Source: http://www.google.com/patents/US7314818?dq=6,243,373
Timestamp: 2014-08-29 22:20:24
Document Index: 496166339

Matched Legal Cases: ['art.\n2', 'Application No. 2002', 'art 24', 'art 24', 'art 24', 'art 24']

Patent US7314818 - Semiconductor device and method of manufacturing the same, circuit board ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA tip of a first wire is bonded to a first electrode. The first wire is drawn from the first electrode to a bump on a second electrode. A part of the first wire is deformed and bonded to the bump. A tip of a second wire formed in the shape of a ball is bonded to the bump by using a tool in a state in...http://www.google.com/patents/US7314818?utm_source=gb-gplus-sharePatent US7314818 - Semiconductor device and method of manufacturing the same, circuit board, and electronic equipmentAdvanced Patent SearchPublication numberUS7314818 B2Publication typeGrantApplication numberUS 11/410,129Publication dateJan 1, 2008Filing dateApr 25, 2006Priority dateFeb 19, 2002Fee statusPaidAlso published asCN1280884C, CN1440064A, US7064425, US20030155660, US20060189117Publication number11410129, 410129, US 7314818 B2, US 7314818B2, US-B2-7314818, US7314818 B2, US7314818B2InventorsTakuya Takahashi, Hiroyuki TomimatsuOriginal AssigneeSeiko Epson CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (14), Referenced by (9), Classifications (76), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and method of manufacturing the same, circuit board, and electronic equipmentUS 7314818 B2Abstract A tip of a first wire is bonded to a first electrode. The first wire is drawn from the first electrode to a bump on a second electrode. A part of the first wire is deformed and bonded to the bump. A tip of a second wire formed in the shape of a ball is bonded to the bump by using a tool in a state in which at least a part of the tip is superposed on the first wire. A part of the first wire which is not deformed by bonding is prevented from being deformed by the tip of the second wire and the tool.
(c) bonding the first wire to the bump with a first part of the first wire deformed; and
(d) bonding a second tip of a second wire formed in a shape of a ball to the bump in a state in which at least a part of the second tip of the second wire is superposed on the first wire without deforming a second part of the first wire that is all of a remaining part of the first wire other than the first part.
2. The method of manufacturing a semiconductor device as defined by claim 1,
the bonding step being performed in a state in which a center of the second tip of the second wire is disposed on a portion of the bump beyond the center of the bump along a drawing direction of the first wire in the step (d).
3. The method of manufacturing a semiconductor device as defined by claim 1,
the bonding step being performed without causing the second tip of the second wire and a tool to come in contact with the second part of the first wire excluding the first part of the first wire that is deformed so that a diameter of the first part of the first wire is decreased to about half or less in the step (d).
4. The method of manufacturing a semiconductor device as defined by claim 1,
the bonding step being performed without causing the second tip of the second wire and a tool to come in contact with the second part of the first wire excluding the first part of the first wire that is deformed so that a diameter of the first part of the first wire is decreased to about a third or less in the step (d).
5. The method of manufacturing a semiconductor device as defined by claim 1, further comprising:
a step of forming another bump on a third electrode,
the second wire being drawn from the second electrode to the bump on the third electrode and bonded to the bump on the third electrode after the step (d).
6. The method of manufacturing a semiconductor device as defined by claim 1, further comprising:
a tool having a hole into which the second wire is inserted, and
the bonding step being performed by using an open end of a tool in the step (d).
the first wire being bonded to a center of the bump or a portion of the bump beyond the center along a drawing direction of the first wire in the step (c).
a part of the bump being deformed in the step (c).
the bump being formed so that a width of the bump is elongated in a drawing direction of the first wire in the step (c).
the bump being formed so that a height of the bump decreases as a distance from the first wire increases in a drawing direction of the first wire in the step (c).
11. The method of manufacturing a semiconductor device as defined by claim 10, further comprising:
the bonding step being performed by using an open end of the tool in the step (d).
12. The method of manufacturing a semiconductor device as defined by claim 1, further comprising, before the step (a):
(g) forming the bump on the second electrode by deforming a portion of the third wire continuously connected to the third tip of the third wire on the third tip, and
13. The method of manufacturing a semiconductor device as defined by claim 12,
the bump being formed to have a bottom end connected with the second electrode and a top end having an almost smooth surface in the step (g).
the top end of the bump being formed so that a width of the top end is elongated in a drawing direction of the first wire connected with the bump toward the bump in the step (g).
15. The method of manufacturing a semiconductor device as defined by claim 13,
the top end of the bump being formed so that a height of the top end decreases as a distance from the first wire increases in a drawing direction of the first wire in the step (g).
16. A semiconductor device manufactured by using a method comprising:
17. A circuit board having a semiconductor device mounted on the circuit board, the semiconductor device being manufactured by using a method comprising:
18. Electronic equipment having a semiconductor device manufactured by using a method comprising:
(d) bonding a second tip of a second wire formed in a shape of a ball to the bump, in a state in which at least a part of the second tip of the second wire is superposed on the first wire with the second tip of the second wire avoiding a center of the bump.
20. A semiconductor device manufactured by using a method comprising:
21. A circuit board having a semiconductor device mounted on the circuit board, the semiconductor device being manufactured by using a method comprising:
22. Electronic equipment having a semiconductor device manufactured by using a method comprising:
This is a Divisional of application Ser. No. 10/347,299, filed Jan. 21, 2003 now U.S. Pat. No. 7,064,425, which claims priority from Japanese Patent Application No. 2002-41680, filed Feb. 19, 2002. The entire disclosures of the prior applications are hereby incorporated by reference in their entirety.
(b) drawing the first wire from the first electrode to a bump of a second electrode;
wherein the bonding step is performed without causing a deformation to a part of the first wire that is not deformed: by bonding by the second tip of the second wire and the tool in the step (d).
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING FIGS. 1A to 1C illustrate a method for forming a bump and a method of manufacturing a semiconductor element having bumps according to a first embodiment of the present invention.;
FIG. 4 is across-sectional view along the line VI-VI shown in FIG. 3;
FIG. 8 is a cross-sectional view along the line VIII-VIII shown in FIG. 7;
(2) In this method of manufacturing a semiconductor device, the bonding step may be performed in a state in which a center of the second tip of the second wire-is disposed on a portion of the bump beyond the center of the bump along a drawing direction of the first wire in the step (d).
This prevents connection failure between the first wire and the bump-more reliably.
(6) In this method of manufacturing a semiconductor device, the tool may have a hole into which the second wire-is inserted, and the bonding step may be performed by using an open end of the tool in the step (d).
(11) In this method of manufacturing a semiconductor device, the tool may have a hole into which the second wire is inserted, and the bonding step may be performed by using an open end of the tool in the step (d)
a first wire having one end electrically connected-with the first electrode, and another end electrically connected with the bump; and
(19) In this semiconductor device, the other end-of the first wire may be bonded to a center of the bump or a portion of the bump beyond the center along a drawing direction of the first wire.
(21) In this semiconductor device, the bump may have a bottom end connected with the second electrode and a top end having an almost smooth surface, and at least the top end of the bump may be formed so that a width of the top end is elongated in a drawing direction of the first wire.
In the example shown in FIG. IC, the part 24 of the wire 20 is drawn from the tip 22 so that the part 24 is bent. This enables the wire 20 to be easily deformed at a portion continuous with the tip 22, on the tip 22. For example, the part 24 of the wire 20 maybe bent by drawing the wire 20 above the electrode 12 by moving the tool 30 in a height direction of the tip 22, and then moving the tool 30 in a width direction of the tip 22. The form (shape, method, for example) of bending the part 24 of the wire 20 is not limited to the above-described example.
In the example shown in FIG. 2A, the tool 30 is moved on the tip 22 in the width direction of the tip 22 (direction indicated by an arrow shown in FIG. 2A) while applying pressure to the tip 22. In other words, the tool 30 is slid in the direction parallel to the surface of the semiconductor element 10 while applying pressure to the tip 22. The bump 40 is formed in an optimum shape in this manner, as shown in FIGS. 3 and 4. FIG. 3 is a plan view of the semiconductor element after formation of the bump. FIG. 4 is a cross-sectional view along the line VI-VI shown in FIG. 3.
This enables another wire 120 to be easily bonded to the top end 42 of the bump 40 in a subsequent step (see FIGS. 7 and 8). In more detail, the distance between the wire 120 and the semiconductor element 10 can be increased by drawing the wire 120 toward the bump 40 so as to descend from the higher side of the bump 40. Therefore, the wire 120 can be prevented from coming in contact with the semiconductor element 10. Moreover, since the wire 120 can be easily prevented from coming in contact with the semiconductor element 10, limitations to design such as the loop shape-and loop height of the wire 120 and the distance between the electrode 12 and the corner (edge) of the semiconductor chip 16 are eliminated, whereby the degree of freedom relating to the design (decrease in height and length of loop of the wire, for example) can be increased.
FIGS. 7 and 8 illustrate the moving direction of the tool 30 (direction of the width of the tip 22). In more detail, FIG. 7 is a plan view of the semiconductor chip after formation of the bump. FIG. 8 is a cross-sectional view along the line VIII-VIII shown in FIG. 7. Each direction indicated by an arrow shown in FIG. 7 indicates a drawing direction of the wire 120 to be connected in a subsequent step toward the bump 40. The wire 120 electrically connects the electrode 12 of the semiconductor chip 16 with another electronic component (interconnect of a substrate or another semiconductor chip, for example).
Any of the subjects (configuration, action, and effect) derived from the features described relating to the above manufacturing method may be selectively applied to the semiconductor device according to the present embodiment. For example, the present embodiment maybe applied to the case where the substrate 50 is replaced with another semiconductor chip.
The tip 222 of the wire 220 and the tool 230 maybe prevented from coming in contact with a part of the wire 120 which is less deformed than a point Y shown in FIG. 18 (on the left side of the point Y) The point Y shown in FIG. 18 is a boundary point at which the diameter (thickness) of the wire 120 is almost halved. This enables the above effects to be achieved more reliably.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4845543Jun 29, 1987Jul 4, 1989Hitachi, Ltd.Semiconductor device and method of manufacturing the sameUS5842628 *Apr 8, 1996Dec 1, 1998Fujitsu LimitedWire bonding method, semiconductor device, capillary for wire bonding and ball bump forming methodUS6215182Mar 20, 2000Apr 10, 2001Fujitsu LimitedSemiconductor device and method for producing the sameUS6559526Apr 26, 2001May 6, 2003Macronix International Co., Ltd.Multiple-step inner lead of leadframeUS6727574Dec 26, 2002Apr 27, 2004Seiko Epson CorporationSemiconductor device and method for manufacturing the same, circuit substrate and electronic apparatusUS6921016Jan 21, 2003Jul 26, 2005Seiko Epson CorporationSemiconductor device and method of manufacturing the same, circuit board, and electronic equipmentUS6946380Jan 21, 2003Sep 20, 2005Seiko Epson CorporationMethod for forming bump, semiconductor element having bumps and method of manufacturing the same, semiconductor device and method of manufacturing the same, circuit board, and electronic equipmentJP2001118877A Title not availableJP2001127246A Title not availableJP2001284388A Title not availableJP2002110898A Title not availableJP2002280410A Title not availableJPH08340018A Title not availableJPH10112471A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7821140Mar 19, 2010Oct 26, 2010Shinkawa Ltd.Semiconductor device and wire bonding methodUS8021825 *Sep 3, 2009Sep 20, 2011Sumitomo Bakelite Co., Ltd.Optical waveguides and methods thereofUS8053166 *Sep 3, 2009Nov 8, 2011Sumitomo Bakelite Co. Ltd.Optical waveguides and methods thereofUS8132709 *Nov 13, 2007Mar 13, 2012Nichia CorporationSemiconductor device and method for manufacturing sameUS8247272 *Jun 22, 2009Aug 21, 2012United Test And Assembly Center Ltd.Copper on organic solderability preservative (OSP) interconnect and enhanced wire bonding processUS8420293Aug 10, 2011Apr 16, 2013Sumitomo Bakelite Co., Ltd.Optical waveguides and methods thereofUS8476726Apr 29, 2010Jul 2, 2013Nichia CorporationSemiconductor device and method of manufacturing the semiconductor deviceUS20080116591 *Nov 13, 2007May 22, 2008Nichia CorporationSemiconductor device and method for manufacturing sameUS20100025849 *Jun 22, 2009Feb 4, 2010United Test And Assembly Center Ltd.Copper on organic solderability preservative (osp) interconnect and enhanced wire bonding process* Cited by examinerClassifications U.S. Classification438/612, 438/666, 257/E23.052, 257/E23.021, 257/E21.518, 257/E21.508, 257/E25.013, 438/617International ClassificationH01L23/485, H01L25/065, H01L21/60, H01L25/18, H01L21/607, H01L21/44, H01L25/07, H01L23/495Cooperative ClassificationH01L2224/16225, H01L2224/48227, H01L2224/92247, H01L24/78, H01L2224/4911, H01L2924/09701, H01L2225/0651, H01L2224/85186, H01L2224/05647, H01L2924/15311, H01L2224/78301, H01L2924/14, H01L2224/48137, H01L2924/01029, H01L2924/01004, H01L2924/01039, H01L2924/01006, H01L24/10, H01L2224/85951, H01L2224/48091, H01L2224/49429, H01L2924/014, H01L2224/48471, H01L2224/85051, H01L2924/01005, H01L2224/32225, H01L2924/0105, H01L24/49, H01L2224/48145, H01L2224/05624, H01L2924/01033, H01L2924/01079, H01L24/45, H01L2924/01013, H01L2224/48624, H01L2224/48479, H01L24/85, H01L24/48, H01L2924/01082, H01L2224/85986, H01L2224/48499, H01L2224/85205, H01L2224/32145, H01L2224/48647, H01L2224/32245, H01L2224/13099, H01L2924/01078, H01L2224/45144, H01L23/49575, H01L2224/48247, H01L2224/73265, H01L2225/06506, H01L25/0657European ClassificationH01L24/49, H01L24/48, H01L24/85, H01L24/10, H01L24/78, H01L23/495L, H01L25/065SLegal EventsDateCodeEventDescriptionJun 1, 2011FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google