Source: http://www.google.com/patents/US7838392?dq=system+for+measuring+web+traffic&ei=Lg8FT__TIIr-sQKzxaGRCg
Timestamp: 2015-01-31 18:53:22
Document Index: 508006045

Matched Legal Cases: ['Application No. 01', 'Application No. 01', 'Application No. 01', 'Application No. 01', 'Application No. 02', 'Application No. 02', 'Application No. 98', 'Application No. 98', 'Application No. 10', 'Application No. 10']

Patent US7838392 - Methods for forming III-V semiconductor device structures - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....http://www.google.com/patents/US7838392?utm_source=gb-gplus-sharePatent US7838392 - Methods for forming III-V semiconductor device structuresAdvanced Patent SearchPublication numberUS7838392 B2Publication typeGrantApplication numberUS 11/943,188Publication dateNov 23, 2010Filing dateNov 20, 2007Priority dateJun 7, 2002Fee statusPaidAlso published asUS6995430, US7259388, US7297612, US7414259, US7420201, US7588994, US8026534, US8586452, US20040005740, US20050189563, US20050199954, US20050205934, US20050212061, US20050218453, US20080128751, US20110073908, US20110318893, US20140051230Publication number11943188, 943188, US 7838392 B2, US 7838392B2, US-B2-7838392, US7838392 B2, US7838392B2InventorsThomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. FitzgeraldOriginal AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (102), Non-Patent Citations (233), Referenced by (5), Classifications (51), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethods for forming III-V semiconductor device structuresUS 7838392 B2Abstract The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
RELATED APPLICATIONS This application is a continuation application of U.S. Ser. No. 11/127,508, filed May 12, 2005, now U.S. Pat. No. 7,297,612, which is a divisional application of U.S. Ser. No. 10/456,103, filed Jun. 6, 2003, now U.S. Pat. No. 6,995,430, which claims the benefit of U.S. Provisional Application 60/386,968 filed Jun. 7, 2002, U.S. Provisional Application 60/404,058 filed Aug. 15, 2002, and U.S. Provisional Application 60/416,000 filed Oct. 4, 2002; the entire disclosures of these two nonprovisional utility patent applications and these three provisional applications are hereby incorporated by reference.
SUMMARY The present invention includes a strained-semiconductor-on-insulator (SSOI) substrate structure and methods for fabricating the substrate structure. MOSFETs fabricated on this substrate will have the benefits of SOI MOSFETs as well as the benefits of strained Si mobility enhancement. By eliminating the SiGe relaxed layer traditionally found beneath the strained Si layer, the use of SSOI technology is simplified. For example, issues such as the diffusion of Ge into the strained Si layer during high temperature processes are avoided.
BRIEF DESCRIPTION OF DRAWINGS FIGS. 1A, 1B, 2A, 2B, and 3-6 are schematic cross-sectional views of substrates illustrating a method for fabricating an SSOI substrate;
DETAILED DESCRIPTION An SSOI structure may be formed by wafer bonding followed by cleaving. FIGS. 1A-2B illustrate formation of a suitable strained layer on a wafer for bonding, as further described below.
Strained layer 18 may have a surface particle density of, e.g., less than about 0.3 particles/cm2. As used herein, �surface particle density� includes not only surface particles but also light-scattering defects, and crystal-originated pits (COPs), and other defects incorporated into strained layer 18. Further, strained layer 18 produced in accordance with the present invention may have a localized light-scattering defect level of less than about 0.3 defects/cm2 for particle defects having a size (diameter) greater than 0.13 microns, a defect level of about 0.2 defects/cm2 for particle defects having a size greater than 0.16 microns, a defect level of about 0.1 defects/cm2 for particle defects having a size greater than 0.2 microns, and a defect level of about 0.03 defects/cm2 for defects having a size greater than 1 micron. Process optimization may enable reduction of the localized light-scattering defect levels to about 0.09 defects/cm2 for particle defects having a size greater than 0.09 microns and to 0.05 defects/cm2 for particle defects having a size greater than 0.12 microns. These surface particles may be incorporated in strained layer 18 during the formation of strained layer 18, or they may result from the propagation of surface defects from an underlying layer, such as relaxed layer 16.
Referring to FIG. 4 as well as to FIG. 3, a split is induced at cleave plane 20 by annealing handle wafer 50 and epitaxial wafer 8 after they are bonded together. This split may be induced by an anneal at 300-700� C., e.g., 550� C., inducing hydrogen exfoliation layer transfer (i.e., along cleave plane 20) and resulting in the formation of two separate wafers 70, 72. One of these wafers (70) has a first portion 80 of relaxed layer 16 (see FIG. 1A) disposed over strained layer 18. Strained layer 18 is in contact with dielectric layer 52 on semiconductor substrate 54. The other of these wafers (72) includes substrate 12, graded layer 14, and a remaining portion 82 of relaxed layer 16. In some embodiments, wafer splitting may be induced by mechanical force in addition to or instead of annealing. If necessary, wafer 70 with strained layer 18 may be annealed further at 600-900� C., e.g., at a temperature greater than 800� C., to strengthen the bond between the strained layer 18 and dielectric layer 52. In some embodiments, this anneal is limited to an upper temperature of about 900� C. to avoid the destruction of a strained Si/relaxed SiGe heterojunction by diffusion. Wafer 72 may be planarized, and used as starting substrate 8 for growth of another strained layer 18. In this manner, wafer 72 may be �recycled� and the process illustrated in FIGS. 1A-5 may be repeated. An alternative �recyling� method may include providing relaxed layer 16 that is several microns thick and repeating the process illustrated in FIGS. 1A-5, starting with the formation of strained layer 18. Because the formation of this thick relaxed layer 16 may lead to bowing of substrate 12, a layer including, e.g., oxide or nitride, may be formed on the backside of substrate 12 to counteract the bowing. Alternatively substrate 12 may be pre-bowed when cut and polished, in anticipation of the bow being removed by the formation of thick relaxed layer 16.
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