Source: http://www.google.com/patents/US8119481
Timestamp: 2017-08-19 19:20:19
Document Index: 146946817

Matched Legal Cases: ['art 2', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093']

Patent US8119481 - High-κ capped blocking dielectric bandgap engineered SONOS and MONOS - Google Patents
A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping...http://www.google.com/patents/US8119481?utm_source=gb-gplus-sharePatent US8119481 - High-κ capped blocking dielectric bandgap engineered SONOS and MONOS
Publication number US8119481 B2
Application number US 12/881,570
Also published as CN101383353A, CN101383353B, EP2031643A2, EP2031643A3, US7816727, US8330210, US20090059676, US20110003452, US20120146126
Publication number 12881570, 881570, US 8119481 B2, US 8119481B2, US-B2-8119481, US8119481 B2, US8119481B2
Inventors Sheng-Chih Lai, Hang-Ting Lue, Chien-Wei Liao
Patent Citations (95), Non-Patent Citations (50), Referenced by (1), Classifications (20), Legal Events (1)
US 8119481 B2
US7419888 * Jul 28, 2006 Sep 2, 2008 Samsung Electronics Co., Ltd. Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same
US7663177 * Oct 12, 2005 Feb 16, 2010 Industrial Technology Research Institute Non-volatile memory device and fabricating method thereof
US20050285184 Jun 9, 2005 Dec 29, 2005 Jung Jin H Flash memory device and method for programming/erasing the same
US20070176227 Jan 30, 2006 Aug 2, 2007 Chun-Li Liu MOS device with nano-crystal gate structure
US20080076224 May 31, 2007 Mar 27, 2008 Samsung Electronics Co., Ltd. Methods of forming flash memory devices including blocking oxide films
US20080093661 Jun 28, 2007 Apr 24, 2008 Hynix Semiconductor Inc. Non-volatile memory device having a charge trapping layer and method for fabricating the same
US20080099830 May 31, 2007 May 1, 2008 Macronix International Co., Ltd. Cylindrical channel charge trapping devices with effectively high coupling ratios
US20080157184 Jan 3, 2007 Jul 3, 2008 Macronix International Co., Ltd. Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure
US20090039414 Aug 27, 2007 Feb 12, 2009 Macronix International Co., Ltd. Charge trapping memory cell with high speed erase
US20090039416 Aug 27, 2007 Feb 12, 2009 Macronix International Co., Ltd. Blocking dielectric engineered charge trapping memory cell with high speed erase
USRE31083 Dec 5, 1980 Nov 16, 1982 International Business Machines Corporation Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure
CN1909250A Jun 14, 2006 Feb 7, 2007 旺宏电子股份有限公司 Non-volatile memory device having a silicon-nitride and silicon oxide top dielectric layer
4 Blomme et al., "Write/Erase Cycling Endurance of Memory Cells with SiO2/HfO2 Tunnel Dielectric," IEEE Trans. on Dev. and Mterials Reliability 4(3), Sep. 2004 345-351.
7 Chang, Sung-Il, et al., "Reliability Characteristics of Tanos (TaN/AIO/SiN/Oxide/Si) NAND Flash Memory with Rounded Corner (RC) Structure," IEEE 2008, 3 pages.
9 Cho, et al., "Simultaneous Hot-Hole Injection at Drain and Source for Efficient Erase and Excellent Endurance in SONOS Flash EEPROM Cells," IEEE Electron Device Letters, vol. 24, No. 4, Apr. 2003, 260-262.
10 DiMaria, D.J., et al., "Conduction Studies in Silicon Nitride: Dark Currents and Photocurrents," IBM J. Res. Dev. May 1977, 227-244.
11 Eitan, et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Lett 21(11) Nov. 2000, 543-545.
12 Govoreanu et al., "An Investigation of the Electron Tunneling Leakage Current Through Ultrathin Oxides/High-k Gate Stacks at Inversion Conditions," IEEE SISPAD Intl. Conf. Sep. 3-5, 2003 287-290.
13 Govoreanu et al., "Simulation of Nanofloating Gate Memory with High-k Stacked Dielectrics," IEEE SISPAD Intl. Conf. Sep. 3-5, 2003 299-302.
14 Govoreanu et al., "Variot: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices," IEEE Electron Dev. Lett. 24(2) Feb. 2003 94-10.
15 Hijiya, S., et al., "High-Speed Write/Erase EAROM Cell with Graded Energy Band-Gap Insulator," Electronics and Communications in Japan, Part 2, vol. 68, No. 2, Jun. 6, 1984, 28-36.
16 Hinkle, C.L., et al., "Enhanced tunneling in stacked gate dielectrics with ultra-thin HfO2 (ZrO2) layers sandwiched between thicker SiO2 layers," Surface Science, Sep. 20, 2004, vol. 566-568, 1185-1189.
17 Ito, et al., "A Novel MNOS Technology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory Applications." 2004 Symp. on VLSI Tech Dig. of Papers 2004, 80-81.
18 Kim et al., "Robust Multi-Bit Programmable Flash Memory Using a Resonant Tunnel Barrier," Electron Dev. Mtg. Dec. 5-7, 2005, IEDM Technical Digest 861-864.
19 Kim, Moon Kyung, et al., "The Effects of ONO thickness on Memory Characteristics in Nano-scale Charge Trapping Devices," Intl Symp on VLIS Technology, Systems and Applications, Apr. 23-25, 2007, pp. 1-2.
21 Lai, Sheng-Chih, et al., "MA BE-SONOS: A Bandgap Engineered SONOS using Metal Gate and AI2O3 Blocking Layer to Overcome Erase Saturation," IEEE Non-Volatile Semiconductor Memory Workshop, Aug. 26-30, 2007, pp. 88-89.
22 Lee, Chang, et al., "A Novel SONOS Structure of SiO2/SiN/AI203 with TaN Metal Gate for Multi-Giga Bit Flash Memories," IEEE 2003 4 pages.
23 Lee, Chungho, et al., "Operational and Reliability Comparison of Discrete-Storage Nonvolatile Memories: Advantages of Single-and Double-Layer Metal Nanocrystals," IEEE IEDM 03-557 22.6.1-22.6.4.
24 Likharev, "Layered Tunnel Barriers for Nonvolatile Memory Devices, "Appl. Phys. Lett. 73(15) Oct. 1998 2137-2139.
25 Lue et al., "A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory," Int'l Symp on VLSI Tech, Apr. 23-25, 2007, 2 pages.
26 Lue et al., "A Novel P-Channel NAND-Type Flash memory 2-bit/cell Operation and High Programming Throughput (>20 MB/sec)," IEEE 2005, 4 pages.
27 Lue et al., "BE-SONOS: A Bangap Engineered SONOS with Excellent Performance and Retention Time," IEDM Tech. Digest Dec. 2005 547-550.
28 Minami, et al., "New Scaling Guidelines for MNOS Nonvolatile Memory Devices," IEEE Trans on Electron Devices 38 (11) Nov 19912519-2526.
29 Padilla, Alvaro, et al., "Dual-Bit SONOS FinFET Non-Volatile Memory Cell and New Method of Charge Detection," Int'l Symp on VLSI Technology, Systems and Applications, Apr. 23-25, 2007, pp. 1-2.
30 Park, Youngwoo, et al., "Highly Manufacturable 32Gb Multi-Level NAND Flash Memory with 0.0098 um2 Cell Size using TANOS (Si-Oxide-AI2O3-TaN) Cell Technology," IEEE IEDM, Dec. 11-13, 2006, 4 pages.
31 Search Report from EP 08252762 mailed Jan. 18, 2010 6 pages.
32 Search Report mailed Feb. 14, 2007 in European Application No. 06000064.3 filed on Jan. 3, 2006, 7 pages.
33 Search Report mailed Feb. 14, 2007 in European Application No. 06000093.2 (Pub. No. EP-01677312) filed on Jan. 3, 2006, 7 pages.
34 Search Report mailed May 9, 2008 in European Application No. 06000064.3 filed on Jan. 3, 2006, 3 pages.
35 Search Report mailed May 9, 2008 in European Application No. 06000093.2 (Pub. No. EP-01677312) filed on Jan. 3, 2006, 4 pages.
36 Search report mailed Nov. 14, 2007 in European Application No. 06000064.3 (Pub. No. EP-01677312) filed on Jan. 3, 2006, 4 pages.
37 Search report mailed Nov. 14, 2007 in European Application No. 06000093.2 (Pub. No. EP-01677312) filed on Jan. 3, 2006, 4 pages.
38 Shih et al., "A Novel 2-bit/cell Nitride Storage Flash Memory with Greater than 1M P/E-cycle Endurance," IEEE IEDM 2004 881-884 (36.3.1-36.3.4).
39 Shin, Yoocheol, et al., "A Novel NAND-Type MONOS Memory Using 63nm Process Technology for Multi-Gigabit Flash EEPROMs," IEEE 2005, 4 pages.
40 Shin, Yoocheol, et al., "High Reliable SONOS-type NAND Flash Memory Cell with AI2O3 for Top Oxide," NVSMW Workshop 2003, 2 pages.
41 Sung et al., "Multi-Layer SONOS with Direct Tunnel Oxide for High Speed and Long Retention Time," IEEE Silicon Nanoelectronics Workshop Jun. 2002 83-84.
42 Takata, M., et al., "New Non-Volatile Memory with Extremely High Density Metal Nano-Dots," IEEE IEDM 03-553, 22.5.1-22.5.4.
43 Tsai et al., "Novel SONOS-Type Nonvolatile Memory Device with Suitable Band Offset in HfAIO Charge-Trapping Layer," Intl'l Tech, Systems and Applications Apr. 23-25, 2007, 2 pages.
44 Walker et al., "3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications," 2003 Symposium on VLSI Tech Digest of Technical Papers, 29-30.
45 Wang, Szu-Yu et al., "Reliability and Processing Effects of Bandgap Engineered SONOS (BE-SONOS) Flash Memory," Physics Symposium, 2007, Proc. 45th Annual IEEE Intl, Apr. 15-19, 2007, 171-176.
46 Wen, Huang-Chun, et al., "Issues associated with p-type band-edge effective work function metal electrodes: Fermi-level pinning and flatband roll-off," Int'l Sympon VLSI Technology, Systems and Applications, Apr. 23-25, 2007, pp. 1-2.
47 White et al., "On the Go with SONOS" IEEE Circuits and Devicces, Jul. 2000, 22-31.
48 Wu, W.-C., et al., "Highly Reliable Multilevel and 2-bit/cell Operation of Wrapped Select Gate (WSG) SONOS Memory," IEEE Electron Device Letters, vol. 28, Issue 3, Mar. 2007, 214-216.
49 Yamada et al., "A self-convergence erasing scheme for a simple stacked gate flash EEPROM," Proc. Int'l. Electron Devices Meeting, Dec. 1991 307-310.
50 Yeh, C.C., et al., "Phines: A Novel Low Power Program/Erase, Small Pitch 2-Bit per Cell Flash Memory," IEDM Tech. Dig. 2002, 931-934.
U.S. Classification 438/258, 257/324, 257/E29.309, 438/288, 257/325, 438/287, 257/E21.423
Cooperative Classification H01L29/4234, H01L27/11568, G11C16/0483, G11C8/10, H01L29/513, H01L21/28282, G11C16/0466
European Classification H01L27/115G4, H01L21/28G, H01L29/423D2B3, H01L29/51B2, G11C8/10