Source: http://www.google.com/patents/US7538772?dq=6031454
Timestamp: 2016-10-23 04:02:51
Document Index: 349079034

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US7538772 - Graphics processing system with enhanced memory controller - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. A memory controller performs a wide range of memory control...http://www.google.com/patents/US7538772?utm_source=gb-gplus-sharePatent US7538772 - Graphics processing system with enhanced memory controllerAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7538772 B1Publication typeGrantApplication numberUS 09/726,220Publication dateMay 26, 2009Filing dateNov 28, 2000Priority dateAug 23, 2000Fee statusPaidAlso published asUS8098255, US20090225094Publication number09726220, 726220, US 7538772 B1, US 7538772B1, US-B1-7538772, US7538772 B1, US7538772B1InventorsFarhad Fouladi, Winnie W. Yeung, Howard ChengOriginal AssigneeNintendo Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (105), Non-Patent Citations (99), Referenced by (33), Classifications (12), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetGraphics processing system with enhanced memory controller
US 7538772 B1Abstract
This application is filed in accordance with 35 U.S.C. � 119(e)(1) and claims the benefit of the provisional application Ser. No. 60/226,894 filed on Aug. 23, 2000, entitled “Graphics Processing System With Enhanced Memory Controller.”
The present invention relates to computer graphics, and more particularly to interactive graphics systems such as home video game platforms. Still more particularly this invention relates to a memory controller for use in such an interactive graphics system that controls resource access to main memory.
This application is particularly related to application Ser. No. 60/226,886, entitled “Method and Apparatus For Accessing Shared Resources”, which is hereby incorporated by reference. This application is also related to the following applications identified below, which focus on various aspects of the graphics processing described herein. Each of the following applications are hereby incorporated herein by reference.
provisional Application No. 60/161,915, filed Oct. 28, 1999 and its corresponding utility application Ser. No. 09/465,754, filed Dec. 17, 1999, both entitled “Vertex Cache For 3D Computer Graphics”, provisional Application No. 60/226,912, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/726,215, filed Nov. 28, 2000, both entitled “Method and Apparatus for Buffering Graphics Data in a Graphics System”, provisional Application No. 60/226,889, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,419, filed Nov. 28, 2000, both entitled “Graphics Pipeline Token Synchronization”, provisional Application No. 60/226,891, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,382, filed Nov. 28, 2000, both entitled “Method And Apparatus For Direct and Indirect Texture Processing In A Graphics System”, provisional Application No. 60/226,888, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,367, filed Nov. 28, 2000, both entitled “Recirculating Shade Tree Blender For A Graphics System”, provisional Application No. 60/226,892, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/726,218, filed Nov. 28, 2000, both entitled “Method And Apparatus For Efficient Generation Of Texture Coordinate Displacements For Implementing Emboss-Style Bump Mapping In A Graphics Rendering System”, provisional Application No. 60/226,893, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,381 filed Nov. 28, 2000, both entitled “Method And Apparatus For Environment-Mapped Bump-Mapping In A Graphics System”, provisional Application No. 60/227,007, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/726,216, filed Nov. 28, 2000, both entitled “Achromatic Lighting in a Graphics System and Method”, provisional Application No. 60/226,900, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/726,226, filed Nov. 28, 2000, both entitled “Method And Apparatus For Anti-Aliasing In A Graphics System”, provisional Application No. 60/226,910, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,380, filed Nov. 28, 2000, both entitled “Graphics System With Embedded Frame Buffer Having Reconfigurable Pixel Formats”, utility application Ser. No. 09/585,329, filed Jun. 2, 2000, entitled “Variable Bit Field Color Encoding”, provisional Application No. 60/226,890, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/726,227, filed Nov. 28, 2000, both entitled “Method And Apparatus For Dynamically Reconfiguring The Order Of Hidden Surface Processing Based On Rendering Mode”, provisional Application No. 60/226,915, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/726,212 filed Nov. 28, 2000, both entitled “Method And Apparatus For Providing Non-Photorealistic Cartoon Outlining Within A Graphics System”, provisional Application No. 60/227,032, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/726,225, filed Nov. 28, 2000, both entitled “Method And Apparatus For Providing Improved Fog Effects In A Graphics System”, provisional Application No. 60/226,885, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,664, filed Nov. 28, 2000, both entitled “Controller Interface For A Graphics System”, provisional Application No. 60/227,033, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/726,221, filed Nov. 28, 2000, both entitled “Method And Apparatus For Texture Tiling In A Graphics System”, provisional Application No. 60/226,899, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,667, filed Nov. 28, 2000, both entitled “Method And Apparatus For Pre-Caching Data In Audio Memory”, provisional Application No. 60/226,913, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,378, filed Nov. 28, 2000, both entitled “Z-Texturing”, provisional Application No. 60/227,031, filed Aug. 23, 2000 entitled “Application Program Interface for a Graphics System”, provisional Application No. 60/227,030, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,663, filed Nov. 28, 2000, both entitled “Graphics System With Copy Out Conversions Between Embedded Frame Buffer And Main Memory”, provisional Application No. 60/226,886, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,665, filed Nov. 28, 2000, both entitled “Method and Apparatus for Accessing Shared Resources”, provisional Application No. 60/226,914, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,390, filed Nov. 28, 2000, both entitled “Low Cost Graphics System With Stitching Hardware Support For Skeletal Animation”, and provisional Application No. 60/227,006, filed Aug. 23, 2000 and its corresponding utility application Ser. No. 09/722,421, filed Nov. 28, 2000, both entitled “Shadow Mapping In A Low Cost Graphics System”. BACKGROUND AND SUMMARY OF THE INVENTION
In controlling memory access between resources seeking to read from and write to main memory, the memory controller minimizes switching between memory reads and memory writes to avoid wasting memory bandwidth due to idle cycles resulting from such switching and thereby enhancing memory access time. The illustrative memory controller minimizes such switching by incorporating a unique write buffering methodology that uses a “global” write queue which queues write requests from various diverse competing resources to reduce read/write switching. In this fashion, multiple competing resources for memory writes are combined into one resource from which write requests are obtained.
Command processor 200 receives display commands from main processor 110 and parses them—obtaining any additional data necessary to process them from shared memory 112 via memory controller 152. The command processor 200 provides a stream of vertex commands to graphics pipeline 180 for 2D and/or 3D processing and rendering. Graphics pipeline 180 generates images based on these commands. The resulting image information may be transferred to main memory 112 for access by display controller/video interface unit 164—which displays the frame buffer output of pipeline 180 on display 56.
In accordance with one exemplary embodiment of the memory controller resource arbitration methodology (and as further described in co-pending application Ser. No. 60/226,886, entitled “Method and Apparatus For Accessing Shared Resources”, which application is hereby incorporated herein by reference), a bandwidth control is uniquely associated with each of the above-identified resources to permit an application programmer to control the bandwidth allocation of, for example, the 3.2 gigabyte's main memory 112 bandwidth. For example, programmable bandwidth control registers are respectively associated with command processor 200 and texture unit 500, which may be utilized to allocate more of the available main memory bandwidth to the command processor 200 than to texture unit 500. In this fashion, sophisticated users are able to tune the above-identified competing interface drivers to their particular application needs to get better overall performance. Accordingly, for each of the above-identified competing interfaces, a register is utilized to control its allocation of memory bandwidth to ensure that for every n number of clock cycles, a request for memory arbitration will be granted. Thus, for each interface, a filter is utilized which will, for example, slow down a request for main memory access if a particular interface is generating a large number of requests at a time when other interfaces are likewise generating requests. Alternatively, if main memory 112 is idle, and no other unit is contending for memory access, then such a request for access may be granted. The filter may define the speed at which requests for a given interface may be granted when other requests from different interfaces are being simultaneously entertained.
3D graphics processor 154 (specifically, command processor 200, texture unit 500 and pixel engine 700), main processor 110 via processor interface 150, audio DSP 156, display controller 164, and peripheral controller 162 for various I/O units (e.g., mass storage access device 106) FIG. 7 illustrates some of the typical operations involved in these “requestors” competing for access to main memory. The arrows in FIG. 7 represent the following operations:
The CPU 110 has two means of writing to main memory: the write-gather buffer and the CPU cache hierarchy. The write-gather buffer is normally used to “blast” graphics commands into memory without affecting the cache. As a result, information sent through the write-gather buffer is not cache coherent. Care must be taken when using the write-gather buffer to avoid writing to areas of memory that maybe found in the CPU cache. The cache flushing instructions shown below maybe used to force data areas out of the CPU cache.
FIG. 8 is a more detailed block diagram of memory controller 152. As shown in FIG. 8, memory controller 152 includes individual “local” interfaces associated with each of the competing resources shown in FIGS. 6A and 6B. A controller pi interface 150I interfaces with processor interface 150, controller DSP interface 156I interfaces with audio DSP 156, controller io interface 802I interfaces with input output interface 802, controller video interface 164I interfaces with video interface 164, controller cp interface 200I interfaces with command processor 200, controller tc interface 500I interfaces with texture unit 500, and interface pe 700I interfaces with pixel engine 700. Memory controller 152 is coupled to main memory via external memory control 829, which is shown in further detail in FIG. 16 described below. External memory control as shown in FIG. 16 generates a read/write control signal which switches the bidirectional memory bus between read and write states.
Turning back to FIG. 8, arbitration control 825 includes the control logic for implementing the arbitration methodology, which is described in further detail below and in the above-identified co-pending application Ser. No. 60/226,886 entitled “Method and Apparatus for Accessing Shared Resources” which has been incorporated herein by reference. Arbitration control 825 is alerted to the presence of, for example, the receipt of a read request in texture interface 500I. Similarly, interfaces 200I, 700I, 150I, 156I, 164I, 802I and 829 are operatively coupled to arbitration control 825 for arbitration of competing memory access requests. As will be explained further below, arbitration control 825 upon receipt of read requests from, for example, memory TC interface 500I and DSP interface 156I (if, for example, 500I and 156I were the only competing resources) may award a first memory cycle to texture unit TC and the next memory cycle to DSP 156, etc. Thus, the read requests may be granted on a round robin basis. Arbitration controller 825 is aware of all pending requests and grants as described in the above-identified co-pending patent application and as set forth further below.
More specifically, as stated above, each of the read “masters” (i.e., a resource seeking to access main memory 112) is associated with a respective corresponding one of read queues RQ1 to RQ6 for queuing read addresses for reading from main memory 112. Each of the write masters seeking to access main memory 112 is associated with a respective corresponding one of write queues WQ1 to WQ4 for queuing write addresses and corresponding data for writing to main memory 112. Arbitration control 825 uses a predetermined arbitration process to allocate main memory access among the read queues RQ1 to RQ6 and to control which write requests among the write queues WQ1 to WQ4 are provided to global write buffer WQ0. The rate at which at least some of the requests are fed into this arbitration process is controllable in accordance with the settings of programmable bandwidth dial registers. By appropriately setting the dial registers for a particular operation, sophisticated users can tune the flow of requests to the arbitration process to improve system performance for that operation.
Thus, bandwidth dial registers influence the memory usage by some of the major memory “hogs”. The read dials control the frequency with which the masters participate in the arbitration process and access memory. The write dials are for control flow and can slow down the writing device by throttling the writes into global write buffer WQ0. As noted, arbitration preferably does not allow the memory to be idle if there are outstanding read requests that not being allowed due to the settings of the bandwidth dials. In this case, a round robin scheme is used among the requesters that are being throttled.
Turning back to FIG. 9, as stated above, each of the read queues RQ1 to RQ6, is resident in an associated interface in FIG. 8. Thus, read RQ1, as suggested by the signal line designation in FIG. 9 is resident in CP interface 200I. Similarly, write queue WQ1 (which in the illustrative embodiment queues eight requests) is resident only in PE interface 7001 and is referred to herein as a “local” write queue buffer. Similarly, WQ2 through WQ4 are resident in the DSP IO and PI interfaces respectively and are local write queue buffers. WQ0 shown in FIG. 9 is the multiple resource or “global” write buffer and is resident in the FIG. 8 component wrbuf 827. The inputs to write buffer 827 shown in FIG. 8 correspond to the inputs to WQ0 shown in FIG. 9.
In the exemplary implementation, there are 4 units that can write to memory: DSP, IO, PE and PI. Any time a device writes to memory, it needs to flush its write buffers explicitly, before signaling another device for reading the data. Each of these 4 interfaces has a 2-wire flush/acknowledge protocol to accomplish this. DSP, IO or PE will issue a flush at the end of a DMA write, before interrupting the CPU 110. This will guarantee that CPU 110 will access the desired data, upon read. CPU 110 also needs to perform an explicit flush when it sets up a buffer in main memory 112 and wants to initiate another device for a read DMA. Before starting the DMA, CPU 110 needs to perform a “sync” instruction. This instruction causes a sync bus cycle, which causes the memory controller 152 to flush the write buffer. Upon completion of the flush, the sync instruction is completed and CPU can start up a read DMA operation.
In the exemplary embodiment, there are dial registers for CP, TC, PE, CPU read and CPU write masters. These dial registers are used to lower the memory bandwidth for the associated master. For example, if the CP dial register contents when added to an associated accumulator is less than one, even if there's a pending CP request, the illustrative arbitration methodology will grant memory access to another master until CP dial register when added to the accumulator equals one or there's no other pending request from any other master. In other words, memory controller 152 never lets memory 112 be in an idle state because of the dial register settings. These dial registers indirectly affect the arbitration scheme by masking the request from that master if the dial register plus accumulator contents does not equal to 1.00. For further details, refer to the methodology described below and in more detail in the copending application Ser. No. 60/226,886 entitled “Method and Apparatus For Accessing Shared Resources”, which has been incorporated herein by reference.
Turning back to the FIG. 8 memory controller block diagram, as set forth above, memory controller 152 includes arbitration control 825 which operates to arbitrate memory access requests between the competing resources identified above. For further details regarding the arbitration control, reference should be made to copending application Ser. No. 60/226,886, entitled “Method and Apparatus For Accessing Shared Resources”, which has been incorporated herein by reference. All reads are single cache-line (32 bytes). It takes 2 cycles of 200 Mhz to read the cache-line. Thus a new read can be performed every 10 nsec. CPU reads will have the highest priority, with round robin arbitration among the rest of the requesters. Memory ownership is changed every 10 nsec among the read requestors and refresh, but the write queue is always written in its entirety. Write queue initiates a request when it gets above a certain level or if a CPU read request address matches an entry in the write-buffer. In accordance with the illustrative embodiment, there are the following restrictions as to the frequency of requests:
FIG. 16A illustrates an example overall emulation process using a host platform 1201, an emulator component 1303, and a game software executable binary image provided on a storage medium 62. Host 1201 may be a general or special purpose digital computing device such as, for example, a personal computer, a video game console, or any other platform with sufficient computing power. Emulator 1303 may be software and/or hardware that runs on host platform 1201, and provides a real-time conversion of commands, data and other information from storage medium 62 into a form that can be processed by host 1201. For example, emulator 1303 fetches “source” binary-image program instructions intended for execution by system 50 from storage medium 62 and converts these program instructions to a target format that can be executed or otherwise processed by host 1201.
FIG. 16B illustrates an emulation host system 1201 suitable for use with emulator 1303. System 1201 includes a processing unit 1203 and a system memory 1205. A system bus 1207 couples various system components including system memory 1205 to processing unit 1203. System bus 1207 may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. System memory 1207 includes read only memory (ROM) 1252 and random access memory (RAM) 1254. A basic input/output system (BIOS) 1256, containing the basic routines that help to transfer information between elements within personal computer system 120I, such as during start-up, is stored in the ROM 1252. System 1201 further includes various drives and associated computer-readable media. A hard disk drive 1209 reads from and writes to a (typically fixed) magnetic hard disk 1211. An additional (possible optional) magnetic disk drive 1213 reads from and writes to a removable “floppy” or other magnetic disk 1215. An optical disk drive 1217 reads from and, in some configurations, writes to a removable optical disk 1219 such as a CD ROM or other optical media. Hard disk drive 1209 and optical disk drive 1217 are connected to system bus 1207 by a hard disk drive interface 1221 and an optical drive interface 1225, respectively. The drives and their associated computer-readable media provide nonvolatile storage of computer-readable instructions, data structures, program modules, game programs and other data for personal computer system 1201. In other configurations, other types of computer-readable media that can store data that is accessible by a computer (e.g., magnetic cassettes, flash memory cards, digital video disks, Bernoulli cartridges, random access memories (RAMs), read only memories (ROMs) and the like) may also be used.
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