Source: http://www.google.com/patents/US4047157?ie=ISO-8859-1&dq=5787449
Timestamp: 2015-05-05 21:27:38
Document Index: 151065578

Matched Legal Cases: ['art 9', 'art 9', 'arts 9', 'arts 9', 'art 9', 'art 9', 'art 9', 'art 9', 'art 11', 'art 11', 'art 11', 'art 11', 'arts 14', 'art 14', 'art 14', 'art 14', 'arts 15', 'arts 15', 'arts 15']

Patent US4047157 - Secondary storage facility for data processing - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA controller for use in a data processing system for coupling a direct access storage element to the system. The controller contains a control path for routing control information from the system to various circuits in the controller and designated storage elements to enable a transfer of data stored...http://www.google.com/patents/US4047157?utm_source=gb-gplus-sharePatent US4047157 - Secondary storage facility for data processingAdvanced Patent SearchPublication numberUS4047157 APublication typeGrantApplication numberUS 05/438,952Publication dateSep 6, 1977Filing dateFeb 1, 1974Priority dateFeb 1, 1974Publication number05438952, 438952, US 4047157 A, US 4047157A, US-A-4047157, US4047157 A, US4047157AInventorsStephen R. JenkinsOriginal AssigneeDigital Equipment CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (30), Classifications (4) External Links: USPTO, USPTO Assignment, EspacenetSecondary storage facility for data processing
US 4047157 AAbstract
A controller for use in a data processing system for coupling a direct access storage element to the system. The controller contains a control path for routing control information from the system to various circuits in the controller and designated storage elements to enable a transfer of data stored on the medium over a data path in the controller. The controller data path also couples the medium to the system and includes a switching network which permits the data to be selectively coupled to or from one of two separate system buses. Control information routed to the controller identifies the system to be involved in a transfer and routing circuits in the controller provide the connection between the controller and designated systems.
1. A controller for a secondary storage facility in a data processing system, said controller being adapted for connection to first and second system buses connected to addressed storage locations and at least one drive including direct access storage means and said controller comprising:A. buffer storage means for data, B. means for transmitting address signals for identifying an addressed storage location connected to a system bus, C. means for transmitting control signals for effecting a system bus data transfer between said controller and the system buses D. means for transferring data between a drive and said buffer storage means, E. register means for assuming at least two states, F. first routing means connected to said address signal transmitting means, said control signal transmitting means and said buffer storage means for transferring address signals to and control signals and data to and from the first system bus in response to a first state of said register means, and G. second routing means connected to said address signal transmitting means, said control signal transmitting means and said buffer storage means for transferring address signals to and control signals and data to or from the second system bus in response to a second state of said register means. 2. A controller as recited in claim 1 including means for receiving control information and means responsive to the receipt of control information for establishing a state of said register means for an ensuing data transfer.
3. A controller as recited in claim 1 wherein said control signal transmitting means includesi. monitoring means for indicating whether said buffer storage means is conditioned for a data transfer to or from a selected system bus, ii. means for transmitting an interruption request signal to initiate a data transfer operation over a selected system bus, iii. means for transmitting a data strobing signal during each system bus data transfer operation in response to a control signal from the selected system bus, iv. means for terminating the interruption request signal in response to a signal from said data strobing signal transmitting means, and v. means responsive during a first data strobing signal after an interruption request signal for being activated to disable said terminating means when said monitoring means indicates said buffer storage means is conditioned for a system bus data transfer. 4. A controller as recited in claim 3 wherein said control signal transmitting means includes monitoring means responsive to error conditions during a data transfer to or from the selected system bus or a drive and error means responsive to said monitoring means for transmitting an error signal, said disabling means being deactivated in response to the error signal to cause the interruption request signal and further data transfers to be terminated.
5. A controller as recited in claim 3 additionally includingi. counter means for producing a count signal after a succession of system bus data transfers, said disabling means being deactivated in response to the count signal, and ii. means for resetting said counter means to a reference value each time said termination means terminates an interruption request signal. 6. A controller as recited in claim 5 additionally comprisingi. means for disabling said counter means to thereby enable a succession of system bus data transfers, and ii. means for indicating the completion of the system bus data transfers for deactivating said disabling means to thereby terminate transfers over the selected bus. 7. A controller as recited in claim 3 additionally including counter means responsive to a second data strobing signal in succession after an interruption request signal is transmitted for deactivating said disabling means to thereby enable each interruption request signal to effect a two data transfer.
8. A controller for a secondary storage facility in a data processing system, said controller being adapted for connection to a system bus and to at least one drive including direct access storage means and said controller comprising:A. buffer storage means for data, B. means for transferring data between the drive and said buffer storage means, and C. means for transferring data between said buffer storage means and the system bus including:i. monitoring means for indicating whether said buffer storage means is conditioned for a data transfer to or from the system bus, ii. means for transmitting an interruption request signal to initiate a data transfer operation over the system bus, iii. means for transmitting a data strobing signal during each system bus data transfer operation in response to a system bus control signal, iv. means for terminating the interruption request signal in response to a signal from said data strobing means, and v. disabling means responsive during a first data strobing signal after an interruption request signal is transmitted for being activated to disable said terminating means when said monitoring means indicates said buffer storage means is conditioned for a data transfer. 9. A controller as recited in claim 8 wherein said data transferring means additionally includes means for monitoring error conditions during a data transfer to or from the system bus or a drive and error means responsive to said monitoring means for transmitting an error signal, said disabling means being deactivated in response to the error signal to cause the interruption request signal and further system bus data transfers to be terminated.
10. A controller as recited in claim 8 additionally includingi. counter means for producing a count signal after a succession of system bus data transfers, said disabling means being deactivated in response to the count signal, and ii. means for resetting said counter means to a reference value each time said termination means terminates an interruption request signal. 11. A controller as recited in claim 8 additionally including counter means responsive to a second data strobing signal in succession after an interruption request signal is transmitted for deactivating said disabling means, said data transferring means thereby being enabled to effect two data transfers in response to each interruption request signal.
12. A data processing system comprising:A. first and second system buses for transferring address, control and data signals, B. addressed storage locations connected to each of said first and second system buses, C. a plurality of direct access storage units for storing data, and D. a controller coupling selectively said first and second buses and at least one said direct access storage units for controlling data transfers between said addressed storage locations connected to a selected one of said buses and one of said direct access storage units, said controller including:i. buffer storage means for data, ii. means for transmitting address signals for identifying an addressed storage location on a system bus, iii. means for transmitting control signals for effecting a system bus data transfer between said controller and system bus, iv. means for transferring data between one of said direct access storage units and said buffer storage means, and v. register means for assuming at least two states, vi. first routing means connected to said address signal transmitting means, said control signal transmitting means and said buffer storage means for transferring address signals to and control signals and data to and from the first system bus in response to a first state of said register means, and vii. second routing means connected to said address signal transmitting means, said control signal transmitting means and said buffer storage means for transferring address signals to and control signals and data to or from the second system bus in response to a second state of said register means. 13. A system as recited in claim 12 including means in said system for transmitting control information to said controller and means in said controller responsive to the receipt of control information for establishing a state of said register means for an ensuing data transfer.
14. A system as recited in claim 12 wherein said control signal transmitting means includesa. monitoring means for indicating whether said buffer storage means is conditioned for a data transfer to or from a selected system bus, b. means for transmitting an interruption request signal to initiate a data transfer operation over a selected system bus, c. means for transmitting a data strobing signal during each system bus data transfer operation in response to a control signal from the selected system bus, d. means for terminating the interruption request signal in response to a signal from said data strobing signal transmitting means, and e. means responsive during a first data strobing signal after an interruption request signal for being activated to disable said terminating means when said monitoring means indicates said buffer storage means is conditioned for a data transfer. 15. A system as recited in claim 14 wherein said control signal transmitting means includes means for monitoring error conditions during a data transfer to or from a system bus or one of said storage units and means responsive to said monitoring means for transmitting an error signal, said disabling means being deactivated in response to the error signal to cause the interruption request signal and further data transfers to be terminated.
16. A system as recited in claim 14 additionally includinga. counter means in said controller for producing a count signal after a succession of system bus data transfers, said disabling means being deactivated in response to the count signal, and b. means in said controller for resetting said counter means to a reference value each time said termination means terminates an interruption request signal. 17. A system as recited in claim 16 additionally comprisinga. means responsive to one state of said register means for disabling said counter means to thereby enable a succession of system bus data transfers, and b. means for indicating the completion of the data transfers for deactivating said disabling means to thereby terminate transfers over the selected bus. 18. A system as recited in claim 14 additionally including counter means in said controller responsive to a second data strobing signal in succession after an interruption request signal is transmitted for deactivating said disabling means to thereby enable each interruption request signal to effect a two data transfer.
19. A data processing system comprisingA. a system bus for transferring address, control and data signals, B. addressed storage locations connected to said system bus, C. a plurality of direct access storage units for storing data, and D. a controller for coupling said system bus and at least one of said direct access storage units for controlling data transfers between said addressed storage locations and one of said direct access storage units, said controller including:i. buffer storage means for data, ii. means for transferring data between one of said memory units and said buffer storage means, and iii. means for transferring data between said buffer storage means and said system bus including:a. monitoring means for indicating whether said buffer storage means is conditioned for a data transfer to or from said system bus, b. means for transmitting an interruption request signal to initiate a data transfer operation over said system bus, c. means for transmitting a data strobing signal during each data transfer operation in response to a system bus control signal, d. means for terminating the interruption request signal in response to a signal from said data strobing means, and e. disabling means responsive during a first data strobing signal after an interruption request signal is transmitted for being activated to disable said terminating means when said monitoring means indicates said buffer storage means is conditioned for a data transfer. 20. A system as recited in claim 19 wherein said data transferring means additionally includes means for monitoring error conditions during a data transfer to or from said system bus or said storage unit and error means for transmitting an error signal, said disabling means being deactivated in response to the error signal to cause the interruption request signal and further data transfers to be terminated.
21. A system as recited in claim 19 additionally includingi. counter means in said controller for producing a count signal after a succession of system bus data transfers, said disabling means being deactivated in response to the count signal, and ii. means in said controller for resetting said counter means to a reference value each time said termination means terminates an interruption request signal. 22. A controller as recited in claim 19 additionally including counter means in said controller responsive to a second data strobing signal in succession after an interruption request signal is transmitted for deactiving said disabling means, said data transferring means thereby being enabled to effect two system bus data transfers in response to each interruption request signal.
Secondary storage facilities comprise elements which are not an integral part of a central processing unit and its random access memory element, but which are directly connected to and controlled by the central processing unit or other elements in the system. These facilities are also known as "mass storage" elements and include magnetic tape memory units, disk units and drum units, for example.
These facilities are also termed "sequential access storage units" because the information stored in one of these unit becomes available, or is stored, only in a "one-after-the-other" sequence, whether or not all the information or only some of it is desired. For example, it is usual practice to retrieve information from a disk unit on a "sector-by-sector" basis, even though only one of several information records in a sector is needed. Similarly, a physical record on a tape is analagous to a sector on a disk and a complete physical record may be retrieved even though it may contain more than one relevant information record.
These devices also are known as "serial storage devices". In a serial storage device, time and sequential position are factors used to locate any given bit, character, word or groups of words appearing one after the other in time sequence. The individual bits appear or are read serially in time.
Prior controllers usually have only one connection to the input/output, memory or equivalent bus in a data processing system. However, random access memories now have connections or "ports" for two independently operating buses. With these "dual-port" memory units, greater operating efficiency is possible. For example, one "port" might be connected to a first bus to which a central processing unit and one or more input/output units connect. The second port might then connect to a second bus in turn connected to a seconday storage facility and other input/output units. With such a configuration, a transfer could occur between the memory and secondary storage port while another transfer was being made simultaneously between the central processing unit and another unit connected to the first bus.
From another viewpoint, secondary storage facilities can transfer large blocks of data to or from memory units in short periods of time. Normally they transfer data only over an input/output bus which handles all transfers to or from input/output devices including secondary storage facilities. Data transfers to or from secondary storage facilities over such a bus can still require such a large portion of the total time available on the bus that the overall efficiency of the system may be reduced because these transfers may prevent others from being made. Alternatively, the system can be arranged to devote a greater proportion of time to central processing unit transfers, but only by sacrificing the transfer rate to or from the secondary storage facility. Thus, as usage of such a system increases, it can become inefficient even though there is a second bus which might be used to handle transfers between the secondary storage facility and the random access memory unit.
Therefore, it is an object of this invention to provide a secondary storage facility which is capable of increased operating efficiency.
Another object of this invention is to provide an improved facility which can transfer data over each of two independent buses in a data processing system.
In accordance with this invention, a controller in a secondary storage facility can transfer data from a recording medium over either of two independent buses in a data processing system. The controller accepts control information over a first bus including a bus selection signal which designates which bus will be used to transfer data. The data passes through a data path in the controller. A switching network in the controller responds to the bus selection signal and routes the necessary address and control signals onto the selected bus and couples the selected bus and data path.
Commands and other information pass over the first bus. While data may also be transferred over the first bus, normally it will be routed over the second bus to or from some other system units, such as a dual-port memory, another data processing system, or an input-output device. Thus, the first bus is only involved in transferring the command information and can be used for transfers simultaneously with a transfer over the second bus involving the secondary storage facility.
FIG. 4 depicts the interconnection between a drive and controller in accordance with this invention;
FIG. 5 is a block diagram of a synchronous data path in a controller as adapted for connection to a system as shown in FIGS. 2 or 3;
FIG. 6 is a block diagram of an asynchronous drive control path in a controller as adapted for connection to a system as shown in FIG. 2 or 3;
FIG. 7 is a block diagram of a device constructed in accordance with this invention;
FIG. 18 is a flow chart of the operation of a controller and drive to store data in the drive;
FIG. 20 comprise FIGS. 20A, 20B, 20C and 20D which together constitute a detailed logic diagram of exemblary control circuitry for storing data in accordance with the invention.
It will become apparent from the following discussion that the disclosed facilities are adapted for all these configurations. The user of a system will determine his own specific configuration. It also will become apparent that if drive 14 is one type of magnetic disk memory unit, drive 15 can be another unit of the same type, a magnetic disk memory unit of another type, or even a magnetic tape or magnetic drum unit or other type of sequential access memory. Moreover, drives 17, 20 and 21 could be directly connected to controller 13 without any modification to either the controller 13 or any of the drives.
This interchangeability and resultant flexibility result because each of the device buses 22, 23, 24 and 25 contains a standard set of corresponding conductors for transferring signals, notwithstanding the drive connected to the device bus or the data processing system which is involved. As new drives are developed with improved storage media such as tapes and disks with higher recording density or even of new media, it will only be necessary to have the drive itself conform to the standard set of signals, no new controller development will be necessary.
New drives will also be independent of the type of data processing systems to which they connect. FIGS. 2 and 3 depict diverse types of data processing systems. The nature of the data processing system has no effect on the drive itself. Although these two data processing systems form no part of the invention, the fact that they are diverse types of systems emphasizes the flexibility of the disclosed secondary storage facilities. Also, specific examples of data processing systems will facilitate an understanding of the detailed discussion of this invention.
The central processing unit 31 can also control the transfer of data between the memory section and a secondary storage facility. In FIG. 2 this storage facility comprises drives 42, 43 and 44 connected to a controller 45 by a device bus 46 in a daisy-chain configuration. The controller 45 receives control information over the input-output bus 36 to be processed by an asynchronous drive control path within the controller 45. A synchronous data path in the controller may transfer data to the memory bus 30 or, as shown, to a second memory bus 47. Thus, transfers between the secondary storage facility and the memory section occur only with minimum use of the input-output bus 36 and the central processing unit 31 because data can be transferred directly through the controller 45 to the memory section. As also shown in FIG. 2 a second central processing unit 50 connects through an input-output bus 51 to other input-output devices 52. The central processing unit 50 also connects to the memory section through a bus 53, which enables the unit 50 to use the memory units 32, 33 and 34 in common with the processing unit 31 including data supplied to the memory section by the secondary storage facility.
As previously stated, this is an example of a data processing system which has separate input-output and memory buses. In operation, the central processing unit 31 might require some program stored in the drive 42. A second program already stored in the memory section would contain the necessary instructions to transfer a command to the controller 45 over the bus 36 to identify a particular drive, such as the drive 42, the starting location in the drive (e.g., the track and sector numbers in a disk memory unit) and other necessary information, as known in the art. Once the controller 45 receives that information, it retrieves data from the drive 42 and then transfers it to the memory bus 47 directly for storage and subsequent use by the central processing unit 31 or even the central processing unit 50. The controller 45 might also write data onto the bus 36 or even another memory bus under program control. Analogous transfers occur in a system using a common bus to interconnect the system elements. Such a system is shown in FIG. 3 and comprises a central processing unit (CPU) 60 and a first common bus 61. The bus 61 contains address, data and control conductors. It connects the central processing unit 60 in parallel with input-output devices 62 and controllers 63 and 64 associated with two secondary storage facilities.
In accordance with this invention, the controller 63 has an additional connection for another bus 72 which is identical to the bus 61. The bus 72 is coupled to a second part of the main memory 65, which is a "dual-port" memory. This bus 72 also connects to a fast memory 73, which is coupled to the central processing unit 60 through dedicated bus 74.
As the drives are connected only to device buses and all device buses are the same, the drive circuits are independent of any particular system. Of course, different data processing systems have different word sizes which can range from eight bits to thirty-six bits or more. Circuit modifications in the controllers or the drives can be made to accomodate these different word sizes. At this point it is sufficient to consider the use of a basic eighteen-bit word. No modification is necessary for a central processing unit using eighteen-bit words. To provide a thirty-six bit word for other data processing systems the controller merely needs to concatenate pairs of eighteen-bit words. Other arrangements can be used when the data processing system word length is not an exact multiple of a drive word length.
To understand the interaction between a controller and device it is helpful to discuss first the specific signals which appear on the device bus and the functions each performs. A device bus, with its signal designations, is shown in FIG. 4; and the same mnemonic identifies a wire or group of wires and the signals they carry. Every device bus has the same constructions. A drive control section 80 contains conductors segregated into a data set 81, an address set 82 and a control set 83. Within the data set 81 there are bidirectional control data (CD) wires 84 for carrying control and status information between a controller and any of its respective drives. A bidirectional CPA wire 85 carries a parity bit. The control information includes commands which control the operation of the drive. Some of the commands initiate data transfers and include READ, WRITE and WRITE CHECK commands. Other commands initiate control operations such as positioning heads in a movable head disk drive, winding a tape in a magnetic tape drive or clearing registers in a drive.
A RUN signal controls the initiation of a data transfer and the overall duration of the transfer; it appears on a RUN wire 107. The controller asserts the RUN signal to start a data transfer in accordance with a command which was previously transferred to the drive over the device bus control section 80. Subsequently, circuits in the drive use the RUN signal to determine the time for terminating the transfer. An EBL signal transmitted by the drive on a wire 110 signals the end of a block. Any transfer terminates if, at the end of an EBL signal, the RUN signal is not asserted. Otherwise, the transfer operation continues through the next block. In this connection the term block has a conventional meaning as applied to magnetic tape memory units and is equivalent to a sector as that term is conventionally applied to magnetic disk memory units. Thus, as used in this description, block is used in a generic sense to indicate a conveniently sized group of data bits to be sent as a unit.
A wire 111 in the synchronous data section 100 is a bidirectional wire for carrying exception (EXC) signals. When the drive transmits the EXC signal, some error has occurred during the transmission. This signal remains asserted until the last EBL signal during the transfer terminates. An EXC signal from a controller, on the other hand, causes the drive to terminate any action it was performing in response to a command.
With this understanding of the signals which appear on a device bus, it is possible to discuss generally the circuits in a controller. Looking first at the synchronous data path in FIG. 5, it will be apparent that only one drive connected to a controller may respond to a READ, WRITE or WRITE-CHECK command at any given time because the data section 100 (FIG. 4) is connected to a all the drives a controller supervises. Data passes from a drive, over a device bus 121 with the construction shown in FIG. 1, through the synchronous data path of FIG. 5 and, in accordance with this invention, to SYSTEM BUS A 120 or to SYSTEM BUS B 400. A reverse operation involving the same route occurs when data passes to a drive. SYSTEM BUS A 120 could correspond to the intpu-output bus 36 in FIG. 2 and SYSTEM BUS B 400, to the memory bus 30 in one arrangement. In FIG. 3, SYSTEM BUS A would correspond to bus 61, SYSTEM BUS B, to bus 72. If one of the two buses also connects to the control path shown in FIG. 6, such as the bus 61 in FIG. 3, that bus is, for purposes of a data transfer, SYSTEM BUS A 120. In the following discussion only, buses 120 and 400 are discussed. Further, reference numerals used to designate wires in FIG. 4 are applied to corresponding wires in the other FIGURES.
Incoming data from either SYSTEM BUS A 120 or SYSTEM BUS B 140 in response to a WRITE command or the data section 101 of a device bus 121 in response to a READ or WRITE-CHECK command is loaded into an input buffer 122 for transfer into a storage facility 123. When the facility 123 is filled, the first word in is loaded into an output buffer 124. A data path control circuit, generally 126, then either routes the data onto the device bus 121 for transfer to the device or onto one of the system buses 120 or 400 for transfer to a designated location in the data processing system. A transfer control circuit 401 selects a bus as described later. The controller also contains the necessary circuits for generating the appropriate address signals to identify a memory location which either stores the data to be transferred to the controller or which is to receive the data from the drive.
A typical drive control path is shown in FIGS. 6 and 7. The controller shown in FIG. 6 contains several registers, which are called local registers. They include:
4. A bus address register 137 for storing the address of a location connected to one of the system buses 120 or 400, which is either sending or receiving the data.
1. A control register 140 analogous to the control and status register 133 (FIG. 6); it stores commands and other control information; the control register 140 and the control and status register 133 can be considered as a single register in which stages are distributed among the controller and each drive connected to the controller;
All operations of controller and drives in a secondary storage facility constructed in accordance with this description are under the control of information stored in these registers in the controller (FIG. 6) and the drive (FIG. 7). For example, a transfer of data between the recording medium and a memory unit requires the central processing unit to transfer several items of information into the local and remote registers. The identification of the drive to be involved in the transfer is loaded into the control and status register 134 (FIG. 6), while the control and status register 133 receives information including which system bus is to be connected to the controller. The register 134, in turn, produces corresponding unit select signals. The bus address register 137 receives the initial memory address while the word counter register 136 receives a number (usually in two's complement) defining the number of data words in the block to be transferred.
Any time there is to be a transfer into or out of a local or remote register, address signals and transfer control signals appear on the system bus 120 shown in FIG. 6 including one set of direction control signals which indicate whether the transfer involves a reading or writing operation. For example, the transfer control signals discussed in U.S. Pat. 3,710,324 include CO and Cl direction control signals. CONI and CONO signals discussed in U.S. Pat. 3,376,554 perform the same function. When the information is to move into a register, the information may appear on the system bus data lines simultaneously with or slightly after address and transfer control signals appear on the address and transfer control lines, depending upon the characteristics of the particular system.
Receivers in receiver/driver 150 in a controller (FIG. 6) comprise buffer circuits and pass the address signals and direction control signals to an address circuit 151. Each register has a unique address which the address signals designate and the address circuit 151 uses the address signals to indicate whether the address is for a register in the controller or in an associated drive. Thus, these signals implicitly indicate whether the designated register is a local or remote register and the address circuit 151 produces a corresponding LOCAL or REMOTE signal. Register selection signals (RS') from the circuit 151 pass to a register selection decoder 152 and to a device bus control circuit 160.
The drive control path shown in FIG. 6 also contains multiplexers 170 and 172. Multiplexer 170 selectively couples signals onto the BUSI bus either from the output buffer 124 or from the drive coupled from the device bus through receivers 171 in response to OBout or CDout signals from the decoder 152. CS1out and CS2out signals from the decoder 152 control the multiplexer 172 so it selects the couples the output of either the register 133 or the register 134 onto the BUSI bus.
The steps for loading information into a local register are similar. The direction control signals from the address circuit 151 indicate a writing operation. Thus, an input conductor for a selected register, rather than a multiplexer, is energized by the decoder 152. When new information is to be stored in the word couter register 136, the decoder 152 produces the WCin signal. The information to be stored appears on the bus 154 which is equivalent to the control data wires 84 in FIG. 4. The coincidence of the REG STR and WCin signals loads the word counter, register 136.
The appearance of a valid address, with its concomitant VALID signal, and the transfer synchronizing signal from the system bus 120 produces the DEV SEL and the REG STR signals as previously discussed. The DEV SEL enables the output to the device bus drivers 161 to couple the RS', UNIT SELECT, and direction control signals onto wires in the control set 83 of the device bus 121 as RS, DS and CTOD signals respectively. In addition, the REG STR signal causes the control 160 to produce a DEMAND signal which passes through the enabled output drivers 161 as the DEM signal.
Now referring to FIG. 7, a drive selection decoder 175 in each drive compares the incoming DS signals with signals from drive selection switches 176 to determine whether the DS signals idensity that particular drive. If they do, the decoder 175 produces an enabling signal on a conductor 177 to activate a register selection decoder 180 and a control section timing unit 181. The register selection decoder 180 receives the RS signals and in response produces signals which are coupled to the selected register in the drive, e.g., registers 140, 141, 142, 144, 145, 146, 147 or 148. These selection signals enable subsequent timing signals from the timing unit 181 to effect a transfer. The timing unit 181 also receives the DEM and CTOD signals from the bus 121 and transfers a TRA signal onto the bus indicating that the drive has moved control information onto the data set 81 or that the data on the data set 81 has been stored.
Referring again to FIG. 6, the device bus control 160 receives the TRA signal and then either enables data to pass through the receivers 171 in response to the CDout signal from the register selection decoder 152 or enables the drivers 182 if the decoder has produced the CDin signal. In addition, the control 160 can produce the previously discussed optional synchronizing signal for controlling the transfer between the system and the controller. Thus, the decoder 152 produces a CDin or CDout signal during each remote register transfer.
A more thorough understanding of these remote register transfers will be obtained from a discussion of reading and writing operations in some detail in terms of the signals transfers between the controller in FIG. 6 and the registers in FIG. 7.
Now referring to FIGS. 6, 7, 8 and 9, the signals on DS, RS and CTOD wires from the controller arrive at the drive at time t3 (Chart 9F), the interval from t1 to t3 representing a bus signal propagation delay. After a similar delay from time t2, the DEM signal is received at the drive at time t4 (Chart 9H) causing the control section timing unit 181 to load (or strobe) the CTOD signal as represented by step 203. The drive selection decoder 175 will have already determined whether the drive is the selected drive. If the DS signals do not designate the drive (step 204), the drive in step 205 determines whether the RS bits designate the attention summary register. If a register other than the attention summary system is designated, but the DS bits do not select a drive, no further steps occur in that drive. If the attention summary register is addressed, then the ATA signal is sent (step 206) as described later.
When the controller receives the control information and the TRA signal as shown in Charts 9C and 9E at t6, the device bus control 160 may immediately disable the DS, RS and CTOD signals (Charts 9A and 9B and step 210). After a short delay, the device bus control 160 opens the receivers 171 at time t7 to load the control information and parity signal from the device bus 121 through the multiplexer 170 and drives 166 onto the system bus 120 (step 211). When the system receives the control information, the control 160 terminates the DEM signal (Chart 9D and step 214) so that the drive senses the transition of the DEM signal (Chart 9H) and terminates the TRA signal (Chart 9I and step 215) and the control data and parity signal. Once the controller senses the termination of the TRA signal at time t10 (Chart 9E), the transfer is complete (step 216).
If a TRA signal from a previous transfer with any drive connected to the controller is still asserted, the controller waits for it to terminate as shown in step 227 and discussed with respect to the reading operation. Then at time t2 the controller, in step 228, transmits the DEM signal onto the device bus 121 as shown in Chart 11D. Steps 230, 231, 232 and 233 are analagous to steps 203, 204, 205 and 206 in FIG. 8. The control information on the data set 81 arrives at the drive at time t3 (Chart 11F) and the DEM signal arrives at time t4 (Chart 11G). In response to these signals, the control section timing unit 181 in the drive (FIG. 7), in step 234 and at t5 in Chart 11H, loads the control information into the designated register and the CPA signal into the parity circuit 183. In steps 240 and 241, the circuit 183 provides a parity error signal if an error exists to set a PAR bit position in the error register 142.
Local registers in the controller and remote registers in the drives store control and status information. Some registers, such as the work counter register 136, contain one item of information, such as the word count, so all bit positions or stages are interrelated. Other registers store diverse information in one or more groups of registers. For example, the control and status register 133 has a stage for indicating special conditions and another stage for indicating that a transfer related error has occurred. Registers in which all stages are interrelated may be arranged so either data can only be retrieved from them by the system (i.e., read-only register) or data can be retrieved or altered in them by the system (i.e., read/write register). Registers in the former category are denoted by a cross to the right of the designation in FIGS. 12 and 13. In registers which contain independent stages, each stage may be arranged so its data either may only be retrieved (i.e., a read only stage) or may be retrieved or altered (i.e., a read/write stage). A cross above a stage indicates that it is a read-only stage.
1. Control and Status Register 133
The control and status register 133 is a multi-stage or multiple bit position register. Some stages are located in the controller; others are located in each drive in what is designated the control and status register 140. The controller stages are shown in FIG. 12. One such stage is an SC stage which is set to indicate that (1) a transfer related error has occurred (i.e., a TRE bit position is set), (2) that an MCPE bit position has been set because a parity error was detected during a remote register reading operation as previously discussed, or (3) that some drive connected to the controller has produced an ATTN signal on the wire 94 in the control set 83 (FIG. 4). The controller resets the SC bit position in response to a system resetting (INIT) signal on the system bus 120 in FIG. 6, to a controller clearing signal which sets a CLR bit position in a control and status register 134 or in response to the correction of the condition causing the drive to assert the ATTN signal. This stage is located in the controller itself.
A PSEL bit position is used to control the switching of the synchronous data path between the two system buses 120 and 400. When the PSEL stage is cleared, the selected system bus is normally the bus which connects to the control data path and data passes through receivers/drivers 295. When this stage is set, data is routed to SYSTEM BUS B 400 through receivers/drivers 402. An INIT or CLR signal or a local register writing operation will clear the stage to thereby restore the connection between the system bus which connects to the control data path, usually SYSTEM BUS A 120.
Several FUNCTION signals designate a specific operation the drive is to perform. They are received by the controller, although the corresponding register stages are located in the control and status register 140 in each drive. These signals define various functions which may involve a data transfer. The register stages are cleared by an INIT or CLR signal. A DRIVE CLEAR operation defined by the FUNCTION bits causes the stages to be cleared. Typical FUNCTION signals also produce the previously discussed READ, WRITE and WRITE-CHECK operations or a SEARCH operation to locate a particular area in the drive without a data transfer taking place.
2. Control and Status Register 134
All stages in the control and status register 134 are located in the controller. Individual register stages reflect the operation and status of the controller, especially error conditions which might exist. A DLT bit position is one example of such a stage which is set when the controller is not able to supply or accept in a timely fashion a data word over the synchronous data path during a writing or reading operation, respectively. In a two-port operation when the PSEL stage in the system 133 is set, an INIT signal at the second system bus also sets the DLT stage if a transfer is then occuring over that second bus. Any time the DLT stage sets, the TRE stage in the register 133 is set.
A UPE bit position is set during a data transfer in response to a WRITE or WRITE-CHECK command over the synchronous data path when a parity error is detected on one of the system buses 120 or 400. The TRE stage also sets in response to such a parity error.
OR and IR bit positions in the register 134 are used in diagnostic operations and are set when the output buffer register 124 is full or the input buffer register 122, respectively, in the synchronous data path is empty.
The UO2 through UO0 bit positions receive their information during a local system writing operation. These stages are cleared in response to a system resetting signal or to a CLR signal. Once a transfer starts, they can be altered without interfering with the transfer.
3. Word Counter Register 136
4. Bus Address Register 137
A data register (not shown) can be addressed, primarily for diagnostic purposes. There may be no physical register. Specifically, if the data register is addressed during a local register writing operation and the IR signal indicates that the storage facility 123 is not full, the information on the system bus 120 is loaded into the input buffer 122 (FIG. 6). This condition is represented by an OBin signal. On the other hand, an OBout signal is produced when the data register is addressed during a local register reading operation and OR signal indicates that data is present. The OBout signal causes the information in the output buffer 124 to be loaded onto the system bus 120.
6. Status and Control Register 140
Now referring to FIG. 13, which contains in diagrammatic form, the organization of typical registers in a drive, the control register 140 stores the FUNCTION and GO bits previously described with respect to the control and status register 133. Whenever the register 133 is loaded, the controller produces a remote writing operation to load FUNCTION and GO bits into corresponding stages in the designated A DVA stage is set whenever the drive is available for operation and is a read-only position.
7. Status Register 141
Still referring to the register 141, MOL and DRY stages are set when the drive is in an operating condition; that is, the MOL stage is set when the drive power is on and, in the case of a continuous moving medium such as a disk or drum, the medium is up to speed. The DRY stage is set to indicate that the drive can accept a command while the drive is not responding to a prior command; the DRY bit position is cleared in response to a data transfer command with the GO bit position set. Any change of state of the MOL stage also causes the ATA stage in the drive to be set.
8. Error Register 142
9. Maintenance Register 144
The maintenance register 144 is used for various diagnostic operations to facilitate analyses of facility operation. It may contain, for example, a WRCLK bit position or stage to aid in simulating drive clocking pulse, an SP bit position to aid in simulating a sector or block pulse and other similar bit positions. Usually the maintenance register also contains a DMD bit position to place the drive in the maintenance or diagnostic mode of operation when that stage is set.
10. Desired Track/Sector Address Register 146
In the track/sector register 146 TRACK ADDRESS and SECTOR ADDRESS bit positions identify, respectively, the track and sector on a disk to be involved in a transfer. In a fixed-head unit, the TRACK ADDRESS bits identify a specific head. The register 146 can be incremented by successive sector signals so that successive sector and tracks can be involved in a transfer. When the last track and sector address allotted to any specific drive have been identified, the LBT stage in the status register 141 is set. The contents of the register 146 can be reset in response to system resetting or CLR signal or a DRIVE CLEAR command.
11. Drive Type Register 147
The drive type register 147 contains preset values to identify the nature of the drive. It might contain, for example, an NSA bit position to indicate a drive which does not use sector addressing or a TAP bit position to indicate a tape, rather than a disk, drive. An MOH bit position can indicate whether a disk is a moving head disk while a 7CH bit position indicates, on a tape unit, whether the tape has seven or nine channels. A DRQ stage could indicate that a drive connects to two controllers. Sometimes a given drive might have a slave drive and an SPR bit position could indicate the presence of such a drive. DRIVE ID bit positions might identify the drive type and major variations.
12. Look-ahead Register 148
13. Drive Serial Number Register 250
For example, it may be desirable to include a drive serial number register 250 in magnetic tape drives or drives with removable disks. The contents of the register will then identify the drive unit during regular operation or during maintenance operations. The contents might be recorded in binary-coded decimal notation.
14. Error Correction Code Register 251 and 252
15. Offset Register 253
16. Desired-cylinder and Current Cylinder Address Registers 254 and 255
17. Attention Summary Register 145
Whenever any stage in an error register 141 sets, its corresponding ATA stage sets. This causes the drive to issue an ATTN signal onto the common ATTN wire 94 to thereby cause system operations to be interrupted. One of the first operations in the ensuing interruption routine is the reading of the attention summary register 145. This reading operation is essentially the same as shown in FIG. 8. In this specific operation, however, the address circuit 151 produces RS' signals with a value of 048, and the RS signals from the output drives 161 have the same value. The controller performs steps 200 through 202 as shown in FIG. 8 and by charts 14A, 14B and 14E at times t1 and t2 in FIG. 14. After a delay, the signals are received by all the drives on the device bus at time t3. Now each drive uses step 204 to branch to step 206 because the DS signals have no meaning. As the RS signals identify register 048, step 205 causes step 206 to transfer the output of the ATA stage in each drive status register 141 onto a corresponding wire in the data set 81 sometime after the DEM signal arrives at t4. At time t5 in Chart 14J each drive transmits its TRA signal and the controller receives all of these in some time interval shown as time t6 in Chart 14F.
Several different signals may be received; however, the controller, while processing them, disables step 217 so the controller timing interval is completed by time t7. Then, in step 221, the controller branches to step 223 and reads the data at time t7 as shown in Chart 14C thereby transferring the ATA signals from all drives to the controller. This is also the time that the controller may terminate the DEM signal as shown in step 214, so that at time t8 the control information is removed and the drives all terminate their respective TRA signals. Then, the reading operation is completed, as previously described, by time t9. Thus, when the reading operation is completed, the system knows exactly which drive or drives sent ATA signals and can immediately begin reading their respective error registers or other registers without any intervening polling operations.
Once all the interrupting drives have been serviced, it is necessary to reset each of the respective ATA stages. This may be done with a writing operation which is similar to that shown in FIG. 10, a specific timing sequence being shown in FIG. 15. At time t1, step 226 loads an appropriate CTOD signal, RS signals with a value 048 and the control information including a parity bit onto their respective wires in the control section 80. At time t2 the DEM signal is loaded onto the bus (step 228). The first control signals are received at t3 and the DEM signal is received at t4, the timing of these signals is shown in Charts 15A, 15B, 15C, 15D, 15F, 15G and 15H. Each drive may respond to the receipt of the DEM signal by transmitting a TRA signal. An ATA stage in each error register also resets at time t5 as shown in FIGURE Charts 15G and 15I if a corresponding signal on a control data wire 84 is asserted. Again, the controller awaits for the completion of the time interval, because in step 246, the controller senses the value of the RS signals. At time t7 the control signals and control data signals shown in Charts 15A, 15B, 15C and 15D are terminated by the controller and the cycle is completed as in a normal remote register writing operation.
There are, as previously indicated, several preliminary drive control path transfers which precede the issuance of any of these data transfer commands. The starting system address must be loaded into the bus address register 137 in the controller (FIGS. 5 and 6). For purposes of this explanation, it is assumed that the A16 and A17 bit positions in the control and status register 133 (FIG. 12) are included in the register 137 as described above. Both the word counter register 136 and the drive word counter register 174 receive a number representing the total number of words to be transferred. The address register 146 in FIG. 7 will contain sector and track addresses and a moving-head disk will contain the desired track, or cylinder, address in the desired-cylinder-address register 254. Once this information has been received by the controller and the designated drive, the system can issue a data transfer command through a register writing operation.
Normally the input buffer 122, the memory 123 and the output buffer 124 are constructed to store some portion of the words from one sector. As already apparent, however, a given transfer may involve more data words or fewer data words than are present in a sector. When the transfer is for fewer words, the drive word counter register 174, which is incremented in response to each data word transfer from the drive to the controller, produces an overflow which is sensed by an overflow circuit 291 before the EBL signal. However, the data words in the input buffer 122 and memory 123 advance until the first word reaches the output buffer 124, the movement into the output buffer 124, being produced by a memory control circuit 292. When the transfer involves more words than are present in a sector, the control 292 senses when the first word reaches the output buffer.
In either case, the presence of a data word in the output buffer causes the control 292 to activate an interruption control circuit 293 to produce an INTERRUPT signal. This signal interrupts the system and, in response to signals received over a selected one of the buses 120 or 400, transfers the contents of the output buffer 124 through bus receivers/drivers 295 or 402 for storage in a location identified by the bus address register 137. These transfers continue until the word counter register 136 indicates that all the required transfers between the controller and the system have occurred. Then the register 136 overflows and an overflow circuit 294 disables the controls 292 and 293.
Thus, in response to a READ command, the controller and drive transfer the desired number of words from a sector or sectors on the medium onto the synchronous data path and then, using direct access memory procedures, to the system over one of the system buses. The storage facility 123 accommodates the diverse transfer rates. Its size and operation also ensure that there is sufficient data available for efficient transfers to the system. If the system does not retrieve data quickly enough, other circuits in the control 126, which are not shown, sense the arrival of data at the receivers 280 and the full input buffer 122 to set the DLT bit in the control and status register 134 as previously indicated.
Initially the interruption control 293 in the controller produces a series of INTERRUPT signals to transfer data as data words during direct memory accesses from one of the system buses 120 or 400 through receiver/drivers 295 or 402 and input multiplexer 281 into the input buffer 122. As the input buffer 122 receives successive data words, the storage control 292 transfers them into the storage facility 123 until the storage facility 123 fills and a data word appears in the output buffer 124 or until the word counter register 136 indicates that all data words to be transferred to the drive are in the controller. In the second case, the data words also shift through the storage facility 123 until the output buffer receives a word.
When the output buffer 124 first receives a data word, the controller may begin a transfer to the drive because the output buffer 124, the storage facility 123 and the input buffer 122 contains a plurality of storage locations. A WRITE signal, produced in response to the FUNCTION bits, enables drivers 297 to load data onto the data set 101 which includes data wires 102 and data parity wire 103. Then the sequence shown in FIGS. 18 and 19 begins.
When the output buffer 124 contains a word, the interruption circuit 292 generates an INTERRUPT signal to effect a data transfer from locations identified by the contents of the bus address register 317 over one of the system buses 120 or 400 through the receivers/drivers circuits 295 or 402 to be a second input to the EXCLUSIVE OR array 298. If any error exists, then the EXCLUSIVE OR array 298 produces a ONE output which a WRITE-CHECK ERROR circuit 299 monitors. The control circuit 126 may then interrupt subsequent operations.
Otherwise the operation is the same as a READ operation in response to a READ command. Successive words from the drive are transferred over the device bus 121. Corresponding words from the system identified by the bus address register 137 are received over one of the system buses 120 or 400 and through the receiver/driver circuits 295 or 402 as in writing operation except they pass directly to the EXCLUSIVE OR array. The word counter register 136 and drive word counter register 174 will terminate the operations and effectively disconnect the controller and the drive as previously discussed.
D. Detailed Description of Control Circuits
I shall now discuss, in detail, the operation of the control circuit 126, shown generally in FIG. 5, which also includes the transfer control circuit 402. A detailed logic circuit is shown in FIGS. 20A, 20B and 20C and 20D. As shown in FIG. 20A, system bus A 120 and system bus B 400 connect respectively to a bus A interface 295a which constitutes a portion of the receivers/drivers 295 shown in FIG. 5 and a bus B interface 401a corresponding to receivers/drivers 401 in FIG. 5. Other portions of the receivers/drivers 295 and 401, shown in FIG. 20D, include a gating A circuit 295b and gating B circuit 401b for coupling data from the output buffer 124 or to the input buffer 122 and a gating A circuit 295c and gating B circuit 401c connected to the output of the address register 137. These four gating circuits in FIG. 20D also are coupled to the system bus A 120 and system bus B 400.
As previously indicated, this invention is directed to operations for routing data, address and control signals to and from an appropriate one of the system buses. The invention itself is applicable to any type of data processing system, but the application of the invention will be clearer if it is described in terms of a specific embodiment. I elect, for purposes of this discussion, to describe the invention in terms of the data processing system described in the previously identified U.S. Pat. No. 3,710,324. The foregoing operations are in response to data transfer commands, such as READ, WRITE and WRITE-CHECK commands as previously discussed. In order to process a data transfer command, there is a transfer of control information to the controller and through the controller to a designated system bus. In order to understand the operation of the circuit shown in FIGS. 20A through 20D, it will be helpful to discuss the READ and WRITE commands in detail. The operation in response to other commands will then be discussed in general terms.
A READ command is issued to retrieve data from the recording medium in a designated drive and route it to one of the system buses 120 or 400. As previously indicated, a sequence of local and remote register transfers prepares the controller and drive for a reading operation. For example, the two's complement value of the number of words to be transferred is loaded into the word counter register 136 and drive word counter register 174. The initial address of a location coupled to the designated system bus for receiving the data word from the drive is loaded into the bus address register 137. Further, the desired address on the drive is loaded into the desired track sector register 146. Other registers also receive information depending on the drive. The final register transfer loads the READ command into the control and status register 133 in FIG. 6 and the control and status register 140 in the drive. As shown in FIGS. 12 and 20D a PSEL bit position (i.e., a PSEL flip-flop 402) is either set or reset during this operation. The signal on a data line corresponding to the PSEL bit position is loaded into the PSEL flip-flop 402 when the REG STR pulse energizes an AND gate 403 enabled by the RDY signal and a CSl in signal. In accordance with the circuits shown in FIG. 20D, the PSEL signal flip-flop 402 sets and transmits a SEL A signal when the PSEL data wire carries a ONE. A ZERO on that wire during the transfer of the READ command would cause the PSEL flip-flop 402 to reset so the SEL A signal would be inactive. In the latter state, the non-asserted SEL A signal would cause the system bus B 400 to be selected
Once these operations are complete, the controller resets or clears the RDY signal to indicate that the controller is actively involved in the data transfer and clears the storage facility 123 and the input and output buffers 122 and 124. Then, the controller asserts the RUN signal to begin the data transfer.
Referring now to transfers over the drive bus 121, when the drive begins to send data it also transmits SCLK pulses on wire 105 (FIG. 4). Timing circuits assure that this signal appears within a predetermined interval. When the SCLK pulse terminates, the drive word counter register 174 is incremented and then the circuitry checks an IBUF FULL flip-flop 404 shown in FIG. 20B. The IBUF FULL flip-flop 404 is normally reset indicating that the input buffer is empty. If it were set upon receipt of an SCLK pulse, an error condition would exist. Other circuitry (not shown) produces the DLT signal and TRE signal in response to this error conduction as previously indicated. Then the RUN signal would be disabled and, upon the negation of the EBL signal on wire 110 (FIG. 4) the drive and controller would effectively disconnect.
During a reading operation, an RWRC signal, which is active whenever a READ or WRITE-CHECK command is decoded, enables an AND gate 405 (FIG. 20B). Assuming that both a system inhibiting (INHCLK) signal and a DRWC OFLO signal are inactive, inverters 406 and 407 enable an AND gate 410 to pass each incoming SCLK pulse to trigger a monostable (i.e., one-shot) multivibrator 411. The triggering pulses are designated DCLK pulses. Each pulse from the multivibrator 411 passes through the enabled AND gate 405, OR gate 412 and OR gate 413 to serve as a CLK IBUF signal. The leading edge of the CLK IBUF pulse loads data into the input buffer 122 and the CLK IBUF pulse serves as an overriding setting signal to the IBUF FULL flip-flop 404. Thus, the flip-flop 404 sets and removes an overriding resetting signal to a BUB IN flip-flop 414. The trailing edge of the CLK IBUF pulse passes through an inverter 415 to shift the BUB IN flip-flop 414 to a set state thereby enabling an AND gate 416. The other input to the AND gate 416 is an IR READY signal transmitted by the storage facility 123 in FIG. 20D whenever that storage facility 123 has a vacant storage location (i.e., is not full). When this IR READY signal is asserted and the BUB IN flip-flop 414 is set, the AND gate 416 produces a SHIFT IN pulse which loads data from the input buffer 122 into the storage facility 123. As soon as the storage facility receives the data, the IR READY signal terminates, so the SHIFT IN pulse also terminates. The trailing edge of the IR READY signal also passes through an inverter 417 to clock the IBUF FULL flip-flop 404 to a reset condition and thereby reset the BUB IN flip-flop 414 and disable the AND gate 416. Even if the storage facility 123 is not now full, the IR READY signal terminates momentarily so as to initiate this resetting operation. The IBUF FULL flip-flop 404 then indicates the input buffer 122 is empty.
The CLK IBUF pulse may be also be produced during a local register writing operation which identifies the input buffer 122 as the destination of control information from the system bus as previously described. In this instance an AND gate 420 receives the OBin signal and the REG STR signal from the register selection decoder 152 and timing circuit 156, respectively (shown in FIG. 6).
Successive SCLK pulses continue to pass through the AND gate 410 to trigger the multivibrator 411 until the drive word counter register 174 in FIG. 6 overflows and activates the DRWC OFLO signal. This indicates that all the requested data has been read from the drive and causes the inverter 407 to inhibit the AND gate 410. If the DRWC OFLO signal is asserted, other circuits (not shown) terminate the RUN signal and wait for the assertion of the EBL signal. When the EBL signal appears and then terminates, the system effectively disconnects and produces the RDY signal indicating that another transfer can occur. If the INH signal becomes active, further operations are also stopped.
As each word is loaded from the input buffer 122 into the storage facility 123, it passes to an output of the storage facility 123 in response to internal control signals. When a word does reach the output, the storage facility 123 transmits an OR READY signal (FIG. 20B). If a BUB OUT flip-flop 421 is set, an AND gate 422 produces a SHIFT OUT pulse concurrently with the OR READY signal to transfer a word out of the storage facility 123. The BUB OUT flip-flop 421 sets each time an OBUF FULL flip-flop 423 resets indicating the output buffer 124 is empty. This pulse also triggers a monostable multivibrator 424 which in turn triggers another monostable multivibrator 425. The output pulse from the monostable multivibrator 425 directly sets the OBUF FULL flip-flop 423 and loads the output buffer 124. With the flip-flop 423 set, the overriding setting signal to the BUB OUT flip-flop 421 terminates so the termination of the OR READY signal after the transfer to the output buffer 124 passes through an inverter 426 to clock the BUB OUT flip-flop 421 to a reset condition and thereby terminate the SHIFT OUT pulse. At this time, the contents of the word counter register 136 are incremented. When the OBUF FULL flip-flop 423 sets, it also enables an AND gate 427 which is enabled during a reading operation by an RWRC signal when a TRE signal from the control and status register 133 is not active indicating that no transfer error exists through an inverter 430. Thus, when the OBUF FULL flip-flop 423 sets and the AND gate 427 is energized, the resulting signal passes through an OR gate 431 as an INTR signal. This signal then causes an interruption sequence to occur with respect to the appropriate one of the system buses 120 or 400.
Now referring to the interruption and transfer sequence, the PSEL flip-flop 402 in FIG. 20D produces an SEL A signal. This signal enables an AND gate 432 in FIG. 20D and, being passed through an inverter 433, disables an AND gate 434. The AND gate 432 enables the gating A circuit 295b while the AND gate 434, which is enabled when the SEL A signal is not active, enables the gating B circuit 401b. During a reading operation, the READ signal also enables an AND gate 435 to produce a DATA-TO-BUS signal while the controller transmits a BUSY signal. The AND gate 435 energizes the enabled one of the AND gates 432 or 434 to load the data from the output buffer 124 through either the gating circuit 295b or 401b onto the system bus 120 or 400. The SEL A signal also energizes or controls the transfer of signals through a multiplexer circuit 436 and an output circuit 437.
When the circuitry in FIG. 20B produces an INTR signal, it passes through an AND gate 440 (FIG. 20A) normally enabled by an inverter 441 which receives a CLR INTR signal which becomes active at the end of an interruption operation. Thus, the INTR signal passes directly through the AND gate 440 and an AND gate 442 which is enabled with a SACK flip-flop 443 and a SYS BUSY flip-flop 444 are both reset. The resulting NPR signal from the AND gate 442 passes through the gating circuit 437 to be routed either onto an NPR conductor in the system bus 120 or 400 after being coupled through the appropriate interface 295a or 401a depending on the value of the SEL A signal.
As described fully in U.S. Pat. No. 3,710,324, the NPR signal on either of the buses 120 or 400 eventually interrupts operations on that system bus. A priority arbitration circuit (not shown) connected to the selected bus transmits an NPG signal indicating that an NPR request has been granted. As described in the foregoing patent, the NPG signal passes through each device connected to the bus in seriatim to be blodked by the first device which has previously generated an NPR signal.
If the controller is connected to system bus A 120, it is necessary for an NPG signal on system bus 400 to pass directly through the controller back to the system bus B 400. Any NPG signal on the system bus A 120 must also pass through the controller unless an NPR signal was previously transmitted by the controller. As shown in FIG. 20A, when the SEL A signal is asserted, indicating that system bus A 120 is the designated bus, it produces one enabling input signal to an AND gate 445 while an inverter 446 disables an AND gate 447. If no INTR signal has been transmitted and if a SYS BUSY flip-flop 444 is not set, an inverter 450 applies a signal to a GRANT A flip-flop 451 which causes the flip-flop 451 to set in response to an input clocking pulse. On the other hand, the inverter 446 keeps the AND gate 447 disabled so long as the SEL A signal is asserted so an inverter 452 applies a signal to a GRANT B flip-flop 453 which causes the flip-flop 453 to set in response to a clocking input signal.
If the SYS BUSY flip-flop 444 is reset and an NPG signal appears on system bus 400, it will not be passed through the multiplexer 436 due to the asserted state of the SEL A signal. However, it does act as a clocking input to the GRANT B flip-flop 453 which sets on the leading edge of the NPG pulse. The output of the GRANT B flip-flop 453 is coupled back directly through the multiplexer 436 to the bus interface 401a and to the system bus B 400. When the incoming NPG pulse terminates, an inverter 454 becomes active and energizes an AND gate 455 which is enabled whenever the GRANT B flip-flop 453 is set. Thus, the trailing edge of the incoming NPG pulse from the system bus 400 resets the GRANT B flip-flop 453 and terminates the outgoing NPG pluse. In this manner, the SEL A signal, when active, assures that any incoming NPG pulses from system bus B 400 pass directly through the controller and back to the bus.
Likewise, if the SEL A signal is not active, indicating that the system is connected to the system bus 400, the AND gate 445 is disabled so the leading edge of an incoming NPG pulse from the system bus A 120 clocks the GRANT A flip-flop 451 to a set condition. The trailing edge of the NPG pulse then energizes an inverter 456 and an enabled AND gate 457 to reset the GRANT A flip-flop 451 and terminate the NPG pulse which is coupled through the bus interface 295a.
Whenever the system shown in already involved in a transfer, the SYS BUSY flip-flop 444 in FIG. 20A is set, and both the AND gates 445 and 447 are disabled. Thus, any incoming NPG pulse from either system bus A or system bus B is routed back through to the appropriate bus as previously described.
Now assuming that the SEL A signal is asserted and the SYS BUSY flip-flop 444 is reset, the AND gate 445 is enabled while the inverter 446 disables the AND gate 447. If no INTR signal appears, both AND gates 445 and 447 are disabled and NPG pulses pass through the controller. However, the appearance of the INTR signal and energization of the AND gate 440 energizes the AND gate 445 so the inverter 450 produces an input to the GRANT A flip-flop 451 which causes it to remain reset upon the appearance of a clocking input. Thus, when an NPG signal appears on system bus A 120, it does not clock the flip-flop 451 to a set condition. Thus, there is no output signal to be coupled back onto the system bus A 120 and the circuit in FIG. 20A blocks the NPG pulse.
Whenever either of the flip-flops 451 or 453 is reset, the multiplexer 436 produces a GRANT signal which enables an AND gate 460. Thus, if an NPG signal is received from the multiplexer 436 while the selected GRANT A flip-flop 451 is reset, the AND gate 460 conditions the SACK flip-flop 443 to be set upon receipt of the leading edge of an NPG pulse from the multiplexer 436 which passes through a delay signal 461. When the SACK flip-flop 443 sets, it couples a SACK signal through the gating circuit 437 and the bus A interface 295a and onto the system bus A 120. In addition, the SACK signal conditions the SYS BUSY flip-flop 444 to be set. Whenever the INTR signal is asserted, the SYS BUSY flip-flop 444 receives a clocking input in response to the concurrent absence of the BUSY signal from the selected bus, indicated by a signal from an inverter 462 and of a SSYN signal as sensed by an inverter 463. If the SACK flip-flop 443 is set, the output from an AND gate 464 clocks the SYS BUSY flip-flop 443 to a set condition and transmits the BUSY signal to the gating circuit 437 back onto the system bus A. This, as described in the foregoing U.S. Pat. No. 3,710,324, enables the controller to control a data transfer to the location on the system bus A 120 addressed by the bus address register 137 shown in FIG. 20D.
Still referring to FIG. 20A, setting the SYS BUSY flip-flop 444 also energizes an OR gate 468 to provide an overriding resetting input to the SACK flip-flop 443. The SACK flip-flop 443 also is maintained in a reset condition whenever the AND gate 440 which is connected to the other input of the OR gate 464.
With the SYS BUSY flip-flop 444 set, an AND gate 465 in FIG. 20C generates an ADR TO BUS signal because an END CYC pulse, when inactive, enables the AND gate 465 through an inverter 466. The END CYC pulse is described later. The ADR TO BUS signal enables AND gates 467 and 470 in FIG. 20D. With the PSEL flip-flop 402 set, the AND gate 470 is enabled while an inverter 471 disables the AND gate 467. As a result, the output of the bus address register 137 is coupled through the gating circuit 295c onto the system bus A 120. As apparent, if the PSEL flip-flop 402 is reset, the AND gate 467 is enabled and the bus address passes through the gating circuit 401c to the system bus B 400. Direction control signals to determine whether a reading or writing operation will be performed over the system bus are also transmitted in response to a READ signal applied to the output circuit 437.
Whenever the OBUF FULL flip-flop 423 in FIG. 20B sets during a drive reading operation, an AND gate 472 in FIG. 20C is disabled so an inverter 473 enables an AND gate 474. Each time the AND gate 465 produces an ADR TO BUS signal, the AND gate 474 triggers a monostable multivibrator 475 which, after a time delay, clocks a DESK COMP flip-flop 476 to a set condition thereby providing one enabling input to an AND gate 477. The time delay enables the data signals on the designated system bus to settle. A second enabling input is provided by an inverter 480 whenever an SSYN signal is not active.
During a reading or write-checking operation, the RWRC signal also enables AND gate 481. Whenever the OBUF FULL flip-flop 423 in FIG. 20B sets, data is available for transfer and produces a signal which energizes the AND gate 477, through an OR gate 482, thereby to clock an MSYN flip-flop 483 to a set condition. The resulting signal is coupled through the output gating circuit 437 in FIG. 20A and onto the selected bus in response to the SEL A signal. This indicates that data is on the system bus.
To prevent a malfunction of the controller should the addressed location be inoperative, the MSYN signal triggers a monostable multivibrator 484 which clocks an NEM flip-flop 485 if the MSYN signal still appears after a time interval. Normally the SSYN signal appears and passes through an OR gate 486 to disable the multivibrator 484 and produce an overriding resetting signal to the flip-flop 485. If the flip-flop 485 should set, it energizes an OR gate 487 and OR gate 490 to terminate further operations; in this type of error condition an ERR CLR signal produced in response to a new function or a clearing command resets the flip-flop 485 and disables the multivibrator 484.
During a normal transfer in response to a READ command, the SSYN signal does appear while the controller is making a transfer, an AND gate 491 energizes the OR gate 487. AND gates 492 and 493 are disabled during a READ command so a monostable multivibrator 494 is inactive and an inverter 495 enables an AND gate 496. Prior to the arrival of the SSYN signal, an inverter 497 enabled an AND gate 500 so the AND gate 500 and an inverter 501 disabled the AND gate 496. With the appearance of the SSYN signal, however, the AND gate 500 is disabled so the AND gate 496 triggers a monostable multivibrator 503 to produce a DATA STR pulse and reset the MSYN flip-flop 483 through an OR gate 504.
During a READ command the DATA STR pulse energizes an AND gate 505 and OR gates 506 and 507 in FIG. 20B to clock the OBUF FULL flip-flop 423 to a reset condition. This sets the BUB OUT flip-flop 421 to permit the next word to pass into the output buffer 124 as previously described. When the DATA STR pulse terminates, an inverter 510 (FIG. 20C) triggers a monostable multivibrator 511 to produce the END CYC pulse. If an OR gate 512 is energized by OR gate 517, an AND gate 513 couples the END CYC pulse as a CLR BUSY pulse.
The CLR BUSY signal passes through an OR gate 514 as the CLR INTR pulse in FIG. 20B so an inverter 515 disables an AND gate 516 which provides a latching feedback path for the OR gate 431. This terminates the INTR signal until the OBUF FULL flip-flop 423 sets again. Each time the RDY signal is transmitted, it also energizes the OR gate 514. In addition, the END CYCLE pulse disables the AND gate 465 to terminate the ADR TO BUS signal momentarily. This removes the address and direction control signals from the system bus while the ADR TO BUS signal is disabled. An inverter 521 on FIG. 20D provides an incrementing or decrementing pulse to the bus address register 137. As shown in FIG. 20D, a flip-flop 522 receives information in response to a GO CLR signal generated when a transfer command is loaded. If particular function bit positions (e.g., F0 and F1 bit positions) are both set, the bus address register is to be incremented to identify successive locations. Some transfer commands may more appropriately load data in a reverse direction. If that occurs, an AND gate 523 is not energized. Thus, when a command is loaded, the flip-flop 522 will set if the contents of the bus address register are to be incremented during each successive transfer. The set and reset outputs from the flip-flop 522 are received by AND gates 524 and 525 respectively. When the ADR TO BUS signal becomes inactive, an AND gate 526 is energized by an inverter 527 if the BAI bit position in the control and status register 134 is reset. The resulting pulse passes through the enabled one of the AND gates 524 or 525 to alter the bus address register 137.
The controller may transmit one data word each time it transmits an NPR pulse as is the normal transfer procedure for other units. During a reading operation, however, it is desirable to keep the storage facility 123 as empty as possible. As apparent, the system may suddenly receive interruptions of a higher priority which do not enable a transfer of data from the output buffer. If the storage facility 123 is kept relatively empty, more transfers from the drive can be buffered before an error condition exists. In accordance with another aspect of this invention, the controller may transfer two data words during each interruption operation. Referring to FIG. 20C, whenever the SYS BUSY flip-flop 444 is reset, an inverter 527 energizes the OR gate 490 to provide an overriding setting signal to a CYC CT flip-flop 530. During a transfer operation, the SYS BUSY flip-flop 444 (FIG. 20A) sets. If the NEM flip-flop 485 remains reset and a WC OFLO signal is inactive, the overriding setting signal is removed. Each DATA STR pulse constitutes a clocking pulse to the flip-flop 530. If a switch 531 is closed and no TRE signal is present, the clocking pulse reverses the state of the flip-flop 530 and resets it thereby disabling one input to the OR gate 517. If an AND gate 532 is energized, indicating another word can be transferred, then an OR gate 533 conditions a NXT CYC flip-flop 534 to be set. When the CYC CT flip-flop 530 is reset and the NEXT CYC flip-flop 534 simultaneously is set, the OR gate 517 is not energized so neither the CLR BUSY nor CIR INTR pulses are generated. Thus, after the END CYC pulse terminates, another transfer operation can occur as soon as the OBUF FULL flip-flop 423 sets. When the DATA STR pulse is now generated after this cycle, however, the CYC CT flip-flop 530 sets thereby energizing the OR gates 517 and 512. Then the AND gate 513 can transmit the CLR BUSY pulse.
It will be apparent, from FIG. 20C, the appearance of a UPE or WCE signal indicating the corresponding error conditions as previously described also energize the OR gate 512 to produce the CLR BUSY signal immediately upon the receipt of the END CYC pulse. Thus, the CYC CT flip-flop 530 and NXT CYC flip-flop 534 enable two transfer operations during one interruption operation.
If the system bus B 400 is connected to other units which cannot control data transfers or are of a very low priority, another signal could be applied to an OR gate 535 so as to maintain the CYC CT flip-flop 536 in a reset condition. Thus, assuming that the intervals between successive DATA STR pulses weresufficiently long enough to enable the storage facility 123 to provide every word, an entire block of data could be transferred onto the system bus B 400 without interruption. Normally this would not be done with system bus A 120 or any bus which has other devices with other units because these block transfers require disproportionately long intervals.
These transfer operations continue until all the words to be read are transferred to the system. Then the WC OFLO signal is generated as the word counter register 136 is incremented. When this occurs, the OR gate 490 in FIG. 20C sets the CYC CT flip-flop so the next END CYC pulse produces the CLR BUSY and CLR INTR pulses. If a word is not available at the output of the facility 123, the OR READY signal does not appear at the time of the DATA STR pulse so the AND gate 532 and OR gate 533 conditions the NXT CYC flip-flop 534 to reset. This energizes the OR gates 517 and 512 so the END CYC pulse produces the CLR BUSY pulse.
Thus, the circuitry in FIGS. 20A through 20D during a reading operation accepts data from a drive and transfers it to the input buffer and through the storage facility 123 to the output buffer 124. Data is then routed to a system bus depending upon the contents of the PSEL bit position in the data transfer command.
During a writing operation, data is supplied from the selected one of system buses 120 or 400 to the input buffer 122 in response to a WRITE command. Initially, local and remote register transfers load the number of words to be transferred into the word counter register 136 and drive word counter register 174 and the starting memory location into the bus address register 137. Other information concerning the starting location in the drive to receive the data is also provided. Then the system loads a WRITE command containing appropriate function bits and a ONE in the GO bit position. In response to this, a RDY signal terminates and the contents of the storage facility 123 and other related circuits are cleared. The initial data transfer during a writing operation occurs between selected system bus 120 or 400 and the controller. When the WRITE signal is generated, it enables an AND gate 537 in FIG. 20B. The coincidence of the WRITE signal, the absence of a WC OFLO signal signified by an assertive signal from an inverter 541 indicating more words are to be transferred and the output from the inverter 430 indicating no transfer errors occur, initially energize an AND gate 542 and the signal from an OR gate 543 produced when the IBUF FULL flip-flop 404 is reset produces an INTR signal at the output of the OR gate 431. The resulting INTR signal produces an NPR signal from the output of an AND gate 442 in FIG. 20A which is routed through the gating circuit 437 in response to the SEL A signal as previously described. Then the circuitry shown in FIG. 20A reacts in response to the incoming NPG signal from the selected bus by setting the SACK flip-flop 443 and, upon the release of the selected bus, by taking control of the bus by setting the SYS BUSY flip-flop 444 and resetting the SACK flip-flop 443.
During a writing operation, the READ signal is not asserted. Thus, the AND gate 472 in FIG. 20C is never energized. Under these conditions the inverter 473 enables an AND gate 474 to pass the ADR TO BUS signal and trigger the multivibrator. Thus, when the SYS BUSY flip-flop 444 in FIG. 20A sets, indicating the controller has control of the system bus, and any prior END CYC signal terminates, the AND gate 465 energizes the AND gate 474 and triggers the multivibrator 475 thereby clocking the DESK COMP flip-flop 471 to a set condition. Assuming that an SSYN signal has previously been terminated, the inverter 480 provides a second enabling input to the AND gate 477. With the IBUF FULL flip-flop 412 in FIG. 20B reset, the output of an AND gate 537, which is enabled by the WRITE signal, produces a third enabling signal through the OR gate 482 to clock the MSYN flip-flop 483 to a set condition. As previously indicated, if no SSYN signal is received from the designated bus after a predetermined time, the multivibrator 484 clocks the NEM flip-flop 485 to a set condition and the operation subsequently terminates with a nonexistent memory error. The timely receipt of an SSYN signal however, disables the multivibrator 484 and provides an overriding resetting signal to the NEM flip-flop 485.
The output from the SYS BUSY flip-flop 444 and the SSYN signal energize an AND gate 491 to provide one enabling input to an AND gate 493. An inverter 507 provides a second enabling input so the MSYN signal from the set flip-flop 483 energizes the AND gate 493 and triggers the multivibrator 494 when the IBUF FULL flip-flop 412 is reset. An inverter 541 indicates a reset IBUF FULL flip-flop 404. The inverter 495 disables the AND gate 496 and then triggers the multivibrator 503 to produce the DATA STR signal.
The DATA STR pulse energizes the AND gate 537 to produce the CLK IBUF pulse and the OR gate 504 to terminate the MSYN signal. Referring to FIG. 20D, the selection from one of the gating circuits 295b or 401b is made in an input gating circuit 542 in response to the SEL A signal and a non-asserted DATA-TO-BUS signal. The termination of the CLK IBUF signal passes through the inverter 415 in FIG. 20B to set the BUB IN flip-flop 414 as setting of the IBUF FULL flip-flop 404 removes the overriding resetting signal from the BUB IN flip-flop 414. When the IR READY signal indicates that the input to the storage facility 123 in FIG. 20D can accept new data, the AND gate 416 in FIG. 20B produces the SHIFT IN pulse so another transfer can occur. If the INTR signal has been disabled, this enables a new INTR signal
Referring to FIG. 20C, if the storage facility has additional space, the IR READY signal will reappear and together with the WRITE signal, energize another AND gate 543. 20C. This produces the same basic operation as during a READ operation if it is desired to couple a pair of words into the input buffer during a writing operation. While it is desirable to keep the storage facility as empty as possible during a reading operation, it is desirable to keep the storage facility 123 as full as possible during a writing operation.
Although not disclosed in any FIGURES, it is sometimes desirable to amass a number of words in the storage facility 123 before starting an actual writing operation over the data bus. A counter might be cleared on receiving a WRITE or WRITE-CHECK operating command to generate subsequently a START signal after the facility 123 receives a predetermined number of words, an indication that all the words to be transferred have been loaded into the storage facility 123, or an indication that a transfer error has occurred. Then a START signal would be generated to initiate a transfer into the system.
Still referring to the interaction between system and the controller during a writing operation, the DATA STR signal also produces the END CYCLE pulse and CLR BUSY pulse with the same results as previously discussed.
Now referring to the transfer of data from the output buffer, the output buffer 124 in FIG. 20B receives the DATA-TO-BUS signal from the AND gate 435 which passes through an inverter 544 to route data from the output buffer onto the device bus 121. When the data being loaded into the storage facility from the system bus is ready for a transfer to the output buffer 124, the OR READY signal energizes the AND gate 422 in FIG. 20B to shift the data out and trigger the multivibrators 424 and 425 thereby set the OBUF FULL flip-flop 423. When this is done and the START signal is generated, the controller generates the RUN signal which enables the drive to transmit SCLK pulses back to the controller. These pulses are applied to an AND gate 545 in FIG. 20B to be transferred back to the drive as WCLK pulses. The appearance of each DCLK pulse from the AND gate 410 during a writing operation causes an AND gate 546 to pass the DCLK pulse to the OR gate 507 to clock the OBUF FULL flip-flop 423 to a reset condition thereby setting the BUB OUT flip-flop 421 and loading data from the output buffer onto the data lines in the device bus 121 with the WCLK pulse. When the SCLK pulse terminates and the OBUF FULL flip-flop 423 is reset to set the BUB OUT flip-flop 421, the drive word counter register 174 can be incremented. If additional words are to be transferred, the next appearance of the OR READY signal will again set the OBUF FULL flip-flop 423 to repeat the process. If the OR READY signal is not asserted, then a DLT and TRE signals are asserted so that the termination of the next SCLK pulse loads ZEROES onto the data lines and terminates the RUN signal. When a normal transfer terminates, the DRWC OFLO signal disables the AND gate 410 so no DCLK pulses are produced. Subsequent locations in the drive are loaded with ZEROES until the RUN signal terminates and the EBL signal is asserted by the drive. Then the drive and controller effectively disengage from each other to terminate the operation.
Thus, during a writing operation, data moves from locations on a selected system bus determined by the output of the PSEL flip-flop 402 into the input buffer 122 through input gating circuit 543. The words may then be transferred into the drive from the output buffer 124.
3. WRITE-CHECK operations
During the WRITE-CHECK operation, the system provides data in accordance with a writing operation while the drive provides data in accordance with the reading operation. Thus, the AND gate 435 in FIG. 20D does not generate a DATA-TO-BUS signal during a write-check operation, so the data from the drive passes to the input buffer 122. In other areas, distinctions are made between a reading operation identified by a READ signal and a reading or write-checking operation either of which produces the RWRC signal. For example, the procedure for clocking the MSYN flip-flop 483 in FIG. 20C is the same for both reading and write-checking operations as is the control of the number of transfers which occur during any given interrupt with respect to the operation of the flip-flops 530 and 534.
This invention has thus been discussed in terms of a specific data processing system and in terms of three specific data transfer commands for performing reading, writing or write-checking operations. Other analogous data transfer commands for reading data or writing data in a reverse mode can also be implemented. Thus, the disclosure is by way of example only. It is realized that many of the circuits including the detailed circuits of FIGS. 20A through 20D may be modified extensively while still performing the same basic operation as those disclosed. Specifically, other circuits will obviously be useful in different systems for generating the INTR signal which produces a data transfer and further, other circuits would be useful in performing the bus selection operation. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the spirit and scope of this invention.
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