Source: https://patents.google.com/patent/US8966284B2/en
Timestamp: 2018-08-20 12:05:14
Document Index: 294493653

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 06814655', 'art 1', 'art 2']

US8966284B2 - Hardware driver integrity check of memory card controller firmware - Google Patents
Hardware driver integrity check of memory card controller firmware Download PDF
US8966284B2
US8966284B2 US11285600 US28560005A US8966284B2 US 8966284 B2 US8966284 B2 US 8966284B2 US 11285600 US11285600 US 11285600 US 28560005 A US28560005 A US 28560005A US 8966284 B2 US8966284 B2 US 8966284B2
loader portion
US11285600
US20070061897A1 (en )
This application is related and claims priority to Provisional Application No. 60/717,347, filed Sep. 14, 2005 entitled “Hardware Driver Integrity Check of Memory Card Controller Firmware” to Micky Holtzman et al.
This application is also related to application Ser. No. 11/284,623 (now U.S. Pat. No. 7,536,540) entitled “Method of Hardware Driver Integrity Check of Memory Card Controller Firmware” to Micky Holtzman et al.; application Ser. No. 11/053,273 entitled “Secure Memory Card with Life Cycle Phases” to Micky Holtzman et al.; Provisional Application No. 60/717,163 entitled “Secure Yet Flexible System Architecture For Secure Devices With Flash Mass Storage Memory” to Micky Holtzman et al.; and Provisional Application No. 60/717,164 entitled “Secure Yet Flexible System Architecture For Secure Devices With Flash Mass Storage Memory” to Micky Holtzman et al. All of the aforementioned applications are hereby incorporated by this reference in their entireties.
It is crucial to be able to verify the functionality of commercially available memory cards before they leave the factory, and to ensure that the cards are secure from hackers once they leave the factory. With the advent of digital rights management and the spread of protected content such as music and movies etc. . . . there is a need to ensure that the contents of the card cannot be freely copied. One way a hacker may attempt to do this is to alter or even replace the firmware that runs the memory card in order to be able to pirate the contents of the card. Thus it is essential to provide a system that ensures both the integrity and the reliability of the firmware running on the card at all times.
The buffer management unit 14 comprises a host direct memory access unit (HDMA) 32, a flash direct memory access unit (FDMA) 34, an arbiter 36, a CPU bus arbiter 35, registers 33, firmware integrity circuitry (FWIC) 31, buffer random access memory (BRAM) 38, and a crypto engine 40 also referred to as encryption engine 40. The arbiter 36 is a shared bus arbiter so that only one master or initiator (which can be HDMA 32, FDMA 34 or CPU 12) can be active at any time and the slave or target is BRAM 38. The arbiter is responsible for channeling the appropriate initiator request to BRAM 38. HDMA 32 and FDMA 34 are responsible for data transported between HIM 16, FIM 18 and BRAM 38 or the RAM 11. The CPU bus arbiter 35 allows for direct data transfer from crypto engine 40 and flash DMA 34 to RAM 11 via system bus 15, which is used in certain situations such as for example when it is desired to bypass the crypto engine. The operation of the HDMA 32 and of the FDMA 34 are conventional and need not be described in detail herein. The BRAM 38 is used to store data passed between the host device 24 and flash memory 20. The HDMA 32 and FDMA 34 are responsible for transferring the data between HIM 16/FIM 18 and BRAM 38 or the CPU RAM 12 a and for indicating sector completion.
FIG. 3 illustrates the structure of some data sectors utilized by system 10 when in integrity check mode. The BLR, in particular, preferably utilizes this structure. The BLR code 307 itself is seen sandwiched between other data to make up the BLR 201 a. Before the BLR code 307 is loaded, some configuration information is loaded. The configuration information is contained in the file identification (FID) sectors 1 and 7. The BLR code 307 is followed by the message authentication code sector 309. Within MAC sector 309 is the MAC value for the corresponding portion of the BLR code 307. This is the MAC value compared with the value calculated in FIG. 5, which is discussed in greater detail below. The MAC sector is zero padded to accommodate data of varying lengths so that the MAC always occupies the last 128 bits of the sector. The BLR code 307 is stored in flash memory 20 in the BLR portion 200 a, and the configuration information may also be stored in flash memory 20.
MAC[0 . . . (i)]=MAC[MAC[0 . . . (i−1)],block(i)].
firmware stored in the flash memory that controls writing data to and reading data from the flash memory and comprises a boot-loader portion and a main portion, wherein the boot loader portion, when executed, loads the main portion to the random access memory;
wherein the integrity of the boot-loader portion is verified by comparing a value stored in the memory card with an encryption value calculated from the boot-loader portion by the controller encryption hardware as the boot-loader portion is uploaded to the random access memory when the memory card is powered up.
2. The memory card of claim 1 wherein the memory card further comprises instructions for checking a flag at the end of an initial booting process indicating that the boot-loader portion integrity has been verified.
3. The memory card of claim 1 wherein the integrity of the boot-loader portion is verified with hash values calculated as the boot-loader portion is uploaded to the random access memory.
4. The memory card of claim 1 wherein verifying the integrity of the boot-loader portion comprises utilizing MAC values for the boot-loader portion.
5. The memory card of claim 1 wherein the flash memory comprises memory cells of the NAND variety, and wherein an intermediate MAC value is calculated for a group of NAND pages.
7. The memory card of claim 1 wherein the controller comprises a firmware integrity circuit that manages the integrity check of the boot-loader portion.
8. The memory card of claim 1 wherein verifying the integrity of the boot-loader portion comprises utilizing SHA-1 values for the boot-loader portion.
a set of instructions that control data storage and retrieval operations of the mass storage device, the set of instructions stored in the flash memory and comprises a boot-loader portion and a main portion, wherein the boot loader portion, when executed, loads the main portion to the random access memory; and
an encryption engine implemented in hardware circuitry of the mass storage device, the encryption engine encrypting and decrypting data stored in and read from the flash memory,
the encryption engine operable to verify the integrity of the boot-loader portion when the mass storage device is powered up, wherein the integrity of the boot-loader portion is verified by comparing a value stored in the mass storage device with an encryption value calculated by the encryption engine.
10. The mass storage device of claim 9 wherein the boot-loader portion does not comprise instructions that verify the integrity of at least a portion of the instructions.
11. The mass storage device of claim 9 wherein the boot-loader portion comprises instructions for checking the status of an indicator, the indicator indicating whether or not the integrity of the boot-loader portion has been verified.
a non-transitory mass storage medium comprising flash memory;
firmware residing in the non-transitory mass storage medium and comprising a boot-loader portion and a main portion, wherein the boot loader portion, when executed, loads the main portion to the random access memory; and
a hardware implemented cryptographic engine, wherein the cryptographic engine is used to verify the integrity of the boot-loader portion when the memory card is powered up, wherein the integrity of the boot-loader portion is verified by comparing a value stored in the memory card with an encryption value calculated by the cryptographic engine.
13. The memory card of claim 12 further comprising code, wherein the code comprises instructions to load the boot loader portion of the firmware into the random access memory.
14. The memory card of claim 13 wherein the code comprises instructions to check a hardware flag indicative of the integrity of the boot loader portion that was verified using the cryptographic engine.
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOLTZMAN, MICHAEL;BARZILAI, RON;ELHAMIAS, REUVEN;AND OTHERS;REEL/FRAME:017404/0572;SIGNING DATES FROM 20060301 TO 20060319
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOLTZMAN, MICHAEL;BARZILAI, RON;ELHAMIAS, REUVEN;AND OTHERS;SIGNING DATES FROM 20060301 TO 20060319;REEL/FRAME:017404/0572
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