Source: http://www.google.com/patents/US6667494?ie=ISO-8859-1&dq=5726663
Timestamp: 2015-02-01 11:57:52
Document Index: 503529346

Matched Legal Cases: ['application No. 10', 'application No. 11', 'application No. 11', 'application No. 7', 'application No. 8', 'application No. 7', 'application No. 7', 'application No. 09', 'application No. 09']

Patent US6667494 - Semiconductor device and semiconductor display device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device including a control circuit for carrying out gamma correction of a supplied signal and a memory for storing data used in the gamma correction. The control circuit and the memory are constituted by TFTs and are a integrally formed on the same insulating substrate. A semiconductor...http://www.google.com/patents/US6667494?utm_source=gb-gplus-sharePatent US6667494 - Semiconductor device and semiconductor display deviceAdvanced Patent SearchPublication numberUS6667494 B1Publication typeGrantApplication numberUS 09/132,633Publication dateDec 23, 2003Filing dateAug 11, 1998Priority dateAug 19, 1997Fee statusPaidAlso published asUS6597014, US6670635, US7126156, US7750347, US20040094765, US20070034873Publication number09132633, 132633, US 6667494 B1, US 6667494B1, US-B1-6667494, US6667494 B1, US6667494B1InventorsShunpei Yamazaki, Jun KoyamaOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (70), Non-Patent Citations (11), Referenced by (17), Classifications (35), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and semiconductor display deviceUS 6667494 B1Abstract A semiconductor device including a control circuit for carrying out gamma correction of a supplied signal and a memory for storing data used in the gamma correction. The control circuit and the memory are constituted by TFTs and are a integrally formed on the same insulating substrate. A semiconductor display device including a pixel region in which a plurality of TFTs are arranged in matrix; a driver for switching the plurality of TFTs; a picture signal supply source for supplying a picture signal; a control circuit for carrying out gamma correction of the picture signal; and a memory for storing data used in the gamma correction of the picture signal. The plurality of TFTs, the driver, the control circuit, and the memory are integrally formed on the same insulating substrate.
a pixel region in which a plurality of TFTs are arranged in matrix; a driver for switching the plurality of TFTs; a digital picture signal supply source for supplying a digital picture signal; a conversion circuit for converting the digital picture signal to an analog signal; a control circuit for carrying out gamma correction of the digital picture signal; and a memory for storing data used in the gamma correction of the digital picture signal, wherein the conversion circuit includes a plurality of voltage lines for supplying different voltages to source lines of the plurality of TFTs; and wherein the plurality of TFTs, the driver, the control circuit, and the memory are integrally disposed on a same insulating substrate. 9. A device according to claim 8, wherein the memory is a nonvolatile memory.
a pixel region in which a plurality of TFTs are arranged in matrix; a driver for switching the plurality of TFTs; a picture signal supply source for supplying a picture signal; a control circuit for carrying out gamma correction of the picture signal; and a memory for storing data used in the gamma correction of the picture signal, wherein the plurality of TFTs, the driver, the control circuit, and the memory are integrally disposed on a same insulating substrate. 14. A device according to claim 13, wherein the memory is a nonvolatile memory.
a pixel region in which a plurality of TFTs are arranged in matrix; a driver for switching the plurality of FTFs; a digital picture signal supply source for supplying a digital picture signal; a conversion circuit for converting the digital picture signal to an analog signal; a control circuit for carrying out gamma correction of the digital picture signal; and a memory for storing data used in the gamma correction of the digital picture signal, wherein the conversion circuit includes a plurality of voltage lines for supplying different voltages to source lines of the plurality of TFTs; and wherein the plurality of TFTs, the driver, the control circuit, and the memory are integrally disposed on a same insulating substrate. 21. A device according to claim 20, wherein the memory is a nonvolatile memory.
SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a semiconductor display device, particularly a liquid crystal display device, which is able to carry out excellent gradation display and which is able to be miniaturized.
Reference numeral 108 denotes a pixel region which is constituted by a plurality of thin film transistors (TFTs) arranged in a matrix. The pixel region 108 is also called a pixel matrix circuit. In this embodiment, the number of pixels was made 1024�768 in length and breadth. Although explanation will be made with respect to a liquid crystal display device having the foregoing number of pixels in this embodiment, the present invention is not limited to a liquid crystal display device having the foregoing number of pixels.
Next, the operation of the liquid crystal display device of this embodiment will be described. Reference will be made to FIG. 2. FIG. 2 is a schematic structural view showing the memory 105 of this embodiment. The memory 105 of this embodiment is constituted by a plurality of memory elements and X- and Y-address decoders 201 and 202. As shown in FIG. 2, a storage element (memory element) for recording each bit information is constituted by two TFTs. One is a P-channel FAMOS (Floating gate Avalanche injection MOS) type nonvolatile memory element Tr1 having a floating gate, and the other is an N-channel switching element Tr2. In the two TFTs Tr1 and Tr2, the drain electrodes are connected in series with each other. This series connection circuit constitutes a one-bit memory element. Memory elements of 64�64 in length and breadth, each of which is made of the foregoing one-bit memory element, are arranged in matrix. Since each memory element can store one-bit information, the memory 105 in this embodiment has a storage capacity of 4096 bits (=about 4K bits).
In this embodiment, management is done so that the concentration of each of C (carbon), N (nitrogen), O (oxygen), and S (sulfur), which are typical impurities in the amorphous silicon film 402, becomes less than 5�1018 atoms/cm3 (preferably not larger than 1�1018 atoms/cm3). This is preferred because if the concentration of any one of the impurities exceeds the above value, the impurity may have a bad influence on the film at crystallization and may cause the film quality to be degraded after the crystallization.
Next, after the adding step of the catalytic element is concluded, dehydrogenating is carried out at about 450� C. for 1 hour. Then, a heat treatment is carried out in an inert gas atmosphere, a hydrogen atmosphere, or an oxygen atmosphere at a temperature of 500 to 700� C. (typically 550 to 650� C.) for 4 to 24 hours to crystallize the amorphous silicon film 402. In this embodiment, the heat treatment is carried out in a nitrogen atmosphere at 570� C. for 14 hours.
In this embodiment, an example is shown in which a heat treatment is carried out in an oxygen atmosphere containing hydrogen chlorine (HCl) of 0.5 to 10 vol % (in this embodiment, 3 vol %) at 950� C. for 30 minutes. If the concentration of HCl is higher than the above-mentioned concentration, roughness comparable to a film thickness is produced on the surfaces of the active layers 409, 410 and 411. Thus, such a high concentration is not preferred.
In this step, it is conceivable that nickel is removed in such a manner that nickel in the active layers 409, 410 and 411 is gettered by the action of chlorine and is transformed into volatile nickel chloride which is released into the air. By this step, the concentration of nickel in the active layers 409, 410 and 411 is lowered to 5�1017 atoms/cm3 or less.
Incidentally, the value of 5�1017 atoms/cm3 is the lower limit of detection for SIMS (Secondary Ion Mass Spectroscopy). As a result of analysis of TFTs experimentally produced by the inventors of the present application, it was discovered that when the concentration is not higher than 1�1018 atoms/cm3 (preferably 5�1017 atoms/cm3 or less), the influence of nickel upon the TFT characteristics can not be seen. However, it should be noted that the concentration of an impurity in the present specification is defined as a minimum value in measurement results of the SIMS analysis.
As a result of a SIMS analysis for other elements, it was confirmed that the concentration of any of C (carbon), N (nitrogen), O (oxygen), and S (sulfur) as typical impurities was less than 5�1018 atoms/cm3 (typically 1�1018 atoms/cm3 or less).
In this embodiment, the addition of impurity is divided and is carried out two times. The first impurity addition (P (phosphorus) is used in this embodiment) is carried out at a high acceleration voltage of about 80 KeV to form a n− region. Adjustment is made so that the concentration of p ion impurity in the n− region becomes 1�1018 to 1�1019 atoms/cm3.
Next, the entire substrate is heated in a hydrogen atmosphere at a temperature of 350� C. for 1 to 2 hours to hydrogenate the entire device, so that the dangling bonds (unpaired bonds) in the film (especially in the active layer) are compensated. Through the above steps, it is possible to manufacture the CMOS circuit and the pixel matrix circuit on the same substrate.
Here, a semiconductor thin film manufactured by a manufacturing method of this embodiment will be described. According to the manufacturing method of this embodiment, it is possible to obtain a crystalline silicon film called by the present applicant �continuous grain boundary crystalline silicon so-called Continuous Grain Silicon: CGS)� by crystallizing an amorphous silicon film.
{220} orientation existence ratio=1 (constant), {111} orientation existence ratio=(relative strength of {111} to {220} of a sample)/(relative strength of {111} to {220} of powder),
The difference in the number of defects appears as the difference in spin density by the analysis of ESR (Electron Spin Resonance). In the present circumstances, it is ascertained that the spin density of the crystalline silicon film by the manufacturing method of this embodiment is at most 5�1017 spins/cm3 (preferably 3�1017 spins/cm3 or less). However, since this measurement value is near the detection limit of an existing measuring device, it is expected that the actual spin density is lower than this value.
Incidentally, in the formation of the CGS, the foregoing annealing step at a temperature above the crystallizing temperature (700 to 1100�) plays an important role with respect to lowering defects in the crystal grain. This will be described below.
However, when Ni, existing in the defects, is removed by carrying out the gettering process of the catalytic element, the bond of Si�Ni is cut. Thus, the remaining bond of silicon immediately forms a Si�Si bond and becomes stable. In this way, the defects disappear.
The inventors of the present invention also contemplate a model in which the crystalline silicon film is bonded to its under layer by a heat treatment at a temperature (700 to 1100� C.) above the crystallizing temperature, and adhesiveness is increased, so that the defects disappear.
The continuity of crystal lattices in the crystal grain boundary is caused from the fact that the crystal grain boundary is a grain boundary called �plane grain boundary�. The definition of the plane grain boundary in the present specification is given as �Planar boundary� set forth in �Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics, vol. 27, No. 5, pp. 751-758, 1988�.
Reference will be made to FIG. 10. Reference numeral 1001 denotes an analog signal supply source for supplying an analog picture signal, such as a video signal or a television signal. Reference numeral 1002 denotes a gamma correction control circuit for gamma correcting the analog signal supplied from the analog picture signal supply source 1001. Reference numeral 1003 denotes a D/A conversion circuit, and 1004 denotes a memory. The memory 1004 is similar to that in Embodiment 1. Reference numeral 1005 denotes a source signal line side driver, and 1006 denotes a gate signal line side driver. Reference numeral 1007 denotes a pixel region which is constituted by a plurality of thin film transistors (TFTs) arranged in a matrix. The pixel region 1007 is also called a pixel matrix circuit. In this embodiment, the number of pixels is made 1024�768 in length and breadth. In this embodiment, although the liquid crystal display device having the foregoing number of pixels will be described, the present invention is not limited to a liquid crystal display device having the foregoing number of pixels.
If Ta or Ta alloy is used for the gate electrode, it is possible to carry out thermal oxidation at about 450� C. to about 600� C., so that an oxide film having excellent film quality, such as a Ta2O3 film, is formed on the gate electrode. It is known that this oxide film has a film quality better than that of the oxide film formed when Al (aluminum) is used for the gate electrode, as described in the above embodiment 1.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4065781Jun 21, 1974Dec 27, 1977Westinghouse Electric CorporationInsulated-gate thin film transistor with low leakage currentUS4394688Aug 25, 1981Jul 19, 1983Hamamatsu Systems, Inc.Video system having an adjustable digital gamma correction for contrast enhancementUS4409724Nov 3, 1980Oct 18, 1983Texas Instruments IncorporatedMethod of fabricating display with semiconductor circuits on monolithic structure and flat panel display produced therebyUS4766477Jul 11, 1986Aug 23, 1988Canon Kabushiki KaishaCarbon, sulfur, nitrogen, oxygenUS4774556Jul 21, 1986Sep 27, 1988Nippondenso Co., Ltd.Non-volatile semiconductor memory deviceUS4780424Sep 28, 1987Oct 25, 1988Intel CorporationNitriding, oxidation, doping, etchingUS4861730Jan 25, 1988Aug 29, 1989Catalyst Semiconductor, Inc.SemiconductorsUS4929988Aug 23, 1988May 29, 1990Kabushiki Kaisha ToshibaNon-volatile semiconductor memory device and method of the manufacture thereofUS5017977Jan 19, 1990May 21, 1991Texas Instruments IncorporatedDual EPROM cells on trench walls with virtual ground buried bit linesUS5021848Mar 13, 1990Jun 4, 1991Chiu Te LongElectrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereofUS5053842May 30, 1990Oct 1, 1991Seiko Instruments Inc.Semiconductor nonvolatile memoryUS5071782Jun 28, 1990Dec 10, 1991Texas Instruments IncorporatedReduced cell area and channel lengthUS5078498Jun 29, 1990Jan 7, 1992Texas Instruments IncorporatedTwo-transistor programmable memory cell with a vertical floating gate transistorUS5146426Nov 8, 1990Sep 8, 1992North American Philips Corp.Electrically erasable and programmable read only memory with trench structureUS5188976Jul 9, 1991Feb 23, 1993Hitachi, Ltd.Manufacturing method of non-volatile semiconductor memory deviceUS5202576Jun 25, 1991Apr 13, 1993Texas Instruments IncorporatedAsymmetrical non-volatile memory cell, arrays and methods for fabricating sameUS5260797Jun 7, 1990Nov 9, 1993Matsushita Electric Industrial Co., Ltd.Projection type image display apparatus with circuit for correcting luminance nonuniformityUS5350937Oct 7, 1992Sep 27, 1994Semiconductor Energy Laboratory Co., Ltd.Non-volatile memory device having a floating gateUS5430320Dec 17, 1993Jul 4, 1995Samsung Electronics Co., Ltd.Thin film transistor having a lightly doped drain and an offset structure for suppressing the leakage currentUS5452019Oct 25, 1993Sep 19, 1995Sharp Kabushiki KaishaProjected image displaying apparatus and a method of correcting color unevenness thereinUS5481317Sep 9, 1994Jan 2, 1996Canon Kabushiki KaishaGamma correction circuit which selects one of a plurality of gamma corrected signals as an output signal based on the level of an input signalUS5481320Jul 13, 1992Jan 2, 1996Semiconductor Energy Laboratory Co., Ltd.Electro-optical apparatus utilizing at least three electro-optical modulating device to provide a sythesized color image and method of driving sameUS5539459May 18, 1995Jul 23, 1996Polaroid CorporationOptimal tone scale mapping in electronic camerasUS5541138Oct 28, 1993Jul 30, 1996Semiconductor Energy Laboratory Co., Ltd.Laser processing method, and method for forming insulated gate semiconductor deviceUS5569615Dec 14, 1994Oct 29, 1996Semiconductor Energy Laboratory Co., Ltd.Method for forming a flash memory by forming shallow and deep regions adjacent the gateUS5633519Jun 30, 1994May 27, 1997Semiconductor Energy Laboratory Co., Ltd.Non-volatile floating gate semiconductor deviceUS5642129Mar 23, 1994Jun 24, 1997Kopin CorporationFor displaying an image from a video sourceUS5643826Oct 25, 1994Jul 1, 1997Semiconductor Energy Laboratory Co., Ltd.Disposing crystallization promoting solution containing specified element in contact with amorphous silicon film on substrate, crystallizing by heatingUS5648277Nov 2, 1994Jul 15, 1997Semiconductor Energy Laboratory Co., Ltd.Performing ion introduction for forming impurity regions using the gate electrode and extensions of gate insulating film as mask; varying conditions of introduction in order to control concentrationUS5666159 *Apr 24, 1995Sep 9, 1997Eastman Kodak CompanyElectronic camera system with programmable transmission capabilityUS5705829Jan 26, 1996Jan 6, 1998Semiconductor Energy Laboratory Co., Ltd.Semiconductor device formed using a catalyst element capable of promoting crystallizationUS5753544Jul 7, 1995May 19, 1998Lg Semicon Co., Ltd.Crystallization process and method of manufacturing thin film transistor using sameUS5784129Dec 14, 1995Jul 21, 1998Semiconductor Energy Laboratory Company, Ltd.Electro-optical apparatus utilizing electro-optical modulating devices to provide a synthesized color imageUS5789292Aug 7, 1996Aug 4, 1998Semiconductor Energy Laboratory Co., Ltd.Laser processing method, method for forming a flash memory, insulated gate semiconductor device and method for forming the sameUS5789762Sep 12, 1995Aug 4, 1998Semiconductor Energy Laboratory Co., Ltd.Semiconductor active matrix circuitUS5793344Mar 21, 1995Aug 11, 1998Koyama; JunSystem for correcting display device and method for correcting the sameUS5818083Mar 27, 1997Oct 6, 1998Fujitsu LimitedSemiconductor memory device having a floating gateUS5847411Apr 10, 1997Dec 8, 1998Matsushita Electric Industrial Co., Ltd.Semiconductor device having a channel region including a vacancy-introduced polysilicon layerUS5895935 *Apr 24, 1997Apr 20, 1999Semiconductor Energy Laboratory Co., Ltd.Display device having a switch with floating regions in the active layerUS5923962Apr 28, 1995Jul 13, 1999Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing a semiconductor deviceUS5926562Jun 21, 1996Jul 20, 1999Fuji Photo Film Co., Ltd.Image processing method using reference values to determine exposure stateUS5933199Jun 3, 1996Aug 3, 1999Lg Electronics Inc.Gamma correction circuit using analog multiplierUS5962872Aug 7, 1997Oct 5, 1999Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for fabricating the sameUS5965915Apr 23, 1997Oct 12, 1999Semiconductor Energy Laboratory Co., Ltd.Laser processing method, method for forming a flash memory, insulated gate semiconductor device and method for forming the sameUS5977562Nov 14, 1996Nov 2, 1999Semiconductor Energy Laboratory Co., Ltd.Electro-optical deviceUS5982427Feb 12, 1996Nov 9, 1999Innovation Tk Ltd.Digital image processingUS5982462 *Mar 6, 1997Nov 9, 1999Frontec IncorporatedInverse stagger or planar type thin-film transistor device and liquid-crystal display apparatus having floating gate electrode which is capacitively coupled with one or more input electrodesUS6006313Jun 6, 1996Dec 21, 1999Sharp Kabushiki KaishaSemiconductor memory device that allows for reconfiguration around defective zones in a memory arrayUS6093937Feb 19, 1997Jul 25, 2000Semiconductor Energy Laboratory Co. Ltd.Semiconductor thin film, semiconductor device and manufacturing method thereofUS6128648Nov 23, 1994Oct 3, 2000International Business Machines CorporationInformation handling system and method for maintaining coherency between network servers and mobile terminalsUS6140667Feb 20, 1998Oct 31, 2000Semiconductor Energy Laboratory Co., Ltd.Semiconductor thin film in semiconductor device having grain boundariesUS6160271Feb 1, 2000Dec 12, 2000Semiconductor Energy Laboratory Co., Ltd.Semiconductor thin film and semiconductor deviceUS6268617May 24, 1999Jul 31, 2001Semiconductor Energy Laboratory Co., Ltd.Electro-optical deviceUS6285042Sep 12, 1997Sep 4, 2001Semiconductor Energy Laboratory Co., Ltd.Active Matry DisplayUS6335541Apr 15, 1996Jan 1, 2002Semiconductor Energy Laboratory Co., Ltd.Semiconductor thin film transistor with crystal orientationUS6335716Aug 31, 1998Jan 1, 2002Semiconductor Energy Laboratory Co., Ltd.Semiconductor display device correcting system and correcting method of semiconductor display deviceJPH0878329A Title not availableJPH07130652A Title not availableJPH07135318A Title not availableJPH07321339A Title not availableJPH08148694A Title not availableJPH09238927A Title not availableJPH09240506A Title not availableJPH10132748A Title not availableJPH10132749A Title not availableJPH10161363A Title not availableJPH10161366A Title not availableJPH10294280A Title not availableJPH11345767A Title not availableJPH11354442A Title not available* Cited by examinerNon-Patent CitationsReference1English abstract re Japanese patent application No. 10-294280, published Nov. 4, 1998.2English abstract re Japanese patent application No. 11-345767, published Dec. 14, 1999.3English abstract re Japanese patent application No. 11-354442, published Dec. 10, 1998.4English abstract re Japanese patent application No. 7-130652, published May 19, 1995.5English abstract re Japanese patent application No. 8-078329, published Mar. 22, 1996.6English abstract re Japanesse patent application No. 7-135318, published May 23, 1995.7English abstract re Japanesse patent application No. 7-321339, published Dec. 8, 1995.8Shimokawa, R. et al, "Characterization of High-Efficiency Cast-Si Solar Cell Wafers By MBIC Measurement," Japanese Journal of Applied Physics, vol. 27, No. 5, pp. 751-758, May, 1988.9U.S. Patent Appliation Ser. No. 09/095,027 (pending) to Ohtani et al filed Jun. 9, 1998, including specification, claims, abstract, drawings, PTO filing receipt and allowed claims.10U.S. patent application No. 09/138,691 (pending) including specification, claims, drawings and officical filing receipt.11U.S. patent application No. 09/144,538 (pending) including specification, claims and drawings.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7038674Sep 25, 2002May 2, 2006Semiconductor Energy Laboratory Co., Ltd.Display device and method for driving the sameUS7126156 *Nov 3, 2003Oct 24, 2006Semiconductor Energy Laboratory Co., Ltd.Thin film transistor display device with integral control circuitryUS7126410 *Sep 2, 2003Oct 24, 2006Commissariat A L'energie AtomiqueCharge pump with charge injectionUS7339820 *May 15, 2003Mar 4, 2008Semiconductor Energy Laboratory Co., Ltd.Nonvolatile memory and semiconductor deviceUS7344926 *Nov 7, 2005Mar 18, 2008Lg. Philips Lcd Co., LtdLiquid crystal display device and method of manufacturing the sameUS7507995Jun 7, 2006Mar 24, 2009Semiconductor Energy Laboratory Co., Ltd.Semiconductor memory cell and semiconductor memory deviceUS7550790 *Feb 22, 2007Jun 23, 2009Semiconductor Energy Laboratory Co., Ltd.D/A conversion circuit and semiconductor deviceUS7596024Jul 12, 2007Sep 29, 2009Semiconductor Energy Laboratory Co., Ltd.Nonvolatile memoryUS7598565Aug 8, 2006Oct 6, 2009Semiconductor Energy Laboratory Co., Ltd.Semiconductor memory element, semiconductor memory device and method of fabricating the sameUS7750347Oct 19, 2006Jul 6, 2010Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and semiconductor display deviceUS7961515Aug 14, 2009Jun 14, 2011Semiconductor Energy Laboratory Co., Ltd.Nonvolatile memoryUS7995024Jun 8, 2010Aug 9, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS8187926 *Mar 12, 2007May 29, 2012Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing a semiconductor deviceUS8391060Feb 7, 2007Mar 5, 2013Semiconductor Energy Laboratory Co., Ltd.Nonvolatile memory and semiconductor deviceUS8492768Aug 23, 2012Jul 23, 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating the sameUS8564578Aug 3, 2011Oct 22, 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS8816347Jul 18, 2013Aug 26, 2014Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating the same* Cited by examinerClassifications U.S. Classification257/59, 257/72, 257/E27.111, 257/315, 257/E29.293, 257/E21.413International ClassificationH01L27/12, H01L21/84, H01L29/786, H01L21/336, G02F1/1362, H01L21/77Cooperative ClassificationH01L29/4908, H01L27/1296, H01L29/04, H01L29/66757, G09G2320/0276, G09G3/3696, G02F1/13454, H01L27/11546, H01L27/11526, G09G3/3688, H01L27/1277, H01L27/105, H01L29/78675European ClassificationH01L29/66M6T6F15A2, H01L27/12T30J, H01L29/04, H01L27/115F6, H01L27/12T30B2A, H01L27/115F6P2, H01L29/49B, H01L27/105, H01L29/786E4C2, G09G3/36C14ALegal EventsDateCodeEventDescriptionMay 25, 2011FPAYFee paymentYear of fee payment: 8Jun 4, 2007FPAYFee paymentYear of fee payment: 4Oct 8, 1998ASAssignmentOwner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAMAZAKI, SHUNPEI;KOYAMA, JUN;REEL/FRAME:009511/0543Effective date: 19981002RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services