Source: http://www.google.com/patents/US7928007?dq=5,963,646
Timestamp: 2014-03-10 06:20:24
Document Index: 489575472

Matched Legal Cases: ['Application No. 095110444', 'Application No. 200680015585', 'Application No. 200680015585', 'Application No. 095110444', 'Application No. 095110444', 'Application No. 200680015585', 'Application No. 095110444', 'Application No. 200680015585']

Patent US7928007 - Method for reducing dielectric overetch when making contact to conductive ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsIn a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second...http://www.google.com/patents/US7928007?utm_source=gb-gplus-sharePatent US7928007 - Method for reducing dielectric overetch when making contact to conductive featuresAdvanced Patent SearchPublication numberUS7928007 B2Publication typeGrantApplication numberUS 12/363,588Publication dateApr 19, 2011Filing dateJan 30, 2009Priority dateMar 25, 2005Also published asCN101189714A, CN101189714B, CN102683267A, EP1861874A2, US7521353, US8497204, US20060216931, US20090142921, US20110189840, US20130295764, WO2006104817A2, WO2006104817A3Publication number12363588, 363588, US 7928007 B2, US 7928007B2, US-B2-7928007, US7928007 B2, US7928007B2InventorsChristopher J. PettiOriginal AssigneeSandisk 3D LlcExport CitationBiBTeX, EndNote, RefManPatent Citations (61), Non-Patent Citations (22), Referenced by (8), Classifications (12) External Links: USPTO, USPTO Assignment, EspacenetMethod for reducing dielectric overetch when making contact to conductive featuresUS 7928007 B2Abstract In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4499557Jul 6, 1981Feb 12, 1985Energy Conversion Devices, Inc.Programmable cell for use in programmable electronic arraysUS4646266Sep 28, 1984Feb 24, 1987Energy Conversion Devices, Inc.Programmable semiconductor structures and methods for using the sameUS5244837Mar 19, 1993Sep 14, 1993Micron Semiconductor, Inc.Semiconductor electrical interconnection methodsUS5612254Jun 29, 1992Mar 18, 1997Intel CorporationMethods of forming an interconnect on a semiconductor substrateUS5915167Apr 4, 1997Jun 22, 1999Elm Technology CorporationThree dimensional structure memoryUS5926732Sep 20, 1996Jul 20, 1999Mitsubishi Denki Kabushiki KaishaMethod of making a semiconductor deviceUS5956618 *Mar 27, 1997Sep 21, 1999Lucent Technologies Inc.Process for producing multi-level metallization in an integrated circuitUS6008116 *Dec 18, 1997Dec 28, 1999Advanced Micro Devices, Inc.Selective etching for improved dielectric interlayer planarizationUS6034882Nov 16, 1998Mar 7, 2000Matrix Semiconductor, Inc.Vertically stacked field programmable nonvolatile memory and method of fabricationUS6072237Sep 30, 1998Jun 6, 2000Taiwan Semiconductor Manufacturing CompanyBorderless contact structureUS6162722May 17, 1999Dec 19, 2000United Microelectronics Corp.Unlanded via processUS6258712Feb 1, 1999Jul 10, 2001Taiwan Semiconductor Manufacturing Co., Ltd.Method for forming a borderless contactUS6313018 *Feb 16, 2000Nov 6, 2001Advanced Micro Devices, Inc.Process for fabricating semiconductor device including antireflective etch stop layerUS6329118 *Oct 21, 1999Dec 11, 2001Intel CorporationMethod for patterning dual damascene interconnects using a sacrificial light absorbing materialUS6395639Sep 16, 1999May 28, 2002Agere Systems Guardian CorporationProcess for improving line width variations between tightly spaced and isolated features in integrated circuitsUS6472308 *Sep 7, 2001Oct 29, 2002Advanced Micro Devices, Inc.Borderless vias on bottom metalUS6544887 *Mar 31, 2000Apr 8, 2003Lam Research CorporationPolycide etch processUS6856572Nov 27, 2002Feb 15, 2005Matrix Semiconductor, Inc.Multi-headed decoder structure utilizing memory array line driver with dual purpose driver deviceUS6879505Mar 31, 2003Apr 12, 2005Matrix Semiconductor, Inc.Word line arrangement having multi-layer word line segments for three-dimensional memory arrayUS6881994Aug 13, 2001Apr 19, 2005Matrix Semiconductor, Inc.Monolithic three dimensional array of charge storage devices containing a planarized surfaceUS6918821Nov 12, 2003Jul 19, 2005Dow Global Technologies, Inc.Materials and methods for low pressure chemical-mechanical planarizationUS6946719Dec 3, 2003Sep 20, 2005Matrix Semiconductor, IncSemiconductor device including junction diode contacting contact-antifuse unit comprising silicideUS6952030May 26, 2004Oct 4, 2005Matrix Semiconductor, Inc.High-density three-dimensional memory cellUS7005350Dec 31, 2002Feb 28, 2006Matrix Semiconductor, Inc.Method for fabricating programmable memory array structures incorporating series-connected transistor stringsUS7063597Oct 24, 2003Jun 20, 2006Applied MaterialsPolishing processes for shallow trench isolation substratesUS7172840Dec 5, 2003Feb 6, 2007Sandisk CorporationPhotomask features with interior nonprinting window using alternating phase shiftingUS7176064Sep 29, 2004Feb 13, 2007Sandisk 3D LlcMemory cell comprising a semiconductor junction diode crystallized adjacent to a silicideUS7224013Sep 29, 2004May 29, 2007Sandisk 3D LlcJunction diode comprising varying semiconductor compositionsUS7233024Mar 31, 2003Jun 19, 2007Sandisk 3D LlcThree-dimensional memory device incorporating segmented bit line memory arrayUS7285464Dec 17, 2004Oct 23, 2007Sandisk 3D LlcNonvolatile memory cell comprising a reduced height vertical diodeUS7422985 *Mar 25, 2005Sep 9, 2008Sandisk 3D LlcMethod for reducing dielectric overetch using a dielectric etch stop at a planar surfaceUS7423304Dec 5, 2003Sep 9, 2008Sandisck 3D LlcOptimization of critical dimensions and pitch of patterned features in and above a substrateUS7474000Dec 5, 2003Jan 6, 2009Sandisk 3D LlcHigh density contact to relaxed geometry layersUS7505321Dec 31, 2002Mar 17, 2009Sandisk 3D LlcProgrammable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of sameUS7521353Mar 25, 2005Apr 21, 2009Sandisk 3D LlcMethod for reducing dielectric overetch when making contact to conductive featuresUS20030057457Dec 6, 2001Mar 27, 2003Kabushiki Kaisha ToshibaSemiconductor device having buried conductive layer and method of manufacturing thereofUS20030109123Dec 27, 2002Jun 12, 2003Toshiyuki OritaMethod of forming a via hole in a semiconductor deviceUS20040142640Oct 24, 2003Jul 22, 2004Applied Materials, Inc.Polishing processes for shallow trench isolation substratesUS20040214425Apr 22, 2003Oct 28, 2004Taiwan Semicondutor Manufacturing Co.Atomic layer deposited tantalum nitride layer to improve adhesion between a copper structure and overlying materialsUS20050012119May 26, 2004Jan 20, 2005Matrix SemiconductorMethod for making high density nonvolatile memoryUS20050012120May 26, 2004Jan 20, 2005Matrix SemiconductorMethod for making high density nonvolatile memoryUS20050012154May 26, 2004Jan 20, 2005Matrix SemiconductorMethod for making high density nonvolatile memoryUS20050012220May 26, 2004Jan 20, 2005Matrix SemiconductorContacts for an improved high-density nonvolatile memoryUS20050014322 *May 26, 2004Jan 20, 2005Matrix SemiconductorMethod for making high density nonvolatile memoryUS20050014334May 26, 2004Jan 20, 2005Matrix SemiconductorMethod for making high density nonvolatile memoryUS20050029664 *Sep 2, 2004Feb 10, 2005Won-Seok ChoUnitary interconnection structures integral with a dielectric layer and fabrication methods thereofUS20050052915Sep 29, 2004Mar 10, 2005Matrix Semiconductor, Inc.Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance statesUS20050079706 *Oct 14, 2003Apr 14, 2005Kaushik KumarDual damascene structure and methodUS20050130352Dec 3, 2004Jun 16, 2005Infineon Technologies North America Corp.High density DRAM with reduced peripheral device area and method of manufactureUS20050167758 *Feb 9, 2005Aug 4, 2005Tae-Hyuk AhnSemiconductor memory device having self-aligned contacts and method of fabricating the sameUS20050168914 *Jan 30, 2004Aug 4, 2005Taiwan Semiconductor Manufacturing Co.Integrated capacitorUS20050221200Apr 1, 2004Oct 6, 2005Matrix Semiconductor, Inc.Photomask features with chromeless nonprinting phase shifting windowUS20060067117Sep 29, 2004Mar 30, 2006Matrix Semiconductor, Inc.Fuse memory cell comprising a diode, the diode serving as the fuse elementUS20060128153 *Dec 14, 2004Jun 15, 2006Matrix Semiconductor, Inc.Method for cleaning slurry particles from a surface polished by chemical mechanical polishingUS20060216926 *Jun 12, 2006Sep 28, 2006Applied Materials, Inc.Method of fabricating a dual damascene interconnect structureUS20060216937 *Mar 25, 2005Sep 28, 2006Matrix Semiconductor, Inc.Method for reducing dielectric overetch using a dielectric etch stop at a planar surfaceUS20080254615Oct 25, 2007Oct 16, 2008Dunton Samuel VMethod for reducing dielectric overetch using a dielectric etch stop at a planar surfaceUS20100297834Aug 3, 2010Nov 25, 2010Dunton Samuel VMethod for reducing dielectric overetch using a dielectric etch stop at a planar surfaceTW511233B Title not availableWO1999016118A1Aug 28, 1998Apr 1, 1999Advanced Micro Devices IncProcess for fabricating semiconductor device including antireflective etch stop layerWO2004061851A2Dec 12, 2003Jul 22, 2004Matrix Semiconductor IncAn improved method for making high-density nonvolatile memory* Cited by examinerNon-Patent CitationsReference1Helm, et al, "A Low Cost, Microprocessor Compatible, 18.4 um2, 6-T Bulk Cell Technology for High Speed SRAMs", in VLSI Technology Symposium Proceedings, 1993.2Herner, S. Brad, U.S. Appl. No. 10/326,470, filed Dec. 19, 2002 (abandoned during examination).3International Preliminary Report on Patentability of International Application No. PCT/US2006/010520 issued Sep. 25, 2007.4International Search Report and Written Opinion of International Application No. PCT/US2006/010520 mailed Sep. 6, 2006.5Koga et al., "Two-Dimensional Borderless Contact Pad Technology for a 0.135 um2 4-Gigabit DRAM Cell," in IEDM Tech. Digest, 1997, pp. 25-28.6Norishima et al., "Fully Integrated Multilevel Interconnect Process for Sub-Half-Micron ASIC Applications," in VLSI Technology Symposium Proceedings, 1995, pp. 47-49.7Notice of Allowance of U.S. Appl. No. 11/089,771 mailed Dec. 12, 2008.8Notice of Allowance of U.S. Appl. No. 11/089,771 mailed Jul. 7, 2008.9Notice of Allowance of U.S. Appl. No. 11/089,771 mailed Sep. 11, 2007.10Nov. 27, 2009 Reply to Office Action of Taiwan Application No. 095110444 issued May 27, 2009.11Office Action of China Application No. 200680015585.8 dated Feb. 6, 2009.12Office Action of China Patent Application No. 200680015585.8, dated Jul. 17, 2009.13Office Action of Taiwan Application No. 095110444 issued Jul. 21, 2008.14Office Action of Taiwan Application No. 095110444 issued May 27, 2009.15Office Action of U.S. Appl. No. 11/089,771 mailed Mar. 20, 2007.16Office Action of U.S. Appl. No. 11/089,771 mailed Nov. 19, 2007.17Reply to Feb. 6, 2009 Office Action of China Application No. 200680015585.8.18Reply to Jul. 21, 2008 Office Action of Taiwan Application No. 095110444.19Reply to Mar. 20, 2007 Office Action of U.S. Appl. No. 11/089,771.20Reply to Nov. 19, 2007 Office Action of U.S. Appl. No. 11/089,771.21Sep. 17, 2009 Reply to Jul. 17, 2009 Office Action of China Patent Application No. 200680015585.8.22Subbanna et al., "A Novel Borderless Contact/Interconnect Technology Using Aluminum Oxide Etch Stop for High Performance SRAM and Logic", IEDM Tech. Digest, 1993, pp. 441-444.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8372743 *Mar 1, 2012Feb 12, 2013Texas Instruments IncorporatedHybrid pitch-split pattern-split lithography processUS8461038 *Mar 1, 2012Jun 11, 2013Texas Instruments IncorporatedTwo-track cross-connects in double-patterned metal layers using a forbidden zoneUS8497204 *Apr 15, 2011Jul 30, 2013Sandisk 3D LlcMethod for reducing dielectric overetch when making contact to conductive featuresUS8575020 *Mar 1, 2012Nov 5, 2013Texas Instruments IncorporatedPattern-split decomposition strategy for double-patterned lithography processUS20110189840 *Apr 15, 2011Aug 4, 2011Petti Christopher JMethod for reducing dielectric overetch when making contact to conductive featuresUS20120225550 *Mar 1, 2012Sep 6, 2012Texas Instruments IncorporatedHybrid pitch-split pattern-split lithography processUS20120225551 *Mar 1, 2012Sep 6, 2012Texas Instruments IncorporatedPattern-split decomposition strategy for double-patterned lithography processUS20120225552 *Mar 1, 2012Sep 6, 2012Texas Instruments IncorporatedTwo-track cross-connects in double-patterned metal layers using a forbidden zone* Cited by examinerClassifications U.S. Classification438/645, 438/638, 257/E21.576International ClassificationH01L21/4763Cooperative ClassificationH01L21/76802, H01L23/5252, H01L21/76829, H01L21/768, H01L21/76801European ClassificationH01L21/768B2, H01L21/768B, H01L21/768B10RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google