Source: https://patents.google.com/patent/US8826101B2/en
Timestamp: 2019-07-16 11:34:46
Document Index: 774081182

Matched Legal Cases: ['Application No. 200980128341', 'Application No. 2011', 'Application No. 09800787', 'Application No. 09774012', 'Application No. 13157772', 'Application No. 20098012573', 'Application No. 10', 'Application No. 10', 'Application No. 1020117002671', 'Application No. 2011', 'Application No. 2011', 'Application No. 2011', 'Application No. 10', 'Application No. 200980125792', 'Application No. 10', 'Application No. 098121258', 'Application No. 10', 'Application No. 200980125792', 'Application No. 200980128341', 'Application No. 098114848', 'Application No. 098120886', 'Application No. 098124606']

US8826101B2 - Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system - Google Patents
US8826101B2
US8826101B2 US14/028,134 US201314028134A US8826101B2 US 8826101 B2 US8826101 B2 US 8826101B2 US 201314028134 A US201314028134 A US 201314028134A US 8826101 B2 US8826101 B2 US 8826101B2
US14/028,134
US20140053040A1 (en
2013-09-16 Application filed by Micron Technology Inc filed Critical Micron Technology Inc
2013-09-16 Priority to US14/028,134 priority patent/US8826101B2/en
2014-02-20 Publication of US20140053040A1 publication Critical patent/US20140053040A1/en
2014-09-02 Publication of US8826101B2 publication Critical patent/US8826101B2/en
This application is a continuation of U.S. patent application Ser. No. 13/371,045, filed Feb. 10, 2012, which is a continuation of U.S. patent application Ser. No. 12/192,796, filed Aug. 15, 2008, issued as U.S. Pat. No. 8,127,204 on Feb. 28, 2012. These applications and patent are incorporated by reference herein in their entirety and for all purposes.
a bus including a plurality of signal lines configured to transmit; and
a controller configured to serially provide a plurality of portions of data to the bus, a portion of data of the plurality of portions of data having fewer bits than a number of the plurality of signal lines of the bus, wherein the controller is further configured to provide additional information to the plurality of signal lines of the bus not utilized by the portion of data of the plurality of portions of data in parallel with the portion of the data of the plurality of portions of data.
a receiver configured to, in a plurality of data bursts, receive a plurality of data bits and further receive a plurality of additional bits related to the plurality of data bits;
a first plurality of interconnects configured to, in the plurality of data bursts, provide the plurality of data bits to the receiver; and
a second plurality of interconnects configured to, in the plurality of data bursts, provide the plurality of additional bits to the receiver, wherein a count of the plurality of additional bits is less than or equal to a product of a count of the plurality of data bursts and a count of the second plurality of interconnects, wherein the plurality of additional bits include received error correcting bits and data bus inversion bits.
10. The apparatus of claim 8, wherein the receiver comprises a serial to parallel converter that is configured to deserialize the additional bits into the received error correcting bits and the data bus inversion bits.
serially providing a plurality of data bursts to a data bus, the data bus comprising a plurality of signal lines, and at least one data burst of the plurality of data bursts utilizing less than all of the signal lines of the data bus; and
providing, in parallel with the at least one burst, additional information to the signal lines of the data bus not utilized by the at least one data burst.
US14/028,134 2008-08-15 2013-09-16 Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system Active US8826101B2 (en)
US13/371,045 Continuation US8539312B2 (en) 2008-08-15 2012-02-10 Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system
US20140053040A1 US20140053040A1 (en) 2014-02-20
US8826101B2 true US8826101B2 (en) 2014-09-02
CN101036131B (en) 2004-11-22 2011-01-26 英特尔公司 Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding
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First Examination Report dated Feb. 21, 2013 received for EP 09800787.5.
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Notice of Preliminary Rejection dated Mar. 21, 2013 for KR Application No. 10-2011-7002671.
Notice of Preliminary Rejection dated Sep. 24, 2012 for KR Application No. 1020117002671.
Notice of Rejection dated Jun. 25, 2013 for JP Application No. 2011-520079.
Office Action dated Feb. 12, 2013 received for JP Application No. 2011-520079.
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Office Action dated Jun. 14, 2013 for KR Application No. 10-2013-7010171.
Office Action dated Nov. 2, 2012 for CN Application No. 200980125792.2.
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Office Action for TW Application No. 098121258 issued Dec. 2, 2013.
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Second Office Action for CN Application No. 200980128341.4; Issued Nov. 19, 2013.
Taiwanese Search Report dated Mar. 11, 2013 for TW Application No. 098114848.
TW First Office Action and Search Report dated Apr. 24, 2013 for TW Application No. 098120886.
TW Office Action dated May 9, 2013 for TW Application No. 098124606.
US8539312B2 (en) 2013-09-17
US20010042163A1 (en) 2001-11-15 Ram controller interface device for ram compatibility