Source: https://patents.google.com/patent/US20060161745A1/en
Timestamp: 2018-07-20 11:37:07
Document Index: 720330485

Matched Legal Cases: ['Application No. 2004', 'Application No. 2004', 'Application No. 2001', 'Application No. 2004', 'Application No. 2004', 'Application No. 2001']

US20060161745A1 - Methods of operating memory systems including memory devices set to different operating modes and related systems - Google Patents
US20060161745A1
US20060161745A1 US11315470 US31547005A US2006161745A1 US 20060161745 A1 US20060161745 A1 US 20060161745A1 US 11315470 US11315470 US 11315470 US 31547005 A US31547005 A US 31547005A US 2006161745 A1 US2006161745 A1 US 2006161745A1
US11315470
US7369445B2 (en )
The present application claims the benefit of priority as a Continuation-In-Part application of U.S. patent application Ser. No. 10/916,156 filed on Aug. 11, 2004, which claims the benefit of priority as a Continuation-In-Part application of U.S. patent application Ser. No. 10/199,857 filed on Jul. 19, 2002. In addition, the present application claims the benefit of priority from Korean Application No. 2004-0112199 filed Dec. 24, 2004; U.S. patent application Ser. No. 10/916,156 claims the benefit of priority from Korean Application No. 2004-0032500 filed May 8, 2004; and U.S. patent application Ser. No. 10/199,857 claims the benefit of priority from Korean Application No. 2001-0043789 filed Jul. 20, 2001. The present application thus claims the benefit of priority from U.S. patent application Ser. No. 10/916,156, U.S. patent application Ser. No. 10/199,857, Korean Application No. 2004-0112199, Korean Application No. 2004-0032500, and Korean Application No. 2001-0043789, and the disclosures of all of the above referenced U.S. and Korean Patent Applications are hereby incorporated herein in their entirety by reference.
Accordingly, the memory devices M1, M5, and M9 generate first, fifth, and ninth internal clock signals ICLK1, ICLK5, and ICLK9, at different times, respectively. In FIG. 3, the first internal clock signal ICLK1 may be generated earlier than the fifth internal clock signal ICLK5 by a period 4 T, and the fifth internal clock signal ICLK5 may be generated earlier than the ninth internal clock signal ICLK9 by a period 4 T.
In contrast, a clock/command/address bus 112 may couple control/address signals CA and a system clock signal CK from the memory controller 100 to each of the memory devices 300M1-300M9. Accordingly, a length of the transmission line for the clock signal CK may be different for each of the memory devices 300M1-300M2 so that a propagation delay of the clock signal CK may vary for each of the memory devices 300M1-300M9. If the memory devices 300M1-300M9 are evenly spaced along the control/address/clock bus 112, the clock signal CK may experience an incremental propagation delay T (also referred to as a phase difference or phase shift) for each memory device 300M1-300M9 in the memory module 200. Arbitrarily assigning a propagation delay of 0 for the first memory device 300M1, for example, the clock signal CK propagation delay of T may result at second memory device 300M2, a propagation delay of 2 T may result at memory device 300M3, a propagation delay of 3 T may result at memory device 300M4, a propagation delay of 4 T may result at memory device 300M5, a propagation delay of 5 T may result at memory device 300M6, a propagation delay of 6 T may result at memory device 300M7, a propagation delay of 7 T may result at memory device 300M8, and a propagation delay of 8 T may result at memory device 300M9. The arrangement of FIG. 5 with the clock signal CK being provided to each of the memory devices 300M1-300M9 may be referred to as providing a fly-by clock.
With nine different delay taps for the control unit 315, nine different timing commands MRS1-MRS9 may be provided to define the tap to be selected by the tap selection circuit 405 as illustrated, for example, in FIG. 7B. Moreover, a four bit code may be provided over four predetermined address lines of the clock/command/address bus 112 during a selective mode register set operation to define the different timing commands MRS1-MRS9. For example, each of the delay circuits 401 a-h may provide an advance/delay T approximately equal to a difference in a propagation delay of a system clock signal CK between adjacent memory devices along a clock/command/address bus 112. With reference to FIGS. 7A and 7B, timing command MRS1 may provide a relative delay +4 T of the internal clock signal iCLK by selecting a tap at the output of delay circuit 401 h; timing command MRS2 may provide a relative delay +3 T of the internal clock signal iCLK by selecting a tap at the output of delay circuit 401 g; timing command MRS3 may provide a relative delay +2 T of the internal clock signal iCLK by selecting a tap at the output of delay circuit 401 f; timing command MRS4 may provide a relative delay +1 T of the internal clock signal iCLK by selecting a tap at the output of delay circuit 401 e; timing command MRS5 may provide a reference or default (0 advance or delay) for the internal clock signal iCLK by selecting a tap at the output of delay circuit 401 d; timing command MRS6 may provide a relative advance −1 T of the internal clock signal iCLK by selecting a tap at the output of delay circuit 401 c; timing command MRS7 may provide a relative advance −2 T of the internal clock signal iCLK by selecting a tap at the output of delay circuit 401 b; timing command MRS8 may provide a relative advance −3 T of the internal clock signal iCLK by selecting a tap at the output of delay circuit 401 a; and timing command MRS9 may provide a relative advance −4 T of the internal clock signal iCLK by selecting a tap at the input of delay circuit 401 a.
During an nth mode register set operation Cn, an nth mode register set command MRSn may be applied over the clock/command/address bus 112, an enabling mode register set enable/disable signal IDn (logic level 0) may be applied to the nth memory device 300Mn, and disabling mode register set enable/disable signals ID1-ID(n-1) (logic level 1) may be applied to the memory devices 300M1-300M(n-1). Accordingly, the nth mode register set operation Cn may provide delay adjustment for an internal clock signal iCLKn of memory device 300Mn.
During an nth selective mode register set operation Cn, an nth selective mode register set command MRSn may be applied over the clock/command/address bus 112, an enabling mode register set enable/disable signal IDn may be applied as DMn to the nth memory device 300Mn, and disabling mode register set enable/disable signals ID1-ID(n-1) may be applied as DM1-DM(n-1) to the memory devices 300M1-300M(n-1). Accordingly, the nth selective mode register set operation Cn may provide delay adjustment for an internal clock signal iCLKn of memory device 300Mn.
During an nth mode register set operation Cn, an nth mode register set command MRSn may be applied over the clock/command/address bus 112, an enabling mode register set enable/disable signal IDn may be applied as DQSn to the nth memory device 300Mn, and disabling mode register set enable/disable signals ID1-ID(n-1) may be applied as DQS1-DQS(n-1) to the memory devices 300M1-300M(n-1). Accordingly, the nth mode register set operation Cn may provide delay adjustment for an internal clock signal iCLKn of memory device 300Mn.
During an nth mode register set operation Cn, an nth mode register set command MRSn may be applied over the clock/command/address bus 112, an enabling mode register set enable/disable signal IDn may be applied as DQn to the nth memory device 300Mn, and disabling mode register set enable/disable signals ID1-ID(n-1) may be applied as DQ1-DQ(n-1) to the memory devices 300M1-300M(n-1). Accordingly, the nth mode register set operation Cn may provide delay adjustment for an internal clock signal iCLKn of memory device 300Mn.
As shown in FIG. 17, a clock/command/address bus 112B may enter the memory module 200B between memory devices in the row of memory devices 300M1-300M9, and the bus 112 may extend in opposite directions. Moreover, terminations 400B may be provided for the bus 112 at opposite ends of the row of memory devices 300M1-300M9. Each line of the bus 112 may thus be terminated using a pair of resistors, with a first resistor of the pair terminating the line at a first end of the row of memory devices and with a second resistor of the pair terminating the line at a second end of the row of memory devices. By providing that the bus is fed from approximately a center of the row of memory devices, a skew of the system clock signal received at different memory devices in the row can be reduced. In the example of FIG. 5, a transition of the system clock signal may be received at memory device 300M9 a period of time 8 T after the transition is received is received at memory device 300M1. Assuming an additional propagation delay of T for each memory device along the bus 112B of FIG. 17, a transition of the system clock signal may be received at memory device 300M1 a period of time 4 T after the transition is received at memory device 300M5. Accordingly, a maximum skew of the system clock signal received at different memory devices of module 200B may be reduced by a factor of approximately 2.
US11315470 2001-07-20 2005-12-22 Methods of operating memory systems including memory devices set to different operating modes and related systems Active 2023-05-27 US7369445B2 (en)
US20060161745A1 true true US20060161745A1 (en) 2006-07-20
US7369445B2 US7369445B2 (en) 2008-05-06
US11315470 Active 2023-05-27 US7369445B2 (en) 2001-07-20 2005-12-22 Methods of operating memory systems including memory devices set to different operating modes and related systems
US12058441 Abandoned US20080175071A1 (en) 2001-07-20 2008-03-28 Methods of Operating Memory Systems Including Memory Devices Set to Different Operating Modes
US20160116939A1 (en) * 2011-02-25 2016-04-28 Samsung Electronics Co., Ltd. Memory system and method of controlling same
US20030008327A1 (en) * 2001-06-26 2003-01-09 Olga Ornatskaia Methods and systems for identifying kinases, phosphatases, and substrates thereof
US9817434B2 (en) * 2011-02-25 2017-11-14 Samsung Electronics Co., Ltd. Memory system controlling peak current generation for a plurality of memories by synchronizing internal clock of each memory with a processor clock at different times to avoid peak current generation period overlapping
US7369445B2 (en) 2008-05-06 grant
US20080175071A1 (en) 2008-07-24 application