Source: http://www.google.com/patents/US7831871?dq=4168396
Timestamp: 2013-12-06 09:50:01
Document Index: 22537275

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'art 1100', 'art 1100', 'art 1200', 'art 1200']

Patent US7831871 - Testing embedded memories in an integrated circuit - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsVarious new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input...http://www.google.com/patents/US7831871?utm_source=gb-gplus-sharePatent US7831871 - Testing embedded memories in an integrated circuitPublication numberUS7831871 B2Publication typeGrantApplication numberUS 12/400,664Publication dateNov 9, 2010Filing dateMar 9, 2009Priority dateFeb 13, 2003Also published asUS7502976, US8209572, US20040190331, US20090172486, US20110145774, WO2004073041A2, WO2004073041A3Publication number12400664, 400664, US 7831871 B2, US 7831871B2, US-B2-7831871, US7831871 B2, US7831871B2InventorsDon E. Ross, Xiaogang Du, Wu-Tung Cheng, Joseph C. RayhawkOriginal AssigneeMentor Graphics CorporationPatent Citations (14), Non-Patent Citations (18), Referenced by (2), Classifications (12), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetTesting embedded memories in an integrated circuitUS 7831871 B2Abstract Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (�EDA�) software tool.
1. An apparatus used for testing an embedded memory in an integrated circuit, comprising:
a clocked element that inputs data from a data-input path and outputs data along a data-output path;
a primary multiplexer having a primary output coupled to the data-input path and two or more primary inputs coupled to at least a system-data path and a secondary-multiplexer path, respectively, the primary multiplexer being operable to selectively output at least system data or secondary-multiplexer data on the data-input path; and
a secondary multiplexer having a secondary output coupled to the secondary-multiplexer path and secondary inputs coupled to at least a scan-chain-data path and a memory-test-data path, the secondary multiplexer being operable to selectively output at least scan-chain data or memory-test data on the secondary-multiplexer path,
wherein the data-output path comprises input logic and is coupled to an input of an embedded memory that is not part of a scan chain path, and
wherein the memory-test-data path comprises compensatory logic and is coupled to an output of a memory built-in self-test (MBIST) controller, the compensatory input logic being configured to perform an inverse function of the input logic.
2. The apparatus of claim 1, wherein the clocked element is a flip-flop.
3. The apparatus of claim 1, wherein the clocked element comprises a part of a scan chain in the integrated circuit.
4. The apparatus of claim 1, wherein the primary multiplexer and the secondary multiplexer are two-input multiplexers.
5. The apparatus of claim 1, further comprising a two-input OR gate having a first input coupled to a memory-test enable signal, a second input coupled to a scan-chain enable signal, and an output coupled to a data-select input of the primary multiplexer.
6. The apparatus of claim 1, wherein the memory-test data is a constant value.
7. A computer-readable storage device storing computer-executable instructions which when executed will cause a computer system to perform a method, the method comprising:
modifying a design database to include circuit design information for embedded memory test circuitry, the circuit design information defining:
8. The computer-readable storage device of claim 7, wherein the clocked element is a flip-flop.
9. The computer-readable storage device of claim 7, wherein the clocked element comprises a part of a scan chain in the integrated circuit.
10. The computer-readable storage device of claim 7, wherein the primary multiplexer and the secondary multiplexer are two-input multiplexers.
11. The computer-readable storage device of claim 7, wherein the circuit design information further defines a two-input OR gate having a first input coupled to a memory-test enable signal, a second input coupled to a scan-chain enable signal, and an output coupled to a data-select input of the primary multiplexer.
12. The computer-readable storage device of claim 7, wherein the memory-test data is a constant value.
13. A computer-readable storage device storing a design database that comprises design information for an apparatus used for testing an embedded memory in an integrated circuit, the apparatus comprising:
14. A method for testing an embedded memory in an integrated circuit, comprising:
switching one or more sequential elements of the integrated circuit into a memory-test mode;
loading memory-test data into the one or more sequential elements from a memory-test controller located on the integrated circuit; and
outputting the memory-test data from the one or more sequential elements and into the embedded memory, wherein the one or more sequential elements are coupled to the embedded memory via one or more system paths, wherein the system paths are not part of a scan chain, and wherein at least one of the system paths comprises combinational logic.
15. The method of claim 14, wherein the act of loading the memory-test data includes performing a function on the memory-test data, the function compensating for a function performed along the one or more system paths.
16. The method of claim 14, wherein at least one of the sequential elements comprises a modified scan cell of a scan chain.
17. The method of claim 14, wherein at least one of the sequential elements is in a shadow register.
18. The method of claim 14, wherein at least one of the sequential elements comprises a modified system register.
19. The method of claim 14, wherein the one or more sequential elements are a plurality of sequential elements, wherein the one or more system paths are a plurality of system paths, and wherein at least one of the system paths is a direct path between an output of a respective one of the sequential elements and an input of the embedded memory.
20. The method of claim 14, wherein the one or more sequential elements are one or more input sequential elements, and wherein the system paths are one or more system-input paths, the method further comprising:
outputting memory-test responses from the embedded memory into one or more output sequential elements, wherein the one or more output sequential elements are coupled to the embedded memory via one or more observation paths.
outputting the memory-test responses from the one or more output sequential elements; and
receiving the memory-test responses in the memory-test controller.
22. The method of claim 21, wherein the act of outputting the memory-test responses comprises performing a function on the memory-test responses, the function compensating for a function performed along the one or more observation paths.
switching the one or more sequential elements of the integrated circuit into a scan-chain mode; and
loading test patterns for testing the integrated circuit into the one or more sequential elements from an external tester while operating in the scan-chain mode.
24. An integrated circuit comprising hardware configured to perform a method for testing an embedded memory in an integrated circuit, the method comprising:
25. The integrated circuit of claim 24, wherein the act of loading the memory-test data includes performing a function on the memory-test data, the function compensating for a function performed along the one or more system paths.
26. The integrated circuit of claim 24, wherein at least one of the sequential elements comprises a modified scan cell of a scan chain.
27. The integrated circuit of claim 24, wherein at least one of the sequential elements is in a shadow register.
28. The integrated circuit of claim 24, wherein at least one of the sequential elements comprises a modified system register.
29. The integrated circuit of claim 24, wherein the one or more sequential elements are a plurality of sequential elements, wherein the one or more system paths are a plurality of system paths, and wherein at least one of the system paths is a direct path between an output of a respective one of the sequential elements and an input of the embedded memory.
30. The integrated circuit of claim 24, wherein the one or more sequential elements are one or more input sequential elements, and wherein the system paths are one or more system-input paths, the method further comprising:
31. The integrated circuit of claim 30, wherein the method further comprises:
32. The integrated circuit of claim 31, wherein the act of outputting the memory-test responses comprises performing a function on the memory-test responses, the function compensating for a function performed along the one or more observation paths.
33. The integrated circuit of claim 24, wherein the method further comprises:
34. A computer-readable storage device storing computer-executable instructions which when executed will cause a computer system to design hardware configured to perform a method for testing an embedded memory in an integrated circuit, the method comprising:
35. The computer-readable storage device of claim 34, wherein the act of loading the memory-test data includes performing a function on the memory-test data, the function compensating for a function performed along the one or more system paths.
36. The computer-readable storage device of claim 34, wherein at least one of the sequential elements comprises a modified scan cell of a scan chain.
37. The computer-readable storage device of claim 34, wherein at least one of the sequential elements is in a shadow register.
38. The computer-readable storage device of claim 34, wherein at least one of the sequential elements comprises a modified system register.
39. The computer-readable storage device of claim 34, wherein the one or more sequential elements are a plurality of sequential elements, wherein the one or more system paths are a plurality of system paths, and wherein at least one of the system paths is a direct path between an output of a respective one of the sequential elements and an input of the embedded memory.
40. The computer-readable storage device of claim 34, wherein the one or more sequential elements are one or more input sequential elements, and wherein the system paths are one or more system-input paths, the method further comprising:
41. The computer-readable storage device of claim 40, wherein the method further comprises:
42. The computer-readable storage device of claim 41, wherein the act of outputting the memory-test responses comprises performing a function on the memory-test responses, the function compensating for a function performed along the one or more observation paths.
43. The computer-readable storage device of claim 34, wherein the method further comprises:
44. A computer-readable storage device storing a design database that comprises design information for hardware configured to perform a method for testing an embedded memory in an integrated circuit, the method comprising:
45. A system for testing an embedded memory in an integrated circuit, comprising:
means for switching one or more sequential elements of the integrated circuit into a memory-test mode;
means for loading memory-test data into the one or more sequential elements from a memory-test controller located on the integrated circuit; and
means for outputting the memory-test data from the one or more sequential elements and into the embedded memory, wherein the one or more sequential elements are coupled to the embedded memory via one or more system paths, wherein the one or more system paths are not part of a scan path, and wherein at least one of the system paths comprises combinational logic. Description
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional of U.S. application Ser. No. 10/779,205, filed Feb. 13, 2004 now U.S. Pat. No. 7,502,976, which claims the benefit of U.S. Provisional Application No. 60/447,583 filed Feb. 13, 2003, and claims the benefit of U.S. Provisional Application No. 60/512,278, filed Oct. 17, 2003, all of which are hereby incorporated herein by reference.
TECHNICAL FIELD This application relates to the testing of embedded memories in an integrated circuit using hardware that is built into the chip.
BACKGROUND In modern integrated-circuit design, embedded memories occupy a large, area of a chip. In microprocessors, for example, embedded memories can occupy more than 30% of the chip area, and in a system-on-a-chip (SoC), they can exceed 60%. The memory array is typically the densest physical structure on the chip and is usually made from the smallest geometry process features available.
SUMMARY Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. The disclosed exemplary apparatus and methods should not be construed as limiting in any way. Instead, the present disclosure is directed toward novel and non-obvious features and aspects of the various disclosed embodiments, alone and in various combinations and subcombinations with one another. The methods are not limited to any specific aspect, feature, or combinations thereof, nor do the disclosed methods require that any one or more specific advantages be present or problems be solved.
Another disclosed method for designing an MBIST architecture for testing an embedded memory in an integrated circuit comprises finding controlling paths from memory inputs of the embedded memory to one or more respective control points (where the control points comprise a modified scan cell or a modified system register), and synthesizing hardware that couples at least one of the control points to an associated output of a memory-test controller located on the integrated circuit. The act of finding the controlling paths can comprise sensitizing individual control paths to the memory inputs, and justifying applicable values to memory inputs that cannot be sensitized. In certain embodiments, the memory inputs that cannot be sensitized comprise unconstrained inputs or constrained/dependent inputs, and the memory inputs to which the applicable values are justified comprise the constrained/dependent inputs. In some embodiments, the act of synthesizing includes searching for connections between the hardware and the control points using functions that have as few variables as possible. Similarly, in some embodiments, the act of synthesizing includes minimizing the hardware by identifying two or more of the control points that can be coupled to a single respective output of the memory-test controller. For instance, the act of synthesizing might comprise inserting a fan-out from a single respective output of the memory-test controller to control two or more of the control points. In such an embodiment, placement of the fan-out can be delayed in order to reduce the area overhead of the hardware.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a conventional memory built-in self-test (MBIST) architecture.
DETAILED DESCRIPTION Disclosed below are representative embodiments of methods and apparatus for testing embedded memories in an integrated circuit using built-in self-test (BIST) hardware. Such hardware is collectively referred to as �memory BIST� or �MBIST.� Desirably, testing is performed at-speed and with less or none of the unnecessary delay that is introduced by conventional MBIST circuits. The disclosed methods and apparatus should not be construed as limiting in any way. Instead, the present disclosure is directed toward novel and nonobvious features and aspects of the various disclosed embodiments, alone and in various combinations and subcombinations with one another. Moreover, the methods and apparatus are not limited to any specific aspect or feature or combinations thereof, nor do the disclosed methods and apparatus require that any one or more specific advantages be present or problems be solved.
Although the operations of some of the disclosed methods and apparatus are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the attached figures may not show the various ways in which the disclosed methods and apparatus can be used in conjunction with other methods and apparatus. Additionally, the description sometimes uses terms like �determine� and �evaluate� to describe the disclosed methods. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.
As used herein, the term �register� refers generally to a sequential (or clocked) element. A sequential (or clocked) element is a circuit element that changes states at times specified by a free-running clock signal. Examples of sequential (or clocked) elements include flip-flops and latches.
To implement the exemplary architecture illustrated in FIG. 2 in a scan-based circuit design, one or more enhanced scan cells 300B as shown in FIG. 3( b) can be utilized. In particular, an enhanced scan cell 300B can be constructed by adding a secondary multiplexer 302B to a conventional scan cell, such as the scan cell 300A shown in FIG. 3( a). The secondary multiplexer 302B operates to select either scan-chain data in a scan-chain mode (i.e., data from an upstream scan cell or pin that is ordinarily transmitted along the scan-chain-data path (SI)) or memory-test data (i.e., data used to test the relevant embedded memory) from the memory-test-data path (MBI) in a memory-test (or MBIST) mode. As shown in FIG. 3( b), additional logic may be included to implement the enhanced scan cell 300B. For example, in FIG. 3(B), the MBIST-enable signal (MBE) and the scan-enable signal (SE) are coupled to a gate 306B, which implements an OR function. The output of the gate 306B is used as a select signal for a primary multiplexer 308B, which functions similarly to the multiplexer 308A in FIG. 3( a). The secondary multiplexer 302B in the illustrated embodiment uses the MBIST-enable signal (MBE) to select either the scan-chain-data path (SI) or the memory-test-data path (MBI). In the illustrated embodiment, then, if the scan cell 300B is in a system (or operation) mode, SE and MBE are desirably set to �0�; when the circuit is in a scan mode, MBE is desirably set to �0� and SE is desirably set to �1�; and when the circuit is in the memory-test mode, MBE is desirably set to �1� and SE is desirably set to �0�. These values should not be construed as limiting in any way, however, as the desired functionality and advantages of the disclosed architecture can be accomplished using architectures that operate with different values. All such variations, however, are considered to be within the scope of the present disclosure.
In certain embodiments, the scan-enable signal (SE) and the MBIST-enable signal (MBE) are prevented from both being set to �1� at the same time. Because the secondary multiplexer 302B and the gate 306B are not implemented along a system path, no extra delay is added to the existing system paths as a result of the new hardware. Consequently, the system mode (or system path) performance penalty experienced in the conventional MBIST architecture is eliminated.
Typically, not all of the scan cells in a circuit's scan chains need to be modified to implement the disclosed MBIST architecture. For example, in some designs, modifications to existing scan cells can be limited to only those scan cells that are used for testing the one or more embedded memories. Moreover, in some embodiments, the gate 306B used to OR the MBIST-enable signal (MBE) and the scan-enable signal (SE) may not be necessary. For example, FIG. 3( c) illustrates an embodiment of an enhanced scan cell 300C where the gate 306B is excluded. In FIG. 3( c), the scan-enable signal (SE) is controlled such that it selects the secondary-multiplexer path 303C during the appropriate times (i.e., during scan-chain mode and MBIST mode).
In still other embodiments, an enhanced scan cell is utilized in the disclosed MBIST architecture that propagates a constant value during MBIST mode. FIG. 3( f) shows one such exemplary scan cell 300F. Scan cell 300F is substantially similar to scan cell 300B described above, but inputs a constant value 310F (�0� or �1�) into the secondary multiplexer 302F, through the primary multiplexer 308F, and into the memory element 304F during memory-test (or MBIST) mode. As more fully explained below, such scan cells can be used, for example, to justify or sensitize input paths to the embedded memory.
The compensatory input logic 224 (G1) can be implemented using the following exemplary method. Assume for purposes of this exemplary method that the number of input variables into the compensatory input logic 224 (G1) is N and that the number of input variables into the input logic 216 (F1) is M. Typically, M is larger than N. To get test values V at the output of F1 from the output of the MBIST controller, in one desirable embodiment, F1 is reduced to a modified function F1′ having as few independent input variables as possible. In one exemplary embodiment, after the creation of F1′, the compensatory input logic 224 (G1) is created, desirably having the property that F1′�G1(V)=V. In this implementation, G1 is said to be the inverse of F1′ over the set of memory inputs.
For purposes of determining and implementing F1′, scan cells or primary inputs whose state change can possibly result in a state change at a memory input are referred to as �controlling points� or �control points� of the memory input. In general, controlling points are part of at least one path through the input logic 216 (F1) that leads to the corresponding memory input. Therefore, paths driven by controlling points are sometimes referred to as �controlling paths� or �control paths.�
FIG. 4 is a block diagram 400 illustrating the concept of controlling paths for two memory inputs 402, 404. In FIG. 4, the values �0� and �1� are justified backward from the first memory input 402 and the second memory input 404. As illustrated by the second memory input 404 in FIG. 4, there may exist more than one controlling point for a particular memory input. More specifically, the second memory input 404 can be controlled by controlling point 408 (scan cell b) and by controlling point 410 (scan cell c). Further, opposite values may be used at certain scan cells to produce the correct values at the corresponding memory input. For example, the first memory input 402 is controlled by controlling point 406 (scan cell a) and has a value of �0� and �1� when the controlling point generates �1� and �0,� respectively. Typically, there are many scan cells or combinations of scan cells that can be used to control a particular memory input. Moreover, some memory pins may block paths of other pins, while others will not. Accordingly, in one exemplary embodiment, a decision tree is maintained for each input pin of the embedded memory so that backtracking to the previous pin is easier when a pin cannot be justified (assuming that the current failure results from the wrong decision for one of the previous pins).
FIG. 5 is block diagram 500 illustrating how certain input variables may be set to a constant value such that the function F1 can be functionally reduced to a simplified function F1′. In the example shown in FIG. 5, if scan cell 502 (scan cell a) is set to �1� and scan cell 508 (scan cell e) to �1�, scan cells 504, 506, and 510 (scan cells b, d, and f, respectively) can individually control memory inputs 512, 514, and 516, respectively (memory inputs INP1, INP2, and INP3). Consequently, the circuit can be functionally reduced to the simplified circuit shown in FIG. 6. In particular, with scan cells 502 and 508 held constant, the input logic illustrated from FIG. 5 is reduced to an inverter 620 and a buffer 622. Moreover, each of the memory inputs 512, 514, and 516 can be controlled by exactly one scan cell through one controlling path.
As illustrated by the examples above, it is desirable in one exemplary embodiment to find and establish one controlling path from one control point to each respective memory input so that the memory inputs can be independently controlled. The process of finding a single controlling point and a single controlling path for a memory input is generally referred to as �sensitizing� a path for the memory input. The process of determining what values the off-path inputs should have in order to obtain the desired values along the sensitized path is generally referred to as �justifying� the sensitized path. Justifying also refers generally to the process of determining the input values necessary to propagate a certain value (e.g., a �0� or a �1�) to any memory input (even a memory input that cannot be sensitized to a single control path).
The controlling paths for a particular embedded memory can be found using a variety of different methods. For example, in one exemplary embodiment, the BACK algorithm is used. The BACK algorithm is described in W. T. Cheng, �The BACK Algorithm for Sequential Test Generation,� IEEE ICCD 1988, pp. 66-69. If there is a controlling path to a memory input, the path can be sensitized from the memory input back to the controlling point by setting the off-path inputs into the path to non-controlling values (i.e., justifying the path). For example, in the circuit illustrated by block diagram 800 in FIG. 8, a first memory input 802 and a second memory input 804 are sensitized to control points 812 and 814 along controlling paths 822 and 824, respectively. For the controlling path 822, off-path inputs 830, 832, and 834 are set such that they do not interfere with the value set at control point 812 (scan cell a). Similarly, for controlling path 824, off-path inputs 836 and 838 are set such that they do not interfere with the value set by control point 814 (scan cell f).
As was shown in FIG. 7, however, when a specific controlling path is sensitized for a memory input, the off-path values that are justified may interfere with controlling paths to other memory inputs. This can occur, for example, when the off-path values required for the sensitized path block controlling paths for other inputs, or when the on-path values for the chosen controlling path block controlling paths for other inputs when these values are implied. For this reason, when controlling paths are established, it is desirable to determine whether the controlling paths will block paths to other memory inputs. This process of determining the impact of a controlling path on other paths can be performed, for example, by propagating off-path values and controlling-path values to all possible gates. According to one exemplary embodiment, the evaluation can be performed for off-path values by implication, and for controlling-path values by simulation (e.g., simulating the on-path lines that will place a �0� and �1� on the controlled input of the memory). For example, a controlling-path value might be able to propagate through all gates of a controlling path so long as all other inputs of the gates are set to non-controlling values. Thus, if there is one input of a gate that is a control value for another controlling path, the two controlling paths cannot both be sensitized. In such cases, however, it may still be possible to justify a �0� or a �1� to both of the memory inputs using multiple control points to control the value being propagated to the memory input. For example, consider again the circuit shown in FIG. 7. When an attempt is made to sensitize a controlling path for the second memory input 710, it is observed that doing so would block the controlling path for the third memory input 712 because the off-path value used to select the proper input for the multiplexer 720 would be constant. In order to overcome this problem, an evaluation can be performed as to whether a �0� and �1� can be justified at all on the memory input 710. This evaluation may be performed using a variety of justification methods, but in one implementation, all possible combinations for justifying a �0� and a �1� to the memory input are searched and all successful combinations that can be used to set the memory input are stored. For example, for the circuit illustrated in FIG. 7, there are three possible settings that result in a �0� at the memory input 710: (1) set scan cells b and d to �0�; (2) set scan cell c to �0� and scan cell d to �1�; or (3) set scan cells b and c to �0.� The first two settings, however, block the path 732 to the third memory input 712, whereas the last setting does not. Thus, scan cells b and c can both be marked as controlling points for propagating a �0� to the second memory input 710 without interfering with other controlling paths. Similarly, a value of �1� can be justified on the second memory input 710 by setting scan cells b and c to �1.� Thus, the second memory input 710 can be set without blocking the path to the third memory input 712 by controlling both scan cells b and c. In one embodiment, scan cells b and c can thereafter be marked as being forbidden for inclusion in establishing controlling paths to any other memory input.
FIG. 9 shows pseudocode 900 for an exemplary method of sensitizing controlling path(s) from one or more memory inputs of a memory-under-test. The pseudocode 900 shows only one exemplary embodiment for sensitizing controlling path(s) and should not be construed as limiting in any way. The variable �back_track� in the pseudocode 900 is used to indicate whether the exemplary method is involved in reevaluating a pin already considered or whether the exemplary method is analyzing the pin for the first time. If the �back-track� variable is set, for example, a different path from the one previously considered is sensitized for the input, otherwise any available path is sensitized. According to the exemplary method shown in FIG. 9, once a controlling path is sensitized, the controlling point for the selected controlling path is forbidden from being used to justify any other controlling paths or to control any other memory inputs. Additionally, when it is not possible to sensitize a single controlling path, but is possible to justify a �0� or a �1� to a memory input, the scan cells used to propagate the values should not be set to opposite values during the relevant timeframes.
The process of implementing the logic at the output side of the memory-under-test is similar to that of implementing the logic at the input side. For example, if there exists one or more paths from a memory output to a scan cell or primary output, this scan cell (or primary output) can be defined as an �observing point� or �observation point,� and the path from the memory output to its observing point can be defined as an �observing path� or �observation path.�
According to one exemplary embodiment (and with reference to FIG. 2), it is desirable to reduce output logic 218, which performs a function F2, to logic that performs a modified function F2′ and has the simplest form possible. For example, the output logic 218 (F2) can be reduced to comprise mostly or only buffers and/or inverters. This reduction can be achieved, for example, by specifying some input variables to the output logic 218 (F2) as constant. According to one exemplary embodiment, after the creation of F2′, the function of the complementary output logic 226 (G2) desirably has the property that F2′�G2(U)=U. In these embodiments, G2 is said to be the inverse of F2′ over the set of memory outputs. As a result of the functions F2′ and G2, the proper output values U are received by the MBIST controller 204.
A procedure similar to the one for establishing controlling paths to memory inputs can be applied to sensitize observation paths for the memory outputs. For example, in one exemplary implementation, the nine-value D-Algorithm is used. One such algorithm is described at C. W. Cha, W. E. Donath, and F. Ozguner, �9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits,� IEEE Trans. Comput., vol. C-27, pp. 193-200 (1978). A decision tree can also be maintained for each output pin in order to facilitate backtracking. Thus, when an observation-path sensitization fails for a particular memory output, it is possible to back track to one or more of the previously considered memory outputs and to sensitize new observation paths for those memory outputs. Additionally, if observation paths are not found for all memory outputs, it may be a result of scan cells being set to justify controlling paths to the memory inputs. In such cases, the decision tree can be used to back track and resensitize the memory inputs.
An example of a fan-out architecture as may be used in the compensatory input logic is shown in FIG. 10. In FIG. 10, scan cells 1002 and 1004 (scan cells a and d) are used to control the memory input 1010 through input combinational logic 1020. In particular, when scan cell 1002 is �1� and scan cell 1004 is �0,� a value of �0� is produced at the memory input 1010; and when scan cell 1002 is �0� and scan cell 1004 is �1,� a value of �1� is produced. In order to correctly produce the desired values at the memory input 1010, the control values from the MBIST controller can be fanned out to both scan cells 1002 and 1004 and an inverter 1006 implemented.
FIG. 11 is a flowchart 1100 of a basic algorithm for implementing the input logic and compensatory input logic utilizing the concepts discussed above. The flowchart 1100 shows only one exemplary embodiment of implementing the input logic and the compensatory input logic and should not be construed as limiting in any way. At process block 1102, controlling paths to the memory inputs of the memory-under-test are sensitized. Any of the methods discussed above can be utilized to search for the controlling paths (e.g., the BACK algorithm or the process illustrated in FIG. 9). In one exemplary embodiment, all of the memory inputs are considered for sensitization. Thus, with reference to FIG. 2, this subprocess essentially reduces F1 to a modified function F1′ having as few independent input variables as possible. At process block 1104, a determination is made as to whether all of the memory inputs were successfully sensitized. If so, the process 1100 ends, otherwise the process continues at process block 1106. At process block 1106, the memory inputs that could not be sensitized are evaluated to see if the applicable values (usually �0� and �1�) can be justified on the failing memory inputs. As noted above, a variety of justification methods can be used, but in one implementation, all possible settings for justifying a �0� and a �1� to the relevant memory input are searched and all successful combinations that can be used to set the memory input are stored. The stored controlling points can then be evaluated to determine whether there is a set of controlling points that does not interfere with other controlling paths. At process block 1108, the compensatory input logic can be determined based on the controlling paths and controlling points found for the input logic. For example, in one implementation, the compensatory input logic is calculated to be the inverse of the input logic (e.g., with reference to FIG. 2, the compensatory input logic 224 (G1) is calculated such that F1′�G1(V)=V).
FIG. 12 is a flowchart 1200 showing a similar basic algorithm for implementing the output logic and compensatory output logic utilizing the concepts discussed above. The flowchart 1200 shows only one exemplary embodiment of implementing the output logic and the compensatory output logic and should not be construed as limiting in any way. At process block 1202, observation paths from the memory outputs of the memory-under-test are sensitized. Any of the methods-discussed above can be utilized to search for the observation paths (e.g., the nine-value D-Algorithm). In one exemplary embodiment, all of the memory outputs are considered for sensitization. Thus, with reference to FIG. 2, this process essentially involves reducing F2 to a modified function F2′ having as few observation paths as possible. At process block 1204, a determination is made as to whether all of the memory outputs were successfully sensitized. If so, the process 1200 ends, otherwise the process continues at process block 1206. At process block 1206, the memory outputs that could not be sensitized are evaluated to see if observation paths can be justified at all from the failing memory outputs. For example, multiple MBIST tests may be utilized wherein different memory outputs are observed during each test or a direct feed from the unobservable outputs into the MBIST controller may be utilized. At process block 1208, the compensatory output logic can be determined based on the observation paths and observation points found for the output logic. For example, in one implementation, the compensatory output logic is calculated to be the inverse of the output logic (e.g., with reference to FIG. 2, the compensatory output logic 226 (G2) is calculated such that F2′�G2(U)=U.)
Tie-value constraints exist when some inputs of a memory are tied to �0� or �1.� For example, the output-enable signal (OE) may be tied to �1,� or the most-significant bit (MSB) of data input may be tied to �0� or �1.� An incomplete-control-space constraint exists when not all combinations of the control signals are possible. For example, the write-enable (WEN) and read-enable (REN) signals of a memory usually cannot both be active at the same time. An incomplete-address-space constraint results when only a range of addresses can be present at the memory inputs. An address-scrambler constraint exists when an address scrambler of a particular design causes the address bits to not be independently controllable. A constrained output exists when one or more memory outputs have to be set to a certain value in order to observe other outputs. This type of output is referred to herein as a �type-1 constrained output.� Dependency between different groups of memory inputs may also exist. For example, in some designs, a subset of address inputs may be used as data inputs, and data outputs may have some dependency with some control inputs. This type of output is referred to herein as a �type-2 constrained output.� Dependency between different memory ports in a multi-port memory may also exist. For example, in some designs, two ports cannot be written at the same time.
At process block 1302 (�phase 1�), memory pins tied to a particular value (i.e., a �0� or a �1�) or directly connected to other pins are disregarded or removed from the input analysis, as these pins cannot be controlled independently. However, additional output logic may result if, for example, a tied data input's corresponding data output is connected to system logic. Typically, it will be unconnected, and the memory can be treated as having one less data pin on both its input and output ports. In certain unusual circumstances, the MBIST controller comparison values and/or sequences may have to be modified to compensate for the effects of memory-input logic constraints on expected memory outputs.
At process block 1304 (�phase 2�), one of the basic algorithms discussed above is utilized to try to sensitize controlling paths and observing paths for the memory pins (e.g., the BACK algorithm for controlling paths and the nine-value D-algorithm for observation paths).
At process block 1308 (�phase 3�), the failing pins or groups of pins are identified and classified. This identification and classification process can be performed by applying the basic sensitizing algorithm to each group of pins individually. From this process, the memory inputs can be classified as either �constrained inputs� or �unconstrained inputs.� In general, the memory inputs that fail the basic sensitizing algorithm when it is applied to the memory inputs individually can be classified as constrained inputs. The inputs that pass the basic algorithm when it is applied individually, but are found to be dependent on another group of memory pins, can be classified as unconstrained inputs. For the unconstrained inputs, a determination can be made as part of process block 1308 to identify the input pin groups that cannot be simultaneously controlled, as there exists a dependency between the groups. These unconstrained input pins can be further classified as �dependent inputs.� The remaining unconstrained input pins can be classified as �independent inputs.� The memory outputs that cannot be sensitized using the basic algorithm can also be evaluated and classified as being constrained by either a type-1 output constraint or a type-2 output constraint.
At process block 1310 (�phase 4�), independent paths are found for the unconstrained, independent inputs using the basic sensitizing algorithm, and/or all applicable values are justified for the constrained inputs and dependent inputs. In general, the applicable values are those values that are functionally useful. For example, only the address values �0� to �39� should be justified if only the addresses between �0� and �39� are to be used in functional operation. A memory with forty words, for instance, needs a 6-bit address, which has a range from 0 to 63. In this case, the potential range might be constrained by the input logic so that the memory will never see an illegal address. Because the MBIST controller will only generate addresses from 0 to 39, the justification process need only be performed for 0 to 39, and the unnecessary values can be skipped. Similarly, only the values (1, 0) and (0, 1) should be justified for the read-enable (REN) and write-enable (WEN) inputs of a memory where these inputs are implemented as complementary signals in the system control logic.
At process block 1314 (�phase 5�), the test patterns used to test the memory are justified to the memory inputs. In the exemplary method 1300, process block 1314 is used only if it is not possible to control any pin group independent of another pin group. In process block 1314, the test vectors used to test the memory are justified and inverse functions found using the same method of finding an inverse function described in the examples below. In the worst-case scenario, all possible test vectors will need to be justified. Typically, however, the number of test vectors that need to be justified is much smaller than the total number of possible test vectors. For example, a typical set of test vectors (e.g., from March algorithms) covers only a small fraction of the total possible patterns. Thus, according to one exemplary embodiment of the disclosed method, only those test vectors that will actually be used during testing are justified at process block 1314.
An exemplary application of the method 1300 is described below with respect to FIG. 14. For purposes of this example, �pin-vector� notation can be used. A pin vector (vv . . . v) denotes how a pin of the memory-under-test will be controlled or observed. Each value �v� in the pin vector corresponds to one respective pin of the embedded memory. The value of �v� can be �038�, �1�, �x�, or �I.� As used herein, �0� and �1� indicate that the corresponding pin will be set to �0� and �1,� respectively; �x� indicates that the corresponding pin is a �don't care� value; and �I� indicates that the pin is independently controlled or observed.
Suppose that an exemplary embedded memory has four address inputs (denoted as A[3:0]), four data inputs (denoted as D[3:0]), two control inputs (denoted as �REN� and �WEN�), and four data outputs (denoted as Q[3:0]). At process block 1302, the pins tied to a particular value or directly to another pin are removed. As there are no such pins in the exemplary memory, the process continues at process block 1304. At process block 1304, one of the basic algorithms is used to try to sensitize all the memory inputs and outputs such that they can be controlled and observed independently. The pin vector (IIII IIII II IIII), which indicates that such an algorithm has succeeded, can be used to denote the desired goal of process block 1304, where the pin vector corresponds to the values assigned respectively to (A[3:0] D[3:0] REN WEN Q[3:0]).
Assume that there exists a constraint such that the pins (REN WEN) can only be (0 0), (1 0) or (0 1). At process block 1306, a determination will be made that process block 1304 fails and the process will continue to process block 1308. At process block 1308, the constraint will be identified and classified as an incomplete-control-space constraint. At process block 1310, the pins vectors (IIII IIII 00 IIII), (IIII IIII 10 IIII), and (IIII IIII 01 IIII) will be able to be justified, which means that the address inputs A and the data inputs D can be controlled independently and the data outputs Q observed independently at the same time control inputs (REN WEN) are set for (0 0), (1 0), and (0 1). Because the control signals REN and WEN cannot be controlled independently, an inverse function for the control signals can be found and implemented as part of the compensatory input logic, if necessary. For instance, the exemplary architecture 1400 shown in FIG. 14 produces the following justification table for control inputs (REN WEN) over the justifiable combinations of their binary values:
SC1 SC2 0
From the justification table, it is possible to determine the equations for the compensatory input logic (G1 in FIG. 2) that connect the corresponding MBIST control outputs (specifically, MBISTREN and MBISTWEN) to scan cells SC1 and SC2. It should be remembered that G1 should desirably be synthesized in such a way that F1′�G1(V)=V. To accomplish this, the MBIST controller variable can be substituted for the corresponding memory variable in the table heading, and the justification table interpreted as a truth table with the scan cells (SCi in the table heading) as outputs. Justifications can be done consistently for any set of justifiable memory input values such that the justification table, when so interpreted, will define a function. For example, for FIG. 14, it can be observed from Table 1 that SCi=MBISTREN and SC2=MBISTWEN are the simplest equations consistent with the table, implying that G1 comprises two direct wires from the MBIST controller to the scan cell inputs, SC1 and SC2. Thus, with reference to FIG. 14, memory control signals (REN WEN) can be set to (0 0), (0 1), and (1 0) by setting the scan cells 1402 and 1404 (SC1 and SC2) to (0 0), (0 1), and (1 0), respectively.
If it is not possible to justify (IIII IIII 10 IIII) and (IIII IIII 01 IIII) due to some dependency between different pin groups, then the pin vector can be divided into two vectors. For example, the pin vectors (IIII xxxx 10 IIII) and (IIII IIII 01 xxxx) could be used based on the fact that the data inputs D[3:0] are essentially �don't cares� when the memory is being read (i.e., when REN and WEN are set to �1� and �0,� respectively) and the data outputs Q[3:0] are essentially �don't cares� when the memory is being written (i.e., when REN and WEN are set to �0� and �1,� respectively).
FIG. 15 illustrates another example of the justification process (as can occur at process blocks 1310 or 1314) and the process of synthesizing the hardware that couples the MBIST controller to the scan cells, which may include compensatory input logic. FIG. 15 shows a memory input M1 that is controllable by two scan chains 1502 and 1504 (SC1 and SC2, respectively), whose outputs are coupled via a two-input AND gate 1510. Assume that the memory input M1 has the values �0,� �1,� and �x� assigned to it in the associated test patterns. Assume also that a conventional MBIST controller is to be used such that the desired values for each memory input (Mi) correspond directly with the associated MBIST outputs (MBi) (that is, MBi=Mi). Assume also that SC1 is to be used consistently to control memory input M1. In this case, all patterns with M1=�1� require both SC1 and SC2 to be set to �1,� whereas patterns with M1=�0� will need SC1 set to �0� while SC2 does not matter. This result can be represented in the following justification table:
M1 SC1 SC2 1
In one embodiment, the hardware between the MBIST controller and the scan cells 1502, 1504, is synthesized using functions having as few variables as possible. According to one particular implementation of the method 1300, for instance, the justification process proceeds in the following order: (1) constants are considered for justifying the memory inputs; (2) single input variables are considered (the variables may be considered in some particular order (e.g., M1, M2, . . . , Mj) or at random); (3) complements of single variables are considered (possibly in the same order); (4) functions of two variables are considered; (5) complements of the functions of two variables are considered; and so on. In this implementation, this order can continue until all possibilities have been tried or until the memory inputs have been successfully justified.
Applying this exemplary implementation to the example illustrated in FIG. 15, it can be observed from Table 2 that SC1 cannot be a constant �0� or �1,� so it must be a function of at least one variable. Checking all the variables M1 . . . Mj(M2 . . . Mj not shown), it is found that the SC1 column's � 0/1� values match at least those of M1, so a single-variable implementation, SC1=MB (recall that M1=MB1), can be selected to implement the connections between SC1 and the MBIST controller. For SC2, it is found that setting SC2 to a constant value of �1� will produce the correct values shown in Table 2. Thus, SC2 can be set to a constant �1� during MBIST mode (using scan cell 300F shown in FIG. 3( f), for example).
When Using Both Scan Cells to Control M1 M1 SC1 SC2 1
Justification Table for Memory Inputs M1 and M2 in FIG. 15
When Using Both Scan Cells to Control M1 M1 M2 SC1 SC2 SC3 0
FIG. 17 shows another example 1700 of the justification process as may be used at process blocks 1310 or 1314 and illustrates how the hardware between the MBIST controller and the scan cells can be minimized in certain situations. In particular, FIG. 17 shows the data input port 1710 of 64-word, 80-bit memory 1702. Thus, there are eighty scan cells 1712 that output eighty bits into the memory 1702 during a single clock cycle. Now assume that to test the memory, two data backgrounds (the data patterns written to all words in a single pass through all addresses) and their complements are used. Assume that the first data background is all �0�s (and thus has a complement of all �1�s) and that the second data background comprises alternating �0�s and �1�s (that is, �0 1 . . . 0 1,� which has a complement of �1 0 . . . 1 0�). Further, assume that in this example, the data inputs are always justified back to the same scan cells and that, for illustrative purposes only, there are no inversions (so that the scan cell values are the same as the data values required by the memory). The resulting justification table after simulating all patterns is shown in Table 5:
M1 M2 M3 M4 M5 . . .
M78 M79 M80 SC1 SC2 SC3 SC4 SC5 . . .
SC78 SC79 SC80 0
In this example, all of the SCi columns from Table 5 have both �0� and �1� values, so none of them can be implemented using constants. Thus, according to the exemplary implementation of the method 1300 described above, single variables are checked, starting with M1. For SC1, the first comparison shows that SC1=M1, so SC1=MB1 is the implementation (a wire from MB1). For SC2, the third row does not match M1, so M2 is tried. M2 is found to match, so SC2=M2, and SC2 is implemented as a wire from MB2. For SC3, M1 again matches, so another fan-out from MB1 becomes the SC3 input. This continues, resulting in connections from MB1 to all of the odd SCi scan cells (SC1, SC3, . . . , SC79), as well as connections from MB2 to all of the even SCi scan cells (SC2, SC4, . . . , SC80). The resulting fan-outs 1704 are shown in FIG. 17. Because each of the fan-outs 1704 drives forty outputs, small buffer trees may be added to handle the load. If buffers are inadequate to meet performance requirements, additional latency can be added to the architecture (e.g., using additional registers).
M1 M2 M3 SC1 SC2 SC3 0
As with the examples discussed above, MBi=Mi. In this example, there are no SCi columns in Table 6 that can be implemented using constants. From Table 6, it can be determined that SC1=M1, so the input hardware for SC1 can be implemented as a wire from MB1. However, both SC2 and SC3 are more complex functions. For them, a synthesis tool can be used to derive the hardware from tables, or a simple sum of products expression can be generated. Using the latter method, and evaluating the �1�s of the SC2 function, it is observed that SC2 has a value of �1� when the memory inputs are: 010, 011, 100, or 101. SC2 can therefore be written as a function of the memory inputs in the following manner:
SC 2 = ⁢ ( M 1 _ � M 2 � M 3 _ ) + ( M 1 _ � M 2 � M 3 ) + ( M 1 � M 2 _ � M 3 _ ) + ⁢ ( M 1 � M 2 _ � M 3 ) = ⁢ ( M 1 _ � M 2 ) � ( M 3 _ + M 3 ) + ( M 1 � M 2 _ ) � ( M 3 _ + M 3 ) = ⁢ ( M 1 _ � M 2 ) + ( M 1 � M 2 _ ) = ⁢ M 1 ⁢ ⁢ XOR ⁢ ⁢ M 2 ( 1 ) Accordingly, MBIST outputs MB1 and MB2 can be XORed in compensatory input logic to produce the SC2 output. A solution for SC3 can be similarly found as follows:
SC 3 = ⁢ ( M 1 _ � M 2 _ � M 3 ) + ( M 1 _ � M 2 � M 3 _ ) + ( M 1 � M 2 _ � M 3 _ ) + ⁢ ( M 1 � M 2 � M 3 ) = ⁢ ( M 1 _ ) ⁢ ( M 2 ⁢ ⁢ XOR ⁢ ⁢ M 3 ) + ( M 1 ) ⁢ ( M 2 ⁢ ⁢ XNOR ⁢ ⁢ M 3 ) = ⁢ ( M 1 _ ) ⁢ ( M 2 ⁢ ⁢ XOR ⁢ ⁢ M 3 ) + ( M 1 ) ⁢ ( M 2 ⁢ ⁢ XOR ⁢ ⁢ M 3 _ ) = ⁢ M 1 ⁢ ⁢ XOR ⁢ ⁢ ( M 2 ⁢ ⁢ XOR ⁢ ⁢ M 3 ) ( 2 ) Thus, all three MBIST outputs MB1, MB2, and MB3 can be XORed together in the compensatory input logic to produce the proper SC3 value.
EXPERIMENTAL RESULTS Results from experiments using the exemplary extended method of FIG. 13 to implement the disclosed MBIST architecture are shown in Table 7.
of Ctrl.
Outp.
F1 F2 SC
Overh.
26 57
MEM14
In the first column, an identification number for the memory tested is given. In the second and third columns, the number of inputs and outputs of the memories are given. In the fourth and fifth columns, the number of gates in the original system input logic (F1) and the original system output logic (F2) are given. In some cases, F1 and F2 had some overlap. The sixth column lists the number of enhanced scan cells that needed to be set to �0� or �1� in order to sensitize the paths from/to the memory inputs/outputs or to justify the constrained values. From Table 7, it can be observed that only a small number of scan cells were fixed. Only for memories MEM2 and MEM13 were many scan cells set. Memory MEM2, however, was a multi-port memory, and the number of scan cells used for the MBIST architecture was not large relative to the total number of pins in the memory. The seventh and eighth columns of Table 7 list the maximum length of the controlling paths and observing paths, respectively. The length of the respective paths is measured in terms of the number of gates in the path. As noted, the disclosed MBIST architecture reduces the slack between the input logic and the memory inputs. Consequently, more timing defects can be detected during at-speed testing of the memory-under-test using the architecture disclosed herein than with the conventional MBIST architecture. Additionally, some of the delay faults and stuck-at faults in the logic around the memory may also be detected using the disclosed MBIST architecture. The ninth column of Table 7 lists the extra area overhead for implementing the exemplary MBIST architectures in terms of the MUX+OR gates used in the enhanced scan cells and the gates used to implement inverse functions. For purposes of Table 7, one MUX+OR gate has an area overhead of 4.3 two-input NAND gates. In general, the majority of the extra overhead resulted from the MUX+OR gates used to enhance the scan cells. The tenth column of Table 7 indicates at which phase the exemplary modified method succeeded. Among the twenty-eight memories, the exemplary method succeeded after phase 2 for five memories, after phase 4 for seventeen memories, and after phase 5 for four memories. The exemplary modified method failed for two memories. In these memories, failure only occurred when no direct access was allowed for any memory pin, and the test set (and therefore the MBIST controller) could not modified. Since the exemplary method needed to perform phases 4 and 5 for twenty-three of the twenty-eight memories, it can be concluded that most of the embedded memories tested had constraints and/or dependencies between the memory inputs. From the last column of Table 7, it can be seen that memory-output constraints also existed. For nine memories, no constraints existed. One memory had a type-1 output constraint, while the others had type-2 output constraints.
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