Source: https://patents.google.com/patent/US8790954B2/en
Timestamp: 2018-05-26 16:09:46
Document Index: 90405777

Matched Legal Cases: ['Application No. 2008100053075', 'Application No. 2007101487965', 'Application No. 2007101011893', 'Application No. 2006', 'Application No. 2006', 'Application No. 10']

US8790954B2 - Method of making wafer structure for backside illuminated color image sensor - Google Patents
US8790954B2
US8790954B2 US14014663 US201314014663A US8790954B2 US 8790954 B2 US8790954 B2 US 8790954B2 US 14014663 US14014663 US 14014663 US 201314014663 A US201314014663 A US 201314014663A US 8790954 B2 US8790954 B2 US 8790954B2
US14014663
US20130344640A1 (en )
Yuan-Chih Hsieh
An integrated circuit device is provided. The integrated circuit device can include a substrate; a first radiation-sensing element disposed over a first portion of the substrate; and a second radiation-sensing element disposed over a second portion of the substrate. The first portion comprises a first radiation absorption characteristic, and the second portion comprises a second radiation absorption characteristic different from the first radiation absorption characteristic.
This application is a continuation of U.S. patent application Ser. No. 12/537,167, filed Aug. 6, 2009, which is a continuation of U.S. patent application Ser. No. 11/626,664, filed Jan. 24, 2007, now U.S. Pat. No. 7,638,852, issued Dec. 29, 2009, which claims benefit of U.S. Provisional Patent Application Ser. No. 60/798,876, filed May 9, 2006, each of which is incorporated herein by reference in its entirety.
FIGS. 2-5 are sectional views of a sensor having a plurality of backside illuminated pixels, constructed according to aspects of the present disclosure.
In the present embodiment, the substrate 110 comprises P-type silicon formed over a silicon dioxide base. Silicon doping may be implemented using a process such as ion implantation or diffusion in various steps. The substrate 110 may comprise lateral isolation features to separate different devices formed on the substrate. The thickness of the substrate 110 has been thinned to allow for etching of the backside of the substrate. This reduction in thickness may be accomplished by back grinding, diamond scrubbing, chemical mechanical planarization (CMP), or other similar techniques.
The sensor 50 includes a plurality of pixels 100 formed on the front surface of the semiconductor substrate 110. For the sake of example, the pixels are further labeled 100R, 100G, and 100B to correspond with example light wavelengths of red, green, and blue, respectively. As noted above, the pixels 100 (also referred to as radiation-sensing elements) sense different wavelengths of radiation (light) and record an intensity or brightness of the radiation (light). The pixels 100 each comprise a light-sensing region (or photo-sensing region) which in the present embodiment is an N-type doped region having dopants formed in the semiconductor substrate 110 by a method such as diffusion or ion implantation. In continuance of the present example, the doped regions are further labeled 112R, 112G, and 112B to correspond with the pixels 100R, 100G, and 100B, respectively. In some embodiments, the doped regions 112 can be varied one from another, such as by having different material types, thicknesses, and so forth.
providing a semiconductor substrate having a substantially planar front surface and a back surface;
forming a first pixel and a second pixel on the substantially planar front surface of the semiconductor substrate; and
forming a first portion of the semiconductor substrate having a first thickness and a second portion of the semiconductor substrate having a second thickness, wherein the first portion having the first thickness is aligned with the first pixel and the second portion having the second thickness is aligned with the second pixel.
2. The method of claim 1, further comprising forming a planarization layer over the back surface of the semiconductor substrate.
3. The method of claim 2, wherein forming the planarization layer over the back surface of the semiconductor substrate includes forming the planarization layer directly on the first and second portions of the semiconductor substrate.
4. The method of claim 1, wherein forming the first portion of the semiconductor substrate having the first thickness and the second portion of the semiconductor substrate having the second thickness includes performing an etching process to the back surface of the semiconductor substrate.
5. The method of claim 4, wherein the etching process includes a wet etching process.
6. The method of claim 1, further comprising forming a color filter layer over the first and second portions of the semiconductor substrate.
7. The method of claim 6, wherein the color filter layer includes a first type of color filter aligned with the first portion and a second color filter aligned with the second portion.
forming a first radiation-sensing element and a second radiation-sensing element on a substantially planar first surface of a substrate; and
removing portions of the substrate such that the substrate has a first thickness and a second thickness, wherein the first thickness and the second thickness are between the substantially planar first surface and a second surface of the substrate, and wherein the first thickness is aligned with the first radiation-sensing element and the second thickness is aligned with the second radiation-sensing element.
9. The method of claim 8, wherein forming the first radiation-sensing element and the second radiation-sensing element on the substantially planar first surface of the substrate further includes forming a third radiation-sensing element on the substantially planar first surface of the substrate.
10. The method of claim 9, further comprising forming red, green, and blue color filters over the second surface of the substrate that are aligned with the first, second, and third radiation-sensing elements, respectively.
11. The method of claim 9, wherein removing portions of the substrate such that the substrate has the first thickness and the second thickness further includes removing additional portions of the substrate such that the substrate has a third thickness, and
wherein the third thickness is between the substantially planar first surface and the second surface of the substrate, and
wherein the third thickness is aligned with the third radiation-sensing element.
12. The method of claim 11, wherein the first thickness defines a first absorption depth for a first radiation directed towards the first radiation-sensing element from the second surface,
wherein the second thickness defines a second absorption depth for a second radiation directed towards the second radiation-sensing element from the second surface, and
wherein the third thickness defines a third absorption depth for a third radiation directed towards the third radiation-sensing element from the second surface.
13. The method of claim 8, wherein the substrate is a silicon-on-insulator substrate.
14. The method of claim 8, further comprising forming one of an organic material layer or a polymeric material layer over the second surface of the substrate.
providing a substrate having a substantially planar first surface and an opposing second surface;
forming a first pixel and a second pixel on the substantially planar first surface of the substrate; and
removing portions of the substrate such that the substrate has a first thickness and a second a second thickness, wherein the first thickness is aligned with the first pixel and the second thickness is aligned with the second pixel.
16. The method of claim 15, furthering including forming a plurality of metal layers over the substantially planar first surface of the substrate.
17. The method of claim 15, further comprising forming a planarization layer over the second surface of the substrate.
18. The method of claim 17, wherein the planarization layer includes a first surface facing the second surface of the semiconductor substrate and an opposing substantially planar second surface,
wherein the planarization layer has a first portion having a first thickness extending from the first surface of the planarization layer to the substantially planar second surface and a second portion having a second thickness extending from the first surface of the planarization layer to the substantially planar second surface, and
wherein the first portion of the planarization layer is aligned with the first pixel and the second portion of the planarization layer is aligned with the second pixel.
19. The method of claim 17, further comprising forming a color filter layer over the planarization layer; and
forming a lens over the color filter layer.
20. The method of claim 19, wherein forming the color filter layer over the planarization layer includes forming a first type of color filter over the planarization layer that is aligned with the first thickness and a second type of color filter over the planarization layer that is aligned with the second thickness.
US14014663 2006-05-09 2013-08-30 Method of making wafer structure for backside illuminated color image sensor Active US8790954B2 (en)
US79887606 true 2006-05-09 2006-05-09
US11626664 US7638852B2 (en) 2006-05-09 2007-01-24 Method of making wafer structure for backside illuminated color image sensor
US12537167 US8525286B2 (en) 2006-05-09 2009-08-06 Method of making wafer structure for backside illuminated color image sensor
US14014663 US8790954B2 (en) 2006-05-09 2013-08-30 Method of making wafer structure for backside illuminated color image sensor
US12537167 Continuation US8525286B2 (en) 2006-05-09 2009-08-06 Method of making wafer structure for backside illuminated color image sensor
US20130344640A1 true US20130344640A1 (en) 2013-12-26
US8790954B2 true US8790954B2 (en) 2014-07-29
US11626664 Expired - Fee Related US7638852B2 (en) 2006-05-09 2007-01-24 Method of making wafer structure for backside illuminated color image sensor
US12537167 Active 2027-03-20 US8525286B2 (en) 2006-05-09 2009-08-06 Method of making wafer structure for backside illuminated color image sensor
US14014663 Active US8790954B2 (en) 2006-05-09 2013-08-30 Method of making wafer structure for backside illuminated color image sensor
KR101133154B1 (en) * 2011-02-03 2012-04-06 디지털옵틱스 코포레이션 이스트 Bsi image sensor package with variable-height silicon for even reception of different wavelengths
US4001878A (en) 1975-11-19 1977-01-04 Rca Corporation Charge transfer color imagers
US4154632A (en) 1977-08-12 1979-05-15 Hitachi, Ltd. Method of diffusing aluminum into silicon substrate for manufacturing semiconductor device
US4193826A (en) 1977-08-15 1980-03-18 Hitachi, Ltd. Vapor phase diffusion of aluminum with or without boron
US4199386A (en) 1978-11-28 1980-04-22 Rca Corporation Method of diffusing aluminum into monocrystalline silicon
US4290830A (en) 1977-03-25 1981-09-22 Hitachi, Ltd. Method of selectively diffusing aluminium into a silicon semiconductor substrate
US4481522A (en) 1982-03-24 1984-11-06 Rca Corporation CCD Imagers with substrates having drift field
US5005063A (en) 1986-03-03 1991-04-02 California Institute Of Technology CCD imaging sensor with flashed backside metal film
JPH07202161A (en) 1993-12-29 1995-08-04 Nikon Corp Solid-state image pickup device and manufacture thereof
US5508625A (en) 1994-06-23 1996-04-16 The Boeing Company Voltage stand off characteristics of photoconductor devices
CN1229526A (en) 1997-06-11 1999-09-22 精工爱普生株式会社 Semiconductor device, liquid crystal display and electronic apparatus including the same
US6227055B1 (en) 1999-11-01 2001-05-08 Delphi Technologies, Inc. Pressure sensor assembly with direct backside sensing
KR20020005990A (en) 2000-07-11 2002-01-18 이데이 노부유끼 Semiconductor device
US20040169625A1 (en) 2003-02-28 2004-09-02 Won-Sang Park Liquid crystal display panel, liquid crystal display device having the same,and method of manufacturing the same
US20050110050A1 (en) 2003-11-20 2005-05-26 Tom Walschap Planarization of an image detector device for improved spectral response
JP2005150463A (en) 2003-11-17 2005-06-09 Sony Corp Solid state image sensor, and method for manufacturing the same
JP2005206432A (en) 2004-01-23 2005-08-04 Univ Of Tokyo Method and apparatus for producing carbon nanotube
KR20050103782A (en) 2004-04-27 2005-11-01 매그나칩 반도체 유한회사 Cmos image sensor with detecting light in backside of wafer and having enlarged photodiode
US6969839B2 (en) 2003-01-31 2005-11-29 Intevac, Inc. Backthinned CMOS sensor with low fixed pattern noise
CN1776917A (en) 2004-10-20 2006-05-24 索尼株式会社 Solid-state imaging device
US7067922B2 (en) 2003-03-27 2006-06-27 Kabushiki Kaisha Toshiba Semiconductor device
CN1877845A (en) 2005-06-07 2006-12-13 中芯国际集成电路制造(上海)有限公司 Method for preparing complementary metal oxide image sensor-mixed silicide
CN1905201A (en) 2005-07-29 2007-01-31 富士通株式会社 Semiconductor imaging device and fabrication process thereof
US7232698B2 (en) 2003-10-24 2007-06-19 Magnachip Semiconductor, Ltd. Method for fabricating CMOS image sensor protecting low temperature oxide delamination
US20080265348A1 (en) 2004-06-09 2008-10-30 Koninklijke Philips Electronics, N.V. Method of Manufacturing an Image Sensor and Image Sensor
US7485940B2 (en) 2007-01-24 2009-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Guard ring structure for improving crosstalk of backside illuminated image sensor
US7491993B2 (en) 2004-12-24 2009-02-17 Dongbu Electronics Inc. CMOS image sensor and method for manufacturing the same
WO1998059373A1 (en) 1997-06-25 1998-12-30 Advanced Photonix, Inc. Active large area avalanche photodiode array
JP4794821B2 (en) 2004-02-19 2011-10-19 キヤノン株式会社 A solid-state imaging device and an imaging system
Chinese Patent Office, Office Action mailed Jul. 10, 2009, Application No. 2008100053075, 9 pages.
Chinese Patent Office, Office Action mailed Mar. 20, 2009, Application No. 2007101487965, 4 pages.
Chinese Patent Office, Office Action mailed May 8, 2009, Application No. 2007101011893, 6 pages.
Japanese Patent Office, Office Action mailed Feb. 15, 2010, Application No. 2006-175291, 4 pages.
Japanese Patent Office, Office Action mailed Jul. 17, 2009, Application No. 2006-175291, 4 pages. (English Translation, 3 pages).
Korean Intellectual Property Office, Notice of Preliminary Rejection mailed May 28, 2008, Application No. 10-2007-0045138, 8 pages.
US7638852B2 (en) 2009-12-29 grant
US8525286B2 (en) 2013-09-03 grant
US20130344640A1 (en) 2013-12-26 application
US20070262364A1 (en) 2007-11-15 application
US20090294886A1 (en) 2009-12-03 application
US20070207566A1 (en) 2007-09-06 Method of fabricating backside illuminated image sensor
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSU, TZU-HSUAN;HSIEH, YUAN-CHIH;YAUNG, DUN-NIAN;AND OTHERS;REEL/FRAME:033104/0781