Source: https://patents.google.com/patent/EP2232499B1/en
Timestamp: 2019-11-20 18:33:28
Document Index: 411302478

Matched Legal Cases: ['Application No. 11', 'Application No. 2006', 'Application No 11', 'Application No. 2006', 'Application No. 11', 'Application No. 10', 'Application No. 09', 'Application No. 11', 'Application No. 2006', 'Application No 11', 'Application No. 2006']

EP2232499B1 - Large capacity one-time programmable memory cell using metal oxides - Google Patents
EP2232499B1
EP2232499B1 EP20080867812 EP08867812A EP2232499B1 EP 2232499 B1 EP2232499 B1 EP 2232499B1 EP 20080867812 EP20080867812 EP 20080867812 EP 08867812 A EP08867812 A EP 08867812A EP 2232499 B1 EP2232499 B1 EP 2232499B1
EP20080867812
EP2232499A1 (en
2008-11-05 Application filed by SanDisk 3D LLC filed Critical SanDisk 3D LLC
2010-09-29 Publication of EP2232499A1 publication Critical patent/EP2232499A1/en
2014-07-16 Publication of EP2232499B1 publication Critical patent/EP2232499B1/en
150000004706 metal oxides Chemical class 0 claims description title 58
229910044991 metal oxides Inorganic materials 0 claims description title 43
Cells may also vary in the number of data states each cell can achieve. A data state may be stored by altering some characteristic of the cell which can be detected, such as current flowing through the cell under a given applied voltage or the threshold voltage of a transistor within the cell. A data state is a distinct value of the cell, such as a data '0' or a data '1'.
Some solutions for achieving erasable or multi-state cells are complex. Floating gate and SONOS memory cells, for example, operate by storing charge, where the presence, absence or amount of stored charge changes a transistor threshold voltage. These memory cells are three-terminal devices that are relatively difficult to fabricate and operate at the very small dimensions required for competitiveness in modem integrated circuits.
Thus, a nonvolatile memory array having erasable or multi-state memory cells formed using semiconductor materials in structures that are readily scaled to small size and having a capacity of more than I bit/cell (i.e., ≥ bits/cell) is desirable.
US 2007/069276 A1 , over which the independent claims are characterised, describes a multi-use memory cell.
According to an aspect of the present invention there is provided a method of programming a nonvolatile memory device, comprising (i) providing a nonvolatile memory cell comprising a diode in series with at least one metal oxide, (ii) applying a first forward bias to change a resistivity state of the metal oxide from a first state to a second state; (iii) applying a second forward bias to change a resistivity state of the metal oxide from a second state to a third state; and (iv) applying a third forward bias to change a resistivity state of the metal oxide from a third state to a fourth state. The fourth resistivity state is higher than the third resistivity state, the third resistivity state is lower than the second resistivity state, and the second resistivity state is lower than the first resistivity state.
According to another aspect of the present invention there is provided a device as claimed in claim 14.
Figs. 3(a)-3(b) are side cross-sectional views illustrating two embodiments of a memory cell.
Figs. 4(a)-4(d) are schematic side cross-sectional views illustrating alternative diode configurations according to an embodiment of the present invention.
Leakage current can be greatly reduced by forming each memory with a diode. A diode has a non-linear I-V characteristic, allowing very little current flow below a turn-on voltage, and substantially higher current flow above the turn-on voltage. In general a diode also acts as one-way valves passing current more easily in one direction than the other. Thus, so long as biasing schemes are selected that assure that only the selected cell is subjected to a forward current above the turn-on voltage, leakage current along unintended paths (such as the U 1-U2-U3 sneak path of Fig. 1) can be greatly reduced.
In preferred embodiments, the memory cell includes a cylindrical semiconductor diode is located in series with a cylindrical metal oxide layer or film. The diode and the film are disposed between two electrodes, as illustrated in Fig. 2. The number of oxide layers or films need not be limited to one; for example, it can be two or more. The diode and metal oxide film may have a shape other than cylindrical, if desired. For a detailed description of a the design of a memory cell comprising a diode and a metal oxide, see for example US Patent Application No. 11/125,939 filed on May 9, 2005 (which corresponds to US Published Application No. 2006/0250836 to Herner et al :), and US Patent Application No 11/395,995 filed on March 31, 2006 (which corresponds to US Patent Published Application No. 2006/0250837 to Herner et al. ,). In the preferred embodiments of the invention, the metal oxide film serves as the resistivity switching element and the diode as the steering element of the memory cell.
Fig. 2 illustrates the perspective view of a memory cell formed according to a preferred embodiment of the present invention. A bottom conductor 101 is formed of a conductive material, for example tungsten, and extends in a first direction. Barrier and adhesion layers, such as TiN layers, may be included in bottom conductor 101. The semiconductor diode 110 has a bottom heavily doped n-type region 112; an intrinsic region 114, which is not intentionally doped; and a top heavily doped p-type region 116, though the orientation of this diode may be reversed, as shown in Figures 4a to 4d. Such a diode, regardless of its orientation, will be referred to as a p-i-n diode or simply diode. A metal oxide layer 118 is disposed on the diode, either on the p-type region 116 or below the n-region 112 of the diode 110, as shown for example in Figs. 3(a) and 3(b). Top conductor 100 may be formed in the same manner and of the same materials as bottom conductor 101, and extends in a second direction different from the first direction. The semiconductor diode 110 is vertically disposed between bottom conductor 101 and top conductor 100. The diode can comprise any single crystal, polycrystalline, or amorphous semiconductor material, such as silicon, germanium, or silicon-germanium alloys.
In the preferred embodiments, the diode 110 comprise three different regions 112, 114, 116. In this discussion a region of semiconductor material which is not intentionally doped is described as an intrinsic region 114 as shown in Fig. 2 and Figs. 3(a)-(b). It will be understood by those skilled in the art, however, that an intrinsic region may in fact include a low concentration of p-type or n-type dopants. Dopants may diffuse into the intrinsic region from the adjacent n or p-doped regions (112 and 116, respectively in Fig. 3(a) and 3(b)) or may be present in the deposition chamber during deposition due to contamination from an earlier deposition. It will further be understood that deposited intrinsic semiconductor material (such as silicon) may include defects which cause it to behave as if slightly n-doped. Use of the term "intrinsic" to describe silicon, germanium, a silicon-germanium alloy, or some other semiconductor material is not meant to imply that this region contains no dopants whatsoever, nor that such a region is perfectly electrically neutral. The diode need not be limited to a p-i-n design as described; rather, a diode can comprise a combination of the different regions, each with different concentrations of dopants, as illustrated in Figs. 4(a)-4(d).
Herner et al., US Patent Application No. 11/148,530 (Publication No. US 2005/0226067 ), "Nonvolatile Memory Cell Operating by Increasing Order in Polycrystalline Semiconductor Material," filed June 8, 2006; and Herner, US Patent Application 10/954,510 (Publication No. US 2005/0121743 ), "Memory Cell Comprising a Semiconductor Junction Diode Crystallized Adjacent to a Silicide," filed September 29, 2004, both owned by the assignee of the present invention, describe that crystallization of polysilicon adjacent to an appropriate silicide affects the properties of the polysilicon. Certain metal silicides, such as cobalt silicide and titanium silicide, have a lattice structure very close to that of silicon. When amorphous or microcrystalline silicon is crystallized in contact with one of these silicides, the crystal lattice of the silicide provides a template to the silicon during crystallization. The resulting polysilicon will be highly ordered, and relatively low in defects. This high-quality polysilicon, when doped with a conductivity-enhancing dopant, is relatively highly conductive as formed. Such a diode preferably acts as a steering element of the memory cell because the diode does not change resistivity when certain voltage pulses are applied which are sufficient to switch the resistivity state of the metal oxide film.
The metal oxide film can be any resistivity switching metal oxide film, such as a perovskite, such as CaTiO3 or (Ba,Sr)TiO3, or NiO, Nb2O5, TiO2, HfO2, Al2O3, MgO, CrO2, ZnO2, ZrO2, VO, or Ta2O5. The thickness of the metal oxide in the preferred embodiments of the invention can be preferably about 20-1000 Å, more preferably about 40-400 Å, or more preferably about 70-100 Å.
The memory cell initially starts in a high resistivity, low read current state (referred to as the unprogrammed or virgin state). The cell can be put in the programmed, low resistivity state by a high forward bias voltage pulse, preferably at the factory where the cell is made before the product is sold, where power is not a consideration. Once the product is sold, the cell is subsequently put in one or more other states by subsequent forward bias programming pulses. The difference between the read currents of the unprogrammed and programmed states constitutes the "window" for the memory cell. It is desirable for this window to be as large as possible for manufacturing robustness. The present inventors realized that the read current window of the programmed cell and the number of bits per cell can be increased by the following programming method.
Without wishing to be bound by a particular theory, the conductivity, or inversely the resistivity, of the metal oxide can be modified because the conductivity of the oxide is largely affected by the movements of the oxygen vacancies. For example, a partial depletion of the oxygen vacancies as a result of the vacancies moving out of the oxide film surface can result in an increase of the conductivity, or conversely, a decrease in resistivity. For more detailed descriptions of the characterizations of the metal oxides in nonvolatile memory cell application, see for example Sim et al., IEEE Electron Device Letters, 2005, 26, p292; Lee et al., IEEE Electron Device Letters, 2005, 26, p719; Sakamoto et al., Applied Physics Letters, 2007, 91, p092110-1.
In a preferred embodiment of the present invention, a diode formed of polycrystalline semiconductor material and at least one metal oxide are arranged in series. The device is used as a one-time programmable multilevel cell, in preferred embodiments having four distinct data states. The term "one-time programmable" means that cell can be non-reversibly programmed into up to four different states.
Fig. 6 is a probability plot showing read current of a memory cell at 2 V in various states. In one embodiment of the invention, a series of 3 forward biases are applied. A first forward bias current limited voltage (V1→2) (i.e., the programming pulse described above) lowers the resistivity of the metal oxide and changes the resistivity state of the cell from the first state 1 to the second state 2. A second higher current limited forward bias voltage (V2→3) further lowers the resistivity of the oxide and changes the resistivity state of the cell from the second state 2 to the third state 3. Finally, a third even higher current limited forward bias voltage (V3→4) increases the resistivity of the metal oxide and changes the resistivity state of the cell from the third state 3 to the fourth state 4. Thus, state 2 is obtained with a predetermined voltage at a predetermined current limit. Then, state 3 is obtained with a higher voltage and at a higher current limit than state 2. State 4 is obtained with a lower voltage than state 3, but at a higher current limit than state 3 (i.e., the current limit to obtain state 4 is the highest current limit of the four states). The successive current limits for the different states ensure that state 2 is obtained without moving directly to state 3 or 4 without going through state 2 by the application of the forward bias voltages. The four resistivity states of the oxide are distinguishable from the states of the diode, which in the preferred embodiments is used as a steering element and has minimal effects on change of cell resistivity.
The initial read current is between about 1x10-13 and 2x10-13 A when a first electrical forward bias pulse, V1→2, is applied. The pulse has a magnitude greater than a minimum voltage required for programming the cell. The voltage applied can be about 10 V. The pulse width can be between about 100 and about 500 nsec. This first electrical pulse switches the metal oxide from a first resistivity state 1 to a second resistivity state 2, with the second state having lower resistivity than the first state; this transition is labeled "1→2" in Fig. 6. The resultant read current in the F state is between about 2x10-6 and 11x10-6 A. A second forward bias pulse V2→3 is then applied, with V2→3 being larger than V1→2, further lowering the resistivity of the oxide. The resulting read current of the cell is between about 2x10-5 and 10x10-5 A. Finally, a third forward bias pulse V3→4 is applied, with V3→4 being smaller than V2→3, increasing the resistivity of the oxide. The resulting read current is between about 0.7x10-7 and 4x10-7 A.
Generally, a device for programming the memory cells is a driver circuit located under, over, or adjacent to the memory cell. The circuit can have a monolithic integrated structure, or a plurality of integrated device packaged together or in close proximity or diebonded together. For a detailed descriptions of the driver circuit, see for example, US Patent Application No. 10/185,508 (Publication No. US 2004/0002184) by Cleeves ; US Patent Application No. 09/560,626 by Knall ; and US Patent No. 6,055,180 to Gudensen et al.
The memory cell maybe fabricated by any suitable methods. For example, the methods described US Patent Application No. 11/125,939 filed on May 9, 2005 (which corresponds to US Published Application No. 2006/0250836 to Herner et al. ), and US Patent Application No 11/395,995 filed on March 31, 2006 (which corresponds to US Patent Published Application No. 2006/0250837 to Herner et al. ,) may be used.
The above described memory cell shown in Figure 2 may be located in a one memory level device. If desired, additional memory levels can be formed above the first memory level to form a monolithic three dimensional memory array. In some embodiments, conductors can be shared between memory levels; i.e. top conductor 100 shown in Figure 2 would serve as the bottom conductor of the next memory level. In other embodiments, an interlevel dielectric (not shown) is formed above the first memory level, its surface planarized, and construction of a second memory level begins on this planarized interlevel dielectric, with no shared conductors.
A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a wafer, with no intervening substrates. The layers forming one memory level are deposited or grown directly over the layers of an existing level or levels. In contrast, stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, US Patent No. 5,915,167 , "Three dimensional structure memory." The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.
A method of programming a nonvolatile memory cell, comprising:
providing a nonvolatile memory cell comprising a diode (110) in series with at least one metal oxide (118);
applying a first forward bias to change a resistivity state of the metal oxide (118) from a first state to a second state; characterised by
applying a second forward bias to change a resistivity state of the metal oxide (118) from a second state to a third state; and
applying a third forward bias to change a resistivity state of the metal oxide (118) from a third state to a fourth state;
The method according to claim 1, wherein the diode (110) comprises a steering element and the metal oxide (118) comprises a resistivity switching element.
The method according to claim 1, wherein the memory cell is a one-time programmable cell and the diode (110) comprises p-i-n polysilicon diode.
The method according to claim 1, wherein the metal oxide (118) comprises a perovskite, NiO, Nb2O5, TiO2, HfO2, Al2O3, MgO, CrO2, ZnO2, ZrO2, VO, or Ta2O5.
The method according to claim 4, wherein the metal oxide (118) is a perovskite comprising CaTiO3 or (Ba,Sr)TiO3.
The method according to claim 1, wherein the metal oxide (118) has a higher resistivity than the diode (110) and/or wherein the metal oxide (118) has a thickness of about 20 to about 1000 A.
The method according to claim 1, wherein the metal oxide (118) has a thickness of about 40-400 A.
The method according to claim 1, wherein memory cell comprises a portion of a monolithic three dimensional array of nonvolatile memory cells.
The method according to claim 1, wherein the first forward bias is smaller than the second forward bias and/or wherein the second forward bias is larger than the third forward bias.
the third forward bias is applied at a higher current limit than the second forward bias; and/or
the fourth resistivity state is intermediate between the first and the second resistivity states.
The method according to claim 1, wherein the first, second and third forward biases range from 1 to 20 V.
The method according to claim 1, wherein the first, second and third forward biases range from 2 to 10 V.
The method according to claim 1, wherein the first, second and third forward biases range from 3 to 8 V.
at least one nonvolatile memory cell comprising a diode steering element (110) located in series with a metal oxide resistivity switching element (118); and
a means for programming the at least one nonvolatile memory cell by applying a first forward bias to change a resistivity state of the metal oxide (118) from a first state to a second state, characterised by applying a second forward bias to change a resistivity state of the metal oxide (118) from a second state to a third state, and applying a third forward bias to change a resistivity state of the metal oxide (118) from a third state to a fourth state, wherein the fourth resistivity state is higher than the third resistivity state, the third resistivity state is lower than the second resistivity state, and the second resistivity state is lower than the first resistivity state.
the metal oxide (118) has a higher resistivity than the diode (110); and
the means for programming comprises a driver circuit; and/or
the device comprises a monolithic three dimensional array of nonvolatile memory cells; and/or
the diode (110) comprises p-i-n polysilicon diode; and
the metal oxide (118) comprises a perovskite, NiO, Nb2O5, TiO2, HfO2, Al2O3, MgO, CrO2, ZnO2, ZrO2, VO, or Ta2O5.
EP20080867812 2007-12-27 2008-11-05 Large capacity one-time programmable memory cell using metal oxides Expired - Fee Related EP2232499B1 (en)
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EP2232499B1 true EP2232499B1 (en) 2014-07-16
EP20080867812 Expired - Fee Related EP2232499B1 (en) 2007-12-27 2008-11-05 Large capacity one-time programmable memory cell using metal oxides
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