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Patent US6489943 - Data driver for use in liquid crystal display - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA ramp signal application type of data driver in a liquid crystal display. The data driver includes a plurality of shift registers and sample and hold circuits that sample data lines. A plurality of timing control parts receive the sampled data from the sample and hold circuits and n timing signals having...http://www.google.com/patents/US6489943?utm_source=gb-gplus-sharePatent US6489943 - Data driver for use in liquid crystal displayAdvanced Patent SearchPublication numberUS6489943 B1Publication typeGrantApplication numberUS 09/487,663Publication dateDec 3, 2002Filing dateJan 19, 2000Priority dateJul 27, 1996Fee statusPaidAlso published asUS6049320Publication number09487663, 487663, US 6489943 B1, US 6489943B1, US-B1-6489943, US6489943 B1, US6489943B1InventorsJu-Cheon YeoOriginal AssigneeLg Electronics Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (6), Classifications (10), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetData driver for use in liquid crystal displayUS 6489943 B1Abstract A ramp signal application type of data driver in a liquid crystal display. The data driver includes a plurality of shift registers and sample and hold circuits that sample data lines. A plurality of timing control parts receive the sampled data from the sample and hold circuits and n timing signals having different periods from each other to thereby perform a logical operation. A plurality of transistors receive a ramp signal and are switched in accordance with the signals output by the timing control parts to output the ramp signal based on when the transistor is on and off.
What is claimed is: 1. A driving circuit for a liquid crystal display, comprising:
a plurality of data lines; a sample and hold circuit connected to the data lines, for sampling and storing digital data of n bits from the data lines; a timing control circuit for receiving the digital data and a plurality of timing signals, and performing a logical operation on the plurality of timing signals in accordance with the digital data; and a switching circuit for receiving a time varying signal and switching the time varying signal to a signal line of the liquid crystal display, wherein the switching time is controlled by the output of the timing control circuit. 2. The driving circuit according to claim 1, wherein the timing control circuit receives a plurality of timing signals of different period.
3. The driving circuit according to claim 2, wherein the plurality of timing signals includes a first timing signal and a second timing signal, and wherein the first timing signal has half the period of the second timing signal.
4. The driving circuit according to claim 1, wherein the time varying signal increases with time.
5. The driving circuit according to claim 4, wherein the time varying signal includes a ramp signal.
6. The driving circuit according to claim 1, wherein the number of the timing signals is equal to the number of bits of the digital data.
7. The driving circuit according to claim 1, wherein the timing control circuit includes a plurality of AND gates for receiving a corresponding timing signal and corresponding digital data to perform a logical ANDing operation, and an OR gate for receiving output signals from the plurality of AND gates to perform a logical ORing operation and for outputting the Ored result as an output.
8. The driving circuit according to claim 7, wherein the number of the AND gates is equal to the number of the plurality of timing signals.
9. The driving circuit according to claim 7, wherein the Ored output is fed back to the OR gate.
This is a continuation of application Ser. No. 08/823,904, filed Mar. 25, 1997, now U.S. Pat. No. 6,049,320 which is incorporated herein by reference.
The present invention relate to a data driver for use in a liquid crystal display and, more particularly, to a ramp signal application type of data driver.
FIG. 1 is a block diagram illustrating a construction of a conventional data driver. FIGS. 2A to 2C are timing diagrams illustrating output states at point. A, B and C of FIG. 1. Referring to FIG. 1, the conventional data driver includes a plurality of registers 1, a plurality of counters 2 and a plurality of pass transistors 3. Digital data is sequentially loaded into the plurality of registers 1. After the digital data is loaded into a register it is transferred to a corresponding counter 2.
When a load signal is applied to the lead line of each of the counters 2, the counters 2 each set a corresponding digital data count value and count down from the digital data count value according to an input clock signal. The counters 2 execute a logical ORing operation on signals output from a plurality of internal flip-flops, to thereby produce a pulse width modulated output. Output digital bits from the counters 2 are applied to corresponding pass transistors 3 for producing ramp signal for producing ramp signal lines.
When a load signal is applied to the lead line of each of the counters 2, the counters 2 each set a corresponding digital data count value and count down from the digital data count value according to an input clock signal. The counters 2 execute a logical Oring operation on signals output from a plurality of internal flip-flops, to thereby produce a pulse width modulated output. Output digital bits from the counters 2 are applied to corresponding pass transistors 3 for producing ramp signal lines.
When the output digital bits from the counters 2 become high, �H� level, the corresponding pass transistors 3 are turned on, and the ramp signals are applied to data lines.
On the other hand, when the output signals from the counters 2 become low, �L� level, the corresponding pass transistors 3 are turned off and the ramp voltage on the data lines is unchanged. The ramp voltage determines a brightness of picture elements in a liquid crystal display.
FIG. 2A is a timing diagram showing output waveforms of the applied ramp signal. FIG. 2B is a timing diagram showing output waveforms of a counter 2 in the case of digital data �000010� and �111101�. FIG. 2C is a timing diagram showing output waveforms of a voltage or responding to a transformed ramp signal of FIG. 2A in response to digital data output of the counter 2 of FIG. 2B.
FIG. 3 is a circuit diagram of the counter 2 of FIG. 1. A load signal is inverted and applied to �OR� gate 300, digital data, data A-D, is supplied to each terminal of the counters 2 through �AND� gates 310. Next, the counters 2 are each set to a corresponding data count value of the applied digital data. After the data loading is completed, a clock signal is applied to flip-flops 312-318 in counter 2. The counters 2 respectively countdown by 1 from the digital data count value, and when the digital data value is �0000�, the counter is reset and halted. Then, OR Gate 320 performs a logical OR operation on the flip-flop outputs QA, QB, QC and QD. The counters 2 respectively output the OR-ed result as an output signal.
Accordingly, the conventional data driver for use in a liquid crystal display requires counters with complicated circuit construction.
SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a data driver for use in a liquid crystal display that has a simplified structure.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a data driver in a liquid crystal display, the data driver including a plurality of data lines; a plurality of shift registers for sequentially outputting a sample control signal; a plurality of sample and hold circuits, connected to each of the data lines, for sampling data on corresponding data lines in response to the sample control signal; and a plurality of timing control parts for receiving sampled data from the sample and hold circuits and for performing a logical operation on the sample data.
FIG. 1 is a block diagram illustrating a construction of a conventional data driver;
FIGS. 2A to 2C are timing diagrams illustrating the signals at points A, B and C of FIG. 1;
FIG. 3 is a circuit diagram of the counter included in a Shift register of FIG. 1;
FIG. 4 is a block diagram of a data driver according to the present invention;
FIG. 5 is a circuit diagram illustrating a 4-bit logic circuit of a timing control part of FIG. 4;
FIGS. 6A to 6D are timing diagrams illustrating input/output waveforms to/from a timing control part of FIG. 5;
FIG. 7 is a circuit diagram of a timing control part of a data driver according to one embodiment of the present invention;
FIG. 8 is a circuit diagram of a timing control part of a data driver according to a second embodiment of the present invention; and
FIG. 9 is a circuit diagram of a timing control part of a data driver according to a third embodiment of the present invention.
FIG. 4 is a block diagram illustrating a data driver for use in a liquid crystal display according to the present invention. The data driver includes a plurality of shift registers 10, a plurality of sample and hold circuits 11 preferably of a conventional type, a plurality of timing control parts 12 and a plurality of transistors 13. The plurality of shift registers 10 respectively output signals to sample and hold circuits 11 for sequentially sampling digital data from data lines. A corresponding image signal on each data line is stored in digital data format in the sample and hold circuits 11.
After the digital data is stored in the sample and hold circuits 11, a data enable signal is applied to each of the sample and hold circuits 11. simultaneously, the digital data stored in each of the sample and hold circuits 11 is applied to a corresponding timing control part 12.
Each of the timing control parts 12 receives the digital data and �n� timing signals, each having different periods from each other. The timing control parts 12 perform logical operations on the digital data and the timing signals to produce pulse width modulated (PWM) output signals to the pass transistors 13.
The pass transistors 13 are each connected to an external ramp signal line and receive respective PWM output signals from the timing control parts 12. When the output signals from the timing control parts 12 are low, at the �L� level, the corresponding pass transistors 13 are turned on, thereby blocking the ramp signal from transmitting to pixels in the liquid crystal display 4A and when the output signals are high, at the �H� level, the corresponding pass transistors 13 are turned off passing light to pixels in the liquid crystal device.
When the pass transistors are turned off, a ramp voltage is maintained on the data line connected to a picture element. The ramp voltage determines a brightness of the picture element in the liquid crystal display. The application of the ramp signal can be controlled by the PWM output signal from the timing control part 12.
FIG. 5 is a circuit diagram of a logic circuit in each timing control part 12 for handling bits of digital data of FIG. 4. FIGS. 6A to 6D are timing diagrams illustrating input/output waveforms to/from the timing control part logic circuit of FIG. 5.
As shown in FIG. 5, each timing control part 12 is comprised of a plurality of AND gates 500, an OR gate 510, which may be preset or reset, and a clocked buffer 520. The n timing signals t0, t1, t2, . . . , tn, which correspond to the number of bits, and the digital data input signals b0, b1, b2, . . . , bn are respectively input to AND gates 500. The AND gates 500 perform a logical AND operation on the respective timing signals and data input signals. In the example shown in FIGS. 6A and 6B for four bits, the timing signals are t0-t3 as shown in FIG. 6A, and the data input signals are b0-b3. A logical OR operation is performed on the AND gate outputs.
The timing signal t0, corresponding to a most significant bit b0 among the digital data input signals, has the longest period, the timing signal t1 corresponding to the bit b1 has half the timing signal t0 period, and the timing signal t2 corresponding to the bit b2 has a quarter of the timing signal to period. That is, I-th timing signal has the period Ti as follows: Ti=(�)1 T0.
As shown in FIGS. 6B and 6D, when the data enable signal rst of the �H� level is input to a timing control part 12, the output signal of OR gate 510 is preset to the �H� level. Next, when the data enable signal rst of the �L� level is input, the output signal of OR gate 510 is controlled in accordance with the digital data signals from AND gates 500.
An output signal from the OR gate 510 is fed back to a reset input of the OR gate 510 through the clocked buffer 520.
When the output signal from the OR gate 510 becomes low, �L� level, as shown in FIG. 6C, the output signal is reset to halt the operation of the timing control part 12, keeping the output state of the timing control part 12 at the �L� level as shown in FIG. 6D. When the output of a timing control part 12 is high, the corresponding transistor 13 is on and ramp signal passes to light elements of a liquid crystal display.
When the data enable signal rst, as shown in FIG. 6B, is again input to the timing control part 12, the above operation is repeatedly performed. Accordingly, the output signal of the timing control part 12 is output as a pulse width modulated signal in accordance with the digital data input signal. The PWM output waveforms of the timing control part 12 in FIG. 6D show the cases of digital data input signals �1010� and �0110�.
FIG. 7 is a circuit diagram of a timing control part of a data driver according to a second embodiment of the present invention. Referring to FIG. 7, parallel pairs of P-type transistors 710 and 720 constitute an AND gate and perform a logical ANDing operation, and the serial connection of each parallel pair of transistors 710 and 720 act as OR gates and perform a logical ORing operation. A final output signal is input to an N-type transistor 730 connected to the P-type transistor pairs 710 and serves to perform a reset function.
When the data enable signal rst 700 is applied, a first P-type transistor 20 is turned off, and a node A is connected from voltage VDD. A first N-type transistor 21 is then turned on, and when the clock signal 705 goes to the �H� or high level to turn on transistor 730, the node A is connected to a ground voltage and is low. Meanwhile, when the data enable signal rst is changed to the �L� or low level, the timing signals t0, t1, t2 and t3 are applied to transistors 710 and a logical AND operation is performed. For the logical operation, the node A is precharged while the clock is held at the �H� or high level and the logical operation of input bits do, d1, d2 and d3 the timing signals to, t1, t2 and t3 is performed while the clock is kept at the �L� or low level, which result is output through an inverter 740. A p-type transistor 750 applies rst signal 700 to inverter 740.
While the output signal is kept at the �H� or high level, a second N-type transistor 22 is turned on and then a logical OR operation is performed, whereas when the output signal becomes low, �L� level, the second N-type transistor 22 is turned off and the node A remains at the �H� or high level. Therefore, until the next data enable signal rst 700 is applied, the output signal of the timing control part is held to the �L� or low level.
FIG. 8 is a circuit diagram of a timing control part of a data driver according to a third embodiment of the present invention. In comparison to FIG. 7, the first N-type transistor 21 receiving the data enable signal rst 100 is directly connected to the node A, and the P-type transistor applying the data enable a signal rst to an inverter is not included, thereby making the discharge of the transistor faster and the circuit more stable.
FIG. 9 is a circuit diagram of a timing control part of a data driver according to a fourth embodiment of the present invention. A plurality of N-type transistor pairs 900 are connected in series to perform a logical ANDing operation, and a pair of N-type transistors 910 performs a logical ORing operation, being connected in parallel to each other.
As discussed above, a data driver for use in a liquid crystal display according to the present invention has advantages as follows: 1) a circuit construction can be simple, since the timing control parts, to which pulses are applied do not require a counter in each data line; and 2) a production yield of the liquid crystal display can be increased because of the simple data driver construction.
The foregoing description of preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. The embodiments were chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in th art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto, and their equivalents.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5166670Dec 27, 1990Nov 24, 1992Sharp Kabushiki KaishaColumn electrode driving circuit for a display apparatusUS5266936May 4, 1992Nov 30, 1993Nec CorporationDriving circuit for liquid crystal displayUS5434899Aug 12, 1994Jul 18, 1995Thomson Consumer Electronics, S.A.Phase clocked shift register with cross connecting between stagesUS5477234Apr 13, 1994Dec 19, 1995International Business Machines CorporationLiquid crystal display apparatusUS5583535Aug 19, 1994Dec 10, 1996Sharp Kabushiki KaishaColumn electrode drive circuit of liquid crystal display device capable of simultaneously applying display voltages to column electrodes as well as sequentially applying scanning voltages to column electrodesUS5796379Apr 10, 1996Aug 18, 1998Fujitsu LimitedDigital data line driver adapted to realize multigray-scale display of high qualityReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6860609 *Jun 2, 2003Mar 1, 2005Infocus CorporationImage-rendering deviceUS7140731Mar 15, 2006Nov 28, 2006Infocus CorporationImage-rendering deviceUS7350923Feb 15, 2005Apr 1, 2008Infocus CorporationImage-rendering deviceUS8402185Feb 1, 2007Mar 19, 2013Seiko Epson CorporationDisplay device adapter with digital media interfaceUS8654254 *Aug 24, 2010Feb 18, 2014Magnachip Semiconductor, Ltd.Device and method for driving display panel using time variant signalUS20110069232 *Aug 24, 2010Mar 24, 2011Magnachip Semiconductor, Ltd.Device and method for driving display panel* Cited by examinerClassifications U.S. Classification345/99, 345/98, 345/100International ClassificationG09G3/36, G09G3/20Cooperative ClassificationG09G3/3688, G09G2310/0259, G09G3/2011European ClassificationG09G3/20G2, G09G3/36C14ALegal EventsDateCodeEventDescriptionApr 22, 2014FPAYFee paymentYear of fee payment: 12Jun 5, 2012ASAssignmentEffective date: 20080229Free format text: CHANGE OF NAME;ASSIGNOR:LG PHILIPS LCD CO., LTD;REEL/FRAME:028323/0911Owner name: LG DISPLAY CO., LTD., KOREA, REPUBLIC OFJun 1, 2012ASAssignmentOwner name: LG PHILIPS LCD CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LG ELECTRONICS, INC.;REEL/FRAME:028305/0212Effective date: 19990921May 7, 2010FPAYFee paymentYear of fee payment: 8May 12, 2006FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google