Source: https://patents.justia.com/patent/8867182
Timestamp: 2019-07-18 22:07:14
Document Index: 275589338

Matched Legal Cases: ['Application No. 2011', 'Application No. 100109055', 'Application No. 2008', 'Application No. 10', 'Application No. 200680030274', 'Application No. 10', 'Application No. 2011', 'Application No. 10', 'Application No. 2008', 'Application No. 11', 'Application No. 201110386197', 'Application No. 11', 'Application No. 101130902']

US Patent for Signal-powered integrated circuit with ESD protection Patent (Patent # 8,867,182 issued October 21, 2014) - Justia Patents Search
Justia Patents Voltage ResponsiveUS Patent for Signal-powered integrated circuit with ESD protection Patent (Patent # 8,867,182)
Jun 7, 2010 - Agere Systems Inc.
The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.
This is a divisional of co-pending application Ser. No. 11/159,614, filed on Jun. 23, 2005, the teachings of which are incorporated herein by reference.
The present invention relates generally to digital communication between two devices.
One embodiment of the invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring sufficient power to operate the line-side circuitry without draining power from the telephone line. The present inventors have recognized that a tremendous amount of power may be transmitted from a system-side interface circuit to a line-side interface circuit using an isolation transformer, and that the cost of using a transformer as the isolation barrier may be greatly reduced by transmitting both data and power over a single isolation transformer. Accordingly, an embodiment of the invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer over which both data and power signals may be transmitted. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive forward-going data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit.
Another embodiment of the invention further provides a communication protocol for use in a communication interface including an isolation barrier. A single frame in the communication protocol includes one or more forward data bits; one or more forward control bits; one or more reverse data bits, and one or more reverse control bits, encoded via Manchester encoding such that the flux balance of the isolation barrier is maintained. The communication frame may further include one or more “padding” bits that may be added or removed based on the number of forward and reverse data bits that are in the frame, so that the communication interface may accommodate more than one data throughput rate while retaining a fixed clock rate. The frame may still further include a “sync” pattern comprising three consecutive cycles having the same value.
Still another embodiment of the invention provides a method of communicating signals across an isolation barrier in accordance with the above communication protocol.
Yet another embodiment of the invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.
FIG. 1 is a block diagram depicting a digital communication link according to one embodiment of the invention;
FIG. 2 is a timing diagram illustrating the operation of the digital communication link of FIG. 1;
FIG. 3 is a framing diagram illustrating the composition of a frame suitable for use in the digital communication link of FIG. 1;
FIG. 4 is a further framing diagram illustrating the composition of a frame having an odd-numbered quantity of cycles, suitable for use in the digital communication link of FIG. 1;
FIG. 5 is a circuit diagram illustrating a digital communication link according to another embodiment of the invention;
FIG. 6 is a conceptual diagram illustrating the transfer of power in the digital communication link of FIG. 5;
FIG. 7 is a circuit diagram illustrating a single-ended embodiment of a digital communication link according to still another embodiment of the invention; and
FIG. 8 is a chart illustrating the relationship between power transfer and the forward-to-reverse transmission ratio in the digital communication link of FIG. 5.
Embodiments of the present invention provide an isolated digital communication link between line-side circuitry and system-side circuitry in a DAA. In accordance with one embodiment of the invention, a single transformer is employed as the isolation barrier. Using the single-transformer isolation barrier (“STIB”), a sufficiently large amount of power may be transferred from a system-side interface circuit (“SSIC”) to operate the line-side interface circuit (“LSIC”) without relying on the telephone line as a primary source of power. The STIB may carry bi-directional data, clock and power signals.
FIG. 1 depicts a digital communication link according to an embodiment of the invention. Digital communication link 100 comprises SSIC 180 and LSIC 182, separated by STIB 136. Preferably, each of SSIC 180 and LSIC 182 are integrated respectively on a single integrated circuit. The STIB 136 is preferably a surface-mounted component with a high power capacity and low impedance. Each of SSIC 180 and LSIC 182 include at least one tri-state buffer 108, 156 connected to the STIB 136 (at nodes 126 and 138) for transmitting signals across the STIB 136. Each of SSIC 180 and LSIC 182 further includes a receive buffer 133, 176 connected to the STIB 136, for receiving signals transmitted by the other interface circuit. Each of buffers 108, 156, 133 and 176 are preferably amplifying-type buffers, which respectively amplify either the signal to be transmitted across the STIB 136 or the received signal received via the STIB 136.
In accordance with one embodiment of the invention, the switches comprising differential rectifying buffer 512 are operated as a synchronous rectifier. Diagram 610 depicts an exemplary state of the circuit, in which a “one” transmission bit is transmitted from SSIC 180 to LSIC 182 by closing switches M1S and M4S and opening switches M2S and M3S. A forward current loop is created from a supply source Vsply through switch M1S, through the primary winding of the STIB 136, and finally through switch M4S to ground (ignoring the internal resistances). On the line side, switches M1L and M4L are closed, while switches M2L and M3L are opened. As a result, the current that is imposed on the secondary winding of the STIB 136 flows through switch M1L, through load impedance RL, and finally through switch M4L, while at the same time charging supply capacitor CL.
EnF Enable Forward Transmission SelF Select Forward Transmission TxF+ Transmit Forward Data (Pos) - “Positive” differential input for data to be transmitted from the SSIC 180 to the LSIC 182 across the isolation barrier TxF− Transmit Forward Data (Neg) - “Negative” differential input for data to be transmitted from the SSIC 180 to the LSIC 182 across the isolation barrier RxR+ Received Reverse Data (Pos) - “Positive” differential input for data received by the SSIC 180 from the LSIC 182 across the isolation barrier RxR− Received Reverse Data (Neg) - “Positive” differential input for data received by the SSIC 180 from the LSIC 182 across the isolation barrier EnR Enable Reverse Transmission SelR Select Reverse Transmission TxR+ Transmit Reverse Data (Pos) - “Positive” differential input for data to be transmitted from the LSIC 182 to the SSIC 180 across the isolation barrier TxF− Transmit Reverse Data (Neg) - “Negative” differential input for data to be transmitted from the LSIC 182 to the SSIC 180 across the isolation barrier RxF+ Received Forward Data (Pos) - “Positive” differential input for data received by the LSIC 182 from the SSIC 180 across the isolation barrier RxF− Received Forward Data (Neg) - “Negative” differential input for data received by the LSIC 182 from the SSIC 180 across the isolation barrier
Once a given value for the RxF+ and RxF− signals is established, a positive feedback loop is created which effectively latches the values in, provided that the SelR signal is low and further assuming the tri-state buffer is “enabled” by an appropriate EnR signal. This latching effect may be a significant issue if the transistors on the SSIC 180 are not large enough to “overdrive” the transistors on the LSIC 182. Accordingly, an embodiment of the present invention provides a “break-before-make” switching scheme, as described above with reference to FIG. 6, to interrupt the latch and allow new transmission values to be imposed on the transformer. In particular, the EnR signal may be used to disable the tri-state buffers for a short time, thereby interrupting the latch and allowing the transmitting circuitry more easily to force the transformer to the next data state (either high or low). Alternatively, the Select lines (SelF and SelR) may also be used to disable or interrupt the latch.
The differential rectifying buffer configuration described above may also be applied in the SSIC 180, as shown in FIG. 5. During the TDM time interval when the SSIC 180 is to receive rather than transmit, tri-state buffers 108 and 114 are caused to latch to, and minor, the forward pulse stream transmitted by the LSIC 182, as a result of the positive feedback through mode switches MX1S and MX2S and tri-state buffers 108 and 114. At the end of each TDM bit period, just before a new value is to be transmitted by the LSIC 182, the SSIC 180 switches are briefly disabled (e.g., placed in a high-impedance state) for a short period of time in the same “break-before-make” fashion described above. The LSIC 182 thus has an opportunity to impose new data values on the transformer without interference from the SSIC drivers. When the SSIC 180 switches are re-enabled, the SSIC 180 latches to, and amplifies, the new value. In effect, a master-slave relationship arises between the transmitting circuitry and the receiving circuitry, wherein the slave circuit latches in the value that is transmitted by the master.
Embodiments of the present invention may also be implemented in a single-ended configuration, rather than a differential configuration. FIG. 7 depicts an exemplary single-ended embodiment. This embodiment is similar to the double-ended embodiment of FIG. 5, except that the negative terminals Vp− and Vs− of the transformer primary and secondary windings are connected to ground, and the primary terminals Vp+ and Vs+ are connected directly to RxR+ and RxF+, respectively. The single-ended embodiment depicted in FIG. 7 operates in the same manner as the double-ended embodiment of FIG. 5.
The chart in FIG. 8 illustrates the anticipated effectiveness of the power transfer between the system-side circuitry and the line-side circuitry using an embodiment of the present invention. More specifically, the y-axis represents the line-side supply voltage VddL generated across capacitor CL in the differential rectifying buffer embodiment described above. The x-axis represents the forward transmission ratio, which ranges between 0 and 1.0 (or 0% to 100%). It may be seen that the line-side supply voltage remains surprisingly stable (between 2.75 V and 2.79 V) regardless of the forward transmission ratio.
Embodiments of the present invention thus have several significant advantages over conventional DAAs. First, the transformer provides excellent high-voltage isolation between the primary and secondary windings. Second, common-mode noise rejection is greatly improved by the use of the STIB 136 and differential signaling across the interface. The latching technique described above further reduces common-mode noise, because the tri-state buffers are placed in a non-enabled state only for a very small portion of a standard bit period, so that even if common-mode noise were transferred across the barrier, it would only grow while the switches are disconnected (i.e., tri-stated). Third, because a single transformer is used as the isolation barrier for both data and power signals, there is a significant savings in component costs when compared with prior art systems that use multiple-component isolation barriers.
Finally, the use of STIB 136 allows a tremendous amount of power to be transferred from the SSIC to the LSIC, so that little, if any, power from a telephone line is needed for the LSIC. For example, in a typical modem, the line-side DAA and associated circuitry may require in the range of about 25 to about 50 milliwatts of power. Using embodiments of the present invention, this amount of power (about 25 to about 50 milliwatts) may readily be transferred from the system-side circuitry to the line-side circuitry—enough to operate the line-side circuitry without tapping power from the telephone line. In general, the amount of power that may be transferred using embodiments of the present invention is limited primarily by the current-carrying capacity of the complementary transistors in the tri-state buffer rather than the power-transfer capacity of the STIB 136. Thus, it is feasible to provide large complementary transistors in the line-side and system-side circuitry, such that more than 50 milliwatts, or even as much as about 100 milliwatts of power or more, may be transferred across the STIB 136.
It will be recognized that embodiments of the present invention may also be used in conjunction with prior art line-side circuits that tap power from a telephone line while a call is in progress (i.e., in an off-hook condition). If so, a portion of the line-side power may be obtained from the telephone line, while the remaining portion may be supplied by the system-side circuit in the manner described above. In this variation, any desired percentage (0% to 100%) of the power needed by the line-side circuit may be supplied from the system-side circuitry via embodiments of the present invention. Preferably, at least a substantial portion (e.g., about 30%) of the power needed by the line-side circuit during a call is supplied by the system-side circuitry across the STIB 136. Still more preferably, the amount power supplied by the system-side circuitry across the STIB 136 is at least a majority, at least a super-majority, or approximately the entirety of the power needed by the line-side circuit.
It should also be understood that although the system-side interface circuits, line-side interface circuits, rectifying buffer and transmission protocols of embodiments of the present invention have been described above in connection with the STIB 136, they are not limited to use with a transformer isolation barrier. Rather, they may be used with any transmission medium, including, for example, a four-port interface such as a two-wire twisted pair or a two-capacitor interface.
1. A signal-powered integrated circuit, comprising:
an integrated circuit die including a ground node, a supply node configured to provide a supply voltage to a plurality of circuits on the integrated circuit die, and a first terminal for receiving an input signal having data content and a predetermined energy;
a receive buffer formed on the integrated circuit die, connected to the first terminal and capable of receiving the data content associated with the input signal, the receive buffer having an output terminal configured to output the buffered input signal;
a rectifier formed on the integrated circuit die, the rectifier including a first diode connected between the first terminal and the ground node, and a second diode connected between the first terminal and the supply node;
a transmit buffer having an input terminal and an output terminal that is connected to the first terminal of the integrated circuit die; and
a feedback path connected between the output terminal of the receive buffer and the input terminal of the transmit buffer, and configured such that the buffered input signal passes through the feedback path to the input terminal of the transmit buffer;
wherein: the rectifier is capable of rectifying the input signal and passing at least a portion of the input signal's predetermined energy to the supply node, and each of the first and second diodes is capable of withstanding an ESD impulse.
2. The circuit of claim 1, wherein each diode in the rectifier is capable of withstanding an ESD impulse of at least about 1000 volts.
3. The circuit of claim 1, wherein each diode in the rectifier is capable of withstanding an ESD impulse in the range from about 1000 volts to about 2000 volts.
4. The circuit of claim 1, wherein the first and second diodes are parasitic diodes in a first transistor and a second transistor, respectively.
5. The signal-powered integrated circuit of claim 4, wherein the first and second transistors are complementary transistors in the transmit buffer.
6. The circuit of claim 1, wherein the average energy of the input signal is sufficiently large to cause the first and second diodes to operate as a rectifier.
7. The circuit of claim 1, wherein the first and second diodes are the primary devices or the only devices that protect the integrated circuit die from electrostatic discharge through the first terminal.
the input signal is a differential input signal formed by a first signal and a second signal complementary to the first, and the first terminal is capable of receiving the first signal;
the integrated circuit die further includes a second terminal capable of receiving the second signal;
the rectifier further includes a third diode connected between the second terminal and the ground node, and a fourth diode connected between the second terminal and the supply node;
the first, second, third and fourth diodes together provide full-wave rectification for the differential input signal; and
each of the third and fourth diodes is capable of withstanding an ESD impulse.
9. The signal-powered integrated circuit of claim 1, wherein the supply node is connected to the receive buffer to provide the supply voltage to the receive buffer.
10. The signal-powered integrated circuit of claim 1, wherein the receive buffer is an amplifying-type buffer that amplifies the input signal.
11. The signal-powered integrated circuit of claim 1, wherein the feedback path comprises:
a mode-selection switch that is (i) configured to receive (a) the buffered input signal and (b) a reverse transmit signal for transmission via the first terminal, and (ii) configured to select either the buffered input signal or the reverse transmit signal and to pass the selected signal to the transmit buffer's input terminal.
12. The signal-powered integrated circuit of claim 11, wherein the mode-selection switch is a multiplexer.
13. A method of powering an integrated circuit, comprising the steps of:
passing a first portion of the first input signal through a first receive buffer to produce a first buffered input signal;
passing the first buffered input signal through a first feedback path to an input terminal of a first transmit buffer having a first output terminal connected to the first terminal of the integrated circuit;
rectifying a second portion of the first input signal via a first diode connected between the first terminal and a ground node of the integrated circuit, and a second diode connected between the first terminal and a supply node configured to provide a supply voltage to a plurality of circuits on the integrated circuit; and
14. The method of claim 13, wherein each diode in the rectifier is capable of withstanding an ESD impulse of at least about 1000 volts.
15. The method of claim 13, wherein each diode in the rectifier is capable of withstanding an ESD impulse in the range from about 1000 volts to about 2000 volts.
16. The method of claim 13, wherein the first and second diodes are parasitic diodes in a first transistor and a second transistor, respectively.
17. The method of claim 13, wherein the first input signal has an average energy that is sufficiently large to enable the rectifier to rectify the input signal.
18. The method of claim 13, further comprising the step of protecting the integrated circuit from electrostatic discharge through the first terminal only by the first and second diodes.
passing a first portion of the second input signal through a second receive buffer to produce a second buffered input signal;
passing the second buffered input signal through a second feedback path to an input terminal of a second transmit buffer having an output terminal connected to the second terminal of the integrated circuit;
rectifying a second portion of the second input signal via a third diode connected between the second terminal and the ground node of the integrated circuit, and a fourth diode connected between the second terminal and the supply node of the integrated circuit, each diode being capable of withstanding an ESD impulse; and
20. The method of claim 13, further comprising providing the supply voltage to the first receive buffer from the supply node.
21. The method of claim 16, wherein the first and second transistors are complementary transistors in the first transmit buffer.
22. The method of claim 13, wherein passing the first buffered input signal through the first feedback path to the input terminal of the first transmit buffer comprises:
a mode-selection switch receiving (a) the first buffered input signal and (b) a reverse transmit signal for transmission via the first terminal, selecting either the first buffered input signal or the reverse transmit signal, and passing the selected signal to the first transmit buffer's input terminal.
23. The method of claim 22, wherein the mode-selection switch is a multiplexer.
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Patent Publication Number: 20100246695
Inventors: Boris A. Bark (Middletown, NJ), Brad L. Grande (Port Murray, NJ), Peter Kiss (Basking Ridge, NJ), Johannes G. Ransijn (Wyomissing Hills, PA), James D. Yoder (Leola, PA)
Application Number: 12/794,845
International Classification: H02H 9/00 (20060101); H04M 19/00 (20060101);