Source: http://www.google.com/patents/US8171185?dq=6,202,008
Timestamp: 2017-12-12 10:55:23
Document Index: 554883483

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Patent US8171185 - Electronic device and communication method - Google Patents
This invention provides an electronic device that can suppress the undesired influence of signals flowing on the bus as interference on devices connected to the bus. The electronic device has two ports connected to the bus with corresponding physical layer processing means. The physical layer processing...http://www.google.com/patents/US8171185?utm_source=gb-gplus-sharePatent US8171185 - Electronic device and communication method
Publication number US8171185 B2
Application number US 12/627,584
Also published as US20100217893
Publication number 12627584, 627584, US 8171185 B2, US 8171185B2, US-B2-8171185, US8171185 B2, US8171185B2
US 8171185 B2
wherein packet data input to said first node via said first communication path is output to said second communication path via said first node, said first physical layer, said internal communication line, said second physical layer, and said second port, and said first communication path and said second communication path operate as buses on the same protocol.
In this example, the IEEE 1394 bus operates as two buses 10 a and 10 b on different protocols. CPU 60 sets PHY parts 22 and 24 into the PHY unconnected mode. With this setting, PHY parts 22 and 24 are in the unconnected state. No data transfer is performed between them. CPU 60 set LLC parts 32 and 34 in the ON state. Communication device 20 is recognized as a node from other nodes connected to bus 10 a and is recognized as a node from other nodes connected to bus 10 b.
Data input from bus 10 a via port 16 to PHY part 22 is subjected to physical layer level processing by PHY part 22. This data is output to LLC part 32 and subjected to link layer level processing in LLC part 32. The data processed by LLC part 32 is output to packetizer 40. Packetizer 40 outputs the data input from LLC part 32 to CPU 60 via host I/F 58 and then to encryption part 44. Packetizer 40 outputs the processed data input from CPU 60 or encryption part 44 to LLC part 32. This data is subjected to link layer level processing by LLC part 32 and then output to PHY part 22. PHY part 22 performs physical layer level processing. This data is then output via port 16 to bus 10 a.
Data input via port 18 from bus 10 b to PHY part 24 is physical layer level processed by PHY part 24. This data is then output to LLC part 34. LLC part 34 performs link layer level processing. The data processed by LLC part 34 is output to packetizer 40. Packetizer 40 outputs the data input from LLC part 34 to CPU 60 via host I/F 58. This data is then output to encryption part 44.
Data processed by CPU 60 or encryption part 44 is input to packetizer 40 and then output to LLC part 34. LLC part 34 subjects this data to link layer level processing and outputs the data to PHY part 24. PHY part 24 performs physical layer level processing and outputs this data via port 18 to bus 10 b.
In Operation Example 2, the bus of IEEE 1394 is divided into two buses, buses 10 a and 10 b, which use different protocols. When a bus reset occurs on bus 10 a due to an increase or decrease in the number of nodes caused by removal or insertion of node or the turning ON or OFF of the power supply, the bus reset signal is transferred by only bus 10 a and not by bus 10 b. Bus reset processing is performed by nodes connected to bus 10 a. No bus reset processing is not performed by nodes connected to bus 10 b. Thus for nodes connected to bus 10 b, when data are transferred in the AKE protocol, AKE is not interrupted by a bus reset on bus 10 a.
In Operation Example 2, with LLC bus 54 set in the connected state, it is possible to perform information transfer (bridge operation) on the link layer level between the node connected to bus 10 a and the node connected to bus 10 b. LLC parts 32 and 34 can operate as a single LLC part.
Once packetizer 40 processes data input from CPU 60 or encryption part 44 it outputs to PHY part 22. This data is subjected to link layer level processing in LLC part 32 and then output to PHY part 22. PHY part 22 physical level processes the data which is then output via port 16 to bus 110 a.
PHY part 24 physical layer level processes data input via port 18 from bus 110 b. PHY part 24 outputs this data are output to LLC part 34. LLC part link layer level processes this data and then outputs to packetizer 40. Packetizer 40 outputs the input data input from LLC part 34 to CPU 60 via host I/F 58 and to encryption part 44.
In Operation Example 2, the IEEE 1394 bus is divided via protocol into two buses, buses 110 a and 110 b. When a bus reset takes place with respect to bus 110 a due to an increase or decrease in the number of nodes caused by removal or insertion of AV-HDD 140, optical disk driver 150 and personal computer 160 or the turning ON or OFF of a power supply, the bus reset signal is transmitted only within bus 110 b and is not transmitted within bus 110 a. Bus reset processing is performed only for the nodes connected to bus 110 b, while no bus reset processing is performed for the nodes connected to bus 110 a. Thus for data transferred by AKE protocol between AV-HDD 130 and DTV 120 connected to bus 110 a, AKE is not interrupted by a bus reset on bus 110 b.
US7747793 * Nov 9, 2007 Jun 29, 2010 Xilinx, Inc. Method and apparatus for controlling a distributed buffering system having configurable circuitry
JP2000174786A Title not available
U.S. Classification 710/33, 710/20, 710/10
Cooperative Classification H04L12/40052, H04L12/40078
European Classification H04L12/40F4, H04L12/40F
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NAKAMURA, TORU;REEL/FRAME:024340/0574