Source: http://www.google.com/patents/US8019975?dq=%22Meaning-based+information+organization+and+retrieval%22
Timestamp: 2017-09-25 20:59:34
Document Index: 759411004

Matched Legal Cases: ['Application No. 1994', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 1994', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000']

Patent US8019975 - System and method for handling load and/or store operations in a superscalar ... - Google Patents
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order...http://www.google.com/patents/US8019975?utm_source=gb-gplus-sharePatent US8019975 - System and method for handling load and/or store operations in a superscalar microprocessor
Publication number US8019975 B2
Application number US 11/113,135
Also published as US6230254, US6735685, US6957320, US6965987, US7447876, US7844797, US7861069, US20020188829, US20040128487, US20050188184, US20050283591, US20070101106, US20090217001
Publication number 11113135, 113135, US 8019975 B2, US 8019975B2, US-B2-8019975, US8019975 B2, US8019975B2
Patent Citations (157), Non-Patent Citations (99), Referenced by (4), Classifications (32), Legal Events (3)
US 8019975 B2
mov ebx, [ecx] EBX <-- [1201] = 8765_0001
or [eax], ebx [EAX] <-- 0000_4321 or
8765_0000 = 8765_4321
(SIZE_16) EBX <-- [0100 + 3] = [0103] = FF87 -> 8765_FF8
mov ebx, [eax + 3]
US4279014 Aug 14, 1978 Jul 14, 1981 Compagnie Internationale pour 1'Informatique CII-Honeywell Bull (Societe Anonyme) Arrangement for converting virtual addresses into physical addresses in a data processing system
US5659782 Sep 16, 1994 Aug 19, 1997 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
DE3603240C2 Feb 3, 1986 May 26, 1988 Siemens Ag, 1000 Berlin Und 8000 Muenchen, De Title not available
EP0147775B1 Dec 18, 1984 Jun 5, 1991 Hitachi, Ltd. Data processing apparatus for processing operand store conflict
EP0170398A3 Jun 26, 1985 Jun 1, 1988 Unisys Corporation Programme scanner for a processor having plural data and instruction streams
EP0171595B1 Jul 9, 1985 Apr 17, 1991 International Business Machines Corporation Floating point arithmetic unit
EP0302999B1 Apr 21, 1988 Sep 15, 1993 International Business Machines Corporation Out-of-sequence operand fetches
EP0368332B1 Nov 10, 1989 Sep 24, 1997 Hitachi, Ltd. Pipeline data processor
EP0377990B1 Dec 20, 1989 May 2, 1997 International Business Machines Corporation Data processing systems
EP0402856B1 Jun 12, 1990 Jan 28, 1998 Nec Corporation Instruction execution control system
EP0426393B1 Oct 26, 1990 Jan 7, 1998 Fujitsu Limited Instructing method and execution system
EP0479390B1 Oct 3, 1991 Jan 7, 1999 Philips Electronics N.V. Processing device including a memory circuit and a group of functional units
FR2575564B1 Title not available
GB2241801B Title not available
4 Advisory Action for U.S. Appl. No. 11/640,968, dated Jun. 4, 2010.
5 Agerwala et al., "High Performance Reduced Instruction Set Processors," IBM Research Division, Mar. 31, 1987, pp. 1-61.
6 Aiken, A. and Nicolau, A., "Perfect Pipelining: A New Loop Parallelization Technique," pp. 221-235.
7 Anderson, D.W. et al., "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling", IBM Journal, Jan. 1967, pp. 8-24.
8 Andrews, W., "Distinctions Blur Between DSP Solutions," Computer Design, vol. 28, No. 9, May 1, 1989, Littleton, Mass., pp. 86-99.
9 Bakoglu, H.B. et al., "IBM Second-Generation RISC Machine Organization", 1990 IEEE, pp. 173-178.
10 Boland, L.J., et al., "The IBM System/360 Model 91: Storage System", IBM Journal, Jan. 1967, pp. 54-68.
11 Charlesworth, A.E., "An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family," Computer, vol. 14, Sep. 1981, pp. 18-27.
12 Colwell, R.P. et al., "A VLIW Architecture for a Trace Scheduling Compiler," Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 5-8, 1987, California, pp. 180-192.
13 Crawford, J., "The Execution Pipeline of the Intel i486 CPU," IEEE, 1990, pp. 254-258.
14 Decision of Final Rejection received Oct. 24, 2003 in Japanese Appl. No. JP 2000-008264, (3 pages) with translation (3 pages).
15 Decision of Final Rejection received Oct. 24, 2003 in Japanese Appl. No. JP 2000-008267, (3 pages) with translation (3 pages).
16 Decision of Final Rejection received Oct. 24, 2003 in Japanese Appl. No. JP2000-008265, (3 pages) with translation (3 pages).
17 Decision of Final Rejection received Oct. 24, 2003 in Japanese Appl. No. JP2000-008266, (3 pages) with translation (4 pages).
19 English-language translation of Japanese Laid-Open Patent Application No. H2-130634, (May 18, 1990—date of publication), 56 pages.
20 English-language translation of Japanese Laid-Open Patent Application No. H2-148238, (Jun. 7, 1990—date of publication), 15 pages.
21 English-language translation of Japanese Laid-Open Patent Application No. H4-77925, (Mar. 12, 1992—date of publication), 33 pages.
22 English-language translation of Japanese Laid-Open Patent Application No. S58-217054, (Dec. 16, 1983—date of publication), 18 pages.
23 English-language translation of Japanese Laid-Open Patent Application No. S59-154548, (Sep. 3, 1984—date of publication), 15 pages.
24 English-language translation of Japanese Laid-Open Patent Application No. S61-33546, (Feb. 17, 1986—date of publication), 25 pages.
25 English-language translation of Kuga, M. et al., "Low-Level Parallel Processing Algorithms for the "Shinpu" Processor Based on the SIMP (Single Instruction Stream/Multiple Instruction Pipelining) Method," Transactions of Information Processing Society of Japan, Information Processing Society of Japan, vol. 30, No. 12, Dec. 1989, pp. 1603-1624.
26 English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 1994-509063, mailed Aug. 27, 2002, 5 pages.
27 English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 2000-008263, mailed Aug. 14, 2002, 5 pages.
28 English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 2000-008266, mailed Aug. 14, 2002, 5 pages.
29 English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 2000-008267, mailed Aug. 16, 2002, 6 pages.
30 English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 2000-008268, mailed Aug. 14, 2002, 5 pages.
31 English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 2000-008271, mailed Aug. 14, 2002, 5 pages.
32 Faix, M. and Schuenemann, C., "Combined Macro/Micro Program Machine," IBM Technical Disclosure Bulletin, vol. 14, No. 1, Jun. 1971, p. 298.
33 Final Office Action for U.S. Appl. No. 11/640,968, dated Feb. 19, 2010.
34 Foster et al., "Percolation of Code to Enhance Parallel Dispatching and Execution," IEEE Trans. on Computers, Dec. 1971, pp. 1411-1415.
35 Garth, S.C.J., "Combining RISC and CISC in PC Systems," IEEE, pp. 10/1-10/5.
36 Goodman, J.R. and Hsu, W., "Code Scheduling and Register Allocation in Large Basic Blocks," ACM, 1988, pp. 442-452.
37 Gross et al., "Optimizing Delayed Branches," Proceedings of the 5th Annual Workshop on Microprogramming, Oct. 5-7, 1982, pp. 114-120.
38 Groves, R.D. and Oehler, R., "An IBM Second Generation RISC Processor Architecture," IEEE, 1989, pp. 134-137.
39 Heath, S., "Architectural considerations for a M88000 superscalar RISC processor," pp. 6/1-6/6.
40 Hennessy et al., Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Inc., 1990 (in its entirety).
41 Horst, R.W. et al., "Multiple Instruction Issue in the NonStop Cyclone Processor," IEEE, 1990, pp. 216-226.
42 Hwu et al., "Checkpoint Repair for High-Peformance Out-of-Order Execution Machines," IEEE Trans. on Computers, vol. C-36, No. 12, Dec. 1987, pp. 1496-1514.
43 Hwu et al., "Exploiting Parallel Microprocessor Microarchitectures with a Compiler Code Generator," Proceedings of the 15th Annual Symposium on Computer Architecture, Jun. 1988, pp. 45-53.
44 Hwu et al., "HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality," Proceedings from ISCA-13, Tokyo, Japan, Jun. 2-5, 1986, pp. 297-306.
45 i486™ Microprocessor Hardware Reference Manual, Order No. 240552, Intel Corporation, Santa Clara, California, 1990.
46 i486™ Microprocessor Programmer's Reference Manual, Order No. 240486, Intel Corporation, Santa Clara, California, 1990.
47 IBM Journal of Research and Development, vol. 34, No. 1, Jan. 1990, pp. 1-70.
48 Jelemensky, J. et al., "New Microcomputer Features Advanced Hardware for Real-Time Control Applications," Electro Conference Record, vol. 14, Apr. 11, 1989, Los Angeles, CA, pp. 1-9.
49 Johnson, M., Superscalar Microprocessor Design, Prentice Hall, 1991, pp. 50-53 and pp. 147-163.
50 Johnson, M., Superscalar Microprocessor Design, Prentice-Hall, Inc., 1991.
51 Johnson, William M., Super-Scalar Processor Design, (Dissertation), Copyright 1989, 134 pages.
52 Jouppi et al., "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines," Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 1989, pp. 272-282.
53 Jouppi, N.H., "Integration and Packaging Plateaus of Processor Performance," IEEE, 1989, pp. 229-232.
54 Jouppi, N.P., "The Nonuniform Distribution of Instruction-Level and Machine Parallelism and its Effect on Performance," IEEE Transactions on Computers, vol. 38, No. 12, Dec. 1989, pp. 1645-1658.
55 Keller, R.M., "Look-Ahead Processors," Computing Surveys, vol. 7, No. 4, Dec. 1975, pp. 177-195.
56 Kuga, M. et al., "Low-Level Parallel Processing Algorithms for the "Shinpu" Processor Based on the SIMP (Single Instruction Stream/Multiple Instruction Pipelining) Method," Transactions of Information Processing Society of Japan, Information Processing Society of Japan, vol. 30, No. 12, Dec. 1989, pp. 1603-1611.
57 Lam, M.S., "Instruction Scheduling for Superscalar Architectures," Annu. Rev. Comput. Sci., vol. 4, 1990, pp. 173-201.
58 Lee, R.B., "Precision Architecture," Computer, Jan. 1989, pp. 78-91.
59 McGeady, S., "The i960CA Superscalar Implementation of the 80960 Architecture", 1990 IEEE, pp. 232-240.
60 McNeley, K.J. and Milutinovic, V.M., "Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer," IEEE Micro, vol. 7, No. 1, pp. 60-71, Feb. 1987.
61 Melear, C., "The Design of the 88000 RISC Family," IEEE Micro, vol. 9, No. 2, Apr. 1989, Los Alamitos, CA, pp. 26-38.
62 Murakami, K. et al., "SIMP (Single Instruction stream/Multiple instruction Pipelining): A Novel High-Speed Single-Processor Architecture," ACM, 1989, pp. 78-85.
63 Nakano, H. et al., "A 80 Mflops 64-bit Microprocessor for Parallel Computer", IEEE 1991 Custom Integrated Circuits Conference, pp. 15.2.1-15.2.4.
64 Notice of Allowance for U.S. Appl. No. 12/436,607, dated Jul. 22, 2010.
65 Notification of Reason for Refusal for Japanese Patent Application No. 1994-509063, mailed Aug. 27, 2002, 3 pages.
66 Notification of Reason for Refusal for Japanese Patent Application No. 2000-008263, mailed Aug. 14, 2002, 3 pages.
67 Notification of Reason for Refusal for Japanese Patent Application No. 2000-008266, mailed Aug. 14, 2002, 3 pages.
68 Notification of Reason for Refusal for Japanese Patent Application No. 2000-008267, mailed Aug. 16, 2002, 3 pages.
69 Notification of Reason for Refusal for Japanese Patent Application No. 2000-008268, mailed Aug. 14, 2002, 3 pages.
70 Notification of Reason for Refusal for Japanese Patent Application No. 2000-008271, mailed Aug. 14, 2002, 3 pages.
71 Odnert, D. et al., "Architecture and Compiler Enhancements for PA-RISC Workstations," Proceedings from IEEE Compcon, Feb. 25-Mar. 1, 1991, San Francisco, CA, pp. 214-218.
72 Office Action for U.S. Appl. No. 12/436,607, dated Mar. 5, 2010.
73 Ohr, S., "Superlong instructions help supermini refine number crunching," Electronic Design, vol. 33, No. 26, Nov. 1985.
74 Patent Abstracts of Japan, vol. 009, No. 006 (P-326), Jan. 11, 1985.
75 Patent Abstracts of Japan, vol. 010, No. 089, Apr. 1986, & JP, A, 60 225 943 (Hitachi Seisakusho K K) Nov. 11, 1985.
76 Patent Abstracts of Japan, vol. 017, No. 082 (P-1489), Feb. 18, 1993.
77 Patent Abstracts of Japan, vol. 017, No. 084 (P-1490), Feb. 19, 1993.
78 Patt et al., "Critical Issues Regarding HPS, A High Performance Microarchitecture," Proceedings of the 18th Annual Workshop on Microprogramming, Dec. 1985, pp. 109-116.
79 Patt et al., "HPS, A New Microarchitecture: Rationale and Introduction," Proceedings of the 18th Annual Workshop on Microprogramming, Dec. 1985, pp. 103-108.
80 Pleszkun et al., "The Performance Potential of Multiple Functional Unit Processors," Proceedings of the 15th Annual Symposium on Computer Architecture, Jun. 1988, pp. 37-44.
81 Pleszkun et al., "WISQ: A Restartable Architecture Using Queues," Proceedings of the 14th International Symposium on Computer Architecture, Jun. 1987, pp. 290-299.
82 Popescu, V. et al., "The Metaflow Architecture," IEEE Micro, Jun. 1991, pp. 10-13 & 63-73.
83 Smith et al., "Implementation of Precise Interrupts in Pipelined Processors," Proceedings of the 12th Annual International Symposium on Computer Architecture, Jun. 1985, pp. 36-44.
84 Smith et al., "Limits on Multiple Instruction Issue," Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 1989, pp. 290-302.
85 Smith, J.E. et al., "Implementing Precise Interrupts in Pipelined Processors," IEEE Transactions on Computers, vol. 37, No. 5, May 1998, pp. 562-573.
86 Smith, M.D. et al., "Boosting Beyond Static Scheduling in a Superscalar Processor," IEEE, 1990, pp. 344-354.
87 Sohi et al., "Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors," 14th Annual Int'l Symposium on Computer Architecture, Jun. 2-5, 1987, pp. 27-34.
88 Tetsuya Hara et al., "Organizations of an Extended Superscalar Processor Prototype Based on the SIMP (Single Instruction Stream/Multiple Instruction Pipelining) Architecture", Electronic Information Communication Society Technical Research Report CPSY90-38-63, Electronic Information Communication Society, Inc., Jul. 20, 1990, vol. 90, No. 144, pp. 103-108 (with English language translation, 14 pages).
89 Thornton, J.E., Design of a Computer: The Control Data 6600, Control Data Corporation, 1970, pp. 58-140.
90 Tjaden et al., "Detection and Parallel Execution of Independent Instructions," IEEE Trans. on Computers, vol. C-19, No. 10, Oct. 1970, pp. 889-895.
91 Tjaden et al., "Representation of Concurrency with Ordering Matrices," IEEE Trans. on Computers, vol. C-22, No. 8, Aug. 1973, pp. 752-761.
92 Tjaden, Representation and Detection of Concurrency Using Ordering Matrices, (Dissertation), 1972, pp. 1-199.
93 Tomasulo, R.M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal, vol. 11, Jan. 1967, pp. 25-33.
94 Turley, James L., Advanced 80386 Programming Techniques, © 1998, McGraw-Hill, Inc., pp. 45-84 and 117-168.
95 Uht, A.K., "An Efficient Hardware Algorithm to Extract Concurrency From General-Purpose Code," Proceedings of the 19th Annual Hawaii International Conference on System Sciences, 1986, pp. 41-50.
96 Wedig, R.G., Detection of Concurrency in Directly Executed Language Instruction Streams, (Dissertation), Jun. 1982, pp. 1-179.
97 Weiss et al., "Instruction Issue Logic in Pipelined Supercomputers," Reprinted from IEEE Trans. on Computers, vol. C-33, No. 11, Nov. 1984, pp. 1013-1022.
98 Weiss, R., "Third-Generation RISC Processors," EDN, Mar. 30, 1992, pp. 96-108.
99 Wharton, J. J., "Parallel 486 pipelines produce peak processor performance," Microprocessor Report, vol. 3, No. 6, Jun. 1989, p. 13(5).
U.S. Classification 712/225, 712/23, 712/220
International Classification G06F7/38, G06F9/44, G06F9/00, G06F15/00, G06F9/38, G06F15/76, G06F9/312, G06F9/318
Cooperative Classification G06F9/30087, G06F9/30043, G06F9/3017, G06F9/3836, G06F9/3834, G06F9/3885, G06F9/3838, G06F9/3004, G06F9/3857, G06F9/3855
European Classification G06F9/38E, G06F9/38D4, G06F9/30A2L, G06F9/30A2, G06F9/30A8S, G06F9/38D1, G06F9/38T, G06F9/38E6, G06F9/30U2, G06F9/30U, G06F9/38D