Source: http://www.google.com/patents/US5917225?dq=6,606,102
Timestamp: 2018-01-17 08:13:56
Document Index: 799712921

Matched Legal Cases: ['Application No. 3', 'Application No. 4', 'Application No. 4', 'Application No. 4', 'Application No. 4', 'Application No. 3']

Patent US5917225 - Insulated gate field effect transistor having specific dielectric structures - Google Patents
In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate electrode and the gate insulating film to prevent invasion of movable...http://www.google.com/patents/US5917225?utm_source=gb-gplus-sharePatent US5917225 - Insulated gate field effect transistor having specific dielectric structures
Publication number US5917225 A
Application number US 08/721,052
Also published as CN1051882C, CN1081022A
Publication number 08721052, 721052, US 5917225 A, US 5917225A, US-A-5917225, US5917225 A, US5917225A
Inventors Shunpei Yamazaki, Hongyong Zhang, Yasuhiko Takemura
Patent Citations (47), Non-Patent Citations (2), Referenced by (125), Classifications (19), Legal Events (3)
Insulated gate field effect transistor having specific dielectric structures
US 5917225 A
1. An insulated gate thin film transistor comprising:
a semiconductor layer comprising crystalline silicon formed on an insulating surface of a substrate;
a channel region formed within said semiconductor layer;
source and drain regions formed within said semiconductor layer with said channel region therebetween;
a first insulating film comprising silicon oxide formed on said channel region;
a second insulating film formed on said first insulating film; and
a gate electrode formed over said channel region with said first and second insulating films interposed therebetween,
said transistor characterized in that said second insulating film comprises a material selected from the group consisting of silicon nitride and aluminum oxide, and that said second insulating film extends beyond side edges of said gate electrode but does not cover a major surface of said source and drain regions,
wherein said first insulating film is thicker than said second insulating film.
2. The transistor of claim 1 wherein said material of the second insulating film is silicon nitride.
5. An insulated gate thin film transistor comprising:
said transistor characterized in that said second insulating film comprises a material selected from the group consisting of silicon nitride and aluminum oxide, and that said first insulating film is thicker than said second insulating film.
6. The transistor of claim 5 wherein said material of the second insulating film is silicon nitride.
10. An insulated gate thin film transistor comprising:
a second insulating film formed on said first insulating film wherein said first insulating film is thicker than said second insulating film; and
said transistor characterized in that said second insulating film comprises a material selected from the group consisting of silicon nitride and aluminum oxide, and that said second insulating film extends beyond side edges of said gate electrode but does not cover a major surface of said source and drain regions while said first insulating film covers the major surface of said source and drain regions except for contact portions thereof.
11. The transistor of claim 10 wherein said material of the second insulating film is silicon nitride.
14. An insulated gate field effect transistor comprising:
a gate insulating film formed on said semiconductor layer; and
said transistor characterized in that said gate insulating film comprises at least a first insulating film comprises silicon oxide and a second insulating film comprises silicon nitride which is thinner than said first insulating film, and that at least said second insulating film extends beyond side edges of said gate electrode to cover a part of said source and drain regions.
15. The insulated gate field effect transistor according to claim 14 wherein the thickness of said first insulating film is 50 to 200 nm.
17. An insulated gate field effect transistor comprising:
said transistor characterized in that said gate insulating film comprises at least a first insulating film comprises silicon oxide and a second insulating film comprises silicon nitride, that said first insulating film is thicker than said second insulating film.
18. The insulated gate field effect transistor according to claim 17 wherein the thickness of said first insulating film is 50 to 200 nm.
20. An insulated gate field effect transistor comprising:
a semiconductor layer comprising crystalline silicon formed over a substrate;
a pair of impurity regions formed within said semiconductor layer with said channel region therebetween;
a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and
a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween,
wherein at least said second insulating film extends beyond side edges of the gate electrode,
21. An insulated gate field effect transistor according to claim 20 wherein said pair of impurity regions are source and drain regions of the transistor.
26. An insulated gate field effect transistor comprising:
27. An insulated gate field effect transistor according to claim 26 wherein said pair of impurity regions are source and drain regions of the transistor.
32. An insulated gate field effect transistor comprising:
a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising aluminum oxide; and
wherein, said first insulating film is thicker than said second insulating film.
33. An insulated gate field effect transistor according to claim 32 wherein said pair of impurity regions are source and drain regions of the transistor.
36. An insulated gate field effect transistor comprising:
wherein said first insulting film is thicker than said second insulating film and the thickness of said first insulating film is 50 to 200 nm.
37. An insulated gate field effect transistor comprising:
a gate insulating film adjacent to said semiconductor layer, including at least a first insulting film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and
wherein said first insulating film is thicker than said second insulating film and the thickness of said second insulating film is 2 to 50 nm.
38. An insulated gate field effect transistor comprising:
wherein said first insulating film is thicker than said second insulating film and the thickness of said first insulating film is 50 to 200 nm.
39. An insulated gate field effect transistor comprising:
40. The insulated gate field effect transistor according to claim 32 wherein the thickness of said first insulating film is 50 to 200 nm while the thickness of said second insulating film is 2 to 50 nm.
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 101. This glass has high strain temperature, but contains a large amount of lithium and natrium. Therefore, in order to prevent invasion of these movable ions from the substrate, a silicon nitride film 102 was formed in thickness of 10 to 50 nm on the substrate by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film serving as a sealer was formed in thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600° C. for 12 to 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process by the photolithography and the reactive ion etching (RIE) method, thereby forming islandish semiconductor regions 104 (for N-channel TFT) and 105 (for P-channel TFT) as shown in FIG. 1(A).
Through these processes, the structure as shown in FIG. 1(C) was obtained. Naturally, the portion doped with the impurity by the ion injection method had low crystallinity, and thus it was substantially in a non-crystal state (amorphous state, or a polycrystal state close to the amorphous state). Therefore, a laser anneal treatment was conducted to restore crystallinity at the portion. This process may be carried out by a heat annealing treatment at 600 to 850° C. The same laser annealing condition as disclosed in Japanese Patent Application No. 3-237100 for example was adopted.
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 1. This glass has high strain temperature, but contains a large amount of lithium and natrium. Therefore, in order to prevent invasion of these movable ions from the substrate, a silicon nitride film 2 was formed in thickness of 10 to 50 nm on the substrate by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film serving as a sealer was formed in thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600° C. for 12 to 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process by the photolithography and the reactive ion etching (RIE) method, thereby forming islandish semiconductor regions 4 (for N-channel TFT) and 105 (for P-channel TFT) as shown in FIG. 4(A).
Through these processes, the structure as shown in FIG. 4(D) was obtained. Naturally, the portion doped with the impurity by the ion injection method had low crystallinity, and thus it was substantially in a non-crystal state (amorphous state, or a polycrystal state close to the amorphous state). Therefore, a laser anneal treatment was conducted to restore crystallinity at the portion. This process may be carried out by a heat annealing treatment at 600 to 850° C. The same laser annealing condition as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 to 450° C. under hydrogen atmosphere (1 to 700 torr, preferably 500 to 700 torr), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.).
Through these processes, the structure as shown in FIG. 5(D) was obtained. In the laser doping technique, unlike the Embodiment 4, no laser annealing process or no heat annealing process is required because the injection of the impurities and the annealing treatment are simultaneously carried out. After the laser doping treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 to 450° C. under hydrogen atmosphere (1 to 700 torr or 500 to 700 torr), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.).
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 501. A silicon nitride film 502 was formed in thickness of 10 to 50 nm on the substrate by the plasma CVD method or the low pressure CVD method. Further, a silicon oxide film 503 serving as a sealer was formed in thickness of 100 to 800 nm by the sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness or 20 to 100 nm by the plasma CVD method, and annealed at 600° C. for 12 to 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process to form islandish semiconductor regions 504 (for N-channel TFT) and 505 (for P-channel TFT) as shown in FIG. 6(A).
Through these processes, the structure as shown in FIG. 6(D) was obtained. Naturally, the crystallinity of the portions to which the impurities were injected by the ion injection was extremely low, and these portions were substantially in a non-crystal state (amorphous state or polycrystal state close to the amorphous state). Therefore, the crystallinity was restored by the laser annealing treatment. This process may be replaced by the heat annealing treatment at 600 to 850° C. The condition for the laser annealing treatment as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. Here, no short-wavelength ultraviolet rays below 250 nm wavelength is passed through the silicon nitride film 507, so that XeCl laser (308 nm wavelength) or XeF laser (351 nm wavelength) was used.
After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 to 450° C. under hydrogen atmosphere (1 to 700 torr or 500 to 700 torr), to thereby depress lattice defects (dangling bond, etc.). Actually, delivery of hydrogen was little carried out between the inside of the semiconductor region and the outside thereof because the silicon nitride film 507 exists. Therefore, a large amount of hydrogen atoms are simultaneously injected into the semiconductor region in the plasma doping method, and on the other hand, in the ion injection method, a process of injecting hydrogen atoms is separately required. If the amount of hydrogen atoms is insufficient, hydrogen atoms are required to be separately doped even in the plasma doping method.
An N--O glass produced by Nippon Electric Glass Co., Ltd was used as a substrate 1001. This glass has high strain temperature, however, contains a large amount of lithium and natrium. Therefore, in order to prevent invasion of these movable ions from the substrate and in order to prevent the over-etching, an aluminum oxide film 1002 was formed on the substrate 1001 in thickness of 10 to 50 nm by an organic metal CVD method. Further, a silicon oxide film 1003 serving as a sealer was formed on the aluminum oxide film 1002 in thickness of 100 to 800 nm by the sputtering method. An amorphous silicon film was formed in thickness of 20 to 100 nm on the silicon oxide film 1003 by the plasma CVD method, and then annealed at 600° C. for 12 to 72 hours at nitrogen atmosphere to be crystallized. The result was subjected to the patterning process by the photolithography and the reactive ion etching (RIE) method to form islandish semiconductor regions 1004.
Subsequently, N-type impurity was doped into the semiconductor region 1004 by the well-known ion injection method to form N-type impurity regions (source, drain) 1005 and 1006. In the manner as described above, the structure as shown in FIG. 13(A) was obtained. Naturally, the crystallinity at the portion doped with the impurities by the ion injection method was extremely low, and this portion was substantially in a non-crystal (amorphous state, or polycrystal state close to the amorphous state). Therefore, the crystallinity at the portion was restored by the laser annealing treatment. This process may be replaced by the heat annealing treatment at 600 to 850° C. The laser annealing condition as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 to 450° C. under hydrogen atmosphere (1 to 700 torr, preferably 500 to 700 torr) to inject hydrogen atoms into the semiconductor region and depress the lattice defect (dangling bond, etc.).
Thereafter, an aluminum film was formed by the sputtering method or the electron beam deposition method, and then subjected to a patterning process to form gate electrode/wirings 1107 to 1109. Further, current was supplied to the gate electrode/wirings 1107 to 1109 in the electrolyte to form aluminum oxide films 1110 to 1112 by the anodic oxidation method. The anodic oxidation condition as disclosed in Japanese Patent Application No. 4-30220 which was invented by the inventor of this application, et.al was adopted in this embodiment. Further, by the laser doping technique (Japanese Patent Application No. 3-283981) which was invented by the inventor of this application, et.al, N-type impurity was doped into the semiconductor region 1104, thereby forming an N-type impurity region (source, drain). The laser doping method requires no laser annealing treatment and no heat annealing treatment which were required for the Embodiment 8 because the injection of the impurities and the annealing treatment were simultaneously carried out. After the laser doping treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 to 450° C. under hydrogen atmosphere (1 to 700 torr or 500 to 700 torr), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.). This state is shown in FIG. 14(A).
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U.S. Classification 257/411, 438/287, 257/347, 257/72, 438/216, 438/591
International Classification H01L29/78, H01L29/786, H01L21/336, H01L31/0392
Cooperative Classification H01L29/78603, H01L27/1218, H01L29/78636, H01L29/4908, H01L29/04
European Classification H01L29/49B, H01L29/786A, H01L29/786B6, H01L27/12T