Source: http://www.google.com/patents/US4958184?ie=ISO-8859-1
Timestamp: 2014-03-13 12:22:18
Document Index: 616276609

Matched Legal Cases: ['art.\n3', 'art.\n5', 'art 101', 'art 101', 'art 101', 'art 104', 'art 104', 'art 104', 'art 201', 'art 202', 'art 201', 'art 202', 'art 206', 'art 202', 'art 206', 'art 208', 'art 208', 'art 208', 'arts 101', 'art 208', 'art 208', 'art 104', 'art 104', 'art 205', 'art 205', 'art 203', 'art 203', 'arts 203', 'art 104', 'art 106', 'art 201']

Patent US4958184 - Display device for use in a camera - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA display device for use in a camera comprises a central processing unit and display units to display exposure data and various control modes under the control of the CPU. The display units are arranged to display the exposure data with suitable marks or characters in rows so as to make the operator...http://www.google.com/patents/US4958184?utm_source=gb-gplus-sharePatent US4958184 - Display device for use in a cameraAdvanced Patent SearchPublication numberUS4958184 APublication typeGrantApplication numberUS 07/308,991Publication dateSep 18, 1990Filing dateFeb 9, 1989Priority dateDec 14, 1984Fee statusLapsedAlso published asUS4847651, US5014083, US5113217Publication number07308991, 308991, US 4958184 A, US 4958184A, US-A-4958184, US4958184 A, US4958184AInventorsAkihiko Fujino, Manabu Inoue, Shuji Izumi, Kunio Kawamura, Masaaki Nakai, Masatake Niwa, Yuji TakarabeOriginal AssigneeMinolta Camera Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (16), Referenced by (5), Classifications (5), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetDisplay device for use in a cameraUS 4958184 AAbstract A display device for use in a camera comprises a central processing unit and display units to display exposure data and various control modes under the control of the CPU. The display units are arranged to display the exposure data with suitable marks or characters in rows so as to make the operator to read the display easily. The CPU provides control data to deenergize the display unit at the time of initial states of the camera such as at the time of loading a battery in the camera to prevent to display confusing information.
What is claimed is: 1. A display device for use in a camera provided with a plurality of exposure control modes including a shutter time priority automatic exposure control mode and a diaphragm aperture priority automatic exposure control mode, said display device comprising:a first display part for displaying a shutter time value; a second display part for displaying a diaphragm aperture value; a third display part for indicating the shutter time priority automatic exposure control mode; and a fourth display part for indicating the diaphragm aperture priority automatic exposure control mode, said first display part, said third display part, said fourth display part and said second display part being arranged in the order thereof and in a row. 2. A display device according to claim 1, wherein the exposure control modes include a programmed automatic exposure control mode, and said display device further comprising a fifth display part for indicating the programmed automatic exposure control mode; said fifth display part being disposed between said third display part and said fourth display part.
3. A display device for use in a camera operable in a shutter time priority automatic exposure control mode or in a diaphragm aperture priority automatic exposure control mode, said display device comprising:first display means for displaying a shutter time value and a diaphragm aperture value to be manually set in the shutter time priority automatic exposure control mode and the diaphragm aperture priority automatic exposure control mode, respectively; and second display means arranged in a row with respect to said first display means, for indicating the shutter time priority automatic exposure control mode and the diaphragm aperture priority automatic exposure control mode and having a partially characteristic shape directing to said first display means, and wherein said first display means includes a first display part for displaying the shutter time value and a second display part for displaying the diaphragm aperture value and said second display means includes a third display part for indicating the shutter time priority automatic exposure control mode and having a shape directing to said first display part, and a fourth display part for indicating the diaphragm aperture priority automatic exposure control mode and having a shape directing to said second display part, and first display part, said third display part, said fourth display part and said second display part being arranged in the order thereof and in a single row. 4. A display device according to claim 3, wherein said camera is further operable in a programmed automatic exposure control mode, and said display device further comprising third display means including a fifth display part for indicating the programmed automatic exposure control mode, said fifth display part being disposed between said third display part and said fourth display part and having a shape neither directing to said first display part nor directing to said second display part.
5. A display device for use in a camera selectively operable in a plurality of exposure control modes including a manual exposure control mode, a shutter time priority automatic exposure control mode, a diaphragm aperture priority automatic exposure control mode and a programmed automatic exposure control mode, said display device comprising:first display means for indicating the shutter speed priority automatic exposure control mode, the diaphragm aperture priority automatic exposure control mode and the programmed automatic exposure control mode respectively; second display means for displaying exposure control values to be controlled; third display means for indicating the manual exposure control mode; said first display means, said second display means and said third display means being arranged in a row, and one of the exposure control values of said second display means being displayed between said first display means and said third display means. 6. A display device according to claim 5, wherein said second display means includes a first display part for displaying a shutter time value and a second display part for displaying a diaphragm aperture value, said first and second display parts being disposed at each side of said first display means respectively, and said display device further comprising fourth display means for displaying an exposure deviation value representing a difference between a proper exposure value and a manually set exposure value, said fourth display means being disposed at an opposite side of said third display means with respect to said first display means.
7. A display device for use in a camera selectively operable in a shutter time priority automatic exposure control mode and diaphragm aperture priority automatic exposure control mode, said display device comprising:selection means for selecting one of the exposure control modes; first display means for displaying a shutter time value and a diaphragm aperture value, the shutter time value and the diaphragm aperture value being displayed in different rows of said first display means; and second display means for indicating the selected exposure control mode, said second display means having a first display part disposed adjacent to the display portion of the shutter time value of said first display means and a second display part disposed adjacent to the display portion of the diaphragm aperture value of said first display means, and said first display part being turned-on only when the shutter time priority automatic exposure control mode is selected and said second display part being turned-on only when the diaphragm aperture priority automatic exposure control mode is selected. 8. A display device according to claim 7, wherein said camera is further operable in a programmed automatic exposure control mode, and said first and second display parts are both turned-off when the programmed automatic exposure control mode is selected.
9. A display device according to claim 7, wherein said camera is further operable in a manual exposure control mode, and said first and second display parts are both turned-on when the manual exposure control mode is selected.
This application is a continuation of application Ser. No. 196,298, filed May 20, 1988 now abandoned, which is a divisional of application Ser. No. 808,251, filed Dec. 12, 1985, now U.S. Pat. No. 4,847,651.
In automatic exposure control cameras, as the number of the functions or operations adopted in the camera increase, it is required to display many kinds of information in order to inform a user of the operations or functions which are instantaneously used or available in the camera.
Besides the problems mentioned above, there has been proposed to use in a camera a micro processor as a central processing unit (CPU) which is operated with a predetermined program or sequence so as to process various data taken from the external circuits such as a light measurement circuit and to send the necessary data to display device for displaying the information. In this device, the data communication between the CPU and the external circuits and the display device are made with a period defined by the program. Therefore, before the light measurement circuit provides correct light measurement data to the CPU, the CPU might transfer indefinite data to the display device. The displayed data will be nonsense or confusing.
SUMMARY OF THE INVENTION An essential object of the present invention is to provide a display device for use in a camera, with which the user can easily recognize not only the contents of the operation but the relationship between the exposure data and the operator.
a central processing unit (CPU) for controlling the camera provided with a (1) primary state in which only a power supply is applied being unavailable to perform processing and a (2) control state in which the CPU is available to perform processing and to provide preliminary displaying data containing one of data for deenergizing the display of the display means and representing stand by mode occurring when the main switch is turned on before the picture taking mode is enabled, and
a central processing unit (CPU) for controlling the camera provided with a (1) primary state in which only a power supply is applied being unavailable to perform processing and a (2) control state in which the CPU is available to perform processing and provide preliminary displaying data containing one of data for deenergizing the display of the display means and representing stand by mode occurring when the main switch is turned on before the picture taking mode is enabled, said CPU outputting the preliminary displaying data at least two times when a battery for the camera is loaded and
FIG. 8 is a detailed circuit diagram showing a part of a segment driver shown FIG. 5
FIGS. 31(a) to 38 and 40(a) to 42(b) are respectively schematic diagrams showing the various examples displayed in the internal and external display units,
FIGS. 46 (a) to (c) are schematic diagrams showing a modification of a display to indicate camera shake, and
The contents displayed by the external display unit 4 are shown in FIG. 3. On the top portion of the display by the unit 4 as viewed in FIG. 3 are characters P, R, O, G, R, A, M and S for displaying exposure control modes (referred to as AE mode hereinafter). When AE mode is set to the programmed automatic exposure control mode (referred to as P mode), the characters PROGRAM are displayed with the character S deenergized. When a diaphragm aperture priority automatic exposure control mode (referred to as A mode) is set, only the character A is displayed with the characters PROGR and MS deenergized. In case of a manual exposure control mode (referred to as M mode), only the character M is displayed. In case of a shutter time priority automatic exposure control mode (referred to as S mode), only the character S is displayed. A mark 100 of characters ISO is disposed below the characters PROGRAMS and is displayed for indicating a film speed value, i. e., ISO value being displayed. A first numerical display part 101 having four digit display elements 101-1, 101-2, 101-3 and 101-4 is disposed below the ISO mark 100 and displays the values of shutter speed, ISO data and the frame number of the film counter. A first set indication mark 102 of a triangular shape is disposed to the right of the numerical display part 101. A horizontal bar 103 is disposed below the numerical display part 101. The bar 103 is displayed when the main switch SM is turned on and is deenergized when the main switch SM is turned off. Below the bar 103 are a second numerical display part 104 having two digit display elements 104-1, 104-2 and a decimal point 104-3, a character F and a square shaped mark 105 including symbols + and -. The second numerical display part 104 displays the values of the diaphragm aperture and exposure adjustment. A second set indication marks 106 is disposed to the right of the second numerical display part 104. The symbols + and - are displayed when an exposure compensation i.e., the override is set in the camera.
FIG. 4 shows the detailed arrangement of the internal display unit 6. A blur warning display part 201 is formed by a pair of marks CA1 and CA2. A third numeric display part 202 having four digit display elements is disposed right to the camera shake display part 201 and displays the data of the shutter speed, ISO sensitivity and the frame number of the film counter. Marks 203, 204 and 205 with the characters S, P and A which respectively represent the S, P and A modes are disposed to the right of the third numerical display part 202. A fourth numerical display part 206 having two digit display elements is disposed right to the mark 205, and displays the value of the diaphragm aperture. The mark 203 has a tapered shape portion directed to the third numerical display part 202 so as to show that the shutter time is preferentially set. The mark 205 has a tapered portion directed to the fourth numerical display part 206 so as to show that the diaphragm aperture is preferentially set. Further the internal display unit 6 contains a mark 207 with a character M for displaying the M mode, a fifth numerical display part 208 having symbols + and - and two digit display elements for displaying either the data of the exposure compensation value in the automatic exposure control mode, i.e., P, A and S modes and the value of deviation set in the metered manual operation in the M mode. A mark 209 of a square shape and a dot 210 is disposed at the rightmost portion of the internal display unit 6 for displaying two kinds of light measurement. In case of an average light measurement, only the square shape mark 209 is displayed. In case of a partial or spot light measurement, both of the mark 209 and the dot 210 are displayed.
The character M with the fifth numeric display part 208 in the internal display unit 6 are provided for facilitating recognition of the metered manual mode since the metered manual mode display of the symbols .+-. are displayed.
FIGS. 35 (a) and (b) and FIGS. 36 (a) and (b) show examples of display on the external display unit 4 and internal display unit 6 when the exposure compensation mode is set. It is noted that the position of the exposure compensation value displayed in the internal display unit 6 during the exposure compensation (.+-.) mode is different from the position during the AE male so that the exposure compensation value can be displayed at the central part of the display in the internal display unit 6 in order that the operator can easily read the override value during the exposure compensation mode.
A central processing unit 10 (CPU) made of a microprocessor for controlling the camera operation is fed with a DC at a potential +E from a battery 11 loaded in the camera. The main switch SM has it one terminal grounded and another terminal connected to the CPU directly and to the battery 11 through a pull-up resistor R. The CPU 10 is coupled with a crystal oscillating element XL1 for a standard clock pulse train.
Connected to the CPU 10 are a preview switch S10 for checking the depth of field, switches S11 and S12 for shifting the program predetermined in the P mode, a switch S13 for selecting the exposure control mode and a switch S14 for setting the exposure adjustment value. The switches S10 and S14 are respectively operable by the push buttons PB 1 to PB5. A switch S15 for detecting an interchangeable lens attached to the camera is also connected to the CPU 10. The switch S15 is operated when the interchangeable lens is successfully attached to the camera.
A display circuit 20 is supplied with DC power from the battery 11 and is adapted to receive the signal from the main switch SM and the signals CS, PWC SDATA and SCK from the CPU 10. Also the display circuit 20 is coupled with a crystal oscillating element XL2 for standard clock pulses. A standard voltage generator circuit 27 in the display circuit 20 receives voltages form a voltage source 21 and generates a standard voltage for driving the liquid crystal display elements (LCD) of the external display unit 4 and internal display unit 6. The outputs of the display circuit 20 are supplied to the external display unit 4 and the internal display unit 6.
FIG. 7 shows the details of the common driver 25. The circuit 25 receives the voltages V.sub.LCDO, V.sub.LCD2, and V.sub.DD and output the voltage to the output terminals COM1 and COM2 through analog switches AS1 to AS4 and p channel field effect transistors (FET) FP1 and FP2 by the timing pulses φ9 and φ10. The timing of outputting the voltage V.sub.LCDO, V.sub.LCD2 and V.sub.DD is defined by NAND gates NA1 and NA2, NOR gate NOR1 and NOR2 and inverters IN3 and IN4.
The serial clock pulses SCK passes an OR gate OR11 and is applied to NOR gates NR3 to NR9 as the signal φs. The signal φs is also applied to a clock terminal φ of a counter decoder CD. When a set terminal s of the counter decoder CD is High, the outputs BS1 to BS7 of the counter decoder CD are all High. When the set terminal s is Low. one of the output terminals BS1 to BS7 is made Low sequentially each time eight pulses are applied to the terminal φ. When one of the terminals BS1 to BS7 is Low, one of the NOR gates NR3 to NR9 can be enabled correspondingly to pass the signal φs to the input terminal φ of the corresponding shift register SRi (i=1 to 7).
External control signals PWC and CS are logically summed in the OR gate OR3 to generate the signal P.CS, which is applied to one input terminal of the OR gate OR1 and a terminal of the counter decoder CD. The signal P.CS is applied to one input terminal of the OR gate OR2 in which the signal P.CS is logically summed with the signal BS7. The output of the OR gate OR2 is applied to the D input of a flip flop FF3 and the one input terminal of a NAND gate NA8. The flip flop FF3 receives the power on reset signal POR at its S input terminal and the Q output is applied to another input terminal of the NAND gate NA8. The clock pulses φ2 is applied to the φinput of the flip flop FF3.
In FIGS. 12, A, B, C and D are input lines and Q is an output line. The circles on the intersecting points of the input lines B and D and the output line Q denote a NAND gate having inputs B and D as shown in the right hand of FIG. 12. The logic of the matrix with the circles on the lines B and D represents B
FIG. 14 shows the details of the switch circuit SW2 in which the inputs p1 to p9 are outputted to the terminals q71 to q78, q82 to q89 by the switching signals MON, and .+-. ON.
The same operation can be made about the signal .+-. ON.
FIG. 16 shows the details of the data converter C2, showing the logic between the outputs q40 to q62 and the inputs p12 to p16.
FIG. 20 shows the relation between the outputs q1 to q39 of the data converter DC1 and the characters displayed on the external display unit 4 and the internal display unit 6. The characters can be displayed in such a manner that when the output q1 of the data converter DC1 is High, the numerical character displayed on the place of 10 display unit 4 (and 6) is 0, and with q1 low of 10 With q2 High the 10 10
The data concerning the shutter speed SS can be supplied to the input terminals p22 to p37. ISO data can be supplied to the input terminals p32 to p37. CTR value can be supplied to the input terminals p40 to p47 and the signal CTR.
As shown, the outputs from the terminals q40 to q62, q71 to q78 and q82 to q89 change in accordance with the states of the signals on the input terminals p12 to p16 of the data converter DC2, the signals on the input terminals t1 to p9 of the switch circuit SW2, and the signals MON and .+-. ON.
The diaphragm aperture values are obtained by the signals on the input terminals p12 to p16. Exposure compensation values and the exposure deviation values are obtained by the signals on the input terminals p1 to p9.
FIG. 24 shows the details of a part of the data converter DC4, showing the logic processing for obtaining the switching signals MON, .+-. ON, FON, CTR, ISO and SS used in the switch circuits SW1 and SW2, ON and OFF signal for the output control circuit CTL1 and OFFVCLD signal for the voltage generator circuit 27. The input signals to the data converter DC4 are j10, j11, j55, j56, j60 to j67, j70, j71 and the external signals SM and PWC.
FIG. 27 shows the details of the voltage generator circuit 27. A reference voltage VLCD is obtained by dividing the voltage +E by the circuit formed by diodes D1 and a resistor R1 provided exterior of the generator 27. The reference voltage VLCDS is fed to a booster 27a comprising capacitors C1 and C2, so as to generate a multiplied voltage (+E-VLCD1) of a voltage (+E-VLCD). The voltages VLCDS and VLCD1 are introduced output terminals VLCD0 and VLCD2 through an output control circuit formed by analog switches AS21, and FETs Q21 and Q22.
The terminals VLCD0 and VLCD2 respectively change their state in such a manner that when the signal OFFVLCD is Low, the terminal VLCD0 is VLCDS and VLCD2=VLCD1, and when the signal OFFVLCD is High, both terminals VLCD0 and VLCD 2 assume voltage VDD.
The contents of the registers SR1 to SR7 can be updated form the old data D(old) to the new data D(new) by the negative edges of every pulse SCK while the signals PWC* and CS* are Low.
At the positive edge of 49th pulse of SCK just after the update of the register SR6 is completed, in addition to the start of update of the register SR7, the Q output of the flip flop FF3 is changed to Low state which is kept until the signal BS7 becomes High in order to read in the D input by the positive edge of the clock pulse φ2.
The pulse LTCH* is generated by the Q output of the flip flop FF3 and P.CS signal, then the contents of the registers SR1 to SR7 are transferred to the latches LT1 to LT7.
After the voltage is stabilized, the voltage VLCD0 and VLCD2 for driving the LCD elements of the display units 4 and 6 can be fed upon application of the signal OFFVLCD of Low.
FIGS. 36(a) and 36(b) show the display after the exposure compensation is set. The mark+is only displayed in the external display unit 4. The value +1.5 is displayed in the internal display unit 6 but is flashed or blinked.
Upon application of the DC power from the battery 11, the flip flop FF1 (FIG. 6) of the frequency divider 26, the flip flop FF2 (FIG. 8) of the clock generator of the segment driver 214, the flip flop FF3 and the latch LT1 of the data latch 23, the starting FET 27b (FIG. 27) of the voltage generator 27 are respectively initialized by the power on reset pulse POR generated by the power on reset circuit 40. By the initialization, the terminals j10 and j11 of the latch LT1 are made Low and High and Q outputs of the flip flops FF1 and FF2 are made Low and High and Q outputs thereof are made High and Low.
In the voltage generator 27, FFET 27b is turned on in a short period, so that the capacitor C2 is charged and the terminal VLCD1 is grounded.
In the state mentioned above, the crystal oscillator XL2 of the oscillator circuit 41 has not yet started to oscillate, therefore, the display circuit 20 awaits the start of the oscillation of the crystal oscillator XL2 and the generation of the pulse φ0 without any circuit operation of the display circuit 20 keeping the initialized states of various parts of the circuit 20.
On the other hand, any one of the voltage VDD, VLCD2 r VLCD0 is applied to both of the external and internal display units 4 and 6 through the terminals COM and SEG. The voltage at the terminal COM1 is the voltage VLCD2. COM2 is VLCD0, SEGn is VDD or VLCD2 depending on the state of the signals S2n and S2n-1.) In this case, the voltage OFFVLCD applied to the voltage generator 27 is set to High by the Low signal of the terminal j10 and the High signal of the terminal j11 which are fed through the AND gate A50, inverter I50 and OR gate O50, then VLCDS2+VDD can be obtained. Namely, the voltages applied to the respective electrodes of the LCD elements of the external and internal display units 4 and 6 are equal, so that application of a harmful DC voltage to the electrodes of the LCD elements is prevented.
The clock pulses φ9 and φ10 are applied to the segment driver 24 and common driver 25 in which both pulses are shaped suitable for driving the LCD display elements.
The clock pulses φ4 are applied to the output control circuit CTL1 of the decoder 23 and are used for causing the display units to be turned on and off repeatedly.
When the signal PWC and CS are Low, the data latch 22 can be operated. The signal PWC is used as a timing signal for supplying the power source to the light measurement circuit of the camera. The light measurement circuit states its operation with Low of PWC signal. The signal CS is used for determining the forwarding address of the serial data. The forwarding address of the serial data is determined when the CS is Low.
The NOR gate NR3 is opened when the signal BS1 is Low at the time of the positive edge of the first SCK pulse. The input signal φ0 to the shift register SR1 is raised at the time of falling of the first SCK pulse, then the shift register SR1 takes one bit of the content of SDATA. The data is output from the terminal j10. When the second SCK pulse is applied, the shift register SR1 takes the second bit of SDATA. A similar operation as mentioned above is repeated for every bits of SDATA. At the negative edge of the 8th pulse of SDATA, eight bits of SDATA are taken in the shift register SR1 and the signal of 8th bit is output from the terminal j17. The signal BS1 is kept low while the above operation is performed.
When the 9th SCK pulse occurs, the signal BS1 becomes High and BS2 becomes Low, the NOR gate NR3 is closed and the NOR gate NR4 is opened. At the negative edge of the 9th SCK pulse, the φinput of the shift register SR2 raises taking one bit of SDATA. The data taken in the register SR2 at this time is output from the terminal j20. An operation similar to that mentioned above is repeated. When the 49th SCK pulse is raised, the signal BS6 becomes High with BS7 being Low, then the NOR gate NR8 is closed and NR9 is opened. Further the output of the OR gate OR2 becomes Low. The shift register SR7 takes up to 56th SCK pulses. While the first to 56th SCK pulses are taken in the shift register SR1 to SR7, the signal LTCH is kept High, thus the latches LT1 to LT7 do not take the contents of the shift registers SR1 to SR7 in this period. In detail, although the output of the OR gate OR2 is made low by the 49th SCK pulse, the flip flop FF3 takes Low signal at D input by the positive edge of the clock pulse φ2, causing Q output to be High. However another input of the NAND gate NA8 is made Low earlier than the Q output of the flip flop FF3 become Low, thus the signal LTCH is kept High. When the 57th SCK pulse occurs or any one of PWC or CS* become High, the output of the OR gate OR2 becomes High. Since the Q output of the flip flop FF3 which is another input of the NAND gate NA8 is High, the output of the NAND gate NA8 or the signal LTCH becomes Low. The negative edge of the signal LTCH causes the latches LT1 to LT7 to be triggered to take the outputs of the shift registers SR1 to SR7 in the latches LT1 to LT7. Subsequently, the flip flop FF3 takes the High signal of D input by the positive edge of the clock pulse φ2 and Q output of the flip flop FF3 is made Low. The counter decoder CD is set in the initial state by any one of High signal of PWC or CS.
In the operation mentioned above, it is one advantage that even if a number of bytes of the clock pulses of the received serial data are missing, the last latch pulse LTCH* is not outputted, whereby no failure of data occurs. It is a further advantage that even if the number of bytes of the clock pulses is too great, the data is cut off at the 57th SCK pulse automatically so that no accident occurs. It is a still further advantage that since the CPU 10 processes the data so that the clock pulses are not interrupted in every byte, any data transfer accident can be prevented.
In case there is any accident of the internal clock pulses φ2 under the normal condition of the external signals PWC, CS, SCK and SDATA, the signal LTCH can not be outputted, whereby the data stored in the shift registers SR1 to SR7 can not be transferred to latches LT1 to LT7. When such accident occurs, the wave form of the LCD driving signal becomes a straight line. In this case, terminal j10 is kept Low and j11 is kept High, thereby causing the signal OFFVLCD to be High to inhibit application of the driving voltage to the LCD elements. For this purpose, the external data is inhibited from being taken in the display circuit 20 when the clock pulse φ2 is not operated.
The detailed operation of the common driver 25 and the segment driver 24 is explained hereinafter.
Referring to FIGS. 7, 8 and 30, the analog switches AS1 to AS4, and the FETs of p channel FP1 and FP2, are turned on and off by the output signals generated by a gate circuit formed by the NAND gates NA1 and NA2, NOR gates NR1 and NR2 and inverters IN3 and IN4 controlled by the clock pulses φ9 and φ10 so as to produce the signals COM1 and COM2 of the common driver 25. The signals COM1 and COM2 are changed as shown in FIG. 30 synchronized with the clock pulses φ9 and φ10. The period of the outputs COM1 and COM2 is the same period of the clock pulse φ10 and the phase of the signals COM1 and COM2 is shifted by 1/4 period. The signals COM1 and COM2 have three levels VDD, VLCD0 and VLCD2.
Referring to FIG. 8, four kinds of clock pulses are produced by processing the clock pulses φ9 and φ10 by a clock generator composed of the inverter IN5 and the flip flop FF2. The four kinds of clock pulses are selected by the NAND gates NA3 to NA7 on the basis of the signal S2n and S2n-.sub.1 to produce the segment signal SEGn. The segment signal SEGn has two levels VDD and VLCD2 with the period equal to the period of the clock pulse φ10. The phase of the signal SEGn can be changed by 1/4 period as shown in FIG. 30 depending on the logic levels of Low or High of the signals S2n and S2n-.sub.1. The respective states of the signal SEGn corresponding to the level of the signals S2n and S2n-.sub.1 are expressed SEGn (L,L), SEGn (L,H), SEGn (H,L) and SEGn (H,H). The LCD elements of the display units 4 and 6 can be turned on in the displaying condition when the voltage difference between signals COM1 or COM2 and the signal SEGn is 2 segment signals SEGn (LH) or SEGn (HH) are applied can be turned on. For the signal COM2, the segment of LCD to which the segment signals SEGn (H,L) or SEGn (H,H) are applied can be turned on. When the segment signal SEGn (L,L) is applied, the segment is not turned on for both of the signals COM1 and COM2. The signal S2n-.sub.1 is used as the control signal of the segment of LCD receiving the signal COM1. The segment of LCD receiving the signal COM1 can be turned on when the signal S2n-.sub.1 is High and turned off when the signal S2n-.sub.1 is Low. The signal S2n is used as the control signal of the segment of LCD receiving the signal COM2. The segment receiving the signal COM2 is turned on when the signal S2n is High and turned off when the signal S2n is Low.
EXPLANATION OF THE SIGNALS j10 TO j77 Referring to FIG. 9, the signals j10 and J11 are the control signals to control the supply of the LCD drive voltage. When the signal j10 is Low and j11 is High, the supply of the LCD drive voltage is cut off.
The signal j20 is the signal relating to the warning of the exhaustion of the battery 11. When the signal j20 is High, all displays on the display units 4 and 6 are turned on and off with the frequency defined by the frequency of the clock pulse φ14.
The signals j22 to j27 are the signals representing the shutter time value. The combination of the signals j22 to j27 provides thirty-six shutter time values. When the signals j22 to j27 are all High, no shutter time is displayed.
The signals j32 to j37 are the signals representing the ISC sensitivity values of the photographic film. The combination of the signals j32 to j37 provides thirty-one ISO sensitivity values. When the signals j32 to j37 are all High, no ISO sensitivity value is displayed.
The signals j54 to j56 are the signals representing the sign attached to the exposure compensation value and the exposure deviation value. The signal j54 represents+and
The signals j55 and j56 are used for switching the override value and the metered manual difference value for both of the external display unit 4 and the internal display unit 6.
The signal j60 is the signal for preferentially displaying ISO value. In case the main switch SM is turned off and the signal OFFVLCD is High, the LCD driving voltage is cut off. However even under such state, when the signal j60 is made High, the signal OFFVLCD can be turned to Low so as to supply the LCD driving voltage to the segment driver 24 and the common driver 25 (see FIG. 24). The signal j60 is not used alone but is used with the ISO display mode signal and the ISO data from the CPU 10. This state corresponds to the state just after the battery is mounted in the camera.
The signal j62 is the shift signal SHIFT used to turn on and off the mark 204 during the program shift is set. The program shift means that combination of the diaphragm aperture value and the shutter time are manually shifted by equal degree but complementarily keeping the suitable exposure value from the aperture diaphragm value and the shutter time set in the P mode. Specifically, assuming that the shutter time 1/250 sec. and the aperture value 5.6 are selected according to a predetermined program line in the P mode. A program shift might slow down the shutter time to 1/125 sec. while increasing the diaphragm aperture value to 8. When the signal j62 is High, the mark 204 is turned on and off repeatedly.
The signals j70 and j71 are the camera operation mode signals CALL MODE (see FIG. 39) representing any one of the AE mode, the stand-by mode, ISO setting mode and .+-./- mode. The contents of the display can be selectively changed depending on the states of the CALL MODE signals. Normally j70 set, j70 j70 mode is set, j70
The signals j76 and j77 are the signals for switching the light measurement mode of the average light measurement mode and the spot light measurement mode. When the spot light measurement mode is set, any one of the signals j76 and 77 are made Low, whereby the mark 210 of the internal display unit 6 is turned on. The mark 209 is constantly turned on during the AE mode.
The switch data decoder shown in FIG. 24 is arranged mainly to provide the signals for use in the switching circuits SW1 and SW2 in which FOM, CTR ISO and SS signals are used to control the switch circuit SW1 and MON, .+-. ON signals are used to control the switch circuit SW2. ON and OFF signals respectively control the output control circuit CTL1 so as to turn on and off all of the LCD segments of the display units 4 and 6. When the signal OFFVLCD is High, the power source to the display units 4 and 6 and the driver circuit are cut off in order to prevent application of DC voltage to the LCD segments of the display unit 4 and 6 while the crystal oscillator XL2 is stopped and in order to save the power while the main switch SM is turned off.
When the signal PWC is Low with the signal j65 High, namely when the bulb count mode is set, the CTR signal is High and the signals j40 to j47 are representing the timer count information are selected and decoded and displayed. In this case, SS and ISO signals are Low the shutter time and ISO value are deleted by the switch circuit SW1. Further in this case, .+-. ON signal is Low, MON signal is High so far as the signal PWC is Low and the signals j50 or j56 are Low, therefore, the exposure compensation value is deleted and the exposure deviation value is displayed.
When the ISO setting mode is set, the signals SS, CTR, FON, MON and .+-. ON are Low but only the signal ISO is High, so that the switch circuit SW1 is enabled and the signals j32 to 37 representing the ISO value are selected, decoded and displayed. The other numeric display parts except for 101 and 202 are turned off.
During the standby mode, the signals SS,CTR,FON,ISO, MON and .+-. ON are respectively Low so that all of the numeric display parts are turned off.
During .+-. mode, the signals SS, ISO, CTR FON and MON are Low and the signal .+-. ON is High is PWC Low, so that the signals j50 to j53 representing the exposure compensation value are selected, decoded and displayed.
The signal B7 is used to turn on and off the numeric display part 208 of the internal display unit 6 and is mainly controlled by the signals j55, j56 and j61.
The signal B4 is used to turn on and off the numeric display parts 101 of the external display unit 4 and 202 of the internal display unit 6 and is mainly controlled by the signals j63 and j74.
The signal B1 is used to turn on and off all parts of the display units 4 and 6 except for the display parts controlled by the signals B8 to B2 and the mark 201. The signals B8 to B1 are also controlled by the signal j20.
In the switch circuit SW1 shown in FIG. 11, the signals j12 to j16 representing the diaphragm aperture value, j22 to j27 representing the shutter time value, j32 to j37 representing the ISO value and j40 to j47 representing the timer count value are applied thereto. Each of the NAND gates can be opened when the corresponding signal of one of FON, CTR, ISO and SS is High and passes the input jn to the output pn. When the signals FON, CTR etc. are Low, the corresponding NAND gate is closed to make its output High.
The signals q40 to q62 representing the diaphragm aperture values of twenty-three kinds as shown in SD5 of FIG. 23. The signals q40 to q62 are applied to the segment decoder SD5 for decoding them onto the signals r30 to r43. In the above example, when q40 is Low, the decoded output corresponds to "- -".
In the decoder DC3, the input j50 represents the value smaller than the decimal point. The outputs p1 and p2 can be obtained by the input j50. The inputs j51 to j53 represent the data 0 to 6 and the corresponding outputs are p3 to p9 of High level. The outputs p3 to p9 are fed to the switch circuit SW2 and controlled by MON and .+-.ON signals. When the signal MON is High, .+-.ON signal is Low and the signals p2 to p9 are reversed to produce at outputs q82 to q89 with the outputs q71 to q78 being High. When the signal .+-.ON is High, the signal MON is Low and the signals p1 to p7 are reversed to produce at outputs q71 to q77 with the outputs q82 to q89 being High. When the signals MON and .+-.ON are Low, the outputs q71 to q78, q82 to q89 are all High. The outputs q71 to q78 of the switch circuit SW2 are applied to the segment decoder SD5 and the outputs q82 to q89 to SD6.
The details of the output control circuit CTL1 is shown in FIGS. 18 and 19 and its logical truth table is shown in the table 1. In FIG. 19, when a High signal is inputted to the terminal r69, the gates corresponding to S69 and S70 are opened to output the reversed signals at S69 and S70 corresponding to the clock pulse φ14, so that the marks CA1 and CA2 are turned on and off repeatedly to give the operator the image of a vibrating camera.
The relation between the output of the output control circuit CTL1 and the terminal SEGn is shown in the table 2. The name of the segments are the same shown in FIG. 4.
When the battery 11 is mounted in the camera, the power source voltage +E is applied to the CPU 10 and the display circuit 20. The crystal oscillator XL1 with higher frequency than that of the crystal oscillator XL2 may start its oscillation earlier than the oscillation of the crystal oscillator XL2. Once the crystal oscillator XL1 has started its oscillation, the CPU 10 operates according to the instructions provided by the ROM. Since CPU 10 has little to do at the time of mounting the battery, the CPU 10 stops its operation after some 0.1 miliseconds after the battery mounting, waiting for the next task. In general, rising of the oscillation of the crystal oscillator XL2 for the display circuit 20 has not been completed within 100 miliseconds to one second. In this period, the CPU 10 does not accept the communication of the serial data and the clock pulses φ2 is not generated, thus the signal LTCH does not generated. On the other hand, so long as the serial data is not generated even if the oscillation of the crystal oscillator XL2 is already established, the data in the display circuit 20 is not updated because the signal LTCH is not generated as the signal PWC, CS, SDATA and SCK are not generated. In the arrangement mentioned above, the display units 4 and 6 may keep the unstable information obtained at the time of mounting of the battery. The drawback mentioned above can be avoided in the present invention by turning off the power to the display units 4 and 6 by the signals j10, j11 and POR generated from the power on reset circuit, thereby eliminating unreliable information from the display at the initial state. In case the power on reset circuit fails or it is not preferred that the display units remain suppressed, it is possible to display the necessary information in the display units 4 and 6 as soon as the reliable serial data is obtained by performing the communication of the serial data by the CPU 10 even in the period before the oscillation of the crystal oscillator XL2 is stabilized after the mounting of the battery so that when the oscillation of the crystal oscillator XL2 is stabilized, reliable data is displayed on the display units 4 and 6. In this case, the data to be displayed before the reliable data is obtained may be a data used for turning off the display unit, standby data or the like. In this case the CPU 10 operates to communicate the display data such as standby data mentioned above before the oscillation of the crystal oscillator XL2 is stabilized after mounting of the battery, then the CPU 10 is stopped if there is no work. In this case interruption to the CPU 10 should be disabled before the crystal oscillator XL2 is stabilized.
Just before the CPU 10 is stopped, the CPU 10 transfers the display data of the standby mode to the display units 4 and 6. Thereafter, if the display data does not change, the contents displayed on the display units 4 and 6 do not change to continue the standby mode. When the main switch SM is turned off but just before the CPU 10 is stopped, the CPU 10 transfer the data to eliminate the display on the display units 4 and 6. Unless the main switch SM is turned on, the display is kept eliminated since no data is transferred to the display units 4 and 6.
The signals j66 and j67 are provided for the test of the connection of the display units 4 and 6. When the signal j67 is High, the signals having the wave form to turn on all LCD segments of the display units 4 and 6 can be outputted from the terminals SEGn and COM. When the signal j66 is Low, the signals having the wave form to turn off all LCD segments of the display units 4 and 6 can be outputted from the terminals SEGn and COM. The signals j66 and j67 have the second priority. When such turn on signals mentioned above are applied to every LCD segments, each LCD segment having right connection is turned on but LCD segment having a wrong connection can not be turned on. When the turn off signals mentioned above have applied to every LCD segments, each LCD segment having the right connection is turned off but LCD segment having wrong connection can not be turned off. Thus any wrong connection to the LCD segments can be easily found.
The signal q43 to q62 are used to display the diaphragm aperture value expressed every round off 0.5 Ev value.
On the other hand, there are such values 3.5 and 4.5 conventionally used as the full open diaphragm aperture value. Since the full open diaphragm aperture values conventionally used as mentioned above are not suitable to use with the aperture values scaled by unit of 0.5 Ev, there are provided the signals q41 and q42 to display the values 3.5 and 4.5. In this way, when the diaphragm aperture value which is manually set or is the result of the calculation by the CPU 10 is the full open diaphragm aperture values such as 3.4 or 4.8 which corresponds to the conventionally used value 3.5 or 4.5, the CPU 10 modifies the values 3.4 or 4.8 into 3.5 or 4.5 and the data 3.5 or 4.5 are outputted to the display units 4 and 6. When the diaphragm aperture value which is manually set or is the result of the calculation by the CPU is not the full open diaphragm aperture value, the CPU 10 generates the value 3.4 or 4.8 for the display.
As shown in FIG. 43, the CPU 10 reads the full open diaphragm aperture value Avo from the interchangeable lens 3 in the step SS1, storing the value Avo in the register in the CPU 10. The CPU 10 calculates a diaphragm aperture value Av (referred to as a calculated F value) on the basis of the result of light measurement and other necessary values set in the camera in the step SS2. Subsequently the CPU 10 judges whether or not Avo=Av in the step SS#. With Avo=Av, the full open diaphragm aperture value Avo is adopted in the step SS4. On the other hand, when the calculated F value Av is not equal to Avo, the calculated F value Av is adopted in the step SS5 and quantized by every 0.5 Ev value. For example if the calculated F value is 3.3, the value 3.3 is quantized into 3.4. If the value is 4.6, the value 4.6 Ev is quantized into 4.8. Then the data AvDSP of the signals j12 to j16 for displaying the diaphragm aperture value adopted in the steps SS4 or SS5 is transferred to the display circuit 20 in the step SS6.
COMBINED USE OF THE DISPLAY DEVICE FOR THE EXPOSURE COMPENSATION VALUE AND THE EXPOSURE DEVIATION VALUE The value +6.5 shown in FIG. 34 (b) displayed in the display part 208 in the internal display unit 6 is the exposure deviation value. The exposure deviation value is displayed in case of the M mode. The available range of the exposure deviation value which can be displayed is +6.5 Ev to -6.5 Ev as shown in the right column in FIG. 23. If the exposure deviation value is out of the range, any one of the values +6.5 or -6.5 is turned on and off repeatedly. The display part 208 is turned on and off when the signal j61 named M'dOVER is High.
The external display unit 4 is adapted to be turned on at the display part 104 to display the mark .+-. in the case of the exposure compensation. The display part 104 is not displayed in case of the exposure deviation mode.
DISPLAY OF THE S MODE AND A MODE. In FIG. 32 (b), in the A mode, the display part 205 in the internal display unit 6 is turned on. The tapered side of the mark of the display part 205 is directed toward the diaphragm aperture value of the manual set. In the S mode as shown in FIG. 33(b), the display part 203 is turned on. The tapered side of the mark of the display part 203 is directed toward the shutter time value of manual set. By the display mentioned above, the operator can easily recognize the meaning of the AE mode and the displayed numeric value.
FIGS. 41 (a) and (b) show the contents of the display during the initial loading just after the mounting of the photographic film in the camera. While the photographic film is preliminary forwarded during the initial loading, the camera is controlled under the shutter time value 1/4000 with the maximum diaphragm aperture value (F22 in the present example). In such a state, the exposure mode display parts 203 to 205 are all eliminated by making the signal j75 High.
FIGS. 42 (a) and (b) show the display when the exchangeable lens is not attached to the camera. When the CPU 10 detects that the photographic lens is not attached to the camera, the signals j12 to j16 are all made Low in the step SS18 shown in FIG. 44. The data converter DC2 provides the q40 signal by the signals j12 and j16 to make the signals r62 of the data converter DC4 Low. Accordingly the display of the diaphragm aperture value on the display part 104 as - - with the display part 106 turned off.
SUMMARY OF THE CONTROL OF THE CPU 10 When the battery 11 is mounted in the camera, the CPU 10 starts at the step SS0 and the display circuit 20 receives the power supply. Then all parts including the CPU 10 are initialized in the step SS10. Subsequently, in the step SS11, the display data, turning off data, standby data and ISO data etc. are transferred to the display circuit 20 more than one time. Said number of times of transferring the data can be determined corresponding to the length of time until the display circuit 20 can operate in a stable manner. When the necessary data is transferred, an interruption from any operation switches enabled the CPU 10 in the step SS12. In case where the there is no specific operation to the camera, the CPU 10 stops stopping the internal clock in the step SS13. The light measurement switch S1 and the initial loading switch SB are related with respect to the main switch SM as shown in FIG. 47. When the main switch SM is turned off, the light measurement switch S1 and the initial loading switch SB are pulled down to GND by the inverters IN21 to IN25. Namely the S1 and SB signals are disabled. In this case only the main switch SM can provide the interruption signal INTset. When the INT set signal is generated from the main switch SM by turning on the main switch SM, an interruption flip flop (not shown) is set to enable the interruption in the step SS14. The flip flop can be set by the positive edge of the INT set signal and once the interruption is enabled, the flip flop is reset to wait subsequent interruption.
When the interruption is enabled, it is detected whether the switch SB is turned on or off in the step SS15. If the switch SB is turned off, the light measurement circuit (not shown) starts the light measurement in the step SS16. Then the exposure calculation is performed in the step SS17, the necessary display data for the display unit 4 and 6 are transferred in the step SS18. If it is detected in the step SS19 that the main switch SM is turned off, the CPU 10 transfers the data to turn off the display units 4 and 6, and then stop the light measurement in the steps SS20 and SS21. Subsequently the program flow goes to the steps SS12 and SS13. In case it is detected in the step SS19 that the main switch SM is turned on, the switch S1 is checked in the step SS26. With off of the switch S1, the stand by data is transferred to the display circuit 20 and the program flow goes to the steps SS16, SS21, SS12 and SS13. If the switch S1 is turned on, the release switch S2 is checked. If the switch S2 is turned on, the exposure control is performed in the step SS23 then the program flow goes to the step SS17. On the other hand, if the switch S2 is turned off, the program flow goes to the step SS17 directly to perform exposure calculation.
In case it is detected in the step SS15 that the initial loading switch SB is turned on, the shutter time value, diaphragm aperture value for the initial loading, the MODE OFF signal j75 of High level are outputted i the step SS24. Then the initial loading is made in the step SS25 to execute the shutter control with the initial shutter time value and diaphragm aperture value. Thereafter, the initial loading switch SB is checked in the step SS15 and the program flow goes to the step SS16 to perform the light measurement depending on the state of the initial loading switch SB.
FIG. 46 shows the operation of detection of the critical condition where the camera shake photographing occurs. In the step SS31, the CPU 10 reads the necessary data such as focus length and so on from the lens. Then in the step SS32, shutter time value Tv is calculated by the exposure calculation, then the shutter time value Tv.sub.L at the critical warning point at which the camera shake occurs is calculated. Then the value Tv is compared with the value Tv.sub.L in the step SS33. In case Tv&lt;Tv.sub.L, the program flow goes to the step SS34. In case Tv≧Tv.sub.L, the program flow goes to the step SS35. In the step SS34, the LOWSS signal is made High to turn on and off repeatedly the marks CA1 and CA2 of the display part 201 to warn the camera shake. In the step SS35 the signal LOWSS is made Low to eliminate the marks CA1 and CA2.
TABLE 1______________________________________ ##STR1##ON        OFF       Bm       &#966;.sub.14                                S2n______________________________________L         --        --       --      HH         H         --       --      LH         L         L        --      r2nH         L         H        L       r2nH         L         H        H       L______________________________________ Combination of r2n and Bm B1 ; r51 to r53, r61 to r65 B2 ; r54 B3 ; r55 to r58, r67 r68 B4 ; r1 to r29 B5 ; r30 to r43 B6 ; r59, r60 B7 ; r44 to r50 B8 ; r66
TABLE 2______________________________________Seg-                         external                                internalment For COM1   For COM2     display display______________________________________ 1   1-a     S1     1-b     S2   Y       Y 2   1-c     S3     1-d     S4   Y       Y 3   1-e     S5     1-f     S6   Y       Y 4   1-g     S7     2-a     S8   Y       Y 5   2-b     S9     2-c     S10  Y       Y 6   2-d     S11    2-e     S12  Y       Y 7   2-f     S13    2-g     S14  Y       Y 8   2-h     S15    3-a     S16  Y       Y 9   3-b     S17    3-c     S18  Y       Y10   3-d     S19    3-e     S20  Y       Y11   3-f     S21    3-g     S22  Y       Y12   4-a     S23    4-b     S24  Y       Y13   4-c     S25    4-d     S26  Y       Y14   4-e     S27    4-f     S28  Y       Y15   4-g     S29    5-a     S30  Y       Y16   5-b     S31    5-c     S32  Y       Y17   5-d     S33    5-e     S34  Y       Y18   5-f     S35    5-g     S36  Y       Y19   col. 1  S37    6-a, 6-d                       S38  Y       Y20   6-b     S39    6-c     S40  Y       Y21   6-e     S41    6-f     S42  Y       Y22   6-g     S43    7-a, 7-d                       S44  Y       Y23   7-b     S45    7-c     S46  X       Y24   7-e     S47    7-f     S48  X       Y25   7-g     S49    col. 2,3                       S50  X       Y26   MT+     S51    MT-,    S52  X       Y27   bar     S53    ISO     S54  Y       X28   S       S55    P.PROGR S56  Y       Y29   A2      S57    M2      S58  X       Y30   AS2     S59    AS1     S60  X       Y31   TA1     S61    TA2     S62  Y       X32   OR+     S63    OR-     S64  Y       X33   ORS     S65    F       S66  Y       X34   A1      S67    M1      S68  Y       X35   CA1     S69    CA2     S70  X       Y______________________________________ Y: available to display, X: unavailble to display.
TABLE 3__________________________________________________________________________           display pattern           external display                      internal displaymodeoperate  ##STR2##            ##STR3##                       ##STR4##__________________________________________________________________________AE mode L L L L --           F (F value)                      (F value)     FIGS. 31 (a), (b)  L    L      H        L          L            ##STR5##   (F value) + (+/- value) *                                     FIGS. 36 (a), (b)  L    L      H        L          H            ##STR6##   (F value) - (+/- value) * L L --       H L F (F value)                      (F value) + (M value)                                    FIGS. 34 (a), (b) L L --       H H F (F value)                      (F value) - (M value) +/- mode  H    H      L        L          --            ##STR7##   (+/- value) .+-.                                     +/-value = 0  H    H      H        L          L            ##STR8##   (+/- value) +                                     FIGS. 35 (a), (b)  H    H      H        L          H            ##STR9##   (+/- value) -__________________________________________________________________________ *blinking
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