Source: https://patents.google.com/patent/US20100058146A1/en
Timestamp: 2019-05-19 16:41:37
Document Index: 164978970

Matched Legal Cases: ['Application No. 60', 'Application No. 61', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61']

US20100058146A1 - Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications - Google Patents
US20100058146A1
US20100058146A1 US12/595,640 US59564008A US2010058146A1 US 20100058146 A1 US20100058146 A1 US 20100058146A1 US 59564008 A US59564008 A US 59564008A US 2010058146 A1 US2010058146 A1 US 2010058146A1
US12/595,640
US8276051B2 (en
2008-09-17 Priority to PCT/IL2008/001235 priority patent/WO2009074979A2/en
2008-09-17 Priority to US12/595,640 priority patent/US8276051B2/en
2010-03-04 Publication of US20100058146A1 publication Critical patent/US20100058146A1/en
2010-12-17 Assigned to DENSBITS TECHNOLOGIES LTD. reassignment DENSBITS TECHNOLOGIES LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANTER, OFIR AVRAHAM, STERIN, ELI, WEINGARTEN, HANAN
2012-09-25 Publication of US8276051B2 publication Critical patent/US8276051B2/en
Priority is claimed from the following co-pending applications: U.S. Provisional Application No. 60/996,948, filed Dec. 12, 2007 and entitled “Low Power BCH/RS Decoding: a Low Power Chien-Search Implementation”, U.S. Provisional Application No. 61/071,487, filed May 1, 2008 and entitled “Chien-Search System Employing a Clock-Gating Scheme to Save Power for Error Correction Decoder and other Applications” and U.S. Provisional Application No. 61/071,468, filed Apr. 30, 2008 and entitled “A Low Power Chien-Search Based BCH/RS Recoding System for Flash Memory, Mobile Communications Devices and Other Applications”.
Other co-pending applications include: U.S. Provisional Application No. 60/960,207, filed Sep. 20, 2007 and entitled “Systems and Methods for Coupling Detection in Flash Memory”, U.S. Provisional Application No. 61/071,467, filed Apr. 30, 2008 and entitled “Improved Systems and Methods for Determining Logical Values of Coupled Flash Memory Cells”, U.S. Provisional Application No. 60/960,943, filed Oct. 22, 2007 and entitled “Systems and methods to reduce errors in Solid State Disks and Large Flash Devices” and U.S. Provisional Application No. 61/071,469, filed Apr. 30, 2008 and entitled “Systems and Methods for Averaging Error Rates in Non-Volatile Devices and Storage Systems”, U.S. Provisional Application No. 60/996,027, filed Oct. 25, 2007 and entitled “Systems and Methods for Coping with Variable Bit Error Rates in Flash Devices”, U.S. Provisional Application No. 61/071,466, filed Apr. 30, 2008 and entitled “Systems and Methods for Multiple Coding Rates in Flash Devices”, U.S. Provisional Application No. 61/006,120, filed Dec. 19, 2007 and entitled “Systems and Methods for Coping with Multi Stage Decoding in Flash Devices”, U.S. Provisional Application No. 61/071,464, filed Apr. 30, 2008 and entitled “A Decoder Operative to Effect A Plurality of Decoding Stages Upon Flash Memory Data and Methods Useful in Conjunction Therewith”, U.S. Provisional Application No. 61/006,385, filed Jan. 10, 2008 and entitled “A System for Error Correction Encoder and Decoder Using the Lee Metric and Adapted to Work on Multi-Level Physical Media”, U.S. Provisional Application No. 61/064,995, filed Apr. 8, 2008 and entitled “Systems and Methods for Error Correction and Decoding on Multi-Level Physical Media”, U.S. Provisional Application No. 60/996,782, filed Dec. 5, 2007 and entitled “Systems and Methods for Using a Training Sequence in Flash Memory”, U.S. Provisional Application No. 61/064,853, filed Mar. 31, 2008 and entitled “Flash Memory Device with Physical Cell Value Deterioration Accommodation and Methods Useful in Conjunction Therewith”, U.S. Provisional Application No. 61/129,608, filed Jul. 8, 2008 and entitled “A Method for Acquiring and Tracking Detection Thresholds in Flash Devices”, U.S. Provisional Application No. 61/006,806, filed Jan. 31, 2008 and entitled “Systems and Methods for using a Erasure Coding in Flash memory”, U.S. Provisional Application No. 61/071,486, filed May 1, 2008 and entitled “Systems and Methods for Handling Immediate Data Errors in Flash Memory”, U.S. Provisional Application No. 61/006,078, filed Dec. 18, 2007 and entitled “Systems and Methods for Multi Rate Coding in Multi Level Flash Devices”, U.S. Provisional Application No. 61/064,923, filed Apr. 30, 2008 and entitled “Apparatus For Coding At A Plurality Of Rates In Multi-Level Flash Memory Systems, And Methods Useful In Conjunction Therewith”, U.S. Provisional Application No. 61/006,805, filed Jan. 31, 2008 and entitled “A Method for Extending the Life of Flash Devices”, U.S. Provisional Application No. 61/071,465, filed Apr. 30, 2008 and entitled “Systems and Methods for Temporarily Retiring Memory Portions”, U.S. Provisional Application No. 61/064,760, filed Mar. 25, 2008 and entitled “Hardware efficient implementation of rounding in fixed-point arithmetic”, U.S. Provisional Application No. 61/071,404, filed Apr. 28, 2008 and entitled “Apparatus and Methods for Hardware-Efficient Unbiased Rounding”, U.S. Provisional Application No. 61/136,234, filed Aug. 20, 2008 and entitled “A Method Of Reprogramming A Non-Volatile Memory Device Without Performing An Erase Operation”, U.S. Provisional Application No. 61/129,414, filed Jun. 25, 2008 and entitled “Improved Programming Speed in Flash Devices Using Adaptive Programming”, and several other co-pending patent applications being filed concurrently (same day).
The present invention relates generally to Chien searches and more particularly to Chien search algorithms in error correction decoders.
[3] “Error Correction Coding Mathematical Methods and Algorithms”, Todd K. Moon, John Wiley & Sons, Inc., 2005.
[4] “Introduction to Coding Theory”, Ron M. Roth, Cambridge University Press, 2006.
[5] “Algebraic Codes for Data Transmission”, Richard E. Blahut, Cambridge University Press, 2003.
[6] “Introduction to Error Correcting Codes”, Michael Purser, Artech House Inc. 1995.
Still further in accordance with at least one embodiment of the present invention, the power saving unit comprises power saving logic operative to selectively deactivate any of a group of subsets of the functional units, the group comprising at least one predetermined subset of the plurality of functional units.
Additionally in accordance with at least one embodiment of the present invention, the power saving logic is operative to selectively deactivate an individual subset of functional units within the group of subsets, if all functional units in the individual subset are operative to compute terms whose degree exceeds the rank.
Further in accordance with at least one embodiment of the present invention, the group of subsets comprises at least one predetermined nested subset of the sequence of functional units, each predetermined nested subset including a sequence of functional units terminating in the functional unit in the sequence of functional units which has the highest degree.
Also provided, in accordance with at least one embodiment of the present invention, is a Chien search method operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the method comprising providing a sequence of functional units each operative to compute a corresponding term in the error locator polynomial, each term having a degree; and de-activating at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank.
Further in accordance with at least one embodiment of the present invention, a histogram of the number of errors per data block in the stream is known, and the method also comprises designing power saving logic operative to effect the de-activating, including selecting, for each predetermined subset, a cut-off point in the sequence of functional units above which all functional units belong to the predetermined subset, wherein the cut-off point is selected to maximize power saving achieved by the de-activating, given the histogram.
Further in accordance with at least one embodiment of the present invention, the data blocks are Reed-Solomon-encoded.
Additionally in accordance with at least one embodiment of the present invention, the data blocks are stored in a flash memory device.
A particular feature of certain embodiments of the present invention is that registers can be controlled, in groups pre-defined at the design stage to include one or more registers sharing a single clock, by gating or not gating the group clock.
A particular feature of certain embodiments of the present invention is that error information is used to determine power consumption.
FIG. 1A is a simplified functional block diagram illustration of a communication system which performs a low power Chien search using a subset of taps which depend on the rank of the error locator polynomial of the Chien search, all in accordance with certain embodiments of the present invention;
FIG. 1B is a simplified functional block diagram illustration of the Chien search performing ECC decoder of FIG. 1A, constructed and operative in accordance with certain embodiments of the present invention which may be based on BCH or Reed-Solomon algorithms;
FIG. 3 is a simplified prior art functional block diagram illustration of a Chien search apparatus for error locator polynomial evaluation;
FIG. 4 is a diagram of a design process, constructed and operative in accordance with certain embodiments of the present invention, in which error information and optional complexity constraints are considerations in the design of a preferably optimal clock gating scheme;
FIG. 6A is a simplified functional block diagram illustration of a first example of a tap control scheme constructed and operative in accordance with certain embodiments of the present invention;
FIG. 6B is a simplified functional block diagram illustration of a second example of a tap control scheme constructed and operative in accordance with certain embodiments of the present invention;
FIG. 7 is a first table describing notation used in first portions of the following description;
FIG. 8 is a graph showing, on a logarithmic scale, an example of probabilities of various numbers of errors per page or other block of data, which graph is useful in designing certain embodiments of the present invention; and
FIG. 1A is a simplified functional block diagram illustration of an encoder-decoder system which performs a low power Chien search using a subset of taps which depends on the rank of the error locator polynomial of the Chien search, all in accordance with certain embodiments of the present invention. It is appreciated however that the applicability of the present invention includes all possible applications of Chien searches and is not limited to error correction decoders.
As shown in FIG. 1A, the theory of Error Correction Coding (ECC) comprises computing and adding a redundancy to the message m(x) which it is desired to transmit or store, making it into a codeword c(x) of some known codebook. The channel or medium through which the message is conveyed from transmitter to receiver or to the storage medium, adds errors e(x) to the codeword c(x), i.e. r(x)=c(x)+e(x) where r(x) is the received data. Errors may for example stem from various physical processes such as thermal noise, deterioration of storage medium over time and, after many read/write operations, inaccuracies in the transmitter or receiver hardware. The receiver, using the redundancy that was added to the message and the known codebook, is able to reconstruct the original message m′(x) and convey it to the intended target i.e. the message sink.
The BCH and RS codes are conventional cyclic error correction codes. The encoder for BCH and RS codes can be described in terms of a generation matrix G, thus the encoding process comprises a matrix multiplication c=mG, where c is the transmitted codeword and m is the message to be transmitted.
The decoding of BCH/RS codes comprises syndrome decoding, i.e. there exists a parity check matrix H which has the following property: GHT=0. It follows that cHT=mGHT=0.
The received vector r comprises the transmitted codeword c and the errors added in the channel i.e. r=c+e. The receiver computes the syndrome vector s using the parity check matrix i.e. s=rHT=cHT+eHT=mGHT+eHT=0+eHT=eHT, or in short s=eHT.
The construction of BCH and RS codes and the special form of the parity check matrix H are known. Due to the special form of the BCH and RS codes and the matrix H the set of equations s=eHT can be solved directly by exhaustive search in the decoder thereby to find the error vector e and correctly decode the received message. Since exhaustive search is a computationally unattractive way to implement the decoder, the problem is solved by introducing an Error Locator Polynomial (ELP) whose roots are the reciprocals of the error locations. Several algorithms exist to derive the error locator polynomial from the syndromes, such as Berlekamp-Massey and the Euclidean algorithms, e.g. as described in “Error Correction Coding Mathematical Methods and Algorithms”, Todd K. Moon, John Wiley & Sons, Inc., 2005. The error locator polynomial can be written as follows, where j (or v) denotes the number of errors in the received vector:
Λ(x)=Λ0+Λ1 x+Λ 2 x 2+Aj x j
Once the decoder computes the error locator polynomial, all is left for the decoder to do is to evaluate the error locator polynomial for all the elements of the field; the ones that zero the error locator polynomial are the error locations.
FIG. 1B is a simplified functional block diagram illustration of the ECC decoder of FIG. 1A, constructed and operative in accordance with certain embodiments of the present invention.
FIG. 1B depicts the decoding process of the BCH/RS decoder both for the binary BCH case and for the case of non-binary code, in which an additional functionality is provided (block 230): error value computation, e.g. based on Forney's algorithm.
The apparatus of FIGS. 1A and 1B have a wide variety of applications such as but not limited to flash memory applications e.g. as shown in FIG. 2.
Reference is now made to FIG. 3 which is a simplified prior art functional block diagram illustration of apparatus for error locator polynomial evaluation. Error locator polynomial evaluation typically uses the Chien search algorithm. The computations are all done in the GF(qm) which is a finite field. Denoting a as a primitive element, it is well known that all the field elements can be generated from consecutive powers of α i.e. α0, α1, . . . , αq̂m. Error locator polynomial evaluation or the “Chien-Search” then comprises of finding all the roots of Λ(x). x is evaluated for all powers of α i.e. x=1, α, α2, α3, . . . , αq̂m. This can be achieved by the hardware depicted in FIG. 3 which includes an array of registers 300 and an array of multipliers 330 together defining J “taps” or “functional units” 335, each comprising a register and a multiplier.
In FIG. 3, Reg_1 to Reg_J are J registers which are initiated prior to the beginning of operation to hold Λ_1, . . . , Λ_J i.e. the coefficients of the error locator polynomial. J is the error correction capability of the designed code, whereas j is not a constant over multiple operations of the circuit, but rather varies and denotes the number of errors in the currently decoded data block. The clk signal in FIG. 3 denotes the clock signal that clocks the Reg_1 . . . Reg_J registers. Const_1 . . . Const_J in FIG. 3 are constants of successive powers of the primitive element in the field α. The apparatus is shown in an initial state in which the registers Reg_1 to Reg_J store Λ_1 to Λ_J respectively; subsequently, at each cycle, the registers are updated.
In each successive clock (clk signal) the contents of each register Reg_1 . . . Reg_J is multiplied with a respective constant from among constants Const_1 . . . Const_J and latched into a respective one of the registers Reg_1 . . . Reg_J. Each register and associated multiplier forms a “tap” 335, as shown. An adder adds the partial sums of the error locator polynomial to produce sum A which is the evaluation of the error locator polynomial for x=αn at the n'th clock cycle. If A equals Λ0 at some clock n, this means, as described above, and as is well known in the art, that αn is a root of the error locator polynomial. It follows that an error has occurred in bit n (for binary BCH codes) or in symbol n (for non-binary BCH or RS codes) of the received data. Having iterated over all elements in the field, and identified all errors, decoding is complete.
59 taps are provided altogether. If 2 clock domains are provided, the clock gating unit is operative to deactivate, say, all taps from 20 to 59. The clock gating unit typically does so if the rank is known to be less than 20. If the rank is 20 or larger, the taps from 20 to 59 are active i.e. are not de-activated. Alternatively, 3 clock domains may be provided, such that all taps from (say) 10 to 59 may be de-activated, or alternatively, all taps from 20 to 59 may be de-activated, or alternatively, all taps may be active. These 3 options are used when the rank of the error locator polynomial is known to be smaller than 10, smaller than 20 but greater than 10, and greater than 20, respectively. The 3 clock domains therefore define 2 subsets of taps—the first including taps 10 to 19, or 10 to 59, in the sequence of taps, the second subset including taps 20 to 59. Another example would be having 3 clock domains, associated with taps 0-9, 10-20 and 21-59 respectively.
FIGS. 6A-6B are simplified functional block diagram illustrations of two examples of Chien search apparatus constructed in accordance with the embodiments of FIGS. 4-5 which use a number of taps determined by the rank of the error locator polynomial.
As described above, j denotes the actual number of errors in the currently decoded data, which is also the rank of the error locator polynomial such that j is known at the time Chien-Search (CS) computation begins. J denotes the maximum error correcting capability of the constructed BCH/RS code.
The designed hardware includes J parallel “taps” as in FIG. 3, which include one register (from among Reg1 . . . Reg_J) and one multiplier (from among Mul_1 . . . Mul_J) receiving one constant (from among Const_1 . . . Const_J). The apparatus is shown in an initial state in which the registers Reg_1 to Reg_J store Λ_1 to Λ_J respectively; subsequently, at each cycle, the registers are updated. If initially a particular Λ is zero the contents of the associated tap remain zero since multiplying by zero equals zero.
When the number of errors which occurs is less than the maximum error correction capability of the error correction code, all the coefficients of the error locator polynomial (Λ(x)) higher than j are equal to zero.
When j errors occur and j<J, natural power saving occurs; registers Reg_j+1 . . . Reg_J will constantly be equal to zero and the power associated with switching of the combinatorial logic and data inputs/outputs of the flip-flops is saved. But the power associated with the register's clock input still continues to draw power unnecessarily. This wasted power can represent a major part of the power dissipated by the circuit; specifically it is most wasteful at higher clock frequencies.
As shown, the clock signal (clk) that is fed to each of the registers may be gated depending on j, per each received data block. Each register need not receive its own gated clk; the registers may be partitioned into any suitable number of groups, such as 2 or 3 or more groups, typically according to the error probability of the application at hand.
In FIG. 6A, for example, gating logic is added to generate the gated clock “clk_1” that enables “clk_1” when j (number of errors) of the received data is greater than some predefined Vthr.
The v_thr inputs to the gating logic units in FIGS. 6A and 6B indicates how many errors need to occur in order to switch on (ungate) the corresponding docks.
The power saved in accordance with the above-described scheme can be computed, assuming, say, that the clock scheme is subdivided into 2 clk trees. The following description uses the notation presented in the table of FIG. 7.
The power dissipated in the traditional clk scheme for a particular received data block i.e. for a particular j, can be expressed as follows.
jEtap-clk-data+(J−j)Etap-clk
E old  -  total = ∑ V  P  ( j = V )  ( jE tap  -  clk  -  data + ( J - j )  E tap  -  clk )
Simplifying, and assuming Etap≈Etap-clk-data≈Etap-clk which is a reasonable simplification at fast clock frequencies, yields:
Eold-total=tEtap
The power dissipated in the clk scheme shown herein, for a particular received data block and particular j can be expressed as follows
jE tap-clk-data+(V thr −j)E tap-clk j≦V thr
jE tap-clk-data+(J−j)E tap-clk j>V thr
E new-total =P Vthr V thr E tap+(1−P Vthr)tE tap
Since PVthr≈1 and (1−PVthr) is small:
Enew-total=VthrEtap
Finally the power was reduced by factor of
( ≈ v thr J ) .
FIG. 8 shows a graph of an example of the probability of error on logarithmic scale vs. number of errors (i.e. rank of error locator polynomial) in a particular practical application. Setting Vthr=21 yields the optimal power saving for this particular application. In this example, even if only two groups of taps (2 clock domains) are defined, it can be shown that the power is nonetheless reduced by roughly 60%.
1) Express the power of the Chien-Search as a function of the number of allowed clock-domains, e.g., using the notation of FIG. 9:
E total = ∑ i = 0 l 1 - 1  P i  l 1  E  ( i , l 1 ) + ∑ i = l 2 l 2 - 1  P i  l 2  E  ( i , l 2 ) + … + ∑ i = l n - 1 l n - 1  P i  l n  E  ( i , l n )
Minimization of the above expression (Etotal) for I1, I2, . . . In, where I1, I2, . . . In denotes the clk-gating partition scheme, yields optimal power, however the present invention is not limited to those applications in which optimal (minimal) power is achieved.
It is appreciated that the teachings of the present invention can, for example, be implemented by suitably modifying, or interfacing externally with, flash controlling apparatus. The flash controlling apparatus controls a flash memory array and may comprise either a controller external to the flash array or a microcontroller on-board the flash array or otherwise incorporated therewithin. Examples of flash memory arrays include Samsung's K9XXG08UXM series, Hynix's HY27UK08BGFM Series, Micron's MT29F64G08TAAWP or other arrays such as but not limited to NOR or phase change memory. Examples of controllers which are external to the flash array they control include STMicroelectrocincs's ST7265x microcontroller family, STMicroelectrocincs's ST72681 microcontroller, and SMSC's USB97C242, Traspan Technologies' TS-4811, Chipsbank CBM2090/CBM 1190. Examples of commercial IP software for Flash file systems are: Denali's Spectra™ NAND Flash File System, Aarsan's NAND Flash Controller IP Core and Arasan's NAND Flash File System. It is appreciated that the flash controller apparatus need not be NAND-type and can alternatively, for example, be NOR-type or phase change memory-type.
3. Apparatus according to claim 1 wherein said power saving unit comprises power saving logic operative to selectively deactivate any of a group of subsets of said functional units, said group comprising at least one predetermined subset of said plurality of functional units.
6. A Chien search method operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the method comprising:
providing a sequence of functional units each operative to compute a corresponding term in the error locator polynomial, each term having a degree; and
de-activating at least one individual functional unit from among said sequence of functional units, said individual functional unit being operative, when active, to compute a term whose degree exceeds said rank.
9. Apparatus according to claim 1 wherein said data blocks are Reed-Solomon-encoded.
11. Apparatus according to claim 1 and also comprising an error locator polynomial generator operative to generate said error locator polynomial and output its rank to said power saving unit.
US12/595,640 2007-12-12 2008-09-17 Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications Active 2029-10-06 US8276051B2 (en)
US61071468 Continuation 2008-04-30
US20100058146A1 true US20100058146A1 (en) 2010-03-04
US8276051B2 US8276051B2 (en) 2012-09-25
US12/595,640 Active 2029-10-06 US8276051B2 (en) 2007-12-12 2008-09-17 Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications
US20150039975A1 (en) * 2013-02-27 2015-02-05 Kabushiki Kaisha Toshiba Error correction device and error correction method
US8990666B2 (en) 2010-09-16 2015-03-24 Samsung Electronics Co., Ltd. Decoder, method of operating the same, and apparatuses including the same
US20170126253A1 (en) * 2015-10-30 2017-05-04 Infineon Technologies Ag Error correction
WO2009074979A2 (en) 2009-06-18
JP2013141219A (en) 2013-07-18 Method of reading data from storage device, error correction device, and storage system including error correction code decoder
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