Source: https://patents.google.com/patent/US20060087450?oq=6008737
Timestamp: 2018-04-27 01:06:24
Document Index: 44462796

Matched Legal Cases: ['application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60']

US20060087450A1 - Remote sensor processing system and method - Google Patents
Remote sensor processing system and method Download PDF
US20060087450A1
US20060087450A1 US11243528 US24352805A US2006087450A1 US 20060087450 A1 US20060087450 A1 US 20060087450A1 US 11243528 US11243528 US 11243528 US 24352805 A US24352805 A US 24352805A US 2006087450 A1 US2006087450 A1 US 2006087450A1
US11243528
US7619541B2 (en )
The present application claims priority from U.S. provisional patent application No. 60/615,192, filed on Oct. 1, 2004; U.S. Provisional patent application No. 60/615,157, filed Oct. 1, 2004; U.S. provisional patent application No. 60/615,170 filed Oct. 1, 2004; U.S. provisional patent application No. 60/615,158 filed Oct. 1, 2004; U.S. provisional patent application No. 60/615,193 filed Oct. 1, 2004 and, United States provisional patent application No. 60/615,050, filed Oct. 1, 2004, which are incorporated herein by reference in their entirety and for all their teachings and disclosures..
This application is related to U.S. patent application Ser. No. 10/684,102 entitled IMPROVED COMPUTING ARCHITECTURE AND RELATED SYSTEM AND METHOD (Attorney Docket No. 1934-11-3), Ser. No. 10/684,053 entitled COMPUTING MACHINE HAVING IMPROVED COMPUTING ARCHITECTURE AND RELATED SYSTEM AND METHOD (Attorney Docket No. 1934-12-3), Ser. No. 10/684,057 entitled PROGRAMMABLE CIRCUIT AND RELATED COMPUTING MACHINE AND METHOD (Attorney Docket No. 1934-14-3), and Ser. No. 10/683,932 entitled PIPELINE ACCELERATOR HAVING MULTIPLE PIPELINE UNITS AND RELATED COMPUTING MACHINE AND METHOD (Attorney Docket No. 1934-15-3), which have a common filing date and owner and which are incorporated by reference.
FIG. 4 is a more detailed functional block diagram of a peer vector machine 40 that may be included in the system 30 of FIG. 3 according to one embodiment of the present invention. The peer vector machine 40 includes a host processor 42 corresponding to the host processor 38 of FIG. 3 and a pipeline accelerator 44 corresponding to the pipeline accelerator 32 of FIG. 3. The host processor 42 communicates with the pipeline accelerator 44 over the communications channel 36 (FIG. 3) and through a communications adapter 35. The communications interface 35 and host processor 42 communicate data over the communications channel 36 according to an industry standard interface in one embodiment of present invention, which facilitates the design and modification of the machine 40. If the circuitry in the pipeline accelerator 44 changes, the communications adapter 35 need merely be modified to interface this new accelerator to the channel 36. In the example embodiment of FIG. 4,the sensors 34 are coupled directly to one of a plurality of hardware or hardwired pipelines 74 1-n in the pipeline accelerator 44. The hardwired pipeline 74 1, processes data without executing program instructions, as do each of the pipelines 74 to perform required tasks. A firmware memory 52 stores the configuration firmware for the accelerator 44 to configure the hardwired pipelines 74 to execute these tasks, as will be described in more detail below.
The peer vector machine 40 generally and the host processor 42 and pipeline accelerator 44 more specifically are described in more detail in U.S. patent applicationn. Ser. No. 10/684,102 entitled IMPROVED COMPUTING ARCHITECTURE AND RELATED SYSTEM AND METHOD (Attorney Docket No. 1934-11-3), application. Ser. No. 10/684,053 entitled COMPUTING MACHINE HAVING IMPROVED COMPUTING ARCHITECTURE AND RELATED SYSTEM AND METHOD (Attorney Docket No. 1934-12-3), application. Ser. No. 10/683,929 entitled PIPELINE ACCELERATOR FOR IMPROVED COMPUTING ARCHITECTURE AND RELATED SYSTEM AND METHOD (Attorney Docket No. 1934-13-3), aApplication. Ser. No. 10/684,057 entitled PROGRAMMABLE CIRCUIT AND RELATED COMPUTING MACHINE AND METHOD (Attorney Docket No. 1934-14-3), and Ser. No. 10/683,932 entitled PIPELINE ACCELERATOR HAVING MULTIPLE PIPELINE UNITS AND RELATED COMPUTING MACHINE AND METHOD (Attorney Docket No. 1934-15-3), all of which have a common filing date of Oct. 9, 2003 and a common owner and which are incorporated herein by reference.
The pipeline accelerator 44 is disposed on at least one programmable logic integrated circuit (PLIC) (not shown) and includes hardwired pipelines 74 1-74 n, which process respective data without executing program instructions. The firmware memory 52 stores the configuration firmware for the accelerator 44. If the accelerator 44 is disposed on multiple PLICs, these PLICs and their respective firmware memories may be disposed in multiple pipeline units (FIG. 4). The accelerator 44 and pipeline units are discussed further below and in previously cited U.S. patent application. No. 10/683,932 entitled PIPELINE ACCELERATOR HAVING MULTIPLE PIPELINE UNITS AND RELATED COMPUTING MACHINE AND METHOD (Attorney Docket No. 1934-15-3). Alternatively, the accelerator 44 may be disposed on at least one application specific integrated circuit (ASIC), and thus may have internal interconnections that are not configurable. In this alternative, the machine 40 may omit the firmware memory 52. Furthermore, although the accelerator 44 is shown including multiple pipelines 74, it may include only a single pipeline. In addition, although not shown, the accelerator 44 may include one or more processors such as a digital-signal processor (DSP).
As previously mentioned, in the embodiment of FIG. 4 the sensors 34 are shown coupled to the pipeline bus 50, which corresponds to the communications channel 36 of FIG. 3. In this embodiment, the sensors 34 would of course include suitable circuitry for communicating raw data from the sensors over the pipeline bus, typically through an industry standard communications protocol or interface such as RapidIO. In another embodiment, the sensors 34 are coupled to the bus 50 and communicate data via the bus to the pipeline accelerator 44. The data provided is stored in memory (not shown) in the pipeline accelerator 44, and is read out of memory and processed by the appropriate one of the hardware pipelines 74. The accelerator 44 may further include a data output port for directly supplying data to the sensors 34, which corresponds to the interconnection between the sensors and pipeline 74, in FIG. 4. The pipeline accelerator 44 can supply data to the sensors 34 where the system 30 containing the peer vector machine 40 is a sonar system and the sensors are to be utilized to transmit desired sound waves, as previously mentioned. Data to be supplied to the sensors 34 is supplied over the pipeline bus 50 and communications channel 36 and stored in memory (not shown) in the accelerator 44, and is thereafter retrieved from memory and output through the data output port to the sensors.
FIG. 5 is a more detailed block diagram of the pipeline accelerator 44 of FIG. 4 according to one embodiment of the present invention. The accelerator 44 includes one or more pipeline units 78, one of which is shown in FIG. 5. Each pipeline unit 78 includes a pipeline circuit 80, such as a PLIC or an ASIC. As discussed further below and in previously cited U.S. patent application Ser. No. 10/683,932 entitled PIPELINE ACCELERATOR HAVING MULTIPLE PIPELINE UNITS AND RELATED COMPUTING MACHINE AND METHOD (Attorney Docket No. 1934-15-3), each pipeline unit 78 is a “peer” of the host processor 42 and of the other pipeline units of the accelerator 44. That is, each pipeline unit 78 can communicate directly with the host processor 42 or with any other pipeline unit. Thus, this peer-vector architecture prevents data “bottlenecks” that otherwise might occur if all of the pipeline units 78 communicated through a central location such as a master pipeline unit (not shown) or the host processor 42. Furthermore, it allows one to add or remove peers from the peer-vector machine 40 (FIG. 3) without significant modifications to the machine.
The hardwired pipelines 74 1-74 n perform respective operations on data as discussed above in conjunction with FIG. 3 and in previously cited U.S. patent application Ser. No. 10/684,102 entitled IMPROVED COMPUTING ARCHITECTURE AND RELATED SYSTEM AND METHOD (Attorney Docket No. 1934-11-3), and the communication shell 84 interfaces the pipelines to the other components of the pipeline circuit 80 and to circuits (such as a data memory 92 discussed below) external to the pipeline circuit.
The configuration manager 90 sets the soft configuration of the hardwired pipelines 74 1-74 n, the communication interface 82, the communication shell 84, the controller 86, the exception manager 88, and the interface 91 in response to soft-configuration data from the host processor 42 (FIG. 3)—as discussed in previously cited U.S. patent application Ser. No. 10/684,102 entitled IMPROVED COMPUTING ARCHITECTURE AND RELATED SYSTEM AND METHOD (Attorney Docket No. 1934-11-3), the hard configuration denotes the actual topology, on the transistor and circuit-block level, of the pipeline circuit 80, and the soft configuration denotes the physical parameters (e.g., data width, table size) of the hard-configured components. That is, soft configuration data is similar to the data that can be loaded into a register of a processor (not shown in FIG. 4) to set the operating mode (e.g., burst-memory mode) of the processor. For example, the host processor 42 may send soft-configuration data that causes the configuration manager 90 to set the number and respective priority levels of queues in the communication interface 82. The exception manager 88 may also send soft-configuration data that causes the configuration manager 90 to, e.g., increase the size of an overflowing buffer in the communication interface 82.
As discussed above in conjunction with FIG. 5, where the pipeline circuit 80 is a PLIC, the firmware memory 52 stores the firmware that sets the hard configuration of the pipeline circuit. The memory 52 loads the firmware into the pipeline circuit 80 during the configuration of the accelerator 44, and may receive modified firmware from the host processor 42 (FIG. 4) via the communication interface 82 during or after the configuration of the accelerator. The loading and receiving of firmware is further discussed in previously cited U.S. patent application Ser. No. 10/684,057 entitled PROGRAMMABLE CIRCUIT AND RELATED COMPUTING MACHINE AND METHOD (Attorney Docket No. 1934-14-3).
Still referring to FIG. 5, the pipeline circuit 80, data memory 92, and firmware memory 52 may be disposed on a circuit board or card 98, which may be plugged into a pipeline-bus connector (not shown) much like a daughter card can be plugged into a slot of a mother board in a personal computer (not shown). Although not shown, conventional ICs and components such as a power regulator and a power sequencer may also be disposed on the card 98 as is known sensors 34
Further details of the structure and operation of the pipeline unit 78 will now be discussed in conjunction with FIG. 6. FIG. 6 is a block diagram of the pipeline unit 78 of FIG. 5 according to an embodiment of the invention. For clarity, the firmware memory 52 is omitted from FIG. 6. The pipeline circuit 80 receives a master CLOCK signal, which drives the below-described components of the pipeline circuit either directly or indirectly. The pipeline circuit 80 may generate one or more slave clock signals (not shown) from the master CLOCK signal in a conventional manner. The pipeline circuit 80 may also a receive a synchronization signal SYNC as discussed below. The data memory 92 includes an input dual-port-static-random-access memory (DPSRAM) 100, an output DPSRAM 102, and an optional working DPSRAM 104.
The controller 86 includes a sequence manager 148 and a synchronization interface 150, which receives one or more synchronization signals SYNC. A peer, such as the host processor 42 (FIG. 3), or a device (not shown) external to the peer-vector machine 40 (FIG. 3) may generate the SYNC signal, which triggers the sequence manager 148 to activate the hardwired pipelines 74 1-74 n as discussed below and in previously cited U.S. patent application Ser. No. 10/683,932 entitled PIPELINE ACCELERATOR HAVING MULTIPLE PIPELINE UNITS AND RELATED COMPUTING MACHINE AND METHOD (Attorney Docket No. 1934-15-3). The synchronization interface 150 may also generate a SYNC signal to trigger the pipeline circuit 80 or to trigger another peer. In addition, the events from the input-event queue 124 also trigger the sequence manager 148 to activate the hardwired pipelines 74 1-74 n as discussed below.
Furthermore, the sequence manager 148 maintains a predetermined internal operating synchronization among the hardwired pipelines 74 1-74 n. For example, to avoid all of the pipelines 74 1-74 n simultaneously retrieving data from the DPSRAM 100, it may be desired to synchronize the pipelines such that while the first pipelineu 74 1 is in a preprocessing state, the second pipeline 742 is in a processing state and the third pipeline 743 is in a post-processing state. Because a state of one pipeline 74 may require a different number of clock cycles than a concurrently performed state of another pipeline, the pipelines 74 1-74 n may lose synchronization if allowed to run freely. Consequently, at certain times there may be a “bottle neck,” as, for example, multiple pipelines 74 simultaneously attempt to retrieve data from the DPSRAM 100. To prevent the loss of synchronization and its undesirable consequences, the sequence manager 148 allows all of the pipelines 74 to complete a current operating state before allowing any of the pipelines to proceed to a next operating state. Therefore, the time that the sequence manager 148 allots for a current operating state is long enough to allow the slowest pipeline 74 to complete that state. Alternatively, circuitry (not shown) for maintaining a predetermined operating synchronization among the hardwired pipelines 74 1-74 n may be included within the pipelines themselves.
Typically, a SYNC signal triggers a time-critical function but requires significant hardware resources; comparatively, an event typically triggers a non-time-critical function but requires significantly fewer hardware resources. As discussed in previously cited U.S. patent application Ser. No. 10/683,932 entitled PIPELINE ACCELERATOR HAVING MULTIPLE PIPELINE UNITS AND RELATED COMPUTING MACHINE AND METHOD (Attorney Docket No. 1934-15-3), because a SYNC signal is routed directly from peer to peer, it can trigger a function more quickly than an event, which must makes its way through, e.g., the pipeline bus 50 (FIG. 3), the input-data handler 120, and the input-event queue 124. But because they are separately routed, the SYNC signals require dedicated circuitry, such as routing lines, buffers, and the SYNC interface 150, of the pipeline circuit 80. Conversely, because they use the existing data-transfer infrastructure (e.g. the pipeline bus 50 and the input-data handler 120), the events require only the dedicated input-event queue 124. Consequently, designers tend to use events to trigger all but the most time-critical functions.
For some examples of function triggering and generally a more detailed description of function triggering, see application. No. 10/683,929 entitled PIPELINE ACCELERATOR FOR IMPROVED COMPUTING ARCHITECTURE AND RELATED SYSTEM AND METHOD (Attorney Docket No. 1934-13-3).
local processing circuitry physically positioned proximate the sensor and electrically coupled to the sensor, the local processing circuitry including an output port adapted to be coupled to a communications channel and the local processing circuitry operable to process data from the sensor to generate processed sensor data and to provide the processed data on the output port.
2. The sensor assembly of claim 1 wherein the local processing circuitry applies the processed sensor data on the output port according to a bandwidth-enhancement communications protocol.
3. The sensor assembly of claim 2 wherein the bandwidth-enhancement communications protocol comprises one of the xDSL protocols.
4. The sensor assembly of claim 1 wherein the processed sensor data comprises a message including a header portion indicating a destination of the message and a payload portion.
5. The sensor assembly of claim 1 wherein the local processing circuitry comprises a peer vector machine.
6. The sensor assembly of claim 1 wherein the local processing circuitry comprises a pipeline accelerator.
7. The sensor assembly of claim 6 wherein the pipeline accelerator is formed in a field programmable gate array (FPGA).
8. The sensor assembly of claim 7 wherein the pipeline accelerator comprises:
receive data from the sensor;
load the data into the memory;
retrieve the data from the memory;
process the retrieved data; and
provide the processed retrieved data to a host processor coupled to the hardwired-pipeline circuit via the communications channel and output port.
9. The sensor assembly of claim 6 wherein the pipeline accelerator includes an input port and wherein the sensor is coupled to the input port.
10. The sensor assembly of claim 8 further comprising a plurality of sensors and a plurality of hardwired-pipeline circuits, each hardwired-pipeline circuit being coupled to a respective sensor.
11. The sensor assembly of claim 1 wherein the sensor is coupled to the local processing circuitry through the communications channel.
local processing circuitry physically positioned proximate the sensor and electrically coupled to the sensor and to the communications channel, the local processing circuitry operable to process data from the sensor to generate processed sensor data and to communicate the data over the communications channel to the host processor.
13. The system of claim 12 wherein the local processing circuitry communicates the processed sensor data over the communications channel according to a bandwidth-enhancement communications protocol.
14. The system of claim 13 wherein the bandwidth-enhancement communications protocol comprises one of the xDSL protocols.
15. The system of claim 12 wherein the processed sensor data comprises a message including a header portion indicating a destination of the message and a payload portion.
16. The system of claim 12 wherein the local processing circuitry comprises a peer vector machine.
17. The system of claim 12 wherein the local processing circuitry comprises a pipeline accelerator.
18. The system of claim 17 wherein the pipeline accelerator is formed in a field programmable gate array (FPGA).
19. The system of claim 17 wherein the pipeline accelerator comprises:
20. The system of claim 12 wherein the pipeline accelerator includes an input port and wherein the sensor is coupled to the input port.
21. The system of claim 19 further comprising a plurality of sensors and a plurality of hardwired-pipeline circuits, each hardwired-pipeline circuit being coupled to a respective sensor.
22. The system of claim 12 wherein the sensor is coupled to the local processing circuitry through the communications channel.
23. A method of processing data from a sensor, comprising:
receiving data from the sensor;
locally processing the received data physically proximate the sensor; and
communicating the processed data over a communications channel.
24. The method of claim 23 further comprising receiving the processed data communicated over the communications channel and making operational decisions using the received processed data.
25. The method of claim 23 wherein locally processing the received data physically proximate the sensor comprises
26. The method of claim 23 wherein communicating the processed data over a communications channel comprises communicating the processed data using a bandwidth-enhancement communications protocol.
27. The method of claim 26 wherein the bandwidth-enhancement communications protocol comprises one of the xDSL protocols.
28. A sensor assembly, comprising:
local processing circuitry physically positioned proximate the sensor and electrically coupled to the sensor, the local processing circuitry including an output port adapted to be coupled to a degraded communications channel, the local processing circuitry operable to process data from the sensor to generate processed sensor data and to enhance the bandwidth of such data, the local processing circuitry providing the processed and bandwidth enhanced data on the output port for communication over the degraded communications channel.
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SCHULZ, KENNETH R.;HAMM, ANDREW;RAPP, JOHN;REEL/FRAME:017461/0129;SIGNING DATES FROM 20051028 TO 20051101