Source: http://www.google.com/patents/US7049837?dq=5,825,242
Timestamp: 2017-10-20 07:34:26
Document Index: 577326470

Matched Legal Cases: ['arts 4', 'arts 51', 'arts 51', 'arts 51', 'arts 4', 'in fine', 'art 4', 'art 8', 'art 4', 'art 8', 'art 8', 'art 4', 'art 8', 'art 4', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8']

Patent US7049837 - Probe sheet, probe card, semiconductor test equipment and semiconductor ... - Google Patents
A probe card has first contact terminals electrically connected to the fine-pitch electrodes of a test target; wirings drawn from the first contact terminals; and second contact terminals electrically connected to the wirings, wherein the first contact terminals are formed each using an anisotropically...http://www.google.com/patents/US7049837?utm_source=gb-gplus-sharePatent US7049837 - Probe sheet, probe card, semiconductor test equipment and semiconductor device fabrication method
Publication number US7049837 B2
Application number US 10/676,609
Also published as CN1281966C, CN1512186A, US20040070413
Publication number 10676609, 676609, US 7049837 B2, US 7049837B2, US-B2-7049837, US7049837 B2, US7049837B2
Inventors Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akio Hasebe
Patent Citations (17), Referenced by (55), Classifications (32), Legal Events (6)
US 7049837 B2
(1) A probe sheet comprising contact terminals that get into contact with electrodes provided on a wafer; wirings drawn from the contact terminals; and electrode pads electrically connected to the wirings, wherein a pitch of the electrode pads is wider than a pitch of the contact terminals.
(2) A probe card comprising a probe sheet having contact terminals that get into contact with electrodes provided on a wafer; and a multi-layer wiring substrate on which electrodes, which are electrically connected to the contact terminals, are provided on a surface opposed to the wafer, wherein a pitch of the electrodes provided on the surface of the multi-layer wiring substrate opposed to the wafer is wider than a pitch of the contact terminals.
(3) A probe card comprising contact terminals that get in contact with electrodes provided on a wafer; and a multi-layer wiring substrate having electrodes electrically connected to the contact terminals, wherein the electrodes of the multi-layer wiring substrate are provided in a device-opposed-area on the multi-layer wiring substrate and a pitch of the electrodes is wider than a pitch of the contact terminals.
(4) Semiconductor test equipment comprising a stage on which a wafer is mounted; and a probe card having contact terminals that get in contact with electrodes of semiconductor devices formed on the wafer and electrically connected to a tester that tests electrical characteristics of the semiconductor devices wherein the probe card comprises a probe sheet having the contact terminals and a multi-layer wiring substrate whose electrodes electrically connected to the contact terminals are provided on a surface opposed to the wafer and wherein a pitch of the electrodes of the multi-layer wiring substrate provided on the surface opposed to the wafer is wider than a pitch of the contact terminals.
(5) A semiconductor device fabrication method comprising the steps of creating circuits on a wafer to form semiconductor devices; testing electrical characteristics of the semiconductor devices; and dicing the wafer into semiconductor devices wherein, in the step of testing electrical characteristics of the semiconductor devices, a plurality of semiconductor devices are tested at a time using a probe card comprising a probe sheet having contact terminals that get in contact with electrodes of the semiconductor devices and a multi-layer wiring substrate electrically connected to the contact terminals and having electrodes, whose pitch is wider than a pitch of the contact terminals, on a surface opposed to the wafer.
FIGS. 3A–3B show examples of wiring patterns on a probe sheet on a probe card of the present invention;
FIGS. 10A–10G are diagrams showing a part of the fabrication process for forming a probe sheet (structure) in a probe card of the present invention;
FIGS. 11A–11D are diagrams showing the fabrication process that follows FIGS. 10A–10G;
FIGS. 12A–12G are diagrams showing another fabrication process, in order of steps, for forming a probe sheet in a probe card of the present invention;
FIGS. 13A–13D are diagrams showing another fabrication process, in order of steps, for forming a probe sheet in a probe card of the present invention;
FIGS. 13E–13F are schematic cross section diagrams showing the probe sheet in the probe card of the present invention;
FIGS. 14A–14B are diagrams showing another fabrication process, in order of steps, for forming a probe sheet in a probe card of the present invention;
FIGS. 15A–15C are diagrams showing another fabrication process, in order of steps, for forming a probe sheet in a probe card of the present invention;
FIGS. 16A–16B are diagrams showing another fabrication process, in order of steps, for forming a probe sheet in a probe card of the present invention;
FIGS. 17A–17B are diagrams showing another fabrication process, in order of steps, for forming a probe sheet in a probe card of the present invention;
FIGS. 18A–18B are diagrams showing another fabrication process, in order of steps, for forming a probe sheet in a probe card of the present invention;
FIGS. 22A–22B are top views showing indentations left on an electrode pad during a test process, FIG. 22A shows indentations left on an aluminum electrode pad, and FIG. 22B shows indentations left on a gold bump;
FIGS. 23A–23C are schematic cross section diagrams showing typical examples of semiconductor devices packaged or bump-formed after a test process, FIG. 23A is a schematic cross section diagram of an QFP, FIG. 23B is a schematic cross section diagram of a BGA, and FIG. 23C is a schematic cross section diagram of a flip-chip type package;
Major technical terms used in this specification are defined as follows. A semiconductor device may be in any form; that is, a wafer on which integrated circuits are formed, a semiconductor device itself, or a packaged semiconductor device (QFP, BGA, CSP, and so on). A probe sheet refers to a thin film, about 10 μm to 100 μm in thickness, on which contact terminals that will get in contact with a test target and wirings drawn from the contact terminals, as well as electrodes on the wirings for external connection, are provided. A probe card refers to a structure (for example, a structure shown in FIGS. 2A–2C) having terminals that will get in contact with a test target, a multi-layer wiring substrate, and so on. Semiconductor test equipment refers to test equipment having a probe card and a sample-mounting table on which a test target is mounted.
A number of LSI semiconductor devices (chip) 2, which are an example of a test target, are formed on a wafer 1 as shown in FIGS. 1A–1B and, then, cut into individual die for use. FIG. 1A is a perspective view showing the wafer 1 on which many semiconductor devices 2 are arranged, and FIG. 1B is a close-up perspective view showing one semiconductor device 2. On the surface of the semiconductor device 2, many electrodes 3 are arranged along its four sides.
Another tendency is that the high-temperature operation test (85° C.–150° C.) is made by putting semiconductor devices in a high temperature environment to clearly make sure their characteristics and reliability.
The semiconductor test equipment according to the present invention is compatible with dense, fine-pitch electrodes and, in addition, makes possible various types of check including the multiple-chip simultaneous probing test and the high-speed electrical signal (100 MHz—several GHz) test.
In addition, a part of the construction material of the probe card in the semiconductor test equipment uses a material, which has a heat resistance of 150° C. and a linear expansion coefficient approximately equal to that of a test object, prevents the tip of the probe from being misaligned at the ambient temperature.
FIGS. 2A–2C show the major parts of a probe card in a first embodiment of the present invention and show, in stages, the probing-time operation when there is a slight slant between the electrodes on the wafer and the contact terminals on the test equipment. FIG. 2A is a cross section diagram showing the status of the test equipment immediately before the probing operation, FIG. 2B is a cross section diagram showing the status of the test equipment that initially follows the slant of a wafer, and FIG. 2C is a cross section diagram showing the status of the test equipment that adds a desired load on the wafer surface to make an electrical characteristic test.
The parallel motion and pressure mechanism that moves the probe sheet 4 comprises the probe sheet holding substrate 6 that are pressed onto temporary parallel motion holding members (bottom) 7, fixed on the multi-layer wiring substrate 50, by a plurality of auxiliary springs 20; and the pressure member holding substrate 11 a that is pressed onto temporary parallel motion holding members (top) 10, fixed on the multi-layer wiring substrate 50, by a plurality of main springs 21. The spring probe 12 inserted into the pressure member 11 is positioned right above the electrode 4 d on the probe sheet 4 but not in contact with the electrode 4 d. It is easily understood that the spring probe 12 may be slightly in contact with the electrode 4 d.
FIG. 2B shows the next stage in which the probe sheet 4 is pressed onto the surface of the wafer 1 that is at a slant. This causes an initial variation in the probe sheet 4 to be transmitted to the probe sheet holding substrates 6 via the probe sheet frame 5 and pushes up a part of auxiliary springs 20 to make the probe sheet 4 follow the slant of the wafer 1. In this state, all contact terminals are in contact with the electrodes on the wafer. Minimizing the pressure of the auxiliary springs 20 (for example, about 1N) reduces the load on the contact terminals that first get into contact and, at the same time, allows all contact terminals to be brought into contact with the electrodes under a light load.
FIG. 2C shows the test equipment in the last stage in which the test equipment applies a desired load to the surface of the wafer 1 to make an electrical characteristic test. In this state, the total load of the main springs 21, auxiliary springs 20, and spring probes 12 is applied to all contact terminals with the spring probes 12 in contact with the electrodes 4 d on the probe sheet 4. Electrical signals for use in testing are sent to, and received from, a tester (not shown), which tests the electrical characteristics of semiconductor devices, through contact terminals 4 a in contact with the electrodes 3 on the wafer 1, connection electrode parts 4 b, pitch extension wires 4 c, electrodes 4 d, spring probes 12, electrodes 50 a, internal wires 50 b, and electrodes 50 c.
The electrode 50 a and the electrode 50 c in the multi-layer wiring substrate 50 described above are electrically connected via substrate-installed parts 51 that include capacitors and resistors for preventing fluctuations in test signals of semiconductor devices and fuses for cutting off over-currents of faulty semiconductor devices. To achieve the effect described above, fuses may be provided, one for each electrode or semiconductor device or one for a plurality of electrodes or semiconductor devices. In the structure described above, wirings are drawn almost vertically from the contact terminals (spring probes in the first embodiment) and are connected to the electrodes 50 a in the multi-layer wiring substrate. This structure allows the substrate-installed parts 51 to be placed near the electrodes 3 on the wafer 1 and minimizes the distance from the electrodes 3 to the substrate-installed parts 51, thus stabilizing the signals and allowing high-speed signals to be processed. It is desirable that the electrodes 50 a be formed in a device-opposing area on the multi-layer wiring substrate. The device-opposing area on the multi-layer wiring substrate refers to an area on the multi-layer wiring substrate that is above the probe sheet, an area created above semiconductor devices that are created on the wafer and that are to be tested, or an area near that area.
The following describes a wiring pattern on the probe sheet 4 described above with reference to FIGS. 3A–3B.
FIGS. 3A–3B show an example of a wiring pattern on the probe sheet on which contact terminals 4 a, connection electrode parts 4 b, pitch extension wires 4 c, and vertical wire-drawing electrodes 4 d (connection electrodes for spring probe or wire probe) are formed.
For the contact terminals 4 a provided on the probe sheet 4, pyramid-shaped or truncated-pyramid-shaped contact terminals formed by utilizing the holes created by anisotropic etching on a crystalline member are used. This provides a stable contact resistor (about 0.05Ω–0.1Ω) having a low stylus force (contact pressure with an electrode is about 3–50 mN per pin), prevents damages to the chip, and minimizes indentations that may be created on the semiconductor device during the test. The details of the contact terminals 4 a and probe sheet 4, as well as their production method, will be described later.
The probe sheet 4 with the wiring pattern shown in FIGS. 3A–3B is installed on the press mechanism shown in FIGS. 2A–2C to complete a probe card. That is, as shown in FIG. 4, the spring probes 12 are first pushed into the pressure member 11, which is composed of the pressure member holding substrate 11 a positioned and fixed between the spring probe positioning upper substrate 11 b and the spring probe positioning lower substrate 11 c by dowel pins 16. With the pressure member 11 held inside the temporary parallel motion holding members (top) 10, the temporary parallel motion holding members (top) 10 is fixed on the multi-layer wiring substrate installation fixing plates 15. Next, with the probe sheet holding substrates 6 held inside the probe sheet frame 5 of the probe sheet 4 by the temporary parallel motion holding member (bottom) 7, the temporary parallel motion holding member (bottom) 7 is fixed on the multi-layer wiring substrate installation fixing plates 15. Next, the fixing plates 15 are positined with the dowel pins 16 and fixed on the multi-layer wiring substrate 50. After that, the auxiliary springs 20 and the main springs 21 are fixed on the multi-layer wiring substrate installation fixing plates 15 such that the load becomes a desired initial load. In this way, the probe card is built.
Next, with reference to FIG. 5, a probe card in a second embodiment of the present invention will be described. In this embodiment, wire probes 12 a are used instead of the spring probes 12 in FIGS. 2A–2C. Wires, used for the wire-drawing connection parts, enable the electrodes to be arranged in finer pitches than in the first embodiment in which spring probe widths result in restrictions, making it possible to increase the density of semiconductor device electrodes 3. The probing operation performed when there is a slight slant between the electrodes 3 on the surface of the wafer 1 and the contact terminals 4 a on the probe card is the same as that in the description of FIGS. 2A–2C and, therefore, the description is omitted.
FIG. 6 is a cross section diagram showing the major part of a probe card in a third embodiment of the present invention. Bonding wires 55 are used for conduction from the lead-wire electrodes 4 d on a probe sheet 4 to the electrodes 50 a on a multi-layer wiring substrate 50. The bonding wire 55 is, for example, a gold wire or a gold wire coated with insulating materials. The moving action part of the probe card is constituted by a main spring (center pivot) 21 a that fixes the probe sheet 4 onto a probe sheet holding substrate 6 a through a probe sheet frame 5, that presses the probe sheet holding substrate 6 a onto a temporary parallel motion support member (bottom) 7 a fixed on the multi-layer wiring substrate 50 through a plurality of auxiliary springs 20, and that is positioned in the center of the probe sheet holding substrate 6 a and fixed on the multi-layer wiring substrate 50. In this case, the tip of the main spring 21 a is slightly spaced (about 0.05 mm) from the upper surface of the probe sheet holding substrate 6 a. This prevents the load of the main spring 21 a from placing on a part of the contact terminals before all contact terminals get in contact with the electrodes on the wafer surface during the initial ‘follow-operation’ and thus prevents the load from concentrating on a part of the contact terminals. When there is a slight slant between the electrodes on the wafer surface and the contact terminals on the probe card, the operation is performed as follows during the probing operation. That is, the probe sheet 4 is pressed on the surface of the wafer 1 that is at a slant, the initial variation in the probe sheet 4 is transmitted to the probe sheet holding substrate 6 a via the probe sheet frame 5, a part of the auxiliary springs 20 are pushed up to cause the sheet to follow the slant of the wafer 1, and all contact terminals get into contact with the electrodes on the wafer. Minimizing the pressure of the auxiliary springs 20 (for example, about 1N) reduces the load on the contact terminals that first get into contact and, at the same time, allows all contact terminals to be brought into contact with the electrodes under a light load.
Further pressing the probe sheet 4 until a predetermined value (overdrive amount) is reached adds the total load (a desired load) of the main spring 21 a and the auxiliary springs 20 to all contact terminals. In this state, electrical signals for use in testing are sent to, and received from, a tester (not shown) through contact terminals 4 a in contact with the electrodes 3 on the wafer 1, pitch extension wires 4 c, electrodes 4 d, bonding wires 55, electrodes 50 a, internal wirings 50 b, and electrodes 50 c.
FIG. 7 is a cross section diagram showing the major part of a probe card in a fourth embodiment of the present invention. This probe card differs from the probe card in the first embodiment in that one end of a spring probe 12 is in contact with an electrode 60 a formed on an electrode fixing substrate 60 instead of the electrodes 50 a on the multi-layer wiring substrate 50 shown in FIGS. 2A–2C. In this configuration, one end of the spring probe is connected, via a lead wire 60 b and through soldering, from the electrode 60 a to an electrode 50 d on the multi-layer wiring substrate 50 on which the electrode fixing substrate 60 is fixed. This configuration allows the connection between lead wire 60 b and the electrode 50 d on the multi-layer wiring substrate 50 to be changed, eliminates the need for the multi-layer wiring substrate 50 to be created for each wiring pattern on the probe sheet 4 but allows it to be shared, and therefore lowers the cost. In addition, the ability to remove the spring probes 12 allows the probe card to be used flexibly on any wiring patterns on the probe sheet 4. The lead wire 60 b may be an enamel coated copper wire, a gold bonding wire, or a coaxial cable.
Next, with reference of FIGS. 10A–10G and FIGS. 11A–11D, the method for fabricating an example of a probe sheet (structure) used for the probe card will be described.
Out of the process for fabricating the probe card shown in FIGS. 2A–2C, FIGS. 11A–10G show a fabrication process for forming a metallic-film-reinforced thin film probe sheet. In particular, the figures show the fabrication process in order of steps. In this process, a truncated-pyramid-shaped contact terminal tip is formed on a pitch extension wire using an anisotropically etched, truncated-pyramid-shaped hole formed on a silicon wafer 80, which is used as a cast. Then, a metallic-film-reinforced thin film probe sheet is formed by adhering a metallic film to a polyimide adhesive sheet and by processing the metallic film to form a lead-wire electrode.
First, the step shown in FIG. 10A is performed. In this step, about 0.5 μm of a silicon dioxide film 81 is formed on both sides of the silicon wafer (100) 80, which is 0.2 mm–0.6 mm in thickness, through thermal oxidation. A photo-resist 85 is coated and, after forming a pattern the through photolithography process, the silicon dioxide film 81 is removed by etching with a mixture of hydrofluoric acid and ammonium fluoride with the photo-resist 85 as the mask.
Next, the step shown in FIG. 10D is performed. First, the conductive coating 83 exposed in the opening of the polyimide film 84 is electroplated, with the conductive coating 83 as the electrode and with materials with a high degree of hardness as its major component, to form the contact terminal 4a and the connection electrode part 4 b as a unit. The conductive coating 83 is electroplated sequentially with materials with a high degree of hardness, for example, nickel 8 a, rhodium 8 b, and nickel 8 a, to form a contact terminal part 8 that includes both the contact terminal 4 a and the connection electrode part 4 b.
For example, for the adhesion layer 89, a polyimide adhesive sheet or an epoxy adhesive sheet is used. For the metallic film 90, a metallic sheet such as a 42 alloy (containing 42% nickel and 58% iron with linear expansion coefficient of 4 ppm/° C.) or an invar (for example, an alloy containing 36% nickel and 64% iron with linear expansion coefficient of 1.5 ppm/° C.) which has a low linear expansion coefficient and which has a linear expansion coefficient close to that of the silicon wafer (silicon material) 80 is used. This metallic sheet is adhered to the polyimide film 84 in which the wiring material 88 has been formed in the adhesion layer 89. This configuration increases the strength and the area of the probe sheet 4 that will be formed, ensures position precision in various situations and, in addition, prevents a misalignment that may be caused by a change in the temperature at test time. In view of this, a material with a linear expansion coefficient close to that of a semiconductor device to be tested may also be used for the metallic film 90 to ensure position precision at burn-in test time.
The above adhesion step is performed, for example, by placing the silicon wafer 80, on which the contact terminal part 8 and the polyimide film 84 having therein the wiring material 88 as shown FIG. 10D, onto the adhesion layer 89 and the metallic film 90 and then by applying a temperature higher than the glass transition temperature (Tg) of the adhesion layer 89 under the pressure of 10–200 Kgf/cm2 to do temperature/pressure adhesion in a vacuum.
For example, as the elastomer 93, an elastic resin is printed or applied by a dispenser or a silicon sheet is installed. The function of the elastomer 93 is that it reduces the overall impact when the tips of many contact terminals get in contact with the electrodes 3 arranged on the semiconductor wafer 1. Another function is that the elastomer 93, which has local irregular shapes, smoothes several μm or smaller variations in the heights of the contact terminals on the probe sheet to enable the contact terminals to fit them to the variations in height in the range of about ±0.5 μm to evenly get into contact with the contact targets (electrodes) 3 arranged on the semiconductor wafer 1.
Next, with reference to FIGS. 12A–12G, a probe sheet (structure) in a second embodiment that is different from the probe sheet (structure) described above, its structure, and its fabrication method will be described.
FIGS. 12A–12G show, in order of steps, another fabrication process for forming a probe sheet (structure).
First, after executing the step shown in FIGS. 10A–10B in which the truncated-pyramid-shaped etching hole 80 a is formed on the silicon wafer 80 and the silicon dioxide film 82 is formed on its surface, the step shown in FIG. 12A is performed. In this step, a photo-resist mask 85 a is formed on the surface of the conductive coating 83, which is formed on the silicon dioxide film 82, to create an opening for a contact terminal part 8.
Next, after the same steps as those in FIGS. 10F–10G and FIGS. 11A–11D, the probe sheet structure 105 shown in FIG. 12G is fabricated.
With reference to FIGS. 13A–13F, a probe sheet (structure) in a third embodiment, its structure, and its fabrication steps will be described.
The probe sheet fabrication method in this embodiment is the same as the probe sheet fabrication method described in FIGS. 10A–10G and FIGS. 11A–11D. The major difference is that a dummy terminal 107 similar to the contact terminal 4 a in shape is created at the same time the contact terminals 4 a is created. The dummy terminal 107 is provided to prevent the probe sheet 4 from being deformed when it gets into contact with the electrode 3 on the wafer 1 and to prevent a load from being concentrated initially on the end of the contact terminals. The dummy terminal 107 need not have the same shape as that of the contact terminal 4 a but, as shown in FIGS. 13A–13F, may have the shape of a truncated pyramid with a base area (area in contact with wafer 1) larger than that of the contact terminal 4 a. A similar dummy terminal 107 may also be formed when fabricating a probe sheet in other probe sheet fabrication methods.
With reference to FIGS. 13A–13F, an example of a method for fabricating the dummy terminal will be described below.
First, the step shown in FIG. 13A is performed. In this step, a silicon dioxide film 81, about 0.5 μm in thickness, is formed on both sides of the silicon wafer 80, which is 0.2 mm–0.6 mm in thickness, through thermal oxidation. The silicon dioxide film 81 is removed by etching with a mixture of hydrofluoric acid and ammonium fluoride using a photo-resist mask 85 b as the mask.
Next, the step shown in FIG. 13D is performed. In this step, the conductive coating 83 a exposed in the opening of the polyimide film 84 a is electroplated, with the conductive coating 83 a as the electrode and with materials with high degree of hardness as its major component, to form the contact terminal 4 a and the connection electrode part 4 b as a unit. The conductive coating 83 a is sequentially electroplated with materials with high degree of hardness, for example, nickel 8 a, rhodium 8 b, and nickel 8 c, to form a contact terminal part 8 that includes both the contact terminal 4 a and the connection electrode part 4 b.
Next, after the same steps as those in FIGS. 10D–10G and FIGS. 11A–11D, a probe sheet structure 105 shown in FIG. 13E is fabricated.
Next, with reference to FIGS. 15A–15D, a probe sheet (structure) in a fourth embodiment, its structure, and its fabrication steps will be described.
The fabrication method of this probe sheet is similar to the fabrication method of a probe sheet described in FIGS. 10A–10G and FIGS. 11A–11D except only in the way the elastic resin is formed in an area where the contact terminal part 8 is formed.
FIG. 15A shows the status in which, after the steps in FIGS. 10A–10F are executed, the adhesion layer 89 of the area where the contact terminal part 8 is formed and the part of the polyimide film 84 not covered by the wiring material 88 are removed by a laser. After that, the step shown in FIG. 15B is performed in which an elastic resin 93 a is printed or is formed by a dispenser. After that, as shown in FIG. 15C, an elastic resin layer is formed such that an elastic resin layer 93 b remains in the area where the contact terminal part 8 is formed. An unnecessary elastic resin layer can be removed by a laser, for example, using an aluminum mask 93 c.
Next, after the same steps as those in FIGS. 11A–11D, the step shown in FIG. 15D is performed. In this step, the polyimide film 84, adhesion layer 89, and adhesive bond 96 b, which are combined into one unit running along the peripheral part of the probe sheet frame 5, are cut into a probe sheet structure.
FIGS. 16A–16C shows the structure and the fabrication steps of a probe sheet (structure) in a fifth embodiment of the present invention.
The fabrication method of this probe sheet is that, after the same steps as those shown in FIGS. 10A–10F, the step in FIG. 10G is not executed in which the elastomer 93 is formed in the area where the contact terminal part 8 is formed; instead, the steps shown in FIGS. 11A–11D are executed to fabricate a probe sheet structure in the state shown in FIG. 16A. After that, as shown in FIG. 16B, the adhesion layer 89 of the area where the contact terminal part 8 is formed and the part of the polyimide film 84 not covered by the wiring material 88 are removed by a laser. As a result, the contact terminal 4 a is formed as a structure supported by both the wiring material 88 and the polyimide film 84.
FIG. 16C is a plan view, as viewed from the bottom of the probe sheet in FIG. 16B, showing a part of the area shown in FIG. 16B where the contact terminal part 8 is formed. Cutting off both sides of the contact terminal part 8 as shown in the figure allows the ‘follow-mechanism’ to be prepared for each contact terminal part 8.
The fabrication method of this probe sheet is that, after the same steps as those shown in FIGS. 10A–10F, the step in FIG. 10G is not executed in which the elastomer 93 is formed in the area where the contact terminal part 8 is formed; instead, the steps shown in FIGS. 11A–11D are executed to fabricate a probe sheet structure in the state shown in FIG. 17A. After that, as shown in FIG. 17B, the adhesion layer 89 of the area where the contact terminal part 8 is formed and the part of the polyimide film 84 not covered by the wiring material 88 are removed by a laser. As a result, the contact terminal 4 a is formed as a structure supported by both the wiring material 88 and the polyimide film 84. FIG. 17C is a plan view, as viewed from the bottom of the probe sheet in FIG. 17B, showing a part of the area shown in FIG. 16B where the contact terminal part 8 is formed. Separating the contact terminal part 8 as shown in the figure allows each ‘follow-mechanism’ to move more easily than that in the fifth embodiment described above.
When a bonding wire is used as a lead line as shown in FIG. 6 or FIG. 8, the wiring may be wire bonded to the electrode 92. Instead, as shown in FIGS. 18A–18C, a plating layer 88 a suitable for wire bonding may be formed on the wiring material to allow a wire to be wire bonded to the plating layer 88 a to form a lead wire.
FIG. 18A shows a step in which a photo-resist mask 91 a is formed on the metallic film 90 by the same steps as those in FIGS. 10A–10E. FIG. 18B shows a step in which a plating layer 88 a for wire bonding is formed on the surface of the wiring material 88, with the etched metallic film 90 as the mask, by removing the adhesion layer 89 with a laser until the wiring material 88 is reached. The plating layer 88 a is, for example, a nickel-plated plating layer that is gold plated. After that, the steps in FIG. 10F and FIGS. 11A–11D are executed to fabricate the probe sheet structure shown in FIG. 18C.
Above the stage 162 is provided the probe system 120. That is, the probe card 120 and the multi-layer wiring substrate 50 shown in FIG. 2 are opposed to the stage 162 in parallel. Each contact terminal 4 a is connected to the electrode 50 c on the multi-layer wiring substrate 50 via the pitch extension wiring 4 c, electrode 4 d, and spring probe 12 on the probe sheet 4 on the probe card 120 and via the electrode 50 a and the internal wiring 50 b on the multi-layer wiring substrate 50 and is connected to the tester 170 via a cable 171 connected to the electrode 50 c.
To prevent a positional misalignment caused by a difference in temperature between the wafer heated by a heater to a desired temperature and the probe sheet on which the contact terminals, connected to the electrodes on the wafer for electrical signal testing, are formed and to adjust the alignment precisely and quickly, a temperature-controllable heating element may be formed in advance on the surface, or in the inside, of the probe sheet or the probe card. The heating element may be created, for example, by forming a high-resistance metallic material, such as Ni—Cr, or a high-resistance conductive resin directly on the probe sheet or the multi-layer wiring substrate layer or by inserting a sheet, on which the material is formed, into the probe sheet or pasting the sheet on the probe card. In addition, heated liquid may be poured into the tube in the heat block, which is then brought into contact with the probe card for use as the heating element.
The operation of the semiconductor test equipment will be described below. First, the semiconductor wafer 1 to be tested is positioned and mounted on the stage 162, and the X-Y stage 167 and the turning mechanism are driven to position the electrodes 3, formed on a plurality of semiconductor devices arranged on the semiconductor wafer 1, right below many contact terminals 4 arranged on the probe card 120. After that, the drive control system 150 activates the elevation drive unit 165 to elevate the stage 162 until the whole surface of many electrodes (contact target) 3 is brought up about 60 μm above the point at which it gets into contact with the tips of the contact terminals. This pushes out the region 4 a, where many contact terminals 4 are arranged in the multi-layer film 6, and moves, in parallel, the precisely flattened tips of the many contact terminals 4 with the use of the compliance mechanism (pressure mechanism) so that the tips follow the surface of many electrodes 3 (whole) arranged on the semiconductor device. As a result, the contact terminals are pushed under an even load (about 3–150 mN per pin) so that the contact terminals follow the contact target (electrodes) 3 arranged on the semiconductor wafer 1, and the contact terminals 4 and the electrodes 3 are connected under a low resistance (0.01Ω–0.1Ω).
The wafer holder is rotated, 90° at a time, to sequentially test simultaneous test chips 200 a, 200 b, 200 c, and 200 d as shown in FIG. 20. The whole wafer is tested in four 90° rotations. This allows all chips to be tested in the minimum touchdown count, thus increasing test efficiency. It is easily understood that the rotation may be made any angles other than 90°.
Referring to FIGS. 22A–22B to FIGS. 25A–25B, the features and effects of the semiconductor device itself will be described more in detail.
FIGS. 22A–22B show the top view of the trace of an indentation (probing indentation) left on an electrode pad during a test process. In FIGS. 22A–22B, for easy comparison between an indentation 300 left by a conventional cantilever probe and an indentation 301 left by contact terminals disclosed in this application, both indentations are combined and shown side by side on the same electrode. Of course, the scaling is not changed.
That is, the surface of the electrode pad of a semiconductor device tested using a conventional probe becomes rough and, as a result, a connection problem may develop in the bonding/mounting process (wire bonding, gold bump connection, solder bump connection, Au—Sn connection, and so on) that is performed after the test process.
This problem will be described more in detail with reference to FIGS. 24A–24B. FIG. 24A is a general cross section diagram showing an electrode pad 3 exposed from a protective film 510 after a test using a conventional prober. Because the scrub operation was executed, the electrode surface is rough and electrode waste 502 is present. Because the surface was scrubbed under a heavy load, a part of an aluminum layer 500 becomes extremely thin or is chipped off with the result that a part of a base film 501 (for example, SiO2) is exposed.
This is described more in detail with reference to FIGS. 25A–25B. Because, the pyramid-shaped or truncated-pyramid-shaped contact terminal leaves a small indentation 301 on, and applies a low load to, the electrode pad 3 tested using the contact terminal disclosed in this application, the electrode pad 3 remains in good state in which no part of the base film 501 is exposed.
Although examples of an electrode pad and a gold wire bond whose top layer is aluminum are shown in FIGS. 24A–24B and FIGS. 25A–25B, the material may be changed. The same effect may be achieved not only in the wire bonding process but also in other bonding/mounting processes.
(2) A probe sheet comprising contact terminals arranged according to an array of peripheral electrodes of semiconductor devices formed on a wafer; wires drawn from the contact terminals; and electrode pads electrically connected to the wires, wherein the electrode pads are arranged in a grid pattern.
(3) A probe sheet comprising contact terminals that get into contact with electrodes provided on a wafer; wires drawn from the contact terminals; and electrode pads electrically connected to the wires, wherein the probe sheet is provided with a metallic sheet from which at least a part corresponding to signal electrode pads of the electrode pads is removed.
(4) The probe sheet as described in (3) wherein the linear expansion coefficient of the metallic sheet is almost equal to the linear expansion coefficient of the wafer.
(5) The probe sheet as described in (3) or (4) wherein the metallic sheet is a 42 alloy sheet.
(6) The probe sheet as described in one of (1)–(5) wherein dummy terminals, each of which has a larger contact area with the wafer than the contact terminal, are provided on a surface on which the contact terminals are provided.
(7) The probe sheet as described in one of (1)–(6) wherein the contact terminals are created each by using an anisotropically etched hole in a crystalline substrate as a cast.
(8) A probe card comprising a probe sheet having contact terminals that get into contact with electrodes provided on a wafer; and a multi-layer wiring substrate on which electrodes, which are electrically connected to the contact terminals, are provided on a surface opposed to the wafer, wherein a pitch of the electrodes provided on the surface of the multi-layer wiring substrate opposed to the wafer is wider than a pitch of the contact terminals.
(9) A probe card comprising a probe sheet on which contact terminals arranged according to an array of peripheral electrodes of semiconductor devices formed on a wafer; and a multi-layer wiring substrate having electrodes provided on a surface opposed to the wafer, the electrodes being electrically connected to the contact terminals, wherein the electrodes provided on the surface of the multi-layer wiring substrate opposed to the wafer are arranged in a grid pattern.
(10) A probe card comprising contact terminals that get in contact with electrodes provided on a wafer; and a multi-layer wiring substrate having electrodes electrically connected to the contact terminals, wherein the electrodes of the multi-layer wiring substrate are provided in a device-opposed-area on the multi-layer wiring substrate and a pitch of the electrodes is wider than a pitch of the contact terminals.
(11) A probe card as described in one of (8) to (10) wherein at least one of capacitors, resistors, or fuses are mounted in the device-opposed area on the multi-layer wiring substrate.
(12) A probe card comprising a probe sheet having contact terminals that get in contact with electrodes on a wafer; and a multi-layer wiring substrate having electrodes electrically connected to the contact terminals wherein the electrodes of the contact terminals and the electrodes of the multi-layer wiring substrate are electrically connected by a connection part provided almost vertically with respect the multi-layer wiring substrate.
(13) A probe card comprising a probe sheet having contact terminals that get in contact with electrodes provided on a wafer; and a multi-layer wiring substrate having electrodes electrically connected to the contact terminals wherein a connection between the electrodes of the contact terminals and the electrodes of the multi-layer wiring substrate is made via wires drawn from the contact terminals, electrode pads connected to the wires and having a pitch wider than a pitch of the contact terminals, and spring probes electrically connected to the electrode pads.
(14) The probe card as described in (13) wherein the spring probes are removable.
(15) A probe card comprising a probe sheet having contact terminals that get in contact with electrodes provided on a wafer; and a multi-layer wiring substrate having electrodes electrically connected to the contact terminals wherein a connection between the electrodes of the contact terminals and the electrodes of the multi-layer wiring substrate is made via wirings drawn from the contact terminals, electrode pads connected to the wirings and having a pitch wider than a pitch of the contact terminals, and wires electrically connected to the electrode pads.
(16) A probe card comprising contact terminals that get in contact with electrodes provided on a wafer; and a multi-layer wiring substrate having electrodes electrically connected to the contact terminals wherein the probe card has a temperature adjustment function.
(17) A probe card comprising contact terminals that get in contact with electrodes provided on a wafer; and a multi-layer wiring substrate having electrodes electrically connected to the contact terminals wherein a heating element capable of controlling a temperature is provided at least in a part of the probe card.
(18) The probe card as described in one of (8)–(17) wherein the contact terminals are each a pyramid-shaped or truncated-pyramid-shaped terminal created with an anisotropically etched hole in a crystalline substrate as a shape former.
(19) A probe card comprising contact terminals that get in contact with electrodes provided on a wafer; and a multi-layer wiring substrate having electrodes electrically connected to the contact terminals wherein the probe card has a two-level pressure mechanism.
(20) A probe card comprising a probe sheet having contact terminals that get in contact with electrodes provided on a wafer; and a multi-layer wiring substrate having electrodes electrically connected to the contact terminals wherein the probe sheet is the probe sheet described in one of (1)–(7).
(21) Semiconductor test equipment comprising a stage on which a wafer is mounted; and a probe card having contact terminals that get in contact with electrodes of semiconductor devices formed on the wafer and electrically connected to a tester that tests electrical characteristics of the semiconductor devices wherein the probe card comprises a probe sheet having the contact terminals and a multi-layer wiring substrate whose electrodes electrically connected to the contact terminals are provided on a surface opposed to the wafer and wherein a pitch of the electrodes of the multi-layer wiring substrate provided on the surface opposed to the wafer is wider than a pitch of the contact terminals.
(22) Semiconductor test equipment comprising a stage on which a wafer is mounted; and a probe card having contact terminals that get in contact with electrodes of semiconductor devices formed on the wafer and electrically connected to a tester that tests electrical characteristics of the semiconductor devices wherein a temperature of the stage and the probe card can both be controlled.
(23) The semiconductor test equipment as described in (21) or (22) wherein the contact terminals are each a pyramid-shaped or truncated-pyramid-shaped terminal created with an anisotropically etched hole in a crystalline substrate as a shape former.
(24) The semiconductor test equipment comprising a stage on which a wafer is mounted; and a probe card having contact terminals that get in contact with electrodes provided on the wafer wherein the probe card is one of the probe cards described in (8) to (20).
(25) A semiconductor device fabrication method comprising the steps of creating circuits on a wafer to form semiconductor devices; testing electrical characteristics of the semiconductor devices; and dicing the wafer into semiconductor devices wherein, in the step of testing electrical characteristics of the semiconductor devices, a plurality of semiconductor devices are tested at a time using a probe card comprising a probe sheet having contact terminals that get in contact with electrodes of the semiconductor devices and a multi-layer wiring substrate electrically connected to the contact terminals and having electrodes, whose pitch is wider than a pitch of the contact terminals, on a surface opposed to the wafer.
(26) A semiconductor device fabrication method comprising the steps of creating circuits on a wafer to form semiconductor devices; testing electrical characteristics of the semiconductor devices; and dicing the wafer into semiconductor devices wherein, in the step of testing electrical characteristics of the semiconductor devices, a plurality of semiconductor devices are tested at a time using a probe card comprising contact terminals that get in contact with electrodes provided on the wafer and a multi-layer wiring substrate electrically connected to the contact terminals, provided in an area corresponding to an upper part of the semiconductor devices formed on the wafer, and having electrodes whose pitch is wider than a pitch of the contact terminals.
(27) A semiconductor device fabrication method comprising the steps of creating circuits on a wafer to form semiconductor devices; sealing the wafer with resin; and testing electrical characteristics of the semiconductor devices formed on the sealed wafer wherein, in the step of testing electrical characteristics of the semiconductor devices, a plurality of semiconductor devices are tested at a time using a probe card comprising a probe sheet having contact terminals that get into contact with electrodes of the semiconductor devices and a multi-layer wiring substrate electrically connected to the contact terminals and having electrodes, whose pitch is wider than a pitch of the contact terminals, on a surface opposed to the wafer.
(28) A semiconductor device fabrication method comprising the steps of creating circuits on a wafer to form semiconductor devices; sealing the wafer with resin; and testing electrical characteristics of the semiconductor devices formed on the sealed wafer wherein, in the step of testing electrical characteristics of the semiconductor devices, a plurality of semiconductor devices are tested at a time using a probe card comprising contact terminals that get in contact with electrodes provided on the wafer and a multi-layer wiring substrate electrically connected to the contact terminals, provided in an area corresponding to an upper part of the semiconductor devices formed on the wafer, and having electrodes whose pitch is wider than a pitch of the contact terminals.
(29) The semiconductor device fabrication method as described in one of (25)–(28) wherein the contact terminals are each a pyramid-shaped or truncated-pyramid-shaped terminal created with an anisotropically etched hole in a crystalline substrate as a shape former. p0 (30) A semiconductor device fabrication method comprising the steps of creating circuits on a wafer to form semiconductor devices; testing electrical characteristics of the semiconductor devices; and dicing the wafer into semiconductor devices wherein, in the step of testing electrical characteristics of the semiconductor devices, the wafer is rotated for testing.
The effect achieved by the representative inventions disclosed in this application is described briefly below.
(1) A probe card is provided that can test a plurality of semiconductor devices, with a narrow-pitch electrode structure, at a time.
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U.S. Classification 324/754.07, 324/762.05
International Classification G01R31/02, G01R1/073, G01R3/00, H01L21/66, G01R1/067
Cooperative Classification H01L2924/00011, H01L2924/14, H01L2224/32245, H01L2924/15311, H01L2924/181, H01L2224/32225, H01L2224/04042, H01L2924/12042, H01L2224/45147, H01L2224/45144, G01R31/2874, G01R1/06711, G01R3/00, G01R1/0735, G01R1/06744, H01L2224/48227, H01L2224/48463, H01L2224/48465, H01L2224/73265, H01L2224/48247, H01L24/05, H01L2224/48453, H01L2224/48091
European Classification G01R1/073B6, G01R1/067C3B
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KASUKABE, SUSUMU;HASEBE, TAKEHIKO;NARIZUKA, YASUNORI;ANDOTHERS;REEL/FRAME:014572/0903;SIGNING DATES FROM 20030911 TO 20030916