Source: http://www.google.com/patents/US7984203?ie=ISO-8859-1&dq=7222078
Timestamp: 2014-03-09 04:58:58
Document Index: 734460280

Matched Legal Cases: ['Application No. 0722953', 'Application No. 200680022186', 'Application No. 10', 'Application No. 11', 'Application No. 11', 'Application No. 10', 'Application No. 200680022186']

Patent US7984203 - Address window support for direct memory access translation - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn apparatus is disclosed. The apparatus includes a remapping circuit to facilitate access of one or more I/O devices to a memory device for direct memory access (DMA) transactions. The remapping circuit of the apparatus includes a translation mechanism to perform memory address translations for I/O...http://www.google.com/patents/US7984203?utm_source=gb-gplus-sharePatent US7984203 - Address window support for direct memory access translationAdvanced Patent SearchPublication numberUS7984203 B2Publication typeGrantApplication numberUS 12/648,461Publication dateJul 19, 2011Filing dateDec 29, 2009Priority dateJun 21, 2005Also published asCN101203838A, CN101203838B, DE112006001642T5, US20060288130, US20100100648, WO2007002425A1Publication number12648461, 648461, US 7984203 B2, US 7984203B2, US-B2-7984203, US7984203 B2, US7984203B2InventorsRajesh Madukkarumukumana, Udo A. Steinburg, Steven M. Bennett, Andrew V. Anderson, Gilbert NeigerOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (57), Non-Patent Citations (16), Classifications (8), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetAddress window support for direct memory access translationUS 7984203 B2Abstract An apparatus is disclosed. The apparatus includes a remapping circuit to facilitate access of one or more I/O devices to a memory device for direct memory access (DMA) transactions. The remapping circuit of the apparatus includes a translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations.
This application is a continuation of U.S. patent application Ser. No. 11/157,675 filed Jun. 21, 2005 now abondoned entitled �Address Window Support for Direct Memory Access Translation.�
FIELD OF THE INVENTION The present invention relates generally to microprocessors, more specifically, the present invention relates to input/output (I/O) virtualization.
BACKGROUND As microprocessor architecture becomes more and more complex to support high performance applications, I/O management presents a challenge. Existing techniques to address the problem of I/O management have a number of disadvantages. One technique uses software-only I/O virtualization to support virtual machine (VM) I/O. This technique has limited functionality, performance, and robustness.
DETAILED DESCRIPTION A Direct Memory Access (DMA) translation architecture implementing address window based translation is described. Reference in the specification to �one embodiment� or �an embodiment� means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase �in one embodiment� in various places in the specification are not necessarily all referring to the same embodiment.
Elements of one embodiment of the invention may be implemented by hardware, firmware, software or any combination thereof. The term hardware generally refers to an element having a physical structure such as electronic, electromagnetic, optical, electro-optical, mechanical, electro-mechanical parts, etc. The term software generally refers to a logical structure, a method, a procedure, a program, a routine, a process, an algorithm, a formula, a function, an expression, etc. The term firmware generally refers to a logical structure, a method, a procedure, a program, a routine, a process, an algorithm, a formula, a function, an expression, etc that is implemented or embodied in a hardware structure (e.g., flash memory, read only memory, erasable read only memory). Examples of firmware may include microcode, writable control store, micro-programmed structure. When implemented in software or firmware, the elements of an embodiment of the present invention are essentially the code segments to perform the necessary tasks. The software/firmware may include the actual code to carry out the operations described in one embodiment of the invention, or code that emulates or simulates the operations. The program or code segments can be stored in a processor or machine accessible medium or transmitted by a computer data signal embodied in a carrier wave, or a signal modulated by a carrier, over a transmission medium. The �processor readable or accessible medium� or �machine readable or accessible medium� may include any medium that can store, transmit, or transfer information. Examples of the processor readable or machine accessible medium include an electronic circuit, a semiconductor memory device, a read only memory (ROM), a flash memory, an erasable ROM (EROM), a floppy diskette, a compact disk (CD) ROM, an optical disk, a hard disk, a fiber optic medium, a radio frequency (RF) link, etc. The computer data signal may include any signal that can propagate over a transmission medium such as electronic network channels, optical fibers, air, electromagnetic, RF links, etc. The code segments may be downloaded via computer networks such as the Internet, intranet, etc. The machine accessible medium may be embodied in an article of manufacture. The machine accessible medium may include data that, when accessed by a machine, cause the machine to perform the operations described in the following. The machine accessible medium may also include program code embedded therein. The program code may include machine readable code to perform the operations described in the following. The term �data� here refers to any type of information that is encoded for machine-readable purposes. Therefore, it may include program, code, data, file, etc.
For assigning I/O devices to domains, physical-address translation and protection are applied for DMA requests from all I/O devices in the platform. For simplicity, the physical address translation functionality for I/O device DMA requests is referred to as DMA remapping. In discussions that follow, it should be understood that the term �remapping� also includes protection mechanisms in addition to the mapping of addresses from one address space to another (e.g., guest-physical addresses to host-physical addresses).
In a further embodiment, each AW is described by a DPA-to-HPA translation structure in memory called an Address Window page-table (AWPT). The entries in an AWPT are called AW page-table-entries (AWPTE). Each AWPTE provides the translation for a 4 KB region (referred as a slot) within the AW. Thus, there are 512 slots in an AW, and the AWPT associated with each AW is 4 KB in size (with 512 AWPTEs). According to one embodiment, AWPTEs are 64-bits in size and have the format illustrated in FIG. 6. In one embodiment, an AWPTE includes access control bits such as bits (�read� and �write�) specifying if read accesses and/or write accesses are allowed to the DPA used to access the AWPTE. In one embodiment, the address field (�ADDR�) specifies the mapping of a subset of the bits in the DPA to HPA. In one embodiment, the remaining bits (e.g., bits [11:0]) may be passed unmodified from the DPA to the HPA. Many other configurations are possible and do not limit the scope of the invention.
Further, in an embodiment, each entry in the AWPTR table includes Valid, Tag and Data fields. The Valid field indicates whether an entry is valid. In another embodiment, there is no valid bit and the remapping circuit 135 treats all AWPTR table entries as being valid. The Tag field indicates the particular device ID to which the entry is associated. For example, in FIG. 8 software has bound AW 4 to an I/O device with device ID 11 and AW 6 to an I/O device with device ID 18. In one embodiment, identification of a device originating an access (e.g., determination of device ID) may include information on the bus, device and function within the device. The originator of a DMA request is referred to herein as a �device� or �requesting I/O device� and is identified by a �device ID�. However, it should be understood that in other embodiments a single physical device may be identified by one or more device-IDs.
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