Source: http://www.google.com/patents/US6574289?ie=ISO-8859-1&dq=5,581,513
Timestamp: 2014-11-26 12:55:09
Document Index: 398818432

Matched Legal Cases: ['art 278', 'art 280', 'art 3000', 'art 3000', 'art 3000', 'art 4000', 'art 4000', 'art 4000', 'art 4000', 'art 4000']

Patent US6574289 - Method for determining frame rate of a data frame in a communication system ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method of determining a frame rate of a data frame in a communication system by using apriori knowledge of data frame. In one embodiment, a signal is received at the communication device. Then a data frame portion of the signal is isolated. Next, a potential frame rate is chosen and the data frame...http://www.google.com/patents/US6574289?utm_source=gb-gplus-sharePatent US6574289 - Method for determining frame rate of a data frame in a communication system by using apriori knowledge of data frameAdvanced Patent SearchPublication numberUS6574289 B1Publication typeGrantApplication numberUS 09/427,502Publication dateJun 3, 2003Filing dateOct 26, 1999Priority dateOct 26, 1999Fee statusPaidAlso published asDE60035099D1, DE60035099T2, EP1142238A1, EP1142238B1, WO2001031864A1, WO2001031864A9Publication number09427502, 427502, US 6574289 B1, US 6574289B1, US-B1-6574289, US6574289 B1, US6574289B1InventorsHau (Howard) Thien Tran, Jyoti SetlurOriginal AssigneeKoninklijke Philips Electronics N.V.Export CitationBiBTeX, EndNote, RefManPatent Citations (5), Non-Patent Citations (4), Referenced by (6), Classifications (16), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetMethod for determining frame rate of a data frame in a communication system by using apriori knowledge of data frameUS 6574289 B1Abstract A method of determining a frame rate of a data frame in a communication system by using apriori knowledge of data frame. In one embodiment, a signal is received at the communication device. Then a data frame portion of the signal is isolated. Next, a potential frame rate is chosen and the data frame is formatted accordingly. Decoding, at the chosen potential frame rate, occurs on the data frame. Then, a tail bit portion of the data frame is isolated. Afterward, a logic level of the decoded tail bit data is compared against the apriori knowledge of a transmitted logic level for the tail bit portion of the data frame. In addition, comparisons are also made between other data metrics and their expected values. Finally, a level of confidence is communicated to the communication device based upon a result of the comparisons.
d1) calculate an �expected 0� branch metric for every state of a given time stage; d2) sum said expected 0 branch metrics obtained from step d1); d3) calculate an �expected 1� branch metric for every state of a given time stage; d4) sum said expected 1 branch metrics obtained from step d3); d5) calculate a delta, said delta equal to a difference between said sum obtained from step d2) and said sum obtained from step d4); d6) repeat step d1) through d5) for every time stage in a tail bit portion of said data frame; and d7) sum said deltas obtained from step d6) to obtain a deltasum. 27. The method recited in claim 26 wherein said step e) comprises the step of:
d1) calculate an �expected 0� branch metric for every state of a given time stage; d2) sum said expected 0 branch metrics obtained from step d1); d3) calculate an �expected 1� branch metric for every state of a given time stage; d4) sum said expected 1 branch metrics obtained from step d3); d5) calculate a delta, said delta equal to a difference between said sum obtained from step d2) and said sum obtained from step d4); d6) repeat step d1) through d5) for every time stage in a tail bit portion of said data frame; and d7) sum said deltas obtained from step d6) to obtain a deltasum. 44. The communication device recited in claim 43 wherein said step e) comprises the step of:
TECHNICAL FIELD The present claimed invention relates to the field of digital communication. Specifically, the present claimed invention relates to an apparatus and a method for determining frame rate of a data frame in a communication system by using apriori knowledge of the data in a frame.
BACKGROUND ART Wireless telephony, e.g. cellular phone use, is a widely-used mode of communication today. Variable rate communication systems, such as Code Division Multiple Access (CDMA) spread spectrum systems, are among the most commonly deployed wireless technology. Because of increasing demand and limited resources, a need arises to improve their fidelity and performance.
DISCLOSURE OF THE INVENTION The present invention provides a method and apparatus for improving the fidelity and performance of digital communication. In particular, the present invention provides a method and apparatus for determining the frame rate of a data frame in a variable rate communication system. More specifically, the present invention determines the frame rate using new methods, or algorithms. Additionally, the method and apparatus of the present invention is easy to implement and is conducive to use with existing variable rate communication systems. Lastly, the present invention provides some methods of determining a frame rate of a data frame that require only minor modifications to the communication device hardware.
Specifically, the present invention utilizes apriori knowledge of a logic level for a portion of a data frame to determine the frame rate of the data frame. One embodiment utilizes the fact that, for convolutionally encoded data that uses tail bits, each data frame uses a tail bit portion to reset the shift registers used for encoding the data frame. The tail bit portion of the data frame is established as having eight bits with a low logic level, e.g. �0,� for the case of constraint length K=9, for a convolutional encoder, though other constraint lengths are possible. However, with different frame rates in a variable rate communication system, the last eight bits span different amounts of time. This provides a useful discriminator between the different possible frame rates as applied to an actual data frame. This information generates, in one embodiment, a method to enhance the level of reliability in determining a frame rate for a data frame. In particular, if a correlation result between a received data signal and its apriori-established transmitted data signal exceeds a threshold value, then a good level of confidence can be established that the assumed frame rate is probably correct.
In one embodiment, the apriori knowledge that the tail bits have a logic zero level can be used to evaluate the frame rate in a different manner. In this embodiment, performance of the Viterbi decoder is used to determine the frame rate of the data frame. Specifically, if the chosen frame rate implemented by a Viterbi decoder yields a state change, in an apriori-established direction or sequence, for the last eight bits of the data frame, for at least one possible path in the trellis diagram evaluation, then a good level of confidence exists that the frame rate implemented is the true frame rate of the data frame. In addition, a branch metric is calculated for an expected input of 0 and an expected input of 1 for every state. The �expected 0� branch metrics are summed together for all states of a given time stage in the tail-bit portion of the trellis diagram. Similarly, the �expected 1� branch metrics are also summed together for all states of a given time stage. A delta is then calculated from the difference between the summed expected 1 branch metric and the summed expected 0 branch metric for each given time stage. Next, the deltas for all time stages in the tail bit portion are summed to obtain a deltasum. If the deltasum is a large positive value, then a good level of confidence exists that the frame rate utilized by the Viterbi decoder is the correct one. If the deltasum is a smaller number, then a lower level of confidence exists that the frame rate utilized by the Viterbi decoder is the correct one. The branch metric deltas for the tail bits, provided by the symbol detector portion of the Viterbi decoder, provide a soft decision about the frame rate. In the present embodiment, a lower metric, and hence a larger deltasum, is established as representing a higher level of confidence. However, the present invention is well-suited to an alternative embodiment where a higher metric, and hence a smaller deltasum, is established as representing a higher level of confidence.
In another embodiment, the normal �hard decision� decoded tail bit outputs of the Viterbi Decoder are used along with �soft decisions� that arise from the branch metric deltas for the tail bits described in the previous embodiment. The hard decision decoded tail bit outputs are provided by a traceback operation implemented by the sequence detector portion of the Viterbi decoder. Hence, the present embodiment utilizes both the traceback operation and the symbol detector portion of the Viterbi decoder. Consequently, a more reliable soft output is obtained, thereby enhancing the reliability of the frame rate determination process.
It should be borne in mind, however, that all of these terms are to be interpreted as referencing physical manipulations and quantities and are merely convenient labels to be interpreted further in view of terms commonly used in the art. Unless specifically stated otherwise as apparent from the following discussions, it is understood that throughout discussions of the present invention, terms such as �receiving,� �selecting,� �choosing,� �sampling,� �comparing,� �indicating,� �repeating,� �ecoding,� �determining,� �providing,� or the like, refer to the action and processes of a communication device or a similar electronic computing device, that manipulates and transforms data. The data is represented as physical (electronic) quantities within the communication devices components, or the computer system's registers and memories, and is transformed into other data similarly represented as physical quantities within the communication device components, or computer system memories or registers, or other such information storage, transmission or display devices.
Referring now to FIG. 2A, a hypothetical data frame used in a communication system is shown, in accordance with one embodiment of the present invention. FIG. 2A shows an abscissa of time 204, over which bits of information may be separated, and an ordinate of amplitude 202, for representing logic levels, e.g. high and low, of data. In general, transmitted and received signals in a digital communication system are segregated into data frames, comprised of a specific length of binary digits, or bits. For example, FIG. 2A shows an exemplary data frame 206 a, which is followed by subsequent data frames, e.g. 206 b. Data frame 206 a in the present embodiment includes a data portion 208, which can include system information as a header, and a tail bit portion 210. The data frame shown in FIG. 2A is the unencoded data bit configuration of the frame. It is appreciated that the data frame shown can also exist in an encoded symbol domain, for transmission. Noteworthy is the fact that the tail bits of the unencoded data all have a low logic level, e.g. �0.� While the present embodiment utilizes low logic levels for tail bits, the present invention is well-suited to other logic levels, e.g. �1,� assuming the level is inverted as appropriate for coding and decoding operations. The data portion 208 of the data frame 206 a typically includes low logic levels and high logic levels that represent data values. In lieu of using �+1� and �0� for logic levels, the present invention is well-suited to using logic levels of �+1� and �−1� for transmitting data signals and tail bit signals. In this latter embodiment, the test conditions would appropriately change for the new logic levels.
Referring now to FIG. 2B, a block diagram of a composition of data frames at different frame rates is shown, in accordance with one embodiment of the present invention. The data frames are shown together in FIG. 2B only to allow simultaneous comparison. Similar to the previous figure, present FIG. 2B shows an abscissa of time 204, over which bits of information are separated, and an ordinate of amplitude 202, for representing logic levels of data. However, for clarity, the amplitude of individual data bits for each data frame in FIG. 2B is not shown. Ordinate of FIG. 2B shows a first data frame 226 a that has a full-rate frame rate �A� 220 a, a second data frame 226 b that has a half-rate frame rate �B� 220 b, a third data frame 226 c that has a quarter-rate frame rate �C� 220 c, and a fourth data frame 226 d that has an eighth-rate frame rate �D� 220 d. While the present embodiment shows four different frame rates, the present invention is well-suited to having any quantity and any value of frame rates. In the present embodiment, the four frame rates provided actually correspond to frame rates used in Code Division Multiple Access (CDMA) variable rate system. In one embodiment, a full-rate can be defined as 400 bits/20 millisecond (msec) for rate A, a half-rate can be defined as 200 bits/20 msec for rate B, a quarter-rate can be defined as 100 bits/20 msec, and an eighth-rate can be defined as 50 bits/20 msec. Again, while the present embodiment shows four specific frame rates, the present invention is well-suited to having any value for the frame rates. For example, the present invention is well-suited to using the actual CDMA data rates.
Still referring to FIG. 2B, the differences in the frame rates for each data frame are manifested in the length of the tail bit portions of each data frame. The difference in the time length, shown on time scale 204, of the tail bits, e.g. 222 a-222 d, arises because, regardless of the frame rate, the length of the tail bit always consumes the last eight bits of the data frame, for a constraint length K=9 convolutional code. Thus, for example, at full-rate, the last eight bits, e.g. tail 222 a, consume 0.4 msec, e.g. 8 bits�(20 msec/400 bits). Similarly, at half-rate, the last eight bits, e.g. tail 222 b, consume 0.8 msec. At quarter-rate, the last eight bits, e.g. tail 222 c, consume 1.6 msec, and at eighth-rate, the last eight bits, e.g. tail 222 d, consume 3.2 msec. This phenomenon is applicable to any rate, besides those used in the present embodiment. Furthermore, the present embodiment uses tail bits having a low logic level, e.g. �0,� although an alternative logic level may be used.
Referring now to FIG. 2D, an abbreviated trellis diagram, used to provide frame rate determination of a data frame, is shown, in accordance with one embodiment of the present invention. Trellis diagram 200 d is abbreviated, for clarity, to show only two states, state �a� 294 and state �d� 296. However, many other states can exist therein. Trellis diagram 200 d is divided into two parts over time, in this figure. The first part 278 of the trellis diagram 200d represents states, and state changes, for the data portion of the data frame. In contrast, the second part 280 of trellis diagram 200 d represents states, and state changes, for the tail bit portion of the data frame. Each row of points represents a possible state of the encoder. Hence, the ordinate 270 of trellis diagram 200 d can represent states. Similarly, each column of points represents a stage, or a point in time where a new bit of data is received. Hence, the abscissa 272 of trellis diagram 200 d can represent time, or received data bits. Trellis diagram 200 d starts at point 282, representing the zero state with all shift registers of the encoder zeroed out at the start of a given data frame.
In the present embodiment, the movement towards an all-zero state occurs gradually, over all stages, within the tail bit portion 280 of trellis diagram 200 d. However, in an alternative embodiment, the movement of states for tail bits to an all-zero state can occur within a single stage and remain there until the end of the tail bit section. Alternatively, the movement of states for tail bits to an all-zero state can occur over any number of stages available in the portion of the tail bit portion 280 of trellis diagram 200 d so long as the state of the last tail bit is at the all-zero state. While the present embodiment expects states in the tail bit portion of the data frame to move to an all-zero state, because of an all zero content of tail bits, the present invention is well-suited to using alternative movements of the states in the tail-bit portion of the data frame to establish the frame rate of the data frame. For example, if the tail tails used a high logic value, e.g. �1,� instead of a low logic value, then the expected movement of states for the tail bit portion of the data frame would be towards an all 1 data state.
In step 3004 of the present embodiment, a potential frame rate is chosen and formatted. Step 3004 is implemented, in one embodiment, in FIG. 5 where formatting is shown for the different chosen frame rates. Step 3004 arises because the present embodiment utilizes a �variable-rate� communication system. Thus, the rate at which data is communicated between two devices can have any one of many possible rates. There could only be two rates in one embodiment. However, the present invention is well-suited to a communication system having any number of communication rates. Following step 3004, flowchart 3000 proceeds to step 3006.
In step 3027 of the present embodiment, an inquiry determines whether the branch metric deltas for the tail bits exceed a threshold. Step 3027 implements the following procedure. A branch metric for �expected 0� input and a branch metric for �expected 1� input is calculated and respectively summed, e.g. Equation 1.1 below, for every state of a given time stage in the tail bit portion, e.g. 280 of FIG. 2D, of the trellis diagram, e.g. 200 d. There are 256 states for a given time state with constraint length K=9. A delta, e.g. Equation 1.1 below, is then calculated from the difference between the summed expected 1 branch metric and the summed expected 0 branch metric for each time stage. In the present embodiment, a small branch metric is a good metric result. Next, the deltas for all time stages in the tail bit portion are summed to obtain a deltasum, e.g. Equation 1.2 below. While the present embodiment shows specific number of states and time stages, e.g. tail bits, the present invention is well-suited to using any number of states and time stages. In mathematical form, the equations for the present embodiment are as follows.
delta(tail bit)={Σ[Expected 1 branch metrics(states)]−Σ[Expected 0 branch metrics(states)]}; (Eqn. 1.1) for states=1 to 2K−1, where K is the constraint length.
deltasum=Σdelta(tail bits); for tail bits=1 to 8, for K=9 (Eqn. 1.2) If the deltasum is a large positive value, then flowchart 3000 proceeds to step 3028. However, if the deltasum is a smaller number, then flowchart 3000 proceeds to step 3029.
In step 4004 of the present embodiment, a potential frame rate is chosen and formatted. Step 4004 is implemented, in one embodiment, in FIG. 5 where formatting is shown for the different chosen frame rates. Step 4004 arises because the present embodiment utilizes a �variable-rate� communication system. Thus, the rate at which data is communicated between two devices can have any one of many possible rates. The present embodiment utilizes four possible frame rates, e.g. full rate A 220 a, half-rate B 220 b, quarter-rate C 220 c, and eighth-rate D 220 d, as shown in FIG. 2B. However, the present invention is well-suited to a communication system having any number of communication rates. Step 4006 is implemented, in one embodiment, by the communication device in FIG. 2C. A potential frame rate can be chosen from those stored in memory 258 of communication device 200 c, and communicated to baseband processor 260 for evaluation of the data frame portion of the signal. FIG. 5 provides several cases of one embodiment that implements step 4002. Following step 4004, flowchart 4000 proceeds to step 4006.
In step 4006 of the present embodiment, a data frame is decoded by the Viterbi decoder at the chosen potential frame rate. Step 4006 is implemented, in one embodiment, by the communication device 200 c in FIG. 2C. Specifically, Viterbi decoder 262 of communication device 200 c is adapted to decode a data frame. It is appreciated that the construction and operation of the Viterbi decoder 262 is well known in the art. It is further appreciated that a Viterbi decoder typically provides the following outputs. First, a �symbol detector� portion of the Viterbi decoder outputs eight branch metric deltas, e.g. �soft decision outputs,� at the end of the received data frame. These branch metric deltas correspond to the eight tail bit output 4006a of flowchart 4000. In parallel, a �sequence detector� portion of the Viterbi decoder outputs the decoded bits of the data frame. The present embodiment utilizes the decoded bits corresponding to the eight tail bits, e.g. the �hard decision outputs,� 4006 b of flowchart 4000. These outputs are utilized in subsequent steps of flowchart 4000. Following step 4006, flowchart 4000 proceeds to step 4008.
Step 4008 of the present embodiment comprises the following sub-steps. First, the hard and soft decision outputs obtained from step 4006 are respectively combined together to obtain eight �soft symbols.� The hard and soft decisions may be combined in a wide variety of ways, adaptable to a given preference. The soft symbol outputs are reliable because they arise from a combination of apriori knowledge, e.g. the branch metric deltas, and the actual decoding process, e.g. the decoded tail bits.
The second sub-step of step 4008 matches the eight soft symbols to apriori-established logic levels of tail bits. The present embodiment accomplishes this portion of step 4008 by determining the correlation of each of the eight soft symbols with each respective expected value of the tail bit. Thus, a �correlation result� is obtained. The final sub-step compares the correlation result with a threshold value, for the currently chosen frame rate, that was determined from the apriori-established level of the tail bits. Consequently, a �comparison result� is obtained. In one embodiment, the threshold value is different for different available frame rates. In the present embodiment, the amount by which the correlation result falls below the threshold values, corresponds to an increasing level of confidence that the frame rate utilized for encoding is the frame rate used for transmitting the data. The comparison result obtained from step 4008 can be stored in memory for subsequent referencing. FIG. 5 provides one embodiment that implements step 4008. Following step 4008, flowchart proceeds to step 4010.
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E81-B, No. 7, Jul. 1, 1998, pp. 1365-1372, XP000790169 ISSN: 0916-8516 abstract p. 1367, paragraph 3�p. 1368, paragraph 1.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7046719 *Mar 8, 2001May 16, 2006Motorola, Inc.Soft handoff between cellular systems employing different encoding ratesUS7167502 *Nov 22, 2000Jan 23, 2007Skyworks Solutions, Inc.Zero-overhead symbol rate adaptation system for OVSF codeUS7395492 *Sep 13, 2004Jul 1, 2008Lucent Technologies Inc.Method and apparatus for detecting a packet error in a wireless communications system with minimum overhead using tail bits in turbo codeUS7447281 *Aug 24, 2004Nov 4, 2008Nxp B.V.Method for the improved recognition of the validity of IEEE 802.11a signals, and circuit arrangement for performing the methodUS8665970Apr 29, 2011Mar 4, 2014Telefonaktiebolaget Lm Ericsson (Publ)Method and arrangement related to blind detectionWO2012118419A1 *Apr 29, 2011Sep 7, 2012Telefonaktiebolaget L M Ericsson (Publ)Method and arrangement related to blind detection* Cited by examinerClassifications U.S. Classification375/341, 375/368, 375/225, 375/287, 375/228, 375/262International ClassificationH04L1/00, H04L29/08, H04L1/08, H04L25/02Cooperative ClassificationH04L1/08, H04L25/0262, H04L1/0046European ClassificationH04L1/08, H04L25/02J, H04L1/00B5BLegal EventsDateCodeEventDescriptionApr 9, 2014ASAssignmentEffective date: 20131215Owner name: BREAKWATERS INNOVATIONS LLC, VIRGINIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NXP B.V.;REEL/FRAME:032642/0564Sep 24, 2012ASAssignmentFree format text: CHANGE OF NAME;ASSIGNOR:PHILIPS SEMICONDUCTORS VLSI INC.;REEL/FRAME:029033/0062Owner name: PHILIPS SEMICONDUCTORS INC., NEW YORKEffective date: 19991220Owner name: PHILIPS SEMICONDUCTORS VLSI INC., NEW YORKFree format text: CHANGE OF NAME;ASSIGNOR:VLSI TECHNOLOGY, INC.;REEL/FRAME:029014/0745Effective date: 19990702Oct 29, 2010FPAYFee paymentYear of fee payment: 8Dec 15, 2006ASAssignmentOwner name: NXP B.V., NETHERLANDSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KONINKLIJKE PHILIPS ELECTRONICS N.V.;REEL/FRAME:018635/0787Effective date: 20061117Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KONINKLIJKE PHILIPS ELECTRONICS N.V.;U.S. PHILIPS CORPORATION;U.S. PHILIPS CORPORATION;AND OTHERS;REEL/FRAME:018635/0755;SIGNING DATES FROM 20061117 TO 20061127Nov 21, 2006FPAYFee paymentYear of fee payment: 4Apr 18, 2003ASAssignmentOwner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., NETHERLANDSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PHILIPS SEMICONDUCTORS, INC.;REEL/FRAME:013970/0122Effective date: 20030411Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V. 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