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Patent US7847344 - Memory utilizing oxide-nitride nanolaminates - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsStructures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate...http://www.google.com/patents/US7847344?utm_source=gb-gplus-sharePatent US7847344 - Memory utilizing oxide-nitride nanolaminatesAdvanced Patent SearchPublication numberUS7847344 B2Publication typeGrantApplication numberUS 10/190,689Publication dateDec 7, 2010Filing dateJul 8, 2002Priority dateJul 8, 2002Fee statusPaidAlso published asUS7489545, US7494873, US20040004247, US20050023574, US20060258097, US20060261376Publication number10190689, 190689, US 7847344 B2, US 7847344B2, US-B2-7847344, US7847344 B2, US7847344B2InventorsLeonard Forbes, Kie Y. AhnOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (103), Non-Patent Citations (91), Referenced by (1), Classifications (18), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMemory utilizing oxide-nitride nanolaminatesUS 7847344 B2Abstract Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.
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