Source: http://www.google.com/patents/US20010037481?dq=5,241,671
Timestamp: 2014-08-23 18:26:29
Document Index: 360673240

Matched Legal Cases: ['art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6']

Patent US20010037481 - CRC code calculation circuit and CRC code calculation method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA CRC code calculation circuit for calculating a CRC code from byte parallel data which is variable-length data. In a CRC code calculation circuit 10 for calculating a CRC code from four-byte parallel data having a residual portion in a final stage, a four-byte parallel CRC code calculation circuit 2calculates...http://www.google.com/patents/US20010037481?utm_source=gb-gplus-sharePatent US20010037481 - CRC code calculation circuit and CRC code calculation methodAdvanced Patent SearchPublication numberUS20010037481 A1Publication typeApplicationApplication numberUS 09/816,513Publication dateNov 1, 2001Filing dateMar 23, 2001Priority dateMar 31, 2000Also published asUS6763495Publication number09816513, 816513, US 2001/0037481 A1, US 2001/037481 A1, US 20010037481 A1, US 20010037481A1, US 2001037481 A1, US 2001037481A1, US-A1-20010037481, US-A1-2001037481, US2001/0037481A1, US2001/037481A1, US20010037481 A1, US20010037481A1, US2001037481 A1, US2001037481A1InventorsMasayoshi Suzuki, Takao Inoue, Kenjiro MoriOriginal AssigneeMasayoshi Suzuki, Takao Inoue, Kenjiro MoriExport CitationBiBTeX, EndNote, RefManReferenced by (8), Classifications (8), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetCRC code calculation circuit and CRC code calculation methodUS 20010037481 A1Abstract A CRC code calculation circuit for calculating a CRC code from byte parallel data which is variable-length data. In a CRC code calculation circuit 10 for calculating a CRC code from four-byte parallel data having a residual portion in a final stage, a four-byte parallel CRC code calculation circuit 2calculates a CRC code in parallel from the four-byte parallel data except the final stage. A byte serial conversion circuit 3 converts data of the final stage into serial data. A one-byte serial CRC code calculation circuit 4 calculates a CRC code in serial from the serial data converted by the byte serial conversion circuit 3 using a calculated result of the four-byte parallel CRC code calculation circuit 2 as an initial value. Images(6) Claims(5)
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0044] An embodiment of the invention will be described in detail with reference to the accompanying drawings below. [0045] Incidentally, in the embodiment, CRC code calculation from four-byte parallel data will be described for facilitating illustration. [0046] First, a configuration will be described. [0047] As shown in FIG. 1, a CRC code calculation circuit 1 generally comprises a four-byte parallel CRC code calculation circuit 2, abyte serial conversion circuit 3, a one-byte serial CRC code calculation circuit 4, a SEL 5, and a control part 6. [0048] The four-byte parallel CRC code calculation circuit 2 is a circuit for calculating a CRC code in parallel from data (see {circle over (1)}, {circle over (2)} of FIG. 3) except for a residual portion of four-byte parallel data (see four-byte parallel data D of FIG. 3) inputted from an external circuit (omission of being shown in the drawing) based on a control timing signal (whose detail is described later) inputted from the control part 6 and latching the calculated (intermediate) result to output the result to the SEL 5 and also outputting the result to the one-byte serial CRC code calculation circuit 4. [0049] The byte serial conversion circuit 3 is a circuit for converting data (see {circle over (3)} of FIG. 3) of a residual portion of the four-byte parallel data inputted from the external circuit (omission of being shown in the drawing) into one-byte serial data based on the control timing signal inputted from the control part 6 and outputting the converted one-byte serial data to the one-byte serial CRC code calculation circuit 4. [0050] Also, when the residual portion is converted into a plurality of the one-byte serial data, the byte serial conversion circuit 3 outputs the plurality of the converted one-byte serial data to the one-byte serial CRC code calculation circuit 4 one by one sequentially. [0051] The one-byte serial CRC code calculation circuit 4 is a circuit for calculating a CRC code in serial from the calculated intermediate result (CRC code) inputted from the four-byte parallel CRC code calculation circuit 2 and the one-byte serial data inputted from the byte serial conversion circuit 3 and latching the CRC code which is the calculated result to output the result to the SEL 5. [0052] Also, when the one-byte serial data is further inputted, the one-byte serial CRC code calculation circuit 4 again calculates a CRC code from the calculated result and the inputted one-byte serial data and latches the calculated CRC code to output the code to the SEL 5. [0053] The SEL 5 is means for selecting and outputting a desired CRC code from plural CRC codes inputted. [0054] The control part 6 is means for outputting various control timing signals (various control signals described below) and performing control for calculating a CRC code from the four-byte parallel data inputted to the CRC code calculation circuit 1. [0055]FIG. 2 is a block diagram showing a CRC code calculation circuit 10. [0056] The CRC code calculation circuit 10 shown in FIG. 2 has the generally same configuration as that of the CRC code calculation circuit 1 of FIG. 1. Here, the same numeral is attached to the same configuration portion as that of the CRC code calculation circuit 1 and a description is omitted. [0057] In FIG. 2, DFFs (D-type flip-flop) 1 to 8 are means for latching the CRC code calculated by each the CRC code calculation circuit 2, 4 and outputting the latched CRC code to the SEL 5. Also, a DFF 9 is means for selecting a desired CRC code of the inputted plural CRC codes as the final calculated result to the SEL 5. [0058] The control part 6 is means for outputting various control signals described below and performing control for calculating a CRC code from the four-byte parallel data inputted to the CRC code calculation circuit 10. [0059] Next, four-byte parallel data for calculating a CRC code and various control signals (CRCEN, STROBE, STATE[n]; corresponding to the control timing signal in FIG. 1) outputted from the control part 6 will be described briefly. [0060] The four-byte parallel data is communication data in which a data frame is variable length, and is inputted to the four-byte parallel CRC code calculation circuit 2 and the byte serial conversion circuit 3. [0061] A CRCEN (CRC ENABLE) signal, which is a signal for indicating a range calculating a CRC code, is inputted to the four-byte parallel CRC code calculation circuit 2. [0062] A STROBE signal, which is a signal for indicating final stage data of the four-byte parallel data, is respectively inputted to the four-byte parallel CRC code calculation circuit 2, the byte serial conversion circuit 3, the one-byte serial CRC code calculation circuit 4, and the DFFs 8, 9. [0063] A STATE [n] signal is a signal for indicating the number n of bytes (residual portion) included in the final stage data indicated by the STROBE signal. [0064] Next, operations of the embodiment will be described. [0065] A procedure of calculating a CRC code from the four-byte parallel data will be described with reference to FIG. 3. [0066] As shown in FIG. 3, four-byte parallel data D having a frame length (1 to 10) of ten bytes consists of three stages of {circle over (1)} (1 to 4), {circle over (2)} (5 to 8) and {circle over (3)} (9 to 10). The final stage {circle over (3)} consists of a residual portion 9, 10 of two bytes and invalid data (shaded areas in FIG. 3) of two bytes. [0067] The data {circle over (1)}, {circle over (2)} of the four-byte parallel data D is inputted to the four-byte parallel CRC code calculation circuit 2. Then, the four-byte parallel CRC code calculation circuit 2 calculates a CRC code from the inputted four-byte parallel data {circle over (1)}, {circle over (2)} and outputs the calculated CRC code (calculated intermediate result) to the one-byte serial CRC code calculation circuit 4. [0068] Also, the data {circle over (3)} of the four-byte parallel data D is converted into one-byte serial data 9, 10 by the byte serial conversion circuit (see numeral 3 of FIG. 1). [0069] Then, the one-byte serial CRC code calculation circuit 4 calculates the calculated intermediate result inputted from the four-byte parallel CRC code calculation circuit 2 and the one-byte serial data 9. Further, a CRC code is calculated from the calculated result and the one-byte serial data 10. [0070]FIG. 4 is a timing chart showing calculation processing of a CRC code by the CRC code calculation circuit 10 shown in FIG. 2. [0071] First, a CRC code calculation start signal is inputted to the four-byte parallel CRC code calculation circuit 2 (omission of being shown in the drawing). [0072] Then, when a CRCEN signal outputted from the control part 6 changes to �L� (see (1) in the drawing) and four-byte parallel data 1 is inputted to the four-byte parallel CRC code calculation circuit 2 (see (2) in the drawing), the four-byte parallel CRC code calculation circuit 2 outputs a calculated result A (see (3) in the drawing). [0073] Here, the calculated result A is a CRC code calculated from the four-byte parallel data 1. [0074] Next, when four-byte parallel data 2 is inputted to the four-byte parallel CRC code calculation circuit 2 (see (4) in the drawing), the four-byte parallel CRC code calculation circuit 2 outputs a calculated result B (see (5) in the drawing). Here, the calculated result B is a CRC code obtained by calculating the calculated result A and the four-byte parallel data 2. [0075] Subsequently, when four-byte parallel data 3 to 7 is inputted to the four-byte parallel CRC code calculation circuit 2 in order, the four-byte parallel CRC code calculation circuit 2 outputs calculated results C to G, respectively. [0076] Next, four-byte parallel data 8 consisting of two-byte parallel data (8-1, 8-2) and invalid data of two bytes is inputted to the four-byte parallel CRC code calculation circuit 2 and the byte serial conversion circuit 3 (see (6) in the drawing). [0077] At this time, a STROB signal outputted from the control part 6 changes to �L� (see (7) in the drawing) since the four-byte parallel data 8 is data of the final stage, and a STATE signal outputted from the control part 6 changes to [2] (see (8) in the drawing) since the number of significant bytes of the data 8 of the final stage is two bytes. [0078] Then, after the four-byte parallel data 8 of the final stage is inputted, the CRCEN signal outputted from the control part 6 changes to �H� (see (9) in the drawing) while the STROB signal also changes to �H� (see (10) in the drawing). [0079] Then, the byte serial conversion circuit 3 converts the inputted four-byte parallel data 8 into two one-byte serial data 8-1, 8-2 and outputs the data to the one-byte serial CRC code calculation circuit 4 in order of 8-1, 8-2. [0080] Next, the one-byte serial CRC code calculation circuit 4 calculates a byte serial initial value G (see (11) in the drawing) inputted from the four-byte parallel CRC code calculation circuit 2 and the one-byte serial data 8-1 (see (12) in the drawing) inputted from the byte serial conversion circuit 3, and outputs a calculated result H (see (13) in the drawing). [0081] Further, the one-byte serial CRC code calculation circuit 4 calculates the calculated result H (see (14) in the drawing) and the one-byte serial data 8-2 (see (15) in the drawing) inputted from the byte serial conversion circuit 3, and outputs a calculated result I (see (16) in the drawing). [0082] Then, the calculated result I becomes a CRC code calculated from the four-byte parallel data 1 to 8 by the CRC code calculation circuit 1. [0083] As described above, the CRC code calculation circuits 1 and 10 of the invention provide the byte serial conversion circuit 3 for converting the residual portion of the final stage of four-byte variable-length parallel data into serial data. [0084] Also, there is provided the one-byte serial CRC code calculation circuit 4 for calculating a CRC code in serial from the serial data converted by the byte serial conversion circuit 3 using the calculated result of the four-byte parallel CRC code calculation circuit 2 as an initial value. [0085] Therefore, the residual portion of the final stage of four-byte variable-length parallel data calculated by plural calculation circuits conventionally can be calculated by one serial calculation circuit (one-byte serial CRC code calculation circuit 4), so that a circuit scale of the CRC code calculation circuits 1 and 10 can be decreased and manufacturing costs can be reduced. [0086] Incidentally, in the embodiment, the calculation circuit for calculating a CRC code from the four-byte parallel data is used in order to facilitate a description, but the invention is not limited to this and the number of bytes of parallel data may be set arbitrarily. [0087] Also, both of the residual portion (9, 10) of the final stage {circle over (3)} of the four-byte parallel data D shown in FIG. 3 and the residual portion (8-1, 8-2) of the final stage 8 of the four-byte parallel data 1 to 8 shown in FIG. 4 are set at two bytes, but the number of bytes of the residual portion may be set arbitrarily. [0088] Also, a concrete circuit configuration of the CRC code calculation circuits 1 and 10 can be changed properly. [0089] According to the invention, by converting the final stage of parallel data into serial data, CRC code calculation of a residual portion of the parallel data final stage can be calculated by one serial calculation circuit, so that a circuit scale of a CRC code calculation circuit can be decreased and manufacturing costs can be reduced. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7353448Oct 21, 2003Apr 1, 2008Marvell Semiconductor Israel Ltd.Methods, architectures, circuits and systems for transmission error determinationUS7360142Mar 3, 2004Apr 15, 2008Marvell Semiconductor Israel Ltd.Methods, architectures, circuits, software and systems for CRC determinationUS7434150Mar 3, 2004Oct 7, 2008Marvell Israel (M.I.S.L.) Ltd.Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinationsUS7451381Feb 3, 2004Nov 11, 2008Phonex Broadband CorporationReliable method and system for efficiently transporting dynamic data across a networkUS7734965Apr 1, 2008Jun 8, 2010Marvell Isreal (M.I.S.L.) Ltd.Methods, architectures, circuits and systems for transmission error determinationUS8402353 *Sep 10, 2009Mar 19, 2013Nec CorporationCyclic code processing circuit, network interface card, and cyclic code processing methodUS20100070839 *Sep 10, 2009Mar 18, 2010Nec CorporationCyclic code processing circuit, network interface card, and cyclic code processing methodEP1750264A2 *Jul 19, 2006Feb 7, 2007NEC Electronics CorporationError detecting code calculation circuit, error detecting code calculation method, and recording apparatus* Cited by examinerClassifications U.S. Classification714/758International ClassificationH04L1/00, H03M13/09, G06F11/10Cooperative ClassificationH03M13/6516, H03M13/091European ClassificationH03M13/65F3, H03M13/09BLegal EventsDateCodeEventDescriptionSep 2, 2008FPExpired due to failure to pay maintenance feeEffective date: 20080713Jul 13, 2008LAPSLapse for failure to pay maintenance feesJan 21, 2008REMIMaintenance fee reminder mailedApr 6, 2005ASAssignmentOwner name: YOKOGAWA ELECTRIC CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ANDO ELECTRIC CO., LTD.;REEL/FRAME:016438/0627Effective date: 20050203Owner name: YOKOGAWA ELECTRIC CORPORATION 9-32, NAKACHO 2-CHOMFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ANDO ELECTRIC CO., LTD. /AR;REEL/FRAME:016438/0627Mar 23, 2001ASAssignmentOwner name: ANDO ELECTRIC CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUZUKI, MASAYOSHI;INOUE, TAKAO;MORI, KENJIRO;REEL/FRAME:011640/0236Effective date: 20010314Owner name: ANDO ELECTRIC CO., LTD. 3-484, TSUKAGOSHI, SAIWAI-Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUZUKI, MASAYOSHI /AR;REEL/FRAME:011640/0236RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google