Source: http://www.google.com/patents/US6147402?dq=6,460,050
Timestamp: 2017-07-22 06:17:20
Document Index: 207486485

Matched Legal Cases: ['application No. 08', 'application No. 08', 'application No. 08', 'application No. 07', 'application No. 07', 'application No. 07']

Patent US6147402 - Refractory metal capped low resistivity metal conductor lines and vias - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsCapping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive...http://www.google.com/patents/US6147402?utm_source=gb-gplus-sharePatent US6147402 - Refractory metal capped low resistivity metal conductor lines and viasAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6147402 APublication typeGrantApplication numberUS 09/113,918Publication dateNov 14, 2000Filing dateJul 10, 1998Priority dateFeb 26, 1992Fee statusLapsedAlso published asCN1044649C, CN1076548A, CN1081390C, CN1111908C, CN1112730C, CN1120241A, CN1150597C, CN1192040A, CN1192049A, CN1192050A, DE69329663D1, DE69329663T2, DE69332917D1, DE69332917T2, DE69333604D1, DE69333604T2, EP0561132A1, EP0561132B1, EP0788156A2, EP0788156A3, EP0788156B1, EP0966037A2, EP0966037A3, EP0966037B1, US5300813, US5403779, US5426330, US5585673, US5889328, US5976975, US6323554Publication number09113918, 113918, US 6147402 A, US 6147402A, US-A-6147402, US6147402 A, US6147402AInventorsRajiv V. Joshi, Jerome J. Cuomo, Hormazdyar M. Dalal, Louis L. HsuOriginal AssigneeInternational Business Machines CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (122), Non-Patent Citations (48), Referenced by (35), Classifications (50), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetRefractory metal capped low resistivity metal conductor lines and vias
US 6147402 AAbstract
1. A semiconductor device comprising:a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer; a liner in the at least one hole or line; a conductive metal or alloy within the liner, the conductive metal or alloy having a surface; and a metal-containing layer in contact with at least part of the conductive metal or alloy surface. 2. The semiconductor device of claim 1 wherein the liner is a refractory metal or an alloy or compound thereof.
3. The semiconductor device of claim 1 wherein the conductive metal or alloy includes copper.
4. The semiconductor device of claim 1 wherein the conductive metal or alloy is the alloy Alx Cuy where x+y=1 and x and y are less than or equal to 1.
5. The semiconductor device of claim 1 wherein the metal-containing layer is a refractory metal or an alloy or compound thereof.
6. The semiconductor device of claim 1 wherein the liner and metal-containing layer are made of the same material.
7. The semiconductor device of claim 1 wherein the dielectric layer has a surface and the liner has a sidewall, wherein the sidewall terminates substantially even with the dielectric layer surface.
8. The semiconductor device of claim 1 wherein the liner is a bilayer liner.
9. The semiconductor device of claim 1 wherein the dielectric layer has a surface therein and wherein the conductive metal or alloy surface is substantially even with the dielectric layer surface.
10. The semiconductor device of claim 1 wherein the metal-containing layer is in contact with all of the conductive metal or alloy surface.
11. The semiconductor device of claim 1 wherein the dielectric layer has a surface therein and the metal-containing layer is on the dielectric surface.
12. The semiconductor device of claim 1 wherein the liner is a refractory metal or an alloy or compound thereof and the refractory metal or an alloy or compound thereof includes tantalum.
13. The semiconductor device of claim 1 wherein the metal-containing layer is a refractory metal or an alloy or compound thereof and the refractory metal or an alloy or compound thereof includes tantalum.
14. The semiconductor device of claim 1 wherein the liner is a first liner and further comprising a second dielectric layer having a second submicron hole or line therein and a second liner in the submicron hole or line wherein the metal-containing layer forms part of the second liner.
15. The semiconductor device of claim 1 wherein the liner is substantially conformal.
16. The semiconductor device of claim 7 wherein the conductive metal or alloy surface is substantially even with the dielectric layer surface.
17. The semiconductor device of claim 16 wherein the metal-containing layer is in contact with all of the conductive metal or alloy surface.
18. The semiconductor device of claim 16 wherein the metal-containing layer is on the dielectric surface.
19. The semiconductor device of claim 8 wherein at least one layer of the liner comprises a refractory metal or an alloy compound thereof.
20. The semiconductor device of claim 18 wherein the surface area of the conductive metal or alloy surface is less than the surface area of the metal-containing layer in contact with the conductive metal or alloy surface.
21. The submicron device of claim 13 wherein the dielectric layer comprises a plurality of insulating layers.
22. The semiconductor device of claim 14 wherein the second hole or line is in a surface of the second dielectric layer and the first liner has a sidewall, wherein the sidewall terminates substantially even with the second dielectric layer surface.
23. The semiconductor device of claim 14 wherein the second hole of line is in a surface of the second dielectric layer and the conductive metal or alloy surface is substantially even with the second dielectric layer surface.
24. The semiconductor device of claim 22 wherein the conductive metal or alloy surface is substantially even with the second dielectric layer surface.
25. A semiconductor device comprising:a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer, the at least one hole of line having at least first and second sections, wherein at least one of the width, length or height of the first section is different than the width, length or height of the second section; a first liner in the first section of the at least one hole or line; a first conductive metal of alloy within the first liner, the first conductive metal having a surface; a metal-containing layer in contact with at least part of the conductive metal or alloy surface; and a second liner in the second section of the at least one hole or line, wherein the metal-containing layer forms part of the second liner. 26. A semiconductor device comprising:a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer; a nonporous liner in the at least one hole or line; a conductive metal or alloy within the liner, the conductive metal or alloy having a surface; and a metal-containing layer in contact with at least part of the conductive metal or alloy surface. 27. A semiconductor device comprising:a dielectric layer; at least one high aspect ratio submicron hole or line in the dielectric layer, the at least one hole of line having at least first and second sections, wherein at least one of the width, length or height of the first section is different than the width, length or height of the second section; a nonporous first liner in the first section of the at least one hole or line; a first conductive metal of alloy within the first liner, the first conductive metal having a surface; a metal-containing layer in contact with at least part of the conductive metal or alloy surface; and wherein the second nonporous liner in the second section of the at least one hole or line, or in the metal-containing layer forms part of the second liner. Description
This is a continuation of application No. 08/753,991 filed Dec. 3, 1996, now U.S. Pat. No. 5,889,328, which is a continuation of application No. 08/346,208 filed Nov. 22, 1994, now U.S. Pat. No. 5,585,673, which is a divisional of application No. 08/125,107 filed Sep. 21, 1993, now U.S. Pat. No. 5,426,330, which is a continuation of application No. 07/841,967 filed Feb. 26, 1992, now U.S. Pat. No. 5,300,813 and application No. 07/928,335 filed Aug. 12, 1992, now U.S. Pat. No. 5,403,779 which is a divisional of application No. 07/841,967.
TABLE 1______________________________________DEPOSITION OF LINER BY COLLIMATION             STEP COVERAGE BOTTOM/TOP  ASPECT RATIO SIDEWALL/TOP (%) (%)______________________________________1:1           38            60  1:2 39 70  1:4 42 100  NO COLLIMATION  0 10 12______________________________________
FIGS. 5B-E show similar steps to those shown in FIGS. 2B-E and FIGS. 4A-E are performed in another variation on the invention. Like in FIG. 4A, FIG. 5B shows that an adhesion promoter layer 26, such as Ti, Cr, Ta, Ti/W, or the like, is deposited by PVD evaporation over the top of the refractory metal liner and in the bottom of the gap 14. Like in FIG. 2B, FIG. 5B shows Al--Cu alloy or other metalization 16 being deposited by PVD evaporation techniques to a level 100 to 400 nm below the surface of the dielectric. FIGS. 5C-E respectively show deposition of a conformal layer of tungsten or other refractory material to cap the low resistivity metalization 16, planarizing the tungsten by RIE or polishing, or the like, and planarizing the structure using the two step wet etching of the aluminum-copper alloy with H2 O2 followed by chemical-mechanical polishing of tungsten as shown in FIGS. 4c and 4d or simply. planarizing by one step RIE or chemical-mechanical polishing. For one step chemical-mechanical polishing, a slurry similar to that used for tungsten polishing can be used. Like the structure shown in FIG. 2E, the structure shown in FIG. 5E has a CVD refractory metal 17 encapsulating a low resistivity metalization 16 where there is a tapered refractory metal 17 region.
TABLE 2______________________________________LINE RESISTANCE OF TUNGSTEN CAPPED LOW RESISTIVITY  METAL AFTER POLISHINGa                Resistance Resistance  Structure before W dep. after W dep. Yield______________________________________(A) CREATED USING EVAPORATIONb  Ti(20 nm)/TiN(35 nm)/                0.042      0.04     95%  Al--Cu(800 nm)/W(200 nm)  Ti(20 nm)/Al--Cu(800 nm)/ 0.042 0.052  95%  W(200 nm)  Ti(20 nm)/Al--Cu(800 nm)/ 0.042 0.054  94%  Ti(20 nm)/W(200 nm)  Ti(20 nm)/TiN(25 nm)/ 0.025 0.023  97%  CVD W(30 nm)/  Al--Cu(1300 nm)/W(200 nm)  Ti(50 nm)/TiN(25 nm)/Ti(20 nm)/ 0.025 0.032  96%  Al--Cu(1300 nm)/Ti(20 nm)/  TiN(20 nm)/W(200 nm)  Ti(50 nm)/TiN(50 nm)/Ti(50 nm)/ 0.023 0.021 100%  Al--Cu(600 nm)/Ti(20 nm)/  Cu(700 nm)/Ti(20 nm)/  TiN(20 nm)/CVD W(200 nm)(B) CREATED USING COLLIMATED SPUTTERINGc  Ti(20 nm)/TiN(35 nm)/                0.042      0.04     84%  Al--Cu(800 nm)/CVD W(200 nm)  Ti(20 nm)/Al--Cu(800 nm)/ 0.042 0.05   81%  CVD W(200 nm)  Ti(20 nm)/W(20 nm)/ 0.040 0.039  85%  Al--Cu(800 nm)/CVD W(200 nm)  Ti(20 nm)/TiN(75 nm)/ 0.024 0.022  80%  Cu(800 nm)/Ti(20 nm)/  TiN(25 nm)/CVD W(200 nm)(C) CREATED USING SPUTTERING WITHOUT COLLIMATIONd  Ti(20 nm)/TiN(35 nm)/                0.040      0.04     86%  Al--Cu(800 nm)/CVD W(200 nm)______________________________________
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