Source: http://www.google.com/patents/US20020136540?dq=5726663
Timestamp: 2017-09-21 08:00:13
Document Index: 174995370

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 06']

Patent US20020136540 - Digital video system and methods for providing same - Google Patents
A digital image enhancer includes a deinterlacing processor receptive to an interlaced video stream. The deinterlacing processor includes a first deinterlacer and a second deinterlacer and provides a deinterlaced video stream. The digital image enhancer also includes a video output processor receptive...http://www.google.com/patents/US20020136540?utm_source=gb-gplus-sharePatent US20020136540 - Digital video system and methods for providing same
Publication number US20020136540 A1
Application number US 10/032,136
Also published as US7215376
Publication number 032136, 10032136, US 2002/0136540 A1, US 2002/136540 A1, US 20020136540 A1, US 20020136540A1, US 2002136540 A1, US 2002136540A1, US-A1-20020136540, US-A1-2002136540, US2002/0136540A1, US2002/136540A1, US20020136540 A1, US20020136540A1, US2002136540 A1, US2002136540A1
Inventors Dale Adams, Laurence Thompson, Jano Banks, David Buuck, Cheng Chee
Original Assignee Dvdo, Inc.
Patent Citations (29), Referenced by (24), Classifications (62), Legal Events (8)
US 20020136540 A1
a deinterlacing processor means receptive to an interlaced video stream, said deinterlacing processor means including a first deinterlacer and a second deinterlacer and providing a deinterlaced video stream; and
a video output processor means receptive to said deinterlaced video stream to provide a scaled, deinterlaced video stream.
2. A digital image enhancer as recited in claim 1 wherein said first deinterlacer is operative to analyze progressive frames of said interlaced video stream in an attempt to determine an original source type and sequencing used for the interlaced video stream.
3. A digital image enhancer as recited in claim 2 wherein said first deinterlacer is further operative to convert said interlaced video stream into a deinterlaced video stream using a conversion process that is dependent upon said detection of said original source type and sequencing.
4. A digital image enhancer as recited in claim 1 wherein said second deinterlacer is operative to reduce motion artifacts detected by a frequency analysis of said interlaced video stream.
5. A digital image enhancer as recited in claim 1 wherein said second deinterlacer is operative to detect diagonal features and to smooth said detected diagonal features.
6. A digital image enhancer as recited in claim 1 wherein said deinterlacing processor means processes said deinterlaced video stream in vertical slices.
7. A digital image enhancer as recited in claim 1 wherein said video output processor means is operative to scale said deinterlaced video stream to modify a video display output format of a video output stream.
8. A digital image enhancer as recited in claim 1 wherein said video output processor means includes a data rate synchronizer between a first data rate of said deinterlaced video stream and a second data rate of a video output stream.
9. A digital image enhancer comprising:
a video output processor receptive to the output of said deinterlacing processor, wherein said deinterlacing processor means processes said interlaced video stream in vertical slices to provide a scaled, deinterlaced video stream.
10. A digital image enhancer as recited in claim 9 wherein said deinterlacing processor is operative to analyze progressive frames of said interlaced video stream in an attempt to determine an original source type and sequencing used for the interlaced video stream.
11. A digital image enhancer as recited in claim 10 wherein said deinterlacing processor is further operative to convert said interlaced video stream into a deinterlaced video stream using a conversion process that is dependent upon said detection of said original source type and sequencing.
12. A digital image enhancer as recited in claim 9 wherein said deinterlacing processor is operative to reduce motion artifacts detected by a frequency analysis of said interlaced video stream.
13. A digital image enhancer as recited in claim 9 wherein said deinterlacing processor is operative to detect diagonal features and to smooth said detected diagonal features.
14. A digital image enhancer as recited in claim 9 wherein said video output processor is operative to scale said deinterlaced video stream to modify a video display output format of a video output stream.
15. A digital image enhancer as recited in claim 9 wherein said video output processor includes a data rate synchronizer between a first data rate of said deinterlaced video stream and a second data rate of a video output stream.
16. A portable DVD player comprising:
a digital processing system including a decoder, an image enhancement means, and a display controller where said decoder receives signals from a DVD inserted into said enclosure to provide a decoded, interlaced video signal, said image enhancement means converts said interlaced video signal to a deinterlaced video signal, and said display controller uses said deinterlaced video signal to provide progressively scanned video on said video display.
17. A portable DVD player as recited in claim 16 wherein said digital processing system includes a microprocessor providing control signals to said decoder, said image enhancement means, and said display controller.
18. A portable DVD player as recited in claim 16 further comprising a DVD transport mechanism associated with said port in said enclosure.
19. A portable DVD player as recited in claim 18 wherein said DVD transport mechanism comprises a drawer which extends from a side surface for the loading and unloading of a DVD and which retracts into said enclosure for the playing of said DVD.
20. A portable DVD player as recited in claim 16 further comprising an infrared port associated with said enclosure and coupled to said digital processing system.
21. A portable DVD player as recited in claim 20 further comprising an infrared remote control providing control commands to said DVD player via said infrared port.
22. A portable DVD player as recited in claim 16 further comprising a docking station coupled to a video monitor, wherein said docking station includes a docking port receptive to at least a portion of said enclosure.
23. A portable DVD player as recited in claim 16 further comprising shock isolation means for reducing the affect of physical shocks impinging upon said enclosure.
24. A method for processing digital video comprising:
deinterlacing an interlaced video stream by at least one of a number of deinterlacing methods to produce a deinterlaced video stream; and
25. A method for processing digital video as recited in claim 24 wherein said deinterlacing methods include at least one of an original source detection method, a diagonal feature detection method, and a motion artifact detection method.
26. A method for processing digital video as recited in claim 24 wherein said deinterlacing methods include processing said interlaced video stream in vertical slices.
27. A method for processing digital video as recited in claim 24 wherein said scaling includes a horizontal scaling of the deinterlaced video stream.
28. A method for processing digital video as recited in claim 24 wherein said scaling includes a data rate synchronizer between a first data rate of said deinterlaced video stream and a second data rate of a video output stream.
This application claims the benefits of co-pending U.S. Provisional Patent Application No. 60/060,974 (attorney docket no. DVDOP001+) filed on Oct. 6, 1997, U.S. Patent Provisional Application No. 60/096,144 (attorney docket no. DVDOP002+) filed on Aug. 11, 1998, U.S. Patent Provisional Application No. ______ (attorney docket no. DVDOP003+) filed on Oct. 2, 1998, U.S. Patent Provisional Application No. 60/100,401 (attorney docket no. DVDOP004+) filed on Sep. 15, 1998, U.S. Patent Provisional Application No. 60/094,390 (attorney docket no. DVDOP005+) filed on Jul. 28, 1998, U.S. Patent Provisional Application No. 60/093,815 (attorney docket no. DVDOP006+) filed on Jul. 23, 1998, U.S. Patent Provisional Application No. 06/095,164 (attorney docket no. DVDOP007+) filed on Aug. 3, 1998, and is a continuation in part of U.S. Patent Application number ______ (attorney docket no. DVDOP001AX) filed on Oct. 5, 1998, which are incorporated herein by reference.
[0020]FIGS. 1A and 1B illustrate a portable DVD player in accordance with one embodiment of the present invention.
[0021]FIGS. 2A, 2B, and 2C illustrate several different applications for the DVD player in accordance with one embodiment of the present invention.
[0022]FIG. 2D illustrates a docking station and associated video monitor for the DVD player in accordance with one embodiment of the present invention.
[0023]FIG. 2E illustrates a “DeskTablet™” DVD player in accordance with one embodiment of the present invention.
[0024]FIG. 3 is a block diagram of the electronic circuitry of the DVD player in accordance with one embodiment of the present invention.
[0025]FIG. 4 illustrates a system diagram of the Image Enhancement Engine (IE2) in accordance with one embodiment of the present invention.
[0026]FIG. 5 illustrates a method of combining fields into frames in a deinterlacing process in accordance with one embodiment of the present invention.
[0027]FIG. 6 is a block diagram of a video deinterlacer in accordance with one embodiment of the present invention.
[0028]FIG. 7 is a system diagram of a progressive frame detector in accordance with one embodiment of the present invention.
[0029]FIG. 8 is a flow diagram of the processing steps within a field-differencing module in accordance with one embodiment of the present invention.
[0030]FIG. 9 illustrates details of the frequency detection module in accordance with one embodiment of the present invention.
[0031]FIG. 10 is a system diagram of the PFPD module in accordance with one embodiment of the present invention.
[0032]FIG. 11 is an illustration of a deinterlace process in accordance with one embodiment of the present invention.
[0033]FIG. 12 shows a two-dimensional array of pixel values used to describe the present invention.
[0034]FIG. 13 is a diagram illustrating a method for using obtaining an output pixel from the two-dimensional array of FIG. 12 in accordance with one embodiment of the present invention.
[0035]FIG. 14A is an illustration used to describe the method in accordance with one embodiment of the present invention.
[0036]FIG. 14B is a graph of a set of samples from the sampling line of FIG. 14A.
[0037]FIG. 14C is a graph of a sampled cosine wave.
[0038]FIG. 15 is an illustration used to describe the method of thresholding a detection value in accordance with one embodiment of the present invention.
[0039]FIG. 16 is a block diagram of a mixing circuit in accordance with one embodiment of the present invention.
[0040]FIG. 17 is a diagram of an exemplary operation of the mixing circuit in accordance with one embodiment of the present invention when the DV is greater than “0,” but less than “1.”
[0041]FIG. 18 is an illustration of a method for detecting diagonal features in accordance with one embodiment of the present invention.
[0042]FIG. 19 is a block diagram of a diagonal mixing circuit in accordance with one embodiment of the present invention.
[0043]FIG. 20 is a diagram showing the pixels of secondary array used for calculating the output of the diagonal mixing circuit of FIG. 16.
[0044]FIG. 21 is a flow chart of a diagonal detection method in accordance with one embodiment of the present invention.
[0045]FIG. 22 is an example of a variable scaling FIR filter in accordance with one embodiment of the present invention.
[0046]FIG. 23 is a graph of low-pass filter coefficients in the time domain.
[0047]FIG. 24 is a table of coefficients organized into L sets of mults per set.
[0048]FIG. 25 is a flow chart of a method for quantization in accordance with one embodiment of the present invention.
[0049]FIG. 26 is a flow chart of a method for changing coefficients in accordance with one embodiment of the present invention.
[0050]FIG. 27 illustrates a video frame in accordance with one embodiment of the present invention which is subdivided into a number of vertical slices for a slice scanning sequence exemplified by a corresponding number of scan lines.
[0051]FIG. 28 illustrates an example of an initial slice core that has a problem with unavailable data on its left edge and right edge.
[0052]FIG. 29 illustrates a slice that has added wings along the initial slice core's left and right edges.
[0053]FIG. 30 illustrates an overall structure of overlapping slice/wing combinations.
[0054]FIG. 31 is a flow chart illustrating a method of processing video in accordance with one embodiment of the present invention.
[0055]FIG. 32 illustrates a system diagram for a slice based video processor in accordance with one embodiment of the present invention.
[0056]FIG. 33 illustrates a system diagram of a video processing chip architecture in accordance with one embodiment of the present invention.
[0057]FIG. 34 is a diagram of an asynchronous interface in accordance with one embodiment of the present invention.
[0058]FIG. 35 is a diagram of an alternative asynchronous interface in accordance with one embodiment of the present invention.
[0059]FIG. 36 is a diagram of a 3-buffer synchronizer sequence illustrating the sequencing and relative relationships of read and write operations to three RAM buffers in accordance with one embodiment of the present invention.
[0060]FIG. 37 is a flow chart of a method for sequencing through RAM addresses and modules in accordance with one embodiment of the present invention.
[0061]FIG. 38 is a diagram of a synchronizer of the present invention configured for use in a video scaling application in accordance with one embodiment of the present invention.
[0063]FIGS. 1A and 1B illustrate a portable DVD player 10 in accordance with one embodiment of the present invention. The DVD player 10 includes a housing 12 that serves as an enclosure or chassis for the components of the DVD player 10. A screen 14 for viewing the video and control buttons 16 to control the DVD player 10 are located on the top face of the housing 12. Power and signal interfaces 18 are located on one of the two side faces of the housing 12, while an infrared (IR) interface 20 and a media transport 22 are located on the other side face. A DVD 24 can fit within a suitably configured recess in the media transport 22, and the media transport 22 withdraws into the housing 12 to permit the playback of DVD 24.
[0064]FIG. 2A shows an illustration of use in an automobile, but the idea can be extended to most types of transportation. The present invention is ideally suited to the traveler who spends long hours in a passive commute, such as on an airplane, train, or subway as illustrated in FIG. 2B. In addition, many commercial applications are possible as well, for example, video advertising in taxicabs or other settings where a captive audience exists. The present invention can also be placed on the magazine rack of every Stairmaster® exercise machine and treadmill in a fitness center setting, as illustrated in FIG. 2C.
[0067]FIG. 2D illustrates a “Home Theater Docking Station” provides an uncomplicated, one-step connection and operation capability for when the present invention is used as a simple DVD player with a normal home television set. The dock provides a cabled electrical interface to a television or other home theater components—such as an audio system—that can remain permanently in place for when the present invention is used with an external system. The dock is preferably the same form-factor as a typical VCR; it will be designed to blend in with the rest of the system components that a user owns, and also be instantly recognizable for its intended function.
[0069]FIG. 2E illustrates one embodiment in accordance with one embodiment of the present invention for the desktop market is referred to herein as a “DeskTablet™” DVD player. Applications for the DeskTablet include uses such as in the bedroom, den, or kitchen, where a “fixed” unit placement is needed. This product is essentially in the same marketing space as conventional TV/VCR combination units. Similar in form factor to the “Monorail” personal computer, the thin DeskTablet form factor will be capable of either freestanding or wall hanging operation. Freed of many of the portability-driven design constraints required of the present invention mobile machine, the DeskTablet will include a high-quality integrated loudspeaker system.
[0070]FIG. 3 is a block diagram of the drive module 26 of the DVD player 10 of FIGS. 1 and 2. The drive module 26 includes the media transport 22 that reads the DVD. Video data from the DVD is then transferred over to a MPEG/Dolby digital (or “MPEG/AC-3”) decoder 28. After decoding, an Image Enhancement Engine™ (IE2) 30 deinterlaces the digital video to provide a progressively scanned video signal. Finally, the video is displayed through a display 36.
[0088]FIG. 4 illustrates a system diagram of the Image Enhancement Engine (IE2) 30 (see FIG. 3) in accordance with one embodiment of the present invention. The E2 30 includes a two dimensional video processing chip architecture 50 and a video output processor 60. The chip architecture 50 includes a first deinterlacing stage 70 and a second deinterlacing stage 80 and a set of addressing and sequencing FIFOs 90. The first deinterlacing stage 70 includes progressive frame sequence detection and field difference processing. The second deinterlacing stage 80 includes vertical frequency detection, sign reversal detection and diagonal feature detection. The video output processor 60 includes horizontal scaling, color space conversion, 8 to 6 bpp dithering and gamma, contrast, and brightness corrections.
[0092]FIG. 6 is a block diagram of a video deinterlacer 130 in accordance with one embodiment of the present invention. A digital video stream enters the deinterlacer 130 through a FIFO memory module 132 before being written into a digital memory unit 134. The digital memory unit 134 has the capacity to store four complete video fields in a set of field buffers 134 a-d. The incoming field is written to each of the field buffers 134 a-d in sequence. Therefore, the first incoming video field is written to field buffer 134 a, the second incoming video field is written to field buffer 134 b, etc. After field buffer 134 d is filled, the next incoming video field is written to field buffer 134 a again.
[0101]FIG. 7 is a system diagram of a progressive frame detector 142 in accordance with one embodiment of the present invention. The frame detector 142 includes a field differencing module 154, a frequency detection module 156, and a progressive frame pattern detection (PFPD) module 158. The field differencing module 154 calculates the difference between a Next Field 160 and a Last Field 162, processes the differences into the Stage1DV 148, a transition detection 3:2 value 166, and a plurality of equal field history bits 168.
[0103]FIG. 8 is a flow diagram of the processing steps within the field-differencing module 154 in accordance with one embodiment of the present invention. A Next array of pixels 174, which is a subset of the Next Field 160, and a Last array of pixels 176, which is a subset of the Last Field 162 are the inputs to a differencer 178. The Next and Last pixel arrays 174 and 176 can be viewed as windows moving across their respective fields. The “window” is moved from left to right and top to bottom. Each time the windows are moved, a new difference is computed. The result of the difference operation 178 is an array of differences 180.
[0106]FIG. 9 illustrates details of the frequency detection module 156 in accordance with one embodiment of the present invention. Vertically adjacent pixels 206 from the Current Field 164 and the Last Field 162 are assembled, as they would appear spatially on a display. A frequency detection value is calculated in an operation 208. This calculation is performed to detect the frequencies that are associated with deinterlaced motion artifacts. In an operation 210, the output of the frequency detection is compared with a programmable threshold value 212. The results of five adjacent frequency detection values are stored in a memory module 214 and are summed in an operation 216.
[0109]FIG. 10 is a system diagram of the PFPD module 158 in accordance with one embodiment of the present invention. The PFPD module 158 performs logical operations on a set of field difference history bits 244, the frequency detection history bits 242, the transition 3:2 value 192 (see FIG. 8), and the transition value 228 (see FIG. 9). After the input of the field difference history bits 244, a logical operation 246 determines the 3:2 pulldown detection bit by looking for patterns in which every fifth field is equal. Then, a logical operation 248 detects still images by setting the STILL bit when the most recent four field differences are zeros. The state of the L/N control signal is set by a logical operation 250.
[0117]FIG. 12 shows a two-dimensional array of pixel values 318 that is a subset of the combined frame 312 of FIG. 11 that will be used to describe the present invention by way of example. The array of pixels 318 is shown having a width of 5 and a height of 7 pixels. The array 318 is labeled across the top C0 to C4 indicating columns and is labeled vertically along the left side from the top to bottom R0 to R6 indicating rows. The pixels contained in array 318 are used to compute a frequency detection value. In addition, the array 318 is also used to detect diagonal features and finally to compute the resulting pixel.
[0120]FIG. 13 illustrates a method 326 for obtaining an output pixel 338 from the two-dimensional array 318. In an operation 328, a frequency detection value is obtained using the seven pixels of each column of the two-dimensional array 318. Because there are five columns, there are five frequency detection operations performed, producing a set of detection values fd0, fd1, fd2, fd3, and fd4. Next, an operation 330 thresholds the set of detection values fd0-fd4. Then, in an operation 332, the set of detection values fd0-fd4 is combined in a weighted average to arrive at an ultimate detection value (UDV) 334.
The UDV 334 computed in operation 332 is used to control a mixing operation 336, which preferably implements the following equation: pixelout=(UDV*(pR2C2+pR4C2)/2)+((1−UDV)*pR3C2) where pixelout is the new output pixel of the deinterlacing operation, pR2C2 is a pixel in the array 318 at location Row 2, Column 2, pR4C2 is a pixel in the array 318 at location Row 4, Column 2, and pR3C2 is a pixel in the array 318 at location Row 3, Column 2.
[0124]FIG. 14A illustrates an image 340 showing operation 328 in greater detail. The image 340 shows the computation of a single frequency detection value for one column of array 318. Image 340 includes a distorted object 342 which is effected by an interlace motion artifact. The image is sampled along a line 344, which is shown for exemplary purposes. This sampling corresponds to one of the columns in the two-dimensional array 318. In this example, line 344 passes through an area where artifacts exist, but in general, a sampling of vertical adjacent pixels may or may not contain artifacts.
[0125]FIG. 14B is a graph 346 of a set of samples 348 obtained by sampling along line 344 of FIG. 14A. The set of samples 348 are plotted with the row numbers along the horizontal axis and the brightness or intensity of the pixel along the vertical axis. From graph 346, it is apparent that the areas where motion artifacts exist, such as the set of samples 348, will show a characteristic frequency. This is frequency in space rather than in time and is most conveniently expressed as cycles per line rather than cycles per second or Hertz. The characteristic frequency is 1 cycle/2 lines or 0.5 cycle/line.
[0126]FIG. 14C is a graph of a sampled cosine wave 350. The characteristic frequency created by the motion artifact is detected by multiplying the set of samples 348 by the sampled cosine wave 350. The sampled cosine wave 350 has a frequency equal to the characteristic frequency of the motion artifact. Then, the result is integrated using the following equation: fd = ∑ R = 0 R = 6   Y  ( R )  cos  ( 2  R   π * 0.5   cycle / line )
The expression cos (2πR*0.5 cycle/line) simplifies to 1 for R=0, 2, 4, and 6 and −1 for R=1, 3, and 5. If 1 and −1 are substituted for R0 . . . R6, the frequency detection equation becomes: fd=(Y6/2+Y4+Y2+Y0/2)−(Y5+Y3+Y1). Note that Y6 and Y0 are divided by 2 because the integration is over the limits 0 to 6. The final fd is the absolute value: fd=Abs(fd). The method 326 of FIG. 13 is repeated for each column in array 318, producing the set of frequency detection values 330.
[0129]FIG. 15 is a graph 352 illustrating thresholding operation 330 in greater detail. Each fd is a number in the range 0 to 1. Graph 352 includes a non-thresholded scale 354 from which values are thresholded to the thresholded scale 356. Thresholding sets all values above the upper threshold point 358 to the value of 1. All values below the lower threshold point 360 are set to a value of 0. Values between the upper and lower thresholds are expanded to the range 0 to 1. Thresholding can be described with the following equation: tdf=(ptfd−LTH)/UTH where tdf is the thresholded frequency detection value, pthfd is the pre-thresholded frequency detection value (the output of operation 328), LTH is the lower threshold value and UTH is the upper threshold value. If tfd>1.0, then tfd=1.0. Otherwise, if tfd<0 then tfd=0.
It will therefore be appreciated that the deinterlacing process of the present invention provides good vertical resolution without creating edge artifacts in moving objects in a video image. This is accomplished by employing two-field interlacing where the image is relatively-static, and employing one-field line doubling where the image is rapidly changing. The combination of these techniques provides a low-artifact, high-resolution deinterlaced image.
[0132]FIG. 17 is a diagram of an exemplary operation of the mixing circuit 400 when the UDV 334 is greater than “0,” but less than “1.” The mixing circuit 400 uses information from the three-pixel array 402 by blending R3C2, and the average of R2C2 and R4C2 to form a new output pixel 406 at location R3C2.
[0133]FIG. 18 is an illustration of a method 408 for detecting diagonal features. A secondary array 410 that is a subset of array 318 is input into a diagonal detection circuit 412 which operates in parallel to the method 326 of FIG. 13. If no diagonal feature is detected, then the diagonal detection circuit 412 produces no output. However, if a diagonal feature is detected, the diagonal detection circuit 412 produces two outputs: a single bit Sign signal 414 and a multiple bit SlopeFade signal 416. The specific method for calculating the Sign and SlopeFade signals 414 and 416 is shown in FIG. 21 and its corresponding description.
[0135]FIG. 19 is a block diagram of a diagonal mixing circuit 418 in accordance with one embodiment of the present invention. The diagonal mixing circuit 418 includes a multiplexer 420, a first mixer 422, and a second mixer 424. The multiplexer 420 relies on the Sign signal 414 to determine which pair of diagonally adjacent pixels are used. After a pair of diagonally adjacent pixels is chosen, the first mixer 422 blends the pixel values that are vertically adjacent to R3C2 with those that are diagonally adjacent to R3C2. The amount of blending is determined by the SlopeFade signal 416, which is proportional to the magnitude of the diagonal feature that is detected.
[0137]FIG. 20 is a diagram showing the pixels of secondary array 410 used for calculating the output of the diagonal mixing circuit 418. If no diagonal features are detected within the secondary array 410, then the output of the mixing circuit is determined from the pixels along a line 426. If a diagonal feature is detected in diagonal detection circuit 412, the pixels that are diagonally adjacent to R3C2 along a line 428 or a line 430 are used to calculate the output pixel. The Sign signal 414 is used to determine which line 428 or 430 is used.
[0138]FIG. 21 is a flow chart of a diagonal detection method 432 in accordance with one embodiment in accordance with one embodiment of the present invention. The method 432 shows the flow of logical and mathematical operations used to compute the SlopeFade signal 416 and the Sign signal 414 from the secondary array 410. The corner pixels are divided into two horizontal pairs and two vertical pairs by an operation 434. The horizontal pairs are labeled hv2 and hv4 and the two vertical pairs are labeled vv2 and w4. Differences are computed for each pair of corner pixel values by subtraction, producing a pair of horizontal differences and a pair of vertical differences.
[0147]FIG. 23 is a graph of low-pass filter coefficients 520 in the time domain stored in the coefficient storage unit 516 to produce coefficients. The low-pass filter coefficients 520 are represented by the equation below. ∑ i = 1 m   c  ( i ) = 2  Lfc 2   fcπ  ( i - 1 / 2 ) * sin  [ 2   fcπ  ( i - 1 / 2 ) ] * { 0.54 + 0.46  cos  [ 2  π  ( i - 1 / 2 ) / taps ] } ( 1 )
[0149]FIG. 24 shows the coefficients 524 organized into L=8 sets of mults=6 coefficients per set. The sum of all the coefficients in each set i where i=1 to L is represented by the equation below. s  ( i ) = ∑ j = 1 j = mults   c  ( L  ( j - 1 ) + i ) ( 2 )
[0150]FIG. 25 is a flow chart of a quantization method 526 in accordance with one embodiment of the present invention. The method 526 initializes with a given set of parameters 528 needed to compute the coefficients where L is the numerator of the scaling ratio L/M; mults is the number of multipliers used in the FIR filter; and n is the number of bits to which the coefficients will be quantized. An operation 530 computes the FIR filter coefficients using equation 1. In an operation 532, the coefficients are organized from left to right and labeled c(1), c(2), c(3), . . . c(L*mults).
[0153]FIG. 26 is a flow chart of the operation 546 from FIG. 25 in much greater detail. An operation 548 is a loop set up to step through the coefficients of set(i) in a particular order. The order starts with the outermost coefficient of the set(i), and then moves toward the center of the set. Operation 548 is executed mults times, because there are mults number of coefficients per set. Next, an index k is computed in an operation 550, which is used to process the coefficients in the previously stated order.
Operation 554 evaluates whether the absolute value of the sum of c(1) and F is less than or equal to the absolute value of the coefficient to the right of c(1). This means that c(k+1) <c(2). If the result is true, then c(1) can be adjusted by adding F without creating a discontinuity or divergence from the zero axis. The coefficient is adjusted in an operation 564, and operation 546 is exited successfully. If the result is false, then operation 560 performs a loop iteration.
If operation 552 determines that the coefficient to be adjusted is neither the leftmost or rightmost one, then an operation 558 is performed. Operation 558 evaluates whether the sum of c(k) and F is outside the limits of the coefficients on the left and right, that is c(k−1) and c(k+1), by evaluating the equations c(k−1)≦c(k)≦c(k+1) and c(k−1)≧c(k)≧c(k+1). If either of the equations is true, then the coefficient c(k) is set equal to c(k)+F in operation 564 and a discontinuity is not introduced. Therefore, operation 546 is successfully exited. If either of the equations is false, then a loop iteration is performed in operation 560.
[0161]FIG. 28 illustrates an example of a slice core 606 that has a problem with unavailable data on its left edge 608 and right edge 610. For purposes of illustration, unavailable data is shown only on the left edge in FIG. 28. Video processing requires that data surrounding a given pixel be available in both the horizontal and vertical directions (in this case 5×5 matrices 612 and 614 centered on the pixel).
[0164]FIG. 29 illustrates a slice 622 that includes a pair of thin vertical slices or “wings” 624 and 626 along the left and right edges 608 and 610. Wing 624 has been added to the slice core 606 to provide the pixel data needed for the processing matrix. Wing 626 has been added to the right edge 610 of the slice core 606. Because wing 624 has been added to slice 622, processing matrix 614 no longer suffers from the lack of data outside of the left edge 608 of slice 622.
[0165]FIG. 30 illustrates an overall structure of overlapping slice/wing combinations 628. Slice 622 from FIG. 29 is shown as an exemplary slice. Wings 624 and 626 of slice 622 are composed of data from a pair of adjacent slices, one to the left and one to the right of slice 622. More specifically, the missing two left columns of pixels in wing 624 are supplied from the two right most columns 630 of a slice 632 immediately to the left of slice 622. So in a sequence of slices 634, the left-most wing of slice N overlaps the core of slice N−1, while the right-most wing of slice N−1 overlaps the core of slice N.
[0166]FIG. 31 is a flow chart illustrating a method 636 of processing video in accordance with one embodiment of the present invention. The input to a video processing block is therefore the slice 622 with slice core 606, left wing 624 and right wing 626. The left wing 624 is divided into a left outer wing 638 and a left inner wing 640. The right wing 626 is divided into a right outer wing 644 and a right inner wing 642. In this example, the video processing block has multiple processing stages, each with its own requirement for horizontal pixels on each side of the center.
A preferred embodiment of the present invention utilizes three vertical video processing blocks. The first processing stage 646 requires a pair of outer wings 638 and 644 having a width of 2 pixels; the second processing stage 650 requires a pair of inner wings 640 and 642 with a width of 4 pixels; and the third processing stage 652 requires no wings as the specific processing algorithm used does not require data horizontal to the vertical data being processed. The slice core width chosen was 36 pixels, resulting in an initial input slice width of 48 pixels. (Core+left-inner-wing+right-inner-wing+left-outer-wing+right-outer-wing=36+4+4+2+2=48.)
[0172]FIG. 32 illustrates an example of a system diagram for a slice-based video processor 654. A first input buffer 656, a second input buffer 658, a first output buffer 660, and a second output buffer 662 are required for the slice conversion process. Because video applications typically require real-time input and output, and because the scanning process for a conventional raster-scan and a slice-scan are different, the first input buffer 656 is used to store the video input data stream from the input data formatter 664. The second input buffer 658 (filled in the previous field/frame period) is used to provide data to the vertical video processing section 666 in a slice-scan format.
[0174]FIG. 33 illustrates a system diagram of one example of a video processing chip architecture 670. The video processing chip architecture 670 includes a video processor 672 and an external memory source 674. In this particular video processing implementation, multiple input field storage (for temporal processing) is required. Video data is provided to an input stage 676 in the video processor 672 that adds the redundant wing data directly into the video data stream. The data is then written (wings included) in a raster-scan sequence to a first field memory buffer 678 in the external memory source 674 by the memory controller 680 which is located inside the video processor 672.
Overall, this implementation results in a greater than 10× reduction in on-chip memory requirements due to the slice-scan architecture. This expense saved with the reduction in on-chip memory requirements more than offsets the additional required external memory, and provides a variety of prototyping and production options.
A synchronization logic unit 720 external to the synchronizer 705 coordinates the reading and writing of data. Optionally, the synchronization logic 720 could be part of the synchronizer 705 itself Multiple synchronization schemes may be implemented. For example, the synchronization logic 720 could signal the WCL unit 706 and the data source 702 when to start a data transfer. A predetermined period later, when the first RAM buffer 708 has been filled and the second RAM buffer 710 is in the process of being filled, the synchronization logic 720 instructs the RCL unit 714 to begin reading data from the first RAM buffer 708 and to provide it to the data destination 718.
[0186]FIG. 35 is a diagram of an alternative asynchronous interface 722. Data transfer is initiated via an external signal to the WCL unit 724 that indicates that a data transfer is to begin. The WCL 724, synchronous to clock C1, generates write enables and addresses for the a first single-ported RAM buffer 726, a second single-ported RAM buffer 728, and a third single-ported RAM buffer 730. The single-ported RAM buffers 726, 728, and 730 have synchronous write and asynchronous read capabilities.
[0189]FIG. 36 is a diagram of a 3-buffer synchronizer sequence 738 illustrating the sequencing and relative relationships of read and write operations to three RAM buffers. Potential clock synchronization delay issues pertaining to real-time buffer sequencing for the continuous data output stream are mitigated by the fact that read and write operations are separated from each other by a skew 739 of approximately 1½ RAM buffers.
[0191]FIG. 37 is a flow chart of a method 740 for sequencing through RAM addresses and modules in accordance with one embodiment of the present invention. The method 740 begins at an operation 742 in which the RAM address for both read and write operations is set to zero, as is the selected RAM buffer. Next, an operation 744 asks if the data is valid. If the answer is no, operation 744 repeats itself until data is valid. If the answer is yes, then the method 740 proceeds to an operation 746 which asks if a variable called EndCnt is equal to 1. If the answer is yes, then the last RAM module has been reached and an operation 748 increments to select the next RAM module before executing an operation 750. If the answer is no from operation 746, then operation 750 increments the RAM address.
[0193]FIG. 38 is a diagram of a synchronizer 758 in accordance with one embodiment of the present invention intended for use in a video scaling application. The input source generates an 8-bit wide input data stream 760 for the synchronizer 758. The input data stream 760 runs at a clock rate of 732 MHz (C1) with an average data rate of 48 MHz (C2). Three 8-bit wide by 16-element deep RAM buffers 762, 764, and 766 are used. A WCL unit 768 generates three RAM write-enable signals and a 4-bit RAM address.
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U.S. Classification 386/232, 386/E05.07, 348/E05.108, 348/E05.133, 348/E05.067, 386/E09.013, 348/446, 348/448, 348/E07.015, 348/E05.062
International Classification H04N5/66, G09G5/39, H04N5/44, H04N5/85, H04N9/804, G09G5/393, G06T5/00, H04N5/14, H04N7/01, H04N5/775, G06T3/40, B60R11/02, G06F1/16, B60R11/00
Cooperative Classification G06T2207/10016, G06T5/002, G06T2207/20192, H04N9/8042, H04N5/775, B60R2011/0017, H04N7/012, G06F1/1656, G06F1/1632, G06F1/1626, H04N5/85, H04N7/0112, B60R2011/0012, B60R11/0235, B60R11/0252, H04N5/14, H04N5/147, H04N5/66, G06T3/40, B60R11/0211, G09G2310/0229, G09G5/39, H04N5/4401, G09G5/393, G06F1/166
European Classification G06F1/16P9E, G06F1/16P6, G06F1/16P9E2, H04N7/01G3, H04N7/01F, H04N9/804B, G06T5/00D, H04N5/775, G06T3/40, G06F1/16P3, B60R11/02J, B60R11/02C, B60R11/02E2
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