Source: https://patents.google.com/patent/US7381990B2/en
Timestamp: 2020-02-17 12:48:57
Document Index: 653216959

Matched Legal Cases: ['arts 12', 'art 12', 'arts 12', 'arts 12', 'arts 12', 'arts 12', 'arts 12', 'arts 12', 'arts 12', 'arts 12', 'arts 12', 'art 12', 'arts 52', 'art 52', 'arts 52', 'arts 52', 'art 52', 'arts 52', 'arts 52', 'arts 52', 'arts 12', 'arts 52', 'arts 52', 'arts 12', 'arts 12', 'arts 52', 'arts 52']

US7381990B2 - Thin film transistor with multiple gates fabricated using super grain silicon crystallization - Google Patents
Thin film transistor with multiple gates fabricated using super grain silicon crystallization Download PDF
US7381990B2
US7381990B2 US11/023,640 US2364004A US7381990B2 US 7381990 B2 US7381990 B2 US 7381990B2 US 2364004 A US2364004 A US 2364004A US 7381990 B2 US7381990 B2 US 7381990B2
US11/023,640
US20050158920A1 (en
2001-12-19 Priority to KR2001-81446 priority Critical
2001-12-19 Priority to KR20010081446A priority patent/KR100477103B1/en
2004-12-29 Priority to US11/023,640 priority patent/US7381990B2/en
2004-12-29 Application filed by Samsung SDI Co Ltd filed Critical Samsung SDI Co Ltd
2005-07-21 Publication of US20050158920A1 publication Critical patent/US20050158920A1/en
2006-12-08 Assigned to SAMSUNG SDI CO., LTD. reassignment SAMSUNG SDI CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SO, WOO-YOUNG
2008-06-03 Publication of US7381990B2 publication Critical patent/US7381990B2/en
238000002425 crystallisation Methods 0 abstract description title 19
229910052710 silicon Inorganic materials 0 abstract description title 4
239000010703 silicon Substances 0 abstract description title 4
A thin film transistor with multiple gates is fabricated using a super grain silicon (SGS) crystallization process. The thin film transistor a semiconductor layer formed in a zigzag shape on an insulating substrate, and a gate electrode intersecting with the semiconductor layer. The semiconductor layer has a high-angle grain boundary in a portion of the semiconductor layer that does not cross the gate electrode.
The present invention relates to a thin film transistor using super grain silicon crystallization (hereinafter referred to as “SGS”), and more particularly, to a TFT with multiple gates which prevents defects by removing a high-angle grain boundary in a channel region and reduces leakage current by materializing multiple gates without increasing the area.
” shaped structure equipped with a pair of body parts 12L1 and 12L2 and a connection part 12B connecting the body parts 12L1 and 12L2 as shown in FIG. 2A, the semiconductor layer 12 a is not necessarily limited to such a structure, but can have a “E” or “
” shaped structure, or a combination thereof equipped with a plurality of body parts 12L, wherein the plurality of body parts 12L are connected by a plurality of connection parts 12B so that the semiconductor layer 12 a has a zigzag shaped structure as shown, for example, in FIG. 10.
On the other hand, the gate electrode 16 may have parts acting as more than two gates since parts of the gate electrode 16 overlapping the body parts 12L would each act as a gate where the semiconductor layer 12 a is not formed in a “
” shape as shown in FIG. 2A, but is formed in a zigzag shape equipped with a plurality of body parts 12L as shown, for example, in FIG. 10. The example shown in FIG. 10 has five body parts 12L, such that the gate electrode 16 would have five parts overlapping the five body parts 12L and acting as five gates.
Referring to FIG. 1C, FIG. 1C′ and FIG. 2C, an interlayer insulating film 18 is formed on the gate insulating film 14 comprising the gate electrode 16, and contact holes 19-1 and 19-2 are respectively formed in impurity areas 12-11 and 12-13 for the source/drain regions by etching the interlayer insulating film 18 and the gate insulating film 14 using a third mask (which is not shown in the drawings). The contact holes 19-1 and 19-2 are formed at edge parts of both sides of the semiconductor layer 12 a formed in a “
” shape so that the contact holes 19-1 and 19-2 are formed at one side edge of the body part arranged at the outermost wall part in a plurality of body parts 12L1 and 12L2, that is, one side edge of the body part that is not connected by a connection part 12B.
Referring to FIG. 3B and FIG. 4B, the photosensitive film 34 is then reflowed to form a reflowed photosensitive film 34 a that completely covers the patterned blocking layer 33. A first pattern 34-1 a and a second pattern 34-2 a of the reflowed photosensitive film 34 a formed from the first pattern 34-1 and the second pattern 34-2 of the photosensitive film 34 contact each other. The blocking layer 33, a portion of the amorphous silicon film 32 surrounding the block layer 33, and a portion of the amorphous silicon film 32 between the first pattern 33-1 and the second pattern 33-2 of the blocking layer 33 are completely covered by the reflowed photosensitive film 34 a.
Subsequently, referring to FIG. 3B and FIG. 4B, a capping layer 35 and a metal film 36 each having a thickness of several angstroms Å to hundreds of angstroms Å are formed on the reflowed photosensitive film 34 a and the amorphous silicon film 32. The capping layer 35 controls a concentration of metal diffused from the metal film 36 into the amorphous silicon film 32. The capping layer 35 is made of SiO2 or SiNx, and is preferably made of SiO2. The metal film 36 is made of a metal such as Ni or Pd. Metal from the metal film 36 is diffused into the amorphous silicon film 32 to form crystallization seeds in the amorphous silicon film 32.
Each of impurity areas 39 a˜39 d for source/drain regions are formed by ion-implanting high concentrations of impurities of P-type or N-type into the first semiconductor layer 40 a and the second semiconductor layer 40 b using the gate electrode 38 as a mask, wherein a part overlapped by the first gate 38-1 in the first semiconductor layer 40 a acts as a first channel region 40 c, while a part overlapped by the second gate 38-2 in the second semiconductor layer 40 b acts as a second channel region (not shown).
” shaped structure is illustrated in FIG. 6A in which the semiconductor layer 52 a is equipped with a pair of body parts 52L1 and 52L2 and a connection part 52B to connect the body parts 52L1 and 52L2, the semiconductor layer 52 a is not limited to the body parts 52L1 and 52L2 and the connection part 52B, but can be equipped with a plurality of body parts 52L, wherein the plurality of body parts 52L are connected by a plurality of connection parts 52B so that the semiconductor layer 52 a has a zigzag shaped structure similar to the semiconductor layer 12 a equipped with a plurality of body parts 12L shown in FIG. 10.
On the other hand, the gate electrode 56 may have parts acting as more than four gates since parts of the gate electrode 56 equipped with the slot 56S overlapping the body parts 52L would each act as a gate where the semiconductor layer 52 a is not formed in a “
” shape as shown in FIG. 6A, but is formed in a zigzag shape equipped with a plurality of body parts 52L similar to the semiconductor layer 12 a equipped with a plurality of body parts 12L shown in FIG. 10. The example shown in FIG. 10 has five body parts 12L, such that if the semiconductor layer 52 a were equipper with five body parts 52L, the gate electrode 56 equipped with the slot 56S would have ten parts overlapping the five body parts 52L and acting as ten gates.
” shaped semiconductor layer 82 is formed by patterning the polycrystalline silicon film 82 b using a mask after removing the capping layer and the metal film 84, as illustrated in FIG. 8C. This embodiment can be applied to a thin film transistor having the same structure as in the embodiment of FIGS. 1A to 1D so that a high-angle grain boundary 82 c exists outside channel regions. Thereafter, a thin film transistor with multiple gates is fabricated by the same method as in the embodiment of FIGS. 1A to 1D.
” shaped semiconductor layer 92 is formed by patterning the polycrystalline silicon film 92 b using a mask after removing the capping layer and the metal film 93 as illustrated in FIG. 9C. This embodiment can be applied to a thin film transistor having the same structure as in the embodiment of FIG. 7 so that a high-angle grain boundary 92 c exists outside channel regions during formation of multiple gates. Thereafter, a thin film transistor with multiple gates is fabricated by the same method as in the embodiment of FIG. 7.
6. The thin film transistor of claim 1, wherein the semiconductor layer is formed in a
shape on the insulating substrate.
7. The thin film transistor of claim 1, wherein the semiconductor layer is formed in a
US11/023,640 2001-12-19 2004-12-29 Thin film transistor with multiple gates fabricated using super grain silicon crystallization Active 2023-04-26 US7381990B2 (en)
US10/890,999 Continuation-In-Part US7001802B2 (en) 2001-12-19 2004-07-15 Thin film transistor with multiple gates using metal induced lateral crystalization and method of fabricating the same
US20050158920A1 US20050158920A1 (en) 2005-07-21
US7381990B2 true US7381990B2 (en) 2008-06-03
CN107482066A (en) * 2017-09-20 2017-12-15 京东方科技集团股份有限公司 Thin film transistor (TFT) and preparation method thereof, array base palte and display device
KR20190113236A (en) 2018-03-28 2019-10-08 양승선 Cricket breeding apparatus
US20060006465A1 (en) 2004-07-07 2006-01-12 Byoung-Keon Park Thin film transistor and method of fabricating the same
US20060046357A1 (en) 2004-08-24 2006-03-02 Sang-Woong Lee Method for fabricating thin film transistor
U.S. Appl. No. 11/010,271, filed Dec. 14, 2004, So, Samsung SDI Co., Ltd.
U.S. Appl. No. 11/011,584, filed Dec. 15, 2004, So, Samsung SDI Co., Ltd.
U.S. Appl. No. 11/023,637, filed Dec. 29, 2004, So, Samsung SDI Co., Ltd.
U.S. Appl. No. 11/105,382, filed Apr. 14, 2005, So, Samsung SDI Co., Ltd.
CN100350617C (en) 2007-11-21 Semiconductor element and semiconductor device using said element
KR19980032907A (en) 1998-07-25 The manufacturing method of the crystalline semiconductor
CN1716635A (en) 2006-01-04 Thin film transistor and method of fabricating the same
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SO, WOO-YOUNG;REEL/FRAME:018656/0102