Source: https://patents.google.com/patent/US8374299B2/en
Timestamp: 2019-07-19 06:42:55
Document Index: 331066643

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

US8374299B2 - Serial cancellation receiver design for a coded signal processing engine - Google Patents
US8374299B2
US8374299B2 US13/076,332 US201113076332A US8374299B2 US 8374299 B2 US8374299 B2 US 8374299B2 US 201113076332 A US201113076332 A US 201113076332A US 8374299 B2 US8374299 B2 US 8374299B2
US13/076,332
US20110182330A1 (en
2001-09-28 Priority to US32521501P priority Critical
2001-10-02 Priority to US32619901P priority
2001-11-16 Priority to US33148001P priority
2001-11-27 Priority to US33314301P priority
2002-01-15 Priority to US34810602P priority
2002-02-05 Priority to US35409302P priority
2002-09-20 Priority to US10/247,836 priority patent/US7158559B2/en
2011-03-30 Priority to US13/076,332 priority patent/US8374299B2/en
2011-03-30 Application filed by Rambus Inc filed Critical Rambus Inc
2011-07-28 Publication of US20110182330A1 publication Critical patent/US20110182330A1/en
2013-02-12 Publication of US8374299B2 publication Critical patent/US8374299B2/en
2013-12-16 Assigned to RAMBUS INC. reassignment RAMBUS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OLSON, ERIC S., THOMAS, JOHN K., NARAYAN, ANAND P.
2014-05-16 Assigned to THOMAS, JOHN K. reassignment THOMAS, JOHN K. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NARAYAN, ANAND P.
2014-05-16 Assigned to THOMAS, JOHN K. reassignment THOMAS, JOHN K. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JAIN, PRASHANT
2014-05-16 Assigned to RAMBUS INC. reassignment RAMBUS INC. CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED ON REEL 031788 FRAME 0971. ASSIGNOR(S) HEREBY CONFIRMS THE NUNC PRO TUNC ASSIGNMENT EFFECTIVE 3/30/2011. Assignors: OLSON, ERIC S.
2014-05-16 Assigned to THOMAS, JOHN K. reassignment THOMAS, JOHN K. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GRAHAM, GREG
2014-05-19 Assigned to TENSORCOMM, INC. reassignment TENSORCOMM, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: THOMAS, JOHN K.
2014-05-19 Assigned to THOMAS, JOHN K. reassignment THOMAS, JOHN K. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MEYER, DAVID
2014-05-19 Assigned to RAMBUS INC. reassignment RAMBUS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TENSORCOMM, INC.
This application is a continuation of U.S. patent application Ser. No. 11/858,074, entitled “Methods for managing alignment and latency in interference cancellation,” and filed Sep. 19, 2007; which (1) claims priority to U.S. Patent Application No. 60/845,594, entitled “Calculation of constant processing latency in a system with two locked clocks,” and filed on Sep. 19, 2006; (2) claims priority to U.S. Patent Application No. 60/845,595, entitled “Latency and Clock Frequency Reduction Using Data Reuse in Interference Cancellation for Coded Systems,” and filed Sep. 19, 2006; (3) claims priority to U.S. Patent Application No. 60/846,213, entitled “Real Time Implementation Techniques for Interference Cancellation,” and filed Sep. 21, 2006; and (4) is a continuation-in-part of U.S. patent application Ser. No. 11/103,138, entitled “Serial cancellation receiver design for a coded signal processing engine,” and filed on Apr. 11, 2005, now U.S. Pat. No. 7,359,465, which is a divisional of (a) U.S. patent application Ser. No. 10/247,836, entitled “Serial cancellation receiver design for a coded signal processing engine,” and filed on Sep. 20, 2002, now U.S. Pat. No. 7,158,559, and claims priority to (b) U.S. Patent Application No. 60/354,093, entitled “A Parallel CSPE Based Receiver for Communication Signal Processing,” and filed Feb. 5, 2002, (c) U.S. Patent Application No. 60/348,106, entitled “Serial Receiver Design for a Coded Signal Processing Engine,” and filed Jan. 14, 2002, (d) U.S. Patent Application No. 60/333,143, entitled “Method and Apparatus to Compute the Geolocation of a Communication Device Using Orthogonal Projection Methods,” and filed Nov. 27, 2001, (e) U.S. Patent Application No. 60/331,480, entitled “Construction of an Interference Matrix for a Coded Signal Processing Engine,” and filed Nov. 16, 2001; (f) U.S. Patent Application No. 60/326,199, entitled “Interference Cancellation in a Signal,” and filed Oct. 2, 2001; and (g) U.S. Provisional Patent Application No. 60/325,215, entitled “An Apparatus for Implementing Projections in Signal Processing Applications,” and filed Sep. 28, 2001. The entirety of each of the foregoing patents, patent applications, and patent application publications is incorporated by reference herein.
This application also incorporates by reference in their entirety U.S. patent application Ser. No. 09/988,218, entitled “Interference Cancellation In a Signal,” and filed Nov. 19, 2001, now U.S. Pat. No. 6,711,219; U.S. Patent Application No. 60/251,432, entitled “Architecture for Acquiring, Tracking and Demodulating Pseudorandom Coded Signals in the Presence of Interference,” and filed Dec. 4, 2000; U.S. patent application Ser. No. 09/988,219, entitled “A Method and Apparatus for Implementing Projections in Signal Processing Applications,” and filed Nov. 19, 2001, now U.S. Pat. No. 6,856,945; U.S. patent application Ser. No. 09/612,602, entitled “Rake receiver for spread spectrum signal demodulation,” and filed Jul. 7, 2000, now U.S. Pat. No. 6,430,216; and U.S. patent application Ser. No. 09/137,183, entitled “Printed circuit board socket,” and filed Aug. 20, 1998, now U.S. Pat. No. 5,928,035.
Δo′=Δo=Δp
The A/D converter at the front end of the receiver samples data at a rate higher than the chipping rate. The higher sampling rate is denoted as N×, while the chip rate is denoted as 1×. The sample rate (N×) is converted to the chip rate (1×) before the interference estimation process which uses 1× data. The N× data is accompanied with chip enable indicators at the chips of a finger. The chip enable indicators can be used to pick 1× data from an N× stream of data. The 1× data stream is then aligned to its symbol boundaries before the symbol and interference estimation process. The interference estimates stay at the 1× rate till the input of the interpolator. The interpolator creates N× data samples from the 1× data samples, creating an N× data stream for all fingers. Using RAM 100, the 1× input data to the interpolator was aligned to the closest chip point. Any left over sample level alignment is performed using delay lines on the N× data stream at the output of the interpolator. The interference removal can be performed at the sample level (N×) data rate. The interference removed data can then be stripped back to 1× data rate using stored chip enable indicators corresponding to the un-canceled data. Alternatively, the chip enable indicators can be regenerated using the symbol boundary information per finger. The interference removed 1× rate data can be sent out to the rake receiver or used in another iteration of interference cancellation.
1. An apparatus configured for generating an interference suppressed signal, comprising:
one or more power estimators configured for computing power estimates of components of a received signal;
a control block coupled to the one or more power estimators configured to determine an order of suppression of the components of a received signal based at least in part on the power estimates; and
one or more processing fingers coupled to the control block configured for generating at least one interference suppressed signal stream;
wherein the one or more processing fingers comprises at least one Hadamard transform module configured to compute the amplitudes of a plurality of channels.
2. An apparatus configured for generating an interference suppressed signal, comprising:
wherein the one or more processing fingers comprises a de-spreader configured for despreading an input signal.
3. A receiver for a wireless communication system, said communication system comprising:
a control processor configured for receiving a signal y having one or more data parameters, said control processor configured for selecting which of the one or more data parameters to send to each of one or more fingers, the one or more fingers comprising at least one search finger and at least one tracking finger;
at least one correlator residing in said at least one tracking finger, said at least one correlator being configured to correlate said signal y with a reference signal sn; and
a Coded Signal Processing Engine (CSPE) residing in said at least one tracking finger and configured for performing interference suppression in the signal y, said CSPE configured for generating a projection from the signal y, signal y comprising, a spread signal matrix si of the source of interest, signals of other interfering sources s1, s2, s3 . . . , sp; and noise n.
4. The receiver recited in claim 3, wherein the receiver is further configured to divide the signal y into yi channel and a yQ channel.
5. The receiver recited in claim 4, wherein said at least one search finger is configured in the yi channel to multiply a pilot Walsh code with a short code to generate a first reference signal if the Walsh code is non-zero.
6. The receiver recited in claim 5, wherein said at least one search finger is further configured to multiply the first reference signal by an orthogonal projection matrix to generate a second reference signal with at least one interference signal removed.
7. The receiver recited in claim 6, wherein said at least one search finger is further configured to multiply the second reference signal with the signal yi to generate an intermediate signal.
8. The receiver recited in claim 7, wherein said at least one search finger is further configured to correlate the intermediate signal by summing the product of yi and the second reference signal over a correlation length N to generate a first one or more summation signals.
9. The receiver recited in claim 8 wherein in the yQ channel, said at least one search finger is further configured to multiply a pilot Walsh code with a short code to generate a first reference signal if the Walsh code is non-zero.
10. The receiver recited in claim 9, wherein said at least one search finger is further configured to multiply the first reference signal by a respective orthogonal projection matrix to generate a second reference signal having at least one interference signal removed.
11. The receiver recited in claim 10, wherein said at least one search finger is further configured to multiply the second reference signal with the signal yQ to generate a second intermediate signal.
12. The receiver recited in claim 11, wherein said at least one search finger is further configured to correlate the second intermediate signal by summing the product of yQ and the second reference signal over a correlation length N in said summer to generate a second one or more summation signals.
13. The receiver recited in claim 12, wherein said at least one search finger is further configured to process the first one or more summation signals and the second one or more summation signals to select a strongest summation signal.
US13/076,332 2001-09-28 2011-03-30 Serial cancellation receiver design for a coded signal processing engine Active 2022-10-11 US8374299B2 (en)
US32521501P true 2001-09-28 2001-09-28
US32619901P true 2001-10-02 2001-10-02
US33148001P true 2001-11-16 2001-11-16
US33314301P true 2001-11-27 2001-11-27
US34810602P true 2002-01-15 2002-01-15
US35409302P true 2002-02-05 2002-02-05
US13/076,332 US8374299B2 (en) 2001-09-28 2011-03-30 Serial cancellation receiver design for a coded signal processing engine
US20110182330A1 US20110182330A1 (en) 2011-07-28
US8374299B2 true US8374299B2 (en) 2013-02-12
US10/247,836 Active 2022-10-22 US7158559B2 (en) 2002-01-15 2002-09-20 Serial cancellation receiver design for a coded signal processing engine
US11/103,138 Active 2023-10-24 US7359465B2 (en) 2001-09-28 2005-04-11 Serial cancellation receiver design for a coded signal processing engine
US13/076,332 Active 2022-10-11 US8374299B2 (en) 2001-09-28 2011-03-30 Serial cancellation receiver design for a coded signal processing engine
AU (1) AU2003205117A1 (en)
WO (1) WO2003060546A2 (en)
JP4952979B2 (en) * 2006-04-27 2012-06-13 独立行政法人理化学研究所 Signal separating apparatus, a signal separation method, and program
TW201022959A (en) * 2008-10-30 2010-06-16 Ibm Method, device, computer program and computer program product for determining a representation of a signal
EP0610989A2 (en) 1993-02-05 1994-08-17 Philips Patentverwaltung GmbH Radio system with space diversity transmitter/receiver
US20060217080A1 (en) * 2005-03-25 2006-09-28 The Mitre Corporation High-quality detection based on sequential interference cancellation techniques
2002-09-20 US US10/247,836 patent/US7158559B2/en active Active
2003-01-13 WO PCT/US2003/000928 patent/WO2003060546A2/en active Application Filing
2003-01-13 AU AU2003205117A patent/AU2003205117A1/en not_active Abandoned
2005-04-11 US US11/103,138 patent/US7359465B2/en active Active
2011-03-30 US US13/076,332 patent/US8374299B2/en active Active
Corrected Response dated Apr. 13, 2011 to the Office Action mailed Feb. 22, 2011 re U.S. Appl. No. 11/858,074. 8 Pages.
Information Disclosure Statement submitted Apr. 7, 2011 re U.S. Appl. No. 11/858,074. 7 Pages.
Kaplan, Elliott D., Editor, "Understanding GPS-Principles and Applications," Artech House, Norwood MA, 1996, pp. 152-236. (Provided publication missing pp. 83-151 of cited reference.) 46 pages.
Kaplan, Elliott D., Editor, "Understanding GPS—Principles and Applications," Artech House, Norwood MA, 1996, pp. 152-236. (Provided publication missing pp. 83-151 of cited reference.) 46 pages.
Notice of Allowance and Fee(s) Due dated May 13, 2011 re U.S. Appl. No. 11/858,074 includes Information Disclosure Statement. 18 Pages.
Office Action with filing date of Sep. 19, 2007, and mail date of Sep. 15, 2010, re U.S. Appl. No. 11/858,074, includes Notice of References Cited. 7 pages.
Office Action with mail date of Feb. 22, 2011 re U.S. Appl. No. 11/858,074. 7 Pages.
Price, et al., "A Communication Technique for Multipath Channels," Proceedings of the IRE, vol. 46, The Institute of Radio Engineers, New York, NY, US, 1958. 16 pages.
Rappaport, Theodore S., Editor, "Wireless Communications—Principles & Practice," Prentice Hall, Upper Saddle River, NJ, 1996, pp. 518-533. 14 pages.
Response dated Apr. 12, 2011 to the Office Action mailed Feb. 22, 2011 re U.S. Appl. No. 11/858,074. 8 Pages.
Response dated Nov. 19, 2010 to the Office Action mailed Sep. 15, 2010 re U.S. Appl. No. 11/858,074. 8 Pages.
Response to Restriction Requirement and Amendment dated Jul. 26, 2010 re U.S. Appl. No. 11/858,074. 4 pages.
Scharf, Louis L., "Statistical Signal Processing—Detection, Estimation, and Time Series Analysis," Addison-Wesley Publishing Company, 1991, pp. 23-75 and 103-178. 74 pages.
Viterbi, Andrew J., "CDMA—Principles of Spread Spectrum Communication," Addison-Wesley Publishing Company, Reading, MA, 1995, pp. 11-75 and 179-233. 66 pages.
WO2003060546A2 (en) 2003-07-24
US20050180496A1 (en) 2005-08-18
US7158559B2 (en) 2007-01-02
US7359465B2 (en) 2008-04-15
US20110182330A1 (en) 2011-07-28
WO2003060546A3 (en) 2004-09-23
US20040022302A1 (en) 2004-02-05
AU2003205117A8 (en) 2003-07-30
AU2003205117A1 (en) 2003-07-30
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