Source: http://www.google.es/patents/US7297612?dq=flatulence
Timestamp: 2014-04-24 01:43:30
Document Index: 422363175

Matched Legal Cases: ['Application No. 01', 'Application No. 01', 'Application No. 01', 'Application No. 02', 'Application No. 02', 'Application No. 98', 'Application No. 98']

Patente US7297612 - Methods for forming strained-semiconductor-on-insulator device structures by ... - Google PatentesB�squeda Im�genes Maps Play YouTube Noticias Gmail Drive M�s »Iniciar sesi�n B�squeda avanzada de patentesPatentesThe benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....http://www.google.es/patents/US7297612?utm_source=gb-gplus-sharePatente US7297612 - Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes B�squeda avanzada de patentes N�mero de publicaci�nUS7297612 B2Tipo de publicaci�nConcesi�n N�mero de solicitudUS 11/127,508 Fecha de publicaci�n20 Nov 2007 Fecha de presentaci�n12 May 2005 Fecha de prioridad7 Jun 2002TarifaPagadasTambi�n publicado comoUS6995430, US7259388, US7414259, US7420201, US7588994, US7838392, US8026534, US8586452, US20040005740, US20050189563, US20050199954, US20050205934, US20050212061, US20050218453, US20080128751, US20110073908, US20110318893, US20140051230 N�mero de publicaci�n11127508, 127508, US 7297612 B2, US 7297612B2, US-B2-7297612, US7297612 B2, US7297612B2 InventoresThomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald Cesionario originalAmberwave Systems CorporationExportar citaBiBTeX, EndNote, RefManCitas de patentes (101), Otras citas (99), Citada por (6), Clasificaciones (66), Eventos legales (3) Enlaces externos: USPTO, Cesi�n de USPTO, EspacenetMethods for forming strained-semiconductor-on-insulator device structures by use of cleave planesUS 7297612 B2 Resumen The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
Citas de patentes Patente citada Fecha de presentaci�n Fecha de publicaci�n Solicitante T�tuloUS401004527 Abr 19761 Mar 1977Ruehrwein Robert AProcess for production of III-V compound crystalsUS470430220 Ago 19863 Nov 1987Commissariat A L'energie AtomiqueProcess for producing an insulating layer buried in a semiconductor substrate by ion implantationUS47107881 Dic 19861 Dic 1987Licentia Patent-Verwaltungs-GmbhModulation doped field effect transistor with doped Six Ge1-x -intrinsic Si layeringUS49690313 Feb 19836 Nov 1990Hitachi, Ltd.Semiconductor devices and method for making the sameUS49874626 Ene 198722 Ene 1991Texas Instruments IncorporatedPower MISFETUS499097927 Abr 19895 Feb 1991Eurosil Electronic GmbhNon-volatile memory cellUS499777620 Jun 19905 Mar 1991International Business Machines Corp.Complementary bipolar transistor structure and method for manufactureUS501368129 Sep 19897 May 1991The United States Of America As Represented By The Secretary Of The NavyMethod of producing a thin silicon-on-insulator layerUS508987227 Abr 199018 Feb 1992North Carolina State UniversitySelective germanium deposition on silicon and resulting structuresUS509176718 Mar 199125 Feb 1992At&T Bell LaboratoriesArticle comprising a lattice-mismatched semiconductor heterostructureUS51555716 Ago 199013 Oct 1992The Regents Of The University Of CaliforniaComplementary field effect transistors having strained superlattice structureUS51660843 Sep 199124 Nov 1992Motorola, Inc.Process for fabricating a silicon on insulator field effect transistorUS517758310 Ene 19915 Ene 1993Kabushiki Kaisha ToshibaHeterojunction bipolar transistorUS52022841 Dic 198913 Abr 1993Hewlett-Packard CompanySelective and non-selective deposition of Si.sub.1-x Ge.sub.x on a Si subsrate that is partially masked with SiO.sub.2US520786430 Dic 19914 May 1993Bell Communications ResearchLow-temperature fusion of dissimilar semiconductorsUS520818212 Nov 19914 May 1993Kopin CorporationDislocation density reduction in gallium arsenide on silicon heterostructuresUS521211026 May 199218 May 1993Motorola, Inc.Method for forming isolation regions in a semiconductor deviceUS522141324 Abr 199122 Jun 1993At&T Bell LaboratoriesMethod for making low defect density semiconductor heterostructure and devices made therebyUS52408761 Jun 199231 Ago 1993Harris CorporationMethod of fabricating SOI wafer with SiGe as an etchback film in a BESOI processUS524119713 Sep 199131 Ago 1993Hitachi, Ltd.Transistor provided with strained germanium layerUS524284727 Jul 19927 Sep 1993North Carolina State University At RaleighSelective deposition of doped silion-germanium alloy on semiconductor substrateUS525044517 Ene 19925 Oct 1993Texas Instruments IncorporatedDiscretionary gettering of semiconductor circuitsUS528508618 Jun 19928 Feb 1994At&T Bell LaboratoriesSemiconductor devices with low dislocation defectsUS529143912 Sep 19911 Mar 1994International Business Machines CorporationSemiconductor memory cell and memory array with inversion layerUS529845221 Feb 199229 Mar 1994International Business Machines CorporationMethod and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layersUS531045119 Ago 199310 May 1994International Business Machines CorporationMethod of forming an ultra-uniform silicon-on-insulator layerUS531695831 May 199031 May 1994International Business Machines CorporationMethod of dopant enhancement in an epitaxial silicon layer by using germaniumUS53468481 Jun 199313 Sep 1994Motorola, Inc.Method of bonding silicon and III-V semiconductor materialsUS537456415 Sep 199220 Dic 1994Commissariat A L'energie AtomiqueProcess for the production of thin semiconductor material filmsUS53995228 Sep 199321 Mar 1995Fujitsu LimitedMethod of growing compound semiconductorUS5405802 *25 May 199411 Abr 1995Canon Kabushiki KaishaProcess of fabricating a semiconductor substrateUS541367930 Jun 19939 May 1995The United States Of America As Represented By The Secretary Of The NavyMethod of producing a silicon membrane using a silicon alloy etch stop layerUS54242439 Sep 199413 Jun 1995Fujitsu LimitedMethod of making a compound semiconductor crystal-on-substrate structureUS54260699 Abr 199220 Jun 1995Dalsa Inc.Method for making silicon-germanium devices using germanium implantationUS54263168 Jun 199420 Jun 1995International Business Machines CorporationTriple heterojunction bipolar transistorUS54398436 Sep 19948 Ago 1995Canon Kabushiki KaishaMethod for preparing a semiconductor substrate using porous siliconUS54422059 Ago 199315 Ago 1995At&T Corp.Semiconductor heterostructure devices with strained semiconductor layersUS546124329 Oct 199324 Oct 1995International Business Machines CorporationSubstrate for tensilely strained semiconductorUS546125010 Ago 199224 Oct 1995International Business Machines CorporationSiGe thin film or SOI MOSFET and method for making the sameUS546288311 Abr 199431 Oct 1995International Business Machines CorporationMethod of fabricating defect-free silicon on an insulating substrateUS547681314 Nov 199419 Dic 1995Kabushiki Kaisha ToshibaMethod of manufacturing a bonded semiconductor substrate and a dielectric isolated bipolar transistorUS547903327 May 199426 Dic 1995Sandia CorporationComplementary junction heterostructure field-effect transistorUS548466421 Ene 199416 Ene 1996Fujitsu LimitedHetero-epitaxially grown compound semiconductor substrateUS55232438 Jun 19944 Jun 1996International Business Machines CorporationMethod of fabricating a triple heterojunction bipolar transistorUS55235921 Feb 19944 Jun 1996Hitachi, Ltd.Semiconductor optical device, manufacturing method for the same, and opto-electronic integrated circuit using the sameUS553471320 May 19949 Jul 1996International Business Machines CorporationComplementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layersUS553636123 Ene 199516 Jul 1996Canon Kabushiki KaishaProcess for preparing semiconductor substrate by bonding to a metallic surfaceUS55407854 Abr 199430 Jul 1996International Business Machines CorporationFabrication of defect free silicon on an insulating substrateUS554812814 Dic 199420 Ago 1996The United States Of America As Represented By The Secretary Of The Air ForceDirect-gap germanium-tin multiple-quantum-well electro-optical devices on silicon or germanium substratesUS557204315 May 19955 Nov 1996The Furukawa Electric Co., Ltd.Schottky junction device having a Schottky junction of a semiconductor and a metalUS559652713 Feb 199521 Ene 1997Nippon Steel CorporationElectrically alterable n-bit per cell non-volatile memory with reference cellsUS560787629 Dic 19954 Mar 1997Xerox CorporationFabrication of quantum confinement semiconductor light-emitting devicesUS56173515 Jun 19951 Abr 1997International Business Machines CorporationThree-dimensional direct-write EEPROM arrays and fabrication methodsUS56309055 Jun 199520 May 1997The Regents Of The University Of CaliforniaMethod of fabricating quantum bridges by selective etching of superlattice structuresUS56591877 Jun 199519 Ago 1997International Business Machines CorporationLow defect density/arbitrary lattice constant heteroepitaxial layersUS56839343 May 19964 Nov 1997Motorola, Inc.Enhanced mobility MOSFET device and methodUS569886913 Sep 199516 Dic 1997Kabushiki Kaisha ToshibaInsulated-gate transistor having narrow-bandgap-sourceUS570542122 Nov 19956 Ene 1998Mitsubishi Materials CorporationA SOI substrate fabricating methodUS571477719 Feb 19973 Feb 1998International Business Machines CorporationSi/SiGe vertical junction field effect transistorUS572862316 Mar 199517 Mar 1998Nec CorporationMethod of bonding a III-V group compound semiconductor layer on a silicon substrateUS57395678 Nov 199414 Abr 1998Wong; Chun Chiu D.Highly compact memory device with nonvolatile vertical transistor memory cellUS575989819 Dic 19962 Jun 1998International Business Machines CorporationProduction of substrate for tensilely strained semiconductorUS577734718 Jul 19977 Jul 1998Hewlett-Packard CompanyVertical CMOS digital multi-valued restoring logic deviceUS578661216 Abr 199628 Jul 1998Mitsubishi Denki Kabushiki KaishaSemiconductor device comprising trench EEPROMUS57866148 Abr 199728 Jul 1998Taiwan Semiconductor Manufacturing Co., Ltd.Separated floating gate for EEPROM applicationUS579267930 Ago 199311 Ago 1998Sharp Kabushiki KaishaMethod for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implantUS58083444 Feb 199715 Sep 1998International Business Machines CorporationSingle-transistor logic and CMOS invertersUS582157730 Nov 199213 Oct 1998International Business Machines CorporationGraded channel field effect transistorUS584741916 Sep 19978 Dic 1998Kabushiki Kaisha ToshibaSi-SiGe semiconductor device and method of fabricating the sameUS586383018 Sep 199526 Ene 1999Commissariat A L'energie AtomiqueProcess for the production of a structure having a thin semiconductor film on a substrateUS587707031 May 19972 Mar 1999Max-Planck SocietyMethod for the transfer of thin layers of monocrystalline material to a desirable substrateUS588298726 Ago 199716 Mar 1999International Business Machines CorporationSmart-cut process for the production of thin semiconductor material filmsUS589176927 Feb 19986 Abr 1999Motorola, Inc.Method for forming a semiconductor device having a heteroepitaxial layerUS59067086 Dic 199525 May 1999Lawrence Semiconductor Research Laboratory, Inc.Silicon-germanium-carbon compositions in selective etch processesUS590695130 Abr 199725 May 1999International Business Machines CorporationStrained Si/SiGe layers on insulatorUS591247925 Jul 199715 Jun 1999Sony CorporationHeterojunction bipolar semiconductor deviceUS59230463 Sep 199713 Jul 1999Kabushiki Kaisha ToshibaQuantum dot memory cellUS594356019 Abr 199624 Ago 1999National Science CouncilMethod to fabricate the thin film transistorUS596381716 Oct 19975 Oct 1999International Business Machines CorporationBulk and strained silicon on insulator using local selective oxidationUS59666228 Oct 199712 Oct 1999Lucent Technologies Inc.Process for bonding crystalline substrates with different crystal latticesUS599367710 Ene 199730 Nov 1999Commissariat A L'energie AtomiqueProcess for transferring a thin film from an initial substrate onto a final substrateUS59988079 Sep 19977 Dic 1999Siemens AktiengesellschaftIntegrated CMOS circuit arrangement and method for the manufacture thereofUS601313418 Feb 199811 Ene 2000International Business Machines CorporationAdvance integrated chemical vapor deposition (AICVD) for semiconductor devicesUS601355315 Jul 199811 Ene 2000Texas Instruments IncorporatedZirconium and/or hafnium oxynitride gate dielectricUS601356319 Feb 199811 Ene 2000Silicon Genesis CorporationControlled cleaning processUS602025214 May 19971 Feb 2000Commissariat A L'energie AtomiqueMethod of producing a thin layer of semiconductor materialUS603397410 Ago 19997 Mar 2000Silicon Genesis CorporationMethod for controlled cleaving processUS603399516 Sep 19977 Mar 2000Trw Inc.Inverted layer epitaxial liftoff processUS60580449 Dic 19982 May 2000Kabushiki Kaisha ToshibaShielded bit line sensing scheme for nonvolatile semiconductor memoryUS605989513 May 19999 May 2000International Business Machines CorporationStrained Si/SiGe layers on insulatorUS607491920 Ene 199913 Jun 2000Advanced Micro Devices, Inc.Method of forming an ultrathin gate dielectricUS609659030 Jun 19981 Ago 2000International Business Machines CorporationScalable MOS field effect transistorUS610355930 Mar 199915 Ago 2000Amd, Inc. (Advanced Micro Devices)Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabricationUS610359711 Abr 199715 Ago 2000Commissariat A L'energie AtomiqueMethod of obtaining a thin film of semiconductor materialUS61035993 Jun 199815 Ago 2000Silicon Genesis CorporationPlanarizing technique for multilayered substratesUS610765323 Jun 199822 Ago 2000Massachusetts Institute Of TechnologyControlling threading dislocation densities in Ge on Si using graded GeSi layers and planarizationUS61112674 May 199829 Ago 2000Siemens AktiengesellschaftCMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layerUS611775021 Dic 199812 Sep 2000France TelecomProcess for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectivelyUS61304534 Ene 199910 Oct 2000International Business Machines CorporationFlash memory structure with floating gate in vertical trenchUS613379925 Feb 199917 Oct 2000International Business Machines CorporationVoltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETSUS6774010 *25 Ene 200110 Ago 2004International Business Machines CorporationTransferable device-containing layer for silicon-on-insulator applications* Citada por examinadorOtras citasReferencia1"2 Bit/Cell EEPROM Cell Using Band to Band Tunneling for Data Read-Out," IBM Technical Disclosure Bulletin, vol. 35, No. 4B (Sep. 1992) pp. 136-140.2Armstrong et al., "Design of Si/SiGe Heterojunction Complementary Metal-Oxide-Semiconductor Transistors," IEDM Technical Digest (1995) pp. 761-764.3Armstrong, "Technology for SiGe Heterostructure-Based CMOS Devices", Ph.D Thesis, Massachusetts Institute of Technology (1999) pp. 1-154.4Augusto et al., "Proposal for a New Process Flow for the Fabrication of Silicon-Based Complementary MOD-MOSFETs without Ion Implantation," Thin Solid Films, vol. 294, No. 1-2 (1997) pp. 254-258.5Barradas et al., "RBS analysis of MBE-grown SiGe/(001) Si heterostructures with thin, high Ge content SiGe channels for HMOS transistors," Modern Physics Letters B (2001) (abstract).6Batterman, "Hillocks, Pits, and Etch Rate in Germanium Crystals," Journal of Applied Physics, vol. 28, No. 11 (Nov. 1957), pp. 1236-1241.7Bohg, "Ethylene Diamine-Pyrocatechol-Water Mixture Shows Etching Anomaly in Boron-Doped Silicon," Journal of the Electrochemical Society, vol. 118, No. 2 (Feb. 1971), pp. 401-402.8Borenstein et al., "A New Ultra-Hard Etch-Stop Layer for High Precision Micromachining," Proceedings of the 1999 12<SUP>th </SUP>IEEE International Conference on Micro Electro Mechanical Systems (MEMs) (Jan. 17-21, 1999) pp. 205-210.9Bouillon et al., "Search for the optimal channel architecture for 0.18/0.12 mum bulk CMOS Experimental study," IEEE (1996) pp. 21.2.1-21.2.4.10Brunner et al., "Molecular beam epitaxy growth and thermal stability of Si<SUB>1-x</SUB>Ge<SUB>x </SUB>layers on extremely thin silicon-on-insulator substrates," Thin Solid Films, vol. 321 (1998), pp. 245-250.11Bufler et al., "Hole transport in strained Si<SUB>1-x</SUB>Ge<SUB>x </SUB>alloys on Sil-yGey substrates," Journal of Applied Physics, vol. 84, No. 10 (Nov. 15, 1998) pp. 5597-5602.12Burghartz et al., "Microwave Inductors and Capacitors in Standard Multilevel Interconnect Silicon Technology", IEEE Transactions on Microwave Theory and Techniques, vol. 44, No. 1 (Jan. 1996) pp. 100-104.13Canaperi et al., "Preparation of a relaxed Si-Ge layer on an insulator in fabricating high-speed semiconductor devices with strained epitaxial films," International Business Machines Corporation, USA (2002) (abstract).14Carlin et al., "High Efficiency GaAs-on-Si Solar Cells with High Voc Using Graded GeSi Buffers," IEEE (2000) pp. 1006-1011.15Chang et al., "Selective Etching of SiGe/Si Heterostructures," Journal of the Electrochemical Society, No. 1 (Jan. 1991) pp. 202-204.16Chen et al., "The Band Model and the Etching Mechanism of Silicon in Aqueous KOH," Journal of the Electrochemical Society, vol. 142, No. 1 (Jan. 1995), pp. 170-176.17Cheng et al., "Electron Mobility Enhancement in Strained-Si n-MOSFETs Fabricated on SiGe-on-Insulator (SGO1) Substrates," IEEE Electron Device Letters, vol. 22, No. 7 (Jul. 2001) pp. 321-323.18Cheng et al., "Relaxed Silicon-Germanium on Insulator Substrate by Layer Transfer," Journal of Electronic Materials, vol. 30, No. 12 (2001) pp. L37-L39.19Cullis et al, "Growth ripples upon strained SiGe epitaxial layers on Si and misfit dislocation interactions," Journal of Vacuum Science and Technology A, vol. 12, No. 4 (Jul./Aug. 1994) pp. 1924-1931.20Currie et al., "Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates," J. Vac. Sci. Technol. B., vol. 19, No. 6 (Nov./Dec. 2001) pp. 2268-2279.21Currie et al., "Controlling Threading Dislocation in Ge on Si Using Graded SiGe Layers and Chemical-Mechanical Polishing," vol. 72 No. 14 (Apr. 6, 1998) pp. 1718-1720.22Desmond et al., "The Effects of Process-Induced Defects on the Chemical Selectivity of Highly Doped Boron Etch Stops in Silicon," Journal of the Electrochemical Society, vol. 141, No. 1 (Jan. 1994), pp. 178-184.23Eaglesham et al., "Dislocation-Free Stranski-Krastanow Growth of Ge on Si(100)," Physical Review Letters, vol. 64, No. 16 (Apr. 16, 1990) pp. 1943-1946.24Ehman et al., "Morphology of Etch Pits on Germanium Studied by Optical and Scanning Electron Microscopy," Journal of Applied Physics, vol. 41, No. 7 (Jun. 1970), pp. 2824-2827.25Examination Report for European Patent Application No. 01 973 651.1-1528, dated Mar. 22, 2004, 3 pages.26Examination Report for European Patent Application No. 01 973 651.1-1528, dated Nov. 13, 2004, 9 pages.27Examination Report for European Patent Application No. 01 989 893.1-1235, dated Aug. 16, 2004, 5 pages.28Examination Report for European Patent Application No. 02 709 406.9-2203, dated Mar. 24, 2005, 5 pages.29Examination Report for European Patent Application No. 02 709 406.9-2203, dated May 11, 2004, 3 pages.30Examination Report for European Patent Application No. 98 931 529.6-2203, dated Jan. 10, 2002, 4 pages.31Examination Report for European Patent Application No. 98 931 529.6-2203, dated May 9, 2003, 5 pages.32Feij�o et al., "Epitaxial Si-Ge Etch Stop Layers with Ethylene Diamine Pyrocatechol for Bonded and Etchback Silicon-on-Insulator," Journal of Electronic Materials, vol. 23, No. 6 (Jun. 1994) pp. 493-496.33Feij�o et al., "Etch Stop Barriers in Silicon Produced by Ion Implantation of Electrically Non-Active Species," Journal of the Electrochemical Society, vol. 139, No. 8 (Aug. 1992), pp. 2309-2313.34Finne et al., "A Water-Amine-Complexing Agent System for Etching Silicon," Journal of the Electrochemical Society, vol. 114, No. 9 (Sep. 1967), pp. 965-970.35Fischetti et al., "Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys," J. Appl. Phys., vol. 80, No. 4 (Aug. 15, 1996) pp. 2234-2252.36Fischetti, "Long-range Coulomb interactions in small Si devices. Part II. Effective electron mobility in thin-oxide structures," Journal of Applied Physics, vol. 89, No. 2 (Jan. 15, 2001) pp. 1232-1250.37Fitzgerald et al., "Dislocation dynamics in relaxed graded composition semiconductors," Materials Science and Engineering B67 (1999) pp. 53-61.38Fitzgerald et al., "Dislocations in Relaxed SiGe/Si Heterostructures," Physica Status Solidi A, Applied Research, Berlin, DE, vol. 171, Nr. 1, p. 227-238, Jan. 16, 1999.39Fitzgerald et al., "Relaxed Ge<SUB>x</SUB>Si<SUB>1-x </SUB>structures for III-V integration with Si and high mobility two-dimensional electron gases in Si," AT&T Bell Laboratories, Murray Hill, NJ 07974 (1992) American Vacuum Society, pp. 1807-1819.40Fitzgerald et al., "Totally Relaxed Ge<SUB>x</SUB>Si<SUB>1-x </SUB>Layers with Low Threading Dislocation Densities Grown on Si Substrates," Applied Physics Letters, vol. 59, No. 7 (Aug. 12, 1991) pp. 811-813.41Fitzgerald, "GeSi/Si Nanostructures," Annual Review of Materials Science, vol. 25 (1995), pp. 417-454.42Frank, "Orientation-Dependent Dissolution of Germanium," Journal of Applied Physics, vol. 31, No. 11 (Nov. 1960), pp. 1996-1999.43Fukatsu, "SiGe-based semiconductor-on-insulator substrate created by low-energy separation-by-implanted-oxygen," Applied Physics Letters, vol. 72, No. 26 (Jun. 29, 1998), pp. 3485-3487.44Gannavaram, et al., "Low Temperature (<=800� C.) Recessed Junction Selective Silicon-Germanium Source/Drain Technology for sub-70 nm CMOS," IEEE International Electron Device Meeting Technical Digest, (2000), pp. 437-440.45Garone et al., "Silicon vapor phase epitaxial growth catalysis by the presence of germane," Applied Physics Letters, vol. 56, No. 13 (Mar. 26, 1990) pp. 1275-1277.46Ge et al., "Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering," IEEE International Electron Devices Meeting Technical Digest, (2003) pp. 73-76.47Ghandi et al., "Chemical Etching of Germanium," Journal of the Electrochemical Society, vol. 135, No. 8 (Aug. 1988), pp. 2053-2054.48Ghani et al., "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors," IEEE International Electron Devices Meeting Technical Digest, (2003), 978-980.49Godbey et al., "A Si<SUB>0.7</SUB>Ge<SUB>0.3 </SUB>strained-layer etch stop for the generation of thin layer undoped silicon," Applied Physics Letters, vol. 56, No. 4 (Jan. 22, 1990), pp. 373-375.50Godbey et al., (1990) "Fabrication of Bond and Etch-Back Silicon Insulator Using a Strained SI<SUB>0.7</SUB>GE<SUB>0.3 </SUB>Layer as an Etch Stop," Journal of the Electrical Society, vol. 137, No. 10 (Oct. 1990) pp. 3219-3223.51Gray and Meyer, "Phase-Locked Loops", Analysis and Design of Analog Integrated Circuits (1984) pp. 605-632.52Grillot et al., "Acceptor diffusion and segregation in (Al<SUB>x</SUB>Ga<SUB>1-x</SUB>)<SUB>0.5</SUB>In<SUB>0.5</SUB>P heterostructures," Journal of Applied Physics, vol. 91, No. 8 (2002), pp. 4891-4899.53Gr�tzmacher et al., "Ge segregation in SiGe/Si heterostructures and its dependence on deposition technique and growth atmosphere," Applied Physics Letters, vol. 63, No. 18 (Nov. 1, 1993) pp. 2531-2533.54Hackbarth et al., "Alternatives to thick MBE-grown relaxed SiGe buffers," Thin Solid Films, vol. 369, No. 1-2 (Jul. 2000) pp. 148-151.55Hackbarth et al., "Strain relieved SiGe buffers for Si-based heterostructure field-effect transistors," Journal of Crystal Growth, vol. 201/202 (1999) pp. 734-738.56Halsall et al., "Electron diffraction and Raman studies of the effect of substrate misorientation on ordering in the AlGalnP system," Journal of Applied Physics, vol. 85, No. 1 (1999), pp. 199-202.57Hamada et al., "A New Aspect of Mechanical Stress Effects in Scaled MOS Devices," IEEE Transactions on Electron Devices, vol. 38, No. 4 (Apr. 1991), pp. 895-900.58Herzog et al., "SiGe-based FETs: buffer issues and device results," Thin Solid Films, vol. 380 (2000) pp. 36-41.59Herzog et al., "X-Ray Investigation of Boron- and Germanium-Doped Silicon Epitaxial Layers," Journal of the Electrochemical Society, vol. 131, No. 12 (Dec. 1984), pp. 2969-2974.60H�ck et al., "Carrier mobilities in modulation doped Si<SUB>1-x</SUB>Ge<SUB>x </SUB>heterostructures with respect to FET applications," Thin Solid Films, vol. 336 (1998) pp. 141-144.61H�ck et al., "High hole mobility in Si<SUB>0.17 </SUB>Ge<SUB>0.83 </SUB>channel metal-oxide-semiconductor field-effect transistors grown by plasma-enhanced chemical vapor deposition," Applied Physics Letters, vol. 76, No. 26 (Jun. 26, 2000) pp. 3920-3922.62H�ck et al., "High performance 0.25 mum p-type Ge/SiGe MODFETs," Electronics Letters, vol. 34, No. 19 (Sep. 17, 1998) pp. 1888-1889.63Holmes, "The Orientation Dependence of Etching Effects on Germanium Crystals," Acta Metallurgica, vol. 7, No. 4 (Apr. 1959), pp. 283-290.64Hsu et al., "Surface morphology of related Ge<SUB>x</SUB>Si<SUB>1-x </SUB>films," Appl. Phys. Lett., vol. 61, No. 11 (1992), pp. 1293-1295.65Huang et al., "Isolation Process Dependence of Channel Mobility in Thin-Film SOI Devices," IEEE Electron Device Letters, vol. 17, No. 6 (Jun. 1996), pp. 291-293.66Huang et al., "LOCOS-Induced Stress Effects on Thin-Film SOI Devices," IEEE Transactions on Electron Devices, vol. 44, No. 4 (Apr. 1997), pp. 646-650.67Huang et al., "The Impact of Scaling Down to Deep Submicron on CMOS RF Circuits", IEEE Journal of Solid-State Circuits, vol. 33, No. 7, Jul. 1998, pp. 1023-1036.68Huang et al., (2001) "Carrier Mobility enhancement in strained Si-on-insulatoir fabricated by wafer bonding", 2001 Symposium on VLSI Technology, Digest of Technical Papers, pp. 57-58.69Huang, et al., "Reduction of Source/Drain Series Resistance and Its Impact on Device Performance for PMOS Transistors with Raised Si<SUB>1-x</SUB>Ge<SUB>x </SUB>Source/Drain", IEEE Electron Device Letters, vol. 21, No. 9, (Sep. 2000) pp. 448-450.70Hunt et al., "Highly Selective Etch Stop by Stress Compensation for Thin-Film BESOI," 1990 IEEE/SOI Technology Conference, (Oct. 2-4, 1990), pp. 145-146.71IBM Technical Disclosure Bulletin, vol. 32, No. 8A, Jan. 1990, "Optimal Growth Technique and Structure for Strain Relaxation of Si-Ge Layers on Si Substrates", pp. 330-331.72Iida et al., "Thermal behavior of residual strain in silicon-on-insulator bonded wafer and effects on electron mobility," Solid-State Electronics, vol. 43 (1999), pp. 1117-1120.73International Search Report for Patent Application No. PCT/US 98/13076, dated Oct. 27, 1998, 2 pages.74International Search Report for Related International Application No. PCT/US/18007, Jan. 5, 2004.75Ishikawa et al., "SiGe-on-insulator substrate using SiGe alloy grown Si(001)," Applied Physics Letters, vol. 75, No. 7 (Aug. 16, 1999) pp. 983-985.76Ismail et al., "Modulation-doped n-type Si/SiGe with inverted interface," Appl. Phys. Lett., vol. 65, No. 10 (Sep. 5, 1994) pp. 1248-1250.77Ismail, "Si/SiGe High-Speed Field-Effect Transistors," Electronic Devices Meeting, Washington, D.C. (Dec. 10, 1995) pp. 20.1.1-20.1.4.78Ito et al., "Mechanical Stress Effect on Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design," IEEE International Electron Devices Meeting Technical Digest, (2000), pp. 247-250.79Jaccodine, "Use of Modified Free Energy Theorems to Predict Equilibrium Growing and Etching Shapes," Journal of Applied Physics, vol. 33, No. 8 (Aug. 1962), pp. 2643-2647.80Kearney et al., "The effect of alloy scattering on the mobility of holes in a Si<SUB>1-x</SUB>Ge<SUB>x </SUB>quantum well," Semicond. Sci Technol., vol. 13 (1998) pp. 174-180.81Kern, "Chemical Etching of Silicon, Germanium, Gallium, Arsenide, and Gallium Phosphide," RCA Review, vol. 39 (Jun. 1978), pp. 278-308.82Kim et al., "A Fully Integrated 1.9-GHz CMOS Low-Noise Amplifier," IEEE Microwave and Guided Wave Letters, vol. 8, No. 8 (Aug. 1998) pp. 293-295.83Klauk et al., "Thermal stability of undoped strained Si channel SiGe heterostructures," Applied Physics Letter, No. 68, Apr. 1, 1996, pp. 1975-1977.84Koester et al., "Extremely High Transconductance Ge/Si<SUB>0.4</SUB>Ge<SUB>0.6 </SUB>p-MODFET's Grown by UHV-CVD," IEEE Electron Device Letters, vol. 21, No. 3 (Mar. 2000) pp. 110-112.85K�nig et al., "p-Type Ge-Channel MODGET's with High Transconductance Grown on Si Substrates," IEEE Electron Device Letters, vol. 14, No. 4 (Apr. 1993) pp. 205-207.86K�nig et al., "SiGe HBTs and HFETs," Solid-State Electronics, vol. 38, No. 9 (1995) pp. 1595-1602.87Kuznetsov et al., "Technology for high-performance n-channel SiGe modulation-doped field-effect transistors," J. Vac. Sci. Technol., B 13(6) (Nov./Dec. 1995) pp. 2892-2896.88Lang et al., "Bulk Micromachining of Ge for IR Gratings," Journal of Micromechanics and Microengineering, vol. 6, No. 1 (Mar. 1996), pp. 46-48.89Langdo et al., (2002) "Preparation of Novel SiGe-free Strained Si on Insulator Substrates" IEEE International SOI Conference, pp. 211-212 (XP002263057).90Larson, "Integrated Circuit Technology Options for RFIC's-Present Status and Future Directions", IEEE Journal of Solid-State Circuits, vol. 33, No. 3, Mar. 1998, pp. 387-399.91Leancu et al., "Anisotropic Etching of Germanium," Sensors and Actuators, A46-47 (1995), pp. 35-37.92Lee et al., "CMOS RF Integrated Circuits at 5 GHz and Beyond", Proceedings of the IEEE, vol. 88, No. 10 (Oct. 2000) pp. 1560-1571.93Lee et al., "Strained Ge channel p-type metal-oxide-semiconductor field-effect transistors grown on Si<SUB>1-x</SUB>Ge<SUB>x</SUB>/Si virtual substrates," Applied Physics Letters, vol. 79, No. 20 (Nov. 12, 2001) pp. 3344-3346.94Lee et al., "Strained Ge channel p-type MOSFET's fabricated on Si<SUB>1-x</SUB>Ge<SUB>x</SUB>/Si virtual substrates," Mat. Res. Soc. Symp. Proc., vol. 686 (2002) pp. A1.9.1-A1.9.5.95LeGoues et al., "Relaxation of SiGe thin films grown on Si/SiO<SUB>2 </SUB>substrates," Applied Physics Letters, vol. 75, No. 11 (Jun. 1, 1994), pp. 7240-7246.96Lehmann et al., "Implanted Carbon: An Effective Etch-Stop in Silicon," Journal of the Electrochemical Society, vol. 138, No. 5 (May 1991), pp. 3-4.97Leitz et al., "Channel Engineering of SiGe-Based Heterostructures for High MOSFETs," Mat. Res. Soc. Symp. Proc., vol. 686 (2002) pp. A3.10.1-A3.10.6.98Leitz et al., "Dislocation glide and blocking kinetics in compositionally graded SiGe/Si," Journal of Applied Physics, vol. 90, No. 6 (Sep. 15, 2001) pp. 2730-2736.99Leitz et al., "Hole mobility enhancements in strained Si/Sil-yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si<SUB>1-x</SUB>Ge<SUB>x </SUB>(x<y) virtual substrates," Applied Physics Letters, vol. 79, No. 25 (Dec. 17, 2001) pp. 4246-4248. Citada por Patente citante Fecha de presentaci�n Fecha de publicaci�n Solicitante T�tuloUS7381622 *14 Nov 20063 Jun 2008Advanced Micro Devices, Inc.Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch processUS7442599 *15 Sep 200628 Oct 2008Sharp Laboratories Of America, Inc.Silicon/germanium superlattice thermal sensorUS7838392 *20 Nov 200723 Nov 2010Taiwan Semiconductor Manufacturing Company, Ltd.Methods for forming III-V semiconductor device structuresUS8586452 *7 Sep 201119 Nov 2013Taiwan Semiconductor Manufacturing Company, Ltd.Methods for forming semiconductor device structuresUS20110303291 *17 Feb 201015 Dic 2011Robert Cameron HarperFormation of thin layers of semiconductor materialsUS20110315664 *19 May 201129 Dic 2011Michel BruelMethod for treating a part made from a decomposable semiconductor material* Citada por examinadorClasificaciones Clasificaci�n de EE.UU.438/458, 257/E21.127, 257/E21.129, 257/E21.415, 257/E29.297, 257/E21.371, 257/E21.564, 257/E21.442, 257/E29.298, 257/E21.57, 257/E21.703, 257/E29.295, 257/E21.567, 257/E21.568, 438/455, 257/E21.448, 257/E21.121, 257/E27.112, 438/459 Clasificaci�n internacionalH01L21/331, H01L27/12, H01L21/84, H01L21/762, H01L21/336, H01L21/20, H01L21/337, H01L21/30, H01L29/786 Clasificaci�n cooperativaH01L21/76254, H01L27/1203, H01L21/84, H01L29/785, H01L29/7842, H01L29/78687, H01L21/76259, H01L21/28518, H01L29/78684, H01L29/66916, H01L29/41783, H01L29/165, H01L29/66628, H01L29/66242, H01L29/78603, H01L21/76264, H01L29/66772, H01L29/66787, H01L29/7849, H01L21/76256, H01L21/76275 Clasificaci�n europeaH01L29/66M6T2H, H01L29/66M6T6F15C, H01L29/66M6T6T3, H01L29/78R, H01L21/285B4A, H01L29/66M6T6F11D3, H01L29/417D12R, H01L29/78R7, H01L21/762D8D, H01L21/762D8F, H01L29/786G2, H01L29/786A, H01L29/786G, H01L21/762D20, H01L21/762D8B, H01L21/84, H01L27/12BEventos legales FechaC�digoEventoDescripci�n20 May 2011FPAYFee paymentYear of fee payment: 426 Ene 2010ASAssignmentOwner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AMBERWAVE SYSTEMS CORPORATION;REEL/FRAME:023848/0183Effective date: 200911229 Jun 2005ASAssignmentOwner name: AMBERWAVE SYSTEMS CORPORATION, NEW HAMPSHIREFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LOCHTEFELD, ANTHONY J.;LANGDO, THOMAS A.;HAMMOND, RICHARD;AND OTHERS;REEL/FRAME:016667/0014;SIGNING DATES FROM 20030815 TO 20050418GirarImagen originalP�gina principal de Google - Sitemap - Descargas masivas de USPTO - Pol�tica de privacidad - Condiciones de servicio - Acerca de Google Patentes - Danos tu opini�nDatos proporcionados por IFI CLAIMS Patent Services©2012 Google