Source: http://www.google.de/patents/US5917225
Timestamp: 2013-06-20 01:05:19
Document Index: 417245852

Matched Legal Cases: ['Application No. 3', 'Application No. 4', 'Application No. 4', 'Application No. 4', 'Application No. 4', 'Application No. 3']

Patent US5917225 - Insulated gate field effect transistor having specific dielectric structures - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr » Erweiterte Patentsuche | Webprotokoll | Anmelden Erweiterte Patentsuche PatenteIn a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate electrode and the gate insulating film to prevent invasion of movable...http://www.google.de/patents/US5917225?utm_source=gb-gplus-sharePatent US5917225 - Insulated gate field effect transistor having specific dielectric structures Ver�ffentlichungsnummerUS5917225 APublikationstypErteilung Anmeldenummer08/721,052 Ver�ffentlichungsdatum29. Juni 1999Eingetragen26. Sept. 1996 Priorit�tsdatum5. M�rz 1992Auch ver�ffentlicht unterCN1051882C, CN1081022A Ver�ffentlichungsnummer08721052, 721052, US 5917225 A, US 5917225A, US-A-5917225, US5917225 A, US5917225A ErfinderYasuhiko Takemura, Shunpei Yamazaki, Hongyong ZhangUrspr�nglich Bevollm�chtigterSemiconductor Energy Laboratory Co., Ltd.Patentzitate (47), Nichtpatentzitate (2), Referenziert von (59), Klassifizierungen (19) Externe Links: USPTO, USPTO-Zuordnung, EspacenetInsulated gate field effect transistor having specific dielectric structuresUS 5917225 A Zusammenfassung In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate electrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate electrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion. Further, an aluminum oxide or silicon nitride is formed as an etching stopper between the gate electrode and the gate insulating film or between the substrate and the layer on the substrate, so that the over-etching can be prevented and the flatness of the element can be improved. In addition, a contact is formed in no consideration of the concept "contact hole".
What is claimed is: 1. An insulated gate thin film transistor comprising:a semiconductor layer comprising crystalline silicon formed on an insulating surface of a substrate; a channel region formed within said semiconductor layer; source and drain regions formed within said semiconductor layer with said channel region therebetween; a first insulating film comprising silicon oxide formed on said channel region; a second insulating film formed on said first insulating film; and a gate electrode formed over said channel region with said first and second insulating films interposed therebetween, said transistor characterized in that said second insulating film comprises a material selected from the group consisting of silicon nitride and aluminum oxide, and that said second insulating film extends beyond side edges of said gate electrode but does not cover a major surface of said source and drain regions, wherein said first insulating film is thicker than said second insulating film. 2. The transistor of claim 1 wherein said material of the second insulating film is silicon nitride.
3. The insulated gate thin film transistor according to claim 1 wherein the thickness of said first insulating film is 50 to 200 nm.
4. The insulated gate thin film transistor according to claim 3 wherein the thickness of said second insulating film is 2 to 50 nm.
5. An insulated gate thin film transistor comprising:a semiconductor layer comprising crystalline silicon formed on an insulating surface of a substrate; a channel region formed within said semiconductor layer; source and drain regions formed within said semiconductor layer with said channel region therebetween; a first insulating film comprising silicon oxide formed on said channel region; a second insulating film formed on said first insulating film; and a gate electrode formed over said channel region with said first and second insulating films interposed therebetween, said transistor characterized in that said second insulating film comprises a material selected from the group consisting of silicon nitride and aluminum oxide, and that said first insulating film is thicker than said second insulating film. 6. The transistor of claim 5 wherein said material of the second insulating film is silicon nitride.
7. The transistor of claim 5 wherein said first and second insulating films are coextensive with each other.
8. The insulated gate thin film transistor according to claim 5 wherein the thickness of said first insulating film is 50 to 200 nm.
9. The insulated gate thin film transistor according to claim 8 wherein the thickness of said second insulating film is 2 to 50 nm.
10. An insulated gate thin film transistor comprising:a semiconductor layer comprising crystalline silicon formed on an insulating surface of a substrate; a channel region formed within said semiconductor layer; source and drain regions formed within said semiconductor layer with said channel region therebetween; a first insulating film comprising silicon oxide formed on said channel region; a second insulating film formed on said first insulating film wherein said first insulating film is thicker than said second insulating film; and a gate electrode formed over said channel region with said first and second insulating films interposed therebetween, said transistor characterized in that said second insulating film comprises a material selected from the group consisting of silicon nitride and aluminum oxide, and that said second insulating film extends beyond side edges of said gate electrode but does not cover a major surface of said source and drain regions while said first insulating film covers the major surface of said source and drain regions except for contact portions thereof. 11. The transistor of claim 10 wherein said material of the second insulating film is silicon nitride.
12. The insulated gate thin film transistor according to claim 10 wherein the thickness of said first insulating film is 50 to 200 nm.
13. The insulated gate thin film transistor according to claim 12 wherein the thickness of said second insulating film is 2 to 50 nm.
14. An insulated gate field effect transistor comprising:a semiconductor layer comprising crystalline silicon formed on an insulating surface of a substrate; a channel region formed within said semiconductor layer; source and drain regions formed within said semiconductor layer with said channel region therebetween; a gate insulating film formed on said semiconductor layer; and a gate electrode formed over said channel region with said gate insulating film interposed therebetween, said transistor characterized in that said gate insulating film comprises at least a first insulating film comprises silicon oxide and a second insulating film comprises silicon nitride which is thinner than said first insulating film, and that at least said second insulating film extends beyond side edges of said gate electrode to cover a part of said source and drain regions. 15. The insulated gate field effect transistor according to claim 14 wherein the thickness of said first insulating film is 50 to 200 nm.
16. The insulated gate field effect transistor according to claim 15 wherein the thickness of said second insulating film is 2 to 50 nm.
17. An insulated gate field effect transistor comprising:a semiconductor layer comprising crystalline silicon formed on an insulating surface of a substrate; a channel region formed within said semiconductor layer; source and drain regions formed within said semiconductor layer with said channel region therebetween; a gate insulating film formed on said semiconductor layer; and a gate electrode formed over said channel region with said gate insulating film interposed therebetween, said transistor characterized in that said gate insulating film comprises at least a first insulating film comprises silicon oxide and a second insulating film comprises silicon nitride, that said first insulating film is thicker than said second insulating film. 18. The insulated gate field effect transistor according to claim 17 wherein the thickness of said first insulating film is 50 to 200 nm.
19. The insulated gate field effect transistor according to claim 18 wherein the thickness of said second insulating film is 2 to 50 nm.
20. An insulated gate field effect transistor comprising:a semiconductor layer comprising crystalline silicon formed over a substrate; a channel region formed within said semiconductor layer; a pair of impurity regions formed within said semiconductor layer with said channel region therebetween; a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween, wherein at least said second insulating film extends beyond side edges of the gate electrode, wherein said first insulating film is thicker than said second insulating film. 21. An insulated gate field effect transistor according to claim 20 wherein said pair of impurity regions are source and drain regions of the transistor.
22. An insulated gate field effect transistor according to claim 20 wherein said gate electrode is located over said channel region.
23. An insulated gate field effect transistor according to claim 20 wherein said silicon nitride film is in direct contact with said gate electrode.
24. The insulated gate field effect transistor according to claim 20 wherein the thickness of said first insulating film is 50 to 200 nm.
25. The insulated gate field effect transistor according to claim 24 wherein the thickness of said second insulating film is 2 to 50 nm.
26. An insulated gate field effect transistor comprising:a semiconductor layer comprising crystalline silicon formed over a substrate; a channel region formed within said semiconductor layer; a pair of impurity regions formed within said semiconductor layer with said channel region therebetween; a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween, wherein said first insulating film is thicker than said second insulating film. 27. An insulated gate field effect transistor according to claim 26 wherein said pair of impurity regions are source and drain regions of the transistor.
28. An insulated gate field effect transistor according to claim 26 wherein said gate electrode is located over said channel region.
29. An insulated gate field effect transistor according to claim 26 wherein said silicon nitride film is in direct contact with said gate electrode.
30. The insulated gate field effect transistor according to claim 26 wherein the thickness of said first insulating film is 50 to 200 nm.
31. The insulated gate field effect transistor according to claim 30 wherein the thickness of said second insulating film is 2 to 50 nm.
32. An insulated gate field effect transistor comprising:a semiconductor layer comprising crystalline silicon formed over a substrate; a channel region formed within said semiconductor layer; a pair of impurity regions formed within said semiconductor layer with said channel region therebetween; a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising aluminum oxide; and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween, wherein, said first insulating film is thicker than said second insulating film. 33. An insulated gate field effect transistor according to claim 32 wherein said pair of impurity regions are source and drain regions of the transistor.
34. An insulated gate field effect transistor according to claim 32 wherein said gate electrode is located over said channel region.
35. An insulated gate field effect transistor according to claim 34 wherein said silicon nitride film is in direct contact with said gate electrode.
36. An insulated gate field effect transistor comprising:a semiconductor layer comprising crystalline silicon formed over a substrate; a channel region formed within said semiconductor layer; a pair of impurity regions formed within said semiconductor layer with said channel region therebetween; a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween, wherein at least said second insulating film extends beyond side edges of the gate electrode, wherein said first insulting film is thicker than said second insulating film and the thickness of said first insulating film is 50 to 200 nm. 37. An insulated gate field effect transistor comprising:a semiconductor layer comprising crystalline silicon formed over a substrate; a channel region formed within said semiconductor layer; a pair of impurity regions formed within said semiconductor layer with said channel region therebetween; a gate insulating film adjacent to said semiconductor layer, including at least a first insulting film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween, wherein at least said second insulating film extends beyond side edges of the gate electrode, wherein said first insulating film is thicker than said second insulating film and the thickness of said second insulating film is 2 to 50 nm. 38. An insulated gate field effect transistor comprising:a semiconductor layer comprising crystalline silicon formed over a substrate; a channel region formed within said semiconductor layer; a pair of impurity regions formed within said semiconductor layer with said channel region therebetween; a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween, wherein said first insulating film is thicker than said second insulating film and the thickness of said first insulating film is 50 to 200 nm. 39. An insulated gate field effect transistor comprising:a semiconductor layer comprising crystalline silicon formed over a substrate; a channel region formed within said semiconductor layer; a pair of impurity regions formed within said semiconductor layer with said channel region therebetween; a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween, wherein said first insulating film is thicker than said second insulating film and the thickness of said second insulating film is 2 to 50 nm. 40. The insulated gate field effect transistor according to claim 32 wherein the thickness of said first insulating film is 50 to 200 nm while the thickness of said second insulating film is 2 to 50 nm.
41. The insulated gate field effect transistor according to claim 20 wherein said semiconductor film is 20 to 100 nm thick.
42. The insulated gate field effect transistor according to claim 26 wherein said semiconductor film is 20 to 100 nm thick.
43. The insulated gate field effect transistor according to claim 32 wherein said semiconductor film is 20 to 100 nm thick.
This is a divisional application of Ser. No. 08/460,560, filed Jun. 2, 1995 now abandoned, which is a divisional application of Ser. No. 08/037,162 filed Mar. 25, 1993 now U.S. Pat. No. 5,468,987, which is a continuation-in-part of Ser. No. 07/846,164 filed Mar. 5, 1992 now U.S. Pat. No. 5,289,030.
As is apparent from FIG. 12, the planar type of TFT is so designed as to be very flat over its whole body. This structure is very favorable for a case where it is used as an active element for a liquid crystal display device. This is because in the liquid crystal display device, the thickness of a liquid crystal layer is about 5 to 6 μm, and it is required to control the thickness with accuracy of .+-1 μm as a whole. Therefore, an element structure having high unevenness (a large number of recesses and projections) causes ununiformity of electric field, so that not only the characteristic of the element is deteriorated, but also the element itself suffers a mechanical damage.
SUMMARY OF THE INVENTION An object of this invention is to provide an insulating gate type of semiconductor device (an insulated gate field effect transistor) and a producing method therefor in which an over-etching phenomenon is depressed to prohibit the diffusion of foreign elements from a substrate and flatness of the device is further improved.
The silicon nitride film serves to block movable ions such as natrium, etc., and thus prevent the movable ions from invading from the gate electrode and other portions into a channel region. In addition, silicon nitride has higher conductivity than silicon oxide which is usually used for the gate insulating film, and thus the silicon nitride film also serves to prevent an excessive voltage from being applied between the gate electrode and the semiconductor region (channel region) beneath the gate electrode, so that breakdown of the gate insulating film is prevented.
A reference numeral 701 represents a substrate, and a reference numeral 702 represents a silicon nitride layer (first silicon nitride layer) which is formed to prevent diffusion or foreign elements of the substrate into the TFT. A reference numeral 703 represents a silicon oxide layer serving as a sealer for preventing back-leak of the TFT. A reference numeral 704 represents a semiconductor region, and after the formation of the semiconductor region 704, a gate insulating film 705 and the aluminum oxide or silicon nitride layer (second aluminum oxide or silicon nitride layer) are formed. Thereafter, a wiring 707 and a gate electrode 708 are formed of a first metal layer. In this embodiment, an oxide is formed by the anodic oxidation method around the wiring and the electrode to strengthen insulating and heat-resistance properties. However, like the prior art, the formation of the oxide may be eliminated. Subsequently, an impurity region is formed in the semiconductor region 704 in self-alignment.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a process for producing a semiconductor device (cross-sectional view) according to this invention;
FIG. 11 is a cross-sectional view or a semiconductor device in a conventional method;
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Preferred embodiments according to this invention will be described with reference to the accompanying drawings.
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 101. This glass has high strain temperature, but contains a large amount of lithium and natrium. Therefore, in order to prevent invasion of these movable ions from the substrate, a silicon nitride film 102 was formed in thickness of 10 to 50 nm on the substrate by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film serving as a sealer was formed in thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600 crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process by the photolithography and the reactive ion etching (RIE) method, thereby forming islandish semiconductor regions 104 (for N-channel TFT) and 105 (for P-channel TFT) as shown in FIG. 1(A).
Through these processes, the structure as shown in FIG. 1(C) was obtained. Naturally, the portion doped with the impurity by the ion injection method had low crystallinity, and thus it was substantially in a non-crystal state (amorphous state, or a polycrystal state close to the amorphous state). Therefore, a laser anneal treatment was conducted to restore crystallinity at the portion. This process may be carried out by a heat annealing treatment at 600 to 850 condition as disclosed in Japanese Patent Application No. 3-237100 for example was adopted.
FIG. 2 shows an embodiment in which this invention was applied to a TFT having two-layered channel which was invented by the inventor of this application, et.al., and described in applications filed on Feb. 25, 1992 entitled "THIN FILM INSULATING GATE TYPE OF SEMICONDUCTOR DEVICE AND A PRODUCING METHOD THEREFOR" (applicant: Semiconductor Energy Laboratory Co., Ltd, docketing numbers: P002042-01 to P002044-03).
Next, the impurity doping, the formation of an interlayer insulator and formation of a contact hole were performed in the same manner as the Embodiment 1 (that is, an insulating layer (an interlayer insulating layer) was formed on the oxide film 305 and a second contact hole was formed in this insulating layer by selectively etching the insulating layer, and then a second metal wiring 307 was formed of aluminum as a third conductor layer. At this time, the second metal wiring 307 was connected with the gate wiring (the first conductor layer) at the position 308 of FIG. 3 (FIG. 3(E)) through a contact which comprises the first contact hole and the second contact hole. The gate electrode/wirings 303 may comprise tantalum instead of aluminum. The second conductor layer comprises a material different from that of the gate electrode/wirings 303 in any case. For example, the second conductor layer comprises chromium, gold, titanium, silicon, indium oxide, titanium oxide or zinc oxide.
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 1. This glass has high strain temperature, but contains a large amount of lithium and natrium. Therefore, in order to prevent invasion of these movable ions from the substrate, a silicon nitride film 2 was formed in thickness of 10 to 50 nm on the substrate by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film serving as a sealer was formed in thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600 for 12 to 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process by the photolithography and the reactive ion etching (RIE) method, thereby forming islandish semiconductor regions 4 (for N-channel TFT) and 105 (for P-channel TFT) as shown in FIG. 4(A).
Through these processes, the structure as shown in FIG. 4(D) was obtained. Naturally, the portion doped with the impurity by the ion injection method had low crystallinity, and thus it was substantially in a non-crystal state (amorphous state, or a polycrystal state close to the amorphous state). Therefore, a laser anneal treatment was conducted to restore crystallinity at the portion. This process may be carried out by a heat annealing treatment at 600 to 850 condition as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 to 450 C. under hydrogen atmosphere (1 to 700 torr, preferably 500 to 700 torr), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.).
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 401. A silicon nitride film 402 was formed in thickness of 10 to 50 nm on the substrate by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film 403 serving as a sealer was formed in thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600 at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process to form islandish semiconductor regions 404 (for N-channel TFT) and 405 (for P-channel TFT) as shown in FIG. 5(A).
Through these processes, the structure as shown in FIG. 5(D) was obtained. In the laser doping technique, unlike the Embodiment 4, no laser annealing process or no heat annealing process is required because the injection of the impurities and the annealing treatment are simultaneously carried out. After the laser doping treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 to 450 atmosphere (1 to 700 torr or 500 to 700 torr), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.).
Through the manner as described above, the outline or the element was shaped. Afterwards, similarly in the ordinary manner, the interlayer insulator 418 was formed by the sputtering method for silicon oxide film formation, and a hole for electrode was formed by a well-known photolithography to expose the surface of the semiconductor region or the gate electrode/wiring. Finally, a second metal film (aluminum or chrome) was selectively formed to form electrode/wirings 419 to 421. Through these processes, NTFT 422 and PTFT 423 were formed.
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 501. A silicon nitride film 502 was formed in thickness of 10 to 50 nm on the substrate by the plasma CVD method or the low pressure CVD method. Further, a silicon oxide film 503 serving as a sealer was formed in thickness of 100 to 800 nm by the sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness or 20 to 100 nm by the plasma CVD method, and annealed at 600 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process to form islandish semiconductor regions 504 (for N-channel TFT) and 505 (for P-channel TFT) as shown in FIG. 6(A).
Through these processes, the structure as shown in FIG. 6(D) was obtained. Naturally, the crystallinity of the portions to which the impurities were injected by the ion injection was extremely low, and these portions were substantially in a non-crystal state (amorphous state or polycrystal state close to the amorphous state). Therefore, the crystallinity was restored by the laser annealing treatment. This process may be replaced by the heat annealing treatment at 600 to 850 annealing treatment as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. Here, no short-wavelength ultraviolet rays below 250 nm wavelength is passed through the silicon nitride film 507, so that XeCl laser (308 nm wavelength) or XeF laser (351 nm wavelength) was used.
After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 to 450 atmosphere (1 to 700 torr or 500 to 700 torr), to thereby depress lattice defects (dangling bond, etc.). Actually, delivery of hydrogen was little carried out between the inside of the semiconductor region and the outside thereof because the silicon nitride film 507 exists. Therefore, a large amount of hydrogen atoms are simultaneously injected into the semiconductor region in the plasma doping method, and on the other hand, in the ion injection method, a process of injecting hydrogen atoms is separately required. If the amount of hydrogen atoms is insufficient, hydrogen atoms are required to be separately doped even in the plasma doping method.
Through the manner as described above, the outline of the element was shaped. Afterwards, similarly in the ordinary manner, the interlayer insulator 518 was formed by the sputtering method for silicon oxide film formation, and a hole for electrode was formed by a well-known photolithography to expose the surface of the semiconductor region or the gate electrode/wiring. Finally, a second metal film (aluminum or chrome) was selectively formed to form electrode/wirings 519 to 521. Through these processes, NTFT 522 and PTFT 523 were formed.
FIG. 5 shows an embodiment in which this invention was applied to the TFT having two-layered channel which was invented by the inventor of this application, et.al., and described in applications filed on Feb. 25, 1992 entitled "THIN FILM INSULATING GATE TYPE OF SEMICONDUCTOR DEVICE AND A PRODUCING METHOD THEREFOR" (applicant: Semiconductor Energy Laboratory Co., Ltd, docketing numbers: P002042-01 to P002044-03).
An N--O glass produced by Nippon Electric Glass Co., Ltd was used as a substrate 1001. This glass has high strain temperature, however, contains a large amount of lithium and natrium. Therefore, in order to prevent invasion of these movable ions from the substrate and in order to prevent the over-etching, an aluminum oxide film 1002 was formed on the substrate 1001 in thickness of 10 to 50 nm by an organic metal CVD method. Further, a silicon oxide film 1003 serving as a sealer was formed on the aluminum oxide film 1002 in thickness of 100 to 800 nm by the sputtering method. An amorphous silicon film was formed in thickness of 20 to 100 nm on the silicon oxide film 1003 by the plasma CVD method, and then annealed at 600 crystallized. The result was subjected to the patterning process by the photolithography and the reactive ion etching (RIE) method to form islandish semiconductor regions 1004.
Subsequently, N-type impurity was doped into the semiconductor region 1004 by the well-known ion injection method to form N-type impurity regions (source, drain) 1005 and 1006. In the manner as described above, the structure as shown in FIG. 13(A) was obtained. Naturally, the crystallinity at the portion doped with the impurities by the ion injection method was extremely low, and this portion was substantially in a non-crystal (amorphous state, or polycrystal state close to the amorphous state). Therefore, the crystallinity at the portion was restored by the laser annealing treatment. This process may be replaced by the heat annealing treatment at 600 to 850 as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 to 450 hydrogen atmosphere (1 to 700 torr, preferably 500 to 700 torr) to inject hydrogen atoms into the semiconductor region and depress the lattice defect (dangling bond, etc.).
Subsequently, the wet etching treatment using hydrochloric acid was conducted with the above mask 1011 on the interlayer insulator 1010 and the gate insulating film 1007 and the silicon oxide film 1003. The aluminum oxide film 1002 was exposed by etching them with the first wiring and the islandish semiconductor region 1004 as masks. However, the substrate was subjected to no etching treatment because the aluminum oxide 1002 functioned as a barrier. Therefore, the substrate was not exposed by virtue of the aluminum oxide 1002. In addition, silicon was not etched and thus each or the gate electrode 1009 and the semiconductor region 1004 was left as it was. The surface of the impurity regions of the semiconductor region were exposed. This state is shown in FIG. 13(C).
Subsequently, an aluminum or chrome film was formed, and then subjected to the patterning process to form as a second wiring wiring/electrode 1012 and 1013 in contact with a portion of the islandish semiconductor region 1004. At this time, the impurity region of the semiconductor region was exposed, and thus it was unnecessary to provide a contact. Further, a transparent electrode 1014 was formed of ITO. Through these processes, the semiconductor device was completed. The aluminum oxide film 1002 may be replaced by a silicon nitride film.
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 1101. A silicon nitride film 1102 was formed in thickness of 10 to 50 nm on the substrate by the plasma CVD method or the low pressure CVD method. Further, a silicon oxide film 1103 serving as a sealer was formed in thickness of 100 to 800 nm by the sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process to form islandish semiconductor regions 1104.
Thereafter, an aluminum film was formed by the sputtering method or the electron beam deposition method, and then subjected to a patterning process to form gate electrode/wirings 1107 to 1109. Further, current was supplied to the gate electrode/wirings 1107 to 1109 in the electrolyte to form aluminum oxide films 1110 to 1112 by the anodic oxidation method. The anodic oxidation condition as disclosed in Japanese Patent Application No. 4-30220 which was invented by the inventor of this application, et.al was adopted in this embodiment. Further, by the laser doping technique (Japanese Patent Application No. 3-283981) which was invented by the inventor of this application, et.al, N-type impurity was doped into the semiconductor region 1104, thereby forming an N-type impurity region (source, drain). The laser doping method requires no laser annealing treatment and no heat annealing treatment which were required for the Embodiment 8 because the injection of the impurities and the annealing treatment were simultaneously carried out. After the laser doping treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 to 450 500 to 700 torr), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.). This state is shown in FIG. 14(A).
Patentzitate Zitiertes PatentEingetragen Ver�ffentlichungsdatum Antragsteller TitelUS4015281 *5. M�rz 197129. M�rz 1977Hitachi, Ltd.MIS-FETs isolated on common substrateUS4042945 *14. Juli 197516. Aug. 1977Westinghouse Electric CorporationN-channel MOS transistorUS4468855 *4. Aug. 19824. Sept. 1984Fujitsu LimitedMethod of making aluminum gate self-aligned FET by selective beam annealing through reflective and antireflective coatingsUS4485393 *26. Mai 198127. Nov. 1984Tokyo Shibaura Denki Kabushiki KaishaSemiconductor device with selective nitride layer over channel stopUS4557036 *25. M�rz 198310. Dez. 1985Nippon Telegraph & Telephone Public Corp.Semiconductor device and process for manufacturing the sameUS4746628 *29. Aug. 198624. Mai 1988Sharp Kabushiki KaishaMethod for making a thin film transistorUS4866498 *20. Apr. 198812. Sept. 1989The United States Department Of EnergyIntegrated circuit with dissipative layer for photogenerated carriersUS4905066 *19. Apr. 198927. Febr. 1990Kabushiki Kaisha ToshibaThin-film transistorUS5041888 *16. Juli 199020. Aug. 1991General Electric CompanyInsulator structure for amorphous silicon thin-film transistorsUS5051794 *3. Juli 198924. Sept. 1991Kabushiki Kaisha ToshibaNon-volatile semiconductor memory device and method for manufacturing the sameUS5079605 *27. Nov. 19897. Jan. 1992Texas Instruments IncorporatedSilicon-on-insulator transistor with selectable body node to source node connectionUS5097311 *5. Juli 198917. M�rz 1992Kabushiki Kaisha ToshibaSemiconductor deviceUS5146301 *14. Okt. 19888. Sept. 1992Sharp Kabushiki KaishaTerminal electrode structure of a liquid crystal panel displayUS5177577 *5. Juli 19915. Jan. 1993Hitachi, Ltd.Liquid crystal display device with TFT's each including a Ta gate electrode and an anodized Al oxide filmUS5225356 *30. Dez. 19916. Juli 1993Nippon Telegraph & Telephone CorporationMethod of making field-effect semiconductor device on sotUS5237188 *27. Nov. 199117. Aug. 1993Kabushiki Kaisha ToshibaSemiconductor device with nitrided gate insulating filmUS5240868 *20. Dez. 199131. Aug. 1993Samsung Electronics Co., Ltd.Method of fabrication metal-electrode in semiconductor deviceUS5272361 *1. Nov. 199121. Dez. 1993Semiconductor Energy Laboratory Co., Ltd.Field effect semiconductor device with immunity to hot carrier effectsUS5289030 *5. M�rz 199222. Febr. 1994Semiconductor Energy Laboratory Co., Ltd.Semiconductor device with oxide layerUS5328861 *29. Okt. 199212. Juli 1994Casio Computer Co., Ltd.Method for forming thin film transistorUS5412493 *24. Sept. 19932. Mai 1995Sony CorporationLiquid crystal display device having LDD structure type thin film transistors connected in seriesUS5422293 *18. Dez. 19926. Juni 1995Casio Computer Co., Ltd.Method for manufacturing a TFT panelUS5424230 *29. Juli 199413. Juni 1995Casio Computer Co., Ltd.Method of manufacturing a polysilicon thin film transistorUS5583366 *26. Jan. 199510. Dez. 1996Seiko Epson CorporationActive matrix panelJP1274117A * Titel nicht verf�gbarJP2159730A * Titel nicht verf�gbarJP2210420A * Titel nicht verf�gbarJP2216129A * Titel nicht verf�gbarJP2228042A * Titel nicht verf�gbarJP3038278A * Titel nicht verf�gbarJP3165575A * Titel nicht verf�gbarJP3217059A * Titel nicht verf�gbarJP4299864A * Titel nicht verf�gbarJP4360580A * Titel nicht verf�gbarJP5881972A * Titel nicht verf�gbarJP58023479A * Titel nicht verf�gbarJP58032466A * Titel nicht verf�gbarJP58106861A * Titel nicht verf�gbarJP58115864A * Titel nicht verf�gbarJP58124273A * Titel nicht verf�gbarJP58158967A * Titel nicht verf�gbarJP60245173A * Titel nicht verf�gbarJP62124769A * Titel nicht verf�gbarJP62214669A * Titel nicht verf�gbarJP63009978A * Titel nicht verf�gbarJP63070832A * Titel nicht verf�gbarJP63178560A * Titel nicht verf�gbar* Vom Pr�fer zitiertNichtpatentzitateReferenz1IBM Technical Disclosure Bulletin "Method To Fabricate CMOS On Insulator", vol. 28, No. 7, Dec. 1985, pp. 3120-3122, Dec. 1993.2 *IBM Technical Disclosure Bulletin Method To Fabricate CMOS On Insulator , vol. 28, No. 7, Dec. 1985, pp. 3120 3122, Dec. 1993.* Vom Pr�fer zitiert Referenziert von Zitiert von PatentEingetragen Ver�ffentlichungsdatum Antragsteller TitelUS6184616 *23. Dez. 19986. Febr. 2001Sony CorporationResistor electron gun for cathode-ray tube using the same and method of manufacturing resistorUS619145229. Sept. 199820. Febr. 2001Sanyo Electric Co., Ltd.Thin film transistor having a stopper layerUS6232622 *28. Sept. 199915. Mai 2001Sanyo Electric Co., Ltd.Semiconductor device with high electric field effect mobilityUS6243155 *19. Okt. 19985. Juni 2001Semiconductor Energy Laboratory Co., Ltd.Electronic display device having an active matrix display panelUS6265247 *15. Juni 199924. Juli 2001Sanyo Electric Co., Ltd.Thin-film transistor and manufacturing method for improved contact holeUS626573028. Sept. 199824. Juli 2001Sanyo Electric Co., Ltd.Thin-film transistor and method of producing the sameUS6284583 *26. Juni 19984. Sept. 2001Kabushiki Kaisha ToshibaSemiconductor device and method of manufacturing the sameUS632352829. Juli 199827. Nov. 2001Semiconductor Energy Laboratory Co,. Ltd.Semiconductor deviceUS6331443 *19. Nov. 199918. Dez. 2001Samsung Electronics Co., Ltd.Method for manufacturing a liquid crystal displayUS6441444 *14. Juli 199927. Aug. 2002Mitsubishi Denki Kabushiki KaishaSemiconductor device having a nitride barrier for preventing formation of structural defectsUS6462806 *29. Dez. 20008. Okt. 2002Semiconductor Energy Laboratory Co., Ltd.Electronic device having an active matrix display panelUS6479867 *29. Aug. 200112. Nov. 2002Hitachi, Ltd.Thin film transistorUS65382716. Juni 200125. M�rz 2003Kabushiki Kaisha ToshibaSemiconductor device and method of manufacturing the sameUS654882828. Sept. 199815. Apr. 2003Sanyo Electric Co., Ltd.Thin-film transistor and method of manufacturing thin-film transistor with tapered gate of 20 degrees or lessUS655541921. Dez. 200029. Apr. 2003Sanyo Electric Co., Ltd.Thin film transistor and manufacturing method of thin film transistorUS66136184. Apr. 20002. Sept. 2003Sanyo Electric Co., Ltd.Thin-film transistor and method of producing the sameUS6621103 *28. M�rz 200216. Sept. 2003Sanyo Electric Co., Ltd.Semiconductor device and active matrix type displayUS662445025. Jan. 199923. Sept. 2003Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the sameUS6709906 *19. Dez. 200023. M�rz 2004Semiconductor Energy Laboratory Co., Ltd.Method for producing semiconductor deviceUS682226118. Okt. 200123. Nov. 2004Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the sameUS685300427. Juli 20018. Febr. 2005Semiconductor Energy Laboratory Co., Ltd.Thin film transistor formed on a resin substrateUS686495018. Sept. 20028. M�rz 2005Semiconductor Energy Laboratory Co., Ltd.Electronic device with active matrix type display panel and image sensor functionUS68670753. M�rz 200315. M�rz 2005Shiro NakanishiManufacturing method of thin film transistor in which a total film thickness of silicon oxide films is definedUS697243522. Juni 20046. Dez. 2005Semiconductor Energy Laboratory Co., Ltd.Camera having display device utilizing TFTUS69798419. Sept. 200327. Dez. 2005Semiconductor Energy Laboratory Co., Ltd.Semiconductor integrated circuit and fabrication method thereofUS698219419. Apr. 20023. Jan. 2006Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the sameUS70425488. M�rz 20059. Mai 2006Semiconductor Energy Laboratory Co., Ltd.Image sensor having thin film transistor and photoelectric conversion elementUS704628218. Sept. 199816. Mai 2006Semiconductor Energy Laboratory Co., Ltd.Image sensor and image sensor integrated type active matrix type display deviceUS707827411. Juli 200318. Juli 2006Sanyo Electric Co., Ltd.Method of forming active matrix type display including a metal layer having a light shield functionUS7087963 *16. M�rz 20008. Aug. 2006Sanyo Electric Co., Ltd.Method of manufacturing thin film transistorUS71701388. Sept. 200430. Jan. 2007Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS71800926. Mai 200320. Febr. 2007Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS718999726. M�rz 200213. M�rz 2007Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the sameUS72534414. Febr. 20057. Aug. 2007Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS72658114. Mai 20064. Sept. 2007Semiconductor Energy Laboratory Co., Ltd.Integral-type liquid crystal panel with image sensor functionUS72861734. Mai 200623. Okt. 2007Semiconductor Energy Laboratory Co., Ltd.Image sensor and image sensor integrated type active matrix type display deviceUS73012097. Dez. 200627. Nov. 2007Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS741428821. Okt. 200519. Aug. 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having display deviceUS74463406. Aug. 20074. Nov. 2008Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS75256154. Sept. 200728. Apr. 2009Semiconductor Energy Laboratory Co., Ltd.Integral-type liquid crystal panel with image sensor function and pixel electrode overlapping photoelectric conversion elementUS756940830. Apr. 19974. Aug. 2009Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the sameUS757268525. Apr. 200611. Aug. 2009Sanyo Electric Co., Ltd.Method of manufacturing thin film transistorUS7573110 *24. Aug. 199911. Aug. 2009Semiconductor Energy Laboratory Co., Ltd.Method of fabricating semiconductor devicesUS761578631. Okt. 200710. Nov. 2009Semiconductor Energy Laboratory Co., Ltd.Thin film transistor incorporating an integrated capacitor and pixel regionUS76878092. Mai 200830. M�rz 2010Semiconductor Energy Laboratory Co., LtdMethod for producing a semiconductor integrated circuit including a thin film transistor and a capacitorUS770154117. Okt. 200620. Apr. 2010Semiconductor Energy Laboratory Co., Ltd.In-plane switching display device having electrode and pixel electrode in contact with an upper surface of an organic resin filmUS779111714. Aug. 20077. Sept. 2010Semiconductor Energy Laboratory Co., Ltd.Image sensor and image sensor integrated type active matrix type display deviceUS785510625. Jan. 200521. Dez. 2010Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the sameUS785962127. Apr. 200928. Dez. 2010Semiconductor Energy Laboratory Co., Ltd.Integral-type liquid crystal panel with image sensor functionUS791505819. Jan. 200629. M�rz 2011Semiconductor Energy Laboratory Co., Ltd.Substrate having pattern and method for manufacturing the same, and semiconductor device and method for manufacturing the sameUS795597521. Juli 20107. Juni 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor element and display device using the sameUS803065829. Sept. 20084. Okt. 2011Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS804927531. Okt. 20051. Nov. 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS821228420. Jan. 20113. Juli 2012Semiconductor Energy Laboratory Co., Ltd.Display device and manufacturing method of the display deviceUS823716923. Sept. 20117. Aug. 2012Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS8304298 *15. Mai 20086. Nov. 2012Canon Kabushiki KaishaInverter manufacturing method and inverterUS83731736. Aug. 201212. Febr. 2013Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS840514916. Mai 200826. M�rz 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having display deviceUS20100085081 *15. Mai 20088. Apr. 2010Canon Kabushiki KaishaInverter manufacturing method and inverter* Vom Pr�fer zitiertKlassifizierungen US-Klassifikation257/411, 438/287, 257/347, 257/72, 438/216, 438/591Internationale KlassifikationH01L29/78, H01L29/786, H01L21/336, H01L31/0392 UnternehmensklassifikationH01L29/78603, H01L29/78636, H01L27/1214, H01L29/4908, H01L29/04 Europ�ische KlassifikationH01L29/49B, H01L29/786A, H01L29/786B6, H01L27/12TDrehenOriginalbildGoogle-Startseite - Sitemap - USPTO-Bulk-Downloads - Datenschutzerkl�rung - Nutzungsbedingungen - �ber Google Patente - Feedback gebenDaten bereitgestellt von IFI CLAIMS Patent Services.© 2012 Google