Source: https://patents.google.com/patent/JP5808586B2/en
Timestamp: 2020-08-08 01:50:11+00:00
Document Index: 72954727

Matched Legal Cases: ['art 1', 'art 2', 'art 2', 'art 3', 'art 4', 'art 20', 'art 30', 'art 6', 'art 7', 'art 6', 'art 6', 'art 7', 'art 6', 'art 7', 'art 7', 'art 7', 'art 6', 'art 7', 'art 6', 'art 7', 'art 6', 'art 7', 'art 6', 'art 7', 'art 7', 'art 6', 'art 7']

JP5808586B2 - Manufacturing method of interposer - Google Patents
Manufacturing method of interposer Download PDF
JP5808586B2
JP5808586B2 JP2011136861A JP2011136861A JP5808586B2 JP 5808586 B2 JP5808586 B2 JP 5808586B2 JP 2011136861 A JP2011136861 A JP 2011136861A JP 2011136861 A JP2011136861 A JP 2011136861A JP 5808586 B2 JP5808586 B2 JP 5808586B2
JP2011136861A
JP2013004881A5 (en
JP2013004881A (en
坂口　秀明
秀明 坂口
2011-06-21 Application filed by 新光電気工業株式会社 filed Critical 新光電気工業株式会社
2011-06-21 Priority to JP2011136861A priority Critical patent/JP5808586B2/en
2013-01-07 Publication of JP2013004881A publication Critical patent/JP2013004881A/en
2014-06-26 Publication of JP2013004881A5 publication Critical patent/JP2013004881A5/ja
2015-11-10 Publication of JP5808586B2 publication Critical patent/JP5808586B2/en
239000010410 layers Substances 0.000 claims description 209
239000000758 substrates Substances 0.000 claims description 141
229920000642 polymers Polymers 0.000 claims description 130
239000011347 resins Substances 0.000 claims description 130
239000011799 hole materials Substances 0.000 claims description 64
239000011521 glass Substances 0.000 claims description 13
230000000149 penetrating Effects 0.000 claims description 7
238000010030 laminating Methods 0.000 claims description 3
XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound 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238000007747 plating Methods 0.000 description 32
239000010949 copper Substances 0.000 description 19
229910052802 copper Inorganic materials 0.000 description 15
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239000000919 ceramic Substances 0.000 description 9
239000003822 epoxy resin Substances 0.000 description 9
239000002184 metal Substances 0.000 description 9
229910052751 metals Inorganic materials 0.000 description 9
238000004089 heat treatment Methods 0.000 description 7
229920001721 Polyimides Polymers 0.000 description 3
239000000654 additives Substances 0.000 description 3
RTAQQCXQSZGOHL-UHFFFAOYSA-N titanium Chemical compound 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[Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
229910052709 silver Inorganic materials 0.000 description 2
ATJFFYVFTNAWJD-UHFFFAOYSA-N tin hydride Chemical compound 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[Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
229910052759 nickel Inorganic materials 0.000 description 1
The present invention relates to a method for manufacturing an interposer having a stress relaxation mechanism.
2. Description of the Related Art Conventionally, a mounting structure in which a semiconductor chip is flip-chip connected to a mounting substrate has been widely adopted as electronic devices become smaller, thinner, and higher performance. In such a mounting structure, after the solder bumps of the semiconductor chip are flip-chip connected to the connection electrodes of the mounting substrate, the underfill resin is filled in the lower gap of the semiconductor chip. In some cases, the semiconductor chip is flip-chip connected to the interposer, and the interposer is connected to the mounting substrate.
JP 2005-64467 A
As will be described in the preliminary item section described later, the semiconductor chip (silicon) and the mounting substrate (glass epoxy resin) to which it is flip-chip connected have considerably different thermal expansion coefficients. For this reason, in the heat treatment at the time of mounting the semiconductor chip, residual stress tends to be concentrated on the joint due to the generation of thermal stress.
As a result, the junction between the semiconductor chip and the mounting substrate and the element of the semiconductor chip may be destroyed, and sufficient electrical connection reliability cannot be obtained. A similar problem occurs when a semiconductor chip is connected to a mounting substrate via a silicon interposer.
It is an object of the present invention to provide a method for manufacturing an interposer having a stress relaxation mechanism for reliably connecting a semiconductor chip to a mounting substrate.
According to one aspect of the disclosure below, a substrate resin layer having an opening penetrating in the thickness direction, a wiring layer formed in a region including the opening on one surface of the substrate resin layer, and the substrate resin A lower wiring board formed on one surface of the layer and including an interlayer insulating layer covering the wiring layer; an upper wiring board disposed above the lower wiring board via a space; and the upper wiring board The through-hole electrode is formed up to the opening of the substrate resin layer and connected to the wiring layer, and connects the upper wiring substrate and the lower wiring substrate, and the side surface of the through electrode is An interposer is provided that is in direct contact with the inner wall surface of the opening of the substrate resin layer and exposed to the space formed between the lower wiring substrate and the upper wiring substrate.
According to another aspect of the disclosure, the interposer according to any one of claims 1 to 4, a semiconductor chip flip-chip connected to a wiring layer on an upper surface side of the upper wiring board portion, and the lower wiring board There is provided a semiconductor device having a mounting substrate connected to a connection terminal on the lower surface side of the part.
Further, according to another aspect of the disclosure, a step of forming a through hole in the upper substrate, and a sacrificial resin layer in which an opening is provided at a position corresponding to the through hole on one surface of the upper substrate. Forming the resin layer having an opening provided at a position corresponding to the through hole on the outer surface of the sacrificial resin layer, and forming the through hole, the opening of the sacrificial resin layer, and the resin layer. A step of obtaining a communication through hole formed in communication with the opening, a step of forming a through electrode in the communication through hole, and a lower wiring by laminating a wiring layer and an insulating layer on the resin layer There is provided an interposer manufacturing method including a step of forming a substrate portion and a step of separating the resin layer and the upper substrate by removing the sacrificial resin layer.
According to the following disclosure, in the interposer, the upper wiring substrate unit is disposed on the lower wiring substrate unit in a separated state (via the cavity), and the upper wiring substrate unit, the lower wiring substrate unit, Are connected by a through electrode.
Since the semiconductor chip is flip-chip connected to the upper wiring substrate (silicon or glass) that can be set to have the same thermal expansion coefficient, the generation of thermal stress is suppressed.
Further, the thermal expansion coefficient of the lower wiring board part (resin or ceramics) can be approximated to the thermal expansion coefficient of the mounting board (resin). Therefore, when the interposer is mounted on the mounting substrate, the generation of thermal stress is suppressed, and the reliability of electrical connection at the joint can be improved.
Furthermore, even if thermal stress or mechanical stress is applied to the interposer, the stress can be dispersed by bending the connecting portion of the through electrode.
FIGS. 1A to 1C are cross-sectional views (part 1) for explaining preliminary matters. FIG. 2 is a cross-sectional view (part 2) for explaining preliminary matters. Drawing 3 (a)-(e) is a sectional view (the 1) showing the manufacturing method of the interposer of an embodiment. 4A to 4C are cross-sectional views (part 2) illustrating the method for manufacturing the interposer according to the embodiment. 5A to 5E are cross-sectional views (part 3) illustrating the method for manufacturing the interposer according to the embodiment. 6A to 6C are cross-sectional views (part 4) illustrating the method of manufacturing the interposer according to the embodiment. Drawing 7 (a)-(c) is a sectional view (the 5) showing a manufacturing method of an interposer of an embodiment. FIG. 8 is a cross-sectional view showing the interposer of the embodiment. FIG. 9 is a cross-sectional view showing a state where a semiconductor chip is flip-chip connected to the interposer of FIG. FIG. 10 is a cross-sectional view showing a semiconductor device in which a semiconductor chip is connected to a mounting substrate via the interposer shown in FIG. FIG. 11 is a cross-sectional view showing a state in which an underfill resin is filled on the lower side of the semiconductor chip and the lower side of the interposer of the semiconductor device of FIG. FIG. 12 is a cross-sectional view showing a state in which an underfill resin is filled in the lower side of the semiconductor chip and the cavity and lower side of the interposer of the semiconductor device of FIG.
Hereinafter, embodiments will be described with reference to the accompanying drawings.
Prior to the description of the present embodiment, a preliminary matter as a basis will be described. 1 and 2 are cross-sectional views for explaining preliminary matters.
As shown in FIG. 1A, first, a semiconductor chip 100 and a mounting substrate 200 (package substrate) are prepared. The semiconductor chip 100 includes solder bumps 120 on the lower surface side.
The mounting substrate 200 is formed of glass epoxy resin, and includes a connection electrode 220 and a solder resist 240 provided so as to expose the connection electrode 220 on the upper surface side.
Then, as shown in FIG. 1B, solder is applied on the connection electrodes 220 of the mounting substrate 200, and the solder bumps 120 of the semiconductor chip 100 are disposed on the connection electrodes 220 of the mounting substrate 200. Furthermore, the semiconductor chip 100 is flip-chip connected to the mounting substrate 200 by melting the solder by heat treatment and performing reflow soldering.
In the case of lead (Pb) -free solder such as tin (Sn) -silver (Ag) -copper (Cu), it is necessary to perform heat treatment at a relatively high temperature of about 220 to 250 ° C.
Here, the thermal expansion coefficient of the semiconductor chip 100 (silicon) is 3 to 4 ppm / ° C., and the thermal expansion coefficient of the mounting substrate 200 (glass epoxy resin) is 18 ppm / ° C. Yes.
For this reason, as shown in FIG. 1B, the mounting substrate 200 having a large thermal expansion coefficient is expanded by thermal expansion during the reflow soldering heat treatment. Next, after lowering to room temperature, the underfill resin 300 is filled in the lower gap of the semiconductor chip 100. When the temperature is lowered to room temperature, the mounting substrate 200 expanded by thermal expansion returns to the original state.
At this time, the residual stress is concentrated at the joint between the semiconductor chip 100 and the mounting substrate 200. For this reason, the joint between the semiconductor chip 100 and the mounting substrate 200 may be broken by the residual stress.
That is, the connection part on the semiconductor chip 100 side, the connection part on the mounting substrate 200 side, or the solder bump 120 may be broken, and a conduction failure may occur. Alternatively, the elements inside the semiconductor chip 100 may be destroyed by the residual stress.
As described above, the mismatch of the thermal expansion coefficients between the semiconductor chip 100 and the mounting substrate 200 makes it difficult to flip-chip connect the semiconductor chip 100 to the mounting substrate 200 with high reliability. In particular, when the area of the semiconductor chip 100 is large (15 to 20 mm □) or the height of the solder bump 120 is lowered, the joint portion tends to be significantly broken.
FIG. 2 shows a state in which the semiconductor chip 100 is flip-chip connected to the mounting substrate 200 via the silicon interposer 400. The silicon interposer 400 includes a through electrode 420 that allows conduction between the upper and lower sides. The solder bump 120 of the semiconductor chip 100 is flip-chip connected to the electrode on the upper surface side of the silicon interposer 400.
Then, the solder bumps 440 of the silicon interposer 400 on which the semiconductor chip 100 is mounted are connected to the connection electrodes 220 of the mounting substrate 200 by reflow soldering.
Even in such a mounting structure, a thermal expansion coefficient mismatch occurs between the silicon interposer 400 and the mounting substrate 200, and therefore, the junction between the silicon interposer 400 and the mounting substrate 200 is easily broken by residual stress. .
By using the interposer of the embodiment described below, the above-described problems can be solved.
3-7 is sectional drawing which shows the manufacturing method of the interposer of embodiment, FIG. 8 is sectional drawing which shows the interposer of embodiment.
In the manufacturing method of the interposer of the embodiment, as shown in FIG. 3A, first, a silicon wafer 10 (upper substrate) is prepared. The thickness of the silicon wafer 10 is 50 to 200 μm, and a silicon wafer having a thickness of 700 to 800 μm is obtained by grinding and thinning with a BG (back grinder).
Next, as shown in FIG. 3B, a resist (not shown) having an opening is formed on the silicon wafer 10 by photolithography, and the silicon wafer 10 is dry-etched by RIE or the like through the opening of the resist. Through.
Thereafter, the resist is removed. Thereby, a first through hole TH1 penetrating from the upper surface to the lower surface is formed in the silicon wafer 10. The diameter of the first through hole TH1 is set to about 50 to 100 μm, for example.
A number of interposer regions for obtaining an interposer are defined in the silicon wafer 10, and a plurality of first through holes TH1 are arranged in each interposer region. FIG. 3B schematically shows one interposer region of the silicon wafer 10.
Next, as shown in FIG. 3C, by thermally oxidizing the silicon wafer 10, the insulating layer 12 made of a silicon oxide layer having a thickness of about 1 μm is formed on both surfaces of the silicon wafer 10 and the inner surface of the first through hole TH1. Form. Alternatively, the insulating layer 12 may be formed by forming a silicon oxide layer or a silicon nitride layer on both surfaces of the silicon wafer 10 and the inner surface of the first through hole TH1 by a CVD method.
In the present embodiment, the silicon wafer 10 is illustrated as the upper substrate, but a glass substrate may be used instead of the silicon wafer 10. When a glass substrate is used, it is not necessary to form the insulating layer 12.
Subsequently, as illustrated in FIG. 3D, a sacrificial resin layer 20 having an opening 20 a provided at a position corresponding to the first through hole TH <b> 1 is formed on one surface (lower surface) of the silicon wafer 10. As a result, the opening 20a of the sacrificial resin layer 20 communicates with the first through hole TH1 of the silicon wafer 10.
The sacrificial resin layer 20 is selectively removed later by wet treatment with respect to other layers, and a portion where the sacrificial resin layer 20 is formed becomes a cavity (gap). As such a removable sacrificial resin layer 20, a resist is preferably used, but an acrylic resin, a polyimide resin, or the like that can be removed with a dedicated stripping solution can be used.
As a method for forming the sacrificial resin layer 20, an opening 20a is formed by photolithography after attaching a photosensitive resin film (resist or the like). Or after apply | coating liquid resin (resist etc.), you may form the opening part 20a by photolithography. Alternatively, the opening 20a may be formed by processing a resin film (such as a resist) with a laser.
Further, as shown in FIG. 3 (e), a substrate resin layer 30 (lower surface) in which an opening 30a is provided on the outer surface (lower surface) of the sacrificial resin layer 20 at a position corresponding to the first through hole TH1 of the silicon wafer 10. Side substrate). As a result, the second through hole TH2 is formed under the first through hole TH1 of the silicon wafer 10 by the opening 20a of the sacrificial resin layer 20 and the opening 30a of the substrate resin layer 30. The first through hole TH1 and the second through hole TH2 communicate with each other to form a communication through hole CH.
As the substrate resin layer 30, a polyimide resin or an epoxy resin used for an interlayer insulating layer of a general build-up wiring is used, and has resistance when the sacrificial resin layer 20 is removed by a wet process. Resins that are not removed are used.
As a method for forming the substrate resin layer 30, an opening 30a is formed by photolithography after attaching a photosensitive resin film. Or after apply | coating liquid resin, you may form the opening part 30a by photolithography. Alternatively, the opening 30a may be formed by processing a resin film or the like with a laser.
In the present embodiment, the substrate resin layer 30 is illustrated as a lower substrate formed under the sacrificial resin layer 20, but a ceramic substrate such as alumina may be bonded under the sacrificial resin layer 20 as a lower substrate. . In this case, a ceramic substrate having an opening provided at a position corresponding to the first through hole TH1 of the silicon wafer 10 is prepared and bonded to the lower surface of the sacrificial resin layer 20 with an adhesive. Alternatively, the sacrificial resin layer 20 having adhesiveness may be used, and heat treatment may be performed to directly bond the ceramic substrate to the sacrificial resin layer 20.
Next, as shown in FIG. 4A, a plated power supply member 31 such as a copper plate or a copper foil is disposed under the structure of FIG. Then, a metal plating layer made of copper or the like is formed from the lower side to the upper side of the communication through hole CH by electrolytic plating using the plating power supply member 31 as a plating power supply path. Thereby, the through electrode TE is filled in the communication through hole CH. Thereafter, the plating power supply member 31 is removed.
It is also possible to arrange the plating power supply member 31 on the upper surface side of the silicon wafer 10 and form the through electrode TE in the communication through hole CH by the same electrolytic plating. Alternatively, the through electrode TE may be obtained by selectively filling the through hole CH with a copper plating layer by electroless plating.
Next, as shown in FIG. 4B, the upper wiring layer 40 connected to the upper end of the through electrode TE is formed on the upper surface side of the silicon wafer 10. The upper wiring layer 40 is formed by, for example, a semi-additive method. More specifically, a seed layer (not shown) is obtained by forming, for example, a titanium (Ti) layer / copper (Cu) layer on the upper surface side of the silicon wafer 10 by sputtering or electroless plating.
Further, a plating resist (not shown) provided with an opening in a portion where the upper wiring layer 40 is disposed is formed on the seed layer. Thereafter, a metal plating layer (not shown) made of copper or the like is formed in the opening of the plating resist by electrolytic plating using the seed layer as a plating power feeding path.
Next, after removing the plating resist, the upper wiring layer 40 formed from the seed layer and the metal plating layer is obtained by etching the seed layer using the metal plating layer as a mask.
Further, as shown in FIG. 4C, the protective insulating layer 42 is obtained by patterning a solder resist so that the connection portion of the upper wiring layer 40 is exposed.
Thus, the intermediate structure 5 for obtaining the interposer of the embodiment is obtained. Although the method of obtaining the intermediate structure 5 by the first method shown in FIGS. 3 and 4 has been described, the same intermediate structure as FIG. 4C is obtained by the second method shown in FIGS. 5 and 6 below. 5 may be obtained.
More specifically, as shown in FIG. 5A, the through hole TH is formed in the silicon wafer 10 and the insulating layer 12 is formed on the entire surface of the silicon wafer 10 in the same manner as in FIGS. Form.
Next, as shown in FIG. 5 (b), a plating power supply member 31 such as a copper plate or copper foil is disposed on the lower surface of the silicon wafer 10, and the silicon wafer 10 is subjected to electrolytic plating using the plating power supply member 31 as a plating power supply path. The first through electrode portion TE1 is formed in the through hole TH. Thereafter, the plating power supply member 31 is removed.
Subsequently, as shown in FIG. 5C, the upper wiring layer connected to the upper surface of the silicon wafer 10 and the upper end of the first through electrode portion TE1 by the same method as the method of FIG. 4B described above. 40 is formed. Further, the protective insulating layer 42 is obtained by patterning a solder resist so that the connection portion of the upper wiring layer 40 is exposed.
Next, as shown in FIG. 5D, the through hole TH (first through electrode portion TE1) of the silicon wafer 10 is formed on one surface (lower surface) of the silicon wafer 10 as in FIG. 3D described above. A sacrificial resin layer 20 having an opening 20a is formed at a position corresponding to.
Further, as shown in FIG. 5 (e), in the same manner as in FIG. 3 (e) described above, on the outer surface (lower surface) of the sacrificial resin layer 20, on the through hole TH (first through electrode portion TE1) of the silicon wafer 10. A substrate resin layer 30 having openings 30a at corresponding positions is formed.
Thereby, the opening 20a of the sacrificial resin layer 20 and the opening 30a of the substrate resin layer 30 communicate with each other, and a communication hole CHx is formed under the first through electrode portion TE1.
Next, as shown in FIG. 6A, for example, a titanium (Ti) layer / copper (Cu) layer is sequentially formed on the surface on which the upper wiring layer 40 of FIG. A power feeding layer 41 is obtained. The plating power supply layer 41 is electrically connected to each first through electrode portion TE1 through the upper wiring layer 40.
Although the plating power feeding layer 41 is drawn not to be connected to the first through electrode portion TE1 in the center of FIG. 6A, in practice, all the first through electrode portions TE1 are not shown. And connected to the plating power supply layer 41 via the upper wiring layer.
Then, as shown in FIG. 6B, the upper portion of the first through electrode portion TE1 is formed by electrolytic plating using the plating power feeding layer 41, the upper wiring layer 40, and the first through electrode portion TE1 as a plating power feeding path (FIG. 6). In (b), the second through-hole electrode portion TE2 is obtained by filling a metal plating layer such as copper into the communication hole CHx arranged at the bottom.
Thereby, the first through electrode portion TE1 and the second through electrode portion TE2 are connected, and the through electrode TE penetrating the silicon wafer 10, the sacrificial resin layer 20, and the substrate resin layer 30 is obtained. Thereafter, as shown in FIG. 6C, the plating power supply layer 41 is removed.
The second through electrode portion TE2 can be formed by other methods. First, a titanium layer / copper layer is sequentially formed by sputtering on the lower surface of the substrate resin layer 30 and the inner surface of the communication hole CHx in FIG. 5E to form a seed layer.
Next, a metal plating layer such as copper is formed on the lower surface side of the substrate resin layer 30 by electrolytic plating using the seed layer as a plating power feeding path, and the inside of the communication hole CHx is filled with the metal plating layer.
Thereafter, the metal plating layer is polished by CMP or the like until the substrate resin layer 30 is exposed, whereby the second through electrode portion TE2 is filled in the communication hole CHx, and the through electrode TE is obtained. When this method is used, the step of forming the upper wiring layer 40 may be performed after the through electrode TE is formed.
In this way, as shown in FIG. 6C, the intermediate structure 5 having the same structure as that of FIG. 4C can be obtained by using the second method.
The following steps will be described using the intermediate structure 5 in FIG. As shown in FIG. 7A, a first lower wiring layer 50 connected to the lower portion of the through electrode TE is formed on the lower surface side of the intermediate structure 5 in FIG. 4C. The first lower wiring layer 50 is formed by, for example, a semi-additive method, similarly to the upper wiring layer 40 of FIG. 4B described above.
Subsequently, as shown in FIG. 7B, an interlayer insulating layer 32 covering the first lower wiring layer 50 is formed under the substrate resin layer 30, and then the interlayer insulating layer 32 is processed by laser. A via hole VH reaching the first lower wiring layer 50 is formed. The interlayer insulating layer 32 is formed by attaching a resin sheet such as an epoxy resin or a polyimide resin.
Alternatively, a photosensitive resin may be used as the interlayer insulating layer 32 and the via hole VH may be formed by photolithography. In addition to attaching the resin sheet, a liquid resin may be applied.
Further, as shown in FIG. 7B, a second lower wiring layer 52 connected to the first lower wiring layer 50 through the via hole VH is formed on the interlayer insulating layer 32. The second lower wiring layer 52 is also formed by, for example, the semi-additive method described above.
Thereafter, the protective insulating layer 34 is obtained by patterning a solder resist so that the connection portion of the second lower wiring layer 52 is exposed. Further, if necessary, a contact layer is formed by performing nickel / gold plating on each connection portion of the upper wiring layer 40 and the second lower wiring layer 52 on both sides.
In this way, the first and second lower wiring layers 50 and 52 perform pitch conversion so that the narrow pitch of the upper wiring layer 40 corresponding to the semiconductor chip corresponds to the wide pitch of the connection electrodes of the mounting substrate.
As described above, the wiring layers (first and second lower wiring layers 50 and 52) and insulating layers (interlayer insulating layer 32 and protective insulating layer 34) connected to the through electrode TE are laminated on the substrate resin layer 30. Thus, a resin wiring board portion 6 (lower wiring board portion) described later is formed.
Next, as shown in FIG. 7C, the sacrificial resin layer 20 is selected with respect to other layers by immersing the structure of FIG. 7B in a stripping solution (etching solution) of the sacrificial resin layer 20. To remove. When a resist is used as the sacrificial resin layer 20, it can be easily removed by a resist stripper (resist stripping solution).
As a result, the sacrificial resin layer 20 between the silicon wafer 10 and the substrate resin layer 30 is removed, and a cavity C (gap) is formed. In this way, the silicon wafer 10 and the substrate resin layer 30 are separated from each other.
Then, the connecting portion Tx of the through electrode TE is exposed in the cavity C so as to penetrate the cavity C up and down.
Note that the removal of the sacrificial resin layer 20 is performed in order from the end of the silicon wafer 10 to the inside. Therefore, when the silicon wafer 10 having a particularly large size is used, the sacrificial resin layer 20 may take a long time to be removed. The
In such a case, although not particularly illustrated, a removal hole that reaches the sacrificial resin layer 20 may be formed in the substrate resin layer 30, the interlayer insulating layer 32, and the protective insulating layer. Thus, since the resist stripper is supplied to the sacrificial resin layer 20 also from the removal holes, the sacrificial layer 20 can be removed in a short time. Alternatively, a removal hole that reaches the sacrificial resin layer 20 may be similarly formed in the silicon wafer 10.
Further, as shown in FIG. 7C, the external connection terminal 54 is formed by mounting a solder hole in the connection portion of the second lower wiring layer 52. Thereafter, at a predetermined timing before or after mounting the semiconductor chip, the structure shown in FIG. 7C is cut from the upper surface to the lower surface so that individual interposer regions are obtained.
As described above, the interposer 1 of the embodiment is obtained as shown in FIG. FIG. 8 shows an example in which the structure of FIG. 7C is cut before the semiconductor chip is mounted.
As shown in FIG. 8, the interposer 1 according to the embodiment includes a resin wiring board part 6 (lower wiring board part) and a silicon wiring board part 7 (upper wiring board part) disposed above the resin wiring board part 6. A cavity portion C is provided between the resin wiring substrate portion 6 and the silicon wiring substrate portion 7, and they are separated from each other.
The silicon wiring substrate portion 7 is provided with a penetrating electrode TE that penetrates in the thickness direction. The penetrating electrode TE is further provided through the cavity C and extending into the resin wiring substrate portion 6. A connecting portion Tx of the through electrode TE is disposed in the cavity C between the resin wiring substrate portion 6 and the silicon wiring substrate portion 7. The side surface of the through electrode TE is exposed to a space formed between the resin wiring board part 6 (lower wiring board part) and the silicon wiring board part 7 (upper wiring board part).
In this way, the resin wiring board part 6 and the silicon wiring board part 7 are connected by the through electrode TE.
Further, in the silicon wiring substrate portion 7, communication through holes CH are formed in the silicon substrate 10x, and insulating layers 12 are formed on both surfaces of the silicon substrate 10x and the inner surfaces of the communication through holes CH. The through electrode TE is filled in the communication through hole CH.
On the upper surface of the silicon substrate 10x, an upper wiring layer 40 connected to the upper end of the through electrode TE is formed. Further, a protective insulating layer 42 is formed on the upper surface of the silicon substrate 10x so as to expose the connection portion of the upper wiring layer 40.
Further, in the resin wiring board portion 6, a first lower wiring layer 50 is formed on the lower surface of the substrate resin layer 30. The through electrode TE penetrating the silicon substrate 10 x and the cavity C is further provided through the substrate resin layer 30, and the lower end of the through electrode TE is connected to the first lower wiring layer 50.
An interlayer insulating layer 32 that covers the first lower wiring layer 50 is formed on the lower surface of the substrate resin layer 30. A via hole VH reaching the first lower wiring layer 50 is formed in the interlayer insulating layer 32. Further, a second lower wiring layer 52 connected to the first lower wiring layer 50 through the via hole VH is formed on the lower surface of the interlayer insulating layer 32.
A protective insulating layer 34 is formed on the lower surface of the interlayer insulating layer 32 so as to expose the connection portion of the second lower wiring layer 52. An external connection terminal 54 is provided at the connection portion of the second lower wiring layer 52.
As described above, in the interposer 1 according to the present embodiment, the resin wiring substrate unit 6 and the resin wiring substrate unit 6 are formed by the through-electrodes TE standing so as to penetrate the cavity C provided between the resin wiring substrate unit 6 and the silicon wiring substrate unit 7. The silicon wiring substrate portion 7 is connected.
The upper wiring layer 40 (pad) of the silicon wiring substrate portion 7 is electrically connected to the first lower wiring layer 50 and the second lower wiring layer 52 (pad) of the resin wiring substrate portion 6 through the through electrode TE. ing.
The first and second lower wiring layers 50 and 52 perform pitch conversion so that the narrow pitch of the upper wiring layer 40 corresponding to the semiconductor chip corresponds to the wide pitch of the connection electrodes of the mounting substrate. For example, the pitch of the upper wiring layer 40 is 150 μm, and the pitch of the second lower wiring layer 52 is set to 300 to 500 μm.
In the interposer 1 of the present embodiment, the upper wiring board part on which the semiconductor chip (silicon) is mounted is formed from the silicon wiring board part 7, and the lower wiring board part mounted on the mounting board (glass epoxy resin) is used as the resin wiring. The substrate portion 6 is formed.
By doing so, first, since the semiconductor chip (silicon) is flip-chip mounted on the silicon wiring substrate part 7 having the same thermal expansion coefficient as that, generation of thermal stress when mounting the semiconductor chip is suppressed, Generation of residual stress at the joint can be reduced.
Although the silicon wiring substrate portion 7 is exemplified as the upper wiring substrate portion, as described above, a glass substrate (thermal expansion coefficient: 3 to 10 ppm / ° C.) that can be set to the same thermal expansion coefficient as that of the semiconductor chip (silicon) is used as the upper wiring substrate. May be used as a part of the substrate, and in this case, the same effect can be obtained.
Furthermore, the resin wiring board part 6 is arranged under the silicon wiring board part 7 through the cavity C, and the resin wiring board part 6 is connected to the silicon wiring board part 7 by the through electrode TE. Since the resin wiring board 6 does not have a core board (rigid board), it functions as a flexible board. For this reason, even if a thermal stress occurs when a semiconductor chip is mounted, the stress can be dispersed by the resin wiring board portion 6 having flexibility.
And the thermal expansion coefficient of the resin wiring board part 6 can be set to 18-30 ppm / degrees C, and can be approximated to the thermal expansion coefficient (18 ppm / degrees C) of the mounting board (glass epoxy resin) connected. Therefore, when the interposer 1 is mounted on the mounting substrate, generation of thermal stress is suppressed, and generation of residual stress at the joint can be reduced.
Although the resin wiring board portion 6 is exemplified as the lower wiring board portion, as described above, a ceramic wiring board portion may be formed by using a ceramic substrate such as alumina instead of the substrate resin layer 30. The thermal expansion coefficient of the ceramic substrate is 8 to 10 ppm / ° C., and is between the thermal expansion coefficient (18 ppm / ° C.) of the mounting substrate (glass epoxy resin) and the thermal expansion coefficient of the silicon wiring substrate portion 7 (3 to 4 ppm / ° C.). Is set to an intermediate value.
Thereby, since the ceramic wiring board part which has a thermal expansion coefficient in the middle between them is arranged between the silicon wiring board part 7 and the mounting board, generation of thermal stress is suppressed and generation of residual stress in the joint part Can be reduced.
Furthermore, the resin wiring board part 6 and the silicon wiring board part 7 are stacked via the cavity part C and are not in contact with each other, and the connecting part Tx of the through electrode TE is exposed to the cavity part C. The through electrode TE functions as a column having a certain degree of strength because it is integrally formed from a metal plating layer such as copper and has no seam.
For this reason, even if a thermal stress is generated in the interposer 1, the stress can be dispersed by bending the connecting portion Tx of the through electrode TE. Further, when mechanical stress is applied from the outside, the structure is strong against stress.
Next, a method for manufacturing a semiconductor device using the interposer 1 of the embodiment will be described.
As shown in FIG. 9, first, a semiconductor chip 60 (LSI chip) having solder bumps 62 on the lower surface side is prepared. The semiconductor chip 60 is obtained by cutting a silicon wafer on which various elements such as transistors are formed.
Then, solder is applied on the upper wiring layer 40 of the interposer 1 shown in FIG. 8, and the solder bumps 62 of the semiconductor chip 60 are disposed on the upper wiring layer 40 of the interposer 1. Further, reflow soldering is performed by heat treatment. Do. In this way, the semiconductor chip 60 is flip-chip connected to the interposer 1.
At this time, as described above, since the semiconductor chip 60 (silicon) and the silicon wiring substrate portion 7 of the interposer 1 have the same thermal expansion coefficient, the generation of thermal stress is suppressed, and the residual stress at the joint portion is reduced. Generation can be reduced. Further, as described above, the same effect can be obtained when a glass wiring board part is used instead of the silicon wiring board part 7 as the upper wiring board part.
Next, as shown in FIG. 10, a mounting substrate 70 is prepared. The mounting substrate 70 is made of an organic substrate containing a resin such as glass epoxy resin, and functions as a wiring substrate for a semiconductor package. A connection electrode 72 is provided on the upper surface side of the mounting substrate 70, and a protective insulating layer 74 is formed on one surface so that the connection electrode 72 is exposed.
A connection electrode 72a is also provided on the lower surface side of the mounting substrate 70, and a protective insulating layer 74a is formed on one surface so that the connection electrode 72a is exposed. The connection electrodes 72 and 72a on the upper and lower surfaces of the mounting substrate 70 are interconnected by internal wiring.
Further, external connection terminals 76 are provided on the connection electrodes 72 a on the lower surface side of the mounting substrate 70.
Then, the external connection terminal 54 (solder) on the lower surface of the interposer 1 (FIG. 9) on which the semiconductor chip 60 is mounted is placed on the connection electrode 72 of the mounting substrate 70, and reflow soldering is performed by heat treatment. Thereby, the semiconductor chip 60 is electrically connected to the mounting substrate 70 via the interposer 1.
As described above, the semiconductor device 2 of the embodiment is obtained.
At this time, since the resin wiring board portion 6 of the interposer 1 approximates the mounting substrate 70 and the thermal expansion coefficient, generation of thermal stress is suppressed, and generation of residual stress at the joint portion can be reduced. . In addition, as described above, the same effect can be obtained when a ceramic wiring board portion is used instead of the resin wiring board portion 6 as the lower wiring board portion.
Moreover, the resin wiring board part 6 is connected to the silicon wiring board part 7 by the through electrode TE through the cavity part C, and functions as a flexible substrate. For this reason, even if a thermal stress occurs in the interposer 1, the stress can be dispersed by the resin wiring board portion 6 having flexibility.
When using lead (Pb) -free solder such as tin (Sn) -silver (Ag) -copper (Cu), it is necessary to heat-treat at a relatively high temperature of about 220 to 250 ° C. Even in such a case, by using the interposer 1 of the present embodiment, it is possible to manufacture the semiconductor device 2 with a high reliability of the bonding portion with a high yield.
Further, even when the area of the semiconductor chip 60 is increased or the height of the solder bumps is decreased due to the narrow pitch, the reliability of the joint portion can be ensured.
Further, the connecting portion Tx of the through electrode TE is exposed in the cavity C between the resin wiring substrate portion 6 and the silicon wiring substrate portion 7. For this reason, even if thermal stress is generated in the interposer 1 or mechanical stress is applied, the stress can be dispersed by bending the connecting portion Tx of the through electrode TE.
As described above, by connecting the semiconductor chip 60 to the mounting substrate 70 via the interposer 1 with the stress relaxation mechanism of the present embodiment, it is possible to avoid concentration of residual stress at each joint portion between the semiconductor chip 60 and the interposer 1. it can.
As a result, problems such as the destruction of each junction between the semiconductor chip 60 and the interposer 1 and the destruction of the elements of the semiconductor chip 60 are eliminated, and the reliability of the semiconductor device can be improved.
Since the semiconductor device 2 of this embodiment uses the interposer 1 with a stress relaxation mechanism, sufficient reliability of the joint can be obtained without filling the underfill resin under the semiconductor chip 60 or the like.
As another form, as shown in FIG. 11, underfill resin 80 is filled in the gap between the semiconductor chip 60 and the interposer 1 and the gap between the interposer 1 and the mounting substrate 70 as necessary. May be. By sealing the joint with the underfill resin 80, the stress is further dispersed, so that the reliability of electrical connection can be further improved.
Furthermore, as shown in FIG. 12, in addition to the gap between the semiconductor chip 60 and the interposer 1 and the gap between the interposer 1 and the mounting substrate 70, the underfill resin 80 is also applied to the cavity C of the interposer 1. It may be filled.
DESCRIPTION OF SYMBOLS 1 ... Interposer, 2 ... Semiconductor device, 5 ... Intermediate structure, 6 ... Resin wiring board part (lower wiring board part), 7 ... Silicon wiring board part (upper wiring board part), 10 ... Silicon wafer (upper board) DESCRIPTION OF SYMBOLS 10x ... Silicon substrate (upper side substrate), 12 ... Insulating layer, 20 ... Sacrificial resin layer, 20a, 30a ... Opening, 30 ... Substrate resin layer (lower side substrate), 31 ... Plating feeding material, 32 ... Interlayer insulating layer 34, 42, 74, 74a ... protective insulating layer, 40 ... upper wiring layer, 41 ... plating power supply layer, 50 ... first lower wiring layer, 52 ... second lower wiring layer, 54, 76 ... external connection terminals 60 ... Semiconductor chip, 62 ... Solder bump, 70 ... Mounting substrate, 72, 72a ... Connection electrode, 80 ... Underfill resin, C ... Cavity, CH ... Communication through hole, CHx ... Communication hole, TE ... Penetration electrode, TE1 ... 1st feedthrough Parts, TE2 ... second through electrode unit, TH1 ... first through hole, TH2 ... second through hole, Tx ... connecting portion, VH ... via hole.
Forming a through hole in the upper substrate;
Forming a sacrificial resin layer provided with an opening at a position corresponding to the through hole on one surface of the upper substrate;
By forming a resin layer having an opening provided at a position corresponding to the through hole on the outer surface of the sacrificial resin layer, the through hole, the opening of the sacrificial resin layer, and the opening of the resin layer Obtaining a communication through hole formed by communicating with each other;
Forming a through electrode in the communication through hole;
Forming a lower wiring board by laminating a lower wiring layer and an insulating layer connected to the through electrode on the resin layer;
And a step of separating the resin layer and the upper substrate by removing the sacrificial resin layer.
Forming a first through electrode portion in the through hole;
By forming a resin layer provided with an opening at a position corresponding to the through hole on the outer surface of the sacrificial resin layer, the opening of the sacrificial resin layer and the opening of the resin layer communicate with each other. Obtaining a communication hole to be formed;
Forming a through electrode penetrating the upper substrate, the sacrificial resin layer, and the resin layer by forming a second through electrode portion connected to the first through electrode portion in the communication hole;
Manufacturing method of the interposer of claim 1 or 2, characterized in that it has further a step of forming an upper wiring layer connected to the upper end of the through electrode on the upper surface of the upper substrate.
The upper substrate, an interposer manufacturing method according to claim 1 or 2, characterized in that it consists of silicon or glass.
JP2011136861A 2011-06-21 2011-06-21 Manufacturing method of interposer Active JP5808586B2 (en)
JP2011136861A JP5808586B2 (en) 2011-06-21 2011-06-21 Manufacturing method of interposer
US13/528,100 US8536714B2 (en) 2011-06-21 2012-06-20 Interposer, its manufacturing method, and semiconductor device
JP2013004881A JP2013004881A (en) 2013-01-07
JP2013004881A5 JP2013004881A5 (en) 2014-06-26
JP5808586B2 true JP5808586B2 (en) 2015-11-10
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JP2011136861A Active JP5808586B2 (en) 2011-06-21 2011-06-21 Manufacturing method of interposer
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