Source: http://www.google.com/patents/US7532144?ie=ISO-8859-1&dq=7,134,016
Timestamp: 2014-12-25 13:24:05
Document Index: 144835548

Matched Legal Cases: ['art 101', 'art 101', 'art 102', 'art 101', 'art 101', 'art 102', 'art 103', 'art 101', 'art 73', 'art 74', 'art 73', 'art 72', 'art 72', 'art 73', 'art 74', 'art 72', 'art 73', 'art 81']

Patent US7532144 - AD converter and radio receiver - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsDisclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n≦m≦2n), a decoding part to generate m pieces of decoded analog signals from the...http://www.google.com/patents/US7532144?utm_source=gb-gplus-sharePatent US7532144 - AD converter and radio receiverAdvanced Patent SearchPublication numberUS7532144 B2Publication typeGrantApplication numberUS 12/104,488Publication dateMay 12, 2009Filing dateApr 17, 2008Priority dateFeb 23, 2006Fee statusPaidAlso published asUS7379009, US20070194971, US20080204298Publication number104488, 12104488, US 7532144 B2, US 7532144B2, US-B2-7532144, US7532144 B2, US7532144B2InventorsTakafumi Yamaji, Takeshi UenoOriginal AssigneeKabushiki Kaisha ToshibaExport CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (4), Classifications (7), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetAD converter and radio receiverUS 7532144 B2Abstract Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n≦m≦2n), a decoding part to generate m pieces of decoded analog signals from the m parallel pieces of quantized signals, and a residual amplifying part to output m pieces of amplified residual signals by multiplying respective differences between each of the m pieces of analog signals and each of the m pieces of decoded analog signals; a second conversion stage including a quantizing part to generate m parallel pieces of quantized signals from the m pieces of amplified residual signals; and a synthesizing part to generate m parallel pieces of digital signals by synthesizing each of the quantized signals in the first conversion stage and in the second conversion stage at each parallel position.
outputting m parallel pieces of K-bit digital values in each piece of which bits up to a Kth bit have been decided, as the m parallel pieces of K-bit digital signals, in respective states where the �k� is changed from 0 to K−1.
outputting three parallel K-bit digital values in each of which bits up to a Kth bit have been decided, as the three parallel K-bit digital signals, in respective states where the �k� is changed from 0 to K−1;
CROSS REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from and is a continuation of application Ser. No. 11/623,803 filed on Jan. 17, 2007, which is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2006-47125, filed on Feb. 23, 2006 and No. 2006-204140 filed on Jul. 27, 2006; the entire contents of which are incorporated herein by reference.
BRIEF SUMMARY OF THE INVENTION An AD converter according to one aspect of the present invention includes: a first conversion stage including a first quantizing part that quantizes each of m pieces of analog signals representing n-dimensional vectors (n≦m≦2n) to generate m parallel pieces of first quantized signals, a first decoding part that decodes the m parallel pieces of first quantized signals to generate m pieces of first decoded analog signals, and a first residual amplifying part that multiplies respective differences between the m pieces of analog signals and the m pieces of first decoded analog signals by a constant multiplier to output m pieces of amplified residual signals; a second conversion stage including a second quantizing part that quantizes each of the m pieces of amplified residual signals to generate m parallel pieces of second quantized signals; and a synthesizing part that synthesizes each of the first quantized signals and each of the second quantized signals at each parallel position after delaying the first quantized signals by a delay amount of the second quantized signals relative to the first quantized signals, to generate m parallel pieces of digital signals.
An AD converter according to still another aspect of the present invention converts m pieces of analog signals representing n-dimensional vectors (n<m<2n) to m parallel pieces of K-bit digital signals, and includes: a decoding part that decodes m parallel pieces of K-bit digital values in each piece of which bits up to a kth bit (0≦k≦K−1) have been decided and a (k+1)th bit and thereafter are given tentative values, to generate m pieces of decoded analog signals; a quantizing part that generates m parallel pieces of 1-bit quantized signals by comparing each of the m pieces of analog signals and each of the m pieces of decoded analog signals; a first control part that decides a (k+1)th bit of each of m parallel pieces of K-bit digital codes based on each of values of the m parallel pieces of 1-bit quantized signals, to output m parallel pieces of K-bit digital values in each piece of which bits up to a (k+1)th bit have been decided and a (k+2)th bit and thereafter are given tentative values; and a second control part that causes the decoding part, the quantizing part, and the first control part to operate in respective states where the �k� is changed from 0 to K−1, and outputs m parallel pieces of K-bit digital values in each piece of which bits up to a Kth bit have been decided, as the m parallel pieces of K-bit digital signals.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of an AD converter according to one embodiment.
DETAILED DESCRIPTION OF THE INVENTION Description of Embodiments Embodiments of the present invention will be described with reference to the drawings, but these drawings are provided only for an illustrative purpose and in no way limit the present invention.
If the quantizing part 101 shown in FIG. 3 were free from error, the input analog signals would be converted to binary codes shown in FIG. 6 respectively according to six areas segmented by the broken lines shown in FIG. 6. No area corresponding to a code �000� or a code �111� would exist. However, the actual comparison circuits 101 a etc. have offsets, and the reference voltage generated in advance does not always match a common mode component voltage of the three analog signals.
Therefore, actually, the positions of the broken lines deviate from the ideal places as shown in FIG. 7. Outputs of the comparison circuits 101 a, 101 b, 101 c become �000� in an area close to the center surrounded by the broken lines in FIG. 7. Depending on how the broken lines deviate, the outputs sometimes become �111� in the area close to the center. Taking these errors into consideration, the quantizing part 101 can be regarded as a quantizer that quantizes signals to seven points shown in FIG. 8. The center point corresponds to �000� or �111�.
Further, a decoder D1 especially detects that the three parallel 1-bit quantized signals are �000� and �111� (that is, detects a case where the three analog signals correspond to the center point on the phase plane). When this is detected, the position of a switch SW6 is changed to �com�. In a case of the other codes, the position of the switch SW6 is changed to Vref_P or Vref_N according to high/low of the quantized signal corresponding to the inputted analog signal. The �com� is an intermediate voltage between Vref_P and Vref_N. The function of the decoding part 102 is realized by the decoder D1, the switch SW6, and the three reference voltages com, Vref_P, Vref_N.
This MDAC has the same configuration as that of a single-ended or differential MDAC except in the above-described characteristic of the 3-input 3-output operational amplifying circuit A1 and in the existence of the decoder D1. As an example, a case where the three parallel 1-bit quantized signals are �001� and �101� will be discussed. In the case of �001�, the positions of the three switches SW6 (three including SW6 in circuits for the other two signals) are changed to Vref_N, Vref_N, and Vref_P respectively. If Vref_P−Vref_N is 1 V, decoded analog signals after the common mode component is removed (that is, equivalent to outputs of the 3-input 3-output operational amplifier A1) are (−⅓, −⅓, ⅔) respectively.
In the case of �101�, the connection positions of the three switches SW6 are Vref_P, Vref_N, and Vref_P respectively, and the decoded analog signals after the common mode component is removed (that is, equivalent to outputs of the 3-input 3-output operational amplifying circuit A1) are (⅓, −⅔, ⅓) respectively. These decoded analog signals are subtracted from the input analog signals respectively, and the subtraction results are amplified twofold in the 3-input 3-output operational amplifying circuit A1 to be outputted therefrom.
The design shown in FIG. 12 makes it possible to generate decoded analog signals corresponding to �001� or �101� in a form in which a common mode component is removed therefrom, such as (−0.5, −0.5, 1.0) or (0.5, −1.0, 0.5) (the sum of the three decoded analog signals is zero).
FIG. 14 shows, on a phase plane, the operation of the quantizing part 101A shown in FIG. 13 (ideal case). The quantizing part 101A shown in FIG. 13 quantizes each of difference components among the three analog signals to 1-bit information, and therefore without any error in the comparison circuits 101 d, 101 e, 101 f, boundaries of areas and axes of the three analog signals match each other as shown in FIG. 14. With some error in the comparison circuits 101 d, 101 e, 101 f, an area corresponding to �111� or �000� exists as shown in FIG. 15.
FIG. 16 shows a concrete example of a decoding part 102A and a residual amplifying part 103A which are adapted to the quantizing part 101A shown in FIG. 13. To simplify the description, only a circuit corresponding to one signal is shown. This circuit as a whole is an MDAC similarly to the circuits shown in FIG. 9 and FIG. 12. Here, the same reference numerals and symbols are used to designate the same constituent elements as those shown in FIG. 9 and FIG. 12. A description thereof will be omitted. As shown in FIG. 16, in this circuit, the intermediate voltage �com� between Vref_P and Vref_N which is necessary in the circuit shown in FIG. 12 is not required. Further, as a signal that controls switches SW61, SW62, output signals of the comparison circuits 101 d, 101 d, 101 f can be directly utilized without any intervention of the decoder D2. Further, SW51 and SW52 are not necessary.
When �111� signals are inputted to this MDAC, one of SW61 and SW62 is connected to Vref_P and the other is connected to Vref_N, so that the inputted signals cause cancellation. Therefore, the resultant state is the same as the state where a capacitor C21 and a capacitor C22 are connected to the intermediate voltage com in FIG. 12. When �000� signals are inputted, voltages to which the capacitor C21 and the capacitor 22 in FIG. 16 are connected are reversed from those in the case of the �111�, and as a result, the inputted signals cause cancellation. Therefore, without using the decoder D2, �111� and �000� are decoded as signals corresponding to �0�. Because the decoder D2 is not required, it is possible not only to simplify the circuit but also to realize a circuit suitable for higher-speed operation.
FIG. 21 shows, on the phase plane, the operation of the control part 73 shown in FIG. 18. A black square represents input analog signals and a black circle represents outputs of the decoding part 74 according to outputs of the control part 73 at a certain stage. As shown in FIG. 21, this 3-input AD converter can detect the direction of residual vectors instead of the simple magnitude of each scalar in outputs of the quantizing part 72. That is, when the outputs of the quantizing part 72 are, for example, �100�, it is determined that the input analog signals (vectors) are in a right 60� fan-shaped area on the phase plane (FIG. 8 can be also referred to). Consequently, the outputs of the control part 73 are corrected so that the outputs (vector) of the decoding part 74 are corrected as shown by the arrow 141.
Next, residual vector between the corrected decoded vector and the input analog vector is quantized in the quantizing part 72, whereby the residual vector can be found as �110�. Consequently, the control part 73 corrects digital codes of its outputs as shown by the arrow 142. Next, further correction is repeated so as to gradually reduce difference between the input vector and the decoded vector as shown by the arrow 143, whereby the most approximate decoded vector and corresponding digital codes can be decided.
[ y 0 y 1 y 2 ] = [ D 0 0 - D 0 0 0 D 0 0 - D 0 0 0 D 0 0 - D ] [ x 0 x 1 x 2 v 0 v 1 v 2 ] where ( 2 ) D = C s C I ( 1 - z - 1 ) ( 3 ) FIG. 23 shows the case where the linear conversion part 81 uses the switched capacitor integrator as its component, but it is well known that a switched capacitor filter can realize not only a low-pass characteristic such as that of an integrator but also a band-pass characteristic and a high-pass characteristic. Further, since many prototypes using a high-order filter in ordinary delta-sigma AD converters for scalar signal have been reported, any of these high-order filters can be extended for use in this embodiment.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6031480Nov 4, 1997Feb 29, 2000Texas Instruments IncorporatedMethod and apparatus for implementing a pipelined A/D converter with inter-stage amplifiers having no common mode feedback circuitryUS6753801Aug 23, 2002Jun 22, 2004Micron Technology, Inc.Fully differential reference driver for pipeline analog to digital converterUS7286074Jul 27, 2005Oct 23, 2007Renesas Technology CorporationSemiconductor integrated circuit for communication including analog-to-digital conversion circuitUS7379009 *Jan 17, 2007May 27, 2008Kabushiki Kaisha ToshibaAD converter and radio receiverUS20050219101Mar 23, 2005Oct 6, 2005Daisuke KuroseMultiple input analog-to-digital conversion apparatus and radio receiver using the sameUS20070024359Mar 23, 2006Feb 1, 2007Kabushiki Kaisha ToshibaAmplifier, filter using the same, and radio communication deviceUS20070026835Mar 22, 2006Feb 1, 2007Kabushiki Kaisha ToshibaMultiplier and radio communication apparatus using the sameUS20080204298Apr 17, 2008Aug 28, 2008Kabushiki Kaisha ToshibaAd converter and radio receiverJP2007228270A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7619445 *Jul 1, 2008Nov 17, 2009Nec CorporationDifferential amplifier, digital-to-analog converter and display apparatusUS7801849 *Aug 16, 2007Sep 21, 2010American Express Travel Related Services Company, Inc.Test strategy system and method for accounts held direct at-fundUS8037020 *Aug 12, 2010Oct 11, 2011American Express Travel Related Services Company, Inc.Test strategy system and method for accounts held direct at-fundUS8538913Sep 7, 2011Sep 17, 2013American Express Travel Related Services Company, Inc.Test strategy system and method for accounts held direct at-fund* Cited by examinerClassifications U.S. Classification341/156, 341/155International ClassificationH03M1/12Cooperative ClassificationH03M1/44, H03M1/123, H03M1/46European ClassificationH03M1/12M6Legal EventsDateCodeEventDescriptionSep 28, 2012FPAYFee paymentYear of fee payment: 4Apr 17, 2008ASAssignmentOwner name: KABUSHIKI KAISHA TOSHIBA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAMAJI, TAKAFUMI;UENO, TAKESHI;REEL/FRAME:020819/0766Effective date: 20061221Owner name: KABUSHIKI KAISHA TOSHIBA,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAMAJI, TAKAFUMI;UENO, TAKESHI;US-ASSIGNMENT DATABASE UPDATED:20100329;REEL/FRAME:20819/766RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google