Source: https://patents.google.com/patent/US7951649B2/en
Timestamp: 2018-09-19 10:17:17
Document Index: 553033887

Matched Legal Cases: ['Application No. 0607442', '§119', 'Application No. 026', 'Application No. 030', 'Application No. 092', 'Application No. 131', 'Application No. 148', 'Application No. 181', 'Application No. 201870', 'Application No. 221437', 'Application No. 226', 'Application No. 272', 'Application No. 274205', 'Application No. 296', 'Application No. 296', 'Application No. 361', 'Application No. 407', 'Application No. 507', 'Application No. 527', 'Application No. 735', 'Application No. 89', 'Application No. 920']

US7951649B2 - Process for the collective fabrication of 3D electronic modules - Google Patents
Process for the collective fabrication of 3D electronic modules Download PDF
US7951649B2
US7951649B2 US12438179 US43817907A US7951649B2 US 7951649 B2 US7951649 B2 US 7951649B2 US 12438179 US12438179 US 12438179 US 43817907 A US43817907 A US 43817907A US 7951649 B2 US7951649 B2 US 7951649B2
US12438179
US20090209052A1 (en )
B1) a step of depositing an adhesive support (40) on the component-side face;
C1) a step of removing the silicon wafer (10) so as to expose the test pads (20);
D1) a step of electrically testing the components of the wafer via the test pad (20) and of marking the valid components (11′) and/or defective components; and
E1) a step of bonding the dies (50) onto an adhesive film (41), each die comprising a valid component (11′) connected to test pads (20) and to at least one track (3), insulating resin (6), and an insulating layer (4), the dies being separated by second grooves (31) of width L2 with which the connection tracks (3) of the valid components (11′) are flush.
This step, repeated K times, is followed by a step of stacking the K wafers, of forming metallized holes in the thickness of the stack, which are intended for connecting the dies together, and then of dicing the stack in order to obtain the n 3D modules.
The present Application is based on International Application No. PCT/EP2007/058090, filed on Aug. 3, 2007, which in turn corresponds to French Application No. 0607442 filed on Aug. 22, 2006, and priority is hereby claimed under 35 USC §119 based on these applications. Each of these applications are hereby incorporated by reference in their entirety into the present application.
One method consists in connecting the pads of the component directly to those of the insulating substrate by sending ultrasound waves. The energy sent is proportional to the number of pads to be connected. For components having a large number of pads, the energy needed for the connection sometimes causes the component to break. One solution for reducing this energy consists in heating the substrate, which then softens and adsorbs some of the ultrasonic energy sent, thereby making the connection very difficult. Furthermore, during encapsulation of the components, by curing carried out at about 150° C., the substrate tends to become curved since the expansion coefficient of the components is different from that of the substrate, typically four times smaller.
US12438179 2006-08-22 2007-08-03 Process for the collective fabrication of 3D electronic modules Active 2028-05-23 US7951649B2 (en)
FR0607442A FR2905198B1 (en) 2006-08-22 2006-08-22 Method for mass production of 3D electronic modules
FR0607442 2006-08-22
PCT/EP2007/058090 WO2008022901A3 (en) 2006-08-22 2007-08-03 Process for the collective manufacturing of electronic 3d modules
US20090209052A1 true US20090209052A1 (en) 2009-08-20
US7951649B2 true US7951649B2 (en) 2011-05-31
ID=37888100
US12438179 Active 2028-05-23 US7951649B2 (en) 2006-08-22 2007-08-03 Process for the collective fabrication of 3D electronic modules
US (1) US7951649B2 (en)
EP (1) EP2054929B1 (en)
JP (1) JP5433899B2 (en)
KR (1) KR101424298B1 (en)
FR (1) FR2905198B1 (en)
WO (1) WO2008022901A3 (en)
FR3053158A1 (en) * 2016-06-22 2017-12-29 3D Plus Method for mass production of electronic modules 3d configured to operate more than 1 ghz
EP1041620A2 (en) 1999-04-02 2000-10-04 Alcatel Alsthom Compagnie Generale D'electricite Method of transferring ultrathin substrates and application of the method to the manufacture of a multi-layer thin film device
JP2001332685A (en) 2000-05-24 2001-11-30 Matsushita Electric Ind Co Ltd Method for manufacturing semiconductor device
US20080170374A1 (en) 2005-04-01 2008-07-17 3D Plus Low-Thickness Electronic Module Comprising a Stack of Electronic Packages Provided with Connection Balls
US20080289174A1 (en) 2005-12-23 2008-11-27 3D Plus Process for the Collective Fabrication of 3D Electronic Modules
US20080316727A1 (en) 2005-11-30 2008-12-25 3D Plus 3D Electronic Module
JP2000252411A (en) 1999-03-03 2000-09-14 Mitsui High Tec Inc Stacked semiconductor device and its manufacture
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KR20090048597A (en) 2009-05-14 application
US20090209052A1 (en) 2009-08-20 application
EP2054929A2 (en) 2009-05-06 application
EP2054929B1 (en) 2016-03-16 grant
FR2905198B1 (en) 2008-10-17 grant
JP2010502006A (en) 2010-01-21 application
JP5433899B2 (en) 2014-03-05 grant
KR101424298B1 (en) 2014-08-01 grant
FR2905198A1 (en) 2008-02-29 application
WO2008022901A3 (en) 2008-06-19 application
WO2008022901A2 (en) 2008-02-28 application
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