Source: http://www.google.com/patents/US8013381?dq=ininventor:oliver+ininventor:steele
Timestamp: 2016-02-14 01:08:53
Document Index: 128149505

Matched Legal Cases: ['Application No. 2008', 'Application No. 2008', 'art 1005', 'art) 1006', 'art 1006', 'art 1006', 'art 1006']

Patent US8013381 - Semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and...http://www.google.com/patents/US8013381?utm_source=gb-gplus-sharePatent US8013381 - Semiconductor deviceAdvanced Patent SearchPublication numberUS8013381 B2Publication typeGrantApplication numberUS 12/360,941Publication dateSep 6, 2011Filing dateJan 28, 2009Priority dateJan 31, 2008Fee statusLapsedAlso published asUS20090194841Publication number12360941, 360941, US 8013381 B2, US 8013381B2, US-B2-8013381, US8013381 B2, US8013381B2InventorsNorio MAGOME, Toshifumi Minami, Tomoaki Hatano, Norihisa AraiOriginal AssigneeKabushiki Kaisha ToshibaExport CitationBiBTeX, EndNote, RefManPatent Citations (39), Classifications (32), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device
US 8013381 B2Abstract
A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-20632, filed on Jan. 31, 2008, and the Japanese Patent Application No. 2008-318453, filed on Dec. 15, 2008, the entire contents of which are incorporated herein by reference.
According to one aspect of the present invention, there is provided: a semiconductor device, comprising:
FIG. 1 is a schematic diagram showing an example of a memory cell array of a NAND flash memory 1000 having a semiconductor device 100 according to an embodiment 1 of the present invention, which is an aspect of the present invention, and a peripheral circuit thereof;
The present invention relates to a semiconductor device having a plurality of high-voltage MOSFETs for controlling a nonvolatile semiconductor storage device arranged in an array. The breakdown voltage for device isolation of the high-voltage MOSFETs is optimized, thereby increasing the integration density.
FIG. 1 is a schematic diagram showing an example of a memory cell array of a NAND flash memory 1000 having a semiconductor device 100 according to an embodiment 1 of the present invention, which is an aspect of the present invention, and a peripheral circuit thereof.
The row decoder 1001 is configured to select one of word lines “WL1” to “WL8” and select gate lines “SGD” and “SGS”. The row decoder 1001 has a row main decoder circuit part 1005 and a core part (row sub decoder circuit part) 1006.
The core part 1006 has transfer gate transistors “TGTD” and “TGTS” connected to a common transfer gate line “TG” at their respective gates and a plurality of high-voltage MOSFETs (insulated-gate field effect transistors).
Each NAND cell 1007 includes eight memory cell transistors “MT” and select transistors “ST1” and “ST2”. The memory cell transistor “MT” has a multilayer structure in which a floating gate electrode is formed on a principal surface of a semiconductor substrate with a gate insulating film interposed therebetween, a inter-gate insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-gate insulating film (not shown).
The memory cell transistors “MT” are disposed between the select transistors “ST1” and “ST2” in such a manner that the current circuits thereof are connected in series to each other.
The number of memory cell transistors “MT” is not limited to 8 but can be 16, 32 or 64, for example.
Similarly, the number of select transistors “ST1” and “ST2” is not necessarily limited to 2. As far as selection from among the NAND cells 1007 is possible, either of the select transistors “ST1” and “ST2” may be omitted.
The control electrodes of the memory cell transistors “MT” in the same column are connected to the word lines “WL1” to “WL8”, respectively. The gates of the select transistors “ST1”, which are included in the same row, are connected to the select gate line “SGD”, and the gates of the select transistors “ST2”, which are included in the same row, are connected to the select gate line “SGS”.
The drains of the select transistors “ST1”, which are included in the same row, are connected to bit lines “BL1” to “BLn”, respectively. The sources of the select transistors “ST2” are connected to a common source line “SL”, which is connected to a source line driver 1004.
The sense amplifier 1003 is configured to amplify data read from the selected memory cell transistor “MT”.
The source line driver 1004 is configured to apply a voltage to the source line “SL”.
FIG. 1 shows only a representative one block in the memory cell array 1002 and the internal configuration of the core part 1006 associated with the block. Actually, however, the memory cell array 1002 includes a plurality of blocks. The core part 1006 also includes transfer gate transistors “TGTD” and “TGTS” and a plurality of high-voltage insulated-gate field effect transistors TR associated with the plurality of blocks.
As shown in FIGS. 2 to 4, the semiconductor device 100 has a semiconductor substrate 7, a first high-voltage insulated-gate field effect transistor “TR1”, a second high-voltage insulated-gate field effect transistor “TR2”, a third high-voltage insulated-gate field effect transistor “TR3” and a fourth high-voltage insulated-gate field effect transistor “TR4”.
The first to fourth high-voltage insulated-gate field effect transistors “TR1” to “TR4” are formed on the principal surface of the semiconductor substrate 7.
The first and second high-voltage insulated-gate field effect transistors “TR1” and “TR2” are connected to memory cell transistors included in one block, which are simultaneously written, respectively.
The third and fourth high-voltage insulated-gate field effect transistors “TR3” and “TR4” are connected to memory cell transistors included another block (which is different from the block described above), which are simultaneously written, respectively.
The first device isolation insulating film 4 a is formed in the semiconductor substrate 7 in the gate length direction (in the longitudinal direction in FIG. 2) between the first high-voltage insulated-gate field effect transistor “TR1” and the second high-voltage insulated-gate field effect transistor “TR2”, and between the third high-voltage insulated-gate field effect transistor “TR3” and the fourth high-voltage insulated-gate field effect transistor “TR4”.
The first device isolation insulating film 4 a isolates the first high-voltage insulated-gate field effect transistor “TR1” and the second high-voltage insulated-gate field effect transistor “TR2” from each other. The first device isolation insulating film 4 a also isolates the third high-voltage insulated-gate field effect transistor “TR3” and the fourth high-voltage insulated-gate field effect transistor “TR4” from each other.
The second device isolation insulating film 4 b is formed in the semiconductor substrate 7 in the gate width direction (in the lateral direction in FIG. 2) between the first high-voltage insulated-gate field effect transistor “TR1” and the third high-voltage insulated-gate field effect transistor “TR3”, and between the second high-voltage insulated-gate field effect transistor “TR2” and the fourth high-voltage insulated-gate field effect transistor “TR4”.
The second device isolation insulating film 4 b isolates the first high-voltage insulated-gate field effect transistor “TR1” and the third high-voltage insulated-gate field effect transistor “TR3” from each other. The second device isolation insulating film 4 b also isolates the second high-voltage insulated-gate field effect transistor “TR2” and the fourth high-voltage insulated-gate field effect transistor “TR4” from each other.
As shown in FIGS. 2 to 4, a gate electrode 1 of the first high-voltage insulated-gate field effect transistor “TR1” and a gate electrode 1 of the second high-voltage insulated-gate field effect transistor “TR2” are connected to each other over the first device isolation insulating film 4 a. That is, these gate electrodes 1 are formed not only on the device region 12 but also on the device isolation insulating film 4 a with a gate insulating film interposed therebetween (not shown).
Similarly, a gate electrode 1 of the third high-voltage insulated-gate field effect transistor “TR3” and a gate electrode 1 of the fourth high-voltage insulated-gate field effect transistor “TR4” are connected to each other over the first device isolation insulating film 4 a. That is, these gate electrodes 1 are formed not only on the device region 12 but also on the device isolation insulating film 4 a with a gate insulating film interposed therebetween (not shown).
However, the gate electrodes of the first to fourth high-voltage insulated-gate field effect transistors “TR1”, “TR2” “TR3” and “TR4” are not formed on the second device isolation insulating film 4 b. That is, the gate electrodes of the first and second high-voltage insulated-gate field effect transistors “TR1” and “TR2”, which are adjacent to each other in the lateral direction in FIG. 2, are not connected to the gate electrodes of the third and fourth high-voltage insulated-gate field effect transistors “TR3” and “TR4”, which are adjacent to the first and second high-voltage insulated-gate field effect transistors “TR1” and “TR2” in the longitudinal direction.
Furthermore, the drain of the first high-voltage insulated-gate field effect transistor “TR1” and the drain of the third high-voltage insulated-gate field effect transistor “TR3” are adjacent to each other with the second device isolation insulating film 4 b interposed therebetween. Similarly, the drain of the second high-voltage insulated-gate field effect transistor “TR2” and the drain of the fourth high-voltage insulated-gate field effect transistor “TR4” are adjacent to each other with the second device isolation insulating film 4 b interposed therebetween.
Furthermore, as shown in FIG. 3, the second impurity diffusion layer 2 is formed to continuously extend below the two device isolation insulating films 4 b formed between the first and third high-voltage insulated-gate field effect transistors “TR1” and “TR3” and the p+ diffusion layer 8 formed between the two device isolation insulating films 4 b. The second impurity diffusion layer 2 includes an impurity diffusion layer 2 a and an impurity diffusion layer 2 b. The impurity diffusion layer 2 a is formed below the second device isolation insulating films 4 b. The impurity diffusion layer 2 b is also formed below the second device isolation insulating films 4 b. The impurity diffusion layers 2 a and 2 b function at least as a field inversion preventing layer.
In addition, as shown in FIGS. 2 and 5, the interlayer insulating film 10 is formed on the semiconductor substrate 7. The contact electrode 9 penetrating the interlayer insulating film 10 is connected to the n+ diffusion layer 6 to supply a potential to the source or drain of the first to fourth high-voltage insulated-gate field effect transistors “TR1” to “TR4”.
For example, a high electrical field having a voltage of about 10 to 30 V is applied to the gate electrode of the high-voltage insulated-gate field effect transistor “TR1”, which is a transfer gate transistor. Therefore, a depletion layer is formed in the well region between the first device isolation insulating films 4 a below the gate electrode 1. In this state, if the impurity concentration of the first impurity diffusion layer 5 is excessively high, the threshold voltage rises, and thus, the problem of the voltage of the word lines “WL1” to “WL8” is reduced in other to voltage drop transferred by the high-voltage insulated-gate field effect transistors.
For example, a potential difference of about 20 V can occur between the device regions adjacent to each other in the gate length direction (the longitudinal direction in FIG. 2). As an example, there will be described a case where data is written to a memory cell transistor connected to the first high-voltage insulated-gate field effect transistor “TR1”.
In this case, for example, a voltage of 24 V is applied to the gate electrodes of the first and second high-voltage insulated-gate field effect transistors “TR1” and “TR2”, a program voltage (23 V, for example) is applied to the drain of the first high-voltage insulated-gate field effect transistor “TR1”, and a pass voltage (13 V, for example) is applied to the drain of the second high-voltage insulated-gate field effect transistor “TR2”. Then, charges are injected to the floating gate electrode of the memory cell transistor connected to the first high-voltage insulated-gate field effect transistor “TR1”, and data is written to the memory cell transistor. In this process, a first potential difference “V1” between the drains is 10 V.
In this case, as described earlier, the third high-voltage insulated-gate field effect transistor “TR3” is connected to a memory cell transistor in another block. That is, the third high-voltage insulated-gate field effect transistor is not involved in data write of the relevant memory cell transistor, and therefore, a voltage of 0 V is applied to the drain of the third high-voltage insulated-gate field effect transistor “TR3”, for example. That is, a second potential difference “V2” between the drains of the first and third high-voltage insulated-gate field effect transistors “TR1” and “TR3” is 23 V.
As described above, in some cases, the second potential difference “V2” between the drain of the first high-voltage insulated-gate field effect transistor “TR1” and the drain of the third high-voltage insulated-gate field effect transistor “TR3” is greater than the first potential difference “V1” between the drain of the first high-voltage insulated-gate field effect transistor “TR1” and the drain of the second high-voltage insulated-gate field effect transistor “TR2”.
For the sake of simplicity, the following description will be particularly focused on the structures of the two high-voltage insulated-gate field effect transistors “TR1” and “TR3”.
The impurity diffusion layer 2 a is formed by ion implantation of boron ion (B) as a p-type impurity under the conditions that the acceleration is 200 keV to 300 keV and the concentration is about 1�1012/cm2 to 5�1013/cm2, for example. Reference character “X” in FIG. 7 represents the level of the peak of the p-type impurity concentration of the impurity diffusion layer 2 a. Then, a layout of the device regions 12 and 13 is formed by patterning using lithography, for example, and a trench is formed in the semiconductor substrate 7 by etching, such as RIE.
In the embodiment 1 described above, the semiconductor device includes the impurity diffusion layer 2 b, the p+ diffusion layer 8 and the device region 13.
As shown in FIGS. 10 and 11, as in the embodiment 1, the semiconductor device 200 has a semiconductor substrate 7, a first high-voltage insulated-gate field effect transistor “TR1”, a second high-voltage insulated-gate field effect transistor “TR2”, a third high-voltage insulated-gate field effect transistor “TR3” and a fourth high-voltage insulated-gate field effect transistor “TR4”.
The first and second device isolation insulating films 4 a and 4 b divide the semiconductor substrate 7 into a plurality of device regions 12, 13. Unlike the embodiment 1, the impurity diffusion layer 2 b and the p+ diffusion layer 8 are not formed between the first high-voltage insulated-gate field effect transistor “TR1” and the third high-voltage insulated-gate field effect transistor “TR3”.
Furthermore, as shown in FIG. 11, the second impurity diffusion layer 2 is formed below the second device isolation insulating film 4 b formed between the first and third high-voltage insulated-gate field effect transistors “TR1” and “TR3”. The second impurity diffusion layer 2 includes an impurity diffusion layer 2 a. Unlike the embodiment 1, there are not the p+ diffusion layer 8 and the device region 13, which are formed between separate second device isolation insulating films 4 b in the embodiment 1. That is, the first high-voltage insulated-gate field effect transistor “TR1” and the third high-voltage insulated-gate field effect transistor “TR3” are formed on the opposite sides of the second device isolation insulating film 4 b. The impurity diffusion layer 2 a is formed below the second device isolation insulating film 4 b. The impurity diffusion layer 2 a functions at least as a field inversion preventing layer.
Furthermore, since the p+ diffusion layer 8 and the device region 13 are not formed between the first high-voltage insulated-gate field effect transistor “TR1” and the third high-voltage insulated-gate field effect transistor “TR3”, the interval between the device regions in the longitudinal direction can be reduced.
The impurity diffusion layer 2 a is formed by ion implantation of boron ion (B) as a p-type impurity under the conditions that the acceleration is 200 keV to 300 keV and the concentration is about 1�1012/cm2 to 5�1013/cm2, for example. Reference character “X” in FIG. 12A represents the level of the peak of the p-type impurity concentration of the impurity diffusion layer 2 a. Then, a layout of the device regions 12 is formed by patterning using lithography, for example, and a trench is formed in the semiconductor substrate 7 by etching, such as RIE.
In the embodiment 2, the semiconductor device 200 that does not include the impurity diffusion layer 2 b, the p+ diffusion layer 8 and the device region 13 has been described.
As shown in FIGS. 14 and 15, as in the embodiment 1, the semiconductor device 300 has a semiconductor substrate 7, a first high-voltage insulated-gate field effect transistor “TR1”, a second high-voltage insulated-gate field effect transistor “TR2”, a third high-voltage insulated-gate field effect transistor “TR3” and a fourth high-voltage insulated-gate field effect transistor “TR4”.
The first and second device isolation insulating films 4 a and 4 b divide the semiconductor substrate 7 into a plurality of device regions 12, 13. Unlike the embodiment 1, the impurity diffusion layer 2 b is not formed between the first high-voltage insulated-gate field effect transistor “TR1” and the third high-voltage insulated-gate field effect transistor “TR3”.
Furthermore, as shown in FIG. 15, the second impurity diffusion layer 2 is formed to continuously extend below the two device isolation insulating films 4 b formed between the first and third high-voltage insulated-gate field effect transistors “TR1” and “TR3” and the p+ diffusion layer 8 formed between the two device isolation insulating films 4 b. The second impurity diffusion layer 2 includes an impurity diffusion layer 2 a. The impurity diffusion layer 2 a is formed to continuously extend below the two device isolation insulating films 4 b and the p+ diffusion layer 8 formed between the two device isolation insulating films 4 b. The impurity diffusion layer 2 a functions at least as a field inversion preventing layer.
The impurity diffusion layer 2 a is formed by ion implantation of boron ion (B) as a p-type impurity under the conditions that the acceleration is 200 keV to 300 keV and the concentration is about 1�1012/cm2 to 5�1013/cm2, for example. Reference character “X” in FIG. 16A represents the level of the peak of the p-type impurity concentration of the impurity diffusion layer 2 a. Then, a layout of the device regions 12 and 13 is formed by patterning using lithography, for example, and a trench is formed in the semiconductor substrate 7 by etching, such as RIE.
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name: KABUSHIKI KAISHA TOSHIBA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MAGOME, NORIO;MINAMI, TOSHIFUMI;HATANO, TOMOAKI;AND OTHERS;REEL/FRAME:022540/0558;SIGNING DATES FROM 20090306 TO 20090331Owner name: KABUSHIKI KAISHA TOSHIBA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MAGOME, NORIO;MINAMI, TOSHIFUMI;HATANO, TOMOAKI;AND OTHERS;SIGNING DATES FROM 20090306 TO 20090331;REEL/FRAME:022540/0558Apr 17, 2015REMIMaintenance fee reminder mailedSep 6, 2015LAPSLapse for failure to pay maintenance feesOct 27, 2015FPExpired due to failure to pay maintenance feeEffective date: 20150906RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services