Source: http://www.google.com/patents/US20060145270?dq=6,712,702
Timestamp: 2015-01-29 15:09:10
Document Index: 626172823

Matched Legal Cases: ['Application No. 2004', 'arts 15', 'arts 15', 'arts 35', 'arts 35', 'art 35', 'art 35']

Patent US20060145270 - Semiconductor device having silicide-blocking layer and fabrication method ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device having a silicide-blocking layer is provided. The device includes a field oxide layer defining an active region, source/drain regions in the active region of a substrate, a gate oxide layer and a gate electrode on the substrate between the source/drain regions, dielectric spacers...http://www.google.com/patents/US20060145270?utm_source=gb-gplus-sharePatent US20060145270 - Semiconductor device having silicide-blocking layer and fabrication method thereofAdvanced Patent SearchPublication numberUS20060145270 A1Publication typeApplicationApplication numberUS 11/320,303Publication dateJul 6, 2006Filing dateDec 29, 2005Priority dateDec 30, 2004Also published asUS7358574Publication number11320303, 320303, US 2006/0145270 A1, US 2006/145270 A1, US 20060145270 A1, US 20060145270A1, US 2006145270 A1, US 2006145270A1, US-A1-20060145270, US-A1-2006145270, US2006/0145270A1, US2006/145270A1, US20060145270 A1, US20060145270A1, US2006145270 A1, US2006145270A1InventorsChee ChoiOriginal AssigneeDongbuanam Semiconductor Inc.Export CitationBiBTeX, EndNote, RefManReferenced by (3), Classifications (14), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device having silicide-blocking layer and fabrication method thereofUS 20060145270 A1Abstract A semiconductor device having a silicide-blocking layer is provided. The device includes a field oxide layer defining an active region, source/drain regions in the active region of a substrate, a gate oxide layer and a gate electrode on the substrate between the source/drain regions, dielectric spacers on sidewalls of the gate electrode, and a silicide layer on both the gate electrode and the source/drain regions. The device also includes the silicide-blocking layer formed over the border between the field oxide layer and the source/drain regions. The silicide-blocking layer covers edges of the source/drain regions, obstructing the extension of the silicide layer. Images(5) Claims(6)
CROSS REFERENCE TO RELATED APPLICATIONS This U.S. non-provisional application claims priority under 35 U.S.C. �119 from Korean Patent Application No. 2004-117036, which was filed in the Korean Intellectual Property Office on Dec. 30, 2004, the contents of which are incorporated by reference herein in its entirety. BACKGROUND OF THE INVENTION 1. Technical Field The present invention relates generally to semiconductor integrated circuit (IC) device fabrication technology and, more particularly, to a semiconductor IC device having a silicide-blocking layer and a related fabrication method. 2. Description of the Related Art Metal oxide silicon (MOS) transistor, one of the field effect transistors (FETs), is generally composed of a gate placed on a silicon substrate and source/drain regions formed in the substrate at both sides of the gate. According to channel type, MOS transistors are classified into NMOS and PMOS. In addition, there is CMOS (complementary MOS) transistor in which both NMOS and PMOS transistors are formed together in the identical substrate. In fabrication of such MOS transistors, one of the critical issues is contact resistance between the gate or the source/drain region and metal layers. Silicide, alloys of silicon and metals, has been introduced as contact materials to reduce the contact resistance and thus to improve electrical properties of MOS transistors. Silicide combines the advantageous features of metal contacts (e.g., significantly lower resistivity than polysilicon) and polysilicon contacts (e.g., no electromigration). Silicide may be formed from a variety of metals such as titanium (Ti), cobalt (Co), vanadium (V), chromium (Cr), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), etc. As well known in the art, a silicide layer is formed by salicide (i.e., self-aligned silicide) process in which the silicide contacts are formed only in those areas where deposited metal is in direct contact with silicon, and hence self-aligned contacts are obtained. FIG. 1 shows, in a cross-sectional view, a convention semiconductor device having a suicide layer. Referring to FIG. 1, a field oxide layer 11 is formed in a silicon substrate 10 to define an active region, and a well region 12 is formed in the substrate 10. A gate oxide layer 13 and a gate electrode 14 are then formed on the substrate 10, and low doping parts 15 a of source/drain regions 15 are formed in the substrate 10. Dielectric spacers 16 are formed on sidewalls of the gate electrode 14, and high doping parts 15 b of the source/drain regions 15 are formed in the substrate 10. Then a suitable metal layer is conformally deposited and subjected to annealing. As a result, a silicide layer 17 is formed on both the gate electrode 14 and the source/drain regions 15. Such a silicide layer 17 may, however, have the following drawbacks. In a blanket etching process of forming the spacers 16, the field oxide layer 11 may be often damaged at the edges thereof as shown in FIG. 2. Hence the edges of the field oxide layer 11 are relatively lowered than the adjacent source/drain regions 15. That is, the source/drain regions 15 are partly exposed at the edges of the field oxide layer 11. Therefore, the silicide layer 17 may be unfavorably extended to the exposed portion of the source/drain regions 15. This extended portion of the silicide layer 17 may provide a path of leakage current, consequently degrading the characteristic of the device. SUMMARY OF THE INVENTION Exemplary, non-limiting embodiments of the present invention provide a semiconductor device having a silicide-blocking layer and a method of fabricating such a semiconductor device. According to one exemplary embodiment of the present invention, the semiconductor device comprises a silicon substrate having a field oxide layer formed therein to define an active region, source/drain regions formed in the active region of the substrate, a gate oxide layer and a gate electrode formed on the substrate between the source/drain regions, dielectric spacers formed on sidewalls of the gate electrode, and a silicide layer formed on both the gate electrode and the source/drain regions. The semiconductor device further comprises a silicide-blocking layer formed over the border between the field oxide layer and the source/drain regions. The silicide-blocking layer covers edges of the source/drain regions, obstructing the extension of the silicide layer. In the device, the edges of the source/drain regions may be higher than edges of the field oxide layer, and the silicide-blocking layer may cover the higher edges of the source/drain regions. According to one exemplary embodiment of the present invention, the method comprises forming a field oxide layer in a silicon substrate to define an active region, forming a gate oxide layer and an overlying gate electrode on the active region of the substrate, forming dielectric spacers on sidewalls of the gate electrode, forming source/drain regions in the active region of the substrate, forming a silicide-blocking layer over the border between the field oxide layer and the source/drain regions, and forming a silicide layer on both the gate electrode and the source/drain regions except the blocking layer. In the method, the forming of the silicide-blocking layer may include depositing an insulating layer over the substrate and selectively etching the insulating layer. The silicide-blocking layer may be formed of silicon oxide or silicon nitride. The silicide-blocking layer may be formed of the same material as the dielectric spacers.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a conventional semiconductor device having a silicide layer. FIG. 2 is an enlarged view of section �A� of FIG. 1. FIG. 3 is a cross-sectional view showing a semiconductor device having a silicide-blocking layer in accordance with an exemplary embodiment of the present invention. FIGS. 4A to 4E are cross-sectional views illustrating a method of fabricating the semiconductor device shown in FIG. 3.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION An exemplary, non-limiting embodiment of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed to be limited to the exemplary embodiment set forth herein. Rather, the disclosed embodiment is provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The principles and features of this invention may be employed in varied and numerous embodiments without departing from the scope of the invention. In is noted that well-known structures and processes are not described or illustrated in detail to avoid obscuring the essence of the present invention. It is also noted that the figures are not drawn to scale. FIG. 3 is a cross-sectional view showing a semiconductor device having a silicide-blocking layer in accordance with an exemplary embodiment of the present invention. Referring to FIG. 3, a silicon substrate 30 has a field oxide layer 31 formed therein to define an active region. Further formed in the substrate 30 are a well region 32 and source/drain regions 35. A gate oxide layer 33 and a gate electrode 34 are formed on the substrate 30 between the source/drain regions 35. Dielectric spacers 36 are formed on sidewalls of the gate electrode 34. The source/drain regions 35 have low doping parts 35 a and high doping parts 35 b. A silicide layer 37 is formed on both the gate electrode 34 and the source/drain regions 35. In addition, a silicide-blocking layer 38 is formed over the border between the field oxide layer 31 and the source/drain regions 35. The silicide-blocking layer 38 covers edges of the source/drain regions 35 and obstructs the extension of the suicide layer 37. FIGS. 4A to 4E are cross-sectional views illustrating a method of fabricating the semiconductor device shown in FIG. 3. Referring to FIG. 4A, the field oxide layer 31 is partially formed in the silicon substrate 30 to define the active region. Typical STI (shallow trench isolation) technique is often used for forming the field oxide layer 31. The well region 32 is then formed in the substrate 30 by using well-known ion implantation. Next, referring to FIG. 4B, the gate oxide layer 33 is thermally grown on the substrate 30 and a gate conductor layer such as polysilicon is deposited thereon. The gate conductor layer is then etched together with the gate oxide layer 33 to form the gate electrode 34. The low doping part 35 a of the source/drain regions 35 is formed in the active region of the substrate 30, using the gate electrode 34 as an implant mask. Next, referring to FIG. 4C, suitable dielectric material is deposited over the substrate 30 and blanket-etched. Consequently, the dielectric spacers 36 are formed on sidewalls of the gate electrode 34. Then the high doping part 35 b of the source/drain regions 35 is further formed in the active region of the substrate 30, using both the spacers 36 and the gate electrode 34 as an implant mask. While the blanket etching is performed, the field oxide layer 31 may be damaged at edges thereof as discussed above. Hence the edges of the adjacent source/drain regions 35 become higher than the edges of the field oxide layer 31, being partly exposed. Referring to FIG. 4D, an insulating layer of silicon oxide or silicon nitride is deposited to cover the substrate 30 and then selectively etched. Thus, the silicide-blocking layer 38 is formed over the border between the field oxide layer 31 and the source/drain regions 35, covering the exposed higher edges of the source/drain regions 35. Therefore, in the subsequent salicide process, the blocking layer 38 prevents the silicide layer from being formed on the edges of the source/drain regions 35. In an alternative embodiment, the silicide-blocking layer 38 may be simultaneously formed during the spacer formation discussed earlier. In this case, the blocking layer 38 may be formed of the same material as the dielectric spacers 36. FIG. 4E shows the suicide layer 37. To form the silicide layer 37, an adequate metal layer is conformally deposited over the substrate 30 and then subjected to annealing. As a result, the silicide layer 37 is formed on both the gate electrode 34 and the source/drain regions 35 except the blocking layer 38. While this invention has been particularly shown and described with reference to an exemplary embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7572705 *Sep 21, 2005Aug 11, 2009Advanced Micro Devices, Inc.Semiconductor device and method of manufacturing a semiconductor deviceUS7732298 *Jan 31, 2007Jun 8, 2010Taiwan Semiconductor Manufacturing Company, Ltd.Metal salicide formation having nitride liner to reduce silicide stringer and encroachmentUS20100163938 *Dec 28, 2009Jul 1, 2010Dong-Ho ParkMethod for forming silicide in semiconductor device* Cited by examinerClassifications U.S. Classification257/384, 438/300, 257/E21.206, 257/E21.438, 257/E29.266International ClassificationH01L29/76, H01L21/336Cooperative ClassificationH01L29/7833, H01L29/6659, H01L21/28123, H01L29/665European ClassificationH01L29/66M6T6F3, H01L21/28E2B30, H01L29/78FLegal EventsDateCodeEventDescriptionSep 20, 2011FPAYFee paymentYear of fee payment: 4Jul 11, 2006ASAssignmentOwner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: CHANGE OF NAME;ASSIGNOR:DONGBUANAM SEMICONDUCTOR INC.;REEL/FRAME:018093/0282Effective date: 20060324Owner name: DONGBU ELECTRONICS CO., LTD.,KOREA, REPUBLIC OFFree format text: CHANGE OF NAME;ASSIGNOR:DONGBUANAM SEMICONDUCTOR INC.;US-ASSIGNMENT DATABASE UPDATED:20100427;REEL/FRAME:18093/282Dec 29, 2005ASAssignmentOwner name: DONGBUANAM SEMICONDUCTOR INC., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHOI, CHEE HONG;REEL/FRAME:017429/0795Effective date: 20051220RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services