Source: http://www.google.com/patents/US20090086808?ie=ISO-8859-1
Timestamp: 2014-03-16 04:36:10
Document Index: 299741256

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US20090086808 - Equalization And Decision-Directed Loops With Trellis Demodulation In High ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsImproved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals....http://www.google.com/patents/US20090086808?utm_source=gb-gplus-sharePatent US20090086808 - Equalization And Decision-Directed Loops With Trellis Demodulation In High Definition TVAdvanced Patent SearchPublication numberUS20090086808 A1Publication typeApplicationApplication numberUS 12/330,064Publication dateApr 2, 2009Filing dateDec 8, 2008Priority dateNov 3, 1998Also published asUS6775334, US7474695, US8098725, US20040258184Publication number12330064, 330064, US 2009/0086808 A1, US 2009/086808 A1, US 20090086808 A1, US 20090086808A1, US 2009086808 A1, US 2009086808A1, US-A1-20090086808, US-A1-2009086808, US2009/0086808A1, US2009/086808A1, US20090086808 A1, US20090086808A1, US2009086808 A1, US2009086808A1InventorsTian-Min Liu, Loke Kun Tan, Steven T. JaffeOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManReferenced by (4), Classifications (47), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetEqualization And Decision-Directed Loops With Trellis Demodulation In High Definition TVUS 20090086808 A1Abstract Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE's ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.
a Trellis coded modulation (TCM) decoder to provide a maximum likelihood decision based on a current symbol; and a DFE to process the maximum likelihood decision with one or more first equalization coefficients to provide a weighted maximum likelihood decision; and a first summing junction to combine the weighted maximum likelihood decision and one or more symbol samples to provide the current symbol. 2. The decision directed equalization circuit of claim 1, wherein the TCM decoder determines a maximum likelihood sequence path, and wherein the TCM decoder provides the maximum likelihood decision based upon the maximum likelihood sequence path.
3. The decision directed equalization circuit of claim 2, wherein the TCM decoder determines correlations between the current symbol and one or more intermediate maximum likelihood decisions to determine the maximum likelihood sequence path.
4. The decision directed equalization circuit of claim 3, wherein the TCM decoder determines correlations between the current symbol and the one or more intermediate maximum likelihood decisions by maximum likelihood sequence estimation.
5. The decision directed equalization circuit of claim 1, wherein the maximum likelihood decision includes one symbol from at least one of a current maximum likelihood decision and one or more intermediate maximum likelihood decisions.
6. The decision directed equalization circuit of claim 5, wherein the DFE processes the one symbol from the at least one of the current maximum likelihood decision and the one or more intermediate maximum likelihood decisions with the one or more first equalization coefficients.
7. The decision directed equalization circuit of claim 1, wherein the maximum likelihood decision includes more than one symbol from at least one of a current maximum likelihood decision and one or more intermediate maximum likelihood decisions.
8. The decision directed equalization circuit of claim 7, wherein the DFE processes the more than one symbol from the at least one of the current maximum likelihood decision and the one or more intermediate maximum likelihood decisions with the one or more first equalization coefficients.
a first delay circuit configured to delay the current symbol by a first delay; and a symbol timing reference loop to provide a symbol timing reference based on an output of the first delay circuit and the maximum likelihood decision, wherein the first delay causes an output of the first delay circuit to have a substantially similar time stamp as the maximum likelihood decision. 10. The decision directed equalization circuit of claim 1, further comprising:
a second delay circuit configured to delay the current symbol by a second delay; and a carrier loop configured to estimate at least one of: an angle of an output of the second delay circuit and a phase of the output of the second delay circuit based on the maximum likelihood decision, wherein the second delay causes the output of the second delay circuit to have a substantially similar time stamp as the maximum likelihood decision. 11. The decision directed equalization circuit of claim 1, further comprising:
a feedword equalizer (FFE) to process an input signal with one or more second equalization coefficients to provide the one or more symbol samples. 12. The decision directed equalization circuit of claim 11, further comprising:
a third delay circuit configured to delay the current symbol by a third delay; and a second summing junction configured to combine an output of the third delay circuit and the maximum likelihood decision to produce an error term, wherein the third delay causes the output of the third delay circuit to have a substantially similar time stamp as the maximum likelihood decision. 13. The decision directed equalization circuit of claim 12, wherein the error term is used to drive at least one of:
a coefficient tap update of the FFE; and a coefficient tap update of the DFE. 14. The decision directed equalization circuit of claim 1, wherein the TCM decoder comprises:
a decision device configured to calculate a path metric for one or more states of the current symbol; a path metrics module to produce a selection signal based on the path metric; a path memory module including one or more traceback registers, wherein each traceback register corresponds to a respective one of the one or more states; and a multiplexer to select one of the one or more traceback registers based on the selection signal to provide the maximum likelihood decision, wherein at least one of the path memory module and the path metrics module includes one or more intermediate likelihood decisions. 15. The decision directed equalization circuit of claim 14, wherein the path metric represents a distance between each of the one or more states and the current symbol.
(a) providing a maximum likelihood decision based on a current symbol; and (b) processing the maximum likelihood decision with one or more first equalization coefficients to provide a weighted maximum likelihood decision; and (c) combining the weighted maximum likelihood decision and one or more symbol samples to provide the current symbol. 17. The method of claim 16, wherein step (a) comprises:
(a)(i) determining a maximum likelihood sequence path (a)(ii) providing the maximum likelihood decision based upon the maximum likelihood sequence path. 18. The method of claim 17, wherein step (a)(i) comprises:
(a)(i)(A) determining correlations between the current symbol and one or more intermediate maximum likelihood decisions to determine the maximum likelihood sequence path. 19. The method of claim 18, wherein step (a)(i)(A) comprises:
(a)(i)(A)(1) determining correlations between the current symbol and the one or more intermediate maximum likelihood decisions by maximum likelihood sequence estimation. 20. The method of claim 16, wherein step (a) comprises:
(a)(i) providing one symbol from at least one of a current maximum likelihood decision and one or more intermediate maximum likelihood decisions based on the current symbol. 21. The method of claim 20, wherein step (b) comprises:
(b)(i) processing the one symbol from at least one of the current maximum likelihood decision and the one or more intermediate maximum likelihood decisions with the one or more first equalization coefficients to provide the weighted maximum likelihood decision. 22. The method of claim 16, wherein step (a) comprises:
(a)(i) providing more than one symbol from at least one of a current maximum likelihood decision and one or more intermediate maximum likelihood decisions based on the current symbol. 23. The method of claim 22, wherein step (b) comprises:
(b)(i) processing the more than one symbol from at least one of the current maximum likelihood decision and the one or more intermediate maximum likelihood decisions with the one or more first equalization coefficients to provide the weighted maximum likelihood decision. 24. The method of claim 16, further comprising:
(d) delaying the current symbol by a first delay to provide a first delayed symbol, wherein the first delay causes the first delayed symbol to have a substantially similar time stamp as the maximum likelihood decision; and (e) providing a symbol timing reference based on the first delayed symbol and the maximum likelihood decision. 25. The method of claim 16, further comprising:
(d) delaying the current symbol by a second delay to provide a second delayed symbol, wherein the second delay causes the second delayed symbol to have a substantially similar time stamp as the maximum likelihood decision; and (e) estimating at least one of: an angle of the second delayed symbol and a phase of the output of the second delayed symbol based on the maximum likelihood decision. 26. The method of claim 16, further comprising:
(d) processing an input signal with one or more second equalization coefficients to provide the one or more symbol samples. 27. The method of claim 26, further comprising:
(e) delaying the current symbol by a third delay to provide a third delayed symbol, wherein the third delay causes the third delayed symbol to have a substantially similar time stamp as the maximum likelihood decision; and (f) combining the third delayed symbol and the maximum likelihood decision to produce an error term. 28. The method of claim 27, further comprising:
(g) driving a coefficient tap update using the error term. 29. The method of claim 16, wherein step (a) comprises:
(a)(i) calculating a path metric for one or more states of the current symbol; (a)(ii) producing a selection signal based on the path metric; (a)(iii) select a respective one of the one or more states based on the selection signal to provide the maximum likelihood decision. 30. The method of claim 29, wherein step (a)(i) comprises:
(a)(i)(A) determining a distance between each of the one or more states and the current symbol. Description
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 10/895,879, filed Jul. 21, 2004, which is a continuation of U.S. patent application Ser. No. 09/433,733, filed Nov. 3, 1999, which claims the benefit of: U.S. Provisional Patent Application No. 60/106,921, filed Nov. 3, 1998; U.S. Provisional Patent Application No. 60/106,922, filed Nov. 3, 1998; U.S. Provisional Patent Application No. 60/106,923, filed Nov. 3, 1998; U.S. Provisional Patent Application No. 60/106,938, filed Nov. 3, 1998; U.S. Provisional Patent Application No. 60/107,103, filed Nov. 4, 1998; and U.S. Provisional Patent Application No. 60/107,037, filed Nov. 3, 1998, each of which is incorporated by reference herein in its entirety.
However, a 4-bit representation of each of the 256 QAM symbol points in the two's compliment numbering system can be expressed as {100 b, 1001 b, 1010b, 1011b, 1100b, 1101b, 1110b, 1111b, 0000b, 0001b, 0010b, 0011b, 0100b, 0101 b, 0110b, 0111b} which, when expressed in common numerical form represents an input signal, denoted by z(n), which takes on the discrete values {− 16/16, − 14/16, − 12/16, − 10/16, −fraction 8/16, − 6/16, − 4/16, − 2/16, 0, 2/16, 4/16, 6/16, 8/16, 10/16, 12/16 and 14/16}. Thus, it will be understood that the effective input signal z(n), when processed, would give symbol quantization results that are incorrect by a fixed offset, equal to − 1/16, and which is denoted herein by a. Since − 1/16 may be represented by the binary value 00001 in two's compliment, the − 1/16 fixed offset may be corrected by adding a=00001 to z(n) as a correction factor.
y  ( n ) = ∑ k  d  ( k )  x  ( n - k ) . However, if the input signal to the exemplary filter of FIG. 15 is viewed as including an input stimulus portion and a fixed offset portion, the input signal could be expressed as x(n)=z(n)+a. Given this particular mathematical relationship, and substituting terms in the filter response characteristic, the filter output might be represented as
y  ( n ) = ∑ k  d  ( k )  z  ( n - k ) + ∑ k  d  ( k )  a , where a represents the fixed offset term and z(n) represents the input stimulus.
∑ k  d  ( k )  a is added to the output of the decision feedback filter 220 at the summing junction 226 down-stream from the output of the decision feedback filter.
Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7720165 *Nov 14, 2006May 18, 2010Realtek Semiconductor Corp.Demapper applied to quadrature amplitude modulation trellis coded modulation decoder and related methodUS8121183 *Jul 13, 2007Feb 21, 2012Lsi CorporationSystem for an adaptive floating tap decision feedback equalizerUS8526542Apr 25, 2011Sep 3, 2013Samsung Electronics Co., Ltd.Diversity receiver for processing VSB signalUS20130128946 *Nov 22, 2011May 23, 2013Lsi CorporationMethod of optimizing floating dfe receiver taps* Cited by examinerClassifications U.S. Classification375/233International ClassificationH04L27/00, H04N11/00, H04N5/44, H04L25/03, H04L27/34, H04N5/21, H04L27/06, H04L27/02, H04B1/68, H04L27/227, H04N5/46, H04L27/01, H04L27/38Cooperative ClassificationH04L2027/0032, H04L2025/03503, H04N5/44, H04L27/3827, H04L27/066, H04B1/68, H04L2025/0349, H04L2027/0042, H04N5/211, H04L2027/0067, H04N5/4401, H04L25/03057, H04L2027/0057, H04L27/02, H04L2027/0087, H04L27/3427, H04L2025/03382, H04N5/46, H04L2025/0342, H04N11/002, H04N5/21, H04L27/2273European ClassificationH04N5/21, H04L27/06C, H04L27/02, H04L27/227A3, H04N5/46, H04L27/38C1, H04N5/21A, H04N5/44N, H04L25/03B1A7, H04B1/68, H04L27/34C3CLegal EventsDateCodeEventDescriptionFeb 5, 2013CCCertificate of correctionDec 8, 2008ASAssignmentOwner name: BROADCOM CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIU, TIAN-MIN;TAN, LOKE KUN;JAFFE, STEVEN T.;REEL/FRAME:021939/0825Effective date: 19991103RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google