Source: http://www.google.com/patents/US7110227?dq=3798359
Timestamp: 2014-10-23 17:38:38
Document Index: 524902721

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US7110227 - Universial energy conditioning interposer with circuit architecture - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a...http://www.google.com/patents/US7110227?utm_source=gb-gplus-sharePatent US7110227 - Universial energy conditioning interposer with circuit architectureAdvanced Patent SearchPublication numberUS7110227 B2Publication typeGrantApplication numberUS 10/237,079Publication dateSep 19, 2006Filing dateSep 9, 2002Priority dateApr 8, 1997Fee statusPaidAlso published asUS20030067730, US20030206388Publication number10237079, 237079, US 7110227 B2, US 7110227B2, US-B2-7110227, US7110227 B2, US7110227B2InventorsAnthony A. Anthony, William M. AnthonyOriginal AssigneeX2Y Attenuators, LlcExport CitationBiBTeX, EndNote, RefManPatent Citations (107), Non-Patent Citations (72), Referenced by (5), Classifications (39), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetUniversial energy conditioning interposer with circuit architectureUS 7110227 B2Abstract The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.
1. An integral capacitor comprising:
a power plane having a power surface and a power periphery, the power plane coupling power to signals of an integrated circuit operating at a fundamental frequency; a first ground plane having a first ground surface and a first ground periphery, the first ground plane coupling ground to the signals, the first ground plane being separated from the power plane by a first distance, the first ground surface being larger than the power surface; the first ground periphery extending at least a second distance from the power periphery, the second distance being at least larger than N times the first distance; and a dielectric layer formed between the power plane and the first ground plane. 2. The integral capacitor of claim 1 further comprising:
a second ground plane having a second ground surface and a second ground periphery, the second ground plane being separated from the power plane by the third distance; the second ground surface being larger than the power surface and the second ground periphery extending at least a fourth distance from the power periphery; the fourth distance being at least larger than M times the third distance, the second ground plane being coupled to the first ground plane by a via chain connecting a first plurality of vias located around the first ground periphery to a second plurality of vias located around the second ground periphery; and the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency. 3. The integral capacitor of claim 1 wherein the dielectric layer is made of a dielectric material having a high dielectric constant.
4. The integral capacitor of claim 1 wherein N is an integer ranging from 1 to 20.
5. The integral capacitor of claim 1 wherein M is an integer ranging from 1 to 20.
6. The integral capacitor of claim 1 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
7. The integral capacitor of claim 6 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.
8. The integral capacitor of claim 1 further comprises a contact array to connect to at least the first ground plane and the power plane.
9. The integral capacitor of claim 8 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array.
10. The integral capacitor of claim 9 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
11. A packaged device comprising:
a die containing an integrated circuit; a plurality of controlled collapse chip connection (C4) bumps attaching the die to a substrate; and an integral capacitor attaching to the die to reduce radiation, the integral capacitor comprising: a power plane having a power surface and a power periphery, the power plane coupling power to signals of an integrated circuit operating at a fundamental frequency, a first ground plane having a first ground surface and a first ground periphery, the first ground plane coupling ground to the signals, the first ground plane being separated from the power plane by a first distance, the first ground surface being larger than the power surface and the first ground periphery extending at least a second distance from the power periphery, the second distance being at least larger than N times the first distance, and a dielectric layer formed between the power plane and the first ground plane. 12. The packaged device of claim 11 wherein the integral capacitor further comprising:
a second ground plane having a second ground surface and a second ground periphery, the second ground plane being separated from the power plane by the third distance, the second ground surface being larger than the power surface and the second ground periphery extending at least a fourth distance from the power periphery, the fourth distance being at least larger than M times the third distance, the second ground plane being coupled to the first ground plane by a via chain connecting a first plurality of vias located around the first ground periphery to a second plurality of vias located around the second ground periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency. 13. The packaged device of claim 12 wherein the dielectric layer is made of a dielectric material having a high dielectric constant.
14. The packaged device of claim 11 wherein N is an integer ranging from 1 to 20.
15. The packaged device of claim 11 wherein M is an integer ranging from 1 to 20.
16. The packaged device of claim 11 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
17. The packaged device of claim 16 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.
18. The packaged device of claim 11 wherein the integral capacitor further comprises a contact array to connect to at least the first ground plane and the power plane.
19. The packaged device of claim 18 wherein the contact array is one of a C4) bump array, a BGA ball array, and a FCPGA pin array.
20. The packaged device of claim 19 wherein the ground plane has a plurality 15 of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter, wavelength of the fundamental frequency.
coupling power to signals of an integrated circuit operating at a fundamental frequency by a power plane having a power surface and a power periphery; coupling ground to the signals by a first ground plane having a first ground surface 5 and a first ground periphery, the first ground plane being separated from the power plane by a first distance, the first ground surface being larger than the power surface and the first ground periphery extending at least a second distance from the power periphery, the second distance being at least larger than N times the first distance; and forming a dielectric layer between the power plane and the first ground plane. 22. The method of claim 21 further comprising:
coupling a second ground plane to the first ground plane by a via chain, the second ground plane having a second ground surface and a second ground periphery, the second ground plane being separated from the power plane by the third distance, the second ground surface being larger than the power surface and the second ground periphery extending at least a fourth distance from the power periphery, the fourth distance being at least larger than M times the third distance, the via chain connecting a first plurality of vias located around the first ground periphery to a second plurality of vias located around the second ground periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency. 23. The method of claim 22 wherein the dielectric layer is made of a dielectric material having a high dielectric constant.
24. A method of claim 21 wherein N is an integer ranging from 1 to 20.
25. The method of claim 21 wherein M is an integer ranging from 1 to 20.
26. The method of claim 21 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
27. The method of claim 26 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.
28. The method of claim 21 further comprises connecting to at least the first ground plane and the power plane by a contact array.
29. The method of claim 28 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array.
30. The method of claim 29 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
31. An energy conditioner comprising;
a first pathway having a first surface and a first perimeter, and the first pathway coupled to an integrated circuit; a second pathway having a second surface and a second perimeter, and the second pathway coupled to the integrated circuit; the second pathway being separated from the first pathway by a first distance; the second surface being larger than the first surface; the second perimeter extending at least a second distance from the first perimeter; the second distance being at least larger than a number times the first distance; and a dielectric layer formed between the first pathway and the second pathway. 32. An enclosure comprising:
a power plane having a power surface and a power periphery, the power plane coupling power to signals of an integrated circuit operating at a fundamental frequency; and first and second ground planes having first and second ground surfaces and first and second ground peripheries, the first and second ground planes coupling ground to the signals, the first and second ground planes being separated from the power plane by first and second distances, respectively, the first and second ground surfaces being larger than the power surface, the first and second ground peripheries extending at least third and fourth distances from the power peppery, respectively, the third and fourth distances being N and M times larger than the first and second distances, respectively. 33. The enclosure of claim 32 wherein the first and second ground planes have first and second pluralities of vias located around the first and second ground peripheries, respectively, and outside the power periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency, the first and second pluralities of vias being connected by a via chain.
34. The enclosure of claim 33 wherein the signals are on a signal plane located between the power plane and the second ground plane.
35. The enclosure of claim 32 wherein N is an integer ranging from 1 to 20.
36. The enclosure of claim 32 wherein M is an integer ranging from 1 to 20.
37. The enclosure of claim 32 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
38. The enclosure of claim 37 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.
39. The enclosure of claim 32 further comprises a contact array to connect to at least the first ground plane and the power plane.
40. The enclosure of claim 39 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array.
41. The enclosure of claim 40 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
a die containing an integrated circuit having signals operating at a fundamental frequency; a plurality of controlled collapse chip connection (C4) bumps attaching the die to a substrate; and an enclosure attaching to the die to reduce radiation, the enclosure comprising: a power plane having a power surface and a power periphery, the power plane coupling power to the signals of the integrated circuit, and first and second ground planes having first and second ground surfaces and first and second ground peripheries, the first and second ground planes coupling ground to the signals, the first and second ground planes being separated from the power plane by first and second distances, respectively, the first and second ground surfaces being larger than the power surface, the first and second ground peripheries extending at least third and fourth distances from the power periphery, respectively, the third and fourth distances being N and M times larger than the first and second distances, respectively. 43. The packaged device of claim 42 wherein the first and second ground planes have first and second pluralities of vias located around the first and second ground peripheries, respectively, and outside the power periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency, the first and second pluralities of vias being connected by a via chain.
44. The packaged device of claim 43 wherein the signals are on a signal plane located between the power plane and the second ground plane.
45. The packaged device of claim 42 wherein N is an integer ranging from 1 to 20.
46. The packaged device of claim 42 wherein M is an integer ranging from 1 to 20.
47. The packaged device of claim 42 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
48. The packaged device of claim 47 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.
49. The packaged device of claim 42 wherein the enclosure further comprises a contact array to connect to at least the first ground plane and the power plane.
50. The packaged device of claim 49 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array.
51. The packaged device of claim 50 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
coupling power to signals of an integrated circuit operating at a fundamental frequency by a power plane having a power surface and a power periphery; and coupling pound to the signals by first and second ground planes having first and second ground surfaces and first and second ground peripheries, the first and second ground planes being separated from the power plane by first and second distances, respectively, the first and second ground surfaces being larger than the power surface, the first and second ground peripheries extending at least third and fourth distances from the power periphery, respectively, the third and fourth distances being N and M times larger than the first and second distances, respectively. 53. The method of claim 52 wherein the first and second ground planes have first and second pluralities of vias located around the first and second ground peripheries, respectively, and outside the power periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency, the first and second pluralities of vias being connected by a via chain.
54. The method of claim 53 wherein the signals are on a signal plane located between the power plane and the second ground plane.
55. The method of claim 52 wherein N is an integer ranging from 1 to 20.
56. The method of claim 52 wherein M is an integer ranging from 1 to 20.
57. The method of claim 52 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
58. The method of claim 57 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.
59. The method of claim 52 further comprises connecting to at least the first ground plane and the power plane by a contact array.
60. The method of claim 59 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array.
61. The method of claim 60 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
This application is a continuation-in-part of application Ser. No. 09/600,530, which is a U.S. national stage application of international application PCT/US99/01040, filed Jan. 16, 1999, now issued as U.S. Pat. No. 6,498,710, and a continuation-in-part of application Ser. No. 09/632,048, filed Aug. 3, 2000, which is a continuation-in-part of co-pending application Ser. No. 09/594,447, filed Jun. 15, 2000, which is a continuation-in-part of application Ser. No. 09/579,606, filed May 26, 2000, now issued as U.S. Pat. No. 6,373,673, which is a continuation-in-part of application Ser. No. 09/460,218, filed Dec. 13, 1999, now issued as U.S. Pat. No. 6,331,926, which is a continuation of application Ser. No. 09/056,379, filed Apr. 7, 1998, now issued as U.S. Pat. No. 6,018,448, which is a continuation-in-part of application Ser. No. 09/008,769, filed Jan. 19, 1998, now issued as U.S. Pat. No. 6,097,581, which is a continuation-in-part of application Ser. No. 08/841,940, filed Apr. 8, 1997, now issued as U.S. Pat. No. 5,909,350, application Ser. No. 09/579,606 claims the benefit of U.S. Provisional Application No. 60/136,451, filed May 28, 1999, U.S. Provisional Application No. 60/139,182, filed Jun. 15, 1999, U.S. Provisional Application No. 60/146,987, filed Aug. 3, 1999, U.S. Provisional Application No. 60/165,035, filed Nov. 12, 1999, U.S. Provisional Application No. 60/180,101, filed Feb. 3, 2000, U.S. Provisional Application No. 60/185,320, filed Feb. 28, 2000, U.S. Provisional Application No. 60/200,327, filed Apr. 28, 2000, and U.S. Provisional Application No. 60/203,863, filed May 12, 2000, and application Ser. No. 09/632,048 claims the benefit of U.S. Provisional Application No. 60/191,196, filed Mar. 22, 2000 and U.S. Provisional Application No. 60/215,314, filed Jun. 30, 2000.
Processor operating frequency (speed) is now matched by the development and deployment of ultra-fast RAM (Random Access Memory) architectures. These breakthroughs have allowed an increase of the overall system�operating frequency (speed) of the active components past the 1 GHz mark. During this same period, however, passive component technologies have failed to keep up with these new breakthroughs and have produced only incremental changes in composition and performance. These advances in passive component design and changes have focused primarily upon component size reduction, slight modifications of discrete component electrode layering, dielectric discoveries, and modifications of device manufacturing techniques or rates of production that decrease unit production cycle times.
Numerous other arrangements and configurations are also disclosed which implement and build upon the above objects and advantages of the invention in order to demonstrate the versatility arid wide spread application of a universal energy conditioning interposer with circuit architecture for energy and EMI conditioning and protection within the scope of the present invention.
Equally so, the invention is not limited: to any possible conductive material such as magnetic, nickel-based materials, MOV-type material, ferrite material;�any substances and processes that can create conductive pathways for a conductive material such as Mylar films or printed circuit board materials; or any substances or processes that can create conductive areas such as, but not limited to, doped polysilicons, sintered polycrystallines, metals, or polysilicon silicates, polysilicon silicide. When or after the structured layer arrangement is manufactured as an interposer it is not limited to just IC packages, it can be combined with, shaped, buried within or embedded, enveloped, or inserted into various electrical packaging, other substrates, boards, electrical arrangements, electrical systems or other electrical sub-systems to perform simultaneous energy conditioning, decoupling, so to aid in modifying an electrical transmission of energy into a desired electrical form or electrical shape.
The invention will also provide for simultaneous physical and electrical shielding to portions an active chip structure as well as for internally propagating energies within the new structure by allowing predetermined, simultaneous energy interactions to take place between grouped and energized�conductive pathways to be fed by pathways external to the embodiment elements.
A superior approach when utilizing various interconnection platforms and methodologies for direct IC chip attachment configurations to a PCB or other package connections is to provide low impedance from the energy pathways or electrode planes using a single embodiment. It is impractical to utilize many discrete, low impedancede-coupling capacitors on an interposer or PCB, if low impedance energy planes are not available to hook them up.
By surrounding predetermined conductive pathway electrodes with cage-like structures made up with one centralized and shared, common conductive pathway or area, this common pathway or area becomes a 0-reference common conductive pathway for circuit voltages and exists between at least two oppositely phased or voltage potential conductive structures which in turn are located each respectively on opposite sides of the just described sandwiched centralized and shared, common conductive pathway or area.
Low inductance is advantageous in modern l/O and high-speed data lines as the increased switching speeds and fast pulse rise times of modern equipment create unacceptable voltage spikes which can only be managed by low inductance surge devices and networks. It should also be evident that labor intensive aspects of using multi-functional energy conditioner 10 as compared to combining discrete components found in the prior art provides an easy and cost effective method of manufacturing. Because connections only need to be made to either ends of electrical conductors 12 to provide a line to line capacitance to the circuit that is approximately half the value of the capacitance measured for each of the line to common conductive pathway capacitance also developed internally within the embodiment. This provides flexibility for the user as well as providing a potential savings in time and space in manufacturing a larger electrical system utilizing the invention.
In FIG. 3, differential conductive by-pass electrode pathway 809 is sandwiched between the shared, central common conductive pathway 804/804-IM of structure 20 and common conductive pathway 810 (not shown in FIG. 3), which is seated above pathway 809 in depiction FIG. 4. Positioned above and below by-pass pathway 809 is a dielectric material or medium 801. Common conductive pathways 804/804-IM and 810, as well as pathway 809, are all separated from each other for the most part by a general parallel interposition of a predetermined dielectric material or medium 801, which is placed or deposited during the manufacturing process between each of said conductive pathway applications. All of the conductive common conductive pathways 860/860-IM, 840, 804/804-IM, 810, 830, and 850/850-IM are offset a pre-determined distance 814 from the outer edge of embodiment 800B. In addition, all of the differential conductive pathways 809 are offset an additional distance 806 from the outer edge of embodiment 800B such that the outer edge 803 of differential conductive pathway 809 is overlapped by the edge 805 of the common conductive pathways. Accordingly, differential conductive pathway 809 comprises a conductive area that will always be less than any of one conductive area of any given said common conductive pathways' conductive area when calculating its' total conductive area. The common conductive pathways will generally all possess nearly the same as manufacturability controllable conductive area that is homogenous in area size to on another as well in general make-up. Thus, any one of the sandwiching common conductive pathway's will posses a total top and bottom conductive area sum always greater than the total conductive area top and bottom summed of any one differential conductive pathway and will always be almost completely physically shielded by the conductive area of any common conductive pathway of Faraday-cage-like common conductive shield structure.
The following sections that reference to common conductive pathway 804/804-IM, also apply to common conductive pathways 808 and 810. Common conductive pathway 804/804-IM is offset a distance 814 from the edge of the invention. One or more portions 811A and 811B of the common conductive pathway electrode 804/804-IM extends through material 801 and is attached to common conductive band or conductive material structures 802A and 802B. Although not shown, common 802A and 802B electrically connects common conductive pathways 804/804-IM, 808 and 810 to each other and to all other common conductive pathways (860/860-IM, 840, 830, and 860/860-IM) if used.
This enables the extension of external conductive element like 6803, shown in FIG. 5B to perform electrostatic shielding functions, among others, that the energized combination as just described will enhance and produce efficient, simultaneous conditioning upon the energy propagating on or along said portions of assembly 900A's differential conductors 809 and 809″ (not shown). The internal and external parallel arrangement groupings of a combined common conductive 900A will also cancel or suppress unwanted parasitics and electromagnetic emissions that can escape from or enter upon portions of said differential conductors differential conductors 809 and 809′ (not shown) used by said portions of energy as it propagates along a conductive pathways (not shown) to active assembly load(s), which is explained further, below with FIG. 5A.
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