Source: http://www.google.de/patents/US5475259
Timestamp: 2013-05-21 08:52:00
Document Index: 522708543

Matched Legal Cases: ['art.\n4', 'art.\n5', 'art.\n6', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'arts 21', 'arts 21', 'arts 21', 'art 8', 'art 8']

Patent US5475259 - Semiconductor device and carrier for carrying semiconductor device - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr » Erweiterte Patentsuche | Webprotokoll | Anmelden Erweiterte Patentsuche PatenteA semiconductor device comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads...http://www.google.de/patents/US5475259?utm_source=gb-gplus-sharePatent US5475259 - Semiconductor device and carrier for carrying semiconductor device Ver�ffentlichungsnummerUS5475259 APublikationstypErteilung Anmeldenummer07/961,161 Ver�ffentlichungsdatum12. Dez. 1995Eingetragen16. Okt. 1992 Priorit�tsdatum17. Okt. 1991Auch ver�ffentlicht unterEP0538010A2EP0538010A3EP0689241A2EP0689241A3US5637923US5666064US5736428US5750421 ErfinderJunichi KasaiTakashi MashikoYukio SaigoMasao SakumaMasashi TakenakaNorio TaniguchiKazuto TsujiYoshiyuki YonedaUrspr�nglich Bevollm�chtigterFujitsu Automation LimitedFujitsu LimitedKyushu Fujitsu Electronics Limited US-Klassifikation257/692257/E23.48257/E23.32257/687257/E23.55257/E23.124257/E21.504257/E23.43257/706257/730Internationale KlassifikationH01L23/433H01L23/31H01L21/68H01L21/56H01L23/58H01L23/495G01R1/04 UnternehmensklassifikationH01L23/4334H01L2924/1532H01L2924/15153H01L2224/16245H01L2924/01078H01L23/49517H01L2224/73265H01L21/565G01R1/04H01L2924/01013H01L2924/01079G01R1/0433H01L2224/48465H01L23/49572H01L2224/48091H01L2224/16H01L23/49555H01L2221/68313H01L2924/01029H01L23/3107H01L22/32H01L2924/1517H01L2224/49171H01L23/49541H01L21/6835H01L2924/3011H01L2224/48247H01L24/48H01L24/49 Europ�ische KlassifikationH01L21/683TH01L22/32H01L23/433EG01R1/04S3H01L21/56MG01R1/04H01L23/31HH01L23/495CH01L23/495GH01L23/495JH01L23/495G4B6ReferenzenPatentzitate (24)Nichtpatentzitate (2) Referenziert von (18)Externe LinksUSPTO USPTO-Zuordnung EspacenetSemiconductor device and carrier for carrying semiconductor deviceUS 5475259 A Zusammenfassung A semiconductor device comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.
What is claimed is: 1. A semiconductor device comprising: a plurality of leads respectively made up of an inner lead and an outer lead; a semiconductor chip electrically connected to the inner leads; and a package encapsulating at least the inner leads and said semiconductor chip, wherein the outer leads extend outwardly from said package, said package having an upper part and a lower part which have different sized perimeters, said upper part and lower part formed together such that a flat stepped part is formed between the upper and lower parts due to the different sized perimeters, ones of said outer leads having a given width with a wide part having a width which is wider than the given width of other parts of the outer lead extending outwardly from said package, said wide part being provided only on the stepped part of said package.
2. The semiconductor device as claimed in claim 1, further comprising projections integrally formed on the stepped part and at both sides of each outer lead.
3. A semiconductor device comprising: a plurality of leads respectively made up of an inner lead and an outer lead; a semiconductor chip electrically connected to the inner leads; and a package encapsulating at least the inner leads and said semiconductor chip, wherein the outer leads extend outwardly from said package, said package having an upper part and a lower part which have different sized perimeters, said upper part and lower part formed together such that a flat stepped part is formed between the upper and lower parts due to the different sized perimeters, ones of said outer leads having a wide part which is wider than other parts of the outer lead extending outwardly from said package, said wide part being provided only on the stepped part of said package, wherein each outer lead has an exposed surface which is exposed at the stepped part, and surfaces of each outer lead other than the exposed surface are embedded in one of the upper and lower parts having a larger perimeter at the stepped part.
4. A semiconductor device comprising: a plurality of leads respectively made up of an inner lead and an outer lead; a semiconductor chip electrically connected to the inner leads; and a package encapsulating at least the inner leads and said semiconductor chip, wherein the outer leads extend outwardly from said package, said package having an upper part and a lower part which have different sized perimeters, said upper part and lower part formed together such that a flat stepped part is formed between the upper and lower parts due to the different sized perimeters, ones of said outer leads having a wide part which is wider than other parts of the outer lead extending outwardly from said package, said wide part being provided only on the stepped part of said package, wherein each outer lead has a length of at least 400 μm along the stepped part.
5. The semiconductor device as claimed in claim 1, wherein the wide parts of the ones of said outer leads are arranged in a zigzag pattern within the stepped part.
6. The semiconductor device as claimed in claim 1, wherein: said leads are formed by a lead frame having a stage at a central part thereof; said semiconductor chip is mounted on the stage of the lead frame; and the semiconductor device further comprises a plurality of wires which bond the semiconductor chip to the inner leads.
7. The semiconductor device as claimed in claim 1, wherein said leads are formed on a tape carrier, and the semiconductor device further comprises a plurality of bumps which bond the semiconductor chip to the inner leads.
12. The semiconductor device as claimed in claim 1, further comprising: a radiator member provided on one of the upper and lower parts of said package having a smaller perimeter, to improve thermal conduction of heat generated from said semiconductor chip, said radiator member being made of a material having a thermal conductivity higher than that of said package.
13. The semiconductor device as claimed in claim 12, wherein said radiator member is embedded in the one of the upper and lower parts of said package having the smaller perimeter.
15. The semiconductor device as claimed in claim 1, further comprising: a radiator member provided on the stepped part to improve thermal conduction of heat generated from said semiconductor chip, said radiator member being made of a material having a thermal conductivity higher than that of said package.
16. The semiconductor device as claimed in claim 15, wherein said radiator member has a hole which matches the size of a smaller one of the upper and lower parts of said package having the smaller perimeter, wherein a surface of the smaller one part, exposed through the hole, is planar with a surface of said radiator member.
19. The semiconductor device as claimed in claim 15, wherein: said leads are formed by a lead frame having a stage at a central part thereof and support bars for supporting the stage; said semiconductor chip is mounted on the stage of the lead frame; said support bars extend outwardly from said package at the stepped part said radiator member is adhered to the outer leads and the support bars at the stepped part; and the semiconductor device further comprises a plurality of wires which bond the semiconductor chip to the inner leads.
20. The semiconductor device as claimed in claim 1, wherein the inner leads of said leads overlap a portion of said semiconductor chip, making electrical contact therewith.
22. An apparatus including a semiconductor device and a carrier for carrying the semiconductor device, said apparatus comprising: the semiconductor device comprising: a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a generally rectangular package encapsulating at least the inner leads and the semiconductor chip, wherein the outer leads extend outwardly from said package, said package having an upper part and a lower part which have different sized perimeters, said upper part and lower part formed together such that a flat stepped part is formed between the upper and lower parts due to the different sized perimeters, ones of said outer leads having a given width with a wide part having a width which is wider than the given width of other parts of the outer lead, said wide part being exposed only at the stepped part of said package; and the carrier comprising: a sidewall part having a hollow rectangular column shape and which opens at a top and a bottom thereof, and locking parts, provided on said sidewall part, locking respective corners of the stepped part of the semiconductor device which is accommodated within the sidewall part, said sidewall part surrounding sides of the semiconductor device, protecting the outer leads.
23. The apparatus as claimed in claim 22, wherein each of said locking parts comprise a pushing claw pushing against the respective corner of the stepped part of the semiconductor device.
In the first embodiment of the semiconductor device shown in FIGS. 2(A) and 2(B), the outer leads 8 have an approximate S-shape. However, according to a first modification shown in FIG. 5(A), each outer lead 8.sub.A is bent to an approximate L-shape. Furthermore, according to a second modification shown in FIG. 5(B), each outer lead 8.sub.B is not bent and thus has a linear shape. In the modifications shown in FIGS. 5(A) and 5(B), the outer leads 8.sub.A and 8.sub.B also have the exposed part 8a, and the effects obtained by these modifications are the same as those obtainable by the first embodiment of the semiconductor device.
A semiconductor device 1.sub.B shown in FIG. 6 has the exposed part 8a formed on the lower surface of the outer leads 8 and the upper resin 7a is larger than the lower resin 7b, similarly to the first embodiment of the semiconductor device. But in this second embodiment of the semiconductor device, projections 16 are formed on both sides of each outer lead 8 at the exposed part 8a. The projection 16 is integrally formed on the upper resin 7a.
In FIG. 6, the upper resin 7a of the package 7 is larger than the lower resin 7b. However, it is also possible to make the lower resin 7b of the package 7 larger than the upper resin 7b. In this case, the exposed part 8a is formed at the upper surfaces of the outer leads 8, and the projections 16 are integrally formed on the lower resin 7b. The probes may in this case be arranged above the semiconductor device 1.sub.B, so that each probe makes positive electrical contact with the corresponding outer lead 8 at the exposed part 8a by being restricted with respect to its position by the projections 16.
For example, the width of the outer lead 8 is 0.1 mm, the outer leads 8 are arranged at a pitch of 0.3 mm, and the difference between the sizes of the upper and lower resins 7a and 7b is 1.0 mm, as shown in FIG. 7(C). At the exposed part 8a within the 1.0 mm wide part of the upper resin 7a, the wide parts 21, respectively, having the size of 0.3.times35 mm, are arranged in a zigzag or checker-board pattern. This arrangement of the wide parts 21 can easily be realized by forming the wide parts 21 in the process of forming the lead frame 2.
In FIGS. 7(A)-7(C), the upper resin 7a of the package 7 is larger than the lower resin 7b. However, it is also possible to make the lower resin 7b of the package 7 larger than the upper resin 7b. In this case, the exposed part 8a is formed at the upper surfaces of the outer leads 8, and the projections 16 are integrally formed on the lower resin 7b. The probes may in this case be arranged above the semiconductor device 1.sub.c, so that each probe makes positive electrical contact with the corresponding outer lead 8 at the exposed part 8a.
Patentzitate Zitiertes PatentEingetragen Ver�ffentlichungsdatum Antragsteller TitelUS39633157. Apr. 197515. Juni 1976Lockhead Missiles & Space Company, Inc.Semiconductor chip carrier and testing fixtureUS421870124. Juli 197819. Aug. 1980Citizen Watch Co., Ltd.Package for an integrated circuit having a container with support barsUS47117008. Mai 19868. Dez. 1987United Technologies CorporationMethod for densifying leadframe conductor spacingUS471495230. Okt. 198522. Dez. 1987Nec CorporationCapacitor built-in integrated circuit packaged unit and process of fabrication thereofUS480650323. Okt. 198621. Febr. 1989Sharp Kabushiki KaishaMethod for the replacement of semiconductor devicesUS488163922. Febr. 198921. Nov. 1989Yamaichi Electric Mfg. Co., Ltd.IC carrierUS502630318. Mai 199025. Juni 1991Yamaichi Electric Manufacturing Co., Ltd.Slotless type IC carrierUS519896424. Sept. 199130. M�rz 1993Hitachi, Ltd.Packaged semiconductor device and electronic device module including sameUS522402119. Okt. 199029. Juni 1993Matsushita Electric Industrial Co., Ltd.Surface-mount network deviceUS525084121. Jan. 19935. Okt. 1993Motorola, Inc.Semiconductor device with test-only leadsEP0295007A22. Juni 198814. Dez. 1988Kabushiki Kaisha ToshibaFilm carrier, method for manufacturing a semiconductor device utilizing the same and an associated testerEP0338706A210. Apr. 198925. Okt. 1989Control Data CorporationA carrier assembly and a process for producing a carrier assembly for a semi-conductor packageEP0446868A112. M�rz 199118. Sept. 1991Kabushiki Kaisha ToshibaTape carrier having improved test padsGB2094552A Titel nicht verf�gbarJP1128456A Titel nicht verf�gbarJP1243560A Titel nicht verf�gbarJP2130950A Titel nicht verf�gbarJP2294059A Titel nicht verf�gbarJP3220756A Titel nicht verf�gbarJP59117247A Titel nicht verf�gbarJP63182841A Titel nicht verf�gbarJP63211744A Titel nicht verf�gbarJP63296360A Titel nicht verf�gbarWO1990015517A114. Mai 199013. Dez. 1990Labinal Components & Systems, Inc.Improved electrical connectors and ic chip tester embodying sameNichtpatentzitateReferenz1RESEARCH DISCLOSURE, "Floating Quadfiner Carrier Operation-Formed Quadpack into Carrier," No. 313, pp. 447-448, May 1990, Havant GB.2RESEARCH DISCLOSURE, Floating Quadfinger Carrier Operation Formed Quadpack into Carrier, No. 313, pp. 447 448, May 1990, Havant GB. Referenziert von Zitiert von PatentEingetragen Ver�ffentlichungsdatum Antragsteller TitelUS555482323. Dez. 199210. Sept. 1996Rohm Co., Ltd.Packaging device and its manufacturing methodUS585232424. Jan. 199722. Dez. 1998Sgs-Thomson Microelectronics S.R.L.Plastic body surface-mounting semiconductor power device having dimensional characteristics optimized for use of standard shipping and testing modesUS592750330. Juni 199727. Juli 1999Micron Technology, Inc.Tray for processing and/or shipping integrated circuit deviceUS59862099. Juli 199716. Nov. 1999Micron Technology, Inc.Package stack via bottom leaded plastic (BLP) packagingUS614691921. Juni 199914. Nov. 2000Micron Technology, Inc.Package stack via bottom leaded plastic (BLP) packagingUS616632821. Juni 199926. Dez. 2000Micron Technology, Inc.Package stack via bottom leaded plastic (BLP) packagingUS617772416. Sept. 199923. Jan. 2001Mitsubishi Denki Kabushiki KaishaSemiconductor deviceUS618802110. Juni 199913. Febr. 2001Micron Technology, Inc.Package stack via bottom leaded plastic (BLP) packagingUS621374721. Juni 199910. Apr. 2001Micron Technology, Inc.Package stack via bottom leaded plastic (BLP) packagingUS626566018. Aug. 200024. Juli 2001Micron Technology, Inc.Package stack via bottom leaded plastic (BLP) packagingUS653705128. M�rz 200125. M�rz 2003Micron Technology, Inc.Encapsulation mold with a castellated inner surfaceUS671042918. Juni 200123. M�rz 2004Renesas Technology Corp.Semiconductor device and process for production thereofUS675359931. Jan. 200222. Juni 2004Samsung Electronics Co., Ltd.Semiconductor package and mounting structure on substrate thereof and stack structure thereofUS689953418. Febr. 200331. Mai 2005Micron Technology, Inc.Mold assembly for a package stack via bottom-leaded plastic (blp) packagingUS69141989. Sept. 20025. Juli 2005Micron Technology, Inc.Electrical device allowing for increased device densitiesUS709404625. Mai 200522. Aug. 2006Micron Technology, Inc.Mold assembly for a package stack via bottom-leaded plastic (BLP) packagingUS723032029. Juli 200312. Juni 2007Hitachi, Ltd.Electronic circuit device with reduced breaking and crackingUS723032113. Okt. 200312. Juni 2007Mccain JosephIntegrated circuit package with laminated power cell having coplanar electrodeDrehenOriginalbildGoogle-Startseite - Sitemap - USPTO-Bulk-Downloads - Datenschutzerkl�rung - Nutzungsbedingungen - �ber Google Patente - Feedback gebenDaten bereitgestellt von IFI CLAIMS Patent Services.© 2012 Google