Source: http://www.patentgenius.com/patent/8536015.html
Timestamp: 2018-07-19 23:27:41
Document Index: 778925505

Matched Legal Cases: ['Application No. 200980122112', 'Application No. 09729975', 'Application No. 09729975', 'Application No. 09729975', 'Application No. 09729975', 'Application No. 200980122112', 'Application No. 200980122112']

Memory cell that includes a carbon-based memory element and methods of forming the same - Patent # 8536015 - PatentGenius
8536015 Memory cell that includes a carbon-based memory element and methods of forming the same
U.S. Class: 438/386; 257/2; 257/E45.001; 257/E45.002; 257/E45.003; 257/E45.004; 365/148; 438/102; 438/103; 438/2; 977/712; 977/720; 977/721; 977/723; 977/734; 977/788; 977/789; 977/790; 977/855; 977/943
Field Of Search: 438/2; 438/102; 438/103; 438/386; 365/148; 977/712; 977/720; 977/721; 977/723; 977/734; 977/788; 977/789; 977/790; 977/855; 977/943
International Class: H01L 21/00; G11C 11/00; H01L 29/02; H01L 21/06
Foreign Patent Documents: 101000866; 101132052; 1 763 037; 1763037; 1 892 722; 1 916 722; 20090011933; WO 98/45847; WO 2004/052781; WO 2004/070735; WO 2005/019104; WO 2007/008902; WO 2008/021900; WO 2008/082897; WO 2008/118486; WO 2009/126871; WO 2009/126876; WO 2009/134603
Other References: Office Action and Search Report in related Chinese Patent Application No. 200980122112.1 mailed Sep. 5, 2012. cited by applicant.
International Search Report and Written Opinion of International Application No. PCT/US2009/040183 mailed Jul. 16, 2009. cited by applicant.
Gerstner et al., "Nonvolatile Memory Effects in Nitrogen Doped Tetrahedral Amorphous Carbon Thin Films" Jour. Applied Physics, vol. 84, No. 10, pp. 5647-5651 (1998). cited by applicant.
Office Action of U.S. Appl. No. 12/418,855 mailed Oct. 15, 2010. cited by applicant.
EPO Rule 161(1) and 162 Communication of EP Patent Application No. 09729975.4 dated Nov. 22, 2010. cited by applicant.
Dec. 23, 2010 Response to EPO Communication of EP Patent Application No. 09729975.4 dated Nov. 22, 2010. cited by applicant.
Jan. 14, 2011 Response to Office Action of U.S. Appl. No. 12/418,855 mailed Oct. 15, 2010. cited by applicant.
Final Office Action of U.S. Appl. No. 12/418,855 mailed May 12, 2011. cited by applicant.
Abbaschian et al. "Physical Metalurgy Principles, 4th edition", 2009, Cengage Learning, Stamford CT, p. 263. cited by applicant.
Notice of Allowance of U.S. Appl. No. 12/418,855 mailed Oct. 3, 2011. cited by applicant.
Amendment After Final Submitted with RCE of U.S. Appl. No. 12/418,855, filed Aug. 12, 2011. cited by applicant.
Office Action of related European Patent Application No. 09729975.4 issued Feb. 13, 2012. cited by applicant.
Lemme, M., et al., "A Graphene Field-Effect Device", IEEE Electron Device Letters, vol. 28, No. 4, Apr. 2007. cited by applicant.
Jun. 20, 2012 Reply to Office Action of related European Patent Application No. 09729975.4. cited by applicant.
Jan. 23, 2013 Response to Sep. 5, 2012 Office Action and Search Report in related Chinese Patent Application No. 200980122112.1. cited by applicant.
Office Action in related Chinese Patent Application No. 200980122112.1 dated May 2, 2013. cited by applicant.
1. A method of forming a metal-insulator-metal ("MIM") stack, the method comprising: forming a first conducting layer; forming a resistivity-switching carbon-basedmaterial above the first conducting layer; and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers.
2. The method of claim 1, wherein the MIM stack comprises a reversible resistance switching element.
3. The method of claim 1, wherein the carbon-based material comprises amorphous carbon.
4. The method of claim 1, wherein forming the carbon-based material comprises depositing the carbon-based material using a plasma enhanced chemical vapor deposition technique.
5. The method of claim 4, wherein the plasma enhanced chemical vapor deposition technique is performed at processing temperatures less than 600.degree. C.
6. The method of claim 4, wherein the plasma enhanced chemical vapor deposition technique is performed at processing temperatures less than 450.degree. C.
7. The method of claim 1, further comprising forming a steering element coupled to the MIM stack.
8. The method of claim 7, wherein the steering element comprises a p-n or p-i-n diode.
9. The method of claim 7, wherein the steering element comprises a polycrystalline diode.
10. The method of claim 1, wherein the MIM stack comprises a memory element.
12. A method of forming a metal-insulator-metal ("MIM") stack, the method comprising: forming a first conducting layer; forming a resistivity-switching carbon-based material above the first conducting layer; and forming a second conductinglayer above the carbon-based material, wherein forming the carbon-based material comprises repeatedly performing the following steps: forming a layer of the carbon-based material, the layer having a thickness of about one monolayer; and subjecting thelayer of carbon-based material to a thermal anneal.
13. The method of claim 12, wherein the thermal anneal is performed at processing temperatures less than about 600.degree. C.
14. The method of claim 12, wherein the thermal anneal is performed using a non-oxidizing ambient.
15. The method of claim 12, wherein one monolayer comprises about one atomic layer of the carbon-based material.
16. The method of claim 12, wherein the MIM stack comprises a reversible resistance switching element.
17. The method of claim 12, wherein the carbon-based material comprises amorphous carbon.
18. The method of claim 12, wherein forming the carbon-based material comprises depositing the carbon-based material using a plasma enhanced chemical vapor deposition technique.
19. The method of claim 18, wherein the plasma enhanced chemical vapor deposition technique is performed at processing temperatures less than 600.degree. C.
20. The method of claim 18, wherein the plasma enhanced chemical vapor deposition technique is performed at processing temperatures less than 450.degree. C.
21. The method of claim 12, further comprising forming a steering element coupled to the MIM stack.
22. The method of claim 21, wherein the steering element comprises a p-n or p-i-n diode.
23. The method of claim 21, wherein the steering element comprises a polycrystalline diode.
24. The method of claim 12, wherein the MIM stack comprises a memory element.
25. A memory cell formed using the method of claim 12.
Non-volatile memories formed from reversible resistance switching elements are known. For example, U.S. patent application Ser. No. 11/968,154, filed Dec. 31, 2007, titled "Memory Cell That Employs A Selectively Fabricated Carbon Nano-TubeReversible Resistance Switching Element And Methods Of Forming The Same" (the "'154 Application"), which is hereby incorporated by reference herein in its entirety for all purposes, describes a rewriteable non-volatile memory cell that includes a diodecoupled in series with a carbon-based reversible resistivity switching material.
In accordance with a first aspect of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the firstconducting layer, and forming a second conducting layer above the carbon-based material. The carbon-based material has a thickness of not more than ten atomic layers.
In accordance with a second aspect of the invention, a method of forming a metal-insulator-metal is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conductinglayer, and forming a second conducting layer above the carbon-based material. Forming the carbon-based material includes repeatedly performing the following steps: forming a layer of the carbon-based material, the layer having a thickness of about onemonolayer, and subjecting the layer of carbon-based material to a thermal anneal.
Certain carbon-based films, including but not limited to graphene, amorphous carbon ("aC") containing microcrystalline or other regions of graphene, other graphitic carbon films, etc., may exhibit resistivity switching properties that may beused to form microelectronic non-volatile memories. Such films therefore are candidates for integration within a three-dimensional memory array.
Indeed, carbon-based materials have demonstrated memory switching properties on lab-scale devices with a 100.times.separation between ON and OFF states and mid-to-high range resistance changes. Such a separation between ON and OFF statesrenders carbon-based materials viable candidates for memory cells in which the carbon-based material is coupled in series with vertical diodes, thin film transistors or other steering elements. For example, a metal-insulator-metal ("MIM") stack formedfrom a carbon-based material sandwiched between two metal or otherwise conducting layers may serve as a resistance-switching element for a memory cell.
Carbon-based materials are often deposited using plasma-enhanced chemical vapor deposition ("PECVD") techniques. Such carbon-based material may have an "initial resistivity" (i.e., the resistivity of the material as formed) that may be lowrelative to the resistivities of the surrounding materials. As a result, a resistance-switching element that includes the carbon-based material may conduct a high initial current that is incompatible with a steering element used to control current flowthrough the resistance-switching element, such as an adjacent diode. Additionally or alternatively, the initial resistivity of the carbon-based material may require a high voltage and current to reset the material upon initial use.
In accordance with an exemplary embodiment of this invention, a memory cell is formed that includes a MIM stack that includes a carbon-based material, and that is coupled to a steering element such as a diode. The memory cell is formed bydepositing a thin layer of carbon-based material having a thickness of about ten atomic layers or fewer.
In accordance with another exemplary embodiment of this invention, a memory cell is formed that includes a MIM stack that includes a carbon-based material, and that is coupled to a steering element such as a diode. The memory cell is formed byperforming multiple depositions to form multiple monolayers or near-monolayers of a carbon-based material. As used herein, a monolayer of a carbon-based material is about one atomic layer of the carbon-based material. After each monolayer ofcarbon-based material is formed, the material is annealed at processing temperatures less than about 600.degree. C. before forming the next and successive layer. Subjecting each respective layer to an anneal may facilitate formation of in-plane carbonbonds and limit the number of out-of-plane carbon bonds, thereby increasing the resistivity of the carbon-based material to current flowing in a direction perpendicular to the material's surface. Increasing the resistivity of the carbon-based materialin this way may increase the resistance of the reversible-resistance switching element formed from the carbon-based material, thereby decreasing initial current flow through the reversible-resistance switching element.
FIG. 1 is a schematic illustration of an exemplary memory cell 10 in accordance with this invention. Memory cell 10 includes a reversible resistance switching element 12 coupled to a steering element 14. Reversible resistance switching element12 includes a reversible resistivity switching material (not separately shown) having a resistivity that may be reversibly switched between two or more states.
FIG. 2A is a simplified perspective view of an exemplary embodiment of a memory cell 10 in accordance with this invention that includes a steering element 14 and a carbon-based reversible resistance switching element 12. Reversible resistanceswitching element 12 is coupled in series with steering element 14 between a first conductor 20 and a second conductor 22. In some embodiments, a barrier layer 24 may be formed between reversible resistance switching element 12 and steering element 14,and a barrier layer 33 may be formed between reversible resistance switching element 12 and second conductor 22. An additional barrier layer 28 also may be formed between steering element 14 and first conductor 20. For example, barrier layers 24, 28and 33 may include titanium nitride, tantalum nitride, tungsten nitride, or other similar barrier layer.
As discussed above, steering element 14 may include a thin film transistor, a diode, metal-insulator-metal tunneling current device, or another similar steering element that exhibits non-ohmic conduction by selectively limiting the voltageacross and/or the current flow through reversible resistance switching element 12. In the example of FIG. 2A, steering element 14 is a diode. Accordingly, steering element 14 is sometimes referred to herein as "diode 14."
Diode 14 may include any suitable diode such as a vertical polycrystalline p-n or p-i-n diode, whether upward pointing with an n-region above a p-region of the diode or downward pointing with a p-region above an n-region of the diode. Forexample, diode 14 may include a heavily doped n+ polysilicon region 14a, a lightly doped or an intrinsic (unintentionally doped) polysilicon region 14b above the n+ polysilicon region 14a, and a heavily doped p+ polysilicon region 14c above intrinsicregion 14b. It will be understood that the locations of the n+ and p+ regions may be reversed. Exemplary embodiments of diode 14 are described below with reference to FIG. 3.
Reversible resistance switching element 12 may include a carbon-based material (not separately shown) having a resistivity that may be reversibly switched between two or more states. For example, reversible resistance switching element 12 mayinclude aC containing microcrystalline or other regions of graphene. For simplicity, reversible resistance switching element 12 will be referred to in the remaining discussion as "carbon element 12."
FIG. 2B is a simplified perspective view of a portion of a first memory level 30 formed from a plurality of memory cells 10, such as memory cell 10 of FIG. 2A. For simplicity, carbon element 12, diode 14, and barrier layers 24, 28 and 33 arenot separately shown. Memory array 30 is a "cross-point" array including a plurality of bit lines (second conductors 22) and word lines (first conductors 20) to which multiple memory cells are coupled (as shown). Other memory array configurations maybe used, as may multiple levels of memory.
For example, FIG. 2C is a simplified perspective view of a portion of a monolithic three dimensional array 40a that includes a first memory level 42 positioned below a second memory level 44. Memory levels 42 and 44 each include a plurality ofmemory cells 10 in a cross-point array. Persons of ordinary skill in the art will understand that additional layers (e.g., an interlevel dielectric) may be present between the first and second memory levels 42 and 44, but are not shown in FIG. 2C forsimplicity. Other memory array configurations may be used, as may additional levels of memory. In the embodiment of FIG. 2C, all diodes may "point" in the same direction, such as upward or downward depending on whether p-i-n diodes having a p-dopedregion on the bottom or top of the diodes are employed, simplifying diode fabrication.
For example, in some embodiments, the memory levels may be formed as described in U.S. Pat. No. 6,952,030, titled "High-Density Three-Dimensional Memory Cell" which is hereby incorporated by reference herein in its entirety for all purposes. For instance, the upper conductors of a first memory level may be used as the lower conductors of a second memory level that is positioned above the first memory level as shown in the alternative exemplary three dimensional array 40b illustrated in FIG.2D. In such embodiments, the diodes on adjacent memory levels preferably point in opposite directions as described in U.S. patent application Ser. No. 11/692,151, filed Mar. 27, 2007 and titled "Large Array Of Upward Pointing P-I-N Diodes HavingLarge And Uniform Current" (hereinafter "the '151 Application"), which is hereby incorporated by reference herein in its entirety for all purposes. For example, as shown in FIG. 2D, the diodes of the first memory level 42 may be upward pointing diodesas indicated by arrow A1 (e.g., with p regions at the bottom of the diodes), whereas the diodes of the second memory level 44 may be downward pointing diodes as indicated by arrow A2 (e.g., with n regions at the bottom of the diodes), or vice versa.
As previously stated, any suitable carbon-based switching material may be used as carbon element 12. In some embodiments, a preferred resistivity of the material used to form carbon element 12 is at least 1.times.10.sup.1 ohm-cm when carbonelement 12 is in an ON-state, whereas a preferred resistivity of the material used to form carbon element 12 is at least 1.times.10.sup.3 ohm-cm when carbon element 12 is in an OFF-state.
FIG. 3 is a cross-sectional view of an exemplary embodiment of memory cell 10 of FIG. 1. In particular, FIG. 3 shows an exemplary memory cell 10 which includes carbon element 12, diode 14, and first and second conductors 20 and 22,respectively. Memory cell 10 may also include barrier layers 26, 28, and 33, a silicide layer 50, a silicide-forming metal layer 52, and dielectric layer 58, as well as adhesion layers, antireflective coating layers and/or the like (not shown) which maybe used with first and/or second conductors 20 and 22, respectively, to improve device performance and/or facilitate device fabrication.
In FIG. 3, diode 14 may be a vertical p-n or p-i-n diode, which may either point upward or downward. In the embodiment of FIG. 2D in which adjacent memory levels share conductors, adjacent memory levels preferably have diodes that point inopposite directions such as downward-pointing p-i-n diodes for a first memory level and upward-pointing p-i-n diodes for an adjacent, second memory level (or vice versa).
In some embodiments, a thin germanium and/or silicon-germanium alloy layer (not shown) may be formed on n+ polysilicon region 14a to prevent and/or reduce dopant migration from n+ polysilicon region 14a into intrinsic region 14b. Use of such alayer is described, for example, in U.S. patent application Ser. No. 11/298,331, filed Dec. 9, 2005 and titled "Deposited Semiconductor Structure To Minimize N-Type Dopant Diffusion And Method Of Making" (hereinafter "the '331 Application"), which ishereby incorporated by reference herein in its entirety for all purposes. In some embodiments, a few hundred angstroms or less of silicon-germanium alloy with about 10 at % or more of germanium may be employed.
A barrier layer 28, such as titanium nitride, tantalum nitride, tungsten nitride, etc., may be formed between the first conductor 20 and the n+ region 14a (e.g., to prevent and/or reduce migration of metal atoms into the polysilicon regions).
If diode 14 is fabricated from deposited silicon (e.g., amorphous or polycrystalline), a silicide layer 50 may be formed on diode 14 to place the deposited silicon in a low resistivity state, as fabricated. Such a low resistivity state allowsfor easier programming of memory cell 10 as a large voltage is not required to switch the deposited silicon to a low resistivity state. For example, a silicide-forming metal layer 52 such as titanium or cobalt may be deposited on p+ polysilicon region14c. During a subsequent anneal step (described below) employed to crystallize the deposited silicon that forms diode 14, silicide-forming metal layer 52 and the deposited silicon of diode 14 interact to form silicide layer 50, consuming all or aportion of the silicide-forming metal layer 52. In some embodiments, a nitride layer (not shown) may be formed at a top surface of silicide-forming metal layer 52. For example, if silicide-forming metal layer 52 is titanium, a TiN layer may be formedat a top surface of silicide-forming metal layer 52.
A rapid thermal anneal ("RTA") step may then be performed to form silicide regions by reaction of silicide-forming metal layer 52 with p+ region 14c. The RTA may be performed at about 540.degree. C. for about 1 minute, and causessilicide-forming metal layer 52 and the deposited silicon of diode 14 to interact to form silicide layer 50, consuming all or a portion of the silicide-forming metal layer 52. As described in U.S. Pat. No. 7,176,064, titled "Memory Cell Comprising ASemiconductor Junction Diode Crystallized Adjacent To A Silicide," which is hereby incorporated by reference herein in its entirety for all purposes, silicide-forming materials such as titanium and/or cobalt react with deposited silicon during annealingto form a silicide layer.
In embodiments in which a nitride layer was formed at a top surface of silicide-forming metal layer 52, following the RTA step, the nitride layer may be stripped using a wet chemistry. For example, if silicide-forming metal layer 52 includes aTiN top layer, a wet chemistry (e.g., ammonium, peroxide, water in a 1:1:1 ratio) may be used to strip any residual TiN.
In at least some embodiments, described in more detail with respect to FIGS. 4A-4E, reversible resistance switching element 12 may be formed by depositing a thin layer of a carbon-based material, such as aC, having a thickness of about tenatomic layers or fewer.
In other embodiments, carbon element 12 may be formed by performing multiple depositions of a carbon-based material, such as aC, to form multiple monolayers or near-monolayers of the carbon-based material and annealing each layer beforedepositing a successive layer. Forming carbon-based material in this manner may increase the resistivity of the material to current flowing in a direction perpendicular to the material's surface.
Preferably between two and about ten monolayers or near-monolayers are deposited to form carbon element 12. The total thickness of carbon element 12 is between about 1 angstrom and about 800 angstroms, preferably between about 5 angstrom and100 angstroms.
In particular embodiments, carbon-based switching materials may be formed to exhibit sheet resistance (".OMEGA./.quadrature." or "ohms/square") for a 1000 angstrom film from about 1.times.10.sup.5 .OMEGA./.quadrature. to about 1.times.10.sup.8.OMEGA./.quadrature., and more preferably about 1.times.10.sup.4 .OMEGA./.quadrature. or greater. Similarly, some embodiments may comprise an aC film with nanocrystallites. Other film parameters and characteristics may be pursued as well (e.g.,alternate values of deposition rate, film thickness, sheet resistance/resistivity, etc.).
A barrier layer 33, such as titanium nitride, tantalum nitride, tungsten nitride, etc., may be formed between carbon element 12 and second conductor 22. Second conductor 22 may be formed above barrier layer 33, as shown in FIG. 3. Secondconductor 22 may include one or more barrier and/or adhesion layers 26 and a conductive layer 140.
Referring now to FIGS. 4A-4E, a first exemplary method of forming an exemplary memory level in accordance with this invention is described. In particular, FIGS. 4A-4E illustrate an exemplary method of forming an exemplary memory level includingmemory cells 10 of FIG. 3. As will be described below, the first memory level includes a plurality of memory cells that each include a steering element and a carbon-based reversible resistance switching element coupled to the steering element. Additional memory levels may be fabricated above the first memory level (as described previously with reference to FIGS. 2C-2D).
After first conductors 20 have been formed, a dielectric layer 58a is formed over substrate 100 to fill the voids between first conductors 20. For example, approximately 3000-7000 angstroms of silicon dioxide may be deposited on the substrate100 and planarized using chemical mechanical polishing or an etchback process to form a planar surface 110. Planar surface 110 includes exposed top surfaces of first conductors 20 separated by dielectric material (as shown). Other dielectric materialssuch as silicon nitride, silicon oxynitride, low K dielectrics, etc., and/or other dielectric layer thicknesses may be used. Exemplary low K dielectrics include carbon doped oxides, silicon carbon layers, or the like.
Following planarization, the diode structures of each memory cell are formed. With reference to FIG. 4B, a barrier layer 28 is formed over planarized top surface 110 of substrate 100. Barrier layer 28 may be about 20 to about 500 angstroms,and preferably about 100 angstroms, of titanium nitride or another suitable barrier layer such as tantalum nitride, tungsten nitride, combinations of one or more barrier layers, barrier layers in combination with other layers such as titanium/titaniumnitride, tantalum/tantalum nitride or tungsten/tungsten nitride stacks, or the like. Other barrier layer materials and/or thicknesses may be employed.
After deposition of barrier layer 28, deposition of the semiconductor material used to form the diode of each memory cell begins (e.g., diode 14 in FIGS. 1 and 3). Each diode may be a vertical p-n or p-i-n diode as previously described. Insome embodiments, each diode is formed from a polycrystalline semiconductor material such as polysilicon, a polycrystalline silicon-germanium alloy, polygermanium or any other suitable material. For convenience, formation of a polysilicon,downward-pointing diode is described herein. It will be understood that other materials and/or diode configurations may be used.
A thin (e.g., a few hundred angstroms or less) germanium and/or silicon-germanium alloy layer (not shown) may be formed on n+ silicon layer 14a prior to depositing intrinsic silicon layer 14b to prevent and/or reduce dopant migration fromn+silicon layer 14a into intrinsic silicon layer 14b (as described in the '331 Application, previously incorporated).
Heavily doped, p-type silicon may be either deposited and doped by ion implantation or may be doped in situ during deposition to form a p+ silicon layer 14c. For example, a blanket p+ implant may be employed to implant boron a predetermineddepth within intrinsic silicon layer 14b. Exemplary implantable molecular ions include BF.sub.2, BF.sub.3, B and the like. In some embodiments, an implant dose of about 1.times.5.times.10.sup.15 ions/cm.sup.2 may be employed. Other implant speciesand/or doses may be used. Further, in some embodiments, a diffusion process may be employed. In at least one embodiment, the resultant p+ silicon layer 14c has a thickness of about 100-700 angstroms, although other p+ silicon layer sizes may be used.
Following the RTA step and the nitride strip step, carbon element 12 is formed above silicide-forming metal layer 52. In at least some embodiments described herein, carbon element 12 is formed by depositing a carbon-based reversible resistivityswitching material such as aC. In alternative embodiments, other carbon-based materials may be used, including, without limitation, graphene, graphite, etc. For each material, a ratio of sp.sup.2 (double carbon-carbon bonds to sp.sup.3 (singlecarbon-carbon bonds) may be determined via, e.g., Raman spectroscopy, by evaluating the D and G bands. The range of usable materials may be identified by a ratio such as M.sub.yN.sub.z, where M is the sp.sup.3 material and N is the sp.sup.2 material,and y and z are any fractional value from zero to one and y+z=1.
As discussed above, carbon element 12 may be formed by depositing a thin layer of aC having a thickness of only a few atomic layers (e.g., approximately ten atomic layers or fewer). Researchers have asserted that depositing a carbon-basedmaterial in this manner may facilitate the formation of carbon-carbon ring structures in the carbon-based material. For example, the formation of sp.sup.2 carbon-carbon pi bonds typical in graphitic materials may be facilitated.
For example, carbon element 12 may be formed using a plasma enhanced decomposition and deposition procedure, such as PECVD, performed at processing temperatures between about 300.degree. C. and 900.degree. C., preferably below 600.degree. C.,more preferably below 450.degree. C., using a mixture of hydrogen and hexane. In other embodiments, other deposition methods may be used, including, without limitation, sputter deposition from a target, CVD, arc discharge techniques and laser ablation.
In other embodiments, carbon element 12 may be formed by performing multiple depositions of an aC material to form multiple monolayers or near-monolayers of the aC material and annealing each respective monolayer or near-monolayer beforedepositing a successive layer. Forming a carbon-based material in this manner may increase the resistivity of the material to current flowing in a direction perpendicular to the material's surface.
Each monolayer or near-monolayer may be annealed at processing temperatures less than about 600.degree. C. in a non-oxidizing ambient before deposition of the successive layer. Subjecting each respective layer to an anneal may facilitateformation of in-plane carbon bonds and limit the number of out-of-plane carbon bonds, thereby increasing the resistivity of the aC material in the direction perpendicular to the material's surface. Increasing the resistivity of the aC material in thismanner may increase the resistance of reversible resistance switching element 12 formed from the aC material, thereby decreasing initial current flow through the reversible-resistance switching element 12.
Preferably between two and about ten layers of aC material are deposited to form reversible resistance switching element 12. The total thickness of reversible resistance switching element 12 is between about 1 angstrom and about 800 angstroms,preferably between about 5 angstrom and 100 angstroms.
A barrier layer 33 is formed over reversible resistance switching element 12. Barrier layer 33 may be about 5 to about 800 angstroms, and preferably about 100 angstroms, of titanium nitride or another suitable barrier layer such as tantalumnitride, tungsten nitride, combinations of one or more barrier layers, barrier layers in combination with other layers such as titanium/titanium nitride, tantalum/tantalum nitride or tungsten/tungsten nitride stacks, or the like. Other barrier layermaterials and/or thicknesses may be employed.
As shown in FIG. 4C, barrier layer 33, reversible resistance switching element 12, silicide-forming metal layer 52, diode layers 14a-14c and barrier layer 28 are patterned and etched to form pillars 132. Pillars 132 may have about the samepitch and about the same width as conductors 20 below, such that each pillar 132 is formed on top of a conductor 20. Some misalignment may be tolerated.
For example, photoresist may be deposited, patterned using standard photolithography techniques, layers 28, 14a-14c, 52, 12, and 33 may be etched, and then the photoresist may be removed. Alternatively, a hard mask of some other material, forexample silicon dioxide, may be formed on top of the barrier layer 33, with bottom antireflective coating ("BARC") on top, then patterned and etched. Similarly, dielectric antireflective coating ("DARC") may be used as a hard mask.
Pillars 132 may be formed using any suitable masking and etching process. For example, layers 28, 14a-14c, 52, 12, and 33 may be patterned with about 1 to about 1.5 micron, more preferably about 1.2 to about 1.4 micron, of photoresist ("PR")using standard photolithographic techniques. Thinner PR layers may be used with smaller critical dimensions and technology nodes. In some embodiments, an oxide hard mask may be used below the PR layer to improve pattern transfer and protect underlyinglayers during etching.
Any suitable etch chemistries, and any suitable etch parameters, flow rates, chamber pressures, power levels, process temperatures, and/or etch rates may be used. In some embodiments, barrier layer 33, reversible resistance switching element12, silicide-forming metal layer 52, diode layers 14a-14c and barrier layer 28 may be patterned using a single etch step. In other embodiments, separate etch steps may be used. The etch proceeds down to dielectric layer 58a. Such etched pillars 132have been observed to have nearly vertical sidewalls and little or no undercut of reversible resistance switching element 12.
After etching pillars 132 may be cleaned using a dilute hydrofluoric/sulfuric acid clean. Such cleaning, whether or not PR asking is performed before etching, may be performed in any suitable cleaning tool, such as a Raider tool, available fromSemitool of Kalispell, Mont. Exemplary post-etch cleaning may include using ultra-dilute sulfuric acid (e.g., about 1.5-1.8 wt %) for about 60 seconds and ultra-dilute hydrofluoric ("HF") acid (e.g., about 0.4-0.6 wt %) for 60 seconds. Megasonics mayor may not be used.
After pillars 132 have been cleaned, a dielectric layer 58b may be deposited over pillars 132 to fill the voids between pillars 132. For example, approximately 200-7000 angstroms of silicon dioxide may be deposited and planarized using chemicalmechanical polishing or an etchback process to remove excess dielectric material 58b and form a planar surface 134, resulting in the structure illustrated in FIG. 4D. Planar surface 134 includes exposed top surfaces of pillars 132 separated bydielectric material 58b (as shown). Other dielectric materials such as silicon nitride, silicon oxynitride, low K dielectrics, etc., and/or other dielectric layer thicknesses may be used. Exemplary low K dielectrics include carbon doped oxides, siliconcarbon layers, or the like.
With reference to FIG. 4E, second conductors 22 may be formed above pillars 132 in a manner similar to the formation of first conductors 20. For example, in some embodiments, one or more barrier layers and/or adhesion layers 26 may be depositedover pillars 132 prior to deposition of a conductive layer 140 used to form second conductors 22.
Conductive layer 140 may be formed from any suitable conductive material such as tungsten, another suitable metal, heavily doped semiconductor material, a conductive silicide, a conductive silicide-germanide, a conductive germanide, or the likedeposited by any suitable method (e.g., CVD, PVD, etc.). Other conductive layer materials may be used. Barrier layers and/or adhesion layers 26 may include titanium nitride or another suitable layer such as tantalum nitride, tungsten nitride,combinations of one or more layers, or any other suitable material(s). The deposited conductive layer 140 and barrier and/or adhesion layer 26 may be patterned and etched to form second conductors 22. In at least one embodiment, second conductors 22are substantially parallel, substantially coplanar conductors that extend in a different direction than first conductors 20.
Following formation of second conductors 22, the resultant structure may be annealed to crystallize the deposited semiconductor material of diodes 14 (and/or to form silicide regions by reaction of the silicide-forming metal layer 52 with p+region 14c). The lattice spacing of titanium silicide and cobalt silicide are close to that of silicon, and it appears that silicide layers 50 may serve as "crystallization templates" or "seeds" for adjacent deposited silicon as the deposited siliconcrystallizes (e.g., silicide layer 50 enhances the crystalline structure of silicon diode 14 during annealing at temps of about 600-800.degree. C.). Lower resistivity diode material thereby is provided. Similar results may be achieved forsilicon-germanium alloy and/or germanium diodes.
Persons of ordinary skill in the art will understand that alternative memory cells in accordance with this invention may be fabricated in other similar techniques. For example, memory cells may be formed that include reversible resistanceswitching element 12 below diode 14.
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