Source: http://www.google.com/patents/US7061218?dq=inventor:%22Arthur+R.+Hair%22
Timestamp: 2017-03-25 11:52:46
Document Index: 579091904

Matched Legal Cases: ['art.\n10', 'Application No. 2004', 'art 40', 'art 40', 'art 40', 'art 40', 'art 40', 'art 42', 'art 42', 'art 42', 'arts 40']

Patent US7061218 - Control circuit of DC—DC converter and control method thereof - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThere are provided a control circuit of a DC—DC converter of a synchronous rectification system which can realize rapid lowering of an output voltage with low power consumption at the stop of power supply, and a control method thereof. While a power supply stop signal is at low level, a control part...http://www.google.com/patents/US7061218?utm_source=gb-gplus-sharePatent US7061218 - Control circuit of DC—DC converter and control method thereofAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7061218 B2Publication typeGrantApplication numberUS 11/025,134Publication dateJun 13, 2006Filing dateDec 30, 2004Priority dateSep 30, 2004Fee statusPaidAlso published asUS7218088, US20060071651, US20060181260Publication number025134, 11025134, US 7061218 B2, US 7061218B2, US-B2-7061218, US7061218 B2, US7061218B2InventorsHidenobu ItoOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (22), Classifications (7), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetControl circuit of DC—DC converter and control method thereof
US 7061218 B2Abstract
There are provided a control circuit of a DC—DC converter of a synchronous rectification system which can realize rapid lowering of an output voltage with low power consumption at the stop of power supply, and a control method thereof. While a power supply stop signal is at low level, a control part controls an NMOS transistor according to the output signals of a comparator and a flip-flop circuit. While the power supply stop signal is at high level, the control part masks a reverse current detection signal and the output signal of the flip-flop circuit to control the NMOS transistor according to a detection signal of a comparator. When a choke coil current is reversely flowed and an output voltage is lowered to an output reference voltage corresponding to a reference voltage, the NMOS transistor is brought to the non-conductive state to regenerate the electric power to an input terminal.
1. A DC—DC converter control circuit which controls a first switching device brought into conduction when electric power is stored in an inductive device and a second switching device switching controlled and brought into conduction according to the period of the discharge of the electric power stored in the inductive device to a load, comprising:
a reverse current detection part detecting an electric current in the reverse direction of the discharge of the electric power to the load to output a reverse current detection signal; and
a control part which is a circuit bringing the second switching device to the non-conductive state according to the reverse current detection signal and neglects the reverse current detection signal according to a predetermined signal instructing lowering of a load application voltage applied to the load to bring the second switching device to the non-conductive state according to the load application voltage.
2. The DC—DC converter control circuit according to claim 1,
3. The DC—DC converter control circuit according to claim 2, wherein the regulating operation is stopped according to the power supply stop signal.
4. The DC—DC converter control circuit according to claim 2, wherein the control part masks the reverse current detection signal according to the power supply stop signal.
5. The DC—DC converter control circuit according to claim 2, wherein the reference load application voltage is an output voltage when substantially half of electric power stored on the load side is moved to the inductive device.
6. The DC—DC converter control circuit according to claim 2, wherein the reference load application voltage has a voltage value ( 1/2) times the load application voltage in the stationary state.
7. The DC—DC converter control circuit according to claim 1,
wherein the DC—DC converter control circuit has:
a reference voltage part in which a voltage is lowered with time according to the power supply stop signal; and
8. The DC—DC converter control circuit according to claim 7,
9. The DC—DC converter control circuit according to claim 8, wherein the capacitor is a capacitor for soft-start.
10. The DC—DC converter control circuit according to claim 1,
a reference voltage changing part in which a voltage is changed according to the changing signal; and
11. The DC—DC converter control circuit according to claim 10, wherein the control part masks the reverse current detection signal according to the changing signal.
12. The DC—DC converter control circuit according to claim 10,
13. A DC—DC converter control method which controls a first current path brought into conduction when electric power is stored in an inductive device and a second current path brought into conduction according to the period of the discharge of the electric power stored in the inductive device to a load, comprising:
detecting an electric current in the reverse direction of the discharge of the electric power to the load to output a reverse current detection signal;
bringing the second switching device to the non-conductive state according to the reverse current detection signal; and
14. The DC—DC converter control method according to claim 13,
15. The DC—DC converter control method according to claim 13,
16. The DC—DC converter control method according to claim 13,
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-288533 filed on Sep. 30, 2004, the entire contents of which are incorporated herein by reference.
The present invention relates to the control of a DC—DC converter. More specifically, the present invention relates to the control of an output voltage with the stop of operation and the change in a set output voltage in a DC—DC converter of a synchronous rectification system.
Portable type electronic equipment uses a battery as a power source. The electric power of the battery is discharged with time according to power consumption with the operation of the equipment. The output voltage of the battery is lowered. To maintain the voltage value of the power source of the equipment constant to the change in the battery voltage with time, the DC—DC converter makes the voltage of supplied power constant.
Electronic equipment may use a plurality of voltage sources having different voltage values. A DC—DC converter may be provided for each of the voltage sources. In this case, with the start and stop of the electronic equipment, it is important that start and stop be performed in suitable order in consideration of the start and stop sequence of the voltage sources. Unless the order of the start and stop sequence is suitable, a semiconductor device constructing the electronic equipment can cause a latchup phenomenon in which the state of applying a forward bias to a PN junction part is maintained to continuously flow an undesired electric current. Upon occurrence of the latchup phenomenon, in the case of limiting no electric currents, the semiconductor device can be burnt.
To avoid these disadvantages, when the DC—DC converter is stopped, regardless of a heavy or light load, electric power stored in the capacitance on the load side such as an output capacitor must be efficiently drawn out to rapidly lower an output voltage. The rapid lowering of the output voltage can prevent the power source from remaining at stop and from performing unexpected operation. The start operation can be performed in the state that there is no remaining voltage in the voltage source to suitably perform the start sequence of the voltage source.
In a DC—DC converter of a synchronous rectification system shown in FIG. 6, in the operation state, energy stored in a choke coil L121 by the conduction of a main transistor Tr121 is discharged to an output voltage side VO by the conduction of a transistor for synchronous rectification Tr122 in the non-conductive period of the main transistor Tr121. The conductive control of the transistor for synchronous rectification Tr122 is performed by a synchronous rectification control circuit 250.
When the DC—DC converter shown in the prior art forcefully discharges the capacitance on the load side at stop, the conduction of the transistor for synchronous rectification Tr122 connects one end of the choke coil L121 to the ground potential. The other end of the choke coil L121 is connected to the output side VO. At this point, the output voltage is considered to remain. In particular, in the light load state, a voltage value close to a predetermined output voltage regulated in the operation state remains. The capacitance on the load side including an output capacitor C121 is in the state that energy according to the output voltage is stored. The conduction of the transistor for synchronous rectification Tr122 increases the discharge current at a gradient according to (the voltage across terminals of the choke coil)/(inductance of the choke coil). According to the increased electric current, the energy stored in the output capacitor is sequentially moved to the choke coil L121.
In Japanese unexamined patent publication No. H9(1997)-154275, the energy stored in the output capacitor C121 is consumed via the ground potential with increase in the discharge current to be stored in the choke coil L121. Finally, the energy stored in the choke coil L121 is flowed as the discharge current to be consumed. The energy remaining on the output side VO is consumed with the stop of the DC—DC converter. The electric power is wastefully consumed.
Electronic equipment may change a source voltage value according to the state of the load. When changing to a lower voltage value in the light load state, it is desirable that an output voltage supplied from the DC—DC converter be rapidly lowered. Also in this case, excessive energy stored in the output capacitor must be rapidly drawn out. In the method of Japanese unexamined patent publication No. H9(1997)-154275, it is difficult to regulate the drawn-out output voltage.
The present invention has been made to solve at least one of the prior art problems. An object of the present invention is to provide a control circuit of a DC—DC converter of a synchronous rectification system which can realize rapid lowering of an output voltage with low power consumption by rapidly lowering the output voltage while regenerating energy stored in the capacitance component on the load side to the input side, regardless of a heavy or light load, at the stop of power supply and a control method thereof.
To achieve the object, a DC—DC converter control circuit according to a first invention which controls a first switching device brought into conduction when electric power is stored in an inductive device and a second switching device switching controlled and brought into conduction according to the period of the discharge of the electric power stored in the inductive device to a load, has a reverse current detection part detecting an electric current in the reverse direction of the discharge of the electric power to the load to output a reverse current detection signal; and a control part which is a circuit bringing the second switching device to the non-conductive state according to the reverse current detection signal and neglects the reverse current detection signal according to a predetermined signal instructing lowering of a load application voltage applied to the load to bring the second switching device to the non-conductive state according to the load application voltage.
A DC—DC converter control method according to the first invention which controls a first current path brought into conduction when electric power is stored in an inductive device and a second current path brought into conduction according to the period of the discharge of the electric power stored in the inductive device to a load, includes detecting an electric current in the reverse direction of the discharge of the electric power to the load to output a reverse current detection signal; bringing the second switching device to the non-conductive state according to the reverse current detection signal; and neglecting the reverse current detection signal according to a predetermined signal instructing lowering of a load application voltage applied to the load to bring the second switching device to the non-conductive state according to the load application voltage.
In the DC—DC converter control circuit or control method according to the first invention, the second switching device or the second current path is switching controlled and brought into conduction according to the period of the discharge of the electric power stored in the inductive device to the load. The voltage across terminals of the inductive device is inverted to flow an electric current at a negative gradient with time; the synchronous rectification operation is performed. The reverse current detection part detects an electric current flowing in the reverse direction of the discharge of the electric power to the load. The control part is a circuit bringing the second switching device to the non-conductive state according to the reverse current detection signal in the normal regulating operation. The control part neglects the reverse current detection signal according to a predetermined signal lowering a load application voltage applied to the load to bring the second switching device to the non-conductive state according to the load application voltage.
In the prior art DC—DC converter control circuit, as the reverse current detection part detects an electric current in the reverse direction of the discharge of the electric power to the load to output the reverse current detection signal, the second switching device is brought to the non-conductive state. The control part of the DC—DC converter control circuit according to the present invention neglects the reverse current detection signal according to a predetermined signal instructing lowering of the load application voltage applied to the load. When the reverse flow of an electric current from the load to the inductive device is started, the second switching device is not non-conductive to allow the reverse flow of the electric current. According to this, the electric power on the load side is moved to the inductive device to be stored. When the electric power discharged to the load side is excessive in the state that power consumption in the load is less, the conductive state of the second switching device or the second current path is maintained beyond the electric power discharge period of the inductive device to make it possible to return the excessive electric power to the inductive device.
When the second switching device or the second current path is non-conductive according to the load application voltage applied to the load, the electric power returned to the inductive device is regenerated to the input side to make it possible to return the excessive electric power to the input side. This can regenerate the excessive electric power stored on the load side to avoid waste power consumption. The electric power conversion efficiency of the DC—DC converter can be improved. This can be done by providing a device having a rectifying function from the inductive device to the input side. When using a MOS transistor as the first switching device or the first current path, the body diode of the MOS transistor is used to make it possible to perform regeneration.
FIG. 1 is a circuit diagram of a current control type DC—DC converter 1 according to a first embodiment;
FIG. 2 is a timing chart when stopping power supply of the DC—DC converter 1;
FIG. 3 is a circuit diagram of a voltage control type DC—DC converter 1 a according to a second embodiment;
FIG. 4 is a circuit diagram of a current control type DC—DC converter 1 b according to a third embodiment;
FIG. 5 is a circuit diagram of a current control type DC—DC converter 1 c according to a fourth embodiment; and
FIG. 6 is a circuit diagram of a prior art DC—DC converter of a synchronous rectification system.
Embodiments embodying a control circuit of a DC—DC converter and a control method thereof according to the present invention will be described below in detail with reference to the drawings based on FIGS. 1 to 5.
A first embodiment of the present invention will be described using FIGS. 1 and 2. FIG. 1 is a circuit diagram of a current control type DC—DC converter 1 of a synchronous rectification type switching system according to the first embodiment. Means for on/off controlling an NMOS transistor FET2 as a synchronous rectification switch circuit at the stop of the power supply operation of the DC—DC converter 1 is provided to reversely flow electric power stored in the capacitance on the load side via the NMOS transistor FET2 to a choke coil L1 for regenerating it to the input side so that an output voltage VOUT of the DC—DC converter 1 is rapidly lowered.
One end of a capacitor C2 is connected to the ground potential and the other is connected to the terminal (SS). The capacitor C2 is a capacitor for soft-start. The terminal (SS) is connected to the inverting input terminal of the error amplifier ERA1 and the switch circuit SW. The switch circuit SW is constructed so that one of a constant-current circuit IS or the ground potential can be selected. The selection of the constant-current circuit IS charges the capacitor C2. The selection of the ground potential discharges the capacitor C2. When the DC—DC converter 1 is stopped, the terminal (SS) is connected to the ground potential so that the electric charge of the capacitor C2 is discharged to set its potential to 0V. When the terminal (SS) is connected to the constant-current circuit IS, the capacitor C2 is charged to increase the potential of the capacitor C2 in a fixed time.
A power supply stop signal STP is inputted to the AND gate circuits AND1 and AND2. The power supply stop signal STP is a signal which is at high level while the DC—DC converter 1 stops the power supply operation and which is at low level during the start of the power supply operation or the operation. The output terminal of the comparator COMP3 is connected to the input terminal of the AND gate circuit AND2. The input terminal of an OR gate circuit OR1 is connected to the output terminals of the AND gate circuits AND1 and AND2. The output terminal of the OR gate circuit OR1 is connected to the output terminal (DL). The error amplifier ERA1, the reference voltage E1, the capacitor C2, the switch circuit SW, the constant-current circuit IS, the comparator COMP3, and the reference voltage E2 construct a monitoring part monitoring the output voltage of the DC—DC converter 1. The comparator COMP3 and the reference voltage E2 construct a detection part detecting that the output voltage VOUT is equal to or below a later-described output reference voltage OE2. The comparator COMP2 constructs a reverse current detection part.
When the load as the power receiving side of the DC—DC converter 1 is brought to the standby state or the stop state to be in the extremely light load state, the circuit operation when stopping power supply of the DC—DC converter 1 will be described by FIG. 2.
When the power supply operation of the DC—DC converter 1 is stopped at time T10, the output of the flip-flop circuit FF is stopped to stop the regulating operation. The output level of the output terminal (Q) is brought to low level to switch the power supply stop signal STP from low to high level. The operation on the load side is also in the stop state. The coil current IL1 is 0 (A). The output voltage VOUT is an output voltage set value V1 (V). Drive signals VDH and VDL are both in the undefined state. The power supply stop signal STP at high level which is inverted to low level is inputted to the AND gate circuit AND1 of the control part 40. The output signal of the AND gate circuit AND1 is determined to be at low level. The reverse current detection signal BUD outputted from the comparator COMP2 and the output signal of the inverted output terminal (Q_) of the flip-flop circuit FF are masked by the AND gate circuit AND1. The comparator COMP2 and the flip-flop circuit FF prohibit the NMOS transistor FET2 from being controlled.
The switching control of the NMOS transistor FET2 in the periods PT3 and PT4 constructs a boosting type DC—DC converter supplying electric power from the output terminal (VO) to the input terminal (VI), combined with the body diode of the NMOS transistor FET1. The energy regenerated to the input side which is obtained by adding the energy of the output capacitor C1 to the energy stored in the choke coil L1 is regenerated to the input side.
A method of calculating the set value of the reference voltage E2 will be described. When the set value of the output voltage of the DC—DC converter 1 is the output voltage set value V1 and the capacitance on the load side is C, a total energy amount PWC stored in the capacitance on the output side at the stop of power supply are given by the following equation.
PWC=(½)×C×V12 (1)
(½)×C×VOUT2=(½)×(½)×C×V12 (2)
VOUT=( 1/2)×V1 (3)
It is found that the reference voltage E2 may be set so that the value of the output reference voltage OE2 is ( 1/2) times the output voltage set value V1.
As described above in detail, in the control circuit 11 according to the first embodiment, the electric power stored in the capacitance on the load side is reversely flowed to the choke coil L1 with the stop of the regulating operation. While regenerating the electric power to the input side, the excessive electric power stored on the load side of the DC—DC converter 1 can be rapidly lowered. The electric power returned to the inductive device is regenerated to the input side after the NMOS transistor FET2 is brought to the non-conductive state. The excessive electric power can be returned to the input side. The electric power conversion efficiency of the DC—DC converter can be improved.
A pseudo load such as a bleeder resistance need not be provided on the load side. Without additional power consumption with the bleeder resistance, the excessive electric power returned to the inductive device can be regenerated to the input side. The electric power conversion efficiency can be improved. At the timing in which half of the electric power stored in the output capacitor C1 is stored in the choke coil L1, the NMOS transistor FET2 is transited to the non-conductive state to be moved to the regenerating operation. All the electric power on the load side can be regenerated. Occurrence of resonance of the DC—DC converter 1 can be prevented.
A second embodiment of the present invention will be described using FIG. 3. The first embodiment is an embodiment of a current control type DC—DC converter. The second embodiment is an embodiment according to a voltage control type DC—DC converter.
FIG. 3 is a circuit diagram of a voltage control type DC—DC converter 1 a of a synchronous rectification type switching system according to a second embodiment. A control circuit 11 a of FIG. 3 has a PWM comparator 16 and a triangular-wave oscillator OSC2 in place of the flip-flop circuit FF and the oscillator OSC1 of the control circuit 11 of FIG. 1. The amplifier AMP1 and the comparator COMP1 of the control circuit 11 of FIG. 1 are not provided in the control circuit 11 a of FIG. 3. The PWM comparator 16 is a voltage comparator having one inverting input and one non-inverting input, and a voltage pulse width converter comparing the non-inverting input with the inverting input and outputting a pulse when the voltage of the non-inverting input is higher than that of the inverting input. The output of the triangular-wave oscillator OSC2 is inputted to the inverting input of the PWM comparator 16. The output of the error amplifier ERA1 is inputted to the non-inverting input. As compared with the DC—DC converter 1 of FIG. 1, the DC—DC converter 1 a of FIG. 3 is not provided with the sense resistance device Rs and the terminal (CS). The error amplifier ERA1, the reference voltage E1, the capacitor C2, the switch circuit SW, and the constant-current circuit IS construct a monitoring part monitoring the output voltage of the DC—DC converter 1 a. Other circuit construction is the same as the DC—DC converter 1 (FIG. 1) according to the first embodiment, and the description is omitted here.
When the power receiving side of the DC—DC converter 1 a is brought to the standby state or the stop state and is in the extremely light load state, the circuit operation when stopping the power supply operation of the DC—DC converter 1 a will be described with FIG. 3. When the power supply operation of the DC—DC converter 1 a is brought to the stop operation, the power supply stop signal STP is transited from low to high level. The power supply stop signal STP at high level which is inverted to low level is inputted to the AND gate circuit AND1 of the control circuit 11 a. The inverted output of the PWM comparator 16 is masked by the AND gate circuit AND1. This prevents the NMOS transistor FET2 from being controlled by the PWM comparator 16. The power supply stop signal STP at high level is inputted to the AND gate circuit AND2. The AND gate circuit AND2 passes the detection signal DET outputted from the comparator COMP3 as it is. The detection signal DET controls the NMOS transistor FET2. When the power supply stop signal STP is at high level, the control part 40 controls the NMOS transistor FET2 according to the detection signal DET outputted from the comparator COMP3.
The power supply operation of the DC—DC converter 1 a is stopped to stop the output of the PWM comparator 16. The output level of the output terminal (Q) is fixed to low level. The NMOS transistor FET1 is brought to the non-conductive state. The power supply stop signal STP is switched from low to high level.
The same operation of the DC—DC converter 1 according to the first embodiment is performed. The description of the detailed operation is omitted here. The electric power stored in the capacitance on the load side is reversely flowed to the choke coil L1. While regenerating the electric power to the input side, the output voltage VOUT of the DC—DC converter 1 a can be rapidly lowered.
As described above in detail, the control circuit 11 a according to the second embodiment stops the regulating operation in the voltage control type DC—DC converter 1 a and reversely flows the electric power stored in the capacitance on the load side to the choke coil L1. While regenerating the electric power to the input side, excessive power stored on the load side of the DC—DC converter 1 a can be rapidly lowered. The electric power returned to the inductive device can be regenerated to the input side. The electric power conversion efficiency of the DC—DC converter 1 a can be improved.
A third embodiment of the present invention will be described using FIG. 4. A control circuit 11 b of a DC—DC converter 1 b (FIG. 4) according to the third embodiment is a control circuit having means for lowering the reference voltage of the error amplifier ERA1 controlling the output voltage of the DC—DC converter 1 b with time, and means for forcefully continuing the switching operation at a fixed frequency after stopping the power supply of the DC—DC converter 1 b. After stopping the power supply of the DC—DC converter 1 b, it is a control circuit which can gradually lower the output voltage VOUT in a predetermined time while boosting the output voltage of the DC—DC converter using the NMOS transistor FET2 to returning it to the input side.
The control circuit 11 b of FIG. 4 has a switch circuit SW2, a resistance device R3, and a control part 40 b in place of the switch circuit SW and the control part 40 of the control circuit 11 of FIG. 1. The control part 40 b has an OR gate circuit OR2 and an AND gate circuit AND3. The reverse current detection signal BUD and the power supply stop signal STP outputted from the comparator COMP2 are inputted to the OR gate circuit OR2. The output terminal of the OR gate circuit OR2 and the inverted output terminal (Q_) of a flip-flop circuit FF are connected to the AND gate circuit AND3. The output terminal of the AND gate circuit AND3 is connected to the output terminal (DL). The power supply stop signal STP is inputted to the switch circuit SW2. The resistance device R3 is provided between the switch circuit SW2 and the ground potential. The capacitor C2, the switch circuit SW2, and the resistance device R3 construct a reference voltage part. The switch circuit SW2 and the resistance device R3 construct a discharge part forming an electric charge discharge path. The error amplifier ERA1, the reference voltage E1, the capacitor C2, the switch circuit SW2, the constant-current circuit IS, and the resistance device R3 construct a monitoring part monitoring the output voltage of the DC—DC converter 1 b. Other construction is the same as the control circuit 11 according to the first embodiment and the description is omitted here.
While starting or operating the DC—DC converter 1 b, the power supply stop signal STP at low level is inputted to the OR gate circuit OR2. The OR gate circuit OR2 performs the operation for passing the reverse current detection signal BUD outputted from the comparator COMP2 as it is to output it to the AND gate circuit AND3. It performs the same operation as the DC—DC converter 1 according to the first embodiment.
The operation when the DC—DC converter 1 b stops power supply will be described. When the DC—DC converter 1 b is brought to the stop operation, the power supply stop signal STP is switched from low to high level. The power supply stop signal STP at high level is inputted to the OR gate circuit OR2. The output signal of the OR gate circuit OR2 is defined as high level. The reverse current detection signal BUD of reverse flow prevention control of an electric current outputted from the comparator COMP2 to the choke coil L1 is masked by the OR gate circuit OR2. The NMOS transistor FET2 is constantly controlled by the inverted output of the flip-flop circuit FF. After the power supply stop signal STP is transited to high level, the regulating operation is continued. The flip-flop circuit FF continues the output of the output terminal (Q) and the inverted output terminal (Q_) at a fixed frequency. The NMOS transistor FET1 and the NMOS transistor FET2 are on/off controlled at a fixed frequency.
The switch circuit SW2 connects the terminal (SS) to the resistance device R3 according to the transition of the power supply stop signal STP to high level. The electric charge of the capacitor C2 is discharged by the resistance device R3 to gradually lower the voltage of the terminal (SS). As the voltage of the terminal (SS) as a reference voltage of the error amplifier ERA1 is gradually lowered, the DC—DC converter 1 b attempts to lower the output voltage VOUT. After the transition of the power supply stop signal STP to high level, in the initial stage in which the voltage of the terminal (SS) is lowered, the output voltage is continuously maintained by the output capacitor C1. The flip-flop circuit FF performs the reset operation by the comparator COMP1 in a short time after the set operation of the oscillator OSC1. The on-duty of the NMOS transistor FET2 is increased. The coil current IL1 starts reversely flowing via the NMOS transistor FET2 to the choke coil L1.
By the regenerating function, the output voltage of the DC—DC converter is controlled so as to output a voltage determined by the voltage of the terminal (SS) and is then gradually lowered. The gradient of the output voltage VOUT after the power supply stop signal STP is transited to high level is determined by a discharge time constant of the capacitor connected to the terminal (SS) and can be controlled without depending on the load of the DC—DC converter. The same operation is repeated at a predetermined frequency. After the elapse of a predetermined time, finally, a voltage VST of the capacitor C2 and the output voltage VOUT are both 0(V).
The NMOS transistor FET2 is non-conductive in a predetermined cycle according to the output of the flip-flop circuit FF. The amount of electric power moved from the load side to the choke coil L1 is limited. While preventing excessive electric power from being returned all together from the load side to the choke coil L1, the regenerating operation is performed for each predetermined cycle. The electric power can be gradually returned to the input side. When the load side is in the light load state or in the no-load state, the electric power is not retuned all together and the output voltage can be gradually lowered in a predetermined time. The lowering gradient of the output voltage VOUT at the stop of power supply of the DC—DC converter 1 b can be determined by the discharge time constant of the capacitor C2 connected to the terminal (SS) without depending on the load of the DC—DC converter 1 b. As described above in detail, the control circuit 11 b according to the third embodiment uses the NMOS transistor FET2 to boost the output voltage of the DC—DC converter 1 b to regenerate it to the input side and can gradually lower the output voltage VOUT in a predetermined time. When regenerating electric power exceeding the limit of the total amount of energy stored in the choke coil L1, the regeneration of the electric power is gradually performed. It is possible to prevent an excessive current flowing with the magnetic saturation of the choke coil L1 from damaging the NMOS transistor FET2 and other components. The deterioration of the characteristic of the choke coil L1 itself can be prevented.
A fourth embodiment of the present invention will be described using FIG. 5. A control circuit 11 c of a DC—DC converter 1 c shown in FIG. 5 is a circuit which can change the output voltage set value V1 of the output voltage VOUT to a lower output voltage set value V2 in a predetermined time without depending on the load of the DC—DC converter 1 c. Like the third embodiment, it is a control circuit which can gradually change the output voltage set value V1 to the output voltage set value V2 by gradually lowering the reference voltage E1 to E3.
The control circuit 11 c of FIG. 5 has a reference voltage changing part 42 in place of the reference voltage E1 of the control circuit 11 b of FIG. 4. The reference voltage changing part 42 has a switch circuit SW3, a resistance device R0, a capacitor C0, and the reference voltages E1 and E3. The inverting input terminal of the error amplifier ERA1 is connected via the capacitor C0 to the ground potential and is connected via the resistance device R0 to the switch circuit SW3. The capacitor C0 and the resistance device R0 construct an integrating circuit determining the time constant of voltage change when switching the reference voltage from the E1 to E3. A changing signal CHG is inputted to the switch circuit SW3 and the OR gate circuit OR2. The error amplifier ERA1, the reference voltage changing part 42, the capacitor C2, the switch circuit SW, the constant-current circuit IS, and the resistance device R3 construct a monitoring part monitoring the output voltage VOUT of the DC—DC converter 1 c. Other construction is the same as the DC—DC converter 1 according to the first embodiment and the description is omitted here.
The operation of the DC—DC converter 1 c will be described. The operation during the operation or the stop operation of the DC—DC converter 1 c is the same as the DC—DC converter 1 b according to the third embodiment and the description is omitted here. The operation when the DC—DC converter is brought to the changing operation of the output voltage set value and the output voltage set value is changed from the V1 to V2 will be described. The changing signal CHG is brought to high level according to the start of the changing operation. The switch circuit SW3 performs the operation for switching the reference voltage of the error amplifier ERA1 from the E1 to E3 as the changing signal CHG at high level is inputted.
The resistance device R0 and the capacitor C0 construct an integrating circuit determining a time constant of voltage change when switching the reference voltage from the E1 to E3. When the switch circuit SW3 switches the reference voltage of the error amplifier ERA1 to the reference voltage E3, the reference voltage of the error amplifier ERA1 is gradually changed from the E1 to E3. When the reference voltage of the error amplifier is gradually lowered, the DC—DC converter attempts to lower the output voltage value. When the DC—DC converter 1 c has no load, an output capacitor C1 continues to maintain the output voltage set value V1. The on-duty of the NMOS transistor FET2 is increased. The coil current IL1 starts reversely flowing via the NMOS transistor FET2 to the choke coil L1 to perform the regenerating operation of the electric power like the third embodiment.
The output voltage VOUT of the DC—DC converter is rapidly changed from the output voltage set value V1 to V2 in a time of a time constant determined by the resistance device R0 and the capacitor C0. When the changing operation of the output voltage is completed, the changing signal CHG is brought to low level. The DC—DC converter 1 c is returned to the normal operation mode to perform the regulating operation so as to output the output voltage set value V2.
As described above in detail, the control circuit 11 c according to the fourth embodiment uses the NMOS transistor FET2 to boost the output voltage of the DC—DC converter 1 b for regenerating it to the input side and can change the value of the output voltage VOUT in a predetermined time. The gradient of the output voltage VOUT when changing the output voltage of the DC—DC converter 1 c can be determined by the time constant of the integrating circuit connected to the error amplifier ERA1 without depending on the load of the DC—DC converter 1 b. When regenerating electric power exceeding the limit of the total amount of energy stored in the choke coil L1 at the change of the output voltage, the regeneration of the electric power is gradually performed. It is possible to prevent an overcurrent flowing with the magnetic saturation of the choke coil L1 from damaging the NMOS transistor FET2 and other components. The deterioration of the characteristic of the choke coil L1 itself can be prevented.
In the control parts 40, 40 b and 40 c in this embodiments, to stop the signal transmission of the reverse current detection signal BUD from the comparator COMP2 as a reverse current detection part to the NMOS transistor FET2, the method of masking the reverse current detection signal BUD is used. This form is not limited. For instance, in place of the masking method, a method of stopping the operation of the comparator COMP2 to fix the reverse current detection signal BUD to low level may be used.
According to the present invention, it is possible to provide a control circuit of a DC—DC converter of a synchronous rectification system which can realize rapid lowering of an output voltage with low power consumption by rapidly lowering the output voltage while regenerating energy stored in the capacitance component on the load side to the input side, regardless of a heavy or light load, at the stop of power supply operation and a control method thereof.
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