Source: http://patents.com/us-9934978.html
Timestamp: 2018-09-21 23:21:23
Document Index: 295035334

Matched Legal Cases: ['art 300', 'art 300', 'art 300', 'art 300', 'art 300', 'art 300', 'art 300', 'art 300', 'art 300', 'art 300']

US Patent # 9,934,978. Method of fabricating an electrical contact for use on a semiconductor device - Patents.com
United States Patent 9,934,978
Jordan April 3, 2018
Method of fabricating an electrical contact for use on a semiconductor device
According to an embodiment, a method of manufacturing a group III-V semiconductor device includes forming a gate contact that includes an electrode stack including a first titanium layer, an aluminum layer over the first titanium layer, and a second titanium layer over the aluminum layer, and forming a biased reactive capping layer over the second titanium layer. The biased reactive capping layer includes biased reactive titanium nitride. The gate contact is a gate electrode that makes Schottky contact with the group III-V semiconductor device.
Jordan; Sadiki (Torrance, CA)
Family ID: 1000003209222
15/335,608
US 20170047228 A1 Feb 16, 2017
14227167 Mar 27, 2014 9484425
12583809 Apr 1, 2014 8686562
Current CPC Class: H01L 21/28581 (20130101); H01L 21/28575 (20130101); H01L 29/401 (20130101); H01L 29/4958 (20130101); H01L 29/778 (20130101); H01L 29/7787 (20130101); H01L 29/452 (20130101); H01L 29/2003 (20130101)
Current International Class: H01L 21/285 (20060101); H01L 29/45 (20060101); H01L 29/778 (20060101); H01L 29/40 (20060101); H01L 29/49 (20060101); H01L 29/20 (20060101)
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Fernandez, et al., "Low resistance Ti / Al / Ti--W / Au Ohmic contact to n-GaN for high temperature applications", Applied Physics Letters, vol. 90, Issue 8, 083504, Feb. 2007, pp. 1-3. cited by applicant.
1. A method of manufacturing a group III-V semiconductor device, the method comprising: forming a gate contact that comprises an electrode stack including a first titanium layer, an aluminum layer over the first titanium layer, and a second titanium layer over the aluminum layer; and forming a biased reactive capping layer over the second titanium layer, the biased reactive capping layer comprising biased reactive titanium nitride, wherein the gate contact is a gate electrode that makes Schottky contact with the group III-V semiconductor device.
2. The method of claim 1, wherein the aluminum layer of the electrode stack further comprises silicon.
3. The method of claim 1, wherein the group III-V semiconductor device comprises a high electron mobility transistor (HEMT).
4. A method of manufacturing a group III-V semiconductor device, the method comprising: forming a gate contact over a gate insulator layer so as to form a gate of the group III-V semiconductor device, the gate contact comprising an electrode stack including a first titanium layer, an aluminum layer over the first titanium layer, and a second titanium layer over the aluminum layer; and forming a biased reactive capping layer over the second titanium layer, the biased reactive capping layer comprising biased reactive titanium nitride.
5. The method of claim 4, wherein the aluminum layer of the electrode stack further comprises silicon.
6. The method of claim 4, wherein the group III-V semiconductor device comprises a high electron mobility transistor (HEMT).
7. A method of fabricating an electrical contact for use on a semiconductor device, the method comprising: forming an electrode stack including a plurality of metal layers over the semiconductor device; depositing a refractory metal nitride capping layer for the electrode stack over the plurality of metal layers; and forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.
8. The method of claim 7, wherein depositing the refractory metal nitride capping layer comprises biasing a substrate supporting the semiconductor device while performing a deposition process in the presence of nitrogen gas so as to form a biased reactive refractory metal nitride capping layer over the plurality of metal layers.
9. The method of claim 7, wherein depositing the refractory metal nitride capping layer comprises depositing a titanium nitride capping layer over the plurality of metal layers.
10. The method of claim 7, wherein depositing the refractory metal nitride capping layer comprises depositing a tantalum nitride capping layer over the plurality of metal layers.
11. The method of claim 7, wherein forming the electrode stack comprises: forming a first metal layer comprising titanium; forming a second metal layer comprising aluminum over the first metal layer; and forming a third metal layer comprising titanium over the second metal layer.
12. The method of claim 7, further comprising annealing the electrode stack at a temperature of approximately 850.degree. C.
13. The method of claim 7, wherein the semiconductor device is a group III-V semiconductor device.
In the present application, "group semiconductor" refers to a compound semiconductor that includes at least one group III element and at least one group V element, such as, but not limited to, gallium nitride (GaN), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), iridium gallium nitride (InGaN) and the like. Analogously, "III-nitride semiconductor" refers to a compound semiconductor that includes nitrogen and at least one group III element, such as, but not limited to, GaN, AlGaN, InN, AlN, InGaN, InAlGaN and the like.
The present invention is generally in the field of semiconductor device fabrication. More specifically, the present invention is in the field of fabrication of compound semiconductor devices.
It is generally desirable to merge the enhanced power handling capabilities of group III-V semiconductor power devices, such as III-nitride power transistors, and the energy efficiency and ease of fabrication of lower power silicon, or other group IV semiconductor devices, on a common die. However, traditional techniques for fabricating III-nitride power transistors make monolithic integration of those devices with commonly used silicon devices quite challenging.
For example, III-nitride power semiconductor device fabrication typically includes forming electrical contacts, such as ohmic source/drain contacts, having a low Specific Linear Contact Resistivity (SCLR). Conventional approaches to implementing electrical contacts displaying suitably low SCLR values on III-nitride devices have utilized aluminum as part of an electrode stack, and a noble metal, such as gold to form a capping layer of the stack. As a specific example, an electrical contact stack comprising pure films of titanium, aluminum, and nickel, capped with gold, has been widely used.
This conventional approach entails several significant drawbacks, however. One drawback is that use of gold as a capping layer is costly. Another is that gold has been found to diffuse through the electrode stack, as well as capping it, so that some gold undesirably appears at the interface of the electrical contact and the III-nitride semiconductor body. Yet another significant drawback to the use of gold as a capping layer is its propensity to contaminate a silicon fabrication process flow. Consequently, despite its favorable contribution to desirable SCLR values, the conventional approach to using gold as a capping layer for electrical contacts formed on III-nitride power semiconductor devices makes it particularly difficult to integrate those devices with silicon devices.
Thus, there is a need to overcome the drawbacks and deficiencies in the art by providing an electrical contact for use on a group III-V semiconductor device that renders integration of group III-V and group IV semiconductor devices more efficient and cost effective by posing a reduced contamination risk to silicon, or other group IV semiconductor fabrication process flows.
A refractory metal nitride capped electrical contact and method for fabricating same, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
FIG. 1 is a block diagram showing a group semiconductor device including a plurality of refractory metal nitride capped electrical contacts, according to one embodiment of the present invention.
FIG. 2 is a more detailed block diagram showing a refractory metal nitride capped electrical contact, according to one embodiment of the present invention.
FIG. 3 is a flowchart presenting a method for fabricating a refractory metal nitride capped electrical contact, according to one embodiment of the present invention.
The present invention is directed to a refractory metal nitride capped electrical contact and a method for its fabrication. More specifically, the present invention discloses such a contact for implementation as an electrode on a semiconductor device, such as a group III-V power semiconductor device, for example. Although the present inventive concepts are described with respect to specific embodiments, the principles of the invention, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments of the invention described herein. Moreover, in the description of the present invention, certain details have been left out in order to not obscure the inventive aspects of the invention. The details left out are within the knowledge of a person of ordinary skill in the art.
FIG. 1 is a block diagram showing an example group III-V semiconductor device including a plurality of refractory metal nitride capped electrical contacts, according to one embodiment of the present invention. Structure 100, in FIG. 1, shows a specific implementation of the present inventive concepts. It should be understood that particular details such as the materials used to form structure 100 and the semiconductor device represented by structure 100, for example, are provided for conceptual clarity, and should not be interpreted as limitations.
As shown in FIG. 1, structure 100 comprises a group III-V semiconductor high electron mobility transistor (HEMT) implemented in gallium nitride (GaN). Structure 100 includes substrate 102, transition structure 104, and GaN body 110 comprising GaN layer 112 and aluminum gallium nitride (AlGaN) layer 114. Structure 100 also includes a plurality of electrical contacts including source electrode 136, drain electrode 138, and insulated gate electrode 132. Further shown in FIG. 1 is two-dimensional electron gas (2DEG) 116, which provides a conduction channel for the charge carriers of the HEMT, and is generated at the heterojunction formed by the interface of GaN layer 112 and AlGaN layer 114, in GaN body 110.
Substrate 102 may comprise any commonly utilized substrate material for GaN, such as sapphire, silicon, or silicon carbide, for example. As shown in FIG. 1, in the present embodiment, GaN body 110 is formed over transition structure 104, which is itself formed over substrate 102. It is noted that the present embodiment is merely one representation of a group III-V semiconductor device, however, and in other embodiments, transition structure 104 may not be utilized. For example, where substrate 102 is a suitable native substrate for GaN layer 112, GaN layer 112 may be formed on substrate 102, eliminating transition structure 104 entirely.
Where, however, as in the present embodiment, transition structure 104 is used, transition structure 104 may correspond to a plurality of distinguishable layers mediating the lattice transition from substrate 102 to GaN layer 112. Transition structure 104 may include, for example, a series of AlGaN layers comprising progressively less aluminum nitride and more gallium nitride, until a suitable transition to GaN layer 112 is achieved.
Source electrode 136 and drain electrode 138 are power electrodes ohmically coupled to the heterojunction formed by GaN layer 112 and AlGaN layer 114. Moreover, insulated gate electrode 132 is situated between source electrode 136 and drain electrode 138, on GaN body 110. As shown in FIG. 1, each of source electrode 136, drain electrode 138, and insulated gate electrode 132 comprises electrode stack 120. Electrode stack 120 includes a refractory metal nitride capping layer (not explicitly shown in FIG. 1), such as a titanium nitride (TiN) capping layer, for example. As further shown in FIG. 1, insulated gate electrode 132 includes gate insulator layer 134, such as a silicon nitride (Si.sub.3N.sub.4) or silicon dioxide (SiO.sub.2) layer, for example, underlying electrode stack 120. It is noted that although in the embodiment of FIG. 1, gate electrode 132 is shown as an insulated gate electrode, in other embodiments, gate electrode 132 comprising electrode stack 120 may make Schottky contact with GaN body 110.
Turning now to FIG. 2, FIG. 2 is a more detailed block diagram showing a refractory metal nitride capped electrical contact, according to one embodiment of the present invention. FIG. 2 shows electrical contact 230 comprising electrode stack 220. Electrical contact 230 may be seen to correspond to any of source electrode 136, drain electrode 138, or insulated gate electrode 132, in FIG. 1. Electrode stack 220, which corresponds to electrode stack 120 in FIG. 1, includes first titanium (Ti) layer 222, aluminum (Al) layer 224, second Ti layer 226, and TiN capping layer 228.
More generally, electrode stack 220 corresponds to an electrode, stack including a plurality metal layers, e.g., first Ti layer 222, Al layer 224, and second Ti layer 226, and a capping layer comprising a refractory metal nitride. The expression "refractory metal" may be interpreted in more than one way, as is commonly acknowledged in the art. For the purposes of the present application, the wider definition of refractory metal to include the elements Ti, zirconium (Zr), and vanadium (Vn), as well as the traditionally recognized refractory metals niobium (Nb), molybdenum (Mo), tantalum (Ta), and tungsten (W), is adopted. Thus, "refractory metal nitride" may refer to any of TiN, TaN, ZrN, VN, NbN, MoN, and WN.sub.2, or any combination of those refractory nitride compounds.
Moreover, the number and character of the plurality of metal layers 222, 224, and 226 of electrode stack 220 are merely exemplary. As a result, in other embodiments, electrode stack 220 may comprise more, or fewer, metal layers underlying the refractory metal nitride capping layer, e.g., TiN capping layer 228, and the plurality of metal layers may be different from those shown in FIG. 2. For example, second Ti layer 226 may in other embodiments correspond to a nickel (Ni) layer, while in some embodiments Al layer 224 may further comprise silicon (Si) up to approximately ten percent (10%) by weight.
The present inventive concepts will be further described by reference to flowchart 300, in FIG. 3, which describes the steps, according to one embodiment of the present invention, of a method for fabricating a refractory metal nitride capped electrical contact. It is noted that certain details and features have been left out of flowchart 300 that are apparent to a person of ordinary skill in the art. For example, a step may comprise one or more substeps or may involve specialized equipment or materials, as known in the art. While steps 310 through 360 indicated in flowchart 300 are sufficient to describe one embodiment of the present invention, other embodiments of the invention may utilize steps different from those shown in flowchart 300.
Beginning with step 310 of flowchart 300 and referring to FIGS. 1 and 2, step 310 of flowchart 300 comprises forming first Ti layer 222 of electrode stack 120 over GaN body 110 formed over substrate 102. Any suitable deposition process may be used to form first Ti layer 222. For example, first Ti layer 222 may be sputter deposited over GaN body 110. Alternatively, Ti layer 222 may formed using a chemical vapor deposition (CVD) or electron beam deposition process, for example. It is contemplated that first Ti layer 222 is formed to a thickness of approximately 100 .ANG., plus or minus approximately ten percent (+/-10%). Although the present embodiment refers to formation of first Ti layer 222 over GaN body 110, it is emphasized that GaN body 110 may correspond to a body formed from any combination of suitable group III-V semiconductor materials, as described in the "Definition" section above.
Typically, the only constraint placed upon the composition of GaN body 110 is that it comprise at least one layer of a group III-V semiconductor material. In some embodiments, as shown in FIG. 1, GaN body 110 may comprise a first group III-V semiconductor layer, e.g., GaN layer 112, and a second group III-V semiconductor layer formed over the first III nitride semiconductor layer, e.g., AlGaN layer 114 formed over GaN layer 112, for example, wherein the second group semiconductor layer comprises a group III-V semiconductor having a different, e.g., wider, band gap than the group III-V semiconductor forming the first group III-V semiconductor layer.
Continuing with step 320 of FIG. 3, step 320 of flowchart 300 comprises forming Al layer 224 of electrode stack 120 over first Ti layer 222 of electrode stack 120. As was the case for formation of first Ti layer 222, in step 310, formation of Al layer 224 in step 320 may proceed using any suitable deposition technique, such as sputter deposition, CVD, or electron beam deposition. As shown in FIG. 2, in the present embodiment, Al layer 224 is formed to a greater thickness than first Ti layer 222. Al layer 224 may be formed to a thickness of approximately 1300 .ANG., plus or minus approximately ten percent (+/-10%), for example.
Moving to step 330 of flowchart 300, step 330 comprises forming second Ti layer 226 of electrode stack 120 over Al layer 224 of electrode stack 120. Once again, formation of second Ti layer 226 in step 330 may proceed using any suitable deposition technique, such as sputter deposition, CVD, or electron beam deposition. As shown in FIG. 2, in the present embodiment, second Ti layer 226 is formed to a thickness greater than that of first Ti layer 222, and less than that of Al layer 224, but that representation is merely exemplary. In the present embodiment, for example, second Ti layer 226 may be formed to a thickness of approximately 680 .ANG., plus or minus approximately ten percent (+/-10%).
Continuing with step 340 of flowchart 300, step 340 comprises depositing biased reactive TiN capping layer 228 over second Ti layer 226. As is well known in the art, a species of TiN having a particularly high density, i.e., "biased reactive TiN" (also referred to in the art as "gold" TiN), can be formed by deposition of TiN onto a body supported by a substrate to which an appropriate biasing voltage is applied, in the presence of nitrogen gas with which the TiN reacts. Thus, in one embodiment, substrate 102 supporting GaN body 110, in FIG. 1, may receive a biasing voltage during deposition of TiN capping layer 228 of electrode stack 120, in a deposition chamber to which nitrogen gas has been introduced.
As shown in FIG. 2, in the present embodiment, TiN capping layer 228 is formed to a thickness comparable to that of second Ti layer 226. For example, TiN capping layer 228 may be formed to a thickness of approximately 600 .ANG., plus or minus approximately ten percent (+/-10%). As previously mentioned, other embodiments may employ a different refractory metal nitride capping layer in place of TiN capping layer 228. For instance, in one embodiment, refractory metal nitride capping of electrode stack 220 may be performed by a TaN capping layer corresponding to TiN capping layer 228.
In step 350 of flowchart 300, TiN capping layer 228, second Ti layer 226, Al layer 224, and first Ti layer 222 may be patterned and plasma etched to form one or more of electrode stacks 120 over GaN body 110. Subsequently, in step 360, electrode stacks 120 are annealed at approximately 850.degree. C. for approximately sixty seconds to produce one or more electrical contacts, e.g., source contact 136 and/or drain contact 138, on GaN body 110. In some embodiments, annealing of electrode stacks 120, in step 360, may be performed in the presence of nitrogen gas.
Thus, according to the present invention, the novel refractory metal nitride capped electrical contact described herein presents significant advantages over the conventional art, such as rendering integration of group III-V and group IV semiconductor devices more efficient and cost effective by posing a reduced contamination risk to silicon, or other group IV semiconductor fabrication process flows.
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