Source: https://patents.google.com/patent/US8508984B2/en
Timestamp: 2019-08-22 23:46:15
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Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'arts 2', 'arts 2']

US8508984B2 - Low resistance high-TMR magnetic tunnel junction and process for fabrication thereof - Google Patents
Low resistance high-TMR magnetic tunnel junction and process for fabrication thereof Download PDF
US8508984B2
US8508984B2 US12/040,801 US4080108A US8508984B2 US 8508984 B2 US8508984 B2 US 8508984B2 US 4080108 A US4080108 A US 4080108A US 8508984 B2 US8508984 B2 US 8508984B2
US12/040,801
US20080164548A1 (en
2008-02-29 Application filed by Avalanche Tech Inc filed Critical Avalanche Tech Inc
2008-03-24 Assigned to YADAV TECHNOLOGY INC. reassignment YADAV TECHNOLOGY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KESHTBOD, PARVIZ, MALMHALL, ROGER KLAS, RANJAN, RAJIV YADAV
2008-07-10 Publication of US20080164548A1 publication Critical patent/US20080164548A1/en
2013-08-13 Publication of US8508984B2 publication Critical patent/US8508984B2/en
This application is a continuation-in-part of U.S. application Ser. No. 11/674,124 filed on Feb. 12, 2007, entitled “Non-Uniform Switching Based Non-Volatile Magnetic Based Memory,” which claims priority to U.S. Provisional Application No. 60/853,115 filed on Oct. 20, 2006 entitled “Non-Uniform Switching Based Non-Volatile Magnetic Based Memory”; and is a further continuation-in-part of U.S. application Ser. No. 11/678,515 filed Feb. 23, 2007, entitled “A High Capacity Low Cost Multi-State Magnetic Memory,” which claims priority to U.S. Provisional Application No. 60/777,012 filed Feb. 25, 2006 entitled “A High Capacity Low Cost Multi-State Magnetic Memory”; and is a further continuation-in-part of U.S. application Ser. No. 11/739,648, filed Apr. 24, 2007 entitled “Non-Volatile Magnetic Memory with Low Switching Current and High Thermal Stability”; and is a further continuation-in-part of U.S. application Ser. No. 11/740,861, filed Apr. 26, 2007, titled “High Capacity Low Cost Multi-Stacked Cross-Line Magnetic Memory”; and is a further continuation-in-part of U.S. application Ser. No. 11/776,692, filed Jul. 12, 2007, titled “Non-Volatile Magnetic Memory Element with Graded Layer”; and is a further continuation-in-part of U.S. application Ser. No. 11/860,467 filed Sep. 24, 2007, titled “Low cost multi-state magnetic memory”; and is a further continuation-in-part of U.S. application Ser. No. 11/866,830 filed Oct. 3, 2007 entitled “Improved High Capacity Low Cost Multi-State Magnetic Memory”; and is a further continuation-in-part of U.S. application Ser. No. 11/932,940 filed Oct. 31, 2007 entitled “Current-Confined Effect of Magnetic Nano-Current-Channel (NCC) for Magnetic Random Access Memory (MRAM),” which claims priority to U.S. Provisional Application No. 60/863,812 filed Nov. 1, 2006 entitled “Novel Spintronic Device.”
The challenge with other prior art techniques has been that the switching current is too high to allow the making of a functional device for memory applications due to the memory's high power consumption. The high switching current is due, at least partly, to the memory element's electrical resistance. Several current solutions suggest that the switching current can be reduced by having the memory element pinned by two anti-ferromagnetic (AF)-couple layers resulting in spin oscillations or “pumping” and thereby reducing the switching current. Although these methods are helpful in reducing the memory element's resistance, further improvements in reducing the resistance of magnetic memory devices is desirable.
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a structure and a corresponding method for fabrication of a magnetic storage memory device that is based on current-induced-magnetization-switching having reduced switching current in the magnetic memory.
FIG. 1( a) shows relevant layers of a magnetic tunneling junction (MTJ) to include a fixed layer, a barrier (or tunneling) layer, and a free layer.
U.S. application Ser. No. 11/932,940 filed Oct. 31, 2007 titled “current-confined effect of magnetic nano-current-channel (NCC) for magnetic random access memory (MRAM)” by Wang,
U.S. application Ser. No. 11/866,830 filed Oct. 3, 2007, titled “Improved high capacity low cost multi-state magnetic memory” by Ranjan et alia, and
U.S. application Ser. No. 11/860,467 filed Sep. 24, 2007, titled “Low cost multi-state magnetic memory” by Ranjan et alia.
Typically, a non-volatile magnetic memory element includes a free layer, a barrier layer, and a fixed layer among a plurality of layers. Together, these layers comprise a magnetic tunneling junction (MTJ). Each memory element is comprised of a single MTJ, or multiple MTJs “stacked” upon each other in order to increase memory storage density. The fixed layer's magnetic polarity is static, or “fixed,” for example by an adjacent “pinning layer.” The free layer's magnetic polarity can be switched between at least two states by passing an electrical current through the MTJ.
As electrons flow through the free layer, the magnetic moment of the free layer polarizes the “spin-states” of the electrons. The quantum tunneling effect, which is well-known to those familiar with the art, causes a portion of the spins to tunnel through the barrier layer. The probability that any given spins will tunnel through the barrier layer is determined by the spin states of that electron and the magnetic moment of the fixed layer.
T =  j transmitted   j incident  , Equation ⁢ ⁢ ( 1 )
where jincident is the probability current in the wave incident upon the barrier and jtransmitted is the probability current in the wave moving away from the barrier on the other side.
R = 1 T - 1 Equation ⁢ ⁢ ( 2 )
Therefore, for example, a barrier layer with a tunneling coefficient of zero is deemed to have infinite resistivity, whereas a barrier layer with a tunneling coefficient of 1 is deemed to have zero resistivity. It should be noted that Equation (2) is shown here to merely illustrate the relationship between a barrier layer's electrical resistivity with its tunneling coefficient. Equation (2) is not necessarily widely used in the art, nor is the value of resistivity necessarily measured in Ohms.
Effectively, the resistance of the MTJ is determined by the direction of the magnetic moments of the MTJs' free and fixed layers in respect to each other. The MTJ takes on one of several states at any given time, each having a unique electrical resistivity. In its simplest form, the MTJ has only two states, representing a binary 1 or 0. Other exemplary embodiments of the MTJ are disclosed in the applications incorporated by reference hereinabove, For example, U.S. Application No. 60/853,115, filed Oct. 20, 2006, titled “Non-Uniform Switching Based Non-Volatile Magnetic Base Memory” by Ranjan, discloses a non-uniform switching layer to reduce the current necessary to switch the magnetic moment of the free layer. Similarly, U.S. application Ser. No. 11/860,467 filed Sep. 24, 2007, titled “Low cost multi-state magnetic memory” by Ranjan et alia discloses MTJs that have several states. The several states represent more than one binary digit. For example, a 4-state MTJ can depict binary values 00, 01, 10, and 11.
The fixed layer 101 is generally made of magnetic material and in an exemplary embodiment is typically made of CoFe alloys. In one embodiment, the fixed layer 101 comprises of three layers namely, Cobalt-iron-boron alloy, CoFeB, Ruthenium, Ru, and Cobalt-iron alloy, CoFe, with CoFeB alloy layer being largely amorphous and placed adjacent to the barrier layer. The barrier layer 103 is generally made of non-magnetic material, such as magnesium oxide (MgO), titanium oxide (TiO2), aluminum oxide (Al2O3), ruthenium oxide (RuO), strontium oxide (SrO), europium oxide (EuO) and any combination of these as well as other minority oxides. The free layer 107 is generally made of magnetic material and in an exemplary embodiment is made of Cobalt-iron-boron alloy, CoFeB or multi-layers of CoFe or NiFe or other relatively lower anisotropy alloys of Cobalt, Co, iron, Fe, and nickel, Ni.
FIG. 1( b) shows relevant layers of one embodiment of a non-uniform switching based non-volatile magnetic memory element 100, in accordance with an embodiment of U.S. application Ser. No. 11/674,124, filed Feb. 12, 2007, titled “Non-Uniform Switching Based Non-Volatile Magnetic Based Memory” by Ranjan et alia, the contents of which are incorporated by reference hereinabove.
In one embodiment of the memory element 100, the fixed layer 101 is multi-layered, the multiple layers of which, in an exemplary embodiment are the following layers: cobolt iron chromium, on top of which is formed Ruthenium X (RuX), where X is one or more of the following: Chromium Cr, Molybdenum (Mo) and Tantalum (Ta), on top of which is formed cobolt iron boron chromium x (CoFeBCrx), wherein, x is typically 0-15 atomic percent.
FIG. 7 shows the molecular structure of the barrier (tunneling) layer 103, which is comprised of molecules 500 in a 3-dimensional lattice configuration. The natural tendency of MgO is to form into a lattice structure, absent a crystalline underlying structure. The lattice is often compromised of a plurality of generally cube-shaped “unit cells.” In this context a “unit cell” is often defined as the minimum number of atoms that replicate in the structure.
α = Δ ⁢ ⁢ l / l Δ ⁢ ⁢ T Equation ⁢ ⁢ ( 3 )
Where Δl/l represents the ratio of change of length, and ΔT represents change in temperature, as measured in degrees Kelvin. The unit for a is commonly K−1.
In one embodiment of the present invention, the α of the CSIL 200 should be at least twice that of the barrier layer 103. In an exemplary embodiment, the CSIL 200 has an α greater than 15×10−6. Table 1 below shows a list of some of the materials that can be used to form the CSIL 200, and their corresponding α:
Material α
Al 25 × 10−6
Cu 17 × 10−6
Zn 35 × 10−6
CuZn 19 × 10−6
Ag 18 × 10−6
The α of the barrier layer 103 depends upon the material used. In an exemplary embodiment, where the barrier layer 103 is formed from MgO, it has an α that is typically less than 1e-06.
The CSIMs 501, typically being smaller than the other unit cells 500 in the barrier layer 103(b), induce compressive stress upon the entire barrier layer 103(b), thus reducing its electrical resistivity, Examples of materials that may be used for the CSIM include, but are not limited to Ruthenium oxide, RuO2, strontitum oxide, SrO, strontium titanate, SrTiO3, calcium oxide, CaO, titanium oxide, TiO2, europium oxide, EuO. Of these, RuO2, SrO and EuO are the more preferred as they pertain similar cubic structure as MgO. The typical percentages of these are below 50 mol % with a preferred range being below 10 mol %. The final film can be formed preferably by rf-sputtering form one composite target although these can be premixed in the plasma through multiple target sources or by using reactive sputtering such as in presence of a Ar—O2 or such oxidizing gases.
a magnetic tunneling junction (MTJ) including a barrier layer, said barrier layer having associated therewith an electrical resistivity, and
a compressive stress inducing layer (CSIL) formed on top of said MTJ and characterized to induce compressive stress on said MTJ thereby reducing electrical resistively of the barrier layer thereof.
2. The current-switching non-volatile magnetic memory element, as recited in claim 1, wherein said MTJ comprises:
said barrier layer formed on top of said fixed layer; and
a free layer formed on top of said barrier layer.
3. The current-switching non-volatile magnetic memory element, as recited in claim 1, wherein said MTJ comprises:
said barrier layer formed on top of said free layer; and
a fixed layer formed on top of said barrier layer.
4. The current-switching non-volatile magnetic memory element, as recited in claim 1, wherein said CSIL comprises one or more of the following materials: Al, Cu, Zn, CuZn, Ag., Ru, Ta, W, TiW, NiAL, RuAl, or NiNb.
5. The current-switching non-volatile magnetic memory element, as recited in claim 1, wherein said CSIL is deposited at a temperature in excess of 250° C.
6. A current-switching non-volatile magnetic memory element including;
a compressive stress inducing layer (CSIL); and
a magnetic tunneling junction (MTJ) formed on top of said CSIL,
said MTJ including a barrier layer, said barrier layer having associated therewith an electrical resistivity,
wherein said electrical resistivity of said barrier layer in said MTJ is reduced by compressive stress induced by said CSIL.
7. The current-switching non-volatile magnetic memory element, as recited in claim 6, wherein said MTJ comprises:
a fixed layer, said barrier layer formed on said fixed layer; and
a free layer formed on said barrier layer.
8. The current-switching non-volatile magnetic memory element, as recited in claim 6, wherein said MTJ comprises:
a free layer, said barrier layer formed on top of said free layer; and
9. The current-switching non-volatile magnetic memory element, as recited in claim 6, wherein said CSIL comprises one or more of the materials: Al, Cu, Zn, CuZn, Ag., Ru, Ta, W, TiW, NiAL, RuAl, or NiNb.
10. The current-switching non-volatile magnetic memory element, as recited in claim 6, wherein said CSIL is deposited at a temperature in excess of 250° C.
11. A method of manufacturing current-switching non-volatile magnetic memory element comprising:
forming a magnetic tunneling junction (MTJ) including a barrier layer, said barrier layer having associated therewith an electrical resistivity; and
depositing at high temperature, a compressive stress inducing layer (CSIL) on top of said MTJ,
wherein said CSIL, upon cooling, shrinks, thus inducing compressive stress on said barrier layer and resulting in reduction of electrical resistivity of said barrier layer.
12. The method of manufacturing current-switching non-volatile magnetic memory, as recited in claim 11, wherein said forming the MTJ step comprises:
forming a fixed layer;
depositing said barrier layer on top of said fixed layer; and
depositing a free layer on top of said barrier layer.
13. The method of manufacturing current-switching non-volatile magnetic memory, as recited in claim 11, wherein said forming the MTJ step comprises:
depositing said barrier layer on top of said free layer; and
depositing a fixed layer on top of said barrier layer.
14. The method of manufacturing current-switching non-volatile memory element, as recited in claim 11, wherein the CSIL is deposited at a temperature in excess of 250° C.
15. The method of manufacturing current-switching non-volatile memory element, as recited in claim 11, wherein said CSIL comprises one or more of the materials: Al, Cu, Zn, CuZn, Ag., Ru, Ta, W, TiW, NiAL, RuAl, or NiNb.
16. A method of manufacturing current-switching non-volatile magnetic memory element comprising:
forming a magnetic tunneling junction (MTJ) including a barrier layer, said barrier layer having associated therewith an electrical resistivity,
wherein electrical resistivity of said barrier layer is reduced by depositing said barrier layer under compressive film stress in a sputtering process with an inert gas.
17. The method of manufacturing current-switching-non-volatile memory element, as recited in claim 16, wherein said inert gas used in said sputtering process is comprised substantially of Ar, Kr, or Xe.
18. The method of manufacturing current-switching non-volatile memory element, as recited in claim 16, wherein said inert gas used during said sputtering process is at pressures less than 15 m Torrs.
19. The method of manufacturing current-switching-non-volatile memory element, as recited in claim 16, wherein said MTJ is formed by;
depositing said barrier layer on top of said free layer, and
20. The method of manufacturing current-switching-non-volatile memory element, as recited in claim 16, wherein said MTJ is formed by the steps of:
21. The method of manufacturing current-switching non-volatile magnetic memory element comprising:
wherein electrical resistivity of said barrier layer is reduced by dissolving into a molecular lattice of said barrier layer, compressive-stress-inducing molecules (CSIM).
22. The method of manufacturing current-switching-non-volatile memory element, as recited in claim 21, wherein said MTJ is formed by the steps of:
23. The method of manufacturing current-switching-non-volatile memory element, as recited in claim 21, wherein said MTJ is formed by the steps of:
depositing said barrier layer on said fixed layer; and
depositing a free layer on said barrier layer.
24. The method of manufacturing current-switching non-volatile magnetic memory element, as recited in claim 21, wherein the barrier layer is formed substantially from MgO, and the CSIM that is dissolved into the barrier layer molecular lattice is comprised substantially of: RuO2, SrO, TiO2, SrTiO2, CaO, or EuO.
25. The method of manufacturing current-switching non-volatile magnetic memory element, as recited in claim 21, wherein the percent of CSIM dissolved into the molecular lattice of the barrier layer is below 10 mol %.
US12/040,801 2006-02-25 2008-02-29 Low resistance high-TMR magnetic tunnel junction and process for fabrication thereof Active 2030-11-10 US8508984B2 (en)
PCT/US2008/065066 WO2009108212A1 (en) 2008-02-29 2008-05-29 An improved low resistance high-tmr magnetic tunnel junction and process for fabrication thereof
US13/720,327 Continuation-In-Part US8760914B2 (en) 2006-02-25 2012-12-19 Magnetic memory write circuitry
US12/125,866 Continuation-In-Part US8363457B2 (en) 2006-02-25 2008-05-22 Magnetic memory sensing circuit
US20080164548A1 US20080164548A1 (en) 2008-07-10
US8508984B2 true US8508984B2 (en) 2013-08-13
ID=41016398
US12/040,801 Active 2030-11-10 US8508984B2 (en) 2006-02-25 2008-02-29 Low resistance high-TMR magnetic tunnel junction and process for fabrication thereof
US (1) US8508984B2 (en)
WO (1) WO2009108212A1 (en)
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