Source: http://www.google.com/patents/US7788514?ie=ISO-8859-1&dq=6702462
Timestamp: 2014-07-23 22:52:08
Document Index: 190729870

Matched Legal Cases: ['Application No. 05010673', 'Application No. 05010671', 'Application No. 05010672', 'Application No. 05010676', 'Application No. 05010993', 'Application No. 05010992', 'Application No. 05010994', 'Application No. 05010673', 'art 16', 'art 16']

Patent US7788514 - Low power computer with main and auxiliary processors - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn architecture for a computer includes a primary processor that consumes power at a first rate, that is operated when the computer is in an high power mode and that is not powered when the computer is in a low power mode. A primary graphics processor communicates with the primary processor, is operated...http://www.google.com/patents/US7788514?utm_source=gb-gplus-sharePatent US7788514 - Low power computer with main and auxiliary processorsAdvanced Patent SearchPublication numberUS7788514 B2Publication typeGrantApplication numberUS 12/152,030Publication dateAug 31, 2010Filing dateMay 12, 2008Priority dateJun 10, 2004Fee statusPaidAlso published asCN1707400A, CN1707400B, CN1866161A, CN1866161B, CN1866162A, CN1866162B, EP1605361A2, EP1605361A3, EP1607836A2, EP1607836A3, EP1621972A2, EP1621972A3, US7730335, US7827423, US8572416, US20050278559, US20080222357, US20080222437, US20100235660, US20140052887Publication number12152030, 152030, US 7788514 B2, US 7788514B2, US-B2-7788514, US7788514 B2, US7788514B2InventorsSehat Sutardja, Hong-Yi ChenOriginal AssigneeMarvell World Trade Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (54), Non-Patent Citations (41), Referenced by (2), Classifications (18), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetLow power computer with main and auxiliary processorsUS 7788514 B2Abstract An architecture for a computer includes a primary processor that consumes power at a first rate, that is operated when the computer is in an high power mode and that is not powered when the computer is in a low power mode. A primary graphics processor communicates with the primary processor, is operated when the computer is in the high power mode and is not powered when the computer is in the low power mode. A secondary graphics processor communicates with a secondary processor. The secondary processor consumes power at a second rate that is less than the first rate. The secondary processor and the secondary graphics processor are operated when the computer is in the low power mode.
1. A computer system that operates in low power and high power modes, the computer system comprising:
nonvolatile memory that comprises:
a low power disk drive (LPDD); and
a high-power disk drive (HPDD);
an operating system that provides a virtual memory, wherein:
said virtual memory includes at least a portion of said volatile memory;
said operating system includes a virtual memory adjustment module; and
said virtual memory adjustment module enables designation of at least a portion of said nonvolatile memory for paging files to increase virtual memory of said computer system; and
a drive control module that controls data access to said LPDD and said HPDD,
said designation of said at least a portion of said nonvolatile memory is based on a user request to increase said virtual memory; and
said drive control module at least one of:
selectively controls data access to said LPDD and said HPDD independent of control signals from a host computer; and
selectively controls data transfer between said LPDD and said HPDD independent of said control signals from said host computer.
said operating system increases an amount of said nonvolatile memory;
said amount of said nonvolatile memory is designated for said paging files based on said user request.
3. The computer system of claim 2, wherein said user request indicates said amount.
said operating system selectively stores said paging files in said LPDD.
said drive control module is implemented as a system on chip (SOC) in a multi-disk drive system;
said multi-disk drive system includes said LPDD and said HPDD; and
said SOC is connected between said host computer and said multi-disk drive system.
6. The computer system of claim 5, further comprising a host control module that provides an interface between said drive control module and said host computer.
7. The computer system of claim 6, wherein said host control module is implemented as part of said SOC.
8. The computer system of claim 6, wherein said drive control module includes:
a hard drive controller (HDC) that communicates with said host control module;
high power (HP) and low power (LP) spindle/voice coil motor (VCM) drivers that communicate with said HDC and said HPDD and said LPDD, respectively; and
HP and LP read/write channel circuits that communicates with said HDC and said HPDD and said LPDD, respectively.
9. The computer system of claim 6, wherein said drive control module comprises:
a first spindle/voice coil motor (VCM) driver that communicate with said HDC and said HPDD; and
a first read/write channel circuit that communicates with said HDC and said HPDD.
10. The computer system of claim 9, wherein said drive control module include an interface that is connected between said HDC and another interface of said LPDD.
a host control module that is in communication with a host computer;
a first drive control module that is connected between said host control module and said HPDD; and
a second drive control module that is connected between said host control module and said LPDD.
12. The computer system of claim 11, wherein said first drive control module comprises:
a first hard drive controller (HDC) that communicates with said host control module;
a first spindle/voice coil motor (VCM) driver that communicates with said first HDC and said HPDD; and
a first read/write channel circuit that communicates with said first HDC and said HPDD.
13. The computer system of claim 12, wherein said second drive control module comprises:
a second hard drive controller (HDC) that communicates with said host control module;
a second spindle/voice coil motor (VCM) driver that communicates with said second HDC and said LPDD; and
a second read/write channel circuit that communicates with said second HDC and said LPDD.
14. A method for storing data in a computer system that operates in low power and high power modes, the method comprising:
providing volatile memory;
providing nonvolatile memory that includes at least one of a low power disk drive (LPDD);
providing a virtual memory that includes at least a portion of said volatile memory;
receiving a user request to increase said virtual memory;
enabling designation of at least a portion of said nonvolatile memory for paging files to increase virtual memory of the computer system based on said user request;
providing said LPDD;
providing a high-power disk drive (HPDD);
controlling data access to said LPDD and said HPDD via a drive control module; and
selectively controlling data access to said LPDD and said HPDD independent of control signals from a host computer; and
selectively controlling data transfer between said LPDD and said HPDD independent of said control signals from said host computer.
15. The method of claim 14, comprising increasing an amount of said nonvolatile memory that is designated for said paging files based on said user request.
16. The method of claim 15, wherein said user request indicates said amount.
wherein said paging files are selectively stored in said LPDD.
18. The method of claim 17, wherein said drive control module is implemented as a system on chip (SOC) in a multi-disk drive system that includes said LPDD and said HPDD.
19. The method of claim 17, further comprising providing an interface between said drive control module and said host computer via a host control module.
communicating with said host control module via a hard drive controller (HDC);
communicating with said HDC and said HPDD and said LPDD, respectively via high power (HP) and low power (LP) spindle/voice coil motor (VCM) drivers; and
communicating with said HDC and said HPDD and said LPDD, respectively via HP and LP read/write channel circuits.
communicating with said HDC and said HPDD via a first spindle/voice coil motor (VCM) driver; and
communicating with said HDC and said HPDD a first read/write channel circuit.
22. The method of claim 20, further comprising providing an interface that is connected between said HDC and another interface of said LPDD.
providing a host control module that is in communication with said host computer;
providing a first drive control module that is connected between said host control module and said HPDD; and
providing a second drive control module that is connected between said host control module and said LPDD.
communicating with said host control module via a first hard drive controller (HDC);
communicating with said first HDC and said HPDD via a first spindle/voice coil motor (VCM) driver; and
communicating with said first HDC and said HPDD via a first read/write channel circuit.
communicating with said host control module via a second hard drive controller (HDC);
communicating with said second HDC and said LPDD via a second spindle/voice coil motor (VCM) driver; and
communicating with said second HDC and said LPDD via a second read/write channel circuit.
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional of U.S. patent application Ser. No. 10/865,732, filed Jun. 10, 2004. This application is related to U.S. patent application Ser. No. 10/779,544, filed Feb. 13, 2004 and U.S. patent application Ser. No. 10/865,368, filed Jun. 10, 2004. The disclosures of the above application are incorporated herein by reference in their entirety.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4425615Nov 14, 1980Jan 10, 1984Sperry CorporationHierarchical memory system having cache/disk subsystem with command queues for plural disksUS5485595Oct 4, 1993Jan 16, 1996Cirrus Logic, Inc.Flash memory mass storage architecture incorporating wear leveling technique without using cam cellsUS5581736 *Jul 18, 1994Dec 3, 1996Microsoft CorporationIn a computer systemUS5596708Jan 25, 1996Jan 21, 1997At&T Global Information Solutions CompanyMethod and apparatus for the protection of write data in a disk arrayUS5659718Aug 19, 1994Aug 19, 1997Xlnt Designs, Inc.Synchronous bus and bus interface deviceUS5768164Apr 15, 1996Jun 16, 1998Hewlett-Packard CompanySpontaneous use display for a computing systemUS5809336Jun 7, 1995Sep 15, 1998Patriot Scientific CorporationHigh performance microprocessor having variable speed system clockUS5937423Dec 26, 1996Aug 10, 1999Intel CorporationRegister interface for flash EEPROM memory arraysUS6035408Jan 6, 1998Mar 7, 2000Magnex Corp.Portable computer with dual switchable processors for selectable power consumptionUS6122720Aug 7, 1998Sep 19, 2000Altera CorporationCoarse-grained look-up table architectureUS6282614Apr 15, 1999Aug 28, 2001National Semiconductor CorporationApparatus and method for reducing the power consumption of a microprocessor with multiple levels of cachesUS6457135Aug 10, 1999Sep 24, 2002Intel CorporationSystem and method for managing a plurality of processor performance statesUS6496915Dec 31, 1999Dec 17, 2002Ilife Solutions, Inc.Apparatus and method for reducing power consumption in an electronic data storage systemUS6501999Dec 22, 1999Dec 31, 2002Intel CorporationMulti-processor mobile computer system having one processor integrated with a chipsetUS6578129Jul 23, 1999Jun 10, 2003Imec VzwOptimized virtual memory management for dynamic data typesUS6594724Mar 30, 2000Jul 15, 2003Hitachi Global Storage Technologies Netherlands B.V.Enhanced DASD with smaller supplementary DASDUS6598148Jul 29, 1998Jul 22, 2003Patriot Scientific CorporationHigh performance microprocessor having variable speed system clockUS6628469Jul 11, 2000Sep 30, 2003International Business Machines CorporationApparatus and method for low power HDD storage architectureUS6631469Jul 17, 2000Oct 7, 2003Intel CorporationMethod and apparatus for periodic low power data exchangeUS6631474Dec 31, 1999Oct 7, 2003Intel CorporationSystem to coordinate switching between first and second processors and to coordinate cache coherency between first and second processors during switchingUS6639827Mar 12, 2002Oct 28, 2003Intel CorporationLow standby power using shadow storageUS6763480Dec 24, 2002Jul 13, 2004Sandisk CorporationFlash EEprom systemUS6775180Dec 23, 2002Aug 10, 2004Intel CorporationLow power state retentionUS6859856Oct 23, 2001Feb 22, 2005Flex P Industries Sdn. BhdMethod and system for a compact flash memory controllerUS6925529Jul 12, 2001Aug 2, 2005International Business Machines CorporationData storage on a multi-tiered disk systemUS6976180May 30, 2002Dec 13, 2005Dualcor Technologies, Inc.Personal electronics deviceUS6985778May 28, 2003Jan 10, 2006Samsung Electronics Co., Ltd.NAND flash memory interface deviceUS6986066Jan 5, 2001Jan 10, 2006International Business Machines CorporationComputer system having low energy consumptionUS7035442Jun 1, 2001Apr 25, 2006Secugen CorporationUser authenticating system and method using one-time fingerprint templateUS7069388Jul 10, 2003Jun 27, 2006Analog Devices, Inc.Cache memory data replacement strategyUS7082495Feb 21, 2003Jul 25, 2006Microsoft CorporationMethod and apparatus to reduce power consumption and improve read/write performance of hard disk drives using non-volatile memoryUS7184003Jan 13, 2003Feb 27, 2007Dualcor Technologies, Inc.Personal electronics device with display switchingUS7221331May 5, 2003May 22, 2007Microsoft CorporationMethod and system for auxiliary display of information for a computing deviceUS7231531Feb 28, 2003Jun 12, 2007Dualcor Technologies, Inc.Personal electronics device with a dual core processorUS7240228May 5, 2003Jul 3, 2007Microsoft CorporationMethod and system for standby auxiliary processing of information for a computing deviceUS7254730Feb 14, 2003Aug 7, 2007Intel CorporationMethod and apparatus for a user to interface with a mobile computing deviceUS20020129288Mar 8, 2001Sep 12, 2002Loh Weng WahComputing device having a low power secondary processor coupled to a keyboard controllerUS20030100963Nov 28, 2001May 29, 2003Potts John F. L.Personal information device on a mobile computing platformUS20030153354Jan 13, 2003Aug 14, 2003Cupps Bryan T.Novel personal electronics device with keypad applicationUS20050015562 *Jul 16, 2003Jan 20, 2005Microsoft CorporationBlock cache size management via virtual memory manager feedbackUS20050064911Jun 17, 2004Mar 24, 2005Vulcan Portals, Inc.User interface for a secondary display module of a mobile electronic deviceUS20050066209Jun 17, 2004Mar 24, 2005Kee Martin J.Portable electronic device having high and low power processors operable in a low power modeUS20060069848Sep 30, 2004Mar 30, 2006Nalawadi Rajeev KFlash emulation using hard diskUS20060075185Oct 6, 2004Apr 6, 2006Dell Products L.P.Method for caching data and power conservation in an information handling systemUS20060129861Feb 9, 2006Jun 15, 2006Kee Martin JPortable electronic device having high and low power processors operable in a low power modeUS20070028292Feb 20, 2004Feb 1, 2007Secure Systems LimitedBus bridge security system and method for computersUS20070055841Dec 16, 2003Mar 8, 2007Real Enterprise Solutions Development B.V.Memory allocation in a computer systemCN1550951AMay 8, 2004Dec 1, 2004微软公司Method and system for auxiliary processing of information for a computing deviceEP0666539A2Jan 13, 1995Aug 9, 1995International Business Machines CorporationCache control systemEP0702305A1Sep 12, 1995Mar 20, 1996Nec CorporationDisk memory apparatusEP1605453A2May 17, 2005Dec 14, 2005Marvell World Trade Ltd.Adaptive storage systemEP1605456A2May 17, 2005Dec 14, 2005Marvell World Trade Ltd.Hard disk drive power reduction moduleWO2001015161A1Aug 23, 2000Mar 1, 2001Seagate Technology LlcIntelligent power management of disc drivesWO2004090889A1Apr 5, 2004Oct 21, 2004Wilhelmus F J FontijnFormat mapping scheme for universal drive device* Cited by examinerNon-Patent CitationsReference1 *"How to increase virtual memory in XP", Mar. 25, 2002, Retrieved from: http://www.computing.net/answers/windows-xp/how-to-increase-virtual-memory-in-xp/20067.html on Aug. 3, 2009, [Online].22002 Silicon Storage Technology, Inc.; "ATA Flash Disk Controller" SST55LDo17A/SST55LD017B/SST55LD017C; Preliminary Specifications; 2002/52 pages.3Cast, Inc. (Jun. 2004) "NFlashCtrl NAND Flash Memory Controller Megafunction"; 2 pgs.4Cast, Inc., "NFlashCtrl NAND Flash Memory Controller Core"; http://222.cast-inc.com/cores/nflashcntl/index.shtml - Jul. 29, 2005; 3 pgs.5Cirrus Logic; Cl-SH7660 Preliminary Product Bulletin; "Advanced Architecture ATA Disk Controller"; Sep. 1998; 4 pgs.6Communication from EP dated Aug. 31, 2006 transmitting European search report for Application No. 05010673.1-2210; 3 pgs.7Communication from EPO dated Aug. 31, 2006 transmitting European search report for Application No. 05010671.5-2210; 3 pgs.8Communication from EPO dated Aug. 31, 2006 transmitting European search report for Application No. 05010672.3-2210; 3 pgs.9Communication from EPO dated Aug. 31, 2006 transmitting European search report for Application No. 05010676.4-2210; 3 pgs.10Communication from the European Patent Office dated Oct. 11, 2006 with the European Search Report for Application No. 05010993.3-1245; 3 pages.11Communication from the European Patent Office dated Oct. 6, 2006 with the partial European Search Report for Application No. 05010992.5-1245; 5 pages.12Communication from the European Patent Office dated Oct. 9, 2006 with the European Search Report for Application No. 05010994.1-1245; 3 pages.13Electronics Press World, "Power Digital Card (PDC) and Samsun Strikes Again As An Industry First to Release the 128MegaByte Reduced Size MultiediaCards," http://electronics.press-world.com/v/48895/power-digital-card-pdc-and-samsung-strikes-again-as-an-indust...; Jul. 7, 2003; 3 pgs.14Electronics Press World, "Power Digital Card (PDC) and Samsun Strikes Again As An Industry First to Release the 128MegaByte Reduced Size MultiediaCards," http://electronics.press-world.com/v/48895/power-digital-card-pdc-and-samsung-strikes-again-as-an-indust...; Jul. 7, 2003; 3 pgs.15First Official Communication from the European Patent Office dated May 22, 2007 for Application No. 05010673.1 - 1232; 4 pgs.16GD Technik Press Release; Flash Memory Module Thinks It's a Hard Disk; http//www.electronicstalk.com/news/gdt/gdt17.html; Apr. 25, 2005; 2 pgs.17Hachman, M., "Samsung: 'Hybrid' Hard Drives Will Ship in 2006," http://www.extremetech.com/article 2/0, 1558, 1789189,00.asp, Apr. 25, 2005; 2 pgs.18Hachman, M., "Samsung: �Hybrid� Hard Drives Will Ship in 2006," http://www.extremetech.com/article 2/0, 1558, 1789189,00.asp, Apr. 25, 2005; 2 pgs.19IEEE Std. 802.11a-1999; Supplement to IEEE Standard for Information Technology-Telecommunications and Information Exchange Between Systems - Local and Metropolitan (MAC) and Physical Layer (PHY) Specifications; High-speed Physical Layer in the 5 GHz Band; pp. 1-83.20IEEE Std. 802.11b; Supplement to IEEE Standard for Information Technology - Telecommunications and information exchange between systems - Local and metropolitan (MAC) and Physical Layer (PHY) specifications: Higher-Speed Physical Layer Extension in the 2.4GHz Band; Approved Sep. 16, 1999; pp. 1-89.21IEEE Std. 802.16; IEEE Standard for Local and metropolitan area networkds; Part 16: Air Interface for Fixed Broadband Wireless Access Systems; Apr. 8, 2001; pp. 1-322.22IEEE Std. 802.16a; IEEE Standard for Local and Metropolitan Area Networks; Part 16: Air Interface for Fixed Broadband Wireless Access Systems - Amendment 2: Medium Access Control Modifications and Additional Physical Layer Specifications for 2-11 GHz; Apr. 1, 2003; pp. 1-292.23MemoryClub.co.uk; "High Speed-MC"; Kingmax HS-MMC 512 mb; http://www.websetters.co.uk/MemoryClub/HSMMC.htm; 1 pg, 2006.24Mittoni; "CompactFlash Controller"; http://www.mittoni.com/compacfflash/article5.html; 2 pgs. 2005.25Mittoni; "CompactFlash Memory Cards"; http://www.mittoni.com/compactflash/compactflash.html, 2 pgs, 2005.26Optics Planet, Inc. "Silicon Power SD/MMC Card Reader": http://222.opticsplanet.net/silicon-power-sd-mmc-card-reader.html; 2003.27Pretec Electronics Corp.; Mini IDE (MIDE) Flash Drive; http://www.pretec.com/product/SSD/industrial/miniide.htm; 2005; 4 pgs.28Takahashi, Dean: "PortalPlayer Takes a Leap", The Mercury News, Mar. 14, 2006, 3 pgs.29U.S. Appl. No. 10/779,544, filed Feb. 13, 2004; "Computer With Low-Power Secondary Processor and Secondary Display"; Sehat Sutardja.30U.S. Appl. No. 10/865,368, filed Jun. 10, 2004; "Adaptive Storage System"; Sehat Sutardja.31U.S. Appl. No. 60/678,249, filed May 2005, Yang.32U.S. Appl. No. 60/799,151, filed May 2006, Sutardja et al.33U.S. Appl. No. 60/820,867, filed Jul. 2006, Sutardja et al.34U.S. Appl. No. 60/822,015, filed Aug. 2006, Sutardja et al.35U.S. Appl. No. 60/823,453, filed Aug. 2006, Sutardja et al.36U.S. Appl. No. 60/825,368, filed Sep. 2006, Sutardja et al.37U.S. Appl. No. 60/890,684, filed Feb. 2007, Sutardja et al.38Wikipedia; "Flash Memory"; http://en.wikipedia.org/wiki/Flash-memory; 3 pgs.; 2006.39Wikipedia; "Flash Memory"; http://en.wikipedia.org/wiki/Flash�memory; 3 pgs.; 2006.40Wikipedia; CompactFlash; http://web.archive.org/web/2006010900303/http://en.wikipedia.org/wiki/CompactFlash-II; Jan. 9, 2006; 4 pgs.41Wikipedia; CompactFlash; http://web.archive.org/web/2006010900303/http://en.wikipedia.org/wiki/CompactFlash�II; Jan. 9, 2006; 4 pgs.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8250648 *Mar 29, 2004Aug 21, 2012Secure Systems LimitedSecurity system and method for computer operating systemsUS20080104348 *Mar 29, 2004May 1, 2008Richard KabzinskiSecurity System And Method For Computer Operating Systems* Cited by examinerClassifications U.S. Classification713/320, 713/300International ClassificationG06F12/08, G06F1/32Cooperative ClassificationG06F12/0897, Y02B60/1225, G06F12/0866, G06F2212/222, G06F13/28, G06F12/08, G06F1/3203, G06F1/3293, G06F1/3275European ClassificationG06F1/32P5P8, G06F1/32P, G06F12/08B12, G06F12/08, G06F12/08B22LLegal EventsDateCodeEventDescriptionFeb 28, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google