Source: http://www.patentgenius.com/patent/6900463.html
Timestamp: 2018-03-23 05:27:03
Document Index: 458421065

Matched Legal Cases: ['application No. 09', 'application No. 09', 'Application No. 88974', 'Application No. 88974', 'Application No. 88974', 'Application No. 55', 'application No. 06', 'Application No. 55', 'application No. 06']

Semiconductor device - Patent # 6900463 - PatentGenius
6900463 Semiconductor device
Application: 08/104,264
U.S. Class: 257/57; 257/66; 257/72; 257/E21.101; 257/E27.125; 257/E29.003; 257/E29.082; 257/E29.084; 257/E29.1; 257/E29.104; 257/E29.277; 257/E29.288; 257/E29.29; 257/E29.297
Field Of Search: 357/2; 357/4
U.S Patent Documents: 2280840; 2820841; 3151379; 3191061; 3271632; 3339128; 3585088; 3644741; 3650737; 3716844; 3771026; 3787823; 3801966; 3846767; 3886577; 3988720; 3999212; 4055884; 4062034; 4113531; 4117506; 4160260; 4179528; 4217374; 4224084; 4225222; 4226898; 4239554; 4240843; 4253882; 4254429; 4265991; 4267011; 4270018; 4272880; 4289822; 4317844; 4329699; 4339285; 4390791; 4398343; 4400409; 4470667; 4485389; 4498092; 4581620; 4605941; 4761058; 5091334
Foreign Patent Documents: 51-112188; 54-18886; 54-37697; 54-37698; 54-92022; 54-108595; 54-152894; 54152894; 53-83467; 53-83468; 53-86867; 53-86868; 55-11329; 5511329; 55-11330; 5511330; 55-13938; 5513938; 55-13939; 5513939; 55-050663; 55-050664; 56-43678; 56135968; 6059594
Other References: Notice of Motion and SEL's Motion for Partial Summary Judgment on Defenses of Defendants; Memorandum of Points and Authorities (RedactedVersion), Jul. 9, 2003..
Declaration of Stanley A. Schlitter (Schlitter Declaration) in Support of SEL's Two Motions for Partial Summary Judgment (Redacted Version), with Exhibits, Jul. 9, 2003..
Exhibit 3 of Schlitter Declaration, Copy of AU Optronics' Answer to SEL's First Amended Complaint and Counterclaims..
Exhibit 4 of Schlitter Declaration, Copy of U.S. Patent No. 6,355,941 ("the '941 Patent")..
Exhibit 5 of Schlitter Declaration, Copy of Expert Witness Report of Richard A. Killworth..
Exhibit 7 of Schlitter Declaration, Copy of U.S. Patent 6,404,480 ("the '480 Patent")..
Exhibit 8 of Schlitter Declaration, Copy of Manual of Patent Examining Procedure (MPEP), .sctn. 1302.12..
Exhibit 9 of Schlitter Declaration, Copy of the May 28, 1998 IDS Form from the '941 Patent Application..
Exhibit 10 of Schlitter Declaration, Copy of the Specification and Claims for application Ser. No. 08/104,264 ("the '264 Application")..
Exhibit 11 of Schlitter Declaration, Copy of the Jan. 14, 1999 Office Action from the '264 Application..
Exhibit 12 of Schlitter Declaration, Copy of the Apr. 2, 1998 Office Action from the '941 Patent Application..
Exhibit 13 of Schlitter Declaration, Copy of the Apr. 17, 1998 Notice of Appeal from the '941 Patent Application..
Exhibit 14 of Schlitter Declaration, Copy of the Jun. 25, 1999 Order Remanding to Examiner from the '941 Patent Application..
Exhibit 15 of Schlitter Declaration, Copy of the May 28, 1998 IDS Form, Signed and Dated by the Examiner (With Lines Drawn Through the References), from the '941 Patent Application..
Exhibit 16 of Schlitter Declaration, Copy of the May 28, 1998 IDS Form, Signed and Dated by the Examiner (Without Lines Drawn Through References), from the '941 Patent Application..
Exhibit 17 of Schlitter Declaration, Copy of the May 23, 2001 Board of Patent Appeals' Decision on Appeal from the '941 Patent Application..
Exhibit 18 of Schlitter Declaration, Copy of the Sep. 10, 2001 Notice of Allowability from the '941 Patent Application..
Exhibit 19 of Schlitter Declaration, Copy of MPEG .sctn. 1214.04..
Exhibit 20 of Schlitter Declaration, Copy of the Deposition Transcript of Richard A. Killworth..
Exhibit 21 of Schlitter Declaration, Copy of the Specification and Claims of application Ser. No. 06/278,418 ("the '418 Application ")..
Ehibit 22 of Schlitter Declaration, Copy of U.S. Patent No. 5,929,527l ("the '527 Patent")..
Exhibit 23 of Schlitter Declaration, Copy of SEL's Original Complaint for Patent Infringement dated Jun. 11, 2002..
Exhibit 24 of Schlitter Declaration, Copy of the April 28, 1998 Amendment from the '264 Application (Filed Under Seal, Copy Not Provided)..
Exhibit 25 of Schlitter Declaration, Copy of Selections from the '941 Patent Application File History..
Exhibit 26 of Schlitter Declaration, Copy of U.S. Patent No. 5,591,987 ("the '987 Patent")..
Exhibit 27 of Schlitter Declaration, Copy of U.S. Patent No. 5,262,350 ("the '350 Patent")..
Exhibit 28 of Schlitter Decelartion, Copy of Selections from the File Histories of the '418, '767, '705, '102, '167, and '548 Patent Applications..
Exhibit 44 of Schlitter Declaration, Copy of U.S. Patent No. 5,859,443..
Exhibit 45 of Schlitter Declaration, Copy of the Deposition Transcript of Shumpei (sic) Yamazaki [Redacted Version, pp. 2-43, 63-65, and 69-111]..
Exhibit 46 of Schlitter Declaration, Copy of U.S. patent application No. 09/046,685, which Issued as the '471 Patent and which was the Parent Application to the one that Issued as the '480 Patent..
Exhibit 47 of Schlitter Declaration, Copy of a Request for Drawings Made by Counsel for SEL to Quinn Patent Drawing Service and the Resulting Drawings from the '471 Patent Applications..
Exhibit 48 of Schlitter Declaration, Copy of U.S. patent application No. 09/734,177, which Led to the Issuance of the '480 Patent..
Exhibit 49 of Schlitter Declaration, Copy of a Verified Translation of a Japanese Priority Document from the '480 Patent Application..
Exhibit 51 of Schlitter Declaration, Copy of Exhibit 3 from the Deposition of Shumpei (sic) Yamazaki..
AU Optronics Corporation's and Acer and Acer America's Opposition to SEL's Motion for Partial Summary Judgment on Defenses of Defendant; Memorandum of Points and Authorities in Support Thereof, Jul. 24, 2003..
Declaration of Minda R. Schechter (Schechter Declaration) in Support of AU Optronics Corporation's and Acer and Acer America's Opposition to SEL's Motion for Partial Summary Judgment on Defenses of Defendants, with Exhibits, Jul. 24, 2003..
Exhibit 1 of Schechter Declaration, Copy of Pages from the PTO Website..
Exhibit 2 of Schechter Declartion, Copy of Pages from the PTO website..
Exhibit 3 of Schechter Declaration, Copy of Semiconductor Energy Laboratory Co., Ltd., v. Samsung Electronics Co. Ltd., 204 F.3d 1368(Fed. Cir. 2000)..
Exhibit 4 of Schechter Declaration, Copy of U.S. Patent No. 6,355,941 ( the '941 Patent)..
Exhibit 5 of Schechter Declaration, Copy of Semiconductor Energy Laboratory Co., Ltd. v. Samsung Electronics Co. Ltd., 4 F.Supp. 2d 477 (E.D. Va. 1998)..
Exhibit 6 of Schechter Declaration, Copy of Amendment and Information Disclosure Statement, Dated Aug. 8, 1996, from '941 Certified File Wrapper..
Exhibit 7 of Schechter Declaration, Copy of Submission of Declaration, Dated Apr. 24, 1997, from '941 Certified File Wrapper..
Exhibit 8 of Schechter Declaration, Copy of Appeal Brief, Dated Apr. 20, 1998, from '941 Certified File Wrapper..
Exhibit 9 of Schechter Declaration, Copy of an English Translation of Japanese Application Patent No. 55-050663, Filed Oct. 7, 1978..
Exhibit 10 of Schechter Declaration, Copy of an English Translation of Japanese Application Patent No. 55-050664, Filed Oct. 7, 1978..
Exhibit 11 of Schechter Declaration, Copy of Expert Witness Report of Richard A. Killworth, Dated May 22, 2003..
Exhibit 12 of Schechter Declaration, Copy of Order Remanding to Examiner in Appeal No. 99-1466; application 08/371,486, Mailed Jun. 25, 1999 in '941 Certified File Wrapper..
Exhibit 13 of Schechter Declaration, Copy of PTO Office Communication Dated Jul. 16, 1999 in '941 Certified File Wrapper..
Exhibit 14 of Schechter Declaration, Copy of the Information Disclosure Statement Dated May 28, 1998 in '941 Certified File Wrapper..
Exhibit 15 of Schechter Declaration, Copy of pp, 76-83 [sic, and pp. 1, 2 and 110] and Exhibits 3 and 4 to the Deposition Transcript of Shumpei (sic) Yamazaki, Taken Apr. 30, 2003..
Exhibit 16 of Schechter Declaration, Copy of Amendment Dated Aug. 29, 1985 in '941 Certified File Wrapper..
Exhibit 17 of Schechter Declaration, Copy of an Advisory Action Dated Sep. 13, 1985 in '941 Certified File Wrapper..
Exhibit 18 of Schechter Declaration, Copy of Amendment Dated Sep. 12, 1985 in '941 Certified File Wrapper..
Exhibit 19 of Schechter Declaration, Copy of Amendment Dated Apr. 22, 1994 in '941 Certified File Wrapper..
Exhibit 20 of Schechter Declaration, Copy of the "Contents" Sheet from the '941 Certified File Wrapper..
Exhibit 21 of Schechter Declaration, Copy of an English Translation of Japanese Patent Application No. 88974/80..
Exhibit 22 of Schechter Declaration, Copy of the First Request for Production of Documents and Things from Acer, Inc., Acer America Corp., and AU Optronics Corp. to Semiconductor Energy Laboratory Co., Ltd. Dated Dec. 5, 2002..
Expert Witness Report of Robert A. Street of May 22, 2003..
Exhibit 1 of Expert Witness Report of Robert A. Street, U.S. Patent No. 6,355,941 entitled "Semiconductor Device," to Yamazaki, et al..
Exhibit 2 of Expert Witness Report of Robert A. Street, File History of U.S. Patent No. 6,355,941..
Exhibit 3 of Expert Witness Report of Robert A. Street, Translation of Osamu Osada of certified copy of Japanese Patent Application No. 88974/80, paper #8 from application Ser. No. 06/278,418..
Exhibit 4 of Expert Witness Report of Robert A. Street, Certified copy of Japanese Patent Application No. 88974/80, paper #9 from application Ser. No. 06/278,418..
Exhibit 5 of Expert Witness Report of Robert A. Street, U.S. Patent No. 4,470,667 entitled, "Display Process and Apparatus Thereof Incorporating Overlapping of Color Filters," to Okubo, et al..
Exhibit 6 of Expert Witness Report of Robert A. Street, J. Snell, et al., "Application of Amorphous Silicon Field Effect Transistors in Addressable Liquid Crystal Display Panels," Appl. Phys. 24, pp. 357-362, 1981..
Exhibit 7 of Expert Witness Report of Robert A. Street, M.J. Powell, et al., "Amorphous Silicon-Silicon Nitride Thin-Film Transistors," Appl. Phys. Lett. 38 (10), May 15, 1981..
Exhibit 8 of Expert Witness Report of Robert A. Street, M. Matsumura, et al., "Amorphous-Silicon Image Sensor IC," IEEE Electron Device Letters, vol. EDL-1, No. 9, pp. 182-184, Sep. 1980..
Exhibit 9 of Expert Witness Report of Robert A. Street, Masakiyo Matsumura, et al., "Amorphous-Silicon Integrated Circuit," Proceedings of the IEEE, vol. 68, No. 10, pp. 1349-1351, Oct. 1980..
Exhibit 10 of Expert Witness Report of Robert A. Street, T. I. Kamins, et al., "A Monolithic Integrated Circuit Fabricated in Laser-Annealed Polysilicon," IEEE Transactions on Electron Devices, vol. ED-27, No. 1, Jan. 1980..
Exhibit 11 of Expert Witness Report of Robert A. Street, Madan, et al., "Investigation of the Density of Localized States in a-Si Using the Field Effect Technique," Journal of Non-Crystalline Solids, vol. 20, pp. 239-257, 1976..
Exhibit 12 of Expert Witness Report of Robert A. Street, P.G. Le Comber, et al., "Amorphous-Silicon Field-Effect Device and Possible Application," Electronic Letters, vol. 15, No. 6, pp. 179-181 Mar. 15, 1979..
Exhibit 13 of Expert Witness Report of Robert A. Street, M. Hirose, et al., "Electronic Density of States in Discharge-Produced Amorphous Silicon," Appl. Phys. Lett. vol. 34, No. 3, pp. 234-236, Feb. 1, 1979..
Exhibit 14 of Expert Witness Report of Robert A. Street, Masataka Hirose, et al., "Determination of Localized State Density Distribution in Glow Discharge Amorphous Silicon," Proceedings of the 10.sup.th Conference on Solid State Devices; JapaneseJournal of Applied Physics, vol. 18, Supplement 18-1, pp. 109-113, 1979..
Exhibit 15 of Expert Witness Report of Robert A. Street, Hiroshi Hayama, et al., "Amorphous-Silicon Thin-Film Metal-Oxide-Semiconductor Transistors," Appl. Phys. Lett., 36(9), pp. 754-755, May 1, 1980..
Exhibit 16 of Expert Witness Report of Robert A. Street, Matsumura, et al., "a-Si p-channel FET," Partial Translation of National Convention Record, The Institute of Electronics and Communication Engineers of Japan, pp. 2, 281-282, Mar. 1980..
Exhibit 17 of Expert Witness Report of Robert A. Street, Japanese Laid Open No. 55-050663--Inventor: Shunpei Yamazaki..
Exhibit 18 of Expert Witness Report of Robert A. Street, Japanese Laid Open No. 55-050664--Inventor: Shunpei Yamazaki..
Exhibit 19 of Expert Witness Report of Robert A Street, Japanese Laid Open No. 54-152894--Inventor: Tsutomu Otake, et al..
Exhibit 20 of Expert Witness Report of Robert A. Street, Takashi Ito, et al., "Thermally Grown Silicon Nitride Films for High-Performance MNS Device," Appl. Phys. Lett., 32(5), pp. 330-331, Mar. 1, 1978..
Exhibit 21 of Expert Witness Report of Robert A. Street, Masakiyo Matsumura, "Amorphous Silicon Thin-Film Electron Devices," Applied Physics, vol. 49, No. 7, pp. 729-732, 1980..
Exhibit 22 of Expert Witness Report of Robert A. Street, Hiroshi Hayama, et al., "Amorphous Silicon Thin-Film MOS Transistors," Transactions of the Institute of Electronics and Communication Engineers of Japan, vol. J63-C, No. 2, pp. 128-129, Feb.1980..
Exhibit 23 of Expert Witness Report of Robert A. Street, Hiroshi Hayama, et al., "a-Si FET IC Integrated on a Glass Substrate," English Translation of National Convention Record, The Institute of Electronics and Communication Engineers of Japan, pp.287-0288..
Exhibit 24 of Expert Witness Report of Robert A. Street, Paul K. Weimer, "The Insulated-Gate Thin-Film Transistor," RCA Laboratories, Princeton, New Jersey, pp. 147-192..
Exhibit 25 of Expert Witness Report of Robert A. Street, Paul K. Weimer, "The TFT-A New Thin-Film Transistor," Proceedings of the IRE, pp. 1462-1469, Jun. 1962..
Exhibit 26 of Expert Witness Report of Robert A. Street, W.E. Spear, et al., "Investigation of the Localised State Distribution in Amorphous Si Films," Journal of Non-Crystalline Solids, 8-20, 00. 727-738, 1972..
Exhibit 27 of Expert Witness Report of Robert A. Street, Akihisa Matsuda, et al., "Electrical and Structural Properties of Phosphorous-Doped Glow-Discharge Si:F:H and Si:H Films," Japanese Journal of Applied Physics, vol. 19, No. 6, pp. L305-308,Jun. 1980..
Exhibit 28 of Expert Witness Report of Robert A. Street, S. M. Sze, "Physics of Semiconductor Devices," pp. xi-xiv, 505-624, 1969..
Exhibit 29 of Expert Witness Report of Robert A. Street, John C. Knights, "Characterization of Plasma-Deposited Amorphous Si:H Thin Films," Japanese Journal of Applied Physics, vol. 18, pp. 01-108, Sep. 1979..
Expert Report of Lloyd L. Zickert in Opposition to Expert Report of Richard A. Killworth, dated Jun. 6, 2003..
Exhibit 1 of Expert Witness Report of Lloyd L. Zickert, Partial Translation of Yamazaki Deposition Exhibit 9..
Exhibit 2 of Expert Witness Report of Lloyd L. Zickert, Yamazaki Deposition Exhibit 9..
Exhibit 3 of Expert Witness Report of Lloyd L. Zickert, '941 Patent..
Exhibit 4 of Expert Witness Report of Lloyd L. Zickert, Yamazaki Deposition Transcript, pp. 79-80 and 88-89 and 150 [and additional pages included in 78-81, 86-89, and 150-153 as attached to the report]..
Exhibit 5 of Expert Witness Report of Lloyd L. Zickert, Form 1449 Executed By Examiner of '941 Patent..
Exhibit 6 of Expert Witness Report of Lloyd L. Zickert, Form 1449 Executed By Examiner of '941 Patent..
Exhibit 7 of Expert Witness Report of Lloyd L. Zickert, Examiner's Communication to Board..
Exhibit 8 of Expert Witness Report of Lloyd L. Zickert, Form 1449 Submitted by Applicants in the '264 Application..
Exhibit 9 of Expert Witness Report of Lloyd L. Zickert, Amendment in the '264 Application..
Exhibit 10 of Expert Witness Report of Lloyd L. Zickert, Office Action of Examiner of '264 Application..
Exhibit 11 of Expert Witness Report of Lloyd L. Zickert, JP 55-050664 ('664 application) and 55-050663 ('663 application) Japanese References and Translations..
Exhibit 12 of Expert Witness Report of Lloyd L. Zickert, Appeal Brief in the '941 Patent..
Exhibit 13 of Expert Witness Report of Lloyd L. Zickert, Robinson Deposition Transcript, p. 97 [and additional pages included in 94-97 as attached to the report]..
Exhibit 14 of Expert Witness Report of Lloyd L. Zickert, Partial Translation of Matsumura Reference. [a-Si p-channel FET, pp. 2, 281-282, Mar. 1980]..
Exhibit 15 of Expert Witness Report of Lloyd L. Zickert, Full Translation of Matsumura Reference. [a-Si p-channel FET, pp. 2, 281-182, Mar. 1980]..
Exhibit 19 of Expert Witness Report of Lloyd L. Zickert, Powell Reference [Amorphous silicon--silicon nitride thin-film transistors, May 15, 1981]..
Exhibit 20 of Expert Witness Report of Lloyd L. Zickert, Snell Reference. [Application of Amorphous Silicon Field Effect Transistors in Addressable Liquid Crystal Display Panels, Applied Physics, 1981]..
Exhibit 21 of Expert Witness Report of Lloyd L. Zickert, Matsumura Reference. [Amorphous-Silicon Integrated Circuit, Proceedings of the IEEE, vol. 68, No. 10, Oct. 1980]..
Exhibit 22 of Expert Witness Report of Lloyd L. Zickert, Matsumura Reference. [Amorphous-Silicon Image Sensor IC, IEEE Electron Device Letters, vol. EDL-1, No. 9, Sep. 1980]..
Exhibit 23 of Expert Witness Report of Lloyd L. Zickert, '941 Priority Document and Translation. [JP Application 55-88974]..
*Electronics Letters 15th Mar. 1979, vol. 15, No. 6, pp 179-181..
IEEE Transactions on Electron Devices, vol. Ed-20, No. 11, Nov. 1973, pp 995-1001..
*Matsuda et al., "Electrical and Structural Properties of Phosphorus--Doped Glow-Discharge Sj:F:H and Si:H Films", Japanese Journal of Applied Physics, vol. 19, No. 6, Jun., 1980, pp. L305-L308..
Applied Physics Letter, pp 754-755, May 1980..
The Japan Society of Applied Physics, vol. 49, No. 7, pp 729(81)-732(84), Jul. 10, 1980, Matsumura..
* National Convention Record, The Institute of Electronics and communications Engineers of Japan, pp 2-287-287, Mar. 1980..
Electronics Letters, vol. 15, No. 14, pp 435-437, Jul. 1979..
Philosophical Magazine, 1976, vol. 33, No. 6, 935-949 "Electronic Properties of Substantially Doped Amorphous Si and Ge", W.E. Spear et al., 1976..
Physics of Semiconductor Devices, pp. 568-621, S.M. Sze, 1969..
Applied Physics Letters, vol. 34, pp 234-236, "Electronic Density of States in Discharge-Produced Amorphous Silicon", M. Hirose et al., Feb. 1, 1979..
*Extended Abstracts (The 40th Autumn Meeting) The Japan Society of Applied Physics, p. 325, 30P-S-17, Nakamura et al., 9/79..
Proceedings of the 10th Conference on Solid State Devices, JAP, vol. 18, p 109-113, "Determination of Localized State Density Distribution in Glow Discharge Amorphous Silicon", Hirose et al., 1979..
Extended Abstracts (The 40th Autumn Meeting) The Japan Society of Applied Physics, p. 326, 30P-S-18, Matsumura et al., 1979 (including partial translation)..
A Journal of Theoretical Experimental and Applied Physics, "Localized States in the Mobility Gap of Amorphous Quartz and Glass", p. 839-851, Anderson, 1974..
Physics of Semiconductor Devices, p. 32, S.M. Sze, 1981..
*National Convention Record, The Institute of Electronics and Communication Engineers of Japan, 2- 281-282, Matsumura et al., 3/80, (including partial translation)..
Proc. 7th Intern. Vac. Congr. & 34d Intern. Conf. Solid Surfaces, "Preparation and Reliability of Thin Film Transistors Based on CdSe", M.J. Lee, 1979..
Solid State Communications, vol. 17, No. 9, pp. 1193-1196, "Substitutional Doping of Amorphous Silicon", Speal et al., 1975..
*National Convention Record, The Institute of Electronics and Communication Engineers of Japan, 2- 287-288 Matsumura et al., 3/80 (including partial translation)..
The Transactions of The Institute of Electronics and Communication Engineers of Japan, vol. 363-C No. 2 pp. 128-129, "Amorphous Silicon Thin Film MOS Transistors", Matsumura et al., 2/80 (including partial translation)..
National Convention Record, The Institute of Electronics and Communication Engineers of Japan, 2-285-286, Matsumura et al., 3/80 (including partial translation)..
Extended Abstracts (The 26th Spring Meeting) The Japan Society of Applied Physics and Related Societies, p. 326, Matsumura et al., 3/79..
Optoelectronics, vol. 4, No. 2, pp 209-222, Active Matrix Addressed Liquid Crystal Displays Using Amorphous Silicon Thin Film Transistors, Ibaraki et al., 12/89..
Journal of Non Crystalline Solids 8-10, 727-738, "Investigation of the Localized State Distribution in Amorphous Si Films", Spear et al.,v 1972..
Electronics Letters, vol. 15, No. 6, 179-181, Amorphous-Silicon Field-Effect Device and Possible Application, Le Comber, 3/79..
Extended Abstracts (The 26th Spring Meeting) The Japan Society of Applied Physics and Related Societies, p. 143, 27P-E-15, Suzuki et al., 1978 (including partial translation)..
IBM Technical Bulletin, vol. 9, No. 5, Oct. 1966, W.R. Beam, Charge-Storage Beam-Addressable Memory, pp. 555-556..
Solid-State Electronics, vol. 15, 1972, pp 789-799..
Acer Incorporated and Acer America Corporation's Reply in Support of its Motion for Summary Judgment of Unenforceability of U.S. Patent No. 6,355,941, Jul. 30, 2003..
SEL's Reply in Support of its Motion for Partial Summary Judgment on Defenses of Defendants, Jul. 30, 2003..
Supplemented Final Invalidity Contentions of AU Optronics Corporation Pursuant to Patent L.R. 3-6(b)(1)..
Notice of Motion and Motion of Au Optronics Corporation for Partial Summary Judgment that U.S. Patent No. 6,355,941 is not Entitled to the Filing Date of JP 55-88974 and is Not Entitled to the Filing Date of U.S. patent application Ser. No.06/237,609, Jul. 9, 2003..
Declaration of Manuel Nelson (Nelson Declaration) in Support of AU Optronics Corporation's Motion for Partial Summary Judgment that U.S. Patent No. 6,355,941 is Not Entitled to the Filing Date of JP 55-88974 and is Not Entitled to the Filing Date ofU.S. patent application Ser. No. 06/237,608, with Exhibits, Jul. 9, 2003..
Exhibit 1 of Nelson Declaration, Plaintiff SEL's Objections and Responses to Defendant AU Optronics Corporations's First Set of Interrogatories Nos. 1-13 and Document Request No. 67..
Exhibit 2 of Nelson Declaration, SEL's Disclosure of Asserted Claims and Preliminary Infringement Contentions..
Exhibit 3 of Nelson Declaration, Copy of Application Paper filed Jun. 29, 1981 During Prosecution of U.S. patent application Ser. No. 06/278,418..
Exhibit 4 of Nelson Declaration, Paper No. 30, Request for File Wrapper Continuing Application Under 37 CFR 1.62, Filed Jan. 11, 1995 During Prosecution of U.S. patent application Ser. No. 08/371,486..
Exhibit 5 of Nelson Declaration, U.S. Patent No. 6,355,941 to Yamazaki et al. Issued Mar. 12, 2002..
Exhibit 6 of Nelson Declaration, Final Claim-Construction Order for United States Patent Nos. 5,929,527; 6,355,941; 6,404,476, and 6,404,480..
Exhibit 7 of Nelson Declaration, Paper No. 8, Certified Translation of JP 55-55974 [sic, 55-88974]("Transl. JP 55-88974"), Filed May 30, 1984, During Prosecution of U.S. patent application Ser. No. 06/278,418..
Exhibit 8 of Nelson Declaration, Paper No. 9, Certified Copy of Japanese Patent Application No. 55-88974 ("JP 55-55974" [sic--"JP 55-88974"]), Filed May 30, 1984 During Prosecution of U.S. patent application Ser. No. 06/278,418..
Exhibit 9 of Nelson Declaration, Copy of U.S. patent application No. 06/237,609 (the '609 application)..
AU Optronics' Reply to SEL's Opposition to AU Optronics Corporation's Motion for Partial Summary Judgment that U.S. Patent No. 6,355,941 is Not Entitled to the Filing Date of JP 55-88974 and is Not Entitled to the Filing Date of U.S. patentapplication Ser. No. 06/237,609, Jul. 30, 2003..
Declaration of Manuel Nelson (Nelson Declaration) in Support of AU Optronics' Reply to SEL's Opposition to AU Optronics Corporation's Motion for Partial Summary Judgment that U.S. Patent No. 6,355,941 is Not Entitled to the Filing Date of JP55-88974 and is Not Entitled to the Filing Date of U.S. patent application Ser. No. 06/237,609, Jul. 30, 2003..
Exhibit 1 of Nelson Declaration, Expert Witness Report of Robert A. Street..
Exhibit 2 of Nelson Declaration, Expert Report of Lloyd L. Zickert in Opposition to Expert Report of Richard A. Killworth..
Exhibit 3 of Nelson Declaration, Expert Witness Report of L. Rafael Reif, Ph.D..
Exhibit 4 of Nelson Declaration, Oppsition Report of L. Rafael Reif, Ph.D..
Exhibit 5 of Nelson Declaration, Rebuttal Report of L. Rafael Reif, Ph.D..
Acer Incorporated and Acer America Corporation's Motion for Summary Judgment of Unenforceability of U.S. Patent No. 6,355,941, Jul. 9, 2003..
Declaration of Peter J. Wied (Wied Declaration) in Support of Acer Incorporated and Acer America Corporation's Motion for Summary Judgment of Unenforceability of U.S. Patent No. 6,355,941, with Exhibits, Jul. 9, 2003..
Exhibit A of Wied Declaration, Copy of a Portion of the File History of U.S. Patent No. 5,543,636, Titled Information Disclosure Statement and Dated Nov. 15, 1995..
Exhibit B of Wied Declaration, Copy of a Portion of the File History of U.S. Patent No. 5,543,636, Titled Partial Translation of JP Laid-Open 56-135968..
Exhibit C of Wied Declaration, Copy of a Portion of the File History of U.S. Patent No. 6,355,941, Titled Supplemental Information Disclosure Statement, Bearing Bates Nos. SEL 59245-59254..
Exhibit D of Wied Declaration, Copy of a Portion of the File History of U.S. Patent No. 6,355,941, Titled Supplemental Information Disclosure Statement and Response, Bearing Bates Nos. SEL 59520-59524..
Exhibit E of Wied Declaration, Copy of Documents Produced by SEL in this Case, Bearing Bates Nos. SEL 67909-67920..
Exhibit F of Wied Declaration, Copy of a Portion of the Deposition Transcript of Shumpei (sic) Yamazaki on May 2, 2003 [pp. 201, 236, 243, 256, and 257]..
Exhibit G of Wied Declaration, Copy of a Portion of the File History of U.S. Patent No. 6,355,941, Titled Amendment and Information Disclosure Statement, Bearing Bates Nos. SEL 59227-59243..
Exhibit H of Wied Declaration, Copy of U.S. Patent No. 6,355,941, Bearing Bates Nos. SEL 60023-60045..
Exhibit I of Wied Declaration, Copy of a Portion of the File History of U.S. Patent No. 6,355,941, Bearing Bates Nos. SEL 59530-59533..
Exhibit J of Wied Declaration, Copy of a Portion of the File History of U.S. Patent No. 6,355,941, Bearing Bates Nos. SEL 58863-58869..
Exhibit K of Wied Declaration, Copy of a Portion of the Deposition Transcript of Eric Robinson on May 14, 2003 [pp. 1, 90, 91, 100, and 100 (second occurrence)]..
Exhibit L of Wied Declaration, Copy of the Decision of the Court in Semiconductor Energy Laboratory Co., Ltd. v. Samsung Electronics Co., Ltd., Reported at 4F. Supp. 2d 477..
Exhibit M of Wied Declaration, Copy of a Portion of the File History of U.S. Patent No. 6,355,941, Titled Information Disclosure Statement, Bearing Bates Nos. SEL 59831-59834..
Exhibit N of Wied Declaration, Copy of a Portion of the File History of U.S. Patent No. 6,355,941, Titled Amendment, Bearing Bates Nos. SEL 59679-59700..
Exhibit O of Wied Declaration, Copy of the Decision of the Court in Semiconductor Energy Laboratory Co., Ltd. v. Samsung Electronics Co., Ltd. Dated Mar. 2, 2000..
Exhibit P of Wied Declaration, Copy of a Letter From Terrence J. Truax Dated May 3, 2003..
Exhibit Q of Wied Declaration, Copy of a Translation of Japanese Patent Laid-Open No. 56-135968 labeled SEL Trial Exhibit No. 429.2 SEL v. Samsung, CA No. 96-1460-A..
Exhibit R of Wied Declaration, Copy of U.S. Patent No. 5,543,636..
SEL's Opposition to Acer's Motion for Summary Judgment of Unenforceability of U.S. Patent No. 6,355,941, Jul. 23, 2003..
Declaration of Donald R. Harris (Harris Declaration) in Support of SEL's Opposition to the Five Summary Judgment Motions of AU and Acer (Redacted Version), Jul. 23, 2003..
Exhibit 5 of Harris Declaration, Copy of the Answers Filed by the Acer Defendants on Sep. 24, 2002..
Exhibit 6 of Harris Declaration, Copy of Court's Case Management Order..
Exhibit 7 of Harris Declaration, Copy of U.S. Patent No. 5,543,636..
Exhibit 8 of Harris Declaration, Copy of U.S. Patent 6,355,941..
Exhibit 9 of Harris Declaration, Copy of the Apr. 24, 1997 Response to Office Action from the '941 Patent Prosecution History..
SEL's Opposition to AU's Motion for Partial Summary Judgment that U.S. Patent No. 6,355,941 is Not Entitled to the Filing Date of JP 55-88974 and is Not Entitled to the Filing Date of U.S. patent application Ser. No. 06/237,609, Jul. 23, 2003..
Declaration of L. Rafael Reif in Support of SEL's Opposition to AU's Motion for Partial Summary Judgment that U.S. Patent No. 6,355,941 is Not Entitled to the Filing Date of JP 55-88974 and is Not Entitled to the Filing Date of U.S. patentapplication Ser. No. 06/237,609, Jul. 18, 2003..
Declaration of Donald R. Harris (Harris Declaration) in Support of SEL's Oppositions to the Five Summary Judgment Motions of AU and Acer (Redacted Version), Jul. 23, 2003..
Exhibit 8 of Harris Declaration, U.S. Patent 6,355,941 to Yamazaki et al., Issued Mar. 12, 2002..
Exhibit 18 of Harris Declaration, Copy of English Translation of Japanese Patent Application No. 55-88974, Which is Found in the Prosecution History of U.S. Patent 4,581,620..
Exhibit 19 of Harris Declaration, Copy of U.,S. patent application No. 06-278418..
Exhibit 20 of Harris Declaration, Amendment Filed on May 30, 1984, Which is Found in the Prosecution History of U.S. Patent No. 4,581,620..
Exhibit 21 of Harris Declaration, Examiner's Action Dated Jul. 9, 1984, Which is Found in the Prosecution History of U.S. Patent No. 4,581,620..
Exhibit 22 of Harris Declaration, Court's Final Claim Construction Order..
Opposition Report of L. Rafael Reif, Ph.D. dated Jun. 6, 2003..
Exhibit 1 of Opposition Report of L. Rafael Reif, Ph.D., Expert Witness Report of Robert A. Street including materials reviewed--May 23, 2003 [sic, May 22, 2003]..
Exhibit 2 of Opposition Report of L. Rafael Reif, Ph.D., Expert Witness Report of Richard A. Killworth--May 23, 2003, [sic. May 22, 2003]..
Exhibit 3 of Opposition Report of L. Rafael Reif, Ph.D., Deposition Transcript of Dr. Yamazaki pp. 1-4, 78-83, 86-89, 110, 113-117, 138-153, and 198--Apr. 30-May 2, 2003..
Exhibit 4 of Opposition Report of L. Rafael Reif, Ph.D., Deposition Transcript of Eric Robinson pp. 1-6, 29-69, 94-97, and 99-101--May 14, 2003..
Exhibit 5 of Opposition Report of L. Rafael Reif, Ph.D., Japanese Patent Publication No. 50-37500..
Exhibit 6 of Opposition Report of L. Rafael Reif, Ph.D., Japanese Patent Application Publication No. Sho51-1389..
Exhibit 7 of Opposition Report of L. Rafael Reif, Ph.D., Japanese Patent Application Publication No. Sho52-20312..
Opposition Expert Witness Report of Robert A. Street dated Jun. 4, 2003..
Exhibit 1 of Opposition Expert Witness Report of Robert A. Street, Expert Report of L. Rafael Reif..
Exhibit 2 of Opposition Expert Witness Report of Robert A. Street, Expert Report of John Bradley..
Exhibit 3 of Opposition Expert Witness Report of Robert A. Street, Tentative Claim Construction Order for United States Patent Nos. 5,929,527, 6,355,941, 6,404,476, and 6,404,480..
Expert Witness Report of Richard A. Killworth of May 22, 2003..
Reference 1 of Expert Witness Report of Richard A. Killworth, U.S. Patent No. 6,355,941..
Reference 2 of Expert Witness Report of Richard A. Killworth, May 1, 2003 Yamazaki Deposition Transcript (pp. 141-150)..
Reference 3 of Expert Witness Report of Richard A. Killworth, Yamazaki Deposition Exhibit 9..
Reference 4 of Expert Witness Report of Richard A. Killworth, Yamazaki Deposition Exhibit 10..
Reference 5 of Expert Witness Report of Richard A. Killworth, Apr. 30, 2003 Yamazaki Deposition Transcript (pp. 80-81)..
Reference 6 of Expert Witness Report of Richard A. Killworth, Information Disclosure Statement (SEL 00962-SEL 00963) and PTO Form 1449 (SEL 00963)..
Reference 7 of Expert Witness Report of Richard A. Killworth, Jul. 16, 1999 Office Action (SEL 00978-SEL 00979)..
Reference 8 of Expert Witness Report of Richard A. Killworth, May 14, 2003 Robinson Deposition Transcript (pp. 29-58)..
Reference 9 of Expert Witness Report of Richard A. Killworth, PTO Appeal Brief (SEL 00891-SEL 00908)..
Reference 10 of Expert Witness Report of Richard A. Killworth, PTO Board Ruling (SEL 00999)..
Reference 11 of Expert Witness Report of Richard A. Killworth, Oct. 10, 1995 Supplemental Information Disclosure Statement (SEL 00683-SEL 00692)..
Reference 12 of Expert Witness Report of Richard A. Killworth, Partial Translation of National Convention Record (SEL 59441)..
Reference 13 of Expert Witness Report of Richard A. Killworth, U.S. Patent No. 6,404,480..
Reference 14 of Expert Witness Report of Richard A. Killworth, May 15, 2003 Hirakata Deposition Transcript (p. 41)..
Exhibit 1 of Expert Witness Report of Richard A. Killworth, Curriculum Vitae..
Exhibit 2 of Expert Witness Report of Richard A. Killworth, Illustration of Violation of the Best Mode Requirement of 35 USC 112 in the '941 Patent..
Exhibit 3 of Expert Witness Report of Richard A. Killworth, Illustration of Examiner's Non-consideration of Material Prior Art in the '941 Patent, Namely Japanese Patents 55-050663 and 55-050664..
Exhibit 4 of Expert Witness Report of Richard A. Killworth, Illustration of Information Inconsistent with Positions Taken by '941 Patent Applicants..
Exhibit 5 of Expert Witness Report of Richard A. Killworth, Illustration of Misrepresentations Made During the Prosecution of the '480 Patent..
Preliminary Invalidity Contentions of Acer Incorporated, Acer America Corporation, and AU Optronics Corporation..
Physics of Semiconductor Devices, S.M. Sze "Thin Film Devices," pp. 567-624, 1969..
Matsumura et al., Extended Abstracts (The 40.sup.th Autumn [sic. Should be 26.sup.th Spring] Meeting), The Japan Society of Applied Physics, "a-Si Thin-Film MOS Transistors," 30P-S-18, p. 326.
Matsumura, The Japan Society of Applied Physics, vol. 49, No. 7, "Amorphous Silicon Thin-Film Electron Devices," Jul. 1980, pp. 729(81)-732(84)..
Matsumura et al., The Transactions of the Institute of Electronics and Communication Engineers of Japan, vol. J63-C, No. 2, "Amorphous Silicon Thin Film MOS Transistors," Feb. 1980, pp. 128-129..
Matsumura et al., National Convention Record, The Institute of Electronics and Communication Engineers of Japan, "a-Si FET Switching Properties," S3-12, Mar. 1980, pp. 2-285 to 2-286..
Weimer, Proceedings of the IRE, 50, "The TFT--A New Thin-Film Transistor," Jun. 1962, pp. 1462-1469..
Weimer, Physics of Thin Films, vol. 2 (ed. Haas), "The Insulated Gate Thin Film Transistor," 1964, pp. 147-192..
Powell et al., Appl. Phys. Lett. 38, "Amorphous Silicon--Silicon Nitride Thin-Film Transistors," May 15, 1981, pp. 794-796..
Matsumura et al., Proc. IEEE, vol. 68, No. 10, "Amorphous-Silicon Integrated Circuit," Oct. 1980, pp. 1349-1350..
SEL's Proposed Preliminary Claim Constructions and Extrinsic Evidence (Jan. 27, 2003)..
Acer Incorporated's Answer to First Amended Complaint for Patent Infringement and Counterclaims in Case No. C 02-02800 WHA..
Acer America Corporation's Answer to First Amended Complaint for Patent Infringement and Counterclaims in Case No. C 02-02800 WHA..
AU Optronics Corporation's Answer to First Amended Complaint for Patent Infringement and Counterclaims in Case No. C 02-02800 WHA..
Final Claim Construction Order for United States Patent Nos. 5,929,527, 6,355,941, 6,404,476, and 6,404,480 dated Jun. 11, 2003..
Final Invalidity Contentions of AU Optronics Corporation dated Jun. 20, 2003..
A. Madan, P.G. LeComber and W.E. Spear; Investigating the Density of Localized States in a-Si Using the Field Effect Technique; pp. 239-257; received Apr. 29, 1975--revised manuscript received Jun. 9, 1975; Journal of Non-Crystalline Solids 20(1976); North-Holland Publishing Company..
A.J. Snell, K.D. Mackenzie, W.E. Spear, and P.G. LeComber and A.J. Hughes; Application of Amorphous Silicon Field Effect Transistors in Addressable Liquid Crystal Display Panels; pp. 357-362; Applied Physics 24 (1981); Spring-Verlag 1981..
P.G. LeComber; Amorphous Silicon Thin Film Transistors and Memory Devices; pp. 341-351; Mal. Res. Soc. Symp. Proc. vol. 49, 1985; Materials Research Society..
Solid-State Electronics, vol. 15, 1972, pp. 789-799..
Philosophical Magazine, 1976, vol. 33, No. 6, pp 935-949, Electronic Properties of Substantially Doped Amorphous Si and Ge, W.E. Spear et al., 1976..
Proceedings of the 10th Conference on Solid States Devices, JAP, vol. 18, p 109-113, Determination of Localized State Density Distribution in Glow Discharge Amorphous Silicon, Hirose et al. 1979..
A Journal of Theoretical Experimental and Applied Physics Localized States in the Mobility Gap of Amorphous Quartz and Glass, pp 839-851, Anderson, 1974..
Proc. 7th Intern. Vac. Congr. & 34d Intern. Conf. Solid Surfaces, Preparation and Reliability of Thin Film Film Transistors Based on CdSe, M.J. Lee, 1979..
Solid State Communications, vol. 17, No. 9, pp 1193-1196, "Substitutional Doping of Amorphous Silicon", Spear et al., 1975..
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English Translation of National Convention Record, The Institute of Electronics and Communication Engineers of Japan, titled "A Si FET IC Integrated on a Glass Substrate", Tokyo Industrial University, Department of Technology, Hiroshi Hayama,Masakiyo Matsumura, pp. 1-5..
Matsuda et al., "Electrical and Structural Properties of Phosphorus--Doped Glow-discharge Si:F:H and Si:H Films", Japanese Journal of Applied Physics, vol. 19, No. 6, Jun., 1980, pp. L305-L308..
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M.J. Powell, et al., "Evidence for the Defect Pool Concept for Si Dangling Bond States in a-Si:H From Experiments with Thin Film Transistors," Journal of the Non-Crystalline Solids, 114 (1989), pp. 642-644..
Abstract: A semiconductor device which has a non-single crystal semiconductor layer formed on a substrate and in which the non-single crystal semiconductor layer is composed of a first semiconductor region formed primarily of non-single crystal semiconductor and a second semi-conductor region formed primarily of semi-amorphous semiconductor. The second semi-conductor region has a higher degree of conductivity than the first semiconductor region so that a semi-conductor element ray be formed.
1. A thin film transistor comprising: a pair of source and drain regions; a channel region between said source and drain regions; and a gate electrode adjacent to saidchannel region with a gate insulating film interposed therebetween, said channel region comprising an amorphous silicon semiconductor material doped with a recombination center neutralizer selected from the group consisting of H, a halogen and acombination thereof; said pair of source and drain regions comprising a non-single crystal semiconductor material doped with a recombination center neutralizer selected from the group consisting of H, a halogen and a combination thereof, and having animpurity conductivity type to form junctions in contact with said channel region, wherein at least a portion of said gate insulating film which is in direct contact with said channel region comprises a nitride.
2. A thin film transistor according to claim 1 wherein said channel region has an intrinsic conductivity type.
5. A thin film transistor comprising: a pair of source and drain regions; a channel region between said source and drain regions; and a gate electrode adjacent to said channel region with a gate insulating film interposed therebetween, saidchannel region comprising an intrinsic amorphous silicon semiconductor material doped with a recombination center neutralizer selected from the group consisting of H, a halogen and a combination thereof; said pair of source and drain regions comprisinga non-single crystal semiconductor material doped with a recombination center neutralizer selected from the group consisting of H, a halogen and a combination thereof, and having a P or N type conductivity to form PI or NI junctions in contact with saidchannel region, wherein at least a portion of said gate insulating film which is in direct contact with said channel region comprises a nitride.
6. A thin film transistor according to claim 5 wherein said gate electrode is located over said channel region.
8. A thin film transistor comprising: a semiconductor film having at least source, drain and channel regions comprising amorphous silicon, said source and drain regions forming junctions with said channel region; a gate insulating film adjacentto said channel region; and a gate electrode adjacent to said channel region with said gate insulating film therebetween, wherein said amorphous silicon semiconductor film contains a recombination center neutralizer selected from the group consisting ofH, a halogen and a combination thereof, and at least a portion of said gate insulating film which is in contact with said channel region comprises a nitride.
9. A thin film transistor according to claim 8 wherein said channel region has an intrinsic conductivity type.
11. A thin film transistor according to claim 1, 5 or 8 wherein said channel region comprises a material expressed by one of Si.sub.x Ge.sub.1-x (0<x<1); Si.sub.3 N.sub.4-x (0<x<4); SiO.sub.2-x (0<x<2); and SiC.sub.x(0<x<1).
12. A thin film transistor comprising: a pair of source and drain regions; a channel region between said source and drain regions; and a gate electrode adjacent to said channel region with a gate insulating film interposed therebetween, saidchannel region comprising an amorphous silicon semiconductor material doped with a recombination center neutralizer selected from the group consisting of H, a halogen and a combination thereof; said pair of source and drain regions comprising anon-single crystal semiconductor material doped with a recombination center neutralizer selected from the group consisting of H, a halogen and a combination thereof, and having an impurity conductivity type to form junctions in contact with said channelregion, wherein at least a portion of said gate insulating film which is in direct contact with said channel region comprises a nitride; wherein said channel region is interposed between said gate insulating film and another insulator different fromsaid gate insulating film; and wherein at least a portion of said junctions are covered by said another insulator.
13. A thin film transistor comprising: a pair of source and drain regions; a channel region between said source and drain regions; and a gate electrode adjacent to said channel region with a gate insulating film interposed therebetween, saidchannel region comprising an intrinsic amorphous silicon semiconductor material doped with a recombination center neutralizer selected from the group consisting of H, a halogen and a combination thereof; said pair of source and drain regions comprisinga non-single crystal semiconductor material doped with a recombination center neutralizer selected from the group consisting of H, a halogen and a combination thereof, and having a P or N type conductivity to form PI or NI junctions in contact with saidchannel region, wherein at least a portion of said gate insulating film which is in direct contact with said channel region comprises a nitride; and wherein said channel region is interposed between said gate insulating film and another insulatordifferent from said gate insulating file; and wherein at least a portion of said junctions are covered by said another insulator.
14. A thin film transistor comprising: a semiconductor film having at least source, drain and channel regions comprising amorphous silicon, said source and drain regions forming junctions with said channel region; a gate insulating filmadjacent to said channel region; and a gate electrode adjacent to said channel region with said gate insulating film therebetween, wherein said amorphous silicon semiconductor film contains a recombination center neutralizer selected from the groupconsisting of H, a halogen and a combination thereof, and at least a portion of said gate insulating film which is in contact with said channel region comprises a nitride; and wherein said channel region is interposed between said gate insulating filmand another insulator different from said gate insulating film; and wherein at least a portion of said junctions are covered by said another insulator.
Further, in the semi-amorphous semiconductor device, the semi-amorphous semiconductor provides a high degree of photoconductivity, a high degree of dark-conductivity, a high impurity ionization rate and a large diffusion length of minoritycarriers as compared with an amorphous or poly-crystalline semiconductor. This means that the semi-amorphous semiconductor device achieves a higher decree of photoelectric conversion efficiency than an amorphous or polycrystalline semiconductor device.
In the foregoing semi-amorphous semiconductor device, however, the number of recombination centers contained in the semi-amorphous semiconductor is as large as about 10.sup.17 to 10.sup.19 /cm.sup.3. Owing to such a large number of recombinationcenters, the diffusion length of the minority carriers in the semi-amorphous semiconductor is not set to a desirable value of about 1 to 50 .mu.m which is intermediate between 300 .ANG. which is the diffusion length of the minority carriers in anamorphous semiconductor and 10.sup.3 .mu.m which is the diffusion length of the minority carriers in a single crystal semiconductor. Therefore, according to the foregoing semiconductor technology, the semi-amorphous semiconductor device has aphotoelectric conversion efficiency as low as only about 2 to 4%.
In such a semiconductor device, however, the structure for isolating the plurality of semiconductor elements inevitably occupies an appreciably large area relative to the overall area of the device. Therefore, this semiconductor device is low inintegration density. In addition, the structure for isolating the plurality of semiconductor elements is inevitably complex. Therefore, the semi-conductor device of this type cannot be obtained with ease and at low cost.
Then, a non-single crystal semiconductor 7 doped with a dangling bond neutralizer is formed in layer on the major surface 1 of the substrate 2 to cover each of the conductive layers 3 through the insulating layer 6, as depicted in FIG. 1C. Inthis example the non-single crystal semiconductor, layer extends on the outer side surfaces of the conductive layers 3 and 5. The layer 7 can be formed 0.5 to 5 .mu.m thick.
The non-single crystal semiconductor layer 7 can be formed of non-single crystal silicon, germanium or additional semiconductor material compound expressed by Si.sub.3 N.sub.4-x (0<x<4), SiO.sub.2x (0<x<2), SiC.sub.x (o<x<1) orSi.sub.x Ge.sub.1-x (0<x<1). The dangling bond neutralizer is composed of hydrogen or halogen such as fluoride or chlorine.
Disposed around the semiconductor depositing region 34 of the reaction chamber 31 is an orientating-accelerating high-frequency power source 39 which applies to the semi-conductor depositing region 34 an orientating-accelerating electric fieldperpendicularly to the surfaces of the substrates 2. The electric field has a relatively low alternating frequency, for example, 1 to 100 MHz, preferably 13.6 MHz. The high-frequency power source may be formed by a coil which is supplied with ahigh-frequency current. The high-frequency power source 39 is covered with a heating source 40 which heats the semiconductor depositing region 34 and consequently the substrates 2. The heating source 40 may be a heater which is supplied with a directcurrent.
From the main semiconductor material compound gas source 47 is supplied a main semiconductor material compound gas A such as a main semiconductor m material hydride gas, a main semiconductor material halide gas, a main semiconductor materialorganic compound gas or the like. The main semiconductor material gas A is, for example, a silane (SiH.sub.4) gas, a dichlorosilane (SiH.sub.2 Cl.sub.2) gas, a trichlorosilane (SiHCl.sub.3) gas, silicon tetrachloride (SiCl.sub.4) gas, a silicontetrafluoride (SiF.sub.4) gas or the like. From the impurity compound gas source 48 is supplied an impurity compound gas B such as hydride, halide or hydroxide gas of a metallic impurity, for example, a trivalent impurity such as Ga or In, or aquadrivalent impurity such as Sn or Sb. From the impurity compound gas source 49 is supplied an impurity compound gas C such as hydride, halide or hydroxide gas of a metallic impurity, for example, a pentavalent impurity such as As or Sb. From theadditional semiconductor material compound gas source 50 is supplied an additional semiconductor material compound gas D such as an additional semiconductor material hydroxide or halide gas of nitrogen, germanium, carbon, tin, lead or the like, forexample, an SnCl.sub.2, SnCl.sub.4, Sn(OH).sub.2, Sn(OH).sub.4, GeCl.sub.4, CCl.sub.4, NCl.sub.3, PbCl.sub.2, PbCl.sub.4, Pb(OH).sub.2, Pb(OH).sub.4 or the like gas. From the carrier gas source 51 is supplied a carrier gas E which is a gas composed ofor contains a Helium (He) and/or neon (Ne) gas, for example, a gas composed of the helium gas, a neon gas or a mixer gas of the helium gas or the neon gas and a hydrogen gas.
In the semiconductor depositing region 34 of the reaction chamber 31 there is placed on a boat 38 as of quartz the substrate 2 which has provided on the major surface thereof the conductive layer 3 and the insulating layer 6 thereon, as describedpreviously in respect of FIG. 1C.
As described above, the substrate 2 is placed in the semiconductor depositing region 34 of the reaction chamber 31 and, in the state in which the gas in the reaction chamber 31 is exhausted by the exhauster 54 through the gas outlet 25, the gasoutlet pipe 52 and the control valve 53, a mixture gas F containing at least the main semiconductor material compound gas A available from the main semiconductor material compound gas source 47 via the control valve 42 and the carrier gas E availablefrom the carrier gas source 51 via the control valve 46 is introduced into the gas ionizing region of the reaction chamber 31 via the gas inlet 32. In this case, the mixture gas F may contain the impurity compound gas B available from the impuritycompound gas source 48 via the control valve 43 or the impurity compound gas C available from the impurity compound gas souurce 49 via the control valve 44. Further, the mixture gas F may also contain the additional semiconductor material compound gasavailable from the additional semiconductor material compound gas source 50 via the control valve 45. The amount of the carrier gas E contained in the mixture gas F may be 5 to 99 flow rate %, in particular, 40 to 90 flow rate % relative to the mixturegas F.
The mixture gas plasma G thus formed is flowed into the semiconductor depositing region 34 through the gas homogenizer 55 by exhausting the gas in the reaction chamber 31 by means of the exhauster 54 through the gas outlet 25, the gas outlet pipe52 and the control valve 53.
By flowing the mixture gas plasma G into the semiconductor depositing region 34, semiconductor material is deposited on the substrate 2 placed in the semiconductor depositing region 34. In this case, the flow rate of the mixture gas F introducedinto the reaction chamber 31, especially the flow rate of the carrier gas E contained in the mixture gas F is controlled beforehand by the adjustment of the control valve 46 and the flow rate of the gas exhausted from the reaction chamber 31 trough thegas outlet 25 is controlled in advance by adjustment of the control valve 53, by which the atmospheric pressure in the reaction chamber 31 is held below 1 atm. Moreover, the substrate 2 is maintained at a relatively low temperature under a temperatureat which semiconductor layers deposited on the substrate 2 become crystallized, for example, in the range from the room temperature to 700.degree. C. In the case of maintaining the substrate 2 at room temperature, the heating source 40 need not be used,but in the case of holding the substrate 2 at a temperature higher than the room temperature, the heating source 40 is used to heat the substrate 2. Furthermore, the deposition of the semiconductor material on the substrate 2 is promoted by theorientating-accelerating electric field established by the orientating-accelerating high-frequency source 39 in a direction perpendicular to the surfaces of the substrate 2.
In addition, since the flow rate of the semiconductor material compound gas plasma contained in the mixture gas plasma G formed in the gas ionizing region 33 is large with respect to the flow rate of the entire gas in the gas ionizing region 33,as mentioned previously, the flow rate of the semiconductor material compound gas plasma contained in the mixture gas on the surface of the substrate 2 in the semi-conductor depositing region 34 is also large relative to the flow rate of the entire gason the surface of the substrate 2. This ensures that the non-single crystal semi-conductor 7 deposited on the surface of the substrate 2 has substantially no or a negligibly small number of voids and is homogeneous in the direction of the surface of thesubstrate 2.
Besides, since the carrier gas plasma contained in the mixture gas plasma forced in the gas ionizing region 33 has a large ionizing energy, as referred to previously, the energy of the carrier gas plasma has a large value when and after themixture gas plasma flows into the semi-conductor depositing region 34, and consequently the energy of the semiconductor material compound gas plasma contained in the mixture plasma on the substrate 2 in the semiconductor depositing region 34 has a largevalue. Accordingly, the non-single crystal semiconductor 7 can be deposited on the substrate 2 with high density.
Furthermore, the carrier gas plasma contained in the mixture gas plasma is composed of or includes the helium gas plasma and/or the neon gas plasma, and hence has a high thermal conductivity. Incidentally, the helium gas plasma has a thermalconductivity of 0.123 Kcal/mHg.degree.C. and the neon gas plasma 0.0398 Kcal/mHg.degree.C. Accordingly, the carrier gas plasma greatly contributes to the provision of a uniform temperature distribution over the entire surface of the substrate 2. Inconsequence, the non-single crystal semi-conductor 7 deposited on the substrate 2 can be made homogeneous in the direction of its surface.
Moreover, since the carrier gas plasma contained in the mixture gas in the semiconductor depositing region 34 is a gas plasma composed of or containing the helium gas plasma and/or the neon gas plasma, the helium gas plasma is free to move in thenon-single crystal semiconductor 7 formed on the substrate 2. This reduces the density of recombination centers which tends to be formed in the non-single crystal semiconductor 7, ensuring to enhance its property.
The above has clarified the manufacturing method of the present invention and its advantages in the case where the non-single crystal semiconductor 7 is the semi-amorphous semiconductor. Also in the case where the non-single crystalsemiconductor 7 is an amorphous semiconductor or a mixture of the semi-amorphous semiconductor and the amorphous semi-conductor, it can be formed by the above-described method, although no description will be repeated.
Following this, a conductive layer 9 is formed by a known method on the non-single crystal semiconductor 7 in an opposing relation to the conductive layer 3 through the insulating layer 8 as depicted in FIG. 1D. The conductive layer 9 can beprovided in the form of a film of aluminum, magnesium or the like. In this example, each conductive layer 9 extends across the side of the non-single crystal semiconductor layer 7 and the surface 1 of the substrate 2 to the conductive layer 5 contagiousto the adjoining conductive layer 9.
Then, a power source 11 is connected at one end with alternate ones of the conductive layers 4 and at the other end with intermediate ones of them; accordingly, the power source 11 is connected across the conductive layers 3 and 9. At this time,the region Z2 of the non-single crystal semi-conductor layer 7, except the outer peripheral region z1 thereof, is exposed to high L from the side of the light-permeable substrate 2 through the light-permeable conductive layer 3 and insulating layer 6 bythe application of light L, electron-hole pairs are created in the non-single crystal semiconductor 7 to increase its conductivity. Accordingly, the irradiation by light L during the application of the current I to the non-single crystal semiconductor 7facilitates a sufficient supply of the current I to the region Z2 even if the non-single crystal semiconductor 7 has a low degree of conductivity or conductivity close to intrinsic conductivity. For the irradiation of the non-single crystalsemiconductor 7, a xenon lamp, fluorescent lamp and sunlight, can be employed. According to an experiment, good results were obtained by the employment of a 10.sup.3 -lux xenon lamp. In the region Z2 a semi-amorphous semiconductor S2 is formed, asdepicted in FIG. 1G. The mechanism by which the semi-amorphous semiconductor S2 is formed in the region Z2 is that heat is generated by the current I in the region Z2, by which it is changed in terms of structure.
In the case where the non-single crystal semiconductor 7 is formed of the semi-amorphous semiconductor (which will hereinafter be referred to as a starting semi-amorphous semi-conductor), the region Z2 is transformed by the heat generated by thecurrent I into the semi-amorphous semiconductor S2 which contains the microcrystalline semiconductor more richly than does the starting semi-amorphous semiconductor. Even if the non-single crystal semiconductor 7 is the amorphous semi-conductor or themixture of the semi-amorphous and the amorphous semiconductor, the semi-amorphous semiconductor S2 is formed to have the same construction as in the case where the non-single crystal semiconductor 7 is the semi-amorphous one.
By the thermal energy which is yielded in the region Z2 when the semi-amorphous semiconductor S2 is formed in the region Z2, dangling bonds of the semiconductor are combined, neutralizing the dangling bonds in that region. The non-single crystalsemiconductor 7 is doped with a dangling bond neutralizer such as hydrogen and/or halogen. Accordingly, the dangling bond neutralizer is activated by the abovesaid thermal energy in the region Z2 and its vicinity and combined with the dangling bonds ofthe semiconductor. As a result of this, the semi-amorphous semiconductor S2 formed in the region Z2 has a far smaller number of recombination centers than the non-single crystal semiconductor. According to our experience, the number of recombinationcenters in the semi-amorphous semiconductor S2 was extremely small--on the order of 1/10.sup.2 to 1/10.sup.4 that of the non-single crystal semiconductor 7.
The thermal energy which is produced in the region Z2 during the formation therein of the semi-amorphous semiconductor S2 contributes to the reduction of the number of recombination centers and the provision of the suitable diffusion length ofminority carriers. Further, it has been found that the generation of the abovesaid heat contributes to the formation of the semi-amorphous semiconductor S2 with an interatomic distance close to that of the single crystal semiconductor although thesemiconductor S2 does not have the atomic orientation of the latter. In the case where the non-single crystal semiconductor 7 was non-single crystal silicon, the semi-amorphous semiconductor S2 was formed with an interatomic distance of 2.34.ANG..+-.20% nearly equal to that 2.34 .ANG. of single crystal silicon. Acccordingly, the semi-amorphous semiconductor S2 has stable properties as semiconductor, compared with the non-single crystal semiconductor 7.
Further, it has been found that the abovementioned heat generation contributes to the formation of the semi-amorphous semiconductor S2 which exhibits an excellent electrical conductivity characteristic. FIG. 3 shows this electrical conductivitycharacteristic, the abscissa representing temperature 100/T (.degree.K.sup.-1) and the ordinate dark current log .sigma. (.sigma.:.sigma. cm.sup.-1). According to our experiments, in which when the non-single crystal semiconductor 7 had acharacteristic indicated by the curve al, the currents having densities of 3.times.10.sup.1 and 1.times.10.sup.3 A/cm.sup.2 were each applied as the aforesaid current I for 0.5 sec. while irradiating by the light L at an illumination of 10.sup.4 LX, suchcharacteristics as indicated by the curves a2 and a3 were obtained, respectively. In the case where when the non-single crystal semi-conductor 7 had such a characteristic as indicated by the curve b1, the currents of the same values as mentioned abovewere each applied as the current I for the same period of time under the same illumination condition, a characteristics indicated by the curves b2 and b3 were obtained, respectively. The curve b1 shows the characteristic of a non-single crystalsemiconductor obtained by adding 1.2 mol % of the aforementioned metallic impurity, such as Ga or In, Sn or Pb, or As or Sb, to the non-single crystal semiconductor 7 of the characteristic indicated by the curve a1. As is evident from a comparison ofthe curves a2, a3 and b2, b3, a semi-amorphous semiconductor obtained by adding the abovesaid metallic impurity to the semi-amorphous semiconductor S2 exhibits an excellent conductivity characteristic over the latter with such a metallic impurity added. It is preferred that the amount of metallic impurity added to the semi-amorphous semiconductor S2 be 0.1 to 10 mol %.
Also it has been found that the aforesaid heat generation greatly contributes to the reduction of dangling bonds in the semi-amorphous semiconductor S2. FIG. 4 shows the reduction of the dangling bonds, the abscissa representing the density D(A/cm.sup.2) of the current I applied to the region Z2 when forming the semi-amorphous semiconductor S2 and the ordinate representing the normalized spin density G of the dangling bonds. The curves C1, C2 and C3 indicate the reduction of dangling bondsin the cases where the current I was applied to the region Z2 for 0.1, 0.5 and 2.5 sec., respectively. It is assumed that such reduction of the dangling bonds is caused mainly by the combination of semiconductors as the semi-amorphous semiconductor S2contains as small an amount of hydrogen as 0.1 to 5 mol % although the non-single crystal semiconductor 7 contains as large an amount of hydrogen as 20 mol % or so.
FIG. 1 illustrates a semiconductor device according to the present invention produced by the manufacturing method described in the foregoing. On the substrate 2 there are provided the semi-amorphous semiconductor region S2 of the abovesaidexcellent properties and the non-single crystal semiconductor region S1 formed by that region Z1 of the non-single crystal semiconductor layer 7 in which the current I did not flow during the formation of the semi-amorphous semiconductor region S2. Thenon-single crystal region S1 does not possess the abovesaid excellent properties of the semi-amorphous semiconductor region S2. Especially, the region S1 does not have the excellent conductivity characteristic of the region S2 and the former can beregarded as an insulating region relative to the latter. Consequently, the non-single crystal semiconductor region S1 electrically isolates the semi-amorphous semiconductor regions S2 from adjacent ones of them. The conductive layer 3, the insulatinglayer 6 and the semi-amorphous semiconductor region S2 make up one MIS structure, and the conductive layer 9, the insulating layer 8 and the semi-amorphous semiconductor region S2 make up another MIS structure. Such a construction is similar to that ofa MIS type photoelectric conversion semiconductor device proposed in the past. Accordingly, by using the conductive layers 3 and 9 as electrodes and applying light to the semiconductor device of FIG. 1F from the outside thereof so that the light mayenter the semi-amorphous semiconductor S2 through the light-permeable substrate 2, conductive layer 3 and insulating layer 6, it is possible to obtain the photoelectric conversion function similar to that obtainable with the conventional MIS typephotoelectric conversion semiconductor device. In the semi-amorphous semiconductor S2 of the semi-amorphous semi-conductor device of FIG. 1F, however, the number of recombination centers is far smaller than in the case of an ordinary semi-amorphoussemiconductor (corresponding to the case where the non-single crystal semiconductor 7 prior to the formation of the semi-amorphous semiconductor S2 is semi-amorphous); the diffusion length of minority carriers is in the range of 1 to 50 .mu.m; and theinteratomic distance is close to that in the single crystal semiconductor. Therefore, the semi-conductor device of FIG. 1G has such an excellent feature that it exhibits a markedly high photo-electric conversion efficiency of 8 to 12%, as compared withthat of the prior art semiconductor device (corresponding to a device which has the construction of FIG. 1E and has its non-single crystal semiconductor 7 formed of semi-amorphous semiconductor).
The manufacture starts with the reparation of an insulating substrate 62 with a major surface 61, such as shown in FIG. 6A. The substrate 61 is one that has an amorphous material surface, such as a glass plte, ceramic plate or silicon wafercovered over the entire area of its surface with a silicon oxide film.
Following this, as shown in FIG. 6C, a ring-shaped insulating layer 64 of semiconductor oxide is formed by known oxidizing method to a relatively large thickness of, for example, 0.2 to 0.5 .mu.m on the side of the surface of the layer 63. Then,an insulating layer 65 of amorphous semi-conductor nitride is formed relatively thin, for example, 50 to 100 .ANG. in that region of the layer 63 surrounded by the insulating layer 64.
Thereafter, as depicted in FIG. 6I, a conductive layer 66 of amorphous or semi-amorphous semiconductor is formed on the insulating layer 65 to extend across the ring-shaped insulating layer 64 diametrically thereof (in the direction perpendicularto the sheet in the drawing). The semiconductor layer 66 is doped with 0.1 to 5 mol % of an N type conductive material such as Sb or As, or a P type conductive material such as In or Ga. Further, windows 67 and 68 are formed in the insulating layer 65on both sides of the conductive layer 66 where the windows are contiguous to the insulating layer 64. A conductive layers 69 and 70 similar to the layer 66 extending on the insulating layer 64 are formed to make ohmic contact with the semiconductorlayer 63 through the windows 67 and 68, respectively.
This is followed by connecting a prower source 76 across the conductive layers 69 and 70, by which the current I flows through the regions 71, 72 and 74. In this case, no current flows in the region 73. By the current application, heat isgenerated in the regions 71, 72 and 74. In consequence, as described previously in respect of FIGS. 1F and 1G, the regions 71, 72 and 74 respectively undergo a structural change into semi-amorphous semiconductor regions 77, 78 and 79, respectively, asshown in FIG. 6H.
Thereafter, the non-single crystal semiconductor layer 84 is exposed to irradiation by laser light, with a power source 86 connected across the conductive layers 83 and 85, as illustrated in FIG. 7E. In this case, a laser beam L' having adiameter of 0.3 to 3 .mu.m, for instance, is applied to the non-single crystal semiconductor layer 84 at selected ones of successive positions a.sub.1, a.sub.2, . . . thereon, for example, a.sub.1, a.sub.3, a.sub.4, a.sub.8, a.sub.9, at the momentst.sub.1, t.sub.3, t.sub.4, t.sub.8, t.sub.9, . . . in a sequential order, as depicted in FIG. 8. By this irradiation the conductivity of the non-single crystal semiconductor layer 84 is increased at the positions a.sub.1, a.sub.3, a.sub.4, a.sub.8,a.sub.9, . . . to flow there currents I.sub.1, I.sub.3, I.sub.4, I.sub.8, I.sub.9, . . . , thus generating heat. As a result of this, the non-single crystal semiconductor layer 84 undergoes a structural change at the positions a.sub.1, a.sub.3,a.sub.4, a.sub.8, a.sub.9, . . . to provide semi-amorphous semiconductor regions K.sub.1, K.sub.3, K.sub.4, K.sub.8, K.sub.9, . . . , as showin in FIG. 7F.
In the semiconductor device of the present invention illustrated in FIG. 7F, the regions K.sub.1, K.sub.3, K.sub.4, K.sub.8, K.sub.9, . . . correspond to the semi-amorphous semiconductor region S2 in FIG. 1G, providing a high degree ofconductivity. Regions K.sub.2, K.sub.5, K.sub.6, K.sub.7, K.sub.11, . . . at the positions a.sub.2, a.sub.5, a.sub.6, a.sub.7, a.sub.11, . . . other than the regions K.sub.1, K.sub.3, K.sub.4, K.sub.8, K.sub.9, . . . correspond to the non-singlecrystal semiconductor S1 in FIG. 1G, providing the property of an insulator.
The semiconductor device shown in FIG. 7F can be regarded as a memory in which "1", "0", "1", "1", "0", . . . in the binary representation are stored at the positions a.sub.1, a.sub.2, a.sub.3, a.sub.4, a.sub.5, . . . , respectively. When theregions K.sub.1, K.sub.3, K.sub.4, . . . and consequently the positions a.sub.1, a.sub.3, a.sub.4, . . . are irradiated by a laser beam of lower intensity than the aforesaid one L' while at the same time connecting the power source across theconductive layers 83 and 85 via a load, the regions K.sub.1, K.sub.3, K.sub.4, . . . become more conductive to apply a high current to the load. Even if the regions K.sub.2, K.sub.5, K.sub.6, . . . are irradiated by such low-intensity laser beam,however, no current flows in the load, or if any current flows therein, it is very small. Accordingly, by irradiating the positions a.sub.1, a.sub.2, a.sub.3, . . . by low-intensity light successively at the moments t.sub.1, t.sub.2, t.sub.3, . . . ,outputs corresponding to "1", "0", "1", "1", . . . are sequentially obtained in the load, as shown in FIG. 9. In other words, the semiconductor device of this embodiment has the function of a read only memory.
Although in the foregoing embodiments the semiconductor device of the present invention has been described as being applied to a photoelectric conversion element, a MIS type field effect transistor and a photo memory, the embodiments should notbe construed as limiting the invention specifically thereto. According to this invention, it is possible to obtain a photoelectric conversion element array composed of a plurality of series-connected photoelectric conversion elements as shown in FIG.1G. Further, it is possible to form an inverter by a series connection of two MIS type field effect transistors as depicted in FIG. 6H. In this case, those regions of either of MIS type field effect transistors which serve as the source and drainregions thereof differ in conductivity type from those of the other and the region which serves as the channel region is doped, as required, with an impurity that makes it opposite in conductivity type to that of the source and drain regions. Moreover,the semi-amorphous semiconductor forming the semi-conductor device according to the present invention permits direct transition of electrons even at lower temperatures than does the amorphous semiconductor. Therefore, it is also possible to obtainvarious semiconductor elements that are preferred to utilize the direct transition of electrons. Also it is possible to obtain various semiconductor elements, including a bipolar transistor and a diode, of course, which have at least one of PI, PIN, PIand NI junctions in the semi-amorphous semiconductor layer forming the semiconductor device according to the present invention.
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