Source: http://www.google.com/patents/US7957185?dq=6289460
Timestamp: 2015-05-03 13:24:15
Document Index: 21888287

Matched Legal Cases: ['Application No. 200580049799', 'Application No. 10000203', 'Application No. 05', 'Application No. 2008', 'Application No. 094116919', 'Application No. 094116919']

Patent US7957185 - Non-volatile memory and method with power-saving read and program-verify ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative...http://www.google.com/patents/US7957185?utm_source=gb-gplus-sharePatent US7957185 - Non-volatile memory and method with power-saving read and program-verify operationsAdvanced Patent SearchPublication numberUS7957185 B2Publication typeGrantApplication numberUS 11/534,297Publication dateJun 7, 2011Filing dateSep 22, 2006Priority dateMar 16, 2005Fee statusPaidAlso published asCN101180682A, CN101180682B, DE602005019789D1, EP1859448A1, EP1859448B1, EP2169684A1, US7251160, US7570513, US8154923, US8542529, US20060209592, US20070014156, US20070014161, US20110222345, US20120243332, WO2006101500A1Publication number11534297, 534297, US 7957185 B2, US 7957185B2, US-B2-7957185, US7957185 B2, US7957185B2InventorsYan Li, Seungpil Lee, Siu Lung ChanOriginal AssigneeSandisk CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (64), Non-Patent Citations (14), Referenced by (5), Classifications (10), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetNon-volatile memory and method with power-saving read and program-verify operations
US 7957185 B2Abstract
1. In an array of nonvolatile memory cells, wherein each memory cell is accessible by a set of word lines and bit lines and is programmable to a current conducting threshold voltage that corresponds to one of multiple memory states, a method of sensing in parallel a group of the memory cells to be sensed, comprising:
precharging the set of word lines for the memory cells of said group to a set of predetermined word line voltages;
precharging the bit lines for the memory cells of said group each to a predetermined bit line voltage so as to allow a conduction current to flow in each of the memory cells depending on each memory state, said precharging bit lines being sustained over a duration at least after the set of predetermined word line voltages and each predetermined bit line voltage have stabilized; and
sensing the memory cells in parallel to determine the state of each memory cells; wherein said precharging the set of word lines preempts said precharging of each bit line for the group of memory cells to be sensed so as to minimize said duration.
5. The nonvolatile memory as in claim 1, wherein the non-volatile memory is a flash EEPROM.
6. The nonvolatile memory as in claim 1, wherein the nonvolatile memory is embodied in a memory card.
7. The nonvolatile memory as in claim 1, wherein the nonvolatile memory is embedded in a computing device.
8. The nonvolatile memory as in any one of claims 1-7, wherein the nonvolatile memory has memory cells that individually store one bit of data.
9. The nonvolatile memory as in any one of claims 1-7, wherein the nonvolatile memory has memory cells that individually store more than one bit of data.
FIG. 4 illustrates the relation between the source-drain current ID and the control gate voltage VCG for four different charges Q1-Q4 that the floating gate may be selectively storing at any one time. The four solid ID versus VCG curves represent four possible charge levels that can be programmed on a floating gate of a memory cell, respectively corresponding to four possible memory states. As an example, the threshold voltage window of a population of cells may range from 0.5V to 3.5V. Six memory states (�1�-�6�) may be demarcated by partitioning the threshold window into five regions in interval of 0.5V each. For example, if a reference current, IREF of 2 μA is used as shown, then the cell programmed with Q1 may be considered to be in a memory state �1� since its curve intersects with IREF in the region of the threshold window demarcated by VCG=0.5V and 1.0V. Similarly, Q4 is in a memory state
United States Patent Publication No. 2004-0057318-A1 discloses a memory device and a method thereof that allow sensing a plurality of contiguous memory cells in parallel. For example, all memory cells along a row sharing the same word lines are read or programmed together as a page. This �all-bit-line� architecture doubles the performance of the �alternate-bit-line� architecture while minimizing errors caused by neighboring disturb effects. However, sensing all bit lines does bring up the problem of cross-talk between neighboring bit lines due induced currents from their mutual capacitance. This is addressed by keeping the voltage difference between each adjacent pair of bit lines substantially independent of time while their conduction currents are being sensed. When this condition is imposed, all displacement currents due to the various bit lines capacitance drop out since they all depend on a time varying voltage difference. The sensing circuit coupled to each bit line has a voltage clamp on the bit line so that the potential difference on any adjacent pair of connected bit lines is time-independent. With the bit line voltage clamped, the conventional method of sensing the discharge due to the bit line capacitance can not be applied. Instead, the sensing circuit and method allow determination of a memory cell's conduction current by noting the rate it discharges or charges a given capacitor independent of the bit line. This will allow a sensing circuit independent of the architecture of the memory array (i.e., independent of the bit line capacitance.) Especially, it allows the bit line voltages to be clamped during sensing in order to avoid bit line crosstalk.
FIG. 6A illustrates schematically a compact memory device having a bank of read/write circuits, which provides the context in which the present invention is implemented. The memory device includes a two-dimensional array of memory cells 300, control circuitry 310, and read/write circuits 370. The memory array 300 is addressable with addresses ADDR by word lines via a row decoder 330 and by bit lines via a column decoder 360. The read/write circuits 370 is implemented as a bank of sense modules 480 (such as Sense Module 1, Sense Module 2, . . . , and Sense Module p) and allows a block (also referred to as a �page�) of memory cells to be read or programmed in parallel. In a preferred embodiment, a page is constituted from a contiguous row of memory cells. In another embodiment, where a row of memory cells are partitioned into multiple blocks or pages, a block (or page) multiplexer 350 is optionally provided to multiplex the read/write circuits 370 to the individual blocks.
STEP 430: Providing an array of nonvolatile memory cells, wherein each memory cell is programmable to a threshold voltage for conducting current, corresponding to one of multiple memory states. STEP 432: Providing a series of predetermined demarcation current values in decreasing order to discriminate between multiple memory states with lower and lower conduction currents. STEP 434: Selecting a first predetermined demarcation current value from the series. STEP 436: Sensing the plurality of memory cells in parallel to identify those memory cells having conduction currents higher than the selected demarcation current value. STEP 438: Turning off the conduction currents of those identified, higher current, memory cells among the plurality of memory cells being sensed in parallel. STEP 440: Has the end of the series been reached? If not proceed to STEP 442. Otherwise proceed to STEP 450. STEP 442: Selecting a next demarcation threshold voltage in the series. Proceed to STEP 436 STEP 450: End.
Programming is accomplished by alternately applying a programming pulse to a page of memory cells in parallel followed by sensing or program verifying on each of the cells to determine if any of them has been programmed to their target states. Whenever a cell has been program verified, it is locked out or program inhibited from further programming even as the programming pulses continue to be applied to complete the programming of the other cells in the group. It can be seen from FIGS. 8B and 8C that during the lower page programming, program verification need be performed relative to state �A� (denoted by �verifyA�) with the demarcation threshold voltage DA. However, for the upper page programming, program verification need be performed relative to states �B� and �C�. Thus, the upper page verify will require a 2-pass verify of �verifyB and �verifyC�, respectively relative to the demarcation threshold voltages DB and DC.
FIG. 9D illustrates the read operation that is required to discern the lower bit of the 4-state memory encoded with the LM code. The decoding will depend on whether the upper page has been programmed or not. If the upper page has been programmed, reading the lower page will require one read pass of readB relative to the demarcation threshold voltage DB. On the other hand, if the upper page has not yet been programmed, the lower page is programmed to the �intermediate� state (FIG. 9B), and readB will cause error. Rather, reading the lower page will require one read pass of readA relative to the demarcation threshold voltage DA. In order to distinguish the two cases, a flag (�LM� flag) is written in the upper page when the upper page is being programmed. During a read, it will first assume that the upper page has been programmed and therefore a readB operation will be performed. If the LM flag is read, then the assumption is correct and the read operation is done. On the other hand, if the first read did not yield a flag, it will indicate that the upper page has not been programmed and therefore the lower page would have to be read by a readA operation.
FIG. 9E illustrates the read operation that is required to discern the upper bit of the 4-state memory encoded with the LM code. As is clear from the figure, the upper page read will require a 2-pass read of readA and readC, respectively relative to the demarcation threshold voltages DA and DC. Similarly, the decoding of upper page can also be confused by the �intermediate� state if the upper page is not yet programmed. Once again the LM flag will indicate whether the upper page has been programmed or not. If the upper page is not programmed, the read data will be reset to �1� indicating the upper page data is not programmed.
FIG. 12(A)-12(I) are timing diagrams that controls the operation of the sense module 480 shown in FIG. 11 during the 3-pass read as applied to a NAND memory cell that is part of a memory page in parallel. FIG. 12(A) shows the read operation to be divided into seven phases, with phases (1) and (2) grouped under a world line precharge suboperation, followed by phases (3) and (4) under readA, phases (5) and (6) under readB and phase (7) under readC suboperations respectively. FIG. 12(B) shows that the read operation is timed at the start and end by the FSM READ signal rising and falling respectively.
The readA suboperation begins at phase (3) with the signal RST resetting the sense amplifier's output signal INV to zero (FIG. 12(G)). At the same time, the NAND chain is enabled for connection to the bit line by the signals SGS and SGD turning on a pair of select transistors of the NAND chain. The bit line is then coupled to the sense module by an enabling signal BLS (FIG. 12(H)). At that moment, the precharge/clamp circuit 640 in the sense module charges up the bit line to a predetermined voltage (e.g. 0.5V) against a draining conduction current, IDS, of the memory cell (shown as �IDS ON� in FIG. 12(H). As soon as the bit line voltage is stable, a strobe signal STB enables a latching of the result of the cell current discriminator 650 into the latch 660 (shown as �Latch A� in FIG. 12(I)). If the programmed threshold voltage of the memory cell is less than that of the demarcation threshold DA, (or equivalently, the cell's conduction current is higher than a demarcation current) the node SEN or SEN2 will be drained down to LOW by the conduction current. This will result in a latch result with an INV signal at HIGH. Conversely, if the programmed threshold voltage of the memory cell is higher than DA, SEN2 will be detected to be HIGH and INV will be latched LOW. As soon as the data from the sense amplifier is latched, the signal BLS goes LOW, thereby disconnecting the memory cell from the sense module.
STEP 510: Providing an array of nonvolatile memory cells, wherein each memory cell is programmable to a threshold voltage for conducting current, corresponding to one of multiple memory states. STEP 520: Programming a group of memory cells in parallel with a programming pulse. STEP 530: Turning off the conduction currents of those memory cells in the group that are program inhibited. STEP 540: Sensing in parallel the group of memory cells to verify if each of the memory cells have been programmed to its target memory state. STEP 542: Has all memory cells of the group been verified? Otherwise proceed to STEP 520. STEP 540: End. FIGS. 16(A)-16(J) are timing diagrams for the operation of the sense module shown in FIG. 11 during the verify phase of the program operation of FIG. 15. The example shows a 3-pass sensing, verifyA, verifyB and verifyC relative to the memory states �A�, �B�and �C� respectively. The timing signals and operations are similar to the 3-pass read operation shown in the timing diagrams of FIG. 12(A)-12(I). The main difference in the verify case is that at the beginning of each verify suboperation, the memory cells which are not program-inhibited or locked out will have their bit lines selected for precharged (with INV=0) (see FIG. 16 (I) where the signal BLSe1 has the non-locked out bits selected) while the rest have their bit lines pulled down to ground (with INV=1).
STEP 550: In an array of nonvolatile memory cells, wherein each memory cell is programmable to a threshold voltage for conducting current, corresponding to one of multiple memory states. STEP 560: Programming a group of memory cells in parallel with a programming pulse. STEP 570: Turning off the conduction currents of those memory cells in the group with programmed memory states other than the target memory state currently being program-verified. STEP 580: Sensing in parallel the group of memory cells to verify if each of the memory cells have been programmed to the target memory state. STEP 582: Has all memory cells of the group been verified? Otherwise proceed to STEP 560. STEP 590: End. FIGS. 18(A)-18(J) are timing diagrams for the operation of the sense module 480 shown in FIG. 11 during the verify phase of the program operation of FIG. 17. Again, the example shows similar timing signals as in FIG. 12 and FIG. 16 for a 3-pass sensing, verifyA, verifyB and verifyC relative to the memory states �A�, �B� and �C� respectively. The timing and operations are similar to the 3-pass verify operation shown in the timing diagrams of FIG. 17(A)-172(J). The main difference in the memory-state-specific verify case is that at the beginning of each verify suboperation, the memory cells which are known to have a memory state current undergoing verification will have their bit lines selected for precharged (with INV=0) (see FIG. 18 (I)) while the rest have their bit lines pulled down to ground (with INV=1). Thus, during the suboperation verifyA, only the memory cells slated for state �A� are selected to have their bit lines precharged and sensed. Similarly, for verifyB and verifyC, only the memory cells respectively slated for state �B� and �C� are precharged and sensed. Furthermore, since different memory cells within the page with different memory states are selected during each verify suboperation, all bit lines within the page have their INV reset to zero before each selection (FIG. 18(G)).
FIG. 20 illustrates a preferred scheme for jump-starting the word line precharge in a sensing operation. The reference characters are similar to that in FIG. 19. Two sense cycles, Sense Cycle (n-1) and Sense Cycle n are shown, each comprising readA and readB subcycles. Essentially, when the period for word line precharge (WL Precharge) is longer than that of bit line precharge (BL Precharge), the word lines are preemptively precharged (WL Precharge) at an earlier sense cycle. In the precharged operation, the selected bit line typically rises by about 0.5V, the unselected word lines by about 5.5V and the selected word line by about 1V. Since the unselected word lines have to be increased by 5.5V, the time for them to get there will become longer as the word line capacitance increases with increasing page size. Before latching of the sense result can take place, the VT(i) on the selected word line must be stable, which, due to coupling effect, is predicated on a reasonably stable voltage on the unselected word lines. Expediently, the jump-start on precharging the unselected word lines can take place during the data transfer phase of the previous sensing cycle. In this way, at least some of the delays caused by a longer word line precharge period can be reduced if not eliminated altogether and the overall precharge period will then be determined by the time for the bit line precharge to become stable (shown as �BL Settling�).
For example in programming a page of memory cells, the data will require some cells to be programmed to a threshold voltage greater than a demarcation threshold voltage DA (�Group PROGRAM� cells) while other cells will not be programmed (�Group LOCKOUT� cells) having a threshold voltage less than DA. Initially, Group LOCKOUT will be constituted from cells that are dictated by data to be unprogrammed. In the first program phase, Group PROGRAM cells will have their bit lines at 0V while Group LOCKOUT cells will have their bit lines charged up to Vdd to effect program inhibition. In the next verfyA phase, the state of Group LOCKOUT cells is known and need not be sensed. Group PROGRAM cells have their bit lines charged up to at least 0.5V for sensing. The sense result will distinguish two subgroups from Group PROGRAM. One subgroup (�Subgroup NOTVERIFIED�) is for cells that have not yet been programmed past DA while the other subgroup (�Subgroup VERIFIED�) is for cells that have already been programmed past DA. In the next pass of program phase, subgroup NOTVERIFIED will become Group PROGRAM while Subgroup VERIFIED will be added to group LOCKOUT.
Similarly, if the program and verify operation is with respect to more than one demarcation threshold voltages, the same considerations apply where no saving is reaped from lockout cells verified relative to a previous demarcation threshold voltage, but there will be power-saving from those verified relative to a current demarcation threshold voltage when there are multiple cycles involved. For example, the invention will reap benefit in a program/verify operation that may include three cycles of program/VerifyA, six cycles of program/verifyAJB, four cycles of program/verifyA/B/C, six cycles of program/verifyB/C and 3 cycles of program/verifyC.
In the program/verifyA cycle, the program inhibited cells will have their bit lines charged up to Vdd in the program phase, and are not discharged at the end of the phase. During the verifyA phase, the bit line of the unprogrammed cells will be discharge by the conducting cells. However the bit lines associated with group VERIFIED will not be discharged. These will remain at Vdd and need not be re-charged at the next pass of the program phase. In the program/verifyA/B cycles, similarly, during the verifyA/B phase, the bit lines of the unprogrammed and �A�-verified cells will discharge by the conducting cells while the B-verified cells will not and need not be re-charged at the next pass of the program phase. Similarly, in the program/verifyA/B/C cycles, the power saving will be on the �C�-verified cells. In the program/verifyB/C cycles, the power saving will be on the �C�-verified cells. In the program/verifyC cycle, the power saving will be on the �C�-verified cells. It has been estimated for a random data pattern, that the power saving is about 25%.
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No. 11/534,307, mailed on Jan. 26, 2007, 12 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8154923 *May 24, 2011Apr 10, 2012Sandisk Technologies Inc.Non-volatile memory and method with power-saving read and program-verify operationsUS8238156 *Mar 10, 2010Aug 7, 2012Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device and method of operating the sameUS8542529Mar 26, 2012Sep 24, 2013Sandisk CorporationNon-volatile memory and method with power-saving read and program-verify operationsUS8995211Apr 23, 2012Mar 31, 2015Sandisk Technologies Inc.Program condition dependent bit line charge rateUS20110222345 *May 24, 2011Sep 15, 2011Yan LiNon-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations* Cited by examinerClassifications U.S. Classification365/185.03, 365/185.22, 365/185.25, 365/185.12, 365/185.33, 365/185.17International ClassificationG11C11/34Cooperative ClassificationG11C2211/5621, G11C11/5642European ClassificationG11C11/56D4Legal EventsDateCodeEventDescriptionNov 5, 2014FPAYFee paymentYear of fee payment: 4May 26, 2011ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:026350/0782Owner name: SANDISK TECHNOLOGIES INC., TEXASEffective date: 20110404RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services