Source: http://www.google.com/patents/US7982522?dq=5,381,459
Timestamp: 2016-08-28 13:01:59
Document Index: 5450559

Matched Legal Cases: ['Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 096109940', 'Application No. 200710088747']

Patent US7982522 - Semiconductor integrated circuit for realizing an amplifier having ringing ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn N-channel transistor is provided as a switch between a high potential power line and a low potential power line. A high-pass filter is constituted by a capacitor and a resistor. When a voltage between the high potential power line and the low potential power line is started to oscillate by a switching...http://www.google.com/patents/US7982522?utm_source=gb-gplus-sharePatent US7982522 - Semiconductor integrated circuit for realizing an amplifier having ringing reduction circuitryAdvanced Patent SearchPublication numberUS7982522 B2Publication typeGrantApplication numberUS 12/690,090Publication dateJul 19, 2011Priority dateMar 22, 2006Fee statusLapsedAlso published asUS20080012632, US20100164590Publication number12690090, 690090, US 7982522 B2, US 7982522B2, US-B2-7982522, US7982522 B2, US7982522B2InventorsNobuaki Tsuji, Hirotaka KawaiOriginal AssigneeYamaha CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (25), Non-Patent Citations (6), Classifications (7), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor integrated circuit for realizing an amplifier having ringing reduction circuitry
US 7982522 B2Abstract
1. A ringing reduction circuit provided inside a semiconductor integrated circuit that includes an output buffer circuit and an output signal line for transmitting an output signal of the output buffer to a load outside the semiconductor integrated circuit, the ringing reduction circuit comprising:
a ringing detector that outputs a signal for turning on the switching element when ringing occurs in the output signal and the output signal exceeds a reference level in a positive or negative direction, wherein the ringing detector comprises a comparator for detecting that the output signal exceeds the reference level in the positive or negative direction by comparing a level of the high-potential power line or the low-potential power line with a level of a power line that is different from the high-potential power line and the low-potential power line and is not part of a path of a switching current flowing through the output buffer circuit.
2. The ringing reduction circuit according to claim 1, wherein
3. The ringing reduction circuit according to claim 1, wherein
4. The ringing reduction circuit according to claim 1, wherein
circuitry for outputting a pulse subjected to pulse width modulation in accordance with a level of an input signal;
an output buffer circuit, responsive to the pulse width modulated pulse, for providing an output signal on an output signal line which is coupled to a load external to the semiconductor integrated circuit; and
a ringing reduction circuit, the ringing reduction circuit including:
a ringing detector that outputs a signal for turning on the switching element when ringing occurs in the output signal and the output signals exceeds a reference level in a positive or negative direction, wherein the ringing detector includes a comparator for detecting that the output signal exceeds the reference level in the positive or negative direction by comparing a level of the high-potential power line or the low-potential power line with a level of a power line than is different from the high-potential power line and the low-potential power line and is not part of a path of a switching current flowing through the output buffer circuit. Description
This application is a divisional of U.S. patent application Ser. No. 11/726,613, filed Mar. 22, 2007, now abandoned, which is based upon, and claims priority from, Japanese Patent Applications Nos. 2006-079771 and 2006-190991, the contents of which are incorporated herein by reference.
In consideration of the circumstances, it is an object of the invention to provide a semiconductor integrated circuit capable of reducing ringing in an output signal without sacrificing operating speed.
According to the invention, when the voltage between the high potential power line and the low potential power line is about to oscillate by a switching operation, the high-pass component of the voltage is given to the switch through the high-pass filter so that the switch is turned ON. Therefore, an oscillating component of the voltage between the high potential power line and the low potential power line is eliminated by use of the switch so that ringing can be reduced.
According to the invention, when ringing occurs in the output signal due to a switching operation of the output buffer circuit to and the output signal exceeds the reference level in the positive or negative direction, the switching element is turned on. As a result, a discharge occurs from the output signal line to the low-potential power line or the high-potential power line and the ringing is thereby reduced.
FIG. 1 is a circuit diagram showing a structure of a class-D amplifier 600 according to a first embodiment of a semiconductor integrated circuit in accordance with the invention. The class-D amplifier 600 has a high potential power terminal 601, a low potential power terminal 602, an input terminal 603, and output terminals 604A and 604B. The high potential power terminal 601 is connected to a positive electrode of a power supply VDD, and the low potential power terminal 602 is connected to a negative electrode of the power supply VDD and is grounded. In the example shown in the drawing, a single power supply is used. For this reason, the low potential power terminal 602 is grounded. In the case in which there is employed such a structure that a power supply for generating a positive source voltage and a power supply for generating a negative source voltage are used, however, it is preferable that the high potential power terminal 601 should be connected to an output terminal of the former power supply and the low potential power terminal 602 should be connected to an output terminal of the latter power supply. An audio signal is received from a sound source (not shown) at the input terminal 603. A load 700, which may include a low-pass filter and a speaker, is connected to the output terminals 604A and 604B.
In the class-D amplifier 600, a PWM modulator 501 is a circuit for outputting a pulse subjected to a pulse width modulation corresponding to a level of an input signal given through the input terminal 603. A predriver 502 is a circuit for driving an output buffer circuit 503 in response to the pulse. In the example shown in the drawing, the output buffer circuit 503 has a so-called bridge structure and is constituted by a transistor pair including a P-channel field effect transistor (hereinafter referred to as a P-channel transistor) 531 P and an N-channel field effect transistor (hereinafter referred to as an N-channel transistor) 531 N which are provided between the high potential power line 611 and the low potential power line 612, and a transistor pair including a P-channel transistor 532P and an N-channel transistor 532N which are provided between the high potential power line 611 and the low potential power line 612. Each of the drains of the P-channel transistor 531 P and the N-channel transistor 531 N is connected to the output terminal 604A and each of the drains of the P-channel transistor 532P and the N-channel transistor 532N is connected to the output terminal 604B. The predriver 502 supplies pulses GP1, GNI, GP2 and GN2 to gates of the transistors 531 P, 531 N, 532P and 532N in order to carry out a conduction to the load 700 for a period corresponding to a width of a pulse supplied from the PWM modulator 501. In order to prevent a so-called through current, moreover, the predriver 502 includes a circuit for regulating a timing of the pulse supplied to the gate of each of the transistors in such a manner that two P-channel transistors and two N-channel transistors (that is, a set of the transistors 531 P and 531 N and a set of the transistors 532P and 532N) connected directly without the load 700 are not turned ON at the same time.
A ringing reducing circuit 504 is peculiar to the embodiment 1. The ringing reducing circuit 504 is constituted by an N-channel transistor 541 and a high-pass filter 542. The N-channel transistor 541 has a drain connected to the high potential power line 611 and a source connected to the low potential power line 612. The N-channel transistor 541 is provided as a switch for causing an oscillating component thereof to be removed and reducing a ringing in the case in which a voltage between the high potential power line 611 and the low potential power line 612 is about to oscillate. In the semiconductor integrated circuit, usually, a transistor having a large size is inserted as an electrostatic breakdown protecting device between the high potential power line and the low potential power line. The N-channel transistor 541 may serve as the electrostatic breakdown protecting device. The high-pass filter 542 is obtained by inserting a capacitor 542A and a resistor 542B in series between the high potential power line 611 and the low potential power line 612, and a voltage on both ends of the resistor 542B is supplied as a gate-source voltage to the N-channel transistor 541. The high-pass filter 542 serves to cause a high-pass component having a certain frequency or more to pass and to provide the high-pass component at the N-channel transistor 541, thereby turning ON the N-channel transistor 541 when the high-pass component is generated on the voltage between the high potential power line 611 and the low potential power line 612. It is preferable that proper values should be selected for a capacitance value of the capacitor 542A and a resistance value of the resistor 542B corresponding to a frequency of a ringing to be reduced. As an example, the capacitor 542A has a capacitance value of 5 pF and the resistor 542B has a resistance value of 50 kΩ.
At a time t2 shown in FIG. 2, next, the P-channel transistor 532P and the N-channel transistor 531N are turned from ON to OFF. Ideally, the P-channel transistor 532P and the N-channel transistor 531N are turned OFF at the same time. In general, however, a shift is generated in a timing in which both of the transistors are turned OFF. As is illustrated in FIG. 3B, when the N-channel 531N is turned OFF in a state in which the P-channel transistor 532P is ON, a path for the source current i passing through the parasitic inductance 621 and a path for the source current i passing through the parasitic inductance 622 are blocked. Therefore, an oscillatory voltage is induced to both ends of the parasitic inductances 621 and 622. In the case in which the load 700 is an inductive load, moreover, a voltage to maintain the source current i flowing to the load 700 until that time is induced to the load 700. Therefore, an oscillatory current flows in a loop constituted by the load 700, a parasitic diode 531D provided between the P-channel transistor 531P and the semiconductor substrate, and the P-channel transistor 532P as shown in the drawing. For this reason, if some countermeasure is not taken, a great oscillation is generated on a voltage between the high potential power line 611 and the low potential power line 612 so that a ringing caused by the oscillation appears on a signal to be output to the load 700.
In the embodiment 1, however, when the oscillating component starts to be generated on the voltage between the high potential power line 611 and the low potential power line 612, it is provided to a gate of the N-channel transistor 541 through the high-pass filter 542 so that the N-channel transistor 541 is turned ON. For this reason, a current corresponding to the oscillating component generated between the high potential power line 611 and the low potential power line 612 flows to the N-channel transistor 541 so that the oscillating component is damped before it is increased. Accordingly, the ringing in the signal to be output to the load 700 is reduced. In the class-D amplifier 600, various switching operations are carried out in addition to the switching operation from the state shown in FIG. 3A to the state shown in FIG. 3B. Also in those cases, however, when the path for the current flowing to the parasitic inductance and the load is blocked and the voltage between the high potential power line 611 and the low potential power line 112 is about to oscillate, a high-pass component of the voltage turns ON the N-channel transistor 541. Consequently, the ringing is reduced.
(2) It is also possible to use the P-channel transistor as a switch for reducing ringing. FIG. 5 shows this example. In this example, a P-channel transistor 543 has a source connected to the high potential power line 611 and a drain connected to the low potential power line 612. A high-pass filter 544 has a resistor 544A and a capacitor 544B inserted in series between the high potential power line 611 and the low potential power line 612 and a voltage on both ends of the resistor 544A is supplied as a gate-source voltage to the P-channel transistor 543. Also in this manner, it is possible to obtain the same advantages as those in the embodiment 1.
The class-D amplifier 100A is a semiconductor integrated circuit in which the individual circuits shown in FIGS. 6 and 7 are formed on a semiconductor substrate and sealed in a package. A high-potential power line 111 which is connected to the high-potential power terminal 101 and a low-potential power line 112 which is connected to the low-potential power terminal 102 are formed on the semiconductor substrate. A power supply current is supplied from the power source VDD to the individual circuits constituting the class-D amplifier 100A via the high-potential power line 131, the high-potential power terminal 101, a parasitic inductance 141 of a lead, a bonding wire etc., and the high-potential power line 111. A power supply current that has passed through the individual circuits goes to the negative pole of the power source VDD via the low-potential power line 112, a parasitic inductance 142 of a lead, a bonding wire, etc., the low-potential power terminal 102, and the low-potential power line 132.
In the class-D amplifier 100A, a PWM modulator 10 is a circuit for outputting pulse-width-modulated pulses in accordance with the level of an input signal that is supplied via the input terminal 103. A predriver 20 is a circuit for driving an output buffer circuit 30 according to those pulses. In the illustrated example, the output buffer circuit 30 is a circuit having what is called an inverter structure and is composed of a p-channel field-effect transistor (hereinafter referred to simply as “p-channel transistor”) 30P and an n-channel field-effect transistor (hereinafter referred to simply as “n-channel transistor”) 30N which are inserted between the high-potential power line 111 and the low-potential power line 112. The drains of the p-channel transistor 30P and the n-channel transistor 30N are connected to each other and their connecting point is connected to the output terminal 104 via an output signal line 120. The predriver 20 supplies pulses GP and GN to the gates of the respective transistors 30P and 30N so that the load 200 is energized in periods corresponding to the pulse widths of the pulses supplied from the PWM modulator 10. To prevent what is called a flow-through current, the predriver 20 includes a circuit for performing timing adjustment to the pulses to be supplied to the gates of the respective transistors 30P and 30N so that the transistors 30P and 30N are not turned on simultaneously.
The ringing reduction circuits 40NA and 40PA are circuits that are unique to the embodiment 2. As shown in FIG. 6, the ringing reduction circuit 40NA is composed of an n-channel transistor 401 as a switching element and a comparator 410 as a ringing detector. The drain of the transistor 401 is connected to the output signal line 120 which transmits an output signal OUT of the output buffer circuit 30 to the external load 200, and the source of the transistor 401 is connected to the low-potential power line 112 of the high-potential power line 111 and the low-potential power line 112 which supply a power supply voltage to the output buffer circuit 30. The comparator 410 has p-channel transistors 411 and 412 and constant current sources 413 and 414. The source of the transistor 411 serves as a non-inverting input terminal (plus terminal) of the comparator 410 and is connected to the output signal line 120. The source of the transistor 412 serves as an inverting input terminal (minus terminal) of the comparator 410 and is connected to the high-potential power line 111. The gates of the transistors 411 and 412 are connected to the drain of the transistor 412, and the drain of the transistor 412 is connected to the low-potential power line 112 via the constant current source 414. The drain of the transistor 411 is connected to the low-potential power line 112 via the constant current source 413. The connecting point of the drain of the transistor 411 and the constant current source 413 serves as an output terminal of the comparator 410 and is connected to the gate of the transistor 401. Having the above configuration, the comparator 410 compares the output signal OUT to be supplied to the load 200 via the output signal line 120 with the level PVDDI (reference level) of the high-potential power l7ine 111. If the output signal OUT exceeds the reference level in the positive direction (occurrence of an overshoot), the comparator 410 supplies an H-level gate voltage to the transistor 401 and thereby turns on the transistor 401 which is the switching element.
In view of the above, in the embodiment 3, as shown in FIGS. 9 and 10, the class-D amplifier 100B is provided with a high-potential power terminal 101 a and a low-potential power terminal 102 a separately from the high-potential power terminal 101 and the low-potential power terminal 102 for supplying the power supply voltage to the individual circuits including the output buffer circuit 30. The high-potential power terminal 101 a and the low-potential power terminal 102 a are connected to the positive pole and the negative pole of the power source VDD, respectively. The comparator 410 of the ringing reduction circuit 40NB detects an overshoot in the output signal OUT by comparing the output signal OUT with the level PVDDIa of a high-potential power line 111 a which is connected to the high-potential power terminal 101 a. The comparator 420 of the ringing reduction circuit 40PB detects an undershoot in the output signal OUT by comparing the output signal OUT with the level PVSSIa of a low-potential power line 112 a which is connected to the low-potential power terminal 102 a. The ringing reduction circuit 40NB is configured in such a manner that a p-channel transistor 431 and a non-inverting buffer 432 are added to the ringing reduction circuit 40NA of the above-described embodiment 2. The source of the transistor 431 is connected to the output signal line 120 and its gate and the drain are connected to the source of the transistor 411. The transistor 431 serves to lower the sensitivity of the comparator 410 so that the comparator 410 does not react too sensitively to a subtle oscillation that is too small to be called an overshoot when it occurs in the output signal OUT. Likewise, an n-channel transistor 433 for lowering the sensitivity of the comparator 420 is added to the ringing reduction circuit 40PB. The non-inverting buffer 432 serves to generate a gate voltage being of such a level as to allow the transistor 401 to be switched on/off reliably.
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