Source: http://www.google.com/patents/US7351991?ie=ISO-8859-1&dq=6,232,546
Timestamp: 2014-10-23 03:13:03
Document Index: 474227334

Matched Legal Cases: ['Application No. 2003', 'art 319', 'art 319', 'art 319', 'art 319', 'art 319', 'art 319', 'art 319', 'art 325', 'art 325', 'art 325', 'art 325', 'art 325', 'art 319', 'art 325', 'art 319', 'art 325', 'art 325', 'art 319', 'art 319', 'art 319', 'art 325', 'art 325', 'art 325', 'art 325', 'art 319', 'art 319', 'art 319']

Patent US7351991 - Methods for forming phase-change memory devices - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsPhase-change memory devices include a phase-change material layer and a first electrode having a contact area therebetween. The contact area extends into a recess of the first electrode to provide current density concentration....http://www.google.com/patents/US7351991?utm_source=gb-gplus-sharePatent US7351991 - Methods for forming phase-change memory devicesAdvanced Patent SearchPublication numberUS7351991 B2Publication typeGrantApplication numberUS 11/413,318Publication dateApr 1, 2008Filing dateApr 28, 2006Priority dateApr 2, 2003Fee statusPaidAlso published asUS7067837, US20040195604, US20060211165Publication number11413318, 413318, US 7351991 B2, US 7351991B2, US-B2-7351991, US7351991 B2, US7351991B2InventorsYoung-Nam Hwang, Young-Tae KimOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (7), Classifications (22), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMethods for forming phase-change memory devicesUS 7351991 B2Abstract Phase-change memory devices include a phase-change material layer and a first electrode having a contact area therebetween. The contact area extends into a recess of the first electrode to provide current density concentration.
1. A method for fabricating a phase-change memory device comprising:
forming a first insulation layer having a first opening therein on an integrated circuit substrate;
forming a first electrode on the first insulation layer, the first electrode including a recess in an upper portion thereof in the first opening; and
forming a phase-change material layer on the first electrode and extending into the recess, wherein the recess tapers away from the phase-change material layer.
2. A method for fabricating a phase-change memory device comprising:
forming a first electrode on the first insulation layer, the first electrode having a vertical part including a recess in an upper portion thereof in the first opening; and
forming a phase-change material layer on the first electrode and extending into the recess, wherein:
forming a first insulation layer includes patterning the first insulation layer to form the first opening, the first opening including a top opening defined by a sloped upper sidewall part and a bottom opening defined by a substantially vertical bottom sidewall part;
forming a first electrode includes forming a conformal first electrode layer along the first insulation layer and the first opening to have a recessed slope part in the first opening;
forming a phase-change material layer comprises:
forming a second insulation layer on the first electrode layer;
patterning the second insulation layer to have a second opening exposing the recessed slope part of the first electrode layer; and
forming a phase-change material layer on the second insulation layer to fill the second opening, the method further comprising:
forming a second electrode layer on the phase-change material layer; and
sequentially patterning the second electrode layer, the phase-change material layer, the second insulation layer and the first electrode layer.
3. The method for fabricating the phase-change memory device of claim 2, wherein patterning the first insulation layer comprises:
forming an etching mask on the first insulation layer;
isotropic etching a partial thickness of the first insulation layer exposed by the etching mask to form the top opening; and then
anisotropic etching a remainder of the first insulation layer exposed by the etching mask to form a bottom opening.
4. The method for fabricating the phase-change memory device of claim 2, wherein patterning the first insulation layer comprises:
forming an etching mask on the first insulating layer;
anisotropic etching the first insulation layer exposed by the etching mask to form a temporary bottom opening having diameter of the bottom opening on the first insulation layer; and then
isotropic etching a partial thickness of the first insulation layer defining the top of the temporary bottom opening to form the top opening, wherein a residual temporary bottom opening corresponds to the bottom opening.
5. The method for fabricating the phase-change memory device of claim 3, wherein the first insulation layer is formed by sequentially stacking a silicon oxynitride layer and a silicon oxide layer, and wherein the top opening is formed in the oxide silicon layer, and wherein the bottom opening is formed in the silicon oxynitride layer.
6. The method for fabricating the phase-change memory device of claim 4, wherein the first insulation layer is formed by sequentially stacking a silicon oxynitride layer and a silicon oxide layer and wherein the top opening is formed in the oxide silicon layer, and wherein the bottom opening is formed in the silicon oxynitride layer.
7. The method for fabricating the phase-change memory device of claim 2, wherein the second opening is formed to have a diameter smaller than a diameter of the bottom opening of the first opening.
8. The method for fabricating the phase-change memory device of claim 2, further comprising:
forming a silicon oxynitride layer and a silicon oxide layer on the second electrode layer, after forming the second electrode layer; and
patterning the silicon oxide layer and the silicon oxynitride layer while patterning the second electrode layer, the phase-change material layer, the second insulation layer and the first electrode layer.
9. The method for fabricating the phase-change memory device of claim 8, further comprising:
before forming the first insulation layer:
forming a transistor on the semiconductor substrate;
forming a first interlayer dielectric layer to cover the transistor on the semiconductor substrate; and
forming a contact pad electrically connected to a source region of the transistor and a first interconnection connected to a drain region of the transistor, and after patterning the oxide layer, the nitride oxide layer, the second electrode layer, the phase-change material layer, the second insulation layer and the first electrode layer:
forming a protection insulation layer;
forming a second interlayer dielectric layer on the protection insulation layer;
patterning the second interlayer dielectric layer, the protection insulation layer, the patterned silicon oxide layer and the patterned silicon oxynitride layer to form a via hole exposing the patterned second electrode layer;
filling the via hole with a conductive material; and
forming a second interconnection on the second interlayer dielectric layer and the conductive material.
10. A method for fabricating a phase-change memory device, comprising:
patterning the first insulation layer to form a temporary opening;
forming an insulation layer spacer on a sidewall of the temporary opening, the insulation layer spacer defining a first opening comprised of a top opening defined by a sloped-top lateral part and a bottom opening defined by a vertical-bottom-lateral part;
forming a first electrode layer along the first opening and the first insulation layer to have a recessed slope part in the first opening;
patterning the second insulation layer to have a second opening exposing the recessed slope part of the first electrode layer;
forming a phase-change material layer in the second opening and on the second insulation layer;
11. The method for fabricating the phase-change memory device of claim 10, wherein the second opening is formed to have a diameter smaller than a diameter of the bottom opening of the first opening.
12. The method for fabricating the phase-change memory device of claim 10, further comprising:
forming a silicon oxynitride layer and an silicon oxide layer on the second electrode layer after forming the second electrode layer; and
patterning the silicon oxide layer and silicon oxynitride layer while sequentially patterning the second electrode layer, the phase-change material layer, the second insulation layer and the first electrode layer.
13. The method for fabricating the phase-change memory device of claim 12, further comprising:
forming a contact pad electrically connected to a source region of the transistor and a first interconnection connected to a drain region of the transistor, and
after sequentially patterning the silicon oxide layer, the silicon oxynitride layer, the second electrode layer, the phase-change material layer, the second insulation layer and the first electrode layer:
patterning the second interlayer dielectric layer, the protection insulation layer, the patterned oxide silicon layer and the silicon oxynitride layer to form a via hole exposing the patterned second electrode layer;
CLAIM OF PRIORITY This application claims priority to and is a divisional of parent application Ser. No. 10/814,670, filed Mar. 31, 2004, now issued as U.S. Pat. No. 7,067,837, which claims the benefit from Korean Patent Application No. 2003-20755, filed on Apr. 2, 2003, in the Korean Intellectual Property Office, the disclosures of which are hereby incorporated herein by reference.
BACKGROUND OF THE INVENTION The present invention relates to integrated circuit (semiconductor) memory devices and more specifically, to phase-change memory devices and methods for forming the same.
Semiconductor memory devices are generally classified as volatile memory devices or as non-volatile memory devices, based on whether data can be maintained when power to the device is turned off. Examples of a volatile memory device include a dynamic random access memory (DRAM) or a static random access memory (SRAM). An example of a non-volatile memory device is a FLASH memory. In such memory devices, stored binary information, having a �0� or a �1� state, may be determined by sensing a stored charge in a memory cell.
SUMMARY OF THE INVENTION Embodiments of the present invention provide phase-change memory devices that include a phase-change material layer and a first electrode having a contact area therebetween. The contact area extends into a recess of the first electrode to provide current density concentration adjacent thereto (i.e., an increase as compared to a flat contact area). The portion of the phase-change material layer extending into the recess of the first electrode may be a tapering tip of a vertical part of the phase-change material layer that contacts the first electrode at the contact area. The tapering tip of the vertical part may be �V� shaped.
In other embodiments of the present invention the phase-change material layer also includes a horizontal part extending above the vertical part and the phase-change memory device further includes a second electrode on the horizontal part. The first electrode may include a recessed slope part contacting the tip of the vertical part and a horizontal part extending from the recessed slope part and separated from the horizontal part of the phase-change material layer by an insulation layer.
In other embodiments of the present invention, phase-change memory devices include a semiconductor substrate and a first insulation layer on the semiconductor substrate. The first insulation layer has a first opening defined by an upper sloped sidewall part and a bottom vertical sidewall part extending from the upper sloped sidewall part. A first electrode is disposed in the first opening and on the first insulation layer. The first electrode has a recessed slope part in the first opening and a horizontal part on the first insulation layer outside of the first opening. A second insulation layer is on the first electrode. The second insulation layer has a second opening that exposes the recessed slope part of the first electrode. A phase-change material layer is disposed in the second opening and on the second insulation layer and a second electrode is on the phase-change material layer. The recessed slope part of the first electrode may be substantially �V� shaped.
BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a further understanding of the invention and incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention.
DETAILED DESCRIPTION OF THE INVENTION The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the relative sizes of regions may be exaggerated for clarity. It will be understood that when an element is referred to as being �attached�, �connected,� �on� or �coupled� to another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being �directly attached,� �directly connected,� �directly on� or �directly coupled� to another element, there are no intervening elements present. Like numbers refer to like elements throughout the specification. As used herein the term �and/or� includes any and all combinations of one or more of the associated listed items.
Furthermore, relative terms, such as �lower� or �bottom� and �upper� or �top,� may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as being on the �lower� side of other elements would then be oriented on �upper� sides of the other elements. The exemplary term �lower�, can therefore, encompasses both an orientation of �lower� and �upper,� depending of the particular orientation of the figure.
The first insulation layer 315 may include a sequentially stacked silicon oxynitride layer (SiON) 311 and oxide silicon layer (SiO2) 313. In such embodiments, the top opening 317U of the first opening 317 may be formed in the oxide silicon layer 313 and the bottom opening 317L of the first opening 317 may be formed in the silicon oxynitride layer 311 as shown in FIG. 3B. As illustrated in FIG. 3B, the top opening 317U of the first opening 317 slopes and provides the first electrode 319 a recessed top surface. In other words, the first electrode 319 includes the horizontal part 319H and the recessed slope part 319S. The recessed slope part 319S is placed in the first opening 317 and the horizontal part 319H is placed on the first insulation layer 315 outside of the first opening 317. The top surface 319Hh of the horizontal part 319H of the first electrode 319 is illustrated as flat and the top surface 319Ss of the slope part 319S is sloped. As a result, the top surface 319Ss of the slope part 319S has a �V� shaped configuration.
The phase-change material layer 325 is shown as being disposed on the second insulation layer 321 and filling the second opening 323. As a result, the contact area 320 between the phase-change material layer 325 and the first electrode 319 is formed in a sharp, in particular, �V,� shape. More specifically, referring to FIG. 3B, the phase-change material layer 325 includes the horizontal part 325H and the vertical part 325V. The horizontal part 325H is placed on the second insulation layer 321. The vertical part 325V extends from the horizontal part 325H and is in contact with the top surface 319Ss of the recessed slope part 319S of the first electrode 319. The tip of the vertical part 325V of the phase-change material layer 325 in the embodiments of FIG. 3B has a conical or �V� shape defined by the recessed slope part 319S of the first electrode 319. In other words, the vertical part 325V of the phase-change material layer 325 includes the vertical sidewall 325Vv and the slope sidewall 325Ss. The vertical sidewall 325Vv is vertical to the horizontal part 325H of the phase-change material layer 325 and the slope sidewall 325Ss defines a sharp tip of the phase-change material layer 325 extending into the lower electrode 319. Thus, FIG. 3B illustrates embodiments of the present invention where a phase-change material layer and a first electrode have a contact area therebetween that extends into a recess (shown as �V� shaped in FIG. 3B) of the first electrode to provide increased current density adjacent thereto as compared to a flat contact area.
The phase-change material layer 325 may be a compound of at least one material having chalcogen elements, such as Te, Se, and/or at least one material selected from the group including or consisting of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P and/or O. In other words, the phase-change material layer 325 may include Ge�Sb�Te, As�Sb�Te, As�Ge�Sb�Te, Sn�Sb�Te, 5A group-Sb�Te, 6A group-Sb�Te, 5A group-Sb�Se and/or 6A group-Sb�Se.
As the contact area 320 between the phase-change material layer 325 and the first electrode 319 has a sharp profile, shown as �V� shaped in FIG. 3B, a current pulse supplied through the first electrode 319 generally flows in the direction indicated by the arrows is FIG. 3B. Accordingly, current density may be concentrated in the conical or �V� shaped tip of the phase-change material layer 325. As a result, the program current may be reduced. As shown in the embodiments of FIG. 3B, the program volume 300 may have a generally conical shape.
Referring now to to FIG. 5, a transistor including a gate electrode 503, a source region 505 s and a drain region 505 d is formed, for example, by a conventional metal on semiconductor field effect transistor (MOSFET) technique on an integrated circuit (semiconductor) substrate 501. The gate electrode 503 shown in FIG. 5 is formed on the semiconductor substrate 501 and extends in a direction into and out of the figure. The source and drain regions 505 s and 505 d are formed on the substrate 501 on the sides of the gate electrode 503, that is, in an active region. A gate insulation layer 503′ is disposed between the gate electrode 503 and the substrate 501.
Referring to FIG. 9, after removing the first etching mask 611, a first electrode layer 319 is formed in the first opening 317 and on the first insulation layer 315. As a diameter of the top of the first opening 317, that is, the top opening 317U, becomes gradually decreased, the first electrode layer 319 has a recessed slope part 319S in the first opening 317. The recessed slope part 319S has a concave, more particularly, �V� shape. In other words, the configuration of the top surface 319Ss of the recessed slope part 319S has a concave shape. The first electrode 319 may be formed of a conductive material containing a nitride element, a conductive material containing a carbon element, titanium, tungsten, molybdenum, tantalum, titanium silicide, tantalum silicide and/or a combination thereof. The first electrode 319 may be formed by deposition methods, such as chemical vapor deposition (CVD), plasma vapor deposition (PVD) and/or atomic layer deposition (ALD). The conductive material containing a nitride element may be one or more of titan nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), niobium nitride (NbN), silicon titanium nitride (TiSiN), aluminum titan nitride (TiAlN), boron titan nitride (TiBN), silicon zirconium nitride (ZrSiN), silicon tungsten nitride (WsiN), boron tungsten nitride (WBN), aluminum zirconium nitride (ZrAlN), silicon molybdenum nitride (MoSiN), aluminum molybdenum nitride (MoAlN), silicon tantalum nitride (TaSiN), aluminum tantalum nitride (TaAlN), oxy titan nitride (TiON), oxy aluminum titan nitride (TiAlON), oxy tungsten nitride (WON) and/or oxy tantalum nitride (TaON).
Referring now to FIG. 12, after removing the second etching mask 613, a phase-change material layer 325 and a second electrode layer 327 may be sequentially formed. The phase-change material layer 325 may be formed on the second insulating layer 321 and filling the second opening 323. Thus, the phase-change material layer 323 includes a vertical part 325V and a horizontal part 325H. The vertical part 325V fills the second opening 323 and the horizontal part 325H is on the second insulation layer 321. As shown in FIG. 12, the contact area 320 between the first electrode 319 and the phase-change material layer 325 has a concave, more particularly, �V� or �cone� shaped profile.
The phase-change material layer 325 may be a compound of at least one material having chalcogen elements, such as Te and/or Se, and at least one material selected from the group including Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P and/or O. In other words, the phase-change material layer 325 may include Ge�Sb�Te, As�Sb�Te, As�Ge�Sb�Te, Sn�Sb�Te, 5A group-Sb�Te, 6A group-Sb�Te, 5A group-Sb�Se and/or 6A group-Sb�Se.
In some embodiments of the present invention, the first opening 317 (FIG. 8) is formed by sequentially performing isotropic etching and anisotropic etching. However, this etching order can be reversed in other embodiments. That is, as shown in FIG. 15, the first insulation layer 315 exposed by the first etching mask 611 may be anisotropically etched to form a temporary bottom opening 317L′. As shown in FIG. 16, after forming the temporary bottom opening 317L′, an isotropic etching process may be performed to slope the top of the temporary bottom opening 317L′. As a result, the first opening 317 composed of the top opening 317U and the bottom opening 317L′ is formed. A diameter of the top opening 317U gradually decreases and the bottom opening 317L corresponds to the bottom of the temporary bottom opening 317L′.
Referring to FIG. 19, a first electrode layer 319 and a second electrode layer 321 may be sequentially formed on the first opening 317 and the first insulation layer 315. As previously described, the first electrode 319 may have a recessed slope part 319S. The configuration of the top surface 319Ss of the recessed slope part 319S may be concave, more particularly, �V� shaped. After forming the second etching mask 613 on the second insulation layer 321, the second exposed insulation layer 321 may be anisotropic etched to form a second opening 323 exposing the recessed slope part 319S of the first electrode 319.
As previously discussed, as the contact area of the first electrode and the phase-change material layer is formed with a concave, sharp or �V� shaped configuration, a current density can be integrated, which may reduce current required during programming.
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