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Timestamp: 2020-05-29 14:36:04
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Matched Legal Cases: ['art 1', 'art 2', 'art 3', 'art 4', 'art 5', 'art 6']

Programmable universal signaling circuit for a telephone network - XEL Communications, Inc.
Programmable universal signaling circuit for a telephone network
United States Patent 5151935
A programmable universal signaling circuit for use in a universal channeling unit of a telephone network. The programmable universal signaling circuit uses a line converter and decoder circuit which under control of a microprocessor generates a unique set of configuration signals for configuring the universal signaling circuit into one of a plurality of standard signaling telephone circuits. The universal signaling circuit can be reconfigured either at the location of the universal channel unit or remotely.
Slife, Jimmy D. (Aurora, CO)
Farrell, David (Lafayette, CO)
07/609083
XEL Communications, Inc. (Aurora, CO)
379/240
370/359, 379/269
H04J3/12; H04M3/00; H04M7/00; H04Q1/30; H04Q11/04; (IPC1-7): H04J3/12; H04M7/10
379/229, 379/230, 379/234, 379/235, 379/240, 379/201, 379/269, 370/62, 370/56, 370/58.3, 370/58.2, 370/110.1
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4734935 Communication system with remotely controllable signal receiving means 1988-03-29 Toudo 379/236
4636584 Signaling protocol channel unit 1987-01-13 Bimkerd et al. 379/240
4307461 Call processor for a satellite communications controller 1981-12-22 Brickman et al. 379/269
4247740 Trunk interface circuit 1981-01-27 Auderson et al. 379/124
ROBERT C. DORR (DORR, CARSON, SLOAN & PETERSON 3010 EAST SIXTH AVE., DENVER, CO, 80206, US)
1. A programmable universal signaling circuit (180) for use in a universal channel unit (40) of a telephone network; said universal channel unit having: A, B, E, M SB, and SG telephone network signaling paths, a microprocessor (190) and a PCM interface (170); said PCM interface being connected to a PCM bus (50), said programmable universal signaling circuit comprising:
means (200) connected to said microprocessor and receptive of data from said microprocessor for generating a unique set of configuration signals corresponding to said received data, said generating means further generating a plurality of different sets of configuration signals corresponding to a plurality of different data received from said microprocessor,
first means (210) connected to said generating means, to said microprocessor, and to said A and B signaling paths for selectively configuring to function as a preselected one of a number of loop circuits, said first generating means being receptive of a first portion of said unique set of configuration signals to configure into said preselected one of said number of loop circuits so as to provide A and B signals over said A and B signaling paths necessary for said preselected one loop circuit, said first configuring means delivering the sensed loop current value or loop voltage value for said A and B signaling paths to said microprocessor, and
second means (220) connected to said generating means, to said microprocessor, and to said E, M, SG, and SB signaling paths for selectively configuring to function as a preselected one of a number of E & M circuits, said second configuring means being receptive of a second portion of said unique set of configuration signals to configure into said preselected one of said number of E & M circuits so as to provide E, M, SB, and SG signals over said E, M, SB and SG signaling paths necessary for said selected one E & M circuit, said second configuring means further delivering the sensed E & M current value or E & M voltage value for said E & M signaling paths to said microprocessor.
2. The programmable universal signaling circuit of claim 1 wherein said generating means comprises:
a line converter (202) connected to said microprocessor to receive said data from said microprocessor,
a decoder (204) connected to the outputs of said line converter for decoding a predetermined number of said outputs of said line converter, and
said unique set of configuration signals being generated from the outputs of said decoder.
3. The programmable universal signaling circuit of claim 1 wherein said first configuring means comprises:
means (320) connected to said generating means, to said microprocessor and to said A and B signaling paths for sensing said loop current or loop voltage for said A and B signaling paths, said sensing means being selectively activated by said first portion of said unique set of configuration signals from said generating means to deliver said sensed loop current value or loop voltage value to said microprocessor.
4. The programmable universal signaling circuit of claim 1 wherein said first configuring means comprises:
a battery feed circuit (333),
a plurality of switches, each of said switches being selectively activated by said first portion of said unique set of configuration signals from said generating means, said plurality of switches at least comprising:
(a) an A ground switch (322) for selectively connecting said A signaling path to ground,
(b) an A battery switch (326) for selectively connecting said A signaling path to said battery feed circuit,
(c) a B ground switch (325) for selectively connecting said B signaling path to ground,
(d) a B battery switch (334) for selectively connecting said B signaling path to said battery feed circuit,
(e) a loop switch (323) for selectively connecting said A and B signaling paths together,
(f) a B ringing switch (329) for selectively connecting ringing to the B signaling path,
(g) a 20 volt DX source, and
(h) a B 20 volt switch for selectively connecting said 20 volt DX source to said B signaling path.
5. The programmable universal signaling circuit of claim 1 wherein said second configuring means comprises:
means (308) connected to said microprocessor and to said E signaling path for sensing current in said E signaling path, said E current sensing means delivering the value of the said sensed E current to said microprocessor, and
means (318) connected to said microprocessor and to said M signaling path for sensing current in said M signaling path, said M current sensing means delivering the value of said sensed M current to said microprocessor.
6. The programmable universal signaling circuit of claim 1 wherein said second configuring means comprises:
a minus 48 volt battery (314),
a plurality of switches, each of said switches being collectively activated by said second portion of said unique set of configuration signals from said generating means, said plurality of switches at least comprising:
(a) an E battery switch (309) for selectively connecting said minus 48 volt battery to said E signaling path,
(b) an M battery switch (317) for selectively connecting said minus 48 volt battery to said M signaling path,
(c) an SB battery switch (310) for selectively connecting said minus 48 volt battery to said SB signaling path,
(d) an E to SG switch (306) for selectively connecting said E signaling path to said SG signaling path,
(e) an SG ground switch (307) for selectively connecting ground to said SG signaling path,
(f) an E ground switch (306) for selectively connecting ground to said E signaling path,
(g) an SB ground switch (319) for selectively connecting ground to said SB signaling path,
(h) an M to SB switch (311) for selectively connecting said M signaling path to said SB signaling path,
(i) an M to SG switch (312) for selectively connecting said M signaling path to said SG signaling path,
(j) an M ground switch (313) for selectively connecting ground to said M signaling path, and
(k) an M detector switch (315) for selectively connecting said M signaling path to either ground or said minus 48 volt battery directly or through a predetermined resistance.
7. The programmable universal signaling circuit of claim 1 wherein said second configuring means comprises an A to SG switch (304) for selectively connecting said SG signaling path to said A signaling path in response to said second portion of said unique set of configuration signals from said generating means for operation in a tandem mode.
8. A programmable universal signaling circuit (180) for use in a universal channel unit (40) of a telephone network; said universal channel unit having: A, B, E, M, SB, and SG telephone network signaling paths, a microprocessor (190) and a PCM interface (170); said PCM interface being connected to a PCM bus (50), said programmable universal signaling circuit comprising:
means (200) connected to said microprocessor and receptive of data from said microprocessor for generating a unique set of configuration signals corresponding to said received data, said generating means further generating a plurality of different sets of configuration signals corresponding to a plurality of different data received from said microprocessor, said generating means comprising:
(i) a line converter (202) connected to said microprocessor to receive said data from said microprocessor,
(ii) a decoder (204) connected to the outputs of said line converter for decoding a predetermined number of said outputs of said line converter, and
(iii) a plurality of different sets of configuration signals corresponding to a plurality of different data received from said microprocessor, said unique set of configuration signals being generated from the outputs of said decoder,
first means (210) connected to said line converter and said decoder, to said microprocessor, and to said A and B signaling paths for selectively configuring to function as a preselected one of a number of loop circuits, said first configuring means being receptive of a first portion of said unique set of configuration signals to configure into said preselected one of said number of loop circuits so as to provide A and B signals over said A and B signaling paths necessary for said preselected one loop circuit, said first configuring means delivering the sensed loop current value or loop voltage value for said A and B signaling paths to said microprocessor, said first configuring means comprising:
(i) a battery feed circuit (333),
(ii) a plurality of switches, each of said switches being selectively activated by said first portion of said unique set of configuration signals, said plurality of switches at least comprising:
(h) a B 20 volt switch for selectively connecting said 20 volt DX source to said B signaling path, and
second means (220) connected to said line converter and said decoder, to said microprocessor, and to said E, M, SG, and SB signaling paths for selectively configuring to function as a preselected one of a number of E & M circuits, said second configuring means being receptive of a second portion of said unique set of configuration signals to configure into said preselected one of said number of E & M circuits so as to provide E, M, SB, and SG signals over said E, M, SB and SG signaling paths necessary for said selected one E & M circuit, said second configuring means delivering the sensed E & M current value or E & M voltage value for said E & M signaling paths to said microprocessor, said second configuring means comprising:
(i) a minus 48 volt battery (314),
(ii) a plurality of switches, each of said switches being collectively activated by said second portion of said unique set of configuration signals from said generating means, said plurality of switches at least comprising:
(f) an E ground switch (308) for selectively connecting ground to said E signaling path,
9. The programmable universal signaling circuit of claim 8 wherein said second configuring means also comprises an A to SG switch (304) for selectively connecting said SG signaling path to said A signaling path in response to said second portion of said unique set of configuration signals for operation in a tandem mode.
10. The programmable universal signaling circuit of claim 8 wherein said first configuring means comprises:
means (320) connected to said line converter and said decoder, to said microprocessor and to said A and B signaling paths for sensing said loop current or loop voltage for said A and B signaling paths, said sensing means being selectively activated by said first portion of said unique set of configuration signals to deliver said sensed loop current value or loop voltage value to said microprocessor.
11. The programmable universal signaling circuit of claim 8 wherein said second configuring means comprises:
means (308) connected to said microprocessor and to said E signaling path for sensing current in said E signaling path, said E current sensing means delivering the value of said sensed E current to said microprocessor, and
The programmable universal signaling circuit of the present invention is used in a universal channel unit of a telephone network. Conventional A, B, E, M, SB, and SG telephone network signaling paths exist within the universal channel unit as well as microprocessor and a PCM interface which is connected to a PCM bus.
FIG. 1 sets forth a block diagram illustrating the installation of the Universal Signaling Circuit of the present invention in a telephone network;
FIG. 1 sets forth a general representation of a telephone network. A telephone or other Network Communication Terminating Equipment (NTCE) 10 may be connected to a standard metallic interface 20. Likewise, a central office or private branch exchange (PBX) 30 may also be connected to the standard metallic interface 20. The metallic interface 20 is connected to a channel bank, not shown, which comprises a number of universal channel units (UCUs) 40 such as 24 to 48.
Telephony Terms:
2W Two-Wire
4W Four-Wire
OFH Off-Hook
ONH On-Hook
PBX or PABX
Private Branch Exchange or Private Automatic
NCTE Network Communication Terminating Equip-
The Six Primary Signaling Lines:
1. A A signaling lead - Normally providing a ground
connection to Tip
1. Tip Tip Signaling Lead - Normally thought of as a
2. B B signaling lead - Normally providing a battery
connection to Ring
2. Ring Ring Signaling Lead - Normally thought of as a
3. E Ear Lead in E&M Signaling
4. M Mouth Lead in E&M Signaling
5. SG Signal Ground Lead in E&M Signaling
6. SB Signal Battery Lead in E&M Signaling
Common Prefixes and Suffixes:
TO Transmission Only (no Signaling)
ETO Equalization and Transmission Only (no Signal-
GT Gain Transfer
LS Loop Start Signaling Protocol
GS Ground Start Signaling Protocol
In-Band (in the voice band) Signaling Mode:
SF Single Frequency (2600 Hz), In-Band Signaling
E&M Signaling Modes:
PLR Pulse Link Repeater (e.g. PLR-1, PLR-2,
PLR-3)
E&M Ear and Mouth Signaling (e.g. E&M-1, E&M-2,
E&M-3)
TDM Tandem Signaling
Loop Signaling Modes:
LSFXS Loop Start Foreign Exchange - Station Side
GSFXS Ground Start Foreign Exchange - Station Side
LSFXO Loop Start Foreign Exchange - Office Side
GSFXO Ground Start Foreign Exchange - Office Side
PLAR Private Line Automatic Ring Down
FX/RD Foreign Exchange Ring Down Signaling Mode
DX Duplex Signaling
DXN Duplex Signaling - Normal Battery
DXR Duplex Signaling - Reverse Battery
DPO Dial Pulse Originate Signaling
DPT Dial Pulse Terminate Signaling
T-1 Signaling Leads:
Ra Receive A Channel, usually for On-Hook/Off-
Rb Receive B Channel, usually for ringing
Ta Transmit A Channel, usually for On-Hook/Off-
Tb Transmit B Channel, usually for ringing
R Det Ring Detect
Batt Battery Voltage, usually -48 vdc
RngGnd Ring Lead Ground
BSense Battery connection thru 3KΩ sense resistor
GSense Ground connection thru 3KΩ sense resistor
Batt-CL Battery Source thru 50 ma current limiter
Vrms Volts, root-mean-square. Measure of AC voltage
ma or mA milli Ampheres of electrical current
The details of the universal signaling circuit 180 of the present invention is set forth in FIG. 2. In FIG. 2, a serial to parallel convert and decode circuit 200 is interconnected with the loop circuits 210 and with the E & M circuits 220. The serial to parallel convert and decode circuit 200 receives data, clock, and strobe signals over lines 186 from the microprocessor 190. The serial to parallel convert and decode circuit 200 is further interconnected over lines 230 to the loop circuits 210 and over lines 240 to the E & M circuits 220. The loop circuits 210 provide the A and B signaling path outputs to the transmit and receive voice paths 130 and a loop sensor signal 184 to the microprocessor 190. The E & M circuits 220 provide the E, M, SG, and SB signaling path outputs to the metallic interface 20 and the E sensor 184b and the M sensor 184c signals to the microprocessor 190.
Signaling Lead Connections versus Mode and State Mode/State A Lead B Lead E Lead M Lead SB Lead SG Lead
2W-Disconnect (Safe)
4W-Disconnect (Safe)
2W-FX/RD and PLAR1&2
Gnd Batt Open
2W-PLAR/RD-Idle Gnd Batt Open
2W-PLAR/RD-Ringing
Gnd Ringing
2W-PLAR/RD-Busy Gnd Batt Open
4W-FX/RD and PLAR1&2
4W-PLAR/RD-Idle Gnd Batt Open
4W-PLAR/RD-Ringing
4W-PLAR/RD-Busy Gnd Batt Open
2W-LSFXS-Idle Gnd Batt Open
2W-LSFXS-Ringing
2W-LSFXS-Busy Gnd Batt Open
4W-LSFXS-Idle Gnd Batt Open
4W-LSFXS-Ringing
4W-LSFXS-Busy Gnd Batt Open
2W-GSFXS-Idle Open Batt Open
2W-GSFXS-Tip Gnd
2W-GSFXS-Ringing
2W-GSFXS-Busy Gnd Batt Open
4W-GSFXS-Idle Open Batt Open
4W-GSFXS-Tip Gnd
4W-GSFXS-Ringing
4W-GSFXS-Busy Gnd Batt Open
2W-LSFXO-Idle Open Open Open
2W-LSFXO-R Det Open Open Open
2W-LSFXO-Busy *Loop
2W-GSFXO-Idle Batt Open Open
2W-GSFXO-RngGnd Batt Gnd Open
2W-GSFXO-Ring Det
Batt Gnd Open
2W-GSFXO-Busy *Loop
4W-LSFXO-Idle Open Open Open
4W-LSFXO-R Det Open Open Open
4W-LSFXO-Busy *Loop
4W-GSFXO-Idle Batt Open Open
4W-GSFXO-RngGnd Batt Gnd Open
4W-GSFXO-Ring Det
4W-GSFXO-Busy *Loop
2W-DXN-Idle *Gnd DXV Open
2W-DXN-Busy *Batt
DXV Open
2W-DXR-Idle DXV *Gnd Open
2W-DXR-Busy DXV *Batt
4W-DXN-Idle *Gnd DXV Open
4W-DXN-Busy *Batt
4W-DXR-Idle DXV *Gnd Open
4W-DXR-Busy DXV *Batt
2W-DPO-Ra = 0 Gnd (N)
Batt (N)
2W-DPO-Ra = 1 Batt (R)
Gnd (R)
2W-DPT-Ra = 0 Open Open Open
2W-DPT-Ra = 1 *Loop
TDM Options E, S or T, R or V
TDM: opt. Z; Ra = 0
Open Open *Open
TDM: opt. Z; Ra = 1
Open Open *Gnd
TDM Options S or T, R or V
TDM: opt. W; Rb = 1
Open Open -- Bsense
Gnd --
TDM: opt. W; Rb = 0
SG Open -- BSense
2WTO/2WETO/GT Open Open Open
4WTO/4WETO/SF Open Open Open
4W-Sealing Current-norm
4W-Sealing Current-ZAP
4W-Sealing Current-Sink
Loop Loop Open
E&M and PLR Modes
2W-PLR1-ONH Open Open BSense
*Gnd Open Open
2W-PLR1-OFH Open Open BSense
*Batt
4W-PLR1-ONH Open Open BSense
4W-PLR1-OFH Open Open BSense
2W-E&M1-ONH Open Open *Open
2W-E&M1-OFH Open Open *Gnd
4W-E&M1-ONH Open Open *Open
4W-E&M1-OFH Open Open *Gnd
2W-PLR2-ONH Open Open BSense
2W-PLR2-OFH Open Open BSense
*SB *M Gnd
4W-PLR2-ONH Open Open BSense
4W-PLR2-OFH Open Open BSense
2W-E&M2-ONH Open Open *Open
Batt-CL
2W-E&M2-OFH Open Open *SG GSense
4W-E&M2-ONH Open Open *Open
4W-E&M2-OFH Open Open *SG GSense
2W-PLR3-ONH Open Open BSense
*SG *Open
2W-PLR3-OFH Open Open BSense
*SB *M *Open
4W-PLR3-ONH Open Open BSense
4W-PLR3-OFH Open Open BSense
2W-E&M3-ONH Open Open *Open
2W-E&M3-OFH Open Open *SG GSense
4W-E&M3-ONH Open Open *Open
4W-E&M3-OFH Open Open *SG GSense
Where *indicates Dial Pulsing Contact DXV = 19.6 vdc for DX Signaling (N) = Normal Battery (R) = Reverse Battery BSense = Battery Connected Sense GSense = Ground Connected Sense BattCL = Battery Current Limiter
TABLE III (part 1)
Universal Signaling Circuit Control Lines Loop Modes Decoder Outputs Decoder Outputs *Ring Long *M Gnd *M Batt *M-SG *M-SB *E Gnd *E Batt *E-SG Hi Bias *A-SG *Rev Dis Sw Sw Sw Sw Sw Sw Sw Gain
Reference Number ->
320 304 140
313 317 312 311 308 309 306 320
1 1 1 0 1 1 1 1 1 1 1 1
2W-PLAR/RD-Idle
2W-PLAR/RD-Busy
4W-PLAR/RD-Idle
4W-PLAR/RD-Busy
2W-LSFXS-Idle 1 1 1 0 1 1 1 1 1 1 1 1
2W-LSFXS-Busy 1 1 1 0 1 1 1 1 1 1 1 1
4W-LSFXS-Idle 1 1 1 0 1 1 1 1 1 1 1 1
4W-LSFXS-Busy 1 1 1 0 1 1 1 1 1 1 1 1
2W-GSFXS-Idle 1 1 1 0 1 1 1 1 1 1 1 1
2W-GSFXS-Busy 1 1 1 0 1 1 1 1 1 1 1 1
4W-GSFXS-Idle 1 1 1 0 1 1 1 1 1 1 1 1
4W-GSFXS-Busy 1 1 1 0 1 1 1 1 1 1 1 1
TABLE III (part 2)
Universal Signaling Circuit Control Lines Loop Modes Decoder Outputs *A *B *SB *23 *50 Gnd *A Batt Gnd *B *Bring Volt *Mdet *SBBatt SGGnd Gnd SW ma ma *Loop Sw Sw Sw Sw Sw
315 310 307 319 335
0 1 1 0 1 1 1 1 1 1 1 1 1
2W-FX/RD and
PLAR1&2
0 1 1 0 1 1 0 1 0 1 1 0 1
2W-PLAR/RD-Ring-
0 1 1 0 1 1 0 1 0 1 1 0 0
4W-FX/RD and
4W-PLAR/RD-Ring-
2W-LSFXS-Idle
2W-LSFXS-Busy
4W-LSFXS-Idle
4W-LSFXS-Busy
2W-GSFXS-Idle
0 1 1 0 1 1 0 1 0 1 1 1 1
0 1 1 0 1 1 0 1 0 1 1 1 0
2W-GSFXS-Busy
4W-GSFXS-Idle
4W-GSFXS-Busy
TABLE III (part 3)
320 304 140 335 313 317 312 311 308 309 306 320
2W-LSFXO-Idle
2W-LSFXO-R Det
2W-LSFXO-Busy
2W-GSFXO-Idle
2W-GSFXO-RngGnd
2W-GSFXO-Busy
4W-LSFXO-Idle
4W-LSFXO-R Det
4W-LSFXO-Busy
4W-GSFXO-Idle
4W-GSFXO-RngGnd
4W-GSFXO-Busy
2W-DXN-Idle 1 1 1 1 1 1 1 1 1 1 1 1
2W-DXN-Busy 1 1 1 1 1 1 1 1 1 1 1 1
2W-DXR-Idle 1 1 0 1 1 1 1 1 1 1 1 1
2W-DXR-Busy 1 1 0 1 1 1 1 1 1 1 1 1
4W-DXN-Idle 1 1 1 1 1 1 1 1 1 1 1 1
4W-DXN-Busy 1 1 1 1 1 1 1 1 1 1 1 1
4W-DXR-Idle 1 1 0 1 1 1 1 1 1 1 1 1
4W-DXR-Busy 1 1 0 1 1 1 1 1 1 1 1 1
2W-DPO-Ra = 0
2W-DPO-Ra = 1
1 1 0 0 1 1 1 1 1 1 1 1
TABLE III (part 4)
1 1 1 0 1 1 1 1 1 1 1 1 1
0 1 1 0 1 1 1 0 1 1 1 1 1
1 1 1 0 1 1 1 1 0 1 1 1 1
1 1 1 0 1 1 1 1 0 0 1 1 1
0 1 1 0 1 1 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 0 1 1 1
1 1 1 0 1 1 1 1 1 0 0 1 1
2W-DXN-Idle
2W-DXN-Busy
0 1 1 0 1 1 0 1 1 0 1 1 1
2W-DXR-Idle
2W-DXR-Busy
4W-DXN-Idle
4W-DXN-Busy
4W-DXR-Idle
4W-DXR-Busy
TABLE III (part 5)
2W-DPT-Ra = 0 1 1 1 0 1 1 1 1 1 1 1 1
2W-DPT-Ra = 1 1 1 1 0 1 1 1 1 1 1 1 1
TDM Options E, S or T, R
1 1 1 0 1 0 1 1 1 1 0 1
TDM: opt. Y; Ra = 1
TDM: opt. Y; Ra = 0
TDM Options S or T, R or
1 0 1 0 1 0 1 1 1 1 0 1
2WTO/2WETO/GT 1 1 1 0 1 1 1 1 1 1 1 1
4WTO/4WETO/SF 1 1 1 0 1 1 1 1 1 1 1 1
2W-PLR1-ONH 1 1 1 0 0 1 1 1 1 0 1 1
2W-PLR1-OFH 1 1 1 0 1 0 1 1 1 0 1 1
4W-PLR1-ONH 1 1 1 0 0 1 1 1 1 0 1 1
4W-PLR1-OFH 1 1 1 0 1 0 1 1 1 0 1 1
2W-E&M1-ONH 1 1 1 0 0 1 1 1 1 1 1 1
2W-E&M1-OFH 1 1 1 0 0 1 1 1 0 1 1 1
4W-E&M1-ONH 1 1 1 0 0 1 1 1 1 1 1 1
4W-E&M1-OFH 1 1 1 0 0 1 1 1 0 1 1 1
TABLE III (part 6)
2W-PLR2-ONH
2W-PLR2-OFH
4W-PLR2-ONH
4W-PLR2-OFH
2W-E&M2-ONH
0 0 0 0 1 1 1 1 1 1 1 1 1
2W-E&M2-OFH
4W-E&M2-ONH
4W-E&M2-OFH
2W-PLR3-ONH
2W-PLR3-OFH
4W-PLR3-ONH
4W-PLR3-OFH
2W-E&M3-ONH
0 0 0 1 1 1 1 1 1 1 1 1 1
2W-E&M3-OFH
4W-E&M3-ONH
4W-E&M3-OFH
Where: Normal: 1 = On, 0 = Off *before name means 0 = On, 1 = Off
Example I is a 2 wire-loop start FXS (2W-LSFXS). As shown, three states exist: idle, ringing, and busy. In all three states the A lead remains at ground and the E, M, SB and SG leads are open (i.e., only the loop circuits 210) are involved. The B lead operates to provide battery feed or ringing during the ringing state.
ExampIe II
Example 2 is a 2W-E&M2 having two states: on hook (ONH) and off hook (OFH). Here the A and B leads are open. The M lead is in ground connected sense (GSense). The SB lead is connected to the battery current limiter. The E and SG leads are initially open on on-hook and close together for the off-hook state.
a. Serial to Parallel Convert and Decode Circuit 200
The serial to parallel convert and decode circuit 200 is shown to comprise a line converter 202 and four decoders 204. In the preferred embodiment, the line converter is preferably a three to twenty-four line converter using a Model CD4094-type shift register. Each decoder 204 is a two to four line decoder.
b. Loop Circuits 210
A discussion of the preferred design for the loop circuits 210 follows.
c. The E & M Circuits
The E & M circuits 220 set forth an arrangement of signaling switches and sensors associated with conventional telephony E & M signaling modes. The E & M switches are used for E & M signaling modes 1 through 5.
d. Configuration signals
In Table III below, the sets of configuration signals of the present invention are set forth. These are the signals delivered over lines 230 and 240 from the serial to parallel converter 200 which according to the diagram of FIGS. 3A and 3B, controls the loop and E & M circuits 210 and 220.
In FIG. 4, the configured signaling circuit of Example I (i.e., 2W-LSFXS) is set forth. FIG. 4 also illustrates the configuring of the loop circuit 210 for a 2W-LSFXO. This example illustrates on the phone side of the telephone network a loop start FXS and on the central office side a loop start FXO modes of operation.
Idle R. Det. Busy
Ring Bias 0 0 1
(loop sensor) 320
Hi Gain 0 0 1
Volt 1 1 0
Loop SW 323 1 1 0
In this example, two configurations for the E & M circuits 220 are set forth. On the central office number one side, a 2W-E&M2 interface circuit is configured corresponding to Example II above. In the central office number two side, a PLR2 interface is configured in the universal signaling circuit of the present invention. This illustrates two E & M trunk applications.
ONH OFH
E-SG Sw 306 1 0
SB Batt 310 0 0
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