Source: https://patents.google.com/patent/US5198814A/en
Timestamp: 2019-09-22 23:34:28
Document Index: 499196581

Matched Legal Cases: ['art 153', 'art 154', 'art 153', 'art 154', 'art 153', 'art 153', 'art 153']

US5198814A - Digital-to-analog converter with conversion error compensation - Google Patents
Digital-to-analog converter with conversion error compensation Download PDF
US5198814A
US5198814A US07/800,922 US80092291A US5198814A US 5198814 A US5198814 A US 5198814A US 80092291 A US80092291 A US 80092291A US 5198814 A US5198814 A US 5198814A
US07/800,922
1990-11-28 Priority to JP32634490 priority Critical
1990-11-28 Priority to JP2-326344 priority
1991-11-27 Application filed by NEC Corp filed Critical NEC Corp
1992-01-15 Assigned to NEC CORPORATION reassignment NEC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: OGAWARA, TAKESHI, TAKIGUCHI, TOMIO
1993-03-30 Publication of US5198814A publication Critical patent/US5198814A/en
Next, referring to FIG. 2(d), the EPROM 17 has a decoder 241 which decodes the code words (A1, A0) from the counter 13 (FIG. 2(a)) and a memory cell array 240 which has a capacity of 4×4 bits corresponding to the addresses (0, 0) to (3, 3) (in the figure the memory address (x, y) is represented by Pxy so that the abovementioned addresses correspond to P00 to P33).
TABLE 1______________________________________  t.sub.2      t.sub.4      t.sub.6 t.sub.8______________________________________A.sub.1  0     0            0 to 1                             1A.sub.0  0     0 to 1       1 to 0                             0 to 1______________________________________
TABLE 2______________________________________                        Time at which           Time at which                        compensation data           compensation data                        are transferred toA.sub.0 A.sub.1   are output   register circuit______________________________________0     0         --           t.sub.30     1         t.sub.4 + ACCT                        t.sub.51     0         t.sub.6 + ACCT                        t.sub.71     1         t.sub.8 + ACCT                        t.sub.9______________________________________ (ACCT means the time required for reading the memory circuit.)
To describe the relation between the code word (S0 to S10) and the DA converted output VOUT in more detail, first, let the current value that flows in the resistor element 123 of the resistor element group 174 be determined when a specific one alone among the switching elements 112 to 118 of the main DAC part 153 is connected to the resistor element group 174 in response to the above-mentioned code word, and only the constant current source that corresponds to the specific one switching element draws a current I to the grounding potential. If one assumes that the specific switching element mentioned above is the switching element 112, then the constant current source 101 alone draws the current I to the grounding potential via the resistor element group 174. Since the value of the resultant resistance of the resistor elements 124 to 131 of the resistor element group 174 is 2R, the current is divided according to the ratio of the resistance value of the resistor element 123 to the resultant resistance value 2R in the above, and the current I0 that flows in the resistor element 123 is evaluated to be 2/3I. Similarly, the current I0 that flows in the resistor element 123 when the switch element 113 alone is switched on can be evaluated to be 2/3I. In the same manner, the current I0 that flows in the resistor element 123 corresponding to the states in which only one of the switching elements 114, 115, 116, 117, and 118 is switched on can be evaluated to be 2/3I, (1/2)·(2/3I), (1/2)2 ·(2/3I), (1/2)3 ·(2/3I), and (1/2)4 ·(2/3I), respectively, The current I0 that flows in the resistor element 123 can be evaluated by calculating the current values corresponding to the individual on-state of each one of the switching cells 112 to 118 in the above according to the principle of superposition.
In addition, the minimum value of the current I0 that flows in the resistor element 123 is given by the current value for the state in which all of the movable contacts of the switching elements 112 to 118 are made to fall to the left side in FIG. 2(b), which is equal to zero. Moreover, the minimum step width of the current I0 is determined by the switching on/off of the switching cell 118, and its value is equal to (1/2)4 ·(2/3I). The product of the current value evaluated in the above and the resistance value of the resistor element 123 gives the DA converted output voltage VOUT.
The operation of the main DAC part will be described in more detail by taking the case of the digital input code word (D5, D4, D3, D2, D1, D0) of the parallel six bits is (0,1,0,1,0,1) as an example. Accompanying the code word input, the highest order two bits (D5, D4)=(0,1) are input to the decoder 135. The decoder 135 supplies the respective bits of the 3-bit parallel codes (0,0,1) corresponding to the higher two bits (0,1) to the latch circuits 136, 137, and 138, respectively. These parallel codes (0,0,1) held in the latch circuits 136 to 138 are supplied respectively to the switching elements 112 to 114 as the control inputs. The lowest order four bits (0,1, 0,1) of the digital input code word (D5, D4, D3, D2, D1, D0) are respectively added directly to the latch circuits 139 to 142 to be latched, and are supplied to the switching elements 115 to 118 as a parallel 4-bit control input (S7, S6, S5, S4). In response to the control input (0,1, 0,1) the switching elements 112, 113, 115, and 117 go to the state in which the movable contacts are made to fall to the left side in FIG. 2(b) and the switching elements 114, 116, and 118 go to the state in which the movable contacts are made to fall to the right side. In response to the above-mentioned state of the switching elements 112 to 118, the constant current sources 101, 102, 105, and 107 draws the respective currents I from the power terminal 132 to the grounding potential via the resistor element group 174. The currents that flow in the resistor element due to the above driving of the switching elements 112, 113, 115, and 117 are 2/3I, 1/2·(2/3I), (1/2)2 ·(2/3I), and (1/2)3 ·(2/3I), respectively, so that the resultant current I0 that flows in the resistor element 123 is equal to (42/16)·(2/3I) by the principle of superposition. Therefore, the DA converted output VOUT for the parallel 6-bit code word (0,1,0,1,0,1) is equal to (42/16)·(2/3I)·R.
Next, the compensation due to the auxiliary DAC part 154 of the conversion error in the main DAC part 153 will be described. The current I0 which flows in the resistor element 123 when only the switching element 119 among the switching elements 119 to 122 is made to fall to the left side in the circuit diagram in FIG. 2(b) to be connected to the resistor element group 174 and the constant current source 108 draws the constant current I, is the same value of (1/2)3 ·(2/3I) for the case in which the switching element 117 alone is made to fall to the left side. Similarly, the current value I0 for the state in which the switching element 120 alone is made to fall to the left side equals (1/2)4 ·(2/3I). The current value I0 for the states in which the switching element 121 alone and the switching element 122 alone are made to fall to the left side are (1/2)5 ·(2/3I) and (1/2)6 ·(2/3I), respectively. The maximum value of the compensation of the conversion error is obtained corresponding to the current value I0 for the state in which all of the switching elements 119 to 122 are made to fall to the left side, and the maximum value is (15/64)·(2/3I). In addition, the minimum value of the conversion error compensation is zero. Further, the minimum step width of the conversion error compensation can be determined by the response to the switching on/off of the switching element 122, and its value can be found to be (1/64)·(2/3I).
Next, the relation between the quantity of the conversion error and the input digital code word (D0 to D5) will be described. As in the above, the degrees of influence of the highest order two bits (D5, D4) and the lowest order four bits (D3, D2, D1, D0) on the conversion error that appear in the DA converted output VOUT show, from the result in the above that the current value I0 in the case where the switching element 115 draws the constant current I via the resistor element group 174 is (1/2)·(2/3I) while the current value I0 in the case where the switching elements 112, 113, and 114 draw the constant current I the resistor element group 174 is (2/3I), that the degree of influence of the switching element 115 can be considered to be 50% of the degree of influence of the switching elements 112 to 114. Similarly, the degrees of influence of the switching elements 116, 117, and 118 are 25%, 12.5%, and 6.75%, respectively, of the degree of influence of the switching elements 112 to 114. Accordingly, the object of the error compensation needs only be limited to the switching cells 112, 113, and 114 that are related to the highest order two bits (D5, D4), and there will arise no practical inconvenience if the switching element 115 is dropped from the object of the compensation.
Next, the correction data for the case when the highest order two bits (D5, D4) are (0,0) will be computed. If the input digital code word (D5, D4, D3, D2, D1, D0) is assumed to be (0,0,1,1,1,1), the switching elements 115 to 118 are all made to fall to the right side in FIG. 2(b) since the lowest order four bits are all "1", and the currents due to these switching elements do not pass through the resistor element 123 and hence they do not influence the conversion error of the DA converted output VOUT. On the other hand, the highest order two bits (D5, D4) are (0,0) so that the code word that appear in the outputs of the latch circuits 136 to 138 is (0,0,0) and the switching elements 112 to 114 are made to fall to the left side, and the currents due to these switching elements all pass through the resistor element 123. In this state, the theoretical value of the DA converted output VOUT is (6/2)·(2/3I)·R, but the DA conversion errors due to the constant current sources 101, 102, and 103 are inevitable. Now, assume that the intrinsic conversion error of the main DAC part of the DAC measured prior to the storage of the compensation data to the EPROM 17 is (1/16)·(2/3I)·R. This conversion error is equal to the output voltage (1/16)·(2/3I)·R of the auxiliary DAC part for the state in which the switching element 120 is made to fall to the left side and the switching elements 119, 121, and 122 are made to fall to the right side, so that the above-mentioned conversion error can exactly be compensated for. In other words, the compensation of the conversion error can be achieved by setting the control input (S3, S2, S1, S0) to the switching elements 119 to 122 of the auxiliary DAC part to (1,0,1,1). These highest order two bits (D5, D4) are made to correspond to the address of the EPROM 17 and the control input (1,0,1,1) is stored in the EPROM 17. Namely, the code word (1,1,0,1) is stored in the zero-th column (P00, P10, P20, P30) of the memory cell array 240 of the EPROM 17.
For the case of the highest order two bits (D5, D4) of the input digital signal are (0,1), the compensation data is found in the manner similar to the case of (0,0) in the above. Namely, assume that the lowest order four bits D3 to D0 of the digital input code word (D0 to D5) is all "1", that is (0,1,1,1,1,1). In this case, the highest order two bits (0,1) are converted to the code word (0,0,1) and are latched in the latch circuits 136 to 138. Accordingly, the switching elements 112 and 113 are made to fall to the left side and the switching element 114 is made to fall to the right side, and the theoretical value of the DA converted output VOUT becomes equal to (4/2)·(2/3I)·R. Assuming that the conversion errors measured in advance due to the constant current sources 101 and 102 were (3/64)·(2/3I)·R, it is possible to generate a compensation output of {(1/2)5 +(1/2)6 }·(2/3I)·R, namely, (3/64)·(2/3I)·R for the state in which the switching elements 121 and 122 of the auxiliary DAC part are made to fall to the left side and the switching elements 119 and 120 are made to fall to the right side, so that the above-mentioned conversion error can be eliminated. This conversion error can be accomplished by setting the control input (S3, S2, S2, S0) to the switching elements 119 to 122 of the auxiliary DAC part 154 to the code word (1,1,0,0). For this purpose, the memory contents (P01, P11, P21, P31) (FIG. 2(d)) of the first column of the highest order two bits (0,1) of the memory cell array 240 of the EPROM 17 are set to (1,1,0,0). The compensation data for the cases in which the highest order two bits (D5, D4) of the input digital signal are (1,0) and (1,1) can be determined in the procedure analogous to the cases of (0,0) and (0,1), and the memory contents of the second column (P02, P12, P22, P32) and the third column (P03, P13, P23, P33) of the memory cell array 240 of the EPROM 17 are set to (0,1,1,1) and (1,1,1,1), respectively.
As described in the above, the theoretical value of the DA converted output VOUT of the main DAC part 153 corresponding to the input code word (0,1,0,1,0,1) is (42/16)·(2/3I)·R. In reality, however, in the main DAC part 153, there are generated conversion errors due to the constant current sources 101 to 107 and the resistor element circuit group 174. Assume, then, that the actual measured value of the DA converted outout VOUT that includes the error is (42/16)·(2/3I)·R-(4/64)·(2/3I)·R. The register circuit 18 is holding the compensation data which was transferred from the EPROM 17 through the above-mentioned process. Since the highest order two bits (D5, D4) of the input code word (0,1,0,1,0,1) are (0,1), the matrix switching circuit 19 selects the output signals R01, R11, R21, and R31 of the DFFs 201, 211, 221, and 231 by means of the semiconductor switches 24 to 27. In other words, the control output (S3, S2, S1, S.sub. 0) from the matrix switching circuit 19 will have the value (1,1,0,0) (see FIG. 4(c)). Since the switching elements 121 and 122 of the auxiliary DAC part are made to fall to the left side due to the control output (S3, S2, S1 S0), currents flow through the resistor element circuit group 174, the error correction quantity of the DA converted output VOUT of the main DAC part 153 becomes
{(1/2).sup.5 +(1/2).sup.6 }·(2/3I)·R=(3/64)·(2/3I)·R.
(42/16)·(2/3I)·R-(2/64)·(2/3I)·R+(3/64)·(2/3I)·R=(42/16-1/64)·(2/3I).
(1/2).sup.4 ·(2/3I)·R.
US07/800,922 1990-11-28 1991-11-27 Digital-to-analog converter with conversion error compensation Expired - Lifetime US5198814A (en)
JP32634490 1990-11-28
JP2-326344 1990-11-28
US5198814A true US5198814A (en) 1993-03-30
ID=18186739
US07/800,922 Expired - Lifetime US5198814A (en) 1990-11-28 1991-11-27 Digital-to-analog converter with conversion error compensation
US (1) US5198814A (en)
EP (1) EP0488282B1 (en)
DE (2) DE69128910D1 (en)
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1991-11-27 US US07/800,922 patent/US5198814A/en not_active Expired - Lifetime
1991-11-28 DE DE1991628910 patent/DE69128910D1/en not_active Expired - Lifetime
1991-11-28 EP EP19910120393 patent/EP0488282B1/en not_active Expired - Lifetime
1991-11-28 DE DE1991628910 patent/DE69128910T2/en not_active Expired - Lifetime
US8878709B2 (en) * 2009-07-02 2014-11-04 Sony Corporation Semiconductor integrated circuit and liquid crystal drive circuit
DE69128910T2 (en) 1998-09-10
EP0488282A3 (en) 1994-11-09
DE69128910D1 (en) 1998-03-19
EP0488282B1 (en) 1998-02-11
EP0488282A2 (en) 1992-06-03
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:OGAWARA, TAKESHI;TAKIGUCHI, TOMIO;REEL/FRAME:005983/0826