Source: http://www.google.com/patents/US7132756?dq=6,208,537
Timestamp: 2017-10-19 00:18:19
Document Index: 627639526

Matched Legal Cases: ['arts 104', 'arts 104', 'arts 104', 'arts 104', 'arts 104', 'arts 104', 'arts 104', 'arts 104']

Patent US7132756 - Semiconductor device and method for manufacturing the same - Google Patents
A semiconductor device (1) of the present invention includes a semiconductor element (103) including electrode parts (104), and a wiring substrate (108) including an insulation layer (101), electrode-part-connection electrodes (102) provided in the insulation layer (101), and external electrodes (107)...http://www.google.com/patents/US7132756?utm_source=gb-gplus-sharePatent US7132756 - Semiconductor device and method for manufacturing the same
Publication number US7132756 B2
Application number US 10/692,938
Also published as CN1499617A, CN100442481C, EP1420441A1, US7390692, US20040084769, US20060290009
Publication number 10692938, 692938, US 7132756 B2, US 7132756B2, US-B2-7132756, US7132756 B2, US7132756B2
Inventors Yasuhiro Sugaya, Toshiyuki Asahi, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani
Patent Citations (16), Classifications (65), Legal Events (5)
US 7132756 B2
9. The semiconductor device according to claim 8, wherein in the case where the material containing the thermosetting resin does not contain thermosetting polyimide, the material containing the thermosetting resin contains a thermosetting resin with a glass transition temperature of not higher than 150° C.
In the semiconductor device of the present embodiment, preferably, the insulation layer is made of a material containing a thermosetting resin, and the material containing a thermosetting resin contains 75 wt % to 91 wt % of an inorganic filler, and 9 wt % to 25 wt % of a resin composition containing a thermosetting resin. The thermosetting resin preferably contains at least one kind of resin selected from the group consisting of epoxy resins, phenol resins, cyanate resins, and thermosetting polyimide. In the case where the material containing the thermosetting resin does not contain thermosetting polyimide, the material containing the thermosetting resin preferably contains a thermosetting resin with a glass transition temperature of not higher than 150° C. The wiring substrate including the insulation layer made of such a material is capable of reducing stresses occurring due to the thermal expansion difference between the semiconductor element and the wiring substrate, even if the electrode part and the electrode-part-connection electrode are bonded directly by metal joint.
In the method of the present embodiment for manufacturing a semiconductor device, the material containing a thermosetting resin in a non-cured state preferably contains 75 wt % to 91 wt % of an inorganic filler, and 9 wt % to 25 wt % of a resin composition containing a thermosetting resin, and the thermosetting resin preferably contains at least one kind of resin selected from the group consisting of epoxy resins, phenol resins, cyanate resins, and thermosetting polyimide. Besides, in the case where the material containing the thermosetting resin in a non-cured state does not contain thermosetting polyimide, the material containing the thermosetting resin in a non-cured state preferably contains a thermosetting resin with a glass transition temperature of not higher than 150° C. It should be noted that the content of the inorganic filler and the content of the resin composition containing a thermosetting resin are calculated in terms of a composition that does not contain a solvent.
The resin composition preferably contains, as the thermosetting resin, at least one kind of resins selected from the group consisting of epoxy resins, phenol resins, cyanate resins, and thermosetting polyimide. Brominated epoxy resins preferably are used in particular, since they exhibit fire retardance. Further, in the case where the resin composition does not contain thermosetting polyimide, it preferably contains a thermosetting resin having a glass transition temperature (Tg) of not higher than 150° C. In the case where the thermosetting resin contained in the resin composition contains two or more kinds of resins selected from the foregoing group (excluding thermosetting polyimide), at least one kind of a thermosetting resin may have a glass transition temperature (Tg) of not higher than 150° C. It should be noted that in the case where the resin composition contains thermosetting resins that are categorized as the same kind but have different glass transition temperatures (Tg), for instance, two kinds of epoxy resins having different glass transition temperatures (Tg), these resins are regarded as resins of different kinds, and at least one kind of an epoxy resin among the foregoing two or more kinds of epoxy resins may have a glass transition temperature of not higher than 150° C. It should be noted that no lower limit of the glass transition temperature is set particularly, but normally, the glass transition temperature preferably is not lower than 50° C.
In the case where the resin composition contains two or more kinds of resin, a proportion by weight between the thermosetting resin having a glass transition temperature of not higher than 150° C. and the other resins is not limited particularly, but normally the ratio by weight preferably is 1:3 to 3:1.
Examples usable as a solvent for decreasing the viscosity of a mixture that contains an inorganic filler and a resin composition containing a thermosetting resin include ethyl carbitol, butyl carbitol, and butyl carbitol acetate. These have boiling points of not lower than 150° C. Additionally, the examples include methyl ethyl ketone, isopropanol, toluene, etc. These have boiling points of not higher than 100° C. One kind, or two or more kinds of these solvents may be used.
First, a mixture slurry containing an inorganic filler, a resin composition containing a thermosetting resin, a solvent having a boiling point of not lower than 150° C., and a solvent having a boiling point of not higher than 100° C. is prepared, and a film is formed with this mixture slurry on a releasing film (not shown). The method for forming the film is not limited particularly, and examples of the same include doctor blading, coater method, extrusion, etc. Next, only the solvent having a boiling point of not higher than 100° C. is removed by drying from the film thus formed. By so doing, the insulation member 30 in a non-cured state having flexibility is formed.
In the present embodiment, for instance, a copper foil with a thickness of 9 μm is laminated on a surface 30 a of the insulation member 30 on one side thereof at 100° C., and after pressure application thereto, unnecessary portions thereof are removed, whereby a wiring pattern 31 b is formed. Thereafter, it is subjected to electroless plating so that the protruded wiring pattern 31 including metal layers (Au layers) 31 a is formed. Thus, a mounting member 32 as shown in FIG. 9C is formed. By forming the wiring pattern 31 so that it protrudes from the surface 30 a as described above, the pressure applied upon the metal joint of the metal layers 102 a of the electrode-part-connection electrodes 102 and the metal layer 104 a of the electrode parts 104 is applied accurately to an interface where the electrode-part-connection electrodes 102 and the electrode parts 104 are in contact with each other. Therefore, the electrode-part-connection electrodes 102 and the electrode parts 104 are bonded firmly with each other (see FIG. 1).
Next, the transfer carriers 45 and 46 provided with the wiring patterns 43 and 44, respectively, and the insulation member 40 are aligned and superposed, and the laminate thus obtained is heated in an atmosphere at approximately 100° C. to 120° C. while a pressure of 3 MPa to 10 MPa is applied thereto, so that the wiring patterns 43 and 44 are transferred to the insulation member 40.
Next, as shown in FIG. 14C, transfer carriers 56 and 57 provided with wiring patterns 54 and 55, respectively, are prepared. Subsequently, the transfer carriers 56 and 57 provided with the wiring patterns 54 and 55, and the second sheet-like material 53 are aligned and superposed, and the laminate thus obtained is heated in an atmosphere at approximately 100° C. to 120° C. while pressure of 3 MPa to 10 MPa is applied thereto, so that the wiring patterns 54 and 55 are transferred to the second sheet-like material 53. By so doing, a third sheet-like material 58 in a non-cured state is obtained, as shown in FIG. 14D.
Next, the fifth sheet-like material 61, and the transfer carrier 63 provided with the wiring pattern 62 are aligned and superposed on the third sheet-like material 58 in the stated order, and the laminate thus obtained is heated in an atmosphere of approximately 100° C. to 120° C., while pressure of 3 MPa to 10 MPa is applied thereto. Subsequently, the transfer carrier 63 is removed from the foregoing laminate, whereby a sixth sheet-like material 64 in a non-cured state is formed, as shown in FIG. 14F.
As the condition under which the lamination is carried out while the non-cured states of the first and fourth sheet-like materials 50 and 60 are maintained, it is preferable that the foregoing laminate is heated at approximately 120° C. in the step described with reference to FIG. 14E, in the case where the atmosphere temperature when the wiring patterns 54 and 55 are transferred is, for instance, approximately 100° C. This is because even if the curing of the thermosetting resin contained in the first sheet-like material 50 is promoted by the transfer of the wiring patterns in an atmosphere at 100° C., such first and fourth sheet-like materials 50 and 60 can be laminated without delamination occurring thereto.
Next, on the multilayer wiring substrate 901 on which the semiconductor element 4 of the present invention and the circuit component 903 are mounted, the sheet-like material 910 having the through holes filled with the conductive resin composition 905 and the transfer carrier 906 provided with the wiring pattern 907 are aligned and superposed in the stated order, and are subjected to temperature of 100° C. to 180° C. and pressure of 3 GPa to 10 GPa. By so doing, the semiconductor device 4 of the present invention, the circuit component 903, and the wiring pattern 907 are embedded in the sheet-like material 910, and then, the sheet-like material 910 is cured to become the insulation substrate 904 (see FIG. 17C).
Epoxy resin (manufactured by Asahi-Chiba Co., Ltd., currently Asahi Kasei Epoxy Co., Ltd., 6041, Tg=75° C.): 22 wt %
Epoxy resin (manufactured by Asahi-Chiba Co., Ltd., currently Asahi Kasei Epoxy Co., Ltd., 6041, Tg=75° C.): 13 wt %
Epoxy resin (manufactured by Nippon Pelnox Corporation, WE-2025, Tg=50° C.): 6 wt %
Epoxy resin (manufactured by Asahi-Chiba Co., Ltd., currently Asahi Kasei Epoxy Co., Ltd., 6018, Tg=130° C.): 7 wt %
Epoxy resin (manufactured by Yuka Shell Epoxy K.K., currently Japan Epoxy Resins Co., Ltd., EPIKURE YH-306, Tg=110° C.): 9 wt %
Epoxy resin (manufactured by Yuka Shell Epoxy K.K., currently Japan Epoxy Resins Co., Ltd., EPICURE YH-306, Tg=110° C.): 9 wt %
Polyimide (manufactured by New Japan Chemical Co., Ltd., RIKACOAT EN-20, Tg=190° C.): 11 wt %
Polyimide (manufactured by New Japan Chemical Co., Ltd., RIKACOAT EN-20, Tg=190° C.): 7 wt %
Epoxy resin (manufactured by Asahi-Chiba Co., Ltd., currently Asahi Kasei Epoxy Co., Ltd., 6041, Tg=75° C.): 7 wt %
Epoxy resin (Tg=150° C.): 13 wt %
Epoxy resin (manufactured by Asahi-Chiba Co., Ltd., currently Asahi Kasei Epoxy Co., Ltd., 6099, Tg=178° C.): 22 wt %
Epoxy resin (manufactured by Asahi-Chiba Co., Ltd., currently Asahi Kasei Epoxy Co., Ltd., 6099, Tg=178° C.): 13 wt %
Epoxy resin (manufactured by Asahi-Chiba Co., Ltd., currently Asahi Kasei Epoxy Co., Ltd., 6099, Tg=178° C.): 9 wt %
Thermosetting polyphenylene ether resin (Tg=198° C.): 22 wt %
Next, as shown in FIG. 9D, the mounting member 32, and a semiconductor element including electrode parts 104 whose surfaces were plated with Au (i.e., having Au layers) (TEG, 10 mm square, 0.1 mm thick, having 100 pad electrodes (electrode parts), distance between pad electrodes: 125 μm) were aligned and superposed. Next, the laminate of these was heated at 40° C., and while pressure of 1.5 N per electrode part (pad electrode) was applied thereto, surfaces at which the electrode parts 104 and the wiring pattern 31 were brought into contact with each other were heated using ultrasonic vibration, so that the electrode parts 104 and the electrode-part-connection electrodes 102 were connected by metal joint. The frequency of the ultrasonic was 60 kHz, and the time of oscillating the ultrasonic wave was 500 m/s.
Next, the laminate composed of a semiconductor element 103 and the mounting member 32 was heated at 120° C. while pressure of 3 MPa was applied thereto so that portions of the wiring pattern 31 that were bonded with the electrode parts 104 (electrode-part-connection electrodes 102) and the electrode parts 104 were embedded in the insulation member 30. Thus, the semiconductor element 103 and the mounting member 32 were brought into close contact with each other, and the insulation member 30 was cured. The semiconductor device thus obtained had a thickness of 200 μm (see FIG. 9E).
The elastic modulus was measured according to JIS K6911. A sample that was 1.5 mm thick, 8 mm±1 mm wide, and 50 mm long was prepared, both ends of the sample were supported by supports as shown in FIG. 18, and a load F (2 kgf to 5 kgf) was applied to a center area of the sample from above. A distance L between the supports was 24 mm, and a lading rate was 0.8 mm/min. An inclination (F/Y) in a straight line region of the obtained load-deflection curve was calculated, and it was substituted in a Formula 1 shown below, so as to calculate the elastic modulus.
E=(L 3/4bh 3)×(F/Y) (Formula 1)
b: width of sample (mm)
h: thickness of sample (mm)
L: distance between supports (mm)
F: load (kgf)
F/Y: inclination of load-deflection curve
An operation of leaving a circuit component package in an atmosphere at −55° C. for 30 minutes, and subsequently leaving the same in an atmosphere at 125° C. for 30 minutes as one cycle was repeated 1000 times, and if a connection resistance was not more than 100 mΩ per electrode part, this was regarded as indicating that excellent electric connection was achieved. This is indicated with ◯ in Table 1. In the case where the connection resistance was completely unchanged from that at an initial stage, this is indicated with ⊚. In the case where the connection resistance exceeded 100 mΩ per electrode part before the 1000 cycles of the foregoing operation were completed, this is indicated with X.
Resin Elastic Thermal
Inorganic compo- mod- expansion Thermal
filler sition Tg ulus coefficient shock test
(wt %) (wt %) (° C.) (GPa) (ppm/° C.) result
Ex. 1 77 (78) 22 (22) 75 3 12 ◯
Ex. 2 86 (87) 13 (13) 75 4 19 ◯
Ex. 3 86 (87) 13 (13) 50/130 3 9 ⊚
Ex. 4 90 (91) 9 (9) 110 4 7 ⊚
Ex. 5 90 (91) 9 (9) 110 4 13 ◯
Ex. 6 88 (89) 11 (11) 190 3 10 ⊚
Ex. 7 85 (86) 14 (14) 190/75  4 11 ⊚
Ex. 8 86 (87) 13 (13) 150 5 13 ◯
Comp. 77 (78) 22 (22) 178 20 13 X
Comp. 86 (87) 13 (13) 178 20 9 X
Comp. 90 (91) 9 (9) 178 36.5 — X
Comp. 77 (78) 22 (22) 198 12 — X
It is seen from Table 1 that in the case where the elastic modulus of the insulation layer was not less than 1 GPa and not more than 5 GPa, a change in the connection resistance was small, and high connection reliability in electrical connection was achieved. Besides, in the case where the material containing a thermosetting resin did not contain thermosetting polyimide, the material had an elastic modulus of not more than 5 GPa in the case where it contained a thermosetting resin with a glass transition temperature of not higher than 150° C., and the material had an elastic modulus of more than 5 GPa in the case where all the thermosetting resins contained in the insulation layer had glass transition temperatures of higher than 150° C. Still further, in the case where the material containing a thermosetting resin did not contain thermosetting polyimide and contained two or more thermosetting resins, the material had an elastic modulus of not less than 1 GPa and not more than 5 GPa as long as it contained at least one kind of a thermosetting resin with a glass transition temperature of not higher than 150° C.
Still further, it was confirmed that in the case where the value of the thermal expansion coefficient of the insulation layer was approximated to the value of the thermal expansion coefficient of the semiconductor element (3 ppm/° C.) by appropriately adjusting the type, amount, and particle diameter of the inorganic filler, the connection reliability was improved further.
US5926694 Jul 11, 1997 Jul 20, 1999 Pfu Limited Semiconductor device and a manufacturing method thereof
US20020056906 Feb 27, 2001 May 16, 2002 Ryoichi Kajiwara Flip chip assembly structure for semiconductor device and method of assembling therefor
US20020090759 Sep 3, 1999 Jul 11, 2002 Nobuaki Hashimoto Semiconductor device, method of connecting a semiconductor chip, circuit board, and electronic equipment
EP0907205A2 Oct 2, 1998 Apr 7, 1999 Matsushita Electric Industrial Co., Ltd. Semiconductor package and method for manufacturing the same
JP2000114314A Title not available
JP2000150549A Title not available
JP2001127108A Title not available
JP2002151551A Title not available
JPH1079362A Title not available
JPH09188119A Title not available
JPH11168112A Title not available
U.S. Classification 257/787, 257/E23.062, 257/E23.077, 257/E23.069, 257/E23.004
International Classification H05K1/02, H05K3/46, H01L23/498, H01L23/13, H01L23/48, H05K1/03, H05K3/32, H01L21/60, H05K3/20
Cooperative Classification H01L2224/05568, H01L2224/05001, H01L2224/05023, H05K2201/10674, H05K2201/091, H05K3/4626, H05K3/4614, H05K3/328, H05K3/326, H05K3/20, H05K1/0373, H05K1/0271, H01L2924/19105, H01L2924/01044, H01L2924/01037, H01L2224/24226, H01L2224/2402, H01L24/94, H01L24/25, H01L24/24, H01L23/49894, H01L23/49822, H01L23/49816, H01L23/13, H01L2924/04953, H01L24/82, H01L2924/3011, H01L2924/15311, H01L2924/01327, H01L2924/01077, H01L2924/01046, H01L2924/01039, H01L2924/0103, H01L2924/014, H01L2924/01082, H01L2924/01079, H01L2924/01078, H01L2924/01076, H01L2924/01074, H01L2924/01051, H01L2924/01047, H01L2924/01033, H01L2924/01029, H01L2924/01027, H01L2924/01019, H01L2924/01013, H01L2924/01006, H01L2924/01005, H01L2224/16, H01L2924/12042
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUGAYA, YASUHIRO;ASAHI, TOSHIYUKI;KOMATSU, SHINGO;AND OTHERS;REEL/FRAME:014642/0296