Source: https://patents.google.com/patent/WO2015173966A1/en
Timestamp: 2018-10-20 22:54:36
Document Index: 458380730

Matched Legal Cases: ['art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2', 'art 3', 'art 1', 'art 2', 'art 1', 'art 2']

WO2015173966A1 - Information processing device, write control circuit, write control method, and write control program - Google Patents
Information processing device, write control circuit, write control method, and write control program Download PDF
WO2015173966A1
WO2015173966A1 PCT/JP2014/063125 JP2014063125W WO2015173966A1 WO 2015173966 A1 WO2015173966 A1 WO 2015173966A1 JP 2014063125 W JP2014063125 W JP 2014063125W WO 2015173966 A1 WO2015173966 A1 WO 2015173966A1
PCT/JP2014/063125
荒津雅紀
日下田雅紀
早坂和美
A control unit controls writing of data to a plurality of blocks included in a storage device. The control unit, when a first number of times of writing to a first block for storing data is greater than a second number of times of writing to a second block for storing data, transfers the first block data to a backup third block, and changes the first block to a backup block.
The information processing apparatus, a write control circuit, the write control method, and programming program
The present invention relates to an information processing apparatus, a write control circuit, the write control method, and a write control program.
In recent information processing system, the non-volatile memory device is widely used. For example, NAND flash memory device which is a kind of nonvolatile memory devices, benefits and operation speed than the conventional magnetic disk device or the like is fast and easy to capacity than other non-volatile storage, that having. Therefore, NAND flash memory devices are utilized in various fields, such as storage systems and storage systems. In the following, the NAND flash memory device is sometimes referred to as "NAND device."
Whereas the NAND devices with benefits as described above, because it does not correspond to overwrite data, when rewriting the data written in the NAND device, to erase data once, again the data is written. Further, since the degraded storage element each time to erase by rewriting the data, some number (e.g., about 10,000 times to 100,000 times) when erasing, it becomes difficult to perform more writing.
Constraints for such write count, NAND device controller may have an address management mechanism and wear leveling mechanism for controlling the writing and erasing of the NAND devices (e.g., see Patent Document 1). Wear leveling mechanism, in order to increase the reliability of the NAND device, a mechanism to equalize the number of times of writing data.
Figure 1 shows a configuration example of an information processing apparatus including such a conventional NAND device. The information processing apparatus 101 of FIG. 1 includes a central processing unit (CPU) 111, a controller 112 and NAND devices 113,.
Storage area in the NAND device 113 is divided into units called blocks (physical blocks), NAND device 113 inputs and outputs data for each block. Block is further divided into units called pages, NAND device 113 is also input and output data for each page.
In this example, the storage area of ​​the NAND device 113, # 1 ~ # N (N is an integer of 2 or more) is divided into N blocks of the these blocks, the physical address of the P1 ~ PN It is allocated. Accordingly, the controller 112, by specifying the physical address, it is possible to identify one block. # 1 ~ # M of the N blocks (M is an integer of 2 or more) are only M blocks of being open to the user, the N-M number of blocks remaining # M + 1 ~ # N, the user is a spare block which is not open to.
Controller 112, read and write control unit 121, First-In First-Out (FIFO) queue 122, and an address conversion table 123. Then, controller 112, in response to a read or write request from the CPU 111, controls the writing of data to read or NAND device 113 of the data from the NAND device 113.
Address conversion table 123, the logical address of the file system software manages (logical address), and a physical address of a block of NAND device 113 is a storage area associated with each block. Address conversion table 123 is a table M words, each word includes a logical address, the written flag, and the physical address.
Physical address of the address conversion table 123 is used as a pointer to the corresponding block in the NAND device 113. The written flag, after the initial setting of the NAND device 113, indicating whether or not writing to the block indicated by each physical address is performed.
FIFO queue 122 may store the physical address corresponding to the N-M number of spare blocks. Then, FIFO queue 122 sequentially outputs the stored physical address from that stored previously.
Reading and writing control unit 121 refers to the address conversion table 123 converts a logical address indicated by the read or write request from the CPU111 into a physical address. Then, the read-write control unit 121 controls the writing of data to the read or the resulting physical address of the data of the obtained physical address.
The read-write controller 121 performs a control for storing the physical address of the spare block in the FIFO queue 122, and a control to retrieve the physical address head from FIFO queue 122.
Figure 2 shows a state after the initial setting of the NAND device 113 in FIG. By default, the contents of all blocks of the NAND device 113 (data) is erased. The address conversion table 123, in association with the logical address of the L1 ~ LM, the physical address of the P1 ~ PM corresponding to the M block that is open to the user is set. Then, the write flag for each physical address is set to non-written state (OFF). Further, the FIFO queue 122, the physical address of the PM + 1 ~ PN corresponding to N-M number of spare blocks is stored.
3 and 4, the controller 112 CPU 111, shows a first example of the write control when receiving the write request for a logical address L4. Procedure of the write control are as follows.
Process 301: reading and writing control unit 121 refers to the address conversion table 123, the write flag corresponding to the logical address L4 shown write request detects that is OFF.
Process 302: reading and writing control unit 121 refers to the address conversion table 123, a physical address corresponding to the logical address L4 detects that a P4.
Process 303: reading and writing control unit 121, the block of the NAND device 113 corresponding to the physical address P4, writes the write data indicating a write request.
Process 304: reading and writing control unit 121 updates the write flag corresponding to the logical address L4 of the address translation table 123 to the write state (ON).
5 and 6, the controller 112 CPU 111, illustrates a second example of the write control when receiving the write request for a logical address L4. Procedure of the write control are as follows.
Process 501: reading and writing control unit 121 refers to the address conversion table 123, a write flag is ON corresponding to the logical address L4 indicated by the write request, the physical address is P4 corresponding to the logical address L4 it is detected that there is.
Process 502: reading and writing control unit 121 extracts the physical address PM + 1 beginning from the FIFO queue 122.
Process 503: reading and writing control unit 121, the spare block of the NAND device 113 corresponding to the physical address PM + 1, writes the write data indicating a write request.
Process 504: reading and writing control unit 121 updates the physical address corresponding to the logical address L4 of the address translation table 123 in PM + 1.
Process 505: reading and writing control unit 121 erases the data of the block in the NAND device 113 corresponding to the physical address P4.
Process 506: reading and writing control unit 121 stores the physical addresses P4 to the FIFO queue 122.
According to such a write control, the physical address P4 stored in the FIFO queue 122 will first be retrieved from the FIFO queue 122 to N-M th time of writing that occurs thereafter. Even if the write request is concentrated to a specific logical address, in rotation of the N-M + 1 blocks comprising N-M number of spare blocks, each block is used. Therefore, as compared with the case where the relationship between the logical addresses and physical addresses are fixed one to one, appear to rewrite limit for the same logical address becomes N-M + 1 times.
The wear leveling mechanism using such a FIFO queue, to equalize the number of writing of each block by rotation of the block to be used, it is possible to extend the life of NAND device. In this case, "wear leveling" refers to a technique to extend the life of NAND device by equalizing the number of write operations block.
Also known is a memory control method for more effective leveling respect nonvolatile semiconductor memory (e.g., see Patent Document 2). In the memory control method, a memory control unit, and the data block is a physical block during use of the non-volatile semiconductor memory, separately manages the replacement block is a physical block waiting. Then, the memory controller manages the number of times of rewriting of each physical block, a predetermined number of times or more replacement block rewrite frequency, non-rewrite time alternates between a long data block than the predetermined time.
JP 7-78485 discloses JP 2010-79860 JP
The write control of the conventional NAND devices described above have the following problems.
The wear leveling mechanism using FIFO queue, regardless of the number of writes spare blocks, since the spare block corresponding to the oldest physical address FIFO queue is used in order, which enables high-speed writing control. However, even in large blocks of write count, once to be used always when it is stored in the FIFO queue, if more of the number of writing times block is stored frequently in the FIFO queue, wear leveling effect is reduced.
On the other hand, in the patent document 2 of the memory control method, a queue is provided for each range of the number of times of rewriting of the replacement block, the number of times of rewriting the predetermined number of times or more replacement block, the data for a long time rewriting has not occurred is written. Thus, it is possible to change to a dedicated block reading more replacement block of the number of rewrites, a higher wear-leveling effect can be expected.
However, in this memory control method, block data becomes a candidate for replacement block is erased, among the plurality of queues are registered in the queue corresponding to the number of times of rewriting the block. Therefore, every time the candidate data is erased replacement block of the block based on the write request to the nonvolatile semiconductor memory is produced, the process of determining the number of times of rewriting is performed. Therefore, to decrease the processing speed of the data write based on the write request is considered that the writing performance deteriorates.
Incidentally, such a problem is not limited to the write control of the NAND device, but also occurs in the write control of the other non-volatile storage.
In one aspect, an object of the present invention, the memory device including a plurality of blocks, is to perform high-performance programming control to equalize the number of writing of each block.
In one proposal, the information processing apparatus includes a storage unit and a control unit including a plurality of blocks.
Control unit controls the writing of data to a plurality of blocks. Then, the control unit has a first number of write operations of the first block for storing data is greater than the second number of write operations of the second block for storing data, spare data of the first block It is moved to the third block, to change the first block to a spare block.
According to the information processing apparatus of the embodiment, the memory device including a plurality of blocks, the write count of each block can be carried out high-performance programming control to equalize.
It is a configuration diagram of a conventional information processing apparatus. It is a diagram illustrating a state after the initial setting of the NAND devices. It is a diagram showing a first example of the write control for the write request to the NAND device (Part 1). It is a diagram showing a first example of the write control for the write request to the NAND device (Part 2). It is a diagram showing a second example of the write control for the write request to the NAND device (Part 1). It is a diagram showing a second example of the write control for the write request to the NAND device (Part 2). It is a configuration diagram of an information processing apparatus of the embodiment. It is a flowchart of the write control. It is a diagram showing a first specific example of the information processing apparatus of the embodiment. It is a diagram showing a state after initialization of the memory device. It is a flow chart of a first specific example of the write control (Part 1). It is a flow chart of a first specific example of the write control (Part 2). It is a flowchart of a data movement control. It shows a first example of the first embodiment of the write control for the write request to the storage device; FIG. It shows a first example of the first embodiment of the write control for the write request to the storage device; FIG. It shows a second example of the first embodiment of the write control for the write request to the storage device; FIG. It shows a second example of the first embodiment of the write control for the write request to the storage device; FIG. It shows a first example of the first embodiment of the write control for data movement request (Part 1). It shows a first example of the first embodiment of the write control for data movement request (Part 2). It shows a second example of the first embodiment of the write control for data movement request (Part 1). It shows a second example of the first embodiment of the write control for data movement request (Part 2). It shows a first specific example of the write control for the deletion request (Part 1). It shows a first specific example of the write control for the deletion request (Part 2). It is a diagram showing a second specific example of the information processing apparatus of the embodiment. It is a flow chart of a second specific example of the write control (Part 1). It is a flow chart of a second specific example of the write control (Part 2). It is a flow chart of a second specific example of the write control (Part 3). It shows a first example of the second embodiment of the write control for data movement request (Part 1). It shows a first example of the second embodiment of the write control for data movement request (Part 2). It shows a second example of the second embodiment of the write control for data movement request (Part 1). It shows a second example of the second embodiment of the write control for data movement request (Part 2). It is a block diagram of a processing circuit.
Hereinafter, with reference to the drawings, an embodiment in detail.
Figure 7 shows an exemplary configuration of an information processing apparatus of the embodiment. The information processing apparatus 701 of FIG. 7 includes a storage device 712 includes a write control circuit 711 and a plurality of blocks, the write control circuit 711 includes a control unit 721.
Figure 8 is a flow chart showing an example of a writing control executed by the control unit 721 of FIG. First, the control unit 721 controls the writing of data to a plurality of blocks included in the storage device 712 (step 801).
First write count of the first block to store the data of those blocks is greater than the second number of write operations of the second block for storing data, control unit 721, the first block moving data to a third block of the spare (step 802). Then, the control unit 721 changes the first block to a spare block (step 803).
According to such an information processing apparatus 701, the memory device including a plurality of blocks, the write count of each block can be carried out high-performance programming control to equalize.
Figure 9 shows a first embodiment of the information processing apparatus 701 of FIG. The information processing apparatus 901 of FIG. 9 includes CPU 911, controller 912, and the storage device 913. Controller 912 and the storage device 913 corresponds to the control unit 721 and a storage device 712 of FIG. The storage device 913 can be used NAND flash memory devices, NOR flash memory devices, non-volatile storage device such as a magnetoresistive random access memory (MRAM).
Storage area within the storage device 913, # 1 ~ # N (N is an integer of 2 or more) is divided into N blocks of the those blocks, physical address of the P1 ~ PN are assigned . Accordingly, the controller 912, by specifying the physical address, it is possible to identify one block. # 1 ~ # M of the N blocks (M is an integer of 2 or more) are only M blocks of being open to the user, the N-M number of blocks remaining # M + 1 ~ # N, the user is a spare block which is not open to.
The controller 912 includes read and write control unit 921, the data migration control unit 922, FIFO queue 923, FIFO queue 924, the address conversion table 925, and the information management table 926. The controller 912, in response to a read or write request from the CPU 911, controls the writing of data to read or storage 913 of the data from the storage device 913.
Address conversion table 925 and the physical address of the block of the logical address and the storage device 913 is a storage area associated with each block. Address conversion table 925 is a table M words, each word includes a logical address, the written flag, and the physical address.
Physical address of the address conversion table 925 is used as a pointer to the corresponding block in the storage device 913. The written flag, after the initial setting of the memory device 913, indicating whether the writing to the block indicated by each physical address is performed.
Information management table 926, a physical address of a block of the storage device 913, and a counter indicating the number of writes that block is a storage area associated with each block. The write count of the block, for example, can be used the number of times the data has been erased in the block.
Information management table 926 is a table N word stores information N blocks, including the spare block. Each word contains the physical address, counter, and a logical address associated with the physical address. For the physical address of the spare block, conveniently logical address L0 is assigned.
FIFO queue 923 is a storage unit for storing physical addresses, L number (L is 1 or more N-M-1 an integer) can store a physical address corresponding to the spare block of. Then, FIFO queue 923 sequentially outputs the stored physical address from that stored previously.
FIFO queue 924 is a storage unit for storing the physical address, it can be stored a physical address corresponding to N-M-L-number of the spare blocks. Then, FIFO queue 924 sequentially outputs the stored physical address from that stored previously.
Read and write control unit 921 refers to the address conversion table 925 converts a logical address indicated by the read or write request from the CPU911 into a physical address. Then, the read-write control unit 921 controls the writing of data to the read or the resulting physical address of the data of the obtained physical address.
Read and write control unit 921, when erasing the data block of the storage device 913, the counter of the corresponding physical address information management table 926 is incremented by one.
Read and write control unit 921, when receiving a write request from the CPU 911, it retrieves the physical addresses from the FIFO queue 923 performs control to store the different physical addresses to the FIFO queue 923. Read and write control unit 921, when receiving the data movement request from the data movement control unit 922 extracts the physical address from the FIFO queue 924 performs control to store the different physical addresses to the FIFO queue 924.
Data movement control unit 922 refers to the information management table 926 at a predetermined timing, L1 ~ of LM logical address M number indicated physical address corresponding to the block, write count indicated by the counter is relatively large block to identify. The relatively large block write count, for example, can be used the largest block write count. The data movement control unit 922, a data movement request directed to the logical address assigned to a particular block, and issues the read and write control unit 921.
According to such a controller 912, when receiving a write request from the CPU 911, using the spare blocks FIFO queue 923 indicates the data is written. Further, it can be stored asynchronously with the write request from the CPU 911, by moving the data of the relatively large blocks write count to another block, the physical address of the source block in the FIFO queue 924.
Thus, by reducing the frequency of use of write count is relatively large blocks, it is possible to effectively equalize the number of writes. Since it is not necessary to determine the number of writing when data is written based on the write request, it does not write performance is degraded. Therefore, increasing the wear leveling effect while maintaining write performance, it is possible to perform high-performance programming control.
Figure 10 shows a state after the initial setting of the memory device 913 of FIG. 9. By default, data in all the blocks of the storage device 913 is erased. The address conversion table 925, in association with the logical address of the L1 ~ LM, the physical address of the P1 ~ PM corresponding to the M block that is open to the user is set. Then, the write flag for each physical address is set to non-written state (OFF).
The information management table 926, P1 ~ M number of logical addresses L1 ~ LM in correspondence to the physical addresses of the PM is set, the preliminary block in association with N-M number of physical addresses of the PM + 1 ~ PN logical addresses L0 indicated is set. Since the data of all the blocks has been erased, the counter for each physical address is set to 1. Incidentally, the initial setting of the second time storage device 913 is performed in this state, the counter of each physical address will be updated to 2.
The FIFO queue 923, the physical address of the PM + 1 ~ PM + L corresponding to the L spare block is stored. The FIFO queue 924, the physical address of the PM + L + 1 ~ PN corresponding to N-M-L-number of the spare block is stored.
11 and FIG. 12 is a flowchart showing an example of the write control of the read-write controller 921 of FIG.
Read and write control unit 921 receives the data movement request from the write request or data movement control unit 922 from the CPU 911, the request received is checked whether it is a request (step 1101).
If the received request is a data movement request (step 1101, YES), the read and write control unit 921 then refers to the address conversion table 925. Then, the read-write controller 921, the write flag corresponding to the logical address data move request indicated checks whether or not the write state (ON) (step 1102).
If the written flag is ON (step 1102, YES), the read-write controller 921 reads data from the block indicated by the physical address corresponding to the logical address data movement request indicates (step 1103). Then, the read-write control unit 921 erases the data of the block (step 1104).
Then, the read-write control unit 921 extracts the physical address head from FIFO queue 924 (step 1105), writes the read data in step 1103, the block indicated by the physical address fetched (step 1106). Thus, the data block corresponding to the logical address data movement request indicates, it can be moved to a spare block corresponding to the physical address fetched from the FIFO queue 924. Then, the read-write control unit 921, a physical address corresponding to the logical address data move request shown, stored in the FIFO queue 924 (step 1107).
Then, the read-write controller 921 in the information management table 926, increments the counter corresponding to the logical address data move request shown by 1 (step 1108). Then, the read-write controller 921 in the information management table 926, and updates the logical address corresponding to the physical address stored in the FIFO queue 924 in L0.
Then, the read-write controller 921, the address conversion table 925, a physical address corresponding to the logical address data movement request indicates to update the physical address fetched from the FIFO queue 924 (step 1109).
Then, the read-write controller 921 in the information management table 926, the logical address corresponding to physical address fetched from the FIFO queue 924 is updated to a logical address where the data move request shown (step 1110).
On the other hand, if the written flag is OFF (step 1102, NO), the read and write control unit 921 extracts the physical address head from FIFO queue 924 (step 1111), corresponding to the logical address data move request indicating the physical address is stored in the FIFO queue 924 (step 1112).
Then, the read-write controller 921 in the information management table 926, and updates the logical address corresponding to the physical address stored in the FIFO queue 924 in L0 (step 1113), step 1109 and subsequent steps.
If the received request is a write request (step 1101, NO), the read and write control unit 921 then refers to the address conversion table 925. Then, the read-write controller 921, the write flag corresponding to the logical address indicated by the write request is checked whether or not ON (step 1201).
If the written flag is ON (step 1201, YES), the read and write control unit 921 erases the data of the block indicated by the physical address corresponding to the logical address indicated by the write request (step 1202).
Then, the read-write control unit 921 extracts the physical address head from FIFO queue 923 (step 1203), writes the write data indicated by the write request, the block indicated by the physical address fetched (step 1204). Then, the read-write control unit 921, a physical address corresponding to the logical address indicated by the write request is stored in the FIFO queue 923 (step 1205).
Then, the read-write controller 921 in the information management table 926, increments the counter corresponding to the logical address indicated by the write request by 1 (step 1206). Then, the read-write controller 921 in the information management table 926, and updates the logical address corresponding to the physical address stored in the FIFO queue 923 in L0.
Then, the read-write controller 921, the address conversion table 925, a physical address corresponding to the logical address indicated by the write request, and updates the physical address fetched from the FIFO queue 923 (step 1207).
Then, the read-write controller 921 in the information management table 926, the logical address corresponding to physical address fetched from the FIFO queue 923 is updated to a logical address indicated by the write request (step 1208).
On the other hand, if the written flag is OFF (step 1201, NO), the read and write control unit 921, the block indicated by the physical address corresponding to the logical address indicated by the write request writes the write data indicating the write request (step 1209). Then, the read-write controller 921, the address conversion table 925, changes the write flag corresponding to the logical address indicated by the write request to ON (step 1210).
Figure 13 is a flowchart showing an example of data movement control by the data movement control unit 922 of FIG. Data movement control unit 922 starts the data movement control at a predetermined timing. The predetermined timing, for example, can be used the following timing.
(1) Regular (2) read or write request idle time control is not performed in the CPU 911 (3) when the write request from CPU 911 has a predetermined number of occurrences
First, the data migration control unit 922 sets a variable n representing the number of the logical address to 1 (step 1301), refers to the address conversion table 925, reads the physical address corresponding to the logical address Ln (step 1302) .
Next, the data migration control unit 922 refers to the information management table 926, reads the value of the counter corresponding to the read physical address is set to the variable C1 (step 1303).
Next, the data migration control unit 922, n checks whether or not 1 (step 1304). When n is 1 (step 1304, YES), the data movement control unit 922 sets the value of the variable C1 to variable C2 (step 1306), and sets the physical address Ln variable X (step 1307).
Next, the data migration control unit 922, n is checked whether M (step 1308), if n is not M (step 1308, NO), increments n by 1 (step 1310), step 1302 to repeat the subsequent processing.
If n is not 1 (step 1304, NO), the data movement control unit 922 compares the C1 and C2 (Step 1305). If C1 is greater than C2 (step 1305, YES), the data movement control unit 922 performs step 1306 and subsequent steps. Thus, C2 Gayori updated on a large counter value, X is updated to a logical address corresponding to the counter value updated. On the other hand, if C1 is C2 or less (step 1305, NO), the data movement control unit 922 performs step 1308 and subsequent steps.
When the n has reached M (step 1308, YES), the data movement request for the logical address X, and issues the read-write control unit 921 (step 1309).
According to such a data movement control, at predetermined timing, the counter data of the largest block write count indicated by moving to the spare block, it is possible to change the movement source block to a spare block. Therefore, it is possible to reduce the frequency of use of the largest block write count.
Incidentally, according to the data movement control in FIG. 13, when the counter of all blocks have the same value, since X is not updated while the L1, data migration request for the logical address L1 has been issued. However, this case is the frequency of use of all the blocks are the same, the data movement control unit 922 may issue a data migration request for the logical address other than L1.
14 and 15, the controller 912 from the CPU 911, shows a first example of the write control when receiving the write request for a logical address L4. Procedure of the write control are as follows.
Processing 1401: read-write control section 921 refers to the address conversion table 925, the write flag corresponding to the logical address L4 shown write request detects that is OFF.
Processing 1402: read-write control section 921 refers to the address conversion table 925, a physical address corresponding to the logical address L4 detects that a P4.
Processing 1403: read and write control unit 921, a block storage unit 913 corresponding to the physical address P4, writes the write data indicating a write request.
Processing 1404: read and write control unit 921 updates the write flag corresponding to the logical address L4 of the address translation table 925 to ON.
16 and 17, the controller 912 from the CPU 911, illustrates a second example of the write control when receiving the write request for a logical address L4. Procedure of the write control are as follows.
Processing 1601: read and write control unit 921 detects that refers to the address conversion table 925, the write flag corresponding to the logical address L4 indicated write request is ON.
Processing 1602: read-write control section 921 refers to the address conversion table 925, a physical address corresponding to the logical address L4 shown write request detects that a P4.
Processing 1603: read and write control unit 921 erases the data of the block in the storage device 913 corresponding to the physical address P4.
Processing 1604: read and write control unit 921 extracts the physical address PM + 1 of the head from the FIFO queue 923.
Processing 1605: read and write control unit 921, the spare block of the storage device 913 corresponding to the physical address PM + 1, writes the write data indicating a write request.
Processing 1606: read and write control unit 921 stores the physical addresses P4 to the FIFO queue 923.
1607: read and write control unit 921, the value of the counter corresponding to the physical address P4 information management table 926 is incremented by one. Thus, the value of the counter is updated from 1 to 2.
Processing 1608: read and write control unit 921 updates the logical address corresponding to physical address P4 information management table 926 in the L0.
Processing 1609: read and write control unit 921 updates the physical address corresponding to the logical address L4 of the address translation table 925 in PM + 1.
Processing 1610: read and write control unit 921 updates the logical addresses L4 corresponding to the physical address PM + 1 information management table 926.
18 and 19, the controller 912 from the data movement control unit 922 shows a first example of the write control when receiving the data migration request for the logical addresses L4. In this example, a state value of the counter of the entire block is 1 information management table 926, instead of the data movement request for the logical address L1, data movement request is issued to the logical address L4. Procedure of the write control are as follows.
Processing 1801: read-write control section 921 refers to the address conversion table 925, detects that the write flag is ON corresponding to the logical address L4 data movement request indicates.
Processing 1802: read-write control section 921 refers to the address conversion table 925, a physical address corresponding to the logical address L4 data movement request indicates detects that a P4.
Processing 1803: read-write controller 921 reads data from the block of the storage device 913 corresponding to the physical address P4.
Processing 1804: read and write control unit 921 erases the data of the block in the storage device 913 corresponding to the physical address P4.
Processing 1805: read and write control unit 921 extracts the physical address PM + L + 1 of the head from the FIFO queue 924.
Processing 1806: read and write control unit 921, the spare block of the storage device 913 corresponding to the physical address PM + L + 1, and writes the read data from the block corresponding to the physical address P4.
Processing 1807: read and write control unit 921 stores the physical addresses P4 to the FIFO queue 924.
Processing 1808: read and write control unit 921, the value of the counter corresponding to the physical address P4 information management table 926 is incremented by one. Thus, the value of the counter is updated from 1 to 2.
Processing 1809: read and write control unit 921 updates the logical address corresponding to physical address P4 information management table 926 in the L0.
Processing 1810: read and write control unit 921 updates the physical address corresponding to the logical address L4 of the address translation table 925 in PM + L + 1.
Processing 1811: read and write control unit 921 updates the logical addresses L4 corresponding to the physical address PM + L + 1 of the information management table 926.
20 and 21, the controller 912 from the data movement control unit 922 shows a second example of the write control when receiving the data migration request for the logical addresses L4. Procedure of the write control are as follows.
Processing 2001: read-write control section 921 refers to the address conversion table 925, the write flag corresponding to the logical address L4 data movement request indicates detects that is OFF.
Processing 2002: read-write control section 921 refers to the address conversion table 925, a physical address corresponding to the logical address L4 data movement request indicates detects that a P4. In this case, since the block corresponding to the physical address P4 is no data, read and write control unit 921 does not perform the reading and erasing data in that block.
Processing 2003: read and write control unit 921 extracts the physical address PM + L + 1 of the head from the FIFO queue 924.
Processing 2004: read and write control unit 921 stores the physical addresses P4 to the FIFO queue 924.
Processing 2005: read and write control unit 921 updates the logical address corresponding to physical address P4 information management table 926 in the L0.
Processing 2006: read and write control unit 921 updates the physical address corresponding to the logical address L4 of the address translation table 925 in PM + L + 1.
Processing 2007: read and write control unit 921 updates the logical addresses L4 corresponding to the physical address PM + L + 1 of the information management table 926.
Meanwhile, CPU 911, in addition to read and write requests may be issued an erase request for erasing the data of the block to the controller 912.
22 and 23, the controller 912 CPU 911, shows an example of the write control when receiving the deletion request for the logical addresses L4. Procedure of the write control are as follows.
Processing 2201: read-write control section 921 refers to the address conversion table 925, detects that the write flag corresponding to the logical address L4 shown erase request is ON.
Processing 2202: read-write control section 921 refers to the address conversion table 925, a physical address corresponding to the logical address L4 shown erase request detects that a P4.
Processing 2203: read and write control unit 921 erases the data of the block in the storage device 913 corresponding to the physical address P4.
Processing 2204: read and write control unit 921 extracts the physical address PM + 1 of the head from the FIFO queue 923.
Processing 2205: read and write control unit 921 stores the physical addresses P4 to the FIFO queue 923.
Processing 2206: read and write control unit 921, the value of the counter corresponding to the physical address P4 information management table 926 is incremented by one. Thus, the value of the counter is updated from 1 to 2.
Processing 2207: read and write control unit 921 updates the logical address corresponding to physical address P4 information management table 926 in the L0.
Processing 2208: read and write control unit 921 updates the physical address corresponding to the logical address L4 of the address translation table 925 in PM + 1.
Processing 2209: read and write control unit 921 updates the write flag corresponding to the logical address L4 of the address translation table 925 to OFF.
Processing 2210: read and write control unit 921 updates the logical addresses L4 corresponding to the physical address PM + 1 information management table 926.
According to the write controller in the information processing apparatus 901 of FIG. 9, the physical address of a large block of write count which is changed to the spare block on the basis of the data movement request from the data movement control unit 922 is always stored in the FIFO queue 924 . On the other hand, the write destination based on the write request from the CPU 911, the spare blocks are used always shown the physical address in the FIFO queue 923. Therefore, the frequency of large spare block number of write operations is used as the write destination based on the write request becomes low.
By operating the data migration control unit 922 at a predetermined timing, by inhibiting the writing of the CPU911 for large blocks of write count, it is possible to effectively equalize the write count of each block. Since it is not necessary to determine the number of writing when data is written based on the write request, it does not write performance is degraded. Therefore, it is possible to enhance the wear leveling effect while maintaining write performance.
Figure 24 shows a second specific example of the information processing apparatus 701 of FIG. The information processing apparatus 2401 in FIG. 24 has a configuration obtained by replacing the controller 912 in FIG. 9 to the controller 2411. The controller 2411 corresponds to the controller 721 of FIG.
The controller 2411 includes read-write control section 2421, the data migration control unit 922, FIFO queue 923, FIFO queue 924, FIFO queue 2422, counter register 2423, an address conversion table 925, and the information management table 926.
Unlike the information processing apparatus 901 of FIG. 9, FIFO queue 924, K pieces (K is 1 or more N-M-L-1 an integer) can store a physical address corresponding to the spare block of.
FIFO queue 2422 is a storage unit for storing the physical address, it can be stored a physical address corresponding to N-M-L-K-number of the spare blocks. Then, FIFO queue 2422 sequentially outputs the stored physical address from that stored previously.
Counter register 2423, in the information management table 926 stores the maximum value of the counter is updated based on the data movement request from the data movement control unit 922.
Read and write control unit 2421 refers to the address conversion table 925 converts a logical address indicated by the read or write request from the CPU911 into a physical address. Then, the read-write control unit 2421 controls the writing of data to the read or the resulting physical address of the data of the obtained physical address.
Read and write control unit 2421, when erasing the data block of the storage device 913, the counter of the corresponding physical address information management table 926 is incremented by one. In case of receiving the data movement request from the data movement control unit 922, if the value of the counter after the update is larger than the value stored in the counter register 2423, read and write control unit 2421 is stored in the counter register 2423 to update the value of the value of the counter after the update.
Read and write control unit 2421, upon receiving a write request from the CPU 911, it retrieves the physical addresses from the FIFO queue 923 performs control to store the different physical addresses to the FIFO queue 923.
Read and write control unit 2421, when receiving the data movement request from the data movement control unit 922 performs control for the FIFO queue 924 or FIFO queue 2422 retrieve the physical address. At this time, the read-write control section 2421, based on a result of comparison between the values ​​of the counter register 2423 for counter information management table 926, selects one of the FIFO queue 924 or FIFO queue 2422. Then, the read-write control section 2421 performs control to store the different physical addresses to the selected FIFO queue.
Operation of the data movement control unit 922 are the same as those of the information processing apparatus 901 of FIG. 9.
FIGS. 25 to 27 are flowcharts showing an example of the write control of the read-write control section 2421 of FIG. 24.
Read and write control unit 2421 receives the data movement request from the write request or data movement control unit 922 from the CPU 911, the request received is checked whether it is a request (step 2501).
If the received request is a data movement request (step 2501, YES), the read-write control unit 2421 then refers to the address conversion table 925. Then, the read-write control unit 2421, the write flag corresponding to the logical address data move request indicated checks whether or not ON (step 2502).
If the written flag is ON (step 2502, YES), the read-write control section 2421 reads data from the block indicated by the physical address corresponding to the logical address data movement request indicates (step 2503). Then, the read-write control unit 2421 erases the data of the block (step 2504), the information management table 926, increments the counter corresponding to the physical address of the block which has been erased by one (step 2505).
Then, the read-write control unit 2421 compares the value of the incremented counter, the value of the counter register 2423 (step 2506).
If the value of the incremented counter is greater than the value of the counter register 2423 (step 2506, YES), the read-write control unit 2421 extracts the physical address head from FIFO queue 2422 (step 2507). Then, the read-write control unit 2421 writes the data read in step 2503, the block indicated by the physical address fetched (step 2508). Thus, the data block corresponding to the logical address data movement request indicates, it can be moved to a spare block corresponding to the physical address fetched from the FIFO queue 2422.
Then, the read-write control unit 2421, a physical address corresponding to the logical address data move request shown, stored in the FIFO queue 2422 (step 2509).
Then, the read-write control unit 2421 updates the value of the counter increments the value of counter register 2423 (step 2510). Then, the read-write control unit 2421, the information management table 926, and updates the logical address corresponding to the physical address stored in the FIFO queue 2422 to L0 (Step 2511).
Then, the read-write control unit 2421, the address conversion table 925, a physical address corresponding to the logical address data movement request indicates to update the physical address fetched from the FIFO queue 2422 (step 2512).
Then, the read-write control unit 2421, the information management table 926, the logical address corresponding to physical address fetched from the FIFO queue 2422, updates to the logical address data movement request indicates (step 2513).
On the other hand, if the value of the incremented counter is less than or equal to the value of the counter register 2423 (step 2506, NO), the read-write control unit 2421 extracts the physical address head from FIFO queue 924 (step 2514). Then, the read-write control unit 2421 writes the data read in step 2503, the block indicated by the physical address fetched (step 2515). Thus, the data block corresponding to the logical address data movement request indicates, it can be moved to a spare block corresponding to the physical address fetched from the FIFO queue 924.
Then, the read-write control unit 2421, a physical address corresponding to the logical address data move request shown, stored in the FIFO queue 924 (step 2516).
Then, the read-write control unit 2421, the information management table 926, and updates the logical address corresponding to the physical address stored in the FIFO queue 924 in L0 (Step 2511).
Then, the read-write control unit 2421, the address conversion table 925, a physical address corresponding to the logical address data movement request indicates to update the physical address fetched from the FIFO queue 924 (step 2512).
Then, the read-write control unit 2421, the information management table 926, the logical address corresponding to physical address fetched from the FIFO queue 924 is updated to a logical address where the data move request shown (step 2513).
If the written flag is OFF (step 2502, NO), the read-write controller 2421 refers to the address conversion table 925, and acquires a physical address corresponding to the logical address data movement request indicates (step 2601). Then, the read-write control unit 2421 compares the value of the counter corresponding to the acquired physical address information management table 926, the value of the counter register 2423.
Information Management If the value of the counter table 926 is greater than the value of the counter register 2423 (step 2601, YES), the read-write control unit 2421 extracts the physical address head from FIFO queue 2422 (step 2602). Then, the read-write control unit 2421, a physical address corresponding to the logical address data move request shown, stored in the FIFO queue 2422 (step 2603).
Then, the read-write control unit 2421, the information management table 926, and updates the logical address corresponding to the physical address stored in the FIFO queue 2422 to L0 (Step 2604).
Then, the read-write control unit 2421, the address conversion table 925, a physical address corresponding to the logical address data movement request indicates to update the physical address fetched from the FIFO queue 2422 (step 2605).
Then, the read-write control unit 2421, the information management table 926, the logical address corresponding to physical address fetched from the FIFO queue 2422, updates to the logical address data movement request indicates (step 2606).
On the other hand, when the value of the counter information management table 926 is less than the value of the counter register 2423 (step 2601, NO), the read-write control unit 2421 extracts the physical address of the beginning of FIFO queue 924 (step 2607). Then, the read-write control unit 2421, a physical address corresponding to the logical address data move request shown, stored in the FIFO queue 924 (step 2608).
Then, the read-write control unit 2421, the information management table 926, and updates the logical address corresponding to the physical address stored in the FIFO queue 924 in L0 (Step 2604).
Then, the read-write control unit 2421, the address conversion table 925, a physical address corresponding to the logical address data movement request indicates to update the physical address fetched from the FIFO queue 924 (step 2605).
Then, the read-write control unit 2421, the information management table 926, the logical address corresponding to physical address fetched from the FIFO queue 924 is updated to a logical address where the data move request shown (step 2606).
If the received request is a write request (step 2501, NO), the read-write control unit 2421 performs the process of FIG. 27. Processing of steps 2701 to S 2710 in FIG. 27 is the same as the processing in steps 1201 to step 1210 in FIG. 12.
28 and 29, the controller 2411 from the data movement control unit 922 shows a first example of the write control when receiving the data migration request for the logical addresses L4. In this example, the value of the counter 5 corresponding to the physical address PN information management table 926, in a state the value of the counter of the block other than the PN is 1, instead of the data movement request for the logical address L1, logic data movement request is issued for the address L4. Procedure of the write control are as follows.
Processing 2801: read-write control unit 2421 refers to the address conversion table 925, it detects that the write flag is ON corresponding to the logical address L4 data movement request indicates.
Processing 2802: read-write control unit 2421 refers to the address conversion table 925, a physical address corresponding to the logical address L4 data movement request indicates detects that a P4.
Processing 2803: read-write control section 2421 reads data from the block of the storage device 913 corresponding to the physical address P4.
Processing 2804: read-write control unit 2421 erases the data block of the storage device 913 corresponding to the physical address P4.
Processing 2805: read-write control unit 2421, the value of the counter corresponding to the physical address P4 information management table 926 is incremented by one. Thus, the value of the counter is updated from 1 to 2.
Processing 2806: read-write control unit 2421 refers to the counter register 2423, the value of the counter register 2423 detects that a 5.
Processing 2807: read-write control unit 2421 compares the value 5 of the value 2 of the counter of the updated counter register 2423, since towards the value 2 of the counter after the update is small, selecting the FIFO queue 924. Then, the read-write control unit 2421 extracts the physical addresses PM + L + 1 of the head from the FIFO queue 924.
Processing 2808: read-write control unit 2421, the spare block of the storage device 913 corresponding to the physical address PM + L + 1, and writes the read data from the block corresponding to the physical address P4.
Processing 2809: read-write control section 2421 stores the physical addresses P4 to the FIFO queue 924.
Processing 2810: read-write control unit 2421 updates the logical address corresponding to physical address P4 information management table 926 in the L0.
Processing 2811: read-write control unit 2421 updates the physical address corresponding to the logical address L4 of the address translation table 925 in PM + L + 1.
Processing 2812: read-write control unit 2421 updates the logical addresses L4 corresponding to the physical address PM + L + 1 of the information management table 926.
30 and 31, the controller 2411 from the data movement control unit 922 shows a second example of the write control when receiving the data migration request for the logical addresses L4. In this example, a state value of the counter 4 that corresponds to the physical address P4 information management table 926 is the maximum value, the data move request is issued to the logical address L4. Procedure of the write control are as follows.
Processing 3001: read-write control unit 2421 refers to the address conversion table 925, it detects that the write flag is ON corresponding to the logical address L4 data movement request indicates.
Processing 3002: read-write control unit 2421 refers to the address conversion table 925, a physical address corresponding to the logical address L4 data movement request indicates detects that a P4.
Processing 3003: read-write control section 2421 reads data from the block of the storage device 913 corresponding to the physical address P4.
Processing 3004: read-write control unit 2421 erases the data block of the storage device 913 corresponding to the physical address P4.
Processing 3005: read-write control unit 2421, the value of the counter corresponding to the physical address P4 information management table 926 is incremented by one. Thus, the value of the counter is updated from 4 to 5.
Processing 3006: read-write control unit 2421 refers to the counter register 2423, the value of the counter register 2423 detects that a 2.
Processing 3007: read-write control unit 2421 compares the value 2 and value 5 of the counter after the update counter register 2423, since towards the value 5 in the counter after the update is large, it selects a FIFO queue 2422. Then, the read-write control unit 2421 extracts the physical addresses PM + L + K + 1 of the head from the FIFO queue 2422.
Processing 3008: read-write control unit 2421, the spare block of the physical address PM + L + K + memory device 913 that corresponds to 1, writes the read data from the block corresponding to the physical address P4.
Processing 3009: read-write control section 2421 stores the physical addresses P4 to the FIFO queue 2422.
Processing 3010: read-write control unit 2421 updates the value of the counter register 2423 to the value 5 of the counter after the update.
Processing 3011: read-write control unit 2421 updates the logical address corresponding to physical address P4 information management table 926 in the L0.
Processing 3012: read-write control unit 2421 updates the physical address corresponding to the logical address L4 of the address translation table 925 in PM + L + K + 1.
Processing 3013: read-write control unit 2421 updates the logical addresses L4 corresponding to the physical address PM + L + K + 1 of the information management table 926.
According to the write controller in the information processing apparatus 2401 in FIG. 24, FIFO queue 2422 is provided in addition to the FIFO queue 924, the physical address of the block that exceeds the maximum value of the past number of writes is stored in the FIFO queue 2422. Thus, the frequency of use of the block indicated by the physical address of the FIFO queue 2422, can be lower than the frequency of use of the block indicated by the physical address of the FIFO queue 924. Therefore, it is possible to enhance the wear leveling effect than the information processing apparatus 901 of FIG. 9.
The information processing apparatus 701 of FIG. 7, the configuration of the information processing apparatus 2401 of the information processing apparatus 901, and FIG. 24 in FIG. 9 is only an example, omit some of the components depending on the application and conditions of the information processing apparatus or it may be changed.
For example, if the read and write control unit 921 of FIG. 9 contains the function of the data movement control unit 922, it can be omitted data movement control unit 922 of FIG. Similarly, when the read-write control section 2421 of FIG. 24 contains the function of the data movement control unit 922, it can be omitted data movement control unit 922 of FIG. 24. Also, if it is possible to add information in the information management table 926 in FIG. 9 and FIG. 24 in the address conversion table 925, it is possible to omit the information management table 926.
The controller 2411 of FIG. 24, may be further added one or more FIFO queue. By adding a FIFO queue, it is possible to further enhance the wear leveling effect.
8, the flowchart shown in FIGS. 11 to 13, and 25 through 27 is only an example, it may be omitted or changed a part of the processing according to the configuration and conditions of the information processing apparatus. For example, the order of processing in steps 1108 to S 1110 in FIG. 11, but may be any order. Similarly, the order of the processing of step 1206 through step 1208 in FIG. 12, may be any order.
The order of the processing of steps 2510 to S 2513 in FIG. 25, may be any order. The order of the processing of steps 2604 to S 2606 in FIG. 26, may be any order. The order of the processing of steps 2706 to S 2708 in FIG. 27, may be any order.
The data movement control in FIG. 13, instead of issuing a data migration request for the logical address of the largest block write count, number of times of writing may issue a data migration request for the logical address of the larger block than the predetermined block .
Controller 2411 of the control unit 721, the controller 921 of FIG. 9, and 24 of Figure 7 also can be implemented as a hardware circuit, as shown in FIG. 32, realized as a processing circuit (computer) that executes programs it is also possible.
Processing circuit of Figure 32 is, Micro-Processing Unit (MPU) 3201, a memory 3202, an interface 3203, and an interface 3204. These components are interconnected by a bus 3205.
Memory 3202, for example, Read Only Memory (ROM), Random Access Memory (RAM), a semiconductor memory such as a flash memory, stores the write control program and data used in the write control. Memory 3202 may also be used as a FIFO queue 923, FIFO queue 924, FIFO queue 2422, counter register 2423, an address conversion table 925, and information management table 926 in FIG. 9 and FIG. 24.
MPU3201 (processor), for example, by executing the write control program using the memory 3202, operates as a read-write controller 921 and a data migration control unit 922 of FIG. MPU3201 by executing the write control program may also operate as a read-write control section 2421 and the data migration control unit 922 of FIG. 24.
Interface 3203 is a communication interface that communicates with CPU911 in FIGS. 9 and 24. Interface 3203, a read request from the CPU 911, a write request, receive an indication of such erasure request, the requested read data is transmitted to the CPU 911 a response including the processing result.
Interface 3204 is a communication interface that communicates with the storage device 913 of FIG. 9 and FIG. 24. Interface 3204, read request, write request, transmits an instruction such as a deletion request to the storage device 913 receives the read data, a response including the processing result from the storage device 913.
Processing circuit of Figure 32, the write control program stored in the auxiliary storage device or a portable recording medium, can also be used by being loaded into the memory 3202.
The auxiliary storage device, for example, a magnetic disk device, a magneto-optical disk device, a tape device or the like. The external storage device may be a hard disk drive. Portable recording medium, for example, a memory device, a flexible disk, an optical disk, a magneto-optical disk, or the like. The portable recording media, Compact Disk Read Only Memory (CD-ROM), Digital Versatile Disk (DVD), flash memory, may be a Universal Serial Bus (USB) memory, or the like.
Thus, the recording medium computer-readable storing a write control program and data used in the write control memory 3202, an auxiliary storage device, and as a portable recording medium, physical (non-transitory ) includes the recording medium.
Have been described in detail embodiments of the disclosure and its advantages, one skilled in the art, der capable of without departing from the scope of the invention as clearly described in the claims, various modifications, additions, omissions wax.
A storage device including a plurality of blocks,
It controls the writing of data to the plurality of blocks, a first number of write operations of the first block to store the data of the plurality of blocks, than the second number of write operations of the second block for storing data If so, a control unit for the data of the first block is moved to the third block of the spare of the plurality of blocks, changing the first block to a spare block,
A first storage unit for storing identification information of the spare block of the plurality of blocks,
A second storage unit for storing identification information of the spare block of the plurality of blocks,
The first storage unit stores the identification information of the fourth block,
The second storage unit stores the identification information of the third block,
When receiving the write request, erase the data of the fifth block corresponding to the logical address which the write request is shown, the removed identification information of the fourth block from the first storage unit, indicated by the write request write the write data to the fourth block, and stores the identification information of the fifth block in the first storage unit,
If the data of the first block is moved to the third block, it takes out the identification information of said third block from said second storage section, the first block identification information the second of the information processing apparatus according to claim 1, wherein the storing in the storage unit.
Wherein, when the first write count is the largest in number of writes of the plurality of blocks, claim 1, wherein the moving data of the first block to the third block or information processing apparatus according.
Further comprising a third storage unit for storing identification information of the spare block of the plurality of blocks,
The third storage unit stores the identification information of the sixth block,
Wherein greater than the first number of times of writing said second write times, if the third write count obtained by adding 1 to the first write count is smaller than a predetermined value, said from said second storage unit the taking out the identification information of the third block, the data of the first block is moved to the third block, and stores the identification information of the first block to the second storage section,
Wherein greater than the first number of times of writing said second write times, when the third write count is greater than the predetermined value, retrieves the identification information of the sixth block from the third storage unit, the data of the first block is moved to the sixth block, any one of claims 1 to 3 the identification information of the first block, characterized in that stored in the third storage unit the information processing apparatus according to.
Wherein, when the data of the first block is moved to the sixth block, the information processing apparatus according to claim 4, wherein updating the predetermined value in said third number of writes .
Controls the writing of data to a plurality of blocks included in the storage device, a first number of write operations of the first block to store the data of the plurality of blocks, a second of the second block for storing data If greater than the number of times of writing, characterized in that it comprises a control unit for changing the data of the first block is moved to the third block of the spare of the plurality of blocks, the first block to a spare block write control circuit to.
If the data of the first block is moved to the third block, it takes out the identification information of said third block from said second storage section, the first block identification information the second of the write control circuit according to claim 6, wherein the storing in the storage unit.
Wherein greater than the first number of times of writing said second write times, when the third write count is greater than the predetermined value, retrieves the identification information of the sixth block from the third storage unit, wherein the data of the first block is moved to the sixth block, the write control circuit according to claim 7, wherein the identification information of the first block is stored in the third storage unit.
Controls the writing of data to a plurality of blocks included in the storage device,
First write count of the first block to store the data of the plurality of blocks is greater than the second number of write operations of the second block for storing data, said data of the first block is moved to the third block of the spare of the plurality of blocks, changing the first block to a spare block,
The write control method, characterized in that.
First storage unit for storing identification information of the spare block of the plurality of blocks, second to store the identification information of the fourth block, and stores the identification information of the spare block of said plurality of blocks storage unit stores the identification information of the third block,
If the data of the first block is moved to the third block, it takes out the identification information of said third block from said second storage section, the first block identification information the second of write control method according to claim 9, wherein the storing in the storage unit.
The third storage unit for storing identification information of the spare block of the plurality of blocks, stores the identification information of the sixth block,
Wherein greater than the first number of times of writing said second write times, when the third write count is greater than the predetermined value, retrieves the identification information of the sixth block from the third storage unit, wherein the data of the first block is moved to the sixth block, the write control method according to claim 10, wherein the identification information of the first block is stored in the third storage unit.
Write control program for executing the processing to the computer.
If the data of the first block is moved to the third block, it takes out the identification information of said third block from said second storage section, the first block identification information the second of claim 12, wherein the write control program, characterized in that stored in the storage unit.
Wherein greater than the first number of times of writing said second write times, when the third write count is greater than the predetermined value, retrieves the identification information of the sixth block from the third storage unit, wherein the data of the first block is moved to the sixth block, claim 13, wherein the write control program of the identification information of the first block, characterized in that stored in the third storage unit.
PCT/JP2014/063125 2014-05-16 2014-05-16 Information processing device, write control circuit, write control method, and write control program WO2015173966A1 (en)
PCT/JP2014/063125 WO2015173966A1 (en) 2014-05-16 2014-05-16 Information processing device, write control circuit, write control method, and write control program
JP2015531387A JP5943153B2 (en) 2014-05-16 2014-05-16 The information processing apparatus, a write control circuit, the write control method, and programming program
WO2015173966A1 true true WO2015173966A1 (en) 2015-11-19
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JP (1) JP5943153B2 (en)
WO (1) WO2015173966A1 (en)
JP2005275722A (en) * 2004-03-24 2005-10-06 Kyocera Corp Electronic device
JP2010079659A (en) * 2008-09-26 2010-04-08 Nec Personal Products Co Ltd Apparatus for prolonging life of flash memory, and method and program for the same
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US20080126891A1 (en) 2008-05-29 Memory lifetime gauging system, method and computer program product
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