Source: http://www.google.com/patents/US6696859?dq=5,579,517
Timestamp: 2016-12-09 16:08:20
Document Index: 667307913

Matched Legal Cases: ['art 30', 'art 32', 'art 30', 'art 30', 'art 30', 'art 30', 'art 32']

Patent US6696859 - Input/output interfacing circuit, input/output interface, and semiconductor ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThe current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents...http://www.google.com/patents/US6696859?utm_source=gb-gplus-sharePatent US6696859 - Input/output interfacing circuit, input/output interface, and semiconductor device having input/out interfacing circuitAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6696859 B2Publication typeGrantApplication numberUS 10/178,519Publication dateFeb 24, 2004Filing dateJun 25, 2002Priority dateNov 8, 2000Fee statusPaidAlso published asUS6525570, US6876225, US20020053926, US20020158667, US20020175708Publication number10178519, 178519, US 6696859 B2, US 6696859B2, US-B2-6696859, US6696859 B2, US6696859B2InventorsYoshimasa Yagishita, Toshiya UchidaOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (7), Referenced by (6), Classifications (11), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetInput/output interfacing circuit, input/output interface, and semiconductor device having input/out interfacing circuit
US 6696859 B2Abstract
What is claimed is: 1. A semiconductor device comprising an input/output interfacing circuit including:
a reference current generating unit for generating a plurality of reference currents; a plurality of current comparing units for respectively comparing output current supplied from exterior of the semiconductor device in accordance to logic values, with said reference currents; and a data restoring unit for restoring said logic values according to comparison results from said current comparing units. 2. The semiconductor device comprising the input/output interfacing circuit according to claim 1, comprising:
a dummy current generating unit for generating standard current at an input; and a correcting unit for controlling said reference current generating unit to correct values of said reference currents according to a difference between said standard current at an output which is supplied from the exterior and said standard current at the input. 3. The semiconductor device comprising the input/output interfacing circuit according to claim 1, comprising:
a first current source for supplying a current to said reference current generating unit; and a second current source for supplying a current to an external device which generates said output current. 4. The semiconductor device comprising the input/output interfacing circuit according to claim 1, wherein said current comparing units compare said reference currents with said output current in synchronization with a timing signal supplied from the exterior, respectively.
This is Division of application Ser. No. 09/820,719 filed Mar. 30, 2000 U.S. Pat. No. 6,525,570. The disclosure of the prior application(s) is hereby incorporated by reference herein in its entirety.
The nMOSs 20 a, 20 b, 20 c and 20 d are formed so as to make the channel lengths hereof the same. For this reason, the current drivability of the nMOSs 20 a, 20 b, 20 c and 20 d is increased two times by two times in proportion to the gate width. Output data D3 through D0 are, respectively, provided into the gates of the nMOSs 20 a, 20 b, 20 c and 20 d. That is, since the gate widths of the nMOSs 20 a, 20 b, 20 c and 20 d are set with respect to the weighting of the output data D3 through D0, the output current IOUT that is generated in the output circuit 10 has sixteen types corresponding to the binary number of output data D3 through D0.
The accepting circuit 28 of the input circuit 12 is composed of a latch part 30 and an output part 32. The latch part 30 includes CMOS inverters 30 a and 30 b that constitutes a latch, to which an input and an output are alternately connected, a feedback nMOS 30 c that receives inverted logic of the output of the CMOS inverter 30 a by the gate, a feedback nMOS 30 d that receives inverted logic of the output of the CMOS inverter 30 b by the gate, nMOS 30 e and 30 f whose gates are, respectively, connected to the node ND01 and ND02, pMOS 30 g and 30 h that, where the internal clock signal ICLK being a timing signal is at a low level, make the outputs of the CMOS inverters 30 a and 30 b into a high level, and inactivates the latch, and an nMOS 30 i that, where the internal clock signal ICLK is at a high level, connects the latch part 30 to the power supply (ground line VSS), and activates the latch part 30.
The latch part 30 accepts the comparison results by the current comparing unit 24, which is expressed in terms of a potential difference between the nodes ND01 and ND02, in synchronization with a rise edge of the internal clock signal ICLK, and outputs the accepted information to the output part 32.
For example, when drivability of the transistor of the semiconductor device in the transmitter is large, the output current IOUT that is generated in the current generating unit 36 shown in FIG. 9 is larger than the current flowing in the nMOS produced under standard producing conditions (typical condition). Therefore, the relative values (FIGS. 1 through 8) of the drivability of the nMOSs of the output circuit 34 shown in FIG. 10 may change, respectively, compared with the relative values (figures 14.5 through 0.5) of the drivability of the nMOSs in the reference current generating unit 42 shown in FIG. 12. As the result, there is a possibility that the comparison in the current comparing units 24 is not correctly carried out.
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