Source: https://patents.google.com/patent/JP2006100409A/en
Timestamp: 2019-12-11 03:09:51
Document Index: 612248882

Matched Legal Cases: ['art 39', 'art 39', 'art 39', 'art 39', 'art 39', 'art, 39', 'art, 40']

JP2006100409A - Semiconductor device and its manufacturing method - Google Patents
JP2006100409A
JP2006100409A JP2004282336A JP2004282336A JP2006100409A JP 2006100409 A JP2006100409 A JP 2006100409A JP 2004282336 A JP2004282336 A JP 2004282336A JP 2004282336 A JP2004282336 A JP 2004282336A JP 2006100409 A JP2006100409 A JP 2006100409A
JP2004282336A
JP4410075B2 (en
紀久子 杉前
2004-09-28 Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
2006-04-13 Publication of JP2006100409A publication Critical patent/JP2006100409A/en
2010-02-03 Publication of JP4410075B2 publication Critical patent/JP4410075B2/en
A semiconductor device and a method of manufacturing the same are provided which are advantageous for miniaturization and can improve reliability.
A semiconductor device includes a transistor ST including a metal layer 31 on a gate electrode, a first barrier film 23, a first insulating layer 24, a second barrier film 25, and a second insulating layer 26 which are sequentially provided. The second barrier film has a first width W1 and extends in the first direction; the second barrier film has a bottom 40 through the second insulating layer; and the bottom is in the first direction. A contact hole upper portion 39-1 having a second width W2 larger than the first width in a second direction crossing the first through hole, and penetrating the first insulating layer and the first barrier film from the upper portion of the contact hole through the groove. Then, a conductor hole is continuously embedded in the contact hole lower portion 39-2 provided on the diffusion layer and having an upper surface of the first width W1 in the second direction, and the contact hole upper portion and the contact hole lower portion. Contact 39 comprises a.
The present invention relates to a semiconductor device and a method for manufacturing the same, and is applied to, for example, a selection transistor for selecting a memory cell transistor in which current paths of a NAND flash memory are connected in series.
With the recent miniaturization of cells, contacts that electrically connect cell diffusion layers and the like are also becoming increasingly miniaturized. Furthermore, as the generation of cells progresses, it is difficult to make contacts finer by so-called lithography technology.
Therefore, for example, in Patent Document 1, an etching mask film 13a having an opening pattern corresponding to the pattern of the diffusion layer 7 acting as a source / drain is formed on the first insulating film 11, and the etching mask film 13a is used as a mask. A method is disclosed in which the first insulating film 11 is etched to the surface of the silicide layer 8 on the diffusion layer 7 to form a contact hole 14 a on the diffusion layer 7.
However, in the case of the above method, if the controllability of the etching process is not sufficient, the silicide layer 8 on the diffusion layer 7 is scraped or the reaction between the silicide layer 8 and the insulating layer 2 causes the silicide layer 8 to be formed by the cell. There is a problem in that the resistance value varies and the reliability decreases.
Furthermore, the structure having the silicide layer 8 on the conventional diffusion layer 7 has a problem that it is disadvantageous for miniaturization due to the following (1) and (2).
(1) When the silicide layer 8 and the gate insulating film 2 are close to each other, a substance (for example, cobalt or the like) in the silicide layer 8 affects the film quality of the gate insulating film 2, and the insulating property of the gate insulating film is reduced. Reduce reliability.
(2) The silicide layer 8 on the diffusion layer generates a so-called junction leak.
In addition, the silicide layer 8 on the diffusion layer 7 reacts with the gate insulating film 2 to cause a short circuit between the silicide layer 8 and the gate electrode 6, thereby causing a problem that the insulating property is lowered.
As described above, the conventional semiconductor device is disadvantageous for miniaturization, and the silicide layer on the diffusion layer reacts with the gate insulating film, and the silicide layer and the gate electrode are short-circuited. However, there is a situation that reliability is lowered.
Further, in the conventional method of manufacturing a semiconductor device, if the controllability of the etching process for forming the contact hole is not sufficient, the silicide layer on the diffusion layer is scraped or the silicide layer and the insulating layer react to cause a cell. As a result, the resistance value of the silicide layer varies and there is a problem that the reliability is lowered.
JP 2002-118166 A Specification
In view of the above circumstances, the present invention provides a semiconductor device that is advantageous for miniaturization and that can improve reliability and a method for manufacturing the same.
According to one embodiment of the present invention, a gate electrode provided on a semiconductor substrate with a gate insulating film interposed therebetween, a metal layer provided on the gate electrode, and the substrate are isolated so as to sandwich the gate electrode. A gate-insulated field effect transistor having a diffusion layer serving as a source or a drain, a first barrier film provided on the diffusion layer and on a sidewall of the transistor, and provided on the first barrier film A first barrier layer, a second barrier film continuously provided on the metal layer and the first insulating layer, an opening having a first width in the second barrier film, and a first direction. A second insulating layer provided on the second barrier film, and a bottom portion penetrating the second insulating layer in the second barrier film, the bottom portion extending in the first direction. It is larger than the first width in the second direction that intersects An upper portion of the contact hole having a width of 2 and provided on the diffusion layer from the upper portion of the contact hole through the groove and through the first insulating layer and the first barrier film, and the upper surface in the second direction is It is possible to provide a semiconductor device including a contact hole lower portion having a width and a contact in which a conductor is continuously embedded in the upper portion of the contact hole and in the lower portion of the contact hole.
According to one embodiment of the present invention, a gate electrode provided on a semiconductor substrate with a gate insulating film interposed therebetween, a metal layer provided on the gate electrode, and the substrate are isolated so as to sandwich the gate electrode. A gate-insulated field effect transistor having a diffusion layer serving as a source or a drain, a first barrier film provided on the diffusion layer and on a sidewall of the transistor, and provided on the first barrier film A first insulating layer, a second barrier film continuously provided on the metal layer and the first insulating layer, a second insulating layer provided on the second barrier film, A groove-like structure having a bottom portion in the second barrier film through the two insulating layers, and the diffusion layer through the first insulating layer and the first barrier film from the bottom of the groove-like structure And the groove structure Embedded structure of the same conductive material and the hole structures are continuous, the groove-like structure serves as an electrical wire, wherein the hole structure can provide a semiconductor device that functions as an electrical contact.
According to one aspect of the present invention, a plurality of memory cell transistors formed on a semiconductor substrate with a first insulating film interposed therebetween, and the memory cell transistors are continuous in the first direction while sharing their source and drain. Adjacent to each other in the first direction, a select transistor formed on both ends of the memory cell array arranged via the first insulating film, and a metal layer formed on the gate of the select transistor and the memory cell transistor A first barrier film provided on a diffusion layer located between two select transistors belonging to different memory cell columns and on opposite side surfaces of the two select transistors; and a first barrier film provided on the first barrier film. One insulating layer, a second barrier film continuously provided on the metal layer and the first insulating layer, and the two selection transistors, A groove extending in a second direction having a first width in the second barrier film and intersecting the first direction; a second insulating layer provided on the second barrier film; and a second width in the first direction. A contact hole top having a bottom in the second barrier film through the second insulating layer, and the first insulating layer and the first insulating layer through the groove from the top of the contact hole. A lower part of the contact hole provided on the diffusion layer through the barrier film, and a contact in which a conductor is continuously embedded in the upper part of the contact hole and in the lower part of the contact. The second width of the semiconductor device can be larger than the first width of the groove.
According to one aspect of the present invention, a gate insulating field effect transistor formed on a semiconductor substrate via a gate insulating film and having a metal layer on the gate, the diffusion layer serving as a source or drain of the transistor, and the above A first barrier film provided on a sidewall of the transistor; a first insulating layer provided on the first barrier film; and a second barrier film provided continuously on the metal layer and the first insulating layer. A barrier film; a second insulating layer provided on the second barrier film; an opening located on the diffusion layer; provided in the second barrier film; and passing through the opening and the second insulation. A layer, the first insulating layer, the first barrier film and the first hole structure located on the diffusion layer, and the second insulating layer, the second barrier film. Second hole connected on the gate It can provide a concrete, a semiconductor device including a first hole structure within and embedded in the second hole structures conductor.
According to one aspect of the present invention, a step of forming a diffusion layer in the substrate so as to sandwich the gate electrode formed on the main surface of the semiconductor substrate, and forming a diffusion layer on the sidewall and the diffusion layer of the gate electrode Forming a first barrier film; forming a first insulating layer on the first barrier film; forming a silicide layer on the gate electrode; and on the silicide layer and the first insulating layer A step of forming a second barrier film thereon, a step of forming an opening having a first width in the second barrier film on the diffusion layer, and a step of forming a second insulating layer on the second barrier film Forming a mask layer on the second insulating layer; forming a second width larger than the first width on the mask layer on the opening; and etching using the mask layer as a mask Through the second insulating layer Using the second barrier film as a stopper, an upper portion of a contact hole having a second width bottom is formed in the second barrier film, and etching proceeds from the position of the opening so that the first insulating layer and the first barrier film are formed. Forming a lower portion of the contact hole having a first width and a depth reaching the diffusion layer in the second barrier film; and embedding a conductive layer in the first and second contact holes to form a contact A method of manufacturing a semiconductor device including the forming step.
According to the present invention, it is possible to obtain a semiconductor device which is advantageous for miniaturization and can improve reliability and a method for manufacturing the same.
First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a plan view schematically showing the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional structure diagram seen from the direction of the arrow along the line 2-2 in FIG. FIG. 3 is an enlarged sectional view showing the contact 39 in the vicinity of the barrier film 25 in FIG. FIG. 4 is a cross-sectional structure diagram seen from the direction of the arrow along the line 3-3 in FIG. Hereinafter, in this embodiment, a NAND flash memory will be described as an example.
As shown in the figure, a memory cell array 11 and a peripheral circuit 12 are provided on the main surface of a semiconductor (silicon) substrate 21.
In the memory cell array 11, an element region AA is provided along the bit line direction, a word line WL and a select gate electrode SG are provided along the word line direction, and a bit line is formed on the element region AA along the bit line direction. BL (not shown in FIG. 1) is provided. A selection transistor ST is provided at the intersection between the bit line BL and the select gate electrode SG, and a memory cell transistor MT is provided at the intersection between the bit BL and the word line.
The peripheral circuit 12 includes an element region AA along the bit line direction, a gate line GL along the word line direction, and a bit line BL (in FIG. 1) on the element region AA along the bit line direction. (Not shown) is provided. A transistor TR is provided at the intersection of the element region AA and the gate line GL.
The selection transistor (insulated gate type field effect transistor) ST includes a gate insulating film 22 provided on the substrate 21, a select gate electrode SG provided on the gate insulating film 22, a silicide layer 31 provided on the select gate, A diffusion layer 38 is provided in the substrate 21 so as to sandwich the select gate electrode SG and serve as a source / drain. The insulating film 35 in the select gate electrode SG is cut near the center of the gate SG, and the upper and lower conductive layers are continuous.
The memory cell transistor MT includes a floating electrode FG provided on the gate insulating film 22, an inter-gate insulating film 33 provided on the floating electrode, a control electrode CG provided on the inter-gate insulating film 33, and the control electrode CG. And a diffusion layer 38 which is provided in the substrate 21 and functions as a source / drain so as to be sandwiched between the silicide layer 32 and the floating electrode FG. The word line WL has a laminated structure of the control electrode CG and the silicide layer 32, and the floating electrode FG is separated for each memory cell transistor MT.
A barrier film (first barrier film) 23 is provided on the sidewalls of the selection transistor ST and the memory cell transistor MT and on the diffusion layer 38. An insulating layer 24 (first insulating layer) is provided on the barrier film 23. A barrier film (second barrier film) 25 is provided on the silicide layers 31 and 32. An insulating layer 26 (second insulating layer) is provided on the barrier film 25, a bit line BL is provided on the insulating layer 26, and an insulating layer 27 is provided on the bit line BL.
Further, when the barrier films 23 and 25 are formed of, for example, a silicon nitride (SiN) film or the like, the thickness of the barrier film 25 is larger than that of the barrier film 23. It is desirable to be about twice as thick.
Further, in the barrier film 23, the silicide layers 31, 32, and 41S react with the diffusion of substances such as ions and moisture in the insulating layers 24 and 26 and the substances such as cobalt silicon (CoSi) in the insulating layers 24 and 26. Act as a barrier to things. The barrier film 23 functions as a barrier against the diffusion of the material in the insulating layer 24 and the reaction between the material of the insulating layer 24 and the silicide layers 31, 32, 41S. In addition, the barrier films 23 and 25 also function as stoppers when the contacts 39 are formed.
As described above, the memory cell transistors MT share the diffusion layer 38 that is adjacent in the bit line direction and serves as a source / drain. Further, the memory cell transistor MT is provided such that a current path is connected in series between the selection transistors ST, and is selected by the selection transistor ST. Here, illustration of the other selection transistor to be connected to the current path of the memory cell transistor MT is omitted. Furthermore, the number of memory cell transistors MT connected in series between the select transistors ST may be a plurality of, for example, 8, 16, 32, and the number is not limited.
A contact 39 is provided on the diffusion layer (drain) 38 of the selection transistor ST through the insulating layers 26 and 24, the barrier films 25 and 23, and the gate insulating film 22, and electrically connects the diffusion layer 38 and the bit line BL. Connected.
As shown in FIG. 3, the contact 39 in the direction along the bit line BL passes through the insulating layer (second insulating layer) 26, and the bottom 40 is located in the barrier film (second barrier film) 25. 40 has a width W1 (W1 <W2) in which the upper surface thereof is smaller than the width W2 in the contact hole upper portion 39-1 having a width W2 and from the position of the bottom 40 of the contact hole upper portion 39-1. (Second barrier film) 25, insulating layer (first insulating layer) 24, barrier film (first barrier film) 23, and contact hole lower portion 39-2 provided on diffusion layer 38 through gate insulating film 22 It is formed by embedding a conductive layer of metal or the like inside. In other words, the cross-sectional shape of the contact 39 in the barrier film 25 is a step-like cross-sectional shape having a wide upper portion and a narrow lower width.
The width W2 of the contact 39 is preferably, for example, about twice or more in the bit line direction as compared with the width W1, but may be wider.
As shown in the figure, since the widths W1 and W2 are actually formed narrower in the lower part, the contact widths W1 and W2 slightly vary depending on the depth position, but satisfy the relationship of W1 <W2. It only has to be. Furthermore, a portion of the opening width W2 is provided in the opening of the second barrier film 25 by etching back a part of the opening (opening width W1) of the second barrier film 25.
Further, when the selection ratio between the insulating layer 26 and the barrier film 25 is weak, an opening having a continuous width is not provided in the barrier film 25 without providing an opening having a step difference between the width W1 and the width W2 as shown in the figure. It is also conceivable that a part is provided.
Further, in the etching process for forming the contact hole lower part 39-2, it may be considered that the width of the contact hole lower part 39-2 does not necessarily coincide with the width W1 due to spreading in the bit line direction.
However, in the cross section shown in FIG. 4, since the contact 39 is not provided, the width in the barrier film 25 is always W1.
The transistor TR is provided in the substrate 21 so as to function as a source / drain while being isolated so as to sandwich the gate insulating film 22 provided on the substrate 21, the gate line GL provided on the gate insulating film 22, and the gate line GL. A diffusion layer 45 is provided. The insulating film 42 in the gate line GL is cut near the center of the gate CG, and the upper and lower conductive layers 41 are continuous. A silicide layer 41S is provided on the conductive layer 41. The conductive layer 41 only needs to be electrically connected to the upper and lower conductive layers. For example, an example in which the upper and lower conductive layers are connected by being cut off at the periphery of the insulating film 42 is also conceivable.
A barrier film 23 is provided on the sidewall of the transistor TR and the diffusion layer 45. An insulating layer 24 is provided on the barrier film 23. A barrier film 25 is provided on the silicide layer 41S. An insulating layer 26 is provided on the barrier film 25, a wiring layer 44 is provided on the insulating layer 26, and an insulating layer 27 is provided on the wiring layer 44.
A contact 43 is provided on the diffusion layer 45 of the transistor TR through the insulating layers 26 and 24, and the diffusion layer 45 and the wiring layer 44 are electrically connected.
As described above, in the semiconductor device according to this embodiment, the barrier film 25 is provided so as to cover the silicide layers 31, 32, and 41S. Therefore, it acts as a barrier against the diffusion of substances such as ions and moisture in the insulating layers 24 and 26 and the reaction between the silicide layers 31, 32 and 41S with substances such as cobalt silicon (CoSi) in the insulating layers 24 and 26, Reliability can be improved.
A barrier film 23 is provided on the diffusion layer 38 and the side wall of the selection transistor ST and the memory cell transistor MT. Therefore, it acts as a barrier against the diffusion of the material in the insulating layer 24 and the reaction between the material of the insulating layer 24 and the silicide layers 31, 32, 41S, and the reliability can be improved.
Further, no silicide layer is provided on the diffusion layer 38. Therefore, so-called junction leakage due to the silicide layer does not occur, and the silicide layer does not affect the insulation of the gate insulating film 23 and the insulation is not lowered, so that the reliability can be improved. In addition to the above effect, the cell area in the bit line direction can be reduced by the amount not provided with the silicide layer, which is advantageous for miniaturization.
Further, in the direction along the bit line BL, the bottom 40 is located in the barrier film 25 through the insulating layer 26, and the bottom 40 has a width W2, and the contact hole upper portion 39-1. -1 through the barrier film 25, the insulating layer 24, the barrier film 23, and the gate insulating film 22 with the upper surface having a width W1 (W1 <W2) smaller than the width W2 from the bottom 40 position. A contact 39 embedded with a metal or the like is provided in a contact hole lower portion 39-2 provided on the layer 38.
Therefore, the width W1 of the contact 39 is small, and the cell area in the bit line direction can be reduced while ensuring electrical connection with the diffusion layer 38, which is advantageous for miniaturization. On the other hand, since the width W2 of the contact 39 is large, the resistance value of the contact 39 can be reduced.
The width W2 is preferably, for example, about twice or more in the bit line direction compared to the width W1, but may be wider. When the width W2 is more than twice the width W1, the resistance value of the contact 39 can be reduced.
According to such a configuration of the contact 39, the diameter of the contact hole lower portion 39-2 can be reduced even when the aspect ratio between the insulating layer 26 and the insulating layer 24 is large. Therefore, it is advantageous for forming contacts between miniaturized cells.
Next, a method for manufacturing the semiconductor device according to this embodiment will be described with reference to FIGS. 5 to 14 by taking the NAND flash memory shown in FIG. 1 or FIG. 2 as an example.
First, as shown in FIG. 5, the gate insulating film 22, the select gate electrode SG, the insulating layer 35, the floating electrode FG, and the inter-gate insulation are formed on the main surface of the substrate 21 to be the memory cell array 11 using a known process. The film 33, the control electrode CG, and the diffusion layer 38 are formed.
At the same time, the gate insulating film 22, the conductive layer 41, the insulating layer 42, and the diffusion layer 45 are formed on the main surface of the substrate 21 to be the peripheral circuit 12 using a known process.
Subsequently, as shown in FIG. 6, silicon nitride (SiN) is formed on the gate insulating film 22, the select gate electrode SG, the control electrode CG, and the conductive layer 41 by, for example, a CVD (Chemical Vapor Deposition) method. A barrier film (first barrier film) 23 is formed by depositing a film or the like.
Subsequently, as shown in FIG. 7, an insulating layer 24 is deposited on the barrier film 23 by using, for example, a CVD method. Thereafter, the insulating layer 24 and the barrier film 23 are planarized to the surface of the select gate electrode SG, the control electrode CG, and the conductive layer 41 by using, for example, a CMP (Chemical Mechanical Polishing) method, and the select gate electrode SG, The barrier film 23 is left on the control electrode CG and the side walls of the conductive layer 41 and the diffusion layers 38 and 45.
Subsequently, as shown in FIG. 8, silicide layers 31, 32, and 41S are formed by reacting the select gate electrode SG, the control electrode CG, and the conductive layer 41 with the refractory metal layer by a salicide process. Thereafter, a silicon nitride film or the like is deposited and formed on the silicide layers 31, 32, 41S, the insulating layer 24, and the barrier film 23 by, for example, a CVD method to form a barrier film (second barrier film) 25.
In the salicide process, the material that reacts with the select gate electrode SG, the control electrode CG, and the conductive layer 41 is not limited to the refractory metal layer. That is, for example, the silicide layers 31, 32, and 41S can also be formed by reacting a metal layer that can form a silicide layer that is not classified as a refractory metal such as cobalt (Co) or nickel (Ni). It is.
Here, when the barrier films 23 and 25 are formed of the same material, in the step of forming the barrier film 25, for example, by selecting reaction conditions and the like, the thickness of the barrier film 25 is set to be equal to that of the barrier film 23. It is desirable to form the film so as to be thicker than the film thickness (for example, about twice or more).
Subsequently, as shown in FIGS. 9 and 10, a photoresist is applied on the barrier film 25. Further, the photoresist is exposed and developed, and a pattern as shown in FIG. 9 is transferred to form a photoresist 50. Here, the photoresist 50 has a groove (opening) 51 having a width W1 along the word line direction on the diffusion layer 38 in the memory cell array 11, and the opening on the diffusion layer 45 in the peripheral circuit 12. 52.
The photoresist can be a hard mask.
Thereafter, using the photoresist 50 to which the pattern is transferred as a mask, the barrier film 25 is removed by performing, for example, anisotropic etching such as RIE (Reactive Ion Etching) to at least the surface of the insulating layer 24. Thereafter, the photoresist 50 is removed.
Subsequently, as shown in FIGS. 11 and 12, an insulating layer 26 is formed on the insulating layer 24 and the barrier film 25 by using, for example, a CVD method. Thereafter, a photoresist is applied on the insulating layer 26. Further, the photoresist is exposed and developed to transfer a pattern as shown in FIG.
Here, the photoresist 60 has an opening 61 having a width W2 larger than the width W1 along the word line direction on the diffusion layer 38 in the memory cell array 11. The peripheral circuit 12 has an opening 63 on the diffusion layer 45. Further, the opening 63 is formed to have a smaller diameter than the opening 52 formed in the photoresist 50.
Subsequently, as shown in FIG. 13, using the photoresist 60 to which the pattern is transferred as a mask, up to the surface of the barrier films 23 and 26, for example, a different ratio with respect to the insulating layer 23 by the RIE method or the like. Isotropic etching is performed to form a contact hole 64 that penetrates the insulating layers 26 and 24.
Next, as shown in FIG. 14, using the photoresist 60 as a mask, for example, anisotropic etching such as RIE is performed until the substrate 21 on the diffusion layers 45 and 38 is exposed, and the gate insulating film 22 and A contact hole penetrating the barrier film 23 and partially etched back of the barrier film 25 is formed. That is, anisotropic etching is performed using the photoresist 60 as a mask, and an upper contact hole 39-1 having a bottom with a width W2 is formed in the barrier film 25 using the barrier film 25 as a stopper, and the groove 51 (opening) is formed. Etching is further advanced from the position to form a contact hole lower part 39-2 having a width W1 and a depth reaching the diffusion layer 38 in the barrier film 25 through the barrier film 23 and the gate insulating film 22.
Thereafter, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), polysilicon (Poly-Si), or the like is buried in the contact hole 65 to form the contact 39.
As described above, a part of the barrier film 25 is etched back during the anisotropic etching process for forming the contact hole upper part 39-1, so that the contact hole upper part 39-1 having the opening width W2 is formed. Forming.
Thereafter, the bit line BL and the insulating layer 27 are formed by a known process, and the semiconductor device shown in FIG. 1 or FIG. 2 can be manufactured.
As described above, the method for manufacturing a semiconductor device according to this embodiment uses the photoresist (mask layer) 60 having an opening having a width W2 wider than the width W1 as a mask, and the barrier film 25 having an opening having a width W1. Is used as a stopper layer to anisotropically etch the insulating layers 26 and 24 to form contact hole upper portions 39-1 and 39-2 (FIGS. 13 and 14).
Therefore, by increasing the width W2 of the opening, it is possible to increase the etching rate of the insulating layer 26 and increase the selection ratio with the barrier film 25. Therefore, the barrier film 25 can be used as a stopper, and the barrier A fine contact having the same width as the width W 1 of the opening of the film 25 can be formed in the insulating layer 24.
Further, in the above process, a part of the barrier film 25 formed to be larger than the film thickness of the barrier film 23 can be etched back by selecting time or the like, so that the barrier film 25 is overetched. Therefore, the contact 39 and the select gate electrode SG can be prevented from being short-circuited, and the reliability can be improved.
In this embodiment, an example in which the barrier films 23 and 25 are formed of the same material is shown. However, even when the barrier films 23 and 25 are formed of different materials, the same effect can be obtained by selecting the time, reaction conditions, and the like in the above process.
The memory cell array 11 has a groove 51 having a width W1 along the word line direction on the diffusion layer 38, and the peripheral circuit 12 is insulated using the photoresist 50 having an opening 52 on the diffusion layer 45 as a mask. For example, anisotropic etching such as RIE is performed up to the surface of the layer 24 to remove the barrier film 25 (FIGS. 9 and 10).
In the above process, the barrier film 25 of the memory cell array 11 and the peripheral circuit 12 can be removed simultaneously according to the groove 51 and the opening 52 of the photoresist 50. Therefore, it is advantageous in that the manufacturing cost can be reduced.
Further, a photoresist having an opening 61 having a width W2 larger than the width W1 along the word line direction on the diffusion layer 38 of the memory cell array 11, and having an opening 63 on the diffusion layer 45 of the peripheral circuit 12. Using the mask 60 as a mask, anisotropic etching is performed to form a contact hole 64 penetrating the insulating layers 26 and 24 (FIGS. 11 to 13).
In the above process, contact holes 64 can be simultaneously formed in the insulating layers 26 and 24 of the memory cell array 11 and the peripheral circuit 12. Therefore, it is advantageous in that the manufacturing cost can be reduced.
In this embodiment, an example is shown in which the contact holes 64 and 65 of the memory cell array 11 and the peripheral circuit 12 are formed simultaneously. However, in the memory cell array 11 and the peripheral circuit 12, the contact holes 64 and 65 can be formed independently.
A method for manufacturing a semiconductor device according to the first modification of the present invention will be described with reference to FIGS. This modification relates to the photoresist 60 shown in the first embodiment. 15 and 16 are plan views schematically showing a photoresist 60 used in the method for manufacturing a semiconductor device according to the first modification. Hereinafter, the description of the same part as the first embodiment is omitted.
The photoresist 60 shown in FIG. 15 has a groove 61 having a width W2 larger than the width W1 along the word line direction. Therefore, according to this photoresist 60, a so-called common source line is formed in which the potentials of the diffusion layers 38 of the selection transistors ST in the word line direction are made the same.
Further, the photomask 60 shown in FIG. 16 has a circular opening 61 having a diameter W2 larger than the width W1. Therefore, according to this photoresist 60, as in the first embodiment, a drain contact separated for each diffusion layer 38 of the select transistor ST in the bit line direction is formed.
The cross-sectional structure is the same as in FIG. 2 regardless of the photoresist in FIGS.
As described above, according to the manufacturing method of the semiconductor device according to the first modification, the same effect as in the first embodiment can be obtained. Furthermore, a common source line can be formed by performing anisotropic etching using the photoresist 60 having a groove 61 having a width W2 larger than the width W1 along the word line direction as a mask (FIG. 15).
Therefore, the common source line can be formed without increasing the number of masks, which is advantageous in that the manufacturing cost can be reduced.
Further, drain contact can be formed by performing anisotropic etching using a photoresist 60 having a circular opening 61 having a diameter W2 larger than the width W1 as a mask (FIG. 16). Since the circular opening 61 in the above process can have the same shape as the opening 63 of the peripheral circuit, it is advantageous in that the manufacturing cost can be reduced.
A semiconductor device and a manufacturing method thereof according to Modification 2 of the present invention will be described with reference to FIGS. FIG. 17 is a cross-sectional structure diagram schematically illustrating a semiconductor device according to Modification 2. 18 and 19 are cross-sectional structure diagrams showing one manufacturing process of the semiconductor device according to the second modification. This modification relates to the gate line GL of the peripheral circuit 12 in the first embodiment. Hereinafter, the description of the same part as the first embodiment is omitted.
According to the semiconductor device according to the second modification, the same effect as in the first embodiment can be obtained. Further, as shown in the drawing, no silicide layer is provided on the gate line GL of the transistor TR of the peripheral circuit 12. Therefore, it is advantageous in that the selectivity of the gate structure in the memory cell array 11 and the peripheral circuit 12 can be improved.
Next, a method for manufacturing a semiconductor device according to Modification 2 will be described. First, the gate structures of the memory cell array 11 and the peripheral circuit 12 are formed by the same process as in the first embodiment.
Subsequently, as shown in FIG. 18, the barrier film 68 such as a silicon nitride (SiN) film is formed only on the insulating layer 24, the barrier film 68, and the conductive layer 41 of the peripheral circuit 12 by using, for example, the CVD method. Form.
Subsequently, silicide layers 31 and 32 are formed by reacting the select gate electrode SG and the control electrode CG with the refractory metal layer by a salicide process. In this step, since the barrier film 68 is formed on the conductive layer 41 of the peripheral circuit 12, the conductive layer 41 and the refractory metal do not react.
Thereafter, the semiconductor device shown in FIG. 17 can be manufactured by the same process.
As described above, according to the manufacturing method of the semiconductor device according to the second modification, the same effect as in the first embodiment can be obtained. Further, in a state where the barrier film 68 is formed on the conductive layer 41 of the peripheral circuit 12, the silicide layers 31 and 32 are formed only in the memory cell array 11 by the salicide process. Therefore, the conductive layer 41 does not react with the refractory metal, and the silicide layer of the peripheral circuit 12 cannot be selectively formed, which is advantageous in that the selectivity can be improved.
[Second Embodiment (Dual Damascene Wiring Structure)]
A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 20 is a cross-sectional structure diagram schematically illustrating the semiconductor device according to the second embodiment. The second embodiment is an example in which the contact 39 shown in the first embodiment has a so-called dual damascene wiring structure. Hereinafter, the description of the same part as the first embodiment is omitted.
As shown in the figure, a contact 39 penetrating the barrier films 25 and 23, the insulating layer 24, and the gate insulating film 22 and provided on the diffusion layer 38, and provided on the barrier film 25 and electrically connected to the contact 39. A dual damascene wiring layer 80 including a wiring layer 77 is provided. The wiring layer 77 serves as a wiring that electrically connects the contacts 39 in the bit line direction, applies a predetermined potential, and conducts a predetermined current.
As described above, according to the semiconductor device of the second embodiment, the same effects as those of the first embodiment can be obtained. Further, a dual damascene wiring layer including a contact 39 penetrating the barrier films 25 and 23, the insulating layer 24 and the gate insulating film 22 and provided on the diffusion layer 38, and a wiring layer 77 provided on the barrier film 25. 80 is provided. Therefore, it is effective in that the memory cell array 11 can be multilayered and miniaturized.
Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS.
First, as shown in FIG. 22, the insulating layer 26 is formed in the memory cell array 11 and the peripheral circuit 12 by the same process as in the first embodiment.
Subsequently, a photoresist is applied on the insulating layer 26, and the photoresist is exposed and developed to form a photoresist 60 to which a pattern as shown in FIG. 21 is transferred. Here, as shown in the figure, the photoresist 60 has a groove 61 formed on the diffusion layer 38 along the bit line direction.
Subsequently, as shown in FIG. 23, anisotropic etching such as RIE is performed to the surface of the substrate 21 using the photoresist 60 as a mask and the barrier film 25 as a stop layer, so that the groove 82 and the contact hole 65 are formed. Form.
Thereafter, the semiconductor device shown in FIG. 20 can be manufactured through the same steps as those in the first embodiment.
According to the manufacturing method as described above, the same effects as those of the first embodiment can be obtained. Further, anisotropic etching is performed using the photoresist 60 having the groove 61 on the diffusion layer 38 along the bit line direction as a mask to form the groove 82 and the contact hole 65 (FIGS. 21 to 23). Since the groove 61 formed in the photoresist 60 is a so-called line and space along the bit line direction, the manufacturing cost can be reduced, which is advantageous for miniaturization.
Next, a semiconductor device and a method for manufacturing the same according to a third embodiment of the present invention will be described with reference to FIGS. Hereinafter, the description of the same part as the first embodiment is omitted.
FIG. 24 is a plan view schematically showing a semiconductor device according to the third embodiment. FIG. 25 is a sectional view taken along line 25-25 in FIG. FIG. 26 is a sectional structural view taken along line 26-26 in FIG.
As shown in the drawing, on the diffusion layer 45, an opening 91 provided through the barrier film 25, and the insulating layers 26 and 24, the barrier film 23, and the gate insulating film 22 are continuously passed through the opening 91. Then, a contact 43 (first hole structure) provided on the diffusion layer 45 is provided.
Further, a contact 90 (first contact) located on the element isolation region STI, continuously passing through the insulating layer 26 and the barrier film 25 and provided on the silicide layer 41S to electrically connect the gate electrode and the wiring layer 44. A two-hole structure) is provided.
According to the above configuration, the same effect as in the first embodiment is obtained.
Next, a method for manufacturing the semiconductor device according to this embodiment will be described using the semiconductor device shown in FIGS. 25 and 26 as an example.
First, as shown in FIGS. 27 and 28, the opening 91 is formed in the barrier film 25 located on the diffusion layer 45 by the same process as described above, and the insulating layer 26 is formed on the barrier film 25 and the insulating layer 24. Form.
Subsequently, a photoresist 93 is applied on the insulating layer 25, and the photoresist is exposed and developed to form openings in the photoresist located on the diffusion layer 45 and the gate electrode 41, respectively.
Further, using the photoresist 93 as a mask, for example, anisotropic etching is performed by the RIE method or the like, using the barrier film 23 as a stopper, the contact hole 95-1 penetrating the insulating layers 26 and 23, and the barrier film 25 as a stopper. A contact hole 97-1 that penetrates the insulating layer 26 is formed simultaneously.
Subsequently, as shown in FIGS. 29 and 30, anisotropic etching is further performed using the photoresist 93 as a mask to penetrate the barrier film 23 and the gate insulating film 22 to form a contact hole 95− located on the diffusion layer 45. 2 and a contact hole 97-2 penetrating the barrier film 25 and located on the silicide layer 41S.
In the following, the semiconductor device shown in FIGS. 25 and 26 can be manufactured using known processes.
According to the above manufacturing method, the contact 43 on the diffusion layer 45 located on the element region AA and the contact 90 on the gate electrode (on GC) located on the STI can be simultaneously formed.
Therefore, it is advantageous in that the manufacturing process and manufacturing cost can be reduced.
Further, the barrier film 25 on the element region AA forms a wide opening 91 during the anisotropic etching (contact etching) step, but the barrier film 25 on the STI is not opened. That is, the barrier film 25 on the STI that is not opened is used as a stopper for the subsequent anisotropic etching process. Therefore, when the contact etching process is performed, the contact hole 95-1 on the STI stops on the barrier film 25, and the contact hole 97-1 on the element region AA stops on the barrier film 23 (FIGS. 27 and 28). . Opening is performed simultaneously by subsequent barrier film etching, and contact holes 95-2 and 97-2 are formed simultaneously (FIGS. 29 and 30).
As described above, the contact holes 95-2 and 97-2 of the STI and the STI can be formed by using the same etching process, which is advantageous in that the manufacturing process can be reduced.
In addition, since the thin barrier films 23 and 25 are simultaneously etched and opened in the second etching step, it is advantageous in that a problem such as a short circuit due to overetching can be prevented and reliability can be improved.
In the cross section shown in this embodiment, the silicide layer (metal layer) 41S may or may not be present.
Furthermore, in this embodiment, the peripheral circuit 12 has been described as an example, but the present invention is not limited to the peripheral circuit and can be applied to all contact formations.
In the first to third embodiments, the first modification, and the second modification, the illustrated peripheral circuit 12 is an example. For example, various peripheral circuits are conceivable, for example, the diffusion layers 45 of adjacent transistors TR are not connected but are provided independently.
As mentioned above, although this invention was demonstrated using the said 1st thru | or 3rd embodiment, the modification 1, and the modification 2, this invention is not limited to the said each embodiment and each modification, Various modifications can be made in the implementation stage without departing from the scope of the invention. Each of the above embodiments includes various inventions, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in each embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. In a case where at least one of the obtained effects can be obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.
1 is a plan view schematically showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional structure diagram taken along line 2-2 in FIG. FIG. 3 is an enlarged sectional view showing a contact in the vicinity of a barrier film 25 in FIG. 2. FIG. 4 is a sectional structural view taken along line 4-4 in FIG. FIG. 3 is a cross-sectional structure diagram schematically showing one manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 3 is a cross-sectional structure diagram schematically showing one manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 3 is a cross-sectional structure diagram schematically showing one manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 3 is a cross-sectional structure diagram schematically showing one manufacturing process of the semiconductor device according to the first embodiment of the invention. 1 is a plan view schematically showing a photoresist in one manufacturing process of a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a cross-sectional structure diagram schematically showing one manufacturing process of the semiconductor device according to the first embodiment of the invention. 1 is a plan view schematically showing a photoresist in one manufacturing process of a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a cross-sectional structure diagram schematically showing one manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 3 is a cross-sectional structure diagram schematically showing one manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 3 is a cross-sectional structure diagram schematically showing one manufacturing process of the semiconductor device according to the first embodiment of the invention. The top view which shows typically the photoresist of one manufacturing process of the semiconductor device which concerns on the modification 1 of this invention. The top view which shows typically the photoresist of one manufacturing process of the semiconductor device which concerns on the modification 1 of this invention. FIG. 9 is a cross-sectional structure diagram schematically showing a semiconductor device according to Modification 2 of the invention. FIG. 10 is a cross-sectional structure diagram schematically showing one manufacturing process of a semiconductor device according to Modification 2 of the invention. FIG. 10 is a cross-sectional structure diagram schematically showing one manufacturing process of a semiconductor device according to Modification 2 of the invention. FIG. 6 is a cross-sectional structure diagram schematically showing a semiconductor device according to a second embodiment of the present invention. The top view which shows typically the photoresist of the one manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional structure figure which shows typically one manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional structure figure which shows typically one manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 6 is a plan view schematically showing a semiconductor device according to a third embodiment of the present invention. FIG. 25 is a cross-sectional structure diagram taken along line 25-25 in FIG. 24. FIG. 25 is a sectional structural view taken along line 26-26 in FIG. 24. Sectional structure figure which shows typically one manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional structure figure which shows typically one manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional structure figure which shows typically one manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional structure figure which shows typically one manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention.
DESCRIPTION OF SYMBOLS 11 ... Memory cell array, 12 ... Peripheral circuit, 21 ... Semiconductor substrate, 22 ... Gate insulating film, 23, 25 ... Barrier film, 24, 26, 27 ... Insulating layer, BL ... Bit line (1st wiring), WL ... Word Line (second wiring), ST ... select transistor, MT ... memory cell transistor, TR ... transistor, SG ... select gate, 35, 42 ... insulating film, 31, 32, 41S ... silicide layer, 39, 43 ... contact, 39 -1 ... contact hole upper part, 39-2 ... contact hole lower part, 40 ... bottom of contact hole lower part, W1 ... width of contact hole lower part in barrier film 25, W2 ... width of bottom of contact hole upper part in barrier film 25 38, 45 ... diffusion layer, 55 ... groove.
Acts as a gate electrode provided on a semiconductor substrate via a gate insulating film, a metal layer provided on the gate electrode, and a source or drain provided in the substrate so as to sandwich the gate electrode A gate insulating field effect transistor having a diffusion layer;
A first barrier film provided on the diffusion layer and on the sidewall of the transistor;
A first insulating layer provided on the first barrier film;
A second barrier film continuously provided on the metal layer and the first insulating layer;
A groove opening in the second barrier film with a first width and extending in a first direction;
A second insulating layer provided on the second barrier film;
A contact hole top having a bottom in the second barrier film, penetrating through the second insulating layer, the bottom having a second width greater than the first width in a second direction intersecting the first direction. When,
A contact hole lower portion provided on the diffusion layer from the upper portion of the contact hole through the groove and passing through the first insulating layer and the first barrier film, and having an upper surface in the second direction having the one width;
A semiconductor device comprising a contact in which a conductor is continuously embedded in an upper part of the contact hole and in a lower part of the contact hole.
A groove-like structure having a bottom through the second insulating layer and in the second barrier film;
A hole structure extending from the bottom of the groove-like structure through the first insulating layer and the first barrier film to the diffusion layer,
The groove-like structure and the hole structure are embedded by the same continuous conductor, the groove-like structure functions as an electrical wiring, and the hole structure functions as an electrical contact. apparatus.
A plurality of memory cell transistors formed on a semiconductor substrate via a first insulating film;
A selection transistor formed through the first insulating film at both ends of a memory cell array in which the memory cell transistors share the source and drain of each other and are continuously arranged in the first direction;
A metal layer formed on gates of the selection transistor and the memory cell transistor;
A first barrier film provided on a diffusion layer located between two select transistors belonging to different memory cell columns adjacent in the first direction and on opposite sides of the two select transistors;
A groove located between the two select transistors and extending in a second direction intersecting the first direction with a first width in the second barrier film;
A groove-like structure having a second width in the first direction, and an upper part of a contact hole penetrating the second insulating layer and having a bottom in the second barrier film;
A lower part of the contact hole provided on the diffusion layer through the first insulating layer and the first barrier film through the groove from the upper part of the contact hole;
A contact embedded with a conductor continuously in the upper part of the contact hole and in the lower part of the contact;
The semiconductor device, wherein the second width of the upper part of the contact hole is larger than the first width of the groove.
A gate insulating field effect transistor formed on a semiconductor substrate via a gate insulating film and having a metal layer on the gate;
A first barrier film provided on a diffusion layer serving as a source or drain of the transistor and on a sidewall of the transistor;
An opening located on the diffusion layer and provided in the second barrier film;
A first hole structure passing through the opening and continuously passing through the second insulating layer, the first insulating layer, and the first barrier film and located on the diffusion layer;
A second hole structure continuously passing through the second insulating layer and the second barrier film and connected to the gate;
A semiconductor device comprising: a conductor embedded in the first hole structure and the second hole structure.
Forming a diffusion layer in the substrate so as to sandwich the gate electrode formed on the main surface of the semiconductor substrate; and
Forming a first barrier film on the sidewall and diffusion layer of the gate electrode;
Forming a first insulating layer on the first barrier film;
Forming a silicide layer on the gate electrode;
Forming a second barrier film on the silicide layer and the first insulating layer;
Forming an opening having a first width in the second barrier film on the diffusion layer;
Forming a second insulating layer on the second barrier film;
Forming a mask layer on the second insulating layer;
Forming a second width larger than the first width in the mask layer on the opening;
Etching is performed using the mask layer as a mask, an upper portion of a contact hole having a second width bottom is formed in the second barrier film using the second barrier film as a stopper, penetrating the second insulating layer, and the opening Etching from the position to form a lower part of the contact hole having a first width and reaching the diffusion layer in the second barrier film through the first insulating layer and the first barrier film; ,
And a step of forming a contact by embedding a conductive layer in the first and second contact holes.
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