Source: http://www.google.com/patents/US8141076?dq=7,403,220
Timestamp: 2015-03-30 18:29:46
Document Index: 744694952

Matched Legal Cases: ['application No. 06254919', 'Application No. 2008', 'Application No. 2008', 'application No. 2006', 'application No. 2006', 'application No. 200610142304', 'application No. 200610142305']

Patent US8141076 - Cell processor methods and apparatus - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsMethods and apparatus for cell processors are disclosed. A policy module is loaded from a main memory of a cell processor into the local memory of a selected synergistic processing unit (SPU) under control of an SPU policy module manager (SPMM) running on the SPU. The policy module loads a work queue...http://www.google.com/patents/US8141076?utm_source=gb-gplus-sharePatent US8141076 - Cell processor methods and apparatusAdvanced Patent SearchPublication numberUS8141076 B2Publication typeGrantApplication numberUS 11/238,077Publication dateMar 20, 2012Filing dateSep 27, 2005Priority dateSep 27, 2005Also published asEP1934740A1, EP2284703A2, EP2284703A3, US20070074212, WO2007038458A1Publication number11238077, 238077, US 8141076 B2, US 8141076B2, US-B2-8141076, US8141076 B2, US8141076B2InventorsJohn P. Bates, Payton R. White, Attila VassOriginal AssigneeSony Computer Entertainment Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (74), Non-Patent Citations (64), Referenced by (1), Classifications (10), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetCell processor methods and apparatus
US 8141076 B2Abstract
after completing the one or more tasks or upon a pre-emption, returning control of the secondary processing element to the policy module manager. Description
This application is related to commonly-assigned U.S. patent application Ser. No. 11/238,087 entitled �SPU TASK MANAGER FOR CELL PROCESSOR� to John P. Bates, Payton R. White, Richard Stenson, Howard Berkey, Attila Vass and Mark Cerny, which is filed the same day as the present application, the entire disclosures of which are incorporated herein by reference.
This application is also related to commonly-assigned U.S. patent application Ser. No. 11/238,095 entitled �CELL PROCESSOR TASK AND DATA MANAGEMENT� to Richard B. Stenson and John P. Bates, which is filed the same day as the present application, the entire disclosures of which are incorporated herein by reference.
This application is also related to commonly-assigned U.S. patent application Ser. No. 11/238,086 entitled �OPERATING CELL PROCESSORS OVER A NETWORK� to Tatsuya Iwamoto, which is filed the same day as the present application, the entire disclosures of which are incorporated herein by reference.
This application is also related to commonly-assigned U.S. patent application Ser. No. 11/238,085 entitled �METHOD AND SYSTEM FOR PERFORMING MEMORY COPY FUNCTION ON A CELL PROCESSOR� to Antoine Labour John P. Bates and Richard B. Stenson, which is filed the same day as the present application, the entire disclosures of which are incorporated herein by reference.
A major advance in electronic computation has been the development of systems that can perform multiple operations simultaneously. Such systems are said to perform parallel processing. Recently, cell processors have been developed to implement parallel processing on electronic devices ranging from handheld game devices to main frame computers. A typical Cell processor has a power processor unit (PPU) and up to 8 additional processors referred to as synergistic processing units (SPU). Each SPU is typically a single chip or part of a single chip containing a main processor and a co-processor. All of the SPUs and the PPU can access a main memory, e.g., through a memory flow controller (MFC). The SPUs can perform parallel processing of operations in conjunction with a program running on the main processor. The SPUs have small local memories (typically about 256 kilobytes) that must be managed by software�code and data must be manually transferred to/from the local SPU memories. For high performance, this code and data must be managed from SPU software (PPU software involvement must be minimized). There are many techniques for managing code and data from the SPU. Often, different techniques for managing code and data from the SPU need to operate simultaneously on a cell processor. There are many programming models for SPU-driven task management. Unfortunately, no single task system is right for all applications.
One prior art task management system used for cell processors is known as SPU Threads. A �thread� generally refers to a part of a program that can execute independently of other parts. Operating systems that support multithreading enable programmers to design programs whose threaded parts can execute concurrently. SPU Threads operates by regarding the SPUs in a cell as processors for threads. A context switch may swap out the contents of an SPU's local storage to the main memory and substitute 256 kilobytes of data and/or code into the local storage from the main memory where the substitute data and code are processed by the SPU. A context switch is the computing process of storing and restoring the state of a SPU or PPU (the context) such that multiple processes can share a single resource. Context switches are usually computationally intensive and much of the design of operating systems is to optimize the use of context switches.
Each SPU 104 includes a local memory 110. Code and data obtained from the main memory 106 can be loaded into the local memory 110 so that the SPU 104 can process tasks. As shown in the inset, a small software manager referred to herein as an SPU Policy Module Manager (SPMM) 112 resides in the local memory 110 of each SPU 104. Preferably, the SPMM 112 takes up only a small fraction of the total memory space available in each local memory 110 (e.g., less than about 1% of each SPU memory). The heart of SPMM 112 is referred to as an �SPMM Kernel�, which typically takes up about 2 KB resident on each SPU. For a 256K local storage, this represents about 0.8% SPU Local Store usage.
The SPMM Kernel provides Priority-based Work Queue scheduling. As used herein, the term �Work-Queue� refers to work defined at some location in a memory, such as, SPU work defined in main memory 106. This is often a queue of task definitions. A Policy Module associated with the work-queue determines how this work is interpreted and executed. As used herein, �Policy Module� refers to a small manager object on an SPU that defines a programming model and task execution scheme. A given Policy Module can manage code and/or data in the remaining SPU memory to execute SPU work. Policy Modules may be transferred from main RAM to SPU local storage to execute as needed by the current Work Queue. Other schemes of transferring a Policy Module from SPU to SPU are also recognized by the present inventors. The SPMM Kernel typically chooses a new Work Queue every time it runs.
Bytes (13)
Memory address of Work
Memory address of Policy Module Definition
Contention (Number of SPUs)
Maximum Allowed Contention
Minimum Contention
Bytes (12)
Policy Module Definition
Address of Policy Module SPU code image
Size of SPU code image
Code image offset of function that takes Work
FIG. 2B is a flow diagram illustrating an example of an algorithm 220 for choosing a Work Queue at step 202. The algorithm 220 is run by the SPMM 112. Initially, a parameter CHOICE is set to none at step 222. The parameter CHOICE represents the Work Queue that the SPMM 112 chooses to process. A pointer W is set to point to the first Work Queue definition in the WQ array 114 at step 224. At step 226 the SPMM checks whether the Work Queue definition represents a valid Work Queue. If it is not, the algorithm ends. As an example of an invalid WQ definition consider a case where the Work Queue array 114 has a size, N. If the index of the Work Queue definition is greater or equal to N, it is invalid. The algorithm iterates over all valid Work Queue definitions. If the Work Queue definition is valid, the SPMM 112 checks whether the first Work Queue is ready for processing at step 228. By way of example SPMM 112 may check whether the state attribute of the Work Queue definition is set to �READY�. If the first WQ is not ready, the value of W is set to point to the next WQ definition in the WQ array 114 at step 230 and the algorithm returns to step 226. If at step 232 the WQ is ready the SPMM 112 compares the WQ's contention (i.e., the number of SPUs currently working on it) to its max_contention (i.e., the most SPUs that could work on it). If the WQ's contention is greater than or equal to its max_contention, the value of W is set to point to the next WQ definition in the WQ array 114 at step 230 and the algorithm returns to step 226.
The SPMM 112 schedules multiple SPU work-queues 118 based on priorities and readiness. When higher priority work becomes available, the SPMM 112 can assign high priority tasks to available SPUs. Embodiments of the present invention are said to be semi-preemptive in that they can also implement cooperative preemption. Specifically, the Policy Module 124 can periodically check an SPU event channel to determine preemption. If and when preemption occurs, the Policy Module 124 can clean up and return control of the SPU 104 to the SPMM 112. When higher priority work becomes ready, preemption events are sent to lower priority SPUs�Policy Modules return to allow processing of higher priority work. Priority and contention of a given task or work queue may be stored as part of the work definition in the work queue array.
The Policy Modules 124 have one required function: execute(EA work_queue) { . . . }, where EA stands for �effective address��the main memory address of the WQ, from the chosen WQ definition. The function does not have to be called �execute�, but it must take a single 32-bit parameter. The size of the parameter (e.g., 32-bits) may vary based on the implementation, but the parameter is the address of the chosen Work Queue. The execute function represents the entry point for the Policy Module. This function should process the Work Queue passed to it via the work_queue parameter. The execute function may be configured to return state information which can be passed to main memory in the PPU, depending on the particular configuration of the Policy Module. However the execute function to process a work queue will typically not return a value.
Although the above discussion addresses atomic mutex locking to avoid race condition it may also be possible to avoid such conditions in a lock-free manner. In general, once the policy module determines that a given WQ contains no more tasks the policy module needs to prevent task states from being changed while the WQ state is set to empty. Alternatively, the processes of adding work or finishing work must be atomic. In the context of embodiments of the present invention, adding work includes setting the task state to �ready� in the policy module space and setting the SPMM WQ state to �ready.� Finishing work refers to a condition in which the last task is either taken or set to a not_ready state. Finishing work includes updating the task state to not ready and setting the SPMM WQ state to �not ready�.
Pre-emption may also occur under certain circumstances when W and CHOICE are of equal priority at step 240. For example, if at step 242 the policy module 124 finds that W and CHOICE are of equal priority and W's contention is greater than zero but less than a minimum contention value (min_contention) control of the SPU may be returned to the SPMM 112 at step 236. In such a case W is said to be �urgent�. The concept of minimum contention is useful in situations where work cascades from one SPU to one or more other SPUs. For example, in many physics applications, such as cloth simulation, the output of one SPU serves as input for another SPU running a different part of a process implementing a given work queue. When such a work queue is of equal priority to other work being processed, the algorithm 220 attempts to balance the contention by making SPUs available for such a process. If enough SPUs are available to process the work, the output may be loaded directly into the next SPU. Alternatively, the output may be temporarily stored in the main memory 106 until additional SPUs become available to process the output.
If at step 242 it is determined that W is not �urgent� the policy module can check at step 244 whether CHOICE represents urgent work, e.g., by determining whether CHOICE's contention is greater than zero but less than its min_contention. If CHOICE is urgent the policy module 124 continues to check other work, e.g., by returning the algorithm to step 230. If CHOICE is not urgent, the policy module 124 can balance contention by checking whether W's contention is less than CHOICE's contention at step 246 and, if so, setting CHOICE equal to W at step 236 and returning control to the SPMM 112. If W's contention is not less than CHOICE's contention the policy module 124 can check whether W and CHOICE are of equal contention at step 248. If not, the policy module 124 continues to check other work, e.g., by returning the algorithm to step 230. If W and CHOICE are of equal contention, the policy module 124 may check, at step 250 whether there is affinity, i.e., if W's policy is already loaded into SPU 104. If there is affinity, the policy module may set CHOICE equal to W at step 236 and return control of the SPU 104 to the SPMM 112.
The advantage of SPMM is that SPURS and other policies can be easily switched between as the nature of the work requires. For example, FIG. 3E depicts a memory map for a local storage 320 in which SPU Task Manager (STM) 322 is implemented as a policy under SPMM 312. The STM policy 332 manages a STM taskset having a task code 334 and one or more sets of task data 336, 338 The STM policy 332 reads one or more task definitions stored in the main memory into the local storage 320. Based on information contained in the task definitions the SPU loads code and/or data related to the task definitions from the main memory into the local memory associated with the selected SPU. The selected SPU then performs one or more tasks using the code and/or data. STM can be modified to run on SPMM with same program start address for STM tasks. When running under SPMM 312, the STM policy 332 does not need to manage multiple tasksets. STM is described in detail in commonly-assigned U.S. patent application Ser. No. 11/238,087 entitled �SPU TASK MANAGER FOR CELL PROCESSOR� to John P. Bates, Payton R. White, Richard Stenson, Howard Berkey, Attila Vass and Mark Cerny, which is filed the same day as the present application, the entire disclosures of which are incorporated herein by reference.
Another possible policy that may be loaded under SPMM is known as Cell Processor Task and Data Management (CTDM). FIG. 3F depicts a memory map for a local storage 320 in which a CTDM 342 is implemented as a policy under SPMM 312. The CTDM policy 342 allows the SPU to break up sets of data that are too large to fit in the local storage 320 into smaller segments 344 than can be processed by code 346 running on the SPU. The data can also be divided up into groups of a size suitable for processing on a subsequent processor such as a graphics card. CTDM is described in detail in commonly-assigned U.S. patent application Ser. No. 11/238,095 entitled �CELL PROCESSOR TASK AND DATA MANAGEMENT� to Richard B. Stenson and John P. Bates, which is filed the same day as the present application, the entire disclosures of which are incorporated herein by reference.
As used herein, the term I/O generally refers to any program, operation or device that transfers data to or from the system 400 and to or from a peripheral device. Every transfer is an output from one device and an input into another. Peripheral devices include input-only devices, such as keyboards and mouses, output-only devices, such as printers as well as devices such as a writable CD-ROM that can act as both an input and an output device. The term �peripheral device� includes external devices, such as a mouse, keyboard, printer, monitor, external Zip drive or scanner as well as internal devices, such as a CD-ROM drive, CD-R drive or internal modem or other peripheral such as a flash memory reader/writer, hard drive.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3496551 *Jul 13, 1967Feb 17, 1970IbmTask selection in a multi-processor computing systemUS3596257Sep 17, 1969Jul 27, 1971Burroughs CorpMethod and apparatus for allocating small memory spaces to a computer programUS5047923Aug 19, 1988Sep 10, 1991Siemens AktiengesellschaftModularly structured digital communication system for interconnecting terminal equipment and public networksUS5136712Jun 29, 1989Aug 4, 1992Digital Equipment CorporationTemporary object handling system and method in an object based computer operating systemUS5185694Jun 26, 1989Feb 9, 1993Motorola, Inc.Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks variesUS5452452Jun 4, 1993Sep 19, 1995Cray Research, Inc.System having integrated dispatcher for self scheduling processors to execute multiple types of processesUS5504901Feb 2, 1993Apr 2, 1996Digital Equipment CorporationPosition independent code location systemUS5528513 *Nov 4, 1993Jun 18, 1996Digital Equipment Corp.Scheduling and admission control policy for a continuous media serverUS5592671Jan 5, 1996Jan 7, 1997Kabushiki Kaisha ToshibaResource management system and methodUS5745778Jan 26, 1994Apr 28, 1998Data General CorporationApparatus and method for improved CPU affinity in a multiprocessor systemUS5794017Feb 6, 1995Aug 11, 1998International Business Machines CorporationMethod and system of updating graphics memory in a graphics display system through multiple address transferring of pixel dataUS5826081May 6, 1996Oct 20, 1998Sun Microsystems, Inc.Real time thread dispatcher for multiprocessor applicationsUS5832262Sep 14, 1995Nov 3, 1998Lockheed Martin CorporationRealtime hardware scheduler utilizing processor message passing and queue management cellsUS6003112Jun 30, 1997Dec 14, 1999Intel CorporationMemory controller and method for clearing or copying memory utilizing register files to store address informationUS6144986Mar 27, 1997Nov 7, 2000Cybersales, Inc.System for sorting in a multiprocessor environmentUS6279040Apr 27, 1999Aug 21, 2001Industrial Technology Research InstituteScalable architecture for media-on demand serversUS6289369Aug 25, 1998Sep 11, 2001International Business Machines CorporationAffinity, locality, and load balancing in scheduling user program-level threads for execution by a computer systemUS6295598Jun 30, 1998Sep 25, 2001Src Computers, Inc.Split directory-based cache coherency technique for a multi-processor computer systemUS6341324Oct 6, 1995Jan 22, 2002Lsi Logic CorporationException processing in superscalar microprocessorUS6370681Oct 28, 1997Apr 9, 2002Massachusetts Institute Of TechnologyComputer system and computer implemented process for representing software system descriptions and for generating executable computer programs and computer system configurations from software system descriptionsUS6378072Feb 3, 1998Apr 23, 2002Compaq Computer CorporationCryptographic systemUS6463457Aug 28, 2000Oct 8, 2002Parabon Computation, Inc.System and method for the establishment and the utilization of networked idle computational processing powerUS6526491Mar 22, 2001Feb 25, 2003Sony Corporation Entertainment Inc.Memory protection system and method for computer architecture for broadband networksUS6665699Sep 23, 1999Dec 16, 2003Bull Hn Information Systems Inc.Method and data processing system providing processor affinity dispatchingUS6665783Mar 6, 2003Dec 16, 2003Intel CorporationMemory-to-memory copy and compare/exchange instructions to support non-blocking synchronization schemesUS6728959Aug 8, 1995Apr 27, 2004Novell, Inc.Method and apparatus for strong affinity multiprocessor schedulingUS6785756 *May 10, 2001Aug 31, 2004Oracle International CorporationMethods and systems for multi-policy resource schedulingUS6792461 *Sep 19, 2000Sep 14, 2004International Business Machines CorporationSystem and method to manage data to a plurality of proxy servers through a router by application level protocol and an authorized listUS7024671Jan 31, 2001Apr 4, 2006Fujitsu LimitedScheduling apparatus performing job scheduling of a parallel computer systemUS7039736 *Jan 15, 2003May 2, 2006Hewlett-Packard Development Company, L.P.Systems and methods for accessing bus-mastered system resourcesUS7058750May 10, 2000Jun 6, 2006Intel CorporationScalable distributed memory and I/O multiprocessor systemUS7127477Nov 6, 2002Oct 24, 2006Everyware Solutions Inc.Method and system for access to automatically synchronized remote filesUS7236738Aug 1, 2003Jun 26, 2007Pathfire, Inc.Multicast control systems and methods for dynamic, adaptive time, bandwidth,frequency, and satellite allocationsUS7236998Sep 25, 2003Jun 26, 2007International Business Machines CorporationSystem and method for solving a large system of dense linear equationsUS7298377Jun 24, 2004Nov 20, 2007International Business Machines CorporationSystem and method for cache optimized data formattingUS7304646Aug 19, 2004Dec 4, 2007Sony Computer Entertainment Inc.Image data structure for direct memory accessUS7321958Oct 30, 2003Jan 22, 2008International Business Machines CorporationSystem and method for sharing memory by heterogeneous processorsUS7478390 *Sep 25, 2003Jan 13, 2009International Business Machines CorporationTask queue management of virtual devices using a plurality of processorsUS7516456Sep 25, 2003Apr 7, 2009International Business Machines CorporationAsymmetric heterogeneous multi-threaded operating systemUS7522168Sep 27, 2005Apr 21, 2009Sony Computer Entertainment Inc.Cell processor task and data managementUS7565651May 25, 2000Jul 21, 2009Oracle International CorporationParallel task scheduling system for computersUS7734827Oct 24, 2005Jun 8, 2010Sony Computer Entertainment, Inc.Operation of cell processorsUS7760206Feb 13, 2009Jul 20, 2010Sony Computer Entertainment Inc.Processor task and data managementUS20020138637Mar 22, 2001Sep 26, 2002Masakazu SuzuokiComputer architecture and software cells for broadband networksUS20020169907May 10, 2001Nov 14, 2002Candea George M.Methods and systems for multi-policy resource schedulingUS20030154284Aug 16, 2002Aug 14, 2003James BernardinDistributed data propagatorUS20030195920 *Jun 5, 2003Oct 16, 2003Brenner Larry BertApparatus and method for minimizing lock contention in a multiple processor system with multiple run queuesUS20040054883Sep 13, 2002Mar 18, 2004International Business Machines CorporationFirmware updatingUS20040208178May 14, 2004Oct 21, 2004Tuck Russell R.Method and apparatus for intelligent sorting and process determination of data packets destined to a central processing unit of a router or server on a data packet networkUS20050081203Sep 25, 2003Apr 14, 2005International Business Machines CorporationSystem and method for asymmetric heterogeneous multi-threaded operating systemUS20050091473Sep 25, 2003Apr 28, 2005International Business Machines CorporationSystem and method for managing a plurality of processors as devicesUS20050188372Feb 20, 2004Aug 25, 2005Sony Computer Entertainment Inc.Methods and apparatus for processor task migration in a multi-processor systemUS20050188373Feb 20, 2004Aug 25, 2005Sony Computer Entertainment Inc.Methods and apparatus for task management in a multi-processor systemUS20060190942Feb 3, 2006Aug 24, 2006Sony Computer Entertainment Inc.Processor task migration over a network in a multi-processor systemUS20070198628Jul 31, 2006Aug 23, 2007Sony Computer Entertainment Inc.Cell processor methods and apparatusUS20090147013Feb 13, 2009Jun 11, 2009Sony Computer Entertainment Inc.Processor task and data managementUS20090150634Feb 17, 2009Jun 11, 2009Sony Computer Entertainment Inc.Method and system for performing memory copy function on a cell processorUS20100251245Jun 8, 2010Sep 30, 2010Sony Computer Entertainment Inc.Processor task and data managementEP0806730A2May 1, 1997Nov 12, 1997Sun Microsystems, Inc.Real time dispatcherGB2394336A Title not availableJP2001005679A Title not availableJP2002007364A Title not availableJP2004246702A Title not availableJP2004320174A Title not availableJP2005235228A Title not availableJP2005235229A Title not availableJP2005513587A Title not availableJPH1055284A Title not availableJPH01258135A Title not availableWO1997006484A1Jul 25, 1996Feb 20, 1997Novell IncMethod and apparatus for strong affinity multiprocessor schedulingWO2002003208A2Jun 7, 2001Jan 10, 2002Intel CorpMethod and apparatus for secure execution using a secure memory partitionWO2002091180A2May 8, 2002Nov 14, 2002Oracle CorpMethods and systems for multi-policy resource schedulingWO2004015553A1Aug 13, 2002Feb 19, 2004Nokia CorpComputer architecture for executing a program in a secure of insecure modeWO2004084069A2Mar 19, 2004Sep 30, 2004Sony Comp Entertainment IncLoad balancing and taskdistribution system* Cited by examinerNon-Patent CitationsReference1Advisory Action dated Dec. 9, 2010 issued for U.S. Appl. No. 12/372,665.2Advisory Action dated Oct. 15, 2010 issued for U.S. Appl. No. 11/238,077.3Advisory Action dated Oct. 25, 2010 issued for U.S. Appl. No. 11/238,087.4Alan Heirich, "Optimal Automatic Multi-Pass Shader Partitioning by Dynamic Programming", Graphics Hardware (2005), pp. 91-98.5Alexandre E. Eichenberger et al., "Optimizing Compiler for a Cell Processor", Proceedings of 14th International Conference on Parallel Architectures and Compilation Techniques, 2005 (PACT'05), pp. 161-172.6B. Flachs et al., "A Streaming Processing Unit for a Cell Processor", 2005 IEEE International Solid-State Circuits Conference-Digest of Technical Papers, pp. 134-135.7B. Flachs et al., "A Streaming Processing Unit for a Cell Processor", 2005 IEEE International Solid-State Circuits Conference�Digest of Technical Papers, pp. 134-135.8D S Milojicic et al., "Process Migration" ACM Computing Surveys, ACM, New York, NY, US, vol. 32, No. 3, Sep. 2000, pp. 241-299, XP002254767 ISSN: 0360-0300.9European Search Report for European application No. 06254919 dated Dec. 21, 2007.10Final Office Action dated Aug. 16, 2010 issued for U.S. Appl. No. 11/238,087.11Final Office Action dated Aug. 5, 2008 issued for U.S. Appl. No. 11/238,085.12Final Office Action dated Aug. 5, 2010 issued for U.S. Appl. No. 11/238,077.13Final Office Action dated Dec. 17, 2010 issued for U.S. Appl. No. 12/372,665.14Final Office Action dated Feb. 5, 2010 issued for U.S. Appl. No. 11/238,086.15Final Office Action dated Jul. 29, 2008 for U.S. Appl. No. 11/238,095.16Final Office Action dated Nov. 8, 2010 issued for U.S. Appl. No. 11/238,086.17Final Office Action dated Sep. 29, 2010 issued for U.S. Appl. No. 12/372,665.18George M. Candea et al. "Vassal: Loadable Scheduler Support for Multi-Policy Scheduling" Proceedings of the Usenix Window NT Symposium, Aug. 1998, pp. 157-166.19Gschwind, "Chip Multiprocessing and the Cell Broadband Engine", ACM, 2006, pp. 1-8.20International application No. PCT/US2006/037334, "The International Search Report and The Written Opinion of the International Searching Authority".21International application No. PCT/US2006/037336, "The International Search Report and The Written Opinion of the International Searching Authority".22International application No. PCT/US2006/037338, "The International Search Report and The Written Opinion of the International Searching Authority".23International application No. PCT/US2006/037345, "The International Search Report" and "The Written Opinion of the International Searching Authority".24J. A. Kahle et al. "Introduction to the Cell Multiprocessor" IBM Journal of Research and Development, vol. 49, No. 4-5, , Jul. 2005, pp. 589-604.25Jaspal Subhlok et al., "Communication and Memory Requirements as the Basis for Mapping Task and Data Parallel Programs", Supercomputing'94, Proceedings Washington, DC, 1994 IEEE, pp. 330-339.26K Chanchio et al., "Data Collection and Restoration for Heterogeneous Process Migration" Software Practice & Experience, Wiley & Sons, Bognor Regis, GB, vol. 32, No. 9, Jul. 25, 2002, pp. 845-871, XP001115308 ISSN: 0038-0644.27Notice of Allowance and Fee Due(s) dated Mar. 8, 2010 issued for U.S. Appl. No. 12/371,424.28Notice of Allowance and Fee Due(s) dated Nov. 3, 2008 issued for U.S. Appl. No. 11/238,085.29Notice of Allowance and Fee(s) Due dated Jan. 26, 2010 issued for U.S. Appl. No. 11/257,761.30Notice of Allowance and Fee(s) Due dated Nov. 25, 2008 issued for U.S. Appl. No. 11/238,095.31Notification of Reason(s) for Refusal dated Nov. 30, 2010 issued for Japanese Patent Application No. 2008-533492.32Notification of Reason(s) for Refusal dated Nov. 30, 2010 issued for Japanese Patent Application No. 2008-533495.33Office Action (Final) dated Apr. 20, 2009 for U.S. Appl. No. 11/238,086.34Office Action (Final) dated May 7, 2009 for U.S. Appl. No. 11/257,761.35Office Action dated Apr. 14, 2010 issued for U.S. Appl. No. 11/238,087.36Office Action dated Aug. 11, 2009 issued for U.S. Appl. No. 11/238,08637Office Action dated Aug. 16, 2010 for Japanese patent application No. 2006-262023 and its English translation.38Office Action dated Aug. 16, 2010 for Japanese patent application No. 2006-262024 and its English translation.39Office Action dated Aug. 27, 2009 issued for U.S. Appl. No. 11/257,761.40Office Action dated Aug. 30, 2007 issued for U.S. Appl. No. 11/238,085.41Office Action dated Feb. 20, 2008 issued for U.S. Appl. No. 11/238,085.42Office Action dated Jan. 10, 2008 for U.S. Appl. No. 11/238,095.43Office Action dated Jun. 22, 2010 issued for U.S. Appl. No. 11/238,086.44Office Action dated Jun. 4, 2010 issued for U.S. Appl. No. 12/372,665.45Office Action dated May 13, 2008 issued for U.S. Appl. No. 11/238,086.46Office Action dated May 27, 2010 for Chinese patent application No. 200610142304.7 and its English translation.47Office Action dated May 6, 2010 for Chinese patent application No. 200610142305.1 and its English translation.48Office Action dated Nov. 15, 2010 issued for U.S. Appl. No. 12/796,601.49Office Action dated Nov. 24, 2008 issued for U.S. Appl. No. 11/257,761.50Office Action dated Nov. 4, 2008 issued for U.S. Appl. No. 11/238,086.51Office Action dated Oct. 16, 2009 issued for U.S. Appl. No. 12/371,424.52Office Action dated Sep. 29, 2010 issued for U.S. Appl. No. 11/461,390.53Pratit Santiprabhob et al. "Fuzzy Rule-Based Process Scheduling Method for Critical Distributed Computing Environment"-Proceedings 2003 IEEE, Mar. 8, 2003, vol. 5, pp. 52267-52276.54Pratit Santiprabhob et al. "Fuzzy Rule-Based Process Scheduling Method for Critical Distributed Computing Environment"�Proceedings 2003 IEEE, Mar. 8, 2003, vol. 5, pp. 52267-52276.55Scott Whitman, "Dynamic Load Balancing for Parallel Polygon Rendering", IEEE Computer Graphics and Applications, vol. 14, No. 4, Jul. 1994, pp. 41-48.56Sony Computer Entertainment Incorporated, "Cell Broadband Engine Architecture", Version 1.0, Aug. 8, 2005.57U.S. Appl. No. 11/238,085, entitled "Method and System for Performing Memory Copy Function on a Cell Processor", to Antoine Labour et al, filed Sep. 27, 2005.58U.S. Appl. No. 11/238,086, entitled "Operating Cell Processors Over a Network", to Tatsuya Iwamoto, filed Sep. 27, 2005.59U.S. Appl. No. 11/238,087, entitled "SPU Task Manager for Cell Processor", to John P. Bates et al, filed Sep. 27, 2005.60U.S. Appl. No. 11/238,095, entitled "Cell Processor Task and Data Management", to Richard B. Stenson et al, filed Sep. 27, 2005.61U.S. Appl. No. 11/257,761, entitled "Secure Operation of Cell Processors", to Tatsuya Iwamoto, filed Oct. 24, 2005.62U.S. Appl. No. 12/787,344, filed May 25, 2010.63U.S. Appl. No. 60/650,153, filed Feb. 4, 2005.64William et al., "The Potential of the Cell Processor for Scientific Computing", Conference on Computing Frontiers, ACM, 2006, pp. 9-20.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS20120320051 *Aug 29, 2012Dec 20, 2012Transgaming Technologies Inc.General purpose software parallel task engine* Cited by examinerClassifications U.S. Classification718/100, 718/102, 718/103, 718/101, 718/104International ClassificationG06F9/46Cooperative ClassificationG06F9/5066, G06F9/5083European ClassificationG06F9/50L, G06F9/50C2Legal EventsDateCodeEventDescriptionDec 27, 2011ASAssignmentOwner name: SONY COMPUTER ENTERTAINMENT INC., JAPANEffective date: 20100401Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SONY NETWORK ENTERTAINMENT PLATFORM INC.;REEL/FRAME:027557/0001Dec 26, 2011ASAssignmentEffective date: 20100401Free format text: CHANGE OF NAME;ASSIGNOR:SONY COMPUTER ENTERTAINMENT INC.;REEL/FRAME:027446/0001Owner name: SONY NETWORK ENTERTAINMENT PLATFORM INC., JAPANDec 29, 2005ASAssignmentOwner name: SONY COMPUTER ENTERTAINMENT AMERICA INC., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BATES, JOHN P.;WHITE, PAYTON R.;VASS, ATTILA;REEL/FRAME:017417/0043Effective date: 20051219RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services