Source: http://www.google.com/patents/US5087583?dq=5251294
Timestamp: 2016-09-25 21:14:40
Document Index: 302351895

Matched Legal Cases: ['art. 11', 'art. 12', 'art. 13', 'art. 14', 'art. 15', 'art. 16', 'art. 18', 'art. 19']

Patent US5087583 - Process for EEPROM cell structure and architecture with shared programming ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by...http://www.google.com/patents/US5087583?utm_source=gb-gplus-sharePatent US5087583 - Process for EEPROM cell structure and architecture with shared programming and erase terminalsAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS5087583 APublication typeGrantApplication numberUS 07/385,436Publication dateFeb 11, 1992Filing dateJul 27, 1989Priority dateFeb 5, 1988Fee statusLapsedPublication number07385436, 385436, US 5087583 A, US 5087583A, US-A-5087583, US5087583 A, US5087583AInventorsEmanuel HazaniOriginal AssigneeEmanuel HazaniExport CitationBiBTeX, EndNote, RefManPatent Citations (4), Non-Patent Citations (8), Referenced by (24), Classifications (27), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetProcess for EEPROM cell structure and architecture with shared programming and erase terminals
US 5087583 AAbstract
An EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polycrystalline silicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.
1. A method of manufacturing a non-volatile memory transistor containing a floating gate in an array comprising:depositing a nitride layer on, but separated from a surface of semiconductor substrate by first insulation; forming first resist layer on said nitride layer and patterning said first resist into spaced apart first resist segments separated by first resist windows; etching said nitride layer through said first resist windows to form first nitride windows directly underneath said resist windows and extending in the direction of the semiconductor surface down to surface of said insulation thereby forming nitride segments separated by said nitride windows; removing said first resist to reveal said nitride segments and nitride windows; depositing first polycrystalline silicon layer over the entire structure; anisotropically etching said polycrystalline silicon in a direction perpendicular to the surface of said substrate thereby exposing the top surface of said nitride segments and forming pairs of said polycrystalline silicon segments each segment laterally extending from said nitride segment into a separate said nitride windows and having first edge connected across top surface of said polycrystalline silicon to second edge and first edge of each of said polycrystalline silicon segments positioned near said nitride segments and said second edge of a selected said polycrystalline silicon segment spaced apart from said second edge of a first adjacent polycrystalline silicon segment across a portion of said nitride window to form first opening therewithin; implanting selected impurities layer through said first opening into first portions of said semiconductor substrate thereby to simultaneously form source and drain regions each extending from and self aligned to said second edge of respective polycrystalline silicon segments; chemically stripping said nitride segments to expose second portions of said semiconductor substrate extending from first edge of said selected polycrystalline silicon segment to first edge of a second adjacent polycrystalline silicon segment laterally extending from first source region by geometrical width of said polycrystalline silicon segment; forming a second resist pattern over said selected polycrystalline silicon segment but not on said first adjacent or said second adjacent polycrystalline silicon segment, and said second resist layer covers section of said drain region extending from said second edge of said selected polycrystalline silicon segment and said second resist layer also covers section of said second portion of said substrate extending from first edge of said selected polycrystalline silicon segment; and etching said first polycrystalline silicon layer and removing said second resist layer thereby forming a floating gate polycrystalline silicon from said selected polycrystalline silicon segment and a channel region including drain area extending laterally from said drain region to said first edge of said floating gate polycrystalline silicon and source area extending from first edge of said polycrystalline silicon floating gate to said source region. 2. The method of claim 1 wherein said second resist pattern is patterned to expose a laterally extending surface portion of said drain region extending from a point near the middle of said drain region to said second edge of said first adjacent polycrystalline silicon segment and said second resist pattern and exposes laterally extending surface portion of said second portion of said substrate, said surface portion extending from a point near the middle of said second portion of the substrate to said first edge of said second adjacent polycrystalline silicon segment.
3. The method of claim 1 further comprising: forming a second polycrystalline silicon layer to overlay said floating gate and said source area of said channel, but be electrically insulated therefrom to define a control gate of a memory transistor.
4. A method according to claim 1 further comprising:forming second polycrystalline silicon to insulatively overlap first portion of the floating gate, source area of the channel, source region and drain region and said second polycrystalline silicon defining first control gate of said memory transistor; and forming third polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally spaced apart from said channel and said third polycrystalline silicon defining second control gate of said memory transistor. 5. A method according to claim 1 further comprising:oxidizing said polycrystalline floating gate to form asperites, bumps and rough edges covered by a first silicon dioxide layer; etching said first silicon dioxide layer to expose said asperites, bumps and rough edges of said polycrystalline floating gate; growing a second silicon dioxide layer to cover the entire structure; forming second polycrystalline silicon to insulatively overlap first portion of the floating gate, source area of the channel, source region and drain region and said second polycrystalline silicon defining first control gate of said memory transistor; and forming third polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally space apart from said channel region and said third polycrystalline silicon defining second control gate of said memory transistor. 6. A method according to claim 1 further comprising:oxidizing said polycrystalline floating gate to form asperites, bumps and rough edges covered by a first silicon dioxide layer; etching said first silicon dioxide layer to expose said asperites, bumps and rough edges of each of said polycrystalline floating gate; growing a second silicon dioxide layer to cover the entire structure; forming second polycrystalline silicon to insulatively overlap first portion of the floating gate, source area of the channel, source region and drain region and said second polycrystalline silicon defining first control gate of said memory transistor; implanting selected impurities to destroy said asperites, bumps and rough edges from second portion of each of said polycrystalline floating gate laterally space apart from said channel region; and forming third polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally space apart from said channel region in each memory cell and said third polycrystalline silicon defining second control gate of said memory transistor. 7. A method according to claim 1 further comprising:oxidizing said polycrystalline floating gate to form asperites, bumps and rough edges covered by a first silicon dioxide layer; etching said first silicon dioxide layer to expose said asperites, bumps and rough edges of said polycrystalline floating gate; growing a second silicon dioxide layer to cover the entire structure; depositing second polycrystalline silicon over the entire structure; and etching second polycrystalline silicon to form two laterally spaced apart segments insulatively overlapping said floating gate to define two control gates, and first control gate overlapping first portion of the floating gate, source area of the channel, source region and drain region of said memory transistor, and second control gate overlapping source region, drain region and second portion of the floating gate laterally space apart from said channel region of said memory transistor. 8. A method of manufacturing an array of non-volatile memory transistors containing a floating gate comprising:depositing a nitride layer on, but separated from a surface of semiconductor substrate by first insulation; forming first resist layer on said nitride layer and patterning said first resist into spaced apart first resist segments separated by first resist windows; etching said nitride layer through said first resist windows to form first nitride windows directly underneath said resist windows and extending in the direction of the semiconductor surface down to surface of said insulation thereby forming nitride segments separated by said nitride windows; removing said first resist to reveal said nitride segments and nitride windows; depositing first polycrystalline silicon layer over the entire structure; anisotropically etching said polycrystalline silicon in a direction perpendicular to the surface of said substrate thereby exposing the top surface of said nitride segments and forming pairs of said polycrystalline silicon segments each segment laterally extending from said nitride segment into a separate said nitride windows and having first edge opposite second edge and first edge of each of said polycrystalline silicon segments positioned near an associated said nitride segment and said second edge of a selected said polycrystalline silicon segment spaced apart from said second edge of a first adjacent polycrystalline silicon segment across a portion of an associated said nitride window to form first opening therewithin and said polycrystalline silicon segments are arranged in lines parallel to a vertical axis and spaced apart along a horizontal axis perpendicular to said vertical axis; implanting selected impurities layer through said first opening into first portions of said semiconductor substrate thereby to simultaneously form source and drain regions each extending from and self aligned to said second edge of respective polycrystalline silicon segments and running vertically in lines parallel to said vertical axis; chemically stripping said nitride segments to expose second portions of said semiconductor substrate extending from first edge of said selected polycrystalline silicon segments to first edge of a second adjacent polycrystalline silicon segments laterally extending from first source regions by geometrical width of said polycrystalline silicon segments; forming a second resist layer pattern over said selected polycrystalline silicon segment but not over said first adjacent or said second adjacent polycrystalline silicon segments, and said second resist layer covers section of said drain regions extending from said second edge of said selected polycrystalline silicon segments and also covers section of said second portions of said substrate extending from first edge of said selected polycrystalline silicon segments to form an array of half-of-M even numbered rows along even numbered horizontal lines by N columns of holes in said second resist said holes separated along lines parallel to said vertical axis by half-of-M odd numbered second resist rows arranged along odd numbered horizontal lines covering portions of said pairs of polycrystalline silicon segments and said portions of source and drain regions and said second portions of said substrate along said odd numbered horizontal lines; etching said first polycrystalline silicon layer and removing said second resist layer thereby forming polycrystalline silicon first floating gates units from first adjacent and second adjacent polycrystalline silicon segments along said odd numbered horizontal lines and said first floating gate units spaced apart along a line parallel to said vertical axis and said etching step also forming channel regions along said even numbered horizontal lines each including drain area extending laterally from said drain regions to said first edge of said selected polycrystalline silicon segments underneath and said channel regions each also including source area extending from first edge of said selected polycrystalline silicon segments to an associated said source region and separated along lines parallel to said vertical axis by rows of said first floating gate units arranged along said odd numbered horizontal line; forming a third resist layer pattern over said polycrystalline silicon first floating gate units but not over portions of said selected polycrystalline silicon segments along said odd numbered horizontal line, and said third resist layer covers section of said drain regions extending from said second edge of said polycrystalline silicon first floating gate units along odd numbered horizontal lines and also covers section of said second portions of said substrate extending from first edge of said polycrystalline silicon first floating gate units along said odd numbered horizontal lines to form an array of half-of-M odd numbered rows along said odd numbered horizontal lines by N columns of holes in said third resist and said third resist holes separated along lines parallel to said vertical axis by half-of-M even numbered third resist rows arranged along said even numbered horizontal lines covering portions of said selected polycrystalline silicon segments along said even numbered horizontal lines and also covering portions of said source and drain regions and said channel regions along said even numbered horizontal lines forming first set of even numbered rows of said third resist separating said odd numbered horizontal lines of said third resist holes from each other along lines parallel to vertical axis; and etching said first polycrystalline silicon layer and removing said third resist layer thereby forming polycrystalline silicon second floating gates units from said selected polycrystalline silicon segments along said even numbered horizontal lines and said second floating gate units spaced apart along lines parallel to said vertical axis and said etching step also forming channel regions along said odd numbered horizontal lines each including drain area extending laterally from said drain regions to said first edge of said polycrystalline silicon first floating gate units underneath and source area extending from first edge of said polycrystalline silicon first floating gate units to an associated said source region and separated along lines parallel to said vertical axis by said second floating gate units. 9. A method according to claim 8 further comprising:forming second polycrystalline silicon to insulatively overlap the floating gate, source area of the channel, source region and drain region in each memory cell and said second polycrystalline silicon defining a control gate of said memory transistor connected to other control gates along a horizontal line to form a control word line along each of said horizontal lines forming a plurality of control word lines laterally spaced apart and insulated from each other. 10. A method according to claim 8 further comprising:forming second polycrystalline silicon to insulatively overlap first portion of the floating gate, source area of the channel, source region and drain region in each memory cell and said second polycrystalline silicon defining first control gate of said memory transistor connected to other first control gates along a horizontal line to form read/program/erase word line along each of said horizontal lines forming a plurality of read/program/erase word lines laterally spaced apart; and forming third polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally space apart from said channel region in each memory cell and said third polycrystalline silicon defining second control gate of said memory transistor connected to other second control gates along a horizontal line to form one steering word line between each pair of said read/program/erase word lines forming a plurality of steering word lines laterally spaced apart. 11. A method according to claim 8 further comprising:oxidizing said polycrystalline floating gates to form asperites, bumps and rough edges covered by a first silicon dioxide layer; etching said first silicon dioxide layer to expose said asperites, bumps and rough edges of each of said polycrystalline floating gates; growing a second silicon dioxide layer to cover the entire structure; forming second polycrystalline silicon to insulatively overlap first portion of the floating gate, source area of the channel, source region and drain region in each memory cell and said second polycrystalline silicon defining first control gate of said memory transistor connected to other first control gates along a horizontal line to form read/program/erase word line along each of said horizontal lines forming a plurality of read/program/erase word lines laterally spaced apart; and forming third polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally space apart from said channel region in each memory cell and said third polycrystalline silicon defining second control gate of said memory transistor connected to other second control gates along a horizontal line to form one steering word line between each pair of said read/program/erase word lines forming a plurality of steering word lines laterally spaced apart. 12. A method according to claim 8 further comprising:oxidizing said polycrystalline floating gates to form asperites, bumps and rough edges covered by a first silicon dioxide layer; etching said first silicon dioxide layer to expose said asperites, bumps and rough edges of each of said polycrystalline floating gates; growing a second silicon dioxide layer to cover the entire structure; forming second polycrystalline silicon to insulatively overlap first portion of the floating gate, source area of the channel, source region and drain region in each memory cell and said second polycrystalline silicon defining first control gate of said memory transistor connected to other first control gates along a horizontal line to form read/program/erase word line along each of said horizontal lines forming a plurality of read/program/erase word lines laterally spaced apart; implanting selected impurities to destroy said asperites, bumps and rough edges from second portion of each of said polycrystalline floating gates laterally space apart from said channel regions; and forming third polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally space apart from said channel region in each memory cell and said third polycrystalline silicon defining second control gate of said memory transistor connected to other second control gates along a horizontal line to form one steering word line between each pair of said read/program/erase word lines forming a plurality of steering word lines laterally spaced apart. 13. A method according to claim 8 further comprising:forming second polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally space apart from said channel region in each memory cell and said second polycrystalline silicon defining first control gate of said memory transistor connected to other first control gates along a horizontal line to form one steering word line between each pair of said horizontal lines forming a plurality of steering word lines laterally spaced apart; and forming third polycrystalline silicon to insulatively overlap first portion of the floating gate, source area of the channel, source region and drain region in each memory cell and said third polycrystalline silicon defining second control gate of said memory transistor connected to other second control gates along a horizontal line to form read/program/erase word line along each of said horizontal lines forming a plurality of read/program/erase word lines laterally spaced apart. 14. A method according to claim 8 further comprising:oxidizing said polycrystalline floating gates to form asperites, bumps and rough edges covered by a first silicon dioxide layer; etching said first silicon dioxide layer to expose said asperites, bumps and rough edges of each of said polycrystalline floating gates; growing a second silicon dioxide layer to cover the entire structure; forming second polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally space apart from said channel region in each memory cell and said second polycrystalline silicon defining first control gate of said memory transistor connected to other first control gates along a horizontal line to form one steering word line between each pair of said horizontal lines forming a plurality of steering word lines laterally spaced apart; and forming third polycrystalline silicon to insulatively overlap first portion of the floating gate, source area of the channel, source region and drain region in each memory cell and said third polycrystalline silicon defining second control gate of said memory transistor connected to other second control gates along a horizontal line to form read/program/erase word line along each of said horizontal lines forming a plurality of read/program/erase word lines laterally spaced apart. 15. A method according to claim 8 further comprising:oxidizing said polycrystalline floating gates to form asperites, bumps and rough edges covered by a first silicon dioxide layer; etching said first silicon dioxide layer to expose said asperites, bumps and rough edges of each of said polycrystalline floating gates; growing a second silicon dioxide layer to cover the entire structure; forming second polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally space apart from said channel region in each memory cell and said second polycrystalline silicon defining first control gate of said memory transistor connected to other first control gates along a horizontal line to form one steering word line between each pair of said horizontal lines forming a plurality of steering word lines laterally spaced apart; implanting selected impurities to destroy said asperites, bumps and rough edges from first portion of each of said polycrystalline floating gates overlapping said drain area of the channel; and forming third polycrystalline silicon to insulatively overlap said first portion of the floating gate, source area of the channel, source region and drain region in each memory cell and said third polycrystalline silicon defining second control gate of said memory transistor connected to other second control gates along a horizontal line to form read/program/erase word line along each of said horizontal lines forming a plurality of read/program/erase word lines laterally spaced apart. 16. A method of manufacturing an array of non-volatile memory transistors containing a floating gate comprising:depositing a nitride layer on, but separated from a surface of semiconductor substrate by first insulation; forming first resist layer on said nitride layer and patterning said first resist into spaced apart first resist segments separated by first resist windows; etching said nitride layer through said first resist windows to form first nitride windows directly underneath said resist windows and extending in the direction of the semiconductor surface down to surface of said insulation thereby forming nitride segments separated by said nitride windows; removing said first resist to reveal said nitride segments and nitride windows; depositing first polycrystalline silicon layer over the entire structure; anisotropically etching said polycrystalline silicon in a direction perpendicular to the surface of said substrate thereby exposing the top surface of said nitride segments and forming pairs of said polycrystalline silicon segments each segment laterally extending from said nitride segment into a separate said nitride windows and having first edge opposite second edge and first edge of each of said polycrystalline silicon segments positioned near an associated said nitride segment and said second edge of a selected said polycrystalline silicon segment spaced apart from said second edge of a first adjacent polycrystalline silicon segment across a portion of an associated said nitride window to form first opening therewithin and said polycrystalline silicon segments are arranged in lines parallel to a vertical axis and spaced apart along a horizontal axis perpendicular to said vertical axis; implanting first selected impurities layer through said first opening into first portions of said semiconductor substrate thereby to simultaneously form source and drain regions each extending from and self aligned to said second edge of respective polycrystalline silicon segments and running vertically in lines parallel to said vertical axis; chemically stripping said nitride segments to expose second portions of said semiconductor substrate extending from first edge of said selected polycrystalline silicon segments to first edge of a second adjacent polycrystalline silicon segments laterally extending from first source regions by geometrical width of said polycrystalline silicon segments; thermally growing second oxide layer over the entire structure; anisotropically etching said second oxide layer in a direction perpendicular to the surface of said substrate thereby forming first thin side wall oxide abutting said first and second edge of said first polycrystalline silicon segments; depositing third oxide layer over the entire structure; anisotropically etching said third oxide layer in a direction perpendicular to the surface of said substrate thereby forming second thin side wall oxide abutting said first side wall oxide to form an oxide spacer extending from each side of said first polycrystalline silicon segments and covering portion of said source and drain regions and portion of said second portions of the substrate; implanting a second impurities layer with lighter dose then said first selected impurities layer over the entire structure to form a lightly doped source region in said second portions of said semiconductor substrate thereby to form asymmetry between the electrical source and electrical drain of each transistor; forming a second resist layer pattern over said selected polycrystalline silicon segment but not over said first adjacent or said second adjacent polycrystalline silicon segments, and said second resist layer covers section of said drain regions extending from said second edge of said selected polycrystalline silicon segments and also covers section of said lightly doped source region of extending from first edge of said selected polycrystalline silicon segments to form an array of half-of-M even numbered rows along even numbered horizontal lines by N columns of holes in said second resist said holes separated along lines parallel to said vertical axis by half-of-M odd numbered second resist rows arranged along odd numbered horizontal lines covering portions of said pairs of polycrystalline silicon segments and said portions of source and drain regions and said lightly doped source region along said odd numbered horizontal lines; etching said first polycrystalline silicon layer and removing said second resist layer thereby forming polycrystalline silicon first floating gates units from first adjacent and second adjacent polycrystalline silicon segments along said odd numbered horizontal lines and said first floating gate units spaced apart along a line parallel to said vertical axis and said etching step also forming channel regions along said even numbered horizontal lines each extending laterally from said drain regions to said first edge of said selected polycrystalline silicon segments underneath and abutting said lightly doped source region extending from first edge of said selected polycrystalline silicon segments to an associated said source region and separated along lines parallel to said vertical axis by rows of said first floating gate units arranged along said odd numbered horizontal line; forming a third resist layer pattern over said polycrystalline silicon first floating gate units but not over portions of said selected polycrystalline silicon segments along said odd numbered horizontal line, and said third resist layer covers section of said drain regions extending from said second edge of said polycrystalline silicon first floating gate units along odd numbered horizontal lines and also covers section of said lightly doped source region extending from first edge of said polycrystalline silicon first floating gate units along said odd numbered horizontal lines to form an array of half-of-M odd numbered rows along said odd numbered horizontal lines by N columns of holes in said third resist and said third resist holes separated along lines parallel to said vertical axis by half-of-M even numbered third resist rows arranged along said even numbered horizontal lines covering portions of said selected polycrystalline silicon segments along said even numbered horizontal lines and also covering portions of said source and drain regions and said lightly doped source regions along said even numbered horizontal lines forming first set of even numbered rows of said third resist separating said odd numbered horizontal lines of said third resist holes from each other along lines parallel to said vertical axis; etching said first polycrystalline silicon layer and removing said third resist layer thereby forming polycrystalline silicon second floating gates units from said selected polycrystalline silicon segments along said even numbered horizontal lines and said second floating gate units spaced apart along lines parallel to said vertical axis and said etching step also forming channel regions along said odd numbered horizontal lines each including drain area extending laterally from said drain regions to said first edge of said polycrystalline silicon first floating gate units underneath and lightly doped source region extending from first edge of said polycrystalline silicon first floating gate units to an associated said source region and separated along lines parallel to said vertical axis by said second floating gate units; and implanting a third impurities layer with a dose similar to said first selected impurities layer over the entire structure to extend said source region partially into said lightly doped source region and to abut said oxide spacer thereby to define the width of said lightly doped source region to be the same as the width of said oxide spacer. 17. A method according to claim 16 further comprising:forming second polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally space apart from said channel region in each memory cell and said second polycrystalline silicon defining first control gate of said memory transistor connected to other first control gates along a horizontal line to form one steering word line between each pair of said horizontal lines forming a plurality of steering word lines laterally spaced apart; and forming third polycrystalline silicon to insulatively overlap first portion of the floating gate, said lightly doped source region, source region and drain region in each memory cell and said third polycrystalline silicon defining second control gate of said memory transistor connected to other second control gates along a horizontal line to form read/program/erase word line along each of said horizontal lines forming a plurality of read/program/erase word lines laterally spaced apart. 18. A method according to claim 16 further comprising:oxidizing said polycrystalline floating gates to form asperites, bumps and rough edges covered by a forth silicon dioxide layer; etching said fourth silicon dioxide layer to expose said asperites, bumps and rough edges of each of said polycrystalline floating gates; growing a fifth silicon dioxide layer to cover the entire structure; forming second polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally space apart from said channel region in each memory cell and said second polycrystalline silicon defining first control gate of said memory transistor connected to other first control gates along a horizontal line to form one steering word line between each pair of said horizontal lines forming a plurality of steering word lines laterally spaced apart; and forming third polycrystalline silicon to insulatively overlap first portion of the floating gate, lightly doped source region of the channel, source region and drain region in each memory cell and said third polycrystalline silicon defining second control gate of said memory transistor connected to other second control gates along a horizontal line to form read/program/erase word line along each of said horizontal lines forming a plurality of read/program/erase word lines laterally spaced apart. 19. A method according to claim 16 further comprising:oxidizing said polycrystalline floating gates to form asperites, bumps and rough edges covered by a fourth silicon dioxide layer; etching said fourth silicon dioxide layer to expose said asperites, bumps and rough edges of each of said polycrystalline floating gates; growing a fifth silicon dioxide layer to cover the entire structure; forming second polycrystalline silicon to insulatively overlap source region, drain region and second portion of the floating gate laterally space apart from said channel region in each memory cell and said second polycrystalline silicon defining first control gate of said memory transistor connected to other first control gates along a horizontal line to form one steering word line between each pair of said horizontal lines forming a plurality of steering word lines laterally spaced apart; implanting selected impurities to destroy said asperites, bumps and rough edges from first portion of each of said polycrystalline floating gates overlapping said drain area of the channel; and forming third polycrystalline silicon to insulatively overlap first portion of the floating gate, lightly doped source region of the channel, source region and drain region in each memory cell and said third polycrystalline silicon defining second control gate of said memory transistor connected to other second control gates along a horizontal line to form read/program/erase word line along each of said horizontal lines forming a plurality of read/program/erase word lines laterally spaced apart. Description
This application is a division of application Ser. No. 152,702, filed July 7, 1989, now U.S. Pat. No. 4,845,538.
The invention of application Ser. No. 152,702, now U.S. Pat. No. 4,845,538 issued to the present applicant E. Hazani uses electron tunneling between two polysilicon layers to perform programming and erasure. U.S. Pat. No. 4,763,299 issued to Emanuel Hazani (the '299 patent) describes an invention that uses hot electrons from the substrate to program and polysilicon to polysilicon electron tunneling to erase.
Although the EEPROM cell and process described in application Ser. No. 331,481, which is a continuation in part to application Ser. No. 152,702, now U.S. Pat. No. 4,845,538 issued to the present applicant E. Hazani, results in a small cell area it requires higher on-chip programming voltage. Also as typical to EEPROMs that program using electron tunneling the cell programming time of such an embodiment is about two milliseconds (2 mS), which is relatively long. So usage for this invention are in applications where low cost is the most important factor. The following are some examples: computer program-memory, computer operating systems memory, and smart identification cards.
The invention of the '299 patent programs by using hot electrons from the substrate. It has a very high programming efficiency due to the use of two control gates to couple the programming voltage to the floating gate. The programming time of a cell of this embodiment is much shorter then that of a tunneling-program mechanism, in the range of one micro second (1 uS). This programming efficiency also reduces the programming drain-source current to about one micro Ampere (1 uA), which is much lower in comparison to other UVEPROM and EEPROM cells that program by using hot electrons from the substrate.
FIGS. 16a and 16b illustrate a cross section and top view, which result after a stage in the processing of the fifth embodiment of the invention, which does not have a split gate structure. This stage of processing come after the stage of FIGS. 7a and 7b of the first embodiment, but relates to the fifth embodiment. FIGS. 16a and 16b illustrate the use of CVD oxide spacer in the formation of N-implant in one side of the floating gate in order to create an asymmetry in programming of a non-split-gate EEPROM embodiment.
FIG. 1 depicts the overall layout of the array of EEPROM cells. Referring not to FIG. 1, the array is laid out on the major surface 10 of a P doped monocrystalline silicon substrate. A first set of equispaced, vertical N+ regions 12 form the source/drain lines of the array. These source/drain lines are crossed by a first set of horizontal polysilicon read word lines 14. The source/drain lines 12 are also crossed by a second set of horizontal polysilicon program/erase word lines 15. A third set of floating gate poly layers 30 each include a first region disposed below an associated word line 14.
FIG. 4a illustrates a cross sectional view of the wafer for a fabrication step, which comes after the definition of the isolation regions. Field isolation regions are defined by a photolithography mask step. These defined region are then etched into the wafer and the field oxide 41 is then thermally grown over these regions in a manner well known in the art. In FIG. 4a a thin oxide layer of 250 Angstroms is thermally grown at 800 degrees Celsius to form gate oxide 29a of floating gate 30. Thereafter a nitride film 35 is deposited to form a thickness of about 3500 Angstroms and patterned by isotropic etching, by plasma for example, to form equispaced nitride lines in parallel to the bit-line axis. The result is illustrated as a top view in FIG. 4b.
Polysilicon layer 30 is then deposited as illustrated in FIG. 5 for example at 650 degrees Celsius by low pressure chemical vapor deposition (LPCVD) to a desired thickness, for example 5000 Angstrom, which is half a micrometer (0.5 um). The polysilicon layer 30 is then doped with phosphorous by passing POCL3 through a chamber at 950 degree Celsius for about 15 minutes.
The anisotropic etching of the polysilicon 30 by plasma or preferably by RIE, provide another opportunity to reduce the memory cell size by narrowing the width of bit line diffusion 28, which is measured between polysilicon lines 30. This can be done due to the ability of the anisotropic etching by plasma or RIE to create a space for diffusion 28, as narrow as 0.3 micrometers in today's technology, between the two polysilicon lines 30. This could not be achieved if today's photolithography equipment would be used, as described for example in prior art U.S. Pat. No. 4,639,893 assigned to Waferscale Integration Inc., which discloses a process to manfacture a split gate UVEPROM.
By having the capability to narrow the width of bit line 28, one can design the mask of nitride layer 35 (and layer 41), so as to bring the parallel nitride stripes 35 much closer to each other, thus reduce memory cell size. The practical limit of reduction will be the ability to use resist mask 20 to define the geometrical length of floating gates 30 in one masking step. This is because resist mask 20, which is used to etch polysilicon line 30, will limit the spacing between poly lines 30 along the geometrical width to the photolithography specification.
Using two separate photoresist masks 27 and 36, permits further narrowing of the distance between centers of adjacent nitride lines 35 (and mask 41). This is accomplished by over exposing the positive photoresist mask that defines the nitride lines 35 (and that of mask 41) of FIGS. 4a and 4b, to a point where the nitride lines 35 are etched to produce final line-width narower then the minimum specification of the photolithography equipment. When the final line width of nitride 35 and isolation layer 41 are planned in advance to take advantage of the overexposed masks, the photoresist masks of layers 35 and 41, will be designed to draw a significantly smaller size memory cell that will include the narrow diffusion bit-line width 28 created by the anisotropic etching procedure described above.
In the next processing step the 250 Angstroms thin oxide 29a is removed from all area of the wafer excluding channel region 34a under floating gates 30, where it functions as gate oxide. Floating gate polysilicon 30 protects oxide 29a underneath it from the etchant that etches oxide much faster then polysilicon. This is done in preparation for growing the interpoly oxide dielectric between floating gate poly 30 and either of the word lines' polysilicon. This procedure keeps the oxide thickness over channel region 34b close to the oxide thickness over channel region 34a.
Another layer of TEOS (tetraethylothosilane) based LPCVD oxide layer 32 is deposited to a thickness of about 300 Angstrom over thermal oxide 31, as shown in FIG. 2. This combination of thermal oxide and deposited oxide dielectric was shown to increase the oxide breakdown voltage and reduce electron trapping in the oxide, which is advantageous in EEPROM memory chips. Although, a combination of thermal oxide and deposited oxide was chosen in this embodiment, thermal oxide along or deposited oxide alone will be sufficient to function as the interpoly dielectric.
In the following step in the process a photoresist layer 63 (not shown) aligned to the second polysilicon layer 33, defines the steering program/erase word line 60s. Polysili-con 60s is etched away except from the area over the steering regions 30s of the floating gate polysilicon 30 where it serves as a word line 15 of FIG. 1.
It was disclosed in application Ser. No. 152,702, now U.S. Pat. No. 4,845,538 issued to the present applicant E. Hazani, and in accompanying application Ser. No. 331,481 that the cell may be programmed by holding the drain diffusion 28 at a high voltage Vpp while the control gate polysilicon 33 (read word line 14 of FIG. 1) is held at Vss ground potential. The source diffusion 28 may be held at Vss or at half Vpp (1/2*Vpp). This biasing condition ensures that the source area of the channel 34b is not inverted and that there is no current between drain and source. At this voltage conditions the drain voltage is coupled to the floating gate through the capacitance of the overlap area between floating gate 30 and drain diffusion 28a. The floating gate voltage increases to such a level which is higher than the unprogrammed threshold voltage of the cell, thus inverting the drain area of the channel 34a. Once the drain area 34a is inverted it carries the high voltage Vpp of the drain diffusion 28a. The capacitive coupling between the channel's drain area 34a and the floating gate 30 is about 10 times that of the capacitive coupling between the drain 28a and the floating gate 30.
TABLE (1)______________________________________      VD     VS     VP2      VP3  IDS______________________________________Selected Even        14       7      0      14   0Numbered RowUnselected    7       7      0      14   0On Same RowUnselected On         7       14     7       3   0Same ColumnOdd Numbered RowUnselected On        14       7      7      3    0Same ColumnEven Numbered Row______________________________________
For unselected cells in the same row, VD is 7 Volts, VP3 is 14 Volts, so VP1 is about 5 volts, which is the voltage difference between P1 and P2. This voltage difference is insufficient to cause reverse tunnelling. For unselected cells in the same column, the potential of the read work lines 14 is at 7 V, thus the potential difference between the floating gates 30 to the control gates 14 is about 3 volts, which is below the reverse tunneling threshold. Thus these cells will not program undesirably due to tunnelling of electrons. In addition VGS of the cell is 0 volts, because VP2 is 0 volts and SA is not depleted, so that no IDS exists. Thus accidental hot electron programming will not occur. Accordingly, the present system provides for programming a single cell. Very little, current is drawn because the floating gate is charged by the tunnelling mechanism.
Details about the assymmetry associated with the cell's programming operation and the reason that adjacent cells on the same row do not program, are detailed in the '299 patent.
During read operation of the selected cell the drain voltage is held relatively low at about 1 volt in order to prevent "soft write", which is an undesired acceleration of hot electrons that by accumulating with time on the floating gate 30 may change the cell's threshold voltage and so change a predetermined binary state of the cell. The source voltage is held at about 0 volts and the read word line 14 is at 5 volts. The program/erase word line 15 is held at about 3 volts in order to prevent a potential difference of more than 3.2 electron-Volts (3.2 eV is the band-gap energy of the polysilicon to silicon dioxide interface) to the floating gate 30, thus cause charge loss to this word line, which is lightly coupled to the floating gate 30 at about 10 percent capacitive ratio. In contrast, the read word line 14 is heavily coupled to the floating gate at about 85 percent capacitive ratio, thus will always pull the floating gate 30 closer to its voltage, which guarantees less the 3.2 eV potential difference across than oxide dielectric.
In order to create the asymmetry in hot electrons programming of this embodiment, an n- implant into the substrate of arsenic with a dose of about 3E13 cm-2 is performed at about 40 KeV.
When programming a cell of the second version of the fifth embodiment in an array, a source voltage biasing is required at about 1 Volt. This is done in order to minimize a parasitic drain to source current that is introduced by unselected cells along the same bit-line, but under different word lines. This phenomenon is called "drain turn-on" and is introduced by coupling of the drain 28's voltage to the floating gate 30 to a point where the channel 34 is depleted and current starts to flow between drain and source. This phenomenon is well known in the art, and does not exist in the split gate embodiments, such as the third and fourth since the floating gate 30 inverts only the drain area 34a, where the source are 34b is "off" because it is covered by the read word line polysilicon 33, which is held at 0 volts for the unselected cells.
Preferred embodiments of the invention have now been described. Various substitutions and alterations to these embodiments will be apparent to persons of skill in the art apprised by the teaching of this patent. It is therefore not intended that the invention be limited to the described embodiments, but that the invention be defined by the appended claims.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4763299 *Oct 15, 1985Aug 9, 1988Emanuel HazaniE2 PROM cell and architectureUS4794565 *Sep 15, 1986Dec 27, 1988The Regents Of The University Of CaliforniaElectrically programmable memory device employing source side injectionUS4845538 *Feb 5, 1988Jul 4, 1989Emanuel HazaniE2 prom cell including isolated control diffusionUS4868629 *Aug 2, 1985Sep 19, 1989Waferscale Integration, Inc.Self-aligned split gate EPROM* Cited by examinerNon-Patent CitationsReference1 *J. Miyamoto et al., A 1.0 m CMOS/Bipolar Technology for VLSI Circuits, IEDM 83.2J. Miyamoto et al., A 1.0 μm CMOS/Bipolar Technology for VLSI Circuits, IEDM-83.3 *K. Yoshikawa et al., An Asymmetrical Lightly Doped Source (ALDS), Cell for Virtual, Ground High Density EPROMs, IEDM 88, 1988.4K. Yoshikawa et al., An Asymmetrical Lightly-Doped Source (ALDS), Cell for Virtual, Ground High Density EPROMs, IEDM-88, 1988.5 *R. Kazerounian et al., A 5 Volt High Density Poly Poly Erase Flash EPROM Cell, IEDM 88 (Dec. 11).6R. Kazerounian et al., A 5 Volt High Density Poly-Poly Erase Flash EPROM Cell, IEDM-88 (Dec. 11).7 *T. Mizuno et al., Si 3 N 4 /SiO 2 Spacer Induced High Reliability in LODMOSFET and Its Simple Degradation Model, IEDM 88.8T. Mizuno et al., Si3 N4 /SiO2 Spacer Induced High Reliability in LODMOSFET and Its Simple Degradation Model, IEDM-88.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5303329 *Dec 10, 1991Apr 12, 1994Synaptics, IncorporatedContinuous synaptic weight update mechanismUS5498558 *May 6, 1994Mar 12, 1996Lsi Logic CorporationIntegrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making sameUS5521108 *Sep 15, 1993May 28, 1996Lsi Logic CorporationProcess for making a conductive germanium/silicon member with a roughened surface thereon suitable for use in an integrated circuit structureUS5527168 *Aug 3, 1994Jun 18, 1996Eaton CorporationSupercharger and housing, bearing plate and outlet port thereforUS5644152 *Jun 5, 1995Jul 1, 1997Lsi Logic CorporationConductive germanium/silicon member with a roughened surface thereon suitable for use in an integrated circuit structureUS5650648 *Jun 5, 1995Jul 22, 1997Lsi Logic CorporationIntegrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making sameUS5814543 *Nov 22, 1995Sep 29, 1998Hitachi, Ltd.Method of manufacturing a semicondutor integrated circuit device having nonvolatile memory cellsUS6127240 *Jan 8, 1998Oct 3, 2000Mitsubishi Denki Kabushiki KaishaMethod of manufacturing a semiconductor device having a capacitorUS6242304 *May 29, 1998Jun 5, 2001Micron Technology, Inc.Method and structure for textured surfaces in floating gate tunneling oxide devicesUS6259130 *Mar 9, 1999Jul 10, 2001Texas Instruments - Acer IncorporatedHigh density flash memories with high capacitive-couping ratio and high speed operationUS6316316 *Jun 18, 1999Nov 13, 2001Texas Instruments-Acer IncorporatedMethod of forming high density and low power flash memories with a high capacitive-coupling ratioUS6359321 *Jun 13, 1997Mar 19, 2002Mitsubishi Denki Kabushiki KaishaMIS transistor and method of fabricating the sameUS6403455Aug 31, 2000Jun 11, 2002Samsung Austin Semiconductor, L.P.Methods of fabricating a memory deviceUS6476441Jun 4, 2001Nov 5, 2002Micron Technology, Inc.Method and structure for textured surfaces in floating gate tunneling oxide devicesUS6528844 *Oct 31, 2001Mar 4, 2003National Semiconductor CorporationSplit-gate flash memory cell with a tip in the middle of the floating gateUS6689668Aug 31, 2000Feb 10, 2004Samsung Austin Semiconductor, L.P.Methods to improve density and uniformity of hemispherical grain silicon layersUS6706597Nov 1, 2002Mar 16, 2004Micron Technology, Inc.Method for textured surfaces in floating gate tunneling oxide devicesUS6849514Dec 30, 2003Feb 1, 2005Donghu Electronics Co., Ltd.Method of manufacturing SONOS flash memory deviceUS6861306Nov 13, 2002Mar 1, 2005National Semiconductor CorporationMethod of forming a split-gate memory cell with a tip in the middle of the floating gateUS7586145 *Jul 27, 2005Sep 8, 2009Taiwan Semiconductor Manufacturing Co. LtdEEPROM flash memory device with jagged edge floating gateUS8320191Nov 27, 2012Infineon Technologies AgMemory cell arrangement, method for controlling a memory cell, memory array and electronic deviceUS9030877Oct 11, 2012May 12, 2015Infineon Technologies AgMemory cell arrangement, method for controlling a memory cell, memory array and electronic deviceUS20040157434 *Dec 30, 2003Aug 12, 2004Chang Hun HanMethod of manufacturing SONOS flash memory deviceUS20070023816 *Jul 27, 2005Feb 1, 2007Taiwan Semiconductor Manufacturing Co., Ltd.EEPROM flash memory device with jagged edge floating gate* Cited by examinerClassifications U.S. Classification438/260, 438/594, 257/E27.103, 257/E29.304, 438/266, 438/264International ClassificationH01L27/115, G11C16/04, G11C11/56, H01L29/788, G11C16/10Cooperative ClassificationG11C11/5621, G11C2211/5611, H01L29/7883, H01L27/115, G11C2029/0403, G11C16/10, G11C11/5628, G11C16/0425, G11C11/5635European ClassificationG11C16/10, G11C16/04F2, G11C11/56D2, H01L27/115, G11C11/56D, G11C11/56D2E, H01L29/788B4Legal EventsDateCodeEventDescriptionSep 19, 1995REMIMaintenance fee reminder mailedDec 8, 1995FPAYFee paymentYear of fee payment: 4Dec 8, 1995SULPSurcharge for late paymentSep 7, 1999REMIMaintenance fee reminder mailedFeb 13, 2000LAPSLapse for failure to pay maintenance feesApr 25, 2000FPExpired due to failure to pay maintenance feeEffective date: 20000211RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services