Source: http://www.google.com/patents/US5581745?dq=7,007,239
Timestamp: 2014-03-13 07:14:32
Document Index: 661241468

Matched Legal Cases: ['art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 32']

Patent US5581745 - Apparatus for suspending the bus cycle of a microprocessor by inserting wait ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn interrupt request processing device and method for control of the bus cycle of a microprocessor which implements predetermined wait periods dependent upon a detected wait request. Predetermined wait states, programmable in the microprocessor, are assigned to wait request signals for implementation...http://www.google.com/patents/US5581745?utm_source=gb-gplus-sharePatent US5581745 - Apparatus for suspending the bus cycle of a microprocessor by inserting wait statesAdvanced Patent SearchPublication numberUS5581745 APublication typeGrantApplication numberUS 08/168,392Publication dateDec 3, 1996Filing dateDec 17, 1993Priority dateJan 12, 1990Fee statusLapsedAlso published asEP0437276A2, EP0437276A3Publication number08168392, 168392, US 5581745 A, US 5581745A, US-A-5581745, US5581745 A, US5581745AInventorsKiminori Fujisaku, Hiroshi MuraokaOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (24), Referenced by (75), Classifications (10), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetApparatus for suspending the bus cycle of a microprocessor by inserting wait statesUS 5581745 AAbstract An interrupt request processing device and method for control of the bus cycle of a microprocessor which implements predetermined wait periods dependent upon a detected wait request. Predetermined wait states, programmable in the microprocessor, are assigned to wait request signals for implementation of a predetermined wait period corresponding to a detected wait request signal, in which the bus cycle is suspended for the predetermined wait period while the signal to be applied to the connected peripheral device is held during access to the peripheral device. After the predetermined wait period is over the bus cycle is unsuspended and the microprocessor is again able to detect wait request signals.
What is claimed is: 1. A data processing device comprising:a control part for processing data and communicating with one of a plurality of peripheral devices during a bus cycle; a plurality of registers, each register being connected to said control part for storing data which designates a length of a wait period; and a plurality of wait circuits, each wait circuit suspending said bus cycle in response to a wait request signal and maintaining the bus cycle suspension regardless of a succeeding wait signal by outputting a wait instruction signal, "OR" logic means, having said wait instruction signals of each wait circuit as inputs and having an output to said control part; whereinsaid data processing device holds a signal to be applied to one of the plurality of peripheral devices accessed during said wait period, and resumes said bus cycle after a lapse of said wait period. 2. The microprocessor according to claim 1 wherein said control part, said wait circuit, and said register are provided in an Large Scale Integrated chip.
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1A, 1B and 1C are circuit diagrams for explaining the principle of this invention.
FIRST EMBODIMENT FIGS. 2 and 3 show the first embodiment of the microcomputer and its bus cycle control method according to the present invention.
Because initial values of the number of wait States comparing circuit 23 and the number of wait states setting register 13 are all "0" after the microprocessor 11 is reset, the output QX from the number of wait states comparing circuit 23 becomes "0", and both the wait request latching circuit 21 and the counter circuit 22 are reset. Hence, until any value other than "00.sub.B " is set in the number of wait states setting register 13 after the microprocessor 11 is reset, the output QX of the number of wait states comparing circuit 23 remains "0" and each circuit is kept reset. Thus, the wait instruction signal for the microprocessor 11 becomes a deactivating (wait clearing) signal.
If "11.sub.B " is set to the number of wait states register 13 after reset clearing of the microprocessor 11, the input value "00.sub.B " (C1, C0) from the counter circuit 22 does not agree with the input value "11.sub.B " (WS1, WS0) from the number of wait states setting register 13 at the number of wait states comparing circuit 23. Thus, the wait state number register 13 outputs "1" as a result of comparing the timing of the rising or falling edges of the clock TFP. Consequently, the resetting of the wait request latching circuit 21 and the counter circuit 22 are cleared (RX input is set to "1"), and the wait request latching circuit 21 becomes capable of latching the wait request at a predetermined timing and counter circuit 22 becomes capable of performing a count-up operation.
If an address signal is concurrently outputted from the microprocessor 11 to the peripheral device 16, it is detected as a wait request signal by the address selector circuit 15. That is, only when the addresses A0, A1 and A2 outputted from the main control part 12 are "111.sub.B " does the address selector circuit 15 output "1" and a wait request for the microprocessor 11. Here, the output level of the wait request signal is assumed to be finalized at a latching, since the wait request latching circuit 21 latches the wait request signal at a timing of a rising edge of the clock TL. In other words, the addresses A0, A1 and A2 outputted from the main control part 12 are assumed to be finalized sufficiently in advance of the rising of the clock TL (to allow time for signal propagation delays due to, e.g., gate delay and wiring capacitance).
Since the latched signal is "1", the main control part 12 latches the wait instruction signal at a falling of the clock TL and inserts one wait state into the next bus cycle. The wait instruction signal is also inputted to the counter circuit 22 as its count enabling signal (EN). The counter circuit 22 is counted up at a falling timing of the clock TL when the wait instruction signal is "1", and the output changes from "00.sub.B " to "01.sub.B ".
The number of wait states comparing circuit 23 compares the input value "01.sub.B " (C1, C0) from the counter circuit 22 with the input value "11.sub.B " (WS1, WS0) at a rising or falling timing of the clock TFP. Due to the non-agreement, however, the output QX remains "1", and the wait request latching circuit 21 continues to output the wait instruction signal "1" (the wait request) to the main control part 12.
Then, the wait request latching circuit 21 outputs the wait instruction signal "1" to the main control part 12, until the counter circuit 22 is counted up at a timing of a falling edge of the clock TL, and their outputs Q1 and Q0 change from "00.sub.B " through "01.sub.B " and "10.sub.B " to "11.sub.B ", and finally match the value of the number of wait states "11.sub.B " and the number of wait states comparing circuit 23 outputs "0" (agreement) as a comparing result. Thereafter, since the wait request latching circuit 21 and the counter circuit 22 are reset (RX input is "0") when the number of wait states comparing circuit 23 outputs "0" (agreement), the wait instruction signal becomes "0" and the main control part 12 ceases to insert a wait state from the next bus cycle.
SECOND EMBODIMENT FIG. 4 is a circuit diagram showing of the second embodiment of this invention, in which a plurality (n pieces) of peripheral devices 16a through 16n and their corresponding address selector circuits 15a through 15n are provided. The address selector circuits 15a through 15n detect a chip-select signal outputted from a main control part 32 corresponding to peripheral devices 16a through 16n as wait request signals 1 through n, and output the results to the corresponding wait instruction circuits 33a through 33n. That the address selector circuits 15a through 15n output chip-select signals to the corresponding peripheral devices 16a through 16n.
THIRD EMBODIMENT FIGS. 5 and 6 illustrate the third embodiment of this invention.
FOURTH EMBODIMENT FIG. 7 is a circuit diagram of the fourth embodiment of this invention, in which a plurality (n pieces) of peripheral devices 16a through 16n and their corresponding address selector circuits 55a through 55n are provided, as in the second embodiment. The address selector circuits 55a through 55n differ from the address selector circuits 15a through 15n shown in the second embodiment in that they are changed to output chip-select signals in synchronization with a timing of a falling edge of an address strobing signal (ADS) outputted from a microprocessor 51 to the peripheral devices 16a through 16n. 52 is a main control part.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A, 1B and 1C are circuit diagrams for explaining the principle of this invention;
BACKGROUND OF THE INVENTION This invention pertains to a microcomputer and a method for controlling its bus cycle, and in particular, to a microcomputer and a bus cycle control method with an improved wait control of the bus cycle.
DESCRIPTION OF THE RELATED ART With recent advances in the microcomputer field, demand for improved functions has necessarily increased. Various special chips, Large Scale Integration packages (LSIs), for executing particular functions normally performed by a Central Processing Unit (CPU) or microprocessor, have been developed as peripheral devices to CPUs. Microprocessors for controlling peripheral devices need to have a wait state inserted into their bus cycle to make their speed correspond with that of low-speed peripheral devices.
SUMMARY OF THE INVENTION This invention aims at providing a microcomputer and a bus cycle control method that enables an automatic wait control of a microcomputer at a low cost, without significantly increasing the size of either the microprocessor's internal circuit or its external circuit necessary for a wait control.
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