Source: http://www.google.com/patents/US8054129?dq=6,108,703
Timestamp: 2016-10-23 06:29:58
Document Index: 719014081

Matched Legal Cases: ['Application No. 2006', 'Application No. 2006', 'Application No. 2005', 'art 100', 'art 100', 'art 100', 'art 100', 'art 100', 'art 100', 'art 100', 'art 100', 'art 100', 'art 100', 'art 100', 'art 100', 'Application No. 2006', 'Application No. 2006', 'Application No. 201010147558', 'Application No. 201010147571', 'Application No. 201010147574']

Patent US8054129 - Class D amplifier - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA class D amplifier includes: an amplifier that generates a digital signal for driving a load based on an input signal; an attenuator that attenuates the input signal according to an attenuation command signal; and a clip prevention controller that outputs the attenuation command signal to intermittently...http://www.google.com/patents/US8054129?utm_source=gb-gplus-sharePatent US8054129 - Class D amplifierAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8054129 B2Publication typeGrantApplication numberUS 12/317,613Publication dateNov 8, 2011Priority dateSep 28, 2005Fee statusPaidAlso published asCN1941613A, CN1941613B, CN101807887A, CN101807887B, CN101807888A, CN101807888B, CN101807889A, CN101807889B, EP1770855A1, EP1770855B1, EP1962419A2, EP1962419A3, EP1962419B1, US7482870, US8299853, US20070103234, US20090115514, US20110221529Publication number12317613, 317613, US 8054129 B2, US 8054129B2, US-B2-8054129, US8054129 B2, US8054129B2InventorsToshio MaejimaOriginal AssigneeYamaha CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (22), Non-Patent Citations (10), Classifications (6), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetClass D amplifier
US 8054129 B2Abstract
A class D amplifier includes: an amplifier that generates a digital signal for driving a load based on an input signal; an attenuator that attenuates the input signal according to an attenuation command signal; and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.
an amplifier that generates a digital signal for driving a load based on an input signal, the amplifier including an error integrator that integrates errors between the input signal and the digital signal and outputs an error signal indicative of the integrated errors;
a clip prevention controller that outputs an attenuation command signal when the error signal from the error integrator exceeds a reference level; and
an attenuator coupled between the input terminal and the amplifier to attenuate the input signal according to the attenuation command signal.
2. The class D amplifier according to claim 1, wherein
the amplifier outputs the digital signal having a pulse width corresponding to the input signal according to a periodic synchronization signal, and
the clip prevention controller outputs the attenuation command signal according to the periodic synchronization signal.
3. The class D amplifier according to claim 2, further comprising:
a triangular wave generator for outputting a periodic triangular wave signal as the periodic synchronization signal,
wherein the amplifier includes a pulse-width modulator for outputting the digital signal having the pulse width modulated according to a level of the error signal from the error integrator by comparing the error signal from the error integrator with the triangular wave signal, and
wherein the clip prevention controller assumes that the digital signal is in a clip state or a near-clip state when the error signal from the error integrator exceeds the reference level and outputs the attenuation command signal.
4. The class D amplifier according to claim 1,
wherein the digital signal is in a clip state or a near-clip state when the error signal from the error integrator exceeds the reference level.
5. The class D amplifier according to claim 3, wherein
the clip prevention controller includes a comparison voltage generator for generating a comparison voltage at a level where the comparison voltage crosses the triangular wave signal when the error signal from the error integrator exceeds the reference level, and a comparator for comparing the comparison voltage with the triangular wave signal to output the attenuation command signal.
6. The class D amplifier according to claim 3, wherein
the clip prevention controller detects that the digital signal is in the clip state or the near-clip state based on the level of the digital signal at a timing of a peak of the triangular wave signal or at an immediately previous timing of the peak.
7. The class D amplifier according to claim 3, wherein
the clip prevention controller holds a signal showing the result of comparison between the error signal from the error integrator and the triangular wave signal at a timing of a peak of the triangular wave signal or at an immediately after timing of the peak and detects that the digital signal is in the clip state or the near-clip state based on the held signal.
8. A class D amplifier comprising:
an amplifier that generates a digital signal for driving a load based on an input signal,
an attenuator that includes a transistor provided at an input part of the amplifier and attenuates the input signal by turning the transistor on according to an attenuation command signal; and
a clip prevention controller that outputs the attenuation command signal to attenuate the input signal.
9. The class D amplifier according to claim 8, wherein
10. The class D amplifier according to claim 9, wherein
the amplifier includes an error integrator that integrates errors between the input signal and the digital signal and outputs an error signal indicative of the integrated errors.
11. The class D amplifier according to claim 10,
12. The class D amplifier according to claim 10, further comprising:
13. The class D amplifier according to claim 12, wherein
14. The class D amplifier according to claim 12, wherein
15. The class D amplifier according to claim 12, wherein
the clip prevention controller holds a signal showing the result of comparison peak and detects that the digital signal is in the clip state or the near-clip state based on the held signal.
16. The class D amplifier according to claim 8, wherein
the input signal is an analog or a digital signal.
17. The class D amplifier according to claim 8, wherein
the amplifier includes a first input terminal portion which supplies a positive phase signal and a second input terminal portion which supplies a negative phase signal, and
the transistor is inserted between the first input terminal portion and the second input terminal portion.
18. The class D amplifier according to claim 8, wherein
the attenuator attenuates the input signal by intermittently turning the input signal to 0V at predetermined time intervals according to the attenuation command signal.
19. The class D amplifier according to claim 8, wherein
the clip prevention controller is connected to a predetermined node in the amplifier to receive a signal from the predetermined node in the amplifier.
20. The class D amplifier according to claim 19, wherein
the clip prevention controller outputs the attenuation command signal according to the signal received from the predetermined node in the amplifier.
21. The class D amplifier according to claim 19, wherein
the amplifier includes a pulse-width modulator having the predetermined node.
22. The class D amplifier according to claim 19, wherein
the amplifier includes an error integrator that integrates errors between the input signal and the digital signal and outputs an error signal indicative of the integrated errors, and
the predetermined node is an output terminal of the error integrator. Description
This application is a continuation of U.S. patent application Ser. No. 11/541,999, now U.S. Pat. No. 7,482,870, filed Sep. 28, 2006, which in turn claims priority from Japanese Patent Application No. 2006-226272 filed on Aug. 23, 2006, Japanese Patent Application No. 2006-226269 filed on Aug. 23, 2006, and Japanese Patent Application No. 2005-282128 filed on Sep. 28, 2005, all of which are incorporated herein by reference.
The class D amplifier is an amplifier that generates a pulse train with its pulse width or time density modulated according to an input signal and drives a load by way of the pulse train. The class D amplifier is often used as a power amplifier for driving a speaker in an audio system. In this type of power amplifier, clip occurs in an output signal waveform in case the level of an input signal exceeds a proper range. Such clip must be prevented because, once given to speakers as a load, it is output from the speakers as an unpleasant sound. In the related art technology, a level adjuster has been arranged before a power amplifier in order to optimize the amplitude of an input signal to the power amplifier thus preventing occurrence of clip. This technology is disclosed as “related art technology” for example in JP-A-2003-332867.
According to the technology disclosed in JP-B-3,130,919, variable gain amplification means is provided in the preceding stage of the PWM (Pulse Width Modulation) modulator of a class D amplifier. In case an input signal that is likely to generate clip is given to a PWM modulator, the source voltage of a switching amplification stage arranged after the PWM modulator is switched to a high voltage and the gain of the variable gain amplification means before the PWM modulator is decreased to prevent clip. The problem with the technology disclosed in Patent Reference 1 is that means for controlling the switching amplification stage is required to prevent clip thus resulting in a larger circuit. The technology disclosed in Patent Reference 1 switches the source voltage of the switching amplification stage to a high voltage when clip is likely to occur. Thus, the peak level of the output signal of a class D amplifier may become unnecessarily high. This does not fully satisfy the needs for audio reproduction at an appropriate sound volume and with reduced distortion.
In order to solve the above objects, the present invention is characterized by having the following arrangements.
an amplifier that generates a digital signal for driving a load based on an input signal; an attenuator that attenuates the input signal according to an attenuation command signal; and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state. (2) The class D amplifier according to (1), wherein
the amplifier outputs the digital signal having a pulse width corresponding to the input signal according to a periodic synchronization signal, and the clip prevention controller outputs the attenuation command signal according to the synchronization signal. (3) The class D amplifier according to (2), further comprising a triangular wave generator for outputting a periodic triangular wave signal as the synchronization signal,
wherein the amplifier includes an error integrator for integrating and outputting errors between the input signal and the digital signal, and a pulse-width modulator for outputting a digital signal pulse-width-modulated according to a level of the output signal from the error integrator based on a comparison between the output signal from the error integrator and the triangular wave signal, and wherein the clip prevention controller assumes that the digital signal is in the clip state or near-clip state when the output signal from the error integrator exceeds a reference level and outputs the attenuation command signal. (4) The class D amplifier according to (3), wherein the clip prevention controller includes a comparison voltage generator for generating a comparison voltage at a level where the comparison voltage crosses the triangular wave signal when the output signal from the error integrator exceeds the reference level, and a comparator for comparing the comparison voltage with the triangular wave signal to output the attenuation command signal.
(5) The class D amplifier according to (3), wherein the clip prevention controller detects that the digital signal is in the clip state or near-clip state based on the level of the digital signal at a timing of a peak of the triangular wave signal or at an immediately previous timing of the peak.
(6) The class D amplifier according to (3), wherein the clip prevention controller holds a signal showing the result of comparison between the output signal from the error integrator in the pulse-width modulator and the triangular wave signal at a timing of a peak of the triangular wave signal or at an immediately after timing of the peak and detects that the digital signal is in the clip state or near-clip state based on the held signal.
(7) The class D amplifier according to any one of (1) through (6), wherein the input signal is an analog signal.
(8) The class D amplifier according to any one of (1) through (6), wherein the input signal is a digital signal.
(9) A class D amplifier comprising:
an amplifier that generates a digital signal for driving a load based on an input signal; and a gain controller that decreases a gain of the amplifier according to an increase in a level of the input signal so that a peak level of a waveform of the digital signal maintains a predetermined level when the digital signal is brought into a clip state or a near-clip state. (10) The class D amplifier according to (9), wherein the gain controller includes:
an attenuator that attenuates the input signal according to an attenuation command signal, the attenuator being provided at an input part of the amplifier; and a clip prevention controller that detects that the digital signal is brought into the clip state or near-clip state by monitoring a signal of a predetermined node in the amplifier and outputs the attenuation command signal. (11) The class D amplifier according to (10), wherein
the amplifier outputs a digital signal having a pulse width corresponding to the input signal according to a periodic synchronization signal, and the clip prevention controller outputs the attenuation command signal according to the synchronization signal. (12) The class D amplifier according to (11), further comprising a triangular wave generator that outputs a periodic triangular wave signal as the synchronization signal,
wherein the amplifier includes an error integrator for integrating and outputting errors between the input analog signal and the digital signal and a pulse-width modulator for outputting a digital signal pulse-width-modulated according to a level of an output signal from the error integrator based on a comparison between the output signal from the error integrator and the triangular wave signal, and wherein clip prevention controller assumes that the digital signal is in the clip state or near-clip state when the output signal from the error integrator exceeds a reference level and outputs the attenuation command signal. (13) The class D amplifier according to (12), wherein the clip prevention controller includes a comparison voltage generator for generating a comparison voltage at a level where the comparison voltage crosses said triangular wave signal when the output signal from the error integrator exceeds a reference level, and a comparator for comparing the comparison voltage with the triangular wave signal to output the attenuation command signal.
(14) The class D amplifier according to (12), wherein the clip prevention controller detects that the digital signal is in the clip state or near-clip state based on the level of the digital signal at a timing of a peak of the triangular wave signal or at an immediately previous timing of the peak.
(15) The class D amplifier according to (12), wherein the clip prevention controller holds a signal showing the result of comparison between the output signal from the error integrator in the pulse-width modulator and the triangular wave signal at a timing of a peak of the triangular wave signal or at an immediately after timing of the peak and detects that the digital signal is in the clip state or near-clip state based on the held signal.
(16) The class D amplifier according to (9), wherein
the amplifier includes a pulse generator for outputting as the digital signal a pulse having a pulse width or pulse density modulated by a modulating signal, the gain controller forms a part of the amplifier and includes a dynamic range compressor for performing dynamic range compression on a compression target signal given from a preceding stage to output as the modulating signal the resulting signal to the pulse generator, the dynamic range compressor amplifies the compression target signal with a predetermined gain in a linear region where the peak level of the compression target signal is lower than a predetermined threshold, and decreases the gain according to an increase in the peak level of the compression target signal so that the peak level of the modulating signal output to the pulse generator maintains the predetermined level in a saturation region where the peak level of the compression target signal exceeds the predetermined threshold. (17) The class D amplifier according to (16), wherein
the gain controller includes variable gain amplifier arranged in a preceding stage of the dynamic range compressor, and the variable gain amplifier amplifies the input signal with a gain corresponding to a sound volume adjustment signal provided from outside and outputs the resulting signal as the compression target signal to the dynamic range compressor. (18) The class D amplifier according to any one of (9) through (17), wherein the input signal is an analog signal.
(19) The class D amplifier according to any one of (9) through (17), wherein the input signal is a digital signal.
According to this invention, an attenuation command signal is generated to intermittently attenuate the input analog signal when the digital signal is brought into the clip or near-clip state. As a result, the input analog signal to the amplifier part is intermittently thinned on a time axis thus preventing clip on the digital signal. In this case, the input analog signal is intermittently thinned although its waveform is substantially unchanged. This prevents clip without generating waveform distortion.
FIG. 1 is a circuit diagram showing the configuration of a class D amplifier according to the first embodiment of the invention. The class D amplifier roughly includes an amplifier part 100, a clip prevention controller 200, and a triangular wave generator 300. The triangular wave generator 300 is a circuit that generates a triangular wave signal TR of a constant cycle changing in the shape formed by a linear slope within the voltage range of 0V to +VB and supplies the triangular wave signal TR to the amplifier part 100 and the clip prevention controller 200. The amplifier part 100 is a device for generating a digital signal to drive a load based on an input analog signal. Specifically, the amplifier part 100 is a circuit for generating a positive phase digital signal VOp and a negative phase digital signal VOn which are pulse-width-modulated according to the levels of the positive phase analog input signal VIp and the negative phase analog input signal VIn supplied to input terminals 101 p and 101 n and outputting the digital signals from output terminals 102 p and 102 n. The clip prevention controller 200 is a circuit for monitoring a signal to be fetched from a predetermined node in the amplifier part 100. When the level of the signal has deviated from a predetermined range, the clip prevention controller 200 assumes that the output signal VOp or VOn is in the clip or near-clip state, and generates an attenuation command signal SW to command intermittent attenuation of an input analog signal and supplies the attenuation command signal SW to amplifier part 100. The triangular wave signal TR is used as a synchronization signal to determine the generation timing of the digitals signals VOp and VOn and the generation timing of the attenuation command signal SW in the amplifier part 100 and the clip prevention controller 200. The configuration of the amplifier part 100 and the clip prevention controller 200 will be described in this order.
In the amplifier part 100, resistors R1, R3, R5 are serially inserted between the input terminal 101 p and the output terminal 102 n. Resistors R2, R4, R6 are serially inserted between the input terminal 101 n and the output terminal 102 p. The common connection point of the resistors R3 and R5 is connected to the positive phase input terminal 111 p of an error integrator 110. The common connection point of the resistors R4 and R6 is connected to the negative phase input terminal 111 n of the error integrator 110. A switch 130 using a MOSFET (field effect transistor composed of a Metal-Oxide Semiconductor) is inserted between the common connection point of the resistors R1 and R3 and the common connection point of the resistors R2 and R4. The switch 130 functions as an attenuator for intermittently attenuating an input analog signal according to the attenuation command signal SW supplied from the clip prevention controller 200. The switch 130 and the clip prevention controller 200 serve as a gain controller for decreasing the entire gain of the amplifier part 100 according to an increase in the level of each of the input signal VIp and VIn so that the peak level of the waveform shown by the digital signal VOp or VOn will maintain a certain level when the digital signal VOp or VOn is brought into a clip or a near-clip state.
In the error integrator 110, the positive phase input analog signal VIp is supplied to the positive phase input terminal 111 p via the resistors R1 and R3, and the negative phase input analog signal VIn is supplied to the negative phase input terminal 111 n via the resistors R2 and R4. A negative phase digital signal VOn is fed back to the positive phase input terminal 111 p of the error integrator 110. A positive phase digital signal VOp is fed back to the negative phase input terminal 111 n of the error integrator 110. The error integrator 110 is a circuit for integrating the errors between thus supplied input analog signals VIp and VIn and the digital signals VOp and VOn and outputting a positive phase signal VDp and a negative phase signal VDn respectively from the positive phase output terminal 112 p and the negative output terminal 112 n. Various types of error integrator 110 are available. The illustrated example uses a second-order error integrator 110 including a differential amplifier 113, four capacitors C1 to C4 and two resistors R11 and R12. The positive phase input terminal (plus input terminal) and the negative phase input terminal (minus input terminal) of the differential amplifier 113 serve as the positive phase input terminal 111 p and the negative phase input terminal 111 n of the error integrator 110, respectively. The positive phase output terminal (plus output terminal) and the negative phase output terminal (minus output terminal) of the differential amplifier 113 serve as the positive phase output terminal 112 p and the negative phase output terminal 112 n of the error integrator 110, respectively. Capacitors C1 and C2 for integrating errors are serially inserted between the positive phase input terminal and the negative phase output terminal of the differential amplifier 113. The common connection point of these capacitors is grounded via a resistor R11. Capacitors C3 and C3 for integrating errors are serially inserted between the negative phase input terminal and the positive phase output terminal of the differential amplifier 113. The common connection point of these capacitors is grounded via a resistor R12.
The positive phase input terminal 121 p and the negative phase input terminal 121 n of a pulse-width modulator 120 are connected to the positive phase output terminal 112 p and the negative phase output terminal 112 n of the error integrator 110, respectively. A triangular wave signal TR output from the triangular wave generator 300 is supplied to the triangular wave input terminal of the pulse-width modulator 120. The positive phase output terminal 123 p and the negative phase output terminal 123 n of the pulse-width modulator 120 serve as the output terminals 102 p and 102 n of the amplifier part 100, respectively. The pulse-width modulator 120 is a circuit for generating a positive phase digital signal VOp and a negative phase digital signal VOn having pulse widths corresponding to the levels of the output signals VDp and VDn of the error integrator 110 by using the triangular wave signal TR supplied to the triangular wave input terminal 122 and outputting the digital signals from the positive output terminal 123 p and the negative output terminal 123 n. Various types of pulse-width modulator 120 are available. The illustrated example uses a pulse-width modulator including: comparators 124 p and 124 n whose positive phase input terminals receive the triangular wave signal TR and whose negative phase input terminals receive a positive output signal VDp and negative output signal VDn from the error integrator 110, respectively; inverters 125 p and 125 n for inverting the level of each of output signals VEp and VEn from the comparators 124 p and 124 n and outputting the resulting signals; a NAND gate 126 p to which the output signal VEn from the comparator 124 n and the output signal from the inverter 125 p are input; a NAND gate 126 n to which the output signal VEp from the comparator 124 p and the output signal from the inverter 125 n are input; and inverters 127 p and 127 n for inverting the level of each of the output signals from the NAND dates 126 p and 126 n and outputting the resulting signals as signals VOp and VOn from the positive phase output terminal 123 p and the negative phase output terminal 123 n. This is the end of the description of the configuration of the amplifier part 100.
Next, the configuration of the clip prevention controller 200 will be described. A current output comparator 201 is a circuit for comparing the level of each of the output signals VDp and VDn from the error integrator 110 with a reference level VLEV and outputting a constant current to a parallel circuit of a capacitor C21 and a resistor R21 in the case that at least one of the output signals VDp and VDn exceeds the reference level VLEV. The reference level VLEV is set to the peak voltage VB of the triangular wave signal TR or a voltage slightly lower than VB. In this example, typically in order not to cause digital output signals VOp and VOn to generate clip, the reference level VLEV is set to the upper peak voltage of the triangular wave signal TR or a voltage slightly lower than the upper peak voltage. The clip prevention controller 200 according to the embodiment compares the upper peak voltage of the output signal VDp (or VDn) with the reference level VLEV and generates an attenuation command signal SW for clip prevention based on the comparison results, so that the reference level VLEV is set as described above. The clip prevention controller 200 may compare the lower peak voltage of the output signal VDp (or VDn) with the reference level VLEV and generate an attenuation command signal SW for clip prevention based on the comparison results. In this case, the reference level VLEV is set to the lower peak voltage of the triangular wave signal TR or a voltage slightly higher than the lower peak voltage. The reference level VLEV may be set according to the variation range of the pulse width modulation factor of the output digital signals VOp and VOn. In case it is necessary to maximize the variation range of the pulse width modulation factor of the output digital signals VOp and VOn, the reference level VLEV must be set as close as possible to VB or 0V. Otherwise, the reference level VLEV may be set apart from VB or 0V. In order to effect the clip prevention feature, the reference level VLEV may be arbitrarily set within the range of VB/2<VLEV<VB or 0V<VLEV<VB.
FIG. 2 is a circuit diagram showing an exemplary configuration of the current output comparator 201. In FIG. 2, an N-channel FET 221 has its source grounded and its drain and gate connected to a constant current source 220. N-channel FETs 222 to 224 have their sources grounded and their gates given the same gate voltage as the N-channel FET 221. That is, the N-channel. FETs 221 to 224 constitute a current mirror. Drain currents proportional to the drain current flowing through the N-channel FET 221 flow through the N-channel FETs 222 to 224.
Referring to FIG. 1, a portion from the current output comparator 201 to the preceding stage of the comparators 204 and 205 constitutes a comparison voltage generator for generating a comparison voltage having a level at which the output signal of the error integrator 110 crosses the triangular wave signal TR when the output signal has exceeded the reference level LEV. To be more precise, the parallel circuit comprising the capacitor C21 and the resistor R21 constitutes an integrator 21 for integrating the currents output from the current output comparator 201. An operational amplifier 202 constitutes a voltage follower buffer whose output terminal and negative phase input terminal are shorted and that transmits as a first comparison voltage the output voltage VC1 from the integrator 21 to the subsequent stage. The first comparison voltage VC1 output from the voltage follower buffer is supplied to the negative phase input terminal of the operational amplifier 203 via a resistor R22. A resistor 23 having the same resistance value as the resistor 22 is inserted between the negative phase input terminal and the output terminal of the operational amplifier 203. A reference level +VB/2 is supplied to the positive phase input terminal of the operational amplifier 203. Assuming that the output voltage of the operational amplifier 203 is VC2, the following equation is obtained:
(VC1+VC2)/2=VB/2 (1)
Solving the equation in terms of VC2 obtains:
VC2=VB−VC1 (2)
Next, operation of this embodiment will be described. FIG. 3 is a waveform chart showing the waveform of each part of the amplifier 100. The error integrator 110 integrates the errors between the input analog signals and output analog signals of the amplifier 100. Thus, the waveforms of the output signals VDp and VDn are like those of the input analog signals VIp and VIn with ripples corresponding to the output digital signals superimposed thereon. The pulse-width modulator 120 compares the output signals VDp and VDn from the error integrator 110 with the triangular wave signal TR. In the period when VDp>VDn, as shown in the left half of FIG. 3, the digital signal VOp is kept High in a period from when the level of the triangular wave signal TR exceeds the level of the signal VDn to when the level of the triangular wave signal TR reaches the level of the signal VDp and in a period from when the level of the triangular wave signal TR lowers the level of the signal VDn to when the level of the triangular wave signal TR drops to the level of the signal VDn and the digital signal VOn is kept Low continuously. In the period when VDn>VDp, as shown in the right half of FIG. 3, the digital signal VOn is kept High in a period from when the level of the triangular wave signal TR exceeds the level of the signal VDp to when the level of the triangular wave signal TR reaches the level of the signal VDn and in a period from when the level of the triangular wave signal TR lowers the level of the signal VDn to when the level of the triangular wave signal TR drops to the level of the signal VDp and the digital signal VOp is kept Low continuously. In this way, the pulse-width modulator 120 generates digital signals VOp and VOn having a pulse width proportional to the level difference between the positive and negative phase output signal VDp and VDn from the error integrator 110.
In this embodiment, the triangular wave signal TR changes within a range between 0V and +VB. In order to obtain as pulse trains the output signals VOp and VOn without generating clip, both output signals VDp and VDn from the error integrator 110 must be within the range at which terminals that output signals cross the triangular wave signal TR. In case the amplitudes of the input analog signal VIp and VIn are within a proper range, the output signals VDp and VDn from the error integrator 110 fall within the range of the amplitude of the triangular wave signal TR. In case the input analog signals VIp and VIn whose amplitudes substantially deviate from the proper range are supplied to the class D amplifier, the output signal VDp or VDn from the error integrator 110 deviates from the range of the amplitude of the triangular wave signal TR thus causing a clip state where the output digital signal VOp or VOn is continuously kept High. Note that, in this embodiment, the clip is prevented by the clip prevention controller 200. This operation will be described referring to FIGS. 4A and 4B. Incidentally, the proper range of the amplitudes of the input analog signal VIp and VIn is a range within which a clip does not occur at the output digital signals VOp and Von, and is a range smaller than a value which is obtained by dividing the half of the power voltage of the output portion (for example, the inverters 127 p and 127 n of FIG. 1) of the class D amplifier by the gain of the class D amplifier.
As shown in FIG. 4A, in case the amplitude of each of the input analog signals VIp and VIn is within the proper range and the maximum value of each of the output signals VDp and VDn is below the reference level VLEV, the output current from the current output comparator 201 is 0, the first comparison voltage VC1 is 0V, and the second comparison voltage VC2 is +VB. Thus, the triangular wave signal TR dose not cross the comparison voltages VC1 and VC2 and the attenuation command signal SW is continuously set Low as an inactive level. Thus, the switch 130 is kept OFF. The waveforms of the analog signals VIp′ and VIn′ at the terminals of the switch 130 are similar to those of the input analog signals VIp and VIn as shown in FIG. 4A.
As shown in FIG. 4B, in case the amplitude of each of the input analog signals VIp and VIn increases and at least one of the output signals VDp and VDn from the error integrator 110 exceeds the reference level VLEV, a constant current is output from the current output comparator 201 while the signal VDp or VDn exceeds the reference level VLEV. The constant current recharges the capacitor C21. Output of the constant current and recharging of the capacitor C21 by the current output comparator 201 are made each time the signal VDp or VDn exceeds the reference level. As a result, the first comparison voltage VC1 changes in a pulsating manner as described below. The first comparison voltage VC1 rises when the signal VDp or VDn has exceeded the reference level. Afterwards, the first comparison voltage VC1 drops as the stored electric charges are discharged via the resistor R21 until the signal VDp or VDn exceeds the reference level the next time. As the first comparison voltage VC1 shows such a behavior, the second comparison voltage VC2 (=VB−VC1) drops from the voltage VB and repeats the same pulsation as the voltage VC1. As a result, the triangular wave signal TR crosses the comparison voltages VC1 and VC2. The attenuation command signal SW that is set High in a period when the triangular wave signal TR is lower than the voltage VC1 and a period when the triangular wave signal TR is higher than the voltage VC2 is output from the Low-active OR gate 206.
The switch 130 is turned OFF while the attenuation command signal SW is Low and turned ON while the attenuation command signal SW is High. In a period when the attenuation command signal SW is Low, the analog signals VIp′ and VIn′ at the terminals of the switch 130 shows signal values corresponding to the original input analog signals VIp and VIn. In a period when the attenuation command signal SW is High, the analog signals VIp′ and VIn′ are 0V. The analog signals VIp′ and VIn′ show waveforms thinned at predetermined time intervals as illustrated. An analog signal substantially input to the error integrator 110 is attenuated and the level of the output signal from the error integrator 110 falls within the proper range of 0V to +VB, thereby preventing clip on the output digital signals VOp and VOn.
Specifically, in the situation where the amplitudes of the input analog signals VIp and Vin are large and such thinning is made, as the amplitudes of the input analog signals VIp and Vin become larger and the amplitude of the output signals VDp and VDn of the error integrator 110 become larger accordingly, thinning ratio is increased and the gain of the entire class D amplifier is decreased, that is, a so-called negative feedback control is made. As a result of such a negative feedback control, the input analog signals VIp and VIn are amplified without generating distortion. When the input analog signals VIp and VIn each has reached a peak level, the gain of the entire class D amplifier is adjusted to an optimum value so that the pulse width modulation factor of the output digital signal VOp or VOn will reach a certain upper limit value. Thus, in this embodiment, in a region where the amplitudes of the input analog signals VIp and Vin are larger than the proper range, an output signal waveform (an waveform obtained by integrating the output digital signals VOp and VOn) given to a load is not distorted and the peak level of the output signal waveform maintains a certain value even in case the amplitudes of the input analog signals VIp and Vin have increased.
In this embodiment, as mentioned above, the negative feedback control is made by thinning in a region where the amplitude of an input analog signal is larger than the proper range. Ideally, it is thus possible to amplify the input analog signals VIp and VIn s as not to clip the output signal waveform even in case the amplitudes of the input analog signal VIp and VIn have reached the infinity. In reality, an input protection circuit is provided in case a class D amplifier is implemented as a semiconductor integrated circuit. In case the amplitudes of the input analog signal VIp and VIn exceeds the source voltage range, the input analog signals VIp and VIn are clipped when these signals passes through the input protection circuit. In this case, the class D amplifier amplifies the clipped input analog signals VIp and VIn. In the meantime the class D amplifier performs amplification through thinning-based negative feedback control so that the class D amplifier gives no additional distortion to the input analog signals VIp and VIn.
In this embodiment, the triangular wave generator 300 in the first embodiment is replaced with a triangular wave generator 300A for outputting positive phase and negative phase triangular wave signals TRp and TRn. Accordingly, the pulse-width modulator 120 in the first embodiment is replaced with a pulse-width modulator 120A for performing pulse-width modulation by using positive phase and negative phase triangular wave signals TRp and TRn. In the pulse-width modulator 120A, a comparator 141 p outputs a High signal when the instantaneous value of the triangular wave signal TRp is lower than that of the output signal VDp of the error integrator 110. A comparator 142 p outputs a High signal when the instantaneous value of the triangular wave signal TRp is higher than that of the output signal VDn of the error integrator 110. In a period when the output signals of the comparators 141 p and 142 p are set High, that is, VDp>VDn, an AND gate 143 p maintains the digital signal VOp High in a period from when the instantaneous value of the triangular wave signal TRp exceeds the signal VDn to when it reaches the signal VDp, and in a period when the instantaneous value of the triangular wave signal TRp drops below the signal VDp to when it reaches the signal VDn. The comparator 141 n outputs a High signal when the instantaneous value of the triangular wave signal TRn is lower than that of the output signal VDn of the error integrator 110. The comparator 142 n outputs a High signal when the instantaneous value of the triangular wave signal TRn is higher than that of the output signal VDn of the error integrator 110. In a period when the output signals of the comparators 141 n and 142 n are set High, that is, VDn>VDp, an AND gate 143 n maintains the digital signal VOn High in a period from when the instantaneous value of the triangular wave signal TRn exceeds the signal VDp to when it reaches the signal VDn, and in a period when the instantaneous value of the triangular wave signal TRn drops below the signal VDn to when it reaches the signal VDp. That is, in the pulse-width modulator 120A, same as the pulse-width modulator 120 in the first embodiment, digital signals VOp and VOn each having a pulse width proportional to the level difference between the positive phase and negative phase output signals VDp and VDn of the error integrator 110.
FIG. 6 is a block diagram showing the configuration of a class D amplifier according to the third embodiment of the invention. In this embodiment, the clip prevention controller 200 in the first embodiment is replaced with a clip prevention controller 200B. In this embodiment, a pulse-shaped timing signal S is supplied to the clip prevention controller 200B from the triangular wave generator 300 with the timing the triangular wave signal TR is at the positive peak and the timing the triangular wave signal TR is at the negative peak.
FIG. 9 is a waveform chart showing the operation of this embodiment. In the pulse-width modulator 120A, the output signal VEpb of the comparator 142 p is set High in a period when the triangular wave signal TRp exceeds the level of the signal VDn. The output signal VEpa of the comparator 141 p is set Low in a period when the triangular wave signal TRp exceeds the level of the signal VDp. In the pulse-width modulator 120A, the output signal VEnb of the comparator 142 n is set High in a period when the triangular wave signal TRn exceeds the level of the signal VDp. The output signal VEna of the comparator 141 n is set Low in a period when the triangular wave signal TRp exceeds the level of the signal VDn.
Thus, in case the levels of the output signals VDp and VDn of the error integrator 110 are within a proper range and VDp>VDn, the AND gate 143 p maintains the digital signal VOp High in a period from when the triangular wave signal TRp exceeds the signal VDn to when it reaches the signal VDp and in a period when the triangular wave signal TRp drops below the signal VDp to when it reaches the signal VDn in the pulse-width modulator 120A. In case the levels of the output signals VDp and VDn of the error integrator 110 are within a proper range and VDn>VDp, the AND gate 143 n maintains the digital signal VOn High in a period from when the triangular wave signal TRn exceeds the signal VDp to when it reaches the signal VDn and in a period from when the triangular wave signal TRn drops below the signal VDn to when it reaches the signal VDp in the pulse-width modulator 120A.
As shown in the left part of FIG. 9, when the level of the output signal VDp of the error integrator 110 reaches the level VDp′ close to the positive peak of the triangular wave signal TRp, the signal VEpa has its pulse width narrowed as shown by the signal VEpa′ in the figure. When the amplifier 100 is in the clip or near-clip state and the signal VEpa is set High on the rising edge of the clock CK, a High signal is output from the flip-flop 263. The switch 262 is turned ON and the charging voltage VC of the capacitor C21 rises as illustrated, and the pulse-shaped attenuation command signal SW is output, thus preventing occurrence of clip.
As shown in the right part of FIG. 9, when the level of the output signal VDn of the error integrator 110 reaches the level VDn′ close to the positive peak of the triangular wave signal TRn, the signal VEna has its pulse width narrowed as shown by the signal VEna′ in the figure. When the amplifier 100 is in the clip or near-clip state and the signal VEna is set High on the falling edge of the clock CK, a High signal is output from the flip-flop 264. The switch 262 is turned ON and the charging voltage VC of the capacitor C21 rises as illustrated, and the pulse-shaped attenuation command signal SW is output, thus preventing occurrence of clip.
This embodiment obtains the same working effect as each of the preceding embodiments. The fourth embodiment may have the following variant. That is, the rising timing and falling timing of the clock CK supplied to the flip-flops 263 and 264 are slightly delayed with respect to a peak of the triangular wave signal TRp or TRn. With this approach, the attenuation command signal SW is generated just before occurrence of clip, or in other words, when the pulse width of the negative pulses as signals VEn and VEp synchronous with the peak timing of the triangular wave signals TRp and TRn has become extremely narrow. This previously avoids occurrence of clip. In this case also, as a result of the negative feedback similar to that in the foregoing embodiments, the input analog signals VIp and VIn are amplified without being distorted. When the input analog signals VIp and VIn each has reached a peak level, the gain of the entire class D amplifier is adjusted to an optimum value so that the pulse width modulation factor of the output digital signal VOp or VOn will reach a certain upper limit value (just before occurrence of clip) slightly lower than 100 percent.
FIG. 10 is a circuit diagram showing the configuration of a class D amplifier according to the fifth embodiment of the invention. FIG. 11 is a waveform chart showing the operation of the fifth embodiment. In the foregoing embodiments, positive phase and negative phase input analog signals VIp and VIn are given to a class D amplifier. In this embodiment, as shown in FIG. 11, positive phase and negative phase bit streams each being a single-bit digital signal are given as input signals VIp and VIn to a class D amplifier. In this embodiment, as shown in FIG. 10, in order to appropriately process the bit streams VIp and VIn, a synchronization circuit 310 for synchronizing the phase of a triangular wave signal TR output from the triangular wave signal generator 300 with the bit streams VIp and VIn is added to the class D amplifier of the first embodiment.
In this embodiment, in case the input signals is a bit stream, the error integrator 110 integrates the errors between the output signals VOp and VOn and the input signals VIp and VIn and the pulse-width modulator 120 generates pulse-width-modulated digital signals VOp and VOn based on the signals VDp and VDn indicating the integration result in a similar fashion as the first embodiment. In this embodiment, it is possible to apply, to a load (not shown), a signal having the same waveform as the analog signal waveform of the bit streams VIp and VIn. In the situation that the peak of the signal waveform of the bit streams VIp and VIn rises and clip is likely to occur, the first comparison voltage VC1 and the second comparison voltage VC2 repeat pulsation and the attenuation command signal SW is intermittently generated, same as the first embodiment. In this way, the input signals VIp′ and VIn′ given to the error integrator 110 becomes signals in which the input signals VIp′ and VIn′ are thinned by bit streams VIp and VIn, thus occurrence of clip is prevented. While the class D amplifier of the first embodiment has been modified to provide a class D amplifier of this embodiment, the class D amplifier of any other embodiment may be similarly modified to provide a class D amplifier of this embodiment.
In the variable gain amplification processing 401, an input signal is amplified with a variable gain and the resulting signal is passed to the DRC processing 402. The gain in the variable gain amplification processing 401 is set according to a sound volume adjustment signal generated depending on the operation of an operator such as a volume control. The compression target signal obtained by the variable gain amplification processing 401 is an m-bit digital signal and a value that can be represented by this signal has an upper limit. To obtain a distortion-free compression target signal from an input signal in the variable gain amplification processing 401, there must be an appropriate relationship between the peak level of the input signal and the gain used when amplifying the input signal so that the result of amplification of the input signal will not exceed a maximum value represented by an m-bit digital signal, for example an instantaneous value represented by a digital signal with m bits all “1”. In case the peak level of an input signal falls with a proper range appropriate for amplification using a gain set according to a sound volume adjustment signal, the input signal is amplified without being distorted and a compression target signal having a similar waveform to that of the input signal is obtained (in the illustrated example, compression target signals B1 to B4 corresponding to input signals A1 to A4). In case the peak level of an input signal exceeds the proper range, the compression target signal obtained by the variable gain amplification processing 401 will be saturated at the maximum value that can be represented by the m-bit digital signal and accordingly clipped (in the illustrated example, compression target signals B5 and B6 corresponding to input signals A5 and A6).
FIG. 13 shows an input/output characteristic as a relationship between the peak level of a compression target signal given to the DRC processing 402 and the peak level of a modulating signal obtained by the DRC processing 402. As illustrated, the input/output characteristic of the DRC processing 402 is divided into a linear region and a saturation region. The linear region is a region below a threshold th at the peak level of the compression target signal. In the linear region, the compression target signal is amplified with a predetermined gain to generate a modulating signal having a peak level proportional to that of the compression target signal (in the illustrated example, modulating signals C1 and C2 corresponding to compression target signals B1 and B2). In this embodiment, the gain in the linear region is determined so that a modulation signal having a peak level indicating a modulation factor of 100 percent may be obtained when a compression target signal having a peak level corresponding to the threshold th is given. The saturation region is a region where the peak level of a compression target signal is equal to or above the threshold th. In the saturation region, the peak level of a modulating signal has reached a value indicating a modulation factor of 100 percent. In the DRC processing 402, the gain used when amplifying a compression target signal is decreased according to an increase in the peak level of the compression target signal so that the peak level of the modulating signal obtained by amplifying the compression target signal maintains the value indicating a modulation factor of 100 percent (in the illustrated example, modulating signals C3 to C6 corresponding to compression target signals B3 to B6). To be more precise, a value obtained by dividing the value of a modulating signal indicating a modulation factor of 100 percent by the peak level of the compression target signal is used as a gain used when amplifying a compression target signal.
(3) While in the first embodiment the source voltage of the current output comparator 201 is +VB (refer to FIG. 2) and the reference level +VB/2 is given to the positive phase input terminal of the operational amplifier 203 (refer to FIG. 1). For the class D amplifier according to the first embodiment, at least the center potential of the triangular wave signal TR must be equal to a potential given to the positive phase input terminal of the operational amplifier 203. The source voltage of the current output comparator 201 and the potential given to the positive phase input terminal may respectively have arbitrary values.
(4) While single-channel positive phase and negative phase bit streams are given to the input terminals 101 p and 101 n in the fifth embodiment, a multi-channel positive phase bit stream may be given to the input terminal 101 p and a multi-channel negative phase bit stream may be given to the input terminal 101 n. It is thus possible to provide a class D amplifier equipped with a mixing feature. In this case, a configuration is possible where variable resistors corresponding to the multiple channels are arranged before the input terminals 101 p and 101 n and the bit stream on each channel is given to the input terminal 101 p or 101 n via the variable resistor corresponding to the particular channel, and weighting on each channel is made in mixing through adjustment of the resistance value of each variable resistor.
(5) While single-bit positive phase and negative phase bit streams are given to the input terminals 101 p and 101 n in the fifth embodiment, a multi-bit positive phase bit stream may be given to the input terminal 101 p and a multi-bit negative phase bit stream may be given to the input terminal 101 n. In this case, a configuration is possible where weighted resistors corresponding to the multiple bits are arranged before the input terminals 101 p and 101 n and the bit stream for each bit is given to the input terminal 101 p or 101 n via the corresponding weighted resistor.
(6) Control of the degree of thinning using the switch 130 at the input part of a class D amplifier may be made in any form. While in the above embodiments negative feedback control is made where the amplitudes of the input analog signals VIp and VIn become larger and the level of the output signal of the error integrator increases, the thinning ratio is increased, control of the thinning ratio may be made in a form other than negative feedback control. For example, a form is possible where thinning ratios are previously determined to avoid clip on the input signals VIp and VIn at various peak levels, and the peak level of each of the input signals VIp and VIn is detected in operation of a class D amplifier and an appropriate thinning ratio is selected to avoid clip at that particular level in order to thin the input signals VIp and VIn. In an operation region where the input analog signals VIp and VIn are thinned, the upper limit value of the pulse-width modulation factor of each of the output digital signals VOp and VOn need to be maintained at a certain value in case the input analog signals VIp and VIn have increased. For example, the upper limit value of the pulse-width modulation factor may be slightly decreased according to the increase in the amplitude of each of the input analog signals VIp and VIn.
(8) While the variable gain amplification processing 401, the DRC processing 402 and the PWM processing 403 are executed by the DSP 400 in the sixth embodiment, a digital circuit or an analog circuit for respectively executing the variable gain amplification processing 401, the DRC processing and the PWM processing 403 may be arranged before the switching amplification stage 410 instead of arranging the DSP 400.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3620631 *Aug 26, 1969Nov 16, 1971Collins Radio CoGain-controlled amplifierUS4173739Sep 18, 1978Nov 6, 1979Sony CorporationOverload detecting circuit for a PWM amplifierUS4376267 *Nov 24, 1980Mar 8, 1983Martin Martietta CorporationVideo preamplifier for laser systemsUS4600891Aug 21, 1984Jul 15, 1986Peavey Electronics CorporationDigital audio amplifier having a high power output level and low distortionUS4724396Jun 13, 1986Feb 9, 1988Peavey Electronics CorporationDigital audio amplifierUS5767740Sep 27, 1996Jun 16, 1998Harris CorporationSwitching amplifier closed loop dual comparator modulation techniqueUS6118336Oct 30, 1998Sep 12, 2000Intersil CorporationStart-up circuit for self oscillating class D modulatorUS6122331 *Jun 14, 1999Sep 19, 2000Atmel CorporationDigital automatic gain controlUS7167046 *Nov 24, 2004Jan 23, 2007Yamaha CorporationClass-D amplifierUS7183840Oct 18, 2004Feb 27, 2007Yamaha CorporationClass-D amplifierUS7579910 *Jan 2, 2008Aug 25, 2009Pacifictech Microelectronics, Inc.Low distortion switching amplifier circuits and methodsUS7656202 *May 15, 2007Feb 2, 2010Asahi Kasei Emd CorporationDriving device and driving methodUS7728666 *Jul 8, 2008Jun 1, 2010Monolithic Power Systems, Inc.Close-loop class-D audio amplifier and control method thereofUS20040184621Mar 19, 2004Sep 23, 2004Andersen Jack B.Clip detection in PWM amplifierUSRE33333Mar 11, 1988Sep 11, 1990Peavey Electronics CorporationDigital audio amplifier having a high power output level and low distortionCN1179032ASep 26, 1997Apr 15, 1998哈里公司Switch amplifier closed loop double comparator modulating technologyEP1003280A2Nov 17, 1999May 24, 2000Intersil CorporationClass D amplifier with current limit circuit and load impedance sensing circuitJP2003332867A Title not availableJP2005123949A Title not availableJPH04172705A Title not availableJPH10256839A Title not availableJPS6011518A Title not available* Cited by examinerNon-Patent CitationsReference1Chinese Patent Office "Request for Invalidation of a Patent" of Patent No. ZL200610141503.6, dated Nov. 29, 2010, 23 pages.2European Patent Office, "European Search Report," dated Dec. 6, 2006.3Japan Patent Office "Notification of Reasons for Refusal" of Patent Application No. 2006-226272, dated Nov. 24, 2010, 2 pages.4Japanese Patent Office "Notification of Reasons for Refusal"�of Patent No. 2010-099207, dated Jul. 26, 2011, 2 pages.5Japanese Patent Office "Utility Model Publication SHO-60-11518" Date of Publication of Application: Jan. 26, 1995, Utility Model Application Serial No. SHO-58-103656, Applicant: Nippon Gakki Co., Ltd., 2 pages.6Japanese Patent Office, "Notification of Reasons for Refusal", Patent Application No. 2006-226269, Drafting Date: Mar. 18, 2010, six pages.7The State Intellectual Property Office of the People's Republic of China, "Notification of First Office Action" Chinese Patent Application No. 201010147558.4 dated Feb. 25, 2011, 7 pages.8The State Intellectual Property Office of the People's Republic of China, "Notification of First Office Action" Chinese Patent Application No. 201010147571.X dated Feb. 25, 2011, 7 pages.9The State Intellectual Property Office of the People's Republic of China, "Notification of First Office Action" Chinese Patent Application No. 201010147574.3 dated Feb. 25, 2011, 5 pages.10The State Intellectual Property Office of the People's Republic of China, "Observation for Reexamination or Invalidation of Patent" Chinese Patent No. ZL200610141503.6 dated Feb. 25, 2011, 21 pages.Classifications U.S. Classification330/207.00P, 330/298International ClassificationH03F21/00Cooperative ClassificationH03F2200/66, H03F3/217European ClassificationH03F3/217Legal EventsDateCodeEventDescriptionApr 22, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services