Source: http://www.google.com/patents/US7851872?dq=5960409
Timestamp: 2017-05-26 17:20:42
Document Index: 616084851

Matched Legal Cases: ['Application No. 050002849', 'Application No. 06011395', 'Application No. 06011396', 'Application No. 04', 'Application No. 05', 'Application No. 04', 'Application No. 200780025919', 'Application No. 06', 'Application No. 06', 'Application No. 2004']

Patent US7851872 - Efficient transistor structure - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn integrated circuit comprises a first source, a first drain, a second source, a first gate arranged between the first source and the first drain, and a second gate arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the drain....http://www.google.com/patents/US7851872?utm_source=gb-gplus-sharePatent US7851872 - Efficient transistor structureAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7851872 B2Publication typeGrantApplication numberUS 11/524,113Publication dateDec 14, 2010Filing dateSep 20, 2006Priority dateOct 22, 2003Fee statusPaidAlso published asUS7528444, US7652338, US7863657, US20070032063, US20070034903, US20070034904, US20070037353Publication number11524113, 524113, US 7851872 B2, US 7851872B2, US-B2-7851872, US7851872 B2, US7851872B2InventorsSehat SutardjaOriginal AssigneeMarvell World Trade Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (59), Non-Patent Citations (14), Referenced by (3), Classifications (35), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetEfficient transistor structure
US 7851872 B2Abstract
An integrated circuit comprises a first source, a first drain, a second source, a first gate arranged between the first source and the first drain, and a second gate arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the drain. The first and second gates are arranged farther apart in the first regions than in the second regions.
a second source;
a first gate arranged between said first source and said first drain;
a second gate arranged between said first drain and said second source,
wherein said first and second gates define alternating first and second regions in said drain, wherein said first and second gates are arranged farther apart in said first regions than in said second regions; and
a well substrate contact arranged in said first regions.
R well substrate contacts arranged in said first regions, where R is an integer greater than one.
3. The integrated circuit of claim 2 wherein R is an integer that is greater than three and less than seven.
4. The integrated circuit of claim 1 wherein said integrated circuit includes a plurality of transistors.
5. The integrated circuit of claim 4 wherein said transistors include PMOS transistors.
6. The integrated circuit of claim 2 herein said R well substrate contacts are associated with respective ones of R transistors.
wherein said first and second gates define alternating first and second regions in said drain, wherein said first and second gates are arranged farther apart in said first regions than in said second regions;
a third gate arranged between said second source and said second drain,
wherein said second and third gates define alternating third and fourth regions, said second and third gates are arranged farther apart in said third regions than in said fourth regions,
wherein said first regions are arranged adjacent to said fourth regions and said second regions are arranged adjacent to said third regions, and
wherein said first and third regions include R well substrate contacts and R is an integer greater than one.
8. A method for providing an integrated circuit comprising:
providing a first source;
providing a first drain;
providing a second source;
locating a first gate between said first source and said first drain;
locating a second gate between said first drain and said second source;
defining alternating first and second regions in said drain using said first and second gates;
arranging said first and second gates farther apart in said first regions than in said second regions; and
locating a well substrate contact in said first regions.
9. A method for providing an integrated circuit comprising:
locating R well substrate contacts in said first regions, where R is an integer greater than one.
10. The method of claim 9 wherein R is an integer that is greater than three and less than seven.
11. The method of claim 8 wherein said integrated circuit includes a plurality of transistors.
12. The method of claim 11 wherein said transistors include PMOS transistors.
13. The method of claim 9 further comprising associating said R well substrate contacts with respective ones of R transistors.
14. A method for providing an integrated circuit comprising:
arranging said first and second gates farther apart in said first regions than in said second regions;
providing a second drain;
providing a third gate between said second source and said second drain;
defining alternating third and fourth regions using said second and third gates;
arranging said second and third gates farther apart in said third regions than in said fourth regions; and
arranging said first regions adjacent to said fourth regions and said second regions adjacent to said third regions,
wherein said first and third regions include R well substrate contacts, where R is an integer greater than one. Description
This application claims the benefit of U.S. Provisional Application Nos. 60/825,517, filed Sep. 13, 2006, 60/824,357, filed Sep. 1, 2006, 60/823,332, filed on Aug. 23, 2006, 60/821,008, filed Aug. 1, 2006 and 60/798,568, filed on May 8, 2006 and is a continuation-in-part of U.S. patent application Ser. No. 11/252,010 filed on Oct. 17, 2005, which is a continuation of U.S. patent application Ser. No. 10/691,237 filed on Oct. 22, 2003. The disclosure of the above application is incorporated herein by reference in its entirety.
The present invention relates to transistor structures, and more particularly to transistor structures with reduced chip area.
Integrated circuits or chips may include a large number of interconnected transistors. The transistors and other circuit elements are interconnected in various ways to provide desired circuit functions. It is usually most efficient to fabricate multiple integrated circuits on a single wafer. After processing, the integrated circuits that are fabricated on the wafer are separated and then packaged. The wafer can accommodate a fixed number of integrated circuits for a given integrated circuit size. Reducing the size of individual transistors in the integrated circuit may help to reduce the overall size of the integrated circuit. This, in turn, allows an increased number of integrated circuits or chips to be made on each wafer and reduces the cost of the integrated circuits.
Referring now to FIG. 3, the body 18 includes a p+ region and may include a contact tap 30. The source 16 includes an n+ region and may include a contact tap 32. The drain 12 includes an n+ region and may include a contact tap 34. Additional transistors may be fabricated on one or sides of the transistor 10 as indicated by “ . . . ” in FIG. 3.
Referring now to FIG. 4, the body 18 may be repeated between sources 16 of adjacent transistors. The body 18 takes up valuable chip area and increases the size of the transistor and the integrated circuit. Additional transistors can be arranged on one or more sides of the transistor 10 as shown by “ . . . ” in FIG. 4.
The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify the same elements. Additional transistors can be arranged on one or more sides of the illustrated transistors that are shown in the FIGs. as indicated by “ . . . ” in the FIGs.
Each of the drain regions 306 may have an area that is greater than or equal to two times the area of each of the source regions 304. In FIG. 12A, the drain regions 306 have a width “b” and a height “a”. The source regions 304 have a width (or height) “d” and a height (or width) “c”. The drain regions 306 may have substantially the same length as the source regions 304. The drain regions 306 may have greater than or equal to two times the width of the source regions 304.
Substantially all of the current flowing between the drain region 306-3 and the source contacts 311-1, 311-2, . . . and 311-B of the adjacent source region 304-2 flows between a facing portion 335 of the drain contact 334-3 and facing halves 337-1, 337-2, . . . and 337-B of source contacts 311-1, 311-2, . . . and 311-B in the source region 304-2. Current flows in a similar manner between other facing portions of the drain contact 334-3 and source contacts (not shown) in other adjacent source regions 304-5, 304-6 and 304-7.
In some implementations, the substrate contacts 347-11, 347-12, 347-21, 347-22, 347-23, . . . may be arranged in some, none or all of the second areas 345-B1, 345-B2, 345-B3 and 345-B4 of the source regions 344-1, 344-2, . . . and 344-R, for example as shown in FIG. 12D. The substrate contacts 347-11, 347-12, 347-21, 347-22, 347-23, . . . are shown arranged in the elongated substrate regions 344-1 and 344-2 and tend to lower RDS — ON. The substrate contacts 347-11, 347-12, 347-21, 347-22, 347-23, . . . may have a height that is less than or equal to a width “c” of the source regions 304 (as shown in FIG. 12A) and a width that is less than or equal to a width “d” of the source regions 304 (as shown in FIG. 12A).
Referring now to FIG. 12E, substrate contacts 330-1 and 330-2 are provided between pairs of elongated source regions 344-1A and 344-1B and 344-2A and 344-2B, respectively. The elongated source regions 344-1A and 344-2A are driven from one side by drivers 346-1A and 346-2A. The elongated source regions 344-1B and 344-2B are driven from another side by drivers 346-1B and 346-2B.
Drain contacts 334 in FIGS. 12A-12E may have a minimum size or a size that is greater than the minimum size. Drain contacts 334 may have a simple or regular shape and/or an irregular or complex shape. For example, the drain contacts 334 may have a square or rectangular shape (as shown at 344 in FIG. 12A), a cross shape (as shown at 344-W in FIG. 12F), clover-leaf shapes (as shown at 334-X and 334-Y in FIGS. 12G and 12H, respectively), a modified cross-shaped region (as shown at 334-Z in FIG. 121) and/or other suitable shapes such as but not limited to diamond, circular, symmetric, non-symmetric, etc. The substrate contacts 347 may similarly have a simple or regular shape and/or an irregular or complex shape similar to the drain contacts 334.
Referring now to FIGS. 13-15, drain, source and gate regions can also have other shapes that can be used to minimize RDSON. For example, drain regions 348 can have a circular shape as shown in FIG. 13, an elliptical shape as shown in FIG. 14 and/or other suitable shapes. Gate regions 349 include circular-shaped gate regions 350 that are connected by linear gate connecting regions 352. Similar elements are identified in FIG. 14 using a prime symbol (“′”). The drain regions 348 are located in the circular-shaped gate regions 350. Source regions 360 are located in between the gate regions 349 in areas other than the inside of the circular shaped gate regions 350. Substrate contacts 364 are located in the source regions 360. The drain regions 348 may also include a contact region 366. The linear gate regions 352 may have a vertical spacing “g” that is minimized to increase density. Likewise, lateral spacing identified at “f” between adjacent circular-shaped gate regions 350 may be minimized to increase density.
Drain areas 368 can also have polygon shapes. For example, the drain areas can have a hexagon shape as shown in FIG. 15, although other polygon shapes can be used. Gate regions 369 include hexagon-shaped gate regions 370 that are connected by linear gate connecting regions 372. The drain regions 368 are located in the hexagon-shaped gate regions 370. Source regions 380 are located in between the gate regions 369 in areas other than the inside of the hexagon-shaped gate regions 370. Substrate contacts 384 are located in the source regions 380. The drain regions may also include a contact region 386. The linear gate connecting regions 372 preferably have a vertical spacing “j” that is minimized to increase density. Likewise lateral spacing identified at “i” between adjacent hexagon-shaped gate regions 370 is minimized to increase density.
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