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Patent US4293877 - Photo-sensor device and image scanning system employing the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA photo-sensor device comprises a light receiving part composed of a plurality of photo-sensor elements for converting photosignals into electrical signals. A portion of the light receiving part is shielded by light shielding means so that in reading out the output from the device, there can be obtained...http://www.google.com/patents/US4293877?utm_source=gb-gplus-sharePatent US4293877 - Photo-sensor device and image scanning system employing the sameAdvanced Patent SearchPublication numberUS4293877 APublication typeGrantApplication numberUS 06/025,542Publication dateOct 6, 1981Filing dateMar 30, 1979Priority dateMar 31, 1978Also published asDE2912884A1, DE2912884C2Publication number025542, 06025542, US 4293877 A, US 4293877A, US-A-4293877, US4293877 A, US4293877AInventorsTokuichi Tsunekawa, Makoto Masunaga, Kazuya Hosoe, Yukichi Niwa, Mitsutoshi Owada, Noriyuki AsanoOriginal AssigneeCanon Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (7), Non-Patent Citations (2), Referenced by (64), Classifications (16) External Links: USPTO, USPTO Assignment, EspacenetPhoto-sensor device and image scanning system employing the same
US 4293877 AAbstract
A photo-sensor device comprises a light receiving part composed of a plurality of photo-sensor elements for converting photosignals into electrical signals. A portion of the light receiving part is shielded by light shielding means so that in reading out the output from the device, there can be obtained also a signal of dark current information from the shielded photo-sensor elements.
1. A radiation sensing device comprising:(a) radiation sensing means having a plurality of radiation sensitive elements, each for providing an electrical signal corresponding to received radiation, said plurality of radiation sensitive elements in said radiation sensing means being arranged in array; (b) optically opaque means for shielding a portion of said radiation sensing means so that an electrical signal indicative of a dark current is provided by one or more radiation sensitive elements shielded by said opaque means, said optically opaque means shielding at least one radiation sensitive element located at or near the end of said array; (c) time-seriation output means for emitting in seriatim electrical signals provided by said radiation sensitive elements in order of arrangement of said elements in the array; (d) means for receiving a bias voltage to be supplied to said device; and (e) means electrically coupled with said bias voltage receiving means so as to provide an electrical signal informing of internal voltage variation in said device relative to variation of said bias voltage,wherein said optically opaque means is disposed to shield one or more such radiation sensitive elements the electrical signals of which are to be put out by said time-seriation output means relatively early in the output sequence, and said radiation sensing means, said time-seriation output means, said bias voltage receiving means and said internal voltage variation information providing means are formed on or in the same semiconductive substrate. 2. A radiation sensing device according to claim 1, wherein said internal voltage variation information providing means includes a field effect transistor having source, gate and drain electrodes for producing the electrical signal information of internal voltage variation through the source electrode wherein the drain electrode is electrically coupled to said bias voltage receiving means, and the gate electrode is constructed such that a potential variable in accordance with the internal voltage variation in the sensing device is applied to the gate electrode.
3. An image scanning system comprising:(A) a radiation sensing device arranged to receive an image, said device having;(a) radiation sensitive means for providing electrical signals corresponding to received radiations; (b) means for providing an electrical signal indicative of a dark current of the sensing device; (c) means for receiving a bias voltage to be supplied to said device; and (d) means electrically coupled with said bias voltage receiving means so as to provide an electrical signal informing of internal voltage variation in said device relative to variation of said bias voltage,wherein said internal voltage variation information providing means includes a field effect transistor having source, gate and drain electrode for producing the electrical signal information of internal voltage variation through the source electrode wherein the drain electrode is electrically coupled to said bias voltage receiving means, and the gate electrode is constructed such that a potential variable in accordance with the internal voltage variation in the sensing device is applied to the gate electrode; and (B) circuit means electrically coupled to said sensing device for compensating for the electrical signals provided by said radiation sensitive means with the electrical signal provided by said internal voltage variation information providing means and the dark current signal provided by said dark current signal providing means. 4. An image scanning system according to claim 3, wherein said circuit means includes:a first circuit for compensating for the electrical signals provided by said radiation sensitive means with the electrical signal provided by said internal voltage variation information providing means; and a second circuit for compensating for the electrical signals provided by said radiation sensitive means with the dark current signal provided by said dark current signal providing means. 5. An image scanning system according to claim 3, wherein said circuit means includes;a first circuit for compensating for the electrical signals provided by said radiation sensitive means and the dark current signal provided by said dark current signal providing means with the electrical signal provided by said internal voltage variation information providing means; and a second circuit for compensating for the electrical signals compensated by said first circuit and related to the radiation sensitive means with the dark current signal compensated by the first circuit and related to the dark current signal providing means. 6. An image scanning system comprising:(a) a radiation sensing device arranged to receive an image, said sensing device including:(i) An array of a plurality of radiation sensitive elements, each for providing an electrical signal indicative of received portion of said image; (ii) Optically opaque means for shielding a portion of said array so that an electrical signal indicative of a dark current is provided by one or more radiation sensitive elements shielded by said opaque means; (iii) time-seriation output means for emitting in seriatim electrical signals provided by said radiation sensitive elements in order of arrangement of said elements in the array; and (iv) output terminal means for leading out the electrical signals provided by said radiation sensitive elements to the exterior of said sensing device; and (b) means coupled to said output terminal means of said sensing device to subtract the electrical signal provided by said one or more radiation sensitive elements shielded by said opaque means from the electrical signals provided by unshielded radiation sensitive elements,wherein said array of radiation sensitive elements, said time-seriation output means and at least a portion of said subtract means are formed on or in the same semi-conductive substrate, said sensing device further comprising: means for receiving a bias voltage to be supplied to the sensing device; detection means electrically coupled to said bias voltage receiving means for detecting internal voltage variation in the sensing device relative to variation of said bias voltage and producing a detection signal to indicate the variation of the internal voltage; and second output terminal means for leading out the detection signal provided by said detection means to the exterior of said sensing device; and wherein said image scanning system further comprises: means coupled to both of said output terminal means of the sensing device to compensate for the electrical signals provided by the radiation sensitive elements with the detection signal provided by said detection means,wherein said bias voltage receiving means, said detection means and at least a portion of said compensation means are formed on or in said semi-conductive substrate. 7. An image scanning system according to claim 6, wherein said subtracting means is coupled to said compensation means to receive the compensated electrical signals by said compensation means.
8. An image scanning system according to claim 6, wherein said subtracting means includes:a circuit coupled to the output terminal means of said sensing device to sample and hold the electrical signal provided by said one or more radiation sensitive elements shielded by said opaque means; and a circuit coupled to the output terminal means and said sampling and holding circuit to subtract the electrical signal sampled and held by said sampling and holding circuit from the electrical signals provided by the unshielded radiation sensitive elements,wherein at least a portion of said sampling and holding circuit and at least a portion of said subtract circuit are formed on or in said semi-conductive substrate. 9. An image scanning system according to claim 8, which further comprises control means coupled to said sampling and holding circuit for controlling said circuit so that only the electrical signal provided by said one or more radiation sensitive elements shielded by said opaque may be sampled and held by said sampling and holding circuit.
12. An image scanning system comprising:(a) a radiation sensing device arranged to receive an image, said sensing device including:(i) an array of a plurality of radiation sensitive elements, each for providing an electrical signal indicative of received portion of said image; (ii) optically opaque means for shielding a portion of said array so that an electrical signal indicative of a dark current is provided by one or more radiation sensitive elements shielded by said opaque means; (iii) time-seriation output means for emitting in seriatim electrical signals provided by said radiation sensitive elements in order of arrangement of said elements in the array; and (iv) output terminal means for leading out the electrical signals provided by said radiation sensitive elements to the exterior of said sensing device; and (b) means coupled to said output terminal means of said sensing device to subtract the electrical signal provided by said one or more radiation sensitive elements shielded by said opaque means from the electrical signals provided by unshielded radiation sensitive elements, said subtracting means including:a circuit coupled to the output terminal means of said sensing device to sample and hold the electrical signal provided by said one or more radiation sensitive elements shielded by said opaque means; and a circuit coupled to the output terminal means and said sampling and holding circuit to subtract the electrical signal sampled and held by said sampling and holding circuit from the electrical signals provided by the unshielded radiation sensitive elements, wherein at least a portion of said sampling and holding circuit and at least a portion of said subtract circuit are formed on or in said-semi-conductive substrate, and wherein said array of radiation sensitive elements, said time-seriation output means at least a portion of said subtract means are formed on or in the same semi-conductive substrate, said sampling and holding circuit including: a capacitor adapted for holding an electrical signal corresponding to the electrical signal provided by said one or more radiation sensitive elements shielded by said opaque means; a charging circuit coupled to said capacitor for charging the capacitor with a constant current; a charge control circuit for controlling the charging of said capacitor with said constant current on the basis of the electrical signal provided by said one or more radiation sensitive elements shielded by the opaque means, said charge control circuit being coupled to said output terminal means and to said charging circuit; and an output circuit coupled to said capacitor for putting out the electrical signal held by the capacitor as the electrical signal provided by said one or more radiation sensitive elements shielded by the opaque means; said subtract circuit being coupled to said output circuit and subtract the electrical signal provided through the output circuit from the electrical signals provided by the unshielded radiation sensitive elements. 13. An image scanning system comprising:(a) a radiation sensing device arranged to receive an image, said sensing device including:(i) an array of a plurality of radiation sensitive elements, each for providing an electrical signal indicative of received portion of said image; (ii) optically opaque means for shielding a portion of said array so that an electrical signal indicative of a dark current is provided by one or more radiation sensitive elements shielded by said opaque means; (iii) time-seriation output means for emitting in seriatim electrical signals provided by said radiation sensitive elements in order of arrangement of said elements in the array; and (iv) output terminal means for leading out the electrical signals provided by said radiation sensitive elements to the exterior of said sensing device; and (b) means coupled to said output terminal means of said sensing device for subtracting the electrical signal provided by said one or more radiation sensitive elements shielded by said opaque means from the electrical signals provided by unshielded radiation sensitive elements,wherein, said subtracting means includes: a circuit coupled to the output terminal means of said sensing device to sample and hold the electrical signal provided by said one or more radiation sensitive elements shielded by said opaque means; and a circuit coupled to the output terminal means and said sampling and holding circuit to subtract the electrical signal sampled and held by said sampling and holding circuit from the electrical signals provided by the unshielded radiation sensitive elements, and wherein said sampling and holding circuit includes: a capacitor adapted for holding an electrical signal corresponding to the electrical signal provided by said one or more radiation sensitive elements shielded by said opaque means; a charging circuit coupled to said capacitor for charging the capacitor with a constant current; a charge control circuit for controlling the charging of said capacitor with said constant current on the basis of the electrical signal provided by said one or more radiation sensitive elements shielded by the opaque means, said charge control circuit being coupled to said output terminal means and to said charging circuit; and an output circuit coupled to said capacitor for putting out the electrical signal held by the capacitor as the electrical signal provided by said one or more radiation sensitive elements shielded by the opaque means; said subtract circuit being coupled to said output circuit and subtract the electrical signal provided through the output circuit from the electrical signals provided by the unshielded radiation sensitive elements; means for receiving a bias voltage to be supplied to the sensing device; detection means electrically coupled to said bias voltage receiving means for detecting internal voltage variation in the sensing device relative to variation of said bias voltage and producing a detection signal to indicate the variation of the internal voltage; and second output terminal means for leading out the detection signal provided by said detection means to the exterior of said sensing device; and wherein said image scanning system further comprises:means coupled to both of said output terminal means of the sensing device to compensate for the electrical signals provided by the radiation sensitive elements with the detection signal provided by said detection means, and wherein said detection means includes: a field effect transistor having source, gate and drain electrodes for producing the detection signal indicative of the internal voltage variation through the source electrode wherein the drain electrode is electrically coupled to said bias voltage receiving means, and the gate electrode is constructed such that a potential variable in accordance with the internal voltage variation in the sensing device is applied to the gate electrode. 14. An image scanning system according to claim 13 which further comprises control means coupled to said sampling and holding circuit for controlling said circuit so that only the electrical signal provided by said one or more radiation sensitive elements shielded by said opaque means may be sampled and held by said sampling and holding circuit.
17. A radiation sensing device comprising:(a) radiation sensitive means for providing electrical signals corresponding to received radiations; (b) means for providing an electrical signal indicative of a dark current of the sensing device; (c) means for receiving a bias voltage to be supplied to said device; and (d) means electrically coupled with said bias voltage receiving means so as to provide an electrical signal informing of internal voltage variation in said device relative to variation of said bias voltage, wherein said radiation sensitive means, said dark current signal providing means, said bias voltage receiving means and said internal voltage variation information providing means are formed on or in the same semi-conductive substrate. 18. A radiation sensing device according to claim 17, wherein said internal voltage variation information providing means includes a field effect transistor having source, gate and drain electrode for producing the electrical signal information of internal voltage variation through the source electrode wherein the drain electrode is electrically coupled to said bias voltage receiving means, and the gate electrode is constructed such that a potential variable in accordance with the internal voltage variation in the sensing device is applied to the gate electrode.
19. A radiation sensing device comprising:(a) radiation sensitive means for providing electrical signals corresponding to received radiations; (b) means for providing an electrical signal indicative of a dark current of the sensing device; (c) means for receiving a bias voltage to be supplied to said device; and (d) means electrically coupled with said bias voltage receiving means so as to provide an electrical signal informing of internal voltage variation in said device relative to variation of said bias voltage,wherein said internal voltage variation information providing means includes a field effect transistor having source, gate and drain electrode for producing the electrical signal information of internal voltage variation through the source electrode wherein the drain electrode is electrically coupled to said bias voltage receiving means, and the gate electrode is constructed such that a potential variable in accordance with the internal voltage variation in the sensing device is applied to the gate electrode. 20. An image scanning system comprising:(A) a radiation sensing device arranged to receive an image, said device having;(a) radiation sensitive means for providing electrical signals corresponding to received radiations; (b) means for providing an electrical signal indicative of a dark current of the sensing device; (c) means for receiving a bias voltage to be supplied to said device; and (d) means electrically coupled with said bias voltage receiving means so as to provide an electrical signal informing of internal voltage variation in said device relative to variation of said bias voltage,wherein said radiation sensitive means, said dark current signal providing means, said bias voltage receiving means and said internal voltage variation information providing means are formed on or in the same semi-conductive substrate; and (B) circuit means electrically coupled to said sensing device for compensating for the electrical signals provided by said radiation sensitive means with the electrical signal provided by said internal voltage variation information providing means and the dark current signal provided by said dark current signal providing means. 21. An image scanning system according to claim 20, wherein at least a portion of said circuit means is formed on or in said semi-conductive substrate.
22. An image scanning system according to claims 20 or 21, wherein said circuit means includes:a first circuit for compensating for the electrical signals provided by said radiation sensitive means with the electrical signal provided by said internal voltage variation information providing means; and a second circuit for compensating for the electrical signals provided by said radiation sensitive means with the dark current signal provided by said dark current signal providing means. 23. An image scanning system according to claims 20 or 21, wherein said circuit means includes;a first circuit for compensating for the electrical signals provided by said radiation sensitive means and the dark current signal provided by said dark current signal providing means with the electrical signal provided by said internal voltage variation information providing means; and a second circuit for compensating for the electrical signals compensated by the first circuit and related to the radiation sensitive means with the dark current signal compensated by the first circuit and related to the dark current signal providing means. 24. An image scanning system according to claim 20, wherein said internal voltage variation information providing means includes a field effect transistor having source, gate and drain electrode for producing the electrical signal information of internal voltage variation through the source electrode wherein the drain electrode is electrically coupled to said bias voltage receiving means, and the gate electrode is constructed such that a potential variable in accordance with the internal voltage variation in the sensing device is applied to the gate electrode.
25. A radiation sensing device comprising:(a) radiation sensing means having a plurality of radiation sensitive elements, each for providing an electrical signal corresponding to received radiation, said plurality of radiation sensitive elements in said radiation sensing means being arranged in array; (b) optically opaque means for shielding a portion of said radiation sensing means so that an electrical signal indicative of a dark current is provided by one or more radiation sensitive elements shielded by said opaque means, said optically opaque means shielding at least one radiation sensitive element located at or near the end of said array; (c) time-seriation output means for emitting in seriatim electrical signals provided by said radiation sensitive elements in order of arrangement of said elements in the array; (d) means for receiving a bias voltage to be supplied to said device; and (e) means electrically coupled with said bias voltage receiving means so as to provide an electrical signal informing of internal voltage variation in said device relative to variation of said bias voltage,wherein said optically opaque means is disposed to shield one or more such radiation sensitive elements the electrical signals of which are to be put out by said time-seriation output means relatively early in the output sequence, and wherein said internal voltage variation information providing means includes a field effect transistor having source, gate and drain electrode for producing the electrical signal information of internal voltage variation through the source electrode wherein the drain electrode is electrically coupled to said bias voltage receiving means, and the gate electrode is constructed such that a potential variable in accordance with the internal voltage variation in the sensing device is applied to the gate electrode. Description
Accordingly, it is primary object of the present invention to provide a novel photo-sensor device which eliminates the problem of disturbing noise signals such as that of dark current mentioned above.
FIG. 1 is a schematic view of a photo-sensor device showing an embodiment of the invention;
Referring first to FIG. 1 showing an embodiment of the invention, a photo-sensor device is generally designated by 1. In this embodiment, a four phase transfer type of self-scanning CCD photo-sensor or CCD photo-diode array is selected as the photo-sensor device 1 which has been modified in accordance with the invention.
41 and 42 are electric charge transfer parts of which the first transfer part 41 serves to take up the accumulated charge on a group of light receiving elements, for example, elements in odd numbers through a transfer gate 31 and transfer the charge to an output part 5 successively in response to transfer clock. The second transfer part 42 takes up the charge accumulated on the light receiving elements in even numbers through a second transfer gate part 32 and transfer it to the output part 5 in the same manner. The output part 5 converts the electric charge transferred thereto by the transfer parts 41 and 42 into a corresponding voltage or current which is then put out from the output part.
1a is a voltage input terminal through which voltage VE is applied to the light receiving part 2 as a photo gate voltage in the manner known per se (or the voltage VE becomes a substrate bias voltage). 1b is a start pulse input terminal through which start pulse φs (FIG. 6-(g)) is applied to the two transfer gate parts 31 and 32 as gate pulse. Through transfer clock input terminals 1c, 1d, 1e and 1f there are applied to the charge transfer parts 41 and 42 four phase transfer clocks φ1, φ2, φ3 and φ4 which are shifted in period by 1/4 each other as shown in FIGS. 6-(b) to (e). These transfer clocks serve to initiate the charge transfer parts into taking up and transferring of the charges. 1g designates a reset pulse input terminal through which a reset pulse φR (FIG. 6-(f)) is applied to a charge resetting transistor at the output part 5. Designated by 1h is a ground terminal, and output terminal 1i of the device 1 are connected to the output part 5.
Light receiving elements constituting the light receiving part 2 are replaced by photo diodes respectively and the transfer gate parts 31 and 32 are replaced by a switch array of MOS-FET disposed to address the photo diodes. Also, the charge transfer parts 41 and 42 are replaced by shift registers for switch addressing. Pulses to be applied to the shift registers in this case are start pulse and such two clocks selected from the four phase clocks φ1 -φ4 having an inverted relation to each other, for example, clocks φ1 and φ3. When the photo diodes are addressed by the shift operation of the shift registers (41, 42), photo-electric signals are issued from the output terminal 1i through the corresponding FET switches in the array of MOS-FET switches (31, 32). Thus, in this case, the above described output part 5 is no longer necessary. Also, in this case, the above mentioned voltage VE to be applied through the input terminal 1a is used as a charging voltage to charge p-n capacitors of the photodiodes.
In case of CCD photo-sensor or CCD photo-diode array it is preferable to select, as the shielded elements 2', those elements located near the output part 5, namely those elements whose electric charges are to be transferred to the output part 5 early in the period of charge transferring by the charge transfer parts 41 and 42.
In case of self-scanning type photo-diode array, it is also preferable to select, as the shielded elements 2', those photodiodes which are to be addressed early in the shift operation of the shift registers (41, 42).
The detection part 7 is so formed as to detect the voltage variation within the device 1 relative to the variation of voltage VE applied to the device 1 through the input terminal 1a and produce an electrical signal corresponding to the detected voltage variation.
In FIG. 2, voltage divider resistances 7a and 7b are electrically connected to the input terminal 1a and to the ground terminal 1h through semiconductor channel respectively to divide the voltage VE. 7d is a MOS-FET whose gate is electrically connected to the dividing point between the two voltage divider resistances 7a and 7b. Its drain is connected to the input terminal 1a whereas the source is connected to the ground terminal 1h through a resistance 7c. With this arrangement there is produced, at the junction between the source of FET 7d and the resistance 7c, a voltage corresponding to the internal voltage in the device 1 relative to the voltage VE. Therefore, when any variation occurs in VE, there is obtained an electrical signal informing of the voltage variation within the device 1 relative to the voltage variation of VE. Designated by 1j is an output terminal for the voltage variation information signal which is connected to the junction between the source of FET 7d and the resistance 7c.
Generally designated by 8 is a differential amplifier circuit serving as the voltage variation component eliminating circuit mentioned above. Output signal from the output terminal 1i of the sensor device 1 which output signal is hereinafter referred to as sensor output signal (FIG. 5(a)) and output signal from the output terminal 1j, that is, the voltage variation information signal from the variation detection part 7 are introduced into the differential amplifier circuit 8 to remove the voltage variation component from the sensor output signal. The circuit 8 is constituted of an operation amplifier OP1 and resistances R1 ro R4. The sensor output signal is applied to the inversion input terminal of the operational amplifier OP1 through the resistance R1. The voltage variation information signal is applied to the non-inversion input terminal of the operational amplifier OP1 through the resistance R3.
Generally designated by 9 is a dark current signal sampling and holding circuit which receives the output signal from the above circuit 8, that is, the sensor output signal free of any voltage variation component. The sampling and holding circuit 9 is so formed as to sample and hold only such portion of the received sensor output signal which corresponds to the output signal derived from the shielded light receiving elements 2' as a dark current signal. Comparator CP1, resistances R5 -R7, transistors Tr1-Tr5, condenser C1 and buffer amplifier BP1 constitute the dark current signal sampling and holding circuit 9. The output signal issued from the above described differential amplifier circuit 8 is allowed to enter the non-inversion input terminal of comparator CP1 through the resistance R5 only when the input control transistor Tr1 is in its nonconductive state. At that time, to the inversion input terminal of the comparator CP1 there is applied a voltage stored in the condenser C1. The output from CP1 is applied to the base of transistor Tr2 in such manner that the charging level of condenser C1 can be determined depending upon the level of input signal to the non-inversion input terminal. Therefore, condenser C1 can be charged with constant current for a long time determined by the output of comparator CP1, namely for a long time which corresponds to the level of the input signal applied to the non-inversion input terminal of comparator CP1. As a result, this circuit operates in a manner of constant current operation. As previously mentioned, the input to the non-inversion input terminal of the comparator CP1 is limited only to such a portion of the output signal from the circuit 8 which corresponds to the output signal coming from the shielded light receiving elements 2'. To this end, the input to the non-inversion input terminal of CP1 is controlled by a control signal generating circuit which, as described hereinafter, applies a control signal φ5 (FIG. 5-(c)) to the base of the input control transistor Tr1. Before the output of the circuit 8 is applied to the non-inversion input terminal of CP1, the storage value of C1 is cleared up by a control signal φ6 (FIG. 5-(d)) applied to the base of storage value clearing transistor Tr5.
Output signal from the above mentioned circuit 8, that is, the sensor output signal freed of voltage variation component and output from the circuit 9, that is, the dark current information signal held by the condenser C1 are introduced into the differential amplifier circuit 10. Operational amplifier OP2 and resistances R8 to R11 constitute the circuit 10. The output from the differential circuit 8 is applied to the non-inversion input terminal of the operational amplifier OP2 through the resistance R8 whereas its inversion terminal receives the output signal from the dark current signal sampling and holding circuit 9 through the resistance R10. The sensor output signal already freed from voltage variation component is further processed by this circuit 10 to remove the dark current component from it.
A filter circuit generally designated by 11 is provided to filter off any remaining high frequency noise component from the output signal coming out from the above differential amplifier circuit 10. The filter circuit 11 is composed of a resistance R12 and a condenser C2.
Among these circuits, a circuit generally designated by 12 is a peak detection circuit for detecting the peak of the output signal of the above filter circuit 11, that is, the peak value of a sensor output signal which has already got free of voltage variation component, dark current component and high frequency noise component. Comparator CP2, resistances R13 to R15, condenser C3, transistors Tr6 to Tr10 and buffer amplifier BP2 constitute the detection circuit 12. The peak detection circuit is so formed as to operate in a manner of constant current operating circuit like the above described dark current signal sampling and holding circuit 9.
The output signal coming from the above filter circuit 11 is applied to the non-inversion input terminal of the comparator CP2 through the resistance R13. This input to the non-inversion terminal is controlled by a control signal φ7 (FIG. 5-(e)) applied to the base of the input control transistor Tr6. The control is, in this case, made in such manner that only such portion of the output signal coming from the filter circuit 11 is applied to the non-inversion terminal which corresponds to the basic view field image previously described in connection with the range finder apparatus disclosed in U.S. Pat. No. 4,004,852. Before the output of the filter circuit is applied to the comparator CP2, the storage value of the condenser C3 is cleared up by a control signal φ8 (FIG. 5-(f)) applied to the base of storage value clearing transistor Tr10.
A circuit generally designated by 13 is a peak value holding circuit. This circuit serves to holding the peak value of the sensor output signal detected by the above peak detection circuit 12 for one scanning period of time. Comparator CP3, resistances R16 to R18, transistors Tr11 to Tr15, peak value holding condenser C4 and buffer amplifier BP3 constitute the peak value holding circuit 13. Like the above described circuits 9 and 12, this circuit 13 is also formed as a constant current operation circuit. The output signal coming from the above peak detection circuit 12, that is, the peak value information signal stored in the condenser C3 is applied to the non-inversion input terminal of the comparator CP3 through the resistance R16. Input of the peak value information signal to the comparator is controlled by a control signal φ9 (FIG. 5-(g)) applied to the base of the input control transistor Tr11 in such manner that the inputting may be effected only after the reading-out of the sensor output signal has been finished. Before this inputting of the peak value information signal to the comparator CP3, the storage value of the condenser C3 is cleared up by a control signal φ10 (FIG. 5-(h)) applied to the base of the storage value clearing transistor Tr15.
Function of this circuit 14 is to set a slice level relying upon the output signal coming from the above peak value holding circuit 13, namely the peak voltage (hereinafter referred to as Vp) stored in the condenser C4. The slice level is used as a basis on which the sensor output signal is binary coded.
Voltage divider resistances R19 and R20 and variable resistance for adjustment VR constitute the voltage dividing circuit 14. A voltage obtained at the dividing point between R19 and R20 which is hereinafter referred to as Vs is used as the slice level for binary coding.
Designated by 15 is a binary coding circuit for binary coding the output signal coming from the above filter circuit 11 making use of the above mentioned output voltage Vs of the circuit 14 as a slice level. The circuit 15 comprises a binary coding comparator CP4 which receives at its non-inversion input terminal the output from the filter circuit 11 and at its inversion input terminal the output voltage Vs from the voltage dividing circuit 14.
FIG. 4 shows a basic form of a control signal generating circuit for generating various clocks and control pulses such as start pulse φs, transfer clocks φ1 -φ4 and reset pulse φR required to drive the sensor device 1 and control signals φ5 -φ10 required to control the above described circuits 9, 12 and 13. In FIG. 4, the reference numeral 16 designates a fundamental clock pulse generating circuit for generating fundamental clock CLK (FIG. 6-(a)). 17 is a driver circuit for generating the above mentioned start pulse φs, transfer clocks φ1 -φ4 and reset pulse φR to drive the sensor device 1 in accordance with the start signal φA externally given and the fundamental clock pulse CLK given by the fundamental clock generating circuit 16. The driver circuit 17 is formed in a manner known per se and comprises a frequency dividing counter and a group of logical gates.
18 is a control signal generating circuit for generating the above mentioned control signals φ5 -φ10 to control the dark current signal sampling and holding circuit 9, peak detection circuit 12 and peak value holding circuit 13. The circuit 18 comprises a counter or shift register and a group of logical gates. It operates in accordance with the start pulse φs and reset pulse φR issued from the above driver circuit 17. The driver circuit issues the start pulse φs in response to the start signal φA which is externally given.
In FIG. 5, an electric power switch not shown is thrown in the circuit at to and thereby a voltage VE is applied to the input terminal 1a of the sensor device 1 as well as to the differential amplifier circuit 8 (FIGS. 3A and 3B). At the same time, to other circuits is applied also a voltage V'E. This results in forming potential wells in the light receiving part 2 at the area under of close to the elements 2' and 2". Now, accumulation of charge is started. On the other hand, the fundamental clock generating circuit 16 starts issuing CLK (FIG. 6-(a)) that is a fundamental clock pulse which in turn makes the driver circuit 17 issue transfer clocks φ1 -φ4 and reset pulse φR (FIG. 6-(b) to (f)) which are applied to the input terminals 1c-1g of the sensor device 1. In this position, if a start signal φA is given to the driver circuit 17 at a time point about t1, then the driver circuit will put out a start pulse φs (FIG. 5-(b)) which is applied to the input terminal 1b of the sensor device 1. Now, on the sensor device 1, there are formed potential wells at the transfer gate parts 31 and 32.
Among the light receiving elements 2' and 2", a group of elements, for example, those located in odd numbers allow then the electric charge accumulated therein to be taken up by the charge transfer part 41 through the transfer gate part 31. Similarly, the electric charge accumulated in another group of elements in even numbers is taken up by the charge transfer part 42 through the transfer gate part 32.
In this manner, during the time from t2 to t10, all of the electric charges accumulated in the light receiving elements 2', 2" are transferred to the output part 5 through the charge transfer parts 41 and 42 and therefore, as shown in FIG. 5-(a), an output in a form of voltage or of current can be put out in time series from the output terminal 1i. This sensor output signal obtained from the output terminal 1i is shown in FIG. 5-(a) as a signal of wave form. But, in fact the output signal is obtained as a time series pulse signal.
The sensor output signal from the output terminal 1i is applied to the operation amplifier OP1 of the differential amplifier circuit 8 at its inversion input terminal. On the other hand, to the non-inversion input terminal of the same operational amplifier OP1 there is applied from the output terminal 1j a voltage variation information signal at the same time. This signal is derived from the above described voltage variation detection part 7 which detects variation in voltage within the sensor device 1 relative to the voltage VE being applied to the input terminal 1a. Therefore, the output Vopl coming from the operational amplifier OP1 is given by the following equation:
Vopl=r4 /(r3 +r4)�(r1 +r2)/r1 �V2 -(r2 /r1)�V1 wherein,
V1 is output of the output terminal 1i,
V2 is output of the output terminal 1j, and
r1 -r4 represent resistance values of the resistances R1 -R4 respectively.
When r1 =r2 =r3 =r4, then
Vopl=V2 -V1 From the above it will be understood that at the output terminal of the differential amplifier circuit 8 there appears a signal free of the voltage variation component. In this manner, variation component attributable to variation of the voltage VE can be removed from the sensor output signal.
In reading out the output of the sensor device 1, there is obtained, as an example, a signal corresponding to the electric charge accumulated in the shielded elements 2' of the light receiving part 2 during the time of from t2 to t5. However, during the time of from t2 to t3, the control signal generating circuit 18 will give the base of Tr5 of the dark current signal sampling and holding circuit 9 a control signal φ6 which is in the high level at that time as shown in FIG. 5-(d). As a result, the transistor Tr5 becomes conductive so that the charge of the condenser C1 can be cleared up during this time. After the condenser charge is cleared up, the control signal generating circuit 18 applies to the base of the input control transistor Tr1, during the time of t3 to t4, a control signal φ5 which is in the low level as shown in FIG. 5-(c). As a result, during this time, the transistor Tr1 becomes nonconductive. Therefore, the output coming from the circuit 8 is allowed to enter the non-inversion input terminal of the comparator CP1 only during the time of the transistor Tr1 being non-conductive, namely during the time of from t3 to t4. The output signal actually applied to the non-inversion input terminal of the comparator CP1 during the time is therefore such signal which corresponds to the charge accumulated in those elements only which are located in the central area of the group of shielded elements 2'. Those elements are indicated by 2'a in FIG. 1. The signal is applied in a form free of voltage variation component for the reason mentioned above.
As previously described, the inversion input terminal of the comparator CP1 is connected to the condenser C1. When Tr1 is conductive and the output of the circuit 8 is allowed to enter the non-inversion input terminal, the potential of the non-inversion input becomes higher than that of the inversion input. Therefore, the output of the comparator CP1 is then inverted from Low to High. Transistor Tr2 now becomes conductive and the base and collector are short-circuited. As a result, a constant current IR6 determined by the resistance R6 flows through Tr4 functioning as a diode. At the same time, Tr3 becomes conductive and charging of the condenser C1 is initiated by the current I1 flowing through the transistor Tr3. Assuming that the resistance value of R7 is sufficiently higher than that of R6 and that the base current in Tr3 is negligible, the voltage VBE4 between base and emitter of Tr4 and the voltage VBE3 between base and emitter of Tr3 will be given by the following equations respectively: ##EQU1## wherein, K is Boltzmann's constant,
IR6 is current flowing through the resistance R6, and
I1 is charge current of the condenser C1.
For the shown embodiment of circuit, VBE4 =VBE3 and, therefore, IR6 =I1. This means that the condenser C1 is charged with a constant current equal to the current flowing through R6.
With rising up of the potential of C1, the potential of the inversion input of CP1 rises up gradually and at last it becomes higher than the potential of the non-inversion output thereof. At the time point, the output of the comparator CP1 is inversed High to Low so that Tr2 becomes nonconductive. Then, charging of the condenser C1 is stopped.
In this manner, the dark current signal sampling and holding circuit 9 can operate to sample and hold the dark current signal based upon the output signal coming from the above circuit 8 but using only such signal thereof which corresponds to the charge accumulated in the element 2'a centrally located in the group of the shielded light receiving elements 2'. The dark current informaton signal thus stored in the condenser C1 is put out through the buffer amplifier BP1.
The function of the above mentioned resistance R7 is to eliminate the delay is switching of the transistor Tr3 caused by junction capacitance of the diode connected transistor Tr4 when Tr2 is turned nonconductive. The delay in operation of inversion of CP1 and of Tr2 and Tr3 is constant. Therefore, assuming that charging of the condenser C1 is always stopped a constant time (tD) after the time point when the potential of the inversion input of the comparator CP1 exceeds that of the non-inversion input, irrespective of any variation of the output voltage from the above circuit 8, the detection error voltage ΔV caused by over-charging the condenser C1 due to delay in response of the circuit system will become:
&#916;V=(tD �I1 /Cq)
wherein, Cq is capacity of the condenser C1. Therefore, it is possible to obtain a voltage which correctly and accurately corresponds to the dark current signal voltage by shifting the offset voltage of CP1 or BP1 by an amount corresponding to the error voltage ΔV or by connecting a differential amplifier circuit to the output terminal of BP1 to subtract the error voltage ΔV.
Again, referring to FIG. 5, during the time from t5 to t10 there is obtained a signal corresponding to the charge accumulated in the unshielded elements 2" of the light receiving part 2. This signal contains the scanning signal relating to the basic view field image and reference view field image formed on the elements 2". After the voltage variation component are removed from it, the signal is to be applied to the non-inversion input terminal of the operational amplifier OP2 of the next circuit, that is, the differential amplifier circuit 10. However, at this time, to the inversion input terminal of the same operational amplifier OP2 on the other hand there is applied the dark current information signal sampled and held by the above circuit 9 during the time of from t3 to t4. Therefore, like the above mentioned output Vop1 of the operational amplifier OP1 in the circuit 8, the output VoP2 of the operational amplifier OP2 is given by:
Vop2=r9 /(r8 +r9)�r10 +r11 /r10 �Vop1-(r11 /r10)�VBP1 wherein, VBP1 is output from the dark current signal sampling and holding circuit 9, and r8 -r11 are resistance values of the resistances R8 -R11 respectively.
Let r8 =r9 =r10 =r11, then Vop2=Vop1-VBP1.
In the peak detection circuit 12, there is given a control signal φ8 to the base of transistor Tr10 by the control signal generating circuit 18 during the time of from t2 to t6 as shown in FIG. 5-(f). Since the control signal φ8 is a High level signal, Tr10 is conductive during the time and the charge in the condenser C3 is cleared up. After clearance of the charge, the control signal generating circuit 18 gives the base of input control transistor Tr6 a Low level control signal φ7 during the time of t6 to t7 so that Tr6 becomes nonconductive during the time. Therefore, among the outputs coming from the above filter circuit 11 only such output as issued therefrom during the time of t6 to t7, namely during the time of Tr6 being nonconductive is allowed to come into the non-inversion input terminal of the comparator CP2. As will be understood from FIG. 5-(a) this output corresponds to the basic view field image formed on the unshielded elements 2". The remaining output obtained during the time of t5 to t6 corresponds to the signal derived from those elements lying near the basic view field image and therefore it is not a scanning signal of the basic view field image. In this manner, by turning down the control signal φ7 from High to Low at the time point t6 it is assured that the comparator CP2 receives only such signal which accurately corresponds to the basic view field image.
As described above, at the time point t6 the comparator CP2 receives at its non-inversion input terminal from the above filter circuit 11 a scanning output of the basic view field image which no longer contains any voltage variation component, dark current component and high frequency noise component. Like CP1 in the circuit 9, the inversion input terminal of the comparator CP2 is connected to condenser C3. Therefore, upon the time when the above mentioned output of the filter circuit 11 is applied to the non-inversion input terminal of the comparator CP2, the output thereof is inverted from Low to High. This makes transistors Tr7 and Tr8 conductive so that charging of the condenser C3 is started with a constant current equal to the current flowing through the resistance R14 in the same manner as in the case of the above described circuit 9. When the charge voltage on C3 exceeds the output voltage from the filter circuit 11, the output of CP2 is again inverted from High to Low to stop charging of the condenser C3. The above described operation of starting and stopping charging of the condenser C3 depending upon the variation of output from the filter circuit 11 is repeated up to the end of time t7 in the peak detection circuit 12. Finally, when t7 has passed, transistor Tr6 is turned conductive so that delivery of the output from the filter circuit 11 to the non-inversion input terminal of CP2 is cut off. At this time point, there remains stored in the condenser C3 the maximum value among the outputs put out from the filter circuit 11 during the time of t6 to t7. This maximum value is a voltage corresponding to the peak of the scanning output relating to the basic view field image. In this manner, the peak of the scanning output signal relating to the basic view field image can be detected.
With the advance of the operation time to t8, t9 and t10, the scanning signals obtained during the time are successively applied to the binary coding circuit 15 after the voltage variation component, dark current component and high frequency noise component are removed in the circuits 8, 10 and 11 respectively in the same manner as described above. Like the signals obtained during the time of t5 to t6, those signals as obtained during the time of t7 to t8 and during the time of t9 to t10 among all the signals during the time of from t7 to t10 are not related to the view field image. The scanning signals related to the reference view field image are only those which are obtained during the time of t8 to t9.
After t10 has passed and reading out the output of the sensor device has been finished, a control signal φ10 is applied to the base of transistor Tr15 in the peak value holding circuit 13 from the control signal generating circuit 18 at the beginning of t11. As shown in FIG. 5-(h), the control signal φ10 is in High level during the time of from t11 to t12. Therefore, during the time, Tr15 becomes conductive so that the charge on C4 is cleared up. After the clearance of charge of the condenser C4, there is applied to the base of input control transistor Tr11 from the control signal generating circuit 18 a control signal φ9 which becomes low during the time of from t12 to t13 as shown in FIG. 5-(g). As a result Tr11 is non-conductive during the time and the output coming out from the above peak detection circuit 12 is allowed to come into the non-inversion input terminal of the comparator CP3. Thus, in a manner as previously described in connection with the dark current signal sampling and holding circuit 9 and the peak detection circuit 12, the condenser is charged up to a level corresponding to the potential of non-inversion input of the comparator CP3. The result is that a voltage corresponding to the peak value of scanning output signal relating to the basic view field image detected by the above circuit 12 is stored in the condenser C4. The voltage stored in C4 is then applied to the voltage divider circuit 14 as a peak voltage Vp through buffer amplifier BP3. At the output terminal of the voltage divider circuit 14 there appears a voltage Vs which can be represented by: ##EQU2## wherein, r19 and r20 are resistance values of resistances R19 and R20 respectively, and vr is resistance value of variable resistance VR. This output constitutes a slice level for binary coding of signal and is applied to the inversion input terminal of the comparator CP4 in the binary coding circuit 15.
In the above described position of operation and at a time point, for example, about t14, start signal φA may be given to the driver circuit 17 again. By doing so, the driver circuit issues again a start pulse φs to initiate again reading out the output of the sensor device. Scanning output signal obtained this time is applied to the non-inversion input terminal of the comparator CP4 in the binary coding circuit 15 after the voltage variation component, dark current component and high frequency noise component being removed through the circuits 8, 10 and 11 in the same manner as described above. Thus, by the comparator CP4, a binary coding of the scanning signal is effected using the slice level of Vs set based upon the peak voltage Vp detected the last time.
In reading out the output of the sensor device this time, sampling and holding the dark current signal by the circuit 9 is effected during the time of from t16 to t17 and the dark current component detected thereby is then removed in the differential amplifier circuit 10. During the time of t19 to t20 there is carried out the detection of peak value again by the circuit 12 and at t23 the reading out of output of the sensor device comes to end. At t24, the peak voltage Vp stored in the circuit 13 is cleared up and at t25 the peak value is rewritten by a new peak value detected by the circuit 12 during the time of from t19 to t20. The output voltage Vs obtained this time from the voltage divider circuit becomes a slice level for binary coding of scanning signal to be obtained by the next reading of sensor device output.
The operation described above is repeated thereafter whenever a new start signal φA is applied to the driver circuit 17. Thus, from the binary coding circuit 15 there are obtained, with high accuracy, binary coded data related to the basic view field image and the reference view field image optically formed on the sensor device 1.
As illustrated in FIG. 7, the sensor device 1 is of composition of 128 bits. In other words, the light receiving part 2 comprises 128 elements. Of these 128 light receiving elements, 14 elements at the side close to the output part, namely at the left hand side as viewed in the drawing are used as shielded elements 2'. But, among the shielded elements 2', the left end area D1 covering 4 (four) bits and the right end area D2 covering 4 bits are blocking areas, and the central area DM covering 6 bits is used for detection of dark current. The area covering 6 bits designated by D3 is a dummy area. The next area covering 30 bits generally designated by A is an area for receiving the basic view field image and the area B covering 60 bits is that for receiving the reference view field image. The area D4 covering 12 bits between the areas A and B is used as an image separation area. The last area covering 6 bits designated by D5 is also a dummy area.
The time from the application of a start pulse φs to the sensor device 1 to the actual start of output is assumed to be equal to the time required to drive four bits as suggested by a broken line in FIG. 7.
As the control pulse φ10 to be applied to the storage value clearing transistor Tr15 in the peak value holding circuit 13, there is used such signal which changes from Low to High after the elapse of a four bit driving time following to the end of output from the device 1 and returns to High from Low after the elapse of a further six bit driving time.
Similarly, as the control signal φ9 to be applied to the input control transistor Tr11 there is used a signal the level of which changes from High to Low at the time of the above control signal φ10 being returned to Low from High and returns to High from Low after the lapse of time necessary to drive six bits following the first change of the level.
In FIG. 8, designated by SR is a shift register of 148 bit, input in series-output in parallel type. The shift register receives, at its data input terminal D, start pulse φs and at its clock input terminal CK, reset pulse φR from the driver circuit 17. G1 to G7 are OR-gates of which G1 is provided for making a logical sum of outputs from the fifth to eighth bits. Similarly, G2 is for the 9th to 14th of bits, G3 is for the 15th to 24th, G4 is for the 25th to 54th, G5 is for the 137th to 142th and G6 is for the 143th to 148th of bits. G7 is used for making a logical sum of outputs coming G1 to G3. The circuit 18 further comprises three inverters IV1, IV2 and IV3 to put out the outputs of G2, G5 and G7 in an inversed logical form respectively.
In the position of the circuit in which a reset pulse φR is being applied to the clock input terminal CK of the shift register SR from the driver circuit 17, a start pulse φs is issued from the driver circuit in response to a start signal φA externally given. Then, the data input of the shift register SR will become "1" and when a reset pulse φR is applied during the time of the start pulse φs being in High level as shown in FIG. 6, the "1" will be stored in the first bit of the shift register SR. Since, as seen in FIG. 6, the start pulse φs returns to Low to High in timing with the change of the reset pulse φR from High to Low, the data input of the register SR remains "0" after that. Therefore, the stored data "1" is shifted bit by bit in the direction of arrow Y every time when reset pulse φR is applied. In this step of shifting the stored data "1" in response to the reset pulse φR, the data enters the section of from the fifth bit to the eight one. During the time at which the data "1" is in any bit of the section, the output of OR-gate G1 is High. As will be understood from FIG. 7, the time period during which the output of G1 is High corresponds to the time period during which the output of the shielded blocking area D1 is being read out. Therefore, this output coming from the OR-gate G1 is the control signal φ6 (FIG. 5-(d)) to be applied to transistor Tr5 in the dark current sampling and holding circuit 9.
The data "1" is further advanced in the shift register SR and comes into the section of from the 9th bit to the 14th bit. During the time of the data being in any bit of the section, the output of G2 is High. Since the time period during which this OR-gate G2 issues the high output corresponds to the time period during which the output coming from the dark current detection area DM of the light receiving part 2 is being read out, the inversed output of the inverter IV1 derived from this output of the gate G2 constitutes the control signal φ5 (FIG. 5-(c)) to be applied to the input control transistor Tr1 in the circuit 9.
On the other hand, during the time period at which the stored data "1" is in any one of the bit group consisting of bits from the 5th bit to 24th bit, any one of outputs coming from gates G1-G3 is High. Therefore, during this time period the output of the gate G7 is also High. As seen from FIG. 7, this time period just corresponds to the time period during which reading-out of output is effected for the areas D1, DM, D2 and D3 covering 20 bits in total in the light receiving part 2. Therefore, this output of G7 is the control signal φ8 (FIG. 5-(f)) for the storage value clearing transistor Tr10 in the peak detection circuit 12.
The stored data "1" is further advanced in the shift register SR and comes into the section of from the 25th bit to the 54th one. During the time period of the data being in this section, the output of OR-gate G4 is High. This time period just corresponds to the time period of reading out the output coming from the basic view field image area A covering 30 bits in the light receiving part 2. Therefore, the inversed output of the inverter IV2 derived from the output of the gate G4 is the control signal φ7 (FIG. 5-(e)) to be applied to the input control transistor Tr6 of the peak detection circuit 12.
The data "1" is further advanced in the shift register SR and when it comes into the 132th bit, the readout of output of the sensor device 1 is completed all over. A driving time of more 4 bits after, the data "1" will be stored in the 137th bit. During the time period of the data being further shifted up to the 143th bit, the output of the gate G5 is High and therefore it becomes the control signal φ10 (FIG. 5-(h)) to be applied to transistor Tr15 of the peak value holding circuit 13. During the next period of data shift from the 143th bit to the end position at which the stored data is discharged from the shift register SR, the output of the gate G6 is High. Since the gate G6 is connected to the inverter IV3, this output of the gate G6 inverted by the inverter constitutes the control signal φ9 (FIG. -(g)) to be applied to the input control transistor Tr11 in the circuit 13.
In this manner, all the control signals φ5 -φ10 necessary for the dark current signal sampling and holding circuit 9, peak detection circuit 12 and peak value holding circuit 13 are obtainable from the control signal generating circuit 18 shown in FIG. 8.
Theoretically, the number of the shielded elements 2' may be three in total, one for the dark current detection area DM and two for the two blocking areas D1 and D2. In practice, however, considering the problem of signal level and the signal processing in the after-connected circuits, it is advisable to use two or more elements in each of the areas D1, D2 and DM as in the case of the shown embodiment. That is true in particular for the case wherein the electric charges accumulated in the light receiving part 2 are divided into two groups, namely, a first group of elements in odd numbers and a second group of even numbered elements and they are transferred separately through separate CCD channels (charge transfer parts 41 and 42) as in the case of FIG. 1 embodiment. In this case, variation of dark current ocurred in one channel and that in another are not always equal to each other. Therefore, it is preferable for the dark current detection area to comprise two or more continuous elements.
For example, the application of the present invention is not limited only to the line type photo-sensor device shown in the embodiment but it is equally applicable to an area type photo-sensor device. Also, in the combination of the photo-sensor device shown in FIG. 1 and the circuits 8, 12 and 10 shown in FIG. 3A, these circuits may be formed integrally with the sensor device as that of so-called on-chip structure. In this case, as the circuits 8, 9 and 10 there are used those of CMOS structure and as the memory condenser C1 in the dark current sampling and holding circuit 9 there is used an electrostatic capacity formed at the junction between silicon semiconductor and printed pattern or its equivalent.
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