Source: http://www.google.com/patents/US7859884?dq=6,272,646
Timestamp: 2016-02-11 17:20:51
Document Index: 392408322

Matched Legal Cases: ['Application No. 200680006301', 'Application No. 2007', 'Application No. 10', 'Application No. 7018952', 'Application No. 2007', 'Application No. 200680006301', 'Application No. 10', 'Application No. 7018952']

Patent US7859884 - Structure and method for biasing phase change memory array for reliable writing - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected...http://www.google.com/patents/US7859884?utm_source=gb-gplus-sharePatent US7859884 - Structure and method for biasing phase change memory array for reliable writingAdvanced Patent SearchPublication numberUS7859884 B2Publication typeGrantApplication numberUS 11/930,620Publication dateDec 28, 2010Filing dateOct 31, 2007Priority dateJan 19, 2005Fee statusPaidAlso published asCN101189679A, CN101189679B, EP1846954A2, EP1846954A4, US7307268, US8102698, US8385141, US8576609, US20060157679, US20080130352, US20110110149, US20110310662, US20130135925, WO2006078506A2, WO2006078506A3Publication number11930620, 930620, US 7859884 B2, US 7859884B2, US-B2-7859884, US7859884 B2, US7859884B2InventorsRoy E. ScheuerleinOriginal AssigneeSandisk 3D LlcExport CitationBiBTeX, EndNote, RefManPatent Citations (32), Non-Patent Citations (23), Referenced by (61), Classifications (21), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetStructure and method for biasing phase change memory array for reliable writing
US 7859884 B2Abstract
providing a plurality of memory cells in the non-volatile memory array, each of the memory cells comprising a reversibly switchable material formed in series with a dielectric material, a non-ohmic element and a resistive heater,
supplying a first programming current to a first memory cell, wherein the first programming current is generated by a programmable control circuit and applied at an intermediate level for a long duration such that the first memory cell is programmed into a set state; and
supplying a second programming current to a second memory cell, wherein the second programming current is generated by the programmable control circuit and applied at a high level for a short duration such that the second memory cell is programmed into a reset state, supplying of said second programming current simultaneous with supplying of said first programming current.
6. A method of programming a memory chip, the method comprising:
providing a first programming pulse to a first memory cell, said first programming pulse comprising a current amplitude sufficient to program said first memory cell into a set state, said first programming pulse is generated using a self-timed programmable pulse width control circuit, said first memory cell comprising a switchable memory material in series with an anti-fuse and a diode; and
providing a second programming pulse to a second memory cell, said second programming pulse comprising a current amplitude sufficient to program said second memory cell into a reset state, said second memory cell comprising a switchable memory material in series with an anti-fuse and a diode, said second programming pulse overlapping in time with said first programming pulse.
14. A method of writing two-terminal non-volatile memory cells, the method comprising:
programming a first memory cell into a set state using a first programming pulse, said first memory cell comprising a dielectric layer in series with a phase change material and a non-ohmic conductive device, said first programmable pulse is generated using a programmable pulse width control circuit, wherein said programmable pulse width circuit and said first memory cell share a semiconductor substrate; and
programming a second memory cell into a reset state using a second programming pulse, said second memory cell comprising a dielectric layer in series with a phase change material and a non-ohmic conductive device, wherein said first memory cell and said second memory cell are programmed simultaneously.
Referring to FIG. 4 a, bottom conductor or input terminal 20 is formed of a conductive material, for example a refractory metal or refractory metal compound such as tungsten or titanium tungsten. In this exemplary cell, bottom conductor 20 is in the form of a rail. As shown in FIG. 4 a, barrier layer 43 of, for example, titanium nitride may be used between diode 42 and state change element 23. This memory cell contacts an output terminal 21 in the form of a rail-shaped top conductor. Top conductor 21 is preferably perpendicular to bottom conductor 20. In one embodiment shown in FIG. 2 of concurrently filed U.S. application Ser. No. 11/040,255, to Scheuerlein et al, entitled “A Non-Volatile Memory Cell Comprising a Dielectric Layer and a Phase Change Material in Series” (incorporated herein by reference), the rail shaped conductor 21 is a multilayer structure including a layer of barrier material such as TiN and a layer of phase change material.
FIG. 4 c shows yet another alternative memory cell structure in which the state change material 23 rather than the heater material 44 has been narrowed for more efficient heating to achieve state change. Such a structure may be achieved by forming a narrow post of sacrificial material, filling and planarizing around the narrow sacrificial post, and removing the sacrificial post to expose heater element 44, and applying the state change material 23, which then contacts heater element 44 in a narrow region. The structure of FIG. 4 c is also discussed in detail in the above mentioned patent application to Scheuerlein, Ser. No. 11/040,465, entitled “A Non-Volatile Phase Change Memory Cell Having a Reduced Thermal Contact Area” and incorporated herein by reference. See particularly the discussion of FIGS. 3 a-3 e of that application.
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