Source: http://www.google.com/patents/US6461899?dq=7,446,777
Timestamp: 2014-03-10 06:39:00
Document Index: 686795163

Matched Legal Cases: ['application No. 10', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 7', 'application No. 7', 'application No. 8']

Patent US6461899 - Oxynitride laminate �blocking layer� for thin film semiconductor devices - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsChannel doping is an effective method for controlling Vth, but if Vth shifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope....http://www.google.com/patents/US6461899?utm_source=gb-gplus-sharePatent US6461899 - Oxynitride laminate �blocking layer� for thin film semiconductor devicesAdvanced Patent SearchPublication numberUS6461899 B1Publication typeGrantApplication numberUS 09/558,736Publication dateOct 8, 2002Filing dateApr 26, 2000Priority dateApr 30, 1999Fee statusPaidAlso published asUS6940124, US7456474, US7855416, US20030100150, US20050247934, US20090224255Publication number09558736, 558736, US 6461899 B1, US 6461899B1, US-B1-6461899, US6461899 B1, US6461899B1InventorsHidehito Kitakado, Masahiko Hayakawa, Shunpei Yamazaki, Taketomi AsamiOriginal AssigneeSemiconductor Energy Laboratory, Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (25), Non-Patent Citations (18), Referenced by (73), Classifications (23), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetOxynitride laminate �blocking layer� for thin film semiconductor devicesUS 6461899 B1Abstract Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B)manufactured from SiH4and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.
What is claimed is: 1. A semiconductor device including at least one thin film transistor formed over a substrate, said semiconductor device comprising:
a first silicon oxynitride film (A) formed on said substrate; a second silicon oxynitride film (B) formed on said silicon oxynitride film (A); and a semiconductor layer formed on the silicon oxynitride film (B), wherein a composition ratio of nitrogen, with respect to oxygen, in the silicon oxynitride film (A) is more than or equal to 0.6, and is less than or equal to 1.5; and a composition ratio of nitrogen, with respect to oxygen, in the silicon oxynitride film (B) is more than or equal to 0.01, and is less than or equal to 0.4. 2. A semiconductor device having at least one thin film transistor formed over a substrate, comprising:
a first silicon oxynitride film (A) formed on the substrate; a second silicon oxynitride film (B) formed on the first silicon oxynitride film (A); and a semiconductor layer formed on the silicon oxynitride film (B); wherein an oxygen concentration of the silicon oxynitride film (A) is more than or equal to 20 atomic %, and less than or equal to 30 atomic %; and a nitrogen concentration of the silicon oxynitride film (A) is more than or equal to 20 atomic %, and less than or equal to 30 atomic %; an oxygen concentration of the silicon oxynitride film (B) is more than or equal to 55 atomic %, and less than or equal to 65 atomic %; and a nitrogen concentration of the silicon oxynitride film (B) is more than or equal to 1 atomic %, and less than or equal to 20 atomic %. 3. The semiconductor device according to claim 1 or 2, wherein the thickness of a gate insulating film of the thin film transistor is from 40 to 150 nm and a thickness of a channel forming region of the semiconductor layer is from 25 to 80 nm, and the thin film transistor has an S value of more than or equal to 0. 10 V/dec, and less than or equal to 0.30 V/dec.
4. The semiconductor device according to claim 1 or 2, wherein a gate electrode of the thin film transistor comprises a first conducting layer (A) comprising a material selected from the group consisting of tantalum nitride, tungsten nitride, titanium nitride, and molybdenum nitride; and a second conducting layer (B) comprising one or more materials selected from the group consisting of tantalum, tungsten, titanium, and molybdenum.
5. The semiconductor device according to claim 1 or 2, wherein a gate electrode of the thin film transistor comprises a conducting layer (B) comprising one or more materials selected from the group consisting of tantalum, tungsten, titanium, and molybdenum.
6. A semiconductor device having a pixel TFT formed over a pixel portion of a substrate, and an n-type TFT and a p-type TFT of a driver circuit formed over said substrate, comprising:
a first silicon oxynitride film (A) formed on the substrate; a second silicon oxynitride film (B) formed on the first silicon oxynitride film (A); the pixel TFT formed on the silicon oxynitride film (B); and the n-type TFT and p-type TFT of the driver circuit, wherein a composition ratio of nitrogen, with respect to oxygen, in the silicon oxynitride film (A) is more than or equal to 0.6, and is less than or equal to 1.5; and a composition ratio of nitrogen, with respect to oxygen, in the silicon oxynitride film (B) is more than or equal to 0.01, and is less than or equal to 0.4. 7. A semiconductor device having a pixel TFT formed over a pixel portion of a substrate, and an n-type TFT and a p-type TFT of a driver circuit formed over said substrate, comprising:
a first silicon oxynitride film (A) formed on the substrate; a second silicon oxynitride film (B) formed on the silicon oxynitride film (A); the pixel TFT formed on the silicon oxynitride film (B), and the n-type TFT and p-type TFT of the driver circuit; wherein an oxygen concentration of the silicon oxynitride film(A) is more than or equal to 20 atomic %, and less than or equal to 30 atomic %; a nitrogen concentration of the silicon oxynitride film (A) is more than or equal to 20 atomic %, and less than or equal to 30 atomic %; an oxygen concentration of the silicon oxynitride film (B) is more than or equal to 55 atomic %, and less than or equal to 65 atomic %; and a nitrogen concentration of the silicon oxynitride film (B) is more than or equal to 1 atomic %, and less than or equal to 20 atomic %. 8. The semiconductor device according to claim 6 or 7, wherein a thickness of a gate insulating film of the pixel TFT is from 40 to 150 nm, a thickness of the semiconductor layer of a channel forming region is from 25 to 80 nm, and the pixel TFT has an S value of more than or equal to 0.10 V/dec, and less than or equal to 0.30 V/dec.
9. The semiconductor device according to claim 6 or 7, wherein a thickness of a gate insulating film of the pixel TFT is from 40 to 150 nm; a thickness of the semiconductor layer of a channel forming region is from 25 to 80 nm; and a threshold voltage of the pixel TFT is more than or equal to 0.5 V, and less than or equal to 2.5 V.
10. The semiconductor device according to claim 6 or 7, wherein a thickness of a gate insulating film of the pixel TFT is from 40 to 150 nm; a thickness of the semiconductor layer of a channel forming region is from 25 to 80 nm; and an electric field effect mobility of the pixel TFT is more than or equal to 120-cm2/V�sec, and less than or equal to 250-cm2/V�sec.
11. The semiconductor device according to claim 6 or 7 wherein a thickness of a gate insulating film of the n-type TFT and the p-type TFT of the driver circuit is from 40 to 150 nm; a thickness of the semiconductor layer of a channel forming region of the n-type TFT and p-type TFT is from 25 to 80 nm; and the n-type TFT and the p-type TFT of the driver circuit have an S value of more than or equal to 0.10 V/dec, and less than or equal to 0.30 V/dec.
12. The semiconductor device according claim 6 or 7 wherein a thickness of a gate insulating film of the n-type TFT and the p-type TFT of the driver circuit is from 40 to 150 nm; a thickness of the semiconductor layer of a channel forming region of the n-type TFT and the p-type TFT is from 25 to 80 nm; a threshold voltage of the n-type TFT of the driver circuit is more than or equal to 0.5 V, and less than or equal to 2.5 V; and a threshold voltage of the p-type TFT of the driver circuit is more than or equal to −2.5 V, and less than or equal to −0.5 V.
13. The semiconductor device according to claim 6 or 7 wherein a thickness of a gate insulating film of the n-type TFT and the p-type TFT of the driver circuit is from 40 to 150 nm; a thickness of the semiconductor layer of a channel forming region of the n-type TFT and the p-type TFT is from 25 to 80 nm; an electric field effect mobility of the n-channel TFT of the driver circuit is more than or equal to 120 cm2/V�sec, and less than or equal to 250 cm2/V�sec; and an electric field effect mobility of the P-channel TFT of the driver circuit is more than or equal to 80 cm2/V�sec, and less than or equal to 150 cm2/V�sec.
14. The semiconductor device of claim 6 or 7 wherein a gate electrode of the pixel TFT, a gate electrode of the n-channel TFT, and a gate electrode of the P-channel TFT, each has a conducting layer (A) comprising a material selected from the group consisting of tantalum nitride, tungsten nitride, titanium nitride, and molybdenum nitride; and a conducting layer (B) comprising one or more materials selected from the group consisting of tantalum, tungsten, titanium, and molybdenum.
15. The semiconductor device of claim 6 or 7, wherein a gate electrode of the pixel TFT, a gate electrode of the n-channel TFT, and a gate electrode of the P-channel TFT, each has a conducting layer (B) comprising one or more materials selected from the group consisting of tantalum, tungsten, titanium, and molybdenum.
16. The semiconductor device of claim 1, 2, 6 or 7, wherein a composition ratio of hydrogen, with respect to oxygen, in the silicon oxynitride film (A) is more than or equal to 0.3, and is less than or equal to 1.5; and a composition ratio of hydrogen, with respect to oxygen, in the silicon oxynitride film (B) is more than or equal to 0.001, and is less than or equal to 0.15.
17. The semiconductor device of claim 1, 2, 6 or 7 wherein a hydrogen concentration of the silicon oxynitride film (A) is more than or equal to 10 atomic %, and less than or equal to 20 atomic %; and a hydrogen concentration of the silicon oxynitride film (B) is more than or equal to 0.1 atomic %, and less than or equal to 10 atomic %.
18. The semiconductor device of claim 1, 2, 6 or 7 wherein the silicon oxynitride film (A) has a density of more than or equal to 8�1022 atoms/cm3, and less than or equal to 2�1023 atoms/cm3; and the silicon oxynitride film (B) has a density of more than or equal to 6�1022 atoms/cm3 1, and less than or equal to 9�1022 atoms/cm3.
19. The semiconductor device according to claim 1, 2, 6 or 7 wherein an etching rate of the silicon oxynitride film (A) by a mixed aqueous solution of 7.13% ammonium hydrogen fluoride (NH4HF2) and 15.4% ammonium fluoride (NH4F) at 20� C. is more than or equal to 40 nm/min, and less than or equal to 70 nm/min; and an etching rate of the silicon oxynitride film (B) by a mixed aqueous solution of 7.13% ammonium hydrogen fluoride (NH4HF2) and 15.4% ammonium fluoride (NH4F) at 20� C. is more than or equal to 90 nm/min, and less than or equal to 130 nm/min.
20. The semiconductor device according to claim 1, 2, 6 or 7 wherein a thickness of the silicon oxynitride film (A) is more than or equal to 10 nm, and less than or equal to 150 nm; and a thickness of the silicon oxynitride film (B) is more than or equal to 10 nm, and less than or equal to 250 nm.
21. The semiconductor device according to claim 1, 2, 6 or 7 wherein the semiconductor device is selected from the group consisting o a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, and an electronic amusement device.
22. A method of manufacturing a semiconductor device having a TFT formed over a substrate, comprising:
forming a first silicon oxynitride film (A) on the substrate; forming a second silicon oxynitride film (B) on the silicon oxynitride film (A); forming a semiconductor layer on the silicon oxynitride film (B); forming a gate insulating film on the semiconductor layer; and forming a gate electrode on the gate insulating film; wherein a composition ratio of nitrogen, with respect to oxygen, in the silicon oxynitride film (A) is more than or equal to 0.6, and is less than or equal to 1.5; and a composition ratio of nitrogen, with respect to oxygen, in the silicon oxynitride film (B) is more than or equal to 0.01, and is less than or equal to 0.4. 23. A method of manufacturing a semiconductor device having a TFT formed over a substrate, comprising:
forming a silicon oxynitride film (A) on the substrate; forming a silicon oxynitride film (B) on the silicon oxynitride film (A); forming a semiconductor layer on the silicon oxynitride film (B); forming a gate insulating film on the semiconductor layer; and forming a gate electrode on the gate insulating film; wherein an oxygen concentration of the silicon oxynitride film (A) is more than or equal to 20 atomic %, and less than or equal to 30 atomic %; and a nitrogen concentration of the silicon oxynitride film (A) is more than or equal to 20 atomic %, and less than or equal to 30 atomic %; an oxygen concentration of the silicon oxynitride film (B) is more than or equal to 55 atomic %, and less than or equal to 65 atomic %; and a nitrogen concentration of the silicon oxynitride film (B) is more than or equal to 1 atomic %, and less than or equal to 20 atomic %. 24. The method of manufacturing a semiconductor device according to claim 22 or 23, wherein the gate electrode has a conducting layer (A) comprising a material selected from the group consisting of tantalum nitride, tungsten nitride, titanium nitride, and molybdenum nitride; and a conducting layer (B) comprising one or more materials selected from the group consisting of tantalum, tungsten, titanium, and molybdenum.
25. The method of manufacturing a semiconductor device according to claim 22 or 23, wherein the gate electrode is formed from a conducting layer (B) comprising one or more elements selected from among the group consisting of tantalum, tungsten, titanium, and molybdenum.
26. The method of manufacturing a semiconductor device according to claim 24, wherein thermal annealing is performed at a temperature of more than or equal to 500� C. and less than or equal to 700� C. after forming the gate electrode.
27. A method of manufacturing a semiconductor device having a pixel TFT formed over a pixel portion of a substrate, and an n-channel TFT and a p-channel TFT of a driver circuit formed over said substrate, said method comprising the steps of:
forming a silicon oxynitride film (A) on the substrate; forming a silicon oxynitride film (B) on the silicon oxynitride film (A); and forming the pixel TFT, and the n-channel TFT and the P-channel TFT of the driver circuit, on the silicon oxynitride film (B); wherein a composition ratio of nitrogen, with respect to oxygen, in the silicon oxynitride film (A) is more than or equal to 0.6, and at less than or equal to 1.5; and a composition ratio of nitrogen, with respect to oxygen, in the silicon oxynitride film (B) is more than or equal to 0.01, and at less than or equal to 0.4. 28. A method of manufacturing a semiconductor device having a pixel TFT formed over a pixel portion of a substrate, and an n-channel TFT and a p-channel TFT of a driver circuit formed over said substrate, said method comprising the steps of:
forming a silicon oxynitride film (A) on the substrate; forming a silicon oxynitride film (B) on the silicon oxynitride film (A); forming the pixel TFT, and the n-channel TFT and the P-channel TFT of the driver circuit, on the silicon oxynitride film (B); wherein: the oxygen concentration of the silicon oxynitride film (A) is more than or equal to 20 atomic %, and at less than or equal to 30 atomic %; the nitrogen concentration of the silicon oxynitride film (A) is more than or equal to 20 atomic %, and at less than or equal to 30 atomic %; the oxygen concentration of the silicon oxynitride film (B) is more than or equal to 55 atomic %, and at less than or equal to 65 atomic %; and the nitrogen concentration of the silicon oxynitride film (B) is more than or equal to 1 atomic %, and at less than or equal to 20 atomic %. 29. The method of manufacturing a semiconductor device according to claim 27 or 28, wherein the gate electrode of the pixel TFT, the gate electrode of the n-channel TFT, and the gate electrode of the P-channel TFT, are each formed from a conducting layer (A) comprising a material selected from the group consisting of tantalum nitride, tungsten nitride, titaniumnitride, and molybdenum nitride; and from a conducting layer (B) comprising one or more elements selected from among the group consisting of tantalum, tungsten, titanium, and molybdenum.
30. The method of manufacturing a semiconductor device according to claim 27 or 28, wherein the gate electrode of the pixel TFT, the gate electrode of the n-channel TFT, and a gate electrode of the P-channel TFT, are each formed from a conducting layer (B) comprising one or more elements selected from among the group consisting of tantalum, tungsten, titanium, and molybdenum.
31. The method of manufacturing a semiconductor device according to claim 29, wherein thermal annealing is performed at a temperature of more than or equal to 500� C., and less than or equal to 700� C., after forming the gate electrode.
32. The method of manufacturing a semiconductor device according to claim 22, 23, 27 or 28, wherein the composition ratio of hydrogen, with respect to oxygen, in the silicon oxynitride film (A) is formed at more than or equal to 0.3, and at less than or equal to 1.5; and
the composition ratio of hydrogen, with respect to oxygen, in the silicon oxynitride film (B) is formed at more than or equal to 0.001, and at less than or equal to 0.15. 33. The method of manufacturing a semiconductor device according to claim 22, 23, 27 or 28, wherein the hydrogen concentration of the silicon oxynitride film (A) is formed at more than or equal to 10 atomic %, and at less than or equal to 20 atomic %; and
the hydrogen concentration of the silicon oxynitride film (B) is formed at more than or equal to 0.1 atomic %, and at less than or equal to 10 atomic %. 34. The method of manufacturing a semiconductor device according to claim 22, 23, 27 or 28, wherein the silicon oxynitride film (A) is formed at a density of more than or equal to 8�1022 atoms/cm3, and at less than or equal to 2�1023 atoms/cm3; and
the silicon oxynitride film (B) is formed at a density of more than or equal to 6�1022 atoms/cm3, and at less than or equal to 9�1022 atoms/cm3. 35. The method of manufacturing a semiconductor device according to claim 22, 23, 27 or 28, wherein the etching rate of the silicon oxynitride film (A) by a mixed aqueous solution of 7.13% ammonium hydrogen fluoride (NH4HF2) and 15.4% ammonium fluoride (NH4F) at 20� C. is formed at more than or equal to 40 nm/min, and at less than or equal to 70 nm/min; and
the etching rate of the silicon oxynitride film (B) by a mixed aqueous solution of 7.13% ammonium hydrogen fluoride (NH4HF2) and 15.4% ammonium fluoride (NH4F) at 20� C. is formed at more than or equal to 90 nm/min, and at less than or equal to 130 nm/min. 36. The method of manufacturing a semiconductor device according to claim 22, 23, 27 or 28, wherein the thickness of the silicon oxynitride film (A) is formed at more than or equal to 10 nm, and less than or equal to 150 nm; and
the thickness of the silicon oxynitride film (B) is formed at more than or equal to 10 nm, and less than or equal to 250 nm. 37. The method of manufacturing a semiconductor device according to claim 22, 23, 27 or 28, wherein the semiconductor device is selected from the group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, and an electronic amusement device.
38. The method of manufacturing a semiconductor device according to claim 25, wherein thermal annealing is performed at a temperature of more than or equal to 500� C. and less than or equal to 700� C., after forming the gate electrode.
39. The method of manufacturing a semiconductor device according to claim 30, wherein thermal annealing is performed at a temperature of more than or equal to 500� C., and less than or equal to 700� C., after forming the gate electrode.
TFT characteristics can be shown by typical parameters such as electric field effect mobility and threshold voltage (hereafter abbreviated to Vth). As shown in FIG. 23A in the graph of (drain current)� vs. gate voltage (hereafter abbreviated as Id and Vg, respectively), Vth can be found by extrapolating the straight line region to the Vg axis. Further, the relationship between the drain current and the gate voltage in the neighborhood or below, Vth is referred to as the sub-threshold characteristic, and is an important property for determining the TFT performance as a switching element. A sub-threshold coefficient (hereafter shortened to S value) is used as a constant showing the merit of the sub-threshold characteristic. As shown in FIG. 23B, when the sub-threshold characteristics are plotted on a semi-log graph, the S value is defined as the gate voltage required in order to have a change of one order of magnitude in the drain current. The smaller the S value is, the faster it is possible to operate the TFT, and the lower its power consumption becomes. Furthermore, in a shift register circuit formed in a driver circuit, if the S value is large (if the sub-threshold characteristics are poor), then charge loss occurs due to the leak current, and this causes a fatal operation fault.
In order to control the value of Vth, a method of doping an impurity element that imparts p-type conductivity into a channel forming region of the active layer, at a concentration about 1�1016 and 5�1017atoms/cm3, is employed. This type of measure is referred to as a channel dope, and is important in the manufacture processes of the TFT.
In order to solve the above stated problems, a blocking layer is formed on the back channel side of the TFT from a laminate of a silicon oxynitride film (A) (also called �silicon nitride oxide�) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B) manufactured from SiH4 and N2O. By using this type of laminate silicon oxynitride film structure, contamination by alkaline metallic elements from the substrate can be prevented, and the impact of stress imparted to the TFT caused by internal stress can be relieved.
FIG. 12 is across-sectional view showing a pixel TFT, a storage capacitor, and driver circuit TFTs;
The characteristics of the silicon oxynitride films (A) to (C) thus manufactured are brought together and shown in Table 2. The composition ratios and densities of hydrogen (H), nitrogen (N), oxygen (O) and silicon (Si) found by Rutherford back scattering spectrometry (hereafter abbreviated as RBS; device used is system 3S-R10, accelerator is NEC 3SDH pelletron, and end station is CE&A RBS-400) are shown in Table 2. The densities of N�H bonds and of Si�H bonds found by Fourier transform infrared spectroscopy (hereafter referred to as FT-IR; device used is Nicolet Magna-IR 760) are also shown in Table 2, as are etching speeds at 20� C. in an aqueous solution containing 7.13% ammonium hydrogen fluoride (NH4HF2) and 15.4% ammonium fluoride (NH4F) (manufactured by Stela-chemifa Corp.; under the product name of LAL500), and changes in internal stresses due to thermal annealing. An Ionic System Corp. model 30114 is used as the measurement device for internal stress, and a sample manufactured on a silicon wafer substrate was measured. The internal stresses shown by a+symbol are tensile stresses (a stress transforming the film in the inside direction), and the internal stresses shown by a−symbol are compressive stresses (a stress transforming the film in the outside direction).
Composi-t
8.07 � 109 (−4.26 �
(−2.00 �
7.42 � 1010 (−7.29 �
(−1.30 �
The manufacturing conditions of the silicon oxynitride films are of course not limited to those of Table 1. The silicon oxynitride film (A) may be made by: using SiH4, NH3, and N2O; using a substrate temperature of between 250 and 450� C., a reaction pressure of between 10 and 100 Pa, and a power source frequency of 13.56 MHz or higher; setting the discharge power density from 0.15 to 0.80 W/cm2; making the hydrogen concentration between 10 and 30 atomic %, the nitrogen concentration between 20 and 30 atomic %, the oxygen concentration between 20 and 30 atomic %, and the density from 8�1022 to 2�1023 atoms/cm3;and making the etching speed by the above aqueous solution, containing 7.13% ammonium hydrogen fluoride (NH4HF2) and 15.4% ammonium fluoride (NH4F), between 40 and 70 nm/min. On the other hand, the silicon oxynitride film (B) may be made by: using SiH4 and N2O; using a substrate temperature of between 250 and 450� C., a reaction pressure of between 10 and 100 Pa, and a power source frequency of 13.56MHz or higher; setting the discharge power density from 0.15 to 0.80 W/cm2; making the hydrogen concentration between 0.1 and 10 atomic %, the nitrogen concentration between 1 and 20 atomic %, the oxygen concentration between 55 and 65 atomic %, and the density from 6�1022 to 9�1022 atoms/cm3; and making the etching speed by the above aqueous solution, containing 7.13% ammonium hydrogen fluoride (NH4HF2) and 15.4% ammonium fluoride (NH4F), between 90 and 130 nm/min.
In addition, solid state lasers such as a YAG laser, a YVO4 laser, a YAlO3 laser, and a YLF laser can also be used. The second harmonic (532nm), the third harmonic (355nm), and the fourth harmonic (266 nm) of these solid state lasers is used rather than the base wavelength of 1064 nm. Heating and crystallization can be performed by the penetration length of the light. Heating is from the surface and from the interior of the semiconductor layer when the second harmonic (532 nm) is used, and is from the surface of the semiconductor layer when the third harmonic (355 nm) or the fourth harmonic (266 nm) is used, similar to an excimer laser.
For the case of thermal annealing, annealing is performed in a nitrogen atmosphere at a temperature about 600 to 660� C. using an annealing furnace. Which ever method is used, realignment of atoms occurs during crystallization of the amorphous semiconductor layer, making it fine and minute, and the thickness of the crystalline semiconductor layer manufactured is reduced about between 1 and 15% from the thickness of the original amorphous semiconductor layer (55 nm in embodiment mode 1).
A conducting layer is formed on the gate insulating film in order to form a gate electrode. A single layer may be formed for this conducting layer, but a laminate structure of two layers or three layers can also be formed when necessary. In embodiment mode 1, a conducting layer (A) 111 made from a conducting metallic nitride film and a conducting layer (B) 112 made from a metallic film are laminated. The conducting layer (B) 112 maybe formed from an element selected from the group consisting of tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), or from an alloy having one of these element as its principal constituent, or from an alloy film of a combination of these elements (typically a Mo�W film or a Mo�Ta film). The conducting layer (A) 111 is formed from tantalum nitride (TaN), tungsten nitride (WN), titaniumnitride (TiN) ormolybdenum nitride (MoN). Further, tungsten silicide, titanium silicide, or molybdenum silicide may be applied for the conducting layer (A) 111. The concentration of contained impurities may be reduced in order to be able to make the resistance of the conducting layer (B) 112 lower, and in particular, it is good to reduce the oxygen concentration to 30 ppm or less. For example, by reducing the oxygen concentration of tungsten (w) to 300 ppm or less, a resistivity value of 20 μΩcm or less can be realized with tungsten (W).
<p+doping process: FIG. 2C>
Next formation of an impurity region 118 which forms a source region or a drain region of the n-channel TFT is performed. Ion doping using phosphine (PH3) is performed here, and the phosphorous (P) concentration is set to between 1�1020 and 1�1021 atoms/cm3 in this region. The concentration of the impurity element for imparting n-type conductivity contained in the:impurity region 118 is referred to as (n+) throughout this specification. Phosphorous (P) is similarly added to the impurity region 117, but compared to the concentration of boron (B) already added by the previous step, the concentration of phosphorous (P) added to the impurity region 117 is about one-third to one-half of that of boron, and therefore the p-type conductivity is ensured and no influence is imparted to the TFT characteristics.
FIG. 3 is a view showing-the relationship between the S value and Vshift for an n-channel TFT without channel doping, with the film thickness of each blocking layer taken as a parameter. As shown in FIG. 23C, Vshift is defined as the voltage value at the intersection of: a line tangent to the largest slope in the sub-threshold characteristic of the drain current (Id) VS. the gate voltage (Vg); and the horizontal line Id=1�10−12 A. The smaller the Vshift the better, and ideally Vshift=0 V. With the data shown in FIG. 3, a clear correlation is seen between the S value and the Vshift. It is clear that the closer that Vshift approaches 0 V, the smaller that the S value becomes, and the TFT characteristics approach an ideal state.
FIG. 6 shows the results of measuring the contamination prevention effect by alkaline metal elements in the blocking layer 102, using secondary ion mass spectroscopy (SIMS). The device used for the measurements was Model 6600 produced by Physical Electronics Corp., and the test piece is as follows: first, a silicon oxynitride film (A) with a 50 nm thickness is formed adhering to a glass substrate, a silicon oxynitride film (B) of 125 nm thickness is formed thereon, and an additional silicon film with a thickness of 50 nm is formed. This is processed at the crystallization temperature by thermal annealing using an annealing furnace, (processed at 500� C. for 1 hour, followed by 4 hours at 550� C. ). The data of FIG. 6 shows the distributions of silicon (Si), oxygen (O), and nitrogen (N) by the strength of secondary ions, and the distribution of sodium (Na) with respect to those distributions is determined and shown. The results show that diffusion or exudations from the glass substrate to the silicon oxynitride film (A) were not detected, and it could be verified that even a silicon oxynitride film (A) of 50 nm thickness has a sufficient effect as a blocking layer.
FIG. 7 shows the changes of Vshift with respect to the changes in internal stress of the blocking layer before and after processing at the above crystallization temperature. The combination of film thickness of the silicon oxynitride film (A) and the silicon oxynitride film (B) was investigated, and it become clear that the smaller the amount of change in internal stress, the smaller Vshiftbecomes.
A semiconductor film 203 a having an amorphous structure is formed next, with a thickness of between 25 and 80 nm (preferably between 30 and 60nm), by a known method such as plasma CVD or sputtering. In embodiment 1, an amorphous silicon film is formed to have a thickness of 55 nm by plasma CVD. Amorphous semiconductor films and microcrystalline semiconductor films exist as semiconductor films having an amorphous structure, and compound semiconductor films having an amorphous structure, such as an amorphous silicon germanium film, are also suitable. Further, the blocking layer 202 and the amorphous semiconductor layer 203 a may both be formed successively, because a same method is applied to both layers. By not exposing the surface to the atmosphere after forming the base film, it becomes possible to prevent contamination of the surface, and dispersion in the characteristics of the manufactured TFT, and fluctuations in the threshold voltage, can be reduced. (See FIG. 8A.)
The crystalline silicon film 203 b is then etched and divided into island-shapes, forming island-shape semiconductor layers 204 to 207, which are made into active layers. A mask layer 208 is then formed by plasma CVD, reduced pressure CVD, or sputtering to a thickness of between 50 and 100 nm. For example, a silicon oxide film is formed by reduced pressure CVD using a mixed gas of SiH4 and O2 and heated to 400� C. at a pressure of 266 Pa. (See FIG. 8C.) Channel doping is then performed. A photoresist mask 209 is formed first, and boron (B) is added as an impurity element that imparts p-type conductivity to the entire surface of the island-shape semiconductor layers 205 to 207, at a concentration about 1�1016 to 5�1017atoms/cm3, with the aim of controlling the threshold voltage. Ion doping may be used for the addition of boron (B), and boron (B) can be added at the same time as the amorphous silicon film is formed. It is not always necessary to add boron (B) here, but it is preferable to form semiconductor layers 210 to 212 with added boron in order to place the threshold voltage of the n-channel TFT within a predetermined range. The method shown by embodiment mode 2 or embodiment mode 3 may also be used for this channel doping process. (See FIG. 8D.)
Next, in order to form a source region and a drain region of the P-channel TFT of the driver circuit, a process of adding an impurity element that imparts p-type conductivity is performed. Impurity regions are formed in a self-aligning manner here with the gate electrode 228 as a mask. The region in which the n-channel TFT is formed is covered with a photoresist mask 233. An impurity region (p+) 234 at a concentration of 1�1021 atoms/cm3is then formed by ion doping using diborane (B2H6). (See FIG. 10A.)
Formation of impurity regions for functioning as a source region or a drain region of the n-channel TFT is performed next. Resist masks 235 to 237 are formed, and an impurity element that imparts n-type conductivity is added, forming impurity regions 238 to 242. This is performed by ion doping using phosphine (PH3), and the concentration of the impurity regions (n+) 238 to 242 is set to 5�1020 atoms/cm3. Boron (B),is already contained in the impurity region 238 in a previous step, but in comparison, phosphorous (P) is added with a concentration of one-third to one-half that of the boron (B), and therefore the influence of phosphorous (P) need not be considered, and there is no influence imparted to the characteristics of the TFT. (See FIG. 10B.)
A process of adding an impurity that imparts n-type conductivity is then performed in order to form an LDD region of the n-channel TFT of the pixel portion. An impurity element that imparts n-type conductivity is added by ion doping in a self-aligning manner using the gate electrode 231 as a mask. The concentration of phosphorous (P) added is set to 5�1016 atoms/cm3, and this is a lower concentration than that of the impurity elements added by the steps of FIG. 9A, FIG. 10A, and FIG. 10B, and in practice only impurity regions (n ) 243 and 244 are formed. (See FIG. 10C.)
Through thermal annealing, the Ta films 228 b to 232 b forming the gate electrodes 228 to 231, and the capacitor wiring 232, have conducting films (C) 228 c to 232 c, made from TaN, formed in their surfaces to a thickness of 5 to 80nm. In addition, when the conducting layers (B) 228 b to 232 b are tungsten (W), tungsten nitride (WN) is formed, and titanium nitride (TiN) can be formed when the conducting layers are titanium (Ti). Further, these can be formed similarly by exposing the gate electrodes 228 to 231 to a plasma atmosphere containing nitrogen using a substance such as nitrogen or ammonia. In addition, a process of hydrogenation of the island-shape semiconductor layers is performed by thermal annealing at 300 to 450� C. for between 1 and 12 hours in an atmosphere containing between 3 and 100% hydrogen. This process is the one of terminating dangling bonds in the semiconductor layers by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by a plasma) may be performed as another means of hydrogenation.
Next, a silicon nitride film, a silicon oxide film or a silicon oxynitride film with a thickness of between 50 and 500 nm (typically between 100 and 300 nm) is formed as a passivation film 259. If hydrogenation processing is performed in this state, then the desirable result as to the improvement of TFT characteristics can be obtained. For example, it is good to perform heat treatment for between 1 and 12 hours at 300 to 450� C. in an atmosphere of 3 to 100% hydrogen, and a similar effect can be obtained by using plasma hydrogenation. Note that openings may be formed in the passivation film 259 in positions in which contact holes for connecting to the pixel electrode, and to the drain wiring, will later be formed. (See FIG. 1C.)
Embodiment 2 In embodiment 2, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate of embodiment 1 is explained. As shown in FIG. 18, an alignment film 601 is formed for the active matrix substrate in the state of FIG. 12. A polyimide resin is often used for the alignment film of a liquid crystal display device. A light shielding film 603, a transparent conducting film 604, and an alignment film 605 are formed on an opposing substrate 602. After forming the alignment films, a rubbing process is performed to give the liquid crystal molecules a certain fixed pre-tilt angle, bringing them into alignment. The active matrix substrate, on which the pixel matrix circuit and the CMOS circuit are formed, and the opposing substrate are then joined together by a sealing material or spacers (both not shown in the figures)in accordance with a known cell construction process. Next, a liquid crystal material 606 is injected between both substrates, and the cell is completely sealed by a sealant (not shown in the figures). A known liquid crystal material may be used as the liquid crystal material. Thus the active matrix liquid crystal display device shown in FIG. 18 is completed.
In addition, the wiring 16 is electrically connected to the FPC 17 through the gap (filled by the sealant 81) between the sealant material 19 and the. substrate 10. Note that an explanation of the wiring 16 has been made here, and that the wirings 14 and 15 are also connected electrically to the FPC 17 by similarly passing underneath the sealing material 19.
Reference numeral 43 denotes a pixel electrode (EL element cathode) from a conducting film with high reflectivity, and is electrically connected to the drain of the current control TFT 2403. It is preferable to use a low resistance conducting film, such as an aluminum alloy film, a copper alloy film, and a silver alloy film, or a laminate of such films, as the pixel electrode 43. A laminate structure with other conducting films may also be used, of course. Further, a light emitting layer 45 is formed in the middle of the groove (corresponding to the pixel) formed by banks 44 a and 44 b formed by insulating films (preferably resins). Note that only one pixel is shown in the figures here, but the light emitting layer may be divided to correspond to each of the colors R (red), G (green), and B (blue). A conjugate polymer material is used as an organic EL material. Polyparaphenylene vinylenes (PPVs), polyvinyl carbazoles (PVCS), and polyfluoranes can be given as typical polymer materials. Note that there are several types of PPV organic EL materials, and the materials recorded in Shenk, H., Becker, H., Gelsen, O., Kluge, E., Kreuder, W., and Spreitzer, H., Gelsen, O, Polymers for Light Emitting Diodes ,Euro Display Proceedings, 1999, pp. 33-7, and in Japanese Patent Application Laid-open No. Hei 10-92576, for example, may be used.
Embodiment 6 Examples of cases in which the pixel structure differs from that of the circuit view shown in FIG. 28B are shown in embodiment 6 with FIGS. 29A to 29C. Note that in embodiment 6, reference numeral 2701 denotes a source wiring of a switching TFT 2702, reference numeral 2703 denotes agate wiring of the switching TFT 2702, reference numeral 2704 denotes a current control TFT, 2705 denotes a capacitor, 2706 and 2708 denote electric current supply lines, and 2707 denotes an EL element.
Further, FIG. 29B is an example of a case in which the electric current supply line 2708 is formed parallel to the gate wiring 2703. Note that in FIG. 29B, the structure is formed such that the electric current supply line 2708 and the gate wiring 2703 do not overlap, but, provided that both are wirings formed on different layers, they can be formed to overlap through an insulating. film. In this case, the exclusive surface area can be shared, and the pixel portion can be made even more high definition by the electric current supply line 2708 and the gate wiring 2703.
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INTEREST;ASSIGNORS:KITAKADO, HIDEHITO;HAYAKAWA, HASAHIKO;YAMAZAKI, SHUNPEI;AND OTHERS;REEL/FRAME:011080/0238;SIGNING DATES FROM 20000807 TO 20000822Owner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. 398, HASRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google