Source: http://www.google.com/patents/US4528683?dq=7,013,345/
Timestamp: 2016-02-11 02:36:00
Document Index: 493607888

Matched Legal Cases: ['art 21', 'art 28', 'art 22', 'art 22', 'arts 21', 'art 21', 'art 28', 'art 22', 'art 21', 'art 21', 'art 21', 'art 21', 'art 22', 'art 21']

Patent US4528683 - Circuit for storing a multi-digit decimal numerical value of the distance ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA circuit for storing a multi-digit decimal numerical value of the distance traversed by a vehicle having a signal transmitter which gives off electric counting pulses, and particularly an electronic tachometer. The improvement consists of the numerical value being able to be stored by means for coding...http://www.google.com/patents/US4528683?utm_source=gb-gplus-sharePatent US4528683 - Circuit for storing a multi-digit decimal numerical value of the distance traversed by a vehicleAdvanced Patent SearchPublication numberUS4528683 APublication typeGrantApplication numberUS 06/381,674Publication dateJul 9, 1985Filing dateMay 25, 1982Priority dateJun 15, 1981Fee statusLapsedAlso published asDE3123654A1, DE3123654C2, EP0067925A2, EP0067925A3, EP0067925B1Publication number06381674, 381674, US 4528683 A, US 4528683A, US-A-4528683, US4528683 A, US4528683AInventorsPeter HenryOriginal AssigneeVdo Adolf Schindling AgExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Non-Patent Citations (2), Referenced by (28), Classifications (9), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetCircuit for storing a multi-digit decimal numerical value of the distance traversed by a vehicle
US 4528683 AAbstract
A circuit for storing a multi-digit decimal numerical value of the distance traversed by a vehicle having a signal transmitter which gives off electric counting pulses, and particularly an electronic tachometer. The improvement consists of the numerical value being able to be stored by means for coding the numerical value in a one-step code for a non-volatile storage formed of floating-gate storage cells.
1. In a circuit for storing a multi-digit decimal numerical value of the distance traversed by a vehicle having a signal transmitter which gives off electric counting pulses, and particularly an electronic tachometer, particularly adapted for use with an odometer, the improvement wherein said circuit further comprisesan electronic encoder coding the numerical value in a one-step code whereby the numerical value can be stored; and wherein said encoder includes decade counters in which each decade of a counter for the counting of the numerical value is adapted for use with the one-step code; said circuit further comprising means for transferring the numerical value coded in the one-step code from said counter to a non-volatile storage formed of floating gate storage cells each having an input; and wherein one group each of floating gate storage cells can be addressed for the storage of one-step coded numerical values corresponding to each decade, and wherein said means for transferring the numerical value include means which are actuated at predetermined numeral values for cyclically interchanging the addresses of the storage places of the lowest of said decades. 2. The circuit as set forth in claim 1, whereinthe means for coding the numerical value performs the coding by use of the Libaw-Craig code. 3. The circuit as set forth in claim 1, whereineach of the counter outputs of the lowest five of said decades are cyclically connected, via a decade selector developed as a multiplexer, with each of the inputs to said storage being addressable by a single address; said circuit further comprising coding means and an address counter which counts successive decades and controls said decade selector as well as a first input of said coding means, a second input thereof being fed by at least one decade of said counter; and wherein an address output of the coding means is present for cyclically interchanging the addresses of the lowest five of said decades with the storage. 4. The circuit as set forth in claim 1, further comprisingmeans comprising a buffer capacitor in the circuit in order to secure the data in case of the failure of the operating voltage during a writing process for transferring the counter reading into the storage. 5. The circuit as set forth in claim 1, whereineach address of the non-volatile storage is incremented by one bit at a time, the circuit further comprising a voltage monitoring device, a buffer capacitor and a control logic unit controlled by said voltage monitoring device and being so constructed that, in case of a failure of operating voltage during the transfer of the reading of the counter into the non-volatile storage, the writing process under one address of a decade is carried out to the end by means of said buffer capacitor and thereupon an additional one of said bits is added to the decade, and that upon the next following connection of the operating voltage the contents of the addresses of lower decades of said counter are set at a predetermined number. 6. In an electric circuit for storing numerical data for an odometer in a vehicle, said data being incremented bit by bit corresponding to the distance travelled by said vehicle, said circuit comprising:a storage unit operative in response to electric energy from a source thereof, the utilization of said energy being dependent on the number of changes in state of data stored in said storage unit, said storage unit being a non-volatile storage formed of floating gate storage cells; means coupled between said storage unit and a source of said data for coding said data with a code wherein the number of said changes in state is minimized between successive values of said data, thereby minimizing said utilization of said energy; and wherein said coding means comprises an electronic encoder coding the numerical data in a one-step code, said encoder including decade counters in which each decade of a counter for the counting of the numerical data is adapted for use with the one-step code; means for transferring the numerical data coded in the one-step code from said counter to said storage unit; and wherein one group each of floating gate storage cells can be addressed for the storage of one-step coded numerical data corresponding to each decade; and wherein said means for transferring the numerical data include means which are actuated at predetermined numerical values for cyclically interchanging the addresses of the storage places of the lowest of said decades. 7. The circuit according to claim 6, whereinsaid coding is accomplished with a Libaw-Craig code. 8. The circuit according to claim 6, further comprisingmeans comprising a capacitor for storing further energy for the operation of said storage unit, and said further energy maintaining operation of said circuit during a transistion in said data between successive values thereof, thereby preventing a loss of data in the event of a failure of said energy source. Description
For demonstration purposes the attempt has already been made to store the distance traveled by a C-MOS-RAM write-read memory in combination with a battery. In this connection, however, the disadvantages are noted, among other things, that a battery may not have sufficient storage capacity over the temperature range of -25� C. to +70� C. which occurs in automobiles. Furthermore, suitable batteries, for instance lithium batteries, are expensive.
The object of the invention is therefore to create--while avoiding the disadvantages of previous odometers or distance storage devices--using semiconductor technology, a storage circuit which has a storage life of at least ten years with operating voltage disconnected over a wide operating temperature range of from -25� C. to +70� C. and whose storage charge time or erasure time is sufficiently short to store the changing numerical value. The circuit should furthermore make it possible, at least in the long run, to reduce the cost of manufacturing the storage and the storage indication.
With this circuit, which has a non-volatile storage consisting of floating-gate storage cells, a storage life of more than ten years is obtained with an ambient temperature of 70� C. The operating temperature range of -25� C. to +70� C. is maintained. The logic for the control of the storage can be arranged in advantageous manner on the same chip as the storage cells. The storage charge time, i.e. the time for writing a logical 1 (L) is independent of the number of write-erase cycles and typically remains less than 20 ms. The time for erasing the storage depends on the number of erase cycles and after 10,000 erase processes it is typically about 100 ms. In accordance with the invention, in order to keep the number of erase cycles as small as possible and thus keep the erase time short, the numerical value is stored in a one-step code in the non-volatile storage. In this way, upon passage from one multi-digit numerical value to the next higher multi-digit numerical value, only one place will change its value from a first binary state, for instance 1, to a second binary state, for instance 0.
With the customary organization of a multi-decade counter and storage, a lower decade will, upon incrementation, change the values of its positions more frequently than the positions of the next higher decade will change. In order therefore to permit the erase times for the storage cells of the lower decade to increase as little as possible during the storage time of the non-volatile storage, means (coder 23) which are actuated at predetermined numerical values are provided for cyclically interchanging the addresses of the storage places (A0,A1 . . . A5) of the lowest decades (D0, D1, D2, D3, D4).
In detail, for the transfer of the numerical value from the counter into the non-volatile storage, the circuit, with due consideration of the above inventive principles, is developed in the manner that each of the counter outputs (20) of the lowest five decades (D0 to D4) can be cyclically connected, via a decade selector developed as multiplexer, with the storage inputs each of which can be addressed with a single address; that an address counter (29) which counts successive decades is provided, it controlling the decade selector (30) as well as a first input of a coder (23) whose second input is fed by at least one decade (6th decade, D5) of the counter; and that an address output (bus line) of the coder is present for cyclically interchanging the addresses of the lowest five decades with the storage (storage part 21).
The circuit is provided with the data securing means particularly advantageously in the manner that each address (A0, A1 to A5) of the non-volatile storage (21, 22) is increased by an additional bit (sixth storage cell); that a control logic (control logic part 28 and 1-bit register F), controlled by an operating voltage monitoring device, is so constructed that in case of a failure of operating voltage during the transfer of the reading of the counter into the non-volatile storage (21, 22), the writing process under one address of a decade is carried out to the end by means of the buffer capacitor; thereupon the additional bit is added to this decade. Upon the next following connection of the operating voltage, the contents of the addresses of the lower decades are set at a predetermined number (zero).
In FIGS. 2 and 3, D0, D1, D2, D3, D4, D5 are six decades of a counter. Each decade is developed as a shift counter with five bits. The counting pulse--possibly after reshaping--is fed into the first decade D0 via a line 18. The origin of line 18 is a signal transmitter or a pulse shaping circuit feeding the mentioned counting pulse with a signal having usable shape into said line 18. A carry-over line 19 which connects decade D0 to decade D1 feeds a pulse into the next higher decade D1 when a counting cycle of decade D0 has been completed. In the same way, carry-overs are fed into the decades D2, D3, D4, D5. Each counter has five counter outputs 20 which are designated Q0 0, Q0 1, Q0 2, Q0 3 and Q0 4 in FIG. 3 for the first decade. In corresponding manner, the counter outputs for the second decade D1 are designated bit-wise by Q1 0, Q1 1, etc. up to Q5 0, Q5 1, Q5 2, Q5 3, Q5 4 of the sixth decade D5.
In the table of state of FIG. 4, Z designates the counting pulses with which the counter states or outputs Q0 to Q4 are bit-wise associated. From the table of state it is clear that upon the occurrence of each counting pulse Z, at most one bit changes from binary state 1 to binary state 0, for instance upon the first counting pulse in the lowermost bit, associated with the output Q0. The change from the binary state 0 to the binary state 1 starting from the sixth counting pulse is of less interest here since no erasing of a storage cell is associated with it but rather the writing of a binary number 1.
The count of the counter of each decade D0 to D5 is stored in a word of a non-volatile storage consisting of floating-gate storage cells. Each word comprises five bits for the storage of a decade word and a sixth additional bit for the securing of the data, which will be explained further below.
In FIG. 2 the non-volatile storage part which is associated with the lowermost five decades and can be addressed by five words is designated 21. The storage part 22 which is associated with the highest decade can be addressed by another address consisting of six bits. In FIG. 3, the storage addresses are designated A0, A1 to A5 and the storage inputs are designated q0 0, q0 1, q0 2, q0 3, q0 4 for the lowermost decade and q1 0, q1 1, q1 2, q1 3, q1 4 for the next higher decade. The representation contained in FIG. 3 of the storage addresses for the decades of the counter is present in this connection for a given time interval, in this case for the first 100,000 km. As explained below, the association is changed as a function of the count of the counter or numerical value every 100,000 km in the case of the lowermost five decades while the association for the uppermost decade D5 with the storage part 22 is retained at all times.
The function table for the forming of the addresses is realized in FIG. 2 in the coder 23. Accordingly a bus line 24 for the addresses leads to both storage parts 21 and 22. The coder is fed via a bus line 25 with information about the counting interval which is just present, which is taken from the decade D5, since the counting interval is 100,000 km. A further bus line 26 feeds the coder with information as to what value of one of the decades D0 to D5 is to be transferred to the non-volatile storage part 21.
The decade selector 30 is developed as a multiplexer and determines, by signals of the address counter 29 via the bus line 26, the numerical value of what decade is to be transferred in each case into the non-volatile storage. The interrogating of the decades D0 to D5 takes place in this connection from the highest decade to the lowest, i.e. starting from D5.
The circuit operates in the manner that counting pulses are fed via the line 18 into the six decadic counters so that the1r decades D0 to D5 are incremented corresponding to the number of counting pulses fed, and the numerical value is present in the counter as a number coded in the Libaw-Craig code. For the carry-over of the individual decades of the numerical value, the address counter 29 is placed in operation, controlled by the control logic part 28, so that the decades are carried over from D5 to D0 one after the other into the non-volatile storage 21, 22. First of all, the content of the decade D5 is fed into the storage part 22, this being caused by a signal on the line 33, when the address counter has counted the decade K=5. The counter readings of the decades D4 to D0 are then written cyclically in time-division multiplex operation by the decade selector 30 into the storage part 21 of the non-volatile storage, for which purpose the decade selector is controlled by signals in the bus line 26. At the same time, the coder 23, which also contains signals from the bus line 26 corresponding to the decade value to be carried over as well as signals from the bus line 25 concerning the specific counting interval, determines the address of the five-bit word in the storage part 21 under which the content of the decade simultaneously selected by the decade selector is to be stored in the non-volatile storage part 21. This process is repeated until one carry over cycle when the lowest decade D0 is also interrogated. The association of the addresses in the storage part 21 changes, controlled by the address counter 29, every 100,000 km while the association of the address j=5 with the storage part 22 remains unchanged.
If during a transfer of the numerical value of one decade, for instance of the decade D3, the operating voltage should fail, the transfer of the counter reading of said decade D3 will nevertheless be carried out completely. Thereupon, if the content of the decade D3 had been changed just before the transfer of its contents, then a logical 1 will be recorded in the sixth storage cell under this address. This sixth storage cell, which is normally not acted upon, can be written very rapidly. Due to the voltage failure the contents of the decades D2, D1, D0 are no longer transferred within this transfer cycle. Upon restoration of the operating voltage, however, it is checked whether a sixth storage cell has been set to 1. Since this takes place here in the sixth storage cell, which belongs to the address under which the value of the decade D3 is transferred, the value zero upon restoration of the operating voltage is stored in the storage part 21 under the addresses for the decades D2, D1 and D0. This means that in the event that the sixth storage cell has been set to 1 at the address under which the value of the decade D3 was stored, the counter in decades D2, D1, D0 has made a carry forward up to decade D3 so that the content of the addresses D2, D1, D0 must be zero.
FIG. 2 also shows the multiplexing feature of the decade selector 30. This feature is indicated by two switches 30a and 30b. Both switches are actuated by the address counter 29 via the bus line 26, cf. the second paragraph on page 12. The switches 30a and 30b are adapted to connect the outputs 20 of each of the decades D0 to D4 with each of the portions of the storage 21 having the addresses A0 through A4 in a particular sequence, cf. the second paragraph on page 2.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3456200 *Feb 9, 1966Jul 15, 1969Philips CorpFrequency divider having a first decade with an adjustable counting length that is repeatable during each divider cycleUS3684870 *Sep 3, 1970Aug 15, 1972Veeder Industries IncPercentage counterUS3916390 *Dec 31, 1974Oct 28, 1975IbmDynamic memory with non-volatile back-up modeUS3984815 *May 2, 1975Oct 5, 1976Sperry Rand CorporationTime of event recorderUS4263664 *Aug 31, 1979Apr 21, 1981Xicor, Inc.Nonvolatile static random access memory system* Cited by examinerNon-Patent CitationsReference1 *IBM Technical Disclosure Bulletin, vol. 23, No. 2, Jul. 1980, pp. 460 462, Modified Gray Code Counters, by Barrs et al.2IBM Technical Disclosure Bulletin, vol. 23, No. 2, Jul. 1980, pp. 460-462, Modified Gray Code Counters, by Barrs et al.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS4642787 *Jul 30, 1984Feb 10, 1987Motorola, Inc.Field presettable electronic odometerUS4674054 *Feb 12, 1986Jun 16, 1987Sumikin Coke Company LimitedAutomatic control method for coke oven working machines and fixed position control apparatus thereforUS4768210 *Aug 3, 1987Aug 30, 1988Siemens AktiengesellschaftMethod and apparatus for failsafe storage and reading of a digital counter in case of power interruptionUS4803707 *Dec 21, 1987Feb 7, 1989Ncr CorporationNonvolatile electronic odometer with excess write cycle protectionUS4807264 *Jun 13, 1986Feb 21, 1989Robert Bosch GmbhCircuit arrangement for the addition, storage and reproduction of electric counting pulsesUS4860228 *Feb 24, 1987Aug 22, 1989Motorola, Inc.Non-volatile memory incremental counting systemUS4947410 *Feb 23, 1989Aug 7, 1990General Motors CorporationMethod and apparatus for counting with a nonvolatile memoryUS5046029 *Dec 8, 1988Sep 3, 1991Nissan Motor Company, Ltd.Electronic odo/trip meter for automobilesUS5222109 *Dec 28, 1990Jun 22, 1993Ibm CorporationEndurance management for solid state filesUS5924057 *Jun 25, 1997Jul 13, 1999Ford Motor CompanyMethod of preventing odometer fraudUS5963480 *Nov 12, 1998Oct 5, 1999Harari; EliyahouHighly compact EPROM and flash EEPROM devicesUS6081447 *Mar 5, 1999Jun 27, 2000Western Digital CorporationWear leveling techniques for flash EEPROM systemsUS6230233Sep 13, 1991May 8, 2001Sandisk CorporationWear leveling techniques for flash EEPROM systemsUS6570790 *Nov 17, 1993May 27, 2003Sandisk CorporationHighly compact EPROM and flash EEPROM devicesUS6594183Jun 30, 1998Jul 15, 2003Sandisk CorporationWear leveling techniques for flash EEPROM systemsUS6850443May 2, 2003Feb 1, 2005Sandisk CorporationWear leveling techniques for flash EEPROM systemsUS6914817Feb 11, 2003Jul 5, 2005Sandisk CorporationHighly compact EPROM and flash EEPROM devicesUS7120729Oct 14, 2003Oct 10, 2006Sandisk CorporationAutomated wear leveling in non-volatile storage systemsUS7353325Jan 3, 2005Apr 1, 2008Sandisk CorporationWear leveling techniques for flash EEPROM systemsUS7552272Oct 10, 2006Jun 23, 2009Sandisk CorporationAutomated wear leveling in non-volatile storage systemsUS8040727Aug 28, 1998Oct 18, 2011Sandisk CorporationFlash EEprom system with overhead data stored in user data sectorsUS20030218920 *Feb 11, 2003Nov 27, 2003Sandisk CorporationHighly compact Eprom and flash EEprom devicesUS20040083335 *Oct 14, 2003Apr 29, 2004Gonzalez Carlos J.Automated wear leveling in non-volatile storage systemsUS20050114589 *Jan 3, 2005May 26, 2005Lofgren Karl M.Wear leveling techniques for flash EEPROM systemsUS20050243601 *Apr 26, 2005Nov 3, 2005Eliyahou HarariHighly compact Eprom and flash EEprom devicesUS20070083698 *Oct 10, 2006Apr 12, 2007Gonzalez Carlos JAutomated Wear Leveling in Non-Volatile Storage SystemsUS20080162798 *Feb 27, 2008Jul 3, 2008Lofgren Karl M JWear leveling techniques for flash eeprom systemsWO1986000985A1 *Jun 24, 1985Feb 13, 1986Motorola IncField presettable electronic usemeter* Cited by examinerClassifications U.S. Classification377/24.1, 377/34, 377/26International ClassificationH03K21/40, G01C22/02Cooperative ClassificationH03K21/403, G01C22/02European ClassificationG01C22/02, H03K21/40MLegal EventsDateCodeEventDescriptionMay 25, 1982ASAssignmentOwner name: VDO ADOLF SCHINDLING AG, 6000 FRANKFURT/MAIN, GRAFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:HENRY, PETER;REEL/FRAME:004013/0734Effective date: 19820426Owner name: VDO ADOLF SCHINDLING AG, GERMANYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HENRY, PETER;REEL/FRAME:004013/0734Effective date: 19820426Nov 28, 1988FPAYFee paymentYear of fee payment: 4Jul 11, 1993LAPSLapse for failure to pay maintenance feesSep 28, 1993FPExpired due to failure to pay maintenance feeEffective date: 19930711RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services