Source: http://www.google.fr/patents/US7925808?hl=fr
Timestamp: 2013-05-18 17:10:18
Document Index: 301013939

Matched Legal Cases: ['Application No. 200810098473', 'Application No. 2006', 'Application No. 200480003983', 'Application No. 200480003983', 'Application No. 2006', 'Application No. 200810098473', 'Application No. 2006', 'Application No. 200810098473']

Brevet US7925808 - Memory system and device with serialized data transfer - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Historique Web | Connexion Recherche avanc�e dans les brevets BrevetsA memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory...http://www.google.fr/patents/US7925808?utm_source=gb-gplus-shareBrevet US7925808 - Memory system and device with serialized data transfer Num�ro de publicationUS7925808 B2Type de publicationOctroi Num�ro de demande12/116,439 Date de publication12 avr. 2011 Date de d�p�t7 mai 2008 Date de priorit�13 janv. 2003Autre r�f�rence de publicationCN1748204ACN1748204BCN101281508AUS6826663US7216187US7313639US7478181US7921245US8347047US20040139253US20040139288US20050232020US20070073926 InventeursRichard E PeregoFrederick A Ware Cessionnaire d'origineRambus Inc. Classification aux �tats-Unis710/71365/221710/74711/155 Classification internationaleG06F13/16G11C16/06G06F13/12G06F13/38G06F13/00G06F12/00 Classification coop�rativeG06F13/1684 Classification europ�enneG06F13/16D6R�f�rencesCitations de brevets (42)Citations hors brevets (21)Liens externesUSPTO Cession USPTO EspacenetMemory system and device with serialized data transferUS 7925808 B2 R�sum� A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.
Citations de brevets Brevet cit� Date de d�p�t Date de publication D�posant TitreUS436951110 nov. 198018 janv. 1983Nippon Telegraph & Telephone Public Corp.Semiconductor memory test equipmentUS45436449 sept. 198224 sept. 1985Hitachi, Ltd.Control circuit for matrix-driven recordingUS474557715 nov. 198517 mai 1988Fujitsu LimitedSemiconductor memory device with shift registers for high speed reading and writingUS509190712 oct. 199025 f�vr. 1992Alcatel N.V.Multiplexer and demultiplexer, particularly for information transmission networks with a synchronous hierarchy of the digital signalsUS52166332 mai 19911 juin 1993Samsung Electronics Co., Ltd.Nonvolatile semiconductor memory device including access code circuitryUS52437035 mars 19927 sept. 1993Rambus, Inc.Apparatus for synchronously generating clock signals in a data processing systemUS531556015 oct. 199224 mai 1994Mitsubishi Denki Kabushiki KaishaSemiconductor memory device having a write per bit function in page modeUS54993855 mars 199212 mars 1996Rambus, Inc.Method for accessing and transmitting data to/from a memory in packetsUS57154078 ao�t 19963 f�vr. 1998Rambus, Inc.Process and apparatus for collision detection on a parallel bus by monitoring a first line of the bus during even bus cycles for indications of overlapping packetsUS572971131 mai 199417 mars 1998Sharp Kabushiki KaishaData driven information processing system using address translation table to keep coherent cache and main memories and permitting parallel readings and writingsUS576496320 sept. 19959 juin 1998Rambus, Inc.Method and apparatus for performing maskable multiple color block writesUS576502016 janv. 19979 juin 1998Rambus, Inc.Method of transferring data by transmitting lower order and upper odermemory address bits in separate words with respective op codes and start informationUS580607016 sept. 19978 sept. 1998Sandisk CorporationDevice and method for controlling solid-state memory systemUS581304312 juil. 199622 sept. 1998Motorola, Inc.Method and system including memory patching utilizing a transmission control signal and circuitUS587299611 sept. 199716 f�vr. 1999Rambus, Inc.Method and apparatus for transmitting memory requests by transmitting portions of count data in adjacent words of a packetUS58965459 sept. 199720 avr. 1999Rambus, Inc.Transmitting memory requests for multiple block format memory operations the requests comprising count information, a mask, and a second maskUS61221892 oct. 199819 sept. 2000Rambus Inc.Data packet with embedded maskUS615123915 nov. 199921 nov. 2000Rambus Inc.Data packet with embedded maskUS626673710 janv. 200024 juil. 2001Rambus Inc.Method and apparatus for providing a memory with write enable informationUS63473549 oct. 199812 f�vr. 2002Rambus IncorporatedApparatus and method for maximizing information transfers over limited interconnect resourcesUS64011679 oct. 19984 juin 2002Rambus IncorporatedHigh performance cost optimized memoryUS657812621 sept. 200110 juin 2003Emc CorporationMemory system and method of using sameUS675778930 janv. 200229 juin 2004Rambus, Inc.Apparatus and method for maximizing information transfers over limited interconnect resourcesUS680145922 mars 20025 oct. 2004Intel CorporationObtaining data mask mapping informationUS682666311 mars 200330 nov. 2004Rambus Inc.Coded write maskingUS69523673 nov. 20034 oct. 2005Intel CorporationObtaining data mask mapping informationUS695730722 mars 200218 oct. 2005Intel CorporationMapping data masks in hardware by controller programmingUS71433299 mars 200428 nov. 2006Xilinx, Inc.FPGA configuration memory with built-in error correction mechanismUS716517719 mars 200116 janv. 2007France TelecomMethod of protecting an electronic chip against fraudUS717152821 juil. 200430 janv. 2007Rambus Inc.Method and apparatus for generating a write mask keyUS721618714 juin 20058 mai 2007Rambus Inc.Memory system including a circuit to convert between parallel and serial bitsUS731363911 mars 200325 d�c. 2007Rambus Inc.Memory system and device with serialized data transferUS2003015903919 mars 200121 ao�t 2003France TelecomMethod of protecting an electronic chip against fraudUS2003017960522 mars 200225 sept. 2003Intel CorporationObtaining data mask mapping informationUS2003018251922 mars 200225 sept. 2003Intel CorporationMapping data masks in hardware by controller programmingUS200400934713 nov. 200313 mai 2004Dodd James M.Obtaining data mask mapping informationUS2007007392616 oct. 200629 mars 2007Rambus Inc.Memory system and device with serialized data transferEP0604309A121 d�c. 199329 juin 1994Bull S.A.Informationsystem with high data throughput, and resulting memory circuit and memory controllerEP0883066A22 juin 19989 d�c. 1998Sony CorporationSerial data transmission betwe data processing apparatus and an external storage apparatusJP7121351A Titre non disponibleJPH03122492U Titre non disponibleWO2002015020A214 ao�t 200121 f�vr. 2002Sandisk CorporationMultiple removable non-volatile memory cards serially communicating with a hostCitations hors brevetsR�f�rence1"A Logical Overview of Direct Rambus Architecture," Rambus, Inc., Mar. 1998, 150 pages.2"AMD-751 System Controller Data Sheeet", AMD, Mar. 2000.3"AMD-762 System Controller Data Sheet", AMD, Dec. 2001.4"FCRAM I IP CORE", Lattice Semiconductor Corporation, Nov. 2004.5"Virtex Synthesizable High Performance SDRAM Controller", XILINX, XAPP 134, Version 2.1, Sep. 10, 1999.6Chinese Office Action dated Nov. 8, 2010, State Intellectual Property Office, Chinese Patent Application No. 200810098473.4 filed Jan. 13, 2004.7English Translation of Response to Japanese Office Action filed Aug. 23, 2010, Japan Patent Office, Japanese Patent Application No. 2006-500933, filed Jan. 13, 2004.8English Translation of the Abstract of European Patent Publication No. EP0604309 dated Jun. 29, 1994.9Final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 11/549,841, filed Oct. 16, 2006, Jul. 11, 2008.10Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 11/549,841, filed Oct. 16, 2006, Sep. 22, 2008.11Notification of First Office Action, The Patent Office of the People's Republic of China, Application No. 200480003983.9 filed on Jan. 13, 2004, Jun. 4, 2007.12Notification of Second Office Action, The Patent Office of the People's Republic of China, Application No. 200480003983.9 filed on Jan. 13, 2004, Aug. 15, 2008.13Office Action dated Feb. 23, 2010, Japan Patent Office, Japanese Patent Application No. 2006-500933 filed Jan. 13, 2004.14Rambus Inc., "16/18Mbit (2Mx8/9) & 64/72 Mbit (8Mx8/9) Concurrent RDRAM-Advance Information," Rambus Inc. Data Sheet, Jul. 1996, 61 pages.15Rambus Inc., "8/9-Mbit (1Mx8/9) & 16/18Mbit (2Mx8/9) RDRAM-Preliminary Information," Rambus Inc. Data Sheet, Mar. 1, 1996, 30 pages.16Rambus Inc., "16/18Mbit (2Mx8/9) & 64/72 Mbit (8Mx8/9) Concurrent RDRAM�Advance Information," Rambus Inc. Data Sheet, Jul. 1996, 61 pages.17Rambus Inc., "8/9-Mbit (1Mx8/9) & 16/18Mbit (2Mx8/9) RDRAM�Preliminary Information," Rambus Inc. Data Sheet, Mar. 1, 1996, 30 pages.18Response to Chinese Office Action filed Jan. 5, 2011, State Intellectual Property Office, Chinese Patent Application No. 200810098473.4 filed Jan. 13, 2004.19Response to Final Office Action, U.S. Appl. No. 11/549,841, filed Oct. 16, 2006, Aug. 26, 2008.20Response to Japanese Office Action filed Aug. 23, 2010, Japan Patent Office, Japanese Patent Application No. 2006-500933, filed Jan. 13, 2004.21Response to Office Action dated Feb. 2, 2010, Chinese Patent Application No. 200810098473.4 filed Jan. 13, 2004.Faire pivoterImage d'origineAccueil Google - Plan du site - T�l�chargements par lot sur l'USPTO - R�gles de confidentialit� - Conditions d'utilisation - � propos de Google�Brevets - Envoyer des commentairesDonn�es fournies par IFI CLAIMS Patent Services©2012 Google