Source: http://www.google.com/patents/US5953457?dq=system+for+measuring+web+traffic&ei=Lg8FT__TIIr-sQKzxaGRCg
Timestamp: 2014-12-25 18:56:30
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Patent US5953457 - Method and apparatus for improved video decompression by prescaling of pixel ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA video decoding apparatus and method greatly reduces the computational burden of video decoding by processing several pixels in parallel, thereby reducing the computational load by a factor approximating the number of pixels processed at one time....http://www.google.com/patents/US5953457?utm_source=gb-gplus-sharePatent US5953457 - Method and apparatus for improved video decompression by prescaling of pixel and error terms to mergingAdvanced Patent SearchPublication numberUS5953457 APublication typeGrantApplication numberUS 08/887,678Publication dateSep 14, 1999Filing dateJul 3, 1997Priority dateApr 18, 1995Fee statusLapsedPublication number08887678, 887678, US 5953457 A, US 5953457A, US-A-5953457, US5953457 A, US5953457AInventorsMichael R. Tucker, Geoffrey S. Strongin, Yi LiuOriginal AssigneeAdvanced Micro Devices, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (11), Non-Patent Citations (20), Referenced by (7), Classifications (17), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod and apparatus for improved video decompression by prescaling of pixel and error terms to mergingUS 5953457 AAbstract A video decoding apparatus and method greatly reduces the computational burden of video decoding by processing several pixels in parallel, thereby reducing the computational load by a factor approximating the number of pixels processed at one time.
What is claimed is: 1. A method of executing a saturation-add operation comprising:loading a plurality of multiple-bit pixel values corresponding to a plurality of pixel storage locations of an image memory into a respective plurality of segments of a first register, each of the segments of the first register having a plurality of bits in a hierarchy of significance from at least significant bit to a most significant bit; shifting the plurality of pixel values in the first register one bit to the right in a single, multiple-bit shift operation; masking the most significant bit of the shifted plurality of pixel values in each of the segments of the first register in a single, multiple-bit mask operation; loading a plurality of pixel modification values corresponding to the plurality of pixel values into a respective plurality of segments of a second register, each of the segments of the second register having a plurality of bits in a hierarchy of significance from a least significant bit to a most significant bit; adding the pixel values and the pixel modification values in the first and second registers respectively and holding a resulting sum in a sum register having a plurality of segments; shifting the resulting sum values in the sum register one bit to the left; and displaying a plurality of pixel values to a plurality of pixel locations on a display, the plurality of pixel values being retrieved from the plurality of segments of the sum register, the plurality of segments of the sum register corresponding to the plurality of segments of the first register. 2. A method according to claim 1 further comprising:subsequent to the adding operation and prior to the left shifting operation, testing the most significant bit in each of the segments of the sum register; and for a segment of the sum register having the most significant bit in a set condition, setting the segment value to a preselected saturated value. 3. A method according to claim 1 wherein the displaying operation includes writing the plurality of pixel values to a picture memory.
7. A method according to claim 1 wherein:the first register, second register and sum register are 32-bit registers. 8. A method according to claim 7 wherein:the segments of the plurality of segments in the first register, the second register and the sum register are 8-bit registers. 9. A method according to claim 1 wherein the pixel modification values are 7-bit two's complement values having a range of -128 to +127.
11. A system for decompressing video information comprising:an input stream decoding portion implemented in a processor and including an inverse discrete cosine transformation; an adder implemented in the processor and coupled to the input stream decoding portion; and an executable program code implementing the method of claim 1. 12. An article of manufacture encoding an executable program code executing on the processor and implementing the method of claim 11.
13. A method of executing a saturation-add operation comprising:loading a plurality of multiple-bit pixel values corresponding to a plurality of pixel storage locations of an image memory into a respective plurality of segments of a first register, each of the segments of the first register having a plurality of bits in a hierarchy of significance from a least significant bit to a most significant bit; shifting the plurality of bits in the first register one bit in a first direction in a single, multiple-bit shift operation; masking one bit of the plurality of shifted bits in each of the segments of the first register in a single multiple-bit mask operation; loading a plurality of pixel modification values having a one-to-one correspondence to the plurality of pixel values into a corresponding plurality of segments of a second register, each of the segments of the second register having a plurality of bits in a hierarchy of significance from a least significant bit to a most significant bit; adding the values in the first and second registers and holding a resulting sum in a sum register; and shifting resulting sum values in the sum register one bit in a second direction opposite to the first direction. 14. A method according to claim 13 wherein:the first direction of shifting is a right shift operation; and the bit masked in each segment of the first register is a most significant bit. 15. A method according to claim 13 further comprising:subsequent to the adding operation and prior to the resulting sum value shifting operation, testing a bit in each of the segments of the sum register; and for a segment of the sum register having the bit set, setting the segment value to a preselected saturated value. 16. A method according to claim 13 further comprising:writing the plurality of pixel values to a picture memory. 17. A system for decompressing video information comprising:an input stream decoding portion implemented in a processor and including an inverse discrete cosine transformation; an adder implemented in the processor and coupled to the input stream decoding portion; and an executable program code implementing the method of claim 13. 18. An article of manufacture encoding an executable program code executable on the processor and implementing the method of claim 17.
FIELD OF THE INVENTION The present invention relates to decompression of video information and, more particularly, to improved performance of video decompression by prescaling of pixel and error terms prior to merging.
pixeli +errori =resulti if (resulti &lt;0) resulti =0;
if (resulti &gt;255) resulti =255;
SUMMARY OF THE INVENTION In accordance with a first embodiment of the present invention, a method of executing a saturation-add operation includes the step of loading a plurality of pixel values into a respective plurality of segments of a first register. Each of the segments of the first register have a plurality of bits in a hierarchy of significance from a least significant bit to a most significant bit. The method also includes the steps of shifting bit values in the first register one bit to the right and masking the most significant bit in each of the segments of the first register. A plurality of pixel modification values corresponding to the plurality of pixel values are loaded into a respective plurality of segments of a second register. Each of the segments of the second register have a plurality of bits in a hierarchy of significance from a least significant bit to a most significant bit. The values in the first and second registers are added and the resulting sum is held in a sum register, which is shifted one bit to the left. Pixel values from a plurality of segments of the sum register are then utilized, with the plurality of sum register segments corresponding to the plurality of segments of the first register.
______________________________________for(i=-384; i&lt;640; i++) {   if(i &lt; 0) clip i! = 0;   else if(i &gt; 255) clip i! = 255;   else clip i! = i;   }______________________________________
______________________________________iblock=0;for(iy=iycorner; iy&lt;iycorner+8; iy++) {   for (ix=ixcorner; ix&lt;ixcorner+8; ix++) {     pixel ix! iy! = clip pixel ix! iy! +error iblock!!;     iblock++;     }   }______________________________________
where iblock addresses an element in array error !--a 64-element DCT coefficient block, ix and iy designate x,y coordinates of an 8�8 block of pixels having an upper left corner at coordinates ixcorner, iycorner, and pixel ! ! is an array of 8-bit pixels in a picture.
This suitably efficient saturation-add operation performs a table lookup function on essentially every pixel in a video picture. In a SIF video, for example, 352�240 pixels/frame or 330 macroblocks/frame are processed. In a typical video picture, only 5% to 7% of macroblocks are skipped so that approximately 310�6�8�8 (19,040) pixels/frame are processed by the saturation-add operation.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5164828 *Feb 21, 1991Nov 17, 1992Sony CorporationVideo signal transmission and method and apparatus for coding video signal used in thisUS5329318 *May 13, 1993Jul 12, 1994Intel CorporationMethod for optimizing image motion estimationUS5357282 *Sep 30, 1993Oct 18, 1994Goldstar Co., Ltd.Video decoder with parallel implementationUS5369438 *May 17, 1993Nov 29, 1994Goldstar Co., Ltd.Apparatus for processing image motion compensation information for an image processing systemUS5371547 *May 20, 1993Dec 6, 1994General Electric CompanyApparatus for excising (and reinserting) specific data from a compressed video data stream to reduce its transmission bandwidthUS5386232 *Jun 16, 1993Jan 31, 1995Intel CorporationMethod and apparatus for encoding images using a specified data formatUS5450599 *Jun 4, 1992Sep 12, 1995International Business Machines CorporationImage data processing systemUS5502493 *May 19, 1994Mar 26, 1996Matsushita Electric Corporation Of AmericaVariable length data decoder for use with MPEG encoded video dataUS5515388 *Mar 18, 1994May 7, 1996Sony CorporationApparatus and method for preventing repetitive random errors in transform coefficients representing a motion picture signalUS5523847 *Oct 9, 1992Jun 4, 1996International Business Machines CorporationDigital image processor for color image compressionUS5543846 *Sep 22, 1992Aug 6, 1996Sony CorporationMotion picture encoding system* Cited by examinerNon-Patent CitationsReference1Andy C. Hung, et al, "A Comparison of Fast Inverse Discrete Cosine Transform Algorithms", Multimedia Systems, �1994, pp. 204-217.2 *Andy C. Hung, et al, A Comparison of Fast Inverse Discrete Cosine Transform Algorithms , Multimedia Systems, 1994, pp. 204 217.3Dr. Richard Baker, "Standards Dominate Videoconferencing Implementations", Computer Design, Dec. 1994, pp. 66-70.4 *Dr. Richard Baker, Standards Dominate Videoconferencing Implementations , Computer Design, Dec. 1994, pp. 66 70.5 *ISO/IEC 11172 1, Information Technology Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1,5 Mbit/s Part 1: Systems, Aug. 1, 1993, pp. i vi, 1 53.6 *ISO/IEC 11172 2, Information Technology Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1,5 Mbit/s Part 1: Video, Aug. 1, 1993, pp. i ix, 1 112.7 *ISO/IEC 11172 3, Information Technology Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1,5 Mbit/s Part 1: Audio, Aug. 1, 1993, pp. i vi, 1 150.8ISO/IEC 11172-1, Information Technology-Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1,5 Mbit/s--Part 1: Systems, Aug. 1, 1993, pp. i-vi, 1-53.9ISO/IEC 11172-2, Information Technology-Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1,5 Mbit/s--Part 1: Video, Aug. 1, 1993, pp. i-ix, 1-112.10ISO/IEC 11172-3, Information Technology-Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1,5 Mbit/s--Part 1: Audio, Aug. 1, 1993, pp. i-vi, 1-150.11Kevin L. Gong, et al., "Parallel MPEG-1 Video Encoding", Report, University of California, Berkeley, Computer Science Division, 1994, pp. 1-14.12 *Kevin L. Gong, et al., Parallel MPEG 1 Video Encoding , Report, University of California, Berkeley, Computer Science Division, 1994, pp. 1 14.13Lawrence A. Rowe, et al., "MPEG Video in Software: Representation, Transmission, and Playback", High Speed Networking and Multimedia Computing, Symp. on Elec. Imaging Sci. & Tech., San Jose, CA, Feb., 1994, pp. 1-11.14 *Lawrence A. Rowe, et al., MPEG Video in Software: Representation, Transmission, and Playback , High Speed Networking and Multimedia Computing, Symp. on Elec. Imaging Sci. & Tech., San Jose, CA, Feb., 1994, pp. 1 11.15P1180/D1, "Draft Standard Specification for the Implementations of 8�8 Inverse Discrete Cosine Transform", May 29, 1990, pp. 1-9.16 *P1180/D1, Draft Standard Specification for the Implementations of 8 8 Inverse Discrete Cosine Transform , May 29, 1990, pp. 1 9.17Peng H. Ang, et al., "Video Compression Makes Big Gains", IEEE Spectrum, Oct. 1991, pp. 16-19.18 *Peng H. Ang, et al., Video Compression Makes Big Gains , IEEE Spectrum, Oct. 1991, pp. 16 19.19Stephen Ohr, "Digital Video Spearheads TV and Videoconferencing Applications", Computer Design, Dec. 1994, pp. 59-64.20 *Stephen Ohr, Digital Video Spearheads TV and Videoconferencing Applications , Computer Design, Dec. 1994, pp. 59 64.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6873735Feb 5, 2001Mar 29, 2005Ati Technologies, Inc.System for improved efficiency in motion compensated video processing and method thereofUS7085693Jun 19, 2001Aug 1, 2006International Business Machines CorporationManipulation of electronic media using off-line mediaUS7801224Oct 17, 2005Sep 21, 2010Advanced Micro Devices, Inc.Optimizing decoders on a hardware platform that supports video accelerationUS7885336Nov 27, 2002Feb 8, 2011Ati Technologies UlcProgrammable shader-based motion compensation apparatus and methodUS7958177 *Nov 29, 2006Jun 7, 2011Arcsoft, Inc.Method of parallelly filtering input data words to obtain final output data words containing packed half-pel pixelsUS8804850 *May 6, 2013Aug 12, 2014Marvell International, Ltd.System and method to execute a clipping instructionUS20080247464 *Sep 12, 2007Oct 9, 2008Samsung Electronics Co., Ltd.Method and apparatus for encoding and decoding based on intra prediction using differential equation* Cited by examinerClassifications U.S. Classification382/233, 375/E07.093, 382/236, 375/240.03, 375/E07.189, 375/E07.211, 375/240.2, 375/240.15International ClassificationH04N7/26, G06T9/00, H04N7/50Cooperative ClassificationH04N19/00781, H04N19/00903, H04N19/00478European ClassificationH04N7/50, H04N7/26L, H04N7/26PLegal EventsDateCodeEventDescriptionNov 11, 2003FPExpired due to failure to pay maintenance feeEffective date: 20030914Sep 15, 2003LAPSLapse for failure to pay maintenance feesApr 2, 2003REMIMaintenance fee reminder mailedRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google