Source: http://www.google.com/patents/US4231015?dq=6,034,652
Timestamp: 2017-05-28 04:31:37
Document Index: 499278515

Matched Legal Cases: ['ART 36', 'ART 36', 'ART 36', 'ART 36', 'ART 36', 'ART 36', 'ART 36', 'ART 36', 'ART 36', 'ART 36', 'ART 36', 'ART 36', 'ART 36']

Patent US4231015 - Multiple-processor digital communication system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA digital communication system is disclosed for communicating among two central consoles and a plurality of local controllers, such as may be used in a radiation and monitoring system and the like. Communication occurs between each of the consoles and all of the local controllers via dual paths. Each...http://www.google.com/patents/US4231015?utm_source=gb-gplus-sharePatent US4231015 - Multiple-processor digital communication systemAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS4231015 APublication typeGrantApplication numberUS 05/946,566Publication dateOct 28, 1980Filing dateSep 28, 1978Priority dateSep 28, 1978Also published asCA1119272A, CA1119272A1Publication number05946566, 946566, US 4231015 A, US 4231015A, US-A-4231015, US4231015 A, US4231015AInventorsDonald C. UnionOriginal AssigneeGeneral Atomic CompanyExport CitationBiBTeX, EndNote, RefManPatent Citations (36), Non-Patent Citations (2), Referenced by (9), Classifications (19), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMultiple-processor digital communication system
US 4231015 AAbstract
A digital communication system is disclosed for communicating among two central consoles and a plurality of local controllers, such as may be used in a radiation and monitoring system and the like. Communication occurs between each of the consoles and all of the local controllers via dual paths. Each path is independent of the other and each extends from one of the consoles to all of the local controllers from opposite directions, thereby forming a unique noncontinuous loop.
1. A system for communicating among two central consoles and a plurality of local controllers, comprising:first and second central consoles for controlling the communication of said system, said consoles selectively issuing command messages to said controllers and for receiving response messages therefrom; a first two line communication path for selectively transmitting messages in both directions, said first path extending from one central console serially to and being connected to all of said plurality of controllers; a second two line communication path for selectively transmitting messages in both directions, said second path extending from the other console serially to and being connected to all of said plurality of controllers, the controllers being connected nearer to said first console via said first path also being connected relatively farther from said second console via said second path; an interconnecting communication path interconnecting said consoles; said first console being capable of communicating with each of said controllers via said first path an via said interconnecting path, said second console and said second path; said second console being capable of communicating with each of said controllers via said second path and via said interconnecting path, said first console and said first path. Description
Another object of the present invention is to provide a system wherein the local controllers are linked together by two communication paths, wherein each path is independent of the other and wherein a local controller can be isolated from the paths without destroying communication between all other controllers by either console via one or the other of the paths.
A more detailed object of the present invention is to provide a system that utilizes bidirectional duplex communication links between local controllers wherein command messages originating at a console are transmitted in one direction and response messages from a local controller are transmitted in the opposite directions and wherein reflections of these messages are blocked from being transmitted in the wrong direction.
Broadly stated, the present invention comprises a communication system that can be used in radiation monitoring and control systems of a nuclear power station and the like, which has extreme flexibility of operation which contributes to its overall reliability to carry out the communication functions that are necessary in such an application. Because system reliability is of such critical importance in such an environment, the present invention incorporates many desirable system features such as redundancy and the ability to reconfigure or isolate malfunctioning components and does so in a unique manner as will become apparent. The system utilizes two central control consoles, with a communication path extending from each console to all of the local controllers that are part of the system and also includes an interconnection between the two consoles. When the system is operating without a malfunction or fault, each console can communicate with any local controller in the system via its own independent half duplex two wire communication path which extends from the console to all of the local controllers. A communication path is also provided between the consoles which enables one console to use the other console's direct communication path in the event that a malfunction occurs in its own path. If the malfunction occurs at a local controller that is, for example, in the middle of the group of local controllers, all controllers upstream of the malfunctioning controller can be communicated with by the subject console directly through its communication path and all controllers downstream or beyond the malfunctioning controller can be communicated with via the second communication path, the other console and the interconnection between consoles. (As a matter of definition herein, upstream relative to a local controller is intended to mean toward the console in the particular communication path and downstream is intended to be away from the console in the path. Thus, the local controller would be upstream from another in one path, but downstream from the other in the other path.) In the above example, the malfunctioning controller can be isolated and communications can be continued between the console and all other local controllers in the system.
The capability of isolating a local controller prevents a malfunctioning local controller from interrupting communication between a console and several of the controllers as is the case with many prior art systems. This aspect of the system can be more readily understood by referring to FIG. 1 which is a greatly simplified block diagram embodying the system and includes two central consoles 10 and 12, as well as a plurality of local controllers, the block diagram of which includes only three controllers 14a, 14b and 14c. The console 10 is connected to the controllers via a communication path 16 and the console 12 is connected to the same controllers via the communication path 18. A communication path 20 extends between the consoles 10 and 12. Each of the communication paths 16, 18 and 20 preferably comprises half duplex, two wire cables and the paths 16 and 18 are independent from one another. During normal operation, the console 10 can communicate with the controllers via communication path 16 and the console 12 can communicate with the same controllers via the communication path 18. The advantages of the noncontinuous loop is that communication between one console and the controllers is independent of the communication between the controller and the other console by virtue of the independent paths 16 and 18, and yet, when a controller 14 fails and does not relay command messages from one console, that console can communicate through the other console to the controllers beyond the failed one. More specifically, in the event that controller 14b fails, console 10 can communicate with controller 14a via the path 16 and can also communicate with controller 14c via communication path 18, console 12 and the path 20. Each console remains master over all communications along its path through the controllers and merges communication requests from the other console into its own communication stream.
The local controllers also generate response messages to the command messages, provided the command message has addressed the particular local controller, it being understood that all local controllers receive and process all command messages and only the local controller in which a unique address identifying the same generates a response. In the event that a response is generated, it is transmitted back to the console to provide the requested information. During the transmission of the response message and referring to FIG. 2b, a response message from local controller 14c, for example, (not shown) would appear on the right-most lines 16 and be received by the receiver R2 of controller 14b which would relay the message to transmitter T1 which would transmit it to receiver R2 of controller 14a as well as to its own receiver R1. Receiver R2 of controller 14awould relay the message to transmitter T1 which would transmit the message back to the console as desired. Receiver R1 of controller 14a would not relay the message to transmitter T2 (or receiver R1 to transmitter T2 in controller 14b) for if this happened, the action of transmitter T2 of controller 14a would be received by receiver R2 which would be mixed in with the new responses being originated by the local controller 14c. Thus, as is evident from the foregoing brief description of FIGS. 2a and 2b, the reflected signals are blocked by logic (not shown) that detects a new message in one direction and blocks all messages in the opposite directions. In other words, when command messages are being transmitted along lines 16 to the right, receivers associated with response messages are precluded from relaying any reflected command messages to response message transmitters and, conversely, when response messages are being transmitted, command message receivers do not relay any reflected messages to the command message transmitters. This insures that command messages travel the full length of the communication path so that an addressed local controller will receive, process and respond to the command message and the response messages will be transmitted back to the console as desired and will not be reflected and transmitted in the wrong direction.
If it is assumed that the local controller 14c or some other downstream local controller has been addressed and requested to provide a response message, it will appear on the rightward lines 16, the upper one of which extends to an opto-isolator 54, the line being specifically connected to a LED 56 that is optically coupled to a photo-transistor 58, the collector of which is connected to line 60 that extends to reclocking circuitry 38 that accomplishes the same task that is performed with respect to the data on line 34. The reclocking circuitry 38 response message output appears on line 64 which extends to one input of an AND gate 66, the other input of which is supplied by line 68, the transmitter output of the USART 36. The output of the AND gate 66 appears on line 70 is connected to a LED 72 and the data that is present on line 70 will cause the LED 72 to selectively switch the photo-transistor 30 so that the response message can be transmitted via the leftward lines 16 back to the console 10 as desired.
It should be appreciated that the photo-transistor 30 is in the same current loop as the LED 26 so that a response message will also be detected by the photo-transistor 32 and will therefore be available on line 34. However, the operation of the circuitry is such that the gate 35 is disabled when a response message is being reclocked through the controller or if a response message is being generated by this controller. Since the response message is reflected onto line 34 is not desired to be transmitted through the reclocking circuitry 38 onto line 46 toward the rightward local controllers since line 46 should only carry command messages, the reclocking circuitry 38 automatically inhibits this portion of the circuitry and effectively blocks the reflected message. In a similar manner, transmission of a command message on line 46 will cause the opto-isolator 48 to operate and this message will be detected by the opto-isolator 54 via lines 16. Thus, the reflected command message will be present on line 60. However, the reclocking circuitry 38 will automatically block this path so that the command message will not be sent back upstream toward the console.
The system is designed to issue a poll to each local controller at predetermined intervals. If the processing unit 42 of the local controller 14b fails to receive a poll on path 16, its processing unit 42 automatically issues a signal to the USART 36 causing it to apply a signal on a line 74 that causes the reclocking circuitry 38 to block transmission in both directions. The processing unit also has associated timing circuitry which determines if the processing unit is properly operating, i.e., the processing unit must issue a particular signal to the circuitry at regular intervals. If the signal is not received by the timing circuitry, it shuts down the processing means and also de-energizes relays which isolate the entire local controller from the lines 16. The timing circuitry is not specifically shown but is easily constructed and may comprise a monostable multivibrator which is adapted to time out and provide a suitable output signal if it does not receive the regular pulses (1 per second, for example) from the processing means. The isolation is accomplished by relay contacts 76 switching from position 1 to position 2 where lines 78 effectively bypass the entire local controller. The circuitry shown in the lower half of FIG. 3 is virtually identical to that shown and described with respect to the communication path 16, the lower half merely comprising circuitry for the path 18.
The overall operation of the system having the local controllers 14a, 14b and 14c to consoles 10 and 12 in the manner as shown in FIG. 4 with the local controllers having circuitry generally as shown in FIG. 3 will now be described. If a console command message is transmitted via communication path 16 to the local controllers, all controllers accept and process the message to determine which controller is being addressed. If the command message from the console 10 is addressed to local controller 14b, for example, the controller will originate the response message after the command message is completely received. The response message is forwarded by USART 36 via gate 66 and line 70 to the transmitter comprised of the opto-isolator 24, and is sent back to the console 10 via the local controller 14a. As is evident from the circuitry of FIG. 3, a response message is relayed back through the upstream local controllers without their processing means 42 seeing the response message and this prevents the processing means of the local controllers from being burdened by the often lengthy response messages that pass along the communication path 16. The response messages may be quite long because they contain large amounts of data from the distributed data base stored and maintained within each controller.
One of the many advantages of the present system is that a runaway or continuously operating transmitter will not prevent each console 10 or 12 from providing command messages to all other local controllers and receiving responses from them. If the transmitter T2 of controller 14b were transmitting a command message and began malfunctioning so as to transmit continously, communication along path 16 from the console 10 would be jammed to downstream local controllers, i.e., controllers 14c (and any other local controllers beyond 14c is a large number were incorporated in the system). Console 10 would send commands to controller 14c by routing the commands through console 12. Console 12 would merge these commands with its own commands and also remain master over its independent communication path 18 through the local controller. The first communication path 16 is jammed between local controller 14b and 14c but the second path 18 is independent of that jam because the communication loop is noncontinuous.
Similarly, if a response transmitter, e.g., transmitter T1 in the local controller 14c, were to transmit continuously, no communication would be possible along path 16. Thus, periodic polling messages from the console 10 along path 16 would not be possible. When the processing means 42 of a local controller does not receive a polling command message for a predetermined time interval, it will block the relaying of messages in either direction. In terms of what is being accomplished by the circuitry shown in FIG. 3, a processing means 42 instructs the USART 36 to provide a signal on line 74 to inhibit the reclocking circuit 38 so that any response messages received by the receiver 54 and which appear on line 60 as well as command messages on line 34 are not reclocked and will therefore not be passed to the respective transmitters 24 and 48.
Since the response transmitter T1 of local controller 14c was operating continuously and prevented any command messages from being transmitted on the communication path 16, the processing unit of all local controllers 14a, 14b and 14c causes similar blocking of the response messages. After the jamming is stopped, console 10 will initially command controller 14a to permit it to generate a response and if the path is not jammed by operation of the local controller 14a, it will send a response message. The console will then send a command message commanding local controller 14b to issue a response message which, in the described example, will result in proper operation. When the console 10 commands local controller 14c, the faulty transmitter T1 will again jam the communication path and the console 10 will thereby locate the fault and issue an alarm that controller 14c has a faulty transmitter on conmmunication path 16. The controllers will again provide the blocking action in the same manner and the console 10 will repeat the reconnection process but will not poll controller 14c, since it now knows that this controller has a faulty transmitter in communication path 16.
With respect to the operation of the circuitry shown in FIG. 5, when a command message is being received from the console 10 after having come through the opto-isolator 22, it appears on line 34 and is applied to the NAND gate 35 as well as to a flip-flop 92. The other input lines 94 and 96 to the NAND gate 35 are normally high so that the data is gated onto line 98 that extends to the receiver terminal of the USART 36. As previously mentioned, the data is in the form of 10 bits, including an initial start bit, eight data bits and a stop bit, with the start and stop bits being high bits. As soon as all 10 bits are received by the USART 36, it communicates with the processing unit 42 and forwards the data to it via lines 90.
As previously mentioned, the command message that is received on line 34 and which is processed by the USART 36 and the processing unit 42 as described, is also transmitted to all other local controllers for processing in a similar manner. If the address contained in the command message is determined to be that of a particular local controller, then it can generate its response message and transmit it via the USART onto line 68, through NAND gate 66 and onto line 70 which will cause the opto-isolator 24 to apply the message onto lines 16 extending back toward the console 10. The command message on line 34 as previously mentioned is applied to the J input of the JK flip-flop 92 as well as to the J input of a flip-flop 102. The data is also inverted by an inverter 104 and applied to the K input of the flip-flop 102. The Q output of flip-flop 92 is applied to a NAND gate 106 via line 108 and the Q output of flip-flop 102 is also applied to the NAND gate 106 via line 110. During operation, the data that present in the data stream is actually clocked through the flip-flop 102 which essentially reclocks the same and applies it onto line 46 as the flip-flops 92 and 102 are clocked by clock line 112.
In accordance with an important aspect of the reclocking circuitry, the clock signal on line 112 which clocks the data through the flip-flops 92 and 102 is produced by a counter 114 which is a four bit binary counter that is preset to a count of seven and thereby reaches its terminal count of 15 after eight counts. The counter 114 is clocked by a clock signal on the line 100 and is at a rate that is 16 times the rate of the data that is being received on line 34. As soon as the counter 114 is allowed to count, it counts eight counts before it reaches its terminal count, in which event the output line 112 goes high, and provides the clock signal to the flip-flops 92 and 102, as well as to two additional JK flip-flops 116 and 118 which reclock the response messages being received on line 60 as will be hereinafter explained. The use of the counter 114 essentially permits the circuitry to examine the initial high start data bit to determine if it is a legitimate data bit as opposed to a short duration noise pulse or the like. Since the clock rate to the counter 114 is 16 times the data rate, and by virtue of its being preset to a count of seven, its terminal count which produces a high signal on line 112 will occur in the middle of a legitimate start bit. A second counter 120 is provided adjacent the counter 114 and effectively provides a high output on line 122 when it has received 10 counts, corresponding to the full 10 bit word. This is accomplished by presetting the counter to five and incrementing it until it reaches its terminal count of 15. While it is also clocked at the same rate at counter 114 by line 124 which has a signal that is the inverse of the clock signal on line 100 by virtue of having passed through an inverter 126, it is effectively only clocked at the same rate as the data messages and this is accomplished in the following manner. The output line 112 of the counter 114 is applied to two terminals of the counter 120 and these terminals must be high for the counter 120 to count and this only occurs at the terminal count of the counter 114. Thus, whenever the counter 114 reaches its terminal count, the counter 120 is incremented by one and after it has generated 10 counts, it reaches its terminal count which provides a high signal on line 122 that is applied to the K input of flip-flop 92 and resets it. As will be explained, this essentially turns off the counters and the reclocking circuitry is then ready to receive another 10 bit message.
To start the counters 114, the high start bit on line 34 results in line 98 going low and this line provides one input of a NAND gate 128, the other inputs of which are supplied by lines 130, 96 and 134 which are normally high before data is received. When line 98 goes low, output line 136 of the NAND gate 128 will go high and this line is connected to the load input of the counters 114 and 120 which takes them out of the load condition and enables them to start counting. Thus, when the start bit of the data message is received, the counters are permitted to run. After a total of 10 bits has been reclocked through the flip-flops 92 and 102, the counter 120 reaches it terminal count and a high is produced on line 122 which will reset the flip-flop 92. This causes the Q output line 130 to go high at the next clock transition which will result in the AND gate 128 having a low output on line 136 which will place the counters back in their load condition, in essence turning them off. This is a desired result, since the 10 bits of data have been reclocked through the flip-flop 194 as desired.
The Q output of the flip-flop 92 appearing on line 130 also accomplished the task of maintaining the counters on during the receipt of 10 bits of data since the active data between the start and stop bits will include low bits. This is accomplished by providing a low signal on line 130 whenever the data contains logical 0 or low bits, since a low level on lne 130 will maintain a high output from the NAND gate 128 that is connected to the load inputs of the counters 114 and 120. Whenever the active data in the 10 bit stream is a logical 1 or high level which would also include the high start and stop bits, line 98 will be low which will cause the NAND gate 128 to maintain its high output.
When a response message from a more distant local controller is received on line 60 and is to be reclocked toward the control console 10, the high start bit on line 60 is applied to NAND gate 148, the other input of which is supplied by line 140 and latter of which is normally high when the USART 36 is not transmitting and when the flip-flop 92 is reset. Thus, the high start bit on line 60 causes the NAND gate 148 to have its output line 134 switched from a normally high signal to a low signal which will cause NAND gate 128 to produce a high signal on line 136 which will start the counter 114 as is desired. The data will then be reclocked by flip-flops 116 and 118 in the manner substantially as described with respect to the flip-flops 92 and 102. When flip-flop 116 is clocked, its Q output on line 96 is applied to the NAND gate 128 which maintains its output high to permit the counter to keep running and the low signal on line 96 is also applied to an AND gate 152 having an output line 154 that will be held low and maintain the flip-flop 92 in its reset condition which prohibits its operating to reclock any data that may appear on line 34. This is important when it is considered that operation of the opto-isolator 24 by the response message being reclocked will be detected by the opto-isolator 22 and will be present on line 34 during operation and it is important that the flip-flops 92 and 102 not reclock this reflected message back toward the direction that the response message is originating. The Q output line 96 of the flip-flop 116 is also applied to the NAND gate 35 which causes its output line 98 to be held low and this precludes the reflected message that is present on line 34 from being received by the USART 36 as desired. The data on line 64 is passed through the flip-flop 66 onto line 70, since line 68 from the USART 36 will be normally high when it is not transmitting. Similarly, when it is transmitting, the other input of the NAND gate 66, i.e., line 64 will be normally high when no data is being received, so that the data being transmitted from the USART 36 onto line 68 will be gated onto line 70 as is desired. The USART 36 has an output line 156 which is connected to an inverter 158 that will provide a low signal on line 94 when it is transmitting so that the USART 36 will not receive its own transmission since it will be reflected and appear on line 34 by virtue of the operation of the opto-isolators 24 and 22 as previously mentioned.
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P.Free format text: ASSIGNS ENTIRE INTEREST. SUBJECT TO REORGANIZATION AGREEMENT DATED JUNE 14, 1982;ASSIGNOR:GENERAL ATOMIC COMPANY;REEL/FRAME:004081/0313Effective date: 19821029Jul 11, 1988ASAssignmentOwner name: GENERAL ATOMICSFree format text: CHANGE OF NAME;ASSIGNOR:GA TECHNOLOGIES, INC.,;REEL/FRAME:004914/0588Effective date: 19880201RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services