Source: https://patents.google.com/patent/CN108962876A/en
Timestamp: 2020-01-29 14:13:29
Document Index: 586962646

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CN108962876A - POP structure and forming method thereof - Google Patents
POP structure and forming method thereof Download PDF
CN108962876A
CN108962876A CN201810603222.0A CN201810603222A CN108962876A CN 108962876 A CN108962876 A CN 108962876A CN 201810603222 A CN201810603222 A CN 201810603222A CN 108962876 A CN108962876 A CN 108962876A
CN201810603222.0A
陈旭贤
叶恩祥
吕孟升
陈承先
2012-10-11 Priority to US13/649,941 priority Critical patent/US8975726B2/en
2012-10-11 Priority to US13/649,941 priority
2013-05-06 Application filed by 台湾积体电路制造股份有限公司 filed Critical 台湾积体电路制造股份有限公司
2013-05-06 Priority to CN201310162895.4A priority patent/CN103730434A/en
2018-12-07 Publication of CN108962876A publication Critical patent/CN108962876A/en
238000000465 moulding Methods 0 abstract 3
239000002957 persistent organic pollutant Substances 0 abstract 1
POP structure and forming method thereof.A kind of device includes the top seal engaged with bottom package.Bottom package includes moulding material；The component pipe core moulded in moulding material；Penetrate the component through-hole (TAV) of moulding material；And the redistribution line above component pipe core.Top seal includes being encapsulated in discrete passive component therein.Discrete passive component is electrically connected with redistribution line.
POP structure and forming method thereof
The application be submitted on May 06th, 2013 application No. is 201310162895.4 entitled " POP structures And forming method thereof " application for a patent for invention divisional application.
The present invention relates to POP structures and forming method thereof.
In Application of integrated circuit, more and more functions are integrated into product.For example, it may be desirable to will such as 3G view Frequency element, WiFi element, bluetooth element and audio/video element different function element be integrated together to form application.
In traditional Integrated Solution, different components is bonded to intermediary layer, which is further bonded to encapsulation Substrate.For example, in mobile application, can be used this scheme engagement power management integrated circuit chip, transponder chip with And multilayer ceramic capacitor.Obtained packaging part is usually very thick on area and very big.Further, since engaged with intermediary layer Various parts are connect by many electrical connections with intermediary layer, therefore the spacing needs of the electrical connection of intermediary layer are very small, and And as low as about 40nm to 50nm sometimes.So small pitch requirements intermediary layer uses dimpling block (u- convex block), the formation of dimpling block Still suffer from technological challenge.
In order to solve the problems in the existing technology, according to an aspect of the present invention, a kind of device is provided, comprising: Bottom package, the bottom package include: moulding material；The first component pipe core moulded in the moulding material；It wears The component through-hole (TAV) of the saturating moulding material；With the first redistribution line being located above the moulding material；And top envelope Piece installing, the top seal includes the discrete passive component being encapsulated in the top seal, wherein the top encapsulation Part is located above the bottom package and engage with the bottom package, and the discrete passive component with it is described again Distribute line electrical connection.
In the device, the discrete passive component is discrete capacitor.
The device further comprises: the second component pipe core moulded in the moulding material, wherein described first Component pipe core and second component pipe core flush each other.In one embodiment, first component pipe core includes the first electricity Connector, second component pipe core include the second electrical connector, and the end of first electrical connector and described second The end of electrical connector is flushed with the surface of the moulding material.In another embodiment, first component pipe core and institute The second component pipe core is stated to be selected from substantially by power management integrated circuit (PMIC) tube core, transceiver (TRX) tube core and base band pipe Group composed by core.
The device further comprises: on the face opposite with first redistribution line of the moulding material Second redistribution line, wherein second redistribution line is electrically connected by the TAV with first redistribution line.
The device further comprises: including another component pipe core in the top seal, wherein described another One component pipe core is engaged with the bottom package；And it is in the moulding material and electric with another component pipe core Another TAV of connection.
According to another aspect of the present invention, a kind of device is provided, comprising: bottom package, the bottom package packet It includes: moulding material；The first component pipe core moulded in the moulding material；The second device moulded in the moulding material Tube core, wherein the table of the end of the electrical connector of first component pipe core and second component pipe core and the moulding material Face flushes；Multiple component through-holes (TAV) of the moulding material are penetrated, wherein first component pipe core and second device The end of the electrical connector of tube core is flushed with the end of the multiple TAV；First on the first face of the moulding material Redistribution layer, wherein first redistribution layer includes a plurality of first redistribution line；Be located at the moulding material with it is described The second redistribution layer on the second opposite face of first face, wherein second redistribution layer includes a plurality of second redistribution line； And the top seal above the bottom package, wherein the top seal includes being encapsulated in the top envelope Discrete capacitor in piece installing, and the discrete capacitor is engaged with the bottom package.
In the device, the top seal further comprises the third device engaged with the bottom package Tube core.
In the device, the top seal further comprises another moulding material, and the discrete capacitor Device moulds in another moulding material.In one embodiment, another moulding material connects with the bottom package Touching.
In the device, the discrete capacitor is multilayer ceramic capacitor (MLCC).
In the device, the end of the electrical connector of first component pipe core and second component pipe core and institute The bottom surface for stating moulding material flushes.
In the device, first component pipe core is power management integrated circuit (PMIC) tube core, and described Two component pipe cores are transceiver (TRX) tube cores.
According to another aspect of the invention, it provides a method, comprising: form bottom package, form bottom package The step of part includes: that the first component pipe core and the second component pipe core are placed above carrier；It is formed above the carrier multiple Component through-hole (TAV)；First component pipe core, second component pipe core and the multiple TAV are moulded in moulding material； The moulding material is thinned, wherein exposing the multiple TAV's by the moulding material after the thinned step The top of the electrical connector of top and first component pipe core and second component pipe core；With in the moulding material A plurality of first redistribution line (RDL) is formed on first face, wherein a plurality of first RDL is electrically connected with the multiple TAV；And The step of forming top seal, forming top seal includes: that discrete passive component is bonded to the bottom package.
In the described method, the step of forming the top seal further comprises being bonded to third component pipe core The bottom package.
The method further comprises: the discrete passive component is moulded in the moulding material.Implement at one In example, after the step of discrete passive component is bonded to the bottom package, executes and mould the discrete passive The step of device.
The method further comprises: implement die separation with by the top seal and the bottom package with Other packaging parts separate.
The method further comprises: a plurality of 2nd RDL is formed on the second face of the moulding material, wherein described A plurality of 2nd RDL is electrically connected by the multiple TAV with a plurality of first RDL.
To be more fully understood by the present embodiment and its advantage, now using following description taken in conjunction with the accompanying drawings as reference, Wherein:
Fig. 1 to Figure 10 is the intermediate stage that manufacture stacked package (POP) structure is according to some exemplary embodiments Sectional view, wherein being embedded with component pipe core in POP packaging part.
The manufacture and use of the embodiment of the present invention are described in detail below.It should be appreciated, however, that embodiment provides many The applicable inventive concept that can be realized in various specific environments.The specific embodiment discussed is only exemplary, Rather than it limits the scope of the invention.
Stacked package (POP) structure and forming method thereof is provided according to each exemplary embodiment.It shows to form envelope The intermediate stage of assembling structure.Discuss the variation of embodiment.In all each attached drawings and exemplary embodiment, it is identically numbered For indicating identical element.
Fig. 1 to Figure 10 is the sectional view that the intermediate stage of manufacture POP structure is according to some exemplary embodiments.Fig. 1 Carrier 20 and the adhesion coating 22 on carrier 20 are shown.Carrier 20 can be glass carrier, ceramic carrier etc..Adhesion coating 22 It can be formed by the sticker of such as ultraviolet light (UV) glue.
Fig. 2 shows the placement of component pipe core 24 and 25 and the formation of conductive column 28.Such as by adhesion coating 22 in carrier 20 top mask placement device tube cores 24 and 25, and flush it each other.Component pipe core 24 and 25 can be including logic crystalline substance The logical device tube core of body pipe.For example, in some exemplary embodiments, component pipe core 24 and 25 is designed for mobile application Tube core and may include power management integrated circuit (PMIC) tube core and transceiver (TRX) tube core.Although showing two pipes Core 24 and 25, but may be placed over more tube cores in carrier 20 and flush it each other.
Throughout the specification, conductive column 28 is alternatively termed component through-hole (Through AssemblyVia, TAV) 28.In some embodiments, it is pre-formed TAV 28, is then placed it on adhesion coating 22.In an alternate embodiment of the invention, TAV 28 can be formed by plating method.It can implement to plate TAV 28 before placing tube core 24 and 25, and plating TAV 28 can be with It is included in formation seed layer (not shown) above carrier 20, forms and pattern photoresist (not shown), and passing through light TAV 28 is plated on the seed layer portion of photoresist exposure.Then the seed layer portion that photoresist can be removed and be covered by photoresist. Then component pipe core 24 and 25 can be placed on to 20 top of carrier.The material of TAV28 may include copper, aluminium etc..In Fig. 2 In obtained structure, the bottom end of TAV 28 and the bottom surface of component pipe core 24 and 25 are substantially flush.
In some exemplary embodiments, metal column 26 (such as copper post) be formed as component pipe core 24 and 25 top and It is electrically connected with the device in component pipe core 24 and 25.In some embodiments, dielectric layer 27 is formed in component pipe core 24 and 25 Top surface, wherein at least lower part of metal column 26 is located in dielectric layer 27.It the top surface of dielectric layer 27 can also be with the top of metal column 26 End is substantially flush.Optionally, do not form dielectric layer 27, and metal column 26 component pipe core 24 and 25 remainder it is upper Side is stretched out.
With reference to Fig. 3, in 28 upper mold molding moulding material 40 of component pipe core 24 and 25 and TAV.Moulding material 40 fills device It gap between tube core 24 and 25 and TAV 28 and can be contacted with adhesion coating 22.Moreover, moulding material 40 can fill Into the gap between metal column 26.Moulding material 40 may include moulding compound, molded underfill object, epoxy resin or tree Rouge.The top surface of moulding material 40 is higher than the top of metal column 26 and TAV 28.Next, implementing reduction steps, (it, which can be, is ground Mill step) moulding material 40 is thinned until exposing metal column 26 and TAV 28.Obtained structure is shown in FIG. 4.By In reduction steps, the top 28A of the TAV 28 and top 26A of metal column 26 is substantially flush and the top surface with moulding material 40 40A is substantially flush.
Next, forming redistribution line (RDL) 42 above moulding material 40 for connecting 26 He of metal column with reference to Fig. 5 TAV 28.RDL 42 can also interconnect metal column 26 and TAV 28.RDL is formed in dielectric layer 44.In some embodiments, lead to It crosses deposited metal layer, patterned metal layer and the gap filled between RDL 42 with dielectric layer 44 and forms RDL 42.Optional Embodiment in, use mosaic technology to form RDL 42 and dielectric layer 44.RDL 42 may include metal or metal alloy, packet Include aluminium, copper, tungsten and/or their alloy.
The formation of the electrical connector 46 according to some exemplary embodiments is also shown in Fig. 5.The formation of connector 46 can wrap It includes and places solder ball on the expose portion of RDL 42, be then refluxed for solder ball.In an alternate embodiment of the invention, the shape of connector 46 At including executing plating steps to form solder areas above RDL 42, it is then refluxed for solder areas.Connector 46 can also include Metal column or metal column and solder caping (solder cap), can also be formed by plating method.Throughout the specification, it wraps Include component pipe core 24 and 25, TAV 28, moulding material 40 and on the composite structure of RDL 42 and dielectric layer 44 covered be referred to as Packaging part 48, can have wafer form in this step.It in an alternate embodiment of the invention, is not to form electricity in the fabrication stage Connector 46, but electrical connector 46 is formed after the engagement of package parts 58 and 60, which is shown in FIG. 9.
With reference to Fig. 6, implement carrier exchange (carrier switch).In carrier exchange process, carrier 49 is connect first It is bonded to packaging part 48, wherein carrier 20 and 49 is located on the opposing face of packaging part 48.Carrier 49 can be connect by sticker 50 It is bonded to packaging part 48, sticker 50 can be UV glue, adhesive tape etc..Then by make adhesion coating 22 lose adherence by carrier 20 from Packaging part 48 unloads.Then adhesion coating 22 is removed.For example, when adhesion coating 22 is formed by UV glue, it can be by the exposure of adhesion coating 22 In UV light, so that adhesion coating 22 loses adherence, and therefore carrier 20 and adhesion coating 22 can be removed from packaging part 48.
The rear end 28B of TAV 28 is exposed after carrier exchange with reference to Fig. 7.In the illustrated structure, TAV 28 Rear end 28B is flushed with the back side 25A of the back side 24A of component pipe core 24 and component pipe core 25.The rear end 28B of TAV 28 can also be with The surface 40B of moulding material 40 is substantially flush.In some embodiments, implement grinding with slightly 24 He of grinding elements tube core The back side of 25 and TAV28.As grinding as a result, TAV 28 can slightly be stretched in the back side of component pipe core 24 and 25 Out, or flush the end 28B of TAV 28 with surface 40B, 24A and 25A.It is alternatively possible to omit grinding steps.
As shown in figure 8, forming dielectric layer 52 and RDL 54.In some embodiments, dielectric layer 52 is by such as oxide, nitrogen Compound, carbide, carbonitride, their combination and/or their multilayer dielectric material formed.RDL 54 is formed in dielectric It is connect in layer 52 and with TAV 28.Some RDL 54 can extend above component pipe core 24 and 25 and with component pipe core 24 With 25 alignments.Therefore, RDL 54 has fan-in structure.For example, being located at RDL 54 above component pipe core 24 and 25 simultaneously And the part being aligned with component pipe core 24 and 25 connects positioned at 28 top TAV and with RDL 54 with the part being aligned TAV 28 It connects.
Fig. 9 shows the engagement of package parts 58 and 60 Yu packaging part 48.Package parts 58 and 60 can be packaging part, device Tube core and/or passive device etc..In some exemplary embodiments, package parts 58 are component pipe cores, and package parts 60 are Discrete passive component, it is integrated on the same chip that there is no the active devices with such as transistor.For example, ought seal accordingly When piece installing is used for mobile application, package parts 58 can be base band tube core, and package parts 60 are multilayer ceramic capacitors (MLCC).Implement to engage by connector 62 it is, for example, possible to use flip-chip bond, wherein connector 62 may include weldering Material.It should be understood that component pipe core 24,25 and 58 can be arranged to be different from shown exemplary embodiment.For example, PMIC Tube core or TRX tube core can be component pipe core 58, and base band tube core can be one of component pipe core 24 and 25.
After the engagement of package parts 58 and 60, such as the molded package component 58 and 60 in moulding material 64.Mold member Material 64 can be contacted with bottom package 48.Obtained package parts 58 and 60 and moulding compound 64 thus form top seal 66, it is bonded to the bottom package 48 of lower section.Therefore, obtained structure is POP structure.Next, being unloaded from carrier 49 Top seal 66 and bottom package 48.Obtained structure is shown in FIG. 10.It then can be by wafer-level packaging part 48 Multiple POP structures 68 are cut into, wherein each POP structure 68 includes the top envelope engaged with a bottom package 48 Piece installing 66.
In these embodiments, multiple component pipe cores are embedded into bottom package 48 together with TAV 28.Insertion The thickness of formula bottom package 48 is less than the thickness of typical package substrate, and the merging for being less than intermediary layer and package substrate is thick Degree.Therefore, it is bonded to intermediary layer with wherein component pipe core and package parts, which further engages on the package substrate Traditional structure is compared, and obtained POP structure 68 has reduced thickness.Moreover, by component pipe core 24 and 25 and package parts 58 and 60 (Figure 10) are stacked up, without being engaged on same intermediary layer (such as in traditional structure).Therefore, with conventional junction Structure is compared, and the gross area that component pipe core 24 and 25 and package parts 58 and 60 occupy reduces.
According to embodiment, a kind of device includes the top seal engaged with bottom package.Bottom package includes mould Moulding material；The component pipe core moulded in moulding material；Penetrate the TAV of moulding material；And above component pipe core again Distribute line.Top seal includes being encapsulated in discrete passive component therein.Discrete passive component is electrically connected with redistribution line.
According to other embodiments, a kind of device includes top seal and bottom package.Bottom package includes molding Material；The first component pipe core moulded in moulding material；And the second component pipe core moulded in moulding material.First He The end of the electrical connector of second component pipe core is flushed with the surface of moulding material.Bottom package further comprises penetrating molding Multiple TAV of material, wherein the end of the electrical connector of the first and second component pipe cores is flushed with the end of multiple TAV.Bottom Packaging part further comprises the first redistribution layer on the first face of moulding material, wherein the first redistribution layer includes a plurality of First redistribution line, and the second redistribution layer on second face opposite with the first face of moulding material, wherein second Redistribution layer includes a plurality of second redistribution line.Top seal includes being encapsulated in discrete capacitor therein, wherein discrete electric Container is engaged with bottom package.
According to other embodiment, a kind of method includes forming bottom package comprising first is placed above carrier Component pipe core and the second component pipe core；Multiple TAV are formed above carrier；The first component pipe core, are moulded in moulding material Two component pipe cores and multiple TAV；And thinned moulding material.After reduction steps, multiple TAV are exposed by moulding material Top and the first component pipe core and the second component pipe core electrical connector top.The formation of bottom package is further wrapped It includes and forms a plurality of RDL in the one side of moulding material, wherein a plurality of RDL is electrically connected with multiple TAV.This method further comprises shape At top seal comprising discrete passive component is bonded to bottom package.
Although embodiment and its advantage has been described in detail, it is to be understood that can be wanted without departing substantially from appended right In the case where the conception and scope for seeking the embodiment of restriction, various changes, replacement and change are carried out.Moreover, scope of the present application It is not limited in the particular implementation of technique described in this specification, machine, manufacture, material component, device, method and steps Example.It is answered according to the present invention as those of ordinary skill in the art it will be understood that can use according to the present invention existing or modern That develops afterwards is used to execute the substantially the same result of the function or acquisition substantially the same to corresponding embodiment described herein Technique, machine, manufacture, material component, device, method or step.Therefore, appended claims expection includes within its scope Such technique, machine, manufacture, material component, device, method or step.In addition, every claim constitutes and individually implements Example, and the combination of multiple claims and embodiment is within the scope of the invention.
1. a kind of device, comprising:
Bottom package, comprising:
Moulding material；
The first component pipe core moulded in the moulding material, wherein first component pipe core includes metal column, the mould Moulding material is arranged in the gap between the metal column；
Penetrate the component through-hole (TAV) of the moulding material；With
The first redistribution line above the moulding material；And
Top seal, including the discrete passive component being encapsulated in the top seal, wherein the top seal position It is engaged above the bottom package and with the bottom package, and the discrete passive component and described first is again Distribute line electrical connection.
2. device according to claim 1, wherein the discrete passive component is discrete capacitor.
3. device according to claim 1, further comprises: the second component pipe core moulded in the moulding material, Wherein first component pipe core and second component pipe core flush each other.
4. device according to claim 3, wherein first component pipe core include the first electrical connector, described second Component pipe core includes the second electrical connector, and the end of first electrical connector and the end of second electrical connector with The surface of the moulding material flushes.
5. device according to claim 3, wherein first component pipe core and second component pipe core are selected from substantially On the group as composed by power management integrated circuit (PMIC) tube core, transceiver (TRX) tube core and base band tube core.
6. device according to claim 1, further comprises: positioned at the moulding material and first redistribution line The second redistribution line on opposite face, wherein second redistribution line passes through the TAV and first redistribution line electricity Connection.
7. device according to claim 1, further comprises:
Include another component pipe core in the top seal, wherein another component pipe core by solder areas with it is described Bottom package engagement, the solder areas is located at the top of first redistribution line；And
Another TAV being electrically connected in the moulding material and with another component pipe core.
8. device according to claim 1, wherein the bottom surface of the metal column is coplanar with the bottom surface of the moulding material.
9. device according to claim 1, wherein the metal column includes vertical edge.
10. device according to claim 1, wherein the discrete passive component is located above first redistribution line And it is engaged with first redistribution line by solder joints, and wherein the device further includes being located at the solder joints Between another moulding material.
11. a kind of device, comprising:
The first component pipe core moulded in the moulding material；
Top seal is located above the bottom package and engages with the bottom package, wherein the top is sealed Piece installing includes:
Another electrical part is electrically connected to first redistribution line；With
Another moulding compound moulds another electrical part in another moulding compound, wherein another moulding compound be located at The second redistribution line above the moulding material directly contacts.
12. device according to claim 11, wherein another electrical part is discrete passive component.
13. device according to claim 11, further comprises: the second device pipe moulded in the moulding material Core, wherein first component pipe core and second component pipe core flush each other.
14. device according to claim 11, wherein first component pipe core includes metal column, and wherein, described Moulding material is arranged in the gap between the metal column.
15. device according to claim 14, wherein the bottom surface of the metal column and the bottom surface of the moulding material are total Face.
16. device according to claim 11, wherein another electrical part is another component pipe core, and wherein, institute It states another component pipe core and directly engages second redistribution line.
17. device according to claim 11, wherein another electrical part is located above second redistribution line, And wherein, the device further comprise between another electrical part and second redistribution line and with the two The solder areas of electrical interconnection.
CN201810603222.0A 2012-10-11 2013-05-06 POP structure and forming method thereof CN108962876A (en)
US13/649,941 US8975726B2 (en) 2012-10-11 2012-10-11 POP structures and methods of forming the same
US13/649,941 2012-10-11
CN201310162895.4A CN103730434A (en) 2012-10-11 2013-05-06 Pop structures and methods of forming the same
CN201310162895.4A Division CN103730434A (en) 2012-10-11 2013-05-06 Pop structures and methods of forming the same
CN108962876A true CN108962876A (en) 2018-12-07
ID=50454452
CN201810603222.0A CN108962876A (en) 2012-10-11 2013-05-06 POP structure and forming method thereof
US (2) US8975726B2 (en)
CN (2) CN108962876A (en)
TW (1) TWI543310B (en)
US9184128B2 (en) * 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
TWI517343B (en) * 2014-03-25 2016-01-11 恆勁科技股份有限公司 Flip-chip package-on-package structure and its fabrication method
CN106057786B (en) * 2015-04-13 2018-11-30 台湾积体电路制造股份有限公司 3D stacked chip packages part
US9666520B2 (en) 2014-04-30 2017-05-30 Taiwan Semiconductor Manufactuing Company, Ltd. 3D stacked-chip package
US9331021B2 (en) 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9754918B2 (en) 2014-05-09 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US9385110B2 (en) 2014-06-18 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9831214B2 (en) 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US9847317B2 (en) 2014-07-08 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
US9691726B2 (en) * 2014-07-08 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming fan-out package structure
CN104157619B (en) * 2014-08-22 2016-09-28 山东华芯半导体有限公司 A kind of novel PoP stack package structure and manufacture method thereof
US9190367B1 (en) * 2014-10-22 2015-11-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
US9420695B2 (en) * 2014-11-19 2016-08-16 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
US20160172274A1 (en) * 2014-12-16 2016-06-16 Qualcomm Incorporated System, apparatus, and method for semiconductor package grounds
TWI559488B (en) * 2014-12-27 2016-11-21 矽品精密工業股份有限公司 Package structure and fabrication method thereof
US9583472B2 (en) * 2015-03-03 2017-02-28 Apple Inc. Fan out system in package and method for forming the same
US9978729B2 (en) * 2015-03-06 2018-05-22 Mediatek Inc. Semiconductor package assembly
US10368442B2 (en) * 2015-03-30 2019-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method of forming
US9659907B2 (en) * 2015-04-07 2017-05-23 Apple Inc. Double side mounting memory integration in thin low warpage fanout package
US9553001B2 (en) * 2015-04-28 2017-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a molding layer for semiconductor package
US9627288B2 (en) * 2015-05-29 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures and methods of forming the same
US10304769B2 (en) * 2015-08-27 2019-05-28 Intel Corporation Multi-die package
US9881850B2 (en) * 2015-09-18 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
CN105261611B (en) * 2015-10-15 2018-06-26 矽力杰半导体技术(杭州)有限公司 The laminated packaging structure and lamination encapsulating method of chip
US9837378B2 (en) * 2015-10-23 2017-12-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Fan-out 3D IC integration structure without substrate and method of making the same
WO2017078709A1 (en) * 2015-11-04 2017-05-11 Intel Corporation Three-dimensional small form factor system in package architecture
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
CN106876358A (en) * 2015-12-11 2017-06-20 安世有限公司 Electronic component and its manufacture method
US20170236809A1 (en) * 2016-02-16 2017-08-17 Xilinx, Inc. Chip package assembly with power management integrated circuit and integrated circuit die
CN107154385A (en) * 2016-03-04 2017-09-12 讯芯电子科技（中山）有限公司 Stack package structure and its manufacture method
US10276402B2 (en) * 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof
DE112016006656T5 (en) * 2016-03-25 2018-12-06 Intel Corporation Substrate-free system in housing design
US10109617B2 (en) 2016-07-21 2018-10-23 Samsung Electronics Co., Ltd. Solid state drive package
US9997471B2 (en) * 2016-07-25 2018-06-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US20180053746A1 (en) * 2016-08-18 2018-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
US20180076179A1 (en) * 2016-09-09 2018-03-15 Powertech Technology Inc. Stacked type chip package structure and manufacturing method thereof
US10529666B2 (en) * 2016-11-29 2020-01-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10002852B1 (en) 2016-12-15 2018-06-19 Dyi-chung Hu Package on package configuration
US9978731B1 (en) 2016-12-28 2018-05-22 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package module
TWI643305B (en) * 2017-01-16 2018-12-01 力成科技股份有限公司 Package structure and manufacturing method thereof
TWI653725B (en) * 2017-02-08 2019-03-11 南茂科技股份有限公司 Fingerprint package
US10319683B2 (en) * 2017-02-08 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stacked package-on-package structures
US20180286824A1 (en) * 2017-03-30 2018-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming package structure
US20180350708A1 (en) * 2017-06-06 2018-12-06 Powertech Technology Inc. Package structure and manufacturing method thereof
US10217720B2 (en) * 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US20190103386A1 (en) * 2017-09-29 2019-04-04 Advanced Semiconductor Engineering, Inc. Stacked semiconductor package assemblies including double sided redistribution layers
US20190131273A1 (en) * 2017-10-27 2019-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
KR20190101174A (en) 2018-02-22 2019-08-30 삼성전자주식회사 Semiconductor package
CN109300863A (en) * 2018-09-28 2019-02-01 中国科学院微电子研究所 Semiconductor package and method for packaging semiconductor
CN109786271A (en) * 2018-12-29 2019-05-21 华进半导体封装先导技术研发中心有限公司 A kind of three-dimensional stacking encapsulation method and structure
CN102157391A (en) * 2010-01-29 2011-08-17 新科金朋有限公司 Semiconductor device and method of forming thin profile wlcsp with vertical interconnect over package footprint
US20110260336A1 (en) * 2010-04-26 2011-10-27 Nepes Corporation Wafer level semiconductor package and fabrication method thereof
CN102569214A (en) * 2010-12-22 2012-07-11 群成科技股份有限公司 Three-dimensional system-in-package package-on-package structure
TW201230266A (en) * 2010-11-26 2012-07-16 Cambridge Silicon Radio Ltd Multi-chip package
US20120208319A1 (en) * 2010-03-31 2012-08-16 Infineon Technologies Ag Packaged Semiconductor Device with Encapsulant Embedding Semiconductor Chip that Includes Contact Pads
CN102931173A (en) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 Multi-chip wafer level package
JP3619523B2 (en) 1996-12-04 2005-02-09 株式会社ルネサステクノロジ Semiconductor device
US20040187297A1 (en) 2003-03-27 2004-09-30 E Touch Corporation Method of fabricating a polymer resistor in an interconnection via
TWI260079B (en) 2004-09-01 2006-08-11 Phoenix Prec Technology Corp Micro-electronic package structure and method for fabricating the same
US7105920B2 (en) 2004-11-12 2006-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design to improve chip package reliability
US7515434B2 (en) 2004-12-20 2009-04-07 Nortel Networks Limited Technique for enhancing circuit density and performance
US20080006936A1 (en) 2006-07-10 2008-01-10 Shih-Ping Hsu Superfine-circuit semiconductor package structure
US7514797B2 (en) 2007-05-31 2009-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die wafer level packaging
US8093722B2 (en) * 2008-05-27 2012-01-10 Mediatek Inc. System-in-package with fan-out WLCSP
US7704796B2 (en) 2008-06-04 2010-04-27 Stats Chippac, Ltd. Semiconductor device and method of forming recessed conductive vias in saw streets
JP5147678B2 (en) 2008-12-24 2013-02-20 新光電気工業株式会社 Manufacturing method of fine wiring package
EP2460180A1 (en) 2009-07-30 2012-06-06 Megica Corporation System-in packages
US9230898B2 (en) 2009-08-17 2016-01-05 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8102599B2 (en) 2009-10-21 2012-01-24 International Business Machines Corporation Fabrication of optical filters integrated with injection molded microlenses
KR101099578B1 (en) 2009-11-03 2011-12-28 앰코 테크놀로지 코리아 주식회사 Stack Chip Package using RDL and TSV
TWI436463B (en) 2009-12-31 2014-05-01 Advanced Semiconductor Eng Semiconductor package and method for making the same
US8115260B2 (en) 2010-01-06 2012-02-14 Fairchild Semiconductor Corporation Wafer level stack die package
WO2011114774A1 (en) 2010-03-18 2011-09-22 日本電気株式会社 Substrate having integrated semiconductor element, and manufacturing method for same
US8823166B2 (en) 2010-08-30 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar bumps and process for making same
KR101695353B1 (en) 2010-10-06 2017-01-11 삼성전자 주식회사 Semiconductor package and semiconductor package module
KR101236798B1 (en) 2011-02-16 2013-02-25 앰코 테크놀로지 코리아 주식회사 wafer level stack package and method for manufacturing the same
US20120319295A1 (en) 2011-06-17 2012-12-20 Chi Heejo Integrated circuit packaging system with pads and method of manufacture thereof
US8634221B2 (en) 2011-11-01 2014-01-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a method
US8928114B2 (en) 2012-01-17 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Through-assembly via modules and methods for forming the same
US9881894B2 (en) 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
US8723309B2 (en) 2012-06-14 2014-05-13 Stats Chippac Ltd. Integrated circuit packaging system with through silicon via and method of manufacture thereof
US9209156B2 (en) 2012-09-28 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuits stacking approach
US8957525B2 (en) 2012-12-06 2015-02-17 Texas Instruments Incorporated 3D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
US9087765B2 (en) 2013-03-15 2015-07-21 Qualcomm Incorporated System-in-package with interposer pitch adapter
2012-10-11 US US13/649,941 patent/US8975726B2/en active Active
2013-05-06 CN CN201810603222.0A patent/CN108962876A/en active Search and Examination
2013-05-06 CN CN201310162895.4A patent/CN103730434A/en not_active Application Discontinuation
2013-10-09 TW TW102136459A patent/TWI543310B/en active
2015-02-10 US US14/618,446 patent/US9490167B2/en active Active
CN103730434A (en) 2014-04-16
US9490167B2 (en) 2016-11-08
TW201415586A (en) 2014-04-16
US20150155203A1 (en) 2015-06-04
US8975726B2 (en) 2015-03-10
TWI543310B (en) 2016-07-21
US20140103488A1 (en) 2014-04-17
US8946870B2 (en) 2015-02-03 Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
TWI550763B (en) 2016-09-21 Semiconductor device and method of forming 3d inductor from prefabricated pillar frame
TWI614875B (en) 2018-02-11 Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-d fo-wlcsp
CN103325727B (en) 2018-04-10 Form the semiconductor approach and device for being fanned out to packaging body laminated device
CN103035536B (en) 2016-03-09 EMI package and manufacture method thereof
CN103681613B (en) 2017-03-01 There is the semiconductor device of discrete area
US8648470B2 (en) 2014-02-11 Semiconductor device and method of forming FO-WLCSP with multiple encapsulants
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