Source: http://www.google.com/patents/US8173906?dq=4200770
Timestamp: 2017-04-23 13:15:38
Document Index: 492605328

Matched Legal Cases: ['§119', 'Application No. 08', 'Application No. 08250440', 'Application No. 08', 'Application No. 08250440', 'Application No. 200880011449', 'Application No. 200880011449']

Patent US8173906 - Environmental protection coating system and method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAccording to one embodiment of the disclosure, an environmental protection coating comprises a circuit assembly having a first protective dielectric layer and a second dielectric layer. The circuit assembly has an outer surface on which a plurality of discrete electrical components are attached. The...http://www.google.com/patents/US8173906?utm_source=gb-gplus-sharePatent US8173906 - Environmental protection coating system and methodAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8173906 B2Publication typeGrantApplication numberUS 11/848,891Publication dateMay 8, 2012Filing dateAug 31, 2007Priority dateFeb 7, 2007Fee statusPaidAlso published asEP1956872A2, EP1956872A3, EP1956872B1, EP2469993A1, EP2469993B1, US8148830, US8319112, US8857050, US20080185173, US20090288876, US20090290314, US20090291200Publication number11848891, 848891, US 8173906 B2, US 8173906B2, US-B2-8173906, US8173906 B2, US8173906B2InventorsJohn M. Bedinger, Michael A. MooreOriginal AssigneeRaytheon CompanyExport CitationBiBTeX, EndNote, RefManPatent Citations (31), Non-Patent Citations (19), Referenced by (5), Classifications (32), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetEnvironmental protection coating system and method
US 8173906 B2Abstract
According to one embodiment of the disclosure, an environmental protection coating comprises a circuit assembly having a first protective dielectric layer and a second dielectric layer. The circuit assembly has an outer surface on which a plurality of discrete electrical components are attached. The first protective dielectric layer overlays the circuit assembly. The second dielectric layer overlays the first protective dielectric layer and is made of a dielectric material having modulus of elasticity less than 3.5 Giga-Pascal (GPa), dielectric constant less than 2.7, dielectric loss less than 0.008, breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), temperature stability to 300° Celsius, defect densities less than 0.5/centimeter, pinhole free in films greater than 50 Angstroms, capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 10%.
a circuit board having an outer surface, the outer surface comprising a plurality of discrete electrical components that are each manufactured independently of one another;
a first protective dielectric layer of alumina overlying at least a portion of the outer surface of the circuit board and at least one of the plurality of discrete electrical components, the first protective dielectric layer entirely covering the at least one discrete electrical component;
a second dielectric layer overlying the first protective dielectric layer, the second dielectric layer being parylene F, parylene AF-4, or any other parylene having a thickness in the range of approximately 50 to 2000 angstroms, the second dielectric layer entirely covering the at least one discrete electrical component; and
a coupling agent between the first protective dielectric layer and the second dielectric layer.
2. The circuit board assembly of claim 1, further comprising an initial layer of silicon-nitride or silicon-dioxide between the substrate surface and first protective dielectric layer, the initial layer of silicon-nitride or silicon-dioxide having a thickness in the range 25 to 400 Angstroms.
3. The circuit board assembly of claim 1, further comprising an additional protective dielectric layer between the first protective dielectric layer and the second dielectric layer, the additional protective dielectric layer having a thickness in the range of approximately 50 to 2000 angstroms.
4. The circuit device of claim 1, wherein the coupling agent is gamma-methacryloxypropyltrimethoxysilane.
5. The circuit board assembly of claim 1, wherein the plurality of discrete electrical components are selected from the group consisting of resistors, capacitors, inductors, diodes, and transistors, integrated circuits, microwave monolithic integrated circuits, couplers, dividers and transmission lines.
a first protective dielectric layer of alumina overlying and contacting at least a portion of the outer surface of the circuit board, the first protective dielectric layer also overlying and contacting at least one of the plurality of discrete electrical components, the first protective dielectric layer entirely covering the at least one discrete electrical component;
7. The circuit board assembly of claim 6, wherein the coupling agent is gamma-methacryloxypropyltrimethoxysilane.
8. The circuit board assembly of claim 6, wherein the plurality of discrete electrical components are selected from the group consisting of resistors, capacitors, inductors, diodes, and transistors, integrated circuits, microwave monolithic integrated circuits, couplers, dividers and transmission lines.
9. The circuit board assembly of claim 6, wherein the first protective dielectric layer has a thickness in the range of approximately 50 to 2000 angstroms.
a first continuous protective dielectric layer of alumina overlying and contacting at least a portion of the outer surface of the circuit board, the first continuous protective dielectric layer also overlying and contacting two or more of the plurality of discrete electrical components, the first continuous protective dielectric layer entirely covering the two or more discrete electrical components;
a second continuous dielectric layer overlying the first continuous protective dielectric layer, the second continuous dielectric layer being parylene F, parylene AF-4, or any other parylene having a thickness in the range of approximately 50 to 2000 angstroms, the second continuous dielectric layer entirely covering the two or more discrete electrical components; and
a coupling agent between the first continuous protective dielectric layer and the second continuous dielectric layer.
11. The circuit board assembly of claim 10, wherein the coupling agent is gamma-methacryloxypropyltrimethoxysilane.
12. The circuit board assembly of claim 10, wherein the plurality of discrete electrical components are selected from the group consisting of resistors, capacitors, inductors, diodes, and transistors, integrated circuits, microwave monolithic integrated circuits, couplers, dividers and transmission lines.
13. The circuit board assembly of claim 10, wherein the first continuous protective dielectric layer has a thickness in the range of approximately 50 to 2000 angstroms.
This application claims priority under 35 U.S.C. §119(e) of U.S. Provisional Application Ser. No. 60/888,715, entitled “ENVIRONMENTAL PROTECTION COATING SYSTEM AND METHOD,” filed Feb. 7, 2007.
According to one embodiment of the disclosure, an environmental protection coating comprises a circuit assembly having a first protective dielectric layer and a second dielectric layer. The circuit assembly has an outer surface on which a plurality of discrete electrical components are attached. The first protective dielectric layer overlays the circuit assembly. The second dielectric layer overlays the first protective dielectric layer and is made of a dielectric material having modulus of elasticity less than 3.5 Giga-Pascal (GPa), a dielectric constant less than 3.0, a dielectric loss less than 0.008, a moisture absorption less than 0.04 percent, a breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), a temperature stability to 3000 Celsius, pinhole free in films greater than 50 Angstroms, hydrophobic with a wetting angle greater than 45 degrees, capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 30%.
In another embodiment of the disclosure, a method generally includes attaching a number of discrete electrical components to an outer surface of a circuit board and coating the outer surface and discrete electrical components with a first dielectric layer. The discrete electrical components are attached during the assembly level phase of production. The first dielectric layer is a dielectric material having a moisture permeability less than 0.01 gm/meter/day, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength in excess of 8 million volts/centimeter (MV/cm), a sheet resistivity greater than 1015 ohm-centimeter, capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 30%.
In another embodiment of the disclosure, a structure consisting of an environmentally sealed domed lid enclosure is placed locally over the active or passive device region which is sensitive to dielectric loading. The localized enclosure allows utilization of a relatively thick environmental coating to provide improved electrical performance, mechanical protection, and environmental protection. The relatively thick environmental coating described in this disclosure may also eliminate or minimize the occurrence of tin whiskers. The thick environmental coating may be utilized independently or in conjunction with the lid for lower frequency circuit board operation where dielectric loading is a second order concern.
FIG. 8 is an enlarged view showing a component 216, which in this particular case is a field effect transistor (FET). Component 216 has a source 216s, a gate 216 g, and a drain 216 d that are separated from each other by air gap 217. To achieve superior performance, the air gap 217 is maintained by design of gate recess and gate geometry in conjunction with protective dielectric layer 222 and a thin initial layer 221 of silicon-nitride. As can be seen, the combined thicknesses of the first protective dielectric layer 222 and thin initial layer 221 maintain air gaps 17 such that internode capacitance Cgs and Cgd may be reduced. In one particular embodiment this passivation layer includes a thin layer 221 of silicon-nitride in the range of 25 to 400 Angstroms and a low permeability layer 222 of amorphous alumina having a thickness in the range of 50 to 2000 Angstrom. First dielectric layer 222 may also be formed of any of the same materials as first protective dielectric layer 22, described above.
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No. 11/848,891, 12 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8345434 *May 25, 2010Jan 1, 2013Kabushiki Kaisha ToshibaHigh frequency circuit having multi-chip module structureUS8927911 *Jul 20, 2010Jan 6, 2015Ppg Industries Ohio, Inc.Enhanced bus bar system for aircraft transparenciesUS9130752Nov 26, 2012Sep 8, 2015Honeywell International Inc.Tamper-resistant coating for an integrated circuitUS20110017487 *Jul 20, 2010Jan 27, 2011Ppg Industries Ohio, Inc.Enhanced bus bar system for aircraft transparenciesUS20110044016 *May 25, 2010Feb 24, 2011Kabushiki Kaisha ToshibaHigh frequency circuit having multi-chip module structure* Cited by examinerClassifications U.S. Classification174/258, 361/760International ClassificationH05K1/00Cooperative ClassificationH01L2924/14, Y10T29/49146, Y10T29/49982, Y10T29/49124, Y10T29/49155, H01L2924/1305, H01L2224/2929, H01L2224/293, H01L2924/00011, H01L2924/19041, H01L2224/8592, H05K2203/1322, H01L2924/01004, H01L2224/83851, H01L24/83, H01L2224/73265, H05K2201/0195, H01L23/3192, H01L2924/01019, H01L2924/1423, H01L2924/0781, H01L2224/83801, H01L23/4821, H05K2201/0179, H05K3/284, H01L2224/48137European ClassificationH01L23/482A, H01L23/31P12, H05K3/28DLegal EventsDateCodeEventDescriptionAug 31, 2007ASAssignmentOwner name: RAYTHEON COMPANY, MASSACHUSETTSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BEDINGER, JOHN M.;MOORE, MICHAEL A.;REEL/FRAME:019775/0602Effective date: 20070827Oct 21, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services