Source: http://www.google.com/patents/US5413966?dq=7,446,777
Timestamp: 2014-03-17 03:33:50
Document Index: 613670209

Matched Legal Cases: ['application No. 07', 'application No. 07', 'application No. 07', 'application No. 632', 'application No. 632', 'application No. 07']

Patent US5413966 - Shallow trench etch - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA trench mask is formed of two dissimilar layers of material deposited over a substrate. The lower of the two layers is an insulating layer such as silicon dioxide or silicon nitride, or combinations of both, and the upper of the two layers is doped or undoped polysilicon. Together, the two layers are...http://www.google.com/patents/US5413966?utm_source=gb-gplus-sharePatent US5413966 - Shallow trench etchAdvanced Patent SearchPublication numberUS5413966 APublication typeGrantApplication numberUS 08/179,751Publication dateMay 9, 1995Filing dateSep 9, 1993Priority dateDec 20, 1990Fee statusPaidPublication number08179751, 179751, US 5413966 A, US 5413966A, US-A-5413966, US5413966 A, US5413966AInventorsPhilippe SchoenbornOriginal AssigneeLsi Logic CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (10), Referenced by (22), Classifications (39), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetShallow trench etchUS 5413966 AAbstract A trench mask is formed of two dissimilar layers of material deposited over a substrate. The lower of the two layers is an insulating layer such as silicon dioxide or silicon nitride, or combinations of both, and the upper of the two layers is doped or undoped polysilicon. Together, the two layers are patterned in a first etch step to form a trench mask for subsequent etching of trenches in the substrate. The upper layer is deposited to a thickness "t" related to the desired depth "d" of the trenches to be etched. In a second etch step, the trenches are formed in the substrate. In the case of substantially uniform etching of the polysilicon and the substrate, the thickness of the polysilicon is substantially equal to the desired trench depth. In the case of unequal etching of the polysilicon and the substrate, the thickness of the polysilicon is based on the etch rate disparity. In either case, trench etch endpoint detection is provided by clearing of the polysilicon and consequent exposure of the lower layer of the trench mask. In both cases, loading effects during the second etch step are alleviated, or completely eliminated, because both the upper layer and the substrate are silicon-based materials.
What is claimed is: 1. A method of forming isolation trenches adjacent active areas in semiconductor devices, consisting of essentially:applying a first non-patterned layer of a first material over a substrate; applying a second non-patterned layer of a second material, dissimilar from the first material, over the first non-patterned layer; in a first etching step, etching holes through the first and second non-patterned layers directly atop selected areas in the substrate, and exposing a surface of the substrate underlying the first layer, said first etching step being conducted as an anisotropic plasma etch employing a chlorine containing gas and hydrogen bromide; in a second, subsequent etching step, etching the second layer and the substrate until the first layer is exposed, thereby forming trenches in the substrate; wherein: the second layer is applied to a thickness "t" which is a multiple, based on the disparity of the etching rates of the second layer and the substrate, of a desired trench depth "d", and wherein "d" is at most about 1 micrometer. 2. A method according to claim 1, wherein:the first layer is a single or multi-layer of materials selected from the group of silicon dioxide and silicon nitride. 3. A method according to claim 1, wherein:the second layer is polysilicon. 4. A method according to claim 1 wherein:the second layer etches substantially uniformly with the substrate; and the thickness "t" of the second layer is substantially equal to the desired trench depth "d". 5. A method according to claim 1, wherein:the second etching step is a chlorine-based anisotropic polysilicon etch process which contains hydrogen bromide. 6. A method according to claim 1 wherein:the first etching step is continued until the substrate become exposed. 7. A method according to claim 1, wherein:both the second layer and the substrate are silicon-based materials; and loading effects in the second etching step are thereby alleviated. 8. A method according to claim 1, wherein:the first layer is a multi-layer of thin oxide under nitride. 9. A method, according to claim 1, wherein:the thickness of the second layer is a multiple of the depth of the trench. 10. A method, according to claim 1, wherein:the second layer is doped to etch at the same rate as the substrate. 11. A method, according to claim 1, wherein:in the first etching step, etching is performed in a plasma etcher, and the plasma has a total flow of He, HBr and Cl-- containing gases, as follows: the percent of He flow in the total flow is within 0-30% of the total flow; the balance of the total flow is HBr and any chlorine-containing gas such as Cl.sub.2, BCl.sub.3, and HCl; and the percent of He flow in the balance of the total flow is within 30-50%; and wherein: the etcher has a discharge gap "g" and a plasma pressure "p"; the plasma flow has a residence time, and an electrical field having a discharge power is deposited in the plasma; the product of the gap ("g", in cm) times the pressure ("p", in mTorr) divided by the total gas flow ("F", in sccm) related to the residence time is between 0.5 and 1.2; and the ratio of square root of the power deposited in the plasma ("W", in watts) by the pressure "p", or W.sup.1/2 /p, related to the ratio of the electrical field ("E") to the pressure (E/p) is within 0.046 to 0.070. 12. A method, according to claim 1, wherein:in the second etching step, etching is performed in a plasma etcher, and the plasma has a total flow of He, HBr and Cl-- containing gases, as follows: the percent of He flow in the total flow is within 0-30% of the total flow; the balance of the total flow is HBr and any chlorine-containing gases such as Cl.sub.2, BCl.sub.3, and HCl; and the percent of HBr flow in the balance of the total flow is weithin 30-50%; and wherein: the etcher has a discharge gap "g" and a plasma pressure "p"; the plasma flow has a residence time, and an electrical field having a discharge power is deposited in the plasma; the product of the gap ("g", in cm) times the pressure ("p", in mTorr) divided by the total gas flow ("F", in sccm) related to the residence time is between 0.5 and 1.2; and the ratio of the square root of the power deposited in the plasma ("W", in watts) by the pressure "p", or W.sup.1/2 /p related to the ratio of the electrical field ("E") to the pressure (E/p) is within 0.046 to 0.070. 13. A method, according to claim 1, wherein:the second layer etches at a lower rate than the substrate. 14. A method, according to claim 1, wherein:the second layer etches at a higher rate than the substrate. 15. A method according to claim 1 wherein the etch rate of the second layer may be adjusted by the varying the doping level of the second layer.
16. A method according to claim 1 wherein trenches are formed in substrates comprising GaAs.
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of application Ser. No. 07/779,838, filed on Jun. 24, 1991, now abandoned, which is a continuation-in-part of commonly-owned U.S. patent application No. 07/711,624, now U.S. Pat. No. 5,290,396, entitled TRENCH PLANARIZATION TECHNIQUES and filed on Jun. 06, 1991 by Pasch and Schoenborn, which is a continuation-in-part of commonly-owned U.S. patent application No. 07/632,461, now U.S. Pat. No. 5,242,536, entitled ANISOTROPIC POLYSILICON ETCHING PROCESS and filed on Dec. 20, 1990 by Schoenborn.
TECHNICAL FIELD OF THE INVENTION The present invention relates to the fabrication of semiconductor devices and, more particularly, to techniques for forming trenches, such as for isolation structures.
BACKGROUND OF THE INVENTION Electrical isolation of semiconductor integrated transistors from one another can be achieved by laterally (in the plane of the wafer) isolating "active" regions of the device with insulating material. Two techniques are common: 1) selectively oxidizing wafer silicon surrounding the active region by means of Low Temperature Oxidation (LTO), Local Oxidation of Silicon (LOCOS), or the like, or 2) depositing insulating material, such as silicon dioxide in trenches formed around the active regions.
Regarding the latter technique (trench formation and filling), trenches are typically etched (e.g. plasma etched) into the substrate around the active regions to a depth "d" of from a few hundred Angstroms (Å) to a few microns (μm). A patterned mask, such as silicon dioxide or silicon nitride, is used for etching the trenches, and an etchant such as fluorine and/or chlorine containing gases, are normally used for etching the substrate selectively (preferentially) to the mask material. Commonly, the resulting trenches are overfilled with silicon dioxide ("oxide"), and excess oxide (that which is not within the trench) is removed, such as by polishing--as disclosed in commonly-owned, copending U.S. patent application No. 07/711,624, entitled TRENCH PLANARIZATION TECHNIQUES, and filed on Jun. 06, 1991 by Schoenborn and Pasch.
FIG. 1 shows a semiconductor device 110, including a substrate 112, an etched trench 114 of width "w" and depth "d" adjacent (surrounding) diffusion regions 116, and a mask layer 118 having an opening 120 for allowing etchants 122 to form the trench 114. Ultimately, the trench will be filled with an insulating material, and will form an isolation structure.
The mask 118 can be composed of several layers. In the case of the top layer of the mask 118 being nitride, the bottom layer would be a stress-reducing buffer oxide. The important factor is that layer(s) 118 be designed such that it protects the substrate during trench etch and fulfills subsequent requirements, such as acting as a polish stop layer if a uniform trench-fill insulating material is further planarized by mechanical polishing.
The technique illustrated in FIG. 1 is commonly employed, but does not provide a suitable mechanism for endpoint detection. Therefore, in order to form trenches of equal depth, from wafer-to-wafer (e.g., using a single wafer etcher), or from batch-to-batch (e.g., using a batch reactor), etch rate must be very well controlled, and usually must be measured immediately prior to etching.
Furthermore, in the case of trenches having different sizes (widths), loading effects are uneven and the various size trenches will not etch to the same depth. (Etching to the same depth is generally preferred from the viewpoint of device performance consistency and quality of manufacturing.) For a common range of trench widths, ranging from 10 μm to 1 mm, resulting etch depth can vary widely, which is undesirable as it is a difficult effect to control.
Additionally, while trench depth can be measured with a stylus, such a measuring technique is both slow and destructive.
What is needed is a technique for self-controlling trench etch depth.
DISCLOSURE OF THE INVENTION It is therefore an object of the present invention to provide an improved technique for etching trenches, particularly shallow isolation trenches (e.g., less than 1 μm deep) in semiconductor devices.
It is another object of the present invention to provide a built-in endpoint detection mechanism in the trench etching process.
It is another object of the present invention to provide a technique for etching trenches which alleviates loading problems associated with etching trenches of different sizes (widths).
According to the invention, two dissimilar layers of material are deposited over a substrate, and together they are patterned in a first etch step to form a trench mask for subsequent etching of trenches in the substrate. The lower layer is an insulating layer such as silicon dioxide or silicon nitride, and the upper layer is a layer of undoped polysilicon deposited to a thickness "t" related to the desired depth "d" of the trenches.
As in the prior art, the nitride (e.g., lower) layer may be a composite layer of nitride and stress-reducing buffer oxide. Hereinafter, this layer is simply referred to as a "mask" layer.
In a second etch step ("trench etch"), the trenches are formed in the substrate. In the case of substantially uniform etching of the polysilicon and the substrate, the thickness of the polysilicon is substantially equal to the desired trench depth. In the case of unequal etch rates between the polysilicon and the substrate, the thickness of the polysilicon is based on the etch rate disparity. In either case, trench etch endpoint detection is provided by clearing of the polysilicon and consequent exposure of the first mask layer. In both cases, loading effects during the silicon trench etch step are alleviated, or completely eliminated, because both the top layer and the substrate are silicon-based materials.
By using the technique of the present invention, manufacturability of semiconductor devices is improved. Resulting trench depth will be more uniform and predictable. Hence, process "uptime" can be significantly increased, and a reduction in failures will be experienced.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a prior art semiconductor structure, illustrating the process of etching trenches for isolation structures.
FIG. 2A is a cross-sectional view of a semiconductor structure, formed according to the present invention, prior to trench etching.
FIG. 2B is a cross-sectional view of the semiconductor structure of FIG. 2A, at a later stage in fabrication, after a first etch step and prior to the trench etch step, according to the present invention.
FIG. 2C is a cross-sectional view of the semiconductor structure of FIG. 2B, at a yet later stage in fabrication, after the trench etch step wherein a trench is formed, such as for an isolation structure, according to the present invention. At this point, any suitable trench-filling technique can be employed to fill the resulting trench.
It should be understood that while only one semiconductor structure is shown, the present invention is applicable to a plurality of such structures on a semiconductor device.
DETAILED DESCRIPTION OF THE INVENTION FIG. 1 shows a semiconductor trench structure and trench etching technique of the prior art, and has been discussed hereinabove.
FIG. 2A shows an in-process semiconductor structure 210, according to the present invention. The structure 210 includes a substrate 212, including within the substrate an area 214 (within the dashed lines) in which an isolation trench will be formed adjacent diffusion regions (active areas) 216.
A single or multi-layer layer of insulating materials 218, selected from the group of silicon dioxide ("oxide") and silicon nitride, is deposited without patterning over the substrate. As in the prior art, the layer 218 will eventually become patterned, with openings (220 with respect to FIG. 2B) for allowing etching of trenches through the openings. Hence, the material 218 is suitably a common trench etch mask material, and is suitably deposited to a thickness comparable to that in the prior art (e.g., approximately 1000 Å). The layer 218 is hereinafter referred to as a "mask" layer (since it will eventually be etched).
As in the prior art, the mask layer 218 may be composed of several layers, for example a layer of nitride over a stress-reducing buffer oxide.
A non-patterned layer of undoped polysilicon 222 is deposited over the mask layer 218, to a thickness "t". The thickness "t" is established to be related, and preferably substantially equal to the ultimate depth "d" of the trench 214' to be formed (see FIG. 2C).
A patterned layer of photoresist 224 is deposited over the polysilicon layer 222, and has openings 226 directly over the areas 214 where trenches are to be formed.
The structure 210 of FIG. 2A is now etched to create openings 220 (one opening 220 shown) through the polysilicon and mask layers directly over the inchoate isolation trench area 214. A suitable recipe for plasma etching through the polysilicon and mask layer is a chlorine-based anisotropic polysilicon etch process which may contain hydrogen bromide (HBr), while a fluorocarbon-based anisotropic oxide/nitride etch would be suitable in defining the mask layer.
Etching with HBr is disclosed in copending, commonly-owned U.S. patent application No. 632,461, entitled ANISOTROPIC POLYSILICON ETCHING PROCESS and filed on Dec. 20, 1990 by Schoenborn, the disclosure of which is incorporated by reference herein.
Generally, the first etching step proceeds until silicon (substrate 212) is exposed, and this endpoint is suitably detected by observing the appearance of silicon from the substrate 212 in the etching environment and/or observing the appearance and subsequent disappearance of material from the mask layer 218 in the etching environment. In either case, etching in the first step continues until the substrate 212 becomes exposed.
Preferably, etching of the single or multi-layer 218 proceeds in one or several steps until silicon (substrate 212) is exposed. In the case of the layer 218 being composed of nitride on top of a thin (&lt;500 Å) oxide, the oxide may be stripped (etched) by wet chemicals such as HF, which has a high selectivity to both silicon and nitride while leaving an undamaged silicon surface 212 prior to trench etch.
The photoresist 224 is then stripped away, using known techniques, and the resulting Structure is illustrated in FIG. 2B.
FIG. 2B shows the semiconductor device 210 of FIG. 2A, after the first etch step and resist strip. As mentioned hereinbefore, holes 220 through the polysilicon and mask layers are formed over the areas 214 in the substrate 212 that are to become trenches for subsequent filling with isolation material (oxide).
Holes 220 having been formed through the polysilicon and mask layers, together they may be considered to be a two-layer "trench mask" (as distinguished from the terminology "mask layer" used to reference the layer 218). The device 210 is now subjected to a second etch step. In this step, the areas 214 are etched to a depth "d", and will become trenches 214', such as isolation trenches filled with oxide. (The process of filling isolation trenches is known.) As noted above, the thickness "t" of the polysilicon layer 222 is related to (a function of) the desired trench depth "d".
Advantageously, in the trench (second) etch step, the entire surface being etched is silicon-based material--native silicon in the case of the substrate 212, and deposited polysilicon in the case of the layer 222. Hence, loading effects are substantially alleviated (in some cases, to zero). This is in marked contrast to the techniques of the prior art (see FIG. 1), where loading effects can be profoundly manifest and troublesome.
The loading effect is well described by Mogab (C. J. Mogab, "The Loading Effect in Plasma Etching", J. Electrochem. Soc., 124, 1262 (1977)), and can manifest itself not only at the wafer scale but also at a microscopic level whereby the etch rate at a particular location on the wafer or within a device depends on local properties of the surface, such as exposed area, or proximity of a narrow trench to wide open trenches as opposed to having a regular pattern made of features with similar geometries. On the wafer scale, a loading effect may result in dissimilar trench depths depending on products with different trench isolation areas.
Further, a built-in endpoint detection mechanism is provided in the trench (second) etch step. Since etching is intended to proceed until the polysilicon layer 222 is substantially removed (cleared), when this occurs the mask layer 218 will become exposed, slightly etched, and detected in the etching environment.
A suitable recipe for plasma etching in the trench etch step is a chlorine-based anisotropic polysilicon etch process which may contain hydrogen bromide. Reference is again made to U.S. patent application No. 632,461. This recipe will etch the polysilicon 222 and wafer 212 substantially uniformly. Hence, with substantially similar etch rates for the polysilicon 222 and wafer 212, the thickness "t" of the polysilicon layer 222 would be established to be substantially equal to the desired trench depth "d". In the case where the polysilicon and wafer etch at dissimilar rates (and these rates are readily determined), the thickness "t" of the polysilicon layer can be established as a simple multiple of the desired trench depth "d"--in other words, as a function of the etch rate disparity. To the effect of forming a trench of depth "d" at the time when the layer 222 is substantially removed from the wafer, the polysilicon 222 may be doped so as to adjust its etch rate with respect to the silicon 212. In either case, the target is continuing etching (in the trench etch step) until the polysilicon is substantially etched away--resulting in the etching of trenches of a desired depth.
In all (first and second/trench) etch steps, etching is continued until a material dissimilar from that being etched becomes exposed. As mentioned hereinabove, this phenomenon is readily observable. Various techniques for detecting the appearance of a dissimilar substance in the etching environment are known, and include optical techniques such as collecting the plasma emission intensity at a particular wavelength and monitoring its change at endpoint, and other techniques such as monitoring a particular gaseous species by mass-spectrometry, the concentration of which changes at endpoint.
As mentioned hereinabove, various techniques are known for subsequently filling the trenches, which in the case of the isolation trenches discussed herein, would be a subsequent step in device fabrication. (There may be other steps in-between, which do not affect the mechanical structure, such as implant, trench oxidation, etc.) Specific reference is made to the techniques for filling and planarizing isolation trenches disclosed in commonly-owned, copending U.S. patent application No. 07/711,624, entitled TRENCH PLANARIZATION TECHNIQUES and filed on Jun. 06, 1991 by Pasch and Schoenborn, incorporated by reference herein.
The techniques for constructing trenches disclosed herein are also applicable to devices based on gallium arsenide (GaAs) as opposed to silicon. For example, in the formation of silicon-based microsensors (micromachining), a multi-layer trench mask (e.g., deposited oxide on polysilicon) could be applied over an "initial" layer of oxide wherein the oxide should not be etched down to the silicon substrate. Again, it is preferable that the materials for the two layers of the two-layer trench mask be selected so that the top layer of the trench mask etches substantially uniformly with the initial layer, and the bottom layer of the trench mask is a dissimilar material providing convenient endpoint detection for the second etch step.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3479237 *Apr 8, 1966Nov 18, 1969Bell Telephone Labor IncEtch masks on semiconductor surfacesUS4019248 *Jun 16, 1975Apr 26, 1977Texas Instruments IncorporatedHigh voltage junction semiconductor device fabricationUS4032373 *Oct 1, 1975Jun 28, 1977Ncr CorporationMethod of manufacturing dielectrically isolated semiconductive deviceUS4038110 *Jun 14, 1976Jul 26, 1977Ibm CorporationPlanarization of integrated circuit surfaces through selective photoresist maskingUS4256534 *Jul 31, 1978Mar 17, 1981Bell Telephone Laboratories, IncorporatedDevice fabrication by plasma etchingUS4276557 *Dec 29, 1978Jun 30, 1981Bell Telephone Laboratories, IncorporatedIntegrated semiconductor circuit structure and method for making itUS4470874 *Dec 15, 1983Sep 11, 1984International Business Machines CorporationPlanarization of multi-level interconnected metallization systemUS4473598 *Jun 30, 1982Sep 25, 1984International Business Machines CorporationMethod of filling trenches with silicon and structuresUS4484979 *Apr 16, 1984Nov 27, 1984At&T Bell LaboratoriesTwo-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layerUS4490209 *Dec 27, 1983Dec 25, 1984Texas Instruments IncorporatedPlasma etching using hydrogen bromide additionUS4493142 *May 7, 1982Jan 15, 1985At&T Bell LaboratoriesIII-V Based semiconductor devices and a process for fabricationUS4508815 *Nov 3, 1983Apr 2, 1985Mostek CorporationRecessed metallizationUS4520041 *Nov 3, 1983May 28, 1985Tokyo Shibaura Denki Kabushiki KaishaMethod for forming metallization structure having flat surface on semiconductor substrateUS4541168 *Oct 29, 1984Sep 17, 1985International Business Machines CorporationMethod for making metal contact studs between first level metal and regions of a semiconductor device compatible with polyimide-filled deep trench isolation schemesUS4545852 *Jun 20, 1984Oct 8, 1985Hewlett-Packard CompanyPlanarization of dielectric films on integrated circuitsUS4609809 *Mar 16, 1984Sep 2, 1986Hitachi, Ltd.Method and apparatus for correcting delicate wiring of IC deviceUS4666553 *Aug 28, 1985May 19, 1987Rca CorporationMethod for planarizing multilayer semiconductor devicesUS4671851 *Oct 28, 1985Jun 9, 1987International Business Machines CorporationMethod for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing techniqueUS4708770 *Jun 19, 1986Nov 24, 1987Lsi Logic CorporationPlanarized process for forming vias in silicon wafersUS4758306 *Aug 17, 1987Jul 19, 1988International Business Machines CorporationStud formation method optimizing insulator gap-fill and metal hole-fillUS4775550 *Jun 3, 1986Oct 4, 1988Intel CorporationSurface planarization method for VLSI technologyUS4789648 *Oct 28, 1985Dec 6, 1988International Business Machines CorporationMethod for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud viasUS4791073 *Nov 17, 1987Dec 13, 1988Motorola Inc.Trench isolation method for semiconductor devicesUS4793895 *Jan 25, 1988Dec 27, 1988Ibm CorporationIn situ conductivity monitoring technique for chemical/mechanical planarization endpoint detectionUS4851097 *Dec 24, 1987Jul 25, 1989Seiko Instruments Inc.Apparatus for repairing a pattern filmUS4876217 *Mar 24, 1988Oct 24, 1989Motorola Inc.Method of forming semiconductor structure isolation regionsUS4876223 *Oct 20, 1988Oct 24, 1989Kabushiki Kaisha ToshibaMethod of manufacturing semiconductor devicesUS4879257 *Nov 18, 1987Nov 7, 1989Lsi Logic CorporationPlanarization processUS4879258 *Aug 31, 1988Nov 7, 1989Texas Instruments IncorporatedIntegrated circuit planarization by mechanical polishingUS4892614 *Mar 10, 1989Jan 9, 1990Texas Instruments IncorporatedIntegrated circuit isolation processUS4892845 *Aug 31, 1984Jan 9, 1990Texas Instruments IncorporatedMethod for forming contacts through a thick oxide layer on a semiconductive deviceUS4894351 *Feb 16, 1988Jan 16, 1990Sprague Electric CompanyMethod for making a silicon IC with planar double layer metal conductors systemUS4897150 *Jun 29, 1988Jan 30, 1990Lasa Industries, Inc.Method of direct write desposition of a conductor on a semiconductorUS4897364 *Feb 27, 1989Jan 30, 1990Motorola, Inc.Method for locos isolation using a framed oxidation mask and a polysilicon buffer layerUS4897365 *Nov 23, 1987Jan 30, 1990Sgs Microelecttronica S.P.A.Reduced-beak planox process for the formation of integrated electronic componentsUS4898841 *Jun 16, 1988Feb 6, 1990Northern Telecom LimitedMethod of filling contact holes for semiconductor devices and contact structures made by that methodUS4900689 *Dec 8, 1988Feb 13, 1990Harris CorporationMethod of fabrication of isolated islands for complementary bipolar devicesUS4901132 *Jan 31, 1989Feb 13, 1990Texas Instruments IncorporatedSemiconductor integrated circuit with switching bipolar transistors having high withstand voltage capabilityUS4902641 *Jul 31, 1987Feb 20, 1990Motorola, Inc.Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structureUS4903109 *Mar 2, 1987Feb 20, 1990U.S. Philips Corp.Semiconductor devices having local oxide isolationUS4903112 *Jun 22, 1988Feb 20, 1990Siemens AktiengesellschaftSemiconductor component with contact holeUS4905062 *Feb 17, 1989Feb 27, 1990Texas Instruments IncorporatedPlanar famos transistor with trench isolationUS4905073 *Jul 3, 1989Feb 27, 1990At&T Bell LaboratoriesIntegrated circuit with improved tub tieUS4906592 *Mar 14, 1989Mar 6, 1990Bull S.A.Method for forming a multilayered metal network for bonding components of a high-density integrated circuit using a spin on glass layerUS4906593 *Mar 4, 1988Mar 6, 1990Fujitsu LimitedMethod of producing a contact plugUS4906595 *Jul 21, 1989Mar 6, 1990U.S. Philips CorporationMethod of manufacturing a semiconductor device, in which a silicon wafer is provided at its surface with field oxide regionsUS4907063 *May 20, 1987Mar 6, 1990Hitachi Microcomputer Engineering, Ltd.Semiconductor body, and device formed therefrom, having grooves with silicon nitride on the groove surfacesUS4907066 *Feb 22, 1988Mar 6, 1990Cornell Research Foundation, Inc.Planar tungsten interconnect with implanted siliconUS4908683 *Aug 11, 1987Mar 13, 1990Harris CorporationTechnique for elimination of polysilicon stringers in direct moat field oxide structureUS4910155 *Oct 28, 1988Mar 20, 1990International Business Machines CorporationWafer flood polishingUS4910168 *May 6, 1988Mar 20, 1990Mos Electronics CorporationMethod to reduce silicon area for via formationUS4912062 *May 20, 1988Mar 27, 1990Motorola, Inc.Method of eliminating bird's beaks when forming field oxide without nitride maskUS4914056 *Dec 5, 1988Apr 3, 1990Kabushiki Kaisha ToshibaMethod of manufacturing a semiconductor device having tapered pillarsUS4916087 *Aug 29, 1989Apr 10, 1990Sharp Kabushiki KaishaMethod of manufacturing a semiconductor device by filling and planarizing narrow and wide trenchesUS4916494 *Oct 6, 1987Apr 10, 1990Robert Bosch GmbhMonolithic integrated planar semiconductor system and process for making the sameUS4916514 *May 31, 1988Apr 10, 1990Unisys CorporationIntegrated circuit employing dummy conductors for planarityUS4918510 *Oct 31, 1988Apr 17, 1990Motorola, Inc.Compact CMOS device structureUS4920070 *Nov 27, 1987Apr 24, 1990Fujitsu LimitedMethod for forming wirings for a semiconductor device by filling very narrow via holesUS4920401 *Mar 14, 1985Apr 24, 1990Nippon Telegraph & Telephone Public Corp.Bipolar transistorsUS4924284 *Jan 20, 1988May 8, 1990International Business Machines CorporationMethod of trench fillingUS4927780 *Oct 2, 1989May 22, 1990Motorola, Inc.Encapsulation method for localized oxidation of siliconUS4929996 *Jun 29, 1988May 29, 1990Texas Instruments IncorporatedTrench bipolar transistorUS4931409 *Jan 30, 1989Jun 5, 1990Kabushiki Kaisha ToshibaMethod of manufacturing semiconductor device having trench isolationUS4933303 *Jul 25, 1989Jun 12, 1990Standard Microsystems CorporationMethod of making self-aligned tungsten interconnection in an integrated circuitUS4935095 *Jun 21, 1985Jun 19, 1990National Semiconductor CorporationGermanosilicate spin-on glassesUS4935378 *Mar 18, 1988Jun 19, 1990Kabushiki Kaisha ToshibaMethod for manufacturing a semiconductor device having more than two conductive layersUS4935804 *Mar 3, 1988Jun 19, 1990Fujitsu LimitedSemiconductor deviceUS4939105 *Aug 3, 1989Jul 3, 1990Micron Technology, Inc.Planarizing contact etchUS4940507 *Oct 5, 1989Jul 10, 1990Motorola Inc.Lapping means and methodUS4942137 *Aug 14, 1989Jul 17, 1990Motorola, Inc.Self-aligned trench with selective trench fillUS4944836 *Oct 28, 1985Jul 31, 1990International Business Machines CorporationChem-mech polishing method for producing coplanar metal/insulator films on a substrateUS4946550 *Feb 21, 1989Aug 7, 1990U.S. Philips CorporationForming electrical connections for electronic devicesUS4946800 *Aug 6, 1973Aug 7, 1990Li Chou HMethod for making solid-state device utilizing isolation groovesUS4948742 *Nov 20, 1989Aug 14, 1990Mitsubishi Denki Kabushiki KaishaMethod of manufacturing a semiconductor deviceUS4950617 *Jan 12, 1989Aug 21, 1990Kabushiki Kaisha ToshibaMethod of manufacturing semiconductor deviceUS4952274 *May 27, 1988Aug 28, 1990Northern Telecom LimitedMethod for planarizing an insulating layerUS4952524 *May 5, 1989Aug 28, 1990At&T Bell LaboratoriesSemiconductor device manufacture including trench formationUS4952525 *Dec 11, 1989Aug 28, 1990U.S. Philips CorporationMethod of manufacturing a semiconductor device in which a silicon wafer is locally provided with field oxide regionsUS4954214 *Jan 5, 1989Sep 4, 1990Northern Telecom LimitedMethod for making interconnect structures for VLSI devicesUS4954458 *Apr 4, 1988Sep 4, 1990Texas Instruments IncorporatedMethod of forming a three dimensional integrated circuit structureUS4954459 *Jul 3, 1989Sep 4, 1990Advanced Micro Devices, Inc.Method of planarization of topologies in integrated circuit structuresUS4956313 *Oct 11, 1988Sep 11, 1990International Business Machines CorporationVia-filling and planarization techniqueUS4956314 *May 30, 1989Sep 11, 1990Motorola, Inc.Differential etching of silicon nitrideUS4957873 *Sep 21, 1989Sep 18, 1990Stc PlcProcess for forming isolation trenches in silicon semiconductor bodiesUS4959325 *Feb 24, 1989Sep 25, 1990Micron Technology, Inc.Reduction of electric field effect in the bird's beak region of a DRAM cell following expansion of active region through local encroachment reductionUS4963951 *Nov 29, 1985Oct 16, 1990General Electric CompanyLateral insulated gate bipolar transistors with improved latch-up immunityUS4966861 *Apr 25, 1989Oct 30, 1990Fujitsu LimitedVapor deposition method for simultaneously growing an epitaxial silicon layer and a polycrystalline silicone layer over a selectively oxidized silicon substrateUS4980019 *Jul 28, 1989Dec 25, 1990Intel CorporationEtch-back process for failure analysis of integrated circuitsUS4980311 *Nov 23, 1988Dec 25, 1990Seiko Epson CorporationMethod of fabricating a semiconductor deviceUS4985740 *Jun 1, 1989Jan 15, 1991General Electric CompanyPower field effect devices having low gate sheet resistance and low ohmic contact resistanceUS5006482 *Oct 25, 1989Apr 9, 1991International Business Machines CorporationForming wide dielectric-filled planarized isolation trenches in semiconductorsUS5011788 *Dec 15, 1988Apr 30, 1991Hitachi, Ltd.Process of manufacturing semiconductor integrated circuit device and product formed therebyUS5015602 *May 10, 1990May 14, 1991U.S. Philips CorporationMethod of manufacturing a semiconductor device having a planarized constructionUS5069002 *Apr 17, 1991Dec 3, 1991Micron Technology, Inc.Apparatus for endpoint detection during mechanical planarization of semiconductor wafersUS5091289 *Apr 30, 1990Feb 25, 1992International Business Machines CorporationProcess for forming multi-level coplanar conductor/insulator films employing photosensitive polyimide polymer compositionsUS5091330 *Dec 28, 1990Feb 25, 1992Motorola, Inc.Method of fabricating a dielectric isolated areaUS5094972 *Jun 14, 1990Mar 10, 1992National Semiconductor Corp.Means of planarizing integrated circuits with fully recessed isolation dielectricUS5102822 *Oct 23, 1990Apr 7, 1992Thomson Hybrides Et MicroondesPlanar-type microwave integrated circuit with at least one mesa component, method of fabrication thereofUS5104482 *Mar 5, 1991Apr 14, 1992Lam Research CorporationSimultaneous glass deposition and viscoelastic flow processUSRE32207 *Sep 30, 1982Jul 15, 1986At&T Bell LaboratoriesMethod for making integrated semiconductor circuit structure with formation of Ti or Ta silicide* Cited by examinerNon-Patent CitationsReference1"Chemical Vapor Deposited Device Isolation With Chemical/Mechanical Planarization", IBM Technical Disclosure Bulletin, vol. 29, No. 2, Jul. 1986, pp. 577-579.2"Thin Film Process"; Vossen et al; pp. 497-521; 1987.3 *Chemical Vapor Deposited Device Isolation With Chemical/Mechanical Planarization , IBM Technical Disclosure Bulletin, vol. 29, No. 2, Jul. 1986, pp. 577 579.4 *English translation of the Japanese Kokai No. 62 120028.5English translation of the Japanese Kokai No. 62-120028.6 *Glass Planarization By Stop Layer Polishing , Beyer, Mendel, Plikin, Riseman, 1985, IBM TDB, vol. 27 No. 8, pp. 4700 4701. pp. 577 579.7Glass Planarization By Stop-Layer Polishing, Beyer, Mendel, Plikin, Riseman, 1985, IBM TDB, vol. 27 No. 8, pp. 4700-4701. pp. 577-579.8 *Thin Film Process ; Vossen et al; pp. 497 521; 1987.9 *Trench Planarization Technique , C. W. Koburger, 1984, IBM (TDB), vol. 27 No. 6, pp. 3242 32433.10Trench Planarization Technique, C. W. Koburger, 1984, IBM (TDB), vol. 27 No. 6, pp. 3242-32433.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5766823 *Sep 22, 1997Jun 16, 1998Kabushiki Kaisha ToshibaMethod of manufacturing semiconductor devicesUS5814547 *Oct 6, 1997Sep 29, 1998Industrial Technology Research InstituteForming different depth trenches simultaneously by microloading effectUS6124206 *Dec 29, 1997Sep 26, 2000Siemens AktiengesellschaftReduced pad erosionUS6136712 *Sep 30, 1998Oct 24, 2000Lam Research CorporationMethod and apparatus for improving accuracy of plasma etching processUS6165907 *May 2, 1997Dec 26, 2000Kabushiki Kaisha ToshibaPlasma etching method and plasma etching apparatusUS6194321 *Aug 19, 1998Feb 27, 2001Micron Technology, Inc.Semiconductor processing methods utilizing boron and nitrogen, and semiconductor wafers comprising boron and nitrogenUS6200902 *Mar 31, 1998Mar 13, 2001Nec CorporationMethod of etching a layer in a semiconductor deviceUS6251791 *Jul 20, 1999Jun 26, 2001United Microelectronics Corp.Eliminating etching microloading effect by in situ deposition and etchingUS6270622Apr 10, 2000Aug 7, 2001Lam Research CorporationMethod and apparatus for improving accuracy of plasma etching processUS6277752 *Jun 28, 1999Aug 21, 2001Taiwan Semiconductor Manufacturing CompanyMultiple etch method for forming residue free patterned hard mask layerUS6475919 *Jan 3, 2001Nov 5, 2002Infineon Technologies AgMethod for producing trenches for DRAM cell configurationsUS6503813Jun 16, 2000Jan 7, 2003International Business Machines CorporationMethod and structure for forming a trench in a semiconductor substrateUS6511920Jun 14, 2001Jan 28, 2003Applied Materials, Inc.Optical marker layer for etch endpoint determinationUS6524961 *Jul 22, 1999Feb 25, 2003Hitachi, Ltd.Semiconductor device fabricating methodUS6569737 *Mar 28, 2001May 27, 2003Hyundai Electronics Industries Co., Ltd.Method of fabricating a transistor in a semiconductor deviceUS6746881Nov 17, 2000Jun 8, 2004Atmel, Nantes SaMethod and device for controlling the thickness of a layer of an integrated circuit in real timeUS6867143Jun 22, 2000Mar 15, 2005International Business Machines CorporationMethod for etching a semiconductor substrate using germanium hard maskUS6919259 *Oct 21, 2002Jul 19, 2005Taiwan Semiconductor Manufacturing Co., LtdMethod for STI etching using endpoint detectionUS7087498Sep 30, 2003Aug 8, 2006Agere Systems Inc.Method for controlling trench depth in shallow trench isolation featuresUS7354834 *Dec 26, 2003Apr 8, 2008Dongbu Electronics Co., Ltd.Semiconductor devices and methods to form trenches in semiconductor devicesUS8071460 *Dec 4, 2008Dec 6, 2011Seiko Instruments Inc.Method for manufacturing semiconductor deviceCN101459060BDec 12, 2008Aug 15, 2012精工电子有限公司Method for manufacturing semiconductor device* Cited by examinerClassifications U.S. Classification438/421, 257/E21.312, 438/714, 257/E21.555, 257/E21.55, 257/E21.244, 438/702, 257/E21.241, 257/E21.195, 257/E21.547, 148/DIG.50, 438/718, 438/717, 257/E21.314International ClassificationH05K3/46, H01L21/762, H01L21/28, H01L21/3105, H01L21/3213, H05K1/11Cooperative ClassificationY10S148/05, H01L21/32139, H01L21/76227, H01L21/28026, H05K3/4644, H05K1/115, H01L21/76235, H01L21/7621, H01L21/31053, H01L21/32137, H01L21/3105European ClassificationH01L21/762C2, H01L21/3213D, H01L21/3105, H01L21/3213C4B2, H01L21/3105B2, H01L21/28E2B, H01L21/762B2C, H01L21/762C6ALegal EventsDateCodeEventDescriptionNov 3, 2006FPAYFee paymentYear of fee payment: 12Jun 13, 2002FPAYFee paymentYear of fee payment: 8Aug 24, 1998FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google