Source: http://www.google.com/patents/US20030128702?dq=6322901
Timestamp: 2016-05-25 19:45:42
Document Index: 491024137

Matched Legal Cases: ['art 701', 'art 701', 'art 704', 'art 726', 'art 727', 'art 727', 'art 727', 'art 726', 'art 727']

Patent US20030128702 - Communication method and apparatus for assigning device identifier - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA communication system carries out communication between a master device and one or more groups of multiple slave devices. In addition to bus 5 that connects master device 1 and multiple slave devices 30, the communication system also has multiple daisy chain connection lines 7-1˜N that connect multiple...http://www.google.com/patents/US20030128702?utm_source=gb-gplus-sharePatent US20030128702 - Communication method and apparatus for assigning device identifierAdvanced Patent SearchPublication numberUS20030128702 A1Publication typeApplicationApplication numberUS 10/314,809Publication dateJul 10, 2003Filing dateDec 9, 2002Priority dateDec 28, 2001Also published asDE60233858D1, EP1326172A2, EP1326172A3, EP1326172B1Publication number10314809, 314809, US 2003/0128702 A1, US 2003/128702 A1, US 20030128702 A1, US 20030128702A1, US 2003128702 A1, US 2003128702A1, US-A1-20030128702, US-A1-2003128702, US2003/0128702A1, US2003/128702A1, US20030128702 A1, US20030128702A1, US2003128702 A1, US2003128702A1InventorsMasahito Satoh, Hitoshi Kondoh, Shigetoshi NakaoOriginal AssigneeMasahito Satoh, Hitoshi Kondoh, Shigetoshi NakaoExport CitationBiBTeX, EndNote, RefManPatent Citations (13), Referenced by (84), Classifications (8), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetCommunication method and apparatus for assigning device identifier
US 20030128702 A1Abstract
A communication system carries out communication between a master device and one or more groups of multiple slave devices. In addition to bus 5 that connects master device 1 and multiple slave devices 30, the communication system also has multiple daisy chain connection lines 7-1˜N that connect multiple devices 30 in a daisy chain DC. By using the daisy chain, a device identifier can be automatically assigned to each slave device in the slave device group, or a sequential number in a sequence for allocating a sharable resource is assigned to each slave device. Images(16) Claims(26)
1. A communication system having multiple devices, and carries out communication among the multiple devices, comprises: buses that connect the multiple devices to each other and daisy chain connection lines that connect the multiple devices into a daisy chain. 2. The communicator system as in claim 1, wherein the multiple devices comprises a master device and one or more groups of multiple slave devices; wherein communication is carried out between the master device and each of the multiple slave devices, wherein the buses connect the master device and each of the one or more groups of multiple slave devices; wherein the daisy chain connection lines connect each of the one or more groups of multiple slave devices in a daisy chain. 3. The communication system as in claim 1, wherein daisy chain connection lines are used to assign a device identifier to each of the multiple slave devices for identifying the number of each device among the multiple slave devices or identifying the number of a device in a prescribed order in the system. 4. The communication system as in claim 2, wherein the one or more groups comprise multiple groups of the multiple slave devices. 5. The communication system as in claim 2, wherein that the daisy chain connection lines are used to assign device identifiers to the multiple slave devices of the one or more groups. 6. The communication system as in claim 5, wherein each of the daisy chain connection lines is set for each of the one or more groups of slave devices. 7. The communication system as in claim 6, wherein the one or more groups of slave devices connected to each of the multiple daisy chain connection lines have the corresponding identifier of the daisy chain connection lines connected to the devices. 8. The communication system as in claim 5, wherein the system also has an apparatus for assigning device identifiers to the one or more groups of multiple slave devices; the device identifier assignment circuit comprises a device identifier assigning token generating circuit, which is set in the most upstream device positioned at the most upstream portion of the daisy chain in the one group of multiple slave devices to send out a device identifier assigning token at a first time point to the downstream of the daisy chain, with the most upstream device having the first device identifier; a memory circuit that is set in the most upstream device to store the first device identifier; a time measuring circuit, which is set in each downstream device located downstream of the daisy chain to measure the time difference between the first and second time points when the device identifier assigning token is received at the second time point; a determining circuit, which is set in each downstream device to determine the device identifier of each downstream device on the basis of the measured time difference; and a memory circuit that is set in each downstream device to store the determined device identifier; in this way, the multiple devices can be identified by using the first device identifier of the most upstream device and each of the device identifiers that are determined for each of the downstream devices and are different from the first device identifier. 9. The communication system as in claim 1 wherein that the buses transmit the information including both data and control signals between the master device and each of the multiple slave devices. 10. The communication system as in claim 2, wherein communication is carried out as time-division multiplex communication. 11. The communication system as in claim 10, wherein the communication is carried out in at least two different transmission bands. 12. The communication system as in claim 11, wherein the communication is carried out using consecutive time slots. 13. The communication system as in claim 12, wherein the different transmission bands are realized by different numbers of time slots in a prescribed time frame. 14. The communication system as in claim 13, wherein the number of time slots used for each of the slave devices is variable. 15. The communication system as in claim 14, wherein the number of time slots used is preset. 16. The communication system as in claim 14, wherein the number of time slots used is 0 or 1 or a larger integer. 17. The communication system as in claim 14, wherein the daisy chain connection lines are used to transfer time-slot allocating token used for allocating time slots to each of the one or more groups of multiple slave devices of the one or more groups of multiple slave devices. 18. The communication system as in claim 17, wherein each of the group of multiple slave devices, when the time-slot allocation token is transferred among the one or more groups of multiple slave devices and when a specific slave device receiving the time-slot allocating token uses the time slots, use of the time slots is started when the time-slot allocating token is received; the time slots are used only in the number of time slots used; when use of the time slots in the number of time slots used is finished, use of the time slots is completed; since the time slot that comes after the last time slot used among the time slots is allocated to the next slave device connected in the daisy chain among the groups of multiple slave devices, the time-slot allocating token is transferred to the next slave device. 19. The communication system as in claim 2, wherein the buses are serial buses. 20. The communication system as in claim 19, wherein the communication via the serial buses is carried out during a communication time frame, and the communication time frame is equal to one period of the first reference clock signal. 21. The communication system as in claim 19, wherein the communication via the serial buses is carried out in a communication format that is common to both data and control signals. 22. The communication system as in claim 21, wherein the common communication format includes at least one command field during initialization and at least one command field and at least one data channel field during the operation. 23. The communication system as in claim 22, wherein the command field includes the device identifier. 24. The communication system as in claim 23, wherein when the system has multiple daisy chain connection lines, the command field includes a daisy chain number. 25. The communication system as in claim 2, wherein the buses are parallel buses. 26. The communication system as in claim 2, wherein the system is an audio system.
FIELD OF THE INVENTION [0001] The present invention pertains to a communication method and apparatus for circuits, devices, or other systems having elements connected in a daisy chain. BACKGROUND OF THE INVENTION [0002] Communication between the various types of integrated circuit chips, units, equipment, etc., that comprise circuits, apparatuses, and other systems requires some means of identifying these constituent parts. There are various methods for identifying these devices of a system. The first method is to use the intrinsic identifier of a device as the device identifier or address for communication within the system. The intrinsic identifier of a device, such as an integrated circuit chip, can be a number, etc. burned in the ROM during manufacturing. Specifications for using such intrinsic device identifiers include JTAG specifications used in testing chip assemblies on boards and IIC (such as: Audio I/F (IIC)) specifications used for many audio products. The second method is to assign an address from outside to the branch, leaf device. The IEEE1394 specification is an example of this method. The third method is to preset an identifier, that is, an address for a device. One such example is the SCSI-2 specification, in which a specific address is preset by an operating system for printers, displays, or other devices. [0003] In the case of the first method using the intrinsic identifier of the device, especially in the case of an integrated circuit chip, the intrinsic identifier depends on the type determined by the manufacturer of the device and the particular functions of the device. An intrinsic device identifier is assigned to each device and is written in the ROM of the device. Consequently, different device identifiers will be assigned to the same type of device manufactured by different manufacturers. As a result, devices used in audio products or other systems cannot be easily replaced with the same types of devices produced by different manufacturers. To make such substitution, the device identifiers in the system of the devices before the substitution must be replaced with the device identifiers of the devices after the substitution. This entails rewriting software, rewriting the contents of ROMs, etc. Another problem is that when multiple devices of the same type are used in a system, the devices assigned with the same device identifier cannot be used. In order to solve this problem, multiple device identifiers must be burned into the ROM for one device so that one of them can be selected when the device is used. Also, in a system that requires other device identifiers besides the intrinsic device identifiers of the devices, new device identifiers or addresses must be assigned to the devices. In addition, the intrinsic identifier of a device is a very long number because it also includes the part for identifying the manufacturer. [0004] In the second method, since it is necessary to assign addresses from the outside to the devices, hardware and software for address assignment are required. [0005] In the third method, since the addresses used by given devices are preset in an operating system, etc., assigning of addresses is limited. Also, the number of devices that can be connected to the system is limited. [0006] Thus, one purpose of the present invention is to provide a communication method and apparatus that can automatically assign identifiers for identifying the numbers of multiple devices in a system to the devices in the system during communication in circuits, apparatuses, and other systems. [0007] Another purpose of the present invention is to provide a communication method and apparatus that can automatically assign identifiers for identifying the sequential numbers in a prescribed sequence, such as the allocation order of a sharable resource, to the devices in a system during communication within the system. [0008] Yet another purpose of the present invention is to provide a variable time-division multiplex communication method and apparatus using the identifiers in the system. SUMMARY OF THE INVENTION [0009] In order to realize the purposes, the present invention provides a communication system including a system comprising multiple devices, the communication system that carries out communication among the multiple devices has buses that connect the multiple devices to each other and daisy chain connection lines that connect the multiple devices in a daisy chain. [0010] According to the present invention, the multiple devices comprises a master device and one or more groups of multiple slave devices. In the communication system, since the master device communicates with each of the multiple slave devices, the buses connect the master device to each group of multiple slave devices. The daisy chain connection lines connect the group of multiple slave devices in a daisy chain. [0011] According to the present invention, the daisy chain connection lines can be used to assign a device identifier to each of the multiple slave devices to identify the number of each device among the multiple slave devices or the sequential number of each device in a prescribed order in the system. [0012] According to the present invention, one or more groups can be comprised of multiple groups of the multiple slave devices. [0013] The daisy chain connection lines can be used to assign device identifiers to the group of multiple slave devices. In this case, each of the daisy chain connection lines can be set for one of the multiple groups of slave devices. In this way, the group of slave devices connected to each of the multiple daisy chain connection lines will have the identifier of the corresponding daisy chain connection line. [0014] According to the present invention, the communication system may also have a device for assigning device identifiers to one group of the multiple slave devices. The device identifier assignment device has the following circuit: a device identifier assigning token generating circuit, which is set in the most upstream device positioned at the most upstream portion of the daisy chain in the group of multiple slave devices to transmit a device identifier assigning token at a first time point to the downstream portion of the daisy chain, with the most upstream device having the first device identifier; a memory circuit that is set in the most upstream device to store the first device identifier; a time measuring circuit, which is set in each downstream device positioned at the downstream portion of the daisy chain to measure the time difference between the first and second time points when the device identifier assigning token is received at the second time point; a determining circuit, which is set in each downstream device to determine the device identifier of each downstream device itself on the basis of the measured time difference; and a memory circuit that is set in each downstream device to store the determined device identifier. In this way, the multiple devices can be identified by using the first device identifier of the most upstream device and each of the device identifiers that are determined for each of the downstream devices and that are different from the first device identifier. [0015] According to the present invention, the buses can transmit information including both data and control signals between the master device and each of the multiple slave devices. [0016] Also, according to the present invention, the communication technique can be time-division multiplexing. In this case, the communication is carried out in at least two different transmission bands. The communication can be carried out using consecutive time slots. The different transmission bands can be realized by different numbers of time slots in a prescribed time frame. The number of time slots used for each of the slave devices can vary. The number of time slots used can be preset. The number of the time slots used can be 0 or 1 or a larger integer. According to the present invention, the daisy chain connection lines can be used to transfer a time-slot allocating token used for allocating time slots to each of the group of multiple slave devices among the group of multiple slave devices. In this case, for each of the group of multiple slave devices, when the time-slot allocating token is transferred among the group of multiple slave devices and when a specific slave device receiving the time-slot allocating token uses the time slots, use of the time slots is started when the time-slot allocating token is received. The time slots are used only in the number of time slots used. When use of the time slots in the number of time slots used is finished, use of the time slots is completed. Since the time slot that comes after the last time slot used among the time slots is allocated to the next slave device connected in the daisy chain among the one group of multiple slave devices, the time-slot allocating token is transferred to the next slave device. [0017] According to the present invention, the buses can be serial buses. In this case, the communication via the serial buses is carried out during a communication time frame, and the communication time frame is equal to one period of the first reference clock. Here, the communication via the serial buses can be carried out in a communication format that is common to both data and control signals. The common communication format includes at least one command field during initialization and at least one command field and at least one data channel field during the operation. The command field can include the device identifier. When the system has multiple daisy chain connection lines, the command field can include a daisy chain number. [0018] The present invention also provides a method for assigning device identifiers to multiple devices. The method comprises the following steps: a step in which the multiple devices are connected in a daisy chain; a step in which a device identifier assigning token is sent at a first time point from the most upstream device positioned at the most upstream portion of the daisy chain among the multiple devices to the downstream portion of the daisy chain, where the most upstream device has the first device identifier; a step in which each of the downstream devices located in the downstream portion of the daisy chain receives the device identifier assigning token at a second time point; and a step in which each downstream device determines the device identifier for itself that is different from the first device identifier on the basis of the time difference between the first and second time points. In this way, the multiple devices can be identified by using the first device identifier of the most upstream device and each of the device identifiers that are determined for each of the downstream devices and that are different from the first device identifier. [0019] According to the present invention, the first time point is determined by the first reference clock pulse, and the time difference is the count value of the number of the second reference clock pulses starting from the first time point. The device identifiers are determined on the basis of the count value. Also, each of the devices has a memory circuit for storing the device identifier. [0020] Also, according to the present invention, the multiple devices are of the same type. The same type of device can be either an input device or output device. [0021] The present invention also provides a device identifying method characterized by the following facts: in a system having a master device and multiple slave devices, the method is used by the master device to identify the multiple slave devices. The method comprises the following steps: A. the master device assigns device identifiers to the multiple slave devices, and the device identifiers of the multiple slave devices are determined by executing the device identifier assignment method; B. the master device identifies the multiple slave devices depending on the device identifiers assigned to the slave devices using the device identifier assignment method. [0022] According to the present invention, the master device can store the device identifiers to be assigned to the multiple slave devices using the device identifier assignment method with a memory means preset in the master device. Or, the master device can receive the device identifiers to be assigned to the multiple slave devices by using the device identifier assignment method from the slave devices and store them in a memory means in the master device. [0023] Also, according to the present invention, the multiple slave devices can be comprised of multiple groups of slave devices. In this case, the device identifiers are assigned to the slave devices in each group by connecting the multiple groups of slave devices in multiple daisy chains. The device group identifiers are assigned to the multiple groups of slave devices connected in the multiple daisy chains. In this way, each slave device in the multiple groups of slave devices can be identified by combining the device group identifier and the device identifier. [0024] The present invention also provides a data transmitting method characterized by the fact that the method is used to transmit data between a master device and multiple slave devices, where the device identifiers obtained by using the device identification method are used, and the master device transmits data to the multiple slave devices. [0025] In addition, the present invention provides a device identifier assigning device characterized by the following facts: the device is used to assign device identifiers to multiple devices; the device is comprised of the following circuits: daisy chain connection lines that connect the multiple devices in a daisy chain; a device identifier assigning token generating means, which is arranged in the most upstream device located in the most upstream portion of the daisy chain in the group of multiple slave devices to transmit a device identifier assigning token at a first time point to the downstream portion of the daisy chain, where the most upstream device has the first device identifier; a memory circuit that is arranged in the most upstream device to store the first device identifier; a time measuring circuit, which is arranged in each downstream device located in the downstream portion of the daisy chain to measure the time difference between the first and second time points when the device identifier assigning token is received at the second time point; a determining circuit, which is arranged in each downstream device to determine the device identifier of the given downstream device on the basis of the measured time difference; and a memory circuit that is arranged in each downstream device to store the determined device identifier. [0026] The present invention also provides a device comprised of an input terminal for connection to the upstream side of a daisy chain, an output terminal for connection to the downstream side of the daisy chain, and a device identifier assignment circuit that assigns a device identifier to the device on the basis of the position of the device in the daisy chain. [0027] According to the present invention, the device identifier assignment circuit has a time measuring circuit that measures the time difference between the first and second time points when the device identifier assigning token sent from the most upstream portion of the daisy chain at the first time point is received at the second time point, a device identifier determining circuit that determines the device identifier of the given device on the basis of the measured time difference, and a memory circuit for storing the determined device identifier. [0028] The present invention also provides a device identification system characterized by the following facts: in a system having a master device and multiple slave devices, the master device identifies the multiple slave devices; the device identification system has the conventional device identifier assigning device and a memory circuit set in the master device for storing the device identifiers of the multiple slave devices assigned by the device identifier assigning device; in this way, the master device is able to identify the multiple slave devices by means of the device identifiers of the slave devices stored in the master device. [0029] According to the present invention, the multiple slave devices can be comprised of multiple groups of slave devices. In this case, the device identifiers are assigned to the slave devices in each group by connecting the multiple groups of slave devices in multiple daisy chains. Device group identifiers are assigned to the multiple groups of slave devices connected in the multiple daisy chains. In this way, each slave device in the multiple groups of slave devices can be identified by combining the device group identifier and the device identifier. BRIEF DESCRIPTION OF THE DRAWINGS [0030] [0030]FIG. 1 is a block diagram illustrating a communication system with the basic configuration disclosed in the embodiment of the present invention. [0031] [0031]FIG. 2 is a block diagram illustrating an audio multi-chip system B as an embodiment of the communication system shown in FIG. 1. [0032] [0032]FIG. 3 is a block diagram illustrating the device ID assignment circuit and the time-slot allocating circuit in each slave device shown in FIG. 2. [0033] [0033]FIG. 4 is a diagram illustrating the communication frame for variable time-division multiplex communication (VTDMCA) used in the system shown in FIG. 2 as well as the format during initialization and operation of the data (PDI input and PDO output) transmitted in the frame. [0034] [0034]FIG. 5 is a diagram illustrating the structure of the command field and expanded command field in the transmission format shown in FIG. 4. FIG. 5(a) shows the command field, FIG. 5(b) shows the expanded command field, and FIG. 5(c) shows the status field. [0035] [0035]FIG. 6 is a flow chart illustrating the operation of the entire audio multi-chip system B shown in FIG. 2. [0036] [0036]FIG. 7 is a diagram illustrating the timing of clock LRCK and BCK used for determining VTDMCA mode. [0037] [0037]FIG. 8 is a timing diagram illustrating various types of signals in the device ID assignment sequence. [0038] [0038]FIG. 9 is a circuit diagram illustrating the details of the device ID assignment circuit 70 shown in FIG. 3. [0039] [0039]FIG. 10 is a timing diagram explaining the operation of the device ID assignment circuit 70 shown in FIG. 9 for the header device (most upstream device). [0040] [0040]FIG. 11 is a timing diagram explaining the operation of the device ID assignment circuit 70 shown in FIG. 9 for the second device on the downstream side of the header device. [0041] [0041]FIG. 12 is a timing diagram explaining the operation of the entire time-slot allocating circuit group shown in FIG. 3. [0042] FIGS. 13(a) and (b) are circuit diagrams illustrating the details of the time-slot allocating circuit 72 shown in FIG. 3. [0043] [0043]FIG. 14 is a circuit diagram illustrating the details of the header token production circuit shown in FIG. 13. [0044] [0044]FIG. 15 is a circuit diagram illustrating the details of the token propagation circuit shown in FIG. 13. [0045] [0045]FIG. 16 is a timing diagram illustrating various types of signals in the time-slot allocating circuit in the case when the header device uses channel ch1 but not channel ch2. [0046] [0046]FIG. 17 is a timing diagram illustrating various types of signals in the time-slot allocating circuit in the case when the header device uses channels ch1-ch4. [0047] [0047]FIG. 18 is a timing diagram illustrating various types of signals in the time-slot allocating circuit in the case when the header device uses two channels by means of the high enable signals of ch1 and ch3. [0048] [0048]FIG. 19 is a timing diagram illustrating various types of signals in the time-slot allocating circuit in the case when the ch1 enable signal is low and only the ch2 enable signal is high in the header device. [0049] [0049]FIG. 20 is a timing diagram illustrating various types of signals in the time-slot allocating circuit in the case when all of the ch enable signals in the header device are low. [0050] [0050]FIG. 21 is a timing diagram illustrating receiving/transmitting of SA token between multiple devices. [0051] [0051]FIG. 22 is a block diagram illustrating a system example, in which the same device is connected in two daisy chains. DETAILED DESCRIPTION [0052] In the following, an embodiment of the present invention will be explained in detail with reference to figures. [0053] First, FIG. 1 shows a communication system A with the present invention incorporated in its basic configuration. As shown in the figure, said system A comprises one master device 1, multiple slave device groups 3-1˜3-N (SDG1-N), and buses 5 that connect each of the slave device groups to master device 1. Each slave device group has at least one or, as shown in the figure, multiple slave devices, that is, slave devices 30-1-1˜30-1-N or 30-2-1˜30-2-N. Each of the slave devices is connected to bus 5. Also, communication system A has at least one daisy chain, such as DC1˜DCN. Each daisy chain corresponds to one slave device group. One daisy chain is related to the slave devices in the corresponding group. For example, in slave device group 3-1, daisy chain DC1 is formed by connecting multiple slave devices in the form of a daisy chain using daisy chain connection line 7-1. Daisy chain connection lines 7-2˜7-N are used for other slave device groups. [0054] In the communication system A shown in FIG. 1, commands or other control signals and data are transmitted via bus 5 between master device 1 and each slave device 30 in slave device groups SDG1˜N. The bus is a serial bus. However, it is also possible to use parallel buses. The identifiers of the devices used for the transmission are automatically assigned by each of daisy chains DC1˜DCN arranged in slave device groups 3-1˜3-N. In other words, the device identifier (device ID) of each of slave devices 30-1-1˜30-1-N in slave device group SDG1 is assigned by daisy chain DC1 by transmitting device ID assigning token or resource allocation token (to be described later) between the slave devices. If the device IDs assigned by daisy chain DC1 to slave devices 30-1-1˜30-1-N are preset during design of the system, these device IDs can be pre-stored in the memory of master device 1. If the device identifiers cannot be determined when designing the system, the device IDs to be assigned to the slave devices can also be kept in the master device and assigned by a circuit of communication between the master device and the slave devices. In the configuration shown in FIG. 1, since there are multiple slave device groups, in order to distinguish the slave devices between the device groups, it is necessary to use slave device group identifiers and daisy chain identifiers. The slave device group identifiers are stored in the ROM or RAM for slave devices set in each slave device group or can be set from an external setting terminal (H is “1,” L is “2”). [0055] As described above, the device ID (including the case of using slave device group identifier) assigned to each of the slave devices can be used as the number of a slave device in communication system A, that is, the number in system or as a sequential number in a prescribed sequence, such as the allocation sequence of a sharable resource, in the system. [0056] For example, as will be explained below, the present system A can be operated using VTDMCA (variable time division multiplex command and audio data). For example, for the variable time division multiplex command and audio data, there are multiple consecutive time slots in each communication time frame. When these time slots are allocated to each of multiple channels, the system can be operated using a certain communication format to conduct communication. [0057] In the following, an audio multi-chip system B as another embodiment of the communication system A of the present invention shown in FIG. 1 will be explained with reference to FIG. 2. The system B has a digital signal processor DSP 1B as master device as well as N slave devices 30-1-1B, 30-1-2B . . . 30-1-NB (only two shown in the figure) as input (IN) device groups and N slave devices 30-2-1B, 30-2-2B . . . 30-2-NB (only two shown in the figure) as output (OUT) device groups. Consequently, system B has two slave device groups. In this case, the IN devices (devices receiving input from DSP) include digital/analog converter (DAC) and other devices, while OUT devices (devices that output to DSP) include analog/digital converter (ADC) and other devices. As will be described below, the system may also include CODECs or other IN/OUT devices and PLLs and other NO devices with no input/output used for signal processing. System B has conductors 50B and 52B as the buses for connecting DSP 1B and IN devices 30-1-1B˜NB as well as OUT devices 30-2-1B˜NB. In other words, one connection line is used for the transmission from the master device to the multiple slave devices, while another connection line is used for the transmission from the multiple slave devices to the master device. Also, conductor 60 is used to supply frame synchronizing clock signal, while conductor 62 is used to supply port synchronizing clock signal. System B also has daisy chains for the two slave device groups, that is, daisy chain DC1B for devices 30-1-1B˜NB in the IN device group and daisy chain DC2B for devices 30-2-1B˜NB in the OUT device group. As will be described below, for device ID (device ID), a “1” is assigned to IN device 30-1-1B, while a “2” is assigned to IN device 30-1-2B. Similarly, for device ID, a “1” is assigned to OUT device 30-2-1B, while a “2” is assigned to OUT device 30-2-2B. In order to distinguish between these two device groups, a slave device group identifier is assigned by pre-burning the identifier in the ROM of the devices that belong to each group. For example, a “1” is assigned to the IN device group, while a “2” is assigned to the OUT device group. [0058] More specifically, any general digital signal processor can be used as DSP 1B. It includes a port to supply the frame synchronizing clock signal for determining the communication frame (FSX) used for transmitting and the communication frame (FSR) used for receiving, a port to supply the port synchronizing clock signal (CLKX) for transmitting and the port synchronizing clock signal (CLKR) for receiving, as well as the serial ports of the DSP, that is, the data transmitting port DX for transmitting commands and data and the data receiving port DR for receiving the commands and data. On the other hand, each of the IN devices and OUT devices has an LRCK port for receiving the frame synchronizing clock via conductor 60, a BCK port for receiving the port synchronizing clock signal via conductor 62, an input port PDI for receiving commands and data from DSP 1B via conductor 50B, and an output port PDO for outputting status or data to DSP 1B via conductor 52B. In order to assign device ID to each device, each of these ports has an input port DCI and an output port DCO for daisy chain. These ports are connected to either daisy chain connection line 7-1B or 7-2B that constitutes the daisy chain. If the IN device is a DAC, the analog output terminal will not be shown in the figure. Also, if the OUT device is an ADC, its analog input terminal will not be shown in the figure. Only the line transmitting the digital signals is displayed. [0059] In the following, the circuit using a daisy chain to assign device ID (or device number) will be explained in detail with reference to FIG. 3. FIG. 3 only shows two devices, that is, IN device 30-1-1B and 30-1-2B in system B shown in FIG. 2. Other IN devices and OUT devices are the same. IN device 30-1-1B has a device ID assignment circuit 70-1B for assigning device ID to the device and a time-slot allocating circuit 72-1B for allocating a sequential number for use of the bus as a sharable resource (in the present example, a time slot with a specific sequential number among many consecutive time slots in the communication frame) to the device as circuits that constitute part of daisy chain DC1B. The inputs of these circuits are connected to connection line 7-1BU1 on the upstream side of the daisy chain via DCI port, while their outputs are connected to connection line 7-1BD1 on the downstream side via DCO port. Also, connection line 7-1BU1 on the upstream side is connected to a reference voltage, while connection line 7-1BD1 on the downstream side is connected to the upstream connection line 7-1BU2 of the next IN device 30-1-2B. Similarly, IN device 30-1-2B also has ID assignment circuit 70-2B and time-slot allocating circuit 72-2B. Its downstream connection line 7-1BD2 is connected to the upstream connection line of the next IN device. The details of these circuits will be explained below. [0060] In the following, the overall operation of audio multi-chip system B shown in FIG. 2 will be explained with reference to FIG. 4. FIG. 4 shows the format of VTDMCA used in the present system. The frame synchronizing clock signal LRCK has a period of 1/fs, or the reciprocal of frequency fs, which is the same as the sampling frequency of the audio signal. The duty ratio of this clock signal is much smaller than 50% compared with the one with a duty ratio of 50% for the audio serial interface used in conventional audio products. For example, it has interval “H” comprising two periods of clock signal BCK in order to guarantee compatibility with the conventional system by making it possible to distinguish the VTDMCA communication interface of the present invention from the conventional communication interface on the basis of the difference in the duty ratio. The many consecutive time slots in one period of the frame synchronizing clock are determined by the frequency of the port synchronizing clock signal BCK. In this way, correspondence with multi-channels becomes possible, and time-division multiplex communication can be realized. FIG. 4 also shows the input format of the data and commands input/output to the input port PDI of the IN device and OUT device as well as the output format of the data and commands output from the output port PDO during initialization and operation in the communication frame having many consecutive time slots. During initialization, as shown in the figure, the format of input PDI has a command field (CMD) as the header followed by many expanded command fields (EMD). Each field has 32 bits and a length that fits in the period of one time slot. The format of the output PDO from the IN device has consecutive 8-bit status field (STF). Each status field includes status data stored in a register. During operation, the format of input PDI has a 32-bit command field (CMD) as the header followed by audio channel fields (Ch1-Ch(n)) corresponding to n channels ch1-chn. The format of output PDO has an 8-bit status field (STF) as the header followed by audio channel fields Ch1-Ch(m) corresponding to m channels. Since the numbers of the input channels may differ from the number of output channels, the number of channels m and n may differ. In other words, during operation, since the IN device only receives the input data, only the PDI format is used. On the other hand, since the OUT device only sends out the output data, only the PDO format is used. As described above, in the VTDMCA communication of the present invention, a serial bus is used with a time-division multiplex format. [0061] In the following, the command field, expanded command filed, and audio channel field will be explained with reference to FIG. 5. FIG. 5(a) shows the format of the command field. The DID field at the header of the command indicates whether a device ID determining sequence is executed. A “1” bit means that the determining sequence is executed. A “0” bit means that the next command will be executed. The EMD field indicates the presence/absence of the expanded field shown in FIG. 4. If this bit is “1,” the next field is an expanded command field. If it is “0,” the next field is an audio channel field. The daisy chain selecting (DCS) field is used to indicate the slave device group. In the example shown in FIG. 2, 0 is assigned to the IN device, while 1 is assigned to the OUT device. The “device ID” field is the device number assigned by the device ID determining sequence. It is used to identify the device. If the “device ID” field is “0�00,” it means that none of the devices is selected. If it is “0�1F,” it means that all of the devices are selected. This field can be set as the same at one time (such as enable of DAC, on/on of mute, etc.). The “register ID” field is the number assigned to each intrinsic register of the IN device or OUT device. This number is used to identify the register. This field includes a R/W flag, which is used to indicate writing to or reading from the internal register. The “data” field includes the data for the designated internal register of a designated device selected depending on the device ID and register ID. [0062] [0062]FIG. 5(b) shows an expanded command field. This field has the same format as the command field shown in FIG. 5(a) except that the MSB bit is not used (rvd). Also, no expanded command field can be selected after this field. [0063] [0063]FIG. 5(c) shows a status field (STF). It only uses 8 bits, that is, bits 8-15 of 32 bits (8 bits in FIG. 4). The status field is used to read the status of a slave device stored in a register of the slave device in response to the request of a command field or an expanded command field and then send the status to DSP 1B. [0064] Finally, the audio channel field, although not shown in the figure, is used to transmit audio data. Each audio channel field is handled as the audio data of the device selected by the command field that is previous to this field. The audio format can be selected as desired for each device. [0065] As can be seen from the format that has been explained above, registers used for selecting audio channels occupied by each device, although not shown in the figure, are set in the IN device and OUT device used as the slave devices shown in FIGS. 2 and 3. Also, for the purpose of confirmation, it is preferred to use registers for storing the device ID of each device. Also, as described above, the internal register of each device cannot only be used to store the control data but also to read the control data. In the system shown in FIG. 2, PDO port is used as the read port. However, the connections to the PDO ports of all devices can be wired-OR connections by setting the PDO to Hiz output (high impedance, that is, open). Since the read/write timing for the registers is known to the expert in the field, the explanation of its details is omitted. [0066] In the following, the overall operation of the audio multi-chip system B shown in FIG. 2 will be explained with the aid of the flow chart shown in FIG. 6. Also, this flow chart shows the control from the host controller (DSP in this example). First, in step 60, it is determined whether the VGTDMCA communication mode is used. This judgment is usually made at the system design stage. If it is found that no VTDMCA mode is used, the conventional operating mode will be used in step 61. Audio Serial Interface and Host Serial Interface are used in the conventional mode. On the other hand, if it is found that VTDMCA mode is used, the host controller will execute initialization for using the VTDMCA mode in step 62. In other words, the serial port of DSP 1B is initialized to set the length of interval “H” of the frame synchronizing clock LRCK, the number of BCK clocks, the data length, and the frame length, etc. A VTDMCA mode determining sequence is then generated in step 63. Also, when the PDI input (the DID field in FIG. 5(a) is “1”) for initialization shown in FIG. 4 is generated, the device ID determining sequence is started. In this way, the device IDs are assigned automatically to IN devices and OUT devices. Next, in step 64, if necessary, the device IDs of all of the IN devices and OUT devices are confirmed. The confirmation is executed by DSP 1B, which reads the device ID stored in the internal register of each device. In other words, DSP 1B uses the PDI input to send a command on reading the internal register that stores the device ID to each slave device. In response to this command, each slave device uses the PDO output to send the read device ID to DSP 1B. DSP 1B compares the received device ID of each slave device with the device ID of the slave device that is pre-stored in the memory of the DSP itself. Also, in step 64, all of the slave devices are initialized by using the expanded command field (shown in FIG. 5(b)) of the PDI data. After initialization is completed, in step 65, DSP 1B sends the PDI input to IN device or receives the PDO output from OUT device. For example, during operation, for the PDI input to an IN device, DSP 1B first sends a command field of writing or reading to a certain IN device (can be selected as desired), followed by sending the audio channel field. The audio channel field has been allocated by the initialization performed for all of the devices. If the command field is for reading, the contents of the register designated by the command field is output from the PDO port to a status field. The command field for OUT device is also the same. Only the audio channel field is changed to sending of audio data. [0067] In the following, the operation of said system B will be explained in detail with reference to FIGS. 7-21. [0068] [0068]FIG. 7 shows a timing diagram for clock signals LRCK and BCK for DSP (1B) to determine the VTDMCA mode in step 62 in FIG. 6. As shown in the figure, the H (“1”) interval of LRCK is equal to two periods of BCK clock. To prevent faulty operation, VTDMCA mode is confirmed on the side of the IN device and OUT device by a double detection method (in FIG. 7, the first cycle is shown as (pre) VTDMCA frame, and the second cycle is shown as VTDMCA frame). Also, as described above, the reason that the H (“1”) interval of LRCK is equal to two periods of BCK clock is to distinguish from the LRCK 50% duty cycle of Audio Serial Interface in the conventional operating mode. [0069] Next, the timing diagram of the device ID assigning sequence will be explained with reference to FIG. 8. This sequence is executed in step 63 in FIG. 6. The device ID determining sequence is carried out independently for the IN device group and the OUT device group. It is carried out by passing a device ID assigning token (DID token) from the most upstream portion of a daisy chain to the downstream portion. Only IN device will be explained below. However, the operation is the same for the OUT device group. More specifically, the DID token is formed by the reference voltage connected to the most upstream portion of the daisy chain. First, the PDI data input to the PDI port in FIG. 8 includes a command field with the DID field set to “1” in order to start the device ID assigning sequence. The IN device receiving this command is the most upstream IN device in the daisy chain. Since a constantly high DID token is received at the DCI1 port, the device ID=1 is obtained when the clock signal LRCK becomes high. Then, the DID token is passed to the IN device at the downstream portion. The downstream IN device determines its own device ID on the basis of the number of the BCK clock pulses counted until said DID token is received (the identifier is 1 if two clock pulses are counted). As shown in FIG. 8, the IN device that is directly next to the most upstream IN device (called header device) counts the BCK clock pulses until the DCI2 connected to DCO1 becomes high. Therefore a count of 4 means device ID=2. For the next IN device, a count of 6 means device ID=3. In other words, two or more digits of the internal counter are used to determine the device ID. As described above, when the DID token is passed from the most upstream to downstream in the daisy chain, the device IDs of the IN devices can be determined. In summary, depending on the DID field in the command field, all of the slave devices are able to recognize the device ID determining sequence and pass the DID token sequentially from the header slave device synchronously with BCK. Each slave device is able to recognize which number it is connected to during the cycle when “high” occurs at the DCI port. The slave device also outputs the DID token to the next device. By fixing the DCI port of the header device to “1,” device ID=1 can be recognized as the starting point. [0070] By using the device ID determination method of the present invention, even if there are multiple devices of the same type in the same system, the master device, such as a DSP, is able to identify each of them. Compared with the method that simply uses the external terminals of the master device to identify devices, the method of the present invention has the advantage that the number of devices that can be identified is not limited by the number of master device terminals that can be used. In other words, the present invention eliminates the limitation of the conventional method by using a daisy chain. The number of the slave devices can be increased without increasing the number of available terminals of the master device. [0071] In the following, a detailed example of the device ID assignment circuit 70 shown in FIG. 3 for executing the device ID assigning sequence will be explained with reference to FIG. 9. Since other device ID assignment circuits are the same, only circuit 70-2B will be explained in detail. As shown in the figure, device ID assignment circuit 70-2B receives clock signals LRCK and BCK, the device identifier (DID) assigning token from the DCI port, a command for starting the device ID determining sequence, and a system reset signal as the inputs. The circuit generates a DID assigning token output to the DCO port as the output. The starting command is the signal “1” in the DID field in the command field explained in FIG. 8. The system reset signal goes high when the system reset is cancelled. As shown in the figure, the circuit with the inputs and output is approximately comprised of device ID determining sequence start control unit 700, time measurement part 701, device ID memory unit 702, token judging circuit 703, downstream DID assigning token production circuit 704, header device (the most upstream device) judging circuit 705, and header token production circuit 706. More specifically, sequence start control unit 700 has a D-type flip-flop (F/F5) 7000, which has D input, CK input, reset (RST) input, and Q output. The CK terminal receives clock signal LRCK via inverter 7002. When the reset signal is high and the start command is high, F/F5 generates a high Q output in response to clock signal LRCK. The high Q output outputs a signal that indicates the period (equal to the period of 1 frame) from the beginning to the end of the determination sequence. [0072] On the other hand, time measurement part 701 is formed by counter 7010. The counter 7010 has a CLOCK terminal for receiving clock signal BCK and a RESET terminal connected to the output of F/F5. The counter is reset with the falling edge of the Q output of F/F2 received at the RESET terminal and starts to count clock signal BCK received after the device ID determining sequence is started. The counter starts to measure the time after the beginning of the determination sequence and outputs the count value as the time measurement result. Device ID memory unit 702 comprises a +1 adder 7020 and a register 7022. The +1 adder 7020 has its input connected to receive the output of the counter except for the LSB of counter 7010. It adds 1 to the output of the counter and outputs the result. In this way, two periods of clock signal BCK are counted as 1 for the device identifier. Register 7022 has a LATCH terminal for receiving token input and an input connected to the output of +1 adder 7020 in addition to the CLOCK terminal that receives clock BCK. When said register 7022 receives a high token input, it latches the output of the adder as the time measurement result from the beginning of the determining sequence to the time when the token is received in response to clock signal BCK. The output of the adder is stored as the device ID of the corresponding device. The downstream DID assigning token production part 704 included in device ID assignment circuit 70-2B comprises a D-type flip-flop (F/F1) 7040 and a D-type flip-flop (F/F2) 7042. These F/Fs have an RST input for receiving the Q output of F/F5 7000 and a CK terminal for receiving clock signal BCK. Their D inputs are connected in such a way that F/F1 receives a token from token judging circuit 703, and F/F2 receives the Q output of F/F1. With the configuration, F/F1 and F/F2 operate as follows. When these flip-flops receive a token via token judging circuit 703 after they are reset (reset with the falling edge) at the beginning of the determining sequence, the received token is delayed by two periods of clock signal BCK (two-stage F/F), and the delayed token occurs at the Q output of F/F2 as the DID assigning token on the downstream side. The operation described above is the general operation of the devices, including the header device. In the case of the header device, however, since the DID assigning token input is constantly high, it is necessary to generate a special header token. Therefore, as described above, device ID assignment circuit 70-2B also has circuits 703, 705, and 706. [0073] More specifically, token judging circuit 703 has a selector 7030. It has an input for receiving the DID assigning token (it is a constantly high signal for the header device) and an input for receiving the header token (to be described below). It also has a control input for receiving a header device signal for indicating that a device is the header device (when it is high). When the header device signal is high, the selector sends the header token to the output. If it is low, it sends the DID assigning token coming from the upstream portion to the output. Header device judging circuit 705 has a flip-flop (F/F6) 7050 and an AND gate 7052. F/F6 has a reset input for receiving the system reset signal, a CK terminal for receiving clock signal LRCK via inverter 7002, and a D terminal connected to the output of AND gate 7052. The AND gate has an input for receiving the start command and an input for receiving the DID token assigning input. In the case of the header device, since DCI is constantly high, AND gate (AN1) 7052 sends out a high output when the start command goes high. The F/F6 receiving this output generates a high Q output in response to the falling edge of clock LRCK. The output becomes low at the next falling edge of clock LRCK (see FIG. 10). On the other hand, for the downstream devices other than the header device, since the start command and the DCI input cannot be high simultaneously, the Q output of F/F6 is constantly low. In this way, the high Q output of the F/F6 indicates that the device is the header device. [0074] Header token production circuit 706 is used to generate a token specially used for the header device since the DCI is constantly high in the header device. More specifically, circuit 706 has F/F3 7060 and F/F4 7062, inverter 7064, and AND gate (AN2) 7066. F/F3 and F/F4 have a reset terminal for receiving the Q output of F/F5 and a CK terminal for receiving clock BCK. F/F3 has a D terminal for receiving the header device signal (Q output of F/F6), while F/F4 has a D terminal connected to the Q output of F/F3. With this connection, F/F3 and F/F4 delay the front edge of the header device signal by two clock pulses for every clock pulse (see FIG. 10). When receiving the signal obtained by inverting the delayed signal with inverter 7064 and the header device signal, AND gate AN2 generates a signal that is high for over two periods of clock signal BCK at the output since the beginning of the communication frame (falling edge of clock signal LRCK). The output constitutes the header token used for the header device (see FIG. 10). As described above, the header token is supplied to token judging circuit 703. For downstream devices other than the header device, the header device signal is constantly low, and thus the output of AND gate AN2 is constantly low. [0075] In the following, the operation of said device ID assignment circuit 70 will be explained with reference to FIGS. 10 and 11. First, the header device will be explained with reference to the timing diagram shown in FIG. 10. After the system reset signal goes high, clock signal LRCK goes high, and the VTDMCA frame is started. When the start command goes high to indicate the beginning of a device ID determining sequence, the Q output of F/F5 goes high to indicate the device ID determination sequence. As a result, counter 7010 starts to count clock pulses BCK as shown in the figure, and up-counting of the device identifier is started by addition of adder 7020. On the other hand, F/F6 outputs a header device signal indicating that the device is the header device. As a result, a header token that is high for over two clock pulses as shown in the figure is generated via F/F3, 4, etc. Since the header device signal is high, the header token is passed by selector 7030 to its output and supplied to register 7022 and F/F1 . In response to the header token, register 7022 latches the output “1” of the adder at that time and stores it. Said “1” indicates that the device identifier of the device=1. When receiving the header token, F/F1 operates together with F/F2 to delay the header token by two clock pulses to generate a downstream side token, which appears at the Q output of F/F2. As a result of the operation, device identifier=1 is assigned to the header device. [0076] In the following, the device directly next to the header device on the downstream side will be explained with reference to FIG. 11. In the case of the downstream device, as described above, since the Q outputs of F/F6 and F/F3, 4, 5 are all low, the header device signal (the Q output of F/F6) and the header token (output of AN) are low. On the other hand, when a downstream token from the header device is received as a DID assigning token via DCI, since the header device signal is low, the selector 7030 will pass the DID assigning token to its output and supply it to register 7022 and F/F1. Register 7022 latches the output of the adder at that time and stores device identifier=2. In the meantime, F/F1 and F/F2 delay the token by two clock pulses to generate the DID assigning token for the next downstream device. [0077] By performing the operation, each device in the IN device group can determine its own device ID, that is, receive the assigned device ID. When the Q output of F/F5 goes “low,” the determination sequence is terminated. It is only necessary to carry out the determining sequence once during initialization of the system. Consequently, the start command is only generated once during the initialization. During the operation after the initialization, the determined device ID is stored as is in the register. [0078] In the following, the overall operation of the time-slot allocating circuit 72 shown in FIG. 3 will be explained with reference to FIG. 12. This circuit is used to allocate the time slots in a communication frame to each slave device, such as IN device or OUT device, during VTDMCA communication. Also, like the case of device ID assignment circuit 70, the circuit allocates the time slots using the same method independently for the IN device group and the OUT device group. Therefore, only the IN device group shown in FIG. 12 will be explained. As shown in the figure, one communication frame is the period from one rising edge of clock signal LRCK to the next rising edge. The first time slot starts from the rising edge of clock LRCK and is followed by many consecutive time slots. In the example shown in FIG. 12, the command field of PDI input exists in the first time slot, and one of audio channel fields ch1-ch8 exists in each time slot since the second time slot. The period after ch8 is not used in the example shown in the figure. In the example shown in FIG. 12, when each IN device uses 2 channels, the most upstream device (DID=1) uses ch1 and ch2, the next device (DID=2) uses channel uses ch3 and ch4, the further next device (DID=3) uses ch5 and ch6, and the final device (DID=4) uses ch7 and ch8. [0079] After the communication frame starts, the header (most upstream) device with a device ID (DID=1) of number one enables two audio channels, and since the DCI1 port is constantly high, it picks up two channels from the first audio channel field that follows the command field in the PDI input received at the PDI port from DSP (1B). At that time, DCO1 port is at the high level during the period of the time slot of the audio channel field of ch2. As a result, a time-slot allocating token (referred to as time-slot allocating (SA) token hereinafter) is generated and is sent to the next downstream device, that is, the second IN device (DID=2). Since the second IN device also picks up two channel fields, it picks up ch3 and ch4. Similarly, at that time, DCO2 port goes high during the period of the time slot of the audio channel field of ch4 to generate an SA token and pass it to the next downstream device, that is, the third IN device (DID=3). After that, similarly, the final IN device (DID=4) receives the SA token and picks up the audio channel fields of the number of the channels used by itself (two) from the audio channel field that immediately follows. Then, an SA token is generated during the period of the time slot of the final audio channel field (ch8), and the SA token is passed to the next downstream IN device. In this way, time-division multiplex communication is realized. Also, in this example, there is no need for the final IN device (DID=4) to recognize itself as the final device, and it outputs an SA token downstream. Also, variable time-division multiplex communication can be realized by allocating a different number of time slots to each device. The timing for the IN device group is the same for the OUT device group. [0080] In the following, the details of the time slot allocating circuit 72 shown in FIG. 3 will be explained with reference to FIGS. 13-15. As shown in FIGS. 13(a) and (b), time-slot allocating circuit 72 approximately comprises time-slot position indicating unit 720, used time-slot indicating unit 721 (FIG. 13(b)), allocated time-slot judging unit 722 (FIG. 13(b)), data retaining unit 724, data storage unit 725, SA (slot allocation) token production part 726, and source token production part 727. Said time-slot position indicating unit 720 comprises a counter (7200) and an AND gate 7202. Counter 7200 has RST terminal for receiving clock signal LRCK, CK terminal for receiving clock signal BCK, and a 5-bit counter output Q1˜Q5. It is reset by the falling edge of clock signal LRCK. When counting of the number of BCK clock pulses generated during one time slot (32 BCK clock pulses) is completed, the 5-bit counter outputs Q1˜Q5 all go high (since counting starts from the second BCK clock pulses all of the bits go high at the count of “31”). The AND gate 7202 having its input connected to each bit of the counter output generates a high output only when all of the bits in the counter output are “1”. The high AND gate output becomes a signal bc3l indicating that each time slot is ended. [0081] Used time slot indicating unit 721 is used to indicate the number of the time slots used by a certain IN device. It is constituted with an N-bit register 7210. N is the total number of channels set in the device. Said register 7210 has channel enable bits from ch1 to chN. When a bit is “1,” the corresponding channel is enabled, that is, the IN device is set to use that channel (or time slot). Consequently, the channel enable bits of “1” constitute the enable signal for use of time slot. Since there are N bits, up to N channels can be assigned to the IN device. In this way, variable time-division multiplex communication can be realized. In this case, the ch1 enable signal is not the ch1 slot shown in FIG. 12. It simply means that the first slot is set to be used by the device. Said register 7210 is included in command register 7212, that is, the internal register of the IN device. Each bit, of register 7210 can be preset in the IN device. It is preferred to prestore these bits in the memory of DSP 1B used as the master device during the system design. However, if the allocation of the time slots to the slave devices is not made available during system design, or if it is made variable, the master device can write the time slot allocation for the slave devices made after system design in the master device into the register 7210 of the command register 7212 of each slave device (using the command field) by means of communication. This can be achieved via shift register 7240 and an address decoding circuit (FIG. 13(b)). The set contents of the register in each slave device can also be received by the master device by means of communication. This can be realized by reading register 7210 of the slave device via the status field output circuit (parallel/series conversion circuit) shown in FIG. (13(b)). Allocated time slot judging unit 722 is comprised of N AND gates 7220-1˜N corresponding to channels 1˜N. Each AND gate 7220 receives one corresponding channel enable signal among ch1-chN at one input. Another input receives the SA (time-slot allocation) token input SA1˜SAN (or DCO) of the same corresponding channel. The third input is connected to receive time-slot starting position indicating signal bc31. Each of SA tokens SA1˜SAN is used to allocate the time slot corresponding to each of audio channel fields 1˜N so that the device can use the time slot. Consequently, the output of each AND gate 7220 is concerned with a certain specific time slot. The use of the time slot (or channel) is enabled, and an SA token is received. Also, a high output will be generated only when a time slot position indicating signal is received. The high output becomes an allocated slot use indication signal, indicating that the time slot when the output is high is the slot allocated to the device (that is, the allocated slot) and is the slot used by the device (that is, the used slot). When the channel enable signal is low, since the time slot is not used by the device, the allocated slot use indication signal is low. [0082] As shown in the figure, data retaining unit 724 is constituted by a shift register 7240. The shift register has a DATA terminal for receiving the packet data, that is, the PDI input from the PDI port and a CK terminal for receiving clock signal BCK. It also has an output terminal for generating the data retained in the shift register. The shift register 7240 can retain data with a length of one packet (or one time slot) for the incoming PDI input. [0083] Data storage unit 725 comprises N audio channel registers 7250-1˜N in the same number as N channels. Each of the registers has an enable EN terminal for receiving the allocated slot use indicating signal from the corresponding AND gate 7222 and a CK terminal for receiving BCK terminal. It also has an input (schematically shown in the figure) connected to the output of shift register 7240. Each register 7250 receives, latches, and stores the packet in the allocated slot (or the allocated channel) from shift register 7240 in response to the allocated slot use indicating signal sent from AND gate 7222. In this way, the IN device can receive data from the allocated and used time slot. The data in register 7250 will be read out for a later processing (in the case of DAC, digital/analog conversion). [0084] Source token production part 727 is a circuit for generating the source token. It generates a header token or outputs an SA token from the upstream portion. Source token production part 727 has a multiplexer (MUX) 7270 and a header token production circuit 7272. One of the inputs of MUX 72720 is connected to the daisy chain input DCI, while the other input is connected to the output of header token production circuit 7272. It also has a control input for receiving the header device signal from a circuit that is the same as header device judging circuit 705 shown in FIG. 9 (one circuit can be shared). Consequently, when the header device signal becomes high, that is, when the device concerned is identified as the header device, the header token from circuit 7272 is passed to the output. If header device signal is low, that is, if the given device is identified as a device other than the header device, the SA token received at the DCI port from the upstream is passed to the output. Header token production circuit 7272 has a BCK terminal for receiving clock signal BCK, an LRCK terminal for receiving clock signal LRCK, and an output for generating the header token. [0085] More specifically, as shown in FIG. 14, header token production circuit 7272 comprises 6-bit counter 72720, AND gate 72722, and OR gate 72724. Counter 72720 has CLK terminal connected to the output of AND gate 72722 and RST terminal connected to receive clock signal LRCK. It also has 6-bit counter output Q1˜Q6. One of the inputs of AND gate 72722 is used to receive clock signal BCK, while the other input is connected to the most significant Q6 terminal. Consequently, when Q6 is low, clock signal BCK is output to counter CLK terminal. When Q6 goes high and thereafter, the supply of the clock signals to the counter CLK terminal is stopped until reset. Consequently, the OR gate that receives counter output Q1˜Q5 generates a high output (see token in FIG. 16) when at least one bit output of the 5-bit counter is high, that is, when the counter output is in the range of 1 to 31 (that is, during the first of all the time slots in the command field). This high OR-gate output constitutes the header token. [0086] Finally, the SA token production part 726 shown in FIG. 13(a) has N series connected token propagation circuits 7260-1˜N corresponding to the N channels. Each token propagation circuit 7260 has a BCK terminal for receiving BCK clock signal, a BC31 terminal for receiving the time slot starting position indicating signal bc31, an enable terminal EN for receiving the channel enable signal of the corresponding channel, an input IN terminal, and an output OUT terminal. The transmitting circuit in the first stage has an input IN terminal for receiving the token from source token production part 727. In each of the following stages, the input IN terminal is connected to the OUT terminal of the previous stage. When the channel enable signal is high, the result at the output OUT terminal of each transmitting circuit is obtained by delaying the token received at the IN terminal by about 1 time slot (almost 32 BCK clock signals). When the channel enable signal is low, the token is passed undelayed to the output. The OUT terminal of 7260-N in the final stage supplies the SA token (SAN) to the next downstream device. In this way, the devices on the downstream side can use the time slots sequentially. The token generated at the OUT terminal of each transmitting circuit becomes the token sent to the next stage or the next downstream device and is used as time-slot allocating token SA1˜SAN in that device. Also, when the channel enable signals of both ch1 and ch2 go high, it means that two channels, that is, two time slots are used. It does not mean that the time slots represented by ch1 and ch2 in FIG. 12 must be used. Consequently, when the device on the upstream of the given device uses ch1 and ch2 shown in FIG. 12, the ch1 and ch2 used by the device concerned are equivalent to the time slots represented by ch3 and ch4 shown in FIG. 12. [0087] More specifically, as shown in FIG. 15, each transmitting circuit 7260 is comprised of multiplexer (MUX) 72600 and an enable control D-type F/F 72602. One of the inputs of MUX 72600 is connected to the IN terminal of the transmitting circuit, while the other input is connected to the Q output of F/F 72602. The control input is connected to the EN terminal. In this way, when the EN terminal is low, the token received at the IN terminal is passed directly. If the EN terminal is high, the output of the MUX, that is, the token at the IN terminal delayed by one time slot is passed to the Q output of the F/F. The D terminal of F/F 72602 is connected to the IN terminal, and the EN terminal is connected to receive bc3l. Also, the F/F has a CLK terminal connected to receive clock BCK. The input signal is latched only when EN is high. Consequently, the F/F will generate a high signal during the next time slot if the signal input from the IN terminal is high if signal bc31 is high. Also, the setting of the channels used by the device concerned is stored in register 7210 as described above. [0088] In the following, the overall operation of time-slot allocating circuit 72 will be explained with reference to the timing diagrams shown in FIGS. 16-21. [0089] First, the operation of a device example, such as the header device, will be explained with reference to FIGS. 16-20. As shown in FIGS. 17-20, the device has a 4-channel processing part. FIG. 16 shows the case in which the header device uses channel ch1 and other channels not shown in the figure except for ch2. More specifically, with the clock signals LRCK and BCK shown in the figure, 5-bit counter 7200 counts as shown in the figure and generates bc31 signal that goes high at the end of each time slot to indicate the end of each time slot. Then, header token production circuit 7272 generates a header token during the first time slot, as shown in the figure. Since the header device uses ch1, ch1 enable signal is high. As a result, token propagation circuit 7260-1 generates a token SA1 delayed by 1 slot at its output. In response to the token, the header device latches and stores the contents of shift register 7240 (data of channel ch1) in register 7250-1. Since ch2 enable signal is low, the next token propagation circuit 7260-2 that receives token SA1 passes SA1 undelayed as token SA2. At that time, the output of AND gate 7220-2 stays low since the ch2 enable signal is low. Consequently, no latching of register 7250-2 occurs. After using other channels, the header device finally generates a token to the downstream at DCO port. In this way, the device can only receive the channel data of the time slots used. [0090] [0090]FIG. 17 shows the case in which the header device uses four channels ch1-ch4 (the channel enable signals of ch1-ch4 are high). In this case, since the enable signals of ch1-ch4 are high, as shown in the figure, each of SA1, SA2, SA3, SA4 (=DCO) is delayed by one slot from the header token. At that time, since the outputs of AND gates 7220-1˜4 are high, latching of registers 7250-1˜4 occurs. Also, token SA4 is output to the DCO port as the token to the downstream device. In this case, variable time-division multiplex communication can be realized since multiple time slots can be used by each device. [0091] [0091]FIG. 18 is a timing diagram illustrating the case when the header device uses two channels as a function of the high enable signals for ch1 and ch3. In this case, since ch2 enable signal is low, token SA2 is the same as token SA1. At that time, since ch3 enable signal is high for AND gate 7220-3, register 7250-3 latches the data in the ch2audio channel field into ch3 register 7250-3 instead of ch2 register 7250-2. Consquently, when two or more received channels are used by one device, the enabled channels are not necessarily consecutive. Under certain conditions, if ch2 and ch4 in the device are not used or if ch1 and ch3 as well as ch2 and ch4 in the device use the same data, such a setting can improve the data transmission efficiency of the master device. In this way, any channel can be specified and used, and there is no need to perform wasted data transmission. In the present example, the number of time slots used is 2. [0092] [0092]FIG. 19 is a timing diagram illustrating the case when only ch2 enable signal is high in the header device. In this case, since ch1 enable signal is low, SA1 is equal to the header token. SA2 is obtained by delaying SA1 by one slot. After that, SA3, etc. is equal to SA2 with no delay. In this case, since only the output of AND gate 7220-2 is high, ch2 register 7250-2 receives the data in ch1 audio channel field. This is an example of using only ch2 of the four channels set in the device. [0093] [0093]FIG. 20 is a timing diagram illustrating the case in which all of the ch enable signals of the device are low; that is, none of the time slots is used. In this case, the header token is transmitted directly to the downstream devices as SA1, SA2, SA3, etc. without being delayed. This use mode can be used when none of the devices is used under certain conditions or when connection of the daisy chain is necessary but there is no need to use any time slot without performing any inputs or outputs. In this case, the number of time slots used is 0. As described above, since use or no use can be set for each channel in a device to avoid wasted data transmission, the transmission efficiency can be improved. [0094] [0094]FIG. 21 is a timing diagram illustrating sending/receiving of SA tokens between multiple devices. It shows an example in which multiple devices are cascade-connected as shown in FIG. 21(i a). Also, device 1 uses 1 channel, device 2 uses 2 channels, device 3 uses none of the channels, and device 4 uses 3 channels. In this case, as shown in the timing diagram of FIG. 21 (b), by using ch1 audio channel field, device 1 generates a token delayed by 1 time slot from the header token at output DCO1. Then, since device 2 uses 2 channels, a token that is further delayed by 2 slots is generated at DCO2. Since device 3 uses no slots, the output token of device 2 is directly output to DCO3 without being delayed. Then, since device 4 uses 3 channels, a token delayed by another 3 slots from the token sent from device 3 is generated at DCO4. In this way, the time-slot allocating token can be transmitted sequentially by using the daisy chain between the devices. Also, since the number of time slots used for each device can be set as desired, in the present example, device 2 has a transmission band twice as wide as that of device 1, and device 4 has a transmission band three times as wide as that of device 1. The transmission band of device 3 is zero. As described above, according to the present invention, variable time-division multiplex communication can be realized using elements configured in a daisy chain. [0095] Data transmission from DSP 1B to IN devices was explained above. Data transmission from OUT devices to DSP 1B can be realized in the same way as described above. The difference is that data sent out to register 7250 are used, and the data are transferred to shift register 7240 and output from the PDO port at the beginning of the allocated slot. Receiving/transmitting of other time slot allocating (SA) tokens and use of the channel enable signals are the same. As can be seen from the explanation, the IN device group and the OUT device group can operate at the same time since they have separate daisy chains so that assigning of the device identifiers and transmission of time-slot allocating tokens can be performed for these groups independently of each other. [0096] A preferred embodiment of the present invention was explained above. This embodiment, however, can be modified in various ways. First, the number of daisy chains can be selected as desired as two or more corresponding to the number of device groups. In this case, it is necessary to store the identifier or number of the daisy chain connection line as the device group identifier in the devices of each daisy chain group. Second, besides DSPs, other programmable devices, such as microprocessors, can be used as the master device. The serial port can be used for data transmission with the slave devices. Third, the device identifiers of the slave devices can also be transmitted from the slave devices to the master device instead of being prestored in the memory of the master device. This can be realized by reading the internal registers of the slave devices. [0097] Fourth, as shown in FIG. 22, the same device can be connected in two or more daisy chains. For example, the figure shows a case in which the slave device is an IN/OUT device, such as a codec. In this case, it is possible to use only one device ID assignment circuit 70, while it is necessary to set up two groups of time-slot assignment circuits 72. This is because, since the device ID is used for transmitting/receiving of the command field, it can be distinguished from the master side, and thus only one assignment circuit is necessary. However, since the audio channel fields are independent of each other on the receiving side (IN side) and the transmitting side (OUT side), two daisy chains are required. Fifth, as described above, since the number of slots assigned to each slave device is variable, variable transmission band that is different for each slave device can be realized. [0098] Sixth, a serial bus is used in the embodiment. However, it is also possible to use parallel buses. Seventh, the embodiment discloses an example of setting the time-slot allocating sequence of the bus as the “prescribed sequence.” The present invention, however, can be applied to other source allocation sequences. Eighth, the system is an audio system. The present invention, however, can also be applied to other systems (such as LANs, ATMs, remote monitoring systems, automatic measuring apparatuses, etc.). Ninth, the slave devices are DACs, ADCs, etc. However, other integrated circuit chips or other types and scales of circuits, units, devices, machines (such as terminals, computers, cameras, microphones, temperature sensors, humidity sensors, pressure sensors, actuators, etc.) can also be used as slave devices. [0099] As explained above, according to the present invention, identifiers can be automatically assigned to integrated circuit chips or other devices. Also, since identifiers can be assigned freely to devices, different device identifiers can be assigned to the same type of chip. In this way, multiple chips of the same type can be used or supported in the same system. As a result, there is no need to burn the device identifiers or addresses for the chips in ROM during chip manufacturing or assign special device identifiers to specific device types. Also, it becomes unnecessary to assign the device identifiers to the devices from the outside. In this way, since the design of circuits or other systems is not limited by the intrinsic device identifiers of the chips, the same type of chip can be exchanged between different manufacturers. [0100] Compared with the redundant intrinsic device identifiers used in the conventional method, the device identifiers of the present invention assigned to circuits or other systems are simple numbers. Consequently, the device identifiers can be used directly to form the optimum addresses or can also be used as the sequential numbers of an allocation sequence of a sharable resource in the system. [0101] If the sequential numbers are used for a sharable resource, the resource can be used efficiently. Also, variable time-division multiplex communication can be realized if the sharable resource is the time slot for use of the bus. In addition, when the number of the allocated time slots is variable, in spite of the coexistence of the devices that do not use the sharable resource of the bus, the devices that use the sharable resource, and the devices that use the sharable resource at a high frequency (IN device (DAC), OUT device (ADC), IN/OUT device (CODEC)), it is still possible to optimize the communication traffic of these devices (with little redundance). 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examinerClassifications U.S. Classification370/390, 370/404International ClassificationG06F13/368, G06F13/14, G06F13/37, G06F13/372Cooperative ClassificationG06F13/37European ClassificationG06F13/37Legal EventsDateCodeEventDescriptionMar 17, 2003ASAssignmentOwner name: TEXAS INSTRUMENTS INCORPORATED, TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SATOH, MASAHITO;KONDOH, HITOSHI;NAKAO, SHIGETOSHI;REEL/FRAME:013866/0770Effective date: 20030224RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services