Source: https://encrypted.google.com/patents/US9536110
Timestamp: 2018-04-23 02:07:23
Document Index: 641422055

Matched Legal Cases: ['Application No. 2004', 'Application No. 12165501', 'Application No. 12165519', 'Application No. 12165501', 'Application No. 12165519', 'Application No. 12165494', 'Application No. 12165501', 'Application No. 12165515', 'Application No. 2011', 'application No. 200710140450', 'Application No. 2004']

Patent US9536110 - Secure processor and a program for a secure processor - Google Patents
The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform...https://www.google.com/patents/US9536110?utm_source=gb-gplus-sharePatent US9536110 - Secure processor and a program for a secure processor
Publication number US9536110 B2
Application number US 14/091,488
Filing date Nov 27, 2013
Also published as CN1722046A, CN100361039C, CN101174290A, CN101174290B, CN101178758A, CN101178758B, EP1632835A2, EP1632835A3, EP1632835B1, EP2482222A2, EP2482222A3, EP2482222B1, EP2490146A2, EP2490146A3, EP2490146B1, EP2490147A2, EP2490147A3, EP2490147B1, EP2490148A2, EP2490148A3, EP2490148B1, US7865733, US8886959, US9141829, US9652635, US9672384, US20060015748, US20110167278, US20140082371, US20140089676, US20140089680, US20140089681, US20170046538, US20170046539
Publication number 091488, 14091488, US 9536110 B2, US 9536110B2, US-B2-9536110, US9536110 B2, US9536110B2
Original Assignee Socionext Inc.
Patent Citations (75), Non-Patent Citations (38), Classifications (23), Legal Events (1)
US 9536110 B2
1. A secure processor, comprising
an instruction execution circuit configured to execute an execution code of a process in a memory;
a secure process identifier generation circuit configured to generate a secure process identifier when an instruction to generate the process is issued;
a process information retention circuit configured to retain the secure process identifier and an authentication key for authentication of the execution code while the process is still present as information related to the process;
a translation look aside buffer including a page table entry of a page storing the execution code, the secure process identifier read from the process information retention circuit being set up in the page table entry when paging-in the execution code into the memory;
an authentication circuit configured to set a secure page flag in the page table entry when the execution code corresponding to the process is successfully authenticated using the authentication key, after the execution code corresponding to the process is stored in an unused page in the memory and the secure process identifier corresponding to an address of the unused page is stored in the page table entry; and
a memory access control circuit configured to compare the secure process identifier stored in the page table entry, in which the corresponding secure page flag is set, with the secure process identifier which is retained in the process information retention circuit, and to permit the instruction execution circuit to access the page in the memory where the execution code is stored and execute the execution code when the secure process identifier retained by the process information retention circuit matches the secure process identifier stored in the page table entry.
2. The secure processor according to claim 1, further comprising a secure process identifier elimination circuit configured to eliminate the secure process identifier which is generated and retained in the process information retention circuit when the process disappears.
3. The secure processor according to claim 1, wherein the secure processor pages-in the execution code in a format in which authentication information is added.
4. The secure processor according to claim 3, wherein the authentication information added to the execution code is information at a page unit in the memory.
5. The secure processor according to claim 1, further comprising a direct memory access circuit configured to perform a calculation which is necessary for the authentication of the execution code in parallel with storing of the execution code in the memory, to retain the results of the calculation, and to give the results to the authentication circuit.
6. The secure processor according to claim 1, further comprising:
an encryption processing circuit configured to perform encryption/decryption of information which includes a secure page flag and a secure process identifier stored in the page table entry and an address of a memory page storing an execution code, using the processor-specific key before evacuating the information to the outside or retrieving back the information from the outside.
7. The secure processor according to claim 1, further comprising:
a falsification detection circuit configured to generate a falsification detection information for information which includes a secure page flag and a secure process identifier stored in the page table entry and an address of a memory page storing an execution code, using the processor-specific key when saving the information to the outside, or detecting falsification for the information using the processor-specific key when retrieving the information back from the outside.
8. The secure processor according to claim 1, further comprising cores having respective instruction execution circuit and a cache: a secure core configured to execute only the execution code which is authenticated, and a normal core configured to execute regular execution code which is not authenticated.
9. The secure processor according to claim 8, wherein the normal core also executes the authenticated code in addition to the regular non-authenticated code.
10. The secure processor according to claim 1, further comprising a mode specifying circuit configured to select either a secure mode in which the secure processor having the instruction execution circuit executes only the authenticated execution code or a normal mode in which the secure processor executes only the non authenticated regular execution code, and the secure processor executes either in the secure mode or in the normal mode in response to the selection by the mode specifying circuit.
11. The secure processor according to claim 1, further comprising:
an encryption processing circuit configured to perform encryption/decryption of the information which contains the secure process identifier and is retained in the process information retention circuit, using the processor-specific key when evacuating the information to the outside or when retrieving the information back from the outside.
12. The secure processor according to claim 1, further comprising:
a falsification detection circuit configured to generate falsification detection information for the information which contains the secure process identifier and is retained in the process information retention circuit using the processor-specific key when evacuating the information to the outside, to add the falsification detection information to the information, and to detect falsification of the information using the processor-specific key when retrieving the information back from the outside.
13. A non-transitory computer readable storage medium used by a computer when paging-in an execution code into a memory, storing a program for causing the computer to execute the following operations:
generating a secure process identifier and retaining the secure process identifier by a process information retention circuit when an instruction to generate a process corresponding to the execution code is issued, prior to the execution of the process corresponding to the execution code;
requesting a direct memory access mechanism in the computer to transfer a page storing the execution code in an unused page in a memory;
setting up data regarding the page in a page table entry in a translation look aside buffer of the computer and storing the secure process identifier corresponding to an address of the unused page in the page table entry, after the page is transferred successfully;
requesting hardware to perform authentication of the page and to set a secure page flag in the page table entry when the execution code corresponding to the process is successfully authenticated by using an authentication key after the execution code is stored in the unused page in the memory and the secure process identifier corresponding to an address of the unused page is stored in the page table entry; and
comparing the secure process identifier retained by the process information retention circuit with the secure process identifier stored in the page table entry, in which the corresponding secure page flag is set, before an instruction execution circuit of the computer executes the execution code, and permitting the instruction execution circuit to execute the execution code when the secure process identifier retained by the process information retention circuit matches the secure process identifier stored in the page entry table.
14. A non-transitory computer readable storage medium used by a computer when a page including an execution code is authenticated, storing a program for causing the computer to execute the following operations:
performing a hash calculation for the page read into a main memory from a secondary memory storing the page and a first electronic signature, the first electronic signature corresponding to the page;
decrypting a second electronic signature stored in a storage circuit of a processor of the computer, the second electronic signature corresponding to the first electronic signature, by using an authentication key generated with a specific key retained inside the processor;
comparing the decryption result of the second electronic signature with the result of the hash calculation; and
setting a secure page flag, indicating that authentication of the page is successful, in a page table entry within a translation look aside buffer in the computer when the decryption result of the second electronic signature matches the result of the hash calculation.
This application is a divisional of U.S. application Ser. No. 12/926,476, filed Nov. 19, 2010, which is a divisional of U.S. application Ser. No. 11/089,352, filed Mar. 25, 2005, which is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-194951, filed Jun. 30, 2004, the entire contents of all of which are incorporated herein by reference.
When a processing starts in FIG. 63, the following procedures are taken. Using the program operated on the core 154, generally by the transfer management unit 157 which received instructions such as the transfer source address from the OS. The data reader 158 is instructed to read the next 64 byte data from the I/O device 102, and the 64 byte data are read by the data reader 158 at Step S111. The hash operator 159 is instructed to perform hash operation by the transfer management unit 157 at Step S112 and the hash operation is performed by the hash operator 159 at Step S113. The interim results are retained and, a data writer 160 is instructed to write 64 byte data to the physical memory 101 is instructed by the transfer management unit 157 at Step S114 and the 64 byte data are written in the physical memory 101 by the data writer 160 at Step S115. Whether or not the data transfer of one page is completed is determined at Step S116. If it is not completed, the processes from Step S110 are repeated, whereas if it is completed, a pair of hash values and the physical page top address as a transfer destination address is given by the transfer management unit 157 to a retention unit 161 to end the processing.
A computer system shown in FIG. 75 comprises a central processing unit (CPU) 200, a read only memory (ROM) 201, a random access memory (RAM) 202, a communication interface 203, a memory device 204, I/O device 205, a mobile storage medium reading device 206, and a bus 207 connecting all of the components.
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International Classification G06F21/70, G06F21/71, G06F21/52, G06F11/30, G06F21/57, G06F12/14, G06F21/64, G06F21/55, G06F21/72
Cooperative Classification G06F21/70, G06F21/74, G06F12/1027, G06F21/53, G06F13/24, G06F2212/1052, G06F2212/682, G06F12/1408, G06F21/71, G06F21/554, G06F21/64, G06F21/575, G06F21/52, G06F21/72
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