Source: http://www.google.com/patents/US6934214?dq=5,646,839
Timestamp: 2016-12-06 06:50:53
Document Index: 481224563

Matched Legal Cases: ['art 1', 'art 2', 'art 3', 'art 1', 'art 2', 'art 3']

Patent US6934214 - Semiconductor memory device having a hierarchical I/O structure - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsMemory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality...http://www.google.com/patents/US6934214?utm_source=gb-gplus-sharePatent US6934214 - Semiconductor memory device having a hierarchical I/O structureAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6934214 B2Publication typeGrantApplication numberUS 10/875,209Publication dateAug 23, 2005Filing dateJun 25, 2004Priority dateJun 29, 2000Fee statusPaidAlso published asUS6665203, US6765844, US20020001215, US20040047229, US20040228176Publication number10875209, 875209, US 6934214 B2, US 6934214B2, US-B2-6934214, US6934214 B2, US6934214B2InventorsHiroki Fujisawa, Shuichi Kubouchi, Koichiro NinomiyaOriginal AssigneeHitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (11), Referenced by (11), Classifications (27), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor memory device having a hierarchical I/O structure
US 6934214 B2Abstract
a memory bank area including a plurality of memory array areas arranged in a first direction, a plurality of sense amplifier areas arranged alternately relative to the plurality of memory array areas, and a plurality of first local input/output lines provided corresponding to the plurality of first sense amplifier areas and extending in a second direction intersecting the first direction; a plurality of first sub-amplifiers arranged along the memory bank area in the first direction, each of the plurality of first sub-amplifiers being connected to a corresponding one of the plurality of the first local input/output lines; and a first main input/output line including a first line extending in the first direction and a second line extending in the second direction and directly connected to the first line, wherein each of the plurality of memory array areas has a plurality of dynamic memory cells provided at intersections between a plurality of word lines and a plurality of data lines, wherein the first line is connected to the plurality of first sub-amplifiers, and wherein the second line passes through at least one of the plurality of memory array areas. 2. A semiconductor memory device according to claim 1, further comprising:
a main amplifier coupled with the second line, wherein the memory bank area is arranged between the main amplifier and the plurality of first sub-amplifiers. 3. A semiconductor memory device according to claim 1,
wherein each of the plurality of first sub-amplifiers has a first switch circuit, and wherein the first switch circuit selects to transfer an output of the first sub-amplifier to the first line. 4. A semiconductor memory device according to claim 1,
wherein each of the first local input/output lines comprises a pair of lines for transferring complementary signals, wherein each of the plurality of first sub-amplifiers has differential type first and second MOSFETs, and wherein a gate of the first MOSFET is connected to one of the first local input/output line pair and a gate of the second MOSFET is connected to the other of the first local input/output line pair. 5. A semiconductor device according to claim 1,
wherein the plurality of memory array areas are arranged in the first direction and the second direction so as to form a matrix, and wherein the memory bank area further includes a plurality of the word driver areas arranged alternately relative to the plurality of memory array areas in the second direction. 6. A semiconductor device according to claim 5, further comprising:
a plurality of second sub-amplifiers arranged along the memory bank area in the first direction, wherein the memory bank area further includes a plurality of second local input/output lines provided corresponding to a plurality of second sense amplifier areas which are arranged at a different row from the plurality of first sense amplifier areas and extending in the second direction, wherein each of the plurality of second sub-amplifiers is connected to a corresponding one of the plurality of the second local input/output lines, and wherein the memory bank area is arranged between the plurality of first sub-amplifiers and the plurality of second sub-amplifiers.
This application is a Continuation application of U.S. patent application Ser. No. 10/658,396 filed Sep. 10, 2003 now U.S. Pat. No. 6,765,844 issued on Dec. 16, 2003, which is a Divisional application of U.S. patent application Ser. No. 09/866,623 now U.S. Pat. No. 6,665,203, filed May 30, 2001, the entire disclosure of which is hereby incorporated by reference.
As a result of investigations that were carried out subsequent to the completion of the present invention, Unexamined Patent Publication No. Hei 2(1990)-308489 (hereinafter called “prior art 1”), Unexamined Patent Publication No. Hei 9(1997)-205182 (corresponding to U.S. Pat. No. 5,793,664 and hereinafter called “prior art 2”), and Unexamined Patent Publication No. Hei 10(1998)-178158 (corresponding to U.S. Pat. No. 5,949,697 and hereinafter called “Prior art 3”), which are considered to be related to the technical subject matter of the present invention, were discovered. The prior art 1 discloses an arrangement wherein intermediate amplifiers (sub amplifiers) are provided outside each of a plurality of memory cell arrays. The prior art 2 discloses an arrangement wherein N channel type MOSFETs and P channel type MOSFETs of a sense amplifier control circuit are distributively disposed at a cross portion where a sense amplifier row and a sub-word driver column intersect. The prior art 3 discloses an arrangement wherein switch means for connecting GIO (Global Input/Output lines) and LIO (local Input/Output lines) brought into a hierarchical structure are distributively disposed in a conjunction area where a sense amplifier row (sense amplifiers) and a sub-word driver column intersect, and pairs of P channel type driver MOSFETs and N channel type driver MOSFETs of the sense amplifiers are disposed in the same conjunction area. However, none of these publications discloses or gives any consideration to a hierarchical IO structure according to the present invention, which is to be described later in this application.
Another object of the present invention is to provide a semiconductor memory device having a hierarchical IO structure, which has achieved high integration and increased speed of operation.
In order to meet the requirements of such a DDR SDRAM, the memory cell array corresponding to one memory bank is divided into two memory blocks as viewed in the bit-line direction, and a memory cell corresponding to each word is selected from each of the memory blocks. Therefore, half or fifty-fifty of the bit lines in the memory array placed in the central portion of the memory cell array are used as edge mats of the divided two memory blocks.
Since 1024 bit lines are provided in one memory mat 15, except for the above-described edge memory mats, about 4K memory cells are connected in the word-line direction. Since 512 sub-word lines are provided, 512×32=16K memory cells are connected in the bit-line direction. Thus, one memory cell array (memory bank) has a storage capacity of 4K×16K=64 Mbits. The four memory arrays (memory banks) have a storage capacity of 4×64M=256 Mbits over the whole memory chip.
When the corresponding word line of the array 1 is selected, bit lines are divided fifty-fifty among 1024 bits lines intersecting the word line and connected to their corresponding sense amplifiers. Therefore, when the word line of the array 1 is selected, other sense amplifiers SA provided so as to interpose the array 1 therebetween are also provided with local input/output lines LIO at which the input/output of data corresponding to two bits is performed in the same manner as described above. This is similar even to local input/output lines LIO provided in other sense amplifiers SA corresponding to the array 2. Accordingly, the reading and writing of data corresponding to eight bits as a whole are allowed in the arrays 1 and 2.
In the above-described DRAM according to the present invention, the sub-amplifiers are collectively disposed in parallel with the sub-word drivers SWD outside the memory cell array without being laid out in each cross area. The local input/output lines LIO far from the sub amplifiers are connected to their corresponding sub amplifiers so as to pass over the array from above each sense amplifier SA. The main input/output lines MIO are connected to their corresponding main amplifiers MA so as to pass over the sub-amplifier areas. The main amplifier MA circuits are placed side by side in the direction orthogonal to each Y decoder area.
In the present embodiment, the sub amplifiers are placed outside the memory cell array in parallel with the sequence or array of lines SWD without being laid out in the cross area. In this configuration, the local input/output lines LIO in the array 1 are connected so as to pass over the sense amplifier. The local input/output lines in the array 2 pass over their corresponding sense amplifier and thereafter are connected to the corresponding sub amplifier so as to pass over the array. Thus, a hierarchical IO structure can be realized even if the sub amplifiers are not laid out in the cross area.
In the configuration wherein the read-system subamplifier circuit and the write-system CMOS buffer are used as in the embodiment shown in FIG. 5, a core portion of each sub amplifier makes use of the so called π-connected gate-reception differential N channel type MOSFETs Q20 and Q21. Consequently, a small signal on each local input/output signal line LIO can be transmitted to its corresponding main input/output line MIO at high speed (start timing free). The execution of the write operation by the CMOS buffer makes it possible to produce a CMOS amplitude relative to each local input/output line LIO at high speed. Incidentally, since it is near to impossible to lay out the sub amplifiers in each cross area in terms of the number of elements in the configuration wherein the read-system and write-system amplifier circuits are used as in the embodiment, the configuration is suitable for the layout of the sub amplifiers outside the corresponding memory cell array.
An overall schematic layout diagram of a further embodiment of a DRAM according to the present invention is shown in FIG. 7. In the present embodiment, sub-amplifier blocks are laid out in two rows, as viewed in central portions of memory cell arrays (memory banks), as viewed in a word-line direction and in the direction of the center of a chip. Although the invention is not restricted in particular, the number of memory arrays (memory mats) is set to 2×2 times that employed in the embodiment shown in FIG. 1. Circuit symbols attached to principal circuit blocks in one memory bank BANK0 are shown in the drawing in enlarged form.
Namely, one memory bank has a storage capacity corresponding to one memory chip shown in FIG. 1 and is divided into two memory blocks with Y decoders YDC as the center. They are respectively provided thirty-two by thirty-two in a bit-line direction as to normal arrays alone. The corresponding block is divided into two by the sub-amplifier block lying in the direction of the center of the chip. They have four memory arrays as viewed in the word-line direction. As a result, the number of the memory arrays is provided as eight in one memory bank, as viewed in the direction in which word lines extend. In regard to the normal arrays alone, the number thereof is provided as sixty-four, as viewed in the bit-line direction. In the case of the memory array in which 1024×512 memory cells are laid out, as described above, the memory array has a storage capacity like about 1G (Giga) bits as a whole.
When the storage capacity is 256 Mbits in a manner similar to the embodiment shown in FIG. 1, one memory array takes a 512×256 bit configuration. The number of memory cells connected to one bit line is reduced like 256, and the number of memory cells connected to one sub-word line is reduced like 512. Therefore, an increase in the amount of a signal read from each memory cell and the speeding up of the operation of selecting each word line make it possible to implement a high-speed DRAM.
A cross-sectional diagram illustrating one embodiment of a DRAM according to the present invention is shown in FIG. 8. An array is provided with MOSFETs for address selection and capacitors for storage, which constitute each memory cell. Word lines are formed integrally with gate electrodes comprised of MOSFETS. A bit line is comprised of a metal wiring (Metal 1: hereinafter called simply “M1”) corresponding to a first layer. Each of the storage electrodes of the memory cell is connected to one source or drain diffused layer (activation region) of a MOSFET by a contact for connecting each storage electrode and one source or drain diffused layer thereof, whereas, each bit line is connected to one source or drain diffused layer (activation region) of one MOSFET by a contact for connecting the bit line and one source or drain diffused layer thereof. The metal M1 and each bit line lies in the same wiring layer, and a polysilicon layer FG corresponding to a first layer and each sub-word line WL are also formed in the same wiring layer.
In the present embodiment, some of the power lines are assigned to main input/output lines MIO and local input/output lines LIO, respectively. Namely, local input-/output line LIO wirings for guiding main input/output lines MIO which cross the memory cell array in the word-line direction, and local input/output lines LIO formed in the sense amplifier areas of the arrays 2 and 3 to their corresponding sub amplifiers are passed between the main word lines (metal wirings M2). In the present embodiment, main input/output lines MIO and sub-word driver select signal lines FX are caused to normally pass through the metal wiring M3 on each sub-word driver. Further, the metal wirings M2 are used to allow the main word lines MWL and power lines to pass therethrough.
This is similar even to the sub-word drivers SWD. 512 sub-word lines WL provided in the memory mat MAT0 are divided 256 by 256, which in turn are connected to their corresponding 256 sub-word drivers SWD of the sub-word driver arrays SWDA placed on both sides of the memory mat MAT0. In the present embodiment, the sub-word drivers SWD provided two by two are dispersively placed with two sub-word lines WL as each pair. Namely, two sub-word drivers are placed on the one-end side (on the upper side in the drawing) of the memory mat MATO with the sub-word lines corresponding to two memory cells which share the use of a portion connected to each bit line, as one pair; whereas, two sub-word drivers are placed on the other end side (on the lower side in the drawing) of the memory mat MAT0 with the similar two sub-word lines adjacent thereto as one pair.
In the present embodiment, the above-described plate electrodes PLO and PL1 respectively formed in the memory mats MATO and MAT1 provided on both sides of each sense amplifier array SAA are connected to one another by wirings PLSA using a plate layer itself. Further, the wirings PLSA are provided in plural form so as to penetrate the sense amplifier arrays SAA, thereby greatly reducing the resistance between the two plate electrodes PLO and PL1. Thus, phase-reversal noise developed in the plate electrodes PLO and PL1, when a small signal read from each memory cell MC selected between complementary bit lines BL for the memory mats MATO and MAT1 is amplified by the corresponding sense amplifier SA, can be canceled out at high speed, thereby making it possible to greatly reduce the noise produced in the plate electrodes PLO and PL1.
In the case of a storage capacity of 256 Mbits, for example, an address terminal for inputting the address signal A14 as a column address signal is provided when a memory access is carried out in 2-bit units. In an ×4-bit configuration, the address signals up to the address signal A11 are rendered valid. In an ×8-bit configuration, the address signals up to the address signal A10 are made valid, and the address signals up to the address signal A9 are rendered valid in an ×16-bit configuration. In the case of a storage capacity of 64 Mbits, the address signals up to the address signal A10 are rendered valid in an ×4-bit configuration, and the address signals up to the address signal A9 are made valid in an ×8-bit configuration. Further, the address signals up to the address signal A8 are set valid in an ×16-bit configuration, as shown in the drawing.
A mode register (Mode Register) 213 holds various operation mode information therein. Of the row decoders (Row Decoders) 201 A through 201D, only one corresponding to the bank specified by a bank select (Bank Select) circuit 212 is activated to allow the operation of selecting each word line. Although the invention is not restricted in particular, a control circuit (Control Logic) 209 is supplied with external control signals such as clock signals CLK, /CLK (symbol/indicate each of bar signals which means that signals marked therewith are row enable signals), a clock enable signal CKE, a chip select signal /CS, a column address strobe signal /CAS, a row address strobe signal /RAS and a write enable signal /WE, etc., /DM and DQS, and address signals inputted through the mode register 213. The control circuit 209 forms internal timing signals for controlling an operation mode for the DDR SDRAM and the operations of the circuit blocks, based on changes in the levels of these signals, timing, etc. and is provided with input buffers respectively corresponding to the signals.
The row address signals are defined based on the levels of AO through A11 in a row address strobe/bank active command cycle to be described later synchronized with the rising edge of the clock signal CLK (internal clock signal).
When the ×16-bit configuration is set in 256 Mbits as described above, the column address signals are defined according to the levels of AO through A9 in a read or write command (corresponding to a column address/read command or a column address/write command to be described later) cycle synchronized with the rising edge of the clock signal CLK (internal clock). Each of the column addresses defined in this way is set as a start address for a burst access.
This is a command required to start a burst read operation. Further, this is also a command for providing instructions for a column address strobe. The present command is specified according to /CS and /CAS=low level and /RAS and /WE=high level. Column addresses supplied to AO through A9 (in the case of the ×16-bit configuration) at this time are captured as column address signals, respectively. Thus, the captured column address signals are supplied to the column address counter 207 as burst start addresses.
The corresponding command is specified according to /CS, /CAS and /WE=low level and /RAS=high level. Addresses supplied to A0 through A9 at this time are captured as column address signals. Thus, the captured column address signals are supplied to the column address counter 207 as burst start addresses upon the burst write. The procedure of the burst write operation specified thereby is also performed in a manner similar to the burst read operation. However, no CAS latency is provided for the write operation and the capturing of the write data is started from after one clock of the column address/write command cycle.
Thus, unless data D0 through D15 collide with one another at a data input/output terminal comprising 16 bits, for example, the precharge command and the row address strobe/bank active command for a memory bank different from a memory bank to be processed or handled by an process-unfinished command are issued during the execution of the corresponding command to thereby allow the commencement of an internal operation in advance. Since the DDR SDRAM according to the present embodiment performs the memory access in 16-bit units, has the addresses corresponding to about 4M, based on the addresses of A0 through A11, and comprises the four memory banks as described above, it has a storage capacity of about 256 Mbits (4M×4 banks×16 bits) as a whole.
After three CLKs following the input of the row address, a column address and a bank select signal are inputted simultaneously with CAS=0 and respectively held in the column address buffer 206 and the bank select circuit 212. If the specified bank is active, then the held column address is outputted from the column address counter 207 and the corresponding column decoder 203 selects a column. The selected data is outputted from the sense amplifier 202. The data outputted at this time corresponds to two pairs or sets (8 bits in an ×4-bit configuration and 32 bits in an ×16-bit configuration).
The data outputted from the sense amplifier 202 is outputted from the data output circuit 211 to the outside of the chip through a data bus DataBus. Timing provided to output it is synchronized with both the rising and falling edges of QCLK outputted from the DLL 214. At this time, the two pairs of data are parallel-to-serial converted into data of one pair×two as described above. Simultaneously with the output of the data, the DQS buffer 215 outputs a data strobe signal DQS therefrom. When the burst length stored in the mode register 213 is 4 or more, the column address counter 207 automatically increments addresses to read out the next column data.
(11) In addition to the above, a still further effect is obtained in that each memory cell array area is divided into a first memory block and a second memory block separated into two in the first direction, the first select signal generating circuit commonly supplies a select signal to the first memory block and the second memory block, the second select signal generating circuit supplies a select signal to each of the first memory block and the second memory block, and the specific memory array area is set as one located in the direction of the center of the chip, of the memory array areas provided for the first and second memory blocks as viewed in the first direction, whereby each signal transfer channel, which leads to the input/output circuit, can be shortened.
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