Source: http://www.google.com/patents/US6974737?dq=patent:5992892
Timestamp: 2016-07-25 23:09:18
Document Index: 232019363

Matched Legal Cases: ['application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'art 1']

Patent US6974737 - Schottky barrier CMOS fabrication method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions...http://www.google.com/patents/US6974737?utm_source=gb-gplus-sharePatent US6974737 - Schottky barrier CMOS fabrication methodAdvanced Patent SearchPublication numberUS6974737 B2Publication typeGrantApplication numberUS 10/440,498Publication dateDec 13, 2005Filing dateMay 16, 2003Priority dateMay 16, 2002Fee statusPaidAlso published asUS8154025, US20040041226, US20050287730, US20100006949Publication number10440498, 440498, US 6974737 B2, US 6974737B2, US-B2-6974737, US6974737 B2, US6974737B2InventorsJohn P. Snyder, John M. LarsonOriginal AssigneeSpinnaker Semiconductor, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (51), Non-Patent Citations (56), Referenced by (40), Classifications (12), Legal Events (9) External Links: USPTO, USPTO Assignment, EspacenetSchottky barrier CMOS fabrication method
US 6974737 B2Abstract
This application claims priority to U.S. provisional patent application No. 60/445,711, filed Feb. 7, 2003. This application claims priority to U.S. provisional patent application No. 60/381,162, filed May 16, 2002. This application claims priority to U.S. provisional patent application No. 60/381,238, filed May 16, 2002. This application claims priority to U.S. provisional patent application No. 60/388,659, filed May 16, 2002. This application claims priority to U.S. provisional patent application No. 60/381,240 filed May 16, 2002. This application claims priority to U.S. provisional patent application No. 60/381,237, filed May 16, 2002. This application claims priority to U.S. provisional patent application No. 60/381,321, filed May 16, 2002. This application claims priority to U.S. provisional patent application No. 60/381,239, filed May 16, 2002. This application claims priority to U.S. provisional patent application No. 60/381,236, filed May 16, 2002. This application claims priority to U.S. provisional patent application No. 60/381,320, filed May 16, 2002. Each of the above provisional patent applications is incorporated by reference herein in its entirety.
For digital applications, MOS transistors behave like switches. When ‘on’, they drive relatively large amounts of current and when turned ‘off’ they are characterized by a certain amount of leakage current. A common CMOS inverter circuit, comprising an NMOS and PMOS device connected in series, dissipates appreciable power only during switching transients. Otherwise, the quiescent power dissipation, or the power dissipated by the CMOS circuit when idle, is a strong function of MOSFET leakage current, and significantly affects the overall circuit power dissipation for most applications.
The present invention is particularly suitable for use with MOSFET semiconductor devices, but the use of the present teachings is not limited to this particular application. Other semiconductor devices, may be applied to the present invention teachings. Thus, while this specification speaks in terms of ‘MOSFET’ devices, this term should be interpreted broadly to include any device for regulating the flow of electrical current having a conducting channel that has two or more points of electrical contact.
The present invention is particularly suitable for use and fabrication of CMOS integrated circuits, but the use of the present teachings is not limited to this particular application. Other circuits comprising complimentary or non-complimentary NMOS and/or PMOS transistors may be applied to the present invention teachings. Thus, while this specification speaks in terms of ‘CMOS’ circuits, this term should be interpreted broadly to include any circuit that comprises connected N- and/or P-MOS transistors.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4053924Aug 2, 1976Oct 11, 1977California Linear Circuits, Inc.Ion-implanted semiconductor abrupt junctionUS4300152Apr 7, 1980Nov 10, 1981Bell Telephone Laboratories, IncorporatedComplementary field-effect transistor integrated circuit deviceUS4485550Jul 23, 1982Dec 4, 1984At&T Bell LaboratoriesFabrication of schottky-barrier MOS FETsUS4513309Nov 3, 1982Apr 23, 1985Westinghouse Electric Corp.Prevention of latch-up in CMOS integrated circuits using Schottky diodesUS4554569Mar 29, 1982Nov 19, 1985Tove Per ArneIntegrated electron circuits having Schottky field effect transistors of P- and N-typeUS4780429May 13, 1986Oct 25, 1988Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux EfcisMethod of fabrication of MOS transistors having electrodes of metallic silicideUS4942441Mar 27, 1987Jul 17, 1990Hitachi, Ltd.Thin film semiconductor device and method of manufacturing the sameUS5040034Jan 18, 1990Aug 13, 1991Nissan Motor Co., Ltd.Semiconductor deviceUS5079182Apr 2, 1990Jan 7, 1992National Semiconductor CorporationBicmos device having self-aligned well tap and method of fabricationUS5250834Sep 19, 1991Oct 5, 1993International Business Machines CorporationSilicide interconnection with schottky barrier diode isolationUS5323053Jul 9, 1993Jun 21, 1994At&T Bell LaboratoriesSemiconductor devices using epitaxial silicides on (111) surfaces etched in (100) silicon substratesUS5338698Dec 18, 1992Aug 16, 1994International Business Machines CorporationMethod of fabricating an ultra-short channel field effect transistorUS5361225Mar 19, 1993Nov 1, 1994Rohm Co., Ltd.Nonvolatile memory device utilizing field effect transistor having ferroelectric gate filmUS5444302Dec 22, 1993Aug 22, 1995Hitachi, Ltd.Semiconductor device including multi-layer conductive thin film of polycrystalline materialUS5663584Dec 29, 1994Sep 2, 1997Welch; James D.Schottky barrier MOSFET systems and fabrication thereofUS5665993Mar 26, 1996Sep 9, 1997Texas Instruments IncorporatedIntegrated circuit including a FET device and Schottky diodeUS5760449Dec 26, 1995Jun 2, 1998Welch; James D.Regenerative switching CMOS systemUS5767557May 24, 1996Jun 16, 1998Lucent Technologies Inc.PMOSFETS having indium or gallium doped buried channels and n+polysilicon gates and CMOS devices fabricated therefromUS5801398Oct 17, 1995Sep 1, 1998Frontec CorporationField effect transistorUS5883010Aug 7, 1997Mar 16, 1999National Semiconductor CorporationMethod for protecting nonsilicided surfaces from silicide formation using spacer oxide maskUS5891769Feb 27, 1998Apr 6, 1999Motorola, Inc.Method for forming a semiconductor device having a heteroepitaxial layerUS6037605Aug 19, 1997Mar 14, 2000Kabushiki Kaisha ToshibaSemiconductor device and method of manufacturing the sameUS6096590Jun 30, 1998Aug 1, 2000International Business Machines CorporationScalable MOS field effect transistorUS6130750Aug 28, 1997Oct 10, 2000International Business Machines CorporationOptical metrology tool and method of using sameUS6153484Jun 19, 1996Nov 28, 2000Imec VzwEtching process of CoSi2 layersUS6160282Apr 21, 1998Dec 12, 2000Foveon, Inc.CMOS image sensor employing silicide exclusion mask to reduce leakage and improve performanceUS6255227Jan 6, 2000Jul 3, 2001Interuniversitair Microelektronica CentrumEtching process of CoSi2 layersUS6268636Feb 8, 1999Jul 31, 2001James D. WelchOperation and biasing for single device equivalent to CMOSUS6303479Dec 16, 1999Oct 16, 2001Spinnaker Semiconductor, Inc.Method of manufacturing a short-channel FET with Schottky-barrier source and drain contactsUS6323528Jul 29, 1998Nov 27, 2001Semiconductor Energy Laboratory Co,. Ltd.Semiconductor deviceUS6353251Nov 24, 1998Mar 5, 2002Mitsuteru KimuraMOS gate Schottky tunnel transistor and an integrated circuit using the sameUS6413829Jun 1, 2001Jul 2, 2002Advanced Micro Devices, Inc.Field effect transistor in SOI technology with schottky-contact extensionsUS6420742Jun 16, 2000Jul 16, 2002Micron Technology, Inc.Ferroelectric memory transistor with high-k gate insulator and method of fabricationUS6452232Dec 1, 1999Sep 17, 2002Sharp Kabushiki KaishaSemiconductor device having SOI structure and manufacturing method thereofUS6486080Nov 30, 2000Nov 26, 2002Chartered Semiconductor Manufacturing Ltd.Method to form zirconium oxide and hafnium oxide for high dielectric constant materialsUS6495882Feb 6, 2001Dec 17, 2002Spinnaker Semiconductor, Inc.Short-channel schottky-barrier MOSFET deviceUS6509609Jun 18, 2001Jan 21, 2003Motorola, Inc.Grooved channel schottky MOSFETUS6548875 *Mar 6, 2001Apr 15, 2003Kabushiki Kaisha ToshibaSub-tenth micron misfet with source and drain layers formed over source and drains, sloping away from the gateUS6555879Jan 11, 2002Apr 29, 2003Advanced Micro Devices, Inc.SOI device with metal source/drain and method of fabricationUS6661061Dec 8, 1998Dec 9, 2003Advanced Micro Devices, Inc.Integrated circuit with differing gate oxide thicknessUS6744103Sep 6, 2002Jun 1, 2004Spinnaker Semiconductor, Inc.Short-channel schottky-barrier MOSFET device and manufacturing methodUS6784035Jan 15, 2003Aug 31, 2004Spinnaker Semiconductor, Inc.Field effect transistor having source and/or drain forming Schottky or Schottky-like contact with strained semiconductor substrateUS20010024847Feb 6, 2001Sep 27, 2001Snyder John P.MOSFET device and manufacturing methodUS20020030231May 30, 2001Mar 14, 2002Seiko Epson CorporationSemiconductor device having electrostatic protection circuit and method of fabricating the sameUS20020125471Dec 4, 2001Sep 12, 2002Fitzgerald Eugene A.CMOS inverter circuits utilizing strained silicon surface channel MOSFETSUS20030057416Sep 20, 2002Mar 27, 2003Amberwave Systems CorporationSemiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating sameUSRE32613Jul 19, 1985Feb 23, 1988American Telephone And Telegraph Company, At&T Bell LaboratoriesMethod of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor deviceEP0603102A2Nov 19, 1993Jun 22, 1994International Business Machines CorporationLow-temperature MOSFET source drain structure with ultra-short channelJP2000124329A Title not availableJPH0697109A Title not availableWO2001045157A1Dec 15, 2000Jun 21, 2001Spinnaker Semiconductor, Inc.Mosfet device system and method* Cited by examinerNon-Patent CitationsReference1Calvet, L. E., Luebben, H., Reed, M.A., Wang, C., Snyder, J.P., and Tucker, J.R. Subthreshold and scaling of PtSi Schottky barrier MOSFETs, 2000 Academic Press, Superlattices and Microstructures, vol. 28, No. 5/6; pp. 501-506.2Gang, D., Xiaoyan, L., Lei, S., Jiaping, Y., Ruqi, H., Houlet, P., and Fujitan, H. Monte Carol Simulation of 50nm n-Channel Schottky Barrier Tunneling Transistors. Chinese Journal of Electronics, vol. 11, No. 2, Apr. 2002; pp. 200-203.3Geppert, Linda. The 100-Million Transistor IC. IEEE Spectrum, Jul. 1999; pp. 23-24.4Hargrove, M., Crowder, S., Novak, E., Logan, R., Han, L.K., Ng, H., Ray, A., Sinitsky, D., Smeys, P., Guarin, F., Oberschmidt, J., Crabbe, E., Yee, D., Su, L. High Performance Sub-0.08um CMOS with Dual Gate Oxide and 9.7 ps Inverter Delay. IEDM Technical Digest, Dec. 1998; pp. 627-630.5Hattori, Reiji, Nakae, Akihiro, Shirafuji, Junji. A New Type of Tunnel-Effect Transistor Employing Internal Field Emission of Schottky Barrier Junction. Japan J. Appl. Phys., vol. 31, 1992; pp. L1467-L1469.6Hattori, Reiji, Shirafuji, Junji. Numerical Simulation of Tunnel Effect Transistors. Japan J. Appl. Phys., vol. 33, 1994; pp. 612-618.7Hitoshi Kisaki Tunnel Transistor Proceedings of the IEEE, Jul. 1973, pp. 1053-1054.8Huang et al. Two Dimensional Numerical Simulation of Schottky Barrier MOSFET with Channel Length to 10 nm. IEEE Transactions on Electron Devices, vol. 45, No. 4, Apr. 1988, pp. 842-848.9International Technology Roadmap for Semiconductors 1999, US Copyright 1999 by Semiconductor Industry Association, Front End Processes Section, p. 107.10Kedzierski, J., Xuan, P., Subramanian, V., Bokor, J., King, T-J., Hu, C., Anderson, E. A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain. Superlattices and Microstructures, vol. 28, No. 5/6, 2000, pp. 445-452.11Kimura, Mitsuteru, Matsudate, Tadashi. A New Type of Schottky Tunnel Transistor. IEEE Electron Device Letters, EDL-15, No. 10, Oct. 1994, pp. 412-414.12Kisaki, Hitoshi. Tunnel Transistor. Proceedings of the IEEE, Jul. 1973; pp. 1053-1054.13Koeneke, C.J., Lynch, W.T. Lightly Doped Schottky MOSFET. IEDM, 1982; pp. 466-469.14Koeneke, C.J., Sze, S.M., Levin, R.M., Kinsbron, E. Schottky MOSFET for VLSI. IEDM, 1981; pp. 367-370.15Lancaster, D. CMOS Cookbook, Second Edition. Howard W. Sams and Company, 1988, p. 2.16Laplante, Philip A. (Editer-in-Chief). Comprehensive Dictionary of Electrical Engineering. 1999, IEEE Press, p. 97.17Lepselter, M.P., Macrae, A.U., Macdonald, R.W. SE-IGFET, II: An Ion Implanted IGFET Using Schottky Barriers. Proceedings of the IEEE, May 1969; pp. 812-813.18Lepselter, M.P., Sze, S.M. SB-IGFET: An Insulated Gate Field Effect Transistor Using Schottky Barrier Contacts for Source and Drain. Proceedings of the IEEE, Aug. 1968; pp. 1400-1402.19Magnusson, U. et al. "Bulk Silicon Technology For Complementary MESFETs." Electronics Letters, vol. 25, No. 9, Apr. 27, 1989; pps. 565-566.20Misra, D., Simhadri, V.S. A Survey of the Potential of an IrSi Schottky Barrier MOSFET Based on Simulation Studies. Solid State Electronics, vol. 35, No. 6, 1992; pp. 829-833.21Mochizuki, T., Wise, K.D. An n-Channel MOSFET with Schottky Source and Drain. IEEE Electron Device Letters, EDL-5, No. 4, Apr. 1984; pp. 108-111.22Muller, Richard S. and Kamins, Theodore I. Device Electronics for Integrated Circuit. 1977, 1986, John Wiley & Sons, Second Edition, pp. 484, 505-511.23Neudeck, Gerold W. Volume II: The PN Junction Diode, Modular Series On Solid State Devices. Addison-Wesley, 1983; pp. 8-10.24Nishisaka, Mika, Asano, Tanemasa. Reduction of the Floating Body Effect in SOI MOSFETs by Using Schottky Source/Drain Contacts. Japan J. Appl. Phys., vol. 37, Mar. 1998; pp. 1295-1299.25Oh, C.S., Koh, Y.H., Kim, C.K. A New P-Channel MOSFET Structure with Schottky Clamped Source and Drain, IEDM, 1984; pp. 609-612.26On-line Encyclopedia Britannica, 2001, definition of "rare-earth element.", date not established; 2 pages.27Pierret, Modular Series on Solid State Devices, vol. 1 Semiconductor Fundamentals, 1983, Addison-Wesley, pp. 29-33.28Random House College Dictionary, 1980, Random House, Inc., Revised Ed., pp. 17 and 1066.29Rishton, S.A., Ismail, K., Chu, J.O., Chan, K. A MOS Transistor with Schottky Source/Drain Contacts and a Self-Aligned Low-Resistance T-gate, Microelectronics Engineering, vol. 35, 1997; pp. 361-363.30Rishton, S.A., Ismail, K., Chu, J.O., Chan, K.K., Lee, K.Y. New Complimentary metal-oxide semiconductor technology with self-aligned Schottky source/drain and low-resistance T gates. J. Vac. Sci. Technol. B, 15(6), Nov./Dec. 1997, pp. 2795-2798.31Saitoh et al. Analysis of Short-Channel Schottky Source/Drain MOSFET on Silicon-on-Insulator Substrate Demonstration of Sub-50-nm n-Type Devices with Metal Gate. Jpn. J. Appl. Phys., part 1, vol. 38, No. 11, Nov. 1999, pp. 6226-6231.32Saitoh, W., Yamagami, S., Itoh, A., Asada, M. 35nm Metal Gate SOI-p-MOSFETs with PtSi Schottky Source/Drain. 57<SUP>th </SUP>Annual Device Research Conference Digest, Jun. 1999; pp. 30-31.33Snyder, John P., Helms, C.R., Nishi, Yoshio. Experimental Investigaton of a PtSi Source and Drain Field Emission Transistor. Applied Physics Letters, vol. 67, No. 10, Sep. 4, 1995; pp. 1420-1422.34Snyder, John P., Holms, C.R., Nishi, Yoshio. Analysis of the Potential Distribution in the Channel Region of a Platinum Silicided Source/Drain Metal Oxide Semiconductor Field Effect Transistor. Applied Physics Letters, vol. 74, No. 22, May 31, 1999; pp. 3407-3409.35Sugino, M., Akers, L.A., Rebeschini, M.E. CMOS Latch-Up Elimination Using Schottky Barrier PMOS. IEDM, 1982; pp. 462-465.36Swirhun, Stanley E., et al. A VLSI Suitable Schottky Barrier CMOS Process. IEEE Transactions on Electron Devices, ED-32, No. 2, Feb. 1985; pp. 194-202.37Sze, S.M. Physics of Semiconductor Devices, John Wiley & Sons, Second Edition, 1981; pp. 293-294.38Sze, S.M. Physics of Semiconductor Devices. 1981, John Wiley & Sons, Second Edition, pp. 451-453.39Taur, Yuan, Wann, Clement H., Frank, David J, 25 nm CMOS Design Considerations. IEDM Technical Digest, Dec. 1998; pp. 789-792.40Taur, Yuan. The Incredible Shrinking Transistor, IEEE Spectrum, Jul. 1999; pp. 25-29.41Tove, P.A., Bohlin, K., Masszi, F., Norde, H., Nylander, J., Tiren, T., Magnusson, U. Complementary Si MESFET Concept Using Silicon-on-Sapphire Technology. IEEE Electron Device Letters, vol. 9, No. 1, Jan. 1988; pp. 47-49.42Tove, P.A., Bohlin, K.E., Norde, H., Magnusson, U., Tiren, J., Soderbarg, A., Rosling, M., Masszi, F., Nyander, J. Silicon IC Technology Using Complementory MESFETs. Solid State Devices, Elsevier Science Publishers (North Holland), 1988; pp. 607-609.43Tsui, B., Chen, M. A Novel Process for High-Performance Schottky Barrier PMOS. J. Electrochem Soc., vol. 136, No. 5, May 1989; pp. 1456-1459.44Tu, K.N. Thompson, R.D., Tsaur, B.Y. Low Schottky Barrier of Rare-Earth Silicide on n-Si. Applied Physics Letters, vol. 38, No. 8, Apr. 1981; pp. 626-628.45Tucker, J.R. Schottky Barrier MOSFETs for Silicon Nanoelectronics. Jan. 1997, IEEE Frontiers in Electronics, pp. 97-100.46Tucker, J.R., Wang, C., Carney, P.S. Silicon Field-Effect Transistor Based on Quantum Tunneling. Applied Physics Letters, vol. 65, No. 5, Aug. 1, 1994; pp. 618-620.47Tucker, J.R., Wang, C., Lyding, J.W., Shen, T.C., Abeln, G.C. Nanometer Scale MOSFETs and STM Patterning on Si. SSDM 1994, Aug. 1994; pp. 322-324.48Unewisse, M.H., Storey, J.W.V. Electrical and Infared Investigation of Erbium Silicide. J. Appl. Phys., vol. 72, No. 6, Sep. 1992; pp. 2367-2371.49Wang, C., Snyder, John P., Tucker, J.R. Sub-40nm PtSi Schottky Source-Drain Metal-Oxide-Semiconductor Field-Effect-Transistors. Applied Physics Letters, vol. 74, No. 8, Feb. 22, 1999; pp. 1174-1176.50Wang, C., Snyder, John P., Tucker, J.R. Sub-50nm PtSi Schottky Source/Drain p-MOSFETs. 56<SUP>th </SUP>Annual Device Research Conference Digest, Jun. 1998, pp. 72-73.51Web page "provided by Laurie Calvet", "Device Physics of the SBMOSFET", http://www.eng.yale.edu/reedlab/research/semicond.html, date not established; 7 pages.52Winstead, B. and Ravaioli, U. Simulation of Schottky Barrier MOSFET's with a Coupled Quantum Injection/Monte Carol Technique. IEEE Transactions on Electron Device, vol. 47, No. 6, Jun. 2000; pp. 1241-1246.53Wolf, Stanley. Silicon Processing For the VLSI Era, vol. 3: The Submicron MOSFET, Lattice Press, Sunset Beach, CA, pp. 523-528 (1995).54Wolf, Stanley. Silicon Processing for the VLSI Era, vol. 3: The Submicron MOSFET. Lattice Press, 1995; pp. 183-187.55Wolf, Stanley. Silicon Processing for the VLSI Era. vol. 3: The Submicron MOSFET, Lattice Press, Sunset Beach, CA, 1995; pp. 523-528.56Zhao, Q.T., Klinkhammer, F., Dolle, M., Kappius, L., Mantl, S. Nanometer Patterning of Epitaxial CoSi2/Si(100) for Ultrashort Channel Schottky Barrier Metal-Oxide-Semiconductor Field Effect Transistors. Applied Physics Letters, vol. 74, No. 3, Jan. 18, 1999; pp. 454-456.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7052945 *Feb 7, 2003May 30, 2006Spinnaker Semiconductor, Inc.Short-channel Schottky-barrier MOSFET device and manufacturing methodUS7291524Oct 4, 2004Nov 6, 2007Spinnaker Semiconductor, Inc.Schottky-barrier mosfet manufacturing method using isotropic etch processUS7510940 *Feb 16, 2007Mar 31, 2009Taiwan Semiconductor Manufacturing Company, Ltd.Method for fabricating dual-gate semiconductor deviceUS7566642 *Jul 22, 2005Jul 28, 2009Electronics And Telecommunications Research InstituteProcess of manufacturing an N-type Schottky barrier tunnel transistorUS7799644Jul 28, 2006Sep 21, 2010Freescale Semiconductor, Inc.Transistor with asymmetry for data storage circuitryUS7863121 *May 8, 2007Jan 4, 2011Electronics And Telecommunications Research InstituteMethod for fabricating Schottky barrier tunnel transistorUS7871871 *Feb 26, 2009Jan 18, 2011Renesas Electronics CorporationManufacturing method for semiconductor integrated circuit deviceUS8039284Dec 18, 2006Oct 18, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Dual metal silicides for lowering contact resistanceUS8058167Sep 28, 2009Nov 15, 2011Avolare 2, LlcDynamic Schottky barrier MOSFET device and method of manufactureUS8415748Apr 9, 2013International Business Machines CorporationUse of epitaxial Ni silicideUS8482076Sep 16, 2009Jul 9, 2013International Business Machines CorporationMethod and structure for differential silicide and recessed or raised source/drain to improve field effect transistorUS8482646 *Jan 20, 2010Jul 9, 2013Canon Kabushiki KaishaImage sensing device and cameraUS8513122Feb 5, 2013Aug 20, 2013International Business Machines CorporationMethod and structure for differential silicide and recessed or raised source/drain to improve field effect transistorUS8513765Jul 19, 2010Aug 20, 2013International Business Machines CorporationFormation method and structure for a well-controlled metallic source/drain semiconductor deviceUS8658530Sep 12, 2012Feb 25, 2014International Business Machines CorporationMethod of fabricating an epitaxial Ni silicide filmUS8670059Jan 20, 2010Mar 11, 2014Canon Kabushiki KaishaPhotoelectric conversion device having an n-type buried layer, and cameraUS8723285Jan 8, 2010May 13, 2014Canon Kabushiki KaishaPhotoelectric conversion device manufacturing method thereof, and cameraUS8809987Sep 8, 2010Aug 19, 2014The Hong Kong University Of Science And TechnologyNormally-off III-nitride metal-2DEG tunnel junction field-effect transistorsUS20030139002 *Feb 7, 2003Jul 24, 2003Snyder John P.Short-channel schottky-barrier MOSFET device and manufacturing methodUS20050104152 *Sep 17, 2004May 19, 2005Snyder John P.Schottky barrier integrated circuitUS20050118793 *Oct 4, 2004Jun 2, 2005Snyder John P.Schottky-barrier MOSFET manufacturing method using isotropic etch processUS20050287730 *Aug 30, 2005Dec 29, 2005Snyder John PSchottky barrier CMOS device and methodUS20060131664 *Jul 22, 2005Jun 22, 2006Kim Yark YN-type schottky barrier tunnel transistor and manufacturing method thereofUS20070001223 *Jul 1, 2005Jan 4, 2007Boyd Diane CUltrathin-body schottky contact MOSFETUS20070120204 *Jan 25, 2007May 31, 2007Kabushiki Kaisha ToshibaSemiconductor device and manufacturing method thereofUS20080026529 *Jul 28, 2006Jan 31, 2008White Ted RTransistor with asymmetry for data storage circuitryUS20080121868 *May 8, 2007May 29, 2008Electronics And Telecommunication Research InstituteSchottky barrier tunnel transistor and method for fabricating the sameUS20080145984 *Dec 18, 2006Jun 19, 2008Chung-Hu KeDual metal silicides for lowering contact resistanceUS20080197420 *Feb 16, 2007Aug 21, 2008Chen-Nan YehMethod for fabricating dual-gate semiconductor deviceUS20090140351 *Nov 30, 2007Jun 4, 2009Hong-Nien LinMOS Devices Having Elevated Source/Drain RegionsUS20090221105 *Feb 26, 2009Sep 3, 2009Renesas Technology Corp.Manufacturing method for semiconductor integrated circuit deviceUS20090250756 *Jun 16, 2009Oct 8, 2009Yark Yeon KimN-type schottky barrier tunnel transistor and manufacturing method thereofUS20100015802 *Sep 28, 2009Jan 21, 2010Avolare 2, LlcDynamic schottky barrier mosfet device and method of manufactureUS20100025774 *Feb 4, 2010Avolare 2, LlcSchottky barrier integrated circuitUS20100032771 *Feb 11, 2010Avolare 2, LlcShort-channel schottky-barrier mosfet device and manufacturing methodUS20100059819 *Mar 11, 2010Spinnaker Semiconductor, Inc.Power transistor with metal source and method of manufactureUS20110062525 *Mar 17, 2011International Business Machines CorporationMethod and structure for differential silicide and recessed or raised source/drain to improve field effect transistorUS20110068326 *Mar 24, 2011Moon-Gyu JangSchottky barrier tunnel transistor and method for fabricating the sameUS20120220111 *May 3, 2012Aug 30, 2012Macronix International Co.,Injection method with schottky source/drainWO2007109658A2 *Mar 20, 2007Sep 27, 2007Rochester Institute Of TechnologyShared metallic source/drain cmos circuits and methods thereof* Cited by examinerClassifications U.S. Classification438/199, 257/E27.068, 438/581, 257/E29.271International ClassificationH01L27/095, H01L29/51, H01L29/78Cooperative ClassificationH01L27/095, H01L29/517, H01L29/7839European ClassificationH01L29/78H, H01L27/095Legal EventsDateCodeEventDescriptionSep 5, 2003ASAssignmentOwner name: SPINNAKER SEMICONDUCTOR, INC., MINNESOTAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SNYDER, JOHN P.;LARSON, JOHN M.;REEL/FRAME:014451/0876Effective date: 20030819Dec 5, 2006CCCertificate of correctionJun 22, 2009REMIMaintenance fee reminder mailedSep 23, 2009ASAssignmentOwner name: AVOLARE 2 LLC, NORTH CAROLINAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SPINNAKER SEMICONDUCTOR, INC;REEL/FRAME:023263/0581Effective date: 20090914Owner name: AVOLARE 2 LLC,NORTH CAROLINAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SPINNAKER SEMICONDUCTOR, INC;REEL/FRAME:023263/0581Effective date: 20090914Dec 9, 2009SULPSurcharge for late paymentDec 9, 2009FPAYFee paymentYear of fee payment: 4Jul 26, 2013REMIMaintenance fee reminder mailedDec 9, 2013FPAYFee paymentYear of fee payment: 8Dec 9, 2013SULPSurcharge for late paymentYear of fee payment: 7RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services