Source: http://www.google.com/patents/US7271855?dq=Frischling
Timestamp: 2017-12-18 15:32:09
Document Index: 52473863

Matched Legal Cases: ['Application No. 2002', 'arts 6', 'arts 6', 'arts 6', 'arts 6', 'arts 6', 'arts 6', 'arts 6', 'arts 6', 'arts 6', 'arts 6', 'art 6', 'arts 6', 'arts 6', 'arts 6', 'arts 6', 'arts 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6']

Patent US7271855 - Liquid crystal display with pads having one edge having grooves therein ... - Google Patents
Disclosed is a method for fabricating a liquid crystal display. The method includes the steps of: forming a lower substrate and an upper substrate, the lower substrate including a data drive circuit connected with data lines of a thin film transistor array and a gate drive circuit connected with gate...http://www.google.com/patents/US7271855?utm_source=gb-gplus-sharePatent US7271855 - Liquid crystal display with pads having one edge having grooves therein wherein the edge is formed at a cutting line of the shorting bar
Publication number US7271855 B2
Application number US 10/689,623
Also published as US7768586, US20040085488, US20070285612
Publication number 10689623, 689623, US 7271855 B2, US 7271855B2, US-B2-7271855, US7271855 B2, US7271855B2
Inventors So Haeng Cho, Hyun Sang Chung
Patent Citations (12), Referenced by (4), Classifications (11), Legal Events (5)
Liquid crystal display with pads having one edge having grooves therein wherein the edge is formed at a cutting line of the shorting bar
US 7271855 B2
Disclosed is a method for fabricating a liquid crystal display. The method includes the steps of: forming a lower substrate and an upper substrate, the lower substrate including a data drive circuit connected with data lines of a thin film transistor array and a gate drive circuit connected with gate lines of the thin film transistor array, a pad part connected with the gate drive circuit and the data drive circuit, and a shorting bar connected with the pad part, the upper substrate including a color filter and a black matrix; dispensing a spacer on the lower substrate and forming a seal pattern at a display region on the upper substrate; attaching the lower substrate and the upper substrate to face with each other and then forming holes at an inner upper portion of the pads at a predetermined distance; scribing the holes-formed-portion of the pads to remove the shorting bar and dividing the attached upper and lower substrates into a plurality of LCD panels; and providing a liquid crystal layer between the upper and lower substrates.
a shorting bar, said shorting bar to be removed;
a plurality of gate lines, wherein the gate lines cross the data lines to define a plurality of pixel regions;
thin film transistors and pixel electrodes formed at respective pixel regions; and
at least one pad connected with the plurality of gate lines or the plurality of data lines, the pad having at least one edge having grooves therein,
wherein said grooves expose a passivation layer beneath said pad,
wherein the edge is formed at a cutting line of the shorting bar.
2. The liquid crystal display according to claim 1, the grooves having an upper boundary and a lower boundary, wherein the lower boundary of the grooves are located spaced apart by a predetermined distance from the at least one edge of the pad.
3. The liquid crystal display according to claim 1, wherein the grooves are formed at the uppermost portion of the pad.
4. The liquid crystal display according to claim 1, wherein the shorting bar has been removed by a scribing wheel passing over the upper boundary of the grooves.
5. The liquid crystal display according to claim 1, wherein the thin film transistor has an active region made of amorphous silicon.
a shorting bar, said shorting bar to be removed from said liquid crystal display device;
at least one pad connected with the plurality of gate lines or the plurality of data lines via a link pattern, the pad having at least one edge having grooves therein; and
a data drive circuit connected with the data lines and a gate drive circuit connected with the gate lines,
7. The liquid crystal display according to claim 6, the grooves having an upper boundary and a lower boundary, wherein the lower boundary of the grooves are located spaced apart by a predetermined distance from the at least one edge of the pad.
8. The liquid crystal display according to claim 6, wherein the grooves are formed at the uppermost portion of the pad.
9. The liquid crystal display according to claim 6, wherein the shorting bar has been removed by a scribing wheel passing on the locations where the holes are formed.
10. The liquid crystal display according to claim 6, wherein the thin film transistor has an active region made of poly silicon.
This application claims the benefit of Korean Patent Application No. 2002-66790, filed on Oct. 31, 2002, which is hereby incorporated by reference for all purposes as if fully set forth herein.
The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display structure with a simplified fabrication process, and a fabrication method thereof.
Generally, a liquid crystal display (LCD) displays an image corresponding to data signals on an LCD panel by controlling light transmittance of liquid crystal cells arranged in a matrix configuration on the LCD panel with video data signals supplied to each of the liquid crystal cells.
To achieve this, the LCD includes electrodes for applying an electric field to a liquid crystal layer, thin film transistors (TFTs) for selectively switching data supplied to the liquid crystal cells, data lines for supplying the liquid crystal cells with the data supplied from the exterior, and gate lines for supplying a control signal of the TFT.
The LCD is fabricated by various processes including a process of forming a lower substrate and an upper substrate of an LCD panel, accompanying a process for forming liquid crystal cells defining pixel units, a process of forming and rubbing an alignment film for aligning liquid crystal molecules, a process of attaching the upper substrate and the lower substrate, and a process of injecting and sealing liquid crystal between the upper plate and the lower plate. Here, a color filter, a common electrode and a black matrix are formed on the upper substrate. Signal lines such as data lines and gate lines are formed on the lower plate. Thin film transistor (TFT) is formed at a crossing portion of the data line and the gate line.
FIG. 1 is a plan view of a substrate of an LCD panel on which a plurality of thin film transistor arrays are formed.
Referring to FIG. 1, in the related art LCD fabrication method, a plurality of TFT arrays 13 are formed on a lower substrate 1. On the TFT array 13, gate lines 17 and data lines 15 are formed to cross each other at right angles. A thin film transistor (TFT) (not shown) and a pixel electrode (not shown) are formed at each crossing of the gate lines 17 and data lines 15. Each of the thin film transistor arrays 13 constitutes an independent display device.
Also, on the lower substrate 1, a pad part including a plurality of pads (not shown) connected with the data lines 15 and the gate lines 17 are provided. The pad part is connected with a shorting bar 12.
If the active layer of the thin film transistor provided on each pixel region of the LCD is made of polycrystalline silicon, a drive circuit can be formed by patterning polycrystalline silicon. Accordingly, a data drive circuit (not shown) connected with the data lines 15 of the thin film transistor array 13 and a gate drive circuit (not shown) connected with the gate lines 17 of the thin film transistor array 13 are mounted on the lower substrate 1. Also, the pad part (not shown) is connected with the gate drive circuit and the data drive circuit via corresponding link patterns. The shorting bar 12 is connected with the pad part. Here, the shorting bar 12 functions prevents static electricity from being generated while the fabrication processes are carried out.
Next, spacers are dispensed on the lower substrate 1, and seal pattern is formed on the upper substrate. The spacers and the seal pattern allow a gap to be formed between the upper substrate and the lower substrate. After that, the upper substrate 2 and the lower substrate 1 are attached to face each other, to form a mother LCD panel including a plurality of LCD panels. The mother LCD panel is then subjected to a scribing and/or breaking process and is thereby divided into a plurality of unit LCD panels.
After the scribing process is completed, liquid crystal is injected into the respective divided unit LCD panels through an injection hole in the seal pattern. The injection of the liquid crystal is carried out by the capillary phenomenon using a pressure difference between the inside of the LCD panel and the outside of the LCD panel. After the injection of the liquid crystal is completed, the injection holes are sealed and the divided unit LCD panels are subject to a grinding process in which the shorting bar is removed, and edges of the upper substrate and the lower substrate are ground to enhance a resistance against edge fracture that may be caused in the edges.
FIGS. 2A and 2B are plan views illustrating a periphery of a related art LCD. Specifically, FIG. 2A illustrates an amorphous silicon (a-Si) TFT LCD, and FIG. 2B illustrates a polycrystalline silicon (poly-Si) TFT LCD.
Referring to FIG. 2A, the related art LCD includes an upper substrate 2, a lower substrate 1 facing the upper substrate 2, a liquid crystal layer (not shown) interposed between the upper substrate 2 and the lower substrate 1, a plurality of pad parts 6 mounted on edges of the lower substrate 2, a plurality of data lines 15 and a plurality of gate lines 17 extending from respective pads 11 of the pad parts 6. The plurality of data lines 15 and the plurality of gate lines 17 are shaped in a matrix configuration. A pixel region (A) provided with thin film transistor and pixel electrode is formed at each of crossing portions of the plurality of data lines 15 and the plurality of gate lines 17.
The shorting bar 12 is provided above the pad parts 6 and is commonly connected with the pad parts 6. The shorting bar 12 is made of metal at edges of the lower substrate 1 corresponding to non-display region, and is removed from the lower substrate 1 while the edges of the lower substrate 1 are ground along cutting lines in the scribing process and the grinding process.
If the shorting bar 12 is removed as above, a tape carrier package (hereinafter referred to as ‘TCP’) is bonded on the pad parts by a drive circuit mounting method such as tape automated bonding (hereinafter referred to as ‘TAB’) method. In other words, output pads of the TCP are connected with the pad parts 6 on the lower substrate 1 and input pads of the TCP are connected with a printed circuit board (PCB).
Also, referring to FIG. 2B, the related art LCD includes an upper substrate 2, a lower substrate 1 facing the upper substrate 2, a liquid crystal layer (not shown) interposed between the upper substrate 2 and the lower substrate 1, a gate or data drive circuit 9 patterned on the lower substrate 1, for driving a plurality of data lines 15 or a plurality of gate lines 17, a plurality of pad parts 6 connected with the gate or data drive circuit 9 via a link pattern 4. The upper substrate 2 and the lower substrate 1 are attached to each other with a seal pattern 7 dispensed on edges of the upper substrate 2. Liquid crystal is injected into a space defined by attaching the upper substrate 2 and the lower substrate 1.
The gate or data drive circuit 9 is located within the seal pattern 7 within a region defined by attaching the upper substrate 2 and the lower substrate 1 and is connected with the data lines 15 or the gate lines 17. A pixel region (A) including thin film transistor and pixel electrode is formed at each of crossing portions of the data lines 15 and the gate lines 17.
Also, a shorting bar 12 is provided outside the pad parts 6 and is commonly connected with the pad parts 6. The shorting bar 12 is grounded to a GND terminal during the LCD fabrication process and functions to eliminate static electricity applied to the LCD panel. The shorting bar 12 is formed for the purpose of performing IPT (In Processing Test) for the plurality of pad parts 6.
The shorting bar 12 is made of metal at edges of the lower substrate 1 corresponding to non-display region and is removed from the lower substrate 1 while the edges of the lower substrate 1 are ground along cutting lines in the scribing process and the grinding process.
FIGS. 2A and 2B are discriminated from each other by a difference in the material of the active layer, i.e., the active layer of FIG. 2A being made of amorphous silicon while the active layer of FIG. 2B being made of polycrystalline silicon. Hence, according to the material used as the active layer, the drive circuit may be patterned on the lower substrate or formed separately from the lower substrate.
As a result, the structures of the pad parts formed on the lower substrate and the shorting bar connected with the pad parts shown in FIG. 2A are the same as those shown in FIG. 2B. However, there is a difference between FIG. 2A and FIG. 2B in that in case of FIG. 2A, the data lines 15 and the gate lines 17 extend directly from the respective pads 11 of the pad parts 6, but in case of FIG. 2B, the data lines 15 and the gate lines 17 extend via the link pattern 4 formed by patterning within the pad part 6 and the drive circuit 9 from the respective pads 11 of the pad parts 6.
FIGS. 3A to 3C are plan views illustrating a state in which the shorting bar 12 shown in a selected portion of FIG. 2B is removed. It is noted that FIGS. 3A to 3C describe such a state with the example of FIG. 2B, but the shorting bar shown in FIG. 2A can be also removed by the same method.
A related art method for removing the shorting bar 12 will be described hereinafter with reference to FIGS. 3A to 3C.
First, as illustrated in FIG. 3A, during the scribing process, the respective unit LCD panels, i.e., thin film transistor arrays, are divided. At this point, a scribing wheel 16 scribes the mother LCD panel (the panel containing multiple unit LCD panels) along a cutting line 14 formed above the shorting bar 12.
In other words, by the scribing process, a portion of the shorting bar 12 is removed, and the remaining portion of the shorting bar 12 connected with the pad parts 6 is removed from the lower substrate 1 while it is ground by a grinding process using a grinding machine 18. The removal process of the shorting bar 12 is illustrated in FIG. 3B.
Thus, while the mother LCD panel is subject to the scribing process and the grinding process, the shorting bar 12 formed in the respective unit LCD panels is completely removed. The structure of the pad part when the shorting bar 12 is completely removed is illustrated in FIG. 3C.
However, if the shorting bar is removed as above, the shorting bar of metal may generate a lot of particles during the removal process, so that the pad may be damaged.
In addition, the scribing process and the grinding process essentially used for removing the shorting bar make the fabrication process of the LCDs complicated.
Accordingly, the present invention is directed to a liquid crystal display and fabrication method thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide a liquid crystal display and fabrication method thereof in which holes are formed at predetermined locations of upper side of the pad part at a predetermined distance and a scribing wheel passes on the locations where the holes are formed to remove the shorting bar only by the scribing process, thereby reducing an occurrence amount of metal particles during the removal process of the shorting bar and simplifying the fabrication process of the LCD.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, there is provided a liquid crystal display provided with a thin film transistor and a pixel electrode which are formed at a cross portion of a plurality of gate lines and a plurality of data lines arranged in a matrix configuration. The liquid crystal display includes a pad connected with the plurality of gate lines or the plurality of data lines; and a shorting bar connected with the pad, wherein the pad connected with the shorting bar comprises holes formed in an inner upper portion of the pad at a predetermined distance. In the above LCD, the thin film transistor is an amorphous silicon TFT.
In an aspect of the invention, there is provided a liquid crystal display provided with a thin film transistor and a pixel electrode which are formed at a cross portion of a plurality of gate lines and a plurality of data lines arranged in a matrix configuration. The liquid crystal display includes a data drive circuit connected with the data lines and a gate drive circuit connected with the gate lines; a pad part connected with the gate drive circuit and the data drive circuit via a link pattern; and a shorting bar connected with the pad part, wherein the pad connected with the shorting bar comprises holes formed in an inner upper portion of the pad at a predetermined distance. In the above LCD, the thin film transistor is a polycrystalline silicon TFT.
In one aspect of the invention, there is provided a method for fabricating a liquid crystal display provided with a lower substrate including a plurality of pads connected with data lines and gate lines of a thin film transistor array, and a shorting bar to which the plurality of pads are connected, and an upper substrate including a color filter and a black matrix. The method includes the steps of: dispensing a spacer on the lower substrate and forming a seal pattern at a display region on the upper substrate; attaching the lower substrate and the upper substrate to face with each other and then forming holes at an inner upper portion of the pads at a predetermined distance; scribing the holes-formed-portion of the pads to remove the shorting bar and dividing the attached upper and lower substrates into a plurality of LCD panels; and providing a liquid crystal layer between the upper and lower substrates. In the above LCD, the thin film transistor is an amorphous silicon TFT.
In another aspect of the invention, there is provided a method for fabricating a liquid crystal display. The method includes the steps of: forming a lower substrate and an upper substrate, the lower substrate including a data drive circuit connected with data lines of a thin film transistor array and a gate drive circuit connected with gate lines of the thin film transistor array, a pad part connected with the gate drive circuit and the data drive circuit, and a shorting bar connected with the pad part, the upper substrate including a color filter and a black matrix; dispensing a spacer on the lower substrate and forming a seal pattern at a display region on the upper substrate; attaching the lower substrate and the upper substrate to face with each other and then forming holes at an inner upper portion of the pads at a predetermined distance; scribing the holes-formed-portion of the pads to remove the shorting bar and dividing the attached upper and lower substrates into a plurality of LCD panels; and providing a liquid crystal layer between the upper and lower substrates. In the above LCD, the thin film transistor is a polycrystalline silicon TFT.
FIG. 1 is a plan view of a substrate of a liquid crystal panel on which a plurality of thin film transistor arrays are formed;
FIGS. 2A and 2B are plan views illustrating a periphery of a related art LCD;
FIGS. 3A to 3C are plan views illustrating when the shorting bar shown in a selected portion of FIG. 2B is removed;
FIGS. 4A and 4B are plan views illustrating a drive circuit, a pad part and a shorting bar formed on a lower substrate of an LCD according to the present invention;
FIGS. 5A and 5B are plan views illustrating a pad part and a shorting bar formed on a lower substrate of an LCD according to the present invention;
FIGS. 6A and 6B are sectional views taken along the lines I-I′ and II-II′ of FIG. 4A; and
FIGS. 7A to 7C are plan views illustrating that the shorting bar shown in FIG. 4A is removed.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The present invention is not limited to the embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention.
FIGS. 4A and 4B are plan views illustrating a drive circuit, a pad part and a shorting bar formed on a lower substrate of an LCD according to the present invention. Specifically, FIGS. 4A and 4B illustrate a specific portion of a polycrystalline silicon TFT LCD, i.e., a region corresponding to the specific portion (B) of FIG. 2B according to the related art.
In the above, the polycrystalline silicon TFT means that the active region of a thin film transistor (TFT) provided in each pixel region of an LCD, i.e., a channel region, is formed of polycrystalline silicon.
Referring to FIGS. 4A and 4B, an LCD according to the invention includes an upper substrate 2, a lower substrate 1 facing the upper substrate 2, a liquid crystal layer (not shown) interposed between the upper substrate 2 and the lower substrate 1, a gate or data drive circuit 9 patterned on the lower substrate 1 for driving gate lines or data lines, and a plurality of pad parts 6 connected with the gate or data drive circuit 9 via a link pattern 4.
The upper substrate 2 and the lower substrate 1 are attached to each other with a seal pattern 7 dispensed on their edges. Liquid crystal is provided a space defined by attaching the upper substrate 2 and the lower substrate 1. The liquid crystal may be injected into the space after the lower and upper substrates 1 and 2 are attached or dispensed on the surface of one of the lower and upper substrates 1 and 2 before they are attached. The gate or data drive circuit 9 is located within the seal pattern 7 inside the attachment region and is connected with gate lines or data lines.
The LCD is also provided with a shorting bar 12, which is commonly connected with the plurality of pad parts 6. The shorting bar 12 is also grounded to a GND terminal during a fabrication process of the LCD to function to eliminate static electricity applied to the LCD panel. The shorting bar 12 is formed for the purpose of performing IPT (In Processing Test) for the plurality of pad parts 6.
According to the present invention, holes or open portions 20 are formed in predetermined portions of the pad part 6 at a predetermined location on the pad part 6 and may be spaced apart by a predetermined interval.
Generally, the shorting bar 12 is made of metal and is located at edges of the lower substrate 1 corresponding to non-display region and should be removed from the lower substrate 1 after the IPT is completed.
In the related art fabrication process of LCD, the attached panel is subject to the scribing process and the grinding process. The shorting bar 12 is finally removed by grinding an upper portion of the pad part connected with the shorting bar 12.
However, as reviewed in the above, since the shorting bar and the pad part are made of metal, a lot of metal particles are generated during the removal process of the shorting bar. As a result, the pad may be damaged. In addition, the scribing process and the grinding process essentially used for removing the shorting bar make the fabrication process of the LCDs complicated.
Hence, according to the present invention, holes 20, 20′ are formed in an inner upper portion of the pad part 6 connected with the shorting bar 12. The holes may be spaced apart at a constant interval. During fabrication, a scribing wheel passes on the locations where the holes 20, 20′ are formed to remove the shorting bar 12 and thus overcome the aforementioned drawback caused in the related art.
In more detail, according to the invention, the shorting bar 12 is substantially removed only by a scribing process without being subject to the grinding process. Also, since the holes 20 are formed at locations where the scribing wheel passes, the amount of metal particle that is generated during the scribing process is decreased compared with that in the related art.
Moreover, the holes may be formed at the inner upper portion of the pad part 6 connected with the shorting bar 12 at a constant interval and a predetermined distance from the shorting bar 12 or the edge of the pad part 6. In addition, the holes 20 may be made in various shapes, as may be appreciated by those of skill in the art. FIGS. 4A and 4B illustrate examples of various embodiments of the present invention according to the modification in the shape of the hole 20.
First, in case of FIG. 4A, hole 20 is not formed immediately adjacent the edge of the pad part 6 connected with the shorting bar 12, taking into account resistance against a signal supplied through the pad part 6 while the IPT is carried out. Instead, the holes 20 may be formed at a predetermined portion below the edge or uppermost portion of the pad part 6 at a constant distance from the edge of the pad part 6. It is noted that the holes 20 may be formed wider relative to the hole 20′ shown in FIG. 4B.
On the contrary, in case of FIG. 4B, hole 20′ is formed closer to the edge of the pad part 6 connected with the shorting bar 12 and may have a narrower width than the hole 20 of FIG. 4A, thereby preventing resistance against a signal supplied through the pad part 6 from being increased. In addition, the holes 20′ of the embodiment of FIG. 4B may have a reduced area compared to the holes 20 of the embodiment of FIG. 4A. As illustrated in FIG. 4B, the holes 20′ may extend to the edge of the pad part 6.
There is an advantage to the holes having a greater area in that fewer particles are generated owing to a larger open, i.e., metal, area. However, the greater hole area may result in a reduced area through which the scribing wheel may be applied. For example, the hole area in the embodiment of FIG. 4A results in fewer particles being generated than the hole area provided in the embodiment of FIG. 4B, whereas the embodiment of FIG. 4B has an advantage in that failure rate is lowered since the passage through which the scribing wheel passes is widened.
FIGS. 5A and 5B are plan views showing a pad part and a shorting bar formed on a lower substrate of an LCD according to the present invention. Specifically, FIGS. 5A and 5B show a specific portion of an amorphous silicon TFT LCD, i.e., a region corresponding to the specific portion (C) of FIG. 2A according to the related art.
In the above, the amorphous silicon TFT means that the active region of a thin film transistor (TFT) provided in each pixel region of an LCD, i.e., channel region, is formed of amorphous silicon.
The structures of FIGS. 5A and 5B are similar to those of FIGS. 4A and 4B, but have differences in that the pad part is comprised of respective independent pads 11, and the gate lines or the data lines 15 extend directly from the pad 11.
Accordingly, the amorphous silicon TFT LCD according to an embodiment of the present invention is characterized in that the drive circuit is not formed within the substrate, unlike those of FIGS. 4A and 4B; and the holes 20, 20′ are formed at an upper portion of each of the independent pads 11, unlike the holes 20, 20′ formed at the upper portion of the single pad part 6, as illustrated in FIGS. 4A and 4B.
In other words, in forming the holes 20, 20′ and removing the shorting bar 12 by the scribing process, the embodiment of FIG. 5A is similar in the process and hole shape to that of FIG. 4A, and the embodiment of FIG. 5B is similar in the process and hole shape to that of FIG. 4B.
However, there is only a difference between them in that the embodiment of FIGS. 4A and 4B has the holes 20, 20′ formed in the single pad part but the embodiment of FIGS. 5A and 5B has the holes 20, 20′ formed respectively in the independent pad parts.
FIGS. 6A and 6B are sectional views taken along the lines I-I′ and II-II′ of FIG. 4A.
FIGS. 6A and 6B are the same as the sectional views taken along the lines I-I′ and II-II′ for viewing a specific portion of the pad and are described with reference to FIG. 4A only for the convenience of description.
Referring to FIG. 6A, the section of the pad part in which the holes are not formed, includes a thin metal film pattern 3, and a transparent conductive pattern 5, which is patterned along with the pixel electrode. The thin metal film pattern 3 is formed on a gate insulating layer 1 a of inorganic insulator and is patterned along with source/drain electrode of a thin film transistor, a data line connected with the source electrode, and a link pattern.
Also, the transparent conductive pattern 5 is connected with the thin metal film pattern 3 through a contact hole (not shown) formed in a passivation layer 8 of inorganic material or organic material.
The section of the pad part in which the holes are formed is illustrated in FIG. 6B, and is distinguished from the section of FIG. 6A in that the holes 20 are formed at a constant interval and distance, thereby the passivation layer 8 of inorganic material or organic material is directly exposed to the outside through the holes 20.
Thus, the transparent conductive pattern shown in FIG. 6B is formed by an exposing process and a developing process using a photomask having exposure regions corresponding to the holes 20.
FIGS. 7A to 7C are plan views illustrating that the shorting bar illustrated in FIG. 4A is removed.
It is obvious to those skilled to the art that the removal process of the shorting bar 12 can be equivalently applied to those of FIGS. 4B, 5A and 5B.
Hereinafter, there will be reviewed a removal process of the shorting bar 12 according to the invention with reference to FIGS. 7A to 7C.
First, as shown in FIG. 7A, holes 20 are formed in an inner upper portion of the pad part 6 connected with the shorting bar 12 at a constant distance. In this state, a scribing wheel 16 is aligned to pass on the locations where the holes 20 are formed. At this point, the scribing wheel 16 should pass the portions where the holes 20 are formed, i.e., a path inside a scribe line margin 22.
As the scribing wheel 16 passes on the locations where the holes 20 are formed, the shorting bar 12 is removed from the lower substrate. The removing step of the shorting bar 12 is illustrated in FIG. 7B. By doing so, the grinding step, which is essentially used for removing the shorting bar 12 in the related art, is omitted.
Thus, by performing the scribing process, the shorting bar formed in the respective divided LCD panels. In FIG. 7C, there is illustrated a structure of the pad part 6 when the shorting bar 12 is removed.
As described previously, according to an LCD and fabrication method thereof according to the invention, the shorting bar is removed by one scribing process. As a result, the fabrication process of the LCD is simplified and, accordingly, the production space necessary for a clean room can be reduced.
Also, since holes ate formed in the cutting portion of the pad part at a constant distance, metal particles are reduced during the scribing process, so that pad damage can be minimized.
US5825439 * Dec 22, 1995 Oct 20, 1998 Kabushiki Kaisha Toshiba Array substrate for display
US5929958 * May 15, 1998 Jul 27, 1999 Hitachi, Ltd. Liquid crystal display device with wide viewing angle characteristics
US6633361 * Jun 2, 2000 Oct 14, 2003 Nec Lcd Technologies, Ltd. LCD panel in which signal line terminals have slits to allow inspection of alignment of the terminals and the TCP leads
US6870559 * Apr 1, 2003 Mar 22, 2005 Canon Kabushiki Kaisha Image forming apparatus
US20050094045 * Dec 6, 2004 May 5, 2005 Gee-Sung Chae Array substrate for a liquid crystal display device and method for fabricating thereof
JPH0772508A * Title not available
JPH0882805A * Title not available
JPH05265021A * Title not available
JPH06146225A * Title not available
JPH08201833A * Title not available
US7692617 * Apr 20, 2005 Apr 6, 2010 Samsung Electronics Co., Ltd. Thin film transistor array panel and display device including the same
US9310657 Feb 17, 2010 Apr 12, 2016 Samsung Display Co., Ltd. Thin film transistor array panel and display device including the same
US20060022201 * Apr 20, 2005 Feb 2, 2006 Samsung Electronics Co., Ltd. Thin film transistor array panel and display device including the same
US20100141622 * Feb 17, 2010 Jun 10, 2010 Dong-Gyu Kim Thin film transistor array panel and display device including the same
U.S. Classification 349/40, 349/152, 349/149
International Classification G02F1/1333, G02F1/1362, G02F1/1345
Cooperative Classification G02F1/13458, G02F1/136204, G02F1/133351
European Classification G02F1/1345T, G02F1/1362A
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHO, SO HAENG;CHUNG, HYUN SANG;REEL/FRAME:014635/0128
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHO, SO HAENG;CHUNG, HYUN SANG;REEL/FRAME:019740/0293