Source: http://www.google.com/patents/US6313520?dq=5251294
Timestamp: 2014-09-17 01:58:34
Document Index: 127199669

Matched Legal Cases: ['arts 16', 'arts 16', 'arts 16', 'art 16', 'art 16', 'art 16', 'arts 16', 'arts 16']

Patent US6313520 - Resin-sealed power semiconductor device including substrate with all ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA resin-sealed power semiconductor device is provided. The thicknesses of a die pad (19) and a lead part (2) are made equal and as great as possible. A thick film substrate (8) is bonded with a bonding layer (20) onto a plurality of supporting inner leads (2AS) among first inner leads (2A1) positioned...http://www.google.com/patents/US6313520?utm_source=gb-gplus-sharePatent US6313520 - Resin-sealed power semiconductor device including substrate with all electronic components for control circuit mounted thereonAdvanced Patent SearchPublication numberUS6313520 B1Publication typeGrantApplication numberUS 09/664,341Publication dateNov 6, 2001Filing dateSep 18, 2000Priority dateMar 7, 2000Fee statusPaidAlso published asDE60042110D1, EP1143514A2, EP1143514A3, EP1143514B1Publication number09664341, 664341, US 6313520 B1, US 6313520B1, US-B1-6313520, US6313520 B1, US6313520B1InventorsTakanobu Yoshida, Toshiaki Shinohara, Hisashi KawafujiOriginal AssigneeMitsubishi Denki Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (10), Referenced by (39), Classifications (44), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetResin-sealed power semiconductor device including substrate with all electronic components for control circuit mounted thereonUS 6313520 B1Abstract A resin-sealed power semiconductor device is provided. The thicknesses of a die pad (19) and a lead part (2) are made equal and as great as possible. A thick film substrate (8) is bonded with a bonding layer (20) onto a plurality of supporting inner leads (2AS) among first inner leads (2A1) positioned above the die pad (19). Patterns of a control circuit of power semiconductor elements (1) are formed as thick film patterns (10) on an upper surface of the substrate (8), and a control circuit element (IC) (9) and all electronic components (12) are mounted on the patterns (10) by soldering. The constituents (9, 12, 10, 8, 1, 2A1, 19, 2B1) are sealed in a sealing resin (5). The resin-sealed power semiconductor device improves noise immunity while conventionally effectively dissipating heat generated by the power semiconductor elements, and is designed to be adaptable to increase in functionality thereof.
What is claimed is: 1. A resin-sealed power semiconductor device comprising:
a frame part comprising a lead part having a plurality of inner leads and a plurality of outer leads continuous respectively with said plurality of inner leads, and a die pad equal in thickness to said lead part; a power semiconductor element mounted on a portion of said die pad; a substrate bonded onto a support of said frame part except said portion of said die pad; a pattern of a control circuit of said power semiconductor element, said control circuit pattern being formed on at least a first main surface of said substrate; a semiconductor element mounted on said control circuit pattern for controlling said power semiconductor element; electronic components all mounted on said control circuit pattern and constituting said control circuit in conjunction with said semiconductor element; and a sealing resin for sealing therein said plurality of inner leads, said die pad, said power semiconductor element, said substrate, said semiconductor element and all of said electronic components. 2. The resin-sealed power semiconductor device according to claim 1,
wherein said support of said frame part comprises at least two supporting inner leads among said plurality of inner leads. 3. The resin-sealed power semiconductor device according to claim 2,
wherein said substrate is a ceramic substrate, and wherein said control circuit pattern is a thick film pattern. 4. The resin-sealed power semiconductor device according to claim 2,
wherein said substrate is a glass epoxy substrate. 5. The resin-sealed power semiconductor device according to claim 2,
wherein said substrate comprises a plurality of through hole parts equal in number to said at least two supporting inner leads; wherein a conducting pattern is provided for each of said through hole parts and formed on a wall surface of each of said through hole parts and on portions of said first main surface and a second main surface of said substrate which surround each of said through hole parts; and wherein a portion of said conducting pattern on said second main surface is bonded with a conductive bonding layer to an associated one of said at least two supporting inner leads. 6. The resin-sealed power semiconductor device according to claim 5,
wherein said substrate is a glass epoxy substrate. 7. The resin-sealed power semiconductor device according to claim 2,
wherein said support comprises supporting inner leads adjacent to each other. 8. The resin-sealed power semiconductor device according to claim 1,
wherein said support of said frame part corresponds to another portion of said die pad. 9. The resin-sealed power semiconductor device according to claim 1,
wherein said support of said frame part comprises first and second supporting inner leads among said plurality of inner leads; wherein at least one intermediate inner lead among said plurality of inner leads which is present between said first and second supporting inner leads is shorter than said first and second supporting inner leads; wherein said substrate includes a first end portion supported by said first supporting inner lead, with a bonding layer therebetween, a second end portion opposite from said first end, portion and supported by said second supporting inner lead, with said bonding layer therebetween, and third and fourth end portions opposite from each other and orthogonal to said first and second end portions, said third and fourth end portions being unsupported by said at least one intermediate inner lead; wherein said control circuit pattern includes a first control circuit pattern formed on a first main surface of said substrate, and a second control circuit pattern formed on a second main surface of said substrate, said second main surface being opposite from said first main surface; and wherein said semiconductor element and some of said electronic components are mounted on said first control circuit pattern, and the remainder of said electronic components are mounted on said second control circuit pattern. 10. The resin-sealed power semiconductor device according to claim 9,
wherein said substrate is a glass epoxy substrate.
SUMMARY OF THE INVENTION According to a first aspect of the present invention, a resin-sealed power semiconductor device comprises: a frame part comprising a lead part having a plurality of inner leads and a plurality of outer leads continuous respectively with the plurality of inner leads, and a die pad equal in thickness to the lead part; a power semiconductor element mounted on a portion of the die pad; a substrate bonded onto a support of the frame part except the portion of the die pad; a pattern of a control circuit of the power semiconductor element, the control circuit pattern being formed on at least a first main surface of the substrate; a semiconductor element mounted on the control circuit pattern for controlling the power semiconductor element; electronic components all mounted on the control circuit pattern and constituting the control circuit in conjunction with the semiconductor element; and a sealing resin for sealing therein the plurality of inner leads, the die pad, the power semiconductor element, the substrate, the semiconductor element and all of the electronic components.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a vertical sectional view of a semiconductor device according to a first preferred embodiment of the present invention;
On the other hand, a thick film substrate 8 is bonded with a bonding layer 20 comprising, for example, a brazing material, an adhesive or a bonding tape onto upper surfaces of a plurality of inner leads (referred to as supporting inner leads) 2AS constituting the �support of the frame part� among the plurality of second inner leads 2A1. The thick film substrate 8 used herein is a ceramic substrate (e.g., an alumina substrate or an AlN substrate) which allows a thick film pattern to be formed on at least its first main surface. On the first main surface or upper surface of the thick film substrate 8 are formed all patterns 10 of thick film required to constitute the control circuit of the power semiconductor elements 1. A semiconductor element (IC) 9 comprising a microcomputer and the like for controlling the power semiconductor elements 1 is mounted on one of the thick film patterns 10 by soldering, and all electronic components (resistors, capacitors and the like) 12 constituting the control circuit are mounted on the other thick film patterns 10 by soldering. Thin metal wires 11 establish electric connection between electrodes of the semiconductor element 9 and bonding pads 18 of the thick film substrate 8 and between electrodes of the element 9 and electrodes of the electronic components 12. Thin metal wires 13 establish connection between the upper surfaces of the supporting inner leads 2AS serving as a first electrode and the thick film patterns 10 or the bonding pads 18 on the thick film substrate 8, and also establish electric connection between electrodes of the power semiconductor elements 1 and the patterns 10 or the bonding pads 18 of the thick film substrate 8. A thin metal wire 13A (13) with its first end directly bonded onto the upper surface of the die pad 19 establishes electric connection between one of the bonding pads 18 of the thick film substrate 8 and the upper surface of the die pad 19 at its arbitrary position. All of the first inner leads 2A1 including the supporting inner leads 2AS, all of the second inner leads 2B1, the thick film substrate 8 on which the semiconductor element 9 and all of the electronic components 12 are mounted, the power semiconductor elements 1, the die pad 19, and the thin metal wires 4, 11, 13 are sealed in a sealing resin 5. Each of the plurality of first and second outer leads 2A2 and 2B2 projecting outwardly from the sealing resin 5 is formed into a suitable configuration, e.g. substantially L-shaped cross-sectional configuration, and has a tip subjected to surface treatment such as solder plating.
(2) A portion of the die pad 19 on which the power semiconductor elements 1 are not formed may be used as the �support� of the thick film substrate 8 having the structure shown in FIG. 1, in place of the supporting inner leads 2AS of the first preferred embodiment. An example of such an arrangement is shown in FIG. 4. In this modification, as schematically shown in FIG. 4, all of the first inner leads 2A1 function only as the first electrode to be electrically connected to an external device or customer's device.
(3) A glass epoxy substrate with the control circuit patterns formed on only one of the main surfaces (a first main surface) thereof may be used as the substrate for the control circuit for mounting thereon the semiconductor element 9 and all of the electronic components 12, in place of the thick film substrate 8 of the first preferred embodiment shown in FIGS. 1 and 2. The heart of such an arrangement is schematically shown in perspective view of FIG. 5. As shown in FIG. 5, a second main surface or bottom surface of a glass epoxy substrate 14A is bonded to the upper surface of each of the supporting inner leads 2AS with the bonding layer 20 such as an adhesive or a bonding tape. All control circuit patterns 10A (including bonding pads) of copper foil are formed on the first main surface or upper surface of the substrate 14A, and the semiconductor element (IC) 9 and all of the electronic components 12 are mounted on the patterns 10A.
The modifications (1) and (2) may be applied to the modification (3) and to a modification (4) to be described later.
Further, the modification (3) may be also modified in such a manner that the glass epoxy substrate 14A is bonded with the bonding layer 20 onto the upper surfaces of the two inner leads 2AS opposed to each other, with the short intermediate inner leads 2AM arranged therebetween, as illustrated in FIG. 13.
An object of this modification is to establish electric connection between pattern portions constituting the bonding pads of the glass epoxy substrate 14A and the corresponding supporting inner leads 2AS by means of patterns provided in through hole parts formed in the substrate 14A in place of the wire bonding using the thin metal wires. To this end, the glass epoxy substrate 14A comprises through hole parts 16 extending through the substrate 14A, the number of through hole parts 16 being equal to the number of supporting inner leads 2AS supporting the substrate 14A. A conducting pattern 15 c is provided for each of the through hole parts 16, and is formed on a wall surface of each through hole part 16 and on portions of the first main surface (upper surface) and the second main surface (bottom surface) of the substrate 14 which surround each through hole part 16. A portion of the pattern 15 c on the upper surface is wire-bonded by a thin metal wire to the semiconductor element 9 or one of the electronic components 12 (not shown) on the substrate 14A, as illustrated in FIG. 6. The portion of the pattern 15 c on the upper surface may be electrically connected to an extension of the control circuit patterns of the substrate 14A. In other words, the portion of the pattern 15 c on the upper surface is electrically connected to an electrode of the corresponding semiconductor element 9 or electronic component by at least the thin metal wire. A portion of the conducting pattern 15 c on the bottom surface or second main surface is bonded to the upper surface portion of the supporting inner lead 2AS corresponding to the pattern 15 c or the through hole part 16 by a conductive bonding layer 17 such as a brazing material. Each bonding layer 17 serves to bond the supporting inner lead 2AS corresponding thereto and the bottom surface portion of the glass epoxy substrate 14A in contact with the lead 2AS to each other, and to provide electric continuity between the control circuit patterns 10A on the substrate 14A and the supporting inner lead 2AS serving as the first electrode for connection to the external device.
FIG. 7 is a perspective view schematically showing principal parts of the resin-sealed power semiconductor device according to a second preferred embodiment of the present invention. FIGS. 8 and 9 are cross-sectional views taken along the line I�II and the line III-IV of FIG. 7, respectively. For purposes of illustration, the cross-sectional configurations of the through hole parts 16 are shown in the cross sections of FIGS. 8 and 9.
The second preferred embodiment features the use of a double-sided board mounted glass epoxy substrate 14 as the substrate in place of the thick film substrate 8 of the first preferred embodiment. More specifically, all of the electronic components 12 and the semiconductor element (IC) 9 which constitute the control circuit are mounted by soldering or the like on first and second control circuit patterns 15 a and 15 b (generically referred to as control circuit patterns) formed respectively on a first main surface (upper surface) and a second main surface (bottom surface opposite from the upper surface) of the glass epoxy substrate 14. In particular, in the second preferred embodiment, the element 9 and some of the electronic components 12 are connected to the first control circuit pattern 15 a through solder or the like, and the remaining electronic components 12 are mounted on the second control circuit pattern 15 b with solder or the like therebetween. The patterns 15 a and 15 b on the opposite sides are electrically connected to each other through the through hole parts 16 provided in any position within the substrate 14.
Additionally, the bottom surfaces of opposed first and second end portions extending along the shorter sides of the glass epoxy substrate 14 are bonded with the bonding layer 20 such as an adhesive to only the upper surfaces of first and second supporting inner leads 2AS1 and 2AS2 among the plurality of inner leads 2A1. At least one inner lead (referred to as an intermediate inner lead) 2AM between the first and second supporting inner leads 2AS1 and 2AS2 is shorter in length than the first and second supporting inner leads 2AS1 and 2AS2. Opposed third and fourth end portions of the substrate 14 extending along the longer sides thereof and orthogonal to the first and second end portions are not supported by the upper surface of the at least one intermediate inner lead 2AM. In this state, the constituents 1, 19, 2A1, 2B1, 9, 12, 14, 15 a, 15 b, 16 are sealed in the sealing resin 5.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5083189 *Apr 9, 1990Jan 21, 1992Kabushiki Kaisha ToshibaResin-sealed type IC deviceUS5291054 *Jun 23, 1992Mar 1, 1994Sanyo Electric Co., Ltd.Light receiving module for converting light signal to electric signalUS5313095 *Jan 29, 1993May 17, 1994Mitsubishi Denki Kabushiki KaishaMultiple-chip semiconductor device and a method of manufacturing the sameUS5434449 *Aug 4, 1994Jul 18, 1995Mitsubishi Denki Kabushiki KaishaSemiconductor device in a single package with high wiring density and a heat sinkUS5703399 *May 15, 1996Dec 30, 1997Mitsubishi Denki Kabushiki KaishaSemiconductor power moduleUS5767573 *Apr 17, 1996Jun 16, 1998Mitsubishi Denki Kabushiki KaishaSemiconductor deviceUS5792676 *Jun 5, 1996Aug 11, 1998Mitsubishi Denki Kabushiki KaishaMethod of fabricating power semiconductor device and lead frameUS5998856 *Nov 28, 1996Dec 7, 1999Mitsubishi Denki Kabushiki KaishaSemiconductor deviceUS6002166 *Nov 28, 1996Dec 14, 1999Mitsubishi Denki Kabushiki KaishaSemiconductor deviceUS6184585 *Nov 13, 1998Feb 6, 2001International Rectifier Corp.Co-packaged MOS-gated device and control integrated circuit* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6432750 *Feb 22, 2001Aug 13, 2002Fairchild Korea Semiconductor Ltd.Power module package having insulator type heat sink attached to rear surface of lead frame and manufacturing method thereofUS6486535 *Mar 20, 2001Nov 26, 2002Advanced Semiconductor Engineering, Inc.Electronic package with surface-mountable device built thereinUS6545364 *Mar 16, 2001Apr 8, 2003Sanyo Electric Co., Ltd.Circuit device and method of manufacturing the sameUS6627982 *May 7, 2001Sep 30, 2003Stmicroelectronics S.R.L.Electrical and electronic apparatus comprising semiconductor bodies housing integrated circuits having terminals, supports and electrodes; radio or high frequency oscillatorsUS6710439 *Sep 12, 2002Mar 23, 2004Fairchild Korea Semiconductor Ltd.Bonding wire for electrically coupling of control circuit terminals; encapsulating moldingUS6727575 *Sep 17, 2001Apr 27, 2004Mitsubishi Denki Kabushiki KaishaSemiconductor deviceUS6765285Mar 5, 2003Jul 20, 2004Mitsubishi Denki Kabushiki KaishaPower semiconductor device with high radiating efficiencyUS6798044 *Dec 4, 2000Sep 28, 2004Fairchild Semiconductor CorporationFlip chip in leaded molded package with two diesUS6833608 *Nov 15, 2002Dec 21, 2004Sanyo Electric Co., Ltd.Semiconductor device and packaging system thereforeUS7061080 *Jun 10, 2002Jun 13, 2006Fairchild Korea Semiconductor Ltd.Power module package having improved heat dissipating capabilityUS7145223 *Apr 28, 2003Dec 5, 2006Matsushita Electric Industrial Co., Ltd.Semiconductor deviceUS7196909 *Feb 4, 2004Mar 27, 2007Sumitomo Electric Industries, Ltd.AC coupling circuit having a large capacitance and a good frequency responseUS7208819 *Oct 26, 2004Apr 24, 2007Fairchild Korea Semiconductor Ltd.Power module package having improved heat dissipating capabilityUS7405467 *Sep 22, 2005Jul 29, 2008Cyntec Co., Ltd.Power module package structureUS7642638Dec 19, 2007Jan 5, 2010United Test And Assembly Center Ltd.Inverted lead frame in substrateUS7659608 *Sep 15, 2006Feb 9, 2010Stats Chippac Ltd.Stacked die semiconductor device having circuit tapeUS7786575Dec 4, 2009Aug 31, 2010Stats Chippac Ltd.Stacked die semiconductor device having circuit tapeUS7800224 *Dec 28, 2007Sep 21, 2010Fairchild Korea Semiconductor, Ltd.Power device packageUS7935899 *Aug 30, 2006May 3, 2011Sanyo Electric Co., Ltd.Circuit device and method of manufacturing the sameUS8102047May 27, 2010Jan 24, 2012Denso CorporationLoad driving deviceUS8203848 *Aug 30, 2006Jun 19, 2012Sanyo Electric Co., Ltd.Circuit device and method of manufacturing the sameUS8471373 *Jun 3, 2011Jun 25, 2013Panasonic CorporationResin-sealed semiconductor device and method for fabricating the sameUS8471374 *Feb 21, 2007Jun 25, 2013Stats Chippac Ltd.Integrated circuit package system with L-shaped leadfingersUS8471381 *Jun 30, 2006Jun 25, 2013Vishay-SiliconixComplete power management system implemented in a single surface mount packageUS8472196 *Mar 16, 2011Jun 25, 2013Delta Electronics, Inc.Power moduleUS8547709Feb 12, 2010Oct 1, 2013Cyntec Co. Ltd.Electronic system with a composite substrateUS8692377Mar 23, 2011Apr 8, 2014Stats Chippac Ltd.Integrated circuit packaging system with plated leads and method of manufacture thereofUS8699228 *Feb 23, 2012Apr 15, 2014Panasonic CorporationPower moduleUS8809118 *Oct 22, 2012Aug 19, 2014Marvell World Trade Ltd.Chip on leadsUS20100176498 *Mar 24, 2010Jul 15, 2010Fairchild Korea Semiconductor, Ltd.Power module package having excellent heat sink emission capability and method for manufacturing the sameUS20120014069 *Mar 16, 2011Jan 19, 2012Jian-Hong ZengPower moduleUS20120112332 *Jun 3, 2011May 10, 2012Masanori MinamioResin-sealed semiconductor device and method for fabricating the sameUS20120218717 *Feb 23, 2012Aug 30, 2012Panasonic CorporationPower moduleUS20130045573 *Oct 22, 2012Feb 21, 2013Marvell World Trade Ltd.Chip on leadsCN101283449BJun 30, 2006Aug 20, 2014维税-希力康克斯公司以单个贴装封装实现的完整功率管理系统CN101373761BDec 24, 2007Jun 27, 2012崇贸科技股份有限公司Multi-chip module packageCN102339818BJul 15, 2010Apr 30, 2014台达电子工业股份有限公司Power module and manufacture method thereofCN102340233BJul 15, 2010May 7, 2014台达电子工业股份有限公司功率模块DE102010000199B4 *Jan 26, 2010Jul 17, 2014Infineon Technologies AgEinkapselungsverfahren* Cited by examinerClassifications U.S. Classification257/676, 257/666, 257/724, 257/691, 257/E25.03, 257/E23.052International ClassificationH01L25/16, H01L23/495, H01L23/28, H01L25/07, H01L23/34, H01L21/60, H01L23/50, H01L25/18Cooperative ClassificationH01L24/48, H01L23/49575, H01L2224/32245, H01L2924/01082, H01L2924/19107, H01L2924/01078, H01L2224/73265, H01L2924/01013, H01L2224/48247, H01L2224/48137, H01L2924/01029, H01L2224/4911, H01L2924/01004, H01L2924/01006, H01L2924/014, H01L24/49, H01L25/162, H01L2224/45124, H01L2924/19041, H01L2924/13055, H01L24/45, H01L2924/09701, H01L2924/19043, H01L2924/01005, H01L2924/13091, H01L2924/01033, H01L2224/48091European ClassificationH01L24/49, H01L25/16F, H01L23/495LLegal EventsDateCodeEventDescriptionMar 7, 2013FPAYFee paymentYear of fee payment: 12Apr 8, 2009FPAYFee paymentYear of fee payment: 8Apr 13, 2005FPAYFee paymentYear of fee payment: 4Sep 17, 2001ASAssignmentOwner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YOSHIDA, TAKANOBU;SHINOHARA, TOSHIAKI;KAWAFUJI, HISASHI;REEL/FRAME:012165/0415Effective date: 20000719Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA 2-3, MARUNOUCHIFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YOSHIDA, TAKANOBU /AR;REEL/FRAME:012165/0415Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA 2-3, MARUNOUCHIRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google