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Timestamp: 2018-06-21 14:33:50
Document Index: 164060766

Matched Legal Cases: ['Application No. 05852180', 'Application No. 09167223', 'Application No. 11', 'Application No. 11168734', 'Application No. 05852180', 'Application No. 11168735', 'Application No. 07', 'Application No. 2007']

Multi-column addressing mode memory system including an integrated circuit memory device - Rambus Inc.
United States Patent 8908466
Lai, Lawrence (San Jose, CA, US)
Bellows, Chad A. (Northville, MI, US)
Richardson, Wayne S. (Saratoga, CA, US)
13/860825
711/5, 711/105, 711/154, 711/168
G11C8/14; G11C8/10; G11C8/12; G11C8/16
711/5, 711/105, 711/154, 365/189.04, 365/230.03, 365/230.06, 365/233
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This application is a continuation of U.S. patent application Ser. No. 13/410254, filed Mar. 1, 2012, which is a continuation of U.S. patent application Ser. No. 13/239846, filed Sep. 22, 2011 (now U.S. Pat. No. 8,154,947), which is a divisional of U.S. patent applicant Ser. No. 13/019,785, filed Feb. 2, 2011 (now U.S. Pat. No. 8,050,134), which is a continuation of U.S. patent application Ser. No. 12/391,873, filed Feb. 24, 2009 (now U.S. Pat. No. 7,907,470), which is a continuation of U.S. patent application Ser. No. 11/853,708 (now U.S. Pat. No. 7,505,356), which is a continuation of U.S. patent application Ser. No. 10/955,193 (now U.S. Pat. No. 7,280,428), each entitled “Multi-Column Addressing Mode Memory System Including an Integrated Circuit Memory Device.” Each of these earlier applications and patents are hereby incorporated by reference.
1. An apparatus to interact with a memory integrated circuit characterized by a row decoder cycle time, the apparatus comprising: a command interface to convey read commands to the memory integrated circuit; and a data interface to receive data from the memory integrated circuit via a data interconnect responsive to the read commands; wherein the apparatus has two operational modes, including a first operational mode in which the apparatus is to issue via the command interface a first read command to access a single column of an open row of the memory integrated circuit during the row decoder cycle time, and a second operational mode in which the apparatus is to issue via the command interface a second read command to access two columns of the open row of the memory integrated circuit within the row decoder cycle time, using respective column addresses that can be selectively offset relative to one another.
2. The apparatus of claim 1, embodied as at least one of a memory controller or a graphics controller.
3. The apparatus of claim 2, wherein: the command interface and data interface are embodied as a dynamic random access memory (DRAM) controller integrated circuit; the memory integrated circuit comprises a DRAM integrated circuit; and said apparatus further embodied as a module comprising the DRAM controller integrated circuit and the DRAM integrated circuit.
4. The apparatus of claim 1, wherein the data interface is operable to receive data from the data interconnect at a maximum data width of the data interconnect irrespective of whether the apparatus is operated in the first operational mode or the second operational mode, the maximum data width corresponding to a maximum number of bits that can be concurrently received via respective data lines of the data interconnect.
5. The apparatus of claim 4, wherein during the second operational mode, the data interface is operable to receive the data as respective columns of data corresponding to the respective column addresses in a manner where each of the respective columns of data is received at the maximum data width at respective times over the data interconnect.
6. The apparatus of claim 4, wherein, during the second operational mode, the data interface is operable to concurrently receive respective columns of data corresponding to the respective column addresses, each in a manner corresponding to a respective half of the maximum data width.
7. The apparatus of claim 1, wherein the apparatus further comprises circuitry to program a register of the memory integrated circuit to operate in a first mode, if the apparatus is to operate in the first operational mode, and a second mode, if the apparatus is to operate in the second operational mode.
8. The apparatus of claim 1, wherein the apparatus further has a third operational mode in which the apparatus is to issue via the command interface a third read command to access four columns of the open row of the memory integrated circuit within the row decoder cycle time, using four respective column addresses that can be selectively offset variable relative to one another.
9. The apparatus of claim 1, wherein the apparatus comprises circuitry to generate the second read command as a command packet having two fields adapted to each carry a different one of the respective column addresses.
10. The apparatus of claim 1, adapted for use where the memory integrated circuit comprises multiple banks, wherein the apparatus is to issue each of the read commands in a manner that contains a bank address field to select one of the multiple banks.
11. The apparatus of claim 1, wherein the respective column addresses are directed to respective halves of a page of memory.
12. An apparatus to interact with a memory integrated circuit characterized by a row decoder cycle time, the apparatus comprising: a command interface to convey read commands to the memory integrated circuit; and a data interface to receive data from the memory integrated circuit via a data interconnect responsive to the read commands, the data interconnect characterized by a data width corresponding to a maximum number of bits that can be concurrently received via respective data lines of the data interconnect; wherein the apparatus has two operational modes, including a first operational mode in which the apparatus is to issue via the command interface a first read command to access a single column of an open row of the memory integrated circuit during the row decoder cycle time, and in which the data interface is to receive read data responsive to the first read command at the data width from the data interconnect, and a second operational mode in which the apparatus is to issue via the command interface a second read command to access two columns of the open row of the memory integrated circuit within the row decoder cycle time, using respective column addresses that can be selectively offset relative to one another, and in which the data interface is to receive read data responsive to the second read command at the data width from the data interconnect.
13. The apparatus of claim 12, embodied as at least one of a memory controller or a graphics controller.
14. The apparatus of claim 12, wherein: the command interface and the data interface are embodied as a dynamic random access memory (DRAM) controller integrated circuit; the memory integrated circuit comprises a DRAM integrated circuit; and the apparatus is further embodied as a module comprising the DRAM controller integrate circuit and the DRAM integrated circuit, wherein DRAM controller integrated circuit is operable to issue activate and precharge commands in association with each of the first read command and the second read command.
15. The apparatus of claim 12, wherein during the second operational mode, the data interface is operable to receive the data as respective columns of data corresponding to the respective column addresses in a manner where each column of data is received using the data width and where the apparatus is to receive the respective columns of data are received at different times from the data interconnect.
16. The apparatus of claim 12, wherein, during the second operational mode, the data interface is operable to concurrently receive respective columns of data corresponding to the respective column addresses, each in a manner corresponding to a respective half of the data width.
17. The apparatus of claim 12, wherein the apparatus comprises circuitry to generate the second read command as a command packet having two fields adapted to each carry a different one of the respective column addresses.
18. The apparatus of claim 12, adapted for use where the memory integrated circuit comprises multiple banks, wherein the apparatus is to issue each of the read commands in a manner that contains a bank address field to select one of the multiple banks.
19. A controller for a memory integrated circuit characterized by a row decoder cycle time, the controller comprising: a command interface; means for issuing read commands to the memory integrated circuit for performance during the row decoder cycle time, including a first read command to access a single column of an open row of the memory integrated circuit during the row decoder cycle time, and a second read command to access two columns of the open row of the memory integrated circuit during the row decoder cycle time, using respective column addresses that can be selectively offset relative to one another; and means for receiving read data from the memory integrated circuit responsive to the first read command and the second read command each at a maximum data width of a data interconnect in terms of bits that can be concurrently received via respective data lines.
20. The controller of claim 19, embodied as a dynamic random access memory (DRAM) controller, wherein the memory integrated circuit is a DRAM integrated circuit, wherein the means for issuing read commands is operable to issue activate and precharge commands in association with each of the first read command and the second read command, and wherein the respective column addresses are directed to respective halves of a page of memory.
FIG. 1 illustrates a memory system 140 including an integrated circuit memory device 100 coupled to master device 130 by interconnects RQ and DQ. Integrated circuit memory device 100 includes N memory banks 101, in a memory core 100a, and an interface 100b.
Reading and writing to memory banks 101 are initiated by row decoder 122 and dual column decoder 123 in response to row and column addresses, respectively. A plurality of storage cells or referred to as row 112 (also referred to as a page) outputs a plurality of data (or set of data) to sense amplifiers 121 in response to a row address provided to row decoder 122 followed by a column address or column addresses provided to dual column decoder 123 on internal interconnect A. Memory device 100 includes an internal interconnect A for providing control and address signals for addressing a storage location in memory banks 101. Interconnect A is coupled to circuitry 105 for coupling interface 100b to core 100a. Pipeline register 102 is coupled to circuitry 105 and receiver 108. External interconnect RQ is coupled to receiver 108 and carries external control and address signals between interface 100b and master device 130. In an embodiment, interconnect RQ is a twelve signal line unidirectional control/address bus. Internal interconnect S, in an embodiment, is an internal bidirectional bus for providing read/write data signals between sense amplifiers 121 memory banks 101. Interconnect S is coupled to circuitry 106 and 107 for coupling interface 100b to core 100a. Pipeline registers 103 and 104 are coupled to circuitry 106 and 107, respectively. Transmitter 109 and receiver 110 are coupled to pipeline registers 103 and 104, respectively. An external interconnect DQ transfers external bidirectional read/write data signals and is coupled to transmitter 109 and receiver 110 as well as master device 130. In an embodiment, interconnect DQ is a sixteen signal line bidirectional data bus.
In an embodiment, interface 100b includes a plurality of conducting contacts, such as pins and/or balls, for coupling to interconnect RQ, interconnect DQ and one or more CLK lines. In an embodiment, interface 100b includes twelve pins for coupling to interconnect RQ and sixteen pins for coupling to interconnect DQ. As one of ordinary skill in the art would appreciate, more or less contacts may be provided in alternate embodiments.
FIGS. 5 and 6 illustrate a first time mapping 500 and second time mapping 600, respectively, from a page of the integrated circuit memory device 100 to an external interconnect DQ. FIG. 5 illustrates how page 502 of memory bank 501 can have a first half (or odd half of open page 502a) accessed responsive to a first column address value in a first column field CP[8:4] in a COL request packet 401 and a second half (or even half of open page 502b) accessed in response to a second address in a second column field C[8:4] in the same COL request packet 401 shown in FIG. 4. A COLM request packet 402 may likewise be used in an embodiment.
FIG. 5 illustrates how an interleaved 32 bytes per column cycle time tCC are output onto an interconnect DQ having 16 signal lines. A first 16 bits by 8 bits is obtained from an odd half of open page 502a and output on interconnect DQ and then a second 16 bits by 8 bits are obtained from an even half of open page 502b and output on interconnect DQ. In the embodiment illustrated by FIG. 5, a plurality of data is output from integrated circuit memory device 100 on interconnect DQ from interleaved odd and even halves of a page 502. Column granularity per column cycle time interval tCC is 128 bits or 16 bytes. Column granularity per time interval tRR is 512 bits or 64 bytes.
FIG. 6 illustrates how 32 bytes per column cycle time tCC from both halves of page 602 are simultaneously output on an interconnect DQ having 16 signal lines. A first 8 bits by 16 bits from an odd half of open page 602a and a second 8 bits by 16 bits from an even half of an open page 602b of open page 602 in memory bank 601 is output simultaneously on interconnect DQ in an alternate embodiment. Column granularity per column address remains the same at 128 bits or 16 bytes. Column granularity per column cycle time interval tCC is also 256 bits or 32 bytes in the embodiment illustrated by FIG. 6.
FIG. 4 illustrates formats of request packets 400-404, in particular request packets having two or more column addresses for accessing a page of an integrated circuit memory device 100. A request packet represents control and address signals, such as commands and column addresses, asserted by master device 130 on interconnect RQ to integrated circuit memory device 100 in an embodiment. Request packets consist of 24 bits or logical values that may be represented by voltage values provided on interconnect RQ (RQ0-RQ11 data signal lines) and sampled at interface 100b on two successive clock signal edges (indicated as “Even” and “Odd” in FIG. 4) in an embodiment. As one of ordinary skill in the art would appreciate, other request packets having different formats and/or sizes may be used in alternate embodiments.
FIG. 10 is timing diagram and bank content mapping 1000 illustrating a first mode of operation using a quad column addressing mode of the integrated circuit memory device 900 shown in FIG. 9. FIG. 10 illustrates request packets provided on a control interconnect RQ by master device 130 to output a plurality of data values on interconnects DQ-A and DQ-B from memory banks 901 and 903 as well as 902 and 904, respectively, in integrated circuit memory device 900. The timing of the request packets and subsequent data output on interconnects DQ-A and DQ-B is similar to the timing constraints described above in regard to FIG. 3. An ACT command ACT B0 is provided on interconnect RQ to activate banks B0 in memory banks 901 and 904. In an embodiment, a COL request packet B0a B0b and COL request packet B0c B0d is then asserted on interconnect RQ by master device 130. In an embodiment, COL request packet B0a B0b and COL request packet B0a B0d are in a request format similar to a request packet 401 shown in FIG. 4. Fields C[8:4] contain a first column address for accessing data B0a and fields CP[8:4] contain a second column address for accessing data B0b in page 1010 in banks B0 of memory banks 901 and 904, respectively. Likewise in the second COL request packet B0c B0d, fields C[8:4] contains a first column address for accessing data B0c and fields CP[8:4] contains a second column address for accessing data B0d in page 1010 in banks B0 of memory banks 901 and 904, respectively. A PRE command PRE B0 is then provided on interconnect RQ by master device 130 and directed to banks B0 in memory banks 901 and 904. In an embodiment, data B0a (128 bits or 8 bits by 16 bits of data) is output on interconnect DQ-A during column cycle time interval tCC. Likewise, data B0b is output on interconnect DQ-B. During a next column cycle time intervals tCC, data B0c and B0d is output from integrated circuit memory device 900 on interconnects DQ-A and DQ-B, respectively. The operation may then be repeated for memory banks B1, B2, B3, B4, B5, B6 and B7 in memory banks 901 and 903 as well as 902 and 904. It should be noted that there is no restriction on accessing memory banks in a particular order in an embodiment illustrated by FIG. 10.
FIG. 11 is timing diagram and memory bank content mapping 1100 illustrating a second mode of operation using a quad column addressing mode of the integrated circuit memory device 900 shown in FIG. 9. In an embodiment illustrated by FIG. 11, an integrated circuit memory device 100 is operating at approximately 250 MHz (1/tCC). It is typically more difficult to provide enough data to an interface 100b with low access granularity unless multi-column addressing is used as described herein. In alternate embodiments, an integrated circuit memory device 100 is operating at a relatively faster approximate 500 MHz. FIG. 11, like FIG. 10, illustrates request packets asserted on a control interconnect RQ by master device 130 to output a plurality of data values on interconnects DQ-A and DQ-B from memory banks 901-904 in integrated circuit memory device 900. The timing of the request packets and subsequent data output on interconnects DQ-A and DQ-B is similar to the timing constraints described above in regard to FIG. 3. ACT commands ACT B0 and ACT B1 are asserted on interconnect RQ to activate memory banks B0 and B1 in memory banks 901-904. In an embodiment, four COL request packets B0a B0b, B1a B1b, B0c B0d, and B1c B1d are then asserted on interconnect RQ by master device 130. In an embodiment, COL request packets B0a B0b, B1a B1b, B0c B0d, and B1c B1d are in a request format similar to request packet formats 801 and 802 shown in FIG. 4. Fields CP[8:4], C[8:4] and a SEL value contain column address values for independently accessing four columns of page 1110 in memory banks B0 of memory banks 901 and 904 and page 1120 of banks B1 of memory banks 902 and 903. In particular, the first COL request packet B0a B0b contains the column address for accessing data B0a and B0b in the page 1110 in memory banks B0; the second COLM request packet B1a B1b contains the column address for accessing data B1a and B1b in page 1120; the third COLM request packet B0c B0d contains the column address for accessing data B0c and B0d in page 1110; and the fourth COLM request packet B1c B1d contains the column address for accessing data B1c and B1d in page 1120. In an embodiment, PRE commands PRE B0 and PRE B1 are then asserted on interconnect RQ by master device 130 and directed to memory banks B0 and B1. In an embodiment, data B0a (128 bits or 8 bits by 16 bits of data) is output on interconnect DQ-A during column cycle time interval tCC. Likewise, data B0b is output on interconnect DQ-B. During a next column cycle time interval tCC, data B1a and B1b is output from integrated circuit memory device 900 on interconnects DQ-A and DQ-B, respectively. During a next column cycle time interval tCC, data B0c and B0d is output from integrated circuit memory device 900 on interconnects DQ-A and DQ-B, respectively. Also, during a next column cycle time interval tCC, data B1c and B1d is output from integrated circuit memory device 900 on interconnects DQ-A and DQ-B, respectively. It should be noted that data output from odd and even pairs of memory banks are paired to avoid conflicts.
1. An integrated circuit memory device, comprising: an interface;
a second column decoder to access the second row of storage cells, wherein the integrated circuit memory device is operable in a first mode and a second mode,
a fourth column decoder to access the fourth row of storage cells, wherein the
integrated circuit memory device is operable in a first mode and second mode of operation, wherein:
a column decoder to access the first row of storage cells, wherein the integrated
circuit memory device is operable in a first mode and second mode of operation, wherein:
generating the first column address by a master device; and generating the second column address by the master device.
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