Source: http://www.google.com/patents/US8149928?dq=%22robert+sheehan%22
Timestamp: 2015-02-02 00:26:05
Document Index: 118914869

Matched Legal Cases: ['Application No. 200480021224', 'Application No. 200480021224', 'Application No. 2006', 'Application No. 10', 'Application No. 200480021320', 'Application No. 04756759', 'Application No. 04777713', 'Application No. 04777713', 'Application No. 04777713', 'Application No. 2006', 'Application No. 0600306', 'Application No. 0600306']

Patent US8149928 - Receivers for cycle encoded signals - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsSome embodiments include a transmitter having a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the...http://www.google.com/patents/US8149928?utm_source=gb-gplus-sharePatent US8149928 - Receivers for cycle encoded signalsAdvanced Patent SearchPublication numberUS8149928 B2Publication typeGrantApplication numberUS 12/782,120Publication dateApr 3, 2012Filing dateMay 18, 2010Priority dateJul 23, 2003Also published asCN1826783A, CN100593310C, EP1647119A2, EP1647119B1, US7305023, US7720159, US20050018779, US20080101505, US20100226419, WO2005011225A2, WO2005011225A3Publication number12782120, 782120, US 8149928 B2, US 8149928B2, US-B2-8149928, US8149928 B2, US8149928B2InventorsJed D. Griffin, Jerry G. Jex, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu KollaOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (43), Non-Patent Citations (32), Referenced by (1), Classifications (15), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetReceivers for cycle encoded signalsUS 8149928 B2Abstract Some embodiments include a transmitter having a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.
The invention claimed is: 1. A chip comprising:
wherein the receiver comprises an initial receiving circuit to receive the full cycle encoded signal and provide a received signal in response thereto, and a logic circuit to provide another data output signal which recovers data from another cycle encoded signal.
2. The chip of claim 1, wherein:
within some of the data time segments at least one cycle of the full cycle encoded signal is an inverse of other cycles of the full cycle encoded signal within others of the data time segments; and
within some of the data time segments at least one cycle of the full cycle encoded signal constitutes one cycle and within others of the data time segments at least one cycle of the full cycle encoded signal constitutes a half cycle.
3. The chip of claim 1, wherein the receiver further receives a complementary full cycle encoded signal and wherein the receiver provides the data output signal responsive to the full cycle encoded signal and the complementary full cycle encoded signal.
4. The chip of claim 3, wherein the receiver comprises the initial receiving circuit to compare the full cycle encoded signal and the complementary full cycle encoded signal to provide the received signal in response thereto and the logic circuit to provide the data output signal.
5. The chip of claim 4, wherein the logic circuit also provides an inverse of the data output signal.
7. The chip of claim 4, wherein the logic circuit includes an exclusive-OR gate to receive at least two delayed signals and first and second flip-flips to receive an output of the exclusive-OR gate and to receive the received signal at clock inputs of the first and second flip-flops, wherein the first flip-flop is clocked on a rising edge and the second flip-flop is clocked on a falling edge.
8. A chip comprising:
a receiver to receive a cycle encoded signal in which data is represented in data time segments, wherein each data time segment represents a cycle and at least some data time segments do not have more than one cycle, and provide a data output signal responsive to the cycle encoded signal,
wherein the receiver comprises an initial receiving circuit to receive the cycle encoded signal and provide a received signal in response thereto, and a logic circuit to provide another data output signal which recovers data from another cycle encoded signal.
9. The chip of claim 8, wherein the cycle encoded signal is a full cycle encoded signal in which no data time segment has more than one cycle.
10. The chip of claim 9, wherein:
11. The chip of claim 8, wherein the logic circuit also, provides an inverse of the data output signal.
12. The chip of claim 8, wherein the logic circuit responds to changes the received signal at the beginning of a data time segment, but not to mid-data time segment changes in the received signal.
(a) a cycle encoding circuit to receive a data input signal and provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals, wherein some of the different encoding signals have a different frequency than others of the different encoding signals and some of the different encoding signals have a different phase than others of the different encoding signals; and
(b) a complementary cycle encoding circuit to receive the data input signal and provide a complementary full cycle encoded signal in response thereto by continuously joining portions of the different encoding signals; and
a receiver to receive the full cycle encoded signal and the complementary full cycle encoded signal and recover values of the data input signal in response thereto, wherein the receiver includes an initial receiving circuit to compare the full cycle encoded signal and the complementary full cycle encoded signal to provide a received signal in response thereto, and a logic circuit to provide a data output signal which represents the recovered values,
wherein the initial receiving circuit receives the full cycle encoded signal and provides the received signal in response thereto, and the logic circuit provides another data output signal which recovers data from the complementary full cycle encoded signal.
14. The system of claim 13, wherein the different encoding signals include a first encoding signal with frequency F, a second encoding signal that is an inverse of the first encoding signal, a third encoding signal that has a frequency F/2, and a fourth encoding signal that is an inverse of the third encoding signal.
15. The system of claim 13, wherein the full cycle encoded signal in which no data time segment has more than one cycle.
16. The system of claim 13, wherein the logic circuit responds to changes of the received signal at the beginning of a data time segment, but not to a mid-data time segment changes in the received signal.
17. The system of claim 13, wherein the logic circuit includes an exclusive-OR gate to receive at least two delayed signals and first and second flip-flips to receive an output of the exclusive-OR gate and receive the received signal at clock inputs of the first and second flip-flops, wherein the first flip-flop is clocked on a rising edge and the second flip-flop is clocked on a falling edge.
18. The system of claim 13, further comprising a synchronizing circuit to synchronize the data and another data output signals to a second periodic signal and wherein the synchronizing circuit includes a periodic signal deriving circuit to provide a first periodic signal in response to the full and complementary full cycle encoded signals and wherein the first periodic signal is used in synchronizing. Description
RELATED APPLICATION This application claims priority from and is a continuation of U.S. patent application Ser. No. 11/925,474 filed Oct. 26, 2007, now U.S. Pat. No. 7,720,159, which is a continuation of application Ser. No. 10/625,944, filed Jul. 23, 2003, now U.S. Pat. No. 7,305,023. These applications are incorporated herein by reference for all purposes.
TECHNICAL FIELD Some embodiments relate to receivers for cycle encoded signals and to related systems.
BACKGROUND Inter symbol interference (ISI) degrades signal integrity through superimposition of pulses at varying frequencies. Data patterns with high frequency pulses are susceptible to ISI. Higher frequency pulses may phase shift more and attenuate more relative to lower frequency pulses leading to loss of the higher frequency pulses when superimposed with lower frequency pulses. The distortion to data patterns caused by ISI may lead to errors. The frequency at which uncompensated random data patterns in conventional signaling can be transmitted may be limited by ISI.
BRIEF DESCRIPTION OF THE DRAWINGS The inventions will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the inventions which, however, should not be taken to limit the inventions to the specific embodiments described and shown, but are for explanation and understanding only.
DETAILED DESCRIPTION A. Overview The inventions described herein include a system having a transmitter that encodes a data signal into a cycle encoded signal (CES). A CES is made of portions of different periodic encoding signals which are continuously joined, wherein data is represented by the encoding signals in data time segments of the cycle encoded signal. Some of the encoding signals have a different frequency and/or phase than others of the encoding signals. In a CES, at least some of the data time segments do not include more than one cycle of a particular encoding signal. In a full CES, no data time segment has more than one cycle of an encoding signal. In a partial CES, some data time segments have more than one cycle of an encoding signal, and other data time segments do not have more than one cycle of an encoding signal. The CES's described in connection with FIGS. 4, 5, 7, 10, 11, 12, and 13 are full CES's. In the CES's described in connection with FIGS. 4, 5, 7, 10, 11, 12, and 13, there is only one encoding signal per data time segment. In other embodiments, one encoding signal may be used in part of a data time segment, while another encoding signal may be used in the remainder of the data time segment.
C. Transmitters, Receivers, and Synchronizer Circuits of FIGS. 4-9. 1. Transmitter of FIGS. 4-6.
The CES in FIG. 5 illustrates the meaning of the term �cycle� in a data time segment. For example, in data time segments 3, 4, 6, and 8, there is one cycle. In data time segments 1, 2, 5, and 7, there is a half cycle, which is less than one cycle. If the SF had twice the frequency shown in FIG. 5 and was passed by MUX 156, then there would be two cycles in a data time segment.
Delay circuit 184 delays RS by about � of a data time segment (� T delay signal) and by about � of a data time segment (� T delay signal). Delay circuit 184 may be made of a delay chain or DLL. Delay circuit 184 may also provide a delay of one data time segment to provide a 1 T delay signal, but this is not required for all embodiments. The 1 T delay signal may be used in the optional additional circuit such as in FIG. 8.
The outputs of delay circuit 184 are provided to XOR gate 190. Table 1 below shows the truth table for XOR gate 190 and compares it to the value represented by CES and CCES. The input to XOR 190 is the same as the output of delay circuit 184. As can be seen, in this particular example, when the value represented by CES and CCES is 0, the output of XOR gate 190 is 0; and when the value represented by CES and CCES is 1, the output of XOR gate 190 is 1. This is arbitrary and the opposite voltages could correspond to 0 and 1.
� T Delay
FIG. 7 shows an example of RS (output of initial receiving circuit 182), the � T delay and � T delay signals from delay circuit 184, the output of XOR gate 190, the Q1 and Q2 outputs of flip-flops 196 and 198, and the output of AND gate 202 for data time segments 1+, 2+, 3+, 4+, 5+, and 6+. Data time segments 1+-6+ correspond to data time segments 1-6 in FIG. 5 but are slightly delayed in time through driver 122, interconnect 24A, and initial receiving circuit 182. FIG. 7 follows the convention that a �0� represents a low voltage and a �1� represents a high voltage. The opposite convention could be used. Flip-flops 196 and 198 are in the reset condition (Q1 and Q2 are both 0) at time t0.
At time t1, when RS has a falling edge, the � T delay and � T delay are both 1 so XOR 190 outputs a 0. The falling edge of RS causes flip-flip 198 to output as Q2 what is at its D input, which is a 0. Q1 continues to be 0. Accordingly, the output of AND gate 202 is a 0.
At time t2, when RS has a rising edge, the � T delay and � T delay are both 0 so XOR 190 outputs a 0. The rising edge of RS causes flip-flip 196 to output as Q1 what is at its D input, which is a 0. Q2 continues to be 0. Accordingly, the output of AND gate 202 is a 0.
At time t2.5, when RS has a falling edge, the � T delay is 1 and the � T delay is 0 so XOR 190 outputs a 1. The falling edge of RS causes flip-flip 198 to output as Q2 what is at its D input, which is a 1. Q1 continues to be 0. Accordingly, the output of AND gate 202 continues to be a 0 even though there was a transition of RS at time t2.5.
At time t3, when RS has a rising edge, the � T delay is 0 and � T delay is 1 so XOR 190 outputs a 1. The rising edge of RS causes flip-flip 196 to output as Q1 what is at its D input, which is a 1. Q2 continues to be 1. Accordingly, the Output Data from AND gate 202 changes to a 1 shortly following time t3. The amount of time between the transition in RS at t3 and the change of the Output Data depends on delays between flip-flops 196 and 198 and AND gate 202. Note that the signals of FIG. 7 are not necessarily to scale. Indeed, the delay between a change in the change in the RS signal and the change in data out signal may be somewhat smaller than is shown in FIG. 7.
At time t3.5, when RS has a falling edge, the � T delay is 1 and the � T delay is 0 so XOR 190 outputs a 1. The falling edge of RS causes flip-flip 198 to output as Q2 what is at its D input, which is a 1. Q1 continues to be 1. Accordingly, the output of AND gate 202 continues to be a 1 even though there was a transition of RS.
At time t4, when RS has a rising edge, the � T delay is 0 and � T delay is 1 so XOR 190 outputs a 1. The rising edge of RS causes flip-flip 196 to output as Q1 what is at its D input, which is a 1. Q2 continues to be 1. Accordingly, the output of AND gate 202 continues to be a 1.
At time t5, when RS has a falling edge, the � T delay is 1 and the � T delay is 1 so XOR 190 outputs a 0. The falling edge of RS causes flip-flip 198 to output as Q2 what is at its D input, which is a 0. Q1 continues to be 1. Accordingly, the output of AND gate 202 changes to a 0.
At time t5.5, when RS has a rising edge, the � T delay is 0 and � T delay is 1 so XOR 190 outputs a 1. The rising edge of RS causes flip-flip 196 to output as Q1 what is at its D input, which is a 1. Q2 continues to be 0. Accordingly, the output of AND gate 202 continues to be a 0 even though there was a transition of RS.
At time t6, when RS has a falling edge, the � T delay is 1 and the � T delay is 0 so XOR 190 outputs a 1. The falling edge of RS causes flip-flip 198 to output as Q2 what is at its D input, which is a 1. Q1 continues to be 1. Accordingly, the output of AND gate 202 changes to a 1.
In summary, for the receiver of FIG. 4, the output of initial receiving circuit 182 is delayed such that a sample is taken of the received signal in each of two halves of the data time segment. In the case of FIG. 4, the delays are by amounts of � and �, but in other embodiments, delays by other amounts could be made. Further, in other embodiments, more than two delays may be made.
D. Receivers of FIGS. 10-11. FIG. 10 shows other embodiments of receivers 28 and 104. Referring to FIG. 10, initial receiving circuit 318 (which may be the same as circuit 182 in FIG. 4) receives CES and CCES and produces a received signal RS in response thereto. Delay circuit 320 provides a 1 T delay signal, a � delay signal, and a � delay signal. An XOR gate 332 provides a signal to flip-flops 336 and 338 in response to the � and � delay signals. A NOR gate 326 provides a signal rising (SR) signal in response to an output (Q2) of flip-flop 338 and an inverted 1 T delay signal through inverter 324. An OR gate 330 provides a signal falling (SF) signal in response to an output (Q1) of flip-flop 336 and the 1 T delay signal. A state machine in the form of an AND gate 342 and an OR gate 344 provides an output control signal. AND gate 342 receives the SF signal and the fedback output control signal. OR gate 344 provides the output control signal in response to the output of AND gate 342 and the SR signal. MUXs 352 and 354 are controlled by the output control signal. MUX 352 receives the Q1 and Q2 signals and provides the data out signal. MUX 352 receives inverted Q1 and Q2 signals (through inverters 346 and 348) and provides the data out* signal. In some embodiments, there is only MUX 352 or only MUX 354.
At time t6.5, the 1 T delay signal is rising and Q2 is 1 so that SR stays 0. As mentioned, this blocks flip-flop 336 from clocking Since Q1 is 0 and the 1 T delay signal is 1, SF changes to 1 and flip-flop 338 does not clock. Therefore, Q1 and Q2 remain 0 and 1, respectively. Since the output control signal was 0 and SR is 0, the output control signal remains 0 even though SF is 1. Accordingly, MUXs 352 and 354 continue to pass Q2 and Q2*, respectively.
E. Additional Embodiments and Information The inventions are not limited to use with complementary signals CES and CCES. For example, FIG. 12 shows a transmitter 384 (which is an example of transmitter 20 of FIG. 1) with cycle encoding circuit 152, but not complementary cycle encoding circuit 154 so that the CES but not the CCES is produced. Receiver 388 (which is an example of receiver 28 in FIG. 1) includes an initial receiving circuit 392, which may be a comparator, and which compares the CES to a reference signal Vref. As an example, Vref might be between a high and low voltage for the CES. To show different possibilities, in FIG. 12, a DLL 382 provides a periodic reference signal rather than a PLL as in FIG. 4.
The inventions are not limited to use with only a 0 or 1 being represented. For example, FIG. 13 illustrates a CES that can represent 0, 1, or 2. The choice of which encoding signal SF, SF*, SF/2, SF/2*, SF/4, and SF/4* that represents 0, 1, and 2 is arbitrary. The signals of FIG. 13 can be created by adding additional circuits to those of circuits 162-168 and 172-178. A receiver could take samples at additional locations through for example, additional delays. Also, the logic would be more complicated logic than shown in FIG. 4 or 10. More circuits could be added to provide SF/8 and SF/8* to represent 0, 1, 2, and 3. The encoding signals do not have to be at divisions of two of the maximum frequency. For example, in some embodiments, the encoding signals might include those with ⅔ or � of the maximum frequency.
The term �responsive� means that one thing or event at least partially causes another thing or event, although there may be other causes for the thing or event. Two circuits may be coupled directly or coupled indirectly through an intermediate circuit.
An embodiment is an implementation or example of the inventions. Reference in the specification to �an embodiment,� �one embodiment,� �some embodiments,� or �other embodiments� means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances �an embodiment,� �one embodiment,� or �some embodiments� are not necessarily all referring to the same embodiments.
If the specification states a chip, feature, structure, or characteristic �may�, �might�, or �could� be included, that particular chip, feature, structure, or characteristic is not required to be included. If the specification or claim refers to �a� or �an� element, that does not mean there is only one of the element. If the specification or claims refer to �an additional� element, that does not preclude there being more than one of the additional element.
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No. 11/925,474, mailed on Mar. 10, 2010, 2 pages.32Written Opinion received for Singapore Patent Application No. 0600306-5, mailed on May 15, 2008, 7 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8559530Oct 26, 2007Oct 15, 2013Intel CorporationTransmitters providing cycle encoded signalsClassifications U.S. Classification375/244, 375/364, 375/242International ClassificationH04B14/06, H04L1/06, H04L27/24, H04L25/49, H04L7/06, H04B14/04Cooperative ClassificationH04L25/4904, H04L1/06, H04L27/24European ClassificationH04L27/24, H04L25/49C, H04L1/06Legal EventsDateCodeEventDescriptionJun 12, 2012CCCertificate of correctionRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services