Source: http://www.google.com/patents/US8053909?dq=5251294
Timestamp: 2014-12-27 10:57:56
Document Index: 190784635

Matched Legal Cases: ['Application No. 07749404', 'Application No. 10', 'Application No. 10', 'Application No. 2009', 'Application No. 2008', 'Application No. 2008', 'Application No. 2008']

Patent US8053909 - Semiconductor component having through wire interconnect with compressed bump - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side,...http://www.google.com/patents/US8053909?utm_source=gb-gplus-sharePatent US8053909 - Semiconductor component having through wire interconnect with compressed bumpAdvanced Patent SearchPublication numberUS8053909 B2Publication typeGrantApplication numberUS 13/007,743Publication dateNov 8, 2011Filing dateJan 17, 2011Priority dateApr 8, 2005Also published asEP1872387A2, EP1872387A4, US7371676, US7682962, US7728443, US7757385, US7919846, US20060228825, US20070200255, US20070202617, US20070222054, US20100140753, US20110108959, WO2006110266A2, WO2006110266A3Publication number007743, 13007743, US 8053909 B2, US 8053909B2, US-B2-8053909, US8053909 B2, US8053909B2InventorsDavid R. HembreeOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (101), Non-Patent Citations (61), Classifications (98), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor component having through wire interconnect with compressed bumpUS 8053909 B2Abstract A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3761782May 19, 1971Sep 25, 1973Signetics CorpSemiconductor structure, assembly and methodUS4348253Nov 12, 1981Sep 7, 1982Rca CorporationMethod for fabricating via holes in a semiconductor waferUS4394712Mar 18, 1981Jul 19, 1983General Electric CompanyAlignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafersUS4710795Feb 25, 1985Dec 1, 1987Brown, Boveri & Cie AktiengesellschaftSemiconductor power moduleUS4807021Mar 5, 1987Feb 21, 1989Kabushiki Kaisha ToshibaSemiconductor device having stacking structureUS4808273May 10, 1988Feb 28, 1989Avantek, Inc.Electroplating interior surfaces of apertures; using conductive pads as cathodesUS4897708Jul 17, 1986Jan 30, 1990Laser Dynamics, Inc.Semiconductor wafer arrayUS5229647Sep 21, 1992Jul 20, 1993Micron Technology, Inc.High density data storage using stacked wafersUS5432999Mar 21, 1994Jul 18, 1995Capps; David F.Integrated circuit lamination processUS5483741Nov 7, 1994Jan 16, 1996Micron Technology, Inc.Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor diceUS5495667Nov 7, 1994Mar 5, 1996Micron Technology, Inc.Method for forming contact pins for semiconductor dice and interconnectsUS5496775Apr 8, 1994Mar 5, 1996Micron Semiconductor, Inc.Tower, integrated circuitUS5503285Jul 26, 1993Apr 2, 1996Litton Systems, Inc.Method for forming an electrostatically force balanced silicon accelerometerUS5519332Mar 1, 1995May 21, 1996Micron Technology, Inc.Carrier for testing an unpackaged semiconductor dieUS5649981Sep 23, 1996Jul 22, 1997Texas Instruments IncorporatedTool and fixture for the removal of tab leads bonded to semiconductor die padsUS5674785Nov 27, 1995Oct 7, 1997Micron Technology, Inc.Forming wire electroconnection between the patterned pads and patterned conductor through the opening; materials handling; packagingUS5686352Jul 31, 1995Nov 11, 1997Motorola Inc.Method for making a tab semiconductor device with self-aligning cavity and intrinsic standoffUS5739585Jul 29, 1996Apr 14, 1998Micron Technology, Inc.Single piece package for semiconductor dieUS5793103May 8, 1997Aug 11, 1998International Business Machines CorporationInsulated cube with exposed wire leadUS5814889Jun 5, 1995Sep 29, 1998Harris CorporationIntergrated circuit with coaxial isolation and methodUS5824569Mar 5, 1996Oct 20, 1998Micron Technology, Inc.Semiconductor device having ball-bonded padsUS5840199Apr 8, 1997Nov 24, 1998Litton Systems, Inc.Method for purging a multi-layer sacrificial etched silicon substrateUS5852871Dec 11, 1995Dec 29, 1998Form Factor, Inc.Method of making raised contacts on electronic componentsUS5866949Oct 8, 1997Feb 2, 1999Minnesota Mining And Manufacturing CompanyChip scale ball grid array for integrated circuit packagingUS5894983Jan 9, 1997Apr 20, 1999Harris CorporationHigh frequency, low temperature thermosonic ribbon bonding process for system-level applicationsUS5931685Jun 2, 1997Aug 3, 1999Micron Technology, Inc.Interconnect for making temporary electrical connections with bumped semiconductor componentsUS5950070May 15, 1997Sep 7, 1999Kulicke & Soffa InvestmentsMethod of forming a chip scale package, and a tool used in forming the chip scale packageUS5990546Dec 29, 1995Nov 23, 1999Nitto Denko CorporationChip scale package type of semiconductor deviceUS6002177Dec 27, 1995Dec 14, 1999International Business Machines CorporationHigh density integrated circuit packaging with chip stacking and via interconnectionsUS6033614Aug 24, 1998Mar 7, 2000Micron Technology, Inc.Encapsulating electronic elements in a plastic material.US6040702Jul 3, 1997Mar 21, 2000Micron Technology, Inc.Carrier and system for testing bumped semiconductor componentsUS6043564Oct 20, 1998Mar 28, 2000Micron Technology, Inc.Semiconductor device having ball-bonded padsUS6100175Aug 28, 1998Aug 8, 2000Micron Technology, Inc.Method and apparatus for aligning and attaching balls to a substrateUS6107109Dec 18, 1997Aug 22, 2000Micron Technology, Inc.Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrateUS6114240Feb 12, 1999Sep 5, 2000Micron Technology, Inc.Method for fabricating semiconductor components using focused laser beamUS6184587Oct 21, 1996Feb 6, 2001Formfactor, Inc.Resilient contact structures, electronic interconnection component, and method of mounting resilient contact structures to electronic componentsUS6187678Aug 24, 1999Feb 13, 2001International Business Machines CorporationHigh density integrated circuit packaging with chip stacking and via interconnectionsUS6235554May 24, 1999May 22, 2001Micron Technology, Inc.Method for fabricating stackable chip scale semiconductor packageUS6236115Jul 29, 1999May 22, 2001International Business Machines CorporationHigh density integrated circuit packaging with chip stacking and via interconnectionsUS6251703Dec 13, 1999Jun 26, 2001Ela Medical S.A.CMS coated microelectronic component and its method of manufactureUS6252298May 19, 1998Jun 26, 2001Samsung Electronics Co., Ltd.Semiconductor chip package using flexible circuit board with central openingUS6253992Mar 17, 1999Jul 3, 2001Tessera, Inc.Solder ball placement fixtures and methodsUS6294837Aug 30, 1999Sep 25, 2001Micron Technology, Inc.Semiconductor interconnect having laser machined contactsUS6316287Sep 13, 1999Nov 13, 2001Vishay Intertechnology, Inc.Chip scale surface mount packages for semiconductor device and process of fabricating the sameUS6326689Jul 26, 1999Dec 4, 2001Stmicroelectronics, Inc.Backside contact for touchchipUS6332569May 24, 2000Dec 25, 2001International Business Machines CorporationEtched glass solder bump transfer for flip chip integrated circuit devicesUS6336269May 26, 1995Jan 8, 2002Benjamin N. EldridgeMethod of fabricating an interconnection elementUS6339260Sep 13, 1999Jan 15, 2002Hyundai Electronics Industries Co., Ltd.Wire arrayed chip size packageUS6368896Apr 23, 1999Apr 9, 2002Micron Technology, Inc.Method of wafer level chip scale packagingUS6380555Dec 24, 1999Apr 30, 2002Micron Technology, Inc.Bumped semiconductor component having test pads, and method and system for testing bumped semiconductor componentsUS6395581Jul 10, 2000May 28, 2002Hyundai Electronics Industries Co., Ltd.BGA semiconductor package improving solder joint reliability and fabrication method thereofUS6400172Dec 30, 1999Jun 4, 2002Micron Technology, Inc.Semiconductor components having lasered machined conductive viasUS6435200Apr 24, 2000Aug 20, 2002Sez Semiconductor-Equipment Zubehor Fur Die Halbleiterfertigung AgDevice and process for liquid treatment of wafer-shaped articlesUS6437254Aug 24, 2001Aug 20, 2002International Business Machines CorporationApparatus and method for printed circuit board repairUS6444576Jun 16, 2000Sep 3, 2002Chartered Semiconductor Manufacturing, Ltd.Three dimensional IC package moduleUS6451624Aug 7, 2001Sep 17, 2002Micron Technology, Inc.Stackable semiconductor package having conductive layer and insulating layers and method of fabricationUS6465877Mar 27, 2000Oct 15, 2002Micron Technology, Inc.Semiconductor package including flex circuit, interconnects and dense array external contactsUS6485814Feb 25, 2000Nov 26, 2002Fujitsu LimitedHigh density thin film circuit board and method of production thereofUS6494221Nov 16, 1999Dec 17, 2002Sez AgDevice for wet etching an edge of a semiconductor diskUS6498074Jun 6, 2001Dec 24, 2002Tru-Si Technologies, Inc.Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and cornersUS6501165Jun 3, 2002Dec 31, 2002Micron Technology, Inc.Stackable semiconductor package having conductive layer and insulating layers and method of fabricationUS6528984Sep 12, 1997Mar 4, 2003Ibm CorporationIntegrated compliant probe for wafer level test and burn-inUS6566747Jul 16, 2001May 20, 2003Ars Electronics Co., Ltd.Semiconductor package and production method thereofUS6569762Jun 11, 2002May 27, 2003Chartered Semiconductor Manufacturing Ltd.Three dimensional IC package moduleUS6577013Sep 5, 2000Jun 10, 2003Amkor Technology, Inc.Chip size semiconductor packages with stacked diesUS6582992Aug 15, 2002Jun 24, 2003Micron Technology, Inc.Stackable semiconductor package and wafer level fabrication methodUS6600221Aug 29, 2001Jul 29, 2003Nec Electronics CorporationSemiconductor device with stacked semiconductor chipsUS6601888Mar 19, 2001Aug 5, 2003Creo Inc.Contactless handling of objectsUS6605551Dec 8, 2000Aug 12, 2003Intel CorporationElectrocoating process to form a dielectric layer in an organic substrate to reduce loop inductanceUS6608371Jul 11, 2001Aug 19, 2003Seiko Epson CorporationSimple electrical connection of miniature, stacked chipsUS6611052Nov 16, 2001Aug 26, 2003Micron Technology, Inc.Wafer level stackable semiconductor packageUS6614104Oct 4, 2002Sep 2, 2003Micron Technology, Inc.Stackable semiconductor package having conductive layer and insulating layersUS6620633Apr 13, 2001Sep 16, 2003Micron Technology, Inc.Method for testing bumped semiconductor componentsUS6620731Jan 4, 2002Sep 16, 2003Micron Technology, Inc.Method for fabricating semiconductor components and interconnects with contacts on opposing sidesUS6638847Apr 19, 2000Oct 28, 2003Advanced Interconnect Technology Ltd.Method of forming lead-free bump interconnectionsUS6653170Feb 6, 2001Nov 25, 2003Charles W. C. LinSemiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuitUS6680213Apr 2, 2001Jan 20, 2004Micron Technology, Inc.Method and system for fabricating contacts on semiconductor componentsUS6712261Mar 20, 2002Mar 30, 2004International Business Machines CorporationSolid conductive element insertion apparatusUS6717245Jun 2, 2000Apr 6, 2004Micron Technology, Inc.Chip scale packages performed by wafer level processingUS6720661Jun 1, 2001Apr 13, 2004Seiko Epson CorporationSemiconductor device, method of fabricating the same, stack-type semiconductor device, circuit board and electronic instrumentUS6724074Nov 6, 2002Apr 20, 2004Samsung Electronics Co., Ltd.Stack semiconductor chip package and lead frameUS6727116Jun 27, 2002Apr 27, 2004Micron Technology, Inc.Semiconductor devices including peripherally located bond pads, assemblies, packages, and methodsUS6731013Jun 5, 2001May 4, 2004Sharp Kabushiki KaishaWiring substrate, semiconductor device and package stack semiconductor deviceUS6740582Apr 26, 2002May 25, 2004Tru-Si Technologies, Inc.Integrated circuits and methods for their fabricationUS6740960Aug 29, 2002May 25, 2004Micron Technology, Inc.Semiconductor package including flex circuit, interconnects and dense array external contactsUS6740982Oct 30, 2001May 25, 2004Conti Temic Microelectronic GmbhMicroelectronic package with an attachment layer including spacer elementsUS6803303Jul 11, 2002Oct 12, 2004Micron Technology, Inc.Method of fabricating semiconductor component having encapsulated, bonded, interconnect contactsUS6812549Oct 21, 2002Nov 2, 2004Seiko Epson CorporationWiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrumentUS6824074Feb 18, 2003Nov 30, 2004Spraying Systems Co.Air assisted spray nozzle assembly for spraying viscous liquidsUS6828175Jun 10, 2003Dec 7, 2004Micron Technology, Inc.Semiconductor component with backside contacts and method of fabricationUS6831367Dec 19, 2002Dec 14, 2004Kabushiki Kaisha ToshibaSemiconductor device and method of manufacturing the sameUS6833317Feb 20, 2003Dec 21, 2004Micron Technology, Inc.High permeability composite films to reduce noise in high speed interconnectsUS6833612Jul 3, 2003Dec 21, 2004Micron Technology, Inc.Flip-chip image sensor packagesUS6833613Sep 25, 2001Dec 21, 2004Micron Technology, Inc.Stacked semiconductor package having laser machined contactsUS6841883Mar 31, 2003Jan 11, 2005Micron Technology, Inc.Multi-dice chip scale semiconductor components and wafer level methods of fabricationUS6846725 *Jan 27, 2003Jan 25, 2005Institute Of MicroelectronicsWafer-level package for micro-electro-mechanical systemsUS6848177Mar 28, 2002Feb 1, 2005Intel CorporationIntegrated circuit die and an electronic assembly having a three-dimensional interconnection schemeUS6858092Jun 10, 2002Feb 22, 2005Sez AgDevice and process for liquid treatment of wafer-shaped articlesUS6881648Mar 13, 2003Apr 19, 2005Motorola, Inc.Semiconductor wafer having a thin die and tethers and methods of making the sameUS6882057Sep 19, 2003Apr 19, 2005Via Technologies, Inc.Quad flat no-lead chip carrierUS20020117330 *Dec 28, 2001Aug 29, 2002Formfactor, Inc.Resilient contact structures formed and then attached to a substrate* Cited by examinerNon-Patent CitationsReference1Boschman web site, "Film Assisted Molding: Encapsulation processes for advanced and standard packages", date unavailable, pp. 1-3.2btechcorp, High Thermally and Electrically Conductive Z-Axis Film Adhesives, spec sheet, Mar. 22, 2006, pp. 1-2.3Dr. Ning-Cheng Lee, "The Use of Solder as an Area-Array Package Interconnect", Chip Scale Review, Sep.-Oct. 1999, pp. 1-8. Available on line: www:chipscalereview.com/issues/.4European Search Report from Application No. EP 06 73 9005 dated Jul. 23, 2010, pp. 1-11.5Extended European Search Report from European Patent Application No. 07749404.5 dated May 17, 2011, pp. 1-10.6George A. Riley, PhD., FLIPCHIPS dot.com. Tutorial 37, "Too much gold can be a bad thing", Mar. 24, 2005, pp. 1-3. Available on line: www.flip[chips.com/tutoria137.html.7IBM and SUSS announce semiconductor technology agreement, internet article, Sep. 13, 2004, pp. 1-2.8IBM Research & IBM Systems and Technology Group, C4NP Technology for lead-free wafer bumping, internet article, Sep. 2004, pp. 1-13.9Indium Corporation of America, Product Data sheet, "Pb-Free Solder Fabrication", pp. 1-2, date unavailable.10International Technology Roadmap for Semiconductors, 2005 Edition, Assembly and Packaging, pp. 1-50.11Ivy Wei Qin, PhD et al., "Automatic Wedge Bonding with Ribbon Wire for High Frequency Applications", Kulicke & Soffa, 2002 SEMICON� West 2002 SEMI� Technology Symposium: International Electronics Manufacturing Technology (IEMT) Symposium, pp. 1-11.12Korean Patent Application No. 10-2007-7026928, Notice of Preliminary Rejection (Non-Final), (English translation), Jul. 20, 2009, pp. 1-7.13Kulicke & Soffa, Dispense/UV/ Cure Kit for NOSWEEP(TM) , advertising, Mar. 15, 2005, pp. 1-2. Available on line:www.kns.com.14Kulicke & Soffa, Dispense/UV/ Cure Kit for NOSWEEP� , advertising, Mar. 15, 2005, pp. 1-2. Available on line:www.kns.com.15Leon Oboler, "Still at the Head of the Class", Chip Scale Review, internet article, Jul./Aug. 1999, pp. 1-7.16Notice of Allowance dated Aug. 3, 2007 from U.S. Appl. No. 11/296,057 (US Patent No. 7,307,348), pp. 1-6.17Notice of Allowance dated Jan. 7, 2008 from U.S. Appl. No. 11/102,408 (US Patent No. 7,371,676), pp. 1-9.18Notice of Allowance dated Mar. 5, 2008 from U.S. Appl. No. 11/133,085 (US Patent No. 7,393,770), pp. 1-8.19Notice of Allowance dated Sep. 28, 2009 from U.S. Appl. No. 11/409,638, pp. 1-8.20Notice of Allowance from U.S. Appl. No. 11/743,636 dated Nov. 17, 2009 (US Patent No. 7,682,962), pp. 1-9.21Notice of Allowance from U.S. Appl. No. 11/743,660 dated Jan. 26, 2010, pp. 1-6.22Notice of Allowance from U.S. Appl. No. 11/743,689 dated Mar. 22, 2010, pp. 1-4.23Notice of Allowance from U.S. Appl. No. 11/859,776 dated Apr. 3, 2010, pp. 1-7.24Notice of Allowance from U.S. Appl. No. 12/114,757 dated Jan. 5, 2011, pp. 1-7.25Notice of Allowance from U.S. Appl. No. 12/114,761 dated Apr. 9, 2010, pp. 1-7.26Notice of Allowance from U.S. Appl. No. 12/117,919 dated Jan. 26, 2010, pp. 1-7.27Notice of Allowance from U.S. Appl. No. 12/581,255 dated Sep. 29, 2010, pp. 1-17.28Notice of Allowance from U.S. Appl. No. 12/703,520 dated May 2, 2011, pp. 1-10.29Notice of Allowance from U.S. Appl. No. 12/703,551 dated Dec. 10, 2010, pp. 1-10.30Notice of Preliminary Rejection (Non-Final) dated Sep. 30, 2010 (English Translation from Korean Patent Application No. 10-2008-7028703, pp. 1-12.31Notice of Rejection Ground from Japanese Patent Application No. 2009-507675 dated May 25, 2011 (English translation), pp. 1-3.32Notice of Rejection Grounds from Japanese Patent Application No. 2008-505335 dated Sep. 8, 2010, pp. 1-5.33Notice of Rejection Grounds from Japanese Patent Application No. 2008-512322 dated Jan. 28, 2011, (English translation), pp. 1-2.34Notice of Rejection Grounds from Japanese Patent Application No. 2008-512322 dated Sep. 9, 2010, pp. 1-2.35Office Action dated Dec. 29, 2009 from U.S. Appl. No. 11/743,660, pp. 1-10.36Office Action dated Feb. 11, 2008 from U.S. Appl. No. 11/133,085 (US Patent No. 7,393,770), pp. 1-10.37Office Action dated Jul. 11, 2007 from U.S. Appl. No. 11/102,408 (US Patent No. 7,371,676). pp. 1-8.38Office Action dated Jul. 13, 2009 from U.S. Appl. No. 11/409,638, pp. 1-17.39Office Action dated Jun. 4, 2007 from U.S. Appl. No. 11/296,057 (US Patent No. 7,307,348, pp. 1-9.40Office Action dated Mar. 12, 2009 from U.S. Appl. No. 11/409,638, pp. 1-18.41Office Action dated Nov. 14, 2008 from U.S. Appl. No. 11/712,815 (US Patent No. 7,579,267), pp. 1-5.42Office Action dated Oct. 17, 2007 from U.S. Appl. No. 11/102,408 (US Patent No. 7,371,676), pp. 1-9.43Office Action dated Oct. 31, 2007 from U.S. Appl. No. 11/133,085 (US Patent No. 7,393,770), pp. 1-13.44Office Action from U.S. Appl. No. 11/743,636 dated Aug. 3, 2009, pp. 1-8.45Office Action from U.S. Appl. No. 11/743,660 dated Aug. 4, 2009, pp. 1-11.46Office Action from U.S. Appl. No. 11/743,689 dated Nov. 30, 2009 pp. 1-8.47Office Action from U.S. Appl. No. 11/859,776 dated Feb. 19, 2010, pp. 1-10.48Office Action from U.S. Appl. No. 12/114,757 dated Dec. 14, 2010, pp. 1-8.49Office Action from U.S. Appl. No. 12/114,757 dated Sep. 17, 2010, pp. 1-28.50Office Action from U.S. Appl. No. 12/114,761 dated Feb. 24, 2010, pp. 1-11.51Office Action from U.S. Appl. No. 12/114,761 dated Oct. 7, 2009, pp. 1-11.52Office Action from U.S. Appl. No. 12/117,919 dated Oct. 5, 2009, pp. 1-10.53Office Action from U.S. Appl. No. 12/703,520 dated Jul. 9, 2010, pp. 1-13.54Office Action from U.S. Appl. No. 12/703,520 dated Nov. 12, 2010, pp. 1-14.55Office Action from U.S. Appl. No. 12/703,551 dated Oct. 5, 2010, pp. 1-17.56PCT Search Report from International Application No. PCT/US2006//017036 dated May 2, 2007, pp. 1-6.57PCT Search Report from International Application No. PCT/US2006/010044 dated Aug. 29, 2007, pp. 1-8.58PCT Search Report from International Application No. PCT/US2007/002336 dated Feb. 13, 2008, pp. 1-8.59Renesas News Releases, "Hitachi and Renesas Technology Develop Through-Hole Electrode Technology to Enable Interconnection of Stacked Chips at Room Temperature", Tokyo, Jun. 1, 2005, pp. 1-2.60Supplementary European Search Report from Application No. EP 06 73 9005 dated Aug. 10, 2010, pp. 1-7.61U.S. Appl. No. 60/172,186, filed Dec. 17, 1999 titled Multi-Flip Chip Semiconductor Assembly,Inventors: Ruben Rolda, Jr. et al., pp. 1-25.Classifications U.S. Classification257/784, 438/617, 257/E23.023International ClassificationH01L23/49Cooperative ClassificationH01L2224/45565, H01L24/78, H01L23/49827, H01L2924/01084, H01L2225/06596, H01L2224/45147, H01L2224/85201, H01L2224/16, H01L21/76898, H01L2924/01013, H01L2924/01078, H05K3/4046, H01L2924/01012, H01L2924/01006, H01L2924/20751, H01L2924/01029, H01L2224/45164, H01L25/50, H01L24/85, H01L2924/20754, H01L2225/06541, H01L2924/01031, H01L2924/2076, H01L2924/01075, H01L2225/06562, H01L2924/20755, H01L2224/45015, H01L2924/20757, H01L2924/30105, H01L2924/20758, H01L2225/06506, H01L2924/01033, H01L2225/06589, H01L2224/9202, H01L2224/4813, H01L2224/85951, B23K20/004, H01L2924/01005, H01L2224/81815, H01L2924/014, H01L2224/45124, H01L2924/01014, H01L2224/85043, H01L2924/19041, H01L24/48, H05K2201/10287, H01L2224/48455, H01L2224/8121, H05K2203/049, H01L2924/0105, H01L25/0657, H01L2224/48145, H01L2224/4807, H01L2924/3025, H01L2224/78301, H01L2924/0102, H01L2924/20756, H01L2224/45144, H01L2224/45139, H01L2924/20753, H01L2924/20759, H01L2924/01047, H01L2224/48471, H01L2924/01028, H01L2924/12044, H01L2224/81224, H01L2924/01046, H01L23/481, H01L2224/85045, H01L24/45, H01L24/81, H01L2225/06527, H01L2924/01079, H01L2224/48091, H01L2924/01082, B23K20/005, H01L2924/10329, H01L2224/85205, H01L2224/48699, H01L2924/14, H01L2224/48599, H01L2224/48992European ClassificationH01L24/48, H01L24/85, H01L25/065S, H05K3/40D1, H01L21/768T, B23K20/00D2B, H01L23/48J, B23K20/00D2, H01L23/498E, H01L25/50, H01L24/81, H01L24/78Legal EventsDateCodeEventDescriptionJan 10, 2012CCCertificate of correctionRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google