Source: http://www.google.com/patents/US8073006?dq=5,867,764
Timestamp: 2014-10-25 13:55:57
Document Index: 135929557

Matched Legal Cases: ['Application No. 11', 'art 3', 'art 4', 'art 5', 'art 4', 'art 5', 'art 4', 'art 4', 'art 5', 'art 5', 'art 4', 'art 4', 'art 5', 'art 5', 'art 4']

Patent US8073006 - ATM cell conversion circuit and ATM cell conversion method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsSending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell...http://www.google.com/patents/US8073006?utm_source=gb-gplus-sharePatent US8073006 - ATM cell conversion circuit and ATM cell conversion methodAdvanced Patent SearchPublication numberUS8073006 B2Publication typeGrantApplication numberUS 11/170,789Publication dateDec 6, 2011Filing dateJun 30, 2005Priority dateMay 13, 1999Also published asUS6944182, US20060002396, US20120051367Publication number11170789, 170789, US 8073006 B2, US 8073006B2, US-B2-8073006, US8073006 B2, US8073006B2InventorsTatsuhiko Amagai, Yuichi SuzukiOriginal AssigneeJuniper Networks, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (20), Referenced by (1), Classifications (10) External Links: USPTO, USPTO Assignment, EspacenetATM cell conversion circuit and ATM cell conversion methodUS 8073006 B2Abstract Sending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell conversion request means for issuing an ATM cell conversion request is provided every output route, and the cell conversion processing of the frame is selected and performed in the order of higher sending priority every time one cell conversion.
CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 09/567,442 filed May 10, 2000, now U.S. Pat. No. 6,944,182, the disclosure of which is hereby incorporated herein by reference. The present invention claims priority from Japanese Patent Application No. 11-133384 filed May 13, 1999, the contents of which are incorporated herein by reference.
SUMMARY OF THE INVENTION The present invention is implemented in view of the above-mentioned problems, and it is an object of the invention to provide an ATM cell conversion circuit and an ATM cell conversion method in which in addition to a cell conversion method statically assigned every frame or output connection according to a quality class, priority of a frame for making cell conversion is dynamically changed in consideration of congestion states of plural stages every output route, a frame length to be sent or elapsed time of cell conversion processing, etc. and thereby, fine sending priority control can be performed and further ATM cell conversion processing and ATM cell output control with high efficiency can be performed, with the result that efficiency of buffer resources within an apparatus and network use can be more improved.
According to a first aspect of the present invention, there is provided an ATM cell conversion circuit comprising cell conversion means for processing cell conversion to convert data of a frame format (hereinafter simply called �frame�) into cells which are a transfer format in the asynchronous transfer mode (ATM) and outputting the converted cells to switch means for distributing sending cells every route for output to send out the cells to an ATM network; and cell conversion request means provided every output route for issuing a cell conversion request of a frame whose sending request has occurred to the cell conversion means, characterized in that the cell conversion means selects the next cell conversion request to process cell conversion of the corresponding frame every time cell conversion of the frame corresponding to one cell conversion request is processed by one cell.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows one embodiment of a cell conversion circuit of the present invention. A cell conversion circuit 1 comprises sending request queues 2, a queue readout control part 3, and a frame information storage part 4 independently every output route in order to make cell conversion processing of non-blocking, and comprises a cell division multiplex part 5 in the output side of the frame information storage part 4. A frame buffer 6 is connected to the cell division multiplex part 5. Frames trying to send are stored in the frame buffer 6 and information on the frames is stored in the frame information storage part 4 every the route.
The frame information storage part 4 issues a cell conversion request with information of the stored frame to the cell division multiplex part 5 when storage of the descriptor is completed. After the cell division multiplex part 5 receives the cell conversion request from the frame information storage part 4 to send out cells, information of a frame for storage is updated in the frame information storage part 4. The updating is performed so that a storage position of data to make the next cell conversion is indicated by setting the frame start address to �+48 bytes� and the residual frame length is set to �−48 bytes� every time the cell division multiplex part 5 sends out one cell since a payload length of one ATM cell is 48 bytes.
In the determination of step S15, if the cell division multiplex part 5 determines that the frame data for making cell conversion is not EOM (step S15/No), the cell is sent to the switch core 7 (step S16), and the frame information storage part 4 updates the start address of the frame buffer in the descriptor stored in the temporary to �+48 bytes� and the residual frame length to be sent to �−48 bytes� (step S17).
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