Source: http://www.google.se/patents/US8294180
Timestamp: 2017-11-22 09:17:01
Document Index: 701950636

Matched Legal Cases: ['Application No. 03788707', 'Application No. 2006800444311', 'Application No. 11', 'Application No. 094136197', 'Application No. 03817697', 'Application No. 10', 'Application No. 10', 'Application No. 200580009823', 'Application No. 200680021817', 'Application No. 05711376', 'Application No. 06815547', 'Application No. 112006001735', 'Application No. 10', 'Application No. 10', 'Application No. 95134963', 'Application No. 0724762', 'Application No. 200680023301', 'Application No. 03817699', 'Application No. 2006', 'Application No. 200580007279', 'Application No. 95122087', 'Application No. 95122087', 'Application No. 95123858', 'Application No. 95123858', 'Application No. 95123858', 'Application No. 95135820', 'Application No. 95135820', 'Application No. 95135820', 'Application No. 095143047', 'Application No. 200680021817', 'Application No. 200580032314', 'Application No. 200680044431', 'Application No. 200580032314', 'Application No. 2005070131', 'Application No. 200604766']

Patent US8294180 - CMOS devices with a single work function gate electrode and method of ... - Google Patent
Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of...http://www.google.se/patents/US8294180?utm_source=gb-gplus-sharePatent US8294180 - CMOS devices with a single work function gate electrode and method of fabrication
Publikationsnummer US8294180 B2
Ansökningsnummer US 13/038,190
Publiceringsdatum 23 okt 2012
Registreringsdatum 1 mar 2011
Även publicerat som US7902014, US20070090416, US20070111419, US20110180851
Publikationsnummer 038190, 13038190, US 8294180 B2, US 8294180B2, US-B2-8294180, US8294180 B2, US8294180B2
Citat från patent (552), Citat från andra källor (201), Hänvisningar finns i följande patent (22), Klassificeringar (22), Juridiska händelser (1)
US 8294180 B2
1. A pair of pMOS transistors, comprising:
a first SiGe channel region on a first region of a silicon substrate, the first SiGe channel region having a first concentration of Ge;
a second SiGe channel region on a second region of the silicon substrate, the second SiGe channel region having a second concentration of Ge, different than the first concentration of Ge;
a gate insulator on the first and second SiGe channel regions;
a first gate electrode on the gate insulator over the first SiGe channel region;
a second gate electrode on the gate insulator over the second SiGe channel region, wherein the first gate electrode and the second gate electrode have a same mid-gap work function to provide a first of the pair of pMOS transistors with a threshold voltage that is different than a second of the pair of pMOS transistors; and
a p-type doped source and drain on opposite sides of both the first and second gate electrodes.
6. The pMOS transistors of claim 5, wherein at least one of the first and second cladding layers have a thickness of between 5 Å and 300 Å and wherein at least one of the first or second concentration of Ge is between 25% and 30%.
11. A CMOS device, comprising
the pMOS transistors of claim 1, and
an nMOS transistor including a gate electrode of a material having a mid-gap work function between 4.5 and 4.9 eV.
This continuation application is related to, and claims priority to, the utility application entitled “CMOS DEVICES WITH A SINGLE WORK FUNCTION GATE ELECTRODE AND METHOD OF FABRICATION,” filed on Sep. 28, 2005 now abandoned having an application Ser. No. of 11/238,447; and divisional application entitled “CMOS DEVICES WITH A SINGLE WORK GATE ELECTRODE AND METHOD OF FABRICATION,” filed on Jan. 3, 2007, now U.S. Pat. No. 7,902,014 having an application Ser. No. of 11/649,545.
In the embodiments depicted in FIGS. 2A and 2B, CMOS devices 200 and 300, respectively, have a gate insulator layer 212. In the depicted embodiments, gate insulator 212 surrounds the cladding 208 of pMOS device 204 and the semiconductor body 207 of the nMOS device. In such tri-gate embodiments, gate dielectric layer 212 is formed on the sidewalls as well as on the top surfaces of the cladding 208 and semiconductor body 207, as shown in FIGS. 2A and 2B. In other embodiments, such as in FinFET or dual-gate designs, gate dielectric layer 212 is only formed on the sidewalls of the cladding 208 and sidewalls of semiconductor body 207. Gate insulator 212 can be of any commonly known dielectric material compatible with the cladding 208, semiconductor body 207 and the gate electrode 213. In an embodiment of the present invention, the gate dielectric layer is a silicon dioxide (SiO2), silicon oxynitride (SiOxNy) or a silicon nitride (Si3N4) dielectric layer. In one particular embodiment of the present invention, the gate dielectric layer 212 is a silicon oxynitride film formed to a thickness of between 5-20 Å. In another embodiment of the present invention, gate dielectric layer 212 is a high K gate dielectric layer, such as a metal oxide dielectric, such as to tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, or aluminum oxide. Gate dielectric layer 212 can be other types of high K dielectric, such as lead zirconium titanate (PZT).
In certain embodiments, semiconductor cladding layer 208 is selectively formed on the semiconductor body 206 of the pMOS device 204, as shown in FIG. 3E. Any commonly known epitaxial processes suitable for the particular semiconductor materials can be used to form the semiconductor cladding layer on the semiconductor body 206. In a particular embodiment, an LPCVD process using germane and a silane as precursors forms a SiGe cladding on a silicon semiconductor body. In still another embodiment, a silicon cladding layer is formed on a SiGe body to form an nMOS device. The cladding layer can be grown to have a particular composition determined by the amount of band offset desired. In a particular embodiment of the present invention a silicon germanium cladding layer having about 25 percent to about 30 percent germanium is formed. In other embodiments, the germanium concentration is about 50 percent. Ideally, the formation process is capable of producing a single crystalline cladding 208 from the semiconductor body 206 seed layer. In an embodiment of the present invention the cladding layer is epitaxially grown on both the top surface and the sidewalls of the semiconductor body 206. In another embodiment where the top surface of semiconductor body 206 is protected by a dielectric, the cladding layer is only grown on and adjacent to the sidewalls. In still other embodiments, when the transistor is a planar design, the cladding layer is grown only on the top surface. The semiconductor cladding layer is grown to the desired thickness, some embodiments including in-situ impurity doping. In certain embodiments where the semiconductor cladding 208 is not lattice matched to the semiconductor body 206, the maximum cladding thickness is the critical thickness. In an embodiment of the present invention, a SiGe cladding is grown to a thickness of 5-300 Å. Once the cladding 208 is formed, the mask layer 320 protecting the nMOS region 205 is removed by commonly known techniques, as shown in FIG. 3E. In still other embodiments of the present invention, semiconductor cladding 208 is formed on both the pMOS device 204 and the nMOS device 205.
EP1566844A3 18 feb 2005 5 apr 2006 Samsung Electronics Co., Ltd. Multi-gate transistor and method for manufacturing the same
JP6224440A Ingen titel tillgänglig
WO2007064492A1 17 nov 2006 7 jun 2007 Intel Corporation Dielectric interface for group iii-v semiconductor device
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USA-klassificering 257/192, 257/E29.242
Kooperativ klassning H01L29/1054, H01L29/785, H01L29/66795, H01L27/1211, H01L21/845, H01L21/823878, H01L21/823821, H01L21/823807, H01L29/66439, H01L29/775, H01L29/068, H01L29/0673
Europeisk klassificering H01L21/8238C, H01L27/12B4, H01L21/8238U, H01L21/8238F, H01L29/66M6T6F16F, H01L29/78S, H01L21/84F