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Patent US7031668 - Adaptive radio transceiver with a local oscillator - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including...http://www.google.com/patents/US7031668?utm_source=gb-gplus-sharePatent US7031668 - Adaptive radio transceiver with a local oscillatorAdvanced Patent SearchPublication numberUS7031668 B2Publication typeGrantApplication numberUS 10/165,464Publication dateApr 18, 2006Filing dateJun 7, 2002Priority dateOct 21, 1999Fee statusPaidAlso published asUS6404293, US6417737, US6608527, US7555263, US7720444, US7970358, US8041294, US20030042984, US20030067359, US20060205374, US20090286487, US20100295598Publication number10165464, 165464, US 7031668 B2, US 7031668B2, US-B2-7031668, US7031668 B2, US7031668B2InventorsHooman Darabi, Ahmadreza Rofougaran, Maryam RofougaranOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (22), Non-Patent Citations (1), Referenced by (33), Classifications (26), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetAdaptive radio transceiver with a local oscillatorUS 7031668 B2Abstract An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
a local oscillator comprising:
a quadrature oscillator that generates a first signal having a first frequency,
a quadrature frequency divider that generates a second signal from the first signal, the second signal having a second frequency, and
a first quadrature mixer that mixes the first signal and the second signal and produces a third signal having a third frequency; and
a transmitter having a second quadrature mixer, the second quadrature mixer mixing the third signal with a fourth signal.
2. A transceiver, comprising:
an oscillator configured to generate a first signal having a first frequency,
a frequency divider configured to generate a second signal from the first signal, the second signal having a second frequency, and
a first mixer configured to mix the first signal and the second signal to produce a third signal having a third frequency, and
a transmitter having a second mixer configured to mix the third signal and a fourth signal.
3. The transceiver according to claim 2, wherein the oscillator, the frequency divider, the first mixer and the second mixer are each quadrature.
4. The transceiver according to claim 2, wherein the third frequency comprises a sum of the first frequency and the second frequency.
5. The transceiver according to claim 2, wherein the oscillator comprises a voltage controlled oscillator.
6. The transceiver according to claim 5, wherein the local oscillator comprises a phase locked loop configured to control the first frequency of the first signal generated by the voltage controlled oscillator.
7. The transceiver according to claim 6,
wherein the local oscillator comprises a second oscillator and a second frequency divider,
wherein the second frequency divider is coupled to the second oscillator, and
wherein the voltage controlled oscillator is phase locked to an output of the second frequency divider.
8. The transceiver according to claim 7, wherein the second frequency divider comprises a programmable divisor input.
9. The transceiver according to claim 8, further comprising:
a receiver having a third mixer configured to mix the third signal and a fifth signal with a first control signal applied to the programmable divisor input,
wherein the third signal and the fourth signal are mixed by the second mixer with a second control signal applied to the programmable divisor input, and
wherein the second control signal is different from the first control signal.
10. The transceiver according to claim 2, wherein the fourth signal comprises a baseband signal.
11. The transceiver according to claim 2, wherein the frequency divider is programmable.
12. A method of communications, comprising:
generating, by an oscillator, a first signal having a first frequency;
generating, by a frequency divider, a second signal having a second frequency, the second signal being generated from the first signal;
mixing the first signal and the second signal to produce a third signal having a third frequency; and
mixing the third signal and a fourth signal.
13. The method according to claim 12, wherein the mixing of the first signal and the second signal is performed by a first mixer.
14. The method according to claim 13, wherein the oscillator, the frequency divider and the first mixer are part of a local oscillator of a transceiver.
15. The method according to claim 14, wherein the oscillator comprises a voltage controlled oscillator.
16. The method according to claim 15, wherein the local oscillator comprises a phase locked loop that controls the first frequency of the first signal generated by the voltage controlled oscillator.
18. The method according to claim 17, wherein the second frequency divider comprises a programmable divisor input.
mixing, by a third mixer of a receiver, the third signal and a fifth signal;
applying a first control signal to the programmable divisor input and
applying a second control signal to the programmable divisor input, the second control signal being different from the first control signal,
wherein the mixing of the third signal and the fourth signal is performed by a second mixer.
20. The method according to claim 13, wherein the mixing of the third signal and a fourth signal is performed by a second mixer.
21. The method according to claim 20, wherein the second mixer is part of a transmitter of a transceiver.
22. The method according to claim 21, wherein the oscillator, the frequency divider, the first mixer and the second mixer are each quadrature.
23. The method according to claim 12, wherein the third frequency comprises a sum of the first signal and the second signal.
24. The method according to claim 12, wherein the fourth signal comprises a baseband signal.
25. The method according to claim 12, wherein the frequency divider is programmable.
CROSS-REFERENCE TO RELATED APPLICATION The present application is a continuation of patent application Ser. No. 09/691,633, filed Oct. 18, 2000, now issued U.S. Pat. No. 6,404,293 B1, which is a continuation of patent application Ser. No. 09/634,552, filed Aug. 8, 2000, which claims priority to and benefit from provisional Application No. 60/160,806, filed Oct. 21, 1999; Application No. 60/163,487, filed Nov. 4, 1999; Application 60/163,398, filed Nov. 4, 1999; Application No. 60/164,442, filed Nov. 9, 1999, Application No. 60/164,494, filed Nov. 9, 1999; Application No. 60/164,314, filed Nov. 9, 1999; Application No. 60/165,234, filed Nov. 11, 1999; Application No. 60/165,239, filed Nov. 11, 1999; Application No. 60/165,356, filed Nov. 12, 1999; Application No. 60/165,355, filed Nov. 12, 1999; Application No. 60/172,348, filed Dec. 16, 1999; Application No. 60/201,335, filed May 2, 2000; Application No. 60/201,157, filed May 2, 2000; Application No. 60/201,179, filed May 2, 2000; Application No. 60/202,997, filed May 2, 2000; and Application No. 60/201,330, filed May 2, 2000. All these applications are expressly incorporated herein by reference in their entirety as though fully set forth in full.
FIELD OF THE INVENTION The present invention relates to telecommunication systems and, in particular, to radio transceiver systems and techniques.
BACKGROUND OF THE INVENTION Transceivers are used in wireless communications to transmit and receive electromagnetic waves in free space. In general, a transceiver comprises three main components: a transmitter, a receiver, and an LO generator or frequency synthesizer. The function of the transmitter is to modulate, upconvert, and amplify signals for transmission into free space. The function of the receiver is to detect signals in the presence of noise and interference, and provide amplification, downconversion and demodulation of the detected signal such that it can be displayed or used in a data processor. The LO generator provides a reference signal to both the transmitter for upconversion and the receiver for downconversion.
SUMMARY OF THE INVENTION In one aspect of the present invention, an oscillator circuit includes an oscillator to generate a first signal having a first frequency, a second oscillation source to generate a second signal having a second frequency, and a mixer to mix the first and second signals.
In another aspect of the present invention, an oscillator circuit, comprising oscillation means for generating a first signal having a first frequency, signal generation means for generating a second signal having a second frequency, and mixer means for mixing the first and second signals.
In yet another aspect of the present invention, a transceiver includes a local oscillator generator having an oscillator with a first signal having a first frequency, a frequency divider coupled to the oscillator to divide the first frequency of the first signal to produce a second signal having a second frequency, the frequency divider having a programmable divisor, and a mixer to mix the first and second signals, and a controller to program the divisor.
In still another aspect of the present invention, a method of generating a signal having a signal frequency includes generating a first signal having a first frequency, dividing the first frequency to generate a second signal having a second frequency, and mixing the first and second signals to generate the signal frequency.
In a further aspect of the present invention, a method of generating a local oscillator signal having a signal frequency includes generating a first signal having a first frequency, generating a second signal having a second frequency, and mixing the first and second signals to generate the signal frequency.
FIG. 7 is a graphical depiction of the frequency response of the biquad stage of FIG. 6 in accordance with an exemplary embodiment of the present invention;
FIG. 10 is an electrical diagram of a modified biquad stage of FIG. 6 in accordance with an exemplary embodiment of the present invention;
FIG. 12( b) is an electrical diagram of a tunable array of resistors in accordance with an exemplary embodiment of the present invention;
FIG. 16( b) is a block diagram of a full-wave rectifier of the programmable multiple stage amplifier of FIG. 14 in accordance with an exemplary embodiment of the present invention;
FIG. 19( b) is a graphical depiction of a signal spectrum at the output of a two stage polyphase filter of the clock generator of FIG. 18 in accordance with an exemplary embodiment of the present invention;
FIG. 27 is an electrical diagram of a bias circuit for a current source of the differential power amplifier of FIG. 25 in accordance with an exemplary embodiment of the present invention;
FIG. 33 is a block diagram of a LO architecture in accordance with yet another exemplary embodiment of the present invention;
The receiver 10 provides detection of desired signals in the presence of noise and interference. It should be able to extract the desired signals and amplify it to a level where information contained in the received transmission can be processed. In the described exemplary embodiment, the receiver 10 is based on a heterodyne complex (I-Q) architecture with a programmable intermediate frequency (IF). The LO generator 14 provides a reference signal to the receiver 10 to downconvert the received transmission to the programmed IF.
FIG. 2 shows a block diagram of the transceiver in accordance with an embodiment of the invention. The described exemplary embodiment is integrated into a single IC. For case of understanding, each component coupled to the controller is shown with a �program� designation or a �calibration� designation. These designations indicate whether the component is programmed by the controller or calibrated by the controller, in practice, in accordance with the described exemplary embodiment of tbc present invention, the components that are programmed receive the most significant bits (MSBs) and the components that are calibrated receive the least significant bits (LSBs). The components requiring both programming and calibration receive the entire digital output from the controller. As those skilled in the art will appreciate, any number of methodologies may be used to deliver programming and calibration information to the individual components. By way of example, a single controller bus could be used having the programming and or calibration data with the appropriate component addresses.
The output of the amplifier 28 is coupled to a second set of complex IF mixers 30 where it is mixed with the IF clocks from the LO generator for the purpose of downconverting the complex IF signal to baseband. The complex IF mixers 30 not only reject the image of the complex IF signal, but also reduce some of the unwanted cross modulation spurious signals thereby relaxing the filtering requirements.
The complex baseband signal from the mixers 30 is coupled to a programmable passive polyphase filter within a programmable low pass filter 32. The programmable low pass filter 32 further filters out higher order cross modulation products. The polyphase filter can be centered at four times the IF frequency to notch out one of the major cross modulation products which results from the multiplication of the third harmonic of the IF signal with the IF clock. After the complex baseband signal is filtered, it either is passed through an analog-to-digital (A/D) converter 34 to be digitized or is passed to an analog demodulator 36. The analog demodulator 36 can be implemented to handle any number of different modulation schemes by way of example FSK. Embodiments of the present invention with an FSK demodulator uses the A/D converter 34 to sample baseband data with other modulation schemes for digital demodulation in a digital signal processor (not shown).
The LO generator 14 provides the infrastructure for frequency planning. The LO generator 14 includes an IF clock generator and an RF clock generator. The IF clock generator includes an oscillator 38 operating at a ratio of the RF signal (fOCS). High stability and accuracy can he achieved in a number of ways including the use of a crystal oscillator.
The reference frequency output from the oscillator 38 is coupled to a divider 40. The divider 40 divides the reference signal fOSC by a number L to generate the IF clocks for downconverting the complex IF signal in the receiver to baseband. A clock generator 41 is positioned at the output of the divider 40 to generate a quadrature sinusoidal signal from the square wave output of the divider 40. Alternatively, the clock generator 41 can be located in the receiver. The divider 40 may be programmed by the program input. This feature allows changes in the IF frequency to avoid interference from an external source.
In the described exemplary embodiment, the RF clocks are generated in the LO generator 14. This can be accomplished in various fashions including, by way of example, either generating the RF clocks in the VCO or using a polyphase circuit to generate the RF clocks. Regardless of the manner in which the RF clocks are generated, the mixer 52 will produce a spectrum of frequencies including the sum and difference frequencies, specifically, fVCO�(1+(1/N)) and its image fVCO�(1−(1/N)). To reject the image, the mixer 52 can be configured as a double quadrature mixer as depicted in FIG. 3. The double quadrature mixer includes one pair of mixers 55, 57 to generate the Q-clock and a second pair of mixers 59, 61 to generate the I-clock. The Q-clock mixers utilizes a first mixer 55 to mix the I output of the VCO 48 (see FIG. 2) with the Q output of the divider 50 and a second mixer 57 to mix the Q output of the VCO with the I output of the divider. The outputs of the first and second mixers are connected together to generate the Q-clock. Similarly, the I-clock mixers utilizes a first mixer 59 to mix the I output of the divider with the I output of the VCO and a second mixer 61 to unix the Q output of the divider with the Q output of the VCO. The outputs of the first and second mixers are connected together to generate the I-clock. This technique provides very accurate I-Q clocks by combination of quadrature VCO and filtering. Because of the quadrature mixing, the accuracy of the I-Q clocks is not affected by the VCO inaccuracy, provided that the divide by N circuit generates quadrature outputs. This happens for even divide ratios, such as N=2.
FIG. 4 shows a schematic of a single-to-differential amplifier having two identical cascode stages that are driven by the same single-ended input 64. The input 64 is coupled to a T-network having two series capacitors 82, 84 and a shunt inductor 72. The first stage includes a pair of transistors 74, 78 connected between the shunt inductor 72 and a DC power source via an inductor 68. The second stage includes a complimentary pair of transistors 76, 80 connected between ground and the DC power source via an inductor 70. The gate of one of the transistors 80 in the second stage is connected to the output of the T-network at the capacitor 84. A bias current is applied to the gate of each transistor.
For DC biasing purposes, the shunt inductor 72 provides a short circuit to ground allowing both stages of the amplifier to operate at the same DC drain current. The output capacitor 84 provides DC isolation between the gate bias applied to the transistor 80 of the second stage and the source 79 of the transistor 78 in the first stage.
In operation, a signal applied to the input of the amplifier is coupled to both the source 79 of the transistor 78 of the first stage and the gate 75 of the transistor 80 of the second stage. This causes the gain of each stage to vary inversely to one another. As a result, the signal voltage applied to the input of the amplifier is converted to a signal current with the signal current in the first stage being inverted from the signal current in the second stage. Moreover, the two stages will generate the same gain because the gm of the transistors should be the same, and therefore, the total gain of the amplifier is twice as much as conventional single-to-differential amplifiers.
The output of cascoded transistor 481 is coupled to the supply voltage through a first inductor 490. The output of the cascoded transistor 486 is coupled to the supply voltage through a second inductor 492. The LNA is tuned to the operating frequency by the output inductors 490, 492. More particularly, these inductors 490, 492 resonate with the LNA output parasitic capacitance, and the input capacitance of the next stage (not shown). Embodiments of the present invention integrated into a single integrated circuit do not require a matching network at the LNA output.
The described complex filter can be integrated into a single chip transceiver or used in other low noise applications, in the case of transceiver chip integration, the off-chip filters used for image rejection and channel selection can be eliminated. A low-IF receiver architecture enables the channel-select feature to be integrated into the on-chip filter. However, if the IF lies within the bandwidth of the received signal, e.g., less than 80 MHz in the Bluetooth standard, the on-chip filter should be a complex filter (which in combination with the complex mixers) can suppress the image signal. Thus, either a passive or an active complex filter with channel select capability should be used. Although a passive complex filter does not dissipate any power by itself, it is lossy, and loads the previous stage significantly. Thus, an active complex filter with channel select capability is preferred. The channel select feature of the active complex filter can achieve comparable performance to conventional band-pass channel-select filters in terms of noise figure, linearity, and power consumption.
The Poles of a Biquad Stage
FIG. 6 shows an exemplary embodiment of a biquad stage of the complex filter. The biquad stage includes two first order resistor-capacitor (RC) filters each being configured with a differential operational amplifier 94, 96, respectively. The first differential operational amplifier 94 includes two negative feedback loops, one between each differential output and its respective differential input. Each feedback loop includes a parallel RC circuit (98, 106), (108, 100), respectively. Similarly, the second differential operational amplifier 96 includes two negative feedback loops, one between each differential output and its respective differential input. Each feedback loop includes a parallel RC circuit (102, 110), (112, 104), respectively. This topology is highly linear, and therefore, should not degrade the overall IIP3 of the receiver. The RC values determine the pole of the biquad stage.
V OI = A ⁢ ⁢ ( 1 + j ⁢ ⁢ RC ⁢ ⁢ ω ) ⁢ V II + 2 ⁢ QV IQ ( 1 + j ⁢ ⁢ RC ⁢ ⁢ ω ) 2 + 4 ⁢ Q 2 ⁢ ( 1 ) and
V OQ = A ⁢ - 2 ⁢ QV II + ( 1 + j ⁢ ⁢ RC ⁢ ⁢ ω ) ⁢ V IQ ( 1 + j ⁢ ⁢ RC ⁢ ⁢ ω ) 2 + 4 ⁢ Q 2 ( 2 ) FIG. 7 shows the frequency response for the complex biquad filter.
H ⁡ ( j ⁢ ⁢ ω ) = V o V I ⁢ ( jω ) = A 1 + j ⁢ ⁢ RC ⁢ ⁢ ω - j ⁢ ⁢ 2 ⁢ Q ( 3 ) This shows a passband gain of A 122 at a center frequency of 2Q/RC 124, with a 3-dB bandwidth of 2RC 126. Thus, the quality factor of the second-order stage will be Q. For the image signal however, the signal at the I branch leads, and as a result:
H ⁡ ( jω ) = A 1 + j ⁢ ⁢ RC ⁢ ⁢ ω + j ⁢ ⁢ 2 ⁢ ⁢ Q ( 4 ) which shows that the image located at 2Q/RC is rejected by
j ⁢ ⁢ ω → j ⁡ ( ω - ω 0 ) BW ( 5 ) where ω0 is the bandpass (BP) center frequency, and BW is the lowpass (LP) equivalent bandwidth, equal to half of the bandpass filter bandwidth. For instance, for a second-order biquad stage (as shown in FIG. 6), ω0=2Q/RC, and BW=1/RC. The biquad stage is designed by finding its LP equivalent frequency response using equation (5). Once the LP poles are known, the BP poles are calculated based on equation (5). Assume that the LP equivalent has n poles, and Pl,LP=αi+jβ, is the ith pole. From equation (5), the BP pole will be:
P l,BP =BW�P l,LP +jω 0=αl �BW+j(ω0+βl �BW) (6)
α i � BW = - 1 RC ( 7 ) and
ω o + β i � BW = 2 ⁢ Q RC ( 8 ) Since the LP equivalent poles are located in the left-half plane, ai is always negative. The above equations set the value of Q and RC in each stage. The gain of each biquad stage can be adjusted based on the desired gain in the complex filter, and noise-linearity trade-off: increasing the gain of one biquad stage lowers the noise contributed by the following biquad stages, but it also degrades the linearity of the complex filter.
jω → j ⁡ ( ω 2 - ω 0 2 ) BW � ω ( 9 ) This symmetric response in the biquad stage ensures a uniform group delay across the data band.
In order to have a zero located at jω axis in the frequency response, Yl should contain a term such as 1−ω/ωz. If Yl is simply made of a resistor Rz in parallel with a capacitor Cz, then the input admittance will be equal to:
Y i = 1 R z + j ⁢ ⁢ ω ⁢ ⁢ C z ( 11 ) which is not desirable, since the zero will be in the left-half plane, rather than the j ω axis.
FIG. 10 shows a single biquad stage modified to have a zero at the j ω axis. The biquad stage includes capacitors 138, 140, 142, 144. The combination of capacitors 138, 140, 142, 144 and resistors 116, 118 determines a complex zero with respect to the center frequency. The transfer function for the received signal will be:
H ⁡ ( j ⁢ ⁢ ω ) = A ⁢ ⁢ 1 - RC z A ⁢ ω 1 + j ⁢ ⁢ RC ⁢ ⁢ ω - j ⁢ ⁢ 2 ⁢ Q ( 14 ) Equation (14) is analogous to equation (3), with the difference that now a zero at A/RCz is added to the biquad stage of the complex filter. By knowing the LP equivalent characteristics of the biquad stage, the poles are calculated based on equation (6). The value of Q and RC in each biquad stage is designed by using equation (7) and equation (8). If the normalized LP zeros are at �ωz,LP, then the biquad stage should be realized with two biquad stages cascoded, and the frequency of zeros in the biquad stages will be (equation (5)):
ωzl,2=ω0�ωz,LP �BW (15)
The center frequency of the complex filter can be adjusted by setting 1/RuCu equal to a reference frequency generated, by way of example, by the crystal oscillator in the controller. The filter is automatically tuned by monotonic successive approximation as described in detail in Section 4.0 herein. Once the value of RuCu is set, the complex filter characteristics depends only on the four-bit code for the capacitors and the five-bit code for the resistors. For example, assume that the value of the resistors in the biquad stage of FIG. 6 is as following: Ri=nARu, Rf=nQRu, and Rc=nQRu. Likewise, assume that C=nCCu, where nC is a constant, and that 1RuCu=ωu. The value of ωu is set to a reference crystal by a successive approximation feedback loop. The filter frequency response for the received signal will be:
H ⁡ ( j ⁢ ⁢ ω ) = n F n A 1 + j ⁢ ⁢ n c ⁢ n F ⁢ R u ⁢ C u ⁢ ω - j ⁢ ⁢ n F n Q ( 16 ) Therefore, the biquad stage gain (A), center frequency (ω0), and bandwidth (BW) will be equal to:
A = n F n A . ( 17 ) ω 0 = 1 n C ⁢ n Q � ω u ( 18 ) BW = 1 n C ⁢ n F � ω u ( 19 ) The above equations show that the characteristics of the biquad stage is independently programmed by varying nA, nF, and nQ. For instance, by setting nF, the gain of the biquad stage changes from nF/31 to nF by changing nA from 1 to 31.
FIG. 14 shows a block diagram of an exemplary embodiment of the programmable multiple gain amplifier with an RSSI output. The RSSI output provides an indication of the strength of the IF signal. The programmable multiple gain amplifier includes three types of amplifiers. The input buffer is shown as a type I amplifier 929 and the type III amplifier 944 serves as the output buffer. The core amplifier is shown as a direct-coupled cascade of seven differential amplifiers 930, 931, 932, 933, 934, 935, 936. The core amplifier includes seven bypass switches 930′, 931′, 932′, 933′, 934′, 935′, 936′, one bypass switch connected across each differential amplifier. The bypass switches provide programmable gain under control of the controller (see FIG. 2).
Turning back to FIG. 14, the type II core amplifier includes a direct-coupled cascade of seven differential amplifiers 930, 931, 932, 933, 934, 935, 936, each with a voltage gain, by way of example, 12 dB. The voltage at the output of each differential amplifier930, 931, 932, 933, 934, 935, 936 is coupled to a rectifier 937, 938, 939, 940, 941, 942, 943, respectively. The outputs of the rectifiers are connected to ground through a common resistor 945. The summation of the currents from each of the rectifiers flowing through the common resistor provides a successive logarithmic approximation of the input IF voltage. With a 12 dB gain per each differential amplifier, a total cascaded gain of 84 dB is obtained. As those skilled in the art will appreciate, any number of differential amplifiers, each with the same or different gain, may be employed.
y=β 2 V ln 2 (20)
Now, assume that S is the maximum input range of one differential amplifier and rectifier combination, whichever is smaller. This is determined with the lowest of the two values Vl and VL that are the maximum input range of each differential amplifier, and the maximum input range of the rectifier, respectively.
S=min(V l ,V L) (21)
Ideal��Dynamic��Range = 20 ⁢ ⁢ log ⁢ ⁢ S S A n = 20 ⁢ ⁢ log ⁢ ⁢ A n = 20 ⁢ ⁢ ( n ) ⁢ log ⁢ ⁢ A ( 22 ) However, in the case of a large amount of gain, the input level will be limited with the input noise and the dynamic range will also be limited to:
Dynamic��Range = 20 ⁢ ⁢ log ⁢ ⁢ S σ n ⁢ ⁢ σ n = total��noise��rms ⁢ ⁢ σ n = ( BW ) � Noise��Factor ( 23 ) If each differential amplifier has the same input dynamic range VL and each full-wave rectifier has similar input dynamic range Vi, then the dynamic range of the logarithmic differential amplifier and the total RSSI circuitry are the same.
A 2β2 v in 2 +A 4β4 v in 4 + . . . +A 2(n−m)β2(n−m) v in 2(n−m) +mβ 2S2 =RSSI (25)
RSSI = ( A ⁢ ⁢ β ) 2 ( A ⁢ ⁢ β ) 2 - 1 ⁢ V in 2 ⁡ [ ( A ⁢ ⁢ β ) 2 ⁢ ( n - m - 1 ) - ] + m ⁢ ⁢ β 2 ⁢ S 2 ( 26 ) RSSI ≈ 1 ( A ⁢ ⁢ β ) 2 - 1 ⁢ V in 2 ⁡ ( A ⁢ ⁢ β ) 2 ⁢ ( n - m ) + m ⁢ ⁢ β 2 ⁢ S 2 ( 27 ) The above equation is a first order approximation to the logarithmic function shown in equation (28) according to the first two terms of the Taylor expansion at a given operating point.
Ideal RSSI=C log V in 2 (28)
Max RSSI−Min RSSI=C log A 2n (29)Δ RSSI=C log A 2n (30)
C = Δ ⁢ ⁢ RSSI 2 ⁢ n ⁢ ⁢ log ⁢ ⁢ A ( 31 ) ( Ideal ) ⁢ RSSI = Δ ⁢ ⁢ RSSI 2 ⁢ n ⁢ ⁢ log ⁢ ⁢ A ⁢ log ⁢ ⁢ V in 2 ( 32 ) To find the relation between the gain of a differential amplifier, the gain of a rectifier, and the maximum input range of the combined differential amplifier and the rectifier, the RSSI will be calculated for the two consecutive differential amplifier and rectifier combinations (see equations (33) and (34)) for both ideal RSSI equations (32) and approximated RSSI equation (27):
V in ⁢ ⁢ 1 = S ( A ) n - m ( 33 ) V in ⁢ ⁢ 2 = S ( A ) n - m - 1 ( 34 ) (Ideal)RSSI 2 −RSSI 1=log(A)2 (35)(Approximated)RSSI 2 −RSSI 1=β2 S 2 (36)
RSSI = 1 ( A ⁢ ⁢ β ) 2 - 1 ⁢ ( A ⁢ ⁢ β ) 2 ⁢ ( n - m ) ⁢ V in 2 + m ⁢ ⁢ Δ ⁢ ⁢ RSSI n ; S A n - m < V in < S A n - m - 1 ( 39 ) FIG. 16( a) shows a schematic diagram for an exemplary embodiment of the differential amplifier used in the type II core amplifier. The differential input signal is fed to the gates of transistor amplifiers 955, 957. The amplified differential output signal is provided at the drains of the transistor amplifiers 955, 957. The gain of the transistor amplifiers is set by load transistors 958, 860, each connected between the drain of one of the transistor amplifiers and a power source. More particularly, the gain of the differential amplifier is determined by the ratio of the square root of transistor amplifiers-to-load transistors.
Gain ⁢ ( A ) = ⁢ w in w in = ⁢ 200 6 ≈ 5.8 ( 40 ) The sources of the transistor amplifiers 955, 957 are connected in common and coupled to a constant current source transistor 952. In the described exemplary embodiment, the controller provides the bias to the gate of the transistor 952 to set the current.
Transistors 970 and 971 provide a current-mirror load to cross-coupled transistors 968, 962. Similarly, transistors 972, 973 provide a current-mirror load to cross-coupled transistors 966, 964. The current through the cross-coupled transistors 966, 964 is the sum of the current through the load transistor 972 and the current through the load transistor 971 which is mirrored from the load transistor 970. The current through the cross-coupled transistors 966, 964 is also mirrored to load transistor 973 for the RSSI output.
When the transistors 962, 964, 966, and 968 are operating in the saturation region, the following equations are shown for the differential output current DISQBl where k is the ratio of the two unbalanced source-coupled transistors:
if ⁢ ⁢ Δ ⁢ ⁢ I SQM1 = ⁢ ( I D1 + I D4 ) - ( I D2 + I D3 ) = ⁢ 2 ⁢ ( I DC + I SQ ) = ⁢ 2 ⁢ k - 1 k + 1 ⁢ I o - 4 ⁢ k ⁢ ( k - 1 ) ⁢ β N ( k + 1 ) 2 ⁢ V I 2 ( 41 ) The input dynamic range of the full rectifier is then:
if ⁢ ⁢ Δ ⁢ ⁢ I SQM1 = O , V i = � I o ⁢ β N ⁢ k + 1 2 ⁢ k ⁢ ( 42 ) The full-wave rectifier includes two unbalanced differential pairs with a unidirectional current output. One rectifier taps each differential pair and sums their currents into a 10 kW resistor RL.
β 2 ⁢ S 2 = 4 ⁢ ⁢ k ⁢ ( k - 1 ) ⁢ β N ( k + 1 ) 2 ⁢ V i 2 ⁢ R L ( 43 ) By plugging the Vl from equation (42) and replacing β2S2 from equation (38), the following relation is obtained:
Δ ⁢ ⁢ RSSI n = 2 ⁢ ⁢ k - 1 k + 1 ⁢ I o ⁢ R L ( 44 ) For ΔRSSI=1V, n=7 stages, RL=10000Ω, and k=4, from the above equation Io is calculated to be 12 mA. Therefore, each rectifier will be biased with two 12 mA current sources (one 12 ma current source for the I signal and a second 12 ma current source for the Q channel). This results in an approximately logarithmic voltage, which indicates the received signal-strength (RSSI).
The outputs of the limiters are coupled to the quadrature clocks of the IF mixers (I_in for mixer 322, Q_in for mixer 323, I_in for mixer 324, Q_in for mixer 325) and the IF clocks are coupled to the data input of the IF mixers. This configuration minimizes spurs at the output of the IF mixers because the signal being mixed is the IF clocks which is a clean sine wave, and therefore, has minimal harmonics. The limiting action of the programmable multiple stage amplifier on the I and Q data will have essentially no effect on the spurs at the output of the IF mixers. FIG. 17 b shows the IF mixer clock signal spectrum which contains only odd harmonics. The IF signals do not have even harmonics in embodiments of the present invention using a fully differential configuration. The bandwidth of the m'th(=2n+1) harmonic is directly proportional to mfs, whereas its amplitude is inversely proportional to mfs. FIG. 17 c shows the sinusoidal input spectrum of the IF clocks. FIG. 17 d shows the IF mixer output spectrum.
A clock generator can be used to generate a quadrature sinusoidal signal with controlled amplitude. The clock generator can be located in the receiver, or alternatively the LO Generator, and provides a clean sinusoidal IF from the square wave output of the divider in the LO Generator for downconverting the IF signal in the receiver path to baseband. FIG. 18 shows a block diagram and signal spectrum of a clock generator. A sinusoidal signal is generated from a square-wave using cascaded polyphase. FIG. 18 shows a clock generator block diagram. The clock generator outputs clk_I and clk_Q for the IF mixer buffer (see FIG. 17). The clock generator includes a polyphase filter at 3fs 360, a polyphase filter at 5fs 362, and a low pass filter 364. FIG. 19 a shows the input clock signal spectrum. FIG. 19 b shows the spectrum after 3fs 366 and 5fs 368 polyphase. FIG. 19 c shows the sinusoidal signal generation after the low pass filter 364.
FIG. 23 shows an exemplary analog multiplier 331, 332 with zero higher harmonics in accordance with the present invention. Buffers one 337 and two 335 are added to a Gilbert cell to linearize the voltage levels. Buffers one 337 and two 335 convert the two inputs into two voltage levels for true analog multiplication using a Gilbert cell. The Gilbert cell is comprised of transistors 336, 338, resistors 382, 372 and cross-coupled pairs of transistors 374, 376 and transistors 378, 380.
An exemplary peak detector/slicer for frequency data detection is shown in FIG. 24. The differential input signal is coupled to a peak detector 346 which detects the high peak. The differential input signal is also coupled to a second peak 347 detector which detects the low valley of the signal. The outputs of the peak detectors are coupled to a resistor divider network 348, 349 to obtain the average of the output signal. The, average signal output from the resistor divider network is used as the calibrated zero frequency to obviate frequency offset problems due to the frequency translation process from IF to baseband.
A differential amplifier 345 is used to digitize the frequency information by comparing the differential input signal with the calibrated zero frequency. The output of the amplifier is a logic �1 � if the baseband frequency is greater than the calibrated zero frequency and a logic �0� if the baseband frequency is less than the calibrated zero frequency. The output is amplified through several inverters 350 which in turn generate digital rail to rail output.
Capacitances associated with bias resistors may also be addressed. Consider a typical distributed model for a polysilicon (�poly� for short) resistor. Around 4fF to substrate can be associated with every kilo-ohm of resistance in a poly resistor. This means that, for example in a 20 Kohm resistor, around 80fF of distributed capacitance to the substrate exists. This can contribute to power loss because part of the power will be drained into the substrate. One way of biasing the input stage and the output stage is through a resistive voltage divider as shown in FIG. 26( a). The biasing of the input stage is shown for the transistor 616 in FIG. 25, however, those skilled in the art will readily appreciate that the same biasing circuit can be used for the transistor 614 (FIG. 25). One drawback from this approach, however, is that the gate of the transistor will see the capacitance from the two resistors 658, 660 of the voltage divider. Capacitor 662 is a coupling capacitor, which couples the previous stage to the voltage divider. Switch 664 is for powering down the stage of the power amplifier that is connected to the voltage divider. The switch 664 is on in normal operation and is off in power down mode.
The power control circuit includes transistor pairs in parallel. Transistors 674, 676, 678, 680 are switch transistors and are coupled to diode-connected transistors 682, 684, 686, 688, respectively. The switch transistors 674, 676, 678, 680 are coupled to a current source 670. Each diode-connected transistor 682, 684, 686, 688 can be switched into the parallel combination by turning its respective switching transistor on. Conversely, any diode-connected transistor can be removed from the parallel combination by turning its respective switch transistor off. The current from the current source 670 is injected into a parallel combination of switch transistors 674, 676, 678, 680. The power level can be incremented or decremented by switching one or more switch transistors into the parallel combination. By way of example, a decrease in the power level can be realized by switching a switch transistor into the parallel combination. This is equivalent to less voltage drop across the parallel combination, which in turn corresponds to a lower power level. A variety of stages are comprehended in alternative embodiments of the invention depending on the number of power levels needed for a given application. A thermometer code from the controller can be applied to the power control circuit according to which the power level is adjusted.
Alternatively, the bias circuit of the amplifying transistors 700, 702 for single IC embodiments can be set with a power control circuit as shown in FIG. 28. The current source is connected directly to the amplifying transistor 700. By incrementally switching the diode-connected transistors 682, 684, 686, 688 into the parallel combination, the voltage applied to the gate of the amplifying transistor 700 is incrementally pulled down toward ground. Conversely, by incrementally switching the diode-connected transistors 682, 684, 686, 688 out of the parallel combination, the voltage applied to the gate of the amplifying transistor 700 is incrementally pulled up toward the source voltage (not shown). A similar power control circuit can be used with the amplifying transistor 702.
Transistor 756 has two purposes. First, it is a current source that biases transistors 734, 738. Second, it provides a means for switching transistors 734, 738 in and out of the circuit to alter the gain of the output stage amplifier. Each transistors 758, 760, 762 serves the same purpose for its respective transistor pair. A digital control word from the controller can be applied to the gates of the transistors 756, 758, 760, 762 to digitally set the power level. This approach provides the flexibility to apply ramp up and ramp down periods to the PA, in addition to the possibility of digitally controlling the power level. The drains of the transistors 734, 744, 748, 752 and 738, 746, 750, 754 are connected to a circuit that serves a twofold purpose: 1) it converts the differential output to single ended output, and 2) it matches the stage to external 50 ohm antenna to provide maximum transferable gain.
In embodiments of the present invention utilizing a low-IF or direct conversion architecture, techniques are implemented to deal with the potential disturbance of the local oscillator by the PA. Since the LO generator has a frequency which coincides with the RF signal at the transmitter output, the large modulated signal at the PA output may pull the VCO frequency. The potential for this disturbance can be reduced by setting the VCO frequency far from the PA output frequency. To this end, an exemplary embodiment of the LO generator produces RF clocks whose frequency is close to the PA output frequency, as required in a low-IF or direct-conversion architectures, with a VCO operating at a frequency far from that of the RF clocks. One way of doing so is to use two VCOs 864, 866, with frequencies of f1 and f2 respectively, and mix 868 their output to generate a clock at a higher frequency of f1+f2 as shown in FIG. 31( a). With this approach, the VCO frequency will be away from the PA output frequency with an offset equal to f1 (or f2). A bandpass filter 876 after the mixer can be used to reject the undesired signal at f1�f2. The maximum offset can be achieved when f1 is close to f2.
An alternative embodiment for generating RF clocks far away in frequency from the VCO is to generate f2 by dividing the VCO output by N as shown in FIG. 31( b). The output of the VCO 864 (at f1) is coupled to a divider 872. The output of the divider 872 (at f2) is mixed with the VCO at mixer 868 to produce an RF clock frequency equal to: fLO=f1′(1+1/N), where f1 is the VCO frequency. A bandpass filter 874 at the mixer output can be used to reject the lower sideband located at f1�f1/N.
In another embodiment of the present invention, a single sideband mixing scheme is used for the LO generator. FIG. 32 shows a single sideband mixing scheme. This approach generates I and Q signals at the VCO 864 output. The output of the VCO 864 is coupled to a quadrature frequency divider 877 that should be able to deliver quadrature outputs. Quadrature outputs will be realized if the divide ratio (N) is equal to two to the power of an integer (N=2n). The I signal output of the divider 877 is mixed with the I signal output of the VCO 864 by a mixer 878. Similarly, the Q signal output of the divider 877 is mixed with the Q signal output of the VCO 864 by a mixer 880.
FIG. 33 shows an LO generator architecture in accordance with an embodiment of the present invention. This architecture is similar to the architecture shown in FIG. 32, except that the LO generator architecture in FIG. 33 generates I-Q data. In a low-IF system, a quadrature LO is desirable for image rejection. In the described embodiment, the I and Q outputs of the VCO can be applied to a pair of single sideband mixer to generate quadrature LO signals. A quadrature VCO 48 produces I and Q signals at its output. Buffers are included to provide isolation between the VCO output and the LO generator output. The buffer 884 buffers the I output of the VCO 48. The buffer 886 buffers the Q output of the VCO 48. The buffer 888 combines the I and Q outputs of the buffers 884, 886. The signal from the buffer 888 is coupled to a frequency divider 890 where it is divided by N and separated into I and Q signals. The I-Q outputs of the divider 890 are buffered by buffer 891 and buffer 894. The I output of the divider 890 is coupled to a buffer 891 and the Q signal output of the divider 890 is coupled to a buffer 894. A first mixer 896 mixes the I signal output of the buffer 891 with the I signal output of the buffer 884. A second mixer 897 mixes the Q signal output from the buffer 894 with Q signal output from the buffer 886. A third mixer 898 mixes the Q signal output of the buffer 894 with the I signal output of the buffer 884. A fourth mixer 899 mixes the I signal output from the buffer 891 with the Q signal output from the buffer 886. The outputs of the first and second mixers 896, 897 are combined and coupled to buffer 893. The outputs of the third and fourth mixers 898, 899 are combined and coupled to buffer 895. LC circuits (not shown) can be positioned at the output of each buffer 893, 895 to provide a second-order filter which rejects the spurs and harmonics produced due to the mixing action in the LO generator.
The lower sideband signal is ideally rejected with the described embodiment of the LO generator because of the quadrature mixing. However, in practice, because of the phase and amplitude inaccuracy at the VCO and divider outputs, a finite rejection is obtained. In single IC fully integrated embodiments of the present invention, the rejection is mainly limited to the matching between the devices on chip, and is typically about 30�40 dB. Since the lower sideband signal is 2�f1/N away in frequency from the desired signal, by proper choice of N, it can be further attenuated with on-chip filtering.
Because of the hard switching action of the buffers, the mixers will effectively be switched by a square-wave signal. Thus, the divider output will be upconverted by the main harmonic of VCO (f1), as well as its odd harmonics (n�f1), with a conversion gain of 1/n. In addition, at the input of the mixer, because of the nonlinearity of the mixers, and the buffers preceding the mixers, all the odd harmonics of the input signals to the mixers will exist. Even harmonics, both at the LO and the input of the mixers can be neglected if a fully balanced configuration is used. Therefore, all the harmonics of VCO (n�f1) will mix with all the harmonics of input (m�f2), where f2 is equal to f1/N. Because of the quadrature mixing, at each upconversion only one sideband appears at the mixer output. Upper or lower sideband rejection depends on the phase of the input and LO at each harmonic. For instance, for the main harmonics mixed with each other, the lower sideband is rejected, whereas when the main harmonic of the VCO mixes with the third harmonic of the divider output signal, the upper sideband is rejected. Table 1 gives a summary of the cross modulation products up to the 5th harmonic of the VCO and input. In each product, only one sideband is considered, since the other one is attenuated due to quadrature mixing, and is negligible.
1st:f1/N
3rd:3f1/N
5th:5f1/N
1st:f1 f1 � (1 + 1/N)
3rd:3f1 f1 � (3 − 1/N)
5th:5f1 f1 � (5 + 1/N)
Cos(ω1t)�Cos(ω1t)−Sin(ω1t)−Sin(ωt)→Cos(2ω1t) (45)andCos(ω1t)�Sin(ω1t)+Sin(ω1t)�Cos(ω1t)→Sin(2ω1t) (46)
 H ⁡ ( f )  = f Q ⁢ ⁢ f 0 [ 1 - ( f f 0 ) 2 ] 2 + ( f Q ⁢ ⁢ f 0 ) 2 ( 49 ) The following discussion changes based on the Q value. Considering a Q of about 5 for the inductor, with f0=1.5f1, the spur located at 2.5f1 is rejected by about 15 dB by each LC a circuit. This spur is produced at the LO generator output due to the mixing of the VCO third harmonic (at 3f1) with the divider output (at 0.5f1). This signal is attenuated by 10 dB since the third harmonic of a square-wave is one third of the main harmonic, 15 dB at the LC resonator at the mixers output tuned to 1.5f1, and another 15 dB at the output of the buffers 893, 895 in FIG. 33). This gives a total rejection of 40 dB. When applied to the mixers in the transmitter, this LO genemtor output will upconvert the baseband data to 2.5f1. With LC filters (not shown) positioned at the upconversion mixers and PA output in the transmitter, another 15+15=30 dB rejection is obtained (FIG. 33). The spur located at 0.5f1 is produced because of the third harmonic of the divider output (at 1.5f1) is mixed with the VCO output (at f1). Because of the hard switching action at the divider output, the third harmonic is about 10 dB lower than the main harmonic at 0.5f1. The buffer at the divider output tuned to 0.5f1 (891, 894 in FIG. 33), rejects this signal by about 22 dB (equation (24)). This spur can be further attenuated by LC circuits at the mixer and its buffer output by (2)(22)=44 dB. The total rejection is 76 dB.
FIG. 33( a) shows a signal passing through a limiting buffer 912 (such as the buffers implemented in the LO generator). When a large signal at a frequency of f accompanied with a small interferer at a frequency of Δf911 away pass through a limiting buffer, at the limiter output the interferer produces two tones �Δf914, 916 away from the main signal, each with 6 dB lower amplitude. Therefore, the spur at 2.5f1 will actually be 10+15+15+6=46 dB attenuated when it passes through the buffer, instead of the 40 dB calculated above. It will also produce an image at 0.5f1 which is 10+15+22+6=53 dB lower than the main signal. This will dominate the spur at 0.5f1 because of the third harmonic of the divider mixed with the VCO signal, which is more than 75 dB lower than the main signal. Since the buffer is nonlinear, another major spur at the LO generator output is the third harmonic of the main signal located at 3�1.5f1. This signal will be 10+22=32 dB lower than the main harmonic. The 22 dB rejection results from an LC circuit (not shown) tuned to 1.5f1 (equation (49)) in the buffer. This undesired signal will not degrade the LO generator performance, since even if a perfect sinewave is applied to upconversion (or downconversion) mixers, due to hard switching action of the buffer, the mixer is actually switched by a square-wave whose third harmonic is only 10 dB lower. Thus, if a nonlinear PA is used in the transmitter, even with a perfect input to the PA, the third harmonic at the transmitter output willbe 10+22+10=42 dB lower. The first 10 dB is because the third harmonic of a square-wave is one third of the main one, the 22 dB is due to the LC filter at the PA output, and the last 10 dB is because the data is spread in the frequency domain by three times. Any DC offset at the mixer input in the transmitter is upconverted by the LO, and produces a spur at f1. This spur can be attenuated by 13 dB for each LO circuit used (equation (49)). In addition, the signal at the mixer input in the transmitter is considerably larger (about 10�20 times) than the DC offset. Thus the spur at f1 will be about 13+13+26=52 dB lower than the main signal. All other spurs given in Table 1 are more than 55 dB lower at the LO generator output. The dominant spur is the one at 2.5f1 which is about 46 dB lower than the main signal.
V out � l=Cos(ω2 t)�Cos(ω1 t+θ)−Sin(ω2 t)�Sin(ω1 t) (50)and V out � Q=Cos(ω2 t)�Sin(ω1 t)+Sin(ω2 t)�Cos(ω1 t+θ) (51)
V out_I = - Sin ⁡ ( θ 2 ) � Sin ⁢ ⁢ ( ( ω 1 - ω 2 ) ⁢ t + θ 2 ) + Cos ⁡ ( θ 2 ) � Cos ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 2 ) ( 52 ) and
V out_Q = - Sin ⁡ ( θ 2 ) � Cos ⁢ ⁢ ( ( ω 1 - ω 2 ) ⁢ t + θ 2 ) + Cos ⁡ ( θ 2 ) � Sin ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 2 ) ( 53 ) The above equations show that regardless of the value of θ, the outputs are always in quadrature. However, other effects should be evaluated. First, a spur at ω1−ω2=0.5ω1 is produced at the output. This spur can be attenuated by 2�22=44 dB by the LC filters at the mixer and its buffer outputs. Thus, for 60 dB rejection, the single sideband mixers need to provide an additional 16 dB of rejection (about 0.158). Based on equation (53), tan(θ/2)=0.158, or θ≈18�, phase accuracy of better than 18� can generally be achieved. Second, phase error at the VCO output lowers the mixer gain (term Cos(θ/2) in equation (52) or (53)) For a phase error of 18�, the gain reduction is, however, only 0.1 dB, which is negligible. For θ=90� (a single-phase VCO), both sidebands are equally upconverted at the mixer output. However, the LC filters reject the lower sideband by about 44 dB. The mixer gain will also be 3 dB lower. This will slightly increase the power consumption of the LO generator. If θ=180� (the VCO I and Q outputs are switched), the lower sideband is selected, and the desired sideband is completely rejected.
V out_I = - Sin ⁢ ⁢ ( θ 1 - θ 2 2 ) � Sin ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 1 - θ 2 2 ) + Cos ⁡ ( θ 1 + θ 2 2 ) � Cos ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 1 + θ 2 2 ) ( 54 ) and
V out_Q = - Sin ⁢ ⁢ ( θ 1 + θ 2 2 ) � Cos ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 1 - θ 2 2 ) + Cos ⁢ ⁢ ( θ 1 - θ 2 2 ) � Sin ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 1 + θ 2 2 ) ( 55 ) This shows that the outputs still have phases of 0 and 90�, but their amplitudes are not equal. The amplitude imbalance is equal to:
Δ ⁢ ⁢ A A = 2 ⁢ ⁢ Cos ⁡ ( θ 1 + θ 2 2 ) - Cos ⁡ ( θ 1 - θ 2 2 ) Cos ⁢ ⁢ ( θ 1 + θ 2 2 ) + Cos ⁡ ( θ 1 - θ 2 2 ) = 2 ⁢ ⁢ tan ⁢ ⁢ ( θ 1 2 ) � tan ⁡ ( θ 2 2 ) ( 56 ) If θ1 and θ2 are small and have an equal standard deviation, that is, the phase errors in the VCO and divider are the same in nature, then the output amplitude standard deviation will be:
Phase errors in the divider can originate from the mismatch at its output. Moreover, for N=2, if the input of the divider does not have a 50% duty cycle, the outputs will not be in quadrature. Again, the deviation from a 50% duty cycle in the divider input signal may be caused due to mismatch. Typically, with a careful layout, this mismatch is minimized to a few percent. The latter problem can also be alleviated by improving the common-mode rejection of the buffer preceding the divider (888 in FIG. 33). One possible way of doing so is to add a small resistor at the common tail of the inductors/in the buffer. For a differential output, this resistor does not load the resonator at the buffer output, since the inductors common tail is at AC ground. A common-mode signal at the output is suppressed however, since this resistor degrades the LC circuit quality factor. The value of the resistor should be chosen appropriately so as not to produce a headroom problem in the buffer.
FIG. 34 shows a block diagram of the wide tuning range VCO comprising two coupled oscillators where the amount of coupling transconductance is variable. The wide tuning range VCO comprises two resonators 800, 802 and four transconductance cells, gm cells 804, 806, 807, 805. The transconductance cells are drivers that convert voltage to current. The transconductance cells used to couple the oscillators together have a variable gain. The first VCO 800 provides the I signal and the second VCO provides the Q signal. The output of the first VCO 800 and the output of the second VCO 802 are coupled to transconductance cells 806, 807, respectively, combined, and fed back to the first VCO 800. The transconductance cell 807 used for feeding back the output of the second VCO to the first VCO is a programable variable gain cell. Similarly, the output of the second VCO 802 and the output of the first VCO 800 are coupled to transconductance cells 805, 804, respectively, combined, and fed back to the second VCO 802. The transconductance cell 804 used for feeding back the output of the first VCO to the second VCO is a programmable variable gain cell. The gain of the programmable variable gain transconductance cells 804, 807 can be digitally controlled from the controller.
Transistors 818 and 820 form a cross-coupled pair that injects a current into tank #1 in which the current through the transistor 818 is exactly 180 degrees out of phase with the current in the transistor 820. Likewise, transistors 822 and 824 form a cross-coupled pair that injects a current into tank #2 in which the current through the transistor 822 is exactly 180 degrees out of phase with the current in the transistor 824. The first set of coupling devices 834, 836 injects a current into tank #1 that is 90 degrees out of phase with current injected respectively by the transistors 818, 820. The second set of coupling devices 838, 840 injects a current into tank #2 that is 90 degrees out of phase with the current injected respectively by the transistors 822, 824. The tank impedances cause a frequency dependent phase shift. By varying the amplitude of the coupled signals, the frequency of oscillation changes until the phase shift through the tanks results in a steady-state solution. Varying the bias of the current source controls the gm of the coupling devices. Current sources 812, 816 provide control ofVCO tuning. Current sources 810, 814 provide segmentation of the VCO tuning range.
FIG. 36( a) shows the typical tuning curve of the wide tuning range VCO before and after segmentation. The horizontal axis is voltage. The vertical axis is frequency. FIG. 36( b) shows how segmentation is used to divide the tuning range and linearize the tuning curve. The linear tuning curves correspond to different VCO segments. The slope of the linear tuning curves is a result of VCO tuning. The horizontal axis is voltage. The vertical axis is frequency.
The controller performs adaptive programming and calibration of the receiver, transmitter and LO generator (see FIG. 2). An exemplary embodiment of the controller in accordance with one aspect of the present invention is shown in FIG. 38. A control bus 17 provides two way communication between the controller and the external processing device (not shown). This communication link can be used to externally program the transceiver parameters for different modulation schemes, data rates and IF operating frequencies. In the described exemplary embodiment, the external processing device transmits data across the control bus 17 to a bank of addressable registers 900�908 in the controller. Each addressable register 900�908 is configured to latch data for programming one of the components in the transmitter, receiver LO generator. By way of example, the power amplifier register 900 is used to program the gain of the power amplifier 62 in the transmitter (see FIG. 2). The LO register 902 is used to program the IF frequency in the LO generator. The demodulator register 903 is used to program the demodulator for FSK demodulation, or alternatively in the described exemplary embodiment program the A/D converter to handle different modulation schemes. The AGC register 905 programs the gain of the programmable multiple stage amplifier when in the AGC mode. The filter registers 901, 904, 906 program the frequency and bandwidth of their respective filters.
The transmission of data between the external processing device and the controller can take on various forms including, by way of example, a serial data stream parsed into a number of data packets. Each data packet includes programming data for one of the transceiver components accompanied by a register address. Each register 900�908 in the controller is assigned a different address and is configured to latch the programming data in the each data packet where the register address in that data packet matches its assigned address.
The programming data from the addressable registers 900�908 and the calibration data from the RC calibration circuit 907 and the bandgap calibration circuit 908 are coupled to an output register 909. The output register 909 formats the programmability and calibration data into a data packets. Each data packet includes a header or preamble which addresses the appropriate transceiver component. The data packets are then transmitted serially over a controller bus 910 to their final destination. By way of example, the output register 909 packages the programming data from the power amplifier register 900 with the header or preamble for the power amplifier and outputs the packaged data as the first data packet to the controller bus 910.
Finally, the output register 909 can configure additional data packets from the output of the RC calibration circuit 907 and, in separate data packets, the output of the bandgap calibration circuit 908 with appropriate headers or preambles.
FIG. 39 shows an exemplary RC calibration circuit in accordance with an embodiment of the present invention. The calibration circuit uses the reference clock from the LO generator to generate a 4-bit control word using a compare=and=increment loop until an optimum value is obtained. The 4-bit control provides an efficient technique for calibrating the RC circuits of the transceiver with a maximum deviation from its optimal value of only 5%.
FIG. 40 shows an exemplary embodiment of the RC calibration circuit using polyphase filtering. The RC calibration circuit uses the reference clock from the LO generator to adjust the RC value in two polyphase filters 280, 282 in successive steps until an optimum value has been selected. In this process, the two polyphase filters 280, 282 provide signal rejection that is dependent upon the value of w=(RC)−1 to which they are tuned by control logic 286. Initially, the first filter (Polyphase A) 280 is tuned to a frequency less than the frequency of the reference clock (reference frequency), and the second filter (Polyp hase B) 282 is tuned to a frequency greater than the reference frequency by control logic 286. The signals at the outputs of the polyphase filters are detected with a received-signal-strength-indicator (RSSI) block 284, 285 in each path. Polyphase A filter is coupled to RSSI block 284 and the polyphase B filter is coupled to RSSI block 285.
With an input dynamic range of 50 dB, the RSSI circuit is designed to detect the levels of rejection provided by the polyp hase filtering. The outputs of RSSI block 284 and RSSI block 285 are coupled to a comparator 288 where the level of signal rejection of each polyphase filter is compared by comparator 288. The outputs of the RSSI blocks are also coupled to the control logic 286. The control logic 286 determines from the RSSI outputs whichpolyphase filter has a lower amount of signal suppression. Then, the control logic 286 adjusts the frequency tuning of that filter in an incremental step via the control logic 286. This is done by either increasing the tuned frequency of the first filter (polyphase A) filter 280, or by decreasing the tuned frequency of the second filter (polyphase B) 282 by changing the appropriate 4-bit control word. This process continues in successive steps until the 4-bit control word in each branch are identical, at which point, the RC values of the two polyphase filters are equal. The 4-bit control word provides a maximum deviation of only �5%.
The switches can be binary-weighted in size and the switch sizes can be chosen according to tradeoffs regarding parasitic capacitances and frequency limitations based on the on-resistance of the CMOS switches. The capacitive error resulting from the parasitic capacitance in each capacitive array does not result in frequency error between the three polyphase stages of the RC calibration circuit in the controller. This is achieved by using the same capacitor array in each filter, and by scaling the resistance accordingly in each case. Scaling resistances, relative to those in the fundamental polyp hase filter, by factors of ⅓ and ⅕ in the 3rd and 5th harmonic filters respectively, are achieved with a high degree of accuracy with proper layout. Similarly, RC tuning in all other blocks utilizing the calibrated code is optimized when an identical capacitive array is used, scaling only the resistance value in tuning to the desired frequency. The capacitors inthe capacitive arrays are laid out in 100 fF increments to improve the matching and parasitic fringing effects.
FIG. 42 shows an exemplary embodiment of the bandgap calibration circuit. The bandgap calibration circuit uses the reference clock provided from the LO generator and a reference resistor RREF 236 to adjust a tunable resistance value RPOLY 238 in a compare-and-increment loop until an optimum value is obtained. In embodiments of the present invention which are integrated into a single IC, the reference resistor RREF 236 can be off-chip to provide improved calibration accuracy. A 4-bit control word is output to accurately calibrate the resistors in the transmitter, receiver and LO generator within �2%. Transistors 224, 226, 228, 230, 232, 234 form a cascode current with a reference current IREF. The transistors 224, 230 each have their gates tied to their respective sources to set up the reference current IREF. By tying the gates of the transistors 224, 230, respectively to the gates of the transistors 226, 232, the reference current IREF is mirrored to the reference resistor RREF 236. Similarly, by tying the gates of the transistors 228, 234, respectively to the gates of the transistors, the reference current IREF is also mirrored to the tunable resistor RPOLY 238. The voltage generated across the tunable resistor RPOLY 238 is compared, using a latched comparator 240, to the voltage generated across the reference resistor RREF 236. The value of the tunable resistor RPOLY 238 is incremented in successive steps, preferably, every 0.5 μs, through the utilization of control logic 242 that is clocked, by way of example, at 2 MHz. This process continues until the voltage VP0LY across the tunable rcsistor RPOLY 238 matches the voltage VREF across the off chip reference resistor RREF 236 causing the output of the comparator to change states and disable the control logic 242. Once the control logic is disabled, the 4-bit control word can be used to accuratcly calibrate the resistors in the transmitter, receiver and LO generator.
The bandgap calibration circuit can be used for numerous applications. By way of example, FIG. 43 shows a bandgap calibration circuit 244 used in an application for calibrating a bandgap reference current that is independent oftemperature. The 4-bit control word from the bandgap calibration circuit is coupled, by way of illustration, to the receiver. The 4-bit control word is used to calibrate resistances in a proportional-to-absolute-temperature (PTAT) bias circuit 246, and also in a VBE (negative temperature coefficient) bias circuit 248. The outputs of these blocks are two bias voltages, VP 250 and VN, 252 that generate currents exhibiting a positive temperature coefficient, and a negative temperature coefficient, respectively. When these currents are summed together using the cascode current mirror formed by transistors 254, 256, 258, 260, the resultant current IOUT displays a (ideally) zero temperature coefficient.
In the transmitter, receiver and LO generator non-silicided polysilicon resistors can be used. As those skilled in the art will appreciate, other resistor technologies can also be used. Non-silicided polysilicon resistors have a high sheet resistance of 200-Ω/square along with desirable matching porperties. A switching resistor array as shown in FIG. 44 can be used to calibrate a resistor. The array includes serial connected resistors 208, 210, 212, 214, 216, which, by way of example, have resistances of 2200Ω, 1100Ω, 550Ω, 275Ω, and 137Ω, respectively. The resistors 210, 212, 214, 216 include a bypass switch for switching the resistors in and out of the array. The switch positions are nominally selected to produce an equivalent of 3025Ω. This resistance value has been chosen as a convenience to match the value used in generating an accurate bandgap reference current. A 4-bit calibration code is used to control the total resistance in this array. As seen in FIG. 44, the resistances are binary-weighted in value and the accurate scaling of each incremental resistance results by placing the largest resistor (2200Ω) 208 in series to generate each value. In the described embodiment, the incremental resistances shown in FIG. 44 are chosen so that the total resistance in the array covers a range 30% above and below its nominal value, with a maximum resistance error of +2% determined by the incremental resistance switched by the LSB. The range of resistance covered by the array is sufficient to cover typical process variations in a semiconductor process. A series resistive array may be desirable as opposed to a parallel resistive array because of the smaller area occupied on the wafer.
FIG. 45 is a block diagram of the Floating MOS capacitor in accordance with an embodiment of the present invention. As shown in FIG. 45, the capacitor comprises two similar devices 858, 859 in series. Each MOS transistor has its source and drain connected together. The connected drain-source terminal of the MOS transistor 858 constitutes the input of the CMOS capacitor and the connected drain-source terminal of the MOS transistor 859 constitutes the output of the CMOS capacitor. The gates ofeachMOS transistor are connected through a common resistor 862 to a bias source (not shown).
Since the antenna is usually single-ended, differential applications generally require a mechanism to convert the antenna signal from single-ended to differential for connection to the differential low noise amplifier (LNA) or the differential PA. The circuit implementation for a single-ended to differential LNA is shown in FIGS. 46 and 47. LC circuit, 646,648 and the CL circuit 652, 650 matches the PA to the antenna when the PA is on and the LNA is off (as shown in FIG. 46), and matches the LNA to the antenna when the LNA is on and the PA is off (as shown in FIG. 47). When the LNA is off it only introduces a capacitive loading to the PA. The matching circuit can be designed to compensate for this additional capacitance.
In operation, during the transmit mode, a differential voltage across the drains of the PA transistors 634, 632 is generated. The two drains assert 180-degree out of phase voltages and they are combined through the LC and CL matching circuits to yield a single-ended voltage at the output. The LC circuit shifts the phase of the output signal from the transistor 632 by 90 degrees. The CL circuit shifts the phase of the signal output from the transistor 634 by 90 degrees inthe opposite direction. Consequently, both signals are in-phase when combined at the output of the matching circuits.
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Classification455/75, 455/323, 455/84International ClassificationH03H21/00, H03H11/12, H04B1/40Cooperative ClassificationH04B17/0012, H03J2200/10, H03H11/1291, H04B1/40, H04B1/30, H04B17/0027, H03H21/0001, H03H21/0012, H03H2011/0494, H04B17/0037, H03B21/01European ClassificationH04B1/40, H04B1/30, H03B21/01, H04B17/00A3S, H04B17/00A1T, H04B17/00A2S, H03H11/12F, H03H21/00A, H03H21/00BLegal EventsDateCodeEventDescriptionNov 12, 2013SULPSurcharge for late paymentYear of fee payment: 7Nov 12, 2013FPAYFee paymentYear of fee payment: 8Oct 2, 2009FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google