Source: http://www.google.com/patents/US5880967?dq=6101531
Timestamp: 2017-01-19 19:48:36
Document Index: 709898261

Matched Legal Cases: ['art 600', 'arts 600', 'arts 600', 'art 600', 'art 600', 'art 600', 'art 1100', 'art 1100']

Patent US5880967 - Minimization of circuit delay and power through transistor sizing - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method for minimizing signal delay and power consumption is provided. Through combined power simulation and delay analysis, iterative transistor resizing is performed based on a variety of factors including relative delay of associated circuit paths, nodal switching activities and association of transistors...http://www.google.com/patents/US5880967?utm_source=gb-gplus-sharePatent US5880967 - Minimization of circuit delay and power through transistor sizingAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS5880967 APublication typeGrantApplication numberUS 08/431,988Publication dateMar 9, 1999Filing dateMay 1, 1995Priority dateMay 1, 1995Fee statusPaidAlso published asUS6209122Publication number08431988, 431988, US 5880967 A, US 5880967A, US-A-5880967, US5880967 A, US5880967AInventorsHenry Horng-Fei Jyu, An-Chang DengOriginal AssigneeSynopsys, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (14), Non-Patent Citations (70), Referenced by (114), Classifications (9), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetMinimization of circuit delay and power through transistor sizing
US 5880967 AAbstract
1. In a programmed digital computer, a method of minimizing signal delay and power consumption of a selected circuit, wherein the selected circuit includes a plurality of circuit paths constructed from transistors and nodes, said method comprising the steps of:determining a time delay of each path in said selected circuit, wherein a time delay of greatest value is associated with a critical path of said selected circuit; selecting a first transistor, said first transistor residing in a first path in said selected circuit having a first time delay; simulating operation of said selected circuit; counting state switches of a first node of said selected circuit during said simulation step, said first node being coupled to said first transistor; and resizing said first transistor based upon a number of state switches occurring at said first node, wherein said resizing step includes the steps of:sizing up said first transistor when said first time delay normalized to the time delay of greatest value exceeds a predetermined threshold value; and sizing down said first transistor when said first time delay normalized to the time delay of greatest value is less than said predetermined threshold value. 2. The method of claim 1 further comprising the steps of:estimating wiring capacitance of said first node in said selected circuit based upon fanin and fanout and area of said first node. 3. The method of claim 1 further comprising the step of:inputting a netlist of an original circuit into said computer, said original circuit including a plurality of circuit paths and transistors included in these paths; generating a scaling circuit from said netlist of said original circuit, said scaling circuit having transistor widths that are scaled values of transistor widths in said original circuit; generating a changing circuit from said netlist of said original circuit, said changing circuit having transistor widths that are uniform; and choosing said selected circuit from said original, scaling and changing circuits based on user-selected criteria. 4. The method of claim 3 wherein said user-selected criteria is power consumption of said original, scaling and changing circuits.
5. The method of claim 3 wherein said user-selected criteria is a cost function based on power, delay and area of said original, scaling and changing circuits.
6. The method of claim 3 wherein said user-selected criteria is delay of said original, scaling and changing circuits.
7. In a programmed digital computer, a method of minimizing signal delay and power consumption of a selected circuit, wherein the selected circuit includes a plurality of circuit paths constructed from transistors and nodes, said method comprising the steps of:determining a time delay of each path in said selected circuit, wherein a time delay of greatest value is associated with a critical path of said selected circuit; identifying all transistors that are channel connected in a pseudo gate within said selected circuit; determining an average ratio value associated with said pseudo gate based on individual ratio values associated with each of said all transistors, said ratio value being a function of time delays associated with one or more circuit paths; assigning said average ratio value to each of said all transistors in a data structure stored in a computer-readable medium; and resizing each of said all transistors using said average ratio value. 8. The method of claim 7 wherein said average ratio value comprises an average p-type ratio value and an average n-type ratio value and wherein said determining step comprises the steps of:determining an average p-type ratio value derived from individual ratio values associated with each of said all transistors that are p-type transistors; and determining an average n-type ratio value derived from individual ratio values associated with each of said all transistors that are n-type transistors, said p-type and n-type ratio values being functions of time delays associated with one or more circuit paths. 9. The method of claim 7 wherein said data structure comprises an array of transistor parameter records, each of said parameter records including a plurality of fields containing data.
10. The method of claim 7 further comprising the step of:inputting a netlist of an original circuit into said computer, said original circuit including a plurality of circuit paths and transistors included in these paths; generating a scaling circuit from said netlist of said original circuit, said scaling circuit having transistor widths that are scaled values of transistor widths in said original circuit; generating a changing circuit from said netlist of said original circuit, said changing circuit having transistor widths that are uniform; and choosing said selected circuit from said original, scaling and changing circuits based on user-selected criteria. 11. The method of claim 10 wherein said user-selected criteria is a cost function based on power, delay and area of said original, scaling and changing circuits.
12. The method of claim 10 wherein said user-selected criteria is power consumption of said original, scaling and changing circuits.
13. The method of claim 10 wherein said user-selected criteria is delay of said original, scaling and changing circuits.
14. In a programmed digital computer, a method of minimizing circuit signal delay and power consumption comprising the steps of:inputting into said computer a netlist of a first circuit, said first circuit including a plurality of circuit paths constructed from transistors and nodes; generating a second circuit based on a modification of transistor size in said first circuit; selecting a chosen circuit between said first and said second circuits based on circuit performance; resizing a first transistor in said chosen circuit based on path delay; performing a static timing analysis and power simulation of said chosen circuit; and terminating transistor resizing when performance degradation exceeds a predetermined threshold. 15. The method of claim 14 wherein said predetermined threshold is based on a composite value of normalized power, delay and area values.
16. The method of claim 14 wherein said resizing step is further based on a number of state switches occurring at a node coupled to said first transistor.
17. The method of claim 14 wherein said resizing step includes the steps of:determining a time delay of each path in said chosen circuit, wherein said first transistor resides in a select path having a select time delay and a critical path of said chosen circuit has a time delay of greatest value; sizing up said first transistor when said select time delay normalized to the time delay of greatest value exceeds a predetermined threshold value; and sizing down said first transistor when said select time delay normalized to the time delay of greatest value is less than said predetermined threshold value. 18. The method of claim 14 wherein said resizing step includes selecting a cell from a predefined cell library.
19. The method of claim 14 wherein said resizing step includes:identifying all transistors that are channel connected with said first transistor in a pseudo gate; determining an average ratio value associated with said pseudo gate based on individual ratio values associated with each of said all transistors, said ratio value being a function of time delays associated with one or more circuit paths; assigning said average ratio value to each of said all transistor in a data structure stored in a computer-readable medium; and resizing each of said all transistors using said average ratio value. 20. The method of claim 19 wherein said data structure comprises an array of transistor parameter records, each of said parameter records including a plurality of fields containing data.
U.S. Patent Applications for "TRANSISTOR-LEVEL TIMING AND POWER SIMULATOR AND POWER ANALYZER," Ser. No. 08/040,531 filed Mar. 29, 1993, and "POWER DIAGNOSIS FOR VLSI DESIGNS," Ser. No. 08/231,207 filed Apr. 21, 1994, are hereby expressly incorporated by reference in their entirety for all purposes.
A Paper Appendix of a source code listing of an embodiment of the invention comprising 104 sheets has not been printed, but can be found in the application file wrapper. The Appendix includes source code for "amps", "amps-- d" and "spice2e".
In digital design, the delay of a MOS circuit is determined by the delay of the critical path, which can be computed from the summation of the delays of stages along this path (each stage is separated by the gate of a MOS transistor), as represented by Equation 1 (EQ 1): ##EQU1## Ri is the conducting resistance of the transistor along the path that drives node i. Ci is the node capacitance of node i. For a transistor, the conducting resistance is inversely proportional to the width of the transistor gate while the terminal capacitance is proportional to the width of the gate. Increasing the transistor width can reduce the resistance of this transistor, and thus reduce the delay of this stage. However, it also increases the loading capacitance of the previous stage, which increases the delay of the previous stage.
Regarding power, Equation 2 (EQ 2) is widely adopted in estimating the power consumption of a circuit: ##EQU2## Vdd is the power supply voltage, f is the clock frequency, and Pi is the toggling probability of node i in a clock cycle (i.e., Pi indicates probability of a delay in a particular gate toggling from one logic state to another due to the delay of an input). With respect to capacitance, it seems straightforward that reducing the transistor sizes can reduce the power. However, since toggling probability heavily depends on the transistor delays, reducing capacitance alone does not necessarily reduce the power. In addition, Equation 2 only considers the charging/discharging power consumed in the capacitors. It does not capture the DC leakage and short-circuit power, which is significant for some types of circuits.
Most previous transistor autosizers focus on reducing transistor delay and area. (See, for example, J. Fishburn et al., "TILOS: A Posynomial Programming Approach to Transistor Sizing," Proceedings of the International Conference on Computer-Aided Design, pages 326-328 (1985) ("Fishburn"); K. Hedlund, "Electrical Optimization of PLAs," Proceedings of the Design Automation Conference, pages 681-687 (June 1985); A. E. Ruehli et al., "Analytical Power/Timing Optimization Technique for Digital System," Proceedings of the Design Automation Conference, pages 142-146 (June 1977); and U.S. Pat. No. 4,827,428 issued to Dunlop et al. Some approaches use area as a first-order estimation for power. Due to the correlation between delay and power, however, reducing area does not necessarily reduce the power.
To guarantee an optimal solution, a true convex programming approach for transistor sizing is proposed. See, S. Sapatnekar et al., "An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization," IEEE Transactions on Computer-Aided Design, pages 1621-1634, Vol. 12 (11) (November 1993). However, the intractability of convex programming makes it difficult to apply to large circuits and complex device models.
To overcome the efficiency and convergence problems of convex programming, a linear programming approach has been proposed. M. Berkelaar et al., "Computing the Entire Active Area/Power Consumption versus Delay Trade-Off Curve for Gate Sizing with a Piecewise Linear Simulator," Proceedings of the International Conference on Computer-Aided Design, pages 474-480 (November 1994). This approach represents design criteria in terms of linear equations and constraints as linear inequalities. A problem with this approach is that the delay and power of a transistor is not ideally a linear equation of its size. Modifications to this approach that ignore nonlinear effects and incorporate piece-wise linear approximation have been proposed. These modifications will decrease precision and increase the number of constraints.
In one aspect of the present invention, a method of minimizing signal delay and power consumption of a circuit that includes circuit paths constructed from transistors and nodes includes the steps of: determining a time delay of each path in the circuit, wherein a time delay of greatest value is associated with a critical path of the circuit; selecting a first transistor, the first transistor residing in a first path in the circuit having a first time delay; sizing up the first transistor when the first time delay normalized to the time delay of greatest value exceeds a predetermined threshold value; and sizing down the first transistor when the first time delay normalized to the time delay of greatest value is less than the predetermined threshold value.
FIG. 6 and FIGS. 6a-6d are flow charts describing initial circuit search and select operation;
FIGS. 7a-7c illustrate data structures of netlist transistors and nodes;
FIGS. 11a and 11b together display a flow chart describing ratio value determination;
FIGS. 11c and 11d is source code illustrating calculation of scale-- up, scale-- down and threshold values;
FIG. 14 shows pseudo code describing stop-- check operation;
FIG. 17 is a flow chart describing "leakage-- fix" configuration command;
Transistor autosizing system 1 is shown embodied in one type of computer system. The particular computer system shown is representative only. Other types of computer systems suitable for use in the present invention include so-called "notebook," "palmtop" or "hand-held," "patent top," etc., computers. Further, the use of the term "mouse" or "user input device" is understood to include other means for inputting information into a computer such as a touch screen, track ball, MIDI keyboard, light pen, data glove, etc. It will be readily apparent to one of ordinary skill in the art that many types of computer hardware, and configurations of the hardware, are suitable for use in conjunction with the present invention.
The preferred embodiment of the invention is written using the "C" language, and runs on UNIX™-based engineering workstations such as SUN4, IBM RS6000, HP 700 series, and DECStations. Conforming to the ANSI standard on the "C" language, it can be readily rehosted on any UNIX-based computers with a standard "C" compiler. The flow charts of FIGS. 3-4, 6 and 11, pseudo code in FIGS. 12-14 and code in FIG. 15 describe operations implemented by the central processor 108 under appropriate process control and instruction from procedures stored in the system memory 107 provided as a part of transistor autosizing system 1.
The initial "search and select" operation of engine 320 is represented by initial search block 310, first run-core block 312 and initial select block 314. In block 310, up to two circuits (in addition to the original input circuit) may be derived from the netlist file 306 with varying transistor sizes. These three circuits (original and two derivations) are then forwarded to first run-core block 312 which generates, among other things, a delay and power report for each circuit. (A more detailed illustration of run-core blocks 312 and 316 is provided in FIGS. 4a and 4b, discussed below.) Based at least in part on this delay and/or power information, initial select block 314 typically chooses the optimal candidate (from the initial three circuits presented) as the starting circuit. However, select block 314 may derive an alternative circuit based on different transistor sizes if the three circuits presented exhibit poor performance and an improved alternative is readily apparent. In this case the alternative circuit is returned to block 314 via line 334 for delay and power analysis. After which, iterative processing is initiated to achieve specified design goals. Initial searching can save a considerable amount of time if the initial design is far from the optimal design.
FIG. 4a illustrates a flow chart for first run-core block 312. In brief, a netlist is input on line 402a initiating parallel power simulation and delay analysis. Power simulation requires that any control files (i.e., configuration files) be established in block 404a and power simulation be performed in block 406a. The output of this simulation 408a (i.e., circuit current, toggling activity for each node, identification of nodes with slow rise/fall time and identification of circuit paths coupling power and ground (dc-- path)) is forwarded to initial select block 314 (FIG. 3) for purposes of selecting an initial circuit.
Delay analysis requires that any control files (i.e., configuration files) be established in block 410a and delay analysis be performed in block 412a. The output of this analysis 414a (i.e., critical path delay, critical slack information and driving/loading conditions of each transistor) is also forwarded to initial select block 314 (FIG. 3) for purposes of selecting an initial circuit. Power simulation, delay analysis and selection of an initial circuit is discussed in greater detail below.
FIG. 4b illustrates a flow chart for second run-core block 316. In brief, block 316 functions the same as block 312 with respect to operations 404b-414b (which correspond directly to 404a-414a). However, block 316 also includes a transistor resizer block 416 and decision block 417 coupled to bypass line 420. Resizer block 416 processes the information provided by power simulator block 406b and delay analysis block 412b to generate new transistor sizes for the next iteration. These transistor sizes are output on line 418b. Transistor resizing is discussed in greater detail below.
Decision block 417 directs an initial circuit selected from initial searching modes "default" or "search" (discussed below) and associated power/timing data produced in block 312 on to bypass line 420. This information is forwarded directly to transistor resizer 416 since power simulation and delay analysis has already been performed in run-core block 312.
TABLE 1______________________________________File Name    Purpose______________________________________amps. c: init-- search        initial search and select run-- core        run core functionselect c: select-- start        select initial circuitpath-- amps. c: resize      transistor resizer ps-- adapt        modify scale-up, scale-down and threshold fix-- rf        calculate new ratios based on slow        rise/fall times output-- stw        output operationa-- misc. c: check-- stop        stop check operationsa-- cell. c: cell-- core        cell selection operation______________________________________
Netlist file 306 defines the circuit to be analyzed; it is constructed from system elements connected by input and output nodes to form a network. The wire connections between elements are referred to as "nets." The system connectivity is established through the common input, output, and biput I/O nodes among the circuit elements. An element can be a single transistor, resistor, capacitor, gate, register, functional model, stimulus function, global timing error function or output probing function.
Technology file 308 is a data file containing user-specified MOS parameters and SPICE generated characteristics (i.e., Vgs, Vds v. Ids) to create piece-wise linear MOS models for circuit simulation and analysis. Referring to FIG. 3, technology file 308 is created by gen-- tech 326, a utility which accesses data from control file 330 and interfaces directly with SPICE simulator 328 (running HSPICE, Pspice, PRECISE, SPECTRE, SPICE2, SPICE3 or SPECTRE2). The utility submits and invokes all the SPICE runs necessary to characterize CMOS technologies.
Control file 330 is divided into six sections: (1) typical-- case-- model, (2) parameter, (3) corner, (4) lib, (5) invoke, and (6) options. The typical-- case-- model section contains MOS transistor models for SPICE. The model parameters for both p and n channel transistor models are listed in this section. The "parameter" section includes values for a plurality of parameters which are identified in Table 2. The "corner" section specifies the voltage and temperature conditions for the process corner that the present technology file accounts for. The "lib" section allows the user to specify a SPICE model library to be used when running gen-- tech 326. The "invoke" section contains the user-specified command that invokes SPICE in the simulated environment. Finally, the "options" section contains the user-specified SPICE options that would normally appear in an .OPTIONS statement in a SPICE format. A description of the .OPTIONS statement is provided in P. W. Tuinenga, SPICE: A Guide to Circuit Simulation & Analysis Using PSpice, Prentice Hall (1992), which is hereby incorporated by reference in its entirety for all purposes.
TABLE 2______________________________________Parameter Definition______________________________________1.  body-- bias         The sampling source voltage values at         which the body bias effects are         measured. Maximum number of sampling         voltages is five.2.  pn-- ratio         The typical p-transistor width to n-         transistor width ratio used to insure         that inverters have equal rise and         fall intrinsic delays.3.  NW        A set of typical transistor widths         used in calibrations.4.  n-- length         The typical channel length of the n-         transistor. Maximum number of         lengths is ten.5.  p-- length         The typical channel length of the p-         transistor. Maximum number of         lengths is ten.6.  ds-- length         The typical drain-source extension.         The dimension is used in conjunction         with transistor widths to determine         the drain and source area and         perimeter for drain source diffusion         capacitance estimations during         simulation, if such geometries are         not provided. (Listed in the         technology file as diffext.)7.  ldiff/wdiff         Used to explicitly specify the         lateral diffusion for transistor         widths and lengths. The present         invention uses these to calculate the         effective width and length of each         transistor where:         Leffective = Ldrawn-2*ldiff         Weffective = Wdrawn-2*wdiff         Two numbers are associated with each         variable representing NMOS and PMOS         lateral diffusions. If these options         are not used, gen-- tech extracts the         lateral diffusion by running SPICE.8.  vds/vgs   Drain to source and effective gate to         source voltage ranges and their         incremental values are specified for         calibrating device currents.9.  thresholdmos         Specifies the zero bias threshold         voltage. Typically, this is read         from the SPICE model parameter VTO.         If it is desired to override this         parameter, or adjust it with respect         to temperature, or the parameter is         missing from the SPICE model, this         variable can be used to specify the         threshold voltage.10. vto       Species the threshold voltage for a         transistor at nominal temperature.         The threshold voltage is used to         calculate the body bias effect.______________________________________
There are four types of configuration commands used by transistor autosizing engine 320: "design constraints," "initial searching," "design goals" and "miscellaneous." (In the argument part of a configuration command, the following legends are used: f: floating number; i: integer; and c: character. These values are provided by the user.)
"Design constraints" commands define physical characteristics of the subject transistors and include the following:
max-- tx-- size f: the upper bound of transistor size, unit is micron (default is 100).
min-- tx-- size f: the lower bound of transistor size, unit is micron (default is 1).
grid-- size f: the grid(incremental) for tx size, unit is micron (default is 0.01).
"Initial searching" commands force certain limitations to the initial search of a circuit. As a default, transistor autosizing engine 320 (FIG. 3) will initially search three circuits (in blocks 310-314): the original (i.e., input) circuit, the original circuit proportionally scaled down to the smallest size ("default scaling circuit"), and the original circuit with all transistors at the smallest size ("default changing circuit"). However, initial searching commands "search" and "init" can alter this operation, as described below:
search f f: Force the size in auto-searching. As mentioned above, transistor autosizing engine 320 (FIG. 3) will search the original circuit, the smallest scaled-down circuit and the smallest circuit as a default. The "search" command, however, can force engine 320 to search a specific size rather than the smallest ones. The first number specifies the scaling factor, the second one specifies the absolute size.
For example, "search 2.2 11" will direct engine 320 to search the original circuit, the original circuit enlarged by a ratio of 2.2 ("user-specified scaling circuit"), and the original circuit with all transistors having the same width of 11 um ("user-specified changing circuit").
In addition, rather than performing multiple searches at the beginning, users can specify a particular starting circuit by invoking the "init" command: init c f:specify the initial point. This command is further described in Table 3.
TABLE 3______________________________________Init CommandValue of "c" ininit c &#402;         Operation______________________________________"c"           All the transistors ("txs") are changed to         the same size of &#402; micron."s"           All the txs are scaled by the same factor &#402;."i"           The original circuit -- this option does         not need &#402; argument. (Note: If there are         touch/no-- touch nodes (described below),         then the initial point can only be the         original circuit.)______________________________________
"Design goals" commands facilitate three execution modes of the transistor autosizing engine 320: requirement mode, cost-function mode and slack-driven mode (default is cost-function mode).
delay-- req f: f is a floating number, unit is ns.
power-- req f: f is a floating number, unit is mW.
In cost-function mode, the user can define the cost in terms of the sum or product of three criteria: power (p), delay (d) and area (a). The relative weight can be specified by coefficients for the sum or the exponents for the product. The p, d and a values have no units, they are ratios normalize to the power, delay and area of the initial circuit. The related configuration command is: cost-- fx+.linevert split.* fc fc fc:!. This command is further described in Table 4 (where * and signify multiplication and exponent, respectively):
TABLE 4______________________________________Cost function commandCost Function Command(Example)          Arithmetic Operation______________________________________cost-- fx + 1p 2d 3a              cost = p + 2*d + 3*a.cost-- fx + 2d              cost = p + 2*d + a              (default coefficient or              exponent values are 1)cost-fx * .5a 2d 1p              cost = p * d 2 * a .5______________________________________
Slack value=(Required output time)-(Actual arrival time)   (EQ 3)
______________________________________slacksource-- node    i1     i2     delay=0                        ;i1, i2 arrive time 0sink-- node           o1     delay=5                        ;o1 is required at time 5sink-- node           o2     delay=7                        ;o2 is required at time 7______________________________________
As noted above, transistor autosizing engine 320 also uses a set of "miscellaneous" configuration commands to more specifically control the transistor sizing operation. These commands are briefly described below.
1. wire-- cap-- est {on/off}:
This command turns on and off an estimation for wire delays. If no argument is specified, the command defaults to "on." For example, "wire-- cap-- est off" turns off the wire estimation so there is no extra capacitance at each node to account for the wiring load. The estimation formula (described below) takes into account the number of input/output pins and the area of elements connected to the nodes (i.e., the larger the elements and the more connecting pins the longer the wires).
2. node-- switch {on/off}:
This command turns on and off a node switching "weight" in transistor sizing. If no argument is specified, the command defaults to "on." By turning this option on, node switching activities will be taken into account during transistor sizing. That is, the transistors connected to a highly switching node will be kept smaller to reduce the power consumption at that node (default is "on"). (Note: If the power simulation is not very comprehensive, it is better to turn this option off to avoid bias switching information.)
3. size-- level {gate/pn}:
This command resizes the transistor at the "pseudo-gate" level. The pseudo-gates are defined from the transistor netlist as all transistors that are channel-connected to each other. (This definition is a little different from conventional gates if pass transistors and transmission gates are present.)
When the argument of the size-- level command is "gate," the transistors inside a gate will be resized all together by the same ratio. However, when the argument is "pn," the p transistors inside a gate will be resized all together by the same ratio, and the n transistors inside the gate will be resized by the another ratio. When this command is absent from the configuration file, transistor resizing occurs at the transistor level.
4. rf-- fix f:
Since short-circuit current is related to the transition time of the transistor, reducing the rise/fall time can improve the leakage power. Using information generated from power simulation (see below), problematic nodes with slow rise/fall time can be located. The pull-up or pull-down transistors which drive these nodes may then be sized up to reduce both power and delay. As shown in FIG. 26, a circuit with minimal size does not necessarily consumes less power due to the significant percentage of leakage power. FIG. 25 shows the combined effects of transistor widths on delay and power. The rf-- fix command is discussed below.
5. max-- loop i:
6. degrade-- thresh f:
Searching for the smaller circuits is performed as a default if the user does not specify transistor sizes for the initial circuit. The user can also specify a different set of searching circuits by the "search" command, described above. If the user already knows that the initial circuit is very close to the smallest size and the delay requirement is critical, then it is better to force engine 320 to search larger circuits to improve efficiency.
For example, as shown in FIG. 7a, transistor data structures are constructed from an array of transistor parameter records (i.e., 702a-708a). Each transistor parameter record is associated with a particular transistor and contains a variety of fields, such as transistor width 736; transistor type (i.e., p or n) 738; identification of source 744, drain 742 and gate 740 terminal nodes, etc. Similarly, as shown in FIG. 7b, data structures containing an array of nodal parameter records are created for netlist nodes (i.e, 702b-708b). Each nodal parameter record contains a variety of fields, such as a sequential number (unique number assigned to each node) 746; a flag indicating membership within a set of channel-connected transistors 748; total nodal capacitance 750; present nodal voltage 752; etc. Such data structures are accessed during power simulation (406a or 406b) and delay analysis (412a or 412b) for carrying out power simulations and timing analysis. A more detailed discussion of such data structures used by a particular power simulator is provided in U.S. patent application Ser. No. 08/040,531.
In addition to data structures for power simulator 406 and delay analyzer 412, an analogous data structure is generated for transistor resizer 416. Referring to FIG. 7c, transistor data structure 700c is constructed from an array of transistor parameter records 702c, 704c, 706c and 708c. Each transistor parameter record is associated with a single transistor and includes fields shown in FIG. 7c and described in Table 5; i.e., delay 710, slack 712, r 714, pre-- r 716, cg 718, cs 720, cd 722, cap 724, nextc 726, tr 728, stw 730, visited 732 and no-- touch 734. The significance of some of these fields is discussed in greater detail below.
TABLE 5______________________________________Transistor Parameters for Transistor Resizing______________________________________1.    delay:     Delay of path on which transistor resides            (path-- delay).2.    slack:     Slack of path (path slack).3.    r:         Resistance of transistor.4.    pre-- r:            Resistance of previous transistor.5.    cg, cs, cd:            Capacitance of three terminals of            transistor.6.    cap, nextc:            Capacitance of transistor and capacitance            of load.7.    tr:        Toggling rate.8.    stw:       Ratio for new transistor size.9.    visited:1: Indicates whether transistor has already            been resized in the current iteration.10.   no-- touch:1:            Enables user to exclude transistor from            resizing operation. (Transistor            autosizing engine 320 (FIG. 3) will            evaluate every transistor in a given            circuit for resizing in accordance with            the operation discussed herein. However,            if the no-- touch bit for a particular            transistor is set (by the user), this            transistor is excluded from consideration            and remains unchanged.)______________________________________
After completing preprocessing, stimulus file 302 (FIG. 3) is loaded into system memory 107 in block 614, and initial searching begins. In decision block 616, a configuration file (loaded in block 610) is checked for the "search" configuration command. If present, transistor autosizing engine 320 (FIG. 3) generates user-specified scaling and changing circuits (defined above) in block 618 by modifying the transistor width for each transistor in the input circuit. These width modifications are held in the transistor parameter records for power simulation and delay analysis (i.e., FIG. 7a).
For each circuit under consideration (i.e., original, scaling and changing) in block 618, first run-core block 312 performs power simulation and delay analysis (see FIG. 4a). The resulting information is then used to select the "best" initial circuit in block 630 subject to the configuration commands in file 304 (e.g., "design goals" and "design constraints" commands). Selection is controlled by the "design goals" commands in configuration file 304.
If the search mode is not selected, the configuration file is checked for the "init" configuration command in decision block 622. If present, transistor autosizing engine 320 (FIG. 3) modifies the input circuit in block 624 by modifying a transistor width parameter held in associated transistor parameter records for each transistor in the input circuit. This modification is controlled by the init command arguments (i.e., c, s or i), as described above. The modified circuit then becomes the initial circuit in block 632.
Finally, if neither "search" nor "init" are specified in the configuration file, transistor autosizing engine 320 generates the smallest scaling and changing circuits (i.e., "default scaling circuit" and "default changing circuit") in block 626. As described above, these variations of the input circuit are achieved by modifying the transistor width for each transistor in the input circuit.
For each circuit under consideration (i.e., original, default scaling and default changing) in block 626, first run-core block 312 performs power simulation and delay analysis (see FIG. 4a). The resulting information is then used to select the "best" initial circuit in block 630 subject to the configuration commands in file 304 (e.g., "design goals" and "design constraints" commands). Selection is controlled by the "design goals" commands in configuration file 304.
As mentioned above and illustrated in FIG. 6, when operating in search mode (block 618) or default mode (block 626), an initial circuit must be selected in block 630 from at least three candidates. This selection is controlled by the "design goals" commands, which provide for three execution modes: requirement mode, cost-function mode and slack-driven mode. In general, the circuit associated with the "best" size for the controlling execution mode is chosen as the initial circuit and forwarded to second run-core block 316 (FIG. 3) in block 632 (FIG. 6).
For example, the execution report provided in FIG. 23 shows the results of an initial circuit selection based on a cost function (defined by addition). The initial circuits were created in the default mode. Although the initial circuit has the lowest cost (i.e., 7.000), "auto select" chose "change 2.24" as the initial circuit because of the clear potential for an improved cost function. In this instance, the delay element of the cost function had a relatively large coefficient (i.e., 5.0) thereby weighting the significance of this element in the cost analysis. Since both the scaling circuit ("S") and changing circuit ("C") resulted in smaller circuits, each experienced greater delay which pushed their respective cost-- fx values beyond that of the initial circuit ("Initial").
Selection of the initial circuit under cost-function mode is more clearly illustrated in flow chart 600a of FIG. 6a. Referring to FIG. 6a, in block 2702, it is determined whether the cost function (cost-- fx) of changing circuit (C) is less than or equal to the cost function of scaling circuit (S) and initial circuit (INIT). If yes, the changing circuit is selected in block 2704. If no, it is determined whether the cost function of the scaling circuit is less than or equal to the cost function of the changing circuit and the initial circuit in block 2706. If yes, the scaling circuit is selected in block 2708. If no, control flows to block 2710 which determines whether the ratio or scaling factor (stw) is relatively small (i.e., less than 1.001) and whether the delay coefficient (d) is critical. The delay coefficient is deemed critical if this value (i.e., d) divided by the summation of the power coefficient (p) and area coefficient (a) is greater than 2. If no, the initial circuit is selected in block 2712. If yes, operation flows to block 2714 which determines whether the cost function of the scaling circuit is less than or equal to the cost function of the changing circuit. If yes, the calculations as shown in FIG. 6a are carried out in blocks 2716, 2718 and 2720 to produce a scaling factor (stw) no greater than 3.0. In block 2722, the initial circuit is modified by the newly calculated scaling factor stw thereby creating a new scaling circuit. Finally, in block 2724, the scaling circuit is selected as the initial circuit.
For example, the execution report provided in FIG. 21 shows the results of an initial circuit selection based on the delay requirement mode. The initial circuits were created in the default mode. Although the initial circuit ("Initial") has the lowest delay, "auto select" chose "change 1.00" (i.e., the default changing circuit "C") as the initial circuit because it was in a predetermined margin of the required criteria (i.e., 4.0 ns) and had a clear potential for an improved delay. Other examples of initial searching selections are provided in FIGS. 20 and 22-24, discussed below.
Selection of the initial circuit under requirement mode is more clearly illustrated in flow charts 600b, 600c and 600d of FIGS. 6b, 6c and 6d, respectively. Referring to FIG. 6b, flow charts 600b illustrates the calculation of the predetermined margin. In block 2802, it is determined whether the number of transistors in the subject circuit are greater than 2000. If yes, the predetermined margin equals 1.18. If no, operation flows to block 2806 which determines whether the number of transistors in the subject circuit are greater than 100. If yes, the margin is calculated using linear interpolation where the number of transistors ranges from 2000 to 100 and the margin value ranges from 1.18 to 2.0.
Flow chart 600c shown in FIG. 6c illustrates the selection of an initial circuit under delay requirement mode. In block 2902, initial, changing and scaling circuits are sorted in increasing orders of power consumption, where circuit 0 (ckt 0) identifies the circuit with lowest power consumption and circuit 2 (ckt 2) identifies the circuit with greatest power consumption. In block 2903, it is determined whether ckt 0 delay is less than the delay requirements set by the user (dreq). If yes, circuit 0 is selected and the subsequent iteration will downsize transistor width since the circuit with lowest power consumption satisfied the delay requirement at the outset.
If circuit 0 is not less than the delay requirements set by the user (dreq), operation flows to block 2906. In block 2906, it is determined whether circuit 0 delay is less than the product of dreq and margin (i.e., the margin value calculated in flow chart 600b). If yes, circuit 0 is selected as the initial circuit. If no, operation flows to block 2910.
Flow chart 600d in FIG. 6d illustrates the selection of an initial circuit in the power requirement mode. In block 3002, the initial, changing and scaling circuits are sorted in increasing orders of delay, where circuit 0 (ckt 0) represents the smallest delay of these three circuits and circuit 2 (ckt 2) represents the greatest delay of these three circuits. In block 3004, it is determined whether ckt 0 power is less than preq (power requirement set by user). If yes, ckt 0 is selected. If no, operation flows to block 3008 where it is determined whether ckt 1 power is less than preq. If no, circuit ckt 2 is selected in block 3010. If yes, it is further determined in block 3012 (1) whether circuit 1 is less than 70% of preq, (2) whether ckt 1 is the scaling circuit and (3) whether stw (i.e., the current ratio or scaling factor) is less than 0.5. If no, circuit 1 is selected in block 3014 as the initial circuit. If yes, the inequality of block 3016 is evaluated.
Referring to FIG. 6d, if decision block 3016 is no, circuit 1 is selected in block 3024. If yes, a new stw is calculated based on the ratio of preq and the power of circuit 1 in block 3018. (See source code Appendix; select-- start in select.c.) In block 3020, the initial circuit is modified in accordance with the new stw value thereby generating a new scaling circuit. Finally, in block 3022, the scaling circuit newly calculated in block 3020 is selected as the initial circuit.
Finally, the selection of the initial circuit under slack-driven mode is shown in the source code provided in FIG. 6e. Referring to FIG. 6e, the variable "val" represents the critical slack value. If this value for the changing circuit is greater than -15, then the changing circuit is selected. Otherwise, if the critical slack value is greater than -10 for the scaling circuit, then the scaling circuit is selected. Otherwise, if the critical slack value for the initial circuit is greater than -10, then the initial circuit is selected. If none of these inequalities are satisfied, a new value of stw is calculated and this value is used to modify the initial circuit to thereby create a new scaling circuit. Thereafter, the scaling circuit is selected as the initial circuit.
FIGS. 4a and 4b illustrate first run core 312 and second run core 316 (FIG. 3), respectively. As noted above, the difference between run core 312 and run core 316 is the addition of transistor resizer 416 and bypass line 420 in run core 316. Since run core 316 encompasses all the features of run core 312, the following discussion will be directed to run core 316 (it being understood that any discussion directed to blocks 404b-415b applies equally to blocks 404a-415a, respectively).
Block 404b sets up files for power simulator 406b. In the preferred embodiment of the present invention, power simulation block 406b is performed by the POWERMILL software available from EPIC Design Technology, Inc., 2901 Tasman Drive, Suite 212, Santa Clara, Calif. 95054. (However, many other commercially-available circuit simulators may be used in place of the POWERMILL software, some of which are identified below.) POWERMILL software receives a circuit (via netlists) and stimulus (input vectors) and simulates the circuit operation at the transistor level according to a I-V characteristics from technology files 308. After finishing the simulation, POWERMILL software reports detailed simulation results for diagnostics and debugging.
Should the POWERMILL software be used, the files set up in block 404b include a configuration file. The configuration commands used in power simulation differ from those used for transistor resizing. Power simulation configuration commands may be used to define general circuit parameters for proper execution, such as setting the power supply and ground nodes, establishing speed and accuracy control and defining capacitance values of certain nodes. In addition, more power-specific configuration commands can be utilized to specify high and low threshold voltages, report a power histogram and set different power supply voltages.
The power data 408b retrieved from power simulation block 406b include circuit current, toggling activity for each node (i.e., number of logic transitions during a given simulation), identification of nodes with slow rise/fall time and identification of circuit paths coupling power and ground nodes (dc-- path).
Additional description of the POWERMILL software in connection with general operation and current calculation may be found in U.S. patent application Ser. No. 08/040,531. Additional description of the POWERMILL software in connection with identification of nodes with slow rise/fall time and identification of circuit paths coupling power and ground nodes (i.e., direct current path; "dc-- path") may be found in U.S. patent application Ser. No. 08/231,207. Finally, an overall description of the POWERMILL software may be found in Powermill User Manual 3.1 Epic Design Technology, Inc. (July 1994) and Deng, Power Analysis for CMOS/BiCMOS Circuits, IWLPD '94 Workshop Proceedings, pages 3-8 (1994), both of which are hereby incorporated by reference in their entirety for all purposes.
In addition to the POWERMILL software, other commercially-available software may be used as power simulation block 406b to generate the output identified above. Suitable substitutes for the POWERMILL software include "HSPICE" from MetaSoftware (1300 White Oaks Road, Campbell, Calif. 95008); "PSPICE" from MicroSim (20 Fairbanks, Irvine, Calif. 92710); "PRECISE" from Electrical Engineering Software (1900 McCarthy Boulevard, Suite 310, Milpitas, Calif. 95035); "SPECTRE" and "SPECTRE II" from Cadence (555 River Oaks Parkway, Building 1, San Jose, Calif. 95134); and "SPICE2" and "SPICE3" from University of California at Berkeley (Berkeley, Calif. 94720).
Block 410b sets up files for delay analysis 412b. In the preferred embodiment of the present invention, delay analysis block 412b is performed by the PATHMILL software available from EPIC Design Technology, Inc., at the address noted above. (However, many other commercially-available delay analysis tools may be used in place of the PATHMILL software, some of which are identified below.) The PATHMILL software is a static delay analysis tool. It searches the worst case delay from each input node to each output node. This software uses the same technology core as the POWERMILL software. It can achieve transistor-level delay accuracy.
Should the PATHMILL software be used, the files set up in block 410b include a configuration file. The configuration commands used in delay analysis differ from those used in transistor resizing. Like power simulation, certain delay-analysis configuration commands are used to define general circuit parameters for proper execution, such as setting the power supply and ground nodes, establishing speed and accuracy control and defining capacitance values of certain nodes. In addition, more timing-specific configuration commands can be utilized to identify the clocking nodes; set the direction of certain circuit elements; specify the part of the circuit of interest, searching conditions and criteria; and identify what information should is desired.
The timing data 414b retrieved from delay analysis block 412b include path delays or path slack, each transistor driving condition (i.e., resistance of instant and previous transistor) and each transistor loading condition (i.e., capacitance of output node). Delay is broken down into the delay of each stage; i.e., a set of channel-connected transistors. The timing data 414b also identifies the critical path based on delay as well as slack.
Additional description of the PATHMILL software may be found in PathMill User Manual 3.1 EPIC Design Technology, Inc. (July 1994) and commonly-owned, co-pending patent application, Ser. No. 08/429,430 (Attorney Docket No. 015521-000900) filed May 1, 1995, and entitled "A Circuit Analyzer of Black, Gray And Transparent Elements," both of which are hereby incorporated by reference in their entirety for all purposes.
Suitable substitutes for the PATHMILL software capable of generating the necessary timing data 414b as described above include "DESIGN TIME" from Synopsys (700 E. Middlefield Road, Mountain View, Calif. 94043); "PEARL" from Cadence (555 River Oaks Parkway, Building 1, San Jose, Calif. 95134); "LSim" from Mentor Graphics Corporation (8005 SW Boeckman, Wilsonville, Oreg. 97070); and "MOTIVE" from Viewlogic (293 Boston Post Road West, Marlboro, Mass. 01572-4615). Further, once a critical path in a circuit is identified, the driving/loading conditions of the path may simply be retrieved from the netlist rather than through a particular application software.
Detailed driving/loading conditions and nodal switching activity can be collected from power simulation block 406b and delay analysis block 412b in FIG. 4b. This information is used to decide the new sizes of the transistors by transistor resizer 416. The delay and power data is also useful in adjusting the resizing mechanism for the next iteration. During each iteration, power simulation block 406b and delay analysis block 412b are utilized to update power and timing information for the circuit undergoing transistor resizing.
Referring to FIG. 3, transistor autosizing engine 320 receives netlist file 306 describing a circuit at the transistor level. Transistor resizer 416 (FIG. 4b) can resize transistors at two levels: a gate level and an individual transistor level. Moreover, through the use of critical path information received from delay analysis 412b, resizer 416 effectively resizes transistors at a third level: the path level (with the granularity of a transistor).
FIG. 9 shows a portion of a critical path. Gate 904 has resistance R and capacitance C. Its loading capacitance is CN and the previous gate (i.e., gate 902) has a resistance Rp. Suppose we want to change the size of gate 904 by m times, then the delay due to gate 904 can be represented by Equation 4: ##EQU3## The optimal value for m to minimize delay D can be computed from the derivative of D with respect to m (Equation 5): ##EQU4##
Since dramatic change on the transistor size is impractical, transistor resizer 416 avoids this problem by setting a resizing bound at each iteration (i.e., scale-- up, scale-- down and threshold, as discussed below). Within that bound, the new sizes of transistors are computed according to their loading capacitance, driving capability and delay/power data. This computation starts from the primary outputs towards the inputs so that the change in the output load can be updated. This resizing scheme also eases the control of constraints on transistor sizes.
With respect to power demands, the transition activities at each node need to be taken into account. The transistors connected to a highly switching nodes should be kept smaller to reduce the load of that node. As shown in FIGS. 3 and 4b, second run core 316 (which includes transistor resizer 416) runs power simulation 406b at each iteration to determine the actual switching activities at each node. The switching count at each node will be collected to help adjust the sizes of the transistors. This information can take glitching power into account and reflects the correct switching activities under the current delay conditions.
Finally, if the users allow different transistor sizes inside a gate, then there will be additional room for improvements. FIG. 10 shows a simple two-input NAND gate 1000. When discharging, transistor 1001 drives capacitor 1004, while transistor 1002 drives both capacitors 1004 and 1006. If only the size of transistor 1001 is doubled, the discharging delay will be 2.5RC. This is illustrated in Equation 6, where "R" is the individual resistance of transistors 1001 and 1002, and "C" is the individual capacitance of capacitors 1004 and 1006.
However, if transistor 1002 is sized-up instead, the delay will be 2RC, as shown in Equation 7. Thus, for the same area overhead, it is more economical to increase the size of transistor 1002 since it drives more capacitors. This effect is more significant if the internal capacitance of a gate is comparable with its output capacitance. Also, it is very useful to fix a specific rise/fall time problem. ##EQU5##
The operation of transistor resizer 416 is more clearly illustrated in flow chart 1100 in FIGS. 11a, 11b and the pseudo code in FIGS. 12, 13.
Referring to FIG. 11a, an initial circuit presented for iterative analysis is first examined in block 1102 to determine whether the circuit is a product of the "init" configuration command. If yes, the circuit undergoes power and timing analysis in block 1104 (in accordance with block 316 above) since no power or delay analysis was performed in block 312 (FIG. 3). Once power and timing data is obtained, this information is forwarded to block 1108.
Alternatively, if the initial circuit is a product of "default" or "search" initial searching, power and timing analysis has already been calculated in block 312 and this information is forwarded directly to block 1108.
Blocks 1108-1146 represent activity within transistor resizer block 416 of FIG. 4b. In block 1108, resizing bounds "scale-- up," "scale-- down" and "threshold" are determined. Scale-- up represents the upper bound of iterative transistor sizing; typically this value is no larger than 3. Scale-- down represents the lower bound of iterative transistor sizing; this value floats between 0 and 1. Threshold is the triggering value that determines whether a transistor is sized up or sized down. There are separate thresholds for scale-- up and scale-- down. All four values are determined dynamically during each transistor sizing iteration (as illustrated in flow chart 1100) based on a variety of factors.
Specifically, the values of scale-- up, scale-- down and thresholds are a function of at least the user's requirements (i.e., configuration file design constraints), type of execution mode (i.e., cost function, requirement mode or slack mode) and relative improvement achieved in the last transistor resizing iteration.
Scale-- up and scale-- down are increased if one or more of the foregoing factors indicate delay can and should be reduced (i.e., max-- tx-- size is larger than current transistor size; delay coefficient in cost function mode dominates cost calculation; delay requirement in corresponding requirement mode is not met; and/or previous iteration that increased transistor sizes resulted in a decrease in delay without violating any user requirements). Of course, if one or more of these factors are reversed, scale-- up and scale-- down may be decreased. However, scale-- up will never equal 0 since some transistors may need to be sized up--even when the delay requirement in requirement mode is satisfied--to accommodate performance rules in scaling down other transistors.
Additionally, scale up and scale-- down values are decreased if one or more of the foregoing factors indicate power can and should be reduced (i.e., min-- tx-- size is smaller than current transistor size; power coefficient in cost function mode dominates cost calculation; power requirement in corresponding requirement mode is not met; and/or previous iteration that decreased transistor sizes resulted in a decrease in power without violating any user requirements).
The threshold value calculation is analogous to scale-- up and scale-- down. Specifically, if the circuit being processed requires more delay improvement (based at least on the foregoing factors), the scale-- up threshold value is decreased so a greater number of transistors may be increased in size. However, if this circuit demands greater power improvement, the scale-- down threshold value is increased so a greater number of transistors may be decreased in size.
A detailed presentation of calculation of scale-- up, scale-- down and threshold values is provided in FIG. 11c. In this figure, case 0 and 1 apply to cost function mode, case 2 applies to delay requirement mode and case 3 applies to power requirement mode.
Additionally, a detailed presentation of calculation of scale-- up and threshold for scale-- up in slack-driven mode is provided in FIG. 11d. In slack-driven mode, threshold for scale-- up and scale-- down are the same, and scale-- down is equal to the square of the threshold value.
TABLE 6______________________________________Variable   Definition______________________________________d-- cost      Delta cost (improvement from last iteration)max-- pd      maximum path delay of current iterationscale      scale-- uppdp        threshold for scale-- ups2         scale-- downp2         threshold for scale-- downdreq       delay requirement set by userin-- linear      linear interpolation of constants in parenthesispower      current power measurementpreq       power requirement set by usermax-- slk      maximum slack______________________________________
Once the scale-- up, scale-- down and threshold values are determined in block 1108, new transistor ratios are calculated in block 1110. In blocks 1110 through 1115, transistor resizer 416 serially steps through a circuit undergoing resizing analysis (the "subject circuit") and determines a preliminary ratio value for each transistor in the circuit one transistor at a time. (As discussed below, the ratio value is used to calculate a new transistor size.) Pseudo code that describes the new size calculation in block 1110 is provided in FIG. 12.
Referring to FIG. 12, the following parameters are passed to the transistor resizer routine in block 1110: threshold, scale-- up, scale-- down and circuit (i.e., netlist). For each transistor in the circuit, the associated path-- delay ("pd;" element 710) and loading capacitance (element 726) is retrieved from data structure 700 (FIG. 7). Maximum-- path-- delay (i.e., the delay value of the critical path of the subject circuit) is retrieved from delay analysis run on the subject circuit (i.e., either in block 412a for an initial circuit selected from "default" or "search" modes or in block 412b for "init" and subsequent circuits). Switching-- activities (i.e., the number of toggles experienced by a transistor whose gate is coupled to a particular node) is retrieved from power simulation run on the subject circuit (i.e., either in block 406a for an initial circuit selected from "default" or "search" modes or in block 406b for "init" and subsequent circuits). Finally, maximum-- cap is the largest load capacitance held in data structure 700.
For a transistor (i.e., "tx") currently being resized (the "current transistor") in the subject circuit, the associated path-- delay is divided by the maximum-- path-- delay producing a "delay quotient". If this value is greater than the threshold value, the associated transistor is likely on the critical path of the circuit or on a possible critical path. Therefore, the transistor should be sized up to reduce delay. The first ratio-calculation equation in FIG. 12 (i.e., using the scale-- up variable) calculates the ratio value (i.e., stw) for increasing the size of transistors.
However, if the delay quotient is less than the threshold, the associated transistor is not likely to be on the critical or possible critical paths and therefore should be sized down to reduce power consumption. The second ratio-calculation equation in FIG. 12 (i.e., using the scale-- down variable) calculates the ratio value for decreasing the size of transistors.
In block 1112, transistor resizer 416 checks configuration command "node-- switch" (described above). If this command is set "on," the switching-- activities for the current transistor (i.e., the number of times the transistor toggled during simulation) is retrieved from the power simulation data structure. This value and the initial ratio calculated for the current transistor (from the equations mentioned above) are input into a routine called "adjust" in block 1114, which will decrease the value of the ratio for highly active nodes (and thereby reduce power). The details of the adjust routine are provided in FIG. 13.
Referring to FIG. 13, the parameters ratio and SW are passed to "adjust." SW is normalized to the maximum switching activity. If the ratio for the current transistor is greater than 1.5, a new ratio value is calculated based on this value (i.e., 1.5) SW and the ratio value. Alternatively, if the ratio is less than 1, a new value is calculated based on the scale-- down variable. If the ratio value is greater than or equal to 1 and less than or equal to 1.5, it remains unchanged. These values are based on empirical data.
Referring to FIG. 11a, the newly calculated ratio value for the current transistor of the subject circuit is stored in element 730 of data structure 700 (FIG. 7) in block 1114. Additionally, element 732 ("visited") of the corresponding data structure is set to indicate a new ratio value for this transistor has been calculated.
The next transistor to be evaluated in the subject circuit (i.e., a "new" current transistor) is searched for in block 1115. If a new transistor is located, the flow of operation returns to block 1110 to repeat the foregoing operation. Alternatively, if no more transistors are present (i.e., visited field 732 of all transistor parameter records is set), the flow of operation proceeds to block 1116.
In block 1116, transistor resizer 416 checks configuration command "size-- level" (described above). If this command is set at the gate level, all transistors which are channel connected (i.e., a "pseudo gate") are resized together at the same ratio. Specifically, the individual ratio value for each transistor held in data structure 700 included in a pseudo gate is input into a routine called "Average" in block 1118. Routine Average calculates the average value of these ratios by summing the individual ratio values (i.e., ratio(txi)) and dividing this summation by the number of transistors included in the pseudo gate. The result, "new-- ratio," is then placed in location stw 730 (FIG. 7) for each affected transistor in block 1120.
Alternatively, if configuration command "size-- level" is set to the "pn" level, all channel-connected p transistors and n transistors are resized together at the same p and n ratio, respectively. Specifically, the individual ratio value for each channel connected p transistor held in data structure 700 included in a particular pseudo gate is input into a routine called "Average" in block 1124. Routine Average calculates the average value of these ratios by summing the individual ratio values (i.e., ratio(txpi)) and dividing this summation by the number of p transistors included in the pseudo gate. The result, "new-- ratio-- p," is then placed in location stw 730 (FIG. 7) for each affected transistor in block 1126.
Finally, if the size-- level command is absent from configuration file 304 (FIG. 3), ratio values remain calculated at the transistor level (i.e., no averaging is performed), and the flow of operation proceeds to block 1132 in FIG. 11b.
In block 1132, transistor resizer 416 checks configuration command "rf-- fix" (described above). If this command is set on, the user will set a threshold value to identify slow rise/fall nodes in block 1134. Rise/fall time is determined during power simulation. If, for example, the POWERMILL software is used for power simulation, then nodes with excessive rise/fall time may be identified dynamically, as described in U.S. patent application Ser. No. 08/231,207.
Specifically, a variable "term" is calculated in accordance with equation 8: ##EQU6##
In EQ 8, rf is the measured rise/fall time (i.e., from power simulation) and user-- rf is user rise/fall time specified by rf-- fix. Upon calculating term, the associated ratios are sized up in block 1136 in accordance with equation 9:
ratio-- new=ratio*term                                (EQ 9)
This ratio-- new value is placed in stw field 730 of the transistor parameter record (FIG. 7c) for each affected transistor.
Specifically, a variable "gate" is calculated in accordance with equation 10: ##EQU7##
Again, this ratio-- new value is placed in stw field 730 of the transistor parameter record (FIG. 7c) for each affected transistor.
In EQ 10, rf and user-- rf have the same meaning as indicated above in EQ 8. Upon calculating gate, the associated ratios are sized down in block 1138 in accordance with equation 11:
ratio-- new=ratio*gate                                (EQ 11)
Upon completing the rf-- fix operation in blocks 1134-1138 (or skipping this operation entirely if rf-- fix is not specified in block 1132), operation flows to block 1146.
Upon determining the ratio value for each transistor in the subject circuit (and updating this value in element 730 of each transistor parameter record in data structure 700; FIG. 7), this value is multiplied with the corresponding previous transistor width (i.e., i.e., old-- size(tx) held in the parameter data structures for power simulation and delay analysis; i.e., field 736 of FIG. 7a) to obtain a new transistor width (i.e., new-- size(tx)) in block 1146. This new value is loaded into power simulation and delay analysis transistor parameter data structures analogous to data structure 700. This process is carried out for each transistor in the subject circuit via block 1148 until every transistor has been resized.
3. Stop-- Check
FIG. 14 represents pseudo code of the stop-- check block 318 of FIG. 3. After new transistor sizes are calculated but before power simulation and delay analysis is run on these new values, the stop-- check block decides whether analysis should proceed.
More specifically, configuration command "degrade-- thresh" (described above) enables the user to set a threshold for degradation of power or delay. If the level of power or delay from one iteration to the next worsens by more than this threshold value, analysis terminates. The threshold value has no units. It is a percentage based on the maximum value of delay or power in a current iteration (i.e., a threshold of 90% for delay means 90% of maximum path delay).
TABLE 7______________________________________Execution Mode         Analysis Terminates When:______________________________________Cost Function If the change in cost (i.e., increase)         from the previous iteration to the         current iteration exceeds the threshold         percentage.Delay Requirement         If the delay requirement is met and the         change in power (i.e., increase) from         the previous iteration to the current         iteration exceeds the threshold         percentage.Power Requirement         If the power requirement is met and the         change in delay (i.e., increase) from         the previous iteration to the current         iteration exceeds the threshold         percentage.Slack         If slack requirement is met and the         change in power (i.e., increase) from         the previous iteration to the current         iteration exceeds the threshold         percentage.______________________________________
Transistor sizes are not displayed in the execution reports of FIGS. 20-24 due to the typically large volume of transistors making up a subject circuit. These values are maintained in separate transistor parameter data structures accessed by power simulation and delay analysis software. Exemplary data structures are shown in FIG. 7a.
Referring to FIG. 20, a typical execution report includes a header portion 2002 which reveals the mode (slack-driven in this case), max-- tx-- size (300 um in this case), min-- tx-- size (1.0 um in this case), use of wire-- cap-- est command (wire), use of node-- switch command (toggle), argument of size-- level command (transistor level in this case) and the number of elements making up the subject circuit.
The execution report also includes the results of initial searching in portion 2004. The initial circuit, scaling circuit and changing circuit are identified with the abbreviations "Initial," "S," and "C," respectively. In this case the scaling factor equals 0.5, and the smallest transistor size is 1.0 um. Since the changing circuit has the best slack value (i.e., +5.63), engine 320 selects this circuit as the initial circuit for transistor autosizing.
Referring to FIG. 27, engine 320 characterizes a conventional cell 3102 through delay analysis 3104. This characterization includes total-- cap (summation of capacitance of all nodes in gate), output-- c (capacitance of gate output), input-- c (capacitance of gate input), intrinsic delay and driving capability.
During cell evaluation, each cell within circuit 3206 having a functional equivalent in library 3204 is targeted for swapping in a single iteration. Each cell within library 3204 having identical functionality with the targeted cells in the circuit is compared with the cells. This comparison requires the calculation of ΔD and ΔP between each library cell and its functional equivalent in the circuit. The library cells producing the largest values of -ΔD/ΔP (i.e., delay saved/power overhead) are chosen as replacements, and are swapped into circuit 3206.
As noted above, wiring capacitance estimation can be turned on by a configuration command (i.e., "wire-- cap-- est"). If the wiring estimation is turned on, the capacitance of each node will be increased by an estimation amount accounting for the wiring effects. A user can also customize the estimation formula through a command-line option "-u" (which specifies the file that can customize a wire capacitance estimation formula). The user may utilize any of the parameters identified at the top of the routine in FIG. 15.
The operation related to wiring capacitance is illustrated in the C code in FIG. 15. This operation takes place prior to performing power simulation and delay analysis. More specifically, it occurs during preprocessing block 612 of FIG. 6. In preparation for power simulation and delay analysis, engine 320 checks wire-- cap-- est command. If this command is set "on," the routine shown in FIG. 15 is carried out.
Referring to FIG. 15, the first two lines set FANIN-- CAP and FANOUT-- CAP to set values. These values are derived from empirical analysis, user design environment (i.e., type of layout tools) and user technology. Further in the routine, the variable fanin is defined as a summation of the number of channels connected to the subject node and the number of outputs. Similarly, fanout is defined as a summation of the number of gates connected to the subject node, number of inputs and number of biputs. The variables in FIG. 15 include number-- channel (number of channel connected transistors), number-- gate (number of gate connected transistors and number-- input, number-- output, and number-- biput (I/O connections specified by user).
Next, a scaling factor ("fanout-- scale") is selected based on the number of fanouts. The options are shown in FIG. 15. This scaling factor is also derived from empirical analysis. A preliminary cap value for the node is calculated using equation 12:
cap=fanin*FANIN-- CAP+fanout*FANIN-- CAP*fanout-- scale (EQ 12)
The effect of area on capacitance is considered through equation 13: ##EQU8##
In EQ 13, "area" is the total width of transistors coupled to the subject node.
An additional configuration command currently under development is "leakage-- fix," whose operation is shown in FIG. 17. This operation is anticipated to be placed between blocks 1132 and 1146 in FIG. 11b. Referring to FIG. 17, transistor resizer 416 checks configuration command "leakage-- fix" in block 1140. If this command is set "on," the paths of the subject circuit that exhibit coupling between power and ground (i.e., direct current paths: "dc-- paths") are identified in block 1142. DC-- paths are determined during power simulation.
More specifically, power simulation identifies dc-- paths as those paths coupling power to ground immediately prior to input transition. Under desired operating conditions, any switching activity will be complete immediately prior to receiving a new input signal. However, if switching operations are still on-going immediately prior to receipt of new input, then this is indicative of weak driving transistors. Therefore, these transistors should be sized up.
Returning to FIG. 17, sets of channel connected transistors forming direct current paths ("dc-- paths") are identified in block 1142. In block 1144, transistors included in each set are sized up to increase the drive of the dc-- path stage (i.e., the associated ratios are increased in size). The same calculations performed in rf-- fix to size up transistors (i.e., EQ 8 and EQ 9) are used in this operation.
Upon completing the leakage-- fix operation in blocks 1142-1144 (or skipping this operation entirely if leakage-- fix is not specified in block 1140), operation flows to block 1146 in FIG. 11b.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4198697 *Jun 15, 1978Apr 15, 1980Texas Instruments IncorporatedMultiple dummy cell layout for MOS random access memoryUS4495628 *Jun 17, 1982Jan 22, 1985Storage Technology PartnersCMOS LSI and VLSI chips having internal delay testing capabilityUS4587480 *Jun 20, 1984May 6, 1986Storage Technology PartnersDelay testing method for CMOS LSI and VLSI integrated circuitsUS4698760 *Jun 6, 1985Oct 6, 1987International Business MachinesMethod of optimizing signal timing delays and power consumption in LSI circuitsUS4827428 *Nov 15, 1985May 2, 1989American Telephone And Telegraph Company, At&T Bell LaboratoriesTransistor sizing system for integrated circuitsUS4907180 *May 4, 1987Mar 6, 1990Hewlett-Packard CompanyHardware switch level simulator for MOS circuitsUS5235521 *Oct 8, 1991Aug 10, 1993International Business Machines CorporationReducing clock skew in large-scale integrated circuitsUS5349542 *Apr 2, 1992Sep 20, 1994Vlsi Technology, Inc.Method for sizing widths of power busses in integrated circuitsUS5446676 *Mar 29, 1993Aug 29, 1995Epic Design Technology Inc.Transistor-level timing and power simulator and power analyzerUS5459673 *Apr 11, 1994Oct 17, 1995Ross Technology, Inc.Method and apparatus for optimizing electronic circuitsUS5508937 *Apr 16, 1993Apr 16, 1996International Business Machines CorporationIncremental timing analysisUS5541849 *Jun 14, 1993Jul 30, 1996Lsi Logic CorporationMethod and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parametersUS5553008 *Jul 10, 1995Sep 3, 1996Epic Design Technology Inc.Transistor-level timing and simulator and power analyzerUS5557531 *Jun 14, 1993Sep 17, 1996Lsi Logic CorporationMethod and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation* Cited by examinerNon-Patent CitationsReference1 *AIDA Timing Verifier Technical Spec, pp. 1 4.2AIDA Timing Verifier Technical Spec, pp. 1-4.3Aron, "The Program Development Process, The Programming Team, Part II," in The Systems Programming Series, Adison-Wesley, pp. 605-607, 1983.4 *Aron, The Program Development Process, The Programming Team, Part II, in The Systems Programming Series , Adison Wesley, pp. 605 607, 1983.5Berkelaar, et al., "Computing the Entire Active Area/Power Consumption Versus Delay Trade-off Curve for Gate Sizing with a Piecewise Linear Simulator,"Proc. of Int'l. Conference on Computer-Aided Design, pp. 474-480, Nov. 1994.6 *Berkelaar, et al., Computing the Entire Active Area/Power Consumption Versus Delay Trade off Curve for Gate Sizing with a Piecewise Linear Simulator, Proc. of Int l. Conference on Computer Aided Design , pp. 474 480, Nov. 1994.7Black, "Electromigration Failure Modes in Aluminum Metallization for Semiconductor Devices," Proc. of the IEEE, 57(9):1587-1594, 1969.8 *Black, Electromigration Failure Modes in Aluminum Metallization for Semiconductor Devices, Proc. of the IEEE , 57(9):1587 1594, 1969.9Burch, et al., "Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits," Proc. of the IEEE Design Automation Conf., pp. 294-299, 1988.10 *Burch, et al., Pattern Independent Current Estimation for Reliability Analysis of CMOS Circuits, Proc. of the IEEE Design Automation Conf. , pp. 294 299, 1988.11Chan, et al., "Managing IC Power Needs," High Performance Systems, pp. 69-70, 73-74, 1990.12 *Chan, et al., Managing IC Power Needs, High Performance Systems , pp. 69 70, 73 74, 1990.13Chawla, et al., "MOTIS, An MOS Timing Simulator," IEEE Trans. on Circuits and Systems, CAS-22(12):901-910, 1975.14 *Chawla, et al., MOTIS, An MOS Timing Simulator, IEEE Trans. on Circuits and Systems , CAS 22(12):901 910, 1975.15Chowdhury, et al., "Minimal Area Sizing for Power and Ground Nets for VLSI Circuits," Proc. of the 4th MIT Conference on Advanced Research in VLSI, pp. 141-169, 1986.16 *Chowdhury, et al., Minimal Area Sizing for Power and Ground Nets for VLSI Circuits, Proc. of the 4th MIT Conference on Advanced Research in VLSI , pp. 141 169, 1986.17de Geus, "Logic Synthesis Speeds ASIC Design," IEEE Spectrum, pp. 27-31, Aug. 1989.18 *de Geus, Logic Synthesis Speeds ASIC Design, IEEE Spectrum, pp. 27 31 , Aug. 1989.19Deng, "Power Analysis for CMOS/BiCMOS Circuits," Int'l. Workshop on Low Power Design, pp. 3-8, Apr. 1994.20 *Deng, Power Analysis for CMOS/BiCMOS Circuits, Int l. Workshop on Low Power Design , pp. 3 8, Apr. 1994.21Fan, et al., "MOTIS-C: A New Circuit Simulator for MOS LSI Circuits," Proc. of ISCAS, pp. 700-703, 1977.22 *Fan, et al., MOTIS C: A New Circuit Simulator for MOS LSI Circuits, Proc. of ISCAS , pp. 700 703, 1977.23Fishburn, et al., "TILOS: A Posynominal Programming Approach to Transistor Sizing," Proc. of Int'l. Conference on Computer-Aided Design, pp. 326-328, 1985.24 *Fishburn, et al., TILOS: A Posynominal Programming Approach to Transistor Sizing, Proc. of Int l. Conference on Computer Aided Design , pp. 326 328, 1985.25Fred W. Obermeier et al., "An Electrical Optimizer That Considers Physical Layout," 25th ACM/IEEE Design Automation Conference, 1988, IEEE, Paper 29.3, pp. 453-459.26 *Fred W. Obermeier et al., An Electrical Optimizer That Considers Physical Layout, 25th ACM/IEEE Design Automation Conference, 1988, IEEE, Paper 29.3, pp. 453 459.27 *Glasser, et al., The Design and Analysis of VLSI Circuits , Addison Wesley, pp. 97 101,1985.28Glasser, et al., The Design and Analysis of VLSI Circuits, Addison-Wesley, pp. 97-101,1985.29Halliday, "dV/dt Automates Creating Timing Diagrams," Design Management, 15(5), 1991.30 *Halliday, dV/dt Automates Creating Timing Diagrams, Design Management , 15(5), 1991.31Hedlund, "Electrical Optimiztion of PLA's, " Proc. of Design Automation Conference, pp. 681-687, Jun. 1985.32 *Hedlund, Electrical Optimiztion of PLA s, Proc. of Design Automation Conference , pp. 681 687, Jun. 1985.33Jagau, "Simcurrent--An Efficient Program for the Estimation of the Current Flow of Complex CMOS Circuits," IEEE ICCAD Digest of Technical Papers, pp. 396-399, 1990.34 *Jagau, Simcurrent An Efficient Program for the Estimation of the Current Flow of Complex CMOS Circuits, IEEE ICCAD Digest of Technical Papers , pp. 396 399, 1990.35John K. Ousterhout, "Switch-Level Delay Models For Digitals MOS VLSI," 21st Design Automation Conference, 1984 IEEE, Paper 32.3, pp. 542-548.36 *John K. Ousterhout, Switch Level Delay Models For Digitals MOS VLSI, 21st Design Automation Conference, 1984 IEEE, Paper 32.3, pp. 542 548.37Mark D. Matson, "Optimization of Digital MOS VLSI Circuits," 1985, Chapel Hill Conference on Very Large Scale Integration, Edited by Henry Fuchs, pp. 109-126.38 *Mark D. Matson, Optimization of Digital MOS VLSI Circuits, 1985, Chapel Hill Conference on Very Large Scale Integration , Edited by Henry Fuchs, pp. 109 126.39Newton, "Techniques for the Simulation of Large-Scale Integrated Circuits," IEEE Trans. on Circuits and Systems, CAS-26(9):741-749, 1979.40 *Newton, Techniques for the Simulation of Large Scale Integrated Circuits, IEEE Trans. on Circuits and Systems , CAS 26(9):741 749, 1979.41Norman P. Jouppi, "Timing Analysis for nMOS VLSI," 20th Design Automation Conference, 1983 IEEE, Paper 27.3, pp. 411-418.42 *Norman P. Jouppi, Timing Analysis for nMOS VLSI, 20th Design Automation Conference, 1983 IEEE, Paper 27.3, pp. 411 418.43Odryna, et al., "The ADEPT Timing Simulation Algorithm," VLSI Systems Design, pp. 24-34, 1986.44 *Odryna, et al., The ADEPT Timing Simulation Algorithm, VLSI Systems Design , pp. 24 34, 1986.45 *Pathmill User Manual 3.1, EPIC Design Technology Inc. , Jul. 1994.46Pathmill User Manual 3.1, EPIC Design Technology Inc., Jul. 1994.47Rubinstein, et al., "Signal Delay in RC Tree Networks," IEEE Transactions on Computer-Aided Design, 2:202-211, Jul. 1983.48 *Rubinstein, et al., Signal Delay in RC Tree Networks, IEEE Transactions on Computer Aided Design , 2:202 211, Jul. 1983.49Ruehli, et al., "Analytical Power/Timing Optimization Technique for Digital System," Proc. of Design Automation Conference, pp. 142-146, Jun. 1977.50 *Ruehli, et al., Analytical Power/Timing Optimization Technique for Digital System, Proc. of Design Automation Conference , pp. 142 146, Jun. 1977.51Saleh, et al., "Iterated Timing Analysis in SPLICE 1," ICCAD Digest of Technical Papers, pp. 139-140, 1983.52 *Saleh, et al., Iterated Timing Analysis in SPLICE 1, ICCAD Digest of Technical Papers , pp. 139 140, 1983.53Song, et al., "Power Disctribution Tecgniques for VLSI Circuits," IEEE J. of Solid-State Circuits, SC-21(1):150-156, 1986.54 *Song, et al., Power Disctribution Tecgniques for VLSI Circuits, IEEE J. of Solid State Circuits , SC 21(1):150 156, 1986.55Spatnekar, et al., "An Exact Solution to the Transistor Sizing Problem for CMOS CIrcuits Using Convex Optimization," IEEE Transactions on Computer-Aided Design, 12(11):1621-1634, Nov. 1993.56 *Spatnekar, et al., An Exact Solution to the Transistor Sizing Problem for CMOS CIrcuits Using Convex Optimization, IEEE Transactions on Computer Aided Design , 12(11):1621 1634, Nov. 1993.57Tamiya, et al., "LP Based Cell Selection with Costraints of Timing, Area, and Power Consumption," Proc. of Int'l. Conference on Computer-Aided Design, pp. 378-381, Nov. 1994.58 *Tamiya, et al., LP Based Cell Selection with Costraints of Timing, Area, and Power Consumption, Proc. of Int l. Conference on Computer Aided Design , pp. 378 381, Nov. 1994.59Terman, "Simulation Tools for Digital LSI Design," Ph.D. thesis, Massachusetts Institute of Technology, Laboratory for Computer Science, 1983.60 *Terman, Circuit Description and Simulation NET, CNET, RSIM, PRESIM and NL User s Manual , Massachusetts Institute of Technology, 1986.61Terman, Circuit Description and Simulation--NET, CNET, RSIM, PRESIM and NL User's Manual, Massachusetts Institute of Technology, 1986.62 *Terman, Simulation Tools for Digital LSI Design, Ph.D. thesis, Massachusetts Institute of Technology, Laboratory for Computer Science, 1983.63 *Tzu Mu Lin et al., Signal Delay in General RC Networks With Application To Timing Simulation of Digital Integrated Circuits, Conference on Advanced Research in VLSI, M.I.T., Jan. 24, 1984, pp. 93 99.64Tzu-Mu Lin et al., "Signal Delay in General RC Networks With Application To Timing Simulation of Digital Integrated Circuits," Conference on Advanced Research in VLSI, M.I.T., Jan. 24, 1984, pp. 93-99.65Vishwani D. Agrawal, "Synchronous Path Analysis In Mos Circuit Simulator," 19th Design Automation Conference, 1992 IEEE, Paper 35.4, pp. 629-635.66 *Vishwani D. Agrawal, Synchronous Path Analysis In Mos Circuit Simulator, 19th Design Automation Conference, 1992 IEEE, Paper 35.4, pp. 629 635.67William H. Kao et al., "Algorithms for Automatic Transistor Sizing in CMOS Digital Circuits," 22nd Design Automation Conference, 1985 IEEE, Paper 46.2, pp. 781-784.68 *William H. Kao et al., Algorithms for Automatic Transistor Sizing in CMOS Digital Circuits, 22nd Design Automation Conference, 1985 IEEE, Paper 46.2, pp. 781 784.69Yamada, et al., "Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization," Proc. of IEEE Symposium on Low Power Electronics, pp. 50-51, Oct. 1994.70 *Yamada, et al., Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization, Proc. of IEEE Symposium on Low Power Electronics , pp. 50 51, Oct. 1994.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5974244 *Jun 13, 1997Oct 26, 1999Kabushiki Kaisha ToshibaLayout pattern generation device for semiconductor integrated circuits and method thereforUS5983007 *May 30, 1997Nov 9, 1999Lucent Technologies Inc.Low power circuits through hazard pulse suppressionUS6072948 *Feb 2, 1998Jun 6, 2000Mitsubishi Electric System Lsi Design CorporationDevice for rapid simulation of logic circuitsUS6090151 *Jul 1, 1997Jul 18, 2000Motorola, Inc.Electronic device parameter estimator and method thereforUS6148434 *Sep 17, 1997Nov 14, 2000Kabushiki Kaisha ToshibaApparatus and method for minimizing the delay times in a semiconductor deviceUS6175949 *Mar 24, 1998Jan 16, 2001International Business Machines CorporationMethod and system for selecting sizes of components for integrated circuitsUS6185720 *Jun 19, 1998Feb 6, 2001Intel CorporationSlaveless synchronous system designUS6202193 *Jun 27, 1997Mar 13, 2001Nec CorporationApparatus for optimization of circuit designUS6209122 *May 4, 1998Mar 27, 2001Synopsys, Inc.Minimization of circuit delay and power through transistor sizingUS6249897 *Aug 19, 1998Jun 19, 2001Comcad Gmbh Analog Design SupportProcess for sizing of componentsUS6260180 *May 13, 1999Jul 10, 2001Hewlett-Packard CompanySystem and method for detecting FETs that are susceptible to bootstrappingUS6260184 *Oct 20, 1998Jul 10, 2001International Business Machines CorporationDesign of an integrated circuit by selectively reducing or maintaining power lines of the deviceUS6279143 *Mar 23, 1999Aug 21, 2001Hewlett-Packard CompanyMethod and apparatus for generating a database which is used for determining the design quality of network nodesUS6301691 *Apr 27, 1999Oct 9, 2001Hewlett-Packard CompanySystem and method for detecting NFETs that pull up to VDD and PFETs that pull down to groundUS6316301 *Mar 8, 2000Nov 13, 2001Sun Microsystems, Inc.Method for sizing PMOS pull-up devicesUS6327552 *Dec 28, 1999Dec 4, 2001Intel CorporationMethod and system for determining optimal delay allocation to datapath blocks based on area-delay and power-delay curvesUS6339347Mar 30, 2000Jan 15, 2002Intel CorporationMethod and apparatus for ratioed logic structure that uses zero or negative threshold voltageUS6353918 *Mar 12, 1997Mar 5, 2002The Arizona Board Of Regents On Behalf Of The University Of ArizonaInterconnection routing systemUS6367062Feb 18, 1999Apr 2, 2002Hewlett-Packard CompanySystem and method for detecting an excessive number of series-connected pass FETsUS6397169 *Jun 30, 1998May 28, 2002Synopsys, Inc.Adaptive cell separation and circuit changes driven by maximum capacitance rulesUS6405349May 26, 2000Jun 11, 2002General Dynamics Decision Systems, In.Electronic device parameter estimator and method thereforUS6427226May 25, 1999Jul 30, 2002Advanced Micro Devices, Inc.Selectively reducing transistor channel length in a semiconductor deviceUS6449578 *Jun 30, 1999Sep 10, 2002Hewlett-Packard CompanyMethod and apparatus for determining the RC delays of a network of an integrated circuitUS6477695 *Jun 22, 1999Nov 5, 2002Artisan Components, Inc.Methods for designing standard cell transistor structuresUS6543041 *Jun 15, 1999Apr 1, 2003Cadence Design Systems, Inc.Method and apparatus for reducing signal integrity and reliability problems in ICS through netlist changes during placementUS6606587 *Apr 14, 1999Aug 12, 2003Hewlett-Packard Development Company, L.P.Method and apparatus for estimating elmore delays within circuit designsUS6665847Oct 5, 2001Dec 16, 2003Cypress Semiconductor CorporationAccurate and realistic corner characterization of standard cellsUS6711730May 13, 2002Mar 23, 2004Hewlett-Packard Development Company, L.P.Synthesizing signal net information from multiple integrated circuit package modelsUS6754877 *Dec 14, 2001Jun 22, 2004Sequence Design, Inc.Method for optimal driver selectionUS6763506 *Feb 23, 2001Jul 13, 2004Altera CorporationMethod of optimizing the design of electronic systems having multiple timing constraintsUS6769110 *Feb 28, 2002Jul 27, 2004Renesas Technology Corp.Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuitUS6957400 *Aug 29, 2003Oct 18, 2005Cadence Design Systems, Inc.Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit designUS6981231 *Feb 22, 2002Dec 27, 2005Hewlett-Packard Development Company, L.P.System and method to reduce leakage power in an electronic deviceUS7055121 *Sep 26, 2002May 30, 2006Cypress Semiconductor CorporationMethod, system, and computer program product for designing an integrated circuit using substitution of standard cells with substitute cells having differing electrical characteristicsUS7127687 *Oct 14, 2003Oct 24, 2006Sun Microsystems, Inc.Method and apparatus for determining transistor sizesUS7129741Apr 20, 2004Oct 31, 2006Renesas Technology Corp.Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuitUS7137093 *Aug 8, 2003Nov 14, 2006Cadence Design Systems, Inc.Post-placement timing optimization of IC layoutUS7138828Sep 15, 2004Nov 21, 2006Xilinx, Inc.FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the sameUS7185294Sep 23, 2004Feb 27, 2007Verisilicon Holdings, Co LtdStandard cell library having globally scalable transistor channel lengthUS7185298 *Dec 17, 2004Feb 27, 2007Lsi Logic CorporationMethod of parasitic extraction from a previously calculated capacitance solutionUS7219045 *Sep 27, 2001May 15, 2007Cadence Design Systems, Inc.Hot-carrier reliability design rule checkerUS7243312 *Oct 24, 2003Jul 10, 2007Xilinx, Inc.Method and apparatus for power optimization during an integrated circuit design processUS7257801 *Jul 31, 2003Aug 14, 2007Matsushita Electric Industrial Co., Ltd.Cell library database and timing verification and withstand voltage verification systems for integrated circuit using the sameUS7346479 *Sep 4, 1998Mar 18, 2008Intel CorporationSelecting design points on parameter functions having first sum of constraint set and second sum of optimizing set to improve second sum within design constraintsUS7389485Mar 28, 2006Jun 17, 2008Xilinx, Inc.Methods of routing low-power designs in programmable logic devices having heterogeneous routing architecturesUS7404158 *Oct 17, 2005Jul 22, 2008Sharp Kabushiki KaishaInspection method and inspection apparatus for semiconductor integrated circuitUS7506284 *Jan 19, 2006Mar 17, 2009Samsung Electronics Co., Ltd.Event driven switch level simulation method and simulatorUS7506293 *Mar 22, 2006Mar 17, 2009Synopsys, Inc.Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysisUS7567891Sep 27, 2001Jul 28, 2009Cadence Design Systems, Inc.Hot-carrier device degradation modeling and extraction methodologiesUS7584441Sep 19, 2003Sep 1, 2009Cadence Design Systems, Inc.Method for generating optimized constraint systems for retimable digital designsUS7653889 *Sep 20, 2006Jan 26, 2010Fujitsu LimitedMethod and apparatus for repeat execution of delay analysis in circuit designUS7657855 *May 25, 2007Feb 2, 2010Xilinx, Inc.Efficient timing graph update for dynamic netlist changesUS7716618May 31, 2007May 11, 2010Stmicroelectronics, S.R.L.Method and system for designing semiconductor circuit devices to reduce static power consumptionUS7774731Jul 17, 2008Aug 10, 2010Synopsys, Inc.Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysisUS7893712Sep 10, 2009Feb 22, 2011Xilinx, Inc.Integrated circuit with a selectable interconnect circuit for low power or high performance operationUS8015525 *May 2, 2008Sep 6, 2011International Business Machines CorporationSystem and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysisUS8060844Nov 26, 2008Nov 15, 2011Cadence Design Systems, Inc.Method for generating optimized constraint systems for retimable digital designsUS8086988May 18, 2009Dec 27, 2011International Business Machines CorporationChip design and fabrication method optimized for profitUS8127266Sep 17, 2008Feb 28, 2012Tela Innovations, Inc.Gate-length biasing for digital circuit optimizationUS8185865Mar 4, 2010May 22, 2012Tela Innovations, Inc.Methods for gate-length biasing using annotation dataUS8255854 *Apr 2, 2010Aug 28, 2012Actel CorporationArchitecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuitUS8346529 *Dec 29, 2009Jan 1, 2013Mentor Graphics CorporationDelta retiming in logic simulationUS8490043Mar 4, 2010Jul 16, 2013Tela Innovations, Inc.Standard cells having transistors annotated for gate-length biasingUS8635583Sep 14, 2012Jan 21, 2014Tela Innovations, Inc.Standard cells having transistors annotated for gate-length biasingUS8671367 *Dec 19, 2008Mar 11, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Integrated circuit design in optical shrink technology nodeUS8683408 *Oct 31, 2012Mar 25, 2014Synopsys, Inc.Sequential sizing in physical synthesisUS8756555Sep 14, 2012Jun 17, 2014Tela Innovations, Inc.Standard cells having transistors annotated for gate-length biasingUS8863058 *Sep 24, 2012Oct 14, 2014Atrenta, Inc.Characterization based buffering and sizing for system performance optimizationUS8869094Sep 14, 2012Oct 21, 2014Tela Innovations, Inc.Standard cells having transistors annotated for gate-length biasingUS8949768Sep 14, 2012Feb 3, 2015Tela Innovations, Inc.Standard cells having transistors annotated for gate-length biasingUS8966420Sep 12, 2012Feb 24, 2015International Business Machines CorporationEstimating delay deterioration due to device degradation in integrated circuitsUS8987868Feb 24, 2009Mar 24, 2015Xilinx, Inc.Method and apparatus for programmable heterogeneous integration of stacked semiconductor dieUS9000490Apr 19, 2013Apr 7, 2015Xilinx, Inc.Semiconductor package having IC dice and voltage tunersUS9015023May 5, 2010Apr 21, 2015Xilinx, Inc.Device specific configuration of operating voltageUS9069926May 5, 2014Jun 30, 2015Tela Innovations, Inc.Standard cells having transistors annotated for gate-length biasingUS9202003Apr 4, 2014Dec 1, 2015Tela Innovations, Inc.Gate-length biasing for digital circuit optimizationUS20030163792 *Feb 22, 2002Aug 28, 2003Weize XieSystem and method to reduce leakage power in an electronic deviceUS20040040004 *Jul 31, 2003Feb 26, 2004Matsushita Electric Industrial Co., Ltd.Cell library database and timing verification and withstand voltage verification systems for integrated circuit using the sameUS20040143531 *Jan 9, 2004Jul 22, 2004Frank Mark D.Synthesizing signal net information from multiple integrated circuit package modelsUS20040196684 *Apr 20, 2004Oct 7, 2004Renesas Technology Corp.Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor intergrated circuitUS20040243947 *Aug 29, 2003Dec 2, 2004Neolinear, Inc.Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit designUS20050024056 *Aug 1, 2003Feb 3, 2005Sabate Juan AntonioMethods and apparatus for switching frequency ripple reduction in coilsUS20050034089 *Aug 6, 2003Feb 10, 2005Mcguffin Tyson R.Area based power estimationUS20050034091 *Aug 8, 2003Feb 10, 2005Ywh-Pyng HarnPost-placement timing optimization of IC layoutUS20050039155 *Sep 15, 2004Feb 17, 2005Xilinx, Inc.FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the sameUS20050050483 *Aug 25, 2003Mar 3, 2005Keller S. BrandonSystem and method analyzing design elements in computer aided design toolsUS20050050494 *Sep 2, 2003Mar 3, 2005Mcguffin Tyson R.Power estimation based on power characterizations of non-conventional circuitsUS20050062496 *Sep 19, 2003Mar 24, 2005Alexander GidonMethod for generating optimized constraint systems for retimable digital designsUS20050081175 *Oct 10, 2003Apr 14, 2005Scott William FransonMethod for discrete gate sizing in a netlistUS20050210429 *Mar 18, 2004Sep 22, 2005Keller S BSystem and method to limit runtime of VLSI circuit analysis tools for complex electronic circuitsUS20060064665 *Sep 23, 2004Mar 23, 2006Xiaonan ZhangStandard cell library having globally scalable transistor channel lengthUS20060090147 *Oct 17, 2005Apr 27, 2006Sharp Kabushiki KaishaInspection method and inspection apparatus for semiconductor integrated circuitUS20060136850 *Dec 17, 2004Jun 22, 2006Lsi Logic CorporationMethod of parasitic extraction from a previously calculated capacitance solutionUS20060161413 *Jan 13, 2006Jul 20, 2006Legend Design Technology, Inc.Methods for fast and large circuit simulationUS20060190862 *Jan 19, 2006Aug 24, 2006Lee Seuk-WhanEvent driven switch level simulation method and simulatorUS20070226668 *Mar 22, 2006Sep 27, 2007Synopsys, Inc.Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysisUS20070226669 *Sep 20, 2006Sep 27, 2007Fujitsu LimitedMethod and apparatus for repeat execution of delay analysis in circuit designUS20080016478 *Jul 12, 2007Jan 17, 2008Cray Inc.Parasitic impedance estimation in circuit layoutUS20080040698 *May 31, 2007Feb 14, 2008Lina FerrariMethod and system for designing semiconductor circuit devices to reduce static power consumptionUS20080201676 *May 2, 2008Aug 21, 2008Hongliang ChangSystem and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysisUS20080295053 *Jul 17, 2008Nov 27, 2008Synopsys, Inc.Characterizing Sequential Cells Using Interdependent Setup And Hold Times, And Utilizing The Sequential Cell Characterizations In Static Timing AnalysisUS20090083685 *Nov 26, 2008Mar 26, 2009Cadence Design Systems, Inc.Method for generating optimized constraint systems for retimable digital designsUS20090299716 *Jun 17, 2009Dec 3, 2009Zhihong LiuHot-Carrier Device Degradation Modeling and Extraction MethodologiesUS20090326873 *Dec 19, 2008Dec 31, 2009Taiwan Semiconductor Manufacturing Company, Ltd.Integrated circuit design in optical shrink technology nodeUS20100169846 *Mar 4, 2010Jul 1, 2010Tela Innovations. Inc., A Delaware CorporationMethods for gate-length biasing using annotation dataUS20100169847 *Mar 4, 2010Jul 1, 2010Tela Innovations. Inc., A Delaware CorporationStandard cells having transistors annotated for gate-length biasingUS20100192117 *Apr 2, 2010Jul 29, 2010Actel CorporationArchitecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuitUS20100293512 *May 18, 2009Nov 18, 2010International Business Machines CorporationChip design and fabrication method optimized for profitUS20110161066 *Dec 29, 2009Jun 30, 2011Mentor Graphics CorporationDelta retiming in logic simulationUS20130145331 *Oct 31, 2012Jun 6, 2013Synopsys, Inc.Sequential sizing in physical synthesisUS20140089879 *Sep 24, 2012Mar 27, 2014Atrenta, Inc.Characterization based buffering and sizing for system performance optimizationWO2000034902A1 *Nov 22, 1999Jun 15, 2000Artisan Components, Inc.Methods for designing standard cell transistor structuresWO2005029262A2 *Sep 17, 2004Mar 31, 2005Cadence Design Systems, Inc.A method for generating optimized constraint systems for retimable digital designsWO2005029262A3 *Sep 17, 2004Feb 2, 2006Cadence Design Systems IncA method for generating optimized constraint systems for retimable digital designs* Cited by examinerClassifications U.S. Classification716/113, 716/134, 716/133, 716/123, 716/115International ClassificationG06F17/50Cooperative ClassificationG06F2217/78, G06F17/505European ClassificationG06F17/50D2Legal EventsDateCodeEventDescriptionJul 3, 1995ASAssignmentOwner name: EPIC DESIGN TECHNOLOGY, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JYU, HENRY HORNG-FEI;DENG, AN-CHANG;REEL/FRAME:007543/0728Effective date: 19950623Aug 8, 1997ASAssignmentOwner name: SYNOPSYS, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:EPIC DESIGN TECHNOLOGY, INC.;REEL/FRAME:008644/0910Effective date: 19970620Sep 3, 2002FPAYFee paymentYear of fee payment: 4Sep 8, 2006FPAYFee paymentYear of fee payment: 8Oct 11, 2010REMIMaintenance fee reminder mailedNov 19, 2010SULPSurcharge for late paymentYear of fee payment: 11Nov 19, 2010FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services