Source: http://www.google.co.uk/patents/US4231087
Timestamp: 2013-05-20 02:22:33
Document Index: 482314036

Matched Legal Cases: ['ART) 302', 'ART 302', 'ART 302', 'ART 302', 'ART 302', 'ARTI01', 'ART 302', 'ART 302', 'ART 302']

Patent US4231087 - Microprocessor support system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Web History | Sign inAdvanced Patent SearchPatentsThe disclosed microprocessor support system provides a total "laboratory" environment for developing and testing application software as well as for debugging the microprocessor-based application machine itself. The microprocessor support system contains a time shared minicomputer equipped with a full...http://www.google.co.uk/patents/US4231087?utm_source=gb-gplus-sharePatent US4231087 - Microprocessor support systemPublication numberUS4231087 APublication typeGrantApplication number05/952,278Publication date28 Oct 1980Filing date18 Oct 1978Priority date18 Oct 1978InventorsDennis J. HunsbergerCharles E. NahabedianThomas M. QuinnJames H. VanOrnumOriginal AssigneeBell Telephone Laboratories, IncorporatedU.S. Classification714/25714/E11.179International ClassificationG06F11/30Cooperative ClassificationG06F11/30European ClassificationG06F 11/30ReferencesPatent Citations (5)Non-Patent Citations (1)Referenced by (50)External LinksUSPTOUSPTO AssignmentEspacenetMicroprocessor support systemUS 4231087 AAbstract The disclosed microprocessor support system provides a total "laboratory" environment for developing and testing application software as well as for debugging the microprocessor-based application machine itself. The microprocessor support system contains a time shared minicomputer equipped with a full set of peripherals which functions as the main or operating system. A data link connects this operating system with test equipment located at the site of the application machine. This test equipment consists of a field test unit which provides an interface between the application machine, a local keyboard terminal and the operating system such that an engineer at the site of the application machine has access through the field test unit to both the microprocessor-based application machine and the operating system with its sophisticated hardware and software resources to assist in developing and testing application software, as well as debugging the application machine itself.
We claim: 1. A processor support system for providing maintenance and software development for an application system which is controlled by an application processor via data, address, and control buses, wherein said processor support system comprises: computer means for running an operating system to generate and store software for said application system; field test unit means connected between said computer means and said application system for interfacing said computer means with said application system, wherein said field test unit means comprises: program store means for storing control instructions generated by said computer means for regulating the operation of said field test unit means; processor means for controlling the operation of said application system; memory means for storing said software generated by said computer means and written in said memory means by said computer means; interface means responsive to said processor means and directly connectable to said application system data, address, and control buses for connecting said application processor to said memory means; field test unit bus means connected to said program store means and to said processor means for applying said control instructions to said processor means; and wherein said processor means is responsive to said control instructions for directing said application processor via said interface means to execute said software stored in said memory means.
2. The invention of claim 1 wherein said field test unit means includes: terminal means for providing an engineer with data access to said processor support system; access means for transmitting input data from said terminal means on said data link to said computer means; and wherein said computer means are responsive to said input data to generate application software for said application system.
3. The invention of claim 1 wherein said interface means includes: supervision means responsive to said processor means and connected to said application system data, address, and control bus for monitoring and driving said application system data, address, and control bus.
4. The invention of claim 3 wherein said supervision means includes transfer trace means connected to said interface means and responsive to signals appearing on said application system data, address, and control bus for storing data representative of the program branches taken by said application processor in the execution of said application software.
5. The invention of claim 3 wherein said supervision means includes: matcher means connected to said field test unit data, address, and control bus means and responsive to programming signals applied to said field test unit data, address, and control bus means by said processor means for storing said programming signals; and wherein said matcher means are connected to said interface means and are responsive to signals appearing on said application system data bus for generating a match indication signal whenever said signals appearing on said application system data are identical to said programming signals stored in said matcher means.
6. The invention of claim 5 wherein said matcher means includes Nth pass counter means responsive to said programming signals for storing a count indication; wherein said matcher means decrements said count indication stored in said Nth pass counter means whenever said signals appearing on said application system data bus are identical to said programming signals stored in said matcher means; and wherein said matcher means generates an Nth pass match indication signal when said count indication stored in said Nth pass counter means equals zero.
7. The invention of claim 6 wherein said supervision means includes: elapsed time clock means responsive to said match indication signal for indicating the amount of real time elapsed between subsequent appearances of said match indication signal.
8. The invention of claim 3 wherein said supervision means includes: buffer means connected to said application system data, address, and control buses for transmitting all signals appearing on said application system data, address, and control buses to said access means; and wherein said access means is additionally responsive to said buffer means for transmitting said signals appearing on said application system data, address, and control buses to said computer means via said data link for storage.
9. The invention of claim 1 wherein said computer means includes a time-shared computer connectable to a plurality of field test unit means.
11. A processor support system for providing hardware debugging and software development capabilities for an application system which contains both a memory device and an application processor which processor drives data, address, and control buses of said application system, wherein said microprocessor support system comprises: computer means responsive to control signals input from a user terminal for running an operating system to generate control instructions and to manipulate data; field test unit means connected to said computer means by a data link and directly connected to said application system for ordering the flow of said data between said computer means and said application system; wherein said field test unit means includes: field test unit data, address, and control bus means for interconnecting the various circuits of said field test unit means; program store means connected to said field test unit data, address, and control bus means for storing said control instructions generated by said computer means to regulate the operation of said field test unit means; data receiver means connected to both said data link and said field test unit data, address, and control bus means, wherein said data receiver means are responsive to said computer means transmitting said control instructions to said field test unit means via said data link for writing said control instructions into said program store means via said field test unit data, address, and control bus means; processor means connected to said field test unit data, address, and control bus means and responsive to said control instructions stored in said program store means for driving said field test unit data, address, and control bus means; memory means connected to said field test unit data, address, and control bus means for storing data generated by said application system; interface means connected to said field test unit data, address, and control bus means and directly connectable to said application system data, address, and control buses for providing bidirectional data transfer between said application system data, address, and control buses and said memory means via said field test unit data, address, and control bus means in response to control signals transmitted to said processor means to said interface means via said field test unit data, address, and control bus means; and data transmission means connected to both said data link and said field test unit data, address, and control bus means and responsive to said processor means for transmitting said data from said memory means to said computer via said data link.
12. The invention of claim 11 wherein said field test unit means includes transceiver means responsive to said processor means for transmitting data stored in said memory means to said computer means via said data link and for receiving data transmitted by said computer means via said data link.
13. The invention of claim 12 wherein said field test unit means includes: terminal means for providing an engineer with data access to said field test unit; and input means connected to said field test unit data, address, and control bus means and responsive to input data entered into said terminal means for storing said input data in said memory means.
14. The invention of claim 11 wherein said processor means is responsive to said control instructions for concurrently enabling the transfer of data between said interface means and said memory means and between said memory means and said computer means.
FIELD OF THE INVENTION This invention pertains to a microprocessor-based application system and in particular to a microprocessor-based field test unit connected to the application system which enables an engineer at the site of the application system to access a centrally located minicomputer equipped with sophisticated hardware and software resources to assist in the on-site development and testing of application software for the application system. In addition, the microprocessor-based field test unit enables the on-site engineer to perform hardware testing routines to debug the application system hardware.
BACKGROUND OF THE INVENTION The availability of inexpensive microprocessors has caused a proliferation of microprocessor-based application systems, since the microprocessor enables the circuit designer to place a great deal of intelligence in the application system at little cost. However, this configuration has introduced a new cost into system development, and that is the cost of developing and maintaining application software. As applications become increasingly more sophisticated, the software required will become more complex and its development will become more costly.
SUMMARY OF THE INVENTION The disclosed microprocessor support system consists of a set of hardware and software tools designed to provide a total "laboratory" environment for developing and testing application software as well as debugging the application system itself. The microprocessor support system contains a centrally located time-shared minicomputer equipped with a full complement of peripherals which function as the main or operating system. The time-shared minicomputer is provided with a data link, which enables the operating system to communicate with test equipment located at the site of the application system. This remotely located test equipment consists of a field test unit which interfaces to the time-shared minicomputer via a data link, to a local keyboard terminal, and to the application system. Thus, an engineer at the application system has access, through the field test unit, to both the application system and the time-shared minicomputer operating system with its associated sophisticated operating system and hardware resources to assist him in developing and testing the application software as well as in debugging the application system hardware.
GENERAL DESCRIPTION--FIGS. 1 and 2 FIGS. 1 and 2 show one embodiment of our invention in block diagram form wherein a time-shared minicomputer 103 is connected via field test unit 206 to an application system 210. Time-shared minicomputer 103 can receive input data from keyboard terminal 100 and/or computer cards 101 and/or tape 102 and/or any other suitable computer input device. These devices are all connected by cable 114 to time-shared minicomputer 103 wherein machine language instructions are generated in standard fashion from data received from these various input devices under control of standard computer programs. The generation of machine language instructions is accomplished on time-shared minicomputer 103 in well known fashion by having a high level language input via the editor program whose output is processed by the compiler program whose output in turn is processed by the assembler program to generate relocatable machine language instructions which are processed by a loader program to produce a final set of machine language instructions executed by application system 210. Since minicomputer 103 operates on a time-shared basis, a plurality of engineers may concurrently avail themselves of the time-shared minicomputer facilities to each generate a set of machine language instructions for application system microprocessor 212. However, for convenience sake, only one set of peripheral devices and only one data-modem/field-test-unit combination are shown. In an actual operating situation, a plurality of field test units would be connected to time-shared minicomputer 103 with each field test unit controlling an associated application system.
TIME-SHARED MINICOMPUTER 103--FIG. 1 Time-shared minicomputer 103 can be any one of the numerous commercially available minicomputer systems. In the disclosed embodiment, applicants employed a Digital Equipment Corporation PDP 11/70 computer, which is described in the Digital Equipment Corporation's "PDP 11/70 Processor Handbook", copyrighted in 1975. As previously mentioned, numerous peripheral devices are connected to time-shared minicomputer 103 to provide various forms of input and output. For the sake of simplicity, emphasis will be placed on the use of a printing keyboard terminal 100 which is employed as both an input and an output device. Thus, an engineer at the main location can communicate with time-shared minicomputer 103 via keyboard terminal 100.
TIME-SHARED MINICOMPUTER OPERATING SYSTEM Time-shared minicomputer 103 is, of course, supplied with an operating system program as well as an associated set of editor, compiler, assembler and loader programs. The operating system program employed in the disclosed embodiment is the commercially available UNIX program which is described both in an article by D. M. Ritchie and K. L. Thompson entitled "The UNIX Time-sharing System", which appeared in Volume 17, Number 17 of the Communications of the ACM on pages 365-375 in July, 1974 as well as in articles by the same authors and their associates which appeared in Volume 57, Number 6 of the Bell System Technical Journal on pages 1905-2209 in July, 1978. The UNIX program provides the basic operating system on which the editor, compiler, assembler and loader programs can be run. The UNIX system also provides the documentation support for these programs, thereby enabling the engineer to obtain a hard copy listing of the programs run as well as the changes implemented therein. The compiler program employed in the disclosed embodiment is a version of the SMAL language which is described in an article entitled "SMAL -A Structured Macro/Assembly Language for a Microprocessor" by C. Popper in the Digest of Papers for IEEE COMPCON, August, 1974, pages 147 to 151. The SMAL2 language combines the ease of using a high level compiler with the efficiency of an assembly language. The SMAL2 language has a rich set of control structures (If-Else, While, Do-While, Switch) which allow a programmer to use natural compiler notations to describe algorithms. The SMAL2 compiler has been tailored to be used in conjunction with the Intel Corporation 8080-type microprocessor which microprocessor is described in the Intel Corporation's "8080 Microcomputer Systems User's Manual" copyrighted in 1976. Thus, the output of the SMAL2 compiler is then converted to system language for use in the 8080-type microprocessor by standard assembler and loader programs, which are well known in the art, to create an absolute addressed object module and its associated symbol table. The object module consists of the machine language instructions for the 8080-type microprocessor.
APPLICATION MACHINE 210 Application system 210 can be any of the multitude of microprocessor controlled systems presently found in a business environment, such as a point of sale terminal, a ticket system, a telephone switching sytem, etc. The one required element in application system 210 is that it contains a microprocessor 212. In the present disclosure, application system microprocessor 212 will be assumed to be an Intel Corporation model 8080 microprocessor. The model 8080 microprocessor, in most applications, requires the use of buffers to supply the required drive current to activate the various control leads, data and address buses. Therefore, it is also assumed that application system microprocessor 212 is buffered in the standard fashion well known in the art. Application system microprocessor 212 is also connected to Control circuit 211 which comprises various control and "sanity" circuits which are also referred to in the literature variously as recovery circuits, execution control circuits, or processor fault monitoring circuits. The sanity circuit functions to prevent external conditions and/or input control signals from disabling the associated microprocessor by placing it in a nonrecoverable state. The sanity circuit monitors the input signals as well as the microprocessor operation and acts to reset or rescue the microprocessor whenever it exhibits a berrant operation or whenever the input signals would improperly disrupt normal microprocessor operation. Thus, any external test system that attempts to monitor, and/or control, and/or debug the operation of application system microprocessor 212 must first deal with the sanity circuit which may be operating at cross purposes with the external test system.
PROGRAM TRANSFER In the disclosed embodiment, testing of application system 210 is accomplished by the engineer activating time-shared minicomputer 103 through keyboard terminal 100 or 204 to execute a monitor program which will load the machine language instructions into field test unit 206 via the data channel between time-shared minicomputer 103 and field test unit 206. The data channel consists of a pair of data modems 205, 130 and a bidirectional data link 225, such as a telephone line, between time-shared minicomputer 103 and field test unit 206. Data is transferred from time-shared minicomputer 103 to a standard 300 baud data modem 130 on conductors 117 and data modem 130 forwards this data to data modem 205 of field test unit 206 via data link 225. In return, data modem 205 of field test unit 206 transfers data to data modem 30 via data link 225 and date modem 130 forwards this data to time-shared minicomputer 103 on conductors 116. The monitor program in time-shared minicomputer 103 orders the data flow to and from data modem 130 over connections 116 and 117. Therefore, machine language instructions generated on time-shared minicomputer 103 can be transferred to field test unit 206 via data modem 130 and data link 225.
FIELD TEST UNIT 206 Field test unit 206 contains numerous circuits which are all connected together by a system of data, address and control buses. In particular, common address bus CAB, common data bus CDB, and common control bus CCB, connect the memory circuits--Common Memory 221 and Mimic Memory 215--to the other field test unit circuits by way of Arbiter circuit 202. Also, the application system control bus TCB and address and data bus TADB, as extended to field test unit 206 by Interface circuit 216, are routed to the various control and data collection circuits of field test unit 206. Finally, field test unit internal control bus FCB and address and data bus FADB are directly connected to all field test unit circuits for control and data transfer purposes. Thus, field test unit 206 is comprised of a number of somewhat independent control, data storage and interface circuits which circuits operate cooperatively and communicate with each other via the above-mentioned system of buses.
HARDWARE MAINTENANCE The use of FTU microprocessor 209 in field test unit 206 enables an engineer to run sophisticated hardware testing routines on field test unit 206 to debug hardware problems in application system 210. The data link connected to time shared minicomputer 103 provides access to a complete file of debugging routines stored in time-shared minicomputer 103, any of which can be transmitted via the data link to field test unit Program Store 207. FTU microprocessor 209 can then execute the debugging routines, monitoring application system 210 with Matchers and Elapsed Time Clock 208, Transfer Trace 203, and Mimic Memory 215 to detect any flaws in application system 210 hardware operation. Alternatively, the data transmitted via data link 225 to FTU 206 can be placed in Common Memory 221. Any debugging routines stored in Common Memory 221 can be accessed by application system microprocessor 212. Thus, field test unit 206 can cause application system microprocessor 212 to execute various exercise and trouble detection routines stored in Common Memory 221 to thereby isolate and detect hardware faults in application system 210.
SOFTWARE DEVELOPMENT In somewhat analogous fashion, field test unit 206 can be utilized to develop and test software for application system 210. As previously mentioned, application software can be stored in Common Memory 221. Application system microprocessor 212 can access this software by having Arbiter 202 connect extended application system buses TADB, TCB to common buses CAB, CDB, CCB thereby enabling application system 210 to access and execute the instructions stored in Common Memory 221. The new application software can then be monitored by the use of hardware/software debugging aids provided by FTU 206. Monitoring may be controlled at the site of application system 210 via local keyboard terminal 204 which is connected to field test unit 206 via a standard EIA Serial Interface 204 or monitoring may be controlled remotely over data link 225 by keyboard terminal 100 connected to time-shared minicomputer 103.
LABORATORY DEVELOPMENT While all the previous discussion has been concerned with a remotely located application system, the disclosed microprocessor support system is also capable of being operated in the same location as the application system. For example, for the initial stages of the laboratory development of an application system the disclosed microprocessor support system can be used to generate the software for the new system as well as debug prototype hardware. In this situation, the data link between time-shared minicomputer 103 and FTU 206 would be simply a multiwire cable, directly connecting field test unit 206 to time-shared minicomputer 103. Also, application system's ROM/PROM memory would be replaced by a writable program store such as RAM for continual program changes. Thus, the disclosed microprocessor support system can be configured and operated in a number of ways depending on the needs of the engineer.
DETAILED DESCRIPTION--FIGS. 3-23 Drawing FIGS. 3 through 23 disclose the details of the microprocessor support system as shown in FIGS. 1 and 2, and illustrate how the various elements of our inventive embodiment cooperate to provide the microprocessor support system. For simplicity sake, the block diagram of field test unit 206 (FIGS. 1 and 2) have been labeled to show which of FIGS. 3-23 relate to each block of circuitry in field test unit 206. Thus, while the following description delves into the details of each block of field test unit circuitry and its associated figures, the reader will find it helpful to refer to FIGS. 1 and 2 to obtain an overview and to keep the various elements of the disclosed microprocessor support system in perspective.
FIELD TEST UNIT 206 For the sake of clarity, the details of field test unit 206 will now be explored. Field test unit 206 is interposed between time-shared minicomputer 103 and application system 210 and serves to control the operation and testing of application system 210 while also collecting test data and ordering this data for transmission to time-shared minicomputer 103 via the data link. Field test unit 206 is comprised of a Receiver circuit 201, Arbiter circuit 202, FTU microprocessor 209, memory 207, 221, 215, Matcher and Elapsed Time Clock circuit 208, Transfer Trace and PROM Programmer circuit 203, Interface circuit 216, Sanity and Receiver circuit 213. At this point it is important to clarify the terminology employed herein with respect to FTU microprocessor 209. By FTU microprocessor 209, we mean all the circuitry shown on FIGS. 8 and 9. That is, Central Processing Unit 801 and all its associated clock, temporary memory, buffer, driver, decoding and interrupt circuitry. Thus, FTU microprocessor 209 constitutes a complete small computer and references to FTU microprocessor 209 will typically indicate a standard "computer" operation as opposed to some minutiae of circuit operation. These references, of course, will be to well-known standard computer functions, the detailed description of which is beyond the scope of this application.
RECEIVER CIRCUIT 201--FIG. 3 Data from data modem 205 is received in FTU 206 by Receiver circuit 201. A diagram of this circuit is shown in FIG. 3. EIA level signals originated by time-shared minicomputer 103 are received from data modem 205 on lead RXDD and level shifter 304 converts these signals to the TTL levels used in FTU 206. The TTL level serial data stream from level shifter 304 serves as input to an Intel type 8251 Universal Asynchronous Receiver/Transmitter (UART) 302 which converts the serial data stream into 8-bit words which are placed on FTU data bus (FADB) leads DO--D7 upon UART 302 receiving enable signals from data modem 205 on lead CTS*. Since UART 302 operates bidirectionally, 8-bit words of outgoing data are also taken from leads DO--D7 and are converted into a serial data stream and transmitted to data modem 205 on lead TXD via level shifter 301. In the case of incoming data from data modem 205, when UART 302 has assembled an 8-bit parallel word, (a byte), it generates a high signal on output RXRDY* which thereby places low a signal via inverter 305 on lead LEVEL 4. This low signal on lead LEVEL 4 is carried by field test unit control bus FCB to field test unit microprocessor circuit 209 where it activates priority interrupt control 901 shown on FIG. 9. FTU microprocessor 209 and its associated FTU Program Store 207 constitute an 8-bit parallel stored program controller which handles all internal FTU data movement and the interpretation of FTU user directives. Therefore, upon receiving an interrupt from UART 302 via priority interrupt control 901 on lead INT, CPU 801 of FTU microprocessor circuit 209 will place a low enable signal on lead UARTI01, thereby causing UART 302 to place the received data on the FTU data bus leads D0-D7. Since UART 302 has insufficient power to drive FTU data bus FADB directly, bidirectional buffers 303 are interposed between UART 302 and FTU data bus FADB to provide the requisite drive current. The directionality of the buffer operation is also controlled by control data circuit 805 of FTU microprocessor circuit 209 via leads FI/OR* and FI/OW* of FTU control bus FCB which indicate read/write the data bus, respectively. When each 8-bit word of data is placed on FTU data bus leads D0-D7, CPU 801 will read the incoming data and place it in temporary storage which comprises RAM0-7 (910-917) of FTU microprocessor 209 shown on FIG. 9 until 256 bytes have been received. FTU microprocessor circuit 209 then performs a standard checksum operation on the data block to assure its accuracy and moves the block of data to one of three destinations depending on previously input user directives. These three destinations are: (1) FTU Program Store 207 consisting of RAM memory 701 shown on FIG. 7; (2) Application system's RAM memory (not shown) residing in application system 210; (3) Common Memory 221--a 3K block of RAM memory residing in FTU 206, but accessable to both FTU microprocessor 209 and application system microprocessor 212.
DATA STORAGE--FTU PROGRAM STORE 207 Since it is assumed that the user had issued a directive to FTU 206 indicating that incoming serial data was a program to be executed by FTU 206, FTU microprocessor 209 will then place the received blocks of data in RAM memory 910-917 of FTU microprocessor 209. This is accomplished by FTU microprocessor 209 generating program address information and placing this information on leads AD0-15. This, coupled with memory write enable signals appearing on leads FMEMW* and WROT*, will cause the data appearing on leads D0-7 to be stored in the appropriate locations in RAM 701. When the data transmission from time-shared minicomputer 103 is completed, the user would direct FTU microprocessor 209 to begin executing the program it had received.
SANITY AND RECEIVER CIRCUIT 213, INTERFACE CIRCUIT 216--FIG. 6 As previously mentioned, the program that was just stored in FTU Program Store 207 contains instructions for FTU 206 to monitor certain address leads of application system 210. Interface circuit 216 and Sanity and Receiver Circuit 213 function to provide that capability.
MATCHER CIRCUIT 208 (FIGS. 10-12) Matcher circuit 208 contains four data and/or address matchers. Each of these matchers are "bit programmable" in that "don't care" conditions can be specified in the data and address fields when the user is setting up the match to monitor application system 210.
RAM 813--FIGS. 18-20 The basic module used in the programmable bit comparison section of the Matcher circuit is a 16 word by four bit RAM. To understand how the matchers operate, one must first understand how this RAM device can function as a four-bit programmable comparator. FIG. 18 illustrates the comparison circuitry used to monitor the first four bits of application system 210 address bus leads TAB0-TAB3 of bus TADB. The 16 word addresses of RAM 813 can be thought of as representing one of the 16 possible unique states of the four address lines (TAB0-TAB3). The four bits in each word of the RAM provide four independent programmable outputs for each of the 16 unique address line states. These bit outputs are used as the match indicators M1-M4.
MATCHER ACTION SELECT AND STROBE CIRCUITS As previously mentioned, the user may specify that one of several actions (Halt, Status, Wait and Pass) occur when a matcher is triggered. The user must also specify if the match is to take place when application system 210 is doing a memory read as memory write or a I/O read or I/O write. In addition the user may also specify that any or all of the matchers be disabled until a TTL signal using edge input is applied to the matcher's external input connector on the front panel of FTU 206. Another option available to the user is the match on N.sup.th pass although this option is associated with Matcher 1 only. This option allows the user specified action to occur on the N.sup.th time Matcher 1 is triggered. All of the control for implementing the above specified options is provided by the matcher action select and strobe circuitry shown in FIG. 11.
MATCHER ENABLE AND PERIPHERAL CONTROL CIRCUITS--FIGS. 17-21 This section of Matcher 208 allows the user to enable/disable any matcher and/or debugging aid such as Transfer Trace 203 or Mimic Memory 215 when a match is triggered.
ELAPSED TIME CLOCK 1107--FIG. 11 The use of the peripheral control signals can be illustrated by describing their control of Elapsed Time Clock 1107. This feature of FTU 206 allows the user to measure the time it takes application system 210 to execute a program. The feature is invoked by setting one matcher to trigger and start Elapsed Time Clock 1107 at the beginning of the program segment and another matcher to trigger at the end of the segment of code and stop Elapsed Time Clock 1107. By specifying that a matcher will enable Elapsed Time Clock 1107, a user will cause a logic "1" to be stored in bit D4 of the matchers peripheral enable word. For example, FIG. 21 shows the contents of Matcher Control RAM 1103 where Matcher M1 has been programmed to start Elapsed Time Clock 1101. When this matcher triggers and its peripheral enable word is loaded into the output register of RAM 1103 (as previously described) it will switch the enable input of Elapsed Time Clock 1107 to a logic "1" state, allowing the counter to count. The matcher set to stop Elapsed Time Clock 1107 will have a logic "0" stored in bit D3 of its control word. When this second matcher triggers the D3 output of RAM 1103 will go to a logic "0" and stop the Elapsed Time Clock 1107. FTU microprocessor 209 can then read the contents of the Elapsed Time Clock 1107 and display this information to the user.
TRANSFER TRACE The Transfer Trace 203 records a "from", "to" history of the last 128 program branches executed by the application microprocessor. The trace can be turned ON and OFF by matcher 208 via the TFTL control line. Matcher 208 control of the Transfer Trace parallels that of the ETC, previously described. The combination of Matcher 208 control and dual port access to the trace memories allows the Transfer trace 203 to be used without disrupting the service provided application machine 210.
DATA STORAGE--COMMON MEMORY 221--FIG. 16 While we have just described how field test unit 206 could monitor the activity of application machine 210, a far more powerful tool is the use of field test unit 206 to cause application microprocessor 212 to execute program instructions stored in Common Memory 221. This is accomplished by employing time-shared microcomputer 103 in well-known fashion to generate program instructions for application microprocessor 212. This data is transmitted from time-shared minicomputer 103 to field test unit 206 as described above. However, this data would be stored in Common Memory 221.
MEMORY MAP--FIG. 15 Both application system microprocessor 212 and FTU microprocessor 209 have a maximum direct addressing capability of 64 K bytes of memory. Since FTU 206 is required to read and write all of the application system memory as well as its own, it was necessary to develop an extended memory addressing scheme for FTU 206. This scheme uses an extended address bit (EA15) and the high address bit (AD15) of FTU 206 to divide the FTU memory space into three 32 K byte blocks which provides a total addressing capacity of 96 K bytes as shown in FIG. 15. The 0-32 K (AD15-0, EA15=0) address space of FTU microprocessor 209 contains all of the FTU program store, Random Access Memory and memory mapped I/O addresses. When FTU microprocessor 209 address above 32 K (AD15=1) the memory accessed will be that of the application system. Addresses in the 32 K;14 64 K (AD15=1, EA15=0) block of FTU memory are mapped into the 0-32 K address space of application system 210. Addresses in the 64 K-96 K (AD15=1, EA15=1) block of FTU memory are mapped into the application system 32-65 K address space. To access the application system memory, FTU 206 issues a hold request by setting bit 3 of Latch 680. A hold knowledge signal (HOLDACK) from application system 210 will then indicate that the system has tri-stated its buses and FTU 206 may take control of them. HOLDACK will cause the output of gate 263 to go low resulting in buffers 609-624 being enabled in the direction allowing FTU Address Bus leads AD0-AD14 and EA15 to control the application system address bus. During the reading or writing of application system memory, the extended application system data bus TDB0-7 is connected to FTU data bus FADB as will be explained later in the text. Gates 671-672 will enable the FTU read and write strobes (FMEMR* , FMEMW* ) to control the application system read and write strobe leads whenever FTU micprocessor 209 reads or writes memory above its 32K address space (AD15=1). Since in this particular situation, application system 210 has memory mapped I/O, FTU 206 is capable of reading and writing I/O ports in the same manner in which it writes application system Memory.
MIMIC MEMORY 215--FIG. 16 Asynchronous Arbiter 202 provides a similar type of multiprocessor access to a 4 K byte block of RAM used as a Mimic Memory 215. While Common Memory 221 always resides in the 60--63 K address space of application system 210, the specified address of Mimic Memory 215 can be changed by user request. The only requirement being that the specified address be on a 4 K boundry of application system 210 address space. Mimic Memory 215 can be read or written (initialize or monitored) by FTU microprocessor 209; however, it functions as a write only memory in reference to application system microprocessor 212. Once initialized to a 4 K boundry and enabled, any data written to a mimicked 4 K block of application system memory will also be written into Mimic Memory 215. Subsequent disabling of Mimic Memory 215 at some point in the application system program enables the user to capture the state of a 4 K block of the application system memory. The user may examine the contents of this 4 K block on local terminal 204 or transmit its contents to time-shared minicomputer 103 for further analysis.
ARBITER AND ADDRESS DECODING CIRCUIT 202 (FIGS. 4-5) FIGS. 4--5 shows the Arbiter and address decoding circuit 202 used to control Common Memory 221 and Mimic Memory 215 of FTU 206. If application system microprocessor 212 attempts to read or write Common Memory 221 (60-63K), it will activate the appropriate ones of address leads of TAB0--TAB15 and these activated leads will be recognized by address decoder 501 on FIG. 5. Address decoder 501 generates a high output signal indicating that application system 210 is attempting to access Common Memory 221 and this signal in combination with a memory read/write signal on lead TSMEMR/TSMEMW activates gate 512/511 which in turn activates gate 513 causing the application system memory request lead (TSMREQ*) to go low, thereby requesting control of Common Memory 221. This request is received by asynchronous Arbiter circuit 500 which determines whether application system 210 or FTU 206 will be enabled to access Common Memory 221. The actual embodiment of Arbiter 500 comprises gates 520-530 and differs from the Pierce et al Arbiter referred to above essentially only in the selection of logic gates employed. Assuming that FTU 206 is neither requesting nor in control of Common Memory 221, the TSMREQ* signal will force the output of gate 521 to go high, resulting in the output of gate 525 going high thereby causing the application system control (TSCNTL*) output of gate 528 to go low. The presence of the TSCNTL* signal indicates that application system 210 currently has been given control of Common Memory 221. Also, the high signal on lead TSCNTL, coupled with the previously discussed high output signal from address decoder 501, activates gate 503 which turns on gate 504, causing the board select lead BS1* to go low thereby enabling the 3K Common Memory 221. If at this time FTU 206 were to attempt to access Common Memory 221, it would place the address of the Common Memory 221 on address leads AD0-AD15, F24K, and EA15, thereby enabling address decoder 514 which detects the memory access request on the address leads. The output of address decoder 514 coupled with an FTU memory read/write request on lead FMEMR*/FMEMW*. However, application system 210 has control of Common Memory 221 and Arbiter 500 blocks FTU 206 from accessing Common Memory 221 by disabling gate 525 thereby preventing FTU 206 from receiving a control enable signal on lead FCNTL*. Instead, the low signal on lead FMREQ* results in the FTU Ready (FRDY*) output of gate 529 going low, which causes FTU microprocessor 209 to enter a wait state (see Intel 8080 System User's Manual). When application system 210 completes the read or write to Common Memory 221, the TSMREQ* signal would go high allowing the output of gate 522 to go high resulting in the FTU control (FCNTL*) output of gate 527 going low. The presence of the FCNTL* signal indicates that FTU 206 is in control of Common Memory 221. Additionally, the low signal on lead FCNTL* is inverted by gate 502 and coupled with the address signal on lead F24K* activates gate 505 which turns on gate 504 causing the board select lead BS1* to go low thereby enabling the 3K Common Memory 221. It can be easily seen from this example that if the situation were reversed and FTU 206 had control of the memory (FCNTL* were low) after which application system 210 attempted to access Common Memory 221, the application system ready signal (lead TSRDY* gate 526) would switch low causing application system 210 to enter a wait state.
FTU FROM PROGRAMMER 1301 FTU PROM Programmer 1301 provides the capability to program PROMs with data downloaded from time-shared minicomputer 103, or entered manually from FTU keyboard terminal 204.
FTU PROCESSOR CIRCUIT--FIGS. 8 AND 9 As previously mentioned FTU 206 is controlled by an 8-bit stored program controller. This controller is built around the Intel type 8080 microprocessor 209, and its associated Intel type 8224 clock 802, Intel 8238 bus controller 805 and Intel 8214 interrupt controller, as illustrated in FIGS. 8 and 9. (Reference Intel 8080 Microcomputer Systems User's Manual). The microprocessor uses 16 Intel 2708 PROMS to provide its 16K byte to program store. Eight Intel type 2101-1 RAMS and sixteen type 9130 RAMS provide the microprocessor with 9K of buffer and variable storage memory. The controller is implemented on two circuit packs. The first circuit pack contains the Intel 8080 microprocessor 801, eight type 2708 PROMS 920-927 (8K of PROM), eight type 2101-1 RAMS 910-917 (1K of RAM) and a serial EIA Interface 807-810. The block memory address decoding for the PROM and RAM is performed by address decoding logic 493 on FIG. 4. The Disable RAM (DISRAM) and Enable ROM (ENROM) signals are gated to place the 8K of ROM from 0 to 8K in FTU Memory Space (see FTU Memory Map FIG. 15) and the 1K of RAM in the FTU 31-32K address space. The second circuit pack used to implement the controller is the FTU Program Store board 207. FIG. 7 is a block diagram of the Program Store board, which contains the remaining 8K of ROM and 8K of RAM used by the controller. All address decoding for the 8K of PROM and 8K of RAM is performed on the board by the address decoder. The PROM occupies the 8 to 16K block of FTU memory and the RAM occupies the 16-24K block (see FTU Memory Map FIG. 15).
BRIEF DESCRIPTION OF THE DRAWING The operation of the present invention will be more fully apparent from the following description of the drawing, in which:
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