Source: http://www.google.com/patents/US20070099328?dq=Xerox+%2B+%22centroid
Timestamp: 2017-02-20 09:05:49
Document Index: 541637366

Matched Legal Cases: ['art. 23', 'art 308', 'art 308', 'art 308', 'art 306', 'art 306', 'art 306', 'art 308', 'art 308', 'art 308', 'art 308', 'art 308', 'art 308', 'art 308']

Patent US20070099328 - Semiconductor device and interconnect structure and their respective ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor device is described, including a substrate, a transistor, a hard mask layer and an anti-reflection layer. The substrate includes a first area and a second area, wherein the second area includes a photosensing area. The transistor is disposed on the substrate in the first area and the...http://www.google.com/patents/US20070099328?utm_source=gb-gplus-sharePatent US20070099328 - Semiconductor device and interconnect structure and their respective fabricating methodsAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20070099328 A1Publication typeApplicationApplication numberUS 11/163,812Publication dateMay 3, 2007Filing dateOct 31, 2005Priority dateOct 31, 2005Also published asUS20080111160Publication number11163812, 163812, US 2007/0099328 A1, US 2007/099328 A1, US 20070099328 A1, US 20070099328A1, US 2007099328 A1, US 2007099328A1, US-A1-20070099328, US-A1-2007099328, US2007/0099328A1, US2007/099328A1, US20070099328 A1, US20070099328A1, US2007099328 A1, US2007099328A1InventorsYuan-Sheng Chiang, Hsuan-Hsu ChenOriginal AssigneeYuan-Sheng Chiang, Hsuan-Hsu ChenExport CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (57), Classifications (7), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and interconnect structure and their respective fabricating methods
US 20070099328 A1Abstract
A semiconductor device is described, including a substrate, a transistor, a hard mask layer and an anti-reflection layer. The substrate includes a first area and a second area, wherein the second area includes a photosensing area. The transistor is disposed on the substrate in the first area and the hard mask layer over the substrate in the second area. The anti-reflection layer is disposed between the hard mask layer and the substrate. Images(7) Claims(32)
1. A semiconductor device, comprising: a semiconductor substrate including a first area and a second area, wherein the second area comprises a photosensing area; a transistor on the substrate in the first area; a hard mask layer over the substrate in the second area; and an anti-reflection layer between the hard mask layer and the substrate. 2. The semiconductor device of claim 1, wherein the hard mask layer comprises SiO, SiC, BPSG, PSG, FSG or poly-Si. 3. The semiconductor device of claim 1, wherein the hard mask layer has a thickness of 100-1000 Å. 4. The semiconductor device of claim 1, wherein the anti-reflection layer comprises SiN or SiON. 5. The semiconductor device of claim 1, wherein the anti-reflection layer has a thickness of 400-2000 Å. 6. The semiconductor device of claim 1, further comprising a salicide layer on a source/drain region and a gate of the transistor. 7. The semiconductor device of claim 6, wherein the salicide layer comprises WSi, TiSi, CoSi, MoSi, NiSi, PdSi or PtSi. 8. The semiconductor device of claim 1, further comprising a sacrificial layer between the anti-reflection layer and the substrate. 9. The semiconductor device of claim 8, wherein the sacrificial layer comprises SiO. 10. The semiconductor device of claim 8, wherein the sacrificial layer has a thickness of 10-300 Å. 11. A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate that includes a first area and a second area, wherein the first area is disposed with a transistor on the substrate and the second area includes a photosensing area; forming an anti-reflection layer over the substrate; forming a patterned hard mask layer on the anti-reflection layer, the patterned hard mask layer covering the second area; and conducting a wet-etching step using the patterned hard mask layer as a mask to remove the anti-reflection layer outside the second area. 12. The method of claim 11, wherein the step of forming the patterned hard mask layer comprises: forming a hard mask material on the anti-reflection layer; forming a photoresist layer on the hard mask material; conducting lithography and etching steps to pattern the hard mask material; and removing the photoresist layer. 13. The method of claim 12, wherein the hard mask material is formed through PECVD. 14. The method of claim 12, wherein the hard mask material comprises SiO, SiC, BPSG, PSG or FSG. 15. The method of claim 12, wherein the hard mask material comprises poly-Si. 16. The method of claim 15, further comprising a step of removing the patterned hard mask layer after the anti-reflection layer outside the second area is removed. 17. The method of claim 11, wherein an etchant used in the wet-etching step comprises hot phosphoric acid. 18. The method of claim 11, wherein the anti-reflection layer is formed through PECVD. 19. The method of claim 11, further comprising a step of forming a sacrificial layer on the substrate before the anti-reflection layer is formed. 20. The method of claim 19, wherein the sacrificial layer is formed though thermal oxidation or PECVD. 21. The method of claim 11, further comprising a step of forming a salicide layer on a source/drain region and a gate of the transistor after the anti-reflection layer outside the second area is removed. 22. An interconnect structure, comprising: a substrate having a conductive part thereon; a dielectric layer on the substrate; an etching stop layer between the dielectric layer and the substrate; and a via plug electrically connected with the conductive part, including a first part in the dielectric layer and a second part in the etching stop layer, wherein a width of the second part is larger than a width of the first part. 23. The interconnect structure of claim 22, wherein the etching stop layer comprises SiN. 24. The interconnect structure of claim 22, wherein the via plug comprises tungsten (W) or aluminum (Al). 25. The interconnect structure of claim 22, further comprising a barrier layer between the via plug and each of the dielectric layer and the etching stop layer. 26. The interconnect structure of claim 25, wherein the barrier layer comprises Ti, TiN or TaN. 27. A method for fabricating an interconnect structure, comprising: providing a substrate with a conductive part thereon; forming an etching stop layer on the substrate; forming a dielectric layer on the etching stop layer; forming a first opening in the dielectric layer, the first opening exposing a portion of the etching stop layer over the conductive part; conducting a wet etching step using the dielectric layer as a mask to form a second opening in the etching stop layer, the second opening exposing the conductive part and being wider than the first opening; and forming a via plug in the first opening and the second opening. 28. The method of claim 27, wherein forming the first opening comprises: forming a correspondingly patterned photoresist layer on the dielectric layer; conducting lithography and etching steps to pattern the dielectric layer; and removing the patterned photoresist layer. 29. The method of claim 27, wherein the step of forming the via plug comprises an atomic level deposition (ALD) process. 30. The method of claim 27, wherein an etchant used in the wet etching step comprises hot phosphoric acid. 31. The method of claim 27, further comprising a step of forming a barrier layer on internal surfaces of the first opening and the second opening after the second opening is formed but before the via plug is formed. 32. The method of claim 31, wherein the barrier layer is formed through PECVD, MOCVD or ionized metal plasma (IMP) deposition.
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to integrated circuit structures. More particularly, the present invention relates to a semiconductor device of sensor type that has a higher sensitivity, to an interconnect structure structurally correlated with the semiconductor device, and to their respective fabricating methods. [0003] 2. Description of the Related Art [0004] Photodiode image sensors have been widely spread recently. A photodiode image sensor includes an array of sensing units (pixels), each of which includes a reset transistor and a photosensing area including a PN-diode coupled to the reset transistor. [0005] On the other hand, the source/drain (S/D) regions and gates of MOS transistors on the sensor chip are usually formed with self-aligned metal silicide (salicide) thereon. To prevent salicide from forming on the photosensing area, a salicide block (SAB) is usually formed covering the photosensing area before the salicide process. [0006] Conventionally, the SAB is formed by firstly depositing on the substrate a silicon oxide (SiO) layer and then removing the SiO layer outside the photosensing area with dry etching. However, since the SiO material on the gate spacer of a transistor cannot be removed completely with dry etching, an extra spacer is formed covering a portion of the S/D regions and adversely affecting the later salicide process. [0007] Moreover, when the SAB is a SiO layer, the light perpendicularly or obliquely incident to the photosensing area has quite a proportion being reflected by the SiO layer, so that the sensitivity of the image sensor is difficult to improve. SUMMARY OF THE INVENTION [0008] Accordingly, this invention provides a semiconductor device of sensor type that has a higher sensitivity. [0009] This invention also provides a method for fabricating a semiconductor device without forming an extra spacer covering a portion of the S/D regions. [0010] The semiconductor device of this invention includes a semiconductor substrate, a transistor, a hard mask layer and an anti-reflection layer. The substrate includes a first area and a second area, wherein the second area includes a photosensing area. The transistor is disposed on the substrate in the first area and the hard mask layer over the substrate in the second area. The anti-reflection layer is disposed between the hard mask layer and the substrate. [0011] According to various embodiments of the above semiconductor device, the hard mask layer may include SiO, silicon carbide (SiC), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), fluorosilicate glass (FSG) or polysilicon (poly-Si), and the thickness thereof may be 100-1000 Å. The anti-reflection layer may include silicon nitride (SiN) or silicon oxynitride (SiON), and the thickness thereof may be 400-2000 Å. A salicide layer may be further disposed on the S/D regions and gate of the transistor, wherein the salicide may include tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), molybdenum silicide (MoSi), nickel silicide (NiSi), palladium silicide (PdSi) or platinum silicide (PtSi). A sacrificial layer may be further disposed between the anti-reflection layer and the substrate, wherein the material of the sacrificial layer may be SiO and the thickness of the same may be 10-300 Å. [0012] The method for fabricating a semiconductor device of this invention is described below. A semiconductor substrate including a first area and a second area is provided, wherein the first area is disposed with a transistor on the substrate and the second area includes a photosensing area. An anti-reflection layer is formed over the substrate, and then a patterned hard mask layer covering the second area is formed on the anti- reflection layer. A wet-etching step is then conducted using the patterned hard mask layer as a mask to remove the anti-reflection layer outside the second area. [0013] According to various embodiments of the above method, the patterned hard mask layer may be formed with the following steps. A hard mask material is formed on the anti-reflection layer, and then a photoresist layer is formed on the hard mask material. Lithography and etching steps are conducted to pattern the hard mask material, and the photoresist layer is then removed. The hard mask material may be formed through plasma-enhanced chemical vapor deposition (PECVD), and may be SiO, SiC, BPSG, PSG or FSG or include poly-Si. When the hard mask material is poly-Si, the above method may further include a step of removing the patterned hard mask layer after the anti-reflection layer outside the second area is removed. In addition, the etchant used in the wet etching step may be hot phosphoric acid. The anti-reflection layer may be formed through PECVD. The method may further include a step of forming a sacrificial layer over the substrate before the anti-reflection layer is formed, wherein the sacrificial layer may be formed though thermal oxidation or PECVD. The method may further include a step of forming a salicide layer on the S/D regions and the gate of the transistor after the anti-reflection layer is patterned, wherein the patterned hard mask layer and the patterned anti-reflection layer together serve as an SAB. [0014] Since the SAB formed on the photosensing area includes an anti-reflection layer and a hard mask layer, the light incident to the photosensing area is reflected less as compared with the prior art that forms SiO as the SAB. Hence, the sensitivity of the image sensor is enhanced. Moreover, since wet etching is utilized to remove the anti-reflection layer outside the second area in the above method of this invention, an extra spacer is not formed on the sidewall of a gate covering a portion of the S/D region. [0015] This invention further provides an interconnect structure that is structurally related to the above semiconductor device of this invention. The interconnect structure includes a substrate with a conductive part thereon, a dielectric layer on the substrate, an etching stop layer between the dielectric layer and the substrate, and a via plug. The via plug is electrically connected with the conductive part, including a first part in the dielectric layer and a second part in the etching stop layer, wherein the width of the second part is larger than that of the first part. [0016] According to various embodiments of the interconnect structure, the material of the etching stop layer may be SiN, and that of the via plug may be tungsten (W) or aluminum (Al). The above interconnect structure may further include a barrier layer between the via plug and each of the dielectric layer and the etching stop layer, wherein the material of the barrier layer may be Ti, TiN or tantalum nitride (TaN). [0017] This invention also provides a method for fabricating the above interconnect structure, including the following steps. A substrate with a conductive part thereon is provided, and then an etching stop layer is formed on the substrate. A dielectric layer is formed on the etching stop layer, and then a first opening is formed in the dielectric layer to expose a portion of the etching stop layer over the conductive part. A wet etching step is conducted using the dielectric layer as a mask to form a second opening in the etching stop layer, wherein the second opening exposes the conductive part and is wider than the first opening. A via plug is formed in the first and the second openings. [0018] According to various embodiments of the above method, the first opening may be formed with the following steps. A photoresist layer is formed on the dielectric layer. Lithography and etching steps are conducted to pattern the dielectric layer, and then the photoresist layer is removed. The via plug may be formed through an atomic level deposition (ALD) process. The etchant used in the wet etching step may be hot phosphoric acid. Moreover, the method may further include a step of forming a barrier layer on the internal surfaces of the first and second openings after the second opening is formed but before the via plug is formed, wherein the barrier layer may be formed through PECVD, metal organic chemical vapor deposition (MOCVD) or ionized metal plasma (IMP) deposition. [0019] Since the portion of the via plug in the etching stop layer is wider than the portion in the dielectric layer, the contact area between the via plug and the conductive part is increased lowering the contact resistance. Moreover, since the etching step of the first opening is stopped on the etching stop layer, the conductive part under the etching stop layer is not damaged. In addition, because the second opening is formed through wet etching, it is formed wider than the first opening due to the undercut effect to expose more area of the conductive part and increase the contact area between the via plug and the conductive part lowering the contact resistance. [0020] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS [0021] FIGS.1A and 1B illustrate cross-sectional views of two semiconductor devices according to two embodiments of this invention. [0022] FIGS. 2A-2D illustrate, in a cross-sectional view, a process flow of fabricating a semiconductor device according to an embodiment of this invention. [0023] FIGS. 3A and 3B illustrate cross-sectional views of two interconnect structures according to two embodiments of this invention. [0024] FIGS. 4A-4D illustrate, in a cross-sectional view, a process flow of fabricating an interconnect structure according to an embodiment of this invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS [0025] FIG. 1A illustrates a cross-sectional view of a semiconductor device according to an embodiment of this invention. The semiconductor device includes a substrate 100, a transistor 102, a hard mask layer 104 a and an anti-reflection layer 106. The substrate 100 includes a first area 101 and a second area 103 that are defined by an isolation structure 108, such as an STI layer. The second area 103 includes a photosensing area, in which a doped region 105 of different conductivity type is formed in the substrate 100 to form a PN diode. The doped region 105 may alternatively be formed in a well of different conductivity type in the substrate 100 to form a PN diode. [0026] The transistor 102 is disposed on the substrate 100 in the first area 101, and may be a MOS transistor including gate dielectric 10, a gate 12, a spacer 14 and two S/D regions 16. The hard mask layer 104 a is disposed over the substrate 100 in the second area 103, including a material different from that of the anti-reflection layer 106, such as SiO, SiC, BPSG, PSG, FSG or poly-Si, and preferably having a thickness of 100-1000 Å. The anti-reflection layer 106 is between the hard mask layer 104 a and the substrate 100, possibly including SiN or SiON and having a thickness of 400-2000 Å. A salicide layer 111 possibly including WSi, TiSi, CoSi, MoSi, NiSi, PdSi or PtSi may be further disposed on the S/D regions 16 and the gate 12 of the transistor 102. [0027] Since the anti-reflection layer 106 and the hard mask layer 104 a are sequentially stacked on the second area 103, the light perpendicularly or obliquely incident to the photosensing area is reflected less as compared with the prior art using SiO to form the SAB. Therefore, the sensitivity of the photodiode image sensor can be enhanced. [0028] FIG. 1B illustrates a cross-sectional view of a semiconductor device according to another embodiment of this invention. The semiconductor device is different from the above one in that a sacrificial layer 110 is further disposed between the anti-reflection layer 106 and the substrate 100 to improve the adhesion of the anti-reflection layer 106. The sacrificial layer 110 may include SiO, and may have a thickness of 10-300 Å. [0029] FIGS. 2A-2D illustrate a process flow of fabricating a semiconductor device as shown in FIG. 1B according to an embodiment of the invention. [0030] Referring to FIG. 2A, a substrate 100 that includes a first area 101 and a second area 103 defined by an isolation structure 108 is provided, wherein the first area 101 is disposed with a transistor 102 and the second area 103 is a photosensing area. [0031] Referring to FIG. 2B, a sacrificial layer 110 is formed on the substrate 100, possibly through thermal oxidation or PECVD, to enhance the adhesion of the anti-reflection layer 106 formed later. Then, the anti-reflection layer 106 and a hard mask material 104 are sequentially formed on the sacrificial layer 110, wherein the anti-reflection layer 106 or the hard mask material 104 may be formed through PECVD, and possible materials of the same have been described above. In another embodiment, a sacrificial layer is not formed, while the anti-reflection layer 106 is formed directly on the substrate 100. Then, a patterned photoresist layer 107 covering the second area 103 is formed on the hard mask material 104 with a lithography process. [0032] Referring to FIG. 2C, a dry or wet etching step is conducted with the patterned photoresist layer 107 as a mask to etch the hard mask material 104 and form a patterned hard mask layer 104 a. After the photoresist layer 107 is removed, a wet etching step is conducted using the hard mask layer 104 a as a mask to removed the anti-reflection layer 106 and the sacrificial layer 110 outside the second area 103, as shown in FIG. 2D. The wet etching step may be conducted by sequentially removing the exposed anti- reflection layer 106 and the exposed sacrificial layer 110 respectively with hot phosphoric acid and dilute hydrofluoric acid. A salicide process is then conducted, with the hard mask layer 104 a, the anti-reflection layer 106 and the sacrificial layer 110 together serving as an SAB, to form a salicide layer 111 on the gate 12 and the S/D regions 16 of the transistor 102. [0033] It is noted that since a wet etching step is conducted to remove the anti-reflection layer 106 and the sacrificial layer 110 outside the second area 103, the exposed anti-reflection layer 106 and sacrificial layer 110 can be removed completely. Hence, no extra spacer is formed on sidewalls of the gate 12 partially covering the S/D regions 16. [0034] It is also noted that when the hard mask material 104 is poly-Si, the hard mask layer 104 a should be removed after the anti-reflection layer 106 and the sacrificial layer 110 are patterned. When the hard mask material 104 is a dielectric material like SiO, SiC, BPSG, PSG or FSG, the hard mask layer 104 a is not necessary to remove but can serve as a part of the inter-layer dielectric (ILD). [0035] It is further noted that the principle of the above fabricating process may also be applied to the fabrication of an interconnect structure as follows. [0036] FIG. 3A illustrates a cross-sectional view of an interconnect structure according to an embodiment, which includes a substrate 300 having thereon a conductive part 308, an etching stop layer 302 on the substrate 300, a dielectric layer 304 on the etching stop layer 302, and a via plug 306. The conductive part 308 may be a conductive line or a part of a semiconductor device. The dielectric layer 340 may include SiO, BPSG, PSG or FSG, and the etching stop layer 302 may include SiN. The via plug 306 is electrically connected with the conductive part 308, including a first part 306 a in the dielectric layer 304 and a second part 306 b in the etching stop layer 302 wider than the first part 306 a. The material of the via plug 306 may be tungsten or aluminum. Since the part (306 b) of the via plug 306 contacting with the conductive part 308 is wider, the contact area is larger causing a lower contact resistance. [0037] FIG. 3B illustrates an interconnect structure of another embodiment, which is different from the above one in that a barrier layer 310 is further disposed between the via plug 306 and each of the dielectric layer 304 and the etching step layer 302 to separate them and prevent a spike effect. The material of the barrier layer 310 may be Ti, TiN or TaN. [0038] FIGS. 4A-4D illustrate a process flow of fabricating an interconnect structure as shown in FIG. 3B according to an embodiment of the invention. Referring to FIG. 4A, a substrate 300 with a conductive part 308 thereon is provided, and then an etching stop layer 302 is formed on the substrate 300 possibly through PECVD. A dielectric layer 304 is then formed on the etching stop layer 302, possibly through PECVD. [0039] Referring to FIG. 4B, a patterned photoresist layer 305 having therein an opening over the conductive part 308 is formed on the dielectric layer 304 with a lithography step. An etching step, normally a dry etching step, is conducted using the photoresist layer 305 as a mask to form in the dielectric layer 304 an opening 307 that exposes a portion of the etching stop layer 302 over the conductive part 308. Since the etching step of the opening 307 is stopped on the etching stop layer 302, the conductive part 308 is not damaged by the etching. [0040] Referring to FIG. 4C, after the photoresist layer 305 is removed, a wet etching step is conducted using the dielectric layer 304 as a mask to form in the etching stop layer 302 an opening 309 that exposes the conductive part 308, wherein the opening 309 is wider than the opening 307 due to the undercut effect. The etchant used in the wet etching step may be hot phosphoric acid. [0041] Referring to FIG. 4D, a barrier layer 310 is formed on the internal surfaces of the openings 307 and 309, so that the via plug 306 formed later can be separated from the dielectric layer 304 and the etching stop layer 302 to prevent a spike effect. The barrier layer 310 may be formed through PECVD, MOCVD or ionized metal plasma (IMP) deposition. Then, a via plug 306 is formed in the openings 307 and 309, possibly through atomic level deposition (ALD). Since the opening 309 is wider than the opening 307, the contact area between the via plug 306 and the conductive part 308 is increased lowering the contact resistance between them. [0042] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS20020027239 *Sep 7, 2001Mar 7, 2002Nec CorporationCMOS image sensor and manufacturing method thereofUS20020127856 *Feb 25, 2002Sep 12, 2002Sanyo Electric Co., Ltd.Nitride-based semiconductor element and method of forming nitride-based semiconductorUS20040102035 *Nov 10, 2003May 27, 2004Samsung Electronics Co., Ltd.Semiconductor devices and methods for fabricating the sameUS20050017316 *Jul 24, 2003Jan 27, 2005Dun-Nian YaungCMOS image sensor device and methodUS20050287479 *Jan 26, 2005Dec 29, 2005Samsung Electronics Co., Ltd.Image sensor and method for manufacturing the sameUS20060024948 *Jun 21, 2005Feb 2, 2006Samsung Electronics Co., Ltd.Method of fabricating dual damascene interconnectionUS20060289947 *Aug 3, 2005Dec 28, 2006Rohm Co., Ltd.Semiconductor device and its manufacturing methodUS20060292775 *Jun 28, 2005Dec 28, 2006Nanya Technology CorporationMethod of manufacturing DRAM capable of avoiding bit line leakageUS20070082469 *Oct 12, 2005Apr 12, 2007Peters John MForming heaters for phase change memories* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7439152Aug 27, 2004Oct 21, 2008Micron Technology, Inc.Methods of forming a plurality of capacitorsUS7579668 *Oct 19, 2007Aug 25, 2009National Taiwan UniversityMethod for photo-detecting and apparatus for the sameUS7586138 *Aug 3, 2007Sep 8, 2009United Microelectronics Corp.Image sensor and method of forming the sameUS7655968Mar 10, 2005Feb 2, 2010Micron Technology, Inc.Semiconductor devicesUS7682924Aug 13, 2007Mar 23, 2010Micron Technology, Inc.Methods of forming a plurality of capacitorsUS7759193Jul 9, 2008Jul 20, 2010Micron Technology, Inc.Methods of forming a plurality of capacitorsUS7785962Feb 26, 2007Aug 31, 2010Micron Technology, Inc.Methods of forming a plurality of capacitorsUS7825451Apr 12, 2007Nov 2, 2010Micron Technology, Inc.Array of capacitors with electrically insulative ringsUS7858486Apr 8, 2009Dec 28, 2010Micron Technology, Inc.Methods of forming a plurality of capacitorsUS7902081Oct 11, 2006Mar 8, 2011Micron Technology, Inc.Methods of etching polysilicon and methods of forming pluralities of capacitorsUS7915136Jul 30, 2009Mar 29, 2011Round Rock Research, LlcMethods of forming integrated circuit devicesUS7919386Apr 27, 2009Apr 5, 2011Micron Technology, Inc.Methods of forming pluralities of capacitorsUS8129240Aug 16, 2010Mar 6, 2012Micron Technology, Inc.Methods of forming a plurality of capacitorsUS8163613Jun 25, 2010Apr 24, 2012Micron Technology, Inc.Methods of forming a plurality of capacitorsUS8164132Mar 28, 2011Apr 24, 2012Round Rock Research, LlcMethods of forming integrated circuit devicesUS8207563Dec 13, 2006Jun 26, 2012Round Rock Research, LlcIntegrated circuitryUS8263457Oct 10, 2011Sep 11, 2012Micron Technology, Inc.Methods of forming a plurality of capacitorsUS8274777Apr 8, 2008Sep 25, 2012Micron Technology, Inc.High aspect ratio openingsUS8388851Jan 8, 2008Mar 5, 2013Micron Technology, Inc.Capacitor forming methodsUS8450164Feb 22, 2010May 28, 2013Micron Technology, Inc.Methods of forming a plurality of capacitorsUS8518788Aug 11, 2010Aug 27, 2013Micron Technology, Inc.Methods of forming a plurality of capacitorsUS8652926Jul 26, 2012Feb 18, 2014Micron Technology, Inc.Methods of forming capacitorsUS8734656Jan 29, 2013May 27, 2014Micron Technology, Inc.Capacitor forming methodsUS8760841Sep 14, 2012Jun 24, 2014Micron Technology, Inc.High aspect ratio openingsUS8786001Jan 19, 2010Jul 22, 2014Round Rock Research, LlcSemiconductor devicesUS8946043Dec 21, 2011Feb 3, 2015Micron Technology, Inc.Methods of forming capacitorsUS9076680Oct 18, 2011Jul 7, 2015Micron Technology, Inc.Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the arrayUS9076757Aug 12, 2013Jul 7, 2015Micron Technology, Inc.Methods of forming a plurality of capacitorsUS9196673Jan 6, 2014Nov 24, 2015Micron Technology, Inc.Methods of forming capacitorsUS9224798Apr 17, 2014Dec 29, 2015Micron Technology, Inc.Capacitor forming methodsUS20060014344 *Jul 19, 2004Jan 19, 2006Manning H MMethods of forming semiconductor structures and capacitor devicesUS20060063345 *Nov 10, 2005Mar 23, 2006Manning H MMethods of forming plurality of capacitor devicesUS20060148190 *Feb 24, 2006Jul 6, 2006Busch Brett WMethods of forming a plurality of capacitorsUS20060211211 *Mar 18, 2005Sep 21, 2006Sandhu Gurtej SMethods of forming pluralities of capacitorsUS20060246678 *Jun 28, 2006Nov 2, 2006Manning H MMethods of forming a plurality of capacitorsUS20060249798 *Jul 11, 2006Nov 9, 2006Manning H MMethods of forming capacitorsUS20060261440 *May 18, 2005Nov 23, 2006Micron Technology, Inc.Methods of forming a plurality of capacitors, and integrated circuitry comprising a pair of capacitorsUS20070093022 *Dec 13, 2006Apr 26, 2007Cem BasceriIntegrated circuitryUS20070105303 *Dec 26, 2006May 10, 2007Busch Brett WMethods of forming a plurality of circuit components and methods of forming a plurality of structures suspended elevationally above a substrateUS20070134872 *Feb 9, 2007Jun 14, 2007Sandhu Gurtej SMethods of forming pluralities of capacitorsUS20070161202 *Mar 14, 2007Jul 12, 2007Manning H MMethods of forming a plurality of capacitorsUS20070173030 *Mar 14, 2007Jul 26, 2007Micron Technology, Inc.Methods of forming a plurality of capacitorsUS20070196978 *Apr 12, 2007Aug 23, 2007Manning H MIntegrated circuitry comprising a pair of adjacent capacitorsUS20070210348 *Dec 22, 2006Sep 13, 2007Song JongheuiPhase-change memory device and methods of fabricating the sameUS20070238259 *Apr 10, 2006Oct 11, 2007Micron Technology, Inc.Methods of forming a plurality of capacitorsUS20080035968 *Aug 3, 2007Feb 14, 2008Jhy-Jyi SzeImage sensor and method of forming the sameUS20080090416 *Oct 11, 2006Apr 17, 2008Micro Technology, Inc.Methods of etching polysilicon and methods of forming pluralities of capacitorsUS20080206950 *Feb 26, 2007Aug 28, 2008Micron Technology, Inc.Methods of forming a plurality of capacitorsUS20090008736 *Oct 19, 2007Jan 8, 2009National Taiwan UniversityMethod for photo-detecting and apparatus for the sameUS20090176011 *Jan 8, 2008Jul 9, 2009Mark KiehlbauchCapacitor Forming MethodsUS20090209080 *Apr 27, 2009Aug 20, 2009Sandhu Gurtej SMethods of Forming Pluralities of CapacitorsUS20100009512 *Jul 9, 2008Jan 14, 2010Fred FishburnMethods of forming a plurality of capacitorsUS20100117196 *Jan 19, 2010May 13, 2010Manning Homer MSupport For Vertically-Oriented Capacitors During The Formation of a Semiconductor DeviceUS20100151653 *Feb 22, 2010Jun 17, 2010Micron Technology, Inc.Methods Of Forming A Plurality Of CapacitorsUS20100261331 *Apr 8, 2009Oct 14, 2010Manning H MontgomeryMethods Of Forming A Plurality Of CapacitorsUS20100266962 *Jun 25, 2010Oct 21, 2010Micron Technology, Inc.Methods Of Forming A Plurality Of CapacitorsUS20100311219 *Aug 16, 2010Dec 9, 2010Micron Technology, Inc.Methods of Forming a Plurality of Capacitors* Cited by examinerClassifications U.S. Classification438/57, 257/E21.578International ClassificationH01L21/00Cooperative ClassificationH01L27/14689, H01L21/76804European ClassificationH01L21/768B2B, H01L27/146V6Legal EventsDateCodeEventDescriptionOct 31, 2005ASAssignmentOwner name: UNITED MICROELECTRONICS CORP., TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHIANG, YUAN-SHENG;CHEN, HSUAN-HSU;REEL/FRAME:016709/0109Effective date: 20051024RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services