Source: https://patents.google.com/patent/US4783734
Timestamp: 2018-02-25 18:00:16
Document Index: 56757413

Matched Legal Cases: ['application No. 83307078', 'application No. 221455', 'art4', 'application No. 0110642', 'application No. 0110642', 'art25', 'art1']

US4783734A - Computer system with variable length process to process communication - Google Patents
Computer system with variable length process to process communication
US4783734A
US4783734A US06756431 US75643185A US4783734A US 4783734 A US4783734 A US 4783734A US 06756431 US06756431 US 06756431 US 75643185 A US75643185 A US 75643185A US 4783734 A US4783734 A US 4783734A
US06756431
A microcomputer method and system for executing a plurality of concurrent processes provides synchronized message transmission so that data is transmitted between a communicating pair of processes when the two processes are at corresponding program stages. The messages may be variable in length and are transmitted by indicating a source address for the data to be transmitted, a destination address for the data, and a count of the number of standard unit lengths of data to be transmitted in the message.
The invention relates to microcomputers and particularly to microcomputers arranged to permit data transmission between processes.
The present invention is a development of the microcomputer described in our European patent specification No. 0113516. That specification describes the microcomputer with a memory and processor arranged to execute a plurality of concurrent processes and to provide synchronised communication between concurrent processes on the same microcomputer or interconnected microcomputers. However, the device described in that specification was arranged to transmit messages which were each of one word length. After execution of each message instruction one word is transmitted and subsequent message instructions are required in order to cause further words to be transmitted. In the case of a 16 bit machine each message would be of 16 data bits.
It is an object of the present invention to provide an improved microcomputer which permits variable length message transmission.
It is a further object of the present invention to provide an improved microcomputer which may transmit messages in multiples of standard bit length units.
It is a further object of the present invention to provide a microcomputer which may communicate in a network with other devices of different wordlength.
The invention provides a microcomputer comprising memory and a processor arranged to execute a plurality of concurrent processes, each in accordance with a program consisting of a plurality of instructions for sequential execution by the processor, each instruction designating a required function to be executed by the processor, said processor comprising (1) a plurality of registers and data transfer means for use in data transfers to and from said registers (2) means for receiving each instruction and loading into one of the processor registers a value associated with the instruction, and (3) control means for controlling said data transfer means and registers in response to each instruction received to cause the processor to operate in accordance with the instruction, wherein the microcomputer includes:
(i) means for identifying one or more processes to form at least one collection awaiting execution by the processor
(iii) means for scheduling a process by adding it to a collection awaiting execution, and
(b) communication means to permit message transmission from one process to another by use of one or more communication channels when both processes are at corresponding stages in their program sequences, an outputting process operating to output data and an inputting process operating to input data in response to message instructions, said communication means including:
(i) means for transferring from one addressable location to another a message unit of predetermined but length
(ii) means responsive to execution of a message instruction to provide a count of the number of mesaage units to be included in a message.
(iii) source indicator means responsive to execution of a message instruction by an outputting process to indicate the address from which data is to be output, and
(iv) destination indicator means responsive to execution of a message instruction by an inputting process to indicate the address to which the data is to be input.
Preferably said predetermined bit length of each message unit is one byte. Preferably the microcomputer includes means for counting the number of bytes transmitted in a message to or from a process and providing a signal when all bytes in the message have been transmitted.
Preferably, means are provided to alter the address indicated by the source indicator means as the count of the number of bytes remaining to be transmitted decreases.
Preferably, means is provided to change the address indicated by the destination indicator means as the count of the number of bytes remaining to be transmitted changes.
Preferably, the communication means is arranged to permit data transmission between processes which are executed on the same microcomputer and said channel comprising a memory location.
Preferably, the processor has means for copying directly a number of bytes of data indicated as a result of execution of a message instruction, directly from one byte address to another in the memory of the microcomputer.
Preferably, the communication means is arranged to permit external data transmission between processes which are executed on different microcomputers and the or each channel comprises an external communication link.
Preferably, each external communication link comprises store means for holding one byte of data.
Preferably, each external communication link is arranged to deschedule a process which executes a message instruction using the address of that link and each link includes means for storing an indication of the number of bytes to be transmitted through the link together with a pointer to the source or destination address for the next byte of the message.
Preferably, each external communication link includes means for counting the number of bytes transmitted and providing an indication when all bytes have been transmitted.
Preferably, each external communication link includes signal generating means to generate a request signal to the processor to reschedule the process involved in the message transmission when all bytes of the message have been transmitted.
FIG. 2 shows further detail in block diagram form of part of the microcomputer and particularly illustrates the registers, data paths and arithmetic logic unit of the central processing unit as well as the interface between the central processing unit and the memory and communication links,
FIG. 19 illustrates in a sequence from 19(a) to 19(g) operations for effecting communication between two processes on the same microcomputer in which an inputting processes commences an "alternative input" operation before the outputting process commences at output operation and both processes have the same priority,
The microcomputer described in this example comprises an integrated circuit device in the form of a single silicon chip having both a processor and memory in the form of RAM as well as links to permit external communication. The main elements of the microcomputer are illustrated in FIG. 1 on a single silicon chip 11 using p-well complementary MOS technology. A central processing unit (CPU) 12 is provided with some read-only memory (ROM) 13 and is coupled to a memory interface 14 controlled by interface control logic 15. The CPU 12 incorporates an arithmetic logic unit (ALU), registers and data paths illustrated more fully in FIG. 2. The CPU 12 and memory interface 14 are connected to a bus 16 which provides interconnection between the elements on the chip 11. A service system 17 is provided with a plurality of input pins 18. The microcomputer is provided with a random access memory (RAM) 19 and ROM 20 and the amount of memory on the chip is not less than 1K byte so that the processor 12 can be operated without external memory. Preferably the memory on the chip is at least 4K bytes. An external memory interface 23 is provided and connected to a plurality of pins 24 for connection to an optional external memory. To allow the microcomputer to be linked to other computers to form a network, a plurality of serial links 25 are provided having input and output pins 26 and 27 respectively. The input and output pins of one serial link may each be connected by its own single wire non-shared unidirectional connection to the corresponding output and input pins of a serial link on another microcomputer as shown in FIG. 22. Each serial link is connected to a synchronisation logic unit 10 comprising process scheduling logic.
The block diagram shown in FIG. 1 corresponds to that included in European patent application No. 83307078.2, Japanese patent application No. 221455/1983 and U.S. patent application Ser. Nos. 552601, 552602, 553027, 553028 and 553029. To avoid unnecessary repetition of description, the full details of the construction and operation of that microcomputer will not be set out below but the description in the above mentioned patent applications is hereby incorporated herein by reference.
MostNeg: the most negative value (the most significant bit is one, and all other bits are zero)
MostPos: the most positive value (the most significant bit is zero, and all other bits are one)
MachineTRUE: 1
MachineFALSE: 0
NotProcess.p: MostNeg
Enabling.p: MostNeg+1
Waiting.p: MostNeg+2
Ready.p: MostNeg+3
As in the example of the above mentioned patent applications, each process may have a workspace consisting of a vector of words in memory used to hold the local variables and temporary values manipulated by the process. A workspace pointer WPTR is used to point to a set location for the process workspace. As the workspace of each process consists of a number of words, it is not necessary to incorporate the byte selector. It is therefore possible to use the byte selector bits to represent the priority of the process. In this way each process can be identified by a "process descriptor" of the type shown in FIG. 6. The least significant bit indicates the priority of the process and the most significant 15 bits indicate the word in memory identifying the process workspace. In the present example the microcomputer allocates one of two possible priorities to each process. A high priority process is given the designation Pri=0 and a low priority process has a designation Pri=1. It can therefore be seen that each process descriptor comprises a single word which is formed by taking the "bitwise OR" of the workspace pointer WPTR and the process priority Pri. Similarly the workspace point WPTR can be obtained from a process descriptor by forming the "bitwise AND" of the process descriptor and NOT 1. The priority of the process can be obtained by forming the "bitwise AND" of the process descriptor and 1.
______________________________________Abbreviation       Register______________________________________       Common to both priority processesMADDR       Memory address register 42 containing the       address of the memory location required.DATAOUT     A register 43 for supplying data to the       memory on the data bus 31.IB          Instruction buffer 34 for receiving sequen-       tially instructions from the memory.TEMP REG    A temporary register 44.PROCPTR REG A register 45 for holding a process pointer       (no priority indication).PROCDESC REG       A register 46 for containing a process       descriptorPRIFLAG     A 1 bit register or flag 47 for indicating the       priority 0 or 1 of the currently executing       process. If the processor is not executing a       process this is set to 1.PROCPRIFLAG A 1 bit register or flag 48 for indicating a       process priority.       Registers in Bank 38 for Priority 1TREG        A temporary register 49.IPTR REG    A register 50 which holds the instruction       pointer (IPTR) of any process indicated by       register 51WPTR REG    A register 51 for holding the workspace       pointer (WPTR) of the current process or       an interrupted process.BPTR REG    A register 52 holding the workspace pointer       of a process at the end of a list of priority 1       processes awaiting execution.FPTR REG    A register 53 holding the workspace pointer       of a process at the front of a list of priority       1 processes awaiting execution.AREG        A first register 54 for holding an operand       for the ALU 30 and arranged as a stack       with registers 55 and 56.BREG        A second register 55 forming part of the       stack.CREG        A register 56 forming a third register in the       stack.OREG        An operand register 57 for receiving the       data derived from an instruction in the       instruction buffer 34, and used as a tem-       porary register.SNPFLAG     A 1 bit register or flag 58 which when set to       1 indicates that the current process should       be descheduled on completion of the current       instruction.COPYFLAG    A 1 bit register or flag 59 which when set to       1 indicates that the process is copying a       block of data to or from memory.______________________________________
The registers are generally of word length which is in this case is 16 bits apart from the 1 bit flags 47, 48, 58 and 59. The instruction buffer may be 8 bit length if arranged to hold only 1 instruction at a time. The A, B and C register stack 54, 55 and 56 are the sources and destinations for most arithmetic and logical operations. They are organised as a stack so that the loading of a value into the A register is preceded by relocating the existing contents of the B register into the C register and from the A register into the B register. Similarly storing a value derived from the A register causes the contents of the B register to be moved into the A register and the contents of the C register into the B register.
As the workspace point (WPTR) of a process is used as a base from which local variables of the process can be addressed, it is sometimes necessary to calculate offset values from the location indicated by the workspace pointer. The constants box 40 is connected to the Y bus and enables constant values to be placed on that bus under the control of the microinstruction ROM 13. These can be used in pointing to offset locations in a process workspace. In order to effect selection of one or other of the register banks 38 or 39, the register bank selector 41 has inputs from the PRI FLAG 47, the PROCPRI FLAG 48 and the microinstruction ROM 13. The output from the register bank selector is connected to the condition multiplexor 36, to the decoder 35 and to the switches 32. Depending on the output of the microinstruction ROM 13, the selector will chose the register bank indicated by the PRI FLAG 47 or the PROCPRI FLAG 48.
As described in the above mentioned patent application, data is transmitted from one microcomputer to another in the form of data packets having a predetermined protocol. The receipt of data is indicated by the transmission of an acknowledge packet. In this particular example, data is transmitted in the form of packet illustrated in FIG. 8. Each packet consists of a standard unit of data which in this case consists of 1 byte (8 bits). The data packet commences with 2 start bits each of 1 followed by the byte of data and terminating with a stop bit of 0. After transmission of each packet as shown in FIG. 8, the input channel of a serial link which receives the packet is arranged to signal to its associated output channel to transmit an acknowledge packet of the type shown in FIG. 9. This is merely a 2 bit packet starting with a 1 and terminating with a 0. The instructions executed by a process to send or receive data may require that more than one such packet of data is involved in the message transmission and consequently the instruction may indicate how many standard units or bytes of data are to be transmitted in order to complete the message required by the instruction. The structure of the links is shown more fully in FIGS. 10 to 14. In the examples shown in FIGS. 10 or serial links 70, 71, 72 and 73 are shown each having an input pin 26 and an output pin 27. Each link is connected by parallel buses 75 and 76 to the memory interface 14. The links are also connected to the interface control logic 15 by lines 77 and 78 which provide read request and write request signals respectively to the interface control logic. The control logic 15 is arranged to provide a "DATA VALID" signal to the links on a line 79. Each of the links is arranged to provide a status output signal on line 80 to the condition multiplexor 36 of FIG. 2. The Z bus is also connected to each of the links 70 to 73 and the Z bus is connected via line 81 to the sync logic 10. A line 82 provides an output from the microinstruction ROM 13 to the sync logic 10 and lines 83 provide an output from the sync logic 10 to the condition multiplexor 36. Lines 84 connect each of the links to the syn logic 10 for carrying request signals from the links when the links indicate a request for action by the processor. A line 85 connects the microinstruction ROM 13 to each of the links in order to provide request signals to the links from the processor.
The output 116 is connected to the run request signal line which has been marked 84b and also to an AND gate 118 receiving a further input on line 119 from the priority register 110. In this way, the priority of the outputting process can be indicated on line 84a when a run request is made on line 84b. The signals on bus 75 and line 79 from the memory interface pass directly through the channel to the link interface 92 on lines 95 and 96. Bus 75 andd line 95 transmit the value of the byte to be transmitted whereas lines 79 and 96 carry the output data valid signal which is generated by the memory interface to indicate that the data now sent properly represents a full byte of data.
______________________________________State     Inputs      Outputs    Next State______________________________________any       Reset                  IdleIdle      Δ Outputreq       IdleIdle      Outputreq               SendByte0SendByte0             ReadReq    SendByte1Sendbyte1             IncPointer WaitOutputAckWaitOutputAck     Δ OutputAck      WaitOutputAckWaitOutputAck     OutputAck   DecCount   CheckFinishedCheckFinished     Δ CountZero      SendByte0CheckFinished     CountZero   RunRequest Idle______________________________________
The transfer state machine 125 has a reset input from line 101, a count zero state on line 128 from the byte counter 121, an input request from line 85b and a READY signal on line 129 from the READY state machine 127. The transfer state machine 125 has an output DECCOUNT on line 130 in order to decrease the byte counter 121. Similarly it has an output INCPOINTER on line 131 in order to increment the pointer register 122. It also provides an output write request on line 78, input ACK on line 99 and RUNREQ on line 84e.
______________________________________State     Inputs      Outputs    Next State______________________________________any       Reset                  IdleIdle      Δ Inputreq       IdleIdle      Inputreq               AwaitByteAwaitByte Δ Ready          AwaitByteAwaitByte Ready       WriteRequest                            CheckFinished                 IncPointer                 DecCountCheckFinished     Δ CountZero      AwaitByteCheckFinished     CountZero   RunReq     Idle______________________________________
The READY state machine 127 can be in the form of a simple flip-flop and is used to indicate whether a byte of data has been received in an input register in the link interface and not yet acknowledged. The READY state machine 127 has a reset input 101 and in addition it has an input state input data valid on line 98 derived from the link interface when a valid byte of data has been received in an input register of the interface. In addition, the state machine 127 has an input 132 derived from the input ACK signal line 99 so that the state machine is set in one condition when a byte of data has been received by the link interface and is then reset once the input ACK signal has been sent on line 99. The state machine 127 provides a single output READY on line 129 which forms an input to the transfer state machine 125 as well as one input to an AND gate 133 as well as a READY input 134 to the alternative state machine 126. The succession of states of the READY state machine 127 is as follows:
______________________________________TransitionsState    Inputs        Outputs   Next State______________________________________any      Reset                   DataAbsentDataAbsent    Δ InputDataValid  DataAbsentDataAbsent    InputDataValid                  Ready     DataPresentDataPresent    ΔInputAck                  Ready     DataPresentDataPresent    InputAck                DataAbsent______________________________________
__________________________________________________________________________TransitionsStateInputs              Outputs                           Next State__________________________________________________________________________any  Reset                      DisabledDisabledStatusEnquiry              Disabled Disabled ##STR1##            ReadyReq                            Disabled Disabled ##STR2##                   Enabled Disabled ##STR3##                   DisabledEnableStatusEnquiry       Reply  Disabled Enabled ##STR4##            ReadyReq                            Disabled Enabled ##STR5##                   Enabled__________________________________________________________________________
______________________________________OUTPUT STATE MACHINE 140State   Inputs           Outputs   Next State______________________________________1. any  Reset                      idle 2. idle    ##STR6##                   idle3. idle Ackgo            Oneout    ackflag 4. idle    ##STR7##         Oneout    dataflag5. ackflag               Ackgone   idle6. dataflag              Oneout    databits                    Loadcount7. databits   ΔCountzero DecCount  databits                    Shiftout                    Dataout8. databits   Countzero        Datagone  idle______________________________________
______________________________________INPUT STATE MACHINE 142State     Inputs      Outputs     Next State______________________________________1. any    Reset                   idle2. idle   ΔDatain           idle3. idle   Datain                  start4. start  ΔDatain                 SetAckready idle5. start  Datain      LoadCount   databits6. databits     ΔCountzero                 Shiftin     databits                 DecCount7. databits     Countzero   Shiftin     dataend8. dataend            SetDatready idle______________________________________
The operation of this link interface is as follows. Consider first the situation where an output link wishes to output data. The output channel of FIG. 12 causes data to be supplied to the output register along bus 95 and an output data valid signal sets the Ready indicator 147. The output of the indicator 147 is fed to the AND gate 150 and the state of the latch 148 is such that a Datago signal is input at 161. The output on pin 27 is derived through the OR gate 153 and therefore consists either of the signal on the output 166 from the output state machine or the output of the AND gate 151 dependent on the signal supplied on output 167 from the output state machine. As can be seen from the table of transitions from the output state machine 140, when the machine is idle after being reset there is no indicated output for line 166 and consequently this transmits a signal level to the output pin 27 indicating a zero. When the DataGo signal is applied at input 161 this corresponds to line number 4 of the state table where there is an input DataGo and no AckGo signal. As indicated this causes the signal Oneout on output 166. This feeds a signal 1 to the output pin 27 and forms the first bit of the data packet shown in FIG. 8. The output state machine then moves to the state called "DataFlag" as can be seen from line 6 of the state table. In this condition with no further inputs the state machine causes a further Oneout signal on output 166 and a loadcount signal on output 164. This causes the second signal value 1 to be output by pin 27 thereby forming the two start bits of the data packet in FIG. 8. The bit counter 141 is also loaded with the number of bits to be output which in this case would be 8. The output state machine is then in the state called "databits" and as can be seen from lines 7 and 8 of the state table, this provides a dataout signal to the AND gate 151 so as to allow the data contents of the register 144 to be output to the output pin 27. A shiftout signal on output 168 causes sequential discharge of the data from the register 144 with a consequential decrement in the count in the bit counter 141. When the counter reaches zero as shown in line 8 of the state table a Datagone signal is output at 169 which changes the latch 148 and removes the Datago signal from the input 161. As can be seen from line 8 of the state table, no outputs on lines 166 and 167 are shown which means that the signal value 0 is resumed on line 166 which is fed through the OR gate 153 and the output pin 27 thereby forming the stop bit 0 at the end of the data packet shown in FIG. 8. The output state machine returns to the idle condition.
The output channel may also be used to send an acknowledge packet. When the input channel has received a byte of data it sends a signal to the output state machine in order to output an acknowledge packet of the type shown in FIG. 9. A signal is fed to the AND gate 152 from the Ready Indicator 146 and the state of the latch 149 at this time permits the ACKGO signal to be applied to input 163 of the output state machine 140. This corresponds to line 3 of the state table for the output state machine 140 and as can be seen, this causes the output oneout on the output 166. This is passed through the OR gate 153 so that the signal level on pin 27 is changed from the previous zero level to indicate a 1 forming the first bit of the acknowledge packet shown in FIG. 9. This changes the output state machine 140 to the state called ACKFLAG and as can be seen from line 5 of the state table for that machine, this causes no further outputs on lines 166 and 167 and this means that the signal level on output 166 changes back to the zero level so that the signal level on the output 27 reverts to zero giving the second bit of the acknowledge packet shown in FIG. 9. The output state machine 140 also discloses an output ACKGONE on line 170 so as to change the state of the latch 149 and thereby alter the output of the AND gate 152 so that the ACKGO signal is removed from the input 163. The state machine then returns to the idle state.
If however the second bit of the packet arriving at the input pin 26 was a 1 rather than a 0 such that the packet is a data packet of thee type shown in FIG. 8, the line 5 of the state table would apply in that the machine is in the start state due to the first bit of the data packet and the input is now DataIn on input 172. This causes the output loadcount on output 174 so that the bit counter 143 is loaded with the number of bits to be expected in the data packet. In this case the number of bits will be 8 corresponding to 1 byte of data. The machine moves to the new state databits and as can be seen from line 6 of the state table, so long as the input 173 does not reach zero the state machine continues to cause a succession of operations of moving the incoming bits successively along the input register 145 due to the shiftin signal on the output line 176 and it causes progressive decrease in the counter 143 due to the DECCOUNT signal on the output 175. When the count in the counter 143 reaches zero indicating that the required 8 bits of data have now been received, line 7 of the input state machine table applies in that the machine is still in the state databits and a count zero signal is received on line 173. This causes a shiftin output on line 176 to move the last databit into the input register 145 and the machine changes to the dataend state. Line 8 of the state table indicates that in this condition a SetDataready signal is output on line 177 to alter the latch 149 and the Ready Indicator 146. The input state machine 142 then returns to the idle state. The SetDataready signal which was supplied to the Ready Indicator 146 causes the signal "input data valid" on line 98 to indicate that a full byte of data has now been received by the input register 145.
In the following description of the way in which the microcomputer operates, particularly with reference to its functions, operations and procedures, notation is used in accordance with the OCCAM (Trade Mark of INMOS International plc) language. This language is set forth in the booklet entitled "Programming Manual-OCCAM" published and distributed by INMOS Limited in 1983 in the United Kingdom. Furthermore the notation used has been set out fully in European patent application No. 0110642 and for simplicity will not be repeated in this specification. However the explanation of OCCAM and the notation used which is set out in European patent application No. 0110642 is incorporated herein by reference.
AtWord(Base, N, A): sets A to point at the Nth word past Base
AtByte(Base, N, A): sets A to point at the Nth byte past Base
RIndexWord(Base, N, X): sets X to the value of the Nth word past Base
RIndexByte(Base, N, X): sets X to the value of the Nth byte past Base
WIndexWord(Base, N, X): sets the value of the Nth word past Base to X
WIndexByte(Base, N, X): sets the value of the Nth byte past Base to X
WordOffset(Base, X, N): set N to the number of words between X and Base
In the following description thirteen different procedures (PROC) are referred to. The following six procedurees are used in the description of the behaviour of the processor.
______________________________________ 1. PROC Run = 2.  SEQ  3.##STR8##  4.##STR9## 5.   IF 6.    (Pri = 0) OR ((ProcPriFlag = Pri) AND  (WptrReg[Pri] <> NotProcess.p)) 7.     SEQ -- add process to queue 8.      IF 9.       FptrReg[ProcPriFlag] = NotProcess.p10.        FptrReg[ProcPriFlag] := ProcPtrReg11.       TRUE12.        WIndexWord(BptrReg[ProcPriFlag],      Link.s, ProcPtrReg)13.      BptrReg[ProcPriFlag] := ProcPtrReg14.    TRUE15.     SEQ -- either Pri 0 interrupting Pri 1, or Pri 1   and idle m/c16.      Pri := ProcPriReg17.      WptrReg[Pri] := ProcPtrReg18.      RIndexWord(WptrReg[Pri], Iptr.s, IptrReg[Pri])19.      Oreg[Pri] := 0 :______________________________________
______________________________________ 1. PROC StartNextProcess = 2.  SEQ- Clear the SNP flag= 0 4.   IF 5.    FptrReg[Pri] <> NotProcess.p 6.     Dequeue 7.    Pri = 0 8.     SEQ 9.      Pri := 110.      IF11.       (WptrReg[Pri] = NotProcess.p) AND12.       (FptrReg[Pri] <> NotProcess.p)13.        Dequeue14.       TRUE15.        SKIP16.    Pri = 117.     WptrReg[Pri] := NotProcess.p :______________________________________
______________________________________ 1. PROC HandleReadyRequest(VAR PortNo) = 2.  SEQ 3.   RIndexWord(PortBase, PortNo, ProcDescReg)  4.##STR10## 5.   RIndexWord(ProcPtrReg, State.s, TempReg) 6.   IF 7.    TempReg = Enabling.p 8.     WIndexWord(ProcPtrReg, State.s, Ready.p) 9.    TempReg = Ready.p10.     SKIP11.    TempReg = Waiting.p12.     SEQ13.      WIndexWord(ProcPtrReg, State.s, Ready.p)14.      Run :______________________________________
______________________________________ 1. PROC BlockCopyStep = 2.  SEQ 3.   RIndexByte(Creg[Pri], 0, Oreg[Pri]) 4.   WIndexByte(Breg[Pri], 0, Oreg[Pri]) 5.   Oreg[Pri] := 0 6.   AtByte(Creg[Pri], 1, Creg[Pri]) 7.   AtByte(Breg[Pri], 1, Breg[Pri])18.   Areg[Pri] := Areg[Pri] 9.   IF10.    Areg[Pri] = 0 -- has the block copy been completed12.     SEQ13.      CopyFlag[Pri] := 014.      IF15.       Treg[Pri] <> NotProcess.p16.        SEQ17.         ProcDescReg := Treg[Pri]18.         Run19.       Treg[Pri] = NotProcess.p20.        SKIP21.    TRUE22.     SKIP :______________________________________
The four procedures "CauseLinkInput", "CauseLinkOutput", MakeLinkReadyStatusEnquiry" and "EnableLink" describe interaction between the process and a link.
______________________________________1.   PROC LinkChannelInputAction =2.    VAR PortNo :3.    SEQ4.     WIndexWord(WptrReg[Pri], Iptr.s, IptrReg[Pri]) 5. ##STR11##6.     WordOffset(PortBase, Breg[Pri], PortNo)7.     CauseLinkInput (PortNo)8.     SNPFlag[Pri] := 1 :1.   PROC LinkChannelOutputAction =2.    VAR PortNo :3.    SEQ4.     WIndexWord(WptrReg[Pri], Iptr.s, IptrReg[Pri]) 5. ##STR12##6.     WordOffset(PortBase, Breg[Pri], PortNo)7.     CauseLinkOutput(PortNo)8.     SNPFlag[Pri] := 1 :1.   PROC IsThisSelectedProcess =2.    -- this is used by all the disable instructions3.    SEQ4.     RIndexWord(WptrReg[Pri], 0, Oreg[Pri])5.     IF6.      Oreg[Pri] = (-1)7.       SEQ8.        WIndexWord(WptrReg[Pri], 0, Areg[Pri])9.        Areg[Pri] := MachineTRUE10.     Oreg[Pri] <> (-1)11.      Areg[Pri] := MachineFALSE :______________________________________
______________________________________Code No    Abbreviation Name______________________________________0          ldl          load local1          stl          store local2          ldlp         load local pointer3          ldnl         load non-local4          stnl         store non-local5          ldnlp        load non-local pointer6          eqc          equals constant7          ldc          load constant8          adc          add constant9          j            jump10         cj           conditional jump11         call         call12         ajw          adjust workspace13         opr          operate14         pfix         prefix15         nfix         negative prefix______________________________________
______________________________________Code No   Abbreviation Name______________________________________ 0        rev          reverse 1        ret          return 2        gcall        general call 3        gajw         general adjust workspace 4        ldpi         load pointer to instruction 5        bsub         byte subscript 6        wsub         work subscript 7        bcnt         byte count 8        wcnt         word count 9        lend         loop end10        lb           load byte11        sb           store byte12        copy         copy message13        gt           greater than14        add          add15        sub          subtract16        mint         minimum integer17        startp       start process18        endp         end process19        runp         run process20        stopp        stop process21        ldpri        load priority22        in           input message23        out          output message24        alt          alt start25        altwt        alt wait26        altend       alt end27        enbs         enable skip28        diss         disable skip29        enbc         enable channel30        disc         disable channel______________________________________
______________________________________load localdef:    SEQ    Creg[Pri] := Breg[Pri]    Breg[Pri] := Areg[Pri]    RIndexWord(WptrReg[Pri], Oreg[Pri], Areg[Pri])purpose:   to load the value of a location in the current   process workspacestore localdef:    SEQ    WIndexWord(WptrReg[Pri], Oreg[Pri], Areg[Pri])    Areg[Pri] := Breg[Pri]    Breg[Pri] := Creg[Pri]purpose:   to store a value in a location in the current   process workspaceload localpointerdef:    SEQ    Creg[Pri] := Breg[Pri]    Breg[Pri] := Areg[Pri]    AtWord(WptrReg[Pri], Oreg[Pri], Areg[Pri])purpose:   to load a pointer to a location in the current   process workspace   to load a pointer to the first location of a   vector of locations in the current process   workspaceloadnon-localdef:    RIndexWord(Areg[Pri], Oreg[Pri], Areg[Pri])purpose:   to load a value from an outer workspace   to load a value from a vector of values   to load a value, using a value as a pointer   (indirection) - in this case Oreg = 0storenon-localdef:    SEQ    WIndexWord(Areg[Pri], Oreg[Pri], Breg[Pri])    Areg[Pri] := Creg[Pri]purpose:   to store a value in a location in an   outer workspace   to store a value in as vector of values   to store a value, using a value as a   pointer (indirection) - in this case   Oreg = 0loadnon-localpointerdef:    AtWord(Areg[Pri], Oreg[Pri], Areg[Pri])purpose:   to compute pointers to words in word   vectors and workspacesequalsconstantdef:    IF    Areg[Pri] = Oreg[Pri]     Areg[Pri] := MachineTRUE    TRUE     Areg[Pri] := MachineFALSEpurpose:   to test that the Areg holds a constant value   to implement logical   negation   to implement a = c        as eqc c a <> c       as eqc c, eqc 0loadconstantdef:    SEQ    Creg[Pri] := Breg[Pri]    Breg[Pri] := Areg[Pri]    Areg[Pri] := Oreg[Pri]purpose:   to load a valueaddconstantdef:    Areg[Pri] := Areg[Pri] + Oreg[Pri]purpose:   to add a valuejumpdef:    AtByte(IptrReg[Pri], Oreg[Pri], IptrReg[Pri])purpose:   to transfer control forwards or backwards,   providing loops, exits from loops,   continuation after conditional sections of   programconditionaljumpdef:    IF    Areg[Pri] = 0     AtByte(IptrReg[Pri], Oreg[Pri], IptrReg[Pri]    Areg[Pri] <> 0     SEQ      Areg[Pri] := Breg[Pri]      Breg[Pri] := Creg[Pri]purpose:   to transfer control forwards or backwards   only if a zero value is loaded, providing   conditional execution of sections or program   and conditional loop exits   to facilitate comparison of a value against   a set of valuescalldef:    SEQ    WIndexWord(WptrReg[Pri] , -1, Creg[Pri])    WIndexWord(WptrReg[Pri], -2, Breg[Pri])    WIndexWord(WptrReg[Pri], -3, Areg[Pri])    WIndexWord(WptrReg[Pri], -4, IptrReg[Pri])    Areg[Pri] := IptrReg[Pri]    AtWord(WptrReg[Pri], -4, WptrReg[Pri]    AtByte(IptrReg[Pri], Oreg[Pri], IptrReg[Pri])purpose:    to call a procedureadjustworkspacedef:     AtWord(Wptr[Pri], Oreg[Pri], Wptr[Pri])purpose:    to adjust the workspace pointer______________________________________
______________________________________Indirect FunctionsoperateDefinition: operate (OREG[PRI]Purpose:    perform an operation, using the       contents of the operand register       OREG[PRI] as the code defining the       operation required.Prefixing FunctionsprefixDefinition: OREG[PRI] := OREG[PRI] << 4Purpose:    to allow instruction operands which       are not in the range 0-15 to be       represented using one or more       prefix instructionsnegative prefixDefinition: OREG[PRI] := (NOT OREG[PRI] << 4Purpose:    to allow negative operands to be       represented using a single negative       prefix instruction followed by zero       or more prefix instructions______________________________________
OPERATIONS FOR REGISTER MANIPULATION ETC
______________________________________reversedef:          SEQ          Oreg[Pri] := Areg[Pri]          Areg[Pri] := Breg[Pri]          Breg[Pri] := Oreg[Pri]purpose:      to reverse operands of asymmetric operations,         where this cannot conveniently be done in a         compilerreturndef:          SEQ          RIndexWord(WptrReg[Pri], 0, IptrReg[Pri])          AtWord(WptrReg[Pri], 4, WptrReg[Pri])purpose:      to return from a called proceduregeneral calldef:          SEQ          Oreg[Pri] := IptrReg[Pri]          IptrReg[Pri] := Areg[Pri]          Areg[Pri] := Oreg[Pri]purpose:      to perform a procedure call, with         a new instruction pointer in Areggeneral adjust workspacedef:          SEQ          Oreg[Pri] := WptrReg[Pri]          WptrReg[Pri] := Areg[Pri]          Areg[Pri] := Oreg[Pri]purpose:      to change the workspace of the         current process______________________________________
OPERATIONS FOR ADDRESSING
______________________________________load pointerto instructiondef:      AtByte(IptrReg[Pri], Areg[Pri], Areg[Pri])purpose:  to load a pointer to an instructionbyte subscriptdef:      SEQ      AtByte(Areg[Pri], Breg[Pri], Areg[Pri])      Breg[Pri] := Creg[Pri]purpose:  to compute pointers to items in vectors     to convert a number to a byte pointer using,     for example, ldc 0, ldw n, bsubword subscriptdef:      SEQ      AtWord(Areg[Pri], Breg[Pri], Areg[Pri])      Breg[Pri] := Creg[Pri]purpose:  to compute pointers to items in vectors     of words     to convert a number to a word pointer using,     for example, ldc 0, ldl n, wsubbyte countdef:      Areg[Pri] := Areg[Pri] * TraBytesPerWordpurpose:  to convert a length measured in words to one     measured in bytes. TraBytesPerWord means the     number of bytes per word used by the     microcomputer.word countdef:      SEQ      Creg[Pri] := Breg[Pri]      Breg := bytepart(Areg)      Areg :=  wordpart(Areg)purpose:  to convert a pointer into a byte offset from 0     using wcnt, bcnt, add______________________________________
______________________________________loop enddef:           SEQ            RIndexWord(Breg[Pri], 1, Creg[Pri])            Creg[Pri] := Creg[Pri] - 1            WIndexWord(Breg[Pri], 1, Creg[Pri])           IF            Creg[Pri] > 0             SEQ              RIndexWord(Breg[Pri], 0, Creg[Pri])              Creg[Pri] := Creg[Pri] + 1              WIndexWord(Breg[Pri], 0, Creg[Pri])              AtByte(IptrReg[Pri], -Areg[Pri],              IptrReg[Pri])            TRUE             SKIPpurpose:        to implement replicators______________________________________
SINGLE BYTE OPERATIONS
______________________________________load bytedef:            RIndexByte(Areg[Pri], 0, Areg[Pri])purpose:        to load a single bytestore bytedef:            SEQ            WIndexByte(Areg[Pri, 0, Breg[Pri])            Areg[Pri] := Creg[Pri]purpose:        to store a single byte______________________________________
______________________________________copy messagedef:      SEQ      Copy[Pri] := 1  indicate block copy      Treg[Pri] := NotProcess.p                      indicate not input                      or outputpurpose:  to set a vector of bytes to the value of     another block______________________________________
______________________________________greaterthandef:  SEQ  IF   Breg[Pri] > Areg[Pri]    Areg[Pri] := MachineTRUE   TRUE    Areg[Pri] := MachineFALSE  Breg[Pri] := Creg[Pri]pur   to compare Areg and Breg (treating them as twospose: complement integers), loading 1 (MachineTRUE) if Breg is greater than Areg, 0 (MachineFALSE) otherwise to implement b < a by (rev, gt) to implement b <=0 a as (gt, eqc 0), and Breg >= Areg by (rev, gt, eqc 0)______________________________________
______________________________________adddef:            SEQ            Areg[Pri] := Areg[Pri] + Breg[Pri]            Breg[Pri] := Creg[Pri]purpose: to load the sum of Breg and Aregsubtractdef:     SEQAreg[Pri] Areg[Pri] := Breg[Pri]     Breg[Pri] := Creg[Pri]purpose: to substract Areg from Breg, loading    the result    to implement     a = b      as sub, eqc 0     a <>b      as sub, eqc 0, eqc 0     if a <> b  as sub, eqc 0, cj,     if a = b   as sub, cj______________________________________
OPERATIONS FOR SCHEDULING
______________________________________minimum integerdef:       SEQ       Creg[Pri] := Breg[Pri]       Breg[Pri] := Areg[Pri]       Areg[Pri] := MostNegpurpose:   to access hard channels      to initialise soft channelsstart processdef:       SEQ       AtByte(IptrReg[Pri], Breg[Pri], Oreg[Pri])       WIndexWord(Areg[Pri], Iptr.s, Oreg[Pri]       ##STR13##       Runpurpose:   to add a process to the end of the active      process listend processdef:       SEQ       RIndexWord(Areg[Pri], 1, Oreg[Pri])       IF        Oreg[Pri] = 1         SEQ          RIndexWord(Areg[Pri], 0, IptrReg[Pri])          WptrReg[Pri] := Areg[Pri]        Oreg[Pri] <> 1         SEQ          WIndexWord(Areg[Pri], 1, Oreg[Pri]-1)          SNP[Pri] := 1purpose:   to join two parallel processes; two words are      used, one being a counter, the other a pointer      to a workspace, when the count reaches 1,      the workspace is changedrun processdef:       SEQ       ProDescReg := Areg[Pri]       Runpurpose:   to run a process at a specified prioritystop processdef:       SEQ       WIndexWord(WptrReg[Pri], Iptr.s,       IptrReg[Pri])       SNP[Pri] := 1purpose:   to deschedule the current processload prioritydef:       SEQ       Creg[Pri] := Breg[Pri]       Breg[Pri] := Areg[Pri]       Areg[Pri] := Pripurpose:   to obtain the priority of the current process______________________________________
______________________________________input message1.  def:      entered with2.             Areg = count3.             Breg = channel4.             Creg = destination5.         IF6.          hard(Breg[Pri])7.           LinkChannelInputAction8.          soft(Breg[Pri])9.           SEQ10.           RIndexWord(Breg[Pri], 0, Treg[Pri])11.           IF12.            Treg[Pri] = NotProcess.p13.             SEQ 14.       ##STR14##15.           WIndexWord(WptrReg[Pri], Iptr.s, IptrReg[Pri])16.           WIndexWord(WptrReg[Pri], State.s, Creg[Pri])17.           SNPFlag[Pri] := 118.        Treg[Pri] <> NotProcess.p20.          SEQ21.           WIndexWord(Breg[Pri], 0, NotProcess.p)         reset channel22.            prepare for block copy23.            Treg already contains process descriptor24.            Areg already contains count25.           Breg[Pri] := Creg[Pri] destination 26.       ##STR15##27.           RIndexWord(ProcPtrReg.State.s, Creg[Pri]) source28.           CopyFlag[Pri] := 1 set copy flagpurpose: to input a block of bytes from a channeloutput message1.  def:      entered with2.             Areg = count3.             Breg = channel4.             Creg = source5.         IF6.          hard(Breg[Pri])7.           LinkChannelOutputAction8.          soft(Breg[Pri])9.           SEQ10.           RIndexWord(Breg[Pri], 0, Ireg[Pri])11.            IF12.            Treg[Pri] = NotProcess.p13.             SEQ14.              WIndexWord(Breg[Pri], 0,       ##STR16##15.              WIndexWord(WptrReg[Pri], Iptr.s,            IptrReg[Pri])16.              WIndexWord(WptrReg[Pri], State.s,            Creg[Pri])17.              SNPFlag[Pri] := 118.         Treg[Pri] <> NotProcess.p Ready19.          SEQ 20.       ##STR17##21.         read the State location22.        RIndexWord(ProcPtrReg, State.s, Oreg[Pri])23.         check for Alternative process or Input process24.        IF25.         Oreg[Pri] = Enabling.p26.          SEQ27.           WIndexWord(ProcPtrReg , State.s, Ready.p) 28.       ##STR18##29.           WIndexWord(WptrReg[Pri], Iptr.s, IptrReg[Pri])30.           WIndexWord(WptrReg[Pri], State.s, Creg[Pri])31.           SNPFlag[Pri] := 132.         Oreg[Pri] = Waiting.p33.          SEQ34.           WIndexWord(ProcPtrReg. State.s, Ready.p) 35.       ##STR19##36.           WIndexWord(WptrReg[Pri], Iptr.s, IptrReg[Pri])37.           WIndexWord(WptrReg[Pri], State.s, Creg[Pri])38.           SNPFlag[Pri] := 139.           ProcDescReg := Trg[Pri]40.           Run41.         Oreg[Pri] = Ready.p42.          SEQ 43.       ##STR20##44.           WIndexWord(WptrReg[Pri], Iptr.s, IptrReg[Pri])45.            WIndexWord(WptrReg[Pri], State.s, Creg[Pri])46.           SNPFlag[Pri] := 147.         TRUE - Oreg[Pri] contains a valid pointer48.          SEQ49.            Reset channel50.           WIndexWord(Breg[Pri], 0, NotProcess.p)51.            Set up registers for block copy:52.            Treg[Pri] already contains description          inputting process53.           CopyFlag[Pri] := 1 indicate block copy54.           Breg[Pri] := Oreg[Pri] destinationpurpose: to output a block of bytes to a channel______________________________________
______________________________________alternative start1.  def:     WIndexWord(WptrReg[Pri], State.s, Enabling.p)    purpose: to initialise the process state location        prior to enabling alternative inputsalternative wait1.  def:     SEQ2.            WIndexWord(WptrReg[Pri], 0, -1)3.            RIndexWord(WptrReg[Pri], State.s, Areg[Pri])4.            IF5.             Areg[Pri] = Ready.p6.              SKIP7.             TRUE8.              SEQ9.               WIndexWord(WptrReg[Pri], State.s,            Waiting.p)10.              WIndexWord(WptrReg[Pri], Iptr.s            IptrReg[Pri])11.              SNPFlag[Pri] := 1purpose: to wait for one of a number of enabled    channelsalternative end    def:        SEQ1.               RIndexWord(WptrReg[Pri], 0, Oreg[Pri])2.               AtByte(IptrReg[Pri], Oreg[Pri], IptrReg[Pri])purpose: to start execution of the selected input    of an alternative processenable skip1.   def:     IF2.               Areg[Pri] <> MachineFALSE3.                WIndexWord(WptrReg[Pri], State.s,             Ready.p)4.               Areg[Pri] = MachineFALSE5.                SKIPpurpose:  to enable a SKIP guarddisable skipdef:      SEQ      IF       Breg[Pri] <> MachineFALSE        IsThisSelectedProcess       Breg[Pri] = MachineFALSE        Areg[Pri] := MachineFALSE      Breg[Pri] := Creg[Pri]purpose:  to disable a SKIP guardenable channel1.  def:     SEQ2.            IF3.             Areg[Pri] = MachineFALSE4.              SKIP5.             Areg[Pri] <> MachineFALSE6.              SEQ7.               IF8.                soft(Breg[Pri])9.                 SEQ10.                  RIndexWord(Breg[Pri], 0, Oreg[Pri])11.                 IF12.                  Oreg[Pri] = NotProcess.p13.                   WIndexWord(Breg[Pri], 0,         ##STR21##14.                  Oreg[Pri] =         ##STR22##15.                   SKIP16.                  TRUE17.                   WIndexWord(WptrReg[Pri],                 State.s,Ready.p)18.               hard(Breg[Pri])19.                VAR PortNo, Ready :20.                SEQ21.          WordOffset(PortBase, Breg[Pri], PortNo)22.          MakeLinkReadyStatusEnquiry(PortNo,Ready)23.          IF24.           Ready25.            WIndexWord(WptrReg[Pri],State.s,Ready.p)26.           TRUE27.            SEQ28.             WIndexWord(Breg[Pri], 0,         ##STR23##29              EnableLink(PortNo)30. Breg[Pri] :         = Creg[Pri]purpose: to enable a channel inputdisable channel1.  usage:   On entry                Areg = Instruction Offset2.                   Breg = Guard3.                   Creg = Channel4.           On exit IF5.                    this was selected guarded process6.                     Areg = MachineTRUE7.                    otherwise8.                     Areg = MachineFALSE9.  def:     IF10.           Breg[Pri] = MachineFALSE11.            Areg[Pri] : = MachineFALSE12.           Breg[Pri] <> MachineFALSE13.            IF14.             soft(Creg[Pri])15.              SEQ16.               RIndexWord(Creg[Pri]. 0, Breg[Pri])17.                IF18.                Breg[Pri] = NotProcess.p19.                 Areg[Pri] := MachineFALSE20.         ##STR24##21.                 SEQ22.                  WIndexWord(Creg[Pri], 0,                NotProcess.p)23.                  Areg[Pri] := MachineFALSE24.               TRUE25.                IsThisSelectedProcess26.             hard(Creg[Pri])27.              VAR PortNo, Ready :28.              SEQ29.               WordOffset(PortBase, Creg[Pri], PortNo)30.                Check if link channel is Ready.31.                This will cause channel to be disabled.32.               MakeLinkReadyStatusEnquiry(PortNo,             Ready)33.               IF34.                Ready35.                 IsThisSelectedProcess36.                TRUE37.                 Areg[Pri] := MachineFALSEpurpose: to disable an enabled channel    to select one of a number of    alternative enabled inputs______________________________________
The processor shares its time between a number of concurrent processes executing at the two different priority levels 0 and 1. A priority 0 process will always execute in preference to a priority 1 process if both are able to execute. At any time only one of the processes is actually being executed and this process which is the current process has its workspace pointer (WPTR) in the WPTR REG 51 and an instruction pointer (IPTR) in the IPTR REG 50 indicates the next instruction to be executed from the sequence of instructions in the program relating to that particular process. Any process which is not the current process and is not awaiting execution is descheduled. When a process is scheduled it either becomes the current process or is added to a list or queue of processes awaiting execution. Such a list is formed as a linked list with each process on the list having a pointer in the link location 66 of its workspace to the workspace of the next process on that list. The instruction pointer (IPTR) of any process on the list is stored in the IPTR location 65 of its workspace as shown in FIG. 3.
In the present case, the processor maintains two lists of processes which are waiting to be executed, for for each priority level. This situation is shown in FIGS. 3 and 4. FIG. 3 indicates the high priority 0 list whereas FIG. 4 shows a low priority 1 list at a time when a priority 0 process is the current process as shown in FIG. 3. As the current process in this case is a high priority 0 process, the register bank selector 41 has selected the registers in bank 39 for use by the processor. Consequently WPTR REG (0) holds a pointer to the zero location of the workspace 60 of the current process L as indicated in FIG. 3. The IPTR REG (0) contains a pointer 180 to the next instruction in the program sequence 181 which is stored in memory. The registers 54, 55, 56 and 57 indicated in FIG. 3 contain other values to be used during execution of the current process L. The list of priority 0 processes which have been scheduled and are awaiting execution is indicated in FIG. 3 by the three processes M, N and 0 whose workspaces are indicated diagrammatically at 61, 62 and 63. Each of these workspaces is generally similar to that indicated for process L. The FPTR REG (0) marked 53 contains the pointer to the workspace of process M which is the process at the front of this list. The workspace of process M contains in its IPTR location 65 a pointer to the next instruction in the program sequence which is to be executed when process M becomes the current process. The link location 66 of process M contains a pointer to the workspace of process N which is the next process on the list. The last process on the list indicated is process 0 which has its workspace indicated at 63. The BPTR REG (0) marked 52 contains a pointer to the workspace of this last process 0. The workspace 63 of this process 0 is pointed to by the contents of the link location 66 of the previous process N but in this case the link location 66 of process 0 does not contain any pointer as this is the last process on the list.
A process may be taken from the top of a list for execution by use of the procedure "dequeue" which has been defined above. That definition, together with various other definitions above, include line numbers which are not part of the definition but merely facilitate explanation. Line 1 of the definition of Procedure DEQUEUE merely gives the name of the procedure and line 2 indicates that a sequence of events are to occur. According to line 3 the WPTR REG 51 of the appropriate bank 38 or 39 takes the pointer which has been held in the FPTR REG 53 of the same bank. Line 4 indicates that a test of certain conditions is to be carried out. Line 5 indicates that if the contents of the BPTR REG 52 are found to be the same as the contents of the FPTR REG 53 then in accordance with line 6 the value "Not Process p" is loaded into the FPTR REG. Line 7 indicates that if the condition of line 5 was not found to be the case then line 7 applies in that the FPTR REG 53 of the appropriate register bank is loaded with the pointer currently stored in the link location 66 of the workspace previously pointed to by the contents of the FPTR REG. Finally, in accordance with line 9 the IPTR REG 50 is loaded with the IPTR from the IPTR location 65 of the workspace now pointed to by the contents of the WPTR REG 51.
A current process may be descheduled by the procedure "start next process" which has been defined above. A current process may execute an instruction which involves setting the SNP FLAG 58 to the value 1 and in that case, when the processor responds to a microinstruction requiring it to take the next action, the processor will execute the procedure in accordance with the above definition. According to line 3 of the definition the processor initially clears the flag by setting SNP FLAG 58 to the value 0. Line 4 requires the processor to test whether the condition of line 5 is true. Provided the FPTR register does not contain the value "Not Process p" then according to line 6 the dequeue procedure will occur so that the next process is taken off the top list. If however line 5 had not been true this would indicate that there was no process waiting on a list for the current priority. The processor would then check whether the condition of line 7 was true. That involves testing whether the PRI FLAG 47 has the value 0. If it does then we know that there is no priority 0 process waiting due to the result of the test in line 5 and consequently the processor goes on to the sequence commencing with line 9 of setting the priority flag to 1. This causes the processor to examine the register bank for the priority 1 processes and in accordance with lines 11 and 12 the processor checks to see whether the WPTR REG (1) contains the value "Not Process p" and that the FPTR REG (1) does not contain the value "Not Process p". This means that there was no interrupted priority 1 process which has left its WPTR in the WPTR REG 51 and that there is a waiting priority 1 process on the list. Provided this condition is true then according to line 13 the processor executes the procedure dequeue which causes the next priority 1 process to be taken off the front of the list. If however the condition of lines 11 and 12 were not correct then according to lines 14 and 15 the processor skips any action. This means that if there had been a WPTR in the WPTR REG (1) the processor will continue to execute that interrupted process. If there had not been an interrupted process and there had been nothing waiting on the priority 1 list then the processor will await scheduling of a further process. If however the processor had found that the condition in line 7 was not correct but on the other hand the priority was 1 then in accordance with lines 16 and 17 the WPTR REG (1) will take the value "Not Process p".
During message transition a process may be descheduled while waiting for a communicating process to reach a corresponding stage in its program. When the two communicating processes reach a corresponding stage the procedure "run" may be used to schedule a process whose descriptor is contained in the PROCDESC register 46. The action of the processor can then be understood from the definition of the procedure "run" set out above. In accordance with line 3 the priority of the process indicated by the PROCDESC register 46 is calculated and loaded into the PROCPRIFLAG 48. According to line 4 the WPTR of the process having its descriptor in register 46 is calculated and loaded into the PROCPTR REG 45. The processor then tests to see whether the conditions of line 6 apply. The current process has a priority of 0 or if the priority in the PROCPRIFLAG 48 is the same as the priority in the PRIFLAG 47 and at the same time the WPTR REG 51 of the current process contains a workspace pointer then the processor carries out the sequence following line 7. Line 7 merely explains that the sequence is that necessary to add a process to the queue. Line 8 requires that the processor carry out a test whether the condition of line 9 is true. Provided that the FPTR REG of the priority indicated by the flag 48 has the value "Not Process p" then according to line 10 that FPTR REG is loaded with the pointer of register 45. That makes the rescheduled process the top of the list. Line 11 indicates that if the condition of line 10 was not correct then the pointer contained in register 46 is written into the link location 66 of the last process on the list indicated by the BPTR REG of the appropriate priority. That BPTR REG is then loaded with a pointer to the contents of register 45. In other words the rescheduled process is added to the end of the list. Line 14 means that if the condition of line 6 was not the case then the sequence of line 15 will occur. In this case line 16 requires that the PRIFLAG 47 will take the value currently in the PROCPRIFLAG 48 and according to line 17 the WPTR REG of the appropriate priority will be loaded with the pointer from register 45. Line 18 requires that the IPTR REG 50 of appropriate priority will be loaded with the IPTR taken from the IPTR location 65 of the process indicated by the pointer in the WPTR REG 51. Line 19 inserts the value zero into the 0 register of the appropriate priority bank.
Process Y wishes to output a message to process X on the same microcomputer using a soft channel where both processes are of the same priority. This is illustrated in the sequence of FIG. 15. Initially the channel 70 contains the value "Not Process p" as neither process Y nor process X have yet executed an instruction which requires use of that channel. When process Y reaches the point in its program where it wishes to execute an output it loads into its AREG 54 a count indicating the number of bytes which constitute the message, it loads into the BREG 55 the address of the channel to be used for the communication and it loads into the CREG the source address which is the memory address for the first byte of the message to be transmitted. This is in accordance with lines 2, 3 and 4 of the definition of the operation "output message". Further line number references will relate to the definition of output message given above. Line 5 requires the processor to test the contents of the B register to see whether the channel address given corresponds to that of a hard channel. If it does then line 7 of the definition requires the processor to carry out the procedure "link channel output action" which has been defined above. In the example of FIG. 15 that is not the case and consequently line 8 of the definition is found to be true in that the B register contains the address of a soft channel. Consequently the processor carries out the sequence following line 9. In accordance with line 10 the TREG 49 is loaded with the value pointed to by the pointer from the B register with no offset i.e. the channel content. Lines 11 and 12 then require the processor to check whether the TREG contains the value Not Process p and this is of course the case in FIG. 15b. Consequently the processor carries out the sequence of lines 14 to 17 of the output message definition. Line 14 requires the process descriptor for process Y to be written into the channel 70. Line 15 requires the contents of the IPTR REG 50 to be stored in the IPTR location 65 of the workspace for process Y and line 16 requires the source address to be written into the state location 67 of the workspace of process Y. Line 17 requires the SNPFLAG to be set to 1 indicating that process Y should be descheduled by the next action of the processor. That is the position shown in FIG. 15c and remains the position until the inputting process X executes an input instruction.
Again process X first loads into its A register 54 a count of the number of bytes required for the message it is to input. It loads into its B register the address of the channel to be used for the input and its C register is loaded with the destination address in the memory for the first byte to be input. This is in accordance with lines 2, 3 and 4 of the definition of input message and is the position shown in FIG. 15d. Lines 5, 6 and 7 of the input message definition require the processor to check whether the address in the B register corresponds to a hard channel in which case the processor would be required to execute the link channel input action procedure. That is not the case in FIG. 15 as the B register points to the soft channel 70. Consequently the condition of line 8 is true and the sequence following line 9 occurs. Firstly the T register 49 for process X is loaded with the value pointed to by the pointer in thez B register with no offset i.e. the channel content. If that value had been " Not Process p" then the processor would have followed lines 13 to 17 which would have resulted in descheduling process X. However, in the present case the T register is found to meet the requirement of line 18 of the definition in that it does not contain "Not Process p". In accordance with line 21 of the definition the processor then resets the channel 70 by writing the value "Not Process p" into the channel 70 as shown in FIG. 15e. Lines 22 to 24 merely contain the explanation that the processor will now be prepared to carry out a block copy of data from one memory location (source) to another memory location (destination) while the T register 49 now contains the process descriptor of process Y and the A register contains the count of the number of bytes to be transmitted. Line 25 of the definition requires that the B register for process X is now loaded with the destination address which was previously is the C register. According to line 26 the PROC pointer register 45 is loaded with the WPTR of process Y which is derived by taking the process descriptor from register T and removing the priority bit. Line 27 requires that the C register for process X is loaded with the source address taken from the state location 67 of the workspace for process Y. Line 28 then requires the copy flag of the appropriate priority to be set to 1 so that at its next action the processor carries out the procedure "Block copy step" which has been defined above. This causes the processor to transfer one byte at a time from the source memory address to the destination memory address and it repeats this exercise progressively altering the source and destination addresses as each byte is transferred and progressively decreasing the count in the A register of the number of bytes remaining to be transferred. When the count is zero the descheduled process Y is rescheduled by the procedure run. This can be seen from the definition of block copy step. Line 2 defines the sequence that is to occur. The first step is line 3 which reads into the 0 register the byte from the source address in memory indicated by the C register. Line 4 then writes that byte of data from the 0 register into the destination memory address pointed to by the B register. Line 5 then clears the 0 register. Line 6 creates a new source pointer which is advanced by one byte and line 7 creates a new destination address which is advanced by one byte. Line 8 causes the count in the A register to be reduced by one. Line 9 then requires a test to be carried out to find whether in accordance with line 10 the A register now contains a zero count in which case the block copy has been completed. If the A register does not contain a zero count then the condition of line 21 is met. However, as the copy flag is still set to 1 the processor will continue to take an appropriate next action. If the priority of the process involved in the block copy is a low priority process and a high priority process has become ready to run then the processor may interrupt the block copy after transmitting one or a number of bytes prior to completion of the full message transfer in order to execute the higher priority process. However, assuming that there is no higher priority process awaiting then on reaching line 22 of the block copy step, the processor will repeat the sequence commencing from line 2 as the copy flag is still set. Consequently it will repeat the procedure of lines 3 to 8 of the block copy step until the count is zero. Line 13 then requires the copy flag to be cleared and reset to zero. Lines 14 and 15 require the processor to check whether the T register 49 has a value other than Not Process p. In the present case it will have the process descriptor of the descheduled process Y. Consequently the sequence beginning at line 16 will occur and the process descriptor register 46 will be loaded with the process descriptor of process Y which was previously contained in the T register. The previously described procedure run will then be effected in order to reschedule process Y. Lines 19 and 20 merely indicate that if the T register had not contained the process descriptor of a descheduled process then the action would have been skipped.
FIG. 16 shows in the sequence message communication between an outputting process Y on a first microcomputer 251 communicating with an inputting process X on a second microcomputer 252. The output pin 27 of an output channel 90 for process Y is connected by a single wire 253 to the input pin 26 of the input channel 91 for process X.
With all processes executing output or input using a hard channel the process is descheduled after executing the appropriate output or input instruction. The transfer of the required number of bytes from the source address in the memory of one microcomputer to the destination address in the memory of the other microcomputer is carried out under the control of the link units described in FIGS. 10, 11, 12, 13 and 14. The transfer of bytes is carried out independently of action by the processor so that the processor of both microcomputers can be executing current processes independently of the message transfer. When the links have reached a stage in the message transfer which require further action by the processor they make suitable requests to the processor. Each link channel has a channel address which consists of one addressable word in memory called the process word. The addresses of these hard channel process words are chosen so that the processor recognises them as hard channels needing separate connections to the links. In each of FIGS. 16, 17, 18 and 19 a similar format has been used for indicating the output channel 90 for process Y and the input channel 91 for process X. The channel has its associated process word 256 marked with the abbreviation PW. The output channel has registers 254 which have been described above in FIG. 12 and a location 257 in which the state of the transfer state machine 113 is indicated. For the input channel 91 the process word location 256 is shown as well as the input channel registers 255 which have already been described in FIG. 13 and a location 258 shows the states of the three state machines from FIG. 13. In FIG. 16 both processes have similar priority and the outputting process Y attempts to output a message before process X attempts to input a message. In accordance with lines 2 to 4 of the definition of "output message" process Y loads into the A register 54 the count of the number of bytes to be transmitted in the message, into the B register 55 the address of the channel to be used and into the C register 56 the source address in memory for the first byte to be copied. As is shown in FIG. 16a at this time the output channel is idle whereas the input channel has the states data absent, idle and disabled. After FIG. 16a process Y executes the operation "output message" and in accordance with line 6 of the definition of that operation the processor finds that the channel is a hard channel and consequently in accordance with line 7 the procedure "link channel output action" is carried out. The definition of that procedure "link channel output action" indicates that the current IPTR for process Y is taken from the IPTR 50 and stored in the IPTR location of the workspace for process Y. Line 5 requires that the process descriptor of process Y is written into the process word location 256 of the output channel 90. Line 6 sets the port number for the output channel and line 7 requires the procedure "cause link output" which has been described above. That transfers into the channel registers 254 the count source and priority from the appropriate registers in use in execution of the process Y. An input request is also made to the link channel so that the first byte of data is transmitted. According to line 8 the SNPFLAG is set to 1 so that the next action by the processor requires process Y to be descheduled as previously described. The position is as shown in FIG. 16b.
This relates to communication between an outputting process Y on one microcomputer passing message through a serial link to an inputting process X on a different microcomputer. Process X commences the input operations before Y executes any output instructions. None of the alternative inputs is ready at the time the process X commences. It further assumes that once one of the channels becomes ready due to output action by process Y none of the other alternative channels becomes ready. Initially process X executes "alternative start" and in accordance with the definition of that operation it writes "enabling p" into the state location 67 of the workspace of process X. The state machines of the output channel 90 and input channel 91 are as shown in FIG. 17a. Process X then executes the operation "enable channel". It does this for each of the possible input channels but FIG. 17b shows the result of this operation on the particular channel which will be used by process Y. As is shown in the definition of enable channel, process X initially loads a guard value into the A register and this is checked before proceeding with the operation. Lines 8 to 17 specify the sequence to be followed if the channel is a soft channel. In the present case the address of the channel corresponds to that of a hard channel and consequently the sequence from lines 21 to 29 are followed. Line 21 calculates the port number of the channel and line 22 causes the processor to make a status enquiry for that channel. Lines 23 to 25 indicate that if the channel had been ready, the value ready p would have been written into the state location 67 for the process X. However that is not the case and consequently the sequence from lines 27 to 29 apply. The process descriptor for process X is written into the process word location for the channel in accordance with line 28 of the definition and line 29 requires the procedure enable link which has been defined above. This sets the priority flag of the input channel to the priority of the process X and causes an enable request to the link channel. This causes the state of the channel to be changed to "enabled" as shown in FIG. 17b. Process X then executes an alternative wait. In accordance with line 2 of the definition of alternative wait this sets the value -1 into the zero location of the workspace for process X. Lines 3 and 4 check the content of the state location 67 to see if it is ready p. As it is not, the sequence of lines 8 to 11 are carried out. In other words the value waiting p is written into the state locations 67 for process X. The IPTR for process X is stored in the IPTR location 65 and process X is descheduled as a result of setting the SNPFLAG to 1. This is shown in FIG. 17c. After this process Y begins an output operation by effecting output message. In the usual way and as has been described above, this will cause process Y to be descheduled and the output link will send the first data byte. The arrival of that byte will cause the input link for process X to make a ready request to the processor for process X. This is the position shown in FIG. 17d. Process X then becomes rescheduled and carries out the operation "disable channel" which selects one channel and disables the rest. As can be seen from line 1 of the definition of disable channel, the A register is loaded with an instruction offset which is necessary to derive the address of the next instruction to be executed by the inputting process after the operation ALTEND. The B register has a guard value and the C register is loaded with the channel address. It will be understood that this instruction is repeated for each of the possible alternative input channels. Lines 9 and 10 deal with checking the guard values. Providing this test is satisfactory the processor tests according to lines 13 and 14 whether the channel address is that of a soft channel. However in the present case line 26 applies in that the address of the channel is that of a hard channel. Line 29 calculates the port number of the channel and line 32 causes a status enquiry to be made to the link by the processor. If the channel is found to be ready in accordance with line 34 the above defined procedure "is this selected process" is carried out. According to line 4 of that definition this loads into the 0 register the contents of the zero location of the workspace of process X. According to lines 5 and 6 this is tested to see if it is -1 and if so the contents of the A register are written to the memory location indicated by the WPTR REG and the A register has the value machine TRUE indicating that this is the selected process. In accordance with line 10 if the 0 register had not contained the value -1 then this would not be the selected process. FIG. 17e shows the state of the two processes immediately before executing disable channel and FIG. 17f shows the position after executing disable channel. After FIG. 17f process X executes the operation ALTEND which from line 1 of its definition loads the 0 register with the contents of the memory address indicated by the pointer in the WPTR register. It then puts a pointer into the IPTR register which has the previous value of the IPTR register together with the offset contained in the 0 register. This enables the process to continue at the desired position in its instruction sequence. After executing ALTEND, process X may load the appropriate values for the message transmission and execute input message which will carry out the sequence illustrated in FIG. 16 from FIG. 16c onwards.
Although the above example related to use of alternative hard channels, the sequence is generally similar where a process carries out an alternative input through one of a number of alternative soft channels. Initially execution of "alternative start" loads the special value "enabling p" to the state location of the process in order to indicate that the process is carrying out an alternative input. The operation "enable channel" is then carried out on each channel in order to test the state of the channel. Lines 12, 14 and 16 of the definition of "enable channel" check the contents of the channel. In accordance with line 12, if no workspace pointer is found in the channel the value "Not Process p" is written into the channel. In accordance with line 17, if the workspace pointer of the outputting process is found in the channel the value "Ready p" is written into the state location of the inputting process. This is done for each channel in order to check whether any is already "ready" as a result of an instruction executed by an outputting process and for any channels which are not found to be ready the workspace pointer of the inputting process is left in the channel. The inputting process then executes "alternative wait" which effects the inputting process rather than the channel. In accordance with line 2 of the definition it loads the value -1 into the zero location of the workspace for the inputting process and lines 5 and 7 of the definition of "alternative wait" check on the contents of the state location of the inputting process. If it finds value "Ready p" then the inputting process is not descheduled but if it does not find "Ready p" then according to line 9 of the definition it writes "waiting p" into the state location of the process and lines 10 and 11 of the definition lead to descheduling of the inputting process. If the inputting process was not descheduled then it will carry on with its next instruction which will be "disable channel". If on the other hand it had been descheduled it will in due course be rescheduled as a result of an outputting process attempting to use one of the alternative channels and when the inputting process is rescheduled it will resume with its next instruction which will be "disable channel". It will carry out this operation for each of the alternative channels and prior to each operation the A register will be loaded with an offset number to indicate the instruction offset necessary to locate the next instruction in the program sequence for that process should that channel be chosen for the input. Lines 18, 20 and 24 indicate respective tests on whether or not the channel contains the value "Not Process p", a pointer to the inputting process, or a pointer to an outputting process. If in accordance with line 24 it is found that the channel contains a pointer to an outputting process line 25 requires the procedure "is this selected process". According to the definition of this procedure, the zero location of the workspace of the process is checked to see that it still has the value -1 and provided it does this then becomes the selected channel for the input and the procedure removes the value -1 and writes into the zero location of the workspace the instruction offset necessary. When further "disable channels" operations are carried out on the remaining channels some may be found to be "ready" by holding a pointer to an outputting process but when the procedure "is this selected process" is carried out it will no longer locate the value -1 in the zero location of the workspace of the inputting process and consequently it will be apparent that a channel has already been selected and consequently no further channel is to be selected. Any channels which are still found to contain a pointer to the inputting process will meet the condition of line 20 of the "disable channel" definition and this will lead to the sequence following line 22 in which the channel is changed back to "Process p". After the "disable channel" operation has been carried out on all the alternative channels, the inputting process carries out the operation "alternative end" which transfers the instruction offset from the zero location of the workspace of the inputting process and causes the offset to be added to the instruction pointer for the process so that the continuing program for that process is picked up at the correct point in its instruction sequence.
The example shown in FIGS. 20a, 20b and 20c illustrate how a high priority process Y which is executed by the same microcomputer as a lower priority process X can cause interruption of process X. Process X is a low priority 1 process which during the course of its execution created process Y. As process Y has priority 0 which is the high priority process X was interrupted leaving its WPTR in the priority 1 WPTR REG 51. At the position shown in FIG. 20a process Y is the current process with the priority flag 47 set to indicate a priority 0 process and in the example shown no processes are waiting on a list for either priority 1 or priority 0. During execution of process Y it may wish to perform an output message using a link. This will cause wetting of the SNPFLAG to 1 as shown in FIG. 20b and process Y will be descheduled. The start next process procedure will clear the SNPFLAG 58 and the processor will test the FPTR (0) to determine if there was another process on the priority 0 list. As there is not (because the FPTR REG (0) contains the value Not Process p) the processor will set the PRIFLAG 47 to 1 and as the WPTR REG (1) contains a valid workspace pointer for the process X the procedure start next process performs no further action. The processor as its next action checks that there are no requests from links and the SNPFLAG (1) is not set and consequently it restarts execution of process X. This is the position in FIG. 20c. At some later stage the link through which process Y was outputting a message will have received the final acknowledge at the end of the succession of bytes which were incorporated in the message. At that time the link used by process Y will make a run request to the processor. On completion of the current action the processor will decide what action next to perform. The SNPFLAG (1) is not set and there is a run request for a channel priority 0 which is higher than that of priority X which is the current process. The processor therefore performs the procedure "handle run request" which copies the process descriptor of the waiting process Y into the PROCDESC REG and performs the run procedure. The run procedure loads the process workspace pointer of process Y into the PROCPTR REG and the priority of Y into the PROCPRIFLAG. As the priority of Y is higher than that of the priority indicated in the PRIFLAG of the current X process an interrupt occurs. The PRIFLAG is set to 0 and the WPTR REG (0) is set to the process workspace of Y and the IPTR REG (0) is loaded. The position has now returned to that shown in FIG. 20a The next action of the processor will be to execute the next instruction process Y which is the instruction following the output message instruction.
______________________________________1.          VAR rotations :2.          WHILE TRUE3.           SEQ4.            rotations := 05.            WHILE rotations < 10006.             SEQ7.              rotation ? ANY8.              rotations := rotations + 19.            mile ! ANY                Program in OCCAMInstruction Sequence language______________________________________                  Function                  code   Data                              VAR rotations:                              WHILE TRUE                               SEQ1.  L1:2.         ldc    0    7      0      rotations := 03.         stl    0    1      04.  L2:                              WHILE rotations <                                10006.         pfix   3    14     37.         pfix   14   14     14      SEQ8.         ldc    1000 7      89.         ldl    0    0      010.        opr    gt   13     1311.        cj     L3   10     1112.        ldlp   3    2      3        rotation ? ANY13.        ldl    1    0      114.        ldc    1    7      115.        opr    bcnt 13     716.        pfix   1    14     117.        opr    in   13     618.        ldl    0    0      0         rotations :=19.        adc    1    8      1    rotations + 120.        stl    0    1      021.        nfix   1    15     122.        j      L2   9      1523. L3:24.        ldlp   3    2      3      mile ! ANY25.        ldl    2    0      226.        ldc    1    7      127.        opr    bcnt 13     728.        pfix   1    14     129.        opr    out  13     730.        nfix   1    15     131.        j      L1   9      5______________________________________
______________________________________1.          VAR miles :2.          SEQ3.           miles := 04.           WHILE TRUE5.            ALT6.             mile ? ANY7.              miles := miles + 18.             fuel ? ANY9.              SEQ10.              consumption ! miles11.              miles := 0                Program in OCCAMInstruction Sequence language______________________________________                  Function                  code   Data                              VAR miles :                              SEQ1.         ldc    0    7      1     miles := 02.         stl    1    1      1     WHILE TRUE3.  L14.         pfix   1    14     15.         opr    alt  13     8      ALT6.         ldl    3    0      37.         ldc    1    7      18.         pfix   1    14     19.         opr    enbc 13     1310.        ldl    4    0      411.        ldc    1    7      112.        pfix   1    14     113.        opr    enbc 13     1314.        pfix   1    14     115.        opr    altwt                  13     916.        ldl    3    0      317.        ldc    1    7      118.        ldc    (L2-L2) 7                  019.        pfix   1    14     120.        opr    disc 13     1421.        ldl    4    0      422.        ldc    1    7      123.        ldc    (L3-L2) 7                  1024.        pfix   1    14     125.        opr    disc 13     1426.        pfix   1    14     127.        opr    altend 13                  1028. L2:29.        ldlp   2    2      2      miles ? ANY30.        ldl    3    0      331.        ldc    1    7      132.        opr    bcnt 13     733.        pfix   1    14     134.        opr    in   13     635.        ldl    1    0      136.        adc    1    8      1       miles := miles + 137.        stl    1    1      138.        j      L4   9      1239. L3:40.        ldlp   2    2      2      fuel ? ANY41.        ldl    4    0      4       SEQ42.        ldc    1    7      143.        opr    bcnt 13     744.        pfix   1    14     145.        opr    in   13     646.        ldlp   1    2      1        consumption ! miles47.        ldl    5    0      548.        opr    bcnt 13     749.        pfix   1    14     150.        opr    out  13     751.        ldc    0    7      0       miles := 052.        stl    1    1      153. L4:54.        nfix   3    15     355.        j      LI   9      15______________________________________
It can be seen that line 7 of the program requires an input from a channel "rotation" and this causes line 12 of the corresponding instruction sequence to load the destination address for the data to be input. Line 13 loads a pointer to the channel to be used. Line 14 loads a count of the number of words to be input. Line 15 converts the count from words to bytes. Lines 16 and 17 load the operation "input message" by use of the pfix function. Similarly line 9 of the program requires an output through a channel and in the corresponding instruction sequence line 24 loads a pointer to the source of data to be output. Line 25 loads a pointer to the channel to be used. Line 26 loads the count of the output message in words. Line 27 converts this count to bytes. Again line 28 and 29 use a pfix instruction in order to carry out the "output message" instruction.
This example includes an alternative inputting operation which commences at line 5 of the program. This requires an alternative input either from the channel "mile" in accordance with line 6 of the program or from channel "fuel" in accordance with line 8 of the program. In the corresponding instruction sequence it can be seen that the alternative input operation begins at line 5. Line 5 requires the operation "alternative start". Line 6 loads a pointer to the channel "mile". Line 7 loads a guard value "true". Lines 8 and 9 use as pfix function in order to operate "enable channel" for the channel "mile". Line 10 loads a pointer to the channel "fuel" and line 11 loads a guard value "true". Lines 12 and 13 use the pfix function in order to carry out the operation "enable channel" for the channel "fuel". Lines 14 and 15 use a pfix function in order to operate "alternative wait" for this process. Line 16 loads a pointer to the channel "mile" and line 17 loads a guard value "true". Line 18 loads the instruction offset which will be necessary if the process inputs through the channel "mile". In this case the offset required is 0. Lines 19 and 20 use the pfix function to carry out the operation "disable channel" on the channel "mile". Line 21 loads a pointer to the channel "fuel" and line 22 loads a guard value "true". Line 23 loads the instruction offset which will be necessary if the process inputs through the channel "fuel". Lines 24 and 25 use the pfix function in order to operate "disable channel" on the channel "fuel". Lines 26 and 27 use the pfix function in order to operate "alternative end".
1. A method of operating concurrent processes in a computer system wherein each concurrent process executes a program having plurality of instructions comprising the steps of:
(a) forming a respective first pointer for each concurrent process to identify the process,
(b) forming a respective second pointer for each concurrent process to indicate a program stage for the process,
(c) scheduling a plurality of the concurrent processes for execution by a processor, including
(i) indicating a process which is being executed by the processor, said process being referred to as the current process,
(ii) identifying one or more processes forming a collection awaiting execution by the processor,
(iii) in response to a particular instruction stopping execution of the current process, storing a second pointer for said current process, changing the indication of the current process to indicate the next process in said collection and then executing said next process at a program stage indicated by the second pointer of the said next process; and
(d) transmitting messages between concurrent processes so that data is transferred from an outputting process to an inputting process in a communicating pair of processes, each process in said air executing a sequence of instructions in a program including communication instructions, said scheduling step being responsive to said communication instructions so that message transmission between the pair of processes is completed when both are at corresponding program stages, the transfer of data being effected by
(i) transferring from one addressable location to another at least one message unit of predetermined bit length,
(ii) execution of at least one of the processes of each pair providing a count of the number of message units to be transferred in a message,
(iii) execution of the outputting process providing an indication of a source address from which data is to be output,
(iv) execution of the inputting process providing a destination address to which the data is to be input and
(v) transferring from the source address to the destination address the number of message units indicated by said count.
2. The method according to claim 1 wherein said concurrent processes are distributed in a computer system comprising a network of interconnected integrated circuit devices and said step of transmitting messages between concurrent processes further includes addressing communication channels of a first type to permit said data transfer to occur between processes on the same integrated circuit device and addressing channels of a second type to permit said data transfer to occur between two processes, one of which is on one integrated circuit device and the other of which is on a different integrated circuit device.
3. The method according to claim 1 further comprising establishing within said memory a respective workspace for each process, each workspace comprising a plurality of addressable memory locations, and recording in said locations of each workspace variables associated with the corresponding process, and wherein said identifying step in said scheduling step includes forming a linked list of said processes awaiting execution by providing in said workspace of each process on said linked list an indication of the first pointer for the respective next process scheduled for execution by the processor.
4. The method of operating concurrent processes according to claim 1 wherein the transfer of each message unit comprises transferring eight bits.
5. The method of operating concurrent processes according to claim 1 further including counting the number of message units transferred in a message and providing a signal when all message units in the message have been transferred.
6. A method according to claim 1 further including counting the number of message units transferred in a message and changing the indication of source address as the number of message units remaining to be transferred decreases.
7. The method according to claim 1 further comprising counting the number of message units transferred in a message and changing the indication of said destination address as the count of the number of message units remaining to be transferred decreases.
8. A microcomputer comprising memory and a processor coupled thereto and being operable to execute a plurality of concurrent processes in accordance with a plurality of program steps, said program steps comprising a plurality of instructions for sequential execution by the processor, each instruction including a set of function bits which designate a function to be executed by the processor wherein:
(a) the microcomputer includes a scheduling means comprising
(i) means for indicating the process which is being executed by the processor, said process being called the current process,
(ii) means for identifying one or more processes which form a collection awaiting execution by the processor, and
(iii) next process indicator means to indicate the next process in the collection to be executed by the processor,
(b) said processor includes means responsive to a selected one of said instructions to stop execution of said current process by said processor and to respond to said next process indicator means to make the next process in the said collection the current process, whereby the processor is operated to share its processing time among said plurality of concurrent processes; and
(c) said microcomputer includes message transmission means for effecting synchronized data transfer between two of said concurrent processes, said message transmission means comprising a plurality of communication channels, a status indicator to indicate the status of data communication through each channel and synchronizing means cooperating with said scheduling means to respond to said status indicator to interrupt a current process or add an interrupted process to said collection so that communication between two communicating processes is completed when the two processes are at corresponding program steps, said message transmission means further comprising
(i) means for transferring from one addressable location to another a message unit of predetermined bit length,
(ii) means responsive to execution of a message instruction to provide a count of the number of message units to be included in a message,
(iii) source addressing means responsive to execution of a message instruction by an outputting process to indicate the address from which data is to be output and
(iv) destination addressing means responsive to execution of a message instruction by an inputting process to indicate the address to which the data is to be input.
9. The microcomputer according to claim 8 wherein said means for identifying processes comprises a linked list indicating processes awaiting executing by said processor and means for indicating the last process on said linked list.
10. A microcomputer according to claim 9 wherein said memory provides for each process a respective workspace having a plurality of addressable locations, each of said workspaces including:
(i) memory locations for recording variables associated with a corresponding process,
(ii) a program stage indicator for the corresponding process and
(iii) a portion of said linked list when the corresponding process itself is on said linked list, said linked list portion indicating the next process on said linked list.
11. The microcomputer of claim 8 wherein said message transmission means permits data transfer between processes executed on the same microcomputer, at least one of said communication channels comprising a memory location.
12. A microcomputer according to claim 11 in which the processor further includes means for copying directly a number of bytes of data indicated as a result of execution of a message instruction, directly from one byte address to another in the memory of the microcomputer.
13. A microcomputer according to claim 8, wherein the message transmission means is arranged to permit external data transmission between processes which are executed on different microcomputers and the or each channel comprises an external communication link.
14. A microcomputer according to claim 13, wherein each external communication link comprises store means for holding one byte of data.
15. A microcomputer according to claim 14, wherein each external communication link is arranged to transmit a succession of bytes without action by the processor.
16. A microcomputer according to claim 15, wherein each external communication link is arranged to deschedule a process which executes a message instruction using the address of that link and each link includes means for storing an indication of the number of bytes to be transmitted through the link together with a pointer to the source or destination address for the next byte of the message.
17. A microcomputer according to claim 16, in which each external communication link includes means for counting the number of bytes transmitted and providing an indication when all bytes have been transmitted.
18. A microcomputer according to claim 16, wherein each external communication link includes signal generating means to generate a request signal to the processor to reschedule the process involved in the message transmission when all bytes of the message have been transmitted.
19. A network of directly interconnected micro-computers each comprising a single integrated circuit microcomputer, each said microcomputer comprising memory and a processor coupled to said memory and being operable to execute a plurality of concurrent processes in accordance with a plurality of program steps, said program steps comprising a plurality of instructions for sequential execution by the processor, wherein:
(a) each said microcomputer includes a scheduling means comprising
(i) means for indicating the process which is being executed on said microcomputer, said process being called the current process,
(b) each said processor including means responsive to a selected one of said instructions to stop execution of said current process by said processor and to respond to said next process indicator means to make the next process in the said collection the current process whereby each processor is operated to share its processing time among said plurality of concurrent processes, and
(c) each said microcomputer including message transmission means for effecting synchronized data transfer between two of said concurrent processes, said message transmission means comprising a plurality of communication channels, a status indicator to indicate the status of data communication through each channel and synchronizing means cooperating with said scheduling means to respond to said status indicator to interrupt a current process or add an interrupted process to said collection so that communication between two communicating processes is completed when the two processes are at corresponding program steps, said message transmission means further comprising
20. A network according to claim 19 wherein each said means for identifying processes comprises a respective linked list indicating processes awaiting execution by said processor and means for indicating the last process on said linked list, and wherein said memory provides for each process on the microcomputer a respective workspace having a plurality of addressable locations, each of said workspaces including:
(iii) a portion of said linked list when the corresponding process is on said linked list, said linked list portion indicating the next process on said linked list.
US06756431 1983-11-04 1984-11-02 Computer system with variable length process to process communication Expired - Lifetime US4783734A (en)
GB8329509A GB8329509D0 (en) 1983-11-04 1983-11-04 Computer
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EP0145244A2 (en) 1985-06-19 application
WO1985002038A2 (en) 1985-05-09 application
EP0145244B1 (en) 1990-02-21 grant
GB8329509D0 (en) 1983-12-07 grant
US4758948A (en) 1988-07-19 grant
EP0141660A2 (en) 1985-05-15 application
EP0149311A3 (en) 1985-09-25 application
EP0149311A2 (en) 1985-07-24 application
WO1985002037A3 (en) 1985-07-18 application
JP2664662B2 (en) 1997-10-15 grant
WO1985002039A2 (en) 1985-05-09 application
WO1985002039A3 (en) 1985-07-18 application
EP0141660B1 (en) 1990-09-26 grant
EP0141660A3 (en) 1985-10-02 application
DE3481389D1 (en) 1990-03-29 grant
EP0149311B1 (en) 1990-04-11 grant
JPS61500386A (en) 1986-03-06 application
WO1985002038A3 (en) 1985-07-18 application
WO1985002037A2 (en) 1985-05-09 application
DE3483306D1 (en) 1990-10-31 grant
DE3481946D1 (en) 1990-05-17 grant
JP2664663B2 (en) 1997-10-15 grant
JPS61500385A (en) 1986-03-06 application
JPS61500387A (en) 1986-03-06 application
US4794526A (en) 1988-12-27 grant
JP2664664B2 (en) 1997-10-15 grant
EP0145244A3 (en) 1985-09-25 application
Owner name: INMOS LIMITED WHITEFRIARS, LEWINS MEAD, BRISTOL B
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:MAY, MICHAEL D.;SHEPHERD, ROGER M.;REEL/FRAME:004432/0753