Source: http://www.google.com/patents/US6771476?dq=6437692
Timestamp: 2014-07-13 18:49:05
Document Index: 544885815

Matched Legal Cases: ['application No. 1999', 'application No. 1999', 'application No. 2000', 'application No. 2000', 'application No. 2000', 'application No. 2000', 'application No. 2000', 'application No. 2000', 'application No. 2001']

Patent US6771476 - Circuit protector - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA circuit protector comprising a substrate, a conductive layer formed around the substrate, a narrowed portion formed on the conductive layer at a certain part, terminals formed at both ends of the substrate. The substrate has 1-30% pores in a unit surface area in a vicinity of its surface. The present...http://www.google.com/patents/US6771476?utm_source=gb-gplus-sharePatent US6771476 - Circuit protectorAdvanced Patent SearchPublication numberUS6771476 B2Publication typeGrantApplication numberUS 10/032,861Publication dateAug 3, 2004Filing dateDec 27, 2001Priority dateDec 27, 2000Fee statusPaidAlso published asCN1233008C, CN1365131A, DE10164240A1, DE10164240B4, US20020097547Publication number032861, 10032861, US 6771476 B2, US 6771476B2, US-B2-6771476, US6771476 B2, US6771476B2InventorsMichio Fukuoka, Kenichi Hasegawa, Yasuki Nagatomo, Eizo Hatanaka, Hideyuki Tokada, Toshiyuki IwaoOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (20), Non-Patent Citations (9), Referenced by (5), Classifications (14), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetCircuit protectorUS 6771476 B2Abstract A circuit protector comprising a substrate, a conductive layer formed around the substrate, a narrowed portion formed on the conductive layer at a certain part, terminals formed at both ends of the substrate. The substrate has 1-30% pores in a unit surface area in a vicinity of its surface. The present invention also relates to a mounting structure of the circuit protector onto a circuit board.
0.40<(L2�L3)<0.90 where, L3 is a width of longer side of said rectangle, L2 a width of shorter side of said rectangle. 18. The circuit protector of claim 1, wherein a cross sectional shape of said terminal is elliptic, and a face parallel to the major axis of said elliptic shape opposes to a circuit board, when the circuit protector is mounted thereon.
FIELD OF THE INVENTION The present invention relates to a circuit protection device for use in an electronic apparatus, a battery-driven mobile electronic apparatus, etc.; more specifically, those circuit protection devices used in memory devices such as hard disk drives, optical disk drives built in personal computers or mobile personal computers.
BACKGROUND OF THE INVENTION Some of the circuit protection devices (hereinafter referred to as circuit protector) for protecting a circuit board or the like apparatus from an over current have been disclosed in, for example, Japanese Laid-open Patent Publications No. H02-43701, No. H05-120985, No. H03-201504 and so on. Along with the increasing popularity of downsized electronic apparatus, the demand is increasing for components of smaller dimensions. At the same time, requirements in characteristics of such components are becoming more stringent.
Thus, the conventional circuit protectors are not capable of controlling the heat diffusion to a circuit board effectively. As a result, the pre-arcing time-current characteristics (hereinafter referred to as �characteristics�) and other performance items remain out of a stringent control.
SUMMARY OF THE INVENTION A circuit protector of the present invention comprises a substrate, a conductive layer formed around the substrate, a narrowed portion formed on the conductive layer at a certain part, terminals formed at both ends of the substrate. The substrate has 1-30% pores in a unit surface area in a vicinity of its surface. The present invention also relates to a structure relating to the mounting circuit protectors on a circuit board.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a circuit protector in accordance with an exemplary embodiment of the present invention.
FIG. 5 is a side view showing a so-called �Manhattan phenomenon�.
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a perspective view of a circuit protector in accordance with an exemplary embodiment of the present invention. FIG. 2 shows the circuit protector of FIG. 1 as viewed from the direction Z, with part of the protection material 14 removed.
A narrowed portion 13 a is provided at a part of the conductive layer 12, and is disposed in an vicinity of an area restricted by the two ends of continuous groove 13. A circuit protector of the present invention controls the fusing current at the narrowed portion 13 a by defining at least one item among the width of narrowed portion 13 a and the layer thickness of conductive layer 12. It is manufactured based on specifications obtained and established through experiments with respect to such elements as the material for substrate 11, the material and layer thickness of conductive layer 12, and the width of narrowed portion 13 a, so that the narrowed portion 13 a melts when a 5A current flows between the ends 11 b and 11 c. When an electric current of a certain specific value (e. g. 5A) flows between the terminals 15 and 16 (see FIGS. 1 and 9), the narrowed portion 13 a melts down; thereby, the circuit protector protects a circuit board or the like (in the following recited as �board�) or an electronic apparatus from getting damaged.
Coefficient of thermal expansion: lower than 5�10−4/� C. (preferably lower than 2�10−5/� C.) [20� C.-500� C.]
A substrate 11 meeting the foregoing properties in thermal expansion coefficient substantially avoids possible crack troubles. This contributes also to prevent deterioration of the conductive layer 12, and wide deviation in the characteristic with the conductive layer 12 can be prevented. If the coefficient of thermal expansion of substrate 11 is higher than 5�10−4/� C., it would invite cracks due to heat shock, because when a substrate 11 undergoes a laser beam processing or machining with a grindstone for forming the groove 13 temperature of the substrate 11 becomes high locally.
A ceramic material containing alumina as the main ingredient is one of the preferred materials for substrate 11. However, a substrate 11 made of such a ceramic material does not immediately yield the superior characteristics described in the foregoing. The favorable characteristics can only be obtained when substrates 11 are produced under controlled manufacturing conditions, which including such factors as the pressing pressure, the sintering temperature, and certain additives added. Some of the manufacturing conditions are; for example, a pressing pressure of 2-5 t, sintering temperature of 1500-1600� C., sintering time of 1-3 hours.
Furthermore, referring to FIG. 1, width W1 of the narrowed portion 13 a, and space W2 between the groove 13 and the grooves 13 b, 13 c should preferably conform to a relationship; W2�W1 is more than 1.15. Since this relationship provides a stable characteristic without accompanying an increased electric resistance. W1 is normally 10 μm-40 μm.
An insulating layer having a thermal conductivity lower than 5.0 W/(m�k) is formed on substrate 11 for 0.01 μm-1.5 μm thick by means of vacuum deposition or sputtering, and then a conductive layer 12 is formed on the insulating layer. In this way, the pore area per unit area can be reduced, and the heat diffusion is suppressed. Thereby, the characteristic is improved.
Relative relationship between L2 and L3 should preferably be; 0.4<L2�L3<0.90 (more preferably 0.6<L2�L3<0.8). Formation of a narrowed portion 413 a becomes difficult if the L2�L3 is smaller than 0.4. When the L2�L3 is greater than 0.9, there will be a risk that it is mounted erroneously on the smaller face.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5621375 *Mar 7, 1995Apr 15, 1997Cooper IndustriesSubminiature surface mounted circuit protectorUS5664320 *Mar 23, 1995Sep 9, 1997Cooper IndustriesMethod of making a circuit protectorUS5726621 *Aug 11, 1995Mar 10, 1998Cooper Industries, Inc.Ceramic chip fuses with multiple current carrying elements and a method for making the sameUS5774037 *Oct 7, 1996Jun 30, 1998Cooper Industries, Inc.Circuit protector and method for making a circuit protectorJP2001023502A Title not availableJP2001143599A Title not availableJPH025326A Title not availableJPH113820A Title not availableJPH0243701A Title not availableJPH0723921A Title not availableJPH01228101A Title not availableJPH03201504A Title not availableJPH05120985A Title not availableJPH10284307A Title not availableJPH11111504A Title not availableJPS5315556A Title not availableJPS5622601A Title not availableJPS5632402A Title not availableJPS5838988A Title not availableJPS49130345A Title not available* Cited by examinerNon-Patent CitationsReference1Japanese Office Action for patent application No. 1999-188746 dated Apr. 25, 2002.2Japanese Office Action for patent application No. 1999-188746 dated Aug. 7, 2002.3Japanese Office Action for patent application No. 2000-164299 dated Apr. 30, 2002.4Japanese Office Action for patent application No. 2000-164299 dated Aug. 8, 2002.5Japanese Office Action for patent application No. 2000-397685 dated Apr. 25, 2002.6Japanese Office Action for patent application No. 2000-397685 dated Aug. 8, 2002.7Japanese Office Action for patent application No. 2000-397686 dated Apr. 25, 2002.8Japanese Office Action for patent application No. 2000-397686 dated Aug. 9, 2002.9Japanese Office Action for patent application No. 2001-183173 dated Apr. 25, 2002.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7005727 *Sep 3, 2002Feb 28, 2006Intel CorporationLow cost programmable CPU package/substrateUS7413936Nov 9, 2005Aug 19, 2008Intel CorporationMethod of forming copper layersUS7884698 *Apr 30, 2004Feb 8, 2011Panasonic CorporationElectronic component, and method for manufacturing the sameUS8426249Jun 15, 2010Apr 23, 2013Panasonic CorporationChip part manufacturing method and chip partsUS20100245028 *Nov 6, 2008Sep 30, 2010Tomoyuki WashizakiCircuit protective device and method for manufacturing the same* Cited by examinerClassifications U.S. Classification361/103, 361/306.2International ClassificationF16L25/00, F16L37/084, H01H37/76Cooperative ClassificationH01H85/0052, H01H85/06, H01H85/046, H01H2085/0414, H01H69/022, H01H85/0411European ClassificationH01H85/046, H01H85/041B, H01H69/02BLegal EventsDateCodeEventDescriptionJan 23, 2012FPAYFee paymentYear of fee payment: 8Jan 11, 2008FPAYFee paymentYear of fee payment: 4Mar 26, 2002ASAssignmentOwner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUKUOKA, MICHIO;HASEGAWA, KENICHI;NAGATOMA, YASUKI;AND OTHERS;REEL/FRAME:012768/0371Effective date: 20020220Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. KADOMA-SHFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUKUOKA, MICHIO /AR;REEL/FRAME:012768/0371RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google