Source: https://patents.justia.com/patent/8228594
Timestamp: 2019-10-19 18:00:59
Document Index: 194411380

Matched Legal Cases: ['art 256', 'art 255', 'art 232', 'arts 232', 'arts 232', 'art 232', 'arts 255', 'arts 255', 'arts 232', 'art 255', 'art 232', 'art 232', 'art 232', 'arts 232', 'arts 232', 'art 256', 'arts 232', 'art 271', 'art 271']

US Patent for Spatial light modulator with metal layers Patent (Patent # 8,228,594 issued July 24, 2012) - Justia Patents Search
Justia Patents By Changing Physical Characteristics (e.g., Shape, Size Or Contours) Of An Optical ElementUS Patent for Spatial light modulator with metal layers Patent (Patent # 8,228,594)
Oct 9, 2009 - Silicon Quest Kabushiki-Kaisha
Specifically, FIG. 1C exemplifies, as related disclosures, a circuit diagram for controlling a micromirror according to U.S. Pat. No. 5,285,407. The control circuit includes memory cell 32. Various transistors are referred to as “M*” where “*” designates a transistor number and each transistor is an insulated gate field effect transistor. Transistors M5, and M7 are p-channel transistors; transistors, M6, M8, and M9 are n-channel transistors. The capacitances, C1 and C2, represent the capacitive loads in the memory cell 32. The memory cell 32 includes an access switch transistor M9 and a latch 32a based on a Static Random Access switch Memory (SRAM) design. All access transistors M9 on a Row line receive a DATA signal from a different Bit-line 31a. The particular memory cell 32 is accessed for writing a bit to the cell by turning on the appropriate row select transistor M9, using the ROW signal functioning as a Word-line. Latch 32a consists of two cross-coupled inverters, M5/M6 and M7/M8, which permit two stable states, including a state 1 when Node A is high and Node B is low and a state 2 when Node A is low and Node B is high.
Further, the figure indicates the deflection axis 212a, about which a mirror 212 is deflected, using a dotted line. The light emitted from the light source 510 possessing a coherent characteristic is made to enter the mirror 212 so as to be in the orthogonal or diagonal direction (e.g., the range between 0 and 30 degrees) in relation to the deflection axis 212a. The light source 510 possessing a coherent characteristic is, for example, a laser light source.
An OFF electrode 215 and an OFF stopper 215a are placed symmetrically across the hinge 213 that comprises a hinge electrode 213a on the substrate 214, and likewise an ON electrode 216 and an ON stopper 216a are placed thereon.
The OFF electrode 215, when a predetermined voltage is applied thereto, attracts the mirror 212 with a Coulomb force to tilt it to a position abutting on the OFF stopper 215a. This causes the incident light 511 incident to the mirror 212 to be reflected to the light path of an OFF position that is shifted from the optical axis of the projection optical system 130.
The ON electrode 216, when a predetermined voltage is applied thereto, attracts the mirror 212 with a Coulomb force to tilt it to a position abutting on the ON stopper 216a. This causes the incident light 511 incident to the mirror 212 to be reflected to the light path of an ON position that matches the optical axis of the projection optical system 130.
An OFF capacitor 215b is connected to the OFF electrode 215 and to the bit line 221-1 by way of a gate transistor 215c that is constituted by a field effect transistor (FET) and the like.
Further, an ON capacitor 216b is connected to the ON electrode 216, and to the bit line 221-2 by way of a gate transistor 216c that is constituted by a field effect transistor (FET) and the like.
The opening and closing of the gate transistor 215c and gate transistor 216c are controlled through the word line 231.
That is, a horizontal one row of the pixel units 211 in line with an arbitrary word line 231 are simultaneously selected, and the charging and discharging of capacitance to and from the OFF capacitor 215b and ON capacitor 216b are controlled by the bit line driver unit 220 and word line driver unit 230 through the bit lines 221-1 and 221-2, and thereby the individual ON/OFF controls of the mirrors 212 in the respective pixel units 211 within the present one horizontal row are carried out.
In other words, the OFF capacitor 215b and gate transistor 215c on the side where the OFF electrode 215 is placed constitute a memory cell M1 that is so called a DRAM structure.
Likewise, the ON capacitor 216b and gate transistor 216c on the side where the ON electrode 216 is placed constitute a DRAM-structured memory cell M2.
In this case, the disclosed configurations of the memory cells M1 and M2 use metal-insulator-metal (MIM) capacitors as the OFF capacitor 215b and ON capacitor 216b.
That is, FIG. 4A shows the horizontal section of a part of the hinge 213 of the pixel unit 211, in which the hinge 213 is placed such that the longitudinal direction of the rectangular section of the hinge 213 matches the direction of the deflection axis 212a.
The hinge electrode 213a connected to the hinge 213 is placed at the position immediately under the present hinge 213, and further, conductor patterns which will constitute the OFF electrode 215 and ON electrode 216 are symmetrically placed sandwiching the hinge electrode 213a (which is also the deflection axis 212a).
The second ON electrode 235 and grounding Via hole filler conductor 238 are respectively placed at the corner parts sandwiching the hinge electrode 213a (and the deflection axis 212a) at the center and positioning on the outside of the ON electrode 216 and OFF electrode 215.
FIG. 4D shows the layout, in the horizontal section, at the height of the upper capacitor plate of the ON capacitor 216b and the height of the gate transistor 215c.
The present embodiment is configured to place the OFF capacitor 215b and ON capacitor 216b straddling the deflection axis 212a of the pixel unit 211 in the diagonal direction.
FIG. 4E shows the layout, in the horizontal section, at the height where the gate transistor 215c and gate transistor 216c are placed, the height that is lower than the FIG. 4D.
The gate transistor 215c and gate transistor 216c are placed parallel to each other along the direction of placing the word line 231 at the center.
As exemplified in FIGS. 4D and 4E, the gate transistor 215c and OFF capacitor 215b are placed straddling the deflection axis 212a of the mirror 212, and so are the gate transistor 216c and ON capacitor 216b.
The source (i.e., the N-well 214b) of the gate transistor 215c (or gate transistor 216c) and the upper capacitor plate 216b-2 of the OFF capacitor 215b (or ON capacitor 216b) become an electric potential (simply noted as “potential” hereinafter) for controlling the mirror 212, and therefore a transistor and a capacitor are preferred to be placed on a side corresponding to the tilting direction of the mirror 212 as close as possible.
Further, the present embodiment is also configured to wire a poly-silicon gate electrode 214c and word line 231 mutually parallel and overlapped with each other as exemplified in FIG. 4E.
As such, the present embodiment is configured to wire the word line 231 in parallel and overlapped with the poly-silicon gate electrode 214c, in a first layer metal wiring layer ML1, relative to the poly-silicon gate electrode 214c which is placed linearly in the ROW direction, in order to reduce the resistance and stray capacitance of the word line 231 and improve the drive speed of the ROW line.
FIG. 5 is a cross-sectional diagram of the part along the line A-A as indicated in FIGS. 4D and 4E, that is, a cross-sectional diagram of the part of the gate transistor 216c provided for controlling the ON electrode 216.
Introducing an N-type impurity with a field oxidized film (FOX) formed on the principal surface of a substrate 214 made of, for example, a P-type semiconductor used as a mask forms a pair of N-wells 214b; then selectively having the field oxidized film between the pair of N-wells 214b remain forms a gate oxidized film 214a; and placing the poly-silicon gate electrode 214c on and along the formed gate oxidized film 214a, thereby the gate transistor 216c is formed.
The present embodiment is also configured to deposit four metal layers, i.e., the first layer metal wiring layer ML1 through fourth layer metal wiring layer ML4, with insulation layers 214d intervening between the respective adjacent layers, thereby forming various wirings (which are described later).
Note that the insulation layers 214d are actually sequentially deposited between the respective adjacent wiring layers; the borders on which the insulation layer 214d is deposited is not depicted in the figure for easy comprehension thereof.
In this case, the word line 231 is placed in approximately the same width as that of the poly-silicon gate electrode 214c by using the first layer metal wiring layer ML1 right above the poly-silicon gate electrode 214c, with the word line 231 connected to the poly-silicon gate electrode 214c through a contact hole filler conductor 231a.
A flat conductor pattern 221c and conductor pattern 221q are formed in the first layer metal wiring layer ML1 that is at the same height as the word line 231 is.
The conductor pattern 221q, on the lower side thereof, is connected to one N-well 214b of the gate transistor 216c by way of a contact hole filler conductor 221a.
Meanwhile, the conductor pattern 221q, on the upper side thereof, is connected to the bit line 221-2 equipped in the third layer metal wiring layer ML3 by way of Via hole filler conductor 221p, conductor pattern 221n (i.e., the second layer metal wiring layer ML2) and Via hole filler conductor 221m.
The other N-well 214b of the gate transistor 216c is connected to the upper capacitor plate 216b-2 of the ON capacitor 216b by way of the contact hole filler conductor 221b, flat conductor pattern 221c, Via hole filler conductor 221d, conductor pattern 221e (i.e., the second layer metal wiring layer ML2), Via hole filler conductor 221f, conductor pattern 221g (i.e., the third layer metal wiring layer ML3) and Via hole filler conductor 221h.
A lower capacitor plate 216b-1 that is formed as the second layer metal wiring layer ML2 simultaneously with the conductor pattern 221e and conductor pattern 221n is placed oppositely to the upper capacitor plate 216b-2, with a capacitor insulation film 216b-3 intervening between the aforementioned two plates, and thus the two plates form the ON capacitor 216b.
The capacitor insulation film 216b-3 is made of, for example, tantalum pentoxide (Ta2O5) or zirconium dioxide (ZrO2), or consists of a layered film constituted by a film made of tantalum pentoxide (Ta2O5) and that made of niobium pentoxide (Nb2O5).
With this configuration, charging the ON capacitor 216bc from the bit line 221-2 is controlled by the ON/OFF operation of the gate transistor 216c that is controlled through the word line 231.
The upper capacitor plate 216b-2 is connected to the ON electrode 216 by way of the Via hole filler conductor 221h, conductor pattern 221g, Via hole filler conductor 221i, conductor pattern 221j and Via hole filler conductor 221k.
The lower capacitor plate 216b-1 of the ON capacitor 216b is connected to the hinge electrode 213a by way of the Via hole filler conductor 213f, conductor pattern 213e, the Via hole filler conductor 213d, conductor pattern 213c and Via hole filler conductor 213b.
Furthermore, the entire top surface of the second ON electrode 235 is covered with an insulation film 214e functioning as etching stopper, and the ON electrode 216, hinge electrode 213a and further an OFF electrode 215 (which is described later) are placed on the insulation film 214e.
FIG. 6 is a cross-sectional diagram showing the connecting relationship in the first layer metal wiring layer ML1 through fourth layer metal wiring layer ML4 for one pixel unit 211 that comprises the mirror 212, OFF electrode 215 on the OFF side, gate transistor 215c and OFF capacitor 215b (constituting the memory cell M1).
The OFF capacitor 215b, which is constituted by lower capacitor plate 215b-1, upper capacitor plate 215b-2 and capacitor insulation film 215b-3 and which is connected to the OFF electrode 215, and the bit line 221-1 are equipped on the side where the memory cell M1 is placed.
The capacitor insulation film 215b-3 is formed simultaneously with the capacitor insulation film 216b-3 placed on the side where the above described ON capacitor 216b is placed and is made of, for example, tantalum pentoxide (Ta2O5) or zirconium dioxide (ZrO2), or consists of a layered film constituted by a film made of tantalum pentoxide (Ta2O5) and that made of niobium pentoxide (Nb2O5) as described above.
Then, on the side where the memory cell M1 of the OFF electrode 215 is placed, the connecting state of the bit line 221-1, OFF capacitor 215b and OFF electrode 215 is controlled by way of the gate transistor 215c.
Here, the present embodiment is configured to set the forms of the components belonging to the first layer metal wiring layer ML1, i.e., the flat conductor pattern 221c and conductor pattern 221q, the components belonging to the second layer metal wiring layer ML2, i.e., lower capacitor plate 215b-1, conductor pattern 221e and conductor pattern 221n, the components belonging to the third layer metal wiring layer ML3, i.e., the conductor pattern 221g and conductor pattern 213e, and the components belonging to the fourth layer metal wiring layer ML4, i.e., modified plate line 232, conductor pattern 221j and conductor pattern 213c in such a manner as to overlap with one another when viewed from the thickness direction of the device as described below, thereby efficiently preventing the incident light 511 irradiated onto the mirror 212 from entering inside of the memory cell M1 or M2 and thusly preventing the memory cell M1 or M2 of the spatial light modulator 200 from malfunctioning due to an irradiation of the incident light 511. While the materials of all metal wiring layers may be arbitrarily selected, the commonly used material is aluminum or copper. As for the production method, a damascene process or the like may be applied.
FIG. 7 is a plain view diagram showing an exemplary layout of a CMOS structure constituting the gate transistors 215c and 216c comprised in some pixel units 211 which are adjacent to each other in the direction of the bit line 221 of a spatial light modulator 200.
The present embodiment is configured to place substrate grounding unit 250 for every four pixels in the longitudinal direction (i.e., the vertical up/down direction of FIG. 7) of the bit line 221. The substrate grounding unit 250 is formed, simultaneously with the N-well 214b, on the surface of the substrate 214 by mean of a doping and is connected to an external ground potential.
In each pixel unit 211, the gate transistor 216c of the memory cell M2 and the gate transistor 215c memory cell M1 are parallel placed in a pair, with the gate oxidized film 214a and poly-silicon gate electrode 214c placed in such a manner as to traverse the respective centers of the aforementioned two transistors.
Further, the contact hole filler conductor 221a and contact hole filler conductor 221b are connected to the respective N-wells 214b that are placed with the poly-silicon gate electrode 214c sandwiched in between.
Placing the substrate grounding unit 250 for each transistor or capacitor will increase the area size. However, the present embodiment is configured to place the substrate grounding unit 250 for each minimum number of (i.e., for every four pixels in the case of the present embodiment) transistors that is required (i.e., the gate transistor 215c and gate transistor 216c) and capacitors (i.e., the OFF capacitor 215b and ON capacitor 216bc) that are placed above the aforementioned transistors as described above, and therefore it is possible to use the area size of the circuit forming region of the substrate 214 very effectively. In other words, it is possible to secure the largest possible layout area size of a transistor and capacitor. The higher the withstanding voltage of a transistor, the better for driving a mirror, requiring 10 volts or higher, or more preferably up to 20 volts if the layout area size can be secured.
As exemplified in FIG. 8, the word line 231, flat conductor pattern 221c and conductor pattern 221q are placed in the first layer metal wiring layer ML1.
The word line 231 is connected to the poly-silicon gate electrode 214c on the lower side by way of the contact hole filler conductor 231a.
The flat conductor pattern 221c is connected to the contact hole filler conductor 221b on the lower side and to the Via hole filler conductor 221d on the upper side.
The conductor pattern 221q is connected to the contact hole filler conductor 221a on the lower side and to the Via hole filler conductor 221p on the upper side.
The present embodiment is also configured such that the conductor pattern 221q connects the contact hole filler conductor 221a and Via hole filler conductor 221p together along the shortest distance obtained by combining straight lines that are parallel to the word line 231 and bit line 221.
In contrast, the flat conductor pattern 221c is formed in a flat form having a relatively larger area size so as to compensate for the respective narrow parts (i.e., the neck parts) of the lower capacitor plate 216b-1 and lower capacitor plate 215b-1 of the second layer metal wiring layer ML2 (which is described later).
Further, dummy flat conductor patterns 221c used for shielding light are placed at the end (in the viewpoint of FIG. 8) of the array (i.e., near to the substrate grounding unit 250).
The second layer metal wiring layer ML2 is equipped with ground pattern 256 and ground pattern 255, each of which is composed of continuous arrays of the lower capacitor plates 216b-1 and lower capacitor plates 215b-1, respectively, in the direction connecting to the substrate grounding units 250, and the both ends of the ground pattern 256 and the ground pattern 255 arrays are connected to the substrate grounding units 250 with Via hole filler conductors 251 intervening between them.
That is, the present embodiment is configured such that the ground pattern 256 and ground pattern 255 are also used as the lower capacitor plate 216b-1 (of the ON capacitor 216b) and lower capacitor plate 215b-1 (of the OFF capacitor 215b), respectively, in the second layer metal wiring layer ML2.
This configuration makes it possible to decrease the number of metal wiring layers when compared with a case of placing the lower capacitor plate 216b-1 and lower capacitor plate 215b-1 in a different layer from a layer that places the ground pattern 256 and ground pattern 255.
Between the lower capacitor plates 216b-1, which are adjacent in the array direction, and between the lower capacitor plates 215b-1, which are also adjacent in the array direction, are narrow as indicated by pattern neck part 256a and pattern neck part 255a, whereas the above described flat conductor pattern 221c of the first layer metal wiring layer ML1 is formed as an approximate rectangle so as to compensate for the neck part when viewed in the layering direction.
FIG. 10 exemplifies a case in which the lower capacitor plates 216b-1 (of the ground pattern 256) and lower capacitor plates 215b-i (of the ground pattern 255), both of which are serially arrayed in the direction connecting the substrate grounding unit 250, are arrayed without allowing a gap between the respective plates 216b-1 and 215b-1.
The respective ends of the arrays of the lower capacitor plate 216b-1 and lower capacitor plate 215b-i are connected to the substrate grounding unit 250 that is fundamentally at the same potential, and therefore the adjacent individual plates (i.e., the plates 216b-1; and plates 215b-1) may be placed integrally in the midst of the array without causing a problem. In the figure, although the ends of the ground patterns 256 and 255 seem to be cut off, they are actually connected to the neighboring ground patterns (in both of the horizontal directions).
The upper capacitor plate 216b-2 (of the ON capacitor 216b) and upper capacitor plate 215b-2 (of the OFF capacitor 215b), both of which are in rectangular forms, are respectively placed above the corresponding lower capacitor plates 216b-1 and lower capacitor plates 215b-1 with the capacitor insulation film 216b-3 and capacitor insulation film 215b-3 intervening between the respective upper and lower capacitor plates. The capacitance of the capacitors is preferably larger than 10 femto Farad (fF), and accordingly the present embodiment makes it possible to secure a necessary area size for the capacitor.
The third layer metal wiring layer ML3 is equipped with the bit lines 221-1 and 221-2 in a pair and with the conductor pattern 221g and conductor pattern 213e.
The bit lines 221-1 and 221-2 are placed in a certain width and in such a manner as to not overlap with either of the upper capacitor plate 215b-2 and upper capacitor plate 216b-2, which are in the lower layer, in order to not generate an extraneous stray capacitance.
This configuration secures the respective area sizes of the upper capacitor plate 215b-2 and upper capacitor plate 216b-2 so as to place the OFF capacitor 215b and ON capacitor 216b effectively and to obtain the maximum possible capacitance thereof.
Further, the bit lines 221-1 and 221-2 are placed without overlapping with the OFF capacitor 215b and ON capacitor 216b, and therefore these capacitors are not influenced by the current flowing in the bit lines 221-1 and 221-2 when data is loaded onto the capacitors, and thereby it is possible to perform an accurate tilting operation of the mirror 212 by means of the electric charge accumulated in the OFF capacitor 215b and ON capacitor 216b.
The conductor pattern 221g is provided for connecting the upper capacitor plate 215b-2 and upper capacitor plate 216b-2 to the gate transistor 215c (of the memory cell M1) and gate transistor 216c (of the memory cell M2), respectively, while the conductor pattern 213e is provided for connecting together the second layer metal wiring layer ML and fourth layer metal wiring layer ML4.
The modified plate line 232, conductor pattern 213c and conductor patterns 221j on the ON and OFF sides are placed in the fourth layer metal wiring layer ML4.
In this case, the modified plate line 232 is equipped with a second ON electrode placement part 232a used for placing the second ON electrode 235 and, in addition, with branch parts 232b and 232c used for increasing the shielding effect.
The conductor pattern 213c is connected to the ground pattern 255 of the second layer metal wiring layer ML2 by way of the third layer metal wiring layer ML3.
Further, the conductor patterns 221j on the ON and OFF sides are connected to the conductor pattern 221g and conductor pattern 213e, respectively, of the third layer metal wiring layer ML3.
In each pixel unit 211, the rectangular hinge electrode 213a having the center axis in the diagonal direction of the rectangular mirror 212 (not shown in this figure) is placed at the center, and the OFF electrode 215 and ON electrode 216 are placed so as to surround the hinge electrode 213a.
The hinge electrode 213a is connected to the conductor pattern 213c of the fourth layer metal wiring layer ML4, and the OFF electrode 215 and ON electrode 216 are together connected to the conductor pattern 221j of the fourth layer metal wiring layer ML4.
Next is a description of a light shielding effect of the modified plate line 232 comprising the flatly formed flat conductor pattern 221c (which is described above), branch parts 232b and 232c.
That is, FIG. 15A shows the case of placing, in the first layer metal wiring layer ML1, a commonly used fine line conductor pattern 221c-1, in place of the flat conductor pattern 221c according to the present embodiment.
FIG. 15D shows the fourth layer metal wiring layer ML4 in the case of placing a commonly used simple plate line 232-1, as a reference technique, in place of using the modified plate line 232 comprising the branch part 232b according to the above described present embodiment.
When viewed from the irradiating direction of the incident light 511, the pattern neck parts 255a and 256a of the ground patterns 255 and 256 are left as gaps 255g and 256g caused by the forms of the present pattern neck parts 255a and 256a of the ground patterns 255 and 256, respectively.
Then, the incident light 511 irradiates the gate transistor 215c and/or gate transistor 216c of the substrate 214 through the gaps 255g and 256g, constituting a cause for a malfunction of the spatial light modulator 200.
In contrast, the present embodiment is configured to use the flat conductor pattern 221c having a larger area size, in place of using the fine line conductor pattern 221c-1, and to place, instead of the simple plate line 232-1, the modified plate line 232 comprising the branch parts 232b and 232c as shown in the above described FIGS. 8 and 13, thereby closing the gap 255g of the above described pattern neck part 255a, making it possible to securely prevent the incident light 511 from entering the substrate 214.
This configuration differs from the above described reference technique where the flat conductor pattern 221c having a larger area size, instead of the fine line conductor pattern 221c-1, is placed in the first layer metal wiring layer ML1 shown in FIG. 17A, and the modified plate line 232 comprising the branch part 232b is equipped in the fourth layer metal wiring layer ML4 shown in FIG. 17D, in place of equipping the simple plate line 232-1.
Further, the area size (i.e., the length of extrusion) of the branch part 232b of each modified plate line 232 may be changed to the likes of the branch part 232c on an as required basis in terms of the layout or the like.
In the example of FIG. 17D, the branch parts 232c of the modified plate line 232 of the pixel unit 211 that is adjacent on the lower side is shorter than the branch parts 232b on the upper side. The reason is that the layout of the CMOS structure and the layout of the metal wiring layer are slightly shifted from the layout of the electrode and mirror because the substrate grounding unit 250 is provided for every four pixels.
As exemplified in FIG. 18, it is clearly comprehensible that there is no gap 256g of the pattern neck part 256a according to the reference technique shown in the above described FIG. 16 due to the presence of the wide flat conductor pattern 221c and the branch parts 232b and 232c of the modified plate line 232 and thereby the invasion of the incident light 511 into the substrate 214 is completely prevented.
That is, the present embodiment makes it possible to shield the invasion of the incident light 511 into the substrate 214 by placing the flat conductor pattern 221c and modified plate line 232, without a need to equip a specific use shield layer.
Further, in the case of the present embodiment, where the forms are changed are only the flat conductor pattern 221c in the first layer metal wiring layer ML1 and the modified plate line 232 in the fourth layer metal wiring layer ML4, and therefore a minimum change is required of the individual layers and an increase in the stray capacitance is prevented.
The present embodiment is configured to form a barrier metal layer 260 possessing a light shielding property so as to cover the insulation film 214e, on which the OFF electrode 215, ON electrode 216 and hinge electrode 213a are placed.
Further, the OFF electrode 215, ON electrode 216 and hinge electrode 213a are covered with an insulative protection film 270, securing the insulation against the barrier metal layer 260.
The insulative protection film 270 of the OFF electrode 215 and ON electrode 216 also plays the function of OFF stopper 215a and ON stopper 216a and is effective to prevent stiction.
However, the insulative protection film 270 covering the hinge electrode 213a is equipped with an opening part 271, and the hinge electrode 213a is connected to the hinge electrode 213a on the lower side by way of the barrier metal layer 260 deposited on the opening part 271. A use of silicon or the like material as the material of the insulative protection film 270 provides an effectiveness of heat resistance.
Although the configuration (as exemplified in FIGS. 19 and 20) comprising the barrier metal layer 260 on the insulation film 214e provides benefit by itself, it may be combined with the light shielding structure comprising the above described flat conductor pattern 221c and modified plate line 232.
The spatial light modulator 200 according to the present embodiment exemplified in FIGS. 19 and 20 is configured to deposit the barrier metal layer 260 on the insulation film 214e on which the OFF electrode 215, ON electrode 216, hinge electrode 213a and the like, thereby making it possible to prevent the incident light 511, which is irradiated on the spatial light modulator 200 from the light source 510, from entering internally to the substrate 214.
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Patent Publication Number: 20100027101
Inventors: Akira Shirai (Tokyo), Yoshihiro Maeda (Tokyo), Fusao Ishii (Pittsburgh, PA)
Application Number: 12/587,663