Source: https://russianpatents.com/patent/229/2297721.html
Timestamp: 2019-09-20 17:16:25
Document Index: 441960752

Matched Legal Cases: ['art 2', 'art 12', 'art 2', 'art 12', 'art 12', 'art 12', 'art 2', 'art 2', 'art 12', 'art 12', 'art;\n3', 'art 2', 'art 12', 'art 2', 'art 2', 'art 12', 'art 12', 'art 12', 'art 2', 'art 2', 'art 12', 'art 12']

Radio communication equipment with orthogonal frequency multiplexing
The invention relates to radio engineering, in particular to synchronization in digital communications systems.
Known radio system for U.S. patent No. 6515960, 04J 11/00 Radio communication system (radio System), 2003, the system consists of a set of terminals, interacting signals with orthogonal frequency multiplexing (ochm). Foreign sources [1, 2]. this modulation scheme called orthogonal frequency division multiplexing (OFDM). The formation of such a signal, and demodulation is performed using fast Fourier transforms (FFT and inverse FFT), which for the correct decoding at the receiving side requires synchronization. Information in the above-mentioned device is transmitted frames, consisting of a preamble in the form of M-sequences and many OCM symbols modulated bits of information. Synchronization of the receiver is performed on the preamble at the beginning of each frame. This radio control system is working properly, if the misalignment between transmitter and receiver is relatively small and varies slowly. So, in the paper [3] gives the following estimate of the desired frequency adjustment window FFT with data transfer speeds of 155 Mbps in the 60 GHz band: a single measure of sampling rate to 50000 counts or 300 OCM characters. If you apply signals OCM in the shortwave (KB) d is AMAZONE, the adjustment of the FFT window is required for almost every character OCM. Reducing the length of the frame is unprofitable, it increases the redundancy of the signal and thus the loss of the advantages of this type of modulation.
Known also radio equipment using signals OCM described in article A.L.Intini, "Orthogonal Frequency Division Multiplexing for Wireless Networks", University of California, Santa Barbara, aintini@engineering.ucsb.edu, December 2000. (Alentine "Orthogonal frequency multiplexing for wireless networks"). The synchronization principle of this instrument is based on the use of the correlation properties of OCM character. Full OCM symbol is typically composed of N samples, obtained by using the inverse FFT and cyclic prefix (Ngtimes, join to beginning of symbol). Full length OCM symbol equal to (Ng+N) times. Some authors refer to the length of the symbol OCM only N samples and a cyclic prefix of Ngtimes called a protection interval. In any case, the presence of two identical segments in the signal enables you to synchronize, based on a calculation of the correlation function. The disadvantage of these devices is that synchronization is a fragment of the signal, the most affected by distortion due to multipath signal propagation. In [4] this lack of p is sought to eliminate the use of only part of the N gsamples of cyclic prefix for the calculation of the correlation function, which again leads to an increase in redundancy, since the length of the cyclic prefix Ngyou have to choose is certainly more than is dictated by the delay in the channel. If it can be valid in the gigahertz ranges, KB bands such synchronization in hardware or simply does not work (with a small number of samples used to calculate the correlation or redundancy of the structure of the signal is unacceptable.
Closest to the technical essence of the present invention is a radio equipment presented on Fig in U.S. patent No. 6771976, 04J 11/00 "Radiocommunication apparatus, radiocommunication system, and radiocommunication method" (radio Equipment, radio system and method of radio communication), 2004, adopted for the prototype.
Functional diagram of the device of the prototype is presented in figure 1, where we have introduced the following notation:
1 - control unit communication [corresponds to item 11 on Fig the patent application];
2 - transmitting part [corresponds to the element 209];
3 - modulator differential quadrature phase-shift keying (Dcvmn) [corresponds to the element 12];
4 - shaper signal synchronization [corresponds to element 206];
5 - the first switch [corresponds to element 205];
6 is an orthogonal modulator h is frequency multiplexing (ochm) [corresponds to the element 13];
7 - analog Converter (DAC) [corresponds to the
8 - second switch [corresponds to the element 17];
9 - frequency (RF) Converter [corresponds to the element 18];
10 antenna [corresponds to item 26];
11 - analog-to-digital Converter (ADC) [corresponds to the
12 - receiving portion [corresponds to the element 10];
13 - demodulator OCM [corresponds to the element 20];
14 - demodulator Dcvmn [corresponds to the element 21];
15 is a block autocorrelation detection (AAA) [corresponds to the element 22];
16 is a block intercorrelation detection (KJV) [corresponds to the element 24];
17 is a control block [corresponds to the element 27];
18 is a block demodulation cycles [corresponds to the element 23];
19 - masking unit [corresponds to the element 25].
The device prototype contains connected in series control unit connection 1, the first input which is the input of the transmitting part 2, digital to analog Converter (DAC) 7 and the second switch 8, serially connected analog-to-digital Converter (ADC) 11 and the receiving part 12, the output of which is connected to a second input of control unit connection 1, the second output which is the output device. In addition, includes an antenna 10 connected to the first input of high frequency (the H) Converter 9, the second input-output of which is connected with the second input is the output of the second switch 8, the first output of which is connected to the ADC input 11.
Thus, the transmission part 2 contains connected in series modulator differential quadrature phase-shift keying (Dcvmn) 3, the inlet of which is the input of the transmitting part, the first switch 5 and the modulator orthogonal frequency division multiplexing (ochm) 6 whose output is the output of the transmitting portion 2, and also contains the shaper of the clock signal 4, the output of which is connected with the second input of the first switch 5.
The reception part 12 comprises a control unit 17 connected to the control input of the second switch 8, connected in series demodulator OCM 13 and demodulator Dcvmn 14 whose output is the output of the receiving part 12, connected in series block intercorrelation detection (KJV) 16, a masking block 19 and block demodulation cycles 18, the output of which is connected with the second input of the demodulator OCM 13; and contains the block autocorrelation detection (AOD) 15, the output of which is connected with the second input masking unit 19; and the first input of the demodulator OCM 13 connected to the inputs of the block AAA 15 and block EVA 16, is the entrance of the receiving part 12.
The information shall include the signal at the first input of control unit connection 1, which, according to the description of the patent, performs the functions of the encoder and decoder code, error-correcting. The encoded information signal is fed to the input of the transmitting part 2, where it is fed to the input of the modulator Dcvmn 3, in which each pair of bits of the encoded information signal is mapped to a complex number. The stream of complex numbers from the output of the modulator Dcvmn 3 is fed to the first input of the first switch 5, to the second input of which is applied the clock signal from the shaper signal synchronization 4. The synchronization signal is an M-sequence. Using the first switch 5, the synchronization signal is inserted into a stream of complex numbers and serves as a preamble in the frame. The signal in the form of complex numbers from the output of the first switch 5 to the input of the modulator OCM 6, where the inverse FFT is performed and the necessary conversion of the signal format (a series-parallel, and Vice versa). The signal at the output of the transmitting part 2 is a temporary timing multi-frequency signal, which is fed to the input of the DAC 7. The analog signal from the DAC output 7 via the second switch 8 is supplied to the RF Converter 9, where it is transferred to the carrier frequency through the antenna 10 radiates into the channel.
The received signal from antenna 10 is supplied to the RF Converter 9, which assests who is converting the RF signal into videofactory range. On command from the control unit 17 switches the second switch 8 (transmission/reception). From the output of the RF Converter 9 via the second switch 8 accept videofactory signal is input to the ADC 11, with which the digital signal is input to the receiving part 12, where it is fed to the first input of the demodulator OCM 13 and inputs the blocks AAA 15 and EVA 16.
The samples mutual correlation function of the received signal and the synchronization signal exceeding a certain threshold, the output unit 16 serves at the first input masking unit 19. Simultaneously with the EVA unit 16 has a block AAA 15, in which the computation of the autocorrelation function of Ng samples of the cyclic prefix and tail fragment OCM character. The samples of the autocorrelation function from the output unit 15 serves to the second input masking unit 19. In the masking block 19 samples of the autocorrelation function are compared with a threshold, and the result of the comparison is the command that enables or disables the signal from block 16 to block demodulation cycles 18, the output of which forms the control signal demodulator OCM 13. In the demodulator OCM 13 FFT is performed and the necessary conversion of the signal format (a series-parallel and parallel-to-serial), resulting in the received signal from the temporary predstavlyayutsya in frequency. The samples of the signal from the output of the demodulator OCM 13 is fed to the input of the demodulator Dcvmn 14, where there are bits of coded information, which are output from the receiving part 12 receives the second input of control unit connection 1 where are decoded, and then fed to the output device.
The meaning of parallel work units AAA 15 and EVA 16 in the device prototype is to remove the side peaks of the intercorrelation function generated in block 16. According to the description of the patent, as the preamble uses two period M-sequence generated by the 4-tier case (see Fig.6 in the description of the patent). That is, the length of M-sequence is equal to 24-1=15. This signal has low immunity [5], and in conditions of multipath propagation, the side peaks of the correlation function becomes the amplitude is comparable with the main peak (see Fig in the description of the patent), resulting in instead of tuning may fail synchronization. Block AAA 15 allows you to cut all emissions outside some neighborhood of the main peak of the correlation of the preamble.
The disadvantage of this device prototype is a low speed, and accuracy of the adjustment clock signal (time window FFT) when used in channels with strong variability of parameters, for example, in KB channels, where the time and frequency shifts of characters OCM change Auda from one character to such an extent, it becomes impossible to correctly decode the information.
To address these shortcomings in the radio equipment with an orthogonal frequency multiplexing, containing connected in series control unit connection, the first input which is the input of the transmitting part, digital to analog Converter, a second switch, analog-to-digital Converter and the receiving part, the output of which is connected to a second input of control unit connection, the second output which is the output device; an antenna via a radio-frequency Converter connected with the second input is the output of the second switch; and transmitting the part contains connected in series modulator differential quadrature phase manipulation, the input of which is the input of the transmitting part, the first switch and the modulator orthogonal frequency division multiplexing whose output is the output of the transmitting part, and the shaper of the synchronization signal, the output of which is connected with the second input of the first switch; receiving portion comprises a control unit connected to the control input of the second switch block autocorrelation detection, block intercorrelation detection and consistently connected to the orthogonal demodulator frequent the spas multiplexing and demodulator differential quadrature phase manipulation, the output which is the output of the receiving part according to the invention, the receiving part introduced the first memory block, the third switch, connected in series, the fourth switch, the block select maximum and the unit of calculation of time intervals, sequentially the United counter and the second memory block; the first output of the third switch through the power of the autocorrelation detection connected to the first input of the fourth switch, the second output of the third switch through the block intercorrelation detection is connected to a second input of the fourth switch and the meter inlet, second and third outputs of which are connected respectively with the second and third inputs of the block select maximum, the second output of which is connected with the second the input of the memory block, the output of which is connected with the second input of the block of calculation of time intervals, the second output of which is connected with the second Manager input of the third switch and the first output unit for calculation of time intervals connected with the second managing input of the first memory block, the output of which is connected to the input of the demodulator orthogonal frequency multiplexing; the first input of the first memory block connected to the first input of the third switch is an input receiving part.
Functional diagram of the proposed device is presented in figure 2, where we have introduced the following notation:
1 - unit communication control;
2 - transmitting part;
3 - modulator differential quadrature phase-shift keying (Dcvmn);
4 - shaper signal synchronization;
5 is a first switch;
6 - modulator orthogonal frequency division multiplexing (ochm);
7 - analog Converter (DAC);
8 - second switch;
9 - high-frequency (HF) transducer;
10 antenna;
11 - analog-to-digital Converter (ADC);
12 - receiving portion;
13 - demodulator OCM;
14 - demodulator Dcvmn;
15 is a block autocorrelation detection (AAA);
16 is a block intercorrelation detection (EVA);
17 is a control block;
18 - the first block of memory;
19 - the second memory block;
20 - the third switch;
21 - the fourth switch;
the 22 - block select max;
23 - the counter;
24 - unit calculation of time intervals.
The proposed device has connected in series control unit connection 1, the first input which is the input of the transmitting part 2, digital to analog Converter (DAC) 7 and the second switch 8; serially connected analog-to-digital Converter (ADC) 11 and the receiving part 12, the output of which is connected to a second input of control unit connection 1, the second output of which is o the home device. In addition, includes an antenna 10 connected to the first input-output frequency (RF) Converter 9, the second input-output of which is connected with the second input is the output of the second switch 8, the first output of which is connected to the ADC input 11.
Thus, the transmission part 2 contains connected in series modulator differential quadrature phase-shift keying (Dcvmn) 3, the inlet of which is the input of the transmitting portion 2, the first switch 5 and the modulator orthogonal frequency division multiplexing (ochm) 6 whose output is the output of the transmitting part 2; and also includes a shaper of the clock signal 4, the output of which is connected with the second input of the first switch 5.
The reception part 12 comprises a control unit 17 connected to the control input of the second switch, connected in series, the first memory unit 18, a demodulator OCM 13 and demodulator Dcvmn 14 whose output is the output of the receiving part 12; connected in series, the third switch 20, block autocorrelation detection (AOD) 15, the fourth switch 21, the block select maximum 22 and the block of calculation of time intervals 24, the first output of which is connected with the second managing input of the first memory block 18; connected in series block intercorrelation detection (KJV) 16, the counter 23 and the second block of the memory 19, the output of which is connected with the second input of the block of calculation of time intervals 24, the second output of which is connected with the second Manager input of the third switch 20, the second output of which is connected to the input of the EVA unit 16, the output of which is connected to a second input of the fourth switch 21; and the second and third outputs of the counter 23 are connected respectively with the second and third inputs of the block select max 22, a second output of which is connected with the second input of the second memory block 19; the first input of the first memory block 18 connected to the first input of the third switch 20 is input receiving part 12.
The information signal is applied to the first input of the control unit connection 1, which performs the functions of the encoder and decoder. The encoded information signal is fed to the input of the transmitting part 2, where it is fed to the input of the modulator Dcvmn 3, in which each pair of bits of the encoded information signal is mapped to a complex number. The stream of complex numbers from the output of the modulator Dcvmn 3 is fed to the first input of the first switch 5, to the second input of which is applied the clock signal from the shaper signal synchronization 4. The synchronization signal is an M-sequence. Using the first switch 5 synchro signal is Itachi is inserted into a stream of complex numbers and serves as a preamble in the frame. The signal in the form of complex numbers from the output of the first switch 5 to the input of the modulator OCM 6, which performs the inverse FFT and the necessary conversion of the signal format (a series-parallel and Vice versa). The signal at the output of the transmitting part 2 is a temporary timing multi-frequency signal, which is fed to the input of the DAC 7. The analog signal from the DAC output 7 via the second switch 8 is supplied to the RF Converter 9, where it is transferred to the carrier frequency, and through the antenna 10 radiates into the channel.
The main difference of the operation receiving part of the device from the prototype is that the synchronization signal, detected by EVA unit 16, is used to establish frame synchronization, where the frame prenimaetsa sequence of several tens or hundreds of characters OCM, and the block AAA 15 serves to synchronize the individual characters within the frame. To establish frame synchronization, as in the device prototype, signal synchronization, which serves as a preamble in the frame, but unlike the prototype, the proposed device, the synchronization signal generated by the block 4 may be transferred for several consecutive symbols OCM (for example, 2-5 characters).
The signal begins with a search of the preamble. The received signal from antenna 10 postupaet RF Converter 9, which converts the RF signal into videofactory range. On command from the control unit 17 switches the second switch 8, and the output of the RF Converter 9 via the second switch 8 videofactory the signal at the ADC input 11, with which the digital signal is input to the receiving part 12. In the beginning with the third switch 20, the output of the ADC 11 is connected to the input of the EVA unit 16, in which the computation of the mutual correlation function of the received signal and the expected signal synchronization. Once the FF in the EVA unit 16 exceeds a certain threshold, the output of block 16 will appear different from zero signal which resets the counter 23, which, in turn, generates a reset pulse supplied to the second input of the block selecting maximum of 22. Then during the time interval equal to the duration OCM symbol (Ng+N) clock cycles of the sampling frequency at the first input of the block selecting maximum 22 via the fourth switch 21 receives the ACF samples from the block AAA 15 and to the second input of the block selecting maximum of 22 signals the status of the counter 23, (which changes with frequency counts MCFs). If the next count MCFs than the previous, then registers the block 22 is keeping this reference and its serial number. Alternately, if the count MCFs does not exceed the previously stored, no records are made. When the counter counts (Ng+N) clock cycles, the registers in the block 22 will be maximum on the interval symbol OCM value FF and the number of ticks corresponding to the delay of the peak MCFs relative to the first threshold. The number of delay on command from the counter 23 is rewritten in the second memory block 19.
After this procedure the choice of maximum repeated on subsequent symbols of the preamble. After processing all of the symbols of the preamble in the second memory block 19 going non delays highs MCFs for all symbols of the preamble. These numbers are given in the unit of calculation of time intervals 24. To this point in time in the first memory block 18 contains an array of samples of the received signal, recorded during a time interval slightly longer than the duration of all of the symbols of the preamble. Based on the numbers received from the second memory block 19, block calculation of time intervals 24 calculation of indices to read from the first memory block 18 arrays of samples of the received signal for subsequent characters OCM. In block 24 is determined by the average of all symbols of the preamble delay fronts OCM of characters that is used when decoding the subsequent group of characters OCM, the number of which is equal to the number of symbols in the preamble.
After determining the average delay si the oxen preamble command from block 24, the third switch 20 connects the output of the ADC 11 to the input of the block AAA 15, and further, the synchronization is carried out according to the peaks of the autocorrelation function. Moreover, as in the processing of symbols of the preamble are determined delay highs ACF for several consecutive symbols OCM, and the average delay value is used to calculate the index of the read signal samples from the first memory unit 18 in the demodulator OCM 13. In the demodulator OCM 13 performs the FFT and the necessary conversion of the signal format (a series-parallel and parallel-to-serial), resulting in a received signal from a time representation is converted to the frequency domain. The samples of the signal from the output of the demodulator OCM 13 is fed to the input of the demodulator Dcvmn 14, where there are bits of coded information, which are output from the receiving part 12 receives the second input of control unit connection 1, which are decoded and fed to the output device.
After determining the average value of the delay to the last character frame of the third switch 20 again connects the output of the ADC 11 to the input of the EVA unit 16 for detecting a preamble of the next frame.
The average value of the delay OCM characters number of consecutive characters can improve the accuracy of synchronization and, therefore, reduce the probability of error when receiving information. The number of characters within which the proposed device which performs about average delay values, is determined by the parameters of the channel.
Figure 3 presents the probability of errors in the reception of signals OCM without averaging the delay and when averaged over four consecutive symbols. The graphs presented in figure 3, obtained by simulation of signal transmission OCM in the channel KB range for standard requirements of the International consultative Committee for radio (CCIR) channel parameters:
Effect Good channel Moderate channel Bad channel
The time delay 0.5 MS 1 MS 1 MS
The speed of the fading 0.1 Hz 0.5 Hz 2 Hz
Curves (1) and (2) figure 3 shows the probability of error when the reception signal OCM in a bad channel, respectively, without averaging the delay of the maximum of the correlation function and averaged over the four characters.
Curves (3) and (4) figure 3 shows the probability of error when the reception signal OCM in the temperate channel respectively, without averaging the delay of the maximum of the correlation function and averaged over the four characters.
Curves (5) and (6) figure 3 shows the probability of error when the reception signal OCM in good channel, respectively, without averaging the backside of the LCD of the maximum of the correlation function and averaged over the four characters.
Comparison of the graphs shows that the average delay under other equal conditions allow 1-2 order to reduce the probability of error signals OCM.
The block select maximum 22 can be implemented according to the block diagram presented in figure 4, where we have introduced the following notation:
22.1 - first comparator;
22.2 - shaper threshold;
22.3 the first register;
22.4 - second comparator;
22.5 - second register.
The block select maximum 22 contains connected in series shaper threshold 22.2, which input is the first input of the block select max 22, and the first comparator 22.1 whose output is the first output of the block select maximum 22; sequentially connected first register 22.3 and the second comparator 22.4, the first inputs of which are connected to each other and with the input of the shaper threshold 22.2. In addition, the second register contains 22.5, the first input of which is the third input of the block select max 22, and the output of the second output block select maximum of 22. Thus the output of the second comparator 22.4 connected to third inputs of the second register and 22.5 of the first register 22.3, the second output of which is connected with the second input of the first comparator 22.1; the second input of the block selecting maximum 22 is connected with the second inputs of the first 22.3 register and a second register 22.5.
Unit selection the maximum is 22 operates as follows.
From the block 23 on the second inputs of the first 22.3 register and a second register 22.5 receives a reset pulse, which sets the registers to the zero state. From block 21 to the input of the shaper threshold 22.2 and the first inputs of the first register and 22.3 of the second comparator 22.4 received the samples of intercorrelation functions (MCFs). The second comparator 22.4 compares the number corresponding to the next reference MCFs with state of the first register 22.3. Because after reset the state of the first register 22.3 zero, and counts MCFs usually greater than or equal to zero, then the second comparator 22.4 triggered, and the output signal of the second comparator 22.4 is a write command in the first 22.3 and 22.5 second registers. While in the first register 22.3 records a value of the reference MCFs, and the second register 22.5 recorded the number of block 23, is equal to the number of delay mentioned reference MCFs. On the next cycle of operation of the second comparator 22.4 compares the next countdown MCFs with non-zero status block 22.3. If the value of the newly received reference exceeds the amount recorded in the first register 22.3, the second comparator 22.4 again triggered, and a new counting MCFs is written in the first register 22.3, and the corresponding state of the block 23 is written into the second register 22.5. If the value of the newly received reference does not exceed the number of register 22.3, the second comparator 224 is not working, and the state of the first 22.3 and 22.5 second registers are not changed. This process continues for the duration OCM character. At the same time there is a formation threshold shaper threshold 22.2, that is, is the summation of all incoming samples MCFs and multiplying the sum by a certain factor. The result of the calculation of the threshold is supplied to the first input of the first switch 22.1. After receipt of counts EKB corresponding to the duration of one OCM character, case-sensitive 22.3 compared with the threshold of block 22.2. The result of comparison with a threshold is passed to the block 24, and the number of register 22.5 (latency) is recorded in block 19.
The counter 23 can be implemented according to the block diagram presented on figure 5, where we have introduced the following notation:
23.1 - scheme, OR;
23.2 - delay element;
23.3 - shaper reset pulse;
23.4 - pulse counter;
23.5 - first decoder;
23.6 - second decoder;
23.7 - clock.
The counter 23 includes serially connected delay element and 23.2 scheme OR 23.1, the output of which is a second output of the counter 23; connected in series pulse shaper reset 23.3 and pulse counter 23.4, the first group of outputs which the bus is connected with a group of inputs of the first decoder 23.5, the output of which are the two which is the first output of the counter 23, connected to the input of the delay element 23.2; clock 23.7, the output of which is connected with the second clock input of the counter pulses 23.4, single output which is the third output of the counter 23. The second group of outputs of the pulse counter 23.4 bus connected to the group of inputs of the second decoder 23.6, the output of which is connected with the second input of the pulse shaper reset 23.3, the first input which is the input of the counter 23; in addition, the output of pulse shaper reset 23.3 connected with the second input circuit OR.
The counter 23 is as follows.
On the second clock input of the counter pulses 23.4 pulses from the output of the clock 23.7. At the first input of the pulse shaper reset 23.3 signal mutual correlation detection block 16, resulting in a reset pulse to the pulse counter 23.4. This same pulse through the circuit OR 23.1 is supplied to the second input unit 22, and the pulse shaper reset 23.3 blocked for the duration of the frame that is counted by the pulse counter 23.4. Unlock pulse shaper reset 23.3 occurs on a signal from the second decoder 23.6.
The first decoder 23.5 configured on the number corresponding to the number of cycles of the sampling frequency on the duration of one OCM character, and as soon as the gr the PUF outputs of the first decoder 23.5 with the first group of outputs of the pulse counter 23.4 comes the code for this number, the first decoder 23.5 triggered, and the output of the first decoder 23.5 given the signal, which serves as the write command in the block 19. The same signal through the delay element and 23.2 scheme OR 23.1 is supplied to the second input unit 22 to reset the registers. The second decoder 23.6 configured on the number corresponding to the number of cycles of the sampling frequency in the whole frame of the received signal, and as soon as the group of outputs of the second decoder 23.6 from the second group of outputs of the pulse counter 23.4 comes the code of this number, the second decoder 23.6 triggered, and its output signal unlocks the pulse shaper reset 23.3, after which the block 23 is ready for operation in the next frame.
The unit of calculation of time intervals 24 can be implemented in the form of FPGAs [6], the algorithm of functioning of which is presented on Fig.6.
Work unit calculating time intervals 24 begins with a zero status block 24.1 (I=0). From block 22 to block 24.2 signal exceeding or not exceeding the threshold variable (R), which is compared with the threshold value in block 24.3. If the threshold is not exceeded, then block 24.3 along the line of "no" to proceed to the block 24.1, and if the threshold is exceeded, then block 19 block 24.4 enter a number that is the index of the maximum correlation values (the maximum duration of a symbol). This number indicates how many clock cycles of the sampling frequency shifted fronts characters of the input signal in relation to the periods of the counter 23 (see 2). But because the time delay periods of the counter 23 does not coincide with the delays of the received symbol signal, it requires the calculation of a delay closest to the front of the symbol relative to the start time of the counter. This calculation is performed in block 24.5 (see Fig.6):
OUT=OUT[I-1]+X+(D-I/L+1)·L,
where X is the input signal block;
D is the number of symbols in the preamble (or group);
I - the number of the quantum sampling;
L - the number of ticks for the duration of one symbol;
Moreover, this procedure should be repeated for D·L characters, so after calculating the delay unit 24.5 in block 24.6 test conditions
I<D·L
While the number of cycles of sampling did not reach significance D·L, on the line "Yes" to proceed to the unit 24.1. Obtaining D·L cycles along the line of "no" to proceed to the next block 24.7, which by the operation X/D calculates the average value of D delay values.
In the next block 24.8 using found average delay values are calculated indices read:
OUT=X+N·L,
where N=1, ..., (D-1).
The indexes are read using the block 24.9 issued in unit 18 to control the reading of arrays of signal samples corresponding to D consecutive characters.
The process must be continued until the arrival of the next preamble, which is transmitted at the beginning of each frame is. Each frame of the signal contains the number of ticks
K·D·L,
where K - number of groups of symbols in the frame.
In block 24.10 compares the number of counter 24.1 with the frame length. If the number of cycles of sampling is less than K·D·L, on the line "Yes" to proceed to the unit 24.1. If the block 24.1 accumulated number of cycles of sampling corresponding to the length of the frame signal on the line "no" to proceed to the next block 24.11 forming the control signal for the block 20.
When receiving the control signal, the third switch 20 switches its input to the input unit AAA 15 (see figure 2).
The implementation of the remaining blocks is not straightforward, as they are widely published in the technical literature [7].
Thus, the use of the proposed technical solutions can significantly improve the accuracy of the synchronization signals in the radio equipment with an orthogonal frequency multiplexing, which, in turn, reduces the likelihood of errors in the reception of these signals even in such difficult conditions of distribution channels KB range.
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3. .Witrisal et al., "Experimental Study and Comparison of OFDM Transmission Techniques," 5th international OFDM-Workshop in Hamburg, Sept. 2000. (Critical and other "Experimental study and comparison of transfer methods OCM").
4. S. Johansson et al., "An OFDM Timing Synchronization ASIC", IEEE, No. 9, 2000. (Jonson "FPGA timing OCM").
5. Varakin LE "communication Systems with noise-like signals" - M.: Radio and communication, 1985. - 384 C., Il.
6. "Xilinx ISE 6 Software Manuals", www.xilinx.com.support.xilinx.com
(Guidelines for software products by Xilinx).
7. Mmed "200 favorite electronics circuits", translation from English. edited by Itzhaki AS, Moscow, Mir, 1980
Radio equipment with orthogonal frequency multiplexing, containing connected in series control unit connection, the first input which is the input of the transmitting part, digital to analog Converter, a second switch, analog-to-digital Converter and the receiving part, the output of which is connected to a second input of control unit connection, the second output which is the output device; an antenna through a high frequency into which the needle is connected with the second input is the output of the second switch; moreover, the transmitting part contains connected in series modulator differential quadrature phase manipulation, the input of which is the input of the transmitting part, the first switch and the modulator orthogonal frequency multiplexing, the output of which is the output of the transmitting part, and the shaper of the synchronization signal, the output of which is connected with the second input of the first switch; receiving portion comprises a control unit, which switches the second switch unit of the autocorrelation detection, block intercorrelation detection and connected in series demodulator orthogonal frequency multiplexing and demodulator differential quadrature phase manipulation, the output of which is the output of the receiving part, wherein the receiving part is entered the first block memory, the third switch, connected in series, the fourth switch, the block select maximum and the unit of calculation of time intervals, sequentially the United counter and the second memory block; the first output of the third switch through the power of the autocorrelation detection connected to the first input of the fourth switch, the second output of the third switch through the block intercorrelation detection connected with the second I is the home of the fourth switch and the meter inlet, the second and third outputs of which are connected respectively with the second and third inputs of the block select maximum, the second output of which is connected with the second input of the second memory block, the output of which is connected with the second input of the block of calculation of time intervals, the second output of which is connected with the second, the controlling input of the third switch and the first output unit for calculation of time intervals connected with the second, the controlling input of the first memory block, the output of which is connected to the input of the demodulator orthogonal frequency multiplexing; the first input of the first memory block connected to the first input of the third switch is an input receiving part.