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Timestamp: 2020-02-19 10:19:44
Document Index: 3902029

Matched Legal Cases: ['art 106', 'art 106', 'art 106', 'art 106', 'art 106', 'art 110', 'art 110', 'art 110', 'art 110', 'art 110', 'art 110', 'art 110', 'art 110', 'art 110', 'art 110']

MEMORY DEVICES, STYLUS-SHAPED STRUCTURES, ELECTRONIC APPARATUSES, AND METHODS FOR FABRICATING THE SAME - INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
United States Patent Application 20090191367
Chen, Wei-su (Hsinchu, TW)
12/205804
250/492.3, 257/4, 257/E29.323, 257/E45.002, 313/483, 355/67, 360/122, 385/132, 438/102, 216/41
B29D22/00; B32B1/08; G02B6/10; G03B27/54; G11B5/187; G21K5/00; H01J1/62; H01L45/00
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20090110930 MONO-DISPERSIVE SPHERICAL INDIUM OXIDE-BASED PARTICLES AND METHOD FOR PRODUCING THE SAME April, 2009 Wei et al.
1. A hollow stylus-shaped structure, comprising: a hollow column spacer formed over a base layer; and a hollow cone spacer stacked over the hollow column spacer; wherein the hollow cone spacer, the hollow column spacer, and the base layer form a space, and sidewalls of the hollow cone spacer and the hollow column spacer are made of silicon-containing organic or inorganic materials.
7. A method for fabricating a hollow stylus-shaped structure, comprising: providing a base layer; blanketly forming a resist layer over the base layer, wherein the resist layer comprises no silicon; defining the resist layer and forming an opening in the resist layer, wherein the opening exposes a portion of the base layer and a sidewall of the resist layer; conformably forming a spacer layer over a top surface of the resist layer, the sidewall of the resist layer exposed by the opening, and the part of the base layer exposed by the opening, wherein the spacer layer comprises silicon; performing a thermal process, reflowing the resist layer and sealing the opening, dividing the spacer layer into a first portion and a second portion, wherein the first part of the spacer layer covers the top surface of the resist layer, and the second part of the resist layer is embedded in the resist layer and defines a space in combination with the base layer; and sequentially removing the first part of the spacer layer and the first resist layer, exposing the space defined by the second part of the spacer layer in combination with the base layer, wherein the second part of the spacer layer comprises a hollow column spacer and a hollow cone spacer stacked thereof and has a hollow stylus-shaped cross section.
8. The method as claimed in claim 7, wherein the hollow column spacer has a fixed diameter of about 300˜2000 Å.
10. The method as claimed in claim 7, wherein the hollow column spacer has a first height and the hollow cone spacer has a second height, and the first and second heights have a ratio of about 1:1˜4:1.
12. The method as claimed in claim 7, wherein the thermal process is performed at a temperature between 140˜220° C.
13. The method as claimed in claim 7, wherein the spacer layer is formed by a spin coating method under 2000˜6000 rpm.
14. The method as claimed in claim 7, wherein the first part of the spacer layer is removed by a dry etching process using a plasma comprising C2F6.
15. The method as claimed in claim 7, wherein the first resist layer is removed by a dry etching process using a plasma comprising O2.
16. A phase change memory (PCM) device, comprising: a hollow stylus-shaped structure as claimed in claim 1, wherein the base layer is a first conductive layer; a second conductive layer conformably formed over a surface of the hollow stylus-shaped structure and portions of the first conductive layer adjacent to the hollow stylus-shaped structure; a first dielectric layer partially covering the second conductive layer, exposing the second conductive layer over a tip portion of the hollow cone spacer of the hollow stylus-shaped structure; a phase change material layer formed over the first dielectric layer, contacting with the second conductive layer formed over the tip portion of the hollow cone spacer of the hollow stylus-shaped structure; and a third conductive layer formed over the phase change material layer.
19. The PCM device as claimed in claim 16, wherein the second conductive layer over the tip portion of the hollow cone spacer of the hollow stylus-shaped structure has a thickness of about 5˜100 nanometer.
21. A method for fabricating a phase change memory (PCM) device, comprising: providing a plurality of the hollow stylus-shaped structures as claimed in claim 1, wherein the hollow stylus-shaped structures share a base layer and the base layer is a first conductive layer; conformably forming a second conductive layer to cover the hollow stylus-shaped structures and the first conductive layer; forming a first dielectric layer to cover the second conductive layer, leaving a substantially planar surface; etching the first dielectric layer and partially exposing the second conductive layer covering a tip portion of the cone spacer of the hollow stylus-shaped structures; forming a phase change material layer over the first dielectric layer, covering the second conductive layer formed over the tip portion of the hollow cone spacer of the hollow stylus-shaped structures; forming an opening in the phase change material layer, the first dielectric layer, and the second conductive layer between the hollow stylus-shaped structures, and forming a plurality of memory cell structures, wherein the opening partially exposes a part of the first conductive layer, and the memory cell structures respectively comprise: a patterned second conductive layer conformably formed over a surface of the hollow stylus-shaped structure and parts of the first conductive layer adjacent to the hollow stylus-shaped structure; a patterned first dielectric layer partially covering the patterned second conductive layer, exposing the second conductive layer covering the tip portion of the hollow cone spacer of the hollow stylus-shaped structure; and a patterned phase change material layer formed over the first dielectric layer, contacting the second conductive layer covering the tip portion of the hollow cone spacer of the hollow stylus-shaped structure; forming a second dielectric layer over the patterned phase change material layer, filling the opening; forming a plurality of via holes in the second dielectric layer, respectively exposing a part of the patterned phase change material layer of the memory cell structures; and forming a third conductive layer over the second dielectric layer, respectively filling one of the via holes and covering the exposed part of the patterned phase change material layer.
23. The method as claimed in claim 21, wherein the second conductive layer covering the tip portion of the hollow cone spacer of the hollow stylus-shaped structure exposed by the first dielectric layer has a top view diameter of about 5˜100 nanometers.
24. The method as claimed in claim 21, wherein the opening formed between the memory cell structures have a pitch of about 200˜5000 Å.
25. A magnetic random access memory (MRAM) device, comprising: a hollow stylus-shaped structure as claimed in claim 1, wherein the base layer is a first conductive layer; a second conductive layer is conformably formed over a surface of the hollow stylus-shaped structure and parts of the first conductive layer adjacent to the hollow stylus-shaped structure; a first dielectric layer partially covers the conductive layer, exposing the second conductive layer covering a tip portion of the hollow cone spacer of the hollow stylus-shaped structure; a stacked structure formed over the first dielectric layer comprises a free layer, a spacer layer, and a pinned layer sequentially stacked over the first dielectric layer, wherein the free layer covers the second conductive layer over the tip portion of the hollow cone spacer of the hollow stylus-shaped structure; and a third conductive layer formed over the stacked structure.
26. A resistive random access memory (RRAM) device, comprising: a hollow stylus-shaped structure as claimed in claim 1, wherein the base layer is a first conductive layer; a second conductive layer conformably formed over a surface of the hollow stylus-shaped structure and parts of the first conductive layer adjacent to the hollow stylus-shaped structure; a first dielectric layer partially covering the conductive layer, exposing the second conductive layer covering a tip portion of the hollow cone spacer of the hollow stylus-shaped structure; a metal oxide layer formed over the first dielectric layer, wherein the metal oxide layer covers the second conductive layer over the tip portion of the hollow cone spacer of the hollow stylus-shaped structure; and a third conductive layer formed over the stacked structure.
27. A filed emission display (FED) device, comprising: a plurality of hollow stylus-shaped structures as claimed in claim 1, wherein the hollow stylus-shaped structures shares a base layer and the base layer is a cathode layer formed over a first substrate; a conductive layer conformably formed over a surface of the hollow stylus-shaped structures and the cathode layer, wherein the conductive layer formed over the hollow stylus-shaped structures are electrically isolated; a second substrate with an anode layer thereon oppositely disposed to the first substrate; and a plurality of fluorescence layers disposed over the anode layer, substantially aligning to one of the hollow stylus-shaped structures covered by the conductive layer.
28. A multiple-electrobeam direct writing lithography apparatus, comprising: a plurality of hollow stylus-shaped structures as claimed in claim 1, wherein the hollow stylus-shaped structures shares a base layer and the base layer is a semiconductor layer formed over a support substrate; and a conductive layer conformably formed over a surface of the hollow stylus-shaped structures and the semiconductor layer, wherein the conductive layer formed over the hollow stylus-shaped structures and the semiconductor layer are electrically isolated.
29. A high density magnetic storage device, comprising: a probe layer; a cantilever connected with the probe layer; a hollow stylus-shaped structure as claimed in claim 1 formed over an end of the cantilever, wherein the base layer is the cantilever; and a conductive layer conformably covering a surface of the cantilever and the hollow stylus-shaped structure, wherein the hollow stylus-shaped structure covered by the conductive layer acts as a writing component.
30. A microscope apparatus, comprising: a Z-axis direction positioning sensor; a cantilever connected with the Z-axis direction positioning sensor; a hollow stylus-shaped structure as claimed in claim 1 formed over an end of the cantilever, wherein the base layer is the cantilever; a layer conformably covering a surface of the cantilever and the hollow stylus-shaped structure, wherein the layer comprises a material selected from the group consisting of SiOx, SiNx, and tungsten; an X-Y-axis direction positioning sensor; and a substrate disposed over the X-Y-axis direction positioning sensor, wherein the hollow stylus-shaped structure covered by the layer acts as a probe for measuring a surface profile of a sample disposed over the substrate.
31. A lithography apparatus, comprising: a Z-axis direction positioning sensor; a cantilever connected with the Z-axis direction positioning sensor; a hollow stylus-shaped structure as claimed in claim 1 formed over an end of the cantilever, wherein the base layer is the cantilever; a layer conformably covering a surface of the cantilever and the hollow stylus-shaped structure, wherein the layer comprises a material selected from the group consisting of W/ZrOx, W, LaB6, Pt, Au, carbon, and carbon nanotube (CNT); an X-Y-axis direction positioning sensor; a substrate disposed over the X-Y-axis direction positioning sensor, having a resist layer formed thereon; and a power supply, wherein a positive terminal is connected with the substrate and a negative terminal is connected with the layer; wherein the hollow stylus-shaped structure covered by the resist layer acts as an exposing component to pattern the resist layer.
32. A phase change memory (PCM) device, comprising: a first conductive layer; a plurality of solid pillars formed over the first conductive layer, wherein the solid pillars comprise silicon-containing organic or inorganic materials; a phase change material layer conformably formed over a surface of the solid pillars; a second conductive layer formed over a top surface of the phase change material layer; a first dielectric layer disposed between the solid pillars, covering the first conductive layer and portions of the second conductive layer; and a third conductive layer formed over the first conductive layer and through the first dielectric layer, contacting with the second conductive layer.
34. The PCM device as claimed in claim 32, wherein the phase change material layer has a thickness of about 3˜200 nm.
36. A photonic crystal structure, comprising: a substrate; and a plurality of hollow stylus-shaped structures as claimed in claim 1 formed over the substrate, wherein the hollow stylus-shaped structures are arranged with a substantially same pitch therebetween and sidewalls of the hollow stylus-shaped structures are composed of silicon-containing organic or inorganic materials.
38. The photonic crystal structure as claimed in claim 36, wherein a pitch between the hollow stylus-shaped structures is about 1˜5 times that of a diameter of a column portion of the hollow stylus-shaped structures.
In FIG. 3, an electron beam 104 is provided to directly expose a portion of the resist layer 102, thereby forming a plurality of exposed portions 102a in the resist layer 102. It's noted that while the resist layer 102 adopts resist materials of other exposure types, the resist layer 102 can be exposed in other methods such as a DUV exposed method and is not limited to the electro beam method.
In FIG. 4, a development process (not shown) is performed to remove the exposed portions 102a in the resist layer 102, thereby forming a plurality of opening OPI in the resist layer 102. Each of the opening OPI exposes a part of the base layer 100. Next, a spacer layer 106 is spin coated over a surface of the resist layer 102, and sidewalls of the resist layer 102 exposed by the opening OPI under a rotational speed of about 2000 rpm. Herein, the spacer layer 106 also conformably covers a surface of the base layer 100 exposed by the openings OPI. The spacer layer 106 may comprise diluted silicon-containing material such as silicon-containing organic or inorganic materials. In this embodiment, the diluted silicon-containing material of the spacer layer 106 comprises hydrogen silsesquixane (HSQ) diluted by methyl isobutyl ketone (MIBK). Herein, a ratio of MIBK and HSQ for forming the spacer layer 106 is preferably higher than 3:1 to benefit formation of the spacer layer 106. The spacer layer 106 is formed with a thickness not more than 25 nm.
In FIG. 5, the structure illustrated in FIG. 4 is then subjected to a thermal process 108 performed under a temperature of about 140˜200° C. to reflow the resist layer 102 and seal the opening OPI formed in the resist layer 102. As shown in FIG. 5, the spacer layer 106 is divided into a first part 106a formed over the surface of the resist layer 102 and a second part 106b embedded in the resist layer 102 after the thermal process 108. Herein the previously formed openings OPI are sealed and become space G with a substantially stylus-shaped configuration. The surface of the space G is covered and sealed by the second part 106b of the spacer layer 106.
In FIG. 6, a dry etching process (not shown) is next performed to remove the first part 106a of the spacer layer 106 by using a plasma comprising C2F6 and expose the resist layer 102. Next, another dry etching process (not shown) is performed to entirely remove the resist layer 102 by using a plasma comprising O2 and leave a plurality of hollow stylus-shaped structures 110 over the base layer 100.
As shown in FIG. 6, the hollow stylus-shaped structures 110 are formed by encapsulating the spaces G by the second part 106b of the spacer layer 106 and are substantially defined into two parts, including a first part 110b with a substantially hollow column configuration and a second part 110a with a substantially cone configuration stacked over the first part 110b. The first part 110b is formed with a fixed diameter D1 and has a substantially circular configuration from a top view (not shown). The second part 110a is formed with a varied non-fixed diameter, reduced from a bottom to a top thereof and has a substantially circular configuration from a top view (not shown). The hollow stylus-shaped structures 110 illustrated in FIG. 6 are arranged as a configuration with same pitches therebetween and the diameter D1 of the first part 110b thereof may be 300˜2000 Å and a tip portion at an upper portion of the second part 110a thereof may have a minimum diameter less than 100 Å. A height H2 of the first part 110b of the hollow stylus-shaped structures 110 and a height H1 of the second part 110a of the hollow stylus-shaped structures 110 may have a ratio of about 1:1˜4:1 therebetween.
In FIG. 8, a dielectric layer 204 is formed, having a thickness of about 3000˜4000 Å, to blanketly cover the conductive layer 202 and the hollow stylus-shaped structures 110, thereby leaving a substantially planar surface. The dielectric layer 204 may comprise materials such as undiluted HSQ and can be formed by, for example, a spin coating process. The dielectric layer 204 formed by a spin coating process, is preferably formed under a rotational speed of about 2000˜6000 rpm, and more preferably under a rotational speed of about 2000˜3000 rpm. Next, an etching process (not shown) is performed to partially remove the dielectric layer 204 and partially expose the portion of the second conductive layer 202 covering each second part 110b of the hollow stylus-shaped structures 110. The above etching process can be, for example, a wet etching process using highly diluted HF solution (with an HF:water dilution ratio of more than 1:100). At this time, the portion of the conductive layer 202 exposed by the dielectric layer is formed with a diameter D2 which can be controlled by the etching time or the concentration of the HF solution performed in the above etching process. The diameter D2 is preferably about 5˜80 nm to reduce a contact area between the conductive layer 202 and sequentially formed components (not shown). Herein, an optional dielectric oxide layer (not shown) can be provided over the conductive layer 202 and the hollow stylus-shaped structures 110 prior to formation of the dielectric layer 204 to prevent collapse of the hollow stylus-shaped structures 110 during formation of the dielectric layer 204. Methods for forming the above dielectric oxide layer can be, for example, a plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDP CVD) method. In addition, the above etching process can be a dry etching process with a relatively high etching rate for removing a relatively thick part of the dielectric layer 204 (leaving a top surface of the dielectric layer 204 of about 30˜50 nm to the conductive layer 202 at a tip portion of the hollow stylus-shaped structures 110) in combination with a sequential wet etching process using HF solution with a relatively low etching rate for removing a relatively thin part of the dielectric 204 till the conductive 202 at the tip portion of the hollow stylus-shaped structures 110 is exposed. In addition, the above etching process can be a repeated dry etching process with a relatively low etching rate (˜10 nm per time) for cyclic removing a relatively thick part of the dielectric layer 204 till the conductive 202 at the tip portion of the hollow stylus-shaped structures 110 is exposed. For example, the repeated times for dry etching dielectric layer 204 of 100 nm is 10.
In the PCM device as shown in FIG. 11, the conductive layer (e.g. the conductive layer 202a) covering the tip portion of the hollow stylus-shaped structures in each of the PCM cell structure functions as a heating electrode and a contact area between the heating electrode and the phase change material layer can be thus reduced, thereby lowering operation currents and maintaining current density of the PCM device. In addition, since the stylus-shaped structures under the conductive layer 202a are formed with a hollow interior and the interlayer dielectric layer 208 adjacent thereto is formed with air gaps A therein, the phase change material layer 206 is thereby provided with heat insulation during heating thereof, improving heating efficiency of the heating electrode, and preventing heat diffusion within the PCM cell structures.
In FIG. 19, an electron beam 1005 is provided to directly expose a portion of the resist layer 1002, thereby forming a plurality of exposed portions 1002a in the resist layer 1002. It's noted that while the resist layer 1002 adopts resist materials of other exposure types, the resist layer 1002 can be exposed in other methods such as a DUV exposed method and is not limited to the electro beam 1005 method.
In FIG. 20, a development process (not shown) is performed to remove the exposed portions 1002a in the resist layer 1002, thereby forming a plurality of opening OP3 in the resist layer 102. Each of the opening OP3 exposes a part of the conductive layer 1000. Herein, the openings OP3 are formed with an aspect ration of about 1:1˜10:1. Next, a spacer layer 1004 is spin coated over a surface of the resist layer 1002 and fills the openings OP3 under a rotational speed of about 2000˜3000 rpm. Herein, the spacer layer 1004 substantially protrudes over a top surface of the resist layer 1002. Next, a dry or wet etching process (not shown) is performed to remove the portion of the spacer layer over the top surface of the resist layer 1002, thereby leaving a spacer layer 1004 in each of the openings OP3. The spacer layer 1004 has a top surface substantially the same as that of the resist layer 1002.
In FIG. 25, a photolithography and an etching process (both not shown) are performed to partially remove the conductive layer 1118 and leave a plurality of conductive elements 1118a over the PCM cell structures, respectively contacting the phase change material layer 1006 through the conductive layers 1112 and 1110.
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