Source: http://www.google.com/patents/US7087962?dq=7,453,150
Timestamp: 2016-08-29 06:24:53
Document Index: 646958568

Matched Legal Cases: ['art 28', 'art 7', 'art 9', 'art 10', 'art 11', 'art 12', 'art 7', 'art 9']

Patent US7087962 - Method for forming a MOS transistor having lightly dopped drain regions and ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA MOS transistor having a LDD structure is described. In accordance with the present invention a MOS transistor includes a low impurity concentration region formed in a semiconductor film between an end of a gate electrode and a source or drain. The transistor includes an insulating film extending beyond...http://www.google.com/patents/US7087962?utm_source=gb-gplus-sharePatent US7087962 - Method for forming a MOS transistor having lightly dopped drain regions and structure thereofAdvanced Patent SearchPublication numberUS7087962 B1Publication typeGrantApplication numberUS 08/433,561Publication dateAug 8, 2006Filing dateMay 3, 1995Priority dateDec 24, 1991Fee statusLapsedAlso published asUS5292675, US20060267097Publication number08433561, 433561, US 7087962 B1, US 7087962B1, US-B1-7087962, US7087962 B1, US7087962B1InventorsMitsufumi CodamaOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (20), Referenced by (10), Classifications (28), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod for forming a MOS transistor having lightly dopped drain regions and structure thereof
US 7087962 B1Abstract
A MOS transistor having a LDD structure is described. In accordance with the present invention a MOS transistor includes a low impurity concentration region formed in a semiconductor film between an end of a gate electrode and a source or drain. The transistor includes an insulating film extending beyond the gate electrode in the direction of the source and drain, the insulating film having a thicker portion over the channel region of the semiconductor film and a thinner portion over the source and drain regions of the semiconductor film, such that LDD regions can be formed by utilizing the thickness difference between the thick portion of the insulating film and the thin portion of the insulating.
1. An active matrix display device including a thin film transistor for switching a pixel of said display device, said active matrix display device comprising:
a substrate having an insulating surface; a semiconductor layer formed on said insulating surface; an insulating film including a gate insulator therein formed on said semiconductor layer, said insulating film having a thicker portion located on and completely covering a channel region of said semiconductor layer, and thinner portions located on source and drain regions of said semiconductor layer, wherein said source and drain regions extend throughout the thickness of the semiconductor layer, a gate electrode formed on the thicker portion; an interlayer insulating film formed on said insulating film and said gate electrode; and at least one electrode formed over said interlayer insulating film for contacting at least one of said source and drain regions, wherein first and second LDD regions are formed in said semiconductor layer between the channel region and the source region and between the channel region and the drain region below extending parts of the thicker portion, said extending parts of the thicker portion extending beyond the edges of the gate electrode, wherein a concentration of an impurity contained in said source and drain regions monotonically decreases in a thickness direction of the semiconductor layer at least partly toward said insulating surface, wherein said extending parts of the thicker portion and said thinner portions have first surfaces being in contact with said semiconductor layer and second surfaces being in contact with said interlayer insulating film, wherein said at least one electrode extends through said interlayer insulating film and said thinner portion of said insulating film. 2. A device according to claim 1 wherein said impurity comprises at least one of phosphorus and boron.
3. A device according to claim 2 wherein said first and second LDD regions contain said impurity at a concentration lower than said source and drain regions.
4. A device according to claim 2 wherein said source and drain regions become n-type when said impurity is phosphorous and said source and drain regions become p-type when said impurity is boron.
5. A device according to claim 1 wherein said gate electrode comprises a doped polysilicon.
6. A device according to claim 1 wherein said insulating film comprises silicon oxide.
7. A device according to claim 1 wherein edges of the thicker portion of the insulating film are substantially aligned with sides of the source and drain regions adjacent to the LDD regions.
8. A device according to claim 7 wherein edges of the gate electrode are substantially aligned with sides of the LDD regions opposite the source and drain regions.
9. A device according to claim 1 wherein said semiconductor layer is a non-single crystalline semiconductor layer.
10. A device according to claim 1 wherein said interlayer insulating film covers whole surfaces of said extending parts of the thicker portion and said thinner portions.
11. A device according to claim 1 wherein said source and drain regions are formed throughout a thickness of the semiconductor layer so that a bottom surface of each of said source and drain regions contacts the insulating surface.
12. A device according to claim 1, wherein said insulating film has substantially two thicknesses only.
13. A device according to claim 1, wherein said thicker portion of said insulating film is in contact with said gate electrode at substantially only a bottom portion thereof.
14. A device according to claim 1, wherein said insulating film comprises a laminated multilayer structure with a plurality of insulating materials each having a different etching rate, respectively.
15. A device according to claim 1, wherein said insulating film and said interlayer insulating film comprise different material, respectively.
16. A device according to claim 1 wherein said thicker portion of said insulating film is 1000 Å thick.
17. A device according to claim 1 wherein said thinner portions of said insulating film are 300 Å thick.
18. A device according to claim 1 wherein a concentration of an impurity doped in said source and drain regions is 1�1021atoms cm−1.
19. A device according to claim 1 wherein a concentration of an impurity doped in said first and second LDD regions is 6�1017atoms cm−1.
20. An active matrix display device including a thin film transistor for switching a pixel of said display device, said active matrix display device comprising:
a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer including at least a channel region and source and drain regions; an insulating film including a gate insulator therein formed on said semiconductor layer and having a thicker portion and thinner portions, wherein said source and drain regions are covered by the thinner portions of the insulating film and introduced with a dopant impurity through said insulating film at a first concentration, and wherein said channel region is covered by the thicker portion of said insulating film, wherein said source and drain regions extend throughout the thickness of the semiconductor layer; first and second LDD regions formed between the channel region and the source region and between the channel region and the drain region, wherein said first and second LDD regions are introduced with said dopant impurity through said insulating film, wherein a width of said first LDD region is substantially the same as a width of said second LDD region; a gate electrode formed on said thicker portion of the insulating film; an interlayer insulating film formed on said gate electrode and said insulating film; at least one electrode formed over said interlayer insulating film for contacting at least one of said source and drain regions, wherein said extending parts of the thicker portion extend beyond edges of said channel region and cover said LDD regions, wherein extending parts of the thicker portion and said thinner portions have first surfaces being in contact with said semiconductor layer and second surfaces being in contact with said interlayer insulating film, wherein said at least one electrode extends through said interlayer insulating film and said thinner portion of said insulating film, and wherein a concentration of the dopant impurity contained in said source and drain regions monotonically decreases in a thickness direction of the semiconductor layer at least partly toward said insulating surface. 21. A device according to claim 20 wherein said dopant impurity is introduced into said LDD regions through said thicker portion of said insulating film which covers said LDD regions at a second concentration which is lower than said first concentration.
22. A device according to claim 20 wherein said semiconductor layer is a non-single crystalline semiconductor layer.
23. A device according to claim 20 wherein said interlayer insulating film covers whole surfaces of said extending parts of the thicker portion and said thinner portions.
24. A device according to claim 20 wherein said source and drain regions are formed throughout a thickness of the semiconductor layer so that a bottom surface of each of said source and drain regions contacts the insulating surface.
25. A device according to claim 20, wherein said insulating film has substantially two thicknesses only.
26. A device according to claim 20, wherein said insulating film comprises a laminated multilayer structure with a plurality of insulating materials each having a different etching rate.
27. A device according to claim 20, wherein said insulating film and said interlayer insulating film comprise different material, respectively.
28. A device according to claim 20 wherein said thicker portion of said insulating film is 1000 Å thick.
29. A device according to claim 20 wherein said thinner portions of said insulating film are 300 Å thick.
30. A device according to claim 20 wherein a concentration of said dopant impurity in said source and drain regions is 1�1021atoms cm−1.
31. A device according to claim 20 wherein a concentration of said dopant impurity in said first and second LDD regions is 6�1017atoms cm−3.
32. An active matrix display device including a thin film transistor, said active matrix display device comprising:
a substrate having an insulating surface; a semiconductor layer formed on said insulating surface; an insulating film including a gate insulator therein formed on said semiconductor layer, said insulating film including: a thicker portion located on and completely covering a channel region of said semiconductor layer, and thinner portions located on source and drain regions of said semiconductor layer, wherein said source and drain regions extend throughout a thickness of the semiconductor layer; a gate electrode formed on the thicker portion of said insulating film; first and second LDD regions formed in said semiconductor layer between the channel region and the source region and between the channel region and the drain region below extending parts of the thicker portion of said insulating film, said extending parts of the thicker portion extending beyond edges of the gate electrode, wherein a width of said first LDD region is substantially the same as a width of said second LDD region; an interlayer insulating film formed on said insulating film and said gate electrode; and at least one electrode formed over said interlayer insulating film for contacting at least one of said source and drain regions, wherein said extending parts of the thicker portion and said thinner portions have first surfaces being in contact with said semiconductor layer and second surfaces being in contact with said interlayer insulating film, wherein said at least one electrode extends through said interlayer insulating film and said thinner portion of said insulating film, and wherein a concentration of an impurity contained in said source and drain regions monotonically decreases in a thickness direction of the semiconductor layer at least partly toward said insulating surface. 33. A device according to claim 32 wherein said semiconductor layer is a non-single crystalline semiconductor layer.
34. A device according to claim 32 wherein said interlayer insulating film covers whole surfaces of said extending parts of the thicker portion and said thinner portions.
35. A device according to claim 32 wherein said source and drain regions are formed throughout a thickness of the semiconductor layer so that a bottom surface of each of said source and drain regions contacts the insulating surface.
36. A device according to claim 32, wherein said insulating film has substantially two thicknesses only.
37. A device according to claim 32, wherein said insulating film comprises a laminated multilayer structure with a plurality of insulating materials each having a different etching rate.
38. A device according to claim 32, wherein said insulating film and said interlayer insulating film comprise different material, respectively.
39. A device according to claim 32 wherein said thicker portion of said insulating film is 1000 Å thick.
40. A device according to claim 32 wherein said thinner portions of said insulating film are 300 Å thick.
41. A device according to claim 32 wherein a concentration of said impurity doped in said source and drain regions is 1�1021atoms cm−1.
42. A device according to claim 32 wherein a concentration of an impurity doped in said first and second LDD regions is 6�1017atoms cm−3.
43. A device according to claim 32, wherein the thin film transistor is used for switching a pixel of a liquid crystal display or a bit of an image sensor.
This application is a Continuation of Ser. No. 08/173,078, filed Dec. 27, 1993, now abandoned; which itself is a division of application Ser. No. 07/990,288, filed Dec. 14, 1992, now U.S. Pat. No. 5,292,675, issued Mar. 8, 1994.
Up to this time, a thin film transistor (hereinafter referred to as TFT) has been used for a liquid crystal display of a small television set and a computer system, an image sensor used for a facsimile machine, and a thermal head. At present, an amorphous silicon TFT is being most popularly developed, on account of its feature that it can be prepared by a comparatively easy method and it is easy to be formed on a large area substrate. The amorphous silicon TFT, however, has a drawback that the mobility of its electron and hole is very small such as in the order of 1 cm2/V�S and0.1 cm2/V�S respectively. This drawback causes an insufficient performance especially in switching speed in order to construct a driving circuit on the same substrate, though it does not pose a big problem in switching of e.g., each one pixel of a liquid crystal display or each bit of an image sensor.
On the other hand, a polycrystal silicon TFT being used in a small type liquid crystal television or an image sensor, has about 10 cm2/V�S or more of both mobilities of electron and hole, and the product actually constructed with the driving circuit has been on sale. This polycrystal silicon TFT usually has a coplanar type structure, namely; the structure that each electrode of gate, source, and drain is all positioned opposite the substrate toward a silicon channel part.
(1) Firstly, a gate silicon oxide film 23 and a silicon film 22 doped with an impurity in a high concentration will be formed on a silicon which is patterned in an island state. Then, a gate electrode and a gate silicon oxide film will be formed by patterning these films. After an impurity is introduced into an island state silicon part (source 21, drain 20), where is not covered with the gate electrode 22, in a low concentration of 1017 to 1019 atoms/cm3, a silicon oxide film 24 will be formed using a film-forming method with a good step-coverage, thereby obtaining the state of FIG. 2(b). At this time, in the side wall of the gate part, silicon oxide film will be accumulated thickly.
(3) Next, using the above prepared silicon oxide film 25 (Spacer for doping) neighboring the gate electrode 22 as a mask, an ion implantation of impurity will be executed in a high, concentration (1020 to 1021 atoms/cm3). After that, source 28 and drain 27 will be completed by activating the impurity, and also LDD part 28 where the impurity is introduced in a low concentration will be completed, under the silicon oxide film 25 nearby the gate electrode 22, thus obtaining the state of FIG. 2(d). In this way LDD structure can be formed. The above (1) to (3) processes, however, will be added in comparison with the case of preparation for the conventional transistor as shown in FIG. 2(a), the result being that it is disadvantageous in the point of yielding and cost.
forming a semiconductor film; forming an insulating film on said semiconductor film; forming a conductive material on said insulating film; patterning said conductive material into an island; removing a portion of said insulating film by etching to leave a portion of said insulating film unremoved under said island and thin a portion of said insulating film outside the unremoved portion of said insulating film; forming a gate electrode by reducing a width of said island by removing a portion of said island by etching; and introducing an impurity into said semiconductor film with said gate electrode as a mask. A gate insulating film is formed on said semiconductor film under said gate electrode. The portion of said insulating film outside the unremoved portion of said insulating film is made thinner than the gate insulating film by said removing step.
Next, an impurity ion will be implanted into the semiconductor film from the upper of this state through the insulating film 7 and 9 by an ion implantation method etc. [FIG. 1(g)]. At this time, by an impurity implantation using a moderate acceleration voltage and a dose corresponding to the film thickness of each gate silicon oxide, an active layer silicon lying under the thin film part 7 of gate silicon oxide will be densely doped with an impurity, and an under portion of the thick part 9 of gate oxide film will be doped up to the concentration suitable for LDD structure, resulting in that each source part 10 or drain part 11 and LDD part 12 will be formed. Moreover, by setting up to a suitable ratio the film-thickness difference between the removed part and remained part of gate silicon oxide film through an etching it is possible to finish the impurity doping process once at the same time to control the concentration of the impurity introduced into the semiconductor film under the thin part 7 thinner than the gate insulating film part 9 and under the removed portion of the gate electrode silicon island.
That is; in case of an ion implantation method which is usually used as a means to introduce an impurity element into a semiconductor film, if the implantation is effected through another film, the implanted concentration in the semiconductor film will change in accordance with the film thickness. This situation is shown in FIG. 4, in which an axis of abscissa represents a thickness of SiO2 film provided on silicon semiconductor, and an axis of ordinate represents a phosphorus concentration on the highest surface of silicon semiconductor. A computer simulation result in case of the ion implantation of phosphorus, employing 5�1015cm−2 of dose and 40 KV of acceleration voltage is indicated in FIG. 4, in which a peak is at 400 Å. The peak position moves according to the change of acceleration voltage.
In accordance with the present invention, LDD structure can be easily realized, by using a concentration difference of impurity to be implanted into a semiconductor film, owing to the film-thickness difference on this semiconductor film. Namely; an impurity implantation will be executed through the gate insulating film, the thickness of which will be provided to be thin in the area where is in contact with the source or drain part, and will be provided to be thicker in the part where is close by the end of gate electrode.
In this way, for example, when the film of source or drain part is 300 Å thick, 1�1021atoms�cm−3 of an impurity concentration will be implanted into a semiconductor film as seen in FIG. 4. On the other hand, when the insulating film in LDD part is 1000 Å thick as is the same with the gate insulating film, 6�1017atoms�cm−3 of an impurity concentration will be implanted into a semiconductor film, as referred to FIG. 4. It is, therefore, possible to implant both high and low concentrations of an impurity into the same semiconductor film at the same time.
The objects, features, and advantages of the present invention will become more apparent, from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:
FIGS. 1(a)-1(g) shows a schematic diagram of the preparing method for MOS transistor having LDD structure according to the present invention.
FIGS. 2(a)-2(d) shows a schematic diagram of the conventional preparing method for MOS transistor having LDD structure, and a schematic diagram of the structure thereof.
FIGS. 3(a)-3(d) shows an application example of MOS transistor according to the present invention.
After a passivation film was formed on a glass substrate 1, an amorphous silicon film 2 was formed in 1000 Å thick by LPCVD method, Plasma CVD method and the like. The film 2 was heated at 600� C. for 48 hrs. to effect a solid-growth of an amorphous silicon layer, which was then patterned to be an island-like by a photo-lithography [FIG. 1(a)]. As a gate insulating film, a silicon oxide film 3 was formed in 1000 Å thick by sputtering method, the process of which was carried out in 100% of oxygen gas. Further, an amorphous silicon film containing 1 to 10�1020cm−3 of phosphorous as a gate electrode was formed by LPCVD or Plasma CVD method etc. A polysilicon film may be formed as the gate electrode in 3000 to 4000 Å thick instead of the amorphous silicon film by LPCVD method [FIG. 1(b)].
Then, a silicon film 4 was dry-etched, and FIG. 1(c) was obtained. This etching treatment was conducted using a gas of CF4+Cl2 system, setting up RIE (Reactive Ion Etching) mode condition and keeping the temperature of substrate to be treated at 10� C. or less, preferably at 0� C. This patterning step of the silicon film 4 to become a gate electrode is carried out in vacuum. In succession, a silicon oxide layer 3 was etched in 700 Å thick, replacing the reaction gas with CF4+H2 system without breaking the vacuum and keeping RIE mode condition. Thus obtained structure is shown in FIG. 1(d). Namely; it shows a structure that a thin part of insulating film 7 is provided at the side of gate insulating film.
Furthermore, an isotropic plasma etching was effected, replacing the reaction gas with CF4+O2 system and cooling the substrate to 0� C. without breaking the vacuum as it was. Thereby, an etching of a silicon film 5 was proceeded to form a gate electrode as shown in FIG. 1(e). This is ascribed to that the selection ratio of an exposed silicon oxide layer 7 per a gate electrode silicon film 5 is in a degree of tens. It was also found that since the protective film was deposited on the side wall of gate electrode when the etching of silicon oxide layer was conducted before this plasma etching, an etching reproducibility is more improved by ashing the protective film using an oxygen plasma.
In case of the preparation for NMOS as TFT obtained by removing 3000 Å of a gate electrode in a direction of a width of the gate electrode by etching in accordance with the above-mentioned method, phosphorous (P) was implanted as an impurity ion implantation, setting up 2�1013atoms/cm2 of a dose with e.g., 60 kV of acceleration energy. In succession, the ion implantation of 5�1015atoms/cm2 of a dose with 30 kV of acceleration energy was executed. After that, as an impurity activation process, e.g., 600� C. and 24 hrs. of a heat-annealing was applied, thereby obtaining TFT having such LDD structure as shown in FIG. 1(g).
As a next process, a hydrogen treatment was effected at 400� C. and for 2 hrs. and PSG as an interlayer insulating film was formed in 1 μm thick, and a contact hole was made. Then, TFT having LDD structure was completed by film-forming and patterning of Al electrode. Such prepared TFT had a feature that the leak current between source and drain was reduced by about 2 to 3 figure in 10−9A order, and also that a dielectric strength was improved, as the concentration of electric field in the end of drain was lightened and the carrier implantation into the gate silicon oxide film was reduced.
The preparing arrangement for a complementary type MOS is as follows; the structure of FIG. 3(a) was prepared by the preparing process fundamentally according to the above Example 1. Then, boron (B) as an impurity was doped on the whole area, under e.g., 10 kV of acceleration voltage and 1�1015atoms/cm2 of dose, to form a source or a drain part of PMOS 30, 31, and to form LDD 32 nearby the gate electrode 33 at the same time [FIG. 3(b)]. Further, the side of PMOS transistor was covered with resist 34 as shown in FIG. 3(c), and a doping with phosphorous (P) as an impurity was effected, under e.g., 30 kV of acceleration voltage and 5�1015atoms/cm2 of dose. Thereby forming a source or a drain part of NMOS 35, 36, and also forming LDD 37 nearby the gate electrode 38 [FIG. 3(c)].
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4319395Jun 28, 1979Mar 16, 1982Motorola, Inc.Method of making self-aligned deviceUS4757026 *Sep 16, 1987Jul 12, 1988Intel CorporationSource drain doping techniqueUS4897361Dec 14, 1987Jan 30, 1990American Telephone & Telegraph Company, At&T Bell LaboratoriesPatterning method in the manufacture of miniaturized devicesUS4946799Nov 9, 1989Aug 7, 1990Texas Instruments, IncorporatedProcess for making high performance silicon-on-insulator transistor with body node to source node connectionUS4951601Jun 23, 1989Aug 28, 1990Applied Materials, Inc.Multi-chamber integrated process systemUS5162892 *May 17, 1991Nov 10, 1992Sony CorporationSemiconductor device with polycrystalline silicon active region and hydrogenated passivation layerUS5962870Jun 6, 1995Oct 5, 1999Semiconductor Energy Laboratory Co., Ltd.Insulated gate field effect semiconductor devicesUS6011277 *Sep 9, 1998Jan 4, 2000Semiconductor Energy Laboratory Co., Ltd.Gate insulated field effect transistors and method of manufacturing the sameJPH0298143A Title not availableJPH0320046A Title not availableJPH0547791A Title not availableJPH01125866A Title not availableJPH02159730A Title not availableJPH02237037A Title not availableJPS5470762A Title not availableJPS6055665A Title not availableJPS57102067A * Title not availableJPS59161870A Title not availableJPS62174973A Title not availableJPS63204769A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7414288Oct 21, 2005Aug 19, 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having display deviceUS7705358Dec 14, 2007Apr 27, 2010Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of manufacturing the sameUS7816195Oct 19, 2010Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and manufacturing method thereofUS8405149May 16, 2008Mar 26, 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having display deviceUS8574976Oct 14, 2010Nov 5, 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and manufacturing method thereofUS8928081Mar 21, 2013Jan 6, 2015Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having display deviceUS20060043376 *Oct 21, 2005Mar 2, 2006Semiconductor Energy Laboratory Co., Ltd., A Japan CorporationSemiconductor device having display deviceUS20060267097 *Aug 2, 2006Nov 30, 2006Semiconductor Energy Laboratory Co., Ltd.Method for forming a MOS transistor and structure thereofUS20080290345 *May 16, 2008Nov 27, 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having display deviceUS20110033988 *Feb 10, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and manufacturing method thereof* Cited by examinerClassifications U.S. Classification257/347, 257/66, 257/408, 257/351, 257/350, 257/344, 257/352, 257/E29.278, 257/E21.413, 257/72International ClassificationH01L27/12, H01L29/786, H01L29/78, H01L27/01, H01L29/94, H01L29/04, H01L29/76, H01L21/336Cooperative ClassificationY10S438/907, Y10S148/15, H01L27/1214, H01L29/78621, H01L29/66757, H01L27/12, H01L29/66598European ClassificationH01L29/66M6T6F11B3B, H01L29/66M6T6F15A2, H01L29/786B4BLegal EventsDateCodeEventDescriptionJan 6, 2010FPAYFee paymentYear of fee payment: 4Mar 21, 2014REMIMaintenance fee reminder mailedAug 8, 2014LAPSLapse for failure to pay maintenance feesSep 30, 2014FPExpired due to failure to pay maintenance feeEffective date: 20140808RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services