Source: https://patents.google.com/patent/JPH11327518A/en
Timestamp: 2020-07-07 20:20:50
Document Index: 560810330

Matched Legal Cases: ['art 1', 'art 1', 'art 2', 'art 1', 'art 2', 'art 2', 'art 1', 'art 2']

JPH11327518A - Liquid crystal display device - Google Patents
JPH11327518A
JPH11327518A JP24139398A JP24139398A JPH11327518A JP H11327518 A JPH11327518 A JP H11327518A JP 24139398 A JP24139398 A JP 24139398A JP 24139398 A JP24139398 A JP 24139398A JP H11327518 A JPH11327518 A JP H11327518A
JP24139398A
1998-03-19 Priority to JP6962598 priority Critical
1998-03-19 Priority to JP10-69625 priority
1998-08-27 Application filed by Sony Corp, ソニー株式会社 filed Critical Sony Corp
1998-08-27 Priority to JP24139398A priority patent/JPH11327518A/en
1999-11-26 Publication of JPH11327518A publication Critical patent/JPH11327518A/en
(57) [Problem] To consider the application of time-division driving to a general-purpose driver IC for dot inversion driving, the polarity of the output signal of the driver IC for dot inversion driving is reversed for each odd and even number. For this reason, when time-division driving is performed, a state where dot inversion driving cannot be performed may occur. SOLUTION: In a liquid crystal display device using dot inversion driving, when time division driving capable of reducing the number of output pins of a driver IC 14 is applied, the number of time divisions is odd, preferably 3 to the nth power (n is (Natural number) and set the driver IC1
4 is time-division-divided by the time-division switch 16 from the signal line 12-.
1, 12-2, 12-3,... Realizes complete dot inversion driving.
The present invention relates to a liquid crystal display (L).
The present invention relates to a liquid crystal display (CD), and more particularly to an active matrix type liquid crystal display device using time division driving.
2. Description of the Related Art Active matrix type liquid crystal display devices used in personal computers, word processors and the like are mainly used. This active matrix type liquid crystal display device is excellent in response speed and image quality, and has become an optimal display device for colorization in recent years. In this type of display device, each pixel of the liquid crystal display panel uses a non-linear element such as a transistor or a diode. Specifically, a thin film transistor (TFT) is formed on a transparent insulating substrate such as a glass substrate.
film transistor).
In the active matrix type liquid crystal display device, adjacent dots (pixels) are driven as a driving method.
A so-called dot inversion driving method for inverting the polarity of the voltage applied to the pixel is said to be good for improving the image quality. The reason is as follows. That is, by setting the voltage applied to the adjacent dots to the opposite polarity, the jump potential from the signal line due to the cross capacitance between the signal line and the gate line is canceled. As a result, the pixel potential is input stably, and flicker during liquid crystal display is reduced.
On the other hand, when the dot inversion drive is not performed, if the ground level of the gate line fluctuates, the off state of the gate switch of the thin film transistor cannot be determined, so that the retained pixel potential is discharged. Would. For this reason, the transmittance of the pixel decreases, and the contrast of the pixel cannot be obtained. Further, since the jump potentials from the signal lines have the same polarity, the contrast of the pixels for each line is conspicuous, and even if the same gradation is displayed, a different display is performed for each line. become.
[0005] Since these disadvantages can be solved, the dot inversion driving method is an effective driving method for a liquid crystal display device for improving image quality.
Incidentally, the output of an external driver IC for driving the liquid crystal display panel and the signal line of the liquid crystal display panel usually have a one-to-one correspondence. That is, each output of the driver IC is directly supplied to the corresponding signal line. On the other hand, in order to reduce the size of the driver IC, a so-called time-division driving method is known as a driving method of the liquid crystal display panel that enables the number of output pins (output terminals) of the driver IC to be reduced. .
In this time-division driving method, a plurality of signal lines are defined as one unit (block), and signals to be supplied to a plurality of signal lines in the one-division block are time-series.
On the other hand, the liquid crystal display panel is provided with a time-division switch using a plurality of signal lines as one unit, and the time-division switches time-divide the time-series signals output from the driver IC into a plurality of signals. This is a driving method that is sequentially applied to lines.
However, when time division driving is applied to a general-purpose driver IC for dot inversion driving, the polarity of the output signal of the dot inversion driving driver IC is inverted for each odd and even number. Due to the polarity, when the time-division driving is performed, a state where the dot inversion driving cannot be performed may occur. This will be described below by taking, for example, the case of two-time-division driving.
As an example of two-time-division driving, as shown in FIG. 17, two signal lines 71-1 which are adjacent to each other in order regardless of the colors of R (red), G (green) and B (blue). And 71-2,7
.., 1 to 3 as one unit (block), and time division switches 72-1 and 72-2, 72-3 and 72-4,. , Time-series signals supplied from driver ICs (not shown) via output lines 73-1, 73-2,... Are divided into signal lines 71-1 and 71-2, 71-3 and 71, respectively. -4,... May be sequentially applied.
In the case of the two-time-division driving having such a configuration, the odd-numbered and even-numbered inverted signal voltages of the output terminals of the driver IC are distributed to the odd-numbered array and the even-numbered array of the actual pixels and Since the polarity is reversed,
As is clear from FIG. 18 showing the writing state of the signal voltage, the inversion of the polarity of the applied voltage in the adjacent pixels on one line, that is, the dot inversion cannot be achieved over the entire pixel area.
In FIG. 18, the horizontal direction is the scanning order,
The vertical direction indicates the operation order of the time-division switch, and H indicates a high voltage and L indicates a low voltage write state.
As another example of the two-time-division driving, as shown in FIG. 19, two adjacent R, G, and B colors are used.
Book signal lines 81-1 and 81-4, 81-2 and 81-5, 81
-3 and 81-6,... Are defined as one unit (block), and time-division switches 82-1 and 82-1 connected to each of these signal lines.
2-4, 82-2 and 82-5, 82-3 and 82-6,..., Output lines 83-1, 83-2,.
Are time-division-divided into signal lines 81-1 and 81-4, 81-2 and 81-5, 81-3 and 81
-6,... May be given sequentially.
As is apparent from FIG. 20 showing the writing state of the signal voltage, dot inversion cannot be achieved at the boundary between the divided blocks of one line. Then, since the boundary of the divided block deviates from the definition of dot inversion,
The fluctuation of the pixel potential occurs and is displayed as a vertical line.
In FIG. 20, the horizontal direction is the scanning order,
That is, when the number of divisions is an even number, FIG.
20 and FIG. 20, the polarity of the signal voltage A to be written first in the divided block is opposite to the polarity of the signal voltage B to be written last. Since the signal voltage supplied from the driver IC has the opposite polarity between the odd-numbered dot and the even-numbered dot, the signal voltages B1, B2,... The polarity of the signal voltages A2, A3,... Written first is the same.
Therefore, in the former case of the two-time division driving, the dot inversion driving cannot be performed over the entire pixel area, and in the latter case, the dot inversion driving is performed at the boundary between the divided blocks. A state of being unable to perform occurs, which leads to deterioration of image quality. However, it is possible to invert the polarity by rotating the color signal. However, as will be described later, the processing for rearranging the data becomes complicated, and the number of processing circuits increases.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal display device capable of realizing time-division driving without deteriorating image quality. .
According to the liquid crystal display device of the present invention, a plurality of pixels are two-dimensionally arranged at intersections of a plurality of rows of gate lines and a plurality of columns of signal lines arranged in a matrix. A display unit, a driver circuit that outputs a time-series signal corresponding to a predetermined number of time divisions, and a time-series signal output from the driver circuit that is time-divided and corresponds to a plurality of columns of signal lines. And a time-division switch for supplying the signal line to be switched, and the number of time divisions by the time-division switch is set to an odd number.
In the liquid crystal display device having the above-described configuration, the driver circuit outputs time-series signals corresponding to the number of time divisions in order to realize time-division driving. In the case of, for example, dot inversion driving, the time-series signals are signals having alternately different polarities (dot inversion signals). Then, in the time-division switch, this time-series signal is time-division-divided by an odd number of time-division numbers and supplied to the corresponding signal line, so that the voltages applied to adjacent pixels in one line do not have the same polarity. The dot inversion drive is performed over the entire pixel area.
Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a wiring diagram of a liquid crystal display unit in an active matrix liquid crystal display device according to a first embodiment of the present invention.
The active matrix type liquid crystal display device according to the first embodiment has a plurality of gate lines 11-
1, 11-2, 11-3,... And a plurality of signal lines 12-
Are arranged in a matrix on the surface of the liquid crystal, and a backlight is arranged on the back side of the liquid crystal. And the gate line 11
-1, 11-2, 11-3,... And signal lines 12-1, 12-
The intersections of 2, 12-3,... Become pixels and form a liquid crystal display panel (display unit) 10. The configuration of this pixel will be described later.
A plurality of gate lines 11-1, 11-2,
Each end of 11-3,... Is connected to each output end of the corresponding row of the vertical drive circuit 13. The vertical drive circuit 13 is provided on the same substrate (a transparent insulating substrate such as a glass substrate) on which the liquid crystal display panel is provided.
Vertical scanning is performed by sequentially giving selection pulses to 1-1, 11-2, 11-3,... And selecting each pixel on a row-by-row basis.
The signal lines 12-1, 12-2, 12-
3, a driver IC 14 for giving a signal potential corresponding to the image data is provided as an external circuit of the liquid crystal display panel 10. For example, digital image data that enables display of 512 colors or more in eight or more gradations is input to the driver IC 14. Then, the driver IC 14
A general-purpose IC for dot inversion driving is used. The driver IC 14 outputs a signal voltage whose potential is inverted every odd-numbered dot and even-numbered dot in order to realize dot inversion driving.
The driver IC 14 is configured to use a plurality of signal lines as one unit and to output signals given to the plurality of signal lines in time series in order to realize time division driving. Correspondingly, the output lines 15-1, 15-2, 15-3 of the driver IC 14 and the signal lines 12-
1, 12-2, 12-3,..., A time division switch 1
6 are provided. Each configuration of the driver IC 14 and the time division switch 16 will be described later.
FIG. 2 is a circuit diagram of the pixel. As is apparent from FIG.
1, an additional capacitor 22 and a liquid crystal capacitor 23. The thin-film transistor 21 has its gate electrode connected to a gate line..., 11m-1, 11m, 11m + 1,..., And its source electrode connected to a signal line (source line), 12n-1, 12n, 12n + 1,. It is connected to the.
In this pixel structure, the liquid crystal capacitance 23 is
It means a capacitance generated between a pixel electrode formed by the thin film transistor 21 and a counter electrode formed correspondingly. Then, the potential held by this pixel electrode is
Writing is performed at the “H” or “L” potential. here,
“H” indicates a high voltage write state, and “L” indicates a low voltage write state.
In driving the liquid crystal, the potential of the common electrode (common potential VCOM) is set to, for example, a DC potential of 6 V, and the signal voltage is periodically changed to a high voltage H and a low voltage L in one field cycle. , AC drive can be realized. This AC driving can reduce the polarization action of the liquid crystal molecules, and can prevent the charging of the liquid crystal molecules or the charging of the insulating film existing on the electrode surface.
On the other hand, in the pixel 20, the thin film transistor 2
When 1 is turned on, the light transmittance of the liquid crystal changes and the additional capacitor 22 is charged. By this charging, even if the thin film transistor 21 is turned off, the light transmittance state of the liquid crystal by the charging voltage of the additional capacitor 22 is maintained until the thin film transistor 21 is turned on next time. With such a method, the image quality of the image on the liquid crystal display panel 10 is improved.
FIG. 3 is a block diagram showing an example of the internal configuration of the driver IC 14. As is clear from FIG.
The driver IC 14 includes a horizontal shift register circuit 31, a sampling switch group 32, a level shifter 33, a data latch circuit 34, and a digital-to-analog conversion circuit 35. In this example, for example, 5-bit digital image data data1 to data5 and a power supply voltage Vdd , Vss are taken in from both sides of the horizontal shift register circuit 31 in the shift direction.
In the driver IC 14 having the above configuration, the horizontal shift register circuit 31 performs horizontal scanning (column scanning) by sequentially outputting horizontal scanning pulses. Each of the sampling switches in the sampling switch group 32 responds to a horizontal scanning pulse from the horizontal shift register circuit 31 to input digital image data dat.
a1 to data5 are sampled sequentially.
The level shifter 33 boosts digital data of, for example, 5 V sampled by the sampling switch group 32 to digital data of a liquid crystal driving voltage. The data latch circuit 34 is a memory that stores digital data boosted by the level shifter 33 for one horizontal scanning period. The digital / analog conversion circuit 35 converts digital data for one horizontal scanning period output from the data latch circuit 34 into an analog signal and outputs the analog signal.
Here, from the driver IC 14, in order to realize the above-described dot inversion drive, the polarity is inverted at the odd number (odd) and the even number (even) of the output terminal, and 1H (H is a horizontal scanning period). A dot inversion signal whose polarity is inverted every time is output. In addition, in order to realize time division driving, a plurality of signal lines of the liquid crystal display panel 10 are connected to one signal line.
Signals to be given to these signal lines are output in time series from each output terminal as a unit (block).
Hereinafter, a specific example of the first embodiment of the present invention applied to dot inversion driving will be described.
FIG. 4 is a configuration diagram showing a first example of a connection configuration of the time division switch 16, and shows an example of application to three time division driving corresponding to, for example, R, G, and B (part 1). . In the case of the three-time-division driving according to this application example (part 1), signals adjacent to each of R, G, and B colors, that is, signals for three pixels every two pixels, are output from each output terminal of the driver IC 14. Are output in time series via output lines 15-1, 15-2, 15-3,....
Specifically, as shown in the timing chart of FIG.
From the d output terminal to the output line 15-1 are R1, R2, R3
Is output from the even output terminal to the output line 1
The signal of each pixel of G1, G2, G3 is output to 5-2, the signal of each pixel of B1, B2, B3 is output to the output line 15-3 from the odd output terminal, and so on.
On the other hand, time-division switches 16-1, 16-4, 16-7 are connected between the output line 15-1 and the three signal lines 12-1, 12-4, 12-7. Time-division switches 16-2, 16-5, and 16-8 are provided between the line 15-2 and the three signal lines 12-2, 12-5, and 12-8.
Time-division switches 16-3, 16-6, and 16-9 are provided between the signal lines 12-3, 12-6, and 12-9.
These time division switches 16-1, 16-4,
16-7, 16-2, 16-5, 16-8, 16-3, 16-6, 1
6-9, together with a pixel switch (transistor), a transistor constituting the vertical drive circuit 13, and the like, for example, a bottom gate structure shown in FIG. 7A or FIG.
Are formed in the liquid crystal display panel 10 by a polycrystalline TFT (thin film transistor) having a top gate structure shown in FIG.
In the bottom gate type thin film transistor shown in FIG.
2, a polysilicon (Poly-Si) layer 44 is formed thereon with a gate insulating film 43 interposed therebetween, and an interlayer insulating film 45 is further formed thereon. On the gate insulating film 43 on the side of the gate electrode 42, a source region 46 and a drain region 47 made of an N + diffusion layer are formed. In these regions 46 and 47, a source electrode 48 and a drain electrode 49 are formed. Each is connected.
In the thin film transistor having a top gate structure shown in FIG. 7B, a polysilicon layer 52 is formed on a glass substrate 51, and a gate electrode 54 is formed thereon with a gate insulating film 53 interposed therebetween. An interlayer insulating film 55 is formed thereon. A source region 56 and a drain region 57 made of an N + diffusion layer are formed on the glass substrate 51 on the side of the polysilicon layer 52, and a source electrode 58 and a drain electrode 59 are formed in these regions 56 and 57. Each is connected.
6-9,... Are externally applied gate selection signals s
1, s2, and s3 (see the timing chart of FIG. 6), the driver IC is sequentially turned on,
The time series signals output from the output line 14 to the output lines 15-1, 15-2, 15-3,... Are supplied to the corresponding signal lines in three horizontal divisions during one horizontal scanning period.
In this manner, for example, signal potentials enabling display of eight or more gradations and 512 or more colors are output from the driver IC 14 to the output lines 15-1, 15-2, 15-3,.
Are input to signal lines 12-1, 12-2, 12-3,... Via time division switches 16-1, 16-2, 16-3,. In this case, the time-series signals output from the external driver IC 14 are supplied to the time-division switches 16-1, 16-2, 16-3,...
At this time, the number of time divisions is preferably an odd number, particularly a power of 3 (n is a natural number), that is, a multiple of 3. The reason is that since one pixel is composed of R, G, and B3 dots, the R1, R2, and R3 outputs of the pixel become odd and even outputs in the odd and even inverted outputs from the external driver IC 14. This is because it can respond. Naturally, G1, G2, and G3 and B1, B2, and B3 follow this.
As is clear from the above description, each output terminal of the driver IC 14 is connected to each output line 15-1,.
, 15-2, 15-3,... Are output in a synchronized manner. Therefore, the signal potential output from the external driver IC 14 does not need to be rotated, and the data can be continuously rearranged without considering complicated data rearrangement. Memory control for rearranging data can be simplified.
Here, the signal rotation means R,
Instead of the G and B signals being output in a synchronized manner,
Some output terminals start with R and have the order of G and B, other output terminals have the order of B and R, and other output terminals have the order of B and R and have the order of R and G. To tell. To enable this, it is necessary to perform a process of rearranging the color signal data before taking it into the driver IC 14 and storing the data in the buffer memory.
As described above, the signal voltages of the output terminals of the driver IC 14 whose odd and even numbers are inverted in polarity are distributed to the odd and even arrays of actual pixels, and the polarity is inverted for each line. However, in the case of 3 time division driving, since the number of time divisions is an odd number, as is apparent from FIG. 5, the signal voltages B1, B2,. Have different polarities from the signal voltages A2, A3,... Written at the beginning of the divided block. That is, the dot inversion drive is performed over the entire pixel area.
FIG. 5 shows a state in which the signal voltage is written to each pixel in the case of the three-time-division driving shown in FIG. In the figure, the horizontal direction indicates the scanning order, the vertical direction indicates the operation order of the time-division switch, and H indicates a high voltage write state and L indicates a low voltage write state.
FIG. 8 is a configuration diagram showing a second example of the connection configuration of the time division switch 16, and shows an application example (2) to three time division driving corresponding to, for example, R, G, and B. . In the case of three-time-division driving according to this application example (part 2), signal potentials for three pixels of R, G, and B are sequentially output from each output terminal of the driver IC 14 in a time series to the output lines 15-1 and 15-1. Fifteen
-2, 15-3, ... output.
More specifically, as shown in the timing chart of FIG.
The signal of each pixel of R1, G1, B1 is output from the dd terminal to the output line 15-1, the signal of each pixel of R2, G2, B2 is output from the even terminal to the output line 15-2, and the output line 15 is output from the odd terminal. The signal of each pixel of R3, G3, and B3 is output to -3, for example.
On the other hand, time division switches 16-1, 16-2, 16-3 are connected between the output line 15-1 and the three signal lines 12-1, 12-2, 12-3. Time-division switches 16-4, 16-5, and 16-6 are provided between the line 15-2 and the three signal lines 12-4, 12-5, and 12-6.
Time-division switches 16-7, 16-8, 16-9 are provided between the signal lines 12-7, 12-8, 12-9.
These time division switches 16-1, 16-2,
16-3, 16-4, 16-5, 16-6, 16-7, 16-8, 1
6-9,..., As in the previous application example, FIG.
Alternatively, it is formed in the liquid crystal display panel 10 by the polycrystalline TFT having the gate structure shown in FIG. 3B and sequentially turned on in response to gate selection signals s1, s2, and s3 (see the timing chart of FIG. 10) externally applied. As a result, the output lines 15-1, 15-2,
The time-series signals output to 15-3,... Are supplied to the corresponding signal lines in three horizontal divisions during one horizontal scanning period.
Also in the case of the above-mentioned three time division driving, since the number of time divisions is an odd number, as apparent from FIG. 9, the signal voltages B1, B2,
... and the signal voltage A to be written first in the next divided block
2, A3,.... That is, the dot inversion drive is performed over the entire pixel area. As is clear from FIG. 10, after the output of R is completed, the output of G is generated, and further the output of B is generated. Therefore, the output from the external driver IC 14 is performed in the same manner as in the application example. For such a signal potential, there is no need to rotate the signal, and no complicated data rearrangement is required.
FIG. 9 shows a state in which the signal voltage is written to each pixel in the case of the three time division driving shown in FIG. In the figure, the horizontal direction indicates the scanning order, the vertical direction indicates the operation order of the time-division switch, and H indicates a high voltage write state and L indicates a low voltage write state.
As described above, in the active matrix type liquid crystal display device using the dot inversion drive, the complete dot inversion drive can be performed even when the time division drive is applied. super X
GA) and UXGA (ultra XGA), where the number of display pixels tends to increase, without increasing the number of horizontal drive circuits and output ICs of the liquid crystal display device,
Conversely, the number can be reduced. In addition to achieving a stable supply of high-quality images while enabling dot inversion display, the liquid crystal display module can be made more compact, and inexpensive liquid crystal display panels can realize multi-color display. Becomes possible.
In each application example described above, the number of time divisions is 3
Has been described as an example, but is not limited to 3 time division, such as 9 time division, 27 time division,
By setting 3 to the nth power (n is a natural number), the driver I
The inverted signal output from the odd-numbered terminal and the even-numbered terminal of C14 can be synchronized with the inverted signal corresponding to the pixel arrangement at each time division.
FIG. 11 shows a configuration applied to 9-time division driving, and FIG. 12 shows a state in which signal voltages are written to respective pixels in 9-time division driving. Also in the case of the 9 time division drive, since the number of time divisions is an odd number, as apparent from FIG. 12, the signal voltages B1, B2,... , The polarity is different from the signal voltages A2, A3,... Written first, and it can be seen that the dot inversion drive is performed over the entire pixel area.
Further, by setting the number of time divisions to the nth power of three, the signal of each pixel can be handled in units of R, G, and B, thereby simplifying the signal processing. Another advantage is that the amount of data in the memory can be reduced. However, the present invention is not limited to the number of time divisions of 3 to the power of n, and the dot inversion can be realized over the entire pixel area by setting the number of time divisions to an odd number.
FIG. 13 shows a configuration applied to, for example, five-time-division driving, and FIG. 14 shows a state of writing a signal voltage to each pixel in the five-time-division driving. Also in the case of the five time division driving, the number of time divisions is odd,
As apparent from FIG. 4, the polarity of the signal voltages B1, B2,... Written at the end of the previous divided block and the signal voltages A2, A3,. It can be seen that the dot inversion drive is performed over a period of.
On the assumption that dot inversion driving is performed, in order to realize complete dot inversion driving, the number of time divisions is set to an odd number, particularly 3 to the nth power.
M) R, G, B even in inversion drive or 1H inversion drive
In this case, there is an advantage that the time-division driving can be realized without deteriorating the image quality.
Here, the common (VCOM) inversion drive means a common voltage VC commonly applied to the counter electrode of each pixel.
This is a driving method in which the OM is inverted every 1H. Also,
1H inversion driving is a driving method in which the polarity of image data given to each pixel is inverted every 1H with respect to the common voltage VCOM.
Hereinafter, a second embodiment of the present invention applied to common (VCOM) inversion driving will be described.
FIG. 15 is a schematic diagram showing an active matrix type color liquid crystal display device according to a second embodiment of the present invention. The configuration of the active matrix liquid crystal display device according to the second embodiment is basically the same as the configuration of the active matrix liquid crystal display device according to the first embodiment.
In the effective screen area of the color liquid crystal display panel 60, gate lines..., 61m,.
B signal line 62Rn, 62Gn, 62Bn,
1 from 3 dots of R, G, B arranged at the intersection with ...
One pixel is configured. , 63m,..., A common voltage VCOM that is AC-reversed every 1H, for example, is applied to the common electrodes of these pixels via Cs lines. As a result, the common (V
COM) inversion driving is realized.
One end of each of the gate lines..., 61m,... Is connected to each output end of the corresponding row of the vertical drive circuit 65. The vertical drive circuit 65 is provided on the same substrate (a transparent insulating substrate such as a glass substrate) as the color liquid crystal display panel 60, and applies a selection pulse to the gate lines..., 61m,. Vertical scanning is performed by selecting in units of rows.
On the same substrate as the color liquid crystal display panel 60, signal lines..., 62Rn, 62Gn, 6
Analog switches corresponding to each of 2Bn,.
66Rn, 66Gn, 66Bn,... Are formed. These analog switches 66Rn, 66G
n, 66Bn,... are also the same as in the first embodiment.
Polycrystalline TFT having a gate structure shown in FIG. 7 (a) or (b)
And an analog switch..., 66R
n, 66Gn, 66Bn,.
, 62Rn, 62Gn, 62Bn,..., And the other end is a set of R, G, B, and is commonly connected to each set. That is, the analog switch 66R
n, 66Gn and 66Bn form a pair and the other ends are connected in common, and the analog switches 66Rn + 1, 66Gn +
1, 66Bn + 1 form a set and the other ends are connected in common, and so on, and the other ends are connected in common for each set.
These analog switches..., 66Rn,
.., 66Gn, 66Bn,..., Each having a common connection point connected to each corresponding output terminal of the driver IC 67 and having a switch control pulse S output from the switch control circuit 68.
L1, SL2, and SL3 sequentially control on (close) / off (open) R, G, and B in this order, so that each output of the driver IC 67 is connected to three R, G, and B signal lines.
62Rn, 62Gn, 62Bn,... That is, the analog switches 66R, 66G, 66B
Functions as a time division switch.
The switch control circuit 68, together with the driver IC 67, may be made of a single crystal silicon chip on an external substrate separate from the substrate of the color liquid crystal display panel 60. And may be made of polycrystalline TFT on the same substrate.
The driver IC 67 has three signal lines 62 R, 62 R of each vertical pixel column of the color liquid crystal display panel 60.
A circuit configuration is provided for each pair corresponding to G and 62B. That is, for example, regarding the circuit configuration of the n-th column, a sampling circuit 671n that samples input image data, and this sampling circuit 671n
67 for holding image data sampled by
2n, a DA converter 673n for digitizing data held in the memory 672n, and an output circuit 674
In the driver IC 67, the sampling circuit 671n corresponds to the horizontal shift register circuit 3 shown in FIG.
1, sampling switch group 32 and level shifter 3
3, the memory 672n corresponds to the data latch circuit 34, and the DA converter 673n corresponds to the digital-to-analog conversion circuit 35. Note that a circuit portion corresponding to the output circuit 674n is omitted in FIG.
Thus, the analog switches..., 62
By using three time-division driving by Rn, 62Gn, 62Bn,..., The driver IC 67 has a set of a sampling circuit 671, a memory 672, and a DA converter 6 for the three signal lines 62R, 62G, and 62B.
Since only the 73 and the output circuit 674 are required, the area, the cost, and the power consumption of the driver IC 67 can be reduced.
The driver IC 67 sequentially samples the input image data every 1H (one horizontal scanning period), and writes the image data into the pixels of the row that is vertically selected by the vertical drive circuit 65. The image data input to the driver IC 67 has a common voltage V
The polarity is inverted every 1 H with respect to COM. Thus, 1H inversion driving is realized.
In addition to the 1H inversion drive, as described above, the common voltage generation circuit 64 generates the common voltage VCOM that is AC-inverted every 1H, thereby realizing the common inversion drive. As described above, by using the common inversion drive together with the 1H inversion drive, the polarity of the common voltage VCOM is also inverted every 1H, and the AC inversion drive is performed, so that the power supply voltage of the driver IC 67 can be reduced. Thus, power consumption and cost can be reduced.
Next, the operation of the active matrix type color liquid crystal display device according to the second embodiment will be described with reference to the timing chart of FIG.
The image data input to the driver IC 67 is data in which R, G, and B data are serially arranged during 1H. This image data is sampled (O (n)) by the sampling circuit 671 three times during 1H for three data of R, G, and B, and
72 (P (n)), and output via the DA converter 673 and the output circuit 674 (Q
(n)). These signals have a common voltage V within 1H period.
It is of the same polarity for COM.
The output (Q (n)) of the driver IC 67 is 1
This is data in which the polarity is inverted every H, and the switch control pulses SL1, SL2 and SL from the switch control circuit 68.
3 analog switch (time division switch) 66R,
The signal is distributed to three signal lines 62R, 62G, and 62B by the on (closed) / off (open) control of 66G and 66B (3 time division).
As a result, for example, taking the n-th column as an example,
R, G, B signal lines 62Rn, 62Gn, 62Bn
The potentials CRn, CGn, and CBn change as shown in FIG. 16, and the display data is written to the signal lines 62Rn, 62Gn, and 62Bn. Signal line 62R
The display data written to n, 62Gn, and 62Bn is
The vertical scanning is performed by the vertical driving circuit 65 and the selection pulse V
The data is written to the pixel in the row selected vertically by g.
In this embodiment, the case where the present invention is applied to a common (VCOM) inversion drive in which the polarity of the common voltage VCOM is inverted every 1 H has been described.
Is fixed to a certain DC voltage, 1H inversion driving is performed,
This 1H inversion drive is similarly applicable.
As described above, in the common (VCOM) inversion drive or 1H inversion drive, the number of time divisions is R, G, B
The following operational effects can be obtained by adopting the three-time division corresponding to the above.
That is, the potentials written to the signal lines 62R, 62G and 62B by the switch control pulses SL1, SL2 and SL3 by the switch control circuit 68 change during the high impedance period after the analog switches 66R, 66G and 66B are opened. The shift is performed under the influence of various capacitive couplings in the liquid crystal display panel 60. The potential finally written to the pixel is determined at the moment when the selection pulse Vg from the vertical drive circuit 65 falls.
Therefore, as a result, the potential of the pixel corresponding to the signal line written first in the horizontal scanning period is different from the potential of the pixel corresponding to the signal line written last. Therefore, in the case of the above-described two-time-division driving or the like, since one pixel is not a set of R, G, and B, the potential fluctuation of the signal line for each color is not constant, and the color unevenness in the vertical direction (vertical streak) ) Can cause visual problems.
On the other hand, as in the present embodiment, the number of time divisions is set to three time divisions corresponding to R, G, and B, and the data to be written to the signal lines at different timings is R, G, and B.
By providing three lines, G and B, the potential fluctuation of the signal line for each color is substantially uniform, that is, R for R, G for G, and B for B, and this potential difference appears as a luminance difference. Since there is no such change, it appears only as a subtle change in color tone visually, and no practical visual problem occurs.
In the active matrix type liquid crystal display device, when time division driving capable of reducing the number of output pins of the driver IC is applied, by setting the number of time divisions to an odd number, the polarity of the adjacent dots (pixels) in one line is changed. Since different voltages can be applied alternately, even when time-division driving is applied, complete dot inversion driving can be performed, thereby reducing flicker and contrast difference of liquid crystal for each line. Can be eliminated,
Therefore, time-division driving can be realized without deteriorating image quality.
FIG. 1 is a wiring diagram of a liquid crystal display unit in an active matrix type liquid crystal display device according to the present invention.
FIG. 4 is a configuration diagram illustrating a connection configuration of a time division switch in a case of three time division driving (part 1) in the first embodiment.
FIG. 5 is a diagram illustrating a state in which a signal voltage is written to each pixel in the case of three time division driving (1).
FIG. 6 is a timing chart of each signal in the case of three time division driving (1).
FIGS. 7A and 7B are cross-sectional structural views showing an example of a thin film transistor, wherein FIG. 7A shows a case of a bottom gate structure, and FIG. 7B shows a case of a top gate structure.
FIG. 8 is a configuration diagram showing a connection configuration of a time division switch in a case of three time division drive (part 2) in the first embodiment.
FIG. 9 is a diagram illustrating a state in which a signal voltage is written to each pixel in the case of three time division driving (part 2).
FIG. 10 is a timing chart of each signal in the case of three time division driving (No. 2).
FIG. 11 is a configuration diagram showing a connection configuration of a time division switch in the case of 9 time division driving in the first embodiment.
FIG. 12 is a diagram illustrating a state in which a signal voltage is written to each pixel in the case of 9 time-division driving.
FIG. 13 is a configuration diagram showing a connection configuration of a time division switch in a case of five time division driving in the first embodiment.
FIG. 14 is a diagram illustrating a state in which a signal voltage is written to each pixel in the case of five time-division driving.
FIG. 15 is a schematic configuration diagram illustrating an active matrix liquid crystal display device according to a second embodiment of the present invention.
FIG. 16 is a timing chart for explaining the operation of the active matrix liquid crystal display device according to the second embodiment.
FIG. 17 is a configuration diagram showing a connection configuration of a time division switch in a case of two time division driving (No. 1).
FIG. 18 is a diagram illustrating a state in which a signal voltage is written to each pixel in the case of two time division driving (part 1).
FIG. 19 is a configuration diagram showing a connection configuration of a time division switch in the case of two time division driving (No. 2).
FIG. 20 is a diagram illustrating a state in which a signal voltage is written to each pixel in the case of two time division driving (part 2).
10, 60 ... Liquid crystal display panel, 11-1 to 11-3, 61m
... Gate lines, 12-1 to 12-9, 51-1 to 51-4, 6
1-1 to 61-6, 62R, 62G, 62B ... signal lines,
13, 65: vertical drive circuit, 14, 67: driver I
C, 15-1 to 15-6, 53-1, 53-2, 63-1 to 63-3
... output lines, 16, 16-1 to 16-9 ... time-division switches, 20 ... pixels, 21 ... thin film transistors, 22 ... additional capacitors, 23 ... liquid crystal capacitors, 64 ... common voltage generation circuits, 6
6R, 66G, 66B: Analog switch, 68: Switch control circuit
────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroaki Ichikawa 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation
1. A display unit in which a plurality of pixels are two-dimensionally arranged at intersections of a plurality of rows of gate lines and a plurality of columns of signal lines arranged in a matrix, corresponding to a predetermined number of time divisions A driver circuit for outputting a time-series signal obtained from the driver circuit, and a time-division switch for time-dividing the time-series signal output from the driver circuit and supplying the time-series signal to a corresponding signal line among the plurality of columns of signal lines. A liquid crystal display device, wherein the number of time divisions by the time division switch is set to an odd number.
2. The liquid crystal display device according to claim 1, wherein the number of time divisions performed by the time division switch is n to the power of 3 (n is a natural number).
3. When one pixel is composed of three dots of R (red), G (green), and B (blue), the number of time divisions by the time division switch corresponds to R, G, and B. 3. The liquid crystal display device according to claim 2, wherein
4. The liquid crystal display device according to claim 1, wherein the driver circuit is a driver IC disposed outside a transparent insulating substrate on which the display section is formed.
5. The liquid crystal display device according to claim 1, wherein the driver circuit outputs odd-numbered and even-numbered signals of opposite polarities among the output terminals.
6. The liquid crystal display device according to claim 1, wherein the driver circuit outputs a signal having a reverse polarity every horizontal scanning period.
7. The liquid crystal display device according to claim 6, wherein the polarity of the common voltage applied to the counter electrode of the pixel is inverted every horizontal scanning period.
JP24139398A 1998-03-19 1998-08-27 Liquid crystal display device Pending JPH11327518A (en)
JP6962598 1998-03-19
JP10-69625 1998-03-19
JP24139398A JPH11327518A (en) 1998-03-19 1998-08-27 Liquid crystal display device
US09/271,211 US6424328B1 (en) 1998-03-19 1999-03-17 Liquid-crystal display apparatus
KR1019990009393A KR100686312B1 (en) 1998-03-19 1999-03-19 Liquid-crystal display apparatus
JPH11327518A true JPH11327518A (en) 1999-11-26
ID=26410803
JP24139398A Pending JPH11327518A (en) 1998-03-19 1998-08-27 Liquid crystal display device
US (1) US6424328B1 (en)
JP (1) JPH11327518A (en)
KR (1) KR100686312B1 (en)
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