Source: http://www.google.com/patents/US6317377?dq=6,243,373
Timestamp: 2016-06-29 03:18:29
Document Index: 306367995

Matched Legal Cases: ['art 67', 'art 68', 'art 67', 'art 67', 'art 68', 'art 68', 'art 67', 'art 67', 'art 67', 'art 68', 'art 67', 'art 68', 'art 67', 'art 67', 'art 76', 'art 76', 'art 76']

Patent US6317377 - Semiconductor memory device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThe purpose of the present invention is to provide a semiconductor memory device which is capable of suppressing an increase in chip surface area and in power consumption resulting from peripheral circuitry even when the capacity thereof becomes large, and which, moreover, does not experience discrepancies...http://www.google.com/patents/US6317377?utm_source=gb-gplus-sharePatent US6317377 - Semiconductor memory deviceAdvanced Patent SearchPublication numberUS6317377 B1Publication typeGrantApplication numberUS 09/546,915Publication dateNov 13, 2001Filing dateApr 11, 2000Priority dateApr 12, 1999Fee statusPaidPublication number09546915, 546915, US 6317377 B1, US 6317377B1, US-B1-6317377, US6317377 B1, US6317377B1InventorsShotaro KobayashiOriginal AssigneeNec CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (1), Referenced by (58), Classifications (7), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor memory device
FIG. 16 shows the bottom surface of a BGA (ball grid array) which is a type of CSP; this actually realizes a conventional semiconductor memory device which is provided with four memory cell arrays. Ball bumps are disposed in the form of a matrix in the package in BGA, and I/O pads are arranged in a concentrated manner in the vicinity of the center of the package. In other words, in the figure, the parts surrounded by circles (∘) are ball bumps, and the rectangles (□) which are smaller than the ball bumps are the pads. From left to right in the figure, “DQA7-DQA0, DQB0-DQB7” is written in the pads and in the circles (∘) of the ball bumps corresponding thereto, and these correspond to the DQ0-DQ7 and DQ8-DQ 15 shown in FIG. 15. Even if the memory capacity is doubled and the number of memory cell arrays becomes eight, the position of the pads and balls will not change from that shown in FIG. 16; however, because the chip size will not be the same, the shape will be one in which the left and right edges in the figure are further extended in the left and right directions.
In FIG. 2, the “0th bit data”-“3rd bit data” are given numbers “0”-“3” in accordance with the order in which they are processed in a time series manner. That is to say, the readout from the memory cell array and the writing to the memory cell array are processed in such an order that the 0th data is first processed, and then, in order, the first data, the second data, and the third data are processed. Furthermore, as is clear from the figure, the “0th data”, for example, constitutes 8-bit parallel data which is simultaneously exchanged between memory cell arrays.
Additionally, in the present embodiment, the arrangement is such that the data which are simultaneously exchanged from the serial-parallel/parallel-serial conversion circuit with respect to the input/output interface circuit 5-1 are compiled from those outputted initially in a time series manner and outputted. That is to say, the characteristic feature of this is that, among the 8-bit parallel data simultaneously exchanged with the memory cell array, the “0th bit” serial data (the “0th bit data” in the figure) which are initially exchanged with the exterior are positioned closest to the input/output interface circuit 5-1 (interface logic 2). This is to say that the access time in the case in which a readout request is conducted with respect to the semiconductor memory device is determined by how fast the “0th bit” data may be outputted, so that the serial-parallel/parallel-serial conversion circuit and the input/output interface circuit 5-1 are disposed in close proximity so as to output the “0th bit” data in the shortest possible time.
Next, flip flop groups (in the figures, shortened to “FF”) 12-0 through 12-3 store the 0th bit data through 3rd bit data comprising 8 bits, respectively; these incorporate the output of the previous stage flip flop group in a synchronous manner with clock signal CLOCK, and in accordance with the data load signal LOAD, the 0th through 3rd bit data are simultaneously established with respect to these flip flop groups. In actuality, the clock signal CLOCK and the data load signal LOAD are supplied to the eight flip flops comprising the individual flip flop groups; however, in order to avoid complexity, a depiction of this wiring is omitted.
FIG. 3 shows the structure of the semiconductor memory device in accordance with the present embodiment in greater detail than does FIG. 1; those structural elements which are identical to those of FIG. 1 are given identical reference numbers. In the figure, banks Ba0-Ba31 are memory banks which serve to realize high speed operations; the 32 banks are assigned using, as units, two memory cell arrays which employ in common a serial-parallel/parallel-serial conversion circuit. Furthermore, circuit blocks 15-1 through 15-4 contain, in addition to the serial-parallel/parallel-serial conversion circuit (“S-P”) described above, a data amplifier (“DA”) for amplifying data read out from the memory cell array by a sense amplifier (not depicted in the figure), a writing amplifier (the “WA” in the figure) which is employed during the writing of the data into the memory cell array, and the like.
Furthermore, the 16 rectangles (∘) are all bonding pads for data input and output, and these correspond to the DQ0-DQ15 shown in FIG. 15. Furthermore, references 17-1 through 17-8 are row decoders corresponding to the memory cell arrays 1-1 through 1-8, and row predecoders (“Row pre dec.”), redundancy circuits (“Row red.”), bank and column predecoders (“Col pre dec”) and the like are provided in circuit blocks 18-1 through 18-2, and the column decoders which conduct the main decoding of the columns are in the region in which the sense amplifier described above is disposed.
The serial-parallel/parallel-serial conversion circuit shown in FIG. 4 is commonly employed by the adjacent memory cell arrays A and B, and these memory cell arrays A and B correspond to, for example, the memory cell arrays 1-1 and 1-5 which are shown in FIG. 1. Additionally, the depiction in FIG. 2 described above was only of the data flow relating to memory cell array B. In memory cell array A and B, data DQ0-7<0> through DQ0-7<3> correspond to, respectively, the 0th bit data through the 3rd bit data shown in FIG. 2. In other words, the reference to “RDQ0-7” or “WDQ07” indicates eight data lines. As is shown in FIG. 2, in these memory cell arrays A and B, the block of DQ0-7<0> corresponding to the 0th data is disposed at the lower side of the figure, that is to say, at the side of the input/output interface circuit which is not depicted in the figure, while the blocks DQ0-7<1>, DQ0-7<2>and DQ0-7<3> are positioned at increasing distances from the input/output interface circuit.
Next, the parallel-serial conversion circuit for converting the parallel data read out from memory cell arrays A and B to serial data will be explained. The parallel-serial conversion circuit comprises multiplexer (referred to in the figures as MUX) groups 20-1 through 20-3 and flip flop groups 21-1 through 21-3. Multiplexer groups 20-0 through 20-3 each comprise eight multiplexers corresponding to data DQ0-7; in accordance with the logic level of a signal inputted to the SLL terminal, one or the other of the signals connected to the A terminal and the B terminal is selected, and outputted to the Q terminal. Here, when the selection signal SELR inputted into the SEL terminal has a “H” level, then the A terminal is selected, while when the signal has a “L” level, the B terminal is selected. In other words, in accordance with the SELR signal, the multiplexer groups 20-0 through 20-3 output to flip flop groups 21-0 through 21-3, in alternating fashion, the data DQ0-7<0> through DQ0-7<3> from the memory cell array A and the data DQ0-7<0> through DQ0-7<3> from memory cell array B.
On the other hand, flip flop groups 21-0 through 21-3 comprise, in the same way as multiplexer groups 20-0 through 20-3, eight flip flops corresponding to data DQ0-7, and as is explained in the text relating to FIG. 2, these comprise eight groups of shift registers. Furthermore, these flip flop groups 21-0 through 21-3 are flip flops with attached load functions, and when the load terminal is at the “L” level, then the data inputted into the D1 terminal are incorporated on the rise of the clock signal RCLK inputted into the CLK terminal, and are outputted from the Q terminal, while when the load terminal is at the “H” level, then the data inputted into the D2 terminal are incorporated on the rise of the clock signal RCLK and are outputted from the Q terminal.
Next, D latch groups 23-0 through 23-3 incorporate data from the respective D terminals which has been outputted from the Q terminals of the D flip flop groups 22-0 through 22-3, and output these from their own Q terminals, while the latch signal latch which is commonly inputted into the EN terminals has an “H” level. Next, writing amplifier groups 24-0 through 24-3 have a signal WEA which has a “H” level inputted into the EN terminals thereof when data writing is to conducted into the memory cell array A, and when this EN terminal has an “H” level, the output of D latch groups 23-0 through 23-3 is buffered and is outputted to memory cell array A. In the same way, writing amplifier groups 25-0 through 25-3 have inputted into the EN terminals thereof a signal WEB which has a “H” level when writing is to be conducted with respect to the memory cell array B, and when the EN terminal has a “H” level, the output of the D latch groups 23-0 through 23-3 is buffered and is outputted to memory cell array B.
Here, a concrete circuit structure example will be shown with respect to each part comprising the parallel-serial conversion circuit and the serial-parallel conversion circuit depicted in FIG. 4. FIG. 5 is a structural example of the multiplexer groups 20-0 through 20-3; reference 50 shows an inverter, while references 51 and 52 show transfer gates. These transfer gates are those commonly constructed using a pair containing an n-type MOSFET (metal oxide semiconductor field effect transistor) and a p-type MOSFET indicated by a circle (∘); the transfer gates refer to hereinbelow arc identical. In the structure depicted, if the SEL terminal has an “H” level, then the A terminal and the Q terminal are connected by the transfer gate 51, while when the SEL terminal has an “L” level, the B terminal and the Q terminal are connected by transfer gate 52.
Next, FIG. 6 is a structural example of the flip flop gates 21-0 through 21-3 with detached load functions; references 55 through 60 indicate inverters, while references 61 through 66 indicate transfer gates. Among these, inverters 57 and 58 and transfer gate 64 form a data storage part 67, while inverters 59 and 60 and transfer gate 66 form a data storage part 68. By means of the structure depicted in the figure, when the load terminal has an “H” level, then among the transfer gates 61 and 62, only the former is open, and the data (load data) inputted into the D terminal are transmitted to transfer gate 63. On the other hand, when the load terminal has an “L” level, then only the latter transfer gate 62 is opened, and the data (shift data) inputted into terminal D1 are transmitted to the transfer gate 63.
Furthermore, when the clock inputted into the CLK terminal has a level of “L”, the transfer gate 64 closes and the output of inverter 58 is cut off from the input of inverter 57, and by opening transfer gate 63, the data applied to one or the other of terminal D1 and terminal D2 is transmitted to data storage part 67 in accordance with the logic level of the load terminal. Furthermore at this time the transfer gate 65 is closed, so that the data stored in data storage part 67 are prevented from being incorporated into the data storage part 68 side, and the transfer gate 66 is opened and the data storage part 68 stores the data, and the stored data are outputted to the Q terminal. As described above, from the fall of the clock inputted into the CLK terminal until the next rise in the clock, data selected in accordance with the logic level of the load terminal are incorporated into the data storage part.
On the other hand, when the clock inputted into the CLK terminal reaches the “H” level, the transfer gate 63 closes and either the data of the D1 terminal or the D2 terminal is prevented from being transmitted from the data storage part 67, and the transfer gate 64 opens and data storage part 67 continues to store the data incorporated at the point in time at which the clock rose. Furthermore, at this time, the transfer gate 66 closes and the output of inverter 60 is cut off from the input of inverter 59, and by opening transfer gate 65, the data stored in data storage part 67 are transmitted to the data storage part 68 side, so that the data outputted from terminal Q are also changed. In the manner described above, from the rise of the clock to the succeeding fall of the clock, the data incorporated into data storage part 67 at the rise of the clock are transmitted to data storage part 68 and terminal Q.
Next, FIG. 7 is an example of the structure of the D flip flop gates 22-0 through 22-3; those structural elements which are the same as those depicted in FIG. 6 are given identical reference numbers. In the D flip flop shown in FIG. 7, the inverter 55 and the transfer gates 61 and 62 have been eliminated from the structural example of the flip flop with attached load functions shown in FIG. 6, and the D terminal is directly connected to the transfer gate 63. For this reason, whereas in FIG. 6 either the data inputted into the D1 terminal or the data inputted into the D2 terminal was selected and transmitted to the data storage part 67, in the D flip flop shown in FIG. 7, while the clock signal CLK is at the “L”level, the data inputted into the D terminal are transmitted in an unchanged fashion to the data storage part 67, and this is the only point of difference.
Next, FIG. 8 shows a structural example of the D latch groups 23-0 through 23-3; references 70 through 73 indicate inverters, while references 74 through 75 indicate transfer gates. Here, inverters 71 and 72 and transfer gate 75 form data storage part 76. In accordance with the structure depicted in the figure, if the signal inputted into the EN terminal has a level of “H”, the transfer gate 74 opens and the data inputted into the D terminal are transmitted to the data storage part 76, so that the data inputted into the D terminal via inverters 71 and 73 are themselves outputted to the Q terminal. Furthermore, at this time, the transfer gate 75 closes and the output of inverter 72 is prevented from being transmitted to the input of inverter 71. On the other hand, when the signal inputted into the EN terminal has the “L” level, the transfer gate 74 closes and the transfer gate 75 opens, so that the data in the data storage part 76 continue to be stored.
Next, FIG. 9 is a structural example of the writing amplifier groups 24-0 through 24-3 and 25-0 through 25-3; references 80-81 indicate inverters, while references 82-83 indicate p-type MOSFETs, and references 84-85 are n-type MOSFETs. In accordance with the structure depicted in the figure, when the signal inputted into the EN terminal has an “H” level, MOSFET 85 enters an ON state and the output of inverter 80 attains the “L” level, so that MOSFET 82 also enters an ON state. For this reason, the “inputted” data are outputted in an unchanged manner as “output”. In other words, when the inputted data have an “H” level and the output of inverter 81 has the “L” level, then MOSFET 83 enters an ON state, MOSFET 84 enters an OFF state, and the output is connected to the power source. On the other hand, when the inputted data have an “L,” level, then MOSFET 83 enters an OFF state, MOSFET 84 enters an ON state, and the output is connected to the ground. In addition, if the signal inputted into the EN terminal has an “L” level and the output of the inverter 80 has an “H” level, then both MOSFET 82 and 85 enter an OFF state, and the output has a high impedance state irrespective of the inputted data.
Next, the operation of the semiconductor memory device having the structure described above will be explained. Here, FIG. 10 is a timing chart showing the outlines of the operation when parallel data are to be read out from the memory cell array. Here, the explanation will be of a case in which data are read out from the memory cell array A in FIG. 4. In this case, readout is conducted from the memory cell array, so that signal WEA, signal WEB, and the latch signal Latch all have a level of “L”, and a clock is not inputted into clock signal WCLK.
On the other hand, when there is a data readout request with respect to memory cell array A, prior to the actual readout, the signal SELR in FIG. 4 is set in advance to the “H” level. By means of this, multiplexer groups 20-0 through 20-3 select the data DQ0-7<0> through DQ0-7<3> from the memory cell array A, and these are supplied individually to the D2 terminals of flip flop groups 21-0 through 21-3. Next, it will be assumed that the data which are read out from memory cell array A at a time t1 begin to be outputted. The data DQ0-7<0> through DQ0-7<3> read out are the 8-bit data “data 0” through “data 3” in FIG. 10.
Next, when a pulse is inputted into data load signal LOAD and level “H” is attained at time t2, the flip flop groups 21 -0 through 21-3 initiate the incorporation of the data “data 0” through “data 3” inputted into the respective D2 terminals. After this, when the clock signal RCLK starts up at time 23, the flip flop groups 21-0 through 21-3 output the data “data 0” through “data 3”, which were incorporated from the D2 terminals, from the Q terminals. As a result, the “data 0”, which are the 0th bit parallel data, are outputted from the flip flop group 21-0 as data RDQ0-7, and these are outputted to the exterior of the device from the I/O pads corresponding to the data RDQ0-7, via the input/output interface circuit 5-1.
After this, when the data load signal LOAD switches to an “L” level at T4, flip flop groups 21-0 through 21-3 select the D1 terminal side. When the clock circuit RCLK subsequently falls at time t5, flip flop groups 21-0 through 21-3 initiate the incorporation of data inputted into the D1 terminals. That is to say, flip flop groups 21-0 through 21-2 incorporate the data “data 1” through “data 3” which were outputted from flip flop groups 21-1 through 21-3. The D1 terminal of flip flop group 21-3 is connected to the power source, so that a fixed value (“FF” in hexadecimal notation) is incorporated, and this is successively shifted in flip flop groups 21-2 through 22-0, however, an explanation thereof will be omitted here, as it has no direct relationship to the operation of the present embodiment.
Next, when the clock signal RCLK rises at time to, the data “data 1” through “data 3” incorporated by flip flop groups 21-0 through 21-2 are respectively outputted. As a result, in the same way as in the case of the data “data 0”, data “data 1” is outputted to the exterior of the device as data RDQ0-7. Thereinafter, in the same manner, flip flop groups 21-0 and 21-1 initiate the incorporation of data “data 2” and “data 3” which are inputted into the D1 terminals at time t7, and output the incorporated data at time t8, so that “data 2” is outputted to the exterior of the device as data RDQ0-7. Next, at time t9, flip flop group 21-0 initiates the incorporation of data “data 3” inputted into the D1 terminal, and at time t10, outputs the incorporated data as data RDQ0-7, and outputs these to the exterior device. In this way, 8-bit X 4-cycle serial data readout is completed.
The explanation above centered on data readout from memory cell array A, however, the case in which parallel-serial conversion is conducted with respect to the data read out from the memory cell array B is identical to the case of memory cell array A with the exception of the following points. That is to say, in this case the selection signal SELR is set in advance to the “L” level, and the multiplexer groups 20-0 through 20-3 select, respectively, the data DQ0-7<0> through DQ0-7<3> from the memory cell array and supply these to the D2 terminals of the flip flop groups 21-0 through 21-3. The operations after this point are identical to those in those in the case of memory cell array A.
Next, FIG. 11 is a timing chart showing the outlines of the operation in the case of the writing of data with respect to a memory cell array. Here, as well, the explanation will center on the case of writing data to the memory cell array A. In this case, data are written to the memory cell array, so that the data load signal LOAD is at the “L” level and a clock is not inputted into the clock signal RCLK. Furthermore, as in the case of readout, the data “data 0” through “data 3” are written into the blocks DQ0-7<0> through DQ0-7<3> in memory cell array A.
First, in the same way as was explained in the case of the readout above, when a bank and row activation request and the succeeding writing request are applied together with an address signal, the designated bank and word line are activated and a state is established in which writing is possible to the bit line corresponding to the indicated column. Up to this point, this is identical to the case of the conventional semiconductor memory device. Additionally, when there is a writing request with respect to the memory cell array A, the signal WEA is set in advance of the actual writing to the “H” level, while the signal WEB is set to the “L” level. By means of this, the writing amplifier groups 25-0 through 25-3 are placed in a disabled state, and the output thereof is in the high impedance state. On the other hand, the writing amplifier groups 24-0 through 24-3 are placed in an enabled state, so that the state attained is one in which it is possible to conduct output from flip flop groups 23-0 through 23-3 to each block DQ0-7 <0> through DQ0-7<3> of the memory cell array A.
After this, the written data are successively shifted with respect to the semiconductor memory device from the exterior, and when this is done, writing data “data 0” are supplied at time t21 to data WDQ0-7 via the interface logic 2 shown in FIG. 1. These data are inputted into the D terminal of flip flop group 22-3 and data incorporation is initiated. After this, when the clock signal WCLK rises at time t22, as a result of conducting the shift operation in the shift registers, the incorporation of data by flip flop group 22-3 is completed, and data “data 0” are outputted, and these data are inputted into the D terminal of flip flop group 22-2. Next, when t23 is reached, the data in data WDQ0-7 are switched to data “data 1”, and when the clock signal WCLK rises at time t24, flip flop group 22-2 incorporates the data “data 0” outputted by the flip flop group 22-3 and outputs these data and these data are also inputted into the D terminal of flip flop group 22- 1. On the other hand, flip flop group 22-3 incorporates data “data 1” in WDQ0-7 and outputs these.
Thereinafter, the same shift operations are conducted. In other words, at time t25, WDQ0-7 switches over to data “data 2” and when the clock signal WCLK rises at time t26, the flip flop group 22-1 incorporates the data “data 0” outputted by the flip flop group 22-2 and outputs these, and these data are inputted into the D terminal of the flip flop group 22-0. Furthermore, flip flop group 22-2 incorporates and outputs the data “data 1” outputted by the flip flop group 22-3, and flip flop group 22-3 incorporates and outputs the data “data 2” inputted from WDQ0-7. Then, at time t27, WDQ0-7 switches over to data “data 3” and when clock signal WCLK rises at time t28, flip flop groups 22-0 through 22-2 output the data “data 0” through “data 2” outputted by, respectively, the flip flop groups 22-1 through 22-3, and flip flop group 22-3 outputs the “data 3” inputted from WDQ0-7.
As described above, synchronously with the clock signal WCLK, the data “data 0” through “data 3” are successively incorporated into flip flop group 22-3, and simultaneously, the shift registers comprising flip flop groups 22-0 through 22-3 carry out a shift operation. As a result, at time t28, all data corresponding to 8-bits�4-cycles are incorporated into flip flop groups 22-0 through 22-3. After this, when a pulse is inputted into the latch signal Latch at time t29, and this signal reaches the “H” level, then data latch groups 23-0 through 23-3 incorporate the data “data 0” through “data 3” outputted by the flip flop groups 22-0 through 22-3, and output these from the Q terminals. As a result, these data are written into each block DQ0-7<0> through DQ0-7<3> of memory cell array A via the writing amplifier groups 24-0 through 24-3.
The foregoing explanation centered on the writing of data into the memory cell array A; however, the serial-parallel conversion conducted when writing data into memory cell array B is identical to that in the case of the memory cell array A with the exception of the following points. That is to say, in this case, prior to the actual writing, the signal WEA is set to a “L” level, and the signal WEB is set to an “H” level, and as a result, the writing amplifier groups 24-0 through 24-3 enter a disabled state and the output thereof enters a high impedance state, and furthermore, the writing amplifier groups 25-0 through 25-3 enter an enabled state. For this reason, by means of operations similar to those explained in the case of the memory cell array A, data “data 0” through “data 3” are all incorporated into the D latch groups 22-0 through 22-3 and are then written into each block DQ0-7<0> through DQ0-7<3> of the memory cell array B via writing amplifier groups 25-0 through 25-3.
Next, the points of difference between the present embodiment and the first embodiment with respect to the operation of the semiconductor memory device having the structure described above will be explained. Initially, the parallel-series conversion process with respect to parallel data read out from the memory cell array was explained with reference to FIG. 10; however, the operation in this case is identical to that of the First embodiment. In other words, if the case of readout from memory cell array A is assumed as in the first embodiment, then the data DQ0-7<0> through DQ0-7<3>outputted simultaneously from memory cell array A at time t1 are selected when the data load signal LOAD rises at time t2. After this, at time t3, when the clock signal RWCLK (corresponding to the RCLK in FIG. 10) rises, the selected data “data 0” through “data 3” are loaded into, respectively, flip flop groups 21-1 through 21-3 and as a result, the data “data 0” are obtained as the data RDQ0-7. After this, a shift operation is conducted synchronously with the rise of the clock RWCLK, and at times to, t8, and t10, respectively, the data “data 1”, “data 2” and “data 3” are obtained as data RDQ0-7.
Next, the serial-parallel conversion operation conducted when writing is carried out with respect to the memory cell array will be explained with reference to FIG. 11 described above. In this figure, it is necessary to substitute flip flop groups 21-0 through 21-3 for the D flip flop groups 22-0 through 22-3. Here, as well, the case will be assumed in which data are written with respect to the memory cell array A, in the same way as in the first embodiment. First, when data are to be written into the memory cell array, the data load signal LOAD maintains the “L” level, so that flip flop groups 21-0 through 21-3 select the D1 terminal side among the D1 terminal and the D2 terminal. Then, when the data “data 0” are applied as WDQ0-7 at time t21, flip flop group 21-3 initiates the incorporation of this data, and subsequently, when clock signal RWCLK (corresponding to the WCLK in FIG. 11) rises at time t22 and a shift operation is conducted, the flip flop group 21-3 incorporates this data and supplies it to the D1 terminal of flip flop group 21-2. Next, at t23, data “data 1” are applied to WDQ0-7, and when the shift operation is carried out at time t24, flip flop groups 21-2 and 21-3 output, respectively, the data “data 0” and “data 1”.
Thereinafter, in the same manner, data “data 2” are applied to WDQ0-7 at time t25, while time t26, flip flop groups 21-1 through 21-3 output, respectively, data “data 0” through “data 2” as the results of the shift operations. Next, at time t27, data “data 3” are applied to WDQ0-7, and at time t28, flip flop groups 21-0 through 21-3 output, respectively, data “data 0” through “data 3” as the results of the shift operation. In this way, when the serially inputted data corresponding to 4 cycles of 8 bits are arranged in flip flop groups 21-0 through 21-3, the latch signal Latch reaches an “H” level at time t29, and the data stored in flip flop groups 21-0 through 21-3 are transmitted to, respectively. D latch groups 23-0 through 23-3. As a result, the 32 bit data transmitted to these D latch groups is written into each block DQ0-7<0> through DQ0-7<3> in the memory cell array A via writing amplifier groups 24-0 through 24-3.
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