Source: http://www.google.es/patents/USRE42241?hl=es&dq=flatulence
Timestamp: 2013-05-22 12:02:47
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Matched Legal Cases: ['Application No. 11', 'Application No. 2007', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 2007', 'Application No. 2009', 'Application No. 2009']

Patente USRE42241 - Method of fabricating a semiconductor device - Google PatentesB�squeda Im�genes Maps Play YouTube Noticias Gmail Drive M�s » B�squeda avanzada de patentes | Historial web | Iniciar sesi�n B�squeda avanzada de patentesPatentesA semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate,...http://www.google.es/patents/USRE42241?utm_source=gb-gplus-sharePatente USRE42241 - Method of fabricating a semiconductor device N�mero de publicaci�nUSRE42241 E1Tipo de publicaci�nConcesi�n N�mero de solicitud12/418,245 Fecha de publicaci�n22 Mar 2011 Fecha de presentaci�n3 Abr 2009 Fecha de prioridad4 Sep 1998Tambi�n publicado comoUS6335231US6803264US7473592US7473971US7476576US7638805US7642598US20020137265US20050009252US20070184632US20080054269US20080067596US20080070335US20080113487US20080113488US20090236698USRE42097USRE42139 InventoresHisashi OhtaniShunpei Yamazaki Cesionario originalSemiconductor Energy Laboratory Co., Ltd. Clasificaci�n de EE.UU.438/151257/E21.569257/E21.563438/458438/459438/164 Clasificaci�n internacionalH01L21/84H01L21/30H01L21/336H01L29/786H01L21/02H01L21/762H01L27/12 Clasificaci�n cooperativaH01L29/66772H01L29/78603H01L29/045H01L27/1214H01L21/76256H01L27/1266H01L21/76254H01L21/76243H01L27/1203 Clasificaci�n europeaH01L21/762D2H01L21/762D8BH01L21/762D8DH01L27/12BH01L29/66M6T6F15CH01L29/786AH01L29/04BH01L27/12TH01L27/12T30A2ReferenciasCitas de patentes (103)Otras citas (55)Enlaces externosUSPTO Cesi�n de USPTO EspacenetMethod of fabricating a semiconductor deviceUS RE42241 E1 Resumen A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
forming an oxide layer on a single crystal semiconductor substrate; adding hydrogen ions into the single crystal semiconductor substrate through the oxide layer to form a hydrogen-containing layer; bonding the single crystal semiconductor substrate and a supporting substrate with at least the oxide layer located between the single crystal semiconductor substrate and the supporting substrate; separating the single crystal semiconductor substrate by a first heat treatment along the hydrogen-containing layer so that a single crystal semiconductor layer remains on the oxide layer over the supporting substrate; patterning the single crystal semiconductor layer to form an island-like semiconductor layer; forming a gate electrode comprising polysilicon over the island-like semiconductor layer; adding a first impurity into the island-like semiconductor layer with the gate electrode as a mask; forming silicon oxide on side surfaces of the gate electrode; forming side walls comprising silicon nitride adjacent to the side surfaces of the gate electrode with the silicon oxide interposed therebetween; adding a second impurity into the island-like semiconductor layer with the gate electrode and the side walls as a mask so that source and drain regions and LDD regions are formed in the island-like semiconductor layer; forming a metal film in contact with a surface of the gate electrode and surfaces of the source and drain regions of the island-like semiconductor layer; heating the metal film so that an upper portion of the gate electrode and upper portions of the source and drain regions become a metal silicide; and forming an interlayer insulating film over the island-like semiconductor layer and the gate electrode. Descripci�n
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