Source: http://www.google.com/patents/US7436954?dq=5787449
Timestamp: 2015-05-25 08:16:13
Document Index: 10675885

Matched Legal Cases: ['art 118', 'art 118', 'art 118', 'art 118', 'art 118', 'art 118', 'art 118']

Patent US7436954 - Security system with an intelligent DMA controller - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA security subsystem is provided with at least a first security engine, a first set of registers and a control portion to perform a first security operation for each of a first number of data blocks of each of a first number of data segments of a first data object. In one embodiment, the security subsystem...http://www.google.com/patents/US7436954?utm_source=gb-gplus-sharePatent US7436954 - Security system with an intelligent DMA controllerAdvanced Patent SearchPublication numberUS7436954 B2Publication typeGrantApplication numberUS 10/469,467PCT numberPCT/US2002/006384Publication dateOct 14, 2008Filing dateFeb 28, 2002Priority dateFeb 28, 2001Fee statusPaidAlso published asUS7095752, US7096292, US7243179, US7349424, US7653763, US20020159474, US20020161959, US20020161978, US20040186930, US20050259823, US20060212632, US20060221931, WO2002069115A2, WO2002069115A3, WO2002069157A1, WO2002069158A1Publication number10469467, 469467, PCT/2002/6384, PCT/US/2/006384, PCT/US/2/06384, PCT/US/2002/006384, PCT/US/2002/06384, PCT/US2/006384, PCT/US2/06384, PCT/US2002/006384, PCT/US2002/06384, PCT/US2002006384, PCT/US200206384, PCT/US2006384, PCT/US206384, US 7436954 B2, US 7436954B2, US-B2-7436954, US7436954 B2, US7436954B2InventorsGeorge Apostol, Jr., Peter N. DinhOriginal AssigneeCavium Networks, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (43), Classifications (35), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetSecurity system with an intelligent DMA controller
US 7436954 B2Abstract
Base part 118 a for a hashing operation also includes a buffer size 444 and a starting address 446 (in memory 104) of the source buffer holding the base data segment 116 a being described. Base part 118 a also includes the starting address 448 (in memory 104) for the destination buffer for writing back the results of the security operation for the corresponding data bits of the base data segment 116 a. Additionally, base part 118 a for a hashing operation also includes mode 450 specifying the type of hashing operation, e.g. MD5 or SHA-1, to be performed, and descriptor identifier 452 of the descriptor. Further, base part 118 a of a hashing operation also describes at least four chaining variable 454-460, for the hashing operation, and for the SHA-1 mode of operation, a fifth chaining variable 462. For a MD5 hashing operation, base part 118 a also describes the “must write filer data” 462-464 of the hashing operation.
Continuation part 118 n of a descriptor 118 of a hashing operation also includes a buffer size 474 and a starting address 476 (in memory 104) of the source buffer holding the continuation data segment 116 n being described. Continuation part 118 n also includes the starting address 478 (in memory 104) for the destination buffer for writing back the results of the security operation for the corresponding data bits of the continuation data segment 116 n. Security Subsystem
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4352952 *Mar 3, 1980Oct 5, 1982Motorola Inc.Data security moduleUS4697262Jul 25, 1985Sep 29, 1987Siemens AktiengesellschaftDigital carrier channel bus interface module for a multiplexer having a cross-connect bus systemUS5185864Jun 16, 1989Feb 9, 1993International Business Machines CorporationInterrupt handling for a computing system with logical devices and interrupt resetUS5197130Dec 29, 1989Mar 23, 1993Supercomputer Systems Limited PartnershipCluster architecture for a highly parallel scalar/vector multiprocessor systemUS5222223Feb 3, 1989Jun 22, 1993Digital Equipment CorporationMethod and apparatus for ordering and queueing multiple memory requestsUS5224166Aug 11, 1992Jun 29, 1993International Business Machines CorporationSystem for seamless processing of encrypted and non-encrypted data and instructionsUS5353417 *May 28, 1991Oct 4, 1994International Business Machines Corp.Personal computer with bus interface controller coupled directly with local processor and input/output data buses and for anticipating memory control changes on arbitration for bus accessUS5388261Sep 30, 1992Feb 7, 1995Apple Computer, Inc.Apparatus and method for handling frame overruns in a digital signal processing systemUS5606668 *Dec 15, 1993Feb 25, 1997Checkpoint Software Technologies Ltd.System for securing inbound and outbound data packet flow in a computer networkUS5657472Mar 31, 1995Aug 12, 1997Sun Microsystems, Inc.Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processorUS5668813Mar 21, 1996Sep 16, 1997Nat Semiconductor CorpDynamic synchronization code detection windowUS5799207Mar 28, 1995Aug 25, 1998Industrial Technology Research InstituteNon-blocking peripheral access architecture having a register configure to indicate a path selection for data transfer between a master, memory, and an I/O deviceUS5812799Jun 7, 1995Sep 22, 1998Microunity Systems Engineering, Inc.Non-blocking load buffer and a multiple-priority memory system for real-time multiprocessingUS5848367 *Sep 13, 1996Dec 8, 1998Sony CorporationSystem and method for sharing a non-volatile memory element as a boot deviceUS5905876Dec 16, 1996May 18, 1999Intel CorporationQueue ordering for memory and I/O transactions in a multiple concurrent transaction computer systemUS6021201 *Jan 7, 1997Feb 1, 2000Intel CorporationMethod and apparatus for integrated ciphering and hashingUS6028939 *Jan 3, 1997Feb 22, 2000Redcreek Communications, Inc.Data security system and methodUS6034542Oct 14, 1997Mar 7, 2000Xilinx, Inc.Bus structure for modularized chip with FPGA modulesUS6058474Jan 23, 1998May 2, 2000Texas Instruments IncorporatedMethod and apparatus for DMA boot loading a microprocessor without an internal ROMUS6081852 *Apr 29, 1997Jun 27, 2000Texas Instruments IncorporatedPacket data transferring system for autonomously operating a DMA by autonomous boot mode select signal wherein the DMA is enabled to at least one program control listUS6118462Sep 9, 1997Sep 12, 2000Memtrax LlcComputer system controller having internal memory and external memory controlUS6122690Apr 17, 1998Sep 19, 2000Mentor Graphics CorporationOn-chip bus architecture that is both processor independent and scalableUS6185520May 22, 1998Feb 6, 20013Com CorporationMethod and system for bus switching data transfersUS6317803Sep 27, 1996Nov 13, 2001Intel CorporationHigh-throughput interconnect having pipelined and non-pipelined bus transaction modesUS6321285Jun 12, 2000Nov 20, 2001Fusion Micromedia CorporationBus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated methodUS6321318Dec 15, 1998Nov 20, 2001Texas Instruments IncorporatedUser-configurable on-chip program memory systemUS6347344Oct 14, 1998Feb 12, 2002Hitachi, Ltd.Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processorUS6557078Feb 21, 2000Apr 29, 2003Hewlett Packard Development Company, L.P.Cache chain structure to implement high bandwidth low latency cache memory subsystemUS6560160Nov 13, 2000May 6, 2003Agilent Technologies, Inc.Multi-port memory that sequences port accessesUS6675243 *Mar 15, 2000Jan 6, 2004Adaptec, Inc.Methods and apparatus for implementing a device side advanced serial protocolUS6681270Nov 15, 2000Jan 20, 2004Texas Instruments IncorporatedEffective channel priority processing for transfer controller with hub and portsUS6778667 *Dec 30, 1999Aug 17, 2004Intel CorporationMethod and apparatus for integrated ciphering and hashingUS6784890Mar 2, 1998Aug 31, 2004Intel CorporationAccelerated graphics port expedite cycle throttling control mechanismUS7020763Mar 8, 2001Mar 28, 2006Sun Microsystems, Inc.Computer processing architecture having a scalable number of processing paths and pipelinesUS7035966Aug 30, 2001Apr 25, 2006Micron Technology, Inc.Processing system with direct memory transferUS20010026439Apr 17, 2001Oct 4, 2001Micron Technology, Inc.Structure and method for an electronic assemblyUS20010049726May 31, 2001Dec 6, 2001Guillaume ComeauData path engineUS20030189573Mar 31, 2003Oct 9, 2003Dahlen Eric J.Method and apparatus for command translation and enforcement of ordering of commandsUS20040128144Oct 10, 2003Jul 1, 2004Johnson Christopher SeanPrompt management method supporting multiple languages in a system having a multi-bus structure and controlled by remotely generated commandsUS20040172490Apr 11, 2002Sep 2, 2004Mark StadlerReduced-overhead dmaUS20040250056Jun 3, 2003Dec 9, 2004Christopher ChangSystem boot methodUSRE37980Nov 3, 2000Feb 4, 2003Compaq Computer CorporationBus-to-bus bridge in computer system, with fast burst memory rangeWO2001018997A1Sep 7, 2000Mar 15, 2001Fantasma Networks IncBaseband wireless network for isochronous communication* Cited by examinerClassifications U.S. Classification380/37, 710/41, 235/382, 709/243, 713/164, 711/114, 709/228, 370/355, 707/999.001International ClassificationG06F13/362, H04L12/66, G06F13/16, G06F13/364, G06F13/14, H04K1/00, H04K1/06, H04K1/04, G06F13/28, G06F21/00Cooperative ClassificationY10S707/99931, G06F13/28, G06F13/1673, G06F21/72, G06F13/1621, G06F13/364, G06F2213/0038, G06F21/71, G06F13/362European ClassificationG06F21/72, G06F21/71, G06F13/16D2, G06F13/362, G06F13/364, G06F13/16A2M, G06F13/28Legal EventsDateCodeEventDescriptionMar 14, 2012FPAYFee paymentYear of fee payment: 4Jul 21, 2011ASAssignmentEffective date: 20110617Owner name: CAVIUM, INC., CALIFORNIAFree format text: MERGER;ASSIGNOR:CAVIUM NETWORKS, INC.;REEL/FRAME:026632/0672May 24, 2007ASAssignmentOwner name: CAVIUM NETWORKS, INC., CALIFORNIAFree format text: MERGER;ASSIGNOR:CAVIUM ACQUISITION CORP.;REEL/FRAME:019340/0001Effective date: 20070516Feb 14, 2005ASAssignmentOwner name: BRECIS COMMUNICATIONS CORP., CALIFORNIAFree format text: TERMINATION OF SECURITY AGREEMENT;ASSIGNOR:TRANSAMERICA TECHNOLOGY FINANCE CORPORATION;REEL/FRAME:016824/0393Effective date: 20040722Sep 10, 2004ASAssignmentOwner name: CAVIUM ACQUISITION CORP., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BRECIS COMMUNICATIONS CORPORATION;REEL/FRAME:015117/0933Effective date: 20040815Aug 28, 2003ASAssignmentOwner name: BRECIS COMMUNICATIONS CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:APOSTOL, JR., GEORGE;REEL/FRAME:014932/0648Effective date: 20030827Owner name: BRECIS COMMUNICATIONS CORPORATION, CALIFORNIAFree format text: EMPLOYEE INVENTION ASSIGNMENT AND CONFIDENTIALITY AGREEMENT;ASSIGNOR:DIHN, PETER N.;REEL/FRAME:014973/0064Effective date: 20000809Jun 19, 2003ASAssignmentOwner name: TRANSAMERICA TECHNOLOGY FINANCE CORPORATION, CONNEFree format text: SECURITY AGREEMENT;ASSIGNOR:BRECIS COMMUNICATIONS CORPORATION;REEL/FRAME:014172/0322Effective date: 20030613Jun 25, 2002ASAssignmentOwner name: BRECIS COMMUNICATIONS, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:APOSTOL JR., GEORGE;REEL/FRAME:013118/0923Effective date: 20020530Owner name: BRECIS COMMUNICATIONS, CALIFORNIAFree format text: EMPLOYEE INVENTION ASSIGNMENT AND CONFIDENTIALITY AGREEMENT;ASSIGNOR:DINH, PETER N.;REEL/FRAME:013126/0168Effective date: 20000809RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services