Source: http://www.google.com/patents/US8194087?dq=6,455,937
Timestamp: 2016-02-08 20:08:54
Document Index: 145553764

Matched Legal Cases: ['Application No. 02009031', 'Application No. 2002', 'Application No. 2000', 'Application No. 2008', 'Application No. 2008', 'Application No. 2002']

Patent US8194087 - Scalable unified memory architecture - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured...http://www.google.com/patents/US8194087?utm_source=gb-gplus-sharePatent US8194087 - Scalable unified memory architectureAdvanced Patent SearchPublication numberUS8194087 B2Publication typeGrantApplication numberUS 12/911,624Publication dateJun 5, 2012Filing dateOct 25, 2010Priority dateMay 15, 2001Fee statusPaidAlso published asUS6864896, US7821519, US20020171652, US20050146529, US20110037772, US20120182304Publication number12911624, 911624, US 8194087 B2, US 8194087B2, US-B2-8194087, US8194087 B2, US8194087B2InventorsRichard E. PeregoOriginal AssigneeRambus Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (26), Non-Patent Citations (29), Referenced by (2), Classifications (16), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetScalable unified memory architecture
US 8194087 B2Abstract
A particular embodiment of the memory modules shown in FIGS. 6, 7, and 8 uses multiple “Direct Rambus Channels” developed by Rambus Inc. of Mountain View, California. The Direct Rambus Channels connect the multiple memory devices to the associated rendering engine. In this embodiment, the memory devices are Rambus DRAMs (or RDRAMs�). However, other memory types and topologies may also be used within the scope of this invention. For example, memory types such as Synchronous DRAMs (SDRAMs), Double-Data-Rate (DDR) SDRAMs, Fast-Cycle (FC) SDRAMs, or derivatives of these memory types may also be used. These devices may be arranged in a single rank of devices or multiple ranks, where a rank is defined as a group of devices which respond to a particular class of commands including reads and writes.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5325493Mar 30, 1993Jun 28, 1994Hewlett-Packard CompanySystem for distributing command/data packets tagged by their unit identifier for parallel processing by a ready processing unit and recombinationUS5712664Oct 14, 1993Jan 27, 1998Alliance Semiconductor CorporationShared memory graphics accelerator systemUS5808690 *Jun 10, 1996Sep 15, 1998Integrated Device Technology, Inc.Image generation system, methods and computer program products using distributed processingUS5821949 *Jul 1, 1996Oct 13, 1998Sun Microsystems, Inc.Three-dimensional graphics accelerator with direct data channels for improved performanceUS5838334Nov 30, 1995Nov 17, 1998Dye; Thomas A.Memory and graphics controller which performs pointer-based display list video refresh operationsUS5854637 *Aug 17, 1995Dec 29, 1998Intel CorporationMethod and apparatus for managing access to a computer system memory shared by a graphics controller and a memory controllerUS5867180Mar 13, 1997Feb 2, 1999International Business Machines CorporationIntelligent media memory statically mapped in unified memory architectureUS5933195Dec 30, 1997Aug 3, 1999Sarnoff CorporationMethod and apparatus memory requirements for storing reference frames in a video decoderUS6073150Jun 23, 1997Jun 6, 2000Sun Microsystems, Inc.Apparatus for directing a parallel processing computing device to form an absolute value of a signed valueUS6104417 *Sep 13, 1996Aug 15, 2000Silicon Graphics, Inc.Unified memory computer architecture with dynamic graphics memory allocationUS6208273Oct 20, 1999Mar 27, 2001Interactive Silicon, Inc.System and method for performing scalable embedded parallel data compressionUS6275234Mar 19, 1998Aug 14, 2001Kabushiki Kaisha ToshibaDisplay control system and method for controlling display of three-dimensional graphics dataUS6295074 *Mar 21, 1996Sep 25, 2001Hitachi, Ltd.Data processing apparatus having DRAM incorporated thereinUS6317135Feb 4, 2000Nov 13, 2001Alliance Semiconductor CorporationShared memory graphics accelerator systemUS6377266 *Aug 13, 1998Apr 23, 20023Dlabs Inc., Ltd.Bit BLT with multiple graphics processorsUS6473086Dec 9, 1999Oct 29, 2002Ati International SrlMethod and apparatus for graphics processing using parallel graphics processorsUS6476816Jul 15, 1999Nov 5, 20023Dlabs Inc. Ltd.Multi-processor graphics acceleratorUS6657632Jan 24, 2001Dec 2, 2003Hewlett-Packard Development Company, L.P.Unified memory distributed across multiple nodes in a computer graphics systemUS6690726Apr 6, 2000Feb 10, 2004Broadcom CorporationVideo encoding and video/audio/data multiplexing deviceUS7365757Dec 17, 1998Apr 29, 2008Ati International SrlMethod and apparatus for independent video and graphics scaling in a video graphics systemUS20020161596 *Apr 30, 2001Oct 31, 2002Johnson Robert E.System and method for validation of storage device addressesJPH117335A Title not availableJPH0774606A Title not availableJPH1185345A Title not availableJPH08191661A Title not availableJPH08202653A Title not available* Cited by examinerNon-Patent CitationsReference1Comments on Statement of Reasons for Allowance, dated Sep. 22, 2010 in U.S. Appl. No. 11/058,051. 1 page.2Commission Investigative Staff's Post-Hearing Brief dated Nov. 5, 2009 re U.S. Patents 6,591,353, 6,470,405 and 7,287,109 (Barth I Family). 129 pages.3Commission Investigative Staffs Post-Hearing Reply Brief re 33-TA-661 All CBI Redacted, dated Nov. 30, 2009 re US Patent 6,292,903 and 6,226,757. 65 pages.4Complainant Rambus Inc.'s Initial Post-Hearing Brief re 33-TA-661 All CBI Redacted, dated Nov. 5, 2009. 138 pages.5Complainant's Post-Hearing Rebuttal Brief dated Nov. 20, 2009 re Farmwald '755 and '037, '757. 71 pages.6EP Office Action with mail date of Dec. 17, 2009 for EP Application No. 02009031.2 re Summons to attend oral proceedings in Munich on Jun. 23, 2010. 2 pages.7Final Office Action with mail date of Feb. 18, 2010 re U.S. Appl. No. 11/058,051 includes Information Disclosure Statement. 18 pages.8JAZiO Supplemental Information, Platform 2000, JAZiO Incorporated, No Date, Cite No. 4 in Non-Final Office Action dated Dec. 8, 2009, for JP Application No. 2002-122494. 11 pages.9JP Non-Final Office Action with mail date of Dec. 8, 2009 re JP Application No. 2000-516350. 11 pages.10JP Office Action re Decision of Rejection with mail date of Oct. 19, 2009, re JP Application No. 2008-027488 filed on Apr. 24, 2002. 6 pages.11JP Office Action with mail date of Oct. 14, 2009, re Decision of Rejection for JP Application No. 2008-027488 filed on Apr. 24, 2002. 6 pages.12Matsumoto, Craig, "HotRail cools on chip sets, switches to I/O," EE Times Europe, May 2, 2000, downloaded from http://www.eetimes.eu/showArticle.jhtmtjsassionid=WQ5K54PBMUXSVQE1GHPC on Nov. 26, 2009, Cite Ref. No. 3 in Non-Final Office Action for JP Application No. 2002-122494. 4 pages.13Notice of Allowance and Fee(s) Due with mail date of Jul. 1, 2010 re U.S. Appl. No. 11/058,051, includes Notice of References Cited. 9 Pages.14Notice of Allowance and Issue Fee(s) Due with mail date of Oct. 15, 2009 re U.S. Appl. No. 11/767,983, filed Jun. 25, 2007. 14 pages.15Nvidia ITC Trial Transcript Investigation No. 337-TA-661, Oct. 14, 2009. 35 pages.16Nvidia ITC Trial Transcript Investigation No. 337-TA-661, vol. 1 (Przybylski), Oct. 13, 2009. 25 pages.17Nvidia ITC Trial Transcript Investigation No. 337-TA-661, vol. 3 (Reed, Treichler & Subramanian), Oct. 15, 2009. 25 pages.18Nvidia ITC Trial Transcript Investigation No. 337-TA-661, vol. 4 (Subramanian & Barth), Oct. 16, 2009. 57 pages.19Nvidia ITC Trial Transcript Investigation No. 337-TA-661, vol. 5 (Stark, Moniz, Montana & Przybylski), Oct. 19, 2009. 15 pages.20Nvidia ITC Trial Transcript Investigation No. 337-TA-661, vol. 6 (Przybylski), Oct. 20, 2009. 55 pages.21Opponent's Statement of grounds of Appeal filed by Micron dated Nov. 30, 2009 for EP Patent 1,297,778. 84 pages.22Prince, Betty "High Performance Memories", New architecture DRAMs and SRAMs-evolution and function, Revised Edition. Reprinted May 2000, chapter 9, "Fast Packaging Techniques". 36 pages.23Prince, Betty "High Performance Memories", New architecture DRAMs and SRAMs—evolution and function, Revised Edition. Reprinted May 2000, chapter 9, "Fast Packaging Techniques". 36 pages.24Respondents' Final Post-Hearing Brief dated Nov. 5, 2009 re Ware patents and Barth I Patents. 131 pages.25Respondents' Reply Post-Hearing Brief dated Nov. 20, 2009 re Barth I Patents and Farmwald '755. 71 pages.26Response dated Jun. 18, 2010 to Final Office Action of Feb. 18, 2010 re U.S. Appl. No. 11/058,051. 5 Pages.27U.S. Appl. No. 63/177,135, filed Nov. 13, 2001, Reddy, Chitranjan.28U.S. Office Action re Supplemental Notice of Allowability (SNOA) dated Oct. 27, 2009, re U.S. Appl. No. 11/767,983, filed Jun. 25, 2007. 10 pages.29Wang et al., 2001, "A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique," IEEE Journal of Solid-State Circuits, 36:648-657.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8738852 *Aug 31, 2011May 27, 2014Nvidia CorporationMemory controller and a dynamic random access memory interfaceUS20130054884 *Feb 28, 2013Alok GuptaMemory controller and a dynamic random access memory interface* Cited by examinerClassifications U.S. Classification345/542, 345/520, 345/519International ClassificationG09G5/393, G06F13/14, G06F15/167, G09G5/36, G06T1/60Cooperative ClassificationG09G2352/00, G06T1/60, G09G2360/125, G09G5/363, G09G5/393European ClassificationG09G5/36C, G09G5/393, G06T1/60Legal EventsDateCodeEventDescriptionOct 25, 2010ASAssignmentOwner name: RAMBUS INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PEREGO, RICHARD E., MR.;REEL/FRAME:025190/0512Effective date: 20010514Dec 7, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services