Source: http://www.google.com/patents/US20040150118?dq=5998925
Timestamp: 2016-05-31 00:34:10
Document Index: 686547579

Matched Legal Cases: ['art 40', 'art 40', 'art 40', 'art 40', 'art 40', 'art 40', 'art 40', 'art 40', 'art 40', 'art 40', 'art 40', 'art 40', 'art 40', 'arts 50', 'arts 50', 'arts 50', 'art 40', 'art 40', 'art 40', 'art 34', 'arts 34', 'arts 34', 'arts 34', 'arts 34', 'arts 34', 'arts 34', 'art 40', 'art 40', 'art 40', 'art 40', 'art 40', 'arts 34', 'art 40', 'art 40']

Patent US20040150118 - Warp-suppressed semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area...http://www.google.com/patents/US20040150118?utm_source=gb-gplus-sharePatent US20040150118 - Warp-suppressed semiconductor deviceAdvanced Patent SearchPublication numberUS20040150118 A1Publication typeApplicationApplication numberUS 10/763,554Publication dateAug 5, 2004Filing dateJan 23, 2004Priority dateFeb 3, 2003Also published asUS7728440, US8324718, US20100230797Publication number10763554, 763554, US 2004/0150118 A1, US 2004/150118 A1, US 20040150118 A1, US 20040150118A1, US 2004150118 A1, US 2004150118A1, US-A1-20040150118, US-A1-2004150118, US2004/0150118A1, US2004/150118A1, US20040150118 A1, US20040150118A1, US2004150118 A1, US2004150118A1InventorsHirokazu HondaOriginal AssigneeNec Electronics CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (43), Referenced by (90), Classifications (45), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetWarp-suppressed semiconductor device
US 20040150118 A1Abstract
A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first -resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region. Images(23) Claims(19)
What is claimed is: 1. A semiconductor device comprising: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the semiconductor chip and the mounting substrate; a stiffener surrounding the semiconductor chip; and a second resin filling a space between the semiconductor chip and the stiffener in contact with the first resin, the first resin being different in a thermal expansion coefficient from the second resin. 2. The semiconductor device as claimed in claim 1, wherein a thermal expansion coefficient of the second resin is smaller than a thermal expansion coefficient of the first resin. 3. The semiconductor device as claimed in claim 2, wherein the stiffener is adhered to the mounting substrate with a resin the same as the second resin. 4. The semiconductor device as claimed in claim 1, wherein the first resin includes an underfill part filling the gap between the semiconductor chip and the mounting substrate, and a fillet part extended from a region of the semiconductor chip. 5. The semiconductor device as claimed in claim 1, wherein the stiffener is adhered to the mounting substrate with a first adhesive being larger in a thermal expansion coefficient than the second resin. 6. The semiconductor device as claimed in claim 4, wherein the second resin is in contact with inner walls of the stiffener, the fillet part, the mounting substrate and each of side faces of the semiconductor chip. 7. A semiconductor device comprising: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the semiconductor chip and the mounting substrate; a stiffener surrounding the semiconductor chip; a second resin filling a space between the semiconductor chip and the stiffener in contact with the first resin, the first resin being different in a thermal expansion coefficient from the second resin; and a lid for covering the stiffener and the semiconductor chip, wherein the lid is bonded to the stiffener and a backside of the semiconductor chip with a second adhesive. 8. The semiconductor device as claimed in claim 7, wherein the second resin is in contact with an inner wall of the lid. 9. The semiconductor device as claimed in claim 1, wherein an elastic modulus of the second resin is larger than an elastic modulus of the first resin. 10. The semiconductor device as claimed in claim 2, wherein the stiffener has a plurality of concave portions facing the mounting substrate. 11. The semiconductor device as claimed in claim 10, wherein a planer shape of the stiffener is rectangular, and the concave portion is formed on each corner of the stiffener. 12. The semiconductor device as claimed in claim 10, wherein each of concave portions is filled with a resin the same as the second resin. 13. The semiconductor device as claimed in claim 2, wherein the stiffener end surface facing the mounting substrate is convexo-concave, and a gap between the mounting substrate and concave portion of the stiffener end surface is filled with a first adhesive. 14. The semiconductor device as claimed in claim 2, wherein the stiffener end surface facing the mounting substrate is convexo-concave, and a gap between the mounting substrate and concave portion of the stiffener end surface is filled with a resin the same as the second resin. 15. The semiconductor device as claimed in claim 2, wherein the stiffener end surface facing the mounting substrate is convexo-concave, the mounting substrate includes a first metal layer in a region facing the stiffener, the stiffener includes a second metal layer on a surface of a convex portion, and the mounting substrate and the convex portion of the stiffener are connected to each other by a low-melting alloy. 16. The semiconductor device as claimed in claim 1, wherein the stiffener is made of a material selected from the group consisting of Cu, SUS, Al, alumina, silicon, aluminum nitride, and resin. 17. The semiconductor device as claimed in claim 1, wherein each of the first resin and the second resin essentially contains a resin selected from a group consisting of epoxy, polyolefin, silicon, cyanate ester, polyimide, polynorbornene resins. 18. The semiconductor device as claimed in claim 1, wherein a gap member different from the first adhesive is partially arranged between the mounting substrate and the stiffener. 19. The semiconductor device as claimed in claim 18, wherein the gap member is made of a low-melting alloy.
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to a semiconductor device of, e.g., a ball grid array (BGA) type, in which a semiconductor chip is connected, through flip chip bonding, to a mounting substrate manufactured by the same method as that for an organic printed wiring board, and a method for manufacturing the same. [0003] 2. Description of the Related Art [0004] Generally, amounting substrate to which the semiconductor chip is connected through flip chip bonding is manufactured by the same method as that for an organic printed wiring board. The mounting substrate is formed of wiring layers the number of which ranges from two to a dozen or so depending on purposes. However, the thickness of the mounting substrate is about 0.5 to 2.0 m even if there are a dozen wiring layers or so. Accordingly, the mounting substrate is very vulnerable to external force or stress caused by a difference in coefficients of thermal expansion between materials of different kinds and is easily warped. Outside dimensions of the mounting substrate greatly vary depending on a size of a semiconductor chip to be mounted on the mounting substrate, the number of external terminals, and a way of arrangement of the external terminals, e.g., a full grid or a peripheral grid. To take an example, because of lighter weight and thinner formation requirements, the outside dimensions of the mounting substrate are 45 to 50 mm□ and the thickness thereof is about 1.0 to 2.5 mm in a case where a semiconductor chip is about 17 to 20 mm□, the number of pad electrodes of the chip is 2000 to 3000, and the way of arrangement of 1800 to 2000 external terminals (bumps) necessary to be disposed on the mounting substrate is a full grid. [0005] First, a conventional semiconductor device will be described with reference to Japanese Patent Laid-Open Publication No. 2000-323624 and FIGS. 14a and 14 b. FIG. 14a is a plan view of a conventional semiconductor device 200, described in, e.g., Japanese Patent Laid-Open Publication No. 2000-323624, in a state in which a lid 231 is removed, and FIG. 14b is a sectional view taken along the line E-E′ of FIG. 14a in a state in which the lid 231 is attached. In this semiconductor device 200, a semiconductor chip 220 is connected to a mounting substrate 210 with a thickness of about 1 mm through flip chip bonding, and a gap therebetween is filled with an underfill resin 240 to be cured. A stiffener 230 is bonded to the mounting substrate 210 so as to surround the semiconductor chip 220, and the lid 231 is fixed to a backside of the semiconductor chip 220 and to an end surface of the stiffener 230 with a conductive adhesive 243. In addition, a space 247 is formed between the stiffener 230 and side faces of the semiconductor chip 220. [0006] Next, an outline of a method for manufacturing the conventional semiconductor device 200 will be described with reference to FIGS. 15a to 15 g. First, the above-described mounting substrate 210, the semiconductor chip 220, the stiffener 230, the underfill resin 240, an epoxy resin adhesive 242, the conductive adhesive 243, and the lid 231 are prepared, and a wiring board diagram of FIG. 15a is set on a stage (not shown) of a screen printer or of a dispenser. Next, the epoxy resin adhesive 242 with a thermal expansion coefficient of 16 to 22 ppm is applied to a peripheral portion of the mounting substrate 210 by means of the screen printer or the dispenser. Thereafter, the stiffener 230 is mounted thereon, and the epoxy resin adhesive 242 is cured at a predetermined temperature (around 100 to 160� C.) (FIG. 15b). Subsequently, bump electrodes 222 formed on pads 221 of the semiconductor chip 220 and lands 211 of the mounting semiconductor substrate 210 are aligned with each other by a flip chip mounter (not shown), and then melted to be connected at a temperature of around 250� C. in the case of a low-melting alloy, e.g., Pb-free solder (FIG. 15c). [0007] In other methods, as a method of connecting the pads 221 of the semiconductor chip 220 and the lands 211 of the mounting substrate 210, there is a method in which materials of joined surfaces include Au and Al, and Au and Au, respectively, and the pads 221 and the lands 211 are connected by applying an ultrasonic-wave while heating them. In this case, real curing of the epoxy resin adhesive 242 to bond the stiffener 230 to the mounting substrate 210 is carried out in a separate step. Next, in order to secure adhesive strength of the mounting substrate 210 and the semiconductor chip 220, a gap of about several 100 μm therebetween is filled with the underfill resin 240 which has a thermal expansion coefficient of about 32 ppm and flowability, using the dispenser or the like by utilizing capillary. Then, the underfill resin 240 is cured at a temperature of about 100� C. (FIG. 15d) [0008] Next, the conductive adhesive 243 with a thermal expansion coefficient of 16 to 22 ppm is attached onto the end surface of the stiffener 230 and onto the backside of the semiconductor chip 220 by coating or a printing method (FIG. 15e). Subsequently, the lid 231 is aligned with the stiffener 230 and mounted thereon with applying a proper load. Further, in this state, the conductive adhesive 243 is cured at a temperature of about 150 to 170� C. (FIG. 15f). A batch-processing method in an oven or a general method of continuously putting materials into a belt furnace to cure the materials is applicable for the curing method. [0009] Lastly, solder bumps 213, external terminals, are bonded to the lands 212 of the mounting substrate 210 by a general method (FIG. 15g). In the conventional semiconductor device 200, in a state at a room temperature and immediately after the solder bumps 213 are bonded to the lands 212 of the mounting substrate 210, as shown in FIG. 16a for example, a portion of the mounting substrate 210 opposite the semiconductor chip 220 is pulled to a semiconductor chip 220 side by about 100 μm to be convex-shaped on a chip mounting surface side. [0010] [0010]FIG. 16a is a view schematically showing a state of warpage in the mounting substrate 210 when the semiconductor device 200 is at a room temperature of 20� C., and FIGS. 16b and 16 c are views schematically showing state of warpage in the mounting substrate 210 when the semiconductor device 200 is at a low temperature of −45� C. and at a high temperature of 150� C., respectively. As shown in FIG. 16a, the conventional semiconductor device 200 is in a state of being convex to the chip side by about 100 μm at the room temperature of 20� C. When the semiconductor device 200 is cooled to −45� C. from this state, the amount of warpage is increase to 180 μm as shown in FIG. 16b. When the temperature is once returned to the room temperature, and then the semiconductor device 200 is heated to 150� C., the amount of warpage is reduced to about 50 μm as shown in FIG. 16c. Accordingly, in the conventional semiconductor device 200, if a temperature cycling between the low temperature state of −45� C. and the high temperature state of 150� C. is repeated several hundred to several thousand times, cracks may occur in the bump electrodes 222 which join the pads 221 of the semiconductor chip 220 to the lands 211 of the mounting substrate 210, and detachment may also occur in joined interfaces. [0011] A reason for the occurrence of cracks in the solder bumps and for the detachment in the joined interfaces between the pads and the lands can be presumed as follows. FIG. 17 is an enlarged schematic view of the vicinity of one of the bump electrodes 222 to explain the reason. Hereinafter, the description will be made with reference to FIG. 17. Stress with an in-plane direction generated by the thermal expansion coefficient difference between the mounting substrate 210 and the semiconductor chip 220 is absorbed with the underfill resin 240 filled into the gap. However, the contraction of the underfill resin 240 brings a state in which the bump electrode 222 is pulled toward the semiconductor chip 220, and at the same time force in a vertical direction to the surface of the semiconductor chip 220 is applied. If the temperature cycling is repeated in this state, the mounting substrate 210 including the semiconductor chip 220 repeats states in a convex shape and in a flat shape, and thus stresses of tension and compression are repeated in the connected portion of the bump electrode 222 with the pad 221 or in the connected portion of the mounting substrate 210 with the land 211. Consequently, it can be presumed that a crack 217 occurs in the bump electrode 222 and detachment 218 occurs in the joined interface, thus leading to destruction. [0012] In the semiconductor device 200 manufactured by the aforementioned method, the pads 221 of the semiconductor chip 220 with a thickness of 0.7 mm are connected to the wiring electrodes 211 of the resin mounting substrate 210 with a thickness of 0.5 to 2.0 mm through the bump electrodes 222, and secured by the underfill resin 240 for reinforcing the connected portions. In addition, the stiffener 230 with a thickness of about 0.5 to 1.0 mm is bonded to the resin mounting substrate 210 so as to surround the semiconductor chip 220, thereby securing the flatness and the strength of the resin mounting substrate 210. In this state, the lid 243 with a thickness of 0.5 to 1.0 mm for protecting the semiconductor chip 220 is mounted, thus configuring the semiconductor device 200. [0013] The warpage in the substrate as shown in FIG. 16a occurs in the mounting substrate 210 of the semiconductor device 200 constituted of the aforementioned components at the room temperature. This view is a sectional view taken along the line E-E′ of FIG. 14a. A portion directly facing the semiconductor chip 220 is pulled toward the semiconductor chip 220 by the contraction of the underfill resin 240 to be in a convex state on the chip mounting surface side. A portion directly bonded to the stiffener 230 is also deformed to be slightly convex on the chip mounting surface side. In other words, deformation of two-stage shapes occurs. [0014] If the thermal expansion coefficient of the underfill resin 240 is reduced to about 16 to 22 ppm, the phenomenon that the portion directly facing the semiconductor chip 220 is pulled to be convex may be suppressed to a certain extent. However, it is difficult to greatly reduce the amount of warpage in the mounting substrate. To reduce the thermal expansion coefficient of the underfill resin 240, a large amount of silica filler or the like is generally mixed. However, this causes an increase in the viscosity of the resin. Consequently, voids are generated in the underfill resin 240 in a region where the mounting substrate 210 and the semiconductor chip 220 face each other, and thereby the detachment phenomenon easily occurs. Therefore, it was difficult to reduce the thermal expansion coefficient to 32 ppm or lower. That is, there is a trade-off relation between the thermal expansion coefficient of the underfill resin 240 and the viscosity thereof, in which filler such as silica or alumina only needs to be mixed by a large amount in order to reduce the thermal expansion coefficient, but a larger amount of the mixed filler causes a higher viscosity. [0015] Japanese Patent Laid-Open Publication No. 2000-260820 discloses a semiconductor device configured in such a manner that a semiconductor chip is connected to a wiring pattern surface of a mounting substrate; a first sealant (underfill resin) is injected into a gap therebetween at 60 to 120� C. and then cured at 140 to 170� C.; and thereafter side faces of the chip are sealed by a second sealant (well-known fillet material). In this semiconductor device, the first sealant is present in the gap between the chip and the substrate, and the second sealant is formed in a fillet shape on the side faces of the semiconductor chip. [0016] Furthermore, Japanese Patent Laid-Open Publication No. 2000-349203 discloses a semiconductor device configured in such a manner that a semiconductor chip is connected to an interposer substrate through flip chip bonding; a gap between the interposer substrate and the semiconductor chip, and a corresponding portion to the aforementioned stiffener are integrally filled with resin by transfer molding; and a heat spreader (equivalent to the lid) is mounted thereon. [0017] It has now been discovered that, in the conventional semiconductor device, in order to prevent the destruction of the bumps for solder-connecting the materials different in coefficients of thermal expansion, such as the mounting substrate made of an organic resin substrate and the semiconductor chip including, e.g., silicon, a gap between the semiconductor chip and the mounting substrate is filled with the underfill resin with a high thermal expansion coefficient and with a high elastic modulus, thereby reducing stress caused by the difference in thermal expansion coefficients therebetween. However, because of great differences in thermal expansion coefficient and elastic modulus between the materials, at the end of the manufacturing process, the region where the mounting substrate and the semiconductor chip face each other through the underfill resin is in a warped state due to the occurrence of stress to be pulled to the semiconductor chip side. Accordingly, an increased amount of warpage causes a problem that a solder connection failure easily occurs in a warped portion when the semiconductor device is mounted on a circuit board or the like by soldering. Additionally, as for the semiconductor device itself, there is no problem in a state of a room temperature with small fluctuation in a range of about 5� C. to 35� C. However, if a low temperature and a high temperature is repeated like the temperature cycling, there is a problem that the warpage in the mounting substrate causes cracks in the solder bumps for connecting the pads of the semiconductor chip to the lands of the mounting substrate, and detachment in the joined interfaces. [0018] Furthermore, for example, even in the structure in which the first sealant is present in the gap between the chip and the substrate, and the second sealant is formed in a fillet shape on the side faces, it is impossible to completely prevent the contraction of the first sealant and the substrate directly facing the chip. Further, in the case of the structure in which the sealing resin with a large filler content is injected as the underfill resin to fill a gap between the interposer substrate and the semiconductor chip by transfer molding, because of the high viscosity of the resin, voids are easily generated in the gap between the interposer substrate and the semiconductor chip, thereby causing problems leading to loss of reliability, such as the occurrence of cracks and detachment. SUMMARY OF THE INVENTION [0019] An object of the present invention is to provide a semiconductor device including a semiconductor chip mounted on a mounting substrate through flip chip bonding, in which, in a state after sealing, the amount of warpage in the mounting substrate is in a range which does not hinder solder-mounting of the semiconductor device on a mounting board such as a circuit board; in a temperature cycling test, no destruction is caused by the occurrence of cracks, detachment and the like in solder bumps and the like which are connecting members between the semiconductor chip and the mounting substrate; and no cracks and the like occur in the mounting substrate. [0020] In order to achieve the above object, a semiconductor device of the present invention includes: a semiconductor chip mounted on a mounting substrate with a gap between the chip and the mounting substrate; a first resin filling the gap between the semiconductor chip and the mounting substrate; a stiffener surrounding the semiconductor chip; and a second resin filling a space between the semiconductor chip and the stiffener in contact with the first resin, the first resin being different in a thermal expansion coefficient from the second resin. More specifically, the semiconductor device includes the semiconductor chip provided with a plurality of external connection electrodes (hereinafter, referred to as chip electrodes) on one main surface, and the mounting substrate provided with electrodes (hereinafter, referred to as internal land electrodes) corresponding to the chip electrodes on a first surface. The semiconductor chip is mounted on the mounting substrate by connecting the chip electrodes and the corresponding internal land electrodes through conductive electrodes such as solder bumps (hereinafter, referred to as connection member) while allowing the chip electrodes and the internal land electrodes to face each other. Further, the semiconductor device includes the first resin filling the gap between the semiconductor chip and the mounting substrate, the stiffener surrounding the semiconductor chip, and the second resin filling the space between the semiconductor chip and the stiffener in contact with the first resin, and the first resin is different in the thermal expansion coefficient from the second resin. Note that, the first resin may include an underfill part filling the gap between the semiconductor chip and the mounting substrate, and the fillet part extended from the semiconductor chip region. The thermal expansion coefficient of the second resin may be preferably smaller than that of the first resin. The stiffener may be adhered to the mounting substrate with a resin the same as the second resin or a first adhesive being larger in a thermal expansion coefficient than the second resin. [0021] According to the semiconductor device thus configured, by selecting the first resin and the second resin so that a thermal expansion coefficient of the second resin is smaller than that of the first resin, it is possible to relax the contraction/expansion stress of the first resin caused by temperature changes during and after heat curing. Accordingly, warpage in the mounting substrate can be suppressed even if a material with low viscosity but with a slightly high thermal expansion coefficient is used for the first resin in order to prevent the occurrence of voids in the underfill part and to suppress detachment and destruction of the connection members. Moreover, even in a temperature cycling test in which a low temperature state and a high temperature state are repeated by turns, stress caused by the contraction/expansion of the first resin is limited to a minimum. Thus, it is possible to prevent the occurrence of cracks, detachment and destruction in the connection members such as solder bumps, and detachment of the chip electrodes and the internal land electrodes. More preferably, the thermal expansion coefficient of the second resin is smaller than that of the mounting substrate. [0022] A method for manufacturing a semiconductor device of the present invention includes the steps of: bonding a stiffener to a mounting substrate; connecting a semiconductor chip to the mounting substrate; filling a gap with a first resin and curing it; filling a space between the semiconductor chip and the stiffener with a second resin and curing it; attaching a lid; and connecting solder bumps. In this method, at least the step of bonding the stiffener to the mounting substrate is set as a first step, and the step of connecting the semiconductor chip to the mounting substrate is set as a second step. In this case, preferably, the resin curing in the steps of bonding the stiffener to the mounting substrate, of connecting the semiconductor chip to the mounting substrate, of filling a gap with the first resin and curing it, and of filling a space with the second resin and curing it, is a process of semi-curing the resins, and all the resins are completely cured simultaneously in a process of curing in the step of attaching the lid. [0023] According to this manufacturing method, since the strength of the mounting substrate can be reinforced, it is possible to improve handling performance during the manufacturing processes and to suppress warpage in the mounting substrate. Moreover, since the adhesives and the resins are temporarily cured in the respective steps to become in a semi-cured state, and subjected to real curing at the end to be completely cured, it is possible to suppress warpage in the mounting substrate after the manufacture to a minimum. [0024] Further, another method for manufacturing a semiconductor device of the present invention includes the steps of: bonding a stiffener to a mounting substrate; connecting a semiconductor chip to the mounting substrate; filling a gap with a first resin and curing it; attaching a lid; filling a space, which is surrounded by the lid, side faces of the semiconductor chip, the stiffener and the mounting substrate, with a second resin and curing it; and connecting solder bumps. In this method, the step of filling the space with the second resin and curing it is executed after the step of attaching the lid. [0025] According to this manufacturing method, since the second resin is injected and cured after the lid is attached, the space can be completely filled with the second resin without generating any empty space in the vicinity of the lid, and thus deformation of the mounting substrate can be suppressed.
BRIEF DESCRIPTION OF THE DRAWINGS [0026] The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: [0027] [0027]FIG. 1a is a plan view of a semiconductor device of a first embodiment of the present invention, in a state in which a lid is removed; [0028] [0028]FIG. 1b is a sectional view taken along the line A1-A1′ of FIG. 1a, in a state in which the lid is attached to the semiconductor device of the first embodiment; [0029] [0029]FIG. 2 is a sectional view of a semiconductor device of a second embodiment of the present invention, equivalent to FIG. 1b of the first embodiment; [0030] [0030]FIG. 3a is a plan view of a semiconductor device of a third embodiment of the present invention, in a state in which a lid is removed; [0031] [0031]FIG. 3b is a sectional view taken along the line A2-A2′ of FIG. 3a, in a state in which the lid is attached to the semiconductor device of the third embodiment; [0032] [0032]FIG. 3c is a partially enlarged sectional view of a bonded portion of a mounting substrate with a stiffener in FIG. 3b; [0033] [0033]FIG. 4 is a sectional view of a semiconductor device of a fourth embodiment of the present invention, equivalent to FIG. 1b of the first embodiment; [0034] [0034]FIG. 5a is a plan view of a semiconductor device of a fifth embodiment of the present invention, in a state in which a lid is removed; [0035] [0035]FIG. 5b is a partially sectional view taken along the line B-B′ of FIG. 5a, in a state in which the lid is attached to the semiconductor device of the fifth embodiment; [0036] [0036]FIG. 5c is a sectional view taken along the line C-C′ of FIG. 5a, in a state in which the lid is attached to the semiconductor device of the fifth embodiment; [0037] [0037]FIG. 6 is a sectional view of a semiconductor device of a sixth embodiment of the present invention, equivalent to FIG. 1b of the first embodiment; [0038] [0038]FIG. 7 is a sectional view of a semiconductor device of a seventh embodiment of the present invention, equivalent to FIG. 1b of the first embodiment; [0039] [0039]FIGS. 8a to 8 h are sectional views for respective steps, taken along the line A1-A1′ of FIG. 1a, for explaining a method for manufacturing the semiconductor device of the first embodiment; [0040] [0040]FIGS. 9a to 9 i are views for explaining a method for manufacturing the semiconductor device of the fifth embodiment, wherein FIGS. 9a to 9 f are sectional views for respective steps, taken along the line A2-A2′ of FIG. 5a, FIG. 9g is sectional view taken along the line C-C′ of FIG. 5a, FIG. 9h is a plan view for a heating pressing-in nozzle brought into contact with two of the groove parts formed in the corners of the stiffener to which the lid is connected, and FIG. 9i is a sectional view taken along the line D-D′ of FIG. 9h; [0041] [0041]FIGS. 10a to 10 g are sectional views for respective steps, taken along the line A1-A1′ of FIG. 1a, for explaining a method for manufacturing the semiconductor device of the sixth embodiment; [0042] [0042]FIGS. 11a to 11 g are sectional views for respective steps, taken along the line A1-A1′ of FIG. 1a, for explaining a method for manufacturing the semiconductor device of the seventh embodiment; [0043] [0043]FIGS. 12a to 12 e are views, each schematically showing a warped state of a mounting substrate in the semiconductor device of each embodiment of the present invention; [0044] [0044]FIG. 12f is a view schematically showing a warped state of a mounting substrate of a conventional semiconductor device for comparison; [0045] [0045]FIG. 13 is a graph showing results of actually measuring the amount of warpage in a mounting substrate of a semiconductor device of the present invention when the temperature of the semiconductor device is changed; [0046] [0046]FIG. 14a is a plan view of a conventional semiconductor device in a state in which a lid is removed; [0047] [0047]FIG. 14b is a sectional view taken along the line E-E′ of FIG. 14a, in a state in which the lid is attached to the conventional semiconductor device; [0048] [0048]FIGS. 15a to 15 g are sectional views for respective steps, taken along the line E-E′ of FIG. 14a, for explaining a method for manufacturing the conventional semiconductor device; [0049] [0049]FIGS. 16a to 16 c are views, each schematically showing a warped state of the conventional semiconductor device in a temperature cycling test; and [0050] [0050]FIG. 17 is an enlarged sectional view around a bump electrode of the conventional semiconductor device.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0051] The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teaching of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. [0052] (First Embodiment) [0053] As shown in FIGS. 1a and 1 b, a semiconductor device 1 of a first embodiment includes: a mounting substrate 10; a semiconductor chip 20 mounted on a first surface of the substrate 10 through flip chip bonding; a first resin 40 filling a gap between the substrate 10 and the chip 20; a frame-shaped stiffener 30 surrounding the chip 20; a first adhesive 42 for bonding a first end surface of the stiffener 30 to the substrate 10; a lid 31 for covering the stiffener 30 and an area surrounded by the stiffener 30; a second adhesive 43 for bonding the lid 31 to a backside of the chip 20 and to a second end surface opposite the first end surface of the stiffener 30; and a second resin 41 filling a space between the stiffener 30 and the chip 20 in contact with the first resin 40. The first resin 40 includes an underfill part 40 a filling a gap between the chip 20 and the substrate 10, and a fillet part 40 b extended from a region where the chip 20 and the substrate 10 face each other. Detailed description will be made below. [0054] The chip 20 includes a plurality of chip electrodes 21 for external connection on a main surface thereof. The substrate 10 includes internal land electrodes 11 formed in corresponding positions to the chip electrodes 21 on the first surface, external land electrodes 12 formed on a second surface opposite the first surface, an in-substrate wiring 15 for connecting the corresponding internal and external electrodes 11 and 12 to each other, and, e.g., solder bumps 13 bonded to the external land electrodes 12. The solder bumps 13 serve as eternal terminals of the semiconductor device 1. [0055] The internal land electrodes 11 of the substrate 10 and the corresponding chip electrodes 21 of the chip 20 are connected to each other through bump electrodes 22 made of conductive material. The underfill part 40 a filling a gap between the chip 20 and the substrate 10 relaxes stress on the connected portions. [0056] The chip 20 is mounted on a center portion of the substrate 10. The stiffener 30 is bonded to a peripheral portion of the first surface of the substrate 10 with the first adhesive 42 so as to surround the 20. In the semiconductor device 1, the stiffener 30 reduces the warpage in the substrate 10 caused by thermal or mechanical stress during manufacturing processes, and at the same time reinforces the strength of the semiconductor device 1. [0057] The second resin 41 fills the space surrounded by the substrate 10, the inner walls of the stiffener 30, the side walls (or faces) of the chip 20 and the lid 31 in contact with the fillet part 40 b, and all the space is almost eliminated. The thermal expansion coefficient of the second resin 41, more specifically, the linear expansion coefficient thereof is smaller than at least that of the first resin 40. According to such a semiconductor device 1, since the space between the chip 20 and the stiffener 30 is filled with the second resin 41 smaller in thermal expansion coefficient than at least the first resin 40 and the second resin 41 is cured, it is possible to suppress warpage in the substrate 10 due to the expansion/contraction of the first resin 40 at the high/low temperature states. Note that the warpage in the substrate 10 can be further reduced by setting the thermal expansion coefficient of the second resin 41 smaller than those of the first adhesive 42, the second adhesive 43, the substrate 10, and the like. [0058] Here, Table 1 shows examples of characteristics of the used resins such as the first resin 40, the second resin 41 and the like. TABLE 1 Characteristics of each resin Thermal expansion Elastic modulus coefficient (ppm) (GPa) First adhesive 16-22 11-12 First resin 30-32 9-10 Second resin 8-16 11-28 Second adhesive 50-100 3-9 [0059] Next, referring to FIGS. 8a to 8 h, a method for manufacturing the semiconductor device 1 of the first embodiment will be described in the order of steps. First, the mounting substrate 10 is prepared. On the first surface of the substrate 10, the internal land electrodes 11, which are formed in corresponding positions to the chip electrodes 21 of the chip 20 to be mounted, and the external land electrodes 12, which are formed on the second surface opposite the first surface, are provided. The corresponding internal and external land electrodes 11 and 12 are connected to each other through the in-substrate wiring 15 (FIG. 8a). [0060] Second, the first adhesive 42 with a thermal expansion coefficient of 16 to 22 ppm and with an elastic modulus of 11 to 12 GPa is applied to the peripheral portion of the substrate 10 in a shape so as to coincide with the shape of the frame-shaped stiffener 30, which is also prepared beforehand. Thereafter, the stiffener 30 is aligned with the portion coated with the first adhesive 42 and mounted thereon so that the first end surface is brought into contact with the first adhesive 42, which is then temporarily cured at around 125� C. for about 15 minutes (FIG. 8b). In this state, the stiffener 30 is bonded to the mounting substrate 10, but the first adhesive 42 has not completely set yet. Note that the first adhesive 42 essentially contains a resin material selected from the group consisting of, e.g., epoxy, polyolefin, silicon, cyanate ester, polyimide, and polynorbornene resins, and is adjusted by mixing a proper amount of an inorganic filter so as to set the thermal expansion coefficient and the elastic modulus to desired values. A material of the stiffener 30 can be selected from the group consisting of Cu, SUS (ferrite stainless steel), alumina, silicon, aluminum nitride, and epoxy resin. [0061] Third, the chip 20 is connected to the substrate through flip chip bonding. More specifically, the chip 20 in which the bump electrodes 22 are bonded onto the chip electrodes 21 is positioned and mounted on the internal land electrodes 11 so that the bump electrodes 22 are brought into contact with the corresponding internal land electrodes 11, and heated to around 250� C. in, e.g., a nitrogen atmosphere, to be connected to the internal land electrodes 11 of the substrate 10 (FIG. 8c). [0062] Next, the first resin 40 is injected into a gap between the chip 20 and the substrate 10 with a dispenser or the like by a dropping method and fills that. Thereafter, the first resin 40 is temporarily cured at around 100� C. for about 10 minutes (FIG. 8d). In this state, the first resin 40 also has not completely set yet. The first resin 40 is prepared by adjusting, e.g., an epoxy resin so that the thermal expansion coefficient thereof is set to about 32 ppm and the elastic modulus thereof to about 9 GPa. With these characteristics of the first resin 40, the flowability thereof is 1000 to 40000 centipoises (CPS), and the first resin 40 can be injected to fill the gap between the chip 20 and the substrate 10, so that the underfill part 40 a can be formed without generating any voids. At this time, the first resin 40 forms not only the underfill part 40 a in the gap between the chip 20 and the substrate 10 but also the fillet part 40 b extended from the underfill part 40 a to a surrounding area of the chip 20. However, the fillet part 40 b does not reach the stiffener 30, and at this point in time, the first surface of the substrate 10 is exposed between the fillet part 40 b and the stiffener 30. [0063] Subsequently, the space surrounded by the inner walls of the stiffener 30, the sidewalls of the chip 20, the first surface of the substrate 10 and the fillet part 40 b is filled with the second resin 41, which is then temporarily cured at around 150� C. for about 30 minutes (FIG. 8e). In this state, the second resin 41 also has not completely set yet. For the second resin 41, an epoxy resin smaller in thermal expansion coefficient than the first resin 40, for example, an epoxy resin with a thermal expansion coefficient of 8 to 16 ppm and with an elastic modulus of 11 to 28 GPa can be used. It is more preferable if the thermal expansion coefficient of the second resin 41 can be set smaller than that of the substrate 10. As a filling method, a method of injection, transfer molding, liquid resin dropping or the like can be used. [0064] Next, the second adhesive 43 is applied onto the backside of the chip 20 and onto the second end surface of the stiffener 30 (FIG. 8f). Thereafter, the lid 31 is mounted to cover the entire area surrounded by the stiffener 30. A proper load is applied on the lid 31, and the temperature of the entire device is slowly increased to about 175� C. Further maintaining it at about 175� C. for about 60 minutes, real curing is carried out (FIG. 8g). Thus, all of the first resin 40, the second resin 41, the first adhesive 42 and the second adhesive 43 are completely cured, and the lid 31 is completely bonded. Note that, for the second adhesive 43, an epoxy resin with a thermal expansion coefficient of about 50 to 100 ppm can be used, for example. In addition, it is more preferable to mix a proper amount of Ag or Cu powder as inorganic filler to the second adhesive 43 to improve the thermal conductivity of the second adhesive 43. [0065] Finally, the solder bumps 13, which are external terminals, are bonded to the external land electrodes 12 of the substrate 10 by a general method, thus completing the semiconductor device 1 (FIG. 8h). [0066] Note that, for all of the main component resin materials of the first resin 40, of the second resin 41, of the first adhesive 42 and of the second adhesive 43, the same epoxy resin, for example, can be used. The each resin may be adjusted to optimal characteristics in accordance with required characteristics thereof, such as a thermal expansion coefficient, by changing an inorganic filler content added to the main component resin. [0067] (Second Embodiment) [0068] Next, a second embodiment will be described with reference to FIG. 2. Note that a method for manufacturing a semiconductor device 1 a of the second embodiment is similar to that for the semiconductor device 1 of the first embodiment. A configuration of the semiconductor device 1 a is almost the same as that of the semiconductor device 1. The difference between the semiconductor device la and the semiconductor device 1 is that a resin the same as the second resin 41 is used as a first adhesive 42 a for bonding the stiffener 30 to the substrate 10. According to this semiconductor device 1 a, by using the resin the same as the second resin 41 with a thermal expansion coefficient of about 8 to 16 ppm and with an elastic modulus of 11 to 28 GPa for the first adhesive 42 a for bonding the stiffener 30, the contraction in a portion of the substrate 10 directly facing the chip 20 can be reduced more, and thus it is possible to suppress the warpage in the substrate 10. [0069] (Third Embodiment) [0070] Next, a third embodiment will be described with reference to FIGS. 3a to 3 c. Referring to FIGS. 3a to 3 c, a semiconductor device 1 b of the third embodiment includes: amounting substrate 10; a semiconductor chip 20 mounted on a first surface of the substrate 10 through flip chip bonding; a first resin 40 filling a gap between the substrate 10 and the chip 20; a frame-shaped stiffener 32 surrounding the chip 20; a first adhesive 42 for bonding a first end surface of the stiffener 32 to the substrate 10; a lid 31 for covering the stiffener 32 and an area surrounded by the stiffener 32; a second adhesive 43 for bonding the lid 31 to a backside of the chip 20 and to a second end surface opposite the first end surface of the stiffener 32; and a second resin 41 filling a space surrounded by the stiffener 32, side faces of the chip 20 and the substrate 10 in contact with the first resin 40. The first resin 40 includes an underfill part 40 a filling a gap between the chip 20 and the substrate 10, and a fillet part 40 b extended from a region where the chip 20 and the substrate 10 face each other. A configuration of the semiconductor device 1 b of the third embodiment is almost the same as that of the semiconductor device 1. The difference between the semiconductor device 1 b and the semiconductor device 1 is that ruggedness is present in a gap between the first end surface of the stiffener 32 and the substrate 10. Specifically, the entire first end surface of the stiffener 30 of the semiconductor device 1 is planar, while the first end surface of the stiffener 32 is processed, e.g., in a spiral or a grid shape of grooves, or in a shape in which convex parts 50 and concave parts are alternately formed. In this case, a depth of the grooves or of the concave parts can be set as occasion demands, but preferably set to about 50 to 200 μm which is approximately the same to the gap between the chip 20 and the substrate 10. A material of the stiffener 32 can be selected from the group consisting of Cu, SUS (ferrite stainless steel), alumina, silicon, aluminum nitride, and epoxy resin. The stiffener 32 is bonded to the substrate 10 by filling the concave parts in the first end surface with the first adhesive 42. Note that, in this case as well, the concave parts of the first end surface may be filled with a resin the same as the second resin 41 in place of the first adhesive 42. [0071] An operation feature at room temperature and temperature cycling according to the structure of the semiconductor device 1 b, is that the warpage in the substrate 10 by the stiffener 32 is first suppressed by approximating a bonding state between the substrate 10 and the stiffener 32 to that between the chip 20 and the substrate 10. Further, the first resin 40 fills the gap between the chip 20 and the substrate 10 to which the chip is connected, and then the first resin 40 is cured. In addition, the second resin 41 fills the space around the chip 20 so that the second resin 41 occupies the almost entire space, and then the second resin 41 is cured. Up-and-down movements are suppressed by the second resin 41 filling the space between the sidewalls of the chip 20 and the inner walls of the stiffener 32. The stiffener 32 can be made of a material such as silicon or copper, then connection electrodes are disposed in regions of the mounting substrate 10, with which the convex parts 50 of the first end surface are brought into contact, and the convex parts 50 of the first end surface is metalized and activated by use of a flux to be connected to the connection electrodes by solder. In this case, since the bonding state between the substrate 10 and the stiffener 32 can be set similar to that between the chip 20 and the substrate 10, it is possible to suppress warpage in the substrate 10 caused by contraction. Moreover, the example has been described in which the first end surface of the stiffener 32 is in the rugged shape. However, low-melting metal members such as solder bumps, which become gap members, may be arranged in the regions of the mounting substrate 10 brought into contact with the stiffener 32 to form a rugged shape. [0072] (Fourth Embodiment) [0073] Next, a fourth embodiment will be described with reference to FIG. 4. Referring to FIG. 4, a semiconductor device 1 c of the fourth embodiment is different from the semiconductor devices 1, 1 a and 1 b of the first to third embodiments, respectively, only in that a shape of an opening of a stiffener 33 is reverse-tapered. The other configuration may be similar to those of the semiconductor devices 1, 1 a and 1 b. In the semiconductor device 1 c, since an eave portion of the stiffener 33 is spread over the second resin 41, there is an effect of preventing the deformation of the fillet part 40 b and of the second resin 41 toward a lid 31. Note that a method for manufacturing the semiconductor device 1 c of the fourth embodiment is similar to that of each semiconductor device of the first to third embodiments, and therefore description thereof will be omitted. [0074] (Fifth Embodiment) [0075] Next, a fifth embodiment will be described with reference to FIGS. 5a to 5 c. Referring to FIGS. 5a to 5 c, a semiconductor device 1 d of the fifth embodiment includes: amounting substrate 10; a semiconductor chip 20 mounted on a first surface of the substrate 10 through flip chip bonding; a first resin 40 filling a gap between the substrate 10 and the chip 20; a frame-shaped stiffener 34 surrounding the chip 20; a first adhesive 42 for bonding a first end surface of the stiffener 34 to the substrate 10; a lid 31 for covering the stiffener 34 and an area surrounded by the stiffener 34; a second adhesive 43 for bonding the lid 31 to a backside of the chip 20 and to a second end surface opposite the first end surface of the stiffener 34; and a second resin 41 filling a space surrounded by the stiffener 34, side faces of the chip 20 and the substrate 10 in contact with the first resin 40. The first resin 40 includes an underfill part 40 a filling a gap between the chip 20 and the substrate 10, and a fillet part 40 b extended from a region where the chip 20 and the substrate 10 face each other. A configuration of the semiconductor device 1 d of the fifth embodiment is almost the same as that of the semiconductor device 1. The difference is that a concave part 34 a is formed on a first end surface side in each of four corners of the stiffener 34, and these concave parts 34 a are filled with the second resin 41. A rectangular semiconductor device is easily influenced by expansion/contraction in the diagonal direction thereof, because a diagonal length thereof is longest therein. According to the semiconductor device 1 d, the aforementioned structure provides an effect of suppressing an influence by expansion/compression. [0076] In the semiconductor device id of this embodiment, as a material of the stiffener 34, it is preferable to use a material of which the thermal expansion coefficient is approximate to that of the substrate 10, such as Al, Cu or SUS. The first adhesive 42 may be used for bonding the substrate 10 to the other parts than the concave parts 34 a of the stiffener 34, i.e., to side centers of the stiffener 34, but the use of a resin the same as the second resin 41 is more preferable. The concave parts 34 a provided in the corners are filled with the second resin 41. A working feature according to the structure of the fifth embodiment is that the thermal expansion coefficients of the substrate 10 and of the stiffener 34 are nearly matched with each other, and at the same time, the concave parts 34 a are filled with the second resin 41, thereby suppressing the warpage in the substrate 10. Moreover, the warpage in the portion of the substrate 10 directly facing the chip 20 is suppressed by the first resin 40 and the second resin 41. [0077] Next, a method for manufacturing the semiconductor device 1 d of this embodiment will be described. Since a first method for manufacturing the semiconductor device 1 d is almost similar to that for the semiconductor device 1 of the first embodiment, different points will be mainly described. A first different point is the shape of the first end surface of a stiffener. The stiffener 34 has the concave parts 34 a processed on the first end surface in each corner. On the contrary, the first end surface of the stiffener 30 is flat. A second different point is that, in association with the use of the stiffener 34, the first adhesive 42 or the second resin 41 is applied on the substrate 10 in a shape so as to coincide with the shape of the stiffener 34, the second resin 41 is superposedly applied on corresponding positions to the concave parts 34 a, and the stiffener 34 is aligned with the portions coated with the first adhesive 42 or the second resin 41 in the shape so as to coincide with the shape of the stiffener 34 and mounted thereon so that the first end surface is brought into contact with the first adhesive 42 or the second resin 41. The other portions can be manufactured by a similar manufacturing method to that for the semiconductor device 1 of the first embodiment. [0078] Next, a second method for manufacturing the semiconductor device 1 d will be described with reference to FIGS. 9a to 9 i. First, the stiffener 34 (not shown in FIG. 9a) and the substrate 10 are prepared. On the first surface of the substrate 10, the internal land electrodes 11 are formed in corresponding positions to the chip electrodes 21 of the chip 20 to be mounted. The external land electrodes 12 are formed on the second surface opposite the first surface. The corresponding internal and external land electrodes 11 and 12 are connected to each other through in-substrate wiring 15 (FIG. 9a). [0079] Next, the first adhesive 42 with a thermal expansion coefficient of 16 to 22 ppm and with an elastic modulus of 11 to 12 GPa is applied on a peripheral portion of the substrate 10 in a shape so as to coincide with the shape of the prepared stiffener 34. Thereafter, the stiffener 34 is aligned with the portion coated with the first adhesive 42 and mounted thereon so that the first end surface is brought into contact with the first adhesive 42, which is then temporarily cured at around 125� C. for about 15 minutes (FIG. 9b). In this state, the stiffener 34 is bonded to the substrate 10, but the first adhesive 42 has not completely set yet. Note that the first adhesive 42 essentially contains a resin material selected from the group consisting of, e.g., epoxy, polyolefin, silicon, cyanate ester, polyimide, and polynorbornene resins, and is adjusted by mixing a proper amount of inorganic filler so that the thermal expansion coefficient and the elastic modulus are set to desired values. A material of the stiffener 34 is preferably selected from the group consisting of Cu, SUS (ferrite stainless steel), and Al of which the thermal expansion coefficient is approximate to that of the substrate 10. [0080] Next, the chip 20 in which the bump electrodes 22 are bonded to the chip electrodes 21 is positioned and mounted so that the bump electrodes 22 are brought into contact with the corresponding internal land electrodes 11, and heated to about 250� C. in, e.g., a nitrogen atmosphere, thus connecting the chip 20 to the internal land electrodes 11 of the substrate 10 (FIG. 9c). [0081] Next, the first resin 40 is injected with a dispenser or the like by a dropping method to fill a gap between the chip 20 and the substrate 10, and then temporarily cured at around 100� C. for about 10 minutes (FIG. 9d). In this state, the first resin 40 also has not completely set yet. Note that the first resin 40 is prepared by adjusting, e.g., epoxy resin to have a thermal expansion coefficient of about 32 ppm and an elastic modulus of about 9 GPa. With these characteristics of the first resin 40, the flowability thereof is 1000 to 40000 centipoises (CPS), and the first resin 40 can be injected to fill the gap between the chip 20 and the substrate 10 without generating any voids and fills that without generating any voids. At this time, the first resin 40 forms not only the underfill part 40 a filling the gap between the chip 20 and the substrate 10 but also the fillet part 40 b extended from the underfill part 40 a to a surrounding area of the chip 20. However, the fillet part 40 b does not reach the stiffener 34, and at this point of process steps, the first surface of the substrate 10 is exposed between the fillet part 40 b and the stiffener 34. [0082] Next, after the second adhesive 43 is applied onto the backside of the chip 20 and onto the second end surface of the stiffener 34 (FIG. 9e), the lid 31 is mounted on the second adhesive 43 so as to cover the entire area surrounded by the stiffener 34. The second adhesive 43 is then heated at about 150� C. for about 30 minutes, and thereby temporarily cured to bond the lid 31 thereto (FIGS. 9f and 9 g). Note that, for the second adhesive 43, an epoxy resin with a thermal expansion coefficient of about 50 to 100 ppm can be used, for example. In the case of the second adhesive 43, it is more preferable to mix a proper amount of Ag or Cu powder as an inorganic filler to improve the thermal conductivity of the second adhesive 43. [0083] Next, a heating pressing-in nozzle 60 is brought into contact with two of the concave parts 34 a formed in the corners of the stiffener 34 to which the lid 31 is connected, and the second resin 41 is injected to fill the space surrounded by the side faces of the chip 20, the inner walls of the stiffener 34, the lid 31, the substrate 10 and the fillet part 40 b (FIGS. 9h and 9 i). Note that, as the method for injecting the second resin 41 to fill the space, an injection method using a transfer mold can be also used. [0084] Next, after the entire device is slowly heated to about 175� C., it is maintained at the state of about 175� C. for about 60 minutes, so that all of the first resin 40, the second resin 41, the first adhesive 42, and the second adhesive 43 are completely cured. Thereafter, for example, solder bumps 13, which become external terminals, are bonded to the external land electrodes 12 of the substrate 10 by a well known method, thus completing the semiconductor device 1 d as shown in FIGS. 5a to 5 c. [0085] (Sixth Embodiment) [0086] Next, a sixth embodiment will be described with reference to FIG. 6. A semiconductor device 1 e of this embodiment is different from the semiconductor device 1 of the first embodiment in that the stiffener 30 is replaced with a stiffener 35 made of an organic material resin. The other configuration is the same as that of the semiconductor device 1. Except that the stiffener 35 made of the resin is prepared beforehand by, e.g., transfer molding, the other steps of a method for manufacturing the semiconductor device 1 e of this embodiment are similar to those of the method for manufacturing the semiconductor device 1 of the first embodiment, as shown in FIGS. 10a to 10 g, and therefore detailed description thereof will be omitted. To explain an outline, first, the first adhesive 42 is applied on the substrate 10, and the resin stiffener 35 is mounted thereon to temporarily cure the first adhesive 42. Subsequently, the chip 20 is connected to the internal land electrodes 11 through flip chip bonding, and the gap between the chip 20 and the substrate 10 is filled with the first resin 40, which is then temporarily cured. Next, a second resin 41 is injected into the space between the stiffener 35 and the chip 20. Next, the second adhesive 43 is applied onto the backside of the semiconductor chip 20 and onto the second end surface of the stiffener 35, the lid 31 is mounted thereon to carry out full curing, and all of the first adhesive 42, the first resin 40, the second resin 41 and the second adhesive 43 are completely cured. Thus, the semiconductor device 1 e is completed. [0087] Note that, as another method for manufacturing the semiconductor device 1 e of this embodiment, a method in which the substrate 10 is placed in a transfer sealing mold and the resin stiffener 35 is integrally formed on the substrate 10, can be applied. By this method, a shape shown in FIG. 10b can be realized, and the processes thereafter can be carried out similarly to the manufacturing method of the first embodiment. According to this method, it is possible to save labor in the manufacturing processes. [0088] (Seventh Embodiment) [0089] Next, a seventh embodiment will be described with reference to FIG. 7. A semiconductor device if of this embodiment is different from the semiconductor device 1 of the first embodiment in that the stiffener 30 is replaced with a stiffener 36 which is made of an organic material resin and has a reverse-tapered opening. The other configuration is similar to that of the semiconductor device 1. According to the semiconductor device 1 f of this embodiment, the stiffener 36 hangs over the second resin 41 in a manner of eaves. This structure provides an effect of suppressing the deformation of the fillet part 40 b and of the second resin 41 toward a lid 31. A method for manufacturing the semiconductor device 1 f of this embodiment is similar to that of the semiconductor device 1 e of the sixth embodiment. [0090] As described above, according to the present invention, a semiconductor chip is connected to a mounting substrate through flip chip bonding, a gap between the substrate and the chip is filled with a first resin, and a stiffener is attached to the substrate so as to surround the chip to serve as a lid support. In this state, the space surrounded by the mounting substrate, the side-walls of semiconductor chip, the stiffener and the lid is filled with the second resin smaller in thermal expansion coefficient than the first resin, and all the resins are cured. Accordingly, the second resin suppresses the up-and-down movements of the mounting substrate due to the expansion/contraction of the first resin, and thus it is possible to prevent the occurrence of detachment of the chip electrodes from the internal land electrodes and the occurrence of cracks of the solder bumps caused by temperature cycling. Moreover, since the strength of the mounting substrate can be reinforced at an initial stage of the manufacture, it is possible to improve handling performance and to suppress warpage in the mounting substrate during the manufacturing processes. Further, by temporarily curing the adhesives and the resins in the respective steps, and completely curing the adhesives and the resins all together at the end, it is possible to limit deformation to a minimum after the manufacture. [0091] Specifically, for example, FIGS. 12a to 12 e schematically show warped states of the mounting substrates in the respective semiconductor devices of the first to fifth embodiments of the present invention. Note that, for comparison, a warped state of a mounting substrate of a conventional semiconductor device is shown in FIG. 12f. In FIGS. 12a to 12 f, broken lines schematically indicate the warped states of the mounting substrates. As can be understood from FIGS. 12a to 12 e, maximum values Wa, Wb, Wc, Wd and We of the amounts of warpage in the mounting substrates of the semiconductor devices of the respective embodiments of the present invention are all sufficiently smaller than a maximum value Wf of the amount of warpage in the mounting substrate of the conventional semiconductor device. [0092] [0092]FIG. 13 is a graph showing a result of actually measuring the amount of warpage in the mounting substrate of the semiconductor device when the temperature of a sample is changed, regarding the sample (semiconductor chip size: 17.3 mm�17.3 mm, mounting substrate thickness: about 1.0 mm, and mounting substrate size: 50 mm�50 mm) of the semiconductor device of the first embodiment of the present invention. Note that FIG. 13 also shows, as a comparative example, the amount of warpage in the mounting substrate of the semiconductor device of the conventional structure (the semiconductor chip size, the mounting substrate thickness and the mounting substrate size are the same as those of the above sample). It can be understood from FIG. 13 that the warpage in the mounting substrate of the semiconductor device of the present invention is much lower than that of the conventional semiconductor device, in the temperature cycling test. [0093] Moreover, by using a resin the same as the second resin for the first adhesive as in the second embodiment, it is possible to further suppress the up-and-down movements of the mounting substrate due to the expansion/contraction of the first resin. Thus, it is possible to more effectively prevent the occurrence of detachment of the chip electrodes and of the internal land electrodes and the occurrence of cracks of the solder bumps caused by the temperature cycling. [0094] Furthermore, as in the fifth embodiment, by filling the concave parts formed in four corners on the first end surface of the stiffener with the second resin smaller in the thermal expansion coefficient than the first resin to use the second resin as part of the adhesive for bonding the stiffener to the mounting substrate, the influence of expansion/contraction in the diagonal direction of which the length is largest in the rectangular semiconductor device can be further suppressed. Thus, it is possible to more effectively prevent the occurrence of detachment of the chip electrodes and of the internal land electrodes and the occurrence of cracks of the solder bumps caused by the temperature cycling. Additionally, according to the second manufacturing method of the fifth embodiment, the second resin is injected and cured after the lid 31 is attached. Consequently, the space surrounded by the mounting substrate, the stiffener, the side walls of the semiconductor chip, the lid, and the fillet part can be completely filled with the second resin without generating any empty space 47 between the lid 31 and the second resin 41, and thus it is possible to suppress the deformation of the mounting substrate 10. [0095] Note that, in each drawing illustrating a first, a second, a third, a fourth, a sixth and a seventh embodiments of the present invention, the empty space 47 is shown in exaggerated form for clarity. The empty space 47 is very small in practice, so the second resin 41 may be partially in contact with the lid 31 in each of the embodiments. [0096] It is apparent that the present invention is not limited to the above embodiments and description, but may be modified or changed without departing form the scopes and spirits of apparatus claims that are indicated in the subsequent pages as well as methods that are indicated below: [0097] AA. A first method for manufacturing a semiconductor device comprises the steps of: bonding a stiffener to a mounting substrate; connecting a semiconductor chip to the mounting substrate; filling a gap with a first resin and curing the first resin; filling a space surrounded by the stiffener, the mounting substrate, and the semiconductor chip with a second resin and curing the second resin; attaching a lid; and connecting solder bumps to the mounting substrate, wherein at least the step of bonding the stiffener to the mounting substrate is set as a first step, and the step of connecting the semiconductor chip to the mounting substrate is set as a second step. [0098] BB. In the met-hod described in AA, the step of bonding the stiffener to the mounting substrate includes the steps of: applying a first adhesive onto the mounting substrate; and semi-curing the first adhesive after the stiffener is mounted on the first adhesive, [0099] the step of filling the gap with the first resin and curing the first resin includes the steps of: filling the gap between the semiconductor chip and the mounting substrate with the first resin; and semi-curing the first resin, [0100] the step of filling the space with the second resin and curing the second resin includes the steps of: filling the space with the second resin; and semi-curing the second resin, and [0101] the step of attaching the lid includes the steps of: applying the second adhesive onto the backside of the semiconductor chip and onto the second end surface of the stiffener; mounting the lid on the second adhesive; and curing the second adhesive; wherein in the step of curing the second adhesive, the first adhesive, the second adhesive, the first resin and the second resin are completely cured all together. [0102] CC. A second method for manufacturing a semiconductor device comprises the steps of: bonding a stiffener to a mounting substrate; connecting a semiconductor chip to the mounting substrate; filling a gap with a first resin and curing the first resin; filling a space surrounded by the stiffener, the mounting substrate, and the semiconductor chip with a second resin and curing the second resin; attaching a lid; and connecting solder bumps, wherein the step of filling the space with the second resin and curing the second resin is executed after the step of attaching the lid. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4970575 *Apr 9, 1990Nov 13, 1990Hitachi, Ltd.Semiconductor deviceUS5844320 *Mar 6, 1997Dec 1, 1998Matsushita Electric Industrial Co., Ltd.Semiconductor unit with semiconductor device mounted with conductive adhesiveUS5866953 *May 24, 1996Feb 2, 1999Micron Technology, Inc.Packaged die on PCB with heat sink encapsulantUS6117352 *Nov 20, 1997Sep 12, 2000Lsi Logic CorporationRemoval of a heat spreader from an integrated circuit package to permit testing of the integrated circuit and other elements of the packageUS6157080 *Nov 5, 1998Dec 5, 2000Sharp Kabushiki KaishaSemiconductor device using a chip scale packageUS6223429 *Jun 13, 1996May 1, 2001Hitachi Chemical Company, Ltd.Method of production of semiconductor deviceUS6224711 *Aug 25, 1998May 1, 2001International Business Machines CorporationAssembly process for flip chip package having a low stress chip and resulting structureUS6294831 *Oct 28, 1999Sep 25, 2001International Business Machines CorporationElectronic package with bonded structure and method of makingUS6313521 *Nov 3, 1999Nov 6, 2001Nec CorporationSemiconductor device and method of manufacturing the sameUS6407334 *Nov 30, 2000Jun 18, 2002International Business Machines CorporationI/C chip assemblyUS6410981 *Oct 22, 1998Jun 25, 2002Nec CorporationVented semiconductor device package having separate substrate, strengthening ring and cap structuresUS6410988 *May 15, 2000Jun 25, 2002International Business Machines CorporationThermally enhanced and mechanically balanced flip chip package and method of formingUS6437436 *Jan 19, 2001Aug 20, 2002Ang Technologies Inc.Integrated circuit chip package with test pointsUS6448665 *Oct 14, 1998Sep 10, 2002Kabushiki Kaisha ToshibaSemiconductor package and manufacturing method thereofUS6462405 *Jul 18, 2001Oct 8, 2002Siliconware Precision Industries Co., Ltd.Semiconductor packageUS6486562 *Jun 7, 2000Nov 26, 2002Nec CorporationCircuit device with bonding strength improved and method of manufacturing the sameUS6518089 *Feb 2, 2001Feb 11, 2003Texas Instruments IncorporatedFlip chip semiconductor device in a molded chip scale package (CSP) and method of assemblyUS6661104 *Sep 4, 2001Dec 9, 2003Micron Technology, Inc.Microelectronic assembly with pre-disposed fill material and associated method of manufactureUS6740959 *Aug 1, 2001May 25, 2004International Business Machines CorporationEMI shielding for semiconductor chip carriersUS6744132 *Jan 29, 2002Jun 1, 2004International Business Machines CorporationModule with adhesively attached heat sinkUS6756685 *Aug 1, 2002Jun 29, 2004Nec Electronics CorporationSemiconductor deviceUS6762511 *Mar 19, 2001Jul 13, 2004Hitachi, Ltd.Thermosetting resin compositionUS6825556 *Oct 15, 2002Nov 30, 2004Lsi Logic CorporationIntegrated circuit package design with non-orthogonal die cut outUS6869831 *Sep 14, 2001Mar 22, 2005Texas Instruments IncorporatedAdhesion by plasma conditioning of semiconductor chip surfacesUS6894400 *May 25, 2004May 17, 2005Agere Systems Inc.Robust electronic device packagesUS6933619 *Oct 18, 2002Aug 23, 2005International Business Machines CorporationElectronic package and method of formingUS6940162 *May 7, 2004Sep 6, 2005Renesas Technology Corp.Semiconductor module and mounting method for sameUS7115444 *Sep 27, 2005Oct 3, 2006Fujitsu LimitedSemiconductor device with improved heat dissipation, and a method of making semiconductor deviceUS7442578 *Aug 21, 2006Oct 28, 2008Micron Technology, Inc.Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of underfilling micoelectronic devicesUS20010017408 *Feb 26, 2001Aug 30, 2001Nec CorporationSemiconductor packageUS20020056906 *Feb 27, 2001May 16, 2002Ryoichi KajiwaraFlip chip assembly structure for semiconductor device and method of assembling thereforUS20020121705 *Oct 9, 2001Sep 5, 2002Siliconware Precision Industries Co., Ltd.Flip chip semiconductor packageUS20020140108 *Mar 30, 2001Oct 3, 2002International Business Machines CorporationMolded body for pbga and chip-scale packagesUS20030030968 *Aug 13, 2001Feb 13, 2003Taiwan Semiconductor Manufacturing Co., Ltd.Microelectronic assembly with stiffening memberUS20030053297 *Oct 31, 2002Mar 20, 2003International Business Machines CorporationCoupled-cap flip chip BGA package with improved cap design for reduced interfacial stressesUS20030071348 *Nov 25, 2002Apr 17, 2003Shuji EguchiSemiconductor module and mounting method for sameUS20040195701 *Jan 6, 2004Oct 7, 2004Attarwala Abbas IsmailElectronic package and methodUS20050029675 *Sep 3, 2004Feb 10, 2005Fay HuaTin/indium lead-free solders for low stress chip attachmentUS20050082650 *Oct 21, 2003Apr 21, 2005Kooi Chee C.Integrated circuit packaging systemUS20050121757 *Dec 4, 2003Jun 9, 2005Gealer Charles A.Integrated circuit package overlayUS20050121775 *Dec 4, 2003Jun 9, 2005Fitzgerald Thomas J.Device and system for heat spreader with controlled thermal expansionUS20050205984 *May 23, 2005Sep 22, 2005Tai-Saw Technology Co., Ltd.Package structure with a retarding structure and method of making sameUS20050242422 *Jun 27, 2005Nov 3, 2005Klein Dean ASemiconductor component having multiple stacked dice* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7009307 *May 19, 2004Mar 7, 2006Altera CorporationLow stress and warpage laminate flip chip BGA packageUS7459782Oct 5, 2005Dec 2, 2008Altera CorporationStiffener for flip chip BGA packageUS7495346Aug 1, 2008Feb 24, 2009International Business Machines CorporationSemiconductor packageUS7517731Aug 1, 2008Apr 14, 2009International Business Machines CorporationSemiconductor packageUS7531386 *Sep 6, 2007May 12, 2009International Business Machines CorporationSemiconductor packageUS7585702Nov 8, 2005Sep 8, 2009Altera CorporationStructure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrateUS7663254Feb 16, 2010Nec Electronics CorporationSemiconductor apparatus and method of manufacturing the sameUS7709293 *Feb 27, 2008May 4, 2010Fujitsu LimitedSemiconductor device and manufacturing method of the semiconductor deviceUS7741160Aug 4, 2009Jun 22, 2010Altera CorporationStructure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrateUS7782620Apr 24, 2009Aug 24, 2010Kabushiki Kaisha ToshibaElectronic apparatusUS7842552 *Nov 30, 2010International Business Machines CorporationSemiconductor chip packages having reduced stressUS7901986 *Nov 13, 2007Mar 8, 2011Shinko Electric Industries Co., Ltd.Wiring substrate, manufacturing method thereof, and semiconductor deviceUS7906376 *Jun 30, 2008Mar 15, 2011Intel CorporationMagnetic particle-based composite materials for semiconductor packagesUS7919359 *Oct 17, 2007Apr 5, 2011Panasonic CorporationSemiconductor mounting substrate and method for manufacturing the sameUS7923850Aug 26, 2008Apr 12, 2011Advanced Micro Devices, Inc.Semiconductor chip with solder joint protection ringUS7956468 *Jun 7, 2011Fujitsu LimitedSemiconductor deviceUS8004096 *Aug 23, 2011Fujitsu LimitedSemiconductor device and a manufacturing method thereofUS8008133Aug 30, 2011Globalfoundries Inc.Chip package with channel stiffener frameUS8018052 *Jun 29, 2007Sep 13, 2011Stats Chippac Ltd.Integrated circuit package system with side substrate having a top layerUS8119929 *Nov 6, 2008Feb 21, 2012Shinko Electric Industries Co., Ltd.Wiring board and method for manufacturing the sameUS8207618Jan 25, 2010Jun 26, 2012Panasonic CorporationSemiconductor device and method of manufacturing the sameUS8212353May 12, 2010Jul 3, 2012Altera CorporationStructure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrateUS8216887Jul 10, 2012Advanced Micro Devices, Inc.Semiconductor chip package with stiffener frame and configured lidUS8217515Jul 10, 2012Panasonic CorporationSemiconductor mounting substrate and method for manufacturing the sameUS8222730Jan 31, 2011Jul 17, 2012Intel CorporationMagnetic particle-based composite materials for semiconductor packagesUS8232138Apr 14, 2010Jul 31, 2012Advanced Micro Devices, Inc.Circuit board with notched stiffener frameUS8288208 *Oct 16, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Apparatus and methods for semiconductor packages with improved warpageUS8313984Nov 20, 2012Ati Technologies UlcDie substrate with reinforcement structureUS8338936 *Jul 24, 2008Dec 25, 2012Infineon Technologies AgSemiconductor device and manufacturing methodUS8358018 *Apr 29, 2009Jan 22, 2013Panasonic CorporationResin sealing structure for electronic component and resin sealing method for electronic componentUS8378704 *Feb 19, 2013Kyocera CorporationSubstrate for a probe card assemblyUS8405187Mar 26, 2013Globalfoundries Inc.Chip package with channel stiffener frameUS8492888 *Sep 2, 2011Jul 23, 2013Stats Chippac Ltd.Integrated circuit packaging system with stiffener and method of manufacture thereofUS8513792 *Apr 10, 2009Aug 20, 2013Intel CorporationPackage-on-package interconnect stiffenerUS8759685 *Oct 30, 2009Jun 24, 2014Shinko Electric Industries Co., Ltd.Wiring substrate and method of manufacturing the wiring substrateUS8779570 *Mar 19, 2008Jul 15, 2014Stats Chippac Ltd.Stackable integrated circuit package systemUS8779583Aug 27, 2012Jul 15, 2014Infineon Technologies AgSemiconductor device and manufacturing methodUS8796072 *Nov 15, 2012Aug 5, 2014Amkor Technology, Inc.Method and system for a semiconductor device package with a die-to-die first bondUS8847383Feb 1, 2012Sep 30, 2014Ati Technologies UlcIntegrated circuit package strip with stiffenerUS8927344Nov 8, 2012Jan 6, 2015Ati Technologies UlcDie substrate with reinforcement structureUS9040349 *Nov 15, 2012May 26, 2015Amkor Technology, Inc.Method and system for a semiconductor device package with a die to interposer wafer first bondUS9343430 *Sep 2, 2011May 17, 2016Maxim Integrated Products, Inc.Stacked wafer-level package deviceUS9349681Apr 28, 2015May 24, 2016Amkor Technology, Inc.Semiconductor device package and manufacturing method thereofUS20060051912 *Sep 9, 2004Mar 9, 2006Ati Technologies Inc.Method and apparatus for a stacked die configurationUS20060057763 *Sep 14, 2004Mar 16, 2006Agency For Science, Technology And ResearchMethod of forming a surface mountable IC and its assemblyUS20070018310 *Oct 27, 2005Jan 25, 2007Fujitsu LimitedSemiconductor device and manufacturing method thereofUS20070120268 *Jan 13, 2006May 31, 2007Roland IrsiglerIntermediate connection for flip chip in packagesUS20070194464 *Jul 19, 2006Aug 23, 2007Fujitsu LimitedSemiconductor device and a manufacturing method thereofUS20070230146 *Mar 26, 2007Oct 4, 2007Daigo SuzukiPrinted-wiring board with built-in component, manufacturing method of printed-wiring board with built-in component, and electronic deviceUS20080093739 *Oct 17, 2007Apr 24, 2008Junichi KimuraSemiconductor mounting substrate and method for manufacturing the sameUS20080142952 *Sep 6, 2007Jun 19, 2008Tohru NakanishiSemiconductor packageUS20080155820 *Nov 13, 2007Jul 3, 2008Shinko Electric Industries Co., Ltd.Wiring substrate, manufacturing method thereof, and semiconductor deviceUS20080180118 *Nov 20, 2007Jul 31, 2008Kyocera CorporationSubstrate for probe card assembly, method of manufacturing substrate for probe card assembly and method of inspecting semiconductor waferUS20080203564 *Feb 6, 2008Aug 28, 2008Nec Electronics CorporationSemiconductor device having stress alleviating portion positioned at outer circumference of chip, wiring substrate, and method for producing the sameUS20080211095 *Feb 27, 2008Sep 4, 2008Fujitsu LimitedSemiconductor device and manufacturing method of the semiconductor deviceUS20080251913 *Sep 7, 2007Oct 16, 2008Nec Electronics CorporationSemiconductor device including wiring substrate having element mounting surface coated by resin layerUS20080284047 *May 15, 2007Nov 20, 2008Eric TosayaChip Package with Stiffener RingUS20080290501 *Aug 1, 2008Nov 27, 2008International Business Machines CorporationSemiconductor packageUS20080293191 *Aug 1, 2008Nov 27, 2008International Business Machines CorporationSemiconductor packageUS20090001545 *Jun 29, 2007Jan 1, 2009Kim KyungoeIntegrated circuit package system with side substrateUS20090096084 *Oct 12, 2007Apr 16, 2009John Peter KaridisSemiconductor chip packages having reduced stressUS20090126981 *Nov 6, 2008May 21, 2009Shinko Electric Industries Co., Ltd.Wiring board and method for manufacturing the sameUS20090200659 *Feb 11, 2008Aug 13, 2009Eric TosayaChip Package with Channel Stiffener FrameUS20090236731 *Mar 19, 2008Sep 24, 2009Seong Bo ShimStackable integrated circuit package systemUS20090278265 *Apr 29, 2009Nov 12, 2009Panasonic CorporationElectronic component and resin packaging method for electronic componentUS20090296354 *Apr 24, 2009Dec 3, 2009Kabushiki Kaisha ToshibaElectronic apparatusUS20090321923 *Dec 31, 2009Rajasekaran SwaminathanMagnetic particle-based composite materials for semiconductor packagesUS20100019370 *Jul 24, 2008Jan 28, 2010Infineon Technologies AgSemiconductor device and manufacturing methodUS20100052188 *Mar 4, 2010Mohammad KhanSemiconductor Chip with Solder Joint Protection RingUS20100108361 *Oct 30, 2009May 6, 2010Shinko Electric Industries Co., Ltd.Wiring substrate and method of manufacturing the wiring substrateUS20100148368 *Feb 25, 2010Jun 17, 2010Fujitsu LimitedSemiconductor deviceUS20100187675 *Jan 25, 2010Jul 29, 2010Panasonic CorporationSemiconductor device and method of manufacturing the sameUS20100258927 *Oct 14, 2010Sanka GanesanPackage-on-package interconnect stiffenerUS20100276799 *May 4, 2009Nov 4, 2010Heng Stephen FSemiconductor Chip Package with Stiffener Frame and Configured LidUS20110068462 *Nov 24, 2010Mar 24, 2011International Business Machines CorporationSemiconductor chip packages having reduced stressUS20110100692 *Nov 2, 2009May 5, 2011Roden TopacioCircuit Board with Variable Topography Solder InterconnectsUS20110127663 *Jun 2, 2011Rajasekaran SwaminathanMagnetic particle-based composite materials for semiconductor packagesUS20110140270 *Jun 16, 2011Junichi KimuraSemiconductor mounting substrate and method for manufacturing the sameUS20110215194 *Sep 8, 2011Hispano SuizaElectronic power module for an aircraft actuatorUS20110316151 *Dec 29, 2011Shinko Electric Industries Co., Ltd.Semiconductor package and method for manufacturing semiconductor packageUS20120188721 *Jan 21, 2011Jul 26, 2012Nxp B.V.Non-metal stiffener ring for fcbgaUS20130056863 *Sep 2, 2011Mar 7, 2013HeeJo ChiIntegrated circuit packaging system with stiffener and method of manufacture thereofUS20130056866 *Sep 2, 2011Mar 7, 2013Maxim Integrated Products, Inc.Stacked wafer-level package deviceUS20140008775 *Jul 2, 2013Jan 9, 2014Elpida Memory, Inc.Semiconductor deviceUS20150187737 *Dec 5, 2014Jul 2, 2015Industrial Technology Research InstituteMolding package assembly and molding materialUS20150214074 *Jul 17, 2014Jul 30, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Packaging Methods for Semiconductor Devices, and Packaged Semiconductor DevicesCN102110660A *May 27, 2010Jun 29, 2011台湾积体电路制造股份有限公司Semiconductor flip chip package and forming method thereofEP2046105A1 *Jul 25, 2006Apr 8, 2009Panasonic CorporationCircuit board and portable electronic apparatusEP2084739A2 *Aug 31, 2007Aug 5, 2009ATI Technologies ULCFlip chip semiconductor package with encapsulant retaining structure and stripEP2084739A4 *Aug 31, 2007Feb 29, 2012Ati Technologies UlcFlip chip semiconductor package with encapsulant retaining structure and strip* Cited by examinerClassifications U.S. Classification257/778, 257/E23.193, 257/782, 257/E21.503, 438/108, 438/118, 257/E23.14International ClassificationH01L23/24, H01L23/12, H01L21/56, H01L23/10, H01L23/28Cooperative ClassificationH01L2224/32225, H01L2924/01039, H01L2924/16195, H01L2924/01006, H01L2924/01004, H01L2924/01005, H01L2924/01029, H01L2924/12044, H01L2924/01079, H01L2224/73204, H01L2224/92125, H01L24/28, H01L2924/01057, H01L2924/01082, H01L2924/15311, H01L21/563, H01L2924/01033, H01L2224/73203, H01L2224/16225, H01L23/24, H01L23/10, H01L2924/15174, H01L2924/3511, H01L2924/01013, H01L2924/18161, H01L2924/01002, H01L2924/01047, H01L2224/73253, H01L2224/83102European ClassificationH01L24/28, H01L23/10, H01L23/24, H01L21/56FLegal EventsDateCodeEventDescriptionJan 23, 2004ASAssignmentOwner name: NEC ELECTRONICS CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HONDA, HIROKAZU;REEL/FRAME:014928/0847Effective date: 20040121Owner name: NEC ELECTRONICS CORPORATION,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HONDA, HIROKAZU;REEL/FRAME:014928/0847Effective date: 20040121Dec 22, 2010ASAssignmentOwner name: RENESAS ELECTRONICS CORPORATION, JAPANFree format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:025525/0136Effective date: 20100401Jan 10, 2014REMIMaintenance fee reminder mailedJun 1, 2014LAPSLapse for failure to pay maintenance feesJul 22, 2014FPExpired due to failure to pay maintenance feeEffective date: 20140601RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services