Source: http://www.google.com/patents/US7436056?dq=3984803
Timestamp: 2016-12-07 18:27:19
Document Index: 718525376

Matched Legal Cases: ['art.\n4', 'art.\n6', 'art.\n15', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14']

Patent US7436056 - Electronic component package - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn electronic component package includes a dielectric substrate having a first surface where an electronic component is sealed. A first signal line connecting to the electronic component and a first ground conductor are formed on the first surface of the dielectric substrate. A second signal line connected...http://www.google.com/patents/US7436056?utm_source=gb-gplus-sharePatent US7436056 - Electronic component packageAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7436056 B2Publication typeGrantApplication numberUS 11/456,870Publication dateOct 14, 2008Filing dateJul 12, 2006Priority dateApr 17, 2006Fee statusPaidAlso published asUS20070241447Publication number11456870, 456870, US 7436056 B2, US 7436056B2, US-B2-7436056, US7436056 B2, US7436056B2InventorsTszshing Cheung, Tadashi Ikeuchi, Takatoshi YagisawaOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (7), Classifications (52), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetElectronic component package
US 7436056 B2Abstract
An electronic component package includes a dielectric substrate having a first surface where an electronic component is sealed. A first signal line connecting to the electronic component and a first ground conductor are formed on the first surface of the dielectric substrate. A second signal line connected to an outside connection electrode and a second ground conductor are formed on a second surface of the dielectric substrate. The first ground conductor and the second ground conductor are connected by a plurality of ground conductor via-holes. A substrate-buried signal line connected to the first signal line and the second signal line is provided inside of the dielectric substrate so as to be put between the first ground conductor and the second ground conductor above and below and between the ground conductor via-holes on the right and left.
a dielectric substrate having a first surface where an electronic component is sealed;
wherein a first signal line connecting to the electronic component and a first ground conductor are formed on the first surface of the dielectric substrate;
a second signal line connected to an outside connection electrode and a second ground conductor are formed on a second surface of the dielectric substrate;
the first ground conductor and the second ground conductor are connected by a plurality of ground conductor via-holes; and
a substrate-buried signal line connected to the first signal line and the second signal line is provided inside of the dielectric substrate so as to be put between the first ground conductor and the second ground conductor above and below and between the ground conductor via-holes on the right and left.
2. The electronic component package as claimed in claim 1,
wherein the substrate-buried signal line is connected to the first signal line and the second signal line by a via-hole.
3. The electronic component package as claimed in claim 1,
wherein the electronic component is sealed by providing a lid part on the dielectric substrate; and
the first ground conductor functions as a contact between the dielectric substrate and the lid part.
4. The electronic component package as claimed in claim 1,
wherein the first ground conductor is provided on the first surface of the dielectric substrate in a ring shape.
5. The electronic component package as claimed in claim 3,
wherein an electromagnetic wave absorption body is provided on an inside surface or an outside surface of the lid part.
6. The electronic component package as claimed in claim 1,
wherein the outside connection electrode is a metal lead.
7. The electronic component package as claimed in claim 6,
wherein the metal lead has thickness equal to or greater than 0.05 mm and equal to or smaller than 0.3 mm.
8. The electronic component package as claimed in claim 1,
wherein a ground conductor electrode extended from the second ground conductor is formed at both sides of the outside connection electrode connected to the second signal line.
9. The electronic component package as claimed in claim 1,
wherein a metal plate is provided under the second signal line.
10. The electronic component package as claimed in claim 1,
wherein a first surface of the electronic component is positioned substantially coplanar with the first surface of the dielectric substrate.
11. The electronic component package as claimed in claim 1,
wherein the dielectric substrate is a multi-layer substrate;
a layer signal line is formed on a second surface of each layer of the dielectric substrate; and
the layer signal lines are connected to each other by a via-hole so that the substrate-buried signal line is formed.
12. The electronic component package as claimed in claim 1,
wherein a layer ground conductor is formed in the vicinity of the layer signal line.
13. The electronic component package as claimed in claim 1,
wherein a wall part made of a dielectric material is provided in the vicinity of an end part of the dielectric substrate.
14. The electronic component package as claimed in claim 13,
wherein a ground structure connected to the first ground conductor is formed inside of the wall part.
15. The electronic component package, as claimed in claim 1,
wherein substrate-buried ground conductors are provided at both sides of the substrate-buried signal line.
16. The electronic component package as claimed in claim 15,
wherein the substrate-buried ground conductor has a part extending outside of a portion where the first ground conductor is provided.
17. The electronic component package, as claimed in claim 16,
wherein the substrate-buried ground conductor is connected to the first ground conductor and the second ground conductor by a via-hole.
18. The electronic component package as claimed in claim 16,
wherein the part of the substrate-buried ground conductor extending outside of the portion where the first ground conductor is provided is connected to only the second ground conductor by a via-hole.
19. The electronic component package as claimed in claim 1,
Accordingly, the present invention may provide a novel and useful electronic component package solving one or more of the problems discussed above.
FIG. 1 is a view showing a related art package having an electronic component;
FIG. 2 is a view showing a schematic structure of a package having an electronic component of a first embodiment of the present invention. More specifically, FIG. 2-(a) is a plan view of a package substrate where a lid part is not provided on an upper surface (first surface). FIG. 2-(b) is a cross-sectional view taken along a line A-A of FIG. 2-(a) where he lid part is provided on the upper surface.
A wall part 14 a of the lid part 14, the lid part 14 having a cross section of a rectangular shape without one side as viewed in FIG. 2( b) (inverted “U” shape), is mounted on the first ground conductor 13 and the wall part 14 a and the first ground conductor 13 are connected by soldering. As a result of this, a cavity where the LSI 12 is provided is formed inside of the lid part 14. In other words, the first ground conductor 13 functions to contact the lid part 14 so that the LSI 12 is sealed. The lid part 14 is made of for example, metal or dielectric material.
Thus, the first ground conductor 13 is provided on the upper surface of the package substrate 11 and the second ground conductor 16 is provided on a lower surface (second surface) of the package substrate 11. The first ground conductor 13 and the second ground conductor 16 are connected to each other via the via-holes 26-1 and 26-2. In addition, the third signal line 21 is provided so as to be put between the first ground conductor 13 (above) and the second ground conductor 13 (below) and between the via-holes 26-1 (on the right) and 26-2 (on the left).
A metal plate 22 is provided under the second ground conductor 16 so as to be separated from the end part of the metal lead 20. In a case where the metal plate 22 is not provided, even if the signal lines 15, 19 and 21 are provided on and in the package substrate 11 by performing impedance matching so that input impedance and output impedance are, for example, approximately 50 Ω each, the impedance may be mismatched if the package substrate 11 is mounted on the printed wiring board (not shown in FIG. 2). However, it is possible to avoid such a situation by providing the metal plate 22. In addition, it is possible to secure a good solder connection at the time when the package substrate 11 is provided on the printed wiring board (not shown in FIG. 2), by the metal plate 22. Here, the metal plate 22 is made of a metal such as gold (Au) or copper (Cu).
Thus, by providing the ground conductors on all four side of the third signal line 21-1,1 it is possible to perform impedance matching so that the input and output impedances each have a desirable value such as approximately 50 Ω.
f0=speed of light/(2×length of the signal line×Er)
In the meantime, referring back to FIG. 2, in the embodiment of the present invention, the thickness (“t” in FIG. 2) of the metal lead 20 extending to the outside of the package substrate 11 may be equal to or greater than approximately 0.05 mm and equal to or smaller than 0.3 mm if the package substrate 11 is made of ceramic. This is discussed with reference to FIG. 12.
In FIG. 12, the horizontal axis represents the thickness (“t” in FIG. 2) of the metal lead 20 and the vertical axis represents the 3 dB cut-off frequency (GHz).
Referring to FIG. 12, in a case where the thickness (“t” in FIG. 2) of the metal lead 20 is equal to or greater than approximately 0.05 mm and equal to or smaller than 0.3 mm, the 3 dB cut-off frequency is equal to or greater than 40 GHz. Hence, it is possible to apply this to the communication system wherein the signal transmission speed is equal to or greater than 40 Gbps.
In the above-discussed first embodiment of the present invention, the package substrate 11 has a structure where three signal lines 15, 19 and 21 are alternately provided in the thickness direction. However, the present invention is not limited to this example. The present invention can be applied to a three-layer structure where four signal lines are alternately provided in the thickness direction as an example of a multi-layer structure.
Thus, by providing the ground conductors on all four side of the third signal line 72 and the fourth signal line 73, it is possible to perform impedance matching so that the input and output impedances have desirable value such as approximately 50 Ω each.
In the above-discussed first and second embodiments of the present invention, the lid part 14 provided on the upper surface of the package substrate 11 or 71 has the cross-section of a rectangular shape without one side (inverted “U” shape). However, a part where the lid part and the package substrate 11 come in contact with each other may have a configuration shown in FIG. 23 through FIG. 25, so that a lid part 14 having a plate shape may be mounted on a package substrate 11.
In the first embodiment of the present invention, as shown in FIG. 2, the package substrate 11 has a structure where three signal lines 15, 19 and 21 are alternately provided in the thickness direction. However, as shown in FIG. 26 through FIG. 29, third signal line ground conductors 100 may be provided at right and left sides of the third signal line 21 in parallel with the third signal line 21 at the substantially same surface as (coplanar with) the surface where the third signal line 21 is provided.
In the graph shown in FIG. 30, f2 represents, as shown in FIG 11, a 3 dB cut-off frequency where there is 3 dB of attenuation. In addition, f3 through f5, namely fn represents a frequency calculated by the following formula when Er represents a dielectric constant of the package substrate.
fn=speed of light/(2×distance between one signal line and the other signal line×Er)
Thus, the number of the via-holes 26 at a part formed other than a part corresponding to where the third signal line 21-1 is provided on the first ground conductor 113 provided on the upper surface of the package substrate 111 is larger than that of the examples shown in FIG. 26 through FIG. 29. Here, the via-hole 26 connects the first ground conductor 13, the second ground conductor 16, and the third signal line ground conductors 100-1 and 100-2 provided at left and right sides of the third signal line 20-1. Accordingly, it is possible to securely perform impedance matching so that the input and output impedances of the third signal line 21-1 provided at the package substrate 111 have desirable value such as approximately 50 Ω each.
The transmission characteristic of the package substrate 111 is discussed with reference to FIG. 32. Here, FIG. 32 is a graph showing a transmission characteristic of a package substrate 111 having a structure shown in FIG. 31.
In the graph shown in FIG. 32, the horizontal axis represents a frequency (GHz) and the vertical axis represents a transmission characteristic S21 (dB). A characteristic curve represents the frequency characteristic. “f2” represents, as shown in FIG. 30, a 3 dB cut-off frequency where there is 3 dB of attenuation. In addition, f3 through f5, namely fn, represents a frequency calculated by the formula mentioned above.
Therefore, between the signal line of the printed wiring board on which the package substrate is mounted and the electronic component provided on the package substrate, it is possible to securely perform impedance matching so that the input and output impedances have desirable values such as approximately 50 Ω each. Therefore, it is possible to realize high speed communication having low transmission loss.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4739448 *Jun 25, 1984Apr 19, 1988Magnavox Government And Industrial Electronics CompanyMicrowave multiport multilayered integrated circuit chip carrierUS5168344Aug 15, 1990Dec 1, 1992W. R. Grace & Co. Conn.Ceramic electronic package designUS6410847 *Jul 25, 2000Jun 25, 2002Trw Inc.Packaged electronic system having selectively plated microwave absorbing coverUS20060103004 *Nov 16, 2005May 18, 2006NEC CORPORATION andWiring board for semiconductor integrated circuit package and semiconductor integrated circuit device using the same* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8363421Mar 19, 2009Jan 29, 2013Renesas Electronics CorporationSemiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiringUS9078347 *Jul 29, 2011Jul 7, 2015Kyocera CorporationElectronic component housing unit, electronic module, and electronic deviceUS9491873 *May 29, 2012Nov 8, 2016Kyocera CorporationElement housing package, component for semiconductor device, and semiconductor deviceUS20090244869 *Mar 19, 2009Oct 1, 2009Nec Electronics CorporationSemiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiringUS20130128467 *Jul 29, 2011May 23, 2013Kyocera CorporationElectronic component housing unit, electronic module, and electronic deviceUS20130322036 *May 29, 2012Dec 5, 2013Mahiro TsujinoElement housing package, component for semiconductor device, and semiconductor deviceUS20150080050 *Nov 24, 2014Mar 19, 2015Murata Manufacturing Co., Ltd.Composite module* Cited by examinerClassifications U.S. Classification257/698, 257/E23.079, 257/E23.128, 257/E21.501, 257/E23.07, 257/E23.062, 257/E23.18, 257/710, 257/E23.189, 257/704, 257/E23.19, 257/E23.193, 257/E23.067, 257/E21.5, 257/E23.004International ClassificationH01L23/04, H01L23/12Cooperative ClassificationH01L2924/00014, H01L2224/05573, H01L2224/05568, H01L2924/30111, H01L2924/01019, H01L24/48, H01L24/49, H01L2224/48227, H01L23/10, H01L2924/16152, H01L2924/15153, H01L2924/3011, H01L2924/15165, H01L2924/14, H01L2924/01079, H01L2924/15174, H01L23/13, H01L2924/1617, H01L2924/19051, H01L2924/15311, H01L2224/49175, H01L23/49822, H01L2924/01068, H01L2924/01078, H01L23/66, H01L23/49838, H01L2223/6616, H01L2224/16, H01L23/50European ClassificationH01L23/10, H01L23/498G, H01L23/498D, H01L23/50, H01L23/13, H01L23/66Legal EventsDateCodeEventDescriptionJul 12, 2006ASAssignmentOwner name: FUJITSU LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEUNG, TSZSHING;IKEUCHI, TADASHI;YAGISAWA, TAKATOSHI;REEL/FRAME:017915/0753Effective date: 20060614Mar 14, 2012FPAYFee paymentYear of fee payment: 4Mar 30, 2016FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services