Source: http://www.google.com/patents/US8105856?dq=%22Meaning-based+information+organization+and+retrieval%22
Timestamp: 2015-08-03 01:01:49
Document Index: 466879775

Matched Legal Cases: ['Application No. 03025016', 'Application No. 03025016', 'Application No. 03025016', 'Application No. 03028639', 'Application No. 04', 'Application No. 04018715', 'Application No. 03013839', 'Application No. 03013839', 'Application No. 03028639', 'Application No. 03025016', 'Application No. 06026978', 'Application No. 06026978', 'Application No. 10003219', 'Application No. 03028639']

Patent US8105856 - Method of manufacturing semiconductor device with wiring on side surface thereof - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsCost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor...http://www.google.com/patents/US8105856?utm_source=gb-gplus-sharePatent US8105856 - Method of manufacturing semiconductor device with wiring on side surface thereofAdvanced Patent SearchPublication numberUS8105856 B2Publication typeGrantApplication numberUS 10/876,532Publication dateJan 31, 2012Filing dateJun 28, 2004Priority dateApr 23, 2002Fee statusPaidAlso published asCN1257550C, CN1453865A, US7271466, US7312521, US20030230805, US20040235270, US20060033198Publication number10876532, 876532, US 8105856 B2, US 8105856B2, US-B2-8105856, US8105856 B2, US8105856B2InventorsTakashi Noma, Hiroyuki Shinogi, Nobuyuki Takai, Katsuhiko Kitagawa, Ryoji Tokushige, Takayasu Otagaki, Tatsuya Ando, Mitsuru OkigawaOriginal AssigneeSemiconductor Components Industries, LlcExport CitationBiBTeX, EndNote, RefManPatent Citations (132), Non-Patent Citations (44), Referenced by (4), Classifications (26), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod of manufacturing semiconductor device with wiring on side surface thereof
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No. 11/956,160; 11 pages.43Partial European Search Report mailed Jun. 1, 2011, directed to European Patent Application No. 10003219.2 (19 pages).44Partial European Search Report mailed Nov. 5, 2004, directed to European Patent Application No. 03028639.7; 5 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8426249 *Jun 15, 2010Apr 23, 2013Panasonic CorporationChip part manufacturing method and chip partsUS20100255638 *Jun 15, 2010Oct 7, 2010Panasonic CorporationChip part manufacturing method and chip partsUS20100267204 *Jun 29, 2010Oct 21, 2010Mutual-Pak Technology Co., Ltd.Package structure for integrated circuit device and method of the sameUS20120315726 *Dec 13, 2012Byun Hak-KyoonMethod of manufacturing a semiconductor chip package* Cited by examinerClassifications U.S. Classification438/33, 438/68, 438/113International ClassificationH01L21/00, H01L23/485, H01L23/31Cooperative ClassificationH01L2924/01023, H01L2924/01082, H01L2924/01078, H01L2924/01021, H01L2924/01006, H01L2924/01079, H01L2924/01029, H01L2924/01057, H01L2224/13099, H01L23/3114, H01L2924/01033, H01L24/10, H01L2924/014, H01L2924/14, H01L2924/01013, H01L2924/01015, H01L2924/01005, H01L24/13European ClassificationH01L23/31H1, H01L24/10Legal EventsDateCodeEventDescriptionJul 14, 2011ASAssignmentOwner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANYO ELECTRIC CO., LTD.;REEL/FRAME:026594/0385Effective date: 20110101May 6, 2014ASAssignmentOwner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONAFree format text: CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:SANYO ELECTRIC CO., LTD;REEL/FRAME:032836/0342Effective date: 20110101Jan 23, 2015ASAssignmentOwner name: SANYO ELECTRIC CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NOMA, TAKASHI;SHINOGI, HIROYUKI;TAKAI, NOBUYUKI;AND OTHERS;SIGNING DATES FROM 20030714 TO 20030801;REEL/FRAME:034798/0293Jun 24, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services