Source: http://www.google.de/patents/US8026574
Timestamp: 2018-01-21 18:44:13
Document Index: 148565227

Matched Legal Cases: ['Application No. 60', 'Application No. 2006', 'Application No. 05743122', 'Application No. 05743122', 'Application No. 08772785', 'Application No. 2007']

Patent US8026574 - Anti-fuse memory cell - Google Patentsuche
An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide...http://www.google.de/patents/US8026574?utm_source=gb-gplus-sharePatent US8026574 - Anti-fuse memory cell
Veröffentlichungsnummer US8026574 B2
Anmeldenummer US 12/814,124
Auch veröffentlicht unter CA2647233A1, CA2647233C, EP2165369A1, EP2165369A4, EP2165369B1, US7755162, US8313987, US20070257331, US20100244115, US20110312169, WO2008151429A1
Veröffentlichungsnummer 12814124, 814124, US 8026574 B2, US 8026574B2, US-B2-8026574, US8026574 B2, US8026574B2
Erfinder Wlodek Kurjanowicz, Steven Smith
Ursprünglich Bevollmächtigter Sidense Corporation
Patentzitate (231), Nichtpatentzitate (40), Referenziert von (2), Klassifizierungen (15), Juristische Ereignisse (2)
US 8026574 B2
This application is a continuation of U.S. patent application Ser. No. 11/762,552 filed on Jun. 13, 2007, which is a continuation in part of U.S. patent application Ser. No. 10/553,873 filed on Oct. 21, 2005, now U.S. Pat. No. 7,402,855 issued Jul. 22, 2008, which is a national stage entry of PCT Serial No. CA2005/000701 filed on May 6, 2005, which claims priority to U.S. Provisional Patent Application No. 60/568,315 filed on May 6, 2004, which is incorporated herein by reference in its entirety.
FIG. 9 is an enlarged planar layout of the anti-fuse transistor of FIG. 8 a;
FIG. 10 is a planar layout of a memory array using the anti-fuse transistor of FIG. 8 a according to an embodiment of the present invention;
In the previously disclosed embodiments of the invention, one of the thick gate oxide segments has a length extending from one end of the channel region to the other end of the channel region. According to an alternate embodiment, the length of this thick gate oxide segment is slightly reduced such that it does not fully extend across the full length of the channel region. FIG. 16 is a planar layout of an anti-fuse transistor according to an alternate embodiment of the present invention. In FIG. 16, the anti-fuse transistor 800 includes an active area 802, a polysilicon gate 804 and a bitline contact 806. The active area 802 underneath the polysilicon gate 804 is the channel region of anti-fuse transistor 800. In the present embodiment, OD2 mask 808 defines the area within which thick oxide is to be formed, and includes an “L”-shaped opening 809 overlapping an active area 802, within which thin gate oxide will be grown. This embodiment is similar to that shown in FIG. 9, except that one thick gate oxide segment (i.e. 508) extends to a first predetermined distance between the channel region top edge and a second predetermined distance for the adjacent thick gate oxide segment (ie. 510). Therefore, the thin gate oxide will be grown between the first predetermined distance and the channel region top edge, and the second predetermined distance and the channel region top edge.
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US-Klassifikation 257/530, 257/288, 257/50, 257/E23.147
Internationale Klassifikation H01L29/00
Unternehmensklassifikation G11C17/16, H01L27/112, H01L27/11206, H01L2924/0002, H01L23/5252, H01L27/101
Europäische Klassifikation G11C17/16, H01L27/10C, H01L27/112, H01L27/112P