Source: http://www.google.com/patents/US6433294?dq=3140553
Timestamp: 2017-04-23 12:07:07
Document Index: 443358797

Matched Legal Cases: ['art 11', 'application No. 08', 'art 11', 'art 10', 'art 11', 'art 10', 'art 11', 'art 11', 'art 11', 'art 11', 'application No. 08']

Patent US6433294 - Semiconductor device testing apparatus and semiconductor device testing ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor device testing system is provided which can efficiently utilize a plurality of semiconductor device testing apparatus. There are provided a host computer 2 for controlling a plurality of semiconductor device testing apparatus 1A, 1B, and 1C, and a dedicated classifying machine 3. Storage...http://www.google.com/patents/US6433294?utm_source=gb-gplus-sharePatent US6433294 - Semiconductor device testing apparatus and semiconductor device testing system having a plurality of semiconductor device testing apparatusAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6433294 B1Publication typeGrantApplication numberUS 09/505,634Publication dateAug 13, 2002Filing dateFeb 16, 2000Priority dateJul 28, 1995Fee statusLapsedAlso published asCN1084476C, CN1137508C, CN1159227A, CN1237714A, DE19680785B4, DE19680785T0, DE19680785T1, US6066822, US20020036161, WO1997005496A1Publication number09505634, 505634, US 6433294 B1, US 6433294B1, US-B1-6433294, US6433294 B1, US6433294B1InventorsShin Nemoto, Yoshihito Kobayashi, Hiroo Nakamura, Takeshi Onishi, Hiroki IkedaOriginal AssigneeAdvantest CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (29), Non-Patent Citations (1), Referenced by (17), Classifications (13), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device testing apparatus and semiconductor device testing system having a plurality of semiconductor device testing apparatus
US 6433294 B1Abstract
A semiconductor device testing system is provided which can efficiently utilize a plurality of semiconductor device testing apparatus. There are provided a host computer 2 for controlling a plurality of semiconductor device testing apparatus 1A, 1B, and 1C, and a dedicated classifying machine 3. Storage information memory means 4 for storing storage information of each semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and the like is provided in the host computer 2. Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in the handler part 11 of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory means. When all the tests are completed, the storage information of each device stored in the storage information memory means is transmitted to the dedicated classifying machine by which the tested devices are sorted out.
What is claimed is: 1. A semiconductor device testing system comprising:
a semiconductor device testing apparatus comprising: a tester part which comprises a tester head, and a handler part which comprises device transfer means and test tray conveying means; storage information memory means; and a dedicated classifying machine, wherein: a plurality of semiconductor devices to be tested are loaded by said device transfer means on a test tray in a loader section of said testing apparatus, said test tray is transported by said test tray conveying means into a test section of the testing apparatus where said semiconductor devices loaded on said test tray are brought into electrical contact with said tester head of said tester part disposed in said test section to test operation of the semiconductor devices, after completion of the test, said test tray with the tested semiconductor devices loaded thereon is transported by said test tray conveying means from the test section to an unloader section of the testing apparatus where the tested semiconductor devices on said test tray are transferred by said device transfer means from said test tray onto general-purpose trays without being sorted, the general-purpose trays with the tested semiconductor devices loaded thereon, are transported out from said testing apparatus to the dedicated classifying machine, said memory means stores storage information of respective tested semiconductor devices including an identification number assigned to each semiconductor device, and test results of each semiconductor device, every time each tested semiconductor device is loaded on associated one general-purpose tray; said storage information of the tested semiconductor devices loaded on the associated general purpose tray is transmitted from said dedicated classifying machine; and said dedicated classifying machine receives the general-purpose trays loaded with the tested semiconductor devices and sorts the received, tested semiconductor devices loaded on each of the general purpose trays based on their storage information, whereby a sort operation of the dedicated classifying machine is performed independent on an operation of the testing apparatus. 2. A semiconductor device testing system comprising:
a semiconductor device testing apparatus comprising: a tester part which comprises a tester head, and a handler part which comprises device transfer means and a device carrier; storage information memory means; and a dedicated classifying machine, wherein: semiconductor devices to be tested are loaded by said device transfer means on said device carrier in a loader section of the testing apparatus, said device carrier carries said semiconductor devices from the loader section to a test section of said testing apparatus where said semiconductor devices are brought into contact with said tester head and tested by the tester part, and after completion of the test, said device carrier carries the tested semiconductor devices out from the test section to an unloader section of the testing apparatus where the tested semiconductor devices are retained by said device transfer means in a general purpose tray without being sorted, said storage information memory means stores storage information of the respective tested semiconductor devices retained in the general purpose tray including at least their test results, and said dedicated classifying machine receives from the semiconductor device testing apparatus the general purpose tray retaining the tested semiconductor devices without being sorted and sorts the thus received tested semiconductor devices based on their storage information stored in and supplied from said memory means, whereby a sort operation of the dedicated classifying machine is performed independently on an operation of the testing apparatus. 3. A semiconductor device testing system comprising:
a semiconductor devices testing apparatus comprising: a tester having a tester head, and a handler having device transfer means and tray transport means; a test tray and a general purpose tray; storage information memory means; and a dedicated classifying machine, wherein: semiconductor devices to be tested are loaded by the device transfer means of said handler on the test tray in a loader section of said testing apparatus, said test tray thus loaded with the semiconductor devices is transported by the tray transport means of said handler into a test section of the testing apparatus where said semiconductor devices are brought into contact with the tester head and tested by said tester, after completion of the test, said test tray with the tested semiconductor devices is transported by the tray transport means of said handler from the test section to an unloader section of the testing apparatus, in the unloader section, the tested semiconductor devices loaded on said test tray are transferred by the device transfer means of said handler from said test tray onto the general-purpose tray without sorting, said storage information memory means stores storage information of the respective tested semiconductor devices including at least their test results, and said dedicated classifying machine receives the general-purpose trays thus loaded thereon with the tested semiconductor and sorts the tested semiconductor devices based on their storage information from said memory means, whereby a sorting operation of said dedicated classifying machine is performed independently on an operation of said testing apparatus. 4. A semiconductor device testing system comprising:
a semiconductor device testing apparatus comprising a tester and a handler, wherein semiconductor devices to be tested are tested by the tester and after the test the semiconductor devices thus tested are loaded without being sorted by device transfer means of said handler on general purpose trays, which trays are then delivered out from the testing apparatus; a memory coupled to the semiconductor device testing apparatus and storing storage information including test results of respective, tested semiconductor devices as per each of said general-purpose trays; and a dedicated classifying machine coupled to the semiconductor device testing apparatus and to the memory, receiving the general-purpose trays loaded with the tested semiconductor devices from the semiconductor device testing apparatus as well as the storage information of the tested semiconductor devices loaded on the associated general purpose trays from said memory, and sorting the tested semiconductor devices from the respective general purpose trays thus received based on their storage information, whereby a sorting operation of said dedicated classifying machine is performed independently on an operation of the device transfer means of said handler. 5. A semiconductor device testing system, comprising:
a semiconductor device testing apparatus comprising a tester and a handler, wherein semiconductor devices to be tested are tested by the tester and the tested semiconductor devices are loaded by said handler on a general-purpose tray without being sorted; a memory coupled to the semiconductor device testing apparatus and storing storage information including test results of respective, tested semiconductor devices as per said general purpose tray; and a dedicated classifying machine coupled to the semiconductor device testing apparatus and to the memory; wherein said dedicated classifying machine receives the general purpose tray loaded with the tested semiconductor devices without being sorted from the semiconductor device testing apparatus and also receives the storage information from the memory, and then sorts the tested semiconductor devices loaded on the received general-purpose tray without being sorted based on the received storage information of the corresponding general purpose tray, whereby a sorting operation of said dedicated classifying machine is performed independently on an operation of said handler. 6. A semiconductor device testing system comprising:
a semiconductor device testing apparatus which tests semiconductor devices and retains the thus tested semiconductor devices in general purpose trays without sorting; storage information memory means; and a dedicated classifying machine which is disposed outside of the testing apparatus and performs sorting operation of the tested semiconductor devices independently of operation of the testing apparatus, wherein: said storage information memory means stores storage information of respective tested semiconductor devices retained in each general purpose tray, said storage information including at least identification of each tested semiconductor device and its test results, said dedicated classifying machine receives each said general-purpose tray retaining the tested semiconductor devices from said testing apparatus, and said dedicated classifying machine further receives said storage information of each tested semiconductor device from the said storage information memory means, and performs its sorting operation on each said tested semiconductor device retained in the thus received general purpose tray based on the corresponding storage information of the semiconductor device under sorting. 7. The semiconductor device testing system according to claim 6, wherein
the tested semiconductor devices are transferred from a test tray to a general purpose tray without sorting by means of a handler in the testing apparatus, and said dedicated classifying machine receives the general-purpose tray and sorts the tested semiconductor devices retained in the received general purpose tray under its sorting function.
This application is a divisional of application No. 08/809,702, filed Mar. 27, 1997, now allowed, which is a 371 of PCT/JP96/02130, filed Jul. 29, 1996 now U.S. Pat. No. 6,066,822.
Many of semiconductor device testing apparatus (commonly called IC tester) for applying a test signal of a predetermined pattern to a semiconductor device to be tested, i.e. device under test (commonly called DUT) and measuring the electrical characteristics of the devices, have a semiconductor device transporting and handling or processing apparatus (commonly called handler) mounted thereto which transports semiconductor devices to a test section, brings them into electrical contact with a tester head in the test section, after the testing, carries the tested semiconductor devices out of the test section, and sorts them out into pass articles and failure articles on the basis of the test results. In the specification, the testing apparatus which comprises a combination of the IC tester and the handler mounted or connected thereto of the type described above is termed “semiconductor device testing apparatus”. In the following disclosure the present invention will be described by taking ICs typical of semiconductor devices for example for clarity of explanation.
As the density of elements integrated on a semiconductor substrate or chip in an IC becomes higher, the number of terminals or pins of the IC is increased, and it is difficult to test such an IC having a large number of terminals using an IC testing apparatus having a naturally dropping type handler mounted thereto in which ICs are caused to slide down in a sloped carrying path or groove by their gravities for testing the ICs. Therefore, the general trend in recent years is toward the use of an IC testing apparatus having a handler called “horizontal transporting system” mounted thereto which can transport ICs to any desired place or position by using suction head means utilizing a vacuum pump which may pick up one to several ICs at a time and X and Y direction transfer means.
The chamber section 100 comprises a constant temperature or thermostatic chamber 101 for receiving the ICs to be tested loaded on the test tray TST and imposing an intended high or low temperature stress to the ICs, a test or testing chamber 102 for effecting an electrical test on the ICs subjected to the temperature stress in the constant temperature chamber 101, and a temperature-stress removing chamber 103 for removing the temperature stress of the ICs having been applied thereto in the test chamber 102 from the ICs. The test chamber 102 contains therein a tester head 104 of the testing apparatus, supplies various electric signals for testing via the tester head 104 to the ICs to be tested in electrically contact therewith, receives response signals from the ICs, and sends them to the testing apparatus.
In case a temperature stress of a high temperature (a thermal stress) has been applied to the ICs to be tested in the constant temperature chamber 101, the temperature-stress removing chamber 103 cools the tested ICs down to room temperature by blowing, after which they are transported to the unloader section 400. on the other hand, in case a temperature stress of a low temperature such as, for instance, −30° C. (a cryogenic stress) has been applied to the ICs to be tested in the constant temperature chamber 101, the temperature-stress removing chamber 103 heats the tested ICs by warm air or a heater up to a temperature at which the ICs have no any dew condensation, and then they are carried out of the temperature-stress removing chamber 103 to the unloader section 400.
As shown in FIG. 5, an IC transfer means for transferring ICs from a general-purpose tray KST to a test tray TST in the loader section 300 may be in the form of X and Y direction transfer means 304 which comprises a pair of spaced parallel rails 301 mounted on the base plate 105 and extending over the loader section 400 in the front-to-back or forward-rearward direction of the testing apparatus (referred to as the Y direction herein), a movable arm 302 which spans between the two rails 301 and has its opposite ends secured thereto in a manner to be movable in the Y direction, and a movable head 303 which is supported by the movable arm 302 in a manner to be movable in the direction in which the movable arm 302 extends, that is, in the left to right direction of the testing apparatus (referred to as the x direction herein). With this arrangement, the movable head 303 is allowed to reciprocate between the test tray TST and the general-purpose tray KST in the Y direction and move along the movable arm 302 in the X direction.
On the underside of the movable head 303 are vertically movably mounted IC suction pads. Through the movement of the movable head 303 in the X and Y directions and the downward movement of the suction pads in combination, the suction pads are brought into abutment with the ICs placed on the general-purpose tray KST and pick them up and hold thereto by vacuum suction to transfer them to the test tray TST. The number of suction pads that are mounted on the movable head 303 may be eight, for instance, so that a total of eight ICs may be transferred from the general-purpose tray KST to the test tray TST at one time.
It is to be noted here that means 305 for correcting the position of an IC called “preciser” (FIG. 5) is located between stopping positions for the general-purpose tray KST and the test tray TST. The position correcting means 305 includes relatively deep recesses into which the ICs as being attracted against the suction pads are once released to fall prior to being transferred to the test tray TST. The recesses are each defined by vertical tapered side walls which prescribe for the positions at which the ICs drop into the recesses by virtue of the tapering. After eight ICs have been precisely positioned relative to each other by the position correcting means 305, those eight ICs accurately positioned are again attracted against the suction pads and conveyed to the test tray TST. The reason that the position correcting means 305 is provided is as follows. Recesses of the general-purpose tray TST for holding the ICs are sized larger as compared to the size of ICs, resulting in wide variations in positions of ICs placed on the general-purpose tray KST. Consequently, if the ICs as such were vacuum picked up by the suction pads and transferred directly to the test tray TST, there might be some of the ICs which could not be successfully deposited into the IC storage recesses formed in the test tray TST. This is the reason for requiring the position correcting means 305, as described above which acts to array ICs as accurately as the array of the IC storage recesses formed in the test tray TST.
FIG. 6 shows the construction of one example of the test tray TST. The illustrated test tray TST comprises a rectangular frame 12 having a plurality of equally spaced apart parallel cleats 13 between the opposed side frame members 12 a and 12 b of the frame, each of the cleats 13 having a plurality of equally spaced apart mounting lugs 14 protruding therefrom on both sides thereof and each of the side frame members 12 a, 12 b opposing the adjacent cleats having similar mounting lugs 14 protruding therefrom. The mounting lugs 14 protruding from the opposed sides of each of the cleats 13 are arranged such that each of the mounting lugs 14 protruding from one side of the cleat 13 is positioned intermediate two adjacent mounting lugs 14 protruding from the opposite side of the cleat. Similarly, each of the mounting lugs 14 protruding from each of the side frame members 12 a and 12 b is positioned intermediate two adjacent mounting lugs 14 protruding from the opposed cleat. Formed between each pair of opposed cleats 13 and between each of the side frame members 12 a and 12 b and the opposed cleats are spaces for accommodating a multiplicity of IC carriers 16 in juxtaposition. More specifically, each IC carrier 16 is accommodated in one of an array of rectangular carrier compartments 15 defined in each of said spaces, each compartment 15 including two staggered, obliquely opposed mounting lugs 14 located at the diagonally opposed corners of the compartment. In the illustrated example wherein each cleat 13 has sixteen mounting lugs 14 on either side thereof, there are sixteen carrier compartments 15 formed in each of said spaces, in which sixteen IC carriers 16 are mounted. Since there are four of the spaces, 16×4, that is, 64 IC carriers in total can be mounted in one test tray TST. Each IC carrier 16 is placed on corresponding two mounting lugs 14 and fixed thereto by fasteners 17.
In order to prevent IC elements from slipping out of place within the IC carrier 16 or jumping out of the IC carrier 16, a pair of latches 23 are attached to the IC carrier 16, as shown in FIG. 7. These latches 23 are integrally formed with the body of the IC carrier so as to extend upwardly from the base of the IC pocket 19, and are normally resiliently biased such that the top end pawls are urged toward each other by virtue of the resiliency of the resin material of which the IC carrier is made. When the IC element is to be deposited into or removed from the IC pocket 19, the top ends of the two latches 23 are expanded away from each other by a latch releasing mechanism 25 disposed on opposite sides of an IC suction pad 24 for picking up an IC element prior to effectuating the deposition of the IC element into or removal from the IC pocket 19. Upon the latch releasing mechanism 25 being moved out of engagement with the latches 23, the latches 23 will snap back to their normal positions by their resilient forces where the deposited IC is held in place against dislodgement by the top end pawls of the latches 23.
The number of IC elements which may be connected with the tester head 104 at a time depends on the number of IC sockets mounted on the tester head 104. By way of example, where sixty-four IC elements are arranged in an array of 4 lines×16 rows on a test tray TST as shown in FIG. 9, 4×4, that is, 16 IC sockets are arranged and mounted on the tester head 104 such that the IC elements (shown as obliquely hatched) in every fourth row in each of the lines may be tested all at one time. More specifically, in the first test run the examination is conducted on sixteen IC elements located in the first, fifth, ninth and thirteenth rows in each line, the second test run is effected on another sixteen IC elements located in the second, sixth, tenth and fourteenth rows in each line by shifting the test tray TST by a distance corresponding to one row of IC elements, and the third and fourth test runs are carried out in the similar manner until all of the IC elements are tested. The test results are stored in a memory at the addresses determined by, for instance, serial numbers (serial numbers in one lot or batch) assigned to ICs, the identification number given to the test tray TST and the numbers assigned to the IC pockets in the test tray. It is to be appreciated that where thirty-two IC sockets may be mounted on the tester head 104, only two test runs are required to examine all sixty-four IC elements arranged in an array of 4 lines×16 rows. It is also to be noted that there is another type of IC handler in which ICs to be tested are transferred from the test tray into a socket mounted on the tester head 104 and upon the test being completed the tested ICs are transferred from the socket back onto the test tray to transport the ICs, in the test chamber 102.
The IC storage section 200 comprises an IC storage rack (or stocker) 201 for accommodating general-purpose trays KST loaded with ICs to be tested and a tested IC storage rack (or stocker) 202 for accommodating general-purpose trays KST loaded with tested ICs sorted out by categories on the basis of the test results. The IC storage rack 201 and tested IC storage rack 202 are configured to accommodate general-purpose trays in the form of a stack. The general-purpose trays KST with ICs to be tested carried thereon and stored in the form of a stack in the IC storage rack 201 are transported successively from the top of the stack to the loader section 300 where the ICs to be tested (DUTS) are transferred from the general-purpose tray KST onto a test tray TST on standby in the loader section 300. Each of the IC storage rack 201 and the tested IC storage rack 202 may be of identical shape and structure. Either of the IC storage rack 201 and any one of the tested IC storage racks 202 comprises, as any one of the IC storage rack 201 and the tested IC storage racks 202 is shown in FIG. 10, a tray supporting frame 203 open at the top and having an opening at the bottom, and an elevator 204 disposed below the frame 203 so as to be vertically movable through the bottom opening. In the tray supporting frame 203 there are stored and supported a plurality of general-purpose trays KST stacked one on another which are vertically moved by the elevator 204 acting through the bottom opening of the frame 203.
In the example illustrated in FIGS. 4 and 5, eight racks STK-1, STK-2, . . . , STK-8 are provided as tested IC storage racks 202 so as to be able to store tested ICs which may be sorted out into eight categories at a maximum according to the test results. This is because in some applications tested ICs may not only be classified into categories of “conformable or pass article” and “unconformable or failure article” but also be subclassified into those having high, medium and low operation speeds among the “pass” articles and those required to be retested among the “failure” articles, and others. Even if the number of classifiable categories is up to eight, the unloader section 400 in the illustrated example is capable of accommodating only four general-purpose trays KST. For this reason, if there occur some among the tested ICs which should be classified into a category other than categories assigned to the general-purpose trays KST arranged in the unloader section 400, the procedures taken are to return one of the general-purpose trays KST from the unloader section 400 to the IC storage section 200 and in replacement to transfer a general-purpose tray KST for storing the ICs belonging to the new additional category from the IC storage section 200 to the unloader section 400 where those ICs are stored in the new tray.
According to a second aspect of the present invention, there is provided an IC testing system including a plurality of IC testing apparatus each of which is arranged such that ICs to be tested are transferred from a general-purpose tray onto a test tray to be reloaded thereon in a loader section, the test tray with the ICs loaded thereon is transported through a constant temperature or thermostatic chamber into a test section where the ICs loaded on the test tray are caused to undergo a test, and after the completion of the test, the test tray with the tested ICs loaded thereon is transported to an unloader section where the tested ICs are transferred from the test tray onto a general-purpose tray, and further comprising a dedicated classifying machine for exclusively performing the sorting operation of the tested ICs loaded on the general-purpose tray, and storage information memory means provided in a host computer for controlling the plurality of IC testing apparatus or in each IC testing apparatus. Storage information such as the test results of each IC stored in corresponding one IC receiving portion of the general-purpose tray, the number of a socket with which the IC has been brought into contact in the test section, and the like is stored in the storage information memory means at an address thereof which is determined by a serial number assigned to each IC, an identification number assigned to each general-purpose tray, and the number assigned to each of the IC receiving portions of each general-purpose tray. Each IC testing apparatus sorts out the tested ICs into only two categories of the conformable or pass ICs and the unconformable or failure ICs, and the dedicated classifying machine executes the sub-classifying operation of the tested ICs on the basis of the storage information stored in the storage information memory means.
As with the conventional IC testing apparatus described above with reference to FIGS. 4 to 10, the handler part 11 of each IC testing apparatus 1A, lB or IC comprises a chamber section for testing ICs which have been carried on a test tray, an IC storage section for storing ICs to be tested and ICs already tested and sorted out, a loader section where ICs to be tested which a user has beforehand loaded on general-purpose trays are transferred and reloaded onto a test tray capable of withstanding high/low temperatures, and an unloader section where the tested ICs which have been carried on the test tray out of the chamber section subsequently to undergoing a test therein are transferred from the test tray to the general-purpose trays to be reloaded on the latter. The chamber section comprises a constant temperature chamber for imposing a temperature stress of either a designed high or low temperature on ICs to be tested loaded on a test tray, a test chamber for conducting electrical tests on the ICs under the temperature stress imposed in the constant temperature chamber by bringing the ICs into electrical contact with a tester head of the IC tester part 10, and a temperature-stress removing chamber for removing the temperature stress imposed in the constant temperature chamber from the ICs having undergone the tests in the test chamber.
To this end, in this embodiment, storage information memory means 4 is provided in the host computer 2. All the test results of the ICs are stored in the storage information memory means 4. The test results of the ICs are stored at respective addresses of the storage information memory means 4, each address of which is determined by a serial number assigned to each IC, an identification number given to each general-purpose tray, a number allocated to each of IC pockets of each general-purpose tray in the correspondence thereto, and the like every time one of the tested ICs is transferred from the test tray to the general-purpose tray in the unloader section of each handler part 11. Examples of the test results include the condition of the tests, a classification of the tested ICs by operation speeds such as “high speed”, “medium speed” and “low speed” among the pass ICs, the presence of those required to be retested among the failure ICs, the number of the socket of the tester head with which each IC was brought into on testing, and others. The storage information to be stored is transmitted to the host computer 2 via the IC tester part 10 by means of communication means 5 such as, for example, a GPIB communication port between computers or an RS232C communication port or the like to be stored in the storage information memory means 4.
The tested ICs on the test tray are transferred to a general-purpose tray KST in the unloader section. In case this transfer operation is performed, in this second embodiment, at least two empty general-purpose trays KST are transported to the unloader section and the tested ICs are sorted out into only pass ICs and failure ICs which are to be loaded separately on the empty general-purpose trays KST. When a general-purpose tray KST is filled up with pass ICs or failure ICs, the filled general-purpose tray KST is carried back into the container 27 by transporting means. In the container 27, the general-purpose trays KST each having the failure ICs loaded thereon are received, for instance, in the lower side shelves in order from the lowermost shelf such that the first general-purpose tray KST loaded with the failure ICs is received in the lowermost shelf, the second general-purpose tray KST loaded with the failure ICs is received in the second lowermost shelf, and so on. On the other hand, the general-purpose trays KST each-having the pass ICs loaded thereon are received, for instance, in the upper side shelves in order from the uppermost shelf such that the first general-purpose tray KST loaded with the pass ICs is received in the uppermost shelf, the second general-purpose tray KST loaded with the pass ICs is received in the second uppermost shelf, and so on. In such a way, the general-purpose trays each loaded with the pass ICs and the general-purpose trays each loaded with the failure ICs are classified in the container 27.
When all of the ICs as determined to be pass ICs in the preceding two test runs are tested in the last stage IC testing apparatus 1C, the container 27 is moved from the last stage IC testing apparatus 1C to the dedicated classifying machine 3. The dedicated classifying machine 3 sorts out the tested ICs in the container 27 in accordance with the storage information sent from the host computer 2. In this case, since the storage information sent from the host computer 2 is only the information on the tested ICs transmitted from the last stage IC testing apparatus 1C, the test results of the tested ICs as determined to be failure ICs in the first and second two test runs have not been stored in the storage information memory means 4 of the host computer 2. Therefore, if it is desired to further subclassify the tested ICs as determined to be failure ICs in the first and second test runs, although it takes some time period to execute the sorting operation, the test results of the tested ICs as determined to be failure ICs in the first and second stage IC testing apparatus 1A and 1B may be transmitted from the IC testing apparatus 1A and 1B to the host computer 2 to be stored in the storage information memory means 4, and on completing all of the tests, the tested ICs as determined to be failure and received in the container 27 may also be sorted out in subclasses in accordance with the storage information transmitted from the host computer 2 using the dedicated classifying machine 3.
The IC detecting sensor 500 is provided corresponding to the number of lines (the number of transverse rows along the moving direction of the test tray) of the IC carriers 16 mounted to the test tray TST. That is, when the number of carriers 16 mounted to the test tray TST aligned in the direction orthogonal to the moving direction of the test tray TST (in the direction of a longitudinal row) is four (the number of lines is four) as shown, four IC detecting sensors 500 may be arranged at a pitch that is an interval between the four IC carriers 16 aligned in the direction of the longitudinal row. In the illustrated example, the light sources 501 are provided on the upper side of the plane through which the test tray passes, and the photodetectors 502 are provided on the lower side of the plane through which the test tray passes. The light sources 501 and the photodetectors 502 may be, of course, arranged in the reverse relation.
An aperture (through-hole) 16A is formed in a bottom plate of each IC carrier 16 as shown in FIG. 12. The photodetector 502 detects light passing through the aperture 16A. Since there is an opening through which light from the light source 501 passes (an opening through which pins of an IC loaded on the IC carrier 16 are exposed or the like) in the bottom plate of each IC carrier 16, only the light passing through the aperture 16A must be detected by the photodetector 502. For this purpose, as illustrated in FIG. 13 in enlarged size, reflective marks 503A are affixed, for instance, on one of the sides of the rectangular frame 12 of the test tray TST running parallel to the moving direction of the test tray TST, the reflective marks 503A being applied to positions of the one side of the rectangular frame 12 corresponding to the positions of the apertures 16A of the bottom plates of a set of the IC carriers 16 aligned in the moving direction of the test tray in this embodiment. Each of the reflective marks 503A has its size or length in the moving direction selected to be equal to or a little longer than the diameter of corresponding one of the apertures 16A of the bottom plates of a set of the IC carriers 16 aligned in the moving direction of the test tray. In this embodiment, the rectangular frame 12 of each test tray is made of a non-reflective material, and hence portions of the rectangular frame 12 on which the reflective marks 503A are not affixed serve as non-reflective marks 503B. Accordingly, a reflection type optical sensor 504 is located above the test tray and detects light emitted from the optical sensor 504 and reflected from one of the reflective marks 503A. With the construction as described above, only the light passing through the aperture 16A can be detected thereby detecting the presence of an IC on the test tray depending upon whether the IC detecting sensor 500 detects light or not while the optical sensor 504 is detecting light reflected from one of the reflective marks 503A.
As explained above, according to the IC testing system of the first embodiment of the present invention, no classifying process of the tested ICs is required in the handler part 11. In addition, according to the IC testing system of the second embodiment of the present invention, only a sorting operation of the tested ICs into two categories such as pass ICs and failure ICs or other suitable two categories is performed in the handler part 11. Therefore, the time interval required for testing the ICs in each IC testing apparatus can be considerably reduced and the testing process can be executed at high speed. Further, even in the second embodiment, only a classifying operation of the tested ICs into two categories may be performed in the handler part 11, and therefore, the configuration or construction of the handler part can be simplified. Consequently, the cost of the handler part 11 can be reduced. In addition, since the data stored in the storage information memory means includes the number of a socket with which an IC under test is brought into contact in the test section, if failure ICs are concentrated in the tested ICs having contacted with a specified socket, the socket can be presumed to be defective. Therefore, there is an advantage that failure of sockets in the test section can be detected. Moreover, since the dedicated classifying machine 3 performs only classifying operation, it can be manufactured at low cost. Consequently, there is an there is an advantage that a low cost IC testing system can be constructed on the whole.
In addition, according to the IC testing apparatus of the first embodiment of the present invention, a feature for detecting an IC remaining on a test tray TST which should have been emptied of the tested ICs is added thereto. Therefore, it is possible to prevent from occurring in the loader section 300 an erroneous operation that an IC is loaded on the remaining IC in the form of a stack. Consequently, an accident can be prevented that, for example, an IC drops out of the test tray in the constant temperature chamber 101 whereby a transporting apparatus located therebelow can be damaged. In addition, an erroneous classification can be prevented that the upper IC in the stack is transported without being dropped out of the test tray, is tested, and is discharged to the unloader section 400 where the upper IC is sorted out on the basis of the test results of the lower IC in the stack.
Further, according to the IC testing apparatus of the second embodiment of the present invention, even if an IC drops from the test tray during the test in the test section or during the transportation time of the test tray from the test section to the unloader section 400, the dropping of the IC can be detected. Therefore, an erroneous operation can be prevented that an IC is virtually classified from the IC pocket on the test tray in which any IC is absent in accordance with the test results stored in the memory means. That is, a classifying operation with respect to the IC pocket on the test tray in which no IC exists can be eliminated and the time required for the entire classifying operation can be reduced.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3655041Apr 23, 1970Apr 11, 1972Integrated Mechanical SystemsElectronic component handler and testerUS3896935Nov 26, 1973Jul 29, 1975Ramsey Eng CoIntegrated circuit handlerUS4170290Feb 28, 1977Oct 9, 1979Motorola, Inc.Lift and feed mechanism for high speed integrated circuit handlerUS4724965Oct 15, 1986Feb 16, 1988Willberg Hans HeinrichDevice for conveying components, particularly integrated chips, from an input magazine to an output magazineUS4776747Jan 3, 1986Oct 11, 1988Motorola Inc.High speed integrated circuit handlerUS4869636Jun 24, 1987Sep 26, 1989Reid-Ashman Manufacturing, Inc.Handler for IC packagesUS4926118Feb 22, 1988May 15, 1990Sym-Tek Systems, Inc.Test stationUS5307011Dec 4, 1991Apr 26, 1994Advantest CorporationLoader and unloader for test handlerUS5313156Dec 4, 1991May 17, 1994Advantest CorporationApparatus for automatic handlingUS5319353Oct 14, 1992Jun 7, 1994Advantest CorporationAlarm display system for automatic test handlerUS5465850Mar 5, 1993Nov 14, 1995Nec CorporationIntegrated circuit test systemUS5516028Nov 7, 1994May 14, 1996Rasp; Richard A.Process and system for temperature control and in-line testing of electronic, electromechanical and mechanical modulesUS5686834Sep 20, 1996Nov 11, 1997Ando Electric Co., Ltd.Handling systemUS5772387Jun 30, 1995Jun 30, 1998Advantest Corp.Device transfer apparatus and device reinspection method for IC handlerUS5788084Sep 4, 1995Aug 4, 1998Advantest CorporationAutomatic testing system and method for semiconductor devicesUS5865319 *Jun 27, 1996Feb 2, 1999Advantest Corp.Automatic test handler system for IC testerUS6043443 *Jan 23, 1998Mar 28, 2000Lucent Technologies Inc.Fabrication of semiconductor devicesUS6111246Apr 4, 1997Aug 29, 2000Advantest CorporationSemiconductor device testing apparatus having presence or absence detectors issuing an alarm when an error occursCA660104AMar 26, 1963Sylvania Electric ProdTesting and sorting apparatusJPH0339665A Title not availableJPH0643212A Title not availableJPH0658986A Title not availableJPH0695125A Title not availableJPH0815373A Title not availableJPH03138956A Title not availableJPH04343077A Title not availableJPS6221533A Title not availableJPS6292645A Title not availableJPS61290373A Title not available* Cited by examinerNon-Patent CitationsReference1U.S. application No. 08/832,774, Watanabe et al., filed Apr. 4, 1997.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6651202 *Mar 8, 2001Nov 18, 2003Lsi Logic CorporationBuilt-in self repair circuitry utilizing permanent record of defectsUS7348768 *Dec 17, 2003Mar 25, 2008Samsung Electronics Co., Ltd.Tray transfer unit and automatic test handler having the sameUS7427768 *Jul 14, 2006Sep 23, 2008Optopac Co., Ltd.Apparatus, unit and method for testing image sensor packagesUS7633288Sep 27, 2006Dec 15, 2009Samsung Electronics Co., Ltd.Method of testing semiconductor devices and handler used for testing semiconductor devicesUS7714310 *May 27, 2008May 11, 2010Optopac Co., Ltd.Apparatus, unit and method for testing image sensor packagesUS7786722 *Feb 29, 2008Aug 31, 2010Intel CorporationAutomated tray transfer device for prevention of mixing post and pre-test dies, and method of using sameUS7863889Feb 6, 2007Jan 4, 2011Western Digital Technologies, Inc.Component receptacle to segregate componentsUS8310266 *Mar 23, 2010Nov 13, 2012Societe Francaise De Detecteurs Infrarouges-SofradirDevice for characterizing the electro-optical performance of a semiconductor componentUS20040259402 *Dec 17, 2003Dec 23, 2004Eun-Soo LeeTray transfer unit and automatic test handler having sameUS20050139525 *Nov 28, 2003Jun 30, 2005Tung-Hung TsaiChip sorting apparatus and method for fabricating the sameUS20070075719 *Sep 27, 2006Apr 5, 2007Samsung Electronics Co., Ltd.Method of testing semiconductor devices and handler used for testing semiconductor devicesUS20070131881 *Jul 14, 2006Jun 14, 2007Young-Seok KimApparatus, unit and method for testing image sensor packagesUS20080143129 *Feb 29, 2008Jun 19, 2008Intel CorporationAutomated tray transfer device for prevention of mixing post and pre-test dies, and method of using sameUS20080224721 *May 27, 2008Sep 18, 2008Optopac Co., Ltd.Apparatus, unit and method for testing image sensor packagesUS20090314607 *Jul 27, 2006Dec 24, 2009Advantest CorporationElectronic device conveying method and electronic device handling apparatusUS20100259291 *Mar 23, 2010Oct 14, 2010Societe Francaise De Detecteurs Infrarouges-SofradirDevice for characterizing the electro-optical performance of a semiconductor componentCN100582794CJul 7, 2006Jan 20, 2010艾普特佩克股份有限公司Apparatus, unit and method for testing image sensor packages* Cited by examinerClassifications U.S. Classification209/573, 209/571International ClassificationG01R31/26, G01R31/28, G01R31/319Cooperative ClassificationG01R31/2887, G01R31/31912, G01R31/2834, G01R31/31907European ClassificationG01R31/28G5B, G01R31/319C2, G01R31/319C5, G01R31/28F3Legal EventsDateCodeEventDescriptionJun 10, 2003CCCertificate of correctionJan 20, 2006FPAYFee paymentYear of fee payment: 4Jan 14, 2010FPAYFee paymentYear of fee payment: 8Mar 21, 2014REMIMaintenance fee reminder mailedAug 13, 2014LAPSLapse for failure to pay maintenance feesSep 30, 2014FPExpired due to failure to pay maintenance feeEffective date: 20140813RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services