Source: http://www.google.com/patents/US20060003578?ie=ISO-8859-1
Timestamp: 2016-02-06 04:14:08
Document Index: 387163884

Matched Legal Cases: ['art. 9', 'arts 107', 'arts 107', 'arts 107', 'art 107', 'Application No. 10']

Patent US20060003578 - Method of manufacturing a semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThe present invention relates to a method of manufacturing a semiconductor device which may stably transfer an electrical signal by forming a plurality of via holes and contact holes to an underlying conductive layer. According to the present invention, even though a contact or via is electrically shorted,...http://www.google.com/patents/US20060003578?utm_source=gb-gplus-sharePatent US20060003578 - Method of manufacturing a semiconductor deviceAdvanced Patent SearchPublication numberUS20060003578 A1Publication typeApplicationApplication numberUS 11/195,986Publication dateJan 5, 2006Filing dateAug 2, 2005Priority dateDec 16, 2002Also published asUS6964920, US7074716, US20040121584Publication number11195986, 195986, US 2006/0003578 A1, US 2006/003578 A1, US 20060003578 A1, US 20060003578A1, US 2006003578 A1, US 2006003578A1, US-A1-20060003578, US-A1-2006003578, US2006/0003578A1, US2006/003578A1, US20060003578 A1, US20060003578A1, US2006003578 A1, US2006003578A1InventorsJae Lee, Ji KimOriginal AssigneeLee Jae S, Kim Ji AExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (7), Classifications (8), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetMethod of manufacturing a semiconductor device
US 20060003578 A1Abstract
The present invention relates to a method of manufacturing a semiconductor device which may stably transfer an electrical signal by forming a plurality of via holes and contact holes to an underlying conductive layer. According to the present invention, even though a contact or via is electrically shorted, it is possible to stably transfer the electrical signal through the other contact hole(s) or via hole(s). The present method includes: forming a first conductive line on a semiconductor substrate; forming an insulating layer on the semiconductor substrate and the first conductive line; forming a plurality of via holes by selectively etching the insulating layer in order to expose the first conductive line; forming a metal barrier on top of the insulating layer and in the via holes; and forming a plug by depositing a conductive layer sufficiently to fill the via holes, and then planarizing the conductive layer to coplanarity with the insulating layer. Images(5) Claims(13)
1-5. (canceled) 6. A method of manufacturing a semiconductor device, comprising: etching a plurality of via holes in each of a plurality of parts of an insulating layer, each plurality of via holes exposing a conductive line on a semiconductor substrate; etching trenches in the insulating layer to a certain thickness, each of said trenches enabling electrical connection of a subsequently formed conductive layer through a corresponding plurality of via holes to the exposed conductive line; forming a metal barrier on the insulating layer and in the via holes and trenches; depositing a conductive layer in the via holes and trenches sufficiently to fill the via holes and trenches; and planarizing the conductive layer until the conductive layer is substantially coplanar with the insulating layer. 7. The method of claim 6, wherein the trenches are etched before the plurality of via holes are etched. 8. The method of claim 6, wherein the plurality of via holes has a combined width equal to a width of a corresponding insulating layer part. 9. The method of claim 6, further comprising forming the first conductive line by sputtering a metal layer, patterning the metal layer using photolithography, and etching the metal layer. 10. The method of claim 6, wherein the conductive layer and the plug comprise copper. 11. The method of claim 10, wherein forming the plug and depositing the conductive layer comprises depositing a copper seed layer by physical vapor deposition (PVD) and forming a copper bulk layer on the copper seed layer by electroplating. 12. A semiconductor device, comprising: a first conductive line on a semiconductor substrate; an insulating layer on the semiconductor substrate and the first conductive line; a plurality of via holes in each of a plurality of parts of the insulating layer, each of the plurality of via holes exposing the first conductive line, and each of the parts of the insulating layer other than the via holes having a certain thickness greater than zero but less than the insulating layer thickness; trenches in the insulating layer having a certain depth; a metal barrier lining the insulating layer and the via holes; and a plug and a conductive layer filling the via holes, the conductive layer being substantially coplanar with the insulating layer. 13. The semiconductor device of claim 12, wherein the first conductive line comprises copper. 14. The semiconductor device of claim 12, wherein the conductive layer and the plug comprise copper. 15. The semiconductor device of claim 12, wherein the metal barrier comprises Ti, TiN, Ta or TaN. 16. The semiconductor device of claim 12, wherein the insulating layer comprises silicon oxide (SiO2). 17. The semiconductor device of claim 12, wherein each of the plurality of via holes has a width equal to a width of a corresponding insulating layer part.
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a semiconductor device which may stably transfer an electrical signal by forming a plurality of via holes and contact holes to an underlying conductive layer. According to the present invention, even though a contact hole or via hole is electrically shorted, it is possible to stably transfer electric signal through the other contact holes or via holes. [0003] 2. Description of the Background [0004] Generally, with higher integration of semiconductor devices, a conductive line becomes narrower. The narrowing of the conductive line may cause an increase of resistance in the conductive line and a delay of signal transfer. To solve the problem of signal transfer delay, a multi-layered conductive line structure has been introduced instead of the existing single layered conductive line structure. [0005] However, in the multi-layered conductive line structure, an interval between conductive lines is further decreased so that parasitic capacitance between conductive lines on the same layer is increased and signal transfer delay of the semiconductor device further deepens. Particularly, in case of a conductive line with finer line width, signal transfer delay by parasitic capacitance between conductive lines has a marked effect on operational features of semiconductor devices (such as signal transmission speed). To reduce parasitic capacitance between conductive lines, it is preferable to reduce the thickness of conductive line and to thicken a second insulating layer. Accordingly, many proposals have been provided, wherein the conductive line is formed of low specific resistance material, for example, copper presently used, and the second insulating layer is formed of low permittivity materials. However, in case of copper, since vapor pressure of etching by-products is low, it is difficult to perform a dry etching. [0006] One solution to this problem involves a damascene process, which forms a copper conductive line by forming a via hole or contact hole through the second insulating layer, filling the via hole or contact hole with copper and planarizing the copper layer. [0007] The copper conductive line adapted to the damascene structure has excellent electrical conductivity and low resistance compared with an aluminum or aluminum alloy conductive line, thus enabling finer conductive features and high integration of the conductive line while maintaining constant carrier current. The copper conductive line also has excellent electroplating characteristics, thus increasing reliability of the semiconductor device. [0008] A dual damascene process is performed according to the following steps. [0009] First, in a state where a lower conductive line is formed on a semiconductor substrate, a second insulating layer is formed on top of the substrate and the lower conductive line, and a certain portion of the second insulating layer is etched and removed as to expose the lower conductive line, thus forming a via hole and a trench. Then, a thin metal barrier is formed in the via hole and the trench in order to be in contact with the exposed lower conductive line, and a conductive layer, for example, a copper layer, is deposited to completely fill the via hole and the trench. Then, the copper layer is planarized with the second insulating layer, simultaneously forming a plug and an upper conductive line in the via hole and the trench. [0010] Recently, as the design rules of semiconductor devices are refined, line widths of via holes and trenches are also narrowed. Thus, conductive layers such as the copper layer do not always completely fill the via hole and the trench, thus causing a problem in that a contact characteristic with the lower conductive line is degraded or the device fails as a result of an electrical short. [0011] In the conventional damascene or dual damascene process, one via hole and one trench are formed for the plug and the upper conductive line. Thus, when the conductive layer does not completely fill the via hole and trench, an incomplete contact with the lower conductive line results, and a disconnection between the upper and lower conductive lines may be caused, degrading the electrical characteristics of the entire semiconductor device. [0012] U.S. Pat. No. 5,918,149 (assigned to Advanced Micro Devices, Inc.), issued Jun. 29, 1999, discloses a method of improving an embedment property of the conductive layer in the via hole and trench. However, the method does not provide a fundamental solution for resolving the problem of degrading electrical characteristic due to the incomplete filling of the conductive layer. SUMMARY OF THE INVENTION [0013] Accordingly, the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device, which may stably transfer an electrical signal by forming a plurality of via holes and contact holes to an underlying conductive layer. [0014] In order to accomplish at least the above object, in whole or in part, there is provided a method of manufacturing a semiconductor device, including: forming a first conductive line on a semiconductor substrate; forming an insulating layer on top of the semiconductor substrate and the first conductive line; forming a plurality of via holes by selectively etching the insulating layer in order to expose the first conductive line; forming a metal barrier on the insulating layer and in the via holes; and forming a plug by depositing a conductive layer to sufficiently fill the via holes; and then planarizing the conductive layer until it is substantially coplanar with the insulating layer. [0015] The first conductive line and the plug may be formed of copper. [0016] According to the present invention, a plurality of connecting portions of the conductive lines, i.e., contact holes or via holes, of the semiconductor device are formed so that even upon disconnection of one contact hole or via hole, an electrical signal is stably transferred through another contact hole or via hole.
BRIEF DESCRIPTION OF THE DRAWINGS [0017] The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: [0018] FIGS. 1 to 8 illustrate a method of manufacturing a semiconductor device according to the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0019] Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used to designate the same or similar components, and so repetition of the description on the same or similar components will be omitted. [0020] FIGS. 1 to 8 illustrate a method of manufacturing a semiconductor device according to the present invention. [0021] First, as shown in FIG. 1, a first insulating layer 102 is deposited on a semiconductor substrate 101 using a chemical vapor deposition (CVD) process. The semiconductor substrate 101 may be a semiconductor substrate having an impurity diffusion region (not shown), or a lower conductive line. [0022] A first conductive line 103 is formed by performing deposition of a lower metal layer on the first insulating layer by sputtering, etc. and, then, by selectively patterning the lower metal layer using a photolithography process and an etching process. [0023] Then, a second insulating layer 104 is deposited in a certain thickness on top of the substrate, including on the first conductive line 103 and the first insulating layer 102. Herein, the second insulating layer 104 may be composed of Tetra Ethyl OrthoSilicate (TEOS) and/or Spin On Glass (SOG), and the major element thereof is silicon oxide (SiO2). [0024] Then, a certain portion of the second insulating layer is selectively patterned to form (i) a via hole exposing the first conductive line and (ii) a trench etched into the second insulating layer according to a pattern of a second conductive line, an upper conductive line. In the subsequent process, a plug connecting the upper conductive line (the second conductive line) and a lower conductive line (the first conductive line) is formed in the via hole, and the upper conductive line is formed in the trench. [0025] The via hole and the trench are successively patterned according to the steps illustrated in FIGS. 2 to 4. [0026] As shown in FIG. 2, a photoresist is formed on top of the substrate including on the second insulating layer 104, and a first photoresist pattern 105 is formed so as to expose parts 107 a of the second insulating layer 104, where a plurality of via holes, multiple via holes, will be formed. Then, using the first photoresist pattern 105 as an etching mask, the exposed parts 107 a of the second insulating layer 104 is removed to a certain depth or thickness using a dry etching technique such as a Reactive Ion Etching (RIE). [0027] Herein, the process of removing the parts 107 a of the second insulating layer 104 with the dry etching is performed so as not to expose the lower conductive line, and a width of the removed second insulating layer 104 equals an overall width of the multiple via holes of the present invention, the width of a conventional via hole. [0028] Then, as shown in FIG. 3, the first photoresist pattern 105 is removed and a second photoresist pattern 106 is formed on the second insulating layer. A portion exposed by the second photoresist pattern 106 corresponds to respective via hole regions constituting a plurality of via holes. [0029] Then, as shown in FIG. 4, using the second photoresist pattern as an etching mask, the exposed second insulating layer 104 is etched to expose the first conductive line. Herein, the second photoresist pattern defines a plurality of via holes thus to form a plurality of via holes 107 within etched part 107 a. [0030] A characteristic feature of the present invention is to form a plurality of via holes through the above-mentioned processes, which processes are herein referred to a via hole adapted to a single Damascene process as an example. [0031] The method of forming the multiple via holes according to the present invention can be adapted to a Dual Damascene process besides the single Damascene process. That is, a plurality of via holes are formed using the second photoresist pattern and, additionally, the trench can be formed using another photoresist pattern (e.g., first photoresist pattern 105 or a third photoresist pattern as described below). The trench formation process and the formation process of the plug and the second conductive line as the upper conductive line in the via hole and the trench will be now described in detail with reference to FIGS. 5 to 8. [0032] First, as shown in FIG. 5, after the second photoresist pattern 106 is removed, a photoresist is formed on top of the substrate including in the multiple via holes consisting of a plurality of via holes 107 (see, e.g., FIG. 4 or FIG. 6). Then, a third photoresist pattern 108 is formed so as to expose parts of the second insulating layer 104, where trenches will be formed, using a photolithography process. Then, using the third photoresist pattern 108 as an etching mask, the exposed second insulating layer 104 is removed to a certain depth or thickness by etching the exposed second insulating layer. [0033] After the via holes 107 and the trench 109 are formed through the successive processes, as shown in FIG. 6, a metal barrier 110 is formed in the via hole and on the trench. Herein, the metal barrier 110 can be formed by the CVD process of Ti or TiN, or by the sputtering process of Ta or TaN. [0034] Then, as shown in FIG. 7, in order to form a second conductive line, an upper conductive line on the metal barrier 110, an upper conductive layer 111 such as metal is deposited and formed by CVD or sputtering. Herein, the upper conductive layer 111 can be composed of copper, etc. In case of using copper, a copper seed layer (not shown) for forming a copper bulk layer is deposited and formed on the metal barrier by PVD process and, using an electroplating method employing the copper seed layer, the copper bulk layer is formed on the copper seed layer, in a thickness sufficient to fill the contact hole 107 and the trench 109. Accordingly, a connecting portion between conductive lines and a layer of the upper conductive line are simultaneously formed. [0035] As shown in FIG. 8, the copper bulk layer 111 is planarized to expose the surface of the second insulating layer, thus forming the second conductive line 111 b, the upper conductive line electrically connected with the first conductive line 103, and the plug 111 a, without a separate patterning process. Herein, planarizing is conducted by a chemical mechanical polishing (CMP) process. [0036] The method of manufacturing the semiconductor device as described above has the following effects. [0037] A plurality of connecting portions of conductive lines, i.e., contact holes or via holes, of the semiconductor device are formed in an area conventionally used for a single contact hole or via hole, so that even upon disconnection of one contact hole or via hole, an electrical signal is stably transferred through the other contact hole or via hole. [0038] Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. [0039] The entire disclosure of Korean Patent Application No. 10-2002-0080224 filed on Dec. 16, 2002 including specification, claims, drawings and summary are incorporated herein by reference in its entirety. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5918149 *Feb 16, 1996Jun 29, 1999Advanced Micro Devices, Inc.Deposition of a conductor in a via hole or trenchUS6326301 *Jul 13, 1999Dec 4, 2001Motorola, Inc.Method for forming a dual inlaid copper interconnect structureUS6380003 *Dec 22, 1999Apr 30, 2002International Business Machines CorporationDamascene anti-fuse with slot viaUS6498399 *Sep 8, 1999Dec 24, 2002Alliedsignal Inc.Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuitsUS6734090 *Feb 20, 2002May 11, 2004International Business Machines CorporationMethod of making an edge seal for a semiconductor device* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7378342 *Aug 27, 2004May 27, 2008Micron Technology, Inc.Methods for forming vias varying lateral dimensionsUS7528491Sep 5, 2006May 5, 2009Micron Technology, Inc.Semiconductor components and assemblies including vias of varying lateral dimensionsUS7871927 *Oct 15, 2007Jan 18, 2011Cufer Asset Ltd. L.L.C.Wafer via formationUS20050142857 *Jun 28, 2004Jun 30, 2005Lee Se Y.Method for forming metal line in semiconductor deviceUS20060046471 *Aug 27, 2004Mar 2, 2006Kirby Kyle KMethods for forming vias of varying lateral dimensions and semiconductor components and assemblies including sameUS20070001168 *Sep 5, 2006Jan 4, 2007Kirby Kyle KSemiconductor components and assemblies including vias of varying lateral dimensionsUS20080090413 *Oct 15, 2007Apr 17, 2008John TrezzaWafer via formation* Cited by examinerClassifications U.S. Classification438/638, 257/E21.577, 438/644International ClassificationH01L21/4763, H01L21/768, H01L21/28Cooperative ClassificationH01L21/76816European ClassificationH01L21/768B2LLegal EventsDateCodeEventDescriptionFeb 10, 2006ASAssignmentOwner name: DONGBUANAM SEMICONDUCTOR INC., KOREA, REPUBLIC OFFree format text: MERGER;ASSIGNOR:DONGBU ELECTRONICS CO., LTD.;REEL/FRAME:017251/0452Effective date: 20041221May 15, 2006ASAssignmentOwner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: CHANGE OF NAME;ASSIGNOR:DONGBUANAM SEMICONDUCTOR INC.;REEL/FRAME:017616/0966Effective date: 20060328Jan 8, 2010FPAYFee paymentYear of fee payment: 4Feb 21, 2014REMIMaintenance fee reminder mailedJul 11, 2014LAPSLapse for failure to pay maintenance feesSep 2, 2014FPExpired due to failure to pay maintenance feeEffective date: 20140711RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services