Source: https://patents.google.com/patent/US20030199262A1/en
Timestamp: 2018-06-20 10:00:52
Document Index: 456218532

Matched Legal Cases: ['art 216', 'art 216', 'art 216', 'art 218', 'art 216', 'art 217']

US20030199262A1 - Multi-clock domain data input-processing device having clock-reciving locked loop and clock signal input method thereof - Google Patents
Multi-clock domain data input-processing device having clock-reciving locked loop and clock signal input method thereof Download PDF
US20030199262A1
US20030199262A1 US10288540 US28854002A US20030199262A1 US 20030199262 A1 US20030199262 A1 US 20030199262A1 US 10288540 US10288540 US 10288540 US 28854002 A US28854002 A US 28854002A US 20030199262 A1 US20030199262 A1 US 20030199262A1
US7038971B2 (en )
[0006]FIG. 1 illustrates a block diagram of a conventional data input-processing unit including a first processing block (hereinafter referred to as memory controller 100) and a second processing block 200. Although such a system typically has a bi-directional data strobe function, wherein first processing block 100 provides data and a data strobe signal to second processing block 200, and the second processing block 200 provides data and a data strobe signal to the first processing block 100, for purposes of brevity in this discussion, only the forward path from first processing block 100 to second processing block 200 will be discussed. It may be understood that the reverse path has a duplicate description.
[0010]FIG. 3 illustrates a block diagram of a conventional SDRAM 300 having a signal-transmitting delay locked loop T_DLL 330 and a bi-directional data strobe function. FIG. 4 illustrates a timing diagram of a data output operation of the signal-transmitting delay locked loop shown in FIG. 3.
[0014]FIG. 5 illustrates a block diagram of a conventional DDR-SDRAM. FIG. 6 illustrates an operational timing diagram of the write operations of the DDR-SDRAM shown in FIG. 5.
As shown in FIGS. 5 and 6, a DDR-SDRAM is constructed with memory cell arrays 1, 2, word drivers 3, 4, I/O circuits 5A, 6A, write circuits 7, 8, sense amplifier 9, 10, 11, 12, column decoders 13, 14, command decoder 15A, burst counter 16A and column control circuit 17A. As shown in FIG. 6, if a write command is input to a command input port CMD, a data strobe signal DS is applied to I/O circuits 5A, 6A in order to enable the standard tDQSS, which shows the timing difference between data strobe signal DS and clock signal CLK. This timing difference is typically maintained within a regulated range. Assuming that write data D0, D1, D2 and D3 are input as indicated by waveform DQ in FIG. 6 in response to rising and falling edges of the data strobe signal DS, write operation controlling signals WO , W1 are output from column control circuit 17A after a predetermined time interval (for instance, a timing interval of 2 clocks after an input of a command) in response to a read/write command RWCMD output by the command decoder 15A.
On the other hand, when address inputs IA0-IAj are generated in correspondence to addresses A0-Aj designated by CPU, address signals YP0-YPj are output from the burst counter 16A in response to address control signal YALW supplied by the command decoder 15A. After one clock period, an address obtained by adding as much as 2 to the address signals YP0-YPj is output from the burst counter 16A in response to an address control signal NYAL. At this time, data D0 designated by even numbers and data D1 designated by odd numbers are output from data input/output circuits 5A, 6A as data outputs RWBS and RWBSB in response to the write operation control signals W0, W1, respectively. After the data D0, D1 are output from write circuits 7, 8 as write inputs IO and IOB, they are written to memory cells of column selection lines CSL0 and CSL1 designated by addresses YP0, YP1. Then, the data D2, D3 output as write inputs IO and IOB are written to memory cells of column selection lines CSL2 and CSL3 defined by addresses YP0, YP1(+2).
[0018]FIGS. 1, 3 and 5 illustrate a conventional scheme having signal-transmitting DLL only for a case of a data transmission. The signal-receiving DLL is typically required at an input unit if a signal-receiving operation requires a higher frequency. Further, it may be necessary to apply a unidirectional data strobe signal and signal-receiving DLL in order to secure timing estimation.
[0037]FIG. 1 illustrates a block diagram of a conventional data input-processing unit;
[0038]FIG. 2 illustrates an operational timing diagram of the data input unit shown in FIG. 1;
[0039]FIG. 3 illustrates a block diagram of a conventional synchronous semiconductor memory device having a signal-transmitting delay locked loop;
[0040]FIG. 4 illustrates a timing diagram of data output operation showing the function of the signal-transmitting delay locked loop shown in FIG. 3;
[0041]FIG. 5 illustrates a block diagram of a conventional double data rate synchronous random access memory;
[0042]FIG. 6 illustrates an operational timing diagram showing the write operations of the synchronous random access memory shown in FIG. 5;
[0043]FIG. 7 illustrates a block diagram of a conventional data input-processing unit having a signal-receiving delay locked loops;
[0044]FIG. 8 illustrates an operational timing diagram of the data input unit shown in FIG. 7;
[0045]FIG. 9 illustrates a block diagram of a data input-processing unit having a signal-receiving delay locked loops according to a preferred embodiment of the present invention;
[0046]FIG. 10 illustrates an operational timing diagram of the data input unit shown in FIG. 9;
[0047]FIG. 11 illustrates a block diagram of a data input-processing unit having a signal-receiving delay locked loop according to a second embodiment of the present invention;
[0048]FIG. 12 illustrates a block diagram of a data input-processing unit having a signal-receiving delay locked loop according to a third embodiment of the present invention;
[0049]FIG. 13 illustrates a block diagram of a delay locked loop according to the present invention;
[0050]FIG. 14 illustrates an exemplary diagram of a delay locked loop constructed according to FIG. 13; and
[0051]FIGS. 15 through 17 illustrate exemplary block diagrams of circuits for separating clock signals during conversion of a signal-receiving clock in accordance with the present invention.
[0054]FIG. 7 illustrates a block diagram of a conventional data input-processing unit having a signal-receiving delay locked loops (DLLs). FIG. 8 illustrates an associated operational timing diagram.
[0062]FIG. 9 illustrates a block diagram of a data input-processing unit having a signal-receiving DLL in accordance with a preferred embodiment of the present invention. The structure of FIG. 9 is similar to the structure of FIG. 7, except for the addition of input buffers 223 and 233, which each have an output connected to a clock terminal of the data input part 216, thereby allowing first and second clocking signals DS, CLK, to be directly applied to the clock terminals of data input part 216 through buffers 223 and 233, bypassing first and second delay locked loops 220 and 230, respectively, while signals outputted from first and second delay locked loops 220 and 230 are applied to all other parts of the data input-processing unit.
[0065]FIG. 10 illustrates an operation timing diagram of the data input part shown in FIG. 9 with waveforms A2, B2, C2, which are similar to waveforms A1, B1, C1 in FIG. 8. By incorporating the embodiment of the present invention, tDQSS=tCC−(T1+T2), since the time delay intervals T3, T4 of FIG. 8 are eliminated. In other words, despite the use of DS_DLL 220 and R_DLL 230, the operation timing diagram of FIG. 10 is identical to that of FIG. 2, thus providing a timing margin that is adequate for high frequency operations.
[0067]FIG. 11 illustrates a block diagram of a data input-processing unit having a signal-receiving DLL in accordance with a second embodiment of the present invention. As shown in FIG.11, the data input-processing unit includes a clock signal-receiving synchronous circuit R_DLL 230 which generates a signal-receiving internal clock ICLK as an output clocking signal. By phase-delaying the second clock signal CLK by a predetermined time; a data input part 216 inputs data in sequential response to the first clocking signal DS that is applied simultaneously with the application of the data and to the second clocking signal CLK that is applied at a timing different from that of the first clock signal DS. An input-processing part 218 processes the data output from the data input part 216 in response to the signal-receiving internal clock ICLK of the clock signal-receiving synchronous circuit (clock signal receiving locked loop) R_DLL 230.
[0069]FIG. 12 illustrates a block diagram of a data input-processing unit having a signal-receiving DLL according to a third embodiment of the present invention. The structure includes only DS_DLL 220 rather than the R_DLL 230 and DS_DLL 220 combination of the preferred embodiment. As in the other embodiments, the clocking signal bypasses the DS_DLL 220, and externally received data strobe signal DS is directly applied to the signal-receiving clock conversion part CCP through a buffer 223.
[0070]FIGS. 13 and 14 illustrate representative DLLs, such as R_DLL 230 and DS_DLL 220 shown in FIGS. 9, 11 and 12. As shown in FIG. 13, a DLL (i.e., 220, 230) may include: a signal-receiving buffer 211, which receives an input clock signal IN; a variable delay unit 213, which outputs an output clock signal OUT by delaying a signal-receiving clock signal RCLK output from the signal-receiving buffer 211 in response to an applied digital control data CON; a phase detector 215, which detects a difference in the phase between signal-receiving clock signal RCLK and feedback clock signal FCLK to generate shifting control signals UP, DOWN; and a delay control part 217, which supplies to the variable delay unit 213 the digital control data CON to increase or decrease the amount of delay in response to the shifting control signal of the phase detector 215. Also, the DLL 220, 230 preferably includes a clock path replica 219 to generate the feedback clock signal FCLK using the output clock signal OUT and a dummy signal-receiving buffer 212. The time delay of the dummy signal-receiving buffer 212 is preferably the same as that of the signal-receiving buffer 211.
[0071]FIG. 14 illustrates an exemplary diagram of a DLL, which includes a signal-receiving buffer 211 a; a delay unit 213 a; a phase detector 215 a, which generates a shifting control signal SR, SL to indicate shift-right or shift-left operations; a shift register 217 a, which controls the delay unit 213 a. The shift register 217 a provides the digital control data to increase or decrease the amount of time delay in response to the shifting control signal of the phase detector 215 a; a dummy buffer 219 a and a dummy signal-receiving buffer 212 a. Preferably, the delay amount of the dummy signal-receiving buffer 212 a is the same as that of the signal-receiving buffer 211 a, and the delay amount of the dummy buffer 219 a is the same as that of a buffer (not shown) using the output clock signal.
The DDR-SDRAM has a very wide operational frequency range of tCK=7 ns-15 ns, so that DLL is generally constructed to control the time delay hierarchically. In considering power dissipation, a digital DLL may be used to store locking data as digital codes. Preferably, a DLL is not being operated when the DLL is not needed, thereby reducing power consumption.
[0076]FIGS. 15 through 17 illustrate block diagrams of exemplary circuits for separating clock signals during signal-receiving clock conversion in accordance with the present invention.
a data input part that inputs data in sequential response to the first clock signal applied when data is applied and a second clock signal having a timing different from that of the first clock signal; and
a second latch circuit, which latches the latched data output from the first latch circuit in response to a second clock signal having a timing different from the first clock signal for a signal-receiving clock conversion; and
US20030199262A1 true true US20030199262A1 (en) 2003-10-23
US7038971B2 US7038971B2 (en) 2006-05-02
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US7038971B2 (en) 2006-05-02 grant