Source: http://www.google.com/patents/US6341081?dq=actionscript
Timestamp: 2014-09-21 05:02:21
Document Index: 477401485

Matched Legal Cases: ['art 1', 'art 2', 'art 1', 'art 3', 'art 4', 'art 5', 'art 6', 'art 5', 'art 7', 'art 8', 'art 9', 'art 7', 'art 1', 'art 75']

Patent US6341081 - Circuit for driving nonvolatile ferroelectric memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA nonvolatile ferroelectric memory has a plurality of bitlines, a plurality of wordlines and plate lines formed in a direction crossing the bitlines, and a reference bitline on one side of the plurality of bitlines. A cell array has a plural repetition of the plurality of bitlines and the reference bitline...http://www.google.com/patents/US6341081?utm_source=gb-gplus-sharePatent US6341081 - Circuit for driving nonvolatile ferroelectric memoryAdvanced Patent SearchPublication numberUS6341081 B2Publication typeGrantApplication numberUS 09/778,948Publication dateJan 22, 2002Filing dateFeb 8, 2001Priority dateMay 13, 1998Fee statusPaidAlso published asDE19921259A1, DE19921259B4, US6188599, US20010007531Publication number09778948, 778948, US 6341081 B2, US 6341081B2, US-B2-6341081, US6341081 B2, US6341081B2InventorsHee Bok KangOriginal AssigneeHyundai Electronics Industries Co. Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (19), Referenced by (3), Classifications (14), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetCircuit for driving nonvolatile ferroelectric memoryUS 6341081 B2Abstract A nonvolatile ferroelectric memory has a plurality of bitlines, a plurality of wordlines and plate lines formed in a direction crossing the bitlines, and a reference bitline on one side of the plurality of bitlines. A cell array has a plural repetition of the plurality of bitlines and the reference bitline on one side thereof, a sense amplifier array having a plurality of sense amplifiers for sensing data on the bitlines and the reference bitlines in the cell array, a wordline and plateline driver for selective application of driving signals to the wordlines and the platelines, and a switching unit for selective turning on/off of the bitlines, the reference bitlines, and the input/output nodes on the sense amplifier array, whereby improving chip operation performance and lifetime of the chip.
What is claimed is: 1. A nonvolatile ferroelectric memory comprising: p1 a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at a corresponding crossing point of the bitlines with the wordlines and the platelines;
a first reference cell block on one side of the first main cell block, the first reference cell block having first and second reference bitlines formed in a direction crossing the wordlines and the platelines and a reference cell on a corresponding crossing point of the first and second reference bitlines with the wordlines and the platelines; a first lower sense amplifier block having a plurality of sense amplifiers, each sense amplifier with a bitline input/output node connected to an odd numbered bitline for sensing a data on the odd numbered bitline and a reference bitline input/output node connected to the first reference bitline for sensing a data on the first reference bitline; a first upper sense amplifier block having a plurality of sense amplifiers, each sense amplifier with a bitline input/output node connected to an even numbered bitline for sensing a data on the even numbered bitline and a reference bitline input/output node connected to the second reference bitline for sensing a data on the second reference bitline; a first switching unit for selective connection of the odd numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first lower sense amplifier block; a second switching unit for selective connection of the reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first lower sense amplifier block; a third switching unit for selective connection of the even numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first upper sense amplifier block; a fourth switching unit for selective connection of the reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first upper sense amplifier block; and first and second pull-up transistors for pulling-up levels of the first and second reference bitlines to a level of a power supply voltage, respectively. 2. The nonvolatile ferroelectric memory of claim 1, wherein there are n number of bit lines for each of the first and second reference bitlines formed adjacent to the last bitline, where n is an even number at least equal to 2.
3. The nonvolatile ferroelectric memory of claim 1, wherein the first main cell block and the first reference cell block are repeated to form one cell array and the first upper and lower sense amplifier blocks are repeated to form upper and lower sense amplifier arrays.
4. The nonvolatile ferroelectric memory of claim 1, wherein the first, second, third and fourth switching units include NMOS transistors or PMOS transistors.
5. The nonvolatile ferroelectric memory of claim 1, further comprising a wordline and plateline driver disposed on one side of the first main cell block for applying driving signals to the wordlines and the platelines.
6. A nonvolatile ferroelectric memory comprising:
a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at every second crossing point of the bitlines with the wordlines and the platelines; a first reference cell block on one side of the first main cell block, the first reference cell block having first and second reference bitlines formed in a direction crossing the wordlines and the platelines and a reference cell on every second crossing point of the first and second reference bitlines with the wordlines and the platelines; a first lower sense amplifier block having a plurality of sense amplifiers, each sense amplifier having a bitline input/output node connected to an odd numbered bitline for sensing a data on the odd numbered bitline and a reference bitline input/output node connected to the first reference bitline for sensing a data on the first reference bitline; a first upper sense amplifier block having a plurality of sense amplifiers, each sense amplifier having a bitline input/output node connected to an even numbered bitline for sensing a data on the even numbered bitline and a reference bitline input/output node connected to the second reference bitline for sensing a data on the second reference bitline; a first switching unit for selective connection of the odd numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first lower sense amplifier block; a second switching unit for selective connection of the first reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first lower sense amplifier block; a third switching unit for selective connection of the even numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first upper sense amplifier block; a fourth switching unit for selective connection of the second reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first upper sense amplifier block; and pull-up transistors for pulling-up levels of the first and second reference bitlines to a level of a power supply voltage, respectively. 7. The nonvolatile ferroelectric memory of claim 6, wherein there are n number of bitlines, each of the first and second reference bitlines formed adjacent to the last bitline of n number of bit lines, where n is an even number at least equal to 2.
8. The nonvolatile ferroelectric memory of claim 6, wherein the first main cell block and the first reference cell block are repeated to form one cell array, the first lower sense amplifier block are repeated to form one lower sense amplifier array and the first upper sense amplifier block are repeated to form one upper sense amplifier array.
9. A nonvolatile ferroelectric memory comprising:
a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at a corresponding crossing point of the bitlines with the wordlines and the platelines; a first reference cell block on one side of the first main cell block, the first reference cell block having first and second reference bitlines formed in a direction crossing the wordlines and the platelines and a reference cell on a corresponding crossing point of the first and second reference bitlines with the wordlines and the platelines; an odd sense amplifier block having a plurality of sense amplifiers, each sense amplifier with a bitline input/output node connected to an odd numbered bitline for sensing a data on the odd numbered bitline and a reference bitline input/output node connected to the first reference bitline for sensing a data on the first reference bitline; and an even sense amplifier block having a plurality of sense amplifiers, each sense amplifier with a bitline input/output node connected to an even numbered bitline for sensing a data on the even numbered bitline and a reference bitline input/output node connected to the second reference bitline for sensing a data on the second reference bitline. 10. The nonvolatile ferroelectric memory of claim 9, further comprising: p1 an odd switching circuit that selectively connects the odd numbered bitlines to the bitline input/output nodes on the sense amplifiers in the odd sense amplifier block and selectively connects the reference bitline to the first reference bitline input/output node on each of the sense amplifiers in the odd sense amplifier block; and
an even switching circuit that selectively connects the even numbered bitlines to the bitline input/output nodes on the sense amplifiers in the even sense amplifier block and selectively connects the second bitline to the reference bitline input/output node on each of the sense amplifiers in the even sense amplifier block. 11. The nonvolatile ferroelectric memory of claim 10, wherein the odd switching circuit comprises:
a first switching unit for selective connection of the odd numbered bitlines to the bitline input/output nodes on the sense amplifiers in the odd sense amplifier block; and a second switching unit for selective connection of the first reference bitline to the reference bitline input/output node on each of the sense amplifiers in the odd lower sense amplifier block. 12. The nonvolatile ferroelectric memory of claim 10, wherein the even switching circuit comprises:
a first switching unit for selective connection of the even numbered bitlines to the bitline input/output nodes on the sense amplifiers in the even sense amplifier block; and a second switching unit for selective connection of the second reference bitline to the reference bitline input/output node on each of the sense amplifiers in the even sense amplifier block. 13. The nonvolatile ferroelectric memory of claim 10, further comprising first and second pull-up transistors for pulling-up levels of the first and second reference bitlines to a level of a power supply voltage, respectively.
14. The nonvolatile ferroelectic memory of claim 9, wherein there are n number of bit lines for each of the first and second reference bitlines formed adjacent to the last bitline, where n is an even number at least equal to 2.
15. The nonvolatile ferroelectric memory of claim 9, wherein the first main cell block and the first reference cell block are repeated to form one cell array and the even and odd sense amplifier blocks are repeated to form even and odd sense amplifier arrays.
16. The nonvolatile ferroelectric memory of claim 9, further comprising a wordline and plateline driver disposed on one side of the first main cell block for applying driving signals to the wordlines and the platelines.
17. A nonvolatile ferroelectric memory comrising:
a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at every second crossing point of the bitlines with the wordlines and the platelines; a first reference cell block on one side of the first main cell block, the first reference cell block having first and second reference bitlines formed in a direction crossing the wordlines and the platelines and a reference cell on every second crossing point of the first and second reference bitlines with the wordlines and the platelines; an odd sense amplifier block having a plurality of sense amplifiers, each sense amplifier having a bitline input/output node connected to an odd numbered bitline for sensing a data on the odd numbered bitline and a reference bitline input/output node connected to the first reference bitline for sensing a data on the first reference bitline; and an even sense amplifier block having a plurality of sense amplifiers, each sense amplifier having a bitline input/output node connected to an even numbered bitline for sensing a data on the even numbered bitline and a reference bitline input/output node connected to the second reference bitline for sensing a data on the second reference bitline. 18. The nonvolatile ferroelectric memory device of claim 17, further comprising:
an odd switching circuit that selectively connects the odd numbered bitlines to the bitline input/output nodes on the sense amplifiers in the odd sense amplifier block and selectively connects the first reference bitline to the reference bitline input/output node on each of the sense amplifiers in the odd sense amplifier block; and an even switching circuit that selectively connects the even numbered bitlines to the bitline input/output nodes on the sense amplifiers in the even sense amplifier block and selectively connects the second reference bitline to the reference bitline input/output node on each of the sense amplifiers in the even sense amplifier block. 19. The nonvolatile ferroelectric memory device of claim 18, further comprising pull-up transistors for pulling-up levels of the first and second reference bitlines to a level of a power supply voltage, respectively.
20. The nonvolatile ferroelectric memory device of claim 18, wherein said odd switching circuit comprises:
a first switching unit for selective connection of the odd numbered bitlines to the bitline input/output nodes on the sense amplifiers in the odd sense amplifier block; and a second switching unit for selective connection of the first reference bitline to the reference bitline input/output node on each of the sense amplifiers in the odd sense amplifier block. 21. The nonvolatile ferroelectric memory device of claim 18, wherein said even switching circuit comprises:
a first switching unit for selective connection of the even numbered bitlines to the bitline input/output nodes on the sense amplifiers in the even sense amplifier block; and a second switching unit for selective connection of the second reference bitline to the reference bitline input/output node on each of the sense amplifiers in the odd sense amplifier block. 22. The nonvolatile ferroelectric memory of claim 18, wherein there are n number of bitlines, each of the first and second reference bitlines formed adjacent to the last bitline of n number of bit lines, where n is an even number at least equal to 2.
23. The nonvolatile ferroelectric memory of claim 22, wherein the first main cell block and the first reference cell block are repeated to form one cell array, the odd sense amplifier block are repeated to form one odd sense amplifier array and the even sense amplifier block are repeated to form even sense amplifier array.
This application is a Divisional of application Ser. No. 09/240,887 filed Feb. 1, 1999 now U.S. Pat. No. 6,188,599.
A ferroelectric random access memory (FRAM) has a data processing speed as fast as a DRAM and conserves data even after the power is turned off. The FRAM includes capacitors similiar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not lost even after eliminating an electric field applied thereto.
FIG. 1A illustrates a general hysteresis loop of a ferroelectric substance, and FIG. 1B illustrates a construction of a unit capacitor in a background art ferroelectric memory. As shown in the hysteresis loop in FIG. 1A, a polarization induced by an electric field does not vanish, but remains at a certain portion (�d� or �a� state) even after the electric field is cleared due to an existence of a spontaneous polarization. These �d� and �a� states may be matched to binary values of �1� and �0� for use as a memory cell. Referring to FIG. 1B, the state in which a positive voltage is applied to a node 1 is a �c� state in FIG. 1A, the state in which no voltage is applied thereafter to the node 1 is a �d� state. Opposite to this, if a negative voltage is applied to the node 1, the state moves from the �d� to an �f� state. If no voltage is applied to the node 1, thereafter the state moves to an �a� state. If a positive voltage is applied again, the states moves the �c� state via the �b� state. At the end, even if there is no voltage applied on both ends of a capacitor, a data can be stored in stable state of �a� and �d�. On the hysteresis loop, �c� and �d� states correspond to a binary logic value of �1�, and �a� and �f� states correspond to a binary logic value �0�.
FIGS. 3a and 3 b together illustrate a circuit for driving the background art one transistor/one capacitor (1T/1C) ferroelectric memory of FIG. 2. A reference voltage generating part 1 generates a reference voltage, and a reference voltage stabilizing part 2 having a plurality of transistors Q1�Q4 and a capacitor C1 stabilizes a reference voltage on two adjacent bitlines B1 and B2 because the reference voltage from the reference voltage generating part 1 can not be provided to a sense amplifier directly. A first reference voltage storage part 3 having a plurality of transistors Q6�Q7 and capacitors C2�C3 stores a logic value �0� in adjacent bit lines. A first equalizing part 4 having a transistor Q5 equalizes adjacent two bitlines.
A first main cell array part 5 connected to wordlines W/L and platelines P/L different from one another stores data, and a first sense amplifier part 6 having a plurality of transistors Q10�Q15 and P-sense amplifiers PSA senses a data in a cell selected by the wordline from the plurality of cells in the main cell array part 5. A second main cell array part 7 connected to wordlines and platelines different from one another stores data, and a second reference voltage storage part 8 having a plurality of transistors Q�Q29 and capacitors C9�C10 stores a logic value �1� and a logic value �0� in adjacent bit lines. A second sense amlifier part 9 having a plurality of transistors Q15�Q24 and N-sense amplifiers NSA senses a data in the second main cell array part 7.
That is, referring to FIG. 1, since the case of a canceled data is a case when a state is changed from �d� to �f�, and the case of a data not canceled is a case when a state is changed from �a� to �f�, if the sense amplifier is enable after a certain time, in the case of the canceled data, the data is amplified to provide a logic value �1�, and, in the case of the data not canceled, the data is amplified to provide a logic value �0�. After the sense amplifier amplifies and provides a signal, since the cell should be recovered of an original data, during �high� is applied to a corresponding line, the plateline is disabled from �high� to �low�. However, in the background art 1T/1C ferroelectric memory, in which the reference cell is operative more than the main memory cell in data input and output operations, the reference cell degrades rapidly.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the circuit for driving a nonvolatile ferroelectric memory, the memory having a plurality of bitlines, a plurality of wordlines and plate lines formed in a direction crossing the bitlines and a reference bitline on one side of the plurality of bitlines, includes a cell array having a plural times of repetitive arrangement of the plurality of bitlines and the reference bitline on one side thereof, a sense amplifier array having a plurality of sense amplifiers for sensing data on the bitlines and the reference bitlines in the cell array, a wordline and plateline driver for selective application of driving signals to the wordlines and the platelines, and a switching part for selective turning on/off of the bitlines, the reference bitlines, and the input/output nodes on the sense amplifier array, whereby improving a chip operation performance and a lifetime.
The present invention can be achieved in parts or in a whole by a nonvolatile ferroelectric memory comprising: a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at a corresponding crossing point of the bitlines with the wordlines and the platelines; a first reference cell block on one side of the first main cell block, the first reference cell block having first and second reference bitlines formed in a direction crossing the wordlines and the platelines and a reference cell on a corresponding crossing point of the first and second reference bitlines with the wordlines and the platelines; a first lower sense amplifier block having a plurality of sense amplifiers, each sense amplifier with a bitline input/output node connected to an odd numbered bitline for sensing a data on the odd numbered bitline and a reference bitline input/output node connected to the first reference bitline for sensing a data on the first reference bitline; a first upper sense amplifier block having a plurality of sense amplifiers, each sense amplifier with a bitline input/output node connected to an even numbered bitline for sensing a data on the even numbered bitline and a reference bitline input/output node connected to the second reference bitline for sensing a data on the second reference bitline; a first switching unit for selective connection of the odd numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first lower sense amplifier block; a second switching unit for selective connection of the reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first lower sense amplifier block; a third switching unit for selective connection of the even numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first upper sense amplifier block; a fourth switching unit for selective connection of the reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first upper sense amplifier block; and first and second pull-up transistors for pulling-up levels of the first and second reference bitlines to a level of a power supply voltage, respectively.
FIG. 7 illustrates in more detail a circuit for driving a nonvolatile ferroelectric memory in accordance with a first preferred embodiment of the present invention. The circuit shown in FIG. 7 may be repeated to obtain a system shown in FIG. 6. A first main block 71 has a plurality of wordlines W/L_n, W/L_n+2, W/L_n+3, etc., arranged in one direction at fixed intervals, a wordline P/L_n, P/L_n+1, P/L_n+2, P/L_n+3, etc., arranged between every adjacent wordlines, a plurality of bitlines B_n, B_n+1, B_n+2, B_n+3, etc., arranged in one direction crossing the wordlines and the platelines at fixed intervals, and main cells 70, each being formed at a crossing point of each of the bitlines with the wordlines and the platelines.
The circuit may further include a first switching unit 75 having transistors T1, T2, T3, T4, etc., for selective connection of the bitlines to the bitline input/output nodes B1, B2, B3, B4, etc., on each of the sense amplifiers in response to a first control signal C1. The circuit may further include a second switching unit 76 having transistors T11, T22, T33, T44, etc., for selective connection of the reference bitline to the reference bitline input/output nodes R1, R2, R3, R4, etc., on each of the sense amplifiers in response to a second control signal C2, and a pull-up transistor PU0 for pulling-up a level of the reference bitline RB0 to a level of a power supply voltage in response to a third control signal C3. The first and second switching units 75 and 76 may include NMOS transistors or PMOS transistors.
A plural times of repetitive arrangement of the first main block 71 and the first reference cell block 73 as a pair forms one cell array, and a plural times of repetitive arrangement of the first sense amplifier block 74 forms one sense amplifier array. Though the reference bitline is provided after four bitlines are provided in FIG. 7, the reference bitline may be provided after every two or more than two, ie., after every plural bitlines with flexibility. A wordline and plateline driver 77 applies a signal to the wordlines and the platelines. In this first embodiment, the cell array has a memory cell at every crossing of the bitlines with the wordlines and the platelines.
The operation of the circuit for driving a nonvolatile ferroelectric memory in accordance with a first embodiment of the present invention is as follows. Referring to FIG. 7, when the first control signal C1 is enabled to high, all the transistors T1, T2, T3, T4, etc., in the first switching part 75 are turned on, electrically connecting the bitlines B_n, B_n+1, B_n+2, B_n+3, etc., in the first main cell block 71 to the bitline input/output nodes B1, B2, B3, B4, etc., in the first sense amplifier block 74, respectively. When the second control signal C2 is enabled to high, the transistors T11, T22, T33, T44, etc., in the second switching unit 76 is turned on, electrically connecting the reference bitline RB0 to the reference bitline input/output node R1,R2,R3,R4, etc., on the first sense amplifier block 74.
Upon application of high signals from the wordline and plateline driver 77 to the wordline and the plateline under a state the first control signal C1 and the second control signal C2 are thus enabled, a data stored in the main cell 70 is provided to the bitline input/output node B1, B2, B3, B4, etc., in the first sense amplifier block 74 though the bitline B_n, B_n+1, B_n+2, B_n+3, etc. A data in the reference cell 72 is provided to the reference bitline input/output node R1, R2, R3, R4, etc., on the first sense amplifier block 74 through the reference bitline RB0. If the data in the main cell 70 and reference cell 72 are provided to the bitline and the reference bitline adequately, the first control signal C1 and the second control signal C2 are disabled, to turn off all the transistors in the first and second switching units 75 and 76.
FIG. 9 illustrates in more detail the circuit of FIG. 8. The circuit shown in FIG. 9 may be repeated to obtain a system shown in FIG. 8. The circuit includes a first main block 91 having a plurality of wordlines W/L_n, W/L_n+1, W/L_n+2, W/L_n+3, etc., arranged in one direction at fixed intervals, a wordline P/L�n, P/L_n+1, P/L_n+2, P/L_n+3, etc., arranged between every adjacent wordlines, a plurality of bitlines B_n, B_n+1, B�n+2, B_n+3, etc., arranged in one direction crossing the wordlines and the platelines at fixed intervals, and main cells 90, each being formed at a crossing point of each of the bitlines with the wordlines and the platelines.
First reference cell block 93 having first and second reference bitlines RB0 and RB1 is formed on sides of the main cell 91 in a direction crossing the wordlines and the platelines and reference cells 92, each being formed at crossing points of the first and second reference bitlines RB0 and RB1 with the wordlines and the platelines. A first lower sense amplifier block 94 a having a plurality of sense amplifiers, SA1, SA3, etc., each with a bitline input/output node B1, B3, etc., connected to odd numbered one of the bitlines, senses a data on the bitline and senses a data on a reference bitline input/output node R1, R3, etc., connected to the first reference bitline RB0. A first upper sense amplifier block 94 b having a plurality of sense amplifiers SA2, SA4, etc., each with a bitline input/output node B2, B4, etc., connected to even numbered one of the bitlines senses a data on the bitline and senses a data on a reference bitline input/output node R2, R4, etc., connected to the second reference bitline RB1.
The circuit may further includes a first switching unit 95 having transistors T1, T2, etc., for selective connection of odd numbered bitlines to the bitline input/output nodes B1, B3, etc., on the sense amplifiers SA1, SA3, etc., in the first lower sense amplifier block 94 a in response to a first control signal C1. A second switching unit 96 having transistors T11, T12, etc., may be included for selective connection of the reference bitline RB0 to the reference bitline input/output nodes R1, R3, etc., on the sense amplifiers SA1, SA3, etc., in the first lower sense amplifier block 94 a in a response to a second control signal C2. A third switching unit 95 a having transistors T21, T22, etc., may be included for selective connection of even numbered bitlines to the bitline input/output nodes B2, B4, etc., on the sense amplifiers SA2, SA4, etc., in the upper sense amplifier block 94 b in response to a first control signal C1. A fourth switching unit 96 having transistors T31, T32,etc., may be included for selective connection of the reference bitline RB1 to the reference bitline input/output nodes R2, R4, etc., on the sense amplifiers SA2, SA4, etc., in the first upper sense amplifier block 94 b in response to a second control signal C2.
The circuit for driving a nonvolatile ferroelectric memory in accordance with a third preferred embodiment of the present invention includes a first main block 101 having a plurality or wordlines W/L_n, W/L_n+1, W/L_n+2, W/L_n+3, etc., arranged in one direction at fixed intervals, a wordline P/L_n, P/L_n+1, P/L_n+2, P/L_n+3, etc., arranged between every adjacent wordlines, a plurality of bitlines B_n, B_n+1, B_n+2, B_n+3, etc., arranged in one direction crossing the wordlines and the platelines at fixed intervals, and main cells 100.
FIG. 11 illustrates a circuit for driving a nonvolatile ferroelectric memory in accordance with a fourth preferred embodiment of the present invention. Similar to the third embodiment, the memory cells in the cell array of the fourth embodiment have a form of folded bitline. The circuit includes a first main block 111 having a plurality of wordlines W/L_n, W/L_n+1, W/L_n+2, W/L _n+, etc., arranged in one direction at fixed intervals, a plurality of platelines P/L_n, P/L_n+1, P/L_n+2, P/L_n+, etc., arranged between every adjacent wordlines, and a plurality of bitlines B_n, B_n+1, B_n+2, B_n+3, etc., arranged in one direction crossing the wordlines and the platelines at fixed intervals.
A main cell 110 is formed at every second crossing point of the bitlines with the wordlines and the platelines. A first reference cell block 113 has first and second reference bitlines RB0 and RB1, each formed on one side of the main cell block 111 in a direction crossing the wordlines and the platelines. Each reference cell 112 is formed at every second crossing point of the first and second refernce bitlines RB0 and RB1 with the wordlines and the platelines.
The circuit may further includes a first switching unit 115 has transistors T1, T2, etc., for selective connection of odd numbered bitlines to the bitline input/output nodes B1, B3, etc., on the sense amplifiers SA1, SA3, in the lower sense amplifier block 114 a in response to a first control signal C1. A second switching unit 116 has transistors T11, T12,etc., for selective connection of the first reference bitline RB0 to the reference bitline input/output nodes R1, R3, etc., on the sense amplifiers SA1, SA3, etc., in the first lower sense amplifier block 114 a in response to a second control signal C2. A third switching unit 115 a has transistors T21, T22, etc., for selective connection of even numbered bitlines to the bitline input/output nodes B2, B4, etc., on the sense amplifiers SA2, SA4, etc., in the upper sense amplifier block 114 b in response to a first control signal C1. A fourth switching unit 116 a has transistors T31, T32,etc., for selective connection of the reference bitline RB1 to the reference bitline input/output nodes R2, R4, etc., on the sense amplifiers SA2, SA4, etc., in the first upper sense amplifier block 114 b in response to a second control signal C2.
Pull-up transistor PU0 and PU1 may be included for pulling-up levels of the reference bitlines RB0 and RB1 to a level of a power supply voltage in response to a third control signal C3, respectively. The first to fourth switching units 115, 116, 115 a and 116 a may include NMOS transistors or PMOS transistors, respectively. Though the two reference bitlines RB0 and RB1 are provided after four bitlines connected to the upper and lower sense amplifiers 114 b and 114 a are provided in FIG. 11, the reference bitlines RB0 and RB1 may be provided after every even numbered bitlines of 6, 8, 10, etc. A repetitive arrangement of the first main cell block 111 at the first reference cell block 113 may form one cell array, and the first lower and upper sense amplifiers 114 a and 114 b may form the lower and upper sense amplifier arrays.
The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also eqivalent structures.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4433390Jul 30, 1981Feb 21, 1984The Bendix CorporationPower processing reset system for a microprocessor responding to sudden deregulation of a voltageUS4873664Feb 12, 1987Oct 10, 1989Ramtron CorporationSelf restoring ferroelectric memoryUS4888630Mar 21, 1988Dec 19, 1989Texas Instruments IncorporatedFloating-gate transistor with a non-linear intergate dielectricUS4928095Dec 16, 1983May 22, 1990Seiko Instruments Inc.Active matrix-addressed picture display deviceUS5297077Mar 28, 1991Mar 22, 1994Kabushiki Kaisha ToshibaMemory having ferroelectric capacitors polarized in nonvolatile modeUS5371699Nov 17, 1992Dec 6, 1994Ramtron International CorporationNon-volatile ferroelectric memory with folded bit lines and method of making the sameUS5638318Sep 11, 1995Jun 10, 1997Micron Technology, Inc.Ferroelectric memory using ferroelectric reference cellsUS5680344Sep 11, 1995Oct 21, 1997Micron Technology, Inc.Circuit and method of operating a ferrolectric memory in a DRAM modeUS5680357 *Sep 9, 1996Oct 21, 1997Hewlett Packard CompanyHigh speed, low noise, low power, electronic memory sensing schemeUS5737260 *Mar 27, 1996Apr 7, 1998Sharp Kabushiki KaishaDual mode ferroelectric memory reference schemeUS5872739Apr 17, 1997Feb 16, 1999Radiant TechnologiesSense amplifier for low read-voltage memory cellsUS5930180 *Jul 1, 1997Jul 27, 1999Enable Semiconductor, Inc.ROM bit sensingUS5953274 *Aug 14, 1998Sep 14, 1999Kabushiki Kaisha ToshibaSemiconductor memory device capable of storing plural-bit data in a single memory cellUS6002625 *Dec 16, 1997Dec 14, 1999Lg Semicon Co., Ltd.Cell array and sense amplifier structure exhibiting improved noise characteristic and reduced sizeUS6091622 *Dec 15, 1998Jul 18, 2000Lg Semicon Co., Ltd.Nonvolatile ferroelectric memory deviceUS6128213 *Jan 13, 1999Oct 3, 2000Lg Semicon Co., Ltd.Nonvolatile ferroelectric memory and a method of manufacturing the sameUS6188599 *Feb 1, 1999Feb 13, 2001Hyundai Electronics Industries Co., Ltd.Circuit for driving nonvolatile ferroelectric memoryUS6215692 *Dec 28, 1999Apr 10, 2001Hyundai Electronics Industries Co., Ltd.Non-volatile ferroelectric memoryUS6240007 *Nov 2, 1999May 29, 2001Hyundai Electronics Industries Co., Ltd.Nonvolatile ferroelectric memory device having global and local bitlines and split workline driver* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6574132 *Jul 2, 2001Jun 3, 2003Infineon Technologies AgCircuit configuration for equalizing different voltages on line runs in integrated semiconductor circuitsUS6967897 *Jun 30, 2004Nov 22, 2005Hynix Semiconductor Inc.FeRAM having wide page buffering functionUS7313043 *Nov 29, 2005Dec 25, 2007Altis Semiconductor SncMagnetic Memory Array* Cited by examinerClassifications U.S. Classification365/145, 365/210.1, 365/207, 365/210.15, 365/65, 365/210.14International ClassificationH01L21/8246, H01L27/10, H01L27/105, G11C16/06, G11C14/00, G11C11/22Cooperative ClassificationG11C11/22European ClassificationG11C11/22Legal EventsDateCodeEventDescriptionMar 15, 2013FPAYFee paymentYear of fee payment: 12Jun 24, 2009FPAYFee paymentYear of fee payment: 8Jun 28, 2005FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google