Source: https://patents.justia.com/patent/10242727
Timestamp: 2019-10-16 00:32:36
Document Index: 356833061

Matched Legal Cases: ['Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10']

US Patent for Reduction of power consumption in memory devices during refresh modes Patent (Patent # 10,242,727 issued March 26, 2019) - Justia Patents Search
Justia Patents Including Signal ComparisonUS Patent for Reduction of power consumption in memory devices during refresh modes Patent (Patent # 10,242,727)
May 17, 2018 - Intel
The present application is a divisional of U.S. patent application Ser. No. 15/354,200, filed on Nov. 17, 2016, which is a continuation of U.S. patent application Ser. No. 15/181,358, filed on Jun. 13, 2016, which is a divisional of U.S. patent application Ser. No. 13/997,959, filed on Dec. 19, 2013, which was the National Stage of International Application No. PCT/US2012/030657, filed on Mar. 27, 2012. The entire contents of these applications are incorporated herein by reference.
Memory device 110 provides, at least in part, the main system memory for system 100. Memory device 110 may comprise a DRAM device, such as, for example, DDR1, DDR2, DDR3, DDR4, LPDDR, etc., in accordance with any of the embodiments described herein. Memory device 110 may include one or more memory resources 112a-112n. Memory resources 112a-112n represent the resources on which the data is stored for memory 110, sometimes referred to as the memory array. In different embodiments, the memory resources may be configured as separate memory channels, memory banks, memory groups, etc.
After a certain number of clock cycles post SRE command, at timing TVDD_SR, voltage regulator 170 switches the regulated voltage supplied to memory device 110 from the VDD voltage to the lower VDD_SR voltage specified by the register resources. Consistent with the principles described above, VDD is the voltage signal level for active read/write operations, for example, in the case of DDR4 DRAM, VDD=1.2V; while VDD_SR is the voltage signal level that is lower than VDD and still capable of supporting refreshing operations during the self-refresh mode, for example, VDD_SR=1.0V.
a memory controller communicatively coupled with the processor and a memory device, wherein the memory controller comprises hardware logic to control access to the memory device, including to transmit a command to the memory device to program a register to indicate one of multiple voltage rails for the memory device;
wherein, based at least in part on the register, the memory device is to: operate from a first voltage rail in a first mode, wherein the first voltage rail is to provide a first DC voltage at a first magnitude, and wherein the first mode is to accommodate read and write operations; and operate from a second voltage rail in a second mode based at least in part on a register, wherein the second voltage rail is to provide a second DC voltage at a second magnitude that is lower than the first magnitude, and wherein the memory device is to perform self-refresh in the second mode.
the memory device is to operate from a higher voltage rail in the first mode and operate from a lower voltage rail in the second mode based at least in part on the register and based at least in part on a transition to the second mode.
the hardware logic of the memory controller is to further trigger the transition of the memory device into the second mode.
the hardware logic to trigger the transition to the second mode is to: issue a deselect (DES) command to indicate no active read/write operations for the memory device, transition a clock enable signal low, and issue self-refresh enable (SRE) command to memory device.
the memory controller is to cause a transition to the second mode.
the memory controller to cause the transition to the second mode is to: issue a deselect (DES) command to indicate no active read/write operations for the memory device, transition a clock enable signal low, and issue self-refresh enable (SRE) command to memory device.
7. The system of claim 1, wherein the processor includes the memory controller.
the hardware logic is to control access to the memory device in accordance with a DDR (double data rate) standard.
the hardware logic is to control access to the memory device in accordance with an LPDDR (low power double data rate) standard.
the hardware logic is to provide a clock enable signal to the memory device, the clock enable signal to trigger entry into the second mode.
a memory controller to control access to a memory device, including to transmit a command to the memory device to program a register to indicate one of multiple voltage rails for the memory device; and
a voltage regulator to supply regulated output voltages to the memory device via a supply line infrastructure, wherein the supply line infrastructure comprises a first voltage rail to provide a first DC voltage at a first magnitude and a second voltage rail to provide a second DC voltage at a second magnitude that is lower than the first magnitude;
wherein, based at least in part on the register, the memory device is to: operate from the first voltage rail in a first mode, wherein the first mode is to accommodate read and write operations; and operate from a second voltage rail in a second mode based at least in part on a register, wherein the memory device is to perform self-refresh in the second mode.
a power supply to provide a voltage to the voltage regulator.
the memory controller is to control access to the memory device in accordance with a DDR (double data rate) standard.
the memory controller is to control access to the memory device in accordance with an LPDDR (low power double data rate) standard.
the memory controller is to provide a clock enable signal to the memory device, the clock enable signal to trigger entry into the second mode.
first hardware logic to control access to a memory device, including to transmit a command to the memory device to program a register to indicate one of multiple voltage rails for the memory device; and
second hardware logic to provide a clock enable signal to the memory device, the clock enable signal to trigger entry into a self-refresh mode;
wherein, based at least in part on the register, the memory device is to: operate from a first voltage rail in an active mode, wherein the first voltage rail is to provide a first DC voltage at a first magnitude; and operate from a second voltage rail in the self-refresh mode based at least in part on a register, wherein the second voltage rail is to provide a second DC voltage at a second magnitude that is lower than the first magnitude.
18. The memory controller of claim 17, wherein:
the memory device is to operate from a higher voltage rail in the active mode and operate from a lower voltage rail in the self-refresh mode based at least in part on the register and based at least in part on the entry into the self-refresh mode.
19. The memory controller of claim 17, wherein:
the first and second hardware logic is to control access to the memory device in accordance with a DDR (double data rate) standard.
20. The memory controller of claim 17, wherein:
the first and second hardware logic is to control access to the memory device in accordance with an LPDDR (low power double data rate) standard.
5867438 February 2, 1999 Nomura et al.
6215714 April 10, 2001 Takemae et al.
7266031 September 4, 2007 Kim et al.
7800431 September 21, 2010 Chu
20030067824 April 10, 2003 Janzen
20050246558 November 3, 2005 Ku
20060171231 August 3, 2006 Song
20080002485 January 3, 2008 Kim
20080018381 January 24, 2008 Shin
20080080286 April 3, 2008 Tomita
20080298152 December 4, 2008 Ito et al.
20090219767 September 3, 2009 Lines et al.
20130114353 May 9, 2013 Vogelsang
2012027250 March 2012 WO
Korean and English Translation of Korean Fourth Office Action for Patent Application No. 10-2016-7036307, dated May 30, 2018, 6 pages.
Korean and English Translation of Korean Office Action for Patent Application No. 10-2018-7018697, dated Jul. 16, 2018, 4 pages.
English Translation of the Notice of Preliminary Rejection, Application No. 10-2016-7036307, dated Apr. 4, 2017, 3 pages.
English Translation of the Notice of Preliminary Rejection, Patent Application No. 10-2016-7036307, dated Sep. 20, 2017, 2 pages.
English Translation of the Notice of Preliminary Rejection, Patent Application No. 10-2016-7036307, dated Nov. 23, 2017, 4 pages.
Final Office Action for U.S. Appl. No. 15/354,200, dated Oct. 20, 2017, 13 pages.
International Search Report dated Nov. 20, 2012 in corresponding International Patent Application PCT/US2012/030657, total of 3 sheets.
Notice of Allowance for Korean Patent Application No. 10-2014-7027306, dated Sep. 27, 2016, 2 pages.
Notice of Allowance for U.S. Appl. No. 13/997,959, dated Mar. 7, 2016, 9 pages.
Notice of Allowance for U.S. Appl. No. 13/997,959, dated May 11, 2015, 9 pages.
Notice of Allowance for U.S. Appl. No. 15/181,358, dated Aug. 16, 2016, 8 pages.
Notice of Preliminary Rejection for Korean Patent Application No. 10-2014-7027306, dated Mar. 22, 2016, 5 pages.
Office Action for U.S. Appl. No. 13/997,959, dated Oct. 28, 2015, 9 pages.
Office Action for U.S. Appl. No. 15/354,200, dated Jun. 1, 2017, 12 pages.
Restriction Requirement for U.S. Appl. No. 15/354,200, dated Apr. 14, 2017, 6 pages.
Restriction Requirement Received for U.S. Appl. No. 13/997,959, dated Aug. 26, 2015, 7 pages.
Restriction Requirement Received for U.S. Appl. No. 13/997,959, dated Feb. 13, 2015 , 6 pages.
Patent Publication Number: 20180336943
Inventors: Christopher E. Cox (Placerville, CA), Kuljit S. Bains (Olympia, WA), John B. Halbert (Beaverton, OR)
Application Number: 15/983,009
International Classification: G11C 7/00 (20060101); G11C 11/406 (20060101); G11C 11/4074 (20060101); G11C 11/4096 (20060101); G11C 11/409 (20060101); G11C 7/08 (20060101); G11C 16/34 (20060101); G11C 16/26 (20060101); G11C 16/10 (20060101); G11C 16/04 (20060101); G11C 16/24 (20060101);