Source: http://www.google.com/patents/US6502158?dq=7,173,247
Timestamp: 2016-05-30 08:51:17
Document Index: 577720422

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US6502158 - Method and system for address spaces - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA system for allowing a node to be accessed through multiple address spaces. The system includes a virtual address memory providing a software settable bus identification address and a stable node identification address for each node in a net, a physical address memory providing a physically assigned...http://www.google.com/patents/US6502158?utm_source=gb-gplus-sharePatent US6502158 - Method and system for address spacesAdvanced Patent SearchPublication numberUS6502158 B1Publication typeGrantApplication numberUS 09/531,084Publication dateDec 31, 2002Filing dateMar 18, 2000Priority dateApr 23, 1999Fee statusLapsedPublication number09531084, 531084, US 6502158 B1, US 6502158B1, US-B1-6502158, US6502158 B1, US6502158B1InventorsDavid V. James, Bruce FairmanOriginal AssigneeSony Corporation, Sony Electronics, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (62), Non-Patent Citations (2), Referenced by (12), Classifications (60), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for address spaces
US 6502158 B1Abstract
A system for allowing a node to be accessed through multiple address spaces. The system includes a virtual address memory providing a software settable bus identification address and a stable node identification address for each node in a net, a physical address memory providing a physically assigned node identification address for each node in a local bus, and a logical address memory providing a stable node identification address for each node in the local bus.
What is claimed is: 1. A system for allowing a node to be accessed through multiple address spaces comprising:
a virtual address memory providing a net refresh managed bus identification address and a stable node identification address for each node in a net; a physical address memory providing a physically assigned node identification address for each node in a local bus; and a logical address memory providing a stable node identification address for each node in the local bus. 2. The system of claim 1 wherein the system translates stable node identification addresses to physical node identification addresses to allow access to local nodes using logical addresses.
3. The system of claim 1 wherein the system captures requests and translates logical node identification addresses to physical node identification addresses.
4. The system of claim 1 wherein the system captures responses and translates logical node identification addresses to physical node identification addresses.
5. The system of claim 1 wherein the stable node identification address is a initially assigned node identification address.
6. The system of claim 1 wherein a special portal on a bus is always assigned a fixed stable identification address.
7. The system of claim 6 wherein the special portal is the alpha portal.
8. The system of claim 6 wherein the special portal is the delta portal that does stable identification address to physical identification address translations.
9. The system of claim 1 wherein fixed stable identification addresses are assigned to nodes of interest.
10. The system of claim 1 wherein the stable identification addresses are assigned by a bus bridge.
11. The system of claim 1 wherein the stable identification addresses are recognized by a bus bridge and stored in a register on each node of a bus.
12. The system of claim 1 wherein the stable identification addresses are determined by local bus nodes in a cooperative fashion.
a bus including at least two nodes; and at least one bus bridge portal comprising a virtual address space for storing a software settable bus identification address and a stable node identification address for each node in a bus system; a physical address space for storing a physically assigned node identification address for each node in a local bus; and a logical address space for storing a stable node identification address for each node in the local bus. 14. The system of claim 13 wherein a portal captures node access requests from a requesting node and translates stable node identification addresses to physical node identification addresses.
15. The system of claim 13 wherein the requesting node stores the stable node identification address to physical node identification address translation in a cache memory in the requesting node.
16. The system of claim 13 wherein the bus is substantially similar to a version of the IEEE 1394 standard serial bus.
17. A bus bridge comprising:
means for accessing nodes through software settable bus identification addresses and stable node identification addresses; means for accessing nodes through physical node identification addresses on a local bus; and means for accessing nodes through stable node identification addresses on a local bus. 18. A method for identifying nodes on a bus comprising:
receiving a request to access a node on a bus; accepting the request if a bus identification portion of a destination address of the request matches a local bus identification address and a local node identification address of the destination address matches a physical node identification address on the local bus; translating a stable identification address of the destination address to a physical node identification address if the bus identification portion of the destination address matches a logical bus identification address or the bus identification portion of the destination address matches a bus number; and accepting the request if the translated physical node identification address matches a physical node identification address on the local bus. 19. A method of node identification comprising:
identifying a physical node identification address for a node; and storing the physical node identification address as a stable node identification address. 20. The method of claim 19 further comprising:
matching a local identification portion of a received destination address to the stable node identification address; and translating the stable node identification address to a physical node identification address. 21. A memory for storing data for access by a program being executed on a data processing system, comprising:
a data structure stored in a memory, the data structure including information used by a program including: a virtual address data structure including software settable bus identification addresses for nodes on a net; a physical address data structure including physically assigned node identification addresses for nodes on a local bus; and a logical address data structure including stable node identification addresses for nodes on the local bus.
This application claims benefit of U.S. Provisional Application No. 60/130,698 filed Apr. 23, 1999 as well as U.S. Provisional Application No. 60/137,916 filed Jun. 7, 1999, U.S. Provisional Application No. 60/144,101 filed Jul. 16, 1999, U.S. Provisional Application No. 60/150,393 filed Aug. 23, 1999, U.S. Provisional Application No. 60/155,305 filed Sep. 21, 1999 and U.S. Provisional Application No. 60/158,722 filed Oct. 11, 1999.
The present invention relates generally to audio, video, audio/video interconnected systems for home and office use. More particularly, the present invention relates to address spaces on bus bridges.
Some bus bridges lack a stable node identification system. This could result in the wrong node being accessed if the node identifications are changed, which could lead to system corruption.
FIG. 7 is a block diagram of one embodiment for a bus bridge address space;
FIGS. 8a-b are block diagrams of one embodiment for the translation between physical and virtual addresses within a bus bridge;
FIG. 9 is a flow diagram of request management in one embodiment of a bus.
A bus bridge including a memory for storing node addresses is described. The node addresses include a stable node identification address to allow access to nodes after addition or removal of nodes.
Within an interconnect topology 500, the bridge portal with the largest refresh ID identifier is elected to become the prime portal 504. In an alternate embodiment, the bridge portal with the smallest portal ID identifier is elected to become the prime portal 504. Each portal appears as a node on its attached bus. The bus with the prime portal 504 is termed the primary bus 525 and other buses 527-535 are termed secondary buses. On secondary buses 527-535, the bridge portal that leads to the primary bus 525 is called the alpha portal (506, 508). After a bridge bus interconnect is configured, any node within the interconnect may be accessed by its unique 16-bit node identification address. The node identification address contains the bus ID and the local ID components. Referring to FIG. 4, the bus identification IDs of nodes 512-524 are indicated by the letters a, b, and c and the local ID is indicated by the numbers 0-4.
One of the portals, which could be the primary portal 504 is responsible for rejecting missed address asynchronous data packets by accepting these requests and returning error reporting responses. The previous and current prime and alpha portal identifiers are used to classify nodes when an interconnect topology changes, and the alpha portal is the isochronous clock reference for other nodes on the bus.
Bus bridge topology 500 may change and be established dynamically during operation of bus bridge system 500. Bus bridges communicate between themselves, in what is called a net refresh operation, to determine the set of unique busIDs that are assigned to each bus. In one embodiment, the bus bridge topology 500 is established during net refresh. Within topology 500, portals selectively route packets. Asynchronous routing tables are stable until topology 500 changes during a net refresh or net reset operation. Asynchronous routing tables are dynamic and are changed by their asynchronous connect and disconnect operations of the protocols.
The Serial Bus uses a 64-bit addressing architecture. The most-significant 16 bits (nodeID) of the 64 bits specifies a target-node (as discussed above). The least significant 48 bits (offset address) specifies a location within that node (i.e. selects what resource to access within a node). The nodeID has two components: a) the first 10 bits, or busID, is used to identify the bus, and b) the remaining 6 bits (localID) is used to identify the device on the bus. Whenever a node is attached or detached, all the other nodes may change. There are 64 devices on each bus and 1024 buses in a system. Thus, address spaces are a linear way of corresponding to these addresses in a bus bridge, as illustrated in FIG. 7.
FIG. 7 is a block diagram of one embodiment for a bus bridge address space 1000. Referring to FIG. 7, bus bridge addresses for each node include three node identification (nodeID) address spaces: a physical identification address space (phyID) 1005, a logical identification address space (logicalID) 1003, and a virtual identification address space (virtualID) 1002. In one embodiment, the bus numbers associated with these spaces are 3FF16, 3FE16, and net refresh assigned, respectively. BusIDs 1007 range from 0 to 3FF16. Each busID 1006 contains 64 localID addresses, as shown for virtualID 1002.
All nodes reside in physical address space 1005. PhyIDs 1005 are localIDs which are dependent on their cable topology. Local bus nodes are accessed by the bus bridge through their cable topology dependent localID as phyID address assignments.
In one embodiment, a virtual nodeID 1002 may include a software settable busID 1006 and stableID 1001. The busID addresses are assigned during each net refresh providing each bus with a distinct range of 64 stableID addresses 1001. This allows each node to respond to a net-unique semi-stable virtualID address 1002.
In one embodiment, the bridge portals maintain the mapping between stableID 1001 and phyID 1005 addresses. In the case of a same-bus transfer, the request is captured by the delta portal, which translates between stableID 1001 and phyID addresses 1005.
In an alternate embodiment, the bus bridge portals could write the assigned stableID 1001 into a register on each node. Thus, the node has a register that is either updated by a bus bridge portal or retains its last written value unless a conflict is detected. In another embodiment, during a bus reset the stableID values 1001 are determined by the nodes in a cooperative fashion.
FIGS. 8a and 8 b are block diagrams of one embodiment for virtual to phyID 1005 translation by a bridge portal 1101, which is a delta portal in the embodiment shown. The delta portal may be any portal on the bus, but there may only be one delta portal on the bus. In one embodiment, the delta portal 1101 is the portal on a bus having the lowest phyID 1005 and manages the stableIDs 1001 on a bus. The stableID 1001 may be a part of the virtualID 1002 or the logicalID 1003. In an alternate embodiment, the delta portal may be the portal on the path back toward the prime portal or the alpha portal. Thus, the delta portal may be chosen locally or the delta portal may be the alpha portal or any other appropriate portal.
In the operation of FIGS. 8a and 8 b, the delta portal 1101 captures a request having a local bus destination node and translates the destination identification address from the destination node's stableID 1001 to the destination node's phyID 1005 and sends the request to the destination node using the destination node's phyID 1005. The delta portal 1101 also translates the source node's phyID 1005, which is found in the request, to the source node's stableID 1001. The delta portal 1101 also performs stableID 1001 to phyID 1005 translation for the destination node of the response and phyID 1005 to stableID 1001 translation for the source node of the response. The source node of the request (which is the destination node of the response), in this case node C, may then store the phyID 1005 of the destination node of the request, in this case node B, which may be found in the response. The phyID 1005 of the destination node of the request may be stored in a cache memory in the source node for later use. The use of the phyID 1005 later by the source node may further increase efficiency of bus bridge operation.
In FIG. 8a, node C 1104 sends a request 1105 designated for node B 1103. The request is addressed to the stableID 1001 of node B 1103 from the phyID 1005 of node C 1104. Delta portal 1101 captures and translates the destination_ID from the stableID 1001 of node B 1103 to the phyID 1005 of node B and transmits the address translated request 1106, having as a source the stableID 1001 of node C 1104.
In FIG. 8b, node B 1103 then sends a response 1107 to the stableID 1001 of node C 1104. The delta portal 1101 captures the response and translates the addresses from the stableID 1001 of node C 1104 to the phyID 1005 of node C 1104 and from the phyID 1005 of node B 1103 to the stableID 1001 of node B 1103. The delta portal then transmits the address translated response 1108.
The requester, or node C 1104, may then store the stable-to-phyID address translation for node B 1103 in a cache memory (not shown), which can be extracted from the returned response. These cache entries allow the same bus nodes to efficiently access their neighbors, until the next bus reset (which causes these entries to be discarded).
Thus, the same addresses may be used to access node B 1103, for example, whether the requester is on the same bus or a remote bus. Although any portal node has the capability of performing these address translations, allocating this task to the primary portal eliminates the need to define contention resolution protocols.
FIG. 9 is a flow diagram of request management in one embodiment of a bus. At processing block 1201, a request to access a node on the bus is received. At processing block 1202, the busID 1007 address of the destination address is checked to see if it equals 3FF16. This checking may be done at a bus bridge on the bus or at the destination node. If the busID 1007 equals 3FF16, the localID portion of the destination address is compared to phyID 1005 addresses existing on the bus at processing block 1203. If the localID equals a phyID 1005 of a node on the bus, the node at the localID address of the destination address accepts the request at processing block 1204.
If the busID 1007 portion of the destination address does not equal 3FF16, at processing block 1205, the busID 1007 is checked to see if it equals 3FE16, or the logical busID 1007 of the local bus. If the busID 1007 address matches 3FE16, the localID portion of the destination address, the stableID, is translated to the phyID 1005 of the local bus, at processing block 1206. Then the translated phyID 1005 is compared to node phyIDs 1005 of the local bus at processing block 1207. If the translated phyID 1005 matches a node phyID 1005, the node at the phyID 1005 address accepts the request at processing block 1204.
If the busID 1007 portion of the destination address does not match the logical busID 1007, the busID 1007 is compared to the bus number of the bus at processing block 1208. At processing block 1206, if the busID 1007 matches the bus number, the localID portion of the destination address (the stableID) is translated to phyID 1005, as described above, since the destination address is the virtual address of the node. Then, at processing block 1207, the translated phyID 1005 is compared to node phyIDs 1005 of the local bus, as described above. If the translated phyID 1005 matches a node phyID 1005, the node at the phyID 1005 address accepts the request at processing block 1204.
If the localID does not match the phyID 1005 at processing block 1203 or if the busID 1007 does not match the bus number at processing block 1208, the request is ignored by the bus.
The processes described with respect to FIG. 9 may be performed by a bus bridge or a node or both, with a bus bridge performing some of the processes and a node performing the others.
Referring to the logical address space 1003 of FIG. 7, only local bus nodes can be accessed using the logicalID 1003. The local bus nodes may be accessed using their localID which uses their stableID 1001 address assignment. The stableID 1001 may be, according to one embodiment, the phyID 1005 the first time it is accessed. Since the busID 1007 portion of the logicalID 1003 is fixed, the logicalID 1003 is a more stable way to access local nodes than the virtualID 1001, whose busID can change.
Logical address to physical address translations follow the operation of the virtualID 1001-to-phyID 1005 address translations described by FIGS. 8a and 8 b. There are 64 possible busID 1001 addresses on each logically or virtually accessed bus, since a broadcast localID is not supported in either of these spaces.
With regard to FIG. 5, for example, if a device 516 is accessed by another bus, such as bus a 525, bus bridge 502 would be aware of the busID 1007 of bus 527. If the incoming address matched the busID 1007 of bus 527, bus bridge 502 would convert the busID 1007 to 3FF16 and send it out as a physical address of device 516. Without the logicalID 1003, a local portal would be accessed through the phyID 1005, and a portal on the general bus would be accessed through the virtualID 1001.
By partitioning the nodeIDs into bus-sized chunks, only 64 node addresses need be probed by enumeration software instead of 64,000. Like the physical space, the logical space is a way of checking local addresses first to lower the number of comparisons that need to be performed. Further, special nodes, such as a primary, alpha or delta portal 1101, may be assigned to well known logical addresses such as 0 or 63. In FIG. 7, the special portal 1004, is assigned the logical nodeID of 0 so that it may be found more quickly. The existence of the special portal at a known logicalID address1003 simplifies other nodes by allowing them to easily determine how to communicate with the special portal. If the busID 1001 of 0 is always assigned to the special portal, it is possible to find what buses exist by communicating with the special portal, and determine what buses exist on the local bus by checking the 64 nodes. Thus, all the buses in the system may be found by checking for them at the special portal. Time is saved by not having to probe each of the local nodes to determine which is the special portal.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4538259Jul 5, 1983Aug 27, 1985International Business Machines CorporationSystem for digitized voice and data with means to compensate for variable path delaysUS4935894Aug 31, 1987Jun 19, 1990Motorola, Inc.Multi-processor, multi-bus system with bus interface comprising FIFO register stocks for receiving and transmitting data and control informationUS5381138Feb 4, 1994Jan 10, 1995Motorola, Inc.Intelligent over-the-air programmingUS5402416Jan 5, 1994Mar 28, 1995International Business Machines CorporationMethod and system for buffer occupancy reduction in packet switch networkUS5485505Jun 7, 1995Jan 16, 1996Bellsouth CorporationApparatus and method for remotely initiating operation of a cellular telephoneUS5511165Oct 23, 1992Apr 23, 1996International Business Machines CorporationMethod and apparatus for communicating data across a bus bridge upon requestUS5603084Mar 2, 1995Feb 11, 1997Ericsson Inc.Method and apparatus for remotely programming a cellular radiotelephoneUS5623483May 11, 1995Apr 22, 1997Lucent Technologies Inc.Synchronization system for networked multimedia streamsUS5684796Nov 23, 1994Nov 4, 1997Bay Networks Group, Inc.Method and apparatus for determining and maintaining agent topology information in a multi-segment networkUS5684959Apr 19, 1995Nov 4, 1997Hewlett-Packard CompanyMethod for determining topology of a networkUS5689499Mar 28, 1994Nov 18, 1997Curtin University Of TechnologyMethod and apparatus for managing the statistical multiplexing of data in digital communication networksUS5724517Sep 27, 1994Mar 3, 1998International Business Machines CorporationMethod for generating a topology map for a serial busUS5734824Dec 3, 1996Mar 31, 1998Bay Networks, Inc.Apparatus and method for discovering a topology for local area networks connected via transparent bridgesUS5751967Jul 15, 1996May 12, 1998Bay Networks Group, Inc.Method and apparatus for automatically configuring a network device to support a virtual networkUS5757772Oct 24, 1995May 26, 1998Telefonaktiebolaget Lm EricssonPacket switched radio channel traffic supervisionUS5764930Apr 1, 1996Jun 9, 1998Apple Computer, Inc.Method and apparatus for providing reset transparency on a reconfigurable busUS5774683Oct 21, 1996Jun 30, 1998Advanced Micro Devices, Inc.Interconnect bus configured to implement multiple transfer protocolsUS5790530Dec 15, 1995Aug 4, 1998Electronics And Telecommunications Research InstituteMessage-passing multiprocessor systemUS5790815May 17, 1996Aug 4, 1998Advanced Micro Devices, Inc.Computer system having a multimedia bus and comprising a centralized I/O processor which performs intelligent byte slicingUS5812774Jan 6, 1997Sep 22, 1998Cabletron Systems, Inc.System for transmitting data packet from buffer by reading buffer descriptor from descriptor memory of network adapter without accessing buffer descriptor in shared memoryUS5825752Sep 25, 1996Oct 20, 1998Yamaha CorporationLocal area network transferring data using isochronous and asynchronous channelsUS5832245Oct 21, 1996Nov 3, 1998Advanced Micro Devices, Inc.Method for isochronous flow control across an inter-chip busUS5842124Nov 16, 1996Nov 24, 1998Qualcomm IncorporatedSystem and method for user-programmable service programming of cellular telephonesUS5848266Jun 20, 1996Dec 8, 1998Intel CorporationDynamic data rate adjustment to maintain throughput of a time varying signalUS5854910Oct 21, 1996Dec 29, 1998Advanced Micro Devices, Inc.Method for accessing control and status registers across a peer-peer busUS5870387Dec 31, 1996Feb 9, 1999Hewlett-Packard CompanyMethod and apparatus for initializing a ringUS5872524May 14, 1996Feb 16, 1999Nec CorporationAutomatic address assignment methodUS5872944Sep 11, 1996Feb 16, 1999International Business Machines CorporationBus with request-dependent matching of the bandwidth available in both directionsUS5875301Jul 8, 1997Feb 23, 1999Apple Computer, Inc.Method and apparatus for the addition and removal of nodes from a common interconnectUS5883621Jun 21, 1996Mar 16, 1999Sony CorporationDevice control with topology map in a digital networkUS5892929Dec 30, 1996Apr 6, 1999Compaq Computer Corp.Avoiding non-unique identifiers for bus devicesUS5901332Aug 29, 1997May 4, 1999Advanced Micro Devices Inc.System for dynamically reconfiguring subbusses of data bus according to system needs based on monitoring each of the information channels that make up data busUS5905732Aug 27, 1996May 18, 1999Zenith Electronics CorporationPCR restamperUS5910178Jul 24, 1997Jun 8, 1999Electronics And Telecommunications Research InstituteMethod for controlling a message send in a packet-switched interconnection networkUS5920267Jan 26, 1998Jul 6, 1999Europlex Research LimitedRing network systemUS5923673Feb 13, 1997Jul 13, 1999Sony CorporationIEEE 1394 data/protocol analyzerUS5930703Mar 21, 1996Jul 27, 1999Ericsson Inc.Methods and systems for programming a cellular radiotelephoneUS5935208Nov 6, 1998Aug 10, 1999Apple Computer, Inc.Incremental bus reconfiguration without bus resetsUS5941964Jun 7, 1995Aug 24, 1999Intel CorporationBridge buffer management by bridge interception of synchronization eventsUS5961623Aug 29, 1996Oct 5, 1999Apple Computer, Inc.Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer systemUS5970234Jan 30, 1997Oct 19, 1999Samsung Electronics Co., Ltd.PCI bus arbiter and a bus control system having the sameUS5974036Dec 24, 1996Oct 26, 1999Nec Usa, Inc.Handoff-control technique for wireless ATMUS5978854Sep 11, 1997Nov 2, 1999Sony CorporationSystem using ARP or RARP packet for communicating offset address of an application program and node unique ID of a network nodeUS5991520Feb 2, 1996Nov 23, 1999Sony CorporationApplication programming interface for managing and automating data transfer operations between applications over a bus structureUS6005852Apr 22, 1998Dec 21, 1999Nokia Mobile Phones LimitedLoad control method and apparatus for CDMA cellular system having circuit and packet switched terminalsUS6023732Jul 24, 1997Feb 8, 2000Electronics And Teleconnunications Research InstituteMessage transfer apparatus for controlling a message send in a packet switched interconnection networkUS6032211Jun 17, 1998Feb 29, 2000Advanced Micro Devices, Inc.Method of mode control in a bus optimized for personal computer data trafficUS6038625Jan 6, 1998Mar 14, 2000Sony Corporation Of JapanMethod and system for providing a device identification mechanism within a consumer audio/video networkUS6055561Sep 30, 1997Apr 25, 2000International Business Machines CorporationMapping of routing traffic to switching networksUS6072772Jan 12, 1998Jun 6, 2000Cabletron Systems, Inc.Method for providing bandwidth and delay guarantees in a crossbar switch with speedupUS6085270Jun 17, 1998Jul 4, 2000Advanced Micro Devices, Inc.Multi-channel, multi-rate isochronous data busUS6104706Nov 10, 1999Aug 15, 2000Intelligence-At-Large, Inc.Method and apparatus for multiple media digital communication systemUS6108718Nov 12, 1997Aug 22, 2000Sony CorporationCommunication method and electronic apparatus thereofUS6119243Jul 6, 1998Sep 12, 2000Intel Corp.Architecture for the isochronous transfer of information within a computer systemUS6131119Apr 1, 1997Oct 10, 2000Sony CorporationAutomatic configuration system for mapping node addresses within a bus structure to their physical locationUS6137777Dec 29, 1997Oct 24, 2000Ukiah Software, Inc.Control tool for bandwidth managementUS6138178Jan 27, 1998Oct 24, 2000Fuji Photo Film Co., Ltd.Controlled device storing multiple drivers that judges and downloads a particular driver corresponding to a controller's operating system having an identical or greater version numberUS6138196Oct 7, 1999Oct 24, 2000Canon Kabushiki KaishaCommunication system for providing digital data transfer, electronic equipment for transferring data using the communication system, and an interface control deviceUS6141767Apr 3, 1998Oct 31, 2000Sony CorporationMethod of and apparatus for verifying reliability of contents within the configuration ROM of IEEE 1394-1995 devicesUS6151651Jun 17, 1998Nov 21, 2000Advanced Micro Devices, Inc.Communication link with isochronous and asynchronous priority modes coupling bridge circuits in a computer systemUS6185632Oct 19, 1998Feb 6, 2001Hewlett-Packard CompanyHigh speed communication protocol for IEEE-1394 including transmission of request and reply writes to a datagram-FIFO-address to exchange commands to end a jobUS6192428Feb 13, 1998Feb 20, 2001Intel CorporationMethod/apparatus for dynamically changing FIFO draining priority through asynchronous or isochronous DMA engines in response to packet type and predetermined high watermark being reachedNon-Patent CitationsReference1Hoffman, et al., Compcon '95, IEEE 1394: A Ubiquitous Bus, pp. 1-9, (visited Jan. 20, 2000) Mar. 5 to 9, 1995 <http://www.skipstone.com/compcon.html>.2Jennings, R., IEEE 1934 High Performance Serial Bus, Fire on Wire, pp. 1-18, (last modified Apr. 8, 1999) <http://www.chumpchange.com/parkplace/video/dvpapers/firewire.htm>.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6633943 *Sep 20, 2000Oct 14, 2003Sony CorporationMethod and system for the simplification of leaf-limited bridgesUS6751697 *Nov 27, 2000Jun 15, 2004Sony CorporationMethod and system for a multi-phase net refresh on a bus bridge interconnectUS6963938 *Aug 28, 2001Nov 8, 2005Canon Kabushiki KaishaInformation processing apparatus and method thereforUS7228366 *Jun 29, 2001Jun 5, 2007Intel CorporationMethod and apparatus for deterministic removal and reclamation of work items from an expansion bus scheduleUS7290073Apr 30, 2004Oct 30, 2007Avago Technologies Fiber Ip (Singapore) Pte LtdMaster slave serial bus apparatusUS7418527 *Jul 30, 2002Aug 26, 2008Thomson LicensingMethod and device for identifying devices connected to a communication networkUS9178716 *Oct 20, 2014Nov 3, 2015Silver Spring Networks, Inc.Method and system of providing IP-based packet communications in a utility networkUS20020026550 *Aug 28, 2001Feb 28, 2002Naohisa SuzukiInformation processing apparatus and method thereforUS20030005197 *Jun 29, 2001Jan 2, 2003Abramson Darren L.Method and apparatus for deterministic removal and reclamation of work items from an expansion bus scheduleUS20040221085 *Apr 30, 2004Nov 4, 2004Agilent Technologies, Inc.Master slave arrangementUS20040243733 *Jul 30, 2002Dec 2, 2004Guillaume BichotMethod and device for identifying devices connected to a communication networkUS20150039742 *Oct 20, 2014Feb 5, 2015Silver Spring Networks, Inc.Method and system of providing ip-based packet communications in a utility network* Cited by examinerClassifications U.S. Classification710/311, 710/100International ClassificationH04L12/46, H04L12/40, H04L12/64, H04L29/06, H04L12/28, H04L12/24, H04L29/12Cooperative ClassificationH04L69/22, H04L41/12, H04L12/40091, H04L61/10, H04L29/12283, H04L12/40117, H04L29/12254, H04L61/6004, H04L2012/2849, H04L12/40078, H04L61/2092, H04L29/12018, H04L12/6418, H04L12/2803, H04L29/1232, H04L29/12801, H04L61/2046, H04L29/12273, H04L61/6022, H04L29/12839, H04L61/2038, H04L29/12264, H04L61/2053, H04L61/2061, H04L29/12009, H04L61/00, H04L12/4625, H04L41/0896European ClassificationH04L41/12, H04L41/08G, H04L61/10, H04L61/60D11, H04L61/20D, H04L61/60A, H04L61/20I, H04L61/20B, H04L61/20C, H04L61/20E, H04L12/46B7B, H04L29/12A3B, H04L12/64B, H04L29/12A3I, H04L29/12A3C, H04L29/12A3E, H04L29/12A3D, H04L12/40F6, H04L12/40F4, H04L29/12A9A, H04L29/12A1, H04L29/12A9D11, H04L12/40F10Legal EventsDateCodeEventDescriptionAug 7, 2000ASAssignmentOwner name: SONY CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JAMES, DAVID V.;FAIRMAN, BRUCE;REEL/FRAME:011061/0118Effective date: 20000726Owner name: SONY ELECTRONICS, INC., NEW JERSEYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JAMES, DAVID V.;FAIRMAN, BRUCE;REEL/FRAME:011061/0118Effective date: 20000726Jun 30, 2006FPAYFee paymentYear of fee payment: 4Jun 30, 2010FPAYFee paymentYear of fee payment: 8Aug 8, 2014REMIMaintenance fee reminder mailedDec 31, 2014LAPSLapse for failure to pay maintenance feesFeb 17, 2015FPExpired due to failure to pay maintenance feeEffective date: 20141231RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services