Source: https://patents.google.com/patent/US20020043682?oq=flatulence
Timestamp: 2018-02-25 22:00:09
Document Index: 459031189

Matched Legal Cases: ['art 1702', 'art 1703', 'art 1713', 'art 1732', 'art 1733', 'art 1743', 'art 1746']

US20020043682A1 - Non-volatile memory and semiconductor device - Google Patents
US20020043682A1
US20020043682A1 US09970719 US97071901A US2002043682A1 US 20020043682 A1 US20020043682 A1 US 20020043682A1 US 09970719 US09970719 US 09970719 US 97071901 A US97071901 A US 97071901A US 2002043682 A1 US2002043682 A1 US 2002043682A1
US09970719
US6597034B2 (en )
[0022]FIGS. 22A, 22B and 22C are graphs showing relationship between the substrate temperature and gate leak current of a P-channel TFT. FIG. 23A is a graph showing relationship between the substrate temperature and the peaks of the gate leak current of a P-channel TFT. VD denotes a drain voltage, ID denotes a drain current, and VG represents a gate voltage. The gate leak current has a peak value (denoted by IG(peak)) in this case.
[0070]FIG. 1 is a circuit diagram of a non-volatile memory according to the invention.
[0071]FIGS. 2A to 2D are diagrammatic illustrations showing a production process of a liquid crystal display device containing a non-volatile memory of the invention.
[0072]FIGS. 3A to 3D are diagrammatic illustrations showing a production process of a liquid crystal display device containing a non-volatile memory of the invention.
[0073]FIGS. 4A to 4E are diagrammatic illustrations showing a production process of a liquid crystal display device containing a non-volatile memory of the invention.
[0074]FIGS. 5A to 5C are diagrammatic illustrations showing a production process of a liquid crystal display device containing a non-volatile memory of the invention.
[0075]FIG. 6 is a cross sectional view of a liquid crystal display device containing a non-volatile memory of the invention.
[0076]FIGS. 7A to 7C are a perspective view and cross sectional views of a liquid crystal display device containing a non-volatile memory of the invention.
[0077]FIG. 8 is a diagram showing capacitances of a non-volatile memory of the invention.
[0078]FIGS. 9A to 9C are diagrammatic illustrations showing a production process of a liquid crystal display device containing a non-volatile memory of the invention.
[0079]FIGS. 10A to 10D are diagrammatic illustrations showing a production process of a liquid crystal display device containing a non-volatile memory of the invention.
[0080]FIGS. 11A to 11C are diagrammatic illustrations showing a production process of a liquid crystal display device containing a non-volatile memory of the invention.
[0082]FIGS. 13A to 13D are diagrammatic illustrations showing a production process of a liquid crystal display device containing a non-volatile memory of the invention.
[0083]FIGS. 14A to 14D are diagrammatic illustrations showing a production process of a liquid crystal display device containing a non-volatile memory of the invention.
[0084]FIGS. 15A to 15D are diagrammatic illustrations showing a production process of a liquid crystal display device containing a non-volatile memory of the invention.
[0085]FIGS. 16A to 16C are circuit diagrams of a non-volatile memory according to the invention.
[0086]FIGS. 17A to 17E are schematic views of semiconductor devices using a non-volatile memory according to the invention.
[0087]FIGS. 18A and 18B are a cross sectional view and a circuit diagram of a non-volatile memory according to the invention, respectively.
[0088]FIG. 19 is a diagram showing a conventional liquid crystal display device.
[0089]FIG. 20 is a graph showing a relationship between an applied voltage and a transmission light intensity of a liquid crystal display device.
[0090]FIGS. 21A to 21E are graphs showing measurement results of characteristics of a TFT.
[0091]FIGS. 22A to 22C are graphs showing measurement results of characteristics of a TFT.
[0092]FIGS. 23A and 23B are graphs showing measurement results of characteristics of a TFT.
[0093]FIGS. 24A and 24B are HR-TEM photographs showing magnified views of crystal grain boundaries of semiconductor thin films.
[0094]FIGS. 25A to 25C are photographs and a schematic illustration of electron beam diffractiometory.
[0095]FIGS. 26A and 26B are TEM photographs showing crystal grains of crystalline silicon films.
[0096]FIGS. 27A and 27B are photographs showing dark-field images of semiconductor thin films.
[0097]FIG. 28 is a graph showing a result of X-ray diffractiometory.
[0099]FIG. 1 shows a circuit diagram of a non-volatile memory of the Example. The non-volatile memory comprises plural memory cells, X and Y address decoders 101 and 102, and peripheral circuits 103 and 104. As shown in FIG. 1, the memory cell, in which a respective bit information is recorded, comprises two TFTs, one of which is a P-channel FAMOS (floating gate avalanche injection MOS) TFT having a floating gate (Tr1) and the other is an N-channel switching TFT (Tr2). The two TFTs (Tr1 and Tr2) are connected by their drain electrode in series, and a memory cell for one bit is constituted by the series connection circuit. In the non-volatile memory in the Example, the memory cells are arranged in a matrix form of 64 in column and 64 in row. Since each of the memory cells stores one bit information, the non-volatile memory of the Example has a memory capacity of 4,096 bits (ca. 4 kilobits). The peripheral circuits 103 and 104 are circuits for processing other signals.
[0109]FIGS. 2A to 2D are referred. A quartz substrate 201 is provided as a substrate having an insulating surface. A silicon substrate having a thermal oxidized film on the surface can be used instead of the quartz substrate. Furthermore, a substrate can be obtained by forming an amorphous silicon film on a quartz substrate, and then thermally oxidizing the film completely. A quartz substrate or a ceramics substrate having a silicon nitride film as an insulating film can also be used.
[0134]FIGS. 3A to 3D are referred. A metallic film (not shown in Figure) containing aluminum as a main component is formed and then subjected to patterning to produce bases 213, 214 and 215 of gate electrodes formed later. An aluminum film containing 2% by weight of scandium is used in the Example. The state until this step is shown in FIG. 3A. A part of the base 213 becomes a floating gate of a P-channel FAMOS TFT.
[0138]FIGS. 4A to 4E are referred. Impurity elements giving one electro-conductivity are added. As the impurity elements, P (phosphorous) or As (arsenic) may be used for N-type and B (boron) may be used for P-type.
[0149]FIGS. 5A to 5C are referred. Contact holes are formed in the interlayer insulating film 242, and then source-electrodes 243, 244 and 245 and drain electrodes 246 and 247 are formed to obtain the state shown in FIG. 5A.
[0163]FIG. 6 shows a state in which a memory cell including an FAMOS TFT, a pixel TFT and a logic circuit are integrated on the same substrate.
[0172]FIGS. 9A to 9C are referred. FIG. 9A shows a state corresponding to the state after completion of the step of FIG. 4B in Example 1. For steps before FIG. 9A, Example 1 can be referred to. In FIG. 9A, numeral 901 denotes a base substrate. Numeral 903 denotes a source region, 902 denotes a drain region, 904 denotes a low concentration impurity region, 905 denotes a channel forming region, 906 denotes a gate insulating film, 907 denotes a floating gate electrode, and 908 denotes a non-porous anodic oxidized film of a P-channel FAMOS TFT. Numeral 909 denotes a source region, 910 denotes a drain region, 911 denotes a low concentration impurity region, 912 denotes a channel forming region, 913 denotes a gate insulating film, 914 denotes a gate electrode, and 915 denotes a non-porous anodic oxidized film of an N-channel TFT. Numeral 916 denotes a source region, 917 denotes a drain region, 918 denotes a low concentration impurity region, 919 denotes a channel forming region, 920 denotes a gate insulating film, 921 denotes a gate electrode, and 922 denotes a non-porous anodic oxidized film of an N-channel TFT constituting a pixel TFT.
[0178]FIGS. 21A to 21E are referred. FIGS. 21A to 21E show the change of the gate leak current IG depending on the change of the first dose amount of boron in the TFT produced in Example 1. VD denotes the drain voltage, ID denotes the drain current, and VG represents the gate voltage.
[0179]FIGS. 21A to 21E and FIG. 23B show graphs where the first dose amount of boron is changed from 0 (None) to 6×1013 (6E 13) atoms/cm3. The gate leak current has a peak value (denoted by IG(peak)). It is understood from these graphs that when the first dose amount of boron is increased, the peak value of the gate leak current becomes large. Therefore, the gate leak current is increased when the low concentration impurity region is not present, and thus carriers are liable to be injected into the floating gate electrode.
[0180]FIG. 23B shows the relationship between the first dose amount of boron and the peak of the gate leak current.
[0183]FIGS. 10A to 10D are referred. FIG. 10A shows a state corresponding to the state after completion of the step of FIG. 3D (formation of a floating gate) in Example 1. For steps before FIG. 9A, Example 1 can be referred to.
[0201]FIGS. 13A to 13D are referred. A quartz substrate 1301 is prepared as a substrate having an insulating surface. A silicon substrate having a thermal oxidized film on the surface can be used instead of the quartz substrate. Furthermore, a substrate can be obtained by forming an amorphous silicon film on a quartz substrate, and then thermally oxidizing the film completely. A quartz substrate or a ceramics substrate having a silicon nitride film as an insulating film can also be used.
In the Example, the concentrations of C (carbon) , N (nitrogen), O (oxygen) and S (sulfur), the representative impurities, in the amorphous silicon film 1302 are all controlled to less than 5×1018 atoms/cm3, preferably 1×1018 atoms/cm3 or less. In the case where these impurities are present in a concentration more than this value, they adversely affect on crystallization, which may be a reason of deterioration of the film quality after crystallization.
[0222]FIGS. 14A to 14D are referred. A metallic film (not shown in Figure) containing aluminum as a main component is formed and then subjected to patterning to produce bases 1312, 1313 and 1314 of gate electrodes formed later. An aluminum film containing 2% by weight of scandium is used in the Example. The state until this step is shown in FIG. 14A. A part of the base 1312 becomes a floating gate of a P-channel FAMOS TFT.
[0226]FIGS. 15A to 15D are referred. Impurity elements giving one electro-conductivity are added. As the impurity elements, P (phosphorous) or As (arsenic) may be used for N-type and B (boron) may be used for P-type.
[0239]FIG. 16A shows a schematic circuit diagram of the non-volatile memory of the Example. FIG. 16B shows a cross sectional view taken on line A-A′ of FIG. 16A. FIG. 16C shows a circuit diagram equivalent to FIG. 16A.
[0247]FIGS. 18A and 18B are referred. FIG. 18A shows a constitution of an EEPROM of the Example. Numeral 1901 denotes a channel region, 1902 and 1903 denote source and drain regions, 1904 denotes a gate insulating film, 1905 denotes a floating gate electrode, 1906 denotes an anodic oxidized film, 1907 denotes a source electrode and 1908 denotes a control electrode, of a P-type TFT. Numeral 1909 denotes a low concentration impurity region, 1920 denotes a channel region, 1921 denotes a gate insulating film, 1923 denotes a gate electrode, 1924 denotes an anodic oxidized film and 1926 denotes an interlayer film, of a switching TFT.
[0248]FIG. 18B shows a memory in which EEPROMs of the Example are arranged in a matrix form. Numerals 1927 and 1928 denote address decoders.
[0258]FIG. 17A shows a portable computer, which is composed of a main body 1701, a camera part 1702, an image receiving part 1703, a operation switch 1704 and a liquid crystal display device 1705.
[0259]FIG. 17B shows a head mounting display, which is composed of a main body 1711, a liquid crystal display device 1712 and a belt part 1713.
[0260]FIG. 17C shows a projection display of from projection type, which is composed of a main body 1721, a light source 1722, a liquid crystal display device 1723, an optical system 1724 and a screen 1725.
[0261]FIG. 17D shows a cellular phone, which is composed of a main body 1731, a sound output part 1732, a sound input part 1733, a liquid crystal display device 1734, an operation switch 1735 and an antenna 1736.
[0262]FIG. 17E shows a video camera, which is composed of a main body 1741, a liquid crystal display device 1742, a sound input part 1743, an operation switch 1744, a battery 1745 and an image receiving part 1746.
[0281]FIG. 25C is an electron beam diffraction pattern obtained by irradiating an electron beam to single crystal silicon in the direction perpendicular to the {110} plane of the single crystal silicon. Generally, the orientation characteristics of a specimen are estimated from the comparison between the diffraction pattern of the single crystal and that of the specimen.
[0293]FIG. 26A is a TEM photograph of the crystalline silicon film after the crystallization step in Examples 1 to 4 at a magnification of 250,000. In the crystal grain (the black part and the white part appear due to the difference in contrast), defects pointed by the arrows are observed in a zigzag form.
[0295]FIG. 26B is a TEM photograph at the same magnification of the crystalline silicon films finally produced by the production processes of Examples 1 to 4. There is observed substantially no effect due to stacking faults or dislocation in the crystal grain, and it is confirmed to have very high crystallinity. The same tendency can be applied to the whole film. Although it is currently difficult to completely avoid any defect, it can be reduced to the level that there is substantially no defect.
(2) The electric field effect mobility (AFE), which is an index of the operation speed of a TFT, is as large as from 200 to 650 cm2/Vs (typically from 250 to 300 cm2/Vs) for an N-channel TFT and from 100 to 300 cm2/Vs (typically from 150 to 200 cm2/Vs) for a P-channel TFT.
[0324]FIG. 27A shows a TEM photograph (dark-field image) of the semiconductor thin films obtained by the production processes of Examples 1 to 4 at a magnification of 15,000. While there are white regions and black regions, it is indicated that regions having the same color have the same orientation.
[0326]FIG. 27B shows a TEM photograph (dark-field image) of the conventional high temperature polysilicon film at a magnification of 15,000. In the conventional high temperature polysilicon film, the regions having the same plane-azimuth are scattered, and the gathered part in the certain direction as in FIG. 27A cannot be found. It is considered that this is because the orientation of the neighboring crystal grains is entirely irregular.
a semiconductor active layer provided over an insulating substrate;
an insulating film provided over said semiconductor active layer;
a floating gate electrode provided over said insulating film;
a control gate electrode provided in contact with an upper-surface and a side surface of said anodic oxidized film.
2. A non-volatile memory as claimed in claim 1, wherein the number of unpaired bonds in a channel forming region of said semiconductor active layer is smaller than that in a source region and a drain region of said semiconductor active layer.
a control gate electrode provided in contact only with an upper surface of said anodic oxidized film.
4. A non-volatile memory as claimed in claim 3, wherein the number of unpaired bonds in a channel forming region of said semiconductor active layer is smaller than that in a source region and a drain region of said semiconductor active layer.
a control gate electrode provided in contact with an upper surface and a side surface of said anodic oxidized film,
wherein a channel forming region and a source region of said semiconductor active layer are in direct contact with each other, and the channel forming region and a drain region of said semiconductor active layer are in direct contact with each other.
6. A non-volatile memory as claimed in claim 5, wherein the number of unpaired bonds in said channel forming region is smaller than that in said source region and said drain region.
a control gate electrode provided in contact only with an upper surface of said anodic oxidized film,
8. A non-volatile memory as claimed in claim 7, wherein the number of unpaired bonds in said channel forming region is smaller than that in said source region and said drain region.
a driver circuit comprising TFTs driving said plural pixel TFTs; and
said non-volatile memory comprising a semiconductor active layer provided over an insulating substrate, an insulating film provided over said semiconductor active layer, a floating gate electrode provided over said insulating film, an anodic oxidized film obtained by anodic oxidation of said floating gate electrode, and a control gate electrode provided in contact with an upper surface and a side surface of said anodic oxidized film,
said pixel circuit, said driver circuit and said non-volatile memory being integrated over said insulating substrate.
10. A semiconductor device as claimed in claim 9, wherein said semiconductor device is a liquid crystal display device.
said non-volatile memory comprising a semiconductor active layer provided over an insulating substrate, an insulating film provided over said semiconductor active layer, a floating gate electrode provided over said insulating film, an anodic oxidized film obtained by anodic oxidation of said floating gate electrode, and a control gate electrode provided in contact only with an upper surface of said anodic oxidized film,
12. A semiconductor device as claimed in claim 11, wherein said semiconductor device is a liquid crystal display device.
US09970719 1997-08-29 2001-10-04 Non-volatile memory and semiconductor device Expired - Fee Related US6597034B2 (en)
US09138691 Continuation-In-Part US6323515B1 (en) 1997-08-29 1998-08-24 Non-volatile memory and semiconductor device
US09138691 Continuation US6323515B1 (en) 1997-08-29 1998-08-24 Non-volatile memory and semiconductor device
US20020043682A1 true true US20020043682A1 (en) 2002-04-18
US6597034B2 US6597034B2 (en) 2003-07-22
WO2012029674A1 (en) * 2010-09-03 2012-03-08 Semiconductor Energy Laboratory Co., Ltd. Field effect transistor and method for manufacturing semiconductor device
JPH0311390A (en) 1989-06-08 1991-01-18 Matsushita Electric Ind Co Ltd Projection type picture display device
GB9502717D0 (en) 1995-02-10 1995-03-29 Innovation Tk Ltd Digital image processing