Source: https://patents.google.com/patent/JP2012027655A/en
Timestamp: 2020-07-02 09:39:21
Document Index: 490487591

Matched Legal Cases: ['art 202', 'art 202', 'arts 202', 'art 1', 'art 2', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'art 202', 'arts 202', 'arts 202', 'art 108', 'art 109', 'art 1091']

JP2012027655A - Information processor and power-saving memory management method - Google Patents
Information processor and power-saving memory management method Download PDF
JP2012027655A
JP2012027655A JP2010165153A JP2010165153A JP2012027655A JP 2012027655 A JP2012027655 A JP 2012027655A JP 2010165153 A JP2010165153 A JP 2010165153A JP 2010165153 A JP2010165153 A JP 2010165153A JP 2012027655 A JP2012027655 A JP 2012027655A
JP2010165153A
Satoru Kokuni
哲 小国
晋 梶田
新一 町田
優子 石橋
2010-07-22 Application filed by Hitachi Ltd, 株式会社日立製作所 filed Critical Hitachi Ltd
2010-07-22 Priority to JP2010165153A priority Critical patent/JP2012027655A/en
2012-02-09 Publication of JP2012027655A publication Critical patent/JP2012027655A/en
An information processing apparatus and a power saving memory management method capable of appropriately supplying power to a memory used in the information processing apparatus are provided.
A task area unit that is an area for executing a predetermined process, and a power control unit that reads a task area unit in which a process is executed from the process and supplies power to the read task area unit from a power source And a control unit that executes a process in the task area unit supplied with power by the power control unit.
The present invention relates to an information processing apparatus such as a server and a power saving memory management method for managing a memory of the information processing apparatus with power saving.
In recent years, in an information processing apparatus such as a server, a large amount of memory has been installed in the information processing apparatus due to the spread of in-memory databases and virtualization technology in order to reduce the cost of the memory and realize a high-speed processing system. It is coming. However, mounting a large amount of memory in an information processing device limits the physical size of the information processing device due to an increase in the memory mounting space, and there is a limit to high-density mounting due to the amount of heat generated by the memory. there were.
Furthermore, in the information processing apparatus described above, when a large amount of memory is mounted, the power consumption and heat generation amount of the memory increase, the capacity of the power supply unit for supplying power increases, and the FAN that releases the generated heat to the outside of the apparatus. There was a drawback that it was necessary to improve the cooling system. This drawback is a major obstacle in the use of general information processing apparatuses. Specifically, there were problems such as an increase in physical space due to an increase in capacity of the power supply unit and an improvement in the cooling system, and an increase in power consumption associated therewith.
As an improvement measure, there is a technique in which one information processing apparatus is divided into a plurality of parts using a virtualization technique. In addition, there is a method for reducing the power consumption of a memory by temporarily saving a memory area that is less frequently used in another area for use in operating a general information processing apparatus. (For example, Patent Documents 1 and 2).
JP 2009-122733 A JP 2000-215100 A
When the above-described technology is used, the power supply is controlled between the unused memory area of the divided memory and the unused memory area, and the unused memory area is supplied with power. Can be stopped and power consumption can be reduced. However, even this method is not necessarily effective for the problem of heat generation of the information processing apparatus and the reduction of power consumption in applications where all divided memory areas are used. Even if a memory area that is used infrequently is temporarily saved to another area, if the corresponding memory area is used again, it is necessary to load and reuse the data from the saved area. It took a long time to reduce the power consumption and there was a problem that the effect was low. That is, there is a problem that power cannot be appropriately supplied to the memory used in the information processing apparatus.
The present invention has been made in view of the above, and an object of the present invention is to provide an information processing apparatus and a power saving memory management method capable of appropriately supplying power to a memory used in the information processing apparatus. And
In order to solve the above-described problems and achieve the object, an information processing apparatus according to the present invention includes a task area part that is an area for executing a predetermined process and the task area part in which the process is executed. A power control unit that reads from the process and supplies power from a power source to the read task region unit; and a control unit that executes the process in the task region unit to which the power is supplied by the power control unit; , Provided.
The present invention is also a power saving memory management method executed by the information processing apparatus.
ADVANTAGE OF THE INVENTION According to this invention, the information processing apparatus and power saving memory management method which can supply electric power appropriately with respect to the memory utilized with information processing apparatus can be provided.
It is a figure which shows the structure of the information processing apparatus provided with the memory management system. It is a figure which shows the example of a structure of a memory power control table. It is a flowchart which shows the process sequence of the power control process performed with information processing apparatus. It is a figure which shows the example at the time of determining the upper limit of the memory power supply site | part to which electric power is supplied simultaneously when there exist multiple non-volatile memories. It is a figure which shows the example at the time of optimizing arrangement | positioning of the memory power supply site | part which supplies electric power simultaneously when there exist multiple non-volatile memories.
Exemplary embodiments of an information processing apparatus and a power saving memory management method according to the present invention will be explained below in detail with reference to the accompanying drawings. Hereinafter, as an example of the information processing apparatus, a case where access to a memory provided in a server is detected and power supply to a memory area to be accessed is controlled is described. For example, a PC (Personal Computer) The present invention can also be applied to a case where power is supplied to a memory included in various information processing apparatuses such as mobile terminals.
FIG. 1 is a diagram illustrating a configuration of an information processing apparatus 101 including a memory management system according to the present embodiment. As illustrated in FIG. 1, the information processing apparatus 101 includes a processor 102, a main storage device 103, an auxiliary storage device 104, an I / O device device 105, and a memory power switch 110. . Further, the main storage device 103 includes a volatile memory 1031, a plurality of nonvolatile memories 1032, and a memory power control table 1091. It is assumed that the memory power control table 1091 is composed of a nonvolatile storage medium, similar to the nonvolatile memory 1032. Therefore, the memory power control unit 110 described later can supply and access data on the memory before the power supply is stopped, such as when the power supply of the information processing apparatus 101 is turned off. It has become.
The volatile memory 1031 has an operating system 106. The operating system 106 controls the start and stop of the information processing apparatus 101 and the overall operation of the information processing apparatus 101. Further, the operating system 106 includes a scheduler unit 107, a memory management unit 108, and a memory power control unit 109.
The scheduler unit 107 performs execution order and schedule management of processes executed by the processor 102. The memory management unit 108 designates and secures a memory area used by the process. The memory power control unit 110 notifies the memory power switch 110 of a signal (ON signal or OFF signal) indicating whether or not to supply power to the memory area used in the process. The power switch 110 is connected to an external power source (not shown), and switches the state of the power supplied from the outside (supply state or supply stop state) by the above-described ON signal or OFF signal.
Specifically, the memory power control unit 110 acquires information about the order in which the scheduler unit 107 executes instructions and information about the memory area specified by the memory management unit 108. In addition, the memory power control unit 110 further detects access to the memory area, and notifies the memory power switch 110 of the nonvolatile memory 1032 having a task area necessary for the access. The nonvolatile memory 1032 has a task area 10321 for executing various processes.
The processor 102 executes a process execution / interrupt process in response to a task processing instruction from the 120 operating system in the 110 volatile memory loaded in the main storage device 103. The auxiliary storage device 104 is a storage medium such as a hard disk device, for example. The I / O and device device 105 is, for example, a communication medium such as a network interface or a recording medium such as a tape device.
In the following, the main storage device 103 has two nonvolatile memories 1032 and controls to supply power with each nonvolatile memory 1032 as one unit. For example, these two nonvolatile memories 1032 As a unit, it is possible to control a predetermined group such as supplying power to the two nonvolatile memories 1032 simultaneously. In other words, the supply of power to the nonvolatile memory 1032 can supply power to the minimum part where the power supply can be controlled. Next, the memory power control table 1091 will be described.
FIG. 2 is a diagram illustrating an example of the configuration of the memory power control table 1091. 2, the memory power control table 1091 stores a memory address area 201, a memory power control part 202, a power supply state 203, a power supply elapsed time 204, and an elapsed time threshold value 205 in association with each other. is doing.
The memory address area 201 is an address where the task area 10321 included in the nonvolatile memory 1032 is located. The memory power control part 202 specifies a task area 10321 located in the memory address area 201.
For example, in the example shown in FIG. 1, two task areas 10321 have memory power control parts 202 of “memory part 1” and “memory part 2”, and the memory addresses [areas 201 of each memory part are “0x0000”. ˜0x000f ”and“ 0x0010 to 0x001f ”.
The power supply state 203 indicates whether or not power is supplied to the memory power control part 202. When power is supplied to the memory power control part 202, the power supply state 203 is in an “ON” state. When power is not supplied to the power control part 202, the power control part 202 is in an “OFF” state. As will be described later, the power supply state 203 is switched between an “ON” state and an “OFF” state by the memory power switch 110.
The power supply elapsed time 204 indicates the time from the start of power supply to the memory power control part 202. As will be described later, the power supply elapsed time 204 measures the time since the memory power control unit 109 started supplying power to the memory power control part 202, and stores the measured time as the power supply elapsed time 204. I am letting. In the following description, it is assumed that the memory power control unit 109 simply measures the time since the start of power supply to the memory power control unit 202, but in reality, the memory power control unit 109 has the time. It is assumed that the time is measured by a time measuring device such as a counter.
The elapsed time threshold value 205 is a threshold value for stopping the supply of power when a certain time has elapsed since the start of power supply to the memory power control part 202. As will be described later, the memory power control unit 109 determines whether or not the time from the start of power supply to the memory power control part 202 has passed the elapsed time threshold value 205, and the time is the elapsed time. When it is determined that the threshold value 205 has passed, the supply of power to the memory power control part 202 is stopped. Next, processing (power control processing) performed by the information processing apparatus 101 will be described.
FIG. 3 is a flowchart illustrating a processing procedure of power control processing performed by the information processing apparatus 101. As shown in FIG. 3, first, the memory power control unit 109 determines whether or not the information processing apparatus 101 is turned off (step S301), and the information processing apparatus 101 is turned off. If it is determined that the power is present (step S301; Yes), the power control process illustrated in FIG. 3 is terminated.
On the other hand, if the memory power control unit 109 determines that the information processing apparatus 101 is not powered off (step S301; No), the memory power control unit 109 acquires information such as the execution order and schedule of processes managed by the scheduler unit 107. The process of dispatching in the next time slot scheduled by the scheduler unit 107 is acquired (step S302).
Then, the memory power control unit 109 refers to the memory management unit 108, acquires the memory address used by the process, and determines the memory address area 201 in FIG. 2 from the acquired memory address (step S303). For example, the memory power control unit 109 reads a memory address included in an instruction in the process and used for processing, compares the read memory address with the memory address area 201 shown in FIG. The memory address area 201 including the address is specified.
In this embodiment, the case where the memory power control unit 109 acquires a process for dispatching in the next time slot scheduled by the scheduler unit 107 is described. However, from the start of power supply to the nonvolatile memory 1032 A certain amount of time is required before it can be used. Therefore, in consideration of such characteristics, the processes up to a plurality of time slots are acquired in advance, and the memory addresses used for processing are read and used in advance by reading the memory addresses included in the instructions within those processes. It is also possible to determine the memory address area 201 to be used.
Subsequently, the memory power control unit 109 refers to the memory power control table 1091 and specifies the memory power control part 202 corresponding to the memory address area 201 specified in step S303 (step S304), and specifies the specified memory power control part. The power supply state 203 corresponding to 202 is confirmed, it is determined whether the power supply state 203 is “ON” state or “OFF” state (step S305), and the memory power control unit 109 determines the specified memory power. When it determines with the electric power supply state 203 corresponding to the control part 202 being an "ON" state (step S305; Yes), it progresses to step S308.
On the other hand, when the memory power control unit 109 determines that the power supply state 203 corresponding to the specified memory power control part 202 is in the “OFF” state (step S305; No), the memory power control unit 109 In order to supply power to the power control unit 202, a power supply instruction is issued to the memory power switch unit 110 (step S306), and then the power in the memory power control table 1091 corresponding to the memory power control unit 202 that has issued the power supply instruction. The fact that it is “ON” is written in the supply state 203, and zero is set in the power supply elapsed time 204 (step S307).
Then, the memory power control unit 109 confirms the elapsed time of power supply to the memory power control part 202 of the memory power control table 1091 and the elapsed time of power supply to the memory power control part 202 exceeds the elapsed time threshold value 205. (Step S308), when it is determined that the elapsed time of power supply to the memory power control part 202 does not exceed the elapsed time threshold 205 (within a predetermined time) (step S308; No), The power supply elapsed time 204 in the memory power control table 1091 is reset to the elapsed time (step S308).
On the other hand, when the memory power control unit 109 determines that the elapsed power supply time to the memory power control part 202 exceeds the elapsed time threshold 205 (elapsed from a predetermined time) (step S308; Yes), the memory power The power supply state 203 of the control table 1091 is set to the “OFF” state, and the power supply elapsed time 204 is set to zero (step S310), and the power to the memory power control part 202 is supplied to the memory power switch 110. A stop instruction is executed (step S311). When step S311 ends, all the power control processing shown in FIG. 3 ends.
By repeatedly executing the above steps, power is supplied in advance to the memory power control unit 202 that is accessed by the operating system 106 so that the memory can be referenced / written to the memory from the operating system, and there is no memory power. Since power is not supplied to the control portion 202 and the memory cannot be referred to / written from the operating system, it is very useful for power saving of the memory system.
In the definition of the predetermined time used as the determination criterion in step S308, the administrator or the like does not set the time independently. For example, one time slot time of a process performed in the information processing apparatus 101 is defined in advance. After the memory power control unit 109 communicates with the scheduler unit 107 of the operating system 106 and acquires the state of the process being executed in the time slot, the predetermined time period defined above elapses and the state of the process is It is determined whether or not the process is terminated or interrupted, and when it is determined that the state of the process is terminated or interrupted, the memory power switch 110 immediately stops power to the memory power control unit 202. Stops power supply to the memory power control unit 202 in a shorter time by executing the instruction Rukoto is also possible. Further, as a special example of the memory power control, the memory address area 201 (memory power control part 202) with high access frequency can be always set to ON and managed.
As described above, the task area 10321 that is an area for executing a predetermined process is provided, and the memory power control unit 109 reads the task area 10321 in which the process is executed from an instruction in the process, and the read task area 10321 On the other hand, power is supplied from the power source, and the processor 102 executes a process in the task area 10321 to which power is supplied by the memory power control unit 109. Therefore, power is appropriately supplied to the memory used in the information processing apparatus. Can be supplied. For example, in the information processing apparatus, as the installed memory capacity increases, power is supplied only to the necessary memory, so that an increase in the amount of heat generation and power consumption can be suppressed. Further, it is possible to detect access to the memory of the information processing apparatus and control power supply to the memory portion when necessary. That is, since power is supplied when access to the memory is necessary, the power supply amount of the memory can be suppressed and a power saving system can be realized.
FIG. 4 is a diagram illustrating an example (modified example of the memory power control table 1091) in the case where there is a plurality of nonvolatile memories 1032 and the upper limit of the memory power supply portion 202 to which power is simultaneously supplied is determined. The example shown in FIG. 4 is an example of a configuration including ten nonvolatile memories 1032 that can control power supply. By defining three parts that can supply power at the same time, the upper limit of the required power 402 is 3 For example, the power supply load of a device that supplies power to the nonvolatile memory 1032 can be reduced from 10 to 3, and can be simplified. .
FIG. 5 is a diagram illustrating an example (a modification of the memory power control table 1091) in a case where the arrangement of the memory power supply parts 202 that simultaneously supply power is optimized when there are a plurality of nonvolatile memories 1032. In the example shown in FIG. 5, the slot 501 indicates the slot position of the physical nonvolatile memory 1032, and the heat generation amount 502 indicates the heat generation amount for each slot. In FIG. 5, the upper limit of the calorific value 503, which is the total calorific value of the group of three consecutive slots, is defined as 2.
In the example shown in FIG. 5, for example, the sleeping power control portions 202 (memory portion 1 and memory portion 2) corresponding to the slots 1 and 2 are in a power supply state (“ON” state) and generate heat. (The calorific value is “1”), and the calorific value from slot 1 to slot 3 grouped as one group is “2”, and the total calorific value is within 503. Yes. Thus, for example, in a memory system where the maximum heat generation amount is defined as “3”, by defining the upper limit “2” of the heat generation amount of the three physically continuous memory power control parts 202, the memory system The maximum heat generation amount becomes “2”, and the heat generation amount of the memory system can be suppressed and high-density mounting of the memory can be realized.
As described above, by using the modification shown in FIG. 4 or FIG. 5, it is possible to simplify a cooling system such as a power supply device or FAN that is a power supply unit of the information processing device, and to realize a power saving information processing device. The power consumption and heat generation amount of the memory used at the same timing can be suppressed, and for example, a power supply unit such as a power supply and a cooling system such as FAN can be simplified.
In addition, for example, in an information processing apparatus that is normally used for a low processing volume and that has an operating system or monitoring software that runs on a standby server of a hot standby system, the memory is powered only at the timing of access. Therefore, the sleep state can be maintained with more power saving.
DESCRIPTION OF SYMBOLS 101 Information processing apparatus 102 Processor 103 Main memory 1031 Volatile memory 1032 Non-volatile memory 10321 Task area 104 Auxiliary memory 105 I / O, Device device 106 Operating system 107 Scheduler part 108 Memory management part 109 Memory power control part 1091 Memory power control table 110 Memory power switch.
A task area that is an area for executing a predetermined process;
A power control unit that reads the task area unit in which the process is executed from the process and supplies power to the read task area unit from a power source;
In the task area unit to which the power is supplied by the power control unit, a control unit that executes the process;
The information processing apparatus includes a plurality of the task area units,
The power control unit causes the power to be supplied only to the task region unit read from the process among the plurality of task region units.
A plurality of task area units, a power supply state indicating whether or not each task area unit is supplied with the power, and an upper limit value of the task area unit that supplies the power are stored in association with each other. A power control table for
The power control unit causes the power to be supplied only to a number of the task area units determined by an upper limit value of the task area.
The task area unit is configured by a nonvolatile memory.
A schedule unit for determining the execution order of the processes;
The power control unit reads the task area unit from each of the processes ranked in the order determined by the schedule unit, and secures the task area unit before the process is executed.
A power saving memory management method performed by an information processing apparatus including a task area unit that is an area for executing a predetermined process,
A step of reading from the process the task area where the process is executed;
A power control step of supplying power from a power source to the task area unit read in the reading step;
A control step of executing the process in the task area unit to which the power is supplied in the power control step;
A power-saving memory management method comprising:
JP2010165153A 2010-07-22 2010-07-22 Information processor and power-saving memory management method Pending JP2012027655A (en)
JP2010165153A JP2012027655A (en) 2010-07-22 2010-07-22 Information processor and power-saving memory management method
US13/187,249 US8745426B2 (en) 2010-07-22 2011-07-20 Information processing apparatus and power saving memory management method with an upper limit of task area units that may be simultaneously powered
JP2012027655A true JP2012027655A (en) 2012-02-09
ID=45494526
JP2010165153A Pending JP2012027655A (en) 2010-07-22 2010-07-22 Information processor and power-saving memory management method
US (1) US8745426B2 (en)
JP (1) JP2012027655A (en)
JPH0981284A (en) * 1995-09-18 1997-03-28 Casio Comput Co Ltd Power supply control device and its method
JP2005284871A (en) * 2004-03-30 2005-10-13 Nec Electronics Corp Microcomputer and computer system
JP2000215100A (en) 1999-01-21 2000-08-04 Nec Corp Power-saving memory management system
2010-07-22 JP JP2010165153A patent/JP2012027655A/en active Pending
2011-07-20 US US13/187,249 patent/US8745426B2/en not_active Expired - Fee Related
US8745426B2 (en) 2014-06-03
US20120023349A1 (en) 2012-01-26
US8595522B2 (en) 2013-11-26 Monitoring transaction requests using a policy engine within a storage drive driver to change power capability and latency settings for a storage drive