Source: http://www.google.com/patents/US20030199262?dq=6,418,462
Timestamp: 2015-03-28 11:09:40
Document Index: 464437586

Matched Legal Cases: ['Application No. 2002', 'art 110', 'art 110', 'art 110', 'art 216', 'art 216', 'art 216', 'art 216', 'art 218', 'art 218', 'art 216', 'art 216', 'art 218', 'art 216', 'art 218', 'art 217']

Patent US20030199262 - Multi-clock domain data input-processing device having clock-reciving locked ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA multi-clock-domain data input processing device preferably includes: a clock-signal-receiving synchronous circuit that generates an output clocking signal by phase-delaying a first clock signal; a data input part having a delay locked loop (DLL); and an input-processing part. The data input part preferably...http://www.google.com/patents/US20030199262?utm_source=gb-gplus-sharePatent US20030199262 - Multi-clock domain data input-processing device having clock-reciving locked loop and clock signal input method thereofAdvanced Patent SearchPublication numberUS20030199262 A1Publication typeApplicationApplication numberUS 10/288,540Publication dateOct 23, 2003Filing dateNov 6, 2002Priority dateApr 23, 2002Also published asUS7038971Publication number10288540, 288540, US 2003/0199262 A1, US 2003/199262 A1, US 20030199262 A1, US 20030199262A1, US 2003199262 A1, US 2003199262A1, US-A1-20030199262, US-A1-2003199262, US2003/0199262A1, US2003/199262A1, US20030199262 A1, US20030199262A1, US2003199262 A1, US2003199262A1InventorsDae-Hyun ChungOriginal AssigneeDae-Hyun ChungExport CitationBiBTeX, EndNote, RefManReferenced by (16), Classifications (20), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetMulti-clock domain data input-processing device having clock-reciving locked loop and clock signal input method thereof
US 20030199262 A1Abstract
A multi-clock-domain data input processing device preferably includes: a clock-signal-receiving synchronous circuit that generates an output clocking signal by phase-delaying a first clock signal; a data input part having a delay locked loop (DLL); and an input-processing part. The data input part preferably inputs data in response to the first clock signal and the input-processing part transfers data in response to a second clock signal having a timing different from that of the first clock signal. A clock-signal applying method for operating the multi-clock-domain data input-processing device preferably includes the steps of: applying a plurality of clock signals to a signal-receiving clock conversion part; and applying a delayed clocking signal outputted from the DLL to the remaining parts of the data input-processing device. Images(16) Claims(20)
DETAILED DESCRIPTION OF THE INVENTION [0052] Korean Patent Application No. 2002-22260, filed Apr. 23, 2002, and entitled: �Multi-Clock Domain Input Processing Device Having Clock Signal Receiving Locked Loop and Clock Signal Input Method Thereof,� is incorporated by reference herein in its entirety. [0053] Hereinafter, an on-die termination control method and the related control circuit will be described according to embodiments of the present invention with reference to the accompanying drawings. Like reference numerals are used for designation of like or equivalent parts or portions having similar or identical functions throughout the drawings. [0054]FIG. 7 illustrates a block diagram of a conventional data input-processing unit having a signal-receiving delay locked loops (DLLs). FIG. 8 illustrates an associated operational timing diagram. [0055] The data input-processing unit shown in FIG. 7, includes signal-receiving Delay Locked Loop (R_DLL) 230 and Data Strobe Delay Locked Loop (DS_DLL) 220 at a second processing block 200A in a system having a free-running unidirectional data strobe function for high frequency operations. For convenience, the second block 200 and the first block 100 are respectively defined as a data input-processing unit adapted to a SDRAM and a CPU or a memory controller. Data provided by an output processing part 110A of the memory controller 100A is applied to a receiver 221 of a data input-processing unit 200A through a signal-transmitting buffer 112A, and a data strobe signal DS provided by the output processing part 110A is applied to DS_DLL 220 through a signal-transmitting buffer 114A. Also, a command signal CMD provided by the output processing part 110A is applied to a receiver 231 through a signal-transmitting buffer 119. A clock signal CLK is applied from an input node N1 to R_DLL 230. The input operations of a signal-receiving clock conversion part CCP, which uses multi-clock domain, are performed in a data input part 216, which is constructed via the connection of first and second latches 204 and 206, respectively. First latch 204 latches data received through the receiver 221 in response to a data strobe signal received at a clock terminal of first latch 204 through the DS_DLL 220, and the second latch 206 latches data from an output terminal Q of the first latch 204 in response to a clock signal CLK received at a clock terminal of second latch 206 through the R_DLL 230. [0056] A timing margin in the signal-receiving clock conversion part CCP is described with reference to FIG. 8, which shows signal timing at clock terminal CK and input terminal D of the first and second latches 204 and 206. As shown in FIG. 8, when a data strobe signal DS is applied through DS_DLL 220 as waveform A1 having a time delay T3 caused by DS_DLL 220, the output terminal Q of the first latch 204 (data waveform B1) is delayed by as much as a time delay T1 relative to waveform A1. This is due to data waveform B1 being applied to the receiver 221 in synchronization with a signal-transmitting clock CLK propagating through a signal-transmitting delay locked loop T_DLL 117. On the other hand, the clock signal applied to the second latch 206 is clock signal CLK propagating through R_DLL 230 and is represented as waveform C1. Thus, there exists in waveform C1 a time delay T2, which is caused by a mismatch between the paths of clock signal CLK and data strobe signal DS, and a time delay T4 associated with R_DLL 230. As a result, a standard tDQSS showing a difference in the timing between data strobe signal and clock signal is given as a value obtained by subtracting the total value of time intervals T1, T2, T3, T4 from a time interval tCC, which represents one period of the clock signal CLK. In other words, tDQSS=tCC−(T1+T2+T3+T4). [0057] For high frequency operations, clock signals of signal-transmitting and receiving parts are typically generated through respective DLLs. Additionally, the unidirectionally applied data strobe signal DS is also generated through DS_DLL 220. In the structure of a conventional data input-processing unit, such as that shown in FIG. 7, maximizing the timing estimation causes the timing margin of the signal-receiving clock conversion part CCP to be less than that of a unit that does not use an element, such as R_DLL 230 or DS_DLL 220. [0058] As a result, in order to keep the standard tDQSS within a predetermined regulated range for a DDR-SDRAM or other data input-processing unit, the timing margin of the signal-receiving clock conversion part CCP should be maximized. Disadvantageously, since it is difficult to perform high frequency operations without the use of elements R_DLL 230 or DS_DLL 220, it is necessary to obtain a timing margin in the clock conversion part CCP via the application of R_DLL or DS_DLL. [0059] A data input-processing unit and an improved clock signal applying method preferably produce a satisfactory timing margin in a signal-receiving clock conversion part CCP even when signal-receiving DLLs (R_DLL 230 and DS_DLL 220) are used in a data input part 216 having a high operating frequency. FIGS. 9, 11 and 12 illustrate structures of data input-processing units according to preferred embodiments of the present invention. [0060] Since it is recognized that jitter caused by use of DLL in a signal-receiving part represents a major factor in the degradation of the timing margin, there should be an application of R_DLL 230 or DS_DLL 220 such that the DLLs may be bypassed by clock signal and data strobe signals, respectively, when applied to signal clock conversion part CCP. In other words, to avoid any degradation of the timing margin, a clock CLK or a data strobe signal DS may preferably be applied directly to the signal-receiving clock conversion part CCP when present, while clock or data strobe signal output from the corresponding DLL may be used for all other functional blocks, except for the signal-receiving clock conversion part. The foregoing bypass methods may be selectively performed by separating them from an on-chip DLL or by trading off performance and complexity of DLLs. If capacitance increases excessively, the capacitances may be previously separated at an input pin level thereof. [0061] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. [0062]FIG. 9 illustrates a block diagram of a data input-processing unit having a signal-receiving DLL in accordance with a preferred embodiment of the present invention. The structure of FIG. 9 is similar to the structure of FIG. 7, except for the addition of input buffers 223 and 233, which each have an output connected to a clock terminal of the data input part 216, thereby allowing first and second clocking signals DS, CLK, to be directly applied to the clock terminals of data input part 216 through buffers 223 and 233, bypassing first and second delay locked loops 220 and 230, respectively, while signals outputted from first and second delay locked loops 220 and 230 are applied to all other parts of the data input-processing unit. [0063] In the structure of an input circuit designated as a second processing block 200B, a plurality of clock domains are preferably applied to perform a signal-receiving clock conversion. The first and second delay locked loops 220 and 230 are preferably constructed separately from a signal-transmitting synchronizing circuit to generate the first and second output clock signals synchronously-controlled on basis of the first and second clocking signals DS, CLK that are applied through the first and second buffers 223 and 233, respectively. The aforementioned input circuit may be applied to a data input-processing unit of a synchronous type dynamic random access memory or a data input part of CPU and the like. The data input-processing unit 200B preferably includes: a first receiver 221, which receives write data in response to the first output clock signal of the first delay locked loop 220; a second receiver 231, which receives command CMD in response to the second output clock signal of the second delay locked loop 230; a first latch circuit 204, which latches write data received at the first receiver 221 in response to the first clock signal DS applied when the write data is input; a second latch circuit 206, which latches the latched data output from the first latch circuit 204 in response to the second clock signal CLK applied with a timing different from that of the first clock signal for signal-receiving clock conversion; and an input-processing part 218, which input-processes the latch data output from the second latch circuit 206 in response to the first and second output clock signals applied through the delay locked loops 220, 230. [0064] An output OUT of the input-processing part 218 provides a synchronized write control signal or a data signal for writing data or processing data, respectively. The buffers 223, 233 may be implemented to provide for the conversion of clock signals from one type to another, such as converting a TLL level being to a CMOS level. Similarly, receivers 221 and 231 may also include a level conversion architecture (i.e., being constructed using CMOS clocked inverters.) The first and second latches 204 and 206, respectively, may be D-flipflops. [0065]FIG. 10 illustrates an operation timing diagram of the data input part shown in FIG. 9 with waveforms A2, B2, C2, which are similar to waveforms A1, B1, C1 in FIG. 8. By incorporating the embodiment of the present invention, tDQSS=tCC−(T1+T2), since the time delay intervals T3, T4 of FIG. 8 are eliminated. In other words, despite the use of DS_DLL 220 and R_DLL 230, the operation timing diagram of FIG. 10 is identical to that of FIG. 2, thus providing a timing margin that is adequate for high frequency operations. [0066] If the data input part 216 of the present invention is used in a DDR-SDRAM, the latch circuits 204 and 206 are preferably implemented as a three-level shift register and two-level register, respectively, for high-speed processing operations. Serial data signals that are input to the three- or two-level registers are preferably converted to parallel, in order to improve high-speed processing. As in the previous D-flipflop embodiment, data write signals are preferably primarily latched by synchronizing with the rising and falling edges of a data strobe signal and then secondarily latched by synchronizing with a clock signal at the following latch. [0067]FIG. 11 illustrates a block diagram of a data input-processing unit having a signal-receiving DLL in accordance with a second embodiment of the present invention. As shown in FIG.11, the data input-processing unit includes a clock signal-receiving synchronous circuit R_DLL 230 which generates a signal-receiving internal clock ICLK as an output clocking signal. By phase-delaying the second clock signal CLK by a predetermined time; a data input part 216 inputs data in sequential response to the first clocking signal DS that is applied simultaneously with the application of the data and to the second clocking signal CLK that is applied at a timing different from that of the first clock signal DS. An input-processing part 218 processes the data output from the data input part 216 in response to the signal-receiving internal clock ICLK of the clock signal-receiving synchronous circuit (clock signal receiving locked loop) R_DLL 230. [0068] The structure of FIG. 11 preferably includes only a clock signal-receiving synchronous circuit R_DLL 230 for controlling the phase of a signal-receiving clock in an input circuit, rather than the R-DLL 230 and DS_DLL 220 combination as in the preferred embodiment. A clock CLK received from an external source is preferably directly applied through a buffer 233 to the signal-receiving clock conversion part CCP. The signal-receiving internal clock ICLK output from the clock signal-receiving synchronous circuit R_DLL 230 is supplied to the input-processing part 218 and a receiver 231. As a result, despite the use of R_DLL 230, an adequate timing margin is provided for high frequency operations. [0069]FIG. 12 illustrates a block diagram of a data input-processing unit having a signal-receiving DLL according to a third embodiment of the present invention. The structure includes only DS_DLL 220 rather than the R_DLL 230 and DS_DLL 220 combination of the preferred embodiment. As in the other embodiments, the clocking signal bypasses the DS_DLL 220, and externally received data strobe signal DS is directly applied to the signal-receiving clock conversion part CCP through a buffer 223. [0070]FIGS. 13 and 14 illustrate representative DLLs, such as R_DLL 230 and DS_DLL 220 shown in FIGS. 9, 11 and 12. As shown in FIG. 13, a DLL (i.e., 220, 230) may include: a signal-receiving buffer 211, which receives an input clock signal IN; a variable delay unit 213, which outputs an output clock signal OUT by delaying a signal-receiving clock signal RCLK output from the signal-receiving buffer 211 in response to an applied digital control data CON; a phase detector 215, which detects a difference in the phase between signal-receiving clock signal RCLK and feedback clock signal FCLK to generate shifting control signals UP, DOWN; and a delay control part 217, which supplies to the variable delay unit 213 the digital control data CON to increase or decrease the amount of delay in response to the shifting control signal of the phase detector 215. Also, the DLL 220, 230 preferably includes a clock path replica 219 to generate the feedback clock signal FCLK using the output clock signal OUT and a dummy signal-receiving buffer 212. The time delay of the dummy signal-receiving buffer 212 is preferably the same as that of the signal-receiving buffer 211. [0071]FIG. 14 illustrates an exemplary diagram of a DLL, which includes a signal-receiving buffer 211 a; a delay unit 213 a; a phase detector 215 a, which generates a shifting control signal SR, SL to indicate shift-right or shift-left operations; a shift register 217 a, which controls the delay unit 213 a. The shift register 217 a provides the digital control data to increase or decrease the amount of time delay in response to the shifting control signal of the phase detector 215 a; a dummy buffer 219 a and a dummy signal-receiving buffer 212 a. Preferably, the delay amount of the dummy signal-receiving buffer 212 a is the same as that of the signal-receiving buffer 211 a, and the delay amount of the dummy buffer 219 a is the same as that of a buffer (not shown) using the output clock signal. [0072] The function of a data input/output (I/O) block is dependent on the design of the DLL which generates an internal clock. Although, a phase locked loop (PLL) may also be used for clock generation, DLL is generally used when a clock frequency does not have to be multiplied, as in DRAM since a DLL typically has less jitter than a PLL. A variable delay line, such as delay unit 213 a, which controls delay time is the primary determinate of the characteristics of the DLL. The variable delay line may use one of three methods, as follows: varying the delay of each delay cell using an analog method; controlling the number of delay cells; and controlling the number of delay cells for coarse locking and varying the delay of each delay cell using the analog method for fine locking. The first method is widely used, but has a disadvantage of a small operational frequency range. The second method has advantages of ease of control and of storage of the locking data as a digital value, but has a disadvantage of poor resolution, which results in a large jitter. The third method, which is more complex, provides wide operational frequency range using the advantages of the other two methods. [0073] The phase detector 215 a monitors a phase difference between two clocks, the magnitude of static skew, bang-bang jitter, and the like. The phase detector 215 a may be implemented using D-flipflop (D-F/F). However, there is an uncertainty window relating to a setup/hold window of the D-F/F, which increases jitter. Additionally, there is a disadvantage of generating bang-bang jitter in the D-F/F of the phase detector because it determines only that the phase error is positive or negative. The dummy buffer 219 a is preferably adapted as an alternative to harmonic locking. [0074] There may be a restriction on locking time depending on the applications of the DLL. For instance, a DDR-SDRAM should typically complete locking within 200 cycles. In a case of an open-loop type DLL representing a synchronous mirror delay, the locking may be completed only in two cycles, but it is difficult to guarantee the period of locking time with a closed loop type of a general DLL. The most common method of reducing the period of locking time is to sequentially perform coarse locking at a high speed followed by a fine locking procedure. [0075] The DDR-SDRAM has a very wide operational frequency range of tCK=7 ns-15 ns, so that DLL is generally constructed to control the time delay hierarchically. In considering power dissipation, a digital DLL may be used to store locking data as digital codes. Preferably, a DLL is not being operated when the DLL is not needed, thereby reducing power consumption. [0076]FIGS. 15 through 17 illustrate block diagrams of exemplary circuits for separating clock signals during signal-receiving clock conversion in accordance with the present invention. [0077] As shown in FIG. 15, the first and second DLLs 230, 230′, respectively, are preferably included in the data input-processing unit 200B, and direct clock signals CLK, CLK′ are obtained through buffers 233 and 233′ correspondingly connected to the input terminals of the first and second DLLs 230, 230′, respectively. Finally, the clock signals input to the input terminals of the first and second DLLs 230, 230′ are directly separated through clock input pins P1, P2 on the on-chip. [0078] As shown in FIG. 16, the performance and complexity of DLL may be traded off in the structure for selective bypass, (i.e., it illustrates a selective structure). In other words, when the first and second DLLs 230 and 230′, respectively, are included in the data input-processing unit 200B, a direct clock signal CLK is obtained only at the input terminal of the first DLL 230 if the performance of the second DLL 230′ is more favorable than that of the first DLL 230. [0079] As shown in FIG. 17, clocks may be separated at the pin level to avoid an extreme increase in capacitance. In the structure of FIG. 17, clock signals CLK, CLK′ to be directly used are input through pins P3, P4, respectively, and clock signals to be applied to the first and second DLLs 230, 230′ are input through pins P1, P2, respectively. [0080] In any of the structures shown in FIGS. 15 through 17, it is preferable according to the present invention that clock signal or data strobe signal bypass the DLL and be applied directly to the clock conversion part. It is apparent that various changes may be made in the specifications of the method for applying clock signals or the detailed connection structure of an input circuit. [0081] As described above, there are advantages in the multi-clock domain data input-processing unit having clock signal-receiving locked loop and the related clock signal applying method in that a plurality of clock signals are directly applied only to the signal receiving clock conversion part. The clock signals output from the delay locked loop are preferably applied to all the remaining parts of the data input-processing unit, except the signal-receiving clock conversion part, thereby securing a maximized timing margin at the clock conversion part and significantly reducing restrictions for high-speed operations. Thus, the operational speed of the semiconductor memory device is significantly improved by application of the multi-domain data input-processing unit according to the present invention. [0082] Several embodiments, including a preferred embodiment, of the present invention have been disclosed herein and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6903955 *Jun 6, 2003Jun 7, 2005Samsung Electronics Co., Ltd.Semiconductor memory device having consistent skew over entire memory coreUS7271634Nov 23, 2005Sep 18, 2007Advanced Micro Devices, Inc.Delay-locked loop having a plurality of lock modesUS7425858 *Jan 6, 2006Sep 16, 2008Advanced Micro Devices, Inc.Delay line periodically operable in a closed loopUS7519888Aug 4, 2006Apr 14, 2009Virage Logic CorporationInput-output device testingUS7573968 *Nov 30, 2004Aug 11, 2009Oki Semiconductor Co., Ltd.Data transmission circuit with serial interface and method for transmitting serial dataUS7590902Sep 12, 2006Sep 15, 2009Virage Logic CorporationMethods and apparatuses for external delay test of input-output circuitsUS7598726Aug 24, 2006Oct 6, 2009Virage Logic CorporationMethods and apparatuses for test methodology of input-output circuitsUS7616036Jan 25, 2006Nov 10, 2009Virage Logic CorporationProgrammable strobe and clock generatorUS7653849Sep 12, 2006Jan 26, 2010Virage Logic CorporationInput-output device testing including embedded testsUS7817761Jun 1, 2007Oct 19, 2010Advanced Micro Devices, Inc.Test techniques for a delay-locked loop receiver interfaceUS7876261 *Oct 28, 2008Jan 25, 2011Lockheed Martin CorporationReflected wave clock synchronizationUS7948812Jan 9, 2007May 24, 2011Rambus Inc.Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock driftUS8305821May 19, 2011Nov 6, 2012Rambus Inc.Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock driftUS8553475Nov 6, 2012Oct 8, 2013Rambus Inc.Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock driftUS8570881Jan 29, 2007Oct 29, 2013Advanced Micro Devices, Inc.Transmitter voltage and receiver time marginingEP1793524A1 *Dec 1, 2006Jun 6, 2007Agilent Technologies, Inc.Time-stamping at a fraction of a clock cycle* Cited by examinerClassifications U.S. Classification455/265, 455/260International ClassificationG11C7/10, H04L7/00, H03L7/081, H04L7/02, G11C11/4096, G06F5/06Cooperative ClassificationH04L7/0008, H04L7/02, G06F5/06, H03L7/0814, G11C7/222, H04L7/0037, G11C7/1072European ClassificationG11C7/22A, H03L7/081A1, G06F5/06, G11C7/10S, H04L7/02Legal EventsDateCodeEventDescriptionJun 24, 2014FPExpired due to failure to pay maintenance feeEffective date: 20140502May 2, 2014LAPSLapse for failure to pay maintenance feesDec 13, 2013REMIMaintenance fee reminder mailedNov 2, 2009FPAYFee paymentYear of fee payment: 4Nov 6, 2002ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHUNG, DAE-HYUN;REEL/FRAME:013480/0573Effective date: 20021009RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services