Source: http://www.google.com/patents/US20030065994?dq=5,815,794
Timestamp: 2017-11-18 10:23:44
Document Index: 674407895

Matched Legal Cases: ['art 13', 'art 14', 'art 13', 'art 14', 'art 20', 'art 30', 'art 30', 'art 20', 'art 10', 'art 20', 'art 30', 'art 21', 'art 30', 'art 30', 'art 30', 'art 30', 'art 30', 'arts 14', 'art 22', 'art 22', 'art 30', 'art 30', 'art 30', 'art 30', 'art 13', 'art 14', 'art 13', 'art 14', 'art 14']

Patent US20030065994 - Semiconductor device with malfunction control circuit and controlling method ... - Google Patents
An integrated circuit of a semiconductor device has a chip malfunction controlling circuit embedded in a chip. The circuit comprises a fusing part, to which a cutting will be made in the manufacturing process according to the result of the discrimination of a defect in a chip, with one end thereof being...http://www.google.com/patents/US20030065994?utm_source=gb-gplus-sharePatent US20030065994 - Semiconductor device with malfunction control circuit and controlling method thereof
Publication number US20030065994 A1
Also published as US6972612
Publication number 10277573, 277573, US 2003/0065994 A1, US 2003/065994 A1, US 20030065994 A1, US 20030065994A1, US 2003065994 A1, US 2003065994A1, US-A1-20030065994, US-A1-2003065994, US2003/0065994A1, US2003/065994A1, US20030065994 A1, US20030065994A1, US2003065994 A1, US2003065994A1
US 20030065994 A1
a second integrated circuit portion including a plurality of functional groups for reading the data stored in the first integrated circuit portion;
a set of programming circuitry for setting a first state when the device has been determined defective; and
output circuitry coupled to the set of programming circuitry for providing output signals to at least one of the functional groups so that the one functional group is inactivated and the defective device is disabled.
a first set of programming circuitry for setting a first state when the device has been determined defective;
a second set of programming circuitry for setting a second state to allow bypass of the first state; and
output circuitry coupled to the first and second sets of programming circuitry for providing an output signal to at least one of the functional groups, wherein a first level of the output signal is generated to disable the defective device and a second level of the output signal is generated to allow bypass of the first state.
3. A method for controlling circuit malfunction in a semiconductor device, the method comprising:
storing data on a first portion of an integrated circuit;
reading data stored in the first portion of the integrated circuit using a plurality of functional groups;
setting a first set of program circuitry to a first state when the device has been determined defective; and
providing an output signal from the program circuitry to inactivate one or more of the functional groups, disabling the defective device.
4. A method for controlling circuit malfunction in a semiconductor device, the method comprising:
storing data on a first portion of an integrated circuit, reading data stored in the first portion of the integrated circuit using a plurality functional groups;
setting a first set of program circuitry to a first state when the device has been determined defective;
setting a second set of program circuitry to a second state to allow bypass of the first state; and
providing an output signal from the first and second program circuitries to one or more of the functional groups, wherein a first level of the output signal is generated to disable the defective device and a second level of the output signal is generated to allow bypass of the first state.
5. The semiconductor device of claim 2, wherein the first state and the second level of the output signal are logic levels of low, and the second state and the second level of the output signal are logic levels of high.
a chip malfunction setting part for setting a first state when the device has been determined defective;
a chip malfunctional cancellation part for setting a second state in response to an external control signal to allow bypass of the first state; and
a functional selecting part coupled to the chip malfunction setting part and the chip malfunction cancellation part for providing an output signal to at least one of the functional groups in response to the first and second states, wherein a first level of the output signal is generated to disable a normal operation of the semiconductor device and a second level of the output signal is generated to recover a malfunctioned semiconductor device to an enable state.
7. The semiconductor device of claim 6, wherein the external control signal is a mode register setting command signal or a pad input signal.
a chip malfunction cancellation part for setting a second state during only a predetermined time in response to a pad input signal input through pads of the device to allow bypass of the first state during only the predetermined time; and
a functional selecting part coupled to the chip malfunction setting part and the chip malfunction cancellation part for providing an output signal to at least one of the functional groups in response to the first and second states, wherein a first level of the output signal is generated to disable a normal operation of the semiconductor device and a second level of the output signal is generated to recover a malfunctioned semiconductor device to an enable state during only the predetermined time.
9. The semiconductor device of claim 8, wherein the predetermined period of time is set as an input time of the pad input signal.
10. A semiconductor device having a memory cell array and a plurality of internal functional circuitry for allowing output of data from the memory cell array, comprising:
a chip malfunction setting part for outputting a chip malfunction signal when the semiconductor is determined defective;
a chip malfunction cancellation part for outputting a chip malfunction cancellation signal to change the chip malfunction signal to a chip enabling signal in response to an external input signal; and
a functional selecting part for generating a chip driving signal to release the chip malfunction signal in response to the chip malfunction cancellation signal and providing the chip driving signal to at least one of the internal functional circuitry.
11. The semiconductor device of claim 10, wherein the internal functional circuitry includes at least one input buffer.
12. The semiconductor device of claim 10, wherein the internal functional circuitry includes at least one output buffer.
13. The semiconductor device of claim 10, wherein the internal functional circuitry includes at least one direct current generator.
14. A method for releasing a semiconductor device set as a malfunction state, the method comprising the steps of:
generating a malfunction cancellation signal using an internal or external signal;
restoring a malfunction setting signal to a malfunction enabling signal in response to the malfunction cancellation signal; and
inputting the malfunction enabling signal to an internal functional circuit of the semiconductor device.
This application claims priority from Korean Priority Document No. 99-23426, filed on Jun. 22, 1999 with the Korean Industrial Property Office, which document is hereby incorporated by reference. This application is a continuation-in-part of U.S. patent application Ser. No. 09/597,792 and claims the benefit of the filing date of that application.
[0010]FIG. 1 is a diagram for illustrating a representative circuit disclosed in previous patents, including transistors T1, T2 and a fuse F1 between a pin 10 and a supply voltage VCC. At this time, when a test voltage, higher than the voltage added with the supply voltage VCC and the threshold voltage of transistors T1, T2, is applied to the pin 10, the transistors T1, T2 turn on or off according to the prior cutting or not-cutting of the fuse F1. If the fuse F1 is cut, the transistors T1, T2 are at their OFF state, and no current flowing between the pin 10 and the supply voltage VCC will be detected. If the fuse F1 is not cut, the transistors T1, T2 are at their ON state. Therefore, current flowing between the pin 10 and the supply voltage Vcc will be detected. According to cutting or not-cutting of the fuse F1, users can discriminate whether the chip has been repaired or not. For instance, if the chip producer determined that the fuse F1 should be cut in case of a repaired chip, a user can confirm by detecting the current flowing in a chip that the chip has been repaired.
[0022]FIG. 1 is a block diagram of a semiconductor device having a chip malfunction setting function according to a conventional prior art.
[0023]FIG. 2 shows an embodiment of the chip malfunction control circuit shown in FIG. 1.
[0024]FIG. 3 is a block diagram of a semiconductor device having a chip malfunction cancellation function.
[0025]FIG. 4 is a detailed circuit diagram illustrating the chip malfunction cancellation part and functional selecting part as shown in FIG. 3 according to an embodiment of the present invention.
[0026]FIG. 5 is a detailed circuit diagram illustrating the chip malfunction cancellation part and functional selecting part as shown in FIG. 3 according to another embodiment of the present invention.
[0027]FIG. 6 is a detailed circuit diagram illustrating the chip malfunction cancellation part and functional selecting part as shown in FIG. 3 according to yet another embodiment of the present invention.
FIGS. 7 to 10 are detailed circuit diagrams illustrating each of the circuit blocks that receives malfunction control signal created in the functional selecting part in FIG.3.
[0030]FIG. 1 is a block diagram for illustrating a semiconductor device having a chip malfunction controlling circuit in accordance with an embodiment of the present invention. A potential signal PMF (or also called a status signal) supplied from the chip malfunction controlling circuit 10 is applied to an input buffer 11, an output buffer 12, a chip internal circuit part 13 and a chip internal DC voltage generating part 14, which may be interconnected therebetween. At this time, the potential signal can be provided to at least one of those blocks of the input buffer 11, the output buffer 12, the chip internal circuit part 13 and the chip internal DC voltage generating part 14. If any one of those blocks does not properly function under the normal operational conditions of the chip, it becomes impossible for the chip to perform its normal operations.
[0036]FIG. 3 is a block diagram of a semiconductor device having a chip malfunction cancellation function according to an embodiment of the present invention, which further comprises a chip malfunction cancellation part 20 and a functional selecting part 30 compared with FIG. 1. The functional selecting part 30 outputs a malfunction controlling signal PMF_CON for allowing bypass of the malfunction setting signal PMF for setting the chip malfunction or allowing setting of the chip malfunction in response to a state of the malfunction cancellation signal PMFR that is generated from the chip malfunction cancellation part 20. In FIG. 3, the chip malfunction setting part 10 corresponds to the first set of programming circuitry, the chip malfunction cancellation part 20 corresponds to the second set of programming circuitry, and the functional selecting part 30 corresponds to the output circuitry. In addition, a second integrated circuit portion includes an input buffer 11, an output buffer 12, a chip internal circuit 13, and a chip internal DC voltage generator 14. A first integrated circuit portion includes a memory cell array of a semiconductor device (not shown). The malfunction controlling signal PMF_CON may be selectively input to any one of the input buffer 11, output buffer 12, chip internal circuit portion 13 and a chip internal DC voltage generator 14, or all of them.
[0038]FIG. 4 is a detailed circuit diagram showing one implementation of the chip malfunction cancellation part and the functional selecting part as shown in FIG. 3. The chip malfunction cancellation part 21 shown in FIG. 4 includes a fuse F10 by which laser or electric current may be cut off as an embodiment. The fuse F10 is connected to power voltage VCC at one terminal thereof and connected to a source of P channel MOS transistor PMOSFET, Q21 at the other terminal. A drain of the transistor Q21 is connected to a source of another P channel MOS transistor Q22. A drain of the transistor Q22 is commonly coupled to gates of the transistors Q21, Q22. Accordingly, the transistors Q21, Q22 may operate as diodes and correspond to the diode D1 of FIG. 2 equivalently. The resistance R1 is connected between the drain terminal of the transistor Q22 and the ground voltage VSS. The malfunction-cancellation signal PMFR is practically detected at the node N21, the drain terminal of the transistor Q22. The buffer including inverters Q23 Q25 is connected to the node N21 to shape a waveform of the malfunction cancellation signal PMFR that is obtained at the node N21. In this case, the buffer may include only one inverter.
In FIG. 4, the functional selecting part 30 includes an inverter IN1 for inverting the malfunction setting signal PMF, a NOR gate for receiving an output of the inverter IN1 at its one terminal and receiving the malfunction cancellation signal PMFR at the other terminal thereby generating a NOR response, and another inverter IN2 for inverting an output of the NOR gate NOR1, thereby generating the malfunction controlling signal PMF_CON. Accordingly, the malfunction setting signal PMF, which is applied as a high level by cutting off the fuse F10 of FIG. 2, is input to the functional setting part 30 and as a result the chip does not operate. In this case, when the malfunction-cancellation signal PMFR is applied as a high level, the logic level of the malfunction controlling signal PMF_CON becomes a high level, and the malfunctioned chip reverts to its previous state, that is, enabled. If the malfunction setting does not need to be released, the fuse F10 is not cut off. Thus, the functional setting part 30 receives the malfunction setting signal PMF as a high level and the malfunction-cancellation signal PMFR as a low level. As a result, all inputs of the NOR gate NOR1 become low levels and the output becomes a high level. The logic level of the malfunction controlling signal PMF_CON, output through the inverter IN2, becomes a low level, thereby maintaining the malfunction state.
Where there is a normal chip that was not set as a malfunction state, the fuse F10 does not need to be cut off. Accordingly, since the functional selecting part 30 receives both the malfunction cancellation signal PMFR and the mulfaction setting signal PMF as a low level, the logic level of the malfunction control signal PMF_CON is output as a high level. Thus, in this case, the chip remains as enabled.
In addition, in the case of a normal chip that was not set as a malfunction state, since the functional selecting part 30 receives the malfunction cancellation signal PMFR as a high level and the malfunction setting signal PMF as a low level, even though the fuse F10 was cut off, the logic level of the malfunction control signal PMF_CON is output as a high level. In this case, the chip is also at an enabled state.
The malfunction control signal PMF_CON is provided to at least one control terminal out of chip internal functional circuit portions, that is, the input buffer 11, output buffer 12, chip internal circuit portion 13, and chip internal DC voltage generating parts 14.
[0047]FIG. 5 is a detailed circuit diagram illustrating the chip malfunction cancellation part and functional selecting part as shown in FIG. 3 according to another embodiment of the present invention. This embodiment shows that the chip malfunction cancellation part 22 receives a mode register set (MRS) command that is input from an external side, creating a malfunction cancellation signal PMFR. As shown in FIG. 5, the chip malfunction cancellation part 22 includes a transmission gate PG1 receiving the mode register set MRS command, an inverter IN10 inverting the malfunction setting signal PMF to switch the transmission gate PG1, an inverter IN11 inverting an output of the inverter IN10, an inverter IN12 inverting an output of the transmission gate PG1, a NAND gate ND1 receiving an output of inverter IN11 and an output of inverter IN13 to create a NAND response, and an inverter IN14 inverting an output of the NAND gate ND1 to create a malfunction cancellation signal PMFR.
Accordingly, since the functional selecting part 30 receives as high levels both the malfunction cancellation signal PMFR and the malfunction setting signal PMF, the logic level of the malfunction control signal PMF_CON is output as a high level. As a result, a disabled state of that chip returns to a previous state, which is an enabled state.
If the malfunction setting does not need to be canceled or the malfunction setting needs to be set again after cancellation of the malfunction setting, the MRS command is input as a low level from an external side. The functional selecting part 30 receives the malfunction setting signal PMF as a high level and the malfunction cancellation signal PMFR as a low level. As a result, all inputs of the NOR gate NOR1 become low levels, and their outputs become high levels. Additionally, the logic levels of the malfunction control signal PMF_CON output through the inverted IN2 become low levels, and the disabled state of the malfunction function is continuously maintained, or stopped, and returns to a malfunction state again.
[0051]FIG. 6 is a detailed circuit diagram illustrating the chip malfunction cancellation part and functional selecting part as shown in FIG. 3 according to yet another embodiment of the present invention.
Since the functional selecting part 30 receives as high levels both the malfunction cancellation signal PMFR and the malfunction setting signal PMF, the logic level of the malfunction control signal PMF_CON is output as a high level. Thus, the chip that is in a malfunction state turns to a previous state, i.e., an enabled state.
If the malfunction set state does not need to be canceled or the malfunction state needs to be set again after cancellation of the malfunction setting, the pad PAD is output with a voltage signal of ground level, i.e. OV. As a result, the functional selecting part 30 receives the malfunction setting signal PMF as a high level and the malfunction cancellation signal PMFR as a low level. Thus, all inputs of the NOR gate NOR1 become low levels and their outputs become high levels. The logic levels of the malfunction control signal PMF_CON that are output through the inverter IN2 become low levels and the disabled state of the malfunction function is continuously maintained, or the malfunction cancellation state returns to a malfunction state again. The malfunction state of a chip may be cancelled only while the pad is input with a high level and a defective chip is analyzed such that voltage is not applied through the pad. As a result, the defective chip is returned to a malfunction state.
Referring to FIG. 9, a chip internal circuit part 13 uses a clock signal P1. The invention teaches to AND gate the clock signal P1 with the discrimination signal. This can be by an AND gate made from NAND gate Q51 and inverter Q52. The signal is then delayed through four inverters Q53-Q56, to output signal P2.
The status signal PMF can be applied to a chip internal DC voltage generating part 14 which may operate in the controlling principle similar to the chip internal circuit part 13 even if there may be a difference in their structure. In this case, the chip internal DC voltage generating part 14 of the defective chip turns to its malfunction state. There are many kinds of chip internal DC voltage generating part 14 such as internal supply voltage generator for generating internal supply voltage IVCC, negative voltage generator for generating negative voltage VBB, half supply voltage generator for generating half supply voltage VBL (½ VCC) and the like. However, as shown in FIG. 10, only the internal supply voltage generator 14′ for generating the internal supply voltage IVCC and its controlling procedure will be described as an embodiment.
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U.S. Classification 714/708, 257/E23.179
International Classification G11C29/00, H01L23/544, G01R31/30, G11C17/18
Cooperative Classification H01L2223/5444, H01L23/544, G11C17/18, H01L2924/0002, G11C2029/4402, G01R31/30, G11C29/006
European Classification G11C17/18, G11C29/00W, G01R31/30, H01L23/544