Source: http://www.google.com/patents/US20030122231?ie=ISO-8859-1
Timestamp: 2014-07-12 19:21:04
Document Index: 139548324

Matched Legal Cases: ['art 9', 'art 39', 'art 39', 'arts 65', 'arts 65', 'art 94', 'arts 95']

Patent US20030122231 - Chip package and method of manufacturing the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA chip package includes a chip having a first surface provided with a first terminal and a second surface provided with at least one second terminal, the second surface being opposite to the first surface, a first conductive layer formed on the first surface of the chip, a second conductive layer formed...http://www.google.com/patents/US20030122231?utm_source=gb-gplus-sharePatent US20030122231 - Chip package and method of manufacturing the sameAdvanced Patent SearchPublication numberUS20030122231 A1Publication typeApplicationApplication numberUS 10/321,595Publication dateJul 3, 2003Filing dateDec 18, 2002Priority dateDec 27, 2001Also published asCN1206727C, CN1433070A, DE10259881A1, US6774492Publication number10321595, 321595, US 2003/0122231 A1, US 2003/122231 A1, US 20030122231 A1, US 20030122231A1, US 2003122231 A1, US 2003122231A1, US-A1-20030122231, US-A1-2003122231, US2003/0122231A1, US2003/122231A1, US20030122231 A1, US20030122231A1, US2003122231 A1, US2003122231A1InventorsMoon Ahn, Bang Oh, Kwang ChoOriginal AssigneeSamsung Electro-Mechanics Co., Ltd.Export CitationBiBTeX, EndNote, RefManReferenced by (1), Classifications (19), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetChip package and method of manufacturing the sameUS 20030122231 A1Abstract A chip package includes a chip having a first surface provided with a first terminal and a second surface provided with at least one second terminal, the second surface being opposite to the first surface, a first conductive layer formed on the first surface of the chip, a second conductive layer formed on the second surface of the chip, and a substrate attached to the second surface of the chip and including at least one conductive via hole connected to the second terminal of the chip. And the present invention provides a chip package assembly including the chip package. Further, a method of manufacturing the chip package and an assembly including the chip package are provided. The chip package does not use a bonding wire and additional conductive lands, thereby reducing the size of the package and simplifying the manufacturing process. Images(8) Claims(25)
What is claimed is: 1. A chip package comprising: a chip having a first surface provided with a first terminal, a second surface provided with at least one second terminal and a side wall placed between the first surface and the second surface, wherein the second surface being opposite to the first surface a first conductive layer formed on the first surface of said chip; a second conductive layer formed on the second surface of said chip; and a substrate attached to the second surface of said chip and including at least one conductive via hole connected to said second terminal of the chip. 2. The chip package as set forth in claim 1, further comprising a resin molding part formed along the side wall of said chip mounted on the substrate. 3. The chip package as set forth in claim 1, wherein a conductive layer is formed on the upper and the lower surface of said substrate, and the upper and the lower conductive layers are interconnected by said conductive via hole. 4. The chip package as set forth in claim 1, wherein said substrate is made of a printed circuit board. 5. The chip package as set forth in claim 1 having a hexahedral shape. 6. The chip package as set forth in claim 1, wherein said conductive via hole of said substrate is formed on at least one side of the substrate in an approximately semicircular shape. 7. The chip package as set forth in claim 1, wherein said conductive via hole of said substrate is formed on at least one corner of the substrate in an approximately quartered-circular shape. 8. The chip package as set forth in claim 1, wherein said chip is a diode element, and wherein said second surface of the chip comprises one second terminal and said substrate comprises one conductive via hole. 9. The chip package as set forth in claim 1, wherein said chip is a transistor element, and wherein said second surface of the chip comprises two second terminals and said substrate comprises two conductive via holes. 10. A chip package assembly comprising: a chip package comprising: a chip having a first conductive layer with a first terminal, a second conductive layer provided with at least one second terminal and a side wall placed between the first surface and the second surface, the second conductive layer being opposite to the first conductive layer; and a substrate attached to the second conductive layer of said chip and including at least one conductive via hole connected to said second terminal of the chip; and a printed circuit board comprising: a plurality of signal patterns formed on the upper surface of the printed circuit board and connected to said terminals of the chip package; and a plurality of conductors for connecting said first conductive layer and said conductive via hole to said signal patterns, wherein said chip package is vertically mounted on the upper surface of said printed circuit board so that outer surfaces of said first conductive layer and said substrate become side surfaces. 11. The chip package assembly as set forth in claim 10, further comprising a resin molding part formed along the side wall of said chip mounted on the substrate. 12. The chip package as set forth in claim 10, wherein a conductive layer is formed on the upper and the lower surface of said substrate, and the upper and the lower conductive layers are interconnected by said conductive via hole. 13. The chip package assembly as set forth in claim 10, wherein said substrate is made of a printed circuit board. 14. The chip package assembly as set forth in claim 10, wherein said chip package has a hexahedral shape. 15. The chip package assembly as set forth in claim 10, wherein said conductive via hole of said substrate is formed on at least one side of the substrate in an approximately semicircular shape. 16. The chip package assembly as set forth in claim 10, wherein said conductive via hole of said substrate is formed on at least one corner of the substrate in an approximately quartered-circular shape. 17. The chip package assembly as set forth in claim 10, wherein said chip is a diode element, and wherein said second surface of the chip comprises one second terminal and said substrate comprises one conductive via hole. 18. The chip package assembly as set forth in claim 10, wherein said chip is a transistor element, and wherein said second surface of the chip comprises two second terminals and said substrate comprises two conductive via holes. 19. A method of manufacturing a plurality of chip packages, said method comprising the steps of: preparing a wafer having a plurality of chips spaced by a designated interval; preparing a substrate having a plurality of via holes spaced by the same interval as the chips; attaching said wafer to the upper surface of said substrate so that terminals formed on the lower surfaces of the chips are connected to the conductive via holes of the substrate; and sawing the chip assembly into a plurality of unit chip packages. 20. The manufacturing method of the chip packages as set forth in claim 19, wherein a conductive layer is formed on the upper and the lower surface of said substrate, and the upper and the lower conductive layers are interconnected by said conductive via hole. 21. The manufacturing method of the chip packages as set forth in claim 19, wherein said step of attaching said wafer to the upper surface of said substrate comprises the sub-steps of: coating the upper surfaces of the conductive via holes of the substrate with a conductive adhesive; and compressing the lower surface of the wafer on the upper surface of the substrate. 22. The manufacturing method of the chip packages as set forth in claim 19, wherein said step of sawing the chip assembly into a plurality of unit chip packages comprises the sub-steps of: first-sawing said wafer into a plurality of the chips; filling spaces between neighboring chips with resin; and second-sawing said chip assembly into a plurality of the chip packages. 23. The manufacturing method of the chip packages as set forth in claim 22, wherein each of said first-sawing step and said second-sawing step is carried out by a designated blade, and a blade used in the first-sawing step has a thickness less than that of a blade used in the second-sawing step. 24. The manufacturing method of the chip packages as set forth in claim 19, wherein said chip is a diode element. 25. The manufacturing method of the chip packages as set forth in claim 19, wherein said chip is a transistor element, and wherein two terminals are formed on either one of said first and second surfaces of the chip and two conductive via holes are formed on the substrate so as to correspond to the two terminals.
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to the field of semiconductor manufacturing, and more particularly to a chip package, which is miniaturized and more simply manufactured by forming a conductive layer on both surfaces of a chip and by attaching a substrate provided with conductive via holes to one of these surfaces, and a method of manufacturing the chip package. [0003] 2. Description of the Related Art [0004] As well known to those skilled in the art, semiconductor elements such as diodes or transistors are packaged and these packaged elements are then mounted on a printed circuit board. Structurally, this package easily connects terminals of the semiconductor chip to corresponding signal patterns of the printed circuit board and serves to protect the semiconductor chip from external stresses, thereby improving reliability of the package. [0005] In order to satisfy recent trends of miniaturization of semiconductor products, the semiconductor chip packages also have been miniaturized. Therefore, a chip scale package has been introduced. FIG. 1 is a schematic cross-sectional view of a conventional chip scale package. The structure of the chip scale package 10 of FIG. 1 employs a ceramic substrate 1 and is applied to a diode with two terminals. [0006] With reference to FIG. 1, two via holes, i.e., a first via hole 2 a and a second via hole 2 b, are formed on the ceramic substrate 1. The first and the second via holes 2 a, 2 b are filled with a conductive material so as to electrically connect the upper and the lower surfaces of the first and the second via holes 2 a, 2 b. Then, a first and a second upper conductive lands 3 a, 3 b are formed on the upper surfaces of the first and the second via holes 2 a, 2 b, respectively. A first and a second lower conductive lands 4 a, 4 b are formed on the lower surfaces of the first and the second via holes 2 a, 2 b, respectively. The second upper conductive land 3 b is directly connected to a terminal formed on the lower surface of the diode 5, i.e., a mounting surface of the diode 5, on a printed circuit board, and the first upper conductive land 3 a is connected to the other terminal formed on the upper surface of the diode 5 by a wire 7. A molding part 9 using a conventional resin is formed on the upper surface of the ceramic substrate 1 including the diode 5 in order to protect the diode 5 from the external stresses. Thereby, the manufacture of the package 10 is completed. [0007]FIG. 2 is a schematic perspective view of a conventional chip package array. [0008] As shown in FIG. 2, the manufactured chip package 10 is mounted on the printed circuit board 20 by a reflow soldering. The diode package 10 is electrically and mechanically connected to the printed circuit board 20 by arranging the upper conductive lands 3 a, 3 b and the lower conductive lands 4 a, 4 b of the package 10 on the corresponding signal patterns of the printed circuit board 20 and by then connecting the upper conductive lands 3 a, 3 b and the lower conductive lands 4 a, 4 b to the signal patterns with a solder 15. [0009] As shown in FIGS. 1 and 2, since the diode usually has terminals on its two opposite surfaces, these terminals should be interconnected by wires. However, these wires require a rather large space on the upper surface of the chip, thereby increasing the overall height of the package. Further, since either two or three via holes, corresponding to the number of the terminals of the chip, are formed on the ceramic substrate, an area as large as the total diameters of the via holes is further required. Moreover, in order not to connect the conductive lands formed on the upper and the lower surfaces of the via holes to each other, the conductive lands are spaced from each other by a designated interval. Therefore, the size of the substrate imposes a limit in miniaturizing the package. [0010] Accordingly, a packaging technique, which can minimize the size of the package and simplify its manufacturing process, has been demanded. SUMMARY OF THE INVENTION [0011] Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a stable chip package, which is miniaturized, more simply manufactured and improves its reliability by forming a conductive layer on one surface of a chip and by attaching a substrate with conductive via holes to the other surface of the chip. [0012] It is another object of the present invention to provide a chip package assembly, which is mounted on a printed circuit board by a innovative method according to the structure of the chip package. [0013] It is a yet another object of the present invention to provide a method of manufacturing the chip package. [0014] In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a chip package comprising a chip having a first surface provided with a first terminal and a second surface provided with at least one second terminal, the second surface being opposite to the first surface, a first conductive layer formed on the first surface of the chip, a second conductive layer formed on the second surface of the chip, and a substrate attached to the second surface of the chip and including at least one conductive via hole connected to the second terminal of the chip. [0015] Preferably, a resin molding part formed along the outer wall of the chip mounted on the substrate may be further comprised. Further, preferably, a conductive layer may be formed on the upper and the lower surface of the substrate, and the upper and the lower conductive layers may be interconnected by the conductive via hole. The substrate may be a printed circuit board. [0016] Further, preferably, the conductive via hole of the substrate may be formed on at least one side of the substrate in an approximately semicircular shape or on at least one corner of the substrate in an approximately quartered circular shape. [0017] Moreover, preferably, the chip package may be applied to a diode element with two terminals or to a transistor element with three terminals. In case of the transistor element, the second surface of the chip may comprise two second terminals and the substrate may comprise two conductive via holes. [0018] In accordance with another aspect of the present invention, there is provided a chip package assembly comprising a chip package and a printed circuit board. The chip package comprises a chip having a first conductive layer with a first terminal and a second conductive layer provided with at least one second terminal, the second conductive layer being opposite to the first conductive layer, and a substrate attached to the second conductive layer of the chip and including at least one conductive via hole connected to the second terminal of the chip. The printed circuit board comprises a plurality of signal patterns formed on the upper surface of the printed circuit board and connected to the terminals of the chip package, and a plurality of conductors for connecting the first conductive layer and the conductive via hole to the signal patterns. Herein, the chip package is vertically mounted on the upper surface of the printed circuit board so that the outer surfaces of the first conductive layer and the substrate become side surfaces. [0019] Preferably, the conductor may be made of solder. [0020] In accordance with yet another aspect of the present invention, there is provided a method of manufacturing a plurality of chip packages. The method comprises the steps of preparing a wafer having a plurality of chips spaced by a designated interval, preparing a substrate having a plurality of via holes spaced by the same interval as the chips, attaching the wafer to the upper surface of the substrate so that terminals formed on the lower surfaces of the chips are connected to the conductive via holes of the substrate, and sawing the chip assembly into a plurality of unit chip packages. [0021] Preferably, a conductive layer may be formed on the upper and the lower surface of the substrate, and the upper and the lower conductive layers may be interconnected by the conductive via hole. [0022] Further, preferably, the step of attaching the wafer to the upper surface of the substrate may comprise the sub-steps of coating the upper surfaces of the conductive via holes of the substrate with a conductive adhesive, and compressing the lower surface of the wafer on the upper surface of the substrate. [0023] Moreover, preferably, the step of sawing the chip assembly into a plurality of unit chip packages may comprise the sub-steps of first-sawing the wafer into a plurality of chips, filling spaces between neighboring chips with resin, and second-sawing the chip assembly into a plurality of the chip packages. Herein, each of the first-sawing step and the second-sawing step is carried out by a designated blade. A blade used in the first-sawing step has a thickness less than that of a blade used in the second-sawing step.
BRIEF DESCRIPTION OF THE DRAWINGS [0024] The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: [0025]FIG. 1 is a cross-sectional view of a conventional chip package; [0026]FIG. 2 is a schematic perspective view of a conventional chip package array; [0027]FIG. 3 is a perspective view of a chip package in accordance with an embodiment of the present invention; [0028]FIG. 4 is a schematic perspective view of a chip package array in accordance with an embodiment of the present invention; [0029]FIG. 5 is a schematic perspective view of a chip package array in accordance with another embodiment of the present invention; [0030]FIGS. 6a to 6 e are cross-sectional views illustrating a method of manufacturing the chip package of the present invention; and [0031]FIGS. 7a and 7 b are schematic views, each illustrating a different shape of the via holes and the substrates using the via holes in accordance with yet another embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS [0032]FIG. 3 is a perspective view of a chip package in accordance with an embodiment of the present invention. [0033] With reference to FIG. 3, the package 40 includes a chip 35 and a substrate 31 formed on the lower surface of the chip 35. The chip 35 includes a first terminal (not shown) formed on the upper surface and a second terminal (not shown) formed on the lower surface. The first terminal and the second terminal are generally opposite to each other. An upper conductive layer 35 a is formed on the upper surface of the chip 35 with the first terminal, and a lower conductive layer 35 b is formed on the lower surface of the chip 35 with the second terminal. [0034] The chip 35 is attached to the upper surface of the substrate 31. A conductive via hole 33 is formed on the substrate 31. The lower conductive layer 35 b formed on the lower surface of the chip 35 is electrically connected to an external device by the conductive via hole 33 of the substrate 31. The lower conductive layer 35 b serves to more easily connect the terminal of the chip 35 to the substrate 31. The more exact connection of the terminal is achieved by adjusting the location and size of the conductive via hole 33. Herein, the conductive via hole 33 is filled with a conductive material so as to electrically connect the upper surface of the via holes 33 to the lower surface of the via hole 33. [0035] In the same manner, preferably, an upper conductive layer 31 a is formed on the upper surface of the substrate 31 and a lower conductive layer 31 b is formed on the lower surface of the substrate 31. The upper and the lower conductive layers 31 a, 31 b of the substrate 31 serve to easily connect the terminal of the chip 35 to signal patterns of a printed circuit board in mounting the package including the chip 35 on the printed circuit board, as well as to effectively connect the terminal of the chip 35 to the conductive via hole 33 of the substrate 31. [0036] In the chip package structure of FIG. 3, the terminal of the chip 35 is electrically connected to the external device through the conductive via hole 33. The location of the conductive via hole 33 is not limited, and will be further described in detail in FIG. 7. [0037] The package 40 further includes a resin molding part 39 for protecting the side surface of the chip 35 from external stresses. Herein, resin (for example, epoxy resin etc) used as the resin molding part 39 is the same as that of the molding part of the conventional package. [0038] The package 40 of this embodiment of the present invention does not need any wire requiring a large area. Further, since it is unnecessary to form at least two via holes and at least two conductive lands on a single ceramic substrate, an area for spacing the conductive lands is not required, thereby achieving a small-sized package, which is almost as much as the size of the chip. [0039] These characteristics of the chip package of the present invention are more apparent by mounting the chip package on a printed circuit board. FIG. 4 is a schematic perspective view of a chip package array 70 in accordance with an embodiment of the present invention. The chip package 60 is mounted on a printed circuit board 61. Herein, the chip package assembly refers to an assembly including a chip package and the printed circuit board on which the chip package is mounted. [0040] Differing from the conventional mounting method, in which the upper and the lower surfaces of the chip package with terminals are horizontal to the printed circuit board, the chip package 60 of the present invention is turned at an angle of 90 degrees and this turned chip package 60 is then mounted on the printed circuit board 61. That is, as shown in FIG. 4, In order to electrically connect the terminal of the chip 55 to the signal patterns of the printed circuit board 61 through the conductive via hole 53 and the upper and the lower conductive layers 51 a, 51 b of the substrate 51 and the upper conductive layer 551 of the chip 55, the chip package 60 is vertically mounted on the printed circuit board 61 so that the outer surfaces of the substrate 51 and the upper conductive layer 55 a of the chip 55 become side surfaces. [0041] Herein, solder parts 65 for connecting the signal patterns corresponding to each terminal to the lower conductive layer 51 b of the substrate 51 are formed on the printed circuit board 61. [0042] The signal patterns of the printed circuit board 61 are connected to the terminals of the chip 35 within the chip package 60 by the solder parts 65. [0043] In the chip package assembly of FIG. 4, in order to obtain a proper size of the chip package 60 being proper to the interval of the signal patterns, the size of the chip package 60 is changeable by adjusting the thickness of the substrate 51 attached to the lower surface of the chip package 60. Therefore, the chip package 60 of the present invention may be used without changing or modifying the signal patterns on the printed circuit board 61. [0044]FIG. 5 is a schematic perspective view of a chip package array in accordance with another embodiment of the present invention. The chip package array of this embodiment of the present invention is a transistor package array formed by packaging a transistor and mounting the packaged transistor on a printed circuit board 91. One terminal is formed on the upper surface of the transistor 85 and two terminals are formed on the lower surface of the transistor 85. Therefore, one upper terminal of the upper surface of the transistor 85 is connected to a signal pattern of the printed circuit board 91 through the upper conductive layer 85 a by a solder part 94. On the other hand, since two lower terminals are formed on the lower surface of the transistor 85, an additional method of connecting two lower terminals to the printed circuit board 91 is required. [0045] The lower surface of the transistor 85 with two separate lower terminals is attached to a substrate 81 provided with two conductive via holes 83 b, 83 c for connecting the upper and the lower surfaces of the substrate 81. A conductive layer is formed on the upper and the lower surfaces of the substrate 81 with two conductive via holes 83 b, 83 c. A non-conductive area A is formed on the upper and the lower conductive layers of the substrate 81 between the conductive via holes 83 b, 83 c, thereby connecting two separate lower terminals of the transistor 85 to the printed circuit board 91. Two conductive via holes 83 b, 83 c are connected to the wiring circuit of the printed circuit board 91 by the solder parts 95 b, 95 c through the conductive layers 81 b, 81 c of the lower surface of the substrate 81. [0046]FIGS. 6a to 6 e are cross-sectional views illustrating a method of manufacturing the chip package of the present invention. [0047] As shown in FIG. 6a, the substrate 101 is prepared. A plurality of conductive via holes 103 are formed on the substrate 101 and spaced by a designated interval. The interval of the conductive via holes 103 is identical with an interval of chips formed on a wafer. [0048] The upper conductive layer 101 a is formed on the upper surface of the substrate 101 and the lower conductive layer 101 b is formed on the lower surface of the substrate 101. The upper conductive layer 101 a serves to easily connect the terminal of the lower surface of the chip to the conductive via hole, and the lower conductive layer 101 b serves to easily connect the conductive via hole to the signal pattern of the printed circuit board. [0049] As shown in FIG. 6b, the wafer 105 including a plurality of the chips is attached to the upper surface of the substrate 101 by an adhesive. A conductive adhesive may be used as the adhesive. In case of using the conductive adhesive, a conductive layer formed on the upper surface of the substrate 101, i.e., the upper conductive layer 101 a, may be omitted. Therefore, the conductive adhesive serves to mechanically fix the chip wafer 105 to the substrate 101 as well as to electrically connect the chip wafer 105 to the conductive via hole 103 of the substrate 101. [0050] Then, as shown in FIG. 6c, the chip wafer 105 is sawed and cut into a plurality of individual chips 110′. Preferably, only the chip wafer 105 is sawed. That is, the substrate 101 attached to the lower surface of the chip wafer 105 is not sawed. As shown in FIG. 6d, spaces between the chips 110′ are filled with a resin 109. This resin 109 filling the spaces between the chips 110′ forms a resin molding part for protecting the side surface of the chip of a final package. [0051] Then, as shown in FIG. 6e, the manufactured assembly is sawed and cut into a plurality of chip packages, thereby obtaining final chip packages. At this time, the substrate 101 including the upper and the lower conductive layers 101 a, 101 b is thoroughly sawed. Herein, the sawing width is so thin that a designated thickness of the resin 109 remains around the side surface of the chip. Therefore, a sawing blade used in the step of FIG. 6e has a thickness less than that of the sawing blade used in the step of FIG. 6c. [0052] As described above, a plurality of the chip packages of the present invention may be easily manufactured using the substrate with the conductive via holes. [0053] In the chip package of the present invention, the conductive via holes act to electrically connect the terminals of the chip to the signal patterns of the printed circuit board by the soldering. This conductive via hole is not limited in its shape, but may be variously shaped. [0054]FIGS. 7a and 7 b show various shapes of the via holes and the substrates using the via holes, which can be used on the chip packages 210, 220 of the present invention. [0055] As shown in FIG. 7a, a conductive via hole 213 is formed at each corner of the substrate 211. These conductive via holes 213 are obtained by forming initial via holes 213′ on a crossing area of scribe lines of an initial substrate 211′, in forming the initial via hole 213′ on the initial substrate 211′. After sawing the initial substrate 211′ of FIG. 7a into a plurality of unit substrates 211, 4 quartered circular-shaped via holes 213 are formed at each corner of a single substrate 211. Two quartered circular-shaped via holes 213 may be formed at two corners of the same side of the substrate 211 and this side with two quartered circular-shaped conductive via holes 213 may be mounted on the printed circuit board. [0056] As shown in FIG. 7b, a conductive via hole 223 is formed at two opposite sides of substrate 221. These conductive via holes 223 are obtained by forming an initial via hole 223′ on a central area of scribe lines of an initial substrate 221′, in forming the initial via hole 223′ on the initial substrate 221′. After sawing the initial substrate 221′ of FIG. 7b into a plurality of unit substrates 221, 2 semicircular-shaped via holes 223 are formed at two opposite sides of a single substrate 221. One semicircular-shaped via hole 223 may be formed at a side of the substrate 221 and this side with a semicircular-shaped conductive via hole 223 may be mounted on the printed circuit board. [0057] In case of using the conductive via holes of FIGS. 7a and 7 b, when the manufactured chip package is turned at an angle of 90 degrees and the turned chip package is mounted on the printed circuit board, the conductive via holes can be close to the surface of the printed circuit board, thereby more easily connecting these conductive via holes of FIGS. 7a and 7 b to the signal patterns of the printed circuit board by the soldering step. [0058] As apparent from the above description, in accordance with the present invention, the chip package is more miniaturized and a manufacturing method of the chip package is more simplified by forming a conductive layer on one surface of a chip and by attaching a substrate with conductive via holes to the other surface of the chip. Further, the reliability of the chip package can be improved, thereby manufacturing a more stable package. [0059] Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8053885 *Jan 12, 2009Nov 8, 2011Harvatek CorporationWafer level vertical diode package structure and method for making the same* Cited by examinerClassifications U.S. Classification257/678, 257/E23.067, 257/E23.027, 257/E23.125International ClassificationH01L23/492, H01L23/31, H01L23/498, H01L23/48, H05K1/18, H01L21/48Cooperative ClassificationH01L24/48, H01L23/3121, H01L2224/4848, H01L23/4922, H01L23/49827, H01L2224/85051European ClassificationH01L23/498E, H01L23/31H2, H01L23/492HLegal EventsDateCodeEventDescriptionDec 2, 2011FPAYFee paymentYear of fee payment: 8Jan 17, 2008FPAYFee paymentYear of fee payment: 4Dec 18, 2002ASAssignmentOwner name: SAMSUNG ELECTRO-MECHANICS CO., LTD., KOREA, REPUBLFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AHN, MOON BONG;OH, BANG WON;CHO, KWANG CHEOL;REEL/FRAME:013592/0203Effective date: 20021211Owner name: SAMSUNG ELECTRO-MECHANICS CO., LTD. 314 MAETAN-3-DFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AHN, MOON BONG /AR;REEL/FRAME:013592/0203RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google