Source: https://patents.google.com/patent/JP5182993B2/en
Timestamp: 2019-11-17 11:14:59
Document Index: 311132227

Matched Legal Cases: ['art 303', 'art 303', 'art 303', 'art 307', 'art 307', 'art 306']

JP5182993B2 - Display device and manufacturing method thereof - Google Patents
JP5182993B2
JP5182993B2 JP2009073264A JP2009073264A JP5182993B2 JP 5182993 B2 JP5182993 B2 JP 5182993B2 JP 2009073264 A JP2009073264 A JP 2009073264A JP 2009073264 A JP2009073264 A JP 2009073264A JP 5182993 B2 JP5182993 B2 JP 5182993B2
JP2009073264A
JP2009265635A (en
JP2009265635A5 (en
2008-03-31 Priority to JP2008089241 priority Critical
2008-03-31 Priority to JP2008089241 priority
2009-03-25 Application filed by 株式会社半導体エネルギー研究所 filed Critical 株式会社半導体エネルギー研究所
2009-03-25 Priority to JP2009073264A priority patent/JP5182993B2/en
2009-11-12 Publication of JP2009265635A publication Critical patent/JP2009265635A/en
2012-02-23 Publication of JP2009265635A5 publication Critical patent/JP2009265635A5/ja
2013-04-17 Publication of JP5182993B2 publication Critical patent/JP5182993B2/en
The present invention relates to a display device using a thin film transistor in at least a pixel portion and a method for manufacturing the display device, and more particularly to a display device having a pixel portion with a high aperture ratio and a method for manufacturing the display device.
In recent years, large-sized liquid crystal modules with a diagonal size of 30 inches or 40 inches or more are actively developed for use as display devices such as liquid crystal televisions. In particular, high-definition panels for full high-definition (FHD) are in high demand. In particular, liquid crystal modules for use in liquid crystal televisions are required to have various characteristics such as high-speed response to follow moving images, excellent color reproducibility, sufficient luminance, and a high viewing angle in addition to the above-described high definition.
2. Description of the Related Art Conventionally, liquid crystal modules for liquid crystal televisions have used an active matrix type in which a plurality of pixels each having an active element including a thin film transistor (hereinafter referred to as TFT) using amorphous silicon (amorphous silicon) is used. In particular, the TFT generally has an inverted stagger structure suitable for mass production. The element substrate having the inverted staggered amorphous silicon TFT has a conductive film (hereinafter referred to as a first conductive film) first formed on the substrate as a scanning signal line (also referred to as a gate wiring), and gate insulation. A conductive film formed above the film (hereinafter referred to as a second conductive film) is used as a data signal line (or also referred to as a source wiring). The scanning signal lines are provided in the horizontal direction with respect to the substrate plane, and the data signal lines are provided in the vertical direction with respect to the substrate plane.
In a pixel structure in a conventional active matrix display device, an auxiliary capacitor (also referred to as an additional capacitor or a storage capacitor) for holding a data signal for one frame period is provided. This auxiliary capacity portion uses a first conductive film that becomes an auxiliary capacity line and a translucent conductive film that is provided in the uppermost layer and becomes a pixel electrode as a capacity electrode (see Patent Document 1), or an auxiliary capacity line. In this case, the first conductive film and the second conductive film connected to the translucent conductive film are used as capacitive electrodes (see Patent Document 2). The auxiliary capacitance line is provided in parallel with the scanning signal line. These auxiliary capacitance portions are all formed simultaneously in the manufacturing process of the inverted stagger type TFT or the pixel electrode, and the basic idea is to suppress the increase in the number of processes.
In addition, a structure is disclosed in which most of the gate wiring and the source wiring orthogonal to each other are formed with a first conductive film, and the source wiring divided at the intersection is bridged with a second conductive film (Patent Document 3). reference). Also disclosed is a structure in which a pixel electrode made of indium tin oxide (ITO) is formed on the gate insulating film as the auxiliary capacitance portion, and a counter electrode made of indium tin oxide (ITO) is formed with a passivation film interposed therebetween. (See Patent Document 4).
JP-A-2-48639 JP-A-6-202153 JP-A-1-101519 JP-A-5-289111
In the structure of Patent Document 1, a stacked layer of a gate insulating film, a passivation film, and an anodic oxide film is used as a dielectric film between capacitive electrodes. In this case, the sum of the thicknesses of the gate insulating film, the passivation film, and the anodic oxide film is the thickness of the dielectric film, so that the entire thickness of the dielectric film is large, and as a result, the capacitance that can be retained is reduced. End up. For this reason, it is necessary to increase the area of the auxiliary capacitance portion, but an increase in the area of the auxiliary capacitance portion is not desirable because it causes a decrease in the aperture ratio of the pixel portion.
In the structure of Patent Document 2, the dielectric film of the auxiliary capacitance portion is a single layer of the gate insulating film, and the film thickness of the dielectric film can be reduced as compared with the former case. However, the gate insulating film is usually thicker than the passivation film. The thickness of the gate insulating film is designed with the electrical characteristics of the TFT as the first purpose, and is designed in consideration of the electrical characteristics of the TFT and the dielectric strength of the gate insulating film. For this reason, the auxiliary capacitance portion is designed in a secondary manner so as to form a desired auxiliary capacitance portion in accordance with the thickness of the gate insulating film designed on the TFT side.
Therefore, it is ideal to increase the aperture ratio of the pixel portion by using only the passivation film having the thinnest thickness as the dielectric film of the auxiliary capacitance portion. However, in the conventional pixel structure typified by Patent Document 1 and Patent Document 2, the data signal line provided in the vertical direction of the substrate plane is formed by the second conductive film. It is impossible to form the auxiliary capacitance line running in the direction with the same second conductive film. Therefore, in the conventional pixel structure, it is difficult to form an auxiliary capacitor portion in which the light-transmitting conductive film and the second conductive film are used as capacitor electrodes and only the passivation film is used as a dielectric film.
Therefore, the structure of Patent Document 3 in which most of the gate wiring and the source wiring are formed with the first conductive film, and the source wiring divided at the intersection is bridged with the second conductive film can be given. Although not described in the patent document, since the auxiliary capacitance line made of the second conductive film can run in the lateral direction with respect to the substrate, the auxiliary capacitance portion using only the passivation film as a dielectric film is formed. Is possible. However, since the cross-linked structure is used, the data signal line is not formed of a single conductive film. That is, since it is necessary to connect with another conductive film, the contact resistance increases. Since two contacts are formed for each pixel in the row direction, particularly in a large panel having a diagonal of 30 inches or more, the wiring resistance is remarkably increased, resulting in a signal delay. Further, when even one contact failure occurs in the data signal line, all pixels ahead of the contact failure portion of the column connected to the data signal line become defective. Since so-called line defects are caused, reliability is lowered.
In the structure disclosed in Patent Document 4, an auxiliary capacitance unit having a lower electrode made of a pixel electrode, an upper electrode made of a counter electrode, and a dielectric film made of a passivation film can be formed. However, since a passivation film is included between the pixel electrode and the common electrode in addition to the liquid crystal, the electric field applied to the liquid crystal varies, resulting in a reduction in image quality.
In view of the above problems, an object of one embodiment of the present invention is to provide a highly reliable display device including a pixel with a high aperture ratio. Another object of one embodiment of the present invention is to manufacture a display device with a high aperture ratio at low cost.
In order to solve the above problems, according to one embodiment of the present invention, in a pixel portion, a scan signal line and an auxiliary capacitor line are formed using a second conductive film, and a data signal line is formed using a first conductive film. In the TFT portion, the gate electrode is formed of the first conductive film, and is electrically connected to the scanning signal line made of the second conductive film through the opening in the gate insulating film. The source electrode and the drain electrode are formed using a second conductive film. One of the source electrode and the drain electrode is electrically connected to the data signal line formed of the first conductive film through the opening in the gate insulating film. The other of the source electrode and the drain electrode is connected to a pixel electrode made of a light-transmitting conductive film through an opening portion of the passivation film and the planarization film. The pixel electrode is disposed so as to overlap the scanning signal line 101 and the data signal line 102 at the outer peripheral end. In the auxiliary capacitance portion, the auxiliary capacitance line made of the second conductive film is used as the lower electrode, and only the passivation film is used as the dielectric film, and the pixel electrode is used as the upper electrode through the capacitance electrodes.
In one embodiment of the present invention, the opening of the passivation film and the planarization film in the connection portion between the source electrode or the drain electrode and the pixel electrode and the opening of the planarization film in the auxiliary capacitor portion can be simultaneously formed into one photo. In order to form with a mask, photolithography using a multi-tone mask is performed.
One embodiment of the present invention includes a gate electrode formed using a first conductive film provided over a light-transmitting substrate, a data signal line formed using the first conductive film and extending in one direction, A first insulating film provided on the first conductive film; a semiconductor film provided on the first insulating film; and a second conductive film provided on the first insulating film and the semiconductor film. The formed source electrode and drain electrode, the second conductive film, the scanning signal line extending in a direction intersecting with one direction, the second conductive film, and intersecting with one direction. Storage capacitor line extending in the direction, a second insulating film provided on the second conductive film, a third insulating film provided on the second insulating film, and a third insulating film A pixel electrode that is provided on the outer peripheral edge and overlaps a data signal line, a scanning signal line, or a storage capacitor line; One of the drain electrode and the drain electrode is electrically connected to the semiconductor film and the data signal line, the other of the source electrode and the drain electrode is electrically connected to the semiconductor film and the pixel electrode, and the gate electrode is electrically connected to the scanning signal line. The auxiliary capacitance line is a display device in which a pixel electrode and an auxiliary capacitance portion are formed using the second insulating film as a dielectric film.
In another embodiment of the present invention, a gate electrode formed using a first conductive film provided over a light-transmitting substrate and data formed using the first conductive film and extending in one direction are provided. A signal line, a first insulating film provided over the first conductive film, a microcrystalline semiconductor film provided over the first insulating film, and a cross-sectional shape provided over the microcrystalline semiconductor film A concave buffer layer; a first impurity semiconductor film and a second impurity semiconductor film which are provided on the buffer layer and to which an impurity element imparting one conductivity type is added; a first insulating film; A source electrode and a drain electrode formed by a second conductive film provided over the impurity semiconductor film and the second impurity semiconductor film, and a second conductive film, and extending in a direction crossing one direction Formed by the scanning signal line and the second conductive film, and intersects one direction A storage capacitor line extending in the direction, a second insulating film provided on the second conductive film, a third insulating film provided on the second insulating film, and a third insulating film The pixel electrode overlapped with the data signal line, the scanning signal line, or the auxiliary capacitance line is provided on the outer periphery, and one of the source electrode and the drain electrode is electrically connected to the first impurity semiconductor film and the data signal line. The other of the source electrode and the drain electrode is electrically connected to the second impurity semiconductor film and the pixel electrode, the gate electrode is electrically connected to the scanning signal line, and the auxiliary capacitance line is The display device is characterized in that the pixel electrode and the auxiliary capacitor portion are formed using the insulating film of 2 as a dielectric film.
Note that the cross-sectional shape of the above-described semiconductor film is preferably concave. In addition, a first impurity semiconductor film and a second impurity semiconductor film to which an impurity element imparting one conductivity type is added are provided over the semiconductor film, and one of the source electrode and the drain electrode is formed with the first impurity semiconductor film. It is preferable that the impurity semiconductor film, the semiconductor film, and the data signal line are electrically connected, and the other of the source electrode and the drain electrode is electrically connected to the second impurity semiconductor film, the semiconductor film, and the pixel electrode.
Note that the third insulating film is preferably made of a photosensitive organic resin material.
Note that the data signal line and the auxiliary capacitance line preferably cross each other with the first insulating film interposed therebetween.
In another embodiment of the present invention, a gate electrode and a data signal line including a first conductive film are formed over a light-transmitting substrate, and the first insulating film and the semiconductor film are formed over the gate electrode and the data signal line. Are stacked in order, and the semiconductor film is etched to form a second semiconductor film above the gate electrode, the first insulating film is etched, and the first opening reaching the gate electrode Forming a second opening reaching the data signal line, forming a second conductive film over the first insulating film and the second semiconductor film, etching the second conductive film, A scanning signal line electrically connected to the gate electrode through the opening, a source electrode and a drain electrode electrically connected to the data signal line through the second opening, and an auxiliary capacitance line are formed The first insulating film, the second semiconductor film, the source electrode, the drain electrode, and the scanning signal. A second insulating film is formed on the line and the auxiliary capacitance line, a third insulating film is formed on the second insulating film, the second insulating film and the third insulating film are removed, and the drain electrode is formed. A third opening is formed, the third insulating film is removed, and a fourth opening is formed to expose the second insulating film formed above the storage capacitor line. A pixel electrode which is electrically connected to the drain electrode through the third opening on the film and forms the auxiliary capacitance line and the auxiliary capacitance portion using the second insulating film as a dielectric film in the fourth opening This is a method for manufacturing a display device.
In another embodiment of the present invention, a gate electrode and a data signal line including a first conductive film are formed over a light-transmitting substrate, and the first insulating film and the semiconductor are formed over the gate electrode and the data signal line. A film and an impurity semiconductor film to which an impurity element imparting one conductivity type is added are sequentially stacked, and a first mask layer is formed over the impurity semiconductor film by photolithography using a multi-tone mask Then, using the first mask layer, the first insulating film, the semiconductor film, and the impurity semiconductor film are etched to form a first opening that reaches the gate electrode and a second opening that reaches the data signal line. The second mask layer is formed by ashing the first mask layer, the semiconductor film and the impurity semiconductor film are etched using the second mask layer, and the second semiconductor film and the second impurity semiconductor are etched. Forming a first insulating film and a first insulating film; A second conductive film is formed over the impurity semiconductor film, a third mask layer is formed over the second conductive film, and the second conductive film and the second impurity are formed using the third mask layer. A scanning signal line electrically connected to the gate electrode through the first opening by etching the semiconductor film; a source electrode electrically connected to the data signal line through the second opening; A drain electrode, a storage capacitor line, a third impurity semiconductor film, and a fourth impurity semiconductor film are formed, and a first insulating film, a second semiconductor film, a third impurity semiconductor film, and a fourth impurity are formed. A second insulating film is formed over the semiconductor film, the source electrode, the drain electrode, the scanning signal line, and the auxiliary capacitance line, a third insulating film is formed over the second insulating film, and a photo that uses a multi-tone mask. The third opening and the third insulating film that expose the second insulating film to the third insulating film are formed by lithography. Forming a recess having a concave cross-sectional shape and a third insulating film remaining therein, etching the second insulating film in the third opening to form a fourth opening reaching the drain electrode; Ashing the third insulating film to form a fifth opening exposing the second insulating film formed above the storage capacitor line, and forming a fourth opening on the third insulating film. And the pixel electrode constituting the auxiliary capacitance line and the auxiliary capacitance portion is formed using the second insulating film as a dielectric film in the fifth opening and electrically connected to the drain electrode via the portion. This is a method for manufacturing a display device.
According to one embodiment of the present invention, in the storage capacitor portion of the display device, only the passivation film can be a dielectric film, and thus the thickness of the dielectric film can be reduced. As a result, the area of the auxiliary capacitor portion can be reduced, and the aperture ratio of the pixel portion can be improved accordingly. In addition, a display device with a high aperture ratio can be produced at low cost.
FIG. 6 is a plan view of a display device according to one embodiment of the present invention. 4A and 4B illustrate a film formation step of a display device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a display device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a display device according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a display device according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a display device according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a display device according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a display device according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a display device according to one embodiment of the present invention. 6A and 6B illustrate a multi-tone mask that can be used in one embodiment of the present invention. FIG. 6 is a cross-sectional view of a display device according to one embodiment of the present invention. 6A and 6B illustrate a display device according to one embodiment of the present invention. 6A and 6B illustrate a display device according to one embodiment of the present invention. FIG. 14 illustrates an electronic device according to one embodiment of the present invention. FIG. 11 is a block diagram illustrating a main structure of an electronic device according to one embodiment of the present invention.
Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the drawings in this specification, the same portions or portions having similar functions are denoted by the same reference numerals, and description thereof may be omitted.
In this embodiment, a display device including a thin film transistor (hereinafter referred to as a TFT) and a manufacturing process thereof will be described with reference to FIGS.
A TFT uses an n-type semiconductor as a semiconductor film rather than a p-type because the mobility of carriers is higher. Therefore, in this embodiment, the TFT is an n-type. Or p-type. Regardless of which polarity TFT is used, the number of steps can be reduced if all the TFTs formed on the same substrate have the same polarity. On the other hand, when both p-type and n-type are used, a drive circuit with low power consumption can be formed. Here, a pixel TFT using an n-channel TFT and a manufacturing process thereof will be described.
FIG. 1 is an example of a plan view of a display device having a TFT using an active matrix substrate of this embodiment mode. In FIG. 1, for simplification, one pixel configuration among a plurality of pixels arranged in a matrix shape. Is shown. 3 is a cross-sectional view taken along the line XZ-W of FIG. 1, and FIG. 4 is a cross-sectional view taken along the line Y-Z-W.
As shown in FIGS. 1, 3, and 4, the active matrix substrate includes a plurality of scanning signal lines 101 arranged in parallel to each other on a light-transmitting substrate 100 and data signal lines intersecting each scanning signal line 101. A plurality of 102 are provided. The scanning signal line 101 is provided in the horizontal direction with respect to the substrate plane, and the data signal line 102 is provided in the vertical direction with respect to the substrate plane. Here, the vertical direction and the horizontal direction are directions that can be taken arbitrarily, and the short side direction may be the vertical direction or the horizontal direction on the rectangular substrate plane. Further, a plurality of auxiliary capacitance lines 103 are provided in parallel with each scanning signal line 101. The data signal line 102 is formed of a first conductive film, and the scanning signal line 101 and the auxiliary capacitance line 103 are formed of a second conductive film. In addition, in a region surrounded by the scanning signal line 101 and the data signal line 102, the pixel electrode 110 made of a light-transmitting conductive film overlaps the scanning signal line 101 and the data signal line 102 at the outer peripheral end portion. Has been placed.
Further, a TFT is provided as a switching element near the intersection of the scanning signal line 101 and the data signal line 102. This TFT has a gate electrode 104 made of a first conductive film, a gate insulating film 111 on the gate electrode, a semiconductor film 105 on the gate insulating film, and an impurity element imparting one conductivity type on the semiconductor film 105. The doped impurity semiconductor films 112a and 112b and the source or drain electrodes 106a and 106b over the impurity semiconductor films 112a and 112b to which an impurity element imparting one conductivity type is added are included. Note that the TFT used in this embodiment mode is an inverted staggered TFT having a channel etch structure. However, the TFT which can be used in the present invention is not limited to this, and the form thereof can be changed without departing from the spirit and scope of the present invention.
In the TFT portion, the gate electrode 104 and the scanning signal line 101 are electrically connected through the opening 107 in the gate insulating film 111. In addition, one of the source or drain electrodes 106 a and 106 b and the data signal line 102 are electrically connected through the opening 108 in the gate insulating film 111. In addition, the other of the source or drain electrodes 106 a and 106 b and the pixel electrode 110 are electrically passed through the passivation film 113 and the planarization film 114 for the purpose of planarizing the pixel electrode 110 and the opening 109 in the passivation film 113. Connected. Note that since the source electrode and the drain electrode are determined according to the potential of the electrode, the positions of the source electrode and the drain electrode are switched depending on the potential of the electrode. The passivation film is a protective film for the purpose of preventing entry of contaminant impurities such as organic substances, metal substances, and water vapor floating in the air into the semiconductor layer.
The auxiliary capacitance portion has a structure in which the auxiliary capacitance line 103 made of the second conductive film is used as the lower electrode, the pixel electrode 110 is used as the upper electrode, with only the passivation film 113 as a dielectric film, in the opening 115. is there.
2A to 2D are diagrams illustrating a state in which the layers are stacked in the order of film formation. In FIG. 2A, the pattern of the data signal line 102 and the gate electrode 104 is formed using a first conductive film. In FIG. 2B, a pattern of the impurity semiconductor films 112a and 112b in which an impurity element imparting one conductivity type is added to the TFT portion in the TFT portion is formed over the gate insulating film 111. Further, openings 107 and 108 are formed in the gate insulating film 111. Note that the gate insulating film 111 and the impurity semiconductor films 112a and 112b to which an impurity element imparting one conductivity type is added are not illustrated in FIG. In FIG. 2C, the scanning signal line 101, the auxiliary capacitance line 103, and the source or drain electrodes 106a and 106b are formed using a second conductive film. In FIG. 2D, an opening 109 and an opening 115 are formed in the passivation film 113 and the planarization film 114 over the source or drain electrodes 106a and 106b. In addition, a pixel electrode 110 made of a light-transmitting conductive film is also formed on the passivation film 113 and the planarization film 114. Note that the passivation film 113 and the planarization film 114 are not illustrated in FIG.
By adopting the pixel configuration as described above, only the passivation film can be used as the dielectric film in the auxiliary capacitance section, so that the thickness of the dielectric film can be reduced. As a result, the area of the auxiliary capacitor portion can be reduced, and the aperture ratio of the pixel portion can be improved accordingly.
Further, since the data signal line can be formed of a single conductive film without providing a connection through the opening, signal delay due to contact resistance does not occur. Therefore, the wiring delay of the data signal can be reduced, so that a large display device with particularly high quality can be manufactured. Furthermore, even if a contact failure occurs in the data signal line, it does not become a line defect but remains a point defect. For this reason, the displayed image is less likely to have defects, leading to improvements in image quality and reliability. It also improves the yield from the viewpoint of mass production.
In addition, since there is no extra electrode between the pixel electrode and the counter electrode of the pixel capacitance portion, the electric field applied to the liquid crystal becomes uniform and the image quality is improved.
In addition, by using a planarizing film, the pixel electrode provided in the uppermost layer becomes flat without being affected by the uneven shape of the structure below it, so that the liquid crystal alignment disorder caused by the uneven shape is prevented. It is possible to suppress the ideal liquid crystal alignment. Therefore, high quality image display is possible. Further, since the parasitic capacitance between the pixel electrode and the data signal line, and between the pixel electrode and the scanning signal line can be remarkably reduced by inserting a planarization film, the outer peripheral edge of the pixel electrode, the data signal line, and the scanning signal line And the aperture ratio of the pixel can be increased.
Further, since the auxiliary capacitance line can be provided on the data signal line, the auxiliary capacitance portion can be formed even in a portion where the pixel electrode, the auxiliary capacitance line, and the data signal line overlap. Accordingly, the area of the storage capacitor line can be reduced by the area of the overlapping portion, so that the aperture ratio of the pixel can be increased.
In addition, in the HDTV (High Definition Television) standard pixel or the like, the adjacent interval of the scanning signal line is set wider than the adjacent interval of the data signal line. Therefore, by extending the auxiliary capacitance line in the same direction as the scanning signal line, it is possible to widen the interval between the adjacent scanning signal lines, thereby reducing the line capacitance (parasitic capacitance). In addition, since the adjacent interval between the scanning signal lines is wider than the adjacent interval between the data signal lines, the auxiliary capacitance line can be provided more easily between the scanning signal lines than between the data signal lines.
Hereinafter, the production method will be described in detail. 5A to 9B are diagrams illustrating a manufacturing process of a display device having a TFT. 5 to 9, YZW corresponds to a cross section taken along line YZW in FIG.
A first conductive film is formed over the light-transmitting substrate 200, and the data signal line 201 and the gate electrode 202 are formed (see FIG. 5A). The light-transmitting substrate 200 can withstand a processing temperature of quartz or this manufacturing process in addition to an alkali-free glass substrate manufactured by a fusion method or a float method such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass. A heat-resistant plastic substrate or the like can be used. The size of the translucent substrate 200 is 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 730 mm × 920 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm, 1500 mm × 1800 mm, 1900 mm × 2200 mm, 2160 mm × 2460 mm, 2400 mm × 2800 mm, 2850 mm × 3050 mm, or the like can be used.
Since the first conductive film serves as a wiring, it is preferable to use aluminum or copper which is a low resistance material. By using aluminum or copper, signal delay can be reduced and high image quality can be desired. In addition, the use of neodymium, silicon, copper and aluminum alloys, or neodymium, silicon, copper, and a mixture of aluminum has the effect of suppressing hillocks and whiskers, as well as electromigration and stress migration. . For the same reason, an alloy of silicon or the like and copper may be used. Moreover, these materials can be selected according to the etching solution at the time of wiring processing. For the data signal line 201 and the gate electrode 202, a conductive film is formed over the light-transmitting substrate 200 by a sputtering method, a vacuum evaporation method, or a metal organic chemical vapor deposition method (MOCVD), and a photolithography technique or an ink jet is formed over the conductive film. A mask layer can be formed by a method, and the conductive film can be etched using the mask layer. In addition, the data signal line 201 and the gate electrode 202 can be formed by discharging and baking the conductive nanopaste of silver, gold, copper, or the like by an inkjet method.
When aluminum or copper is used alone as the first conductive film, protrusions such as hillocks and whiskers are generated due to stress applied to the substrate and heat history applied in the subsequent manufacturing process. These break down the gate insulating film formed on them and cause defects such as electrical short-circuits. Therefore, refractory metals such as molybdenum, titanium, tungsten, and tantalum having barrier properties and nitrides thereof are laminated. Thus, it is preferable to form a barrier layer. In particular, when copper is used, it is preferable to form a barrier layer because copper may diffuse into the I-type amorphous silicon film serving as a channel formation region due to heat. The barrier layer may be provided between the translucent substrate 200, the data signal line 201, and the gate electrode 202, or may be provided above the data signal line 201 and the gate electrode 202.
Note that since a semiconductor film or a wiring is formed over the data signal line 201 and the gate electrode 202, it is preferable to process the end portion to have a forward taper shape in order to prevent disconnection and an electrical short circuit.
Next, a gate insulating film 203, a semiconductor film 204, and an impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added are sequentially formed over the data signal line 201 and the gate electrode 202 (see FIG. 5B). ).
Note that the gate insulating film 203, the semiconductor film 204, and the impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added are preferably formed successively without exposure to the air. By continuously forming the gate insulating film 203, the semiconductor film 204, and the impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added without being exposed to the atmosphere, atmospheric components and contaminating impurity elements floating in the atmosphere Since each stacked interface can be formed without being contaminated, variation in thin film transistor characteristics can be reduced.
The gate insulating film 203 can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film by a CVD method, a sputtering method, or the like. In this embodiment, a silicon nitride film is used as the gate insulating film 203. The silicon nitride film has a high relative dielectric constant and is preferable as a gate insulating film, and also has a function as a blocking film that prevents diffusion of alkali metal ions such as sodium contained in the glass substrate into the semiconductor film 204. Alternatively, the gate insulating film 203 may be formed by sequentially stacking a silicon nitride film or a silicon nitride oxide film and a silicon oxide film or a silicon oxynitride film. In addition, the gate insulating film 203 is not formed in two layers, but a silicon nitride film or a silicon nitride oxide film, a silicon oxide film or a silicon oxynitride film, and a silicon nitride film or a silicon nitride oxide film are stacked in this order from the substrate side. It can also be formed. Furthermore, it is preferable to form the gate insulating film 203 using a microwave plasma CVD apparatus having a frequency of 1 GHz. A silicon nitride film, a silicon nitride oxide film, and a silicon oxynitride film formed with a microwave plasma CVD apparatus have high withstand voltage and can increase the reliability of a thin film transistor to be formed later.
As an example of a three-layer stacked structure of the gate insulating film 203, a silicon nitride film or a silicon nitride oxide film as a first layer, a silicon oxynitride film as a second layer, and a third layer over the gate electrode 202 and the data signal line 201 Alternatively, a silicon nitride film may be stacked, and a semiconductor film may be formed on the uppermost silicon nitride film. In this case, the thickness of the first silicon nitride film or silicon nitride oxide film is preferably larger than 50 nm, and effects such as a barrier that blocks impurities such as sodium, prevention of hillocks in the gate electrode, and prevention of oxidation of the gate electrode Play. The third silicon nitride film has the effect of improving the adhesion of the semiconductor film and preventing oxidation.
Thus, by forming a nitride film such as an extremely thin silicon nitride film on the surface of the gate insulating film 203, the adhesion of the semiconductor film can be improved. The nitride film may be formed by a plasma CVD method, or nitridation may be performed by high-density and low-temperature plasma treatment using microwaves. Further, a silicon nitride film or a silicon nitride oxide film may be formed when the silane flash treatment is performed in the reaction chamber.
Here, the silicon oxynitride film has a composition that contains more oxygen than nitrogen, and includes Rutherford Backscattering (RBS) and Hydrogen Forward Scattering (HFS). ) In the range of 50 to 70 atomic% oxygen, 0.5 to 15 atomic% nitrogen, 25 to 35 atomic% Si, and 0.1 to 10 atomic% hydrogen. It means what is included. In addition, the silicon nitride oxide film has a nitrogen content higher than that of oxygen as a composition. When measured using RBS and HFS, the concentration range of oxygen is 5 to 30 atomic%, nitrogen. In the range of 20 to 55 atomic%, Si in the range of 25 to 35 atomic%, and hydrogen in the range of 10 to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.
The selection of the gate insulating film material and film forming means is an important factor in determining the film quality and film characteristics. When the conventional gate insulating film and passivation film are used as the dielectric film of the auxiliary capacitor portion, it is necessary to consider the relative dielectric constant of the gate insulating film when forming the auxiliary capacitor portion. However, in this embodiment, since only the passivation film is used as the dielectric film of the auxiliary capacitor portion, it is only necessary to consider only the TFT side design such as TFT characteristics and dielectric strength for the gate insulating film.
The semiconductor film 204 is a semiconductor film to which an impurity element imparting conductivity is not added and can be formed using an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor. In this embodiment mode, amorphous silicon is used for the semiconductor film 204.
Impurity semiconductor film 205 to which an impurity element is added that imparts one conductivity type, in the case of forming an n-channel thin film transistor is, phosphorus may be added as a typical impurity element, such as PH 3 silicon hydride The impurity gas may be added. In the case of forming a p-channel thin film transistor, boron may be added as a typical impurity element, and an impurity gas such as B 2 H 6 may be added to silicon hydride. The impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added can be formed using an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor. In this embodiment mode, amorphous silicon to which phosphorus is added at a high concentration is used as the impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added. Note that the impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added may have a thickness of 2 to 50 nm (preferably 10 to 30 nm). Note that the impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added is not necessarily formed. In that case, similarly to the impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added, an impurity element may be added to the semiconductor film 204 to form a source region and a drain region of the thin film transistor.
Next, mask layers 206a and 206b are formed over the semiconductor film 204 and the impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added (see FIG. 5C).
The mask layers 206a and 206b can be formed by exposure using a multi-tone (high-tone) mask. The mask layers 206a and 206b are formed of a resist. As the resist, a positive resist or a negative resist can be used. Here, a positive resist is used.
Next, using a multi-tone mask as an exposure mask, the resist is irradiated with light to expose the resist.
The multi-tone mask is composed of three parts: a light transmitting part that completely transmits light such as ultraviolet rays, a light semi-transmitting part that reduces light by blocking or absorbing light, and a light blocking part that completely blocks light. . Therefore, the multi-tone mask can perform three kinds of exposure levels, and the transmitted light has a plurality of intensities. By a single exposure and development process, a resist mask having a plurality of (typically two kinds) of thickness regions can be formed. For this reason, the number of exposure masks can be reduced by using a multi-tone mask.
Typical examples of the multi-tone mask include a gray-tone mask 301a as shown in FIG. 10A and a half-tone mask 301b as shown in FIG.
As shown in FIG. 10A, the gray tone mask 301a includes a light-transmitting substrate 302, a light blocking portion 303 formed thereon, and a diffraction grating 304 that is a light semi-transmissive portion. The light transmitting portion is a portion where the light shielding portion 303 and the diffraction grating 304 of the light transmitting substrate 302 are not formed. In the light shielding part 303, the transmissivity is 0%. On the other hand, the diffraction grating 304 can control the light transmittance by setting the interval between the light transmitting portions such as slits, dots, and meshes to be equal to or less than the resolution limit of light used for exposure. Note that the diffraction grating 304 can use either a periodic slit, a dot, or a mesh, or an aperiodic slit, dot, or mesh.
As the light-transmitting substrate 302, a light-transmitting substrate such as quartz can be used. The light shielding portion 303 and the diffraction grating 304 can be formed using a light shielding material that absorbs light, such as chromium or chromium oxide.
When the gray-tone mask 301a is irradiated with exposure light, as shown in FIG. 10B, in the light shielding part 303, the light transmittance 305 is 0%, and the light shielding part 303 and the diffraction grating 304 are provided. In the non-existing region, the light transmittance 305 is 100%. Further, in the diffraction grating 304, the transmissivity can be adjusted in the range of 10 to 70%. The light transmittance in the diffraction grating 304 can be adjusted by adjusting the spacing and pitch of slits, dots, or meshes of the diffraction grating.
As shown in FIG. 10C, the halftone mask 301b includes a light-transmitting substrate 302, a light semi-transmissive portion 306 and a light shielding portion 307 formed thereon. For the light semi-transmissive portion 306, MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like can be used. The light shielding portion 307 can be formed using a light shielding material that absorbs light, such as chromium or chromium oxide.
When the halftone mask 301b is irradiated with exposure light, as shown in FIG. 10D, in the light shielding part 307, the light transmittance 308 is 0%, and the light shielding part 307 and the light semi-transmissive part 306 are In a region where no light is provided, the light transmittance 308 is 100%. Further, in a portion where only the light semi-transmissive portion 306 is provided, the light transmittance can be adjusted in a range of 10 to 70%. The light transmittance in the portion where only the light semi-transmissive portion 306 is provided can be adjusted by the material of the light semi-transmissive portion 306.
Development is performed after exposure using the multi-tone mask as described above, whereby mask layers 206a and 206b having regions with different thicknesses can be formed (see FIG. 5C).
Next, the gate insulating film 203, the semiconductor film 204, and the impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added are etched using the mask layers 206 a and 206 b, so that the opening 207 reaching the data signal line 201 is formed. (See FIG. 6A). At this time, the gate insulating film 203, the semiconductor film 204, and the impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added are also etched in the XZ cross section shown in FIG. Forming part.
Next, the mask layers 206a and 206b are ashed. As a result, the areas of the mask layers 206a and 206b are reduced and the thickness is reduced. At this time, the resist of the mask layers 206a and 206b in the thin region is removed, so that the mask layer 208 can be formed (see FIG. 6B). Note that ashing is removal of a resist by chemically reacting an active oxygen molecule, ozone molecule, oxygen atom, or the like generated by discharge or the like with a resist which is an organic substance to cause ashing.
Using the mask layer 208, the semiconductor film 204 and the impurity semiconductor film 205 to which an impurity element imparting one conductivity type is added are etched, and the semiconductor film 209 and the impurity semiconductor film to which an impurity element imparting one conductivity type is added 210 is formed (see FIG. 6C). Thereafter, the mask layer 208 is removed.
A mask layer formed using a multi-tone mask as an exposure mask has a shape having a plurality of thicknesses, and the shape can be further deformed by ashing. Therefore, the mask layer is used for a plurality of etching processes for processing into different patterns. be able to. Therefore, a mask layer corresponding to at least two or more different patterns can be formed with one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can be reduced, so that the process can be simplified.
Note that in the case where a multi-tone mask is not used, the semiconductor film 204 and the impurity semiconductor film 205 to which the impurity element imparting one conductivity type is added are etched, and the semiconductor film 209 and the impurity element imparting one conductivity type are added. After forming the impurity semiconductor film 210, the opening 207 is preferably formed.
A second conductive film 211 serving as a source electrode, a drain electrode, and a scan signal line is formed over the opening 207, the gate insulating film 203, the semiconductor film 209, and the impurity semiconductor film 210 to which an impurity element imparting one conductivity type is added. (See FIG. 7A). Through the opening 207, the portion that becomes the source electrode or the drain electrode of the second conductive film is connected to the data signal line 201. At this time, also in the XZ cross section of FIG. 1, the gate electrode is connected to the portion serving as the scanning signal line of the second conductive film through the opening on the gate electrode.
The second conductive film 211 is preferably made of aluminum or copper, which is a low resistance material, like the first conductive film. By using aluminum or copper, signal delay can be reduced and high image quality can be desired. In addition, the use of neodymium, silicon, copper and aluminum alloys, or neodymium, silicon, copper, and a mixture of aluminum has the effect of suppressing hillocks and whiskers, as well as electromigration and stress migration. . For the same reason, an alloy of silicon or the like and copper may be used. In addition, it is preferable to form a barrier layer with a refractory metal such as molybdenum, titanium, tungsten, or tantalum having a barrier property, or a nitride thereof, and sandwich the above-described low-resistance material. In this case, the lower refractory metal on the lower resistance material suppresses interdiffusion between the impurity semiconductor film 210 to which the impurity element imparting one conductivity type is added and aluminum or copper, and the upper refractory metal is the pixel. There are effects such as prevention of corrosion due to battery reaction during connection with the electrode.
The second conductive film 211 may be formed by a sputtering method, a vacuum evaporation method, or a metal organic chemical vapor deposition method (MOCVD). Alternatively, the second conductive film 211 may be formed by discharging and baking a conductive nanopaste of silver, gold, copper, or the like using a screen printing method, an inkjet method, or the like.
Mask layers 212a to 212c are formed over the second conductive film 211 (see FIG. 7B).
The impurity semiconductor film 210 to which the impurity element imparting one conductivity type is added and the second conductive film 211 are etched using the mask layers 212a to 212c, and the impurity semiconductor to which the impurity element imparting one conductivity type is added. Films 210a and 210b, source or drain electrodes 213a and 213b, and an auxiliary capacitor line 214 are formed (see FIG. 7C). At this time, it is preferable that the semiconductor film 209 is also etched to make the cross-sectional shape of the semiconductor film 209 concave so that a channel-etched thin film transistor is obtained. By doing so, the impurity semiconductor films 210a and 210b to which the impurity element imparting one conductivity type is added can be completely divided and an electrical short circuit can be prevented. At this time, even in the XZ cross section shown in FIG. 1, the scanning signal line is formed by etching the second conductive film.
Next, the passivation film 215 is formed over the source or drain electrodes 213 a and 213 b, the storage capacitor line 214, the impurity semiconductor films 210 a and 210 b to which an impurity element imparting one conductivity type is added, the semiconductor film 209, and the gate insulating film 203. (See FIG. 8A).
The passivation film 215 can be formed in a manner similar to that of the gate insulating film 203. Note that the passivation film 215 is for preventing entry of contaminant impurities such as organic substances, metal substances, and water vapor floating in the air, and is preferably a dense film. In addition, since the passivation film 215 functions as a dielectric film in the auxiliary capacitance section, it is desirable that the relative dielectric constant is high.
The passivation film 215 can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film by a CVD method, a sputtering method, or the like. In this embodiment mode, a silicon nitride film is used in two layers as the passivation film 215. A silicon nitride film has a high relative dielectric constant and is preferable as a passivation film. At this time, the upper silicon nitride film has a thin and dense structure, and the lower silicon nitride film has a thick and rough structure. The upper silicon nitride film having a dense structure prevents entry of contaminant impurities. Even if the contaminating impurities pass through the upper silicon nitride film, the thicker lower silicon nitride film prevents the contaminating impurities from reaching the semiconductor element. In this two-layer structure, a lower thick silicon nitride film is formed at a high speed and an upper thin silicon nitride film is formed in a relatively long time, so that the throughput in the mass production process is good. Of course, the structure of the passivation film 215 is not limited to this. A single-layer structure may be employed, or a stacked structure of two or more layers may be formed by freely combining a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a silicon nitride oxide film. Furthermore, it is preferable to form the passivation film 215 using a microwave plasma CVD apparatus having a frequency of 1 GHz. A silicon nitride film, a silicon nitride oxide film, and a silicon oxynitride film formed with a microwave plasma CVD apparatus have high withstand voltage and can increase the reliability of a thin film transistor to be formed later. Further, the silicon nitride film may be formed by a plasma CVD method, or may be subjected to nitriding treatment by high-density and low-temperature plasma treatment using microwaves. Further, a silicon nitride film or a silicon nitride oxide film may be formed when the silane flash treatment is performed in the reaction chamber.
Next, a planarization film 216 is formed on the passivation film 215. The planarization film 216 is formed by applying a photosensitive organic resin material (see FIG. 8B). As the organic resin material, materials such as polyimide, polyester, and polyacryl ester are used. Since these organic resin materials have a relative dielectric constant as low as about 2 to 3 compared to inorganic insulating materials such as silicon nitride, they have the effect of reducing the parasitic capacitance between the conductive films.
Next, in the TFT portion, an opening 217 is formed in the passivation film 215 and the planarization film 216 in order to connect the pixel electrode 219 and the source or drain electrode 213b. On the other hand, in the storage capacitor portion, the opening 218 is formed only in the planarization film 216. At this time, the planarizing film 216 is formed by photolithography, and the passivation film 215 is formed by etching.
Here, a multi-tone mask is used to form the opening 217 of the TFT portion and the opening 218 of the auxiliary capacitor portion with the same mask. A multi-tone mask is arranged so that the light transmitting portion is on the portion where the opening 217 is formed and the light semi-transmitting portion is on the portion where the opening 218 is formed. The planarizing film 216 made of the organic resin material is opened, and the opening 220 and the recess 221 having a concave cross-sectional shape are formed. (See FIG. 8C). Here, the photosensitive organic resin material is a positive type in which the photosensitive portion is dissolved and removed by development.
Since the planarizing film 216 corresponding to the source electrode or drain electrode 213b of the TFT portion corresponds to the light transmission portion of the multi-tone mask, the planarizing film 216 is irradiated with strong ultraviolet light as it is. For this reason, ultraviolet rays are irradiated to the bottom of the planarizing film 216, and the photosensitive agent contained in the organic resin material changes from dissolution prevention to acceleration. On the other hand, since the planarizing film 216 corresponding to the auxiliary capacitance line 214 of the auxiliary capacitance portion corresponds to the light semi-transmissive portion of the multi-tone mask, the intensity of ultraviolet rays is attenuated. Therefore, since ultraviolet rays do not reach the bottom of the organic resin material, the photosensitive agent does not change at the bottom of the organic resin material. Further, since the planarizing film 216 other than the above corresponds to the light shielding portion of the multi-tone mask, the photosensitive agent contained in the organic resin material does not change.
Thereafter, development is performed to remove the portion containing the photosensitizer that has obtained a high solubility ratio by ultraviolet irradiation with the organic alkali solution. As a result, the planarization film 216 is completely removed in the opening 220 to expose the passivation film 215, and the planarization film 216 having a certain thickness remains on the passivation film 215 in the recess 221.
Next, the passivation film 215 exposed in the opening 220 is removed by etching to form the opening 222. At this time, since the planarization film 216 remains in the recess 221, the passivation film 215 is not removed (see FIG. 9A).
Next, the planarization film 216 remaining in the recess 221 is removed by ashing to form an opening 218. At this time, the planarization film 216 is also removed in the lateral direction by an isotropic ashing process using oxygen gas plasma or the like. For this reason, the opening 222 is also slightly expanded, and an opening 217 having a step shape is formed from the passivation film 215 to the planarization film 216. (See FIG. 9B).
A planarization film 216 obtained by performing photolithography using a multi-tone mask as an exposure mask has a shape having a plurality of thicknesses, and the shape can be further deformed by performing ashing. Therefore, the planarization film 216 can be formed in at least two kinds of different patterns with one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can be reduced, so that the process can be simplified and the cost can be reduced. Therefore, a high-quality display device such as high image quality and high aperture ratio can be produced at low cost.
Finally, a light-transmitting conductive film is formed over the planarization film 216, the opening 217, and the opening 218, and a pattern is formed in the shape of the pixel electrode 219 (see FIG. 9C).
The light-transmitting conductive film includes indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used.
Alternatively, the light-transmitting conductive film can be formed using a conductive composition including a conductive high molecule (also referred to as a conductive polymer). The translucent conductive film formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / □ or less and a transmissivity of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less.
Through the above-described steps, the channel staggered inverted staggered thin film transistor of this embodiment is formed.
With the configuration of the present embodiment, since only the passivation film can be used as the dielectric film in the auxiliary capacitance section, the thickness of the dielectric film can be reduced. As a result, the area of the auxiliary capacitor portion can be reduced, and the aperture ratio of the pixel portion can be improved accordingly.
In addition, since the pixel electrode is formed on the planarization film and there is no extra electrode between the pixel capacitance portion composed of the pixel electrode and the counter electrode, the electric field applied to the liquid crystal becomes uniform and the image quality is improved.
In addition, by using a planarizing film, the pixel electrode provided in the uppermost layer becomes flat without being affected by the uneven shape of the structure below it, so that the liquid crystal alignment disorder caused by the uneven shape is prevented. It is possible to suppress the ideal liquid crystal alignment. Therefore, high quality image display is possible. Further, since the parasitic capacitance between the pixel electrode and the data signal line, and between the pixel electrode and the scanning signal line can be remarkably reduced by inserting a planarization film, the outer peripheral edge of the pixel electrode, the data signal line, and the scanning signal line And the aperture ratio of the pixel can be improved.
In addition, by using a multi-tone mask in photolithography of a planarization film, a display device can be manufactured without increasing the number of photomasks. Therefore, by reducing the number of photomasks, the photolithography process can be simplified and an increase in manufacturing cost can be suppressed. Therefore, a high-quality display device such as high image quality and high aperture ratio can be produced at low cost.
In the present invention, the display device includes a display element. As the display element, a liquid crystal element (liquid crystal display element) can be preferably used as shown in this embodiment mode. Alternatively, a light-emitting element (EL element) called an electroluminescence (hereinafter referred to as “EL”) in which a layer containing an organic substance, an inorganic substance, or a mixture of an organic substance and an inorganic substance that emits light is interposed between electrodes may be used. Good. In addition, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used. Note that there is an EL display as a display device using an EL element, a liquid crystal display as a display device using a liquid crystal element, a transmissive liquid crystal display, a transflective liquid crystal display, and an electronic paper as a display device using electronic ink. .
The display device includes a panel in which the display element is sealed, and a module in which an IC including a controller is mounted on the panel. Furthermore, the present invention relates to an element substrate corresponding to one mode before the display element is completed in the process of manufacturing the display device, and the element substrate includes a unit for supplying current to the display element. Prepare for. Specifically, the element substrate may be in a state in which only the pixel electrode layer of the display element is formed, or after the conductive film to be the pixel electrode layer is formed and etched to form the pixel electrode layer It may be in the state before forming the film, and all forms are applicable.
Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Also, a connector, for example, a module with a FPC (Flexible Printed Circuit) or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package), a module with a printed wiring board on the end of a TAB tape or TCP, or a display It is assumed that the display device includes all modules in which an IC (integrated circuit) is directly mounted on the element by a COG (Chip On Glass) method.
A thin film transistor 400 which is an inverted staggered thin film transistor having a channel etch structure according to this embodiment is illustrated in FIG.
In FIG. 11, over a substrate 401, a gate electrode 402, a gate insulating film 403, a microcrystalline semiconductor film 404, a buffer layer 405, impurity semiconductor films 406a and 406b to which an impurity element imparting one conductivity type is added, a source electrode, A thin film transistor 400 including drain electrodes 407 a and 407 b is provided, and a passivation film 408 is provided so as to cover the thin film transistor 400.
In this embodiment mode, a microcrystalline semiconductor film 404 is used instead of the semiconductor film made of amorphous silicon in Embodiment Mode 1. Further, a buffer layer 405 is formed between the microcrystalline semiconductor film 404 and the impurity semiconductor films 406a and 406b to which an impurity element imparting one conductivity type is added.
The formation and etching steps of the microcrystalline semiconductor film 404, the buffer layer 405, and the impurity semiconductor films 406a and 406b to which an impurity element imparting one conductivity type is added are performed in a manner similar to that of the semiconductor film 209 in the first embodiment. This is the same as the formation and etching steps of the impurity semiconductor films 210a and 210b to which an impurity element imparting a mold is added.
Since the buffer layer 405 is provided over the microcrystalline semiconductor film 404, damage to the microcrystalline semiconductor film 404 during processing (e.g., film reduction due to radicals or an etchant due to plasma during etching or oxidation) can be prevented. . Accordingly, the reliability of the thin film transistor 400 can be improved.
The microcrystalline semiconductor film 404 may be formed on the surface of the gate insulating film 403 that has been subjected to hydrogen plasma treatment. When the microcrystalline semiconductor film 404 is formed over the gate insulating film 403 on which hydrogen plasma is applied, crystal growth of the microcrystal can be promoted. In addition, lattice distortion at the interface between the gate insulating film 403 and the microcrystalline semiconductor film 404 can be reduced, and the interface characteristics between the gate insulating film 403 and the microcrystalline semiconductor film 404 can be improved. Accordingly, the microcrystalline semiconductor film 404 obtained can have high electrical characteristics and high reliability.
The reaction chamber for forming the gate insulating film 403, the microcrystalline semiconductor film 404, the buffer layer 405, and the impurity semiconductor films 406a and 406b to which an impurity element imparting one conductivity type is added may be used in the same reaction chamber. It may be good or may be carried out in a different reaction chamber for each film type.
Before the reaction chamber is loaded with the substrate, it is cleaned and flushed (hydrogen flush using hydrogen as a flash material, silane flash using silane as a flash material), and the inner walls of each reaction chamber It is preferable to perform coating with a protective film (also referred to as pre-coating treatment). The pre-coating process is a process in which a film forming gas is flowed into the reaction chamber and plasma processing is performed, so that the inside of the reaction chamber is covered with a protective film formed in advance. By the flushing treatment and the precoat treatment, contamination of the film to be formed by impurities such as oxygen, nitrogen, and fluorine in the reaction chamber can be prevented.
Note that the gate insulating film 403, the microcrystalline semiconductor film 404, the buffer layer 405, and the impurity semiconductor films 406a and 406b to which an impurity element imparting one conductivity type is added may be formed successively without exposure to the air. . The gate insulating film 403, the microcrystalline semiconductor film 404, the buffer layer 405, and the impurity semiconductor films 406 a and 406 b to which an impurity element imparting one conductivity type is added without being exposed to the air, so that atmospheric components and Each stacked interface can be formed without being contaminated by a contaminating impurity element floating in the atmosphere. Thus, variation in thin film transistor characteristics can be reduced.
As an example of a three-layer structure of the gate insulating film 403, a silicon nitride film or a silicon nitride oxide film is formed as a first layer over the gate electrode 402, a silicon oxynitride film as a second layer, and a silicon nitride film as a third layer And a microcrystalline semiconductor film may be formed over the uppermost silicon nitride film. In this case, the thickness of the first silicon nitride film or silicon nitride oxide film is preferably larger than 50 nm, and effects such as a barrier that blocks impurities such as sodium, prevention of hillocks in the gate electrode, and prevention of oxidation of the gate electrode Play. The third silicon nitride film has an effect of improving the adhesion of the microcrystalline semiconductor film and preventing oxidation during LP treatment in which laser irradiation is performed on the microcrystalline semiconductor film.
In this manner, by forming a nitride film such as an extremely thin silicon nitride film on the surface of the gate insulating film 403, the adhesion of the microcrystalline semiconductor film 404 can be improved. The nitride film may be formed by a plasma CVD method, or nitridation may be performed by high-density and low-temperature plasma treatment using microwaves. Further, a silicon nitride film or a silicon nitride oxide film may be formed when the silane flash treatment is performed in the reaction chamber.
The microcrystalline semiconductor film 404 exhibits weak n-type conductivity unless an impurity element for the purpose of controlling valence electrons is intentionally added. Therefore, the threshold value is controlled by adding an impurity element imparting p-type conductivity to the microcrystalline semiconductor film 404 functioning as a channel formation region of the thin film transistor 400 at the same time as or after the film formation. It becomes possible. As an impurity element imparting p-type, boron is typically used, and impurity gas such as B 2 H 6 and BF 3 is mixed in silicon hydride at a rate of 1 ppm to 1000 ppm, preferably 1 to 100 ppm. . The boron concentration is preferably 1 × 10 14 to 6 × 10 16 atoms / cm 3 , for example.
The microcrystalline semiconductor film 404 is a film including a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). This semiconductor is a semiconductor having a third state which is stable in terms of free energy, and is a crystalline one having a short-range order and having a lattice distortion. A 20 nm columnar or needle crystal grows in the normal direction to the substrate surface. In addition, a microcrystalline semiconductor and a non-single-crystal semiconductor are mixed. Microcrystalline silicon which is a typical example of a microcrystalline semiconductor has its Raman spectrum shifted to a lower wave number side than 521 cm −1 indicating single crystal silicon. That is, the peak of the Raman spectrum of the microcrystalline silicon exists between 480 cm -1 indicating the 521 cm -1 and the amorphous silicon which represents single crystal silicon. In addition, at least 1 atomic% or more of hydrogen or halogen is contained to terminate dangling bonds (dangling bonds). Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability can be improved and a good microcrystalline semiconductor film can be obtained. A description of such a microcrystalline semiconductor film is disclosed in, for example, US Pat. No. 4,409,134.
The microcrystalline semiconductor film 404 can be formed using a high-frequency plasma CVD apparatus with a frequency of several tens to several hundreds of MHz or a microwave plasma CVD apparatus with a frequency of 1 GHz or more. Typically, a silicon gas (silicon hydride gas, silicon halide gas) such as SiH 4 , Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , or SiF 4 is diluted with hydrogen. Can do. In addition to the silicon gas and hydrogen, the microcrystalline semiconductor film can be formed by dilution with one or more kinds of rare gas elements selected from helium, argon, krypton, and neon. The flow rate ratio of hydrogen to silicon hydride is 5 to 200 times, preferably 50 to 150 times, and more preferably 100 times.
The oxygen concentration of the microcrystalline semiconductor film 404 is 5 × 10 19 atoms / cm 3 or less, 1 × 10 19 atoms / cm 3 or less, and the nitrogen and carbon concentrations are 1 × 10 18 atoms / cm 3 or less. It is preferable. By reducing the concentration of oxygen, nitrogen, and carbon mixed in the microcrystalline semiconductor film, the conductivity type of the microcrystalline semiconductor film 404 can be prevented from becoming n-type.
The microcrystalline semiconductor film 404 is formed with a thickness greater than 0 nm and less than or equal to 50 nm, preferably greater than 0 nm and less than or equal to 20 nm.
The microcrystalline semiconductor film 404 functions as a channel formation region of a thin film transistor 400 to be formed later. By setting the thickness of the microcrystalline semiconductor film 404 within the above range, a thin film transistor 400 to be formed later is a fully depleted type. In addition, since the microcrystalline semiconductor film is formed using microcrystals, the resistance is lower than that of the amorphous semiconductor film. Therefore, a thin film transistor using a microcrystalline semiconductor film has a steep slope at a rising portion of a curve indicating current-voltage characteristics, has excellent response as a switching element, and can operate at high speed. In addition, when the microcrystalline semiconductor film 404 is used for a channel formation region of the thin film transistor 400, variation in threshold voltage of the thin film transistor 400 can be suppressed. Therefore, a display device with little variation in electrical characteristics can be manufactured.
In addition, the microcrystalline semiconductor film has higher mobility than the amorphous semiconductor film. Therefore, the area of the channel formation region, that is, the area of the thin film transistor 400 can be reduced by using the thin film transistor 400 whose channel formation region is formed using the microcrystalline semiconductor film 404 for switching the display element. Thus, the area of the thin film transistor 400 shown per pixel is reduced, and the aperture ratio of the pixel can be increased. As a result, a device with high resolution can be manufactured.
The buffer layer 405 that is an amorphous semiconductor film uses silicon gas (silicon hydride gas, silicon halide gas) such as SiH 4 , Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , SiF 4, or the like. Then, it can be formed by a plasma CVD method. Further, the buffer layer 405 that is an amorphous semiconductor film can be formed by diluting the silicon gas with one or more kinds of rare gas elements selected from helium, argon, krypton, and neon. A buffer which is an amorphous semiconductor film containing hydrogen using hydrogen having a flow rate of 1 to 20 times, preferably 1 to 10 times, more preferably 1 to 5 times the flow rate of silicon hydride. Layer 405 can be formed. In addition, by using the silicon gas and nitrogen or ammonia, the buffer layer 405 that is an amorphous semiconductor film containing nitrogen can be formed. Further, by using the above silicon gas and a gas containing fluorine, chlorine, bromine or iodine (F 2 , Cl 2 , Br 2 , I 2 , HF, HCl, HBr, HI, etc.), fluorine, chlorine, bromine Alternatively, the buffer layer 405 that is an amorphous semiconductor film containing iodine can be formed.
The buffer layer 405 can be formed as an amorphous semiconductor film by sputtering with hydrogen or a rare gas using an amorphous semiconductor as a target. At this time, by including ammonia, nitrogen, or N 2 O in the atmosphere, the buffer layer 405 that is an amorphous semiconductor film containing nitrogen can be formed. In addition, by containing a gas containing fluorine, chlorine, bromine, or iodine (F 2 , Cl 2 , Br 2 , I 2 , HF, HCl, HBr, HI, etc.) in the atmosphere, fluorine, chlorine, bromine, Alternatively, the buffer layer 405 that is an amorphous semiconductor film containing iodine can be formed.
As the buffer layer 405, an amorphous semiconductor film is formed over the surface of the microcrystalline semiconductor film by a plasma CVD method or a sputtering method, and then the surface of the amorphous semiconductor film is subjected to hydrogen plasma, nitrogen plasma, halogen plasma, The surface of the amorphous semiconductor film may be hydrogenated, nitrogenated, or halogenated by treatment with plasma using a gas (helium, argon, krypton, or neon).
The buffer layer 405 is preferably formed using an amorphous semiconductor film. Therefore, in the case where the film is formed by a high-frequency plasma CVD method or a microwave plasma CVD method with a frequency of several tens to several hundreds of MHz, it is preferable to control the film formation conditions so as to form an amorphous semiconductor film.
The buffer layer 405 is typically preferably formed with a thickness greater than or equal to 10 nm and less than or equal to 50 nm. In addition, the total concentration of nitrogen, carbon, and oxygen contained in the buffer layer is preferably 1 × 10 20 atoms / cm 3 to 15 × 10 20 atoms / cm 3 . With the above concentration, the buffer layer can function as a high resistance region even when the film thickness is 10 nm or more and 50 nm or less.
The buffer layer 405 may have a thickness of 150 nm to 200 nm, and the concentrations of carbon, nitrogen, and oxygen contained may be 3 × 10 19 atoms / cm 3 or less, preferably 5 × 10 18 atoms / cm 3 or less. Good.
By forming an amorphous semiconductor film or an amorphous semiconductor film containing hydrogen, nitrogen, or halogen as the buffer layer 405 over the surface of the microcrystalline semiconductor film 404, crystal grains included in the microcrystalline semiconductor film 404 can be obtained. It is possible to prevent natural oxidation of the surface. By forming the buffer layer 405 over the surface of the microcrystalline semiconductor film 404, oxidation of the microcrystalline grains can be prevented. The buffer layer 405 has an effect of preventing oxygen from entering the microcrystalline semiconductor film 404 because hydrogen and / or fluorine are mixed therein.
Further, since the buffer layer 405 is formed using an amorphous semiconductor film or an amorphous semiconductor film containing hydrogen, nitrogen, or halogen, the microcrystalline semiconductor film 404 functioning as a channel formation region is used. Also has high resistance. Therefore, in the thin film transistor 400 formed later, the buffer layer formed between the source and drain electrodes and the microcrystalline semiconductor film functions as a high-resistance region. Therefore, off current of the thin film transistor can be reduced. When the thin film transistor is used as a switching element of a display device, the contrast of the display device can be improved.
The end portion of the microcrystalline semiconductor film 404, the buffer layer 405, and the impurity semiconductor films 406a and 406b to which an impurity element imparting one conductivity type is added is etched into a tapered shape, whereby an impurity imparting one conductivity type The impurity semiconductor films 406a and 406b to which the element is added can be prevented from being in direct contact with the microcrystalline semiconductor film 404. The taper angle of the end is 30 ° to 90 °, preferably 45 ° to 80 °. Accordingly, the distance between the impurity semiconductor films 406a and 406b to which the impurity element imparting one conductivity type is added and the microcrystalline semiconductor film 404 is increased, so that leakage current can be prevented. In addition, disconnection of the wiring due to the step shape can be prevented.
The buffer layer 405 is formed at the same time because the buffer layer under the impurity semiconductor films 406a and 406b to which the impurity element imparting one conductivity type is added and the buffer layer in the channel formation region of the microcrystalline semiconductor film 404 are formed of the same material. It is a continuous film. The buffer layer over the microcrystalline semiconductor film 404 blocks external air and etching residues by hydrogen contained therein, thereby protecting the microcrystalline semiconductor film 404.
By providing the buffer layer 405 that does not contain an impurity imparting one conductivity type, an impurity imparting one conductivity type and a microcrystalline semiconductor included in the impurity semiconductor films 406a and 406b to which the impurity element imparting one conductivity type is added. Impurities imparting one conductivity type for controlling the threshold voltage of the film 404 can be prevented from being mixed with each other. If an impurity imparting one conductivity type is mixed, a recombination center is formed, a leak current flows, and the effect of reducing off-current cannot be obtained.
By providing the buffer layer 405 as described above, a high-breakdown-voltage thin film transistor with reduced leakage current can be manufactured. Therefore, even in the case of a thin film transistor used for a liquid crystal display device to which a voltage of 15 V is applied, it can be used preferably with high reliability.
By forming a channel formation region using a microcrystalline semiconductor film, a field-effect mobility of 1 to 20 cm 2 / V · sec can be obtained. Therefore, this thin film transistor can be used as an element for switching a pixel in the pixel portion and an element for forming a driving circuit on the scanning line (gate line) side.
According to this embodiment, a highly reliable display device including a pixel with a high aperture ratio can be manufactured. Further, by reducing the number of exposure masks, the photolithography process can be simplified, and a reliable display device can be manufactured at low cost with high productivity.
In this embodiment, an example of a manufacturing process in which the microcrystalline semiconductor film is irradiated with laser light in Embodiment 2 will be described.
When a microcrystalline semiconductor film is formed over the gate insulating film by a plasma CVD method or the like, an amorphous component is included more than a crystalline component in the vicinity of the interface between the gate insulating film and the semiconductor film containing a crystal. A region (referred to herein as an interface region) may be formed. In addition, when an ultra-thin microcrystalline semiconductor film having a thickness of about 10 nm or less is formed by plasma CVD or the like, a semiconductor film including microcrystalline grains can be formed, but the quality is uniformly uniform over the entire film. It is difficult to obtain a semiconductor film containing microcrystalline grains. In these cases, the following laser treatment for irradiating with laser light is effective.
First, a gate electrode is formed over a light-transmitting substrate, and a gate insulating film is formed so as to cover the gate electrode. Then, a microcrystalline silicon (SAS) film is deposited as a microcrystalline semiconductor film over the gate insulating film. The thickness of the microcrystalline semiconductor film may be greater than or equal to 1 nm and less than 15 nm, more preferably greater than or equal to 2 nm and less than or equal to 10 nm. In particular, when the film thickness is 5 nm (4 to 8 nm), the absorptance is high with respect to laser light, and thus productivity is improved.
Next, laser light is irradiated from the surface side of the microcrystalline silicon film. The laser light is irradiated at an energy density that does not melt the microcrystalline silicon film. That is, laser processing (laser process, hereinafter also referred to as “LP”) according to the present embodiment is based on solid-phase crystal growth performed without melting the microcrystalline silicon film by radiant heating. That is, a critical region where the deposited microcrystalline silicon film does not become a liquid phase is used. In this sense, it can also be referred to as “critical growth”.
As in this embodiment mode, a crystalline silicon film obtained by directly applying a laser beam to a microcrystalline silicon film after film formation is a conventional microcrystalline silicon film that has been deposited. The growth mechanism and film quality are clearly different from the modified microcrystalline silicon film. In this specification, a crystalline semiconductor film obtained by performing LP treatment on a microcrystalline semiconductor film after deposition is referred to as an LPSAS film.
After forming a microcrystalline semiconductor film such as an LPSAS film, an amorphous silicon (a-Si: H) film is formed at a temperature of 300 ° C. to 400 ° C. as a buffer layer by a plasma CVD method. By this film forming process, hydrogen is supplied to the LPSAS film, and the same effect as that obtained by hydrogenating the LPSAS film can be obtained. That is, by depositing an amorphous silicon film on the LPSAS film, hydrogen can be diffused into the LPSAS film to terminate dangling bonds.
In the subsequent steps, a display device having a thin film transistor is manufactured as in Embodiment Mode 1.
Further, this embodiment mode can be combined with Embodiment Mode 2 as appropriate.
Next, a structure of a display panel which is an embodiment of the disclosed display device is described below. The display device of this embodiment shows an example of a liquid crystal display panel which is an embodiment of a liquid crystal display device including a liquid crystal display element.
FIG. 12 illustrates a mode of a display panel in which only the signal line driver circuit 613 is separately formed and connected to the pixel portion 612 formed over the substrate 611. In this embodiment, the pixel portion 612 and the scan line driver circuit 614 are formed using thin film transistors using an amorphous semiconductor film, a microcrystalline semiconductor film, or a polycrystalline semiconductor film. By forming the signal line driver circuit with a transistor that can obtain higher mobility than a thin film transistor using a microcrystalline semiconductor film, the operation of the signal line driver circuit that requires a higher driving frequency than the scanning line driver circuit is stabilized. be able to. Note that the signal line driver circuit 613 may be a transistor using a single crystal semiconductor, a thin film transistor using a polycrystalline semiconductor, or a transistor using SOI. The pixel portion 612, the signal line driver circuit 613, and the scan line driver circuit 614 are supplied with a potential of a power source, various signals, and the like through the FPC 615, respectively.
In the case where a driver circuit is separately formed, the substrate on which the driver circuit is formed is not necessarily bonded to the substrate on which the pixel portion is formed, and may be bonded to, for example, an FPC. FIG. 12B shows a mode of a display panel in which only the signal line driver circuit 623 is separately formed and connected to the pixel portion 622 and the scan line driver circuit 624 formed over the substrate 621. In this embodiment, the pixel portion 622 and the scan line driver circuit 624 are formed using thin film transistors using an amorphous semiconductor film, a microcrystalline semiconductor film, or a polycrystalline semiconductor film. The signal line driver circuit 623 is connected to the pixel portion 622 through the FPC 625. The pixel portion 622, the signal line driver circuit 623, and the scan line driver circuit 624 are supplied with a potential of a power source, various signals, and the like through the FPC 625, respectively.
Further, only part of the signal line driver circuit or part of the scan line driver circuit is formed over the same substrate as the pixel portion with a thin film transistor using an amorphous semiconductor film, a microcrystalline semiconductor film, or a polycrystalline semiconductor film. It may be formed, and the rest may be separately formed and electrically connected to the pixel portion. In FIG. 12C, an analog switch 633a included in the signal line driver circuit is formed over the same substrate 631 as the pixel portion 632 and the scan line driver circuit 634, and a shift register 633b included in the signal line driver circuit is provided over a different substrate. The form of the display panel formed and bonded is shown. In this embodiment, the pixel portion 632 and the scan line driver circuit 634 are formed using thin film transistors using an amorphous semiconductor film, a microcrystalline semiconductor film, or a polycrystalline semiconductor film. A shift register 633 b included in the signal line driver circuit is connected to the pixel portion 632 through the FPC 635. A potential of a power source, various signals, and the like are supplied to the pixel portion 632, the signal line driver circuit, and the scan line driver circuit 634 through the FPC 635, respectively.
As shown in FIG. 12, in the display device of this embodiment, part or all of the driver circuit is formed using an amorphous semiconductor film, a microcrystalline semiconductor film, or a polycrystalline semiconductor film over the same substrate as the pixel portion. It can be formed using the thin film transistor used.
Note that a method for connecting a separately formed substrate is not particularly limited, and a known COG method, wire bonding method, TAB method, or the like can be used. Further, the connection position is not limited to the position illustrated in FIG. 12 as long as electrical connection is possible. In addition, a controller, a CPU, a memory, and the like may be separately formed and connected.
Next, the appearance and cross section of a display panel, which is one embodiment of the display device of the disclosed invention, will be described with reference to FIGS. FIG. 13A is a top view of a panel in which a thin film transistor 710 and a liquid crystal element 713 formed over a first substrate 701 are sealed with a sealant 705 between the second substrate 706 and FIG. 13B corresponds to a cross-sectional view taken along line MN in FIG.
A sealant 705 is provided so as to surround the pixel portion 702 provided over the first substrate 701 and the scan line driver circuit 704. In addition, a second substrate 706 is provided over the pixel portion 702 and the scan line driver circuit 704. Therefore, the pixel portion 702 and the scan line driver circuit 704 are sealed together with the liquid crystal 708 by the first substrate 701, the sealant 705, and the second substrate 706. A signal line driver circuit 703 formed of a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealant 705 on the first substrate 701. Note that in this embodiment, an example in which a signal line driver circuit including a thin film transistor using a polycrystalline semiconductor film is attached to the first substrate 701 is described; however, the signal line driver circuit is a transistor using a single crystal semiconductor. It may be formed and bonded. FIG. 13 illustrates a thin film transistor 709 formed of a polycrystalline semiconductor film, which is included in the signal line driver circuit 703.
The pixel portion 702 and the scan line driver circuit 704 provided over the first substrate 701 each include a plurality of thin film transistors. FIG. 13B illustrates the thin film transistor 710 included in the pixel portion 702 as an example. Yes. The thin film transistor 710 corresponds to the thin film transistor described in Embodiment 1 and can be similarly manufactured through the steps described in Embodiment 1.
The liquid crystal element 713 and the thin film transistor 710 are electrically connected to each other through a light-transmitting conductive layer 730 that functions as a pixel electrode layer. A counter electrode 731 of the liquid crystal element 713 is formed over the second substrate 706. A portion where the light-transmitting conductive layer 730, the counter electrode 731, and the liquid crystal 708 overlap corresponds to the liquid crystal element 713.
Note that glass, ceramic, or plastic can be used for the first substrate 701 and the second substrate 706. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. In the case of a transmissive liquid crystal display device, the first substrate and the second substrate need to have translucency. In the case of a transflective type, a portion corresponding to the reflective region is made of a reflective material. Also good.
The spacer 735 is a spherical spacer and is provided to control the distance (cell gap) between the translucent conductive layer 730 and the counter electrode 731. Note that a spacer obtained by selectively etching the insulating film may be used.
In addition, a variety of signals and potentials are supplied to the signal line driver circuit 703 and the scan line driver circuit 704 or the pixel portion 702 which are separately formed from the FPC 718 through wirings 714 and 715.
In this embodiment, the connection terminal 716 is formed using the same conductive film as the light-transmitting conductive layer 730 included in the liquid crystal element 713.
The connection terminal 716 is electrically connected to a terminal included in the FPC 718 through an anisotropic conductive film 719.
Although not illustrated, the liquid crystal display device described in this embodiment also includes an alignment film on the second substrate 706 side, and polarizing plates on the first substrate 701 and the second substrate 706 side. doing. Further, a color filter or a shielding film may be provided.
FIG. 13 illustrates an example in which the signal line driver circuit 703 is separately formed and mounted on the first substrate 701; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.
According to this embodiment, a highly reliable display panel including a pixel with a high aperture ratio can be manufactured. Further, by reducing the number of exposure masks, the photolithography process can be simplified, and a reliable display panel can be manufactured at low cost with high productivity.
The display device obtained by the present invention can be used for a display module. That is, the present invention can be implemented in all electronic devices in which they are incorporated in the display portion.
FIG. 14A illustrates a television device. As shown in FIG. 14A, the display module can be incorporated into a housing to complete the television device. A display panel attached to the FPC is also called a display module. A main screen 803 is formed by the display module, and a speaker portion 809, operation switches, and the like are provided as other accessory equipment. In this manner, a television device can be completed.
As shown in FIG. 14A, a display panel 802 using a display element is incorporated in a housing 801. By receiving a general television broadcast by a receiver 805 and connecting to a wired or wireless communication network via a modem 804, the receiver 805 can be connected in one direction (sender to receiver) or bidirectional (between a sender and a receiver, or It is also possible to perform information communication between recipients). The television apparatus can be operated by a switch incorporated in the housing or a separate remote controller 806, and a display unit 807 for displaying information to be output is also provided on the remote controller 806. May be. By applying the display device described in any of the above embodiments to the display panel 802, reliability can be improved by reducing wiring delay, an aperture ratio can be improved by thinning the storage capacitor portion, and image quality can be improved by flattening the pixel electrode. Improvements such as simplification of the photolithography process and reduction of manufacturing costs due to reduction in the number of photomasks can be obtained. Due to the above effects, the display device of the above embodiment is suitable for a large panel for a liquid crystal television among the display panels. In particular, when high resolution is required, the aperture ratio can be increased by the method described in the above embodiment.
In addition, the television device may have a configuration in which the sub screen 808 is formed with the second display panel in addition to the main screen 803 to display the channel, the volume, and the like.
FIG. 15 is a block diagram illustrating a main configuration of the television device. A pixel portion 901 is formed on the display panel. The signal line driver circuit 902 and the scan line driver circuit 903 may be mounted on the display panel by a COG method.
As other external circuit configurations, on the input side of the video signal, among the signals received by the tuner 904, the video signal amplification circuit 905 that amplifies the video signal and the signal output from the signal are red, green, and blue colors And a control circuit 907 for converting the video signal into an input specification of the driver IC. The control circuit 907 outputs a signal to each of the scanning line side and the signal line side. In the case of digital driving, a signal dividing circuit 908 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.
FIG. 14B illustrates an example of a mobile phone 811. The cellular phone 811 includes a display unit 812, an operation unit 813, and the like. By applying the display device described in any of the above embodiments to the display portion 812, the aperture ratio and reliability of the display device can be improved, and mass productivity can be increased at low cost.
A portable computer shown in FIG. 14C includes a main body 821, a display portion 822, and the like. By applying the display device described in any of the above embodiments to the display portion 822, the aperture ratio and reliability of the display device can be improved, and mass productivity can be increased at low cost.
A slot machine which is an example of the gaming machine illustrated in FIG. 14D includes a main body 831, a display portion 832, and the like. By applying the display device described in the above embodiment to the display portion 832, the aperture ratio and reliability of the display device can be improved, and mass productivity can be increased at low cost.
100 Translucent substrate 100
101 scanning signal line 102 data signal line 103 auxiliary capacitance line 104 gate electrode 105 semiconductor film 106a drain electrode 107 opening 108 opening 109 opening 110 pixel electrode 111 gate insulating film 112a An impurity element imparting one conductivity type is added Impurity semiconductor film 113 Passivation film 114 Planarization film 115 Opening 200 Translucent substrate 201 Data signal line 202 Gate electrode 203 Gate insulating film 204 Semiconductor film 205 Impurity semiconductor film 206a to which an impurity element imparting one conductivity type is added Mask Layer 207 Opening 208 Mask layer 209 Semiconductor film 210 Impurity semiconductor film 210a doped with an impurity element imparting one conductivity type Impurity semiconductor film 211 doped with an impurity element imparting one conductivity type Second conductive film 212a Mask Layer 213a Dre Emission electrode 213b drain electrode 214 auxiliary capacitance line 215 a passivation film 216 planarization layer 217 opening 218 opening 219 pixel electrode 220 opening 221 recessed portion 222 opening
A gate electrode formed of a first conductive film provided over a light-transmitting substrate;
A data signal line formed of the first conductive film and extending in one direction;
A first insulating film provided on the first conductive film;
A semiconductor film provided on the first insulating film;
A source electrode and a drain electrode formed by a second conductive film provided on the first insulating film and the semiconductor film;
A scanning signal line formed of the second conductive film and extending in a direction crossing the one direction;
An auxiliary capacitance line formed of the second conductive film and extending in a direction crossing the one direction;
A second insulating film provided on the second conductive film;
A third insulating film provided on the second insulating film;
A pixel electrode provided on the third insulating film and having an outer peripheral end portion overlapping the data signal line, the scanning signal line, or the auxiliary capacitance line;
One of the source electrode and the drain electrode is electrically connected to the semiconductor film and the data signal line,
The other of the source electrode and the drain electrode is electrically connected to the semiconductor film and the pixel electrode,
The gate electrode is electrically connected to the scanning signal line;
The storage capacitor line, the second insulating film as a dielectric display device, and forming the pixel electrode and the capacitor.
A display device, wherein the cross-sectional shape of the semiconductor film is concave.
The concave semiconductor film has a first convex portion and a second convex portion, and an impurity element imparting one conductivity type is added to each of the first convex portion and the second convex portion . A first impurity semiconductor film and a second impurity semiconductor film are provided;
One of the source electrode and the drain electrode is electrically connected to the first impurity semiconductor film, the semiconductor film, and the data signal line,
The other of the source electrode and the drain electrode is electrically connected to the second impurity semiconductor film, the semiconductor film, and the pixel electrode.
A microcrystalline semiconductor film provided over the first insulating film;
A buffer layer having a concave cross-sectional shape provided on the microcrystalline semiconductor film;
The concave buffer layer has a first convex portion and a second convex portion, and an impurity element imparting one conductivity type provided on each of the first convex portion and the second convex portion is added. A first impurity semiconductor film and a second impurity semiconductor film,
A source electrode and a drain electrode formed by a second conductive film provided on the first insulating film, the first impurity semiconductor film, and the second impurity semiconductor film;
A scanning signal line formed by the second conductive film and extending in a direction crossing the one direction, and an auxiliary formed by the second conductive film and extending in a direction crossing the one direction Capacity lines,
One of the source electrode and the drain electrode is electrically connected to the first impurity semiconductor film and the data signal line,
The other of the source electrode and the drain electrode is electrically connected to the second impurity semiconductor film and the pixel electrode,
The display device, wherein the storage capacitor line forms a capacitor with the pixel electrode by using the second insulating film as a dielectric.
The display device, wherein the third insulating film is made of a photosensitive organic resin material.
The display device according to claim 1, wherein the data signal line and the auxiliary capacitance line intersect with each other via the first insulating film.
An electronic apparatus comprising the display device according to any one of claims 1 to 6 in a display portion.
Forming a gate electrode and a data signal line made of a first conductive film on a translucent substrate;
A first insulating film and a semiconductor film are sequentially stacked on the gate electrode and the data signal line;
Etching the semiconductor film to form a second semiconductor film above the gate electrode;
Etching the first insulating film to form a first opening reaching the gate electrode and a second opening reaching the data signal line;
Forming a second conductive film on the first insulating film and the second semiconductor film;
Etching the second conductive film to form a source electrode and a drain electrode, a scanning signal line, and an auxiliary capacitance line;
The scanning signal line is connected through the first opening in the gate electrode and electrically, the source electrode and one of the drain electrode to the data signal line electrically through the second opening connect,
Forming a second insulating film on the first insulating film, the second semiconductor film, the source electrode, the drain electrode, the scanning signal line, and the auxiliary capacitance line;
Etching the second insulating film and the third insulating film to form a third opening reaching the drain electrode;
Etching the third insulating film to form a fourth opening exposing the second insulating film formed above the auxiliary capacitance line;
Forming a pixel electrode on the third insulating film;
The pixel electrode is electrically connected to the drain electrode through the third opening, and forms a capacitance with the auxiliary capacitance line using the second insulating film as a dielectric in the fourth opening. the method for manufacturing a display device comprising a Turkey.
A first insulating film, a semiconductor film, and an impurity semiconductor film to which an impurity element imparting one conductivity type is added are sequentially stacked over the gate electrode and the data signal line;
A first mask layer is formed on the impurity semiconductor film by photolithography using a multi-tone mask, and the first insulating film, the semiconductor film, and the impurity semiconductor are formed using the first mask layer. Etching the film to form a first opening reaching the gate electrode and a second opening reaching the data signal line;
Ashing the first mask layer to form a second mask layer;
Etching the semiconductor film and the impurity semiconductor film using the second mask layer to form a second semiconductor film and a second impurity semiconductor film;
Forming a second conductive film on the first insulating film and the second impurity semiconductor film;
Forming a third mask layer on the second conductive film;
Using the third mask layer, the second conductive film and the second impurity semiconductor film are etched to form a source electrode, a drain electrode, a scanning signal line, an auxiliary capacitance line, a third impurity semiconductor film, Forming a fourth impurity semiconductor film;
The second insulating film, the second semiconductor film, the third impurity semiconductor film, the fourth impurity semiconductor film, the source electrode, the drain electrode, the scanning signal line, and the auxiliary capacitance line are secondly formed. An insulating film of
By photolithography using a multi-tone mask, a third opening for exposing the second insulating film to the third insulating film, and a concave portion in which the third insulating film remains with a concave cross-sectional shape. Forming,
Etching the second insulating film in the third opening to form a fourth opening reaching the drain electrode;
Ashing the third insulating film in the recess to form a fifth opening exposing the second insulating film formed above the storage capacitor line;
The pixel electrode is connected through the fourth opening in said drain electrode and electrically, and to configure the storage capacitance line and the capacitance of the second insulating film as a dielectric in the fifth opening the method for manufacturing a display device comprising a Turkey.
JP2009073264A 2008-03-31 2009-03-25 Display device and manufacturing method thereof Active JP5182993B2 (en)
JP2009073264A JP5182993B2 (en) 2008-03-31 2009-03-25 Display device and manufacturing method thereof
JP2009265635A JP2009265635A (en) 2009-11-12
JP2009265635A5 JP2009265635A5 (en) 2012-02-23
JP5182993B2 true JP5182993B2 (en) 2013-04-17
JP2009073264A Active JP5182993B2 (en) 2008-03-31 2009-03-25 Display device and manufacturing method thereof
JP2013004150A Active JP5285817B2 (en) 2008-03-31 2013-01-14 Display device
JP2013115121A Active JP5685288B2 (en) 2008-03-31 2013-05-31 Display device
JP2015006406A Active JP5917728B2 (en) 2008-03-31 2015-01-16 Display device
TW (1) TWI499848B (en)
TWI654762B (en) * 2011-05-05 2019-03-21 日商半導體能源研究所股份有限公司 Semiconductor device and manufacturing method
CN104508549B (en) * 2012-08-03 2018-02-06 株式会社半导体能源研究所 Semiconductor device
TWI636510B (en) * 2017-12-05 2018-09-21 友達光電股份有限公司 Thin film transistor substrate and manufacturing method thereof
JPH0451140A (en) * 1990-06-19 1992-02-19 Konica Corp Silver halide photographic sensitive material having good pressure fogging characteristic
JP2780681B2 (en) * 1995-08-11 1998-07-30 日本電気株式会社 The active matrix liquid crystal display panel and manufacturing method thereof
JP4869504B2 (en) * 2000-06-27 2012-02-08 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
KR20020002089A (en) 2000-06-29 2002-01-09 주식회사 현대 디스플레이 테크놀로지 Method of manufacturing lcd with high aperture ratio
JP4112168B2 (en) * 2000-12-11 2008-07-02 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
JP4577114B2 (en) * 2005-06-23 2010-11-10 ソニー株式会社 Thin film transistor manufacturing method and display device manufacturing method
CN100474087C (en) * 2006-02-09 2009-04-01 胜华科技股份有限公司 Pixel structure of thin film transistor liquid crystal display
WO2008029582A1 (en) * 2006-09-08 2008-03-13 Sharp Kabushiki Kaisha Semiconductor device, method for manufacturing the semiconductor device, and display device
CN100576045C (en) * 2007-08-31 2009-12-30 友达光电股份有限公司 Liquid crystal display and its manufacture method
2009-03-25 JP JP2009073264A patent/JP5182993B2/en active Active
2009-03-30 CN CN 200910128358 patent/CN101551559B/en active IP Right Grant
2009-03-30 US US12/413,717 patent/US8138500B2/en active Active
2009-03-30 TW TW098110498A patent/TWI499848B/en active
2009-03-30 CN CN201210216767.9A patent/CN102707529B/en active IP Right Grant
2012-03-19 US US13/423,874 patent/US8519398B2/en active Active
2013-01-14 JP JP2013004150A patent/JP5285817B2/en active Active
2013-05-31 JP JP2013115121A patent/JP5685288B2/en active Active
2015-01-16 JP JP2015006406A patent/JP5917728B2/en active Active
JP2009265635A (en) 2009-11-12
JP5917728B2 (en) 2016-05-18
US20120176576A1 (en) 2012-07-12
TWI499848B (en) 2015-09-11
JP5285817B2 (en) 2013-09-11
CN101551559B (en) 2013-01-09
CN102707529B (en) 2015-05-20
CN102707529A (en) 2012-10-03
TW201003267A (en) 2010-01-16
JP2013127626A (en) 2013-06-27
CN101551559A (en) 2009-10-07
JP2015111278A (en) 2015-06-18
JP5685288B2 (en) 2015-03-18
US8138500B2 (en) 2012-03-20
US8519398B2 (en) 2013-08-27
JP2013190820A (en) 2013-09-26
US20090242888A1 (en) 2009-10-01
CN101872097B (en) 2013-11-13 The liquid crystal display device
JP5331389B2 (en) 2013-10-30 Method for manufacturing display device
US8013338B2 (en) 2011-09-06 Display device and electronic device having the display device, and method for manufacturing thereof
JP5503857B2 (en) 2014-05-28 Method for manufacturing thin film transistor
TWI605509B (en) 2017-11-11 Methods for manufacturing thin film transistor and display device
JP2009055008A (en) 2009-03-12 Liquid crystal display device and electronic device
TWI479566B (en) 2015-04-01 Method for manufacturing semiconductor device