Source: http://www.google.com/patents/US20060170412?dq=6,272,646
Timestamp: 2015-08-04 11:15:50
Document Index: 595028620

Matched Legal Cases: ['art 50', 'art 21', 'arts 22', 'art 22', 'art 101', 'art 101', 'art 21']

Patent US20060170412 - Sokcet assembly for testing semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe present invention relates to a socket assembly for testing semiconductor device comprising a socket board electrically connected to an outside testing device wherein a plurality of connection pins connected to leads of a semiconductor is provided; a socket guide mounted to cover the socket board,...http://www.google.com/patents/US20060170412?utm_source=gb-gplus-sharePatent US20060170412 - Sokcet assembly for testing semiconductor deviceAdvanced Patent SearchPublication numberUS20060170412 A1Publication typeApplicationApplication numberUS 11/196,238Publication dateAug 3, 2006Filing dateAug 4, 2005Priority dateJan 28, 2005Also published asCN1812069A, DE102005037024A1, US7429868Publication number11196238, 196238, US 2006/0170412 A1, US 2006/170412 A1, US 20060170412 A1, US 20060170412A1, US 2006170412 A1, US 2006170412A1, US-A1-20060170412, US-A1-2006170412, US2006/0170412A1, US2006/170412A1, US20060170412 A1, US20060170412A1, US2006170412 A1, US2006170412A1InventorsChan Park, Chul Ham, Young Park, Ho Song, Woo Lim, Jae SeoOriginal AssigneeMirae CorporationExport CitationBiBTeX, EndNote, RefManReferenced by (1), Classifications (5), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSokcet assembly for testing semiconductor device
US 20060170412 A1Abstract
The present invention relates to a socket assembly for testing semiconductor device comprising a socket board electrically connected to an outside testing device wherein a plurality of connection pins connected to leads of a semiconductor is provided; a socket guide mounted to cover the socket board, with an open part formed so that the semiconductor may in/out, thereby connecting the semiconductor to the connection pins of the socket board; and a spacer interposed between the socket board and the socket guide for maintaining a predetermined distance between the semiconductor and the socket board by touching an surface of the semiconductor having moved into an inside of the socket guide before a surface of each carrier touches the socket guide. According to the present invention, the balls or the leads of each semiconductor may be pressed to the connection pins of the socket in a predetermined depth without replacing the carriers though the semiconductors have the different thicknesses. Images(10) Claims(11)
DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. In description of preferred embodiments, a semiconductor for being tested is a BGA type semiconductor, wherein a plurality of balls is formed on a first surface thereof. However, a socket assembly of the present invention may be similarly applied to various kinds of semiconductors besides a BGA type semiconductor. To help understanding, same reference codes are used in the constitutional elements of a socket assembly of the present invention same as ones of a conventional socket assembly. Referenced to FIGS. 2 through 5, a first embodiment of a socket assembly for testing semiconductor device according to the present invention will be described in the followings. Shown in FIGS. 2 and 3, a socket assembly of the present invention comprises a socket board 10 wherein a plurality of connection pins 11 is formed, a socket guide 20 formed to cover an upper side of the socket board 10, and a spacer 100 contactablely supporting a semiconductor (S) having moved into an inner side space of the socket guide 20 between the socket guide 20 and the socket board 10. Carriers 50 are formed in a test tray (not shown) at a predetermined distance in plural, for example 64 carriers, and each carrier 50 is employed to keep a semiconductor (S) temporarily in a test tray. A seating part 50 a therein a semiconductor (S) seated is formed on a center of a lower surface of each carrier 50, and a pair of latches 51 for securing/detaching the semiconductor (S) and an operation button 52 moving up/down for operating the latches 51 are formed in both sides of each carrier 50. The operation button 52 is elastically supported by a compressed spring (not shown). Each latch 51 of each carrier 50 is rotatablely fastened about a hinge shaft 53. Also, a guide groove 54 is formed in an inclined long circle shape in the center of the latch 51. A guide pin 55 is secured to the carrier 50 in the guide groove 54 Thus, when the operation button 52 is pressed from outside, the operation button 52 moves down against an elasticity of the compressed spring (not shown). Then the latch 51 is rotoated outward and there is space between the latch 51 and the semiconductor (S), thereby detaching the semiconductor (S). On the contrary, when the outside force having pressed the operation button 52 is removed, the operation button 52 returns to its original location by the elasticity of the compressed spring (not sown). Then, the latch 51 is rotated inward by guiding of the guide pin 55, thereby securing the semiconductor (S). An open part 21 is formed in a center of a socket guide 20 of the socket assembly so as that a semiconductor (S) may approach to a socket board 10. Also, guide parts 22 in a cone shape inserted into guide holes 56 are formed projected upward at the two corners of an upper surface of the socket guide 20. When the carrier 50 approaches to the socket guide 20, each guide part 22 is inserted into each guide hole 56 of the carrier 50 and employed to guide the carrier 50 to its accurate location in the socket guide 20. The connection pins 11 of the socket board 10 are electrically connected to a tester of an outside testing device and the number and the pitch of the connection pins 11 are corresponding to those of the balls (B) of the semiconductor (S). The spacer 100 is formed in a center portion in a plate shape, therein an open part 101 is formed so as that the connection pins 11 of the socket board 10 may be passed through together. In both sides of the open part 101 latch escape holes 102 are formed, being passed through so as that the latches 50 of the carrier 50 may be inserted therein. The spacer 100 may be made of various kinds of materials such as metal, however it is preferable but not necessary that the spacer 100 is made of a resin material such as plastic. The spacer 100 touches a surface of a semiconductor (S) just before or at the moment that a lower surface of the carrier 50 touches an upper surface of a socket guide 20 when connecting a semiconductor (S) to connection pins 11. Thus, the spacer 100 is employed as a kind of a hard stopper so that the semiconductor (S) may maintain a predetermined distance with the socket board 10, in other words, so that the balls (B) of the semiconductor (S) may be pressed to the connection pins 11 in a predetermined depth. Therefore, the spacer 100 is formed thick enough that the balls (B) of the semiconductor (S) may be pressed to the connection pins 11 in a predetermined depth at the same time that the spacer 100 may touch a surface of the semiconductor (S). The size of the socket guide 20, the spacer 100 and the carrier 50 may be set up by the size that the spacer 100 is capable of touching the surface of the semiconductor (S) just before or at the moment that the carrier 50 touches the surface of the socket guide 20, on a basis of the thinnest of all semiconductors (S) for being tested. If the size of the socket guide 20, the spacer 100 and the carrier 50 is set up on a basis of the semiconductor which is thick or thicker, testing the thicker semiconductors is performed well. However when testing the thinnest semiconductor, the carrier 50 touches the socket guide 20 before the semiconductor (S) touches the spacer 100, thereby the balls (B) of the semiconductor (S) may not be connected deep enough or not be connected at all. The detailed description of an operation of the socket assembly is the following. FIG. 4 describes a connection state when testing a thinner semiconductor. As shown in FIG. 4, when a separate transportation device moves a test tray (not shown) and lines up carriers 50 in an outer side of a socket assembly, a press unit 60 outside presses each carrier 50 at a predetermined power and then a semiconductor (S) mounted on each carrier 50 moves toward a socket board 10 through a open part 21 of a socket guide 20. In succession, at the moment that balls (B) of the semiconductor (S) are connected to connection pins 11 of the socket board 10, edge portion of the ball forming surface are supported, touching the spacer 100, thereafter the semiconductor (S) maintaining a predetermined distance with the socket board 10. At this time a lower surface of the carrier 50 is closely adjacent to an upper surface of the socket guide 20. As shown in FIG. 5, in case of testing a thicker semiconductor than the semiconductor of FIG. 4, a surface of a semiconductor (S) is supported, touching a spacer 100 when a semiconductor being connected to the connection pins 11, thereby the distance between the semiconductor (S) and the socket board 10 being the same as the distance illustrated in FIG. 4. That is, the semiconductor (S) is pressed to the connection pins 11 in a predetermined depth. However, since the semiconductor (S) is thicker, the gap (g) between the lower surface of the carrier 50 and the socket guide 20 is increased as much as the thickness of the semiconductor (S) increased. According to the present invention, when the semiconductor (S) is connected to the connection pins 11, the semiconductor (S) is supported, touching the spacer 100 first and then the carrier 50 touches the socket guide 20, resulting in the semiconductor (S) maintaining a predetermined distance with the socket board 10. Accordingly, the semiconductors (S) may be connected to the connection pins 11 at a predetermined distance all the time even if the semiconductors have various thicknesses. Also, as shown in FIG. 4, Edges of a semiconductor (S) are pressed and at the same time supported by a spacer 100. Thereby, the semiconductor (S) may be connected in a straight flat state though a bending of a semiconductor (S) occurs. Accordingly, it is possible to press the entire area of the semiconductor (S) uniformly without applying too much force to the semiconductor (S), FIGS. 6 through 8 describe a second embodiment of the present invention. A socket assembly according to the second embodiment, similar to the socket assembly according to the first embodiment as mentioned above, comprises a socket board 10, a socket guide 20, and a spacer 110. In the socket board 10, a plurality of connection pins is formed and the socket guide 20 is mounted to cover the socket board 10. The spacer 110 is interposed between the socket board 10 and the socket guide 20 for contactably supporting a surface of a semiconductor (S). There is a difference between the socket assembly according to the second embodiment and the socket assembly according to the. first embodiment in a structure of the spacer 110. That is, in the center of the spacer 110 of the second embodiment according to the second embodiment, a plurality of pass through holes 111 is formed so that the connection pins 11 could be inserted respectively. Thus, as shown in FIGS. 7 and 8, when a semiconductor (S) is connected to a socket board 10, each ball (B) of the semiconductor (S) is connected to connection pins 11 through each pass through hole 111 and the entire area of the semiconductor (S) except the area of the balls (S) is supported, touching an upper surface of the spacer 110. Thereby, the semiconductor (S) is capable of maintaining a predetermined distance with the socket board 10, so that the semiconductor (S) may be connected to the connection pins 11 in a predetermined depth. Moreover, in the socket assembly according to the second embodiment, since the connection pins 111 are respectively inserted into each pass through hole 111 of the spacer 110, the arrangement among the spacer 110, the socket board 10 and the socket guide 20, when mounting the spacer 110 on an upper surface of the socket board 10, is precisely performed and it is needed to prevent the spacer 110 from moving after the arrangement. Thus, a socket assembly according to the present invention further comprises a location decision unit including two location decision pins 25, two location decision holes 115, and two location decision recesses 15. The two location decision pins 25 are perpendicularly formed at diagonal corners of an inner side of the socket guide 20 and the two location decision holes 115 are formed, passed through, at diagonal corners of the spacer 110 corresponding to the two location decision pins 25. The two location decision recesses 15 are formed at diagonal comers of the socket board 10 corresponding to the two location decision holes 115. The location decision pins 25 of the socket guide 20 passes through the location decision holes 115 of the spacer 110 and the location decision recesses 15 of the socket board 10 in order, so that it is possible to perform the precise arrangement when assembling the socket assembly and to prevent the location from being moved during the test. On the other hand, in the socket assembly of each above embodiment, the spacer is formed in a single unit in a plate shape. However, as shown in FIG. 9, the spacers 120 may be formed divided in plural so as to touch the area except the area of the balls (B) of a semiconductor (S). A plurality of guide projections 18 may be formed on an upper surface of the socket board 10 for guiding the installation location of each spacer 120. In the embodiments of the present invention, each spacer is formed, separated from the socket board, however it may be formed, united in a single unit to the socket board. Accordingly, the present invention has the following advantageous effects. First, when a semiconductor is connected to connection pins, a semiconductor is supported, touching a spacer first before a carrier touches a socket guide, so that the semiconductor may maintain a predetermined distance with the socket board, thereby the semiconductor connected to the connection pins in a predetermined depth in spite of various thicknesses of the semiconductors. Thus, it is not needed to replace carriers according to the thicknesses of the semiconductors. thereby reducing an expense and time caused by replacing carriers. Second, since edges of a semiconductor are pressed, supported by a spacer, the semiconductor is connected in a straight flat state although a bending of a semiconductor occurs. Therefore, the entire area of the semiconductor may be uniformly pressed without applying too much force to the semiconductor. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7256595 *Mar 22, 2004Aug 14, 2007Micron Technology, Inc.Test sockets, test systems, and methods for testing microfeature devices* Cited by examinerClassifications U.S. Classification324/756.02, 324/762.01International ClassificationG01R31/28Cooperative ClassificationG01R1/0433European ClassificationG01R1/04S3Legal EventsDateCodeEventDescriptionAug 4, 2005ASAssignmentOwner name: MIRAE CORPORATION, KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PARK, CHAN HO;HAM, CHUL HO;PARK, YOUNG GEUN;AND OTHERS;REEL/FRAME:016865/0483;SIGNING DATES FROM 20050720 TO 20050727May 14, 2012REMIMaintenance fee reminder mailedSep 30, 2012LAPSLapse for failure to pay maintenance feesNov 20, 2012FPExpired due to failure to pay maintenance feeEffective date: 20120930RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services