Source: http://www.patentgenius.com/patent/7449366.html
Timestamp: 2018-07-17 06:19:35
Document Index: 609010186

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Wafer level packaging cap and fabrication method thereof - Patent # 7449366 - PatentGenius
7449366 Wafer level packaging cap and fabrication method thereof
Application: 11/365,838
Kim; Woon-bae (Suwon-si, KR)
Lim; Ji-hyuk (Suwon-si, KR)
Ham; Suk-jin (Seoul, KR)
Moon; Chang-youl (Suwon-si, KR)
U.S. Class: 438/115; 257/704; 257/E21.5; 257/E21.505; 438/125
Field Of Search: 438/115; 438/125; 257/704; 257/E21.5; 257/E21.505
1. A fabrication method of a wafer level packaging cap for covering a device wafer with a device thereon, comprising: forming a plurality of connection grooves on a wafer; forming a seed layer on the connection grooves; forming connection parts by plating the connection grooves with a metal material; forming cap pads on a top surface of the wafer to be electrically connected to the connection parts; bonding a supportingfilm with the top surface of the wafer on which the cap pads are formed; forming a cavity on a bottom surface of the wafer to expose the connection parts through the cavity; and forming metal lines on the bottom surface of the wafer to be electricallyconnected to the connection parts.
2. The fabrication method according to claim 1, wherein the operation of forming the connection grooves comprises: patterning a mask on the wafer to correspond to the connection grooves; etching the wafer exposed by the patterned mask, fromthe top surface in a certain depth to fabricate the connection grooves; and removing the patterned mask and cleaning a surface of the wafer.
3. The fabrication method according to claim 1, wherein the operation of forming the seed layer comprises: oxidizing a surface of the wafer on which the connection grooves are formed; and depositing a top surface of the oxidized wafer and aninner surface of the connection grooves with a metal material to deposit the seed layer.
4. The fabrication method according to claim 3, wherein the operation of forming the connection parts comprises: plating the seed layer with the metal material to fill the connection grooves; and removing a top portion of the wafer by acertain thickness to expose the wafer and the metal material filling the connection grooves.
6. The fabrication method according to claim 1, wherein the operation of exposing the connection parts comprises: grinding a bottom portion of the wafer by a certain thickness to reduce a thickness of the wafer; and removing by a certain deptha part of the bottom surface of the wafer with the reduced thickness to form the cavity to expose the connection parts.
9. The fabrication method according to claim 4, wherein the operation of exposing the connection parts comprises: grinding a bottom portion of the wafer by a certain thickness to reduce a thickness of the wafer; and removing by a certain deptha part of the bottom surface of the wafer with the reduced thickness to form the cavity to expose the connection parts.
13. The fabrication method according to claim 9, wherein in the operation of forming the metal lines, the metal material is patterned by the patterned mask so as to be continuously extended from the connection parts, exposed to the cavity,towards an inner surface of the cavity and the bottom surface of the wafer.
14. The fabrication method according to claim 6, wherein in the operation of forming the metal lines, the metal material is patterned by the patterned mask so as to be continuously extended from the connection parts, exposed to the cavity,towards an inner surface of the cavity and the bottom surface of the wafer.
15. The fabrication method according to claim 1, further comprising: forming a cap sealing line on the bottom surface of the wafer to be bonded with a sealing line of the device wafer.
16. The fabrication method according to claim 15, further comprising: removing the supporting film after forming the metal lines and the cap sealing line.
17. The fabrication method according to claim 15, wherein the supporting film has a thickness of approximately 100 .mu.m through 200 .mu.m.
Generally, devices manufactured as a chip unit and performing certain functions are extremely vulnerable to damage from moisture, particles, and high temperature, and therefore, need to be packaged. Examples of the devices include microscopicmechanisms such as a Radio Frequency (RF) filter, RF switch and Radio Frequency Micro Electro Mechanical System (RF MEMS), and an actuator.
The term "wafer level packaging" means that, prior to dicing the wafer with a plurality of devices into individual chips, the wafer is hermetically sealed and packed with a packaging cap formed as a wafer unit.
The device wafer includes a device substrate, a device formed on a top portion of the device substrate to perform a certain function and a plurality of device pads electrically connected with the device, and is manufactured according to a generalsemiconductor fabrication process.
The packaging cap comprises a cap substrate having at the bottom surface a cavity of a certain volume providing a space for receiving the device and integrally packed with the device wafer, a plurality of first metal lines formed at the bottomsurface of the cap substrate to correspond to a plurality of the device pads electrically connected to the device, a plurality of second metal lines formed from the bottom surface of the cap substrate to an inner surface of the cavity to correspond toeach of the first metal lines, a plurality of connection holes penetrating to the top surface of the cap substrate to correspond to each of the second metal lines, a plurality of connection parts formed in each of the plurality of the connection holesand having the bottom portion electrically connected to each of the plurality of second metal lines, and a plurality of cap pads formed at the top surface of the cap substrate and electrically connected to each of top portions of the plurality ofconnection parts.
First, a wafer 10 is provided to be a cap substrate of a packaging cap as shown in FIG. 1A. A cavity is formed on a bottom portion of the wafer 10 according to a certain process, and a seed metal is deposited to cover the surface of the cavityand the bottom portion of the wafer 10 to form a seed layer 11.
As shown in FIG. 1B, mask patterns are formed on a top surface, i.e., an opposite side of the side with seed layer 11, of the wafer 10, and connection holes 10a are etched according to a dry etching by using an Inductively Coupled Plasma ReactiveIon Etching (ICP-RIE) process until the wafer 10 is completely penetrated.
Then, masks, forming the pattern (not shown) of the connection holes 10a, are removed according to an ashing process, and metal is deposited by plating from the seed layer 11 of the bottom of the connection holes 10a to form connection parts 12as shown in FIG. 1C. The heights of the plurality of connection parts 12 are not identical, and therefore, the heights become identical and are cleaned according to a lapping and Chemical Mechanical Polishing (CMP) process.
The seed layer of the bottom surface of the wafer 10 is patterned according to a photolithography to form first metal lines 11' (refer to FIG. 1D). On the bottom surface of the wafer 10, second metal lines 14 connected to the first metal lines11', and sealing lines 15 are formed. The sealing lines 15 are used for packaging with the device substrate during the following packaging process.
The connection holes should be fabricated to penetrate the wafer so that it takes a long time to fabricate the packaging cap. Silicon (Si) wafer is generally used for the cap substrate; however, the silicon wafer can not have the cap substrateless than 300 .mu.m due to the fabrication limitation thereof. Accordingly, the manufacturing cost cannot be reduced.
The present invention has been conceived to solve the above-mentioned problems, and an aspect of the present invention is to provide a wafer level packaging cap with an enhanced structure in which a thin cap substrate can be fabricated, andfabrication method thereof.
In order to achieve the above aspects, there is provided a wafer level packaging cap which covers a device wafer with a device thereon, including a cap substrate having on a bottom surface a cavity providing a space for receiving the device, andintegrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap substrate to correspond to each of a plurality of device pads electrically connected to the device, a plurality of connection parts formed topenetrate from the bottom surface to a top surface of the cap substrate to correspond to each of the metal lines, bottom portions of the connection parts being electrically connected to the metal lines, a plurality of cap pads formed at the top surfaceof the cap substrate to be electrically connected to the plurality of connection parts, and a seed layer formed at a boundary between the connection parts and the cap substrate.
In order to achieve the above aspects, there is provided a fabrication method of a wafer level packaging cap for covering a device wafer with a device thereon, including forming a plurality of connection grooves on a wafer, forming a seed layeron the connection grooves, forming connection parts by plating the connection grooves with a metal material, forming cap pads on a top surface of the wafer to be electrically connected to the connection parts, bonding a supporting film with the topsurface of the wafer on which the cap pads are formed, forming a cavity on a bottom surface of the wafer to expose the connection parts through the cavity, and forming metal lines on the bottom surface of the wafer to be electrically connected to theconnection parts.
The operation of forming the connection grooves may include patterning a mask on the wafer to correspond to the connection grooves, etching the wafer exposed by the patterned mask, from the top surface in a certain depth to fabricate theconnection grooves, and removing the patterned mask and cleaning a surface of the wafer.
The operation of forming the seed layer may include oxidizing a surface of the wafer on which the connection grooves are formed, and depositing a top surface of the oxidized wafer and an inner surface of the connection grooves with a metalmaterial to deposit the seed layer.
The operation of forming the connection parts may comprise plating the seed layer with the metal material to fill the connection grooves, and removing a top portion of the wafer by a certain thickness to expose the wafer and the metal materialfilling the connection grooves.
The operation of exposing the connection parts may include grinding a bottom portion of the wafer by a certain thickness to reduce a thickness of the wafer, and removing by a certain depth a part of the bottom surface of the wafer with thereduced thickness to form the cavity to expose the connection parts.
In the operation of forming the metal lines, the metal material is patterned by the patterned mask so as to be continuously extended from the connection parts, exposed to the cavity, towards an inner surface of the cavity and the bottom surfaceof the wafer.
The supporting film may have a thickness of approximately 100 .mu.m through 200 .mu.m, and the supporting film includes an ultra violet (UV) tape.
Exemplary embodiments of the present invention will be described in detail with reference to the annexed drawings. In the drawings, the same elements are denoted by the same reference numerals throughout the drawings. In the followingdescription, detailed descriptions of known functions and configurations incorporated herein have been omitted for conciseness and clarity.
The cap substrate 20 covering a top portion of a cap device wafer 4, has at the bottom surface a cavity 20b of a certain volume providing a space for receiving a device 50. The plurality of metal lines are formed at the bottom surface of the capsubstrate 20 to correspond to a plurality of device pads 42 electrically connected to the device 50. The plurality of connection parts 24 are formed to penetrate from the bottom surface to the top surface of the cap substrate 20 to correspond to each ofthe metal lines 26. The plurality of cap pads 25 are formed at the top surface of the cap substrate 20 and electrically connected to each of top portions of the plurality of connection parts 24.
The cap substrate 20 is a silicon wafer, and hereinafter is called a wafer. The cavity 20b is formed in a certain depth and width at a part of a bottom surface of the cap wafer 20. The connection parts 24 are exposed through the cavity 20b tothe bottom surface of the wafer 20 so as to be electrically connected to the metal lines 26.
A plurality of the metal lines 26 are provided to extend from an inner side of the cavity 20b over a slant side towards the bottom surface of the wafer 20 except for the cavity 20b so as to be electrically connected to the bottom portion of theconnection parts 24.
The connection parts 24 are formed to penetrate through the wafer 20. The bottom portions of the connection parts 24 are electrically connected to the metal lines 26, and the top portions thereof are electrically connected to the cap pads 25. The connection parts 24 are formed by plating connection grooves formed in the wafer 20 with metal material such as copper. The connection grooves will be explained later. As shown in FIG. 2B, seed layers 23 are formed at plated portions, i.e., theboundary between the wafer 20, of the connection parts 24. The seed layers 23 are formed by depositing metal material with a certain thickness into the connection grooves before the connection parts 24 are formed by plating the connection grooves formedin the wafer 20 with the metal material. The seed layer 23 can be formed by oxidizing the surface of the wafer 20, i.e., the inner side of the connection grooves before depositing. This will be explained later.
After being formed according to the above process, the seed layers 23 are plated with metal material to form the connection parts 24 so that the electric quality of the connection parts 24 can be enhanced and the binding thereof can be alsoenhanced by plating. Therefore, the connection parts 24 can have a stable electric quality.
In FIG. 2A, the reference numeral 41 denotes an insulation layer formed on the packaging surface of the wafer body 40. On the insulation layer 41, a device 50, device pads 42 and the sealing lines 43 are formed. The cavity 20b provides a spacefor receiving the device 50 performing a certain function, and is formed by etching a part of the bottom surface of the wafer 20. Accordingly, the size of the cavity 20b is set depending on the device 50 of certain function formed on the device wafer 4.
As shown in FIG. 3A, a wafer 20 of a certain thickness is provided to form the cap substrate. The initial wafer 20 may have a thickness of approximately 300 .mu.m. A mask 21 is patterned on the top surface of the wafer 20. As shown in FIG. 3B,the top surface of the wafer 20, exposed by the patterning of the mask 21, is etched away in a certain depth to form the connection grooves 20a. The connection grooves 20a are etched according to dry-etching, and may have a thickness of approximately150 .mu.m. Here, the dry-etching may be performed by using an Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) process.
As shown in FIG. 3D, the entire surface of the wafer 20 is oxidized into an oxidized layer 22. The oxidized layer 22 is formed over the top portion, the bottom portion and the side portions of the wafer 20, and the inner side of the connectiongroves 20a.
As shown in FIG. 3F, the top surface of the wafer 20, i.e., the surface of the seed layer 23 is electroplated with metal material so that the connection grooves 20a are filled with metal material that will be the connection parts 24 later. Here,the metal material may be copper (Cu), aurum (Au) and nickel (Ni).
After depositing the metal material by electroplating as above, a part of the top portion of the wafer 20 is removed by a certain thickness and planarized according to a mechanical grinding as shown in FIG. 3G. Then, the metal material plated onthe wafer 20, the seed layer 23 and the oxidized layer 22 are all removed so that the top portions of the wafer 20 and the connection parts 24 are exposed.
As shown in FIG. 3H, metal material is patterned on the planarized wafer 20 to form a plurality of cap pads 25. The cap pads 25 correspond to the number of the connection pads 24, and the cap pads 25 are electrically connected to each of thecorresponding connection parts 24, respectively.
After the cap pads 25 are formed on the wafer 20 as above, a supporting film 30 is bonded with the top surface of the wafer 20 as shown in FIG. 4A. Here, the supporting film 30 may be an ultra violet (UV) tape. The UV tape operates as areinforcement member, that is, strengthens the wafer 20 and prevents breakages or damage during the fabrication process of the wafer 20. The supporting film 30 may have a thickness corresponding to the thickness, i.e., 100 .mu.m through 200 .mu.m, ofthe wafer 20 when the cap pads 25 are formed.
The bottom portion of the wafer 20 bonded with the supporting film 30 is ground by a certain thickness according to a Chemical Mechanical Polishing (CMP) process as shown in FIG. 4B so as to reduce the entire thickness. Here, the wafer 20 groundaccording to the CMP process may have a thickness of approximately 120 .mu.m so that the bottom portion of the connection parts 24 cannot be exposed.
As shown in FIG. 4C, the bottom surface of the wafer 20 is removed according to a certain process to form the cavity 20b to expose the connection parts 24. The depth of the cavity 20b is set depending on the size of the device 50 and sufficientto expose the connection parts 24. The cavity 20b is fabricated according to an etching process. The etching process may be performed according to a dry etching by using ICP-RIE process.
After the cavity 20b is formed, a plurality of metal lines 26 are patterned and formed on the bottom surface of the wafer 20 as shown in FIG. 4D. A plurality of the metal lines 26 are formed to be electrically connected to the connection parts24. Each metal line 26 may be continually formed by extending from the inner side of the cavity 20b over the slant side towards the bottom surface of the wafer 20 around the cavity 20b.
As described above, if the wafer level packaging cap and the fabrication method thereof according to embodiments of the present invention are applied, the oxidized layer and seed layer are formed at the connection grooves, through which theconnection parts are formed, of the wafer to protect the connection parts. Therefore, the metal material can be stably plated so that the physical and electric features of the connection parts can be enhanced.
During the fabrication process of the packaging cap, the supporting film is bonded with the wafer to fabricate the wafer. Therefore, the packaging cap can be completely fabricated before packaged with the device wafer. Accordingly, variousdevices can be simultaneously fabricated on the wafer so that the convenience can be enhanced and an effective yield can be obtained.
Additionally, only the connection grooves are formed in a certain depth to form the connection parts without requiring to penetrate the wafer. Therefore, the time for ICP RIE fabrication and plating to form the connection grooves can be reducedand the entire manufacturing cost can be reduced.
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