Source: http://www.google.com/patents/US7733945?dq=5,579,517
Timestamp: 2014-09-01 14:26:30
Document Index: 162195875

Matched Legal Cases: ['Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'art6', 'art6']

Patent US7733945 - Spread spectrum with doppler optimization - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA method of compensating for doppler phase errors includes receiving a signal at a receiver wherein the signal is spread using a pseudo-noise code, dividing the signal into a plurality of smaller coherent units and then compensating for induced doppler phase errors by analyzing the plurality of smaller...http://www.google.com/patents/US7733945?utm_source=gb-gplus-sharePatent US7733945 - Spread spectrum with doppler optimizationAdvanced Patent SearchPublication numberUS7733945 B2Publication typeGrantApplication numberUS 12/472,642Publication dateJun 8, 2010Filing dateMay 27, 2009Priority dateMar 18, 2008Fee statusPaidAlso published asUS20090238248, WO2010138356A2, WO2010138356A3Publication number12472642, 472642, US 7733945 B2, US 7733945B2, US-B2-7733945, US7733945 B2, US7733945B2InventorsTheodore J. Myers, Daniel Thomas WernerOriginal AssigneeOn-Ramp Wireless, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (103), Non-Patent Citations (44), Referenced by (2), Classifications (6), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSpread spectrum with doppler optimizationUS 7733945 B2Abstract A method of compensating for doppler phase errors includes receiving a signal at a receiver wherein the signal is spread using a pseudo-noise code, dividing the signal into a plurality of smaller coherent units and then compensating for induced doppler phase errors by analyzing the plurality of smaller coherent units. Analysis may include producing a plurality of coherent sums by summing across the smaller coherent units and then summing non-coherently the plurality of coherent sums. Analysis may also include demodulating a symbol from the smaller coherent units. A modulation technique may be selected from a plurality of modulation techniques and then be used to encode and transmit a symbol stream.
receiving a first signal at a receiver, wherein the first signal is spread using a predetermined pseudo-noise (PN) code;
dividing the first signal into a plurality of first smaller coherent units;
summing across each of the plurality of first smaller coherent units to produce a plurality of first coherent sums;
summing non-coherently the plurality of first coherent sums to detect a magnitude of the first signal;
selecting a coherent integration length based on the magnitude of the first signal to configure a demodulation;
receiving a second signal at the receiver, wherein the second signal is spread using the predetermined pseudo-noise (PN) code;
dividing the second signal into a plurality of second smaller coherent units; and
demodulating a first symbol from the plurality of first smaller coherent units and the plurality of second smaller coherent units comprises cross multiplying the complex conjugate of a unit of the first smaller coherent units with a unit of the second smaller coherent units.
2. The method of claim 1, wherein the demodulation of the first symbol relies on a first unit of the plurality of first smaller coherent units and a last unit of the plurality of second smaller coherent units.
3. The method of claim 1, wherein the first signal neighbors the second signal in a sequence of signals.
4. The method of claim 1, wherein the first signal has a first random timing offset.
5. The method of claim 1, wherein the second signal has a second random timing offset.
detecting an induced doppler phase error in the first signal;
selecting a modulation technique from a plurality of modulation techniques from among the following modulation techniques: differential binary phase shift keyed modulation or 2-ary modulation;
encoding a symbol stream using the selected modulation technique; and
transmitting the encoded symbol stream.
7. The method of claim 6, further wherein the selected modulation technique is based on the detected induced doppler phase error.
selecting a second modulation technique from the plurality of modulation techniques; and
encoding a second symbol stream using the selected second modulation technique.
9. A device for communicating in a spread spectrum system comprising:
a receiver in communication with a processor and configured to receive a first signal and a second signal, wherein the first signal is spread using a predetermined pseudo-noise (PN) code and the second signal is spread using the predetermined pseudo-noise (PN) code; and
divide the first signal into a plurality of first smaller coherent units,
sum across each of the plurality of first smaller coherent units to produce a plurality of first coherent sums;
sum non-coherently the plurality of first coherent sums to detect a magnitude of the first signal;
select a coherent integration length based on the magnitude of the first signal to configure a demodulation;
demodulate a first symbol from the plurality of first smaller coherent units and the plurality of second smaller coherent units comprises cross multiplying the complex conjugate of a unit of the first smaller coherent units with a unit of the second smaller coherent units.
10. The device of claim 9, wherein the first signal has a first random timing offset.
a device having a receiver configured to receive a first signal and a second signal, wherein the first signal is spread using a predetermined pseudo-noise (PN) code and the second signal is spread using the predetermined pseudo-noise (PN) code; and a processor operatively coupled to the receiver and configured to:
demodulate a first symbol from the plurality of first smaller coherent units and the plurality of second smaller coherent units comprises cross multiplying the complex conjugate of a unit of the first smaller coherent units with a unit of the second smaller coherent units; and
an access point in communication with the device, wherein the access point comprises a transmitter configured to transmit the first signal.
12. The system of claim 11, wherein the first signal has a first random timing offset.
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS The present application is a continuation-in-part application of U.S. patent application Ser. No. 12/189,609, entitled �Random Phase Multiple Access Communication Interface System and Method,� filed Aug. 11, 2008, which claims priority to U.S. Patent Application No. 61/037,522, filed Mar. 18, 2008. The present application is also a continuation-in-part application of U.S. patent application Ser. No. 12/189,619, entitled �Uplink Transmitter in a Random Phase Multiple Access Communication System,� filed Aug. 11, 2008, which claims priority to U.S. Patent Application No. 61/037,522, filed Mar. 18, 2008. The present application is also a continuation-in-part application of U.S. patent application Ser. No. 12/189,533, entitled �Despreading Spread Spectrum Data,� filed Aug. 11, 2008, which claims priority to U.S. Patent Application No. 61/037,522, filed Mar. 18, 2008. The present application is also a continuation-in-part application of U.S. patent application Ser. No. 12/189,505, entitled �Tag Communications with Access Point,� filed Aug. 11, 2008, which claims priority to U.S. Patent Application No. 61/037,522, filed Mar. 18, 2008. The present application is also a continuation-in-part application of U.S. patent application Ser. No. 12/276,971, entitled �Slotted Mode Acquisition,� filed on Nov. 24, 2008, which claims priority to U.S. Patent Application No. 61/037,522, filed Mar. 18, 2008. The present application is also a continuation-in-part application of U.S. patent application Ser. No. 12/345,267, entitled �Random Phase Multiple Access System with Location Tracking,� filed Dec. 29, 2008, which claims priority to U.S. patent application Ser. Nos. 12/189,505, 12/189,533, 12/189,609, and 12/189,619, all of which were filed on Aug. 11, 2008, and which also claims priority to U.S. Patent Application No. 61/037,522, filed Mar. 18, 2008. The present application is also a continuation-in-part application of U.S. patent application Ser. No. 12/345,374, entitled �Random Phase Multiple Access System with Meshing,� filed on Dec. 29, 2008, which claims priority to U.S. patent application Ser. Nos. 12/189,505, 12/189,533, 12/189,609, and 12/189,619, all of which were filed on Aug. 11, 2008, and which also claims priority to U.S. Patent Application No. 61/037,522, filed Mar. 18, 2008.
FIG. 10 is a diagram illustrating a data sub-slot hierarchy in accordance with a representative embodiment.
In FIG. 12, circular buffer 1200 receives communication signals over the I channel and the Q channel. These signals are sent to time tracking logic 1202. The time tracking logic 1202 also receives a coarse AFC hypothesis and the logic 1202 may reset to zero at even chip�4 parity. The time tracking logic 1202 can have two blocks, one with counters initialized to zero for even chip�4 parity, and one with counters initialized to midrange (i.e., 2^25) for odd chip�4 parity. The output of time tracking logic 1202 is provided to a block 1204 in which virtual chip�4 phases are applied. Block 1204 also can receive parity from an acquisition state machine. Automatic frequency control (AFC) rotation logic 1206 is applied to an output of block 1204. The AFC Rotation logic 1206 output is passed to the PN Despreading Array 1208 described herein. The results from the PN despreading array are used by the non-coherent accumulation buffer 1210 to select the top N paths 1212. The number of paths selected depends on a number of factors include space available for demodulation.
FIG. 13 further illustrates a tag receive path including receive demodulation. In FIG. 13, the circular buffer 1300 receives communication signals over the I channel and the Q channel. These signals are sent to time tracking logic 1302 and on to dedicated fingers 1304. The time tracking logic 1302 also receives a coarse AFC hypothesis and the logic 1302 may reset to zero at even chip�4 parity. The time tracking logic 1302 can have two blocks, one with counters initialized to zero for even chip�4 parity, and one with counters initialized to midrange (i.e., 2^25) for odd chip�4 parity. The output of time tracking logic 1302 is provided to dedicated fingers 1304 which have been assigned during acquisition as previously described. The dedicated fingers 1304 also receive a PN code selection. The output of the dedicated fingers 1304 is passed to a bit width squeezer 1306. The bit width squeezer 1306 output is passed to a frame buffer 1308. The frame buffer 1308 data is demodulated by the cross product multiplication block 1310. The output of the cross product multiplication block 1310 is passed to the fine AFC multiply 1312, which also takes a fine AFC hypothesis as input. The data is then passed to a deinterleaver 1314, which may comprise a Viterbi decoder, and finally to a CRC checker 1316. This process is explained further herein.
FIG. 14 further illustrates a tag receive path including preamble processing which is done on a boosted preamble while the circular sample buffer is frozen. This figure is identical to FIG. 13 up to the Fine AFC Multiply block 1412. In FIG. 14, the circular buffer 1400 receives communication signals over the I channel and the Q channel. These signals are sent to time tracking logic 1402 and on to dedicated fingers 1404. The time tracking logic 1402 also receives a coarse AFC hypothesis and the logic 1402 may reset to zero at even chip�4 parity. The time tracking logic 1402 can have two blocks, one with counters initialized to zero for even chip�4 parity, and one with counters initialized to midrange (i.e., 2^25) for odd chip�4 parity. The output of time tracking logic 1402 is provided to dedicated fingers 1404 which have been assigned during acquisition as previously described. The dedicated fingers 1404 also receive a PN code selection. The output of the dedicated fingers 1404 is passed to a bit width squeezer 1406. The bit width squeezer 1406 output is passed to a frame buffer 1408. The frame buffer 1408 data is demodulated by the cross product multiplication block 1410. The output of the cross product multiplication block 1410 is passed to the fine AFC multiply 1412, which also takes a fine AFC hypothesis as input. The hamming and AFC metrics block 1418 produces results that can be used to determine timing for receive operations and a frequency offset, a spreading factor selection, and a modulation type (DBPSK or 2-ary modulation) for transmit operations. This process is explained further herein.
Acquisition for Phase 1 begins at time 2252 but fails to yield valid CRCs and thus frame timing. The Phase 1 acquisition rectangle successfully completes at time 2254 and a few valid symbols are output by the dedicated fingers. However, the Broadcast channel disappears before a full frame can be demodulated. After 2 full frame durations elapse with no successfully demodulated frames (no CRC test pass) a time-out condition occurs and no frame timing is learned.
At block 2808, the data stream is upsampled by a 4� oversample filter and time tracking logic is used to ensure that all of the frames land at the same sample rate consistent with the frequency reference of the AP. Block 2808 receives a sample slip/repeat indicator as an input. In one embodiment, an output of block 2808 may have a real frequency of approximately 4 megahertz (MHz). At block 2810, an automatic frequency control (AFC) rotation is done including a frequency offset to match the combination of the node and access point's total frequency offset, ensuring that all of the frames from all of the users land near zero frequency offset. In one embodiment, an output of block 2810 may have a complex frequency of approximately 4 MHz. At block 2812, a delay is imposed from the start slot until the correct access slot occurs. In addition, a random chip delay is imposed on the signal. In a representative embodiment, the random chip delay can be from 0 to the spreading factor minus 1. Alternatively, a different random chip delay may be used. The slot access can be described by A(i,j) where i is related to the spreading factor as 2^(13-i) and j is the sub-slot number corresponding to non-overlapping slots. Depending upon the selected spreading factor, there are generally multiple transmit opportunities in a given slot. For the uplink, the access slot can be randomly selected along with a chip offset from 0 to spreading factor minus 1. The node may transmit in multiple sub-slots per slot, as long as these sub-slots do not overlap. As such, the probability of collision between uplink users is minimized, while allowing for re-selection for cases where there are collisions. After the signal has been delayed, the signal can be transmitted to an access point.
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Retrieved from the Internet: <URL: http://www.ss.fpp.edu/�fdimc/laboratorijske�vale/Inteligientni�transportni�sistemi/Literatura�za�sirjenje�obzorja/ITS�mobile�phone�location�determination.pdf>.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8121174May 26, 2011Feb 21, 2012On-Ramp Wireless, Inc.Signal quality measurement systemUS8437431 *Sep 10, 2008May 7, 2013Gregory Hubert PiesingerSequential decoder fast incorrect path elimination method and apparatus for pseudo-orthogonal coding* Cited by examinerClassifications U.S. Classification375/149International ClassificationH04B1/707Cooperative ClassificationH04W56/0035, H04B1/7085European ClassificationH04B1/7085, H04W56/00HLegal EventsDateCodeEventDescriptionNov 6, 2013FPAYFee paymentYear of fee payment: 4Feb 11, 2010ASAssignmentOwner name: ON-RAMP WIRELESS, INC.,CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MYERS, THEODORE J.;WERNER, DANIEL THOMAS;US-ASSIGNMENT DATABASE UPDATED:20100212;REEL/FRAME:23925/743Effective date: 20100210Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MYERS, THEODORE J.;WERNER, DANIEL THOMAS;REEL/FRAME:23925/743Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MYERS, THEODORE J.;WERNER, DANIEL THOMAS;REEL/FRAME:023925/0743RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google