Source: https://patents.google.com/patent/JPWO2007097019A1/en
Timestamp: 2020-01-27 08:32:36
Document Index: 369142473

Matched Legal Cases: ['art 11', 'art 11', 'art 11', 'art 11', 'art 12', 'art 12']

JPWO2007097019A1 - Cache control device and cache control method - Google Patents
Cache control device and cache control method Download PDF
JPWO2007097019A1
JPWO2007097019A1 JP2008501571A JP2008501571A JPWO2007097019A1 JP WO2007097019 A1 JPWO2007097019 A1 JP WO2007097019A1 JP 2008501571 A JP2008501571 A JP 2008501571A JP 2008501571 A JP2008501571 A JP 2008501571A JP WO2007097019 A1 JPWO2007097019 A1 JP WO2007097019A1
JP2008501571A
JP4332205B2 (en
宗太 草地
森田　國樹
國樹 森田
鵜飼　昌樹
昌樹 鵜飼
智順 大川
2006-02-27 Application filed by 富士通株式会社 filed Critical 富士通株式会社
2006-02-27 Priority to PCT/JP2006/303589 priority Critical patent/WO2007097019A1/en
2009-07-09 Publication of JPWO2007097019A1 publication Critical patent/JPWO2007097019A1/en
2009-09-16 Publication of JP4332205B2 publication Critical patent/JP4332205B2/en
When the writing processor detects a block failure, it writes predetermined data indicating that the data is being degenerated outside the ECC protection area and outside the ECC protection area as entry data to the tag RAM, and the read processing section When data is read from the block, the degeneration status determination unit performs a degeneration status determination during / without degeneration after adding data errors to the predetermined data previously written by the write processing unit and In some cases, error judgment such as way degeneration and fatal error is performed.
The present invention relates to a cache memory device having a way including a plurality of blocks in which each entry data is stored and a cache control method, and particularly to reducing degeneration information associated with block degeneration when performing degeneration in units of blocks. The present invention relates to a cache control device and a cache control method capable of performing the above.
2. Description of the Related Art Conventionally, a cache memory that is a small-capacity and high-speed memory that is used to alleviate the performance difference between a processing device such as a CPU (Central Processing Unit) and a storage device such as a memory is known. In this cache memory, a way (Way) including storage units called blocks (blocks) corresponding to the number of indexes is provided in parallel, and a block (cache line) having the same index across each way is generally accessed during data access. Has been done.
Also, a tag RAM (Random Access Memory) for storing a tag (Tag) stored in the cache memory and indicating a position of the cache data on the main memory is prepared, and a cache data address list is provided to the CPU. It is also done. The tag RAM also employs the data structure using the above-described ways and blocks.
Incidentally, an access error may frequently occur in a block which is a storage unit in a cache memory due to the influence of a memory failure or the like. In such a case, if a block in which an access error has occurred is used as it is, a serious failure may be induced. Therefore, it is necessary to stop (degenerate) the use of the corresponding block.
As one of the degeneration methods, there is a method in which when a failure occurs in a specific block, the way itself including the block is degenerated. According to this method, the failure block can be easily reduced, but all the blocks included in the way subject to reduction become unusable, so that the performance of the cache memory is lowered. For this reason, when a failure occurs in a specific block, various reduction methods for reducing only this block have been proposed (see, for example, Patent Document 1 and Patent Document 2).
JP-A-60-101656 JP-A-2-302856
However, when the techniques of Patent Document 1 and Patent Document 2 are used, there is a problem that it is necessary to hold degeneration information representing a degeneration state for each fault block, and the amount of circuits increases. In particular, when many ways including a large number of blocks are provided, the number of blocks becomes very large, and accordingly, a storage circuit for holding degeneracy information is involved.
For this reason, when performing block unit degeneration, how to realize a cache control apparatus capable of reducing degeneration information associated with block degeneration is a major issue. Such a problem is a problem that commonly occurs in information processing apparatuses including a cache memory.
The present invention has been made to solve the above-described problems of the prior art, and provides a cache control device and a cache control method capable of reducing degeneration information associated with block degeneration when performing block-based degeneration. The purpose is to provide.
In order to solve the above-described problems and achieve the object, the present invention provides a cache memory device having a way including a plurality of blocks in which each entry data is stored, wherein the blocks are degenerated. Degeneration information writing means for writing the degeneration information represented to the block, and a degeneration status for determining the degeneration status of the block based on the read result of the degeneration information written by the degeneration information writing means for the block And determining means.
Further, according to the present invention, in the above invention, the degeneration information writing means writes first degeneration information indicating that degeneration is in progress in the error correction protection area in the entry data and is outside the error correction protection area. Is also written with second degeneration information indicating that degeneration is in progress.
Further, the present invention is characterized in that, in the above invention, the degeneration information writing means writes a value that cannot normally be stored in the error correction protection area as the first degeneration information. And
Further, the present invention is characterized in that, in the above-mentioned invention, the degeneration information writing means writes 2-bit information indicating that degeneration is being performed as the second degeneration information.
The present invention is also a cache control method in a cache memory device having a way including a plurality of blocks each storing entry data, wherein degenerate information indicating that the block is degenerated is sent to the block. A degeneration information writing step for writing the block, and a degeneration status determination step for determining the degeneration status of the block based on the read result of the degeneration information written by the degeneration information writing step for the block. Features.
According to the present invention, degenerate information indicating that a block is degenerated is written to this block, and when this block is read, the degeneration status of the block is determined based on the read result of the previously written degeneration information. Since the degenerate information is stored in the entry data for the block, the degeneration information associated with the block degeneration can be reduced when the degeneration is performed in units of blocks.
Further, according to the present invention, the first degeneration information indicating that the degeneration is being performed in the error correction protection area in the entry data is written, and the second degeneration is performed indicating that the degeneration is also being performed outside the error correction protection area. Since the information is written, the size of the degenerate information outside the error correction protection area can be minimized by using the error correction function in the error correction protection area.
In addition, according to the present invention, since the data that should normally be stored in the error correction protection area is written as the first degenerate information, a value that cannot normally be taken is written, so that each item in the error correction protection area is used as it is. By doing so, there is an effect that it is not necessary to secure a new area for storing degenerate information in the error correction protection area.
In addition, according to the present invention, since it is configured to write 2-bit information indicating that degeneration is being performed as the second degeneration information, by using the minimum degeneration information, the necessary degeneration information for each block can be obtained. The storage area can be suppressed. Therefore, particularly in a cache memory including a large number of blocks, there is an effect that it is possible to greatly reduce the area for storing degenerate information.
FIG. 1 is a diagram showing an overview of a cache control method according to the present invention. FIG. 2 is a diagram showing a tag RAM control unit to which the cache control method according to the present invention is applied. FIG. 3 is a block diagram showing a configuration of the tag RAM control unit. FIG. 4 is a diagram illustrating an example of failure information. FIG. 5 is a diagram illustrating an example of degeneration status determination. FIG. 6 is a flowchart showing the processing procedure of the block degeneration processing.
DESCRIPTION OF SYMBOLS 10 Tag RAM control part 11 Control part 11a Write process part 11b Read process part 11c Degeneration situation determination part 12 Storage part 12a Tag RAM
Hereinafter, preferred embodiments of a cache control method according to the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, a case where the cache control method according to the present invention is applied to a tag RAM control unit provided in a system controller (SC) connected to a plurality of CPUs will be described.
First, the outline of the cache control method according to the present invention will be described with reference to FIG. FIG. 1 is a diagram showing an overview of a cache control method according to the present invention. Since the data structure in the tag RAM is also shown in the figure, the data structure in the tag RAM will be first described here. Further, FIG. 1 shows a tag RAM for 1 CPU. For example, in the case of 4 CPUs, there are 4 sets (4 CPUs) of tag RAMs shown in FIG.
As shown in the figure, the tag RAM has a total of 12 ways (WAY) of 0 to 11. Each way includes 2048 blocks (BLOCK). Here, the block is a unit of data entry, and when the CPU refers to the block, blocks (cache lines) having the same index (INDEX) in a plurality of ways are collectively accessed. For example, when referring to a block whose index is “3”, 12 blocks whose indexes are “3” in way 0 to way 11 are simultaneously accessed.
By the way, in such a tag RAM including a large number of blocks, an access error may frequently occur when accessing a specific block due to the influence of a failure at a predetermined position in the RAM. In such a case, if a block in which an error has occurred is left unattended, it may lead to a serious failure. Therefore, it is necessary to degenerate this block.
When a failure block is degenerated, if the way itself including the failed block is degenerated, the degeneration information indicating that degeneration is in progress is only the number of ways (in the case of FIG. 1, 12 is sufficient). Therefore, the amount of circuits such as registers necessary for holding the degeneration information is not increased. However, if the way itself is degenerated, blocks that are not faulty cannot be used, so the performance of the tag RAM is degraded.
On the other hand, if the method of degenerating only the faulty block is used, it is possible to minimize the performance degradation of the tag RAM. However, the degeneration information described above is the number of blocks (in the case of FIG. 1, 12 × (2048 = 24576) is necessary, and how to reduce the size of the degenerate information is a big problem.
Therefore, in the cache control method according to the present invention, when a block to be reduced (failed block) is detected (see (1) in FIG. 1), the entry data for the block has a status indicating that the block is being reduced. It was. In addition, block degeneration is performed by writing degeneration information (information indicating that degeneration is in progress) in the ECC (Error Correcting Code) protection area (for example, a physical address indicating the location of data) and outside the ECC protection area in the entry data. This was expressed (see (2) in FIG. 1).
Normally, when writing the degeneration information only outside the ECC protection area, it is necessary to configure the degeneration information with at least 5-bit data when attempting to completely detect and correct a data error when reading the written data up to a 2-bit error. is there. On the other hand, in the cache control method according to the present invention, since a bit indicating that degeneration is in progress is written in the ECC protection area, an error correction result in the ECC protection area can be used. Therefore, the degeneration information outside the ECC protection area can be suppressed to 2 bits.
In the ECC protection area, when the block is normal, normal time information such as a physical address indicating the location of data and a status indicating the reference state from the CPU is written, but a failure has occurred in the block. In this case, since it is not necessary to hold the normal information, a predetermined bit representing the degenerate information may be written in the ECC protection area.
Next, the relationship between the tag RAM control unit to which the cache control method according to the present invention is applied and other devices will be described with reference to FIG. FIG. 2 is a diagram showing a tag RAM control unit to which the cache control method according to the present invention is applied. In this embodiment, the case where the cache control method is applied to the tag RAM control unit in the system controller (SC) will be described. However, the tag RAM control unit itself may be configured as one cache control device. Absent. Further, the cache control method according to the present invention can be applied not only to cache control in the tag RAM but also to cache control for various cache memories.
In the case shown in FIG. 2, the system controller (SC) including the tag RAM control unit is connected to four CPUs. Each CPU has a cache memory therein and includes a tag RAM as an index of data in the cache memory. The tag RAM control unit holds a copy of the tag RAM of each of the four CPUs.
For example, when the CPU 0 cannot find the desired data in the cache memory in its own CPU, the CPU 0 refers to the tag RAM control unit so that the other CPUs (CPUs 1 to 3) have the desired data. It is determined whether or not. If the other CPU has the desired data, the desired data can be acquired from the corresponding CPU. If the desired data is not found even after referring to the tag RAM in the tag RAM control unit, a request for obtaining desired data is sent to the memory access controller (MAC) connected via the system controller (SC). Will be performed.
Next, the configuration of the tag RAM control unit shown in FIG. 2 will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration of the tag RAM control unit 10. As shown in the figure, the tag RAM control unit 10 includes a control unit 11 and a storage unit 12. The control unit 11 further includes a write processing unit 11a, a read processing unit 11b, and a degeneration status determination unit 11c, and the storage unit 12 includes a tag RAM 12a corresponding to each CPU.
When the control unit 11 detects a faulty block, the control unit 11 writes predetermined fault information in the corresponding block of the tag RAM 12a and reads out the corresponding block based on the read data. It is a process part which performs the process which determines.
The write processing unit 11a is a processing unit that writes entry data from the CPU into each block of the tag RAM 12a and performs processing for writing predetermined failure information to the corresponding block of the tag RAM 12a when a failure block is detected. is there. Here, an example of failure information written by the write processing unit 11a will be described with reference to FIG. FIG. 4 is a diagram illustrating an example of failure information. 41 shows the entry structure of the tag RAM, and 42 in the figure shows a state that the entry structure shown in 41 takes when degenerated.
As shown at 41 in FIG. 4, the tag RAM entry configuration is composed of a flag outside the ECC protection area, a physical address (PA) and status (STS) inside the ECC protection area, and ECC. The flag is 2-bit information, “11” is “degenerate”, “00” is “no degeneration”, “01” or “10” is “unused”, respectively. Appears. The physical address is 22-bit data, for example, and represents an address indicating a data storage destination.
The status is, for example, 8-bit data and indicates a data holding state indicated by a tag (TAG) in the CPU. In this holding state, the corresponding data is held by one CPU, held by a plurality of CPUs, held by a plurality of CPUs, but the data held by the CPU is newer. There are four states. The ECC is, for example, 7-bit data and is used to protect the physical address and status.
When a faulty block is detected, the data indicated by 42 in FIG. 4 is written in the tag RAM entry indicated by 41 in FIG. Specifically, “11” indicating “degenerate” in the flag, “all bits 1” not existing as physical addresses in the physical address, and “status where the CPU does not have valid data” in the status "All bits 0" is written, and "No error" information is written in the ECC.
In this way, the degeneration information indicating that the block is being degenerated is written to the corresponding block, but when reading the written data, data different from the writing time may be read due to a data error. However, as will be described later, the degeneration situation determination unit 11c determines the degeneration situation in consideration of such a data error, so that the degeneration situation can be accurately grasped.
Returning to FIG. 3, the read processing unit 11b will be described. The read processing unit 11b is a processing unit that performs processing for passing the read data read from the tag RAM entry 12a to the CPU and for passing the read information to the degeneration status determination unit 11c when a faulty block is read. .
The degeneration status determination unit 11c is a processing unit that determines the degeneration status of the corresponding block based on the read data received from the read processing unit 11b and notifies the external device of the determination result. Here, details of the determination process performed by the degeneration state determination unit 11c will be described with reference to FIG. FIG. 5 is a diagram illustrating an example of degeneration status determination. In the figure, “CE” indicates a collectable error (there was a data error but has been corrected), and “UE” indicates an uncorrectable error (an uncorrectable data error).
As shown in FIG. 5, the degeneration status determination unit 11c is necessary depending on the block degeneration determination based on the flag that is not subject to ECC protection, the physical address and status within the ECC protection target, and the ECC determination result. Select the error processing that becomes.
A case where the flag is “00” is indicated by 51 in FIG. In this case, as described with reference to FIG. 4, “00” indicates “no degeneration”, but the write processing unit 11 a writes “11 (degenerate)”, but both bits are caused by a data error. Since the probability of inversion is very low, if the flag is “00”, it is determined that there is no degeneration regardless of the status of other items.
A case where the flag is “11” is shown in 52 to 55 in FIG. In this case, unlike the case shown in 51, the presence / absence of block degeneration is determined based on the physical address, status, and ECC determination result. If the read data contains an unacceptable data error in terms of the state of each item (54 or 55), the degeneration status is notified to the corresponding device after making a determination such as way degeneration or fatal error, respectively. Will do.
5 to 59 in FIG. 5 are cases where the flag is “01” or “10”. In this case, the presence / absence of block degeneration is determined based on the physical address, status, and ECC determination result, as in the cases shown in 52-55. If the read data includes an unacceptable data error in view of the state of each item (57, 58, and 59), the degeneration status for the corresponding device is determined after making a determination such as way degeneration or fatal error, respectively. Will be notified.
Returning to the description of FIG. 3, the storage unit 12 will be described. The storage unit 12 is a storage unit including a tag RAM 12a. The tag RAM 12a includes a static RAM (SRAM) and includes the ways and blocks shown in FIG. In the tag RAM 12a, tags corresponding to the number of CPUs that refer to the tag RAM control unit 10 are prepared, and a copy of the tag RAM in each CPU is held.
Next, a processing procedure of block degeneration processing using the above-described failure information will be described with reference to FIG. FIG. 6 is a flowchart showing the processing procedure of the block degeneration processing. As shown in the figure, when the SC (system controller) detects a block error (step S101), it issues a block degeneration request to the CPU (step S102). The CPU that has received this block reduction request determines whether or not the same block in all the ways is in a reduced state when it is assumed that the target block has been reduced (step S103).
If it is determined that the same block in all ways is not in a degenerated state (No in step S103), all data in the way including the block is written back to the main memory (step S104). A process of setting a block flag (see 42 in FIG. 4) is performed (step S105). Subsequently, the CPU issues a degeneration notification to the SC (step S106), and the SC that has received this degeneration notification executes block degeneration (step S107) and ends the process. If it is determined in step S103 that the same block in all ways is in a degenerated state (step S103, Yes), the CPU ends the process without performing the processes in and after step S104.
As described above, in this embodiment, when the write processing unit detects a block failure, the entry data to the tag RAM is predetermined data indicating that the data is being degenerated outside the ECC protection area and outside the ECC protection area. When the read processing unit reads data from the tag RAM block, the degeneration status determination unit considers data error to the predetermined data previously written by the write processing unit and is degenerating / degenerate It is configured to judge the degeneration status of none and to perform error judgment such as way degeneration and fatal error when necessary. That is, the number of bits used outside the ECC protection area can be minimized by using the error correction function by ECC by writing the failure information in the ECC protection area. Therefore, when performing block unit degeneration, degeneration information associated with block degeneration can be reduced.
(Supplementary note 1) A cache memory device having a way including a plurality of blocks in which each entry data is stored, and degenerate information writing for writing degenerate information indicating that the block is degenerated into the block And a degeneration status determination unit that determines a degeneration status of the block based on a read result of the degeneration information written by the degeneration information writing unit to the block. .
(Supplementary Note 2) The degeneration information writing means writes first degeneration information indicating that degeneration is out of the error correction protection area in the entry data and indicates that degeneration is also out of the error correction protection area. The cache memory device according to appendix 1, wherein second degenerate information is written.
(Additional remark 3) The said degeneracy information writing means writes the value which the data which should be stored in the said error correction protection area | region normally cannot be normally taken in as said 1st degeneration information, The appendix 2 characterized by the above-mentioned Cache memory device.
(Supplementary note 4) The cache memory device according to supplementary note 2 or 3, wherein the degeneration information writing means writes 2-bit information indicating that degeneration is being performed as the second degeneration information.
(Supplementary Note 5) The degeneration status determination unit is configured to reduce the block based on the read result of the first degeneration information, the error correction determination result for the first degeneration information, and the read result of the second degeneration information. The cache memory device according to appendix 2, wherein the situation is determined.
(Supplementary Note 6) The degeneration status determination step includes the block degeneration and the way based on the read result of the first degeneration information, the error correction determination result for the first degeneration information, and the read result of the second degeneration information. The cache memory device according to appendix 2, wherein either a degeneration or a fatal error is determined.
(Supplementary Note 7) A cache control method in a cache memory device having a way including a plurality of blocks in which each entry data is stored, wherein degeneration information indicating that the block is degenerated is written to the block A degeneration information writing step; and a degeneration status determination step of determining a degeneration status of the block based on a read result of the degeneration information written in the block by the degeneration information writing step. Cache control method.
(Supplementary Note 8) The degeneration information writing step writes first degeneration information indicating that degeneration is out of the error correction protection area in the entry data and indicates that degeneration is also out of the error correction protection area. 8. The cache control method according to appendix 7, wherein second degenerate information is written.
(Additional remark 9) The said degeneration information writing process writes the value which the data which should be stored in the said error correction protection area | region normally cannot be taken in as said 1st degeneration information normally. Cache control method.
(Supplementary note 10) The cache control method according to supplementary note 8 or 9, wherein the degeneration information writing step writes, as the second degeneration information, 2-bit information indicating that degeneration is in progress.
(Additional remark 11) The said degeneracy status determination process WHEREIN: Based on the read result of said 1st degeneration information, the error correction determination result about said 1st degeneration information, and the read result of said 2nd degeneration information, the degeneration of the said block The cache control method according to appendix 8, wherein the situation is determined.
(Additional remark 12) The said degeneracy situation determination process is a block degeneration, a way based on the read result of said 1st degeneration information, the error correction determination result about said 1st degeneration information, and the read result of said 2nd degeneration information. 9. The cache control method according to appendix 8, wherein either a degeneration or a fatal error is determined.
As described above, the cache control device and the cache control method according to the present invention are useful for reducing the storage area of degeneration information, and are particularly suitable for reducing the storage area of degeneration information in a cache memory that performs degeneration in units of blocks. .
In order to solve the above-described problems and achieve the object, a cache memory device having a way including a plurality of blocks in which each entry data is stored, wherein the degeneration information indicating that the blocks are degenerated Degeneration information writing means for writing to the block, and degeneration status determining means for determining the degeneration status of the block based on the read result of the degeneration information written by the degeneration information writing means for the block. obtain Bei.
Writes degeneration information indicating that block is degenerated with respect to this block, when reading this block, since it is configured to determine a degenerate status of the block based on the read result of the degeneration information written previously by storing the degeneration information in the entry data in the block, in the case of degeneracy of blocks, that Sosu the effect that it is possible to reduce the degeneration information associated with the block degeneracy.
In addition, the first degeneration information indicating that the degeneration is being performed is written in the error correction protection area of the entry data, and the second degeneration information indicating that the degeneration is being performed is also written outside the error correction protection area. Therefore, there is an effect that the size of the degenerate information outside the error correction protection area can be minimized by using the error correction function in the error correction protection area.
In addition, since data that should normally be stored in the error correction protection area is written as the first degenerate information, a value that cannot normally be written is written. Thus, error correction can be performed by using each item in the error correction protection area as it is. There is an effect that it is not necessary to secure a new area for storing degenerate information in the protection area.
In addition, since it is configured to write 2-bit information indicating that degeneration is in progress as the second degeneration information, it is possible to suppress the necessary degeneration information storage area for each block by using the minimum degeneration information. Can do. Therefore, particularly in a cache memory including a large number of blocks, there is an effect that it is possible to greatly reduce the area for storing degenerate information.
A cache memory device having a way including a plurality of blocks in which each entry data is stored,
Degeneration information writing means for writing degeneration information indicating that the block is degenerated into the block;
A cache memory device, comprising: a degeneration status determining unit that determines a degeneration status of the block based on a read result of the degeneration information written by the degeneration information writing unit to the block.
The degeneration information writing means includes:
Write first degeneration information indicating that degeneration is in progress in the error correction protection area in the entry data, and write second degeneration information indicating that degeneration is in progress outside the error correction protection area. The cache memory device according to claim 1.
3. The cache memory device according to claim 2, wherein a value that cannot normally be taken by the data that should be stored in the error correction protection area is written as the first degeneration information.
4. The cache memory device according to claim 2, wherein 2-bit information indicating that degeneration is in progress is written as the second degeneration information.
The degeneration status determining means includes
The degeneration status of the block is determined based on a read result of the first degenerate information, an error correction determination result for the first degenerate information, and a read result of the second degenerate information. 3. The cache memory device according to 2.
The degeneration status determination step includes:
Based on the read result of the first degenerate information, the error correction determination result for the first degenerate information, and the read result of the second degenerate information, a determination is made of block degeneration, way degeneration, or a fatal error. The cache memory device according to claim 2, wherein the cache memory device is performed.
A cache control method in a cache memory device having a way including a plurality of blocks in which each entry data is stored,
A degeneration information writing step of writing degeneration information indicating that the block is degenerated into the block;
A degeneration status determination step of determining a degeneration status of the block based on a read result of the degeneration information written in the degeneration information writing step for the block.
The degeneration information writing step includes:
Write first degeneration information indicating that degeneration is in progress in the error correction protection area in the entry data, and write second degeneration information indicating that degeneration is in progress outside the error correction protection area. The cache control method according to claim 7.
9. The cache control method according to claim 8, wherein a value that cannot normally be stored in the error correction protection area is written as the first degeneration information.
10. The cache control method according to claim 8, wherein 2-bit information indicating that degeneration is in progress is written as the second degeneration information.
The degeneration status of the block is determined based on a read result of the first degenerate information, an error correction determination result for the first degenerate information, and a read result of the second degenerate information. 9. The cache control method according to 8.
Based on the read result of the first degenerate information, the error correction determination result for the first degenerate information, and the read result of the second degenerate information, a determination is made of block degeneration, way degeneration, or a fatal error. The cache control method according to claim 8, wherein the cache control method is performed.
JP2008501571A 2006-02-27 2006-02-27 Cache control device and cache control method Expired - Fee Related JP4332205B2 (en)
PCT/JP2006/303589 WO2007097019A1 (en) 2006-02-27 2006-02-27 Cache controller and cache control method
JPWO2007097019A1 true JPWO2007097019A1 (en) 2009-07-09
JP4332205B2 JP4332205B2 (en) 2009-09-16
ID=38437079
JP2008501571A Expired - Fee Related JP4332205B2 (en) 2006-02-27 2006-02-27 Cache control device and cache control method
US (1) US8060698B2 (en)
JP (1) JP4332205B2 (en)
WO (1) WO2007097019A1 (en)
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JP4332205B2 (en) 2009-09-16
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