Source: http://www.google.com/patents/US6794224?dq=3984803
Timestamp: 2016-10-23 22:52:53
Document Index: 398265864

Matched Legal Cases: ['application No. 09', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 10']

Patent US6794224 - Semiconductor device including leads in communication with contact pads ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method for forming semiconductor device packages that include one or more semiconductor dice, leads in communication with bond pads of each die, and a protective layer, or package, over at least portions of the active surface of each die, and includes electrically exposing the leads through the protective...http://www.google.com/patents/US6794224?utm_source=gb-gplus-sharePatent US6794224 - Semiconductor device including leads in communication with contact pads thereof and a stereolithographically fabricated package substantially encapsulating the leads and methods for fabricating the sameAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6794224 B2Publication typeGrantApplication numberUS 10/080,336Publication dateSep 21, 2004Filing dateFeb 21, 2002Priority dateAug 31, 2000Fee statusPaidAlso published asUS6762502, US20020098623, US20040256740Publication number080336, 10080336, US 6794224 B2, US 6794224B2, US-B2-6794224, US6794224 B2, US6794224B2InventorsSalman AkramOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (84), Non-Patent Citations (12), Referenced by (11), Classifications (40), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device including leads in communication with contact pads thereof and a stereolithographically fabricated package substantially encapsulating the leads and methods for fabricating the same
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2003Grigg Ford B.Stereolithographically marked semiconductor devices and methodsUS20030089999Dec 11, 2002May 15, 2003Salman AkramSemiconductor devices having stereolithographically fabricated protective layers thereon through which contact pads are exposed and assemblies including the sameUS20030092220Dec 11, 2002May 15, 2003Salman AkramStereolithographic methods of fabricating semiconductor devices having protective layers thereon through which contact pads are exposedUS20030093173Nov 12, 2002May 15, 2003Farnworth Warren M.Stereolithographic method and apparatus for packaging electronic componentsUS20030102566Jan 8, 2003Jun 5, 2003Farnworth Warren M.Stereolithographic method for applying materials to electronic component substrates and resulting structuresUS20030129787Jan 28, 2003Jul 10, 2003Farnworth Warren M.Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic 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Paper, 8 pages, General Electric Company, <http://www.geplastics.com/electromaterials/getekconnect/pdf/photoimagable_solder_mask_112901.pdf>.4U.S. patent application No. 09/589,841, filed Jun. 8, 2000, entitled Stereolithographic Methods For Forming A Protective Layer on a Semiconductor Device Substrate and Substrates Including Protective Layers So Formed, inventer Farnworth et al.5U.S. patent application No. 10/370,755,filed Feb. 20, 2003, entitled Chip Scale Package Structures and Method of Forming Conductive Bumps Thereon, inventor Warren M. Farnworth.6U.S. patent application No. 10/455,091, filed Jun. 5, 2003, entitled Methods for Stereolithographic Processing of Components and Assemblies, inventor Warren M. Farnworth.7U.S. patent application No. 10/608,749 filed Jun. 26, 2003, entitled Methods for Labeling Semiconductor Device Components, inventor Grigg et al.8U.S. patent application No. 10/619,918, filed Jul. 15, 2003, entitled Stereolithographic Methods for Fabricating Hermetic Semiconductor Device Packages and Semiconductor Devices Including Stereolithographically Fabricated Hermetic Packages inventor Warren M. Farnworth.9U.S. patent application No. 10/672,098 filed Sep. 26, 2003, entitled Apparatus and Methods for use in Stereolithographic Processing of Components and Assemblies; inventor Warren M. Farnworth.10U.S. patent application No. 10/690,417 filed Oct. 20, 2003, entitled Methods of Coating and Singulating Wafers and Chip Scale Packages Formed Therefrom inventor Farnworth et al.11Webpage, Objet Prototyping the Future, How it Works, 2 pages.12Webpage, Objet Prototyping the Future, Objet FullCure700 Series, 1 page.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7084013Dec 15, 2004Aug 1, 2006Micron Technology, Inc.Methods for forming protective layers on semiconductor device substratesUS7166925Mar 1, 2005Jan 23, 2007Micron Technology, Inc.Semiconductor devices having stereolithographically fabricated protective layers thereon through which contact pads are exposed and assemblies including the sameUS8129839Jul 19, 2005Mar 6, 2012Micron Technology, Inc.Electronic device package structuresUS20050101158 *Dec 15, 2004May 12, 2005Farnworth Warren M.Methods for forming protective layers on semiconductor device substratesUS20050156331 *Mar 1, 2005Jul 21, 2005Salman AkramSemiconductor devices having stereolithographically fabricated protective layers thereon through which contact pads are exposed and assemblies including the sameUS20050251282 *Jun 17, 2005Nov 10, 2005Farnworth Warren MMethod and apparatus for forming structures proximate to workpiecesUS20050253261 *Jul 19, 2005Nov 17, 2005Farnworth Warren MElectronic device package structuresUS20060022320 *Jul 26, 2005Feb 2, 2006Sharp Kabushiki KaishaSemiconductor device and manufacturing method thereofUS20060081966 *Nov 17, 2005Apr 20, 2006Farnworth Warren MChip-scale packagesUS20060197235 *Apr 27, 2006Sep 7, 2006Farnworth Warren MElectronic device components including protective layers on surfaces thereofUS20070117277 *Jan 19, 2007May 24, 2007Salman AkramMethods for fabricating protective layers on semiconductor device components* Cited by examinerClassifications U.S. Classification438/125, 438/111, 438/127, 257/E23.039, 257/E23.021, 257/E21.502, 264/401International ClassificationH01L21/56, H01L23/485, H01L23/495, H01L23/31Cooperative ClassificationH01L2224/4824, H01L2224/05554, H01L2224/13, H01L2224/85399, H01L2224/45099, H01L2224/05599, H01L2924/00014, H01L2924/12042, H01L2924/351, H01L2924/01006, H01L2924/01033, H01L23/4951, H01L2924/01082, H01L2224/13099, H01L2924/01039, H01L23/3114, H01L24/10, H01L2924/014, H01L2924/15311, H01L21/56, H01L2924/14, H01L2224/73215, H01L2224/48091, H01L24/13, H01L24/48European ClassificationH01L24/10, H01L23/31H1, H01L23/495A4, H01L21/56Legal EventsDateCodeEventDescriptionNov 7, 2006CCCertificate of correctionFeb 21, 2008FPAYFee paymentYear of fee payment: 4Sep 22, 2011FPAYFee paymentYear of fee payment: 8Apr 29, 2016REMIMaintenance fee reminder mailedRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services