Source: http://www.google.com/patents/US6658154?ie=ISO-8859-1&dq=7143430
Timestamp: 2014-03-09 06:54:12
Document Index: 513229365

Matched Legal Cases: ['art 12', 'arts 21', 'art 12', 'arts 21', 'art 36', 'art 12', 'art 30', 'art 22', 'art 30', 'art 22', 'art 22', 'art 30', 'art 22', 'art 30', 'art 22', 'art 22', 'art 22', 'art 22', 'art 12']

Patent US6658154 - Method and device for decoding moving picture - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA memory control part 12 cyclically assigns time slots to buffer memory parts 21 to 25 respectively and in each time slot, controls access between the corresponding buffer memory part and a synchronous RAM 11. A time slot is determined while assuming the worst case where access to the synchronous RAM...http://www.google.com/patents/US6658154?utm_source=gb-gplus-sharePatent US6658154 - Method and device for decoding moving pictureAdvanced Patent SearchPublication numberUS6658154 B2Publication typeGrantApplication numberUS 09/365,865Publication dateDec 2, 2003Filing dateAug 3, 1999Priority dateAug 7, 1998Fee statusPaidAlso published asDE19935604A1, DE19935604B4, US20030169929Publication number09365865, 365865, US 6658154 B2, US 6658154B2, US-B2-6658154, US6658154 B2, US6658154B2InventorsKiyoshi Kohiyama, Yukio Otobe, Hidenaga Takahashi, Koji YoshitomiOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (4), Classifications (28), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod and device for decoding moving pictureUS 6658154 B2Abstract A memory control part 12 cyclically assigns time slots to buffer memory parts 21 to 25 respectively and in each time slot, controls access between the corresponding buffer memory part and a synchronous RAM 11. A time slot is determined while assuming the worst case where access to the synchronous RAM is the severest. Time slot groups of [(the number of pixels on one horizontal scanning line)/256] in number are generated in an imaginary one horizontal scanning period, where [ ] denotes an integer portion of the number in the parentheses. For a buffer memory 22 whose data volume changes depending on a compression factor, a time slot ending point may be made variable, or a time slot may be generated by interrupt as an exception.
SUMMARY OF THE INVENTION Accordingly, it is an object to provide a method and device for decoding a moving picture which are good in access efficiency to a RAM.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram showing a structure of a device for decoding a moving picture and a system demultiplexing part of a first embodiment in accordance with the present invention;
First Embodiment FIG. 1 shows a schematic structure of a device 10 for decoding a moving picture and a system demultiplexing part of the first embodiment in accordance with the present invention.
The multiplexed bit stream is provided by way of a shift register 41 to a multiplexer 42. A parallel output of the shift register 41 is compared with a user data identification pattern 44 by a separation control circuit 43 and an coincide signal EQ is provided to a control input of the multiplexer 42 from the separation control circuit 43. The number of bits of the shift register 41 is, for example, a total bit number of a series of a �packet start code,� a �stream ID� and a �packet length.� A packet start code and a stream ID of user data are provided from the user data identification pattern 44. The separation control circuit 43 comprises a comparator (not shown), a user data finish judgment counter 431 and a flip-flop 432 which outputs a coincide signal EQ.
In FIG. 1, the overall control part 36 generates a continuous system clock CLK based on a non-continuous system time clock STC, further generates an imaginary horizontal synchronizing signal VHSYNC (in decoding processing, since the VHSYNC has no relation with a horizontal synchronizing signal of display, the term �imaginary� precedes �horizontal synchronizing signal�) by frequency division of the system clock CLK, still further generates an imaginary vertical synchronizing signal VHSYNC by frequency division of the imaginary horizontal synchronizing signal VHSYNC and provides the memory control part 12 with the resulted signals for generation of time slots.
(1) Determining Method 1 The worst case of a data transfer volume to the variable length decoding part 30 from the buffer memory part 22 is as follows according to the MPEG standard.
9,126 bits�2+4,608 bits�43=216,576 bits. Accordingly, the average bit number per one macroblock in this case is 219,576/45≈4,813 bits.
9,216 bits�4−4,813 bits�3=22,425 bits. If the variable length decoding part 30 processes 3 macroblocks (=9,126 bits�3 times) in 3 macroblock processing period in the worst case and supplements the buffer memory part 22 with 4,813 bits�3 times during the processing time, data of
22,425−9,216�3+4,813�3=9,216 bits remain in the buffer memory part 22 at the start of a next macroblock processing period. The variable length decoding part 30 processes 9,216 bits in the next one macroblock processing period and the buffer memory part 22 is supplemented with 4,813 bits. Therefore, the variable length decoding part 30 can process 4,608 bits in a still next macroblock processing period, and thereby the worst case can be dealt with.
(2) Determining Method 2 If the buffer memory part 22 is supplemented with 9,216 bits in one time slot by widening a time slot width or using a RAM 11 with a high access speed, a necessary capacity of the buffer memory part 22 is 9,216 bits, which is smaller than in the above case.
(3) Determining Method 3 Further, according to the MPEG standard, the maximum number of bits per one picture is 1.75 Mb. When one picture is 675 macroblocks, the average number of bits per one macroblock is 1.75 Mb/675≈2,719 bits. Therefore, it can be allowed that the buffer memory part 22 is supplemented with 2,719 in one time slot. In this case, a necessary storage capacity of the buffer memory part 22 is clearly larger than in the case of (1).
Second Embodiment FIG. 9 shows a time slot and access request signals of the second embodiment in accordance with the present invention, corresponding to FIG. 7(A).
Third Embodiment FIG. 10 is an illustration showing a time slot sequence of a third embodiment in accordance with the present invention, corresponding to FIG. 7(A).
Fourth Embodiment FIG. 11 is an illustration showing a time slot sequence of the fourth embodiment in accordance with the present invention, corresponding to FIG. 10.
Fifth Embodiment FIG. 12 shows a memory control part 12A of the fifth embodiment in accordance with the present invention.
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