Source: http://www.google.com/patents/US7879675?dq=7,346,539
Timestamp: 2014-12-20 16:34:00
Document Index: 366566194

Matched Legal Cases: ['Application No. 094136197', 'Application No. 10', 'Application No. 05711376', 'Application No. 03817697', 'Application No. 112006001735', 'Application No. 11', 'Application No. 200680023301', 'Application No. 03817699', 'Application No. 2006', 'Application No. 200580007279', 'Application No. 95122087', 'Application No. 95122087', 'Application No. 95123858', 'Application No. 95123858', 'Application No. 95123858', 'Application No. 95135820', 'Application No. 95135820', 'Application No. 95135820', 'Application No. 200680021817', 'Application No. 200580032314', 'Application No. 200580032314', 'Application No. 2005070131', 'Application No. 200604766']

Patent US7879675 - Field effect transistor with metal source/drain regions - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent...http://www.google.com/patents/US7879675?utm_source=gb-gplus-sharePatent US7879675 - Field effect transistor with metal source/drain regionsAdvanced Patent SearchPublication numberUS7879675 B2Publication typeGrantApplication numberUS 12/114,227Publication dateFeb 1, 2011Filing dateMay 2, 2008Priority dateMar 14, 2005Also published asUS20060202266, US20090325350Publication number114227, 12114227, US 7879675 B2, US 7879675B2, US-B2-7879675, US7879675 B2, US7879675B2InventorsMarko Radosavljevic, Suman Datta, Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Amian Majumdar, Robert S. ChauOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (124), Referenced by (3), Classifications (21) External Links: USPTO, USPTO Assignment, EspacenetField effect transistor with metal source/drain regionsUS 7879675 B2Abstract A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional of U.S. patent application Ser. No. 11/080,765, filed Mar. 14, 2005, now abandoned (U.S. Patent Application Publication No. US 2006-0202266), published Sep. 14, 2006, the entire contents of which are hereby incorporated by reference herein.
In order to increase the performance of modern integrated circuits, such as microprocessors, silicon on insulator (SOI) transistors have been proposed. Silicon on insulator (SOI) transistors have an advantage in that they can be operated in a fully depleted manner. Fully depleted transistors have an advantage of an ideal subthreshold gradient for optimized on-current/off-current ratios. An example of an proposed SOI transistor which can be operated in a fully depleted manner is a tri-gate transistor 100, such as illustrated in FIG. 1. Tri-gate transistor 100 includes a silicon body 104 formed on insulating substrate 102 having a buried oxide layer 103 formed on a monocrystalline silicon substrate 105. A gate dielectric layer 106 is formed on the top and sidewalls of silicon body 104 as shown in FIG. 1. A gate electrode 108 is formed on the gate dielectric layer and surrounds the body 104 on three sides essentially providing a transistor 100 having three gate electrodes (G1, G2, G3) one on each side of silicon body 104 and one on the top surface of the silicon body 104. A source region 110 and a drain region 112 are formed in the silicon body 104 on opposite sides of the gate electrode 108 as shown in FIG. 1. An advantage of the tri-gate transistor 100 is that it exhibits good short channel effects (SCE). One reason tri-gate transistor 100 has good short channel effects is that the nonplanarity of the device places the gate electrode 108 in such a way as to surround the active channel region. Unfortunately, as tri-gate devices become increasingly smaller, the external contact resistance (Rext) is increasingly becoming more significant portion of the overall device resistance. This is particularly problematic in three dimensional transistors (formed both by etching of Si wafer, or by chemical synthesis of nanowires), where the source region 110 and drain region 112 are formed in the narrow silicon body 104. Unfortunately, standard techniques for reducing contact resistance, such as by forming �raised� source/drain regions where additional epitaxial silicon is formed on the silicon body 104 is difficult to implement in nonplanar transistors. For example, it is difficult to grow �raised� epitaxial source/drain regions on the sides of the silicon body 104. For these reasons the devices suffer from high Rext and degraded performance.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an illustration of a cross-sectional view of a nonplanar transistor.
DETAILED DESCRIPTION OF THE PRESENT INVENTION The present invention is a field effect transistor with metal source/drain regions and its method of fabrication. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. In other instances, well known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention.
A source region 212 and a drain region 214 are formed in the semiconductor body 204 on opposite sides of the gate electrode 208 as shown in FIGS. 2A and 2B. The source region 212 includes a metal portion 216 and a doped semiconductor portion 218 and drain region 214 includes a metal portion 220 and a doped semiconductor portion 222. The portion of the semiconductor body 204 located between the source region 212 and drain region 214 defines a channel region 210 of transistor 200. The doped semiconductor portions 218 and 222 contact the channel region 210 of the semiconductor device. In an embodiment of the present invention, the metal portions 216 and 220 of the source and drain regions 212 and 214, respectively, extend as close as possible to the channel region 210 without actually contacting the channel region. In an embodiment of the present invention, the metal portion 216 and 220 are offset from the channel region 210 by doped semiconductor portions 218 and 222 by approximately 5 nanometers. In an embodiment of the present invention, the doped semiconductor regions have a doping concentration of between 1e20 and 1e21/cm3. In an embodiment of the present invention, the doped semiconductor portions 218 and 222 are doped to the opposite conductivity type than the dopant conductivity of the channel region 210 of the semiconductor body 204. In an embodiment of the present invention, metal regions 216 and 220 and the doped semiconductor regions 218 and 222 of the source and drain regions 212 and 214 extend completely through the semiconductor body 204 and contact the insulating substrate 202. In an embodiment of the present invention, the metal portions 216 and 220 are formed from a high conductivity metal. In an embodiment of the present invention, the metal portion 216 for the source region 212 and the metal portion 220 of the drain region 214 are formed from a material which forms favorable �Schottky barrier� properties with doped semiconductor portions 218 and 222 of the source and drain regions. In an embodiment of the present invention, when semiconductor portions 218 and 222 are silicon the metal portion may be platinum. In an embodiment of the present invention, when semiconductor 218 and 222 are carbon nanotubes the metal portions may be palladium. In an embodiment of the present invention, when forming a PFET (a p type field effect transistor) where the doped portions of source and drain regions are doped to a p type conductivity and the majority carriers are holes, the metal portions 216 and 220 of the source region 212 and drain region 214 can be a metal, such as but not limited to palladium and platinum. In an embodiment of the present invention, when forming NFET (an n type field effect transistor) where the doped source and drain regions are doped to an n type conductivity and the majority carriers are electrons, the metal portions of the source and drain region can be fabricated from a metal, such as but not limited to aluminum and titanium. It is to be appreciated that the source region 212 and drain region 214 can be collectively referred to as a pair of source/drain regions.
A method of fabricating a field effect transistor with source and drain regions having metal portions in accordance with embodiments of the present invention is illustrated in FIGS. 4A-4L. The fabrication of the field effect transistor begins with a substrate 402. A silicon or semiconductor film 408 is formed on substrate 402 as shown in FIG. 4A. In an embodiment of the present invention, the substrate 402 is an insulating substrate such as shown in FIG. 4A. In an embodiment of the present invention, insulating substrate 402 includes a lower monocrystalline silicon substrate 404 and a top insulating layer 406, such as a silicon dioxide film or silicon nitride film. Insulating layer 406 isolates semiconductor film 408 from substrate 404 and in an embodiment is formed to a thickness between 200-2000 Å. Insulating layer 406 is sometimes referred to as �a buried oxide� layer. When a silicon or semiconductor film 408 is formed on an insulating substrate 402, a silicon or semiconductor-on-insulator (SOI) substrate is created. In other embodiments of the present invention, substrate 402 can be a semiconductor substrate, such as but not limited to a silicon monocrystalline substrate and a gallium arsenide substrate. Although semiconductor film 408 is ideally a silicon film, in other embodiments it can be other types of semiconductor films, such as but not limited to germanium, silicon germanium, gallium arsenide, InSb, GaP, GaSb as well as carbon nanotubes.
In an embodiment of the present invention, semiconductor film 408 is an intrinsic (i.e., undoped) silicon film. In other embodiments, semiconductor film 408 is doped to a p type or n type conductivity with a concentration level between 1�1016 to 1�1019 atoms/cm3. Semiconductor film 408 can be insitu doped (i.e., doped while it is deposited) or doped after it is formed on substrate 402 by, for example, ion implantation. Doping after formation enables both PFET and NFET devices to be fabricated easily on the same insulating substrate. The doping level of the semiconductor film 408 determines the doping level of the channel region of the device. In an embodiment of the present invention, semiconductor film 408 is formed to a thickness which is approximately equal to the height desired for the subsequently formed semiconductor body or bodies of the fabricated transistor. In embodiments of the present invention, semiconductor film 408 has a thickness or height 409 of less than 30 nanometers and ideally less than 20 nanometers. In an embodiment of the present invention, semiconductor film 408 is formed to a thickness approximately equal to the gate �length� desired of the fabricated transistor. In an embodiment of the present invention, semiconductor film 408 is formed thicker than the desired gate length of the device. In an embodiment of the present invention, a semiconductor film 408 is formed to a thickness which will enable the fabricated transistor to be operated in a fully depleted manner for a desired gate length (Lg).
Semiconductor film 408 can be formed on insulating substrate 402 in any well known method. In one method of forming a silicon-on-insulator substrate, known as the �SIMOX� technique, oxygen atoms are implanted at a high dose into a single crystalline silicon substrate and then annealed to form the buried oxide 406 within the substrate. The portion of the single crystalline silicon substrate above the buried oxide becomes a silicon film. In another method an epitaxial silicon film transfer technique which is generally referred to as bonded SOI may be utilized to form a SOI substrate.
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