Source: https://patents.justia.com/patent/9379002
Timestamp: 2019-09-23 09:01:23
Document Index: 92490294

Matched Legal Cases: ['§119', 'Application No. 10', 'art 410', 'art 410', 'art 410', 'art 410', 'art 410', 'art 410']

US Patent for Semiconductor device having air-gap Patent (Patent # 9,379,002 issued June 28, 2016) - Justia Patents Search
Justia Patents Integrated Circuit Structure With Electrically Isolated ComponentsUS Patent for Semiconductor device having air-gap Patent (Patent # 9,379,002)
A claim of priority under 35 U.S.C. §119 is made to Korean Patent Application No. 10-2014-0031080 filed on Mar. 17, 2014, the disclosure of which is hereby incorporated by reference in its entirety.
FIG. 2C is a plan view taken along the line III-III′ of FIGS. 2A and 2B according to an embodiment;
FIG. 1 is a layout view showing a semiconductor device in accordance with an embodiment of the inventive concept. FIG. 2A is a cross-sectional view taken along line I-I′ of FIG. 1. FIG. 2B is a cross-sectional view taken along line II-II′ of FIG. 1. FIG. 2C is a plan view taken along line III-III′ of FIGS. 2A and 2B.
The second inner bit line spacer 410b may be located on a second side surface 300S2 of the corresponding bit line structure 300. The second side surface 300S2 of each bit line structure 300 may be opposite the first side surface 300S1 of the corresponding bit line structure 300.
The second inner bit line spacer 410b may extend along the second side surface 300S2 of the corresponding bit line structure 300. The second inner bit line spacer 410b may cover the upper surface of the semiconductor substrate 100 disposed near the second side surface 300S2 of the corresponding bit line structure 300. For example, the shape of the second inner bit line spacer 410b may have a reverse ‘L’ shape. The second inner bit line spacer 410b may include a vertical part like as a first part 410p1 of the first inner bit line spacer 410a, and a horizontal part like as a second part 410p2 of the first inner bit line spacer 410a.
The first areas 430r1 and the second areas 430r2 of the first block bit line spacer 430a may be spaced apart from the first part 410p1 of the first inner bit line spacer 410a in the X-axis direction. A separation distance between the first part 410p1 of the first inner bit line spacer 410a and the second areas 430r2 of the first block bit line spacer 430a in the X-axis direction may be greater than a separation distance between the first part 410p1 of the first inner bit line spacer 410a and the first areas 430r1 of the first block bit line spacer 430a in the X-axis direction. For example, a profile of a first side surface 430S1 of the first block bit line spacer 430a facing the first part 410p1 of the first inner bit line spacer 410a may have an uneven shape.
The storage contact plugs 600 may be in direct contact with the bit line spacers 400. The storage contact plugs 600 may be in direct contact with the plug isolation patterns 500. The storage contact plugs 600 may be defined by the bit line spacers 400 and the plug isolation patterns 500.
Each of the storage contact plugs 600 may include a lower plug pad 610, an intermediate plug pattern 620, a plug bather pattern 630, and an upper contact plug 640.
The plug barrier pattern 630 may be located on the intermediate plug pattern 620. The plug barrier pattern 630 may extend along adjacent bit line spacers 400. For example, the plug bather pattern 630 may extend to an upper surface of a corresponding bit line structure 300 along the second side surface 300S2 of the bit line structures 300.
The interlayer insulating layer 700 may be located on the second side surface 300S2 of each bit line structure 300. The highest level of the second side surface 300S2 of each bit line structure 300 may be the same as the lowest level of the interlayer insulating layer 700. The highest level of the second side surface 300S2 of each bit line structure 300 may be lower than the highest level of the first side surface 300S1 of a corresponding bit line structure 300.
In the method of forming a semiconductor device in accordance with the embodiment of the inventive concept, air-gaps Ag may be formed on side surfaces 300S1 and 300S2 of each second preliminary bit line structure 302 in the process of forming the block spacer insulating layer 431. In the method of forming a semiconductor device in accordance with the embodiment of the inventive concept, the air-gaps Ag may be formed under the outer bit line spacers 420 in contact with the inner spacer pattern 412. In the method of forming a semiconductor device in accordance with the embodiment of the inventive concept, the air-gaps Ag may be formed to be symmetrical at first side surfaces 300S1 and second side surfaces 300S2 of the second preliminary bit line structures 302. Thus, in the method of forming a semiconductor device in accordance with the embodiment of the inventive concept, upper portions of the air-gaps Ag may be fully covered by the outer bit line spacers 420. Accordingly, in the method of forming a semiconductor device in accordance with the embodiment of the inventive concept, inflow of a component formed by a subsequent process into the air-gaps Ag may be prevented.
The process of forming the plug bather layer 631 may include a process of forming a metal nitride layer on the semiconductor substrate 100 including the intermediate plug pattern 620.
Referring to FIGS. 29A and 29B, the method of forming a semiconductor device in accordance with the embodiment of the inventive concept may include a process of forming an upper conductive layer 641 on the plug bather layer 631.
a bit line structure extending along an upper part of the semiconductor substrate and having oppositely facing first and second side surfaces;
an outer bit line spacer disposed on the first side surface of the bit line structure;
an inner bit line spacer including a first part interposed between the bit line structure and the outer bit line spacer, and a second part interposed between the semiconductor substrate and the outer bit line spacer; and
a block bit line spacer interposed between the outer bit line spacer and the second part of the inner bit line spacer, and
wherein the block bit line spacer has a planar horizontal upper surface, and a planar horizontal lower surface such that the upper and lower surfaces of the block bit line spacer are parallel, and
the outer bit line spacer, the inner bit line spacer, and the block bit line spacer delimit a first air-gap constituting a void between the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.
2. The semiconductor device of claim 1, wherein the block bit line spacer has a first side surface facing and spaced from the first part of the inner bit line spacer, and a second side surface, the first and second sides surfaces facing in opposite directions, and each of the first and second side surfaces extending between the upper and lower surfaces of the block bit line spacer, and
a width of the block bit line spacer, as taken in a horizontal direction between the first and second side surfaces of the bit line spacer beneath a lower surface of the outer bit line spacer, is smaller than a thickness of the outer bit line spacer as taken in said horizontal direction along the lower surface of the outer bit line spacer such that the first side surface of the bit line spacer delimits the air gap with the inner and outer bit line spacers.
3. The semiconductor device of claim 1, wherein the block bit line spacer includes a first side surface facing the first part of the inner bit line spacer, and a second side surface opposite the first side surface, and
wherein the second side surface of the block bit line spacer is vertically aligned with a side surface of the outer bit line spacer.
4. The semiconductor device of claim 3, wherein a side surface of the second part of the inner bit line spacer is vertically aligned with the second side surface of the block bit line spacer.
5. The semiconductor device of claim 1, wherein a thickness of the block bit line spacer, as taken in a vertical direction between the upper and lower surfaces of the bit line spacer, is the same as a width of the first air-gap as taken in a horizontal direction between the outer bit line spacer and the first part of the inner bit line spacer.
6. The semiconductor device of claim 5, wherein the upper surface of the block bit line spacer is in contact with a lower surface of the outer bit line spacer, and the lower surface of the block bit line spacer is in contact with the second part of the inner bit line spacer.
7. The semiconductor device of claim 1, wherein a second air-gap, constituting a void, is delimited on the second side surface of the bit line structure, and
wherein the highest level of the second air-gap is the same as the highest level of the first air-gap.
8. The semiconductor device of claim 7, wherein the shape of the second air-gap is symmetrical to the shape of the first air-gap with respect to the bit line structure.
9. The semiconductor device of claim 7, wherein the highest level of the first air-gap is lower than the highest level of the bit line structure.
10. The semiconductor device of claim 9, wherein the outer bit line spacer is in contact with the first part of the inner bit line spacer at the first side surface of the bit line structure, and
wherein the lowest level of an interface between the outer bit line spacer and the first part of the inner bit line spacer is the same as the highest level of the first air-gap.
11. The semiconductor device of claim 1, wherein the bit line structure includes a lower bit line barrier pattern, an upper bit line barrier pattern, a lower bit line electrode, a DC plug, an intermediate bit line pattern, an upper bit line electrode and a bit line capping pattern.
12. The semiconductor device of claim 1, wherein the bit line structure includes at least one barrier pattern disposed on an upper surface of the semiconductor substrate, a bit line electrode extending longitudinally in a first horizontal direction on the at least one barrier pattern, and a direct contact (DC) plug integral with and extending from a lower part of the bit line electrode into the semiconductor substrate to a level below that of the at least one barrier pattern, and
the second part of the inner bit line spacer is interposed between the at least one barrier pattern and the block bit line spacer.
13. The semiconductor device of claim 1, wherein the block bit line spacer has a rectangular cross section in a vertical plane.
wherein the bit line structure includes at least one barrier pattern disposed on an upper surface of the semiconductor substrate, a bit line electrode extending longitudinally in a first horizontal direction on the at least one barrier pattern, and a direct contact (DC) plug integral with and extending from a lower part of the bit line electrode into the semiconductor substrate to a level below that of the at least one barrier pattern,
the second part of the inner bit line spacer is vertically interposed between the at least one barrier pattern and the block bit line spacer, and
15. The semiconductor device of claim 14, wherein the block bit line spacer has a first side surface facing and spaced from the first part of the inner bit line spacer, and a second side surface, the first and second sides surfaces facing in opposite directions, and each of the first and second side surfaces extending between the upper and lower surfaces of the block bit line spacer, and
16. The semiconductor device of claim 14, wherein a thickness of the block bit line spacer, as taken in a vertical direction between the upper and lower surfaces of the bit line spacer, is the same as width of the first air-gap as taken in a horizontal direction between the outer bit line spacer and the first part of the inner bit line spacer.
17. The semiconductor device of claim 14, wherein the block bit line spacer has a rectangular cross section in a vertical plane.
wherein the block bit line spacer has a rectangular cross section in a vertical plane, and
19. The semiconductor device of claim 18, wherein the block bit line spacer has a first side surface facing and spaced from the first part of the inner bit line spacer, and a second side surface, the first and second sides surfaces facing in opposite directions, and each of the first and second side surfaces extending between the upper and lower surfaces of the block bit line spacer, and
20. The semiconductor device of claim 18, wherein a thickness of the block bit line spacer, as taken in a vertical direction between the upper and lower surfaces of the bit line spacer, is the same as width of the first air-gap as taken in a horizontal direction between the outer bit line spacer and the first part of the inner bit line spacer.
20120168899 July 5, 2012 Kim et al.
10-2013-0022872 March 2013 KR
Patent Publication Number: 20150262625
Application Number: 14/554,113
International Classification: H01L 21/00 (20060101); H01L 21/764 (20060101); H01L 27/108 (20060101); H01L 23/532 (20060101); G11C 7/18 (20060101);