Source: http://www.google.com/patents/US5166081?dq=6,073,142
Timestamp: 2014-09-15 02:23:52
Document Index: 167048423

Matched Legal Cases: ['arts 1', 'art 5', 'art 6', 'art 6', 'art 6', 'art 5', 'art 5', 'art 5']

Patent US5166081 - Method of producing a bipolar transistor - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA dummy emitter is formed in the portion corresponding to an emitter region, on a multiplayer structural material comprising layers for forming emitter, base and collector, and using it as mask, an external base region is exposed by etching, and a projection of emitter region is formed, while the dummy...http://www.google.com/patents/US5166081?utm_source=gb-gplus-sharePatent US5166081 - Method of producing a bipolar transistorAdvanced Patent SearchPublication numberUS5166081 APublication typeGrantApplication numberUS 07/549,589Publication dateNov 24, 1992Filing dateJun 27, 1990Priority dateApr 1, 1986Fee statusPaidAlso published asDE3751972D1, DE3751972T2, DE3788527D1, DE3788527T2, EP0240307A2, EP0240307A3, EP0240307B1, EP0558100A2, EP0558100A3, EP0558100B1, US4965650Publication number07549589, 549589, US 5166081 A, US 5166081A, US-A-5166081, US5166081 A, US5166081AInventorsMasanori Inada, Kazuo Eda, Yorito Ota, Atsushi Nakagawa, Manabu YanagiharaOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (17), Classifications (21), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod of producing a bipolar transistorUS 5166081 AAbstract A dummy emitter is formed in the portion corresponding to an emitter region, on a multiplayer structural material comprising layers for forming emitter, base and collector, and using it as mask, an external base region is exposed by etching, and a projection of emitter region is formed, while the dummy emitter is inverted into an emitter electrode, thereby forming an emitter electrode metal layer to cover the whole upper surface of the emitter. Using thus formed emitter electrode metal layer, a base electrode metal layer is formed, by self-alignment, adjacently to the emitter. In other method, on a multilayer structural material, impurities are introduced outside the portion corresponding to the base region of a bipolar transistor in order to insulate, at least, the layer to form the emitter, the layer to form the base, or at most, these layers and the layer to form the collector, and an extension type dummy emitter extending from the emitter portion to the insulating region formed by transforming from the semiconductor material to form the emitter and using it as mask, the external base region is exposed to form a projection coupling the emitter region and insulating region, and the dummy emitter is inverted to transform into an emitter electrode metal layer to cover the whole upper surface of the projection.
The current gain cut-off frequency fT and the power gain cut-off frequency fm of a bipolar transistor (BT) are expressed as follows. ##EQU1## where τe (emitter depletion layer charging time)=re (Cbc+Ceb), τb (base transit time of minority carriers)=Wb2 /2Db, τc (collector depletion layer transit time of minority carriers)=Wc/2Vs, τcc (collector depletion layer charging time)=(Ree+Rc) Cbc, Rb: base resistance, Cbc: base-collector capacitance, Ceb: base-emitter capacitance, Wb: base layer thickness, Db: base diffusion coefficient of minority carriers, Wc: collector depletion layer thickness, Vs: collector saturation velocity of minority carriers, re: emitter resistance, Ree: emitter-contact resistance, and Rc: collector resistance. <Large values of fT and fm are required for high speed operation of BT.>
In the BT, as is clear from the formulae above, to increase fT and fm, it is necessary to decrease the capacitances of Cbc and Ceb, the thickness of base layer, the base resistance, the emitter resistance, and the collector resistance. In particular, to obtain a large fm, it is necessary to reduce Rb and Cbc. For these purposes, it is extremely important to reduce the size of each part of BT, optimize the electrode layout, and optimize the process to lower the contact resistance of the electrodes, and various attempts have been made in these directions.
Nagata et al. has reported a method to form the base electrode very close to the emitter portion by self-alignment and to reduce the external base resistance (Nagata et al., "A New Self-aligned Structure AlGaAs/GaAs HBT for High Speed Digital Circuits," Proc. Symp. on GaAs and Related Compounds (Inst. Phys. Conf. Ser. 790, P. 589, 1985). However, in this process and the structure by it, an emitter mesa and a base mesa are formed, and an emitter electrode is on the emitter mesa and a base electrode is formed very close to the emitter mesa separated by a SiO2 side wall of the emitter mesa. This may necessitate other masks to form the metal delineation from the emitter electrode and the base electrode, and may form steps of the delineation metals at the ends of the emitter mesa and the base mesa, which may incur breakage of the delineation metal. In this process, the base electrode is formed before the emitter electrode is formed. Hence, there may be limitation in the types of the base electrode metals due to the difference in alloying temperature of the base and emitter electrode.
FIGS. 6(a)-(g), 7(a)-(b), 8(a)-(b), 9(a)-(e), and 10 are sectional views indicating the method of forming the emitter electrode metal layer by inverting from the dummy emitter, in which FIGS. 6(a)-(g) relate to a case of covering the entire upper surface of emitter, with the emitter electrode metal layer substantially same in size as the emitter, FIGS. 7(a)-(b) show the emitter electrode metal layer covering the upper surface of the emitter in a form of an umbrella, FIGS. 8(a)-(b) refer to a case of placing a semiconductor material layer greater in the work function than the electrode metal, between the emitter electrode metal layer and emitter shown in FIGS. 6(a)-(g), FIGS. 9(a)-(b) denote a case of placing the emitter electrode metal layer on the emitter to cover its upper surface in a mushroom shape, and FIG. 10 shows a case of using Alx Gal-x As (x≧0.4) as a protective film of emitter-contact layer in the process shown in FIGS. 9(a)-(b);
FIGS. 15(a)-(b), 16(a)-(c), 17(a)-(d), 18(a)-(b), 19(a)-(b), and 20(a)-(c) represent methods of forming a base electrode metal layer adjacent to the emitter portion in self-alignment with the emitter by using the emitter electrode metal layer or the dummy emitter as a mask in which FIGS. 15(a)-(b) show a method of forming a base electrode metal layer using an umbrella-shaped emitter electrode metal layer as a mask, FIGS. 16(a)-(c) show a method of forming a base electrode metal layer using the umbrella-shaped emitter electrode metal layer and SiOx side wall formed at its side as a mask, FIGS. 17(a)-(d) show a method of forming a base electrode metal layer using SiOx side wall formed on the side of the emitter and the emitter electrode metal layer covering the upper surface of emitter portion in the same size, FIGS. 18(a)-(b) show a method of forming a base electrode metal layer using a mushroom-shaped emitter electrode metal layer as a mask, FIGS. 19(a)-(b) show a method of forming emitter electrode metal layer after forming a base electrode metal layer in self-alignment with the emitter using the umbrella-shaped dummy emitter as a mask, and FIGS. 20(a)-(c) show a method of forming an emitter electrode metal layer after forming a base electrode metal layer by self-alignment, using a dummy emitter substantially of the same size as the emitter;
1--semi-insulating GaAs substrate, 2--high doping density n-type GaAs, 2a--part of 2 to compose a bipolar transistor, 3--N-type GaAs, 3a--collection region, 3b--insulation region formed by transforming from material of 3, 4--high doping density p-type GaAs, 4a--part of 4 to compose a bipolar transistor, 4b--base region just beneath emitter electrode metal layer or the layer composed of it and side wall, 4c--base region of outside of 4b, 4d--thick outer base region, 5--n-type Alx GAl-x As, 5a--part of 5 to compose a bipolar transistor, 5b--insulating region formed by transforming from the material of 5, 5c--p-type region formed by transforming from the material of 5, 6--high doping density n-type GaAs, 6a--part of 6 to compose a bipolar transistor, 6b--insulating region formed by transforming from the material of 6, 7--multilayer structural material composed of parts 1 to 7, 8--emitter region composed of 5a and 6a, 9--mesa composed of 8 and 5b, 6b, 10a--emitter electrode metal layer covering the whole upper surface of mesa 9 in a form of umbrella, 10b--wiring pattern of emitter electrode, 10c--emitter electrode metal layer covering the whole upper surface of mesa 9, having substantially same size as mesa 9, 10d--mushroom-shaped emitter electrode metal layer to cover the upper surface of mesa 9, 10e--emitter electrode metal layer covering the whole upper surface of emitter, having substantially same size as emitter, 10f--emitter electrode metal layer to cover the whole upper surface of emitter in a form of umbrella, 10g--mushroom-shaped emitter electrode metal layer to cover the whole upper surface of emitter, 11a--base electrode metal layer extending from outer base region to peripheral insulating region, 11b--base electrode wiring pattern, 11c--base electrode formed adjacently to emitter portion, 12a--collector electrode, 12b--collector electrode wiring pattern, 13--insulating region inside transistor, 14--external insulating region isolating transistors from each other, 15--undercut portion by wet etching, 16--multilayer structural material composed of 7, 35 and 36, 17--side wall, 18--SiOx dummy emitter, 19--Al dummy emitter, 20--dummy emitter, 21--photosensitive resist, 22a--opening with exposed 6a, 22b--umbrella-shaped opening with exposed 6b, 23--Alx Gal-x As (x≧0.4) to protect layer 6, 24--ion implantation (Be+, 25--ion implantation (O+), 26--ion implantation (H+), 27--mask of photosensitive resist, 28--base electrode metal, 29a--base region, 29b--mask in same size as base region, 30--SiOx dummy emitter extending from emitter region to insulating region, 31--Al dummy emitter to cover the whole upper surface of 30, 32--dummy emitter composed of 30 and 31, 33--cross section of bipolar transistor, 34--cross-section of bipolar transistor, 35--n-type Inx Gal-x As (x=0 to 1), 35a--part of 35 formed on emitter portion 8, 36--n-type InAs layer, and 36--part of 36 formed on emitter 8.
On the circumference of base region 4a composed of high doping density p-type GaAs (p+ -GaAs), there are insulating region 13 formed by transforming from the p+ -GaAs and n-type GaAs (n-GaAs) to form collector region 3a, and insulating region 14 formed by transforming from high doping density n-type GaAs (n+ -GaAs) layer to form the contact for collector 2a.
The emitter region 8 is composed of part 5a made of n-type Alx Gal-x As (n-AlGaAs) with a large energy band gap, and part 6a made of N+ -GaAs, and forms the mesa 9 coupled with an insulating region composed of 6b and 5b formed by transforming from the semiconductor materials of 6a and 5a.
Accordingly, the resistance of the emitter contact is extremely small as compared with that of the conventional HBT. Besides, the wiring pattern 10b can be formed very easily by using a simply mask, and this wiring pattern 10b is also free from wire disconnections due to step breakage, which is a conventional problem, because it contacts with the emitter electrode metal layer 10a on three sides. Moreover, since the emitter electrode metal layer 10a serves both as emitter electrode and as emitter electrode delineation metal, an HBT of an extremely small emitter size may be easily fabricated. Part 6b of mesa 9 is insulated in this embodiment, but it is not necessarily insulated. If the part 6b is left in a state of n+ -GaAs, the capacitance in the insulating region 14 enclosed between electrode metal layer 10a and N+ -GaAs layer 2 is slightly increased, but this change is negligibly small in an HBT of small size. To the contrary, since the area used to form the emitter contact is widened, it is effective to reduce the contact resistance. Similarly, the upper portion of part 5b may be also in an n-type state.
In said structure of the HBT, Alx Gal-x As is used as emitter, and GaAs is used to form other parts, but the same structure may be also applicable to an HBT made of other materials, or to be usual homojunction BT composed of an emitter, base and collector of the same semiconductor material, or a pnp type BT. Moreover, it may also be applied to an inverted type HBT or BT in which the positions of emitter and collector are exchanged so that the collector is on the upper side.
2. FIG. 2 shows a different structure of embodiment 1, wherein the base region 4d outside of the base region 4b just beneath the emitter electrode metal layer 10a is a thick external base region composed of a p-type region 5c formed by transforming from the emitter region 5c and external base region 4c of p+ -GaAs.
In FIG. 3, relating to embodiment 1, the whole upper surface of the emitter mesa 9 is covered by the emitter electrode metal layer 10c of substantially the same size therewith, a side wall 17 made of SiOx thin film of 3000 Å in thickness is formed on the sides around the mesa 9 and emitter electrode metal 10c, and a base electrode metal layer 11a is formed substantially in contact with the side wall 17, extending from the external base to the peripheral insulating region. The effect is same as mentioned in embodiment 1. As the side wall, meanwhile, other insulating material such as SiNx may be used.
4. FIG. 4 shows a further different composition of embodiment 1, in which a side wall 17 made of thin film of SiOx in 3000 Å in thickness is formed on the side of emitter mesa 9 and emitter electrode metal layer 10a, and a base electrode metal layer 11a is formed substantially in contact with the side wall 17, extending from the external base to the peripheral insulating region 14. As the side wall, other insulating materials such as SiNx may be also used.
6. FIGS. 6(a)-(g) illustrate a method of fabrication used to form an emitter electrode metal layer 10e which covers the whole upper surface mesa of mesa 9. As shown in FIG. 6(a), on a semi-insulating GaAs substrate 1, a multilayer structural material 7 composed of n+ -GaAs layer 2, n-GaAs layer 3, p+ -GaAs layer 4, n-AlGaAs layer 5, and n+ -GaAs layer 6 is formed by epitaxial growth.
On this multilayer structural material 7, a 1 μm thick SiOx thin film is formed, and in the portion corresponding to emitter on this film, an Al layer 19 of 5000 Å in thickness is formed by evaporating and lifting off, and SiOx layer 18 corresponding to emitter portion is formed by dry etching with CHF3, using the Al layer 19 as a mask (FIG. 6 (b)). By exposing the external base region 4c by etching, using a dummy emitter 20 composed of SiOx layer 18 and Al layer 19 as a mask, and a protruding emitting region 8 is formed (FIG. 6(c)). In succession, the surface is covered and flattened with photosensitive resist 21 (FIG. 6(d)), and the photosensitive resist 21 is etched by dry etching using oxygen plasma, and the upper part of dummy emitter 20 is exposed (FIG. 6(e)), then, removing the Al layer 19 by hydrochloric acid and also removing SiOx 18 by buffer HF, an opening 22a is formed (FIG. 6(f)). Next, in this opening 22 a, AuGe, Ni, Ti and Au are evaporated in this order and lifted off, and an emitter electrode metal layer 10e is formed (FIG. 6(g)). As a result, the emitter electrode metal layer 10e used to cover the whole upper surface of emitter mesa 8 is formed. In this embodiment, meanwhile, as the layer used to form dummy emitter, an SiOx layer and an Al layer are used, but instead of SiOx, other materials such as SiNx may also be used. Or, instead of Al, other metals may be used, too. Incidentally, after forming the SiOx layer 18 by dry etching, the Al layer 19 is not necessarily required. In this embodiment, the external base region 4c can be made also by etching until close to the external base region using a dummy emitter 20 as a mask, and then by etching up to the external base region using the emitter electrode metal layer as a mask. This has an effect to protect the external base region from being damaged during the process. This process can be applied also to a homojunction BT, or a HBT or BT of the inverted type.
8. By forming a multilayer structural material 16 by epitaxial growth of a high doping density n-type Inx Gal-x As layer 35 in which x carrier continuously from 0 to 1 (n-Inx Gal-x As (x=0 to 1) and a high doping density n-type InAs layer 36 on the multilayer structure material 7, an emitter electrode metal layer 10e is formed as shown in FIG. 8(b) by applying the method of embodiment 6. Since the work function of InAs is greater than that of the electrode metal, a low resistance emitter contact may be obtained without any alloying heat treatment. In the embodiment, Inx Gal-x As continuously varying in composition and InAs are formed in layers, but Inx Gal-x As of a specific composition may be also formed in a layer.
9. FIGS. 9(a)-(e) show a fabricating method of mushroom-shaped emitter electrode metal layer 10g. After forming an emitter mesa 8 by etching as shown in FIG. 6(c), using the dummy emitter 20 as a mask, the surface is covered with a thin film of SiOx of 3000 Å in thickness, and a side wall 17 composed of SiOx is formed on the sides of the emitter mesa 8 and dummy emitter 20 by anisotropic dry etching using CHF3 (FIG. 9(a)). Then the surface is coated and flattened with a photosensitive resist 21 (FIG. 9(b)), and the upper part of the dummy emitter 20 is exposed by dry etching using an oxygen plasma (FIG. 9(c)), and after removing Al 19 by HCl, an opening 22b with n+ -GaAs layer 6a exposed is formed by anisotropic dry etching using CHF3 (FIG. 9(d)). In succession, AuGe, Ni, Ti and Au are evaporated in this order and lifted off, thereby forming an emitter electrode metal layer 10g.
10. By forming an Alx Gal-x As layer 23 where x is 0.4 or more on the multilayer structural material in FIG. 6(a), the process of embodiment 9 is applied thereafter. However, in the process of FIG. 9(d), after removing the SiOx layer 18 and also removing Alx Gal-x As layer 23 by using acid, the emitter electrode metal layer 10g is formed. By this method, damage of n+ -GaAs layer 6a by dry etching may be prevented, and a clean n+ -GaAs layer 6a appears, so that an ohmic contact of high quality may be obtained. This method may be also applied in embodiments 6 to 8.
11. FIG. 11 shows a method of forming an external base region 4c of high dope p-type, by ion implantation of p-type dopant into the external base region 4c outside of the base region 4b just beneath the emitter electrode, using the dummy emitter 20 as a mask. After forming the structure of (c) in FIG. 6, Be+ is implanted using the dummy emitter 20 as mask (24), and it is heated to 750� C. for 10 seconds, so that a high doping density external base region 4c as shown in FIG. 11 is formed. Thereafter, applying the method of embodiment 6 shown in FIG. 6, the dummy emitter 20 is inverted to an emitter electrode metal layer 10e.
After ion implantation, it is necessary to anneal at a relatively high temperature, but adverse effects are not present because the n+ -GaAs layer 6 is covered with the SiOx layer 18. Otherwise, Be+ may be implanted at the step of FIG. 6(b), or after etching until close to the external base region 4c, and then the external base may be exposed by etching. Or the implanted Be+ may penetrate even into the collection region 3. For this purpose, aside from Be+, Mg+ or Zn+ may be also used.
12. As shown in FIG. 12, after forming a dummy emitter 20 as in FIG. 6(b), Be+ is implanted, and part of GaAs layer 6 and Alx Gal-x As layer 5 is etched off, and a thick external base region 4d is formed, so that the sheet resistance may be lowered. Thereafter, by applying the method shown in FIGS. 6(a)-(g), the dummy emitter 20 is inverted into an emitter electrode metal layer 10e.
13. FIG. 13 shows a method of forming a buried type collector 3a of the same size as the dummy emitter 20 by ion implantation, using the dummy emitter 20 as a mask. After the step shown in FIG. 6(c), a collector 3a substantially of the same size as the dummy emitter 20 and its peripheral insulating region 3b are formed by implanting O+ ions into the layer 3 using the dummy emitter 20 as a mask as shown in FIG. 13, and, by heat treatment at 750� C. for 10 seconds. Thereafter, by employing he method shown in FIGS. 6(a)-(g), the dummy emitter 20 is inverted into an emitter electrode metal layer 10e. Aside from O+, other ions such as B+ may be used. As in the embodiments 11 and 12, the heat treatment at high temperature is enabled owing to the existance of the SiOx dummy emitter.
14. After forming an emitter electrode metal layer 10e (FIG. 6(g)), the collector region 3a substantially of same size as the emitter electrode metal layer 10e and its peripheral insulating region 3b are formed by implanting H ions which are implanted into a layer 3 for forming a collector, as shown in FIG. 14, using the emitter electrode metal layer 10e as a mask. In the case of H+ ion implantation, since heat treatment is not needed in the formation of the insulating region, the contact part formed between the emitter electrode metal layer 10e and emitter is protected from damage. Hence, it is possible to form a buried type collector region 3a by using H+.
16. After forming an umbrella-shaped emitter electrode metal layer 10f as shown in FIG. 7(b), the surface is coated with a thin film of SiOx to a thickness of 3000 Å, and by anisotropic dry etching using CHF3, an SiOx side wall 17 is formed on the sides around the emitter mesa 8 and electrode metal layer 10f as shown in FIG. 16(a). Furthermore, as shown in FIG. 16(b), base electrode metals 28 are evaporated and lifted off by using photosensitive resist 27 and the umbrella-shaped portion composed of electrode metal layer 10f and side wall 17 as masks. This forms the base electrode metal layer 11c in the external base region 4c outside of the base region 4b just beneath the electrode metal layer 10f and side wall 17, as shown in FIG. 16(b). Then the SiOx side wall 17 is removed by buffer HF.
17. After forming an emitter electrode metal layer 10e (FIG. 6(g)), an SiOx side wall 17 is formed on the sides around the emitter mesa 8 and metal layer 10e, and a mask 27 of photosensitive resist is applied as shown in FIG. 17(a). In succession, the base electrode metal 28 is evaporated and lifted off, and a structure shown in FIG. 17(b) is formed. Then, the surface is covered with a photosensitive resist 21, and the upper portion of electrode metal layer 10e is exposed by dry etching using oxygen plasma as shown in FIG. 17(c). By etching away the metals 28 depositing on the side wall 17, the emitter electrode and base electrode are separated. As a result, as shown in FIG. 17(d), the base electrode metal layer 11c is formed at a distance of the width of side wall 17 with respect to emitter part 5a. Hence, the external base resistance may be reduced.
20. In the formation of structure in FIG. 9(a), a side wall 17 composed of SiNx is formed in a method similar to that shown in FIG. 20(a), and base electrode metals 28 are evaporated and lifted off through the mast 27 of photosensitive resist as shown in FIG. 20(b). Thereafter, applying the method of separation of the base electrode from emitter electrode as shown in embodiment 17, and selectively removing SiNx with respect to the dummy emitter 19, a structure as shown in FIG. 20(c) is formed. Then, conforming to the process of the inversion of the dummy emitter into the emitter electrode metal layer as shown in embodiment 6, the base electrode metal layer 11c is formed adjacent to the emitter part 5a. As in embodiment 19, it is necessary to select a metal, as a base electrode metal, whose ohmic contact forming temperature is not lower than the ohmic contact forming temperature of the emitter. In this embodiment, the external base region 4c can also be exposed by etching until close to the region 4c before forming the side wall 17, and then by etching up to the region 4c.
21. FIGS. 21(a)-1 to (b)-3 show a method of forming an emitting mesa 9 as shown in FIG. 1 and an electrode metal layer 10a serving both as an emitter electrode and as an emitter electrode delineation metal. On the multilayer structure material 7 shown in FIGS. 6(a)-(g), a mask 29b corresponding to the size 29a of the base is formed as shown in FIG. 21(a), and oxygen ions are implanted into the layer 3 for forming the collector. Consequently, an insulating region 13 is formed. Then, on the portion 29a corresponding to the base region, an extension type dummy emitter 32 composed of an SiOx layer 30 and an Al layer 31 extending from the emitter part to the insulation region 13 is formed by the method shown in embodiment 6 (FIG. 21(b)). Thereafter, according to the method shown in embodiment 7, an extension type emitter mesa 9 and an external base region 4c are formed (FIG. 21(c)), and an umbrella-shaped dummy emitter 32 is converted into an emitter electrode metal layer 10a. By employing this method, since the emitter electrode serves also as the emitter electrode delineation metal and it is formed by self-alignment corresponding to the emitter part, a bipolar transistor of a very small emitter size can also be fabricated. In this embodiment, although the method of forming an umbrella-shaped electrode metal layer is exhibited, the formation of the emitter electrode metal layer as disclosed in embodiments 6, 8, 9, 10 is also applicable.
22. FIGS. 22(a)-(b) show a method of forming, by self-alignment, a base electrode metal layer 11a serving as both the base electrode and the base electrode delineation metal and existing adjacent to the emitter portion, referring to a case of using an umbrella-shaped electrode metal layer. In the process shown in FIGS. 21(a)-1 to (b)-3, after forming an umbrella-shaped electrode metal layer 10a as shown in FIG. 1, a collector electrode 12a is formed as shown in FIG. 1, and H+ ions are implanted around the transistor. Consequently, an insulating region 14 ranging from the surface to substrate 1 is formed. Then, as shown in FIG. 22(a), base electrode metals 28 are evaporated and lifted off by using a photosensitive resist mask 27 and the umbrella-shaped emitter electrode metal layer 10a as a mask. Consequently, outside of the base region 4b just beneath the emitter electrode metal layer 10a, a base electrode metal layer 11a extending from the external base region to the peripheral insulating region 14 is formed. In this embodiment, although the method of embodiment 15 of using umbrella-shaped emitter electrode metal layer is employed, the method of formation of base electrode metal layer as disclosed in embodiments 16, 17, 18, 19, 20 is also applicable.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4593305 *May 8, 1984Jun 3, 1986Kabushiki Kaisha ToshibaHeterostructure bipolar transistorUS4593457 *Dec 17, 1984Jun 10, 1986Motorola, Inc.Method for making gallium arsenide NPN transistor with self-aligned base enhancement to emitter region and metal contactUS4617724 *Sep 30, 1985Oct 21, 1986Fujitsu LimitedProcess for fabricating heterojunction bipolar transistor with low base resistanceUS4679305 *Dec 18, 1985Jul 14, 1987Kabushiki Kaisha ToshibaMethod of manufacturing a heterojunction bipolar transistor having self-aligned emitter and base and selective isolation regions* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5266505 *Dec 22, 1992Nov 30, 1993International Business Machines CorporationImage reversal process for self-aligned implants in planar epitaxial-base bipolar transistorsUS5286661 *Aug 26, 1992Feb 15, 1994Motorola, Inc.Method of forming a bipolar transistor having an emitter overhangUS5344786 *Sep 9, 1992Sep 6, 1994Texas Instruments IncorporatedMethod of fabricating self-aligned heterojunction bipolar transistorsUS5362658 *May 3, 1993Nov 8, 1994Mitsubishi Denki Kabushiki KaishaMethod for producing semiconductor deviceUS5434091 *Oct 7, 1994Jul 18, 1995Texas Instruments IncorporatedMethod for making collector up bipolar transistors having reducing junction capacitance and increasing current gainUS5436181 *Apr 18, 1994Jul 25, 1995Texas Instruments IncorporatedMethod of self aligning an emitter contact in a heterojunction bipolar transistorUS5445976 *Aug 9, 1994Aug 29, 1995Texas Instruments IncorporatedMethod for producing bipolar transistor having reduced base-collector capacitanceUS5548141 *May 16, 1995Aug 20, 1996Texas Instruments IncorporatedBipolar transistor having a self emitter contact alignedUS5648278 *Jun 7, 1995Jul 15, 1997Texas Instruments IncorporatedForming islands that do not cross boundariesUS5698460 *Jun 7, 1995Dec 16, 1997Texas Instruments IncorporatedMethod of self-aligning an emitter contact in a planar heterojunction bipolar transistor and apparatus thereofUS5700701 *Jun 7, 1995Dec 23, 1997Texas Instruments IncorporatedMethod for reducing junction capacitance and increasing current gain in collector-up bipolar transistorsUS5783966 *Jan 16, 1997Jul 21, 1998Texas Instruments IncorporatedReducing junction capacitance and increasing current gain in collector-up bipolar transistorsUS5804487 *Jul 10, 1996Sep 8, 1998Trw Inc.Depositing epitaxial layers on substrate, depositing photoresist, patterning, developing, depositing metal to form ohmic contact, lifting off metalUS5994194 *May 7, 1998Nov 30, 1999Trw Inc.Controlling spacings between ohmic metal and emitters on integraterd circuitUS6451659 *Dec 3, 1999Sep 17, 2002Thomson-CsfMethod for forming a bipolar transistor stabilized with electrical insulating elementsUS6552374 *Jan 17, 2001Apr 22, 2003Asb, Inc.Method of manufacturing bipolar device and structure thereofUS7190047 *Jun 3, 2004Mar 13, 2007Lucent Technologies Inc.Transistors and methods for making the same* Cited by examinerClassifications U.S. Classification438/321, 257/E21.387, 257/E29.189, 257/E29.03, 148/DIG.10, 148/DIG.72, 438/315International ClassificationH01L29/417, H01L29/08, H01L29/737, H01L21/331Cooperative ClassificationY10S148/072, Y10S148/01, H01L29/66318, H01L29/0804, H01L29/41708, H01L29/7371European ClassificationH01L29/66M6T2V2, H01L29/417B, H01L29/08B, H01L29/737BLegal EventsDateCodeEventDescriptionApr 20, 2004FPAYFee paymentYear of fee payment: 12May 15, 2000FPAYFee paymentYear of fee payment: 8May 14, 1996FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google