Source: http://www.google.com.tw/patents/US7822057
Timestamp: 2013-05-22 17:41:10
Document Index: 645272452

Matched Legal Cases: ['Application No. 05798761', 'Application No. 05798761', 'Application No. 200580032948', 'Application No. 200580032948', 'Application No. 200580032948', 'Application No. 200580032888', 'Application No. 200580032947', 'Application No. 200580032947']

�M�Q US7822057 - Method and system for keeping a fibre channel arbitrated loop open during ... - Google �M�Q�j�M �Ϥ� �a�� Play YouTube �s�D Gmail ���ݵw�� ��h »�i���M�Q�j�M | �������� | �n�J�i���M�Q�j�M�M�QA method and system for keeping an arbitrated loop open during a frame gap using a fiber channel switch element is provided. The switch element includes a port control module having a receive and transmit segment, wherein the transmit segment activates a timer whose value determines a duration during...http://www.google.com.tw/patents/US7822057?utm_source=gb-gplus-share�M�Q US7822057 - Method and system for keeping a fibre channel arbitrated loop open during frame gaps���}��US7822057 B2�X���������v�ӽЮѽs��12/191,890�o�G���2010�~10��26���ӽФ��2008�~8��14�� �u���v���2004�~7��20����L���}�M�Q��US7420982US20050018671US20090046736�o��HFrank R. DroppsErnest G. KohlweyGary M. Papenfuss��M�Q�v�HQlogic, Corporation ���M�Q������370/424370/528��ڱM�Q������H04L12/42H04L12/56 �X�@����H04L47/245H04L12/42 �ڬw������H04L47/24EH04L12/42�ѦҤ��m�M�Q�ޥ� (107)�D�M�Q�ޥ� (96)�~���s�����M�Q�ӼЧ� ���M�Q�ӼЧ��M�Q����T�� �ڬw�M�Q��Method and system for keeping a fibre channel arbitrated loop open during frame gapsUS 7822057 B2�K�n A method and system for keeping an arbitrated loop open during a frame gap using a fiber channel switch element is provided. The switch element includes a port control module having a receive and transmit segment, wherein the transmit segment activates a timer whose value determines a duration during which the arbitrated loop remains open; determines if a last frame from a sequence of frames from a source port has been transmitted; modifies the timer value if a higher priority frame for transmission is unavailable; and keeps the arbitrated loop open until the timer reaches a certain value. If a higher priority frame is available for transmission before the timer value is modified then the higher priority frame is transmitted and the timer value is re-initialized.
CROSS REFERENCE TO RELATED APPLICATIONS This patent application is a continuation of U.S. patent application Ser. No. 10/894,491, filed Jul. 20, 2004, now U.S. Pat. No. 7,420,982 that claims priority under 35 U.S.C.��119(e)(1) to the following provisional patent applications:
During an arbitrated loop mode, many cycles are wasted while arbitrating for the loop, or opening a device on the loop. If a sequence of frames had to go through arbitration and ��OPEN�� (as defined by the fibre channel standards), it could take more time arbitrating than keeping the loop open and waiting for the next frame of the sequence to arrive in the receive buffer.
��EOF��: End of Frame
��F-Port��: A port to which non-loop N_Ports are attached to a fabric and does not include FL_ports.
��FL_Port��: A L_Port that is able to perform the function of a F_Port, attached via a link to one off more NL_Ports in an Arbitrated Loop topology.
��NL_Port��: A L-Port that can perform the function of a N_Port.
��SOF��: Start of Frame
The fabric element of the present invention is presently implemented as a single CUSS ASIC, and for this reason the term ��fabric elements�� and ASIC are used interchangeably to refer to the preferred embodiments in this specification. Although FIG. 1B shows 20 ports, the present invention is not limited to any particular number of ports.
Switch crossbar 50 is a connectionless crossbar (packet switch) of known conventional design, sized to connect 21��21 paths. This is to accommodate 20 GL ports plus a port for connection to a fabric controller, which may be external to ASIC 20.
In the preferred embodiments of switch chassis described herein, the fabric controller is a firmware-programmed microprocessor, also referred to as the input/out processor (��IOP��. IOP 66 is shown in FIG. 1C as a part of a switch chassis utilizing one or more of ASIC 20. As seen in FIG. 1B, bi-directional connection to IOP 66 is routed through port 67, which connects internally to a control bus 60. Transmit buffer 56, receive buffer 58, control register 62 and Status register 64 connect to bus 60. Transmit buffer 56 and receive buffer 58 connect the internal connectionless switch crossbar 50 to IOP 66 so that it can source or sink frames.
FIG. 1E-1/1E-2 (jointly referred to as FIG. 1E) show yet another block diagram of ASIC 20 with sixteen GL and four XG port control modules. Each GL port control module has a Receive port (RPORT) 69 with a receive buffer (RBUF) 69A and a transmit port 70 with a transmit buffer (TBUF) 70A, as described below in detail. GL and XG port control modules are coupled to physical media devices (��PMD) 76 and 75 respectively.
Frames enter through link 301 and SERDES 302 converts data into 10-bit parallel data to fibre channel characters, which are then sent to receive pipe (��Rpipe��) 303A via a de-multiplexer (DEMUX) 303. Rpipe 303A includes, parity module 305 and decoder 304. Decoder 304 decodes 10B data to 8B and parity module 305 adds a parity bit. Rpipe 303A also performs various Fibre Channel standard functions such as detecting a start of frame (SOF0), end-of frame (EOF), Idles, R_RDYs (fibre channel standard primitive) and the like, which are not described since they are standard functions.
Reading from and writing to RBUF 63A are controlled by RBUF read control logic (RRD) 319 and RBUF write control logic (RWT) 307, respectively. RWT 307 specifies which empty RBUF 69A slot will be written into when a frame arrives through the data link via multiplexer 313B, CRC generate module 313A and EF module 314. EF (external proprietary format) module 314 encodes proprietary (i.e. non-standard) format frames to standard Fibre Channel 8B codes. Mux 313B receives input from Rx Spoof module 314A, which encodes frames to an proprietary format (if enabled). RWT 307 controls RBUF 69A write addresses and provide the slot number to tag writer (��TWT��) 317.
Transmit segment 312 performs various transmit functions. Transmit tag register (TTAG) 330 provides a list of all frames that are to be transmitted. Tag Writer 317 or common segment 311 write TTAG 330 information. The frames are provided to arbitration module (��transmit arbiter�� (��TARB��)) 331, which is then free to choose which source to process and which frame from that source to be processed next.
TTAG 330 includes a collection of buffers (for example, buffers based on a first-in first out (��FIFO��) scheme) for each frame source. TTAG 330 writes a tag for a source and TARB 331 then rears the tag. For any given source, there are as many entries in TTAG 330 as there are credits in RBUF 69A.
TMUX 339 chooses which data path to connect to the transmitter. The sources are: primitive sequences specified by IOP 66 via control registers 326 (shown as primitive 339A), and signals as specified by Transmit state machine (��TSM��) 346, frames following the loop path, or steered frames exiting the fabric via TBUF 70A.
IOP buffer (��IBUF��) 345 provides LOP 66 the means for transmitting frames for special purposes.
Frame multiplexer (��Mux��) 336 chooses the frame source, while logic (TX spoof 3341 converts D_ID and S_ID from public to private addresses. Mux 336 receives input from Tx Spoof module 334, TBUF tags 333, and Mux 335 to select a frame source for transmission.
RPORT 310A uses a virtual lane (��VL) cache 402 that stores plural vector values that are used for virtual lane assignment. In one aspect of the present invention, VL Cache 402 may have 32 entries and two vectors per entry. IOP 66 is able to read or write VL cache 402 entries during frame traffic. State machine 401 controls credit that is received. On the transmit side, credit state machine 347 controls frame transmission based on credit availability. State machine 347 interfaces with credit counters 328A.
In one aspect of the present invention a loop hold timer system 331A (also referred to herein as ��loop hold timer 331A�� or ��timer 331 A��) is provided. System 331A has a counter and is located in TARB 331. The loop hold timer 331A counter allows a transmit port to wait during a frame gap, e.g., when there is a delay in a sequence of frames arriving from a certain source port. This is achieved by preventing other source ports from being selected for frame transfers during this time.
After the transfer is completed and if there are no valid frames available from the same source, timer 331A begins to decrement (or increase, depending upon how the time value is programmed). Valid frames from other source ports are ignored during this ��decrement�� period. Timer 331A will continue to decrement until a valid frame from the source port arrives, or until the timer 331A decrements down to zero. If a valid frame from the source port arrives during the decrement period, the same loading and decrement process will be repeated.
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