Source: http://www.google.com/patents/US7483307?ie=ISO-8859-1
Timestamp: 2015-05-28 13:07:45
Document Index: 70135301

Matched Legal Cases: ['Application No. 60', 'arts 1243', 'arts 1243', 'arts 1244', 'arts 1243', 'arts 1243']

Patent US7483307 - Method and apparatus for sensing in charge trapping non-volatile memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA memory cell with a charge trapping structure is read by measuring current between the substrate region of the memory cell and one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping...http://www.google.com/patents/US7483307?utm_source=gb-gplus-sharePatent US7483307 - Method and apparatus for sensing in charge trapping non-volatile memoryAdvanced Patent SearchPublication numberUS7483307 B2Publication typeGrantApplication numberUS 12/020,793Publication dateJan 27, 2009Filing dateJan 28, 2008Priority dateSep 9, 2004Fee statusPaidAlso published asEP1635357A1, US7345920, US20060050553, US20080137418Publication number020793, 12020793, US 7483307 B2, US 7483307B2, US-B2-7483307, US7483307 B2, US7483307B2InventorsChih Chieh YehOriginal AssigneeMacronix International Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (34), Non-Patent Citations (2), Classifications (12), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMethod and apparatus for sensing in charge trapping non-volatile memory
US 7483307 B2Abstract
A memory cell with a charge trapping structure is read by measuring current between the substrate region of the memory cell and one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation.
a first bit line coupled to the first pass transistor;
a second bit line coupled to the second pass transistor;
logic coupled to the plurality of memory cells, said logic turning on one of the first pass transistor and the second pass transistor to permit electrical coupling of a sense amplifier to the source region or the drain region of a memory cell of the plurality of memory cells, thereby selecting part of the charge trapping structure corresponding to one of the source region or the drain region, and said logic applying a first bias arrangement inducing at least a reverse biased band-to-band current component through one of the source region or the drain region to determine the charge storage state and said logic measuring at least the reverse biased band-to-band current component flowing between the substrate region and one of the source region or the drain region to determine the charge storage state of the selected part of the charge trapping structure.
18. The integrated circuit of claim 1, wherein hot holes generated during the first bias arrangement are insufficient to disturb the charge storage state. Description
This application is a divisional of U.S. application Ser. No. 10/973,593, filed 26 Oct. 2004 by inventor Chih Chieh Yeh entitled Method and Apparatus for Sensing in Charge Trapping Non-Volatile Memory, which claims the benefit of U.S. Provisional Application 60/608,455 filed 9 Sep. 2004 and claims the benefit of U.S. Provisional Application No. 60/608,528 filed 9 Sep. 2004.
In FIG. 12, several memory cells are programmed similar to FIG. 11. The voltage of the substrate 1202 is 0 V. However, with the memory cells selected by the word line 1240, the charge trapping structure parts 1243, 1244, 1245, 1246, and 1247 are selected by turning on the pass transistor word line 1290 with a voltage of 10 V. The voltages of the intervening memory cell word lines 1250, 1260, 1270, and 1280 is set to 10V. The other pass transistor word line 1210 and the remaining memory cell word lines 1220 and 1230 are turned off with a voltage of 0 V. Out of the selected charge trapping structure parts 1243, 1244, 1245, 1246, and 1247, the charge trapping structure parts 1244, 1246, and 1247 are programmed by setting the voltages of the bit lines 1204, 1206, and 1207 to 5 V. Out of the selected charge trapping structure parts 1243, 1244, 1245, 1246, and 1247, the charge trapping structure parts 1243 and 1245 are not programmed, by setting the voltages of the bit lines 1203 and 1205 to 0 V.
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