Source: http://www.google.es/patents/US8042025?dq=flatulence
Timestamp: 2016-02-07 01:25:58
Document Index: 518816197

Matched Legal Cases: ['Application No. 200610172839', 'Application No. 200610172839', 'Application No. 200610172839', 'Application No. 200610172839', 'Application No. 200610172839', 'Application No. 096122784']

Patente US8042025 - Determining a message residue - Google PatentesB�squeda Im�genes Maps Play YouTube Noticias Gmail Drive M�s »Iniciar sesi�nPatentesIn one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift...http://www.google.es/patents/US8042025?utm_source=gb-gplus-sharePatente US8042025 - Determining a message residue B�squeda avanzada de patentes N�mero de publicaci�nUS8042025 B2Tipo de publicaci�nConcesi�n N�mero de solicitudUS 12/291,621 Fecha de publicaci�n18 Oct 2011 Fecha de presentaci�n12 Nov 2008 Fecha de prioridad18 Dic 2007TarifaPagadasTambi�n publicado comoUS20090158132, WO2009082598A1 N�mero de publicaci�n12291621, 291621, US 8042025 B2, US 8042025B2, US-B2-8042025, US8042025 B2, US8042025B2 InventoresVinodh Gopal, Gilbert Wolrich, Wajdi Feghali, Erdinc Ozturk, Shay Gueron Cesionario originalIntel CorporationExportar citaBiBTeX, EndNote, RefManCitas de patentes (65), Otras citas (45), Clasificaciones (7), Eventos legales (2) Enlaces externos: USPTO, Cesi�n de USPTO, EspacenetDetermining a message residue
US 8042025 B2 Resumen
In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.
1. Circuitry for determining a modular remainder with respect to a polynomial of a message comprised of a series of segments, comprising circuitry to:
access a strict subset of segments, the strict subset consisting of the most significant segments representing the message;
independently multiply each of at least the two most significant segments by respective constants;
transform the strict subset of segments into a smaller set of segments based on the independently multiplying each of at least the most significant segments by respective constants; and
determine the modular remainder based on a set of segments output by the repeatedly accessing, multiplying, and transforming; and
store the determined modular remainder.
2. The circuitry of claim 1, wherein the circuitry comprises circuitry to:
simultaneously process at least one second message by repeatedly:
accessing a strict subset of segments of the second message, the strict subset consisting of the most significant segments representing the second message;
independently multiplying each of at least the two most significant segments of the second message by the respective constants;
transforming the strict subset of segments of the second message into a smaller set of segments based on the independently multiplying each of at least the most significant segments of the second message by the respective constants.
3. The circuitry of claim 1, wherein the strict subset of segments consists of four segments and the smaller set of segments consists of two segments.
4. The circuitry of claim 1, wherein the modular remainder comprises a CRC (Cyclic Redundancy Check) value.
5. The circuitry of claim 1,
wherein the constants comprise constants derived by segment size and the polynomial.
6. The circuitry of claim 5,
wherein the circuitry comprises circuitry to determine a value based on the least significant of the subset of segments and the multiplication of the most significant segments by constants derived from the segment size and the polynomial.
7. The circuitry of claim 6, wherein the circuitry comprises circuitry to:
access a set of constants, determined prior to accessing the message, based on at least one of: (a) the polynomial and (b) a size of a segment.
8. The circuitry of claim 1,
wherein the message comprises a set of segments, S, of size n where n is an integer;
wherein each constant is determined by Kn=2z mod polynomial where z is an integer that differs for different constants and n is an integer identifying a one of the constants;
wherein the circuitry comprises circuitry to perform polynomial multiplication of the most significant remaining segment of S by a first one of the constants and the next most significant segment of S by a second one of the constants and xor the results with remaining segments in the strict subset of segments.
wherein each constant is determined by rKn=bitreflect(2z mod polynomial)<<1, where z is an integer that differs for different constants and n is an integer identifying a one of the constants;
10. Computer program instructions disposed an a computer readable storage medium, the instructions, when executed, cause a processor to determine a modular remainder with respect to a polynomial of a message comprised of a series of segments, the instructions comprising instructions to cause the processor to:
11. The computer program instructions circuitry of claim 10, wherein the instructions comprise instructions to cause the processor to:
12. The computer program instructions of claim 11, wherein the instructions cause the processor to:
determine a value based on the least significant of the subset of segments and the multiplication of the most significant segments by constants derived from the segment size and the polynomial;
wherein the instructions comprise instructions to cause the processor to perform polynomial multiplication of the most significant remaining segment of the message by a first one of the constants and the next most significant segment of the message by a second one of the constants and xor the results with remaining segments in the strict subset of segments.
at least one PHY to receive signals from a communications medium,
at least one MAC (media access controller) coupled to the at least one PHY; and
14. The communications system of claim 13, wherein the circuitry comprises circuitry to:
15. The communications system of claim 13, wherein the circuitry comprises circuitry to:
wherein the circuitry comprises circuitry to perform polynomial multiplication of the most significant remaining segment of the message by a first one of the constants and the next most significant segment of the message by a second one of the constants and xor the results with remaining segments in the strict subset of segments. Descripci�n
This application is a continuation-in-part and claims priority to U.S. application Ser. No. 11/959,142, entitled “Determining A Message Residue”, filed on Dec. 18, 2007, by inventors Gilbert Wolrich, Michael Kounavis, and Vinodh Gopal, which is incorporated by reference in its entirety herein.
A variety of computer applications operate on messages to create a message residue. The residue can represent message contents much more compactly. Among other uses, message residues are frequently used to determine whether data transmitted over network connections or retrieved from a storage device may have been corrupted. For instance, a noisy transmission line may change a “1” signal to a “0”, or vice versa. To detect corruption, a message is often accompanied by its message residue. A receiver of the data can then independently determine a residue for the message and compare the determined residue with the received residue.
A common message residue is known as a Cyclic Redundancy Check (CRC). A CRC computation is based on interpreting a stream of message bits as coefficients of a polynomial. For example, a message of “1010” corresponds to a polynomial of (1 x3)+(0 x2)+(1 x1)+(0 x0) or, more simply, x3+x1. The message polynomial is divided by another polynomial known as the modulus. For example, the other polynomial may be “11” or x+1. A CRC is the remainder of a division of the message by the polynomial. CRC polynomial division, however, is somewhat different than ordinary division in that it is computed over the finite field GF(2) (i.e., the set of integers modulo 2). More simply put: even number coefficients become zeroes and odd number coefficients become ones.
FIG. 1 is a diagram illustrating repeated reduction of message segments used to represent a message.
FIG. 2 is a flow-chart of a process to determine a message residue.
FIG. 3 is code illustrating reduction of message segments used to represent a message.
FIG. 4 is a sample execution schedule of instructions to reduce message segments used to represent a message.
FIG. 5 is a sample execution schedule of instructions to reduce message segments used to represent a message.
FIG. 6 is a diagram of a sample binary polynomial multiplication circuit.
FIG. 7 is a diagram illustrating a byte shuffle operation to re-order message bits in order of significance.
FIG. 8 is a diagram illustrating segment reduction of a message having bits arranged in little-endian format.
FIG. 9 is a diagram illustrating a relationship between multiplication of operands and multiplication of bit reflected operands.
FIG. 10 is code illustrating reduction of message segments having bits arranged in big-endian format.
Message residues are commonly used in many different protocols to protect data integrity. Computing these residues, however, imposes significant computational overhead. The following describes techniques that repeatedly whittle a message into a smaller set of equivalent data using fast, inexpensive operations. The resulting, smaller, set of data can then be processed, for example, in a conventional manner to arrive at a final message residue value. In other words, the more burdensome task of determining an exact value of a message residue is postponed until a message is reduced to a smaller size that retains the mathematical characteristics of the original message with respect to the residue.
In greater detail, FIG. 1 depicts a message S 100. To determine a message residue, the bits of the message S can be handled as the coefficients of a polynomial S(x). For example, a 32-bit CRC of S can be defined as:
CRC=S�232 mod g [1]
where g is a 33-bit polynomial. Different values of g have been defined for a variety of applications. For example, iSCSI (Internet Small Computer System Interface) defines a value of 11EDC6F4116 for g. Other applications have selected different polynomial sizes and values. Typically, the resulting CRC value is stored with the message, S, in the empty 32-least significant bits created by the 232 shift. Alternately, the value may be stored in a packet field or other location. Recomputing the CRC value and comparing with the stored value can indicate whether data was corrupted.
As shown, S can be represented as a series of n-bit segments, labeled S[ ], 100 a-100 z. The following describes techniques that successively “fold” the most significant segments into remaining segments, repeatedly reducing the amount of data used to represent S. In particular, the determination of the different values (e.g., 102, 104) to fold into the remaining segments (e.g., 100 c, 100 d), can be independently computed, potentially permitting parallel computation of these values. In comparison with an approach that successively folds a single segment 100 a at a time, folding multiple segments 100 a, 100 b at each iteration can greatly decrease computation time.
In greater detail, FIG. 1 depicts the first two 108 a, 108 b of a series of repeated folding operations that operate on a subset of segments. In the example shown, each subset features the four most significant remaining segments representing S. For example, the initial folding operation 108 a operates on segments 100 a, 100 b, 100 c, 100 d. As shown, the operation 108 a includes binary polynomial multiplication 102 a of the most significant segment 100 a by a first pre-computed constant K2 and a binary polynomial multiplication 104 of the next most significant segment 100 b by a second pre-computed constant K1. The results of these multiplications 102, 104 are folded into the remaining message segments by XORing the results with the values of the least significant segments of the subset 100 c, 100 d to yield segments 106 a, 106 b. The values of these segments 106 a, 106 b preserve the contribution of the most significant segments 100 a, 100 b to the final determination of the residue for S. Thereafter, segments 100 a, 100 b can be discarded or ignored for residue purposes.
As shown, the segments 106 a, 106 b output from the first set of folding operations 108 a can be combined with the next segments of S 100 e, 100 f to form a new subset of segments 106 a, 106 b, 100 e, 100 f. Again, a set of folding operation 108 b proceeds, folding the most significant segments 106 a, 106 b into segments 100 e, 100 f by a multiplication of segment 106 a by constant K2, a multiplication of segment 106 b by a constant K1, and XOR-ing the results with segments 100 e, 100 f to yield segments 110 (labeled S″).
This process of folding can repeat as desired to reduce the data representing S by two segments for each iteration. The reduction may be repeated any number of times. For example, in the sample implementation shown, folding may continue until only two segments remain. The residue of the final two segments (e.g., remaining-segments mod g) can be determined in a variety of ways as described below. The folding operations shown in FIG. 1 use constants K1 and K2 which can be pre-computed prior to accessing any segments of S. These constants may be determined as:
K1=2y mod g K2=2x mod g where x and y demarcate the boundary of the most significant segments folded into the remaining segments. For example, as shown in FIG. 1, y represents the ending bit position of segment 100 b within the subset of segments 100 a-100 d and x represents the ending bit position of segment 100 a within the subset 100 a-100 d. The values of x and y may vary in different implementations and architectures. For instance, for an implementation that operates on subsets of 64-bit segments, y may have a value of 128 and x may have a value of 192. However, in another 64-bit segment implementation, y may have a value of 96 and x may have a value of 160. For an implementation using 32-bit segments, x may have a value of 64 and y may have a value of 96.
The contribution of a given segment (e.g., 100 a, 100 b) to the message residue can, thus, be expressed as S[ ]�Kn. This technique described is well suited to execution on processors that have a Galois-field (carry-less) multiplier, though such hardware is not an implementation requirement.
Since g, x, and y, are constants, a set of K values (e.g., K1, K2, . . . ) can be pre-computed and stored prior to processing of the data values of S. Potentially, different sets of K can be pre-computed and stored for different values of g, x, and/or y. Such an implementation can quickly switch between polynomials by a lookup of a set of K values based on the particular computational setup.
Specific examples described above illustrated determination of a 32-bit CRC polynomial however the techniques described above may be applied to different sized remainders and/or polynomials. The techniques described above work also may work for arbitrary and/or non-uniform segment sizes. Additionally, while the above described folding operations 108 a, 108 b that operate on 4-segment subsets, other implementations may operate on a different number of segments. For example, instead of 4:2 segment reduction another implementation may feature a different segment reduction ratio. For instance, another implementation may fold more than two segments per iteration 108. Further, while the above describes a CRC message residue, the techniques described above can be used in other operations that determine a message residue or perform a modular reduction of a polynomial.
FIG. 2 illustrates a sample process for computing a message residue. As shown, after computing K values 202, the initial data segments 204 are reduced 206 to a set of fewer but equivalent data segments with respect to the residue by folding multiple segments into the remaining message at a time. If additional segments remain 208, reducing 206 continues with each reducing folding multiple segments into remaining ones. As shown, a final residue value 210 can be determined for the final set of remaining segments.
A variety of approaches can determine the final residue value such as a lookup table or a wide variety of algorithms (e.g., Barrett's reduction) to determine a modular remainder. For example, the final segments can be processed using an approach that implements the division process as multiplication. For instance, a n-bit remainder, rn, can be expressed as:
r n =L(g*�(M(s�q+))
L is an operation returning the b-least-significant-bits of data;
g* is the b-least-significant bits of polynomial g,
M is an operation returning the b-most-significant-bits,
q+ is the quotient of (22n/g), and
b is (width of g)−1.
Like the folding techniques described above, this approach can use pre-computed values for g* and q+ to speed computation.
FIG. 3 illustrates a sample implementation 300 of the reduction techniques described above. As shown, the inner loop of code 300 includes a sequence of 7-instructions. In this example, the high order bits of R1 and R2 initially store the value of the first segment, the low order bits of R1 and R2 initially store the value of the second segment, and a register, K, stores both K2 and K1 in the respective high and low order bits of a register.
Two of the operations (operation 3 and 4) use a binary polynomial multiplication instruction (labeled “BMUL”) that performs a polynomial multiplication over GF(2) of specified portions of the operands. That is, the instruction can operate on either the high order and/or low order half of the operands as indicated by the notation “.high” or “.low”. For example, BMUL (R1, K).low multiplies the lower half of R1 by the lower half of the register K (e.g., K1). A sample implementation of circuitry to implement this instruction is described below in conjunction with FIG. 6.
In this particular implementation, each segment is 32-bits and each register (e.g. R0, R1, R2) is 64-bits. For architectures using a 64-bit datapath and/or 64/128-bit register files, the use of 32-bit segments and constant values, K, can reduce the need to shift or mask registers to access segment and constant values during folding operations. Other implementations, however, can feature different sized segments and constants and may be tailored for other architectures.
A given set of instructions using the techniques above can be scheduled in a variety of ways to increase overall throughput. For example, FIG. 4 illustrates an instruction execution schedule 400 that operates on two different messages (“a”, “b”) in parallel. The schedule 400 shown identifies the cycle/processor execution port of the instructions 300 of the sample implementation of FIG. 3. For example, in cycle 1, inner-loop instructions 1 and 2 are executed for message “a” (labeled 1 a, 2 a), while in cycle 2, instruction 3 is executed for message “a” (labeled 1 a) and instructions 1 and 2 are executed for message “b” (labeled 1 b, 2 b).
The sample schedule 400 shown in FIG. 4 reflects a processor architecture featuring multiple ports of execution, though only a single port (port0) implements or is used to execute the binary polynomial multiplication instruction. The schedule 400 also reflects an architecture where the binary polynomial multiplication instruction is a 1-cycle operation. In this sample schedule 400, each iteration of the folding process consumes 7-cycles for the inner loop and uses 4-registers (R0, R1, R2, and a register to store K1 and K2). As shown, 6 8-byte blocks are processed after 17 cycles, averaging close to 3-cycles per 8-byte block. Continued operation approaches an average of 2.5 cycles per block.
FIG. 5 depicts another schedule 500 where the binary polynomial multiplication instruction is assumed to take 3-cycles instead of 1-cycle. While this may increase the total number of instruction cycles used to perform the reduction and may increase the number of registers used, increasing the number of messages simultaneously processed can mask the increase in instruction execution time and nevertheless attain similar performance to the 1-cycle binary polynomial multiplication instruction. For example, the schedule 500 of FIG. 5 processes 4-messages (“a”, “b”, “c”, and “d”) simultaneously and, again, achieves close to 2.5 cycles per 8-byte block.
Other schedules are possible for different architectures and different instructions used to implement the folding operations than those described above. For example, a processor implementing the binary polynomial multiplication instruction on multiple processor execution ports can initiate execution of instructions 3 and 4 in the same cycle.
FIG. 6 depicts a sample of circuitry that may be used to implement the binary polynomial multiplication instruction. In particular, the instruction operates on two operands, src1 and src2. Based on the values imm1 and imm0, the circuitry selects 604, 606 the specified High (“H”) or Low (“L”) order bits of the operands to supply to the multiplier 616. The circuitry can also perform XOR-ing 616, 614 of the High and Low portions of either operand if imm2 is set. The multiplier 616 stores output to the specified destination register 618.
Expressed as pseudo-code, the circuitry implements logic for an instruction having a syntax of:
dest=BMUL(source1,source2)imm8
where the imm8 modifier is composed of imm2, imm1, imm0 bits. The values of these bits instruct the logic to perform the following operations:
Src1_low � src2_low
Src1_low � src2_high
Src1_high � src2_low
Src1_high � src2_high
(src1_low ⊕ src1_high) � (src2_low ⊕
src2_high)
where, in a 64-bit register implementation, low corresponds to bits [31:0] and high corresponds to bits [63:32]. The circuitry like that shown can reduce shifting and masking used to access segment/constant values. However, a wide variety of other implementation of the binary polynomial multiplication instruction are easily constructed. Additionally, other implementations may feature different circuit components, feature a different syntax, and perform different operations on operands.
Implementations of techniques described above may also vary based on the byte arrangement and endianess of message bytes. For example, FIG. 7 illustrates message bytes 700 a ordered from low-order byte (byte-0) to high (byte-15) where the high order byte represents the next sequential byte of a message. However, as shown in the scenario, each byte within the message has a little-endian format 702 a. Thus, the sequence of bits within the message 700 a are not arranged in a linearly ascending or descending order of significance. This “saw-tooth” arrangement of bits, where the byte arrangement is the opposite of the bit endian-ness within a byte, may make computations more difficult.
To organize the bits into a linear sequence, a byte shuffle operation may be used. For example, as shown in FIG. 7, shuffling bytes of message 700 a yields message 700 b. Since both the bytes of message 700 b and the bits within the bytes of message 700 b are arranged in the same sequence of significance (high to low), the bits of message 700 a linearly descend from high to low significance. As shown, pseudo-code 704 features shuffle byte (PSHUFB) instructions 706, 708 that reorder bytes of a message portion to create a linear descending arrangement of bits.
FIG. 8 depicts another scenario where the bytes 902 feature a big-endian format and the bytes are arranged from low to high significance. While the bits proceed in a linearly increasing order of significance, from the least significant bit to the most significant, the bit ordering is the exact opposite of the arrangement of message 700 b in FIG. 7. Instead of rearranging the bits, however, FIG. 9 illustrates a technique that permits circuitry operating on the “reversed” message to proceed without time consuming bit or byte rearrangement. Briefly, due to the bit-agnostic property of polynomial multiplication (i.e., the columns are independent), the constants used can be computed to properly operate on the reversed message, obviating the need for bit-reflections or byte shuffles.
To illustrate, FIG. 9 shows two four-bit numbers a and b. As shown, polynomial multiplication of the bits of a and b yield the bit-values of byte c. FIG. 9 also depicts polynomial multiplication of bit-reflections of a and b, labeled ar and br, to yield the bit-values of byte d. As shown, the values of c and d, excluding the most-significant 0, mirror each other. That is, c0=d6, c1=d5, c2=d4, and c3=d3. In other words, d[6:0]=bitreflect(c[6:0]). Including the zero value of c7 and d7, d<<1=bitreflect(c). While FIG. 9 features 4-bit numbers, this relationship equally applies to larger numbers.
Circuitry can be constructed based on this relationship to permit processing of the “reverse” bit-ordering shown in FIG. 8 without bit reflections or byte shufflings. In other words, instead of rearranging the bit-sequence of the message, the procedure can operate on the bits, as is, by reflecting the constants, K, and shifting them to the left by one. Thus, as shown in FIG. 10, code 1000 performs a bit-reflection and shift of each K value to yield the rK values. This can be a one-time operation performed before processing of a message. As shown, the procedures 1000 uses the rK values in a polynomial multiplication operation with message segments similar to that shown in FIG. 3, though with constant values that reflect the bit-ordering.
The ability to operate on a reflected message may be used in other modular reduction schemes than that described above. For example, a reflected and shifted constant may be used in a scheme that folds a single segment per iteration instead of multiple segments. Additionally, the more general technique of processing a reflected bit sequence with binary polynomial multiplication of a bit reflected/shifted value may be used in a wide variety of applications.
The techniques described above can be implemented in a wide variety of logic. For example, the techniques may be implemented as circuitry (e.g., a processor element (e.g., a CPU (Central Processing Unit) or processor core) that executed program instructions disposed on a computer readable storage medium. While the logic was illustrated as programmatic instructions executed by processor circuitry, the techniques may be implemented in dedicated digital or analog circuitry (e.g., expressed in a hardware description language such as Verilog™), firmware, and/or as an ASIC (Application Specific Integrated Circuit) or Programmable Gate Array (PGA). Alternately, the circuitry may feature a combination of dedicated hardware and programmable execution (e.g., a processor that implements a program that uses a Galois-field (carry-less) multiplier or multiplier configured to handle carry-less multiplication.
The logic may be integrated within a discrete component such as a NIC (Network Interface Controller), framer, offload engine, storage processor, and so forth. For example, to process a received protocol data unit (PDU), a component may verify a CRC value included with the PDU. Alternately, for egress packets, the component may generate a CRC value for including in the PDU. Such components may include a PHY coupled to a MAC (media access controller) (e.g., an Ethernet MAC). As another example, these techniques may be implemented in blade circuitry for insertion into a chassis backplane.
Citas de patentes Patente citada Fecha de presentaci�n Fecha de publicaci�n Solicitante T�tuloUS39808749 May 197514 Sep 1976Burroughs CorporationBinary to modulo M translationUS4945537 *3 Jun 198831 Jul 1990Clarion Co., Ltd.Maximum length linearly occurring code sequence generatorUS494929428 Oct 198814 Ago 1990Thomson-CsfComputation circuit using residual arithmeticUS516697821 Feb 199124 Nov 1992U.S. Philips Corp.Encoding system according to the so-called rsa method, by means of a microcontroller and arrangement implementing this systemUS52747076 Dic 199128 Dic 1993Roger SchlaflyModular exponentiation and reduction device and methodUS5363107 *16 Jul 19938 Nov 1994Massachusetts Institute Of TechnologyStorage and transmission of compressed weather maps and the likeUS5384786 *2 Abr 199124 Ene 1995Cirrus Logic, Inc.Fast and efficient circuit for identifying errors introduced in Reed-Solomon codewordsUS5642367 *7 Feb 199424 Jun 1997Mitsubishi Semiconductor America, Inc.Finite field polynomial processing module for error control codingUS5920702 *24 Abr 19976 Jul 1999Sarnoff CorporationMethod of striping a data stream onto subsets of storage devices in a multiple user data distribution systemUS5942005 *8 Abr 199724 Ago 1999International Business Machines CorporationMethod and means for computationally efficient error and erasure correction in linear cyclic codesUS6128766 *12 Nov 19963 Oct 2000Pmc-Sierra Ltd.High speed cyclic redundancy check algorithmUS61855961 Abr 19986 Feb 2001Fortress U&T Ltd.Apparatus & method for modular multiplication & exponentiation based on Montgomery multiplicationUS622332010 Feb 199824 Abr 2001International Business Machines CorporationEfficient CRC generation utilizing parallel table lookup operationsUS639692626 Mar 199928 May 2002Nippon Telegraph & Telephone CorporationScheme for fast realization of encrytion, decryption and authenticationUS648419228 Ene 199919 Nov 2002Toyo Communication Equipment Co., Ltd.Root finding method and root finding circuit of quadratic polynomial over finite fieldUS6530057 *27 May 19994 Mar 20033Com CorporationHigh speed generation and checking of cyclic redundancy check valuesUS660941026 Sep 200126 Ago 2003Spalding Sports Worldwide, Inc.High strain rate tester for materials used in sports ballsUS666638116 Mar 200123 Dic 2003Hitachi, Ltd.Information processing device, information processing method and smartcardUS672177128 Ago 200013 Abr 2004Sun Microsystems, Inc.Method for efficient modular polynomial division in finite fields f(2{circumflex over ( )}m)US6728052 *26 Jun 200127 Abr 2004Hitachi, Ltd.Recording/reproducing apparatus, error correcting coding method and information recording methodUS673231723 Oct 20004 May 2004Sun Microsystems, Inc.Apparatus and method for applying multiple CRC generators to CRC calculationUS67959465 May 200021 Sep 20043Com CorporationFast frame error checker for multiple byte digital data framesUS690455822 Feb 20027 Jun 2005Agilent Technologies, Inc.Methods for computing the CRC of a message from the incremental CRCs of composite sub-messagesUS702759718 Sep 200111 Abr 2006Cisco Technologies, Inc.Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuitsUS702759819 Sep 200111 Abr 2006Cisco Technology, Inc.Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuitsUS70587875 May 20036 Jun 2006Stmicroelectronics S.R.L.Method and circuit for generating memory addresses for a memory bufferUS7171604 *30 Dic 200330 Ene 2007Intel CorporationMethod and apparatus for calculating cyclic redundancy check (CRC) on data using a programmable CRC engineUS718777016 Jul 20026 Mar 2007Cisco Technology, Inc.Method and apparatus for accelerating preliminary operations for cryptographic processingUS7190681 *9 Jun 200313 Mar 2007Wu William WError coding in asynchronous transfer mode, internet and satellitesUS724328925 Ene 200310 Jul 2007Novell, Inc.Method and system for efficiently computing cyclic redundancy checksUS7343541 *14 Ene 200411 Mar 2008Broadcom CorporationData integrity in protocol offloadingUS742869320 Oct 200423 Sep 2008Fujitsu LimitedError-detecting encoding and decoding apparatus and dividing apparatusUS745800622 Sep 200325 Nov 2008Avago Technologies General Ip (Singapore) Pte. Ltd.Methods for computing the CRC of a message from the incremental CRCs of composite sub-messagesUS746111511 Mar 20032 Dic 2008Sun Microsystems, Inc.Modular multiplierUS754321411 Feb 20052 Jun 2009Marvell International Ltd.Method and system for performing CRCUS2002005323226 Sep 20019 May 2002Axe John D.High strain rate tester for materials used in sports ballsUS2002012683822 Ene 200212 Sep 2002Atsushi ShimboModular exponentiation calculation apparatus and modular exponentiation calculation methodUS2002014420827 Feb 20023 Oct 2002International Business Machines CorporationSystems and methods for enabling computation of CRC' s N-bit at a timeUS2003016744022 Feb 20024 Sep 2003Cavanna Vicente V.Methods for computing the CRC of a message from the incremental CRCs of composite sub-messagesUS2003020265730 Abr 200230 Oct 2003She Alfred C.Method and apparatus of fast modular reductionUS2003021272911 Mar 200313 Nov 2003Sun Microsystems, Inc.Modular multiplierUS2004008325125 May 200129 Abr 2004Geiringer Felix EgmontParallel modulo arithmetic using bitwise logical operationsUS2005004413423 Jul 200324 Feb 2005Krueger Jon H.High-performance hashing systemUS2005013836819 Dic 200323 Jun 2005Sydir Jaroslaw J.Method and apparatus for performing an authentication after cipher operation in a network processorUS2005014972530 Dic 20037 Jul 2005Intel CorporationMethod and apparatus for aligning ciphered dataUS2005014974429 Dic 20037 Jul 2005Intel CorporationNetwork processor having cryptographic processing including an authentication bufferUS2005014981219 Nov 20047 Jul 2005Honeywell International Inc.Message error verification using checking with hidden dataUS20050154960 *30 Dic 200314 Jul 2005Sydir Jaroslaw J.Method and apparatus for calculating CRC on data using a programmable CRC engineUS2006005921916 Sep 200416 Mar 2006Koshy Kamal JMethod and apparatus for performing modular exponentiationsUS2006028274324 May 200514 Dic 2006Michael KounavisInstructions for performing modulo-2 multiplication and bit reflectionUS2006028274425 May 200514 Dic 2006Michael KounavisTechnique for performing cyclic redundancy code error detectionUS200700835857 Oct 200512 Abr 2007Elliptic Semiconductor Inc.Karatsuba based multiplier and methodUS2007015079523 Dic 200528 Jun 2007King Steven RPerforming a cyclic redundancy checksum operation responsive to a user-level instructionUS2007015703030 Dic 20055 Jul 2007Feghali Wajdi KCryptographic system componentUS2007029760127 Jun 200627 Dic 2007Hasenplaugh William CModular reduction using foldingUS2008009202012 Oct 200617 Abr 2008Hasenplaugh William CDetermining message residue using a set of polynomialsUS2008014481114 Dic 200619 Jun 2008Intel CorporationMethod for Simultaneous Modular ExponentiationsUS2009001934213 Jul 200715 Ene 2009Shay GueronDetermining a Message ResidueUS2009015778418 Dic 200718 Jun 2009Vinodh GopalDetermining a message residueUS2009016454621 Dic 200725 Jun 2009Vinodh GopalMethod and apparatus for efficient programmable cyclic redundancy check (crc)US2009016899928 Dic 20072 Jul 2009Brent BoswellMethod and apparatus for performing cryptographic operationsWO2008002828A221 Jun 20073 Ene 2008Gunnar GaubatzModular reduction using foldingWO2009012050A230 Jun 200822 Ene 2009Intel CorpDetermining a message residueWO2009082598A12 Dic 20082 Jul 2009Vinodh GopalDetermining a message residueWO2009085489A224 Nov 20089 Jul 2009Wajdi FeghaliMethod and apparatus for efficient programmable cyclic redundancy check (crc)* Citada por examinadorOtras citasReferencia1"Number Theory and Public Key Cryptography," Introduction to Number Theory, Apr. 1996, pp. 1-12.2Barrett, "Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor," Proceedings on Advances in cryptology-CRYPTO '86,Copyright (c) 1998, Springer-Verlag, Berlin 1987, pp. 311-323.3Bosselaers et al., "Comparsion of three modular reduction function," Comparative Description and Evaluation, Katholieke Universiteit Leuven, Department of Electrical Engineering-ESAT Kardinaal Mercierlaan, Oct. 25, 1993, pp. 1-12.4Campobello et al., "Parallel CRF Realization," IEEE Transactions on Computers, vol. 52, No. 10, Oct. 2003, Published by the IEEE Computer Society, pp. 1312-1319.5Chin-Bou et al., "Design and Implementation of Long-Digit Karatsuba's Multiplication Alogorithm Using Tensor Product Formulation," Workshop on Compiler Techniques for High Performance Computing, 2003, pp. 1-8.6Dhem, "Design of an Efficient Public-Key Cryptographic Library for RISC-Based Smart Cards," Faculte Des Sciences appliquees Laboratoire de Microelectronique, Louvain-la-Neuve, Belgium, May 1998, 198 pages.7Federal Information Processing Standards Publication 197, Announcing the Advanced Encryption Standard (AES), Nov. 26, 2001, 51 pages.8Fischer et al., "Duality Between Multiplication and Modular Reduction," Infineon Technologies AG, Secure Mobile Solutions, Munich, Germany, Intel Corporation, Systems Technology Laboratory, Hillsboro, OR, Mar. 2005, pp. 1-13.9Gordon, "A survey of fast exponentiation methods," Center for Communications Research, Dec. 30, 1997, pp. 1-22.10International Preliminary Report on on Patentability received for PCT Patent Application No. PCT/US2007/071829, mailed on Jan. 15, 2009, 7 pages.11International Preliminary Report on Patentability for PCT Patent Application No. PCT/US2008/085284, mailed on Jul. 1, 2010, 6 pages.12International Preliminary Report on Patentability received for PCT Application No. PCT/US2008/084571 mailed on Jul. 1, 2010, 6 pages.13International Preliminary Report on Patentability received for PCT Patent Application No. PCT/US2008/068801, mailed on Jan. 28, 2010, 6 pages.14International Search Report & Written Opinion received for PCT Application No. PCT/US2007/071829, received on Dec. 12, 2007, 10 Pages.15International Search Report and Written Opinion received for PCT Patent Application No. PCT/US2008/068801, mailed on Dec. 31, 2008, 10 pages.16International Search Report and Written Opinion received for PCT Patent Application No. PCT/US2008/084571, mailed Jun. 18, 2009, 11 pages.17International Search Report/Written Opinion for PCT Patent Application No. PCT/US2008/085284, mailed on May 18, 2009, pp. 11.18Koc et al., "Analyzing and Comparing Montgomery Multiplication Algorithms," IEEE Micro, vol. 16, No. 3, 26-33, Jun. 1996, pp. 1-18.19Koopman et al., "Cyclic Redundancy Code (CRC) Polynomial Selection for Embedded Networks," The International Conference on Dependable Systems and Networks, DSN-2004, pp. 1-10.20Kounavis et al., "A Systematic Approach to Building High Performance Software-based CRC Generators," Proceedings of the 10th IEEE Symposium on Computers and Communications, ISCC 2005, pp. 855-862.21Lin et al., "High-Speed CRC Design for 10 Gbps applications," ISCAS 2006, IEEE, pp. 3177-3180.22Montgomery, "Five, Six, and Seven-Term Karatsuba-Like Formulae," IEEE Transactions on Computers, vol. 54, No. 3, Mar. 2005, 8 pages.23Montgomery, "Modular Multiplication Without Trial Division," Mathematics of 'Computation, vol. 44, No. 170, Apr. 1985, pp. 519-521.24Nedjah et al., "A reconfigurable recursive and efficient hardware for Karatsuba-Ofman's multiplication algorithm", Proceedings of 2003 IEEE Conference on Control Applications, vol. 2, Jun. 23-25, 2003, pp. 1076-1081.25Nedjah et al., "A Review of Modular Multiplication Methods and Respective Hardware Implementation," Informatica, vol. 30, No. 1, 2006, pp. 111-129.26Office Action Received for Chinese Patent Application No. 200610172839.9, mailed on Apr. 15, 2010, 4 Pages of Chinese Office Action and 5 Pages of English Translation.27Office Action Received for Chinese Patent Application No. 200610172839.9, mailed on Feb. 6, 2009, 3 Pages of Chinese Office Action and 5 Pages of English Translation.28Office Action Received for Chinese Patent Application No. 200610172839.9, mailed on Jan. 8, 2010, 3 Pages of Chinese Office Action and 5 Pages of English Translation.29Office Action Received for Chinese Patent Application No. 200610172839.9, mailed on Jul. 30, 2010, 5 Pages of English Translation.30Office Action Received for Chinese Patent Application No. 200610172839.9, mailed on Sep. 18, 2009, 4 Pages of Chinese Office Action and 5 Pages of English Translation.31Office Action Received for Taiwan Patent Application No. 096122784, mailed on Oct. 18, 2010, 10 Pages of Taiwan Office Action including 4 Pages of English Translation.32Office Action Received for U.S. Appl. No. 11/476,432, mailed on May 26, 2010, 13 pages.33Office Action Received for U.S. Appl. No. 11/476,432, mailed on Oct. 28, 2009, 24 pages.34Office Action received for U.S. Appl. No. 11/610,919, mailed on Jul. 8, 2010, 7 pages.35Office Action received for U.S. Appl. No. 11/777,538, mailed on Jan. 8, 2010, 9 pages.36Office Action received for U.S. Appl. No. 11/777,538, mailed on Jul. 9, 2010, 6 pages.37Office Action received for U.S. Appl. No. 11/959,142, mailed on Jun. 30, 2010, 11 pages.38Park et al., "Analysis of the Variable Length Nonzero Window Method for Exponentiation," 1999 Elsevier Science, Computers & Mathematics with Applications, vol. 37, Issue 7, Apr. 1999, pp. 21-29.39Phatak et al., "Fast Modular Reduction for Large Wordlengths via One Linear and One Cyclic Convolution," Proceedings of the 17th IEEE Symposium on Computer Arithmetic, 2005, pp. 179-186.40Ramabadran et al., "A Tutorial on CRC Computations," Micro, IEEE, IEEE Computer Society, Aug. 1988, pp. 62-75.41Sedlak, "The RSA Cryptography Processor," Lecture Notes in Computer Science, Proceedings of the 6th annual international conference on Theory and application of cryptographic techniques, EUROCRYPT'87, 1987, Springer-Verlag Berlin, Heidelberg, pp. 95-105.42Sprachmann, "Automatic Generation of Parallel Circuits," IEEE Design and Test of Computers, May-Jun. 2001, pp. 108-114.43Tenca et al., "A Scalable Architecture for Montgomery Multiplication," Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems, Lecture Notes in Computer Science, No. 1717, Springer-Verlag London, UK, 1999, pp. 94-108.44Weimerskirch et al., "Generalizations of the Karatsuba Algorithm for Polynomial Multiplication," communication Security Group, Department of Electrical Engineering & Information Sciences, Bochum, Germany, Mar. 2002, pp. 1-23.45Williams, "A Painless Guide to CRC Error Detection Algorithms," Version 3, Aug. 19, 2003, Copyright 1993, 37 pages.Clasificaciones Clasificaci�n de EE.UU.714/781, 714/751 Clasificaci�n internacionalH03M13/03 Clasificaci�n cooperativaH03M13/091, G06F7/724 Clasificaci�n europeaG06F7/72F, H03M13/09BEventos legales FechaC�digoEventoDescripci�n15 May 2009ASAssignmentOwner name: INTEL CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GOPAL, VINODH;WOLRICH, GILBERT;FEGHALI, WAJDI;AND OTHERS;REEL/FRAME:022690/0106;SIGNING DATES FROM 20081028 TO 20081108Owner name: INTEL CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GOPAL, VINODH;WOLRICH, GILBERT;FEGHALI, WAJDI;AND OTHERS;SIGNING DATES FROM 20081028 TO 20081108;REEL/FRAME:022690/01061 Abr 2015FPAYFee paymentYear of fee payment: 4GirarImagen originalP�gina principal de Google - Sitemap - Descargas masivas de USPTO - Pol�tica de privacidad - Condiciones de servicio - Acerca de Google Patentes - Enviar sugerenciasDatos proporcionados por IFI CLAIMS Patent Services