Source: http://www.google.com/patents/US7720444?dq=inassignee:doubleclick
Timestamp: 2017-04-24 14:18:22
Document Index: 381500349

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US7720444 - Adaptive radio transceiver with a local oscillator - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including...http://www.google.com/patents/US7720444?utm_source=gb-gplus-sharePatent US7720444 - Adaptive radio transceiver with a local oscillatorAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7720444 B2Publication typeGrantApplication numberUS 11/340,038Publication dateMay 18, 2010Filing dateJan 26, 2006Priority dateOct 21, 1999Fee statusPaidAlso published asUS6404293, US6417737, US6608527, US7031668, US7555263, US7970358, US8041294, US20030042984, US20030067359, US20060205374, US20090286487, US20100295598Publication number11340038, 340038, US 7720444 B2, US 7720444B2, US-B2-7720444, US7720444 B2, US7720444B2InventorsHooman Darabi, Ahmadreza Rofougaran, Maryam RofougaranOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (71), Non-Patent Citations (1), Referenced by (11), Classifications (28), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetAdaptive radio transceiver with a local oscillator
US 7720444 B2Abstract
This application is a continuation of application Ser. No. 10/165,464, filed Jun. 7, 2002 now U.S. Pat. No. 7,031,668 which is a continuation of application Ser. No. 09/691,633, filed Oct. 18, 2000, now issued U.S. Pat. No. 6,404,293 B1, which is a continuation of co-pending application Ser. No. 09/634,552, filed Aug. 8, 2000, which claims priority to and benefit from provisional Application No. 60/160,806, filed Oct. 21, 1999; Application No. 60/163,487, filed Nov. 4, 1999; Application 60/163,398, filed Nov. 4, 1999; Application No. 60/164,442, filed Nov. 9, 1999, Application No. 60/164,194, filed Nov. 9, 1999; Application No. 60/164,314, filed Nov. 9, 1999; Application No. 60/165,234, filed Nov. 11, 1999; Application No. 60/165,239, filed Nov. 11, 1999; Application No. 60/165,356, filed Nov. 12, 1999; Application No. 60/165,355, filed Nov. 12, 1999; Application No. 60/172,348, filed Dec. 16, 1999; Application No. 60/201,335, filed May 2, 2000; Application No. 60/201,157, filed May 2, 2000; Application No. 60/201,179, filed May 2, 2000; Application No. 60/202,997, filed May 10, 2000; and Application No. 60/201,330, filed May 2, 2000. The above-identified applications are hereby incorporated herein by reference in their entirety.
In accordance with an exemplary embodiment of the present invention, a transceiver utilizes a combination of frequency planning, circuit design, layout and implementation, differential signal paths, dynamic calibration, and self tuning to achieve robust performance over process variation and interference. This approach allows for the full integration of the transceiver onto a single IC for a low cost, low power, reliable and more compact solution. This can be achieved by (I) moving external bulky and expensive image reject filters, channel select filters, and balms onto the chip; (2) reducing the number of off-chip passive elements such as capacitors, inductors, and resistors by moving them onto the chip; and (3) integrating all the remaining components onto the chip. As those skilled in the art will appreciate, the described exemplary embodiments of the transceiver do not require integration into a single IC and may be implemented in a variety of ways including discrete hardware components.
FIG. 2 shows a block diagram of the transceiver in accordance with an embodiment of the invention. The described exemplary embodiment is integrated into a single IC. For ease of understanding, each component coupled to the controller is shown with a “program” designation or a “calibration” designation. These designations indicate whether the component is programmed by the controller or calibrated by the controller. In practice, in accordance with the described exemplary embodiment of the present invention, the components that are programmed receive the most significant bits (MSBs) and the components that are calibrated receive the least significant bits (LSBs). The components requiring both programming and calibration receive the entire digital output from the controller. As those skilled in the art will appreciate, any number of methodologies may be used to deliver programming and calibration information to the individual components. By way of example, a single controller bus could be used having the programming and or calibration data with the appropriate component addresses.
In the described exemplary embodiment, the VCO frequency is sufficiently separated (in frequency) from the RF frequency generated by the transmitter 12 to prevent VCO pulling and injection lock of the VCO. Transmitter leakage can pull the VCO frequency toward the RF frequency and actually cause the VCO to lock to the RF signal if their frequencies are close to each other. The problem is exasperated if the gain and tuning range of the VCO is large. If the frequency of the RF clocks is fLO, then the VCO frequency can be defined as: fVCO=NfLO/(N+1). This methodology is implemented with a divide by N circuit 50 coupled to the output of the VCO 48 in the PLL 43. The output of the VCO 48 and the output of the divide by N circuit 50 are coupled to a complex mixer 52 where they are multiplied together to generate the RF clocks. A filter 53 can be positioned at the output of the complex mixer to remove the harmonics and any residual mixing images of the RF clocks. The divide by N circuit can be programmable via the controller through the select input. For example, if N=2, then fVCO=(⅔) fLO, and if N=3, then fVCO=(¾) fLO.
A VCO the frequency set at ⅔ the frequency of the RF clocks works well in the described exemplary embodiment because the transmitter output is sufficiently separated (in frequency) from the VCO frequency. In addition, the frequency of the RF clocks is high enough so that its harmonics and any residual mixing images such as fVCO×1−(1/N)), 3 fVCO×1+(1/N), and 3 fVCO×1−(1/N)) are sufficiently separated (in frequency) from the transmitter output to relax the filtering requirements of the RF clocks. The filtering requirements do not have to be sharp because the filter can better distinguish between the harmonics and the residual images when they are separated in frequency. Programming the divide by N circuit 50 also provides for the quadrature outputs of the divide by N circuit. Otherwise, with an odd number programmed, the outputs of the divide by N circuit 50 would not be quadrature. For an odd number, the divider 50 outputs will be differential, but will not be 90 degrees out of phase, i.e., will not be I-Q signals.
In the described exemplary embodiment, the RF clocks are generated in the LO generator 14. This can be accomplished in various fashions including, by way of example, either generating the RF clocks in the VCO or using a polyphase circuit to generate the RF clocks. Regardless of the manner in which the RF clocks are generated, the mixer 52 will produce a spectrum of frequencies including the sum and difference frequencies, specifically, fVCO×(1(+(1/N)) and its image fVCO×(1−(1/N)). To reject the image, the mixer 52 can be configured as a double quadrature mixer as depicted in FIG. 3. The double quadrature mixer includes one pair of mixers 55, 57 to generate the Q-clock and a second pair of mixers 59, 61 to generate the I-clock. The Q-clock mixers utilizes a first mixer 55 to mix the I output of the VCO 48 (see FIG. 2) with the Q output of the divider 50 and a second mixer 57 to mix the Q output of the VCO with the I output of the divider. The outputs of the first and second mixers are connected together to generate the Q-clock. Similarly, the I-clock mixers utilizes a first mixer 59 to mix the I output of the divider with the I output of the VCO and a second mixer 61 to mix the Q output of the divider with the Q output of the VCO. The outputs of the first and second mixers are connected together to generate the I-clock. This technique provides very accurate I-Q clocks by combination of quadrature VCO and filtering. Because of the quadrature mixing, the accuracy of the I-Q clocks is not affected by the VCO inaccuracy, provided that the divide by N circuit generates quadrature outputs. This happens for even divide ratios, such as N=2.
P i,BP =BW·P i,LP +jω 0=αi ·BW+j(ω0+βi ·BW) (6)
Y i = 1 V = 1 R z - C z ω ( 13 ) which indicates that the filter will have a zero equal to 1/RzCz at the jΦ axis.
ωz1,2=ω0±ωz,LP ·BW (15)
Referring to FIG. 12( a), each capacitor can be implemented with a capacitor 148 connected in parallel with a number of switchable capacitors 150, 152, 154, 156. The capacitance, and thereby the center frequency of the complex filter, can be varied by selectively switching in or out the capacitors based on a four-bit binary code. Each bit is used to switch one of the parallel capacitors from the circuit In the described exemplary embodiment, the capacitor 148 provides a capacitance of Cu/2. Capacitor 150 provides a capacitance of Cu/2. Capacitor 152 provides a capacitance of Cu/4. Capacitor 154 provides a capacitance of Cu/8. Capacitor 156 provides a capacitance of Cu/16. This provides ±50% tuning range with ±3% tuning accuracy. Due to discrete nature of the tuning scheme, there may be some error in the center frequency (±1/(2×2n) for n-bit array). This inaccuracy can be tolerated with proper design.
Referring to FIG. 12( b), each resistor can be implemented with a series of switchable resistors 158, 160, 162, 164, 166. Resistor 166 provides a resistance of R. Resistor 164 provides a resistance of 2 R. Resistor 162 provides a resistance of 4 Ru. Resistor 160 provides a resistance of 8 Ru. Resistor 158 provides a resistance of 16 R. In the described exemplary embodiment, the resistance can be varied between Ru and 31×Ru in incremental steps equal to Ru by selectively bypassing the resistor based on a five-bit binary code.
H ( jω ) = n F n A 1 + jn c n F R u C u ω - j n F n Q ( 16 ) Therefore, the biquad stage gain (A), center frequency (ω0), and bandwidth (BW) will be equal to:
ΔRSSI=C log A2n (30)
V in 1 = S ( A ) n - m ( 33 ) V in 2 = S ( A ) n - m - 1 ( 34 ) (Ideal)RSSI2−RSSI1=log (A)2 (35)(Approximated)RSSI2−RSSI1=β2 S 2 (36)
Capacitances associated with bias resistors may also be addressed. Consider a typical distributed model for a polysilicon (“poly” for short) resistor. Around 4fF to substrate can be associated with every kilo-ohm of resistance in a poly resistor. This means that, for example in a 2 OKohm resistor, around 80fF of distributed capacitance to the substrate exists. This can contribute to power loss because part of the power will be drained into the substrate. One way of biasing the input stage and the output stage is through a resistive voltage divider as shown in FIG. 26( a). The biasing of the input stage is shown for the transistor 616 in FIG. 25, however, those skilled in the art will readily appreciate that the same biasing circuit can be used for the transistor 614 (FIG. 25). One drawback from this approach, however, is that the gate of the transistor will see the capacitance from the two resistors 658, 660 of the voltage divider. Capacitor 662 is a coupling capacitor, which couples the previous stage to the voltage divider. Switch 664 is for powering down the stage of the power amplifier that is connected to the voltage divider. The switch 664 is on in normal operation and is off in power down mode.
Because of the hard switching action of the buffers, the mixers will effectively be switched by a square-wave signal. Thus, the divider output will be upconverted by the main harmonic of VCO (f1), as well as its odd harmonics (n×f1), with a conversion gain of 1/n. In addition, at the input of the mixer, because of the nonlinearity of the mixers, and the buffers preceding the mixers, all the odd harmonics of the input signals to the mixers will exist. Even harmonics, both at the LO and the input of the mixers can be neglected if a fully balanced configuration is used. Therefore, all the harmonics of VCO (n×f1) will mix with all the harmonics of input (m×f2), where f2 is equal to f1/N. Because of the quadrature mixing, at each upconversion only one sideband appears at the mixer output. Upper or lower sideband rejection depends on the phase of the input and LO at each harmonic. For instance, for the main harmonics mixed with each other, the lower sideband is rejected, whereas when the main harmonic of the VCO mixes with the third harmonic of the divider output signal, the upper sideband is rejected.
1st: f1 f1 × (1 + 1/N)
3rd: f1 f1 × (3 − 1/N)
5th: 5f1 f1 × (5 + 1/N)
−Cos(ω1 t)·⅓Cos(3ω1 t)−Sin(ω1 t)·⅓Sin(3ω1 t)→−⅓Cos(2ω1 t) (47)
Cos(ω1 t)·⅓Sin(3ω1 t)−Sin(ω1 t)·⅓Cos(3ω1 t)→−⅓Sin(2ω1 t) (48)
The factor ⅓ appears in the above equations because the third harmonic of a square-wave has an amplitude which is one third of the main harmonic. Comparing equation (46) with equation (48), the two products are added in equation (46), while they are subtracted in equation (47). The reason is that for the main harmonic of the VCO, quadrature outputs have phases of 0 and 90°, whereas for the third harmonic, the phases are 0 and 270°. The same holds true for equation (45) and equation (47). The two cosines in equation (45) and equation (47), when added, give a cosine at 2ωi with an amplitude of 2/3, yet the two sinewaves in equation (46) and equation (48) when added, give a component at 2ωi with an amplitude of 4/3. Therefore, a significant amplitude imbalance exists at the I and Q outputs of the mixers. When these signals pass through the nonlinear buffer at the mixers output, the amplitude imbalance will be reduced. However, because of the AM to PM conversion, some phase inaccuracy will be introduced. The accuracy can be improved with a quadrature generator, such as a polyphase filter, after the mixers. A polyphase filter, however, is lossy, especially at high frequency, and it can load its previous stage considerably. This increases the LO generator power consumption significantly, and renders the choice of N=1 unattractive for embodiments of the present invention employing a low-IF receiver architecture with quadrature LO signals.
The following discussion changes based on the Q value. Considering a Q of about 5 for the inductor, with f0=1.5f1, the spur located at 2.5f1 is rejected by about 15 dB by each LC a circuit. This spur is produced at the LO generator output due to the mixing of the VCO third harmonic (at 3f1) with the divider output (at 0.5f1). This signal is attenuated by 10 dB since the third harmonic of a square-wave is one third of the main harmonic, 15 dB at the LC resonator at the mixers output tuned to 1.5f1, and another 15 dB at the output of the buffers (893, 895 in FIG. 33). This gives a total rejection of 40 dB. When applied to the mixers in the transmitter, this LO generator output will upconvert the baseband data to 2.5f1. With LC filters (not shown) positioned at the upconversion mixers and PA output in the transmitter, another 15+15=30 dB rejection is obtained (FIG. 33).
FIG. 33( a) shows a signal passing through a limiting buffer 910 (such as the buffers implemented in the LO generator). When a large signal at a frequency off accompanied with a small interferer at a frequency of Δf 902 away pass through a limiting buffer, at the limiter output the interferer produces two tones ±Δf 914, 916 away from the main signal, each with 6 dB lower amplitude. Therefore, the spur at 2.5f1 will actually be 10+15+15+6=46 dB attenuated when it passes through the buffer, instead of the 40 dB calculated above. It will also produce an image at 0.5f1, which is 10+15+22+6 53 dB lower than the main signal. This will dominate the spur at 0.5f1, because of the third harmonic of the divider mixed with the VCO signal, which is more than 75 dB lower than the main signal.
Since the buffer is nonlinear, another major spur at the LO generator output is the third harmonic of the main signal located at 3×1.5f1 This signal will be 10+22=32 dB lower than the main harmonic. The 22 dB rejection results from an LC circuit (not shown) tuned to 1155f1 (equation (49)) in the buffer. This undesired signal will not degrade the LO generator performance, since even if a perfect sinewave is applied to upconversion (or downconversion) mixers, due to hard switching action of the buffer, the mixer is actually switched by a square-wave whose third harmonic is only 10 dB lower. Thus, if a nonlinear PA is used in the transmitter, even with a perfect input to the PA, the third harmonic at the transmitter output will be 10+22+10=42 dB lower. The first 10 dB is because the third harmonic of a square-wave is one third of the main one, the 22 dB is due to the LC filter at the PA output, and the last 10 dB is because the data is spread in the frequency domain by three times. Any DC offset at the mixer input in the transmitter is upconverted by the LO, and produces a spur at f1. This spur can be attenuated by 13 dB for each LC circuit used (equation (49)). In addition, the signal at the mixer input in the transmitter is considerably larger (about 10-20 times) than the DC offset. Thus the spur at f1 will be about 13+13+26=52 dB lower than the main signal. All other spurs given in Table 1 are more than 55 dB lower at the LO generator output. The dominant spur is the one at 2.5f1 which is about 46 dB lower than the main signal.
V out — I=Cos(ω2 t)·Cos(ω1 t+θ)−Sin(ω2 t)·Sin(ω1 t) (50)
V out — Q=Cos(ω2 t)·Sin(ω1 t)+Sin(ω2 t)·Cos(ω1 t+θ) (51)
The above equations show that regardless of the value of θ, the outputs are always in quadrature. However, other effects should be evaluated. First, a spur at ω1−ω2=0.5ω1 is produced at the output. This spur can be attenuated by 2×22=44 dB by the LC filters at the mixer and its buffer outputs. Thus, for 60 dB rejection, the single sideband mixers need to provide an additional 16 dB of rejection (about 0.158). Based on equation (53), tan (θ/2)=0.158, or θ≈18°, phase accuracy of better than 18° can generally be achieved. Second, phase error at the VCO output lowers the mixer gain (term Cos (θ/2) in equation (52) or (53)). For a phase error of 18°, the gain reduction is, however, only 0.1 dB, which is negligible. For θ=90° (a single-phase VCO), both sidebands are equally upconverted at the mixer output. However, the LC filters reject the lower sideband by about 44 dB. The mixer gain will also be 3 dB lower. This will slightly increase the power consumption of the LO generator. If θ=180° (the VCO I and Q outputs are switched), the lower sideband is selected, and the desired sideband is completely rejected.
σ A ≈ ( σ θ ) 2 2 ( 57 ) where σA is the standard deviation of the output amplitude, and σθ is the phase standard deviation in radians. Equation (57) denotes that the phase inaccuracy in the VCO and divider has a second order effect on the LO generator. For instance, if θ1 and θ2 are on the same order and about 10°, the amplitude imbalance of the output signals will be only about 1.5%. In this case, the lower sideband will be about 15 dB rejected by the mixers, which will lead to a total attenuation of about 22+22+15=59 dB. This shows that the LO generator is robust to phase errors at the VCO or divider outputs, since typically phase errors of less than 5° can be obtained on chip.
With an input dynamic range of 50 dB, the RSSI circuit is designed to detect the levels of rejection provided by the polyphase filtering. The outputs of RSSI block 284 and RSSI block 285 are coupled to a comparator 280 where the level of signal rejection of each polyphase filter is compared by comparator 280. The outputs of the RSSI blocks are also coupled to the control logic 286. The control logic 286 determines from the RSSI outputs which polyphase filter has a lower amount of signal suppression. Then, the control logic 286 adjusts the frequency tuning of that filter in an incremental step via the control logic 286. This is done by either increasing the tuned frequency of the first filter (polyphase A) filter 280, or by decreasing the tuned frequency of the second filter (polyphase B) 282 by changing the appropriate 4-bit control word. This process continues in successive steps until the 4-bit control word in each branch are identical, at which point, the RC values of the two polyphase filters are equal. The 4-bit control word provides a maximum deviation of only ±5%.
Two branches of polyphase filtering are used in this algorithm. Two 4-bit control words are used to control the value of the capacitances in each polyphase filter. The initial control words set the capacitance in the first filter (Polyphase A) to its maximum value and the capacitance in the second filter (Polyphase B) to its minimum value. This provides an initial condition in which the filters have maximum signal suppression set at frequencies (ωlow and ωhigh) that are approximately ±40% of the frequency of the input signal XIN for the case of nominal process variation. For a sinusoidal input XIN the calibration circuit depicted in FIG. 40 would require only a single-stage polyphase filter in each branch. The single-stage filters would attenuate the sinusoid input signal, generating outputs at XA and XB with the dominant one still at the same frequency as the input signal. However, the reference clock from the LO generator is a digital rail-to-rail clock. Because the input is not a pure sinusoid, multiple-stage filters may provide greater calibration accuracy. In the case of a single-stage filter with a digital clock, the filter would suppress the fundamental frequency component at ωin to a significant degree but the harmonics would pass through relatively unaffected. The RSSI block would then detect and limit the third harmonic component of the input signal at 3ωin, as it becomes the dominant frequency component after the fundamental is suppressed. This could result in an inaccurate calibration code.
FIG. 42 shows an exemplary embodiment of the bandgap calibration circuit. The bandgap calibration circuit uses the reference clock provided from the LO generator and a reference resistor RREF 236 to adjust a tunable resistance value RPOLY 238 in a compare-and-increment loop until an optimum value is obtained. In embodiments of the present invention which are integrated into a single IC, the reference resistor RREF 236 can be off-chip to provide improved calibration accuracy. A 4-bit control word is output to accurately calibrate the resistors in the transmitter, receiver and LO generator within ±2%. Transistors 224, 226, 228, 230, 232, 234 form a cascode current with a reference current IREF. The transistors 224, 230 each have their gates tied to their respective sources to set up the reference current IREF. By tying the gates of the transistors 224, 230, respectively to the gates of the transistors 226, 232, the reference current IREF is mirrored to the reference resistor RREF 236. Similarly, by tying the gates of the transistors 228, 234, respectively to the gates of the transistors, the reference current IREF is also mirrored to the tunable resistor RPOLY 238. The voltage generated across the tunable resistor RPOLY 238 is compared, using a latched comparator 240, to the voltage generated across the reference resistor RREF 236. The value of the tunable resistor RPOLY 238 is incremented in successive steps, preferably, every 0.5 μs, through the utilization of control logic 242 that is clocked, by way of example, at 2 MHz. This process continues until the voltage VPOLY across the tunable resistor RPOLY 238 matches the voltage VREF across the off chip reference resistor RREF 236 causing the output of the comparator to change states and disable the control logic 242. Once the control logic is disabled, the 4-bit control word can be used to accurately calibrate the resistors in the transmitter, receiver and LO generator.
The clock signals used by the calibration circuit are generated by first dividing the reference clock input into the controller from the LO generator down in frequency, and then converting the result into different phases for the comparison and increment phases of calibration. This bandgap calibration circuit provides accurate resistance values for use in various on-chip circuit implementations because resistor scaling and matching on the same integrated circuit can be well controlled with proper layout techniques. The bandgap calibration circuit provides a resistor tuning range of approximately ±30%, which is sufficient to cover the range of process variation typical in semiconductor fabrication. With a 4-bit control word generating 24 possible resistance values, the calibration is completed within (2 MHz)−1(24−1)=7.5 ms. The calibration circuit can be powered down when the optimal resistance value has been obtained.
In the transmitter, receiver and LO generator non-silicided polysilicon resistors can be used. As those skilled in the art will appreciate, other resistor technologies can also be used. Non-silicided polysilicon resistors have a high sheet resistance of 200-Ω/square along with desirable matching properties. A switching resistor array as shown in FIG. 44 can be used to calibrate a resistor. The array includes serial connected resistors 208, 210, 212, 214, 216, which, by way of example, have resistances of 2200Ω, 1100Ω, 550Ω, 275Ω, and 137Ω, respectively. The resistors 210, 212, 214, 216 include a bypass switch for switching the resistors in and out of the array. The switch positions are nominally selected to produce an equivalent of 3025Ω. This resistance value has been chosen as a convenience to match the value used in generating an accurate bandgap reference current. A 4-bit calibration code is used to control the total resistance in this array. As seen in FIG. 44, the resistances are binary-weighted in value and the accurate scaling of each incremental resistance results by placing the largest resistor (2200Ω) 208 in series to generate each value. In the described embodiment, the incremental resistances shown in FIG. 44 are chosen so that the total resistance in the array covers a range 30% above and below its nominal value, with a maximum resistance error of ±2% determined by the incremental resistance switched by the LSB. The range of resistance covered by the array is sufficient to cover typical process variations in a semiconductor process. A series resistive array may be desirable as opposed to a parallel resistive array because of the smaller area occupied on the wafer.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3909527Sep 18, 1973Sep 30, 1975Mitsubishi Electric CorpFrequency shift keying system and methodUS3932814May 20, 1974Jan 13, 1976Takeda Riken Kogyo KabushikikaishaHeterodyne receiver systemUS4129832Jun 20, 1977Dec 12, 1978Harris CorporationMethod and means for linearizing a voltage controlled oscillator sweep generatorUS4283739Aug 30, 1979Aug 11, 1981Texas Instruments IncorporatedColor television receiversUS4429418Jul 11, 1980Jan 31, 1984Microdyne CorporationFrequency agile satellite receiverUS4460872Dec 3, 1981Jul 17, 1984Inventab Audio KbLow noise differential amplifierUS4499435Sep 30, 1982Feb 12, 1985Harris CorporationSystem for linearizing sweep of voltage controlled oscillatorUS4580289Jun 21, 1984Apr 1, 1986Motorola, Inc.Fully integratable superheterodyne radio receiver utilizing tunable filtersUS4581593May 3, 1984Apr 8, 1986Sony CorporationVariable frequency oscillating circuitUS4723318Dec 16, 1985Feb 2, 1988U.S. Philips CorporationActive polyphase filtersUS4893316Jul 24, 1986Jan 9, 1990Motorola, Inc.Digital radio frequency receiverUS4914408Apr 24, 1989Apr 3, 1990U.S. Philips CorporationAsymmetric polyphase filterUS4916411May 19, 1989Apr 10, 1990Hewlett-Packard CompanyVariable frequency jitter generatorUS5014021Feb 8, 1990May 7, 1991Hughes Aircraft CompanyFrequency linearization circuit for a microwave VCO in ridged waveguideUS5108334Jun 1, 1989Apr 28, 1992Trimble Navigation, Ltd.Dual down conversion GPS receiver with single local oscillatorUS5146186May 13, 1991Sep 8, 1992Microsource, Inc.Programmable-step, high-resolution frequency synthesizer which substantially eliminates spurious frequencies without adversely affecting phase noiseUS5155452Nov 12, 1991Oct 13, 1992Silicon Systems, Inc.Linearized and delay compensated all CMOS VCOUS5177450Oct 4, 1991Jan 5, 1993Samsung Electronics Co., Ltd.Cmos power amplifierUS5179725Mar 29, 1991Jan 12, 1993International Business MachinesVoltage controlled oscillator with correction of tuning curve non-linearitiesUS5212459Oct 13, 1992May 18, 1993Silicon Systems, Inc.Linearized and delay compensated all CMOS VCOUS5235335Jun 2, 1992Aug 10, 1993Texas Instruments IncorporatedCircuit and method for tuning capacitor arraysUS5243302Sep 8, 1992Sep 7, 1993International Business Machines CorporationVoltage controlled oscillator with correction of tuning curve non-linearitiesUS5281924Nov 1, 1990Jan 25, 1994Italtel Societa Italiana Telecomunicazione S.P.A.Fully differential CMOS power amplifierUS5374903Apr 22, 1988Dec 20, 1994Hughes Aircraft CompanyGeneration of wideband linear frequency modulation signalsUS5412351Oct 7, 1993May 2, 1995Nystrom; ChristianQuadrature local oscillator networkUS5434569Sep 1, 1993Jul 18, 1995Texas Instruments IncorporatedMethods for adjusting the coupling capacitor of a multi-stage weighted capacitor A/D converterUS5451910Aug 12, 1993Sep 19, 1995Northrop Grumman CorporationFrequency synthesizer with comb spectrum mixer and fractional comb frequency offsetUS5465414Jun 27, 1994Nov 7, 1995Hewlett-Packard CompanyAutomatic determination of the presence of a microwave signal and whether the signal is CW or pulsedUS5511236 *Aug 17, 1994Apr 23, 1996National Semiconductor CorporationHalf duplex RF transceiverUS5537459Jun 17, 1994Jul 16, 1996Price; Evelyn C.Multilevel cellular communication system for hospitalsUS5559473Jun 23, 1994Sep 24, 1996At&T Global Information Solutions CompanyMulti-range voltage controlled oscillatorUS5559475Mar 14, 1995Sep 24, 1996Mitsubishi Denki Kabushiki KaishaFrequency synthesizer for synthesizing signals of a variety of frequencies by cross modulationUS5600283Sep 13, 1995Feb 4, 1997National Semiconductor CorporationDC isolated differential oscillator having floating capacitorUS5610559 *Mar 13, 1996Mar 11, 1997Ericsson Inc.Dual loop frequency synthesizer having fractional dividersUS5614864Sep 29, 1995Mar 25, 1997Rockwell Science Center, Inc.Single-ended to differential converter with relaxed common-mode input requirementsUS5631606Aug 1, 1995May 20, 1997Information Storage Devices, Inc.Fully differential output CMOS power amplifierUS5636213Dec 28, 1994Jun 3, 1997MotorolaMethod, transceiver, and system for providing wireless communication compatible with 10BASE-T EthernetUS5654708Apr 13, 1994Aug 5, 1997Robert Bosch GmbhProcess for compensating component tolerances in analog-digital convertersUS5703525Oct 9, 1996Dec 30, 1997Texas Instruments IncorporatedLow cost system for FSK demodulationUS5715529May 18, 1993Feb 3, 1998U.S. Philips CorporationFM receiver including a phase-quadrature polyphase if filterUS5724001Dec 2, 1996Mar 3, 1998Motorola, Inc.Method and apparatus for demodulating a frequency shift keyed signalUS5787123Oct 25, 1996Jul 28, 1998Sony CorporationReceiver for orthogonal frequency division multiplexed signalsUS5793359Aug 5, 1996Aug 11, 1998Mitsumi Electric Co., Ltd.System for RF communication between a computer and a remote wireless data input deviceUS5805017Nov 13, 1996Sep 8, 1998U.S. Philips CorporationBaseband demodulation of M-ary frequency shift keyed signals and a receiver thereforUS5808509May 7, 1997Sep 15, 1998U.S. Philips CorporationReceiver and demodulator for phase or frequency modulated signalsUS5818830Dec 29, 1995Oct 6, 1998Lsi Logic CorporationMethod and apparatus for increasing the effective bandwidth of a digital wireless networkUS5872810Jan 26, 1996Feb 16, 1999Imec Co.Programmable modem apparatus for transmitting and receiving digital data, design method and use method for said modemUS5878089Feb 21, 1997Mar 2, 1999Usa Digital Radio Partners, L.P.Coherent signal detector for AM-compatible digital audio broadcast waveform recoveryUS5892409Jul 28, 1997Apr 6, 1999International Business Machines CorporationCMOS process compensation circuitUS5905398Apr 8, 1997May 18, 1999Burr-Brown CorporationCapacitor array having user-adjustable, manufacturer-trimmable capacitance and methodUS5909463Nov 4, 1996Jun 1, 1999Motorola, Inc.Single-chip software configurable transceiver for asymmetric communication systemUS5940456Jun 20, 1996Aug 17, 1999Ut Starcom, Inc.Synchronous plesiochronous digital hierarchy transmission systemsUS5953640Apr 30, 1997Sep 14, 1999Motorola, Inc.Configuration single chip receiver integrated circuit architectureUS6072994Aug 31, 1995Jun 6, 2000Northrop Grumman CorporationDigitally programmable multifunction radio system architectureUS6134453Sep 9, 1998Oct 17, 2000Charles M. Leedom, Jr.Adaptive omni-modal radio apparatus and methodsUS6185418Nov 7, 1997Feb 6, 2001Lucent Technologies Inc.Adaptive digital radio communication systemUS6188716 *Mar 2, 1998Feb 13, 2001Pan Atlantic CorporationRadio and communication method using a transmitted intermediate frequencyUS6343207Nov 3, 1998Jan 29, 2002Harris CorporationField programmable radio frequency communications equipment including a configurable if circuit, and method thereforUS6366622May 4, 1999Apr 2, 2002Silicon Wave, Inc.Apparatus and method for wireless communicationsUS6377608Sep 30, 1998Apr 23, 2002Intersil Americas Inc.Pulsed beacon-based interference reduction mechanism for wireless communication networksUS6396355 *Apr 12, 2000May 28, 2002Rockwell Collins, Inc.Signal generator having fine resolution and low phase noiseUS6404293Oct 18, 2000Jun 11, 2002Broadcom CorporationAdaptive radio transceiver with a local oscillatorUS6417737Oct 18, 2000Jul 9, 2002Broadcom CorporationAdaptive radio transceiver with low noise amplificationUS6526034Sep 21, 1999Feb 25, 2003Tantivy Communications, Inc.Dual mode subscriber unit for short range, high rate and long range, lower rate data communicationsUS6714776Sep 28, 1999Mar 30, 2004Microtune (Texas), L.P.System and method for an image rejecting single conversion tuner with phase error correctionUS6738601Oct 18, 2000May 18, 2004Broadcom CorporationAdaptive radio transceiver with floating MOSFET capacitorsUS6973328 *Jun 7, 2000Dec 6, 2005Sharp Kabushiki KaishaMillimeter wave band transmitter, millimeter wave band receiver and millimeter wave band communication apparatus carrying out radio communication in millimeter wave band regionUS7110444 *Aug 4, 2000Sep 19, 2006Parkervision, Inc.Wireless local area network (WLAN) using universal frequency translation technology including multi-phase embodiments and circuit implementationsUS20020191721 *Jul 29, 2002Dec 19, 2002Noriyuki TokuhiroData transmission systemEP0803997A2Apr 22, 1997Oct 29, 1997Nokia Mobile Phones Ltd.A method and arrangement for producing a clock frequency in a radio deviceGB2296141A Title not available* Cited by examinerNon-Patent CitationsReference1Ahmadreza Rofougaran, "A Single-Chip Spread-Spectrum Wireless Transceiver in CMOS," Final Report, Integrated Circuits & Systems Laboratory Electrical Engineering Department, University of California, Los Angeles, California, 339 pages (1999).Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7949309 *May 28, 2010May 24, 2011Broadcom CorporationAntenna system for use within a wireless communication deviceUS8050634 *Apr 18, 2008Nov 1, 2011Telefonaktiebolaget L M Ericsson (Publ)Transceiver with isolated receiverUS8604871Sep 2, 2011Dec 10, 2013Dialog Semiconductor Gmbh.High gain amplifier method using low-valued resistancesUS9252908Apr 12, 2012Feb 2, 2016Tarana Wireless, Inc.Non-line of sight wireless communication system and methodUS9325409Apr 12, 2012Apr 26, 2016Tarana Wireless, Inc.Non-line of sight wireless communication system and methodUS9456354Apr 12, 2012Sep 27, 2016Tarana Wireless, Inc.Non-line of sight wireless communication system and methodUS20090264084 *Apr 18, 2008Oct 22, 2009Telefonaktiebolaget Lm Ericsson (Publ)Transceiver with Isolated ReceiverUS20100232474 *May 28, 2010Sep 16, 2010Broadcom CorporationAntenna system for use within a wireless communication deviceEP2562929A1Aug 26, 2011Feb 27, 2013Dialog Semiconductor GmbHHigh gain amplifier method using low-valued reistancesWO2014151933A2 *Mar 13, 2014Sep 25, 2014Tarana Wireless, Inc.Precision array processing using semi-coherent transceiversWO2014151933A3 *Mar 13, 2014Nov 27, 2014Tarana Wireless, Inc.Precision array processing using semi-coherent transceivers* Cited by examinerClassifications U.S. Classification455/73, 455/208, 455/76, 455/209, 455/183.1International ClassificationH03H21/00, H03H11/12, H04B1/38Cooperative ClassificationH03H21/0012, H03H21/0001, H03H11/1291, H04B1/40, H03J2200/10, H04B17/14, H04B17/19, H03B21/01, H04B17/104, H04B1/30, H03H2011/0494European ClassificationH04B1/40, H03H21/00B, H03H11/12F, H03B21/01, H03H21/00A, H04B17/00A3S, H04B17/00A1T, H04B17/00A2S, H04B1/30Legal EventsDateCodeEventDescriptionNov 18, 2013FPAYFee paymentYear of fee payment: 4Feb 11, 2016ASAssignmentOwner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTHFree format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001Effective date: 20160201RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services