Source: http://www.google.fr/patents/US3959771?hl=fr
Timestamp: 2013-05-18 19:32:57
Document Index: 89995268

Matched Legal Cases: ['art 101', 'arts 100', 'art 104', 'arts 103', 'art 107', 'arts 106', 'art 110', 'arts 109', 'art 113', 'arts 112', 'art 116', 'arts 115', 'arts 13', 'arts 13', 'arts 46']

Brevet US3959771 - Pattern recognition apparatus - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Historique Web | Connexion Recherche avanc�e dans les brevets BrevetsA pattern recognition apparatus for discriminating a body having a specified shape from a number of bodies, in which an image area, at which the image signal has a value within a specified range, within a specified region of the image of a body is measured and whether or not the image area is within...http://www.google.fr/patents/US3959771?utm_source=gb-gplus-shareBrevet US3959771 - Pattern recognition apparatus Num�ro de publicationUS3959771 AType de publicationOctroi Num�ro de demande05/405,257 Date de publication25 mai 1976 Date de d�p�t11 oct. 1973 Date de priorit�13 oct. 1972 InventeursMasakazu EjiriSadahiro IkedaJun MotoikeTakeshi Uno Cessionnaire d'origineHitachi, Ltd. Classification aux �tats-Unis382/291382/218 Classification internationaleG01B11/00H04N7/18B65G43/08G06K9/64G06T7/60G06T1/00G06K9/78 Classification coop�rativeG06K9/6202G06K9/78 Classification europ�enneG06K9/62A1G06K9/78R�f�rencesCitations de brevets (9) R�f�renc� par (18)Liens externesUSPTO Cession USPTO EspacenetPattern recognition apparatusUS 3959771 A R�sum� A pattern recognition apparatus for discriminating a body having a specified shape from a number of bodies, in which an image area, at which the image signal has a value within a specified range, within a specified region of the image of a body is measured and whether or not the image area is within the range predetermined by the body to be recognized is decided.
What we claim is: 1. In a pattern recognition apparatus for determining at least one of the shape and position of an object to be recognized comprising means for scanning objects to obtain video signals representing the shape of the objects, means for quantizing and sampling said video signals to provide output signals in accordance therewith, and means for processing the output signals to detect at least one of whether an object has a specified shape, and the position of the object, the improvement wherein said processing means comprises: means connected to said quantizing and sampling means for generating four specified regions arranged in one direction, means connected to said generating means for measuring an area, where the output signal has a preassigned value, within each of said four specified regions, means for performing one arithmetic operation (a-b+c-d) between said measured areas of said four specified regions, where a, b, c, and d are said measured areas of said four individual specified regions, and means for determining the position of the object from the sign change of the result of the one arithmetic operation.
2. A pattern recognition apparatus according to claim 1, further comprising means for performing another arithmetic operation (a+b+c+d) between said measured areas of said four specified regions, and means for determining whether the result of the another arithmetic operation is less than a predetermined threshold value corresponding to the shape of the object to be recognized.
3. A pattern recognition apparatus according to claim 2, in which said one and another arithmetic operations are simultaneously performed by an up-down counter.
It is assumed that when the arrangement of FIG. 10 scans the central white part of the pattern of FIG. 11a, the output of the analog-to-digital converter 26 is numerical values (that is, the level of brightness) of from 10 to 15, for example, while when it scans the peripheral black part, the output of the converter 26 is numerical values of from 0 to 4. The output of the converter 26 is supplied to the two comparators 8", one of which is denoted by 8".sub.A and the other of which is denoted by 8".sub.B. The comparator 8".sub.A is made to produce an output of a binary 1 when it is supplied with an input of a numerical value of from 9 to 15, while the comparator 8".sub.B is made to produce an output of a binary 1 when it is supplied with an input of a numerical value of from 0 to 6. The output of the comparator 8".sub.A is connected to the gate circuit 14".sub.A which is open at the region A in FIG. 12a, while the output of the comparator 8".sub.B is connected to the gate circuit 14".sub.B which is open at the region B in FIG. 12a.
If the setting condition is made contrary to the above one, that is, if the comparator 8".sub.A is made to produce an output of a binary when it is supplied with an input of a numerical value of from 0 to 6, while the comparator 8".sub.A is made to produce an output of a binary 1 when it is supplied with an input of a numerical value of from 9 to 15, the count of the counter 19" is 0 when the object is the pattern of FIG. 11a and is a larger value when the object is a pattern other than that of FIG. 11a. Consequently, if the comparator 10" is constructed such that it produces an output of a binary 1 when it is supplied with the count approximating 0, its output also represents the result of the recognition of the pattern of FIG. 11a.
First, an example of a specified region of one kind is shown in FIG. 14a. This is on the supposition that the object pattern is limited to the three kinds of patterns of FIGS. 11a to 11c. The amount of space belonging to both region A and black of each object pattern is 100 % of the amount of space of the region A of FIG. 11a, 0 % of that of FIG. 11b, and 25% of that of FIG. 11c. Consequently, the three kinds of patterns can be discriminated by the circuit as shown in FIG. 14b. That is, if it has been made such that when the space gate signal generator 13" is constructed to generate the space gate signal of FIG. 14a and when the values of the amount of space measured by the counter 19" are about 100 %, 0 %, and 25 %, respectively, of the amount of space of the region A, the output of each of digital comparators 10".sub.a, 10".sub.b and 10".sub.c is a binary 1, they can be treated as the recognized output of the patterns of FIGS. 11a to 11c, respectively.
This method will next be described in some detail. It is assumed that in FIGS. 16a to 16c the part 101 is the space region A.sub.1, the parts 100 and 102 are the regions B.sub.1, the part 104 is the region A.sub.2, the parts 103 and 105 are the regions B.sub.2, the part 107 is the region A.sub.3, the parts 106 and 108 are the regions B.sub.3, the part 110 is the region A.sub.4, the parts 109 and 111 are the regions B.sub.4, the part 113 is the region A.sub.5, the parts 112 and 114 are the regions B.sub.5, the part 116 is the region A.sub.6, and the parts 115 and 117 are the regions B.sub.6. Also it is assumed that when the space gate signal generator is employed (FIGS. 4, 10, and 14b) the space gate signal generated by it is designated by the same notation as the above region. The dotted lines in FIGS. 16a to 16c indicate the profiles of the patterns of FIGS. 11a to 11c, respectively.
FIG. 15 is an embodiment of the arrangement according to the present invention for discriminating the patterns of FIGS. 11a to 11c by the setting of FIGS. 16a to 16c. Reference numeral 26' designates a quantizing circuit for putting the output of the sampling circuit 25, i.e. the pattern values of various parts of the object pattern 15 into either of the states 1 and 0. The signal from the hatched parts in FIGS. 11a to 11c is put into a binary 0, and the signal from the remaining parts is put into a binary 1. Reference numeral 13".sub.1 designates a space gate signal generator for generating space gate signals A.sub.1 and B.sub.1, reference numeral 14".sub.A1 designates an AND gate circuit to produce an output of a binary 1 when the signal A.sub.1 of the space gate signal generator 13".sub.1 is a binary 1 and the output of the quantizing circuit 26' is a binary 0, reference numeral 14".sub.B1 designates an AND gate circuit which produces a binary 1 when the signal B.sub.1 of the space gate signal generator 13".sub.1 is a binary 1 and the output of the quantizing circuit 26" is a binary 1, and reference numerals 14".sub.A2 and 14".sub.B2 designate AND gate circuits performing the same operation as the AND circuits 14".sub.A1 and 14".sub.B1, respectively, except that the space gate signals are A.sub.2 and B.sub.2 signals. Reference numerals 18".sub.1 and 18".sub.2 designate OR gates.
Consequently, when the entire pattern space is scanned by the input voltage 24, a number of pulses (because spatially separated by the sampling circuit 25) proportional to the sum of the area of the part which is within the space region 100 or 102 and at which the state of the object pattern is 1 and the area which is within the space region 101 and at at which state of the object pattern is 0 are outputted by the OR gate circuit 18".sub.1. Also, a number of pulses proportional to the sum of the area of the part which is within the sapce region 103 or 105 and at which the state of the object pattern is 1 and the area of the part which is within the sapce region 104 and at which the state of the object pattern is 0 are outputted by the OR gate circuit 18".sub.2.
Reference numerals 19".sub.1 and 19".sub.2 designate counters for counting the numbers of pulses outputted by the OR gate circuits 18".sub.1 and 18".sub.2, respectively. Reference numerals 10".sub.1 and 10".sub.2 designate comparators which produce 1 when the contents of the counters 19".sub.1 and 19".sub.2 are lower than certain set values, otherwise produce 0, respectively. The comparators 10".sub.1 and 10".sub.2 are reset at the start of the scanning by the input device 24, and the counters 19".sub.1 and 19".sub.2 operate when the scanning by the input device 24 is performed over the entire pattern space.
Both of the space regions 101 and 104 in FIG. 16a are set to correspond to a part of the state 1 of the object pattern of FIG. 11a, and all of the space regions 100, 102, 103, and 105 are set to correspond to a part of the state 0 of the object pattern of FIG. 11a. Consequently, when the pattern of FIG. 11a is selected as the object pattern 15, the final counts of the counters 19".sub.1 and 19".sub.2 are both to be zero in principle, so that it is sufficient to select values approximating zero as the set values of the comparators 10".sub.1 and 10".sub.2. Actually, the count may not always be zero due to the deformation of the pattern. Consequently, a somewhat larger value may be selected as the set value to allow this situation. Then, when the pattern of FIG. 11a is selected as the object pattern 15, the output of both comparators 10".sub.1 and 10".sub.2 is a binary 1, so that the output of the AND gate circuit 11a is a binary 1.
When the pattern of FIG. 11b or 11c is selected as the object pattern 15, the output of the AND gate circuit 11a is a binary 0 because the counts of the counters 19".sub.1 and 19".sub.2 after the completion of respective field scanning are never values around zero simultaneously. That is, when set as above, the output of the gate circuit 11a can be regarded as the recognized signal of the pattern of FIG. 11a.
In FIG. 15, if the circuit blocks including the gate circuits 11b and 11c, respectively, are constructed similarly to the circuit block including the gate circuit 11a, the outputs of the gate circuits 11b and 11c are the recognized outputs of the patterns of FIGS. 11b and 11c, respectively. However, since the boundary between the regions 112 and 113 in FIG. 16c, for example, is not in complete agreement with the boundary line of the pattern of FIG. 11c, the final contents of the counters 19".sub.5 and 19".sub.6 are not zero but certain values even when the pattern of FIG. 11a is the object pattern. Since these values can be known beforehand from the pattern of FIG. 11c and the shape and size of the space regions of FIG. 16c, it is sufficient to make the comparators 10".sub.5 and 10".sub.6 such that they produce a binary 1 when the contents of the counters 19".sub.5 and 19".sub.6 approach these values, respectively.
The space regions 100, 101 and 102 in FIG. 16a happen to be the same as the space regions 106, 107 and 108 in FIG. 16b. In such a case, the circuit parts 13".sub.3, 14".sub.A3, 14".sub.B3, 18".sub.3 and 19".sub.3 may be omitted and the output of the counter 19".sub.1 may be supplied to the comparator 10".sub.3. Further, if the comparison condition of the comparator 10".sub.1 is in agreement with that of the comparator 10".sub.3, the comparator 10".sub.3 can of course be omitted so that the gate circuit 11b is supplied with the signal from the comparator 10".sub.1 instead of from the comparator 10".sub.3.
The circuit block including the gate circuit 11a in FIG. 15 which is again shown in FIG. 17a may be modified as shown in FIG. 17b. Strictly speaking, the operations of the circuits of FIGS. 17a and 17b are different from each other, but in some cases they attain the same purpose. In the arrangement of FIG. 17b, an OR gate 18".sub.12 supplies a number of pulses (described above) proportional to the sum of the area of the parts at which the state of the object pattern in the space regions 100, 102, 103 and 105 is 1 and the area of the parts at which the state of the object pattern in the space regions 101 and 104 is 1 to the counter 19".sub.12. The content of the counter 19".sub.12 at the time of the completion of the field scanning is decided by the comparator 10".sub.12. The setting value of the comparator 10".sub.12 should be determined taking the possibility of the deformation of the object pattern into consideration. If the deformation is considered to occur uniformly throughout the pattern, it is good to select the setting value of the comparator 10".sub.18 somewhat larger than the setting values of the comparators 10".sub.1 and 10".sub.2 and taking the characteristics, property, etc. of the object pattern into consideration. Then, the arrangement of FIG. 17b has the advantage that the number of the circuit parts is smaller than that of the arrangement of FIG. 17a.
As regards the number of the circuit parts, the space gate signal generators 13".sub.1, 13".sub.2, ...., 13".sub.6 are not always necessary to be provided independently to individual circuit branches in FIG. 15, but in many cases the arrangement is simplified by replacing these space gate signal generators with a common space gate signal generator. Also, in the arrangement of FIG. 15 the recognition circuit blocks are provided individually for the three patterns, but it may be sufficient to provide only one circuit block which is to be used time sequentially by switching over the space gate signal and the setting value of the comparator, though the comparator, though the processing time is generally prolonged.
In FIG. 18 reference numerals 34, 35, and 36 designate articles, reference numeral 37 designates a belt conveyor carrying the articles, reference numeral 38 designates a relatively bright plate which is luminant or illuminated, and reference numeral 24 designates a television image input device. When the articles 34, 35 and 36 are present in front of the image input device 24, images as shown in FIGS. 19a, 19b and 19c are inputted, respectively. Reference numeral 25 designates a sampling circuit (already described with reference to FIG. 10), and reference numeral 39 designates a quantizing circuit which is assumed to encode the white state of the image as shown in FIGS. 19a to 19c into a binary 1 and the black state into a binary 0. Reference numeral 13" designates a space gate signal generator for generating the space gate signal of FIG. 12a and is assumed to output from its A output a signal which is a binary 1 at the part A in FIG. 12a and from its B output a signal which is a binary 1 at the part B in FIG. 12a. Reference numerals 14".sub.A and 14".sub.B designate AND circuits (small circle at the input indicates negation), and reference numeral 18" designates an OR circuit. Since the AND gate 14".sub.A outputs a signal which is a binary 1 when it is the part A in FIG. 12a and the image is white, and the AND gate 14".sub.B outputs a signal which is a binary 1 when it is the part B in FIG. 12a and the image is black, the output of the OR gate 18" is never a binary 1 when the image of FIG. 19a is inputted. Consequently, even at the stage the scanning of the entire image is completed, the count of the counter 19" is zero in principle. In contrast, when an image other than that of FIG. 19a is inputted, the numerical value corresponding to the area of the part different from the image of FIG. 19a (strictly speaking, the part in FIG. 12a which is not A nor B is subtracted from this part) is counted by the counter 19".
The arrangement of FIG. 18 is provided with three sets of the circuit parts 13", 14".sub.A, 14".sub.B, 18", 19" and 10". These three sets of circuit branches are set suitably for the images of FIGS. 19a to 19c and output the recognized outputs of the articles 34, 35 and 36, respectively.
With respect to the regions A and D, the areas of the parts thereof at which the value of the image signal corresponds to black are measured, and with respect to the regions B and C, the areas of the parts thereof at which the value of the image signal corresponds to white are measured, and the measured areas are denoted by a, d, b and c, respectively. If an arithmetic operation such as S = a - b + c - d, for example, is performed on these areas, it follows that S = 0 when the image of the body 60 is at the regions B and C. If the image of the body 60 is a little on the right-hand side relative to this position, it becomes S &lt; 0, while it is a little on the left-hand side, it results in S &gt; 0. A strict representation of this fact is shown in FIGS. 23a to 23c, in which FIG. 23a shows the specified regions A, B, C and D and FIG. 23b shows the image of the body 60. FIG. 23c shows the value of S which varies depending on the position of the center (denoted by a dot as an example) of the image of the body 60 in the horizontal direction. If it is assumed that the image of the body 60 travels from right to left, the time at which S changes from negative to zero is the time at which the image of the body 60 passes the boundary between the regions B and C.
A practical circuit of the image information processing section 45 will be described referring to FIG. 24. Reference numeral 46 designates a circuit for quantizing circuit an image signal (luminance or brightness signal) which encodes a white image signal into the state 1 and a black image signal into the state 0. Reference numeral 47 designates a sampling circuit which produces an image discrete in the horizontal direction as well as in the vertical direction (an ITV camera produces an image discrete in the vertical direction due to it scanning system). The timing of the sampling is produced by a synchronizing signal generator 48. Reference numerals 49.sub.A, 49.sub.B, 49.sub.C and 49.sub.D designate gate circuits which open at the region A, B, C and D. The gate signals therefor are supplied by a space gate signal generator 50 from its terminals A, B, C and D. These gate signals can be easily produced by utilizing the timing signal for the horizontal sampling (which is equivalent to the horizontal synchronizing signal of an ITV camera). These apparatuses are as described with reference to the above embodiments.
Reference numerals 51.sub.A to 51.sub.D designate counters (generally, integrating elements) for obtaining the areas a, b, c and d, respectively. Since the negation of a quantized image signal passes through the gate circuit 49.sub.A, for example, the counter 51.sub.A counts the value proportional to the area at the time when the output of the quantizing circuit 46 is 0, i.e. the image is black (and at the area A). Similarly, the counters 51.sub.B, 51.sub.C and 51.sub.D count the values proportional to the areas at the time of the image being white, white, and black, respectively. These counters are reset at the start of the scanning by the ITV camera (equivalent to the vertical synchronizing signal).
Reference numerals 52, 52' and 52" designate adders and subtracter which are operated in this state by the timing signal from the synchronizing signal generator 48. The adder 52 performs the addition of the counts of the counters 51.sub.A and 51.sub.B, while the adder 52' performs the addition of the counts of the counters 51.sub.B and 51.sub.D. The subtracter 52" subtracts the output of the adder 52' from the output of the adder 52 to produce an output of S = a - b + c - d.
The arrangement of FIG. 25 is a simplification of the arrangement of FIG. 24 by replacing the counters 51.sub.A to 51.sub.B with an up-down counter 55. The sign "+" in the up-down counter 55 indicates the input terminal for adding the input pulse and the sign "-" indicates the input terminal for subtracting the input pulse. The operations of the circuits parts 46, 47 48, 49.sub.A to 49.sub.D, 50, 53 and 54 are all the same as those in FIG. 24. Reference numerals 56 and 56' designate OR gates. The OR gate 56 makes the outputs of the AND gates 49.sub.A and 49.sub.C pass therethrough to supply them to the + terminal of the up-down counter 55, while the OR gate 56' makes the outputs of the AND gates 49.sub.B and 49.sub.D pass therethrough to supply them to the - terminal of the counter 55. Since the regions A, B, C and D are independent of each other, the content of the counter 55 is a a - b + c - d, i.e. S at least at the end of the image scanning of the ITV camera.
This matter will be described in some detail. Though it may be considered that the size of that part can be known by the sum S of the areas b and c, it is apparent that this leads to an erroneous decision due to the existence of the above-mentioned noise in the image. For example, for the image of FIG. 26a the size of the part corresponding to the body can be known by S. However, for the image of FIG. 26b, S does not represent the size of the part of the body. In such a case, the widths of the two regions B and C are made equal to the width of the body part and the widths of the regions A and D are individually made narrower. Then, whether or not the image of a (seeming) body in the visual field is in agreement with the set region can be decided by S = a + b + c + d, for example, and whether or not that image is passing the center (exactly, the middle between the boundary between the regions A and B and the boundary between the regions C and D) of the set region can be decided by S = a - b + c - d. Here, in case the agreement is decided by S, there results S = 0 when the sum of the widths of the regions B and C is in complete agreement with the width of the image of the body, but it is good to make S&lt;ε (ε is the tolerance) the decision condition by taking image noise and an allowable degree of variation in the width of the image of the body into consideration.
Further, if it is established that whether S&lt;ε is satisfied or not is decided when S varies from negative to positive or zero, the decision of the width of (a part of) the image of the body and the decision of the position (or time) at which that part is passing can be made simultaneously.
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