Source: http://www.google.com/patents/US5535138?dq=5,966,702
Timestamp: 2017-04-27 06:01:02
Document Index: 613228776

Matched Legal Cases: ['application No. 08', 'art1', 'art2', 'art3', 'art4', 'art4', 'art3', 'art2', 'art1']

Patent US5535138 - Encoding and decoding video signals using dynamically generated quantization ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsVideo signals are encoded using quantization matrices generated based on one or more quantization matrix parameters that are contained in the encoded bit stream. Encoded video signals are decoded using quantization matrices generated using the one or more quantization matrix parameters that are contained...http://www.google.com/patents/US5535138?utm_source=gb-gplus-sharePatent US5535138 - Encoding and decoding video signals using dynamically generated quantization matricesAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS5535138 APublication typeGrantApplication numberUS 08/303,313Publication dateJul 9, 1996Filing dateSep 8, 1994Priority dateNov 24, 1993Fee statusPaidAlso published asUS5493513Publication number08303313, 303313, US 5535138 A, US 5535138A, US-A-5535138, US5535138 A, US5535138AInventorsMichael KeithOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (3), Non-Patent Citations (4), Referenced by (40), Classifications (98), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetEncoding and decoding video signals using dynamically generated quantization matrices
The encoder (i.e., preferably pixel processor 302 of FIG. 3) preferably encodes partial blocks by padding them out to the full (8×8) size (using a selected method such as replicating the last column or row). The resulting padded blocks are encoded as if they were originally full blocks. The decoder (i. e., preferably host processor 202 of FIG. 2) reconstructs an original partial block by decoding the full (8×8) padded block and then saving only the appropriate partial block to the final image bitmap in memory. The decoder determines the location and size of partial blocks from the image dimensions which are encoded in the compressed video signal, as described in further detail later in this specification in conjunction with FIG. 15.
As described above in reference to step 402 of FIG. 4, the encoder performs motion estimation to identify, for each (16×16) target macroblock of the current image, a (16×16) macroblock from the reference image that matches (relatively closely) the target macroblock. In general, the encoder implements motion estimation as a three-step log search to identify a motion vector within a specified pixel range of the current macroblock. According to a preferred embodiment, the pixel range is specified as +/-7 pixels in the horizontal and vertical directions.
where array[][] contains the results of the IDST calculation, MCprev[][] is the corresponding motion-compensated (8×8) block of component signals from the previous image, and the function clamp(n,min,max) limits a value n to the range (min,max).
In an alternative preferred embodiment, the block addition for decoding inter blocks may be implemented simultaneously for two different (8×8) blocks of the current image using pseudo-SIMD processing. Pseudo-SIMD processing is described in further detail in U.S. patent application No. 08/182,758, filed Jan. 14, 1994, assigned to the same assignee as the current application, and the disclosure of which is incorporated in its entirety herein by reference.
The forward discrete slam transform (FDST) transforms pixel components in the spatial domain to DST components in the spatial frequency domain. The inverse DST (IDST) transforms DST components back into pixel components. The discrete slam transform applies an (8×1) DST to each of the eight rows and eight columns of an (8×8) block. As described earlier in this specification in conjunction with FIG. 4, pixel processor 302 of FIG. 3 applies the FDST when generating encoded video signals (step 412 of FIG. 4). Pixel processor 302 also applies the IDST when generating the reference frame signals from the encoded video signals (step 426). Similarly, as described earlier in this specification in conjunction with FIG. 21, host processor 202 of FIG. 2 applies the IDST when decoding the encoded video signals (step 2112 of FIG. 21).
______________________________________slant8×1(s,d,fwd)      // s = pointer to input column or row      // d = pointer to output column or rowint s[],d[],fwd;      // fwd = 1 for forward DST, 0 for      inverse DSTint r1,r2,r3,r4,r5,r6,r7,r8;int t,t1,*p;if (fwd)   // apply forward DST{p = s;r1 = *p++; // store value pointed to by p to r1 and      // then increment pr2 = *p++;r3 = *p++;r4 = *p++;r5 = *p++;r6 = *p++;r7 = *p++;r8 = *p++;SlantPart1;SlantPart2;SlantPart3;SlantPart4;p = d;*p++ = r1;*p++ = r4;*p++ = r8;*p++ = r5;*p++ = r2;*p++ = r6;*p++ = r3;*p++ = r7;}else       // apply inverse DST{p = s;r1 = *p++;r4 = *p++;r8 = *p++;r5 = *p++;r2 = *p++;r6 = *p++;r3 = *p++;r7 = *p++;SlantPart4;SlantPart3;SlantPart2;SlantPart1;p = d;*p++ = r1;*p++ = r2;*p++ = r3;*p++ = r4;*p++ = r5;*p++ = r6;*p++ = r7;*P++ = r8;}}______________________________________
TABLE IX______________________________________Initial Assignment of Column DST Operations and FinalAssignment of Row DST Operations.4-bitComplexity      Mask    DSTMask            Values  Operation______________________________________(1xxx)           8-15   slant8×1(01xx)          4-7     slant4×1(001x)          2-3     slant2×1(0001)          1       slant1×1(0000)          0       null______________________________________
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375/E07.224, 375/E07.148, 375/E07.194, 375/E07.145, 375/E07.176, 375/E07.14, 375/E07.241, 375/E07.144, 375/E07.217, 375/E07.138, 375/E07.254, 375/E07.157, 375/E07.226, 375/E07.18, 709/247, 375/E07.19, 375/E07.231, 348/E07.083, 375/E07.193International ClassificationH04N19/895, H04N7/52, H04N7/50, G06T9/00, H04N7/26, H04N7/15, H04Q11/04, H04N7/30, H04N7/46Cooperative ClassificationH04N19/86, H04N19/587, H04N19/174, H04N19/132, H04N19/91, H04N19/61, H04N19/146, H04N19/82, H04N19/107, H04N19/198, H04N19/80, H04N19/895, H04N19/527, H04N19/14, H04N19/126, H04N19/197, H04N19/176, H04N19/196, H04N19/13, H04N19/149, H04N19/124, H04N19/60, H04Q2213/13106, H04Q2213/1324, H04Q2213/1319, H04Q2213/13103, H04N7/152, H04Q2213/13299, H04Q2213/13152, H04Q2213/13034, H04Q2213/13337, H04Q2213/13209, H04N7/52, H04Q11/0435, H04N7/15European ClassificationH04N19/00A4P2, H04N21/2368, H04N19/00A4P1, H04N21/434A, H04N7/15M, H04N7/30E2, H04N7/26A4V, H04N7/50E5F, H04N7/15, H04N7/50R, H04N7/26A4P, H04N7/68, H04Q11/04S1, H04N7/26F, H04N7/52, H04N7/26A4C2, H04N7/46T2, H04N7/50E4, H04N7/50, H04N7/26P4, H04N7/26A4Q2, H04N7/30, H04N7/26F2, H04N7/26A6E4E, H04N7/26A4Z, H04N7/26A8L, H04N7/26A6C2, H04N7/26A8B, H04N7/26M2GLegal EventsDateCodeEventDescriptionSep 8, 1994ASAssignmentOwner name: INTEL CORPORATION, OREGONFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KEITH, MICHAEL;REEL/FRAME:007144/0560Effective date: 19940831Jan 7, 2000FPAYFee paymentYear of fee payment: 4Jan 9, 2004FPAYFee paymentYear of fee payment: 8Jan 4, 2008FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services