Source: https://patents.google.com/patent/KR100812036B1/en
Timestamp: 2020-07-03 11:28:49
Document Index: 591585541

Matched Legal Cases: ['art 10', 'art 1', 'art 1', 'art 10', 'art) 11', 'art 10', 'art 1', 'art 10', 'art 10']

KR100812036B1 - Resolver signal processing device - Google Patents
KR100812036B1
KR100812036B1 KR1020070005999A KR20070005999A KR100812036B1 KR 100812036 B1 KR100812036 B1 KR 100812036B1 KR 1020070005999 A KR1020070005999 A KR 1020070005999A KR 20070005999 A KR20070005999 A KR 20070005999A KR 100812036 B1 KR100812036 B1 KR 100812036B1
KR1020070005999A
KR20070093802A (en
히로시 가와구치
2006-03-15 Priority to JPJP-P-2006-00071597 priority
2007-01-19 Application filed by 오므론 가부시키가이샤 filed Critical 오므론 가부시키가이샤
2007-09-19 Publication of KR20070093802A publication Critical patent/KR20070093802A/en
2008-03-10 Publication of KR100812036B1 publication Critical patent/KR100812036B1/en
238000005070 sampling Methods 0.000 description 44
SUMMARY OF THE INVENTION The present invention provides a resolver signal processing apparatus which can contribute to high speed and low cost, with a low burden on the controller when applying an excitation signal to a resolver. The processing apparatus includes a control unit 1, a resolver 2, and an input / output unit 3. The control unit 1 includes a memory for storing two cycles of sine wave data, and a sine wave with respect to the resolver 2. A DMA controller for transmitting an excitation signal is provided. The calculating part 10 provided in the control part 1 gives the command which carries out DMA transfer of sine wave data for one cycle from a reference phase as an excitation signal at the time of initial setting, and corrects it as an excitation signal at the time of rotation angle detection. A command for DMA transfer of sinusoidal data for one cycle from a phase is given. The correction phase is determined based on the phase shift of the excitation signal and the sinusoidal output signal or the cosine wave output signal and the rotation angle of the resolver at the initial setting.
Control unit, resolver, input / output unit
Resolver Signal Processing Unit {RESOLVER SIGNAL PROCESSING DEVICE}
BRIEF DESCRIPTION OF THE DRAWINGS The main part block diagram of EPS-ECU which is embodiment of this invention.
2 is a waveform diagram for explaining the operation of resolver signal processing;
3 conceptually illustrates sinusoidal data stored in a memory;
4 is a flowchart showing an operation during initial setting.
5 is a flowchart showing an operation at the angle detection.
1: control unit 2: resolver
3: input / output unit
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resolver signal processing apparatus for use in EPS-ECU (Electronic Control Unit for Electric Power Steering).
The resolver signal processing apparatus is provided in the EPS-ECU, which is a vehicle-mounted electronic device, and detects the rotation angle θ of the handle shaft based on a signal from a resolver connected to the handle shaft.
Since the resolver generates a phase shift inherent between the excitation signal and the resolver output signal (a sine wave output signal and the cosine wave output signal) applied to the resolver, the phase shift is detected in advance in the detection of the rotation angle θ. It is necessary to detect and to cancel this value when detecting the rotation angle.
The phase shift is detected at this time by setting a predetermined timing such as the power-on of the resolver signal processing device at the initial setting, and thereafter, the rotation angle? Is detected with reference to the phase shift every fixed time. In addition, the peak values of the sinusoidal wave output signal and the cosine wave output signal are usually detected in order to increase the detection accuracy of the rotation angle θ.
In the conventional resolver signal processing apparatus, when an excitation signal is applied to the resolver, the resolver signal processing device reads the data one by one through the read addresses of the sine wave ROM in which the sine wave is stored for one cycle, and transmits the data to the resolver. Document 1). In addition, in order to compensate for the phase shift, the read start address of the sine wave ROM is shifted based on the phase shift.
Patent Document 1: Japanese Patent No. 3368837
However, since the resolver signal processing apparatus reads data by advancing the read addresses of the sine wave ROM one by one at the time of rotation angle detection, the burden of the control unit is large, and other processing cannot be performed, or the processing capability This high device must be used, resulting in a problem of high overall cost.
The present invention provides a resolver signal processing apparatus that can contribute to high speed and low cost because the burden on the controller when applying the excitation signal to the resolver is light and the processing steps are simplified.
The resolver signal processing apparatus of the present invention detects an excitation signal transmitting means for transmitting an excitation signal composed of a sine wave to the resolver, and an extreme value of the sine wave output signal and the cosine wave output signal from the resolver, based on the value. To detect the rotation angle θ of the resolver.
When a sinusoidal excitation signal is transmitted to the resolver, a sinusoidal output signal and a cosine wave output signal are derived at the two output terminals of the resolver, respectively. By detecting the extremes of these signals, the resolver rotation angle θ can be obtained.
In the resolver signal processing apparatus of the present invention, a storage section for storing sinusoidal data for two cycles and a DMA transfer section for DMA transfer of sinusoidal data for one cycle from the designated phase designated by the storage section as excitation signals to the resolver are provided. Equipped. These storage units and the DMA transfer unit are included in the excitation signal transmitting unit. In the initial setting performed before the operation of the resolver, the specified phase becomes the reference phase. The computing unit issues a DMA transfer command of an excitation signal to the DMA transfer unit from a reference phase, and detects a phase shift between the excitation signal and the sinusoidal output signal or the cosine wave output signal.
With the above configuration, the excitation signal is output to the resolver by DMA transfer. For this reason, the time required for the processing is extremely short, and the burden on the calculation unit is also reduced.
In addition, at the time of detecting the rotation angle performed immediately after the initial setting of the resolver, the calculating unit sets a position where the phase precedes the reference phase by the amount of the phase shift as a correction phase, and the excitation signal is set from this correction phase. A DMA transfer command is issued to the DMA transfer section, and then the rotation angle θ is detected based on the extreme value.
Even in the detection of the rotation angle of sending the excitation signal, which compensates for the phase shift, to the resolver, by using the DMA transfer, the time required for the processing becomes extremely short, and the burden on the controller becomes light.
BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the principal part of EPS-ECU (electronic control unit for electric power steering) which is embodiment of this invention.
The EPS-ECU is used to realize a resolver signal processing function for controlling the resolver 2 connected to the steering wheel shaft of the vehicle, and other functions for electric power steering control. The apparatus is composed of a control unit (MPU) 1 for performing resolver signal processing and other processing, and an input / output unit 3 connected between the control unit 1 and the resolver 2.
The control part 1 is equipped with the calculating part 10 and the memory (memory part) 11 which stores the sine wave data for 2 cycles. The sine wave data stored in the memory 11 is duty ratio data having different values depending on the waveform level. The control unit 1 further outputs from the DMA controller 12 (DMA transfer unit) which performs control for DMA transfer of sinusoidal data stored in the memory 11 for only one cycle. A PWM signal generation circuit 13 for generating a PWM signal corresponding to sine wave data (duty ratio data) is provided. The control unit 1 further includes a first AD converter 14, a second AD converter 15, and a third AD converter 16 connected to the input terminal of the calculation unit 10.
The input / output unit 3 amplifies the sinusoidal signal with Asinωt and amplifies the CR filter 30 that converts the PWM signal output from the PWM signal generation circuit 13 into an analog sinωt sinusoidal signal by filtering. A first amplifying circuit 31 output to the resolver 2 as a signal, and a first input filter 32 for removing noise in the signal of Asinωt and feeding back to the first AD converter 14 of the controller 1; do. The input / output unit 3 further includes a second amplifying circuit 33 and a third amplifying circuit 34 for amplifying the sine wave output signal and the cosine wave output signal output from the resolver 2, and their amplifying circuit 33. And a second input filter 35 and a third input filter 36 for removing noise in the signal amplified by the second signal 34 and inputting the second AD converter 15, the third AD converter 16. Assuming that the resolver rotation angle is θ and no other phase delay is taken into account, the sinusoidal output signal output from the resolver 2 to the second amplifying circuit 33 is sin θ sinωt. The cosine wave output signal output from the resolver 2 to the third amplifying circuit 34 is cos θ sin ω t.
Next, considering the phase delay of the resolver 2, it becomes as follows.
As for the signal output to the calculating part 10 via the resolver 2, the phase delay (phi) generate | occur | produces as much as the one which passes through the resolver 2 compared with the signal which does not pass through the resolver 2. Therefore, the signal passing through the second input filter 35 through the resolver 2 becomes Bsinθsin (ωt + φ), and the signal passing through the third input filter 36 becomes Bcosθsin (ωt + φ). .
When performing the resolver signal processing, the control unit 1 executes two modes of initial setting and rotation angle detection. The initial setting is executed only once before the operation of the resolver 2, for example, when the ignition key of the vehicle is operated and the EPS-ECU starts to operate. Rotation angle detection is performed every fixed time (for example, every 250 microseconds) after initial setting. In the initial setting, the excitation signal Asinωt is output to the resolver 2, and the sinusoidal output signal Bsinθsin (ωt + φ) passed through the second input filter 35 from the resolver 2, or By receiving the cosine wave output signal Bcosθsin (ωt + φ) which has passed through the three input filter 36, the excitation signal Asinωt and the sinusoidal output signal Bsinθsin (ωt + φ), or the cosine wave Phase shift (phase delay of resolver 2) phi between signals of the output signal Bcos θsin (ωt + φ) is detected. In detecting the rotation angle, the rotation angle θ is detected based on the sinusoidal output signal Bsinθsin (ωt + φ) or the cosine wave output signal Bcosθsin (ωt + φ) with reference to the phase shift φ. do.
In addition, at the time of initial setting, the excitation signal Asinωt, which is the output of the first amplifier circuit 31, is fed back to the calculation unit 10, and the feedback signal and the sinusoidal output signal Bsinθsin (ωt + φ) or the cosine wave The output signal Bcos θsin (ωt + φ) is compared to detect the phase shift φ. In this way, when the phase shift φ is detected, the feedback of the output of the first amplifier circuit 31 to the calculator 10 is a signal between the DMA controller 12 and the first amplifier circuit 31. This allows the phase delay of to be ignored.
When the control unit 1 of the present embodiment is in a state in which the resolver signal processing is performed, the operation of initial setting to rotation angle detection is performed. The first AD converter 14, the second AD converter 15, and the third AD are performed. After the sampling start command is given to the converter 16, AD conversion processing of signals irrelevant to the resolver signal processing is also performed until the sampling processing is actually started. Therefore, after a predetermined time has elapsed after the sampling start command is issued (the sampling delay period D1 described later), the sampling process of each AD converter is started. However, since the period D1 is performed by a program, it is always constant, the processing time is not different every time, and there is no difference between the devices. From the above, after the initial setting, after the sampling start command is given to the first AD converter 14, the second AD converter 15, and the third AD converter 16, the schedule until the sampling process is actually performed. Sampling delay period D1 of time is calculated | required, and this value D1 is considered at the time of rotation angle detection, and rotation angle detection is performed. This will be described later.
2 shows a waveform diagram for explaining the operation of the resolver signal processing.
Graphs A to C show waveforms at the time of initial setting. The graph A shows the pulse of the sampling start command, and the graph B shows the excitation signal Asin omega t. Graph C shows a sinusoidal wave output signal Bsin θsin (ωt + φ). In addition, at the time of initial setting, the control part 1 detects phase shift detection among the sine wave output signal Bsin (theta) sin ((omega) + (+)) outputted from the resolver 2 and the cosine wave output signal (Bcos (theta) sin ((ωt + (phi))). Select any one. However, since the rotation angle θ is not clear at the initial setting, for example, when θ = 90 degrees, the cosine wave output signal Bcosθsin (ωt + φ) is zero, and when θ = 0 degrees, the sinusoidal output signal Bsinθsin ( ωt + φ)) is zero, so the sinusoidal output signal Bsin θsin (ωt + φ) is selected for phase shift detection when θ = 90 degrees, and the cosine wave output signal (phase shift detection) when θ = 0 degrees. Bcosθsin (ωt + φ)).
In FIG. 2, at the time of initial setting, a sampling start command is issued to the first AD converter 14, the second AD converter 15, and the third AD converter 16 from the control unit 1. At the same time, the arithmetic unit 10 sets a reference phase as a reference phase for starting to read the sine wave data for two cycles stored in the memory 11. The reference phase is set at the position of the first phase zero of the sine wave data for two cycles, that is, the head address of the memory 11. Then, the DMA controller 12 is instructed to read sine wave data for one cycle from this reference phase and perform DMA transfer.
3 conceptually illustrates sinusoidal data stored in the memory 11. The sinusoidal data stored in the memory 11 is actually duty ratio data for generating a sinusoidal signal, and is not data indicating the value of the sinusoidal wave itself as shown in FIG. In Fig. 3, the reference phase is the position of the first phase zero, that is, the position of the head address of the memory 11. Therefore, the DMA controller 12 transmits sine wave data of one cycle from the reference phase to the PWM signal generation circuit 13. Since DMA transfer is performed, the calculation unit 10 can perform other work in the period of the transfer. The PWM signal generation circuit 13 generates the PWM signal based on the duty ratio and transmits the transmitted sinusoidal data to the CR filter 30. The CR filter 30 converts the input PWM signal into a sinusoidal wave signal sinωt and outputs it to the first amplifier circuit 31. The first amplifier circuit 31 amplifies the input sinusoidal signal sinωt and outputs it to the resolver 2 as an excitation signal Asinω. Graph B shows this excitation signal Asin [omega]. The excitation signal Asin omega t is output to the resolver 2 and also to the first input filter 32. That is, the excitation signal Asin omega t is fed back to the control unit 1.
The resolver 2 is a sinusoidal sinusoidal output signal (sinθsin (ωt + φ)) modulated by a sinusoidal wave sinθ and a cosine wave cosθ and a resolver cosine wave output signal cosθsin based on the input excitation signal Asinωt. ([omega] t + [phi]) is generated and these are output to the second amplifying circuit 33 and the third amplifying circuit 34, respectively. θ is the rotation angle of the resolver. In addition, the rotation angle of the resolver 2 shall not change at the time of initial setting. For this reason, sin (theta) and cos (theta) take the same value.
The second amplifying circuit 33 and the third amplifying circuit 34 are resolver sine wave output signals sinθsin (ωt + φ) and resolver cosine wave output signals cosθsin (ωt + φ) input from the resolver 2. Are amplified to generate a sinusoidal output signal Bsinθsin (ωt + φ) and a cosine wave output signal Bcosθsin (ωt + φ), respectively, and the second input filter 35 and the third input for noise removal are generated. The output is output to the second AD converter 15 and the third AD converter 16 through the output filter 36. The graph C shows a sinusoidal wave output signal Bsin θsin (ωt + φ).
The first AD converter 14 samples the excitation signal Asin omega t over one period. The result of sampling is called excitation signal sampling result. The sampling period is 1/100 of the excitation signal Asinωt period, and the sampling repetition period R is a sinusoidal output signal Bsinθsin (ωt + φ) and a cosinewave output signal Bcosθsin (ωt + φ). It is set to a period longer than one period in which all one cycle of can be sampled.
The control unit 1 is programmed so as not to perform other processing when the first AD converter 14, the second AD converter 15, and the third AD converter 16 perform sampling processing. For this reason, there is no delay in the calculation unit 10 while sampling processing is performed in the first AD converter 14, the second AD converter 15, and the third AD converter 16.
The sampling delay time D1 is a delay time from a sampling start command to actual sampling. In the initial setting, this D1 is obtained, and the excitation signal Asinωt and the sinusoidal output signal Bsinθsin (ωt + peak values (extension values) of?) are obtained from the sampling results, and the detection times P1 and P2 of those peak values are obtained from the sampling start command time. The time obtained by subtracting the sampling delay time D1 from the detection time P1 of the peak value of the excitation signal Asinωt is referred to as D2. This D2 is the time from the time when the actual sampling is performed until the peak value of the excitation signal Asin omega t is detected, and this is called the excitation signal delay time. In addition, when the sampling delay time D1 is longer than the detection time P1 of the peak value, D2 becomes a negative value. Further, from the detection time P2 of the peak value of the sinusoidal output signal Bsinθsin (ωt + φ), the time obtained by subtracting the addition result of the sampling delay time D1 and the excitation signal delay time D2 (that is, from P2) Time subtracted from P1), and this time is called D3. This D3 corresponds to the phase difference of the said shift amount (phi) and rotation angle (theta) with respect to an excitation signal Asin omega t, and this is called modulation signal delay time.
In FIG. 2, the added value of the excitation signal delay time D2 and the modulation signal delay time D3 has the following meaning. That is, when the rotation angle is detected, if the excitation signal Asinωt is preceded by the phase amount corresponding to this addition value, the sinusoidal output signal Bsinθsin (ωt after the sampling start time has elapsed by the sampling delay time D1. + φ)) can be obtained. Therefore, in order to precede the excitation signal Asinωt by the above phase amount, that is, at the time of rotation angle detection, the excitation signal Asin (ωt + φ1) (φ1 = D1 + D2) is output to the resolver 2. In order to do this, the read start address for DMA transfer from the memory 11 is referred to as "reference phase + (D2 + D3) = correction phase" (see Fig. 3). ? 1 corresponds to the output time delay of the resolver 2 including the sampling delay time D1.
Rotation angle detection is performed immediately after initial setting. In the rotation angle detection, the calculation unit 10 indicates the data transfer amount for one cycle in order to DMA transfer the sine wave data from the memory 11 to the resolver 2 by one cycle for the DMA controller 12. A DMA transfer command including an address of the data and the correction phase of "reference phase + (D2 + D3)" which is the read start address is issued. At the same time, a sampling start command is issued to the first AD converter 14, the second AD converter 15, and the third AD converter 16.
The input / output unit 3 outputs an excitation signal Asin (ωt + φ1) to the resolver 2. The signal feeds back to the first AD converter 14 via the first input filter 32. The graph D of FIG. 2 shows this excitation signal Asin (ωt + φ1). The peak time P3 of the excitation signal Asin (ωt + φ1) shown in the graph D has a phase φ1 that corresponds to the time “D2 + D3” more than the excitation signal Asinωt shown in the graph B. As fast as From the resolver 2, a sinusoidal wave output signal Bsin θsin (ωt + φ1) is output and sampled by the second AD converter 15. In addition, the cosine wave output signal Bcos θsin (ωt + φ1) is output and sampled by the third AD converter 16. Graph E of Fig. 2 shows a sinusoidal wave output signal Bsin? Sin (? T +? 1).
As described above, since the peak value of the sinusoidal output signal Bsin? Sin (? T +? 1) can be obtained at the time P4 elapsed by the sampling delay time D1 after the sampling start command, the second AD converter 15 ), Sampling is performed at the time when the time D1 elapses. Similarly, since the peak value of the cosine wave output signal Bcos θsin (ωt + φ1) can be obtained at the time elapsed by the sampling delay time D1 after the sampling start command, in the third AD converter 16, the time ( Sampling is performed at the time when D1) elapses. When each peak value is obtained, the rotation angle (theta) can be calculated | required by calculation by a well-known method. Then, the calculating part 10 calculates the rotation angle (theta) of the resolver 2 from these peak values. That is, the rotation angle θ is calculated as follows based on the respective peak values.
Now, the peak value of the sinusoidal output signal Bsinθsin (ωt + φ1) is referred to as V1, and the peak value of the cosinewave output signal Bcosθsin (ωt + φ1) is referred to as V2. At the peak, sin (ωt + φ1) = 1. Therefore, V1 = Bsinθ and V2 = Bcosθ. At this time, the value of B is not clear. Thus, the ratio of V1 and V2 is calculated.
V1 / V2 = Bsinθ / Bcosθ = sinθ / cosθ = tanθ
For this reason, the value of B cancels.
The peak value V1 of the sine wave output signal is measured by the second AD converter 15. The peak value V2 of the cosine wave output signal is measured by the third AD converter 16. On the other hand, a relationship of tanθ '= tan (θ' + π) is established. At this time, the value of the rotation angle θ is determined based on whether each value of V1 = Bsinθ and V2 = Bcosθ takes a positive value or a negative value.
Therefore, rotation angle (theta) = tan-1 (V1 / V2), or rotation angle (theta) = (tan-1 (V1 / V2) + (pi)).
4 and 5 are flowcharts illustrating the above-described operation. Fig. 4 shows the operation at the time of initial setting and Fig. 5 shows the operation at the detection of the rotation angle. The initial setting is executed only once before the operation of the resolver 2, for example, when the ignition key of the vehicle is operated and the EPS-ECU starts to operate. Rotation angle detection is performed every fixed time (for example, every 250 microseconds) after initial setting.
In FIG. 4, in step ST1, the calculating section 10 issues a DMA transfer command for sinusoidal data for one cycle from the reference phase to the DMA controller 12, and simultaneously issues a sampling start command in step ST2. After the sampling start command, the actual sampling is performed after the sampling delay time D1 elapses. In step ST3, the detection time P1 of the peak of the excitation signal Asinωt and the detection time P2 of the peak of the sinusoidal output signal Bsinθsin (ωt + φ1) (φ1 = D1 + D2) are obtained.
From these values, in step ST4, the excitation signal delay time D2 and the modulated signal delay time D3 are obtained. In addition, in step ST5, the resolver output signal time delay? 1 (= D2 + D3) is obtained. This phi 1 is used as the correction phase, and the read start address of the sine wave data transmitted by DMA is detected at the next rotation angle detection. This completes the initial setup.
In the rotation angle detection of FIG. 5, in step ST10, the calculation unit 10 reads the sine wave data for one cycle from the crystal phase to the DMA controller 12 so as to perform DMA transfer to the PWM signal generation circuit 13. Give a DMA transfer command. At this time, the excitation signal output to the resolver 2 becomes the excitation signal Asin (ωt + φ1). In step ST2, a sampling start command is issued. At this time, in the present embodiment, there is no sampling delay caused by the first AD converter 14, the second AD converter 15, and the third AD converter 16. For this reason, the sampling delay time D1 is zero. Then, in step ST12, the 2nd AD converter 15 and the 3rd AD converter 16 perform the sinusoidal output signal Bsin (theta) sin ((omega) + (phi) 1) and cosine at the elapsed time of the sampling delay time D1 calculated | required by the initial setting. The wave output signal Bcos? Sin (? T +? 1) is sampled. The resolver output obtained by this sampling has a peak value for both the sinusoidal output signal and the cosine wave output signal. And in step ST13, the calculating part 10 calculates the angle (theta) of the resolver 2 by arithmetic.
According to the above-described processing procedure, the calculation unit 10 only needs to issue a DMA transfer command to the DMA controller 12 when outputting the excitation signal to the resolver 2, so that the load on the calculation unit 10 is small. For this reason, other processes can be performed by that, and the operation efficiency of EPS-ECU can be improved. The program step may also be a DMA transfer command step only. In the DMA transfer, since only the ink address of the read address can be used, in the configuration in which the sine wave data for one cycle is stored in the memory 11, when the sine wave data is read from the crystal phase, it is for one cycle. Since the sinusoidal data of? Cannot be outputted, the sinusoidal data for two cycles is stored in the memory 11 as in the present embodiment, so that the phase shift detected at the initial setting irrespective of the magnitude of the corrected phase, that is, Irrespective of the size, it is possible to reliably transfer sine wave data for one cycle.
According to the present invention, since the burden on the controller is small when the excitation signal is applied to the resolver, and the DMA transfer command is issued only when the excitation signal is transmitted to the resolver, the processing steps are simplified, resulting in high speed and low cost. Can contribute.
Excitation signal transmitting means for transmitting an excitation signal consisting of a sine wave to a resolver;
A resolver signal processing device comprising: an operation unit for detecting an extreme value between a sinusoidal output signal and a cosine wave output signal from a resolver and detecting a rotation angle of the resolver based on the value;
The excitation signal transmitting means includes a storage unit for storing sine wave data for two cycles, and a DMA transfer unit for DMA transfer of sine wave data for one cycle from the phase designated by the storage unit as an excitation signal,
At the initial setting performed before the operation of the resolver, a DMA transfer command of an excitation signal is made to the DMA transfer unit from a reference phase to detect phase shifts of the excitation signal and the sinusoidal output signal or the cosine wave output signal,
At the time of detecting the rotation angle executed immediately after the initial setting, a DMA transfer command of an excitation signal is given to the DMA transfer unit from a corrected phase preceded by a phase relative to a reference phase by the phase shift, and the extreme value at that time And the rotation angle is detected based on the resolver signal processing apparatus.
A resolver signal processing method for transmitting an excitation signal composed of a sine wave to a resolver, detecting an extreme value of a sine wave output signal and a cosine wave output signal from the resolver, and detecting a rotation angle of the resolver based on the value.
At the initial setting performed before the operation of the resolver, DMA transfer of sinusoidal data for one cycle from the reference phase of the sinusoidal data for two cycles stored in the storage unit as an excitation signal to the resolver
Detect phase shift of the excitation signal and the sinusoidal output signal or the cosine wave output signal,
At the time of detection of the rotation angle performed after the initial setting of the resolver, the phase whose position precedes the reference phase by the phase shift is set as the correction phase, and the crystal phase in the two cycles of sine wave data stored in the storage unit. Sinusoidal data for one cycle from the DMA is transmitted to the resolver as an excitation signal,
A method of processing a resolver signal, characterized by detecting an extreme value of a sine wave output signal and a cosine wave output signal from the resolver, and detecting a rotation angle of the resolver based on the value.
KR1020070005999A 2006-03-15 2007-01-19 Resolver signal processing device KR100812036B1 (en)
JPJP-P-2006-00071597 2006-03-15
KR20070093802A KR20070093802A (en) 2007-09-19
KR100812036B1 true KR100812036B1 (en) 2008-03-10
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