Source: https://patents.justia.com/patent/5638492
Timestamp: 2019-08-21 07:36:41
Document Index: 295015746

Matched Legal Cases: ['art 3', 'art 3', 'art 6', 'art 3', 'art 3', 'art 6']

US Patent for Information processing apparatus and monitoring apparatus Patent (Patent # 5,638,492 issued June 10, 1997) - Justia Patents Search
Justia Patents US Patent for Information processing apparatus and monitoring apparatus Patent (Patent # 5,638,492)
Aug 17, 1994 - Hitachi, Ltd.
The concept of this known example will be explained below. When an input/output relation is to be represented using fuzzy reasoning in applications to control, recognition and so on, if dedicated hardware is used in order to speed up operations such as calculations of membership function values and composition of fuzzy rules, which are executed every time the reasoning is performed, the circuit scale of the hardware will be extremely extended when the number of input data items and the number of fuzzy rules are increased. To solve this problem, this known example has all possible input/output relations previously stored in a memory, since if a value of input data is determined, the value of output data is uniformly determined also in fuzzy reasoning. For example, when there are two input data items which are each represented by an 8-bit integer value, the values of the input data are regarded as an address having 16 bits, and output values derived by the fuzzy reasoning corresponding to respective input values given as addresses are stored in a memory having a capacity of 65,536 (=2.sup.16) words. In this manner, all operations required for the fuzzy reasoning can be executed by replacing the operations with the addressing of memory.
While the prior art 3 is characterized in that high speed processing is enabled with a relatively simple configuration, a majority of methods belonging to the prior art 3 are supposed to treat two or at most three input variables. If the number of input variables is increased beyond three, an immense memory capacity is required to store lookup tables. Particularly, with a built-in type controller, the provision of a memory having an extremely large capacity is very difficult to realize. For example, if five input variables are to be treated and their values are respectively represented in eight bits, the complete input data is represented by a total of 40 bits. Thus, for storing these data items in a lookup table, the memory requires a capacity of 2.sup.40, i.e., one tera words. For a built-in type controller, this is almost impossible to realize with respect to the cost. Since the number of input variables is increased as a system becomes more complicated, it is apparent that the simple lookup table-based system is applicable only to a limited range.
The prior art 6 essentially implements the prior art 3 with hardware so that a similar problem implied in the prior art 3 cannot be avoided with respect to the memory capacity. Even if an auxiliary storage unit is additionally employed, the prior art 6 cannot solve a similar problem, which becomes more serious as the number of input variables is increased. A method which reduces the capacity of memory by a multi-stage connection, as shown in JP-A-2-56602, apparently causes restrictions on expressible input/output relations. Specifically, supposing that four input variables are divided into two sets each including two variables, and input/output relations are represented by referencing two-stage tables, if all the input variables are represented in eight bits, three memories having a 64k-word capacity are sufficient to represent all the input/output relations. However, since the input variables have an information amount of 32 bits (4.times.8 bits), this method can merely represent an approximation of the input/output relations. This will be understood from the fact that part of the information provided by the input variables is lost at the time 16-bit input data of each set is converted to 8-bit data at the first stage of the lookup table reference in the method shown in JP-A-2-56602.
Then, in an averaging and output process 408, outputs from the memory cells 402, which have been stored in the internal register 407, are averaged to determine final control outputs. The resultant outputs are supplied to the distributer 307 and the fuel injector 308. Assume here that the averaging is performed such that the final outputs are derived, for example, from three memory cells, wherein, supposing that the outputs from the memory cells are represented by Ti and Ri (i=1, 2, 3), resultant averaged values Tav and Rav are expressed by Tav=.SIGMA.Ti/3 and Rav=.SIGMA.Ri/3, respectively, where .SIGMA. represents a sum of Ti or Ri with i=1, 2, 3.
D=.vertline.a-a'.vertline.+.vertline.v-v'.vertline.+.vertline.r-r'.vertline .+.vertline.t-t'.vertline.+.vertline.p-p'.vertline. (1)
D=.vertline.a-a'.vertline.+.vertline.v-v'.vertline.+.vertline.p-p'.vertline .(2)
Tav=.SIGMA.(Ti/Di)/.SIGMA.(1/Di)
Rav=.SIGMA.(Ri/Di)/.SIGMA.(1/Di)
At step 1205, outputs calculated from outputs of memory cells, for example Rav and Tav in the case of the first embodiment, are compared with R'av and T'av given as teacher data, respectively. Then, the difference E=.vertline.Rav-R'av.vertline.**2+.vertline.Tav-T'av.vertline.**2 is calculated. Next, the difference is compared with a predetermined threshold value .theta., and if the difference E is equal to or larger than the threshold value, processes at and after step 1206 are executed, while the process at step 1203 is again executed if smaller.
The thinking of this processing lies in that the contents of, for example, three memory cells used to calculate the outputs Rav, Tar, that is, the contents of either or both of response pattern data and output data, are modified such that the output difference E=.vertline.Rav-R'av.vertline.**2+.vertline.Tav-T'av.vertline.**2 becomes smaller. If a so-called method of steepest descent, which modifies both of the response pattern data and the input data in a direction in which the difference E most rapidly changes, is employed by way of example, the following procedure may be taken.
First, for output data Ri (i=1,2,3), the following equation is satisfied: ##EQU1## where .SIGMA. represents a sum of 1/Dj with j=1, 2, 3, so that modification of Ri may be performed in accordance with the following equations:
Ri.rarw.Ri+.DELTA.Ri, .DELTA.Ri=-.eta..multidot..differential.E/.differential.Ri(4)
where .eta. represents a constant called a learning coefficient for controlling a modification speed for Ri and is normally set to a fixed value approximately ranging from 0.01 to 0.2. Ti can also be modified in the same way completely.
.differential.E/.differential.x'i=.differential.E/.differential.Rav.multido t..differential.Rav/.differential.x'i+.differential.E/Tav.multidot..differe ntial.Tav/.differential.x'i (5)
.differential.Rav/.differential.x'i=.differential.Rav/.differential.(1/Di). multidot.(-1/Di**2).multidot..differential.Di/.differential.x'i(6)
.differential.E/.differential.(1/Di)=2(Rav-R'av).multidot.[Ri/.SIGMA.(1/Dj) -.SIGMA.Rj/(.SIGMA.(1/Dj)**2 ] (7)
.differential./.differential.x'i can be derived when these equations are combined. Thus, the modification by the method of steepest descent can be performed by modifying each response pattern data with the following equation:
x'i.rarw.x'i+.DELTA.x'i, .DELTA.x'i=-.eta..multidot..differential.E/.differential.x'i(8)
In the present embodiment, assume that respective symbolic names have been previously assigned unique numbers (which may be considered as bit patterns). In this way, symbolic data as well as numerical data can be treated in a manner similar to the first or second embodiment. It should be noted however that the distance for symbolic data is determined depending only on whether the symbols are equal or different. Therefore, the numbers have previously been subjected to an appropriate scale conversion of numerical data such that, for example, in a two-byte representation of integers, a range expressed by .gtoreq.0 in 2's complement representation corresponds to numerical data, while a range expressed by <0 corresponds to symbolic data. Then, if the following distance calculation logic is determined for the symbolic data (for example, represented by s): ##EQU2## numerical data can be mixed with symbolic data. In the above logic, s represents input data, s' the value of corresponding response pattern data, and d (>0) a proper constant. Symbolic data may include items which are meaningless unless they coincide. In this case, d in the above equation may be set to a very large value such that the output of that memory cell will not be actually selected unless the symbolic data coincides.
First, in the fuzzy inference engine 1703, examination is made as to which input variable was used to determine an output. When input values are designated, for example, x1-x10, a change in an output value is examined when x1 is changed by a minute amount as expressed by x1+.DELTA.x1 (for example, when an input value is represented by eight bits, the minute amount refers to the value represented by the less significant bit). If the output value changes, x1 is regarded to be used in the determination of the output value. This operation is sequentially repeated until x10 is examined.
At step 2007, the i-th input characteristic value X[i] is checked. If the value is missing, namely, X[i].noteq.*, step 2008 is executed.
In step 3004, for the i-th input sensor, there is obtained the difference Ei=.vertline.Ii-Oi.vertline. between the input data value Ii and the value of mean output data Oi, where .vertline..multidot..vertline. indicates the absolute value of .multidot..
4939648 July 3, 1990 O'Neil et al.
5267348 November 30, 1993 Someya et al.
036150 September 1981 EPX
2-56602 February 1990 JPX
Automobile Technique, vol. 46, No. 5, pp. 100-104. Hitachi Review, vol. 72, No. 11, Nov. 1990, "Decision Support Expert System for Financial Transactions", Shigemi et al, pp. 51-56. "Automatic Exposure Metering by Differential Vector Quantization", IBM Technical Dislosure Bulletin, vol. 33, No. 3B, Aug. 1990, pp. 75-76. W. Brockmann, "Decision Making in Rule-Based Real-Time Systems", Automatisierungstechnik, vol. 39, No. 9, Sep. 1991, pp. 310-316.
Inventors: Akira Maeda (Yokohama), Motohisa Funabashi (Sagamihara), Hiromasa Yamaoka (Hitachi), Nobuyuki Fujikura (Ageo), Mikio Yoda (Ibaraki-ken), Mitsuo Yanagi (Takahagi), Toshihide Ichimori (Kawasaki)
Application Number: 8/291,869
Current U.S. Class: 395/50; 395/51; 395/60; 395/61; 395/903