Source: http://www.google.com/patents/US8077511?dq=5,890,152
Timestamp: 2018-01-23 08:54:34
Document Index: 23757731

Matched Legal Cases: ['Application No. 03820492', 'Application No. 03763311', 'Application No. 03763311', 'Application No. 03763311', 'Application No. 2004', 'Application No. 092118353']

Patent US8077511 - Hybrid non-volatile memory - Google Patents
A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to...http://www.google.com/patents/US8077511?utm_source=gb-gplus-sharePatent US8077511 - Hybrid non-volatile memory
Publication number US8077511 B2
Application number US 11/829,370
Also published as US7283390, US20060023550, US20080205150
Publication number 11829370, 829370, US 8077511 B2, US 8077511B2, US-B2-8077511, US8077511 B2, US8077511B2
Inventors Alberto Pesavento
Patent Citations (206), Non-Patent Citations (70), Referenced by (4), Classifications (19), Legal Events (4)
US 8077511 B2
A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that provide an ON/OFF state output, and the like. Some of the outputs are used to calibrate circuits within a device following power-on. Other outputs are used to store information to be employed by various circuits.
This application is a Continuation Application of U.S. Pat. No. 7,283,390 filed on Sep. 28, 2005, which is a CIP of U.S. patent application Ser. No. 10/830,280 filed on Apr. 21, 2004; Ser. No. 11/839,985 filed on May 5, 2004; Ser. No. 11/016,546 filed on Dec. 17, 2004; and Ser. No. 11/015,293 filed on Dec. 17, 2004.
The present invention relates to Non-Volatile Memory (NVM) circuits and devices; and more particularly, to hybrid NVM devices that include multiple types of NVM circuits supported by common support circuitry.
Memory elements may be classified in two main categories: volatile and nonvolatile. Volatile memory loses any data as soon as the system is turned off. Thus, it requires constant power to remain viable. Most types of random access memory (RAM) fall into this category. Non-volatile memory does not lose its data when the system or device is turned off. An NVM device may be implemented as a MOS transistor that has a source, a drain, an access or a control gate, and a floating gate. It is structurally different from a standard MOSFET in its floating gate, which is electrically isolated, or “floating”.
Aspects of the invention are directed to a hybrid NVM circuit that includes a plurality of NVM sub-circuits of different types. The NVM sub-circuits, which can store data in a way that survives loss of power, may differ in their structure and/or function, but share common support circuitry.
FIG. 1A is a block diagram of a device that includes a programmable fuse block for storing data such as calibration data to be used by an operational component;
Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meanings identified below are not intended to limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference, the meaning of “in” includes “in” and “on.” The term “connected” means a direct electrical connection between the items connected, without any intermediate devices. The term “coupled” means either a direct electrical connection between the items connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, temperature, data, or other measurable quantity. The term “ordinary NVM” refers to an NVM circuit or device that stores and outputs a logic value to be used by an operational component. As such, the “ordinary NVM” may or may not be arranged to provide the logic value for special purposes such as trimming an analog circuit.
Device 202 includes hybrid NVM circuit 210 that is adapted to interact with other circuits 204. Individual cells of hybrid NVM 210 are adapted to store information as a result of “write” operation 206 and provide the stored information as a result of “read” operation 208. The information is stored even during a power-off state of device 202.
“Read” operation 208, which provides the stored information to one or more of the other circuits 204, may occur during a transition from the power-off state to a power-on state for some parts of hybrid NVM circuit 210. For other parts of hybrid NVM circuit 210, “read” operation 208 may occur during the power-on state upon being addressed by another circuit (e.g. a controller).
NVM cell 634 is adapted to store and provide a logic value such as a “1” or a “0” bit. While FIG. 6 shows an example implementation, an “ordinary” NVM cell may be implemented in any way known in the art.
The drain terminal of M0B is arranged to provide output signal OUT, which includes stored value 733. In one embodiment, stored value 733 may be a digital value “0” or “1”.
The programmable fuse forming NVM cell 732 is termed “self-latching”, meaning that once power is applied to the fuse, the latch of the associated fuse will eventually settle to some state. Details of programmable fuses are described in more detail in U.S. patent application Ser. No. 10/813,907 (IMPJ-0027A) filed on Mar. 30, 2004; Ser. No. 10/814,866 (IMPJ-0027B) filed on Mar. 30, 2004; and Ser. No. 10/814,868 (IMPJ-0027C) filed on Mar. 30, 2004.
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U.S. Classification 365/185.01, 365/185.28, 711/103
International Classification G11C11/34, G11C16/34
Cooperative Classification G11C11/005, G11C16/0416, G11C2216/10, G11C16/3477, G11C16/0441, G11C2216/26, G11C16/3486, G11C16/3468
European Classification G11C16/04F4, G11C16/04F1, G11C11/00C, G11C16/34V6Q, G11C16/34V6F, G11C16/34V6
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PESAVENTO, ALBERTO;REEL/FRAME:019783/0440