Source: https://patents.google.com/patent/US8059673B2/en
Timestamp: 2018-10-16 23:59:58
Document Index: 119982884

Matched Legal Cases: ['Application No. 200401969', 'Application No. 200401973', 'Application No. 200401166', 'Application No. 200401969', 'Application No. 200410047784', 'Application No. 200410038432', 'Application No. 200410038546', 'application No. 200410044503', 'Application No. 200410071497', 'Application No. 04255786', 'Application No. 04252205', 'Application No. 04251582', 'Application No. 04252056', 'Application No. 04252202', 'Application No. 04252057', 'Application No. 04252203', 'Application No. 04252054', 'Application No. 10162586', 'Application No. 04255611', 'Application No. 04251581', 'Application No. 04252054', 'Application No. 04252056', 'Application No. 04252057', 'Application No. 04252202', 'Application No. 04252203', 'Application No. 200402057', 'Application No. 04255609', 'Application No. 04255786', 'Application No. 04255610', 'Application No. 04255609', 'Application No. 04252055', 'Application No. 200405336', 'Application No. 04255610', 'Application No. 200405115', 'Application No. 200405129', 'Application No. 200410044503', 'Application No. 200410044503', 'Application No. 200410043419', 'Application No. 200410045686', 'Application No. 200410087460', 'Application No. 200410038545', 'Application No. 04252205', 'Application No. 200410038545', 'Application No. 200410095171', 'Application No. 200410043419', 'Application No. 200410071498', 'Application No. 2004100950502', 'Application No. 200410095171', 'Application No. 200410044503', 'Application No. 08153454', 'Application No. 08153726', 'Application No. 08155263', 'Application No. 08153724', 'Application No. 08155262']

US8059673B2 - Dynamic resource re-allocation in a packet based video display interface - Google Patents
Dynamic resource re-allocation in a packet based video display interface Download PDF
US8059673B2
US8059673B2 US11776411 US77641107A US8059673B2 US 8059673 B2 US8059673 B2 US 8059673B2 US 11776411 US11776411 US 11776411 US 77641107 A US77641107 A US 77641107A US 8059673 B2 US8059673 B2 US 8059673B2
Expired - Fee Related, expires 2024-12-28
US11776411
US20080008172A1 (en )
Genesis Microchip Inc
Typically, when the source is a video source, the data streams 110-114 include various video signals that can have any number and type of well-known formats, such as composite video, serial digital, parallel digital, RGB, or consumer digital video. The video signal can be an analog video signal provided the source 102 includes some form of an analog video source such as for example, an analog television, still camera, analog VCR, DVD player, camcorder, laser disk player, TV tuner, set top box (with satellite DSS or cable signal) and the like. The source 102 can also include a digital image source such as for example a digital television (DTV), digital still camera, and the like. The digital video signal can be any number and type of well known digital formats such as, SMPTE 274M-1995 (1920×1080 resolution, progressive or interlaced scan), SMPTE 296M-1997 (1280×720 resolution, progressive scan), as well as standard 480 progressive scan video.
In the described embodiment, the speed, or transfer rate, of the main link 222 is adjustable to compensate for link conditions. For example, in one implementation, the speed of the main link 222 can be adjusted in a range approximated by a slowest speed of about 1.0 Gbps to about 2.5 Gbps per channel in approximately 0.4 Gbps increments (see FIG. 3). At 2.5 Gbps per channel, the main link 222 can support SXGA 60 Hz with a color depth of 18 bits per pixel over a single channel. It should be noted that a reduction in the number of channels reduces not only the cost of interconnect, but also reduces the power consumption which is an important consideration (and desirable) for power sensitive applications such as portable devices and the like. However, by increasing the number of channels to four, the main link 222 can support WQSXGA (3200×2048 image resolution) with a color depth of 24-bits per pixel at 60 Hz. or QSXGA (2560×2048) with a color depth of 18-bits per pixel at 60 Hz, without data compression. Even at the lowest rate of 1.0 Gbps per channel, only two channels are required to support an uncompressed HDTV (i.e., 1080i or 720p) data stream.
23.76 GHz=210×33×57×111 Hz
Pixel clock rate=2A*3B×5C×11D
A=4 bits, B=2 bits, C=3 bits, and D=1 bit.
Audio rate=(audio sample rate)×(# bits per sample)×(# channels) Eq(2)
FIG. 6 shows a high-level diagram of the multiplexed main link stream 600 as an example of the stream 510 shown in FIG. 5 when three streams are multiplexed over the main link 222. The three streams in this example are: UXGA graphics (Stream ID=1), 1280×720p video (Stream ID=2), and audio (Stream ID=3). The small packet header size of main link packet 400 minimizes the packet overhead, which results in the very high link efficiency. The reason the packet header can be so small is that the packet attributes are communicated via the auxiliary channel 224 prior to the transmission of the packets over main link 222.
In the case of notebook applications, the transmitter on the motherboard graphics engine would drive through internal cabling, an integrated receiver/TCON which would drive the panel directly. For the most cost effective implementation, the receiver/TCON would be mounted on the panel thereby reducing the number of interconnect wires to 8 or 10 as shown in FIG. 24
All of the above examples assume integrated transmitters. However, is it quite feasible to implement as a standalone transmitter integrating into PCI and PCI Express environments through the AGP or SDVO slots, respectively. A standalone transmitter will enable output streams without any change in graphics hardware or software.
For example, if the main link in configured to have four lanes, then the main link can be configured as single lane that is sufficient to support High Definition (HD) resolution (i.e., 1080i/720p) as well as PC resolutions up to 1680×1050 (WSXGA+). Alternatively, if the main link is configured as a 2-lane configuration, then full HD (1080p) and PC resolutions up to 1920×1200 (WUXGA) can be supported. Therefore, when some of the lanes are unused, then the wires for the unused lanes can be used for other purposes (such as to carry power and USB, for example).
US11776411 2003-05-01 2007-07-11 Dynamic resource re-allocation in a packet based video display interface Expired - Fee Related US8059673B2 (en)
US46780403 true 2003-05-01 2003-05-01
US47408403 true 2003-05-28 2003-05-28
US47408503 true 2003-05-28 2003-05-28
US50406003 true 2003-09-18 2003-09-18
US10726794 US20040218599A1 (en) 2003-05-01 2003-12-02 Packet based video display interface and methods of use thereof
US11776411 US8059673B2 (en) 2003-05-01 2007-07-11 Dynamic resource re-allocation in a packet based video display interface
EP20080153724 EP2015170A1 (en) 2007-07-11 2008-03-31 Dynamic resource re-allocation in a packet based video display interface
KR20080063251A KR101471669B1 (en) 2007-07-11 2008-07-01 Dynamic resource reallocation in the packet-based multimedia interface
JP2008179244A JP5588606B2 (en) 2007-07-11 2008-07-09 Multimedia interface
CN 200810128376 CN101345039B (en) 2007-07-11 2008-07-10 Dynamic resource re-allocation in a packet based video display interface
US10726794 Continuation-In-Part US20040218599A1 (en) 2003-05-01 2003-12-02 Packet based video display interface and methods of use thereof
US20080008172A1 true US20080008172A1 (en) 2008-01-10
US8059673B2 true US8059673B2 (en) 2011-11-15
ID=39560877
US11776411 Expired - Fee Related US8059673B2 (en) 2003-05-01 2007-07-11 Dynamic resource re-allocation in a packet based video display interface
US (1) US8059673B2 (en)
EP (1) EP2015170A1 (en)
JP (1) JP5588606B2 (en)
KR (1) KR101471669B1 (en)
CN (1) CN101345039B (en)
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