Source: http://www.google.com/patents/US7159041?dq=5,664,133
Timestamp: 2016-08-27 13:44:31
Document Index: 348631072

Matched Legal Cases: ['art/9612', 'art4', 'art/9606', 'art4', 'art/9606', 'art7', 'art/9606', 'art5', 'art/9606', 'art6', 'art/9606', 'art8', 'art 2']

Patent US7159041 - Method and system for defining and controlling algorithmic elements in a ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are...http://www.google.com/patents/US7159041?utm_source=gb-gplus-sharePatent US7159041 - Method and system for defining and controlling algorithmic elements in a graphics display systemAdvanced Patent SearchPublication numberUS7159041 B2Publication typeGrantApplication numberUS 09/796,577Publication dateJan 2, 2007Filing dateMar 1, 2001Priority dateMar 7, 2000Fee statusPaidAlso published asUS7782316, US7800606, US7800607, US7884817, US7965288, US20020033817, US20050027682, US20050052456, US20050086317, US20050086669, US20100039430Publication number09796577, 796577, US 7159041 B2, US 7159041B2, US-B2-7159041, US7159041 B2, US7159041B2InventorsCharles N. Boyd, Michael A. ToelleOriginal AssigneeMicrosoft CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (24), Non-Patent Citations (75), Referenced by (12), Classifications (8), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for defining and controlling algorithmic elements in a graphics display system
D3DVSD—TOKEN_NOP=0, //NOP or extension D3DVSD—TOKEN_STREAM, //stream selector D3DVSD—TOKEN_STREAMDATA, //stream data definition (map to vertex input memory) D3DVSD_TOKEN_TESSELLEATOR, //vertex input memory from tessellator D3DVSD_TOKEN_CONSTMEM, //constant memory from shader D3DVSD_TOKEN_EXT, //extension D3DVSD_TOKEN_END=7, //end-of-array (requires all DWORD bits to be 1) D3DVSD_FORCE_DWORD=0x7fffffff,//force 32-bit size enum }D3DVSD_TOKENTYPE; #define D3DVSD_TOKENTYPESHIFT 29 #define D3DVSD_TOKENTYPEMASK (7<<D3DVSD_TOKENTYPESHIFT) #define D3DVSD_STREAMNUMBERSHIFT 0 #define D3DVSD_STREAMNUMBERMASK (0xF << D3DVSD_STREAMNUMBERSHIFT) #define D3DVSD13DATALOADTYPESHIFT 28 #define D3DVSD13DATALOADTYPEMASK (0x1<< #D3DVSD_DATALOADTYPESHIFT) #define D3DVSD_DATATYPESHIFT 16 #define D3DVSD_DATATYPEMASK (0xF<<D3DVSD_DATATYPESHIFT) #define D3DVSD_SKIPCOUNTSHIFT 16 #define D3DVSD_SKIPCOUNTMASK (0xF<<D3DVSD_SKIPCOUNTSHIFT) #define D3DVSD_VERTEXREGSHIFT 0 #define D3DVSD_VERTEXREGMASK (0x1F<<D3DVSD_VERTEXREGSHIFT) #define D3DVSD_VERTEXREGINSHIFT20 #define D3DVSD_VERTEXREGINMASK (0xF<<D3DVSD_VERTEXREGINSHIFT) #define D3DVSD_CONSTCOUNTSHIFT 25 #define D3DVSD_CONSTCOUNTMASK (0xF<<D3DVSD_CONSTCOUNTSHIFT) #define D3DVSD_CONSTADDRESSSHIFT 0 #define D3DVSD_CONSTADDRESSMASK (0xF<< D3DVSD_CONSTADDRESSSHIFT) #define D3DVSD_CONTRSSHIFT 16 #define D3DVSD_CONSTRSMASK (0x1FFF<<D3DVSD_CONSTRSSHIFT) #define D3DVSD_EXTCOUNTSHIFT 24 #define D3DVSD_(0x1F<<D3DVSD_EXTCOUNTSHIFT) #define D3DVSD_EXTINFOSHIFT 0 #define D3DVSD_EXTINFOMASK (0xFFFFFF<<D3DVSD_EXTINFOSHIFT) #define D3DVSD_MAKETOKENTYPE(tokenType) ((tokenType<< D3DVSD_TOKENTYPESHIFT) & D3DVSD_TOKENTYPEMASK) //macros for generation of Create VertexShader Declaration token array //Set current stream //_StreamNumber [0..(MaxStreams-1)]stream to get data from // #define D3DVSD_STREAM(_StreamNumber)\
(D3DVSD_MAKETOKENTYPE(D3DVSD_TOKEN—STREAM)| (D3DVSD_STREAMTESSMASK)) //bind single vertex register to vertex element from vertex stream // //_VertexRegister [0..15] address of the vertex register //_Type [D3DVSDT_*] dimensionality and arithmetic data type #define D3DVSD_REG(_VertexRegister,_Type)\
//Input is in D3DCOLOR format (ARGB) expanded to (R, G, B, A) #define D3DVSDT_UBYTE4 0x05 //4D unsigned byte #define D3DVSDT_SHORT2 0x06 //2D signed short expanded to (value, value, 0., 1.) #define D3DVSDT_SHORT4 0x07 //4D signed short //assignments of vertex input registers for fixed function vertex shader // #define D3DVSDE_POSITION 0 #define D3DVSDE_BLENDWEIGHT 1 #define D3DVSDE_BLENDINDICES 2 #define D3DVSDE_NORMAL 3 #define D3DVSDE_PSIZE 4 #define D3DVSDE_DIFFUSE 5 #define D3DVSDE_SPECULAR 6 #define D3DVSDE_TEXCOORD0 7 #define D3DVSDE_TEXCOORD1 8 #define D3DVSDE_TEXCOORD2 9 #define D3DVSDE_TEXCOORD3 10 #define D3DVSDE_TEXCOORD4 11 #define D3DVSDE_TEXCOORD5 12 #define D3DVSDE_TEXCOORD6 13 #define D3DVSDE_TEXCOORD7 14 #define D3DVSDE_POSITION2 15 #define D3DVSDE_NORMAL2 16 //Maximum supported number of texture coordinate sets #define D3DDP_MAXTEXCOORD8 ;begin_internal //-------------------------------------------------------------------- // //Pixel Shader (PS) & Vertex Shader (VS) Instruction Token Definition // //**** Version Token **** //[07:00] minor version number //[015:08] major version number //[31:16] // PS 0xFFFF // VS 0xFFFE // //**** End Token **** //[31:00] 0x0000FFFF // **** Comment Token **** //[15:00] 0xFFFE //[30:16] DWORD Length (up to 2{circle around ( )}15 DWORDS =128 KB) //[31] 0x0 // // ****Instruction Token **** //[15:00] Opcode (D3DSIO_*) //[23:16] Opcode-Specific Controls //[29:24] Reserved 0x0 //[30] Co-Issue—if set then execute this instruction with the previous instruction(s) //[31] 0x0 // //**** Destination Parameter Token **** //[07:00] Register Number (offset in register file) //[15;08] Reserved 0x0 //[19:16] Write Mask // [16] Component 0 (X;Red) // [17] Component 1 (Y;Green) // [18] Component 2 (Z;Blue) // [19] Component 3 (W;Alpha) //[23:30] // PS Result Modifier // VS Reserved 0x0 //[27:24] // PS Result Shift Scale (signed shift) // VS Reserved 0x0 //[30:28]VS Reserved Type // VS Reserved Type // [0x0] Temporary Register File // [0x1] Reserved // [0x2] Reserved // [0x3] // VS Address Register (reg num must be zero) // PS Reserved // [0x4] // VS Rasterizer Output Register File // PS Reserved // [0x5] // VS Attribute Output Register File // PS Reserved // [0x6] // VS Texture Coordinate Register File // PS Reserved // [0x7] Reserved //[31] 0x1 // //**** Source Parameter Token **** //[12:00] Register Number (offset in register file) //[13] // VS Relative Address // PS Reserved 0x0 //[14:15] // VS Relative Address Register Component // PS Reserved 0x0 //[23:16] Source Component Swizzle // [17:16] Component 0 Swizzle // [19:18] Component 1 Swizzle // [21:20] Component 2 Swizzle // [23:22] Component 3 Swizzle //[27:24] Source Modifier // [0x0] None // [0x1] Negate // [0x2] Bias // [0x3] Bias and Negate // [0x4] Sign // [0x5] Sign and Negate // [0x6] Complement // [0x7-0xf] Reserved // [30:28] Register Type // [0x0] Temporary Register File // [0x1] Input Register File // [0x2] Constant Register File // [0x3-0x7] Reserved // [31]0x1 // The exception for source parameter tokens is with the instruction: //D3DSIO_DEF c#,f0,f1,f2,f2 //Here, the source parameter tokens (f#) are each taken as 32 bit floats. // ;end_internal // //Instruction Token Bit Definitions // #define D3DSI_OPCODE_MASK 0x0000FFFF typedef enum_D3DSHADER_INSTRUCTION_OPCODE_TYPE {
D3DSIO_COMMENT=0xFFFE, D3DSIO_END=0xFFFF, D3DSIO_FORCE_DWORD=0x7fffffff, //force 32-bit size enum. }D3DSHADER_INSTRUCTION_OPCODE_TYPE; // //Co-Issue Instruction Modifier-if set then this instruction is to be //issued in parallel with the previous instruction(s) for which this bit //is not set. // #define D3DSI_COISSUE 0x40000000 // Parameter Token Bit Definitions // #define D3DSP_REGNUM_MASK 0x00000FFF //destination parameter write mask #define D3DSP_WRITEMASK—0 0x00010000//Component 0(X;Red) #define D3DSP_WRITEMASK—1 0x00020000//Component 1(Y;Green) #define D3DSP_WRITEMASK—0 0x00040000//Component 2(Z;Blue) #define D3DSP_WRITEMASK—0 0x00080000//Component 3(W;Alpha) #define D3DSP_WRITEMASK_ALL 0x000F0000//All Components //destination parameter modifiers #define D3DSP_DSTMOD_SHIFT 20 #define D3DSP_DSTMOD_MASK 0x00F00000 typedef enum_D3DSHADER_PARAM_DSTMOD_TYPE {
D3DSPSM_NONE=0<<D3DSP_SRCMOD_SHIFT, //nop D3DSPSM_NEG=1<<D3DSP_SRCMOD_SHIFT, //negate D3DSPSM_BIAS=2<<D3DSP_SRCMOD_SHIFT, //bias D3DSPSM_BIASNEG=3<<D3DSP_SRCMOD_SHIFT, //bias and negate D3DSPSM_SIGN=4<<D3DSP_SRCMOD_SHIFT, //sign D3DSPSM_SIGNNEG=5<<D3DSP_SRCMOD_SHIFT, //sign and negate D3DSPSM_COMP=6<<D3DSP_SRCMOD_SHIFT, //complement D3DSPSM_FORCE_DWORD=0x7fffffff, //force 32-bit size enum }D3SHADER_PARAM_SRCMOD_TYPE; //pixel shader version token #define D3DPS_VERSION(_Major,_Minor) (0xFFFF0000|((_Major)<<8|(—Minor)) //vertex shader version token #define D3DVS_VERSION(_Major,_Minor) (0xFFFE0000|((_Major)<<8|(—Minor)) //extract major/minor from version cap #define D3SHADER_VERSION_MAJOR(_Version) (((_Version)8)&0xFF) #define D3SHADER_VERSION_MINOR(_Version) (((_Version)0)&0xFF) //destination/source parameter register type #define D3DSI_COMMENTSIZE_SHIFT 16 #define D3DSI_COMMENTSIZE_MASK 0x7FFF0000 #define D3SHADER_COMMENT(_DWordSize)\ ((((_DWordSize)<<D3DSI_COMMENTSIZE_SHIFT)&D3DSI_COMMENTSIZE_MASK)| D3DSIO_COMMENT) //pixel/vertex shader end token #define D3DPS_END( ) 0x0000FFFF #define D3DVS_END( ) 0x0000FFFF While the above exemplary computer-executable instructions have been described in the context of a procedural shader, these concepts and principles may be applied to any 3D hardware rendering device utilized in connection with a graphics display system.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4805098May 5, 1986Feb 14, 1989Mips Computer Systems, Inc.Write bufferUS4953073Feb 6, 1986Aug 28, 1990Mips Computer Systems, Inc.Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memoriesUS4959779Nov 28, 1988Sep 25, 1990Mips Computer Systems, Inc.Dual byte order computer architecture a functional unit for handling data sets with differnt byte ordersUS5027270Oct 11, 1988Jun 25, 1991Mips Computer Systems, Inc.Processor controlled interface with instruction streamingUS5269021 *Oct 12, 1989Dec 7, 1993Texas Instruments IncorporatedMultiprocessor software interface for a graphics processor subsystem employing partially linked dynamic load modules which are downloaded and fully linked at run timeUS5398328Sep 27, 1993Mar 14, 1995Silicon Graphics, Inc.System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory ordersUS5590294May 24, 1995Dec 31, 1996Silicon Graphics, Inc.Method and apparatus for retarting pipeline processingUS5673377Sep 2, 1994Sep 30, 1997Ray Dream, Inc.Method and system for displaying a representation of a three-dimensional object with surface features that conform to the surface of the three-dimensional objectUS5721928 *May 16, 1996Feb 24, 1998Hitachi, Ltd.Method for partitioning computationUS5801717Apr 25, 1996Sep 1, 1998Microsoft CorporationMethod and system in display device interface for managing surface memoryUS5812136Oct 30, 1996Sep 22, 1998Microsoft CorporationSystem and method for fast rendering of a three dimensional graphical objectUS5822570Oct 30, 1996Oct 13, 1998Microsoft CorporationSystem and method for parsing and executing a single instruction stream using a plurality of tightly coupled parsing and execution unitsUS5844569Apr 25, 1996Dec 1, 1998Microsoft CorporationDisplay device interface including support for generalized flipping of surfacesUS5850232Apr 25, 1996Dec 15, 1998Microsoft CorporationMethod and system for flipping images in a window using overlaysUS5864703Oct 9, 1997Jan 26, 1999Mips Technologies, Inc.Method for providing extended precision in SIMD vector arithmetic operationsUS5880736Jun 20, 1997Mar 9, 1999Silicon Graphics, Inc.Method system and computer program product for shadingUS5949424Feb 28, 1997Sep 7, 1999Silicon Graphics, Inc.Method, system, and computer program product for bump mapping in tangent spaceUS5964843Apr 25, 1996Oct 12, 1999Microsoft CorporationSystem for enhancing device driversUS6008816Apr 25, 1996Dec 28, 1999Microsoft CorporationMethod and system for managing color specification using attachable palettes and palettes that refer to other palettesUS6359630 *Jun 14, 1999Mar 19, 2002Sun Microsystems, Inc.Graphics system using clip bits to decide acceptance, rejection, clippingUS6489963 *Jun 22, 2001Dec 3, 2002Nintendo Co., Ltd.Application program interface for a graphics systemUS6515671 *Dec 6, 1999Feb 4, 2003Nvidia CorporationMethod, apparatus and article of manufacture for a vertex attribute buffer in a graphics processorUS6765571 *Jan 11, 2001Jul 20, 2004Sun Microsystems, Inc.Using a master controller to manage threads and resources for scene-based renderingUS20040201590 *Mar 8, 2004Oct 14, 2004Wu Tsailai Terry3-D graphics chip with embedded DRAM buffers* Cited by examinerNon-Patent CitationsReference1Abrash, M., "Inside Xbox Graphics," Dr. Dobb's J., Aug. 2000, 21-22, 24-26.2Antinori, F. et al., "Experience with a 30 cm<SUP>2 </SUP>silicon pixel plane in CERN experiment WA97," Nucl. Instr. Meth. Phys. Res. A., 1995, 360, 91-97.3Bachstein, W. et al., "Single-Chip erledigt Multimedia," Elektronik, 1996, 17, 58-62.4Bajaj, C. et al., "Making 3D Textures Practical," IEEE: Proceedings-Seventh Pacific Conference on Computer Graphics and Applications, Oct. 5-7, 1999, 259-269.5Bakalash, R. et al., "A Barrel Shift Microsystem for Parallel Processing," in MICRO 23 Microprogramming and Microarchitecture, IEEE: Proceedings of the 23<SUP>rd </SUP>Annual Workshop and Symposium, Orlando Florida, Nov. 27-29, 1990, 223-229.6Bankston, J. et al., "Pipeline Processing with Modula-2," J. Pascal, Ada, & Modula-2, 1986, 5(5), 46-51.7Biernat, M.J. et al., "Approximate Shadow Generation," IEEE Montech Conferences, Nov. 9-12, 1987, 97-101.8Brechb�hler, Ch. et al., "Parametrization of Closed Surfaces for 3-D Shape Description," Comp. Vision Image Understanding, Mar. 1995, 61(2), 154-170.9Chen, Li, "Generalization Discrete Object Tracking Algorithms and Implementation," in Vision Geometry VI, Proceedings of SPIE, Melter, R.A. et al. (eds.), Jul. 28-29, 1997, 3168, 184-195.10Chiarulli, D.M. et al., "Draft: A Dynamically Reconfigurable Processor for Integer Arithmetic," IEEE: Proceedings-7<SUP>th </SUP>Symposium on Computer Arithmetic, University of Illinois, Hwang, K. (ed.), Jun. 4-6, 1985, 309-317.11Conference Paper, "A Shading and Compositing Processor based on Crossbar Switches and SRAM Memory," 1999, 4 pages.12Corrie, B. et al., "Data Shaders," Proceedings Visulaization '93, San Jose, CA, Oct. 25-29, 1993, 275-282.13Cox, M. et al., "Multi-Level Texture Caching for 3D Graphics Hardware," IEEE: Proceedings-The 25<SUP>th </SUP>Annual International Symposium on Computer Architecture, Barcelona, Spain, Jun. 27-Jul. 1, 1998, 86-97.14Dietz, P.H. et al., "Simple Networks for Pixel Plane Median Filtering," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Dec. 1993, 40(12), 799-801.15Glazzard, N. et al., "Implementing a Shading Language," Computer Graphics 90, London, UK, Nov. 6-8, 1990, 111-121.16Gomes, J. et al., "Graphical Objects," The Visual Computer, 1996, 12, 269-282.17Gordon, R.L., Ph.D. et al., "Window Management, Graphics, and Operating Systems," Operating Systems Review, Jul. 1987, 21(3), 5-8.18Goris, A. et al., "A Configurable Pixel Cache for Fast Image Generation," IEEE Computer Graphics and Applications, Mar. 1987, 24-32.19Grimes, J. et al., "A New Processor with 3-D Graphics Capabilities," NCGA '89 Conference Proceedings: 10<SUP>th </SUP>Annual Conference and Exposition Dedicated to Computer Graphics, Philadelphia, Pennsylvania, Apr. 17-20, 1989, vol. 1, 275-284.20Grimes, J. et al., "The Intel i860 64-Bit Processor: A General-Purpose CPU with 3D Graphics Capabilities," IEEE Computer Graphics and Applications, Jul. 1989, 85-94.21Haig, T., "How to program in machine language," Electronics, Aug. 1982, 94-96, 98, 100-103.22Hanrahan, P. et al., "A Language for Shading and Lighting Calculations," Computer Graphics, 1990, 24(4), 289-298.23Harrison, J.P. et al., "The Role of Microcomputers in Interactive Graphical Planning," Engin. Software for Microcomputers, Proc., Apr. 1984, 631-641.24Ho, C-H et al., "Efficient Point-Based Rendering Techniques for Haptic Display of Virtual Objects," Presence, Oct. 1999, 8(5), 477-491.25Hoffman, C. et al., "Automatic Surface Generation in Computer Aided Design," supported by the National Science Foundation, Department of Computer Science, Cornell University, Ithaca, New York, Jan. 1985, 1-22.26Hummel, R., "Render Benders: 26 Graphics Cards for Fast 3-D," Byte, Mar. 1998, 112-119.27James, M., "3-D graphics to become accessible to all," Scientific Computing World, Feb. 1997, 41 and 43.28Johnson, S.P., "Direct3D Revealed: Microsoft's 3-D API provides device-independent access to acceleration hardware. Here's how it works," Core Technologies, http://byte.com/art/9612/sec5/art4.htm, Dec. 1996, 5 pages.29Jones, M. et al., "High-Performance Graphics Via Silicon Compilation," VLSI Systems Design, Mar. 1987, 32, 33, 36 and 38.30Kaya, E.M., "New Trends in Graphic Display System Architecture," in Frontiers in Computer Graphics, Proceedings of Computer Graphics, Tokyo '84, Kunii, T.L. (ed.), 1985, 310-320.31Kumar, S. et al., "Efficient rendering of trimmed NURBS surfaces," Computer-Aided Disign, Jul. 1995, 27(7), 509-521.32Labsik, U. et al., "Progressive transmission of subdivision surfaces," Computational Geometry, 2000, 15, 25-39.33Lachaud, J-O. et al., "Continuous Analogs of Digital Boundaries: A Topological Approach to Iso-Surfaces," Graphical Models, 2000, 62, 129-164.34Lapidous, E. et al., "Optimal Depth Buffer for Low-Cost Graphics Hardware," Trident Microsystems, Inc., 1999, 67-73.35Lastra, A. et al., "Real-Time Programmable Shading," Proceedings: 1995 Symposium on Interative 3D Graphics, Monterey, California, Apr. 9-12, 1995, 59-66.36Lee, J-A. et al., "SPARP: a single pass antialiased rasterization processor," Comput. & Graphics, 2000, 24, 233-243.37Leech, J., "OpenGL Extensions and Restrictions for PixelFlow," The University of North Caroline at Chapel Hill, 1995, 1-39.38Lichten, L., "A Solution to Surface Connectivity Problems in Computer-Aided Design," Computer Graphics, Mar. 1981, 14(4), 168-199.39Mabin, F.H. et al., "A Parallel Algorithm to Reconstruct Bounding Surfaces in 3D Images," J. Supercomputing, 1998, 12, 137-155.40McManus, D. et al., "Optimal Static 2-Dimensional Screen Subdivision for Parallel Rasterization Architectures," Comput. & Graphics, 1997, 21(2), 159-169.41Meyers, D. et al., "Surfaces from Contours," ACM Transactions on Graphics, Jul. 1992, 11(3), 228-258.42Micikevicius, P. et al., "Teaching a Computer Graphics Class Using DirectX," J. Comput. in Small Colleges; Proceedings of the Ninth Annual CCSC South Central Conference, (Jackson, Mississippi, Apr. 17-18), Meinke, J.G. (ed.), Mar. 1998, 13(4), 61-66.43Molnar, S. et al., "PixelFlow: High-Speed Rendering Using Image Composition," Computer Graphics, 26(2), 231-240.44Molnar, S. et al., "PixelFlow: The Continuing Saga," 1995 Parallel Rendering Symposium, Atlanta, GA, Oct. 30-31, 1995, p. 79.45Molnar, S., "The PixelFlow Texture and Image Subsystem,"Computers & Graphics, 1996, 20(4), 491-502.46Nishimura, H. et al., "A Multicomputer System Links: Its Architecture and Graphics Applications," IECON '84: International Conference on Industrial Electronics, Control and Instrumentation, Tokyo, Japan, Oct. 22-26, 1984, 1, 270-274.47NVIDIA Corporation, "System Platform Porcessor (SPP) / Integrated Graphics Processor (IGP): Redefining System and Graphics Performance," nForce SPP/IGP Product Overview, Jan. 2002, Version 1, 2 pages.48NVIDIA Corporation, "Technical Brief: NVIDIA nfiniteFX II Engine From Research to Real Time," Jan. 16, 2002, 7 pages.49NVIDIA Corporation, "Technical Brief: NVIDIA nForce Platform Processing Architecture," 2001, 1-9.50Ohbuchi, R. et al., "Embedding Data in 3D Models," in Interactive Distributed Multimedia Systems and Telecommunication Services, 4<SUP>th </SUP>International Workshop, IDMS '97, Darmstadt, Germany, Sep. 10-12, 1997, 1-10.51Ohhashi, M. et al., "A32b 3-D Graphic Processor Chip with 10M Pixels/s Gouraud Shading," 1988 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 1988, 168-169 and 352.52Olano, M. et al., "A Shading Language on Graphics Hardware: The PixelFlow Shading System," Proceedings of SIGGRAPH 98, Orlando, Florida, Jul. 19-24, 1998, 1-10.53Olano, M. et al., "Procedural Primitives in a High Performance, Hardware Accelerated, Z-Buffer Renderer," UNC Computer Science Technical Report 97-040, Department of Computer Science, University of North Carolina, Chapel Hill, North Carolina, 1997, 1-10.54Olano, M., "A Programmable Pipeline for Graphics Hardware," PhD Dissertation, Department of Computer Science, University of North Carolina at Chapel Hill, 1998, 1-168.55Pountain, D., "PixelFlow-Scalable Image Processing-It Divides and Conquers Rendering by Drawing the Objects First, Then Combining Them," Byte, 1995, 20(11), 6 pages.56Proudfoot, K. et al., "A Real-Time Procedural Shading System for Programmable Graphics Hardware," Computer Graphics Proceedings, SIGGRAPH, 2001, 159-170.57Rowlan, J.S. et al., "A distributed, parallel, interactive volume rendering package," IEEE: Proceedings-Visualization '94, Washington, D.C., Oct. 17-21, 1994, 21-30.58Schneider, B-O. et al., "An adaptive framework for 3D graphics over networks," Comput. & Graphics, 1999, 23, 867-874.59Schneider, B-O. et al., "M-Buffer: A Flexible MISD Architecture for Advanced Graphics," Comput. & Graphics, 1995, 19(2), 239-246.60Senthinathan, R. et al., "A 650-MHz, IA-32 Microprocessor with Enhanced Data Streaming for Graphics and Video," IEEE J. Solid-State Circuits, Nov. 1999, 34(11), 1454-1465.61Shinya, M., "Improvements on the Pixel-tracing Filter: Reflection/Refraction, Shadows, and Jittering," Proceedings: Graphics Interface '95, May 7-19, 1995, 92-102.62Shirali, N.S. et al., "A Parallel Architecture Graphics Processor," IEEE Southeastcon: Conference Proceedings, Knoxville, Tennessee, Apr. 11-13, 1998, 108-111.63Slusallek, P. et al., "Implementing RenderMan-Practice, Problems and Enhancements," Eurographics '94, 1994, 13(3), 443-454.64Smith, D.R. et al., "A Circuit-Switched Shared-Memory Multiprocessor," International J. Mini Microcomputers, 1995, 17(3), 108-118.65Sussman, H. et al., "Graphics Memory Architectures," Wescon/86 Conference Record, 1986, 1-6.66Swanson, R.W. et al., "A Fast Shaded-Polygon Rendered," Computer Graphics, Aug. 1986, 20(4), 95-101.67Teonnies, K.D. et al., "Volume rendering for interactive 3-d segmentation," in Image Display, Proceeding of SPIE, Newport Beach, California, Feb. 23-25, 1997, 3031, 602-609.68Thompson, T., "An inside look at the most popular 3-D environments: OpenGL, QuickDraw 3D, and Direct3D," Must-See 3-D Engines, Jun. 1996, http://byte.com/art/9606/sec11/art4.htm, 7 pages.69Thompson, T., "Direct3D's Engine," Must-See 3-D Engines, Jun. 1996, http://byte.com/art/9606/sec11/art7.htm, 1 page.70Thompson, T., "Open GL's Command Structure," Must-See 3-D Engines, Jun. 1996, http://byte.com/art/9606/sec11/art5.htm, 1 page.71Thompson, T., "QuickDraw 3D's Command Structure," Must-See 3-D Engines, Jun. 1996, http://byte.com/art/9606/sec11/art6.htm, 1 page.72Thompson, T., "Three Ways to Tackle Multithreading," Must-See 3-D Engines, Jun. 1996, http://byte.com/art/9606/sec11/art8.htm, 1 page.73Wilson, J.L. et al., "Designing a Graphics Application Interface," Proceedings Graphics Interface '85, Montreal, Quebec, May 27-31, 1985, 373-380.74Yoshida, M. et al., "Trend of the computer graphics hardware," Information Processing Soc. of Japan, Oct. 1988, 29(10), 1109-1115.75Zheng, Y. et al., "Three-dimensional unstructured mesh generation: Part 2. Surface meshes," Comput. Methods Appl. Mech. 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