Source: http://www.google.com/patents/US20040046204?dq=6322901
Timestamp: 2016-12-06 01:05:46
Document Index: 161100641

Matched Legal Cases: ['art 123', 'art 124', 'art 123', 'art 124', 'arts 123', 'art 129', 'art 128', 'art 129', 'art 128', 'art 124', 'art 128', 'art 124', 'art 128', 'art 129', 'art 129', 'art 129', 'art 129', 'art 129', 'art 123', 'art 124', 'art 123', 'art 124', 'art 123', 'art 123', 'art 129', 'art 128', 'art 124', 'art 129', 'art 129']

Patent US20040046204 - Non-volatile memory device and method of forming the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection gate electrode and spaced apart from...http://www.google.com/patents/US20040046204?utm_source=gb-gplus-sharePatent US20040046204 - Non-volatile memory device and method of forming the sameAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20040046204 A1Publication typeApplicationApplication numberUS 10/458,133Publication dateMar 11, 2004Filing dateJun 10, 2003Priority dateSep 9, 2002Also published asUS6847078, US7351629, US20050101080Publication number10458133, 458133, US 2004/0046204 A1, US 2004/046204 A1, US 20040046204 A1, US 20040046204A1, US 2004046204 A1, US 2004046204A1, US-A1-20040046204, US-A1-2004046204, US2004/0046204A1, US2004/046204A1, US20040046204 A1, US20040046204A1, US2004046204 A1, US2004046204A1InventorsYong-Suk Choi, Og-Hyun LeeOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (4), Classifications (14), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetNon-volatile memory device and method of forming the same
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS [0024] The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like numbers refer to like elements throughout. [0025] [0025]FIG. 4 is a planar view of a portion of a non-volatile memory device in accordance with a preferred embodiment of the present invention. FIG. 5 is a cross-sectional view taken along a line I-I′ of the FIG. 4. [0026] Referring to FIGS. 4 and 5, a plurality of first active regions 102 are disposed in parallel in a predetermined region of a semiconductor substrate 100. A drain region 141 b is disposed in a predetermined region of each of the first active regions 102. A second active region 103 crosses the first active regions 102 and intervenes between a pair of drain regions 141 b. A common source region 141 a is formed in the second active region 103. The common source region 141 a and the drain regions 141 b are formed of an impurity diffusion layer. The drain regions 141 b may be electrically connected to a bit line (not shown). [0027] A pair of selection gate electrodes 125 crosses over the first active regions 102 on both sides of the second active region 103. The selection gate electrode 125 is parallel to the second active region 103. The selection gate electrode 125 crosses over the first active regions 102 between the pair of drain regions 141 b. [0028] The selection gate electrode 125 comprises a selection-vertical part 123 and a selection-protruding part 124. The selection-vertical part 123 has a first curved sidewall “a” and a first planar sidewall “b”. The selection-protruding part 124 is in contact with a lower portion of the first planar sidewall “b”. Bottoms of the selection-vertical and selection-protruding parts 123 and 124 may be disposed at a substantially identical height from the surface of the first active region 102. The pair of the selection gate electrodes 125 are preferably disposed such that the first planar sidewalls thereof face each other. [0029] A floating gate electrode 130 a is disposed over the first active region 102, between the selection gate electrode 125 and the common source region 141 a. The floating gate electrode 130 a is spaced apart from the selection gate electrode 125. The floating gate electrode 130 a comprises a floating-vertical part 129 and a floating-protruding part 128. The floating-vertical part 129 comprises a second curved sidewall “c” and a second planar sidewall “d”. The floating-protruding part 128 is in contact with a lower portion of the second planar sidewall “d”. Bottoms of the floating-vertical and floating-protruding portions 129 and 128 may be disposed at an identical height from the surface of the first active region 102. [0030] The selection gate electrode 125 and the floating gate electrode 130 a are disposed symmetrically over the first active region 102. The selection and floating gate electrodes 125 and 130 a are disposed such that the first and second planar sidewalls “b” and “d” face each other. The selection and floating gate electrodes 125 and 130 a are preferably formed of a doped poly silicon layer. [0031] A separation insulating pattern 105 b intervenes between the selection-protruding part 124 and the floating-protruding part 128. The separation insulating pattern 105 b electrically insulates the selection gate electrode 125 from the floating gate electrode 130 a. [0032] A tunnel insulating layer 115 is disposed between the selection gate electrode 125 and the first active region 102, and between the floating gate electrode 130 a and the first active region 102. The tunnel insulating layer 115 is preferably formed of a thermal oxide layer. The tunnel insulating layer 115 may be disposed on the impurity diffusion layers 141 a and 141 b. The tunnel insulating layer 115 may be omitted from above the impurity diffusion layers 141 a and 141 b. [0033] A hard mask pattern 107 b is preferably disposed between the selection gate electrode 125 and the floating gate electrode 130 a. A first sidewall and a second sidewall of the hard mask pattern 107 b are in contact with the first and second planar sidewalls “b” and “d”, respectively. The selection-protruding part 124 and floating-protruding part 128 are parallel and intervene between the hard mask pattern 107 b and the first active region 102. Preferably, a top surface of the hard mask pattern 107 b is lower than a top of the floating-vertical part 129. The hard mask pattern 107 b may be formed of silicon nitride. The hard mask pattern 107 b may be omitted. [0034] An erasing gate electrode 137 a crossing over the first active region 102 is disposed over the floating gate electrode 130 a. The erasing gate electrode 137 a is parallel to the selection gate electrode 125. The erasing gate electrode 137 a preferably comprises a lower groove 139 surrounding an upper portion of the floating-vertical part 129. An erasing gate insulating layer 135 is disposed between the erasing gate electrode 137 a and the floating gate electrode 130 a. The erasing gate electrode 137 a may be formed of a doped polysilicon layer, and the erasing gate insulating layer 135 may be formed of silicon oxide. The erasing gate insulating layer 135 may be disposed on the impurity diffusion layers 141 a and 141 b. The erasing gate insulating layer 135 may be omitted from above the impurity diffusion layers 141 a and 141 b. [0035] A unit cell of the non-volatile memory device in accordance with a preferred embodiment comprises the selection gate electrode 125, the floating gate electrode 130 a, the erasing gate electrode 137 a, the source region 141 a, and the drain region 141 b. [0036] Programming and erasing of the unit cell will be explained as follows. [0037] For programming the unit cell, a turn-on voltage is applied to the selection gate electrode 125 and a program voltage is applied to the common source region 141 a. The drain region 141 b is grounded. Thus, electrons are injected into the floating gate electrode 130 a from the first active region 102 under the floating gate the electrode 130 a. [0038] For erasing the unit cell, an erasing voltage is applied to the erasing gate electrode 137 a and the common source region 141 a is grounded. Therefore, electrons stored in the floating gate electrode 130 a are released to the erasing gate electrode 137 a. A top of the floating-vertical part 129 is formed having a point, so that an electric field caused by the erasing voltage is concentrated on the top of the floating-vertical part 129. Thus, electrons are released through the top of the floating vertical part 129. [0039] A non-volatile memory device comprising the unit cell may be formed in a cell array on the semiconductor substrate 100. [0040] A method of fabricating the non-volatile memory device will be described herein with reference to FIGS. 6a to 12 b. FIGS. 6b, 7 b, 8 b, 9 b, 10 b, 11 b, and 12 b are cross-sectional views taken along a line II-II′ of the FIGS. 6a, 7 a, 8 a, 9 a, 10 a, 11 a, and 12 a, respectively. [0041] Referring to FIGS. 6a-6 b, a device isolation layer 101 is formed in a predetermined region of a semiconductor substrate 100. The device isolation layer 101 defines a plurality of first active regions 102 arranged in parallel, and a second active region 103 crossing the first active regions 102. The 5 device isolating layer 101 forms a trench isolating layer. A separation insulating layer 105 and a hard mask layer 107 are sequentially formed on the semiconductor substrate 100 with the device isolating layer 101. The separation insulating layer 105 is preferably formed of silicon oxide. The separation insulating layer 105 may be formed of at least one of a chemical vapor deposition (CVD) silicon oxide layer and a thermal oxide layer. The hard mask layer 107 is preferably formed of an insulating layer having an etch selectivity to the separation insulating layer 105, for example, a silicon nitride layer. [0042] Referring to FIGS. 7a, 7 b, 8 a, and 8 b, the hard mask layer 107 and the separation insulating layer 105 are successively patterned to form a pair of preliminary support patterns 109 crossing over the first active regions 102 on both sides of the second active region 103. The preliminary support pattern 109 is comprises a preliminary separation insulating pattern 105 a and a hard mask pattern 107 a that are sequentially stacked. A plurality of photoresist patterns 111 are formed over a semiconductor substrate 100 with the preliminary support pattern 109. The photoresist patterns 111 cover the device isolating layer 101 and the preliminary support patterns 109 thereon. An isotropic etching, such as a wet etching, is applied to a semiconductor substrate 100 with the photoresist patterns 111, thereby forming support patterns 109 a defining under cut regions 113 at lower portions of the both sidewalls. The support pattern 109 a comprises a separation insulating pattern 105 b and a hard mask pattern 107 a that are sequentially stacked. Through the isotropic etching, the preliminary separation insulating pattern 105 a is etched at both sidewalls thereof, thereby forming the separation insulating pattern 105 b having a width W2 that is shorter than a width W1 of the hard mask pattern 107 a. The hard mask pattern 107 a has a lower etch selectivity to the isotropic etch than the preliminary separation insulating pattern 105 a, so that the preliminary separation insulating pattern 105 a is etched faster than the hard mask pattern 107 a. The preliminary separation insulating pattern 105 a on the device isolating layer 101 comprises a region that is not etched by the isotropic etching. That is, the support pattern 109 a on the device isolating layer 101 does not have the under cut regions 113. Accordingly, the under cut regions 113 are surrounded by a bottom of the hard mask pattern 107 a, both sidewalls of the separation insulating pattern 105 b, and the first active region 102. [0043] After forming the support pattern 109 a, the photoresist pattern 111 is removed. [0044] As the photoresist pattern 111 may be omitted. Under cut regions (not shown) may be formed at a lower sidewall of the support pattern 109 a on the device isolating layer 101. [0045] Referring to FIGS. 9a, 9 b, 10 a, and 10 b, a tunnel insulating layer 115 is formed on the first active region 102 of the semiconductor substrate 100. The tunnel insulating layer 115 is formed on a surface of the first active region 102 inside the under cut region 113. The tunnel insulating layer 115 is preferably formed of a thermal oxide layer. A first gate conductive layer 117 is formed on an entire surface of the semiconductor substrate 100 with the tunnel insulating layer 115. The first gate conductive layer 117 fills the under cut regions 113. The first gate conductive layer 117 is preferably formed of a conductive material having desirable step coverage, for example, doped polysilicon. [0046] The first gate conductive layer 117 is anisotropically etched until a portion of the tunnel insulating layer 115 is exposed. The etched first gate conductive layer 117 forms a selection gate electrodes 125 on a sidewall of the support patterns 109 a and 109 b, and preliminary floating gate electrodes 130 on the sidewalls of the support patterns 109 a and 109 b opposite the selection gate electrodes 125, respectively. The preliminary floating gate electrodes 130 are formed over the first active region 102 and between the support patterns 109 a and 109 b and the second active region 103, respectively. Each selection gate electrode 125 comprises a selection-vertical part 123 and a selection-protruding part 124. The selection-vertical part 123 is formed on one sidewall of the support patterns 109 a and 109 b and the selection-protruding part 124 is formed inside the under cut region 113. The shape of the selection-vertical part 123 is substantially similar to a spacer. [0047] Each selection gate electrode 125 comprises the selection-vertical part 123, which is shaped like a spacer through the anisotropic etching. Thus, the selection gate electrodes 125 may be formed to have substantially similar channel widths. Thus, when the selection gate electrodes 125 are formed, a conventional photoresist pattern is not needed. By eliminating the misalignment associated with the use of a photoresist pattern, substantially uniform channel widths can be formed. [0048] Except for the tunnel insulating layer 115 between the first active region 102 and each of the selection gate electrodes 125 and the preliminary floating gate electrodes 130, the exposed tunnel insulating layer 115 may be removed. [0049] Referring to FIGS. 7a, 10 a, 10 b, 11 a, and 11 b, the preliminary floating gate electrode 130 is patterned to form a floating gate electrode 130 a on the first active region 102. The preliminary floating gate electrode 130 on the device isolating layer 101 is etched until the device isolating layer 101 is exposed, thereby isolating the floating gate electrodes 130 a. Each floating gate electrode 130 a comprises a floating-vertical part 129 disposed on a sidewall of the support patterns 109 a and 109 b opposite the selection gate electrodes 125, and a floating-protruding part 128 inside the under cut region 113. The shape of the floating gate electrodes 130 a is substantially similar to a spacer. [0050] If the photoresist pattern 111 of FIG. 7a is omitted, a predetermined region of the hard mask pattern 107 a and the preliminary floating gate electrode 130, which are stacked on the device isolating layer 101, are successively patterned to form a floating gate electrode 130 a on the first active region 102. Considering a planar view, a sidewall of the hard mask pattern 107 a coupled to the floating gate electrode 130 a may be shaped like a dentation. The protruding part of the sidewall of the hard mask pattern 107 a is located over the first active region 102. [0051] After forming the floating gate electrode 130 a, preferably, the hard mask pattern 107 a is recessed using an anisotropic etching process, thereby forming a recessed hard mask pattern 107 b. However, the recessed hard make pattern 107 b may be etched to expose the selection-protruding part 124 and the floating-protruding part 129. [0052] A conformal erasing gate insulating layer 135 is formed on the surface of the semiconductor substrate 100 with the recessed hard mask pattern 107 b. The erasing gate insulating layer 135 may be formed of silicon nitride. A second gate conductive layer 137 is formed on the erasing gate insulating layer 135. The second gate conductive layer 137 may be formed of doped poly silicon. [0053] Referring to FIGS. 12a and 12 b, the second gate conductive layer 137 is patterned to form an erasing gate electrode 137 a crossing over the first active region 102 on an upper portion of the floating gate electrode 130 a. The erasing gate electrode 137 a is parallel to the selection gate electrode 125 and comprises a lower groove 139 surrounding a top of the floating-vertical part 129. The erasing gate insulating layer 135 may be exposed except for a portion between the erasing gate electrode 137 a and the floating gate electrode 130 a. The exposed portion of the erasing gate insulating layer 135 may be removed. [0054] Using the erasing gate electrode 137 a, the selection gate electrode 125, recessed support pattern 107 b and the floating gate electrode 130 a as an mask, impurity ions are implanted into the semiconductor substrate 100 to form impurity diffusion layers 141 a and 141 b. The impurity diffusion layer 141 a of the second active region 103 between the erasing gate electrodes 137 a corresponds to a common source region. The impurity diffusion layer 141 b of the first active region 102 adjacent to the selection gate electrode 125 corresponds to a drain region. [0055] An interlayer dielectric 143 is formed on the surface of the semiconductor substrate 100 with the impurity diffusion layers 141 a and 141 b. The interlayer dielectric 143 may be formed of silicon oxide and can be planarized. A bit line plug 145 is formed through the interlayer dielectric 143 to electrically connect to the drain region 141 b. A bit line 147 is formed to electrically connected to a top surface of the bit line plug 145. The bit line 147 crosses over the selection gate electrode 125. The bit line plug 145 is formed of a conductive layer, for example, a doped poly silicon layer or a metal layer. The bit line 147 may be formed of metal. [0056] According to the present invention, a selection gate electrode is formed in the shape of a spacer on a sidewall of a support pattern. In this case, a photoresist pattern may not be needed for the selection gate electrode. Thus, variations in a channel length of the selection gate electrode due to a misalignment of the photoresist pattern can be avoided. Therefore, property differences between unit cells resulting from the variation of the channel length can be reduced. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5422504 *May 2, 1994Jun 6, 1995Motorola Inc.EEPROM memory device having a sidewall spacer floating gate electrode and processUS5494838 *May 23, 1995Feb 27, 1996Motorola, Inc.Process of making EEPROM memory device having a sidewall spacer floating gate electrodeUS5943267 *Jun 12, 1998Aug 24, 1999Altera CorporationHigh-density nonvolatile memory cellUS6621115 *Nov 6, 2001Sep 16, 2003Integrated Memory Technologies, Inc.Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7381343Jul 8, 2005Jun 3, 2008International Business Machines CorporationHard mask structure for patterning of materialsUS8320191Mar 14, 2008Nov 27, 2012Infineon Technologies AgMemory cell arrangement, method for controlling a memory cell, memory array and electronic deviceUS9030877Oct 11, 2012May 12, 2015Infineon Technologies AgMemory cell arrangement, method for controlling a memory cell, memory array and electronic deviceUS20070020934 *Jul 8, 2005Jan 25, 2007International Business Machines CorporationHard mask structure for patterning of materials* Cited by examinerClassifications U.S. Classification257/315, 257/E27.103, 257/E21.682International ClassificationH01L29/423, H01L29/792, H01L21/8247, H01L27/115, H01L29/788Cooperative ClassificationH01L29/42328, H01L27/11521, H01L27/115European ClassificationH01L27/115, H01L29/423D2B2B, H01L27/115F4Legal EventsDateCodeEventDescriptionJun 10, 2003ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOI, YONG-SUK;LEE, OG-HYUN;REEL/FRAME:014165/0618;SIGNING DATES FROM 20030515 TO 20030519Jul 8, 2008FPAYFee paymentYear of fee payment: 4Jun 26, 2012FPAYFee paymentYear of fee payment: 8Sep 2, 2016REMIMaintenance fee reminder mailedRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services