Source: http://www.google.com.hk/patents/US7292576
Timestamp: 2013-06-20 03:05:47
Document Index: 258551541

Matched Legal Cases: ['Application No. 10', 'Application No. 10', 'Application No. 10', 'art 1', 'art 1', 'art 1', 'art 3', 'art 62', 'art 64', 'art 60', 'art 62', 'art 64', 'art 62', 'art 62', 'art 1']

�M�Q US7292576 - ATM switch having output buffers - Google �M�Q�j�M �Ϥ� �a�� Play YouTube �s�D Gmail ���ݵw�� ��h »�i���M�Q�j�M | �������� | �n�J�i���M�Q�j�M�M�QAn ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input...http://www.google.com.hk/patents/US7292576?utm_source=gb-gplus-share�M�Q US7292576 - ATM switch having output buffers���}��US7292576 B2�X���������v�ӽЮѽs��10/972,175�o�G���2007�~11��6���ӽФ��2004�~10��22�� �u���v���1998�~8��21����L���}�M�Q��CA2280580A1, CA2280580C, EP0982970A2, EP0982970A3, EP0982970B1, US7136391, US7339935, US7474664, US20050053067, US20050053096, US20050083939���}��10972175, 972175, US 7292576 B2, US 7292576B2, US-B2-7292576, US7292576 B2, US7292576B2�o��HSeisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka��M�Q�v�HNippon Telegraph And Telephone Corporation�M�Q�ޥ� (25), �D�M�Q�ޥ� (14), �Q�H�U�M�Q�ޥ� (1), ���� (16) �~���s��: ���M�Q�ӼЧ�, ���M�Q�ӼЧ��M�Q����T��, �ڬw�M�Q��ATM switch having output buffersUS 7292576 B2�K�n An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
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RELATED/PRIORITY APPLICATION INFORMATION This application claims the benefit and priority of and is a division of U.S. patent application Ser. No. 09/376,904, filed Aug. 18, 1999, now U.S. Pat. No. 7,136,391 which claims foreign priority benefits under 35 U.S.C. �� 119 of Japanese Patent Application No. 10-235957, filed Aug. 21, 1998; Japanese Patent Application No. 10-266802, filed Sep. 21, 1998 and Japanese Patent Application No. 10-266930, filed Sep. 21, 1998, all of which are incorporated herein by reference.
A conventional multi stage switch will be described with reference to FIG. 1. FIG. 1 is a block diagram showing the conventional multi stage ATM switch. The first stage has n n��m switches, the second stage has m n��n switches, and the third stage has n m��n switches. Conventionally, it has been known that a cross architecture in which three stages of basic switches are connected is effective for expanding the switch size.
Further, the above-mentioned cell sequence ensuring method has a disadvantage as mentioned below. FIG. 6 shows load dependence of a cell transfer delay distribution. In FIG. 6, the horizontal axis shows the delay time, and the vertical axis shows probability of the cell frequency corresponding to the delay time. As shown in the figure, as the load in the ATM switch increases, the distribution shifts to the direction of increasing delay time. The figure shows that a cell which is transferred with an infinite delay time exists in a finite probability. However, it is physically impossible to provide a sorter with an infinite window size, resulting in carrying out the cell sequence sorting by a sorter with a finite window size in consideration of economy. Thus, the window size �GT, which defines a sorting range of the sorter, is determined probabilistically, giving up cell resequencing for cells with delay below a probability. Therefore, the sorter in the sorting part carries out cell resequencing with the window size �GT.
Moreover, another method for preventing the cell sequence disorder is proposed in M. Collivignarelli et al., ��System and Performance Design of the ATM Node UT-XC,�� IEEE ISS'94, pp. 613-618, in which maximum delay time is added.
Moreover, it is a problem to accommodate a large number of input/output lines in such a high-speed ATM switch. FIG. 7 shows an example of an ATM switch of a 16��16 switch size. For example, when realizing the ATM switch which has the 16��16 switch size and 160-Gbit/s switching throughput (the highway speed is 10-Gbit/s which is 622 Mbit/s��20) and the number of high-speed input/output lines of an LSI chip for the ATM switch is limited to 300 pins at the maximum, an LSI chip of a 4��2 ((4+2)��2��20=240, with 50 control lines) can be realized when inputting high speed signal in parallel to the ATM switch. Therefor, 32 chips are necessary in order to realize a 160-G bit/s cross-point switch.
FIG. 8 shows an LSI chip configuration when transferring cells by splitting cells spatially. As shown in FIG. 8, when cells are split spatially by using a bit slicing technique, 160G/3 throughput can be realized by one chip (16��2��(20/3)≈230, with 50 control lines). Therefore, a 160-G bits/s throughput can be realized with 3 chips at the minimum. In addition, hardware logic in the chip is used effectively since high speed lines for interconnecting between chips can be eliminated.
a second comparing part which compares bit information of the short cells which are output from the switches, the short cells having a delay time of t�ӣn, �n being an acceptable fluctuation time.
FIG. 7 shows an example of an implementation of a 16��16 ATM switch;
FIG. 34 shows an example of an implementation of a 256��256 ATM switch which is configured by 4 switches which include interconnected 16��16 basic switches;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the general outline of a first embodiment of the present invention for cell resequencing in an ATM switch will be described. FIG. 11 shows a block diagram of the ATM switch according to the first embodiment of the present invention. As shown in FIG. 11, the ATM switch includes m basic switches ISW#1-ISW#m at a first stage, m basic switches TSW#1-TSW#m at a second stage and m basic switches OSW#1-OSW#m at a third stage, each of the basic switches having m input lines and m output lines and each of the basic switches of a stage being connected to basic switches of a next stage, thereby forming an m��m input and m��m output ATM switch.
Next, a switching process of a cell input to the ATM switch will be described in chronological order. First, the cell which is input to the ATM switch is input to one of the cell splitting parts SA1-SA4. The cell splitting part splits the input cell spatially, generating short cells which can be sent with a low number of parallel signals for transmission. FIG. 25 shows an example of a cell format of 64-byte length on the assumption that the cells are transmitted in parallel on 16 highways. FIG. 26 shows an example of the short cell. In this example, as shown in the FIGS. 25 and 26, a cell of 16 bits��32 words is split into a short cell of 8 bits��32 words.
Each of the cell splitting parts SA1-SA4 distributes the short cells to the switches P1 and P2 when splitting a cell. For this purpose, routing bits RB�� and RB″ for distribution are added cyclically in the cell splitting parts SA1-SA4. The information of the routing bit RB is written with RB�� and RB″, the routing bit RB being used for switching within the switch.
FIG. 27 shows a case in which each of input cells are split and the split short cells are distributed to basic switches of the second stage in each of the two switches P1 and P2. FIG. 28 shows a periodic table for allocating the second stage. In this example, the cell splitting part SA1 adds routing bits to the short cells cyclically in the order of S1��S2��S3��S4 at the times of T1-T4.
In addition the cell splitting part SA2 cyclically adds routing bits of S2��S3��S4��S1, the cell splitting part SA3 adds routing bits of S3��S4��S1��S2 and the cell splitting part SA4 adds routing bits of S4��S1��S2��S3. Therefore, the cell traffic can be distributed between the switches P1 and P2 such that the basic switches of the second switch have the same load performance. Thus, two split short cells are switched in the two switches P1 and P2 in the same manner and the same cell transfer delay is added to the short cells before the short cells arrive at the outputs. Another cell distribution method will be described later.
FIG. 29 shows a block diagram of the cell splitting part of the embodiment. In the cell splitting part, an input cell is input through an input interface 5 for phase adjustment and sent to a short cell splitting part 1. The short cell splitting part 1 adds the routing bits RB�� and RB″ for cell distribution with reference to the intra-switch routing bit RB, the routing bits RB�� and RB″ being used for identifying which basic switch the short cell enters. At the same time, the time stamp T is added for identifying the cell sequence of the input short cell.
After that, the short cells are stored in the output buffers 21 and 22, and output to the switches P1 and P2 after adjusting the phase of the short cells. Information on the time stamp and the routing bits RB��, RB″ is supplied to the cell splitting part 1 from a control part 3. A counter 4 is provided for synchronization with other cell splitting parts.
FIG. 34 shows an example of a 256��256 ATM switch which is configured by 4 switches which include interconnected 16��16 basic switches. The ATM switch switches 4 split short cells. It can be recognized from the example that the switch scale can be expanded by a simple configuration.
FIG. 44 shows a modification of the third embodiment of the present invention. As shown in the figure, the ATM switch has a delay time inferring part 62 instead of the counter 50 0-50 N-1 and a comparing part 64 instead of the comparing part 60. The delay time inferring part 62 obtains an inferred delay time t of the switches 40 0-40 N-1 and the comparing part 64 compares bit information of short cells output from the switches 40 0-40 N-1 within a delay time t�ӣn. In addition, the delay time inferring part 62 compares between an input time of a timing cell which is a specific cell input to the switches and an output time of the timing cell output from the switches so as to obtain the inferred delay time t. In addition, the delay time inferring part 62 sends the timing cell periodically.
If the value CTL0 and the value CTL1 are the same (CTL0��CTL1) in step 2, the source bits of the split short cells are compared in step 3. When the source bits are the same between the short cells (step 4), the short cells are assembled into an original cell in step 5 because the short cells are originated from a cell.
If the arriving time of the short cell is earlier than the inferred time by exceeding the acceptable fluctuation time �n in step 31 or in step 32, the short cell is determined as an abnormal short cell in step 33. If the arriving time of the short cells is earlier than the inferred time within the acceptable fluctuation time �n and if the routing bits of the short cells are the same in step 34, TAT(t=i+1)=TAT(t=i)+T (t and i represent time) in step 35.
FIG. 46 shows a mechanism for accepting the short cell fluctuation. In the mechanism, �n represents the fluctuation time which can be compensated for and the short cells which arrive within TAT�ӣn are candidates to be assembled.
FIGS. 47A-47D represents the relation between the minimum arriving time T of the short cell, the fluctuation time �n to be compensated for and the inferred arriving time TAT of the short cell in steps 24, 27, 31, 32.
FIG. 53 is a block diagram for explaining a concept of the cell distribution. As shown in the figure, a configuration which has n n��n basic switches forming a multi stage switch is taken as an example.
In order to carry out the cell distribution to avoid blocking in the switch, a scheduling algorithm in consideration of destinations of all n��n input cells is necessary. However, such a scheduling algorithm may have problem of scalability for a large-scale switch. Therefore, the fifth embodiment of the present invention proposes to provide a cell distribution algorithm in each of the n input switches dispersively. Accordingly, since the cell distribution can be carried out in an n��n basic switch, the scalability can be obtained and a large scale switch can be realized.
(k 1 L+k 2 L+ . . . +k n L)/n=L/n(��k 1 +k 2 + . . . +k=1).
As shown in FIG. 55, the maximum L is n��1.0. Therefore, the maximum load distributed to each link is smaller than or equal to 1.0. Thus, load concentration to any output link in the switch can be prevented so as to realize a non-blocking switch.
As shown in FIG. 56, when a cell arrives at the ATM switch in step 1, the cell distribution part determines a destination group of the switch in step 2. Here, the destination group represents an output basic switch of the third stage. Therefore, there are the same number of groups as that of the basic switches of the third stage. For example, there are N groups in a three-stage ATM switch using N N��N basic switches in a stage. For example; cells for output ports 1-N are grouped into group 1, cells for output ports N+1-2N are grouped into group 2, . . . , cells for output ports N2�XN−N2 are grouped into group N. FIG. 56 shows a cell for the output port 2 which is grouped into group 1.
The cell distribution history table provides route information by the group. In the example of the table shown in FIG. 58, each of the values in a group represents the number of cells to be sent through a corresponding route in a period of time. In addition, the table provides �GF which represents difference between the maximum value and the minimum value in R1-Rn. If the value �GF is large, it represents that the cell traffic is not equalized between routes. Therefore, the cell transfer route is determined such that the value AF becomes minimum in each group in step 4.
In the following, the method for determining the cell transfer route will be described concretely. As mentioned above, the group is determined for arriving cells. Next, routes for cells to be transferred are determined starting from the cell which is grouped in a group having the largest �GF. For example, in FIG. 58, since �GF=2 in the group 1 (G1) is the largest value, the route of the cell included in G1 is determined first. Then, a route which has the minimum value among R1−Rn is determined to be the cell transfer route. For example, in FIG. 58, since R2 is 0, which is minimum, the route 2 is selected. By repeating the operation, the routes are-determined. In the process, if there are a plurality of group destinations, all destinations of different groups are determined first. Then, a cell is transferred by using a route with a minimum value among routes which have not been selected.
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