Source: https://patents.google.com/patent/US9891936B2/en
Timestamp: 2018-12-18 19:53:26
Document Index: 209051883

Matched Legal Cases: ['Application No. 2010', 'Application No. 201180062500', 'Application No. 201180062500', 'Application No. 10', 'application No. 2010', 'Application No. 2013', 'Application No. 10', 'Application No. 100145350', 'Application No. 200980139244', 'Application No. 2011', 'Application No. 2011', 'Application No. 101147868', 'Application No. 2010', 'Application No. 201010609068', 'Application No. 201180062500', 'Application No. 101147868', 'Application No. 2011', 'Application No. 2011', 'Application No. 2013', 'Application No. 2013', 'Application No. 10', 'Application No. 200980139244', 'Application No. 200980139244', 'Application No. 2011', 'Application No. 101135588', 'Application No. 101135588', 'Application No. 201010609068', 'Application No. 201180062500', 'Application No. 20101060968', 'Application No. 100145350', 'Application No. 201010609068', 'Application No. 201180062500']

US9891936B2 - Method and apparatus for page-level monitoring - Google Patents
Method and apparatus for page-level monitoring Download PDF
US9891936B2
US9891936B2 US14039195 US201314039195A US9891936B2 US 9891936 B2 US9891936 B2 US 9891936B2 US 14039195 US14039195 US 14039195 US 201314039195 A US201314039195 A US 201314039195A US 9891936 B2 US9891936 B2 US 9891936B2
US14039195
US20150095590A1 (en )
Jiwei Oliver Lu
James D. Beany
Palaniverlrajan Shanmugavelayutham
An apparatus and method for page level monitoring are described. For example, one embodiment of a method for monitoring memory pages comprises storing information related to each of a plurality of memory pages including an address identifying a location for a monitor variable for each of the plurality of memory pages in a data structure directly accessible only by a software layer operating at or above a first privilege level; detecting virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure; responsively updating the monitor variable to reflect the consistency changes or page modifications; checking a first monitor variable associated with a first memory page prior to execution of first program code; and refraining from executing the first program code if the first monitor variable indicates consistency changes or page modifications to the first memory page.
This invention relates generally to the field of computer processors and software. More particularly, the invention relates to an apparatus and method for page level monitoring.
In current binary translation implementations, the binary translation software is loaded from persistent storage such as the platform flash read only memory (ROM) into a predefined area in the system random access memory (RAM). The dynamically translated binary code is then stored in a part of the remaining system RAM, called the “Translation Cache.” The rest of the remaining memory is available for native software (e.g., x86) including the basic input output system (BIOS), operating system (OS) and applications.
Current hardware/software co-designed binary translation platforms enable dynamic binary optimizations through hidden binary translation (BT) software. Such software delivers increased performance in a power efficient fashion and also enables new instruction set architecture (ISA) extensions transparent to the OS and applications. One of the challenges of current binary translation systems is the detection of translation consistency violations occurring due to the following causes:
(1) the virtual page, where the original instruction stream resides, has been remapped to a different physical page which has different instruction stream contents;
(2) the original instruction stream has been modified by the current processor (e.g., via Self-Modifying Code) or remote processors (e.g., via Cross Modifying Code); and
(3) direct memory access (DMA) devices modify the original instruction streams.
Addressing the above issues often results in investing a very complex, dedicated, and expensive processor as well as new ISA extensions. While it is possible for new processor architectures to take such an aggressive step, it may be difficult or impractical for existing matured micro-architectures to do the same.
FIG. 1A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments;
FIG. 1B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments;
FIG. 2 is a block diagram of a single core processor and a multicore processor with integrated memory controller and graphics according to embodiments;
FIG. 7 illustrates a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments;
FIG. 8 illustrates one embodiment of an architecture which includes a page consistency look-aside buffer (PCLB);
FIG. 9 illustrates one embodiment of a PCLB;
FIGS. 10-13 illustrate different methods for updating a PCLB; and
FIG. 14 illustrates updating and using monitor variables in accordance with one embodiment.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described below. It will be apparent, however, to one skilled in the art that the embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments.
FIG. 1A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments. FIG. 1B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments. The solid lined boxes in FIGS. 1A-B illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.
FIG. 2 is a block diagram of a processor 200 that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments. The solid lined boxes in FIG. 2 illustrate a processor 200 with a single core 202A, a system agent 210, a set of one or more bus controller units 216, while the optional addition of the dashed lined boxes illustrates an alternative processor 200 with multiple cores 202A-N, a set of one or more integrated memory controller unit(s) 214 in the system agent unit 210, and special purpose logic 208.
Referring now to FIG. 4, shown is a block diagram of a first more specific exemplary system 400 in accordance with an embodiment of the present invention. As shown in FIG. 4, multiprocessor system 400 is a point-to-point interconnect system, and includes a first processor 470 and a second processor 480 coupled via a point-to-point interconnect 450. Each of processors 470 and 480 may be some version of the processor 200. In one embodiment, processors 470 and 480 are respectively processors 310 and 315, while coprocessor 438 is coprocessor 345. In another embodiment, processors 470 and 480 are respectively processor 310 coprocessor 345.
FIG. 7 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. FIG. 7 shows a program in a high level language 702 may be compiled using an x86 compiler 704 to generate x86 binary code 706 that may be natively executed by a processor with at least one x86 instruction set core 716. The processor with at least one x86 instruction set core 716 represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler 704 represents a compiler that is operable to generate x86 binary code 706 (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core 716. Similarly, FIG. 7 shows the program in the high level language 702 may be compiled using an alternative instruction set compiler 708 to generate alternative instruction set binary code 710 that may be natively executed by a processor without at least one x86 instruction set core 714 (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif. and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.). The instruction converter 712 is used to convert the x86 binary code 706 into code that may be natively executed by the processor without an x86 instruction set core 714. This converted code is not likely to be the same as the alternative instruction set binary code 710 because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter 712 represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 706.
Method and Apparatus for Page Level Monitoring
One embodiment provides a hardware/software co-designed mechanism to detect any change to a memory page and/or to the virtual-physical page mapping. This implementation is beneficial to binary translation systems and is particularly beneficial to a partial translation model. In a partial translation model, guest native execution is mixed with translated code execution. As a result, changes to memory are harder to follow and track as the changes can happen from both native execution and translated execution.
The emergence of multiple processor computing makes the above issues even more challenging. Current systems have yet to solve the multi-processor issues in dealing with the translation consistency violations since multi-processors introduce sophisticated asynchronous occurrences of translation consistency violations by remote processors and DMA devices.
The embodiments described below address the problems mentioned above with an innovative monitor variable concept that may be built with existing hardware units with an extended microcode layer. These embodiments allow binary translated code to check and detect translation consistency violations during runtime using a low-overhead signaling mechanism and solving multi-processor scalability issues.
In particular, one embodiment uses a hardware/software co-designed approach to allow any layer of software to be informed of and to proactively query about a specific page state change such as a virtual-to-physical page mapping consistency, modification of the page, etc., with low cost and no impact to the principle of least privilege employed in layered software design. To enable such low overhead notification mechanisms to software running at lower privilege upon the state change of concerned pages, a signaling mechanism based upon a memory update to a specific memory location, referred to as a “Monitor Variable,” is provided. A processor structure called a Page Consistency Look-aside Buffer (PCLB), which provides this page-state-change monitoring mechanism, is also provided.
One embodiment may be employed within a hardware/software co-designed binary translation system to allow lower privileged translated code to query and be notified upon a virtual-to-physical mapping change and self/cross-modifying code occurrences at very low cost. To exhibit the same privilege faulting behaviors and preserve the security isolation of the original code, a translated version of the original code (translated code) needs to be executed at the same privilege as the original code. This notification mechanism should have no impact to the privilege escalation concern as it does not expose any privileged information (such as physical memory address of the requested page, etc) other than informing that such a requested page state change has occurred.
While some embodiments are used in a binary translation system, it should be noted that the underlying principles are applicable to many other uses such as security computing. For example, anti-malware and anti-rootkit software would benefit with the ability to track memory page and page mapping consistency so that malicious writes to unauthorized memory areas can trigger alerts at the earliest possible stage. In general, the embodiments provide ways for the higher privileged trusted security service layer to notify the lower privileged security agent of the requested state change of the given memory location or to allow the lower privilege security agent to query about the memory state change with low overhead.
FIG. 8 illustrates one embodiment of a co-designed hardware and software binary translation system which includes a page consistency look-aside buffer (PCLB) 850 to perform page level monitoring. The system memory 860 includes a native code memory space 800, a translation cache space 810 and binary translation code space 820. The native code memory 800 is the memory space allocated for native software such as the BIOS software, operating system and applications. In one embodiment, the native software comprises x86 program code. However, the underlying principles are not limited to any particular instruction set architecture.
The binary translation code 820 includes a translator component 821 that transforms a subsection 802 of a native executable binary 801 of the native code memory 800 into translated code 811. In one embodiment, the subsection 802 comprises the entire execution binary 801. In one embodiment, the translated code 811 is stored in a translation cache 810, which may be implemented as a dedicated memory space for the translated code 811. In one embodiment, when the translated code 811 executes, it may use a scratch space 812 to store temporary values.
A runtime component 822 (another sub-module of the binary translation code 820) provides runtime services and manages memory allocation and de-allocation for the translation cache 810. The system layer 823 is another sub-module of the binary translation code 820 that handles system-related events such as interrupts, exceptions and dispatches job requests to the rest of the binary translation modules. The interpreter 824 is an optional module employed in one embodiment in the binary translation code 820 that provides direct emulation of the original binary.
In one embodiment, hardware extensions 831 and/or microcode 832 are implemented on the processor 830 to provide hardware support for the various functions described herein. For example, in one embodiment, the hardware extensions 831 and/or microcode 832 execute operations related to the PCLB monitoring and updating techniques and/or the binary translation functions described herein.
Although FIG. 8 shows one translation cache 810 and one processor 830 and one piece of translated code 811, it should be noted that the underlying principles are not so limited. For example, the translation cache 810 can contain several pieces of translated code 811, possibly from different binaries 801. Similarly, it is possible to have several translation caches 810 per processor 830 (e.g., one translation cache 810 per hardware thread). Other embodiments of the invention may be implemented across several processors.
Additionally, different embodiments of the invention may have different configurations of the system RAM 860 and the placement of the translation cache 810 and binary translation code 820. For example, a portion of the system RAM 860 may be embedded inside the processor as embedded DRAM (EDRAM) and a portion of the EDRAM memory storage may be allocated for the translation cache 810 and the binary translation code 820. In some configuration, the scratch space 812 may also be implemented as processor local storage.
In one embodiment, the binary translation software 820 runs in a separate execution container environment from the other software layers including the virtual machine monitor (VMM), operating system and applications. As mentioned above, its job is to translate and generate an optimized version 811 of the original code 802. To exhibit the same privilege faulting behaviors and preserve the security isolation of the original code 802, the translated code 811 needs to be executed with identical modes/privileges as the original code.
In one embodiment, the page consistency look-aside buffer (PCLB) 850 includes a table that is managed by the processor 830 and/or the firmware layer. It is designed to monitor and detect a change in the page consistency for a given list of pages, including virtual-to-physical mappings and page modifications by the processor or DMA devices. In one embodiment, the PCLB 850 exposes an instruction set architecture or firmware interfaces to the binary translation software 820 which uses those interfaces to insert and delete entries to enable/disable page consistency monitoring for concerned pages.
One embodiment includes self modifying code (SMC) protection hardware which enables write-protection to code pages against self-modifying and cross-modifying conditions. This can be built with a dedicated hardware or by utilizing existing resources within the processor 830 such as the existing memory management unit (MMU) including the TLB and IOTLB. To ensure that the translated versions of the original code are valid and not stale, the binary translation system needs to monitor and detect at least two types of page consistency issues: (i) virtual to physical mapping; and (2) self, cross and OMA modifying code conditions. If such a consistency loss occurs, the binary translation software 820 may invalidate the affected translated code 811 and re-translate the original code 802 if necessary. In order for binary translation software to enable page consistency monitoring, the processor 830 or firmware-managed PCLB 850 and insertion/removal/flush interfaces are provided (the details of which are provided below).
As illustrated in FIG. 9, the PCLB table has multiple entries and each entry has multiple fields. The definitions of each field of the PCLB are as follows:
Valid—If set to 1, the entry is currently valid for page consistency monitoring.
V2P (virtual-to-physical) Monitor—If set to 1, virtual-to-physical mapping consistency check is enabled for the current context.
Write Monitor—If set to 1, the SMC/XMC (self modifying code/cross modifying code) monitor is enabled for the given physical page. This can be accomplished by write-protecting the target physical page by the SMC Protection hardware.
Virtual Page Number, Physical Page Number—Virtual Page Number and Physical Page Number fields are used for the PCLB to track virtual-to-physical mapping consistency. Physical page number refers to host physical address when the extended page table (EPT) is enabled. Physical Page Number is also used to enable write-monitoring for the physical address specified with this Physical Page Number field.
Context ID—As virtual-to-physical memory mapping is context (process) specific, Context ID is used to enable virtual-to-physical mapping consistency monitoring only when the given Context ID is currently active. Typical context IDs used by modern operating systems are, for instance, the CR3 register on x86 architecture, or the page table pointer register on a RISC architecture, etc.
Monitor Variable Address—Consists of the memory location in the format of the physical address of the associated Monitor Variable. The processor uses this address to write appropriate values to the monitor variable. A value “TRUE” indicates that the state of the mapping is unchanged. When the page state consistency is lost, a “FALSE” value will be written to the specified Monitor Variable.
ISA Extensions for PCLB Management
The ISA extensions or the firmware interfaces to manage the PCLB for INSERT, REMOVE and FLUSH operations may be provided to the binary translation software 820. As previously discussed, the processor may include hardware support for these operations with hardware extensions 831 and/or microcode (uCode) 832. There may be different implementations of the PCLB table 850. For instance, the PCLB 850 may be implemented with a dedicated hardware for monitoring both virtual-to-physical mapping consistency and SMC/XMC detection. In another instance, the PCLB features may be implemented through extended microcode or firmware by utilizing the existing processor MMU/IOMMU units such as the TLB for substituting SMC Protection Hardware to detect SMC/XMC conditions. In another embodiment, the PCLB functionality may be implemented by the VMM software layer when binary translation software 820 is part of the VMM managed software components.
Structurally, the PCLB 850 could be built as a direct-mapped table, N-way associative or fully associative table. The number of PCLB entries may be determined based on variables such as the size of the binary translation cache 810, the performance requirements of the system, and the capacity limitation of the structure itself. Overall, the PCLB implementation depends on the specific processor and firmware implementation which determines what and how the interfaces are exposed to the binary translation software 820 via the ISA extension.
Enabling Page Consistency Monitoring
As virtual to physical mapping needs to be tracked on a context (e.g., process) basis, each PCLB entry has a Context ID field. By way of example, and not limitation, in Intel 64 and IA-32 processors, the Context ID value can be created from the CR3 (control register 3) and EPT (extended page table) root values. The Virtual Page Number and Physical Page Number fields are used to track the virtual-to-physical mapping consistency for the given Context ID.
FIG. 10 illustrates one embodiment of an insertion operation for inserting a new entry into the insertion of a new Context ID for a current context into the PCLB 850. At 1001, a determination is made as to whether virtual-to-physical mapping consistency check is enabled for the current context. If not, then an error is generated at 1003 and the process terminates.
If so, then at 1002, a determination is made as to whether a virtual-to-physical mapping is present in the translation lookaside buffer (TLB) and page tables of the processor for the current context. If not, then an error code is generated at 1003. If so, then at 1004, a new PCLB entry is added for the current context (identified via CR3) using the virtual address, physical address, and monitor variable address (MV_ADDR) which, as discussed above comprises the physical address of the associated Monitor Variable. The processor uses this address to write a value of “TRUE” indicating that the state of the mapping is unchanged (or, in this case, new).
If the self-modifying code (SMC) monitor value is set to 1, determined at 1005, then write monitoring is enabled on the physical address for the current context at 1006. If the SMC monitor value is set to 0, then the process terminates.
In one embodiment, in order for the PCLB to track virtual-to-physical mapping consistency per context (process address space), the address space switch operation by the operating system such as the MOV to CR3 operation is intercepted and the method illustrated in FIG. 11 is employed to re-validate the PCLB entries with the new context's address space.
A new context is moved to CR3 at 1101. At 1102, the process begins with the first PCLB entry slot. If the context ID of the slot identifies the old context (i.e., the context just prior to the move to the new context), determined at 1103, then at 1106, a FALSE value is written to the monitor variable address indicating that the state of the mapping has changed. The next PCLB entry slot is selected at 1109 and if the current slot is not the final slot (determined at 1110), then the process returns to 1103.
If the context ID of the slot does not identify the old context at 1103, then at 1104, a determination is made as to whether the context ID identifies the new context (i.e., the context moved into CR3). If not, then the next PCLB entry slot is selected at 1109 and if the current slot is not the final slot (determined at 1110), then the process returns to 1103. If the context ID identifies the new context, and if the virtual-to-physical mapping for the context is present in the TLB and/or page tables, determined at 1107, then at 1108 a TRUE value is written to the monitor variable address indicating that the current state of the mapping is unchanged. In any case, the process returns to the next slot at 1109 and repeats if the slot is not the last slot, determined at 1110. In order to support the memory virtualization scenario, the same flow above may be invoked whenever the EPT root is switched.
Thus, to re-validate the PCLB entries upon context switch, the PCLB needs to scan the entries, compare the CTXT field with the new Context and re-validate virtual-to-physical mapping by checking the TLB or the page table structures of the new context and setting a TRUE or FALSE value to the Monitor Variable memory location depending on the result of each validation. Notification of virtual to physical mapping loss by a context switch will be communicated to binary translation software by writing a FALSE value to the Monitor Variable memory location specified by PCLB Monitor Variable Address field. The PCLB entries that have the matching context value to the new CTXT_ID are revived again if the same virtual-to-physical mapping is found in the TLS or the page table structures for the new context's address space. When reviving a PCLB entry, the Monitor Variable memory location specified by the PCLB Monitor Variable Address field is written with a TRUE value.
Removal and Invalidation of PCLB Entries
To allow the PCLB to detect the loss of virtual-to-physical mapping upon OS and VMM page remapping operation, the PCLB needs to implement the following process for the TLB entry flush operation. An exemplary PCLB flow for an invalidate (INVLPG) instruction is shown in FIG. 12. At 1201, the INVLPG instruction is initiated using a particular virtual address. The process starts with the first PCLB slot entry at 1202. If the context ID of the PCLB entry is equal to the current context, determined at 1203, then at 1204, a determination is made as to whether the virtual-to-physical monitor field is set to 1. If so, then at 1207 the virtual address of the PCLB entry is compared to the virtual address associated with the INVLPG instruction. If there is a match, then at 1208 the virtual-to-physical monitor field is set to 0 and a value of FALSE is written to the monitor variable address. At 1205, the next PCLB slot entry is selected and, if the final one, determined at 1206, the process terminates. If not the final one, then the process returns to 1203.
Thus, the matching PCLB entries having the same Virtual Page Number are invalidated. When a matching occurs, a loss of the virtual-to-physical consistency is notified by writing a FALSE value to the memory location specified by the PCLB Monitor Variable Address field. The PCLB entry removal operation by binary translation software can be done with the same PCLB flow as the INVLPG case since the Virtual Page Number can also be used for the PCLB removal operation to select which PCLB entry to remove.
In one embodiment, the FLUSH operation, which invalidates the entire PCLB, can be implemented by unconditionally invalidating all the PCLB entries and updating each Monitor Variable memory location of the invalidated PCLB entry with a FALSE value.
When the SMC monitoring is enabled, the SMC protection hardware enables write-protection for the target physical page. In one embodiment, when a write occurs to the SMC-protected page, the processor is notified and the process illustrated in FIG. 13 is implemented for the PCLB to detect and signal the occurrence of SMC/XMC condition by writing a FALSE value to the Monitor Variable of the affected PCLB entry. At 1301 at SMC monitor hit condition is detected and at 1302, the first PCLB entry slot is selected. If the virtual-to-physical monitor field is set to 1, then at 1306, the write monitor field is set to 0 and a value of FALSE is written to the monitor variable address. The next PCLB entry slot is selected at 1304 and, if not the last entry slot (determined at 1305), the process loops back to 1303.
When two separate threads have the same virtual-to-physical mapping and run on separate processors, two separate PCLB entries need to be allocated in order for each thread to individually track and monitor the validity of the virtual-to-physical mapping for its own context on each separate processor. In order to support these multi-processor scenarios, the PCLB table may be allocated per logical processor. For example, a logical processor ID may be added to the PCLB entry if the PCLB is built as a global shared resource.
However, this creates interesting issues related to thread migration. Suppose that a thread is monitoring the page consistency for the virtual address 0x5000 with the Monitor Variable A. When this thread migrates to another processor, the location of the Monitor-Variable referred by this thread needs to change for the aforementioned reason. The problem is that it may not be easy for the software itself such as the application thread to know and use a different Monitored Variable location depending upon which logical processor it is currently running on. One solution is to use an address aliasing technique to map the Monitor Variable to a different physical page on each logical processor but with the same virtual address. This technique allows the program that accesses the Monitor Variable to freely migrate from one processor to another without changing the address of the Monitor Variable to track the page consistency state of the particular page.
Monitor Variable Memory Software Management and Usages
As illustrated generally in FIG. 14, for each virtual to physical page mapping for which software needs to track consistency, one monitor variable 1401, a unique memory address location which is accessible from the low-privilege software component 1403 (a consumer of Monitor Variable), may be allocated by the trusted higher-privileged software layer 1402. For the hardware/software co-designed binary translation system, the allocation of the monitor variables 1401 may be done by the binary translation software 1405 (e.g., allocated from concealed memory transparent to the OS). The consumer of the monitor variable, which runs at a lower privilege, is the translated version of the original code (illustrated as Translation 1-4 in FIG. 14) which runs at the same privilege as the original version of the binaries. When the translated version of the original code is generated, the binary translation software is responsible for: (1) enabling the page consistency monitoring for the original code page through PCLB 850; (2) allocating the memory space for the Monitor Variables 1401; (3) making the Monitor Variables 1401 accessible from the translated version of original code.
In the case of page mapping being changed, the OS either issues the INVLPG instruction to invalidate the corresponding TLS entry (this usually happens when single page is remapped) or to change the page table base pointer (e.g., the value of CR3 register on the x86 architecture). In either case, the processor should be able to detect the change and search the entire PCLB table to invalidate impacted entries. Similarly, the processor is able to detect SMC/XMC conditions with help from the SMC/XMC Protection Hardware and search the PCLB lookup table 850 to invalidate impacted entries. As illustrated, the correlated Monitor Variables 1401 are written with FALSE values to indicate the change.
As the translated version of the binary (e.g., Translation 1-4) has embedded code to check the value of the Monitor Variable 1401 prior to executing the translation from the code page which the Monitor Variable corresponds to, the execution of the translated code will stop by itself if the value is read FALSE (i.e. the target page has been affected). Notification of the page consistency loss events is done through simply updating the monitor variable 1401 allocated for the given page that is to be monitored. By checking the monitor variable with simply a memory compare operation, the translated code is able to know whether a change has happened or not. This is a low cost solution as no new instruction extensions are needed to monitor the loss of the page consistency from the translated code.
As said, the details of PCLB structure and the detailed field entry information are not visible to the translated code itself. The translated code does not even need to know what physical address this virtual address is mapped to. From the functional requirement standpoint, the translated code simply needs to know if the consistency is lost for this translation prior to executing the translation and if so it needs to stop executing it. This is exactly provided by monitor variables and the PCLB mechanism. Thus, monitor variables and the PCLB mechanism can enable the least privileged principle of the layered software design and improve the security of the BT Software system.
Though this Binary Translation usage of this invention monitors only virtual-to-physical mapping change and SMC/XMC detection, the PCLB table structure and its concept can be extended to monitor not only write but also read and execution activities to the pages. In particular, this type of extensions may be useful for the potential security usages of this invention. Though the current design prefers using a single monitor variable for reflecting the change in any page consistency, it is also possible to extend the PCLB entry field to allocate separate monitor variable fields for each reflecting the different type of page consistency violations such as virtual-to-physical mapping consistency and write detections. The number of monitor variable required is up to how many monitor sources the software system is in need. The guideline here is, for each page to be monitored in the software execution entity, at least one dedicated monitor variable must be allocated to activate consistency monitoring via the PCLB.
In one embodiment, the PCLB table does not have to be large enough to retain all the old entries. Due to the capacity limitation, the PCLB table may not be able to hold all the requests coming from the software side. In the case when PCLB tab le reaches its size limit, the new coming requests can only be fulfilled after PCLB control logic removes some of the old entries from the table. The detailed replacement policy is flexible for different implementation hence is not covered by this disclosure. But no matter what kind of implementation is in place, it is crucial for the processor to invalidate the value of the associated monitor variable of the replaced PCLB entry. Simply speaking, false alarm may happen to any page, but they can be correctable by the software by re-enabling protection via PCLB.
In summary, monitor variables and the PCLB offer an inexpensive hardware/software codesigned approach to replace current hardware-only solutions. It does not require exposing the host physical address of the given virtual address to the translated code, even if the execution is in the translated code rendered by the binary translation software. This significantly reduces the security risk of the translated code as it lowers the privileges exposed to the translated code. A variance of these PCLB techniques can also be used to define the application level ISA extensions to help application level BT to enable SMC detection.
Embodiments may include various steps, which have been described above. The steps may be embodied in machine-executable instructions which may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.
As described herein, instructions may refer to specific configurations of hardware such as application specific integrated circuits (ASICs) configured to perform certain operations or having a predetermined functionality or software instructions stored in memory embodied in a non-transitory computer readable medium. Thus, the techniques shown in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals—such as carrier waves, infrared signals, digital signals, etc.). In addition, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input/output devices (e.g., a keyboard, a touchscreen, and/or a display), and network connections. The coupling of the set of processors and other components is typically through one or more busses and bridges (also termed as bus controllers). The storage device and signals carrying the network traffic respectively represent one or more machine-readable storage media and machine-readable communication media. Thus, the storage device of a given electronic device typically stores code and/or data for execution on the set of one or more processors of that electronic device. Of course, one or more parts of an embodiment may be implemented using different combinations of software, firmware, and/or hardware. Throughout this detailed description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that may be practiced without some of these specific details. In certain instances, well known structures and functions were not described in elaborate detail in order to avoid obscuring the subject matter of the present invention. Accordingly, the scope and spirit of the invention should be judged in terms of the claims which follow.
1. A method for monitoring memory pages comprising:
storing, in a data structure for each of a plurality of memory pages, information including a context identifier and an address identifying a monitor variable location, the data structure being directly accessible only by a software layer operating above a privilege level being operated by a program code;
detecting virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure;
responsively performing monitor variable update to reflect the virtual-to-physical page mapping consistency changes or page modifications based on context identifier match;
prior to execution of the program code, checking a monitor variable, location of which is identified by the data structure, the monitor variable being associated with a memory page; and
refraining from executing the program code if the monitor variable indicates consistency changes or page modifications to the memory page.
2. The method as in claim 1 wherein if the monitor variable does not indicate consistency changes or page modifications, then executing the program code.
3. The method as in claim 1 wherein the program code comprises translated binary code.
4. The method as in claim 1 wherein the data structure comprises a table with a separate row for each memory page.
5. The method as in claim 4 wherein a value of the monitor variable comprises a Boolean data type with a FALSE value indicating consistency changes or page modifications.
determining whether a virtual to physical mapping is present in a translation lookaside buffer and/or a page table for a current context; and
adding a new entry for a new memory page in the data structure only if a virtual to physical mapping is present in the translation lookaside buffer and/or the page table for the current context.
re-validating entries for memory pages in the data structure within a new context's address space responsive to an address space switch operation.
invalidating one or more entries in the data structure in response to a flush of a corresponding entry in a translation lookaside buffer (TLB).
9. The method as in claim 8 wherein invalidating comprises identifying the one or more entries using a virtual address associated with the flush.
first logic to store, in a data structure for each of a plurality of memory pages, information including a context identifier and an address identifying a monitor variable location, the data structure being accessible only by a software layer operating at or above a privilege level being operated by a program code;
second logic to detect virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure;
third logic to responsively perform monitor variable update to reflect the virtual-to-physical page mapping consistency changes or page modifications based on context identifier match; and
fourth logic to:
prior to execution of the program code, check a monitor variable, location of which is identified by the data structure, the monitor variable being associated with a memory page, and
refrain from executing the program code if the monitor variable indicates consistency changes or page modifications to the memory page.
11. The processor as in claim 10 wherein if the monitor variable does not indicate consistency changes or page modifications, then executing the program code.
12. The processor as in claim 10 wherein the program code comprises translated binary code.
13. The processor as in claim 10 wherein the data structure comprises a table with a separate row for each memory page.
14. The processor as in claim 13 wherein a value of the monitor variable comprises a Boolean data type with a FALSE value indicating consistency changes or page modifications.
15. The processor as in claim 10 further comprising:
fifth logic to add a new entry for a new memory page in the data structure only if a virtual to physical mapping is present in a translation lookaside buffer (TLB) and/or a page table for a current context.
16. The processor as in claim 10 further comprising:
fifth logic to re-validate entries for memory pages in the data structure within a new context's address space responsive to an address space switch operation.
17. The processor as in claim 10 further comprising:
fifth logic to invalidate one or more entries in the data structure in response to a flush of a corresponding entry in a translation lookaside buffer (TLB).
18. The processor as in claim 17 wherein invalidating comprises identifying the one or more entries using a virtual address associated with the flush.
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