Source: http://www.google.com/patents/US6177328?dq=7,546,338
Timestamp: 2016-09-30 18:04:44
Document Index: 645654057

Matched Legal Cases: ['application No. 07', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08']

Patent US6177328 - Methods of forming capacitors methods of forming DRAM cells, and integrated ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsSemiconductor capacitor constructions, DREAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are encompassed by the invention. The invention includes...http://www.google.com/patents/US6177328?utm_source=gb-gplus-sharePatent US6177328 - Methods of forming capacitors methods of forming DRAM cells, and integrated circuits incorporating structures and DRAM cell structuresAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6177328 B1Publication typeGrantApplication numberUS 09/189,706Publication dateJan 23, 2001Filing dateNov 10, 1998Priority dateFeb 11, 1997Fee statusLapsedAlso published asUS5905280, US6175129, US6316312, US20010000493Publication number09189706, 189706, US 6177328 B1, US 6177328B1, US-B1-6177328, US6177328 B1, US6177328B1InventorsYauh-Ching Liu, David Y. KaoOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (28), Non-Patent Citations (13), Referenced by (9), Classifications (21), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetMethods of forming capacitors methods of forming DRAM cells, and integrated circuits incorporating structures and DRAM cell structures
US 6177328 B1Abstract
Semiconductor capacitor constructions, DREAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are encompassed by the invention. The invention includes a method comprising: a) forming an opening within an insulative layer and over a node location; b) forming a spacer within the opening to narrow the opening, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening; c) removing a- portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; d) forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; and e) forming a dielectric layer and a cell plate layer operatively proximate the storage node layer. The invention also includes a construction comprising: a) an opening extending through an insulative layer to a node location; b) a conductive spacer within the opening and narrowing at least a portion of the opening; the conductive spacer having inner and outer surfaces; c) a storage node layer in connecting with the node location and extending along both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; and d) a dielectric layer and a cell plate layer operatively proximate the storage node.
forming an opening within an insulative layer and over a node location; forming a spacer within the opening, the spacer having inner and outer surfaces and narrowing the opening, the spacer having a bottom surface above the node location; removing a portion of the insulative layer from proximate the spacer outer surface to expose at least a portion of the spacer outer surface; forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; forming a dielectric layer operatively proximate the storage node layer; and forming a cell plate layer operatively proximate the dielectric layer. 2. The method of claim 1 wherein the spacer comprises a conductive material.
3. The method of claim 1 wherein the step of forming the storage node layer comprises forming the storage node layer in substantial contact with the node location, spacer inner surface, and exposed spacer outer surface.
forming an opening within an insulative layer and over and above a node location; forming a conductive spacer within the opening to narrow the opening, the conductive spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening; removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; forming a storage node layer in electrical connection with the node location, extending along the conductive spacer inner surface, and extending along the exposed conductive spacer outer surface; the storage node layer and conductive spacer together forming a capacitor storage node; forming a dielectric layer operatively proximate the storage node layer; and forming a cell plate layer operatively proximate the dielectric layer. 5. The method of claim 4 wherein the step of forming the storage node layer comprises forming the storage node layer in substantial contact with the node location, conductive spacer inner surface, and exposed conductive spacer outer surface.
6. The method of claim 4 wherein the step of removing a portion of the insulative layer from proximate the outer surface of the conductive spacer comprises exposing the entire outer surface of the conductive spacer.
7. The method of claim 4 wherein the step of removing a portion of the insulative layer from proximate the outer surface of the conductive spacer comprises exposing only a portion of the outer surface of the conductive spacer.
8. The method of claim 4 wherein the step of removing a portion of the insulative layer from proximate the outer surface of the conductive spacer comprises exposing the entire outer surface of the conductive spacer and undercutting the conductive spacer.
9. The method of claim 4 wherein the storage node layer comprises hemispherical grain polysilicon.
10. The method of claim 4 wherein the conductive spacer comprises polysilicon doped with a conductivity enhancing dopant.
forming an insulative layer over a node location; forming an opening within the insulative layer and over the node location, the opening having a base positioned above the node location; forming a conductive spacer within the opening to narrow the opening, the conductive spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening, the outer surface being against the insulative layer; extending the narrowed opening to the node location; removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; forming a storage node layer within the extended opening, in electrical connection with the node location, in substantial contact with as the conductive spacer inner surface, and in substantial contact with the conductive spacer outer surface; the storage node layer and the conductive spacer together forming a capacitor storage node; forming a dielectric layer operatively proximate the storage node layer; and forming a cell plate layer operatively proximate the dielectric layer. 12. The method of claim 11 wherein the steps of extending the narrowed opening and removing a portion of the insulative layer from proximate the outer surface comprise a common etch step.
13. The method of claim 11 wherein the step of removing a portion of the insulative layer from proximate the outer surface of the conductive spacer comprises exposing the entire outer surface of the conductive spacer.
14. The method of claim 11 wherein the step of removing a conductive spacer comprises exposing only a portion of the outer surface of the conductive spacer.
15. The method of claim 11 wherein the step of removing a portion of the insulative layer from proximate the outer surface of the conductive spacer comprises exposing the entire outer surface of the conductive spacer and undercutting the conductive spacer.
16. The method of claim 11 wherein the conductive spacer comprises polysilicon doped with a conductivity enhancing dopant.
forming an insulative layer over a node location; forming a first opening within the insulative layer over the node location, the first opening having a base positioned above the node location; forming a conductive spacer layer within the opening; anisotropically etching the conductive spacer layer to form a second opening extending to the first opening base, the second opening being narrower than the first opening, the conductive spacer having inner and outer surfaces, the inner surface forming a periphery of the second opening and the outer surface being against the insulative layer; extending the second opening to the node location; removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; forming a storage node layer within the extended opening, in substantial contact with the node location, in substantial contact with the conductive spacer inner surface, and in substantial contact with the conductive spacer outer surface; the storage node layer and conductive spacer together forming a capacitor storage node; forming a dielectric layer operatively proximate the storage node layer; and forming a cell plate layer operatively proximate the dielectric layer. 18. The method of claim 17 wherein the steps of extending the narrowed opening and removing a portion of the insulative layer to expose at least a portion of the outer surface comprise a common etch step.
19. A method of forming a capacitor comprising the following steps:
forming a diffusion region within a semiconductor wafer substrate; forming an insulative layer over the semiconductor wafer substrate; forming an opening within the insulative layer above the diffusion region; forming a conductive spacer within the opening to narrow at least a portion of the opening; the conductive spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed portion of the opening; removing a portion of the insulative layer to expose at least a portion of the outer surface of the conductive spacer; forming a storage node layer in electrical connection with the diffusion region and extending along and in electrical connection with the inner surface of the conductive spacer, and the exposed portion of the outer surface of the conductive spacer; the storage node layer and conductive spacer together forming a capacitor storage node; forming a dielectric layer operatively proximate the storage node layer; and forming a cell plate layer operatively proximate the dielectric layer. 20. The method of claim 19 wherein the step of removing a portion of the insulative layer from proximate the outer surface of the conductive spacer comprises exposing the entire outer surface of the conductive spacer.
21. The method of claim 19 wherein the step of removing a portion of the insulative layer from proximate the outer surface of the conductive spacer comprises exposing the entire outer surface of the conductive spacer and undercutting the conductive spacer.
22. A method of forming a capacitor comprising the following steps:
forming a diffusion region within a semiconductor wafer substrate; forming an insulative layer over the semiconductor wafer substrate; forming an opening within the insulative layer, the opening being formed to a minimum-most photolithographic feature dimension used in the method, the opening having a base positioned over the diffusion region and positioned above the diffusion region; forming a conductive spacer layer within the opening; anisotropically etching the conductive spacer layer to form a conductive spacer within the opening, the conductive spacer having inner and outer surfaces, the conductive spacer narrowing the opening to a cross-sectional dimension which is less than the minimum-most photolithographic feature dimension, the inner surface of the conductive spacer forming a periphery of the narrowed opening; removing a portion of the insulative layer to extend the narrowed opening to the diffusion region, expose the entire outer surface of the is conductive spacer, and undercut the conductive spacer to form a cavity beneath the conductive spacer; forming a storage node layer in physical contact with the diffusion region and extending along and in electrical connection with the inner surface of the conductive spacer, along and in electrical connection with the exposed outer surface of the conductive spacer, and within the cavity beneath the conductive spacer; the storage node layer and conductive spacer together forming a capacitor storage node; forming a dielectric layer operatively proximate the storage node layer; and forming a cell plate layer operatively proximate the dielectric layer. 23. A method of forming a DRAM cell comprising the following steps:
forming a transistor gate over a semiconductor substrate; forming first and second diffusion regions within the semiconductor wafer substrate operatively proximate the transistor gate; forming an insulative layer over the semiconductor wafer substrate; forming an opening within the insulative layer over the first diffusion region; forming a spacer within the opening to narrow at least a portion of the opening; the spacer having inner and outer surfaces; the inner surface forming a periphery of the narrowed portion of the opening; removing a portion of the insulative layer to expose at least a portion of the outer surface of the spacer and to extend the narrowed opening to the first gated diffusion region; forming a storage node layer in electrical connection with the first diffusion region and extending along and in electrical connection with the inner surface of the spacer and the exposed portion of the outer surface of the spacer; the storage node layer and spacer together forming a capacitor storage node; forming a dielectric layer operatively proximate the storage node; forming a cell plate layer operatively proximate the dielectric layer; the dielectric layer, cell plate layer and storage node together comprising a capacitor; forming a bitline in electrical connection with the second diffusion region, the bitline being electrically coupled to the capacitor through the transistor gate to form a DRAM cell. 24. A method of forming a monolithic integrated circuit comprising the following steps:
fabricating integrated circuitry over a portion of a semiconductor substrate, the integrated circuitry comprising transistors, capacitors and resistive elements; the fabrication of at least one of the capacitors comprising the following steps: forming an opening within an insulative layer and over a node location; forming a spacer within the opening, the spacer having inner and outer surfaces and narrowing the opening, the spacer having a bottom surface above the node location; removing a portion of the insulative layer from proximate the spacer outer surface to expose at least a portion of the spacer outer surface; forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; forming a dielectric layer operatively proximate the storage node layer; and forming a cell plate layer operatively proximate the dielectric layer. 25. The method of claim 24 wherein the integrated circuit is fabricated as part of a microprocessor circuit.
26. The method of claim 24 wherein the integrated circuit is fabricated as part of a microprocessor circuit and wherein the at least one capacitor is incorporated into a DRAM cell.
This patent resulted from a divisional application of U.S. patent application Ser. No. 08/798,241, which was filed on Feb. 11, 1997, now U.S. Pat. No. 5,905,280.
A DRAM is a commonly used semiconductor device comprising a capacitor and a transistor. A continuous challenge in the semiconductor industry is to decrease the vertical and/or horizontal size of semiconductor devices, such as DRAMs and capacitors. A limitation on the minimal horizontal footprint of capacitor constructions is impacted by the resolution of a photolithographic etch during fabrication of the capacitor constructions. Although this resolution is generally improving, at any given time there is a minimum photolithographic feature dimension of which a fabrication process is capable. It would be desirable to) form capacitors at least some portions of which have a cross-sectional minimum dimension of less than the minimum capable photolithographic feature dimension of a given fabrication process.
A field oxide region 14, and a gate dielectric layer 16 are formed over substrate 12. Preferably, field oxide region 14 and gate dielectric 14 layer 16 comprise silicon dioxide.
It is noted that the relative exposure of surface 38 can be controlled by a number of methods known to persons of ordinary skill in the art. Generally, the amount of insulative layer 28 removed will be the amount necessary to extend opening 34 to node location 24. Accordingly, by controlling the relative ratio of the depth “X” of first opening 30 to the distance “Y” from base 31 of opening 30 to node location 24, the amount of surface 38 exposed can be controlled. For instance, if “X” is relatively large compared to “Y”, only a portion of surface 38 of spacer 36 will be exposed in the time necessary to extend opening 34 from base 31 (shown in FIGS. 3-5) to node location 24 (an example embodiment of capacitor construction in which only a portion of surface 38 is exposed is shown in FIG. 9). In contrast, if “X” is relatively small compared to −Y, the entire surface 38 will be exposed in the time necessary to extend opening 34 from base 31 to node location 24.
Referring to FIG. 7, a storage node layer 46 is provided over insulative layer 28 and spacers 36, and is provided within opening 34. is Storage node layer 46 thus is provided in electrical contact with diffusion region 24 and extends along and in electrical connection with inner surface 40 of spacer 36, and outer surface 38 of spacer 36. In the preferred embodiment in which spacer 36 comprises conductive material, spacer 36 and storage node layer 46 ultimately together comprise a capacitor storage node 52. (Capacitor storage node 52 is shown in FIG. 8.)
Wafer fragment 10 a comprises a field oxide region 14 a, a gate dielectric region 16 a, word lines 18 a and 20 a, and node locations 22 a and 24 a, analogous to similar structures described above with reference to FIG. 1. Wafer fragment 10 a further comprises a capacitor structure 60 a which includes a storage node 52 a, a dielectric layer 54 a and a cell plate layer 56 a. Capacitor construction 60 a differs from capacitor construction 60 of the previous embodiment (shown in FIG. 8) primarily in that only part of outer surface 38 a of spacer 36 a is covered by storage node layer 46 a, while the entire outer surface 38 of spacer 36 is covered by storage node layer 46 in capacitor construction 60.
Example methods for forming the partially covered outer surface 38 a of capacitor 60 a were mentioned above with reference to FIG. 6. Specifically, such partially covered outer surface 38 a could be formed by appropriate adjustment of the ratio of “X” (shown in FIG. 3) “Y” (shown in FIG. 3).
Capacitor construction 60 a may be described by the language utilized above in describing capacitor construction 60 (shown in FIG. 8), or may be described alternatively. For instance, wafer fragment 10 a may be described as follows. Wafer fragment 10 a comprises a node 24 a within a substrate 12 a, and an insulative layer 28 a over substrate 12 a. A contact opening 70 extends through insulative layer 28 a to node location 24 a. Contact opening 70 comprises a wider as upper portion 72 and a narrower lower portion 74. A conductive spacer 36 a is within wider upper portion 72. Conductive spacer 36 a comprises inner and outer surfaces 40 a and 38 a, respectively, and a bottom surface 42 a. In the shown preferred embodiment, bottom surface 42 a is above node location 24 a. Spacer 36 a narrows upper portion 72 of contact opening 70, with inner surface 40 a forming a periphery of the narrowed contact opening upper portion. A conductive storage node layer 46 a is in electrical contact with node location 24 a and extends along both inner surface 40 a and outer surface 38 a of spacer 36 a. Storage node layer 46 a and spacer 36 a together form a capacitor storage node 52 a. A dielectric layer 54 a and a cell plate layer 56 a are operatively proximate storage node 52 a. The various layers and structures of wafer 10 a will preferably comprise the same preferable construction as discussed above for wafer fragment 10 with reference to FIGS. 1-8. For instance, spacer 36 a will preferably comprise a conductive material, and will most preferably comprise polysilicon-doped with a conductivity enhancing dopant. Also preferably, node location 24 a will comprise a diffusion region within semiconductor substrate 12 a. Semiconductor substrate 12 a will most preferably comprise a silicon wafer.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4845537Dec 1, 1987Jul 4, 1989Mitsubishi Denki Kabushiki KaishaVertical type MOS transistor and method of formation thereofUS4864374Nov 30, 1987Sep 5, 1989Texas Instruments IncorporatedTwo-transistor dram cell with high alpha particle immunityUS5170233Jun 27, 1991Dec 8, 1992Micron Technology, Inc.Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitorUS5206183Feb 19, 1992Apr 27, 1993Micron Technology, Inc.Method of forming a bit line over capacitor array of memory cellsUS5227325Apr 2, 1992Jul 13, 1993Micron Technology, InclMethod of forming a capacitorUS5229310May 26, 1992Jul 20, 1993Motorola, Inc.Method for making a self-aligned vertical thin-film transistor in a semiconductor deviceUS5229326Jun 23, 1992Jul 20, 1993Micron Technology, Inc.Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor deviceUS5244826Apr 16, 1992Sep 14, 1993Micron Technology, Inc.Method of forming an array of finned memory cell capacitors on a semiconductor substrateUS5270968Jun 30, 1992Dec 14, 1993Samsung Electronics Co., Ltd.Thin-film transistor for semiconductor memory device and fabricating method thereofUS5283455Jul 10, 1992Feb 1, 1994Mitsubishi Denki Kabushiki KaishaThin film field effect element having an LDD structureUS5323038Jun 22, 1993Jun 21, 1994Micron Technology, Inc.Array of finned memory cell capacitors on a semiconductor substrateUS5334862Aug 10, 1993Aug 2, 1994Micron Semiconductor, Inc.Thin film transistor (TFT) loads formed in recessed plugsUS5338700Apr 14, 1993Aug 16, 1994Micron Semiconductor, Inc.Method of forming a bit line over capacitor array of memory cellsUS5385858Jul 23, 1993Jan 31, 1995Nec CorporationMethod for fabricating semiconductor device having memory cell of stacked capacitor typeUS5391511 *Jan 5, 1993Feb 21, 1995Micron Technology, Inc.Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitorUS5401681Jul 20, 1994Mar 28, 1995Micron Technology, Inc.Method of forming a bit line over capacitor array of memory cellsUS5438011Mar 3, 1995Aug 1, 1995Micron Technology, Inc.Method of forming a capacitor using a photoresist contact sidewall having standing wave ripplesUS5444013Nov 2, 1994Aug 22, 1995Micron Technology, Inc.Method of forming a capacitorUS5498562Apr 29, 1994Mar 12, 1996Micron Technology, Inc.Semiconductor processing methods of forming stacked capacitorsUS5563089Feb 22, 1995Oct 8, 1996Micron Technology, Inc.Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cellsUS5604147May 12, 1995Feb 18, 1997Micron Technology, Inc.Method of forming a cylindrical container stacked capacitorUS5605857Feb 22, 1995Feb 25, 1997Micron Technology, Inc.Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cellsUS5608247May 15, 1995Mar 4, 1997Micron Technology Inc.Storage capacitor structures using CVD tin on hemispherical grain siliconUS5612558Nov 15, 1995Mar 18, 1997Micron Technology, Inc.Hemispherical grained silicon on refractory metal nitrideUS5623243May 23, 1995Apr 22, 1997Nec CorporationSemiconductor device having polycrystalline silicon layer with uneven surface defined by hemispherical or mushroom like shape silicon grainUS5661064Nov 13, 1995Aug 26, 1997Micron Technology, Inc.Method of forming a capacitor having container membersUS5786249Mar 7, 1996Jul 28, 1998Micron Technology, Inc.Method of forming dram circuitry on a semiconductor substrateUS5972769 *Dec 18, 1997Oct 26, 1999Texas Instruments IncoporatedSelf-aligned multiple crown storage capacitor and method of formation* Cited by examinerNon-Patent CitationsReference1Aoki, M., et al., "Fully Self-Aligned 6F2 Cell Technology For Low Cost 1Gb DRAM", IEEE, pp. 22-23.2Hayden, J.D., et al., "A New Toroidal TFT Structure For Future Generation SRAMs", IEEE 1993, pp. 825-828, IEDM.3IBM Technical Disclosure Bulletin, "Methods of Forming Small Contact Holes", vol. 30, No. 8 (Jan. 1988), pp. 252-253.4Sakao, M., "Capacitor-Over-Bit-Line (COB) Cell With A Hemisperical-Grain Storage Node For 64Mb DRAMs", 1990 IEEE, pp. 27.3.1-27.3.4.5U.S. application No. 07/869,615, Doan et al. filed Apr. 16, 1992.6U.S. application No. 08/000,891, Doan et al. filed Jan. 5, 1993.7U.S. application No. 08/044,824, Dennison et al., filed Apr. 7, 1993.8U.S. application No. 08/047668, Dennison et al., filed Apr. 14, 1993.9U.S. application No. 08/055,085, Sandhu et al., filed Apr. 29, 1993.10U.S. application No. 08/078,616, Lee et al., filed Jun. 17, 1993.11U.S. application No. 08/163,439, Dennison, filed Dec. 7, 1993.12U.S. application No. 08/582,385, Sandhu et al., filed Jan. 3, 1996.13U.S. application No. 08/622,591, Dennison, filed Mar. 26,1996.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6316312 *Dec 5, 2000Nov 13, 2001Micron Technology, Inc.Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structuresUS6580113 *Jun 28, 1999Jun 17, 2003Mitsubishi Denki Kabushiki KaishaSemiconductor device and manufacturing method thereofUS6730609Oct 9, 2001May 4, 2004Micron Technology, Inc.Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor deviceUS7094699May 3, 2004Aug 22, 2006Micron Technology, Inc.Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor deviceUS7573116Aug 18, 2006Aug 11, 2009Micron Technology, Inc.Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor deviceUS9089794Apr 7, 2010Jul 28, 2015Biotage AbChromatography columnUS20040203240 *May 3, 2004Oct 14, 2004Howard Bradley J.Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor deviceUS20060281319 *Aug 18, 2006Dec 14, 2006Howard Bradley JEtch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor deviceWO2010115923A1Apr 7, 2010Oct 14, 2010Biotage AbChromatography column* Cited by examinerClassifications U.S. Classification438/398, 257/E27.089, 257/E21.59, 257/E21.648, 257/E21.013, 257/E21.012, 257/E21.018, 438/255International ClassificationH01L27/108, H01L21/768, H01L21/8242, H01L21/02Cooperative ClassificationH01L27/10852, H01L28/84, H01L27/10817, H01L28/82, H01L28/90, H01L21/76895European ClassificationH01L27/108M4B2, H01L28/82, H01L27/108F2MLegal EventsDateCodeEventDescriptionJul 3, 2001CCCertificate of correctionJun 16, 2004FPAYFee paymentYear of fee payment: 4Jul 8, 2008FPAYFee paymentYear of fee payment: 8Sep 3, 2012REMIMaintenance fee reminder mailedJan 23, 2013LAPSLapse for failure to pay maintenance feesMar 12, 2013FPExpired due to failure to pay maintenance feeEffective date: 20130123RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services