Source: http://www.google.com/patents/US20080175071?ie=ISO-8859-1
Timestamp: 2015-01-25 14:51:30
Document Index: 538094338

Matched Legal Cases: ['Application No. 2004', 'Application No. 2004', 'Application No. 2001', 'Application No. 2004', 'Application No. 2004', 'Application No. 2001']

Patent US20080175071 - Methods of Operating Memory Systems Including Memory Devices Set to ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may...http://www.google.com/patents/US20080175071?utm_source=gb-gplus-sharePatent US20080175071 - Methods of Operating Memory Systems Including Memory Devices Set to Different Operating ModesAdvanced Patent SearchPublication numberUS20080175071 A1Publication typeApplicationApplication numberUS 12/058,441Publication dateJul 24, 2008Filing dateMar 28, 2008Priority dateJul 20, 2001Also published asUS7369445, US20060161745Publication number058441, 12058441, US 2008/0175071 A1, US 2008/175071 A1, US 20080175071 A1, US 20080175071A1, US 2008175071 A1, US 2008175071A1, US-A1-20080175071, US-A1-2008175071, US2008/0175071A1, US2008/175071A1, US20080175071 A1, US20080175071A1, US2008175071 A1, US2008175071A1InventorsKee-Hoon Lee, Chang-sik Yoo, Kye-Hyun KyungOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManReferenced by (4), Classifications (12) External Links: USPTO, USPTO Assignment, EspacenetMethods of Operating Memory Systems Including Memory Devices Set to Different Operating ModesUS 20080175071 A1Abstract A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.
setting a first memory device of the plurality of memory devices to a first operating mode; setting a second memory device of the plurality of memory devices to a second operating mode different than the first operating mode; setting a third memory device of the plurality of memory devices to a third operating mode different than at least one of the first and/or second operating modes; and performing a read/write operation responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation, so that the second memory device operates according to the second operating mode during the read/write operation, and so that the third memory device operates according to the third operating mode during the read/write operation. 2. A method according to claim 1 wherein setting the first memory device to the first operating mode comprises providing a first mode set command address signal to the plurality of memory devices and providing an identification signal to the first memory device without providing an identification signal to the second and third memory devices.
3. A method according to claim 2 wherein setting the second memory device to the second operating mode comprises providing a second mode set command address signal to the plurality of memory devices and providing an identification signal to the second memory device without providing an identification signal to the first and third memory devices.
8. A method according to claim 1 wherein the third operating mode is different than the first and second operating modes. Description
RELATED APPLICATIONS The present application claims the benefit of priority as a Continuation application of U.S. patent application Ser. No. 11/315,470 filed on Dec. 22, 2005, which claims the benefit of priority as a Continuation-In-Part application of U.S. patent application Ser. No. 10/916,156 filed on Aug. 11, 2004, which claims the benefit of priority as a Continuation-In-Part application of U.S. patent application Ser. No. 10/199,857 filed on Jul. 19, 2002. In addition, U.S. patent application Ser. No. 11/315,470 claims the benefit of priority from Korean Application No. 2004-0112199 filed Dec. 24, 2004; U.S. patent application Ser. No. 10/916,156 claims the benefit of priority from Korean Application No. 2004-0032500 filed May 8, 2004; and U.S. patent application Ser. No. 10/199,857 claims the benefit of priority from Korean Application No. 2001-0043789 filed Jul. 20, 2001. The present application thus claims the benefit of priority from U.S. patent application Ser. No. 11/315,470, U.S. patent application Ser. No. 10/916,156, U.S. patent application Ser. No. 10/199,857, Korean Application No. 2004-0112199, Korean Application No. 2004-0032500, and Korean Application No. 2001-0043789, and the disclosures of all of the above referenced U.S. and Korean Patent Applications are hereby incorporated herein in their entirety by reference.
FIELD OF THE I/WENTION The present invention relates to the field of electronics, and more particularly, to electronic memories and related methods.
Accordingly, the memory devices M1, M5, and M9 may generate first, fifth, and ninth internal clock signals ICLK1, ICLK5, and ICLK9 at different times, respectively. In FIG. 4, the first internal clock signal ICLK1 may be generated earlier than the fifth internal clock signal ICLK5 by a period 4T, and the fifth internal clock signal ICLK5 may be generated earlier than the ninth internal clock signal ICLK9 by a period 4T. When data is written, data DATA received from the outside may be stored in the memory cell array 36 in synchronization with the internal clock signal ICLK1, ICLK5, or ICLK9. Referring to FIG. 4, first internal data IDATA1, fifth internal data IDATA5, and ninth internal data IDATA9 may be generated at different times. That is, the internal data IDATA1, IDATA5, and IDATA9 stored in the memory cell array 36 may have data skew DSK.
Moreover, separate lines for mode register set enable/disable signals ID-11D9 are provided between the memory controller 100 and each of the memory devices 300M1-300M2. For example, separate dedicated lines may be provided between the memory controller and dedicated mode register set enable/disable pins on each of the memory devices. In an alternative, lines used to transmit the data strobe signals DQS1-DQS9 during read/write operations, lines used to transmit data signals DATA1-DATA9 during read/write operations, or lines used to transmit the data mask signals DM1-DM9 during read/write operations may be used to separately transmit the mode register set enable/disable signals ID1-ID9 to each of the memory devices 300M1-300M9 during mode register set operations.
As illustrated in the timing diagrams of FIGS. 8 and 9, the selective mode register set operations discussed above may provide an approximate synchronization of internals clock signals iCLK for different memory devices 300M1-300M9 of the memory module 200 illustrated in FIG. 5. During a read operation illustrated in FIG. 8, transitions of the system clock signal CK are received by different memory devices of the memory module at different times due to different propagation delays along the clock/command/address bus 112. More particularly, a rising edge of the system clock signal may be received at memory device 300M1 before it is received at memory device 300M5 as shown by signals CK1 and CK5, and a rising edge of the system clock signal may be received at memory device 300M5 before it is received at memory device 300M9 as shown by signals CK5 and CK9. Because timings of the internal clock signals of the memory devices have been selectively adjusted using selective mode register set operations, the internal clock signals iCLK1, iCLK5, and iCLK9 may be approximately synchronized. More particularly, a delay of the internal clock signal iCLK1 can be increased relative to the clock signal CK1 received at the first memory device 300M1, a default delay of the internal clock signal iCLK5 can be maintained relative to the clock signal CK5 received at the fifth memory device 300M5, and a delay of the internal clock signal iCLK9 can be reduced relative to the clock signal CK9 received at the memory device 300M9.
The timing diagram of FIG. 14 illustrates selective mode register set operations for each of the memory devices 300M1-300Mn of FIG. 10. In the example of FIG. 14, the mode register set enable/disable signals ID1-IDn are provided over data strobe lines to data strobe pins of the respective memory devices 300M1-300M9 during selective mode register set operations. During read and/or write operations, the data strobe lines and pins are used to provide data strobe signals to the respective memory devices. Because the mode register set enable/disable signals ID1-ID9 are provided over data strobe lines and pins, the mode register set enable/disable signals are labeled DQS1-DQSn in FIG. 14.
During an nth mode register set operation Cn, an nth mode register set command MRSn may be applied over the clock/command/address bus 112, an enabling mode register set enable/disable signal lDn may be applied as DQn to the nth memory device 300Mn, and disabling mode register set enable/disable signals ID1-ID(n−1) may be applied as DQ1-DQ(n−1) to the memory devices 300M1-300M(n−1). Accordingly, the nth mode register set operation Cn may provide delay adjustment for an internal clock signal iCLKn of memory device 300Mn.
Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7957210Aug 21, 2008Jun 7, 2011Fujitsu LimitedVariable delay circuit, memory control circuit, delay amount setting apparatus, delay amount setting method and computer-readable recording medium in which delay amount setting program is recordedUS8631194 *Jan 14, 2011Jan 14, 2014Seiko Epson CorporationDRAM refresh schedule control moduleUS8832391Nov 15, 2010Sep 9, 2014Samsung Electronics Co., Ltd.Semiconductor device, controller associated therewith, system including the same, and methods of operationUS20110197020 *Jan 14, 2011Aug 11, 2011Seiko Epson CorporationElectronic device* Cited by examinerClassifications U.S. Classification365/189.04, 365/230.01International ClassificationG11C8/00, G11C7/10Cooperative ClassificationG06F13/1694, G11C7/1045, G11C7/10, G11C11/4093European ClassificationG11C7/10, G11C7/10M7, G11C11/4093, G06F13/16D9RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services