Source: http://www.google.es/patents/US8847380
Timestamp: 2018-01-21 06:58:43
Document Index: 205479030

Matched Legal Cases: ['Application No. 2009', 'Application No. 2009', 'Application No. 2010', 'Application No. 099140226', 'Application No. 100113585', 'Application No. 100144451', 'Application No. 099143374', 'Application No. 100133520']

Patente US8847380 - Staged via formation from both sides of chip - Google Patentes
A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective...http://www.google.es/patents/US8847380?utm_source=gb-gplus-sharePatente US8847380 - Staged via formation from both sides of chip
Número de publicación US8847380 B2
Número de solicitud US 12/884,649
También publicado como CN103210486A, CN103210486B, EP2617054A2, US9362203, US20120068330, US20150130077, US20160284627, WO2012037216A2, WO2012037216A3
Número de publicación 12884649, 884649, US 8847380 B2, US 8847380B2, US-B2-8847380, US8847380 B2, US8847380B2
Citas de patentes (294), Otras citas (33), Citada por (2), Clasificaciones (41), Eventos legales (3)
US 8847380 B2
providing a semiconductor element having a front surface, a rear surface remote from the front surface, and a plurality of conductive pads, each pad having a top surface exposed at the front surface and having a bottom surface remote from the top surface;
forming a hole extending at least through a respective one of the conductive pads by processing applied to the respective one of the conductive pads from above the front surface;
forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the hole and the opening meet at a location between the front and rear surfaces;
forming a first continuous dielectric layer overlying an interior surface of the semiconductor element within the opening;
forming a second continuous dielectric layer partially overlying the respective conductive pad at least at a location above the respective conductive pad and overlying an interior surface of the semiconductor element within the hole; and
forming a conductive interconnect exposed at the rear surface for electrical connection to an external device, the conductive interconnect extending at least into the opening; and
forming a conductive via exposed at the front surface, the conductive via extending at least within the hole and being electrically connected with and directly coupled to the conductive interconnect and the respective conductive pad,
wherein the step of forming the conductive interconnect is performed before the step of forming the conductive via, such that the conductive via is formed in contact with a surface of the conductive interconnect exposed within the hole, and
wherein the step of forming the hole includes:
exposing a surface of the first continuous dielectric layer within the hole; and
extending the hole through the surface of the first continuous dielectric layer to expose the surface of the conductive interconnect within the hole.
2. A method as claimed in claim 1, wherein the step of forming the conductive interconnect forms a conductive contact coupled to the conductive interconnect, the conductive contact being exposed at the rear surface.
3. A method as claimed in claim 2, wherein the conductive contact overlies the rear surface of the semiconductor element.
4. A method as claimed in claim 2, wherein the opening has a first width in a lateral direction along the rear surface, and the conductive contact has a second width in the lateral direction, the first width being greater than the second width.
5. A method as claimed in claim 2, wherein the conductive contact is aligned in a vertical direction with a portion of the semiconductor element within the opening, the vertical direction being a direction of the thickness of the semiconductor element.
6. A method as claimed in claim 1, wherein the step of forming the hole is performed such that the hole extends partially through the thickness of the semiconductor element.
7. A method as claimed in claim 6, wherein the step of forming the hole is performed such that the hole extends up to one-third of the distance between the front surface and the rear surface through the thickness of the semiconductor element, and the opening extends through a remainder of the thickness of the semiconductor element that is not occupied by the hole.
8. A method as claimed in claim 1, wherein the semiconductor element includes a plurality of active semiconductor devices and at least one of the plurality of conductive pads is electrically connected with at least one of the plurality of active semiconductor devices.
9. A method as claimed in claim 1, wherein one or more of the hole and the opening are formed by directing a jet of fine abrasive particles towards the semiconductor element.
10. A method as claimed in claim 1, wherein the step of forming the hole forms two or more holes, and the step of forming the opening is performed such that the opening extends from the rear surface of the semiconductor element to two or more of the holes.
11. A method as claimed in claim 10, wherein the step of forming the opening is performed such that the opening has a channel shape having a length extending in a first direction along a surface of the semiconductor element, and a width extending a second lateral direction transverse to said first direction, the length being greater than the width.
12. A method as claimed in claim 1, wherein the processing applied to the respective conductive pad from above the front surface is chemical etching, laser drilling, or plasma etching.
13. A method of fabricating a stacked assembly including at least first and second semiconductor assemblies, each semiconductor assembly being fabricated as claimed in claim 1, further comprising the step of electrically connecting the first semiconductor assembly with the second semiconductor assembly.
14. A method as claimed in claim 1, wherein the conductive interconnect is formed by plating a metal layer overlying at least an inner surface of the opening, the conductive interconnect conforming to a contour of the opening.
15. A method as claimed in claim 14, wherein the conductive interconnect extends along a portion of the inner surface of the opening.
16. A method as claimed in claim 15, wherein the step of forming the conductive interconnect is performed so as to form two or more conductive interconnects at least within the opening, each of the two or more conductive interconnects extending to a single one of the conductive pads.
17. A method as claimed in claim 14, wherein the conductive interconnect defines an internal space.
18. A method as claimed in claim 17, further comprising the step of filling the internal space with a dielectric material.
19. A method as claimed in claim 14, wherein the conductive interconnect fills a volume between surfaces of the first continuous dielectric layer.
20. A method as claimed in claim 1, wherein the conductive via is formed by plating a metal layer overlying at least an inner surface of the hole, the conductive via conforming to a contour of the hole.
21. A method as claimed in claim 20, wherein the conductive interconnect defines an internal space.
22. A method as claimed in claim 21, further comprising the step of filling the internal space with a dielectric material.
23. A method as claimed in claim 20, wherein of the conductive via fills a volume between surfaces of the second continuous dielectric layer.
24. A method as claimed in claim 1, wherein the second continuous dielectric layer partially overlies the top surface of the respective conductive pad, and the step of forming the conductive via forms the conductive via in contact with the top surface of the respective conductive pad and overlying the continuous dielectric layer over the top surface of the respective conductive pad and within the hole.
25. A method of fabricating a semiconductor assembly, comprising:
forming a continuous dielectric layer partially overlying the respective conductive pad at least at a location above the respective conductive pad and overlying an interior surface of the semiconductor element within the hole; and
wherein the step of forming the conductive via is performed before the step of forming the conductive interconnect, such that the conductive interconnect is formed in contact with a surface of the conductive via exposed within the opening, and
wherein the step of forming the opening includes:
exposing a surface of the continuous dielectric layer within the opening; and
extending the opening through the surface of the continuous dielectric layer to expose the surface of the conductive via within the opening.
Before the stage of fabrication shown in FIG. 13A, the microelectronic unit 10 g can undergo the same stages of fabrication shown in FIGS. 7A-7G. Thereafter, as illustrated in FIG. 13A, the opening 30 g can be formed extending downwardly from the rear surface 22 g to the hole 40, as described above with reference to FIG. 7E. An etch process can be applied to the portion of the dielectric layer 25 that is exposed within the opening 30 g so as to expose the portion of the conductive via 60 that is aligned with the hole.
Thereafter, as illustrated in FIG. 15F, the opening 30 can be formed extending downwardly from the rear surface 22 to the hole 40, as described above with reference to FIG. 7E. Then, a photoimageable layer such as a photoresist or a dielectric layer 70 can be deposited onto the rear surface 22 of the semiconductor element 20 and in the opening 30, as described above with reference to FIG. 13B.
Thereafter, as illustrated in FIG. 151, an etch process can be applied to the portion of the dielectric layer 70 that overlies the hole 40 and the portion of the dielectric layer 25 that is exposed within the opening 30 so as to expose the portion of the conductive via 60 that is aligned with the hole.
Thereafter, as illustrated in FIG. 23B, a portion of the passivation layer 24 can be removed at a location where it is desired to form the hole 40 k, the location being laterally offset from the conductive pad 50 k.
Thereafter, as illustrated in FIG. 23E, the thickness of the semiconductor element 20 k between the front surface 21 and the rear surface 22 can be reduced as described with reference to FIGS. 7F and 7G. During this step, as an example, the initial thickness T3 (shown in FIG. 23G) of the semiconductor element 20 k can be reduced to a thickness T4 (shown in FIG. 23E).
Thereafter, as illustrated in FIG. 231, the opening 30 k can be formed extending downwardly from the rear surface 22 to the hole 40 k, as described above with reference to FIG. 7E. Then, a photoimageable layer such as a photoresist or a dielectric layer 70 k can be deposited onto the rear surface 22 of the semiconductor element 20 k and in the opening 30 k, as described above with reference to FIG. 13B.
Then, a trace-shaped conductive interconnect 80 k and a trace-shaped conductive contact 90 k can be deposited as a metallic layer onto the dielectric layer 70 k within the opening 30 k (the conductive interconnect) and extending along the rear surface 22 (the conductive contact), respectively, as described above with reference to FIG. 151. The conductive contact 90 k is exposed at the outer surface 72 of the dielectric layer 70 k for interconnection with an external device or with another microelectronic unit 10 k in a stacked assembly. The conductive contact 90 k is laterally offset from the opening 30 k and the hole 40 k, but the conductive contact is vertically aligned with (i.e., overlying) the conductive pad 50 k.
JPH01106949A Título no disponible
JPH04365558A Título no disponible
22 Japanese Office Action for Application No. 2009-552696 dated Aug. 14, 2012.
23 Japanese Office Action for Application No. 2009-552696 dated Nov. 1, 2013.
24 Japanese Office Action for Application No. 2010-519953 dated Oct. 19, 2012.
25 Partial International Search Report for Application No. PCT/US2011/063653 dated Jul. 9, 2012.
26 Partial International Search Report, PCT/US2008/002659.
27 PCT/US08/09207, "Reconstituted Wafer Stack Packaging With After Applied Pad Extensions," filed Jul. 25, 2008.
28 Preliminary Examination Report from Taiwan Application No. 099140226 dated Oct. 21, 2013.
29 Supplementary European Search Report, EP 08795005 dated Jul. 5, 2010.
30 Taiwan Office Action for Application No. 100113585 dated Jun. 5, 2012.
31 Taiwan Office Action for Application No. 100144451 dated Apr. 16, 2014.
32 Taiwanese Office Action for Application No. 099143374 dated Jun. 24, 2013.
33 Taiwanese Office Action for Application No. 100133520 dated Dec. 12, 2013.
US9768067 * 29 Nov 2016 19 Sep 2017 Xintec Inc. Chip package and manufacturing method thereof
US20170076981 * 29 Nov 2016 16 Mar 2017 Xintec Inc. Chip package and manufacturing method thereof
Clasificación de EE.UU. 257/698, 257/777, 438/660, 257/778, 438/667, 438/121, 438/698, 257/621, 438/107, 257/774, 257/686
Clasificación internacional A01C1/00, A01C1/04, H01L21/50, H01L25/065, H01L23/00, H01L25/00, H01L23/48, H01L21/283, H01L21/768
Clasificación cooperativa H01L2924/14, H01L2225/06544, H01L2924/12042, H01L2924/07811, H01L2924/01322, H01L23/50, H01L23/481, H01L21/76898, H01L2225/06513, H01L24/03, H01L2224/0401, H01L25/0657, H01L2224/05009, H01L24/05, H01L2225/06541, H01L2224/73204, H01L2224/32145, H01L2224/06181, H01L2224/16145, H01L25/50, H01L2924/00012
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OGANESIAN, VAGE;HABA, BELGACEM;MOHAMMED, ILYAS;AND OTHERS;REEL/FRAME:025301/0972