Source: https://patents.google.com/patent/US7489545?oq=6%2C128%2C731
Timestamp: 2018-03-20 06:37:16
Document Index: 264471507

Matched Legal Cases: ['art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1']

US7489545B2 - Memory utilizing oxide-nitride nanolaminates - Google Patents
Memory utilizing oxide-nitride nanolaminates
US7489545B2
US7489545B2 US11492749 US49274906A US7489545B2 US 7489545 B2 US7489545 B2 US 7489545B2 US 11492749 US11492749 US 11492749 US 49274906 A US49274906 A US 49274906A US 7489545 B2 US7489545 B2 US 7489545B2
Active, expires 2022-08-12
US11492749
US20060258097A1 (en )
This application is a divisional of U.S. application Ser. No. 10/933,050, filed Sep. 2, 2004, which is a divisional of U.S. application Ser. No. 10/190,689, filed Jul. 8, 2002, both of which are incorporated herein by reference.
The present invention relates generally to semiconductor integrated circuits and, more particularly, to gate structures utilizing oxide-nitride nanolaminates.
V. M. Bermudez et al, “The Growth and Properties of Al and AlN Films on GaN,” J. Appl. Physics, Vol. 79, No. 1, pp. 110-119, 1996;
Benjamin, M. C., et al, “UV Photoemission Study of Heteroepitaxial AlGaN films Grown on 6H—SiC”, IEEE Conference Record, 1996 International Conf. on Plasma Science, Cat. No. 96CH35939, p. 141, 1996; Pankove, J. I., et al, “Photoemission from GaN”, Applied Physics Letters, Vol. 25, No. 1, pp. 53-55, 1974);
Akasaki, I., et al, “Effects of AlN Buffer Layer on Crystallographic Structure and on Electrical and Optical Properties of GaN and Gal-x Alx N Films Grown on Sapphire Substrate by MOVPE”, J. of Crystal Growth, Vol. 98, pp. 209-219, 1989, North Holland, Amsterdam;
M. Moriwaki et al. “Improved Metal Gate Process By Simultaneous Gate-Oxide Nitridation During W/WN/Sub X/Gate Formation,” Jpn. J. Appl. Phys., Vol. 39. No. 4B, pp. 2177-2180, 2000;
Petra Alen et al., “Atomic Layer Deposition of Ta(al)N© Thin Films Using Trimethylaluminum as a Reducing Agent”, Jour, of the Electrochemical Society, 148 (10), G566-G571 (2001);
One of the inventors, along with others, has previously described programmable memory devices and functions based on the reverse stressing of MOSFET's in a conventional CMOS process and technology in order to form programmable address decode and correction in the U.S. Pat. No. 6,521,950 entitled, “MOSFET Technology for Programmable Address Decode and Correction.”. That disclosure, however, did not describe write once read only memory solutions, but rather address decode and correction issues. One of the inventors also describes write once read only memory cells employing charge trapping in gate insulators for conventional MOSFETs and write once read only memory employing floating gates. The same are described in co-pending, commonly assigned U.S. patent applications, entitled “Write Once Read Only Memory Employing Charge Trapping in Insulators,” Ser. No. 10/177,077 and “Write Once Read Only Memory Employing Floating Gates,” Ser. No. 10/177,083. The present application, however, describes transistor cells having oxide-nitride nanolaminate layers and used in integrated circuit device structures.
(i) silicon nitride
(ii) aluminum nitride
(iii) gallium nitride
(iv) gallium aluminum nitride
(v) tantalum aluminum nitride
(vi) titanium silicon nitride
(vii) titanium aluminum nitride
(viii) tungsten aluminum nitride
In embodiments of the invention, these nitride material are of the order of 4 nanometers in thickness, with a range of 1 to 10 nm. The compositions of these materials are adjusted so as that they have an electron affinity less than silicon which is 4.1 eV, resulting in a positive conduction band offset as shown in FIG. 5. The materials can be deposited by ALD as described in the next section.
AlN is a low electron affinity material. For example, UV photoemission measurements of the surface and interface properties of heteroepitaxial AlGaN on 6H—SiC grown by organometallic vapor phase epitaxy (OMVPE) show a low positive electron affinity for Al/sub 0.55/Ga/sub 0.45/N sample and GaN, whereas the AlN samples exhibited the characteristics of negative electron affinity. On the other hand, in semi-insulating and degenerate n-type GaN samples prepared by chemical vapor deposition with heat-cleaned surface the electron affinity was found to lie between 4.1 and 2.1 eV.
Assuming the electron affinity of GaN to be around 2.7 eV, the electron affinity decreases for GaAIN as the aluminum composition increases until the material becomes AlN which has a lower electron affinity of around 0.6 eV as shown in FIG. 6.
Ta—N: Plasma-enhanced atomic layer deposition (PEALD) of tantalum nitride (Ta—N) thin films at a deposition temperature of 260° C. using hydrogen radicals as a reducing agent for Tertbutylimidotris(diethylamido) tantalum have been described. The PEALD yields superior Ta—N films with an electric resistivity of 400 μΩcm and no aging effect under exposure to air. The film density is higher than that of Ta—N films formed by typical ALD, in which NH3 is used instead of hydrogen radicals. In addition, the as-deposited films are not amorphous, but rather polycrystalline structure of cubit TaN. The density and crystallinity of the films increases with the pulse time of hydrogen plasma. The films are Ta-rich in composition and contain around 15 atomic % of carbon impurity. In the PEALD of Ta—N films, hydrogen radicals are used a reducing agent instead of NH3, which is used as a reactant gas in typical Ta—N ALD. Films are deposited on SiO2 (100 nm)/Si wafers at a deposition temperature of 260° C. and a deposition pressure of 133 Pa in a cold-walled reactor using (Net2)3 Ta=Nbut [tertbutylimidotris(diethylamido)tantalum, TBTDET] as a precursor of Ta. The liquid precursor is contained in a bubbler heated at 70° C. and carried by 35 sccm argon. One deposition cycle consist of an exposure to a metallorganic precursor of TBTDET, a purge period with Ar, and an exposure to hydrogen plasma, followed by another purge period with Ar. The Ar purge period of 15 seconds instead between each reactant gas pulse isolates the reactant gases from each other. To ignite and maintain the hydrogen plasma synchronized with the deposition cycle, a rectangular shaped electrical power is applied between the upper and lower electrode. The showerhead for uniform distribution of the reactant gases in the reactor, capacitively coupled with an rf (13.56 MHz) plasma source operated at a power of 100 W, is used as the upper electrode. The lower electrode, on which a wafer resides, is grounded. Film thickness and morphology were analyzed by field emission scanning electron microscopy.
Ta(Al)N(C): Technical work on thin films have been studied using TaCl5 or TaBr5 and NH3 as precursors and Al(CH3)3 as an additional reducing agent. The deposition temperature is varied between 250 and 400° C. The films contained aluminum, carbon, and chlorine impurities. The chlorine content decreased drastically as the deposition temperature is increased. The film deposited at 400° C. contained less than 4 atomic % chlorine and also had the lowest resistivity, 1300 μΩcm. Five different deposition processes with the pulsing orders TaCl5-TMA-NH3, TMA-TACl5—NH3, TaBr5—NH3, TaBr5—Zn—NH3, and TaBr5-TMA-NH3 are used. TaCl5, TaBr5, and Zn are evaporated from open boats held inside the reactor. The evaporation temperatures for TaCl4, TaBr5, and Zn are 90, 140, 380° C., respectively. Ammonia is introduced into the reactor through a mass flowmeter, a needle valve, and a solenoid valve. The flow rate is adjusted to 14 sccm during a continuous flow. TMA is kept at a constant temperature of 16° C. and pulsed through the needle and solenoid valve. Pulse times are 0.5 s for TaCl5, TaBr5, NH3, and Zn whereas the pulse length of TMA is varied between 0.2 and 0.8 s. The length of the purge pulse is always 0.3 s. Nitrogen gas is used for the transportation of the precursor and as a purging gas. The flow rate of nitrogen is 400 sccm.
TiN: Atomic layer deposition (ALD) of amorphous TiN films on SiO2 between 170° C. and 210° C. has been achieved by the alternate supply of reactant sources, Ti[N(C2H5CH3)2]4 [tetrakis(ethylmethylamino)titanium: TEMAT] and NH3. These reactant sources are injected into the reactor in the following order: TEMAT vapor pulse, Ar gas pulse, NH3 gas pulse and Ar gas pulse. Film thickness per cycle saturated at around 1.6 monolayers per cycle with sufficient pulse times of reactant sources at 200° C. The results suggest that film thickness per cycle could exceed 1 ML/cycle in ALD, and are explained by the rechemisorption mechanism of the reactant sources. An ideal linear relationship between number of cycles and film thickness is confirmed.
TiAlN: Koo et al published paper on the study of the characteristics of TiAlN thin film deposited by atomic layer deposition method. The series of metal-Si—N barriers have high resistivity above 1000 μΩcm. They proposed another ternary diffusion barrier of TiAlN. TiAlN film exhibited a NaCl structure in spite of considerable Al contents. TiAlN films are deposited using the TiCl4 and dimethylaluminum hydride ethypiperdine (DMAH-EPP) as the titanium and aluminum precursors, respectively. TiCl4 is vaporized from the liquid at 13-15° C. and introduced into the ALD chamber, which is supplied by a bubbler using the Ar carrier gas with a flow rate of 30 sccm. The DMAH-EPP precursor is evaporated at 60° C. and introduced into the ALD chamber with the same flow rate of TiCl4. The NH3 gas is also used as a reactant gas and its flow rate is about 60 sccm. Ar purging gas is introduced for the complete separation of the source and reactant gases. TiAlN films are deposited at the temperatures between 350 and 400° C. and total pressure is kept constant to be two torr.
TiSiN: Metal-organic atomic-layer deposition (MOALD) achieves near-perfect step coverage step and control precisely the thickness and composition of grown thin films. A MOALD technique for ternary Ti—Si—N films using a sequential supply of Ti[N(CH3)2]4 [tetrakis (dimethylamido) titanium: TDMAT], silane (SiH4), and ammonia (NH3), has been developed and evaluated the Cu diffusion barrier characteristics of a 10 nm Ti—Si—N film with high-frequency C-V measurements. At 180° C. deposition temperature, silane is supplied separately in the sequence of the TDMAT pulse, silane pulse, and the ammonia pulse. The silicon content is the deposited films and the deposition thickness per cycle remained almost constant at 18 at. % and 0.22 nm/cycle, even though the silane partial pressure varied from 0.27 to 13.3 Pa. Especially, the Si content dependence is sirikingly different from the conventional chemical-vapor deposition. Step coverage is approximately 100% even on the 0.3 μm diameter hole with slightly negative slope and 10:1 aspect ratio.
BN: Boron nitride has for the first time been deposited from gaseous BBr3 and NH3 by means of atomic layer deposition. The films deposited at 750° C. and total pressure of 10 torr on silica substrates showed a turbostratic with a c-axis at 0.7 nm. The film deposited at 400° C. are significantly less ordered. The film density is obtained by means of X-ray reflectivity, and it is found to be 1.65-1.7 and 1.9-1.95 g cm−3 for the films deposited at 400 and 750° C., respectively. Furthermore, the films are, regardless of deposition temperature, fully transparent and very smooth. The surface roughness is 0.2-0.5 nm as measured by optical interferometry.
Silicon Nitride: Very recently extremely thin silicon nitride high-k (k=7.2) gate dielectrics have been formed at low temperature (<550° C.) by an atomic-layer-deposition technique with subsequent NH3 annealing at 550° C. A remarkable reduction in leakage current, especially in the low dielectric voltage region, which will be operating voltage for future technologies, has made it a highly potential gate dielectric for future ultralarge-scale integrated devices. Suppressed soft breakdown events are observed in ramped voltage stressing. This suppression is thought to be due to a strengthened structure of S—N bonds and the smoothness and uniformity at the poly-Si/ALD-silicon-nitride interface. The wafers are cleaned with a NH4OH:H2O2:H2O=0.15:3:7 solution at 80° C. for 10 min and terminated with hydrogen in 0.5% HF solution to suppress the native oxidation. The silicon-nitride gate dielectrics are deposited by alternately supplying SiCl4 and NH3 gases. The SiCl4 exposure at 340-375° C. followed by NH3 exposure at 550° C. is cyclically repeated 20 times. The gas pressure of SiCl4 and NH3 during the deposition is 170 and 300 Torr, respectively. Just after the ALD, NIH3 annealing is carried out for 90 min at 550° C. The Teq value of the ALD silicon-nitride is determined to be 1.2±0.2 nm from the ratio of the accumulation capacitances of the silicon nitride and the SiO2 samples.
Silicon-Nitride/SiO2: An extremely-thin (0.3-0.4 nm) silicon nitride layer has been deposited on thermally grown SiO2 by an atomic-layer-deposition technique. The boron penetration through the stack gate dielectric has been dramatically suppressed and the reliability has been significantly improved. An exciting feature of no soft breakdown (SBD) events is observed in ramped voltage stressing and time-dependent dielectric breakdown (TDDB) characteristics. After the thermal growth of 2.0 to 3.0 nm thick gate oxides on a Si (001) substrates, silicon nitride layer is deposited by alternately supplying SiCl4 and NH3 gases. The SiCl4 exposure at 375° C. followed by NH3 exposure at 550° C. is cyclically repeated five times, leading to a silicon nitride thickness of 0.3-0.4 nm. The thickness of the ALD silicon nitride is confirmed to be controlled with an atomic layer level by the number of the deposition cycle.
WN: Tungsten nitride films have been deposited with the atomic layer control using sequential surface reactions. The tungsten nitride film growth is accomplished by separating the binary reaction 2WF6+NH3->W2N+3HF+9/2 F2 into two half-reactions. Successive application of the WF6 and NH3 half-reactions in an ABAB . . . sequence produced tungsten nitride deposition at substrate temperatures between 600 and 800 K. Transmission Fourier transform infrared (FTIR) spectroscopy monitored the coverage of WFx* and NHy* surface species on high surface area particles during the WF6 and NH3 half-reactions. The FTIR spectroscope results demonstrated the WF6 and NH3 half-reactions are complete and self-limiting at temperatures >600 K. In situ spectroscopic ellipsometry monitored the film growth on Si(100) substrate vs. temperature and reactant exposure. A tungsten nitride deposition rate of 2.55 Å/AB cycle is measured at 600-800 K for WF6 and NH3 reactant exposure >3000 L and 10,000 L, respectively. X-ray photoelectron spectroscopy depth-profiling experiments determined that the films had a W2N stoichiometry with low C and O impurity concentrations. X-ray diffraction investigations revealed that the tungsten nitride films are microcrystalline. Atomic force microscopy measurements of the deposited films observed remarkably flat surface indicating smooth film growth. These smooth tungsten nitride films deposited with atomic layer control should be used as diffusion control for Cu on contact and via holes.
AlN: Aluminum nitride (AlN) has been grown on porous silica by atomic layer chemical vapor deposition (ALCVD) from trimethylaluminum (TMA) and ammonia precursors. The ALCVD growth is based on alternating, separated, saturating reactions of the gaseous precursors with the solid substrates. TMA and ammonia are reacted at 423 and 623 Kelvin (K), respectively, on silica which has been dehydroxylated at 1023 K pretreated with ammonia at 823 K. The growth in three reaction cycles is investigated quntitatively by elemental analysis, and the surface reaction products are identified by IR and solid state and Si NMR measurements. Steady growth of about 2 aluminum atoms/nm2 silica A/reaction cycle is obtained. The growth mainly took place through (I) the reaction of TMA which resulted in surface Al-Me and Si-Me groups, and (II) the reaction of ammonia which replaced aluminium-bonded methyl groups with amino groups. Ammonia also reacted in part with the silicon-bonded methyl groups formed in the dissociated reaction of TMA with siloxane bridges. TMA reacted with the amino groups, as it did with surface silanol groups and siloxane bridges. In general, the Al—N layer interacted strongly with the silica substrates, but in the third reaction cycle AlN-type sites may have formed.
GaN: Pseudo substrates of GaN templates have been grown by MOCVD on sapphire, apart from the quantum dot samples, which are grown on bulk 6H—SiC. Prior to GaN ALE, about 400-nm-thick fully relaxed AlN layers are deposited on all substrates. The N2 flux has been fixed to 0.5 sccm and the rf power to 300 W, which leads to maximum AlN and GaN growth rates of about 270 nm/h under N-limited metal-rich conditions. The Ga flux has been calibrated by measuring the GaN growth rate under N-rich conditions using reflection high-energy electron diffraction (RHEED) oscillations at Ts=650° C., where it is safe to assume that the Ga sticking coefficient is unity.
In embodiments of the present invention, the gate structure embodiment of FIG. 5, having silicon oxide-metal oxide-silicon oxide-nitride nanolaminates, is used in place of the gate structure provided in the following commonly assigned pending applications: Forbes, L., “Write Once Read Only Memory Employing Charge Trapping In Gate Insulators,” application Ser. No. 10/177,077; Forbes, L., “Write Once Read Only Memory Employing Floating Gates,” application Ser. No. 10/177,083; Forbes, L., “Write Once Read Only Memory with Large Work Funchtion Floating Gates,” application Ser. No. 10/177,213; Forbes, L., “Nanoncrystal Write Once Read Only Memory for Archival Storage,” application Ser. No. 10/177,214; Forbes, L., “Ferroelectric Write Once Read Only Memory for Archival Storage,” application Ser. No. 10/177,082; Forbes, L., “Vertical NROM Having a Storage Density of 1 Bit Per 1F2,” application Ser. No. 10/177,208; Forbes, L., “Multistate NROM Having a Storage Density Much Greater than 1 Bit Per 1F2,” application Ser. No. 10/177,211; Forbes, L., “NOR Flash Memory Cell with High Storage Density,” application Ser. No. 10/177,483.
FIGS. 7A-B and 8 are embodiments useful in illustrating the use of charge storage in the oxide-nitride nanolaminate layers to modulate the conductivity of the transistor cell according to the teachings of the present invention. That is, FIGS. 7A-7B illustrates the operation of an embodiment for a novel transistor cell 701 formed according to the teachings of the present invention. And, FIG. 8 illustrates the operation of a conventional DRAM cell 701. As shown in FIG. 7A, the embodiment consists of a gate insulator stack having insulator layers, 710, 708 and 718, e.g. 1. SiO2/oxide-nitride nanolaminate layers/SiO2. In the embodiment of FIG. 7A, the gate insulator stack having insulator layers, 710, 708 and 718, has a thickness 711 thicker than in a conventional DRAM cell, e.g. 801 and is equal to or greater than 10 nm or 100 Å (10−6 cm). In the embodiment shown in FIG. 7A a transistor cell has dimensions 713 of 0.1 μm (10−5 cm) by 0.1 μm. The capacitance, Ci, of the structure depends on the dielectric constant, ∈i, and the thickness of the insulating layers, t. In the embodiment, the dielectric constant is 0.3×10−12 F/cm and the thickness of the insulating layer is 10−6 cm such that Ci=∈i/t, Farads/cm2 or 3×10−7 F/cm2. In one embodiment, a charge of 1012 electrons/cm2 is programmed into the oxide-nitride nanolaminate layers of the transistor cell. Here the charge carriers become trapped in potential wells in the oxide-nitride nanolaminate layers 708 formed by the different electron affinities of the insulators 710, 708 and 718, as shown in FIG. 7A. This produces a stored charge ΔQ=1012 electrons/cm2×1.6×10−19 Coulombs. In this embodiment, the resulting change in the threshold voltage (ΔVt) of the transistor cell will be approximately 0.5 Volts (ΔVt=ΔQ/Ci or 1.6×10−7/3×10−7=½ Volt). For ΔQ=1012 electrons/cm3 in an area of 10−10 cm2, this embodiment of the present invention involves trapping a charge of approximately 100 electrons in the oxide-nitride nanolaminate layers 708 of the transistor cell. In this embodiment, an original VT is approximately ½ Volt and the VT with charge trapping is approximately 1 Volt.
FIG. 7B aids to further illustrate the conduction behavior of the novel transistor cell of the present invention. As one of ordinary skill in the art will understand upon reading this disclosure, if the transistor cell is being driven with a control gate voltage of 1.0 Volt (V) and the nominal threshold voltage without the oxide-nitride nanolaminate layers charged is ½ V, then if the oxide-nitride nanolaminate layers are charged the transistor cell of the present invention will be off and not conduct. That is, by trapping a charge of approximately 100 electrons in the oxide-nitride nanolaminate layers of the transistor cell, having dimensions of 0.1 μm (10−5 cm) by 0.1 μm, will raise the threshold voltage of the transistor cell to 1.0 Volt and a 1.0 Volt control gate potential will not be sufficient to turn the device on, e.g. Vt=1.0 V, I=0.
Conversely, if the nominal threshold voltage without the oxide-nitride nanolaminate layers charged is ½ V, then I=μCox×(W/L)×((Vgs−Vt)2/2), or 12.5 μA, with μCox=μCi=100 μA/V2 and W/L=1. That is, the transistor cell of the present invention, having the dimensions describe above will produce a current I=100 μA/V2×(¼)×(½)=12.5 μA. Thus, in the present invention an un-written, or un-programmed transistor cell can conduct a current of the order 12.5 μA, whereas if the oxide-nitride nanolaminate layers are charged then the transistor cell will not conduct. As one of ordinary skill in the art will understand upon reading this disclosure, the sense amplifiers used in DRAM arrays, and as describe above, can easily detect such differences in current on the bit lines.
By way of comparison, in a conventional DRAM with 30 femtoFarad (fF) storage capacitor 851 charged to 50 femto Columbs (fC), if these are read over 5 nS then the average current on a bit line 852 is only 10 μA (I=50 fC/5 ns=10 μA). Thus, storing a 50 fC charge on the storage capacitor equates to storing 300,000 electrons (Q=50 f/C/(1.6×10−19)=30×104=300.000 electrons).
FIG. 11 illustrates an embodiment of a novel in-service programmable logic array (PLA) formed with logic cells having a gate structure with oxide-nitride nanolaminate layers, according to the teachings of the present invention. In FIG. 11, PLA 1100 implements an illustrative logical function using a two level logic approach. Specifically, PLA 1100 includes first and second logic planes 1110 and 1122. In this example, the logic function is implemented using NOR-NOR logic. As shown in FIG. 11, first and second logic planes 1110 and 1122 each include an array of, logic cells, having a gate structure with oxide-nitride nanolaminate layers, which serve as driver transistors, 1101-1, 1101-2, . . . , 1101-N, and 1102-1, 1102-2, . . . , 1102-N respectively, formed according to the teachings of the present invention. The driver transistors, 1101-1, 1101-2, . . . , 1101-N, and 1102-1, 1102-2, . . . , 1102-N, have their first source/drain regions coupled to source lines or a conductive source plane. These driver transistors, 1101-1, 1101-2, . . . , 1101-N, and 1102-1, 1102-2, . . . , 1102-N are configured to implement the logical function of FPLA 1100. The driver transistors, 1101-1, 1101-2, . . . , 1101-N, and 1102-1, 1102-2, . . . , 1102-N are shown as n-channel transistors. However, the invention is not so limited. Also, as shown in FIG. 11, a number of p-channel metal oxide semiconductor (PMOS) transistors are provided as load device transistors, 1116 and 1124 respectively, having their source regions coupled to a voltage potential (VDD). These load device transistors, 1116 and 1124 respectively, operate in complement to thedrivertransistors, 1101-1, 1101-2, . . . , 1101-N, and 1102-1, 1102-2, . . . , 1102-N to form load inverters.
writing to one or more vertical MOSFETs arranged in rows and columns extending outwardly from a substrate and separated by trenches in a DRAM array in a reverse direction, wherein each MOSFET in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the DRAM array includes a number of sourcelines formed in a bottom of the trenches between rows of the vertical MOSFETs and coupled to the source regions of each transistor along rows the vertical MOSFETs, wherein along columns of the vertical MOSFETs the source region of each column adjacent vertical MOSFET couple to the sourceline in a shared trench, and wherein the DRAM array includes a number of bitlines coupled to the drain region along rows in the DRAM array, and wherein programming the one or more vertical MOSFETs in the reverse direction includes;
biasing a sourceline for two column adjacent vertical MOSFETs sharing a trench to a voltage higher than VDD;
grounding a bitline coupled to one of the drain regions of the two column adjacent vertical MOSFETs in the vertical MOSFET to be programmed;
applying a gate potential to the gate for each of the two column adjacent vertical MOSFETs to create a hot electron injection into the gate insulator of the vertical MOSFET to be programmed adjacent to the source region such that an addressed MOSFET becomes a programmed MOSFET and will operate at reduced drain source current in a forward direction;
reading one or more vertical MOSFETs in the DRAM array in a forward direction, wherein reading the one or more MOSFETs in the forward direction includes;
grounding a sourceline for two column adjacent vertical MOSFETs sharing a trench;
precharging the drain regions of the two column adjacent vertical MOSFETs sharing a trench to a fractional voltage of VDD;
applying a gate potential of approximately 1.0 Volt to the gate for each of the two column adjacent vertical MOSFETs sharing a trench such that a conductivity state of an addressed vertical MOSFET can be compared to a conductivity state of a reference cell; and
wherein storing the charge within the storage layer less than or equal to 10 nanometers thick includes storing a charge within a storage layer approximately 4 nanometers thick.
2. The method of claim 1, wherein creating a hot electron injection into the gate insulator of the addressed MOSFET adjacent to the source region includes creating a first threshold voltage region (Vt1) adjacent to the drain region and creating a second threshold voltage region (Vt2) adjacent to the source region, wherein Vt2 is greater that Vt1.
3. The method of claim 1, wherein reading one or more vertical MOSFETs in the DRAM array in a forward direction includes using a sense amplifier to detect whether an addressed vertical MOSFET is a programmed vertical MOSFET, wherein a programmed vertical MOSFET will not conduct, and wherein an un-programmed vertical MOSFET addressed over approximately 10 ns will conduct a current of approximately 12.5 μA such that the method includes detecting an integrated drain current having a charge of 800,000 electrons using the sense amplifier.
4. The method of claim 1, wherein in creating a hot electron injection into the gate insulator of an addressed vertical MOSFET includes changing a threshold voltage for the vertical MOSFET by approximately 0.5 Volts.
5. The method of claim 1, wherein creating a hot electron injection into the gate insulator of the addressed vertical MOSFET includes trapping a stored charge in the gate insulator of the addressed vertical MOSFET of approximately 1012 electrons/cm2.
6. The method of claim 1, wherein creating a hot electron injection into the gate insulator of the addressed vertical MOSFET includes trapping a stored charge in the gate insulator of the addressed vertical MOSFET of approximately 100 electrons.
7. The method of claim 1, wherein the method further includes using the vertical MOSFET as active device with gain, and wherein reading a programmed vertical MOSFET includes providing an amplification of a stored charge in the gate insulator from 100 to 800,000 electrons over a read address period of approximately 10 ns.
8. A method of operating a memory array, comprising:
writing a memory state to at least one of a plurality of vertical transistors in an array, including;
storing a charge within a storage layer of a nanolaminate insulator, wherein the storage layer is formed using atomic layer deposition techniques, and the nanolaminate insulator is located on a trench wall, and wherein the nanolaminate insulator layer separates a channel region within the trench wall from a gate located over the nanolaminate insulator within the trench;
wherein storing the charge is performed in a first direction;
reading the memory state of the vertical transistor in a second direction opposite from the first direction; and
further including comparing a source/drain current in the vertical transistor a reference source/drain current in a second vertical transistor.
9. The method of claim 8, wherein comparing the source/drain current to the reference source/drain current includes comparing to a reference source/drain current in a second vertical transistor located on an adjacent wall of the trench.
10. The method of claim 8, wherein storing the charge within the storage layer of a nanolaminate insulator includes storing a charge within a storage layer less than or equal to 10 nanometers thick.
11. A method of operating a memory array, comprising:
wherein storing the charge is performed in a first direction; and
reading the memory state of the vertical transistor in a second direction opposite from the first direction, including comparing a source/drain current of the vertical transistor in the second direction with source/drain current of a vertical reference transistor on an adjacent side of the trench.
12. The method of claim 11, wherein comparing a source/drain current of the vertical transistor in the second direction with source/drain current of a vertical reference transistor includes utilizing a common source line buried in a base of the trench.
13. The method of claim 11, wherein comparing a source/drain current of the vertical transistor in the second direction with source/drain current of a vertical reference transistor includes utilizing a gate that is shared between the vertical transistor and the reference vertical transistor.
14. The method of claim 11, wherein storing the charge within the storage layer of a nanolaminate insulator includes storing a charge within a storage layer less than or equal to 10 nanometers thick.
15. The method of claim 14, wherein storing the charge within the storage layer less than or equal to 10 nanometers thick includes storing a charge within a storage layer approximately 4 nanometers thick.
storing a charge within a nitride storage layer of a nanolaminate insulator, wherein the nitride storage layer is formed using atomic layer deposition techniques, and the nanolaminate insulator is located on a trench wall, and wherein the nanolaminate insulator layer separates a channel region within the trench wall from a gate located over the nanolaminate insulator within the trench;
wherein storing a charge within a nitride storage layer includes storing a charge within a Storage layer with an electron affinity less than 4.1 eV providing a positive conduction band offset with silicon oxide.
17. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a silicon nitride storage layer.
18. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within an aluminum nitride storage layer.
19. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a gallium nitride storage layer.
20. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a gallium aluminum nitride storage layer.
21. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a tantalum aluminum nitride storage layer.
22. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a titanium silicon nitride storage layer.
23. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a titanium aluminum nitride storage layer.
24. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a tungsten aluminum nitride storage layer.
US11492749 2002-07-08 2006-07-25 Memory utilizing oxide-nitride nanolaminates Active 2022-08-12 US7489545B2 (en)
US10190689 US7847344B2 (en) 2002-07-08 2002-07-08 Memory utilizing oxide-nitride nanolaminates
US10933050 US20050023574A1 (en) 2002-07-08 2004-09-02 Memory utilizing oxide-nitride nanolaminates
US11492749 US7489545B2 (en) 2002-07-08 2006-07-25 Memory utilizing oxide-nitride nanolaminates
US20060258097A1 true US20060258097A1 (en) 2006-11-16
US7489545B2 true US7489545B2 (en) 2009-02-10
ID=29999900
US10190689 Active 2022-10-07 US7847344B2 (en) 2002-07-08 2002-07-08 Memory utilizing oxide-nitride nanolaminates
US10933050 Abandoned US20050023574A1 (en) 2002-07-08 2004-09-02 Memory utilizing oxide-nitride nanolaminates
US11492749 Active 2022-08-12 US7489545B2 (en) 2002-07-08 2006-07-25 Memory utilizing oxide-nitride nanolaminates
US11492251 Active 2023-01-01 US7494873B2 (en) 2002-07-08 2006-07-25 Memory utilizing oxide-nitride nanolaminates
US (4) US7847344B2 (en)
US20040004247A1 (en) * 2002-07-08 2004-01-08 Micron Technology, Inc. Memory utilizing oxide-nitride nanolaminates
US20060008966A1 (en) * 2002-07-08 2006-01-12 Micron Technology, Inc. Memory utilizing oxide-conductor nanolaminates
US20070099366A1 (en) * 2004-08-31 2007-05-03 Micron Technology, Inc. Lanthanum aluminum oxide dielectric layer
US20080248618A1 (en) * 2005-02-10 2008-10-09 Micron Technology, Inc. ATOMIC LAYER DEPOSITION OF CeO2/Al2O3 FILMS AS GATE DIELECTRICS
US7915168B2 (en) * 2008-04-11 2011-03-29 Micron Technology, Inc. Semiconductor processing methods
US6521958B1 (en) * 1999-08-26 2003-02-18 Micron Technology, Inc. MOSFET technology for programmable address decode and correction
US6674667B2 (en) * 2001-02-13 2004-01-06 Micron Technology, Inc. Programmable fuse and antifuse and method therefor
US7075829B2 (en) * 2001-08-30 2006-07-11 Micron Technology, Inc. Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
US7012297B2 (en) * 2001-08-30 2006-03-14 Micron Technology, Inc. Scalable flash/NV structures and devices with extended endurance
US8026161B2 (en) * 2001-08-30 2011-09-27 Micron Technology, Inc. Highly reliable amorphous high-K gate oxide ZrO2
US6784480B2 (en) * 2002-02-12 2004-08-31 Micron Technology, Inc. Asymmetric band-gap engineered nonvolatile memory device
US7160577B2 (en) * 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7045430B2 (en) * 2002-05-02 2006-05-16 Micron Technology Inc. Atomic layer-deposited LaAlO3 films for gate dielectrics
US7205218B2 (en) * 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US7269071B2 (en) * 2003-12-16 2007-09-11 Micron Technology, Inc. NROM memory cell, memory array, related devices and methods
US6921702B2 (en) * 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US6790791B2 (en) * 2002-08-15 2004-09-14 Micron Technology, Inc. Lanthanide doped TiOx dielectric films
US6884739B2 (en) * 2002-08-15 2005-04-26 Micron Technology Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
US7183186B2 (en) * 2003-04-22 2007-02-27 Micro Technology, Inc. Atomic layer deposited ZrTiO4 films
KR100568859B1 (en) * 2003-08-21 2006-04-10 삼성전자주식회사 Method for manufacturing transistor of dynamic random access memory semiconductor
US7297608B1 (en) 2004-06-22 2007-11-20 Novellus Systems, Inc. Method for controlling properties of conformal silica nanolaminates formed by rapid vapor deposition
JP4455225B2 (en) * 2004-08-25 2010-04-21 Ｎｅｃエレクトロニクス株式会社 A method of manufacturing a semiconductor device
US7081421B2 (en) * 2004-08-26 2006-07-25 Micron Technology, Inc. Lanthanide oxide dielectric layer
US7365385B2 (en) * 2004-08-30 2008-04-29 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
US7235501B2 (en) * 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
US7294583B1 (en) 2004-12-23 2007-11-13 Novellus Systems, Inc. Methods for the use of alkoxysilanol precursors for vapor deposition of SiO2 films
US7271112B1 (en) 2004-12-30 2007-09-18 Novellus Systems, Inc. Methods for forming high density, conformal, silica nanolaminate films via pulsed deposition layer in structures of confined geometry
US7560395B2 (en) * 2005-01-05 2009-07-14 Micron Technology, Inc. Atomic layer deposited hafnium tantalum oxide dielectrics
US7109129B1 (en) 2005-03-09 2006-09-19 Novellus Systems, Inc. Optimal operation of conformal silica deposition reactors
US7135418B1 (en) * 2005-03-09 2006-11-14 Novellus Systems, Inc. Optimal operation of conformal silica deposition reactors
US7662729B2 (en) * 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7572695B2 (en) * 2005-05-27 2009-08-11 Micron Technology, Inc. Hafnium titanium oxide films
US20070045722A1 (en) * 2005-08-31 2007-03-01 Tzyh-Cheang Lee Non-volatile memory and fabrication thereof
US7589028B1 (en) 2005-11-15 2009-09-15 Novellus Systems, Inc. Hydroxyl bond removal and film densification method for oxide films using microwave post treatment
US7491653B1 (en) 2005-12-23 2009-02-17 Novellus Systems, Inc. Metal-free catalysts for pulsed deposition layer process for conformal silica laminates
US7579646B2 (en) * 2006-05-25 2009-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Flash memory with deep quantum well and high-K dielectric
US7563730B2 (en) * 2006-08-31 2009-07-21 Micron Technology, Inc. Hafnium lanthanide oxynitride films
US8294197B2 (en) * 2006-09-22 2012-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. Program/erase schemes for floating gate memory cells
US20080081114A1 (en) * 2006-10-03 2008-04-03 Novellus Systems, Inc. Apparatus and method for delivering uniform fluid flow in a chemical deposition system
US20080116447A1 (en) * 2006-11-20 2008-05-22 Atmel Corporation Non-volatile memory transistor with quantum well charge trap
US20080212625A1 (en) * 2007-01-15 2008-09-04 Kabusiki Kaisha Y.Y.L. Semiconductor device
US8372473B2 (en) * 2007-05-21 2013-02-12 L'air Liquide Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude Cobalt precursors for semiconductor applications
JP5461390B2 (en) * 2007-05-21 2014-04-02 レール・リキード−ソシエテ・アノニム・プール・レテュード・エ・レクスプロワタシオン・デ・プロセデ・ジョルジュ・クロード New metal precursors for semiconductor applications
US20090261346A1 (en) * 2008-04-16 2009-10-22 Ding-Yuan Chen Integrating CMOS and Optical Devices on a Same Chip
JP5513767B2 (en) * 2008-06-25 2014-06-04 株式会社日立国際電気 Manufacturing method, a substrate processing method of a semiconductor device, a substrate processing apparatus and a semiconductor device
US8735963B2 (en) * 2008-07-07 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Flash memory cells having leakage-inhibition layers
EP2244306B1 (en) * 2009-04-22 2014-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. A memory cell, an array, and a method for manufacturing a memory cell
US8624260B2 (en) 2010-01-30 2014-01-07 National Semiconductor Corporation Enhancement-mode GaN MOSFET with low leakage current and improved reliability
KR101140079B1 (en) * 2010-07-13 2012-04-30 에스케이하이닉스 주식회사 Semiconductor device comprising vertical transistor and method for forming the same
US8916868B2 (en) 2011-04-22 2014-12-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US8809854B2 (en) 2011-04-22 2014-08-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8759234B2 (en) * 2011-10-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Deposited material and method of formation
KR20130056608A (en) * 2011-11-22 2013-05-30 에스케이하이닉스 주식회사 Phase-change random access memory device and method of manufacturing the same
US8592921B2 (en) 2011-12-07 2013-11-26 International Business Machines Corporation Deep trench embedded gate transistor
CN102768988B (en) * 2012-07-25 2014-10-15 上海华力微电子有限公司 An effective barrier layer is determined that copper diffusion barrier capability method
JP2016192460A (en) * 2015-03-31 2016-11-10 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method for semiconductor device
KR20170024221A (en) * 2015-08-24 2017-03-07 삼성전자주식회사 Method for manufacturing semiconductor device
WO2017111874A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Dual threshold voltage (vt) channel devices and their methods of fabrication
US3665423A (en) 1969-03-15 1972-05-23 Nippon Electric Co Memory matrix using mis semiconductor element
US3877054A (en) 1973-03-01 1975-04-08 Bell Telephone Labor Inc Semiconductor memory apparatus with a multilayer insulator contacting the semiconductor
US3964085A (en) 1975-08-18 1976-06-15 Bell Telephone Laboratories, Incorporated Method for fabricating multilayer insulator-semiconductor memory apparatus
US4217601A (en) 1979-02-15 1980-08-12 International Business Machines Corporation Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure
US4507673A (en) 1979-10-13 1985-03-26 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4661833A (en) 1984-10-30 1987-04-28 Kabushiki Kaisha Toshiba Electrically erasable and programmable read only memory
US4939559A (en) 1981-12-14 1990-07-03 International Business Machines Corporation Dual electron injector structures using a conductive oxide between injectors
US5016215A (en) 1987-09-30 1991-05-14 Texas Instruments Incorporated High speed EPROM with reverse polarity voltages applied to source and drain regions during reading and writing
US5021999A (en) 1987-12-17 1991-06-04 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device with facility of storing tri-level data
US5027171A (en) 1989-08-28 1991-06-25 The United States Of America As Represented By The Secretary Of The Navy Dual polarity floating gate MOS analog memory device
US5253196A (en) 1991-01-09 1993-10-12 The United States Of America As Represented By The Secretary Of The Navy MOS analog memory with injection capacitors
US5274249A (en) 1991-12-20 1993-12-28 University Of Maryland Superconducting field effect devices with thin channel layer
US5298447A (en) 1993-07-22 1994-03-29 United Microelectronics Corporation Method of fabricating a flash memory cell
US5303182A (en) 1991-11-08 1994-04-12 Rohm Co., Ltd. Nonvolatile semiconductor memory utilizing a ferroelectric film
US5409859A (en) 1992-09-10 1995-04-25 Cree Research, Inc. Method of forming platinum ohmic contact to p-type silicon carbide
US5430670A (en) 1993-11-08 1995-07-04 Elantec, Inc. Differential analog memory cell and method for adjusting same
US5434815A (en) 1994-01-19 1995-07-18 Atmel Corporation Stress reduction for non-volatile memory cell
US5438544A (en) 1993-03-19 1995-08-01 Fujitsu Limited Non-volatile semiconductor memory device with function of bringing memory cell transistors to overerased state, and method of writing data in the device
US5508544A (en) 1992-12-14 1996-04-16 Texas Instruments Incorporated Three dimensional FAMOS memory devices
US5602777A (en) 1994-09-28 1997-02-11 Sharp Kabushiki Kaisha Semiconductor memory device having floating gate transistors and data holding means
US5627781A (en) 1994-11-11 1997-05-06 Sony Corporation Nonvolatile semiconductor memory
US5670790A (en) 1995-09-21 1997-09-23 Kabushikik Kaisha Toshiba Electronic device
US5754477A (en) 1997-01-29 1998-05-19 Micron Technology, Inc. Differential flash memory cell and method for programming
US5801401A (en) 1997-01-29 1998-09-01 Micron Technology, Inc. Flash memory with microcrystalline silicon carbide film floating gate
US5828605A (en) 1997-10-14 1998-10-27 Taiwan Semiconductor Manufacturing Company Ltd. Snapback reduces the electron and hole trapping in the tunneling oxide of flash EEPROM
US5852306A (en) 1997-01-29 1998-12-22 Micron Technology, Inc. Flash memory with nanocrystalline silicon film floating gate
US5886368A (en) 1997-07-29 1999-03-23 Micron Technology, Inc. Transistor with silicon oxycarbide gate and methods of fabrication and use
US5912488A (en) 1996-07-30 1999-06-15 Samsung Electronics Co., Ltd Stacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programming
US5943262A (en) 1997-12-31 1999-08-24 Samsung Electronics Co., Ltd. Non-volatile memory device and method for operating and fabricating the same
US6005790A (en) 1998-12-22 1999-12-21 Stmicroelectronics, Inc. Floating gate content addressable memory
US6020024A (en) 1997-08-04 2000-02-01 Motorola, Inc. Method for forming high dielectric constant metal oxides
US6049479A (en) 1999-09-23 2000-04-11 Advanced Micro Devices, Inc. Operational approach for the suppression of bi-directional tunnel oxide stress of a flash cell
US6115281A (en) 1997-06-09 2000-09-05 Telcordia Technologies, Inc. Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitors
US6122201A (en) 1999-10-20 2000-09-19 Taiwan Semiconductor Manufacturing Company Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM
US6140181A (en) 1997-11-13 2000-10-31 Micron Technology, Inc. Memory using insulator traps
US6171900B1 (en) 1999-04-15 2001-01-09 Taiwan Semiconductor Manufacturing Company CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET
US6194228B1 (en) 1997-10-22 2001-02-27 Fujitsu Limited Electronic device having perovskite-type oxide film, production thereof, and ferroelectric capacitor
US6243300B1 (en) 2000-02-16 2001-06-05 Advanced Micro Devices, Inc. Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
US6255683B1 (en) * 1998-12-29 2001-07-03 Infineon Technologies Ag Dynamic random access memory
US6269023B1 (en) 2000-05-19 2001-07-31 Advanced Micro Devices, Inc. Method of programming a non-volatile memory cell using a current limiter
US6294813B1 (en) 1998-05-29 2001-09-25 Micron Technology, Inc. Information handling system having improved floating gate tunneling devices
US6313518B1 (en) 1997-10-14 2001-11-06 Micron Technology, Inc. Porous silicon oxycarbide integrated circuit insulator
US6320784B1 (en) 2000-03-14 2001-11-20 Motorola, Inc. Memory cell and method for programming thereof
US6365470B1 (en) 2000-08-24 2002-04-02 Secretary Of Agency Of Industrial Science And Technology Method for manufacturing self-matching transistor
US6380579B1 (en) 1999-04-12 2002-04-30 Samsung Electronics Co., Ltd. Capacitor of semiconductor device
US6429063B1 (en) 1999-10-26 2002-08-06 Saifun Semiconductors Ltd. NROM cell with generally decoupled primary and secondary injection
US6432779B1 (en) 2000-05-18 2002-08-13 Motorola, Inc. Selective removal of a metal oxide dielectric
US6449188B1 (en) 2001-06-19 2002-09-10 Advanced Micro Devices, Inc. Low column leakage nor flash array-double cell implementation
US6456536B1 (en) 2000-06-23 2002-09-24 Advanced Micro Devices, Inc. Method of programming a non-volatile memory cell using a substrate bias
US6456531B1 (en) 2000-06-23 2002-09-24 Advanced Micro Devices, Inc. Method of drain avalanche programming of a non-volatile memory cell
US493140A (en) * 1893-03-07 Attachment of handles to vessels
US4173791A (en) 1977-09-16 1979-11-06 Fairchild Camera And Instrument Corporation Insulated gate field-effect transistor read-only memory array
JP2627096B2 (en) * 1990-01-29 1997-07-02 富士写真フイルム株式会社 Torsion spring drawer method and apparatus
US6521950B1 (en) 1993-06-30 2003-02-18 The United States Of America As Represented By The Secretary Of The Navy Ultra-high resolution liquid crystal display on silicon-on-sapphire
DE69701081T2 (en) * 1996-10-31 2000-08-24 Solvay A process for the preparation of an aqueous sodium hydroxide solution
JP4129071B2 (en) * 1998-03-20 2008-07-30 富士通株式会社 Semiconductor components and semiconductor mounting apparatus
WO2000070675A1 (en) 1999-05-14 2000-11-23 Hitachi, Ltd. Semiconductor memory device
DE19926108C2 (en) 1999-06-08 2001-06-28 Infineon Technologies Ag A non-volatile semiconductor memory cell having a metal oxide dielectric, and process for their preparation
US6867097B1 (en) * 1999-10-28 2005-03-15 Advanced Micro Devices, Inc. Method of making a memory cell with polished insulator layer
US6490205B1 (en) 2000-02-16 2002-12-03 Advanced Micro Devices, Inc. Method of erasing a non-volatile memory cell using a substrate bias
JP4002712B2 (en) 2000-05-15 2007-11-07 スパンション エルエルシー Data holding method of the nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device
US6618290B1 (en) 2000-06-23 2003-09-09 Advanced Micro Devices, Inc. Method of programming a non-volatile memory cell using a baking process
FR2811922B1 (en) * 2000-07-20 2003-01-10 Optoform Sarl Procedes De Prot Dough charged composition of metal powder, process for obtaining metal products from said composition, and metallic product obtained according to said method
US6487121B1 (en) 2000-08-25 2002-11-26 Advanced Micro Devices, Inc. Method of programming a non-volatile memory cell using a vertical electric field
US6459618B1 (en) 2000-08-25 2002-10-01 Advanced Micro Devices, Inc. Method of programming a non-volatile memory cell using a drain bias
US6660660B2 (en) * 2000-10-10 2003-12-09 Asm International, Nv. Methods for making a dielectric stack in an integrated circuit
US6465306B1 (en) 2000-11-28 2002-10-15 Advanced Micro Devices, Inc. Simultaneous formation of charge storage and bitline to wordline isolation
US20020089023A1 (en) 2001-01-05 2002-07-11 Motorola, Inc. Low leakage current metal oxide-nitrides and method of fabricating same
US6567303B1 (en) 2001-01-31 2003-05-20 Advanced Micro Devices, Inc. Charge injection
WO2002073696A1 (en) 2001-03-12 2002-09-19 Hitachi, Ltd. Process for producing semiconductor integrated circuit device
EP1405314A2 (en) 2001-06-18 2004-04-07 Ecole Polytechnique Fédérale de Lausanne (EPFL) Semiconductor device
US6563752B2 (en) 2001-08-02 2003-05-13 Macronix International Co., Ltd. Qualification test method and circuit for a non-volatile memory
US6525969B1 (en) 2001-08-10 2003-02-25 Advanced Micro Devices, Inc. Decoder apparatus and methods for pre-charging bit lines
US20030032270A1 (en) 2001-08-10 2003-02-13 John Snyder Fabrication method for a device for regulating flow of electric current with high dielectric constant gate insulating layer and source/drain forming schottky contact or schottky-like region with substrate
US6570787B1 (en) 2002-04-19 2003-05-27 Advanced Micro Devices, Inc. Programming with floating source for low power, low leakage and high density flash memory devices
US7847344B2 (en) 2002-07-08 2010-12-07 Micron Technology, Inc. Memory utilizing oxide-nitride nanolaminates
US7221017B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide-conductor nanolaminates
US6166401A (en) 1997-01-29 2000-12-26 Micron Technology, Inc. Flash memory with microcrystalline silicon carbide film floating gate
US5989958A (en) 1997-01-29 1999-11-23 Micron Technology, Inc. Flash memory with microcrystalline silicon carbide film floating gate
US6246606B1 (en) 1997-11-13 2001-06-12 Micron Technology, Inc. Memory using insulator traps
US6351411B2 (en) 1997-11-13 2002-02-26 Micron Technology, Inc. Memory using insulator traps
Abbas, S.A., et al., "N-Channel Igfet Design Limitations Due to Hot Electron Trapping", Technical Digest, International Electron Devices Meeting,,Washington, DC,(Dec. 1975),35-38.
Adelmann, C, et al., "Atomic-layer epitaxy of GaN quantum wells and quantum dots on (0001) AIN", Journal of Applied Physics, 91(8). (Apr. 15, 2002),5498-5500.
Ahn, Seong-Deok, et al., "Surface Morphology Improvement of Metalorganic Chemical Vapor Deposition Al Films by Layered Deposition of Al and Ultrathin TiN", Japanese Journal of Applied Physics, Part 1 (Regular Papers, Short Notes & Review Papers),39(6A), (Jun. 2000),3349-3354.
Akasaki, Isamu, et al., "Effects of AIN Buffer Layer on Crystallographic Structure and on Electrical and Optical Properties of GaN and Ga1-xAlxN Films Grown on Sapphire Substrate by MOVPE", Journal of Crystal Growth, 98(1-2). (Nov. 1, 1989),209-219.
Alen, Petra, "Atomic Layer deposition of Ta(Al)N(C) thin films using trimethylaluminum as a reducing agent", Journal of the Electrochemical Society, 148(10). (Oct. 2001),G566-G571.
Asari, K, et al., "Multi-mode and multi-level technologies for FeRAM embedded reconfigurable hardware", Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International,(Feb. 15-17, 1999),106-107.
Benjamin, M., "UV Photoemission Study of Heteroepitaxial AlGaN Films Grown on 6H-SiC", Applied Surface Science, 104/105, (Sep. 1996),455-460.
Bermudez, V., "The Growth and Properties of Al and AlN Films on GaN(0001)-(1 x1)", Journal of Applied Physics, 79(1). (Jan. 1996),110-119.
Bright, A A., et al., "Low-rate plasma oxidation of Si in a dilute oxygen/helium plasma for low-temperature gate quality Si/SiO2 interfaces", Applied Physics Letters, 58(6), (Feb. 1991),619-621.
Britton, J, et al., "Metal-nitride-oxide IC memory retains data for meter reader", Electronics, 45(22), (Oct. 23, 1972),119-23.
Carter, R J., "Electrical Characterization of High-k Materials Prepared By Atomic Layer CVD", IWGI, (2001),94-99.
Chaitsak, Suticai, et al., "Cu(InGa)Se2 thin-film solar cells with high resistivity ZnO buffer layers deposited by atomic layer deposition", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 38(9A). (Sep. 1999),4989-4992.
Chang, C., "Novel Passivation Dielectrics-The Boron-or Phosphorus-Doped Hydrogenated Amorphous Silicon Carbide Films", Journal of the Electrochemical Society, 132, (Feb. 1985),418-422.
Cheng, Baohong, et al., "The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-100nm MOSFET's", IEEE Transactions on Electron Devices, 46(7), (Jul. 1999),1537-1544.
Cricchi, J R., et al., "Hardened MNOS/SOS electrically reprogrammable nonvolatile memory", IEEE Transactions on Nuclear Science, 24(6), (Dec. 1977),2185-9.
Demichelis, F., "Influence of Doping on the Structural and Optoelectronic Properties of Amorphous and Microcrystalline Silicon Carbide", Journal of Applied Physics, 72(4). (Aug. 15, 1992),1327-1333.
Demichelis, F., "Physical Properties of Undoped and Doped Microcrystalline SIC:H Deposited By PECVD", Materials Research Society Symposium Proceedings, 219. Anaheim, CA,(Apr. 30-May 3, 1991),413-418.
Dimaria, D J., "Graded or stepped energy band-gap-insulator MIS structures (GI-MIS or SI-MIS)", Journal of Applied Physics, 50(9), (Sep. 1979),5826-5829.
Dipert, B., et al., "Flash Memory goes Mainstream", IEE Spectrum, No. 10, (Oct. 1993),48-50.
Eitan, Boaz, et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell", IEEE Electron Device Letters, 21(11), (Nov. 2000),543-545.
Elam, J W., et al., "Kinetics of the WF6 and Si2H6 surface reactions during tungsten atomic layer deposition", Surface Science, 479(1-3), (May 2001), 121-135.
Fauchet, P M., et al., "Optoelectronics and photovoitaic applications of microcrystalline SiC", Symp. on Materials Issues in Mecrocrystalline Semiconductors, (1989),291-292.
Ferris-Prabhu, A V., "Amnesia in layered insulator FET memory devices", 1973 International Electron Devices Meeting Technical Digest, (1973),75-77.
Ferris-Prabhu, A V., "Charge transfer in layered insulators", Solid-State Electronics, 16(9), (Sep. 1973),1086-7.
Ferris-Prabhu, A V., "Tunnelling theories of non-volatile semiconductor memories", Physica Status Solidi A, 35(1), (May 16, 1976),243-50.
Fisch, D E., et al., "Analysis of thin film ferroelectric aging", Proc. IEEE Int. Reliability Physics Symp., (1990),237-242.
Forbes, L., et al., "Field Induced Re-Emission of Electrons Trapped in SiO", IEEE Transactions on Electron Devices, ED-26 (11), Briefs,(Nov. 1979),1816-1818.
Forsgren, Katarina, "Atomic Layer Deposition of HfO2 using hafnium iodide", Conference held in Monterey, California, (May 2001),1 page.
Frohman-Bentchkowsky, D, "An Integrated metal-nitride-oxide-silicon (MNOS) memory", Proceedings of the IEEE, 57(6). (Jun. 1969),1190-1192.
Fuyuki, Takashi, et al., "Electronic Properties of the Interface between Si and TiO2 Deposited at Very Low Temperatures", Japanese Journal of Applied Physics, Part 1 (Regular Papers & Short Notes), 25(9). (Sept. 1986),1288-1291.
Fuyuki, Takashi, et al., "Initial stage of ultra-thin SiO2 formation at low temperatures using activated oxygen", Applied Surface Science, 117-118, (Jun. 1997),123-126.
Guha, S, et al., "Atomic beam deposition of lanthanum-and yttrium-based oxide thin films for gate dielectrics", Applied Physics Letters, 77, (2000),2710-2712.
Hubbard, K. J., et al., "Thermodynamic stability of binary oxides in contact with silicon", Journal of Materials Research, 11(11). (Nov. 1996),2757-2776.
Hwang, N., et al., "Tunneling and Thermal Emission of Electrons from a Distribution of Deep Traps in SiO", IEEE Transactions on Electron Devices, 40(6), (Jun. 1993),1100-1103.
Jeong, Chang-Wook, "Plasma-Assisted Atomic Layer Growth of High-Quality Aluminum Oxide Thin Films", Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 40(1), (Jan. 2001),285-289.
Juppo, Marika, "Use of 1,1-Dimethylhydrazine in the Atomic Layer Deposition of Transition Metal Nitride Thin Films", Journal of the Electrochemical Society, 147(9), (Sep. 2000),3377-3381.
Kim, C. T., et al., "Application of Al2O3 Grown by Atomic Layer Deposition to DRAM and FeRAM", International Symposium in Integrated Ferroelectrics, (Mar. 2000),316.
Klaus, J W., et al., "Atomic layer deposition of tungsten nitride films using sequential surface reactions", Journal of the Electrochemical Society, 147(3), (Mar. 2000),1175-81.
Koo, J, "Study on the characteristics of TiAIN thin film deposited by atomic layer deposition method", Journal of Vacuum Science & Technology A-Vacuum Surfaces & Films , 19(6), (Nov. 2001),2831-4.
Kukli, Kaupo, "Atomic Layer Deposition of Titanium Oxide Til4 and H2O2", Chemical Vapor Deposition, 6(6), (2000),303-310.
Kukli, Kaupo, "Tailoring the dielectric properties of HfO2- Ta2O3nanolaminates", Appl. Phys. Lett., 68, (1996),3737-3739.
Lee, Dong H., et al., "Metalorganic chemical vapor deposition of TiO2 Nanatase thin film on Si substrate", Applied Physics Letters, 66(7), (Feb. 1995),815-816.
Lei, T., "Epitaxial Growth and Characterization of Zinc-Blende Gallium Nitride on (001) Silicon", Journal of Applied Physics, 71(10), (May 1992),4933-4943.
Leskela, M, "ALD precursor chemistry: Evolution and future challenges", Journal de Physique IV (Proceedings), 9(8), (Sept. 1999),837-852.
Liu, C. T., "Circuit Requirement and Integration Challenges of Thin Gate Dielectrics for Ultra Small MOSFETs", International Electron Devices Meeting 1998. Technical Digest, (1998),747-750.
Luan, H., "High Quality Ta2O5 Gate Dielectrics with Tox,eq less than 10A", IEDM, (1999),pp.141-144.
Lusky, et al., "Characterization of channel hot electron injection by the subthreshold slope of NROM/sup TM/device", IEEE Electron Device Letters, vol. 22, No. 11, (Nov. 2001),556-558.
Maayan, E., et al., "A 512Mb BROM Flash Data Storage: Memory with 8MB/s Data Rate", ISSCC 2002 / Session 6 / SRAM and Non-Volatile Memories.(Feb. 2002),4 pages.
Marlid, Bjorn, et al., "Atomic layer deposition of BN thin films", Thin Solid Films, 402(1-2), (Jan. 2002),167-171.
Martins, R, "Transport Properties of Doped Silicon Oxycarbide Microcrystalline Films Produced by Spatial Separation Techniques", Solar Energy Materials and Solar Cells, 41-42, (1996),493-517.
Martins, R., "Wide Band Gap Microcrystalline Silicon Thin Films", Diffusion and Defect Data : Solid State Phenomena, 44-46, Part 1, Scitec Publications,(1995),299-346.
Min, J., "Metal-organic atomic-layer deposition of titanium-silicon-nitride films", Applied Physics Letters, 75(11), (1999),1521-1523.
Min, Jae-Sik, et al., "Atomic layer deposition of TiN films by alternate supply of tetrakis (ethylmethylamino)-titanium and ammonia", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 37(9A). (Sep. 1998),4999-5004.
Moazzami, R, "Endurance properties of Ferroelectric PZT thin films", Int. Electron Devices Mtg., San Francisco,(1990),417-20.
Moazzami, R, "Ferroelectric PZT thin films for semiconductor memory", Ph.D Thesis, University of California, Berkeley, (1991).
Molnar, R., "Growth of Gallium Nitride by Electron-Cyclotron Resonance Plasma-Assisted Molecular-Beam Epitaxy: The Role of Charged Species", Journal of Applied Physics, 76(8). (Oct. 1994),4587-4595.
Morishita, S, "Atomic-layer chemical-vapor-deposition of SiO2by cyclic exposures of CH3OSi(NCO)3 and H2O2", Japanese Journal of Applied Physics Part 1- Regular Papers Short Notes & Review Papers , 34(10), (Oct. 1995),5738-42.
Moriwaki, Masaru, et al., "Improved metal gate process by simultaneous gate-oxide nitridation during W/WN/sub x/gate formation", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers , 39(4B), (Apr. 2000) ,2177-2180.
Muller, R. S., et al., In: Device Electronics for Integrated Circuits, Second Edition, John Wiley & Sons, New York,(1986),p. 157.
Nakajima, Anri, et al., "NH3 annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability", Applied Physics Letters, 80(7). (Feb. 2002),1252-1254.
Nakjima, Anri, "Soft breakdown free atomic-layer-deposited silicon-nitride SiO2 stack gate dielectrics", International Electron Devices Meeting. Technical Digest, (2001),6.5.1-4.
Niilisk, A, "Atomic-scale optical monitoring of the initial growth of TiO2 thin films", Proceedings of the SPIE-The International Society for Optical Engineering, 4318. (2001),72-77.
Pankove, J., "Photoemission from GaN", Applied Physics Letters, 25(1), (Jul. 1, 1974),53-55.
Park, Jin-Seong, et al., "Plasma-Enhanced Atomic Layer Deposition of Tantaium Nitrides Using Hydrogen Radicals as a Reducing Agent", Electrochemical & Solid-State Letters, 4(4), (Apr. 2001),C17-19.
Puurunen, R L., et al., "Growth of aluminum nitride on porous silica by atomic layer chemical vapour deposition", Applied Surface Science, 165(2-3), (Sept. 12, 2000),193-202.
Renlund, G. M., "Silicon oxycarbide glasses: Part I. Preparation and chemistry", J. Mater. Res., (Dec. 1991),pp. 2716-2722.
Renlund, G. M., "Silicon oxycarbide glasses: Part II. Structure and properties", J. Mater. Res., vol. 6, No. 12,(Dec. 1991),pp. 2723-2734.
Ritala, Mikko, "Atomic Layer Epitaxy Growth of Titanium, Zirconium and Hafnium Dioxide Thin Films", Annales Academiae Scientiarum Fennicae. (1994),24-25.
Robertson, J., "Band offsets of wide-band-gap oxides and implications for future electronic devices", Journal of Vacuum Science & Technology B (Microelectronics and Nanometer Structures), 18(3), (May-Jun. 2000),1785-1791.
Shimada, Hiroyuki, et al., "Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum layer", IEEE Transactions on Electron Devices, vol. 48, No. 8. (Aug. 200),1619-1626.
Sneh, Ofer, "Thin film atomic layer deposition equipment for semiconductor processing", Thin Solid Films, 402. (2002),248-261.
Song, Hyun-Jung, et al., "Atomic Layer Deposition of Ta2 O5 Films Using Ta2 O5 and NH3", Ultrathin SiO2 and High-K Materials for ULSI Gate Dielectrics. Symposium, (1999),469-471.
Suntola, T., "Atomic Layer Epitaxy", Handbook of Crystal Growth, 3; Thin Films of Epitaxy, Part B; Growth Mechanics and Dynamics. Amsterdam,(1994),601-663.
Suntola, Tuomo, "Atomic layer epitaxy", Thin Solid Films, 216(1), (Aug. 28, 1992),84-89.
Sze, S M., "Physics of Semiconductor Devices", New York : Wiley. (1981),504-506.
Sze, S M., "Physics of Semiconductor Devices", New York : Wiley.(1981),473.
Wei, L S., et al., "Trapping, emission and generation in MNOS memory devices", Solid-State Electronics, 17(6). (Jun. 1974),591-8.
White, M H., "Direct tunneling in metal-nitride-oxide-silicon (MNOS) structures", Programme of the 31st physical electronics conference. (1971), 1.
White, M H., et al., "Characterization of thin-oxide MNOS memory transistors", IEEE Transactions on Electron Devices, ED-19(12). (Dec. 1972),1280-1288.
Wilk, G. D., "High-K gate dielectrics: Current status and materials properties considerations", Journal of Applied Physics, 89(10). (May 2001),5243-5275.
Wood, S W., "Ferroelectric memory design", M.A.Sc. thesis, University of Toronto. (1992).
Yagishita, Atsushi, et al., "Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) with low threshold voltage, high drive current and uniform electrical characteristics", International Electron Devices Meeting 2000. Technical Digest. IEDM. (Dec. 2000),663-666.
Yoder, M, "Wide Bandgap Semiconductor Materials and Devices", IEEE Transactions on Electron Devices, 43. (Oct. 1996), 1633-1636.
Zhang, H., "Atomic Layer Deposition of High Dielectric Constant Nanolaminates", Journal of The Electrochemical Society, 148(4). (Apr. 2001),F63-F66.
Zhu, W J., et al., "Current transport in metal/hafnium oxide/silicon structure", IEEE Electron Device Letters, 23, (2002),97-99.
US8785272B2 (en) * 2002-04-18 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Process to make high-K transistor dielectrics
US8012824B2 (en) * 2002-04-18 2011-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Process to make high-K transistor dielectrics
US20110318915A1 (en) * 2002-04-18 2011-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Process to make high-k transistor dielectrics
US20050023574A1 (en) * 2002-07-08 2005-02-03 Micron Technology, Inc. Memory utilizing oxide-nitride nanolaminates
US20110143538A1 (en) * 2008-04-11 2011-06-16 Micron Technology, Inc. Semiconductor Processing Methods
US8440567B2 (en) 2008-04-11 2013-05-14 Micron Technology, Inc. Semiconductor processing methods
US8735292B2 (en) 2008-04-11 2014-05-27 Micron Technology, Inc. Semiconductor processing methods
US7847344B2 (en) 2010-12-07 grant
US20060258097A1 (en) 2006-11-16 application
US20060261376A1 (en) 2006-11-23 application
US20050023574A1 (en) 2005-02-03 application
US7494873B2 (en) 2009-02-24 grant
US20040004247A1 (en) 2004-01-08 application
US6384448B1 (en) 2002-05-07 P-channel dynamic flash memory cells with ultrathin tunnel oxides
US5886376A (en) 1999-03-23 EEPROM having coplanar on-insulator FET and control gate
US7042052B2 (en) 2006-05-09 Transistor constructions and electronic devices
US6265268B1 (en) 2001-07-24 High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device
US6461949B1 (en) 2002-10-08 Method for fabricating a nitride read-only-memory (NROM)
US6303942B1 (en) 2001-10-16 Multi-layer charge injection barrier and uses thereof
US5969992A (en) 1999-10-19 EEPROM cell using P-well for tunneling across a channel
US7115942B2 (en) 2006-10-03 Method and apparatus for nonvolatile memory
US6249460B1 (en) 2001-06-19 Dynamic flash memory cells with ultrathin tunnel oxides
US5604357A (en) 1997-02-18 Semiconductor nonvolatile memory with resonance tunneling
US6992349B2 (en) 2006-01-31 Rail stack array of charge storage devices and method of making same
US5731238A (en) 1998-03-24 Integrated circuit having a jet vapor deposition silicon nitride film and method of making the same
US6791883B2 (en) 2004-09-14 Program and erase in a thin film storage non-volatile memory
US6461984B1 (en) 2002-10-08 Semiconductor device using N2O plasma oxide and a method of fabricating the same
US20060180851A1 (en) 2006-08-17 Non-volatile memory devices and methods of operating the same
US6768156B1 (en) 2004-07-27 Non-volatile random access memory cells associated with thin film constructions
US6906390B2 (en) 2005-06-14 Nonvolatile semiconductor storage and method for manufacturing the same
US20050023626A1 (en) 2005-02-03 Lanthanide oxide / hafnium oxide dielectrics
US7388246B2 (en) 2008-06-17 Lanthanide doped TiOx dielectric films
US20070187831A1 (en) 2007-08-16 Conductive layers for hafnium silicon oxynitride films