Source: http://www.patentsencyclopedia.com/app/20100277882
Timestamp: 2018-06-25 08:54:52
Document Index: 33220464

Matched Legal Cases: ['art.\n1', 'art.\n3', 'art.\n4', 'art.\n9', 'art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 1', 'art 1', 'art 2', 'art 2', 'art 2', 'art 1', 'art 2', 'art 1', 'art 1', 'art 1', 'art 1', 'art 2', 'art 2', 'art 2', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2']

MOTHERBOARD AND MOTHERBOARD LAYOUT METHOD - Patent application
Patent application title: MOTHERBOARD AND MOTHERBOARD LAYOUT METHOD
Inventors: Chia-Nan Pai (Tu-Cheng, TW) Han-Long Chen (Shenzhen City, CN) Ning Li (Shenzhen City, CN) Shou-Kuo Hsu (Tu-Cheng, TW)
Patent application number: 20100277882
MOTHERBOARD AND MOTHERBOARD LAYOUT METHOD - Patent application <?php require_once('/home/patents/php/mtc.config.php'); require_once('/home/patents/php/mtc.class.php'); $MTC = new MTC(); $MTC->init(); ?>
Inventors: SHOU-KUO HSU CHIA-NAN PAI HAN-LONG CHEN NING LI
A motherboard layout method includes positioning two electronic elements on a top layer of a motherboard, and positioning another two electronic elements on a bottom layer of the motherboard, connecting one end of a first electronic element on the top layer to the same end of a first electronic element on the bottom layer with a first via hole, and connecting the same end of a second electronic element on the top layer to the same end of a second electronic element on the bottom layer with a second via hole. The method further includes connecting the other ends of the two electronic elements on the top layer to a first part, and connecting the other ends of the two electronic elements on the bottom layer to a second part.
1. A motherboard layout method, the method comprising:positioning a first and a third electronic element on a top layer of a motherboard, and positioning an second and a fourth electronic element on a bottom layer of the motherboard;connecting a first bonding pad of one end of the first electronic element on the top layer to a second bonding pad of the same end of the second electronic element on the bottom layer corresponding to the first electronic element on the top layer with a first via hole;connecting a third bonding pad of the same end of the third electronic element on the top layer to a fourth bonding pad of the same end of the fourth electronic element on the bottom layer corresponding to the third electronic element on the top layer with a second via hole;connecting a bonding pad of the other end of the first and the third electronic elements on the top layer with a first part; andconnecting a bonding pad of the other end of the second and the fourth electronic elements on the bottom layer with a second part.
3. The method according to claim 1, a type of the first part is different from a type of the second part.
4. The method according to claim 3, if only the first part is used, the first and the third electronic elements on the top layer are connected to the first part, and differential signals are transmitted to the first part through the first and the third electronic elements on the top layer of the motherboard.
5. The method according to claim 3, if only the second part is used, the second and the fourth electronic elements on the bottom layer are connected to the second part, and differential signals are transmitted to the second part through the second and the fourth electronic elements on the bottom layer of the motherboard.
6. A motherboard, comprising:a first and a third electronic element being positioned on a top layer of the motherboard and an second and a fourth electronic element being positioned on a bottom layer of the motherboard;a first via hole operable to connect a first bonding pad of one end of the first electronic element on the top layer to a second bonding pad of the same end of the second electronic element on the bottom layer corresponding to the first electronic element on the top layer;a second via hole operable to connect a third bonding pad of the same end of the third electronic element on the top layer to a fourth bonding pad of the same end of the fourth electronic element on the bottom layer corresponding to the third electronic element on the top layer;a first part operable to connect to a bonding pad of the other end of the first and the third electronic elements on the top layer; anda second part operable to connect to a bonding pad of the other end of the second and the fourth electronic elements on the bottom layer.
7. The motherboard according to claim 1, wherein the first, second, third, and fourth electronic elements are selected from the group consisting of a capacitor and a resistor.
8. The motherboard according to claim 1, a type of the first part is different from a type of the second part.
9. The motherboard according to claim 8, if only the first part is used, the first and the third electronic elements on the top layer are connected to the first part, and differential signals are transmitted to the first part through the first and the third electronic elements on the top layer of the motherboard.
10. The motherboard according to claim 8, if only the second part is used, the second and the fourth electronic elements on the bottom layer are connected to the second part, and differential signals are transmitted to the second part through the second and the fourth electronic elements on the bottom layer of the motherboard.
[0002]Embodiments of the present disclosure relate to motherboard design methods, and particularly to a motherboard and motherboard layout method.
[0004]Motherboard layout is an important phase in the manufacturing process of a motherboard and is closely related to product quality. If two different kinds of parts are installed on the motherboard, a co-lay method is used to connect the different parts (refer to FIG. 1). Co-lay is a process where one part 1 is electronically connected to the motherboard through another part 2. However, as shown in FIG. 1, if only the part 1 is used, then the connection to the other part 2 becomes a stub, and the stub can interfere with a differential signal transmitted by the part 1.
[0005]FIG. 1 is a schematic diagram of one embodiment of a motherboard layout method in a prior art;
[0006]FIG. 2 is a plane view of one embodiment of a motherboard layout method provided in the present application;
[0007]FIG. 3A is a schematic view of one embodiment of a layout of a first part in FIG. 2;
[0008]FIG. 3B is a schematic view of one embodiment of a layout of a second part in FIG. 2;
[0009]FIG. 4A is a schematic diagram of one embodiment of a simulation result of a differential signal transmitted by the first part of FIG. 1;
[0010]FIG. 4B is a schematic diagram of one embodiment of a simulation result of a differential signal transmitted by second part of FIG. 1;
[0011]FIG. 5A is a schematic diagram of one embodiment of a simulation result of a differential signal transmitted by the first part of FIG. 2; and
[0012]FIG. 5B is a schematic diagram of one embodiment of a simulation result of a differential signal transmitted by the second part of FIG. 2.
[0013]FIG. 2 is a plane view of one embodiment of a motherboard 6 in communication with electronic elements. One embodiment of a layout method for the motherboard 6 is described with reference to FIG. 3A and FIG. 3B, firstly, two electronic elements, such as a capacitor 41 and a capacitor 51, are positioned on a top layer of the motherboard 6, and another two electronic elements, such as a capacitor 42 and a capacitor 52, are positioned on a bottom layer of the motherboard 6. In other embodiments, the electronic elements may be resistors.
[0014]Secondly, a first via hole 4 is connected to a first bonding pad h1 of one end of the capacitor 41 of the top layer, and a second bonding pad h2 of the same end of the capacitor 42 on the bottom layer corresponding to the capacitor 41.
[0015]Thirdly, a second via hole 5 is connected to a third bonding pad h3 of the same end of the capacitor 51 of the top layer, and a fourth bonding pad h4 of the same end of the capacitor 52 on the bottom layer corresponding to the capacitor 51.
[0016]Fourthly, a first part 1 is connected to a bonding pad h5 of the capacitor 41 and a bonding pad h7 of the capacitor 51 on the top layer of the motherboard 6, and a second part 2 is connected to a bonding pad h6 of the capacitor 42 and a bonding pad h8 of the capacitor 52 on the bottom layer of the motherboard 6. In one embodiment, a type of the first part 1 is different from a type of the second part 2.
[0017]If only the first part 1 is used, the two electronic elements on the top layer (e.g., the capacitor 41 and the capacitor 51) of the motherboard 6 are connected to the first part 1, and differential signals sent by a differential signal controller 10 are transmitted to the first part 1 through the two electronic elements on the top layer of the motherboard 6 (refer to a broken line shown in FIG. 3A). In one embodiment, the differential signal controller 10 is positioned on a north bridge or a south bridge of the motherboard 6.
[0018]If only the second part 2 is used, the two electronic elements on the bottom layer (e.g., the capacitor 42 and the capacitor 52) of the motherboard 6 are connected to the second part 2, and differential signals sent by the differential signal controller 10 are transmitted to the second part 2 through the two electronic elements on the bottom layer of the motherboard 6 (refer to a broken line shown in FIG. 3B).
[0019]In other embodiments, the first part 1 may be connected to the bonding pad h6 of the capacitor 42 and the bonding pad h8 of the capacitor 52 on the bottom layer of the motherboard 6, and the second part 2 may be connected to the bonding pad h5 of the capacitor 41 and the bonding pad h7 of the capacitor 51 on the top layer of the motherboard 6.
[0020]FIG. 4A is a schematic diagram of one embodiment of a simulation result of a differential signal transmitted by the first part 1 of FIG. 1, and FIG. 5A is a schematic diagram of one embodiment of a simulation result of a differential signal transmitted by the first part 1 of FIG. 2. In one exemplary example, a length of the stub in FIG. 4A is 800 mil, and the stub in FIG. 5A is substantially removed. Thus, quality of the differential signal transmitted by the first part 1 of FIG. 2 is better than quality of the differential signal transmitted by the first part 1 of FIG. 1.
[0021]FIG. 4B is a schematic diagram of one embodiment of a simulation result of a differential signal transmitted by the second part 2 of FIG. 1, and FIG. 5B is a schematic diagram of one embodiment of a simulation result of a differential signal transmitted by the second part 2 of FIG. 2. In one exemplary example, a length of the stub in FIG. 4B is 1600 mil, and the stub in FIG. 5B is substantially removed. Thus, quality of the differential signal transmitted by the second part 2 of FIG. 2 is better than quality of the differential signal transmitted by the second part 2 of FIG. 1.
[0022]The present embodiment connects the first part 1 and the second part 2 of the motherboard 6 with the via hole 4 and the via hole 5, so as to improve quality of the differential signal transmitted by the first part 1 or the second part 2.
[0023]It should be emphasized that the above-described embodiments of the present disclosure, particularly, any embodiments, are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiment(s) of the disclosure without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and the present disclosure and protected by the following claims.