Source: http://www.google.com/patents/US20020022301?dq=6188988
Timestamp: 2014-07-12 11:01:59
Document Index: 519899779

Matched Legal Cases: ['arts 144', 'arts 144', 'art 144', 'arts 144', 'arts 144', 'arts 144', 'arts 144', 'arts 144', 'arts 190']

Patent US20020022301 - Method for manufacturing a semiconductor package - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via...http://www.google.com/patents/US20020022301?utm_source=gb-gplus-sharePatent US20020022301 - Method for manufacturing a semiconductor packageAdvanced Patent SearchPublication numberUS20020022301 A1Publication typeApplicationApplication numberUS 09/482,216Publication dateFeb 21, 2002Filing dateJan 12, 2000Priority dateJul 12, 1999Also published asUS6376279, US6555921, US20020017711Publication number09482216, 482216, US 2002/0022301 A1, US 2002/022301 A1, US 20020022301 A1, US 20020022301A1, US 2002022301 A1, US 2002022301A1, US-A1-20020022301, US-A1-2002022301, US2002/0022301A1, US2002/022301A1, US20020022301 A1, US20020022301A1, US2002022301 A1, US2002022301A1InventorsYong Kwon, Sa Kang, Nam Seog Kim, Dong JangOriginal AssigneeKwon Yong Hwan, Kang Sa Yoon, Nam Seog Kim, Jang Dong HyeonExport CitationBiBTeX, EndNote, RefManReferenced by (11), Classifications (48), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod for manufacturing a semiconductor packageUS 20020022301 A1Abstract A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film. The semiconductor package includes: an integrated circuit having chip pads; a substrate attached to the integrated circuit so that via holes of the substrate are above the chip pads; solder fillings inside the via holes, the solder fillings electrically connecting the chips pads to the pattern metal layer; and another dielectric layer between the substrate and the semiconductor integrated circuit. The semiconductor package further includes external terminals, interconnection bumps on the chip pads, and polymer protection layers on the solder fillings. Images(14) Claims(20)
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0021] The present invention is directed to chip scale packages and methods for manufacturing the chip scale packages. The methods can fabricate multiple chip scale packages on a semiconductor wafer including integrated circuits, and separate the chip scale packages by sawing. The individual chip scale packages can be mounted on a circuit board of an electronic device. [0022] FIGS. 5 to 22 illustrate a method for manufacturing a chip scale package according to an embodiment of the present invention. Referring to FIG. 5, a known wafer fabrication method produces a semiconductor wafer 100 including integrated circuits (not shown), chip pads 104, and a passivation layer 106 on a silicon wafer substrate 102. Openings in the passivation layer 106 expose chip pads 104. The wafer 100 also includes scribe lines (not shown), which divide the integrated circuits. [0023] With reference to FIG. 6, an under barrier metal (UBM) 108 is formed on the chip pad 104 to increase the adhesion strength between the chip pad 104 and a solder bump to be formed on the chip pad 104. Typically, the UBM 108 is multi-layered and includes nickel (Ni), copper (Cu), gold (Au), titanium (Ti), chromium (Cr), titanium-tungsten (TiW), and/or nickel-vanadium (NiV) layers. Other metal layers also can be a part of the UBM 108. The structure of the UBM 108 and the method of fabricating the UBM 108 are well known in the art. For example, electro-plating or electroless-plating can form the UBM 108. Prior to the plating but before forming the passivation, the chip pads 104 can be coated with Palladium (Pd) or Zinc (Zn) to facilitate the plating. A Pd coating can be formed by dipping the chip pads in PdCl2 diluted with a small quantity of HCl and H2O. To form a Zn coating, the chip pads are first treated with HNO3, dipped in zincate solution for about 1 minute, treated with HNO3 for about 15 seconds, and again dipped in zincate solution for about 1 minute. [0024]FIG. 7 shows the semiconductor wafer 100 on which a metal bump 110 is formed. FIGS. 8 to 13 illustrate various methods for forming the metal bumps on the chip pads 104 having UBM 108. However, other known bump forming methods can form the metal bumps of the present invention. [0025] First, as shown in FIGS. 8 and 9, dipping the wafer 100 in molten solder 114 in a container 112 can form a solder bump 110 a. When the wafer 100 is dipped in the molten solder 114 (FIG. 8) and taken up (FIG. 9), the molten solder 114 sticks only to the UBM 108 on the chip pad 104, not to the passivation layer 106. The solder on the pads 104 solidifies, forming the metal bump 110 a. [0026] Metal jetting of molten solder can also form a solder bump 110 b, as shown in FIGS. 10 and 11. An injector 116 of a metal jetting apparatus (not shown) drops the molten solder 118 on the chip pad 104. The molten solder 118 solidifies on the chip pad 104, forming the metal bump 110 b. [0027]FIGS. 12 and 13 illustrate a wire-cutting method that forms a metal bump 110 c. According to this method, a metal wire 124 is ball-bonded on the chip pad 104 with a wire bonder 120, and a cutting tool 122 cuts the metal wire 124 above the ball-shaped portion of the metal wire 110 c, forming the metal bump 110 c. [0028] Separately from the wafer 100, a rerouting film 130 is prepared, as shown in FIG. 14. The rerouting film 130 includes multiple film units corresponding to individual integrated circuit chips. [0029] The rerouting film 130 includes a base film 132, for example, a polyimide film, and a metal pattern layer 134 embedded in the base film 132. Terminal pads 138 are embedded in the base film 132, connecting to the metal pattern layer 134 as shown in FIG. 14. One surface of the terminal pads 138 contacts the metal pattern layer 134, and the other surface of terminal pads 134 is exposed through a lower surface 131 a of the base film 132. The rerouting film 130 also includes via holes 136, so that the metal pattern layer 143 in the via holes 136. Each chip pad 104 of the wafer 100 has a corresponding via hole 136. Known manufacturing method for flexible printed circuit board can manufacture the rerouting film 130. [0030] To produce chip scale packages (CSPs), the wafer 100 with the metal bumps 110 (FIG. 7) is assembled with the rerouting film 130 (FIG. 14). FIGS. 15 to 22, which schematically show the metal bumps 110 and the rerouting film 130, illustrate the assembly process. [0031] First, as shown in FIG. 15, the rerouting film 130 is attached to a jig 140. A polymer 142, such as an epoxy adhesive, is supplied to a upper surface 131 b of the rerouting film 130 by well-known coating or dispensing method. Then, as shown in FIG. 16, the wafer 100 is aligned above and pressed against the rerouting film 130 such that the metal bumps 110 of the wafer 100 are inside the via holes 136 of the rerouting film 130, and the polymer 142 spreads, filling the gap between the rerouting film 130 and the wafer 100 and the via holes 136 of the rerouting film 130. After the polymer 142 is cured, the wafer 100 is attached to the rerouting film 130. In case of the epoxy resin adhesive, the curing is performed at 150� C. for about 30 minutes. After the attachment, as shown in FIG. 17, the jig 140 (FIG. 16) is removed, and the polymer 142 serves as a dielectric layer, an adhesive layer, and a buffer layer for absorbing and buffering thermal stress. Therefore, the polymer 142 solves several problems of the conventional method, such as the high capacitance due to the limit of the thickness of the dielectric layer and the shortened durability of the solder joint between the package and the substrate. [0032] After the fixing jig 140 is removed, as shown in FIG. 18, the polymer 142 is removed from the via holes 136 of the rerouting film 130 to expose the metal bumps 110. If the wafer 100 does not have the metal bump 110 thereon, the polymer 142 is removed until the chip pads 104 are exposed. Commercial materials are available for stripping the polymer 142 from the via holes without damaging the rerouting film 130. [0033]FIG. 19 illustrates the electrical connection between the metal pattern layer 134 and the metal bump 110. The via holes 136 are filled with solder to form soldering parts 144, which electrically connect the metal pattern layer 134 to the respective metal bumps 110. In the case without the metal bump 110, the soldering parts 144 electrically connected the metal pattern layer 134 to the respective chip pads 104. [0034] The dipping in a molten solder bath that was described with reference to the FIG. 8 can form the soldering part 144 in the via hole 136. As shown in FIG. 19, the dipping method also forms solder layers 146 on the terminal pads 138. The molten solder does not stick to other parts of the rerouting film 130. Optionally, a CVD process can form a metal coating on the inside walls of the via holes prior to the dipping. Such metal coating can be formed, for example, by depositing of metal on the whole surface of the rerouting film and then patterning the metal layer. However, the metal coating by CVD has several drawbacks in that the coating requires an adhesion barrier for the polyimide and additional processing steps, which increase production costs. [0035] Solder paste application and reflow can also form the soldering parts 144. According to this method, a dispenser (not shown) applies a solder paste in the via holes 136 and on the terminal pads 138, and then a conventional reflow in a furnace forms the soldering parts 144 and the solder layer 146 by melting and solidifying the solder paste. A conventional screen-printing method can also apply the solder paste in the via holes 136 and on the terminal pads 138. [0036] After the formation of the soldering parts 144 and the solder layers 146, external terminals 148 are formed on the respective solder layers 146 (or the terminal pads 138). However, prior to the formation of the external terminals 148, a conventional wafer back-lapping can grind the back side of the wafer 100 to reduce its thickness, as shown in FIG. 20. A dotted line indicates the part that the grinding removes. This wafer-grinding is an optional process, and can be performed with the wafer of FIG. 17. [0037] Regarding FIG. 21, a known metal bump formation method, such as solder ball attaching, can form the external terminals 136. Instead of the solder layer 146, known chemical vapor deposition can form another metal layer on the terminal pads 138 to promote the adhesion between the external terminals 148 and the terminal pads 138. In addition, a passivation layer 150 may be further formed on the soldering parts 144 by dispensing a liquid polymer, protecting the soldering parts 144 from the environment. [0038] Finally, as shown in FIG. 22, the wafer 100 and the rerouting film 130 are separated into individual packages 160 along the scribe lines (not shown) by a known sawing process. In the package 160, the chip pads 104 electrically connect to the respective external terminals 148 through the metal pattern layer 134 of the rerouting film [0039] FIGS. 23 to 28 illustrate a method for manufacturing a chip scale package according to an embodiment of the present invention. This method is basically the same as the method described with reference to FIGS. 5 to 22, except that individual integrated circuit chips that passed electrical test, instead of a wafer, are attached to the rerouting film. Accordingly, the process steps of the FIGS. 23 to 28 are identical to those of FIGS. 5 to 22. FIG. 23 depicts supplying a polymer 170 on the rerouting film 130, and FIG. 24 depicts attaching the individual chips 180 to the rerouting film 130. FIG. 25 illustrates the partial removal of the polymer 170, and FIG. 26 illustrates the formation of soldering parts 190. [0040] Regarding to FIG. 27, the back side of the chip 180 is ground, and the external terminals are formed. FIG. 28 shows the separation of the rerouting film 130 to produce individual packages 200. [0041] As described above, the present invention has several feature that can solve the problems of the prior art. First, the rerouting film reduces the number of processes performed directly on the wafer, thereby reducing potential damage to the integrated circuit chips. Second, the polymer layer between the wafer (or the chips) and the rerouting film serves as a dielectric layer and/or a buffer layer for absorbing and alleviating the thermal stress and reducing the capacitance of the package. Third, the polymer coating on the solder filling in the via holes of the rerouting film can improve the reliability of the solder filling. [0042] Although the invention has been described with reference to particular embodiments, the description is only an example of the inventor's application and should not be taken as limiting. Various adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as defined by the following claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6635963 *Feb 5, 2002Oct 21, 2003Oki Electric Industry Co., Ltd.Semiconductor package with a chip connected to a wiring substrate using bump electrodes and underfilled with sealing resinUS6867069Aug 1, 2003Mar 15, 2005Oki Electric Industry Co., Ltd.Semiconductor package with a chip connected to a wiring substrate using bump electrodes and underfilled with sealing resinUS7244635 *Jan 20, 2004Jul 17, 2007Rohm Co., Ltd.Semiconductor device and method of manufacturing the sameUS7638363Mar 9, 2007Dec 29, 2009Chippac, Inc.Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packagesUS7732254May 3, 2007Jun 8, 2010Chippac, Inc.Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packagesUS7759803Jun 13, 2007Jul 20, 2010Rohm Co., Ltd.Semiconductor device and method of manufacturing the sameUS7763977Nov 20, 2007Jul 27, 2010Shinko Electric Industries Co., Ltd.Semiconductor device and manufacturing method thereforUS7935572Apr 26, 2010May 3, 2011Chippac, Inc.Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packagesUS8049343Jun 4, 2010Nov 1, 2011Rohm Co., Ltd.Semiconductor device and method of manufacturing the sameUS8143100 *Aug 31, 2007Mar 27, 2012Chippac, Inc.Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packagesEP1926144A2Nov 23, 2007May 28, 2008Shinko Electric Industries Co., Ltd.Semiconductor device and manufacturing method thereof* Cited by examinerClassifications U.S. Classification438/113, 257/E23.069, 257/E23.067International ClassificationH01L23/498, H01L23/31, H01L23/538Cooperative ClassificationH01L2224/11822, H01L2224/131, H01L2924/01022, H01L23/49816, H01L2924/01079, H01L2924/12044, H01L2224/97, H01L2924/14, H01L2924/30105, H01L2924/01023, H01L24/97, H01L2924/15184, H01L23/3114, H01L2924/01027, H01L2924/01002, H01L2924/01046, H01L24/16, H01L2224/16237, H01L2924/01033, H01L2924/01078, H01L2924/01029, H01L24/12, H01L2924/01006, H01L2924/014, H01L2224/1134, H01L2924/01024, H01L24/11, H01L2924/15311, H01L2924/00013, H01L23/49827, H01L2924/0103, H01L2224/0231, H01L2224/9202, H01L2924/01074, H01L2224/92144European ClassificationH01L24/97, H01L24/11, H01L24/12, H01L24/16, H01L23/498E, H01L23/498C4, H01L23/31H1Legal EventsDateCodeEventDescriptionSep 24, 2013FPAYFee paymentYear of fee payment: 12Oct 1, 2009FPAYFee paymentYear of fee payment: 8Sep 30, 2005FPAYFee paymentYear of fee payment: 4Jan 12, 2000ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KWON, YONG HWAN;KANG, SA YOON;KIM, NAM SEOG;AND OTHERS;REEL/FRAME:010491/0943;SIGNING DATES FROM 19991213 TO 19991214Owner name: SAMSUNG ELECTRONICS CO., LTD. 416, MAETAN-DONG, PARotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google