Source: https://patents.google.com/patent/US20020105088
Timestamp: 2018-03-22 23:46:29
Document Index: 39732042

Matched Legal Cases: ['art 208', 'art 208', 'art, 208', 'art 208', 'art 208', 'art.\n12', 'art.\n17', 'art.\n19']

US20020105088A1 - Semiconductor device having multilayer interconnection structure and manfacturing method thereof - Google Patents
Semiconductor device having multilayer interconnection structure and manfacturing method thereof Download PDF
US20020105088A1
US20020105088A1 US09999104 US99910401A US20020105088A1 US 20020105088 A1 US20020105088 A1 US 20020105088A1 US 09999104 US09999104 US 09999104 US 99910401 A US99910401 A US 99910401A US 20020105088 A1 US20020105088 A1 US 20020105088A1
US09999104
US6836019B2 (en )
A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a line width of an entrance portion adjacent to the surface of the ILD layer larger than the line width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a line width larger than that of the second contact stud. The second contact stud has a line width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad. The entrance portion of the first contact stud has a line width about 30-60% larger than that of the contacting portion.
In multilayer interconnections, active devices and interconnections have a structure in which layers are stacked, and each layer is connected by an interlevel, or interlayer, connection path such as a “plug” or “stud”. Also, a “landing pad” or “tab” for assisting the alignment of the plug is formed on an underlying layer to serve as a target for a plug. Further, the landing pad is connected to an underlying circuit or interconnection, and its surface area is formed to be larger than that of the underlying circuit or interconnection. This results in a larger tolerance of the target for the plug. However, a conventional landing pad or tap assists the alignment of the plug, and due to the line width being larger than that of the stud (or plug), there is a high risk that a short-circuit may occur between neighboring circuit patterns. Thus, at present, instead of using the landing pad, a technology in which self-aligned metal interconnections are formed by an etch stopper has been suggested.
[0006]FIG. 1 is a sectional view of a conventional multilayer metal interconnection structure including a stud and an etch stopper, as disclosed in U.S. Pat. No. 5,891,799. Referring first to FIG. 1, a metal interconnection 102 is formed on a semiconductor substrate 100. A first interlevel dielectric (ILD) layer 104 composed of silicon dioxide (SiO2) and a first etch stopper 106 composed of silicon nitride (Si3N4) are sequentially formed on the semiconductor substrate 100 on which the metal interconnection 102 is formed. Next, lower stud holes 108 a and 108 b are formed by patterning the first etch stopper 106 and the first ILD layer 104 to expose the metal interconnection 102 and the semiconductor substrate 100. Next, the lower stud holes 108 a and 108 b are filled with a metal material to form lower studs 110 a and 110 b. A second ILD layer 112 and a second etch stopper 114 are sequentially formed on the resultant of the semiconductor substrate 100 on which the lower studs 110 a and 110 b are formed. Next, upper stud holes 116 a and 116 b are formed by etching the second etch stopper 114 and the second ILD layer 112 to expose the lower studs 110 a and 110 b. Here, during an etching process for forming the upper stud holes 116 a and 116 b, the first etch stopper 106 serves as an etching reference. Next, upper studs 118 a and 118 b are formed in the upper stud holes 116 a and 116 b.
However, the following problems arise in a conventional multilayer interconnection structure. First, in the mentioned prior art, a landing pad is not used. Thus, even though the first etch stopper 106 is used, there is a high risk that misalignment between the lower studs 110 a, 110 b and the upper studs 118 a, 118 b may occur. Meanwhile, when the landing pad is used, as described above, the distance between patterns decreases. Thus, a short-circuit can readily occur between neighboring conductive patterns.
To address the above limitations, it is a first objective of the present invention to provide a semiconductor device capable of preventing short-circuits between neighboring conductive patterns in highly integrated circuits.
[0030]FIG. 1 is a sectional view of a conventional semiconductor device having a multilayer interconnection structure including an etch stopper;
[0031]FIG. 2 is a sectional view of a semiconductor device having a multilayer interconnection structure according to an embodiment of the present invention;
[0032]FIGS. 3A through 3G are sectional views for each process of the multilayer interconnection structure of a memory device including a cell region and a peripheral region according to another embodiment of the present invention;
[0033]FIGS. 4A and 4B are sectional views for each process of the multilayer interconnection structure of the memory device including the cell region and the peripheral region according to another embodiment of the present invention.
[0036]FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention, and the principles of the present invention will be described with reference to FIG. 2. A conductive pattern 202 is initially formed on a semiconductor substrate 200, and a first interlevel dielectric (ILD) layer 204 is formed on the conductive pattern 202. Lower stud holes 206 a and 206 b are formed in the first ILD layer 204 to expose portions of the conductive pattern 202 and the semiconductor substrate 200, and the lower stud holes 206 a and 206 b are filled with a conductive material, thereby forming lower studs 208 a and 208 b. Here, one lower stud 208 a of the lower studs 208 a and 208 b has the line width of an upper portion (hereinafter, an entrance part 208 a-1) adjacent to the surface of the first ILD layer 204 larger than the line width of a lower portion (hereinafter, a contacting part 208 a-2) adjacent to the semiconductor substrate 200. Preferably, the line width of the upper, entrance part, 208 a-1 is 30%, more preferably, 30-60% larger than that of the lower, contacting part 208 a-2. The lower stud 208 a can be formed to have, for example, a “T”-shaped cross-section. Here, the entrance part 208 a-1 of the lower stud 208 a is formed in the first ILD layer 204 and later serves as a landing pad during subsequent processes.
Meanwhile, the other lower stud 208 b has the line width of a contacting part that is entirely the same as that of the an entrance part. A landing pad 210 formed of a conductive layer is formed on the lower stud 208 b. As well-known, the landing pad 210 has a line width larger than that of the lower stud 208 b.
An etch stopper 216 is formed on the surface and sidewalls of the landing pad 210. The etch stopper 216 includes a first etch stopper 212 formed on the surface of the landing pad 210 and a second etch stopper 214 formed of a spacer on both sidewalls of the landing pad 210.
Typical applications of the present invention will be realized based on the drawings of FIGS. 3A through 3G. Here, FIGS. 3A through 3G are sectional views for each process of the multilayered interconnection structure of a memory device including a cell region and a peripheral region according to another embodiment of the present invention. In the drawings, “X” directions denote, for example, bit line-extended directions, and “Y” directions denote, for example, word line-extended directions.
Next, first stud holes 312 a and 312 b are formed by patterning a portion of the first ILD layer 310. Here, the first stud hole 312 a formed on the cell region 400 a is formed so that the selected contact plugs 309 may be exposed. The first stud hole 312 b formed on the peripheral region 400 b is formed to a predetermined depth of the first ILD layer 310, and the junction regions 308 are not exposed by the first stud hole 312 b. Here, the peripheral region 400 b on which the first stud hole 312 b is formed, may be a region on which a sense amplifier in which circuits are closely arranged is formed. Here, the first stud hole 312 b formed on the peripheral region 400 b has a line width larger than that of the first stud hole 312 a formed on the cell region 400 a. Preferably, the depth of the first stud hole 312 b is equal to or slightly greater than that of the first stud hole 312 a.
Referring to FIG. 3B, a photoresist pattern 314 is formed on the semiconductor substrate 300 on which the first stud holes 312 a and 312 b are formed, so as to define second stud holes. The photoresist pattern 314 is formed to remain even within the internal sidewalls of the first stud hole 312 b formed in the peripheral region 400 b. Next, the first ILD layer 310 is etched by using the photoresist pattern 314 as a mask, thereby forming second stud holes 316. The second stud holes 316 expose, for example, upper portions of the gate electrodes 306 of the peripheral region 400 b, or the junction region 308. Further, one of the second stud holes 316 is formed in the first stud hole 312 b by the photoresist pattern 314 formed in the first stud hole 312 b. Here, preferably, the line width of the first stud hole 312 b coexisting with the second stud hole 316 is about 30%. More preferably, the line width is 30-60% wider than that of the portion of the second stud hole 316 under the first stud hole 312 b.
Next, as shown in FIG. 3C, the photoresist pattern 314 is removed. Here, a stud hole 317 of a stair-shaped cross-section where the first and second stud holes 312 a and 316 coexist, has a wider entrance part and a narrower contacting part and is referred to as “stair-type stud hole” in this embodiment. Next, contact studs 318 a and 318 b are formed in the first stud hole 312 a, the second stud hole 316, and the stair-type stud hole 317.
Here, the contact studs 318 a and 318 b are preferably formed by the following method. First, an adhesion layer (not shown) is formed on the internal surfaces of the first and second stud holes 312 a, 312 b, and 316 and the surface of the first ILD layer 310. Next, a conductive layer is deposited to fill the insides of the first and second stud holes 312 a, 312 b, and 316. Titanium (Ti), or a stacking layer of titanium (Ti) and titanium nitride (TiN) can be used as the adhesion layer. Here, in the case of using titanium (Ti), a titanium (Ti) layer is deposited to a thickness of about 50-150 Å by a chemical vapor deposition (CVD) method. In the case of using the stacking layer of titanium (Ti) and titanium nitride (TiN), a titanium nitride (TiN) layer is formed by one of the CVD method and an atomic layer deposition (ALD) method and has a thickness of about 250-350 Å. A conductive layer for the contact stud can be formed of, for example, tungsten metal, or titanium nitride (TiN). In the case of using tungsten metal, a tungsten metal layer is formed under a pressure 35-45 Torr and at the temperature of 410-420° C. and is expressed by Equation 1.
Meanwhile, in the case of using titanium nitride (TiN), a titanium nitride (TiN) layer is deposited by the CVD method to a thickness of 1400-1600 Å. Next, the conductive layer and the adhesion layer are chemical mechanical polished until the surface of the first ILD layer 310 is exposed, thereby forming contact studs 318 a and 318 b, and simultaneously providing a planarized surface.
Next, as shown in FIG. 3D, a conductive layer 320 for a bit line and a bit line capping layer 322 are sequentially formed on the first ILD layer 310 on which the contact studs 318 a and 318 b are formed. Here, the conductive layer 320 for a bit line can be formed of, for example, tungsten, and the bit line capping layer 322 can be formed of one of silicon nitride (Si3N4), tantalum oxide (Ta2O5), or aluminum oxide (Al2O3). Here, the bit line capping layer 322 is used as an etch reference layer, that is, an etch stopper, when forming an upper level stud hole. Next, portions of the bit line capping layer 322 and the conductive layer 320 for a bit line are patterned, thereby forming a bit line 324. Here, the bit line 324 located on part of the cell region 400 a and the peripheral region 400 b can be used as a bit line 324 for transmitting data, and the bit line 324 located on the other part of the cell region 400 a and the peripheral region 400 b can be used as interconnections and a landing pad 324 b. However, in this embodiment, a member including the bit line for transmitting data, the peripheral interconnections, and the landing pad 324 b is referred to as a “bit line”. Here, the bit line 324 does not contact the contact stud 318 b formed in the stair-type stud hole 317.
Next, the second ILD layer 328, the bit line 324, and the first ILD layer 310 are sequentially etched to expose the selected contact plug 309 of the cell region 400 a, thereby forming a storage node stud hole 330. The storage node stud hole 330 is self-aligned by the bit line spacer 326 and the bit line capping layer 322 on the bit line 324.
Next, as shown in FIG. 3G, a storage node contact 332 is formed to completely fill the inside of the storage node stud hole 330. Next, a cylinder-shaped electrode 334 is formed on the second ILD layer 328 to contact the storage node contact 332. As a result, a storage node electrode 335 is completed on the cell region 400 a.
Next, a third ILD layer 337 is formed on the second ILD layer 328 on which the storage node electrode 335 is formed. The third ILD layer 337 also has the planarized surface and is formed to be thicker than the height of the storage node electrode 335 so as to completely fill the storage node electrode 335. Also, the third ILD layer 337 also has a silicon oxide component. A planarized layer, or an insulating layer of which the surface is chemical mechanical polished, can be also used as the third ILD layer 337.
Next, upper level studs 340 a and 340 b are formed in the upper level stud hole 339. The upper level studs 340 a and 340 b can be formed by the same method as the mentioned contact studs 318 a and 318 b. Here, the upper level studs 340 a and 340 b contact the contact stud 318 b in the stair-type stud hole 317 having a line width larger than that of the upper level studs 340 a and 340 b, and the bit line 324 for serving as the landing pad, thus misalignment does not occur. Also, the contact stud 318 b in the stair-type stud hole 317 b has a line width large enough to serve as the landing pad and is filled in the first ILD layer 310. The bit line 324 for serving as the landing pad is formed on the first ILD layer 310, thus insulation between two materials (the contact stud 318 b and the bit line 324) can be sufficiently obtained (see Y-direction of FIG. 3G). That is, since the contact stud 318 b and the bit line 324 are formed on different layers, the contact stud 318 b and the bit line 324 do not contact neighboring conductive patterns even if the contact stud 318 b and the bit line 314 are formed to a sufficient line width considering the alignment margin regardless of the neighboring conductive patterns. Next, a metal interconnection 342 is formed on the third ILD layer 337 to contact the upper level studs 340 a and 340 b.
[0061]FIGS. 4A and 4B are sectional views for each process of the multilayer interconnection structure of the memory device including the cell region and the peripheral region according to another embodiment of the present invention. In this embodiment, since the steps of forming the gate electrodes 306, the junction region 308, the contact plug 309 on the semiconductor substrate 300 are the same as in the second embodiment, only the following steps will be described. Further, the same reference numerals are used in the same part of the embodiment as that of the second embodiment.
an interlevel dielectric (ILD) layer formed on the semiconductor substrate;
a first contact stud formed in the ILD layer, the first contact stud having a first width of an entrance portion adjacent an upper surface of the ILD layer larger than a second width of a contacting portion adjacent the semiconductor substrate; and
a second contact stud spaced apart from the first contact stud and formed in the ILD layer.
2. The semiconductor device of claim 1, further comprising a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a width larger than that of the second contact stud.
3. The semiconductor device of claim 2, wherein the second contact stud has a width that is substantially the same at entrance and contacting portions.
4. The semiconductor device of claim 2, further comprising at least one lateral spacer formed of an etch stopper material on sidewalls of the landing pad.
5. The semiconductor device of claim 2, further comprising an etch stopper formed on the landing pad.
6. The semiconductor device of claim 1, wherein the entrance portion of the first contact stud has a width about 30-60% larger than that of the contacting portion.
a first contact stud formed in the ILD layer, having a first line width of an entrance portion adjacent an upper surface of the ILD layer larger than a second line width of a contacting portion adjacent the semiconductor substrate; and
a second contact stud spaced apart from the first contact stud and formed in the ILD layer; and
a landing pad formed on the ILD layer to contact an upper surface of the second contact stud, the landing pad having a line width larger than that of the second contact stud.
8. The semiconductor device of claim 7, wherein the second contact stud has a line width that is approximately the same at both a lower contacting portion and an upper entrance portion.
9. The semiconductor device of claim 7, further comprising at least one lateral spacer formed of an etch stopper material on sidewalls of the landing pad.
10. The semiconductor device of claim 7, further comprising an etch stopper formed on the landing pad.
11. The semiconductor device of claim 7, wherein the entrance part of the first contact stud has a line width about 30-60% larger than that of the contacting part.
12. The semiconductor device of claim 7, further comprising a plurality of gate electrodes arranged adjacent to each other between the semiconductor substrate and the ILD layer, self-aligned plugs formed between the gate electrodes, and a third contact stud contacting the self-aligned plugs formed in the ILD layer.
13. The semiconductor device of claim 12, wherein a depth of the entrance portion of the first contact stud is equal to or slightly greater than that of the third contact stud.
14. The semiconductor device of claim 13, wherein the semiconductor substrate is defined by a cell region and a peripheral region, the third contact stud is formed in the cell region, and the first contact stud is formed in the peripheral region.
a first contact stud formed in the ILD layer, having a first line width of an entrance part adjacent to a surface of the ILD layer larger than a second line width of a contacting part adjacent to the semiconductor substrate; and
a second contact stud spaced apart from the first contact stud and formed in the ILD layer;
a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a line width larger than that of the second contact stud; and
an etch stopper for covering only the top and side of the landing pad.
16. The semiconductor device of claim 15, wherein the second contact stud has a line width that is substantially the same in an upper entrance part and a lower contacting part.
17. The semiconductor device of claim 15, wherein the etch stopper includes a first etch stopper formed on the landing pad and a second etch stopper formed of a lateral spacer on sidewalls of the landing pad.
18. The semiconductor device of claim 15, wherein the entrance part of the first contact stud has a line width about 30-60% larger than that of the contacting part.
19. The semiconductor device of claim 15, further comprising a plurality of gate electrodes arranged adjacent to each other between the semiconductor substrate and the ILD layer, self-aligned plugs formed between the gate electrodes, and a third contact stud contacting the self-aligned plugs formed in the ILD layer.
20. The semiconductor device of claim 19, wherein a depth of the entrance part of the first contact stud is equal to or slightly greater than that of the third contact stud.
21. The semiconductor device of claim 20, wherein the semiconductor substrate is defined by a cell region and a peripheral region, the third contact stud is formed in the cell region, and the first contact stud is formed in the peripheral region.
22. A method for manufacturing a semiconductor device, the method comprising:
forming an interlevel dielectric (ILD) layer on a semiconductor substrate;
forming a first stud hole in the ILD layer having a line width at an entrance part adjacent to the surface of the ILD layer larger than a line width at a contacting part adjacent to the semiconductor substrate;
forming a second stud hole spaced apart from the first stud hole, in the ILD layer; and
forming first and second contact studs by filling the first stud hole and the second stud hole with a conductive material.
23. The method of claim 22, wherein the step of forming a first stud hole and the step of forming a second stud hole comprise:
forming a plurality of first holes by etching a portion of the ILD layer to a shallower depth than that of the ILD layer; and
forming a plurality of second holes for etching part of the ILD layer positioned under the first hole selected from the plurality of first holes and a portion of the ILD layer on which the plurality of first holes are not formed and exposing the semiconductor substrate.
24. The method of claim 23, wherein the step of forming a second contact stud comprises:
forming a photoresist pattern on the ILD layer on which the plurality of first holes are formed, while covering internal sidewalls of the selected first hole, which exposes other portions of the ILD layer; and
etching the ILD layer to have the shape of the photoresist pattern.
25. The method of claim 23, before the step of forming the ILD layer on the semiconductor, further comprising the step of exposing portions selected from self-aligned contact plugs simultaneously with the step of forming a plurality of first holes by forming gate electrodes and forming the self-aligned contact plugs between the gate electrodes.
26. The method of claim 25, wherein the first holes are formed to a depth equal to or greater than the distance from the surface of the ILD layer to the surface of the contact plugs.
27. The method of claim 22, wherein the step of forming a first stud hole and the step of forming a second stud hole comprise:
forming a plurality of first holes for etching a portion of the ILD layer and exposing a selection region of the semiconductor substrate; and
forming a plurality of second holes having line widths larger than those of the first holes by etching the ILD layer formed on sides of the first holes selected from the plurality of first holes to a predetermined depth.
28. The method of claim 27, wherein, prior to the step of forming the IDL layer on the semiconductor, further comprising exposing portions selected from self-aligned contact plugs simultaneously with the step of forming a plurality of first holes by forming gate electrodes and forming the self-aligned contact plugs between the gate electrodes.
29. The method of claim 28, wherein the second holes are formed to a depth equal to or greater than the distance from the surface of the ILD layer to the surface of the contact plugs.
30. The method of claim 22, following the step of forming first and second contact studs, further comprising the step of forming a conductive landing pad having a line width larger than that of the second contact stud, on the ILD layer to contact the second contact stud.
31. The method of claim 30, after the step of forming a conductive landing pad, further comprising the step of forming an etch stopper to cover the conductive landing pad.
32. The method of claim 31, wherein the step of forming an etch stopper comprises:
forming a first etch stopper on the conductive landing pad; and
forming a second etch stopper formed of a spacer on sidewalls of the landing pad and the first etch stopper.
US09999104 2001-02-08 2001-10-31 Semiconductor device having multilayer interconnection structure and manufacturing method thereof Active US6836019B2 (en)
KR2001-6123 2001-02-08
KR01-6123 2001-02-08
KR20010006123A KR100400033B1 (en) 2001-02-08 2001-02-08 Semiconductor device having multi-interconnection structure and manufacturing method thereof
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US10989930 Division US7510963B2 (en) 2001-02-08 2004-11-16 Semiconductor device having multilayer interconnection structure and manufacturing method thereof
US20020105088A1 true true US20020105088A1 (en) 2002-08-08
US6836019B2 US6836019B2 (en) 2004-12-28
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US09999104 Active US6836019B2 (en) 2001-02-08 2001-10-31 Semiconductor device having multilayer interconnection structure and manufacturing method thereof
US10989930 Active 2021-12-22 US7510963B2 (en) 2001-02-08 2004-11-16 Semiconductor device having multilayer interconnection structure and manufacturing method thereof
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YANG, WON-SUK;KIM, KI-NAM;JEONG, HONG-SIK;REEL/FRAME:012353/0788;SIGNING DATES FROM 20010927 TO 20010928