Source: https://patents.justia.com/patent/5550770
Timestamp: 2019-10-21 13:32:22
Document Index: 30059370

Matched Legal Cases: ['Art 1', 'Art 2', 'Art 3', 'Art 1', 'Art 2', 'Art 3', 'Art 1', 'Art 3']

US Patent for Semiconductor memory device having ferroelectric capacitor memory cells with reading, writing and forced refreshing functions and a method of operating the same Patent (Patent # 5,550,770 issued August 27, 1996) - Justia Patents Search
Justia Patents FerroelectricUS Patent for Semiconductor memory device having ferroelectric capacitor memory cells with reading, writing and forced refreshing functions and a method of operating the same Patent (Patent # 5,550,770)
Jun 2, 1995 - Hitachi, Ltd.
The semiconductor memory system of this embodiment is adapted to write/read data at the unit of 8 bits. The memory array portion is provided with 2.times.8 memory blocks as a representative. Specifically, the memory array portion is provided with eight memory blocks in the row direction and with two memory blocks in the column direction. The eight memory blocks arranged in the row direction are made to correspond to eight data terminals DIO-0 to DIO-7. In FIG. 1, four of the memory blocks are shown by way of example.
The remaining seven data line terminals D1 to D7 are corresponded to by the Y-selects and write/read circuits having constructions similar to the aforementioned ones. In FIG. 1, there are representatively shown a Y-select 7 and a write/read circuit WRC7, which correspond to the data terminal DIO-7. The write circuit includes a data input buffer DIB, a data in-latch DIL and a write amplifier WA, and the read circuit includes a sense amplifier SA, a data out-latch DOL and a data output buffer DOB. The data to be fed from the data out-latch DOL to the data in-latch DIL are used for the rewrite due to the destructive read. A MOSFET Q0 is a switch MOSFET for feeding the earth potential of the circuit to a common data line connected with the input of the sense amplifier SA and the output of the write amplifier WA in response to a timing signal .phi..
A control circuit CONT produces the outputs of the write voltage of Vo and the half write voltage of Vo/2 in response to a supply voltage Vcc and the timing signal .phi. or the like in response to a write/read signal R/W. In addition, the control circuit CONT is fed, if necessary, with a chip select signal and a forced refreshing (or polling) high voltage, as will be described hereinafter. On the other hand, in case a block accessing operation or an automatic write verifying function is to be added, the control circuit CONT is equipped with a logic circuit for the sequence control.
At Step 1, the selected data line is fed with the precharge voltage such as the earth potential of the circuit. At this time, the first word line WB0 is set to the high selection level, and the switch MOSFETs Q0 to Q7 are turned ON. As a result, the sub-data lines d0 to d7 of the selected unit memory circuit are fed with the precharge voltage of 0 V or the like. This precharge voltage is fed by the MOSFET Q0 which is made receptive of the timing signal .phi. of FIG. 1. At this time, the second word lines W00 to W07 are fed with the potential of Vo/2 no matter whether they might be selected or unselected. Although not shown in FIG. 6, the unselected data lines of each memory block are fed with the voltage of Vo/2 or the like.
Word Line/      Inven-  Prior    Prior Prior
Data Line       tion    Art 1    Art 2 Art 3
Sel/Unsel   N-1     N-1    N-1   N-1
Block   Unsel/Sel   m-1     M-1    0     m-1
Unsel/Unsel 0       NM-l   0
Sel/Unsel   --      --     --    --
Block   Unsel/Sel   --      --     --    --
Unsel/Unsel 0       --     --    #
"Sel": Selected; "Unsel": Unselected; and "#": N.multidot.m(M/m1).
Maximum Stress of the Invention=(N-1)+(m-1) (1);
Maximum Stress of the Prior Art 1=NM-1 (2);
Maximum Stress of the Prior Art 2=N-1 (3);
Maximum Stress of the Prior Art 3=1+(m-1)/(N-1)+Nm/(N-1).multidot.(M/m-1)(4).
Ratio of the Invention=1+(m-1)/(N-1) (5);
Ratio of the Prior Art 1=(NM-1)/(N-1) (6);
Ratio of the Prior Art 3=1+(m-1)/(N-1)+Nm/(N-1).multidot.(M/m-1)(7).
If the number of the aforementioned data lines y0 to yn is exemplified by 32, one block is given a memory capacity of 8.times.32=256 bits. If the eight memory blocks 0 to 7 juxtaposed in the word line direction are simultaneously selected, each block is given a memory capacity of 256 bytes.
At Step (4), the aforementioned sense level is checked. If (OK) a predetermined sense level is obtained, the routine transfers to Step (6), at which it is decided whether or not the corresponding block has been written to the final address. If the predetermined sense level is not obtained, a rewrite is carried out at Step (5). At this time, the write voltage Vo remains as it were, and the writing operation is carried out again under the same condition of the writing time tpw. This writing operation under the same condition is reasoned because its shortage comes from the fact that the writing pulse is not sufficiently applied to the ferroelectric capacitors due to the noise or the like at the writing time. Specifically, the elements having defective characteristics such as the defective ferroelectric capacitors are turned defective even if they are rewritten many times, so that the writing verification makes no substantial meaning. These defects can be omitted by other tests, and their relief cannot be achieved unless it resorts to a redundancy circuit. Considering the more or less deterioration or dispersion of the characteristics of the ferroelectric capacitors, the rewriting time may be increased to (tpw+.alpha.).
When the memory accessing is started, at Step (1), the access number N is stored, and the writing time is set tpwo. The subsequent operations of Step (2) to Step (7) are similar to those of the aforementioned write verification of FIG. 32, and their description will be omitted. At Step (8), the rewriting operation is carried out by incrementing the write by number+1 when the result of the rewrite check is No Good (at this time, the writing time may be increased to (tpw+.alpha.). At Step (9), it is decided whether or not a predetermined number N is exceeded (or whether or not the writing time reaches a maximum value Tpwo). At the probing step, what causes a defective even if the predetermined number N is exceeded or if the maximum time Tpwo is reached is decided, at Step (10), as a defective of the LSI (i.e., semiconductor memory system).
If it is decided at Step (9) that the writing operation is defective even if the allowable number N is reached, the polling number k is set to (k+1) at Step (10). If it is found at Step (11) that the polling number k is 0, the polling operation is carried out at Step (12). Specifically, the writing voltage is set to (Vo+.alpha.) to execute the aforementioned polling (or forced refreshing) operation. After this, the number n is reset to 0 at Step (13), and the routine is returned to Step (3), i.e., the similar writing operation. The operation of this Step (3) is omitted if the writing check of Step (5) resorts to the nondestructive reading operation. The remaining decisions and operations are similar to the aforementioned ones of FIGS. 34 and 35, and their description will be omitted.
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Patent number: 5550770
Inventor: Kenichi Kuroda (Tachikawa)
Application Number: 8/458,159