Source: https://patents.google.com/patent/US8745299B2/en
Timestamp: 2018-11-13 16:39:30
Document Index: 14549045

Matched Legal Cases: ['art 10', 'art 10', 'art 1', 'art 1', 'art 3', 'art 3', 'art 1', 'art 1', 'art 2', 'art 2', 'art 2', 'art 2', 'art 1', 'art 1', 'art 2', 'art 2']

US8745299B2 - Combination non-volatile memory and input-output card with direct memory access - Google Patents
Combination non-volatile memory and input-output card with direct memory access Download PDF
US8745299B2
US8745299B2 US13268287 US201113268287A US8745299B2 US 8745299 B2 US8745299 B2 US 8745299B2 US 13268287 US13268287 US 13268287 US 201113268287 A US201113268287 A US 201113268287A US 8745299 B2 US8745299 B2 US 8745299B2
US13268287
US20120030398A1 (en )
This application is a continuation of U.S. patent application Ser. No. 10/302,009, filed Nov. 21, 2002 now U.S. Pat. No. 8,037,229, which is hereby incorporated by reference.
FIG. 8 is a table showing an exemplary command structure; and
FIG. 9 shows a memory system utilizing multiple memory card sockets with multiple command/response lines connected to them.
An implementation within the exemplary SD card embodiment will now be described in more detail. To make the discussion more concrete, various commands, structures, and registers are referred to that are explained more fully in “The MultiMediaCard System Specification” versions 2.11 and 2.2 and U.S. patent application Ser. Nos. 09/185,649, 09/186,064, and 09/641,023, all of which application are incorporated by reference above.
As also noted above, several exemplary embodiments were referenced in conjunction with documents that are incorporated by reference. One such document that is incorporated by reference is U.S. patent application Ser. No. 09/641,023, and an embodiment shown in that application as FIG. 4 is reproduced herein as FIG. 9. As shown in FIG. 9, host 51′ includes a host controller 52 that interfaces differently with the memory cards' command/response lines. Separate lines 71, 73 and 75 are connected to pin 2 of respective sockets 53, 55 and 57. Each of the separate command/response lines 71, 73 and 75 is one output of switching logic 65 which operates to switch a single command/response line 67 of the controller 52 among the individual lines 71, 73 and 75 in response to a control signal from the host in a circuit 69. More details of that embodiments are described in the '023 application.
The embodiment shown in FIG. 9 can be used with the other embodiments described herein to provide a system comprising a host controller, a first controller, and a second controller, and a bus configured to exchange data and commands between the host controller and the first and second controllers. The first and second controllers can be configured to perform a direct memory access type transfer using the bus in response to a command from the host controller to perform the direct memory access type transfer, and the host controller can be operative to provide a clock signal to the bus during the direct memory access type transfer. The first and second controllers can both be part of an electronic circuit card. Also, the first controller can comprise a memory controller, and the second control can comprise an input-output controller. The system can further comprise a memory module in communication with the memory controller, wherein the memory module includes a non-volatile mass data storage portion, and an input-output module in communication with an input-output controller, the input-output module operative to communicate data between the input-output module and an external device, wherein the direct memory access type transfer is of data between the input-output module and the mass data storage portion. The bus can comprise an SD bus. Also, once the host controller provides the command to perform the direct memory access type transfer, the first and second controllers can perform the direct memory access type transfer independently of the host controller aside from the host controller providing the clock signal to the bus. In another embodiment, the system can comprise a host controller and a bus coupled to the host controller and configured for coupling to two or more controllers. The two or more controllers can include one or more input-output controllers and one or more memory controllers. Additionally, the bus can be further configured to perform data exchange between the two or more controllers and also configured to provide a clock signal during direct memory access type transfer between the two or more controllers.
a bus configured to exchange data and commands between the host controller and the first and second controllers, wherein the first and second controllers are configured to perform a direct memory access type transfer using the bus in response to receiving a command directly from the host controller to perform the direct memory access type transfer;
wherein host controller is operative to provide a clock signal to the bus during the direct memory access type transfer.
2. The system of claim 1, wherein the first and second controllers are both part of an electronic circuit card.
3. The system of claim 1, wherein the first controller comprises a memory controller and the second control comprises an input-output controller.
4. The system of claim 1, wherein the bus comprises an SD bus.
5. The system of claim 1, wherein once the host controller provides the command to perform the direct memory access type transfer, the first and second controllers perform the direct memory access type transfer independently of the host controller aside from the host controller providing the clock signal to the bus.
a memory module in communication with the memory controller, wherein the memory module includes a non-volatile mass data storage portion; and
an input-output module in communication with an input-output controller, the input-output module operative to communicate data between the input-output module and an external device;
wherein the direct memory access type transfer is of data between the input-output module and the mass data storage portion.
a bus coupled to the host controller and configured for coupling to two or more controllers, wherein the two or more controllers includes one or more input-output controllers and one or more memory controllers;
wherein the bus is further configured to perform data exchange between the two or more controllers and also configured to provide a clock signal during direct memory access type transfer between the two or more controllers; and
wherein the two or more controllers are configured to perform a direct memory access type transfer using the bus in response to receiving a command directly from the host controller to perform the direct memory access type transfer.
8. The system of claim 7, wherein the two or more controllers are both part of an electronic circuit card.
a memory module comprising the one or more memory controllers and a non-volatile mass data storage portion; and
an input-output module comprising the one or more input-output controllers;
10. The system of claim 7, wherein the bus comprises an SD bus.
11. The system of claim 7, wherein once the host controller provides a command to perform the direct memory access type transfer, the at least two controllers perform the direct memory access type transfer independently of the host controller aside from the host controller providing the clock signal to the bus.
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US10302009 US8037229B2 (en) 2002-11-21 2002-11-21 Combination non-volatile memory and input-output card with direct memory access
US13268287 US8745299B2 (en) 2002-11-21 2011-10-07 Combination non-volatile memory and input-output card with direct memory access
US10302009 Continuation US8037229B2 (en) 2002-11-21 2002-11-21 Combination non-volatile memory and input-output card with direct memory access
US20120030398A1 true US20120030398A1 (en) 2012-02-02
US8745299B2 true US8745299B2 (en) 2014-06-03
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KR (1) KR20050110609A (en)
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