Source: http://www.google.com/patents/US7840962?dq=7245279
Timestamp: 2017-09-19 16:38:30
Document Index: 712255922

Matched Legal Cases: ['Application No. 11', 'Application No. 200580032344', 'Application No. 11', 'Application No. 11', 'Application No. 2007', 'Application No. 2007', 'Application No. 200580032344', 'Application No. 11']

Patent US7840962 - System and method for controlling switching between VMM and VM using ... - Google Patents
In one embodiment, a method includes transitioning control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a VMM timer indicator is set to an enabling value, and identifying a VMM timer value configured by the VMM. The method further includes periodically comparing a...http://www.google.com/patents/US7840962?utm_source=gb-gplus-sharePatent US7840962 - System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time
Publication number US7840962 B2
Application number US 10/956,239
Also published as CN100514297C, CN101027640A, DE112005002360T5, US20060075402, WO2006039202A2, WO2006039202A3
Publication number 10956239, 956239, US 7840962 B2, US 7840962B2, US-B2-7840962, US7840962 B2, US7840962B2
Inventors Gilbert Neiger, Steven M. Bennett, Erik Cota-Robles, Sebastian Schoenberg, Clifford D. Hall, Dion Rodgers, Lawrence O. Smith, Andrew V. Anderson, Richard A. Uhlig, Michael Kozuch, Andy Glew
Patent Citations (249), Non-Patent Citations (62), Referenced by (9), Classifications (13), Legal Events (3)
US 7840962 B2
An example of a time reference source is the timestamp counter (TSC) used in the instruction set architecture (ISA) of the Intel® Pentium® 4 (referred to herein as the IA-32 ISA). The TSC is a 64-bit counter that is set to 0 following the hardware reset of the processor, and then incremented every processor clock cycle, even when the processor is halted by the HLT instruction. The TSC cannot be used to generate interrupts. It is a time reference only, useful to measure time intervals. The IA-32 ISA provides an instruction (RDTSC) to read the value of the TSC and an instruction (WRMSR) to write the TSC. When WRMSR is used to write the timestamp counter, only the 32 low-order bits may be written; the 32 high-order bits are cleared to 0.
An event causing a VM exit may or may not require the execution of an “event handling” procedure. The event handling procedure refers to event reporting that changes control flow of the code executing on the processor even though no branches requiring such a change exist in the code. Event reporting is typically performed when an event is an exception or an interrupt and may require saving the state of the running code (e.g., on a stack), locating an interrupt vector by traversing a redirection structure (e.g., the interrupt descriptor table (IDT) in the instruction set architecture (ISA) of the Intel® Pentium® 4 (referred to herein as the IA-32 ISA)), loading the state of the event handler, and starting execution in the new code. When an exception or interrupt occurs during the operation of the VM 102 or 114, and this exception or interrupt should be handled by the VMM 112 (e.g., an I/O completion interrupt for an I/O operation that was not initiated by or on behalf of the running VM 102 or 114), the event handling procedure is executed after exiting the running VM 102 or 114 (i.e., transitioning control to the VMM 112).
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JP2001282558A Title not available
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U.S. Classification 718/1, 718/108, 718/104, 714/34, 714/15, 718/100, 718/102, 714/2
International Classification G06F9/46, G06F11/00, G06F9/455
Cooperative Classification G06F9/45558
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NEIGER, GILBERT;BENNETT, STEVEN M.;COTA-ROBLES, ERIK;ANDOTHERS;REEL/FRAME:015867/0795