Source: http://www.google.com/patents/US8045407?dq=inassignee:doubleclick
Timestamp: 2014-03-16 19:31:46
Document Index: 361587689

Matched Legal Cases: ['Application No. 10176311', 'Application No. 10175885', 'Application No. 10177771', 'Application No. 05797483', 'Application No. 10175885', 'Application No. 10176311', 'Application No. 10177771', 'Application No. 05022021', 'Application No. 02009032', 'Application No. 05', 'Application No. 2008']

Patent US8045407 - Memory-write timing calibration including generation of multiple delayed ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal path. Timing information is provided...http://www.google.com/patents/US8045407?utm_source=gb-gplus-sharePatent US8045407 - Memory-write timing calibration including generation of multiple delayed timing signalsAdvanced Patent SearchPublication numberUS8045407 B2Publication typeGrantApplication numberUS 12/757,035Publication dateOct 25, 2011Filing dateApr 8, 2010Priority dateSep 15, 2004Also published asEP1820106A2, EP2267603A2, EP2267603A3, EP2267604A2, EP2267604A3, EP2275942A2, EP2275942A3, US7301831, US7480193, US7724590, US8218382, US8363493, US8493802, US20060056244, US20070206429, US20090063890, US20100188911, US20110317504, US20120275237, US20130176800, US20130262757, WO2006031697A2, WO2006031697A3Publication number12757035, 757035, US 8045407 B2, US 8045407B2, US-B2-8045407, US8045407 B2, US8045407B2InventorsFrederick A. WareOriginal AssigneeRambus Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (45), Classifications (16) External Links: USPTO, USPTO Assignment, EspacenetMemory-write timing calibration including generation of multiple delayed timing signalsUS 8045407 B2Abstract A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal path. Timing information is provided by a third output driver to a third signal path. Rising and falling edge transitions of the timing information indicate times at which subsequent symbols of the write data are valid on the signal path. The timing information is delayed with respect to the control information to account for a difference between a time that the control information takes to reach the destination device while traversing the first signal path and a time that the write data takes to reach the destination device while traversing the second signal path.
1. A method of calibrating timing offsets in a memory controller, the memory controller to control the operation of a plurality of memory devices that share a common control signal path, wherein each memory device of the plurality of memory devices includes a dedicated data signal path to receive write data from a corresponding port of the memory controller, the method comprising:
for each memory device of the plurality of memory devices, the memory controller:
generating a plurality of delayed versions of a timing signal that is used to indicate valid write data on the dedicated data signal path, wherein a rising edge transition of the timing signal indicates a valid first symbol of the write data, and a falling edge transition of the timing signal indicates a valid second symbol of the write data; and
generating a selected timing signal of the plurality of delayed versions of the timing signal, such that the write data, the selected timing signal and the write command corresponding to the write data arrive, within a predetermined time period, at each memory device of the plurality of memory devices.
2. The method of claim 1, wherein the plurality of delayed versions of the timing signal include signals that are phase offset from one another by a predetermined phase value.
3. The method of claim 1, further comprising providing a write command on the control signal path such that the write command traverses the control signal path and is sequentially received by each memory device of the plurality of memory devices.
4. The method of claim 3, further comprising for each dedicated data signal path, generating a timing signal that is delayed with respect to the write command based on a selected timing signal of the plurality of delayed versions of the timing signal that compensates for a propagation time difference between the write command propagating on the control signal path and the write data propagating on the dedicated data signal path.
5. The method of claim 4, further comprising providing to the plurality of memory devices, via an address signal path, address information that identifies a memory location to store the write data, wherein the address information is sequentially received by each memory device of the plurality of memory devices.
6. The method of claim 1 wherein generating a plurality of delayed versions of a timing signal comprises:
selecting a first delayed clock signal of the plurality of delayed clock signals to time transmission of the selected timing signal.
7. The method of claim 6 wherein generating a plurality of delayed clock signals comprises:
generating a delayed version of the first clock signal;
generating a control signal based upon a comparison between the first clock signal and the delayed version of the first clock signal; and
controlling an amount of delay for each clock signal of the plurality of delayed clock signals based at least in part on the control signal.
8. The method of claim 7 wherein the delayed version of the first clock signal is delayed with respect to the first clock signal by an interval substantially equal to one period of the first clock signal.
9. The method of claim 7 further comprising delaying transmission of the write data based, at least in part, on an amount of delay between the first clock signal and the first delayed clock signal.
10. The method of claim 9 wherein delaying transmission of the write data comprises:
generating a plurality of delayed versions of the write data based, at least in part, on the plurality of delayed clock signals; and
selecting one of the plurality of delayed versions of the write data, associated with the first delayed clock signal, for output via the dedicated data signal path.
11. A method of calibrating timing offsets in a memory controller that controls the operation of a memory device, wherein the memory controller is coupled to the memory device via a control signal path and a data signal path, the method comprising:
generating a plurality of delayed versions of a timing signal that is used to indicate valid write data on the data signal path, wherein a rising edge transition of the timing signal indicates a valid first symbol of the write data, and a falling edge transition of the timing signal indicates a valid second symbol of the write data; and
generating a selected timing signal of the plurality of delayed versions of the timing signal, such that the write data, the selected timing signal and the write command corresponding to the write data arrive at the memory device within a predetermined time period.
12. The method of claim 11, wherein the plurality of delayed versions of the timing signal include signals that are phase offset from one another by a predetermined phase value.
13. The method of claim 11, wherein the memory device is included in a plurality of memory devices, the method further comprising providing a write command on the control signal path such that the write command traverses the control signal path and is sequentially received by each memory device of the plurality of memory devices.
14. The method of claim 13, further comprising generating a timing signal that is delayed with respect to the write command based on a selected timing signal of the plurality of delayed versions of the timing signal that compensates for a propagation time difference between the write command propagating on the control signal path and the write data propagating on the data signal path.
15. The method of claim 13, further comprising providing to the plurality of memory devices, via an address signal path, address information that identifies a memory location to store the write data, wherein the address information is sequentially received by each memory device of the plurality of memory devices.
16. The method of claim 11 wherein generating a plurality of delayed versions of a timing signal comprises:
17. The method of claim 16 wherein generating a plurality of delayed clock signals comprises:
18. The method of claim 17 wherein the delayed version of the first clock signal is delayed with respect to the first clock signal by an interval substantially equal to one period of the first clock signal.
19. The method of claim 17 further comprising delaying transmission of the write data based, at least in part, on an amount of delay between the first clock signal and the first delayed clock signal.
20. The method of claim 19 wherein delaying transmission of the write data comprises:
selecting one of the plurality of delayed versions of the write data, associated with the first delayed clock signal, for output via the data signal path.
21. A memory control apparatus for controlling the operation of a memory device, wherein the memory control apparatus is to be coupled to the memory device via a control signal path and a data signal path, the memory control apparatus comprising:
means for generating a plurality of delayed versions of a timing signal that is used to indicate valid write data on the data signal path, wherein a rising edge transition of the timing signal indicates a valid first symbol of the write data, and a falling edge transition of the timing signal indicates a valid second symbol of the write data; and
means for generating a selected timing signal of the plurality of delayed versions of the timing signal, such that the write data, the selected timing signal and the write command corresponding to the write data arrive at the memory device within a predetermined time period. Description
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a division of U.S. patent application Ser. No. 12/246,415 filed Oct. 6, 2008 now U.S. Pat. No. 7,724,590 and entitled �Memory Controller with Multiple Delayed Timing Signals,� which is a division of U.S. patent application Ser. No. 11/746,007 filed May 8, 2007 and entitled �Memory Component with Multiple Delayed Timing Signals� (now U.S. Pat. No. 7,480,193), which is a continuation of U.S. patent application Ser. No. 10/942,225 filed Sep. 15, 2004 and entitled �Memory Systems with Variable Delays for Write Data Signals� (now U.S. Pat. No. 7,301,831). Each of the above-referenced U.S. Patent Applications is hereby incorporated by reference.
Another set of signals that couple the memory controller 802 and the memory component(s) 804 are write data signals W and the corresponding data valid or timing signals TW (also referred to as write data valid signals or write data timing signals TW). The write data signals W carry write data information, and are labeled as W0, W1, and W2 to show the write data signals at different points along the signal path between the memory controller 802 and the memory component(s) 804. The timing signals TW carry timing information that indicates when information is valid on the write data signals W. The timing signals are labeled as TW0, TW1, and TW2 to show the timing signals at different points along the signal path between the memory controller 802 and the memory component(s) 804. Note that the label for address/control timing signal TAO is shortened to T0 in the memory system 800, and likewise, the label for write data timing signal TWO is shortened to T0 because the address circuitry 812 and the write data circuitry 822 operate within a common timing domain in the memory controller 802.
The first unit delay element DE 1 in the series of delay elements couples to receive the write data valid signal T0 as an input. The delay line 202 provides a delayed signal having a total delay that is approximately one period of the write data timing signal T0. Therefore, each of the four unit delay elements DE1-DE4 delays the write data valid signal T0 by an amount that is approximately one-fourth of the write data valid signal T0 period.
Furthermore, the variable delay write circuitry of an embodiment also provides increased control over propagation delay differences in write operations to memory components of multiple-slice memory systems. FIG. 6 is a block diagram of a multiple-slice memory system 600 that includes the variable delay write circuitry 150 for generating write data signals and data valid signals with variable delays, under an embodiment. This memory system 600 includes a memory controller 602 coupled to one or more memory components 604-a in memory slice Sa and one or more memory components 604-b in memory slice Sb; while two memory slices are shown the embodiment is not limited to any number of memory slices and/or components. The memory controller 602 drives address/control signals A and address/control valid signals TA to the memory components 604-a/604-b. Difficulty can be found in controlling the difference between the propagation delays of the TA/A signals and the TW/W signals in this multi-slice memory system because the TA/A signals are coupled to two or more memory components (slices). Each slice Sa and Sb therefore sees a different propagation delay on the TA/A signals (tPD-AatPD-Ab) as a result. The delay of the TW/W signal groups (tPD-Wa, tPD-Wb) will however tend to be approximately the same, since these signal groups have a similar routing topology.
The variable delay write circuitry of an embodiment also provides increased control over propagation delay differences in write operations to memory components of multiple-rank memory systems. FIG. 7 is a block diagram of a multiple-rank memory system 700 that includes the variable delay write circuitry 150 for generating write data signals and data valid signals with variable delays, under an embodiment. This memory system 700 includes a memory controller 702 coupled to on or more memory components 704-z in memory rank Rz and one or more memory components 704-y in memory rank Ry; while two memory ranks are shown the embodiment is not limited to any number of memory ranks and/or components. The memory controller 702 drives write data signals W and write data valid signals TW to the memory components 704-z/704-y. Difficulty can be found in controlling the difference between the propagation delays of the TA/A signals and the TW/W signals in this multi-rank memory system because the TW/W signals are coupled to two or more memory components (ranks) Each rank Rz and Ry therefore sees a different propagation delay on the TW/W signals (tPD-Wz, tPD-Wy) as a result. The delay of the TA/A signal groups (tPD-Az, tPD-Ay) will however tend to be approximately the same, since these signal groups have a similar routing topology.
The memory controller 702 of an embodiment can use the variable delay write circuitry 150 to accommodate the different propagation delay values between memory ranks Rz and Ry. The variable delay write circuitry 150 can be programmed to different delay values for each TA/A signal group in order to accommodate the differences in propagation delays between the TW/W signals to the respective memory ranks For example, the variable delay write circuitry 150 operating generally as described above with reference to FIGS. 1-5 transfers address/control signals Az and address/control valid signals TAz to memory component 704-z where signals Az/TAz are delayed using a first variable delay. Likewise, variable delay write circuitry 150 transfers address/control signals Ay and address/control valid signals TAy to memory component 704-y where signals Ay/TAy are delayed using a second variable delay.
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Data Sheet "Direct RDRAM 256/288-Mbit (1M�16/18�16d)" Preliminary Information, Document DL00105 Version 1.1, 72 pages; copyright Aug. 2000.43Wong Derek., et al., "Inserting Active Delay Elements to Achieve Wave Pipelining," IEEE 1989, pp. 270-273.44Yeung et al., 2000, "A 2.4 Gb/s/pin Simultaneous Bidirectional Parallel Link with Per-Pin Skew Compensation," IEEE Journal of Solid-State Circuits, vol. 35, No. 11:1619-1627.45Yoo, Changsik, DRAM Design 3, Samsung Electronics, High Speed DRAM Interface, 2002, 35 pages.* Cited by examinerClassifications U.S. Classification365/194, 710/107, 365/233.1, 711/168, 711/167, 365/191, 365/233.16International ClassificationG11C8/18, G11C7/00, G06F13/00Cooperative ClassificationG06F13/1689, G06F13/4243, G11C8/18, G11C7/1072European ClassificationG06F13/42C3S, G06F13/16D8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google