Source: https://patents.google.com/patent/US20120064666A1/en
Timestamp: 2018-08-14 08:44:29
Document Index: 690382660

Matched Legal Cases: ['Application No. 2009', 'Application No. 2010', 'Application No. 2002', 'art 44', 'art 44', 'art 44', 'art 44', 'art 44', 'art 44', 'art 38', 'art 38', 'art 3', 'art 38', 'art 38', 'art 38', 'art 38', 'art 44', 'art 38', 'art 38', 'arts 34', 'art 38', 'art 38', 'arts 34', 'arts 34', 'art 38', 'art 38', 'art 34', 'art 38', 'art 25', 'art 25', 'art 25', 'arts 34', 'art 33', 'art 38', 'art 34', 'art 33', 'art 38', 'art 38', 'art 25', 'art 25', 'art 25', 'art 34', 'arts 34', 'art 38', 'arts 34', 'arts 35', 'arts 34', 'arts 34', 'arts 35', 'arts 34', 'arts 35', 'arts 34', 'art 38', 'arts 34', 'art 44', 'art 44', 'art 38', 'art 38', 'art 44', 'art 44', 'art.\n4', 'art.\n5']

US20120064666A1 - Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package - Google Patents
Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package Download PDF
US20120064666A1
US20120064666A1 US13299653 US201113299653A US2012064666A1 US 20120064666 A1 US20120064666 A1 US 20120064666A1 US 13299653 US13299653 US 13299653 US 201113299653 A US201113299653 A US 201113299653A US 2012064666 A1 US2012064666 A1 US 2012064666A1
US13299653
Yoichiro Hamada
Shigeru Hosomomi
SH MATERIALS Co Ltd
A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.
This patent application is based upon and claims the benefit of priority of Japanese Patent Application No. 2009-38563 filed on Feb. 20, 2009 and Japanese Patent Application No. 2010-000305 filed on Jan. 5, 2010 the entire contents of which are incorporated herein by reference.
The present invention relates to a manufacturing method of a substrate for a semiconductor package, a manufacturing method semiconductor package, a substrate for a semiconductor package and a semiconductor package.
Conventionally, a semiconductor package manufacturing method where a semiconductor device is sealed with resin is known as disclosed in Japanese Published Patent Application No. 2002-9196 (which is hereinafter called “Patent Document 1”). In the semiconductor manufacturing method, to begin with, a resist pattern layer with a predetermined pattern is formed on a conductive surface of a substrate. Then, conductive metal is electrodeposited on an exposed surface of the conductive surface of the substrate uncovered with the resist pattern layer so that a thickness of the conductive metal is over that of the resist pattern layer, by which a metal layer for semiconductor device mounting and electrode layers are respectively formed so as to have flared portions. After removing the resist pattern layer, a semiconductor device is mounted on the metal layer, and electrodes on the semiconductor device are electronically connected to the electrode layers by bonding wires. Finally, the semiconductor device mounting part is sealed with resin, and the substrate is removed. As a result, back surfaces of the metal layer and electrode layers are exposed, and a semiconductor device in a resin sealed body, a semiconductor package, is obtained.
Accordingly, embodiments of the present invention may provide a novel and useful manufacturing method of a substrate for a semiconductor package, a manufacturing method of a semiconductor package, a substrate for a semiconductor package and a semiconductor package solving one or more of the problems discussed above.
FIG. 1A is a side view of a semiconductor package of a first embodiment of the present invention;
FIG. 1A and FIG. 1B are views showing an example of a finished product of a semiconductor package 100 of a first embodiment of the present invention. FIG. 1A is a side view showing an example of the finished product of the semiconductor package 100. FIG. 1B is a bottom view showing the finished product of the semiconductor package 100.
The metal layer 40 has a side surface shape where the width is the greatest at the top surface 41 and decreases as a level approaches the bottom surface 42, including a tapering slope part 44 such carved inward. By having a side surface shape including the slope part 44, the width of which decreases as the level approaches the bottom surface 42, the sealing resin 80 wraps around the metal layer 40 from a lower side. This prevents a phenomenon where the metal material 40 is pulled out downward from the sealing resin 80, and can improve humidity resistance. Details on these points are described below.
The semiconductor device 60 is a packaged device as an IC (Integrated Circuit) that includes a predetermined electronic circuit on a semiconductor chip. The semiconductor device 60 includes plural terminals 61 for input and output connections to the internal electronic circuit. However, since the distance between the terminals 61 is extremely short, as shown in FIG. 1A and FIG. 1B, by electrically connecting the terminals 61 of the semiconductor device 60 to the electrodes 46 of the semiconductor package 100 with the bonding wires 70, and by using the bottom surfaces 42 of the electrodes 46 as the outer connection terminals 47, connection to an external circuit becomes easier. Here the bonding wire 70 is a connecting wire between the semiconductor device 60 and the electrode 46, and various kinds of metals for wiring are available for the bonding wire 70.
In FIG. 1A, a cross-sectional view of FIG. 1B along the line A-A is shown. As well as FIG. 1A, a cross-sectional view of FIG. 1B along the line B-B or C-C may also show the side surface 43 of the electrode 46 and the semiconductor device mounting area 45 as a shape of the bottom surface 42 which is shorter than the top surface 41 in width, including the tapered slope part 44. In other words, the semiconductor device mounting area 45 and electrode 46 may have side shapes including the slope part 44 not only in a traverse direction, but also in a longitudinal direction shown in FIG. 18. In the following explanations of the embodiment, the explanations are given by citing an example of a side surface of transverse width, but the explanations are applicable to a side surface viewed from a longitudinal direction side in a similar way. Furthermore, since a decrease of a length as well as a decrease of width causes a decrease of circumference, one of the width and length or both of the width and length can be expressed by using a circumference. The expression of the “width” or “length” can be replaced by the “circumference”.
FIG. 2B is a view showing an example of a plating process, one of processes of a manufacturing method of a substrate for a semiconductor package including the metal layer 40. In FIG. 2B, the metal layer 40 shown in FIG. 2A is formed on a conductive substrate 10, surrounded by a resist pattern 22.
In this way, the semiconductor package 100 shown in FIG. 1A and FIG. 1B is manufactured by using a substrate for a semiconductor device 50 at first. Then, in the end, a bottom surface 42 of the metal layer 40 is exposed by removing the substrate 10. A removing method of the substrate 10 may be a method of dissolving the substrate 10 with a solvent that does not affect the sealing resin 80 other than the method of forcibly pulling the substrate 10 apart from the sealing resin 80. If the substrate 10 is removed by tearing, a downward force pulling the metal layer 40 attached to the substrate 10 acts in a tearing removal step. However, by making the metal layer 40 into a shape including the slope part 44 that is decreased in width and circumference toward the bottom as shown in FIG. 2B, the sealing resin 80 exists in a part between the slope part 44 and the substrate 10, surrounding an electrodeposiion area of the metal layer 40 on the substrate 10. This can fix the metal layer 40 so as to hold the metal layer 40 from below.
FIG. 3A is a view showing a substrate 10. The substrate 10 can be made of a variety of materials including metal as long as the materials have a conductive property. The substrate 10, for example, may be made of stainless or copper metals. Also, regarding the thickness of the substrate 10, a variety of thicknesses of the substrate 10 are available according to application. For example, a stainless-steel substrate 0.18 mm thick is available.
Here an exposure energy amount for the top surface is desired to be 70-85% of a rated exposure energy amount for the negative resist. As mentioned above, details of the mask pattern 31 of the glass mask 30 are described below, but in the embodiment, in order to form a resist pattern 22 with a side shape described in FIG. 2B, the mask pattern 31 needs a specific configuration in a border area between the shielding part 38 of the glass mask 30 and the glass substrate 37 exposed part. The mask pattern 31 in the border area including the specific configuration is provided to adjust transmittance of the border area, but there is a concern that the specific configuration be transferred to the resist layer 21 without modification if the exposure is performed in the rated exposure energy amount. Hence, it is desirable to perform the exposure at a lesser exposure energy amount than the rated exposure energy amount, in order to make the border area between the light shielding part 38 and the glass substrate 37 in the glass mask 30 have an intermediate transmittance between the light shielding part 3B and the glass substrate 37, and to form a desired resist pattern 22.
However, in the manufacturing method of the substrate for a semiconductor package 50 of the embodiment, it is desirable to determine the actual developing time t1 seconds so that the developing time coefficient K is in a range of 1.10 to 1.30 if the substrate 10 is made of copper; and the developing time coefficient K is in a range of 1.03 to 1.09 if the substrate 10 is made of stainless because the resist pattern formation defect rate increases if the developing time is too long or too short. This is because, as mentioned above, since the border area between the shielding part 38 of the glass mask 30 and the exposed part of the glass substrate 37 needs an intermediate transmittance between the shielding part 38 and the exposed part of the glass substrate 37, the exposure is performed under the conditions, and the curing degree of the resist layer 21 in the border area also becomes an intermediate value between the shielding part 38 and the exposed part of the glass substrate 37. In other words, according to the general developing time coefficient K described above, the border area becomes over-developed, and the resist pattern formation defect rate increases. Thus, in the manufacturing method of the substrate for a semiconductor package 50 of the embodiment, it is desirable to set the developing time coefficient K to be more than 1.00, and to be less than the lower limit of a range of the developing time coefficient K in a general development process.
Moreover, an exposure energy amount in the resist pattern stabilization process is desired to be in a range of 80 mJ/cm2 to 120 mJ/cm2. This makes it possible to fully harden the resist layer 21 exposed in the border area between the shielding part 38 of the mask pattern 31 and the exposed part of the glass substrate 37, and to certainly stabilize the shape of the side surface 24 of the resist pattern 22.
FIG. 3F is a view showing a plating process. In the plating process, an exposed part of the conductive substrate 10 is filled with metal material according to the shape of the resist pattern 22, and the metal layer 40 is formed. The plating may be performed by immersing the substrate 10 on which the resist pattern is formed in plating solution, then connecting the substrate 10 to a cathode and placing an anode to face the substrate 10, and performing electroplating. The metal material used for the plating, for example, may be made of not only one such as gold, but may include plural kinds of materials. In this case, for example, by performing plural plating operations with different plating solutions, plating by stacking plural kinds of metal materials can be carried out. For example, from the substrate 10 side, by plating gold (Au) in 0.1 mm film thickness at first, next by plating nickel (Ni) in 50 μm film thickness, and finally by plating gold again in 0.3 μm thickness, the plating process can be executed. This makes it possible to utilize advantages of each of the metal materials and to perform high-quality plating.
It is desirable to make the thickness of the plated metal layer 40 less than the thickness of the resist pattern 22. This allows the top surface 41 of the metal layer 40 to be formed as a flat surface, and the top surface and the size of each of semiconductor device mounting areas 45 and electrodes 46 to be uniform. Due to this, when a semiconductor device 60 is mounted on the semiconductor device mounting area 45 or wire bonding is performed on the electrode 46, it is possible to make certain the adhesion or connection and to decrease product variation of the substrates for a semiconductor device 50.
In the resist removal process, the resist pattern 22 is removed, and the substrate for a semiconductor package 50, which is the conductive substrate 10 on which the semiconductor device mounting areas 45 and electrodes 46 are formed, is completed. Each of the semiconductor device mounting areas 45 and electrodes 46 have a top surface 41 larger than a bottom surface 42 and a side surface 43 including a slope part 44 of which circumference expands from the bottom surface 42 to the top surface 41. More specifically, if a semiconductor package 100 is manufactured by using the substrate for a semiconductor package 50, the metal layer 40 has a shape that makes it difficult to be pulled out because the metal layer 40 has a slope surface that can resist a downward force by the sealing resin 80 wrapping around an area under the metal layer 40. Moreover, because the semiconductor device mounting areas 45 and electrodes 46 are configured as metal layers 40 that have a uniform size and height, each of which has a flat top surface 41, the substrate for a semiconductor package 50 is a high-accuracy substrate that can be sufficiently adapted to miniaturization of interconnections.
FIG. 5A and FIG. 5B are views showing an example of the shape of a mask pattern 31 of the glass mask 30 used for a lithography exposure process of the manufacturing method of the substrate for a semiconductor device 50 of the first embodiment. FIG. 5A is a view showing an example of a top view of the mask pattern 31 of the glass mask 30.
The light shielding area 32 is an area where the glass substrate 37 is fully covered with the light shielding part 38, and becomes a quadrangle formed with the light shielding part 38. On the other hand, the intermediate transmission area 33 is an area near a border with the transmission area 37 a, and plural transmission parts 34 are partially provided in an area made of the light shielding part 38, and the light shielding part 38 and the transmission parts 34 exist in a mixed state. This allows the intermediate area 33 to partially let the light through. Thus, for example, adjustment of the transmittance may be carried out by partially disposing the transmission parts 34 so that the transmittance of the intermediate transmission area 33 of the mask pattern 31 becomes higher than that of the light shielding area 32 among the whole mask pattern 31. From a micro perspective, a part where the light shielding part 38 is formed has 0% transmittance, and a part where the glass substrate 37 is exposed has 100% transmittance. However, as described in FIG. 4, because the intermediate transmission area 33 is disposed between the light shielding area 32 of 0% transmittance and the transmission area 37 a of 100% transmittance made of the exposed glass substrate 37 surrounding the mask pattern 31, the intermediate transmission area 33 is affected by the transmittances on both sides, and the resist layer 21 under the intermediate transmission area 33 becomes a shape including the slope 25. Therefore, without intricately adjusting materials themselves such as the glass substrate 37 and the light shielding part 38, by configuring the glass mask 30 to include the transmission part 34 made of the same material as the transmission area 37 a, and the light shielding part 38 made of the same material as the light shielding area 32 in a mixed state, it is possible to form the intermediate transmission area 33 of which transmittance is lower than that of the transmission area 37 a and is higher than that of the shielding area 38. Furthermore, by using the glass mask 30 including such a mask pattern 31, the resist pattern 22 that includes the slope part 25 and expands outward and downward can be formed, as shown in FIG. 4.
FIG. 5B is a view showing an example of a resist pattern 22 formed by a lithography exposure process by using the glass mask 30 including the mask pattern 31 shown in FIG. 5A. In FIG. 5B, the whole resist pattern 22 forming a hollow part shows the resist pattern 22 formed by the glass mask 30 including the mask pattern 31 of the shape of FIG. 5A. The resist pattern 22 including a flat top surface 23 remains corresponding to the exposed part of the glass substrate 37 of the mask pattern 31. A lower part of a circumference part corresponding to the intermediate transmission area 33 of the mask pattern 31 expands inward and downward in the hollow part, and has the side surface 24 including the slope part 25 that makes a circumference of the hollow part gradually smaller. In a part corresponding to the shielding area 32 of the mask pattern 31, the substrate 10 is exposed.
In this way, it is possible to form the resist pattern 22 that has the side surface 24 including the slope part 25 by partially disposing plural transmission parts 34 and making the intermediate part 33 including the light shielding part 38 and the transmission part 34 in a mixed state. Because the intermediate transmission part 33 is disposed between the transmission area 37 a of 100% transmittance where the light shielding part 38 is not formed at all and the light shielding area 32, the whole surface of which is fully covered with the light shielding part 38, it is possible to form the side surface 24 including the slope part 25 by the influence of both of the transmittances with the glass mask 30 of simple configuration. Though the side surface 24 expands inward and downward of the resist pattern 22 forming the hollow part, and has the slope part 25 of which circumference decreases, seen from the resist pattern 22 where resist remains, since the slope part 25 expands downward and outward, the explanation does not contradict the above-discussed description.
FIG. 9 is a view showing a mask pattern 31 b of a second modified example. FIG. 9 shows an example of the mask pattern 31 b that has a partial transmission part 34 b, 35 b pattern different from the mask pattern 31 in FIG. 7 and the mask pattern 31 a in FIG. 8. The mask pattern 31 b in FIG. 9 differs from the mask pattern 31, 31 a in FIG. 7 or FIG. 8 in that there are plural kinds of partial transmission parts 34 b, 35 b, of which sizes are different in an area of the light shielding part 38 of the intermediate transmission area 33 b.
In FIG. 9, regarding the size of the intermediate transmission area 33 b, the width is 60 μm that is the same as FIG. 7 and FIG. 8, but the first partial transmission parts 34 b of a square 15 μm on a side are centered at a position of 22.5 μm from a border line with a transmission area 37 a at 40 μm pitch in a longitudinal direction.
Furthermore, second partial transmission parts 35 b of a square 5 μm on a side are centered at a position of 55.5 μm from the outer circumference in a transverse direction and at a position in the middle of the adjacent first partial transmission parts 34 b at 40 μm pitch in a longitudinal direction. In other words, the first partial transmission parts 34 b that have a longer side are disposed on a transmission area 37 a side in the intermediate transmission area 33 b, and the second partial transmission parts 35 b are disposed on a light shielding area 32 side, and the first partial transmission parts 34 b and the second partial transmission parts 35 b are disposed alternately in a longitudinal direction.
In this way, it is possible to configure the mask pattern 31 b by partially disposing plural kinds of partial transmission parts 34 b, 35 b in an area of the light shielding part 38 of the intermediate transmission area 33 b. By disposing the partial transmission parts 34 b, 35 b on the transmission area 37 a side and the light shielding area 38 side of the intermediate transmission area 33 b, and by fine-tuning the transmittance, it is possible to adjust the slope 25 of the side surface 24 of the resist pattern 22 with a high degree of accuracy.
FIG. 11A is a view showing a semiconductor device mounting process to mount the semiconductor device 60 on the substrate for a semiconductor device 50. In the semiconductor device mounting process, the semiconductor device 60 is mounted on the semiconductor device mounting area 45 of the metal layer 40 formed on the conductive substrate 10. The semiconductor device 60 may be mounted on the semiconductor device mounting area 45 by placing the terminal 61 facing upward, and by bonding a package part to the semiconductor device mounting area 45. In this process, by using the substrate for a semiconductor package 50 of the embodiment, since the semiconductor device 60 can be mounted on the semiconductor device mounting area 45 that has a flat surface, the semiconductor device mounting process can be performed readily and surely.
FIG. 11C is a view showing a resin sealing process to seal the semiconductor device 60 and so on with the sealing resin 80. In the resin sealing process, the semiconductor device 60 on the substrate 10, the bonding wire 70, the semiconductor device mounting area 45 and the electrode 46 are sealed with the sealing resin 80 from an upper surface, and are thus protected from exterior dust and so on. In the resin sealing process, since a space above the semiconductor 10 is filled with the sealing resin 80 to cover all the above-mentioned components, spaces below lower parts of the semiconductor device mounting area 45 and electrode 46 on the substrate 10 are all filled with the sealing resin 80 and fixed.
If the substrate 10 is removed by peeling, to peel the substrate 10 off from below, a force pulling down acts on the metal layer 40 including the semiconductor device mounting area 45 and the electrode 46 electrodeposited on the substrate 10. In this case, if the metal layer 40 including the semiconductor device mounting area 45 and/or the electrode 46 has the same size for the top surface 41 and the bottom surface 42, and has the side surface 43 parallel to the vertical direction, there is a risk of the metal layer 40 falling out of the sealing resin 80 when the substrate 10 is pulled downward and peeled off. However, in the substrate for a semiconductor device 50, because the side surface 43 of the metal layer 40 has a side shape including the slope part 44 of which decreases in circumference as the circumference approaches the bottom surface 42, the sealing resin 80 acts on the metal layer 40 resisting the downward force, which makes it possible to remove only the substrate 10 from the metal layer 40 and the sealing resin 80.
FIG. 12A and FIG. 12B are views showing an example of a partial configuration of a substrate for a semiconductor package 50 a of a second embodiment. FIG. 12A is an enlarged view showing an example of a part of a metal layer 40 a. FIG. 12B is a view showing an example of a plating process of a manufacturing method of a substrate for a semiconductor device 50 a of the second embodiment.
In FIG. 12A, a side surface 43 a of the metal layer 40 a has a shape where a top surface 41 a, of which width is larger than that of a bottom surface 42 a, and a side surface 43 a includes a slope part 44 a which decreases in circumference as the circumference approaches the bottom surface 42 a, at a part around the bottom surface 42 a. Therefore, the metal layer 40 a has a shape that makes it difficult to be pulled out downward as well as the metal layer 40 of the substrate for a semiconductor package 50 in the first embodiment. More specifically, by such a slope, the substrate for a semiconductor device 50 a has a shape where sealing resin supports and fixes the metal layer 40 a including an electrode 46 and/or a semiconductor device mounting area 45 from below obliquely upward, and a binding force between the sealing resin and the electrode 46 and/or the semiconductor device mounting area 45 can be improved.
However, in FIG. 12A, referring to a top view and a bottom view of the metal layer 40 a, the circumference of the top surface 41 a has a saw-tooth appearance and has a zigzag shape 48. On the other hand, the bottom surface 42 a has a square shape with round corners as well as the bottom surface 42 of the substrate for a semiconductor device 50 a of the first embodiment. In this manner, the metal layer 40 a may have the top surface 41 a, of which circumference is formed into a zigzag shape 48 like saw teeth. By forming the circumference into the zigzag shape 48, when the metal layer 40 a is sealed with resin, it is possible to increase a contact area with the sealing resin 80 and bonding strength. Moreover, when the substrate for a semiconductor device 50 a is configured as a semiconductor package 100, since the top surface 41 a of the metal layer 40 a is hidden by resin sealing, there is no request for an appearance configuration. There is flexibility capable of taking various shapes as long as the shape is superior in function. On the other hand, when configured as the semiconductor package 100, since the bottom surface 42 a becomes an outer terminal 47 by being exposed from a bottom surface of the semiconductor package 100, it is desirable for the bottom surface 42 a to have a rectilinear circumference shape, not a zigzag shape 48. The bottom surface 42 a of the metal layer 40 a on the substrate for a semiconductor package 50 a has a shape that meets such a request.
FIG. 12B shows an example of a plating process of the manufacturing method of the substrate for a semiconductor package 50 a of the second embodiment. The plating, process is carried out after forming a resist pattern 22 a on a substrate 10 as well as the first embodiment. Thus, by forming the resist pattern 22 a so that a top surface circumference has the zigzag shape 48 of a saw-tooth appearance, the shape of the metal layer 40 a shown in FIG. 12A can be realized.
FIG. 13A and FIG. 13B are views showing an example of the mask pattern 31 d shape of the glass mask 30 and a resist pattern 22 a used for a lithography exposure process of the manufacturing method of the substrate for a semiconductor device 50 a of the second embodiment.
FIG. 13A is a view showing an example of a mask pattern 31 d of a glass mask 30 used for a lithography exposure process of the manufacturing method of the substrate for a semiconductor device 50 a of the second embodiment. In FIG. 13A, the mask pattern 31 d includes a transmission area 37 a, an intermediate transmission area 33 d and a light shielding area 32 d. The mask pattern 31 d, for example, is configured by forming a light shielding part 38 with a predetermined shape of a light shielding film on a glass substrate 37. The transmission area 37 a is an area where the glass substrate 37 is exposed. The light shielding area 32 d is an approximately square area where the light shielding part 38 is fully formed as well as the mask pattern 31 in the first embodiment. The mask pattern 31 d has the intermediate area 33 d between the transmission area 37 a and the light shielding area 32 d. These matters are similar to the mask pattern 31 in the first embodiment.
FIG. 14A through FIG. 14D are views showing an example of a shape of the metal layer 40 a formed by a plating process with the resist pattern 22 a described in FIG. 13A and FIG. 13B. FIG. 14A is a top view of the metal layer 40 a. FIG. 14B is a side view of the metal layer 40 a. FIG. 14C is a bottom view of the metal layer 40 a. FIG. 14D is a three-dimensional oblique view of an inverted metal layer 40 a.
As shown in FIG. 14A, a circumference of a top surface 41 a of the metal layer 40 a has a saw-like zigzag shape 48, which can increase the contact area of the side surface 43 a with sealing resin 80 and can improve bonding force. In addition, as shown in FIG. 14C, a bottom surface 42 a of the metal layer 40 a has a smaller area than the top surface 41 a, and is an approximate square that is used as the outer terminal 47 in general.
Moreover, as shown in FIG. 14B, in a cross-sectional shape of the metal layer 40 a, a slope shape 44 a where a cross-sectional area surface parallel to the substrate 10 decreases as the surface parallel to the substrate 10 approaches the bottom surface 42 a is formed around the bottom surface 42 a. Also, the zigzag shape 48 of the top surface 41 a decreases at a level as the level approaches the bottom surface 42 a. The slope part 44 a has a shape capable of applying an upward force when receiving a pull downward force after being sealed with the sealing resin 80. Therefore, the metal layer 40 a is configured to be able to prevent the metal layer 40 a from being pulled down in a substrate removal process of the manufacturing method of the semiconductor package 100. Furthermore, the top surface 41 a has a flat surface, which is appropriate for semiconductor device 60 mounting and wire bonding. This makes it possible to improve adhesion strength for semiconductor device mounting and to facilitate and bind strongly connections between a terminal of the semiconductor device and an electrode by wire bonding. In addition, because there is no flared part in a transverse direction, and a height is less than or equal to the resist pattern 22 a, the metal layer 40 a has a shape sufficiently capable of responding to miniaturization and meeting demands for high accuracy of a metal layer of a substrate for a semiconductor device 50 a.
FIG. 14D is a three-dimensional oblique perspective view of a vertically inverted metal layer 40 a. In FIG. 14D, the bottom surface 42 a to be the outer terminal 47 has a flat surface. Also, the metal layer 40 a has a structure where sealing resin wraps around the slope part 44 a formed into the side surface 43 a near the bottom surface 42 a, which is a shape capable of preventing movement of the metal layer 40 a by providing a downward force even if an upward force acts.
According to the semiconductor package 100 of the second embodiment, it is possible to solidly maintain a binding force between the sealing resin 80 and the metal layer 40 a by the zigzag shape 48, and to prevent the metal layer 40 a from falling out of the sealing resin 80 because the metal layer 40 a tapers downward. In addition, it is possible to prevent water intrusion from a back side of the semiconductor package 100 through borders between the metal layer 40 a or an electrode and the sealing resin layer 80, and to realize superior water resistance. Also, it is possible to carry out wire bonding and semiconductor device mounting easily on a flat surface and to improve adhesion force of the wire bonding and the semiconductor device mounting.
Moreover, with regard to a semiconductor package 100 manufactured by using the substrate for a semiconductor device 50 a of the second embodiment and a manufacturing method of the semiconductor package 100, since an explanation is similar to that in the first embodiment, the explanation is omitted.
1. A manufacturing method of a substrate for a semiconductor package comprising:
2. The manufacturing method of the substrate for a semiconductor package as claimed in claim 1,
wherein the intermediate transmission area of the mask pattern includes a mixture of a transmission part with the same transmittance as that of the transmission area and a light shielding part with the same transmittance as that of the light shielding area.
3. The manufacturing method of the substrate for a semiconductor package as claimed in claim 2,
wherein the intermediate transmission area partially includes the transmission part in the light shielding part.
4. The manufacturing method of the substrate for a semiconductor package as claimed in claim 2,
wherein the intermediate transmission area includes a zigzag border line dividing the transmission part and the light shielding part.
5. The manufacturing method of the substrate for a semiconductor package as claimed in claim 4,
wherein the hollow of the resist pattern has a side shape including a zigzag shape circumference similar to the zigzag border line in a top surface of the resist pattern, and a smaller zigzag shape circumference than that of the top surface as the circumference approaches the substrate.
6. The manufacturing method of the substrate for a semiconductor package as claimed in claim 1,
wherein the metal layer is formed with a thickness less than that of the resist pattern in the plating step.
7. The manufacturing method of the substrate for a semiconductor package as claimed in claim 1,
wherein the metal layer is an electrode for wire bonding or an area for supporting a semiconductor device.
8. The manufacturing method of the substrate for a semiconductor package as claimed in claim 1, further comprising:
a resist pattern stabilization step to expose the resist pattern between the development step and the plating step.
9. A manufacturing method of a semiconductor package comprising:
lithographic exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area disposed between the transmission area and the light shielding area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area;
US13299653 2009-02-20 2011-11-18 Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package Abandoned US20120064666A1 (en)
JP2009038563 2009-02-20
JP2009-038563 2009-02-20
JP2010000305A JP4811520B2 (en) 2009-02-20 2010-01-05 Method of manufacturing a substrate for a semiconductor device, a method of manufacturing a semiconductor device, a semiconductor device substrate and a semiconductor device
JP2010-000305 2010-01-05
US12656866 US8188588B2 (en) 2009-02-20 2010-02-18 Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package
US13299653 US20120064666A1 (en) 2009-02-20 2011-11-18 Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package
US13951612 US9054116B2 (en) 2009-02-20 2013-07-26 Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package
US12656866 Division US8188588B2 (en) 2009-02-20 2010-02-18 Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package
US13951612 Division US9054116B2 (en) 2009-02-20 2013-07-26 Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package
US20120064666A1 true true US20120064666A1 (en) 2012-03-15
ID=42630266
US12656866 Active 2030-08-01 US8188588B2 (en) 2009-02-20 2010-02-18 Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package
US13299653 Abandoned US20120064666A1 (en) 2009-02-20 2011-11-18 Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package
US13951612 Active US9054116B2 (en) 2009-02-20 2013-07-26 Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package
US (3) US8188588B2 (en)
JP (1) JP4811520B2 (en)
KR (2) KR101109795B1 (en)
CN (2) CN102324417B (en)
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