Source: http://www.google.com/patents/US8060221?dq=6,370,566
Timestamp: 2017-03-29 18:06:20
Document Index: 194821675

Matched Legal Cases: ['art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 1510', 'art 1510', 'art 1510', 'art 1510', 'art 24', 'art 24', 'art 2010', 'art 2010', 'Application No. 2008']

Patent US8060221 - Peripheral device of programmable logic controller - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA tracing-result optimization processing unit generates an optimized tracing result. A tracing-result collation processing unit collates the optimized tracing result and a time chart as a basis of a sequence processing for an external apparatus and detects shift of the optimized tracing result. A tracing-result...http://www.google.com/patents/US8060221?utm_source=gb-gplus-sharePatent US8060221 - Peripheral device of programmable logic controllerAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8060221 B2Publication typeGrantApplication numberUS 12/304,632PCT numberPCT/JP2006/311807Publication dateNov 15, 2011Filing dateJun 13, 2006Priority dateJun 13, 2006Fee statusLapsedAlso published asCN101467111A, CN101467111B, DE112006003926B4, DE112006003926T5, US20100049337, WO2007144936A1Publication number12304632, 304632, PCT/2006/311807, PCT/JP/2006/311807, PCT/JP/6/311807, PCT/JP2006/311807, PCT/JP2006311807, PCT/JP6/311807, PCT/JP6311807, US 8060221 B2, US 8060221B2, US-B2-8060221, US8060221 B2, US8060221B2InventorsKaori Sakagami, Masanobu Sumiya, Tomohiro Sato, Makoto NonomuraOriginal AssigneeMitsubishi Electric CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (33), Non-Patent Citations (1), Referenced by (1), Classifications (13), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetPeripheral device of programmable logic controller
US 8060221 B2Abstract
A tracing-result optimization processing unit generates an optimized tracing result. A tracing-result collation processing unit collates the optimized tracing result and a time chart as a basis of a sequence processing for an external apparatus and detects shift of the optimized tracing result. A tracing-result storing unit accumulates and stores therein a tracing result obtained by a programmable logic controller at predetermined time intervals. Every time the tracing result is stored in the tracing-result storing unit, the tracing-result optimization processing unit generates the optimized tracing result.
The present invention relates to a PLC peripheral device that performs creation and editing of a sequence program for a programmable logic controller (PLC).
Conventionally, a sequence program test method for performing an operation test for a sequence program created from a time chart in a PLC peripheral device has been proposed (see, for example, Patent Document 1). In the sequence program test method disclosed in Patent Document 1, based on a sequence time chart as operation patterns of an apparatus controlled by a sequencer program, an operation pattern matrix table obtained by digitizing the operation patterns is created in advance and a value obtained by digitizing an operation output from the apparatus controlled by the sequencer program and the operation pattern matrix table are compared. When the value and the operation pattern matrix table coincide with each other, it is judged that the sequencer program is normal. When the value and the operation pattern matrix table do not coincide with each other, it is judged that the sequencer program is abnormal and a result of the judgment is output to an operator of the peripheral device of the PLC.
However, in the sequence program test method disclosed in Patent Document 1, the shift of timing caused by performance peculiar to the apparatus controlled by the sequence program is not taken into account. As a result, the operation pattern matrix table as a reference of comparison and the value obtained by digitizing the operation output from the apparatus to be compared do not coincide with each other in a strict sense. Therefore, there is a problem in that, in judgment processing, an error rate for allowing the shift between the operation pattern matrix table and the value has to be set and highly accurate judgment cannot be performed. Further, there is also a problem in that, when highly accurate judgment is performed, the operator has to perform debagging of the value obtained by digitizing the operation output from the apparatus.
To achieve the object, a PLC peripheral device according to the present invention is configured to be connected to a programmable logic controller (PLC) that controls an external apparatus based on a sequence program, and verifies an operation state of the sequence program in the PLC. The PLC peripheral device includes a tracing-result optimization processing unit that generates an optimized tracing result obtained by correcting, based on performance of the external apparatus, a tracing result obtained by the PLC executing sequence processing corresponding to a predetermined signal input/output unit out of external apparatuses; and a tracing-result collation processing unit that collates the optimized tracing result and a time chart as a basis of the sequence processing for the external apparatus and detects shift of the optimized tracing result. To achieve the object, a PLC peripheral device according to the present invention is connected to a programmable logic controller, which controls an external apparatus based on a sequence program, and verifies an operation state of the sequence program in the programmable logic controller. The Programmable-logic-controller peripheral device includes a tracing-result optimization processing unit that generates an optimized tracing result obtained by correcting, based on performance of the external apparatus, a tracing result obtained by the programmable logic controller executing sequence processing corresponding to a predetermined signal input/output unit out of external apparatuses; a tracing-result collation processing unit that collates the optimized tracing result and a time chart as a basis of the sequence processing for the external apparatus and detects shift of the optimized tracing result; and a tracing-result storing unit that accumulates and stores therein a tracing result obtained by the programmable logic controller executing, at predetermined time intervals, the sequence processing for the predetermined signal input/output unit out of the external apparatuses. Every time the tracing result is stored in the tracing-result storing unit, the tracing-result optimization processing unit generates a optimized tracing result, and the tracing-result collation processing unit has a function of performing collation of the optimized tracing result and the time chart and detecting shift of timing due to elapse of time.
According to the present invention, when the verification of a sequence program created from a time chart is performed, tracing is executed and a tracing result after optimization, which takes into account a performance error of a verification target apparatus, and the time chart are compared. Therefore, there is an effect that a user can efficiently and accurately verify the sequence program without debagging the tracing result obtained by the PLC. Furthermore, the shift of timing due to performance of an external apparatus as an execution target of the sequence program is excluded from a comparison target. Therefore, there is an effect that it is possible to detect only original problems of the sequence program.
FIG. 1 is a schematic block diagram of the structure of a first embodiment of a PLC peripheral device according to the present invention and the PLC.
Exemplary embodiments of a peripheral device of a programmable logic controller (PLC) (hereinafter, “PLC peripheral device”) and an automatic verification method for a program are explained in detail below with reference to the accompanying drawings. The present invention is not limited by these embodiments.
FIG. 1 is a schematic block diagram of the structure of a first embodiment of the PLC peripheral device according to the present invention and the PLC. A PLC peripheral device 2 is connected to a main body of a PLC 1 that controls a control target apparatus and the like. A display device 3 such as a CRT (Cathode Ray Tube) or an LCD (Liquid Crystal Display) and an input device 4 such as a keyboard are connected to the PLC peripheral device 2.
FIG. 3 is a data structure diagram of a time chart and a tracing result in the PLC peripheral device. The time chart and the tracing result have a common data structure. As shown in the figure, the time chart or the tracing result stores, for each of devices, an ON/OFF state for each elapsed time. For example, an ON state is represented by “1” and an OFF state is represented by “0”. A device name is specified by a combination of a program name and a step number.
FIG. 4 is a flowchart of an example of a procedure of sequence program automatic verification processing in the PLC and the PLC peripheral device shown in FIG. 1. First, the PLC peripheral device 2 discriminates presence or absence of an automatic verification instruction for a sequence program from a user (an operator) (step S101). When there is no automatic verification instruction for a sequence program from the user (“No” at step S101), the sequence program automatic verification processing in the PLC peripheral device 2 ends. On the other hand, when there is an automatic verification instruction for a sequence program from the user (“Yes” at step S101), the tracing-target-device acquisition processing unit 25 acquires the tracing target device 24 c from the time chart 24 b in the data memory 24 (step S102). Specifically, the tracing-target-device acquisition processing unit 25 acquires, as the tracing target device 24 c, a device registered in the time chart 24 b stored in the data memory 24 and sets the tracing target device 24 c in the data memory 24. Subsequently, the tracing-target-device acquisition processing unit 25 transmits the acquired tracing target device 24 c to the PLC 1 via the PLC I/F unit 21 (step S103).
In a second embodiment of the present invention, a PLC peripheral device is explained that can detect the shift of timing due to elapse of time by accumulating the tracing result after optimization acquired in the first embodiment and collating a result of tracing performed every time a predetermined time set in the PLC peripheral device by an operator elapses and a time chart.
FIG. 10 is a schematic block diagram of the structure of the second embodiment of the PLC peripheral device according to the present invention and the PLC. In the PLC peripheral device 2, the data memory 24 in the PLC peripheral device 2 shown in FIG. 1 according to the first embodiment can accumulate and store the tracing result after optimization 24 f and the collation result 24 g. For example, as the tracing result after optimization 24 f, a “tracing result 1” 24 f-1, a “tracing result 2” 24 f-2, and the like as tracing results in the first time, the second time, and the like are stored. As the collation result 24 g, a “collation result” 24 g-1, a “collation result 2” 24 g-2, and the like as collation results in the first time, the second time, and the like are stored. The data memory 24 can store a timing shift detection result 24 h detected by the tracing-result collation processing unit 27.
First, the PLC peripheral device 2 judges presence or absence of an instruction for detection processing for timing shift due to elapse of time from the user (step S201). When there is no instruction for detecting timing shift due to elapse of time (“No” at step S201), the PLC peripheral device 2 finishes the detection processing for timing shift due to elapse of time. On the other hand, when there is an instruction for detecting timing shift due to elapse of time (“Yes” at step S201), the tracing-target-device acquisition processing unit 25 acquires a tracing target device from the time chart 24 b in the data memory 24 (step S202) and sets the tracing target device 24 c in the data memory 24. Thereafter, the tracing-target-device acquisition processing unit 25 transmits the acquired tracing target device to the PLC 1 via the PLC I/F unit 21 (step S203).
In a third embodiment of the present invention, a PLC peripheral device is explained that can correct, when timing shift is detected as a result of collating the time chart and the tracing result after optimization in the first embodiment, a setting value and the like of a timer included in a sequence program and automatically correct the timing shift.
FIG. 14 is a flowchart of an example of a procedure of timing automatic correction processing for a sequence program in the PLC peripheral device. First, the PLC peripheral device 2 discriminates presence or absence of an automatic correction instruction or the sequence program from the user (step S301). When there is no automatic correction instruction for the sequence program (“No” at step S301), the automatic correction processing for the sequence program in the PLC peripheral device 2 ends. On the other hand, when there is an automatic correction instruction for the sequence program (“Yes” at step S301), the PLC peripheral device 2 executes processing for detecting, from the sequence program, a section where the tracing result after optimization 24 f shifts from the time chart 24 b (steps S302 to S308).
The correction-target-timing detection processing unit 28 acquires an inconsistent section using the time chart 24 b in the data memory 24 and the collation result 24 g of the tracing result after optimization 24 f (step S303). The correction-target-timing detection processing unit 28 searches for a step corresponding to the inconsistent section from the sequence program in the program 24 a stored in the data memory 24 (step S304). For example, the correction-target-timing detection processing unit 28 searches for the corresponding step in the sequence program based on a device corresponding to tracing result data having the inconsistent section. Thereafter, the correction-target-timing detection processing unit 28 discriminates whether there is timer processing before the found step (step S305). As a result, when there is the timer processing (“Yes” at step S305), the correction-target-timing detection processing unit 28 calculates, with respect to a present setting value of the timer, a value with which a difference does not occur between the time chart 24 b and the tracing result after optimization 24 f and calculates a new timer setting value using the value (step S306). The correction-target-timing detection processing unit 28 stores correction target timing data including the step found at step S304 and the new timer setting value calculated at step S306 in the correction target timing list 24 i in the data memory 24 (step S307). On the other hand, when there is no timer processing before the corresponding step at step S305 (“No” at step S305), no processing is performed for the step. The processing from step S302 is executed until no inconsistent section is left between the time chart and the tracing result after optimization (steps S302 to S308).
FIG. 15 is a diagram of a specific example of timing automatic correction for a sequence program in the PLC peripheral device. In this figure, a time chart 1510, a tracing result after optimization 1520 and a sequence program 1530 before timing correction, and a tracing result after optimization 1540 and a sequence program 1550 before timing correction are shown. In the figure, a device D of the tracing result after optimization 1540 after the correction has a result exceeding an allowable error ratio with respect to the time chart 1510 as a reference. The correction-target-timing detection processing unit 28 acquires the sequence program 1530 before correction from the data memory and judges whether there is timer processing before a “device D” 1531 of the sequence program 1530 before correction. Timer processing called a standby timer 1532 is present before the “device D” 1531 of the sequence program 1530 before correction. If time Δt during which a difference does not occur between the time chart 1510 and the tracing result after optimization 1520 is one second judging from the tracing result after optimization 1520 before correction and the timer chart 1510, the correction-target-timing detection processing unit 28 sets a new timer setting value obtained by correcting a setting value of the standby timer 1532 from “K20” to “K10”. To specify a step, for example, a number “80” written on a bus on a left side of the sequence program is used. Thereafter, as indicated by the tracing result after optimization 1540 after correction and the sequence program 1550 after correction, the timing is corrected by the timing correction processing unit 29 based on the correction target timing.
In a fourth embodiment of the present invention, a PLC peripheral device is explained that can indicates, when the shift of timing due to elapse of time is detected in the second embodiment, a section causing the shift to a user.
FIG. 17 is a flowchart of an example of a procedure of position presentation processing for a sequence program that causes timing shift due to elapse of time of the PLC peripheral device. First, the PLC peripheral device 2 checks whether timing shift due to elapse of time is detected (step S401). The detection of timing shift due to elapse of time is performed by the tracing-result collation processing unit 27 and a result of the detection is stored in the data memory 24 as the timing shift detection result 24 h. Therefore, presence or absence of detection of timing shift can be judged according to presence or absence of the timing shift detection result 24 h in the data memory 24. The timing shift detection processing by the tracing-result collation processing unit 27 is explained in the second embodiment. Therefore, explanation of the timing shift detection processing is omitted. When timing shift due to elapse of time is not detected (“No” at step S401), the PLC peripheral device 2 finishes the timing shift position presentation processing. On the other hand, when timing shift due to elapse of time is detected (“Yes” at step S401), the PLC peripheral device 2 performs detection processing for a position on the sequence program that causes the timing shift (steps S402 to S407).
First, the correction-target-sequence-program detection processing unit 30 acquires a device as a cause from the timing shift detection result 24 h (step S403). The correction-target-sequence-program detection processing unit 30 searches for, based on the acquired device, a step corresponding to the device in the program (sequence program) 24 a of the data memory 24 (step S404). For example, the correction-target-sequence-program detection processing unit 30 searches for, based on a device corresponding to tracing result data in which timing shift is detected, a step corresponding to the device in the sequence program. As a result of the search, when a step corresponding to the device is found (“Yes” at step S405), the correction-target-sequence-program detection processing unit 30 stores a corresponding section in the sequence program in the correction target sequence program list 24 j as a correction target sequence program (step S406). When a step corresponding to the device is not found at step S405 (“No” at step S405), no processing for the step is performed. The processing from step S402 is executed to the last of the sequence program (steps S402 to S407).
In a fifth embodiment of the present invention, a PLC peripheral device is explained that can search for, when it is necessary to correct the sequence program in the third embodiment, a section where a device as a cause of the correction is used and indicates a related sequence program section to a user.
FIG. 19 is a flowchart of an example of a procedure of timing correction necessary section display processing during timing automatic correction for a sequence program of the PLC peripheral device. First, the PLC peripheral device 2 discriminates presence or absence of an automatic correction instruction for timing of a sequence program (step S501). When there is no automatic correction instruction for timing of the sequence program (“No” at step S501), the timing correction necessary section display processing for the sequence program in the PLC peripheral device 2 ends. On the other hand, when there is an automatic correction instruction for timing of the sequence program (“Yes” at step S501), the PLC peripheral device 2 executes processing for detecting, from the sequence program, a section where a tracing result after optimization shifts from a time chart (steps S502 to S511).
The correction-target-timing detection processing unit 28 acquires an inconsistent section using the time chart 24 b in the data memory 24 and the collation result 24 g of the tracing result after optimization 24 f (step S503). The correction-target-timing detection processing unit 28 searches for a step corresponding to the inconsistent section from the sequence program in the program 24 a stored in the data memory 24 (step S504). For example, the correction-target-timing detection processing unit 28 searches for the corresponding step in the sequence program based on a device corresponding to tracing result data having the inconsistent section. Thereafter, the correction-target-timing detection processing unit 28 discriminates whether there is timer processing before the found step (step S505). As a result, when there is the timer processing (“Yes” at step S505), the correction-target-timing detection processing unit 28 calculates, with respect to a present setting value of the timer, a value with which a difference does not occur between the time chart 24 b and the tracing result after optimization 24 f and calculates a new timer setting value using the value (step S506). The correction-target-timing detection processing unit 28 stores correction target timing data including the step found at step S504 and the new timer setting value calculated at step S506 in the correction target timing list 24 i in the data memory 24 (step S507).
On the other hand, when there is no timer processing before the corresponding step at step S505 (“No” at step S505), the correction-target-sequence-program detection processing unit 30 searches for a coil corresponding to a contact of the corresponding step in the sequence program (step S508). As a result, when the correction-target-sequence-program detection processing unit 30 finds the corresponding coil (“Yes” at step S509), the correction-target-sequence-program detection processing unit 30 stores a start step and an end step of the sequence program including the coil in the correction target sequence program list 24 j as a correction target sequence program (step S510). When the correction-target-sequence-program detection processing unit 30 cannot find the corresponding coil (“No” at step S509), no processing is performed for the step. The processing from step S502 is executed until no inconsistent section is left between the time chart and the tracing result after optimization (steps S502 to S511).
FIG. 20 is a diagram of an example of the timing correction necessary section display processing for the sequence program in the PLC peripheral device. As shown in the figure, a tracing result after optimization 2020 before timing correction is compared and collated with a time chart 2010 as a reference. A position on a sequence program 2030 where the tracing result after optimization 2020 and the time chart 2010 do not coincide with each other is detected. When there is no coil processing before a step corresponding to the position, a coil corresponding to a contact of a correction target step is searched. In the case shown in FIG. 20, looking at the tracing result after optimization 202 before correction, tracing result data of a device C does not coincide with the time chart. Thus, looking at the sequence program 2030 before correction, there is no timer before the “device C” 2031 as the correction target step. Therefore, a “device B” 2032 and a “start switch” 2033 as contacts of a step having the “device C” 2031 are extracted. Thereafter, a “step 78” and a “step 80” as steps in the sequence program 2030 having the “device B” 2032 and the “start switch” 2033 as coils are stored in the correction target sequence program list as a correction target sequence program. The sequence-program highlighting function 221 of the display processing unit 22 performs processing for highlighting the steps stored in this correction target sequence program list. In the case of FIG. 20, as indicated by a sequence program 2040, the “step 78” and the “step 80” including the “device B” and the “start switch” as coils are highlighted.
As explained above, the peripheral device of the PLC according to the present invention are suitably used in performing debagging for a sequence program.
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