Source: http://www.google.com/patents/US5782665?ie=ISO-8859-1&dq=5920316
Timestamp: 2016-02-06 21:39:04
Document Index: 177508499

Matched Legal Cases: ['Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08']

Patent US5782665 - Fabricating array with storage capacitor between cell electrode and dark matrix - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn array is fabricated in which a cell's dark matrix overlaps its cell electrode so that the overlap areas and the dielectric material between them form a storage capacitor. Each cell's dark matrix can overlap the cell's electrode around its perimeter, and the overlap areas of the dark matrix and the...http://www.google.com/patents/US5782665?utm_source=gb-gplus-sharePatent US5782665 - Fabricating array with storage capacitor between cell electrode and dark matrixAdvanced Patent SearchPublication numberUS5782665 APublication typeGrantApplication numberUS 08/581,088Publication dateJul 21, 1998Filing dateDec 29, 1995Priority dateDec 29, 1995Fee statusPaidAlso published asEP0782035A1, EP0782035B1Publication number08581088, 581088, US 5782665 A, US 5782665A, US-A-5782665, US5782665 A, US5782665AInventorsRichard L. Weisfield, Michael G. Hack, Joel LevineOriginal AssigneeXerox CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (25), Non-Patent Citations (23), Referenced by (42), Classifications (15), Legal Events (9) External Links: USPTO, USPTO Assignment, EspacenetFabricating array with storage capacitor between cell electrode and dark matrix
FIGS. 5-8 show an implementation in which a fixed potential dark matrix overlaps with a cell electrode to form a capacitor. The implementation in FIGS. 5-8 can be made using AMLCD technology described in copending, coassigned U.S. Pat. No. 5,621,556, entitled "Active Matrix Liquid Crystal Device and Manufacturing Method" ("the Top ITO Application"), incorporated herein by reference. In the implementation of FIGS. 5-8, each pixel could be square with effective widths of approximately 45 μm�45 μm and scan lines and data lines could be approximately 5 μm wide.
The act in box 302 then deposits bottom nitride layer 260, amorphous silicon layer 262, and top nitride layer 262. The act in box 302 can be implemented as described in relation to FIG. 3B of the Top ITO Application. Bottom nitride layer 260 can be silicon nitride deposited at approximately 300�-380� C. to a thickness of approximately 3000 angstroms. Amorphous silicon layer 262 can contain approximately 5-12% hydrogen and can be deposited at approximately 230�-300� C. to a thickness of approximately 300-500 angstroms. Top nitride layer 264 can be silicon nitride deposited at approximately 200�-250� C. to a thickness of approximately 1000-1500 angstroms.
The act in box 306 deposits n+ amorphous silicon layer 266 and top metal layer 268. The act in box 306 can be implemented as described in relation to FIG. 3C of the Top ITO Application, with n+ amorphous silicon layer 266 including approximately 0.5-2% phosphorous and approximately 5-15% hydrogen, deposited at approximately 200�-250� C. to a thickness of approximately 1000 angstroms. Top metal layer 268 can include molybdenum-chromium, titanium, tantalum, a multilayered structure with alternating layers of aluminum and titanium-tungsten (TiW), or aluminum with appropriate barrier metal layers on top and bottom, such as titanium, TiW, or tantalum. For example, a first sublayer of TiW can be approximately 500 angstroms thick; then an aluminum sublayer can be approximately 3000-10,000 angstroms thick; then a second sublayer of TiW can be approximately 500-1000 angstroms thick.
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*Mar 29, 2007Jul 26, 2007Semiconductor Energy Laboratory Co., Ltd.Display deviceUS20070182678 *Mar 29, 2007Aug 9, 2007Semiconductor Energy Laboratory Co., Ltd.Display deviceUS20080197354 *Oct 30, 2007Aug 21, 2008Kyu-Sik ChoThin film transistor, an organic light emitting device including the same, and a manufacturing method thereofUS20080266514 *Apr 24, 2008Oct 30, 2008Seiko Epson CorporationActive-matrix substrate and method for producing the same, electrooptical device and method for producing the same, and electronic apparatusUS20100320473 *Aug 27, 2010Dec 23, 2010Chih-Chung LiuThin film transistor structure of pixelCN101295680BApr 24, 2008Feb 29, 2012精工爱普生株式会社Active-matrix substrate and method for producing the same, electrooptical device and method for producing the same, and electronic apparatusEP1037094A2Mar 3, 2000Sep 20, 2000Sel Semiconductor Energy Laboratory Co., Ltd.Active matrix type display device* Cited by examinerClassifications U.S. Classification445/24, 445/35, 349/111International ClassificationH01L29/786, G02B5/00, G02F1/1368, G02F1/1335, H01L21/336, G02F1/136, G02F1/1362Cooperative ClassificationG02F1/1368, G02F1/136209, G02F1/136213European ClassificationG02F1/1362B, G02F1/1362CLegal EventsDateCodeEventDescriptionMay 10, 1996ASAssignmentOwner name: XEROX CORPORATION, CONNECTICUTFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WEISFIELD, RICHARD L.;HACK, MICHAEL G.;LEVINE, JOEL;REEL/FRAME:007950/0051;SIGNING DATES FROM 19960414 TO 19960424Dec 3, 2001FPAYFee paymentYear of fee payment: 4Jun 28, 2002ASAssignmentOwner name: BANK ONE, NA, AS ADMINISTRATIVE AGENT, ILLINOISFree format text: SECURITY INTEREST;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:013153/0001Effective date: 20020621Oct 31, 2003ASAssignmentOwner name: JPMORGAN CHASE BANK, AS COLLATERAL AGENT,TEXASFree format text: SECURITY AGREEMENT;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:015134/0476Effective date: 20030625Nov 15, 2005FPAYFee paymentYear of fee payment: 8Feb 22, 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