Source: http://www.google.com/patents/US6341322?dq=5,646,839
Timestamp: 2016-04-30 08:10:07
Document Index: 697794199

Matched Legal Cases: ['art 602', 'art 602', 'art 602', 'art 602', 'art 602', 'art 602', 'art 602']

Patent US6341322 - Method for interfacing two buses - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method and apparatus for interfacing buses includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a response buffer are provided which are accessible via the second bus and coupled to the interface processor. The...http://www.google.com/patents/US6341322?utm_source=gb-gplus-sharePatent US6341322 - Method for interfacing two busesAdvanced Patent SearchPublication numberUS6341322 B1Publication typeGrantApplication numberUS 09/258,095Publication dateJan 22, 2002Filing dateFeb 25, 1999Priority dateMay 13, 1997Fee statusPaidAlso published asUS5987554Publication number09258095, 258095, US 6341322 B1, US 6341322B1, US-B1-6341322, US6341322 B1, US6341322B1InventorsJi-hwan Liu, Ken Nguyen, Karl S. Johnson, Mallikarjunan MahalingamOriginal AssigneeMicron Electronics, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (271), Non-Patent Citations (48), Referenced by (14), Classifications (110), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetMethod for interfacing two buses
US 6341322 B1Abstract
What is claimed is: 1. A method of controlling the transfer of information between one or more processors on a first bus and one or more processors on a second bus through an interface having an interface processor, comprising:
writing information to be transferred across the interface from a second processor on the second bus to a first processor on the first bus to a request buffer; writing a command from the second processor via the second bus to the interface processor to transfer the information residing in the request buffer to the first processor via the first bus; writing information to be transferred across the interface from the first processor on the first bus to the second processor on the second bus to a response buffer; and reading the information in the response buffer via the second bus. 2. The method of claim 1, further including:
generating an interrupt on the second bus in response to a request from the first processor on the first bus; and in response to the interrupt, reading the information in the response buffer. 3. The method of claim 1, further including:
reviewing a status register associated with the interface to determine whether the interface is currently allocated; if the interface is not currently allocated, then allocating control of the interface to a single client on the second bus. 4. The method of claim 2, wherein the information written to the request buffer includes a command to a processor on the first bus and wherein the information written to the response buffer is transmitted in response to the command.
setting the status register to indicate that a processor on the first bus has reported an event and generating an interrupt on the second bus. 6. A method of transferring information between first and second electronic buses through an interface having an interface processor, comprising:
reviewing a status register associated with the interface to determine whether a transfer between the buses is in process; if a transfer between the buses is not in process, then writing information to be transferred across the interface from the second bus to the first bus to a request buffer; writing a command to the interface processor to transfer the information residing in the request buffer to the first bus; writing information to be transferred across the interface from the first bus to the second bus to a response buffer; and generating a message on the second bus indicating that information has been written in the response buffer. 7. The method of claim 6, wherein the message generated is an interrupt on the second bus generated in response to a request from a device on the first bus and in response to the interrupt, the information in the response buffer is read from the second bus.
8. The method of claim 6, wherein the information written to the request buffer includes a command to a device on the first bus and wherein the information written to the response buffer is transmitted in response to the command.
setting the status register to indicate that a device on the first bus has reported an event and generating an interrupt on the second bus. 10. A method of controlling the transfer of information between a first bus and a plurality of clients on a second bus through an interface having an interface processor, comprising:
reviewing a status register associated with the interface to determine whether the interface is currently allocated to one of said plurality of clients; if the interface is not currently allocated to a client, then allocating control of the interface to a single client on the second bus; writing information to be transferred across the interface from the second bus to the first bus to a request buffer; writing a command to the interface processor to transfer the information residing in the request buffer to the first bus; writing information to be transferred across the interface from the first bus to the second bus to a response buffer; generating an interrupt on the second bus in response to a request from a device on the first bus; and in response to the interrupt, reading the information in the response buffer from the second bus. 11. A method of controlling the transfer of information between a first bus and clients on a second bus through an interface including an interface processor, comprising:
placing client messages to be transferred across the interface into a queue; reviewing a status register associated with the interface to determine whether the interface is currently allocated to a client; if the interface is not currently allocated to a client, then assuming control of the interface; writing a first of the client messages in the queue to a request buffer; writing a command to the interface processor to transfer the message in the request buffer to the first bus; determining whether a message result has arrived in a response buffer in response to a client message that was transferred to the first bus; determining the size of the response in the response buffer; verifying that the client associated with the response in the response buffer has allocated sufficient space to receive the response; and writing the contents of the response buffer to a memory location allocated by the client. 12. The method of claim 11, further including repeating the method for each message placed in the queue.
13. The method of claim 11, further including deallocating the interface.
14. A program storage device storing instructions that when executed by a computer perform the method comprising:
writing information to be transferred across a bus interface having an interface processor from a second processor on a second bus to a first processor on a first bus to a request buffer; writing a command from the second processor via the second bus to the bus interface to transfer the information residing in the request buffer to the first processor via the first bus; writing information to be transferred across the bus interface from the first processor on the first bus to the second processor on the second bus to a response buffer; and reading the information in the response buffer via the second bus. 15. A program storage device storing instructions that when executed by a computer perform the method comprising:
reviewing a status register associated with a bus interface between first and second buses to determine whether the bits interface is currently allocated to one of a plurality of clients; if the bus interface is not currently allocated to a client, then allocating control of the bus interface to a single client on the second bus; writing information to be transferred across the bus interface from the second bus to the first bus to a request buffer; writing a command to a bus interface processor to transfer the information residing in the request buffer to the first bus; receiving an interrupt on the second bus; in response to the interrupt, reading information in a response buffer associated with the bus. 16. A method of transferring information between an I2C bus and an ISA bus through an interface, comprising:
reviewing a status register associated with the interface to determine whether the interface is currently allocated; if the interface is not currently allocated, then allocating control of the interface to a client on the ISA bus; writing information to be transferred across the interface from the ISA bus to the I2C bus to a request buffer; writing a command to an interface processor to transfer the information residing in the request buffer to the I2C bus; writing information to be transferred across the interface from the I2C bus to the ISA bus to a response buffer; generating an interrupt on the ISA bus in response to a request from a device on the I2C bus; and reading the information in the response buffer via the ISA bus. Description
This application is a continuation of U.S. Pat. No. 5,987,554, issued Nov. 16, 1999. The subject matter of U.S. Pat. No. 6,182,180, issued Jan. 30, 2001 is related to this application.
The following patent applications and patents, all of which were filed on Oct. 1, 1997 and were commonly owned, are hereby incorporated herein in their entirety by reference thereto:
Patent No./Application
“System Architecture for Remote Access and
Control of Environmental Management”
“Method for Managing aDistributed Processor
“Method for Mapping Environmental Resources
to Memory for Program Access”
“Method for the Hot Add of a Network Adapter
08/942,963
“Method for the Hot Swap of a Network Adapter
5,899,965
“Method for the Hot Swap of a Mass Storage
“Method of Performing an Extensive Diagnostic
Diagnostic Test in Conjunction with a BIOS
“Configuration Management Method for Hot
Adding and Hot Replacing Devices”
“Configuration Management System for Hot
“Method for Resetting a Server”
“System for Displaying a Flight Recorder”
“Method for Displaying a Flight Recorder”
08.943,355
“Method for Facilitating the Replacement or
“System Management Graphical User Interfacr”
08.943,357
“Alert Configuration and Manager”
“Black Box Recorder for Information System
“Method for Displaying System Status”
“Method for Automatically Configuring a Server
after Hot Add of a Device”
“System for Automatically Configuring a Server
“Means for Allowing Two or More Network
Interface Controller Cards to Appear as One
Card to an Operating System”
One such bus architecture is the Inter-IC control bus (I2C bus). The I2C bus is a bi-directional two-wire bus (a serial data line and a serial clock line). Advantages of the I2C bus architecture are that it provides flexibility and lowers interconnecting costs by reducing board space and pin count. The I2C bus has particular application in video cards for computer systems and electronic components such as television tuners, AM/FM tuners, video decoders, video encoders, television audio decoders and video cross bars).
The invention addresses the above and other needs by providing an interface apparatus and method, which in one embodiment includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a response buffer are provided which are accessible via the second bus and coupled to the interface processor. The request buffer can be used to store information to be transmitted from the second bus to the first via the interface processor while the response buffer can be used to store information to be transmitted from the first bus to the second bus via the interface processor. The interface processor may include a status register to indicate the status of the interface controller. The interface controller may also include a command register to receive commands transmitted over the second bus.
One specific environment in which the invention can be utilized is described in application Ser. No. 08/942,402 entitled “Diagnostic and Managing Distributed Processor System” and application Ser. No. 08/942,168, entitled “Method for Automatically Reporting a System Failure in a Server”, which are incorporated herein by reference above and is described below in general terms in order to provide the reader with an example of a specific application of the invention. However, the invention can be utilized in various other systems.
Referring to FIG. 1, a block diagram of an embodiment of a server system 100 is illustrated. The server system 100 may include a central processing unit (CPU) 101 which executes the operating system (OS) software which controls the communications protocol of the server system 100. The CPU 101 is coupled to an Industry Standard Architecture bus (ISA bus) 103 which transfers data to and from the CPU 101. The ISA bus 103 and its functionality are well-known in the art Coupled to the ISA bus 103 is a system interface 105 which provides an interface between the ISA bus and an I2C bus 107. The interface 105 acts as an interface between the ISA bus and an I2C bus which couples a group of microcontrollers that monitor and control various subsystems and components of the server system 100. As described in further detail below, a message such as an event message sent to the system interface 105 may indicate that a system failure or error has occurred. Additionally, other information including date, queries and commands may be sent across the system interface 105. As used herein, the term “event” may refer to the occurrence of any type of system failure or warning. The structure and functionality of the system interface 105 is described in greater detail below with respect to FIG. 2.
Coupled to the system interface 105 is a system bus 107. In one embodiment, the system bus 111 is an Inter-IC control bus (I2C bus), which transfers data to and from the various controllers and subsystems mentioned above. The command, diagnostic, monitoring, and logging functions of the failure reporting system of the invention may be accessed through the common I2C bus protocol. The I2C bus protocol uses a slave address as the means of identifying the devices on the bus. Any function can be queried by generating a “read” request, which has its address as part of its protocol format. Conversely, a function can be executed by “writing” to an address specified in the protocol format. Any controller or processor connected to the bus can initiate read and write requests by sending a message on the I2C bus to the processor responsible for that function.
Coupled to the system bus 107 is a CPU A controller 109, a CPU B controller 111, a chassis controller 112 and four canister controllers 113. These controllers monitor and control various operating parameters and/or conditions of the subsystems and components of the server system 100. For example, CPU A controller 109 may monitor the system fan speeds, CPU B controller 111 may monitor the operating temperature of the CPU 101, the chassis controller 112 may monitor the presence of various circuit boards and components of the server system, and each of the canister controllers 112 may monitor the presence and other operating conditions of “canisters” connected to the server system 100. A “canister” is a detachable module which provides the ability to expand the number of peripheral component interface (PCI) devices that may be integrated into the server system 100. Each canister is capable of providing I/O slots for up to four PCI cards, each capable of controlling and arbitrating access to a PCI device, such as a CD ROM disk drive, for example. If one or more of the various controllers detects a failure, the respective controller sends an event message to the system interface 105 which subsequently reports the occurrence of the event to the CPU 101. In one embodiment, the controllers 109, 111 and 113 are PIC16C65 microcontroller chips manufactured by Microchip Technologies, Inc. and the chassis controller 112 is a PIC16C74 microcontroller chip manufactured by Microchip Technologies, Inc.
Upon detecting a failure condition, a controller (109, 111, 112 or 113) not only transmits an event message to the system interface 105, but also transmits failure information associated with the failure condition to a system recorder 115 connected to the system bus 107. The system recorder 115 then assigns a time stamp to the failure information and logs the failure by storing the failure information, along with its time stamp, into a system log 117. The operation and functionality of the system recorder 115 is described in further detail below with reference to FIG. 6. In one embodiment, the system log 117 is a non-volatile random access memory (NVRAM), which is well-known for its characteristics in maintaining the integrity of data stored within it, even when power to the memory cells is cut off for extended periods of time as a result of a system shutdown or power failure. The following are examples of various monitoring functions performed by some of the controllers described above. However, it is understood that the invention is not limited to these monitoring functions which serve only as examples.
As shown in FIG. 1, the server system 100 further may include a remote interface 119 also connected to the system bus 107. The remote interface 119 also receives event messages from the various controllers 109, 111, 112 has been detected. The re condition has been detected. The remote interface 119 is a link to the server system 100 for a remote user or client. The term “client” is used to refer to a software program. In one embodiment, the remote interface 119 encapsulates messages in a transmission packet to provide error-free communications and link security. This method establishes a communication protocol in which data is transmitted to and from the remote interface 119 by using a serial communication protocol known as “byte stuffing.” In this communication method, certain byte values in the data stream always have a particular meaning. For example, a certain byte value may indicate the start or end of a message, an interrupt signal, or any other command. A byte value may indicate the type or status of a message, or even be the message itself.
Through the remote interface 119, a failure condition may be reported to a local system operator or to a remote operator. As used herein, the term “local” refers to a computer, system, operator or user that is not located in the same room as the hardware of the server system 100 but may be located nearby in a different room of the same building or a different building of the same campus, for example. The term “remote” refers to a computer, system or operator that may be located in another city or state, for example, and is connected to the server system via a modem-to-modem connection. The remote operator is typically a client who is authorized to access data and information from the server system 100 through a remote computer 125.
The system interface 105 may include a system interface processor 201 which receives event and request messages, processes these messages, and transmits command, status and response messages to the ISA bus and thereby to the operating system of the CPU 101. In one embodiment, the system interface processor 201 is a PIC16C65 controller chip manufactured by Microchip Technology, Inc. which includes an event memory (not shown) organized as a bit vector, having at least sixteen bits. Each bit in the bit vector represents a particular type of event. Writing an event to the system interface processor 201 sets a bit in the bit vector that represents the event. Upon receiving an event message from the controller 109 (FIG. 1), for example, the system interface 105 sends an interrupt to the CPU 101 via the ISA bus. Upon receiving the interrupt, the CPU 101 will check the status of the system interface 105 in order to ascertain that an event is pending. Alternatively, the CPU 101 may periodically poll the status of the system interface 105 in order to ascertain whether an event is pending. The CPU 101 may then read the bit vector in the system interface processor 201 to ascertain the type of event that occurred and thereafter notify a system operator of the event by displaying an event message on a monitor coupled to the CPU 101. After the system operator has been notified of the event, as described above, he or she may then obtain further information about the system failure which generated the event message by accessing the system log 117. The system interface 105 communicates with the CPU 101 by receiving request messages from the CPU 101 and sending response messages back to the CPU 101. Furthermore, the system interface 105 can send and receive status and command messages to and from the CPU 101. For example, a request message may be sent from a system operator enquiring as to whether the system interface 105 has received any event messages, or enquiring as to the status of a particular processor, subsystem, operating parameter, etc. A request buffer 203 is coupled to the system interface processor 201 and stores, or queues request data in the order that they are received. Similarly, a response buffer 205 is coupled to the system interface processor 201 and queues outgoing response data in the order that they are received. Collectively the request buffer 203 and the response buffer 205 are referred to as the message data register (MDR) 207. In one embodiment, the MDR 207 is eight bits wide and has a fixed address on the ISA bus which may be accessed by the server's operating system via the ISA bus 103 coupled to the MDR 207. As shown in FIG. 2, the MDR 207 has an I/O address (on the ISA bus) of 0CC0h. “Reads” to that address access the response buffer 205 while “writes” to that address access the request buffer 203.
The MDR 207 and the request and response buffers 203 and 205, respectively, transfer messages between a system operator or client and one or more as of the microcontrollers on the I2C bus. The buffers 203 and 205 may utilize the first-in first-out (FIFO) technique. That is, the next message processed is the one that has been in the queue the longest time. The buffers 203 and 205 have two functions: (1) they match speeds between the high-speed ISA bus 103 and the slower system bus 107 (FIG. 1); and (2) they serve as interim buffers for the transfer of messages—this relieves the system interface processor 201 of having to provide this buffer.
The CSR 209 has two functions. The first is to issue commands, and the second is to report on the status of the execution of a command. The system interface 105 commands are usually executed synchronously. That is, after issuing a command, the client polls the CSR status to confirm command completion. In addition to synchronous I/O mode, the client can also request an asynchronous I/O mode for each command by setting a “Asyn Req” bit in the command. In this mode, an interrupt is generated and sent to the ISA bus 103, via the interrupt line 211, after execution of the command has been completed.
The interrupt line 211 may use an ISA IRQ 15 protocol, as mentioned above, which is well-known in the art. Alternatively, the interrupt line 211 may utilize a level-triggered protocol. A level-triggered interrupt request is recognized by keeping the message at the same level, or changing the level of a signal, to send an interrupt. In contrast, an edge-triggered interrupt, for example, is recognized by the signal level transition. A client can either enable or disable the level-triggered interrupt by sending “Enable Ints” and “Disable Ints” commands. If the interrupt line is enabled, the system interface processor sends an interrupt signal to the ISA bus 103, either when an asynchronous I/O is complete or when an event has been detected.
Allocate The first command in a sequence of commands. This command clears both request register 203 and response register 205. The allocate command can only be successfully accomplished if the interface 105 is not presently allocated to another client.
Deallocate: The last command in a sequence of commands. This command clears the “done” bit and the “interface owner ID” fields in the CSR status register.
Message: This command informs the interface 105 that a command to be transmitted over the e2C bus has been placed in the request buffer 203.
Clear Interrupt This command clears the interrupt request bit in the CSR status register.
Reset: This command unconditionally clears all bits in the CSR status register except the “event indication” bit. This command aborts any currently in progress message operation and clears any interrupt.
In one embodiment, the 8bit CSR status register has the following format: bit 7 (error indication)
As described above, the allocate command, when successful, clears both the request buffer and the response buffer. Therefore, at step 420, the client now writes the request message to the request buffer 203. Next, at step 422, the client writes the “message” command to the command status register. Receipt of the “message” command by the interface 105 causes the interface to begin processing the information in the request buffer 203. Next, at step 424, the client waits for an interrupt issued by the interface 105. The interface 105 issues the interrupt once it has received a response to the “message” command from the ultimate recipient or I2C bus. When the interrupt is issued, the client then reads the response buffer 205 as indicated at step 426.
Once the done bit has been set, the process continues to step 542. At step 542 the client reads the message which has been written to the response buffer 205 by the interface 105. Next, step at 544, the client issues the deallocate command which relinquishes control of the interface the details of which were described previously. Next, at step 546, the client confirms that the interface owner ID was successfully cleared by the deallocate command. If the interface owner ID in the command status register was not successfully cleared, the process proceeds to decision block 548 wherein the client either goes to the timeout process or repeats step 546. Once the interface owner ID is successfully cleared, the process is completed.
If the “allocate” command is present, the process continues to step 616 wherein the system interface 105 resets (clears) the response and request buffers 203, 205 and resets the done bit in the CSR. The system interface also sets the CSR Interface Owner ID. The Owner ID bits identify which client has control of the system interface 105. The process then returns to start 602.
If the “de-allocate” command is present at step 612, the process continues to step 618 wherein the system interface 105 clears the response and request buffers 203, 205, resets the done bit in the CSR and clears the Owner ID bits. The process then returns to start 602.
If the “clear done bit” command is present at step 612, the process continues to step 620 wherein the system interface 105 clears the done bit in the CSR. The process then returns to start 602.
Referring now to FIG. 7B, if the “enable interrupt command” is present at step 612, the process continues to step 622. At step 622 the system interface 105 sets the interrupt enable bit in the CSR. The process then returns to start 602.
If the “disable interrupt” command is present at step 612, the process continues to step 624, wherein the system interface 105 clears the interrupt enable bit in the CSR. The process then returns to start 602 (FIG. 6A).
If the “clear interrupt request” command is present at step 612, the process continues to step 626, wherein, the system interface 105 clears the interrupt request bit in the CSR. The process then returns to start 602 (FIG. 6A).
If the “message” command is present at step 612, the process continues to step 628. At step 628, in response to the message command, the system interface 105 reads data from the request buffer 203 (FIG. 2). The first data read from the request buffer by the interface I2C is the ID (address) of the microcontroller for which the message in the request buffer is intended. Next, at step 630 the interface determines whether the ID is its own. If it is, the process continues to step 632 wherein the interface itself responds to the message and then returns to start 602 in FIG. 6A.
Turning next to FIG. 7B, the processing by the driver of interrupts generated by the interface 105 will be described. The process begins after an interrupt has been transmitted to the ISA bus by the interface 105. Starting at step 710 the driver reads the CSR register 209 (see FIG. 2). Next, at step 712, the driver determines whether the “done bit” in the status register is set. This provides a first indication of whether the interrupt indicates that a response to a message has arrived at the interface or whether the interrupt indicates that an event has occurred. If the done bit is set, the process then continues to step 714. At step 714, the driver, in response to the done bit being set, changes the status flag associated with the message to indicate that a message has arrived. The use of this flag is described more fully below with reference to FIG. 7C. The processing then continues on to step 716.
Referring to FIG. 7C, the process by which the driver processes messages in the message queue will be described. First, at step 730, the driver gets the first message in the queue. If no messages are in the queue, the driver waits until a message is queued. Once the driver has obtained the first message in the queue, it proceeds to step 732. At step 732, the driver determines whether the status of the message is “message queued”. If it does, the process proceeds to step 734 wherein the driver writes the allocated command to the CSR 209 to obtain allocation of the interface 105. Next, at step 736 the queued message is written to request buffer 203. Then, at step 738 the driver writes the message command to the CSR 209. Next, at step 740 the driver changes the message status to “result awaited”. The process then returns to step 730.
If at step 732 the driver determines the message does not have “status queued” associated with it, then the process proceeds to step 742. At step 742 the driver determines whether a message result has arrived as indicated by the status flag associated with the message. Note that the status flag is set by the interrupt processing described previously with reference to step 714 in FIG. 7B. If a message has not arrived, the process returns to step 730. If a message has arrived the process continues to step 744 wherein the message being processed is removed from the queue.
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