Source: http://www.google.com/patents/US8068370?dq=7,444,563
Timestamp: 2017-03-27 04:49:28
Document Index: 17312683

Matched Legal Cases: ['art 2', 'Application No. 09158082', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093']

Patent US8068370 - Floating gate memory device with interpoly charge trapping structure - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA charge trapping floating gate is described with asymmetric tunneling barriers. The memory cell includes a source region and a drain region separated by a channel region. A first tunneling barrier structure is disposed above the channel region. A floating gate is disposed above the first tunneling barrier...http://www.google.com/patents/US8068370?utm_source=gb-gplus-sharePatent US8068370 - Floating gate memory device with interpoly charge trapping structureAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8068370 B2Publication typeGrantApplication numberUS 12/409,935Publication dateNov 29, 2011Filing dateMar 24, 2009Priority dateApr 18, 2008Fee statusPaidAlso published asCN101685821A, CN101685821B, EP2110854A2, EP2110854A3, US20090262583Publication number12409935, 409935, US 8068370 B2, US 8068370B2, US-B2-8068370, US8068370 B2, US8068370B2InventorsHang-Ting LueOriginal AssigneeMacronix International Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (45), Referenced by (6), Classifications (36), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetFloating gate memory device with interpoly charge trapping structure
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Dig. 2002, 931-934.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8916920 *Jul 19, 2011Dec 23, 2014Macronix International Co., Ltd.Memory structure with planar upper surfaceUS9255960 *Feb 25, 2013Feb 9, 2016Peking UniversityTesting structure and method for interface trap density of gate oxideUS9312017Aug 12, 2014Apr 12, 2016Apple Inc.Storage in charge-trap memory structures using additional electrically-charged regionsUS9406689Oct 2, 2013Aug 2, 2016Qualcomm IncorporatedLogic finFET high-K/conductive gate embedded multiple time programmable flash memoryUS20140247067 *Feb 25, 2013Sep 4, 2014Peking UniversityTesting structure and method for interface trap density of gate oxideWO2015108742A1Jan 8, 2015Jul 23, 2015Apple Inc.Improved storage in charge-trap memory structures using additional electrically-charged regions* Cited by examinerClassifications U.S. Classification365/185.28, 365/185.18, 257/E21.422, 257/E21.423, 257/E29.309, 257/315International ClassificationH01L21/336, H01L29/792, H01L29/788, G11C16/06Cooperative ClassificationH01L27/11568, H01L27/115, H01L29/792, G11C16/0408, H01L27/11521, H01L29/4234, G11C16/10, H01L29/42324, H01L21/28282, H01L21/28273, H01L27/11573, H01L27/11526, H01L29/7883European ClassificationH01L29/792, H01L27/115G6, H01L21/28F, H01L27/115G4, H01L27/115F4, H01L27/115F6, H01L29/423D2B3, H01L27/115, G11C16/04F, H01L21/28G, H01L29/788B4, G11C16/10, H01L29/423D2B2Legal EventsDateCodeEventDescriptionMar 24, 2009ASAssignmentOwner name: MACRONIX INTERNATIONAL CO., LTD., TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LUE, HANG-TING;REEL/FRAME:022442/0419Effective date: 20090319Mar 11, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services