Source: https://patents.google.com/patent/US7279792B2/en
Timestamp: 2020-01-21 14:58:00
Document Index: 534563419

Matched Legal Cases: ['Application No. 2004', 'Application No. 200410044719', 'Application No. 200410044719', 'Application No. 2004', 'Application No. 10', 'Application No. 2004', 'Application No. 2004', 'Application No. 10']

US7279792B2 - Semiconductor device and method of manufacturing same - Google Patents
US7279792B2
US7279792B2 US10/842,412 US84241204A US7279792B2 US 7279792 B2 US7279792 B2 US 7279792B2 US 84241204 A US84241204 A US 84241204A US 7279792 B2 US7279792 B2 US 7279792B2
US10/842,412
US20050167800A1 (en
2004-01-19 Priority to JP2004-010688 priority
2004-05-10 Application filed by Casio Micronics Co Ltd filed Critical Casio Micronics Co Ltd
2004-05-10 Assigned to CASIO MICRONICS CO., LTD. reassignment CASIO MICRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NAYA, KINICHI
2005-08-04 Publication of US20050167800A1 publication Critical patent/US20050167800A1/en
2007-10-09 Publication of US7279792B2 publication Critical patent/US7279792B2/en
2011-12-09 Assigned to TERAMIKROS, INC. reassignment TERAMIKROS, INC. CORPORATE SEPARATION Assignors: CASCIO MICRONICS CO., LTD.
2012-02-01 Assigned to TERAMIKROS, INC. reassignment TERAMIKROS, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE STREET ADDRESS FROM 10-6 IMAI 3-CHOME TO 10-6, IMAI 3-CHOME PREVIOUSLY RECORDED ON REEL 027357 FRAME 0151. ASSIGNOR(S) HEREBY CONFIRMS THE CORPORATE SEPARATION. Assignors: CASCIO MICRONICS CO., LTD.
-1 NSG Substances 0 description 1
According to this invention, a semiconductor device has an upper surface on which an external connection electrode is formed and a lower surface which opposes the upper surface and is in a mirror surface state. A roughened region roughened by laser marking is formed at part of the lower surface. The roughened region includes a product information mark of the semiconductor device itself. The product information mark is printed by laser marking. The number, size, shape, and layout position of the roughened regions are decided to make it possible to, when the lower surface is irradiated with light, read the product information from the difference in light reflectance between the roughened region and mirror-finished region.
This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-010688, filed Jan. 19, 2004, the entire contents of which are incorporated herein by reference.
The present invention has been made in consideration of the above situation, and has as its first object to provide a semiconductor device which makes it possible to accurately recognize, by image processing, a mark of product information or the like formed on the lower surface even when it is mirror-finished, and accordingly, execute automatic testing by an optical test apparatus, and a method of manufacturing the same.
The best mode for carrying out the present invention will be described below with reference to the accompanying drawing.
FIG. 6 is a plan view showing an example of the lower surface of a semiconductor device according to the first embodiment of the present invention.
As shown in FIG. 15, the dry film resist 24 is removed by using an alkaline dry film resist release agent to expose the UBM 19. As shown in FIG. 16, the exposed UBM 19 is wholly removed from the surface layer, i.e., the Cu layer by using a (sulfuric acid+hydrogen peroxide) solution- or alkaline-based Cu etchant at a temperature of about 30° C. and by using the redistribution layer 23 as a mask. When the Cu layer removal is ended, cleaning and drying are performed. The exposed Ti layer is etched. The etchant used is a Ti etchant such as a hydrogen peroxide at a liquid temperature of about 50° C. to 65° C. The Ti layer is dipped into the etchant and removed. When the removal is ended, the resultant structure is cleaned by DIW and dried.
As shown in FIG. 17, a sealing resin 28 made of, e.g., an epoxy resin liquid is applied to entirely cover the wafer 10 by a sealing method such as transfer molding or printing such that the post electrodes 26 are completely buried. The sealing resin 28 is heated to about 120° C. to 150° C. in an inert atmosphere or atmosphere for about 60 min by using an oven or furnace (not shown) and set.
FIG. 25 is an enlarged plan view showing another example of the roughened region 14. Referring to FIG. 25, adjacent craters 40 overlap. To promote diffuse reflection and lower the contrast upon light irradiation on the lower surface 10 (#a), as many craters 40 as possible are formed in the roughened region 14. Hence, this layout can be employed. However, to form craters 40 at such a high density, the number of laser irradiation points increases. Hence, formation of the roughened region 14 is time-consuming. The craters 40 are preferably formed at a density sufficient to obtain a minimum necessary diffuse reflection effect. In consideration of the above point, in this embodiment, a separation distance D along the lower surface 10 (#a) between the adjacent craters 40 is set to be equal to or smaller than the diameter W, i.e., the maximum width of the crater 40 and, more preferably, equal to or smaller than ½ the maximum width, as shown in FIG. 24.
From the viewpoint of decreasing the contrast of the lower surface 10 (#a), the number density of the craters 40 in the roughened region 14 is preferably as high as possible. However, to form craters 40 at a high density, the number of laser irradiation points increases. Hence, formation of the roughened region 14 is time-consuming. In this embodiment, however, the separation distance D along the lower surface 10 (#a) between the adjacent craters 40 is set to be equal to or smaller than the diameter, i.e., the maximum width of the crater 40 and, more preferably, equal to or smaller than ½ the maximum width. Hence the minimum necessary diffuse reflection effect can be implemented, and the time required for formation of the roughened region 14 by laser marking can be shortened.
FIG. 31 is a longitudinal sectional view showing the packaging structure of a semiconductor device 16 according to this embodiment.
US10/842,412 2004-01-19 2004-05-10 Semiconductor device and method of manufacturing same Expired - Fee Related US7279792B2 (en)
JP2004-010688 2004-01-19
US20050167800A1 US20050167800A1 (en) 2005-08-04
US7279792B2 true US7279792B2 (en) 2007-10-09
US10/842,412 Expired - Fee Related US7279792B2 (en) 2004-01-19 2004-05-10 Semiconductor device and method of manufacturing same
US20160329304A1 (en) * 2013-05-07 2016-11-10 Ps4 Luxco S.A.R.L. Semiconductor device and method of manufacturing semiconductor device
JPS60377A (en) 1983-06-17 1985-01-05 Taiyo Musen Kk Antenna device of direction detector
US6218199B1 (en) 1998-02-20 2001-04-17 Kazuo Sato Silicon substrate with identification data
JP2003318335A (en) 2002-04-19 2003-11-07 Oki Electric Ind Co Ltd Semiconductor device, manufacturing method thereof and position measuring method of semiconductor device
Chinese Office Action dated Mar. 17, 2006 in regards to corresponding Chinese Patent Application No. 200410044719.1 with English translation.
Chinese Office Action dated Sep. 8, 2006 issued in regards to corresponding Chinese Patent Application No. 200410044719.1 (w/English translation).
English Translation of Japanese Office Action issued Mar. 7, 2006 in connection with Japanese Application No. 2004-010688.
English Translation of Korean Office Action issued Dec. 20, 2005 in connection with Korean Application No. 10-2004-003835.
Japanese Office Action dated Aug. 22, 2006 in regards to corresponding Japanese Patent Application No. 2004-010688 with English translation.
Japanese Office Action issued Mar. 7, 2006 in connection with Japanese Application No. 2004-010688.
Korean Office Action issued Dec. 20, 2005 in connection with Korean Application No. 10-2004-0033835.
JP2005203695A (en) 2005-07-28
DE69534976T2 (en) 2006-12-28 Vertical interconnection process for silicone segments
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NAYA, KINICHI;REEL/FRAME:015313/0104