Source: http://www.google.com/patents/US7479677?dq=6008737
Timestamp: 2018-01-19 20:35:48
Document Index: 591494584

Matched Legal Cases: ['Application No. 02826596', 'Application No. 02826596', 'Application No. 02826596', 'Application No. 02', 'Application No. 07002287', 'Application No. 07002289', 'Application No. 07002288', 'Application No. 07002289', 'Application No. 204', 'Application No. 91132182', 'Application No. 02826596', 'Application No. 02826596']

Patent US7479677 - Multi-state non-volatile integrated circuit memory systems that employ ... - Google Patents
Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one...http://www.google.com/patents/US7479677?utm_source=gb-gplus-sharePatent US7479677 - Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
Publication number US7479677 B2
Application number US 12/020,266
Also published as CN1610976A, CN100539195C, DE60219666D1, DE60219666T2, EP1446840A1, EP1446840A4, EP1446840B1, EP1777750A2, EP1777750A3, EP1777750B1, EP1777751A2, EP1777751A3, EP1777751B1, EP1777752A2, EP1777752A3, EP1777752B1, US6925007, US7341918, US7342279, US7579247, US7834392, US20030109093, US20050157551, US20050180210, US20080116509, US20080119026, US20090286370, WO2003038907A1
Publication number 020266, 12020266, US 7479677 B2, US 7479677B2, US-B2-7479677, US7479677 B2, US7479677B2
Inventors Eliyahou Harari, George Samachisa, Jack H. Yuan, Daniel C. Guterman
Patent Citations (98), Non-Patent Citations (46), Referenced by (9), Classifications (36), Legal Events (4)
US 7479677 B2
1. A non-volatile memory system formed on a semiconductor substrate, comprising:
(a) an array of charge storage transistors, comprising:
a plurality of eight or more conductive word lines with lengths extending across the substrate in a first direction and neighboring each other in a second direction, the first and second directions being orthogonal with each other, and
regions of dielectric charge trapping material sandwiched between the conductive word lines and a surface of the substrate in a manner to provide a plurality of eight or more series connected storage transistors in individual columns extending in the second direction between terminations thereof, and
(b) circuits peripheral to the array, comprising:
a programming circuit that includes a source of voltages connectable to at least the word lines to cause charge to be transferred into regions of dielectric charge trapping material along an addressed word line and within addressed columns of storage transistors by Fowler-Nordheim tunneling, and
a reading circuit including a source of voltages and sensing circuits connectable to at least the word lines and terminations of the columns of storage transistors in a manner that determines a parameter related to a level of charge stored in dielectric regions along an addressed word line and within addressed columns of storage transistors.
2. The memory system of claim 1, wherein the array additionally includes a plurality of discrete source and drain regions formed in the substrate between adjacent word lines along the columns.
3. The memory system of claim 1, wherein the word lines of the array are positioned adjacent each other in the second direction with a layer of dielectric therebetween and without substrate source or drain regions therebetween.
4. The memory system of claim 1, wherein the programming circuit places a voltage on the addressed word line is greater than that placed on the others of the word lines extending across the columns when programming the regions of dielectric material sandwiched by said addressed word line.
5. The memory system of claim 1, wherein
the programming circuit is characterized by transferring charge into addressed individual regions of dielectric charge trapping material in a manner that causes their storage transistors to be programmed into one of more than two threshold levels corresponding to data being programmed, and
the reading circuit is characterized by generating a parameter related to the programmed more than two threshold levels of the addressed one of said dielectric regions,
thereby to store more than one bit of data in individual regions of dielectric charge trapping material.
6. The memory system of claim 1, wherein the dielectric regions of the individual columns are provided in a layer of dielectric charge trapping material formed in strips extending continuously along lengths of the columns in the second direction and spaced apart in the first direction.
7. The memory system of claim 6, additionally comprising lengths of isolation dielectric extending in the second direction and spaced apart in the first direction between the strips of charge storage material.
8. The memory system of claim 1, wherein the programming circuit and reading circuit additionally comprise a state machine that controls at least application of programming and reading voltages to the array of charge storage transistors.
9. The memory system of claim 1, wherein the plurality of conductive word lines comprise a metal material and the dielectric material comprises a first oxide layer on the substrate, a nitride layer over the first oxide layer and a second oxide layer over the nitride layer, the second oxide layer also being contacted by the word line.
10. A non-volatile memory system formed on a semiconductor substrate, comprising:
(a) an array of memory charge storage transistors, comprising:
a plurality of eight or more conductive word lines with lengths extending across the substrate in a first direction and adjacent each other in a second direction with a layer of dielectric therebetween but without source and drain regions therebetween, the first and second directions being orthogonal with each other, and
a programming circuit that includes a source of voltages connectable to the array to cause charge to be transferred into addressed regions of dielectric charge trapping material by Fowler-Nordheim tunneling, and
a reading circuit including a source of voltages and sensing circuits connectable to terminations of the columns of the array that determine a parameter related to a level of charge stored in dielectric regions along an addressed word line and within addressed columns of storage transistors.
11. The memory system of claim 10, wherein
12. The memory system of claim 10, wherein the plurality of conductive word lines comprise a metal material and the dielectric material comprises a first oxide layer on the substrate, a nitride layer over the first oxide layer and a second oxide layer over the nitride layer, the second oxide layer also being contacted by the word line.
13. A non-volatile memory system formed on a semiconductor substrate, comprising:
regions of dielectric charge trapping material sandwiched between the conductive word lines and a surface of the substrate in a manner to provide a plurality of eight or more series connected storage transistors in individual columns extending in the second direction between terminations thereof,
a programming circuit that includes a source of voltages connectable to the array in a manner that causes charge to be transferred into addressed regions of dielectric charge trapping material, wherein the programming circuit is characterized by causing charge to be transferred into addressed individual regions of dielectric charge trapping material to program them into one of more than two threshold levels corresponding to data being programmed, and
a reading circuit that includes a source of voltages connectable to the array that determine a parameter related to a level of charge stored in an addressed one of said dielectric regions within the at least one addressed column, wherein the reading circuit is characterized by generating a parameter related to the programmed more than two threshold levels of the addressed one of said dielectric regions, wherein more than one bit of data are stored in the individual regions of dielectric charge trapping material.
14. The memory system of claim 13, wherein the array additionally includes a plurality of discrete source and drain regions formed in the substrate between adjacent word lines along the columns.
15. The memory system of claim 13, wherein the word lines of the array are positioned immediately adjacent each other in the second direction with a layer of dielectric therebetween and without substrate source or drain regions therebetween.
16. The memory system of claim 13, wherein the programming circuit causes the regions of dielectric material to be programmed by Fowler-Nordheim tunneling.
17. The memory system of claim 13, wherein the word lines individually comprise a metal material and the dielectric charge trapping material includes a first oxide layer on the substrate, a nitride layer over the first oxide layer and a second oxide layer over the nitride layer, the second oxide layer also being contacted by the word line.
18. The memory system of claim 13, wherein the dielectric regions of the individual columns are provided in a layer of dielectric charge trapping material formed in strips extending continuously along lengths of the columns in the second direction and spaced apart in the first direction.
19. The memory system of claim 18, additionally comprising lengths of isolation dielectric extending in the second direction and spaced apart in the first direction between the strips of charge storage material.
20. The memory system of claim 13, wherein the programming circuit and reading circuit additionally comprise a state machine that controls at least application of programming and reading voltages to the array of charge storage transistors.
This is a continuation of application Ser. No. 11/075,423, filed Mar. 7, 2005, now U.S. Pat. No. 7,342,279, which in turn is a divisional of application Ser. No. 10/280,352, filed Oct. 25, 2002, now U.S. Pat. No. 6,925,007, which in turn is a continuation-in-part of application Ser. No. 10/161,235, filed May 31, 2002, now abandoned, which in turn is a continuation-in-part of application Ser. No. 10/002,696, filed Oct. 31, 2001, now U.S. Pat. No. 6,897,522, which applications are incorporated herein in their entirety by this reference.
It is continuously desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell. This is accomplished by dividing a window of a floating gate charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, a cell with sixteen states stores four bits of data, and so on. A multiple state flash EEPROM structure and operation is described in U.S. Pat. Nos. 5,043,940 and 5,172,338, which patents are incorporated herein by this reference.
Increased data density can also be achieved by reducing the physical size of the memory cells and/or of the overall array. Shrinking the size of integrated circuits is commonly performed for all types of circuits as processing techniques improve over time to permit implementing smaller feature sizes. But since there are limits of how far a given circuit layout can be shrunk by scaling through simple demagnification, efforts are so directed toward redesigning cells so that one or more features takes up less area.
In a particular example, the Dual Storage Element Cell described above in the Background has charge-storing dielectric substituted for each of the two floating gates of the memory cells. This dielectric is sandwiched between conductive steering gates and the substrate to form two functionally separate charge storage elements over channels of the memory cells between their sources and drains. One region of charge is preferably stored in each of these two storage elements, which lie along the length of the cell channels on opposite sides of the select transistors, although two such regions may alternatively be used to obtain a further increase in charge storage density. The level of charge in a region affects the threshold level of the portion of the length of the cell channel beneath that region. Two or more such charge levels, and thus two or more different threshold levels, are defined for programming into each of the two charge storage regions of each memory cell. Programming and reading of a selected one of the two charge storage regions of an addressed cell is accomplished in the same manner as in the dual floating gate systems, by turning on the select transistor and driving the other channel portion strongly conductive. This renders the selected charge storage region of the addressed cell responsive to voltages placed on its source, drain and gates. Specific examples of Dual Storage Element Cell arrays in which the charge storage dielectric may be substituted for floating gates are given in U.S. Pat. Nos. 6,091,633, 6,103,573 and 6,151,248, and in application Ser. No. 09/667,344, filed Sep. 22, 2000, by Yuan et al., entitled “Non-volatile Memory Cell Array having Discontinuous Source and Drain Diffusions Contacted by Continuous Bit Line Conductors and Methods of Forming,” now U.S. Pat. No. 6,512,263; Ser. No. 09/925,134, filed Aug. 8, 2001, by Harari et al., entitled “Non-Volatile Memory Cells Utilizing Substrate Trenches,” now U.S. Pat. No. 6,936,887; and Ser. No. 09/925,102, filed Aug. 8, 2001, by Yuan et al., entitled “Scalable Self-Aligned Dual Floating Gate Memory Cell Array and Methods of Forming the Array,” now U.S. Pat. No. 6,762,092, which patents and patent applications are incorporated herein in their entirety by this reference.
In another specific example, a NAND array has its memory cell floating gates replaced by storage element regions of a dielectric layer. This dielectric is sandwiched between word lines and the substrate surface. Otherwise, the array is operated as described in U.S. patent application Ser. No. 09/893,277, filed Jun. 27, 2001, now U.S. Pat. No. 6,522,580 which application is incorporated herein by this reference. Each storage element region may be operated to store more than two charge levels, thus storing more than one bit of data in each such region.
FIGS. 23A and 23B are cross-sectional views of the array of FIG. 22, taken at respective sections VII-VII and VIII-VIII;
FIGS. 25A, 25B and 25C illustrate one process for forming a memory array of the type illustrated in FIGS. 22-24;
Similarly, reading the right region 173, threshold value 179, 0 volt is applied to substrate 163 and source 153, drain 152 is held at a low voltage, and the word line 160 is held at a high voltage. The voltage of the select gate is then varied, and the bit line current monitored to detect the threshold of the region 173.
Exemplary reading voltages for the cell of FIG. 9, when only charge storage regions 172 and 174 have been programmed in the manner described above, can be given as follows:
Reading region 173, 0 volt is applied to substrate 163 and source 152, word line 160 is held at a sufficiently high voltage to ensure regions 171 and 172 are conducting when programmed to their highest threshold states, and a voltage sufficient to deplete through region 174 is applied to drain 153 (approximately 3 volts). The voltage of the select gate 157 is then varied, and the bit line current monitored to detect the threshold of the region 173.
An example is useful to illustrate this. Five programmed threshold level ranges can be designated, from a low of 0, then 1, 2, 3 in order and with 4 as the highest. Four of these are used in each of the charge storage regions 171-174, an upper set of threshold levels 1-4 for each of the outer regions 172 and 174 and a lower set of 0-3 for the inter regions 171 and 173. Ten storage states may then be designated for each charge storing pair from the permitted combinations of threshold voltages of the individual charge storage regions, as follows:
There is also a preferred order of programming the threshold levels in each of the four regions. Namely, both inner regions 171 and 173 are programmed before programming the outer regions 172 and 174. Region 173 is first programmed by source side injection in each cell of a row of such cells that share a common word line. Regions 171 are then similarly programmed along the row, with a voltage VSG placed on their individual control gates 157 that is dependent on the level of charge that has been programmed into the regions 173 under them, in order to enable source side injection. The regions 172 and 174 are then programmed in either order by hot-electron injection.
With reference to FIG. 12, an enlarged view of one of the memory cells of FIG. 11A is given. The cell can be operated to trap charge within the dielectric layer 201 in two regions 211 and 213, adjacent to each side of a select transistor gate 198′ that is part of the word line 198, by programming with the source-side injection technique. If programmed by the channel hot-electron injection technique, on the other hand, charge storage regions 212 and 214 are located adjacent respective source and drain regions 186 and 187 instead. Alternatively, all four of the charge storage regions 211-214 may be utilized by sequentially programming them with the source-side injection and hot-electron injection techniques, each region either in two-states or more than two-states, as limited by the same considerations of threshold relationships that are discussed above with respect to the example of FIG. 9, but without the constraint of writing order sequence. The portions of the dielectric 201 within the memory cell on either side of the select transistor gate 198′ and beneath the word line 198 define the two storage elements of the cell that replace the two conductive floating gates of the Dual Storage Element Cell arrays and systems referenced above. The dielectric layer 201, however, can extend beyond these storage elements. In one form, the layer 201 is formed in strips having individual widths that extend in the x-direction between select transistors of memory cells in adjacent columns and lengths that extend in the y-direction across a large number of rows of memory cells. These strips, and the select transistor gate dielectric between them, can be self-aligned with edges of the steering gates, such as the edges of the steering gates 192 and 193 that are shown in FIG. 12.
The effect of charge stored in the regions 211 and 213 of the dielectric 201 is shown by portions 217 and 219 of a threshold voltage curve 215 in FIG. 12, similar to the other two examples described above, when programmed by source side injection. Source side programming differs in this cell from that of FIG. 9 by moving the terminal which supplies the threshold plus 1 v bias condition. In FIG. 12 this terminal is the word line 198 connected to the select gate 198′ for both storage regions 211 and 213. In addition, the steering gate above the storage regions not being programmed are now driven to a sufficiently high over-drive voltage level (for example 8 volts). For example when storage region 211 is being programmed, steering gate 193 is driven to the overdrive voltage, and word line 198 is driven to about 1 volt above the threshold voltage of select transistor 198′.
Because of the above use of different steering gate voltage levels imposed on the two steering gates during programming of the middle region 401 of the memory cells of FIG. 15, this requires that the voltage on each of the control (steering) gates, as exemplified by elements 189-194 of the array in FIG. 10, be independently controllable. Since it is usually impractical to provide, on the same circuit chip as the array, such a large decoder as required to handle the number of steering gates of a large array, they are preferably connected together in a manner schematically illustrated in FIG. 16 for a few memory cells of one row. Such a connection is further described with respect to FIG. 6 of afore-referenced U.S. patent application Ser. No. 09/871,333, filed May 31, 2001, now U.S. Pat. No. 6,532,172. Every fourth steering gate along the row is connected to a common steering gate line, in this example, which allows the simultaneous programming and reading of one charge storage region of every other cell along the row. A steering gate line 411 is connected to steering gate 191 and others, line 412 to gate 192 and others, line 413 to gates 189, 193 and others, and line 414 to steering gates 190, 194 and others. The word line 198 is connected with the select gate of each of the cells in the row, including select gates 198′ and 198″. Other rows in the array similarly have distinct word lines.
A large number of individually addressable memory cells 11 are arranged in a regular array of rows and columns, although other physical arrangements of cells are certainly possible. Bit lines, designated herein to extend along columns of the array 11 of cells, are electrically connected with a bit line decoder and driver circuit 13 through lines 15. Word lines, which are designated in this description to extend along rows of the array 11 of cells, are electrically connected through lines 17 to a word line decoder and driver circuit 19. Steering gates, which extend along columns of memory cells in the array 11, are electrically connected to a steering gate decoder and driver circuit 21 through lines 23. The steering gates and/or bit lines may be connected to their respective decoders by techniques described in a co-pending patent application by Harari et al. entitled “Steering Gate and Bit Line Segmentation in Non-Volatile Memories,” Ser. No. 09/871,333, filed May 31, 2001, now U.S. Pat. No. 6,532,172, which application is incorporated herein by this reference. Each of the decoders 13, 19 and 21 receives memory cell addresses over a bus 25 from a memory controller 27. The decoder and driving circuits are also connected to the controller 27 over respective control and status signal lines 29, 31 and 33. Voltages applied to the steering gates and bit lines are coordinated through a bus 22 that interconnects the steering gates and bit line decoder and driver circuits 13 and 21.
The memory cell array of the system of FIG. 21 is desirably divided into segments. As will be noted from the second and third examples described above, the sources, drains and steering gates can extend without limit across the entire array in the y-direction unless segmented. These dielectric arrays may be divided into segments that each extends only a portion of the distance across the full array in the y-direction. The sources and drains at an end of a segment are connected through switching transistors to global bit lines, normally made of metal. The steering gates may be similarly connected through switching transistors to global steering lines. Alternatively, the steering gates may be connected to steering gate line bussing associated with the segment, in the manner previously described with respect to FIG. 16. During programming, reading or erasing operations, one selected segment is usually connected to a set of global bit lines at a time, as well as to either a set of global steering lines or to associated steering gate line bussing, depending upon the segmentation embodiment being used. Such segmentation is described with respect to FIG. 10C of aforementioned U.S. Pat. No. 5,712,180, and in U.S. patent application Ser. No. 09/871,333, filed May 31, 2001, now U.S. Pat. No. 6,532,172.
Operation of a memory system such as illustrated in FIG. 21 is described in patents and pending applications identified above, and in other patents and pending applications assigned to SanDisk Corporation, assignee of the present application. Those of the cited references that describe the structure, processing or operation of a memory system using floating gates as the storage elements will be recognized as being relevant to implementing the systems using dielectric storage elements in place of the floating gates. In addition, U.S. patent application Ser. No. 09/793,370, filed Feb. 26, 2001, now U.S. Pat. No. 6,738,289, describes a data programming method applied to either floating gate or dielectric storage element systems, which application is incorporated herein by this reference.
The dielectric strips 245-249 are formed directly on the surface of the substrate 257. The dielectric material and other characteristics are preferably those of one of the two described above with respect to FIGS. 6A and 6B. The word lines 241-244 are, in turn, positioned directly on top of these dielectric strips in regions that become charge storage regions. Charge storage regions 265-267 are indicated in FIG. 23A along the word line 242, and regions 269, 265, 271 and 272 in FIG. 23B along the dielectric strip 246. Doped source and drain regions are formed in surface areas of the substrate 257 between the word lines and the isolation dielectric. For example, source and drain regions 261-263 are positioned in between word lines of a column formed between dielectric isolation regions 251 and 252. This column forms one string of series connected memory cells, as shown in the cross-sectional view of FIG. 23B and represented by an electrical equivalent circuit diagram in FIG. 24. At each end of the string is a switching select transistor, shown in FIG. 23B at one end to have a gate 275 and at the other end to have a gate 277. Terminals 279 and 281 form electrical ends of the string of storage and select transistors. One of these terminals is usually connected to an individual bit line and the other to a common potential. There are a very large number of such transistor column strings, arranged in columns extending in the y-direction, in a typical memory cell array.
Yet another process to form a somewhat different NAND array is illustrated in FIGS. 26A-26D. FIGS. 26A-26C show the development of the structure along section VII-VII of the plan view of FIG. 22, while FIG. 26D shows the intermediate structure of FIG. 26C along the orthogonal section VIII-VIII. A principal difference in the process of FIGS. 26A-26D is the formation of a substrate etch mask with strips of polysilicon instead of nitride, portions of those strips in areas of the memory cells then being retained as part of the word lines. Also, the resulting charge storage dielectric layer is not continuous over the entire memory cell array. Reference numbers of elements that correspond to those of FIGS. 22-25C are the same in FIGS. 26A-26D, with a triple prime (′″) included.
US3979582 Sep 17, 1974 Sep 7, 1976 Westinghouse Electric Corporation Discrete analog processing system including a matrix of memory elements
US4057788 Oct 6, 1975 Nov 8, 1977 Raytheon Company Semiconductor memory structures
US4112507 Jan 30, 1976 Sep 5, 1978 Westinghouse Electric Corp. Addressable MNOS cell for non-volatile memories
US4173766 Sep 16, 1977 Nov 6, 1979 Fairchild Camera And Instrument Corporation Insulated gate field-effect transistor read-only memory cell
US4398248 Oct 20, 1980 Aug 9, 1983 Mcdonnell Douglas Corporation Adaptive WSI/MNOS solid state memory system
US4527257 Aug 25, 1982 Jul 2, 1985 Westinghouse Electric Corp. Common memory gate non-volatile transistor memory
US4622656 Dec 15, 1983 Nov 11, 1986 Seiko Instruments & Electronics Ltd. Non-volatile semiconductor memory
US4870470 Oct 16, 1987 Sep 26, 1989 International Business Machines Corporation Non-volatile memory cell having Si rich silicon nitride charge trapping layer
US5168334 Jan 16, 1991 Dec 1, 1992 Texas Instruments, Incorporated Non-volatile semiconductor memory
US5198996 Apr 10, 1992 Mar 30, 1993 Matsushita Electronics Corporation Semiconductor non-volatile memory device
US5278439 Aug 29, 1991 Jan 11, 1994 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
US5311049 Oct 13, 1992 May 10, 1994 Rohm Co., Ltd. Non-volatile semiconductor memory with outer drain diffusion layer
US5424978 Mar 14, 1994 Jun 13, 1995 Nippon Steel Corporation Non-volatile semiconductor memory cell capable of storing more than two different data and method of using the same
US5426605 Aug 18, 1993 Jun 20, 1995 U.S. Philips Corporation Semiconductor memory device
US5436481 Jan 19, 1994 Jul 25, 1995 Nippon Steel Corporation MOS-type semiconductor device and method of making the same
US5440505 Jan 21, 1994 Aug 8, 1995 Intel Corporation Method and circuitry for storing discrete amounts of charge in a single memory element
US5539690 Jun 2, 1994 Jul 23, 1996 Intel Corporation Write verify schemes for flash memory with multilevel cells
US5705415 Oct 4, 1994 Jan 6, 1998 Motorola, Inc. Process for forming an electrically programmable read-only memory cell
US5824584 Jun 16, 1997 Oct 20, 1998 Motorola, Inc. Method of making and accessing split gate memory device
US5851881 Oct 6, 1997 Dec 22, 1998 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making monos flash memory for multi-level logic
US5889303 Apr 7, 1997 Mar 30, 1999 Motorola, Inc. Split-Control gate electrically erasable programmable read only memory (EEPROM) cell
US5912844 Jan 28, 1998 Jun 15, 1999 Macronix International Co., Ltd. Method for flash EEPROM data writing
US5942787 Nov 18, 1996 Aug 24, 1999 Advanced Micro Devices, Inc. Small gate electrode MOSFET
US5946231 May 5, 1998 Aug 31, 1999 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US5969383 Jun 16, 1997 Oct 19, 1999 Motorola, Inc. Split-gate memory device and method for accessing the same
US6010934 Mar 2, 1998 Jan 4, 2000 Texas Instruments - Acer Incorporated Method of making nanometer Si islands for single electron transistors
US6054734 Nov 5, 1997 Apr 25, 2000 Sony Corporation Non-volatile memory cell having dual gate electrodes
US6091633 Aug 9, 1999 Jul 18, 2000 Sandisk Corporation Memory array architecture utilizing global bit lines shared by multiple cells
US6101125 May 20, 1998 Aug 8, 2000 Motorola, Inc. Electrically programmable memory and method of programming
US6103573 Jun 30, 1999 Aug 15, 2000 Sandisk Corporation Processing techniques for making a dual floating gate EEPROM cell array
US6104072 Jul 13, 1995 Aug 15, 2000 Sony Corporation Analogue MISFET with threshold voltage adjuster
US6137718 Jul 8, 1997 Oct 24, 2000 Siemens Aktiengesellschaft Method for operating a non-volatile memory cell arrangement
US6177318 Oct 18, 1999 Jan 23, 2001 Halo Lsi Design & Device Technology, Inc. Integration method for sidewall split gate monos transistor
US6248633 Oct 25, 1999 Jun 19, 2001 Halo Lsi Design & Device Technology, Inc. Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
US6281075 Jan 27, 1999 Aug 28, 2001 Sandisk Corporation Method of controlling of floating gate oxide growth by use of an oxygen barrier
US6313503 Jun 22, 2000 Nov 6, 2001 Samsung Electronics Co., Ltd. MNOS-type memory using single electron transistor and driving method thereof
US6331953 Oct 26, 2000 Dec 18, 2001 Advanced Micro Devices Intelligent ramped gate and ramped drain erasure for non-volatile memory cells
US6346725 May 22, 1998 Feb 12, 2002 Winbond Electronics Corporation Contact-less array of fully self-aligned, triple polysilicon, source-side injection, nonvolatile memory cells with metal-overlaid wordlines
US6349062 Oct 11, 2000 Feb 19, 2002 Advanced Micro Devices, Inc. Selective erasure of a non-volatile memory cell of a flash memory device
US6366501 Oct 11, 2000 Apr 2, 2002 Advanced Micro Devices, Inc. Selective erasure of a non-volatile memory cell of a flash memory device
US6388293 Jun 16, 2000 May 14, 2002 Halo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, operating method of the same and nonvolatile memory array
US6399441 May 21, 2001 Jun 4, 2002 Halo Lsi Device & Design Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
US6406960 Oct 25, 1999 Jun 18, 2002 Advanced Micro Devices, Inc. Process for fabricating an ONO structure having a silicon-rich silicon nitride layer
US6413821 Sep 18, 2001 Jul 2, 2002 Seiko Epson Corporation Method of fabricating semiconductor device including nonvolatile memory and peripheral circuit
US6418062 Mar 1, 2001 Jul 9, 2002 Halo Lsi, Inc. Erasing methods by hot hole injection to carrier trap sites of a nonvolatile memory
US6436768 Jun 27, 2001 Aug 20, 2002 Advanced Micro Devices, Inc. Source drain implant during ONO formation for improved isolation of SONOS devices
US6445030 Jan 30, 2001 Sep 3, 2002 Advanced Micro Devices, Inc. Flash memory erase speed by fluorine implant or fluorination
US6459622 Mar 15, 2002 Oct 1, 2002 Halo Lsi, Inc. Twin MONOS memory cell usage for wide program
US6472706 Jul 11, 2001 Oct 29, 2002 Koninklijke Philips Electronics Nv Semiconductor device
US6477088 Dec 5, 2001 Nov 5, 2002 Halo Lsi Design & Device Technology, Inc. Usage of word voltage assistance in twin MONOS cell during program and erase
US6487121 Jul 5, 2001 Nov 26, 2002 Advanced Micro Devices, Inc. Method of programming a non-volatile memory cell using a vertical electric field
US6493266 Apr 9, 2001 Dec 10, 2002 Advanced Micro Devices, Inc. Soft program and soft program verify of the core cells in flash memory array
US6531350 Nov 21, 2001 Mar 11, 2003 Halo, Inc. Twin MONOS cell fabrication method and array organization
US6531732 Jul 3, 2001 Mar 11, 2003 Sharp Kabushiki Kaisha Nonvolatile semiconductor memory device, process of manufacturing the same and method of operating the same
US6548861 Jul 6, 2001 Apr 15, 2003 Infineon Technologies Ag Memory cell, memory cell arrangement and fabrication method
US6549463 Dec 14, 2001 Apr 15, 2003 Halo Lsi, Inc. Fast program to program verify method
US6555865 Jul 10, 2001 Apr 29, 2003 Samsung Electronics Co. Ltd. Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same
US6580120 May 28, 2002 Jun 17, 2003 Interuniversitair Microelektronica Centrum (Imec Vzw) Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure
US6636438 Jul 8, 2002 Oct 21, 2003 Halo Lsi, Inc. Control gate decoder for twin MONOS memory with two bit erase capability
US6670240 Aug 13, 2002 Dec 30, 2003 Halo Lsi, Inc. Twin NAND device structure, array operations and fabrication method
US6670669 Feb 28, 2000 Dec 30, 2003 Fujitsu Limited Multiple-bit non-volatile memory utilizing non-conductive charge trapping gate
US6677200 Jul 12, 2002 Jan 13, 2004 Samsung Electronics Co., Ltd. Method of forming non-volatile memory having floating trap type device
US6709922 Jan 23, 2002 Mar 23, 2004 Seiko Epson Corporation Method of manufacturing semiconductor integrated circuit device including nonvolatile semiconductor memory devices
US6735118 Jul 8, 2002 May 11, 2004 Halo Lsi, Inc. CG-WL voltage boosting scheme for twin MONOS
US6858906 Jun 27, 2002 Feb 22, 2005 Samsung Electronics Co., Ltd. Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
US6897522 Oct 31, 2001 May 24, 2005 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6925007 Oct 25, 2002 Aug 2, 2005 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US7341918 Mar 7, 2005 Mar 11, 2008 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US7342279 Mar 7, 2005 Mar 11, 2008 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US20010021126 May 10, 2001 Sep 13, 2001 Tower Semiconductor Ltd. EEPROM array using 2 bit non-volatile memory cells and method of implementing same
US20010055838 Aug 13, 2001 Dec 27, 2001 Matrix Semiconductor Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
US20020005545 Jul 11, 2001 Jan 17, 2002 Koninklijke Philips Electronics N.V. Semiconductor device
US20020064911 Aug 28, 2001 May 30, 2002 Boaz Eitan Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
1 "Basic Programming Mechanisms," Nonvolatile Semiconductor Memory Technology-A Comprhensive Guide to Understanding and Using NVSM Devices, IEEE Press series on microelectronic systems, 1998, pp. 9-25.
2 "Notification of Transmittal of the International Search Report of the Declaration", corresponding PCT application No. PCT/US02/35132, International Searching Authority, United States Patent Office, Mar. 21, 2003, 4 pages.
3 "Notification of Transmittal of the International Search Report of the Declaration", corresponding PCT application No. PCT/US02/35132, International Searching Authority, United States Patent Office, Oct. 31, 2002, 3 pages.
4 Aritome, Seiichi, et al., "A Novel Side-Wall Transfer-Transistor Cell (SWATT CELL) for Multi-Level NAND EEProms", 1995 IEEE International Solid-State Circuits Conference, IDEM 95, pp. 275-278.
5 Boaz Eitan et al., "Can NROM, a 2 Bit, Trapping Storage NMV Cell, Give a Real Challenge to Floating Gate Cells?", Extended Abstracts, 1999 Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 522-524.
6 Chan et al., "A true single-transistor oxide-nitride-oxide EEPROM device," IEEE Electron Device Letters, vol. EDL-8, No. 3, Mar. 1987, pp. 93-95.
7 Chen, Wei-Ming et al., "A Novel Flash Memory Device with SPlit Gate Source Side Injection and ONO Charge Storage Stack (SPIN)", 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64.
8 China State Intellectual Property Office, "First Office Action," corresponding in PRC (China) Patent Application No. 02826596.3, mailed on Dec. 29, 2006, 12 pages (including translation).
9 China State Intellectual Property Office, "Office Action," corresponding Chinese Patent Application No. 02826596.3, mailed on Jul. 4, 2008, 2 pages (translation).
10 China State Intellectual Property Office, "Office Action," corresponding Chinese Patent Application No. 02826596.3, mailed on Oct. 10, 2008, 5 pages (including translation.).
11 D. Frohman-Bentchkowsky, "FAMOS-A new semiconductor charge storage device," Solid-State Electron., 1974, vol. 17, pp. 517-529.
12 D. Frohman-Bentchkowsky, Applied Physics Letters, vol. 18, 1971, pp. 332-334.
13 D. J. DiMaria et al., "Electrically-alterable read-only-memory using Si-rich SiO2 injectors and a floating polycrystalline silicon storage layer," J. Appl. Phys., 52(7), Jul. 1981, pp. 4825-4842.
14 DiMaria, D.J., "Insulator Physics and Engineering: Electrically-Alterable Read-Only-Memory Applications", Oct. 1981, Journal De Physique, C4, No. 10, Tome 42, pp. C4-1115-21.
15 Eiichi Suzuki et al., "A Low-Voltage Alterable EEPROM With Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) Structures", IEEE Transactions on Electron Devices, vol. ED-30, No. 2, Feb. 1883, pp. 122-128.
16 Eitan et al., "Hot-Electron Injection into the Oxide in n-channel MOS Devices," IEEE Transactions on Electron Devices, vol. Ed-28, No. 3, Mar. 1981, pp. 328-340.
17 Eitan et al., "Multilevel flash cells and their trade-offs," IEDM Tech. Dig., 1996, pp. 169-172.
18 Eitan et al., "NROM: A novel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
19 EPO, "Examiner's First Report," mailed in related European Application No. 02 784 379.6 on Jan. 26, 2006, 2 pages.
20 EPO, "Office Action," corresponding European Patent Application No. 07002287.6, mailed on Jun. 23, 2008, 4 pages.
21 EPO, "Office Action," corresponding European Patent Application No. 07002289.2, mailed on Jun. 23, 2008, 3 pages.
22 EPO, "Supplementary European Search Report", mailed in related European Application No. EP 02 78 4379 on Jul. 15, 2005, 1 page.
23 European Search Report for Application No. 07002288.4 for SanDisk Corporation, mailed Jul. 27, 2007, 4 pages.
24 European Search Report for Application No. 07002289.2 for SanDisk Corporation, mailed Jul. 27, 2007, 7 pages.
25 European Search Report, Application No. EP 07002287.6 for SanDisk Corporation, mailed Jul. 27, 2007. 6 pages.
26 F.I. Hampton et al., "Space Charge Distribution Limitation on Scale Down of MNOS Memory Devices", 1979, IEDM Technical Digest, pp. 374-377.
27 Hayashi, Yutaka et al., "Twin MONOS Cell With Dual Control Gates", 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123.
28 Hsia, Yukun, "Memory Applications of the MNOS", Wescon Technical Papers, vol. 16, 1972, pp. 3303-3308.
29 I. Fujiwara et al., "0.13 um MONOS single transistor memory cell with separated source lines," IDEM Tech. Dig., 1998, pp. 995-998.
30 Jan Van Houdt et al., "Multiple Bit Nonvolatile Memory Device and Method for Fabricating the Same", U.S. Appl. No. 60/391,565, filed Jun. 24, 2002, priority claimed by EP1376676.
31 K. T. Chang et al., "A new SONOS memory using source-side injection for programming," IEEE Electron Device Lett., vol. 19, 1998, p. 253-255.
32 Kamiya, M., et al., "EPROM Cell With High Gate Injection Efficiency," International Electronic Devices Meeting of IEEE, San Francisco, California, (Dec. 13-15, 1982) pp. 741-744.
33 Korean Patent Office, "Notice of Preliminary Rejection," corresponding Korean Patent Application No. 204-7006651, mailed on Nov. 3, 2008, 6 pages (including translation.).
34 Krick, P.J., "Dual-Level Sense Scheme for Composite Insulator Memory Arrays", IBM technical Disclosure Bulletin, vol. 17, No. 6, Nov. 1974, pp. 1811-1813.
35 Lai, S.K. et al., "Comparison and Trends in Today's Dominant E2 Technologies", IEEE, IEDM 86, 1986, pp. 580-583.
36 Luc Haspeslagh, "Two Bit Non-Volatile Electrically Erasable and Programmable Memory Structure, a Process for Producing Said Memory Structure and Methods for Programming and Erasing Said Memory Structure", U.S. Appl. No. 60/296,618, filed Jun. 7, 2001, priority claimed by US6,580,120.
37 Nozaki, "A 1-Mb EEPROM with a MONOS memory cell for a semi-conductor disk application," IEEE Journal of Solid State Circuits, vol. 26, No. 4, Apr. 1991, p. 497-501.
38 Office Action dated Apr. 5, 2004, United States Patent and Trademark Office, U.S. Appl. No. 10/161,235, 19 pages.
39 Office Action, Taiwanese Application No. 91132182 for SanDisk Corporation, mailed May 30, 2007, 5 pages.
40 P. J. Krick, "Three-state MNOS FET memory array," IBM Technical Disclosure Bulletin, vol. 18, No. 12, May 1976, pp. 1492-1493.
41 Roizin, Yakov, et al., "Novel Techniques for Data Retention and Leff Measurements in Two Bit microFLASH(R) Memory Cells", AIP Conference Proceedings, vol. 550, Melville, New York, 2001, pp. 181-185.
42 S. Ogura et al., "Low Voltage, Low Current, High Speed Program Step Split Gate Cell With Ballistic Direct Injection for EEPROM/Flash", 1998, IEDM Technical Digest, 36.5, pp. 987-990.
43 Second Office Action, PRC Application No. 02826596.3 for SanDisk Corporation, mailed Sep. 11, 2007, 2 pages.
44 Takashi Hori et al., "A MOSFET with Si-implanted Gate-SiO2 Insulator for Nonvolatile Memory Applications," IEEE, 0-7803-0817-4/92, pp. 17.7.1-17.7.4.
45 Third Office Action for Chinese Application No. 02826596.3 mailed Feb. 22, 2008, 8 pages.
46 Y. Tarui et al., "Electrically Reprogrammable Nonvolatile Semiconductor Memory", IEEE Journal of Solid State Circuits, vol. SC-7, No. 5, Oct. 1972, pp. 369-375.
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U.S. Classification 257/324, 257/E29.309, 257/E27.103, 257/E21.679, 257/326
International Classification G11C11/56, H01L27/115, H01L29/788, G11C16/04, H01L21/8247, H01L21/8246, H01L29/792
Cooperative Classification H01L27/115, H01L27/11521, B82Y10/00, G11C11/5671, G11C16/0491, H01L27/11524, G11C16/0483, H01L27/11568, G11C2216/06, H01L29/7923, G11C16/0466, G11C16/0475, H01L29/4234, Y10S438/947
European Classification G11C16/04M, G11C16/04N, G11C11/56M, H01L29/423D2B3, H01L27/115F4, B82Y10/00, H01L27/115F4N, H01L29/792B, H01L27/115, H01L27/115G4
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