Source: http://www.google.com.tw/patents/US7567592
Timestamp: 2013-05-23 05:37:17
Document Index: 791997061

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 200401969', 'Application No. 200401973', 'Application No. 200401969', 'application No. 200410044503', 'Application No. 200410047784', 'Application No. 200410038432', 'Application No. 200410038546', 'Application No. 04255786', 'Application No. 04252205', 'Application No. 04251582', 'Application No. 04252056', 'Application No. 04252202', 'Application No. 04252057', 'Application No. 04252203', 'Application No. 04252054', 'Application No. 04255611', 'Application No. 04251581', 'Application No. 04252054', 'Application No. 04252056', 'Application No. 04252057', 'Application No. 04252202', 'Application No. 04252203', 'Application No. 04255609', 'Application No. 04252055', 'Application No. 04255610', 'Application No. 200410044503', 'Application No. 200410043419', 'Application No. 200410045686', 'Application No. 200410087460', 'Application No. 04252205', 'Application No. 200410038545', 'Application No. 200410071498', 'Application No. 2004100950502', 'Application No. 200410044503', 'Application No. 08153726', 'Application No. 08155263', 'Application No. 08153724', 'Application No. 08155262']

�M�Q US7567592 - Packet based video display interface enumeration method - Google �M�Q�j�M �Ϥ� �a�� Play YouTube �s�D Gmail ���ݵw�� ��h »�i���M�Q�j�M | �������� | �n�J�i���M�Q�j�M�M�QAn enumeration method providing the link rate and a pixel/audio clock rate is described....http://www.google.com.tw/patents/US7567592?utm_source=gb-gplus-share�M�Q US7567592 - Packet based video display interface enumeration method���}��US7567592 B2�X���������v�ӽЮѽs��11/742,387�o�G���2009�~7��28���ӽФ��2007�~4��30�� �u���v���2003�~5��1����L���}�M�Q��CN101299183AEP1988542A1US20070258453�o��HOsamu Kobayashi��M�Q�v�HGenesis Microchip Inc. ���M�Q������370/538345/208��ڱM�Q������H04N5/44H04J3/02H04N5/765G06F3/153G09G3/36G06F3/14H04N7/00G09G5/00H04L12/56G09G3/20 �X�@����G09G5/006G09G2370/047G09G2370/10G06F3/14G09G2370/042 �ڬw������G09G5/00T4G06F3/14�ѦҤ��m�M�Q�ޥ� (107)�D�M�Q�ޥ� (86)�~���s�����M�Q�ӼЧ� ���M�Q�ӼЧ��M�Q����T�� �ڬw�M�Q��Packet based video display interface enumeration methodUS 7567592 B2�K�n An enumeration method providing the link rate and a pixel/audio clock rate is described.
expressing the multimedia clock rate (MMC) as a subset of the master frequency (MF) using a set of MMC exponents that includes at least an exponent A having a value A, an exponent B having a value B, an exponent C having a value C, and an exponent D having a value D, wherein the value A�� the value MF1; the value B�� the value MF2, the value C�� the value MF3, and the value D�� the value MF4;
expressing the link rate (LR) as a subset of the master frequency (MF) using a set of LR exponents that includes at least an exponent A�� having a value A��, an exponent B�� having a value B��, an exponent C�� having a value C, and an exponent D�� having a value D��, wherein the value A���� the value MF1; the value B���� the value MF2, the value C���� the value MF3, and the value D���� the value MF4; and
2. A method as recited in claim 1, wherein the master frequency MF is further expressed in terms of a set of MF coefficients that includes at least a first coefficient a having a value �\, a second coefficient �] having a value �], a third coefficient �^ having a value �^, and a fourth coefficient �_ having a value �_, wherein the master frequency MF is expressed as �\MF1�ѣ]MF2�ѣ^MF3�ѣ_MF4 Hz, wherein the value �\, the value �], the value �^, and the value �_ depend on the master frequency MF.
3. A method as recited in claim 2, wherein the link rate LR is further expressed in terms of a set of LR coefficients that includes at least a first coefficient �\ having the value �\, a second coefficient �] having the value �\, a third coefficient �^ having the value �^, and a fourth coefficient �_ having the value �_, wherein the link rate LR is expressed as �\A���ѣ]B���ѣ^C���ѣ_D�� Hz.
4. A method as recited in claim 3, wherein the multimedia clock rate MMC is further expressed in terms of a set of MMC coefficients that includes at least a first coefficient a having the value �\, a second coefficient �] having the value �], a third coefficient �^ having the value �^, and a fourth coefficient �_ having the value �_, wherein the multimedia clock rate MMC is expressed as �\A�ѣ]B�ѣ^C�ѣ_D Hz.
5. A method as recited in claim 4, wherein the determined multimedia clock rate MMC=(LR)��(�\A-A��, �]B-B��, �^C-C��, and �_D-D��).
6. A method as recited in claim 5, wherein when the master Frequency MF is 23.76 GHz, then �\=2, �]=3, �^=5, and �_=11 and wherein MF1=10, MF2=3, MF3=7, and MF4=1.
7. A method as recited in claim 6, wherein the link rate LR is expressed as 2A����3B����5C����11D�� Hz, wherein A����10, B����3, C����7, D����1.
8. A method as recited in claim 7, wherein the multimedia clock rate MMC is expressed as 2A��3B��5C��11D Hz, wherein A��10, B��3, C��7, D��1.
9. A method as recited in claim 8, wherein the multimedia clock rate MMC is related to the link rate LR as MMC=(LR)��(2A-A��, 3B-B��, 5C-C�� and 11D-D��).
computer code for expressing the multimedia clock rate (MMC) as a subset of the master frequency (MF) using a set of MMC exponents that includes at least an exponent A having a value A, an exponent B having a value B, an exponent C having a value C, and an exponent D having a value D, wherein the value A�� the value MF1; the value B�� the value MF2, the value C�� the value MF3, and the value D�� the value MF4;
computer code for expressing the link rate (LR) as a subset of the master frequency (MF) using a set of LR exponents that includes at least an exponent A�� having a value A��, an exponent B�� having a value B��, an exponent C�� having a value C, and an exponent D�� having a value D��, wherein the value A���� the value MF1 ; the value B���� the value MF2, the value C���� the value MF3, and the value D���� the value MF4; and
computer code for expressing the master frequency MF in terms of a set of MF coefficients that includes at least a first coefficient �\ having a value �\, a second coefficient �] having a value �], a third coefficient �^ having a value �^, and a fourth coefficient �_ having a value �_, wherein the master frequency MF is expressed as �\MF1�ѣ]MF2�ѣ^MF3�ѣ_MF4 Hz.
computer code for expressing the link rate LR in terms of a set of LR coefficients that includes at least a first coefficient �\ having the value �\, a second coefficient �] having the value �], a third coefficient �^ having the value �^, and a fourth coefficient �_ having the value �_, wherein the link rate LR is expressed as �\A���ѣ]B���ѣ^C���ѣ_D�� Hz.
computer code for expressing the multimedia clock rate MMC in terms of a set of MMC coefficients that includes at least a first coefficient �\ having the value �\, a second coefficient �] having the value �], a third coefficient �^ having the value �^, and a fourth coefficient �_ having the value �_, wherein the multimedia clock rate MMC is expressed as �\A�ѣ]B�ѣ^C�ѣ_D Hz.
computer code for expressing the relationship between the multimedia clock rate MMC to the link rate LR as MMC=(LR)��(�\A-A��, �]B-B��, �^C-C��, and �_D-D��).
16. Computer readable medium as recited in claim 15, wherein when the master frequency MF is 23.76 GHz, then �\=2, �]=3, �^=5, and �_=11 and wherein MF1=10, MF2=3, MF3=7, and MF4=1.
computer code for expressing the link rate LR as 2A����3B����5C����11D�� Hz, wherein A����10, B����3, C����7, D����1.
computer code for expressing the multimedia clock rate MMC as 2A��3B��5C��11D Hz, wherein A��10, B��3, C��7, D��1.
computer code for expressing the relationship between the multimedia clock rate MMC to the link rate LR as MMC=(LR)��(2A-A��, 3B-B��, 5C-C�� and 11D-D��).
CROSS REFERENCE TO RELATED APPLICATIONS This application is a Continuation of U.S. patent application Ser. No. 10/726,794 filed Dec. 2, 2003 entitled ��PACKET BASED VIDEO DISPLAY INTERFACE AND METHODS OF USE THEREOF�� by Kobayashi that, in turn, takes priority under 35 U.S.C. 119(e) to (i) U.S. Provisional Patent Application No. 60/467,804 filed May 1, 2003 entitled ��DIGITAL/ANALOG VIDEO INTERCONNECT AND METHODS OF USE THEREOF�� by Kobayashi, (ii) U.S. Provisional Patent Application No. 60/504,060 filed Sep. 18, 2003 entitled ��DIGITAL/ANALOG VIDEO INTERCONNECT AND METHODS OF USE THEREOF�� by Kobayashi, (iii) U.S. Provisional Patent Application No. 60/474,085 filed May 28, 2003 entitled ��DIGITAL/ANALOG VIDEO INTERCONNECT AND METHODS OF USE THEREOF�� by Kobayashi, and (iv) U.S. Provisional Patent Application No. 60/474,084 filed May 28, 2003 entitled ��SIMPLE ENUMERATION METHOD FOR THE LINK CLOCK RATE AND THE PIXEL/AUDIO CLOCK RATE�� by Kobayashi, each of which is hereby incorporated by reference herein in their entirety. This application is also related to the following U.S. Patent Applications each of which are herein incorporated by reference, (i) U.S. patent application Ser. No. 10/726,802 filed on Dec. 2, 2003 entitled ��METHOD OF ADAPTIVELY CONNECTING A VIDEO SOURCE AND A VIDEO DISPLAY�� by Kobayashi; (ii) U.S. patent application Ser. No. 10/726,438 filed Dec. 2, 2003 that issued as U.S. Pat. No. 7,068,686 and continuing U.S. patent application Ser. No. 11/291,015 that issued as U.S. Pat. No. 7,177,329, both entitled ��METHOD AND APPARATUS FOR EFFICIENT TRANSMISSION OF MULTIMEDIA DATA PACKETS�� by Kobayashi; (iii) U.S. patent application Ser. No. 10/726,440 entitled ��METHOD OF OPTIMIZING MULTIMEDIA PACKET TRANSMISSION RATE�� by Kobayashi; (iv) U.S. patent application Ser. No. 10/727,131 filed Dec. 2, 2003 entitled ��USING AN AUXILARY CHANNEL FOR VIDEO MONITOR TRAINING�� that issued as U.S. Pat. No. 7,088,741 by Kobayashi; (v) U.S. patent application Ser. No. 10/726,350 filed Dec. 2, 2003 entitled ��TECHNIQUES FOR REDUCING MULTIMEDIA DATA PACKET OVERHEAD�� by Kobayashi; (vi) U.S. patent application Ser. No. 10/726,362 filed Dec. 2, 2003 entitled ��PACKET BASED CLOSED LOOP VIDEO DISPLAY INTERFACE WITH PERIODIC STATUS CHECKS�� by Kobayashi; (vii) U.S. patent application Ser. No. 10/726,895 filed Dec. 2, 2003 entitled ��MINIMIZING BUFFER REQUIREMENTS IN A DIGITAL VIDEO SYSTEM�� by Kobayashi; (viii) U.S. patent application Ser. No. 10/726,441 filed Dec. 2, 2003 entitled ��VIDEO INTERFACE ARRANGED TO PROVIDE PIXEL DATA INDEPENDENT OF A LINK CHARACTER CLOCK�� by Kobayashi; and (ix) U.S. patent application Ser. No. 10/726,934 filed Dec. 2, 2003 entitled ��ENUMERATION METHOD FOR THE LINK CLOCK RATE AND THE PIXEL/AUDIO CLOCK RATE�� by Kobayashi that issued as U.S. Pat. No. 6,992,987. This application is also related to the following co-pending applications: (x) U.S. patent application Ser. No. 10/909,103 filed Jul. 29, 2004 entitled ��USING PACKET TRANSFER FOR DRIVING LCD PANEL DRIVER ELECTRONICS�� by Kobayashi; (xi) U.S. patent application Ser. No. 10/909,027 filed Jul. 29, 2004 entitled ��BYPASSING PIXEL CLOCK GENERATION AND CRTC CIRCUITS IN A GRAPHICS CONTROLLER CHIP�� by Kobayashi, (xi) U.S. patent application Ser. No. 10/909,085 filed Jul. 29, 2004 entitled ��PACKET BASED STREAM TRANSPORT SCHEDULER AND METHODS OF USE THEREOF�� by Kobayashi, and (xii) U.S. patent application Ser. No. 10/762,680 filed Jan. 21, 2004 entitled ��PACKET BASED HIGH DEFINITION HIGH-BANDWIDTH DIGITAL CONTENT PROTECTION�� by Kobayashi, each of which is incorporated by reference.
SUMMARY OF THE INVENTION In a system having a linking unit coupling a multimedia source device arranged to provide multimedia source data to a multimedia sink device by way of a plurality of multimedia data packets transmitted at a link rate (LR) over the linking unit, a method providing a multimedia clock rate (MMC) corresponding to the multimedia source data is disclosed. The method includes at least the following operations: expressing a master frequency (MF) in terms of a set of MF coefficients that includes at least a first coefficient MF1 having a value MF1, a second coefficient MF2 having a value MF2, a third coefficient MF3 having a value MF3, and a fourth coefficient MF4 having a value MF4; expressing the multimedia clock rate (MMC) as a subset of the master frequency (MF) using a set of MMC coefficients that includes at least a coefficient A having a value A, a coefficient B having a value B, a coefficient C having a value C, and a coefficient D having a value D, wherein the value A��the value MF1; the value B��the value MF2, the value C��the value MF3, and the value D��the value MF4; expressing the link rate (LR) as a subset of the master frequency (MF) using a set of LR coefficients that includes at least a coefficient A�� having a value A��, a coefficient B�� having a value B��, a coefficient C�� having a value C, and a coefficient D�� having a value D��, wherein the value A����the value MF1; the value B����the value MF2, the value C����the value MF3, and the value D����the value MF4; and providing the multimedia clock rate MMC from the link rate LR using the set of MMC coefficients and the set of LR coefficients.
In another embodiment, computer program product executable by a processor for providing a multimedia clock rate (MMC) corresponding to the multimedia source data in a system having a linking unit coupling a multimedia source device arranged to provide multimedia source data to a multimedia sink device by way of a plurality of multimedia data packets transmitted at a link rate (LR) over the linking unit is disclosed. The computer program product includes at least computer code for expressing a master frequency (MF) in terms of a set of MF coefficients that includes at least a first coefficient MF1 having a value MF1, a second coefficient MF2 having a value MF2, a third coefficient MF3 having a value MF3, and a fourth coefficient MF4 having a value MF4; computer code for expressing the multimedia clock rate (MMC) as a subset of the master frequency (MF) using a set of MMC coefficients that includes at least a coefficient A having a value A, a coefficient B having a value B, a coefficient C having a value C, and a coefficient D having a value D, wherein the value A��the value MF1; the value B��the value MF2, the value C��the value MF3, and the value D��the value MF4; computer code for expressing the link rate (LR) as a subset of the master frequency (MF) using a set of LR coefficients that includes at least a coefficient A�� having a value A��, a coefficient B�� having a value B��, a coefficient C�� having a value C, and a coefficient D�� having a value D��, wherein the value A����the value MF1; the value B����the value MF2, the value C����the value MF3, and the value D����the value MF4; computer code for providing the multimedia clock rate MMC from the link rate LR using the set of MMC coefficients and the set of LR coefficients; and computer readable medium for storing the computer code.
23.76 GHz=2A��3B��5C��11D HzwhereA=10, B=3, C=7, D=1,(23.76 GHz=210��33��57��111 Hz).
This means that a pixel (or audio) clock rate can be expressed as a subset of the master frequency with these four parameters, A, B, C, and D (where A��10, B��3, C��7,D��1) as
Pixel (or audio) clock rate=2A��3B��5C��11D.
Even for a link whose link rate (which is the serial link bit rate/10 for a link that uses 10-bit character such as 8B/10B characters) may be different from the pixel clock rate, there is a benefit in defining the link rate with these four parameters, A��, B��, C��, and D��: The benefit is the simplicity in regenerating pixel/audio clocks from a link clock. For example, let's say the link rate is set as A��=6, B��=3, C��=7, and D��=0 (i.e., LR=26��33��57��11 ) and the corresponding link rate is 135 MHz. However, suppose the pixel clock rate is set as A=8, B=3, C=6, and D=0 (i.e., PC=2833��56��110) =and the corresponding pixel clock rate is 108 MHz , then the pixel clock can be generated from link clock by the following equation
Pixel clock rate=(link rate)��(2A-A��, 3B-B��, 5C-C��, and 11D-D��). For the above example,(Pixel clock rate/Link rate)=(28��33��56��110)/(26��33��57��110) orPixel clock rate=(Link rate)��(22)��(30)��(5−1)��(110)=Link rate��(0.8).Referring back to those systems requiring time base recovery, the time-base recovery unit 226 may be implemented as a digital clock synthesizer. For an uncompressed video stream, the time stamp is stored in the packet header which as described in more detail below, is a 20-bit value. For a given stream, four of 20 bits are stored in each header successively (TS3-0, TS7-4, TS11-8, TS15-12, TS19-16). Native stream frequency (Freq_native) is obtained from link character clock frequency (Freq_link_char) as:
The f �Xaud �X clk =M aud /N aud *f �Xls �X clk The f�Xvid �X clk =M vid /N vid *f �Xls �X clk where f�Xaud �X clk is audio clock frequency,
f�Xvid �X clk is video clock frequency, and
f�Xls �X clk is link symbol clock frequency.
Audio rate=(audio sample rate)��(# bits per sample)��(# channels) Eq (2)
FIG. 6 shows a high-level diagram of the multiplexed main link stream 600 as an example of the stream 510 shown in FIG. 5 when three streams are multiplexed over the main link 222. The three streams in this example are: UXGA graphics (Stream ID=1), 1280��720 p video (Stream ID=2), and audio (Stream ID=3). The small packet header size of main link packet 400 minimizes the packet overhead, which results in the very high link efficiency. The reason the packet header can be so small is that the packet attributes are communicated via the auxiliary channel 224 prior to the transmission of the packets over main link 222.
State Diagrams The invention will now be described in terms of state diagrams shown in FIGS. 18 and 19 described below. Accordingly, FIG. 18 shows the source state diagram described below. At an off state 1802, the system is off such that the source is disabled. If the source is enabled, then the system transitions to a standby state 1804 suitable for power saving and receiver detection. In order to detect whether or not the receiver is present (i.e., hot plug/play), the auxiliary channel is periodically pulsed (such as for 1 us every 10 ms) and a measure of a voltage drop across the termination resistors during the driving is measured. If it is determined that a receiver is present based upon the measured voltage drop, then the system transitions to a detected receiver state 1806 indicating that a receiver has been detected, i.e, a hot plug event has been detected. If, however, there is no receiver detected, then the receiver detection is continued until such time, if ever, a receiver is detected or a timeout has elapsed. It should be noted that in some cases the source device may choose to go to ��OFF�� state from which no further display detection is attempted.
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