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Timestamp: 2018-01-21 08:28:31
Document Index: 492158197

Matched Legal Cases: ['Application No. 200780035313', 'Application No. 200780035313', 'Application No. 96135925', 'Application No. 2009', 'Application No. 096135925', 'Application No. 1020097006156', 'Application No. 200780035313', 'Application No. 2009', 'Application No. 2012']

Voltage regulator with drive override - Intel Corporation
Voltage regulator with drive override
United States Patent 8930741
Dibene II, Joseph T. (Olympia, WA, US)
Aldridge, Tomm (Olympia, WA, US)
13/316645
323/282, 713/501, 713/600
G06F1/04; G06F1/12; G06F1/26; H02M3/158
713/500, 713/501, 713/600, 323/282
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8099619 Voltage regulator with drive override 2012-01-17 Dibene et al. 713/500
7441137 Voltage regulator with internal controls for adjusting output based on feed-forward load information 2008-10-21 Mimberg
7421604 Advanced voltage regulation using feed-forward load information 2008-09-02 Mimberg
7345461 Semiconductor circuit device and data processing system 2008-03-18 Horiguchi et al.
20080002312 Methods and arrangements for generating a control signal for a power converter 2008-01-03 Dibene
7245113 High light load efficiency synchronous buck regulator with pulse skipping control 2007-07-17 Chen et al.
7225349 Power supply voltage droop compensated clock modulation for microprocessors 2007-05-29 Tam et al.
20070013080 Voltage regulators and systems containing same 2007-01-18 Dibene
20070002593 Isolated DCX converter 2007-01-04 Dinh
20060006855 Charge pump DC/DC converter with constant-frequency operation 2006-01-12 Feng et al.
6978388 Method and apparatus for managing a power load change in a system 2005-12-20 Cornelius
20050184717 DC-DC regulator with switching frequency responsive to load 2005-08-25 Walters
6922111 Adaptive frequency clock signal 2005-07-26 Kurd et al.
6876239 Delay locked loop “ACTIVE command” reactor 2005-04-05 Bell
20040257048 SMART VRM TO EXTEND THE BATTERY LIFE 2004-12-23 Chagny
6828848 Integrated circuit device capable of optimizing operating performance according to consumed power 2004-12-07 Lee
20040221182 Pre-emptive power supply control system and method 2004-11-04 He et al.
6804793 Manipulating an integrated circuit clock in response to early detection of an operation known to trigger an internal disturbance 2004-10-12 Josephson et al.
20040125517 CPU surge reduction and protection 2004-07-01 Nguyen et al.
20040119521 Adaptive frequency clock signal 2004-06-24 Kurd et al.
6677736 Energy recovery system for droop compensation circuitry 2004-01-13 Barnes et al.
20030227335 Clock modulating circuit 2003-12-11 Ebihara
6643499 Apparatus and method for controlling a phase-locked loop circuit 2003-11-04 Audinot et al.
20030201758 Voltage regulator with pulse width modulation in dual frequencies 2003-10-30 Chen 323/222
6639391 Variable switching frequency voltage regulator to optimize power loss 2003-10-28 Huang et al.
20030160597 Variable switching frequency voltage regulator to optimize power loss 2003-08-28 Huang et al.
6586971 Adapting VLSI clocking to short term voltage transients 2003-07-01 Naffziger et al.
20030112038 ADAPTING VLSI CLOCKING TO SHORT TERM VOLTAGE TRANSIENTS 2003-06-19 Naffziger et al.
6580597 Voltage regulator module for micro processor and CPO using a super capacitor 2003-06-17 Kanouda et al.
6473280 Switching voltage regulator failure detection circuit and method 2002-10-29 Buxton et al. 361/18
20020144163 System and method for highly phased power regulation using adaptive compensation control 2002-10-03 Goodfellow et al.
6445230 Programmable digital phase lock loop 2002-09-03 Rupp et al.
20020087896 Processor performance state control 2002-07-04 Cline et al.
6388432 CPU core voltage switching circuit 2002-05-14 Uchida
6243784 Method and apparatus for providing precise circuit delays 2001-06-05 Anderson et al.
6184753 Clock delay circuitry producing clock delays less than the shortest delay element 2001-02-06 Ishimi et al.
6152613 Circuit implementations for asynchronous processors 2000-11-28 Martin et al.
5559553 Clock control circuit with independent timing adjustments for image sensing devices 1996-09-24 Bitek
5324996 Floating fault tolerant input buffer circuit 1994-06-28 Mote, Jr.
JP02055572 April, 1990
JP4222455 August, 1992
JP0662562 March, 1994
JP6311731 November, 1994
JP08195659 July, 1996
JP0970620 March, 1997
JP10271883 October, 1998
JP11146302 May, 1999
JP2000270540A 2000-09-29 VOLTAGE SUPPLY CIRCUIT
JP2001202155A 2001-07-27 LOW POWER CONSUMPTION PROCESSOR
JP2004259879A 2004-09-16 REGULATOR BUILT-IN SEMICONDUCTOR DEVICE
JP2004260933A 2004-09-16 POWER SUPPLY SYSTEM
JP2004328837A 2004-11-18 SWITCHING POWER SUPPLY CIRCUIT AND SWITCHING REGULATOR COMPRISING THE SAME
JP2005128902A 2005-05-19 SEMICONDUCTOR CIRCUIT DEVICE AND DATA PROCESSING SYSTEM
JP2006060918A 2006-03-02 ELECTRONIC DEVICE
JP2007523587A 2007-08-16
KR1019960012676 April, 1996
KR1019980015556 May, 1998
KR100208353B1 1999-07-15 POWER SUPPLY CIRCUIT AND CONTROL METHOD OF POWER SUPPLY IN A MICROCOMPUTER
WO2005079486A2 2005-09-01 DC-DC REGULATOR WITH SWITCHING FREQUENCY RESPONSIVE TO LOAD
WO2008042149A1 2008-04-10 VOLTAGE REGULATOR WITH DRIVE OVERRIDE
JPH04222455A 1992-08-12
JPH11146302A 1999-05-28
KR960012676A
JPH06311731A 1994-11-04
KR19980015556A
JPH08195659A 1996-07-30
JPH0970620A 1997-03-18
JPH0662562A 1994-03-04
JPH10271883A 1998-10-09
JPH0255572A 1990-02-23
Office Action received for Chinese Patent Application No. 200780035313.9, mailed on May 13, 2011, 7 pages of Chinese Office Action including 4 pages of English translation.
Office Action received for Japanese Patent Application No. P2009-525665, mailed on May 30, 2011, 4 pages of Japanese Office Aciton including 2 pages of English Translation.
Office Action received for Chinese Patent Application No. 200780035313.9, mailed on Aug. 31, 2010, 10 pages of Chinese Office Action including 6 pages of English translation.
Office Action received for Taiwan Patnet Application No. 96135925, mailed on Dec. 6, 2010, 7 pages Taiwan Office Action including 1 page of English translation.
Office Action received for Korean Patent Application No. 2009-7006156, mailed on Dec. 24, 2010, 3 pages of English translation.
International Preliminary Report on Patentability received for PCT Application No. PCT/US2007/020622, mailed on Apr. 9, 2009, 6 pages.
International Search Report I Written Opinion for PCT Patent Application No. PCT/US2007/020622, mailed on Mar. 17, 2008, 10 Pages.
Rodriguez, Jorge, et al. “Systems and Methods for Voltage Regulator Communication”, U.S. Appl. No. 11/906,008, filed Sep. 29, 2007.
Koertzen, Henry W. “Multi-Cell VOLTA˜E Regulator”, U.S. Appl. No. 11/957,455, filed Dec. 15, 2007.
Bodas, Devadatta, et al., “Methods and Apparatus to Manage Platform Power Consumption Using an Application Agent”, U.S. Appl. No. 11/618,657, filed Dec. 29, 2006.
Office Action received for German Patent Application 11 2007 002 129.2, mailed on Jan. 13, 2012, 5 pages, including 1 page of English translation.
Decision of Refusal mailed Dec. 5, 2011 for Japanese Patent Application No. P2009-525665.
Decision of Refusal issued for Japanese Patent Application No. P2012-086253, mailed Jul. 29, 2013.
Notice of Allowance received for Taiwanese Patent Application No. 096135925, mailed on Sep. 6, 2011, 2 pages of Notice and 1 Page of English Translation.
Notice of Allowance received for Korean Patent Application No. 1020097006156, mailed on May 1, 2012, 2 Pages of Notice and 1 Page of English Translation.
Notice of Allowance received for Chinese Patent Application No. 200780035313.9, mailed on Sep. 1, 2011, 2 Pages of Notice and 2 Pages of English Translation.
Notice of Allowance received for Japanese Patent Application No. 2009-525665, mailed on Jul. 12, 2013, 2 Pages of Notice and 2 Pages of English Translation.
First Office Action received for Japanese Patent Application No. 2012-086253, mailed on Mar. 4, 2013, 3 Pages of Office Action and 3 Pages of English Translation.
Green, Howard & Mughal, LLP
This application is a Continuation of, and claims priority to and incorporates by reference, the corresponding U.S. patent application Ser. No. 11/540,075, filed on Sep. 28, 2006, entitled “VOLTAGE REGULATOR WITH DRIVE OVERRIDE” and issued as U.S. Pat. No. 8,099,619 on Jan. 17. 2012.
1. An apparatus comprising: a switching voltage regulator to be switched with a drive signal derived from a voltage regulator clock signal, the voltage regulator to provide a voltage supply to a functional circuit having an associated functional clock signal having a higher frequency than that of the voltage regulator clock signal; and synchronization circuit to synchronize the functional clock signal with the voltage regulator clock signal, wherein the synchronization circuit provides a first drive signal derived from the voltage regulator clock signal and a second drive signal derived from the functional clock signal, the first and second drive signals being in edge synchronization with one another, and wherein the second drive signal has a higher frequency than the first drive signal.
2. The apparatus of claim 1, wherein the functional circuit is a microprocessor core.
3. The apparatus of claim 2, wherein the microprocessor core issues the control signal when a load of the microprocessor core receiving the power supply is about to increase.
4. The apparatus of claim 2, wherein the microprocessor core issues a control signal a the load receiving the power supply is to increase above a threshold.
5. The apparatus of claim 1, wherein the drive signal to be derived from the functional clock signal in response to a control signal from the functional circuit when the functional circuit is about to require an increased level of power.
6. The apparatus of claim 1, wherein the switching voltage regulator is a multi-phase switching type voltage regulator, and wherein the drive signal comprises multiple drive signals out of phase with respect to one another.
7. The apparatus of claim 1, wherein the switching voltage regulator and the functional circuit are part of a common integrated circuit package.
8. The apparatus of claim 1, wherein the functional circuit and at least part of the switching voltage regulator are on separate dies.
9. The apparatus of claim 1, wherein the drive signal is to be derived from the functional clock signal for a sufficiently small amount of time so as to maintain stability.
10. An apparatus comprising: a switching voltage regulator having at least one switch to generate an output voltage to be provided to a functional circuit, the at least one switch to be driven by a drive signal derived from a clock signal of the functional circuit to inhibit droop in the output voltage when the functional circuit is about to require increased level of power but has not yet increased the level of power, otherwise the at least one switch of the switching voltage regulator to be driven by a drive signal derived from a periodic clock signal of the switching voltage regulator which has a frequency lower than the frequency of the drive signal.
11. The apparatus of claim 10, wherein the functional circuit is a microprocessor core.
12. The apparatus of claim 11, wherein the microprocessor core issues a control signal to the switching voltage regulator to engage the drive signal derived from the clock signal of the functional circuit when a load of the microprocessor core receiving the output voltage will increase.
13. The apparatus of claim 12, wherein the microprocessor core issues the control signal when the load of the microprocessor core is to require the increased current.
14. The apparatus of claim 10, further comprising a synchronization circuit to synchronize the drive signal with a signal normally used to drive the at least one switch.
15. The apparatus of claim 14, wherein the synchronization circuit to provide the drive signal derived from the clock signal of the functional circuit, and to provide the drive signal derived from the periodic clock signal of the switching voltage regulator, the respective drive signals being in edge synchronization with respect to one another.
16. The apparatus of claim 10, wherein the switching voltage regulator and functional circuit are part of a common integrated circuit package.
17. The apparatus of claim 16, wherein the functional circuit and at least part of the switching voltage regulator are on separate dies.
18. The apparatus of claim 10, wherein the drive signal, derived from the clock signal of the function circuit or derived from the periodic clock signal from the switching voltage regulator, is to be active at any given time for a sufficiently small amount of time to maintain stability.
19. A system comprising: a voltage regulator domain having voltage regulators coupled to a common supply output to provide a regulated voltage, the voltage regulators to switch using a drive signal derived from a voltage regulator clock signal, wherein the voltage regulator clock signal is a periodic clock signal; a processor core coupled to the voltage regulator domain to receive the regulated voltage, wherein the voltage regulator domain to operate using the drive signal derived from a clock signal from the processor core, the clock signal from the processor core having a frequency higher than that of the voltage regulator clock signal to inhibit unreasonable droops in the regulated voltage when the processor core is about to require an increased level of power but has not yet increased the level of power; and a memory device coupled to the processor core to provide it with external system memory.
21. The system of claim 19, further comprising a controller to control the voltage regulator domain to be driven by the clock signal from the processor core instead of the voltage regulator clock signal when load of the processor core is to sufficiently increase.
The IVR die 202 may comprise one or more domain VRs, while the microprocessor die 204 may comprise one or more domain cores, as described above. With this package configuration, with the dies mounted next to one another, circuit elements for VR domains can be disposed more proximal to their associated domain core elements. This can allow for sufficient conductive paths (e.g., via solder bumps or other contacts) to conduct relatively large amounts of current to the domain cores. (It should be appreciated that any suitable package configuration using one or more dies to implement the domain cores and VRs may be implemented and are within the scope of the present invention. For example, the IVR die could be “atop” the microprocessor die instead of “below” it. Alternatively it could be next to it, partially against it, or they could be part of the same die.)
Voltage regulator 300 also comprises VR controller 302, core clock driver 304, synchronizer circuits 3061 to 306N, and 2:1 multiplexers 3081 to 308N, coupled together as indicated. The VR controller 302 receives a clock signal (VR CLK) and produces from it N drive signals (∠1 to ∠N) appropriately phase-shifted from one another to drive switches S1 to SN to generate the regulated output voltage VCC. The VR clock signal may be a conventional clock signal with a suitable frequency (e.g., in the range of from 10 MHz. to 250 MHz.) for the efficient generation of VCC. The drive signals will typically have the same frequency as that of VR CLK but this is not required, e.g., they may be derived from a divided or multiplied version of VR CLK. As is known in the art, VR controller 302 controls the duty cycles of the drive signals to increase or lower the amount of current provided to the load in order to regulate VCC.
The separate drive signals are each provided to an associated synchronizer circuit 306i, which also receives a core clock (Core CLK) signal from an associated core (e.g., the core being powered by the voltage regulator 300). The frequency of the Core CLK signal will typically be greater than the frequency (or frequencies) of the drive signals, e.g., from 4 to 20 times greater. Each synchronizer circuit 306i synchronizes the edges of its incoming drive and core clock signal and provides as outputs first and second in-phase drive signals (DC and DV) but with the frequency of DiC being greater than DiV. The synchronizer circuits 306 may be formed from any suitable combination of circuit elements including but not limited to phase locked loops, delay locked loops, logic gates and the like. The drive signals (DiC, DiV) from each synchronizer circuit are fed into a an associated 2:1 multiplexer 308i, whose output is then provided to an associated one of the switches Si. A control signal (CTRL), e.g., from the associated core is also provided to each multiplexer 308 serving as the control to select either the DV drive signal or faster DC drive signal. (Note that in some embodiments, the core clock signal may not necessarily be provided to its synchronizer at all times. For example, it could be gated and disabled under appropriate conditions to save power. In this case, the synchronizer should then have appropriate circuitry to pass the drive signal through to its associated multiplexer, or equivalent, even if the core clock is not being applied.)
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