Source: http://patents.com/us-7436056.html
Timestamp: 2018-05-28 03:40:04
Document Index: 786947552

Matched Legal Cases: ['art.\n4', 'art.\n6', 'art.\n15', 'art 4', 'art 4', 'art 4', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14']

US Patent # 7,436,056. Electronic component package - Patents.com
United States Patent 7,436,056
Cheung , et al. October 14, 2008
Inventors: Cheung; Tszshing (Kawasaki, JP), Ikeuchi; Tadashi (Kawasaki, JP), Yagisawa; Takatoshi (Kawasaki, JP)
Appl. No.: 11/456,870
Apr 17, 2006 [JP] 2006-113454
Current U.S. Class: 257/698 ; 257/704; 257/710; 257/E21.5; 257/E21.501; 257/E23.004; 257/E23.062; 257/E23.067; 257/E23.07; 257/E23.079; 257/E23.128; 257/E23.18; 257/E23.189; 257/E23.19; 257/E23.193
Current International Class: H01L 23/04 (20060101); H01L 23/12 (20060101)
Field of Search: 257/698,704,E23.067,E23.189,E23.193,710,E21.5,E21.501,E23.128,E23.18,E23.19
5168344 December 1992 Ehlert et al.
2006/0103004 May 2006 Sakai et al.
1. An electronic component package, comprising: a dielectric substrate having a first surface where an electronic component is sealed; wherein a first signal line connecting to the electronic component and a first ground conductor are formed on the first surface of the dielectric substrate; a second signal line connected to an outside connection electrode and a second ground conductor are formed on a second surface of the dielectric substrate; the first ground conductor and the second ground conductor are connected by a plurality of ground conductor via-holes; and a substrate-buried signal line connected to the first signal line and the second signal line is provided inside of the dielectric substrate so as to be put between the first ground conductor and the second ground conductor above and below and between the ground conductor via-holes on the right and left.
2. The electronic component package as claimed in claim 1, wherein the substrate-buried signal line is connected to the first signal line and the second signal line by a via-hole.
3. The electronic component package as claimed in claim 1, wherein the electronic component is sealed by providing a lid part on the dielectric substrate; and the first ground conductor functions as a contact between the dielectric substrate and the lid part.
4. The electronic component package as claimed in claim 1, wherein the first ground conductor is provided on the first surface of the dielectric substrate in a ring shape.
5. The electronic component package as claimed in claim 3, wherein an electromagnetic wave absorption body is provided on an inside surface or an outside surface of the lid part.
6. The electronic component package as claimed in claim 1, wherein the outside connection electrode is a metal lead.
7. The electronic component package as claimed in claim 6, wherein the metal lead has thickness equal to or greater than 0.05 mm and equal to or smaller than 0.3 mm.
8. The electronic component package as claimed in claim 1, wherein a ground conductor electrode extended from the second ground conductor is formed at both sides of the outside connection electrode connected to the second signal line.
9. The electronic component package as claimed in claim 1, wherein a metal plate is provided under the second signal line.
10. The electronic component package as claimed in claim 1, wherein a first surface of the electronic component is positioned substantially coplanar with the first surface of the dielectric substrate.
11. The electronic component package as claimed in claim 1, wherein the dielectric substrate is a multi-layer substrate; a layer signal line is formed on a second surface of each layer of the dielectric substrate; and the layer signal lines are connected to each other by a via-hole so that the substrate-buried signal line is formed.
12. The electronic component package as claimed in claim 1, wherein a layer ground conductor is formed in the vicinity of the layer signal line.
13. The electronic component package as claimed in claim 1, wherein a wall part made of a dielectric material is provided in the vicinity of an end part of the dielectric substrate.
14. The electronic component package as claimed in claim 13, wherein a ground structure connected to the first ground conductor is formed inside of the wall part.
15. The electronic component package, as claimed in claim 1, wherein substrate-buried ground conductors are provided at both sides of the substrate-buried signal line.
16. The electronic component package as claimed in claim 15, wherein the substrate-buried ground conductor has a part extending outside of a portion where the first ground conductor is provided.
17. The electronic component package, as claimed in claim 16, wherein the substrate-buried ground conductor is connected to the first ground conductor and the second ground conductor by a via-hole.
18. The electronic component package as claimed in claim 16, wherein the part of the substrate-buried ground conductor extending outside of the portion where the first ground conductor is provided is connected to only the second ground conductor by a via-hole.
19. The electronic component package as claimed in claim 1, wherein the dielectric substrate is made of ceramic.
A wall part 4a of the lid part 4 made of the metal or a dielectric body is mounted on the ground conductor 3 so that a cavity is formed inside of the lid part 4. The LSI 2 is sealed in such a cavity.
More specifically, in a case where the package substrate 1 is made of a dielectric body such as ceramic in the structure shown in FIG. 1, inventors of the present invention recognize through simulation that a -3 dB cut-off frequency is less than approximately 35 GHz.
A wall part 14a of the lid part 14, the lid part 14 having a cross section of a rectangular shape without one side as viewed in FIG. 2(b) (inverted "U" shape), is mounted on the first ground conductor 13 and the wall part 14a and the first ground conductor 13 are connected by soldering. As a result of this, a cavity where the LSI 12 is provided is formed inside of the lid part 14. In other words, the first ground conductor 13 functions to contact the lid part 14 so that the LSI 12 is sealed. The lid part 14 is made of for example, metal or dielectric material.
A metal plate 22 is provided under the second ground conductor 16 so as to be separated from the end part of the metal lead 20. In a case where the metal plate 22 is not provided, even if the signal lines 15, 19 and 21 are provided on and in the package substrate 11 by performing impedance matching so that input impedance and output impedance are, for example, approximately 50 .OMEGA. each, the impedance may be mismatched if the package substrate 11 is mounted on the printed wiring board (not shown in FIG. 2). However, it is possible to avoid such a situation by providing the metal plate 22. In addition, it is possible to secure a good solder connection at the time when the package substrate 11 is provided on the printed wiring board (not shown in FIG. 2), by the metal plate 22. Here, the metal plate 22 is made of a metal such as gold (Au) or copper (Cu).
Referring to FIG. 6, in this modified example, two metal leads 20-2a and 20-2b extending from the metal plate 22 as ground conductors are provided between the metal lead 20-1 connected to the signal line 31-1 of the printed wiring board 30 and the metal lead 20-3 connected to the signal line 31-3 of the printed wiring board 30. Such a structure is effective in a case of the package where the high frequency signal lines are provided in close formation with short pitches. By this structure, it is possible to obtain a good high frequency characteristic under high ground stability.
Thus, by providing the ground conductors on all four side of the third signal line 21-1,1 it is possible to perform impedance matching so that the input and output impedances each have a desirable value such as approximately 50 .OMEGA..
Here, the reflection frequency f0 is expressed by the following formula when Er represents the dielectric constant of the package substrate. f0=speed of light/(2.times.length of the signal line.times.Er)
In the meantime, referring back to FIG. 2, in the embodiment of the present invention, the thickness ("t" in FIG. 2) of the metal lead 20 extending to the outside of the package substrate 11 may be equal to or greater than approximately 0.05 mm and equal to or smaller than 0.3 mm if the package substrate 11 is made of ceramic. This is discussed with reference to FIG. 12.
In FIG. 12, the horizontal axis represents the thickness ("t" in FIG. 2) of the metal lead 20 and the vertical axis represents the 3 dB cut-off frequency (GHz).
Referring to FIG. 12, in a case where the thickness ("t" in FIG. 2) of the metal lead 20 is equal to or greater than approximately 0.05 mm and equal to or smaller than 0.3 mm, the 3 dB cut-off frequency is equal to or greater than 40 GHz. Hence, it is possible to apply this to the communication system wherein the signal transmission speed is equal to or greater than 40 Gbps.
Thus, by providing the ground conductors on all four side of the third signal line 72 and the fourth signal line 73, it is possible to perform impedance matching so that the input and output impedances have desirable value such as approximately 50 .OMEGA. each.
In the above-discussed first and second embodiments of the present invention, the lid part 14 provided on the upper surface of the package substrate 11 or 71 has the cross-section of a rectangular shape without one side (inverted "U" shape). However, a part where the lid part and the package substrate 11 come in contact with each other may have a configuration shown in FIG. 23 through FIG. 25, so that a lid part 14 having a plate shape may be mounted on a package substrate 11.
In the graph shown in FIG. 30, f2 represents, as shown in FIG 11, a 3 dB cut-off frequency where there is 3 dB of attenuation. In addition, f3 through f5, namely fn represents a frequency calculated by the following formula when Er represents a dielectric constant of the package substrate. fn=speed of light/(2.times.distance between one signal line and the other signal line.times.Er)
Thus, the number of the via-holes 26 at a part formed other than a part corresponding to where the third signal line 21-1 is provided on the first ground conductor 113 provided on the upper surface of the package substrate 111 is larger than that of the examples shown in FIG. 26 through FIG. 29. Here, the via-hole 26 connects the first ground conductor 13, the second ground conductor 16, and the third signal line ground conductors 100-1 and 100-2 provided at left and right sides of the third signal line 20-1. Accordingly, it is possible to securely perform impedance matching so that the input and output impedances of the third signal line 21-1 provided at the package substrate 111 have desirable value such as approximately 50 .OMEGA. each.
In the graph shown in FIG. 32, the horizontal axis represents a frequency (GHz) and the vertical axis represents a transmission characteristic S21 (dB). A characteristic curve represents the frequency characteristic. "f2" represents, as shown in FIG. 30, a 3 dB cut-off frequency where there is 3 dB of attenuation. In addition, f3 through f5, namely fn, represents a frequency calculated by the formula mentioned above.
Therefore, between the signal line of the printed wiring board on which the package substrate is mounted and the electronic component provided on the package substrate, it is possible to securely perform impedance matching so that the input and output impedances have desirable values such as approximately 50 .OMEGA. each. Therefore, it is possible to realize high speed communication having low transmission loss.
Previous Patent US 7,436,055 | Next Patent US 7,436,057