Source: http://www.google.com/patents/US5782665?dq=5,687,325
Timestamp: 2017-11-20 04:44:26
Document Index: 387996349

Matched Legal Cases: ['Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08', 'Application No. 08']

Patent US5782665 - Fabricating array with storage capacitor between cell electrode and dark matrix - Google Patents
An array is fabricated in which a cell's dark matrix overlaps its cell electrode so that the overlap areas and the dielectric material between them form a storage capacitor. Each cell's dark matrix can overlap the cell's electrode around its perimeter, and the overlap areas of the dark matrix and the...http://www.google.com/patents/US5782665?utm_source=gb-gplus-sharePatent US5782665 - Fabricating array with storage capacitor between cell electrode and dark matrix
Publication number US5782665 A
Application number US 08/581,088
Also published as EP0782035A1, EP0782035B1
Publication number 08581088, 581088, US 5782665 A, US 5782665A, US-A-5782665, US5782665 A, US5782665A
Inventors Richard L. Weisfield, Michael G. Hack, Joel Levine
Patent Citations (25), Non-Patent Citations (23), Referenced by (43), Classifications (15), Legal Events (9)
US 5782665 A
1. A method of forming an array of light active cells at a surface of a substrate; the method comprising:
producing a series of layers at the surface of the substrate; the series of layers including:
scan lines; and
producing a first patterned layer over the series of layers; the first patterned layer including conductive material; each light active cell including a cell electrode that is part of the first patterned layer;
depositing a layer of dielectric material over the first patterned layer; the layer of dielectric material covering the cell electrode of each light active cell; and
producing a second patterned layer over the layer of dielectric material; the second patterned layer including dark matrix material that is conductive; each light active cell including a dark matrix that is part of the second patterned layer; each cell's dark matrix and cell electrode having an overlap area in which they overlap; the overlap area of the cell electrode, the overlap area of the dark matrix, and a part of the layer of dielectric material between them forming a storage capacitor for the cell.
2. An improved method of forming an array of light active cells at a surface of a substrate; each cell including parts of a series of layers over the surface of the substrate; the series of layers including:
a first patterned layer; the first patterned layer including conductive material; the first patterned layer including scan lines;
a second patterned layer; the second patterned layer including conductive material; the second patterned layer including data lines;
a third patterned layer formed over said first and second patterned layers; the third patterned layer including conductive material; each cell including a cell electrode that is part of the third patterned layer;
a fourth patterned layer formed over said third patterned layer; the fourth patterned layer including dark matrix material that is conductive; each cell including a dark matrix that is part of the fourth patterned layer; and
a layer of dielectric material between the third and fourth patterned layers;
patterning the third patterned layer and the fourth patterned layer so that the cell electrode and the dark matrix of each cell overlap, the cell electrode and the dark matrix each having an overlap area where they overlap; the overlap area of the cell electrode, the overlap area of the dark matrix, and a part of the layer of dielectric material between them forming a storage capacitor for the cell; and
electrically connecting the dark matrix of each cell to fixed potential circuitry to hold the dark matrix at a fixed potential.
3. The improved method of claim 2 in which the improvement further comprises depositing the layer of dielectric material to a thickness between 1000-2500 angstroms.
14. An improved method of forming an array of light active cells at a surface of a substrate; each cell including parts of a series of layers over the surface of the substrate; the series of layers including:
a fourth patterned layer formed under said first and second patterned layers; the fourth patterned layer including dark matrix material that is conductive; each cell including a dark matrix that is part of the fourth patterned layer; and
15. The improved method of claim 14 in which the improvement further comprises depositing the layer of dielectric material to a thickness between 1000-2500 angstroms.
26. An improved method of forming an array of light active calls at a surface of a substrate; each cell including parts of a series of layers over the surface of the substrate; the series of layers including:
a third patterned layer; the third patterned layer including conductive material;
each cell including a cell electrode that is part of the third patterned layer;
a fourth patterned layer; the fourth patterned layer including dark matrix material that is conductive; the fourth patterned layer further including a patterned sublayer of light absorbent material; each cell including a dark matrix that is part of the fourth patterned layer; and
27. The improved method of claim 26 in which the improvement further comprises depositing the layer of dielectric material to a thickness between 1000-2500 angstroms.
US5056894 * Feb 13, 1990 Oct 15, 1991 U.S. Philips Corporation Switching unit for a display device and display device including such a switching unit
EP0554061A1 * Jan 27, 1993 Aug 4, 1993 Canon Kabushiki Kaisha Liquid crystal display
EP0556484A1 * Dec 23, 1992 Aug 25, 1993 Kabushiki Kaisha Toshiba Liquid crystal display device
EP0569601A1 * Nov 27, 1992 Nov 18, 1993 Seiko Epson Corporation Liquid crystal display and method of manufacturing same
EP0592063A2 * Mar 29, 1993 Apr 13, 1994 Kabushiki Kaisha Toshiba Active matrix liquid crystal display device
JPH04280228A * Title not available
1 Kim, S.S., Jang, I.S., Kim, D.G., and Kim, N.D., "A Fault-Tolerant Architecture for Amorphous Silicon TFT Active-Matrix LCDs," Semi Korea, Flat Panel Display Seminar, Sep. 1995, pp. 119-125.
2 * Kim, S.S., Jang, I.S., Kim, D.G., and Kim, N.D., A Fault Tolerant Architecture for Amorphous Silicon TFT Active Matrix LCDs, Semi Korea, Flat Panel Display Seminar, Sep. 1995, pp. 119 125.
3 Matsueda, Y. et al. "HDTV Poly-SI TFT-LCD Light Valve with 70% Aperture Ratio," Conference Proceedings from The 13th International Display Research Conference, Aug. 31-Sep. 3, 1993, Strasbourg, France, pp. 601-605.
4 * Matsueda, Y. et al. HDTV Poly SI TFT LCD Light Valve with 70% Aperture Ratio, Conference Proceedings from The 13th International Display Research Conference, Aug. 31 Sep. 3, 1993, Strasbourg, France, pp. 601 605.
5 Suzuki, K., "High-Aperture TFT Array Structures," SID 94 Digest, 1994, pp. 167-170.
6 * Suzuki, K., High Aperture TFT Array Structures, SID 94 Digest, 1994, pp. 167 170.
7 U.S. Patent Application No. 08/367,984 entitled "Circuitry With Gate Line Crossing Semiconductor Line at Two or More Channels", filed on Jan. 3, 1995, Now U.S. Pat. 5,608,557.
8 * U.S. Patent Application No. 08/367,984 entitled Circuitry With Gate Line Crossing Semiconductor Line at Two or More Channels , filed on Jan. 3, 1995, Now U.S. Pat. 5,608,557.
9 U.S. Patent Application No. 08/453,732 entitled "Active Matrix Liquid Crystal Device and Manufacturing Method", filed on May 30, 1995, Now U.S. Pat. 5,621,556.
10 * U.S. Patent Application No. 08/453,732 entitled Active Matrix Liquid Crystal Device and Manufacturing Method , filed on May 30, 1995, Now U.S. Pat. 5,621,556.
11 U.S. Patent Application No. 08/455,888 entitled "Integrated Dark Matrix For An Active Matrix Liquid Crystal Display And Manufacturing Method", filed on May. 31, 1995, Now U.S. Pat. 5,682,211.
12 * U.S. Patent Application No. 08/455,888 entitled Integrated Dark Matrix For An Active Matrix Liquid Crystal Display And Manufacturing Method , filed on May. 31, 1995, Now U.S. Pat. 5,682,211.
13 U.S. Patent Application No. 08/559,862 entitled "Multiple Gate Polysilicon Structures With Continuously Doped Interchannel Regions", filed on Nov. 20, 1995, Now U.S. Pat. 5,703,382.
14 * U.S. Patent Application No. 08/559,862 entitled Multiple Gate Polysilicon Structures With Continuously Doped Interchannel Regions , filed on Nov. 20, 1995, Now U.S. Pat. 5,703,382.
15 * U.S. Patent Application No. 08/572,357 entitled Array With Metal Scan Lines Controlling Semiconductor Gate Lines, filed on Dec. 14, 1995, Now U.S. Pat. 5,600,155.
16 U.S. Patent Application No. 08/577,634 entitled "Fabricating Fully Self-Aligned Amorphous Silicon Device", filed on Dec. 22, 1995, Now U.S. Pat. 5,773,804.
17 * U.S. Patent Application No. 08/577,634 entitled Fabricating Fully Self Aligned Amorphous Silicon Device , filed on Dec. 22, 1995, Now U.S. Pat. 5,773,804.
18 U.S. Patent Application No. 08/578,780 entitled "Array With Amorphous Silicon TFTS in Which Channel Leads Overlap Insulating Region No More Than Maximum Overlap (as amended)", filed on Dec. 22, 1995, Now U.S. Pat. 5,717,223.
19 * U.S. Patent Application No. 08/578,780 entitled Array With Amorphous Silicon TFTS in Which Channel Leads Overlap Insulating Region No More Than Maximum Overlap (as amended) , filed on Dec. 22, 1995, Now U.S. Pat. 5,717,223.
20 Ueda, T., Sugahara, J., Toeda, H., Akiyama, M., Ikeda, M., Suzuki, K., "A High-Aperture-Ratio TFT-LCD with a Shield-Electrode Structure," SID 93 Digest, May, 1993, pp. 739-742.
21 * Ueda, T., Sugahara, J., Toeda, H., Akiyama, M., Ikeda, M., Suzuki, K., A High Aperture Ratio TFT LCD with a Shield Electrode Structure, SID 93 Digest, May, 1993, pp. 739 742.
22 Yamanaka, H., Fukunaga, T., Koseki, T., Nagayama, K., and Ueki, T., "Integrated Black Matrix on TFT Arrays," SID 92 Digest, May 1992, pp. 789-792.
23 * Yamanaka, H., Fukunaga, T., Koseki, T., Nagayama, K., and Ueki, T., Integrated Black Matrix on TFT Arrays, SID 92 Digest, May 1992, pp. 789 792.
US7176514 * Apr 15, 2003 Feb 13, 2007 Infineon Technologies Ag Method and configuration for reinforcement of a dielectric layer at defects by self-aligning and self-limiting electrochemical conversion of a substrate material
US8120740 * Apr 24, 2008 Feb 21, 2012 Seiko Epson Corporation Active-matrix substrate and method for producing the same, electrooptical device and method for producing the same, and electronic apparatus
US8188518 * Aug 27, 2010 May 29, 2012 Century Display(ShenZhen) Co., Ltd. Thin film transistor structure of pixel with drain extensions overlapping gate electrode and gate electrode extention
US20030224584 * Apr 15, 2003 Dec 4, 2003 Thomas Hecht Method and configuration for reinforcement of a dielectric layer at defects by self-aligning and self-limiting electrochemical conversion of a substrate material
US20080197354 * Oct 30, 2007 Aug 21, 2008 Kyu-Sik Cho Thin film transistor, an organic light emitting device including the same, and a manufacturing method thereof
US20080266514 * Apr 24, 2008 Oct 30, 2008 Seiko Epson Corporation Active-matrix substrate and method for producing the same, electrooptical device and method for producing the same, and electronic apparatus
US20100320473 * Aug 27, 2010 Dec 23, 2010 Chih-Chung Liu Thin film transistor structure of pixel
CN101295680B Apr 24, 2008 Feb 29, 2012 精工爱普生株式会社 Active-matrix substrate and method for producing the same, electrooptical device and method for producing the same, and electronic apparatus
U.S. Classification 445/24, 445/35, 349/111
International Classification H01L29/786, G02B5/00, G02F1/1368, G02F1/1335, H01L21/336, G02F1/136, G02F1/1362
Cooperative Classification G02F1/1368, G02F1/136209, G02F1/136213
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WEISFIELD, RICHARD L.;HACK, MICHAEL G.;LEVINE, JOEL;REEL/FRAME:007950/0051;SIGNING DATES FROM 19960414 TO 19960424