Source: https://patents.google.com/patent/EP0523768B1/en
Timestamp: 2019-06-16 06:52:17
Document Index: 554460422

Matched Legal Cases: ['arts 3', 'art 55', 'art 56', 'arts 55', 'art 56', 'art 55', 'art 56', 'art 55', 'art 56', 'art 56', 'art 55', 'art 56', 'art 55', 'art 56', 'art 55']

EP0523768B1 - Thin-film transistor manufacture - Google Patents
Thin-film transistor manufacture Download PDF
EP0523768B1
EP0523768B1 EP92201808A EP92201808A EP0523768B1 EP 0523768 B1 EP0523768 B1 EP 0523768B1 EP 92201808 A EP92201808 A EP 92201808A EP 92201808 A EP92201808 A EP 92201808A EP 0523768 B1 EP0523768 B1 EP 0523768B1
EP92201808A
EP0523768A2 (en
EP0523768A3 (en
1991-06-28 Priority to GB919114018A priority Critical patent/GB9114018D0/en
1991-06-28 Priority to GB9114018 priority
1992-06-19 Application filed by Philips Electronics UK Ltd, Koninklijke Philips NV filed Critical Philips Electronics UK Ltd
1993-01-20 Publication of EP0523768A2 publication Critical patent/EP0523768A2/en
1993-06-16 Publication of EP0523768A3 publication Critical patent/EP0523768A3/en
1997-01-02 Publication of EP0523768B1 publication Critical patent/EP0523768B1/en
(b) forming the insulated gate at the upper face of the semiconductor film by steps which include providing the gate on an insulating layer at the face of the film remote from the substrate,
(d) coating the conductive layer with the negative photoresist, and effecting the photolithographic step by exposing the photoresist through the combination of the substrate, semiconductor film and conductive layer which together are transparent to the illumination, the gate being opaque to the illumination so as to mask the photoresist area on the gate from being exposed, and developing the photoresist to form a window in the photoresist at the area which was masked by the gate, and
(e) etching the conductive layer through the window in the photoresist, the etching being continued throughout the thickness of the conductive layer where it extends over the insulated gate until the conductive layer is removed from over the insulated gate and separate parts of the conductive layer for forming the source and drain of the transistor are left on at least the semiconductor film at the opposite sides of the insulated gate.
Thus, by providing the gate as a photomask at the upper face of the semiconductor film, the present invention permits the achievement of low gate-to-drain and gate-to-source capacitances while also obtaining benefits of providing the transistor channel in the semiconductor material remote from the substrate. The applicants find that a better quality channel can be formed adjacent to the upper face of the semiconductor film as compared with a transistor channel formed at the lower face of a semiconductor film deposited on an insulated gate on the substrate. The properties of the semiconductor material at the upper face are less affected by the substrate. The transistor may comprise an amorphous semiconductor film, but the invention is particularly advantageous for transistors with crystalline film material at least in the region of the transistor channel. Thus, the invention permits the manufacture of high-speed TFTs due both to the low gate-to-drain and gate-to-source capacitances and to the high mobility of the crystalline semiconductor material adjacent to the insulated gate at the upper face of the film.
There is at present considerable interest in developing high-speed polycrystalline TFTs for large-area flat-panel LCDs. These displays are addressed by a matrix of active devices (TFTs or diodes) with at least one device per pixel. The dominant and most widely used technology at present is based on amorphous silicon TFTs. However amorphous silicon TFTs are too slow to provide the driving circuitry so that at present the display is normally connected externally to peripherally-mounted integrated-circuits formed in monocrystalline silicon. The present invention permits the manufacture of sufficiently fast TFTs to implement the scanning and addressing circuitry functions for such large-area displays, and the display can be fabricated on the same substrate as these TFTs. For this purpose, the TFTs should have a sufficiently high mobility and low parasitic capacitance as to allow the construction of row and column shift registers operating at, for example, about 30kHz and 11MHz respectively, and for output driver TFTs to be able to charge the appropriate row or column capacitances. Such TFTs can be manufactured in accordance with the invention.
The semiconductor film may be deposited as crystalline material on the substrate in step (a). Thus, for example, by chemical vapour deposition at substrate temperatures of 600 to 620oC, columnar polycrystalline silicon can be deposited in a fine grain form with grain widths of up to about 0.1µm. TFTs made from this material with the insulated gate at the upper face remote from the substrate may have mobilities in the range of, for example, 5 to 10cm2.V-1.s-1. It is found that the crystalline grain structure of the upper deposited material is usually better than that deposited immediately adjacent to the substrate.
However, the material for the semiconductor film may be deposited in a fine-grain or even amorphous form in step (a), and this deposited material may then be annealed on the substrate before step (b) so as to crystallize the film at least adjacent to its upper face which is remote from the substrate. Thus, for example, substantially amorphous silicon can be deposited with a substrate temperature of about 540°C and using low-pressure chemical vapour deposition. Alternatively using plasma-enhanced chemical vapour deposition, amorphous silicon material may be deposited at a temperature as low as about 250°C to 300°C. The film may be annealed by heating in a furnace. Thus, for example, with a furnace temperature of about 600°C, such amorphous silicon material can be converted into large-grain (about 1µm in width) polycrystalline silicon as a result of random nucleation. Mobilities in the range of, for example 20 to 80 cm2.V-1.s-1 can be obtained.
Visible light from an argon laser or infrared radiation from a CO2 laser may be used for the annealing step. The paper entitled "Low Temperature Polysilicon TFTs by Non-Mass-Separated Ion Flux Doping Technique" by K Masumo et al (in Japanese Journal of Applied Physics, 22nd Conf on Solid State Devices and Materials, 1990, pages 975-978) describes the use of an argon laser for crystallization of a silicon film in the manufacture of TFTs having their insulated-gate at the upper face of the crystallised silicon film. In this known method, the source and drain of the TFTs are formed by ion implantation using the gate as an implantation mask, and so they are not formed in accordance with the present invention.
Although visible or infrared laser radiation may be used for an annealing step in a method in accordance with the present invention, it is preferable to employ ultra-violet radiation from, for example, an excimer laser. An advantage of ultra-violet radiation is its smaller absorption depth so that, for example, the thickness of material (e.g amorphous material) deposited for the semiconductor film may be larger than the absorption depth of the ultra-violet radiation in the amorphous material. This smaller absorption depth reduces heating of the substrate and of the interface between the substrate and the semiconductor film. The applicants have found that such heating of the substrate can reduce the yield of the manufacturing process by weakening the adhesion of the semiconductor film to the substrate. Hence, it is advantageous in accordance with the invention to provide the insulated gate at the opposite (i.e. upper) face of the film and to do so after annealing the film to form a good quality crystal grain structure adjacent to its upper face. An insulating layer of the insulated-gate structure may be present on the semiconductor film during the annealing. However, it seems at present that a better crystal grain structure may be obtained for the TFT channel when the upper face of the film is not covered with such a layer during the annealing.
Thus, for example, in one form in accordance with the invention a second photolithographic step using negative photoresist is used to define the area at which the upper part of the conductive layer is etched away from the lower part, the negative photoresist in the second photolithographic step being exposed by illumination through the substrate at such an angle that the insulated gate shadow-masks the photoresist over an area of the conductive layer at the drain side of the insulated gate. In another form in accordance with the invention a photolithographic step using a positive photoresist is used to define the area at which the upper part of the conductive layer is etched away from the lower part, the positive photoresist beingexposed by illuminating its upper face which is remote from the substrate at such an angle that the insulated gate shadow-masks the photoresist over the area of the conductive layer at the drain side of the insulated gate; and in this case the shadow-masked area of the photoresist which remains after developing the exposed photoresist may be used in a lift-off process to form a complementary mask on the surrounding area for protecting the surrounding area while etching away said upper part of the conductive layer at the drain side of the insulated gate.
Figure 1 is a cross-section of a semiconductor film deposited on a substrate at an early stage in the manufacture of a TFT by a method in accordance with the invention;
Figures 2 to 5 are similar cross-sections to that of Figure 1 but at later stages in the manufacture of the TFT whose final structure is illustrated in Figure 5;
Figure 6 is a cross-section similar to that of Figure 5 but illustrating a modified TFT structure having a low-doped drain part extending laterally between the insulated gate and the main drain electrode part;
Figure 7 is a similar cross-section of the TFT structure of Figure 6 but at a stage in one method for its manufacture in accordance with the invention and involving a second photolithographic step using the insulated gate to shadow-mask a negative photoresist, and
Figures 8 and 9 are similar cross-sections of the TFT structure of Figure 6 but at two successive stages in another method for its manufacture in accordance with the invention and involving a photolithographic step using the insulated gate to shadow-mask a positive photoresist.
Figures 1 to 5 illustrate one example of a method in accordance with the invention for manufacturing an insulated-gate TFT. The TFT of Figure 5 is present on a transparent substrate 1 and comprises a semiconductor film 2, for example of polycrystalline silicon. The film 2 provides a transistor channel adjacent to an insulated gate structure 3 and 4. The channel and the insulated gate are present between source and drain 51 and 52 of the TFT. These source and drain 51 and 52 are formed from a conductive layer 5 (Figure 3) which in the form illustrated is, for example, highly doped n-type silicon (n+). These n+ source and drain 51 and 52 are contacted in the TFT structure of Figure 5 by metal electrodes 41 and 42 respectively of, for example, aluminium or chromium.
In brief summary the manufacturing method illustrated in Figures 1 to 5 comprises the steps of:
(a) depositing material for the semiconductor film 2, on the substrate 1, see Figure 1,
(d) coating the conductive layer 5 with a negative photoresist 6, and then exposing the photoresist by illumination 25 through the substrate 1 while using the gate 4 as a photomask, see Figure 3, and
A specific example of the method of Figures 1 to 5 will now be described. In this specific example, the substrate 1 may be an alkali-free alumino-borosilicate glass, and a LCD may, for example, be constructed on another area of the substrate 1 not shown in the cross-section of Figures 1 to 5. Using either a low-pressure chemical vapour deposition process at about 540oC or a plasma-enhanced chemical vapour deposition process at about 250oC, hydrogenated amorphous silicon may be deposited on the glass substrate 1 from silane to form the film 2 with a thickness of, less than 0.1µm, for example about 40nm or 60nm. A photolithographic step is then carried out to mask areas of the film 2 where the TFT and other devices are to be formed, and the unmasked areas are etched away to leave amorphous silicon islands 2 on the substrate 1.
Figure 1 shows one such island 2 where a single polycrystalline silicon TFT is to be formed. It should be understood that the substrate 1 of Figure 1 carries many other such silicon islands 2, some of which are to be processed in the same manner as that shown in Figures 1 to 5 and some of which may be processed differently to form a different type of TFT (e.g. an amorphous silicon TFT) or other device.
As illustrated by the arrows 20 in Figure 1 those amorphous silicon islands 2 which are to be annealed to polycrystalline silicon are irradiated at their upper face remote from the substrate 1 with a laser beam 20. Preferably ultra-violet radiation 20 is used with an absorption depth in the silicon of less than the thickness of the silicon film 2. Thus, for example, an ultra-violet wavelength of 248nm from an excimer laser may be used and has an absorption depth of about 6nm in the amorphous silicon film 2. The film 2 may be exposed to multiple pulses (for example, several tens of pulses) from this laser with a pulse energy of between 100mJ.cm-2 and 300mJ.cm-2 per pulse. In this case it is found for a 40nm or 60nm thick film 2, crystallization into large grains of about 80nm width occurs adjacent to its upper surface whereas the underlying material adjacent to the substrate 1 comprises only fine grains of up to about 25nm in width and may even remain substantially amorphous at the interface with the substrate 1. The grain size at the upper surface may increase with increase in the number of pulses to which it is exposed at a given scan rate. More pulses are needed to effect the same anneal if a faster scan rate is used.
The large-grain layer adjacent the upper face of the film 2 provides a high mobility (e.g. in excess of 30cm2.V-1.s-1 for a 200mJ.cm-2 energy pulse) for the TFT channel. This is adequate for both row and column driver circuits of a LCD. Thus, for example, for row and column shift registers operating at about 30kHz and 11MHz respectively, the field-effect mobility for row driver TFTs should be in excess of about 1 cm2.V-1.s-1, whereas that for column driver TFTs should be in excess of about 25 cm2.V-1.s-1. The conductivity of the large-grain layer is effectively intrinsic with its Fermi level near the middle of the energy bandgap. However the film 2 may be lightly doped with a suitable donor such as phosphorus or a suitable acceptor such as boron so as to adjust the gate threshold voltage of the TFT and/or to give the crystallized film 2 a light n or p type conductivity.
The large grains in the upper portion are believed to result from surface melting of the silicon by the strongly absorbed ultra-violet, whereas the underlying fine grains appear to result from solid-phase recrystallization. The depth of the large-grain surface layer is found to be a strong function of incident laser energy, varying from about 10nm for a 150mJ.cm-2 pulse to about 50nm for a 250mJ.cm-2 pulse. Annealing the film 2 in this manner with an ultra-violet laser is advantageous in preserving good adhesion of the film 2 to the substrate 1. The applicants have also annealed such films 2 using visible radiation (514.5nm) from an argon laser; in this case the film 2 is annealed to large crystal grains through most of its thickness, but there was a tendency for the film 2 to peel away from the substrate 1 due to the strong heating of the substrate.
After the film 2 is annealed in this manner, an insulating layer (for example of silicon dioxide) is deposited in known manner, followed by a conductive gate layer (for example of aluminium or chromium). A photolithographic and etching process is then carried out in known manner to remove these layers except in the areas where required to form the insulated gate structure 3 and 4 for the TFTs. The resulting structure is illustrated in Figure 2. The remaining layer parts 3 and 4 extend as stripes (perpendicular to the plane of the drawing) across the film islands 2 which protrude laterally from beneath opposite ends of the insulated gate structure 3 and 4 as shown in Figure 2.
The conductive layer 5 of for example phosphorus-doped silicon is then deposited in known manner by chemical vapor deposition and is coated with the negative photoresist 6. The n type layer 5 may be, for example, about 20nm thick, and the photoresist 6 may be about 1µm thick. The photolithographic and etching process for forming the source and drain 51 and 52 from the layer 5 is now carried out.
As illustrated in Figure 3, the negative photoresist 6 is exposed by illumination with radiation 25 through the combination of the substrate 1, film 2, and layer 5 which together are transparent to the wavelength (for example in the near ultraviolet or visible region of the spectrum) chosen for the illumination 25. Although the insulating layer 3 may also be transparent, the metal gate 4 is opaque at this wavelength and so acts as a photomask. The photoresist is then developed in known manner, and so a window 14 is opened in the unexposed photoresist above the insulated gate 3 and 4 and uncovers the conductive layer 5 in this area. The window 14 is illustrated in broken outline in Figure 3. The layer 5 is then etched away at the window 14 so as to expose the insulated-gate structure 3 and 4 and form the separate source and drain 51 and 52 from the remaining parts of the layer 5 covered by the remaining photoresist 6. The gate 4 is not etched to any significant extent in this etching treatment. Figure 4 illustrates the resulting structure after removal of the remaining photoresist 6.
The remaining source and drain parts interface with the large-grain high-mobility material at the upper face of the film 2 extending laterally beyond the insulated-gate structure 3 and 4. This arrangement provides a good and reliable electrical connection between the TFT channel and the source and drain 51 and 52. The sheet resistance of the source and drain layers 51 and 52 may be reduced if desired by a laser anneal. Because the source and drain 51 and 52 are formed using the gate 4 as a photomask, the gate-to-source and gate-to-drain capacitances are very low, for example less than about 2 x 10-16F per µm of channel width, so permitting fast operation of this high-mobility polycrystalline silicon TFT in, for example, column driver circuits of LCDs.
With high drain bias (for example with drain voltages of above 15 volts) a localised high electric field region can be formed in the channel edge adjacent the drain 52. Charge carriers in this high field can attain kinetic energies in excess of a few eV and so may be injected over the interfacial potential barrier between the film 2 and the gate oxide 3. This carrier injection can cause degradation of the TFT characteristics, such as a reduction in transconductance or a shift in threshold voltage. As already described with reference to Figures 3 and 4, the conductive layer 5 at the window 14 can be etched back to such an extent that a small gap 53 is present between the facing edges of the drain 52 and the insulated-gate structure 3 and 4. This gap can assist in reducing the high field in this area and so reducing hot-carrier injection.
However, an even more advantageous structure can be obtained using a modified process which is also in accordance with the present invention. In this modified process the doping of the conductive layer 5 changes through the thickness of the layer 5 so as to be less in a lower part 55 than it is in a highly conductive upper part 56. The doping level may be varied progressively during the deposition of the layer 5, or the layer 5 may be deposited as two superimposed layers 55 and 56 of different doping levels. After removing the layers or layer parts 55 and 56 from over the gate 4, the upper part 56 is in this case etched away from the lower part 55 at an area A at least at the drain side of the gate 4 so as to space the higher-conductance upper part 56 of the drain 52 laterally from the channel by a lower-doped part 55 of the layer 5. The resulting structure is illustrated in Figure 6.
The area A over which the upper part 56 is etched away may be defined using a separate photomask and requiring an extra alignment step. However, it is also possible to use the insulated-gate structure 3,4 as the photomask, by illuminating the photoresist at such an angle that the insulated-gate structure 3,4 shadow-masks an area of the photoresist at the drain side of the gate 4. This is illustrated by the arrows 26 in Figure 6. The angled illumination 26 may be used instead of the perpendicular illumination 25 of Figure 3 so that the window 14 formed in the negative photoresist 6 is shifted laterally towards the drain. The etching away of the upper part 56 from the lower part 55 may then be effected through this window 14 by continuation of the etching step(s) to remove the layer(s) 55 and 56 from over the gate 4. However this variation in the photolithographic and etching process steps of Figures 3 and 4 can be difficult to reproduce reliably in a manufacturing process, and so preferably the angled illumination 26 is carried out in a separate photolithographic step after the steps of Figures 3 and 4.
Figure 7 illustrates such a separate step in which a new negative photomask 16 is coated on the Figure 4 structure, the conductive layer 5 of which has the different doping levels of 55 and 56. The exposed photoresist 16 is then slightly overdeveloped so as to form a widened window 15 at the unexposed area which was shadow-masked by the gate 4. Figure 7 illustrates the resulting structure before carrying out the etching step to remove the exposed higher-doped upper part 56 from the lower part 55 at the drain side of the insulated-gate structure 3 and 4. If desired a selective etchant may be used which attacks the higher doped material more rapidly than the lower doped material.
Instead of using a second photolithographic step with a negative photoresist 16, a step with a positive photoresist 17 may be used as illustrated in Figure 8. In this case, the positive photoresist is exposed by illuminating its upper face at a suitable angle (arrows 27) for the insulated gate 4 to shadow-mask the resist 17 over an area at the drain side. The original coating of positive resist 17 is shown in broken outline in Figure 8, which also shows in solid outline the shadow-masked area of the resist 17 which remains after developing the exposed photoresist. This remaining resist area 17 is then used in a lift-off process to form a complementary mask 28 on the surrounding area. The mask 28 is formed by depositing a layer of gold for example and then dissolving the remaining resist area 17 to float off the overlying part of gold layer. The mask 28 is then used to protect the underlying surrounding area while etching away the upper part 56 from the lower part 55 at the drain side of the insulated gate 3 and 4. Figure 9 shows the resulting structure before removal of the mask 28.
From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalents and other features which are already known in the design, manufacture and use of TFTs and other semiconductor devices and component parts thereof, and which may be used instead of or in addition to features already described herein. It has been stated above that the drawings illustrate examples of embodiments of the invention and, in order to avoid any misunderstanding, it is hereby further stated that, in the following claims, where technical features mentioned in any claim are followed by reference signs relating to features in the drawings and placed between parentheses, these reference signs have been included in accordance with Rule 29(7) EPC for the sole purpose of facilitating comprehension of the claim, by reference to an example.
A method of manufacturing an insulated-gate thin-film transistor comprising a semiconductor film (2) which provides a transistor channel adjacent to an insulated gate (4) between source and drain of the transistor, the source and drain (51,52) being formed from a conductive layer (5) which is removed from over the gate using a photolithographic step, in which step the gate(4) serves as a photomask while exposing a negative photoresist (6) on the conductive layer (5) by illumination (25) through a transparent substrate (1), which method is characterised by the steps of:
(a) depositing material for the semiconductor film (2), on the substrate (1),
(b) forming the insulated gate at the upper face of the semiconductor film (2) by steps which include providing the gate (4) on an insulating layer (3) at the face of the film (2) remote from the substrate (1),
(c) depositing the conductive layer (5) on the insulated gate (4) and on the semiconductor film (2) beside the insulated gate,
(d) coating the conductive layer (5) with the negative photoresist (6), and effecting the photolithographic step by exposing the photoresist through the combination of the substrate (1), semiconductor film (2) and conductive layer (5) which together are transparent to the illumination (25), the gate (4) being opaque to the illumination so as to mask the photoresist area on the gate (4) from being exposed, and developing the photoresist (6) to form a window (14) in the photoresist at the area which was masked by the gate (4), and
(e) etching the conductive layer (5) through the window (14) in the photoresist (6), the etching being continued throughout the thickness of the conductive layer (5) where it extends over the insulated gate (4) until the conductive layer (5) is removed from over the insulated gate (4) and separate parts (51,52) of the conductive layer (5) for forming the source and drain of the transistor are left on at least the semiconductor film (2) at the opposite sides of the insulated gate (4).
A method as claimed in claim 1, further characterised in that the material for the semiconductor film (2) is deposited in a fine-grain or amorphous form in step (a), and in that, before providing the gate (4) in step (b), this deposited material is annealed on the substrate so as to crystallize the semiconductor film (2) at least adjacent to its upper face which is remote from the substrate (1).
A method as claimed in claim 2, further characterised in that the deposited material for the semiconductor film (2) is annealed in a furnace by heating on the substrate (1).
A method as claimed in claim 2, further characterised in that the deposited material for the semiconductor film (2) is annealed by irradiating its upper face with an energy beam (20), for example, a laser beam.
A method as claimed in claim 4, further characterised in that the annealing is carried out with ultra-violet radiation (20) from a laser.
A method as claimed in claim 5, further characterised in that the thickness of the material deposited on the substrate (1) for the semiconductor film (2) is larger than the absorption depth of the ultra-violet radiation (20) of the laser in this material.
A method as claimed in any one of claims 2 to 5, further characterised in that the deposited material for the semiconductor film (2) is annealed before providing the insulating layer (3) in step (b) at the crystallized upper face of the film (2).
A method as claimed in any one of the preceding claims, further characterised in that the conductive layer (5) is of doped semiconductor material having a lower doping level in a lower part (55) of the layer below an upper part (56) of higher conductance, and in that, after removing the conductive layer (5) from over the gate (4), the upper part (56) is etched away from the lower part (55) at an area (A) at least at the drain side of the gate (4) so as to space the higher conductance upper part (56) of the drain (52) laterally from the channel by a lower-doped part (55) of the conductive layer (5).
A method as claimed in claim 8, further characterised in that a second photolithographic step using negative photoresist (16) is used to define the area (A) at which the upper part (56) of the conductive layer (5) is etched away from the lower part (55), the negative photoresist (16) in the second photolithographic step being exposed by illumination (26) through the substrate (1) at such an angle that the insulated gate (4) shadow-masks the photoresist (16) over an area of the conductive layer (5) at the drain side of the insulated gate (4).
A method as claimed in claim 8, further characterised in that a photolithographic step using a positive photoresist (17) is used to define the area (A) at which the upper part of the conductive layer is etched away from the lower part, the positive photoresist (17) being exposed by illuminating (27) its upper face which is remote from the substrate (1) at such an angle that the insulated gate (4) shadow-masks the photoresist (17) over the area of the conductive layer (5) at the drain side of the insulated gate (4), and in that the shadow-masked area of the photoresist (17) remains after developing the exposed photoresist and is used in a lift-off process to form a complementary mask (28) on the surrounding area for protecting the surrounding area while etching away said upper part (56) of the conductive layer (5) at the drain side of the insulated gate (4).
EP92201808A 1991-06-28 1992-06-19 Thin-film transistor manufacture Expired - Lifetime EP0523768B1 (en)
GB919114018A GB9114018D0 (en) 1991-06-28 1991-06-28 Thin-film transistor manufacture
EP0523768A2 EP0523768A2 (en) 1993-01-20
EP0523768A3 EP0523768A3 (en) 1993-06-16
EP0523768B1 true EP0523768B1 (en) 1997-01-02
EP92201808A Expired - Lifetime EP0523768B1 (en) 1991-06-28 1992-06-19 Thin-film transistor manufacture
TW (1) TW232088B (en)
SE523918C2 (en) * 1999-01-25 2004-06-01 Appliedsensor Sweden Ab Process for the production of integrated sensor arrays on a common substrate and a mask for use in the process
1991-06-28 GB GB919114018A patent/GB9114018D0/en active Pending
1992-05-12 TW TW081103693A patent/TW232088B/zh active
1992-06-19 DE DE69216311A patent/DE69216311D1/en not_active Expired - Fee Related
1992-06-19 EP EP92201808A patent/EP0523768B1/en not_active Expired - Lifetime
1992-06-19 DE DE69216311T patent/DE69216311T2/en not_active Expired - Lifetime
1992-06-23 US US07/902,642 patent/US5264383A/en not_active Expired - Fee Related
1992-06-25 CA CA002072264A patent/CA2072264A1/en not_active Abandoned
1992-06-25 JP JP4167813A patent/JPH05190568A/en active Pending
1992-06-25 KR KR1019920011070A patent/KR100260063B1/en not_active IP Right Cessation
EP0523768A2 (en) 1993-01-20
CA2072264A1 (en) 1992-12-29
DE69216311T2 (en) 1997-06-12
KR100260063B1 (en) 2000-07-01
JPH05190568A (en) 1993-07-30
DE69216311D1 (en) 1997-02-13
GB9114018D0 (en) 1991-08-14
US5264383A (en) 1993-11-23
TW232088B (en) 1994-10-11
EP0523768A3 (en) 1993-06-16
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2005-06-19 PG25 Lapsed in a contracting state [announced from national office to epo]