Source: http://www.google.com/patents/US7050884?dq=5,815,488
Timestamp: 2015-03-29 12:58:13
Document Index: 600974131

Matched Legal Cases: ['art 63', 'art 64', 'art 67', 'arts 68', 'arts 68', 'arts 62', 'art 66', 'arts 68', 'art 63', 'art 63', 'art 63', 'art 67', 'art 67']

Patent US7050884 - Image transmission device and method, transmitting device and method ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn image transmission device and method, a transmitting device and method, a receiving device and method, and robot apparatus are capable of effectively transmitting the image data of multiple channels by using the existing systems which are formed on the premise of transmitting and receiving of the...http://www.google.com/patents/US7050884?utm_source=gb-gplus-sharePatent US7050884 - Image transmission device and method, transmitting device and method, receiving device and method, and robot apparatusAdvanced Patent SearchPublication numberUS7050884 B2Publication typeGrantApplication numberUS 10/390,143Publication dateMay 23, 2006Filing dateMar 17, 2003Priority dateMar 18, 2002Fee statusPaidAlso published asUS7110860, US7269477, US7269478, US7346430, US20040008738, US20050216123, US20050259677, US20050267634, US20050267636Publication number10390143, 390143, US 7050884 B2, US 7050884B2, US-B2-7050884, US7050884 B2, US7050884B2InventorsMasaki Fukuchi, Takayuki Yoshigahara, Kohtaro Sabe, Takeshi OhashiOriginal AssigneeSony CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (12), Non-Patent Citations (3), Classifications (34), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetImage transmission device and method, transmitting device and method, receiving device and method, and robot apparatus
Each of the leg units 5A and 5B is attached to the waste base 11 of the lower part of the main body via a thigh joint system 26 respectively, where each of the leg units 5A and 5B can be independently rotated around a yawing axis 27, a roll axis 28, and a pitch axis 29 orthogonal each other shown in FIG. 3 by driving each of the corresponding actuators A9�A11 of the thigh joint system 26.
This control unit 42 is connected to each of sub control sections 43A�43D disposed inside each of the construction units (the body unit 2, the head unit 3, each of the arm units 4A and 4B, and each of the leg units 5A and 5B) respectively so that this control unit 42 can provide necessary power supply voltage to these sub control sections 43A�43D and can communicate with these sub control sections 43A�43D.
Furthermore, each of the sub control sections 43A�43D is connected to the actuators A1�A14 inside the corresponding construction units respectively so that the actuators A1�A14 inside the construction units can be driven to the designated condition based on the various types of control commands given from the main control section 40.
And the main control section 40 decides the following performance based on the judged result, a control program pre-stored in an internal memory 40A, and the loaded various types of control parameters, then delivers the control command based on the decision result to the corresponding sub control sections 43A�43D. As a result, based on the control command, under the control of the sub control sections 43A�43D, the corresponding actuators A1�A14 are driven, and therefore the performance such as having the head unit 3 swing up and down, right and left, having the arm units 4A and 4B put up, and walking, can be realized by the robot 1.
At the same time, the multiplexing part 63 adds tag information to be used when dividing the image data D1A�D1D according to the original channels at the image receiving unit 61 to the image data D1A�D1D equivalent to the multiplexed each one frame, and delivers so obtained tag information adding multiplexing data D2 to a transmitting part 64.
Furthermore, in the restoring part 67, tag information is extracted from the tag information adding multiplexing data D3, and based on the tag information, one frame of the image data D4A�D4D included in the tag information adding multiplexing data D3 is allocated to the corresponding channel. Then the image data D4A�D4D allocated to each channel are separately delivered to corresponding image processing parts 68A�68D in the main control section 40.
Then, the image processing parts 68A�68D, based on the provided image data D4A�D4D, execute processing such as color detecting processing, motion detecting processing, or edge detecting processing disclosed in H11-129274. The various types of detected processing results are provided to an upper controller of a subsequent stage, and based on these various types of the detected processing results, various types of control processing for above-mentioned autonomous performance are conducted.
The selector 70 has a plurality of input ports 70 IN1�70 INm and a plurality of output ports 70 OUT1�70 OUTn, and under the control of the controller 73, connects the designated input ports 70 IN1�70 INm and the output ports 70 OUT1�70 OUTn.
Then, the selector 70 inputs the image data D1A�D1 m for each channel provided from the CCD cameras 50A and 50B and image processing parts 62A and 62B via the input ports 70 IN1�70 INm respectively, and using one frame of frame memory disposed inside (not shown in Figs.), delivers these image data D1A�D1 m to the multiplexer 71 via the corresponding output ports 70 OUT1�70 OUTn with synchronizing with a vertical synchronizing signal SVSINK1 as a standard signal in the image transmitting unit 51 provided from one of the CCD cameras 50A and 50B.
The multiplexer 71 has a plurality of input ports 71 IN1�71 INn arranged corresponding to each of the output ports 70 OUT1�70 OUTn of the selector 70, a plurality of AND circuits 80 1�80 n arranged corresponding to these input ports 71 IN1�71 INn, and a memory 81 comprising a plurality of one bit memory domain 81 1�81 n corresponding to these AND circuits 80 1�80 n (hereinafter referred to as a switch memory). Each of these input ports 71 IN1�71 INn is connected to the corresponding first signal input terminal of the AND circuits 80 1�80 n while each of the second signal input terminal is connected to the corresponding one bit memory domain 81 1�81 n of the switch memory 81.
In this case, a flag is stored in one of the one bit memory domain 81 1�81 n of the switch memory 81 of the multiplexer 71 by the controller 73. This flag is updated at every arrival of a falling period, in which the image data of the vertical synchronizing signal SVSINK1 is not transmitted within the falling period, and is stored in only one of the memory domain 81 1�81 n corresponding to the channel decided to be output within the next arising period of the vertical synchronizing signal SVSINK1 by the controller 73.
Accordingly, in the multiplexer 71, during the rising period of the vertical synchronizing signal SVSINK1, only the AND circuits 80 1�80 n corresponding to the one bit memory domain 81 1�81 n, in which the flag in the switch memory 81 is stored, validly operate, therefore, only one frame of the image data D1A�D1 m input via the input ports 71 IN1�71 INn connected to the AND circuits 80 1�80 n is delivered, via the AND circuits 80 1�80 n and the output port 71 OUT sequentially, to the tag encoder 72 as multiplexing data D10.
At this time, the tag encoder 72 is, as the above-mentioned tag information D11, provided in advance with the port number of the output ports 70 OUT1�70 OUTn of the selector 70 to which one frame of the image data D1A�D1 m is output (hereinafter referred to as an output port number), the port number of the input ports 7 IN1�70 INm of the selector 70 connected to the output ports 70 OUT1�70 OUTn at this time (hereinafter referred to as an input port number), and the frame number of the frame.
On the other hand, the controller 73 comprises, as is obvious from FIG. 7, a plurality of counters C1�Cn arranged corresponding to each of the output ports 70 OUT1�70 OUTn of the selector 70, an image select register 90 for memory holding after-mentioned output selection control information D12, a control active flag register 91 for storing a flag indicating the update of the output selection control information D12 (hereinafter referred to as a control active flag), an output selection flag register 92 comprising one bit memory domain 92 1�92 n corresponding to each of the one bit memory domain 81 1�81 n of the switch memory 81 of the multiplexer 71, and a tag information storing register 93 for temporally storing the tag information D11.
In this case, the controller 73 is previously provided from the upper controller with the output selection control information D12 in which the port number of the input ports 70 IN1�70 INm of the selector 70 to which each of the output ports 70 OUT1�70 OUTn is expected to be connected, and the output frequency at which the image data of each channel connected to each of the output ports 70 OUT1�70 OUTn of the selector 70 is output (output frequency) are prescribed. Accordingly, the controller 73 keeps the output selection control information D12 as a table shown in FIG. 10 in the image select register 90.
Then, the controller 73, at the initial stage, based on the output selection control information D12 kept in the image select register 90, controls the selector 70, so that corresponding each of the output ports 70 OUT1�70 OUTn and the input ports 70 IN1�70 INm of the selector 70 can be connected.
Furthermore, after above, the controller 73 decides the channel to be output within the next rising period of the vertical synchronizing signal SVSINK1 (in practice, the output ports 70 OUT1�70 OUTn of the selector 70 connected to this channel) at every arrival of the falling period of the above-mentioned vertical synchronizing signal SVSINK1 provided from the CCD cameras 50A and 50B (FIG. 6) so that the output frequency of each channel given as above-mentioned output selection control information D12 is matched.
Then, the controller 73 adds the above-mentioned tag information D11 to one frame of the image data D1A�D1 m provided within the next rising period of the vertical synchronizing signal SVSINK1 to the tag encoder 72 by providing the tag information D11 based on the decision result to the tag encoder 72 via the tag information storing register 93 within the present falling period of the vertical synchronizing signal SVSINK1.
In addition, the controller 73 temporally keeps the flag based on the so decided result in the corresponding one bit memory domain 92 1�92 n in the output selection flag register 92 during the present falling period of the vertical synchronizing signal SVSINK1, as well as outputs so decided one frame of the image data D1A�D1 m of the channel during the rising period of the vertical synchronizing signal SVSINK1 from the multiplexer 71 by storing the flag in the one bit memory domain 81 1�81 n corresponding to the switch memory 81 of the multiplexer 71 based on the flag immediately after the start-up of the next rising period of the vertical synchronizing signal SVSINK1.
Then, the controller 73 is configured to connect the each of the designated input ports 70 IN1�70 INm and the output ports 70 OUT1�70 OUTn as well as to initialize each of the counters C1�Cn based on the new output selection control information D12 and to execute the same control processing based on the output selection control information D12 as described above by controlling the selector 70 based on the new output selection control information D12 stored in the image select register 90 corresponding to that the control active flag is stored in the control active flag register 91 within the falling period of the vertical synchronizing signal SVSINK1 right after above.
For example, the output frequency �1� of the channel connected to the output port with port number �2� means that one frame of the image data D1A�D1 m of the channel connected to the output port 70 OUT2 with port number �2� is required to be output while one frame of the image data D1A�D1 m of the channel connected to the output port 70 OUT1 with port number �1� is input. Therefore, as shown in FIG. 11, in case that there are only two output ports 70 OUT1 and 70 OUT2 with port numbers �1� and �2� respectively, under this output frequency, the image data D1A�D1 m of the channel connected to the output port 70 OUT2 with port number �2� are output at all times (the case of N=1 in FIG. 11).
Further, the output frequency �4� of the channel connected to the output port 70 OUT2 with port number �2� means that one frame of the image data D1A�D1 m of the channel connected to the output port 70 OUT2 with port number �2� is required to be output while four frames of the image data D1A�D1 m of the channel connected to the output port 70 OUT1 with port number �1� are input. Therefore, in this example of FIG. 11, while four frames of the image data D1A�D1 m of the channel connected to the output port 70 OUT1 with port number 1 are input, one frame of the image data D1A�D1 m of the channel connected to the output port 70 OUT2 with port number �2� is output and the image data D1A�D1 m of the channel connected to the output port 70 OUT1 with port number �1� is output as for the rest three frames (the case of N=4 in FIG. 11).
When �0� is assigned as the output frequency, the image data D1A�D1 m of the channel connected to the output ports 70 OUT1�70 OUTn to which this output frequency is assigned are not output. Therefore, for example in FIG. 11, only the image data D1A�D1 m of the channel connected to the output port 70 OUT1 with port number �1� are output (the case N=0 in FIG. 11).
The controller 73 controls the multiplexer 71 so that the image data D1A�D1 m of each of the channels connected to each of the output ports 70 OUT1�70 OUTn respectively are output in one frame at a time with the designated output frequency respectively based on the output frequency for each of the output ports 70 OUT1�70 OUTn of the selector 70 kept in the image select register 90 as the output selection control information D12.
In specifically, the controller 73, at first, sets the value of the output frequency corresponding to each of the output ports 70 OUT1�70 OUTn of the selector 70 kept in the image select register 90 as the initial value of each of the counters C1�Cn corresponding to the output ports 70 OUT1�70 OUTn respectively. For example as shown in FIG. 12, when there are four output ports 70 OUT1�70 OUT4 in the selector 70 and the output frequencies are �3�, �2�, and �5� corresponding to the output ports 70 OUT2�70 OUT4 with port numbers �2�, �3�, and �4� respectively, these values are set as the initial values of the counters C2�C4 corresponding to the output ports 70 OUT2�70 OUT4 respectively.
Then the controller 73 monitors the vertical synchronizing signal SVSINK1, and reads the count values of the counters C2�C4 at every arrival of the falling period of the vertical synchronizing signal SVSINK1. When the count value �1� cannot be found in the counters C2�Cn corresponding to the output ports 70 OUT2�70 OUTn with port number after �2� of the selector 70, the controller 73 decides the channel connected to the output port 70 OUT1 with port number �1� as the channel to which the image data D1A�D1 m is output next, as well as makes one by one decrements of the count values of each of the counters C2�Cn corresponding to the output ports 70 OUT2�70 OUTn with port number after �2�.
For example in FIG. 12, in the initial condition, as the count values of each of the counters C2�C4 corresponding to the output ports 70 OUT2�70 OUT4 with port number �2�, �3�, and �4� of the selector 70 are �3�, �2�, and �5� respectively, the channel connected to the output port 70 OUT1 with port number �1� is decided as the channel to which the image data D1A�D1 m is output next, and the count values of the counters C2�C4 corresponding to the output ports 70 OUT2�70 OUT4 with port numbers �2�, �3�, and �4� are made one by one decrements to be updated to �2�, �1�, and �4� respectively.
On the other hand, when count value �1� is found in the counters C2�Cn corresponding to the output ports 70 OUT2�70 OUTn with port number after �2� of the selector 70, the controller 73 decides the channel connected to the output ports 70 OUT2�70 OUTn of the selector 70 corresponding to the counters C2�Cn as the channel to which the image data D1A�D1 m is output next as well as resets the count values of the counters C2�Cn to the initial values.
For example in FIG. 12, in the channel deciding processing of the second frame, as the count values of the counters C2�C4 corresponding to the output ports 70 OUT2�70 OUT4 with port numbers �2�, �3�, and �4� of the selector 70 are �2�, �1�, and �4�, the channel connected to the output port 70 OUT3 with port number �3� of the selector 70 is decided as the channel to which the image data D1A�D1 m is output next, and the count value of the counter C3 corresponding to this channel is set to the initial value �2�.
Here, when the controller 73 reads each count value of the counters C2�Cn after the arrival of the falling period of the vertical synchronizing signal SVSINK1, the controller 73 reads the counters C2�Cn corresponding to the output ports 70 OUT2�70 OUTn with smaller port number of the selector 70 sequentially from the smallest port number. Therefore, for example the case of deciding the third frame of the channel having multiple counters C2�Cn with count value �1� in FIG. 12, the channel connected to the output ports 70 OUT2�70 OUTn with the smallest port number of the selector 70 among the channels corresponding to these counters C2�Cn is decided as the channel to which the image data D1A�D1 m is output next.
And the controller 73 sequentially decides the channel to which one frame of the image data D1A�D1 m is output, controls the multiplexer 71 based on the decision result as mentioned above, and provides the tag information D11 based on the decision result to the tag encoder 72 by conducting above-mentioned channel deciding processing at every arrival of the falling period of the vertical synchronizing signal SVSINK1.
In actually, the controller 73, in the initial condition, controls the selector 70 base on the output selection control information D12 previously provided from the upper controller, then starts the multiplexing processing procedure RT1 at step SP0 after connecting the input ports 70 IN1�70 INm and the output ports 70 OUT2�70 OUTn, monitors the provided vertical synchronizing signal SVSINK1 at the following step SP1, and waits for the detection of a rising edge or a falling edge of the vertical synchronizing signal SVSINK1.
Then, the controller 73 goes to step SP3 with a negative result at this step SP2, then decides the channel to be output during the coming rising period of the vertical synchronizing signal SVSINK1 at following steps SP3�SP11 as well as executes various types of processing based on the decision result.
On the other hand, the controller 73 goes to step SP4 with a positive result at this step SP3, then controls the selector 70 based on a new output selection control information D12 stored in the image select register 90 (FIG. 7), then reconnects designated each of the input ports 70 IN1�70 INm and the output ports 70 OUT1�70 OUTn of the selector 70.
Following above, the controller 73 goes to step SP5 and resets the control active flag stored in the control active flag register 91 and goes to step SP6 and initializes the count value of each of the counters C1�Cn (FIG. 7) base on the new output selection control information D12, then goes to step SP7.
Then, the controller 73 reads each of the present counters C2�Cn in order at SP7, and judges whether count value �1� is in the counters C2�Cn at the following step SP8.
The controller 73 goes to step SP9 with a positive result at step SP8, decides the channel to be output during the coming rising period of vertical synchronizing signal SVSINK1 corresponding to the counters C2�Cn, and stores the flag in the one bit memory domain 92 1�92 n of the output selection flag register 92 (FIG. 7) corresponding to the counters C2�Cn based on the decision result as well as resets the count values of the counters C2�Cn to the initial values, then goes to step SP11.
On the other hand, the controller 73 goes to step SP10 with a negative result at step SP9, decides the channel connected to the output port 70 OUT1 with port number �1� of the selector 70 as the channel to be output during the coming rising period of the vertical synchronizing signal SVSINK1, and stores the flag in the one bit memory domain 92 1�92 n of the output selection flag register 92 (FIG. 7) corresponding to the channel based on the decision result as well as makes one by one decrements of the count values of the counters C2�Cn except for the counter C1 corresponding to the channel, then goes to step SP11.
When the controller 73 detects the rising edge of the vertical synchronizing signal SVSINK1 at step SP1, the controller 73 goes to step SP12 through step SP2 and stores the flag in the corresponding one bit memory domain 81 1�81 n in the switch memory 81 (FIG. 7) of the multiplexer 71 based on the flag stored in one of the one bit memory domain 92 1�92 n in the output selection flag register 92.
As described above, the controller 73 controls the multiplexer 71 and the tag encoder 72 based on the output selection control information D12 provided from the upper controller, so that the image data D1A�D1 m of each channel are multiplexed at the designated output frequency by frame.
The tag reader 100 has one frame of the frame memory (not shown in Figs.), and buffers the tag information adding multiplexing data D3 provided from the receiving part 66 (FIG. 6) by frame as well as reads and delivers the above-mentioned tag information D11 (FIG. 7) added to the buffered one frame of the tag information adding multiplexing data D3 (one frame of the image data D1A�D1 m (FIG. 7)) to the controller 103.
The tag reader 100 delivers one frame of the tag information adding multiplexing data D3 (one frame of the image data D1A�D1 m), from which this tag information D11 is read out, to the demultiplexer 101 at every arrival of the rising period of the vertical synchronizing signal SVSINK1 provided also to the image receiving unit 61 from above-mentioned CCD cameras 50A and 50B.
The demultiplexer 101 has a plurality of output ports 101 OUT1�101 OUTn disposed corresponding to each of the input ports 71 IN1�71 INn of the multiplexer 71 (FIG. 7) of the image transmitting unit 51 (FIG. 6), a plurality of AND circuits 110 1�110 n disposed corresponding to each of the output ports 101 OUT1�101 OUTn, and a switch memory 111 in which a plurality of one bit memory domain 111 1�111 n are disposed corresponding to each of these AND circuits 110 1�110 n. Each of these output ports 101 OUT1�101 OUTn of the demultiplexer 101 is connected to the corresponding signal output terminal of the AND circuits 110 1�110 n while the first signal input terminal of each of these AND circuits 110 1�110 n is connected to the corresponding one bit memory domain 111 1�111 n in the switch memory 111, and the second signal input terminal is connected to the input port 101 IN of the demultiplexer 101 respectively.
In this case, the flag is stored in one of the one bit memory domain 111 1�111 n of the switch memory 111 of the demultiplexer 101 by the controller 103. This flag is updated at every arrival of the rising period of the vertical synchronizing signal SVSINK1 for the first timing, is stored only in the one bit memory domain 111 1�111 n connected to one of the output ports 101 OUT1�101 OUTn decided as the output ports 101 OUT1�101 OUTn of the demultiplexer 101 to which the controller 103 is expected to output next image data D1A�D1 m during the falling period of the last vertical synchronizing signal SVSINK1.
In this manner, in the demultiplexer 101 during the rising period of the vertical synchronizing signal SVSINK1, only the AND circuits 110 1�110 n connected to one bit memory domain 111 1�111 n in which the flag of the switch memory 111 is stored validly operate, and one frame of the tag information adding multiplexing data D3 (one frame of the image data D1A�D1 m) provided from the tag reader 100 is delivered to the selector 102 only via the validly operating AND circuits 110 1�110 n and the output ports 101 OUT1�101 OUTn connected to the validly operating AND circuits 110 1�110 n.
The selector 102 has a plurality of input ports 102 IN1�102 INn disposed corresponding to each of the output ports 70 OUT1�70 OUTn (FIG. 6) of the selector 70 (FIG. 6) of the image transmitting unit 51 (FIG. 5) and a plurality of the output ports 102 OUT1�102 OUTm disposed corresponding to each of the input ports 70 IN1�70 INm of the selector 70, and each of these input ports 102 IN1�102 INn is connected to the corresponding output ports 101 OUT1�101 OUTn of the demultiplexer 101.
And the selector 102, in the initial condition, connects the designated input ports 102 IN1�102 INn and the output ports 102 OUT1�102 OUTm under the control of the controller 103.
Accordingly, the selector 102 during the rising period of the vertical synchronizing signal SVSINK1, outputs one frame of the tag information adding multiplexing data D3 (one frame of the image data D1A�D1 m) output from one of the output ports 101 OUT1�101 OUTn of the demultiplexer 101 to the corresponding image processing parts 68A�68D of a subsequent stage as the image data D4A�D4 m only via the input ports 102 IN1�102 INn of the selector 102 connected to the output ports 101 OUT1�101 OUTn and the output ports 102 OUT1�102 OUTm connected to the input ports 102 IN1�102 INn.
On the other hand, the controller 103, as is obvious from FIG. 15, has an image select register 120 for memory holding the output selection control information D12, a control active flag register 121 for storing the control active flag, an output selection flag register 122 in which one bit memory domain 122 1�122 n is disposed corresponding to each of the one bit memory domain 111 1�111 n of the demultiplexer 101, and a tag information storing register 123 for temporally keeping the tag information D11 provided from the tag reader 100.
The controller 103, in the initial condition, controls the selector 102 based on the output selection control information D12 kept in the image select register 120, so that the designated input ports 102 IN1�102 INn and output ports 102 OUT1�102 OUTm of the selector 102 are connected.
In addition, the controller 103 temporally keeps the tag information D11 provided from the tag reader 100 in the tag information storing register 123 at every the tag reader 100's accumulating one frame of the tag information adding multiplexing data D3 (one frame of the image data D1A�D1 m) in the internal frame memory, as well as analyzes the tag information D11 kept in the tag information storing register 123 at every arrival of the falling period of the vertical synchronizing signal SVSINK1.
Then, the controller 103 decides the output ports 101 OUT1�101 OUTn of the demultiplexer 101 to which one frame of the tag information adding multiplexing data D3 (one frame of the image data D1A�D1 m) is output during the coming rising period of the vertical synchronizing signal SVSINK1, while comparing the connection relation between each of the input ports 102 IN1�102 INn and the output ports 102 OUT1�102 OUTm of the selector 102 obtained based on the tag information D11 with the connection relation between each of the input ports 102 IN1�102 INn and the output ports 102 OUT1�102 OUTm of the selector 102 obtained based on the output selection control information D12 kept in the image select register 120.
Then, the controller 103, while temporally keeping the flag based on the decision result in the corresponding one bit memory domain 122 1�122 n of the output selection flag register 122 during the falling period of the vertical synchronizing signal SVSINK1, stores the flag in the corresponding one bit memory domain 111 1�111 n of the switch memory 111 of the demultiplexer 101 corresponding to the one bit memory domain 122 1�122 n in which the flag is stored immediately after the start-up of the next rising period of the vertical synchronizing signal SVSINK1, and controls the tag reader to output one frame of the tag information adding multiplexing data D3 (one frame of the image data D1A�D1 m) presently accumulated, so that one frame of the tag information adding multiplexing data D3 is output from the output ports 101 OUT1�101 OUTn decided by the demultiplexer 101.
Then, the controller 103 controls the selector 102 based on the new output selection control information D12 stored in the image select register 120, corresponding to the control active flag's being stored in the control active flag register 121 during the following falling period of the vertical synchronizing signal SVSINK1, so that the controller 103 connects each of the designated input ports 102 IN1�102 INn and the output ports 102 OUT1�102 OUTm of the selector 102 and controls the tag reader 100 and the demultiplexer 101 based on the new output selection control information D12 in the same manner as above-mentioned.
In actually, the controller 103, in the initial condition, controls the selector 102 based on the output selection control information D12 from the upper controller, so that the controller 103 starts the restoration processing procedure RT2 at step SP20 after connecting each of the designated input ports 102 IN1�102 INn and the output ports 102 OUT1�102 OUTm of the selector 102, monitors the above-mentioned vertical synchronizing signal SVSINK1 at the following step SP21, and waits for the detection of the rising edge or the falling edge of vertical synchronizing signal SVSINK1.
Following above, the controller 103 goes to step SP23 with a negative result at SP22, then, at steps SP23�SP27, decides the output ports 101 OUT1�101 OUTn of the demultiplexer 101 to which one frame of the tag information adding multiplexing data D3 (one frame of the image data D1A�D1 m) is output during the coming rising period of the vertical synchronizing signal SVSINK1 as well as executes various types of processing based on the decision result.
On the other hand, the controller 103 goes to step SP24 with a positive result at step SP23 and controls the selector 102 based on the new output selection control information D12 stored in the image select register 120 (FIG. 15), so that each of the designated input ports 102 IN1�102 INn and the output ports 102 OUT1�102 OUTm of the selector 102 are connected, and the control active flag stored in the control active flag register 121 is reset at the following step SP25, then the controller 103 goes to step SP26.
Furthermore, the controller 103 goes to step SP27, decides the output ports 101 OUT1�101 OUTn of the demultiplexer 101 to which one frame of the tag information adding multiplexing data D3 (one frame of the image data D1A�D1 m) during the coming rising period of the vertical synchronizing signal SVSINK1 based on the analysis result of the tag information D11 at step SP26 and the output selection control information D12 stored in the image select register 120, and stores the flag in the one bit memory domain 122 1�122 n of the output selection flag register 122 corresponding to the output ports 101 OUT1�101 OUTn based on the decision result, then goes back to step SP21.
Then, the controller 103 goes to step SP28 through step SP22 with the detection of the rising edge of the vertical synchronizing signal SVSINK1 at step SP21, and stores the flag in the one bit memory domain 111 1�111 n of the switch memory 111 of the demultiplexer 101 corresponding to the one bit memory domain 122 1�122 n in which the flag is stored in the output selection flag register 122.
As described above, the controller 103 controls the tag reader 100, the demultiplexer 101, and the selector 102 based on the tag information D11 embedded in the tag information adding multiplexing data D3 and the output selection control information D12 provided from the upper controller, so that each one frame of the image data D1A�D1 m comprising the tag information adding multiplexing data D3 is allocated for each channel.
In the above construction, the image transmission system 60 of the robot 1 at the image transmitting unit 51, multiplexes the image data D1A�D1 m of the multiple channels to be input with switching the channels by frame and adds the tag information D11 to each frame of the multiplexed image data D1A�D1 m, while at the image receiving unit 61, the image transmission system 60 of the robot 1 analyzes the tag information D11 added to each frame of the image data D1A�D1 m transmitted from the image transmitting unit 51 and outputs the multiplexed image data D1A�D1 m transmitted from the image transmitting unit 51 with dividing by frame to the corresponding channel.
Subsequently, in this image transmission system 60, since the image data D1A�D1 m of the multiple channels can be transmitted via single transmission line without format modification, no additional wiring is required to increase the image data D1A�D1 m to be input to the image transmitting unit 51, which makes such increase easy.
Furthermore, in this image transmission system 60, the output ratio of the image data D1A�D1 m for each of the channels can be specifically configured since the output frequency to be used when the controller 73 of the multiplexing part 63 (FIG. 7) of the image transmitting unit 51 decides the channel to be output next is configured to be shown as the number of the output frames of the channel for the number of the input frames of the image data D1A of the standard channel as above described. In addition, in this image transmission system 60, the ratio of the output of the other channels for the standard channel can be guaranteed since the output of the image data D1A�D1 m of each of the channels are controlled based on the output frequency as described in FIGS. 11 and 12.
In the above construction, the image transmitting unit 51 multiplexes the image data D1A�D1 m of the multiple channels to be input with switching the channels by frame and adds the tag information D11 to each frame of the multiplexed image data D1A�D1 m, while the image receiving unit 61 analyzes the tag information D11 added to each frame of the image data D1A�D1 m transmitted from the image transmitting unit 51 and outputs the multiplexed image data D1A�D1 m transmitted from the image transmitting unit 51 with dividing by frame to the corresponding channel, so that the image data D1A�D1 m of the multiple channels can be transmitted via single transmission line without format modification. Therefore, an image transmission system which is capable of efficiently transmitting the image data D1A�D1 m of multiple channels can be realized by using the existing system formed on the premise of transmitting and receiving the image data through a single transmission line.
In the above embodiment, the present invention is applied to the robot 1 so configured as shown in FIGS. 1�5, however, this invention is not limited to the above embodiment, and can be applied to various types of robot apparatus, and can be widely applied to, other than robot apparatus, various image transmission devices, transmitting devices, or receiving devices which are configured to transmit image data of multiple channels.
Furthermore, in the above embodiment, the multiplexer 71 and the controller 73 are constructed, as shown in FIG. 7, as the multiplexing means for multiplexing the image data D1A�D1 m of multiple channels to be input with switching the channels by frame in the multiplexing part 63 of the image transmitting unit 51, however, the present invention is not limited to the above embodiment, and can be applied to various constructions.
Still further, in the above embodiment, in the multiplexing part 63 of the image transmitting unit 51, the tag encoder 72 as an image information adding means for adding the tag information D11 (image information) to each of the image data D1A�D1 m for each frame multiplexed by the multiplexer 71, as shown in FIG. 8, embeds the data of the tag information D11 at the four continuing pixel positions at the bottom of the left edge in the image. However, this invention is not limited to the above embodiment, and the tag information D11 can be embedded in other positions and can be added to the image data D1A�D1 m by other methods. Also, for example in existing text broadcasting, the tag information D11 can be superposed on a vertical retrace line period portion of the image data D1A�D1 m. In addition, in the above embodiment, in the restoring part 67 of the image receiving unit 61, the controller 103 as an analyzing means for analyzing the tag information D11 added to each of the image data D1A�D1 m for each frame transmitted from the image transmitting unit 51 controls the demultiplexer 101 and the selector 102 based on the tag information and the output selection control information provided from the upper controller. However, the present invention is not limited to the above embodiment, and for example, the demultiplexer 101 and the selector 102 can be controlled based only on the tag information D11 read from the image data D1A�D1 m. Furthermore, in the above embodiment, in the restoring part 67 of the image receiving unit 61, the dividing means for dividing by frame and outputting each of the image data D1A�D1 m for each frame transmitted from the image transmitting unit 51 to the corresponding channels is comprised of the demultiplexer 101 the selector 102, and the controller 103 so configured as FIG. 15, however, the present invention is not limited to the above embodiment, and can be applied to various constructions.
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