Source: http://www.google.com/patents/US7900104?dq=7,346,545
Timestamp: 2017-12-14 07:17:26
Document Index: 754391182

Matched Legal Cases: ['Application No. 04', 'Application No. 00', 'Application No. 00', 'Application No. 04', 'Application No. 04', 'Application No. 00', 'Application No. 04', 'Application No. 2001', 'Application No. 2001', 'Application No. 00']

Patent US7900104 - Test pattern compression for an integrated circuit test environment - Google Patents
A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied...http://www.google.com/patents/US7900104?utm_source=gb-gplus-sharePatent US7900104 - Test pattern compression for an integrated circuit test environment
Publication number US7900104 B2
Application number US 12/405,409
Also published as DE60018101D1, DE60018101T2, DE60030896D1, DE60030896T2, EP1236111A1, EP1236111A4, EP1236111B1, US6327687, US6543020, US7111209, US7509546, US20020053057, US20030131298, US20070016836, US20090259900, WO2001038981A1
Publication number 12405409, 405409, US 7900104 B2, US 7900104B2, US-B2-7900104, US7900104 B2, US7900104B2
Patent Citations (162), Non-Patent Citations (93), Referenced by (15), Classifications (12), Legal Events (2)
US 7900104 B2
US7610539 * Nov 5, 2008 Oct 27, 2009 Nec Laboratories America, Inc. Method and apparatus for testing logic circuit designs
EP1236111B1 Nov 15, 2000 Feb 9, 2005 Mentor Graphics Corporation Test pattern compression for an integrated circuit test environment
EP1475643A1 Nov 15, 2000 Nov 10, 2004 Mentor Graphics Corporation Test pattern compression for an integrated circuit test environment
EP1475643B1 Nov 15, 2000 Sep 20, 2006 Mentor Graphics Corporation Test pattern compression for an integrated circuit test environment
JP3920640B2 Title not available
2 Bardell et al., "Pseudorandom arrays for built-in tests," IEEE Trans. on Computers, vol. C-35, No. 6, pp. 653-658 (1986).
16 European Communication dated Apr. 26, 2005, from European Application No. 04 01 7880.
17 European Communication dated Dec. 22, 2003, from European Application No. 00 97 8684.
18 European Communication under Rule 51(4) EPC dated Aug. 17, 2004, from European Application No. 00 97 8684.
19 European Communication under Rule 51(4) EPC dated Feb. 27, 2006, from European Application No. 04 01 7880.
20 European Decision to Grant dated Aug. 24, 2006, from European Application No. 04 01 7880.
21 European Decision to Grant dated Dec. 30, 2004, from European Application No. 00 97 8684.
22 European Search Report dated Sep. 8, 2004, from European Application No. 04 01 7880.
23 Fagot et al., "On Calculating Efficient LFSR Seeds for Built-In Self Test," IEEE, pp. 7-14 (1999).
24 Frohwerk, "Signature analysis: a new digital field services method," Hewlett-Packard Journal, pp. 2-8 (May 1977).
25 Ghosh-Dastidar et al., "Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information," Proc. ITC, pp. 95-102 (Sep. 1999).
26 Golomb, Shift Register Sequences, Holden Day, San Francisco (1967).
27 Hamzaoglu et al., "Reducing Test Application Time for Full Scan Embedded Cores," IEEE Proc. FTCS, pp. 260-267 (1999).
29 Hayes, "Transition count testing of combinational logic circuits," IEEE Transactions on Computers, vol. C-25, No. 6, pp. 613-620 (1976).
30 Hellebrand et al., "Built-in Test for Circuits With Scan Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers," IEEE Trans. on Computers, vol. C-44, pp. 223-233 (Feb. 1995).
31 Hellebrand et al., "Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE International Test Conference, pp. 120-129 (1992).
32 Hellebrand et al., "Pattern Generation for a Deterministic BIST Scheme," Proc. I-ICAD, pp. 88-94 (1995).
33 Hetherington et al., "Logic BIST for Large Industrial Designs: Real Issues and Case Studies," Proc. ITC, pp. 358-367 (1999).
34 International Preliminary Examination Report from International Application No. PCT/US00/31377.
35 International Search Report from International Application No. PCT/US00/31377.
36 Ireland et al., "Matrix method to determine shift-register connections for delayed pseudorandom binary sequences," Electronics Letters, vol. 4 No. 15, pp. 309-310 (1968).
37 Ishida et al., "COMPACT: A hybrid method for compressing test data," Proc. VLSI Test Symposium, pp. 62-69 (1998).
38 Ivanov et al., "Programmable BIST space compactors," IEEE Transactions on Computers, vol. C-45, No. 12, pp. 1393-1404 (1996).
39 Iyengar et al., "Built-In Self-testing of sequential circuits using precomputed test sets," Proc. VLSI Test Symposium, pp. 418-423 (1998).
40 Japanese Office Action dated May 26, 2005, including an English-language translation, from Japanese Patent Application No. 2001-540467.
41 Japanese Office Action dated Sep. 20, 2006, including an English-language translation, from Japanese Patent Application No. 2001-540467.
42 Jas et al., "Scan vector compression/decompression using statistical coding," Proc. VLSI Test Symposium, pp. 114-120 (1999).
43 Jas et al., "Test vector decompression via cyclical scan chains and its application to testing core-based designs," Proc. ITC, pp. 458-464 (1998).
44 Jone et al., "Space compression method for built-in self testing of VLSI circuits," Int. Journal of Computer Aided VLSI Design, vol. 3, pp. 309-322 (1991).
45 Kapur et al., "Design of an efficient weighted random pattern generation system," Proc. ITC., pp. 491-500 (1994).
46 Karpovsky et al., "Board-Level Diagnosis by Signature Analysis," Proc. ITC, pp. 47-53 (1988).
47 Karpovsky et al., "Design of Self-Diagnostic Boards by Multiple Signature Analysis," IEEE Trans. on Computers, vol. 42, No. 9, pp. 1035-1044 (Sep. 1993).
48 Kiln et al., "On using signature registers as pseudorandom pattern generators in built-in self-testing," IEEE Trans. CAD of IC, vol. CAD-7, No. 8, 1988, pp. 919-928.
49 Koenemann, c/o IBM Corp. , B56/901, "LFSR-Coded Test Patterns for Scan Designs," Proc. European Test Conference, pp. 237-242 (1991).
50 Konemann et al., "Built-In Logic Block Observation Techniques," IEEE Test Conference, 6 pp. (1979).
51 Kundu, "On Diagnosis of Faults in a Scan-Chain," Proc. VLSI Test Symp., pp. 303-308 (1993).
52 Langdon, Jr., "An Introduction to Arithmetic Coding," IBM J. Res. Develop., vol. 28, No. 2, pp. 135-149 (Mar. 1984).
53 Latawiec, "New method of generation of shifted linear pseudorandom binary sequences," Proc. IEE, vol. 121, No. 8, pp. 905-906 (1974).
54 Lew Yan Voon et al., "BIST Linear Generator based on Complemented Outputs," IEEE VLSI Test Symp., pp. 137-142 (1992).
55 Li et al., "Space compression methods with output data modification," IEEE Trans. CAD if Integrated Circuits and Systems, vol. CAD-6, No. 2, pp. 290-294 (1987).
56 Mano, "Decoders and Multiplexers," in Computer System Architecture, Chapter 2, pp. 50-54 (1982).
57 Mrugalski et al., "Synthesis of pattern generators based on cellular automata with phase shifters," Proc. ITC, pp. 368-377 (1999).
58 Muradali et al., "A new procedure for weighted random built-in self-test," Proc. ITC., pp. 600-669 (1990).
59 Narayanan et al., "An Efficient Scheme to Diagnose Scan Chains," Proc. ITC, pp. 704-713 (1997).
60 Pateras et al., "Cube-contained random patterns and their application to the complete testing of synthesized multi-level circuits," Proc. ITC., pp. 473-482 (1991).
61 Pouya et al., "Synthesis of zero-aliasing elementary-tree space compactors," Proc. VLSI Test Symp., pp. 70-77 (1998).
62 Rajski et al., "Accumulator-based compaction of test responses," IEEE Trans. on Computers, vol. C-42, No. 6, pp. 643-650 (1993).
63 Rajski et al., "Automated Synthesis of Large Phase Shifters for Built-In Self-Test," Proc. ITC, Paper 41.1, pp. 1047-1056, (1998).
64 Rajski et al., "Decompression of Test Data Using Variable-Length Seed LFSRs," Proc. VLSI Test Symp., pp. 426-433, (1995).
65 Rajski et al., "Design of Phase Shifters for BIST Applications," Proc. VLSI Test Symp., pp. 218-224 (1998).
66 Rajski et al., "Diagnosis of Scan Cells in BIST Environment," IEEE Trans. on Computers, vol. 48, No. 7, pp. 724-731 (Jul. 1999).
67 Rajski et al., "Test Data Decompression for Multiple Scan Designs with Boundary Scan," IEEE Trans. on Computers, vol. 47, No. 11, pp. 1188-1200 (Nov. 1998).
68 Rajski et al., "Test responses compaction in accumulators with rotate carry adders," IEEE Trans. CAD of Integrated Circuits and Systems, vol. CAD-12, No. 4, pp. 531-539 (1993).
69 Rajski et al., Chapter 3, "Test Response Compaction," and Chapter 4, "Fault Diagnosis," in Arithmetic Built-In Self-Test for Embedded Systems, pp. 87-133 (1998).
70 Reddy et al., "A Data compression technique for built-in self-test," IEEE Trans. on Computers, vol. C-37, pp. 1151-1156 (1988).
71 Saluja et al., "Testing Computer Hardware through Data Compression in Space and Time," Proc. ITC, pp. 83-88 (1983).
72 Savir, "Syndrome-testable design of combinational circuits," IEEE Trans. on Computers, vol. C-29, No. 6, pp. 442-451 (1980).
73 Saxena et al., "Accumulator compression testing," IEEE Trans. on Computers, vol. C-35, No. 4, pp. 317-321 (1986).
74 Saxena et al., "Analysis of checksums, extended-precision checksums, and cyclic redundancy," IEEE Trans. on Computers, vol. C-39, No. 7, pp. 969-975, 1990.
75 Saxena et al., "Extended precision checksums," Proc. FTCS, pp. 142-147 (1987).
76 Serra et al., "The analysis of one-dimensional linear cellular automata and their aliasing properties," IEEE Trans. CAD of Integrated Circuits and Systems, vol. CAD-9, No. 7, pp. 767-778 (1990).
77 Smith, "Measures of the effectiveness of fault signature analysis," IEEE Trans. on Computers, vol. C-29, No. 6, pp. 510-514 (1980).
78 Supplementary European Search Report dated Jul. 24, 2003, from European Application No. 00 97 8684.
79 Touba et al., "Altering a pseudo-random bit sequence for scan-based BIST," Proc. ITC, pp. 167-175 (1996).
80 Touba et al., "Transformed pseudo-random patterns for BIST," Proc. VLSI Test Symp., pp. 410-416 (1995).
81 Tsai et al., "STARBIST: Scan autocorrelated random pattern generation," Proc. DAC, pp. 472-477 (1997).
82 Venkataraman et al., "An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers," IEEE, pp. 572-577 (1993).
83 Waicukauski et al., "A method for generating weighted random test patterns," IBM J. Res. Develop., vol. 33, No. 2, pp. 149-161 (Mar. 1989).
84 Wang, "BIST Using Pseudorandom Test Vectors and Signature Analysis," IEEE Custom Integrated Circuits Conference, pp. 1611-1618 (1998).
85 Williams et al., "Bounds and analysis of aliasing errors in linear-feedback shift registers," IEEE Trans. CAD of Integrated Circuits and Systems, vol. CAD-7, No. 1, pp. 75-83 (1988).
US9519026 Sep 30, 2014 Dec 13, 2016 Apple Inc. Compressed scan testing techniques
International Classification G01R31/28, G01R31/3183, G06F11/22, G01R31/3185
European Classification G01R31/3183E, G01R31/3183M, G01R31/3185S3D