Source: http://www.google.com/patents/US7382723?dq=5,890,152
Timestamp: 2016-08-29 02:56:40
Document Index: 227943171

Matched Legal Cases: ['art 31', 'arts 32', 'art 36', 'art 37', 'art 31', 'art 37', 'art 31', 'arts 32', 'art 36', 'art 37', 'art 212', 'arts 220', 'arts 230', 'art 212', 'arts 220', 'arts 230', 'art 210', 'art 213', 'art 53', 'art 210', 'art 213', 'art 212', 'art 212', 'art 220', 'art 220', 'art 220', 'art 220', 'art 230', 'art 210', 'art 213', 'arts 230', 'art 310', 'art 320', 'art 320', 'arts 340', 'arts 350', 'art 310', 'art 320', 'art 320', 'arts 340', 'arts 350', 'art 314', 'art 313', 'art 313', 'art 314', 'art 313', 'art 313', 'art 310', 'art 320', 'art 320', 'art 320', 'art 340', 'art 320', 'art 350', 'art 314', 'art 410', 'arts 420', 'arts 430', 'art 410', 'arts 420', 'arts 430', 'art 411', 'art 412', 'art 414', 'art 411', 'art 412', 'art 414', 'art 410', 'art 410', 'art 420', 'arts 420', 'arts 430', 'art 411', 'art 412', 'art 414']

Patent US7382723 - Hitless switching system and transmission apparatus - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA hitless switching system includes a sending apparatus and a receiving apparatus. The sending apparatus includes: a distributing part for dividing an original signal into a plurality of signals; and a transmitting part for transmitting the divided signals over one or a plurality of transmission lines...http://www.google.com/patents/US7382723?utm_source=gb-gplus-sharePatent US7382723 - Hitless switching system and transmission apparatusAdvanced Patent SearchPublication numberUS7382723 B2Publication typeGrantApplication numberUS 10/376,262Publication dateJun 3, 2008Filing dateMar 3, 2003Priority dateMar 1, 2002Fee statusLapsedAlso published asCA2420151A1, CA2420151C, DE60322456D1, EP1341329A2, EP1341329A3, EP1341329B1, EP1959599A2, EP1959599A3, EP1959599B1, US20030165115Publication number10376262, 376262, US 7382723 B2, US 7382723B2, US-B2-7382723, US7382723 B2, US7382723B2InventorsAtsushi Sutoh, Kazuhiro OdaOriginal AssigneeNippon Telegraph And Telephone CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (26), Non-Patent Citations (2), Referenced by (1), Classifications (15), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetHitless switching system and transmission apparatus
FIG. 2 shows a block diagram of a transmission system for explaining the virtual concatenation technology. The system shown in FIG. 2 includes a sending side apparatus and a receiving side apparatus. The sending side apparatus includes a distributing part 31, indicator providing parts 32 1˜32 n, sending interfaces 33 1˜33 n. The receiving side apparatus includes receiving interfaces 34 1˜34 n, elastic store memories 35 1˜35 n, a phase control part 36, and a restoring part 37. The distributing part 31 receives a signal 201 to which virtual concatenation is to be applied. The signal 201 is divided and transmitted. Then, a restored signal 202 is output from the restoring part 37.
The signal 201 is divided into a plurality of virtual concatenation signals in the distributing part 31. Then, an indicator used for phase control is provided to each virtual concatenation signal in the indicator providing parts 32 1˜32 n. After that, the virtual concatenation signals are input into the sending interfaces 33 1˜33 n so as to be transmitted over the same route or different routes.
The virtual concatenation signals received by the receiving interfaces 34 1˜34 n are stored in the elastic store memories 35 1˜35 n.
Phases for reading the virtual concatenation signals stored in the elastic store memories 35 1˜35 n are aligned by the phase control part 36. Then, the virtual concatenation signals are input into the restoring part 37 so that the original signal is restored.
An object of the present invention is to provide a hitless switching system and a transmission apparatus, without increasing complexity of the system and the apparatus, to support signals of large capacity accompanying increase of recent LAN traffic, and to support signals of intermediate bandwidth corresponding to virtual concatenations such as VC-3-Xv (50�X Mbit/s (X is an integer of 1˜256)) and VC-4-Xv (150�X Mbit/s (X is an integer of 1˜256)) other than VC-3, VC-4 and VC-4-Xc(X is 4, 16, 64 or 256).
According to this invention, by using virtual concatenation technology, hitless switching can be realized for supporting signals of intermediate bandwidth corresponding to virtual concatenations such as VC-3-Xv (50�X Mbit/s (X is an integer of 1˜256)) and VC-4-Xv (150�X Mbit/s (X is an integer of 1˜256)) other than VC-3, VC-4 and VC-4-Xc(X is 4, 16, 64 or 256).
In the system shown in FIG. 4, the sending side apparatus includes a distributing part 212, indicator providing parts 220 1˜220 n, branch parts 230 1˜230 n, first sending interfaces 240 1˜240 n, and second sending interfaces 250 1˜250 n. The distributing part 212 divides the original signal into a plurality of virtual concatenation signals defined in ITU-T G.707. Each of the indicator providing parts 220 1˜220 n provides H4 byte multi-frame to the virtual concatenation signal for detecting phase difference between virtual concatenation signals. Each of the branch parts 230 1˜230 n branches the virtual concatenation signal into two systems. Each of the first sending interfaces 240 1˜240 n transmits one of the branched virtual concatenation signals to a first transmission line. Each of the second sending interfaces 250 1˜250 n transmits one of the branched virtual concatenation signals to a second transmission line. The first transmission lines and the second transmission lines can be one route or a plurality of routes. This applies also to other Embodiments.
The receiving side apparatus of the hitless switching system includes first receiving interfaces 260 1˜260 n for receiving virtual concatenation signals from first transmission lines, second receiving interfaces 270 1˜270 n for receiving virtual concatenation signals from the second transmission lines, first elastic store memories 280 1˜280 n, second elastic store memories 290 1˜290 n, a phase control part 210, selectors 211 1˜211 n, and a restoring part 213. The selectors 211 1˜211 n corresponds to the switching part 53 in FIG. 3.
The first elastic store memories 280 1˜280 n are for temporarily storing virtual concatenation signals received from the first transmission lines. The second elastic store memories 290 1˜290 n are for temporarily storing virtual concatenation signals received from the second transmission lines. The phase control part 210 detects phase difference between virtual concatenation signals that are transmitted over different routes and aligns phases for reading virtual concatenation signals from each elastic store memory. Each of the selectors 211 1˜211 n, performs switching between a virtual concatenation signal received from the first transmission line and a virtual concatenation signal received from the second transmission line. The restoring part 213 restores the original signal from the virtual concatenation signals in conformity with ITU-T G.707.
The original signal 200 to which hitless switching is to be applied is received by the distributing part 212. The distributing part 212 divides the original signal into a plurality of virtual concatenation signals. After that, each of the indicator providing part 220 1˜220 n writes a specific pattern (indicator) in the H4 byte multi-frame of the virtual concatenation signal, in which the specific pattern is used for detecting phase difference for restoring the divided signals into the original signal and is used for detecting phase difference for hitless switching, however, the phase differences are not distinguished. According to this process, the original signal is divided into the virtual concatenation signals. For example, the original signal (A) is divided into n signals which can be represented as A1, A2, . . . , An. A1 is sent to the indicator providing part 220 1. An is sent to the indicator providing part 220 n.
Next, each of the virtual concatenation signals from the indicator providing part 220 1˜220 n is branched into two different systems by the branch part 230 1˜230 n. One of the branched signals is sent to the first transmission line by corresponding one of the first sending interfaces 240 1˜240 n. Another one of the branched signals is sent to the second transmission line by corresponding one of the second sending interfaces 250 1˜250 n.
The virtual concatenation signals sent over the first transmission lines are transmitted to the first receiving interfaces 260 1˜260 n, via the synchronous digital transmission network. In the same way, the virtual concatenation signals sent over the second transmission lines are transmitted to the second receiving interfaces 270 1˜270 n, via the synchronous digital transmission network.
In the receiving side, the first receiving interfaces 260 1˜260 n receive virtual concatenation signals sent over the first transmission lines, and the second receiving interfaces 270 1˜270 n receive virtual concatenation signals sent over the second transmission lines. The virtual concatenation signals received from the first transmission lines are temporarily stored in the first elastic store memories 280 1,280n, and the virtual concatenation signals received from the second transmission lines are temporarily stored in the second elastic store memories 290 1˜290 n. After that, the phase control part 210 detects phase differences on the basis of the specific pattern (indicator) written in the H4 byte multi-frame. Then, after phases for reading the virtual concatenation signals from the elastic store memories are aligned, the virtual concatenation signals are sent to the selectors 211 1˜211 n. In each of the selectors 211 1˜211 n, switching of selection system is performed within one bit between the virtual concatenation signal received from the first transmission line and the virtual concatenation signal received from the second transmission line. The switching means that each of the selectors 211 1˜211 n selects between receiving a signal from the first elastic store memory or receiving a signal from the second elastic store memory.
The virtual concatenation signals in which switching of selection system is performed by the selectors 211 1˜211 n are sent to the restoring part 213, so that the original signal is restored.
In this embodiment, one branch part is provided to each virtual concatenation signal in the sending side, and one selector is provided to each virtual concatenation signal in the receiving side. However, the branch parts 230 1˜230 n can be replaced by a switch for branching the virtual concatenation signals. In addition, the selectors 211 1˜211 n can be replaced by a switch for selecting between virtual concatenation signals.
In the system shown in FIG. 5, the sending side apparatus includes a branch part 310, a first distributing part 320 1, a second distributing part 320 2, first indicator providing parts 340 1˜340 n, second indicator providing parts 350 1˜350 n, first sending interfaces 360 1˜360 n, and second sending interfaces 370 1˜370 n.
The branch part 310 branches the original signal into two systems. The first distributing part 320 1 divides one original signal in the branched original signals (which will be referred to as first original signal in the following) into a plurality of virtual concatenation signals according to the standard of virtual concatenation defined in ITU-T G.707. The second distributing part 320 2 divides another original signal (which will be referred to as second original signal in the following) into a plurality of virtual concatenation signals according to the standard of virtual concatenation defined in ITU-T G.707. Each of the first indicator providing parts 340 1˜340 n provides H4 byte multi-frame to the virtual concatenation signal divided from the first original signal for detecting phase difference between virtual concatenation signals. Each of the second indicator providing parts 350 1˜350 n provides H4 byte multi-frame to the virtual concatenation signal divided from the second original signal for detecting phase difference between virtual concatenation signals. The phase difference includes phase difference caused by dividing the original signal into virtual concatenation signals and sending the virtual concatenation signals and phase difference caused by sending the virtual concatenation signals over different routes. Each of the first sending interfaces 360 1˜360 n transmits one of the divided virtual concatenation signals divided from the first original signal to a first transmission line. Each of the second sending interfaces 370 1˜370 n transmits one of the divided virtual concatenation signals divided from the second original signal to a second transmission line.
The receiving side apparatus of the hitless switching system includes first receiving interfaces 380 1˜380 n for receiving virtual concatenation signals from first transmission lines, second receiving interfaces 390 1˜390 n for receiving virtual concatenation signals from the second transmission lines, first elastic store memories 311 1˜311 n, second elastic store memories 312 1˜312 n, a phase control part 314, a first restoring part 313 1, a second restoring part 313 2, and a selector 315.
The first elastic store memories 311 1˜311 n are for temporarily storing virtual concatenation signals received from the first transmission lines. The second elastic store memories 312 1˜312 n are for temporarily storing virtual concatenation signals received from the second transmission lines. The phase control part 314 detects phase differences among all virtual concatenation signals and aligns phases for reading virtual concatenation signals from each elastic store memory. The first restoring part 313 1 restores the first original signal from the virtual concatenation signals read from the first elastic store memories 311 1˜311 n. The second restoring part 313 2 restores the second original signal from the virtual concatenation signals read from second elastic store memories 312 1˜312 n. The selector 315 performs switching between the first original signal and the second original signal.
The original signal 200 to which hitless switching is to be applied is received by the dividing part 310. Then, the original signal is branched into the first original signal and the second original signal. After that, the first original signal is received by the first distributing part 320 1, and the second original signal is received by the second distributing part 320 2. The first original signal and the second original signal are the same. The first distributing part 320 1 divides the first original signal into a plurality of virtual concatenation signals. After that, each of the first indicator providing part 340 1˜340 n writes a specific pattern (indicator) in the H4 byte multi-frame of the virtual concatenation signal, in which the specific pattern is used for detecting phase difference for restoring the divided signals into the original signal and is used for detecting phase difference for hitless switching. Then, the virtual concatenation signals are sent to the first transmission lines from the first sending interfaces 360 1˜360 n.
The second distributing part 320 2 divides the second original signal into a plurality of virtual concatenation signals. After that, each of the second indicator providing part 350 1˜350 n writes a specific pattern (indicator) in the H4 byte multi-frame of the virtual concatenation signal, in which the specific pattern is used for detecting phase difference for restoring the divided signals into the original signal and is used for detecting phase difference for hitless switching. Then, the virtual concatenation signals are sent to the second transmission lines from the second sending interfaces 370 1˜370 n.
In the receiving side, the first receiving interfaces 380 1˜380 n receive the first virtual concatenation signals sent over the first transmission lines, and the second receiving interfaces 390 1˜390 n receive the second virtual concatenation signals sent over the second transmission lines. The first virtual concatenation signals received from the first transmission lines are temporarily stored in the first elastic store memories 311 1˜311 n, and the second virtual concatenation signals received from the second transmission lines are temporarily stored in the second elastic store memories 312 1˜312 n. After that, the phase control part 314 detects phase differences among all virtual concatenation signals on the basis of the specific pattern (indicator) written in the H4 byte multi-frame, so that phases for reading the virtual concatenation signals are aligned.
In the system shown in FIG. 6, the sending side apparatus includes a distributing part 410, indicator providing parts 420 1˜420 n, branch parts 430 1˜430 n, a selector 440, a first sending interfaces 450 1˜450 n, and a second sending interface 460. The distributing part 410 divides the original signal into a plurality of virtual concatenation signals defined in ITU-T G.707. Each of the indicator providing parts 420 1˜420 n provides H4 byte multi-frame to the virtual concatenation signal for detecting phase difference between virtual concatenation signals, in which the phase difference includes phase difference caused by dividing the original signals into virtual concatenation signals and sending the virtual concatenation signals and phase difference caused by sending the virtual concatenation signals over different routes. Each of the branch parts 430 1˜430 n branches the virtual concatenation signal into a first virtual concatenation signal and a second virtual concatenation signal. The selector 440 selects a second virtual concatenation signal used for hitless switching from a plurality of second virtual concatenation signals. Each of the first sending interfaces 450 1˜450 n transmits one of the divided virtual concatenation signals to a first transmission line. The second sending interface 460 transmits the second virtual concatenation signal to a second transmission line.
The receiving side apparatus of the hitless switching system includes first receiving interfaces 470 1˜470 n for receiving first virtual concatenation signals from first transmission lines, a second receiving interface 480 for receiving a second virtual concatenation signal from the second transmission line, first elastic store memories 490 1˜490 n, a second elastic store memory 485, a phase control part 411, a branch part 412, selectors 413 1˜413 n, and a restoring part 414.
The first elastic store memories 490 1˜490 n are for temporarily storing the first virtual concatenation signals received from the first transmission lines. The second elastic store memory 480 is for temporarily storing the second virtual concatenation signal received from the second transmission line. The phase control part 411 detects phase differences among all virtual concatenation signals that are transmitted over different routes and aligns phases for reading signals from each elastic store memory. The branch part 412 is for branching the second virtual concatenation signal into a plurality of second virtual concatenation signals. Each of the selectors 413 1˜413 n performs switching between the first virtual concatenation signal and the second virtual concatenation signal. The restoring part 414 restores the original signal from the selected virtual concatenation signals.
The original signal 410 to which hitless switching is to be applied is received by the distributing part 410. The distributing part 410 divides the original signal into a plurality of virtual concatenation signals. After that, each of the indicator providing part 420 1˜420 n writes a specific pattern (indicator) in the H4 byte multi-frame of the virtual concatenation signal. According to this process, the original signal is divided into the virtual concatenation signals.
Next, each of the virtual concatenation signals from the indicator providing parts 420 1˜420 n is branched into the first virtual concatenation signal and the second virtual concatenation signal by the branch parts 430 1˜430 n. The branched first virtual concatenation signals are sent to the first sending interfaces 450 1˜450 n. The branched second virtual concatenation signals are sent to the selector 440. The selector 440 selects a virtual concatenation signal that is to be used for hitless switching from a plurality of second virtual concatenation signals. The selected second virtual concatenation signal is sent to the second sending interface 460.
In the receiving side, the first receiving interfaces 470 1˜470 n receive the first virtual concatenation signals, and the second receiving interface 480 receives the second virtual concatenation signal. The first virtual concatenation signals are temporarily stored in the first elastic store memories 490 1˜490 n, and the second virtual concatenation signal is temporarily stored in the second elastic store memory 485. After that, the phase control part 411 detects phase differences on the basis of the specific pattern (indicator) written in the H4 byte multi-frame.
Then, after phases for reading the virtual concatenation signals from the elastic store memories are aligned, the first virtual concatenation signals are sent to the selectors 413 1˜413 n. The second virtual concatenation signal is sent to the branch part 412 and branched and sent to each of the selectors 413 1˜413 n.
In each of the selectors 413 1˜413 n that receives the first and second virtual concatenation signals, switching of selection system is performed within one bit between the first virtual concatenation signal and the second virtual concatenation signal. The virtual concatenation signals in which switching of selection system is performed by the selectors 413 1˜413 n are sent to the restoring part 414, so that the original signal is restored.
As mentioned above, according to the present invention, phase differences among the first virtual concatenation signals and the second virtual concatenation signals transmitted over a plurality of different routes are detected by using the H4 byte multi-frame in virtual concatenation defined in ITU-T G.707. Then, the elastic store memories absorb the phase differences. Therefore, hitless switching can be realized for signals of intermediate bandwidth corresponding to virtual concatenation such as VC-3-Xv (50�X Mbit/s (X is an integer of 1˜256)) and VC-4-Xv (150�X Mbit/s (X is an integer of 1˜256)) other than VC-3, VC-4 and VC-4-Xc(X is 4, 16, 64 or 256). In addition, virtual concatenation can be compatible with hitless switching, and path trace by J1 byte can be compatible with hitless switching. In addition, it can be avoided that complexity of the apparatuses in the system increases, and increase of delay can be avoided.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4908839Apr 5, 1989Mar 13, 1990Nec CorporationChannel switching systemUS5029333 *Dec 7, 1989Jul 2, 1991Northern Telecom LimitedCommunications systemUS5442620 *Mar 26, 1992Aug 15, 1995At&T Corp.Apparatus and method for preventing communications circuit misconnections in a bidirectional line-switched ring transmission systemUS5461622 *Jun 14, 1994Oct 24, 1995Bell Communications Research, Inc.Method and apparatus for using SONET overheat to align multiple inverse multiplexed data streamsUS5631896 *Jul 17, 1995May 20, 1997Nippon Telegraph And Telephone CorporationHitless path switching apparatus and methodUS5825821 *Mar 11, 1996Oct 20, 1998Nec CorporationHitless switch device and method of switching between different pathsUS6118795 *Jul 21, 1997Sep 12, 2000Fujitsu LimitedReception pointer processing apparatus in SDH transmission systemUS6246668 *Jun 9, 1998Jun 12, 2001Nortel Networks LimitedHitless manual path switching using linked pointer processorsUS6490282 *Mar 12, 1999Dec 3, 2002Nec CorporationSwitching system for asynchronous transfer mode switchUS6678241 *Nov 30, 1999Jan 13, 2004Cisc Technology, Inc.Fast convergence with topology switchingUS6870859 *Mar 3, 2000Mar 22, 2005Kdd CorporationMultiplexing system and multiplexing method of tributary signalsUS6963560 *Sep 28, 2001Nov 8, 2005AlcatelMethod and system for frame and pointer alignment of SONET data channelsUS7079541 *Apr 13, 2000Jul 18, 2006France Telecom SaSystem for access to a synchronous network of the type comprising transmitting equipment and receiving equipmentUS7167442 *May 22, 2001Jan 23, 2007Nortel Networks LimitedHitless protection switchingUS20010046207 *Jan 3, 2001Nov 29, 2001Fujitsu LimitedTransmitting apparatusUS20020018261Jun 21, 2001Feb 14, 2002Koji TakeguchiTransmission systemUS20020018468 *Aug 10, 2001Feb 14, 2002Nec CorporationDevice, method and system for transferring frameUS20020080812 *Dec 10, 2001Jun 27, 2002Andreas StadlerMethod and device for converting virtually concatenated data streams into contiguosly concatenated data streamsUS20030043838 *Dec 12, 2001Mar 6, 2003Yoriaki ShimadaTransmission method allocating a time-division multiplex transmission band according to a channel band of a user packet frameEP0696111A2Jul 17, 1995Feb 7, 1996Nippon Telegraph And Telephone CorporationA hitless path switching apparatus and methodEP1261157A2May 22, 2002Nov 27, 2002Nortel Networks LimitedHitless protection switchingJP2001053705A Title not availableJP2002026855A Title not availableJPH0795186A Title not availableJPS62137934A Title not availableWO2001031818A1Oct 28, 1999May 3, 2001Fujitsu LimitedTransmission system* Cited by examinerNon-Patent CitationsReference1A. Sutoh, et al., IEICE, pp. 1-16, "Study of Hitless Switching With Virtual Concatenation Technologies", Mar. 7, 2002.2Nevin Jones, et al., "A proposal for SONET Standards on Virtual Concatenation of High Order and Low Order SPEs", Lucent Technologies, Nortel Networks. URL:http://www.tl.org/filemgr/filesearch.taf?<SUB>-</SUB>function=list&<SUB>-</SUB>UserReference=622B9A2345CDC7DE39EDB1D6>, XP-002150418, Jan. 17-21, 2000, pp. 1-11.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS20100129075 *Nov 23, 2009May 27, 2010Fujitsu LimitedTransmission system, transmission apparatus, and control method of transmission system* Cited by examinerClassifications U.S. Classification370/227, 370/535International ClassificationH04J3/14, H04J1/16, H04L1/22, H04J3/06Cooperative ClassificationH04J3/062, H04L1/22, H04J3/0602, H04J3/14, H04J2203/0094European ClassificationH04L1/22, H04J3/06B, H04J3/14, H04J3/06ALegal EventsDateCodeEventDescriptionApr 22, 2003ASAssignmentOwner name: NIPPON TELEGRAPH AND TELEPHONE CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUTOH, ATSUSHI;ODA, KAZUHIRO;REEL/FRAME:013984/0556Effective date: 20030220Sep 16, 2011FPAYFee paymentYear of fee payment: 4Jan 15, 2016REMIMaintenance fee reminder mailedJun 3, 2016LAPSLapse for failure to pay maintenance feesJul 26, 2016FPExpired due to failure to pay maintenance feeEffective date: 20160603RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services