Source: http://www.google.com/patents/US5227834?ie=ISO-8859-1&dq=7181427
Timestamp: 2014-12-27 02:32:59
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Matched Legal Cases: ['art 17', 'art 23', 'art 17', 'art 17', 'art 20', 'art 17', 'art 15', 'art 18', 'art 18', 'art 18', 'art 23', 'art 23', 'art 17', 'art 6', 'art 16', 'art 20', 'art 16', 'art 16', 'art 16', 'art 23', 'art 15', 'art 54', 'art 16', 'art 16', 'art 16', 'art 16', 'art 19']

Patent US5227834 - Image sensing system having a one chip solid state image device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn imaging sensing system includes a solid state image device composed of one chip and a controller for controlling the solid state image device. The solid state image device further includes an image sensor of a charge accumulation type for receiving light from an object and for outputting an electric...http://www.google.com/patents/US5227834?utm_source=gb-gplus-sharePatent US5227834 - Image sensing system having a one chip solid state image deviceAdvanced Patent SearchPublication numberUS5227834 APublication typeGrantApplication numberUS 07/774,168Publication dateJul 13, 1993Filing dateOct 15, 1991Priority dateJan 6, 1987Fee statusPaidAlso published asUS5371567, US5469239Publication number07774168, 774168, US 5227834 A, US 5227834A, US-A-5227834, US5227834 A, US5227834AInventorsTokuji Ishida, Toshio Norita, Jun HasegawaOriginal AssigneeMinolta Camera Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (29), Non-Patent Citations (4), Referenced by (11), Classifications (27), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetImage sensing system having a one chip solid state image deviceUS 5227834 AAbstract An imaging sensing system includes a solid state image device composed of one chip and a controller for controlling the solid state image device. The solid state image device further includes an image sensor of a charge accumulation type for receiving light from an object and for outputting an electric signal to the controller. Further, an exemplary embodiment of an image device includes a decoder for decoding a control signal and for outputting a decode signal. A timing signal output indicates the timing of a charge accumulation of an image sensor controller for controlling the image sensor in accordance with the decode signal. In an exemplary embodiment, the controller includes an A/D convertor for converting the electric signal into a digital signal.
What is claimed is: 1. A system comprising a solid state image device composed of one chip and separate control means controlling said solid state image device from outside the one chip, wherein said solid state image device further includes:an image sensor of a charge accumulation type for receiving light from an object and for outputting an electric signal; input means having n (n≦1) input terminals for receiving n control signals from said control means and for outputting said n control signals; decoding means for decoding the control signals and for outputting m (m≦n) decode signals; signal output means for outputting a timing signal indicating the timing of terminating charge accumulation of the image sensor; image sensor control means for controlling said image sensor in response to said decode signal and said timing signal; and output means for outputting the electric signal from said image sensor to said image device control means, and wherein, said separate image device control means further includes:output means for outputting the control signal through n lines to said solid state image device; input means for inputting the electric signal from said solid state image device; and A/D converting means for converting the electric signal into a digital signal. 2. System according to claim 1, wherein said image sensor is an accumulating-type sensor.
3. System according to claim 2, wherein said control signal is a signal for controlling an accumulating period of said image sensor.
4. System according to claim 2, wherein said control signal is a signal for controlling an accumulating mode of a plurality of modes.
5. System according to claim 2, wherein said control signal is a signal indicating an accumulating mode or data outputting mode.
6. System according to claim 1, wherein said control means is composed of one chip.
7. A two chip system comprising a solid state image device composed of one chip and separate image device control means composed of one chip for controlling said solid state image device from outside said one chip, wherein said solid state image device further includes:an image sensing means of a charge accumulation type for receiving light from an object and for producing an electric signal; image sensing control means for transmitting two signals to said image sensing means through two lines and for outputting the electric signal in response to the signals; analog processing means for carrying out an analog processing of the electric signal from said image sensing means and outputting the processed analog signal; first output means for outputting the processed analog signal to said image device control means; and second output means for outputting an A/D convertor start signal in response to an operation of said image sensing control means; and wherein, said separate image device control means further includes:first input means for inputting the processed analog signal; second input means for inputting the A/D convertor start signal; and A/D converting means for converting the processed analog signal into a digital signal in response to the A/D convertor start signal. 8. System according to claim 7, further comprising inhibiting means for inhibiting said second output means from outputting the A/D convertor start signal when A/D converting means operation is not required.
9. System according to claim 7, wherein said image sensing means further includes an image sensor for receiving light to output a signal and an analog processing device for carrying out an analog processing and for outputting a processed signal to said first output means as the electrical signal, and wherein said output means outputs the electric signal to said control means.
10. System according to claim 9, wherein said analog processing includes compensating dark current of said image sensor signal.
11. A two chip system comprising a solid state image device composed of one chip and separate control means composed of one chip for controlling said solid state image device from outside the one chip, wherein said solid state image device further includes:an image sensor of a charge accumulation type for receiving light from an object to output an electric signal; analog processing means for carrying out an analog processing of the electric signal from said image sensor and outputting the processed signal; output means for outputting the processed signal to said control means; input means for inputting a control signal from said control means; decoding means for decoding the control signal to output a decode signal; and image sensor control means for controlling said image sensor in accordance with said decode signal, and wherein, said separate control means further includes:output means for outputting the control signal to said solid state image device; input means for inputting the processed signal from said solid state image device; and processing means for carrying out a predetermined process based on the processed signal received. 12. A two chip system according to claim 11, wherein said control means is a micro-computer.
13. A two chip system according to claim 11, wherein said system is used in an auto-focus system of a camera.
14. A two chip system according to claim 12, wherein said processing means of said control means carries out a focus detection process.
15. A two chip system according to claim 11, wherein the control signal is coded to indicate a plurality of modes, and said image sensor control means decodes the coded control signal to output a decoded control signal and controls said image sensor based on the decoded control signal.
16. A two chip system comprising a solid state image device composed of one chip and a micro-computer composed of another single chip, wherein said solid state image device further includes:an image sensor of a charge accumulation type for receiving light from an object and for outputting an electric signal; image sensor control means for controlling said image sensor; analog processing means for carrying out an analog processing of the electric signal from said image sensor and for outputting the processed analog signal; and output means for outputting the processed analog signal through a single line to said micro-computer, and wherein, said micro-computer further includes:input means for inputting the processed analog signal from said solid state image device; processing means for carrying out a predetermined process based on the processed analog signal received; and and A/D converting means for converting the processed analog signal into a digital signal, based on which said processing means of said micro-computer carries out the predetermined process. 17. A two chip system according to claim 16, wherein said system is used in an auto-focus system of a camera.
18. A two chip system according to claim 16, wherein said processing means of said micro-computer carries out a focus detection process.
19. A two chip system according to claim 16, wherein said solid state image device further includes:input means for inputting a control signal from said control means; and decoding means for decoding the control signal to output a decode signal said image sensor control means controlling said image sensor in accordance with said decode signal, and wherein, said micro-computer further includes output means for outputting the control signal to said solid state image device. 20. A two chip system comprising a solid state image device composed of one chip and a micro-computer composed of another single chip, wherein said solid state image device further includes:an image sensor of a charge accumulation type for receiving light from an object and for outputting an electric signal; image sensor control means for controlling said image sensor; analog processing mean for amplifying the electric signal from said image sensor and for outputting the processed analog signal; and output means for outputting the processed analog signal to said micro-computer, and wherein said micro-computer further includes:input means for receiving the processed analog signal from said solid state image device; processing means for carrying out a predetermined process based on the processed analog signal received; and an A/D converting means for converting the processed analog signal into a digital signal based on which said processing means of said micro-computer carries out the predetermined process. 21. A two chip system comprising a solid state image device composed of one chip and a micro-computer composed of another single chip, wherein said solid state image device further includes:an image sensor of a charge accumulation type for receiving light from an object and for outputting an electric signal; image sensor control means for controlling said image sensor; analog processing means for eliminating noise included in the electric signal from the image sensor and for outputting a processed analog signal; and output means for outputting the processed analog signal to said micro-computer, and wherein said micro-computer further includes:input means for receiving the processed analog signal from said solid state image device; processing means for carrying out a predetermined process based on the processed analog signal received; and an A/D converting means for converting the processed analog signal into a digital signal based on which said processing means of said micro-computer carries out the predetermined process. 22. System according to claim 21, wherein said noise is due to background output of the image sensor which is outputted from the image sensor when no light is coming in the image sensor.
23. System according to claim 21, wherein said analog processing means comprises:a capacitor; charging means for charging electric charges to the capacitor to an amount corresponding to said electric signal; and detecting means for detecting a difference in voltages of the capacitor before and after charging by the charging means. 24. System according to claim 23, wherein the analog processing means further comprises amplifying means for amplifying the electric signal from which noise has been eliminated.
25. A two chip system comprising a solid state image device composed of one chip and control means composed of another single chip for controlling said solid state image device, wherein said solid state image device further includes:an image sensor of a charge accumulation type for receiving light from an object and for outputting an electric signal; analog processing means for carrying out an analog processing of the electrical signal from said image sensor and outputting a processed analog signal; output means for outputting the processed analog signal to a control means; input means for receiving a control signal from said control means; decoding means for decoding the control signal to output a decode signal; and image sensor control means for controlling said image sensor in response to said decode signal, said control means further including:output means for outputting the control signal to said solid state image device; input means for receiving the processed analog signal from said solid state image device; and processing means for carrying out a predetermined process based on the processed analog signal received, said control signal being coded to indicate a plurality of modes, and said image sensor control means decoding the coded control signal to output a decoded control signal for controlling said image sensor based on the decoded control signal. Description
This application is a continuation of application Ser. No. 07/437,512, filed Nov. 16, 1989, now abandoned.
To be brief, an exemplary imaging sensing system includes a solid state image device composed of one chip and a controller for controlling the solid state image device. The solid state image device further includes an image sensor of a charge accumulation type for receiving light from an object and for outputting an electric signal to the controller. Further, an exemplary embodiment of the image device includes a decoder for decoding a control signal and for outputting a decode signal. A timing signal output indicates the timing of a charge accumulation of an image sensor controller for controlling the image sensor in accordance with the decode signal. In an exemplary embodiment, the controller includes an A/D convertor for converting the electric signal into a digital signal.
FIGS. 11a-c are a view showing a structure of an output part of a shift register in FIG. 7 in comparison with the conventional example.
The integration time control part 17 monitors a signal AGCOS given from the monitoring photo diode MPD through the buffer 28, and in response to the result of monitoring, it controls integration time by properly outputting control signals BG, ST and STICG controlling the barrier gate 22, the storage part 23 and the storage part clear gate 24, respectively. In that monitoring, the integration time control part 17 compensates dark component in accordance with .5 the monitor signal AGCOS by a monitor output compensating signal AGCDOS given from the buffer 31. The integration time control part 17 also sends and receives signals to and from the system controller through the I/O control part 20, and among them, an integration end signal TINT is cited as a signal given to the system controller. Furthermore, this integration time control part 17 forcedly completes integration by a command signal SHM from the system controller when the value of integration of the photoelectric conversion part 15 does not reach a predetermined value of integration within a predetermined time, and also generates an automatic gain control signal AGC responding to the value of integration to give it to the analog processing part 18 to compensate the insufficient state of the integration output attending thereon in the stage of analog processing. The analog processing part 18 eliminates noise components from a signal OS from the shift register 26 and the output signals OSY and OSR from the color temperature detecting photo diodes 13 and 14 and performs various analog processing such as dark output signal compensation and automatic gain control as basic functions thereof. In addition, as detailed later, this analog processing part 18 has function for performing standard voltage clamping to match an output signal with a dynamic range of an A/D conversion part of the system controller.
To meet this conflicting requirement, the present inventors considered to vary the depth of the n-type region 37 beneath the above-described P+ film 39 along the longitudinal direction. This means that as the structure of the major part thereof (portion close to the surface) is shown in FIG. 10(c) which is sectioned in the direction shown by a dotted line 40 in a plane configuration view of FIG. 10(a), on forming an n-type region beneath the P+ film 39, an region 37a and an n region 37b are formed by varying the quantity of injection of phosphorus ions along the longitudinal direction (right-left direction in FIG. 10).
A large number of cascade connections of the picture element photo diode PD, the monitoring photo diode MPD, the barrier gate 22, the storage part 23, the storage part clear gate 24, the shift gate 25 and the shift register 26 as described above in FIG. 8 are arranged in the transverse direction, and, for example, the number of segments of the shift registers 26 is 128. Note that as seen at the right end of the above-mentioned arrangement, the number of segments of the picture element photo diode PD, the monitoring photo diode MPD, the barrier gate 22, the storage part 23, the storage part clear gate 24 and the shift gate 25 is smaller by five in comparison with that of the shift register 26 at the right end side. In reverse, only the number of segments of the shift registers 26 is larger by five at the right end side. The reason is as follows. A capacitor C1 receiving the output of the shift register 26, and formed in one-piece with the shift register 26, and specifically as shown in the conventional example of FIG. 11(a), it is formed by a junction capacitance produced between a n+ region 46 formed by diffusion and a P-type region 47.
Then, a distribution capacitance C' is produced also between an aluminum film 49 for shielding light which is filmed on the surface through an insulating film 48 and the above-mentioned n+ region 46 This undesirable distribution capacitance C', as shown in FIG. 11(c), works in parallel with the original capacitor C1 formed by a junction capacitance to increase the output capacitance, resulting in a reduction in photo sensitivity. Also, the above-mentioned distribution capacitance C' produced between the above-mentioned aluminum film 49 for shielding light and the n+ region 46 has large scattering and causes large scattering of photo sensitivity of the product, therefore being not preferable. Then, as shown in FIG. 11(b), the portion 50 of the aluminum film 49 positioned at the output stage is eliminated. This removes almost all of the above-mentioned distribution capacitance C', and the output capacitance C1 is scarcely affected by it, resulting in an increase in photo sensitivity. On the other hand, light shield of the eliminated portion is performed by the field mask 9 as shown in FIG. 2. This means that the junction capacitance portion as the above-mentioned capacitor C1 is disposed at the position deviating from the window of the field mask 9. This elimination is not limited to the capacitor C1 installed at the output stage of the shift register 26, but the aluminum films on the tops of capacitors C2 -C6 installed at each output stage are also eliminated.
In FIG. 7, five pairs of the picture element photo diodes PD and the monitoring photo diodes MPD at the right end and three pairs thereof at the left end are shielded by aluminum film. These light-shielded photo diodes generates dark charges used, for example, for dark compensation of the output of the picture element photo diode A portion of the photo diode array 21 is assigned as a standard part M0 and another portion is assigned as a reference part M1. For example, the standard part M0 comprises 40 combinations of the picture element photo diode and the monitoring photo diode, and the reference part M1 comprises 50 combinations thereof. Note that there is no structural difference between the standard part M0 and the reference part M1, and they are distinguished by software processing in a system controller as described later.
FIG. 13 shows an embodiment following such a view point, and the output signal of the red color temperature detecting photo diode 14 is sent to the shift register 26 utilizing any one of three light-shielded picture element photo diodes OPD (second one from left in illustration) and the barrier gate, the storage part and the shift gate which are connected thereto in sequence. This output signal is sent from the shift register 26 to the capacitor C1 like the output signal of normal picture element photo diode, further being outputted through the buffer 27. FIG. 13 shows a portion relating the red color temperature detecting photo diode 14 corresponding to the reference part Ml as described above, and one end of the light-shielded picture element photo diode OPD second from the left end which is light-shielded by an aluminum film is formed longer than the other picture element photo diodes, being connected to the output end of the red color temperature detecting photo diode 14, and the output end of the yellow color temperature detecting photo diode 13 corresponding to the standard part M0 is connected to any one of five light-shielded picture element photo diodes of the right end side in FIG. 7 which is formed longer likewise.
The integration time control part 17 in FIG. 6 comprises a luminance judging circuit and an integration time control circuit, and in FIG. 14, these luminance control circuit 17a and integration time control circuit 17b are shown separately. Also, a signal processing timing generating part 6B as shown in FIG. 14 is contained in the data output control part 16 as shown in FIG. 16. The I/O control part 20 in FIG. 6 is dispersed in the signal processing timing generating part 16B, an integration time control circuit 17b and the transfer clock generating part 16A in FIG. 14. The system controller 53 first gives the basic clock CP to the photoelectric transducer 12. This basic clock CP is given to the transfer clock generating part 16A and the integration time control circuit 17b. The system controller 53 also gives the mode signals MD1 and MD2 to the photoelectric transducer 12. The mode signal is constituted with two bits, and can express four modes; initialize mode, low luminance integration mode, high luminance integration mode and data dump mode of the photoelectric transducer 12, being sent using two lines.
When the above-mentioned integration clear signal ICS disappears, the integration clear gate signal ICG, the barrier gate signal BG and the storage part clear gate signal STICG also disappear. As a result, the transistors Q2 and Q3 are turned off, and the capacitor C2 charged to the power supply voltage Vcc at initialization starts to drop the voltage in proportion to the generated charges of the monitoring photo diode MPD, and the capacitor C3 slightly drops the voltage responding to a small amount of generated charges of the light-shielded photo diode D1. Also, combined with that the signal PDS is given to the transistors Q4 and Q5, the capacitors C.sub.∝l and C5 drop the voltage from the power supply voltage Vcc at initialization responding to the amount of charges generated by the color temperature detecting photo diodes 13 and 14. On the other hand, the barrier gate 22 and the storage part clear gate 24 are turned off, and resultingly the picture element photo diodes PD start to generate and store photo charges in response to light irradiation, and the light-shielded photo diodes OPD start to store a small amount of dark output charges. Furthermore, the storage part 23 stores dark output charges generated by itself.
The luminance judging circuit 17a judges the state of integration from the monitor output signal AGCOS of the monitoring photo diode MPD and the monitor output correction signal AGCDOS, and when the value of integration reaches a predetermined value, the circuit generates a designating signal VFLG designating that state, gives it to the above-mentioned integration time control circuit 17b, and outputs the gain control signal AGC responding to the amount of shortage of the value of integration. The gain control signal AGC is supplied to an AGC subtracting circuit 71. The AGC subtracting circuit 71 compensates for gains of the picture element output signal OS and the color temperature detection output signals OSR and OSY to be inputted. As described later, the AGC subtracting circuit 71 has also a function of compensating for the dark output of the picture element output signal OS. The AGC data is supplied also to the system controller 53. This is performed to make it possible to judge on whether or not an auxiliary lighting (not illustrated) is required based on the AGC data by the system controller 53. FIG. 15 shows a specific configuration of the above-mentioned luminance judging circuit 17a. In FIG. 15, a block as shown by a dotted line 17a is the luminance judging circuit, and the other block shown by a dotted line is the AGC subtracting circuit 71. In the luminance judging circuit 17a, the monitor output compensating signal AGCDOS is applied to plus inputs (+) of operational amplifiers A1, A2, A3 and A4 through resistors R, 2R, 4R and 8R whose resistance values are in a relation of one time, two times, three times and four times. At this time, a constant current I flows through each resistor by a constant current source B, and therefore voltage drops by the resistors are in a relation of one time, two times, three times and four times respectively. The monitor output signal AGCOS is supplied to minus input terminals (-) of the operational amplifiers A1 -A4, and differential voltages between the signals AGCOS and AGCDOS are produced at the outputs thereof, but as shown in FIG. 7, since the capacitors C2 and C3, the transistors Q2 and Q3 and the buffers 28 and 31 are designed to be the same respectively on the same chip, the both signals AGCOS and AGCDOS have the same potential immediately after the integration clear gate signal ICG has been applied, and soon the monitor output signal AGCOS drops with generation of photo charges in the monitoring photo diodes MPD, while the monitor output compensating signal AGCDOS holds that state intact, holding the initial potential of the monitor output signal all the time. Accordingly, monitoring of the amount of storage of charges (value of integration) is made possible by taking out the difference between those signals. Also, variation in the power supply voltage can be cancelled by taking out the difference of the above-mentioned both signals, and further where the dark output increases by temperature rise, the light-shielded photo diode D1 responds thereto, and therefore the component of the dark output depending on temperature change is contained in the monitor output compensating signal AGCDOS, and the differential voltage between the above-mentioned both signals becomes a correct monitoring information signal wherein temperature effect is also eliminated. When the value of integration in the picture element photo diode PD is considered to have reached a predetermined value, the monitor output signal AGCOS from the monitoring photo diode MPD drops from the initial voltage by I�8R, and therefore a designating signal VFLG is generated from the operational amplifier A4. This designating signal VFLG is supplied to the integration time control circuit 17b. On receiving any one of the designating signal VFLG and a forced integration end signal SHM, the integration time control circuit 17b makes the photoelectric conversion part 15 perform integration completing operation, and generates a latch signal LCK, supplying this latch signal LCK to clock terminals CP of D flip-flops FF1 -FF3 of the above-mentioned luminance judging circuit 17a. The D flip-flops FF1 -FF3 are put in the latched state depending on the value of the monitor output signal AGCOS since the data terminals D are connected to the pre-stage operational amplifiers A1 -A3 Output ends of the respective D flip-flops FF1, FF2 and FF3 are connected to AND gates N1 and N.sub. 2 as illustrated, and resultingly the gain control signals AGC corresponding to the amounts of compensation of a proportion of one time, two times, four times and eight times are outputted to output paths 72, 73, 74 and 75 of the luminance judging circuit 17a. In this connection, under the state that the designating signal VFLG is outputted within a predetermined time controlled by the system controller 53, the signal AGC is generated on the output path 72.
The above-mentioned integration time control circuit 17b also generates the color temperature detection gate signal PDS which rises in synchronism with the barrier gate signal BG and falls in synchronism with the end of a second barrier gate signal. During the period corresponding to the integration clear gate signal ICG, this color temperature detection gate signal PDS puts the switching transistors Q4 and Q5 between the color temperature detecting photo diodes 13 and 14 and the capacitors C4 and C5 in the on-state to discharge the charges unnecessarily stored before then in the color temperature detecting photo diodes 13 and 14 to the capacitors C4 and C5, holds the high level even after the integration clear gate signal ICG has vanished to put the transistors Q4 and Q5 in the on-state, and makes the respective capacitors C4 and C5 store charges generated in the respective color temperature detecting photo diodes 13 and 14. Then, the designating signal VVLG is first generated, the storage part clear gate signal STICG is generated, and then the barrier gate signal BG is generated, and at the point of fall thereof the color temperature detection gate signal PDS falls, putting the above-mentioned transistors Q4 and Q5 in the off-state. Thereby, the integrating operations of charges generated in the respective color temperature detecting photo diodes 13 and 14 in the above-mentioned capacitors C4 and C5 are completed, and the potentials at this point of completion are held as the color temperature detection output signals OSR and OSY until the next start of integration.
Thus, the differences between the dark picture element output VOB sample-held and the picture element output signals Vos outputted eleventhly and after are taken out by the next-stage AGC subtracting circuit 71, and thereby the picture element output signal Vos by only the photo charge output with the dark output eliminated can be obtained. This subtraction is performed by the AGC subtracting circuit 71 as shown previously in FIG. 15. In FIG. 15, symbol A5 designates an operational amplifier taking the difference between the dark picture element output VOB inputted from a terminal 77 and the picture element output signal Vos inputted from a terminal 76. In addition, the amount of shortage of gain of the picture image output signal based on a forced stop of integration at low luminance is compensated by switching resistors r1, r2, r3 and r4 connected between the output end and the negative input terminal (-) of this operational amplifier A5 and resistors r5, r6, r7 and r8 connected between the reference voltage Vref and the positive input terminal (+) by the above-mentioned gain control signal AGC through analog switches S1 -S8. The signal passing through this AGC subtracting circuit 71 is outputted from the photoelectric transducer 12 to the system controller 53. For this purpose, the above-mentioned AGC subtracting circuit 71 is configurated in a manner that the output level is adjusted to the dynamic range (1/3Vref≦DR≦Vref) of the A/D conversion part 54 in the system controller 53, and the dark picture element output is set to Vref, and if the picture element output Vos is increased, an output of a form of Vref Vos can be taken out. This means that when the picture element output voltage Vos equal to the dark output voltage VOB inputted to the terminal 77 is inputted to the terminal 76, the output of the operational amplifier A5 becomes Vref, and when the input Vos becomes lower than VOB, the output of the operational amplifier A5 becomes Vref-Vos.
Next, FIG. 26(a) and FIG. 26(b) show a specific configuration of the transfer clock generating part 16A. Among them, FIG. 26(a) shows a portion forming the shift pulse SH, and FIG. 26(b) shows a portion generating the transfer clocks φ1 and φ2, the signals OSRST, RSS/H, OSS/H, ADS and the like. In FIG. 26(a), numeral 16a designates a first frequency divider dividing the frequency of the basic clock CP from the system controller 53, and the output of the first frequency divider 16a is further divided by a second frequency divider 16c reset by the output of a shift pulse forming part 16b forming the shift pulse SH by logic of SHM, ICS and TINT to generate signals QD0, QD1 and QD2. These outputs are decoded by a decoder part 16d in FIG. 26(b), and the clocks φ1 and φ2, OSRST and the like are formed through a circuit following the decoder part 16d.
Next, the system controller 53 sets the number of picture elements of taken-in data including the number of color temperature detecting photo diodes and the number of picture element output signals, performs A/D conversion of the analog signal Vos to be inputted, stores data in an inner memory every time an interrupt signal is generated by this completion, and repeats this procedure by the number set as mentioned above. Thus, digital signals corresponding to the respective images in the standard part M0 and the reference part M1 which are stored in the memory 55 are used for calculating an amount of defocus df1 by evaluating the image interval between the both parts M0 and M1 using correlative operation as disclosed by the present patent applicant in the Japanese Patent Laid-Open No. 247211/1985. After the calculation of df1, temperature compensation based on the output from the temperature detecting part 19 is also made. Then, symbol β is compensating coefficient of temperature of the camera itself, symbol SBT is temperature information, and symbol SBT0 is basic temperature information at 25� C. Next, the temperature compensated amount of defocus df0 is further compensated by the aberrations compensation data, especially by the chromatic aberration compensation data, and by the infrared chromatic aberration data if infrared light is used for auxiliary illumination, as disclosed in details in U.S. Pat. Nos. 4,511,232 and 4,560,267, respectively. Thus compensated amount of defocus is represented as dF0. The amount of defocus df0 undergoing this compensation is set so as to be a true value where the subject is illuminated by sun light. In the case where this amount of defocus df0 is larger than a predetermined value Tdf (=2-3 mm), the value of color temperature compensation is not so large (about 100-200 μm or less), and therefore the value of compensation itself has not large effect, and in the case where the compensated amount of defocus of the predetermined value Tdf or less is detected when lens drive is performed and remeasurement is made, a value of color temperature compensation Δdf is to be added. After the value of color temperature compensation Δdf has been added in such a manner, judgement of focusing condition is made, and when the result falls within a range of in-focus condition, display of infocus condition is performed, and when the judgement is made to be defocus condition, the photographing lens is shifted according to a lens shifting amount calculated by a product of the above-described coefficient KL and the detected amount of defocus which is the amount of defocus df0 added by the value of color temperature compensation Δdf, the integration mode is set, and then a routine consisting of a step of integration start by generation of ICS and the following steps is repeated.
Compensation of color temperature is made in such a manner, but as another method, necessity or non-necessity of compensation of color temperature is given as lens data responding to the kind of lens, and judgement on whether or not compensation of color temperature is to be made at first as shown in a flow in FIG. 25(b), and thereby when no compensation of color temperature is required, processing can be made faster without going through an extra flow. Also, FIG. 25(c) shows a flow wherein the amount of compensation for the value of R is determined continuously instead of determining the amount of compensation in a dispersed fashion as shown in FIG. 25(a) and (b). Here, the ratio has a possibility of showing infinity for the subject having single-short-wavelength component, while in an optical system, chromatic aberration has naturally a finite value a long as the light is visible one. To accommodate for this situation, in the case of R≦2.5, the value of R is limited to 2.5, and the amount of compensation thereof is determined by a product of color temperature of defocus the predetermined condition K1, and the value subtracted a standard value 1.5 from the ratio R.
Next, in the case where determination is made in a dispersed fashion as shown in FIG. 25(a), when individual lenses can have the value of amount of compensation Δdf, as shown in FIG. 25(d), the amount of compensation Δdf becomes df1 in the case of R≦1.8 and df2 in the case of R≦1.2 which are given to individual lens.
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