Source: https://patents.google.com/patent/US9870047B2/en
Timestamp: 2020-08-06 20:07:20
Document Index: 716353501

Matched Legal Cases: ['Application No. 201180073263', 'Application No. 2014', 'Application No. 2014', 'Application No. 2016', 'Application No. 2016', 'Application No. 2016', 'Application No. 2014', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 201180073263', 'Application No. 201180073263', 'Application No. 104137165', 'Application No. 105114441', 'Application No. 105118773', 'Application No. 101132336', 'Application No. 101132336']

US9870047B2 - Power efficient processor architecture - Google Patents
US9870047B2
US9870047B2 US15/192,134 US201615192134A US9870047B2 US 9870047 B2 US9870047 B2 US 9870047B2 US 201615192134 A US201615192134 A US 201615192134A US 9870047 B2 US9870047 B2 US 9870047B2
US15/192,134
US20160306415A1 (en
2013-06-07 Priority to US201313992361A priority
2016-04-21 Priority to US15/134,770 priority patent/US9864427B2/en
2016-06-24 Application filed by Intel Corp filed Critical Intel Corp
2016-06-24 Priority to US15/192,134 priority patent/US9870047B2/en
2016-10-20 Publication of US20160306415A1 publication Critical patent/US20160306415A1/en
2018-01-16 Publication of US9870047B2 publication Critical patent/US9870047B2/en
239000011162 core materials Substances 0.000 claims abstract description 406
Referring now to FIG. 1, shown is a block diagram of a processor in accordance with one embodiment of the present invention. As seen in FIG. 1, processor 100 may be a heterogeneous processor having a number of large cores, small cores and accelerators. Although described herein in the context of a multi-core processor, understand embodiments are not so limited and in implementations may be within a SoC or other semiconductor-based processing devices. Note that the accelerators can perform work whether the processor cores are powered up or not, based on a queue of input work. In the embodiment of FIG. 1, processor 100 includes a plurality of large cores. In the specific embodiment shown, two such cores 110 a and 110 b (generally, large cores 110) are shown, although understand that more than two such large cores may be provided. In various implementations, these large cores may be out-of-order processors having a relatively complex pipelined architecture and operating in accordance with a complex instruction set computing (CISC) architecture.
In addition, processor 100 further includes a plurality of small cores 120 a-120 n (generally, small cores 120). Although 8 such cores are shown in the embodiment of FIG. 1, understand the scope of the present invention is not limited in this aspect. In various embodiments, small cores 120 may be power efficient in-order processors, e.g., to execute instructions according to a CISC or a reduced instruction set computing (RISC) architecture. In some implementations, two or more of these cores may be coupled together in series to perform related processing, e.g., if several large cores are in power-saving states then one or more smaller cores may be active to perform work that would otherwise wake the large cores. In many embodiments, small cores 120 can be transparent to an OS, although in other embodiments the small and large cores may be exposed to the OS, with configuration options available. In general, any core mix between large and small cores can be used in different embodiments. For example, a single small core can be provided per large core, or in other embodiments a single small core may be associated with multiple large cores.
Still referring to FIG. 1, multiple accelerators 140 a-140 c also may be coupled to interconnect 130. Although the scope of the present invention is not limited in this regard, the accelerators may include media processors such as audio and/or video processors, cryptographic processors, fixed function units and so forth. These accelerators may be designed by the same designers that designed the cores, or can be independent third party intellectual property (IP) blocks incorporated into the processor. In general, dedicated processing tasks can be performed in these accelerators more efficiently than they can be performed on either the large cores or the small cores, whether in terms of performance or power consumption. Although shown with this particular implementation in the embodiment of FIG. 1, understand the scope of the present invention is not limited in this regard. For example, instead of having only two types of cores, namely a large core and a small core, other embodiments may have multiple hierarchies of cores, including at least a large core, a medium core and a small core, with the medium core having a larger chip real estate than the small core but a smaller chip real estate than the large core and corresponding power consumption between that of the large core and the small core. In still other embodiments, the small core can be embedded within a larger core, e.g., as a subset of the logic and structures of the larger core.
Furthermore, while shown in the embodiment of FIG. 1 as including multiple large cores and multiple small cores, it is possible that for certain implementations such as a mobile processor or SoC, only a single large core and a single small core may be provided. Specifically referring now to FIG. 2, shown is a block diagram of a processor in accordance with another embodiment of the present invention in which processor 100′ includes a single large core 110 and a single small core 120, along with interconnect 130 and accelerators 140 a-c. As mentioned, this implementation may be suitable for mobile applications.
Referring now to FIG. 6, shown is a block diagram of a processor in accordance with an embodiment of the present invention. As shown in FIG. 6, processor 400 may be a multicore processor including a first plurality of cores 410 1-410 n that can be exposed to an OS, and a second plurality of cores 410 a-x that are transparent to the OS.
As seen, the various cores may be coupled via an interconnect 415 to a system agent or uncore 420 that includes various components. As seen, the uncore 420 may include a shared cache 430 which may be a last level cache. In addition, the uncore may include an integrated memory controller 440, various interfaces 450 a-n, power control unit 455, and an advanced programmable interrupt controller (APIC) 465.
Referring now to FIG. 7, shown is a block diagram of a processor in accordance with another embodiment of the present invention. As shown in FIG. 7, processor 500 may be a true heterogeneous processor including a large core 510 and a small core 520. As seen, each processor may be associated with its own private cache memory hierarchy, namely cache memories 515 and 525 which may include both level 1 and level 2 cache memories. In turn, the cores may be coupled together via a ring interconnect 530. Multiple accelerators 540 a and 540 b and a LLC, namely an L3 cache 550 which may be a shared cache are also coupled to the ring interconnect. In this implementation, execution state between the two cores may be transferred via ring interconnect 530. As described above, the execution state of the large core 500 can be stored in cache 550 prior to entry into a given low power state. Then upon wakeup of small core 520, at least a subset of this execution state can be provided to the small core to ready the core for execution of an operation that triggered its wakeup. Thus in the embodiment of FIG. 7, the cores are loosely coupled via this ring interconnect. Although shown for ease of illustration with a single large core and a single small core, understand the scope of the present invention is not limited in this regard. Using an implementation such as that of FIG. 7, any state or communication to be exchanged can be handled either via the ring architecture (which may also be a bus or fabric architecture). Or, in other embodiments this communication may be via a dedicated bus between the two cores (not shown in FIG. 7).
Embodiments may be implemented in many different system types. Referring now to FIG. 11, shown is a block diagram of a system in accordance with an embodiment of the present invention. As shown in FIG. 11, multiprocessor system 600 is a point-to-point interconnect system, and includes a first processor 670 and a second processor 680 coupled via a point-to-point interconnect 650. As shown in FIG. 11, each of processors 670 and 680 may be multicore processors, including first and second processor cores (i.e., processor cores 674 a and 674 b and processor cores 684 a and 684 b), although potentially many more cores may be present in the processors. More specifically, each of the processors can include a mix of large, small (and possibly medium) cores, accelerators and so forth, in addition to logic to direct wakeups to the smallest available core, when at least the large cores are in a low power state, as described herein.
an interconnect coupled to the first plurality of cores and coupled to the second plurality of cores;
wherein, based at least in part on a performance requirement, an execution state is transferred from the core of the second plurality of cores to the core of the first plurality of cores to enable the core of the first plurality of cores to execute an operation; and
logic to cause the core of the first plurality of cores to execute the operation, wherein the logic is to cause the core of the second plurality of cores and not the core of the first plurality of cores to be woken in response to an interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state, analyze a plurality of interrupts and if a majority of the plurality of interrupts are to be handled by the core of the first plurality of cores, not wake the core of the second plurality of cores in response to the interrupt and instead wake the core of the first plurality of cores.
2. The processor of claim 1, wherein the logic is to cause the core of the first plurality of cores and not the core of the second plurality of cores to be woken in response to the interrupt when an entry of a table indicates that the core of the second plurality of cores incurred an undefined fault in response to a previous interrupt of the same type as the interrupt.
3. The processor of claim 1, further comprising an interrupt controller to receive a plurality of interrupts and direct the plurality of interrupts to one or more cores of at least one of the first plurality of cores and the second plurality of cores.
4. The processor of claim 1, wherein the execution state comprises a plurality of registers including general-purpose registers and configuration registers.
5. The processor of claim 1, wherein the execution state comprises a subset of an execution state of the core of the second plurality of cores.
6. The processor of claim 5, wherein in response to a determination that the core of the second plurality of cores cannot handle at least one requested operation, the subset of the execution state is to be merged with a remainder of the execution state of the core of the first plurality of cores.
causing a core of a second plurality of cores of a processor to execute an operation, the processor comprising a first plurality of cores, the second plurality of cores, an interconnect coupled to the first plurality of cores and coupled to the second plurality of cores, and a shared cache memory coupled to at least the first plurality of cores, the core of the second plurality of cores having a lower power consumption when in operation than a core of the first plurality of cores;
causing, based at least in part on a performance requirement, an execution state to be transferred from the core of the second plurality of cores to the core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation;
if a majority of the plurality of interrupts are to be handled by the first plurality of cores, waking the core of the first plurality of cores to handle an interrupt and not waking the core of the second plurality of cores.
8. The method of claim 7, further comprising causing the core of the second plurality of cores and not the core of the first plurality of cores to be woken in response to the interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state.
9. The method of claim 8, further comprising causing the core of the first plurality of cores and not the core of the second plurality of cores to be woken in response to the interrupt when an entry of a table indicates that the core of the second plurality of cores incurred an undefined fault in response to a previous interrupt of the same type as the interrupt.
10. At least one non-transitory computer readable storage medium comprising instructions that when executed enable a system to:
cause a core of a second plurality of cores of a processor to execute an operation, the processor comprising a first plurality of cores, the second plurality of cores, an interconnect coupled to the first plurality of cores and coupled to the second plurality of cores, and a shared cache memory coupled to at least the first plurality of cores, the core of the second plurality of cores having a lower power consumption when in operation than a core of the first plurality of cores;
cause, based at least in part on a performance requirement, an execution state to be transferred from the core of the second plurality of cores to the core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation;
11. The at least one non-transitory computer readable storage medium of claim 10, further comprising instructions that when executed enable the system to cause the core of the second plurality of cores and not the core of the first plurality of cores to be woken in response to the interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state.
12. The at least one non-transitory computer readable storage medium of claim 11, further comprising instructions that when executed enable the system to cause the core of the first plurality of cores and not the core of the second plurality of cores to be woken in response to the interrupt when an entry of a table indicates that the core of the second plurality of cores incurred an undefined fault in response to a previous interrupt of the same type as the interrupt.
US15/192,134 2011-09-06 2016-06-24 Power efficient processor architecture Active US9870047B2 (en)
US201313992361A true 2013-06-07 2013-06-07
US15/134,770 US9864427B2 (en) 2011-09-06 2016-04-21 Power efficient processor architecture
US15/192,134 US9870047B2 (en) 2011-09-06 2016-06-24 Power efficient processor architecture
US15/134,770 Continuation US9864427B2 (en) 2011-09-06 2016-04-21 Power efficient processor architecture
US20160306415A1 US20160306415A1 (en) 2016-10-20
US9870047B2 true US9870047B2 (en) 2018-01-16
US13/992,361 Active 2032-06-22 US9360927B2 (en) 2011-09-06 2011-09-06 Power efficient processor architecture
US15/134,770 Active US9864427B2 (en) 2011-09-06 2016-04-21 Power efficient processor architecture
US15/134,756 Active US10048743B2 (en) 2011-09-06 2016-04-21 Power efficient processor architecture
US15/192,134 Active US9870047B2 (en) 2011-09-06 2016-06-24 Power efficient processor architecture
US16/043,738 Active US10664039B2 (en) 2011-09-06 2018-07-24 Power efficient processor architecture
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