Source: https://patents.google.com/patent/US5736428A/en
Timestamp: 2018-11-17 22:55:47
Document Index: 593936070

Matched Legal Cases: ['art 8', 'arts 21', 'arts 21', 'arts 21', 'art 58', 'arts 43']

US5736428A - Process for manufacturing a semiconductor device having a stepped encapsulated package - Google Patents
Process for manufacturing a semiconductor device having a stepped encapsulated package Download PDF
US5736428A
US5736428A US08789661 US78966197A US5736428A US 5736428 A US5736428 A US 5736428A US 08789661 US08789661 US 08789661 US 78966197 A US78966197 A US 78966197A US 5736428 A US5736428 A US 5736428A
US08789661
Takashi Mashiko
Masao Sakuma
Yukio Saigo
Miyachi Systems Co Ltd
A process for manufacturing semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.
This application is a division of application Ser. No. 08/441,462, filed May 15, 1995, now U.S. Pat. No. 5,666,064, which is a division of application Ser. No. 07/961,161, filed Oct. 16, 1992 now U.S. Pat. No. 5,475,259.
The present invention generally relates to semiconductor devices, carriers for carrying semiconductor devices and methods of testing and producing semiconductor devices, and more particularly, to a resin encapsulated semiconductor device having a plurality of pins, a carrier for carrying such a semiconductor device and methods of testing and producing such a semiconductor device.
FIGS. 1(A) and 1(B) show an example of a conventional semiconductor device. FIG. 1(A) shows a plan view of this semiconductor device with a top part thereof omitted, and FIG. 1(B) shows a cross section of this semiconductor device along a line 1B--1B in FIG. 1(A).
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device, a carrier for carrying such a semiconductor device and methods of testing and producing such a semiconductor device, in which the problems described above are eliminated.
FIGS. 1(A) and 1(B) show an example of a conventional semiconductor device in a plan view and a cross sectional view for explaining the problems thereof;
FIG. 6 is a perspective view from the bottom showing a second embodiment of the semiconductor device according to the present invention;
FIGS. 7(A), 7(B) and 7(C) show a third embodiment of the semiconductor device according to the present invention in a side view, a bottom view and an enlarged bottom view in part;
FIGS. 10 through 13 are cross sectional views respectively showing fourth through seventh embodiments of the semiconductor device according to the present invention;
FIGS. 16(A) and 16(B) show a side view and a bottom view for explaining the mounting of the eighth embodiment of the semiconductor device;
FIG. 17 is a flow chart for explaining the production steps of the eighth embodiment of the semiconductor device;
FIGS. 28(A) and 28(B) show cross sectional views respectively along a line 28A--28A and a line 28B--28B in FIG. 27(A);
FIGS. 31(A), 31(B) and 31(C) are diagrams for explaining a general resin molding of the tape carrier;
FIGS. 32(A), 32(B) and 32(C) are diagrams for explaining a resin molding of the tape carrier shown in FIG. 30;
FIG. 39 is a perspective view showing the tenth embodiment of the semiconductor device with a radiator member removed;
FIGS. 42 through 45 are cross sectional views respectively showing modifications of the fourth through seventh embodiments of the semiconductor device shown in FIGS. 10 through 13.
A description will be given of a first embodiment of a semiconductor device according to the present invention, by referring to FIGS. 2(A) and 2(B). FIG. 2(A) shows a side view of the first embodiment in partial cross section, and FIG. 2(B) shows a bottom view of the first embodiment.
For example, the width of the outer lead 8 is 0.1 mm, the outer leads 8 are arranged at a pitch of 0.3 mm, and the difference between the sizes of the upper and lower resins 7a and 7b is 1.0 mm, as shown in FIG. 7(C). At the exposed part 8a within the 1.0 mm wide part of the upper resin 7a, the wide parts 21, respectively, having the size of 0.3×0.35 mm, are arranged in a zigzag or checker-board pattern. This arrangement of the wide parts 21 can easily be realized by forming the wide parts 21 in the process of forming the lead frame 2.
In the third embodiment of the semiconductor device shown in FIG. 7(A), the outer leads 8 have the approximate S-shape. However, the outer leads 8 may be shaped as shown in the modifications of FIGS. 5(A) and 5(B) described above. The effects obtained by such modifications are the same as those obtainable by the third embodiment of the semiconductor device.
Next, a description will be given of an eighth embodiment of the semiconductor device according to the present invention, by referring to FIGS. 14(A) and 14(B). FIG. 14(A) shows a plan view and FIG. 14(B) shows a side view of the eighth embodiment of the semiconductor device. In FIGS. 14(A) and 14(B), those parts which are the same as those corresponding parts in FIGS. 7(A)-7(C) are designated by the same reference numerals and a description thereof will be omitted.
FIGS. 18(A)-18(D) show an embodiment of the carrier according to the present invention which is used when transporting the third embodiment of the semiconductor device 1C described above. FIG. 18(A) shows a plan view of the carrier, FIG. 18(B) shows a bottom view of the carrier, FIG. 18(C) shows a cross sectional view of the carrier along a line 18C--18C in FIG. 18(A), and FIG. 18(D) shows a cross sectional view of the carrier along a line 18D--18D in FIG. 18(A).
FIGS. 19(A)-19(D) show the carrier 41 having the semiconductor device 1C inserted therein. FIG. 19(A) shows a plan view of the carrier, FIG. 19(B) shows a bottom view of the carrier, and FIGS. 19(C) and (D) show cross sectional views of the carrier respectively corresponding to FIGS. 18(C) and (D) described above.
On the other hand, a plurality of carriers 41 having the semiconductor device 1H inserted therein can be stacked as shown in FIGS. 20(A) and 20(B) when being transported, packed for forwarding or the like.
Tip ends 8b of the outer leads 8 are cut off at the part P5, and the semiconductor device 1C is inserted into the carrier at the part P6. The carrier 41 inserted with the semiconductor device 1C is stacked at the ejecting part 58 of the part P7.
FIG. 21(A) shows a case where a plurality of recesses 101 are formed in a tray 100. Each recess 101 has a shape and size slightly larger than those of the carrier 41. The carriers are independently accommodated within the respective recesses 101 of the tray 100.
The plating process shown in FIG. 22 is a final plating process which is carried out after a pre-plating process using Ag, Au, Pb or the like is carried out with respect to the lead frame 2 during the production process of the semiconductor device 1C. However, no plating is made on the cut surface which is formed when the tip ends 8b of the outer leads 8 are cut when this final plating process is carried out Hence, a pre-plating process may be carried out with respect to the cut surface, but such a pre-plating process is not essential. When the final plating process is carried out, the adherence of the plating material on the cut surface at the tip ends of the outer leads 8 is poorer than that of the other parts which have been subjected to the pre-plating process, however, the cut surface at the tip ends of the outer leads 8 help the generation of the solder fillet when mounting the semiconductor device 1C and no problems are caused thereby. For this reason, it is not essential to carry out the pre-plating process with respect to the cut surface of the tip ends of the outer leads 8.
FIG. 28(A) shows a cross section of the carrier 41A taken along a line 28A--28A in FIG. 27(A), and FIG. 28(B) shows a cross section of the carrier 41A taken along a line 28B--28B in FIG. 27(A).
As may be seen from FIGS. 27(A)-28(B), the carrier 41A does not have locking parts 43a through 43d of the carrier 41 shown in FIGS. 19(A)-19(D). Instead, the carrier 41A supports the semiconductor device 1C' by the pushing claws 44a through 44d alone. Hence, both the upper resin 7a and the lower resin 7b of the semiconductor device 1C' become exposed in the bottom view and the top view of the carrier 41A, respectively.
FIGS. 32(A)-32(C) are diagrams for explaining a resin molding of the tape carrier 91 shown in FIG. 30 according to this embodiment of the method of producing the semiconductor device. FIG. 32(A) is a plan view of a metal die which is used for the resin molding, FIG. 32(B) shows a cross section along a line 32B--32B in FIG. 32(A), and FIG. 32(C) shows a cross section along a line 32C--32C in FIG. 32(A).
FIGS. 33(A) and 33(B) are diagrams for explaining the gate shown in FIGS. 32(A)-32(C). FIG. 33(A) shows a plan view of the palette 121, and FIG. 33(B) shows a plan view of the lower metal die 120b. As shown in FIGS. 33(A) and 33(B), the lower runner 122b and the opening 123b of the palette 121 communicate at the upper gate 126, and the communication hole 127 of the lower runner 122b communicates to the lower gate 124 of the lower metal die 120b. It is of course possible to provide the runner 123 in only the palette 121 or in only the upper metal die 120a.
1. A method of producing a semiconductor device which comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a substantially rectangular package encapsulating at least the inner leads and the semiconductor chip, wherein the outer leads extend outwardly of the package, said package having an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts due to the different sizes, each of said outer leads having a part which is exposed at the stepped part of the package, said method comprising the steps of:
(a) placing the semiconductor device on a support, wherein the semiconductor device is supported by the stepped part and one of the upper and lower parts of the package having a smaller size; and
(b) plating a metal on the outer leads.
2. The method of producing the semiconductor device as claimed in claim 1, wherein said step (b) comprises carrying out one of electroplating and electroless plating of the metal on the outer leads.
3. The method of producing the semiconductor device as claimed in claim 1, wherein said step (a) comprises placing the semiconductor device on the support within a plating tank which is filled with a plating liquid so that the outer leads exposed at the stepped part make contact with a first electrode which forms the support, said first electrode being coupled to a second electrode which is within the plating tank via a power source, and said step (b) comprises carrying out an electroplating.
4. The method of producing the semiconductor device as claimed in claim 1, further comprising a step (c) of plating the outer leads prior to said steps (a) and (b).
5. The method of producing the semiconductor device as claimed in claim 1, further comprising a step (c) of carrying out a preplating process with respect to the outer leads prior to said steps (a) and (b).
6. The method of producing the semiconductor device as claimed in claim 1, further comprising a step (c) of accommodating the semiconductor device within a carrier when placing the semiconductor device on the support, said carrier comprising a sidewall part which has a hollow rectangular column shape which opens to a top and bottom thereof and locking parts provided on the sidewall part for locking at least corners of the stepped part of the semiconductor device which is accommodated within the sidewall part, said sidewall part surrounding sides of the semiconductor device to protect the outer leads.
7. The method of producing the semiconductor device as claimed in claim 6, wherein said step (a) comprises placing the carrier accommodating the semiconductor device on the support within a plating tank which is filled with a plating liquid, wherein the outer leads exposed at the stepped part make contact with a first electrode which forms the support, said first electrode being coupled to a second electrode which is within the plating tank via a power source, and said step (b) comprises carrying out an electroplating of the metal on the outer leads.
8. The method of producing the semiconductor device as claimed in claim 1, further comprising a step of (c) cutting off unnecessary parts of the outer leads prior to said steps (a) and (b).
US08789661 1991-10-17 1997-01-27 Process for manufacturing a semiconductor device having a stepped encapsulated package Expired - Fee Related US5736428A (en)
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US08789661 US5736428A (en) 1991-10-17 1997-01-27 Process for manufacturing a semiconductor device having a stepped encapsulated package
US08441462 Division US5666064A (en) 1991-10-17 1995-05-15 Semiconductor device, carrier for carrying semiconductor device, and method of testing and producing semiconductor device
US5736428A true US5736428A (en) 1998-04-07
ID=27458304
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