Source: http://www.google.ca/patents/US5436848
Timestamp: 2013-05-21 15:41:03
Document Index: 99848054

Matched Legal Cases: ['art.\n8', 'art.\n16', 'art.\n28', 'art.\n36', 'art.\n48', 'art.\n56', 'art 41', 'art 43', 'art 42', 'art 44', 'art 41', 'art 43', 'art 41', 'art 41', 'arts 41', 'arts 41', 'arts 41', 'arts 41', 'art 42', 'art 42', 'art 42', 'art 42', 'art 42', 'art 42', 'art 42', 'art 41', 'arts 41', 'art 42', 'arts 41', 'arts 41', 'art 41', 'art 41', 'arts 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'arts 41', 'art 42', 'art 44', 'art 13', 'art 44', 'art 42', 'art 13', 'art 41', 'art 43', 'art 43', 'art 13', 'art 13', 'art 13', 'art 13', 'art 13', 'art 13', 'art 42', 'art 41', 'art 41', 'art 42', 'art 42', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 13', 'art 41', 'art 43', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 41', 'art 43', 'art 42']

Patent US5436848 - Method of and device for transporting semiconductor substrate in ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Web History | Sign inAdvanced Patent SearchPatentsA robot (12) takes a wafer (3f) out of an indexer (1) and then transports the same to a heat processing part (41). A wafer (3e), which has already introduced in the heat processing part (41) is took out thereof by the robot (5). The wafer (3f) is introduced in the heat processing part (41) after a waiting...http://www.google.ca/patents/US5436848?utm_source=gb-gplus-sharePatent US5436848 - Method of and device for transporting semiconductor substrate in semiconductor processing systemPublication numberUS5436848 APublication typeGrantApplication number08/047,449Publication date25 Jul 1995Filing date15 Apr 1993Priority date3 Sep 1990InventorsTetsuya HamadaMasahiro HimotoMasami NishidaTakeo OkamotoNoriaki YokonoOriginal AssigneeDainippon Screen Mfg. Co., Ltd.U.S. Classification700/112700/121414/222.2International ClassificationH01L21/677H01L21/67H01L21/00Cooperative ClassificationH01L21/67745H01L21/67103European ClassificationH01L21/67S2H2H01L21/677B4ReferencesPatent Citations (3)Referenced by (71)External LinksUSPTOUSPTO AssignmentEspacenetMethod of and device for transporting semiconductor substrate in semiconductor processing systemUS 5436848 AAbstract A robot (12) takes a wafer (3f) out of an indexer (1) and then transports the same to a heat processing part (41). A wafer (3e), which has already introduced in the heat processing part (41) is took out thereof by the robot (5). The wafer (3f) is introduced in the heat processing part (41) after a waiting time (18a) so that an excess heat processing in the heat processing part (41) can be avoided. The wafer (3e) is transported to a processing part (43) and introduced therein by the robot (5). After the robot (5) repeats the similar processings in processing parts (13, 42, 44), it returns to the wafer transferring robot (12) to receive a next wafer. At that time, the robot (5) waits for a predetermined time thereby a cycle time is adjusted. After the waiting, the robot (5) takes out the wafer (3f), which has been introduced in the heat processing part (41), out thereof. Since the cycle time is set in common for different lots, the waiting times (18a, 18b) are set individually for each lot.
We claim: 1. A method of sequentially transporting semiconductor substrates with a transportation means in a system having first to N-th processing parts for applying predetermined processing to said semiconductor substrates, wherein said first to N-th processing parts have at least one heat processing part for applying heat to said semiconductor substrates and said semiconductor substrates are transported along a transportation path circulating said first to N-th processing parts, where the number N is an integer larger than one, said method comprising the steps of: (a) determining parameter values including: a single cycle time T.sub.0 common to the first to N-th processing parts and a waiting time T.sub.wj for each number j satisfying 1≦j≦N; and (b) serially transporting said semiconductor substrates to said first to N-th processing parts with said transporting means such that said transporting means repeatedly circulates along said processing path and a stream of said semiconductor substrates flows along said processing path via said first to N-th processing parts, comprising the steps of: (b-1) obtaining a state in which semiconductor substrates S.sub.j-i, S.sub.j and S.sub.j+1 having come from the (j-2)-th, (j-1)-th and j-th processing parts are present in the (j-1)-th, j-th and (j+1)-th processing parts, respectively; (b-2) transporting the semiconductor substrate S.sub.j-1 from the (j-1)-th processing part to the j-th processing part with said transporting means; (b-3) waiting before the j-th processing part until said cycle time T.sub.0 is past since said transporting means having taken the semiconductor substrate S.sub.j+1 out of the j-th processing part; (b-4) taking the semiconductor substrate S.sub.j out of the j-th processing part when said cycle time T.sub.0 is past; (b-5) waiting for said waiting time T.sub.wj ; (b-6) introducing said semiconductor substrate S.sub.j-1 into the j-th processing part when said waiting time T.sub.wj is past; (b-7) transporting the semiconductor substrate S.sub.j to the (j+1)-th with said transporting means; and (b-8) repeating the steps (b-1) to (b-7) for j=1, 2, . . . ,N, where: the (j-2)-th processing part for j=1 and 2; the (j-1)-th processing part for j=1; and the (j+1)-th processing part for j=N; represent a station for supplying said semiconductor substrate to said processing path and receiving said semiconductor substrates having been processed.
2. The method of claim 1, wherein; the step (a) comprises the steps of: (a-1) for each number j satisfying 1≦j≦N, determining a processing time T.sub.j representing how long said semiconductor substrates are to be processed in the j-th processing part; and (a-2) determining said cycle time T.sub.0 so that the following first condition (I) is satisfied for each number j satisfying 1≦j≦N: T.sub.0 &#8807;T.sub.j                                    (I)
3. The method of claim 2, wherein; the step (a) further comprises the steps of: (a-3) determining a transporting time T.sub.c which is a minimum time for said transporting means to circulate said transporting path; and (a-4) determining said cycle time T.sub.0 so that the following second condition (II) as well as said first condition are satisfied: T.sub.0 &#8807;T.sub.c                                    (II)
4. The method of claim 3, wherein; said semiconductor substrates are classified into a plurality of lots; and the step (a) further comprises the step of: (a-5) determining said waiting time t.sub.wj so that the following third condition (III) as well as said first and second conditions are satisfied: T.sub.0 &#8806;T.sub.c +S.sub.m                           (III) where the value S.sub.m is defined according to the following expression (E1): ##EQU4## and the number m is a positive integer designating an m-th lot of said semiconductor substrates.
5. The method of claim 4, wherein; the step (a-5) comprises the step of: (a-5-1) determining said waiting time T.sub.wj so that the following fourth condition (IV) as well as said first through third conditions are satisfied: T.sub.0 T.sub.c +T.sub.wj                                  (IV) where j=1, 2, . . . , N.
6. The method of claim 5, wherein; said plurality of lots include k lots of semiconductor substrates, where k is a positive integer larger than one; different sets of processing times T.sub.j for j=1, 2, . . . N are determined for said k lots of semiconductor substrates to obtain T.sub.1, T.sub.2, . . . T.sub.N2, where N2=K.N; and the step (a-5-1) comprises the step of: determining said cycle time T.sub.0 according to the following expression (E2): T.sub.0 =max (T.sub.1, T.sub.2, . . . ,T.sub.N2, T.sub.c)  (E2) where the symbol max represents the maximum value among the respective values of T.sub.1, T.sub.2, . . . ,T.sub.N2, and T.sub.c.
7. The method of claim 6, wherein; the step (a-5) further comprises the step of: (a-5-2) providing a non-zero value to said waiting time T.sub.wj only for said heat processing part.
8. The method of claim 7, wherein; the step (b) further comprises the step of: (b-9) waiting at said station until said cycle time T.sub.0 is past since said transporting means started said station last time.
9. A device for sequentially transporting semiconductor substrates in a system having first to N-th processing parts for applying predetermined processing to said semiconductor substrates, wherein said first to N-th processing parts have at least one heat processing part for applying heat to said semiconductor substrates and said semiconductor substrates are transported along a transportation path circulating said first to N-th processing parts, where the number N is an integer larger than one, said device comprising: (a) transportation means for transporting a semiconductor substrate along said processing path; (b ) means for holding parameter values including: a single cycle time T.sub.0 common to the first to N-th processing parts and a waiting time T.sub.wj for each number j satisfying 1≦j≦N; (c) control means for generating control signal as a function of said parameter values to deliver said control signal to said transportation means in order to serially transport said semiconductor substrates to said first to N-th processing parts such that said transporting means repeatedly circulates along said processing path and a stream of said semiconductor substrates flows along said processing path via said first to N-th processing parts, said control means comprising: (c-1) means for recognizing that said system is in a state in which semiconductor substrates S.sub.j-1, S.sub.j and S.sub.j+1 having come from the (j-2)-th, (j-1)-th and j-th processing parts are present in the (j-1)-th and (j+1)-th processing parts, respectively; (c-2) means for controlling said transporting means so as to transport a semiconductor substrate S.sub.j-1 from the (j-1)-th processing part to the j-th processing part; (c-3) means for controlling said transportation means so as to wait before the j-th processing part until said cycle time T.sub.0 is past since said transportation means having taken the semiconductor substrate S.sub.j+1 out of the j-th processing part; (c-4) means for controlling said transportation means so as to take the semiconductor substrate S.sub.j out of the j-th processing part when said cycle time T.sub.0 is past; (c-5) means for controlling said transportation means so as to wait for said waiting time T.sub.wj ; (c-6) means for controlling said transportation means so as to introduce said semiconductor substrate S.sub.j-1 into the j-th processing part when said waiting time T.sub.wj is past; (c-7) means for controlling said transportation means so as to transport the semiconductor substrate S.sub.j to the (j+1)-th processing part; and (c-8) means for serially enabling the means (c-1) to (c-7) for j-1, 2, . . . , N, where the (j-2)-th processing part for j=1 and 2; the (j-1)-th processing part for j=1; and the (j+1)-th processing part for j=N; represent a station for supplying said semiconductor substrate to said processing path and receiving said semiconductor substrates having been processed.
10. The device of claim 9, wherein; the means (b) comprises: (b-1) means for holding a processing time T.sub.j representing how long said semiconductor substrates are to be processed in the j-th processing part for each number j satisfying 1≦j≦N; and (b-2) means for accepting said cycle time T.sub.0 only when the following first condition (I) is satisfied for each number j satisfying 1≦j≦N: T.sub.0 &#8807;T.sub.j                                    (I)
11. The device of claim 10, wherein; the means (b) further comprises: (b-3) means for holding a transporting time T.sub.c which is a minimum time for said transporting means to circulate said transporting path; and (b-4) means for accepting said cycle time T.sub.0 only when the following second condition (II) as well as said first condition are satisfied: T.sub.0 &#8807;T.sub.c                                    (II)
12. The device of claim 11, wherein; said semiconductor substrates are classified into a plurality of lots; and the means (b) further comprises: (b-5) means for accepting said waiting time T.sub.wj only when the following third condition (III) as well as said first and second conditions are satisfied: T.sub.0 &#8807;T.sub.c &#8807;S.sub.m                    (III) where the value S.sub.m is defined according to the following expression (E1): ##EQU5## and the number m is a positive integer designating an m-th lot of said semiconductor substrates.
13. The device of claim 12, wherein; the means (b) further comprises: (b-6) means for accepting said waiting time T.sub.wj only when the following fourth condition (IV) as well as said first through third conditions are satisfied: T.sub.0 &#8807;T.sub.j +T.sub.wj                          (IV) where j=1, 2, . . . , N.
14. The device of claim 13, wherein; said plurality of lot include k lots of semiconductor substrates, where k is a positive integer larger than one; different sets of processing times T.sub.j for j=1, 2, . . . N are determined for said k lots of semiconductor substrates to obtain T.sub.1, T.sub.2, . . . T.sub.N2 where N2=k.N; and the means (b-6) further comprises: (b-7) means for accepting said cycle time T.sub.0 determined according to the following expression (E2): T.sub.0 -max (T.sub.1, T.sub.2, . . . ,T.sub.N2, T.sub.c)  (E2) where the symbol max represents the maximum value among the respective values of T.sub.1, T.sub.2, . . . ,T.sub.N2, and T.sub.c.
15. The device of claim 14, wherein; the means (b) further comprises: (b-8) means for accepting a non-zero value of said waiting time T.sub.wj only for said heat processing part.
16. The device of claim 15, wherein; the means (b) further comprises: (b-9) means for inputting a trial value for said cycle time T.sub.0 ; the means (b-2) comprises: (b-2-1) means for comparing said trial value for said cycle time T.sub.0 with said processing times T.sub.1, T.sub.2, . . . T.sub.N2 ; (b-2-2) means for employing said trial value for said cycle time T.sub.0 when the condition (I) is satisfied; and (b-2-3) means for inputting another trial value for said cycle time T.sub.0 when the condition (I) is not satisfied.
17. The device of claim 16, wherein; the means (b-4) comprises: (b-4-1) means for comparing said trial value for said cycle time T.sub.0 with said transporting time T.sub.c ; (b-4-2) means for employing said trial value for said cycle time T.sub.0 when the condition (II) as well as said condition (I) are satisfied; and (b-4-3) means for inputting another trail value for said cycle time T.sub.0 when the condition (II) is not satisfied.
18. The device of claim 17, wherein; the means (b) further comprises: (b-10) means for inputting respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 ; the means (b-5) comprises: (b-5-1) means for comparing said cycle time T.sub.0 with a sum of said transportation time T.sub.c and said respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 ; (b-5-2) means for employing said respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 as said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 when the condition (III) is satisfied; and (b-5-3) means for inputting other respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 when the condition (III) is not satisfied.
19. The device of claim 18, wherein; the means (b-6) comprises: (b-6-1) means for comparing said cycle time T.sub.0 with a sum of each of trail value for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 and said processing time T.sub.j ; (b-6-2) means for employing said respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 as said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 when the condition (IV) is satisfied; and (b-6-3) means for inputting other respective trial values for said waiting times T.sub.1, T.sub.2, . . . ,T.sub.N2 when the condition (IV) is not satisfied.
20. The device of claim 19, wherein; the step (c) further comprises the step of: (c-9) controlling said transporting means so as to wait at said station until said cycle time T.sub.0 is past since said transporting means started said station last time.
21. A method of sequentially transporting semiconductor substrates with a transportation means in a system having first to N-th processing parts for applying predetermined processing to said semiconductor substrates, wherein said first to N-th processing parts have at least one heat processing part for applying heat to said semiconductor substrates and said semiconductor substrates are transported along a transportation path circulating said first to N-th processing parts, where the number N is an integer larger than one, said method comprising the steps of: (a) determining parameter values including: a single cycle time T.sub.0 common to the first to N-th processing parts, a waiting time T.sub.wj and a processing time T.sub.j representing how long said semiconductor substrates are to be processed in the j-th processing part for each number j satisfying 1≦j≦N; and (b) serially transporting said semiconductor substrates to said first to N-th processing parts with said transporting means such that said transporting means repeatedly circulates along said processing path and a stream of said semiconductor substrates flows along said processing path via said first to N-th processing parts, comprising the steps of: (b-1) obtaining a state in which semiconductor substrates S.sub.j-i, S.sub.j and S.sub.j+1 having come from the (j-2)-th, (j-1)-th and j-th processing parts are present in the (j-1)-th, j-th and (j+1)-th processing parts, respectively; (b-2) transporting the semiconductor substrate S.sub.j-1 from the (j-1)-th processing part to the j-th processing part with said transporting means; (b-3) waiting before the j-th processing part until said processing time T.sub.j is past since said transporting means having introduced in the semiconductor substrate S.sub.j+1 into the j-th processing part; (b-4) taking the semiconductor substrate S.sub.j out of the j-th processing part when said processing time T.sub.j is past; (b-5) waiting for said waiting time T.sub.wj ; (b-6) introducing said semiconductor substrate S.sub.j-1 into the j-th processing part when said waiting time T.sub.wj is past; (b-7) transporting the semiconductor substrate S.sub.j to the (j+1)-th with said transporting means; and (b-8) repeating the steps (b-1) to (b-7) for j=1, 2, . . . ,N, where: the (j-2)-th processing part for j=1 and 2; the (j-1)-th processing part for j=1; and the (j+1)-th processing part for j=N; represent a station for supplying said semiconductor substrate to said processing path and receiving said semiconductor substrates having been processed.
22. The method of claim 21, wherein; the step (a) comprises the step of: (a-1) determining said cycle time T.sup.0 so that the following first condition (I) is satisfied for each number j satisfying 1≦j≦N: T.sub.0 &#8807;T.sub.j                                    (I)
23. The method of claim 22, wherein; the step (a) further comprises the steps of: (a-2) determining a transporting time T.sub.c which is a minimum time for said transporting means to circulate said transporting path; and (a-3) determining said cycle time T.sub.0 so that the following second condition (II) as well as said first condition are satisfied: T.sub.0 &#8807;T.sub.c                                    (II)
24. The method of claim 23, wherein; said semiconductor substrates are classified into a plurality of lots; and the step (a) further comprises the step of: (a-4) determining said waiting time t.sub.wj so that the following third condition (III) as well as said first and second conditions are satisfied: T.sub.0 &#8807;T.sub.c +S.sub.m                           (III) where the value S.sub.m is defined according to the following expression (E1): ##EQU6## and the number m is a positive integer designating an m-th lot of said semiconductor substrates.
25. The method of claim 24, wherein; the step (a-4) comprises the step of: (a-4-1) determining said waiting time T.sub.wj so that the following fourth condition (IV) as well as said first through third conditions are satisfied: T.sub.0 &#8807;T.sub.c +T.sub.wj                          (IV) where j=1, 2, . . . , N.
26. The method of claim 25, wherein; said plurality of lots include k lots of semiconductor substrates, where k is a positive integer larger than one; different sets of processing times T.sub.j for j=1, 2, . . . N are determined for said k lots of semiconductor substrates to obtain T.sub.1, T.sub.2, . . . T.sub.N2, where N2=K.N; and the step (a-4-1) comprises the step of: determining said cycle time T.sub.0 according to the following expression (E2): T.sub.0 =max (T.sub.1, T.sub.2, . . . ,T.sub.N2, T.sub.c)  (E2) where the symbol max represents the maximum value among the respective values of T.sub.1, T.sub.2, . . . ,T.sub.N2, and T.sub.c.
27. The method of claim 26, wherein; the step (a-4) further comprises the step of: (a-4-2) providing a non-zero value to said waiting time T.sub.wj only for said heat processing part.
28. The method of claim 27, wherein; the step (b) further comprises the step of: (b-9) waiting at said station until said cycle time T.sub.0 is past since said transporting means started said station last time.
29. A device for sequentially transporting semiconductor substrates in a system having first to N-th processing parts for applying predetermined processing to said semiconductor substrates, wherein said first to N-th processing parts have at least one heat processing part for applying heat to said semiconductor substrates and said semiconductor substrates are transported along a transportation path circulating said first to N-th processing parts, where the number N is an integer larger than one, said device comprising: (a) transportation means for transporting a semiconductor substrate along said processing path; (b) means for holding parameter values including: a single cycle time T.sub.0 common to the first to N-th processing parts, a waiting time T.sub.wj and a processing time T.sub.j representing how long said semiconductor substrates are to be processed in the j-th processing part for each number j satisfying 1≦j≦N; (c) control means for generating control signal as a function of said parameter values to deliver said control signal to said transportation means in order to serially transport said semiconductor substrates to said first to N-th processing parts such that said transporting means repeatedly circulates along said processing path and a stream of said semiconductor substrates flows along said processing path via said first to N-th processing parts, said control means comprising: (c-1) means for recognizing that said system is in a state in which semiconductor substrates S.sub.j-1, S.sub.j and S.sub.j+1 having come from the (j-2)-th, (j-1)-th and j-th processing parts are present in the (j-1)-th and (j+1)-th processing parts, respectively; (c-2) means for controlling said transporting means so as to transport a semiconductor substrate S.sub.j-1 from the (j-1)-th processing part to the j-th processing part; (c-3) means for controlling said transportation means so as to wait before the j-th processing part until said processing time T.sub.j is past since said transportation means having introduced the semiconductor substrate S.sub.j+1 into the j-th processing part; (c-4) means for controlling said transportation means so as to take the semiconductor substrate S.sub.j out of the j-th processing part when said processing time T.sub.j is past; (c-5) means for controlling said transportation means so as to wait for said waiting time T.sub.wj ; (c-6) means for controlling said transportation means so as to introduce said semiconductor substrate S.sub.j-1 into the j-th processing part when said waiting time T.sub.wj is past; (c-7) means for controlling said transportation means so as to transport the semiconductor substrate S.sub.j to the (j+1)-th; and (c-8) means for serially enabling the means (c-1) to (c-7) for j-1, 2, . . . , N, where the (j-2)-th processing part for j=1 and 2; the (j-1)-th processing part for j=1; and the (j+1)-th processing part for j=N; represent a station for supplying said semiconductor substrate to said processing path and receiving said semiconductor substrates having been processed.
30. The device of claim 29, wherein; the means (b) comprises: (b-1) means for accepting said cycle time T.sub.0 only when the folllowing first condition (I) is satisfied for each number j satisfying 1≦j≦N: T.sub.0 &#8807;T.sub.j                                    (I)
31. The device of claim 30, wherein; the means (b) further comprises: (b-2) means for holding a transporting time T.sub.c which is a minimum time for said transporting means to circulate said transporting path; and (b-3) means for accepting said cycle time T.sub.0 only when the following second condition (II) as well as said first condition are satisfied: T.sub.0 &#8807;T.sub.c                                    (II)
32. The device of claim 31, wherein; said semiconductor substrates are classified into a plurality of lots; and the means (b) further comprises: (b-4) means for accepting said waiting time T.sub.wj only when the following third condition (III) as well as said first and second conditions are satisfied: T.sub.0 &#8807;T.sub.c &#8807;S.sub.m                    (Ill) where the value S.sub.m is defined according to the following expression (E1): M.N S.sub.m =&#931; T.sub.wj                                  (E 1) j=(m-1).N+1 and the number m is a positive integer designating an m-th lot of said semiconductor substrates.
33. The device of claim 32, wherein; the means (b) further comprises: (b-5) means for accepting said waiting time T.sub.wj only when the following fourth condition (IV) as well as said first through third conditions are satisfied: T.sub.0 &#8807;T.sub.j +T.sub.wj                          (IV) where j=1, 2, . . . , N.
34. The device of claim 33, wherein; said plurality of lot include k lots of semiconductor substrates, where k is a positive integer larger than one; different sets of processing times T.sub.j for j=1, 2, . . . N are determined for said k lots of semiconductor substrates to obtain T.sub.1, T.sub.2, . . . T.sub.N2 where N2=k.N; and the means (b-5) further comprises: (b-6) means for accepting said cycle time T.sub.0 determined according to the following expression (E2): T.sub.0 -max (T.sub.1, T.sub.2, . . . ,T.sub.N2, T.sub.c)  (E2) where the symbol max represents the maximum value among the respective values of T.sub.1, T.sub.2, . . . ,T.sub.N2, and T.sub.c.
35. The device of claim 34, wherein; the means (b) further comprises: (b-7) means for accepting a non-zero value of said waiting time T.sub.wj only for said heat processing part.
36. The device of claim 35, wherein; the means (b) further comprises: (b-8) means for inputting a trial value for said cycle time T.sub.0 ; the means (b-1) comprises: (b-1-1) means for comparing said trial value for said cycle time T.sub.0 with said processing times T.sub.1, T.sub.2, . . . T.sub.N2 ; (b-1-2) means for employing said trial value for said cycle time T.sub.0 when the condition (I) is satisfied; and (b-1-3) means for inputting another trial value for said cycle time T.sub.0 when the condition (I) is not satisfied.
37. The device of claim 36, wherein; the means (b-3) comprises: (b-3-1) means for comparing said trial value for said cycle time T.sub.0 with said transporting time T.sub.c ; (b-3-2) means for employing said trial value for said cycle time T.sub.0 when the condition (II) as well as said condition (I) are satisfied; and (b-3-3) means for inputting another trail value for said cycle time T.sub.0 when, the condition (II) is not satisfied.
38. The device of claim 37, wherein; the means (b) further comprises: (b-9) means for inputting respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 ; the means (b-4) comprises: (b-4-1) means for comparing said cycle time T.sub.0 with a sum of said transportation time T.sub.c and said respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 ; (b-4-2) means for employing said respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 as said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 when the condition (III) is satisfied; and (b-4-3) means for inputting other respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 when the condition (III) is not satisfied.
39. The device of claim 38, wherein; the means (b-5) comprises: (b-5-1) means for comparing said cycle time T.sub.0 with a sum of each of trail value for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 and said processing time T.sub.j ; (b-5-2) means for employing said respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 as said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 when the condition (IV) is satisfied; and (b-5-3) means for inputting other respective trial values for said waiting times T.sub.1, T.sub.2, . . . ,T.sub.N2 when the condition (IV) is not satisfied.
40. The device of claim 39, wherein; the step (c) further comprises the step of: (c-9) controlling said transporting means so as to wait at said station until said cycle time T.sub.0 is past since said transporting means started said station last time.
41. A method of sequentially transporting semiconductor substrates with a transportation means in a system having first to N-th processing parts for applying predetermined processing to said semiconductor substrates, wherein said first to N-th processing parts have at least one heat processing part for applying heat to said semiconductor substrates and said semiconductor substrates are transported along a transportation path circulating said first to N-th processing parts, where the number N is an integer larger than one, said method comprising the steps of: (a) determining parameter values including: a single cycle time T.sub.0 common to the first to N-th processing parts, a waiting time T.sub.wj and a moving time T.sub.mj for each number j satisfying 1≦j≦N; and (b) serially transporting said semiconductor substrates to said first to N-th processing parts with said transporting means such that said transporting means repeatedly circulates along said processing path and a stream of said semiconductor substrates flows along said processing path via said first to N-th processing parts, comprising the steps of: (b-1) obtaining a state in which semiconductor substrates S.sub.j-1, S.sub.j and S.sub.j+1 having come from the (j-2)-th, (j-1)-th and j-th processing parts are present in the (j-1)-th, j-th and (j+1)-th processing parts, respectively; (b-2) transporting the semiconductor substrate S.sub.j-1 from the (j-1)-th processing part to the j-th processing part with said transporting means by said moving time T.sub.m(j-1) ; (b-3) taking the semiconductor substrate S.sub.j out of the j-th processing part when said transporting means reach the j-th processing part; (b-4) waiting for said waiting time T.sub.wj ; (b-5) introducing said semiconductor substrate S.sub.j-1 into the j-th processing part when said waiting time T.sub.wj is past; (b-6) transporting the semiconductor substrate S.sub.j to the (j+1)-th processing prart, with said transporting means by said moving time T.sub.mj ; and (b-7) repeating the steps (b-1) to (b-6) for j=1, 2, . . . ,N, where: the (j-2)-th processing part for j=1 and 2; the (j-1)-th processing part for j=1; and the (j+1)-th processing part for j=N; represent a station for supplying said semiconductor substrate to said processing path and receiving said semiconductor substrates having been processed.
42. The method of claim 41, wherein; the step (a) comprises the step of: (a-1) for each number j satisfying 1≦j≦N, determining a processing time T.sub.j representing how long said semiconductor substsrates are to be processed in the j-th processing part; and (a-2) determining said cycle time T.sup.0 so that the following first condition (I) is satisfied for each number j satisfying 1≦j≦N: T.sub.0 &#8807;T.sub.j                                    (I)
43. The method of claim 42, wherein; the step (a) further comprises the steps of: (a-3) determining a transporting time T.sub.c which is a minimum time for said transporting means to circulate said transporting path; and (a-4) determining said cycle time T.sub.0 so that the following second condition (II) as well as said first condition are satisfied: T.sub.0 &#8807;T.sub.c                                    (II)
44. The method of claim 43, wherein; said semiconductor substrates are classified into a plurality of lots; and the step (a) further comprises the step of: (a-4) determining said waiting time t.sub.wj so that the following third condition (III) as well as said first and second conditions are satisfied: T.sub.0 &#8807;T.sub.c +S.sub.m                           (III) where the value S.sub.m is defined according to the following expression (E1): ##EQU7## and the number m is a positive integer designating an m-th lot of said semiconductor substrates.
45. The method of claim 44, wherein; the step (a-5) comprises the step of: (a-5-1) determining said waiting time T.sub.wj so that the following fourth condition (IV) as well as said first through third conditions are satisfied: T.sub.0 &#8807;T.sub.c +T.sub.wj                          (IV) where j=1, 2, . . . , N.
46. The method of claim 45, wherein; said plurality of lots include k lots of semiconductor substrates, where k is a positive integer larger than one; different sets of processing times T.sub.j for j=1, 2, . . . N are determined for said k lots of semiconductor substrates to obtain T.sub.1, T.sub.2, . . . T.sub.N2, where N2=K.N; and the step (a-5-1) comprises the step of: determining said cycle time T.sub.0 according to the following expression (E2): T.sub.0 =max(T.sub.1, T.sub.2, . . . ,T.sub.N2, T.sub.c)   (E2) where the symbol max represents the maximum value among the respective values of T.sub.1, T.sub.2, . . . ,T.sub.N2, and T.sub.c.
47. The method of claim 46, wherein; the step (a-5) further comprises the step of: (a-5-2) providing a non-zero value to said waiting time T.sub.wj only for said heat processing part.
48. The method of claim 47, wherein; the step (b) further comprises the step of: (b-9) waiting at said station until said cycle time T.sub.0 is past since said transporting means started said station last time.
49. A device for sequentially transporting semiconductor substrates in a system having first to N-th processing parts for applying predetermined processing to said semiconductor substrates, wherein said first to N-th processing parts have at least one heat processing part for applying heat to said semiconductor substrates and said semiconductor substrates are transported along a transportation path circulating said first to N-th processing parts, where the number N is an integer larger than one, said device comprising: (a) transportation means for transporting a semiconductor substrate along said processing path by a moving time T.sub.mj when said transportation measns moves from j-th processing part for each number j satisfying 1≦j≦N; (b) means for holding parameter values including: a single cycle time T.sub.0 common to the first to N-th processing parts, a waiting time T.sub.wj and said moving time T.sub.mj for each number j satisfying 1≦j≦N; (c) control means for generating control signal as a function of said parameter values to deliver said control signal to said transportation means in order to serially transport said semiconductor substrates to said first to N-th processing parts such that said transporting means repeatedly circulates along said processing path and a stream of said semiconductor substrates flows along said processing path via said first to N-th processing parts, said control means comprising: (c-1) means for recognizing that said system is in a state in which semiconductor substrates S.sub.j-1, S.sub.j and S.sub.j+1 having come from the (j-2)-th, (j-1)-th and j-th processing parts are present in the (j-1)-th and (j+1)-th processing parts, respectively; (c-2) means for controlling said transporting means so as to transport a semiconductor substrate S.sub.j-1 from the (j-1)-th processing part to the j-th processing part, by said moving time T.sub.mj ; (c-3) means for controlling said transportation means so as to take the semiconductor substrate S.sub.j out of the j-th processing part when said transporting means reach the j-th processing part; (c-4) means for controlling said transportation means so as to wait for said waiting time T.sub.wj ; (c-5) means for controlling said transportation means so as to introduce said semiconductor substrate S.sub.j-1 into the j-th processing part when said waiting time T.sub.wj is past; (c-6) means for controlling said transportation means so as to transport the semiconductor substrate S.sub.j to the (j+1)-th processing part by said moving time T.sub.mj ; and (c-7) means for serially enabling the means (c-1) to (c-6) for j=1, 2, . . . N, where the (j-2)-th processing part for j=1 and 2; the (j-1)-th processing part for j=1; and the (j+1)-th processing part for j=N; represent a station for supplying said semiconductor substrate to said processing path and receiving said semiconductor substrates having been processed.
50. The device of claim 49, wherein; the means (b) comprises: (b-1) means for holding a processing time T.sub.j representing how long said seminconductor substrates are to be processed in the j-th processing part for each number j satisfying 1≦j≦N; and (b-2) means for accepting said cycle time T.sub.0 only when the following first condition (I) is satisfied for each number j satisfying 1≦j≦N: T.sub.0 &#8807;T.sub.j                                    (I)
51. The device of claim 50, wherein; the means (b) further comprises: (b-3) means for holding a transporting time T.sub.c which is a minimum time for said transporting means to circulate said transporting path; and (b-4) means for accepting said cycle time T.sub.0 only when the following second condition (II) as well as said first condition are satisfied: T.sub.0 &#8807;T.sub.c                                    (II)
52. The device of claim 51, wherein; said semiconductor substrates are classified into a plurality of lots; and the means (b) further comprises: (b-5) means for accepting said waiting time T.sub.wj only when the following third condition (III) as well as said first and second conditions are satisfied: T.sub.0 &#8807;T.sub.c &#8807;S.sub.m                    (III) where the value S.sub.m is defined according to the following expression (E1): ##EQU8## and the number m is a positive integer designating an m-th lot of said semiconductor substrates.
53. The device of claim 52, wherein; the means (b) further comprises: (b-6) means for accepting said waiting time T.sub.wj only when the following fourth condition (IV) as well as said first through third conditions are satisfied: T.sub.0 &#8807;T.sub.j +T.sub.wj                          (IV) where j=1, 2, . . . , N.
54. The device of claim 53, wherein; said plurality of lot include k lots of semiconductor substrates, where k is a positive integer larger than one; different sets of processing times T.sub.j for j=1, 2, . . . N are determined for said k lots of semiconductor substrates to obtain T.sub.1, T.sub.2, . . . T.sub.N2 where N2=k.N; and the means (b-6) further comprises: (b-7) means for accepting said cycle time T.sub.0 determined according to the following expression (E2): T.sub.0 -max (T.sub.1, T.sub.2, . . . ,T.sub.N2, T.sub.c)  (E2) where the symbol max represents the maximum value among the respective values of T.sub.1, T.sub.2, . . . ,T.sub.N2, and T.sub.c.
55. The device of claim 54, wherein; the means (b) further comprises: (b-8) means for accepting a non-zero value of said waiting time T.sub.wj only for said heat processing part.
56. The device of claim 55, wherein; the means (b) further comprises: (b-8) means for inputting a trial value for said cycle time T.sub.0 ; the means (b-2) comprises: (b-2-1) means for comparing said trial value for said cycle time T.sub.0 with said processing times T.sub.1, T.sub.2, . . . T.sub.N2 ; (b-2-2) means for employing said trial value for said cycle time T.sub.0 when the condition (I) is satisfied; and (b-2-3) means for inputting another trial value for said cycle time T.sub.0 when the condition (I) is not satisfied.
57. The device of claim 56, wherein; the means (b-4) comprises: (b-4-1) means for comparing said trial value for said cycle time T.sub.0 with said transporting time T.sub.c ; (b-4-2) means for employing said trial value for said cycle time T.sub.0 when the condition (II) as well as said condition (I) are satisfied; and (b-4-3) means for inputting another trail value for said cycle time T.sub.0 when the condition (II) is not satisfied.
58. The device of claim 57, wherein; the means (b) further comprises: (b-9) means for inputting respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 ; the means (b-5) comprises: (b-5-1) means for comparing said cycle time T.sub.0 with a sum of said transportation time T.sub.c and said respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 ; (b-5-2) means for employing said respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 as said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 when the condition (III) is satisfied; and (b-5-3) means for inputting other respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 when the condition (III) is not satisfied.
59. The device of claim 58, wherein; the means (b-6) comprises: (b-6-1) means for comparing said cycle time T.sub.0 with a sum of each of trail value for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 and said processing time T.sub.j ; (b-6-2) means for employing said respective trial values for said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 as said waiting times T.sub.1, T.sub.2, . . . T.sub.N2 when the condition (IV) is satisfied; and (b-6-3) means for inputting other respective trial values for said waiting times T.sub.1, T.sub.2, . . . ,T.sub.N2 when the condition (IV) is not satisfied.
60. The device of claim 59, wherein; the step (c) further comprises the step of: (c-9) controlling said transporting means so as to wait at said station until said cycle time T.sub.0 is past since said transporting means started said station last time.
FIELD OF THE INVENTION Method of and Device for Transporting Semiconductor Substrate in Semiconductor Processing System.
BACKGROUND OF THE INVENTION The present invention relates to a method of and a, device for transporting a semiconductor substrate in a semiconductor processing system, and more particularly, it relates to an improved timing control in a semiconductor processing system wherein a transportation mechanism circulates through a plurality of substrate processing parts including a heat processing part in a predetermined order to thereby sequentially transport a plurality of semiconductor substrates to these processing parts.
DESCRIPTION OF THE PRIOR ART Heat processings or thermal treatment for semiconductor substrates are extremely important in the fabrication of semiconductor devices. For example, in a photolithography technology, which is required to diffuse an impurity into a semiconductor as well as to make patterns for circuits into a desired configuration, heat processings for photoresists have a great influence on a patterning accuracy.
The operation of the heat processor will be described now. The moving mechanism 8 moves and rotates the robot 5 as shown by arrows R and Q, respectively, so that the robot 5 travels on the stage 6. The arms 71 and 72 can be stretched and withdrawn so that the arms 71 and 72 can take the wafer 3 in and out of a place which is distant from the robot 5. Through this operation of the robot 5 for transporting the wafers 3, each wafer 3 stored in the cassettes 2 are taken out of the cassette 2 one after another, and circulates through the heat processing part 41, the cool processing part 43, the heat processing part 42 and the cool processing part 44, in that order. Each of the wafers 3 is subjected to predetermined heat processing or cool processing in these processing parts, and then, is stored in its home cassette 2 again. For the purpose of conducting a series of the processing in short time on a large number of wafers, the wafers 3 are transported in a sequential way in which a step of taking out one wafer from one processing part is conducted in connection with a step of introducing a next wafer into the processing part. For example, when one wafer which has been subjected to the heat processing in the heat processing part 41 is transported to the cool processing part 43, another wafer which is next to be processed in the heat processing part 41 is introduced in the heat processing part 41. Accordingly, each wafer is sequentially subjected to the respective processings in the processing parts 41 to 44, in that order. From a different point of view, the processing parts 41 to 44 conduct the respective processings in parallel at the same time on the wafers which are contained therein, respectively. FIG. 13B conceptually shows a flow of these processings and transportations. The robot 5 repeats transportation steps F.sub.1 to F.sub.5, in that order.
In a steady state in which a stream of wafers 3 are flowing through all the processing parts 41, 42, 43 and 44, the rate of circulating the robot 5 for transporting the wafers 3 along the processing parts 41, 42, 43 and 44 is limited to value depending on the heat processing time in the heat processing part 42. This is because the heat processing in the heat processing part 42 requires the longest processing time of 70 seconds among respective processing times. For example, supposed is a time point at which the robot 5 holding a wafer reaches the processing part 42. In this time point, the process in the processing part 42 for a prior wafer has not been completed and it is impossible to take out the prior wafer to introduce the new wafer into the part 42. Accordingly, the robot 5 must wait the completion of the process of 70 seconds in the part 42 for the prior wafer and cannot enter the following transportation processes F.sub.4, F.sub.5, F.sub.1, F.sub.2 and F.sub.3. Therefore, the exchange of the wafers in the part 42 and the transportation F.sub.4 with the robot 5 can be started only after at least 70 seconds has passed from the time point at which the transportation step F.sub.4 has started last time. That is, it takes at least 70 seconds for the robot 5 to make a round of the transportation route. As to the heat processing part 41 which requires the processing time of 60 seconds, for example, at least 70 seconds has past when the robot 5 returns thereto since the robot 5 left there last time. The time required for the transportation operation of the robot 5 is 8 seconds for limitating the rate of rounding the process path. Accordingly, during the stream of the wafers are flowing through all the processing parts 41, 42, 43 and 44, the wafer 3 in one processing part always is transported to the next processing part at intervals of at least 70 seconds which is required for completion of the heat processing in the heat processing part 42. Therefore, the wafers 3 stay in each of the processing parts 41 to 44 for about 70 seconds, regardless of the original processing times which are required for the respective proceessings in the processing parts 41 to 44.
This will be explained, referring to FIGS. 15(a) and 15(b). FIG. 15(a) is a graph illustrating an ideal temperature curve in the heat processing part 41 and indicates that the heat processing therein should be conducted at a temperature of 100 15(b) is a graph illustrating an actual temperature curve in the heat processing part 41 when the wafer 3 moves through the processing parts 41, 43, 42 and 44, in that order. Even if the wafer 3 is separated from the hot plate 9 after 60 seconds has passed, excess heat represented by a hatched portion in FIG. 15(b) is applied to the wafer 3. Therefore, it is difficult to obtain an actual temperature curve approximating the ideal temperature curve only by separating the wafer 3 from the hot plate 9 after the required heat processing in the heat processing part 41 is completed.
SUMMARY OF THE INVENTION The present invention is directed to a method of sequentially transporting semiconductor substrates with a transportation means in a system having first to N-th processing parts for applying predetermined processings to the semiconductor substrates.
According to the present invention, the method comprises the steps of: (a) determining parameter values including a single cycle time T.sub.0 common to the first to N-th processing parts and a waiting time T.sub.wj for each number j satisfying 1≦j≦N; and, (b) serially transporting the semiconductor substrates to the first to N-th processing parts with the transporting means such that the transporting means repeatedly circulates along the processing path and a stream of the semiconductor substrates flows along the processing path via the first to N-th processing parts.
In order to avoid excess heat on semiconductor substrates, obtained is a state in which semiconductor substrates S.sub.j-1, S.sub.j and S.sub.j+1 having come from the (j-2)-th, (j-1)-th and j-th processing parts are present in the (j-1)-th, j-th and (j+1)-th processing parts, respectively.
Then, the semiconductor substrate S.sub.j-1 from the (j-1)-th processing part is transported to the j-th processing part with the transporting means. The transportation mean waits before the j-th processing part until the cycle time T.sub.0 is past since the transporting means having taken the semiconductor substrate S.sub.j+1 out of the j-th processing part.
The transportation means takes the semiconductor substrate S.sub.j out of the j-th processing part when the cycle time T.sub.0 is past, and further waiting for the waiting time T.sub.wj.
Then, the transportation means introduces the semiconductor substrate S.sub.j-1 into the j-th processing part when the waiting time T.sub.wj is past, and transports the semiconductor substrate S.sub.j to the (j+1)-th with the transporting means.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a system for processing semiconductor substrates according to a preferred embodiment of the present invention;
DESCRIPTION OF THE PREFERRED EMBODIMENTS A. Mechanical Structure FIG. 1 is a perspective view showing a system 100 for processing semiconductor substrates according to a preferred embodiment of the present invention.
B. Content of Process Sequence A transportation route of the wafer will be now schematically explained, referring to FIGS. 1, 3(a) and 3(b). A wafer 3f (see FIG. 3(a)) in the cassette 2, which has been in a waiting state for being processed, is put on the arm 71, for example, of the robot 5 via the transferring robot 12. The robot 5 moves to the heat processing part 41 by means of a moving mechanism 8 so that the arm 72 takes out a wafer 3e which has been processed in the processing part 41. The heat processing part 41 is emptied by this operation, whereby the arm 71 introduces the wafer 3f into the processing part 41.
C. Analysis of Transportation Timing (Prior Art) Before a control flow of the system 100 having the above-described transportation route in accordance with the preferred embodiment of the present invention is described, the problems which are liable to occur when a conventional method is applied to transportation of wafers will be analyzed, referring to a transportation diagram shown in FIG. 4. This analysis will make clear features of the method according to the preferred embodiment of the present invention. The symbols IND, HP.sub.1, CP.sub.1, C, HP.sub.2 and CP.sub.2 shown in the left-hand side of FIG. 4 represent the respective processings conducted in the indexer 1, the processing parts 41, 43, 13, 42 and 44, respectively. Void arrows 16a-16h represent respective flows of the processings conducted on the corresponding wafers. The arrows also indicate passage of time that is, FIG. 4 shows that time passes from the left-hand side to the right-hand side. A dashed line 17 represents the movement of the transporting robot 5. For example, the void arrow 16b represents the sequence of the processings conducted on the wafer 3b which has been already subjected to the processings IND, HP.sub.1, CP.sub.1 and C, in that order. The wafer 3b is subjected to the processing HP.sub.2 and then, the wafer 3b is taken out of the processing part 42 and is transported to the processing part 44 to be introduced therein by the robot 5 which comes from the processing part 13 wherein the processing C is conducted. After the wafer 3b is subjected to the processing CP.sub.2 in the processing part 44, it is transported to the indexer 1 by the robot 5 which comes from the processing part 42, wherein the processing HP.sub.2 is conducted, so that the wafer 3b is subjected to the processing IND. The processing IND is a storage processing conducted by the transferring robot 12, by which the wafer 3b is stored in the cassette 2. Similarly, a void arrow 16f represents the processings conducted on the wafer 3f. As represented by the arrow 16f, the wafer 3f is taken out of the cassette 2, is subjected to the processings HP.sub.1 and CP.sub.1, in that order, and is transported to the processing part 13 wherein the processing C is conducted.
Transportation time required for the transportation operation of the robot 5 includes the time necessary to take a wafer out of each processing part as well as the time necessary to take another wafer therein. FIG. 5 conceptually illustrates the transportation time. In FIG. 5, the symbol P.sub.i represents each of the processings IND, HP.sub.1, CP.sub.1, C, HP.sub.2 and CP.sub.2. The symbol P.sub.i-1 represents a processing preceding the processing P.sub.i, while the other symbol P.sub.i+1 represents a processing following the processing P.sub.i. The transportation time between the processings P.sub.i and P.sub.i+1 is the sum of a time T.sub.in required for the arm 71 or 72 to take a wafer in a processing part in which the P.sub.i processing is conducted, a time T.sub.move required for the moving mechanism 8 to move the robot 5 between two processing parts and a time T.sub.out required for the arm 71 or 72 to take another wafer out from the processing part wherein the processing P.sub.i+1 is conducted.
the time T.sub.in required for the arm 71 or 72 to introduce the wafer 3e, which has been contained in the processing part 41, into the processing part 43;
the time T.sub.move required for the robot 5 to move from the processing part 43 to the processing part 13; and
the time T.sub.out required for the arm 71 or 72 to take the wafer 3c, which has been contained in the processing part 13, out of the processing part 13.
The times T.sub.in, T.sub.move and T.sub.out are 2 seconds, 4 seconds, and 2 seconds, respectively, and therefore, the transportation time is 2+4+2=8 seconds. After the wafer 3c is taken out of the processing part 13, the wafer 3d is took in the processing part 13 by the arm 72 or 71. The time required for this operation by the arm 72 or 71 is included in the transportation time between the processing part 13 and the processing part 42.
Similarly to FIG. 3(b), FIG. 6 schematically illustrates the transportation route of wafers. Every transportation equally requires 8 seconds. The processing times required for the processings HP.sub.1, CP.sub.1, C, HP.sub.2, and CP.sub.2 are 60 seconds, 45 seconds, 50 seconds, 70 seconds and 45 seconds, respectively. The total transportation time is 8 seconds time, i.e., 70 seconds for the HP.sub.2 processing, determines the rate of the cyclic flow of the processings.
Referring to FIG. 4 again, it can be seen from the arrow 16f which represents the flow of the wafer 3f that when the robot 5 reaches the processing part 41 as represented by the dashed line 17, t.sub.3 =10 seconds has already past since the processing HP.sub.1 of 60 seconds in the processing part 41 had been completed. The wafer 3f is thus overheated for t.sub.3 =10 seconds. This is due to the processing HP.sub.2. As shown by the arrow 16c, the processing Hp.sub.2 is necessary to be conducted on the wafer 3c for t.sub.1 =70 seconds. Therefore, the time when the robot 5 leaves the indexer 1 for the processing part 42 is appropriately adjusted so that the robot 5 reaches the processing part 42 exactly when the required processing time t.sub.1 =70 seconds has past since it left the indexer 1. The robot 5 has to wait for 70 seconds--(8 seconds the processing part 41 ten (t3=10) seconds later after the processing of 60 seconds in the processing part 41 is completed.
The robot 5 is not necessary to wait for 22 seconds at the indexer IND. However, as long as the transportation procedure shown in FIG. 6 is followed, the processing time required for the processing HP.sub.2, i.e., 70 seconds, determines the rate of the cyclic procedure, and therefore, it is necessary to provide a waiting time of 22 seconds somewhere.
The delay times are represented by dotted portions in FIG. 4. Among these delay times, particularly the delay time t.sub.3 in the processing Hp.sub.1 brings the most significant problem. This is because, as was already described above in reference to FIG. 15, an excess heat processing causes a harmful effect on patterning accuracy of a photoresist.
Furthermore, when plural lots of wafers are continuously processed and different processing times are required in respective lots, the delay time t.sub.3 itself varies within each lot. For example, supposed is the case where the wafers 3a, 3b and 3c are included in a lot requiring 70 seconds in the processing HP.sub.2 and the wafers 3d, 3e, 3f, . . . are included in another lot requiring 65 seconds in the processing HP.sub.2. The arrow 16d represents the flow of the processings conducted on the wafer 3d, which is the first wafer in the latter lot which is to be subjected to the processing HP.sub.2 for t.sub.2 =65 seconds.
In order to conduct the processing HP.sub.2 on the wafer 3d for 65 seconds, the waiting time of the robot 5 at the indexer 1 becomes five-seconds=(70-65 seconds) shorter than the last waiting time, i.e, 22 seconds. That is, the robot 5 waits at the indexer 1 for 17 seconds before it moves to the processing part 41. Therefore, the robot 5 arrives at the processing part 41 to take the wafer 3g 65 seconds after the robot 5 left there last time. The delay time t.sub.3 in the processing HP.sub.1 is now reduced to t.sub.3 ' by 5 seconds in accordance with the reduction in the processing HP.sub.2 by 70-65=5 seconds. This reduction in the delay time t.sub.3 to t.sub.3 ' affects only the wafer 3g and the wafers following the wafer 3g among the chain of wafers 3d, 3e, 3f, 3g, . . . which belong to the same lot. The wafers 3d, 3e and 3f have been already processed in the processing HP.sub.1 when the reduction in the delay time t.sub.3 is caused, and the reduction in the delay time does not affect the processing HP.sub.1 on the wafers 3d, 3e and 3f. As a result, the wafers 3d, 3e and. 3f are subjected to heat processing HP.sub.1 through a temperature curve different from other wafers 3g, . . . In the case where first and second lots are provided and twenty five wafers are contained in each lot, the leading three wafers in the second lot are subjected to the heat processing by the longer time than the following twenty two wafers. As a result, important control parameters such as critical exposure or the like vary within each lot, which brings a serious problem.
The same problem is caused also in the first lot. Since no lots are present prior to the first lot, the processings HP.sub.2 and CP.sub.2 are not started yet during the time leading three wafers in the first lot are sequentially subjected to the processing HP.sub.1. Thus, the cyclic processings in this initial time period are imperfect ones excluding the processings HP.sub.2 and CP.sub.2, so that the rate of the cyclic processings is determined as a function of the processing HP.sub.1 rather than the processings HP.sub.2. Accordingly, the robot 5 can come back to the processing part 41 at a desired time, that is, 60 seconds after the processing HP started in the part 41. When the HP.sub.2 processing is started in response to delivery of the fourth wafer to the processing path, the rate of the cyclic processings comes to depend on the processing HP.sub.2 which requires the longest processing time of 70 seconds. Thus, only the first three wafers, among wafers contained in the same lot, do not receive an excess heat processing. These three wafers therefore are subjected to the heat processing through a different temperature curve from the other twenty-two wafers even though they both are contained in the same lot.
D. Control Flow (Preferred Embodiment) These undesirable results described above can be avoided by:
(2) delaying the starting time of the processing HP.sub.1 by a time corresponding to the time t.sub.3 or t.sub.3 ' so that the processing HP.sub.1 is terminated just when the robot 5 returns to the processing part 41.
According to the preferred embodiment of the present invention, the robot 5 holding a wafer is controlled to wait for a time corresponding to the time t.sub.3 or t.sub.3 ' just before the processing part 41, and then to introduce the wafer into the processing part 41 for the processing HP.sub.1.
Each of the respective processing times in these processing parts corresponds to the time which passes from when a wafer is introduced in the objective processing part until when the wafer is taken out thereof. Each of the processing times therefore includes a taking-in time T.sub.in of a wafer as well as a taking-out time T.sub.out of a wafer. In other words, the taking-in time T.sub.in and the taking-out time T.sub.out constitute a part of the transportation time of the robot 5 as shown in FIG. 5, while they are also a part of the processing time of each processing part. The processing time of each processing part consists of these times T.sub.in and T.sub.out and the net processing time for substantially conducting the net processing. For example, the processing time in the processing part 13 for photoresist-coating consists of the times T.sub.in and T.sub.out and the next time for applying a photoresist to a wafer.
More details of the step 102 are now described, referring to FIG. 8. A value designating the cycle time T.sub.0 is inputted through the keyboard 19 in the step 104. Previously, the restriction of the cycle time T.sub.0 according to other parameters may be shown in the step 101 to help inputting the cycle time T.sub.0. In the next step 105, the cycle time T.sub.o is compared with a circulation time T.sub.c of the robot 5. The circulation time T.sub.c is the time required for the robot 5 to circulate the processing path or loop and is calculated as:
T.sub.c =N.sub.1 where N.sub.1 is the total number of the processing parts and is "5" in the example shown in the Table 2.
Further, the cycle time T.sub.0 is compared with each of the processing times T.sub.j (j=1 to N.sub.2) designated for respective processing parts with respect to different sets of processing times, where N.sub.2 is defined as:
N.sub.2 =k
and k is a positive integer representing the number of different sets of processing times. In the example shown in Table 2, the number of the processing parts N.sub.1 is five and there are two different sets of processing times. The first set of processing times (T.sub.1, T.sub.2, . . . T.sub.5) are for the first lot of wafers and the second set of processing times (T.sub.6, T.sub.7, . . . T.sub.10) are for the second lot of wafers. Thus, obtained are:
N.sub.2 =2
The following processings are conducted only when the tract time T.sub.0 is equal to or longer than the respective values of T.sub.j (j=1 to N.sub.2) and T.sub.c, i.e.,
T.sub.0 &#8807;T.sub.c and T.sub.0 &#8807;T.sub.j (j=1 to N.sub.2) (6)
When the cycle time T.sub.0 is shorter than the circulation time T.sub.c =N.sub.1 impossible to provide a finite waiting time for introduction because there is no additional time for the robot 5 to spare before introducing a wafer into a processing part. When an inadequate cycle time T.sub.0 not satisfying the condition (6) is inputted, a warning is displayed on the display 14 and a new value designating a new cycle time T.sub.0 is inputted. The new cycle time should be longer than the old cycle time. This is because, if a new cycle time shorter than the old cycle time were inputted, the condition (6) would not be satisfied again.
Input of a cycle time is repeated until the condition (6) is satisfied, and when a cycle time satisfying the condition (6) is obtained, the cycle time T.sub.0 is set in common for all wafers in respective lots, i.e., the first and second lots in the example now considered. This cycle time T.sub.0 is used for defining a time period in which the robot 5 circulates the processing loop for one round while serially transporting and exchanging wafers in respective processing parts. The cycle time T.sub.0 is set in common to a steady state and transition states of the processings.
The steady state is such a period in which a train of wafers are progressing along the processing path without changing the sequence of processings. The transition states include an initial state and a terminating state. The initial state is such a state in which the leading wafer of a lot is being processed in the processing path. The terminating state is a state that the end wafer in a lot enters the processing path. Due to step 105, the following condition (7) is applied to the cycle time T.sub.0.
T.sub.0 &#8807;max (T.sub.1, . . . TN.sub.n2, T.sub.c)    (7)
Preferably, the cycle time T.sub.0 is selected in accordance with the condition (8).
In the example now considered, the cycle time T.sub.0 is determined as: ##EQU1##
In the next step 106, values representing the respective waiting times T.sub.wj (j=1 to N.sub.2) for introduction to respective processing parts are inputted. As described above, the respective waiting times T.sub.wj must be equal to or shorter than the time T.sub.s which is obtained by subtracting the circulation time from the cycle time, i.e,
T.sub.wj &#8806;T.sub.s =T.sub.0 -T.sub.c (j=1 to N.sub.2) (10)
If the time T.sub.wj is longer than the value T.sub.s, the robot 5 can not circulate through all the processing parts within the cycle time T.sub.0. In order to direct the operator's attention to the condition (10), the value T.sub.s is displayed on the display 14 before entering the step 106. An additional condition for determining T.sub.wj is provided in the next step 107, which is more severe than the step 105.
What is judged in the step 107 is whether the cycle time T.sub.0 is longer or shorter than the sum U.sub.m of the circulation time T.sub.c =N.sub.1 respective processings on a certain lot represented by m. Further, it is also judged whether the cycle time T.sub.0 is equal to or larger than the sum V.sub.j of the processing time T.sub.j and the waiting time T.sub.wj for j=1, 2, . . . N.sub.2. ##EQU2## and then, judged is whether all of:
T.sub.0 &#8807;U.sub.m =T.sub.c +S.sub.m                  (14)
T.sub.0 &#8807;V.sub.j =T.sub.j +T.sub.wj                 (15)
are satisfied or not, where m=1 to k and j=1, 2 . . . N.sub.2.
This condition (14) is required for the same reason as that described in reference to the step 106, however, the condition (14) in the step 107 is more severe than the condition (6) in the step 105 since the right hand side of the expression (14) includes the sum S.sub.m of the values T.sub.wj satisfying the condition T.sub.wj ≧0 in addition to the value T.sub.c.
When the conditions (14) and (15) are not satisfied, new values for T.sub.wj are inputted and this process is repeated until values of T.sub.wj satisfying the conditions (14) and (15) are found.
Preferably, the waiting times T.sub.wj are determined so that the conditions:
In the example now considered, inputted are the values of T.sub.wj indicated in the following equations (18) to (21). It is easily confirmed that the values of T.sub.wj in the equations (18) to (21) satisfy the conditions (14) and (15) required in the step 107.
T.sub.wj =0 second (j&#8800;1, 6, 9)                       (21)
In other words, the longest one, among the circulation time T.sub.c =N.sub.1 N.sub.2) of all the processing parts, is chosen as a maximum time T.sub.max. Then the cycle time T.sub.0 is chosen so as to satisfy the condition:
T.sub.0 &#8807;T.sub.max                                  (22)
Preferably, finite values are given only to the waiting times T.sub.wj for the heating processing parts. The expressions (20) and (21) correspond to the preferable case.
In the step 109, a number α+1 is given as a new value of α for designating the processing part which follows the processing part in which the robot 5 is positioned at the moment. In the step 110, it is judged whether or not there is a need for moving the robot 5 to the processing part α. For example, after the first wafer is introduced in the processing part 41 for the processing HP.sub.1, there is not a need of moving the robot 5 to the processing part 43 for the processing CP.sub.1. Therefore, the processing is proceeded to a termination routine 111, which will be more fully described later.
When there is a need of transporting the wafer to the processing part for the α-th processing, the robot 5 moves to the α-th processing part (the step 112), and the number i is defined by the number α in the step 113. A cycle timer S.sub.i in the step 114 is a timer provided for the i-th processing part, and the cycle time T.sub.0 is set in the cycle timer S.sub.i. In the step 114, the robot 5 waits at a position fronting on the i-th processing part until the cycle timer S.sub.i times up. In the step 115, the cycle timer S.sub.i is reset and restarted when the cycle time T.sub.0 has passed and the cycle timer S.sub.i times up. In response to the timing-up of the timer S.sub.i, the processing in the i-th processing part is started. The counting of time from zero to T.sub.0 is repeated in the timer S.sub.i, so that the processing in the i-th processing part is repeated at intervals of the cycle time T.sub.0.
In order to avoid complicating FIG. 9, the operation of the cycle timer S.sub.i in the case where the first wafer is processed is not shown in FIG. 9. In this case, a cycle timer S.sub.1 for the indexer 1 times up immediately, and the wafer is transported to the processing part 41 for the processing HP.sub.1 at once. The cycle timers for the following processing parts are not enabled to count the cycle time T.sub.0 because the step 115 of these processing parts have not conducted yet. Therefore, these cycle timer stated are so designed that these cycle timers in the initial state time up when the waiting time and the transportation time have passed since the robot 5 started to take the wafer out of the preceding processing part.
In the step 116, if there is a wafer already in the i-th processing part, this wafer is taken out thereof. In the step 118, it is judged whether a finite waiting time for introduction of the wafer is provided for the current processing part. If provided, the robot 5 spends the waiting time in front of the i-th processing part while waiting for taking the wafer therein, in the step 119. Then, the robot 5 takes the wafer in the i-th processing part in the step 120. By repeating the process described above, the transportation of wafers along the processes path is controlled using the cycle time T.sub.0 and the waiting times T.sub.wj.
With the operation flow described above, an excess heat processing at the processing HP.sub.1 can be avoided. How the excess heat processing can be avoided will be described with reference to FIG. 12A, in which flows the wafers 3a-3h are represented by arrows 16a-16h, respectively.
After the robot 5 takes a wafer 3f out of the indexer 1 (α-1), the robot 5 moves to the processing part 41 (α=2) in the steps 109, 110 and 112. The current position (i=2) is resistered in the step 113. The cycle timer S.sub.2 for the processing part 41 times up when the robot 5 arrived at the processing part 41. Therefore, the timer is reset and starts (the steps 114 and 115). Since the heat processing on a wafer 3e which is in the processing part 41 has been completed, the wafer 3e has to be taken out thereof. In the step 116, therefore, the wafer 3e is taken out of the processing part 41 at a time A shown in FIG. 12A.
According to the conventional transportation method, the wafer 3f is immediately introduced in the processing part 41. According to the preferred embodiment of the present invention, on the other hand, there is provided a waiting time 18a for taking the wafer therein. Specifically, it is found in the step 188 that a finite waiting time is provided to the processing part 41 for the processing HP.sub.1. Then, the robot 5 waits in the step 119 for taking the wafer therein for a time corresponding to the difference t.sub.3 =(70-60) seconds=10 seconds. When the time t.sub.3 has past at a time B shown in FIG. 12A, the wafer 3f is introduced in the processing part 41 in the step 120. Therefore, there is no wafer in the processing part 41 from the time A to the time B, i.e., during the waiting time 18a. The transportation time starts at the time B and ends at the time A, and therefore, the definition of the transportation time shown in FIG. 5 can be applied. Through the step 109 and the others, the robot 5 transports the wafer 3e to the processing part 43 for the CP.sub.1 processing.
Thus, an excess heat on wafers due to limitation in the rounding rate can be avoided by setting the common cycle time T.sub.0 as well as by providing waiting times before the heat processing parts.
To be more precise, when it is not necessary to take a wafer out of the processing part in the step 116, the robot 5 waits for a taking-out time T.sub.out, while the robot waits for a taking-in time T.sub.in when it is not necessary to take the wafer in the processing part in the step 120.
The wafer 3d belongs to the first lot different from the second lot including the wafers 3a to 3c, and is to be subjected to the processing HP.sub.2 for a different time from the wafers 3a to 3c. The wafer 3d and the other respective wafers belonging to the first lot should be subjected to the processing HP.sub.2 for a time shorter by t.sub.1 =t.sub.2 =T.sub.4 -T.sub.9 =5 seconds than a time of the processing HP.sub.2 for the second lot. Since the cycle time T.sub.0 is set in common to respective lots, a waiting time 18b of t.sub.4 =5 seconds can be provided for the wafer 3d. The wafer 3c which has been subjected to the processing HP.sub.2 is taken out of the processing part 42 at the time A, and the wafer 3d is introduced therein at the time B.
As described above, the common cycle time T.sub.0 is set for the plurality of the lots and the waiting times 18a and 18b are provided as a function of the cycle time T.sub.0, so that an excess heat processing on respective wafers can be avoided. Furthermore, the respective wafers are processed in accordance with a temperature curve approximate to the ideal temperature curve shown in FIG. 15, and differences in a heat history among a plurality of lots. Further, a difference in the temperature curves for respective lots can also be avoided.
Although it seems that productivity would fall down if the cycle item for the second lot is also set for 70 seconds, this is not true as understood from the following example. That is, assumed is a case where different cycle times are set for the first and second lots, i.e., cycle times of 70 and 65 seconds are assigned to the respective twenty five wafers in the first and second lots, respectively, and the latter cycle time of 65 seconds is effectuated only after all of the twenty five wafers in the first lot have been processed in the respective processing parts. In this case, the cycle time in the system is changed from 70 seconds to 65 seconds only after the last four wafers, i.e., the twenty-second to the twenty-fifth wafers, in the first lot have been subjected to the processings with the cycle time of 70 seconds. This means that 70 seconds
According to the preferred embodiment of the present invention described above, on the other hand, the lost time is only (70-65 seconds ) on the second lot. Therefore, the lost time is less and the productivity is higher in the preferred embodiment of the present invention than in the case of processing each lot independently.
______________________________________Developer      NMD-3 2.38% (obtainable from          Tokyo Ohka Kogyo Co., Ltd.)Developing Time          60 secondsTemperature of 23DeveloperWater Rinsing  15 secondsDrying         15 seconds______________________________________
When the processing times T.sub.11 to T.sub.15 shown in Table 3 are applied to a lot, the total processing rate in the processing path is determined from the processing time T.sub.90 of the processing C.
In order to satisfy the condition required in the step 107, a cycle time T.sub.0 should be at least 90 seconds. Therefore, a cycle time T.sub.0 is set as T.sub.0 =90 seconds, for example. Since the processings CP.sub.1 and CP.sub.2 are cool processings, it is not necessary to consider the problem of excess heat shown in FIG. 15(b). Thus, a waiting time T.sub.W11 =t.sub.0 -T.sub.11 =20 seconds is provided before the processing HP.sub.1, while a waiting time T.sub.W14-T.sub.0 -T.sub.14 =10 seconds is provided before the processing HP.sub.2. The problem of an excess heat during the processings HP.sub.1 and HP.sub.2 can be thus avoided.
The total transportation time required for transporting a wafer through all the processing parts is 48 seconds, and the difference between the cycle time T.sub.0 and the total transportation time is 42 seconds. The sum of the waiting times T.sub.W11 and T.sub.W14 is 30 seconds and is twelve-seconds less than the difference, i.e., 42 seconds. The robot 5 must wait for the time of twelve seconds other than the waiting times for introduction. The robot 5 may wait for this additional time at any positions. FIG. 12B shows an example in which the robot 5 waits for this additional time at the indexer 1. On arrows 16 representing flows of the processings conducted on respective wafers, time periods 18c and 18d represent the waiting times T.sub.W11 and T.sub.W14, respectively.
The waiting times may be provided under the control other than the control shown in FIG. 9. As shown in FIG. 10, the indexer 1 may control a master cycle timer S.sub.1, while each processing part may control respective processing timers S.sub.1, for example. Specifically, the interval between one departure and the next departure of the robot 5 from the indexer 1 is so controlled in the steps 121 and 114a as to be the cycle time T.sub.0, and the master cycle timer S.sub.1, is started in the step 115a. Exceptionally, the master timer S.sub.1, immediately times up in the step 114a when the first wafer is introduced.
No processing times may be controlled in respective processing parts, as shown in FIG. 11. Step 112a has steps 124, 125 in addition to the step 122. In this case, the respective moving time T.sub.move of the robot 5 between two processing parts are controlled by a moving timer M (the step 123, 124).
When there is a lot which is not subjected to heat processings, the waiting times T.sub.wj for the lot may be determined according to the condition: ##EQU3## where the number m indicates the lot.
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