Source: http://www.google.com/patents/US4954214?ie=ISO-8859-1&dq=5,222,134
Timestamp: 2014-07-26 12:17:57
Document Index: 529740465

Matched Legal Cases: ['Application No. 199', 'Application No. 567', 'Application No. 199', 'Application No. 567', 'Application No. 207', 'Application No. 569', 'Application No. 207', 'Application No. 569']

Patent US4954214 - Very large scale integration, semiconductors - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsIn methods for making interconnect structures for semiconductor devices a layer of seed material is formed on a first substantially planar dielectric layer which covers the semiconductor devices at predetermined locations where interconnect conductor is desired, a second substantially planar dielectric...http://www.google.com/patents/US4954214?utm_source=gb-gplus-sharePatent US4954214 - Very large scale integration, semiconductorsAdvanced Patent SearchPublication numberUS4954214 APublication typeGrantApplication numberUS 07/293,789Publication dateSep 4, 1990Filing dateJan 5, 1989Priority dateJan 5, 1989Fee statusPaidPublication number07293789, 293789, US 4954214 A, US 4954214A, US-A-4954214, US4954214 A, US4954214AInventorsVu Quoc HoOriginal AssigneeNorthern Telecom LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Non-Patent Citations (16), Referenced by (44), Classifications (12), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetVery large scale integration, semiconductorsUS 4954214 AAbstract In methods for making interconnect structures for semiconductor devices a layer of seed material is formed on a first substantially planar dielectric layer which covers the semiconductor devices at predetermined locations where interconnect conductor is desired, a second substantially planar dielectric insulating layer is formed over the first substantially planar dielectric insulating layer and the seed material, the second layer having openings extending therethrough at the predetermined locations to expose at least a portion of the seed material, and conductive material is selectively deposited on the exposed seed material to fill the openings. The seed material may be a material in the group consisting of aluminum alloys, refractory metals and metal silicides, or may be SiO2 selectively implanted with silicon ions. The insulating material may be SiO2. The conductive material used to fill the openings may be tungsten deposited by selective CVD or nickel deposited by selective electroless nickel plating. The steps of the methods may be repeated to form a multilevel interconnect structure. The methods are particularly suited to making interconnect structures for submicron devices.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4317700 *Aug 20, 1980Mar 2, 1982Rockwell International CorporationMethod of fabrication of planar bubble domain device structuresUS4585515 *Mar 11, 1985Apr 29, 1986Rca CorporationFormation of conductive linesUS4652334 *Mar 6, 1986Mar 24, 1987General Motors CorporationMethod for patterning silicon dioxide with high resolution in three dimensionsUS4753709 *Feb 5, 1987Jun 28, 1988Texas Instuments IncorporatedMethod for etching contact vias in a semiconductor deviceUS4844776 *Dec 4, 1987Jul 4, 1989American Telephone And Telegraph Company, At&T Bell LaboratoriesMethod for making folded extended window field effect transistor* Cited by examinerNon-Patent CitationsReference1Broadbent et al, "High-Density High-Reliability Tungsten Interconnection by Filled Interconnect Groove Metallization", IEEE Transactions on Electron Devices, vol. 35, No. 7, pp. 952-956, Jul. 1988.2 *Broadbent et al, High Density High Reliability Tungsten Interconnection by Filled Interconnect Groove Metallization , IEEE Transactions on Electron Devices, vol. 35, No. 7, pp. 952 956, Jul. 1988.3 *Gregory Smith, CVD Tungsten Contact Plugs by in Situ Deposition and Etchback, Jun. 25 26, 1985 V MIC Conf.4Gregory Smith, CVD Tungsten Contact Plugs by in Situ Deposition and Etchback, Jun. 25-26, 1985 V-MIC Conf.5Hennessy et al "Selective CVD Tungsten on Silicon Implanted SiO2 ", Journal of the Electrochemical Society, Solid State Science and Technology, pp. 1730-1734, Jul. 1988.6 *Hennessy et al Selective CVD Tungsten on Silicon Implanted SiO 2 , Journal of the Electrochemical Society, Solid State Science and Technology, pp. 1730 1734, Jul. 1988.7 *Higelin et al, A Contact Filling Process with CVD Tungsten for Multilevel Metallization Systems, Jun. 9 10, 1986 V MIC Conf.8Higelin et al, A Contact Filling Process with CVD-Tungsten for Multilevel Metallization Systems, Jun. 9-10, 1986 V-MIC Conf.9 *Mehta et al, Blanket CVD Tungsten Interconnect for VLSI Devices, Jun. 9 10, 1986 V MIC Conf.10Mehta et al, Blanket CVD Tungsten Interconnect for VLSI Devices, Jun. 9-10, 1986 V-MIC Conf.11 *Proceedings of the IEEE V MIC Conference, pp. 331 337, Jun. 13 14, 1988. Pai et al.12Proceedings of the IEEE V-MIC Conference, pp. 331-337, Jun. 13-14, 1988. Pai et al.13 *U.S. Application No. 199,489 Filed May 27, 1988 and co pending Canadian Application No. 567,935 filed May 27, 1988.14U.S. Application No. 199,489 Filed May 27, 1988 and co-pending Canadian Application No. 567,935 filed May 27, 1988.15 *U.S. Application No. 207,568 filed Jun. 16, 1988 and co pending Canadian Application No. 569,516 filed Jun. 15, 1988.16U.S. Application No. 207,568 filed Jun. 16, 1988 and co-pending Canadian Application No. 569,516 filed Jun. 15, 1988.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5116463 *Jun 19, 1991May 26, 1992Microelectroncs And Computer Technology CorporationFilling aperture in mask which then change the electrochemical potentialUS5183795 *Oct 10, 1991Feb 2, 1993Intel CorporationSelective, electroless deposition of metal into interconnect channels; spacing to give low electrical resistance and high resistance to electromigration and stress migrationUS5209817 *Aug 22, 1991May 11, 1993International Business Machines CorporationSimplification of processUS5225358 *Aug 23, 1991Jul 6, 1993Lsi Logic CorporationIn single step after transistor fabrication by chemical vapor deposition of oxide or borophosphosilicate glass over waferUS5248625 *Aug 22, 1991Sep 28, 1993Lsi Logic CorporationTechniques for forming isolation structuresUS5252503 *Nov 20, 1992Oct 12, 1993Lsi Logic CorporationTechniques for forming isolation structuresUS5298110 *Nov 20, 1992Mar 29, 1994Lsi Logic CorporationPolishingUS5312770 *Nov 20, 1992May 17, 1994Lsi Logic CorporationTechniques for forming isolation structuresUS5354712 *Nov 12, 1992Oct 11, 1994Northern Telecom LimitedMethod for forming interconnect structures for integrated circuitsUS5413966 *Sep 9, 1993May 9, 1995Lsi Logic CorporationSemiconductorsUS5441094 *Feb 8, 1994Aug 15, 1995Lsi Logic CorporationTrench planarization techniquesUS5455198 *Dec 27, 1993Oct 3, 1995Hyundai Electronics Industries Co., Ltd.Method for fabricating tungsten contact plugUS5459100 *Dec 21, 1994Oct 17, 1995Hyundai Electronics Industries Co., Ltd.Method for forming metal wiring of semiconductor deviceUS5646070 *Mar 6, 1995Jul 8, 1997Philips Electronics North American CorporationMethod of forming conductive region on silicon semiconductor material, and silicon semiconductor device with such regionUS5702567 *Jun 1, 1995Dec 30, 1997Kabushiki Kaisha ToshibaPlurality of photolithographic alignment marks with shape, size and spacing based on circuit pattern featuresUS5795825 *Apr 8, 1996Aug 18, 1998Sony CorporationConnection layer forming methodUS5880018 *Oct 7, 1996Mar 9, 1999Motorola Inc.Method for manufacturing a low dielectric constant inter-level integrated circuit structureUS5904533 *Feb 25, 1997May 18, 1999Winbond Electronics Corp.Metal salicide-CMP-metal salicide semiconductor processUS5917205 *May 2, 1997Jun 29, 1999Kabushiki Kaisha ToshibaPhotolithographic alignment marks based on circuit pattern featureUS5940726 *Nov 6, 1997Aug 17, 1999Taiwan Semiconductor Manufacturing Company, Ltd.In the fabrication of an integrated circuitUS5940729 *Apr 17, 1996Aug 17, 1999International Business Machines Corp.Method of planarizing a curved substrate and resulting structureUS5981369 *May 30, 1997Nov 9, 1999Hitachi, Ltd.Semiconductor integrated circuit device and process for manufacturing the sameUS6069078 *Dec 30, 1997May 30, 2000Utmc Microelectronic Systems Inc.Multi-level interconnect metallization techniqueUS6150255 *Aug 13, 1999Nov 21, 2000International Business Machines CorporationMethod of planarizing a curved substrate and resulting structureUS6221763Apr 5, 1999Apr 24, 2001Micron Technology, Inc.Method of forming a metal seed layer for subsequent platingUS6245658Feb 18, 1999Jun 12, 2001Advanced Micro Devices, Inc.Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection systemUS6246118 *Feb 18, 1999Jun 12, 2001Advanced Micro Devices, Inc.Low dielectric semiconductor device with rigid, conductively lined interconnection systemUS6268289 *May 18, 1998Jul 31, 2001Motorola Inc.Method for protecting the edge exclusion of a semiconductor wafer from copper plating through use of an edge exclusion masking layerUS6406743Jul 10, 1997Jun 18, 2002Industrial Technology Research InstituteIntegrated circuitsUS6423992 *May 15, 2001Jul 23, 2002Hitachi, Ltd.Semiconductor integrated circuit deviceUS6436816 *Jul 31, 1998Aug 20, 2002Industrial Technology Research InstitutePatterns to form an interconnect; said metal layer composed of a material selected from the group consisting of ni, cu, and palladium,US6489235Jan 4, 2001Dec 3, 2002Micron Technology, Inc.Method of forming a metal seed layer for subsequent platingUS6660625May 28, 2002Dec 9, 2003Industrial Technology Research InstituteMethod of electroless plating copper on nitride barrierUS6667552 *Feb 18, 1999Dec 23, 2003Advanced Micro Devices, Inc.Low dielectric metal silicide lined interconnection systemUS6713377May 28, 2002Mar 30, 2004Industrial Technology Research InstituteMethod of electroless plating copper on nitride barrierUS6756301Nov 1, 2002Jun 29, 2004Micron Technology, Inc.Method of forming a metal seed layer for subsequent platingUS6815762Oct 13, 1999Nov 9, 2004Hitachi, Ltd.Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit linesUS8294273 *Jan 6, 2011Oct 23, 2012Micron Technology, Inc.Methods for fabricating and filling conductive vias and conductive vias so formedUS8324100 *Feb 17, 2011Dec 4, 2012Micron Technology, Inc.Methods of forming conductive viasUS20110095429 *Jan 6, 2011Apr 28, 2011Micron Technology, Inc.Methods for fabricating and filling conductive vias and conductive vias so formedUS20110136336 *Feb 17, 2011Jun 9, 2011Micron Technology, Inc.Methods of forming conductive viasUS20120244710 *Mar 23, 2011Sep 27, 2012Globalfoundries Dresden Module One Limited Liability Company & Co. KgShrinkage of Critical Dimensions in a Semiconductor Device by Selective Growth of a Mask MaterialDE19538019A1 *Oct 12, 1995Apr 18, 1996Hyundai Electronics IndVerfahren zur Bildung einer Metallverdrahtung einer HalbleitereinrichtungDE19538019B4 *Oct 12, 1995Mar 2, 2006Hyundai Electronics Industries Co., Ltd., IchonVerfahren zur Bildung einer Metallverdrahtung einer Halbleitereinrichtung* Cited by examinerClassifications U.S. Classification438/628, 257/E21.295, 257/E21.586, 438/639, 438/630, 438/683International ClassificationH01L21/768, H01L21/3205Cooperative ClassificationH01L21/76879, H01L21/32051European ClassificationH01L21/768C4B, H01L21/3205MLegal EventsDateCodeEventDescriptionNov 19, 2001FPAYFee paymentYear of fee payment: 12Jul 12, 2001ASAssignmentOwner name: STMICROELECTRONICS N.V., SWITZERLANDFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NORTEL NETWORKS LIMITED;REEL/FRAME:011967/0805Effective date: 20010525Owner name: STMICROELECTRONICS N.V. ROUTE DE PRE-BOIS 20 1215NOwner name: STMICROELECTRONICS N.V. ROUTE DE PRE-BOIS 201215NFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NORTEL NETWORKS LIMITED /AR;REEL/FRAME:011967/0805Aug 30, 2000ASAssignmentOwner name: NORTEL NETWORKS LIMITED, CANADAFree format text: CHANGE OF NAME;ASSIGNOR:NORTEL NETWORKS CORPORATION;REEL/FRAME:011195/0706Effective date: 20000830Free format text: CHANGE OF NAME;ASSIGNOR:NORTEL NETWORKS CORPORATION;REEL/FRAME:11195/706Owner name: NORTEL NETWORKS LIMITED,CANADADec 23, 1999ASAssignmentOwner name: NORTEL NETWORKS CORPORATION, CANADAFree format text: CHANGE OF NAME;ASSIGNOR:NORTHERN TELECOM LIMITED;REEL/FRAME:010567/0001Effective date: 19990429Owner name: NORTEL NETWORKS CORPORATION WORLD TRADE CENTER OFOct 16, 1997FPAYFee paymentYear of fee payment: 8Sep 9, 1993FPAYFee paymentYear of fee payment: 4Mar 30, 1989ASAssignmentOwner name: NORTHERN TELECOM LIMITED, CANADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:HO, VU QUOC;REEL/FRAME:005037/0851Effective date: 19881212RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google