Source: https://patents.google.com/patent/US10146291B2/en
Timestamp: 2020-02-20 10:45:11
Document Index: 187133512

Matched Legal Cases: ['art 600', 'Application No. 2014', 'Application No. 2015', 'Application No. 2014', 'Application No. 2014', 'Application No. 2014']

US10146291B2 - Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints - Google Patents
Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints Download PDF
US10146291B2
US10146291B2 US14/757,924 US201514757924A US10146291B2 US 10146291 B2 US10146291 B2 US 10146291B2 US 201514757924 A US201514757924 A US 201514757924A US 10146291 B2 US10146291 B2 US 10146291B2
US14/757,924
US20160209912A1 (en
2013-03-15 Priority to US13/835,275 priority Critical patent/US20140281622A1/en
2015-12-24 Priority to US14/757,924 priority patent/US10146291B2/en
2016-07-21 Publication of US20160209912A1 publication Critical patent/US20160209912A1/en
2018-12-04 Publication of US10146291B2 publication Critical patent/US10146291B2/en
A serial point-to-point link interface to enable communication between a processor and a device, the high speed serial point-to-point link interface including a transmitter to transmit serial data, a receiver to deserialize serial data, and control logic to implement a protocol stack. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is maintained, and a second off state, in which the supply voltage is not to be provided to the device. The protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device. The protocol stack further provides for accessing the device prior to expiration of the default recovery time to complete the transition based on a device-advertised recovery time.
This application is a continuation of and claims the benefit of priority to U.S. patent application Ser. No. 13/835,275, filed Mar. 15, 2013, which is hereby incorporated by reference herein in its entirety.
This disclosure pertains to computing system, and in particular (but not exclusively) to resume times for root ports and root port integrated endpoints.
As electronic apparatuses become more complex and ubiquitous in the everyday lives of users, more and more diverse requirements are placed upon them. To satisfy many of these requirements, many electronic apparatuses comprise many different devices, such as a CPU, a communication device, a graphics accelerator, etc. In many circumstances, there may be a large amount of communication between these devices. Furthermore, many users have high expectations regarding apparatus performance. Users are becoming less tolerant of waiting for operations to be performed by their apparatuses. In addition, many apparatuses are performing increasingly complex and burdensome tasks that may involve a large amount of inter-device communication. Therefore, there may be some communication between these devices that would benefit from rapid response times.
FIG. 1 illustrates an embodiment of a block diagram for a computing system including a multicore processor according to at least one example embodiment.
FIG. 2 illustrates an embodiment of a computing system including an interconnect architecture according to at least one example embodiment.
FIG. 3 illustrates an embodiment of a interconnect architecture including a layered stack according to at least one example embodiment.
FIG. 4 illustrates an embodiment of a request or packet to be generated or received within an interconnect architecture according to at least one example embodiment.
FIG. 5 illustrates an embodiment of a transmitter and receiver pair for an interconnect architecture according to at least one example embodiment.
FIG. 6 illustrates an example power management state transition chart.
FIG. 7 is a flow diagram according to at least one embodiment.
FIG. 8 is a flow diagram according to at least one embodiment.
FIG. 9 is a flow diagram according to at least one example embodiment.
Although the following embodiments may be described with reference to improving resume times for root ports and root port integrated endpoints, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from improved resume times. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™. And may be also used in other devices, such as handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatus', methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for improved resume times.
FIG. 1 is a block diagram illustrating components associated with improving resume times for root ports and root port integrated endpoints according to at least one example embodiment. The examples of FIG. 1 are merely examples of components associated with improving resume times for root ports and root port integrated endpoints, and do not limit the scope of the claims. For example, operations attributed to a component may vary, number of components may vary, composition of a component may vary, and/or the like. For example, in some example embodiments, operations attributable to one component of the example of FIG. 1 may be allocated to one or more other components.
Processor 100 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SOC), or other device to execute code. Processor 100, in one embodiment, includes at least two cores—core 101 and 102, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 100 may include any number of processing elements that may be symmetric or asymmetric.
As depicted, core 101 includes two hardware threads 101 a and 101 b, which may also be referred to as hardware thread slots 101 a and 101 b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor 100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 101 a, a second thread is associated with architecture state registers 101 b, a third thread may be associated with architecture state registers 102 a, and a fourth thread may be associated with architecture state registers 102 b. Here, each of the architecture state registers (101 a, 101 b, 102 a, and 102 b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 101 a are replicated in architecture state registers 101 b, so individual architecture states/contexts are capable of being stored for logical processor 101 a and logical processor 101 b. In core 101, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 130 may also be replicated for threads 101 a and 101 b. Some resources, such as re-order buffers in reorder/retirement unit 135, branch target buffer (BTB) and instruction-translation buffer (I-TLB) 120, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 150, execution unit(s) 140, and portions of out-of-order unit 135 are potentially fully shared.
Processor 100 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In FIG. 1, an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core 101 includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a BTB and I-TLB 120 to predict branches to be executed/taken and a BTB and I-TLB 120 to store address translation entries for instructions.
Core 101 further includes decode module 125 coupled to BTB and I-TLB 120 to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 101 a, 101 b, respectively. Usually core 101 is associated with a first ISA, which defines/specifies instructions executable on processor 100. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic 125 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below decoders 125, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders 125, the architecture or core 101 takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note decoders 125, in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 125 recognize a second ISA (either a subset of the first ISA or a distinct ISA).
In one example, renamer/allocator block 130 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 101 a and 101 b are potentially capable of out-of-order execution, where allocator and renamer block 130 also reserves other resources, such as reorder buffers to track instruction results. Unit 130 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 100. Reorder/retirement unit 135 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.
In the depicted configuration, processor 100 also includes on-chip interface module 110. Historically, a memory controller, which is described in more detail below, has been included in a computing system external to processor 100. In this scenario, on-chip interface module 110 is to communicate with devices external to processor 100, such as system memory 175, a chipset (often including a memory controller hub to connect to memory 175 and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus 105 may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.
Recently however, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor 100. For example in one embodiment, a memory controller hub is on the same package and/or die with processor 100. Here, a portion of the core (an on-core portion) 110 includes one or more controller(s) for interfacing with other devices such as memory 175 or a device 180. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, on-chip interface 110 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 105 for off-chip communication. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory 175, device 180, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.
In some implementations, a power management controller 160 can also be provided and implemented in hardware and software. A system, and devices connected to the system, can support multiple power states, including full power, low power, and no power states, among other (e.g., intermediate) states and conditions. The power management controller 160 can provide functions and perform tasks to assist in minimizing system power consumption, manage system thermal limits, and maximize system battery life, among other functionality. Power management can include managing other functionality and characteristics of the system, including system speed, noise, battery life, and AC power consumption, among other examples.
On-chip interface can include a resume time module 104. Resume time module 104 can include a processor 182 and memory 184. On-chip interface 110 and device 180 may communicate through a peripheral component interconnect express (PCIe)-compliant, or other connection. In some interconnect protocols, such as peripheral component interconnect (PCI) and PCIe, architected mechanisms can be provided to delay entries of devices into full power states (e.g., in connection with certain power management policies and capabilities). For instance, software, such as power management logic of a device operating system, can at least partially control entries and exits into various power states. In some instances, platform policies can provide minimum recovery times (delays) before allowing software to issuing configuration requests to device, for instance, in connection with the initialization of a power state. For instance, to improve idle power usage, power management policies and functionality can attempt to place devices, including discrete attached devices, Root Ports (RP), and Root Complex Integrated End Points (RCIE), etc., as well as external devices connected over the interconnect, into power managed states where the power to these devices could be removed, the devices could operate in a lower power state, or these devices could be operating under auxiliary power. On resume from these power states, software waits for a specified amount of time (e.g., 10 ms, 100 ms, etc.) before it will issue configuration requests. This can have a significant impact on resume time. Such defined minimum recovery times, while advantageous in some contexts and in connection with some devices, however, may be undesirable in other contexts and in connection with other devices.
In some implementations, on-chip interface can include a resume time module 104. Resume time module 104 can include a processor 182 and memory 184. Resume time module 104 can be configured to allow an internal device, such as a root port, designated port (DP), or RCIE to advertise a device-specific recovery time indicating how soon after a power state transition (e.g., initial power on, D3 to D0 transition, etc.) the device will be ready for first configuration (e.g., in connection with software). In an embodiment, resume time module 104 can further include an interrupt mechanism (e.g., capability description, control mechanism to enable interrupts) for internal devices to trigger an interrupt when it completes or is ready to complete a power state transition (e.g., initial power-on, D3 to D0 transition, etc.), to further force an end to a pre-set recovery time or otherwise initiate configuration tasks to be performed by software.
In some implementations, device-specific resume time capabilities can be defined in one or more capability registers and can be accessed by one or more power management tools, including software-based tools. In one example, during enumeration of devices (e.g., one or more devices 180, including external or internal devices), resume time module 104 may access a device's resume time capability and store it in memory 184 for later use. Resume time module 104 may also read the interrupt capability of a device and implement an interrupt mechanism instead of a polling mechanism to enable triggering and recognition of an interrupt when an internal device is ready for configuration access. For example, at some point, an internal device can transition into a low power state. In an embodiment, resume time module 104 can determine that the internal device is to transition from the low power state into a full power state. Further, resume time module 104 may retrieve the resume time advertised value for device 180 from memory 184 and then issue a first configuration request after waiting for the time period in memory 184 that was advertised by the internal device in a corresponding capability structure, among other examples.
In another embodiment, resume time module 104 can determine that it is going to apply power to the sub-system that has control of a device 180. If device 180 is configured to send an interrupt when device 180 has exited the low power state, resume time module 104 may wait for the interrupt to be received from the device 180 indicating that it is ready for first configuration access. In both cases, resume time module can remove the 100 ms fixed architected wait time before accessing the device with first configuration access. Resume time module 104 may also remove the a fixed, architected wait time for software before accessing a device with first configuration access after writing to a power management control and status register (PMCSR). To maintain backwards compatibility, architected recovery times, (e.g., legacy 100 ms or 10 ms (for access after PMCSR write) delay) should not be extended by resume time module 104 and can be supported as a default for devices that do not employ custom resume time capabilities. As stated above, on-chip interface 110 and device 180 may communicate through a link connection, such as a PCIe, MIPI, QPI, or other protocol-compliant interconnect link.
A primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices. PCIe is a high performance, general purpose I/O interconnect defined for a wide variety of future computing and communication platforms. Some PCI attributes, such as its usage model, load-store architecture, and software interfaces, have been maintained through its revisions, whereas previous parallel bus implementations have been replaced by a highly scalable, fully serial interface. The more recent versions of PCIe take advantage of advances in point-to-point interconnects, switch-based technology, and packetized protocol to deliver new levels of performance and features. Power Management, Quality Of Service (QoS), Hot-Plug/Hot-Swap support, Data Integrity, and Error Handling are among some of the advanced features supported by PCIe.
In one embodiment, controller hub 215 is a root hub, root complex, or root controller in a PCIe interconnection hierarchy. Examples of controller hub 215 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH) a southbridge, and a root controller/hub. Often the term chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include the MCH integrated with processor 205, while controller 215 is to communicate with I/O devices, in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported through root complex 215.
Graphics accelerator 230 is also coupled to controller hub 215 through serial link 232. In one embodiment, graphics accelerator 230 is coupled to an MCH, which is coupled to an ICH. Switch 220, and accordingly I/O device 225, is then coupled to the ICH. I/O modules 231 and 218 are also to implement a layered protocol stack to communicate between graphics accelerator 230 and controller hub 215. Similar to the MCH discussion above, a graphics controller or the graphics accelerator 230 itself may be integrated in processor 205. Further, in some implementations, one or more internal devices (e.g., 211, 212, 213) can be provided, for instance, on a chipset, controller hub, root complex, etc. For instance, root complex integrated endpoints (RCIE), a downstream port or root port (e.g., 217), internal PCI devices, and other internal devices can be provided. Functionality described herein can apply to internal devices as well as external devices.
Referring to FIG. 3, an embodiment of a layered protocol stack is illustrated. Layered protocol stack 300 includes any form of a layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or other layered stack. Although the discussion immediately below in reference to FIGS. 2-5 are in relation to a PCIe stack, the same concepts may be applied to other interconnect stacks. In one embodiment, protocol stack 300 is a PCIe protocol stack including transaction layer 305, link layer 310, and physical layer 320. An interface, such as interfaces 217, 218, 221, 222, 226, and 231 in FIG. 2, may be represented as communication protocol stack 300. Representation as a communication protocol stack may also be referred to as a module or interface implementing/including a protocol stack.
PCIe uses packets to communicate information between components. Packets are formed in the Transaction Layer 305 and Data Link Layer 310 to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side the reverse process occurs and packets get transformed from their Physical Layer 320 representation to the Data Link Layer 310 representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer 305 of the receiving device.
In addition PCIe utilizes credit-based flow control. In this scheme, a device advertises an initial amount of credit for each of the receive buffers in transaction layer 305. An external device at the opposite end of the link, such as controller hub 115 in FIG. 2, counts the number of credits consumed by each TLP. A transaction may be transmitted if the transaction does not exceed a credit limit. Upon receiving a response an amount of credit is restored. An advantage of a credit scheme is that the latency of credit return does not affect performance, provided that the credit limit is not encountered.
In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as 64-bit address. Configuration space transactions are used to access configuration space of the PCIe devices. Transactions to the configuration space include read requests and write requests. Message space transactions (or, simply messages) are defined to support in-band communication between PCIe agents. Therefore, in one embodiment, transaction layer 305 assembles packet header/payload 306. Format for current packet headers/payloads may be found in the PCIe specification at the PCIe specification website.
Transaction descriptor 400 includes global identifier field 402, attributes field 404 and channel identifier field 406. In the illustrated example, global identifier field 402 is depicted as including local transaction identifier field 408 and source identifier field 410. In one embodiment, global transaction identifier 402 is unique for all outstanding requests.
Link layer 310, also referred to as data link layer 310, acts as an intermediate stage between transaction layer 305 and physical layer 320. In one embodiment, a responsibility of the data link layer 310 is providing a reliable mechanism for exchanging Transaction Layer Packets (TLPs) between two components a link. One side of data link layer 310 accepts TLPs assembled by transaction layer 305, applies packet sequence identifier 311, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 312, and submits the modified TLPs to physical layer 320 for transmission across a physical to an external device.
In one embodiment, physical layer 320 includes logical sub block 321 and electrical sub-block 322 to physically transmit a packet to an external device. Here, logical sub-block 321 is responsible for the “digital” functions of physical layer 321. In this regard, the logical sub-block includes a transmit section to prepare outgoing information for transmission by physical sub-block 322, and a receiver section to identify and prepare received information before passing it to link layer 310.
As stated above, although transaction layer 305, link layer 310, and physical layer 320 are discussed in reference to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not so limited. In fact, any layered protocol may be included/implemented. As an example, a port/interface that is represented as a layered protocol includes: (1) a first layer to assemble packets, i.e. a transaction layer; a second layer to sequence packets, i.e. a link layer; and a third layer to transmit the packets, i.e. a physical layer. As a specific example, a common standard interface (CSI) layered protocol is utilized.
A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or other communication path. A connection between two devices, such as device 505 and device 510, is referred to as a link, such as link 415. A link may support one lane—each lane representing a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, a link may aggregate multiple lanes denoted by ×N, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.
As noted above, various platforms, such as PCIe, can support multiple power management states. FIG. 6 illustrates an example state transition chart 600 illustrating example power management states (e.g., 605, 610, 615, 620, 625, 630) and transitions between the states. In the example of FIG. 6, four main power states are supported. For instance, a D0 state (e.g., 605, 620) can be a maximum powered, or active, state at one extreme, and a D3 state (e.g., 610, 615) providing a power “off” state. States D1 (e.g., 625) and D2 (e.g., 630) can provided intermediate power states representing, for instance, sleep or light sleep states for a device. In one example, a D3 hot state (e.g., 610) can be provided where Vcc is still applied to the device, to differentiate from a D3 cold state (e.g., 615) where Vcc is removed to completely power off the device.
As represented in FIG. 6, transitions can be defined between the various states (e.g., 605, 610, 615, 620, 625, 630). For example, in one implementation, devices in state D3 hot can be returned to D0 by first bringing the device, upon power up, into a D0 Uninitialized 620 state, for instance by writing the D0 state command to a corresponding power management control state register. In another example, in device state D3 cold, a function can be brought back to D0 from D3 cold (the only legal state transition from D3 cold). In some instances, software can be invoked in connection with a power management state transition, for instance to perform a full or partial reinitialization of the function including its corresponding configuration space. Further, as introduced above, a minimum recovery time requirement can be defined in some instances (e.g., enforced by system software) between when a function is programmed from D3 to D0 and when the function is accessed (including configuration accesses). This can allow time for the function to reset itself and bring itself to a power-on condition. However, as introduced above, such default minimum recovery times can introduce unnecessary delays into the resume time for particular devices. Accordingly, in some implementations, a resume time capability can be provided to allow the device to instead advertise a device-specific recovery time (e.g., shorter (or longer) than an architected minimum recovery time. Additionally, capabilities can be provided to allow a device to initiate an interrupt to trigger configuration accesses prior to the conclusion of an architected (or, even, in some implementations, a device-advertised) minimum recovery time, among other potential examples.
Turning to FIG. 7, a simplified flow diagram 700 is shown. A software controller, such as power management tools of an operating system, can be ready to transition a particular device, such as an internal device of a chip set or system on chip, to full power and cause the device to be powered on 710 and begin a transition from a low or no power state to an active state (e.g., in connection with a particular function to be performed utilizing the device). Polling (e.g., 710) can take place based on capabilities defined for the device in a corresponding power management register, extended capability structure, or other structure or register. For instance, the controller can identify a resume time for the device (e.g., an architected time or advertised time delay) and issue a configuration write to trigger 725 completion of the power state transition upon identifying that the resume time has lapsed. Alternatively, a device can have an interrupt capability defined, for instance, in a capability structure or register, and the controller can identify the capability and wait for an interrupt 720 from the device indicating that the device is ready to enter the active state and receive configuration accesses.
Turning to FIG. 8, a device enumeration process 805 can be performed, in some implementations, to determine if a device, such as an RCIE, root port, downstream port, or other device, supports one or more resume time capabilities. In the particular example of FIG. 8, the enumeration process can ready 810 a capability structure corresponding to the device and determine 815 whether a customized resume or recovery time is advertised and supported. An enumeration process 805 can, in some instances, also determine whether an interrupt capability is also defined for the device to assist in hastening recovery of the device. If it is determined that resume time is supported (e.g., 820) an advertised recovery value can be identified 825 that is specific to the device (e.g., and specified in the capability structure). The advertised recovery value can then be followed by the software controller when beginning configuration access in connection with a power state transition of the device. Alternatively, if it is determined that a specialized resume time is not supported by the device (e.g., 830), the software controller can default to architected protocols, including standard minimum recovery times defined through the architecture (e.g., a 10 ms, 100 ms, etc. fixed, minimum recovery time).
FIG. 9 is a flow diagram showing a set of operations 900 according to at least one example embodiment. Apparatus, for example resume time module 104 of FIG. 1, or a portion thereof, may utilize the set of operations 900. The apparatus may comprise means for performing the operations of FIG. 9. In an example embodiment, an apparatus is transformed by having memory, for example memory 184 and/or memory 175 of FIG. 1, comprising computer code configured to, working with a processor, cause the apparatus to perform set of operations 900.
At block 905, a device can be determined (e.g., from a corresponding register) to be in a low power state. Transition of the device from the low power state to an active state can be initiated, at block 910, for instance, by an at least partially software-based controller. A fixed minimum recovery time can be defined for transitions from the low power state to the active state within a system, such as an architected recovery time in accordance with an interconnect protocol. A capability of the device can be identified, at block 915, corresponding to power management of the device. The capability can include an interrupt mechanism supported for the device and an advertised, alternate recovery time to be applied to the device in lieu of the fixed minimum recovery time. In some cases, both capabilities can be enabled for a device. Transition of the device to the active state can be completed, at block 920, for instance, through configuration of the device initiated by a trigger corresponding to the identified capability. For instance, an advertised recovery time can be applied or an interrupt can be received to trigger completion of the transition of the device to the active state prior to expiration of the fixed minimum recovery time, among other potential examples and implementations.
The principles described above can apply to any variety of different architectures, including various interconnect platforms. Further, the above principles can be applied in a variety of different devices, including multi-processor servers, personal computers, mobile computing devices (e.g., smartphones, tablets, etc.), among other example. As but one example, turning to FIG. 10, an embodiment of a system on-chip (SOC) design is depicted. As a specific illustrative example, SOC 1000 can be included in a computer comprising user equipment (UE). In one embodiment, UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Often a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.
Here, SOC 1000 includes 2 cores—1006 and 1007. Similar to the discussion above, cores 1006 and 1007 may conform to an Instruction Set Architecture, such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters. Cores 1006 and 1007 are coupled to cache control 1008 that is associated with bus interface unit 1009 and L2 cache 1012 to communicate with other parts of system 1000. Interconnect 1010 includes an on-chip interconnect, such as an IOSF, AMBA, or other interconnect discussed above, which potentially implements one or more aspects of the described invention.
Interface 1010 provides communication channels to the other components, such as a Subscriber Identity Module (SIM) 1030 to interface with a SIM card, a boot rom 1035 to hold boot code for execution by cores 1006 and 1007 to initialize and boot SOC 1000, a SDRAM controller 1040 to interface with external memory (e.g. DRAM 1060), a flash controller 1045 to interface with non-volatile memory (e.g. Flash 1065), a peripheral control 1050 (e.g. Serial Peripheral Interface) to interface with peripherals, video codecs 1020 and Video interface 1025 to display and receive input (e.g. touch enabled input), GPU 1015 to perform graphics related computations, etc. Any of these interfaces may incorporate aspects of the invention described herein.
The following examples pertain to embodiments in accordance with this Specification. One or more embodiments may provide an apparatus, a system, a machine readable storage, a machine readable medium, and a method to determine that a device is in a low power state; initiate a transition of the device from the low power state to an active state, where a fixed minimum recovery time is defined for transitions from the low power state to the active state; identify a capability of the device corresponding to transition of the device from the low power state to the active state; and complete transition of the device from the low power state to the active state based at least in part on the capability, where the transition is to be completed prior to expiration of the fixed minimum recovery time.
In at least one example, the capability includes an interrupt capability and an interrupt is to be received from the device, where the interrupt is an indication that the device is ready to complete the transition. The device can be monitored for the interrupt.
One or more examples can further provide that the transition is to be completed according to a defined recovery time for the device if the interrupt is not received prior to the defined recovery time.
In at least one example, the defined recovery time includes the fixed minimum recovery time. The defined recovery time can includes an advertised recovery time specific to the device.
In at least one example, the capability includes an advertised recovery time for the device, and the advertised recovery time is shorter than the fixed minimum recovery time.
In at least one example, the advertised recovery time can be applied to the transition of the device from the low power state to the active state instead of the fixed minimum recovery time.
In at least one example, the fixed minimum recovery time can be applied to another device in a transition of the other device from the low power state to the active state.
In at least one example, the device includes a Peripheral Component Interconnect Express (PCIe)-compliant device. The low power state can include a D3 state and the active state include a D0 state.
In at least one example, completing the transition of the device from the low power state to the active state is to include sending of a configuration access request to the device.
In at least one example, the device includes at least one of a root port, downstream port, or a root complex integrated end point.
One or more examples can further provide, machine readable memory storing a power management capability structure defining power management capabilities of at least one device; and a power management controller to identify a particular capability for the device from the power management capability structure, and complete transition of the device from a low power state to an active state based at least in part on the particular capability, where the transition is to be completed prior to expiration of a fixed minimum recovery time defined for transitions from the low power state to the active state.
In at least one example, the power management capability structure defines for the device, whether an alternate recovery time is advertised for the device.
In at least one example, the power management capability structure defines an alternate recovery time for the device that is shorter than the fixed minimum recovery time.
In at least one example, the power management capability structure defines for the device, whether an interrupt is supported by the device, and transition of the device from the low power state to the active state is completed based on receipt of the interrupt from the device.
In at least one example, the device is to be monitored for the interrupt if the power management capability structure indicates that the device supports the interrupt.
In at least one example, initiating the transition of the device from the low power state to the active state includes providing power to the device.
1. A high speed serial point-to-point link interface to enable communication between a processor and a device over a physical channel, the high speed serial point-to-point link interface comprising:
a transmitter to transmit serial data;
a receiver to deserialize serial data; and
control logic to implement a protocol stack, wherein the protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is maintained, and a second off state, in which the supply voltage is not to be provided to the device;
wherein the protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device;
wherein the protocol stack provides for accessing the device prior to expiration of the default recovery time to complete the transition based on a device-advertised recovery time; and
wherein the active state is an uninitialized active state and accessing the device prior to expiration of the default recovery time to complete the transition comprises sending a configuration access request to the device.
2. The serial point-to-point link interface of claim 1, wherein the protocol stack is a peripheral component interconnect express (PCIe) protocol stack and the device is a PCIe endpoint device.
3. The serial point-to-point link interface of claim 1, wherein the device-advertised recovery time is specified in a register of the device.
US14/757,924 2013-03-15 2015-12-24 Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints Active US10146291B2 (en)
US13/835,275 US20140281622A1 (en) 2013-03-15 2013-03-15 Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints
US14/757,924 US10146291B2 (en) 2013-03-15 2015-12-24 Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints
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ID=51534126
US13/835,275 Abandoned US20140281622A1 (en) 2013-03-15 2013-03-15 Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints
US14/757,924 Active US10146291B2 (en) 2013-03-15 2015-12-24 Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints
US14/998,158 Active US10139889B2 (en) 2013-03-15 2015-12-24 Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints
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