Source: http://www.google.com/patents/US7009243?dq=patent:5567455
Timestamp: 2014-03-14 00:17:37
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Patent US7009243 - Semiconductor memory device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel...http://www.google.com/patents/US7009243?utm_source=gb-gplus-sharePatent US7009243 - Semiconductor memory deviceAdvanced Patent SearchPublication numberUS7009243 B2Publication typeGrantApplication numberUS 10/985,946Publication dateMar 7, 2006Filing dateNov 12, 2004Priority dateSep 14, 2000Fee statusLapsedAlso published asUS6646300, US6825525, US20020096702, US20030141556, US20050087797Publication number10985946, 985946, US 7009243 B2, US 7009243B2, US-B2-7009243, US7009243 B2, US7009243B2InventorsTomoyuki Ishii, Kazuo YanoOriginal AssigneeHitachi, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (6), Classifications (28), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor memory deviceUS 7009243 B2Abstract A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.
a write transistor having a first source region, a first drain region, a first channel region of a semiconductor material formed on a first insulating film and connecting the first source region and the first drain region, a first gate insulating film formed over the first channel region, and a first gate electrode formed over the first gate insulating film;
a read transistor having a second source region, a second drain region, a second channel region located between the second source region and the second drain region, a charge storage region, a second gate insulating film formed over the second channel region, and a second gate electrode formed over the second gate insulating film; and
a peripheral circuit transistor having a third gate insulating film;
wherein the first gate electrode of the write transistor controls potential of the first channel region of the write transistor, and the second gate electrode of the read transistor controls potential of the second channel region of the read transistor,
wherein the second source region of the read transistor is connected to a source line, one of the first source or first drain regions of the write transistor is connected to the charge storage region of the read transistor, and the other of the first source or first drain regions of the write transistor is connected to a data line; and
wherein a thickness of the first gate insulating film is thickest among the first, second and third gate insulating film, and a thickness of the second gate insulating film is thicker than a thickness of the third gate insulating film.
2. The semiconductor memory device according to claim 1, wherein the charge storage region is located between the second gate insulating film and the second gate electrode.
3. The semiconductor memory device according to claim 1, wherein at least one of the first source and first drain regions of the write transistor are formed on the second gate insulating film.
4. The semiconductor memory device according to claim 1, wherein the first channel region of the write transistor is on a level corresponding to an upper end of at least one of the first source or first drain regions of the write transistor.
5. The semiconductor memory device according to claim 1, wherein a thickness of the first channel region of the write transistor is 5 nm or less.
6. The semiconductor memory device according to claim 1, wherein the first gate insulating film is formed between the first gate electrode and the first channel region,
wherein the first gate electrode and the second gate electrode are comprised of a common gate electrode,
wherein the charge storage region serves as a floating gate formed between the common gate electrode and the second channel region, and
wherein the second gate insulating film is formed between the charge storage region and the second channel region.
7. The semiconductor memory device according to claim 6, wherein the charge storage region is comprised of one of the first source or first drain regions of the write transistor.
CROSS-REFERENCE TO RELATED APPLICATIONS This is a Continuation of application Ser. No. 10/338,001, filed on Jan. 8, 2003, now U.S. Pat. No. 6,825,525 which is a Divisional of parent application Ser. No. 09/811,555, filed Mar. 20, 2001, now U.S. Pat. No. 6,646,300 the entire disclosures of which are hereby incorporated by reference.
A DRAM embedded chip integrally provided with a logic circuit and a DRAM (dynamic random-access memory) on a single chip has been developed to solve the_above-noted problem. Techniques relating to such a DRAM embedded chip are mentioned in H. Ishiuchi, et al., IEEE International Electron Devices Meeting, pp. 33�36 (1997). In view of the facility in integrating the components, an SRAM (static random-access memory) comprising memory cells of only logic transistors is preferable for use in a DRAM. However, since each memory cell of SRAM consists of six transistors, the memory cell needs a large cell area, and high cost makes it difficult to form an SRAM of a large capacity.
A proposed memory cell has been proposed which is called a gain cell. This structure is capable of operating even if the amount of stored charge of a DRAM cell is reduced. Charges are injected through a write transistor to a storage node and information can be read by virtue of the change of the threshold voltage of a read transistor caused by the stored charge for signal storage. Techniques relating to the present invention include a write transistor formed by polysilicon, mentioned in H. Shichijo, et al., Conference on Solid State Devices and Materials, pp. 265�268 (1984), a read transistor formed by polysilicon, mentioned in S. Shukuri, et al., IEEE International Electron Devices Meeting, pp. 1006�1008 (1992), and single-electron memories formed by polysilicon, mentioned in K. Yano, et al., IEEE International Electron Devices Meeting, pp. 541�544 (1993) and K. Yano, et al., IEEE International Solid-state Circuits Conferences, pp. 266�267 (1996). These techniques relate to memory devices that use a single cell for signal storage. Although different from the present invention in the principle of operation and function of the memory cell, those techniques include a general configuration called a TFT configuration having a channel which is thinner than a source and a drain; that is, the bottom of the source/drain region is substantially flush with the thin film channel region.
The reduction of the power consumption of devices, including battery-powered devices such as personal digital assistants, is an important problem. Generally, a semiconductor device consumes most of the power consumed by an apparatus including the semiconductor device, and, hence, the reduction of power consumption of the semiconductor device is required. The current of a transistor in an OFF status is called a leakage current. Since the leakage current is a matter that_can affect all the circuit elements on a chip, the current is one of factors of increasing power consumption of a whole semiconductor chip without distinction in case of as to whether the leakage current exists in a logic circuit or a memory circuit. Therefore, the reduction of power consumption of the semiconductor device is required. The inventors have found out that a TFT structure which includes a polycrystalline silicon base having a thin channel region causes a leakage current in the range of 10−18. However, in case of a FET structure in which the thickness of a channel region is thinner than the thickness of a source and/or drain region, the base height of a source and/or drain region is almost the same as the height of a channel thin film region. A gate insulator layer of this structure is deposited by CVD. Therefore, a step between a top surface of a source and/or a drain region and a top surface of a channel region causes a concentration of an electrical field at a top portion of the step. Therefore, a margin of dielectric strength is reduced when a gate insulation layer is thinner. Some parts of a gate insulating film are thick at the lower portion of the above-said step, and, hence, the performance of the transistor deteriorates and it is possible that the short channel effect can become remarkable.
First, when the logic fabricating processes and the DRAM fabricating processes have only a few processes in_common, many masks and steps are necessary, which increases manufacturing cost. A capacitor forming process, which is the most complicated process among those of fabricating the DRAM, cannot be used for forming the component of the logic circuit. Fast operation is an important capability of the logic circuit, and, hence, the diffusion layer of the MOS transistor of the logic circuit is silicided to reduce the resistance. However, if the diffused layer of the path transistor of the memory cell of the DRAM is silicided, leakage current increases and data retention time decreases greatly. Therefore, a region for the DRAM must be covered during a process for siliciding the diffusion layer of the logic circuit when forming MOS transistors for the circuit, which requires complicated processes.
FIGS. 1( a), 1(b) and 1(c) are, respectively, a typical fragmentary sectional view, a typical fragmentary plan view and a circuit diagram, respectively, of a semiconductor memory device in a first embodiment according to the present invention;
FIGS. 2( a) and 2(b) are views for explaining a method of fabricating the semiconductor memory device in the first embodiment;
FIGS. 3( a) and 3(b) are views for explaining a method of fabricating a write transistor included in the semiconductor memory device in the first embodiment;
FIGS. 4( a) and 4(b) are sectional views for explaining a method of processing a channel included in the semiconductor memory device in the first embodiment;
FIGS. 5( a) and 5(b) are views for explaining a method of fabricating the semiconductor memory device in the first embodiment;
FIGS. 6( a) and 6(b) are views for explaining a method of fabricating the semiconductor memory device in the first embodiment;
FIGS. 8( a) and 8(b) are views for explaining a method of fabricating the semiconductor memory 10 device in a second embodiment;
FIGS. 9( a) and 9(b) are sectional views for explaining a method of fabricating a memory cell included in the semiconductor memory device in the second embodiment;
FIGS. 10( a), 10(b) and 10(c) are sectional views for explaining a method of fabricating the semiconductor memory device in the second embodiment;
FIGS. 11( a), 11(b) and 11(c) are sectional views for explaining a method of fabricating the semiconductor memory device in the second embodiment;
FIGS. 12( a), 12(b) and 12(c) are sectional views for explaining a method of fabricating the semiconductor memory device in the second embodiment;
FIGS. 13( a) and 13(b) are top views for explaining a method of fabricating the semiconductor memory device in the second embodiment;
FIGS. 14( a) and 14(b) are top views for explaining a method of fabricating the semiconductor memory device in the second embodiment;
FIGS. 15( a) and 15(b) are top views for explaining a method of fabricating the semiconductor memory device in the second embodiment;
FIGS. 22( a) and 22(b) are typical sectional views of a semiconductor memory device in a third embodiment according to the present invention in different phases of the semiconductor memory device fabricating process;
FIGS. 28( a) and 28(b) are views for explaining the basic composition of a transistor included in a semiconductor memory device in a fifth embodiment according to the present invention;
FIGS. 29( a) and 29(b) are plan views for explaining the basic composition of a transistor included in the semiconductor memory device in the fifth embodiment;
FIGS. 30( a) and 30(b) are top views for explaining a method of fabricating a semiconductor memory device in a sixth embodiment according to the present invention; and
A semiconductor memory device in a first embodiment according to the present invention is formed on a semiconductor substrate. FIGS. 1( a), 1(b) and 1(c) are, respectively, a sectional view, a top view and a circuit diagram of an equivalent circuit of a memory cell included in the semiconductor memory device in the first embodiment. In FIG. 1( b), some parts of the overlapping outlines of regions are shifted relative to each other to facilitate understanding, and components shown in FIGS. 1( a) to 1(c) correspond with each other. FIG. 1( b) shows the positional relationship between the principal parts of the memory cell but does not accurately show layers.
The write transistor M2 is a thin-film FET. The concentration of impurities in the channel 3 of the FET is low, and the channel 3 is substantially intrinsic. Opposite end parts 1 and 2 of the channel 3 are connected to a laminated structure of an n-type polysilicon layer and a W layer (tungsten layer). The end part 1 is only connected to the channel 3 and is not connected to any other conductive path. The end part 1 serves as a charge storage region 4. The end part 1 corresponds to a part 1 c in the equivalent circuit diagram shown in FIG. 1( c). The other end part 2 is connected to a write data line 34. The end part 2 corresponds to a part 2 c in the equivalent circuit diagram. The laminated layer of the polysilicon layer and the W layer is the one prevalently used in the field of semiconductor technology. Preferably, the W layer of the laminated structure is in contact with the channel to utilize the low resistance of the W layer.
The end part 2 connected to the write data line 34 overlies an isolation region 10. The thickness of the channel 3 is, for example, 6 nm. A 7 nm thick gate insulating film 4 of SiO2 is formed over the channel 3, and a gate electrode 5 of a laminated structure consisting of a p-type polysilicon film and a W film is formed over the gate insulating film 4. The gate insulating film 4 consists of a first SiO2 layer which is formed over a second SiO2 layer 134. In FIG. 1( a), a dotted line indicates the boundary between the first and the second SiO2 layer. In other drawings, this laminated structure of the first and second SiO2 layers will be represented by a single insulating film for simplicity.
In FIG. 1( b), reference numerals 1 and 2 respectively indicate a source region or a drain region, and reference numerals 3 indicates a channel region.
The drain region 6 of the read transistor M1 is connected to a read data line 33 at a point 6 c in FIG. 1( c). A 6 nm thick insulating film 9 is formed between a charge storage part 1 and a silicon substrate 8. The insulating film 9 is an SiO2 film with a nitride treatment. The gate electrode 5 of the read transistor M1 also serves as the gate electrode of the write transistor M2. The gate electrode 5 is indicated at 5 c in FIG. 1( c). Although the read transistor M1 is an n-channel transistor in this embodiment, it may be a p-channel transistor instead. Although threshold voltage shifts when storing charges, and the sign and magnitude of the applied voltage change when the read transistor M1 is a p-channel transistor, the performance of the p-channel transistor is substantially the same as that of the n-channel transistor. The read transistors in this and other embodiments are n-channel transistors for simplicity, although p-channel transistors may be used instead.
When a voltage VWW is applied to the gate electrode 5 (5 c), the write transistor M2 turns on and a current flows through the channel 3 of the write transistor M2. Thus, an amount of charge dependent upon the predetermined potential of the write data line is stored in the charge storage part 1.
When a write data line and a read data line share the same line, the read transistor M1 turns on, and the set potential of the write data line becomes equal to that of the drain 6 (6 c) of the read transistor M1, and the potential of the channel of the read transistor M1 approaches the potential of the drain 6 (6 c) of the read transistor M1. Consequently, when a voltage corresponding to written data is set for the write data line, the potential difference between the charge storage part 1 and the channel of the read transistor M1 increases because the potential difference between the charge storage part 1 and the channel of the read transistor M1 increases when the data line is driven individually, and the potential of the write data line is fixed approximately at the potential of the source. Thus, the change of the signal amount in reading is increased and it is achieved to store information more stably.
A method of fabricating the semiconductor memory device in the first embodiment which has memory cells identical to the foregoing memory cell according to the present invention and is arranged in a matrix will now be described with reference to FIGS. 2 to 6. In FIGS. 2, 5 and 6, sectional views are on the left side and top views are on the right side. In each of the FIGS. 2, 5 and 6, the sectional view on the left side is taken on ine A�A in the top view on the right side. Those top views only show principal components relevant to the corresponding steps of the process and are not accurate top views. Each of the sectional views only shows a structure above a semiconductor layer in which active regions of the semiconductor memory device are formed. The semiconductor layer is formed in a semiconductor substrate or a SOI substrate. In FIGS. 2 to 6, the substrate is omitted for simplicity. In FIGS. 3( b), 4, 5 and 6, impurity regions formed in the substrate are omitted. Those regions can be understood from FIG. 3( a).
A p-type silicon substrate is subjected to ion implantation and annealing to form a triple well structure of an n-type well and a p-type well. As shown in FIG. 2( b), isolating grooves 12 filled with an insulating material are formed by using a masking pattern 11, shown in FIG. 2( a). The isolating grooves 12 are formed in regions that are not covered with the masking pattern 11. The masking pattern 11 corresponds to a plurality of memory cells.
The resist pattern is removed and the surface of the silicon substrate is oxidized to form a 3 nm thick gate insulating film for the logic circuit. The surface of this gate insulating film is nitrided to increase the dielectric constant of the gate insulating film, a polysilicon film for forming the gate electrodes is deposited, and the polysilicon film is doped with an impurity through a mask of a resist film. Then, a W film and an SiO2 film are deposited and gate electrodes 14 as shown in FIG. 2( b), are formed by using a resist pattern 13. The gate electrodes 14 are formed at substantially equal intervals to enable the use of resolution enhancement technology, such as phase-shift exposure.
A low-energy impurity implantation using a resist pattern and gate electrodes as a mask is performed to form a shallow diffusion layer 16 in the semiconductor substrate 8, as shown in FIG. 3( a). Then, an SiO2 film or an Si3N4 film is deposited, and the SiO2 film or the Si3N4 film is 10 subjected to anisotropic etching to form side walls 15 on the side surfaces of the gate electrodes 14. Then, an impurity implantation is performed by using a resist pattern and the gate electrodes 14 coated with the side walls 15 as a mask to form diffusion layers 17, as shown in FIG. 3( a).
Subsequently, an SiO2 film 300 is deposited and is polished by a chemical mechanical polishing process (CMP process) so that the surface of the SiO2 film 300 is flush with the upper ends of the gate electrodes 14, as shown in FIG. 3( b). In FIG. 3(B) portions of the SiO2 film 300 remaining after the CMP process are shown. FIG. 3( c) is a top view of the principal parts after CMP.
The semiconductor substrate thus processed is then cleaned. Next, an 8 nm thick amorphous silicon film 18 and a 5 nm thick SiO2 film 19 are deposited in that order on the semiconductor substrate. The SiO2 film 19 and the amorphous silicon film 18 are etched in a pattern shown in FIG. 4( b) by dry etching, using a resist pattern 20 shown in FIG. 4( a). The resist pattern 20 is formed by using a mask 23 of a pattern shown in FIG. 5( b).
Then, an SiO2 film 25, a p-type polysilicon film, a W film and an SiO2 film 27 are deposited. Dry etching using a resist pattern 23 is performed to form word lines 26, as shown in FIG. 5( b). The word lines 26 are formed by etching a laminated film consisting of the p-type polysilicon film and the W film. The p-type polysilicon film is used to create a positive threshold voltage in the write transistors. The word lines 26 serves also as the gate electrodes of the read and write transistors. The thickness of the SiO2 film 27 overlying the word lines 26 is sufficiently thicker than the gate insulating film 25 of the transistors.
The SiO2 film is etched by dry etching using a mask of a resist having a pattern 28 of openings as shown in FIG. 6( b). Even when the parts 29 of the SiO2 film that are not overlapping the word lines 26 are etched as deeply as the gate electrodes 14 are exposed, the parts of the SiO2 film 27 overlying the word lines remain. When etching the gate electrodes 14 thereafter, the etch selectivity between the parts of the SiO2 film 27 overlying the word lines and the gate electrodes 14 is sufficiently large. FIG. 6( c) is a sectional view of the parts not overlying the word lines 26. Parts 29 and 32 of the gate electrodes 14 not overlying the word lines 26 are not etched, and charge storage regions 30 not having any discharging paths other than the channels 21 of the write transistors are formed. The adjacent gate electrodes 31 are not cut in this way, and they extend perpendicularly to the paper. The gate electrodes 31 serve as the data lines of the write transistors. Since the films are processed by self-alignment processes, the widths of the channels 21 of the write transistors and the charge storage regions 30 are substantially equal to that of the word lines 26. Subsequently, a wiring process is performed to form desired wiring lines.
VD1 �1�
VD1 �1� VD0
line 1 (DW1)
VD0 �0�
~VPC
line 1 (DR1)
FIG. 8( a) is a typical sectional view of a memory cell included in a semiconductor memory device in the second embodiment according to the present invention, and FIG. 8( b) is a top view of the memory cell shown in FIG. 8( a). The memory cell of the second embodiment is basically the same in configuration as the memory cell of the first embodiment, except that the memory cell of the second embodiment is formed on a SOI substrate (silicon-on-insulator substrate). Hence, the gate electrode of the read transistor of the memory cell of the second embodiment, the method of forming the gate electrode of the read transistor, and the thickness of a film forming the channel of the write transistor of the memory cell of the second embodiment are different from those of the memory cell of the first embodiment. Many processes for fabricating the logic circuit of the second embodiment can be used also for fabricating the memory cells of the second embodiment, and only a few additional processes need to be added to fabricate the memory cells. The leakage current from the write transistor of the memory cell of the second embodiment is less than that from the write transistor of the memory cell of the first embodiment, and the storage device of the second embodiment has an excellent data retention characteristic.
Shown in FIG. 8 is a SOI substrate having a semiconductor substrate 400 and an insulating film 48 formed on the substrate 400. Active regions of a semiconductor device are formed on the SOI substrate. Also shown in FIG. 8 are isolation regions 41 and 42, a semiconductor region 43, deep diffusion layers 44 and 45, 10 shallow diffusion regions 47, an insulating film 40, which also serves as a gate insulating film of one of FET5, regions 35, 36 and 38 for forming drain and source regions, a channel region 37, an insulating film 300, an insulating film 39 and a conductive layer 46. Preferably, the regions 35, 36 and 38 for forming drain and source regions are laminated layers of a metal layer and a polysilicon layer, such as a laminated layer of a W layer and a polysilicon layer. Also, the metal layer is preferably formed on the side of the channel layer. In FIG. 8, each of the laminated layers 35, 36 and 38 is represented by a single layer. These laminated layers can be used in other embodiments.
The isolation regions 41 and 42 are formed in the silicon layer 43 which is formed on the buried insulating film 48, which is then formed on the SOI substrate 400. Then, a gate insulating film 50 and dummy gate parts 49 of Si3N4 having the shape of a dummy gate electrode are formed. The diffused regions 47 are formed by ion implantation using the dummy gate parts 49. Side walls 51 are formed on the side surfaces of the dummy gate parts 49. The source region 45 and the drain region 44 are formed by ion implantation. Thus, the structure shown in FIG. 8( a) is fabricated. The side walls are formed by a process similar to that by which the side walls of the first embodiment are formed. FIG. 8( b) corresponds to FIG. 1( b). An insulating film 310 is deposited on the thus prepared workpiece, and the insulating film 310 is polished by a CMP process until the upper surfaces of the dummy gates 49 are exposed, as shown in FIG. 9( b).
The state shown in FIG. 10( a) is the same as that shown in FIG. 9( b). In FIG. 10( a), a region for the memory cells and peripheral circuits is shown on the left side and a region for a logic circuit is shown on the right side. In FIGS. 10, 11 and 12, doped regions in the substrate are omitted. Those regions can be well understood from FIG. 9( a).
The dummy gates 49 are removed as shown in FIG. 10( b), and a resist film 55 is formed in the region for the logic circuit as shown in FIG. 10( c). Portions of the gate insulating film 50 for the read transistors of the memory cells and the transistors of the peripheral circuit are removed by etching, using the resist film 55 as a mask, as shown in FIG. 10( c). Portions for the storage nodes of the memory cells and the gates of the MOS transistors of the peripheral circuit in the surface 53 of the semiconductor region 43 are exposed, while isolation regions are exposed in portions in which write data lines are to be formed.
Another gate insulating film 57 for the peripheral circuit is formed and a resist film 56 is formed, over the region for the peripheral circuit. Dummy gate insulating film corresponding to a portion 58 for the transistors of the logic circuit is removed as shown in FIG. 11( a).
A gate insulating film 59 for the transistors of the logic circuit, as shown in FIG. 11( b), and then a metal film 60, such as a W film, are deposited on the thus constructed workpiece, as shown in FIG. 11( c). Then, the metal film is subjected to a CMP process to form gate electrodes in portions corresponding to grooves in which dummy gates were formed, as shown in FIG. 12( a). The write data line 70 for the memory cells and a gate electrode 72 for the transistors of the logic circuit and the peripheral circuit are also formed by the CMP process, as shown in FIG. 13( a), in which the gate electrode is formed on the left side of the data line 70. FIG. 12( a) is a sectional view taken on line C�C′ in FIG. 13( a), and FIG. 12( b) is a sectional view taken on line D�D′ in FIG. 13( b).
A very thin amorphous silicon film (a-Si film) 61 of 20 a thickness on the order of 3 nm is deposited to form the channels of the write transistors, and then a 10 nm thick SiO2 film 62 is deposited. Then, as shown in FIG. 12( b) the SiO2 film 62 and the a-Si film 61 are etched by an etching process using a mask 65, shown in FIG. 13( b), which is formed by patterning a resist film.
A gate insulating film for the write transistors is formed, and the diffused layers for the transistors of the logic circuit and the peripheral circuit, the contact holes for gates, the diffused layers for the read transistors of the memory cells, the write data lines, the read data lines, and the contact holes 66 for the source lines are formed by using resist masks. FIG. 14( a) shows the arrangement of the contact holes 66, the isolation regions 41 and 42, and a region 72 in which the contact holes are formed.
After removing the resist mask, a metal film 64 is deposited so as to fill up the contact holes and an insulating film 64 a is formed over the metal film 64. The insulating film 64 a and the metal film 64 are processed by using a mask which is formed by patterning a resist film to form word lines 67 a for the memory cell array and wiring lines 67 b for the logic circuit and the peripheral circuit. Source lines for the memory cell array are formed in this layer, as shown in FIG. 12( c). Patterns thus formed are shown in FIG. 14( b).
Subsequently, an etching process using a patterned photoresist film as a mask for forming a hole pattern 68 and using the word lines 67 a of the memory cells as a mask is performed to form charge storage parts 69 and the channels 161 of the write transistors. In FIG. 15( b), the word lines 67 a are indicated by broken lines because the patterns of the word lines 67 a, channels and the charge storage regions overlap each other in a self-alignment process. Since the regions for the logic circuit and the peripheral circuit are masked, they are not etched.
Subsequently, an insulating film is deposited and flattened. This insulating film serves as a layer of insulating film between the first wiring layer and a second wiring layer. Then, as shown in FIG. 18, through holes 84 and 85 are formed by using a mask formed by patterning a resist film. Then, a conductive film of a conductive material, such as a metal, is deposited over the insulating film so as to fill up the through holes 84 and 85, and the conductive film is processed by using a mask formed by patterning a resist film to form wiring lines of the second wiring layer. The conductive material filing up the through holes interconnects the first and the second wiring layer. The write data lines 86 and the read data lines 87 are wiring lines formed in the second wiring layer. The diffused wiring line 71 of the semiconductor base is used as a read data line. The diffused wiring line 71 is thin and narrow, and, hence, has a high resistance. Therefore, in the second embodiment, the diffused wiring line 71 is lined with a metal wiring line to form a laminated wiring line having a low resistance. FIG. 18 is a plan view of the second wiring layer of the semiconductor memory device, and FIG. 27 is a sectional view of the memory cell of the same semiconductor memory device. In the second wiring layer, write data lines 150 and a read data line 151 are extended parallel to each other. Although a wiring line 153 is shown in a sectional view of a logic circuit part shown on the right side in FIG. 27, the shape of the section is dependent on a wiring pattern. Although a similar wiring line 86 is formed for the write data line 76 in the second embodiment, the wiring line 86 may be omitted and only wiring lines of the gate electrode layer may be used to arrange the data lines of the second wiring layer at increased pitches and to form the memory cell array in a smaller area (FIG. 18). As shown in FIG. 28, when the write data lines 151 are omitted, the width and pitches of the read data line 151 can be increased accordingly.
In the first and second embodiments, the drain regions of the plurality of read transistors are connected by the diffused layer. In the third embodiment, memory cells are connected to contacts 113, respectively, and the contacts 113 are connected to a read data line 109, included in an upper wiring layer. The two memory cells share the one contact 113. Although the area of a region in which memory cells are arranged is small when a diffused layer is used, source lines 114 having a small parasitic resistance and permitting quick access are connected by a diffused layer and are extended parallel to word lines 106.
FIGS. 22 to 24 are views for explaining the third embodiment. FIGS. 22( a) and 22(b) are typical sectional views, FIG. 23 is a top view of the memory cell array of the third embodiment, and FIG. 24 is a circuit diagram of an equivalent circuit of the memory cell array of the third embodiment. FIG. 22( a) is a sectional view taken on line L�L′ in FIG. 23, and FIG. 22( b) is a sectional view taken on line M�M′ in FIG. 23. FIG. 23 shows a part 115 enclosed by the continuous lines shown in FIG. 24.
Referring to FIG. 22( a), isolating regions 108 are formed in a semiconductor substrate. FETs having channels of a polysilicon thin film are formed on the isolating regions 108. Doped regions 104 and 105 underlie a polysilicon thin film 103. Word lines 106 are formed on an insulating film covering the polysilicon thin film 103. The polysilicon thin film 103 forms the channel regions of the transistors. A read data line 109 is formed in an upper wiring layer mentioned in connection with FIG. 22( b). The read data line 109 is connected through a contact 113 to a doped semiconductor region.
VD1 (0, 1)
VD2 (1, 1)
VD3 (0, 0)
VD4 (1, 0)
VPC-Δ′
The fourth embodiment stores two bits in one memory cell. When data sets (0, 1), (1, 1), (0, 0) and (1, 0) to be written to a write data line are represented by voltages VD1, VD2, VD3 and VD4, respectively, where VD1, VD2, VD3,VD4, the order of the threshold voltages of the read transistor is opposite to that of the set voltages for the write data line, as shown in FIG. 25. FIG. 25 shows the relation between the word line voltage and the drain current of a read transistor. VDR, VPC, VWW, VW0, VW1, VWR1, VWR2 and VWR3 denote data line voltage, precharge voltage, write' voltage, holding voltage, word line voltage of a nonselected memory cell, first read voltage, second read voltage and third read voltage, respectively.
A read operation for reading information from the memory circuit will now be explained. An I/O interface generates a row address 117, a column address 118, and a high-order/low-order bit selection signal 135 for a requested address signal 116. Two-bit information is stored in a memory cell specified by the given row address 117 and the given column address 118. This is stored in registers 1 and 2 by the aforesaid read procedure. Subsequently, an up/down change circuit 133 performs selection according to the high-order/low-order bit selection signal 135 to provide output data 126. A data storing operation for storing data in the memory circuit will now be described. The I/O interface generates a row address 117, a column address 118, and a high-order/low-order bit selection signal 135 according to a given address signal 116. A row decoder 132 performs a read operation for reading a selected row. The result is stored in the registers 1 and 2. Then, input data 124 is held by the register connected to a data line 129 selected by the row decoder 122. The up/down change circuit 133 selects either the register 1 or the register 2 according to the high-order/low-order bit selection signal 135. The register to which any information is written at this stage holds the information. A voltage for the write data line 130 is set on the basis of the information stored in the register 1 119 and the register 2 120, and a write pulse is given to the word line 128 for writing. Thus, only one of the two bits stored in one memory cell 131 can be rewritten.
A fifth embodiment according to the present invention employs transistors using a semiconductor thin film, such as polysilicon film. The transistor of the fifth embodiment is basically similar to the write transistors of the foregoing embodiments. The fifth embodiment is featured by the arrangement of a source 200, a drain 201 and a channel layer. FIGS. 28( a) and 28(b) are, respectively, a typical sectional view and a top view of an essential part of a semiconductor memory device in the fifth embodiment.
A transistor is formed on an insulating film 206 which is formed on, for example, an SOI substrate. A source region and a drain region are 60 nm thick polysilicon layers, and a channel 202 is a 5 nm thick intrinsic polysilicon thin film. A gate electrode is formed from a laminated structure of a p-type polysilicon layer and a W layer. A gate insulating film 204 is an 8 nm thick SiO2 film. Preferably, the polysilicon thin film is formed of intrinsic crystals. In most cases, the impurity concentration of the polysilicon thin film is 1�1017/cm3, and preferably, 1�1015/cm3.
A gate electrode 203 is formed on a gate insulating film 204. In FIG. 28( b), a part of a channel layer 202, forming a channel shown in FIG. 28( a), is denoted by a reference numeral 202.
FIGS. 29 to 31 are views for explaining a method of fabricating a memory cell array in a sixth embodiment according to the present invention, in which parts enclosed by broken lines are unit structures each including two memory cells of the memory cell array. The unit structures are arranged in rows parallel to an X-direction, and in columns parallel to a Y-direction to form the large-scale memory cell array. The sixth embodiment is featured by a method forming channels and is effective in reducing the thickness of a gate insulating film and enhancing reliability.
The construction will be described in connection with the steps of fabricating the memory cell array. A p-type silicon substrate is used. After accomplishing sacrifice oxidation, a deep n-type well is formed by a high-energy ion Implantation process or a long annealing process. A groove is formed in an isolating region 207, an insulating film is deposited in the groove, and the insulating film is polished flat. After repeating the sacrifice oxidation, an ion implantation process and an annealing process are performed to form p-type wells. The p-type wells are electrically separated from the p-type substrate by the n-type well. Thus, the p-type wells can be set at different potentials, respectively. The surface of the substrate is oxidized to form a gate insulating film for read transistors, and then an n-type polysilicon film is deposited. The source and the drain of a write transistor are formed by processing the n-type polysilicon film. The n-type polysilicon film is etched by using a mask of a resist film provided with an opening 208 in a pattern to remove parts of the n-type polysilicon film corresponding to the openings (FIG. 29( a)). The width of the groove determines the channel length of the transistor.
After depositing and flattening an insulating film, an amorphous silicon thin film for forming channels is deposited. An insulating film that serves as the gate insulating film of the write transistors is deposited on the amorphous silicon thin film, a p-type polysilicon film for forming the gate electrodes of the write transistors is deposited, and the p-type polysilicon film is 5 subjected to activate the impurity. A pattern 210 of the gate electrodes of the write transistors is formed in a mask of a resist film. Then, the p-type polysilicon film for forming the gate electrodes, the insulating film for insulating the gates of the write transistors, the amorphous silicon thin film, and the n-type polysilicon film are etched by using the mask (FIG. 29( b)). Channels for the write transistors are formed in parts 211 where the opening 208 of the mask and the pattern 210 of the mask overlap each other. An n-type impurity is implanted by using the gate pattern of the write transistors to form an extension region. Then, a Ti film (titanium film) is deposited on the surface of the substrate and the Ti film is annealed to reduce the resistance of the surface of the substrate. Subsequently, the gate electrodes are etched partly by using a pattern 212 of an opening to separate the respective gate electrodes of the two adjacent memory cells, while the gate insulating film for the write transistors and the n-type polysilicon film are not etched. Processing the amorphous silicon thin film is not performed before depositing the gate insulating film for the write transistors. Therefore, an insulating film for protecting the amorphous silicon thin film may be omitted.
In other embodiments, the protective film is damaged by a channel processing process, and, hence, another gate insulating film is formed. In the sixth embodiment, only a single insulating film is necessary. Since the insulating film is not damaged, it can be thin, which is effective in reducing the write transistor operating voltage and improving performance. Then, an insulating film is deposited and flattened, and contact holes are formed in the insulating film by using a mask of a resist film (FIG. 30( a)). A contact hole 215 in the drain region of the read transistor shared by two memory cells, a contact hole 213 in the drain region of the write transistor shared by two memory cells, a contact hole 214 which opens to the gate for both the write and the read transistor, contact holes for a peripheral circuit, and the gates of a logic circuit a and diffused regions can be simultaneously formed. The read transistors of two memory cells have source regions 220 and 221, respectively, and are wired in the X-direction by a diffused layer wiring line having a surface layer of titanium silicide. A metal film, such as a W film, is deposited and the metal film is processed by using a mask of a resist film to form metal wiring lines for a first layer (FIG. 30( b). Word lines 216 are formed by the metal wiring lines, and a gate for both the write and the read transistor of each memory cell is extended in the X-direction. A pad 217 connected to the drain of the read transistor and a pad 222 connected to the drain of the write transistor are formed by processing the metal film. Then, an insulating film is deposited and flattened, and a second metal film is deposited and processed by using a mask of a resist film provided with openings 218 and 224 to form wiring lines of a second wiring layer (FIG. 31). The second metal film is processed to form a read data line 219 and a write data line 223 in order to extend in the Y-direction. Generally, a small current flows through the write transistor for charging and discharging a small capacity. The write data line 223 may be thinner than the read data line 219.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5753946Feb 12, 1996May 19, 1998Sony CorporationFerroelectric memoryUS6100954Mar 25, 1997Aug 8, 2000Lg Electronics Inc.Liquid crystal display with planarizing organic gate insulator and organic planarization layer and method for manufacturingUS6218245Nov 24, 1998Apr 17, 2001Advanced Micro Devices, Inc.Method for fabricating a high-density and high-reliability EEPROM deviceUS6376316Dec 9, 1998Apr 23, 2002Hitachi, Ltd.Method for manufacturing semiconductor integrated circuit device having deposited layer for gate insulationJP2000279525A Title not availableReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7697365 *Jul 13, 2007Apr 13, 2010Silicon Storage Technology, Inc.Sub volt flash memory systemUS7859889 *Aug 5, 2008Dec 28, 2010Renesas Electronics CorporationSemiconductor memory deviceUS8018773 *Mar 4, 2009Sep 13, 2011Silicon Storage Technology, Inc.Array of non-volatile memory cells including embedded local and global reference cells and systemUS8072815Dec 10, 2010Dec 6, 2011Silicon Storage Technology, Inc.Array of non-volatile memory cells including embedded local and global reference cells and systemUS8456904Jun 29, 2011Jun 4, 2013Silicon Storage Technology, Inc.Sub volt flash memory systemUS8576620Nov 12, 2010Nov 5, 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and driving method thereof* Cited by examinerClassifications U.S. Classification257/315, 257/320, 257/316, 257/E27.026, 257/E27.103, 257/317, 257/319International ClassificationH01L27/108, H01L27/10, H01L21/8242, B82B1/00, G11C11/405, G11C11/404, H01L27/115, H01L27/06, H01L29/788Cooperative ClassificationH01L27/1156, H01L27/11551, H01L27/115, G11C11/404, G11C11/405, H01L27/0688European ClassificationG11C11/405, H01L27/115F10, H01L27/115F16, H01L27/06E, H01L27/115, G11C11/404Legal EventsDateCodeEventDescriptionApr 27, 2010FPExpired due to failure to pay maintenance feeEffective date: 20100307Mar 7, 2010LAPSLapse for failure to pay maintenance feesOct 12, 2009REMIMaintenance fee reminder mailedRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google