Source: http://www.google.com/patents/US20020024088?dq=5,742,768
Timestamp: 2015-05-07 04:22:29
Document Index: 394645279

Matched Legal Cases: ['art 6', 'art 7', 'art 8', 'art 7', 'art 6', 'art 8', 'art 6', 'art 6', 'art 7', 'art 8', 'art 7', 'art 8', 'art 6', 'art 6', 'art 7', 'art 8', 'art 7', 'art 8', 'art 6', 'art 6', 'art 7', 'art 6', 'art 6', 'art 7', 'art 8', 'art 6', 'art 6', 'art 6', 'art 7', 'art 8', 'art 7', 'art 8', 'art 6', 'art 6', 'art 6', 'art 6', 'art 7', 'art 7', 'art 6', 'art 6', 'art 7', 'art 7', 'art 7', 'art 8', 'art 7', 'art 8', 'art 7', 'art 8', 'art 6', 'art 7', 'art 8', 'art 6', 'art 6', 'art 7', 'art 8', 'art 6', 'art 6', 'art 6']

Patent US20020024088 - Non-volatile semiconductor memory device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsIn the non-volatile semiconductor memory device of the present invention, its memory region comprises a number of erasable, writable and readable memory blocks in which these functions can be carried out simultaneously. According to the present non-volatile semiconductor memory device, since the memory...http://www.google.com/patents/US20020024088?utm_source=gb-gplus-sharePatent US20020024088 - Non-volatile semiconductor memory deviceAdvanced Patent SearchPublication numberUS20020024088 A1Publication typeApplicationApplication numberUS 09/931,109Publication dateFeb 28, 2002Filing dateAug 17, 2001Priority dateAug 30, 2000Also published asUS6563734Publication number09931109, 931109, US 2002/0024088 A1, US 2002/024088 A1, US 20020024088 A1, US 20020024088A1, US 2002024088 A1, US 2002024088A1, US-A1-20020024088, US-A1-2002024088, US2002/0024088A1, US2002/024088A1, US20020024088 A1, US20020024088A1, US2002024088 A1, US2002024088A1InventorsMasamitsu TakiOriginal AssigneeMasamitsu TakiExport CitationBiBTeX, EndNote, RefManReferenced by (5), Classifications (12), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetNon-volatile semiconductor memory device
DETAILED DESCRIPTION OF THE INVENTION [0070] Although the Examples of the present invention is hereinafter explained in detail with referring to FIGS. 1-6, the present invention is never limited to the Examples described below. EXAMPLE [0071] Constitution of the non-volatile semiconductor memory device in accordance with the present invention [0072]FIG. 1 shows a block diagram representing the Example of the present invention. [0073] A non-volatile semiconductor memory device (IC) 1 comprises a control signal 2 to be entered from the outside, data 3, an address 4, and a power supply 5. A command analyzing and status data generating part 6 analyzes a command entered as data 3, and controls the whole of IC 1. [0074] The IC 1 further comprises an erase control part 7 and a write control part 8. A status signal 7 a communicates that the erase control part 7 is busy to the command analyzing and status data generating part 6. A status signal 8 a communicates that the write control part 8 is busy to the command analyzing and status data generating part 6. [0075] A bus 9 transmits an address signal, a data signal, a control signal and a start request signal for an erase or write operation from the command analyzing and status data generating part 6, data to be read and a memory block status signal from the memory block. A bus 9 d connects the bus 9 to the erase control part 7, and a bus 9 e connects the bus 9 to the write control part 8. [0076] Memory blocks 10 a�10 c are composed of a row decoder, a column decoder, a sense amplifier and an memory array cell. [0077] Latch circuits 11 a�11 c temporarily memorize a memory block status sent via the buses 12 a�12 c from the memory blocks 10 a�10 c which are selected by a partition selecting information sent via a bus 21 described below. 34 The buses 12 a�12 c connect the memory blocks 10 a�10 c, the latch circuits 11 a�11 c, and selector circuits 13 a�13 c. [0078] The selector circuits 13 a�13 c transmit any of signals form the bus 9, a bus 14 for erasing, or a bus 15 for writing to the memory blocks 10 a�10 c which are selected by a partition selecting information sent via the bus 21 described below. [0079] The bus 14 is for erasing, and transmits each of an address signal, a data signal and a control signal from the erase control part 7 to the memory blocks 10 a�10 c. [0080] The bus 15 is for writing, and transmit each of an address signal, data signal and control signal from the write control part 8 to the memory blocks 10 a�10 c. [0081] An address bus 16 directs a memory block in which data are erased, written or read. [0082] A partition latch circuit 18 holds information indicating to which partition each of the memory blocks belongs (hereinafter, referred to as �partition division information�). [0083] The bus 17 is a bus for writing the partition division information to the partition latch circuit 18 when the control signal 2, the data 3, and the address 4 received by the command analyzing and status data generating part 6 are a command to write to the partition latch circuit 18. [0084] A bus 19 outputs the partition division information held in the partition latch circuit 18. [0085] A partition selector circuit 20 selects a partition including one memory block directed by the address bus 16 from the address bus 16 and the partition division information bus 19 to make all the memory blocks included in the partition to be in a selected state. [0086] A bus 21 is outputted from the partition selector circuit 20, and sends the partition selection information indicating all the memory blocks in the selected state included in one partition. [0087] A method for selecting memory blocks, as well as erase and write controls [0088] First, a method for selecting memory blocks in a partition at writing, erasing and reading is explained. [0089] The command analyzing and status data generating part 6 receives a control signal 2, data 3 and an address 4 from the outside, and analyzes a function to be carried out and a memory block to be selected. The analyzed information is sent to the erase control part 7 or the write control part 8 via the bus 9. The erase control part 7 or the write control part 8 transmits an erase signal or a write signal to the selector circuits 13 a�13 c via the bus 14 or the bus 15 according to the analyzed information. [0090] The partition latch circuit 18 holds the partition division information sent from the command analyzing and status data generating part 6 via the bus 17. [0091] The partition selector circuit 20 sends a partition selection information which is a signal to select all the memory blocks in the partition to which the selected memory block belongs according to the address information sent from the command analyzing and status data generating part 6 via the bus 16 to select one memory block and the partition division information sent from the partition latch circuit 18 via the bus 19, to the selector circuits 13 a�13 c via the bus 21. [0092] 1. A method for selecting a memory block [0093] An embodiment of the method for selecting all the memory blocks included in a partition is explained using FIG. 2. [0094] A partition comprises a plurality of sets, each set being composed of a memory block, and a latch circuit and a selector circuit connected to the memory block. [0095]FIG. 2 shows a case where two partition are set. Specifically, memory blocks 0, 1 and 2 constitute a Partition 0, and memory blocks 3 and 4 constitute a Partition 1. [0096] In FIG. 2, since the constituents indicated with the same symbols as those in FIG. 1 are the same as or equivalent to the constituents in FIG. 1, only different constituents from FIG. 1 are described below. [0097] Memory blocks 10 a�10 e are composed of a row decoder, a column decoder, a sense amplifier and an memory array cell (not shown). [0098] Buses 12 a�12 e connect the memory blocks 10 a�10 e to latch circuits 11 a�11 e, and selector circuits 13 a�13 e. [0099] The selector circuits 13 a�13 e transmit any of signals form the bus 9, a bus 14 for erasing, or a bus 15 for writing to all of the memory blocks (here, 10 a�10 c) which are selected by a partition selecting information sent via the bus 21. [0100] The bus 14 is for erasing, and transmits each of an address signal and a control signal to be transmitted to the memory blocks 10 a�10 e from the erase control part 7. [0101] First, if the control signal 2, the data 3 and the address 4 are a command to write to the partition latch circuit 18, the command analyzing and status data generating part 6 writes them to the partition latch circuit 18 as partition division information. The partition division information set in the partition latch circuit 18 is further sent to the partition selector circuit 20 via the bus 19. [0102] Below, such a case is considered where the partition division information thus sent to the partition selector circuit 20 instructs to constitute one partition with memory blocks 0, 1 and 2 (i.e., 10 a�10 c) and latch circuits 11 a�11 c and selector circuits 13 a�13 c which are connected to them, to constitute another partition with memory blocks 3 and 4 (i.e., 10 d and 10 e ) and latch circuits 11 d�11 e and selector circuits 13 d�13 e which are connected to them, and the address information sent via the bus 16 to select one memory block directs the memory block 1. [0103] As described above, a partition comprises a plurality of sets, each set being composed of a memory block, and a latch circuit and a selector circuit connected to the memory block, but hereinafter, a partition constitution is represented by a memory block included therein for simplicity. [0104] The partition selector circuit 20 judges that the memory block 1 constitutes a partition together with the memory blocks 0 and 2 from the partition division information entered, to send a partition selection information instructing to make the memory blocks 0 and 1 which are included in the same partition including the memory block 1 to be in the selected state via the bus 21. [0105] Similarly, when the address information sent via the bus 16 to select one memory block directs to the memory block 3, the partition selector circuit 20 judges that the memory block 3 constitutes a partition together with the memory block 4 from the partition division information entered, to send a partition selection information instructing to make the memory block 4 which is included in the same partition including the memory block 3 to be in the selected state via the bus 21. [0106] In this way, based on a first memory block in which data are erased, written or read, all the memory blocks included in the same partition which includes the first memory block can be selected by a command (data), an address, a control signal, to make the whole partition to be in the selected state. [0107] 2. Erase and write control [0108] Next, an erase operation and a write operation are explained in memory blocks included in the above selected partition. [0109] In FIG. 1, the command analyzing and status data generating part 6 receives a control signal 2, data 3 and an address 4 from the outside, and analyzes a function to be carried out and a memory block in which the function is carried out. The analyzed information is sent to the erase control part 7 or the write control part 8 via the bus 9 d or 9 e depending on whether the function to be carried out is erasing or writing. [0110] Herein, such a case is considered where the Partition 0 consisting of memory blocks 0, 1 and 2 (i.e., 10 a�10 c) is selected by the partition selection information. [0111] The selector circuits 13 a�13 c select either an erase or write operation start request signal generated by the command analyzing and status data generating part 6, and transmits the selected operation start request signal to all the memory blocks included in the partition selected by the partition selection information sent via the buses 12 a�12 c from the partition selector circuit 20 via the bus 21. [0112] When all the memory blocks included in the partition selected by the partition selection information sent from the partition selector circuit 20 via the bus 21 receive an erase or write operation start request signal, they send memory block status information indicating on the erase or write operation to the latch circuits 11 a�11 c via the buses 12 a�12 c. [0113] The latch circuits 11 a�11 c hold the memory block status information sent via the buses 12 a�12 c. The held information is sent to the command analyzing and status data generating part 6 and the selector circuits 13 a�13 c via the bus 9 (9 a�9 c), the command analyzing and status data generating part 6 recognizes that the erase control part 7 or the write control part 8 is on an operation, and the selector circuits 13 a�13 c select either the erase or write control signal transmitted from the erase control part 7 or the write control part 8 based on the memory block status information indicating on the held erase or write operation, to send it to the memory block via the bus 12 (12-12 c). This process is continued until the erase or write operation is completed. [0114] A method for carrying out erasing, writing and reading simultaneously [0115] Next, using FIG. 3, an embodiment of a method is explained for carrying out at the same time an erase, write or read operation independently by a partition. [0116]FIG. 3 describes in detail the Partition 0 consisting of the memory blocks 0, 1 and 2. In FIG. 3, since the constituents indicated with the same symbols as those in FIG. 1 are the same as or equivalent to the constituents in FIG. 1, only different constituents from FIG. 1 are described below. [0117] Buses 12 aa, 12 ba and 12 ca connect the latch circuits 11 a�11 c and the memory blocks 10 a�10 c, respectively. Buses 12 ab, 12 bb and 12 cb connect the selector circuits 13 a�13 c and the memory blocks 10 a�10 c, respectively. [0118] As explained in FIG. 2, when the control signal 2, the data 3 and the address 4 are a command for writing to a partition latch circuit 18, the command analyzing and status data generating part 6 writes them to the partition latch circuit 18 as partition division information. [0119] Below, such a case is considered that memory blocks 0, 1 and 2 constitute one partition (partition 0) according to the partition division information, and the memory blocks 0, 1 and 2 constituting the partition 0 are in the selected state according the partition selection information sent via the bus 21 (21 a�21 c). [0120] The command analyzing and status data generating part 6 receives the control signal 2, the data 3 and the address 4 from the outside, and analyzes a function to be carried out and a memory block in which the function is carried out. [0121] 1. Erase and write operations [0122] The case where the function to be carried out is an erase operation is explained. [0123] First, an erase operation start request signal is transmitted to the selector circuits 13 a�13 c via the buses 9 a�9 c. Since the memory blocks 0, 1 and 2 constituting the partition 0 are selected according to the partition selection information sent via the bus 21 (21 a�21 c), the selector circuits 13 a�13 c receive the erase operation start request signal, and transmit the signal to the memory blocks 10 a�10 c via the buses 12 ab, 12 bb and 12 cb. [0124] When the memory blocks 10 a�10 c have received the erase operation start request signal, they start the erase operation, and send memory block status information indicating on an erase operation to the latch circuits 11 a�11 c via the buses 12 aa, 12 ba and 12 ca. [0125] The latch circuits 11 a�11 c hold the memory block status information indicating on the erase operation, which has been sent via the buses 12 aa, 12 ba and 12 ca. The saved memory block status information indicating on the erase operation is sent to the command analyzing and status data generating part 6 and the selector circuits 13 a�13 c via the bus 9 (9 a�9 c). [0126] Then, the command analyzing and status data generating part 6 recognizes that the erase control part 7 is on operation, and the selector circuits 13 a�13 c select the erase control signal transmitted from the erase control part 7 according to the held memory block status information indicating on the erase operation, to transmit the signal to the memory blocks 10 a�10 c via the buses 12 a�12 c. This process is continued until the erase operation is completed. [0127] At the end of the erase operation, the latch circuits 11 a�11 c hold memory block status information indicating the completion of the erase operation, which is sent from the memory blocks 10 a�10 c via the buses 12 aa, 12 ba and 12 ca. [0128] The held memory block status information indicating the completion of the erase operation is sent to the command analyzing and status data generating part 6 and the selector circuits 13 a�13 c via the bus 9. Then, the command analyzing and status data generating part 6 recognizes that the erase control part 7 is not on an operation, and the selector circuits 13 a�13 c finish the transmission, to the memory blocks 10 a�10 c, of the erase control signal transmitted from the erase control part 7 according to the held information indicating the completion of the erase operation. [0129] That is, at the beginning of the erase operation, the memory blocks 10 a�10 c are selected according to the partition selection information sent via the bus 21 (21 a�21 c), while during the erase operation, they are selected according to the memory block status information indicating on the erase operation, which is held in the latch circuits 11 a�11 c. Therefore, during an erase operation, only the erase control part 7 and the selector circuits 13 a�13 c, and the memory blocks 10 a�10 c and the latch circuits 11 a�11 c can carry out the erase operation via the bus 14 for erasing and the bus 12. They are independently operable from other memory blocks, selector circuits, latch circuits and the write control part 8. [0130] Writing operations are similar to the series of the internal operations described above. [0131] Thus, as in the above embodiments, a non-volatile semiconductor memory device of the present invention associates partitions with an erase control part 7 or a write control part 8 one by one allowing an erase operation of a write operation to be carried out every partition. [0132] Additionally, although a single erase control part 7 and a single write control part 8 are shown in FIG. 1, the present non-volatile semiconductor memory device can have a plurality of partitions on an erase operation or a write operation by providing with a plurality of erase control parts and write control parts. [0133] 2. A read operation [0134] A read operation is explained. [0135] In a read operation, the command analyzing and status data generating part 6 transmits a read request signal via the bus 9 to partitions which are associated with neither the erase control part 7 nor the write control part 8, that is, on neither an erase operation nor a write operation. If the latch circuits 11 a�11 c have no memory status information indicating on erase and write operations, since the selector circuits 13 a�13 c do not send memory block status information to the bus 9, the selector circuits 13 a�13 c select the bus 9 to transmit a read request signal transmitted via the bus 9 to the memory blocks 10 a�10 c via the bus 12 a�12 c. The memory blocks 10 a�10 c send read data to the selector circuits 13 a�13 c via the buses 12 ab, 12 bb and 12 cb, the selector circuits 13 a�13 c select the bus 9 to send the read data to the command analyzing and status data generating part 6 via the bus 9, and the command analyzing and status data generating part 6 outputs the read data to the outside via the data 3. [0136] In this way, erase and write operations are independently carried out by holding information indicating on an erase or write operation in the latch circuits 11 a�11 c every partition, and by associating the erase control part 7 or the write control part 8, respectively, with every partition via each independent bus 14 for erasing or bus 15 for writing. In addition, partitions in which an erase or write operation is not carried out is readable via the bus 9 under the control of the command analyzing and status data generating part 6. Therefore, since the erase, write and read operations can be independently carried out, the non-volatile semiconductor memory device of the present invention can have a partition in which these functions can be carried out at the same time. [0137] 3. A method for holding partition division information [0138] Next, a method for holding partition division information in the partition latch circuit 18 is explained. [0139] The partition latch circuit 18 is a latch circuit holding partition division information. The command analyzing and status data generating part 6 receives a control signal 2, data 3 and an address 4 from the outside and, when these are a command to write to the partition latch circuit 18, it writes partition division information to the partition latch circuit 18. [0140] Then, the following sequence is shown as Example 1 of a command input row to write the partition division information to the partition latch circuit 18. [0141] Commands are entered as follows: [0142] 1. Command to write Partition division information [0143] 2. Partition No. [0144] 3. Memory block No. [0145] 4. Memory block No. [0146] wherein memory blocks to be included in a partition directed by Partition No. information in Item 2 are given as Memory block No. information in Items 3 or later. Here, memory blocks to be included in each partition may be directed arbitrarily. [0147] Next, the following sequence is explained using FIG. 4 as Example 2 of a command input row to write the partition division information to the partition latch circuit 18. [0148] Commands are entered as follows: [0149] 1. Command to write Partition division information [0150] 2. Partition division information. The command to write partition division information may be carried out at one write operation by entering data 3 and partition division information in FIG. 1 by an address 4 in FIG. 1. [0151] Partition division information is a flag designating the border between partitions comprised of consecutively numbered memory blocks. [0152] When two adjoining memory blocks belong to the same partition, then, a number �0� is given to a boundary of these two memory blocks, and when two adjoining memory blocks belong to different partition each other, then, a number �1� is given to their boundary. That is, boundaries of memory blocks given the number �1� are border of partitions. In FIG. 4, since the partition division information is �00101000. . . �, the partition 1 includes memory blocks 0, 1 and 2, the partition 2 includes memory blocks 3 and 4, and the partition 3 includes memory blocks 5, 6, 7, and etc. [0153] This method, unlike Example 1 of the input row, can direct successive memory blocks to a partition, but it can lessen the commands to be entered and, further, avoid a risk to direct one memory block to different partitions overlappedly. [0154] Next, an information holding-mean of the partition latch circuit 18 is explained. [0155] In order to hold information, the partition latch circuit 18 may be either a latch circuit using a non-volatile memory or a latch circuit using a volatile memory. [0156] In the case of a non-volatile circuit, a partition division state can be held after the power is shut down. On the other hand, in the case of a volatile circuit, since a rewrite speed is high, a temporary alteration of the partition division information is possible. [0157] In addition, a non-volatile circuit and a volatile circuit may be used together. In this case, the non-volatile circuit holds the initial state of each of partitions at the time when the power is turned on, and the volatile circuit may be used to temporarily alter the partition division information. [0158] 4. Protection of partition division information [0159] Next, a function for protecting the partition division information is explained using FIG. 5. In FIG. 5, since the constituents indicated with the same symbols as those in FIG. 1 are the same as or equivalent to the constituents in FIG. 1, only different constituents from FIG. 1 are described below. [0160] Bus 17 writes partition division information to the partition latch circuit 18 when the control signal 2, the data 3 and the address 4 are a command to write to the partition latch circuit 18. Here, partition division information 17 a�17 d, partition division information write control signal 17 e, and partition division information protect signals 17 f and 17 g are sent via the bus 17. [0161] The partition latch circuit 18 holds information to which partition each of the memory blocks belongs. [0162] Buses 19 output the partition division information held in the latch circuit 18. [0163] Latch circuits 23 (23 a�23 d) hold partition division information, and one latch circuit latches one piece of partition division information. [0164] A protection latch circuit 22 holds information to protect writing to the latch circuits 23 (23 a�23 d). [0165] An output signal 24 is outputted from the protection latch circuit 22. [0166] A circuit 25 judges whether the partition division information write signal 17e is valid or invalid according to the output signal 24 which is the information to protect writing held in the latch circuit 22. [0167] Control signals 26 are signals for rewriting the information of the latch circuits 23 (23 a�23 d) holding the partition division information to partition division information 17 a�17 d. [0168] First, in order to protect partition division information, a latch circuit 22 for protecting partition division information is set in the partition latch circuit 18. Hereinafter, an output signal 24 from the latch circuit 22 for protecting this partition division information is referred to as a �partition division information protection flag 24�. When partition division information is written as described above, by referring to the partition division information protection flag 24, when the protection of the partition division information is valid, the partition division information write control signal 26 becomes invalid and, consequently, the information in the latch circuits 23 (23 a�23 d) holding the partition division information is not rewritten. Therefore, the partition division information is protected. [0169] A method for holding data of the partition division information protection flag is the same as the method for holding partition division information. That is, data of the partition division information protection flag are written in the latch circuit 22 for protecting the partition division information via the buses 17 (17 f and A; 17 g), when the control signal 2, the data 3 and the address 4 entered in the command analyzing and status data generating part 6 from the outside are a command to write to the latch circuit 22 for protecting the partition division information. Here, a write control signal 17 f and a data signal 17 g are transmitted to the latch circuit 22. [0170] The latch circuit 23 holding the partition division information and the protection latch circuit 24 outputting the partition division information protection flag may be either a non-volatile circuit or a volatile circuit. [0171] When the latch circuit 23 is comprised of a non-volatile circuit, as shown in FIG. 6, it is advantageous to add a circuit 27 judging whether the partition division information write control signal 17 e is valid or invalid according to the output signal 24 which is the information to protect writing held in the latch circuit 22, and a partition division information write control signal 28. Thereby, when the partition division information protection flag 24 is valid, the partition division information write control signal 28 becomes invalid and, consequently, the information in the latch circuit 22 is not rewritten. That is, it becomes impossible to make the partition division information protection flag 24 invalid and, therefore, since the partition division information protection flag 24 keeps its validity, writing to the latch circuits 23 (23 a�23 d) keeps being protected. Thus, the partition division information can be fixed to disapprove in future the alteration of the information. [0172] The number of memory blocks included in one partition is determined according to the partition division information in the partition latch circuit 18 and, since the partition division information can be altered by commands, the memory volume of a partition can be varied anytime. Therefore, it is possible to effectively distribute memory segments to be used. [0173] Further, when according to the partition division information given by the command to write partition division information, only one partition is set in the non-volatile semiconductor memory device of the present invention (i.e., all the memory blocks of the non-volatile semiconductor memory device are included in a single partition), for example, during an erase operation, since all the latch circuits 11 hold information indicating on the erase operation, no memory block exists in which a write and read operations can be carried out simultaneously. Since the same thing can be said to a write operation, the above non-volatile semiconductor memory device is not able to carry out two or more functions of erasing, writing and reading. That is, since the above non-volatile semiconductor memory device is equivalent to a non-volatile semiconductor memory device of the prior art, which is not able to carry out two or more functions at the same time, compatibility in a test or usage of a non-volatile semiconductor memory device is maintained. INDUSTRIAL APPLICABILITY [0174] As explained in details above, a non-volatile semiconductor memory device of the present invention has a plurality of erasable, writable and readable memory segments, and can carry out erase, write and read functions simultaneously by altering a combination of these memory segments. Thus, distribution of memory segments to be used can be effectively performed according to the purpose of using by altering the memory segments where these functions can be carried out at the same time. That is, the present invention provides a non-volatile semiconductor memory device which can flexibly satisfy the diversifying market demand. In addition, since the alteration of the memory region distribution is possible by entering a command, the distribution of memory segments to be used can be effectively preformed anytime according to the purpose of use. [0175] In addition, the use of a non-volatile memory or a volatile memory, or both a non-volatile memory and a volatile memory allows a method to save partition division information after the shut-down of the power, to alter it during the use, or to hold partition division information as an initial value at the time when the power is turned on. [0176] The semiconductor memory device of the present invention has a protecting function of rewriting partition division information saved in latch circuits to fix the partition division information. Also, the non-volatile semiconductor memory device of the present invention, as described above, allows to distribute memory segments to be used according to the purpose of the use after the semiconductor has been produced and, at the same time, allows to prevent the distribution of the memory segments to be used from being undesirably altered with entry of an incorrect command by setting the protection information. [0177] In the non-volatile semiconductor memory device of the present invention, its memory region comprises a number of erasable, writable and readable memory blocks in which these functions can be carried out simultaneously. According to the present non-volatile semiconductor memory device, since the memory region is controlled by a partition unit constituting a plurality of memory blocks, the number of objects to be controlled can be reduced relative to the case where the memory region is controlled as individual memory block units. [0178] Thus, in a system using the present non-volatile semiconductor memory device, the control thereof can be simplified than in a conventional system. [0179] In addition, form the viewpoint of products comprising the present non-volatile semiconductor memory device, for example, in the field of portable phones which is a large market of a non-volatile semiconductor memory device such as a flash memory, when internet applications such as a mailing-function which is greatly prevailing in recent years are added to a portable phone only for call, since a program region (a memory region for reading) can be expanded without modifying a design of the product, and the execution of the program (reading from the memory region for reading) can be carried out together with a write operation to a data region (a memory region for writing), a high-speed transaction is achieved. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7095672May 25, 2004Aug 22, 2006Nec CorporationSemiconductor memory device and method of controlling the sameUS7500081 *Sep 30, 2005Mar 3, 2009Intel CorporationPower-up implementation for block-alterable memory with zero-second erase timeUS8527730Sep 9, 2008Sep 3, 2013Kabushiki Kaisha ToshibaData updating method, memory system and memory deviceUS8627031Jun 23, 2011Jan 7, 2014Kabushiki Kaisha ToshibaSemiconductor memory device and method of reading data from and writing data into a plurality of storage unitsEP1482516A1 *May 25, 2004Dec 1, 2004Nec CorporationWear levelling in a non volatile flash memory not needing free blocks* Cited by examinerClassifications U.S. Classification257/314International ClassificationG11C16/04, G06F12/00, G11C16/02, G11C16/08, G11C16/22, G06F12/06Cooperative ClassificationG11C2216/22, G11C16/08, G11C16/22European ClassificationG11C16/08, G11C16/22Legal EventsDateCodeEventDescriptionMar 2, 2015ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD, KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTELLECTUAL PROPERTIES I KFT.;REEL/FRAME:035120/0878Effective date: 20141222Oct 23, 2014FPAYFee paymentYear of fee payment: 12Dec 15, 2011ASAssignmentOwner name: INTELLECTUAL PROPERTIES I KFT., HUNGARYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SHARP KABUSHIKI KAISHA;REEL/FRAME:027387/0650Effective date: 20111115Oct 14, 2010FPAYFee paymentYear of fee payment: 8Oct 20, 2006FPAYFee paymentYear of fee payment: 4Aug 17, 2001ASAssignmentOwner name: SHARP KABUSHIKI KAISHA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAKI, MASAMITSU;REEL/FRAME:012157/0117Effective date: 20010807Owner name: SHARP KABUSHIKI KAISHA 22-22, NAGAIKE-CHO, ABENO-KOwner name: SHARP KABUSHIKI KAISHA 22-22, NAGAIKE-CHO, ABENO-KFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAKI, MASAMITSU /AR;REEL/FRAME:012157/0117Owner name: SHARP KABUSHIKI KAISHA 22-22, NAGAIKE-CHO, ABENO-KFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAKI, MASAMITSU /AR;REEL/FRAME:012157/0117Effective date: 20010807Owner name: SHARP KABUSHIKI KAISHA 22-22, NAGAIKE-CHO, ABENO-KFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAKI, MASAMITSU;REEL/FRAME:012157/0117Effective date: 20010807RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services