Source: http://www.google.com/patents/US7898057?dq=5927278
Timestamp: 2017-02-25 01:02:35
Document Index: 426128990

Matched Legal Cases: ['Application No. 05711267', 'Application No. 200580000549', 'Application No. 05711267', 'Application No. 05711267', 'Application No. 05711267', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 10']

Patent US7898057 - Radio frequency power semiconductor device package comprising dielectric ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and...http://www.google.com/patents/US7898057?utm_source=gb-gplus-sharePatent US7898057 - Radio frequency power semiconductor device package comprising dielectric platform and shielding plateAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7898057 B2Publication typeGrantApplication numberUS 11/387,617Publication dateMar 1, 2011Filing dateMar 23, 2006Priority dateJan 10, 2004Fee statusLapsedAlso published asEP1654765A2, US7847369, US8471378, US9029946, US9177866, US20060226451, US20070057289, US20070090434, US20100032750, US20130328132, US20150221558, US20160056084, US20160329320, WO2005069378A2, WO2005069378A3Publication number11387617, 387617, US 7898057 B2, US 7898057B2, US-B2-7898057, US7898057 B2, US7898057B2InventorsRobert Bruce Davies, Warren Leroy Seely, Jeanne S PavioOriginal AssigneeHvvi Semiconductors, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (110), Non-Patent Citations (36), Referenced by (6), Classifications (105), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetRadio frequency power semiconductor device package comprising dielectric platform and shielding plate
Referring to FIG. 14, protective layers 350 and 385 are removed. Removing protective layer 350 reveals underlying dielectric layer 345. Removing protective layer 385 reveals underlying dielectric layer 375. Dielectric layer 375 is then removed revealing underlying polysilicon layer 370. A dielectric layer 400 is formed in opening 395 on doped region 380. In an embodiment of the wafer process, dielectric layer 400 is a thin pre-implant thermal oxide. An implant step is then performed forming a doped region 405. In an embodiment of the wafer process, the dopant is arsenic (n-type). In particular, the implant dopes polysilicon layer 370 and is implanted through opening 395 into doped region 380 to form doped region 405 which relates to a source of the transistor cell. In an embodiment of the device to ensure adequate coverage, the ion implantation is performed at an angle of approximately 45°, in quadrature, such that the polysilicon layer 370 is converted to N type during the wafer process step.
A thin pre-implant oxide layer is formed in opening 430. An implant step is performed to provide dopant through opening 430 into doped region 380. The implant forms a doped region 435. In an embodiment of the wafer process, an n-type dopant is used such as arsenic or phosphorus. The n-type dopant ion implantation is performed at 7° in quadrature having a concentration in the range of 1E14-1E16 to ensure good coverage. In an embodiment of the transistor a doping concentration of 5E14 is used in n-type doped region 435. Doped region 435 defines the edge of the source region that is adjacent to the channel region of the transistor cell. The thermal processes performed hereinabove causes doped region 405 to further diffuse, both vertically and horizontally, into doped region 380.
Referring to FIG. 18, the dielectric layer formed in FIG. 17 is removed. Sidewall region 445 is then removed revealing protective layer 440. A protective layer is then formed over the first major surface. In an embodiment of the wafer process, the protective layer is silicon nitride (Si3N4). The silicon nitride layer is then formed approximately 750 Å thick. The combination of the silicon nitride layer and protective layer 440 is denoted by protective layer 460. A dielectric layer 465 is then formed over the first major surface. In an embodiment of the wafer process, dielectric layer 465 comprises TEOS. The TEOS layer is formed approximately 6000 Å thick. The TEOS is densified in a thermal process at a temperature of approximately 700° C. The densification step is followed by a rapid thermal anneal process. These processes cause regions 405 and 435 of FIGS. 16-17 to combine to form region 437. Region 437 corresponds to the source of the transistor cell. The thermal anneal activates edge termination region 310, doped region 380, doped region 437, doped region 455, and optional doped region 275 and sets the junction profiles. Region 310 and region 380 are both p-type and electrically coupled together. It should be noted that the sequence of wafer processing steps provides substantial benefits from a thermal perspective. For example, dielectric platform 255 is formed before the transistor cells in the active area thus the high temperature steps required to oxidize large areas of the die are performed before implants are made. Similarly, the majority of the dopings in the active area of the transistor are activated near the end of the process flow which allows the implants to be placed without moving substantially due to additional thermal steps that plague other transistor designs. This produces a device that can be manufactured consistently with low process variation and higher device performance.
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No. 11/387,210, mailed on May 13, 2009, 9 pages.33Prophet, Graham , "Power FETs find their place", EDN, (Apr. 17, 2003), 6 pages.34Radivojevic, Z. , et al., "Novel Material for Improved Quality of RF-PA in Base-Station Applications", Presented at 10th International Workshop on Thermal Investigations of ICs and Systems, Co-Authored by Nokia Research Center and Freescale Semiconductor,(Sep./Oct. 2004), 7 pages.35Sawle, Andrew , et al., "DirectEFT-A Proprietary New Source Mounted Power Package for Board Mounted Power", http://www.irf.com/technical-info/whitepaper/directfet.pdf, (Unknown), 5 pages.36Sawle, Andrew , et al., "DirectEFT—A Proprietary New Source Mounted Power Package for Board Mounted Power", http://www.irf.com/technical-info/whitepaper/directfet.pdf, (Unknown), 5 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8471378Mar 23, 2006Jun 25, 2013Estivation Properties LlcPower semiconductor device and method thereforUS8530963Mar 23, 2006Sep 10, 2013Estivation Properties LlcPower semiconductor device and method thereforUS8642470 *Dec 9, 2011Feb 4, 2014Semiconductor Manufacturing International (Beijing) CorporationSemiconductor device manufacturing methodUS9312382Jul 22, 2014Apr 12, 2016Empire Technology Development LlcHigh voltage transistor device with reduced characteristic on resistanceUS20060226451 *Mar 23, 2006Oct 12, 2006Hvvi Semiconductors, Inc.Power semiconductor device and method thereforUS20060226498 *Mar 23, 2006Oct 12, 2006Hvvi Semiconductors,Inc.Power semiconductor device and method therefor* Cited by examinerClassifications U.S. Classification257/522, 257/E29.122, 257/E29.12International ClassificationH01L29/41, H01L29/10, H01L29/417, H01L23/047, H01L29/40, H01L21/28, H01L23/10, H01L21/762, H01L29/06, H01L29/423, H01L21/336, H01L29/08, H01L23/36, H01L29/78, H01L23/498, H01L23/482Cooperative ClassificationH01L21/823475, H01L25/50, H01L29/41741, H01L23/10, H01L23/49844, H01L29/1095, H01L29/4238, H01L21/56, H01L29/7817, H01L27/0296, H01L29/0696, H01L23/3675, H01L2924/14, H01L21/823412, H01L23/552, H01L21/76838, H01L29/66712, H01L29/66681, H01L21/823487, H01L21/823481, H01L21/823437, H01L21/32055, H01L21/768, H01L21/76224, H01L2924/1305, H01L24/06, H01L23/047, H01L2924/13091, H01L2924/01079, H01L29/66719, H01L2924/01074, H01L29/66727, H01L29/41766, H01L2924/014, H01L23/36, H01L2924/01033, H01L2224/06136, H01L2924/0105, H01L2924/01061, H01L21/2815, H01L2924/3011, H01L2924/01006, H01L2924/30107, H01L2924/01005, H01L2924/0106, H01L2924/01029, H01L29/7811, H01L2924/01013, H01L2224/83193, H01L2924/16152, H01L2924/01014, H01L29/42372, H01L29/42376, H01L2924/1306, H01L2924/19041, H01L23/4824, H01L2924/01082, H01L2924/01322, H01L2224/83801, H01L2924/04941, H01L2223/6644, H01L2924/01022, H01L2924/01019, H01L24/83, H01L2224/48091, H01L2924/01023, H01L2224/04042, H01L23/051, H01L2224/0401, H01L29/0878, H01L29/0661, H01L29/0657, H01L2924/0002, H01L2924/3025, H01L29/402, H01L23/66European ClassificationH01L29/06C4, H01L29/78B2E, H01L29/66M6T6F14V2, H01L29/66M6T6F14V3, H01L23/66, H01L23/051, H01L23/36, H01L29/423D2B7, H01L23/047, H01L24/06Legal EventsDateCodeEventDescriptionMar 23, 2006ASAssignmentOwner name: HVVI SEMICONDUCTORS, INC., ARIZONAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DAVIES, ROBERT;SEELY, WARREN LEROY;PAVIO, JEANNE S;REEL/FRAME:017717/0032Effective date: 20060216May 14, 2013ASAssignmentOwner name: ESTIVATION PROPERTIES LLC, DELAWAREFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HVVI SEMICONDUCTOR, INC.;REEL/FRAME:030408/0580Effective date: 20120628Oct 10, 2014REMIMaintenance fee reminder mailedMar 1, 2015LAPSLapse for failure to pay maintenance feesApr 21, 2015FPExpired due to failure to pay maintenance feeEffective date: 20150301RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services