Source: https://patents.google.com/patent/US8760454B2/en
Timestamp: 2018-11-19 14:52:19
Document Index: 360679088

Matched Legal Cases: ['Application No. 2004800405708', 'Application No. 2004800405708', 'Application No. 2004800405708', 'Application No. 10075685', 'Application No. 10075686', 'Application No. 10075687', 'Application No. 10075688', 'Application No. 04798938']

US8760454B2 - Graphics processing architecture employing a unified shader - Google Patents
Graphics processing architecture employing a unified shader Download PDF
US8760454B2
US8760454B2 US13109738 US201113109738A US8760454B2 US 8760454 B2 US8760454 B2 US 8760454B2 US 13109738 US13109738 US 13109738 US 201113109738 A US201113109738 A US 201113109738A US 8760454 B2 US8760454 B2 US 8760454B2
US13109738
US20110216077A1 (en )
Stephen L. Morein
Andrew E. Gruber
Andi Skende
A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data b a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
This application is a continuation of co-pending U.S. application Ser. No. 12/791,597, filed Jun. 1, 2010, entitled “GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER”, having as inventors Steven Morein et al., owned by instant assignee and is incorporated herein by reference, which is a continuation of co-pending U.S. application Ser. No. 11/842,256, filed Aug. 21, 2007, entitled “GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER”, having as inventors Steven Morein et al., owned by instant assignee and is incorporated herein by reference, which is a continuation of U.S. application Ser. No. 11/117,863, filed Apr. 29, 2005, which has issued into U.S. Pat. No. 7,327,369, entitled “GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER”, having as inventors Steven Morein et al., and owned by instant assignee and is incorporated herein by reference which is a continuation of U.S. application Ser. No. 10/718,318, filed on Nov. 20, 2003, which has issued into U.S. Pat. No. 6,897,871, entitled “GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER”, having as inventors Steven Morein et al., and owned by instant assignee and is incorporated herein by reference.
The present invention generally relates to graphics processors and, more particularly, to a graphics processor architecture employing a single shader.
In computer graphics applications, complex shapes and structures are formed through the sampling, interconnection and rendering of more simple objects, referred to as primitives. An example of such a primitive is a triangle, or other suitable polygon. These primitives, in turn, are formed by the interconnection of individual pixels. Color and texture are then applied to the individual pixels that comprise the shape based on their location within the primitive and the primitives orientation with respect to the generated shape; thereby generating the object that is rendered to a corresponding display for subsequent viewing.
The interconnection of primitives and the application of color and textures to generated shapes are generally performed by a graphics processor. Conventional graphics processors include a series of shaders that specify how and with what corresponding attributes, a final image is drawn on a screen, or suitable display device. As illustrated in FIG. 1, a conventional shader 10 can be represented as a processing block 12 that accepts a plurality of bits of input data, such as, for example, object shape data (14) in object space (x,y,z); material properties of the object, such as color (16); texture information (18); luminance information (20); and viewing angle information (22) and provides output data (28) representing the object with texture and other appearance properties applied thereto (x′, y′, z′).
In exemplary fashion, as illustrated in FIGS. 2A-2B, the shader accepts the vertex coordinate data representing cube 30 (FIG. 2A) as inputs and provides data representing, for example, a perspectively corrected view of the cube 30′ (FIG. 2B) as an output. The corrected view may be provided, for example, by applying an appropriate transformation matrix to the data representing the initial cube 30. More specifically, the representation illustrated in FIG. 2B is provided by a vertex shader that accepts as inputs the data representing, for example, vertices Vx, Vy and Vz, among others of cube 30 and providing angularly oriented vertices Vx′,Vy′ and Vz′, including any appearance attributes of corresponding cube 30′.
In addition to the vertex shader discussed above, a shader processing block that operates on the pixel level, referred to as a pixel shader is also used when generating an object for display. Generally, the pixel shader provides the color value associated with each pixel of a rendered object. Conventionally, both the vertex shader and pixel shader are separate components that are configured to perform only a single transformation or operation. Thus, in order to perform a position and a texture transformation of an input, at least two shading operations and hence, at least two shaders, need to be employed. Conventional graphics processors require the use of both a vertex shader and a pixel shader in order to generate an object. Because both types of shaders are required, known graphics processors are relatively large in size, with most of the real estate being taken up by the vertex and pixel shaders.
In addition to the real estate penalty associated with conventional graphics processors, there is also a corresponding performance penalty associated therewith. In conventional graphics processors, the vertex shader and the pixel shader are juxtaposed in a sequential, pipelined fashion, with the vertex shader being positioned before and operating on vertex data before the pixel shader can operate on individual pixel data.
Thus, there is a need for an improved graphics processor employing a shader that is both space efficient and computationally effective.
The present invention and the associated advantages and features thereof, will become better understood and appreciated upon review of the following detailed description of the invention, taken in conjunction with the following drawings, where like numerals represent like elements, in which:
FIG. 1 is a schematic block diagram of a conventional shader;
FIGS. 2A-2B are graphical representations of the operations performed by the shader illustrated in FIG. 1;
FIG. 3 is a schematic block diagram of a conventional graphics processor architecture;
FIG. 4A is a schematic block diagram of a graphics processor architecture according to the present invention;
FIG. 4B is a schematic block diagram of an optional input component to the graphics processor according to an alternate embodiment of the present invention; and
FIG. 5 is an exploded schematic block diagram of the unified shader employed in the graphics processor illustrated in FIG. 4A.
Briefly stated, the present invention is directed to a graphics processor that employs a unified shader that is capable of performing both the vertex operations and the pixel operations in a space saving and computationally efficient manner. In an exemplary embodiment, a graphics processor according to the present invention includes an arbiter circuit for selecting one of a plurality of inputs for processing in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs.
The shader includes a general purpose register block for storing at least the plurality of selected inputs, a sequencer for storing logical and arithmetic instructions that are used to perform vertex and pixel manipulation operations and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs according to the instructions maintained in the sequencer. The shader of the present invention is referred to as a “unified” shader because it is configured to perform both vertex and pixel operations. By employing the unified shader of the present invention, the associated graphics processor is more space efficient than conventional graphics processors because the unified shader takes up less real estate than the conventional multi-shader processor architecture.
In addition, according to the present invention, the unified shader is more computationally efficient because it allows the shader to be flexibly allocated to pixels or vertices based on workload.
Referring now to FIG. 3, illustrated therein is a graphics processor incorporating a conventional pipeline architecture. As shown, the graphics processor 40 includes a vertex fetch block 42 which receives vertex information relating to a primitive to be rendered from an off-chip memory 55 on line 41. The fetched vertex data is then transmitted to a vertex cache 44 for storage on line 43. Upon request, the vertex data maintained in the vertex cache 44 is transmitted to a vertex shader 46 on line 45. As discussed above, an example of the information that is requested by and transmitted to the vertex shader 46 includes the object shape, material properties (e.g. color), texture information, and viewing angle. Generally, the vertex shader 46 is a programmable mechanism which applies a transformation position matrix to the input position information (obtained from the vertex cache 44), thereby providing data representing a perspectively corrected image of the object to be rendered, along with any texture or color coordinates thereof.
After performing the transformation operation, the data representing the transformed vertices are then provided to a vertex store 48 on line 47. The vertex store 48 then transmits the modified vertex information contained therein to a primitive assembly block 50 on line 49. The primitive assembly block 50 assembles, or converts, the input vertex information into a plurality of primitives to be subsequently processed. Suitable methods of assembling the input vertex information into primitives is known in the art and will not be discussed in greater detail here. The assembled primitives are then transmitted to a rasterization engine 52, which converts the previously assembled primitives into pixel data through a process referred to as walking. The resulting pixel data is then transmitted to a pixel shader 54 on line 53.
The pixel shader 54 generates the color and additional appearance attributes that are to be applied to a given pixel, and applies the appearance attributes to the respective pixels. In addition, the pixel shader 54 is capable of fetching texture data from a texture map 57 as indexed by the pixel data from the rasterization engine 52 by transmitting such information on line 55 to the texture map. The requested texture data is then transmitted back from the texture map 57 on line 57′ and stored in a texture cache 56 before being routed to the pixel shader on line 58. Once the texture data has been received, the pixel shader 54 then performs specified logical or arithmetic operations on the received texture data to generate the pixel color or other appearance attribute of interest. The generated pixel appearance attribute is then combined with a base color, as provided by the rasterization engine on line 53, to thereby provide a pixel color to the pixel corresponding at the position of interest. The pixel appearance attribute present on line 59 is then transmitted to post raster processing blocks (not shown).
As described above, the conventional graphics processor 40 requires the use of two separate shaders: a vertex shader 46 and a pixel shader 54. A drawback associated with such an architecture is that the overall footprint of the graphics processor is relatively large as the two shaders take up a large amount of real estate. Another drawback associated with conventional graphics processor architectures is that can exhibit poor computational efficiency.
Referring now to FIG. 4A, in an exemplary embodiment, the graphics processor 60 of the present invention includes a multiplexer 66 having vertex (e.g. indices) data provided at a first input thereto and interpolated pixel parameter (e.g. position) data and attribute data from a rasterization engine 74 provided at a second input. A control signal generated by an arbiter 64 is transmitted to the multiplexer 66 on line 63. The arbiter 64 determines which of the two inputs to the multiplexer 66 is transmitted to a unified shader 62 for further processing. The arbitration scheme employed by the arbiter 64 is as follows: the vertex data on the first input of the multiplexer 66 is transmitted to the unified shader 62 on line 65 if there is enough resources available in the unified shader to operate on the vertex data; otherwise, the interpolated pixel parameter data present on the second input will be passed to the unified shader 62 for further processing.
Referring briefly to FIG. 5, the unified shader 62 will now be described. As illustrated, the unified shader 62 includes a general purpose register block 92, a plurality of source registers: including source register A 93, source register B 95, and source register C 97, a processor (e.g. CPU) 96 and a sequencer 99. The general purpose register block 92 includes sixty four registers, or available entries, for storing the information transmitted from the multiplexer 66 on line 65 or any other information to be maintained within the unified shader. The data present in the general purpose register block 92 is transmitted to the plurality of source registers via line 109.
The processor 96 may be comprised of a dedicated piece of hardware or can be configured as part of a general purpose computing device (i.e. personal computer). In an exemplary embodiment, the processor 96 is adapted to perform 32-bit floating point arithmetic operations as well as a complete series of logical operations on corresponding operands. As shown, the processor is logically partitioned into two sections. Section 96 is configured to execute, for example, the 32-bit floating point arithmetic operations of the unified shader. The second section, 96A, is configured to perform scaler operations (e.g. log, exponent, reciprocal square root) of the unified shader.
The sequencer 99 includes constants block 91 and an instruction store 98. The constants block 91 contains, for example, the several transformation matrices used in connection with vertex manipulation operations. The instruction store 98 contains the necessary instructions that are executed by the processor 96 in order to perform the respective arithmetic and logic operations on the data maintained in the general purpose register block 92 as provided by the source registers 93-95. The instruction store 98 further includes memory fetch instructions that, when executed, causes the unified shader 62 to fetch texture and other types of data, from memory 82 (FIG. 4A). In operation, the sequencer 99 determines whether the next instruction to be executed (from the instruction store 98) is an arithmetic or logical instruction or a memory (e.g. texture fetch) instruction. If the next instruction is a memory instruction or request, the sequencer 99 sends the request to a fetch block (not shown) which retrieves the required information from memory 82 (FIG. 4A). The retrieved information is then transmitted to the sequencer 99, through the vertex texture cache 68 (FIG. 4A) as described in greater detail below.
If the next instruction to be executed is an arithmetic or logical instruction, the sequencer 99 causes the appropriate operands to be transferred from the general purpose register block 92 into the appropriate source registers (93, 95, 97) for execution, and an appropriate signal is sent to the processor 96 on line 101 indicating what operation or series of operations are to be executed on the several operands present in the source registers. At this point, the processor 96 executes the instructions on the operands present in the source registers and provides the result on line 85. The information present on line 85 may be transmitted back to the general purpose register block 92 for storage, or transmitted to succeeding components of the graphics processor 60.
As discussed above, the instruction store 98 maintains both vertex manipulation instructions and pixel manipulation instructions. Therefore, the unified shader 99 of the present invention is able to perform both vertex and pixel operations, as well as execute memory fetch operations. As such, the unified shader 62 of the present invention is able to perform both the vertex shading and pixel shading operations on data in the context of a graphics controller based on information passed from the multiplexer. By being adapted to perform memory fetches, the unified shader of the present invention is able to perform additional processes that conventional vertex shaders cannot perform; while at the same time, perform pixel operations.
The unified shader 62 has ability to simultaneously perform vertex manipulation operations and pixel manipulation operations at various degrees of completion by being able to freely switch between such programs or instructions, maintained in the instruction store 98, very quickly. In application, vertex data to be processed is transmitted into the general purpose register block 92 from multiplexer 66. The instruction store 98 then passes the corresponding control signals to the processor 96 on line 101 to perform such vertex operations. However, if the general purpose register block 92 does not have enough available space therein to store the incoming vertex data, such information will not be transmitted as the arbitration scheme of the arbiter 64 is not satisfied. In this manner, any pixel calculation operations that are to be, or are currently being, performed by the processor 96 are continued, based on the instructions maintained in the instruction store 98, until enough registers within the general purpose register block 92 become available. Thus, through the sharing of resources within the unified shader 62, processing of image data is enhanced as there is no down time associated with the processor 96.
Referring back to FIG. 4A, the graphics processor 60 further includes a cache block 70, including a parameter cache 70A and a position cache 70B which accepts the pixel based output of the unified shader 62 on line 85 and stores the respective pixel parameter and position information in the corresponding cache. The pixel information present in the cache block 70 is then transmitted to the primitive assembly block 72 on line 71. The primitive assembly block 72 is responsible for assembling the information transmitted thereto from the cache block 70 into a series of triangles, or other suitable primitives, for further processing. The assembled primitives are then transmitted on line 73 to rasterization engine block 74, where the transmitted primitives are then converted into individual pixel data information through a walking process, or any other suitable pixel generation process. The resulting pixel data from the rasterization engine block 74 is the interpolated pixel parameter data that is transmitted to the second input of the multiplexer 66 on line 75.
In those situations when vertex data is transmitted to the unified shader 62 through the multiplexer 66, the resulting vertex data generated by the processor 96, is transmitted to a render back end block 76 which converts the resulting vertex data into at least one of several formats suitable for later display on display device 84. For example, if a stained glass appearance effect is to be applied to an image, the information corresponding to such appearance effect is associated with the appropriate position data by the render back end 76. The information from the render back end 76 is then transmitted to memory 82 and a display controller line 80 via memory controller 78. Such appropriately formatted information is then transmitted on line 83 for presentation on display device 84.
Referring now to FIG. 4B, shown therein is a vertex block 61 which is used to provide the vertex information at the first input of the multiplexer 66 according to an alternate embodiment of the present invention. The vertex block 61 includes a vertex fetch block 61A which is responsible for retrieving vertex information from memory 82, if requested, and transmitting that vertex information into the vertex cache 61B. The information stored in the vertex cache 61B comprises the vertex information that is coupled to the first input of multiplexer 66.
As discussed above, the graphics processor 60 of the present invention incorporates a unified shader 62 which is capable of performing both vertex manipulation operations and pixel manipulation operations based on the instructions stored in the instruction store 98. In this fashion, the graphics processor 60 of the present invention takes up less real estate than conventional graphics processors as separate vertex shaders and pixel shaders are no longer required. In addition, as the unified shader 62 is capable of alternating between performing vertex manipulation operations and pixel manipulation operations, graphics processing efficiency is enhanced as one type of data operations is not dependent upon another type of data operations. Therefore, any performance penalties experienced as a result of dependent operations in conventional graphics processors are overcome.
The above detailed description of the present invention and the examples described therein have been presented for the purposes of illustration and description. It is therefore contemplated that the present invention cover any and all modifications, variations and equivalents that fall within the spirit and scope of the basic underlying principles disclosed and claimed herein.
1. A method carried out by a unified shader comprising:
performing vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor within the unified shader unless the general purpose register block does not have enough available space therein to store incoming vertex data; and
continuing pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
2. A unified shader, comprising:
a general purpose register block for maintaining data;
a sequencer, coupled to the general purpose register block and the processor unit, the sequencer maintaining instructions operative to cause the processor unit to execute vertex calculation and pixel calculation operations on selected data maintained in the general purpose register block; and
wherein the processor unit executes instructions that generate a pixel color in response to selected data from the general purpose register block and generates vertex position and appearance data in response to selected data from the general purpose register block.
3. A unified shader comprising:
a processor unit operative to perform vertex calculation operations and pixel calculation operations; and
shared resources, operatively coupled to the processor unit;
the processor unit operative to use the shared resources for either vertex data or pixel information and operative to perform pixel calculation operations until enough shared resources become available and then use the shared resources to perform vertex calculation operations.
4. A unified shader comprising:
the processor unit operative to use the shared resources for either vertex data or pixel information and operative to perform vertex calculation operations until enough shared resources become available and then use the shared resources to perform pixel calculation operations.
5. A unified shader comprising:
a sequencer coupled to the processor unit, the sequencer maintaining instructions operative to cause the processor unit to execute vertex calculation and pixel calculation operations on selected data maintained in a store depending upon an amount of space available in the store.
6. The shader of claim 5, wherein the sequencer further includes circuitry operative to fetch data from a memory.
7. The shader of claim 5, further including a selection circuit operative to provide information to the store in response to a control signal.
8. The shader of claim 5, wherein the processor unit executes instructions that generate a pixel color in response to the selected data.
9. The shader of claim 5, wherein the processor unit generates vertex position and appearance data in response to a selected data.
10. The shader of claim 7, wherein the control signal is provided by an arbiter.
11. A unified shader comprising:
a processor unit flexibly controlled to perform vertex manipulation operations and pixel manipulation operations based on vertex or pixel workload; and
an instruction store and wherein the processor unit of the unified shader performs the vertex manipulation operations and pixel manipulation operations at various degrees of completion based on switching between instructions in the instruction store.
US13109738 2003-11-20 2011-05-17 Graphics processing architecture employing a unified shader Active US8760454B2 (en)
US10718318 US6897871B1 (en) 2003-11-20 2003-11-20 Graphics processing architecture employing a unified shader
US11117863 US7327369B2 (en) 2003-11-20 2005-04-29 Graphics processing architecture employing a unified shader
US11842256 US20070285427A1 (en) 2003-11-20 2007-08-21 Graphics processing architecture employing a unified shader
US12791597 US20100231592A1 (en) 2003-11-20 2010-06-01 Graphics processing architecture employing a unified shader
US13109738 US8760454B2 (en) 2003-11-20 2011-05-17 Graphics processing architecture employing a unified shader
US14312014 US20140300613A1 (en) 2003-11-20 2014-06-23 Graphics processing architecture employing a unified shader
US14614967 US9582846B2 (en) 2003-11-20 2015-02-05 Graphics processing architecture employing a unified shader
US15193647 US20160307356A1 (en) 2003-11-20 2016-06-27 Graphics processing architecture employing a unified shader
US12791597 Continuation US20100231592A1 (en) 2003-11-20 2010-06-01 Graphics processing architecture employing a unified shader
US14312014 Continuation US20140300613A1 (en) 2003-11-20 2014-06-23 Graphics processing architecture employing a unified shader
US20110216077A1 true US20110216077A1 (en) 2011-09-08
US8760454B2 true US8760454B2 (en) 2014-06-24
ID=34591071
US10718318 Active US6897871B1 (en) 2003-11-20 2003-11-20 Graphics processing architecture employing a unified shader
US11117863 Active US7327369B2 (en) 2003-11-20 2005-04-29 Graphics processing architecture employing a unified shader
US11842256 Abandoned US20070285427A1 (en) 2003-11-20 2007-08-21 Graphics processing architecture employing a unified shader
US12791597 Abandoned US20100231592A1 (en) 2003-11-20 2010-06-01 Graphics processing architecture employing a unified shader
US13109738 Active US8760454B2 (en) 2003-11-20 2011-05-17 Graphics processing architecture employing a unified shader
US14312014 Abandoned US20140300613A1 (en) 2003-11-20 2014-06-23 Graphics processing architecture employing a unified shader
US14614967 Active US9582846B2 (en) 2003-11-20 2015-02-05 Graphics processing architecture employing a unified shader
US15193647 Pending US20160307356A1 (en) 2003-11-20 2016-06-27 Graphics processing architecture employing a unified shader
US (8) US6897871B1 (en)
EP (6) EP2309460B1 (en)
CN (2) CN1947156B (en)
CA (1) CA2585860C (en)
WO (1) WO2005050570A1 (en)
US20040046765A1 (en) * 2002-09-06 2004-03-11 Laurent Lefebvre Gradient noise engine with shared memory
US7796133B1 (en) 2002-11-18 2010-09-14 Ati Technologies Ulc Unified shader
US7061495B1 (en) * 2002-11-18 2006-06-13 Ati Technologies, Inc. Method and apparatus for rasterizer interpolation
US7633506B1 (en) * 2002-11-27 2009-12-15 Ati Technologies Ulc Parallel pipeline graphics system
US8933945B2 (en) * 2002-11-27 2015-01-13 Ati Technologies Ulc Dividing work among multiple graphics pipelines using a super-tiling technique
US7787142B2 (en) * 2003-05-09 2010-08-31 Ppg Industries Ohio, Inc. Method and system for designing the color of a coating composition on an article
US7239322B2 (en) 2003-09-29 2007-07-03 Ati Technologies Inc Multi-thread graphic processing system
US8860737B2 (en) 2003-10-29 2014-10-14 Nvidia Corporation Programmable graphics processor for multithreaded execution of programs
US9659339B2 (en) 2003-10-29 2017-05-23 Nvidia Corporation Programmable graphics processor for multithreaded execution of programs
US7570267B2 (en) 2004-05-03 2009-08-04 Microsoft Corporation Systems and methods for providing an enhanced graphics pipeline
US8044951B1 (en) * 2004-07-02 2011-10-25 Nvidia Corporation Integer-based functionality in a graphics shading language
US7339590B1 (en) * 2004-09-02 2008-03-04 Nvidia Corporation Vertex processing unit supporting vertex texture mapping
US7385609B1 (en) * 2004-11-02 2008-06-10 Nvidia Corporation Apparatus, system, and method for increased processing flexibility of a graphic pipeline
US7542042B1 (en) * 2004-11-10 2009-06-02 Nvidia Corporation Subpicture overlay using fragment shader
US7439979B1 (en) * 2004-11-10 2008-10-21 Nvidia Corporation Shader with cache memory
JP4692956B2 (en) * 2004-11-22 2011-06-01 株式会社ソニー・コンピュータエンタテインメント Drawing processing apparatus and a drawing processing method
US20070070082A1 (en) * 2005-09-27 2007-03-29 Ati Technologies, Inc. Sample-level screen-door transparency using programmable transparency sample masks
CN100489896C (en) 2005-10-18 2009-05-20 威盛电子股份有限公司 Hardware corrected software vertex light chopper
US20090051687A1 (en) * 2005-10-25 2009-02-26 Mitsubishi Electric Corporation Image processing device
US7447873B1 (en) * 2005-11-29 2008-11-04 Nvidia Corporation Multithreaded SIMD parallel processor with loading of groups of threads
US7594095B1 (en) 2005-11-29 2009-09-22 Nvidia Corporation Multithreaded SIMD parallel processor with launching of groups of threads
US7404059B1 (en) 2005-12-07 2008-07-22 Nvidia Corporation Parallel copying scheme for creating multiple versions of state information
US7404056B1 (en) 2005-12-07 2008-07-22 Nvidia Corporation Virtual copying scheme for creating multiple versions of state information
US7593971B1 (en) 2005-12-07 2009-09-22 Nvidia Corporation Configurable state table for managing multiple versions of state information
US7584342B1 (en) 2005-12-15 2009-09-01 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue
US7788468B1 (en) 2005-12-15 2010-08-31 Nvidia Corporation Synchronization of threads in a cooperative thread array
US7861060B1 (en) * 2005-12-15 2010-12-28 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior
US8077174B2 (en) 2005-12-16 2011-12-13 Nvidia Corporation Hierarchical processor array
US7865894B1 (en) 2005-12-19 2011-01-04 Nvidia Corporation Distributing processing tasks within a processor
US8154554B1 (en) * 2006-07-28 2012-04-10 Nvidia Corporation Unified assembly instruction set for graphics processing
US7928990B2 (en) * 2006-09-27 2011-04-19 Qualcomm Incorporated Graphics processing unit with unified vertex cache and shader register file
US8155316B1 (en) 2006-10-19 2012-04-10 NVIDIA Corporaton Contract based memory management for isochronous streams
US8212840B2 (en) * 2006-10-23 2012-07-03 Qualcomm Incorporated 3-D clipping in a graphics processing unit
US20080094408A1 (en) * 2006-10-24 2008-04-24 Xiaoqin Yin System and Method for Geometry Graphics Processing
US7937567B1 (en) 2006-11-01 2011-05-03 Nvidia Corporation Methods for scalably exploiting parallelism in a parallel processing system
US7649538B1 (en) 2006-11-03 2010-01-19 Nvidia Corporation Reconfigurable high performance texture pipeline with advanced filtering
US8108659B1 (en) 2006-11-03 2012-01-31 Nvidia Corporation Controlling access to memory resources shared among parallel synchronizable threads
US7692659B1 (en) * 2006-11-06 2010-04-06 Nvidia Corporation Color-compression using automatic reduction of multi-sampled pixels
US8233004B1 (en) 2006-11-06 2012-07-31 Nvidia Corporation Color-compression using automatic reduction of multi-sampled pixels
US8438370B1 (en) 2006-12-08 2013-05-07 Nvidia Corporation Processing of loops with internal data dependencies using a parallel processor
US7999821B1 (en) 2006-12-19 2011-08-16 Nvidia Corporation Reconfigurable dual texture pipeline with shared texture cache
US8321849B2 (en) * 2007-01-26 2012-11-27 Nvidia Corporation Virtual architecture and instruction set for parallel thread computing
US8421794B2 (en) * 2007-03-23 2013-04-16 Qualcomm Incorporated Processor with adaptive multi-shader
US7624107B1 (en) 2007-08-09 2009-11-24 Nvidia Corporation Radix sort algorithm for graphics processing units
US8094157B1 (en) * 2007-08-09 2012-01-10 Nvidia Corporation Performing an occurence count of radices
US7689541B1 (en) 2007-08-09 2010-03-30 Nvidia Corporation Reordering data using a series of offsets
US8698819B1 (en) * 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US8411096B1 (en) * 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US8195882B2 (en) * 2008-05-30 2012-06-05 Advanced Micro Devices, Inc. Shader complex with distributed level one cache system and centralized level two cache
US8502832B2 (en) * 2008-05-30 2013-08-06 Advanced Micro Devices, Inc. Floating point texture filtering using unsigned linear interpolators and block normalizations
GB2486485B (en) 2010-12-16 2012-12-19 Imagination Tech Ltd Method and apparatus for scheduling the issue of instructions in a microprocessor using multiple phases of execution
US9727385B2 (en) 2011-07-18 2017-08-08 Apple Inc. Graphical processing unit (GPU) implementing a plurality of virtual GPUs
US8525846B1 (en) * 2011-11-11 2013-09-03 Google Inc. Shader and material layers for rendering three-dimensional (3D) object data models
US10102603B2 (en) 2013-06-10 2018-10-16 Sony Interactive Entertainment Inc. Scheme for compressing vertex shader output parameters
US10096079B2 (en) 2013-06-10 2018-10-09 Sony Interactive Entertainment Inc. Fragment shaders perform vertex shader computations
US9613392B2 (en) * 2014-09-03 2017-04-04 Mediatek Inc. Method for performing graphics processing of a graphics system in an electronic device with aid of configurable hardware, and associated apparatus
US5550962A (en) 1994-04-13 1996-08-27 Hitachi, Ltd. System for selectively performing parallel or sequential drawing processing
US5818469A (en) 1997-04-10 1998-10-06 International Business Machines Corporation Graphics interface processing methodology in symmetric multiprocessing or distributed network environments
US6118452A (en) 1997-08-05 2000-09-12 Hewlett-Packard Company Fragment visibility pretest system and methodology for improved performance of a graphics system
US6384824B1 (en) 1999-07-07 2002-05-07 Microsoft Corporation Method, system and computer program product for multi-pass bump-mapping into an environment map
US6417858B1 (en) 1998-12-23 2002-07-09 Microsoft Corporation Processor for geometry transformations and lighting calculations
US20030030643A1 (en) 2001-08-13 2003-02-13 Taylor Ralph C. Method and apparatus for updating state data
US20030076320A1 (en) 2001-10-18 2003-04-24 David Collodi Programmable per-pixel shader with lighting support
US6573893B1 (en) 2000-11-01 2003-06-03 Hewlett-Packard Development Company, L.P. Voxel transfer circuit for accelerated volume rendering of a graphics image
US6650330B2 (en) 1999-12-06 2003-11-18 Nvidia Corporation Graphics system and method for processing multiple independent execution threads
US20040041814A1 (en) 2002-08-30 2004-03-04 Wyatt David A. Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device
US6704018B1 (en) 1999-10-15 2004-03-09 Kabushiki Kaisha Toshiba Graphic computing apparatus
US6724394B1 (en) 2000-05-31 2004-04-20 Nvidia Corporation Programmable pixel shading architecture
US6731289B1 (en) 2000-05-12 2004-05-04 Microsoft Corporation Extended range pixel display system and method
US20040164987A1 (en) 2003-02-24 2004-08-26 Microsoft Corporation Usage semantics
US6864893B2 (en) 2002-07-19 2005-03-08 Nvidia Corporation Method and apparatus for modifying depth values using pixel programs
US20050068325A1 (en) 2003-09-29 2005-03-31 Ati Technologies, Inc. Multi-thread graphic processing system
US6897871B1 (en) 2003-11-20 2005-05-24 Ati Technologies Inc. Graphics processing architecture employing a unified shader
US7015909B1 (en) * 2002-03-19 2006-03-21 Aechelon Technology, Inc. Efficient use of user-defined shaders to implement graphics operations
US7015913B1 (en) 2003-06-27 2006-03-21 Nvidia Corporation Method and apparatus for multithreaded processing of data in a programmable graphics processor
US4985848A (en) 1987-09-14 1991-01-15 Visual Information Technologies, Inc. High speed image processing system using separate data processor and address generator
JP3359393B2 (en) 1993-10-07 2002-12-24 富士通株式会社 Graphic data parallelism display
US5808690A (en) 1996-01-02 1998-09-15 Integrated Device Technology, Inc. Image generation system, methods and computer program products using distributed processing
GB2311882B (en) 1996-04-04 2000-08-09 Videologic Ltd A data processing management system
CN1201268C (en) 1999-06-30 2005-05-11 国际商业机器公司 Image process for realizing moving fuzzification
US6784882B1 (en) 1999-09-10 2004-08-31 Sony Computer Entertainment Inc. Methods and apparatus for rendering an image including portions seen through one or more objects of the image
US6665765B1 (en) * 2000-02-29 2003-12-16 Hewlett-Packard Development Company, L.P. Hot docking drive wedge and port replicator
KR100803114B1 (en) * 2000-11-30 2008-02-14 엘지전자 주식회사 Method and system for arbitrating memory
US7376811B2 (en) 2001-11-06 2008-05-20 Netxen, Inc. Method and apparatus for performing computations and operations on data using data steering
US7233335B2 (en) 2003-04-21 2007-06-19 Nividia Corporation System and method for reserving and managing memory spaces in a memory resource
JP2005260592A (en) * 2004-03-11 2005-09-22 Fujitsu Ltd Antenna device, directivity control method, and communication device
US7742053B2 (en) 2003-09-29 2010-06-22 Ati Technologies Ulc Multi-thread graphics processing system
US20070222786A1 (en) 2003-09-29 2007-09-27 Ati Technologies Ulc Multi-thread graphics processing system
US20070222785A1 (en) 2003-09-29 2007-09-27 Ati Technologies Ulc Multi-thread graphics processing system
US7746348B2 (en) 2003-09-29 2010-06-29 Ati Technologies Ulc Multi-thread graphics processing system
US20100156915A1 (en) 2003-09-29 2010-06-24 Ati Technologies Ulc Multi-Thread Graphics Processing System
US20070222787A1 (en) 2003-09-29 2007-09-27 Ati Technologies Ulc Multi-thread graphics processing system
US7327369B2 (en) 2003-11-20 2008-02-05 Ati Technologies Inc. Graphics processing architecture employing a unified shader
US20070285427A1 (en) 2003-11-20 2007-12-13 Ati Technologies Ulc Graphics processing architecture employing a unified shader
EP2309460A1 (en) 2003-11-20 2011-04-13 ATI Technologies ULC A graphics processing architecture employing a unified shader
US20100231592A1 (en) 2003-11-20 2010-09-16 Ati Technologies Ulc Graphics processing architecture employing a unified shader
EP2296116A2 (en) 2003-11-20 2011-03-16 ATI Technologies Inc. A graphics processing architecture employing a unified shader
EP2299408A2 (en) 2003-11-20 2011-03-23 ATI Technologies Inc. A graphics processing architecture employing a unified shader
US20050200629A1 (en) 2003-11-20 2005-09-15 Steven Morein Graphics processing architecture employing a unified shader
Breternitz, Jr., Mauricio et al.; Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU; IEEE; 2003; pp. 1-11.
Chinese Office Action; Chinese Application No. 2004800405708; dated Nov. 2009.
Chinese Office Action; Chinese Application No. 2004800405708; dated Sep. 2008.
Chinese Office Action; Chinese Application No. 2004800405708; dated Sep. 2010.
Eldridge, Matthew et al.; Pomegranate: A Fully Scalable Graphics Architecture; Computer Graphics, SIGGRAPH 2000 Conference Proceedings; Jul. 23, 2000.
EP Supplemental Search Report; EP Application No. 10075685.7; dated Feb. 25, 2011.
EP Supplemental Search Report; EP Application No. 10075686.5; dated Feb. 25, 2011.
EP Supplemental Search Report; EP Application No. 10075687.3; dated Feb. 25, 2011.
EP Supplemental Search Report; EP Application No. 10075688.1; dated Feb. 25, 2011.
European Patent Office Examination Report; EP Application No. 04798938.9; dated Nov. 9, 2006; pp. 1-3.
International Search Report and Written Opinion; International Application No. PCT/IB2004/003821; dated Mar. 22, 2005.
Mark, William R. et al.; CG: A system for programming graphics hardware in a C-like language; SIGGRAPH '03; San Diego, CA; ACM Transactions on Graphics; Jul. 2002; vol. 22, No. 3; pp. 896-907.
Owens, John D. et al.; Polygon Rendering on a Stream Architecture; Proceedings 2000 SIGGRAPH/Eurographics Workshop on Graphics Hardware; Aug. 21, 2000.
Purcell, Timothy J. et al.; Ray Tracing on Programmable Graphics Hardware; SIGGRAPH '02; San Antonio, TX; ACM Transactions on Graphics; Jul. 2002; vol. 21, No. 3; pp. 703-712.
US9582846B2 (en) 2017-02-28 grant
US6897871B1 (en) 2005-05-24 grant
CN102176241A (en) 2011-09-07 application
EP2296115A3 (en) 2011-04-06 application
EP2309460A1 (en) 2011-04-13 application
EP2299408B1 (en) 2014-02-12 grant
EP2296116B1 (en) 2012-12-19 grant
WO2005050570A1 (en) 2005-06-02 application
CN1947156A (en) 2007-04-11 application
US20150154731A1 (en) 2015-06-04 application
US20050110792A1 (en) 2005-05-26 application
EP2309460B1 (en) 2014-06-25 grant
EP1706847A1 (en) 2006-10-04 application
CN1947156B (en) 2013-07-10 grant
EP2299408A3 (en) 2011-04-13 application
CA2585860C (en) 2014-10-28 grant
EP2296115A2 (en) 2011-03-16 application
US20110216077A1 (en) 2011-09-08 application
EP2296115B1 (en) 2013-10-16 grant
EP2299408A2 (en) 2011-03-23 application
US20100231592A1 (en) 2010-09-16 application
US20070285427A1 (en) 2007-12-13 application
CA2585860A1 (en) 2006-06-02 application
US20160307356A1 (en) 2016-10-20 application
EP2876606A1 (en) 2015-05-27 application
US7327369B2 (en) 2008-02-05 grant
EP1706847B1 (en) 2012-12-19 grant
EP2296116A3 (en) 2011-04-06 application
US20050200629A1 (en) 2005-09-15 application
CN102176241B (en) 2014-04-16 grant
US20140300613A1 (en) 2014-10-09 application
EP2296116A2 (en) 2011-03-16 application
US6169554B1 (en) 2001-01-02 Clip testing unit for a three-dimensional graphics accelerator
US20020130874A1 (en) 2002-09-19 Vector instruction set
Fatahalian et al. 2008 A closer look at GPUs
Deering et al. 1993 Leo: a system for cost effective 3D shaded graphics
US20080303841A1 (en) 2008-12-11 Extrapolation of nonresident mipmap data using resident mipmap data
US6816161B2 (en) 2004-11-09 Vertex assembly buffer and primitive launch buffer
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MOREIN, STEPHEN;LEFEBVRE, LAURENT;SKENDE, ANDI;AND OTHERS;SIGNING DATES FROM 20030820 TO 20030821;REEL/FRAME:032217/0137
Free format text: CHANGE OF NAME;ASSIGNOR:ATI TECHNOLOGIES, INC.;REEL/FRAME:032265/0101
2017-05-16 IPR Aia trial proceeding filed before the patent and appeal board: inter partes review
Free format text: TRIAL NO: IPR2017-01225
Opponent name: LG ELECTRONICS U.S.A., INC. ANDLG ELECTRONICS MOBI