Source: http://www.google.com/patents/US8020056?dq=6,044,471
Timestamp: 2016-12-07 21:13:09
Document Index: 322977533

Matched Legal Cases: ['Application No. 4319', 'Application No. 200480015427', 'Application No. 4', 'Application No. 4', 'Application No. 2006', 'Application No. 2006', 'Application No. 200480015427']

Patent US8020056 - Memory channel with bit lane fail-over - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsMemory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device...http://www.google.com/patents/US8020056?utm_source=gb-gplus-sharePatent US8020056 - Memory channel with bit lane fail-overAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8020056 B2Publication typeGrantApplication numberUS 12/836,953Publication dateSep 13, 2011Filing dateJul 15, 2010Priority dateJun 5, 2003Fee statusPaidAlso published asCN1799035A, CN100511192C, EP1629389A2, US7386768, US7761753, US8135999, US8286039, US8489944, US8510612, US20040250181, US20090013211, US20100281315, US20110131370, US20120102256, US20120331356, US20130097371, WO2004109526A2, WO2004109526A3Publication number12836953, 836953, US 8020056 B2, US 8020056B2, US-B2-8020056, US8020056 B2, US8020056B2InventorsPete D. Vogt, Dennis W. Brzezinski, Warren R. MorrowOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (69), Non-Patent Citations (23), Classifications (24), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMemory channel with bit lane fail-over
US 8020056 B2Abstract
1. An integrated circuit to provide a memory buffer to isolate one or more dynamic random access memory devices (DRAM devices) from a unidirectional differential point-to-point channel, the integrated circuit comprising:
an inbound redrive circuit to receive and redrive signals on an inbound path of the unidirectional differential point-to-point channel, the inbound redrive circuit including, at least in part, two or more bit-lanes for the inbound path of the unidirectional differential point-to-point channel;
an idle pattern generator coupled with the inbound redrive circuit, the idle pattern generator to provide a permuting data pattern if the memory buffer is not sending requested data to a host, wherein the permuting data pattern is generated by a 12-bit linear-feedback shift register (LFSR) with a polynomial of x12+x7+x4+x3+1;
an outbound redrive circuit to receive and redrive signals on an outbound path of the unidirectional differential point-to-point channel, the outbound redrive circuit including, at least in part, two or more bit-lanes for the outbound path of the unidirectional differential point-to-point channel; and
double data rate (DDR) memory interface to couple the memory buffer with the one or more DRAM devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit.
2. The integrated circuit of claim 1, wherein the integrated circuit is attached to a printed circuit board (PCB).
3. The integrated circuit of claim 2, wherein at least on DRAM device is attached to the PCB.
4. The integrated circuit of claim 3, wherein the memory buffer is coupled to the unidirectional differential point-to-point channel.
5. The integrated circuit of claim 4, wherein the host is coupled to the unidirectional differential point-to-point channel.
6. The integrated circuit of claim 4, wherein the host is coupled to the unidirectional differential point-to-point channel.
7. An integrated circuit to provide a memory buffer to isolate one or more dynamic random access memory devices (DRAM devices) from a unidirectional differential point-to-point channel, the integrated circuit comprising:
an idle pattern generator coupled with the inbound redrive circuit, the idle pattern generator to provide a permuting data pattern if the memory buffer is not sending requested data to a host, wherein the permuting data pattern is generated by a 12-bit linear-feedback shift register (LFSR);
an outbound redrive circuit to receive and redrive signals on an outbound path of the unidirectional differential point-to-point channel, the outbound redrive circuit including, at least in part, two or more bit-lanes for the outbound path of the unidirectional differential point-to-point channel;
a double data rate (DDR) memory interface to couple the memory buffer with the one or more DRAM devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit; and
a failover circuit coupled with the inbound redrive circuit, the failover circuit capable of redirecting a signal from a first bit-lane of the inbound path of the unidirectional point-to-point channel to a second bit-lane of the inbound path of the unidirectional point-to-point channel.
8. The integrated circuit of claim 7, wherein the integrated circuit is attached to a printed circuit board (PCB).
9. The integrated circuit of claim 8, wherein at least one DRAM device is attached to the PCB.
10. The integrated circuit of claim 9, wherein the memory buffer is coupled to the unidirectional differential point-to-point channel.
11. The integrated circuit of claim 10, wherein the host is coupled to the unidirectional differential point-to-point channel. Description
This application relates to and is a continuation of U.S. Utility patent application Ser. No. 12/136,028 entitled “MEMORY CHANNEL WITH BIT LANE FAIL-OVER”, filed Jun. 9, 2008, which is indicated to issue as U.S. Pat. No. 7,761,753, on Jun. 20, 2010, which is a continuation of U.S. patent application Ser. No. 10/456,353 entitled “MEMORY CHANNEL WITH BIT LANE FAIL-OVER”, filed Jun. 5, 2003, issued as U.S. Pat. No. 7,386,768, on Jun. 10, 2008, which are incorporated herein by reference for all purposes.
A memory agent according to the inventive principles of this patent may also be capable of intentionally generating an error such as a cyclical redundancy check (CRC) error in a status pattern. Such a technique may be useful as an alternative or supplemental way to distinguish a data pattern from a status pattern. For example, in some memory systems, each frame is sent along with a CRC code that used to check the integrity of the data in the frame.
According to the inventive principles of this patent, a memory agent may intentionally send the wrong CRC code with frame that contains a status pattern. The receiving agent may then interpret the frame as a status frame rather than a data frame. Some memory systems may utilize a path or paths having an extra bit lane to carry CRC data. If such a system is capable of operating in a fail-over mode, the agent or agents may only utilize an intentional CRC error if not operating in fail-over mode. As used herein, the term CRC refers not only to a cyclical redundancy check, but also to any other type of error checking scheme used to verify the integrity of a frame or pattern.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5742840Aug 16, 1995Apr 21, 1998Microunity Systems Engineering, Inc.General purpose, multiple precision parallel operation, programmable media processorUS5748872Mar 19, 1996May 5, 1998Norman; Richard S.Direct replacement cell fault tolerant architectureUS5860080Mar 19, 1996Jan 12, 1999Apple Computer, Inc.Multicasting system for selecting a group of memory devices for operationUS5867422Aug 8, 1995Feb 2, 1999University Of South FloridaComputer memory chip with field programmable memory cell arrays (fpmcas), and method of configuringUS5898863Jun 3, 1997Apr 27, 1999Emc CorporationMethod and apparatus for determining I/O size distribution of an input/output system and its use for load simulationUS5991891 *Dec 23, 1996Nov 23, 1999Lsi Logic CorporationMethod and apparatus for providing loop coherencyUS6006318Oct 13, 1998Dec 21, 1999Microunity Systems Engineering, Inc.General purpose, dynamic partitioning, programmable media processorUS6034878Dec 16, 1997Mar 7, 2000Hitachi, Ltd.Source-clock-synchronized memory system and memory unitUS6038682Mar 19, 1997Mar 14, 2000Hyperchip Inc.Fault tolerant data processing system fabricated on a monolithic substrateUS6092229Oct 9, 1996Jul 18, 2000Lsi Logic CorporationSingle chip systems using general purpose processorsUS6125419Jun 13, 1997Sep 26, 2000Hitachi, Ltd.Bus system, printed circuit board, signal transmission line, series circuit and memory moduleUS6128750 *Jun 26, 1998Oct 3, 2000Emc CorporationFail-over switching systemUS6151648Oct 2, 1998Nov 21, 2000Jazio, Inc.High speed bus system and method for using voltage and timing oscillating references for signal detectionUS6154826Feb 28, 1997Nov 28, 2000University Of Virginia Patent FoundationMethod and device for maximizing memory system bandwidth by accessing data in a dynamically determined orderUS6154855Aug 18, 1999Nov 28, 2000Hyperchip Inc.Efficient direct replacement cell fault tolerant architectureUS6160423Apr 7, 1998Dec 12, 2000Jazio, Inc.High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission linesUS6185644Jan 19, 2000Feb 6, 2001Rambus Inc.Memory system including a plurality of memory devices and a transceiver deviceUS6255859Dec 30, 1999Jul 3, 2001Jazio, Inc.High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission linesUS6263413Apr 27, 1998Jul 17, 2001Nec CorporationMemory integrated circuit and main memory and graphics memory systems applying the aboveUS6316980 *Jun 30, 2000Nov 13, 2001Intel CorporationCalibrating data strobe signal using adjustable delays with feedbackUS6317352 *Sep 18, 2000Nov 13, 2001Intel CorporationApparatus for implementing a buffered daisy chain connection between a memory controller and memory modulesUS6327205May 24, 2000Dec 4, 2001Jazio, Inc.Signal latching of high bandwidth DRAM arrays when skew between different components is higher than signal rateUS6345321May 24, 2000Feb 5, 2002Busless Computers SarlMultiple-mode memory componentUS6369605Sep 18, 2000Apr 9, 2002Intel CorporationSelf-terminated driver to prevent signal reflections of transmissions between electronic devicesUS6389494 *Dec 30, 1998May 14, 2002Emc CorporationSystem for interfacing a data storage system to a host utilizing a plurality of busses for carrying end-user data and a separate bus for carrying interface state dataUS6408402Oct 4, 2000Jun 18, 2002Hyperchip Inc.Efficient direct replacement cell fault tolerant architectureUS6449213Sep 18, 2000Sep 10, 2002Intel CorporationMemory interface having source-synchronous command/address signalingUS6487102Sep 18, 2000Nov 26, 2002Intel CorporationMemory module having buffer for isolating stacked memory devicesUS6493250Dec 28, 2000Dec 10, 2002Intel CorporationMulti-tier point-to-point buffered memory interfaceUS6502161 *Jan 5, 2000Dec 31, 2002Rambus Inc.Memory system including a point-to-point linked memory subsystemUS6505305 *Jul 16, 1998Jan 7, 2003Compaq Information Technologies Group, L.P.Fail-over of multiple memory blocks in multiple memory modules in computer systemUS6513080Aug 10, 2000Jan 28, 2003Jazio, Inc.High speed bus system and method for using voltage and timing oscillating references for signal detectionUS6571355 *Dec 29, 1999May 27, 2003Emc CorporationFibre channel data storage system fail-over mechanismUS6625687Sep 18, 2000Sep 23, 2003Intel CorporationMemory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexingUS6643752Dec 9, 1999Nov 4, 2003Rambus Inc.Transceiver with latency alignment circuitryUS6871294 *Sep 25, 2001Mar 22, 2005Sun Microsystems, Inc.Dynamically reconfigurable interconnectionUS6898728 *Sep 25, 2001May 24, 2005Sun Microsystems, Inc.System domain targeted, configurable interconnectionUS6961347 *Jun 20, 2000Nov 1, 2005Hewlett-Packard Development Company, L.P.High-speed interconnection link having automated lane reorderingUS7100071 *Jul 31, 2002Aug 29, 2006Hewlett-Packard Development Company, L.P.System and method for allocating fail-over memoryUS7127629Jun 3, 2003Oct 24, 2006Intel CorporationRedriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signalUS7143207Nov 14, 2003Nov 28, 2006Intel CorporationData accumulation between data path having redrive circuit and memory deviceUS7165153Jun 4, 2003Jan 16, 2007Intel CorporationMemory channel with unidirectional linksUS7194581Jun 3, 2003Mar 20, 2007Intel CorporationMemory channel with hot add/removeUS7200787Jun 3, 2003Apr 3, 2007Intel CorporationMemory channel utilizing permuting status patternsUS7212423May 31, 2004May 1, 2007Intel CorporationMemory agent core clock aligned to laneUS7219294Nov 14, 2003May 15, 2007Intel CorporationEarly CRC delivery for partial frameUS7320100 *May 19, 2004Jan 15, 2008Cray Inc.Apparatus and method for memory with bit swapping on the fly and testingUS7340537Jun 4, 2003Mar 4, 2008Intel CorporationMemory channel with redundant presence detectUS7383399Jun 30, 2004Jun 3, 2008Intel CorporationMethod and apparatus for memory compressionUS7386768 *Jun 5, 2003Jun 10, 2008Intel CorporationMemory channel with bit lane fail-overUS7395485May 31, 2004Jul 1, 2008Intel CorporationCheck codes mapped across multiple framesUS7447953Nov 14, 2003Nov 4, 2008Intel CorporationLane testing with variable mappingUS20030037278 *Jul 31, 2002Feb 20, 2003Compaq Information Technologies Group, L.P. A Delaware CorporationSystem and method for fail-over memoryUS20030097467 *Oct 11, 2002May 22, 2003Broadcom Corp.System having configurable interfaces for flexible system configurationsUS20030101384Nov 14, 2002May 29, 2003Young-Soo JoData bus arrangement and control method for efficiently compensating for faulty signal linesUS20040068682 *May 8, 2003Apr 8, 2004Hitachi, Ltd.Deskew circuit and disk array control device using the deskew circuit, and deskew methodUS20040073829 *Dec 16, 2002Apr 15, 2004Olarig Sompong P.Fail-over of multiple memory blocks in multiple memory modules in computer systemUS20040136319 *Jan 9, 2003Jul 15, 2004International Business Machines CorporationSelf-healing chip-to-chip interfaceUS20040246786Jun 4, 2003Dec 9, 2004Intel CorporationMemory channel having deskew separate from redriveUS20050022065 *May 19, 2004Jan 27, 2005Dixon R. PaulApparatus and method for memory with bit swapping on the fly and testingUS20050108458Nov 14, 2003May 19, 2005Intel CorporationLane testing with variable mappingUS20050268061May 31, 2004Dec 1, 2005Vogt Pete DMemory channel with frame misalignmentUS20060004953Jun 30, 2004Jan 5, 2006Vogt Pete DMethod and apparatus for increased memory bandwidthEP1113363A2Dec 28, 2000Jul 4, 2001Emc CorporationFibre channel data storage system fail-over mechanismEP1296246A2Sep 24, 2002Mar 26, 2003Sun Microsystems, Inc.System and method for the dynamic reconfiguration of interconnectsJP2000222294A Title not availableWO1999030240A1Nov 23, 1998Jun 17, 1999Intel CorporationMemory system including a memory module having a memory module controllerWO1999041666A1Jan 28, 1999Aug 19, 1999Intel CorporationMemory module controllerWO1999041667A1Jan 28, 1999Aug 19, 1999Intel CorporationMemory module including a memory module controller* Cited by examinerNon-Patent CitationsReference1Farmwald, M. , et al., "A Fast Path to One Memory", IEEE Spectrum, (Oct. 1992), 50-51.2Final Office Action for U.S. Appl. No. 10/456,353 mailed Apr. 27, 2006, 8 pgs.3Final Office Action U.S. Appl. No. 10/456,353 mailed Feb. 16, 2007, 7 pgs.4First Examination Report for Indian Patent Application No. 4319/DELNP/2005 mailed Sep. 11, 2008, 2 pgs.5First Office Action for Chinese Patent Application No. 200480015427.3 mailed Dec. 14, 2007, 32 pgs.6Gjessing, S. , et al., "A RAM Link for High Speed", IEEE Spectrum, (Oct. 1992), 52-53.7IEEE, "Standard for scalable coherent interface (SCI)", IEEE Std 1596-1992, Institute of Electrical and Electronics Engineers, Inc. USA, (1992), i-243.8Internation Search Report for International Application No. PCT/US2004/016116 dated Feb. 14, 2005, 3 pgs.9Jones, F. , "A New Era of Fast Dynamic RAMs", IEEE Spectrum, (Oct. 1992), 43-49.10Ng, R , "Fast Computer Memories", IEEE Spectrum, (Oct. 1992), 36-39.11Notice of Allowance for U.S. Appl. No. 10/456,353 mailed Dec. 27, 2007, 3 pgs.12Notice of Allowance for U.S. Appl. No. 12/136,028 mailed Mar. 4, 2010, 4 pgs.13Office Action for European Patent Application No. 4 753 015.9 mailed Apr. 30, 2007, 4 pgs.14Office Action for European Patent Application No. 4 753 015.9 mailed May 15, 2008, 4 pgs.15Office Action for Japanese Patent Application No. 2006-514926 mailed Jul. 1, 2008, 5 pgs.16Office Action for Japanese Patent Application No. 2006-514926 mailed Nov. 30, 2009, 10 pgs.17Office Action for U.S. Appl. No. 10/456,353 mailed Aug. 22, 2006, 9 pgs.18Office Action for U.S. Appl. No. 10/456,353 mailed Jul. 19, 2007, 9 pgs.19Office Action for U.S. Appl. No. 10/456,353 mailed Nov. 16, 2005, 15 pgs.20Office Action for U.S. Appl. No. 12/136,028 mailed Jul. 24, 2009, 7 pgs.21Salters, R. H., "Fast Drams for Sharper TV", IEEE Spectrum, (Oct. 1992), 40-42.22Second Office Action for Chinese Patent Application No. 200480015427.3 mailed Aug. 8, 2008, 13 pgs.23The Institute of Electrical and, "IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink)", Microprocessor and Microcomputer Standards Committee of the ISSS Computer Society, 1996., (Mar. 19, 1996), 1-91 pages.Classifications U.S. Classification714/718, 714/48, 711/152, 365/233.1, 719/328, 714/54, 710/301, 714/710, 365/189.05, 711/5, 711/105, 327/14, 710/308, 711/115, 365/51International ClassificationG11C29/00, G06F13/16Cooperative ClassificationY02B60/1235, Y02B60/1228, G06F13/4256, G06F12/00, G06F13/4243European ClassificationG06F13/42D4, G06F13/42C3SLegal EventsDateCodeEventDescriptionFeb 25, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services