Source: http://www.google.com/patents/US4965218?dq=6317900
Timestamp: 2015-03-28 01:34:55
Document Index: 205634290

Matched Legal Cases: ['application No. 002', 'application No. 137', 'application No. 002', 'application No. 002', 'application No. 004', 'application No. 113', 'application No. 789']

Patent US4965218 - Self-aligned gate realignment employing planarizing overetch - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method of providing a self-aligned gate (SAG) transistor or FET is disclosed. The method permits large aligment tolerances during manufacture of the SAG FET. A reduction in gate resistance is accomplished by including a second layer of gate metallization, which is highly conductive, after the n+ implant...http://www.google.com/patents/US4965218?utm_source=gb-gplus-sharePatent US4965218 - Self-aligned gate realignment employing planarizing overetchAdvanced Patent SearchPublication numberUS4965218 APublication typeGrantApplication numberUS 07/235,393Publication dateOct 23, 1990Filing dateAug 23, 1988Priority dateOct 21, 1985Fee statusLapsedPublication number07235393, 235393, US 4965218 A, US 4965218A, US-A-4965218, US4965218 A, US4965218AInventorsArthur E. Geissberger, Robert A. Sadler, Paulette Luper, Matthew L. BalzanOriginal AssigneeItt CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (8), Non-Patent Citations (2), Referenced by (32), Classifications (40), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSelf-aligned gate realignment employing planarizing overetch
US 4965218 AAbstract
A method of providing a self-aligned gate (SAG) transistor or FET is disclosed. The method permits large aligment tolerances during manufacture of the SAG FET. A reduction in gate resistance is accomplished by including a second layer of gate metallization, which is highly conductive, after the n+ implant and activation anneal without any critical realignment to the first layer of gate metal. The provision of the second layer after the anneal precludes degradation of the conductivity of the second gate metal by interdiffusion with the first (refractory) gate metal during the anneal. The large tolerance for misalignment of the gate mask level is obtained by a planarization of the anneal cap until the top surface of the first layer of gate metal is exposed, all without the need for a separate mask and etch step to open contact "windows" through the planarization anneal cap layers. The remaining adjacent encapsulant then acts as an insulator over the FET channel region and allows for gross misalignment of the second gate metallization without FET performance degradation. Using this technique, substantially increased performance can be obtained from a self-aligned FET while maintaining the basic simplicity of the RG process.
1. A process for the manufacture of self-aligned gate GaAs FET's having reduced gate length and improved gate resistance comprising:(a) providing a substrate; (b) forming a layer of GaAs on said substrate; (c) forming an active channel region in said layer of GaAs; (d) forming a first patterned gate layer comprising a gate of a refractory metal; (e) ion implanting source and drain regions on respective sides of said gate; (f) providing a first dielectric layer over said first patterned gate layer and said source and drain regions; (g) providing a sacrificial layer of etchable material over said first dielectric layer; (h) exposing a top portion of said first patterned gate layer by non-selectively etching said sacrificial layer and said dielectric layer, said top portion having a lateral expanse encompassing said gate; (i) providing a non-critically aligned photoresist mask over the dielectric layer and patterning said photoresist mask to expose said top portion; (j) forming a second gate layer of a material having low sheet resistivity overlying said photoresist mask and directly contacting said top portion through said photoresist mask; and (k) removing said photoresist mask and lifting off said second gate layer overlying said photoresist mask to leave a non-critically aligned second gate layer directly contacting said top portion. 2. A process as claimed in claim 1, wherein said step of planarizing said first dielectric layer comprises covering said first dielectric layer with a sacrificial planarization layer; andetching said sacrificial planarization layer and first dielectric layer in an etch environment exhibiting a unity etch ratio with respect to said sacrificial planarization layer and said first dielectric layer to improve the planarity of said first dielectric layer. 3. A process as claimed in claim 1, wherein said source and drain regions are activated prior to said step of covering said first gate layer with a first dielectric layer.
This application is a continuation-in-part of commonly owned U.S. patent application No. 002,084, filed Jan. 12, 1987, now abandoned, and a division of commonly owned U.S. patent application No. 137,309, filed Dec. 23, 1987, now issued as U.S. Pat. No. 4,847,212, which was itself a continuation-in-part of each of U.S. patent application No. 002,083, filed Jan. 12, 1987, now issued as U.S. Pat. No. 4,782,032, U.S. patent application No. 002,084 (identified above), U.S. patent application No. 004,992, filed Jan. 20, 1987, currently pending, and U.S. patent application No. 113,367, filed Oct. 21, 1987, currently pending, the latter application being a continuation of U.S. patent application No. 789,523, filed Oct. 21, 1985, now abandoned.
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a contact hole, a ptsi layer, a tiw layer, a tiw(n) layer, an au layer; very stable diffusion barrier by using a nitrided tiw, tiw(n); improved adhesion strength and step coverageUS6333229Mar 13, 2000Dec 25, 2001International Business Machines CorporationMethod for manufacturing a field effect transitor (FET) having mis-aligned-gate structureUS6392278 *Jun 26, 2000May 21, 2002Nec CorporationFet having a reliable gate electrodeUS6472258Nov 13, 2000Oct 29, 2002International Business Machines CorporationDouble gate trench transistorUS6492666 *Jul 17, 2001Dec 10, 2002Mitsumi Electric Co., Ltd.Semiconductor wafer with scribe lines having inspection pads formed thereonUS6703251Oct 10, 2002Mar 9, 2004Mitsumi Electric Co., Ltd.Semiconductor waferUS6739048Jan 27, 2000May 25, 2004International Business Machines CorporationProcess of fabricating a circuitized structureUS6797555 *Sep 10, 2003Sep 28, 2004National Semiconductor CorporationDirect implantation of fluorine into the channel region of a PMOS deviceUS6891155 *Sep 17, 2002May 10, 2005Advion Biosciences, Inc.Dielectric filmUS7112845Jun 18, 2002Sep 26, 2006International Business Machines CorporationDouble gate trench transistorUS7589381 *Sep 13, 2006Sep 15, 2009Kabushiki Kaisha ToshibaField effect transistor and manufacturing method thereofUS7935620 *Dec 5, 2007May 3, 2011Freescale Semiconductor, Inc.Method for forming semiconductor devices with low leakage Schottky contactsUS8592878Mar 8, 2011Nov 26, 2013Freescale Semiconductor, Inc.Semiconductor devices with low leakage Schottky contacts* Cited by examinerClassifications U.S. Classification438/182, 257/E21.575, 257/E29.149, 257/E29.05, 257/E21.173, 257/E21.454, 257/E29.127, 438/574, 257/E21.697, 257/E21.228, 257/E29.317International ClassificationH01L29/812, H01L29/47, H01L21/306, H01L21/8252, H01L21/768, H01L29/423, H01L29/10, H01L21/285, H01L21/338Cooperative ClassificationH01L29/812, H01L29/66878, H01L21/768, H01L21/28581, H01L29/475, H01L21/28587, H01L29/42316, H01L29/1029, H01L21/8252, H01L21/02063European ClassificationH01L29/66M6T6S2L3, H01L21/8252, H01L29/10D2, H01L21/285B6C, H01L21/285B6B, H01L29/423D2, H01L29/47B, H01L29/812, H01L21/768, H01L21/02F4B2Legal EventsDateCodeEventDescriptionDec 17, 2002FPExpired due to failure to pay maintenance feeEffective date: 20021023Oct 23, 2002LAPSLapse for failure to pay maintenance feesMay 7, 2002REMIMaintenance fee reminder mailedJul 3, 2000ASAssignmentOwner name: TYCO ELECTRONICS LOGISTICS AG, SWITZERLANDFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ITT MANUFACTURING ENTERPRISES, INC.;REEL/FRAME:010909/0439Effective date: 20000306Owner name: TYCO ELECTRONICS LOGISTICS AG AMPERESTRASSE 3 CH-9Apr 22, 1998FPAYFee paymentYear of fee payment: 8Apr 4, 1994FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services