Source: http://www.google.com/patents/US7924921?dq=ascentive
Timestamp: 2017-04-23 21:22:33
Document Index: 159263651

Matched Legal Cases: ['art 4', 'art 4', 'art 4', 'art 4', 'art 6', 'art 6', 'art 6', 'art 6', 'art 2']

Patent US7924921 - Signaling coding and display options in entry point headers - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA decoder receives an entry point header comprising plural control parameters for an entry point segment corresponding to the entry point header. The entry point header is in an entry point layer of a bitstream comprising plural layers. The decoder decodes the entry point header. The plural control parameters...http://www.google.com/patents/US7924921?utm_source=gb-gplus-sharePatent US7924921 - Signaling coding and display options in entry point headersAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7924921 B2Publication typeGrantApplication numberUS 10/989,845Publication dateApr 12, 2011Filing dateNov 15, 2004Priority dateSep 7, 2003Fee statusPaidAlso published asUS20050123274Publication number10989845, 989845, US 7924921 B2, US 7924921B2, US-B2-7924921, US7924921 B2, US7924921B2InventorsRegis J. Crinon, Chih-Lung Lin, Jie Liang, Shankar Regunathan, Shuo-Jen Wu, Timothy E. Onders, Thomas W. HolcombOriginal AssigneeMicrosoft CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (107), Non-Patent Citations (61), Referenced by (10), Classifications (19), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSignaling coding and display options in entry point headers
US 7924921 B2Abstract
A decoder receives an entry point header comprising plural control parameters for an entry point segment corresponding to the entry point header. The entry point header is in an entry point layer of a bitstream comprising plural layers. The decoder decodes the entry point header. The plural control parameters can include various combinations of control parameters such as a pan scan on/off parameter, a reference frame distance on/off parameter, a loop filtering on/off parameter, a fast chroma motion compensation on/off parameter, an extended range motion vector on/off parameter, a variable sized transform on/off parameter, an overlapped transform on/off parameter, a quantization decision parameter, and an extended differential motion vector coding on/off parameter, a broken link parameter, a closed entry parameter, one or more coded picture size parameters, one or more range mapping parameters, a hypothetical reference decoder buffer parameter, and/or other parameter(s).
1. In a computing device that implements a video encoder, the computing device including a processor and memory, a method comprising:
with the computing device that implements the video encoder, in a bitstream comprising plural layers, inserting plural different entry point segment control parameters in an entry point header below sequence layer but above picture layer in the bitstream, each of the plural different entry point segment control parameters affecting decoding or display of one or more pictures in an entry point segment of the bitstream, wherein the plural different entry point segment control parameters comprise:
a pan scan on/off parameter that indicates whether pan scan information is present,
a reference frame distance on/off parameter that indicates whether a reference frame distance syntax element is present in respective picture headers for selected types of pictures within the entry point segment,
a loop filtering on/off parameter that indicates whether loop filtering is enabled,
a fast chroma motion compensation on/off parameter that controls rounding of chroma motion vectors,
an extended range motion vector on/off parameter that indicates whether extended range motion vectors are enabled,
a variable sized transform on/off parameter that indicates whether variable sized transform coding is enabled,
an overlapped transform on/off parameter that indicates whether overlapped transforms are used,
a quantization decision parameter that indicates whether quantization step size is variable within a picture, and
an extended differential motion vector coding on/off parameter that indicates whether use of extended range coding of differential motion vector information is signaled for selected types of pictures within the entry point segment; and
with the computing device that implements the video encoder, outputting the entry point header as part of the bitstream.
2. The method of claim 1 wherein the plural layers comprise an entry point layer, and wherein the entry point header is in the entry point layer.
3. The method of claim 1 wherein the entry point segment comprises an entry point key frame, and wherein the entry point key frame is a P/I-frame.
4. In a computing device that implements a video decoder, the computing device including a processor and memory, a method comprising:
receiving, at the computing device that implements the video decoder, an entry point header comprising plural control parameters for an entry point segment corresponding to the entry point header, wherein the entry point header is in an entry point layer of a bitstream comprising plural layers, the plural layers also including sequence layer and picture layer, and wherein the plural control parameters include:
a quantization decision parameter that indicates whether quantization step size is variable within a picture,
a quantizer type parameter that indicates a quantizer used, and
an extended differential motion vector coding on/off parameter that indicates whether use of extended range coding of differential motion vector information is signaled for selected types of pictures within the entry point segment;
with the computing device that implements the video decoder, decoding the entry point header; and
with the computing device that implements the video decoder, decoding one or more pictures in the entry point segment based at least in part on the plural control parameters.
5. The method of claim 4 wherein the plural control parameters further comprise a broken link parameter.
6. The method of claim 4 wherein the plural control parameters further comprise a closed entry parameter.
7. The method of claim 4 wherein the quantization decision parameter indicates one or more layers of signaling for quantization step sizes.
8. The method of claim 4 wherein the quantization type parameter indicates a quantizer type for frames in the entry point segment.
9. The method of claim 4 wherein the plural control parameters further comprise one or more coded picture size parameters.
10. The method of claim 4 wherein the plural control parameters further comprise one or more range mapping parameters indicating how to scale samples of the one or more pictures in the entry point segment after decoding.
11. The method of claim 10 wherein the one or more range mapping parameters comprise a luma range mapping parameter indicating how to scale luma samples of the one or more pictures in the entry point segment after decoding.
12. The method of claim 10 wherein the one or more range mapping parameters comprise a chroma range mapping parameter indicating how to scale chroma samples of the one or more pictures in the entry point segment after decoding.
13. The method of claim 4 wherein the plural control parameters further comprise a hypothetical reference decoder buffer parameter.
14. In a computing device that implements a video decoder, the computing device including a processor and memory, a method comprising:
receiving, at the computing device that implements the video decoder, an entry point header comprising plural control parameters for an entry point segment corresponding to the entry point header, the entry point segment comprising plural frames, wherein the entry point header is signaled in a bitstream at entry point layer below sequence layer but above frame layer that includes frame layer syntax elements for the plural frames; and
with the computing device that implements the video decoder, decoding the entry point header;
wherein the plural control parameters comprise at least:
a reference frame distance on/off parameter that indicates whether a reference frame distance syntax element is present per frame for selected types of frames within the entry point segment;
a loop filtering on/off parameter that indicates whether loop filtering is enabled;
a fast chroma motion compensation on/off parameter that controls rounding of chroma motion vectors;
an extended range motion vector on/off parameter that indicates whether extended range motion vectors are enabled;
a variable sized transform on/off parameter that indicates whether variable sized transform coding is enabled;
an overlapped transform on/off parameter that indicates whether overlapped transforms are used; and
a quantization decision parameter that indicates whether quantization step size is variable within a picture.
15. The method of claim 14 wherein the plural control parameters further comprise an extended differential motion vector coding on/off parameter that indicates whether use of extended range coding of differential motion vector information is signaled for selected types of frames within the entry point segment.
16. The method of claim 14 wherein the plural control parameters further comprise a pan scan on/off parameter that indicates whether pan scan information is present in headers for frames within the entry point segment.
17. The method of claim 14 wherein the plural control parameters further comprise a flag indicating whether a range mapping parameter is present in the entry point header.
18. The method of claim 17 wherein the range mapping parameter is a luma range mapping parameter that indicates how to scale luma samples of the one or more frames in the entry point segment after decoding.
19. The method of claim 17 wherein the range mapping parameter is a chroma range mapping parameter that indicates how to scale chroma samples of the one or more frames in the entry point segment after decoding.
20. The method of claim 14 wherein, for a current frame of the plural frames in the entry point segment, the reference frame syntax element indicates a distance between the current frame and a reference frame.
21. The method of claim 14 wherein the selected types of frames for which the reference frame distance syntax element is present are I/I, I/P, P/P and P/I type frames in the entry point segment.
Techniques and tools for processing digital video are described. For example, a video encoder and decoder use described techniques and tools for signaling control parameters in an entry point layer of a video bitstream.
In general, video compression techniques include “intra-picture” compression and “inter-picture” compression, where a picture is, for example, a progressively scanned video frame. For progressive video frames, intra-frame compression techniques compress individual frames (typically called I-frames or key frames). Inter-frame compression techniques compress frames (typically called predicted frames, P-frames, or B-frames for bi-directional prediction) with reference to preceding and/or following frames (typically called reference or anchor frames).
According to draft JVT-d157 of the JVT/AVC video standard, I-pictures or slices provide access points to a coded sequence where decoding can begin, and various information used in decoding is signaled in network abstraction layer (“NAL”) units. A NAL unit indicates what type of data to expect in the NAL unit, followed by the data itself, interspersed with emulation prevention data. A supplemental enhancement information (“SEI”) NAL unit contains one or more SEI messages. Each SEI message consists of SEI header and SEI payload. The type and size of the SEI payload are coded using an extensible syntax. The SEI payload may have an SEI payload header. For example, a payload header may indicate to which picture the particular data belongs.
Annex D of the draft JVT-d157 describes a syntax for a random access point SEI message. A random access point SEI message contains an indicator of a random access entry point for a decoder. The entry point is indicated as a count relative to the position of the SEI message in units of coded frame numbers prior to the frame number of the current picture. In a random access point SEI message, preroll_count indicates the entry point for the decoding process, and postroll_count indicates the recovery point of output. The exact_match_flag indicates whether decoded pictures at and subsequent to the recovery point in output order obtained by starting the decoding process at the specified entry point shall be an exact match to the pictures that would be produced by a decoder starting at the last prior instantaneous decoder refresh (“IDR”) point in the NAL unit stream. (An IDR picture is an I-picture that causes a decoder to mark all reference pictures in a decoded pictures buffer as unused immediately before decoding the IDR picture, and to indicate that later coded pictures can be decoded without inter prediction from any picture decoded prior to the IDR picture.) The broken_link_flag indicates the presence or absence of a splicing point in the NAL unit stream at the location of the random access point SEI message.
In summary, the detailed description is directed to various techniques and tools for processing video in a video encoder and decoder. Described embodiments implement one or more of the described techniques and tools including, but not limited to, the following:
In one aspect, in a bitstream comprising plural layers, an encoder inserts plural different entry point segment control parameters in an entry point header. Each of the plural different entry point segment control parameters affects decoding or display of one or more pictures in an entry point segment of the bitstream. Each of the plural different entry point segment control parameters is selected from the group consisting of: a pan scan on/off parameter, a reference frame distance on/off parameter, a loop filtering on/off parameter, a fast chroma motion compensation on/off parameter, an extended range motion vector on/off parameter, a variable sized transform on/off parameter, an overlapped transform on/off parameter, a quantization decision parameter, and an extended differential motion vector coding on/off parameter. The entry point segment can comprise an entry point key frame (e.g., a P/I-frame or some other type of key frame).
In another aspect, a decoder receives an entry point header comprising plural control parameters for an entry point segment corresponding to the entry point header. The entry point header is in an entry point layer of a bitstream comprising plural layers. The decoder decodes the entry point header. The plural control parameters include two or more of: a pan scan on/off parameter, a reference frame distance on/off parameter, a loop filtering on/off parameter, a fast chroma motion compensation on/off parameter, an extended range motion vector on/off parameter, a variable sized transform on/off parameter, an overlapped transform on/off parameter, a quantization decision parameter, and an extended differential motion vector coding on/off parameter. The plural control parameters can further comprise a broken link parameter, a closed entry parameter, one or more coded picture size parameters, one or more range mapping parameters (e.g., chroma or luma range mapping parameters), a hypothetical reference decoder buffer parameter, and/or other parameter(s). The fast chroma motion compensation on/off parameter can indicate mechanisms for sub-pixel interpolation for chroma samples and rounding of chroma motion vectors. The quantization decision parameter can indicate one or more layers of signaling for quantization step sizes or a quantizer selection.
In another aspect, a decoder receives an entry point header comprising plural control parameters for an entry point segment corresponding to the entry point header. The entry point segment comprises plural frames. The decoder decodes the entry point header. The plural control parameters comprise at least a reference frame distance on/off parameter, a loop filtering on/off parameter, a fast chroma motion compensation on/off parameter, an extended range motion vector on/off parameter, a variable sized transform on/off parameter, an overlapped transform on/off parameter, and a quantization decision parameter. The plural control parameters may further comprise an extended differential motion vector coding on/off parameter, a pan scan on/off parameter, and/or some other parameter(s).
The scope of parameters listed in an entry point header structure is limited to the sequence corresponding to the preceding sequence header in the bitstream. The parameters are applicable until the occurrence of the next entry point header.
A predicted frame (also called P-frame, B-frame for bi-directional prediction, or inter-coded frame) is represented in terms of prediction (or difference) from one or more reference (or anchor) frames. A prediction residual is the difference between what was predicted and the original frame. In contrast, a key frame (also called I-frame, intra-coded frame) is compressed without reference to other frames. Intra-coded frames include progressive I-frames, interlaced I-frames (frame interlaced mode), interlaced BI-frames (B-frames encoded using intra coding techniques) and I/l frames (field interlaced mode). Parts of other frames also can be compressed without reference to other frames. For example, the I-fields of P/I- or I/P-frames are compressed without reference to other frames and are described in detail below.
In some implementations, the encoder 300 and decoder 400 process video frames organized as follows. A frame contains lines of spatial information of a video signal. For progressive video, these lines contain samples starting from one time instant and continuing through successive lines to the bottom of the frame. A progressive video frame is divided into macroblocks such as the macroblock 500 shown in FIG. 5. The macroblock 500 includes four 8×8 luminance blocks (Y1 through Y4) and two 8×8 chrominance blocks that are co-located with the four luminance blocks but half resolution horizontally and vertically, following the conventional 4:2:0 macroblock format. The 8×8 blocks may be further sub-divided at different stages, e.g., at the frequency transform (e.g., 8×4, 4×8 or 4×4 discrete cosine transforms (“DCTs”) or derivatives of DCT methods) and entropy encoding stages. A progressive I-frame is an intra-coded progressive video frame. A progressive P-frame is a progressive video frame coded using forward prediction, and a progressive B-frame is a progressive video frame coded using bi-directional prediction. Progressive P- and B-frames may include intra-coded macroblocks as well as different types of predicted macroblocks.
The skipped frame insertion module 1934 inserts a number of skipped frames S (treated as P-frames) between two consecutive key frames depending on a trick mode speed factor (e.g., speed-up factor) selected by the user. In one implementation, for a variable-speed fast forward trick mode the value of S is equal to 2 (for 2× speed up) or 4 (for 4× speed up). The number of skipped frames added to the trick mode bitstream 1940 is equal to (K/S)−1, as long as (K/S)−1>0. Thus, if K is 16 and S is 2, the receiver adds 7 skipped frames following each key frame to produce a 2× fast forward effect since 1 second of frames is presented in ½ second. If K is 16 and S is 4, the receiver adds 3 skipped frames following each key frame to produce a 4× fast forward effect since 1 second of frames is presented in ¼ second. If the desired speed factor is such that (K/S)−1<0, then skipped frames are not inserted. Instead, in addition to the non-key frames being dropped, one or more key frames following the current entry point header's key frame are selectively skipped to achieve the selected trick mode speed factor.
The arrangement of trick mode processing modules shown in FIG. 19 can be modified to implement other trick modes. For example, for a slow motion trick mode, a receiver can route an elementary stream to one or more bitstream modification modules to insert duplicate frames into the bitstream. For example, for a half-speed slow motion trick mode, the bitstream modification module(s) can insert one duplicate frame for each frame in the elementary stream. For a quarter-speed slow motion trick mode, the bitstream modification module(s) can insert three duplicate frames for each frame in the elementary stream. Alternatively, the bitstream modification module(s) can insert repeat-frame or repeat-field bitstream elements (or modify the values of repeat-frame or repeat-field elements already in the elementary stream) to instruct the decoder to repeat frames or fields (e.g., repeat once per frame/field for half-speed, repeat three times per frame/field for quarter-speed) to provide a slow motion effect. Or, for a slow motion trick mode, the receiver can change frame rate of the elementary stream input to the decoder but filter the output of the decoder so as to repeat the display of decoded frames for the appropriate number of times. For 2× slow motion, each frame is repeated once in processing outside of the decoder before display. For 4× slow motion, each frame is repeated twice in processing outside of the decoder before display. As for the trick mode bitstream, the frame rate, HRD buffer model parameters, and other real-world timing parameters of the trick mode bitstream are adjusted so that the same elementary stream is decoded over a longer interval of time (e.g., 2×, 4×).
Closed Entry Point (CLOSED_ENTRY (1 Bit)
CLOSED_ENTRY is a 1-bit syntax element. CLOSED_ENTRY=1 indicates that the current entry point segment does not contain any B-pictures that require an I- or or P-picture in the previous entry point segment to decode. CLOSED_ENTRY=0 indicates that the entry point segment may contain B-pictures that require an I- or P-picture in the previous entry point segment to decode.
Coded Size Flag (CODED_SIZE_FLAG) (1 Bit)
Range Mapping Luma Flag (RANGE_MAPY_FLAG) (1 Bit)
TABLE 3 Frame Coding Mode VLC FCM value Frame Coding Mode 0 Progressive 10 Frame-Interlace 11 Field-Interlace Field Picture Type (FPTYPE) (3 Bits)
Step 1: If the RBDU is not null, the EM appends a trailing ‘1’ bit to the end of the RBDU and then stuffs between 0 and 7 bits onto the end of the BDU such that the BDU ends in a byte-aligned location. The value of these stuffing bits is ‘0’. As a result, at the end of this step, the BDU is represented in an integer number of bytes, in which the last byte of the BDU, if present, cannot be a zero-valued byte. The resulting string of bytes is called the payload bytes of the BDU. Step 2: The encoder can begin an EBDU with any number of zero-valued bytes at the beginning of the EBDU. Step 3: The start code is formed by starting with the three-byte start code prefix (0x000001), and appending the appropriate start code suffix that identifies the BDU type as specified in Table 6, below. If no additional zero-valued bytes were placed at the beginning of the EBDU, the start code is placed at the beginning of the EBDU. Otherwise, the start code is placed after the zero-valued bytes that were placed at the beginning of the EBDU. Step 4: The remainder of the EBDU is formed by processing the payload bytes of the BDU through an emulation prevention process as follows, and appending the resulting string of bytes in the EBDU after the start code. The emulation of start code prefixes within the payload bytes of the BDU is eliminated via byte stuffing. The emulation prevention process is performed by starting at the beginning of the payload bytes of the BDU, and replacing each three-byte data string within the payload that consists of two consecutive bytes of value 0x00 followed by a byte that contains zero values in its six MSBs (regardless of the LSB values) with two bytes of value 0x00 followed by a byte equal to 0x03 followed by a byte equal to the last byte of the original three-byte data string. This process is illustrated in Table 4, below. TABLE 4
Step 5: The encoder can end an EBDU with any number of zero-valued bytes at the end of the EBDU.
Step 1: The start code suffix is used to identify the type of BDU. The bytes that follow the start code suffix shall then be further processed as follows. Step 2: The decoder shall remove all zero-valued bytes at the end of EBDU. After this step, if the BDU payload after the start code suffix is not null, the last byte of the BDU will contain the ‘1’ bit and any byte-aligning ‘0’ bits that are present after the end of the RBDU. Step 3: The bytes used for emulation prevention shall be detected and removed according to the following process: Whenever a string of two consecutive bytes of value 0x00 are followed by a byte equal to 0x03, the byte equal to 0x03 is understood to be an emulation prevention byte and is discarded. This process is illustrated in Table 5. TABLE 5
Step 4: If there are bytes not removed in step 2 that follow the start code suffix in the EBDU, in the last byte of the BDU data processed in step 3, the last non-zero bit is identified, and that non-zero bit, and all the zero bits that follow, shall be discarded. The result is the RBBU. If there are no bytes not removed in step 2 that follow the start code suffix in the EBDU, the RBDU shall be considered null.
Sequence Level User Data, Entry-point Level User Data, Frame Level User Data, Field Level User Data, and Slice Level User Data BDU types are used to transmit any user defined data associated with the Sequence, Entry-point, Frame, Field, and Slice respectively.
“End-of-sequence” is an optional BDU type which indicates that the current sequence has ended, and no further data will be transmitted for this sequence. Note that the transmission of an “end-of-sequence” may be present, but the end of a sequence shall be inferred from the header of the next sequence.
FIG. 23 shows a bitstream syntax 2300 that illustrates how an entry point start code and header may be present in this combined implementation before an I/P-frame (Picture Coding Type (FCM) is set to ‘10’ (Field Interlace mode)).
Since the frame is made of an I-field followed by a P-field, the following conditions shall be met in this combined implementation to make this I/P-frame a valid entry point in a bitstream:
1. If a sequence start code or an entry point start code is present in the bitstream immediately before the header of a field interlaced P/I-frame, then a field start code shall be present between the last data byte of the first P-field and the field header of the second I-field. Having described and illustrated the principles of our invention with reference to various embodiments, it will be recognized that the various embodiments can be modified in arrangement and detail without departing from such principles. It should be understood that the programs, processes, or methods described herein are not related or limited to any particular type of computing environment, unless indicated otherwise. Various types of general purpose or specialized computing environments may be used with or perform operations in accordance with the teachings described herein. Elements of embodiments shown in software may be implemented in hardware and vice versa.
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