Source: http://www.google.com/patents/US7256501?dq=7222078
Timestamp: 2014-09-17 12:52:14
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Patent US7256501 - Semiconductor device and manufacturing method of the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsIn a semiconductor device having a package structure in which lead terminals connected to electrodes on both of the upper and lower surfaces of a semiconductor chip are exposed from both of the upper and lower surfaces and side surfaces of a sealing body formed of resin, electrodes of the semiconductor...http://www.google.com/patents/US7256501?utm_source=gb-gplus-sharePatent US7256501 - Semiconductor device and manufacturing method of the sameAdvanced Patent SearchPublication numberUS7256501 B2Publication typeGrantApplication numberUS 11/281,502Publication dateAug 14, 2007Filing dateNov 18, 2005Priority dateDec 24, 2004Fee statusPaidAlso published asUS20060138532Publication number11281502, 281502, US 7256501 B2, US 7256501B2, US-B2-7256501, US7256501 B2, US7256501B2InventorsMasahide Okamoto, Osamu Ikeda, Akira Muto, Yukihiro SatouOriginal AssigneeRenesas Technology Corp.Export CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (15), Classifications (82), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and manufacturing method of the sameUS 7256501 B2Abstract In a semiconductor device having a package structure in which lead terminals connected to electrodes on both of the upper and lower surfaces of a semiconductor chip are exposed from both of the upper and lower surfaces and side surfaces of a sealing body formed of resin, electrodes of the semiconductor chip and the lead terminals are connected by Pb-free connection parts each having a configuration of connection layer/stress buffer layer/connection layer. In each connection part, the connection layer is formed of an inter-metallic compound layer having a melting point of 260� C. or higher or Pb-free solder having a melting point of 260� C. or higher, and the stress buffer layer is formed of a metal layer having a melting point of 260� C. or higher and having a function to buffer the thermal stress.
wherein said first and second connection layers are intermetallic compound layers having a melting point of 260� C. or higher, and are formed by reaction between one of Sn, In, Sn�Ag-based, Sn�Cu-based, Sn�Ag�Cu-based, Sn�Zn-based, Sn�Zn�Bi-based, Sn�In-based, In�Ag-based, In�Cu-based, Bi�Sn-based, and Bi�In-based Pb-free solders and at least one metal of Cu, Ag, Ni, and Au at the time of connection.
wherein said first and second connection layers are Pb-free solder layers having a melting point of 260� C. or higher to 400� C. or lower, and said Pb free solder layers are made of any one of Au�Sn-based alloy, Au�Ge-based alloy, Au�Si-based alloy, Zn�Al-based alloy, Zn�Al�Ge-based alloy, Bi, Bi�Ag-based alloy, Bi�Cu-based alloy, and Bi�Ag�Cu-based alloy.
wherein said stress buffer layer is a metal layer having a melting point of 260� C. or higher and is made of any one of a Cu/invar alloy/Cu composite material, a Cu/Cu20 composite material, a Cu�Mo alloy, Ti, Mo, and W.
CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority from Japanese Patent Application No. JP 2004-372560 filed on Dec. 24, 2004, the content of which is hereby incorporated by reference into this application.
TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device and manufacturing technology thereof. More particularly, it relates to packaging technology of a semiconductor device.
BACKGROUND OF THE INVENTION As a high-power semiconductor device, for example, a semiconductor device in which a semiconductor chip which forms a power supply transistor such as a power MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor), an IGBT (Insulated Gate Bipolar Transistor), or a bipolar power transistor is incorporated in a sealing body is known.
SUMMARY OF THE INVENTION However, the inventors of the present invention have found that the semiconductor device having the above-described package configuration has the following problems.
BRIEF DESCRIPTIONS OF THE DRAWINGS FIG. 1 is a plan view of an upper surface of a sealing body of a semiconductor device of an embodiment of the present invention;
DESCRIPTIONS OF THE PREFERRED EMBODIMENTS In the embodiments described below, the invention will be described in a plurality of sections or embodiments when required as a matter of convenience. However, these sections or embodiments are not irrelevant to each other unless otherwise stated, and the one relates to the entire or a part of the other as a modification example, details, or a supplementary explanation thereof. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
First Embodiment FIG. 1 is a plan view of an upper surface (first principal surface) of a sealing body 1 of a power transistor (semiconductor device) according to a first embodiment; FIG. 2 is a plan view of a lower surface (second principal surface, mounting surface) of the sealing body 1 of the power transistor of FIG. 1; FIG. 3 is a plan view showing the inner structure of the sealing body 1 of the power transistor of FIG. 1 and FIG. 2 viewed from the lower surface side; FIG. 4 is a cross-sectional view taken along the line Y1-Y1 of FIG. 2; FIG. 5 is a cross-sectional view taken along the line Y2-Y2 of FIG. 2; FIG. 6 is a cross-sectional view of an example of a transistor cell formed in a semiconductor chip 2 in the sealing body 1 of FIG. 1, etc.; FIG. 7 is an enlarged cross-sectional view of a connection part (first connection means) 4A which connects a drain lead terminal (first conductive member, external terminal) 3DL to a drain pad (first electrode) DP of the semiconductor chip 2 in the power transistor of FIG. 1, etc.; FIG. 8 is an enlarged cross-sectional view of a connection part (second connection means) 4B which connects a source lead terminal (second conductive member, external terminal) 3SL to a source pad (second electrode) SP of the semiconductor chip 2 in the power transistor of FIG. 1, etc.; and FIG. 9 is a cross-sectional view of a mounted power transistor.
The channel of such power MISFET Q1 is formed in the p type semiconductor region 5 p to which the side surface of the gate electrode 9 of each transistor cell is opposed via the gate insulating film 8 and between the drain epitaxial layer 2EP and the n+ type source semiconductor region 6 n so as to extend along the side surface of the gate electrode 9 (i.e., the side surface of the trench 7) in the thickness direction of the semiconductor substrate 2SUB (direction intersecting with the principal surface and the rear surface of the semiconductor substrate 2SUB). Note that the reference symbol �Dp� denotes an internal diode (parasitic diode).
The connection layers 4 ma and 4 mc are composed of compound layers which are formed by the reaction at the time of connection between, for example, at least one high melting point metal among Cu (copper), Ag (silver), Ni (nickel), and Au (gold) and one of Sn�Ag (tin-silver)-based, Sn�Cu (tin-copper)-based, Sn�Ag�Cu (tin-silver-copper)-based, Sn�Zn (tin-zinc)-based, Sn�Zn�Bi (tin-zinc-bismuth)-based, Sn�In (tin-indium)-based, In�Ag (indium-silver)-based, In�Cu (indium-copper)-based, Bi�Sn (bismuth-tin)-based, and Bi�In (bismuth-indium)-based reactive Pb-free solders. The Sn�Ag-based solder can be exemplified by an Sn-3.5Ag solder (melting point: 221� C.). The Sn�Ag�Cu-based solder can be exemplified by an Sn-3Ag-0.5Cu solder. Also, the Sn�Zn-based solder can be exemplified by an Sn-9Zn-based solder (melting point: 198.5� C.). Also, the Sn�In-based solder can be exemplified by 48Sn�In and Sn-51In solders (melting point: 120� C.). The thickness of the connection layers 4 ma and 4 mc is, for example, about 10 μm.
As the Pb-free solder of the connection layers 4 ma and 4 mc, the solder made of a plurality of metals has better wettability than that made of a single metal. However, in terms of the formation method, the solders made of two metals (for example, Sn�Ag-based, Sn�Cu-based, Sn�Zn-based, In�Ag-based, In�Cu-based, Bi�Sn-based, and Bi�In-based solders) can be readily formed in comparison with the solders made of three or more metals (for example, Sn�Ag�Cu-based and Sn�Zn�Bi-based solders) since the composition is readily controllable. Also, when a material containing Sn is used as the Pb-free solder, since the reaction speed of Cu or Ag with Sn is higher in comparison with that of Au (furthermore, the reaction speed of Ag with Sn is higher than that of Cu), the residual stress can be reduced more when Cu or Ag is used as the high melting point metal.
The material of such stress buffer layer 4 mb is made of, for example, any one of Cu/invar alloy (Fe-36Ni)/Cu (CIC, thermal expansion coefficient is, for example, about 10 ppm/� C.), Cu/Cu20 composite material, a Cu�Mo (copper-molybdenum) alloy, Ti (titanium), Mo (molybdenum), and W (tungsten). The thickness of the stress buffer layer 4 mb is thicker than that of the connection layers 4 ma and 4 mc, and is about 100 μm.
When forming the connection part 4A, first, as shown in FIG. 10A, after the metal foil 4 is disposed between the drain pad DP of the semiconductor chip 2 and the lead terminal 3DL, the drain pad DP and the metal layer 4 ma 0 of the metal foil 4 are brought into contact with each other, and the lead terminal 3DL and the metal layer 4 mc 0 of the metal foil 4 are brought into contact with each other. In this state, the metal foil 4 is sandwiched. Subsequently, in this state, the thermal treatment is performed in a gaseous atmosphere containing, for example, nitrogen (N2) at 350� C. to 400� C. for about several minutes. Consequently, as shown in FIG. 10B, the metal of the metal layer 4 ma 0 of the metal foil 4 and metal of the metal layer 4 mb 1 of the stress buffer layer 4 mb are reacted so that they are partially melted to form an integrated compound, thereby forming the connection layer 4 ma between the stress buffer layer 4 mb and the drain pad DP, and the metal of the metal layer 4 mc 0 of the metal foil 4 and the metal of the metal layer 4 mb 3 of the stress buffer layer 4 mb are reacted so that they are partially melted to form an integrated compound, thereby forming the connection layer 4 mc between the stress buffer layer 4 mb and the lead terminal 3DL. In this case, the connection layers 4 ma and 4 mc are made of, for example, a Sn�Cu compound having a melting point of, for example, 260� C. or higher.
Second Embodiment In a second embodiment, a case where a flexible metal material is used as the material of the stress buffer layer 4 mb of the connection parts 4A, 4B, and 4C will be described. Note that, since the connection layers 4 ma and 4 mc of the connection parts 4A, 4B, and 4C are the same as that of the first embodiment, the description thereof will be omitted.
Also in the case of the second embodiment, the formation method and conditions of the connection part 4A are approximately the same as that of the first embodiment described with reference to FIG. 10. In the case of the second embodiment, when thermal treatment which is similar to that described above is carried out, as shown in FIG. 12B, the metal of the metal layer 4 ma 0 and the metal of the metal layer 4 ma 1 of the metal foil 4 are reacted so that the metals are melted and formed into an integrated compound, thereby forming the connection layer 4 ma between the stress buffer layer 4 mb and the drain pad DP, and also, the metal of the metal layer 4 mc 0 and the metal of the metal layer 4 mc 1 of the metal foil 4 are reacted so that the metals are melted and formed into an integrated compound, thereby forming the connection layer 4 mc between the stress buffer layer 4 mb and the lead terminal 3DL. In this case, the connection layers 4 ma and 4 mc are formed of, for example, a compound of Sn�Cu having a high melting point of, for example, 260� C. or higher.
Third Embodiment In a third embodiment, a case where a high melting point Pb-free solder is used as the material of the connection layers 4 ma and 4 mc of the connection parts 4A, 4B, and 4C will be described. Note that, since the stress buffer layer 4 mb of the connection parts 4A, 4B, and 4C is the same as that of the first embodiment, the description thereof will be omitted.
In the third embodiment, the connection layers 4 ma and 4 mc of the connection parts 4A, 4B, and 4C are made of, for example, a high melting point Pb-free solder having a melting point (for example, 260� C. or higher and 400� C. or lower) higher than the melting point of the adhesive 16. More specifically, the connection layers 4 ma and 4 mc are made of any one of an Au�Sn (gold-tin)-based alloy, an Au�Ge (gold-germanium)-based alloy, an Au�Si (gold-silicon)-based alloy, a Zn�Al (zinc-aluminum)-based alloy, a Zn�Al�Ge (zinc-aluminum-germanium)-based alloy, Bi (bismuth), a Bi�Ag (bismuth-silver)-based alloy, a Bi�Cu (bismuth-copper)-based alloy, and a Bi�Ag�Cu (bismuth-silver-copper)-based alloy. Accordingly, since voids are hardly formed in the connection parts 4A, 4B, and 4C, the thermal resistance and the electrical resistance can be reduced, and the reliability of the power transistor can be improved. Note that the reason for setting the uppermost limit of the melting point of the high melting point Pb-free solder at 400� C. is that, when connection is made by the process at 400� C. or higher, the lead terminals (lead frame) made of copper are softened.
Fourth Embodiment In a fourth embodiment, a case where a high melting point Pb-free solder similar to that described in the third embodiment is used as the material of the connection layers 4 ma and 4 mc of the connection parts 4A, 4B, and 4C, and a flexible metal similar to that described in the second embodiment is used as the material of the stress buffer layer 4 mb will be described.
In the fourth embodiment, the connection layers 4 ma and 4 mc of the connection parts 4A, 4B, and 4C are made of any one of an Au�Sn-based alloy, an Au�Ge-based alloy, an Au�Si-based alloy, a Zn�Al-based alloy, a Zn�Al�Ge-based alloy, Bi, a Bi�Ag-based alloy, a Bi�Cu-based alloy, and a Bi�Ag�Cu-based alloy. Accordingly, voids are hardly formed in the connection parts 4A, 4B, and 4C. Therefore, the thermal resistance and the electrical resistance can be reduced, and the reliability of the power transistor can be improved.
Fifth Embodiment For example, in the first to fourth embodiments, the cases where the materials of the connection layers 4 ma and 4 mc of the connection parts 4A to 4C are the same, and the materials of the stress buffer layers 4 mb of the connection parts 4A to 4C are the same have been described. However, the materials are not limited thereto, and various modifications can be made and different materials can be used depending on the parts.
For example, in current experiments, when Sn serving as a low melting point metal and Cu serving as a high melting point metal are used as the intermetallic compound for the connection layers 4 ma and 4 mc which are formed by reaction of a high melting point metal with a Pb-free solder, it has been confirmed that Cu�Sn compounds (Cu6Sn5, Cu3Sn) and Cu�Ni�Sn compounds are formed on the semiconductor chip 2 side, and Cu�Sn compounds (Cu6Sn5, Cu3Sn) are formed on the Cu frame (lead terminals 3DL, 3SL, and 3GL) side.
As the phases formed by Cu+Sn-3Ag-0.5Cu, phases of Cu�Sn-compounds (Cu6Sn5, Cu3Sn), an Ag�Sn compound (Ag3Sn), and a Cu�Ni�Sn compound have been confirmed on the semiconductor chip 2 side, and phases of Cu�Sn compounds (Cu6Sn5, Cu3Sn), an Ag�Sn compound (Ag3Sn) have been confirmed on the Cu frame (lead terminals 3DL, 3SL, and 3GL) side.
As the phases formed by Cu+Sn-6Zn, phases of Cu�Sn compounds (Cu6Sn5, Cu3Sn) and a Cu�Zn compound have been confirmed on the semiconductor chip 2 side, and phases of a Cu�Zn compound and Cu�Sn compounds (Cu6Sn5, Cu3Sn) have been confirmed on the Cu frame (lead terminals 3DL, 3SL, and 3GL) side.
As the phases formed by Au+Sn, a phase of an Au�Sn compound has been confirmed on the semiconductor chip 2 side, and phases of an Au�Sn compound and Cu�Sn compounds (Cu6Sn5, Cu3Sn) have been confirmed on the Cu frame (lead terminals 3DL, 3SL, and 3GL) side.
As the phases formed by Ni+Sn, a phase of an Ni�Sn compound has been confirmed on the semiconductor chip 2 side, and phases of an Ni�Sn compound, Cu�Sn compounds (Cu6Sn5, Cu3Sn), and an Ni�Cu�Sn compound have been confirmed on the Cu frame (lead terminals 3DL, 3SL, and 3GL) side.
As the phases formed by Ag+Sn, a phase of an Ag�Sn compound (Ag3Sn) and an Ag-rich hcp phase have been confirmed on the semiconductor chip 2 side, and a phase of an Ag�Sn compound (Ag3Sn), an Ag-rich hcp phase, and Cu�Sn compound (Cu6Sn5, Cu3Sn) phases have been confirmed on the Cu frame (lead terminals 3DL, 3SL, and 3GL) side.
As the phases formed by Cu+In-48Sn, phases of Cu�Sn compounds (Cu6Sn5, Cu3Sn), an In�Cu compound, an In�Sn�Cu compound have been confirmed on the semiconductor chip 2 side, and phases of Cu�Sn compounds (Cu6Sn5, Cu3Sn), an In�Cu compound, and an In�Sn�Cu compound have been confirmed on the Cu frame (lead terminals 3DL, 3SL, and 3GL) side.
As the phases formed by Ag+Bi-43Sn, an Ag�Sn compound (Ag3Sn) phase, an Ag-rich hcp phase, and a Bi phase have been confirmed on the semiconductor chip 2 side, and an Ag�Sn compound (Ag3Sn) phase, an Ag-rich hcp phase, a Bi phase, and Cu�Sn compound (Cu6Sn5, Cu3Sn) phases have been confirmed on the Cu frame (lead terminals 3DL, 3SL, and 3GL) side.
Sixth Embodiment In a sixth embodiment, an example of a manufacturing method of the power transistors of the first to fifth embodiments will be described with reference to FIG. 14 and FIG. 15A to FIG. 15F. FIG. 14 is a manufacturing flow diagram of the power transistor, and FIG. 15A to FIG. 15F are explanatory drawings showing the manufacturing process of the power transistor. The upper parts of FIG. 15A to FIG. 15F are plan views of a unit power transistor region, the lower parts of FIG. 15A to FIG. 15C are cross-sectional views taken along the X1-X1 lines of the respective upper parts, and the lower parts of FIG. 15D to FIG. 15F are side views of the respective upper parts.
Seventh Embodiment In a seventh embodiment, an example of a manufacturing method of the power transistors of the first to fifth embodiments, in which the metal foil 4 for forming the connection parts 4A to 4C are bonded by scrubbing will be described.
First, FIG. 16A to FIG. 16C are cross-sectional views showing principal parts of examples of the metal foil 4. In the metal foil 4 of FIG. 16A, the metal layers 4 ma 0 and 4 mc 0 are formed of the reactive Pb-free solders described in the first and second embodiments, and the stress buffer layer 4 mb is formed of the material described in the first embodiment. However, the melting point of the metal layer 4 mc 0 of the metal foil 4 is lower than the melting point of the metal layer 4 ma 0. More specifically, the material of the metal layer 4 mc 0 is, for example, Sn�In-based Sn-51In (melting point: 120� C.) or Sn�Zn-based Sn-9Zn (melting point: 198.5� C.), and the material of the metal layer 4 ma 0 is, for example, Sn-based Sn (melting point: 232� C.) or Sn�Ag-based Sn-3.5Ag (melting point: 221� C.). Other than these, the material of the metal layer 4 mc 0 can be selected from, for example, In-based, Sn�Zn�Bi-based, In�Ag-based, and In�Cu-based materials, and the material of the metal layer 4 ma 0 having a melting point higher than that can be selected from, for example, Sn�Cu-based, Sn�Ag�Cu-based, Bi�Sn-based, and Bi�In based materials.
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