Source: http://www.google.com/patents/US8072461?dq=6,621,746
Timestamp: 2017-09-21 20:14:57
Document Index: 328442845

Matched Legal Cases: ['Application No. 2004800405708', 'Application No. 2004800405708', 'Application No. 2004800405708', 'Application No. 10075685', 'Application No. 10075686', 'Application No. 10075687', 'Application No. 10075688', 'Application No. 04798938']

Patent US8072461 - Multi-thread graphics processing system - Google Patents
A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command...http://www.google.com/patents/US8072461?utm_source=gb-gplus-sharePatent US8072461 - Multi-thread graphics processing system
Publication number US8072461 B2
Application number US 12/718,613
Filing date Mar 5, 2010
Also published as US7239322, US7742053, US7746348, US8305382, US8400459, US8749563, US20050068325, US20070222785, US20070222786, US20070222787, US20100156915, US20120019543, US20130215128, US20140292784, US20160140687
Publication number 12718613, 718613, US 8072461 B2, US 8072461B2, US-B2-8072461, US8072461 B2, US8072461B2
Inventors Laurent Lefebvre, Andrew Gruber, Stephen Morein
Patent Citations (40), Non-Patent Citations (14), Referenced by (1), Classifications (19), Legal Events (2)
Multi-thread graphics processing system
US 8072461 B2
1. In a graphics processing system, a method for selecting a command thread for processing, the method comprising:
selecting a command thread from either of a plurality of pixel command threads and a plurality of vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads, wherein selecting the command thread based on the relative priorities further comprises selecting the command thread based on specific commands that have been executed in any of the plurality of pixel command threads or any of the plurality of vertex command threads; and
providing the command thread to a command processing engine.
2. The method of claim 1, wherein selecting the command thread based on the relative priorities further comprises selecting, as the command thread an oldest one of the plurality of pixel command threads and the plurality of vertex command threads.
3. The method of claim 1, wherein providing the command thread to the command processing engine further comprises, when the command thread is a pixel command thread from the plurality of pixel command threads, interleaving the command thread with at least one vertex command thread of the plurality of vertex command threads and, when the command thread is a vertex command thread from the plurality of vertex command threads, interleaving the command thread with at least one pixel command thread of the plurality of pixel command threads.
4. The method of claim 1, wherein selecting the command thread further comprises selecting a pixel command thread of the plurality of pixel command threads as the command thread without regard to ordering of the plurality of pixel command threads.
5. The method of claim 1, wherein selecting the command thread further comprises selecting a vertex command thread of the plurality of vertex command threads as the command thread without regard to ordering of the plurality of vertex command threads.
6. In a graphics processing system, a method for ensuring maximum utilization of a plurality of command processing engines, the method comprising:
receiving, by an arbiter, a plurality of pixel command threads and a plurality of vertex command threads for execution by the plurality of command processing engines; and
providing, by the arbiter, selected ones of the plurality of pixel command threads and the plurality of vertex command threads to any of the plurality of command processing engines for execution, wherein the selected ones are selected based on specific commands that have been executed in any of the plurality of pixel command threads or any of the plurality of vertex command threads.
7. The method of claim 6, wherein providing the selected ones of the plurality of pixel command threads and the plurality of vertex command threads further comprises interleaving the selected ones of the plurality of pixel command threads and the plurality of vertex command threads.
8. The method of claim 6, further comprising providing the selected ones of the plurality of pixel command threads and the plurality of vertex command threads based on availability of the plurality of command processing engines.
The instant application is a divisional of U.S. patent application Ser. No. 11/746,453 filed May 9, 2007, which application is a continuation of U.S. patent application Ser. No. 10/673,761, filed Sep. 29, 2003 and now issued as U.S. Pat. No. 7,239,322, the entirety of which prior applications are incorporated herein by this reference.
US5550962 Apr 10, 1995 Aug 27, 1996 Hitachi, Ltd. System for selectively performing parallel or sequential drawing processing
US5818469 Apr 10, 1997 Oct 6, 1998 International Business Machines Corporation Graphics interface processing methodology in symmetric multiprocessing or distributed network environments
US6118452 Aug 5, 1997 Sep 12, 2000 Hewlett-Packard Company Fragment visibility pretest system and methodology for improved performance of a graphics system
US6384824 Aug 20, 1999 May 7, 2002 Microsoft Corporation Method, system and computer program product for multi-pass bump-mapping into an environment map
US6573893 Nov 1, 2000 Jun 3, 2003 Hewlett-Packard Development Company, L.P. Voxel transfer circuit for accelerated volume rendering of a graphics image
US6650327 Jun 16, 1998 Nov 18, 2003 Silicon Graphics, Inc. Display system having floating point rasterization and floating point framebuffering
US6704018 Oct 13, 2000 Mar 9, 2004 Kabushiki Kaisha Toshiba Graphic computing apparatus
US6724394 Jun 19, 2001 Apr 20, 2004 Nvidia Corporation Programmable pixel shading architecture
US6731289 May 12, 2000 May 4, 2004 Microsoft Corporation Extended range pixel display system and method
US6897871 Nov 20, 2003 May 24, 2005 Ati Technologies Inc. Graphics processing architecture employing a unified shader
US7015913 Jun 27, 2003 Mar 21, 2006 Nvidia Corporation Method and apparatus for multithreaded processing of data in a programmable graphics processor
US7038685 * Jun 30, 2003 May 2, 2006 Nvidia Corporation Programmable graphics processor for multithreaded execution of programs
US7239322 Sep 29, 2003 Jul 3, 2007 Ati Technologies Inc Multi-thread graphic processing system
US7327369 Apr 29, 2005 Feb 5, 2008 Ati Technologies Inc. Graphics processing architecture employing a unified shader
US7742053 May 9, 2007 Jun 22, 2010 Ati Technologies Ulc Multi-thread graphics processing system
US7746348 May 9, 2007 Jun 29, 2010 Ati Technologies Ulc Multi-thread graphics processing system
US20030030643 Aug 13, 2001 Feb 13, 2003 Taylor Ralph C. Method and apparatus for updating state data
US20030076320 Oct 18, 2001 Apr 24, 2003 David Collodi Programmable per-pixel shader with lighting support
US20030164830 Mar 1, 2002 Sep 4, 2003 3Dlabs Inc., Ltd. Yield enhancement of complex chips
US20040041814 Aug 30, 2002 Mar 4, 2004 Wyatt David A. Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device
US20040164987 Feb 24, 2003 Aug 26, 2004 Microsoft Corporation Usage semantics
US20050068325 Sep 29, 2003 Mar 31, 2005 Ati Technologies, Inc. Multi-thread graphic processing system
US20050110792 Nov 20, 2003 May 26, 2005 Ati Technologies, Inc. Graphics processing architecture employing a unified shader
US20050200629 Apr 29, 2005 Sep 15, 2005 Steven Morein Graphics processing architecture employing a unified shader
US20070222785 May 9, 2007 Sep 27, 2007 Ati Technologies Ulc Multi-thread graphics processing system
US20070222786 May 9, 2007 Sep 27, 2007 Ati Technologies Ulc Multi-thread graphics processing system
US20070222787 May 9, 2007 Sep 27, 2007 Ati Technologies Ulc Multi-thread graphics processing system
US20070285427 Aug 21, 2007 Dec 13, 2007 Ati Technologies Ulc Graphics processing architecture employing a unified shader
US20100231592 Jun 1, 2010 Sep 16, 2010 Ati Technologies Ulc Graphics processing architecture employing a unified shader
EP2296116A2 Nov 19, 2004 Mar 16, 2011 ATI Technologies Inc. A graphics processing architecture employing a unified shader
EP2299408A2 Nov 19, 2004 Mar 23, 2011 ATI Technologies Inc. A graphics processing architecture employing a unified shader
EP2309460A1 Nov 19, 2004 Apr 13, 2011 ATI Technologies ULC A graphics processing architecture employing a unified shader
WO2005050570A1 Nov 19, 2004 Jun 2, 2005 Ati Technologies, Inc A graphics processing architecture employing a unified shader
1 Breternitz, Jr., Mauricio et al.; Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU; IEEE; 2003; pp. 1-11.
2 Chinese Office Action; Chinese Application No. 2004800405708; dated Nov. 2009.
3 Chinese Office Action; Chinese Application No. 2004800405708; dated Sep. 2008.
4 Chinese Office Action; Chinese Application No. 2004800405708; dated Sep. 2010.
5 Eldridge, Matthew et al.; Pomegranate: A Fully Scalable Graphics Architecture; Computer Graphics, SIGGRAPH 2000 Conference Proceedings; Jul. 23, 2000.
6 EP Supplemental Search Report; EP Application No. 10075685.7; dated Feb. 25, 2011.
7 EP Supplemental Search Report; EP Application No. 10075686.5; dated Feb. 25, 2011.
8 EP Supplemental Search Report; EP Application No. 10075687.3; dated Feb. 25, 2011.
9 EP Supplemental Search Report; EP Application No. 10075688.1; dated Feb. 25, 2011.
10 European Patent Office Examination Report; EP Application No. 04798938.9; dated Nov. 9, 2006; pp. 1-3.
11 International Search Report and Written Opinion; International Application No. PCT/IB2004/003821; dated Mar. 22, 2005.
12 Mark, William R. et al.; CG: A system for programming graphics hardware in a C-like language; SIGGRAPH '03; San Diego, CA; ACM Transactions on Graphics; Jul. 2002; vol. 22, No. 3; pp. 896-907.
13 Owens, John D. et al.; Polygon Rendering on a Stream Architecture; Proceedings 2000 SIGGRAPH/Eurographics Workshop on Graphics Hardware; Aug. 21, 2000.
14 Purcell, Timothy J. et al.; Ray Tracing on Programmable Graphics Hardware; SIGGRAPH '02; San Antonio, TX; ACM Transactions on Graphics; Jul. 2002; vol. 21, No. 3; pp. 703-712.
US9727385 Jun 13, 2012 Aug 8, 2017 Apple Inc. Graphical processing unit (GPU) implementing a plurality of virtual GPUs
U.S. Classification 345/522, 345/535, 345/505
International Classification G06T15/00, G06F15/18, G06F13/18, G06F9/38, G06T1/00, G06T15/04
Cooperative Classification G09G5/363, G09G5/001, G06T1/60, G06T15/04, G06T15/005, G06F9/3851, G06T1/20
European Classification G06T15/04, G06T15/00A, G06F9/38E4
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