Source: https://patents.google.com/patent/US6704242?oq=6859936
Timestamp: 2018-06-25 01:29:50
Document Index: 334944203

Matched Legal Cases: ['art 9', 'art 10', 'art 50', 'art 46', 'art 44', 'art 50', 'art 50', 'art 46', 'art 44', 'art 50', 'art 46', 'art 44', 'art.\n9']

US6704242B2 - Semiconductor integrated circuit - Google Patents
US6704242B2
US6704242B2 US10279920 US27992002A US6704242B2 US 6704242 B2 US6704242 B2 US 6704242B2 US 10279920 US10279920 US 10279920 US 27992002 A US27992002 A US 27992002A US 6704242 B2 US6704242 B2 US 6704242B2
US10279920
US20030235105A1 (en )
An input part and a feedback part are arranged in series between a second power supply line and input nodes of inverting circuits. The input part connects the second power supply line to one of the input nodes of the inverting circuits in accordance with an input signal. One of the inverting circuits operates so that a logical value corresponding to the input signal is latched into a latching part. The feedback part connects only one of the input nodes to the input part in accordance with an output level of the latching part, thereby fixing the latching state of the latching part. Since the number of stages of circuits from the input part to the latching part can be reduced, the input signal can be latched reliably even when the power supply voltages are low.
It is an object of the present invention to provide a semiconductor integrated circuit having an input circuit capable of receiving an input signal with reliability. In particular, the object is to receive the input signal reliably when the power supply voltage is low.
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, each thick line represents a signal line that consists of a plurality of lines.
On the contrary, in the conventional input circuit (FIG. 2), the pMOS transistors 9 a and 9 b of the input part 9 are connected to the power supply line VDD through the pMOS transistor 10 a of the power supply connection part 10. In latching the input signal IN, the pMOS transistor 9 b for receiving the reference voltage VREF thus varies at both the source pMOS transistor 9 b.
FIG. 11 shows the operation of the input circuit 30D shown in FIG. 10 (waveforms from a circuit simulation). For a comparative example, the operating waveforms of the conventional input circuit shown in FIG. 2 are presented.
In the conventional input circuit (FIG. 2), the source and drain of the MOS transistor 9 b for receiving the reference voltage VREF vary 1 V and more in voltage. On the other hand, in the input circuit 30D, the drain of the pMOS transistor 32 a for receiving the reference voltage VREF shows voltage variations of 0.5 V and less. That is, the reference voltage VREF is less susceptible to the coupling noise of the pMOS transistor 32 a.
As above, the fifth embodiment can provide the same effects as those of the first embodiment. In addition, the operation margin can be improved even if the input circuits 30D are supplied with an address signal AD of smaller amplitude. The address signal AD can thus be latched with reliability.
The foregoing second embodiment (FIG. 6) has dealt with the case where the input part 50 is supplied with the complementary internal address signals IAD and /IAD, and the precharging part 46 and the power supply connection part 44 are supplied with the internal clock signal /ICLK. The present invention is not limited thereto. For example, as in the fifth embodiment, the input part 50 may directly receive the address signal AD that is supplied to the external terminal. In this case, the gate of the nMOS transistor 50 a of the input part 50 is supplied with the reference voltage VREF. The precharging part 46 and the power supply connection part 44 are then supplied with an internal clock signal /ICLK2 that deviates from the clock signal CLK by 180° in phase.
The gate of the nMOS transistor 50 a of the input part 50 in the fourth embodiment (FIG. 8) may also be supplied with the reference voltage VREF. Here, the precharging part 46 and the power supply connection part 44 are supplied with the internal clock signal /ICLK2 which deviates from the clock signal CLK by 180° in phase.
1. A semiconductor integrated circuit having an input circuit for receiving an input signal, said input circuit comprising:
a latching part having two inverting circuits operating by receiving a first power supply voltage and a second power supply voltage, said inverting circuits having inputs and outputs connected to each other;
a power supply connection part for connecting said inverting circuits to a first power supply line in response to an activation of a control signal, said first power supply line being supplied with said first power supply voltage; and
an input part and a feedback part arranged in series between a second power supply line and input nodes of said inverting circuits, said second power supply line being supplied with said second power supply voltage,
said input part having an input switch circuit for connecting said second power supply line to one of said input nodes through said feedback part in accordance with said input signal and
said feedback part having a feedback switch circuit for connecting said one of the input nodes to said input part in accordance with a level of an output signal output from said latching part.
said input switch circuit has transistors for receiving said input signal and an inverted signal of said input signal at their respective gates, said transistors being connected to said input nodes of said inverting circuits through said feedback switch circuit, respectively.
the sources of said transistors of said input switch circuit are connected directly to second power supply line.
said input switch circuit has transistors for receiving said input signal and a reference voltage at their respective gates, said transistors being connected to said input nodes of said inverting circuits through said feedback switch circuit, respectively.
the sources of said transistors of said input switch circuit are connected directly to said second power supply line.
a precharging part for setting said input nodes of said inverting circuits at a predetermined voltage when said control signal is inactivated.
said predetermined voltage is a voltage for turning on said feedback switch circuit.
a buffer part for amplifying said output signal output from said latching part, and wherein
said feedback part receives said output signal amplified through said buffer part.
9. The semiconductor integrated circuit according to claim 1, wherein:
said inverting circuits are composed of CMOS inverters;
said power supply connection part includes an nMOS transistor for receiving said control signal at its gate;
said input part is composed of pMOS transistors for receiving said input signal and an inverted signal of said input signal at their gates, said pMOS transistors being connected to said second power supply line at their sources;
said feedback part is composed of pMOS transistors for receiving said output signal and an inverted signal of said output signal at their gates; and
said first power supply voltage is lower than said second power supply voltage.
said power supply connection part includes a pMOS transistor for receiving said control signal at its gate;
said input part is composed of nMOS transistors for receiving said input signal and an inverted signal of said input signal at their gates, said nMOS transistors being connected to said second power supply line at their sources;
said feedback part is composed of nMOS transistors for receiving said output signal and an inverted signal of said output signal at their gates; and
said first power supply voltage is higher than said second power supply voltage.
a command latch circuit having said input circuit for receiving a command signal as said input signal; and
a command decoder for generating a core control signal for performing a write operation or a read operation on said memory core, in accordance with said command signal received by said command latch circuit.
said input circuit of said command latch circuit receives said command signal in response to a clock signal that is said control signal.
a memory core having memory cells; and
an address receiver circuit having said input circuit for receiving, as said input signal, an address signal for selecting said memory cells to which a write operation or a read operation is performed.
said input circuit of said address receiver circuit receives said address signal in response to a clock signal that is said control signal.
15. A semiconductor integrated circuit having an input circuit for receiving an input signal, said input circuit comprising:
an input part and a feedback part arranged in parallel between a second power supply line and said latching part to directly receive said second power supply voltage being supplied to said second power supply line,
said input part having an input switch circuit for connecting said second power supply line to one of said inverting circuits in accordance with said input signal and
said feedback part having a feedback switch circuit for connecting said second power supply line to said one of the inverting circuits in accordance with a level of an output signal output from said latching part.
said input switch circuit has transistors for receiving said input signal and an inverted signal of said input signal at their respective gates, said transistors being connected to said inverting circuits, respectively.
said input switch circuit has transistors for receiving said input signal and a reference voltage at their respective gates, said transistors being connected to said inverting circuits, respectively.
19. The semiconductor integrated circuit according to claim 18, wherein
20. The semiconductor integrated circuit according to claim 15, further comprising
a precharging part for setting input nodes of said inverting circuits at a predetermined voltage when said control signal is inactivated.
21. The semiconductor integrated circuit according to claim 20, wherein
said predetermined voltage is a voltage for turning off said feedback switch circuit.
22. The semiconductor integrated circuit according to claim 15, further comprising
23. The semiconductor integrated circuit according to claim 15, wherein:
said input part is composed of pMOS transistors for receiving said input signal and and inverted signal of said input signal at their gates, said pMOS transistors being connected to said second power supply line at their sources;
24. The semiconductor integrated circuit according to claim 15, wherein:
25. The semiconductor integrated circuit according to claim 15, further comprising:
26. The semiconductor integrated circuit according to claim 25, wherein
27. The semiconductor integrated circuit according to claim 26, wherein
28. The semiconductor integrated circuit according to claim 15, further comprising:
US10279920 2002-06-25 2002-10-25 Semiconductor integrated circuit Active 2022-10-29 US6704242B2 (en)
JP2002-184544 2002-06-25
JP2002184544A JP3861031B2 (en) 2002-06-25 2002-06-25 The semiconductor integrated circuit
US20030235105A1 true US20030235105A1 (en) 2003-12-25
US6704242B2 true US6704242B2 (en) 2004-03-09
ID=29728362
US10279920 Active 2022-10-29 US6704242B2 (en) 2002-06-25 2002-10-25 Semiconductor integrated circuit
US (1) US6704242B2 (en)
JP (1) JP3861031B2 (en)
KR (1) KR100823817B1 (en)
KR20150129424A (en) * 2014-05-12 2015-11-20 삼성전자주식회사 Input buffer and memory device including the same
JPH08250997A (en) * 1995-03-14 1996-09-27 Fujitsu Ltd Input circuit
JPH11260064A (en) 1998-03-09 1999-09-24 Sanyo Electric Co Ltd Sense amplifier
JP4110673B2 (en) * 1999-06-18 2008-07-02 富士通株式会社 Semiconductor device
KR100823817B1 (en) 2008-04-21 grant
JP2004032284A (en) 2004-01-29 application
US20030235105A1 (en) 2003-12-25 application
JP3861031B2 (en) 2006-12-20 grant
KR20040002365A (en) 2004-01-07 application
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KOBAYASHI, HIROYUKI;REEL/FRAME:013424/0222