Source: http://www.google.com/patents/US5164666?dq=6,406,777
Timestamp: 2015-01-29 17:35:21
Document Index: 668162704

Matched Legal Cases: ['art 14', 'art 15', 'art 14', 'art 15', 'art 16', 'arts 14', 'arts 19', 'art 23', 'art 23', 'arts 14']

Patent US5164666 - Method and apparatus for analyzing errors in integrated circuits - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsMethod and apparatus for analyzing errors or failures in integrated circuits wherein the integrated circuit is displayed on the picture screen of a work station (AS) and the circuit is excited with a test signal such that at least one measuring location is selected on a malfunction path and an actual...http://www.google.com/patents/US5164666?utm_source=gb-gplus-sharePatent US5164666 - Method and apparatus for analyzing errors in integrated circuitsAdvanced Patent SearchPublication numberUS5164666 APublication typeGrantApplication numberUS 06/753,555Publication dateNov 17, 1992Filing dateJul 10, 1985Priority dateOct 12, 1984Fee statusPaidAlso published asCA1268214A1, DE3437550A1, EP0180072A1, EP0180072B1Publication number06753555, 753555, US 5164666 A, US 5164666A, US-A-5164666, US5164666 A, US5164666AInventorsEckhard Wolfgang, Klaus ZibertOriginal AssigneeICT Integrated Circuit Testing Gesellschaft fur Halbeleiterpruftechnik mbHExport CitationBiBTeX, EndNote, RefManPatent Citations (2), Non-Patent Citations (8), Referenced by (8), Classifications (14), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetMethod and apparatus for analyzing errors in integrated circuitsUS 5164666 AAbstract Method and apparatus for analyzing errors or failures in integrated circuits wherein the integrated circuit is displayed on the picture screen of a work station (AS) and the circuit is excited with a test signal such that at least one measuring location is selected on a malfunction path and an actual signal tappable at this measuring location is compared to a rated signal and wherein the fault location is identified from the comparison results at the measuring locations. The object is to execute a method using an electron beam testing apparatus (EMG) such that the simplest possible measured data transfer occurs. For this purpose the selection of the measuring location on the malfunctioning path proceeds such that a portion (23) of the layout of the integrated circuit corresponding to the measuring location is displayed on the picture screen of the work station and the measuring location is marked by a cursor (24) and position signals depending on the positon of the cursor (24) are supplied to the electron beam measuring apparatus for aligning the electron beam (2) to the measuring location and such that the electron beam testing apparatus is utilized for the identification of the actual signal.
We claim as our invention: 1. A method for error or failure analysis of an integrated circuit specimen having a plurality of circuit layouts which are design layouts, wherein such circuit specimen is displayed on the picture screen of a work station and wherein the circuit specimen is energized with at least one test signal and wherein at least one measuring location is selected on a malfunctioning path which is found to be faulty and an actual signal tappable at said measuring location is compared to a rated signal, and wherein the fault location on the malfunction path is ascertained from the comparison results at the measuring locations, comprising the steps of displaying on a picture screen (BS) at the work station (AS) the selection of a measuring location on the malfunction path on at least that part of one of said design layouts (23) of the integrated circuit specimen corresponding to said measuring location, marking with a cursor (24) on the illustrated part of said one of said design layout (23) the measuring location, and deriving position signals dependent on the cursor position, supplying said position signals to an electron beam testing apparatus (EMG) containing the integrated circuit specimen for the alignment of the electron beam to the measuring location, and utilizing the electron beam testing apparatus for ascertaining the actual signal at the measuring location.
2. A method according to claim 1, characterized in that the measuring locations are selected such that they lie at the branchings of the malfunction path.
3. A method according to claim 1, characterized in that the position signals are supplied to the deflection devices (3, 4) and/or to the controllers of the drive devices (17, 18) of the displaceably table (13) of an electron beam testing apparatus (EMG) which contains said integrated circuit specimen.
4. A method according to claim 1, characterized in that the rated signal which is compared to the tapped actual signal is obtained in the work station (AS) by means of a logic simulation.
5. A method according to claim 1, characterized in that the rated signal which is compared to the tapped actual signal is obtained in the work station by means of a transient simulation.
6. A method according to claim 1, characterized in that the rated signal is composed of a first voltage curve formed in the work station which is displayed on a visual display, particularly on the picture screen of the work station; and in that the actual signal is composed of a second voltage curve which is displayed in contrast to the first voltage curve, being particularly displayed on the same visual voltage curve, being particularly displayed on the same visual display.
7. A method according to claim 1, characterized in that the actual signals, rated signals and comparison signals which are formed from said actual and said rated signals which are developed by said integrated circuit specimen are stored in the work station.
8. A method according to claim 7, characterized in that the actual signals, rated signals and/or comparison signals stored in the work station are output to a printer, plotter or other output device.
9. A method according to claim 1, characterized in that the test signal is composed of a test bit pattern.
10. A method according to claim 9, characterized in that the test signal is composed of a part of the test bit pattern which is formed in the work station.
11. A method for error or failure analysis of an integrated circuit specimen having a plurality of circuit layouts, wherein such circuit specimen is displayed on the picture screen of a work station and wherein the circuit specimen is energized with at least one test signal and wherein at least one measuring location is compared to a rated signal, and wherein the fault location on the malfunction path is ascertained from the comparison results at the measuring locations, comprising the steps of displaying on a picture screen (BS) at the work station (AS) the selection of a measuring location on the malfunction path on at least that part of one of said layouts (23) of the integrated circuit specimen corresponding to said measuring location, marking with a cursor (24) on the illustrated part of said one of said layouts (23) the measuring location, and deriving position signals dependent on the cursor position, supplying said position signals to an electron beam testing apparatus (EMG) containing the integrated circuit specimen for the alignment of the electron beam to the measuring location, and utilizing the electron beam testing apparatus for ascertaining the actual signal at the measuring location, and characterized in that, for the selection of the measuring location, displaying the circuit diagram of the integrated circuit specimen on the picture screen (BS) of the work station, marking the measuring location on the circuit diagram, displaying in that part of the layout (23) of the integrated circuit specimen corresponding to the marked measuring location and its environment, and marking the measuring location by the cursor (24) in such part of the layout (23).
12. A method according to claim 11, characterized in that, after the recognition of a malfunction path, the display of the circuit diagram is essentially limited to said malfunction path.
13. A method according to claims 11 or 12, characterized in that the measuring locations are selected such that they lie at the branchings of the malfunction path.
14. A method according to claims 11 or 12, characterized in the the position signals are supplied to the deflection devices (3, 4) and/or to the controllers of the drive devices (17, 18) of the displaceably table (13) of an electron beam testing apparatus (EMG) which contains said integrated circuit specimen.
15. A method according to one of the claims 11 or 12, characterized in that the rated signal which is compared to the tapped actual signal is obtained in the work station (AS) by means of a transient simulation.
16. A method for error or failure analysis of an integrated circuit specimen having a plurality of circuit layouts, wherein such circuit specimen is displayed don the picture screen of a work station and wherein the circuit specimen is energized with at least one test signal and wherein at least one measuring location is compared to a rated signal, and wherein the fault location on the malfunction path is ascertained from the comparison results at the measuring locations, comprising the steps of displaying on a picture screen (BS) at the work station (AS) the selection of a measuring location on the malfunction path on at least that part of one of said layouts (23) of the integrated circuit specimen corresponding to said measuring location, marking with a cursor (24) on the illustrated part of said one of said layouts (23) the measuring location, and deriving position signals dependent on the cursor position, supplying said position signals to an electron beam testing apparatus (EMG) containing the integrated circuit specimen for the alignment of the electron beam to the measuring location, and utilizing the electron beam testing apparatus for ascertaining the actual signal at the measuring location, and characterized in that the test signal supplied to the integrated circuit specimen (5) from the work station (AS) is converted into a higher frequency with an electronic circuit.
17. A method according to one of the claims 11 or 12, characterized in that the rated signal is composed of a first voltage curve formed in the work station which is displayed on a visual display, particularly on the picture screen of the work station; and in that the actual signal is composed of a second voltage curve which is displayed in contrast to the fist voltage curve, being particularly displayed on the same visual display.
18. A method according to claims 11 or 12, characterized in that the test signal supplied to the integrated circuit specimen (5) from the work station (AS) is converted into a higher frequency with an electronic circuit.
19. A method according to one of the claims 11 or 12, characterized in that the test signal is composed of a test bit pattern.
20. A method according to claim 19, characterized in that the test signal is composed of a part of the test bit pattern which is formed in the work station.
21. A method according to claim 12, characterized in that a scanning electron microscope is employed as the electron beam testing apparatus (EMG), said scanning electron microscope being set up for taking voltage values at individual measuring points of an integrated circuit specimen (5).
22. A method according to one of the claims 11, or 21, characterized in that the position signals are derived via a test bed breadboard (12) containing the integrated circuit specimen.
23. A method according to one of the claims 11 or 21, characterized in that the rated signal which is compared to the tapped actual signal is obtained in the work station (AS) by means of a logic simulation.
This invention relates in general to apparatus and methods for testing and identifying failures in integrated circuits.
Work stations are known in the prior art and are explained, for example, in the special issue CADCAM of the periodical "Elektronik", Vol. 18 dated Sep. 7, 1984 pages 165-169. Work station computers can be utilized in for example design of monolithically integrated circuits both in producing and displaying the circuit diagram as well as for logical simulations of the circuit and for producing the layout.
Electron beam testing apparatus and electron beam testing methods for failure analysis in integrated circuits are known as disclosed for example in Scanning Electron Microscopy 1983/IV, at pages 1595-1604 from the conference volume of the IEEE Computer Society, Test Technology Committee, 16th and 17th of Nov. 1983 (Curriculum for Test Technology, Minneapolis), pages 26-31 as well as from the Phys. B1 38 (1982) No. 8, pages 253-258.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and apparatus which utilizes a work station and electron beam testing apparatus wherein the simplest possible measure data transfer between the work station and the electron beam testing apparatus occurs wherein the selection of a measuring location on the malfunction path occurs such that at least a part of the layout of the integrated circuit corresponding to this measuring location and its environment is displayed on a picture screen of the work station and the measuring location is marked with a cursor on the illustrated part of the layout and position signals depending on the position of the cursor are derived which are supplied to an electron beam testing apparatus containing the integrated circuit which is the specimen and the beam is aligned to the measuring location and the electron beam testing apparatus is utilized for ascertaining the actual signal associated with the measuring location.
The advantage obtainable with the invention is particularly comprised in that the measured data required for the implementation of the method in the electron beam testing apparatus, for example, the coordinates of the individual measuring locations on the chip of the integrated circuit are derived in a particularly simple fashion from the circuit data residing in the work station and are made available on the electron beam testing equipment.
BRIEF DESCRIPTION OF THE DRAWINGS The drawing comprises a block schematic view of the failure analyzing apparatus for testing integrated circuits according to the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS The FIG. illustrates a work station AS which is equipped with a picture screen BS. An electron beam testing apparatus EMG comprises an electron beam generator 1 which produces an electron beam 2 which passes through two deflection systems 3, 4 which deflect the beam in two coordinate directions which are orthogonal relative to each other. The beam 2 impinges on the surface of an integrated circuit 5 which might comprise a chip and an error or failure analysis is to be accomplished on the circuit 5. Secondary electrons are emitted from the surface of the circuit 5 when the electron beam impinges thereon at the locations where the electron beam 2 impinges and these secondary emissions travel in the direction of arrow 6 and are detected by a detector 7. The detector 7 produces a signal from which a control signal for a picture tube 9 is derived in a signal processing unit 8. The beam deflection system of the picture tube 9 is designated by 10. The beam deflection systems receive inputs from a scan generator 11 which also drives the deflection systems 3 and 4 with deflection voltages.
The integrated circuit 5 which may be referred to as a test specimen is contained in a test bed (bread board) 12 which is mounted on an x-y table 13. The x-y table 13 is composed of parts or members 14, 15 and 16 with the part 14 mounted on part 15 and with the part 14 being displaceable in a first parallel deflection direction x. The part 15 is displaceable in a second parallel deflection direction y on the stationary base or bottom part 16. Drive apparatuses 17 and 18 are respectively connected to parts 14 and 15 so as to move them in the x and y directions.
Electron lenses which are required for focusing the electron beam 2 are not shown in the drawing for the sake of simplicity and also since they are well known to those skilled in the art.
In order to test for error or failure analysis on the monolithically integrated circuit 5 the following procedure is utilized: First, the circuit diagram of the circuit 5 which is found to be faulty is displayed on the picture screen BS. By means of a trouble shooting algorithm which sequences the work station AS and which is executed by the employment of test bit patterns (stimuli) which are stored in the work station, a malfunctioning path is emphasized with respect to the remaining portions of the circuit diagram. In the FIG. it is indicated for example, that a malfunctioning path 21 lying between a subcircuit 19 and an AND gate 20 is extracted and indicated on the picture screen BS.
Expediently, a check is then accomplished at a plurality of measuring locations on this particular malfunctioning path by means of the electron beam testing apparatus to determine whether the error or fault appears or does not appear. Such measuring locations are particularly distributed over the malfunctioning paths such that they respectively lie in the region of a branching point. The selection of such measuring locations occurs in a fashion such that it is first marked on the illustrated part of the malfunctioning path as a part of the circuit diagram by means of a cursor 22 or by a trouble shooting algorithm. Subsequently, that part of the layout of the integrated circuit which corresponds to the measuring location is marked and identified by the cursor 22 and then its immediate environment is displayed on the picture screen BS isolated from the remaining layout. This is indicated in the drawing by the view BS1 of the picture tube BS. The transition from the illustrated parts 19 through 21 of the circuit diagram to the illustrated layout part 23 occurs in the work station by means of a preceding "electrical rule check" or, respectively, by a reconstruction of the topology from the topography. The measuring location is then marked on the illustrated layout part 23 by a cursor 24.
Depending upon the position of the adjustable cursor 24, the work station then generates position signals Sx and Sy which are supplied through a line group to the bread board 12. By way of a circuit provided on the bread board which represents a periphery circuit with respect to the circuit 5 under investigation and serves among other things for the drive of the circuit 5, control signals are derived from Sx and Sy which are supplied in one instance by way of lines 26 to the deflection means 3 and 4 and also by way of lines 27 to the drive units 17 and 18. These control signals cause the alignment of the electron beam 2 to the selected measuring location on the chip of the integrated circuit 5. The setting of the parts 14 and 15 thus serves as a rough setting and the deflection of the electron beam by means of the deflection systems 3 and 4 serve as a fine adjustment. A rough adjustment can also be omitted under certain conditions depending on the position of the measuring location on the chip.
The integrated circuit 5 is fed by test signals which are generally present in the form of bit patterns and are likewise supplied from the work station AS by way of the line group 25. These can also be transmitted by means of a PIN electronic system at a significantly higher frequency band before they proceed to circuit 5.
The electron beam 2 which has been aligned to the measuring location causes the emission of a number of secondary electrons which depend on the voltage at the measuring locations so that a voltage curve which is referred to as the actual signal is acquired by the detector 7 and the signal processing unit 8 with the amplitude respectively reflecting the voltage appearing at the measuring location. The time relationship of the actual signal can be displayed on the picture tube 9. For this purpose it is sufficient that the scan generator 11 merely influences the time deflection of the writing electron beam of the picture tube 9 whereas the signal acquired by way of the signal processing unit 8 causes an excursion of the time axis thus described. Alternatively, the actual signal can also be supplied by way of a line 28 to the work station AS and can be displayed on the picture screen BS.
In the work station AS, a rated signal which is allocated to the measuring location under observation is generated by means of a logic simulation and is displayed on the picture screen BS in terms of its time dependency as illustrated in view BS2. A comparison of the actual signal to the rated signal indicates in a simple manner whether the fault or error is present at the particular fault location.
According to a further development of the method of the invention, the actual signal can be displayed with a time spread such that the transition from the lower voltage value to the upper voltage value becomes clearly visible. For comparison, a rated signal that is generated in the work station by a transient simulation is employed. Such a rated signal may be derived from a view BS3 of the screen BS.
When the actual signal and the rated signal are compared to each other on the picture screen BS it is expedient to clearly distinguish one signal from the other by means of color contrast. A differential signal that indicates the size of the mutual deviation can also be formed from the two signals in the work station AS.
For investigating a specific malfunction path a part of a test signal which for example is composed of a long bit pattern can also be extracted therefrom at the work station AS which produces certain advantages. The test signal is thus divided and its extracted portion is then periodically supplied to the integrated circuit 5 by way of the line group 25.
When the actual signal acquired at the measuring location defined by the cursors 22 and 24 does not agree with the rated signal corresponding to BS2 or BS3 then a measuring error is present at this location. When the remaining measuring locations are investigated in an analogous manner, then the conclusion can be drawn that the measuring error can be localized on the malfunction path between a measuring location which still allows the measuring error to be recognized and a following measuring location at which it no longer appears.
The actual signals, the rated signals and the comparison signals which may be derived from such two signals allocated to the integrated circuit 5 can be stored in the work station or can also be supplied as output to printers, platters or other peripheral equipment.
It is seen that the present invention provides a novel and simple manner for testing for errors and failures in integrated circuits and although it has been described with respect to preferred embodiments, it is not to be so limited as changes and modifications may be made which are within the full intended scope as defined by the appended claims.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4538065 *Feb 28, 1983Aug 27, 1985Tokyo Shibaura Denki Kabushiki KaishaStroboscopic scanning electron microscopeEP0081295A1 *Nov 8, 1982Jun 15, 1983Hughes Aircraft CompanyIntelligent probe for fast microcircuit internal node testing* Cited by examinerNon-Patent CitationsReference1"Electron Beam Testing Methodology", P. Fazekas and Wolfgang, 1983 IEEE, pp. 26-31.2 *Electron Beam Measurements in Practice, Fazekas, Fox, Papp, Widulla and Wolfgang, Scanning Electron Microscopy 1983/IV, pp. 1595 1604, Sem Inc.3Electron Beam Measurements in Practice, Fazekas, Fox, Papp, Widulla and Wolfgang, Scanning Electron Microscopy 1983/IV, pp. 1595-1604, Sem Inc.4 *Electron Beam Testing Methodology , P. Fazekas and Wolfgang, 1983 IEEE, pp. 26 31.5 *Elektronenstrahl Besstechnik zur Prufung Integrierter Schaltungen Physik Verlag 38 (1982) No. 8, pp. 253 258.6Elektronenstrahl-Besstechnik zur Prufung Integrierter Schaltungen Physik-Verlag 38 (1982) No. 8, pp. 253-258.7IBM Technical Disclosure Bulletin, De Stafeno et al., "Voltage Comparator System for Contactless . . . ", vol. 17, No. 10, Mar. 1975, pp. 2871-2873.8 *IBM Technical Disclosure Bulletin, De Stafeno et al., Voltage Comparator System for Contactless . . . , vol. 17, No. 10, Mar. 1975, pp. 2871 2873.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5528156 *Jan 14, 1994Jun 18, 1996Advantest CorporationIC analysis system and electron beam probe system and fault isolation method thereforUS5589780 *Sep 30, 1994Dec 31, 1996Advantest CorporationIC Analysis system and electron beam probe system and fault isolation method thereforUS5592100 *Apr 30, 1996Jan 7, 1997Advantest CorporationMethod for detecting an IC defect using charged particle beamUS5682104 *Feb 9, 1995Oct 28, 1997Kabushiki Kaisha ToshibaElectron beam tester and testing method using the sameUS5757198 *Apr 30, 1996May 26, 1998Advantest CorporationMethod and apparatus for detecting an IC defect using charged particle beamUS5821761 *Jan 10, 1997Oct 13, 1998Advantest CorporationApparatus detecting an IC defect by comparing electron emissions from two integrated circuitsUS6895372 *Sep 27, 1999May 17, 2005International Business Machines CorporationSystem and method for VLSI visualizationUS6931580Mar 13, 2000Aug 16, 2005International Business Machines CorporationRapid fail analysis of embedded objects* Cited by examinerClassifications U.S. Classification324/750.16, 324/73.1, 702/117, 324/754.22, 324/762.02International ClassificationG01R31/302, G01R31/26, G01N23/225, G01R31/02, H01L21/66, H01J37/28, G01R31/305Cooperative ClassificationG01R31/305European ClassificationG01R31/305Legal EventsDateCodeEventDescriptionApr 6, 2004FPAYFee paymentYear of fee payment: 12Mar 24, 2000FPAYFee paymentYear of fee payment: 8May 14, 1996ASAssignmentOwner name: ADVANTEST CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ACT ADVANCED CIRCUIT TESTING GESELLSCHAFT FUR TESTSYSTEMENTWICKLUNG MBH;REEL/FRAME:007969/0557Effective date: 19960314Mar 22, 1996FPAYFee paymentYear of fee payment: 4Jan 22, 1996ASAssignmentOwner name: ACT ADVANCED CIRCUIT TESTING GESELLSCHAFT FUR TESTFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ICT INTEGRATED CIRCUIT TESTING GESELLSCHAFT FUR HALBLEITERPRUFTECHNIK MBH;REEL/FRAME:007773/0906Effective date: 19951213Aug 23, 1995ASAssignmentOwner name: ADVANTEST CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ICT INTEGRATED CIRCUIT TESTINGGESELLSCHAFT FUR HALBLEITERPRUFTECHNIK MBH;REEL/FRAME:007588/0954Effective date: 19950721Dec 14, 1989ASAssignmentOwner name: ICT INTEGRATED CIRCUIT TESTING GESELLSCHAFT FUR HAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:SIEMENS AKTIENGESELLSCHAFT;REEL/FRAME:005195/0559Effective date: 19891009Jul 10, 1985ASAssignmentOwner name: SIEMENS AKTIENGESELLSCHAFT, BERLIN AND MUNICH, A GFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:WOLFGANG, ECKHARD;ZIBERT, KLAUS;REEL/FRAME:004434/0207Effective date: 19850619RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services