Source: http://www.google.com/patents/US7739566?dq=%223do%22+dna
Timestamp: 2014-09-02 19:12:16
Document Index: 584554606

Matched Legal Cases: ['Application No. 06', 'art 1', 'art 2', 'art 3', 'art 2', 'art 3', 'art 2', 'art 11']

Patent US7739566 - Scan test circuitry using a state machine and a limited number of dedicated pins - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn electronic circuit includes a group of devices which facilitate scan testing of at least one part of the electronic circuit. Those devices include a scan test device. The circuit further includes a state machine which operates to transfer data from an input pin of the circuit which is dedicated to...http://www.google.com/patents/US7739566?utm_source=gb-gplus-sharePatent US7739566 - Scan test circuitry using a state machine and a limited number of dedicated pinsAdvanced Patent SearchPublication numberUS7739566 B2Publication typeGrantApplication numberUS 11/698,249Publication dateJun 15, 2010Filing dateJan 24, 2007Priority dateJan 27, 2006Fee statusPaidAlso published asDE602007007829D1, EP1813952A1, EP1813952B1, US20070260953Publication number11698249, 698249, US 7739566 B2, US 7739566B2, US-B2-7739566, US7739566 B2, US7739566B2InventorsPaul ArmagnatOriginal AssigneeStmicroelectronics S.A.Export CitationBiBTeX, EndNote, RefManPatent Citations (6), Non-Patent Citations (5), Classifications (6), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetScan test circuitry using a state machine and a limited number of dedicated pinsUS 7739566 B2Abstract An electronic circuit includes a group of devices which facilitate scan testing of at least one part of the electronic circuit. Those devices include a scan test device. The circuit further includes a state machine which operates to transfer data from an input pin of the circuit which is dedicated to the state machine to the devices relating to scan testing. The state machine supports a plurality of data transfer protocols. The choice of the protocol to be used is made as a function of a signal received on the input pin. Responsive to an input pin signal, the state machine enters an operational mode wherein scan test programming data is serially received at the input pin and communicated to the devices which facilitate scan testing. More specifically, the scan test programming data is serially communicated to a scan test register, where the data is output in parallel to the scan test device.
PRIORITY CLAIM The present application claims priority from French Patent Application No. 06 00787 filed Jan. 27, 2006, the disclosure of which is hereby incorporated by reference.
A digital electronic circuit is customarily fabricated on the basis of what is called an RTL description (standing for �Register Transfer Level�) which describes the operations of the circuit in an appropriate programming language, for example, one of the C, Verilog or VHDL language (standing for �Very High Speed Integrated Circuit Hardware Description Language�). An RTL description can customarily be validated with the aid of simulation software tools.
A description at the logic level (called a �netlist�), describing a set of logic gates (corresponding to assemblies of transistors) and of connections, can be synthesized on the basis of the RTL description. The operation of a netlist can be validated by virtue of functional tests.
Steps of placement and routing lead to a drawing of the masks (called a �layout�) on the basis of the description at the logic level. Thereafter, what is called an LVS test (standing for �Layout versus Schematic�) can be executed so as to verify that the layout does indeed correspond to the logic description.
The fabricated circuit must finally be tested so as to verify that no logic gate is �stuck� at a fixed value (�stuck at 0 or stuck at 1�), because of, for example, a short-circuit. To thus test the fabricated circuit, it is known to carry out what is called a scan test. Scan tests use the principle according to which any digital circuit consists of a relatively easy to test combinatorial part and of a sequential part limited to D-type flip-flops. The D-type flip-flops can be connected together by virtue of multiplexers to make it possible readily to control the signals dispatched or received from the combinatorial part.
FIG. 1 shows an exemplary digital part of a relatively simple electronic circuit able to be tested by a scan test. The digital part 1 comprises a sequential part 2 and a combinatorial part 3. The sequential part 2 comprises flip-flops 6 A, 6 B, 6 C, . . . , of type D each associated with a multiplexer 80 A, 80 B, 80 C, . . . , and grouped into a chain 2. Each of the flip-flops 6 A, 6 B, 6 C, . . . , comprises a data input respectively 7 A, 7 B, 7 C, . . . , a scan input respectively 8 A, 8 B, 8 C, . . . , an output respectively 8 B, 8 C, 8 D, . . . , a clock input, not represented, and an enabling input controlled by an enabling signal scan_en. When the enabling signal is at a logic �1� level, the logic state of the scan inputs 8 A, 8 B, 8 C, . . . , is copied over to the corresponding outputs 8 B, 8 C, 8 D, . . . , at each rising clock edge. On the other hand, when the enabling signal is in a logic �0� state, the logic state of the data inputs 7 A, 7 B, 7 C, . . . , is copied over to the corresponding outputs 8 B, 8 C, 8 D, . . . , at each rising clock edge.
The enabling signal scan_en also commands a switch 9. When the signal scan_en is in a logic �0� state, the signal scan_out at the output 5 of the electronic circuit takes the value of the signal Scomb at the output of the combinatorial part 3, termed the functional output. When the signal scan_en is in a logic �1� state, the signal scan_out at the output 5 takes the value of the signal Sseq at the output of the sequential part 2, termed the scan output.
Each sequence of five values of the input signal is called a test vector. Methods of automatic test program management or ATPG (standing for �Automatic Test Pattern Generator�) make it possible to generate test vectors intended to be placed at the input scan_in of the chain. The values of the signals of the test vectors are such that, if the fabricated circuit is operationally correct, all the connections must change value at least once during the conduct of the scan test.
Moreover, a command register 20 or TMC (standing for �Test Mode Control�) makes it possible to store certain command parameters of certain analog parts not represented, such as, for example, a phase-locked loop or PLL, or else yet another multiplexer. These parameters, for example, control the wiring of a PLL, or else also the programming of a multiplexer. The TMC 20 thus makes it possible to place the fabricated circuit in a desired mode, and in particular in a desired test mode. The TMC 20 can, for example, be programmed via a standard interface, for example, 12C (standing for �Inter Integrated Circuit�). This programming generally requires at least one digital pin 19.
SUMMARY OF THE INVENTION According to a first aspect, an embodiment of the invention is an electronic circuit comprising a group of devices, the group of devices comprising a scan test device which functions to test at least one part of the electronic circuit, and a state machine which transfers data from an input pin dedicated to the state machine to the devices of the group of devices. The state machine supports a plurality of data transfer protocols, the choice of the protocol to be used being made as a function at least of a signal received on the input pin.
According to a second aspect, the invention is aimed at an electronic apparatus comprising an electronic circuit according to the first aspect of the invention described above. The present invention is not limited by the nature of the electronic apparatus, so that it finds applications in varied fields. By way of example, the electronic apparatus can, for example, be a reader of DVDs (standing for �Digital Versatile Disk�) or else also a steering control apparatus intended to be carried on board a motor vehicle.
DETAILED DESCRIPTION OF THE DRAWINGS In the embodiment illustrated by FIGS. 4, 5 and 6, an electronic circuit comprises a state machine 24 linked to a digital input pin 21 on the one hand, and to a group of devices 20, 25, 26, 23 on the other hand. The group of devices comprises several scan test devices 25, 26, 23 for a part 11 of the electronic circuit also termed the core.
The group of devices also comprises a command device 20 for prescribing operating modes and in particular test modes. In this example, the device 20 comprises a command register TMC intended to store command parameters of the test mode. The register TMC is a shift register. The register TMC, also termed TCR (standing for �Test Control Register�), makes it possible, for example, to store a memories test parameter or BIST (standing for �Built In Self Test�) and a scan test parameter. If the value of the BIST parameter, respectively scan test parameter, is 1, for example, then the register TMC prescribes the carrying out of a BIST test, respectively of a scan test.
The first and the second shift registers 25, 26 can be linked via a connection 30, for scan test device test purposes (termed a �bypass�).
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