Source: http://www.google.fr/patents/US7348237
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Brevet US7348237 - NOR flash memory cell with high storage density - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus »Connexion Recherche avanc�e dans les brevets BrevetsStructures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region...http://www.google.fr/patents/US7348237?utm_source=gb-gplus-shareBrevet US7348237 - NOR flash memory cell with high storage density Recherche avanc�e dans les brevets Num�ro de publicationUS7348237 B2Type de publicationOctroi Num�ro de demandeUS 11/005,909 Date de publication25 mars 2008 Date de d�p�t6 d�c. 2004 Date de priorit�21 juin 2002�tat de paiement des fraisPay�Autre r�f�rence de publicationUS6996009, US7113429, US7476586, US20030235079, US20050082599, US20050085040, US20070015331 Num�ro de publication005909, 11005909, US 7348237 B2, US 7348237B2, US-B2-7348237, US7348237 B2, US7348237B2 InventeursLeonard Forbes Cessionnaire d'origineMicron Technology, Inc.Exporter la citationBiBTeX, EndNote, RefManCitations de brevets (101), Citations hors brevets (99), Classifications (29), �v�nements juridiques (1) Liens externes: USPTO, Cession USPTO, EspacenetNOR flash memory cell with high storage densityUS 7348237 B2 R�sum� Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.
1. A method for forming a NOR flash memory array, comprising:
forming a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein forming the number of vertical pillars includes forming the number of vertical pillars to serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a programmed cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench;
forming a number of sourcelines in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein a portion of the sourcelines undercut the pillars to form the first source/drain regions, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couples to the sourceline in a shared trench.
2. The method of claim 1, wherein forming each floating gate includes forming each floating gate as a vertical floating gate in a trench below a top surface of each pillar, and forming a pair of floating gates in each trench on opposing sides of the trench and opposing the channel regions in column adjacent pillars.
3. The method of claim 2, wherein the method includes forming the control gate in the trench below the top surface of the pillars and between the pair of floating gates, such that each pair of floating gates shares a single control gate, and wherein forming each floating gate includes forming a vertically oriented floating gate having a vertical length of less than 100 nanometers.
4. The method of claim 2, wherein the method includes forming the control gates in the trench below the top surface of the pillars and between the pair of floating gates, such that each trench houses a pair of control gates each addressing a floating gate on opposing sides of the trench respectively, and wherein the pair of control gates are separated by an insulator layer.
5. The method of claim 2, wherein the method includes forming the control gates disposed vertically above the floating gates, and forming the control gates such that each pair of floating gates shares a single control gate line.
6. The method of claim 2, wherein the method includes forming a pair of control gates disposed vertically above the floating gates.
7. The method of claim 1, wherein forming each floating gate includes forming each floating gate as a horizontally oriented floating gate in a trench below a top surface of each pillar, such that each trench houses a floating gate opposing the channel regions in column adjacent pillars on opposing sides of the trench, and wherein forming each horizontally oriented floating gate includes forming each horizontally oriented floating gate to have a vertical length of less than 100 nanometers opposing the channel regions of the pillars.
8. The method of claim 7, wherein the method includes forming the control gates disposed vertically above the floating gates.
9. The method of claim 1, wherein forming the number of sourcelines in a bottom of the trenches between rows of the pillars includes implanting a doped region in the bottom of the trenches between rows of the pillars.
10. The method of claim 1, wherein forming the first gate insulator of each floating gate transistor includes forming the first gate insulator to have a thickness of approximately 10 nanometers (nm).
11. The method of claim 1, wherein forming the number of vertical pillars to serve as floating gate transistors includes forming floating gate transistors which have a density equivalent to a floating gate transistor having a size of approximately 2.0 lithographic features squared (2F2).
12. A method for forming a NOR memory array, comprising:
forming a number of NOR flash memory cells from vertical pillars extending from a substrate and separated by trenches, wherein each flash memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator, and a control gate separated from the floating gate by a second gate insulator;
coupling a number of bit lines to the second source/drain region of each flash memory cell along rows of the memory array;
coupling a number of word lines to the control gate of each flash memory cell along columns of the memory array;
forming a number of sourcelines along rows in the trenches between the number of flash memory cells extending from a substrate, wherein a portion of the sourcelines undercut the pillars to form the first source/drain regions; and trapping a charge in at least one floating gate such that the flash memory cell operates at reduced drain source current.
13. The method of claim 12, wherein forming the floating gate includes forming a vertically oriented floating gate having a vertical length of less than 100 nanometers.
14. The method of claim 12, wherein forming the vertical floating gate transistor includes forming a vertical floating gate transistor having a size of approximately 2.0 lithographic features squared (2F2).
15. A method for forming an electronic system, comprising:
forming a NOR flash memory array, including:
forming a number of sourcelines along rows in the trenches between the number of flash memory cells extending from a substrate, wherein a portion of the sourcelines undercut the pillars to form the first source/drain regions;
trapping a charge in at least one floating gate, such that the flash memory cell operates at reduced drain source current; and
coupling a processor to the NOR flash memory array.
16. The method of claim 15, wherein forming the number of sourcelines includes doping a region in the bottom of the trenches.
17. The method of claim 15, wherein forming the floating gates includes forming a floating gate in the trenches below a top surface of the pillars.
18. The method of claim 15, wherein forming the floating gate includes forming a vertically oriented floating gate having a vertical length of less than 100 nanometers.
CROSS REFERENCE TO RELATED APPLICATIONS The present application is a divisional of U.S. patent application Ser. No. 10/177,483, filed on Jun. 21, 2002, Pat. No. 6,996,009 which is incorporated herein by reference.
This application is related to the following co-pending, commonly assigned U.S. patent applications: �NOR Flash Memory Cell with High Storage Density�, Ser. No. 11/006,312 �Write Once Read Only Memory Employing Floating Gates,� Ser. No. 10/177,083; �Write Once Read Only Memory Employing Charge Trapping in Insulators,� Ser. No. 10/177,077, now issued as U.S. Pat. No. 6,804,136; �Ferroelectric Write Once Read Only Memory for Archival Storage,� Ser. No. 10/177,082; �Nanocrystal Write Once Read Only Memory for Archival Storage,� Ser. No. 10/177,214; �Write Once Read Only Memory with Large Work Function Floating Gates,� Ser. No. 10/177,213; �Vertical NROM Having a Storage Density of 1 Bit per 1 F2,� Ser. No. 10/177,208; and �Multistate NROM Having a Storage Density Much Greater than 1 Bit per 1 F2,� Ser. No. 10/177,211; each of which disclosure is herein incorporated by reference.
REFERENCES B. Dipert and L. Hebert, �Flash Memory goes Mainstream,� IEEE Spectrum, No. 10, pp. 48�52, (October 1993);
C.-G. Hwang, �Semiconductor Memories for the IT Era,� Abst. IEEE Int. Solid-State Circuits Conf., San Francisco, 2002, pp. 24�27;
R. Shirota et al., �A 2.3 mu2 memory cell structure for 16 Mb NAND EEPROMs,� Digest of IEEE Int. Electron Device Meeting, San Francisco, 1990, pp. 103�106);
FIGS. 5A�5E are cross sectional views of various embodiments of the invention from the same vantage point illustrated in FIG. 3.
FIGS. 6A�6B illustrates the operation of the novel NOR flash cell formed according to the teachings of the present invention.
FIGS. 5A�5E are cross sectional views of various embodiments of the invention from the same vantage point illustrated in FIG. 3. However, FIGS. 5A�5E are intended to illustrate the numerous floating gate and control gate configurations which are intended within the scope of the present invention. For each of the embodiments illustrated in FIGS. 5A�5E, a wordline (not shown for sake of clarity) will couple to the various control gate configurations along columns of an array, and the sourcelines and bitlines will run along rows of the array (here shown running into the plane of the drawing sheet), in the same fashion as wordline 413, sourcelines 415-1, 415-2, . . . , 415-N, and bitlines 411-1, 411-2, . . . , 411-N are arranged in FIG. 4. For each of the embodiments illustrated in FIGS. 5A�5E, a number of vertical pillars, e.g. 500-1 and 500-2, are illustrated with each pillar containing a pair of NOR flash cells. In these embodiments, a single second source/drain region 506 is shared at the top of each pillar. Each of the pillars are separated by rows of trenches 530. A buried sourceline 504 is located at the bottom of each trench 530, e.g. a doped region implanted in the bottom of trenches 530. In these embodiments, a portion of the buried sourceline undercuts the pillars, e.g. 500-1 and 500-2, on opposing sides to serve as the respective first source/drain region for the pair of NOR flash cells. Thus, on each side of a pillar, a conduction channel 505 can be created in the body 507 of the pillar between the second source/drain region 503 and the respective sourcelines in each neighboring trench.
In the embodiment of Figure 5B, a pair of control gates, shown as 513-1 and 513-2, are formed in trenches, e.g. trench 530, below the top surface of the pillars, 500-1 and 500-2, and between the pair of floating gates 509-1 and 509-2. Each one of the pair of control gates, 513-1 and 513-2, addresses the floating gates, 509-1 and 509-2 respectively, on opposing sides of the trench 530. In this embodiment, the pair of control gates 513-1 and 513-2 are separated by an insulator layer.
FIGS. 6A�B and 7 are useful in illustrating the use of charge storage in the floating gate to modulate the conductivity of the NOR flash memory cell according to the teachings of the present invention. That is, FIGS. 6A�6B illustrates the operation of the novel NOR flash memory cell 601 formed according to the teachings of the present invention. And, FIG. 7 illustrates the operation of a conventional DRAM cell 501. As shown in FIG. 7, the gate insulator 702 is made thicker than in a conventional DRAM cell. For example, an embodiment of the gate insulator 610 has a thickness 611 equal to or greater than 10 nm or 100 Å (10−6 cm). In the embodiment shown in FIG. 7A a NOR flash memory cell has dimensions 613 of 0.1 μm (10−5 cm) by 0.1 μm. The capacitance, Ci, of the structure depends on the dielectric constant, ∈i, and the thickness of the insulating layers, t. In an embodiment, the dielectric constant is 0.3�10−12 F/cm and the thickness of the insulating layer is 10−6 cm such that Ci=∈i/t, Farads/cm2 or 3�10−7 F/cm2. In one embodiment, a charge of 1012 electrons/cm2 is programmed into the floating gate of the NOR flash memory cell. This produces a stored charge ΔQ=1012 electrons/cm2�1.6�10−19 Coulombs. In this embodiment, the resulting change in the threshold voltage (Δ Vt) of the NOR flash memory cell will be approximately 0.5 Volts (ΔVt=ΔQ/Ci or 1.6�10−7/3�10−7=� Volt). For ΔQ=1012 electrons/cm3 in an area of 10−10 cm2, this embodiment of the present invention involves trapping a charge of approximately 100 electrons in the floating gate of the NOR flash memory cell. In this embodiment, an original VT is approximately � Volt and the VT with charge trapping is approximately 1 Volt.
Conversely, if the nominal threshold voltage without the floating gate charged is � V, then I=μCox�(W/L)�((Vgs−Vt)2/2), or 12.5 μA, with μCox=μCi=100μA/V2 and W/L=1. That is, the NOR flash memory cell of the present invention, having the dimensions describe above will produce a current I=100 μA/V2�(�)�(�)=12.5 μA. Thus, in the present invention an unwritten, or un-programmed NOR flash memory cell can conduct a current of the order 12.5 μA, whereas if the floating gate is charged then the NOR flash memory cell will not conduct. As one of ordinary skill in the art will understand upon reading this disclosure, the sense amplifiers used in DRAM arrays, and as describe above, can easily detect such differences in current on the bit lines.
By way of comparison, in a conventional DRAM cell 750 with 30 femtoFarad (fF) storage capacitor 751 charged to 50 femto Coulombs (fC), if these are read over 5 nS then the average current on a bit line 752 is only 10 μA (I=50fC/5 ns=10 μA). Thus, storing a 50 fC charge on the storage capacitor equates to storing 300,000 electrons (Q=50fC/(1.6�10−19)=30�104=300,000 electrons).
According to the teachings of the present invention, the floating gate transistors in the array are utilized not just as passive on or off switches as transfer devices in DRAM arrays but rather as active devices providing gain. In the present invention, to program the floating gate transistor �off,� requires only a stored charge in the floating gate of about 100 electrons if the area is 0.1 μm by 0.1 μm. And, if the NOR flash memory cell is unprogrammed, e.g. no stored charge trapped in the floating gate, and if the floating gate transistor is addressed over 10 nS a of current of 12.5 μA is provided. The integrated drain current then has a charge of 125 fC or 800,000 electrons. This is in comparison to the charge on a DRAM capacitor of 50 fC which is only about 300,000 electrons. Hence, the use of the floating gate transistors in the array as active devices with gain, rather than just switches, provides an amplification of the stored charge, in the floating gate, from 100 to 800,000 electrons over a read address period of 10 nS.
FIG. 9 is a block diagram of an electrical system, or processor-based system, 900 utilizing NOR flash memory 912 constructed in accordance with the present invention. That is, the NOR flash memory 912 utilizes the modified NOR flash cell architecture as explained and described in detail in connection with FIGS. 2�6. The processor-based system 900 may be a computer system, a process control system or any other system employing a processor and associated memory. The system 900 includes a central processing unit (CPU) 902, e.g., a microprocessor, that communicates with the NOR flash memory 912 and an I/O device 908 over a bus 920. It must be noted that the bus 920 may be a series of buses and bridges commonly used in a processor-based system, but for convenience purposes only, the bus 920 has been illustrated as a single bus. A second I/O device 910 is illustrated, but is not necessary to practice the invention. The processor-based system 900 can also includes read-only memory (ROM) 914 and may include peripheral devices such as a floppy disk drive 904 and a compact disk (CD) ROM drive 906 that also communicates with the CPU 902 over the bus 920 as is well known in the art.
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