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Patent US8068369 - Sense amplifier circuit and semiconductor memory device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response...http://www.google.com/patents/US8068369?utm_source=gb-gplus-sharePatent US8068369 - Sense amplifier circuit and semiconductor memory deviceAdvanced Patent SearchPublication numberUS8068369 B2Publication typeGrantApplication numberUS 12/461,858Publication dateNov 29, 2011Filing dateAug 26, 2009Priority dateAug 29, 2008Also published asUS20100054065Publication number12461858, 461858, US 8068369 B2, US 8068369B2, US-B2-8068369, US8068369 B2, US8068369B2InventorsKazuhiko KajigayaOriginal AssigneeElpida Memory, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (8), Referenced by (9), Classifications (10), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSense amplifier circuit and semiconductor memory device
US 8068369 B2Abstract
A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor has a gate connected to the sense node and amplifies a signal transmitted from the bit line via the first MOS transistor. The predetermined voltage is supplied to the bit line before read operation and is set to a value such that a required voltage difference at the sense node between high and low level data of the memory cell can be obtained near a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell.
1. A sense amplifier circuit of a single-ended type amplifying a signal which is read out from a memory cell and is transmitted through a bit line, comprising:
a first MOS transistor supplying a predetermined voltage to the bit line and controlling a connection between the bit line and a sense node in response to a control voltage applied to a gate thereof; and
a second MOS transistor having a gate connected to the sense node and amplifying a signal transmitted from the bit line via the first MOS transistor,
wherein the sense amplifier circuit has operating modes including a charge transfer mode and a charge distributing mode, and
wherein the predetermined voltage is supplied to the bit line before a read operation of the memory cell, and the predetermined voltage is set to a value such that a required voltage difference at the sense node between high level data and low level data read out from the memory cell can be obtained in a vicinity of a changing point between the charge transfer mode and the charge distributing mode within a range of a read voltage of the memory cell.
2. The sense amplifier circuit according to claim 1, wherein a variation permissible range of a threshold voltage of the first MOS transistor and a variation permissible range of a threshold voltage of the second MOS transistor are set within the required voltage difference at the sense node.
3. The sense amplifier circuit according to claim 1, further comprising:
a first sense amplifier including the first MOS transistor and the second MOS transistor; and
a second sense amplifier connected to an input/output node to which a drain current of the second MOS transistor is supplied and including a signal voltage determination circuit determining a signal voltage level at the input/output node.
4. The sense amplifier circuit according to claim 1, further comprising:
a local sense amplifier including the first MOS transistor and the second MOS transistor and amplifying a signal transmitted through a local bit line as the bit line; and
a global sense amplifier connected to a global bit line which is selectively connected to a predetermined number of the local bit lines via the local sense amplifier, and including a signal voltage determination circuit determining a signal voltage level of the global bit line.
5. The sense amplifier circuit according to claim 3, further comprising a third MOS transistor precharging the sense node and the bit line to a predetermined precharge voltage in response to a precharge signal applied to a gate thereof.
6. The sense amplifier circuit according to claim 4, further comprising a third MOS transistor precharging the sense node and the bit line to a predetermined precharge voltage in response to a precharge signal applied to a gate thereof.
7. The sense amplifier circuit according to claim 5, wherein the predetermined precharge voltage is set to a voltage lower than the predetermined voltage supplied to the bit line.
8. The sense amplifier circuit according to claim 6, wherein the predetermined precharge voltage is set to a voltage lower than the predetermined voltage supplied to the bit line.
9. The sense amplifier circuit according to claim 3, further comprising:
a fourth MOS transistor switching a connection between a drain of the second MOS transistor and the input/output node in response to a first control signal applied to a gate of the fourth MOS transistor; and
a fifth MOS transistor switching a connection between the sense node and the input/output node in response to a second control signal applied to a gate of the fifth MOS transistor.
10. The sense amplifier circuit according to claim 4, further comprising:
a fourth MOS transistor switching a connection between a drain of the second MOS transistor and the global bit line in response to a first control signal applied to a gate of the fourth MOS transistor; and
a fifth MOS transistor switching a connection between the sense node and the global bit line in response to a second control signal applied to a gate of the fifth MOS transistor.
11. The sense amplifier circuit according to claim 5, wherein the predetermined voltage is supplied to the bit line via the third MOS transistor.
12. The sense amplifier circuit according to claim 6, wherein the predetermined voltage is supplied to the bit line via the third MOS transistor.
13. The sense amplifier circuit according to claim 9, wherein the predetermined voltage is supplied to the bit line via the fifth MOS transistor.
14. The sense amplifier circuit according to claim 10, wherein the predetermined voltage is supplied to the bit line via the fifth MOS transistor.
15. The sense amplifier circuit according to claim 4, further comprising a compensated voltage generating circuit generating a compensated voltage of which fluctuation of a threshold voltage of the first MOS transistor or the second MOS transistor is compensated for an input reference voltage, and supplying the compensated voltage to the local sense amplifier or the global sense amplifier.
16. A semiconductor memory device having the sense amplifier circuit according to claim 1.
17. The sense amplifier circuit according to claim 1, wherein the predetermined voltage (Vb) satisfies the formula Vb=Vg−Vt1, where Vg is the control voltage and Vt1 is a threshold voltage of the first MOS transistor.
18. A circuit for amplifying a signal which is read out from a memory cell and is transmitted through a bit line, comprising:
a first MOS transistor supplying a predetermined voltage to the bit line and controlling a connection between the bit line and a sense node in response to a control voltage applied to a gate of the first MOS transistor;
a second MOS transistor including a gate connected to the sense node and amplifying a signal transmitted from the bit line via the first MOS transistor, a drain current of the second MOS transistor being supplied to an input/output node;
a third MOS transistor precharging the sense node and the bit line to a predetermined precharge voltage in response to a precharge signal applied to a gate of the third MOS transistor;
a fifth MOS transistor switching a connection between the sense node and the input/output node in response to a second control signal applied to a gate of the fifth MOS transistor,
wherein the predetermined voltage is supplied to the bit line before a read operation of the memory cell, and the predetermined voltage is set to a value such that a required voltage difference at the sense node between high level data and low level data read out from the memory cell can be obtained in a vicinity of a changing point between the charge transfer mode and the charge distributing mode within a range of a read voltage of the memory cell. Description
The present invention relates to a single-ended sense amplifier circuit amplifying a signal read out from a memory cell and transmitted through a bit line, and to a semiconductor memory device having the single-ended amplifier circuit.
As capacity of semiconductor memory devices such as a DRAM has recently become large, it has become difficult to obtain a sufficient capacitance value of a capacitor included in a memory cell for the purpose of miniaturization of the memory cell. A charge transfer type sense amplifier circuit is conventionally known as a sense amplifier circuit suitable for amplifying a minute signal voltage read out from the memory cell. For example, configurations of a variety of charge transfer type sense amplifiers are disclosed in the following Patent References 1 to 4.
Patent Reference 1: Japanese Patent Application Laid-open No. 2000-195268 Patent Reference 2: Japanese Patent Application Laid-open No. 2002-157885 Patent Reference 3: Japanese Patent Application Laid-open No. H11-16384 Patent Reference 4: Japanese Patent Application Laid-open No. 2007-73121 FIG. 23 shows a configuration example of a conventional typical charge transfer type sense amplifier circuit. In FIG. 23, there are shown a memory cell MC composed of an N-type selection transistor Q0 and a capacitor Cs, two N-type MOS transistors Qg and Qp, and a latch type differential amplifier 100. The selection transistor Q0 has a source connected to a bit line BL, and a gate connected to a word line WL. The capacitor Cs is connected between the drain of the selection transistor Q0 and a ground potential. The MOS transistor Qg switches connection between the bit line BL and a sense node Ns in response to a control voltage Vg inputted to the gate of the MOS transistor Qg. The MOS transistor Qp switches connection between a power supply voltage VDD and the sense node Ns in response to a control signal SET inputted to the gate of the MOS transistor Qp. The latch type differential amplifier 100 receives a signal voltage at the sense node Ns and a reference voltage Vr respectively, and amplifies a difference therebetween and latches it. In addition, the reference voltage Vr is set to an intermediate voltage of the both voltages at the sense node Ns in reading out high and low level data from the memory cell MC.
In FIG. 23, a bit line capacitance Cb is formed at the bit line BL and a capacitance Ca is formed at the sense node Ns. It has been found from the study of the inventor that operation modes assumed in a sense amplifier circuit are determined depending on parameters such as the capacitance Cs of the capacitor, the potential of the bit line BL and the bit line capacitance Cb, and the potential of the sense node Ns and the capacitance Ca (refer to FIG. 1 and description thereof), and that the sense amplifier circuit is operated in accordance with later-mentioned formulas 1 to 3. It has been confirmed that a charge transfer mode is dominant in the conventional charge transfer type sense amplifier circuit shown in FIG. 23 among the above-mentioned operation modes.
However, when using the charge transfer type sense amplifier circuit of FIG. 23, it is inevitable that the capacitance Ca at the sense node Ns increases since the large-scale latch type differential amplifier 100 is employed. For example, in a configuration including 512 memory cells MC on one bit line BL, it is assumed that the capacitance Ca=10 fF at the sense node Ns is obtained for the bit line capacitance Cb=50 fF. As a result of the study of the inventor under such a condition, it has been found that the amplifying operation of the sense amplifier circuit is not hindered when the power supply voltage VDD is relatively high (for example, 3V or 2V), however, the amplifying operation is hindered when lowering the power supply voltage VDD, for example, an operation under VDD=1V (refer to FIGS. 5 and 6 and descriptions thereof). Under this condition, the voltage difference at the sense node Ns in reading out high and low level data from the memory cell MC becomes reduced, and sufficient operating margin cannot be obtained. Further, it has been found that such a tendency becomes further pronounced when using the capacitor Cs having a smaller capacitance to miniaturize the memory cell MC. As described above, the conventional charge transfer type sense amplifier circuit has a problem in that it is difficult to apply to the configuration achieving the lower voltage operation using memory cells MC having a small capacitance.
The present invention seeks to solve one or more of the above problems and provides a sense amplifier circuit capable of obtaining a sufficient operating margin in a read operation by appropriately controlling amplifying operations in a charge transfer mode and in a charge distributing mode, in case of achieving low voltage operation in a semiconductor memory device employing memory cells each including a capacitor having a small capacitance.
An aspect of the invention is a sense amplifier circuit of a single-ended type amplifying a signal which is read out from a memory cell and is transmitted through a bit line, comprising: a first MOS transistor supplying a predetermined voltage to the bit line and controlling connection between the bit line and a sense node in response to a control voltage applied to a gate thereof; and a second MOS transistor having a gate connected to the sense node and amplifying a signal transmitted from the bit line via the first MOS transistor. In the sense amplifier of the aspect, the predetermined voltage is supplied to the bit line before a read operation of the memory cell, and the predetermined voltage is set to a value such that a required voltage difference at the sense node can be obtained in a vicinity of a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell when reading out high level data and low level data of the memory cell.
According to the sense amplifier circuit of the aspect, in a read operation of the memory cell, the first MOS transistor functions as a charge transfer gate in a state of supplying the predetermined voltage to the bit line in response to the control voltage, and the signal voltage is amplified by the second MOS transistor connected to the sense node based on a charge transfer mode or a charge distributing mode. At this point, when reading out high and low level data in the memory cell, a voltage relation is set so as to obtain a sufficient voltage difference between the high and low level data. Also, since the employment of the single-ended sense amplifier circuit allows the capacitance at the sense node to be reduced, a configuration advantageous for improving operating margin particularly in a low voltage operation can be achieved when memory cells having small capacitance are employed.
Particularly the sense amplifier circuit of the aspect is effectively applied to a hierarchical memory cell array. That is, in a configuration in which a predetermined number of local bit lines are selectively connected to a global bit line via the local sense amplifier, the circuit scale can be smaller by using the single-ended local sense amplifier without employing a differential configuration, and sufficient operating margin of the sense amplifier circuit can be obtained.
Further, particularly the sense amplifier circuit of the aspect is effectively combined with a compensated voltage generating circuit generating a compensated voltage of which fluctuation of a threshold voltage of the first or second MOS transistor is compensated. By supplying such a compensated voltage to the sense amplifier circuit, the above-mentioned operating margin can be further improved.
As described above, according to the invention, when the single-ended sense amplifier is employed in which amplifying operation is controlled based on the charge transfer mode and the charge distributing mode, since the capacitance at the sense node can be small, sufficient operating margin in a low voltage operation of about 1V can be obtained. Particularly, an advantageous configuration can be achieved when using memory cells having a small capacitance of under about 5 fF.
Further, in a semiconductor memory device having a hierarchical bit line structure and a hierarchical sense amplifier circuit, the capacitance at each local bit line can be set to a small value, and therefore excellent operating margin can be obtained in the large capacity semiconductor memory device.
Furthermore, fluctuation of the threshold voltage of the MOS transistor due to manufacturing process and temperature can be appropriately compensated by using the compensated voltage generating circuit. Therefore, the operating margin for sensing can be further improved, thereby improving reliability of the operation of the sense amplifier circuit. Or, since the variation permissible range in the chip can be expanded, when large number of sense amplifier circuits can be implemented in a large capacity DRAM using memory cells having small capacitance, it is possible to improve production yield and to reduce manufacturing cost.
The above featured and advantages of the invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a diagram for explaining basic operating principle of a sense amplifier circuit of embodiments;
FIG. 2 is a diagram showing a configuration example of a sensing part in a DRAM of a first embodiment;
FIG. 3 is a diagram showing an example of a circuit configuration of a sense latch circuit of FIG. 2;
FIGS. 4A and 4B are diagrams for explaining an amplifying operation of the sense amplifier circuit of the first embodiment;
FIG. 5 is a diagram showing a first comparison example corresponding to the amplifying operation of the conventional sense amplifier circuit;
FIG. 6 is a diagram showing a second comparison example corresponding to the amplifying operation of the conventional sense amplifier circuit;
FIG. 7 is a diagram showing a configuration example of a sensing part in a DRAM of a second embodiment;
FIG. 8 is a diagram showing an example of a circuit configuration of a global sense amplifier of FIG. 7;
FIGS. 9A and 9B are diagrams for explaining an amplifying operation of the sense amplifier circuit of the second embodiment;
FIG. 10 is a diagram for explaining a read operation in the DRAM of the second embodiment and showing operation waveforms in a case of reading high level data from a memory cell;
FIG. 11 is a diagram for explaining a read operation in the DRAM of the second embodiment and showing operation waveforms in a case of reading low level data from the memory cell;
FIG. 12 is a diagram showing an example of a circuit configuration of a local sense amplifier in a modification of the second embodiment;
FIG. 13 is a diagram for explaining a read operation in FIG. 12 and showing operation waveforms in a case of reading high level data from a memory cell;
FIG. 14 is a diagram for explaining a read operation in FIG. 12 and showing operation waveforms in a case of reading low level data from a memory cell;
FIG. 15 is a diagram showing an example of a circuit configuration of a global sense amplifier of a third embodiment;
FIG. 16 is a diagram showing a circuit configuration example of a control voltage generating circuit functioning as a compensated voltage generating circuit of the third embodiment;
FIG. 17 is a graph showing an example of process/temperature dependency of a control voltage Vg outputted from the above control voltage generating circuit of FIG. 16;
FIG. 18 is a block diagram showing another example of the compensated voltage generating circuit of the third embodiment;
FIG. 19 is a diagram showing a circuit configuration example of a threshold voltage monitor part of FIG. 18;
FIG. 20 is a diagram showing a circuit configuration example of a level correction part of FIG. 18;
FIG. 21 is a graph showing an example of process/temperature dependency of a correction signal δVt outputted from the level correction part of FIG. 18;
FIG. 22 is a diagram showing a circuit configuration example of a compensated voltage adding part of FIG. 18; and
FIG. 23 is a diagram showing a configuration example of a conventional typical charge transfer type sense amplifier circuit.
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. In the following, three embodiments will be described, in which the invention is applied to a semiconductor memory device having a sense amplifier circuit.
Basic operating principle of a sense amplifier circuit of the embodiments will be described with reference to FIG. 1. In the following, a charge transfer mode and a charge distributing mode are mainly assumed as operation modes of the sense amplifier circuit. FIG. 1 schematically shows a configuration of an input side of the sense amplifier circuit operating in the charge transfer mode and the charge distributing mode. In FIG. 1, there are shown a memory cell MC composed of an N-type selection transistor Q0 and a capacitor Cs, and a sense amplifier circuit including two N-type MOS transistors Qg and Qp.
The selection transistor Q0 has a source connected to a bit line BL, and a gate connected to a word line WL. Further, the capacitor Cs is connected between the drain of the selection transistor Q0 and a ground potential. The MOS transistor Qg functioning as a charge transfer gate is connected between the bit line BL and a sense node Ns. The MOS transistor Qp for supplying the bit line potential is connected between a power supply voltage VDD and the sense node Ns. A control voltage Vg is applied to the gate of the MOS transistor Qg, and a control signal SET is applied to the gate of the MOS transistor Qp. In FIG. 1, a bit line capacitance Cb formed at the bit line BL, a capacitance Ca formed at the sense node Ns, a voltage Vb at the bit line BL, and a voltage Va at the sense node Ns are respectively shown. Among these, the bit line capacitance Cb and the capacitance Ca at the sense node Ns are determined depending on parasitic capacitance of lines, input capacitance of transistors, the number of memory cells MC, or the like.
The sense node Ns is set to the power supply voltage VDD by the operation of the MOS transistor Qp for supplying the bit line potential before a read operation of the memory cell MC. At this point, the voltage Vb (the predetermined voltage of the invention) satisfying Vb=Vg−Vt1 based on the control voltage Vg and a threshold voltage Vt1 of the MOS transistor Qg is supplied to the bit line BL via the MOS transistor Qg.
Thereafter, the MOS transistor Qp is turned off, and subsequently the word line WL is driven so that the selection transistor Q0 is turned on. Thereby, the sensing operation of the sense amplifier circuit is started. When a voltage at a charge accumulation node N0 of the memory cell MC is assumed to be Vs, there can be following three operations in accordance with relations between values of Vs, Vb and VDD.
(1) The MOS transistor Qg is maintained off.
(2) Electric charge is transferred via the MOS transistor Qg in the above-mentioned charge transfer mode.
(3) Electric charge is transferred via the MOS transistor Qg in the above-mentioned charge distributing mode.
Here, the voltage Vb corresponding to a boundary (changing point) between the operation (2) and the operation (3) is defined as Vc. By using this voltage Vc, the voltage Va at the sense node Ns after the above operation is completed can be represented as following formulas 1, 2 and 3 respectively corresponding to the operations (1), (2) and (3).
Vb≦Vs:Va=VDD (formula 1)
Vs<Vb≦Vc:Va=VDD+(Cs/Ca)Vs−(Cs/Ca)Vb (formula 2)
Vc<Vb:Va=(CsVs+CaVDD)/(Cs+Cb+Ca)+(Cb/(Cs+Cb+Ca))Vb (formula 3)
Here, the voltage Vc is calculated according to a following equation.
Vc=((Cs+Cb)CaVDD)+(Cs+Cb)CsVs)/(Cs(Cs+Cb+Ca)+CbCa)
For example, the conventional sense amplifier shown in FIG. 23 is mainly operated in the charge transfer mode of the above formula 2, which corresponds to a charge transfer type sense amplifier. However, the sense amplifier circuit of the embodiments has a feature of being operated by controlling the charge transfer mode and the charge distributing mode.
A first embodiment of the invention will be described below. A feature of the first embodiment is that a single-ended sense amplifier circuit controlled in the charge transfer mode and the charge distributing mode is employed. FIG. 2 shows a configuration example of a sensing part in a DRAM of the first embodiment, in which a memory cell MC, a preamplifier 10 (the first sense amplifier of the invention) functioning as the above basic operation of the sense amplifier circuit, and a sense latch circuit 11 (the second sense amplifier of the invention) located subsequent to the preamplifier 10 are shown.
The memory cell MC is a 1T1C type DRAM memory cell composed of an N-type MOS selection transistor Q0, and a capacitor Cs storing information as electric charge. The selection transistor Q0 has a source connected to the bit line BL and a gate connected to the word line WL. The capacitor Cs is connected between the drain of the selection transistor Q0 and a cell plate voltage VPLT. Although FIG. 2 shows one memory cell MC, a large number of memory cells MC arranged at intersections of a plurality of word lines WL and a plurality of bit lines BL are practically provided. In the first embodiment, it is assumed that 512 memory cells MC, for example, are connected to one bit line BL. In this case, the bit line capacitance Cb totally formed at one bit line BL is, for example, 50 fF.
The preamplifier 10 includes five N-type MOS transistors Q1, Q2, Q3, Q4 and Q5. The MOS transistor Q1 (the first MOS transistor of the invention) functioning as the charge transfer gate is connected between the bit line BL and the sense node Ns of the side of the preamplifier 10, and the control voltage Vg is applied to its gate. The MOS transistor Q2 (the second MOS transistor of the invention) functioning as an amplifying element has a gate connected to the sense node Ns, and senses and amplifies the signal transmitted from the bit line BL via the MOS transistor Q1 so as to convert the signal into a drain current. The drain current flows from an input/output node N1 of the side of the preamplifier 10 to a ground via the MOS transistors Q4 and Q2.
A precharge signal PC is applied to the gate of the MOS transistor Q3 functioning as a transistor for precharging the bit line BL, and the MOS transistor Q3 precharges the sense node Ns to a ground potential when the precharge signal PC is high. When the sense node Ns is precharged, the bit line BL is precharged to the ground potential via the MOS transistor Q1. The MOS transistor Q4 for read control switches connection between the input/output node N1 and the MOS transistor Q2 in response to a control signal RT applied to the gate of the MOS transistor Q4. The MOS transistor Q5 for write control switches connection between the input/output output node N1 and the sense node Ns in response to a control signal WT applied to the gate of the MOS transistor Q5.
Since the preamplifier 10 has a simple configuration including five MOS transistor as shown in FIG. 2, the value of the capacitance Ca formed at the sense node Ns in the preamplifier 10 is, for example, 1 to 2 fF, which is much smaller than that of the bit line capacitance Cb.
FIG. 3 shows an example of a circuit configuration of the sense latch circuit 11 subsequent to the preamplifier 10. As shown in FIG. 3, the input/output node N1, a read bus/RDL and a write bus/WDL are connected to the sense latch circuit 11, and the sense latch circuit 11 includes three P-type MOS transistors Q10, Q13 and Q15, and eight N-type MOS transistors Q11, Q12, Q14, Q16 to Q20. The MOS transistor Q10 for precharging is connected between the power supply voltage VDD and the input/output node N1. The MOS transistor Q10 precharges the input/output node N1 to the power supply voltage VDD when an inverted precharge signal/PC applied to the gate is low. The MOS transistor Q11 switches connection between the input/output node N1 and a node N2 in response to a control signal LTC applied to the gate. Further, the MOS transistor Q12 switches connection between the input/output node N1 and a node N3 in response to a control signal RES applied to the gate.
A signal voltage decision latch 11 a includes MOS transistors Q13, Q14, Q15 and Q16, and determines a binary level of a signal transmitted from the preamplifier 10 to the input/output node N1 so as to latch the signal. In the signal voltage decision latch 11 a, a pair of MOS transistors Q13 and Q14 having gates connected to the node N2 forms a sensing inverter having relatively large driving force. Similarly, a pair of MOS transistors Q15 and Q16 having gates connected to the node N3 forms a latching inverter having relatively small driving force.
Two MOS transistors Q17 and Q18 are connected in series as a read circuit between the read bus/RDL and the ground, and an output signal SD (node N3) of the signal voltage decision latch 11 a is inputted to the gate of the MOS transistor Q17. Two MOS transistors Q19 and Q20 are connected in series as a write circuit between the write bus/WDL and the node N2, and a write enable signal WE is inputted to the gate of the MOS transistor Q19. A sense amplifier selection signal YS is commonly inputted to the gates of the MOS transistors Q18 and Q20.
In a read operation, the latch control signal LTC becomes high and the sense amplifier selection signal YS becomes high, and the output signal SD of the sensing inverter is outputted to the read bus/RDL. At this point, the output signal SD appearing at the node N3 has a voltage obtained by inverting the logic value at the input/output node N1. In a rewrite operation performed for avoiding destruction of data of memory cells MC after the read operation, the latch control signal LTC becomes low, the control signal RES becomes high, and the output signal SD is outputted to the input/output node N1 via the NMOS transistor Q12.
Meanwhile, in a write operation, the sense amplifier selection signal YS becomes high, the write enable signal WE becomes high, and write data is inputted through the write bus/WDL. The write data is inverted by the sensing inverter, and outputted to the input/output node N1 via the MOS transistor Q12.
Next, an amplifying operation of the sense amplifier circuit of the first embodiment will be descried using FIGS. 4A and 4B. FIGS. 4A and 4B show two graphs corresponding to two conditions of capacitances for the purpose of explaining the amplifying operation of the sense amplifier circuit of the first embodiment. In each graph, the power supply voltage VDD=1V is assumed, a characteristic W1 (H) represents a characteristic when reading high level data from the memory cell MC (Vs=1V), and a characteristic W1(L) represents a characteristic when reading low level data level data from the memory cell MC (Vs=0V). In addition, the voltage Vs is a voltage of the capacitor Cs at the charge accumulation node N0. Further, regarding the bit line capacitance Cb, the capacitance of the capacitor Cs (Hereinafter referred to simply as “capacitance Cs”) of the memory cell MC and the capacitance Ca at the sense node Ns, settings in FIG. 4A are Cb=50 fF, Cs=5 fF and Ca=2 fF, and settings in FIG. 4B are Cb=50 fF, Cs=2 fF and Ca=1 fF.
In FIGS. 4A and 4B, since the power supply voltage VDD is 1V in the characteristic W1 (H) of reading high level data, the voltage Va is maintained at 1V for a change in the voltage Vb in accordance with the above formula 1. Meanwhile, the characteristic W1(L) of reading low level data is operated in the charge transfer mode in accordance with the above formula 2 before reaching a changing point P1 (left side of P1), and is operated in the charge distributing mode in accordance with the above formula 3 after passing the changing point P1 (right side of P1). In each graph, a range within which the signal voltage can be read out is determined by a voltage difference between the characteristics W1(H) and W1(L).
Each of FIGS. 4A and 4B also shows a setting example of a variation permissible range Rvt1 for the threshold voltage in the preamplifier 10. A width along a longitudinal axis of the variation permissible range Rvt1 indicates a variation permissible range of a threshold voltage Vt2 of the MOS transistor Q2, and a width along a horizontal axis of the variation permissible range Rvt1 indicates a variation permissible range of a threshold voltage Vt1 of the MOS transistor Q1. In addition, the voltage Vb is set to a voltage lower than the constant control voltage Vg of the MOS transistor Q1 by the threshold voltage Vt1 of the MOS transistor Q1. In the examples of FIGS. 4A and 4B, the variation permissible range of the threshold voltage Vt2 of the MOS transistor Q2 is within 0.5 to 0.8V, and the variation permissible range of the threshold voltage Vt1 of the MOS transistor Q1 is within 0.2 to 0.5V. It is a condition for a stable amplifying operation by the preamplifier 10 that the variation permissible range Rvt1 entirely exists within an area surrounded by the characteristics W1(H) and W1(L). In this case, the larger the variation permissible range Rvt1 in the area surrounded by the characteristics W1(H) and W1(L), the larger the operating margin so as to improve the reliability of the amplifying operation.
Here, FIGS. 5 and 6 show two graphs corresponding to the amplifying operation of the conventional sense amplifier circuit (FIG. 23) as a comparison example of FIGS. 4A and 4B. In each of FIGS. 5 and 6, the power supply voltage VDD is assumed to be operated under 3V, and characteristics in reading high/low level data are shown for three conditions of voltages VDD=3V, 2V, 1V. Further, Cs=5 fF is set in FIG. 5 corresponding to FIG. 4A, and Cs=2 fF is set in FIG. 6 corresponding to FIG. 4B. Also, Cb=50 fF and Ca=10 fF are set in both FIGS. 5 and 6. In FIG. 5, values (3, 2, 1) of VDD, high level data(H) and low level data(L) are denoted with parentheses for respective values of the characteristics W, the changing points P, the permissible ranges X and Y along the longitudinal and horizontal axes. Also, the same representations are shown in FIG. 6 for characteristics W′, changing points P′ and permissible ranges X′ and Y′ along the longitudinal and horizontal axes. Here, X and X′ indicate permissible ranges of a set value of the voltage Vb, while Y and Y′ indicate a difference between read signal voltages of high and low level data in the permissible ranges X and X′.
In the conventional sense amplifier circuit, positions of the changing points P and P′ are shifted to right in a case of the power supply voltage VDD=3V/2V, and thus it is understood that the charge transfer mode is dominant. Here, the difference between read signal voltages is decreased in the case of Cs=2 fF in FIG. 6, in which memory cells having a lower capacitance is employed, relative to the case of Cs=5 fF in FIG. 5. Further, as apparent from FIGS. 5 and 6, it is difficult to obtain the above-mentioned permissible ranges X and Y under a condition of VDD=1V, and it is also difficult to use the conventional sense amplifier circuit in such a low-voltage operation. As described above, the case of FIG. 4 has a remarkable difference in that operating margin is largely improved particularly under the condition of low voltage operation of VDD=1V in comparison with FIGS. 5 and 6. This is mainly an effect due to a reduction in the capacitance Ca at the sense node Ns by employing the single-ended preamplifier 10. In addition, the characteristic W(1L) at VDD=1V of FIG. 5 is represented by a dotted line in FIG. 4A, and the characteristic W′ (1L) at VDD=1V of FIG. 6 is represented by a dotted line in FIG. 4B, which are compared with each other.
Next, a second embodiment of the invention will be described. In the second embodiment, a hierarchical memory cell array is formed, and a charge transfer/distributing type single-ended sense amplifier is applied to a DRAM having hierarchical bit lines and hierarchical sense amplifier circuits. FIG. 7 shows a configuration example of a sensing part in the DRAM of the second embodiment, in which a memory cell MC, a local bit line LBL and a global bit line GBL which serve as the hierarchical bit lines, and a local sense amplifier 20 and a global sense amplifier 21 which serve as the hierarchical sense amplifier circuits are respectively shown. The local bit line LBL connected to the memory cell MC is selectively connected the global bit line GBL via the local sense amplifier 20, and data thereof is transmitted to the corresponding global sense amplifier 21. Although FIG. 7 shows only part of the configuration, the second embodiment employs the configuration in which each local sense amplifier 20 is shared by local bit lines LBL on both sides and each global sense amplifier 21 is shared by global bit lines GBL on both sides. Thereby, the number of the local sense amplifiers 20 and global sense amplifiers 21 can be reduced so as to reduce the chip area.
The memory cell MC has the same structure as that in FIG. 2 of the first embodiment. In the second embodiment, for example, 32 memory cells MC are connected to one local bit line LBL. In this case, the bit line capacitance Cb formed at the local bit line LBL has, for example, a capacitance Cb=3 fF. Further, one local sense amplifier 20 is shared by two local bit lines LBL, so that 64 memory cells MC are connected to the local sense amplifier 20. In the local sense amplifier 20, a circuit portion including the MOS transistors Q1 to Q5 is common to the preamplifier 10 of the first embodiment. Meanwhile, in the local sense amplifier 20, in addition to the MOS transistor Q1 functioning as the charge transfer gate of one local bit line LBL, there is further provided a MOS transistor Q6 functioning as the charge transfer gate of the other local bit line LBL (node N10). A control signal CTL is applied to the gate of the MOS transistor Q1 of the left side of FIG. 7, and a control signal CTR is applied to the gate of the MOS transistor Q6 of the right side of FIG. 7.
Further, for example, eight local sense amplifiers 20 are connected to one global bit line GBL. In this case, 512 memory cells MC in total can be selectively connected to one global bit line GBL. A parasitic capacitance Cgb is formed at each global bit line GBL. There are provided a MOS transistor Q7 switching connection to one global bit line GBL and a MOS transistor Q8 switching connection to the other global bit line GBL, on both sides of the global sense amplifier 21. Then, the global sense amplifier 21 can be selectively connected to either of the global bit lines GBL on both sides by using a control signal SHL applied to the gate of the MOS transistor Q7 and a control signal SHR applied to the gate of the MOS transistor Q8.
FIG. 8 shows an example of a circuit configuration of the global sense amplifier 21. As shown in FIG. 8, the global sense amplifier 21 has substantially the same circuit configuration as the sense latch circuit 11 of the first embodiment (FIG. 3), so description thereof will be omitted. However, a difference exists in that a node N12 in FIG. 8 corresponding to the input/output node N1 in FIG. 3 is connected to the above two MOS transistors Q7 and Q8 on both sides of the global sense amplifier 21.
FIGS. 9A and 9B show two graphs for explaining an amplifying operation of the sense amplifier circuit of the second embodiment. The two graphs as shown in FIG. 9 correspond to two conditions of capacitances for the relation between the voltages Va and Vb similarly as in FIG. 4 of the first embodiment. A characteristic W2(H) represents a characteristic when reading high level data from the memory cell MC (Vs=1V), and a characteristic W2(H) represents a characteristic when reading low level data from the memory cell MC (Vs=0V). Further, regarding the bit line capacitance Cb, the capacitance Cs of the memory cell MC, and the capacitance Ca at the sense node Ns, Cb=3 fF, Cs=5 fF and Ca=2 fF are set in FIG. 9A, and Cb=3 fF, Cs=2 fF and Ca=1 fF are set in FIG. 9B. Other conditions are the same as in FIG. 4.
Each of FIGS. 9A and 9B also shows a setting example of a variation permissible range Rvt2 for the threshold voltage similarly as in FIGS. 4A and 4B. In the graphs of FIGS. 9A and 9B, it is found that the variation permissible range Rvt2 can be set to be larger within an area surrounded by the characteristics W2(H) and W2(L), in comparison with the graphs of FIGS. 4A and 4B. That is, this means that the operating margin of the local sense amplifier 20 increases. This is an effect of a decrease in the bit line capacitance Cb of the local bit line LBL resulting from the hierarchical structure of bit lines. As described above, the local bit line LBL is driven to the voltage Vb=Vg−Vt1 via the MOS transistor Q1 having the threshold voltage Vt1, and however the time required for the operation is shortened with a decrease in the bit line capacitance Cb, thereby obtaining an additional effect of high-speed read operation.
Next, a read operation in the DRAM of the second embodiment will be described with reference to FIGS. 10 and 11. FIG. 10 shows operation waveforms in a case of reading high level data from the memory cell MC, and FIG. 11 shows operation waveforms in a case of reading low level data from the memory cell MC. As shown in upper parts of FIGS. 10 and 11, the entire operation is divided into six terms (T1 to T6).
As shown in FIG. 10, in the read operation of high level data, the local bit line LBL and the sense node Ns are precharged to the ground potential VSS (0V) and the global bit line GBL is precharged to the power supply voltage VDD, before a precharge cancellation term T1. At this point, the precharge signal PC, the control signals SHL, SHR, CTL, CTR, and the latch control signal LTC are respectively high, and the inverted precharge signal/PC, the control signals WT, RT and RES are respectively low.
In the precharge cancellation term T1, the precharge signal PC is controlled to be low so that the MOS transistor Q3 is turned off, and the local bit line LBL and the sense node Ns are precharged to the ground potential VSS and become floating. Further, the control signals SHR and CTR are both controlled to be low, the non-selected global bit lines GBL is disconnected from the global sense amplifier 21, and the non-selected local bit line LBL is disconnected from the local sense amplifier 20. Here, the control signal CTL is set to a voltage value of the above control voltage Vg. In addition, the non-selected local sense amplifier 20 is maintained in a state where the precharge signal PC and the control signals CTL and CTR are controlled to be high and the control signals RT and WT are controlled to be low.
In a local bit line voltage set term T2, the control signal WT is controlled to be the positive voltage VPP and is maintained in this state for a given period. The MOS transistor Q5 is turned on by the control signal WT controlled to be at the positive voltage VPP, and the sense node Ns in the local sense amplifier 20 is driven to the power supply voltage VDD through the global bit line GBL. As a result, the local bit line LBL is driven to the voltage Vg−Vt1 via the MOS transistor Q1. Thereafter, the inverted precharge signal/PC is controlled to be high, and the global bit line GBL is maintained in a state of being precharged to the power supply voltage VDD.
In a cell selection term T3, the word line WL is driven from the negative voltage VKK to the positive voltage VPP. Thereby, a signal voltage of the memory cell MC maintaining high level is read out to the local bit line LBL. At this point, since the voltage Vb of the local bit line LBL is higher than the voltage Vg−Vt1, the MOS transistor Q1 is maintained off. Thus, the sense node Ns is maintained at the power supply voltage VDD.
In a sense term T4, the control signal RT is controlled to be high and is maintained in this state for a given period. At this point, since the potential of the sense node Ns is higher than the upper limit of the variation permissible range Rvt of the threshold voltage Vt2 of the MOS transistor Q2, a large drain current flows through the MOS transistor Q2. Accordingly, electric charge which is charged in the parasitic capacitance Cgb at the global bit line GBL is extracted in a short time by the MOS transistor Q2, and thus the global bit line GBL is rapidly discharged so that its potential changes from the power supply voltage VDD to the ground potential VSS. The potential of the global bit line GBL reaches the ground potential VSS at the end of the sense term T4 and is inverted by the signal voltage decision latch 21 a of the global sense amplifier 21 so that the output signal SD changes to the power supply voltage VDD. Thereafter, the latch control signal LTC is controlled to be low, and the sense term T4 is finished.
In addition, the variation permissible range Rvt of the threshold voltage Vt2 of the MOS transistor Q2 is determined depending on a range in which an entire variation distributed, for example, depending on a minute variation in dimension when forming transistors, variation in thickness of a gate insulating film, a random fluctuation in channel impurity distribution, or the temperature.
Subsequently, in a restore term T5, the control signal RES is controlled to be the positive voltage VPP, the output signal SD of the global sense amplifier 21 is outputted to the global bit line GBL via the MOS transistor Q12, and the potential of the global bit line GBL changes to the power supply voltage VDD. Subsequently, the control signal WT is again controlled to be the positive voltage VPP, and the global bit line GBL is connected to the sense node Ns via the MOS transistor Q5. Then, the control signal CTL maintained at the control voltage Vg is controlled to be the positive voltage VPP at the approximately same timing, and the local bit line LBL is connected to the sense node Ns via the MOS transistor Q1. Thereby, high level data is rewritten into the memory cell MC.
In a precharge term T6, the word line WL is returned to the negative voltage VKK. Subsequently, the control signals WT and RES are controlled to be low, and the latch control signal LTC is controlled to be high. Subsequently, the precharge signal PC is controlled to be high, the inverted precharge signal/PC is controlled to be low, the local bit line LBL and the sense node Ns are both precharged to the ground potential VSS, and the global bit line GBL is precharged to the power supply voltage VDD. Thereby, the output signal SD of the signal voltage decision latch 21 a changes to low. Finally, the control signals SHR and CTR are controlled to be the positive voltage VPP, and the read operation is completed.
Next, as shown in FIG. 11, the operation until the local bit line voltage set term T2 in reading low level data is performed in the same manner as in FIG. 10, so description thereof will be omitted. In the subsequent cell selection term T3, the word line WL is driven from the negative voltage VKK to the positive voltage VPP, and a signal voltage of the memory cell MC maintaining low level is read out to the local bit line LBL. At this point, since the voltage Vb of the local bit line LBL is lower than the voltage Vg−Vt1, the MOS transistor Q1 is turned on. As a result, electric charge of the capacitance Ca at the sense node Ns is transferred to the local bit line LBL via the MOS transistor Q1 in the charge transfer mode or the charge distributing mode, and thereby the voltage Va at the sense node Ns is lowered.
In the sense term T4, the control signal RT is controlled to be high and is maintained in this state for a given period. At this point, since the potential of the sense node Ns is lower than the lower limit of the variation permissible range Rvt of the threshold voltage Vt2 of the MOS transistor Q2, the drain current does not flow through the MOS transistor Q2. Thus, the potential of the global bit line GBL is maintained at the power supply voltage VDD. The potential of the global bit line GBL reaches the power supply voltage VDD at the end of the sense term T4, the potential is inverted by the signal voltage decision latch 21 a of the global sense amplifier 21, and the output signal SD is maintained at the ground potential VSS. Thereafter, the latch control signal LTC is controlled to be low, and the sense term T4 is finished.
In the restore term T5, the control signal RES is controlled to be the positive voltage VPP, the output signal SD of the global sense amplifier 21 is outputted to the global bit line GBL via the MOS transistor Q12, and the potential of the global bit line GBL changes to the ground potential VSS. Subsequently, the control signal WT is again controlled to be the positive voltage VPP, and the global bit line GBL is connected to the sense node Ns via the MOS transistor Q5. Then, the control signal CTL maintained at the control voltage Vg is controlled to be the positive voltage VPP at the approximately same timing, and the local bit line LBL is connected to the sense node Ns via the MOS transistor Q1. Thereby, low level data is rewritten into the memory cell MC.
In the precharge term T6, the word line WL, the control signals WT and RES, the latch control signal LTC, the precharge signal PC, and the inverted precharge signal/PC are controlled in the same manner as in FIG. 10. At this point, the local bit line LBL, the sense node Ns and the global bit line GBL are respectively precharged, each of which returns to an initial state. Finally, the control signals SHR and CTR are controlled to be the positive voltage VPP, and the read operation is completed.
Here, the operation waveforms shown in FIGS. 10 and 11 are applied to the read operation of the second embodiment, and also substantially the same operation waveforms can be applied to the first embodiment. In this case, the local bit line LBL may be replaced with the bit line BL, the global bit line GBL may be replaced with the input/output node N1, the control signal CTL may be replaced with the control voltage Vg, and the control signals CTR, SHL and SHR may be neglected.
Next, a modification of the second embodiment will be described. FIG. 12 shows a configuration as the modification of the second embodiment, in which part of the local sense amplifier 20 is modified. That is, in FIG. 12, the source of the MOS transistor Q3 is connected to a power supply VPC driven to both a predetermined voltage and the ground potential. This predetermined voltage is set to, for example, 1.5V. In addition, other circuit portions in FIG. 12 are common to those in FIG. 7, so description thereof will be omitted.
FIGS. 13 and 14 are diagrams explaining a read operation in the DRAM of this modification, and show operation waveforms corresponding to FIGS. 10 and 11. Since many of the operation waveforms in FIGS. 13 and 14 are common to those in FIGS. 10 and 11, only differences therebetween will be described below. In this modification, the sense node Ns is set to a high voltage of 1.5V, and thus the power supply VPC is increased from the ground potential VSS to 1.5V by controlling the precharge signal PC at the positive voltage VPP in the local bit line voltage set term T2. Thereby, the sense node Ns is driven by the power supply VPC. As shown in FIGS. 13 and 14, an increase in the voltage Va at the sense node Ns results in an effect of expanding the variation permissible range Rvt of the threshold voltage Vt2. In addition, since the method of driving the potential of the sense node Ns is modified, also the control of the inverted precharge signal/PC and the control signal WT is different from that in FIGS. 10 and 11.
Next, a third embodiment of the invention will be described. In a DRAM of the third embodiment, hierarchical bit lines and sense amplifier circuits are configured in the same manner as the second embodiment, part of which differs from the second embodiment. Although the circuit configuration in FIG. 7 of the second embodiment is almost common to the third embodiment, a configuration of certain power source circuits is modified. That is, a compensated voltage generating circuit which compensates fluctuation of the threshold voltage Vt1 of the MOS transistor Q1 and a compensated voltage generating circuit which compensates fluctuation of the threshold voltage Vt2 of the MOS transistor Q2 are employed. Specific configurations thereof will be described below.
FIG. 15 shows an example of a circuit configuration of the global sense amplifier 21 of the third embodiment. The basic circuit configuration in FIG. 15 is almost common to FIG. 8 of the second embodiment, in which however a difference exists in the power source circuits as mentioned above. That is, the power supply voltage VDD supplied to the MOS transistor Q10 and the signal voltage decision latch 21 a is replaced with a voltage VSNH, and the ground potential VSS supplied to the MOS transistor Q17 and the signal voltage decision latch 21 a is replaced with a voltage VSNL. The above compensated voltage generating circuits are employed in order to generate the voltages VSNH and VSNL, which will be described in detail below.
FIG. 16 shows a circuit configuration example of a control voltage generating circuit functioning as the above compensated voltage generating circuit of the third embodiment. This control voltage generating circuit is a feedback type power supply generating circuit generating a control voltage Vg in which the fluctuation of the threshold voltage Vt1 of the MOS transistor Q1 is compensated, and is used for the purpose of, for example, applying a high voltage of the control signal CTL to the gate of the MOS transistor Q1. As shown in FIG. 16, the control voltage generating circuit includes a replica MOS transistor Q1 r, a constant current source 40, and two operational amplifiers 41 and 42. Further, a positive voltage VDL and a negative voltage VEL are used as a pair of constant voltage power supplies, the positive voltage VDL is supplied to the replica MOS transistor Q1 r and to the operational amplifiers 41 and 42, and the negative voltage VEL is supplied to one end of the constant current source 40 and to the operational amplifiers 41 and 42.
In FIG. 16, the replica MOS transistor Q1 r functions as a replica transistor of the MOS transistor Q1 of the local sense amplifier 20 (FIG. 7), and formed in the same shape and size as the MOS transistor Q1. A drain current equal to a constant current Ib1 flowing in the constant current source 40 connected to the source of the replica MOS transistor Q1 r flows in the replica MOS transistor Q1 r. The operational amplifier 41 receives a source voltage of the replica MOS transistor Q1 r at a minus-side input terminal via a resistor, and receives the voltage Vb at a plus-side input terminal. An output voltage of the operational amplifier 41 is inputted to the gate of the replica MOS transistor Q1 r via a resistor. In this case, feedback control is performed so that the output voltage of the operational amplifier 41 matches a value obtained by adding the voltage Vb to the threshold voltage Vt1 of the replica MOS transistor Q1 r. Meanwhile, the subsequent operational amplifier 42 receiving the output voltage of the operational amplifier 41 forms a voltage follower to strengthen current driving ability, and outputs the control voltage Vg equal to Vb+Vt1.
The control voltage Vg outputted from the control voltage generating circuit of FIG. 16 is applied to the gate of the MOS transistor Q1 in the sensing operation. With the fluctuation of the threshold voltage Vt1 of the MOS transistor Q1 in the configuration of FIG. 7, the voltage Vb of the local bit line LBL given by Vb=Vg−Vt1 fluctuates. Meanwhile, in the third embodiment, since the control voltage generating circuit of FIG. 16 generates the control voltage Vg in which the threshold voltage Vt1 is compensated, the value of the voltage Vb is always maintained constant even when the threshold voltage Vt of MOS transistors fluctuates due to manufacturing process and temperature. Accordingly, actual variations can be small enough relative to the variation permissible range Rvt of the threshold voltage in FIG. 4 or 9, thereby further improving the operating margin of the sense amplifier circuit. By employing the control voltage generating circuit of FIG. 16, a variation factor actually existing is becomes restrictive, which is based on a difference between characteristics of the MOS transistor Q1 and the replica MOS transistor Q1 r, thereby reliably enabling the compensation of the manufacturing process or temperature.
FIG. 17 is a graph showing an example of process/temperature dependency of the control voltage Vg outputted from the above control voltage generating circuit. In FIG. 17, three types of characteristics including a typical operation characteristic Sa(typ), a fast operation characteristic Sa(fast), and a slow operation characteristic Sa(slow) are compared corresponding to variation in manufacturing process, and each relation between the temperature and a fluctuation amount of the control voltage Vg is shown in the graph. In addition, the fluctuation amount of the control voltage Vg along a longitudinal axis is a value obtained by a criterion in which the manufacturing process is “typ” and the temperature is 50 degrees. Here, the current Ib1 of the constant current source 40 in FIG. 16 is desired to be set to a small value, for example, 1 nA. This is because when driving the local bit line LBL to the voltage Vb, a value of the current flowing in the MOS transistor Q1 finally becomes extremely small and the current Ib1 needs to match this value.
Next, FIG. 18 is a block diagram showing another example of the compensated voltage generating circuit of the third embodiment, which is used to generate, for example, the voltages VSNH and VSNL of FIG. 15, and the cell plate voltage VPLT and the voltage Vb of FIG. 12. As shown in FIG. 18, the compensated voltage generating circuit includes a threshold voltage monitor part 30 which monitors the threshold voltage Vt2 of the MOS transistor Q2 of the local sense amplifier 20 and generates a monitor signal Sm, a level correction part 31 which shits the monitor signal Sm from the threshold voltage monitor part 30 by a correction amount corresponding to the manufacturing process and generates a correction signal δVt, and a compensated voltage adding part 32 which generates a compensated voltage by adding the reference voltage and the correction signal δVt of the level correction part 31.
FIG. 19 shows a circuit configuration example of the threshold voltage monitor part 30 of FIG. 18. As shown in FIG. 19, the threshold voltage monitor part 30 includes a replica MOS transistor Q2 r, a constant current source 43 and an operational amplifier 44. The replica MOS transistor Q2 r functions as a replica transistor of the MOS transistor Q2 to be monitored, and formed in the same shape and size as the MOS transistor Q2. The constant current source 43 in which a constant current Ib2 flows has the same connection relation as the constant current source 40 of FIG. 16. The operational amplifier 44 receives a source voltage of the replica MOS transistor Q2 r at a minus-side input terminal via a resistor, and receives the ground potential at a plus-side input terminal. An output voltage of the operational amplifier 44 is inputted to the gate of the replica MOS transistor Q2 r via a resistor. In this case, feedback control is performed for the output signal Sm of the operational amplifier 44 so that the source voltage of the replica MOS transistor Q2 r matches the ground potential. Accordingly, the threshold voltage Vt2 of the MOS transistor Q2 r can be monitored by using the ground potential as a criterion based on the output signal Sm.
FIG. 20 shows a circuit configuration example of the level correction part 31 of FIG. 18. As shown in FIG. 20, the level correction part 31 includes a selector 45, a tap selecting circuit 46, a low pass filter 47, and three operational amplifiers 48, 49 and 50. The selector 45 functioning as a correction amount setting circuit sets a desired voltage selected from a large number of intermediate voltages between the positive power supply voltage VDL and the negative the power supply voltage VEL by resistive division based on correction amount information sent from the tap selecting circuit 46, and outputs a correction amount Vm. Selection of the intermediate voltages in the selector 45 is programmed in the tap selecting circuit 46. The correction amount Vm is set so that, for example, the correction signal δVt becomes 0V when the manufacturing process is “typ” and the temperature is 50 degrees. By setting the correction amount Vm in this manner, it is possible to obtain the correction signal δVt in which the fluctuation of the threshold voltage Vt2 of the MOS transistor Q2 due to the fluctuation of manufacturing process at the temperature of 50 degrees is compensated. In order to program the correction amount Vm, it is possible to utilize, for example, laser fuses, electrical fuses, a nonvolatile memory element, or a one-time programmable element.
The first operational amplifier 48 inverts and amplifies the monitor signal Sm of the threshold voltage monitor part 30, and outputs an inverted monitor signal −Sm. The second operational amplifier 49 receives the inverted monitor signal −Sm at a minus-side input terminal and receives the correction amount Vm smoothed through the low pass filter 47 composed of a resistor and a capacitor at a plus-side input terminal as s shifted voltage. When resistors R1 and R2 are arranged as shown in FIG. 20, a signal Sm+2Vm obtained by adding 2Vm to the signal Sm is outputted from the operational amplifier 49. The third operational amplifier 50 forms a voltage follower and outputs the correction signal δVt equal to Sm+2Vm.
FIG. 21 is a graph showing an example of process/temperature dependency of the correction signal δVt outputted from the above level correction part 31. In FIG. 21, three operation characteristics Sb are shown in a graph in the same manner as in FIG. 17. Here, the current Ib2 of the constant current source 43 in FIG. 19 is desired to be set to a relatively large value, for example, 1 μA. This is because when driving the global bit line GBL to the ground VSS, a value of the current flowing in the MOS transistor Q2 is large to some extent and the current Ib2 needs to match this value.
FIG. 22 shows a circuit configuration example of the compensated voltage adding part 32 of FIG. 18. As shown in FIG. 22, the compensated voltage adding part 32 includes three operational amplifiers 51, 52 and 53. The first operational amplifier 51 adds the reference voltage Vref and the correction signal δVt of the level correction part 31 and inverts and amplifies the added signal. The second operational amplifier 52 further inverts and amplifies the output of the operational amplifier 51 and generates a voltage Vref+δVt. The third operational amplifier 53 forms a voltage follower and outputs the voltage Vref+δVt. As described above, the voltages VSNH and VSNL, the cell plate voltage VPLT, the predetermined voltage corresponding to the voltage Vb can be respectively used as the reference voltage Vref in FIG. 22. The value of the reference voltage Vref is set to, for example, 1.0V for the voltage VSNH, 0V for the voltage VSNL, and 0.5V for the cell plate voltage. In these cases, assuming that the value of the correction signal δVt is 0�0.1V, a voltage obtained by adding a fluctuation component �0.1V to the reference voltage Vref in each case can be generated and supplied to a target circuit.
As described above, the fluctuation of the threshold voltage Vt2 of the MOS transistor Q2 due to manufacturing process and temperature can be reflected to each power supply based on the operation of the threshold voltage monitor part 30. Thus, respective values of the voltages VSNH and VSNL, the cell plate voltage VPLT and the voltage Vb can be appropriately set so as to compensate the fluctuation of the threshold voltage Vt2 of the MOS transistor Q2. For example, the voltage VSNH used to precharge the sense node Ns in the local sense amplifier 20 can be controlled to be increased following the increase of the threshold voltage Vt2 of the MOS transistor Q2, and reversely decreased following the decrease of the threshold voltage Vt2. Further, the voltage for writing data of high and low in the memory cell MC can be similarly controlled to be increased or decreased following a change in the threshold voltage Vt2 of the MOS transistor Q2. Furthermore, as to the control voltage Vb or as to the control voltage Vg generated by using the voltage Vb as a criterion, it is possible to control the voltage to be similarly increased or decreased following a change in threshold voltage Vt2 of the MOS transistor Q2. As a result, since each voltage in the sensing part changes in the same manner as the change in the threshold voltage Vt2 of the MOS transistor Q2, the actual variation can be reduced relative to the above-mentioned variation permissible range Rvt of the threshold voltage, thereby further improving the operating margin of the sense amplifier circuit.
In the foregoing, although the contents of the invention have been specifically described based on the embodiments, the invention is not limited the above-described embodiments, and can variously be modified without departing the essentials of the invention. For example, the above embodiments have described the preamplifier 10/the local sense amplifier 20 (the sense amplifier circuit) including five MOS transistors. However, the invention can be widely applied to various sense amplifier circuits having a first MOS transistor functioning as the charge transfer gate and a second MOS transistor amplifying the signal voltage via the first MOS transistor without restriction for other components.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6154402Sep 17, 1999Nov 28, 2000Kabushiki Kaisha ToshibaSemiconductor memory deviceUS6314028 *Jan 8, 2001Nov 6, 2001Mitsubishi Denki Kabushiki KaishaSemiconductor memory device capable of stable sensing operationUS20020060924Nov 20, 2001May 23, 2002Kabushiki Kaisha ToshibaSemiconductor memoryUS20090175066 *Jan 8, 2008Jul 9, 2009Juhan KimHigh-speed DRAM including hierarchical read circuitsJP2000195268A Title not availableJP2002157885A Title not availableJP2007073121A Title not availableJPH1116384A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8310887 *Sep 19, 2011Nov 13, 2012Elpida Memory, Inc.Semiconductor device having single-ended sensing amplifierUS8588019 *Nov 2, 2011Nov 19, 2013Elpida Memory Inc.Semiconductor device having current change memory cellUS8976611 *Mar 15, 2013Mar 10, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Asymmetric sensing amplifier, memory device and designing methodUS8976612Nov 1, 2012Mar 10, 2015Ps4 Luxco S.A.R.L.Sense amplifier circuit and semiconductor deviceUS8982652Nov 13, 2012Mar 17, 2015Ps4 Luxco S.A.R.L.Sense amplifier circuit and semiconductor deviceUS8988958Jun 17, 2014Mar 24, 2015Ps4 Luxco S.A.R.L.Sense amplifier circuit and semiconductor deviceUS20120008368 *Sep 19, 2011Jan 12, 2012Elpida Memory, Inc.Semiconductor device having single-ended sensing amplifierUS20120113735 *Nov 2, 2011May 10, 2012Elpida Memory Inc.Semiconductor device having current change memory cellUS20140269110 *Mar 15, 2013Sep 18, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Asymmetric sensing amplifier, memory device and designing method* Cited by examinerClassifications U.S. Classification365/185.21, 365/196, 365/207International ClassificationG11C16/06Cooperative ClassificationG11C11/4091, G11C7/067, G11C11/4097European ClassificationG11C11/4097, G11C7/06S, G11C11/4091Legal EventsDateCodeEventDescriptionAug 26, 2009ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KAJIGAYA, KAZUHIKO;REEL/FRAME:023174/0422Owner name: ELPIDA MEMORY, INC., JAPANOwner name: ELPIDA MEMORY, INC., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KAJIGAYA, KAZUHIKO;REEL/FRAME:023174/0422Effective date: 20090820Owner name: ELPIDA MEMORY, INC.,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KAJIGAYA, KAZUHIKO;US-ASSIGNMENT DATABASE UPDATED:20100304;REEL/FRAME:23174/422Effective date: 20090820Owner name: ELPIDA MEMORY, INC.,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KAJIGAYA, KAZUHIKO;REEL/FRAME:023174/0422Effective date: 20090820Jul 29, 2013ASAssignmentOwner name: ELPIDA MEMORY INC., JAPANFree format text: SECURITY AGREEMENT;ASSIGNOR:PS4 LUXCO S.A.R.L.;REEL/FRAME:032414/0261Effective date: 20130726May 15, 2014ASAssignmentOwner name: PS4 LUXCO S.A.R.L., LUXEMBOURGFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ELPIDA MEMORY, INC.;REEL/FRAME:032899/0588Effective date: 20130726RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services