Source: http://www.google.com/patents/US7058373?dq=7,181,690
Timestamp: 2017-03-23 02:21:52
Document Index: 157749359

Matched Legal Cases: ['§119', 'art 32', 'art 34', 'art 32', 'art 32', 'art 34', 'art 32', 'art 32', 'art 34', 'art 34', 'art 34', 'art 34', 'art 34', 'art 34', 'art 32', 'art 34', 'art 34', 'art 32', 'art 34', 'art 34', 'art 34', 'art 32', 'art 32', 'art 32', 'art 34', 'art 34', 'art 34', 'art 34', 'art 32', 'art 3']

Patent US7058373 - Hybrid switched mode/linear power amplifier power supply for use in polar ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsIn one aspect this invention provides a DC-DC converter that has a switch mode part for coupling between a DC source and a load, the switch mode part providing x amount of output power; and that further has a linear mode part coupled in parallel with the switch mode part between the DC source and the...http://www.google.com/patents/US7058373?utm_source=gb-gplus-sharePatent US7058373 - Hybrid switched mode/linear power amplifier power supply for use in polar transmitterAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7058373 B2Publication typeGrantApplication numberUS 10/943,547Publication dateJun 6, 2006Filing dateSep 16, 2004Priority dateSep 16, 2003Fee statusPaidAlso published asEP1671197A2, EP1671197A4, EP1671197B1, US7653366, US20050064830, US20060250825, WO2005027297A2, WO2005027297A3, WO2005027297A8Publication number10943547, 943547, US 7058373 B2, US 7058373B2, US-B2-7058373, US7058373 B2, US7058373B2InventorsVlad Gabriel GrigoreOriginal AssigneeNokia CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (26), Non-Patent Citations (2), Referenced by (190), Classifications (28), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetHybrid switched mode/linear power amplifier power supply for use in polar transmitter
52. A method to operate a radio frequency (RF) transmitter (TX), where the TX has a polar architecture comprised of an amplitude modulation (AM) path coupled to a power supply of a power amplifier (PA) and a phase modulation (PM) path coupled to an input of the PA, comprising:
providing the power supply so as to comprise a switch mode part for coupling between a power source and the PA, the switch mode part providing x amount of output power; and
coupling a linear mode part in parallel with the switch mode part between the power source and the PA, the linear mode part providing y amount of output power, where x is greater than y, and the ratio of x to y is optimized for particular application constraints, and where the linear mode part exhibits a faster response time to a required change in output voltage than the switch mode part.
This patent application claims priority under 35 U.S.C. §119(e) from Provisional Patent Application No.: 60/503,303, filed Sep. 16, 2003, the disclosure of which is incorporated by reference herein in its entirety.
In FIG. 1B the output of the power supply 5, Vpa, should be capable of tracking a rapidly varying reference voltage Vm. As such, the power supply 5 must meet certain bandwidth specifications. The required bandwidth depends on the system in which the transmitter 1 is used. For example, the required bandwidth exceeds 1 MHz (dynamic range ˜17 dB for a given power level) for the EDGE system (8 PSK modulation), and exceeds 15 MHz (dynamic range ˜47 dB for a given power level) for the WCDMA (wideband code division multiple access) system. As may be appreciated, these are very challenging requirements. A typical waveform (RF envelope in the EDGE system) that must be tracked is shown in FIG. 2, where the modulating voltage (Vm) is shown as varying between minimum and peak values (the typical rms and average values are also shown).
A second technique, shown in FIG. 4, would be to use a switch mode regulator. In this technique, which is not admitted has been previously used in a polar or ER transmitter, a step-down switching regulator 16 would include a Buck-type or similar converter 18 and voltage-mode control circuitry 20. The PA 6 is shown represented by its equivalent resistance Rpa. While the efficiency of the switch mode regulator 16 can be very high, the required bandwidth would be difficult or impossible to obtain. More specifically, if one where to attempt the use of the switching regulator 16 it would require a very high switching frequency (e.g., at least approximately five times the required bandwidth, or 5–10 MHz or more for EDGE and over 80 MHz for WCDMA). While a switching frequency of 5–10 MHz would be very technically challenging (typical commercial DC-DC converters operate with maximum switching frequencies in the range of about 1–2 MHz), a DC-DC converter having a 100 MHz switching frequency, for example, is currently impractical to implement, especially in low cost, mass produced devices such as cellular telephones and personal communications terminals.
FIGS. 6A–6F illustrate simplified schematic diagrams of embodiments of the hybrid voltage regulator shown in FIG. 5;
(b) the implementation, where one may decide to some extent how much power to process with the switching part 32 and how much with the linear part 34. For example, in EDGE one can process almost all of the power with the switching part 32 by using a 6–7 MHz switching frequency, or less power by using a slower switching converter operating at, e.g., 1 MHz. One may also in certain situations, e.g., at very low power, disable the switching part 32 and use only the linear part 34, in which case the relationship x>y does not apply at all.
FIGS. 6A–6F illustrate various embodiments of the hybrid voltage regulator 30 shown in FIG. 5, where FIGS. 6A, 6C and 6D show the use of a variable voltage source 34A (e.g., the power operational amplifier mentioned above), and where FIGS. 6B, 6E and 6F show the use of a variable current source 34B (e.g., the power operational transconductance amplifier mentioned above). Note that in FIG. 6C two variable voltage sources 34A and 34A′ are used, and that in FIG. 6D the two variable voltage sources 34A and 34A′ are capacitively coupled via C1 to the output power rail of the switching part 32. Note as well that in FIG. 6E two variable current sources 34B and 34B′ are used, and that in FIG. 6F the two variable current sources 34B and 34B′ are capacitively coupled via C1 to the output power rail of the switching part 32.
It is instructive to note that since the linear part 34 has the characteristics of a voltage source, it can fix the voltage level Vpa applied on the PA, and that there is a means to control this voltage level. In addition, the linear part 34 is fast (wide bandwidth), hence it is possible to provide fast modulation of Vpa. Note further that the VCVS 34A of the linear part 34 is bidirectional, in the sense that can both source and sink current.
As was noted, the optional decoupling capacitor Cd may be introduced to ensure that the linear part 34 provides only the AC current component. However, there are certain situations wherein it would be advantageous to allow the linear part 34 to also provide the DC component, albeit with more complicated control. As one example, it may be desirable to provide the DC component from the linear part 34 at low power levels where the switching part 32 maybe de-activated and where the PA 6 current would be provided only by the linear part 34. As another example, it may be desirable to provide the DC component from the linear part 34 at low battery voltage levels, e.g. 2.9V, when the Vpa — peak is very close to this value, e.g. 2.7V, and the switching part 32 is not able to provide it. In such cases the optional Cd would be removed.
FIG. 10 shows an embodiment where a Voltage Controlled Current Source (VCCS) 34B is used to construct the linear part 34. In general, the same considerations apply as in the embodiment of FIG. 7, the only significant difference being that the VCCS is not capable itself to fix the PA 6 voltage level. Instead, the PA 6 voltage is determined by the total current injected into Rpa. The implementation of the linear part 34 can be as an Operational Transconductance Amplifier (OTA), as depicted in FIG. 20B. In this simplified view the collector current of Q1 (Ic1) in the differential pair is mirrored as I5, while the collector current of Q2 (Ic2) is mirrored as I3 and then I4. The output current is I0=I5−I4, and is proportional to the difference between the collector currents IC1–IC2, which in turn is proportional to the differential voltage Vd. As was noted, FIG. 20B shows a simplified representation of the OTA. In practice, a circuit implementation would aim to optimize the accuracy of the current mirrors and to obtain a linear characteristic I0=gVd.
With regard to the simulated waveform diagrams of FIGS. 17 and 18, a similar explanation as was given above for FIGS. I and 12 also applies, except that the contribution of the linear part 34 ilin is partitioned into iaux1 (source) and iaux2 (sink).
In FIG. 21 the switching part 32 operates with voltage-mode control. The controller is composed of a control block 36A that generates an error signal Ve1 and a block 36B with a frequency-dependent characteristic Ge1(s) that has as its input the error signal Ve1 and as its output the control voltage Vctrl — sw for the switching part 32. The error voltage Ve1 is the difference between the reference voltage Vref — sw, which is the modulating signal Vm, and the feedback signal Vfeedback — sw which is the output voltage Vpa. The controller (components 36A, 36B) in this case may be physically implemented as an operational amplifier with an R-C compensation network to obtain the characteristic Gc1(s).
Referring now to FIG. 24, there is shown an embodiment wherein a switching regulator 100 and a linear regulator 102 are coupled in parallel to a SMPA 104 (e.g., a Class E PA) by means of an additional inductor L1 (i.e, additional to the conventional switching part 32 inductor L shown in, for example, FIG. 7B) and an (optional) capacitor C1. The PA 104 supply voltage Vpa is programmed with high accuracy by the linear regulator 102. However, the instantaneous output voltage V1 of the switching regulator 100 cannot be accurately fixed at same value due to the low bandwidth, switching ripple and noise. Therefore, the additional inductor L1 is introduced to accommodate the instantaneous voltage difference Vpa−V1. The average voltage over L1 must be zero, hence the average of V1 equals Vpa.
If C1 is not present, the linear regulator 102 can also provide DC and low frequency components. This may be particularly advantageous under certain conditions, for example when the PA 104 voltage Vpa should be as close as possible to the battery voltage Vbat. One such situation is in the GSM case, at maximum RF output power (the PA 104 needs minimum voltage, e.g., 2.7V), with low battery voltage (e.g., 2.9V). In this case the difference between the input voltage and the output voltage of any regulator interposed between the battery and the PA 104 is very low (only 0.2V in this example). This is a very difficult value to obtain with the switching regulator 100 (considering the voltage drop on one power device, plus the two inductors L and L1, at a duty cycle<100%). In this particular case, the linear regulator 102 can be used to provide the supply voltage nearer to the battery voltage, and thus the linear regulator 102 provides all of the power (DC component, and no capacitor C1). While in this particular case (GSM, max output power, low battery voltage) the efficiency would not be affected because the voltage drop on the linear regulator 102 is small, at lower GSM power levels (i.e. larger drop on the linear regulator 102) the efficiency would be degraded. Therefore, at lower power levels it is more advantageous to use the switching regulator 100 to provide all of the power (DC component).
In FIG. 24 the supply voltage for the linear regulator 102 is Vbat, the same as for the switching regulator 100. While this may be optimum from an implementation point of view, it may not be optimal from an efficiency point of view. At lower power levels, where Vm — pk is much lower than Vbat, the voltage drop on the linear regulator 102 is large and its efficiency is poor. Therefore, a more efficient technique pre-regulates (with high efficiency) the supply voltage of the linear regulator 102 at some level, e.g., 200–300 mV above the peak value of the envelope Vm — pk (see FIG. 2).
In FIG. 25A both regulators 100, 102 are ‘master’, as each has the modulating signal Vm as a reference and each regulator 100, 102 receives its feedback signal (Vfeedback — sw, Vfeedback — in) from its own output.
In the EDGE system or, in general, any system having a variable RF envelope with moderately high dynamics (e.g., required BW>1 MHz), the main functions of the SMPA 104 power supply are power control and envelope tracking. It can be shown that a purely switching regulator with a 6–7 MHz switching frequency is capable of tracking with relatively good accuracy the EDGE RF envelope. However, the system is not robust when using a purely switching regulator, and may exhibit sensitivity to, for example, peaking in the reference-to-output transfer function of the switching regulator 100, and to variations of the SMPA 104 load with the supply voltage (generally the resistance of the SMPA increases as the supply voltage decreases). In addition, there is also the problem of the output voltage ripple, as discussed above. In accordance with this aspect of the invention the linear regulator 102 can be used, if needed, to compensate for the non-optimal dynamics of the switching regulator 100, the SMPA 104 load variation and the switching ripple. If the switching frequency of the switching regulator 100 is sufficiently high enough to allow for good tracking capability, most of the power is processed by the switching regulator 100. However, it is also possible to use a switching regulator 100 with a lower switching frequency, hence with a lower bandwidth, in which case the proportion of the power processed by the linear regulator 102 increases to compensate for the reduction by the switching regulator 100.
With reference to the foregoing, this aspect of the invention provides yet another control mechanism wherein, as in FIG. 21, instead of Vref — lin=Vm, there is instead the relationship Vref — lin=Gc3*Vctrl — sw, where Gc3(s) represents in a simplest case some amount of voltage scaling, and in a more complex case has also a frequency dependent characteristic. Assume as a non-limiting example that Gc3(s)=1. As mentioned above, in the steady-state (constant Vref — sw), Vctrl — sw is proportional to the output voltage Vpa. Assume further for this non-limiting example that the proportionality constant is unity, so that Vpa=Vctrl — sw, and thus also that Vref — lin=Vctrl — sw, so that Vpa=Vref — lin→Ve2=0→ no contribution from the linear part 34. If a fast increase in Vref — sw is provided, this results in a fast increase in Vctrl — sw, as explained above, and thus also a fast increase in Ve2 results in a command to the linear part 34 to source additional current. Similarly, if a fast decrease in Vref — sw is provided, this results in a fast decrease in Vctrl — sw resulting in a fast decrease in Ve2, and the linear part 34 is thus commanded to sink current. Thus, in this manner the linear part 34 is essentially ‘slaved’ to the switching part 32.
In view of the foregoing description of the preferred embodiments of this invention, it should be realized that while the linear stage(s) compensate for the non-ideal dynamics of the switching stage, non-ideal dynamics are also partly caused by non-ideal PA behavior (e.g. load variations), in the sense that Rpa changes with Vpa (i.e., increases when Vpa decreases) and in mismatch conditions. Thus, the linear stage(s) 34, 102 compensate at least for non-ideal dynamics of the switching converter (e.g., insufficient bandwidth and/or peaking in the reference-to-output characteristic). Further in this regard the linear stage(s) 34, 102 and the switching stage 32, 100 complement each other to obtain a specific desired reference-to-output transfer function (not only a specific bandwidth, but also a specific shape of the transfer function). For example, the linear stages 34, 102 may have such a reference-to-output transfer function that the resulting reference-to-output transfer function of the hybrid (switching/linear) power supply is or approximates a flat 2nd order Butterworth filter type. Thus, the linear stage(s) 34, 102 can be used to shape the resulting overall reference-to-output transfer function in order to obtain the desired characteristic. The linear stage(s) 34, 102 also aid in tracking the reference signal, and can be used to obtain a specific desired tracking capability of the reference signal Vm.
The linear stage(s) 34, 102 may also compensate at least for switching ripple, and may also compensate at least for non-ideal PA behavior, such as Rpa variation with operating conditions.
The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the best method and apparatus presently contemplated by the inventor for carrying out the invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. For example, while the power supply of this invention has been described above in the context of a polar or ER transmitter embodiment, the invention can be applied other applications wherein a power supply must meet stringent dynamic requirements, while also exhibiting high efficiency. Further, the various embodiments of FIGS. 6–30 are not to be construed in a limiting sense upon the number of possible embodiments that the hybrid voltage regulator may assume, or of the types of RF power amplifiers and RF communication systems that the embodiments of this invention can be used with. In general, all such and similar modifications of the teachings of this invention will still fall within the scope of the embodiments of this invention.
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