Source: https://patents.google.com/patent/KR20120120458A/en
Timestamp: 2020-01-22 02:13:17
Document Index: 208171525

Matched Legal Cases: ['art 2225', 'art 2227', 'art 2225', 'art 2227', 'art 2277', 'art\n2204', 'art\n2214', 'art\n2231', 'art\n2240']

KR20120120458A - Liquid crystal display device - Google Patents
KR20120120458A
KR20120120458A KR1020127024493A KR20127024493A KR20120120458A KR 20120120458 A KR20120120458 A KR 20120120458A KR 1020127024493 A KR1020127024493 A KR 1020127024493A KR 20127024493 A KR20127024493 A KR 20127024493A KR 20120120458 A KR20120120458 A KR 20120120458A
KR1020127024493A
토시카즈 콘도
2010-02-26 Priority to JPJP-P-2010-042584 priority Critical
2010-02-26 Priority to JP2010042584 priority
2011-02-02 Application filed by 가부시키가이샤 한도오따이 에네루기 켄큐쇼 filed Critical 가부시키가이샤 한도오따이 에네루기 켄큐쇼
2011-02-02 Priority to PCT/JP2011/052676 priority patent/WO2011105210A1/en
2012-11-01 Publication of KR20120120458A publication Critical patent/KR20120120458A/en
This invention makes it a subject to reduce the parasitic capacitance of the signal line which a liquid crystal display device has.
As a transistor provided in each pixel, the transistor provided with an oxide semiconductor layer is applied. In addition, this oxide semiconductor layer is an oxide semiconductor layer which has been highly purified by thoroughly removing impurities (such as hydrogen or water) which becomes an electron donor (donor). This can reduce the leakage current (off current) when the transistor is in the off state. Therefore, it is possible to hold the voltage applied to the liquid crystal element without forming the capacitor in each pixel. In addition to this, it becomes possible to eliminate the capacitor wiring extending to the pixel portion of the liquid crystal display device. Therefore, it is possible to delete the parasitic capacitance in the region where the signal line and the capacitor wiring intersect each other.
[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]
Background Art An active matrix liquid crystal display device having a plurality of pixels arranged in a matrix form is popular. In general, the pixel has a gate electrically connected to a scanning line, one of a source and a drain electrically connected to a signal line, and one terminal of the pixel to an other side of the source and drain of the transistor. A capacitor element electrically connected to a wiring (hereinafter also referred to as a capacitor wiring) to which the other terminal supplies a common potential, and one terminal (pixel electrode) to the other of the source and drain of the transistor and one of the capacitor It has a liquid crystal element electrically connected to the terminal of, and electrically connected to the wiring from which the other terminal (counter electrode) supplies a counter electric potential.
The structural example of the above-mentioned pixel is shown in FIG. Fig. 13A is a top view of the pixel. 13, the figure which abbreviate | omitted a part of liquid crystal element (liquid crystal layer, a counter electrode, etc.) is shown (so-called active-matrix board | substrate is shown). The pixel 1000 illustrated in FIG. 13A is located in an area surrounded by the scan lines 1001 and 1002 arranged in parallel or substantially parallel and the signal lines 1003 and 1004 arranged orthogonally or approximately orthogonally to the scan lines 1001 and 1002. Formed. In the pixel 1000, a transistor 1005, a capacitor 1006, and a pixel electrode layer 1007 are formed. The conductive layer (capacitive wiring 1008) serving as one electrode layer of the capacitor 1006 is arranged to be parallel to or substantially parallel to the scan lines 1001 and 1002 and to traverse a plurality of pixels.
(B) is a figure which shows the cross section in the A-B line | wire shown to FIG. 13 (A). The transistor 1005 includes a gate layer 1011 formed on the substrate 1010, a gate insulating layer 1012 formed on the gate layer 1011, a semiconductor layer 1013 formed on the gate insulating layer 1012, and a semiconductor layer. One side 1014a of the source layer and the drain layer formed on one end of the 1013, and the other side 1014b of the source layer and the drain layer formed on the other end of the semiconductor layer 1013. The capacitor 1006 includes a part of the capacitor wiring 1008, an insulating layer (gate insulating layer 1012) formed on the capacitor wiring 1008, and the other side 1014b of the source layer and the drain layer formed on the insulating layer. It is composed by. The other 1014b of the source layer and the drain layer is electrically connected to the pixel electrode layer 1007 in the contact hole 1016 formed in the insulating layer 1015 formed on the transistor 1005 and the capacitor 1006. have.
(C) is a figure which shows the cross section in the C-D line | wire shown to FIG. 13 (A). The signal line 1003 crosses three-dimensionally through the scanning line 1001 in the region 1017a, the capacitor wiring 1008 in the region 1017b, the scanning line 1002 in the region 1017c, and the gate insulating layer 1012. have. Therefore, the signal line 1003 has a convex surface shape in the regions 1017a, 1017b, and 1017c. Note that although not obvious, the signal line 1004 also has the same top surface shape as the signal line 1003.
In addition, in the liquid crystal display having the pixel 1000 shown in FIG. 13, the scan lines 1001 and 1002 and the capacitor wiring 1008 are formed on the same conductive film, and the gate insulating layer 1012 in the transistor 1005 is formed. It is also applied as a dielectric in the capacitor 1006. That is, this liquid crystal display device can be said to be a liquid crystal display device with a reduced manufacturing process.
In the pixel 1000 illustrated in FIG. 13, the transistor 1005 has a function of controlling the input of a data signal for determining the voltage (potential applied to the pixel electrode layer 1007) applied to the liquid crystal element, and the capacitor element ( 1006 has a function of holding a voltage (potential applied to pixel electrode layer 1007) applied to the liquid crystal element.
For example, when the dielectric of the capacitor 1006 is composed of a silicon oxide film having a thickness of 0.1 μm, the area of the capacitor 1006 having a capacitance value of 0.4 pF is about 1160 μm 2 . Here, when the size of the pixel is 42 µm x 126 µm (a pixel of 4-inch VGA), the ratio of the capacitor 1006 to the area of the pixel is about 22%, which causes a problem that the aperture ratio is lowered. In addition, the capacitor 1006 may be omitted in the pixel configuration. Since there is a storage capacitor of the liquid crystal element itself, it is possible to retain a certain amount of electric charge without forming the capacitor 1006 intentionally. However, since the relative dielectric constant of the liquid crystal is about 3 and the cell gap is 3 to 4 μm, the capacitance becomes about 1/50 compared with the case where the capacitor 1006 having a silicon oxide film having a thickness of 0.1 μm is used as the dielectric. Therefore, the area of the liquid crystal element needs about 58000 µm 2 . That is, since this size is comparable to a pixel of 140 µm x 420 µm, the resolution is about 60 ppi, and a liquid crystal display device having a resolution below that can hold electric charges. In other words, when the pixel is configured with a resolution of 60 ppi or more, the capacitor 1006 is required.
In the liquid crystal display device, the transistor 1005 is turned on by controlling the potential of the scan line 1001, and the potential of the signal line 1003 is controlled to be a data signal for the pixel 1000. Thereby, a desired voltage can be applied to the liquid crystal element which the pixel 1000 has. In addition, since the capacitor 1006 holds this voltage for a certain period, the desired display can be performed in each pixel over a certain period. This liquid crystal display device performs such an operation on each pixel sequentially to form an image (still screen) in the pixel portion. In addition, this liquid crystal display device displays a moving image by sequentially changing this image (for example, 60 times per second (frame frequency is 60 Hz)).
As described above, this moving picture is composed of a plurality of still pictures. In other words, this video is not continuous in a strict sense. Therefore, in the case of displaying a moving video with a high movement rate, the probability of an afterimage or the like on the display increases. In particular, in the liquid crystal display device, each pixel holds the display until the next data signal is input after the data signal is input to each pixel. Therefore, the afterimage tends to surface. Patent Literature 1 discloses a technique for reducing an afterimage (generally referred to as "double speed drive"). Specifically, Patent Literature 1 discloses a technique for reducing an afterimage by creating an image interpolating two images that are subsequently displayed and inserting the images between two images that are subsequently displayed. have.
Japanese Patent Laid-Open No. 4-302289
The above technique can be said to be a technique for increasing the number of data signals input per unit time for each pixel. Therefore, in order to apply this technique to a liquid crystal display device, it is necessary to drive the signal line which is responsible for supplying the data signal to each pixel at high speed. However, in the signal line extending to the pixel portion, parasitic capacitance is generated between other wirings extending to the pixel portion, and this parasitic capacitance may be an obstacle to the high-speed driving of the signal line.
Therefore, one aspect of this invention makes it one of a subject to reduce parasitic capacitance of the signal line which a liquid crystal display device has.
In the liquid crystal display device of one embodiment of the present invention, a transistor including an oxide semiconductor layer is applied as a transistor provided in each pixel. In addition, this oxide semiconductor layer is an oxide semiconductor layer which has been highly purified by thoroughly removing impurities (such as hydrogen or water) which becomes an electron donor (donor). In the highly purified oxide semiconductor layer, there are very few carriers derived from hydrogen or oxygen deficiency, etc. (close to zero), and the carrier density is less than 1 × 10 12 / cm 3 , preferably less than 1 × 10 11 / cm 3 . That is, the carrier density resulting from hydrogen, oxygen deficiency, etc. of an oxide semiconductor layer is made near zero. Since there are very few carriers derived from hydrogen or oxygen vacancies in the oxide semiconductor layer, the leakage current (off current) of the transistor in the off state can be reduced.
This makes it possible to hold the voltage applied to the liquid crystal element without forming the capacitor in each pixel. In addition to this, it becomes possible to eliminate the capacitor wiring extending to the pixel portion of the liquid crystal display device. Therefore, in the conventional liquid crystal display device, the parasitic capacitance is generated in the region where the signal line and the scan line intersect with each other and the region where the signal line and the capacitor line intersect with each other, whereas in the liquid crystal display device of one embodiment of the present invention, There is no parasitic dose. That is, the parasitic capacitance of the signal line can be reduced.
That is, the liquid crystal display device of one embodiment of the present invention includes a first scan line and a second scan line arranged in parallel or substantially parallel, and a first signal line and a second arranged perpendicularly or approximately orthogonally to the first scan line and the second scan line. And an oxide semiconductor layer having a signal line and a gate electrically connected to the first scan line, one of the source and the drain electrically connected to the first signal line, and the other of the source and the drain electrically connected to the pixel electrode layer. Has a transistor. The pixel electrode layer is formed in an area surrounded by the first scan line, the second scan line, the first signal line, and the second signal line. Further, the first signal line and the second signal line three-dimensionally cross the first scan line and the second scan line through an insulating layer formed on the first scan line and the second scan line, and the first signal line three-dimensionally cross the first scan line. The upper surface has a convex surface shape in the area | region and the 2nd area | region which crosses three-dimensionally with a 2nd scanning line. In addition, the upper surface has a planar shape or a substantially planar shape in a region between the first region and the second region. That is, the upper surface of the first signal line exists on the same plane or on substantially the same plane in all regions between the first region and the second region.
The liquid crystal display device of one embodiment of the present invention applies a transistor including an oxide semiconductor layer as a transistor provided in each pixel. This makes it possible to delete the capacitor formed in each pixel. Specifically, even if the liquid crystal display device has a resolution of 60 ppi or more, it is possible to hold a voltage applied to the liquid crystal element without forming a capacitor in each pixel. Thereby, it is possible to improve the aperture ratio in each pixel. In addition to this, it becomes possible to eliminate the capacitor wiring extending to the pixel portion of the liquid crystal display device. That is, in this liquid crystal display device, the parasitic capacitance of a signal line is reduced. Therefore, in the liquid crystal display device of one aspect of the present invention, it becomes possible to improve the drive frequency of the signal line as compared with the conventional liquid crystal display device. That is, the liquid crystal display device of one embodiment of the present invention is suitable as a liquid crystal display device which drives more than double speed driving.
1A is a top view illustrating an example of a structure of a pixel of a liquid crystal display, and FIGS. 1B and 1C are cross-sectional views illustrating an example of a structure of a pixel of a liquid crystal display.
2 shows the characteristics of a transistor;
3 is a circuit diagram for characteristics evaluation of a transistor.
4 is a timing chart for evaluating characteristics of transistors.
5 shows the characteristics of a transistor;
6 shows the characteristics of a transistor;
7 shows the characteristics of a transistor;
8 is a cross-sectional view illustrating an example of a structure of a pixel of a liquid crystal display device.
9 is a cross-sectional view illustrating an example of a structure of a pixel of a liquid crystal display device.
10 (A) and 10 (B) are cross-sectional views showing an example of the structure of a pixel of a liquid crystal display device.
11A to 11D are cross-sectional views each illustrating an example of a transistor manufacturing process.
12A to 12F show an example of an electronic device.
13A is a top view illustrating an example of a structure of a pixel of a liquid crystal display, and FIGS. 13B and 13C are cross-sectional views illustrating an example of a structure of a pixel of a liquid crystal display.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments described below.
(About structure example of pixel)
First, the structural example of the pixel which the liquid crystal display device of one aspect of this invention has is demonstrated with reference to FIG. Specifically, the structural example of the pixel of the liquid crystal display device (the liquid crystal display device which applies a electric field to a liquid crystal material) which has a structure which clamps a liquid crystal material by the one board | substrate with which the pixel electrode was provided, and the other board | substrate with which the counter electrode was provided. This will be described with reference to FIG. 1.
1A is a top view of the pixel. In addition, in FIG.1 (A), the figure which abbreviate | omitted a part of liquid crystal element (liquid crystal layer, a counter electrode, etc.) is shown (it shows what is called an active-matrix board | substrate). The pixel 100 shown in FIG. 1A is located in a region surrounded by the scan lines 101 and 102 arranged in parallel or substantially parallel and the signal lines 103 and 104 arranged orthogonally or approximately orthogonally to the scan lines 101 and 102. Formed. In the pixel 100, a transistor 105 and a pixel electrode layer 107 are formed. In other words, the pixel 100 shown in Fig. 1A has a structure in which the components of the capacitor 1006 are removed from the pixel 1000 shown in Fig. 13A.
(B) is a figure which shows the cross section in the E-F line | wire shown to FIG. 1 (A). The transistor 105 includes a gate layer 111 formed on the substrate 110, a gate insulating layer 112 formed on the gate layer 111, an oxide semiconductor layer 113 formed on the gate insulating layer 112, and an oxide. One side 114a of the source layer and the drain layer formed on one end of the semiconductor layer 113 and the other side 114b of the source layer and the drain layer formed on the other end of the oxide semiconductor layer 113 are provided. The transistor 105 shown in Figs. 1A and 1B uses the protruding portion of the scanning line 101 as a gate, and uses the protruding portion of the signal line 103 as one of the source and the drain. Therefore, in the transistor 105 shown in Figs. 1A and 1B, the gate may be expressed as part of the scan line 101, and one of the source and drain may be expressed as part of the signal line 103. Figs. The other side 114b of the source layer and the drain layer is electrically connected to the pixel electrode layer 107 in the contact hole 116 formed in the insulating layer 115 formed on the transistor 105.
(C) is a figure which shows the cross section in the G-H line | wire shown to FIG. The signal line 103 intersects with the scan line 101 in the region 117a, the scan line 102 in the region 117c, and through the insulating layer (gate insulating layer 112). Therefore, the signal line 103 has a convex surface shape at its upper surface in the regions 117a and 117c. In addition, the signal line 103 has a planar shape or a substantially planar top surface in the area 117b between the area 117a and the area 117c. That is, the upper surface of the signal line 103 exists on the same plane or on substantially the same plane in all the regions 117b between the regions 117a and 117c. This is due to the fact that the capacitor wiring is not provided in the liquid crystal display device having the pixel 100. Note that although not obvious, the signal line 104 also has the same top shape as the signal line 103.
As described above, the transistor 105 shown in FIG. 1 includes an oxide semiconductor layer 113 as a semiconductor layer. As oxide semiconductor used for the oxide semiconductor layer 113, In-Sn-Ga-Zn-O type | system | group which is a quaternary metal oxide, In-Ga-Zn-O type which is a ternary metal oxide, In-Sn-Zn-O type , In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, which are binary metal oxides, Sn -Zn-O-based, Al-Zn-O-based, Zn-Mg-O-based, Sn-Mg-O-based, In-Mg-O-based, or In-O-based, Sn-O-based, which are single-type metal oxides, Zn-O system etc. can be used. Further, SiO 2 may be included in the oxide semiconductor. Here, for example, the In-Ga-Zn-O-based oxide semiconductor is an oxide containing at least In, Ga, and Zn, and the composition ratio is not particularly limited. In addition, elements other than In, Ga, and Zn may be included.
In addition, the oxide semiconductor layer 113 may be a thin film represented by the formula InMO 3 (ZnO) m (m> 0). Here, M represents one or a plurality of metal elements selected from Ga, Al, Mn and Co. For example, Ga, Ga and Al, Ga and Mn, or Ga and Co may be selected as M.
The oxide semiconductor described above is highly purified by intentionally excluding impurities such as hydrogen, moisture, hydroxyl groups, or hydrides (also referred to as hydrogen compounds), which are factors of fluctuation, in order to suppress electrical characteristics fluctuations, thereby making it electrically type I (intrinsic). Oxidized oxide semiconductor.
Therefore, the less hydrogen in oxide semiconductor, the better. Further, in the highly purified oxide semiconductor layer, there are very few carriers derived from hydrogen or oxygen deficiency, etc. (close to zero), and the carrier density is less than 1 × 10 12 / cm 3 , preferably less than 1 × 10 11 / cm 3 . . That is, the carrier density resulting from hydrogen, oxygen deficiency, etc. of an oxide semiconductor layer is made near zero. Since there are very few carriers derived from hydrogen or oxygen vacancies in the oxide semiconductor layer, the leakage current (off current) when the transistor is in the off state can be reduced. The smaller the off current, the better. In the transistor using the oxide semiconductor as the semiconductor layer, the current value per μm of the channel width w is 100 zA / μm (motto ampere) or less, preferably 10 zA / μm or less, or 1 zA / μm or less. In addition, since there is no pn junction and no hot carrier degradation, the electrical characteristics of the transistor are not affected by these factors.
Thus, the transistor which used the highly purified oxide semiconductor for the channel formation area | region by thoroughly removing hydrogen contained in an oxide semiconductor layer can make an off current very small. That is, in the non-conducting state of the transistor, the oxide semiconductor layer can be regarded as an insulator, and circuit design can be performed. On the other hand, the oxide semiconductor layer can expect a higher current supply capability than the semiconductor layer formed of amorphous silicon in the conduction state of the transistor.
As the board | substrate 110, glass substrates, such as barium borosilicate glass and an alumino borosilicate glass, can be used.
In the transistor 105, an insulating film serving as a base film may be formed between the substrate 110 and the gate layer 111. The base film has a function of preventing diffusion of impurity elements from the substrate 110, and has a stacked structure of one or a plurality of films selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film. Can be formed.
The material of the gate layer 111 is aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium The element selected from (Sc), the alloy containing the above-mentioned element as a component, or the nitride containing the above-mentioned element can be applied. Moreover, the laminated structure of these materials can also be applied.
The gate insulating layer 112 is formed using a plasma CVD method, a sputtering method, or the like. Insulators such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride layer, or a hafnium oxide layer can be used. Moreover, you may apply the laminated structure which consists of these insulators. For example, as the first gate insulating layer, a silicon nitride layer (SiN y (y &gt; 0)) having a thickness of 50 nm or more and 200 nm or less is formed by a plasma CVD method, and the second gate insulating layer is formed on the first gate insulating layer. As a layer, a silicon oxide layer (SiO x (x> 0)) having a thickness of 5 nm or more and 300 nm or less can be laminated.
The material of one side 114a of the source layer and the drain layer, and the other side 114b of the source layer and the drain layer is aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti) , An element selected from molybdenum (Mo), tungsten (W), an alloy having the above-mentioned element as a component, or a nitride having the above-described element as a component can be used. Moreover, the laminated structure of these materials can also be applied. In addition, it is good also as a structure which laminated | stacked high-melting-point metal layers, such as titanium (Ti), molybdenum (Mo), and tungsten (W), on the Han group or both of lower or upper metal layers, such as aluminum (Al) and copper (Cu). In addition, it is possible to improve the heat resistance by using an aluminum alloy to which an element (Si, Nd, Sc, etc.) which prevents the generation of hillock and whisker generated in the aluminum (Al) film is added.
In the above-described liquid crystal display device, one side 114a of the source layer and the drain layer is part of the signal line 103. Therefore, from the viewpoint of high speed driving of the signal line 103, the source layer and the drain layer are preferably made of a low resistance conductive material so as not to cause a delay of the signal. For example, it is preferable to comprise with low resistance electroconductive materials, such as copper (Cu) or the alloy which uses copper as a main component. It is also possible to have a laminated structure including a layer made of copper (Cu) or an alloy containing copper as the main constituent element.
In the liquid crystal display device described above, the capacitor is not formed in the pixel 100. Therefore, from the viewpoint of retaining the data signal in the pixel 100, it is preferable to apply metal nitride to the source layer and the drain layer in order to suppress the influx of carriers to the oxide semiconductor layer. For example, it is preferable to apply nitrides such as titanium nitride and tungsten nitride. Further, the layer in contact with the oxide semiconductor layer may be formed of a nitride such as titanium nitride and tungsten nitride, and may have a laminated structure in which another conductive layer is formed thereon. For example, it is possible to have a laminated structure of tungsten nitride and copper (Cu).
As the conductive film serving as one side 114a of the source layer and the drain layer, and the other side 114b of the source layer and the drain layer (including a wiring layer formed from the same layer), a conductive metal oxide may be formed. . Examples of conductive metal oxides include indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), indium tin oxide alloy (abbreviated as In 2 O 3 ? SnO 2 , ITO), and indium oxide oxidation Zinc alloys (In 2 O 3 to ZnO) or those in which silicon oxide is included in these metal oxide materials can be used.
As the insulating layer 115, typically, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film can be used.
In addition, an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, or an aluminum nitride oxide film can be formed on the insulating layer 115.
In addition, a planarization insulating film may be formed on the insulating layer 115 in order to reduce surface irregularities caused by the transistor 105. As the planarization insulating film, organic materials such as polyimide, acrylic resin, benzocyclobutene resin and the like can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) and the like can be used. Further, a plurality of insulating films formed of these materials may be stacked to form a planarization insulating film.
(Off current of transistor 105)
Next, the result of having calculated | required the off current of the transistor provided with the highly purified oxide semiconductor layer is demonstrated.
First, considering that the off current of a transistor having a highly purified oxide semiconductor layer is sufficiently small, a transistor sufficiently large with a channel width W of 1 m was prepared and the off current was measured. The result of measuring the off current of the transistor whose channel width W is 1 m is shown in FIG. In FIG. 2, the horizontal axis is the gate voltage VG and the vertical axis is the drain current ID. When the drain voltage VD was +1 V or +10 V, it was found that when the gate voltage VG was in the range of −5 V to −20 V, the off current of the transistor was below the detection limit of 1 × 10 −12 A. . In addition, it turned out that the off-current density (the value per unit channel width (1 micrometer) here) of a transistor will be 1 aA / micrometer (1 x 10-18 A / micrometer) or less.
Next, a result of more accurately calculating the off current of the transistor including the highly purified oxide semiconductor layer will be described. As mentioned above, it turned out that the off current of the transistor provided with the oxide semiconductor layer highly purified is 1x10-12 A or less which is a detection limit of a measuring instrument. Therefore, a description will be made of a result of obtaining a more accurate off current value (a value below the detection limit of the measuring instrument in the measurement) by fabricating a characteristic evaluation element.
First, the element for characteristic evaluation used for the electric current measuring method is demonstrated with reference to FIG.
In the element for characteristic evaluation shown in FIG. 3, three measuring systems 800 are connected in parallel. The measurement system 800 includes a capacitor 802, a transistor 804, a transistor 805, a transistor 806, and a transistor 808. As the transistors 804 and 808, transistors having a highly purified oxide semiconductor layer are used.
In the measurement system 800, one of a source and a drain of the transistor 804, one terminal of the capacitor 802, and one of a source and a drain of the transistor 805 are a power supply (power supply for supplying V2). Is connected to. The other of the source and the drain of the transistor 804, the one of the source and the drain of the transistor 808, the other terminal of the capacitor 802, and the gate of the transistor 805 are electrically connected. It is. The other of the source and the drain of the transistor 808, the one of the source and the drain of the transistor 806, and the gate of the transistor 806 are electrically connected to a power source (power source for supplying V1). The other of the source and the drain of the transistor 805 and the other of the source and the drain of the transistor 806 are electrically connected to the output terminal.
The gate of the transistor 804 is supplied with a potential Vext_b2 that controls the on and off states of the transistor 804, and the gate of the transistor 808 controls the on and off states of the transistor 808. The potential Vext_b1 is supplied. A potential Vout is output from the output terminal.
Next, a current measurement method using the above-described characteristic evaluation element will be described.
First, the approximation of the initial period in which the potential difference is applied to measure the off current will be described. In an initial period, a node (that is, a transistor) is input to the gate of the transistor 808 with a potential Vext_b1 for turning on the transistor 808 and electrically connected to the other of the source and the drain of the transistor 804. A potential V1 is applied to a node A which is one of a source and a drain of 808, another terminal of the capacitor 802, and a node electrically connected to the gate of the transistor 805. Here, the potential V1 is, for example, a high potential. Further, the transistor 804 is turned off.
Thereafter, a potential Vext_b1 for turning off the transistor 808 is input to the gate of the transistor 808 to turn the transistor 808 off. After the transistor 808 is turned off, the potential V1 is lowered. Here too, the transistor 804 is turned off. The potential V2 is set to the same potential as the potential V1. By the above, an initial period is complete | finished. In the state where the initial period is over, a potential difference occurs between the node A and one of the source and the drain of the transistor 804, and the other of the source and the drain of the node A and the transistor 808. Since a potential difference occurs between the transistors, some electric charges flow through the transistors 804 and 808. That is, an off current is generated.
Next, the approximation of the measurement period of the off current will be described. In the measurement period, one potential V2 of the source and the drain of the transistor 804 and the other potential V1 of the source and the drain of the transistor 808 are fixed at a low potential. On the other hand, during the measurement period, the potential of the node A is not fixed (to be in a floating state). As a result, electric charges flow through the transistors 804 and 808, and the amount of charges held in the node A changes over time. And the potential of the node A fluctuates with the fluctuation | variation of the electric charge quantity hold | maintained in the node A. That is, the output potential Vout of the output terminal also fluctuates.
The detail (timing chart) of the relationship of each electric potential in the initial period which gives the said electric potential difference, and the subsequent measurement period is shown in FIG.
In the initial period, first, the potential Vext_b2 is set to the potential (high potential) at which the transistor 804 is turned on. Thus, the potential of the node A becomes V2, that is, the low potential VSS. In addition, it is not essential to give the node A a low potential VSS. Thereafter, the potential Vext_b2 is set to the potential (low potential) at which the transistor 804 is turned off, and the transistor 804 is turned off. Next, the potential Vext_b1 is set to the potential (high potential) at which the transistor 808 is turned on. Thereby, the potential of the node A becomes V1, that is, the high potential (VDD). Thereafter, Vext_b1 is a potential at which the transistor 808 is turned off. As a result, the node A enters the floating state, and the initial period ends.
In the subsequent measurement period, the electric potential V1 and the electric potential V2 flow into the node A, or the electric potential flows out of the node A. Here, the potential V1 and the potential V2 are set to the low potential VSS. However, at the timing of measuring the output potential Vout, it is necessary to operate the output circuit, so that V1 may be set to the high potential VDD temporarily. The period for setting V1 to the high potential (VDD) is set to a short period that does not affect the measurement.
As described above, when the potential difference is given and the measurement period is started, the amount of charge held in the node A changes with time, and the potential of the node A changes accordingly. Since this means that the potential of the gate of the transistor 805 changes, the potential of the output potential Vout of the output terminal also changes with time.
A method of calculating the off current from the obtained output potential Vout will be described below.
Prior to the calculation of the off current, the relationship between the potential VA of the node A and the output potential Vout is determined. Thereby, the potential VA of the node A can be calculated | required from the output potential Vout. From the above relationship, the potential VA of the node A can be expressed as the following equation as a function of the output potential Vout.
The charge QA of the node A is represented by the following equation using the potential VA of the node A, the capacitance CA connected to the node A, and the constant const. Here, the capacitance CA connected to the node A is the sum of the capacitance different from that of the capacitor 802.
Since the current IA of the node A is obtained by the time derivative of the charge flowing into the node A (or the charge flowing out of the node A), the current IA of the node A is given by the following equation. It is shown as:
In this manner, the current IA of the node A can be obtained from the capacitance CA connected to the node A and the output potential Vout of the output terminal.
By the method described above, the leakage current (off current) flowing between the source and the drain of the transistor in the off state can be measured.
Here, transistors 804 and 808 having a highly purified oxide semiconductor layer of channel length L = 10 µm and channel width W = 50 µm were fabricated. In addition, in each measuring system 800 arrange | positioned in parallel, each capacitance value of the capacitance element 802 was 100 fF, 1 pF, and 3 pF.
In the above-described measurement, VDD = 5V and VSS = 0V. In the measurement period, Vout was measured using the potential V1 as the principle, VSS, and every 10 to 300 sec as VDD for only 100 msec. In addition,? T used for calculation of the current (I) flowing in the device was about 30000 sec.
5 shows the relationship between the elapsed time (Time) and the output potential (Vout) related to the current measurement. From Fig. 5, it can be seen that the potential is changing with time.
In FIG. 6, the off current in room temperature (25 degreeC) computed by the said electric current measurement is shown. 6 illustrates the relationship between the source-drain voltage V and the off current I of the transistor 804 or the transistor 808. 6, it turned out that off current is about 40 zA / micrometer on the conditions which source-drain voltage is 4V. Further, it was found that the off current was 10 zA / μm or less under the condition that the source-drain voltage was 3.1V. Also, 1 zA represents 10 -21 A.
In addition, FIG. 7 shows the off current in a temperature environment of 85 ° C. calculated by the current measurement. FIG. 7 shows the relationship between the source-drain voltage V and the off current I of the transistor 804 or the transistor 808 in a temperature environment of 85 ° C. From Fig. 7, it was found that the off current was 100 zA / μm or less under the condition that the source-drain voltage was 3.1V.
As described above, it was confirmed that the off current is sufficiently small in the transistor including the highly purified oxide semiconductor layer.
(About the liquid crystal display device which has the pixel 100)
The liquid crystal display device disclosed in this specification applies the transistor 105 provided with the oxide semiconductor layer as a transistor provided in each pixel. Since the transistor 105 including the oxide semiconductor layer has a small off-state current, in this liquid crystal display device, it is possible to hold a voltage applied to the liquid crystal element without forming a capacitor in each pixel. Therefore, it is possible to improve the aperture ratio in each pixel. In addition, it is possible to delete the capacitor wiring extending to the pixel portion of the liquid crystal display device. Therefore, in the liquid crystal display device disclosed in this specification, parasitic capacitance resulting from capacitance wiring does not exist. Specifically, parasitic capacitance and the like are not present in the region where the signal lines and the capacitor wirings intersect with each other through the insulating layer. As a result, in the liquid crystal display device disclosed in this specification, it becomes possible to improve the drive frequency of a signal line. That is, the liquid crystal display device disclosed in this specification is suitable as a liquid crystal display device which drives more than double speed drive.
In addition, when the drive of the double speed drive or more is performed, the rewrite frequency of the data signal in each pixel is increased. That is, the period of holding the voltage applied to the liquid crystal element in each pixel is shortened. Therefore, it becomes possible to further reduce the fluctuation (deterioration (change) of the display in each pixel) applied to the liquid crystal element. In addition, the same effect is obtained also when the liquid crystal display disclosed by this specification is driven by the field sequential system. That is, it is preferable to drive by the field sequential system with respect to the liquid crystal display device disclosed in this specification.
In particular, the liquid crystal display device disclosed in this specification has a large effect when used as a large liquid crystal display device (for example, 40 inches or more). In addition to the enlargement of the liquid crystal display device, the probability of surface delay or the like due to wiring resistance increases. On the other hand, the liquid crystal display device disclosed in this specification can reduce the delay of a data signal, etc. by reducing the parasitic capacitance which arises in a signal line. In addition, when the number of pixels is the same in the small liquid crystal display device and the large liquid crystal display device, the size of each pixel of the large liquid crystal display device is increased. This means that the capacitance value which the liquid crystal element itself has becomes large. Therefore, in addition to forming the transistor 105 including the oxide semiconductor layer in each pixel, the capacitance value of the liquid crystal element itself is increased, whereby the variation in the voltage applied to the liquid crystal element can be further reduced.
In addition, the liquid crystal display device disclosed in this specification has a great effect when used as a high-precision (high pixel number) liquid crystal display device (for example, full high-definition (FHD), 2K4K or more). As the number of wirings provided in the pixel portion increases in accordance with the high precision (increasing the number of pixels) of the liquid crystal display device, the probability of increasing the parasitic capacitance generated in the signal line is increased. On the other hand, in the liquid crystal display device disclosed in this specification, since capacitance wiring is not provided, it is possible to reduce the increase of parasitic capacitance. In addition, in the liquid crystal display having a large number of pixels and the liquid crystal display having a small number of pixels, when the size of the liquid crystal display is the same, the wiring density in the former pixel portion is increased. This means that the aperture ratio of each pixel is lowered. On the other hand, in the liquid crystal display device disclosed in this specification, since the capacitor | condenser is not formed in each pixel, it is possible to suppress the fall of aperture ratio.
In the conventional liquid crystal display device, although the retention characteristic of the data signal in each pixel is mainly determined by the characteristics (value of the off current) of the transistor provided in each pixel, the transistor is provided with a highly purified oxide semiconductor layer. By applying 105 as a transistor provided in each pixel, it can mainly determine according to the characteristic (current flowing through a liquid crystal element) of a liquid crystal element. That is, in the liquid crystal display device disclosed herein, the influence of the leakage of the charge through the liquid crystal element is greater than the leakage of the charge through the transistor 105. Therefore, it is preferable to apply the substance with high resistivity as a liquid crystal material which a liquid crystal element has. Specifically, in the liquid crystal display device disclosed in this specification, the resistivity of the liquid crystal material is 1 × 10 12 Ω · cm or more, preferably 1 × 10 13 Ω · cm, more preferably 1 × It is preferable that it exceeds 10 14 Ω * cm. In addition, the resistivity of the liquid crystal element in the case where the liquid crystal element is formed using this liquid crystal material is 1 × 10 11 Ω · cm or more, more preferably 1 ×, considering the possibility that impurities from the alignment film and the sealing material are mixed. It is a preferable condition to exceed 10 12 ohm * cm. In addition, the value of specific resistance in this specification is made into the value measured at 20 degreeC.
(About a modification of the structure of the pixel)
The liquid crystal display device having the above-described configuration is an aspect of the present invention, and a liquid crystal display device having a point different from this liquid crystal display device is also included in the present invention.
For example, in the above-described liquid crystal display device, the configuration in which only the gate insulating layer 112 is formed between the signal line 103 and the scanning lines 101 and 102 is shown (see FIG. 1C). The oxide semiconductor layer 201 is formed between the 103 and the gate insulating layer 112 (see Fig. 8A). That is, in the process of forming the oxide semiconductor layer 113 of the transistor 105 (photolithography process and etching process), the oxide semiconductor layer can be left without etching even in a region where the signal line 103 is formed later. Do. As such, by forming the oxide semiconductor layer 201 between the signal line 103 and the gate insulating layer 112, the parasitic capacitance between the signal line 103 and the scan lines 101 and 102 can be further reduced. have.
It is also possible to form an oxide semiconductor layer selectively between the signal line 103 and the gate insulating layer 112. For example, the oxide semiconductor layers 202a and 202b are selectively formed in regions 117a and 117c where the signal lines 103 and the scan lines 101 and 102 are three-dimensionally intersected (see Fig. 8B). It is possible. In addition to the regions 117a and 117c, it is also possible to have a configuration (see Fig. 8C) to form oxide semiconductor layers 202a and 202b selectively in a portion of the region 117b. In this case, a step occurs in the upper surface of the signal line 103 in the region 117b due to the oxide semiconductor layer between the signal line 103 and the gate insulating layer 112. Shall be a shape contained in a substantially planar shape. In other words, the signal line 103 and the gate insulating layer 112 are in direct contact with each other in the region sandwiched between the scanning lines 101 and 102 and the step caused by part of the oxide semiconductor layers 202a and 202b. In the entire area, the upper surfaces of the signal lines 103 all exist on the same plane or on the same plane.
In addition, in the above-mentioned liquid crystal display device, although the structure provided with the channel-etched transistor 105 which is 1 type of the transistor of a bottom gate structure as a transistor provided in each pixel was shown (refer FIG. 1 (B)), It is also possible to apply a transistor having another structure. For example, a channel stop transistor 210 (see Fig. 9A) which is one type of transistor having a bottom gate structure, or a bottom contact type transistor 220 which is one type of transistor having a bottom gate structure (Fig. 9 It is possible to apply b).
Specifically, the channel stop transistor 210 shown in FIG. 9A has a gate layer 111 formed on the substrate 110, a gate insulating layer 112 formed on the gate layer 111, and gate insulation. An oxide semiconductor layer 113 formed on the layer 112, an insulating layer 211 functioning as a channel protective layer formed on the center portion of the oxide semiconductor layer 113, one end and an insulating layer 211 of the oxide semiconductor layer 113. ) And one side 114a of the source and drain layers formed on one end and the other side 114b of the source and drain layers formed on the other end of the oxide semiconductor layer 113 and the other end of the insulating layer 211. The insulating layer 211 can be formed using an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film.
In addition, the bottom contact transistor 220 shown in FIG. 9B includes a gate layer 111 formed on the substrate 110, a gate insulating layer 112 formed on the gate layer 111, and a gate insulating layer. One side 114a of the source layer and the drain layer formed on the 112, and the other side 114b of the source layer and the drain layer, and one end of the source layer and the drain layer on one end 114a of the source layer and the drain layer An oxide semiconductor layer 113 is formed on one end of the other side 114b and on the gate insulating layer 112.
In addition, when the transistor provided in each pixel is the channel stop transistor 210, the structure which forms the insulating layer 212 between the signal line 103 and the gate insulating layer 112 (FIG. 9C). Reference). The insulating layer 212 is an insulating layer formed based on the same material as the insulating layer 211 serving as a channel protective layer of the transistor 210. The oxide semiconductor layer can also be formed (not shown) between the gate insulating layer 112 and the insulating layer 212. The oxide semiconductor layer is an oxide semiconductor layer formed based on the same material as the oxide semiconductor layer 113 included in the transistor 210. Further, the oxide semiconductor layer and the insulating layer may be selectively formed only on the scan line 101 and the scan line 102 (not shown).
It is also possible to apply the top gate transistor 230 (see Fig. 10A) as the transistor 105. Specifically, the top gate transistor 230 shown in FIG. 10A includes a base insulating layer 231 formed on the substrate 110, an oxide semiconductor layer 113 formed on the base insulating layer 231, and The gate insulating layer 112 formed on the oxide semiconductor layer 113, the gate layer 111 formed on the gate insulating layer 112, and the insulating layer 232 formed on the oxide semiconductor layer 113 and the gate layer 111. Formed in the insulating layer 232 formed on one side 114a of the source and drain layers in contact with the oxide semiconductor layer 113 and the oxide semiconductor layer 113 and the gate layer 111. The contact hole 233b has the other side 114b of the source layer and the drain layer which contact the oxide semiconductor layer 113. The other 114b of the source layer and the drain layer is electrically connected to the pixel electrode layer 107 in the contact hole 235 formed in the insulating layer 234 formed on the transistor 230. In this case, the signal line 103 is three-dimensionally intersected with the scanning lines 101 and 102 through the insulating layer 232 in the regions 117a and 117c (see Fig. 10B). In addition, the base insulating layer 231 can be formed by a laminated structure of one or a plurality of films selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film. The insulating layer 232 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, or a hafnium oxide film. It can be formed by a laminated structure by one or a plurality of films selected from inorganic insulators. The insulating layer 234 can be formed using an inorganic insulator film such as the insulating layer 232, or can be formed using an organic material such as polyimide, acrylic resin, or benzocyclobutene resin.
In addition, in the above-mentioned liquid crystal display device, although the structure which has one transistor provided in each pixel was shown, it is also possible to set it as the structure which two or more transistors are provided in each pixel. For example, in the case where two transistors are provided in each pixel in order to solve a problem regarding a viewing angle of a VA (Vertical Alignment) type liquid crystal display device, as the two transistors, a transistor having an oxide semiconductor layer is used. It is possible to apply. Here, the liquid crystal display device can be expressed as a liquid crystal display device having two leak paths through transistors in each pixel. Therefore, in the conventional liquid crystal display device, the area of the capacitor element was enlarged to hold the voltage applied to the liquid crystal element, for example, by forming two capacitor elements in each pixel. That is, the voltage applied to the liquid crystal element was held at the expense of the aperture ratio. On the other hand, in the liquid crystal display device disclosed in this specification, it is possible to eliminate the capacitive element itself by greatly reducing the leakage of the charge through the transistor provided with the oxide semiconductor layer. That is, the liquid crystal display device disclosed in this specification can be said to be a liquid crystal display device which can maintain a high aperture ratio even when a plurality of transistors are provided in each pixel.
(About specific example of manufacturing method of transistor)
Hereinafter, as an example of a transistor provided in each pixel of the liquid crystal display device disclosed herein, a manufacturing process of the channel etch transistor 410, which is one type of bottom gate structure, will be described with reference to FIG. In addition, although the transistor of a single gate structure is shown here, it can be set as the transistor of the multi-gate structure which has multiple channel formation area as needed.
Hereinafter, the process of manufacturing the transistor 410 on the substrate 400 will be described with reference to FIGS. 11A to 11D.
First, after the conductive film is formed on the substrate 400 having the insulating surface, the gate layer 411 is formed by the first photolithography process. In addition, you may form the resist mask used by this process by the inkjet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.
Although there is no big restriction | limiting in the board | substrate which can be used for the board | substrate 400 which has an insulating surface, it is necessary to have heat resistance to the extent which can endure at least the following heat processing. For example, glass substrates, such as barium borosilicate glass and alumino borosilicate glass, can be used. In addition, as a glass substrate, when the temperature of the post-heating process is high, the strain point should use 730 degreeC or more.
You may form the insulating layer used as a base layer between the board | substrate 400 and the gate layer 411. The base layer has a function of preventing diffusion of impurity elements from the substrate 400, and has a layer structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film. It can form by.
The material of the gate layer 411 can be formed in a single layer or laminated by using a metal such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy containing these as a main component. have.
For example, the two-layer laminated structure of the gate layer 411 includes a two-layer structure in which a molybdenum layer is laminated on an aluminum layer, a two-layer structure in which a molybdenum layer is laminated on a copper layer, and a titanium nitride layer or tantalum nitride on a copper layer. It is preferable to set it as the two-layer structure which laminated | stacked the layer, and the two-layer structure which laminated | stacked the titanium nitride layer and molybdenum layer. As a three-layer laminated structure, it is preferable to set it as the three-layer structure which laminated | stacked the tungsten layer or the tungsten nitride layer, the alloy layer of aluminum and silicon, or the alloy layer of aluminum and titanium, and the titanium nitride layer or titanium layer.
Next, a gate insulating layer 402 is formed over the gate layer 411.
The gate insulating layer 402 may be formed by using a plasma CVD method, a sputtering method, or the like as a single layer or a lamination of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. . For example, the silicon oxynitride layer may be formed by plasma CVD using silane (SiH 4 ), oxygen, and nitrogen as the film forming gas. As the gate insulating layer 402, a high-k material such as hafnium oxide (HfOx) or tantalum oxide (TaOx) may be used. The film thickness of the gate insulating layer 402 is 100 nm or more and 500 nm or less, and in the case of lamination, for example, on the first gate insulating layer and the first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less. It is formed by laminating a second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less.
Here, the silicon oxynitride layer is formed as the gate insulating layer 402 by the plasma CVD method.
As the gate insulating layer 402, a silicon oxynitride layer may be formed using a high density plasma apparatus. Here, a high density plasma apparatus refers to the apparatus which can achieve the plasma density of 1x10 <11> / cm <3> or more. For example, a plasma is generated by applying microwave power of 3 kW to 6 kW to form an insulating layer.
Silane (SiH 4 ), nitrous oxide (N 2 O), and rare gas are introduced into the chamber to generate a high-density plasma under a pressure of 10 Pa 30 Pa to form an insulating layer on a substrate having an insulating surface such as glass. Form. Thereafter, the supply of silane (SiH 4 ) may be stopped and plasma treatment may be performed on the surface of the insulating layer by introducing nitrous oxide (N 2 O) and a rare gas without exposing the insulating layer to the atmosphere. The insulating layer which has passed through the above process sequence is an insulating layer which can ensure the reliability of the transistor even if the film thickness is thin.
At the time of forming the gate insulating layer 402, the flow rate ratio of silane (SiH 4 ) and nitrous oxide (N 2 O) introduced into the chamber is in the range of 1:10 to 1: 200. In addition, although helium, argon, krypton, xenon, etc. can be used as a rare gas introduce | transduced into a chamber, it is preferable to use inexpensive argon among these.
In addition, the insulating layer obtained by the high-density plasma apparatus can form a film of a constant thickness, and thus has excellent step coverage. In addition, the insulating layer obtained by the high density plasma apparatus can precisely control the thickness of the thin film.
The insulating layer that has undergone the above-described process procedure is significantly different from the insulating layer obtained by the conventional parallel plate type PCVD apparatus, and when the etching rates are compared using the same etchant, the insulating layer obtained by the parallel plate type PCVD apparatus is used. 10% or more or 20% or more, and the insulating layer obtained by the high density plasma apparatus can be said to be a dense film.
In addition, since the oxide semiconductor (highly purified oxide semiconductor) that is I-formed or substantially I-formed in a later step is very sensitive to the interface level and the interface charge, the interface with the gate insulating layer is important. Therefore, the gate insulating layer in contact with the highly purified oxide semiconductor is required to be of high quality. Therefore, a high-density plasma CVD apparatus using μ waves (2.45 GHz) is preferable because it can form a high quality insulating film with high density and high dielectric breakdown voltage. This is because the high purity oxide semiconductor and the high quality gate insulating layer are in close contact, whereby the interface state density can be reduced and the interface characteristics can be made good. It is important not only that the film quality as the gate insulating layer is good, but also that the density of the interface state with the oxide semiconductor can be reduced and a good interface can be formed.
Next, an oxide semiconductor film 430 having a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 402. In addition, before forming the oxide semiconductor film 430 by the sputtering method, reverse sputtering is performed in which argon gas is introduced to generate plasma, and powdered substances (particles, dust, etc.) adhered to the surface of the gate insulating layer 402. Is preferably removed. Reverse sputtering is a method of modifying a surface by applying a voltage using an RF power supply to a substrate side in an argon atmosphere without applying a voltage to the target side and forming a plasma near the substrate. Instead of the argon atmosphere, nitrogen, helium, oxygen or the like may be used.
The oxide semiconductor film 430 includes In-Ga-Zn-O, In-Sn-O, In-Sn-Zn-O, In-Al-Zn-O and Sn-Ga-Zn-O. , Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn-O, In-O, Sn-O, A Zn-O based oxide semiconductor film is used. Here, the film is formed by the sputtering method using an In—Ga—Zn—O-based metal oxide target as the oxide semiconductor film 430. The cross-sectional view at this stage corresponds to Fig. 11A. The oxide semiconductor film 430 can be formed by sputtering under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas (typically argon) and oxygen. In the case of using the sputtering method, film formation is performed using a target containing 2 wt% or more and 10 wt% or less of SiO 2 , and the oxide semiconductor film 430 contains SiOx (X> 0) that inhibits crystallization. Crystallization at the time of the heat processing for dehydration or dehydrogenation performed at a later process can also be suppressed.
Here, a metal oxide target containing In, Ga, and Zn (In 2 O 3 : Ga 2 O 3 : ZnO = 1: 1: 1 [mol], In: Ga: Zn = 1: 1: 0.5 [atom] ]), The distance between the substrate and the target is 100 mm, pressure is 0.2 Pa, DC power is 0.5 kW, argon and oxygen (argon: oxygen = 30 sccm: 20 sccm, oxygen flow rate 40%) under the atmosphere. We form. In addition, the use of a pulsed direct current (DC) power supply is preferable because the powdery substance generated during film formation can be reduced, and the film thickness distribution is also uniform. The film thickness of the In-Ga-Zn-O-based film is made 2 nm or more and 200 nm or less. Here, an In-Ga-Zn-O-based film having a film thickness of 20 nm is formed by sputtering using an In-Ga-Zn-O-based metal oxide target as the oxide semiconductor film. Further, a metal oxide target containing In, Ga, and Zn has a composition ratio of In: Ga: Zn = 1: 1: 1 [atom] or In: Ga: Zn = 1: 1: 2 [atom]. An oxide target can also be used.
Sputtering methods include an RF sputtering method and a DC sputtering method using a high frequency power source for the sputtering power supply, and there is also a pulsed DC sputtering method for further imparting bias on a pulse basis. The RF sputtering method is mainly used for forming an insulating film, and the DC sputtering method is mainly used for forming a metal film.
There is also a multiple sputtering device capable of providing a plurality of targets having different materials. The multiple sputtering apparatus may form a film by depositing another material film on the same chamber, or may form a film by simultaneously discharging a plurality of kinds of materials from the same chamber.
As the film forming method using the sputtering method, there is also a reactive sputtering method which chemically reacts a target material with a sputtering gas during film formation, and forms a compound thin film thereof, or a bias sputtering method that applies a voltage to a substrate during film formation.
Next, the oxide semiconductor film 430 is processed into an island-shaped oxide semiconductor layer by a second photolithography step. In addition, you may form the resist mask used by this process by the inkjet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.
Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the 1st heat processing which performs dehydration or dehydrogenation is 400 degreeC or more and 750 degrees C or less, Preferably it is 400 degreeC or more and less than the strain point of a board | substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor layer is subjected to a heat treatment for 1 hour at 450 ° C. under a nitrogen atmosphere, and then to prevent re-incorporation of water or hydrogen into the oxide semiconductor layer, The oxide semiconductor layer 431 is obtained by cooling without bringing it into contact with the atmosphere (see Fig. 11B).
In addition, the heat processing apparatus is not limited to an electric furnace, You may be provided with the apparatus which heats a to-be-processed object by heat conduction or heat radiation from a heat generating body, such as a resistance heating body. For example, an RTA (Rapid Thermal Anneal) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus for heating an object to be processed by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is a device that performs a heating process using a high-temperature gas. As the gas, a rare gas such as argon, or an inert gas that does not react with the object by heat treatment, such as nitrogen, is used.
For example, as a 1st heat processing, even if it carries out the board | substrate in the inert gas heated to 650 degreeC-700 degreeC high temperature, and it heats for several minutes, GRTA which carries out the board | substrate and moves out of the inert gas heated to high temperature may be performed. good. GRTA enables high temperature heat treatment in a short time.
In the first heat treatment, it is preferable that nitrogen, or rare gases such as helium, neon, argon, or the like not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen to be introduced into the heat treatment apparatus, or rare gases such as helium, neon, argon, etc. is 6N (99.9999%) or more, preferably 7N (99.99999%) or more, (ie impurity concentration is 1 ppm or less, preferably Is preferably 0.1 ppm or less).
In addition, the 1st heat processing of an oxide semiconductor layer can also be performed with respect to the oxide semiconductor film 430 before processing into an island shape oxide semiconductor layer. In that case, after a 1st heat processing, a board | substrate is taken out from a heating apparatus and a 2nd photolithography process is performed.
In the dehydration or dehydrogenation heat treatment for the oxide semiconductor layer, after the oxide semiconductor layer is formed, a source electrode layer and a drain electrode layer are laminated on the oxide semiconductor layer, and then a protective insulating film is formed on the source electrode layer and the drain electrode layer, and then You may do it any time.
In the case where the opening is formed in the gate insulating layer 402, the step may be performed before or after the dehydration or dehydrogenation treatment is performed on the oxide semiconductor film 430.
In addition, the etching of the oxide semiconductor film 430 here is not limited to wet etching, You may use dry etching.
As an etching gas used for dry etching, a gas containing chlorine (chlorine-based gas such as chlorine (Cl 2 ), boron trichloride (BCl 3 ), silicon tetrachloride (SiCl 4 ), carbon tetrachloride (CCl 4 ), etc.) is preferable. .
In addition, fluorine-containing gases (fluorine-based gases such as carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), trifluoromethane (CHF 3 ), and bromination) Hydrogen (HBr), oxygen (O 2 ), and gases in which rare gases such as helium (He) and argon (Ar) are added to these gases can be used.
As the dry etching method, a parallel plate-type reactive ion etching (RIE) method or an inductively coupled plasma (ICP) etching method can be used. (The amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, and the like) are appropriately controlled so that etching can be performed with a desired processing shape.
As the etchant used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid and nitric acid, and the like can be used. Further, ITO07N (KANTO CHEMICAL CO., INC.) May be used.
Further, the etchant after the wet etching is removed by cleaning together with the etched material. The wastewater of the etching liquid containing the removed material may be purified and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the wastewater after the etching, the resources can be effectively utilized and the cost can be reduced.
Etching conditions (etching liquid, etching time, temperature, etc.) are suitably adjusted according to a material so that it may etch in a desired process shape.
Next, a metal conductive film is formed over the gate insulating layer 402 and the oxide semiconductor layer 431. The metal conductive film may be formed by sputtering or vacuum evaporation. As the material of the metal conductive film, an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), and the above-described elements are used as components. The alloy to mention, or the alloy which combined the above-mentioned element, etc. are mentioned. Further, a material selected from any one or a plurality of manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), and yttrium (Y) may be used. The metal conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a film mainly containing copper or copper, a two layer structure in which a titanium film is laminated on an aluminum film, and a two layer structure in which a copper film is laminated on a tantalum nitride film or a copper nitride film And a three-layer structure in which an aluminum film is laminated on the titanium film and a titanium film is laminated on the aluminum film. Further, in aluminum (Al), elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) are singular or plural. A combined film, alloy film or nitride film may be used.
When heat processing is performed after metal conductive film formation, it is preferable to give a metal conductive film the heat resistance which can endure this heat processing.
A resist mask is formed on the metal conductive film by the third photolithography step, and selectively etched to form the source layer 415a and the drain layer 415b, and then the resist mask is removed (see Fig. 11C). ). In addition, you may form the resist mask used by this process by the inkjet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.
In addition, during the etching of the metal conductive film, the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layer 431 is not removed.
Here, a titanium film is used as the metal conductive film, an In-Ga-Zn-O-based oxide is used for the oxide semiconductor layer 431, and ammonia fruit water (a mixture of ammonia, water, and hydrogen peroxide solution) is used as the etchant. .
In the third photolithography step, the oxide semiconductor layer 431 may be partially etched into an oxide semiconductor layer having grooves (concave portions).
Further, in order to reduce the number of photomasks and the number of processes used in the photolithography process, an etching process may be performed using a resist mask formed by a multi-gradation mask which is an exposure mask having transmitted light having a plurality of intensities. The resist mask formed by using the multi gradation mask becomes a shape having a plurality of film thicknesses, and the shape can be further modified by ashing, so that the resist mask can be used for a plurality of etching steps to be processed in different patterns. Therefore, a resist mask corresponding to at least two or more types of different patterns can be formed by one multi-tone mask. Therefore, the number of exposure masks can be reduced and the corresponding photolithography process can also be reduced, so that the process can be simplified.
Next, plasma treatment using a gas such as nitrous oxide (N 2 O), nitrogen (N 2 ), or argon (Ar) is performed. Adsorbed water and the like adhering to the surface of the oxide semiconductor layer exposed by the plasma treatment are removed. Further, a plasma treatment may be performed using a mixed gas of oxygen and argon.
After the plasma treatment, the oxide insulating layer 416 serving as a protective insulating film in contact with a part of the oxide semiconductor layer is formed without bringing the oxide semiconductor layer into contact with the atmosphere.
The oxide insulating layer 416 can be formed to have a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering, in which impurities such as water and hydrogen are not mixed in the oxide insulating layer 416. When hydrogen is included in the oxide insulating layer 416, the hydrogen penetrates into the oxide semiconductor layer and the back channel of the oxide semiconductor layer 431 becomes low resistance (N-type), so that a parasitic channel may be formed. Therefore, it is important not to use hydrogen in the film formation method so that the oxide insulating layer 416 is a film containing no hydrogen as much as possible.
Here, as the oxide insulating layer 416, a silicon oxide film having a thickness of 200 nm is formed by the sputtering method. The substrate temperature at the time of film formation may be room temperature or more and 300 degrees C or less, and is 100 degreeC here. The film formation by the sputtering method of a silicon oxide film can be performed in a rare gas (typically argon) atmosphere, oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. In addition, a silicon oxide target or a silicon target can be used as the target. For example, using a silicon target, a silicon oxide film can be formed by sputtering under oxygen and a nitrogen atmosphere.
Next, a second heat treatment (preferably between 200 ° C. and 400 ° C., for example, 250 ° C. and 350 ° C. or less) is performed under an inert gas atmosphere or an oxygen gas atmosphere. For example, 2nd heat processing of 250 degreeC and 1 hour is performed in nitrogen atmosphere. When the second heat treatment is performed, part of the oxide semiconductor layer (channel formation region) is heated in contact with the oxide insulating layer 416. As a result, oxygen is supplied to a part of the oxide semiconductor layer (channel formation region). In addition, by this heat treatment, hydrogen can be taken into the oxide insulating layer 416 from the oxide semiconductor layer.
By performing the above process, after heat-processing for dehydration or dehydrogenation is performed with respect to an oxide semiconductor layer, a part (channel formation area) of an oxide semiconductor layer is made into the excess oxygen selectively. As a result, the channel formation region 413 overlapping the gate layer 411 becomes I type, the source region 414a overlapping the source layer 415a, and the drain region 414b overlapping the drain layer 415b. ) Is formed self-aligning. The transistor 410 is formed by the above process.
For example, under conditions of prolonged exposure to high temperature and high field such as the gate bias and thermal stress test (BT test) (for example, 85 ° C., 2 × 10 6 V / cm, 12 hours), impurities (hydrogen And the like) in the oxide semiconductor, the number of bonds between the impurity and the main component of the oxide semiconductor is cut by the strong electric field (B: bias) and the high temperature (T: temperature), and the unbonded water generated is formed at the threshold voltage (Vth). Will cause drift. On the other hand, impurities of the oxide semiconductor, particularly hydrogen and water, are removed as much as possible, thereby forming a high quality insulating film having a high density and high dielectric breakdown voltage by using the above-described high density plasma CVD apparatus, and satisfactorily improving the interface characteristics with the oxide semiconductor. Thus, a stable transistor can be obtained even in a harsh external environment.
Moreover, you may heat-process in 100 degreeC or more and 200 degrees C or less, 1 hour or more and 30 hours or less in air | atmosphere. Here, heat processing is performed at 150 degreeC for 10 hours. This heat treatment may be performed by maintaining a constant heating temperature, and may be repeated a plurality of times of elevated temperature from room temperature to 100 ° C or higher and 200 ° C or lower, and the temperature drop from the heating temperature to room temperature. In addition, this heat treatment may be performed under reduced pressure before the oxide insulating layer 416 is formed. By carrying out the heat treatment under reduced pressure, the heating time can be shortened.
In addition, by forming the drain region 414b in the oxide semiconductor layer overlapping the drain layer 415b, the reliability of the transistor can be improved. Specifically, by forming the drain region 414b, the conductivity can be changed step by step from the drain layer 415b to the drain region 414b and the channel formation region 413.
The source region or the drain region of the oxide semiconductor layer is formed over the entire film thickness direction when the oxide semiconductor layer has a thin film thickness of 15 nm or less, but the oxide semiconductor layer has a film thickness of 30 nm or more and 50 nm or less. In the case where the thickness is thicker, a portion of the oxide semiconductor layer, a region in contact with the source layer or the drain layer, and the vicinity thereof are reduced in resistance to form a source region or a drain region. You may.
A protective insulating layer may be further formed on the oxide insulating layer 416. For example, a silicon nitride film is formed using the RF sputtering method. Since RF sputtering method has good mass productivity, it is preferable as a film forming method of a protective insulating layer. Protective insulating layer is water or a hydrogen ion, or OH -, without including impurities, they are using the inorganic insulating film which blocks the intrusion from the outside, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, and oxide An aluminum nitride film or the like is used. Here, a protective insulating layer 403 is formed as a protective insulating layer using a silicon nitride film (see Fig. 11D).
(For various electronic devices equipped with liquid crystal display device)
Hereinafter, an example of an electronic device equipped with the liquid crystal display device disclosed in this specification will be described with reference to FIG. 12.
Fig. 12A is a diagram showing a notebook personal computer, and is composed of a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, and the like.
FIG. 12B is a diagram showing a portable information terminal PDA. The main body 2211 is provided with a display portion 2213, an external interface 2215, an operation button 2214, and the like. There is also a stylus 2212 as an accessory for operation.
FIG. 12C is a diagram illustrating an electronic book 2220 as an example of an electronic paper. Electronic book 2220 is composed of two housings, housing 2221 and housing 2223. The housing 2221 and the housing 2223 are integrated by the shaft portion 2237, and the opening and closing operation can be performed using the shaft portion 2237 as the shaft. By this structure, the electronic book 2220 can be used like a book of paper.
The display part 2225 is built in the housing 2221, and the display part 2227 is assembled to the housing 2223. The display unit 2225 and the display unit 2227 may be configured to display a continuous screen or may be configured to display another screen. By setting another screen to display, for example, a sentence is displayed on the right display part (display part 2225 in FIG. 12 (C)), and an image is displayed on the left display part (display part 2227 in FIG. 12 (C)). Can be displayed.
12C illustrates an example in which the housing 2221 is provided with an operation unit or the like. For example, the housing 2221 includes a power switch 2231, an operation key 2233, a speaker 2235, and the like. The operation key 2333 can be used to send a page. In addition, it is good also as a structure provided with a keyboard, a pointing device, etc. on the same surface as the display part of a housing. Furthermore, a configuration may be employed in which the external connection terminal (earphone terminal, USB terminal, terminal that can be connected to various cables such as an AC adapter and a USB cable, etc.) and a recording medium insertion portion are provided on the back surface or the side surface of the housing. The electronic book 2220 may be configured to have a function as an electronic dictionary.
The electronic book 2220 may be configured to transmit and receive information wirelessly. It is also possible to wirelessly purchase desired book data or the like from an electronic book server and download the desired book data or the like.
In addition, the electronic paper can be applied to all fields as long as it displays information. For example, the present invention can be applied to advertisements of vehicles such as posters and trains, displays on various cards such as credit cards, as well as electronic books.
Fig. 12D is a diagram showing a mobile phone. This cellular phone is composed of two housings, a housing 2240 and a housing 2241. The housing 2241 includes a display panel 2242, a speaker 2243, a microphone 2244, a pointing device 2246, a camera lens 2247, an external connection terminal 2248, and the like. The housing 2240 includes a solar cell 2249, an external memory slot 2250, and the like that charge the mobile phone. In addition, the antenna is embedded in the housing 2241.
The display panel 2242 has a touch panel function, and a plurality of operation keys 2245 displayed on an image are shown by dotted lines in FIG. 12D. In addition, this mobile phone is equipped with a booster circuit for boosting the voltage output from the solar cell 2249 to a voltage required for each circuit. In addition to the above configuration, a non-contact IC chip, a small recording device, or the like may be incorporated.
In the display panel 2242, the direction of display is appropriately changed depending on the use form. In addition, since the camera lens 2247 is provided on the same surface as the display panel 2242, video calls are possible. The speaker 2243 and the microphone 2244 are not limited to a voice call, but can make a video call, record, play, and the like. In addition, the housing 2240 and the housing 2241 can slide and overlap each other in an unfolded state as shown in FIG.
The external connection terminal 2248 can be connected to various cables such as an AC adapter and a USB cable, and charging and data communication are possible. In addition, by inserting a recording medium into the external memory slot 2250, a larger amount of data can be stored and moved. In addition to the above functions, an infrared communication function, a television receiving function, and the like may be provided.
12E shows a digital camera. This digital camera is composed of a main body 2221, a display portion (A) 2267, an eyepiece portion 2263, an operation switch 2264, a display portion (B) 2265, a battery 2266, and the like.
Fig. 12F is a diagram showing a television device. In this television device 2270, a display portion 2273 is assembled to a housing 2251. By the display unit 2273, it is possible to display an image. In addition, the structure which supported the housing 2251 by the stand 2275 is shown here.
Operation of the television device 2270 can be performed by the operation switch with which the housing 2251 is equipped, and the separate remote control operation device 2280. The operation keys 2279 included in the remote controller 2280 allow the channel and the volume to be operated, and the video displayed on the display unit 2273 can be operated. In addition, it is good also as a structure which forms the display part 2277 which displays the information output from this remote control manipulator 2280 in the remote control manipulator 2280.
In addition, the television device 2270 is preferably configured to include a receiver, a modem, or the like. The receiver can receive a general television broadcast. In addition, by connecting to a communication network by wire or wireless via a modem, it is possible to perform information communication in one direction (sender to receiver) or in two directions (between the sender and the receiver or between the receivers).
This application is based on a Japanese patent application with serial number 2010-042584, which is incorporated herein by reference in its entirety and filed with the Japan Patent Office on February 26, 2010.
100: pixel
101: Scan line
102: Scan line
103: signal line
104: signal line
105: Transistor
107: pixel electrode layer
110: Board
111: Gate layer
112: gate insulating layer
113: oxide semiconductor layer
114a: one side of a source layer and a drain layer
114b: the other of the source layer and the drain layer
115: insulation layer
116 ： Contact hole
117a ： Area
117b ： Area
117c ： Area
201 ： Oxide semiconductor layer
202a: oxide semiconductor layer
202b: oxide semiconductor layer
210: Transistor
211: Insulation layer
212: Insulation layer
220: Transistor
230: Transistor
231 ： Base Cutting Floor
232 ： Insulation layer
233a ： Contact hole
233b ： Contact hole
234 ： Insulation layer
235: Contact hole
400: Board
402: gate insulating layer
403 ： Protective insulation layer
410 ： Transistor
411 ： gate layer
413: channel formation area
414a ： source area
414b: Drain area
415a ： source layer
415b ： Drain layer
416: oxide insulating layer
430: oxide semiconductor film
431: oxide semiconductor layer
800 ： meter
802: Capacitive element
805: Transistor
806 ： Transistor
808 ： Transistor
1000: Pixel
1001 ： Scan line
1002 ： Scan line
1003: Signal line
1004: Signal line
1005 ： Transistor
1006 ： Capacitor
1007: pixel electrode layer
1008 ： Capacitance wiring
1010 ： Board
1011 ： Gate layer
1012 ： Gate insulation layer
1013 ： Semiconductor Layer
1014a: One side of the source layer and the drain layer
1014b: the other of the source layer and the drain layer
1015: Insulation layer
1016 ： Contact hole
1017a ： Area
1017b ： Area
1017c ： Area
2201: The body
2202: Housing
2203: Display part
2204 ： Keyboard
2211: The body
2212: Stylus
2213: Display part
2214: Operation button
2215 ： external interface
2220: Electronic book
2221 ： Housing
2223 ： Housing
2225 ： display
2227 ： display part
2231: Power supply
2233 ： Operation key
2235: Speaker
2237 ： Shaft part
2240 ： Housing
2241 ： Housing
2242 ： Display panel
2243: Speaker
2244 ： Microphone
2245 ： Operation key
2246 ： pointing device
2247: Lens for camera
2248 ： external connection terminal
2249 ： Solar cell
2250: External memory slot
2261: The body
2263: eyepiece
2264: Operation switch
2265: Display part (B)
2266 ： Battery
2267: Display part (A)
2270 ： TV apparatus
2271 ： Housing
2273 ： Display section
2275 ： Stand
2277 ： Display section
2279 ： Operation key
2280: Remote control unit
In the liquid crystal display device,
A first scan line and a second scan line arranged parallel or approximately parallel to each other,
A first signal line and a second signal line arranged parallel or approximately parallel to each other, and
A liquid crystal element surrounded by the first scan line, the second scan line, the first signal line, and the second signal line,
The first signal line intersects the first scan line such that a first step is formed in the first signal line due to the first scan line.
The first signal line intersects the second scan line such that a second step is formed in the first signal line due to the second scan line.
And an entire upper surface of the first signal line is on the same plane or on substantially the same plane in an area interposed between the first step and the second step.
A liquid crystal display device further comprising a transistor having an oxide semiconductor layer.
And the oxide semiconductor layer comprises gallium, zinc, and indium.
And the transistor includes a gate electrically connected to the first scan line.
The transistor comprises a source and a drain,
One of the source and the drain is electrically connected to the first signal line,
And the other of said source and said drain is electrically connected to said liquid crystal element.
A first signal line and a second signal line arranged parallel or approximately parallel to each other,
A liquid crystal element surrounded by the first scan line, the second scan line, the first signal line, and the second signal line, and
A transistor having a gate, an insulating layer, a semiconductor layer, a source and a drain,
The first signal line intersects the second scan line such that a second step is formed in the first signal line due to the second scan line,
And the insulating layer is further sandwiched between the first signal line and the first scan line, and between the first signal line and the second scan line.
And the first signal line is formed on the insulating layer and in contact with the insulating layer.
The insulating layer and the semiconductor layer are further sandwiched between the first signal line and the first scan line, and between the first signal line and the second scan line.
The first signal line is formed on the insulating layer and the semiconductor layer,
And the first signal line is in contact with the semiconductor layer.
And said semiconductor layer comprises an oxide semiconductor.
And the semiconductor layer comprises gallium, zinc, and indium.
In a liquid crystal display device comprising a plurality of pixels,
At least one of the plurality of pixels
scanning line,
Signal Line,
A transistor having a gate, a source, and a drain, the gate being electrically connected to the scan line, one of the source and the drain being electrically connected to the signal line, and
A liquid crystal element electrically connected to the other of said source and said drain,
The signal line intersects the scan line such that a step is formed in the signal line due to the scan line,
The entire upper surface of the signal line is on the same plane or on substantially the same plane in a region between the step and the step located in the neighboring pixel.
The transistor includes an insulating layer in contact with the gate,
And said insulating layer is further sandwiched between said signal line and said scanning line.
And the signal line is formed over the insulating layer and in contact with the insulating layer.
An insulating layer in contact with the gate;
Having a semiconductor layer in contact with the insulating layer,
And said insulating layer and said semiconductor layer are sandwiched between said signal line and said scanning line.
And the signal line is in contact with the semiconductor layer.
And the signal line is in contact with the insulating layer in the region.
The signal line is in contact with the semiconductor layer in a second region where the signal line overlaps the scan line,
And the transistor comprises an oxide semiconductor layer.
And the transistor comprises an oxide semiconductor layer having gallium, zinc, and indium.
KR1020127024493A 2010-02-26 2011-02-02 Liquid crystal display device KR20120120458A (en)
JPJP-P-2010-042584 2010-02-26
JP2010042584 2010-02-26
PCT/JP2011/052676 WO2011105210A1 (en) 2010-02-26 2011-02-02 Liquid crystal display device
KR20120120458A true KR20120120458A (en) 2012-11-01
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