Source: http://www.google.com/patents/US7663486?dq=5,832,511
Timestamp: 2016-08-31 21:57:29
Document Index: 537652983

Matched Legal Cases: ['art 700', 'art 1600', 'art 1600', 'art 6', 'art 6', 'art 6']

Patent US7663486 - RFID tag user memory indication - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA system and method in a radio frequency identification (RFID) tag for writing and erasing user memory. A write command is received at the tag to write data into user memory of the tag. Based on receipt of the write command, a user memory flag in a first memory bank of the tag is set, and the data is...http://www.google.com/patents/US7663486?utm_source=gb-gplus-sharePatent US7663486 - RFID tag user memory indicationAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7663486 B2Publication typeGrantApplication numberUS 11/453,928Publication dateFeb 16, 2010Priority dateJun 16, 2006Fee statusPaidAlso published asEP2030456A2, EP2030456A4, EP2030456B1, US20080001723, WO2007149218A2, WO2007149218A3Publication number11453928, 453928, US 7663486 B2, US 7663486B2, US-B2-7663486, US7663486 B2, US7663486B2InventorsFrederick SchuesslerOriginal AssigneeMotorola, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (9), Non-Patent Citations (28), Referenced by (2), Classifications (10), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetRFID tag user memory indication
US 7663486 B2Abstract
RFID tags typically include a memory device for storing various items of information. In an agreement with the Automotive Industry, EPCglobal provided a definition to a previously undefined bit within the Protocol Control (PC) bits of a Gen 2-type tag memory word. The previously defined bit is bit 15 (hex) of tag memory bank 01 (also known as “EPC memory”). The new definition of this bit indicates whether or not any data is currently stored in tag memory bank 11 (also known as “user memory”). This bit is also referred to as a “user memory flag.” A “1” logic value for this bit indicates that user memory stores data. A “0” logic value for this bit indicates that user memory stores no data. In light of this new bit definition, two write operations will be required to write data into user memory of a tag. These write operations occur over two separate communications between a reader and the tag. A first write is required to write the data into user memory (memory bank 11), and a second write is required to set bit 15 (hex) of EPC memory (memory bank 01). The first and second write operations can occur in either order.
Because two write operations are required to different memory banks, the possibility exists that if the second write operation fails (for example, because the tag moved out of range of the reader), the user memory flag will not correctly indicate the state of user memory. For example, if the user memory flag is set by the first write operation, and the second write operation fails to write data into a previously-empty user memory, then the user memory flag will incorrectly indicate the presence of user data when no valid data is present. Alternatively, if the first write operation is used to write data into a previously-empty user memory, and the second write operation fails to set the user memory flag, then the user memory flag will incorrectly indicate an “empty” user memory, and the data written into user memory by the first write operation will erroneously be ignored by subsequent readers.
Methods, systems, and apparatuses for writing data to user memory in tags, and to erasing user memory in tags, are described.
Charge pump 312 may be present in a passive tag to rectify the radio frequency communication signal of antenna signal 328 to create a voltage level. Furthermore, charge pump 312 increases the created voltage level to a level sufficient to power circuits of IC die 306. Charge pump 312 may also include a regulator to stabilize the voltage of tag power signal 326. Charge pump 312 may be configured in any suitable way known to persons skilled in the relevant art(s). For description of an example charge pump applicable to tag 102, refer to U.S. Pat. No. 6,734,797, titled “Identification Tag Utilizing Charge Pumps for Voltage Supply Generation and Data Recovery,” which is incorporated by reference herein in its entirety. Alternative circuits for generating power in a tag, as would be known to persons skilled in the relevant art(s), may be present. In active tags, a battery device may be present. Further description of charge pump 312 is provided below.
First memory bank 402 may be referred to as “reserved memory” or “memory bank 00.” Memory bank 402 stores kill and access passwords.
Second memory bank 404 may be referred to as “EPC memory” or “memory bank 01.” FIG. 5 shows further detail of memory bank 404 in a Gen 2-type tag. In a first memory portion 502 at memory addresses 00hex to 0Fhex of memory bank 404, a 16 bit cyclic redundancy check (CRC) checksum (“CRC-16”) is stored. In a second memory portion 504 at memory addresses 10hex to 1Fhex of memory bank 404, Protocol-Control (PC) bits are stored. In a third memory portion 506 beginning at 20hex of memory bank 404, a code is stored (such as an electronic product code (EPC)) that identifies the object to which the tag is associated.
Third memory bank 406 may be referred to as “TID memory” or “memory bank 10.” Memory bank 406 stores an 8-bit ISO/IEC 15963 allocation class identifier (111000102 for EPCglobal) at memory locations 00hex to 07hex. Memory bank 406 further includes sufficient identifying information above 07hex for a reader to uniquely identify the custom commands and/or optional features that a tag supports.
Fourth memory bank 408 may be referred to as “user memory” or “memory bank 11.” Memory bank 408 stores user-specific data. The organization of memory bank 408 is user-defined.
Further description of memory banks 402-408 in a Gen 2-type tag can be found in “EPC™ Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID, Protocol for Communications at 860 MHz-960 MHz,” Version 1.0.9, EPCglobal, Inc., copyright 2004, dated Jan. 1, 2005, pages 1-94, which is incorporated by reference herein in its entirety.
With regard to memory bank 404, memory locations 15hex and 16hex of the PC bits were initially reserved for future use (RFU). In an agreement with the Automotive Industry, EPCglobal provided a definition to bit 15hex of memory bank 404, such that the bit indicates whether or not any data is currently stored in fourth memory bank 408. This bit is also referred to as a “user memory flag.” A “1” logic value for this bit indicates that memory bank 408 stores data. A “0” logic value for this bit indicates that memory bank 408 stores no data. In conventional systems, a reader performs two separate write operations (over two separate wireless communications) to write to user memory in a tag. Using a first write command, the reader writes the data to memory bank 408 (user memory). Using a second write command, the reader writes a “1” to memory bank 404, to set bit 15hex (the user memory flag). The write commands can occur in either order. As described above, a failure in either write command may lead to an error with regard to subsequent access of the data in user memory. In a similar manner, a reader performs two separate operations to erase user memory in a tag. A failure in either operation will lead to an error with regard to subsequent access of user memory.
Example Embodiments for Writing Data and Erasing Data in Tag User Memory
Example embodiments are described herein for writing and erasing data in tag user memory. These embodiments can be implemented in a variety of types of tags and readers, and can be implemented in a variety of RFID environments. For example, embodiments may be implemented in 18000-6C (aka Gen 2) tags, whether they contain EPCglobal or AFI data structures. Furthermore, embodiments can be implemented in a commercial or industrial environment, such as in a warehouse, a factory, a business, or store, and in a military or other non-commercial environment.
Flowchart 700 begins with step 702. In step 702, a write command is received at the tag to write data into user memory of the tag. For example, in an embodiment, the tag is tag 600, and the user memory is second memory bank 612 of tag 600. The write command is received by demodulator 602 from a reader, and demodulator 602 outputs demodulated reader signal 616 (containing the write command) to control logic 604. In a Gen 2 environment, the write command may be a Gen 2 “write” or “write block” command, for example, or may be a Gen 2 “custom” command. In alternative types of RFID communication environment, the write command may have other forms.
FIG. 8 shows a RFID communication system 800, according to an embodiment of the present invention. As shown in FIG. 8, a reader 810 includes a write command 802. Write command 802 includes an extension such that write command 802 causes a write to at least portions of two or more tag memory banks simultaneously. This is different from conventional systems, where separate communications are required to provide write commands for different tag memory banks. As shown in FIG. 8, write command 802 includes a “set flag” command 804 and a “write data” command 806, which are transmitted by reader 810 to tag 600 in a single RFID communication signal 808. Thus, in a Gen 2 embodiment, write command 802 may be a “custom” command, configured to provide both operations in a single command.
FIG. 11 shows a RFID communication system 1100, according to an embodiment of the present invention. As shown in FIG. 11, a reader 1110 includes a write command 1102. Write command 1102 is a conventional type of write command, where separate communications are required to provide write commands directed to different tag memory banks. Thus, in a Gen 2 embodiment, write command 1102 may be a “write” or “write block” command. However, tag 600 of system 1100 includes write logic 1104. Write logic 1104 enables data to be written to two (or more) memory banks of tag 600 upon receipt of a single write command 1102. As shown in FIG. 11, write command 1102 is transmitted from reader 1110 to tag 600 in RFID communication signal 1108.
In an embodiment, user memory flag logic 1202 decodes write command 1102 to determine if a write to user memory is requested. For example, in a Gen 2-type tag embodiment, user memory flag logic 1202 may determine whether write command 1102 includes a write to a “11” memory bank, which is user memory. If write command 1102 includes a write to user memory, user memory flag logic 1202 determines that user memory flag 614 should be set. In such situation, user memory flag logic 1202 causes user memory flag 614 to be set in first memory bank 610.
Flowchart 1600 begins with step 1602. In step 1602, a command to erase data stored in the user memory of the tag is received at the tag. For example, in an embodiment, the user memory is second memory bank 612 of tag 600. An erase command is received by demodulator 602 from a reader, and demodulator 602 outputs demodulated reader signal 616 (containing the erase command) to control logic 604. In a Gen 2 environment, the erase command may be a Gen 2 “erase block” command, for example. In alternative types of RFID communication environment, the erase command may have other forms.
In step 1604, the user memory flag in the first memory bank is cleared. For example, in an embodiment, user memory flag 614 is cleared (e.g., set to “0”) in first memory bank 610. In one embodiment, only the bit (or bits) of user memory flag 614 is cleared. In another embodiment, additional bits, or the entire contents of first memory bank 610 are overwritten (e.g., by appropriate data received in the write command from the reader, and/or by data generated by control logic 604) when user memory flag 614 is cleared.
In step 1606, data stored in the second memory bank is erased. For example, in an embodiment, locations in second memory bank 612 specified in the received erase command are erased (e.g., replaced with “0” data values).
As shown in FIG. 18, erase command 1802 includes a “clear flag” command 1804 and an “erase data” command 1806, which are transmitted by reader 1810 to tag 600 in a single RFID communication signal 1808. In a Gen 2 embodiment, erase command 1802 may be a “custom” command. Similarly to the configuration shown in FIG. 9 for handling write command 802, tag 600 may be configured to handle erase command 1802. For example, control logic 604 can be configured to process erase command 1802 to perform both of steps 1604 and 1606 of flowchart 1600. Based on clear flag command 1804, control logic 604 performs a clear of user memory flag 614. Based on erase data command 1806, control logic 604 performs an erase of memory locations in second memory bank 612. The clear and erase operations can occur in either order or in an overlapping fashion.
As shown in FIG. 19, reader 1910 includes an erase command 1902. Erase command 1902 is a conventional type of erase command, where separate communications are required to erase memory locations in different tag memory banks. Thus, in a Gen 2 embodiment, erase command 1902 may be an “erase block” command, for example. However, tag 600 of system 1900 includes erase logic 1904. Erase logic 1904 enables two (or more) memory banks of tag 600 to be interacted with upon receipt of a single erase command 1902. As shown in FIG. 19, erase command 1902 is transmitted from reader 1910 to tag 600 in RFID communication signal 1906.
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Schuessler, UHF Air Interface Work Group Minutes, Jun. 12, 2006, pp. 1-5.27Search Report and Written Opinion for International Application No. PCT/US07/13271 mailed Mar. 13, 2008, 11 pages.28Stephen F. Roth, Letter to Morris Brown re: Harmonization of Tire RFID Standards, Feb. 1, 2006, p. 1.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8547232May 28, 2010Oct 1, 2013Nokia CorporationMethod and apparatus for transferring data via radio frequency (RF) memory tagsUS20110148598 *Jun 23, 2011Hynix Semiconductor Inc.Rfid system* Cited by examinerClassifications U.S. Classification340/572.1, 340/10.51, 340/10.52, 711/100International ClassificationG08B13/14Cooperative ClassificationG06F11/1004, H04W88/02, G06K19/0723European ClassificationG06F11/10A, G06K19/07TLegal EventsDateCodeEventDescriptionJun 16, 2006ASAssignmentOwner name: SYMBOL TECHNOLOGIES, INC., NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SCHUESSLER, FREDERICK;REEL/FRAME:018004/0452Effective date: 20060616Owner name: SYMBOL TECHNOLOGIES, INC.,NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SCHUESSLER, FREDERICK;REEL/FRAME:018004/0452Effective date: 20060616Nov 15, 2011CCCertificate of correctionMar 18, 2013FPAYFee paymentYear of fee payment: 4Oct 31, 2014ASAssignmentOwner name: MORGAN STANLEY SENIOR FUNDING, INC. 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