Source: http://www.google.com/patents/US4882712?dq=3657699
Timestamp: 2014-07-31 08:34:10
Document Index: 499781076

Matched Legal Cases: ['art 13', 'art 14', 'art 15', 'art 16', 'art 17', 'art 13', 'art 14', 'art 15', 'art 13', 'art 15', 'art 13', 'art 15']

Patent US4882712 - Synchronous semiconductor memory device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA synchronous semiconductor memory device has a noise preventing part for preventing a noise from being transmitted to a memory cell array, where the noise is caused by a change in a write data....http://www.google.com/patents/US4882712?utm_source=gb-gplus-sharePatent US4882712 - Synchronous semiconductor memory deviceAdvanced Patent SearchPublication numberUS4882712 APublication typeGrantApplication numberUS 07/249,058Publication dateNov 21, 1989Filing dateSep 26, 1988Priority dateSep 29, 1987Fee statusLapsedAlso published asDE3883132D1, DE3883132T2, EP0310496A2, EP0310496A3, EP0310496B1Publication number07249058, 249058, US 4882712 A, US 4882712A, US-A-4882712, US4882712 A, US4882712AInventorsChikai Ohno, Michiyuki HirataOriginal AssigneeFujitsu Limited, Fujitsu Vlsi LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (1), Referenced by (85), Classifications (13), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetSynchronous semiconductor memory deviceUS 4882712 AAbstract A synchronous semiconductor memory device has a noise preventing part for preventing a noise from being transmitted to a memory cell array, where the noise is caused by a change in a write data.
What is claimed is: 1. A synchronous semiconductor memory device comprising:first latch means for latching a write command in synchronism with a clock signal; second latch means for latching a write data in synchronism with the clock signal and for outputting two write process signals based on the write data latched thereby; pulse generating means for generating an internal write pulse signal based on the write command latched by said first latch means, said internal write pulse signal having a first logic level only in a write mode of the synchronous semiconductor memory device; write control means supplied with said internal write pulse signal and said write process signals for controlling write and read operations of the synchronous semiconductor memory device; memory means for storing the write data latched by said second latch means; and noise preventing means coupled to said second latch means and said write control means for supplying said write process signals to said write control means only in the write mode responsive to said internal write pulse signal and for setting said write process signals to fixed potentials during a time other than the write mode. 2. A synchronous semiconductor memory device as claimed in claim 1 in which said write control means supplies the write data latched by said second latch means to said memory means in the write mode and cuts off the supply of the write data to said memory means in a read mode of the synchronous semiconductor memory device so as to apply a constant read potential to said memory means.
BACKGROUND OF THE INVENTION The present invention generally relates to semiconductor memory devices, and more particularly to a synchronous semiconductor memory device such as a synchronous random access memory having latch circuits for receiving a write data and a write command.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an example of a conventional asynchronous RAM;
DETAILED DESCRIPTION FIG. 5 shows an embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device generally has first and second latch circuits 11 and 12, a write control part 13, a memory part 14, a noise preventing part 15, a clock gate part 16, a clock generating part 17, and a write pulse generating circuit 21. The first latch circuit 11 latches a write command WE, and the second latch circuit 12 latches a write data DIN. The write control part 13 controls the write and read operations of the semiconductor memory device, and the memory part 14 stores the write data DIN latched by the second latch circuit 12. The noise preventing part 15 is coupled between the second latch circuit 12 and the write control part 13, and the noise preventing part 15 supplies to the write control part 13 the latched write data DIN as write process signals Sa and Sb only in a write mode responsive to an internal write pulse signal SC2 which is formed by the write pulse generating circuit 21 based on a clock signal CLK and the write command WE. The noise preventing part 15 otherwise sets the write process signals Sa and Sb to fixed potentials.
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command/address signals in response to both edges of a clock signalUS8761235Jun 10, 2013Jun 24, 2014Massachusetts Institute Of TechnologyDigital transmitter* Cited by examinerClassifications U.S. Classification365/206, 365/189.05, 365/230.01International ClassificationG11C11/414, G06F12/16, G11C7/00, G11C11/409, G11C7/02, G11C7/22Cooperative ClassificationG11C7/22, G11C7/00European ClassificationG11C7/00, G11C7/22Legal EventsDateCodeEventDescriptionFeb 3, 1998FPExpired due to failure to pay maintenance feeEffective date: 19971126Nov 23, 1997LAPSLapse for failure to pay maintenance feesJul 1, 1997REMIMaintenance fee reminder mailedMay 4, 1993FPAYFee paymentYear of fee payment: 4Sep 26, 1988ASAssignmentOwner name: FUJITSU LIMITED, 1015, KAMIKODANAKA, NAKAHARA-KU,Owner name: FUJITSU VLSI LIMITED, 1884-2, KOZOJI-CHO 2-CHOME,Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:OHNO, CHIKAI;HIRATA, MICHIYUKI;REEL/FRAME:004957/0159Effective date: 19880916Owner name: FUJITSU LIMITED,JAPANOwner name: FUJITSU VLSI LIMITED,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OHNO, CHIKAI;HIRATA, MICHIYUKI;REEL/FRAME:4957/159Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OHNO, CHIKAI;HIRATA, MICHIYUKI;REEL/FRAME:004957/0159RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google