Source: http://www.google.com/patents/US20010022739?dq=7,603,356
Timestamp: 2015-01-28 19:27:36
Document Index: 296657282

Matched Legal Cases: ['art 104', 'art 104', 'art 104', 'art 104', 'art 104', 'art 104', 'art 104', 'art 104', 'art 104', 'art 104', 'art 104', 'art 104', 'art 104']

Patent US20010022739 - Memory system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA memory system comprises a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings and module power...http://www.google.com/patents/US20010022739?utm_source=gb-gplus-sharePatent US20010022739 - Memory systemAdvanced Patent SearchPublication numberUS20010022739 A1Publication typeApplicationApplication numberUS 09/802,842Publication dateSep 20, 2001Filing dateMar 12, 2001Priority dateMar 10, 2000Also published asUS6411539, US6519173, US20020159284Publication number09802842, 802842, US 2001/0022739 A1, US 2001/022739 A1, US 20010022739 A1, US 20010022739A1, US 2001022739 A1, US 2001022739A1, US-A1-20010022739, US-A1-2001022739, US2001/0022739A1, US2001/022739A1, US20010022739 A1, US20010022739A1, US2001022739 A1, US2001022739A1InventorsSeiji Funaba, Yoji NishioOriginal AssigneeSeiji Funaba, Yoji NishioExport CitationBiBTeX, EndNote, RefManReferenced by (8), Classifications (14), Legal Events (9) External Links: USPTO, USPTO Assignment, EspacenetMemory systemUS 20010022739 A1Abstract A memory system comprises a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings and module power wirings respectively. The module data wirings of each memory module are connected in series form through series paths lying within the connectors. Each individual module data wirings do not constitute branch wirings to system data wirings on the system board. Thus, such signal reflection as caused by branching from the data wirings on the system board is not developed. Since the power is supplied in parallel from the system board through parallel paths lying within the connectors, the supply of the power is stabilized. Images(36) Claims(15)
BACKGROUND OF THE INVENTION [0001] The present invention relates to a technology for controlling the reflection of a transmission signal, which is caused by branching of wirings in a memory system using memory modules, etc., and to a technology effective for application to a high-speed access-compatible memory system. [0002] SSTL (Stub Series Terminated Transceiver Logic) has been known as a small-amplitude interface intended for a memory system. The SSTL has been described in, for example, English Paper Journal, VOL. E82-C, NO. 3, Yasuhiro KONISHI, et al., �Interface Technologies for Memories and ASICs-Review and Future Direction�, issued by the Institute of Electronics, Information and Communication Engineers, March 1999. [0003] An SSTL-based memory system principally comprises a memory controller, signal wirings, connectors and memory modules mounted on a motherboard. The memory modules respectively have m memory chips provided on both surfaces of a module substrate. Data terminals of each individual memory chips are connected to their corresponding module data terminals in m units. Access control data terminals such as address terminals of the memory chips are connected to their corresponding module access control terminals. One-sided ends of the signal wirings are connected to their corresponding signal terminals of the memory controller, and the other ends thereof are terminated into a predetermined voltage. A plurality of memory modules are connected in parallel with their corresponding signal wirings through the connectors. Assuming now that the number of data terminals of each memory chip is defined as n and the number of the memory chips placed on the one side of each memory module is defined as m, the present memory system has m�n data signal wirings. The m memory chips placed on the one side of one memory module of plural memory modules are selected for one access according to a chip select signal generated by the memory controller. The ends or terminals of the signal wirings are connected to a terminal voltage through terminal resistors. Stub resistors for the memory controller are respectively series-connected to signal wirings for connecting the memory controller and the connectors. [0004] Here, module wirings for connecting the module terminals of each memory module and the terminals of each memory chip constitute wirings which branch off from the signal wirings of the motherboard through the connectors. Stub resistors are placed in these module wirings. These stub resistors serve as matching loads for relaxing signal reflection developed in the signal wirings. Mismatching is generally developed in characteristic impedance at each wiring branch point. It is thus necessary to provide the stub resistors for relaxing the mismatching. Assuming that the characteristic impedance of each wiring is defined as ZO and the characteristic impedance of each stub wiring is defined as ZsO, Zs-ZO/2 is suitable as the resistance value of each stub resistor. There is however the possibility that when the resistance value of the stub resistor increases, a voltage drop developed across the resistor will become great, thereby attenuating signal voltages such as addresses, data or the like and hence causing an error in a memory operation. When the resistance value of the stub resistor is less reduced to avoid the attenuation of each signal voltage for this season, there is the possibility that signal reflection will become obvious in reverse and hence a signal waveform will disturb, thereby causing a malfunction in the same manner as described above. As the operation is made fast to increase a signal frequency and each branch wiring against which countermeasures are to be taken by each stub resistor, becomes long, the disturbance of a signal waveform at a receiving end becomes great. [0005] On the other hand, the present inventors have discussed, as another memory system, a type wherein a plurality of memory modules are series-connected via connectors to their corresponding signal wirings connected to a memory controller on a motherboard. The present inventors have discussed a configuration wherein on a memory module, a plurality of memory chips are connected by one-stroke writable wiring paths through module data signal wirings. Assuming that the number of data signal terminals of each memory element is defined as n in the present memory system, n module data signal wirings are provided therein regardless of the number m of memory elements placed on one side of each memory module, and one memory chip of the plural memory chips is selected for one access. [0006] In another memory system referred above, all the memory modules are series-connected to their corresponding signal wirings on the motherboard, and the module signal wirings lying within the memory modules are series-connected to all the memory chips arranged in a line and are laid along the longitudinal direction of each memory module. Thus, the memory modules little form the branch wirings with respect to the signal wirings on the motherboard as in the case of the SSTL. A problem decreases that the disturbance of each waveform due to undesired signal reflection caused by the branch wirings occurs. [0007] However, the present inventors have revealed that the length of the signal wiring increases, and the time necessary for the signal to propagate from the memory controller to the corresponding memory chip at the farthest end thereof becomes long, thus increasing a delay in access time. [0008] Thus, a problem arises in that the module wirings of each memory module constitute the branch wirings on the memory system in the case of the SSTL type, whereby the malfunction due to the signal reflection caused thereby occurs and the speeding up of the memory operation is limited. Since such branching for the signal wiring as developed in the SSTL little exists in the memory system of such a type that the plurality of memory modules are connected in series and the memory chips lying within the memory modules are connected in series, the branch wiring-based problem decreases. However, the present inventors have revealed the possibility that an increase in the length of the signal wiring lying within each memory module will cause a delay in access time and cannot cope with higher-speed access. [0009] After the completion of the invention of the present application, the inventors of the present application have recognized the following examples known to date. Japanese Patent Application Laid-Open Nos. Hei 5(1993)-234355 and 6(1994)-150085 respectively have disclosed the invention wherein connectors are provided at both long-side portions of each memory module so that the plural memory modules can be connected in tandem. However, they do not disclose a wiring structure provided inside each memory module. Further, the present inventors have revealed that when the power, a clock signal, etc. are serially supplied, the supply thereof becomes instable. Japanese Patent Application Laid-Open No. Hei 7(1995)-334415 discloses a memory module having extended connectors which allow cascade connections of extended memory modules. Japanese Patent Application Laid-Open No. Hei 7(1995)-261892 discloses the invention wherein each of memory modules is provided with inlet connectors and outlet connectors, a memory bus on the memory module connects between them, and memory elements are connected in series with the memory bus, whereby undesired signal reflection is controlled. However, the first through third known examples merely provide the technology of cascade-connecting the memory modules to thereby configure the memory system. The fourth known example merely shows the system for connecting the plural memory elements to their corresponding memory bus on each memory module in series form. Any of the examples does not provide the conception leading to the invention of the present application. SUMMARY OF THE INVENTION [0010] The present invention aims to provide a memory system capable of controlling the disturbance of a signal waveform due to signal reflection to improve the reliability of signal transmission, increasing the stability of a memory operation, and restraining an increase in access time. [0011] Further, the present invention aims to increase the speed for processing data by a computer system using a memory system. [0012] The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. [0013] Summaries of typical ones of the inventions disclosed in the present application will be explained in brief as follows: [0014] 1. A memory system includes a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to first and second module wirings. The memory connectors respectively have series paths (133, 134, 135) for serially connecting the first module wirings for a plurality of the mounted memory modules between the memory modules, and parallel paths (137, 138, 139) which are connected in parallel with the second module wirings for the plurality of mounted memory modules. The system board has first system wirings (107) connected to the series paths and second system wirings (108) each commonly connected to the parallel paths. [0015] The first module wirings and the series paths constitute, for example, a form connected in series with the first system wirings to thereby constitute a memory access data bus connected to the controller, and the parallel paths constitute branch power wirings with respect to the second system wirings for supplying power. [0016] As another aspect, the first module wirings and the series paths constitute, for example, a form connected in series with the first system wirings to thereby constitute clock wirings connected to the controller. [0017] As a further aspect, the first module wirings and the series paths constitute a form connected in series with the first system wirings to thereby constitute command/address wirings connected to the controller. [0018] The first module wirings (module data wirings) on each memory module constitute the memory access data bus in the memory system. Therefore, in a memory system in which a plurality of memory modules are made parallel, module data wirings for each memory module are connected in series form, and each individual module data wirings do not constitute branch wirings to first system wirings on a system board of the memory system. Thus, such signal reflection as caused by branching from a data bus like the first system wirings on the system board is not developed. Since the power or the like is supplied in parallel from the system board to each memory module through parallel paths, the supply of the power is stabilized. There is a possibility that when the power is supplied to the memory modules on a serial basis, for example, one memory module will produce power noise in the course thereof, thus causing its influence to propagate toward a subsequent stage. The above means do not produce such possibility, and hence a high degree of reliability can be ensured for a memory operation. [0019] 2. A memory system as viewed from a further specific standpoint has a controller capable of controlling a memory, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules includes a plurality of memory chips having chip data terminals, a plurality of module data wirings individually provided in association with the respective chip data terminals of the plurality of memory chips, and module power wirings. The memory connectors respectively have series paths for serially connecting the module data wirings of a plurality of the mounted memory modules between the memory modules, and parallel paths which are connected in parallel with the module power wirings of the plurality of mounted memory modules. The system board has system data wirings connected to the series paths, and system power wirings each commonly connected to the parallel paths. The series paths constitute a memory access data bus together with the module data wirings of the memory modules mounted in the memory connectors, and the system data wirings. The parallel paths constitute power wirings together with the module power wirings of the memory modules mounted in the memory connectors, and the system power wirings. [0020] Even according to the above means in a manner similar to the above, such signal reflection as caused by branching to a data bus on a motherboard of a memory system is not developed. Further, since the power or the like is supplied in parallel from the system board to each memory module through the parallel paths, the supply of the power is stabilized. In the memory system in addition to the above, parallel access for the number of bits corresponding to the width of the memory access data bus is assured for the memory module. Thus, the disturbance of each signal waveform due to the signal reflection is restrained while an increase in access time is being controlled, thereby making it possible to increase the reliability of signal transmission. [0021] 3. A memory system as viewed from a still further standpoint includes a controller capable of controlling the operation of each memory, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings. The memory connectors respectively have series paths for serially connecting the module data wirings of the plurality of mounted memory modules between the memory modules. Further, the system board has system data wirings having one ends connected to the series paths, the other ends connected to terminal resistors, and intermediate portions connected to data terminals of the controller. [0022] According to the above means in particular, since the data terminals of the controller are directly connected to their corresponding system data wirings, undesired branching from the system data wirings to the controller does not exist either in substance, and undesired signal reflection does not occur even in such portions. [0023] If it is desired to positively manifest the fact that no undesired branching occurs in points where the system data wirings and the data terminals of the controller are connected, then their connecting points can be defined as having been included in one-stroke writable wiring paths. Alternatively, even if the branching is developed, no problem occurs if a wiring path length of each branching portion is set short in such a manner that the time necessary for a signal to ensure or assure a normal operation to go to and from a wiring path of the branching portion becomes shorter than a state transition time of the signal. [0024] The terminal resistors may be separated from the system data wirings in response to a writing operation of each memory chip by the controller. Since terminal resistors on the memory controller side are supposed to be subjected to signal reflection read from a memory chip, low power consumption and an increase in signal amplitude can be achieved if the terminal resistors may be separated from the system data wirings in response to the writing operation of the memory chip. [0025] 4. In the type of an output circuit and terminal resistors, a memory system includes a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips having chip data terminals respectively connected to module data wirings. The memory connectors respectively have series paths for serially connecting the module data wirings of the plurality of mounted memory modules between the memory modules. The system board has system data wirings connected to one ends of the series paths and connected to data terminals of the controller respectively. When, at this time, the memory chip has an open drain output circuit coupled to the chip data terminals, terminal resistors may be connected to the other ends of the series paths respectively without providing the system data wirings with their corresponding terminal resistors. When the controller has the open drain output circuit coupled to the data terminals thereof in reverse, the terminal resistors may be connected to the system data wirings respectively without providing the other ends of the series paths with the terminal resistors. [0026] Since the open drain output circuit is high in output impedance and kept substantially constant in output impedance at its output operation, each terminal portion for allowing a signal outputted from the open drain output circuit to propagate is hard to be affected by undesired voltage reflection even if no terminal resistors are provided. It is thus possible to achieve low power consumption and an increase in signal amplitude. [0027] 5. The memory system is particularly effective for application to, for example, a personal computer, a work station, or a data processing system requiring a large capacity memory, like a server. At this time, a data processor connected to the controller of the memory system and capable of obtaining access to each memory chip of the memory system is provided to configure a data processing system. Even when the frequency of the memory system is rendered high, a signal waveform is hard to get out of order owing to the above, and high-speed transmission is also allowed, thus contributing to an increase in the speed for processing data by a computer system. [0028] 6. Terminal resistors are incorporated into the controller so as to be connectable to their corresponding system data terminals, and the electrical connections thereof to the system data wirings may be controlled according to an access mode or the like to each memory chip.
BRIEF DESCRIPTION OF THE DRAWINGS [0029] While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which: [0030]FIG. 1 is a front view showing one example of a memory system according to the present invention; [0031]FIG. 2 is a plan view illustrating the memory system shown in FIG. 1; [0032]FIG. 3 is a schematic equivalent circuit diagram of the memory system shown in FIG. 2; [0033]FIG. 4 is a plan view showing a first memory module applied to the memory system shown in FIG. 1; [0034]FIG. 5 is a side view illustrating the first memory module shown in FIG. 4; [0035]FIG. 6 is an explanatory view showing an example of a wiring arrangement related to a memory chip employed in the memory module shown in FIG. 4; [0036]FIG. 7 is a schematic vertical cross-sectional view illustrating data wiring portions of connectors applicable to the memory module shown in FIG. 1; [0037]FIG. 8 is a schematic vertical cross-sectional view depicting power wiring portions of the connectors applicable to the memory module shown in FIG. 4; [0038]FIG. 9 is a perspective view showing the manner in which the memory module is mounted in the connectors applicable to the memory module shown in FIG. 4; [0039]FIG. 10 is a cross-sectional view showing a state in which the memory modules have been fitted in the connectors each applicable to the memory module shown in FIG. 4; [0040]FIG. 11 is a perspective view showing a memory system related to a comparative example having an SSTL interface; [0041]FIG. 12 is an equivalent circuit diagram illustrating the memory system related to the comparative example shown in FIG. 11; [0042]FIG. 13 is a perspective view depicting a memory system related to a comparative example in which memory modules having memory chips connected in serial form are connected in series; [0043]FIG. 14 is an equivalent circuit diagram showing the memory system related to the comparative example shown in FIG. 13; [0044]FIG. 15 is a simulation circuit diagram of SSTL employed in the memory system configured in the form of FIG. 11; [0045]FIGS. 16A and 16B are respectively explanatory views showing simulation results of SSTL signal waveforms at write and read operations of the simulation circuit shown in FIG. 15; [0046]FIG. 17 is a simulation circuit diagram related to data signals employed in the memory system described in FIG. 2; [0047]FIGS. 18A and 18B are respectively explanatory views illustrating simulation results at write and read operations of the simulation circuit shown in FIG. 17; [0048]FIG. 19 is an equivalent circuit diagram showing a data signal wiring system employed in a second memory system according to the present invention; [0049]FIG. 20 is an equivalent circuit diagram illustrating a data signal wiring system employed in a third memory system according to the present invention; [0050]FIG. 21 is an equivalent circuit diagram depicting a data signal wiring system employed in a fourth memory system according to the present invention; [0051]FIG. 22 is an equivalent circuit diagram related to a command/address signal wiring system employed in the fourth memory system; [0052]FIG. 23 is an equivalent circuit diagram showing a data signal wiring system employed in a fifth memory system according to the present invention; [0053]FIG. 24 is a circuit diagram illustrating a memory controller most suitable for the first memory system according to the present invention; [0054]FIG. 25 is a circuit diagram showing a memory controller most suitable for the second memory system according to the present invention; [0055]FIG. 26 is a circuit diagram depicting a memory controller most suitable for the third memory system according to the present invention; [0056]FIG. 27 is another circuit diagram showing a memory controller most suitable for the third memory system according to the present invention; [0057]FIG. 28 is a circuit diagram illustrating a memory controller most suitable for the fifth memory system according to the present invention; [0058]FIGS. 29A, 29B and 29C are respectively cross-sectional views related to a second memory module; [0059]FIGS. 30A and 30B are respectively explanatory views showing a connector applicable to the second memory module; [0060]FIGS. 31A and 31B are respectively cross-sectional views showing a memory system equipped with the second memory modules; [0061]FIG. 32 is a plan view illustrating a third memory module according to the present invention; [0062]FIGS. 33A and 33B are respectively cross-sectional views illustrating, as examples, forms in which the third memory modules are connected to one another by connectors; [0063]FIG. 34 is a plan view depicting a dummy memory module available together with the first memory module; [0064]FIG. 35 is a side view showing the dummy memory module shown in FIG. 34; [0065]FIGS. 36A, 36B and 36C are respectively explanatory views illustrating a dummy memory module available together with the second memory module; [0066]FIG. 37 is a plan view showing a dummy memory module available together with the third memory module; [0067]FIGS. 38A and 38B are respectively explanatory views illustrating a terminating memory module in which the first memory module is equipped with terminal resistors; [0068]FIG. 39 is an explanatory view depicting a terminating dummy memory module which corresponds to the dummy memory module shown in FIG. 34; [0069]FIGS. 40A, 40B and 40C are respectively explanatory views showing a terminating memory module in which the memory module shown in FIG. 29A is equipped with terminal resistors; [0070]FIG. 41 is an explanatory view illustrating a terminating memory module in which the memory module shown in FIG. 32 is equipped with terminal resistors; [0071]FIG. 42 is a cross-sectional view showing other forms related to the connectors shown in FIGS. 7 and 8 with attention to a data signal wiring portion; [0072]FIG. 43 is a cross-sectional view illustrating other forms related to the connectors shown in FIGS. 7 and 8 with attention to a power wiring portion; [0073]FIG. 44 is a cross-sectional view illustrating a memory module partly provided with connector functions; [0074]FIG. 45 is a cross-sectional view showing connectors corresponding to other forms applicable to a memory module with attention to a data signal wiring portion; [0075]FIG. 46 is a cross-sectional view illustrating connectors corresponding to further forms applicable to a memory module with attention to a data signal wiring portion; [0076]FIG. 47 is a cross-sectional view showing the connectors shown in FIG. 46 with attention to a power wiring portion; [0077]FIG. 48 is a cross-sectional view depicting a state in which memory modules are respectively mounted in the connectors shown in FIGS. 46 and 47; [0078]FIGS. 49A and 49B are respectively perspective views showing a further embodiment of a memory module provided with a module terminal pair extending in a downward direction; [0079]FIG. 50 is a cross-sectional view showing one example of a memory system equipped with the memory modules each shown in FIG. 49; [0080]FIG. 51 is a front view showing an example in which the memory system shown in FIG. 1 is formed on one substrate without using connectors and memory modules; [0081]FIG. 52 is a front view illustrating an example in which memory systems are formed on both surfaces of the same substrate; [0082]FIG. 53 is a plan view depicting an example in which a CPU is mounted together with a memory system to thereby provide multi-chip module form; and [0083]FIG. 54 is a block diagram showing a personal computer system using a memory system.
DETAILED DESCRIPTION OF THE INVENTION [0084] Preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings. [0085] First memory system [0086]FIG. 1 is a plan view showing a memory system according to the present invention, and FIG. 2 is a front view showing the memory system, respectively. [0087] Although not restricted in particular, the memory system shown in the same drawings has includes a memory controller 102, connectors 104A and 104B, terminal resistors 105 and 106, signal wirings 107, power wirings 108, and terminal voltage power wirings 109 provided on a motherboard 101. The memory system is configured in such a manner that, for example, the memory modules 1 are fitted in their corresponding connectors 104A and 104B. [0088] The signal wirings 107 comprise data signal wirings 112, address/command signal wirings 113 and a clock signal wiring 117 illustrated in FIG. 2 by way of example. [0089] As shown in FIG. 2, memory address/command input terminals of memory chips 11 placed on the same surface of one memory module 1, and address/command signal output terminals of an address/command buffer chip 12 are respectively connected to one another by module address/command distribution wirings 19. The memory chip 11 on the memory module 1 receives address/command signals from the address/command buffer chip 12 through the module address/command distribution wirings 19. Further, clock input terminals of the memory chips 11 placed on the same surface of one memory module 1, a clock input terminal of the address/command buffer chip 12, and a clock output terminal of a PLL chip 13 are respectively connected to one another by a clock distribution wiring 20. Each memory chip 11 and the address/command buffer chip 12 receive a clock signal from the PLL chip 13 through the clock distribution wiring 20. [0090] As shown in FIG. 2, memory data terminals of each memory chip 11 placed on the same surface of one memory module are connected to their corresponding module data wirings 15 formed in the memory module 1. Further, command/address input terminals of the address/command buffer chip 12 are connected to their corresponding module command/address wirings 16 formed in the memory module 1. A clock input terminal of the PLL chip 13 is connected to its corresponding clock wiring 17 formed in the memory module 1. [0091] As shown in FIG. 1 by way of example, a plurality of memory modules 1 are placed on the motherboard 101 in parallel and connected to one another in serial form by the right and left connectors 104A and 104B. [0092] Referring to FIG. 1, the connectors 104A and 104B respectively have in-connector wirings 135 and 133 for respectively connecting module data wirings 15 (module command/address wrings 16 and module clock wiring 17) of a plurality of mounted memory modules 1 in series between the memory modules 1. The in-connector wirings 135 and 133 constitute series routes or paths for connecting the module data wirings 15 (module command/address wirings 16 and module clock wiring 17) in serial form. Although not illustrated in FIGS. 1 and 2, module power wirings used as several types of relatively wide power patterns are formed on a module substrate. The module power wirings are connected to their corresponding in-connector power wirings 137, 138 and 139 in parallel and constitute parallel paths. [0093] As shown in FIG. 2 by way of example, the connectors 104A and 104B respectively include the power wirings 108 for supplying power from the motherboard 101 to the memory modules 1, and the signal wirings 107 (112, 113 and 117) for connecting between signal terminals of the adjacent memory modules. The signal wirings 107 constitute first system wirings connected to the series paths, and the power wirings 108 constitute second system wirings commonly connected to the parallel paths, respectively. The signal wirings 107 on the motherboard pass under the memory controller 102 and are conductive to within the plural memory modules 11 and the connectors 104A and 104B. Further, the signal wirings 107 are terminated into a predetermined voltage VTT at the terminal voltage power wirings 109 through the terminal resistors 105 and 106 at both ends thereof or at at least one-sided end thereof. [0094] As shown in FIG. 2, signal terminals of the memory controller 102 are connected to their corresponding signal wirings 107 which pass under the memory controller 102, on the lower-surface side of the memory controller 2. As shown in FIG. 1, data terminals of each memory chip 11 on the memory module 1 are connected to their corresponding data signal wirings 112 which pass through the memory module 1. Incidentally, terminal resistors 114 on the memory controller 102 side may not be provided for the address/command signal wirings 113 and the clock signal wiring 117. This is because address/command signals and a clock signal are signals which propagate in one direction. Address/command input terminals of the address/command buffer chip 12 on the memory module 1 are respectively connected to the address/command signal wirings 113 which pass through the memory module 1. The clock input terminal of the PLL chip 13 on the memory module 1 is connected to its corresponding clock signal wiring 117, which passes each memory module 1. Assuming now that the number of data terminals of each memory chip 11 is defined as n and the number of the memory chips 11 placed on the one side of the memory module 1 is defined as m, the memory system shown in FIG. 1 has m�n data signal wirings 112. The m memory chips 11 placed on the one side of one memory module of plural memory modules are selected for one access according to a chip select signal of command signals generated by the memory controller 102. [0095]FIG. 3 is a schematic equivalent circuit diagram of the memory system shown in FIGS. 1 and 2 and particularly shows one data signal wiring system. When the data signal wiring system is viewed on a circuit basis, terminal power sources 109, terminal resistors 105 and 106, a data signal wiring 112 for a motherboard, internal wirings 135 for connectors 104A, internal wirings 133 for connectors 104B, and module data wirings 15 of memory modules 1 are principally connected in series. Here, since the whole length of the data signal wiring 112 on the motherboard 101 and the module data wirings 15 of the memory modules reaches several tens of millimeters, they are handled as a transmission line on a circuit basis. A memory controller I/O terminal 128 of a memory controller 102 is provided at one-sided end on the terminal resistor 105 side, of the data signal wiring 112 on the motherboard 101. Each of the output capacity of an output circuit 123 of the memory controller 102 and the input capacity of an input circuit 124 of the memory controller 102, etc. is in view as memory controller I/O load capacity 125. Similarly, a data terminal (I/O terminal) 129 of each memory chip 11 is located midway between the data signal wirings 15 of each memory module 1. Each of the output capacity of an output circuit 120 of each memory chip 11 and the input capacity of an input circuit 121 thereof, etc. is in view as memory I/O load capacity 122. In the memory controller output circuit 123 and the output circuit 120 of each memory chip 11, a push-pull type, an open drain type, etc. are considered as their circuit types or modes. In the present embodiment, however, no request is made in particular. Although not illustrated in particular, a mechanism for controlling a through rate and a mechanism for controlling output impedance, for example, may be provided. Both sides of the data signal wiring system are terminated with the terminal resistors for the purpose of preventing reflection with respect to both of a signal transmitted from the memory controller output circuit 123 to the input circuit 121 of each memory chip 11 and a signal transmitted from the output circuit 120 of each memory chip 11 to the memory controller input circuit 124. Thus, terminal resistors may be placed only at a far end with respect to a signal transmission path extending in only one direction as in the case of an address output and a command output of the memory controller 102. As described above, the terminal resistors 114 shown in FIG. 4 may be omitted. [0096] One example of the memory module 1 will now be explained. FIG. 4 is a plan view of the memory module 1, and FIG. 5 is a side view thereof, respectively. The memory module 1 shown in FIGS. 4 and 5 includes a plurality of memory chips 11, a command/address buffer chip 12, and a PLL chip 13 which are respectively mounted on the surface and back surface of a substantially rectangular module substrate 10 made up of an epoxy resin or the like. [0097] The memory module 1 has module data wirings 15, module command/address wirings 16, and a module clock wiring 17 extending in the transverse direction of the module substrate 10 as wirings provided therewithin. Further, the memory module 1 includes module command/address distribution wirings 19 and a module clock distribution wiring 20 extending in the longitudinal direction of the module substrate 10. The module command/address distribution wirings 19 and the module clock distribution wiring 20 are provided with terminal resistors 22 and 23. The terminal resistors 22 and 23 terminate the ends of the module command/address distribution wirings 19 and the module clock distribution wiring 20 in terminal power sources and have resistance values each corresponding to the characteristic impedance or effective characteristic impedance of each connected wiring. Those wirings 15, 16, 17, 19 and 20 are equivalently formed on the surface and back surface of the module substrate 10. Incidentally, a mark 28 on the memory module indicates the direction of mounting of the memory module 1 in its corresponding connector when the memory module 1 is mounted in the connector. [0098] The memory module 1 has module data terminal pairs 24R and 24L, a module command/address terminal pair 25R and 25L, and a module clock terminal pair 26R and 26L as module external terminals along the opposite long sides of the module substrate 10. These module external terminals 24R, 24L, 25R, 25L, 26R and 26L are equivalently formed on the surface and back surface of the module substrate 10. [0099] The module data wirings 15 connect each right and left corresponding module data terminal pair 24R and 24L. Memory data terminals Dm of each memory chip 11 are connected to the midpoints of the module data wirings 15. The memory chip 11 is a flip chip (or flip-chip type semiconductor integrated circuit) having bump electrodes for the implementation of a circuit board or substrate, which are provided in array form, for example. The memory data terminals Dm are provided as solder bump electrodes for each flip chip. In the memory chip 11, such memory data terminals Dm are marked with ◯ respectively. [0100] The module command/address wirings 16 connect the right and left corresponding module command/address terminal pair 25R and 25L to each other. Buffer command/address input terminals CAi of the command/address buffer chip 12 are connected to points midway through the module command/address wirings 16. For example, the command/address buffer chip 12 is also used as the flip chip, and the buffer command/address input terminals CAi are used as solder bump electrodes. In the command/address buffer chip 12, such buffer command/address input terminals CAi are marked with ◯ respectively. [0101] The module clock wiring 17 connects the right and light corresponding module clock terminal pair 26R and 26L to each other. A PLL clock input terminal CLi of the PLL chip 13 is connected to a point midway through the module clock wiring 17. For example, the PLL chip 13 corresponds to a flip chip, and the PLL clock input terminal CLi is used as a solder bump electrode. In the PLL chip 13, such a PLL clock input terminal CLi is marked with ◯. [0102] The module command/address distribution wirings 19 are laid out along the longitudinal direction of the module substrate 10 and have an intermediate portion connected to buffer command/address output terminals CAj of the command/address buffer chip 12. Similarly, the module clock distribution wiring 20 is laid along the longitudinal direction of the module substrate 10 and has an intermediate portion connected to a PLL clock output terminal CLj. The buffer command/address output terminals CAj and the PLL clock output terminal CLj are represented as symbolic so as to be connected with output terminals of output buffers represented in the form of triangles. [0103] Memory command/address terminals (not shown) for command/address input, of each memory chip 11 are connected to the module command/address distribution wirings 19. Further, a memory clock terminal (not shown) for clock input, of the memory chip 11 and a buffer clock terminal (not shown) for clock input, of the buffer chip 12 are connected to the module clock distribution wiring 20. The memory chip 11 and the buffer chip 12 are capable of performing memory and latch operations in synchronism with a clock signal supplied from the PLL chip 13 through the module clock distribution wiring 20. [0104] Incidentally, the memory command/address terminals, memory clock terminal, buffer clock terminal and chip power terminals are not demonstratively shown in FIG. 4. In FIG. 4, module power terminals used for an operating power source are designated at numerals 202L and 202L respectively. [0105]FIG. 6 shows an example of a wiring arrangement related to the memory chip employed in the memory module 1. The module substrate 10 has a double-layer wiring structure having a first layer (surface layer) and a second layer (internal layer) respectively corresponding to the surface and back surface thereof. Wirings included in the first layer are indicated by solid lines, whereas wirings included in the second layer are indicated by broken lines. In the drawing, marks ◯ indicate external terminals like bump electrodes of each memory chip, and marks  indicate via (interlayer trenches or holes) defined in a wiring layer. The memory chip shown in the drawing corresponds to a synchronous DRAM represented as one example. A0 through A13 indicate addresses, D0 through D15 indicate data, and CLK, /CLK indicate two-phase clocks, respectively. CKE indicates a clock enable, DML and DMU indicate data masks, /CS indicates a chip selection, /RAS indicates a row address strobe, /CAS indicates a column address strobe, /WE indicates a write enable, and DQSL and DQSU indicate access control signals or command signals for data strobe. VCCQ, VSSQ, VCC, VSS and VSSQ shown in FIG. 6 indicate power terminals respectively. [0106] The module command/address distribution wirings 19 and the module clock distribution wiring 20 are laid or arranged in the form orthogonal to the module data wirings 15 on the module substrate 10. As is apparent from FIG. 6, the signal wirings 19 and 20 are connected to their corresponding terminals of each memory chip 11 through one-stroke writable wiring paths. It is apparent that according to the one-stroke writable wiring paths, the module command/address distribution wirings 19 and the module clock distribution wiring 20 per se have no branches. [0107] Judging from the standpoint of control on undesired signal reflection, the one-stroke writable paths are most suitable but all the wiring branches are not denied. If the following conditions are met, then no undesired signal reflection is developed for the most part. Namely, the module data wirings 15 for D0, D1, etc. are formed in a wiring layer corresponding to the second layer of the module substrate 10. When the module data wirings 15 are connected to their corresponding memory data terminals Dm of each memory chip 11 through the via (interlayer holes), the via portions slightly form branch portions respectively. Thus, the module data wirings 15 serve as one-stroke writable first wiring paths, whereas the via portions caused to branch off from the first wiring paths so as to be connected to the memory data terminals Dm constitute second wiring paths. At this time, the length of the second wiring path may be set so that the time necessary for a signal to assure a normal operation, for example to go to and from the second wiring path becomes shorter than a state transition time of the signal. In short, each branch portion whose signal path is as short as negligible in terms of signal reflection, may substantially be regarded as part of the one-stroke wiring path. [0108] When the memory data terminals are placed so as to be shifted between at least adjacent terminals as viewed in the direction in which the module data wirings extend, as in the case of D0, D1, . . . in FIG. 6, it becomes easy to form contacts between the memory data terminals Dm and the module data wirings 15. [0109]FIG. 7 is a vertical cross-sectional view schematically showing data wiring portions of connectors 104A and 104B. The connector 104A has a single horizontal trench or groove defined in one side thereof. Connector terminal sequences or rows 130 are formed on upper and lower surfaces of an internal surface of the horizontal groove. The connector terminal sequences 130 are connected to their corresponding wirings of data signal wirings 112 through in-connector wirings 135 every connector terminals. The connector 104B has single horizontal grooves defined in both sides thereof. Connector terminal sequences 131 and 132 are respectively formed on upper and lower surfaces of internal surfaces of the horizontal grooves. Terminals of the connector terminal sequences 131 and terminals of the connector terminal sequences 132, i.e., their corresponding terminals are connected in series to one another by in-connector wirings 133 and 134. [0110]FIG. 8 is a vertical cross-sectional view schematically showing power wiring portions of connectors 104A and 104B. A motherboard 101 is provided with a power wiring 108. Power connector terminals included in connector terminal sequences 130 are connected to their corresponding power wiring 108 through in-connector wirings 137, power connector terminals included in connector terminal sequences 131 are connected to their corresponding power wiring 108 through in-connector wirings 138, and power connector terminals included in connector terminal sequences 132 are connected to their corresponding power wiring 108 through in-connector wirings 139. Even in the case of a power source, the connections shown in FIG. 7 may be adopted. However, the adoption of the connection form shown in FIG. 8 rather than one shown in FIG. 7 allows stabilization of the supply of power to each memory chip 11 or the like. The command/address wirings 113 may also be connected to the connector terminal sequences 130, 131 and 132 of the connectors 104A and 104B in the same manner as the power wiring 108. [0111]FIG. 9 is a perspective view showing the mounting of the memory module 1 in connectors 104A and 104B. In order to fit the memory module 1 in the connectors 104A and 104B, terminal sequences of the memory module 1 are respectively put so as to be inserted between terminal sequences 130 of the connector 104A and between terminal sequences 131 of the connector 104B as shown in FIG. 9. At this time, marks 140 placed on the connectors are those used to indicate or point out the orientation and direction of the surface of the memory module 1. The surface and direction of the memory module 1 are aligned with each other in such a manner that a fit-in direction indication mark 28 for the memory module 1 and the mark 140 of each connector move closest to each other. [0112]FIG. 10 is a cross-sectional view showing the manner in which the memory modules 1 have been mounted in their corresponding connectors 104A and 104B. In FIG. 10, for convenience, paths connected to their corresponding memory chips located on the upper sides of the memory modules 1 are used as signal paths, and paths connected to their corresponding memory chips located on the lower sides of the memory modules 1 are used as power paths. Data signal paths are defined as wiring paths which pass without branching off at the connectors 104A and 104B and the memory modules 1. Since the power wirings of the respective memory modules 1 are also respectively connected to a power wiring 108 of a motherboard 101 through the mounted connectors 104A and 104B, the supply of sufficient power can be implemented and a voltage drop of a power source can be prevented from occurring. [0113] According to the first memory system, the following action and effects can be obtained. As is apparent from FIGS. 1 and 2, the module data wirings 15 on the memory module 1 constitute a memory access data bus together with the data signal wirings 112 on the motherboard 101. Thus, in the memory system in which a plurality of memory modules 1 are connected in series, the module data wirings 15 of the respective memory modules 1 are connected in sequential form. Further, each individual module data wirings 15 do not constitute branch wirings with respect to the data signal wirings 112 on the motherboard 101 of the memory system. Accordingly, such signal reflection as caused by branching with respect to the data signal wirings 112 on the motherboard 101 of the memory system does not occur. Since memory modules are branch-connected to a bus on a motherboard in the case of a memory system related to a comparative example having an SSTL interface, which is shown in FIGS. 11 and 12, for example, stub resistors are placed every branches to cope with undesired signal reflection. Therefore, the amplitude of a bus signal on the motherboard decreases in the comparative example, thus interfering with a stable operation. In the memory system shown in FIGS. 1 and 2, an undesired load on each signal wiring on the motherboard does not increase, and the configuration for inhibiting or blocking the signal reflection does not interfere with a reduction in signal amplitude. [0114] Further, since the data terminals Dm of each memory chip 11 are directly connected to the module data wirings 15 on each memory module 1, such signal reflection as caused by branching to the module data wirings 15 is not developed either. [0115] In the memory module 1, parallel access for the number of bits corresponding to the width of the memory access data bus is assured. Thus, the disturbance of each signal waveform due to the signal reflection is restrained while an increase in access time is being controlled, thereby to allow an increase in reliability of signal transmission. In a comparative example shown in FIGS. 13 and 14, a plurality of memory chips share the use of an in-module data bus on each memory module. The memory modules are connected in series with a serial bus. Further, since the memory modules are not branch-connected to the serial bus, signal reflection caused by branching is not substantially developed. However, limitations are imposed on high-speed access because the bus is made long and hence a wiring delay increases. [0116] Since power or the like is supplied in parallel from the motherboard 101 to the respective memory modules 1 through parallel paths comprising the in-connector wirings 137, 138 and 139, the supply of the power and a clock is stabilized. There is the possibility that when the power is supplied to each memory module in series, for example, one memory module will produce power noise in the course thereof, thus causing its influence to propagate toward a subsequent stage. Such possibility does not occur when operating power is supplied in parallel from parallel paths, and hence a high degree of reliability can be ensured for a memory operation. [0117] As forms of the module data terminal pair 24L and 24R and the module data wirings 15, the module data terminal pairs 24L and 24R are respectively placed at one long-side portions and the other long-side portions of each individual memory chip-mounted surfaces of the module substrate 10 when the plurality of memory chips 11 are arranged along the longitudinal direction of the module substrate 10. In other words, the module data wirings 15 are caused to extend from one long-side portion of each memory chip-mounted surface of the module substrate 10 to the other long-side portion thereof. Thus, the length of each module data wiring 15 becomes consequentially short, and the parasitic capacitance of each wiring and the wiring resistance thereof are reduced. [0118] Since the module data wirings 15 are linearly laid in the transverse direction of the module substrate 10, and the module command/address wirings 16 and 20 are laid in the shape of a substantially cross, they are most suitable for the shortening of wiring lengths of the module command/address wirings together with the module data wirings. [0119] Since the module command/address wirings 16 for coupling the module address terminal pair 25R and 25L to each other are separated from the command/address distribution wirings 19 through the command/address buffer chip 12, the formation of in-negligible impedance mismatching points on the module command/address wirings 16 can also be inhibited or blocked. [0120] Owing to the termination of the module command/address distribution wirings 19 with the resistive elements 22 and 23 having their characteristic impedances, the ends of the module command/address wirings 19 are matched and terminated. Thus, the disturbance of each waveform due to signal reflection can be reduced to the utmost at the wirings 19. [0121] Results of simulation of data signal waveforms employed in the memory system shown in FIGS. 1 and 2 will now be explained. [0122] As a comparative example, a simulation circuit of SSTL employed in the memory system of the type shown in FIG. 11 is first shown in FIG. 15. FIG. 16A shows the result of simulation of SSTL signal waveforms at a write operation of the simulation circuit shown in FIG. 15. FIG. 16B shows the result of simulation of SSTL signal waveforms at a read operation of the simulation circuit shown in FIG. 15. There may be cases in which a signal waveform at a receiving end is disturbed upon a high-speed operation or when each branch wiring is long, in the case of the SSTL of such a circuit type as shown in FIG. 11. [0123]FIG. 17 illustrates a simulation circuit related to data signals employed in the memory system described in FIG. 2 as an example. Let's now assume that a driver 2010 is placed under a memory controller 102 upon write operation simulation, and placed under each memory module upon read operation simulation. A push-pull output circuit having an output resistor 2009 is assumed as the driver 2010. In the present example, the resistance value of the output resistor is set as 50Ω. Further, a terminal resistor Rt is set to a value substantially identical to the effective characteristic impedance of each data signal wiring. A terminal resistor on the memory controller side, which is equal to 55Ω in resistance value, is set to a value substantially equal to the characteristic impedance of a transmission line laid between the memory controller and a memory module located at an end close to the memory controller. [0124]FIG. 18A shows a simulation result at the write operation of the simulation circuit (memory system described in FIG. 2) shown in FIG. 17. It is understood that when data signals bQR0 through bQR3 (2001 through 2004) inputted to each individual memory chips are viewed, they are small in waveform disturbance as compared with data signals bQR0 through bQR3 (2101 through 2104) inputted to the memory chips at the write operation-based simulation result shown in FIG. 16A. FIG. 18B shows a simulation result at the read operation of the simulation circuit (memory system described in FIG. 2) shown in FIG. 17. DQRSIN1 through DQRSIN4 in the drawing respectively indicate data signals DQRSIN1 through DQRSIN4 (2006) respectively inputted to the memory controller when the data signals bQR0 through bQR3 (2001 through 2004) inputted to the memory chips are outputted. It is understood that they are small in waveform disturbance as compared with data signals DQRSIN1 through DQRSIN4 (2106) inputted to their corresponding memory chips at the read operation-based simulation result of the memory system according to the comparative example shown in FIG. 16B. Even in the case of a system in which an output resistor is set to 15Q, a satisfactory waveform is obtained in the same manner as described above. In this case, an effect is brought about in that power consumption increases but logical amplitude can be made great. [0125] Second through fifth memory systems [0126]FIG. 19 is an equivalent circuit diagram of a data signal wiring system employed in a second memory system according to the present invention. In the present memory system, a first switch 230 is newly added to a terminal resistor 105 on the memory controller 102 side, and a second switch 231 is newly added to a terminal resistor 106 on the side opposite to the memory controller 102 as compared with the first memory system shown in FIG. 3. Of these, the first switch 230 is turned on upon read (reading) of each memory and turned off upon write (writing) thereof, whereby the end or terminal on the memory controller 102 side, of a signal wiring 112 can be impedance-matched upon read (reading) of the memory. Further, when the second switch 231 is turned on upon write (writing) of the memory and turned off upon read (reading) of the memory, the end or terminal connected to a signal wiring 135 corresponding to the farthest end as viewed from the memory controller 102 can be impedance-matched. [0127] The first switch 230 and the second switch 231 can be implemented by switch elements each comprising a MOS transistor, for example. The memory controller 102 may perform their control according to an access operation. Further, a command/address buffer chip 12 may be set so as to have its switch control function. [0128] In the first memory system shown in FIG. 3, the terminals at both ends of the series wiring path formed by the signal wiring 112 and the in-connector wiring 135 or the like are always terminated with resistors. Upon write (writing) of each memory and read (reading) thereof, a current flows through both resistors, so that power consumption increases. In the second memory system shown in FIG. 19, only one of the terminals at both ends of a series wiring path formed by the signal wiring 112 and the in-connector wiring 135 or the like is resistance-terminated according to the write (writing) of each memory and the read (reading) thereof, and a current flows through one terminal resistor alone. Therefore, the present memory system can achieve low power consumption as compared with the first memory system. Since logical amplitude can be mage great, a noise margin can also be increased. [0129]FIG. 20 is an equivalent circuit diagram of a data signal wiring system employed in a third memory system according to the present invention. The memory system shown in the same drawing is different from the first memory system shown in FIG. 3 in that a switch 230 is added to a terminal resistor 105 on the memory controller 102 side. The switch 230 is turned on upon read (reading) of each memory and turned off upon write (writing) thereof, so that the end or terminal on the memory controller 102 side, of a signal wiring 112 can be impedance-matched upon read (reading) of the memory. Incidentally, the switch 230 can be implemented by a MOS transistor, and the memory controller 102 may perform its control. In the first memory system referred to above, the terminals at both ends of the signal wiring 112 are always terminated with resistors. Upon write of each memory and read thereof, a current flows through both resistors, so that power consumption increases. On the other hand, in the third memory system, only the end or terminal on the side opposite to the memory controller 102, of the terminals at both ends of the signal wiring 112 is terminated with a resistor 106, and a current flows through one terminal resistor alone upon write of the memory. Therefore, the present memory system can achieve low power consumption as compared with the first memory system. A noise margin at the write can be made great. The second memory system needs two switches at both ends of the series path formed by the signal wiring 112 and the in-connector wirings 133 and 135 and causes an increase in manufacturing cost. In regard to this point of view, the third memory system needs one switch alone and can provide a cost reduction as compared with the second memory system. [0130]FIG. 21 is an equivalent circuit diagram of a data signal wiring system employed in a fourth memory system according to the present invention. In the present memory system, the terminal resistor 105 on the memory controller 102 side is omitted from the first memory system shown in FIG. 3. Further, the present memory system adopts open drain type output transistors 233 as output circuits for memory chips 11. Since an output resistor for each transistor varies upon the operation of a push-pull type output circuit, the effective characteristic impedance of a series wiring path for data, which comprises a signal wiring 112, etc., is disturbed and reflection is easy to take place. On the other hand, if the open drain output circuits comprising the open drain type output transistors 233 are adopted, then an output resistor at its operation can be rendered high and kept substantially constant. Therefore, the effective characteristic impedance of the data series wiring path is not disturbed upon operation. Due to this reason, the present memory system impedance-matches only the end or terminal on the side opposite to the memory controller 102 with a resistor 106. Thus, since the number of terminal resistors becomes one, the present memory system can provide a reduction in cost and low power consumption as compared with the first memory system. [0131]FIG. 22 is an equivalent circuit diagram related to a command/address signal wiring system employed in the fourth memory system. Since a signal is transmitted from a memory controller 102 to each command/address buffer chip 12 in one direction alone in the command/address signal wiring system, only a terminal resistor 106 on the side opposite to the memory controller 102 may be adopted as a terminal resistor in a manner similar to other examples. [0132]FIG. 23 is an equivalent circuit diagram showing a data signal wiring system employed in a fifth memory system according to the present invention. In the memory system shown in the same drawing, the terminal resistor 106 on the side opposite to the memory controller 102 is omitted from the first memory system on the contrary to the fourth memory system shown in FIG. 21. Further, the present memory system adopts an open drain type output transistor 235 constituting an open drain type output circuit, in an output circuit for the memory controller 102. Thus, the present memory system can provide a reduction in cost and low power consumption as compared with the first memory system due to a reason similar to the fourth memory system shown in FIG. 21. [0133] Memory controllers [0134]FIG. 24 is a circuit diagram most suitable for the first memory system (see FIG. 3) according to the present invention. A memory controller 102 shown in the same drawing incorporates therein a resistor 105A matched with the effective characteristic impedance of a data signal wiring 112 and is electrically connected to a data signal terminal 240 and a terminal source 109 provided inside the memory controller. Using the memory controller 102 having adopted a configuration shown in the same drawing in the first memory system eliminates the need for the external terminal resistor 105 on the memory controller 102 side of the motherboard 101 shown in FIG. 1, thereby making it possible to realize a reduction in cost. [0135]FIG. 25 is a circuit diagram of a memory controller 102 most suitable for the second memory system (see FIG. 19) according to the present invention. The memory controller 102 shown in the same drawing has a first switch changeover signal terminal 241 and a second switch changeover signal terminal 242 and outputs signals for selecting the turning on/off of a first switch 243 and a second switch 244 respectively provided outside the memory controller 102. An output circuit 246 outputs an input mode signal 245 inputted to the memory controller 102 to the first switch changeover signal terminal 241 and an inversion output circuit 247 inverts the input mode signal 245 inputted thereto and outputs it to the second switch changeover signal terminal 242, whereby the outputs to these signal terminals 241 and 242 are produced. Here, the input mode signal 245 inputted to the memory controller 102 is brought to a level �H� upon the input of data and brought to a level �L� upon the output thereof. Further, the first switch 243 and second switch 244 provided outside the memory controller 102 comprise, for example, MOS transistors respectively. They are turned on when a gate level is �H� and turned off when the gate level is �L�. Using the present memory controller 102 in the second memory system makes it possible to control or restrain power consumption made by an unnecessary terminal resistor as described above. A terminal resistor 105 may be incorporated into the memory controller 102 as shown in FIG. 24. [0136]FIG. 26 is a circuit diagram most suitable for the third memory system (see FIG. 20) according to the present invention. The memory controller 102 shown in the same drawing has a switch 250 for controlling the connection of a built-in terminal resistor 105A to the signal terminal 240, which resistor is incorporated into the memory controller employed in the first memory system shown in FIG. 24. This switch 250 is turned on and off according to an input mode signal 245 supplied to the memory controller 102. Accordingly, the terminal resistor 105A becomes effective only upon timing requiring it, i.e., only upon the input of the signal to the memory controller 102. Thus, the adoption of the configuration of the memory controller 102 shown in FIG. 26 in the third memory system makes it possible to control power consumption made by an unnecessary terminal resistor and provide a low power consumption type memory system. Since there is no need to provide the terminal resistor 105 on the motherboard 101 on the memory controller 102 side, a reduction in cost can be achieved. [0137]FIG. 27 shows a further circuit example of a memory controller 102 most suitable for the third memory system (see FIG. 20) according to the present invention. The memory controller 102 shown in the same drawing is one from which the inversion output circuit 24 and switch changeover signal terminal 242 of the memory controller employed in the second memory system shown in FIG. 25 are omitted. The adoption of the configuration of FIG. 27 in the memory controller 102 of the third memory system makes it possible to control power consumption made by an unnecessary terminal resistor and provide a low power consumption type memory system. [0138]FIG. 28 is a circuit diagram showing a memory controller most suitable for the fifth memory system shown in FIG. 23. The memory controller 102 shown in the same drawing is one in which an open drain transistor 251 constituting an open drain type output circuit is used in the output circuit of the memory controller 102 employed in the first memory system of FIG. 24. The adoption of the present configuration in the memory controller 102 of the fifth memory system according to the present invention eliminates the need for the terminal resistor 105 on the memory controller side of the motherboard 101 and allows a cost reduction. Of course, the terminal resistor (105) may be placed outside the memory controller as shown in FIG. 1. [0139] Examples of other memory system [0140]FIGS. 29A, 29B and 29C respectively show cross sections of a second memory module having a structure different from FIG. 4. FIG. 29A is a cross-sectional view related to a data signal wiring employed in a one-bank type memory module. In the present memory module 2, a module data terminal pair 24L and 24R is placed on both surfaces of a module substrate 10 along one long-side portion thereof. A module data wiring 15 is connected to the module data terminal pair 24R and 24L via a through hole 200. The module data wiring 15 has a one-stroke writable wiring route or path in a manner similar to the first memory module 1 shown in FIG. 4. Such branches as formed by the via (interlayer holes), which are as small as negligible, are developed between the module data wiring 15 and the memory data terminals Dm of each memory chip 11. Such branch portions do not lead to undesired signal reflection as is apparent from the above. [0141]FIG. 29B is a cross-sectional view related to a signal wiring at a two-bank type memory module. In the memory module 2 shown in FIG. 29A, one module data wiring 15 is connected to its corresponding memory data terminal Dm of one memory chip 11 placed on one side of the module substrate 10, whereas in the memory module shown in FIG. 29B, one module data wiring 15 is connected to memory data terminals Dm and Dm of memory chips 11 and 11 placed on both surfaces of a module substrate 10 on a one-stroke writing basis. [0142]FIG. 29C is a cross-sectional view related to a power wiring for the memory module 2. Module power wirings 201 are wired to their corresponding chip power terminals Dp of the memory chips 11 but have no need for connection under a one-stroke writable route or path. They extend so as to branch off from module power terminals 202L and 202R respectively. Incidentally, module command/address wirings 16 and a module clock wiring 17 may be handled in a manner similar to the module power wirings 201. Alternatively, they may be handled in a manner similar to the module data wirings 15 as shown in FIG. 4. [0143]FIG. 30A shows a connector 210 for the second memory module 2 with attention to each signal wiring. The connector 210 has a single vertical trench or groove. Connector terminal sequences are formed on the right and left internal surfaces of the vertical groove as viewed in the front/back direction of the sheet. Connector terminals 211 and 212 are typically shown in the drawing. Data signal wirings 112 on a motherboard are respectively connected to the connector terminals 211 and 212, where they are divided. [0144]FIG. 30B shows the connector 210 for the second memory module 2 with attention to a power wiring. Connector terminals 213 and 214 typically shown as connector terminals for power are respectively connected to branch wirings 215 and 216 which branch off from the power wiring 108. The power wiring 108 is not electrically divided in the course thereof. [0145] A cross section of a memory system equipped with memory modules 2 is shown in FIG. 31A in relation to a signal wiring. When the memory modules 2 are mounted in their corresponding connectors 210 in the memory system shown in the same drawing, data signal wirings 112 divided by the connectors 210 are connected to one another through module data wirings 15 of the memory modules 2. [0146] A cross section of the memory system equipped with the memory modules 2 is shown in FIG. 31B in association with a power wiring. When the memory modules 2 are fitted in their corresponding connectors 210 in the present memory system, module power terminals of the memory modules 2 are respectively connected to a power wiring 108 of a motherboard 101 through power connector terminals 213 and 214 of the connectors 210. Incidentally, the command/address signal wirings 113 may be connected to each memory module 2 through the connector 210 from the command/address signal wirings 113 of the motherboard 101 in the same manner as the power wiring 108 in FIG. 30B. Of course, they may be connected as shown in FIG. 31B. [0147] Even in the case of the second memory module 2 in the same manner as described above, branching which leads to undesired signal reflection, is not developed. Each memory chip can electrically be connected to the data signal wirings of the motherboard 101 without an increase in wiring length. [0148]FIG. 32 is a plan view of a third memory module. In the memory module 3 shown in the same drawing, module data terminal pairs 24L and 24R are placed so as to adjoin each other on the same surface and side of a module substrate 10. The terminal pairs 24L and 24R are respectively connected to one another by module data wirings 15 laid down on a return or reciprocating basis and thereafter connected to memory data terminals Dm of one memory chip 11 on a one-stroke writing basis in the course of the module data wirings 15. [0149]FIGS. 33A and 33B respectively illustratively show forms in which the third memory modules 3 are connected to one another by connectors. FIG. 33A is supposed as a vertical cross-sectional view at the position of each module data terminal 24L of FIG. 32, whereas FIG. 33B is assumed as a vertical cross-sectional view at the position of each module data terminal 24R of FIG. 32. In FIG. 33A, data signal wirings 112 are connected to their corresponding module data wirings 15 of each memory module 3 through data connector terminals 301L and module data terminals 24L of each connector 300 as viewed from a motherboard 101. The module data wirings 15 include paths folded back on a module substrate 10. Further, the module data wirings 15 reach the module data terminals 24R adjacent to the module data terminals 24L and are made conductive to their corresponding data signal wirings 112 of a motherboard 101 as viewed from data connector terminals 301R of the connectors 300 as illustrated in FIG. 33B by way example. While a form for connection to a power wiring 108 on the motherboard 101 is not illustrated in particular, the power terminal 108 of the motherboard 101 may be connected to its corresponding module power terminal of each memory module 3 through the connector in a manner similar to FIG. 31B. [0150] Even in the case of the third memory module 3 in the same manner as described above, each memory chip can electrically be connected to the data signal wirings without creating branching and causing an increase in wiring length. [0151] Dummy memory modules [0152] Dummy memory modules by which some of memory modules constituting each memory system can be replaced, will be explained. [0153]FIG. 34 is a plan view of a dummy memory module 1A capable of constituting a memory system by using it together with the first memory module 1 described in FIG. 4, and FIG. 35 is a side view of the dummy memory module, respectively. The dummy memory module 1A shown in the same drawing has a configuration in which the memory chips 11, command/address buffer chip 12, PLL chip 13, module command/address distribution wirings 19, module clock distribution wiring 20 and terminal resistors 22 and 23 are omitted from the memory module 1 shown in FIG. 4. In other words, the dummy memory module 1A has module terminal pairs typified by 24L and 25R, module data wirings 15, module command/address wirings 16, and a module clock wiring 17 provided on a module substrate 10. If the dummy memory module 1A shown in FIG. 34 is mounted and used in its corresponding connectors 104A and 104B in place of the memory module 1 in the memory system described in FIGS. 1 and 2, then the memory capacity of the memory system can be changed without producing branching in the paths of the signal wirings 112, 113 and 117 and causing an increase in wiring length. [0154] Although not illustrated in particular, if dummy capacities having reproduced input capacities of chips 11, 12 and 13 are provided for the wirings 15, 16 and 17 on the dummy memory module 1A, then the disturbance of each waveform can further be restrained without disturbing effective characteristic impedance. [0155]FIGS. 36A, 36B and 36C respectively show a dummy memory module 2A available together with the second memory module 2, in which FIG. 36A is a cross-sectional view taken along line a-a, FIG. 36B is an enlarged surface view, and FIG. 36C is an enlarged back side view, respectively. The dummy memory module 2A shown in FIG. 36A has a configuration in which devices such as the memory chips 11, etc. are omitted from the memory module 2 shown in FIGS. 29A, 29B and 29C. In short, the dummy memory module 2A comprise module terminal pairs typified by 24L and 25R, module wirings typified by 15, and through holes 200 for the module wirings, which are provided on the surface and back surface of the module substrate 10. If the dummy memory module 2A is used in place of the memory module 2 in the memory system shown in FIG. 31, then the memory capacity of the memory system can be changed without developing branching and causing an increase in wiring length. [0156]FIG. 37 shows a dummy memory module 3A available together with the third memory module 3. The memory module 3A shown in the same drawing has a configuration in which devices such as memory chips 11, etc. are omitted from the memory module 3 shown in FIG. 32. In short, the dummy memory module 3A comprise module terminal pairs typified by 24L and 25R, and module wirings typified by 15, which are provided on the surface of a module substrate 10. If the dummy memory module 3A is used in place of the third memory module 3, then the memory capacity of the memory system can be changed without developing branching and causing an increase in wiring length. [0157] Memory modules for termination [0158] Memory modules for termination, which are equipped with terminal resistors each externally attached to a motherboard of a memory system, will be explained. [0159]FIGS. 38A and 38B respectively show a memory module 1B for termination, wherein the first memory module 1 is equipped with terminal resistors, wherein FIG. 38A is a partly plan view, and FIG. 38B is a side view, respectively. The memory module 1B shown in FIGS. 38A and 38B has a configuration in which one module terminals 24R of the module terminal pairs 24L and 24R or the like shown in FIG. 1 are removed, terminal resistors 106A are respectively connected to module data wirings 15 connected to the remaining module terminals 24L or the like, and terminating power terminals 30 are connected to the terminal resistors 106A. The back side of a module substrate 10 is also configured in the same manner as described above as shown in FIG. 38B. [0160]FIG. 39 shows a dummy memory module 1C for termination, which corresponds to the dummy memory module 1A shown in FIG. 34. The present dummy memory module 1C has a configuration in which one module terminals 24 or the like of the module terminal pairs 24L and 24R or the like are omitted from the dummy memory module shown in FIG. 34, terminal resistors 106A are connected to their corresponding module data terminals 15 or the like connected to the remaining module terminals 24L or the like, and terminating power terminals 30 are connected to their corresponding terminal resistors 106A. [0161] If either the memory module 1B shown in FIG. 38 or the memory module 1C shown in FIG. 39 is used in place of the memory module 1 in the memory system shown in FIG. 1, then the signal wirings 112, 113 and 117 on the motherboard 101 can be terminated on the memory module without using the terminal resistors 106 on the motherboard 101. [0162]FIGS. 40A, 40B and 40C respectively show a memory module 2B for termination, in which the memory module 2 shown in FIGS. 29A, 29B and 29C is equipped with terminal resistors, wherein FIG. 40A is a cross-sectional view taken along line a-a, FIG. 40B is an enlarged surface view, and FIG. 40C is an enlarged back side view, respectively. The memory module 2B shown in FIGS. 40A, 40B and 40C has a configuration in which one module terminals 24R or the like of the module terminal pairs 24L and 24R or the like shown in FIGS. 29A, 29B and 29C are removed, terminal resistors 106A are connected to their corresponding module data wirings 15 or the like connected to the remaining module terminals 24L or the like, and terminating power terminals 30 are connected to the terminal resistors 106A. [0163] If the memory module 2B for termination is used in place of the memory module 2 in the memory system shown in FIGS. 31A and 31B, then the signal wirings 112 can be terminated on the memory module without using the terminal resistors 106 on the motherboard 101. Other signal wirings 113 and 117 can also adopt a similar configuration respectively. [0164]FIG. 41 shows a memory module 3B for termination, in which the memory module 3 shown in FIG. 32 is equipped with terminal resistors. The memory module 3B shown in FIG. 41 has a configuration in which one module terminals 24R or the like of the module terminal pairs 24L and 24R or the like shown in FIG. 32 are removed, terminal resistors 106A are connected to their corresponding module data wirings 15 or the like connected to the remaining module terminals 24L or the like, and terminating power terminals 30 are connected to the terminal resistors 106A. If the memory module 3B for termination is used in place of the memory module 3 shown in FIG. 32, then the signal wirings 112 and the like can be terminated on the memory module without using the terminal resistors 106 on the motherboard 101. [0165] Other forms of connectors [0166] Other forms of connectors, which constitute each memory system, will be explained. [0167]FIGS. 42 and 43 respectively illustrate other forms of the connectors 104A and 104B shown in FIGS. 7 and 8 by way of example. FIG. 42 shows a portion connected to data signal wirings 112 in the form of a cross section, and FIG. 43 shows portions connected to a power wiring 108 in the form of cross sections. Portions connected to command/address signal wirings 113 and a clock signal wiring 117 are configured as shown in FIG. 43, for example. [0168] In short, the configurations shown in FIGS. 42 and 43 are formed in such a manner that the connectors 104A and 104B shown in FIGS. 7 and 8 are detachably configured in form divided into two as viewed in a vertical direction to thereby facilitate the attachment of the memory modules 1, 1A and 1B. [0169] Namely, the connector 104A is divided into two of 104Aa and 104Ab. A single connector terminal portion 104Ap formed in projected form is provided at the bottom of the divided piece or part 104Aa. Further, a single connector terminal portion 104Ag formed in recessed form is provided on the upper surface of the divided part 104Ab. Similarly, two single connector terminal portions 104Bp1 and 104Bp2 formed in projected form are provided at the bottom of the divided part 104Ba, and two single connector terminal portions 104Bg1 and 104Bg2 formed in recessed form are provided on the upper surface of the divided part 104Bb. [0170] In FIG. 42, data signal wirings 112 are capable of being conductive to their corresponding terminals of connector terminal sequences 130 by connector built-in wirings 135 a and 135 b at portions corresponding to the data signal wirings 112, of the connector terminal portions 104Ap and 104Ag. In FIG. 43, a power wiring 108 is capable of being conductive to its corresponding terminals of connector terminal sequences 130 by connector built-in wirings 137 a and 137 b at portions corresponding to the power wiring 108, of the connector terminal portions 104Ap and 104Ag. The connectors 104Aa and 104Ab connected to the command/address signal wirings 113 and the clock signal wiring 117 are also similar to FIG. 43. [0171] Further, terminals corresponding to data signal wirings 112, of connector terminal sequences 131 and 132 in the divided part 104Ba of the connector 104B are mutually brought into conduction by connector built-in wirings 133 and 134 as shown in FIG. 42 and are configured substantially in the same manner as FIG. 7. In FIG. 43, the power wiring 108 is capable of being conductive to the corresponding terminals of the connector terminal sequence 131 by connector built-in wirings 138 a and 138 b at portions corresponding to the power wiring 108, of the connector terminal portions 104Bp1 and 104Bg1. Similarly, the power wiring 108 is capable of being conductive to the corresponding terminals of the connector terminal sequence 132 by connector built-in wirings 139 a and 139 b at portions corresponding to the power wiring 108, of the connector terminal portions 104Bp2 and 104Bg2. The connectors 104Ba and 104Bb connected to the command/address signal wirings 113 and the clock signal wiring 117 are also similar to FIG. 43. [0172] The operation of mounting memory modules to a memory system using the connectors shown in FIGS. 42 and 43 is as follows. For example, the connector terminal sequences 130 of the connector divided part 104Aa and the connector terminal sequences 131 of the connector divided part 104Ba are respectively coupled to the right and left module terminals of the memory module 1. Subsequently, the connector terminal sequences 132 of the connector divided part 104Ba and the connector terminal sequences 131 of the connector divided part 104Ba are coupled to the right and left module terminals of the next memory module 1. Thus, after the required number of memory modules are horizontally coupled in series, the connector terminal 104Ap of the connector divided part 104Aa connected to the memory module is connected to its corresponding connector terminal 104Ag of the connector divided part 104Ab. Further, the connector terminals 104Bp1 and 104Bp2 of the connector divided part 104Ba connected to the memory module are connected to their corresponding connector terminals 104Bg1 and 104Bg2 of the connector divided part 104Bb. Thus, since a space necessary for the operation of installation of each memory module takes only a space above the memory system, another device can be installed around the memory system or the memory system can be placed in a location surrounded by walls. [0173]FIG. 44 shows an example of a memory module partly provided with connector's functions. The memory module 1C shown in the same drawing takes a configuration in which connector terminal sequences 132E respectively having functions equivalent to the connector terminal sequences 132 shown in FIG. 43 and a connector terminal portion 104BpE having a function equivalent to the connector terminal portion 104Bp2 are added to the memory module 1 shown in FIG. 4. The connector terminal sequences 132E are connected to their corresponding module data wirings 15, and the connector terminal portion 104BpE is connected to the corresponding module power wirings, module command/address wirings 16 and module clock wiring 17. A connector 104B is placed on a motherboard 101 in association with the connector terminal portion 104BpE. Owing to the configuration shown in FIG. 44, the quantity of work for connecting the memory modules to the motherboard can be reduced as compared with the configurations shown in FIGS. 42 and 43. Further, the number of parts employed in the memory system can be reduced. This configuration is also considered to be capable of contributing to a reduction in the cost of the memory system. [0174]FIG. 45 shows portions at which connectors corresponding to other forms applicable to the memory module 1 are connected to their corresponding data signal wirings 112, in the form of cross sections. Connectors 154, 155 and 156 respectively have connector terminals 154A, 155A and 156A formed in upward recessed trenches and are capable of allowing the memory module 1 to uprise and supporting it. A connector 157 has connector terminals 157A and 157B formed in downward recessed trenches and allows a pair of vertically-set memory modules 1 to be inserted therein. The data signal wirings 112 on a motherboard 101 are connected to a connector terminal 154A through in-connector wirings 154 a and 154 b, a connector terminal 155A through in-connector wirings 155 a and 155 b, a connector terminal 156A through in-connector wirings 156 a and 156 b, and connector terminals 157A and 157B through in-connector wirings 157 a and 157 b, respectively. Thus, when the memory modules 1 are mounted in the connectors 154, 155 and 157, the wirings 154 a, 157 a and 156 a are made conductive to their corresponding data signal wirings 112, and the wirings 154 b, 157 b and 156 b are made conductive to their corresponding data signal wirings 112. The memory modules 1 are capable of being conductive to the data signal wirings 112 without having branching. [0175]FIG. 46 shows portions at which connectors corresponding to further forms applicable to the memory module 1 are connected to their corresponding data signal wirings 112, in the form of cross sections. A connector 164 has a connector terminal 164A formed in an upward recessed trench. A connector 165 has connector terminals 165A and 165B formed in upward recessed trenches and is capable of allowing the memory module 1 to uprise and supporting it. A connector 166 has connector terminals 166A and 166B formed in downward recessed trenches and allows a pair of vertically-set memory modules 1 to be inserted therein. The data signal wirings 112 on a motherboard 101 are connected to the connector terminal 164A through in-connector wirings 164 a and 164 b. The connector terminals 165A and 165B are connected to each other through in-connector wirings 165 a and 165 b. The connector terminals 166A and 166B are connected to each other through in-connector wirings 166 a and 166 b. Thus, when the memory modules 1 are mounted in the connectors 164, 165 and 167, the wirings 164 a, 166 a and 165 a are made conductive to their corresponding data signal wirings 112, and the wirings 164 b, 166 b and 165 b are made conductive to their corresponding data signal wirings 112. The memory modules 1 are capable of being conductive to the data signal wirings 112 without having branching. [0176]FIG. 47 shows a cross section of a power wiring portion associated with the connectors shown in FIG. 46. A power wiring 108 on a motherboard 101 branches off in the course thereof, which in turn are connected to corresponding power terminals of the connector terminals 164A and 165A through in-connector wirings 164 c and 165 c. [0177]FIG. 48 shows a state in which memory modules are mounted in the connectors shown in FIGS. 46 and 47. If the connectors 164 through 166 are used, the a memory system for connecting memory elements to their corresponding data signal wirings can be formed on a motherboard in a small occupied area without creating branching and causing an increase in wiring length. This is identical even when the connectors 154 through 157 shown in FIG. 45 are used. Even in relation to the connections of command/address signal wirings 113 and a clock signal wiring 117, the connectors shown in FIG. 45 or 46 may be used. [0178] Other forms of memory system [0179] A perspective view of FIG. 49A and a side view of FIG. 49B respectively show a still further form of a memory module. The memory module 1C shown in the same drawings is different from the memory module 1 in that a module terminal pair 170L and 170R typified by the data terminal pair 24L and 24R is formed in a direction orthogonal to a module substrate 10. [0180]FIG. 50 shows one example of a memory system equipped with the memory modules shown in FIGS. 49A and 49B. Although not restricted in particular, the connectors 164 and 165 shown in FIG. 46 are used as connectors on a motherboard 101. The connectors 154, 155 and 156 or the like shown in FIG. 45 may be used. Since the connector 166 shown in FIG. 46 and the connector 157 shown in FIG. 45 become unnecessary and a space necessary for the work of installation of each memory module is directed only above the memory system, another device can be installed around the memory system or the memory system can be installed in a location surrounded by walls. [0181]FIG. 51 shows one example in which the memory system shown in FIG. 1 is formed on one substrate 260 without using connectors and memory modules. Consequently, the memory system can be brought into less size and is capable of shortening a data access time. The number of parts is reduced, thereby contributing to a cost reduction. Further, the memory system may be formed on both surfaces of the same substrate 260 as shown in FIG. 52 by way of example. It is thus possible to increase the capacity of each memory simultaneously with a size reduction. [0182] As shown in FIG. 53 by way of example, the memory system 261 shown in FIG. 52 is mounted on a substrate 263 together with a CPU 262, and the whole body may be sealed with a package 264 to form an MCM (Multi Chip Module). The CPU 262 is electrically connected to a main controller 102 of the memory module 261 and obtains access to each memory chip 11 through the memory controller 102. [0183] A personal computer system is illustrated in FIG. 54 as one example of a data processing system using the memory system described above. Although not restricted in particular, the personal computer system has a processor bus BUS1 whose operating speed is comparatively fast, and a peripheral bus BUS2 whose operating speed is relatively slow. A microprocessor 280 corresponding to one example of a data processor, an L2 cache memory 281, and the above-described memory system 282 are connected to the processor bus BUS1. It is needless to say that the above-described memory systems represented in various forms can be applied as the memory system 282. On the other hand, a configuration provided with a memory controller 102 and a memory module 1 is typically illustrated in FIG. 54. The microprocessor 280 incorporates a CPU, an L1 cache memory, etc. therein and obtains access to a memory chip with the memory module 1 built therein, as a main memory. A bridge circuit 284 performs control on an interface between the processor bus BUS1 and the peripheral bus BUS2. An IDE (Integrated Device Electronics) controller 287, a graphics controller 285, and another interface controller 288 are connected to the peripheral bus BUS2. The IDE controller 287 is connected to an auxiliary storage device 290 such as hard disk drive or the like and performs disk access control. The graphics controller 285 is connected to a frame buffer memory 286 and a display 291 and performs drawing control and display control. Another peripheral circuit 292 such as a keyboard, a pointing device or the like is connected to another interface controller 288. [0184] If the memory system 282 is adopted in the personal computer system, then a signal waveform is not disturbed even if the frequency of the memory system increases. Further, the latency is also restrained and high-speed data transmission is allowed. Therefore, this contributes to an increase in the speed for processing data by the computer system. [0185] While the invention made by the present inventors has been described above specifically based on the embodiments, the present invention is not limited to the embodiments. It is needless to say that various changes can be made thereto within the scope not departing from the substance thereof. [0186] For example, a memory chip is not limited to a synchronous DRAM, and another storage type memory may be used in place of it. A memory system may be implemented by employing connectors having configurations other than those for the above-described connectors in memory modules. [0187] A memory module according to the present invention is particularly effective for application to a personal computer, a work station, or a computer system requiring a large capacity memory, like a server. [0188] Advantageous effects obtained by a typical one of the inventions disclosed in the present application will be described in brief as follows: [0189] Namely, the disturbance of each signal waveform due to signal reflection can be controlled to improve the reliability of signal transmission. Further, the stability of a memory operation is improved, and an increase in access time can be restrained. [0190] If a memory module according to the present invention is applied to a computer system, then no signal waveform is disturbed even if the frequency of the memory system is increased, and data can be transmitted at high speed while latency is being controlled. It is therefore possible to increase the speed for processing data by a computer system. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6584004 *Feb 28, 2001Jun 24, 2003Hitachi, Ltd.Electronic circuit packageUS6728904Feb 24, 2003Apr 27, 2004Hitachi, Ltd.Electronic circuit packageUS7120069Feb 26, 2004Oct 10, 2006Hitachi, Ltd.Electronic circuit packageUS7233534Jul 14, 2005Jun 19, 2007Hitachi, Ltd.Electronic circuit packageUS7425763Mar 7, 2007Sep 16, 2008Hitachi, Ltd.Electronic circuit packageUS7633147 *Sep 26, 2003Dec 15, 2009Elpida Memory, Inc.Semiconductor unit having two device terminals for every one input/output signalUS7701743Aug 7, 2008Apr 20, 2010Rising Silicon, Inc.Electronic circuit packageWO2007002531A2 *Jun 22, 2006Jan 4, 2007Robert F McclanahanPoint-of-load power conditioning for memory modules* Cited by examinerClassifications U.S. Classification365/63International ClassificationG11C5/04, H05K1/02, G06F13/16, G11C5/06, H05K1/14, G06F1/18, G06F12/02Cooperative ClassificationH05K1/0216, H05K1/14, G11C5/06, G11C5/04European ClassificationG11C5/04, G11C5/06Legal EventsDateCodeEventDescriptionMay 15, 2014ASAssignmentOwner name: PS4 LUXCO S.A.R.L., LUXEMBOURGFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ELPIDA MEMORY, INC.;REEL/FRAME:032894/0746Effective date: 20130726Feb 24, 2014ASAssignmentFree format text: RELEASE BY SECURED PARTY;ASSIGNOR:APPLE, INC;REEL/FRAME:032331/0637Owner name: ELPIDA MEMORY, INC., JAPANEffective date: 20140114Nov 27, 2013FPAYFee paymentYear of fee payment: 12Jul 29, 2013ASAssignmentFree format text: SECURITY AGREEMENT;ASSIGNOR:PS4 LUXCO S.A.R.L.;REEL/FRAME:032414/0261Owner name: ELPIDA MEMORY INC., JAPANEffective date: 20130726May 15, 2012ASAssignmentFree format text: SECURITY AGREEMENT;ASSIGNOR:ELPIDA MEMORY, INC.;REEL/FRAME:028209/0477Owner name: APPLE INC., CALIFORNIAEffective date: 20120410Nov 25, 2009FPAYFee paymentYear of fee payment: 8Oct 19, 2006ASAssignmentOwner name: ELPIDA MEMORY, INC., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HITACHI, LTD.;REEL/FRAME:018420/0080Effective date: 20060614Nov 29, 2005FPAYFee paymentYear of fee payment: 4Mar 12, 2001ASAssignmentOwner name: HITACHI, LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUNABA, SEIJI;NISHIO, YOJI;NAKAGOME, YOSHINOBU;REEL/FRAME:011613/0343;SIGNING DATES FROM 20001214 TO 20001220Owner name: HITACHI, LTD. 6, KANDA SURUGADAI 4-CHOME, CHIYODA-Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUNABA, SEIJI /AR;REEL/FRAME:011613/0343;SIGNING DATES FROM 20001214 TO 20001220RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services