Source: http://www.google.com/patents/US7652813?ie=ISO-8859-1&dq=7350717
Timestamp: 2014-08-21 12:53:52
Document Index: 476552435

Matched Legal Cases: ['art) 501', 'art 501', 'art 501', 'art 503', 'art 501', 'art 516', 'art 516']

Patent US7652813 - Mirror device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA mirror device comprises: an electrode which is covered with a protective film made of a material containing a semiconductor material and is placed on a substrate; a mirror placed above the electrode; and an electrically conductive hinge placed between the mirror and the electrode, wherein an opening...http://www.google.com/patents/US7652813?utm_source=gb-gplus-sharePatent US7652813 - Mirror deviceAdvanced Patent SearchPublication numberUS7652813 B2Publication typeGrantApplication numberUS 12/220,770Publication dateJan 26, 2010Filing dateJul 28, 2008Priority dateAug 30, 2006Fee statusPaidAlso published asUS8134767, US20080285112, US20100128335Publication number12220770, 220770, US 7652813 B2, US 7652813B2, US-B2-7652813, US7652813 B2, US7652813B2InventorsFusao Ishii, Yoshihiro Maeda, Hirotoshi Ichikawa, Naoya SugimotoOriginal AssigneeSilicon Quest Kabushiki-Kaisha, Olympus CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (26), Referenced by (1), Classifications (5), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMirror deviceUS 7652813 B2Abstract A mirror device comprises: an electrode which is covered with a protective film made of a material containing a semiconductor material and is placed on a substrate; a mirror placed above the electrode; and an electrically conductive hinge placed between the mirror and the electrode, wherein an opening part is formed in a part of the protective film, and the hinge penetrates the protective film in the opening part thereof.
the resistance of the hinge is no more than 500 MΩ.
a light-shield or stiction-preventing coating is deposited on the protective film surface so as to not influence the resistance value of the hinge. Description
CROSS REFERENCE TO RELATED APPLICATIONS This application is Continuation in Part (CIP) Application of a Co-Pending patent application Ser. No. 11/894,248 filed on Aug. 18, 2007 by one of the common Inventors of this patent application. Application Ser. No. 11/894,248 is a Non-provisional application of a Provisional application 60/841,173 filed on Aug. 30, 2006. The Provisional Application 60/839,637 is a Continuation in Part (CIP) Application of a pending U.S. patent application Ser. Nos. 11/121,543 filed on May 4, 2005. The application Ser. No. 11/121,543 is a Continuation in part (CIP) Application of three previously filed Applications. These three Applications are U.S. application Ser. Nos. 10/698,620 filed on Nov. 1, 2003, 10/699,140 filed on Nov. 1, 2003, and 10/699,143 filed on Nov. 1, 2003 by one of the Applicants of this patent application. The disclosures made in these patent applications are hereby incorporated by reference in this patent application.
For controlling the deflectable mirror devices, the PWM applies the data formatted into �bit-planes�. Each bit-plane corresponds to a bit weight of the quantity of light. Thus, when the brightness of each pixel is represented by an n-bit value, each frame of data has the n-bit planes. Then, each bit-plane has a �0� or �1� value for each mirror element. According to the PWM control scheme as described in the preceding paragraphs, each bit-plane is independently loaded and the mirror elements are controlled on the basis of bit-plane values corresponding to the value of each bit within one frame. Specifically, the bit-plane according to the LSB of each pixel is displayed as a �1� time slice. Artifacts are shown between adjacent images pixels when adjacent image pixels are displayed with great differences of quantity of light applying the gray scales having very coarse gray scales. That leads to the degradations of image qualities. The degradations of image qualities are specially pronounced in bright areas of image when there are �bigger gaps� of gray scale, i.e. quantity of light, between adjacent image pixels. The artifacts are caused by a technical limitation that the digitally controlled image display is not controlled by a sufficient number of gray scales, i.e. the levels of the quantity of light. Such problems are particularly caused by the fact that the mirrors are controlled either at the ON or OFF position. The quantity of light of a displayed image is determined by the length of time each mirror is held at the ON position. In order to increase the number of levels of the quantity of light, the switching speed of the ON and OFF positions for the mirror must be increased. Consequently, the digital control signals are required to have a higher number of bits. However, when the switching speed of the mirror deflection is increased, a stronger hinge for supporting the mirror is necessary to sustain a required number of switches of the ON and OFF positions for the mirror deflection. Furthermore, a higher voltage applied to the electrode is required in order to drive the mirrors provided with a strengthened hinge to the ON or OFF position. The higher voltage may exceed twenty volts and may even be as high as thirty volts. The mirrors produced by applying the CMOS technologies probably is not appropriate for operating the mirror at such a high range of voltages, and therefore the DMOS mirror devices may be required. In order to achieve a control of a higher number of gray scales, a more complicated production process and larger device areas are required to produce the DMOS mirror. Conventional mirror are therefore faced with a technical difficulty that in order to produce image display device with smaller size it may be necessary to sacrifice high quality of image display with a higher level of gray scales due to a higher range of the operable voltages.
F = k ′ ⁢ eS 2 ⁢ V 2 2 ⁢ ⁢ h 2 ; ( 1 ) where �S� is the area size of the address electrode 307 a or 307 b, �h� is the distance between the mirror 302 and address electrode 307 a or 307 b, �e� is the permittivity between the mirror 302 and address electrode 307 a or 307 b, �V� is the voltage applied to the address electrode 307 a or 307 b, and �k′� is a correction coefficient.
SUMMARY OF THE INVENTION In consideration of the technical difficulties and limitations encountered by the conventional mirror devices as described above, an aspect of the present invention is to manufacture a mirror device with new manufacturing processes with improved device configurations. The improved manufacturing processes and device configurations are implemented for preventing the adverse effects attributable to the incident light projected to a protective layer on a substrate. According to the present invention, a mirror device comprises: an electrode covered with a protective film composed of a semiconductor disposed on a substrate; a mirror disposed above the electrode; and an electrically conductive hinge placed between the mirror and the electrode, wherein an opening part is formed in a part of the protective film, and the hinge penetrates the protective film in the opening part thereof.
FIG. 5A shows the step 1 to form a wiring 502 of a drive circuit for driving and controlling a mirror (which is described later) in a semiconductor wafer substrate (simply noted as �substrate� hereinafter) 501. A cavity as an opening part (i.e., a cavity or concave part) 501 a is opened from a top surface of the substrate 501 and extends to the upper surface of the wiring 502 preferably composed of aluminum. A first protective layer, i.e., a protective film, 503 is deposited on the parts of the substrate 501 except for the opening part 501 a. The first protective layer 503 is deposited before the opening part 501 a of the substrate 501 is formed. An opening part 503 a on the same area size as the to opening part 501 a is also formed as the side surface of the first protective layer 503. The first protective layer 503 is a layer for preventing the wiring 502 from corroded with hydrogen fluoride (HF) when the hydrogen fluoride (HF) is applied to remove the sacrifice layer as described later.
In step 14A-1, the elastic hinge 511 a supported on the substrate 501 is placed near the center of a wafer, while in step 14A-2, the elastic hinge 511 a is shown as disposed at the end of the substrate 501. With these two different configurations, depending on the CMP condition for the respective wafers the amounts of polishing are different between the center and surrounding. In step 14A-1, the CMP process is performed to polish the fourth sacrifice layer 515 and remove the layers covering over the upper surface of the elastic hinge 511 a. Therefore, a mirror can be deposited and formed on top of the elastic hinge 511 a. In step 14A-2, however, the fourth sacrifice layer 515 at the end of the substrate 501 and the layer 513 covering the elastic hinge 311 a cannot be completely removed. In that case, a mirror as will be described later cannot be formed directly on top of the elastic hinge 511 a. Accordingly, a part of the fourth sacrifice layer 515 covering the upper surface of the elastic hinge 511 a is removed by applying an etching process. Then a semiconductor material 516 possessing electric conductivity is deposited by applying a CVD process that is same as step 14B-1 shown in FIG. 5E to deposit the semiconductor material 516 by using a single crystal silicon (Si) or poly-silicon followed by doping the semiconductor material with boron (B), arsenic (As) or phosphorous (P). Alternately, the semiconductor material 516 may compose of a same material as that used for the elastic hinge 511 a. Then, the semiconductor material 516 is removed by applying an etching process. One or at least two joinder parts such as a convex part, a conductive part and a conductive layer 516 a are formed on the top surface after the fourth sacrifice layer 515 is removed (as shown in step 14B-2). Then, a CMP process is performed to further process by polishing the upper surfaces of the third and fourth sacrifice layers 513 and 515 and the upper surface of the joinder part 516 a. The joinder part 516 a is polished to have a predetermined height (e.g., 0.1 μm) in accordance with the flatness of the third and fourth sacrifice layers 513 and 515.
Furthermore, a light shield layer as an antireflective layer for suppressing the reflection light from the surface of the protective layer 506 may be coated on the surface of the protective layer 506. The antireflective light shield layer may be a coated layer, which does not influence the resistance value of the elastic hinge 511 a. Meanwhile, there is an anti-stiction countermeasure process for preventing a moving part (mainly a mirror) from sticking to the stopper part of an electrode to prevent an operation failure. The anti-stiction member may be provided by laminating a monolayer of perfluorooctyltrichlorosilane (CF3(CF2)5(CH2)2SiCl3; PFOTS), perfluorooctyldimethylchlorosilane (CF3(CF2)5(CH2)2Si(CH3)2Cl; PFODCS), or perfluorodecyldimethylchlorosilane (CF3(CF2)7(CH2)2Si(CH3)2Cl; PFDDCS) on the protective layer 506 and mirror 518. When such a monolayer is further deposited on the surface of the protective layer 506, it is preferable to use a high resistance material similar to that of the protective layer 506 to minimize any impacts on the resistance value of the elastic hinge 511 a. In practice, there is the process for dividing a mirror device into mirror devices of a size to be used by carrying out a dicing process followed by the process for packaging the individually divided mirror devices. A description of them is not provided herein.
FIGS. 7A through 7F are diagrams for describing a mirror element 700. Similar to the mirror element 600 shown in FIGS. 6A and 6B, FIG. 7A shows a mirror element 700 manufactured by the processing steps described above. The substrate 701 supports the mirror element 700 that includes the wirings 702 a, 702 b and 702 c of a drive circuit for driving and controlling a mirror 718; first set of via connectors 705 a, 705 b, 705 c, 705 d and 705 e, which are connected to the wirings 702 a, 702 b and 702 c; and a first insulation layer 719. Note that in a preferred embodiment, the drive circuit includes a dynamic random access memory (DRAM). As shown on the left side of FIG. 7A, The wiring 702 a further includes two of the first set of via connectors 705 c and 705 e, both penetrate through the first insulation layer 719. The wiring 702 b on the right side of FIG. 7A also includes two of the first set of via connectors 705 b and 705 d, both penetrate through the first insulation layer 719. Meanwhile, the wiring 702 c at the center includes one of the first set of via connectors 705 a. As described above, five of the first set of via connectors penetrates through the first insulation layer 719. Note that the number of first set of via connectors may be different between the left and right wirings. Further, the number of first set of via connectors may be more, or less, than the five via connectors as shown. Then, second set of via connectors 720 a, 720 b and 720 c or surface electrodes 721 a and 721 b are formed on top of the first set of via connectors 705 a, 705 b, 705 c, 705 d and 705 e. Specifically, the second Vias 720 a, 720 b and 720 c are respectively formed on top of the first set of via connectors 705 a formed on the wiring 702 s at the center, the first via connectors 705 b and 705 c on one side of two first set of via connectors formed on the wirings 702 b and 702 a on the left and right sides. Meanwhile, surface electrodes 721 a and 721 b are respectively formed on top of the remaining first set of via connectors 705 d and 705 e not supporting any of the second set of via connectors 720 a, 720 b and 720 c thereon. The semiconductor wafer substrate 701 is preferably a silicon substrate supporting an insulation layer 719 thereon. A First protective layer 703 is deposited on top of the first insulation layer 719 and a second protective layer 706 is formed on the first protective layer 703. The wirings 702 a, 702 b and 702 c of the drive circuit are preferably formed by using the aluminum wirings. The first set of via connectors 705 a, 705 b, 705 c, 705 d and 705 e and the second set of via connectors 720 a, 720 b and 720 c are preferably formed by using a material including tungsten and cupper.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5447600Mar 21, 1994Sep 5, 1995Texas InstrumentsReducing sticking by forming protective coatingsUS5497262Jun 7, 1995Mar 5, 1996Texas Instruments IncorporatedSupport posts for micro-mechanical devicesUS5526951Sep 30, 1994Jun 18, 1996Texas Instruments IncorporatedFabrication method for digital micro-mirror devices using low temperature CVDUS5673139Jul 19, 1993Sep 30, 1997Medcom, Inc.Microelectromechanical television scanning device and method for making the sameUS5936760Jun 10, 1997Aug 10, 1999Samsung Electronics Co., Ltd.Deformable mirror device and manufacturing method thereofUS5942054Dec 20, 1996Aug 24, 1999Texas Instruments IncorporatedElectrically conductive amorphous aluminum alloys comprising aluminum, titanium, oxygen; for support member from which another component of the micromachine is suspended, such as a hinge; stress relaxationUS6128121Apr 30, 1999Oct 3, 2000Samsung Electronics Co., Ltd.Deformable mirror device and manufacturing method thereofUS6356378Jul 24, 2000Mar 12, 2002Reflectivity, Inc.Double substrate reflective spatial light modulatorUS6496612 *May 3, 2000Dec 17, 2002Arizona State UniversityElectronically latching micro-magnetic switches and method of operating sameUS6735008Jul 31, 2001May 11, 2004Corning IncorporatedMEMS mirror and method of fabricationUS6861277Oct 2, 2003Mar 1, 2005Hewlett-Packard Development Company, L.P.Method of forming MEMS deviceUS6891655Jan 2, 2003May 10, 2005Micronic Laser Systems AbHigh energy, low energy density, radiation-resistant optics used with micro-electromechanical devicesUS6917459Jun 3, 2003Jul 12, 2005Hewlett-Packard Development Company, L.P.MEMS device and method of forming MEMS deviceUS7022249Feb 13, 2002Apr 4, 2006Teem PhotonicsMethod for making an optical micromirror and micromirror or array of micromirrors obtained by said methodUS7046415Nov 21, 2003May 16, 2006Hewlett-Packard Development Company, L.P.Micro-mirrors with flexure springsUS7068417Jul 28, 2004Jun 27, 2006Miradia Inc.Method and apparatus for a reflective spatial light modulator with a flexible pedestalUS7183618Aug 14, 2004Feb 27, 2007Fusao IshiiHinge for micro-mirror devicesUS7273693Jul 30, 2004Sep 25, 2007Hewlett-Packard Development Company, L.P.Method for forming a planar mirror using a sacrificial oxideUS7375872Jul 23, 2005May 20, 2008Silicon Quest Kabushiki-KaishaMethods and configurations for manufacturing hinges for micro-mirror devicesUS7436573Jul 13, 2005Oct 14, 2008Texas Instruments IncorporatedElectrical connections in microelectromechanical devicesUS20040233503May 20, 2004Nov 25, 2004Fuji Photo Film Co., Ltd.Transmissive spatial light modulator and method of manufacturing the sameUS20050128564Oct 26, 2004Jun 16, 2005Pan Shaoher X.High contrast spatial light modulator and methodUS20050162727Jan 24, 2004Jul 28, 2005Fusao IshiiMicromirrors with support wallsUS20050254116Jul 16, 2005Nov 17, 2005Silicon Quest Kabushiki-KaishaSequence and timing control of writing and rewriting pixel memories for achieving higher number of gray scalesUS20060214257Mar 23, 2006Sep 28, 2006Sumco CorporationProduction method of strained silicon-SOI substrate and strained silicon-SOI substrate produced by sameUS20070097486Jun 5, 2006May 3, 2007Miradia Inc.Projection display system including a high fill ratio silicon spatial light modulator* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8134772 *May 2, 2008Mar 13, 2012Silicon Quest Kabushiki-KaishaMirror device with an anti-stiction layer* Cited by examinerClassifications U.S. Classification359/290International ClassificationG02B26/08, G02B26/00Cooperative ClassificationG02B26/0841European ClassificationG02B26/08M4ELegal EventsDateCodeEventDescriptionJan 24, 2014SULPSurcharge for late paymentJan 24, 2014FPAYFee paymentYear of fee payment: 4Sep 6, 2013REMIMaintenance fee reminder mailedSep 3, 2008ASAssignmentOwner name: OLYMPUS CORPORATION, JAPANOwner name: SILICON QUEST KABUSHIKI-KAISHA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ISHII, FUSAO;MAEDA, YOSHIHIRO;ICHIKAWA, HIROTOSHI;AND OTHERS;REEL/FRAME:021476/0421Effective date: 20080526RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google