Source: https://patents.google.com/patent/KR101230874B1/en
Timestamp: 2019-11-18 09:41:57
Document Index: 193581514

Matched Legal Cases: ['Application No. 11', 'Application No. 11', 'Application No. 11', 'Application No. 11', 'Application No. 09', 'Application No. 09', 'Application No. 11', 'Application No. 10', 'Application No. 10', 'application No. 10', 'Application No. 10', 'Application No. 11']

KR101230874B1 - Nonvolatile memory cell comprising switchable resistor and transistor - Google Patents
Nonvolatile memory cell comprising switchable resistor and transistor Download PDF
KR101230874B1
KR101230874B1 KR1020087003254A KR20087003254A KR101230874B1 KR 101230874 B1 KR101230874 B1 KR 101230874B1 KR 1020087003254 A KR1020087003254 A KR 1020087003254A KR 20087003254 A KR20087003254 A KR 20087003254A KR 101230874 B1 KR101230874 B1 KR 101230874B1
switchable resistor
KR1020087003254A
KR20080027932A (en
2005-07-11 Priority to US11/179,122 priority Critical
2005-07-11 Priority to US11/179,122 priority patent/US7426128B2/en
2006-07-11 Application filed by 쌘디스크 3디 엘엘씨 filed Critical 쌘디스크 3디 엘엘씨
2006-07-11 Priority to PCT/US2006/026897 priority patent/WO2007008902A2/en
2008-03-28 Publication of KR20080027932A publication Critical patent/KR20080027932A/en
2013-02-15 Publication of KR101230874B1 publication Critical patent/KR101230874B1/en
A rewritable nonvolatile memory cell is described that includes a series of thin film transistors and a switchable resistor memory element. The switchable resistor element reduces the resistance upon receiving the set voltage magnitude applied in the first direction and increases the resistance upon receiving the reset voltage magnitude applied in the second direction opposite the first direction. In preferred embodiments, the memory cell is formed of an array, preferably a monolithic three dimensional memory array, in which multiple memory levels are formed on a single substrate. In preferred embodiments, the thin film transistor and the switchable resistor memory element are electrically disposed between parallel data lines and reference lines. Preferably, a selection line extending perpendicular to the data line and the reference line controls the transistor.
Thin film transistors, switchable memory elements, nonvolatile memory cells, data lines, reference lines.
NONVOLATILE MEMORY CELL COMPRISING SWITCHABLE RESISTOR AND TRANSISTOR}
This application discloses U.S. Application No. 11 / 179,095, entitled "Memory Cell Comprising a Thin Flim Three-Terminal Switching Device Having a Metal Source and / or Drain Region" (Representative Document No. MA-158), hereinafter '095. Application; US Application No. 11 / 179,123, entitled "123," filed "Apparatus and Method for Reading an Array of Nonvolatile Memory" (agent document number 023-0040); And US Application No. 11 / 179,077 by Scheuerlein, entitled "Apparatus and Method for Programming an Array of Nonvolatile Memory" (Attorney Docket No. 023-0041), hereinafter referred to '077 Application, all of which are assignees of the present invention. And filed on the same day as it is incorporated herein by reference in its entirety.
The present invention relates to a nonvolatile memory cell.
There are materials with at least two different stable resistance states. Materials of this kind can be switched from a high-resistance state to a low-resistance state by applying a voltage magnitude across the material in the first direction. In order to switch the material from the low-resistance state back to the high-resistance state, the voltage magnitude can be reversed.
Some of these materials may be switched between resistance states at relatively low applied pressures, for example 2 volts or less, and preferably 1 volt or less. These characteristics will allow more of these materials to be used in nonvolatile memory arrays that maintain their memory state even when power is removed from the device. Low-voltage switching is useful for reducing power consumption in devices, but provides reversible voltages and low voltages needed to operate cells containing such materials and during reading or writing of other cells in a large array of cells. Many challenges must be overcome to avoid accidental state changes.
The invention is defined by the following claims, and nothing in this paragraph should be taken as a limitation on these claims. In general, the present invention relates to a nonvolatile memory cell adapted for use in a rewritable memory array.
A first aspect of the invention provides a switchable resistor memory device; And a thin film transistor having a channel region, wherein the switchable resistor memory element is disposed in series with the thin film transistor, wherein the switchable resistor memory element has a set voltage magnitude across the resistive memory element. When the reset voltage magnitude is applied across the switchable resistor memory element, the polarity of the set voltage magnitude is opposite to the polarity of the reset voltage magnitude.
Another aspect of the invention is a switchable resistor memory device; And a transistor comprising a channel region, the switchable resistor memory element and the transistor being arranged in series, the transistor being electrically connected between the data line and the reference line, the data line and the reference line. Both lines extend in a first direction, and when the transistor is on, current flows through the channel region in a second direction, the second direction being substantially perpendicular to the first direction, the switchable resistor memory element being set The resistance is reduced when a voltage magnitude is applied and the resistance is increased when a reset voltage magnitude is applied, and the polarities of the set voltage magnitude and the reset voltage magnitude are reversed.
A related aspect of the invention provides a nonvolatile memory cell formed over a substrate, the memory cell comprising a thin film transistor comprising a channel region, the channel region comprising a deposited semiconductor material, the semiconductor material being silicon, germanium Or a thin film transistor, which is a silicon-germanium alloy; And a switchable resistor memory element, wherein the switchable resistor memory element reduces the resistance when the set voltage magnitude is applied and increases the resistance when the reset voltage magnitude is applied, the polarity of the set voltage magnitude and the reset voltage magnitude being The opposite is true.
Another aspect of the invention is a) a first memory level formed over a substrate, the first memory level comprising a first plurality of memory cells, each first memory cell comprising: i) a field effect transistor; And ii) a switchable resistor memory element, wherein the switchable resistor memory element reduces the resistance when the set voltage magnitude is applied and increases the resistance when the reset voltage magnitude is applied, and the set voltage magnitude and the reset voltage magnitude The polarity of the first memory level is opposite; And b) a second memory level monolithically formed above the first memory level.
Preferred embodiments of the invention include a first plurality of substantially parallel and substantially coplanar lines extending in a first direction; A second plurality of substantially parallel and substantially coplanar lines extending in a second direction; A first plurality of switchable resistor memory elements, each switchable resistor memory element being electrically disposed between one of the first lines and one of the second lines, wherein the first switchable resistor memory elements are formed of a substrate. A first plurality of switchable resistor memory elements, at a first height above; A second plurality of switchable resistor memory elements, wherein the second switchable resistor memory elements comprise a second plurality of switchable resistor memory elements that are at a second height above the first height; Claiming a dimensional memory array, the switchable resistor memory elements reduce the resistance when the set voltage magnitude is applied and increase the resistance when the reset voltage magnitude is applied, and the polarities of the set voltage magnitude and the reset voltage magnitude are reversed.
Another aspect of the invention provides a method of forming, setting and resetting a nonvolatile memory cell and associated conductors, the method comprising: forming a first data line extending in a first direction; Forming a first reference line extending in a first direction; Forming a thin film transistor having a channel region, wherein the channel region is electrically disposed between a first data line and a first reference line; Forming a switchable resistor memory element disposed between the channel region and the data line, the switchable resistor memory element having a first resistor; Forming a first selection line extending in a second direction different from the first direction; Applying a set voltage magnitude across a switchable resistor memory element, wherein after application of the set voltage magnitude, the resistive switching memory element has a second resistance lower than a first resistor; And applying a reset voltage magnitude across the switchable resistor memory element, wherein after application of the reset voltage magnitude, the switchable resistor memory element has a third resistance higher than the second resistor, the set voltage magnitude and The polarity of the reset voltage magnitude is reversed.
Each of the aspects and embodiments of the invention described herein may be used alone or in combination with each other.
1A-1D are cross-sectional views illustrating the decomposition of the formation of a conductive bridge in a switchable resistor memory element for use in a memory cell formed in accordance with a preferred embodiment of the present invention.
2 is a cross-sectional view of a memory level formed in accordance with a preferred embodiment of the present invention.
3A, 3B, and 3C are diagrams of memory levels formed in accordance with another preferred embodiment of the present invention, while FIGS. 3A and 3C are cross-sectional views, while FIG. 3B is a plan view.
4A-4F are cross-sectional views illustrating steps in the formation of a memory level in accordance with a preferred embodiment of the present invention.
5A-5J illustrate steps in the formation of a memory level in accordance with another preferred embodiment of the present invention, while FIGS. 5C and 5J are plan views, while others are cross-sectional views.
Figure 6 is a cross-sectional view showing two memory levels sharing reference lines in accordance with a preferred embodiment of the present invention.
FIG. 7A is a cross-sectional view showing two memory levels sharing data lines according to a preferred embodiment, while FIG. 7B is a cross-sectional view showing two memory levels not sharing data lines according to different embodiments.
It has been noted that some materials can be reversibly switched between one or more stable resistance states, for example between high- and low-resistance states. The transition from the high-resistance state to the low-resistance state will be called a set transition, while the transition from the low-resistance state to a high-resistance state will be called a reset transition. US Application No. 11 / 143,269, filed on June 2, 2005, owned by the assignee of the present invention and referred to herein by Petti, entitled " Rewriteable Memory Cell Comprising a Transistor and Resistance-Switching Material in Series. &Quot; Describes a monolithic three dimensional memory array comprising transistors and resistance-switching memory elements, wherein setting and reset may be performed with the same voltage polarity for the resistance-switching memory element. Petti's resistance-switching memory elements require relatively large voltages (eg 2-3 volts) and currents for set or reset conversion.
For some materials, in contrast to those desirable in Petti, the transition from the high-resistance state to the low-resistance state is affected in one direction by applying a voltage of some magnitude, called the set voltage magnitude, The reverse transition from the low-resistance state to the high resistance state is affected by applying a voltage magnitude, called the reset voltage magnitude, in the opposite direction. Thus, these materials are bi-directional. One such material is amorphous silicon doped with V, Co, Ni, Pd, Fe or Mn (these materials are more fully described in US Pat. No. 5,541,869 to Rose et al.). Another kind of material is described by Ignatiev et al. In US Pat. No. 6,473,332: These are Pr 1 - X Ca X MnO 3 , La 1 - X Ca X MnO 3 (LCMO), LaSrMnO 3 (LSMO), or GdBaCo X X Perovskite materials such as O Y (GBCO). Another option for this variable-resistance material is a carbon-polymer film comprising graphite or carbon black particulates mixed into a plastic polymer, as described, for example, by Jacobson et al. In US Pat. No. 6,072,716.
Preferred materials are described by Campbell et al. In US Application No. 09/943190 and by Campbell in US Application No. 09/941544. This material is doped with chalcogenide glass of the formula A X B Y , where A is group IIIA (B, Al, Ga, In, Ti), group IVA (C, Si, Ge, Sn) of the periodic table. , Pb), at least one element from group VA (N, P, As, Sb, Bi), or group VIIA (F, Cl, Br, I, At), B is S, Se and Te and From among their mixtures. The dopant is selected from among precious metals or transition metals including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn or Ni. As will be described, in the present invention, this chalcogenide glass (non-crystalline, amorphous chalcogenide) is formed in a memory cell adjacent to a reservoir of mobile metal ions. Any other solid electrolyte material can be used in place of the chalcogenide glass.
Figure 1a shows a switchable resistor memory element 8 comprising a chalcogenide layer 10 positioned between two electrodes. The chalcogenide layer 10 is amorphous and high-resistance as formed so that the switchable resistor memory element 8 is in a high-resistance state. Electrode 12 is a source of mobile metal ions, preferably silver. The electrode 14 is any conductor that does not readily provide mobile metal ions, for example tungsten, aluminum, nickel, platinum, or a heavily doped semiconductor material.
Referring to FIG. 1B, when positive voltage is applied to the silver electrode 12 and negative voltage is applied to the electrode 14, electrons flow toward the electrode 12, while silver ions (shown as small circles) ) Moves from electrode 12 to chalcogenide layer 10. As shown in FIG. 1C, silver forms a conductive bridge across the chalcogenide layer 10, and the switchable resistor memory element 8 is in a low-resistance state. The memory cell comprising the switchable resistor memory element 8 has been set or converted to a low-resistance state. The resistance difference between the low- and high-resistance of the switchable resistor memory element 8 can be easily and repeatedly detected, in which way the memory state (eg data "0" or data "1") is stored. And can be read.
Referring to FIG. 1D, to reset the memory cell, the voltage is inverted. A negative voltage is applied to the electrode 12 and a positive voltage is applied to the electrode 14. Electrons flow toward the electrode 14, silver in the chalcogenide layer 12 is oxidized, and silver ions move back into the electrode 12, destroying the conductive bridge and once again chalcogenide layer 12 Ensure high resistance. This set and reset cycle can be repeated many times.
It is important to carefully control the circuit conditions that each cell undergoes during read, set, and reset. During the set, if too little current is used to form the conductive bridge, the cell will not be highly conductive and the difference between the programmed and unprogrammed states will be difficult to detect. If too much current is applied, the conductive bridge formed over the chalcogenide layer becomes conductive, so that when a reset is attempted, it is conductive to allow sufficient voltage to allow the silver in the bridge to oxidize and move back to the electrode 12. The resistance of the bridge is too low (current is too high).
During the read operation, a voltage must be applied across the cell to detect the current flow and thus the resistance of the switchable resistor memory element and to determine the corresponding data state of the memory cell from the resistor. However, if too high a voltage is applied, there is a risk that an undesirable high-to-low-resistance or low-to-high-resistance conversion is unintentionally triggered.
When many cells, including such switchable resistor memory elements, are included in a large memory array, control of the voltages experienced by each cell becomes more difficult. The present invention describes a nonvolatile memory cell that stores a data state in a state of a switchable resistor memory element, wherein the switchable resistor memory element reduces resistance when a set voltage magnitude is applied and resists when a reset voltage magnitude is applied. Increases the polarity of the set voltage and the reset voltage. The memory cell of the present invention is adapted to be formed in large arrays, allowing more accurate control of the voltage conditions for each cell.
Large arrays of memory cells may be disturbed when a voltage is applied to neighboring cells, for example, cells on shared conductors. See, for example, US Patent Application No. 11 / 125,939, filed May 9, 2005, incorporated herein by reference, and entitled "Rewriteable Memory Cell Comprising a Diode and a Resistance-Switching Material". In arrays, the resistance-switching material is paired with a diode to provide electrical isolation. Diodes are not the most useful choice for use with materials such as those described herein. The resistance-switching materials of the present invention require bi-directional voltage and current, but the diode is a uni-directional device. In addition, the relatively low switching voltages of the resistance-switching materials used in the present invention are difficult to achieve given the relatively high turn-on voltages associated with conventional diodes.
In the present invention, the bidirectional switchable resistor memory element is paired with a MOSFET. In preferred embodiments, the MOSFET is a thin film transistor adapted to be formed in a monolithic three dimensional memory array, forming a very compact memory device. Accidental disturbances of memory states stored during normal operation of the memory, as described in more detail in the related '123 application (agent document number 023-0040) and' 077 application (agent document number 023-0041) filed with the same application herein The bias polarities for read, set, and reset operations are selected to avoid the use of bidirectional switching resistor elements that switch the resistive state to a very low voltage in the TFT memory array. In an exemplary embodiment, the set bias is positive and the reset and read bias are negative.
Embodiments of two groups will be described. Referring to Fig. 2, the first embodiment includes memory cells in a TFT array each having a transistor in series and a switchable resistor memory element. It will be understood that many other embodiments may exist within the scope of the present invention. These embodiments are provided for clarity and are not intended to be limiting. The substantially parallel rails 20 (shown in cross section and extending out of the page) comprise a plurality of line sets 21, each line set 21 having two data lines 22 ( For example, it consists of 22a and 22b and one reference line 24, which is directly adjacent to the two data lines 22a and 22b or the two data lines 22a and 22b). Substantially parallel select lines 26 are above the rails 20 and preferably extend vertically from the rails. Select lines 26 extend with gate dielectric layer 28 and channel layer 30. Transistors are formed between each adjacent data line and reference line pair. The transistor 34 includes a channel region 41 between the source region 40 and the drain region 42. Each select line 26 controls the transistors with which it is associated. Switchable resistor memory element 36 is disposed between channel region 41 and data line 22b. In this embodiment, adjacent transistors share a reference line; For example, transistor 38 shares reference line 24 with transistor 34. Transistor 38 also includes a resistor memory element 36 that is switchable between channel region 41 and data line 22a. There is no transistor between adjacent data lines 22b and 22c. As will be described, in preferred embodiments, the leakage path between the data lines 22b and 22c may be doped by the channel layer 30 in this region or by using a channel trim masking step to this section of the channel layer 30. By removing it.
3A is a cross sectional view of the second embodiment, in which the transistors are oriented substantially vertically. Multiple substantially parallel data lines 50 are formed. Semiconductor pillars 52 are formed over one of the data lines 50, respectively. Each filler 52 includes heavily doped regions 54 and 58 that serve as drain and source regions, and lightly doped or undoped region 56 that serves as a channel region. In an alternate embodiment, region 56 may be a stack of multiple thin doped semiconductor regions separated by multiple thin tunneling dielectric layers. Such a stack is desirable for very low leakage vertical TFT switches. Gate electrode 60 surrounds each filler 52.
FIG. 3B shows the cells of FIG. 3A seen from above. In a repetitive pattern, the pitch is the distance between the feature and the same feature that appears next. For example, the pitch of pillars 52 is the distance between the center of one pillar and the center of an adjacent pillar. In one direction, the filters 52 have a first pitch P 1 , while in the other direction, the pillars 52 have a larger pitch P 2 ; For example, P 2 may be 1.5 times P 1 . (Feature size is the width of the smallest feature or gap formed by photolithography in the device. In other ways, pitch P 1 can be twice the pitch size, while pitch P 2 is the size of the feature size. Three times.) In the direction with the smaller pitch P 1 shown in Fig. 3A, the gate electrodes 60 of adjacent memory cells are merged to form a single select line 62. In the direction with the larger pitch P 2 , the gate electrodes 60 of adjacent cells are not merged and adjacent select lines 62 are isolated. Fig. 3A shows the structure of the cross section along the line X-X 'of Fig. 3B, while Fig. 3C shows the structure of the cross section along the line Y-Y' of Fig. 3B. For ease of reading, reference lines 64 are omitted from FIG. 3B.
3A and 3C, reference lines 64, preferably parallel to the data lines 50, are formed over the pillars 52, so that each pillar 52 is connected to the data lines 50. In FIG. Is disposed vertically between one of and one of the reference lines 54. Switchable resistor memory element 66 is formed in each memory cell, for example, between source region 58 and reference line 64. Alternatively, a switchable memory element may be formed between the drain region 54 and the data line 50.
Each memory cell of this embodiment has a vertically oriented transistor having a polycrystalline channel region and a switchable resistor memory element, both of which are electrically in series. In contrast, in the embodiment of Figure 2, the overall channel direction is lateral rather than vertical.
Both of these embodiments include a switchable resistor memory element; And a thin film transistor having a channel region, wherein the switchable resistor memory element is disposed in series with the thin film transistor, the switchable resistor memory element having a set voltage magnitude across the resistive memory element. Reduces the resistance when is applied, the switchable resistive memory element increases the resistance when a reset voltage magnitude is applied across the switchable resistive memory element itself, and the polarity of the set voltage magnitude is opposite to the polarity of the reset voltage magnitude. to be. The transistor and the switchable resistor memory element are electrically disposed between the data line and the reference line, the reference line being substantially parallel to the data line. In particular, the channel region of the transistor is electrically disposed between the data line and the reference line. In both embodiments, the select line includes the gate electrodes of the transistors that it selects.
For reasons to be described herein, and in related applications, it is desirable for the thin film transistor of the present invention to have a low threshold voltage and a high current. Thus, in preferred embodiments, the channel region of each transistor may be formed of silicon, but the channel region is germanium or silicon-germanium alloy.
US Patent No. 6,881,994 to Lee et al., Entitled "Monolithic Three Dimensional Array of Charge Stroage Devices Containing a Planarized Surface"; And US Patent Application No. by Walker et al., Owned by the assignee of the present invention and incorporated herein by reference, filed December 31, 2002, entitled "Method for Fabricating Programmable Memory Array Structures Incorporating Series-Connected Transistor Strings." 10 / 335,089 describes monolithic three dimensional memory arrays in which memory cells comprise transistors.
Detailed examples will be provided, one illustrating the fabrication of a monolithic three dimensional memory array formed in accordance with the embodiment of FIG. 2, and the other a monolithic three dimensional memory formed in accordance with the embodiment of FIGS. 3A-3C. The fabrication of the array is described. The fabrication techniques described in Lee et al., Walker et al., And Petti will prove useful during the fabrication of memory arrays according to the present invention. For simplicity, not all manufacturing details from these applications will be included in the description herein, but the content of these integrated patents and applications will not be intended to be excluded.
Lateral Transistor Example: Fabrication
Referring to FIG. 4A, formation of the memory begins with the substrate 100. The substrate 100 may be any semiconductor as known in the art, such as IV-IV compounds, III-V compounds, II-VII compounds, such as monocrystalline silicon, silicon-germanium or silicon-germanium-carbon. Substrate, epitaxial layers on such substrates, or any other semiconductor material. The substrate may include integrated circuits fabricated therein.
An insulating layer 102 is formed over the substrate 100. Insulating layer 102 may be silicon oxide, silicon nitride, a high-dielectric film, a Si-C-O-H film, or any other suitable insulating material.
Conductive material 104 is deposited on insulating layer 102. Conductive material 104 consists of any suitable conductive material or stack of materials. At least the top of the conductive material 104 is preferably strongly doped silicon. In preferred embodiments, the conductive material 104 is a layer of in-situ doped silicon, preferably silicon doped strongly with n-type dopants such as phosphorus. Conductive material 104 may be, for example, any suitable thickness between about 100 and about 250 nm.
Next, a reservoir 106 of mobile metal ions is deposited. This layer is between about 1 and about 100 nm thick, preferably between about 10 and about 30 nm thick. Ion reservoir 106 is any material capable of providing suitable mobile metal ions, preferably silver ions.
Ion conductor layer 108 is then deposited. Layer 108 is preferably a solid electrolyte material comprising a chalcogenide glass of formula A X B Y , where A is group IIIA (B, Al, Ga, In, Ti), group IVA (C, Si, Ge, Sn, Pb), group VA (N, P, As, Sb, Bi), or at least one element from group VIIA (F, Cl, Br, I, At), B is S , Se and Te and mixtures thereof. The dopant is selected from among precious metals or transition metals including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn or Ni. Chalcogenide layer 108 is preferably formed in an amorphous state. Layer 108 is in contact with ion reservoir 106.
Note that some chalcogenide memories work by undergoing state changes between the amorphous and crystalline states. As described, the memory cells of embodiments of the present invention have different mechanisms, formation and disassembly of the conductive bridge and should not undergo a phase change. Thus, chalcogenides that enter the crystalline state more difficult may be desirable.
In other embodiments, other materials may be used instead of chalcogenide that may assist in the formation and decomposition of the conductive bridge. For simplicity, this description will refer to layer 108 as a chalcogenide layer, but it will be understood that other materials may be used instead.
The top electrode 110 deposited next is any suitable electrode material. This should be a material that does not readily provide mobile metal ions to the chalcogenide layer 108 under the electric field. The upper electrode 110 may be, for example, tungsten, nickel, molybdenum, platinum, metal silicides, conductive nitrides such as titanium nitride, or strongly doped polysilicon. Preferred are electrodes that can serve as a diffusion barrier between the chalcogenide layer 108 and the channel layer to be formed now, such as titanium nitride. The upper electrode 110 is preferably between about 10 and about 50 nm thick.
If the top electrode 110 is not formed of strongly doped n-type polysilicon, a thin layer 112 of strongly doped n-type (N +) polysilicon is deposited next. This layer may be in-situ doped or doped through ion implantation. In addition to the layers described, other suitable barrier layers, adhesive layers, or etch stop layers may be included.
Next, conductive material 104, ion reservoir 106, chalcogenide layer 108, top electrode 110, and N + layer 112 are patterned and multiple substantially parallel, substantially coplanar. Etched into lines 200.
Dielectric fill 114, for example HDP oxide, is deposited over and between lines 200 to fill the gaps therebetween. Overfill of dielectric filler 114 is removed to expose N + layer 112 at the tops of lines 200 and, for example, to chemical-mechanical planarization (CMP) or etchback. The planarization step by exposing the N + layers 112 and the dielectric filler 114 together at a substantially planar surface. The structure at this point is shown in Fig. 4A.
Next, referring to FIG. 4B, a masking step is performed to expose all the third lines between the lines 200, only the N + layer 112, the top electrode 110, the chalcogene from the exposed lines. The nitride layer 108 and the ion reservoir 106 are etched away. The exposed lines will be reference lines in the completed array. As shown, layers 112, 110, 108, and 106 are maintained on the other two lines of the three lines, which will be the data lines in the completed array.
Referring to FIG. 4C, a channel layer 116 is then deposited. This layer is preferably a semiconductor material lightly doped with a p-type dopant, preferably between about 10 and about 50 nm thick. In preferred embodiments, channel layer 116 is between about 10 and about 20 nm thick. The channel layer 116 is a semiconductor material and may be silicon, germanium, or silicon, germanium, or an alloy of silicon and germanium. In preferred embodiments, the channel layer 116 is amorphous as deposited and will crystallize at the next annealing step or during subsequent thermal processing, and after recrystallization, it will be polycrystalline. Methods of maximizing grain size in deposited semiconductor channel layers are both produced by Gu, entitled " Large Grain Size Polysilicon Films Formed by Nuclei-Induced Solid Phase Crystallization ", both owned by the assignee of the present invention and referenced herein. US Patent No. 6,713,371; The name is described in US Patent Application No. 10 / 681,509 by Gu et al., "Uniform Seeding to Control Grain and Defect Density of Crystallized Silicon for Use in Sub-Micron Thin Film Transistor".
During subsequent thermal steps, the n-type dopant atoms will diffuse up from the N + layer 112 and the N + material 104 to form N + regions in the channel layer 116, which regions are source and drain in the finished device. Will act as zones.
Channel layer 116 is conformal according to the topography on which it is deposited. Then, on top of the reference lines R 1 and R 2 , where the layers 112, 110, 108, and 106 have been removed, the channel layer 116 has a wavy shape. This wavy shape increases the effective channel length, which can improve device performance at very small dimensions.
In a completed array, transistors will be formed between adjacent data lines and reference lines, but no device is formed between adjacent data lines, for example, between data line D 2 and data line D 3 . Should not. Leakage between these lines can be prevented by an ion implantation step and a masking step of injecting a P-type dopant into the channel layer between the data lines D 2 and D 3 , as shown in FIG. 4C.
In the alternative embodiment shown in FIG. 4F, the channel layer 116 may be selectively removed in the region 117 between the data lines D 2 and D 3 using conventional patterning and etching techniques.
4D, a gate dielectric 120 is next formed. If channel layer 116 is silicon or a silicon rich alloy, gate dielectric 120 may be a layer of silicon dioxide grown by an oxidation process such as thermal or plasma oxidation. In other embodiments, this layer is a deposited dielectric, for example silicon dioxide or higher-K dielectric materials such as Si 3 N 4 , Al 2 O 3 , HfO 2 , HfSiON, or Ta 2 O 5 . Gate dielectric layer 120 is preferably between about 2 and about 10 nm. Higher-K dielectric gate dielectrics may be thicker than gate dielectric formed of silicon dioxide.
Next, word line material 122 is deposited. The word line material 122 may be any conductive material, including tungsten, aluminum, or a heavily doped semiconductor material, such as polysilicon. In some embodiments, the word line material 122 includes a first layer of n-type polysilicon, a thin layer of titanium, a thin layer of titanium nitride, and a second layer of n-type polysilicon. Titanium and titanium nitride will react with the surrounding polysilicon to form a titanium silicide layer that provides lower resistance.
Finally, patterning and etching steps are performed to form word lines 300. This etching continues through gate dielectric layer 120, channel layer 116, and through N + layer 112 and top electrode 110. In preferred embodiments, the etching also continues through the chalcogenide layer 108. Word lines 300 should be completely isolated; Chalcogenide layer 108 is typically high-resistance, but in very large arrays, the low-conductive paths provided by the remaining chalcogenide material between adjacent word lines may not be useful. Ion reservoir 106 is also selectively etched. FIG. 4E shows a 90 degree structure along the line L-L 'for the diagram shown in FIG. 4D after the word line etching is completed.
Dielectric material 124 is deposited over and between word lines 300, filling gaps therebetween. For example, the planarization step by CMP forms a substantially planar surface on the interlevel dielectric formed from dielectric material 124. The first memory level has been formed. Additional memory levels can be formed above this level.
Many variations on the embodiments described herein can be envisioned. In some embodiments, chalcogenide layer 108 is replaced with amorphous silicon doped with V, Co, Ni, Pd, Fe or Mn and sandwiched between appropriate electrode layers. In other embodiments, the chalcogenide layer 108 is replaced with one of the previously named perovskite materials. Any suitable electrode materials can be used with perovskite materials such as aluminum, titanium, vanadium, manganese, copper, niobium, zirconium, silver, tin, indium, hafnium, tantalum, or tungsten. In another embodiment, carbon polymer may replace the chalcogenide layer 108.
In the embodiment just described, note that the data line and the reference line are below the channel region and are substantially parallel. In this embodiment, in order to convert the switchable resistor memory element of the memory cell from the high-resistance state to the low-resistance state, a first voltage is applied to the data line and a second voltage is applied to the reference line and the first The voltage is higher than the second voltage. Conversely, in order to convert the switchable resistor memory element of the memory cell from a low-resistance state to a high-resistance state, a third voltage is applied to the data line and a fourth voltage is applied to the reference line, the fourth voltage being equal to the fourth voltage. Higher than 3 voltages.
Vertical Transistor Example: Fabrication
Referring to FIG. 5A, as in the previous embodiment, fabrication begins through a suitable substrate 100 and insulating layer 102. As described above, the substrate 100 may include an integrated circuit manufactured therein.
Data lines 400 are formed over the substrate 100 and insulator 102. An adhesive layer 404 may be included between the insulating layer 102 and the conductive layer 406 to assist in bonding the conductive layer 406. The preferred material for the adhesive layer 404 is titanium nitride, although other materials may be used, and this layer may be omitted. The adhesive layer 404 may be deposited by any conventional method, for example by sputtering.
The thickness of the adhesive layer 404 may range from about 20 to about 500 angstroms, preferably in the range of about 10 and about 40 nm, most preferably about 20 nm.
The next layer to be deposited is the conductive layer 406. The conductive layer 406 may comprise any conductive material known in the art, such as doped semiconductor material, metals such as turnsten, or conductive metal silicides, or aluminum. The thickness of the conductive layer 406 may be, in part, depending on the desired sheet resistance, and therefore may be any thickness that provides the desired sheet resistance. In one embodiment, the thickness of the conductive layer 406 may range from about 50 to about 300 nm, preferably between about 100 and about 200 nm, most preferably 120 nm.
Preferably another layer 410 of titanium nitride is deposited on the conductive layer 406. This layer may have a thickness comparable to the thickness of layer 404.
Once all the layers that will form the data lines 400 have been deposited, the layers are patterned and etched using any suitable masking and etching process, so that they are substantially parallel and substantially coplanar as shown in cross section in FIG. 5A. Will form data lines 400.
Next, a dielectric material 408 is deposited over the data lines 400 and between the data lines. Dielectric material 408 may be any known electrically insulating material, such as HDP oxide.
Finally, excess dielectric material 408 on top of data lines 400 is removed, exposing the tops of data lines 400 separated by dielectric material 408, leaving a substantially planar surface. . The resulting structure is shown in Fig. 5A. This removal of the dielectric overfill to form a planar surface can be performed by any process known in the art, such as etch back or CMP.
The width of the data lines 400 may be as desired. In preferred embodiments, the data lines 200 may have a width between about 20 and about 250 nm, preferably between about 45 and about 90 nm. In preferred embodiments, the gaps between the data lines 400 have a width substantially the same as the data lines 400, although they may be larger or smaller. In a preferred embodiment, the pitch of the data lines 200 is between about 40 nm and about 500 nm, preferably between about 90 nm and about 180 nm.
Next, referring to FIG. 5B, vertical pillars will be formed over the completed data lines 400. (In order to save space, the substrate 100 is omitted in FIG. 5B and subsequent figures; the presence of the substrate must be assumed). A semiconductor material to be patterned into the pillars is deposited. The semiconductor material may be silicon, germanium or silicon, germanium or an alloy of silicon and germanium.
In preferred embodiments, the semiconductor filler comprises a heavily doped region below the first conductivity type, a lightly doped or undoped region intermediate the second conductivity type, and a heavily doped region above the first conductivity type. do.
In this example, the bottom heavily doped region 412 is heavily doped n-type germanium. In the most preferred embodiment, the heavily doped region 412 is deposited and alternatively, such as phosphorus by any conventional method, preferably in-drilling doping, although it is alternatively possible through some other method such as ion implantation. doped with n-type dopant. This layer is preferably between about 10 and about 80 nm, most preferably between about 20 and about 30 nm. The bottom heavily doped region 412 will act as the source or drain region for the transistor to be formed.
Next, germanium is deposited which forms the remainder of the filler, ie the regions 414 and 416. The lightly doped region 414 will preferably be between about 60 and about 200 nm thick, preferably between about 90 and about 150 nm thick. The upper heavily doped region 416 should be between about 10 and about 50 nm thick, preferably between about 20 and about 30 nm thick. Thus, between 70 and 200 germanium must be deposited to complete the thickness required for the filler. This germanium layer 414 is preferably lightly doped p-type germanium and is preferably in-situ doped. The channel region of the transistor to be formed will be in the germanium layer 414.
In some embodiments, a subsequent planarization step removes some germanium, in which case an extra thickness is deposited. If the planarization step is performed using a conventional CMP method, the thickness of about 800 ohms can be lost (this is average; the amount is variable across the wafer. Methods and slurry used during CMP Germanium loss may be more or less.) Only about 40 nm or less germanium can be removed if the planarization step is performed by an etch back method.
In a preferred embodiment, the top heavily doped n-type region 416 is formed at this point by ion implantation. The heavily doped region 416, which will serve as a source / drain region for the transistor to be formed, is preferably between about 20 and about 30 nm thick.
Next, a layer 421 of the reservoir of mobile metal ions is deposited. This layer is between about 1 and about 100 nm thick, preferably between about 10 and about 30 nm thick. Ion reservoir 421 is any material capable of providing suitable mobile metal ions, preferably silver ions.
An ion conductor (corresponding to chalcogenide layer 108 in the previous embodiment), preferably a layer 418 of chalcogenide, is deposited on ion reservoir 421 and is in contact with the ion reservoir. The thickness and composition of layer 418 may be as described in the previous embodiment. For simplicity, this discussion will refer to the ion conductor layer 418 as the chalcogenide layer, but it will be understood that other materials may be used instead.
Next, an electrode layer 423 is deposited on the chalcogenide layer 418. Layer 423 is one of the materials described for use in the upper electrode layer of the previous embodiment.
Next, a pattern and an etching step are performed to etch the pillars 500. Layers 423, 418, 421, 416, 414, and 412 are etched in this etching step.
The pillars 500 may be formed using any suitable masking and etching processes. For example, photoresist is deposited, patterned using standard photolithography techniques, etched and then the photoresist is removed. Alternatively, a hard mask of some other material, for example silicon dioxide, is formed on top of the stack of semiconductor layers, with a bottom antireflective coating (BARC) on top, and then patterned and etched. Similarly, a dielectric antireflective coating (DARC) can be used as the hard mask.
After etching, the pillars 500 may have a lower heavily doped n-type region 412, a middle weakly doped p-type region 414, an upper heavily doped n-type region 416, an ion A reservoir 421, a chalcogenide layer 418, and an upper electrode 423. In some embodiments, other layers may be included, for example barrier layers.
US Application No. 10/728436, filed December 5, 2003, filed December 5, 2003, owned by the assignee of the present invention and referred to herein by " Photomask Features with Interior Nonprinting Window Using Alternating Phase Shifting "; Or photolithography techniques described in US application No. 10/815312 filed by Chen, filed April 1, 2004, entitled "Photomask Features with Chromeless Nonprinting Phase Shifting Window", are useful in forming a memory array according to the present invention. It can be used to perform any photolithography step used in.
The pillars 500 are preferably about the same width as the data lines 400. Referring to FIG. 5C, which shows the structure seen from above, the pillars 500 have a first pitch P 3 in one direction and a second larger pitch P 4 in the other direction. (The pillars 500 are shown as substantially cylindrical in Fig. 5C. At small feature sizes, the photolithography process will tend to round corners; therefore, independently patterned pillars will tend to be cylindrical. 5A and 5B show pillars at a smaller pitch P 3 , along the line Z-Z ′ of FIG. 5C. The pitch P 3 measured in the direction perpendicular to the data lines 400 is approximately equal to the pitch of the data lines 400 such that each filler 500 is on top of one of the data lines 400. It should be (preferably between about 180 and 360 nm). Some misalignment can be tolerated. The measured pitch P 4 parallel to the data lines 400 should be larger than the pitch P 3 , although it may be larger or smaller if desired, and should preferably be about 1.5 times P 3 . .
Referring to FIG. 5D, a thin gate dielectric layer 426 is conformally deposited over the pillars 500 and surrounds each filter 500 and contacts each filler. Gate dielectric layer 426 may be any suitable material, for example silicon dioxide, and may have any suitable thickness, for example, between about 20 and about 80 angstroms, preferably about 50 angstroms.
Next, a gate material layer 428 is deposited over the gate dielectric layer 426, over the first pillars 500, and between the first pillars 500. Gate material layer 428 is preferably tantalum nitride, although any other suitable conductive material may be used instead, for example, heavily doped silicon or metal.
FIG. 5E shows the structure of FIG. 5D seen from 90 degrees, along line W-W 'of FIG. 5C. The thickness of tantalum nitride layer 428 is selected such that the sidewalls merge in one direction (with smaller pitch P 3 ) rather than in the other direction (with larger pitch P 4 ). For example, suppose pitch P 3 is 180 nm and pitch P 4 is 270 nm. The width of the pillars 500 in the direction of the smaller pitch P 3 is about 90 nm, and the gap between them is about 90 nm; Also assume that the gap between the pillars 300 in the P 4 pitch direction is 180 nm. A tantalum nitride layer 428 of about 45 nm thick fills only gaps in the P 3 pitch direction (shown in FIG. 5D) and fills a gap G of 90 nm in the P 4 pitch direction (shown in FIG. 5E). Will be left. Preferably, the thickness of tantalum nitride layer 428 is between one half of the width of pillars 500 and three quarters of the width of pillars 500. Thus, when the pillars 500 have a width of about 90 nm, the preferred thickness of the tantalum nitride layer 428 is between about 45 nm and about 72 nm, preferably about 60 nm. A thickness of 60 nm will leave a gap of about 60 nm in the P 4 pitch direction.
Referring to Fig. 5F showing the structure in the P 3 pitch direction and Fig. 5G showing the structure in the P 4 pitch direction, the tantalum nitride layer 428 is recessed and the selection lines 430 are removed. Etching is performed to isolate. Select lines 430 are made of tantalum nitride layer 428 merged in the P 3 pitch direction (FIG. 5F), but must be completely separated in the P 4 pitch direction (FIG. 5G). The selection lines 430 are substantially parallel and substantially coplanar.
This etching should be a timed etch and controlled carefully. After etching is complete, tantalum nitride layer 428 is preferably at least 50 nm below the top of the top electrode 423. This 50 nm gap will be filled with a dielectric and will serve to isolate select lines 430 from the overlying conductors to be formed. However, tantalum nitride layer 428 should not be etched unless it reaches the bottom edge of strongly doped region 416, which will be the source / drain region of the transistor.
Next, referring to FIGS. 5H and 5I, dielectric material 408 is deposited over and between fillers 500 and tantalum nitride layer 428, filling gaps therebetween. Dielectric material 408 may be any known electrically insulating material, such as HDP oxide.
Next, the dielectric material on top of the pillars 500 is removed, exposing the top electrodes 423 separated by the dielectric material 138. Gate dielectric layer 426 is simultaneously removed from top electrode 423. Such removal and planarization of the dielectric overfill may be performed by any process known in the art such as CMP or etch back.
Substantially parallel, substantially coplanar reference lines 600 may be formed by any suitable method. Reference lines 600 may be formed using the methods used to form data lines 400: deposit tantalum nitride layer 432, deposit conductive layer 434, and tantalum nitride layer ( 436 is deposited, patterned and etched to form reference lines 600. Reference lines 600 are preferably parallel to data lines 400, although in alternative embodiments the reference lines 600 may be formed perpendicular to data lines 400 if desired. Do. Dielectric material (not shown) is deposited over and between the reference lines 600. Alternatively, reference lines 600 may be formed by a damascene method. Reference lines 600 preferably have approximately the same width as data lines 400. The pitch of the reference lines should be the pitch P 3 such that each filler 500 is vertically disposed between one of the data lines 400 and one of the reference lines 600. Some misalignment can be tolerated.
Alternatively, reference lines 600, including, for example, copper, may be formed by the damascene method. When reference lines 600 are formed by a damascene method, the reference lines deposit a dielectric material; Etching trenches substantially parallel in the dielectric material; Depositing a conductive material on the dielectric material to fill the trenches; It is formed by exposing the dielectric material and planarizing to form reference lines 600.
Fig. 5J shows the structure seen from the top. The diagram of FIG. 5H follows the line Z-Z 'and the diagram of FIG. 5i follows the line W-W'.
Note that in this embodiment, unlike the previous embodiment, one of the data line and the reference line is below the channel region and the other is above the channel region.
Formed in Figures 5H and 5I is the first memory level. In each memory cell, tantalum nitride layer 428 serves as a gate electrode. When a threshold voltage is applied to the gate electrode 428, a vertical conductive channel is formed on the surface of the channel region 414, and a current may flow between the source / drain regions 412 and 416. Each gate electrode is part of one of the select lines 430. Ion reservoir 421, chalcogenide layer 418, and top electrode 423 serve as a switchable resistor memory device. Using the described methods, an additional memory level can be formed above this memory level.
For example, referring to FIG. 6, after the tops of the reference lines 600 are exposed by the planarization step, a second surrounded by the gate electrode material merged to form the second selection lines 750. Fillers 700 may be formed on the reference lines 600, and second data lines 800 may be formed on the second pillars 700. 6 shows two memory levels sharing reference lines 600.
Additional memory levels may be formed over the first two memory levels shown in FIG. Data lines can also be shared or separated. 7A shows four memory levels; Memory levels M 1 and M 2 share reference lines 610, memory levels M 2 and M 3 share data lines 710, memory levels M 3 and M 4 ) shares reference lines 810. FIG. 7B shows four memory levels where reference lines 610 and 810 are shared, but data lines 710 and 712 are not shared between memory levels M 2 and M 3 . The arrangement of FIG. 7A requires fewer masking steps and may therefore be desirable.
In the most preferred embodiments, a control circuit is formed in the substrate under the memory, and electrical connections from the ends of the array's data lines, reference lines and select lines to this circuit should be made. A useful way to make these connections while minimizing the use of a substrate area is a file entitled “Three-Dimensional Memory Device, filed March 31, 2003, both of which is owned by the assignee of the present invention and referenced herein. US Patent Application No. 10 / 403,752 by Scheuerlein et al., Incorporating Segmented Bit Line Momory Array; And US Patent No. 6,879,505 to Scheuerlein et al., Entitled " Word line arrangement having multi-layer word line segments for three-dimensional memory array. &Quot; The arrangement of FIG. 7B which requires more masking steps may use the techniques described by Scheuerlein et al. And may therefore be desirable.
Both described embodiments include a switchable resistor memory element; And a nonvolatile memory cell including a transistor including a channel region, wherein the switchable resistor memory element and the transistor are arranged in series, the transistor being electrically connected between the data line and the reference line, and the data line and the reference line. Both lines extend in a first direction, and when the transistor is on, current flows through the channel region in a second direction, the second direction being substantially perpendicular to the first direction, the switchable resistor memory element being set When the voltage magnitude is applied, the resistance is reduced and the resistance is increased when the reset voltage magnitude is applied, and the polarity of the set voltage magnitude and the reset voltage magnitude is reversed.
In the memory arrays of the present invention, the data lines and the reference lines are parallel, preferably perpendicular to the select lines. This is useful because many cells can be selected by the select line. All of these cells have some current activity, and if the reference line is parallel to this select line, all these currents will pass through the reference line, and the I-R drop will be multiplied several times.
In preferred embodiments of the present invention, the data line and the reference line are perpendicular to the direction of current flow through the channel of the transistor. DRAM devices having a similar configuration are described by Scheuerlein, both filed June 20, 2005 and both of which are incorporated herein by the name "Floating Body Memory Cell System and Method of Manufacture" (Agent No. MAT1P001). US Patent Application No. 11 / 157,293; And US patent application Ser. No. 11 / 157,317 by Scheuerlein, entitled "Volatile Memory Cell Two-Pass Writing Method" (agent document number MAT1P003).
The resistance across the thin film transistor of the present invention is important for device performance. For reasons that are more fully described in the related applications filed as same herein, it is desirable that the resistance of the thin film transistor be comparable to the low-resistance state of the switchable resistor memory element. In the memory cell of the present invention, the resistance of the channel region is reduced by the use of germanium or silicon-germanium alloys. Similarly, using very thin gate dielectrics and high-K dielectric gate materials helps keep the transistor's resistance low.
The set voltage magnitude and the reset voltage magnitude used in the present invention are generally about 2 volts or less, preferably about 1 volt or less.
A monolithic three dimensional memory array is one in which multiple memory levels are formed on a single substrate, such as a wafer, without intervening substrates. The layers forming one memory level are deposited or grown directly on top of an existing level or layers of levels. In contrast, stacked memories are constructed by forming memory levels on separate substrates and attaching them to the top of each other, as in US Pat. No. 5,915,167 by Leedy, entitled “Three dimensional structure memory”. The substrates may be thinned or removed from the memory levels prior to bonding, but since the memory levels are initially formed on separate substrates, such memories are not actual monolithic three dimensional memory arrays.
The monolithic three-dimensional memory array formed on the substrate includes at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight, or indeed any number of memory levels may be formed over the substrate in such a multilevel array.
Embodiments of the present invention include a monolithic three dimensional memory array, wherein the monolithic three dimensional memory array comprises: a) a first memory level formed on a substrate, the first memory level being a first plurality of memories; Cells, each first memory cell comprising: i) a field effect transistor; And ii) a switchable resistor memory element, wherein the switchable resistor memory element reduces the resistance when the set voltage magnitude is applied and increases the resistance when the reset voltage magnitude is applied, the set voltage magnitude and the reset voltage magnitude The polarity of the first memory level is opposite; b) a second memory level monolithically formed above said first memory level. In preferred embodiments, the second memory level includes a second plurality of memory cells.
Because memory cells are formed over the substrate, the first, second, and additional multiple switchable resistor memory elements can be formed at different heights above the substrate.
Embodiments of the present invention provide a method of forming, setting and resetting a nonvolatile memory cell and associated conductors, the method comprising: forming a first data line extending in a first direction; Forming a first reference line extending in a first direction; Forming a thin film transistor having a channel region, wherein the channel region is electrically disposed between a first data line and a first reference line; Forming a switchable resistor memory element disposed between the channel region and the data line, the resistive switching memory element having a first resistor; Forming a first selection line extending in a second direction different from the first direction; Applying a set voltage magnitude across a switchable resistor memory element, wherein after application of the set voltage magnitude, the switchable resistor memory element has a second resistance lower than a first resistor; ; And applying a reset voltage magnitude across the switchable resistor memory element, wherein after application of the reset voltage magnitude, the switchable resistor memory element has a third resistance higher than the second resistor, the set voltage magnitude and The polarity of the reset voltage magnitude is reversed. During the application of the set voltage magnitude, current flows between the first data line and the first reference line through the channel region and the switchable resistor memory element.
While detailed manufacturing methods have been described herein, any other method of forming the same structures can be used as long as the results are within the scope of the present invention.
The foregoing detailed description has described only a few of the many forms that the present invention can take. For this reason, this detailed description is for illustrative purposes, and is not intended to be limiting. Only the following claims, including all equivalents, are intended to define the scope of the invention.
A nonvolatile memory cell,
A switchable resistor memory element 36; 66,
A transistor 34 comprising channel regions 41 and 56, wherein the switchable resistor memory element 36 and 66 and the transistor 34 are arranged in series.
The transistor 34 is electrically connected between the data lines 22a to 22d and 50 and the reference lines 24 and 64, and both the data lines 22a to 22d and 50 and the reference lines 24 and 64 are formed. Extend in one direction,
When the transistor 34 is on, current flows in the second direction through the channel regions 41 and 56, and the second direction is perpendicular to the first direction,
The switchable resistor memory element 36; 66 reduces the resistance when the set voltage magnitude is applied and increases the resistance when the reset voltage magnitude is applied,
Wherein in the polarity of the set voltage magnitude and the reset voltage magnitude are opposite to each other,
Non-volatile memory cell, characterized in that the data lines (22a-22d; 50) and the reference lines (24; 64) are below the channel region (41; 56).
2. The transistor of claim 1 wherein the transistor 34 is connected to select lines 26 and 62, wherein the select lines 26 and 62 extend in the second direction and comprise a gate electrode of the transistor 34. , Nonvolatile memory cell.
3. A nonvolatile memory cell according to claim 1 or 2, wherein the channel region (41; 56) comprises a polycrystalline semiconductor of silicon, germanium or silicon-germanium alloy.
3. A non- volatile memory cell according to claim 1 or 2, wherein the channel region (41; 56) is electrically arranged between the data lines (22a to 22d; 50) and the reference line (24; 64).
3. The switchable resistor memory element 36 or 66 according to claim 1 or 2,
Perovskite material;
Amorphous silicon doped with an element selected from the group consisting of V, Co, Ni, Pd, Fe, and Mn;
Carbon-polymer film; And
In solid electrolyte materials
A nonvolatile memory cell comprising one.
3. The switchable resistor memory device (36; 66) is a solid electrolyte material comprising chalcogenide glass having the formula A X B Y ,
Wherein A is selected from the group consisting of B, Al, Ga, In, Ti, C, Si, Ge, Sn, Pb, N, P, As, Sb, Bi, F, Cl, Br, I and At ,
Wherein B is Si, Se and Te, or a compound thereof.
3. A nonvolatile memory cell according to claim 1 or 2, wherein the switchable resistor memory element (36; 66) is a solid electrolyte material and the reservoir of mobile metal ions is in contact with the solid electrolyte material.
9. The nonvolatile memory cell of claim 8 wherein the mobile metal ions are silver ions.
6. The nonvolatile memory cell of claim 5 wherein the set voltage magnitude and the reset voltage magnitude are less than 2 volts.
A method of forming, setting, and resetting a nonvolatile memory cell and associated conductor,
Forming first data lines 22a-22d; 50 extending in a first direction;
Forming a first reference line (24; 64) extending in a first direction;
Forming a transistor 34 having channel regions 41 and 56, wherein the channel regions 41 and 56 are formed of the first data lines 22a to 22d and 50 and the first reference lines 24 and 64, respectively. Forming a transistor, electrically disposed between
Forming a switchable resistor memory element 36; 66 disposed between the channel region 41; 56 and the data lines 22a-22d; 50, wherein the switchable resistor memory element 36; 66 is formed. Forming a switchable resistor memory element having a first resistance;
Forming a first select line (26; 62) extending in a second direction different from the first direction;
Applying a set voltage magnitude across the switchable resistor memory element 36; 66, wherein after application of the set voltage magnitude, the resistor memory element 36; 66 has a second resistance lower than the first resistor; Applying the set voltage magnitude having:
Applying a reset voltage magnitude across the switchable resistor memory element (36; 66), wherein after application of the reset voltage magnitude, the switchable resistor memory element (36; 66) has a higher resistance than the second resistor; Applying the reset voltage magnitude having 3 resistances, the polarities of the set voltage magnitude and the reset voltage magnitude being opposite to each other;
A method comprising forming, setting, and resetting a nonvolatile memory cell and associated conductor, the method comprising:
The transistor is a thin film transistor,
Forming, setting, and resetting a nonvolatile memory cell and associated conductor, characterized in that the data lines 22a-22d; 50 and the reference lines 24; 64 are below the channel region 41; 56. How to.
12. The method of claim 11, wherein during the applying of the set voltage magnitude, the first data line (22a-22d; 50) through the channel region (41; 56) and the switchable resistor memory element (36; 66) A method for forming, setting, and resetting a nonvolatile memory cell and associated conductor through which a current flows between the first reference line and the first reference line.
13. The method of claim 11 or 12, wherein the switchable resistor memory elements 36; 66 form, set, and reset nonvolatile memory cells and associated conductors comprising a solid electrolyte material in contact with a reservoir of mobile metal ions. How to.
The method of claim 13, wherein during the applying of the set voltage, metal ions migrate to a solid electrolyte material to form, set, and reset nonvolatile memory cells and associated conductors, forming a conductive bridge. Way.
The method of claim 13, wherein during the applying of the reset voltage magnitude, metal ions migrate from the solid electrolyte material to the reservoir of mobile metal ions. .
14. The method of claim 13, wherein the first resistor and the third resistor are identical to each other.
The method of claim 13, wherein the solid electrolyte material comprises a chalcogenide glass layer.
13. The method of claim 11 or 12, wherein forming the thin film transistor 34 comprises depositing a layer of semiconductor material, the layer of semiconductor material comprising silicon, germanium or an alloy of silicon or germanium. A method of forming, setting, and resetting a nonvolatile memory cell and associated conductor.
19. The method of claim 18, wherein forming the thin film transistor (34) further comprises recrystallizing the semiconductor material.
13. The method of claim 11 or 12, wherein applying the set voltage magnitude applies a first voltage to the data lines 22a to 22d and a second voltage to the reference lines 24 and 64. And forming a nonvolatile memory cell and associated conductor, wherein the first voltage is greater than the second voltage.
20. The method of claim 19, wherein applying the reset voltage magnitude comprises applying a third voltage to the data lines 22a to 22d and a fourth voltage to the reference lines 24 and 64. And wherein the fourth voltage is greater than the third voltage, forming, setting, and resetting a nonvolatile memory cell and associated conductor.
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