Source: http://www.google.com/patents/US20030155659?dq=5958006
Timestamp: 2016-12-10 19:11:09
Document Index: 106267692

Matched Legal Cases: ['art 122', 'art 122', 'art 124', 'art 124', 'art 124', 'art 124', 'art 124', 'art 122', 'art 122', 'art 122', 'art 124', 'art 124']

Patent US20030155659 - Memory module having interconnected and stacked integrated circuits - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means...http://www.google.com/patents/US20030155659?utm_source=gb-gplus-sharePatent US20030155659 - Memory module having interconnected and stacked integrated circuitsAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20030155659 A1Publication typeApplicationApplication numberUS 10/080,036Publication dateAug 21, 2003Filing dateFeb 19, 2002Priority dateFeb 19, 2002Also published asUS6731011, US7005730, US7432599, US20040169285, US20060118927Publication number080036, 10080036, US 2003/0155659 A1, US 2003/155659 A1, US 20030155659 A1, US 20030155659A1, US 2003155659 A1, US 2003155659A1, US-A1-20030155659, US-A1-2003155659, US2003/0155659A1, US2003/155659A1, US20030155659 A1, US20030155659A1, US2003155659 A1, US2003155659A1InventorsVani Verma, Khushrav ChhorOriginal AssigneeVani Verma, Chhor Khushrav S.Export CitationBiBTeX, EndNote, RefManPatent Citations (3), Referenced by (35), Classifications (59), Legal Events (9) External Links: USPTO, USPTO Assignment, EspacenetMemory module having interconnected and stacked integrated circuits
[0057] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS [0058] Turning now to the drawings, FIG. 4A illustrates the interconnection between two or more integrated circuits using a wire bonding process. In the scope of the present embodiments, the lower or first integrated circuit 40 b may include a storage element attributable to semiconductor memory devices. Set forth in more detail below, first integrated circuit 40 b may also include a multi-level array of storage cells as described in the commonly assigned U.S. patent application Ser. No. 09/814,727, or any of the patents or applications set forth in the cross-reference section (paragraph one) of this application.. The upper or second integrated circuit 40 a may include similar circuitry, or may include different technology all together. For example, the second integrated circuit 40 a may include a controller for the storage element. In such an example, the controller for the semiconductor memory may be bonded to the top surface of the memory using a die attach adhesive. The die attach adhesive may be tape or epoxy based. A wire bonding machine, which may operate much like a sewing machine, may attach individual wires between bonding pads 42 on the active surface of each die, in such a manner as to achieve the required system functionality and communication between the memory, controller, and the outside world. As such, bonding pads 42 a of integrated circuit 40 a may be directly attached to bonding pads 42 b of integrated circuit 40 b with such a wire bonding process. The wires used in the wire bonding process may typically be aluminum, since aluminum is a good conductor and does not sag like softer materials (for example, gold). [0059] [0059]FIG. 4B indicates the various components that may be found on a single integrated circuit, in one example. More specifically, integrated circuit 41 may be a single die within multiple dice arranged across a semiconductor wafer. Integrated circuit 41 may represent the culmination of multiple processes applied to a single crystalline silicon base material. Such processes may include implantation, deposition, etching, cleaning, and polishing steps, among others. Integrated circuit 41, however, may not be placed in a package after it is scribe-removed from the wafer. According to one example, integrated circuit 41 may be highly integrated, and may include the various circuits needed to store and recall data. Those circuits may also include an array of memory cells that, according to one example, may be based on non-volatile memory cells 44. The mechanism responsible for directing data to and from memory cells 44 may involve memory controller 46. Memory controller 46 may be arranged on-chip, as in the example depicted in FIG. 4B. Alternatively, memory controller 46 may be arranged off-chip. As shown in FIG. 4A, a memory controller may also be coupled to memory as a separate die (i.e. integrated circuit 40 a and 40 b, respectively). [0060] In addition, it may be necessary to maintain data sent to and from memory cells 44 substantially free of noise. Therefore, decoupling capacitors 48 may be used to maintain a more pristine characteristic of the data sent to and from memory cells 44. As shown in FIG. 4B, decoupling capacitors 48 may be incorporated into an integrated circuit along with memory cells 44 and memory controller 46. On the other hand, decoupling capacitors 48 may be arranged on a separate controller die, as described in reference to FIG. 4A. In any case, conductors 49 may transmit data and control signals, and may extend to bonding pads on an integrated circuit. Thus, in the illustrated example, conductors 49 may terminate at bonding pads 43 of integrated circuit 41. [0061] In one embodiment of the multi-chip module, first integrated circuit 40 b may include a multi-level array of storage cells (i.e. three-dimensional memory array) as described in any of the patents or applications set forth in the cross-reference section (paragraph one) of this application. Such a three-dimensional memory array may be fabricated on several levels and may have eight levels of storage, in one example. In one embodiment, each level of storage may include a plurality of parallel rail-stacks aligned in a first direction and another plurality of rail-stacks or conductors aligned in a second direction. Such a second direction may be substantially perpendicular to the first direction, thereby forming right angles at the intersections between rail-stacks. A bit may be stored at each of the intersections of the perpendicular rail-stacks, such that memory cells may be defined by the rail-stacks and intermediate layers. [0062] [0062]FIG. 5 illustrates one embodiment of a three-dimensional memory array that may be included as first integrated circuit 40 b in the memory module of the present invention. In FIG. 5, only three complete levels 50, 51, and 52 of the memory array are depicted for purposes of simplicity. However, the memory array may include additional levels above and/or below the levels shown. The memory array may also be fabricated on a substrate, which may include a plurality of conductors. Also, vias may connect conductors within the rail-stacks to trace conductors within the substrate to read (or write) data from (or to) the memory array. Furthermore, each of the memory array rail-stacks may be a full or half set, such that half rail-stacks may be approximately half the thickness of the full set of rail-stacks used in subsequent levels. In addition, insulating antifuse layers may be used to separate adjacent rail-stacks. [0063] In FIG. 5, for instance, rail-stack 3 may be a full rail-stack including a lightly doped n− layer, a heavily doped n+ layer, a conductor layer, and a second n+ layer. The n+ layers may be formed above and below the conductor layer to prevent unintended Schottky diode formation. Antifuse layer 53 may be formed from a dielectric material, such as silicon dioxide, in one example, and may separate rail-stack 3 from neighboring rail-stack 4. Rail-stack 4 may be a half rail-stack formed above antifuse layer 53, and may include a lightly doped p− layer, a first p+ layer, a conductor layer, and a second p+ layer. After deposition, the layers of rail-stack 4 may be masked and etched to form the structures of half rail-stack 4. Lines 57 in FIG. 5 may indicate that antifuse layer 53 (and similar layers) may not be etched with the rail-stack and may extend over the entire array, thus reducing sidewall leakage into rail-stacks below. [0064] The etching process may also form voids between portions of half rail-stacks, such as void 58 within rail-stack 4, which may be filled with a dielectric material. The fill may be planarized along with a portion of the second p+ layer to control the thickness and contour of the fill. Antifuse layer 54 may be deposited on top of rail-stack 4. The process may be repeated by forming rail-stacks 5 and 6 similar to the formation of railstacks 3 and 4, respectively, or until the 3-D memory array may be completed. [0065] To write a bit into a cell of the 3-D memory array, a relatively high voltage (e.g. 5-20V) may be applied between the conductors of neighboring rail-stacks. Such a high voltage may cause a breach in the antifuse layer, thereby creating a diode at the intersection between rail-stacks. In this manner, each conductor may constitute a bit line for the “cells” above and below it. Conversely, the absence of such a voltage may permit the antifuse layer to retain its insulating properties. Therefore, diodes may be selectively formed to program the memory array by applying a voltage to select pairs of conductors. Similarly, data may be read from the 3-D memory array by applying a voltage that is substantially lower than the voltage used to write data into the array. [0066] Alternative embodiments of the three-dimensional memory array may be further described in the above patent application. Additional embodiments may also be described in commonly owned U.S. Pat. No. 6,034,882 to Johnson et al, as set forth in paragraph one of this specification. [0067] [0067]FIG. 6 illustrates a first embodiment of the multi-chip module of the present invention in which stacked integrated circuits 40 may be incorporated onto substrate 62. Stacked integrated circuits 40 may include controller 40 a and storage element 40 b, such that controller 40 a may be stacked upon and bonded to storage element 40 b. In one example, controller 40 a may also be electrically coupled to storage element 40 b through a wire bonding process (i.e. wire bond 68). However, controller 40 a may be coupled to storage element 40 b by another bonding process, such as tape automated bonding (TAB) or flip-chip attachment. Preferably, storage element 40 b may be a three-dimensional memory array, as described above. [0068] Memory module 60 of FIG. 6 may also include a first set of wires 69 extending between controller 40 a and trace conductors 64. Trace conductors 64 may be arranged on the surface of substrate 62 and/or embedded within the thickness of substrate 62. Trace conductors 64 may, therefore, include one or more layers of trace conductors, each of which may be separated by a dielectric layer. Trace conductors 64 may extend along one or more of layers of the substrate, and may connect leads of at least one integrated circuit to a plurality of conductors 66 through plated-through holes, or vias. [0069] The memory module may further include a molded resin encasing stacked integrated circuits 40 and substrate 62, such that the memory module may include an outer surface having dimensions substantially equal to the dimensions of a conventional memory card. The plurality of conductors 66 may also be shaped similar to edge connectors of a conventional memory card, and may be arranged in a single row near a forward leading edge of memory module 60. Additionally, the row of conductors 66 may extend flush with, or possibly extend slightly above or below, the outer surface of the molded memory module. In this manner, memory module 60 may be inserted into a receptor of an electronic device, such that the row of conductors (i.e. edge connectors) may be retained in surface contact with a corresponding planar conductive surface within the receptor. [0070] [0070]FIG. 7 illustrates a second embodiment of the multi-chip module of the present invention in which stacked integrated circuits 40 may be incorporated onto lead frame 70. In one example, first integrated circuit 40 b may be a three-dimensional memory array, as described above. However, the scope of the present invention may include any storage element, or any other integrated circuit. Lead frame 70 may contain a first portion 72 (i.e. paddle) that may be configured below stacked integrated circuits 40. Integrated circuits 40 may be bonded to the first portion of lead frame using, for example, a die attach adhesive. The die attach adhesive may be tape or epoxy based. As such, lead frame 70 may serve to support the molded memory module, and thus, may be fabricated from a strip of sheet metal by stamping or chemical milling. Lead frame 70 may also provide a holding fixture during the assembly process in which bonding pads 42 of integrated circuits 40 may be connected to the lead frame. After molding, lead frame 70 may become an integral part of the memory module. The lead frame may be fabricated from numerous materials, including nickel-iron or copper alloy. The lead frame may also be layered as a composite strip, such that a copper alloy may be placed upon a stainless steel structure. The lead frame, however, may be conductive. Conversely, a conventional substrate (or printed circuit board/card) may not be conductive, but may be instead semiconductive with layers of non-conductive dielectric interspersed with layers of spaced apart trace conductors. [0071] Extending outward from first portion 72 of lead frame 70 may be support members 74. Support members 74 may thereby secure the position of first portion 72 relative to a frame 76 encircling first portion 72. Extending inward from one side of frame 76 may be a plurality of conductors 78. Each conductor 78 may include a first portion 78 a and a second portion 78 b. First portion 78 a may be relatively narrow in upper surface area, while second portion 78 b may be much wider. Portions 78 a and 78 b may be formed from a single piece of conductive material and may extend as an integral piece with items 72, 74 and 76. Thus, first portion 72, support members 74, frame 76, and conductors 78 may be formed from the same sheet, such that each item may be stamped from that sheet. [0072] [0072]FIG. 8 illustrates a cross sectional view along plane 8 of FIG. 7 after bonding stacked integrated circuits 40 to first portion 72 of lead frame 70. For example, a first integrated circuit 40 b, such as a semiconductor memory, may be bonded to first portion 72 using a die attach adhesive 86. Die attach adhesive 86 may include silicon/gold eutectic bonding or may use a polymer adhesive base. Alternatively, die attach adhesive 86 may include any structure that securely fastens stacked integrated circuits 40 to first portion 72. In any case, die attach adhesive 86 is not electrically conductive, however, adhesive 86 may include thermal conducting properties. [0073] A second integrated circuit 40 a, such as a controller, may then be stacked upon and bonded to an opposing surface of the first integrated circuit using die attach adhesive 86. In another example, a memory die may be stacked upon a controller die, or any other combination of two or more integrated circuits may be used to form a stack of integrated circuits. The individual die may be electrically coupled to one another through a wire bonding process, which may attach individual wires between the bonding pads of each die, such that communication between the die may be achieved. For example, bonding pads 42 b of integrated circuit 40 b may be wire bonded to bonding pads 42 a of integrated circuit 40 a, such that integrated circuits 40 a and 40 b may be electrically and mechanically coupled to one another. [0074] In addition to being interconnected to integrated circuit 40 b, integrated circuit 40 a may also be coupled to a first set of the plurality of conductors 78. For example, a first set of wires may extend between bonding pads 42 a of integrated circuit 40 a and bonding pads arranged on first portion 78 a of conductors 78. Conductors 78 may be adapted for frictional engagement with, and electrical connection to, conductive elements arranged within a receptor of an electronic device. In this manner, integrated circuit 40 a may be coupled to internal circuitry of the electronic device. [0075] A second set of wires may extend between first integrated circuit 40 b and first portion 72, such that the second set of wires may only transmit power and ground signals to integrated circuit 40 b. The first portion of the lead frame may be laterally coupled to a second set of the plurality of conductors 78. In this manner, the first portion may be adapted to couple at least one of the stacked integrated circuits to dedicated power and ground conductors (i.e. second set of the plurality of conductors) from among conductors 78. As such, first portion 72 may include power and ground planar elements. The power element may extend as conductive ring 72 b coplanar with and laterally spaced from the ground element (such that the ground element 72 a may be the paddle portion of the lead frame structure). Conductive ring 72 b may be separated from ground element 72 a by an air gap on all four sides of ground element 72 a. In this manner, conductive ring 72 b may be electrically isolated from ground element 72 a in subsequent processing steps (i.e. when encapsulated with mold compound). [0076] Furthermore, a first one of the second set of conductors may be adapted to connect conductive ring 72 b to a power signal (or any other signal). Similarly, a second one of the second set of conductors may be adapted to connect ground element 72 a to a ground signal (or any other signal). Alternatively, ground element 72 a may be adapted to transmit a power signal and conductive ring 72 b may be adapted to transmit a ground signal. Moreover, first portion 72 may extend flush with or beyond the outer dimension of the stacked integrated circuits. In this manner, first portion 72 may be adapted to couple power and ground signals to bonding pads on any side of an integrated circuit. Alternatively, first portion 72 may be adapted to couple any two bonding pads of conductors 78 to bonding pads on any side of an integrated circuit. Therefore, the above embodiments of the present invention may provide a means to couple one or more stacked integrated circuits to lead frame conductors with the capability to utilize bonding pads on all four sides of an integrated circuit. [0077] [0077]FIG. 8 also indicates that once conductors 78 of lead frame 70 are secured and electrically connected to corresponding bonding pads on integrated circuit 40 a, conductors 78 may be retained between a pair of mold housings 82, and liquid resin 88 may be injected into the air-filled space surrounding integrated circuit 40 a. Contrary to ceramic packaging techniques which may leave an air-filled space between the integrated circuit and the package inner surface, the present technique purposely fills that space with an encapsulate that also suffices as the memory module encasement. Thus, after removing the pair of mold housings 82, the resin may extend outward from the integrated circuit to form an outer surface of memory module 80. [0078] The resin may be any inert component that is not electrically conductive, yet may include some thermal conductive properties. For example, the resin may consist of silicones, phenolics, and bisphenols (epoxy). The resin may also contain various curing agents, hardeners, accelerators, inert fillers, coupling agents, flame-retardants, stress-relief additives, coloring agents, and mold-release agents. In whatever form, resin 88 may be injected in liquid form into the cavity between the inward-facing surfaces of mold housings 82. After the liquid resin has had sufficient time to cure, the resin may harden to the form and dimensions of a conventional memory card. [0079] [0079]FIG. 11 illustrates memory module 80 after removal of the pair of mold housings 82. Memory module 80 may be formed of hardened resin material 110, which may encompass integrated circuits 40 and conductors 78. The hardened resin may serve to protect integrated circuits 40 from ingress of moisture, and may provide a mechanical support for the integrated circuits. [0080] After resin 110 has hardened, a covering 120 may be placed around the hardened resin. For example, covering 120 may be made of plastic that is heat-shrunk to fit the outer dimensions of the molded resin, or may be glued or welded at the joint between a two-part assembly of the covering. Memory card 80 may, therefore, be formed either with or without covering 120. If covering 120 is present, however, a mechanical switch or tab may be formed within the covering, similar to item 38 shown in FIG. 2. Thus, mechanical tab 38 may prevent writing data to integrated circuits 40 when mechanical tab 38 is activated. Alternatively, the switch may be snap assembled to slots formed in resin 110. [0081] Regardless of whether a covering is used, the hardened resin may be partially removed to expose the outer planar surfaces of conductors 78. Removal may take place either by back-lapping or etching of the molded resin to expose conductors 78 as the edge connectors of the memory module. Beneficially, the removal process may be employed on the backside surface of the memory module near the forward-leading edge, so that the forward-leading edge may be inserted into a receptor bearing corresponding conductive elements. Alternatively, the molding process may leave the pad areas free of resin, for example, by forming the mold cavity so that a recess may be formed to expose conductors 78, thereby forming edge connectors. The hardened resin 110 may or may not be encircled by a covering and, as shown in FIG. 11, no covering need be present. [0082] [0082]FIG. 12, however, illustrates the use of covering 120 and, more importantly, depicts a bend placed in conductors 78 of the lead frame. Conductors 78 may thereby be shown with a first part 122. First part 122 may be substantially coplanar with first portion 72 of the lead frame, and may be adapted to receive a wire bond of wire 126. Conductors 78, therefore, may extend along a first plane substantially coplanar to first portion 72, and may further extend downward at an angle to a second plane at which second part 124 may reside. Second part 124 may have an outer surface that may extend flush with the outer surface of hardened resin 110. As such, second part 124 may be exposed at the forward-leading edge of memory module 80. By employing a bend within conductors 78, no back-lapping or etching of hardened resin material 110 may be necessary to expose the edges of conductors 78. Additionally, second part 124 may consist of a widened surface (see FIG. 7) that may be adapted to frictionally engage conductive elements within a receptor of an electronic device, in one example. In this manner, bending one or more conductors within the row of conductors 78 may expose the second part 124 of each conductor. Thus, bending the conductors in the above manner may substantially form a row of edge connectors at the forward-leading edge of memory module 80. The edge connectors may be slightly offset from each other along a single axis. Even though one or more edge connectors within a row may be offset from the axis, the edge connectors nonetheless may maintain somewhat of an alignment along a line relative to one another. First portion 72, conductive ring 79, and integrated circuits 40, however, may remain suspended entirely within hardened resin 110. [0083] [0083]FIG. 13 illustrates an alternative arrangement of the second embodiment, in which first part 122 of conductors 78 may be arranged in a plane above first portion 72. Unlike the arrangement of FIG. 12 in which first part 122 may be coplanar with first portion 72, the first part 122 of FIG. 13 may be arranged above the plane formed by first portion 72, such that second part 124 may be coplanar with first portion 72. FIG. 13, therefore, illustrates elevating conductors 78 above first portion 72 to not only expose second part 124 as an edge connector, but also to expose the backside surface of first portion 72. Recall that first portion 72 may be conductive elements, and that die adhesive 86 may be thermally conductive. Each arrangement, therefore, may allow any heat build-up within integrated circuit 40 b to be transferred downward to thermally conductive elements 86 and 72. As such, the thermally conductive first portion 72 may operate as a heat sink to remove heat from integrated circuit 40 b. In another example, conductors 78 may extend in a single plane, as depicted in FIG. 11, such that conductors 78 may be exposed as edge connectors. [0084] [0084]FIG. 14 is top plane view along a lateral plane of the memory card as described in the second embodiment of the present invention. Thus, FIG. 14 illustrates the manner in which power and ground signals may be transmitted to stacked integrated circuits on all four sides of the integrated circuits. Memory card 80, therefore, may include integrated circuit 40 a stacked upon and bonded to integrated circuit 40 b. Each of the integrated circuits 40 may have an upper active surface that may include bonding pads 42 arranged along all four sides of the active surface. In this manner, bonding pads 42 a of integrated circuit 40 a may be coupled to bonding pads 42 b of integrated circuit 40 b, such that bonding pads may be utilized on all four sides of the integrated circuits. [0085] In addition, memory card 80 may include a plurality of conductors 78 that may be arranged on a forward-leading edge of the memory module. Memory card 80 may also include a molded resin extending completely around the stacked integrated circuits to form an outer dimension of the memory module. Subsequently, conductors 78 may be exposed in a manner as described above, thereby forming a row of edge connectors on the forward-leading edge of the memory card. Memory card 80 may further include a lead frame, in which first portion 72 of the lead frame may extend beyond the outer dimensions of integrated circuits 40. A first set of the plurality of conductors may be spaced laterally from first portion 72, while a second set of the plurality of conductors may be laterally coupled to first portion 72. In this manner, first portion 72 may be adapted to electrically couple integrated circuits 40 to the second set of edge conductors 78. First portion 72 may also be mechanically coupled to the lead frame with support members 140 and 142. Support members 140 and 142 are arranged on a lateral plane separate from conductors 78, such that support members 140 and 142 may be dielectrically spaced and electrically isolated from conductors 78. [0086] As stated above, first portion 72 may include power and ground planar elements. The power element may extend as conductive ring 72 b coplanar with and laterally spaced from ground element 72 a. As such, conductive ring 72 b may be separated from ground element 72 a by an air gap on all four sides of ground element 72 a. In this manner, conductive ring 72 b may be electrically isolated from ground element 72 a by filling the air gap with mold compound during the encapsulation of the memory module. As such, ground element 72 a and conductive ring 72 b may be adapted to couple integrated circuits 40 to at least a portion of conductors 78, such that bonding pads 42 may be utilized on all four sides of integrated circuits 40. [0087] Thus, ground element 72 a may be adapted to couple a ground signal from a first conductor of the second set of conductors 78 to a bonding pad on any of the four sides of an integrated circuit. Similarly, conductive ring 72 b may be adapted to couple a power signal from a second conductor of the second set of conductors 78 to a bonding pad on any of the four sides of an integrated circuit. In an alternative example, ground element 72 a may be adapted to transmit a power signal and conductive ring 72 b may be adapted to transmit a ground signal. Furthermore, first portion 72 may be adapted to couple any two conductors of the plurality of conductors 78 to bonding pads on any side of an integrated circuit. [0088] [0088]FIG. 9 illustrates yet another embodiment of the multi-chip module of the present invention in which stacked integrated circuits 40 may be incorporated onto lead frame 90. Lead frame 90 may be configured similarly to lead frame 70 of FIG. 7, such that lead frame 90 may include first portion 92, support members 94, frame 96, and conductors 98. Conductors 98 may also include first portion 98 a and second portion 98 b, similar in configuration to conductors 78 of lead frame 70 (shown in FIG. 7). Thus, first portion 92, support members 94, frame 96, and conductors 98 may be formed from the same sheet, such that each item may be stamped from that sheet. [0089] Additionally, first portion 92 of lead frame 90 may be configured to receive a first integrated circuit 40 b. A second integrated circuit 40 a may also be stacked upon and coupled to the first integrated circuit. In one example, first integrated circuit 40 b may be a three-dimensional memory array, as described above. However, the scope of the present invention may include any other storage element or integrated circuit. For instance, first integrated circuit 40 b may be a semiconductor memory while second integrated circuit 40 a may be a controller. Alternatively, memory may be stacked upon and coupled to a controller, or any other combination of two or more integrated circuits may also be used to create such a stacked configuration. However, unlike lead frame 70, first portion 92 of lead frame 90 may be further separated into first and second coplanar elements 92 a and 92 b, respectively. [0090] As stated above, the second portion of lead frame 90 may include a plurality of conductors 98, such that a first conductor from among the plurality of conductors may extend toward and connect with first coplanar element 92 a of the first portion. Likewise, a second conductor from among the plurality of conductors 98 may extend toward and connect with second coplanar element 92 b of the first portion. In this manner, the first conductor may transmit a power signal to first coplanar element 92 a, while the second conductor may transmit a ground signal to second coplanar element 92 b. In an alternative example, the first conductor may transmit a ground signal to the first coplanar element, while the second conductor may transmit a power signal to the second coplanar element. In yet a further example, the first and second conductors may transmit any two signals that may be necessary to the functionality of integrated circuits 40. In any case, all other of the first set of conductors 98, except for the first one and second one, may be spaced from the first portion. [0091] [0091]FIGS. 10A and 10B illustrate cross sectional views along planes 10A and 10B of FIG. 9 after bonding stacked integrated circuits 40 to first portion 92 of lead frame 90. Plane 10A is a cross sectional view of FIG. 9 including first coplanar element 92 a, illustrating the coupling between integrated circuit 40 b and first coplanar element 92 a. Similarly, plane 10B is a cross sectional view of FIG. 9 including second coplanar element 92 b, illustrating the coupling between integrated circuit 40 b and second coplanar element 92 b. [0092] In either case, a first integrated circuit 40 b, such as a memory die, may be bonded to first portion 92 in such a manner as to bond integrated circuit 40 b with at least a portion of each of the first and second coplanar elements (i.e. bifurcated paddle) of the lead frame. Die attach adhesive 106 may be used to bond integrated circuit 40 b to first portion 92. Die attach adhesive 106 may include silicon/gold eutectic bonding or may use a polymer adhesive base. Alternatively, die attach adhesive 106 may include any structure that securely fastens integrated circuit 40 b to first portion 92. As stated above, though die attach adhesive 106 may not be electrically conductive, die attach adhesive 106 may include thermal conducting properties. [0093] A second integrated circuit 40 a may be stacked upon and bonded to an opposing surface of the first integrated circuit using die attach adhesive 106. The individual die may be electrically coupled to one another through a wire bonding process, which may attach individual wires between the bonding pads of each die, such that communication between the die may be achieved. For example, bonding pads 42 b of integrated circuit 40 b may be wire bonded to bonding pads 42 a of integrated circuit 40 a, such that integrated circuits 40 a and 40 b may be electrically and mechanically coupled to one another. [0094] In addition to being interconnected to integrated circuit 40 b, integrated circuit 40 a may also be coupled to the plurality of conductors 98. For example, a first set of wires may extend between bonding pads 42 a of integrated circuit 40 a and bonding pads arranged on a first portion 98 a of conductors 98. In this manner, integrated circuit 40 a may be coupled to internal circuitry of an electronic device via conductors 98, such that conductors 98 may be adapted for frictional engagement with, and electrical connection to, conductive elements arranged within a receptor of the electronic device. [0095] Furthermore, first portion 92 may be a bifurcated conductive plate, such that the first and second coplanar elements 92 a, 92 b of the first portion may be adapted to transmit power and ground signals. The bifurcated paddle, or first portion 92, may also be adapted to extend beyond the dimensions of the stacked integrated circuits. In this manner, first coplanar element 92 a may extend beyond the lateral extents of a first portion of the stacked integrated circuits. Similarly, second coplanar element 92 b may extend beyond the lateral extents of a second portion of the stacked integrated circuits. Thus, the bifurcated paddle of the lead frame may be adapted to connect power and ground signals from conductors 98 to bonding pads of integrated circuits 40 on any side of the integrated circuits. For example, first coplanar element 92 a may be connected by a first conductor of conductors 78 to a ground signal (or power signal), while second coplanar element 92 b may be connected by a second conductor of conductors 78 to a power signal (or ground signal). [0096] After coupling the stacked integrated circuits to each other, first portion 92, and conductors 98, the memory module of the present embodiment may be completed in the manner as described in FIGS. 8 and 11-13. Specifically, conductors 98 may be retained between a pair of mold housings 102, and liquid resin 108 may be injected into the air-filled space surrounding integrated circuits 40. Since first coplanar element 92 a may be laterally spaced from second coplanar element 92 b, the liquid resin injected into the mold cavity may fill the common space to electrically isolate the two coplanar elements. liquid resin 108 may harden, and subsequently, the pair of mold housings 102 may be removed. In this manner, the resin may extend outward from the stacked integrated circuits to form an outer surface of memory module 100, such that memory module 100 may exhibit the form and dimensions of a conventional memory card. The hardened resin may also serve to protect integrated circuits 40 from ingress of moisture, and may further provide a mechanical support for the integrated circuits. [0097] The molded resin may be partially removed by a back-lapping or etching process to expose conductors 98 as the edge connectors of memory module 100. Alternatively, a bend may be employed within conductors 98, such that back-lapping or etching of the molded resin may not be necessary to expose the edges of conductors 98. Thus, conductors 98 may substantially form a row of edge connectors at the forward-leading edge of memory module 100. [0098] In an alternative arrangement of the present embodiment, conductors 98 may be elevated above first portion 92 to expose a second part of conductor 98 as an edge connector, as well as to expose the backside surface of first portion 92. In such an arrangement, any heat build-up within integrated circuit 40 b may be transferred downward to the thermally conductive adhesive 106 and first portion 92. As such, the thermally conductive first portion 92 may operate as a heat sink to remove heat from integrated circuit 40 b. In an alternative example of the present arrangement, conductors 98 may extend along a common plane with first portion 92, such that the backside surfaces of conductors 98 and first portion 92 may be exposed. [0099] It will be appreciated to those skilled in the art having the benefit of this disclosure that the details provided herein are believed to denote a memory module that may be mounted on a substrate or lead frame of a memory card package and may include one or more stacked integrated circuits. The memory module of the present invention may also provide a means to couple one or more of the stacked integrated circuits to substrate or lead frame conductors with the capability to utilize bonding pads on all four sides of the integrated circuits. The improved memory module may have further modifications and alternative forms to include various aspects of the present invention, as will be apparent to those skilled in art after having reviewed this description. Thus, it is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded in an illustrative rather than restrictive sense. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6515359 *Jan 20, 1998Feb 4, 2003Micron Technology, Inc.Lead frame decoupling capacitor semiconductor device packages including the same and methodsUS6531773 *Aug 17, 2001Mar 11, 2003Hitachi, Ltd.Semiconductor deviceUS6583512 *Oct 1, 2001Jun 24, 2003Matsushita Electric Industrial Co., Ltd.Semiconductor device and method for fabricating the same* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6826107 *Aug 1, 2002Nov 30, 2004Saifun Semiconductors Ltd.High voltage insertion in flash memory cardsUS6943438 *Jan 31, 2003Sep 13, 2005Samsung Electronics Co., Ltd.Memory card having a control chipUS7199458 *Jan 26, 2004Apr 3, 2007Samsung Electronics Co., Ltd.Stacked offset semiconductor package and method for fabricatingUS7429794 *Jun 21, 2005Sep 30, 2008Samsung Electronics Co., Ltd.Multi-chip packaged integrated circuit device for transmitting signals from one chip to another chipUS7668017Aug 17, 2005Feb 23, 2010Saifun Semiconductors Ltd.Method of erasing non-volatile memory cellsUS7675782Oct 17, 2006Mar 9, 2010Saifun Semiconductors Ltd.Method, system and circuit for programming a non-volatile memory arrayUS7692961Aug 2, 2006Apr 6, 2010Saifun Semiconductors Ltd.Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injectionUS7701779Sep 11, 2006Apr 20, 2010Sajfun Semiconductors Ltd.Method for programming a reference cellUS7738304Oct 11, 2005Jun 15, 2010Saifun Semiconductors Ltd.Multiple use memory chipUS7743230Feb 12, 2007Jun 22, 2010Saifun Semiconductors Ltd.Memory array programming circuit and a method for using the circuitUS7760554Aug 2, 2006Jul 20, 2010Saifun Semiconductors Ltd.NROM non-volatile memory and mode of operationUS7786512Jul 18, 2006Aug 31, 2010Saifun Semiconductors Ltd.Dense non-volatile memory array and method of fabricationUS7808818Dec 28, 2006Oct 5, 2010Saifun Semiconductors Ltd.Secondary injection for NROMUS7855441 *Nov 12, 2007Dec 21, 2010Samsung Electronics Co., Ltd.Semiconductor card package and method of forming the sameUS7919363 *Apr 21, 2006Apr 5, 2011Infineon Technologies AgIntegrated circuit with additional mini-pads connected by an under-bump metallization and method for production thereofUS7964459 *Dec 10, 2009Jun 21, 2011Spansion Israel Ltd.Non-volatile memory structure and method of fabricationUS8053812Mar 13, 2006Nov 8, 2011Spansion Israel LtdContact in planar NROM technologyUS8253452Feb 21, 2006Aug 28, 2012Spansion Israel LtdCircuit and method for powering up an integrated circuit and an integrated circuit utilizing sameUS8487453Feb 22, 2011Jul 16, 2013Infineon Technologies AgIntegrated circuit with pads connected by an under-bump metallization and method for production thereofUS8547703 *Oct 22, 2010Oct 1, 2013Sony CorporationCard-type peripheral apparatusUS9355021 *Jun 4, 2013May 31, 2016Rambus Inc.Cross-threaded memory systemUS20030197261 *Jan 31, 2003Oct 23, 2003Samsung Electronics Co., Ltd.Memory cardUS20040164392 *Jan 26, 2004Aug 26, 2004Chan-Suk LeeStacked semiconductor package and method for fabricatingUS20050280165 *Jun 21, 2005Dec 22, 2005Samsung Electronics Co., Ltd.Multi-chip packaged integrated circuit device for transmitting signals from one chip to another chipUS20060258140 *Apr 21, 2006Nov 16, 2006Armin FischerIntegrated circuit with additional mini-pads connected by an under-bump metallization and method for production thereofUS20080109594 *Oct 31, 2007May 8, 2008Meir GrossgoldNon-volatile memory device controlled by a micro-controllerUS20080116572 *Oct 31, 2007May 22, 2008Samsung Electronics Co., Ltd.Semiconductor memory modules, methods of arranging terminals therein, and methods of using thereofUS20080173996 *Nov 12, 2007Jul 24, 2008Samsung Electronics Co., Ltd.Semiconductor card package and method of forming the sameUS20090321952 *Jun 30, 2008Dec 31, 2009Liang XingzhiWire on wire stitch bonding in a semiconductor deviceUS20110103027 *Oct 22, 2010May 5, 2011Sony CorporationCard-type peripheral apparatusUS20110140236 *Feb 22, 2011Jun 16, 2011Armin FischerIntegrated Circuit with Pads Connected by an Under-Bump Metallization and Method for Production ThereofUS20130258577 *Mar 29, 2013Oct 3, 2013Innodisk CorporationEmbedded memory module and main board insertedly provided thereforUS20130339631 *Jun 4, 2013Dec 19, 2013Rambus Inc.Cross-threaded memory systemCN103632699A *Mar 13, 2013Mar 12, 2014成都海存艾匹科技有限公司Three-dimensional memory containing address/data converter chipEP1667058A1 *Nov 15, 2004Jun 7, 2006Solid State System Co., Ltd.Package structure of memory card and packaging method for the structure* Cited by examinerClassifications U.S. Classification257/777, 257/E25.013, 257/E23.176International ClassificationG06K19/077, H01L23/538, H01L25/065Cooperative ClassificationH01L2924/181, H01L2924/12032, H01L24/48, H01L2924/01082, H01L2224/32245, H01L24/45, H01L2225/06582, H01L23/49537, H01L2224/48257, H01L2224/45124, H01L2224/48247, H01L2224/73265, H01L2224/49171, H01L24/49, H01L2924/01033, H01L2924/14, H01L2225/06562, H01L2225/06555, H01L2224/48091, H01L27/0688, H01L2924/01015, H01L2924/01029, H01L2225/06579, H01L25/0657, H01L2924/01079, H01L25/18, G06K19/07745, G06K19/072, H01L2224/48145, H01L2924/19041, H01L2924/01028, H01L23/3107, H01L2924/01322, H01L23/49575, H01L2224/32145, H01L27/112, H01L23/49551, H01L2225/0651, H01L2225/06506, H01L23/5388, H01L2924/01014, H01L2924/01013European ClassificationG06K19/07P, H01L24/49, H01L23/495L, H01L25/18, H01L23/495G4B, H01L23/31H, H01L23/495F, H01L27/06E, H01L23/538K, G06K19/077M, H01L25/065SLegal EventsDateCodeEventDescriptionFeb 19, 2002ASAssignmentOwner name: MATRIX SEMICONDUCTOR, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VERMA, VANI;CHHOR, KHUSHRAV S.;REEL/FRAME:012643/0311;SIGNING DATES FROM 20020213 TO 20020214Apr 28, 2006ASAssignmentOwner name: SANDISK 3D LLC, CALIFORNIAFree format text: MERGER;ASSIGNOR:MATRIX SEMICONDUCTOR, INC.;REEL/FRAME:017544/0769Effective date: 20051020Owner name: SANDISK 3D LLC,CALIFORNIAFree format text: MERGER;ASSIGNOR:MATRIX SEMICONDUCTOR, INC.;REEL/FRAME:017544/0769Effective date: 20051020Mar 2, 2007ASAssignmentOwner name: SANDISK 3D LLC, CALIFORNIAFree format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECTIVE MERGER TO ADD PAGES TO THE MERGER DOCUMENT PREVIOUSLY RECORDED PREVIOUSLY RECORDED ON REEL 017544 FRAME 0769;ASSIGNOR:MATRIX SEMICONDUCTOR, INC.;REEL/FRAME:018950/0686Effective date: 20051020Owner name: SANDISK 3D LLC,CALIFORNIAFree format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECTIVE MERGER TO ADD PAGES TO THE MERGER DOCUMENT PREVIOUSLY RECORDED PREVIOUSLY RECORDED ON REEL 017544 FRAME 0769. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:MATRIX SEMICONDUCTOR, INC.;REEL/FRAME:018950/0686Effective date: 20051020Owner name: SANDISK 3D LLC, CALIFORNIAFree format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECTIVE MERGER TO ADD PAGES TO THE MERGER DOCUMENT PREVIOUSLY RECORDED PREVIOUSLY RECORDED ON REEL 017544 FRAME 0769. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:MATRIX SEMICONDUCTOR, INC.;REEL/FRAME:018950/0686Effective date: 20051020Oct 22, 2007FPAYFee paymentYear of fee payment: 4Sep 19, 2011FPAYFee paymentYear of fee payment: 8Oct 21, 2015FPAYFee paymentYear of fee payment: 12Mar 30, 2016ASAssignmentOwner name: SANDISK TECHNOLOGIES INC., TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK 3D LLC.;REEL/FRAME:038300/0665Effective date: 20160324Apr 25, 2016ASAssignmentOwner name: SANDISK TECHNOLOGIES INC., TEXASFree format text: CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:SANDISK 3D LLC;REEL/FRAME:038520/0552Effective date: 20160324May 25, 2016ASAssignmentOwner name: SANDISK TECHNOLOGIES LLC, TEXASFree format text: CHANGE OF NAME;ASSIGNOR:SANDISK TECHNOLOGIES INC;REEL/FRAME:038813/0004Effective date: 20160516RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services