Source: http://www.google.es/patents/US20090311819?dq=flatulence
Timestamp: 2013-05-23 17:03:25
Document Index: 302143689

Matched Legal Cases: ['application No. 096139003', 'arts 92', 'arts 92', 'arts 92', 'arts 92', 'arts 92', 'art 2', 'art 2', 'arts 2', 'arts 2', 'arts 2', 'arts 2', 'arts 2']

Patente US20090311819 - Method for Making Micro-Electromechanical System Devices - Google PatentesB�squeda Im�genes Maps Play YouTube Noticias Gmail Drive M�s » B�squeda avanzada de patentes | Historial web | Iniciar sesi�n B�squeda avanzada de patentesPatentesA method for making micro-electromechanical system devices includes: (a) forming a sacrificial layer on a device wafer; (b) forming a plurality of loop-shaped through-holes in the sacrificial layer so as to form the sacrificial layer into a plurality of enclosed portions; (c) forming a plurality of cover...http://www.google.es/patents/US20090311819?utm_source=gb-gplus-sharePatente US20090311819 - Method for Making Micro-Electromechanical System Devices N�mero de publicaci�nUS20090311819 A1Tipo de publicaci�nSolicitud N�mero de solicitud12/244,258 Fecha de publicaci�n17 Dic 2009 Fecha de presentaci�n2 Oct 2008 Fecha de prioridad18 Oct 2007Tambi�n publicado comoUS7824945 N�mero de publicaci�nUS 2009/0311819 A1US2009/0311819A1 InventoresTso-Chi ChangMingching Wu Cesionario originalAsia Pacific Microsystems, Inc. Clasificaci�n de EE.UU.438/51257/E21.499 Clasificaci�n internacionalH01L21/50 Clasificaci�n cooperativaB81C2203/0136B81B2203/0118B81C1/0015B81C1/00333 Clasificaci�n europeaB81C1/00C14ZB81C1/00C4CEnlaces externosUSPTO Cesi�n de USPTO EspacenetMethod for Making Micro-Electromechanical System DevicesUS 20090311819 A1 Resumen A method for making micro-electromechanical system devices includes: (a) forming a sacrificial layer on a device wafer; (b) forming a plurality of loop-shaped through-holes in the sacrificial layer so as to form the sacrificial layer into a plurality of enclosed portions; (c) forming a plurality of cover caps on the sacrificial layer such that the cover caps respectively enclose the enclosed portions of the sacrificial layer; (d) forming a device through-hole in each of active units of the device wafer so as to form an active part suspended in each of the active units; and (e) removing the enclosed portions of the sacrificial layer through the device through-holes in the active units of the device wafer.
1. A method for making micro-electromechanical system devices, comprising:
(a) forming a sacrificial layer on a front side of a device wafer which has a plurality of active units; (b) forming a plurality of loop-shaped through-holes in the sacrificial layer so as to form the sacrificial layer into a plurality of enclosed portions, each of which is surrounded by a loop-shaped route of a respective one of the loop-shaped through-holes and each of which is aligned with a respective one of the active units of the device wafer; (c) forming a plurality of cover caps on the sacrificial layer such that each of the cover caps is aligned with a respective one of the active units of the device wafer and extends into a respective one of the loop-shaped through-holes in the sacrificial layer to contact the front side of the device wafer so as to cooperate with a respective one of the active units of the device wafer to enclose a respective one of the enclosed portions of the sacrificial layer; (d) forming a device through-hole in each of the active units of the device wafer so as to form an active part suspended in each of the active units of the device wafer and so as to expose a respective one of the enclosed portions of the sacrificial layer from a back side of the device wafer; and (e) removing the enclosed portions of the sacrificial layer through the device through-holes in the active units of the device wafer.
2. The method of claim 1, wherein the device wafer includes an active layer, a suspender layer, and an insulator layer sandwiched between the active layer and the suspender layer, the suspender layer and the active layer defining the front and back sides of the device wafer, respectively, the sacrificial layer being formed on the suspender layer in step (a), the device through-hole in each of the active units extending at least through the active layer and the insulator layer.
3. The method of claim 2, wherein the suspender layer is patterned to form a plurality of through-holes therein at each of the active units prior to the formation of the sacrificial layer thereon, the device through-hole in each of the active units being in spatial communication with the through-holes in the suspender layer at the respective one of the active units, the sacrificial layer extending into the through-holes in the suspender layer in step (a).
4. The method of claim 3, wherein the active layer is made from silicon, the insulator layer is made from silicon dioxide, and the suspender layer is made from silicon.
5. The method of claim 3, wherein formation of the cover caps on the sacrificial layer in step (c) is conducted by forming a cap-forming layer on the sacrificial layer such that the cap-forming layer extends into the through-holes, followed by patterning the cap-forming layer through photolithographic techniques.
6. The method of claim 5, wherein formation of the device through-hole in each of the active units of the device wafer is conducted by forming a first hole in the active layer, followed by forming a second hole in the insulator layer that is in spatial communication with the first hole in the active layer and the through-holes in the suspender layer at the respective one of the active units.
7. The method of claim 6, wherein formation of the first hole in the active layer is conducted through inductively coupled plasma etching techniques.
8. The method of claim 6, wherein formation of the second hole in the insulator layer is conducted through wet etching techniques.
9. The method of claim 1, wherein the sacrificial layer is made from a photoresist material.
10. The method of claim 5, wherein the cap-forming layer is made from a photosensitive material.
11. The method of claim 5, wherein the cap-forming layer is made from bisbenzocyclobutene.
12. The method of claim 1, wherein each of the cover caps includes a seed layer of a first metal formed on the sacrificial layer and extending into a respective one of the loop-shaped through-holes in the sacrificial layer, and a plating layer of a second metal formed on the seed layer.
13. The method of claim 12, wherein the first metal is selected from the group consisting of Ti, Cu, and Al, and the second metal is selected from the group consisting of Ni, Cu, and Ni�Fe.
14. The method of claim 12, wherein formation of the seed layer is conducted through vapor deposition techniques, and formation of the plating layer is conducted through plating techniques.
15. The method of claim 14, further comprising forming a plurality of cap-defining walls on the front side of the device wafer after formation of the seed layer and prior to formation of the plating layer such that each of the cap-defining walls cooperates with the respective seed layer to define a loop-shaped gap therebetween, the plating. layer of each of the cover caps extending into the loop-shaped gap between a respective one of the cap-defining walls and the seed layer of the respective one of the cover caps.
16. The method of claim 15, wherein the cap-defining walls are made from a photoresist material.
17. The method of claim 16, further comprising removing the cap-defining walls during removal of the enclosed portions of the sacrificial layer in step (e).
18. The method of claim 1, further comprising attaching a circuit wafer to the back side of the device wafer after step (e) so as to cooperate with each of the cover caps and the device wafer to define an enclosed cavity there among for enclosing the active part of a respective one of the active units of the device wafer.
19. The method of claim 18, wherein the circuit wafer is adhesively bonded to the device wafer through a plurality of adhesive pads.
20. The method of claim 19, wherein the adhesive pads are made from bisbenzocyclobutene.
21. The method of claim 19, further comprising cutting the circuit wafer and the device wafer of the assembly of the circuit wafer, the device wafer and the cover caps so as to form a plurality of individual micro-electromechanical system devices.
22. The method of claim 21, further comprising coupling the device wafer to the circuit wafer through wire bonding techniques for each of the micro-electromechanical system devices, and packaging each of the micro-electromechanical system devices by disposing each of the micro-electromechanical system devices in a ceramic container, followed by sealing hermetically the ceramic container using a cover plate.
23. The method of claim 21, further comprising coupling the device wafer to the circuit wafer through wire bonding techniques for each of the micro-electromechanical system devices, and packaging each of the micro-electromechanical system devices by plastic molding techniques.
CROSS-REFERENCE TO RELATED APPLICATION This application claims priority of Taiwanese application No. 096139003, filed on Oct. 18, 2007.
The invention relates to a method for making micro-electromechanical system (MEMS) devices, more particularly to a method involving forming cover caps on a device wafer through film encapsulating techniques for making MEMS devices.
Micro-electromechanical system (MEMS) devices, such as electrostatic accelerometers, sensors, actuators, and condenser microphones, normally include a movable active part or mass suspended in an enclosed cavity. The active part is connected to and is suspended on a surrounding wall through cantilever(s) so as to be suspended and movable relative to the surrounding wall and so as to properly perform a desired function. However, the cantilever(s) is relatively fragile, and tends to be damaged during wafer dicing or die packaging for forming individual chips of the MEMS devices if left unprotected. Two main approaches, i.e., the wafer bonding techniques and the film encapsulating techniques, have been developed to protect the cantilevers and the active parts from being damaged during dicing or die packaging for the production of the MEMS devices. In the wafer bonding techniques, a cover wafer formed with holes is bonded to a device wafer formed with the MEMS dies through wafer bonding techniques. The assembly of the device wafer and the cover wafer is subsequently subjected to dicing so as to form individual MEMS devices which are then packaged to form chip-level MEMS packages. However, the manufacturing costs of the MEMS devices using wafer bonding techniques are relatively high.
Referring to FIGS. 1A to 1D, U.S. Pat. No. 6,936,491 discloses a method using the film encapsulating techniques to form the cover caps 90 (see FIG. 1D) on a device wafer having a device-preformed structure including active parts 92, surrounding walls 95, and cantilevers (not shown) Each of the active parts 92 is surrounded by and is connected to a respective one of the surrounding walls 95 through a corresponding one or corresponding ones of the cantilevers so as to be suspended on and be movable relative to the surrounding wall 95 in a cavity surrounded by the surrounding wall 95. However, the method requires formation of a sacrificial layer 91 of a silicon dioxide (see FIG. 1A) on the device wafer such that the sacrificial layer 91 fills the cavities in the device wafer so as to permit formation of a first encapsulation layer 93 (see FIG. 1B) indirectly on a front side of the device wafer through the sacrificial layer 91 (otherwise the first encapsulation layer 93 would fill the cavities to enclose the active parts 92 when the sacrificial layer 91 is not formed), and further requires formation of holes 930 in the first encapsulation layer 93 (see FIG. 1C) for removal of the sacrificial layer 91 through the holes 930, and closing of the holes 930 thereafter by forming a second encapsulation layer 94 on the first encapsulation layer 93 (see FIG. 1D). As such, the method is relatively complicated, and the cantilever(s) may be damaged due to the stress imparted thereto by the sacrificial layer 91 that encloses the cantilever(s) and the active parts 92. In addition, since the first and second encapsulation layers 93, 94 are formed through deposition techniques, they are relatively thin and thus are likely to collapse during dicing or packaging, thereby resulting in damage to the cantilevers and the active parts 92.
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for making micro-electromechanical system devices that can overcome the aforesaid drawbacks associated with the prior art.
According to the present invention, there is provided a method for making micro-electromechanical system devices. The method comprises: (a) forming a sacrificial layer on a front side of a device wafer which has a plurality of active units; (b) forming a plurality of loop-shaped through-holes in the sacrificial layer so as to form the sacrificial layer into a plurality of enclosed portions, each of which is surrounded by a loop-shaped route of a respective one of the loop-shaped through-holes and each of which is aligned with a respective one of the active units of the device wafer; (c) forming a plurality of cover caps on the sacrificial layer such that each of the cover caps is aligned with a respective one of the active units of the device wafer and extends into a respective one of the loop-shaped through-holes in the sacrificial layer to contact the front side of the device wafer so as to cooperate with a respective one of the active units of the device wafer to enclose a respective one of the enclosed portions of the sacrificial layer; (d) forming a device through-hole in each of the active units of the device wafer so as to form an active part suspended in each of the active units of the device wafer and so as to expose a respective one of the enclosed portions of the sacrificial layer from a back side of the device wafer; and (e) removing the enclosed portions of the sacrificial layer through the device through-holes in the active units of the device wafer.
FIGS. 1A to 1D are schematic sectional views to illustrate consecutive steps of a conventional method for making MEMS devices;
FIGS. 2A to 2K are schematic sectional views to illustrate consecutive steps of the first preferred embodiment of a method for making MEMS devices according to this invention;
FIG. 2L is a perspective view to illustrate the structure of an active part of a MEMS die formed by an etching step in the method of the first preferred embodiment after formation of cover caps;
FIG. 3A is a schematic sectional view to illustrate a configuration of a MEMS package formed by ceramic packaging a MEMS device made by the method of the first preferred embodiment using a container and a cover plate;
FIG. 3B is a schematic sectional view to illustrate a configuration of a MEMS package formed by post-molded packaging a MEMS device made by the method of the first preferred embodiment using a molding material;
FIGS. 4A and 4B are schematic sectional views to illustrate two consecutive steps of the second preferred embodiment of the method according to this invention;
FIG. 5A is a schematic sectional view to illustrate a configuration of a MEMS package formed by ceramic packaging a MEMS device made by the method of the second preferred embodiment using a container and a cover plate;
FIG. 5B is a schematic sectional view to illustrate a configuration of a MEMS package formed by post-molded packaging a MEMS device made by the method of the second preferred embodiment using a molding material; and
FIGS. 6A to 6F are schematic sectional views to illustrate consecutive steps of the third preferred embodiment of the method according to this invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before the present invention is described in greater detail with reference to the accompanying preferred embodiment, it should be noted herein that like elements are denoted by the same reference numerals throughout the disclosure.
FIGS. 2A to 2K illustrate consecutive steps of the first preferred embodiment of a method for making micro-electromechanical system (MEMS) devices 100, such as electrostatic accelerometers, according to the present invention. The method includes the steps of: (a) preparing a device wafer 1 having a plurality of active units 10 (see FIG. 2A) and forming a sacrificial layer 16 on a front side of the device wafer 1 (see FIG. 2B); (b) forming a plurality of loop-shaped through-holes 161 in the sacrificial layer 16 so as to form the sacrificial layer 16 into a plurality of enclosed portions 162 (see FIG. 2B), each of which is surrounded by a loop-shaped route of a respective one of the loop-shaped through-holes 161 and each of which is aligned with a respective one of the active units 10 of the device wafer in a normal direction relative to the device wafer 1 (see FIG. 2C); (c) forming a plurality of cover caps 18 on the sacrificial layer 16 (see FIG. 2E) such that each of the cover caps 18 is aligned with a respective one of the active units 10 of the device wafer 1 in the normal direction and extends into a respective one of the loop-shaped through-holes 161 in the sacrificial layer 16 to contact the front side of the device wafer 1 so as to cooperate with a respective one of the active units 10 of the device wafer 1 to enclose a respective one of the enclosed portions 162 of the sacrificial layer 16; (d) forming a device through-hole 101 in each of the active units 10 of the device wafer 1 (see FIG. 2G) so as to form a surrounding wall 3, an active part 2, and cantilevers 4 in each of the active units 10 and so as to expose a respective one of the enclosed portions 162 of the sacrificial layer 16 from a back side of the device wafer 1, the active part 2 being surrounded by the surrounding wall 3 and being suspended on the surrounding wall 3 through the cantilevers 4 (see FIG. 2L) so as to be movable relative to the surrounding wall 3 of each of the active units 10 of the device wafer 1 for performing a desired function; (e) removing the enclosed portions 162 of the sacrificial layer 16 through the device through-holes 101 in the active units 10 of the device wafer 1 (see FIG. 2H); (f) attaching a circuit wafer 5 to the back side of the device wafer 1 through adhesive pads 71 of a bonding material after step (e) such that the circuit wafer 5 cooperates with the cover caps 18 and the surrounding walls 3 of the active units 10 of the device wafer 1 to define enclosed cavities 20 thereamong for enclosing the active parts 2 in the enclosed cavities 20, respectively (see FIG. 2I) ; (g) cutting the device wafer 1 of an assembly of the device wafer 1, the circuit wafer 5 and the cover caps 18 along cutting lines (not shown) on the device wafer 1 (see FIG. 2J) using a first cutter (not shown) having a thick edge so as to separate the device wafer 1 into individual dies, each corresponding to a respective one of the active units 10; and (h) further cutting the circuit wafer 5 of the assembly of the device wafer 1, the circuit wafer 5 and the cover caps 18 along cutting lines (not shown) on the circuit wafer 5 (see FIG. 2K) using a second cutter (not shown) having a thin edge so as to separate the circuit wafer 5 into individual dies, each cooperating with a respective one of the dies of the device wafer 1 and a respective one of the cover caps 18 to form a respective one of the MEMS devices 100. The bonding material is preferably a photosensitive material, such as bisbenzocyclobutene (BCB), so as to permit patterning of the bonding material to form the adhesive pads 71 through photolithographic techniques. The bonding of the circuit wafer 5 to the device wafer 1 through the adhesive pads 71 is conducted by heating the bonding material to a temperature of about 250� C.
In this embodiment, the device wafer 1 is a silicon-on-insulator (SOI) wafer, and includes an active layer 11, a suspender layer 14, and an insulator layer 13 sandwiched between the active layer 11 and the suspender layer 14. The active layer 11 is made from silicon, the insulator layer 13 is made from silicon dioxide, and the suspender layer 14 is made from silicon. The suspender layer 14 and the active layer 11 define the front and back sides of the device wafer 1, respectively. The sacrificial layer 16 is formed on the suspender layer 14 in step (a). Preferably, the suspender layer 14 is patterned prior to the formation of the sacrificial layer 16 thereon so as to form a plurality of through-holes 141 therein at each of the active units 10 for defining the cantilevers 4 of the respective one of the active units 10. A protective mask 12 of silicon dioxide is formed on the back side of the device wafer 1 for protecting the device wafer 1 during subsequent processing. The sacrificial layer 16 extends into the through-holes 141 in the suspender layer 14 in step (a) As such, the device through-hole 101 formed in each of the active units 10 in step (d) is required to extend only through the active layer 11 and the insulator layer 13 so as to be in spatial communication with the through-holes 141 in the suspender layer 14 at the respective one of the active units 10. When the suspender layer 14 is not patterned to form the through-holes 141 prior to the formation of the sacrificial layer 16 thereon, the device through-hole 101 formed in each of the active units 10 in step (d) is required to extend through the active layer 11, the insulator layer 13 and the suspender layer 14 so as to release the respective one of the active parts 2 and to expose the respective one of the enclosed portions 162 of the sacrificial layer 16. Since the active parts 2 are released from the respective surrounding walls 3 (see FIG. 2G) of the active units 10 after the cover caps 18 are formed, the stress imparted by the sacrificial layer to the active parts and the cantilevers as encountered in the aforesaid conventional method can be eliminated.
In this embodiment, the sacrificial layer 16 is made from a photoresist material, and is formed by applying the photoresist material on the suspender layer 14 through spin coating. The sacrificial layer 16 thus formed has a layer thickness of about 5 μm, and is patterned using an anchor-forming mask (not shown) through photolithographic techniques so as to form the through-holes 161. In this embodiment, the through-holes 161 in the sacrificial layer 16 have an inner diameter of about 1 mm and an outer diameter of about 1.2 mm. The enclosed portions 162 of the sacrificial layer 16 in step (e) are removed using a photoresist cleaner in a conventional manner. Note that in this embodiment, a non-enclosed portion 163 of the sacrificial layer 16 (see FIGS. 2E and 2G) that surrounds each of the cover caps 18 is also removed together with the enclosed portions 162 in step (e).
In this embodiment, formation of the cover caps 18 on the patterned sacrificial layer 16 in step (c) is conducted by forming a cap-forming layer 17 of a photosensitive material on the sacrificial layer 16 (see FIG. 2D) such that the cap-forming layer 17 extends into the through-holes 161 for forming an anchor portion of each cover cap 18, followed by patterning the cap-forming layer 17 using a cap-forming mask (not shown) through photolithographic techniques for forming a top portion of each cover cap 18 that is lifted by the anchor portion so as to be spaced apart from the front side of the device wafer 1. Preferably, the cap-forming layer 17 is made from bisbenzocyclobutene (BCB) , and is applied to the patterned sacrificial layer 16 using spin coating.
In this embodiment, formation of the device through-hole 101 in each of the active units 10 of the device wafer 1 is conducted by forming a first hole 111 in the active layer 11 (see FIG. 2F), followed by forming a second hole 131 in the insulator layer 13 (see FIG. 2G) that is in spatial communication with the first hole 111 in the active layer 11 and the through-holes 141 in the suspender layer 14 at the respective one of the active units 10. Formation of the first hole 111 in the active layer 11 at each of the active units 10 is conducted through inductively coupled plasma (ICP) etching techniques. Formation of the second hole 131 in the insulator layer 13 at each of the active units 10 is conducted through wet etching techniques using HF solution as etchant. The protective mask 12 is simultaneously removed during formation of the second hole 131 in the insulator layer 13 through the wet etching operation.
FIG. 3A illustrates a configuration of a MEMS package formed by encapsulating the MEMS device 100, which is made by the method of the first preferred embodiment, using a ceramic container 200 and a cover plate 300 through ceramic packaging techniques. During packaging, the MEMS device 100 is disposed in the ceramic container 200, and is subsequently sealed hermetically in the ceramic container 200 by the cover plate 300. The device wafer 1 is provided with a plurality of conductive pads 15 (only one is shown) on the suspender layer 14 at each of the active units 10 for coupling the MEMS device 100 to an external device (not shown). Each of the dies of the circuit wafer 5 is provided with a plurality of conductive pads 25 that are respectively connected to the conductive pads 15 of a respective one of the dies of the device wafer 1 through wire bonding techniques. Note that in this embodiment, the conductive pads 25 and the adhesive pads 71 are disposed at the same side of the die of the circuit wafer 5.
FIG. 3B illustrates a configuration of another MEMS package formed by enclosing the MEMS device 100, which is made by the method of the first preferred embodiment, using a plastic molding material 72 through post-molded. packaging techniques.
FIGS. 4A and 4B illustrate two consecutive steps of the second preferred embodiment of the method according to this invention. The second preferred embodiment differs from the previous embodiment in that the conductive pads 25 and the adhesive pads 71 are respectively disposed at opposite sides of the die of the circuit wafer 5. As such, the MEMS device 100 thus formed is a flip-chip-type device. FIG. 4A illustrates the step of bonding the circuit wafer 5 to the device wafer 1 through the adhesive pads 71. FIG. 4B illustrates the step of cutting simultaneously the device wafer 1 and the circuit wafer 5 of the assembly of the device wafer 1, the circuit wafer 5 and the cover caps 18 so as to form the individual MEMS devices 100.
FIG. 5A illustrates a configuration of a MEMS package formed by encapsulating the MEMS device 100, which is made by the method of the second preferred embodiment, using a ceramic container 200 and a cover plate 300 through ceramic packaging techniques.
FIG. 5B illustrates a configuration of another MEMS package formed by enclosing the MEMS device 100, which is made by the method of the second preferred embodiment, using a plastic molding material 72 through post-molded packaging techniques.
FIGS. 6A to 6F illustrate consecutive steps of the third preferred embodiment of the method according to this invention. The third preferred embodiment differs from the previous embodiments in that each of the cover caps 18 is formed by forming a seed layer 41 of a first metal on the patterned sacrificial layer 16 (see FIGS. 6A and 6B) and a plating layer 43 of a second metal on the seed layer 41 (see FIG. 6C). The seed layer 41 is formed in a manner such that the seed layer 41 cooperates with the device wafer 1 to enclose a respective one of the enclosed portions 162 of the sacrificial layer 16 and extends into a respective one of the loop-shaped through-holes 161 in the sacrificial layer 16.
The method of the third preferred embodiment further includes the step of forming a plurality of cap-defining walls 42 on the front side of the device wafer 1 after formation of the seed layer 41 and prior to formation of the plating layer 43 (see FIG. 6C) such that each of the cap-defining walls 42 cooperates with the respective seed layer 41 to define a loop-shaped gap 40 therebetween. The plating layer 43 of each of the cover caps 18 is formed in a manner such that the plating layer 43 extends into the loop-shaped gap 40 between a respective one of the cap-defining walls 42 and the seed layer 41 of the respective one of the cover caps 18. The first hole 111 in the active layer 11 (see FIG. 6D) and the second hole 131 in the insulator layer 13 (see FIG. 6E) are subsequently formed after formation of the cover caps 18 so as to expose the sacrificial layer 16 from the back side of the device wafer 1. The cap-defining walls 42 are preferably made from a photoresist material, and are simultaneously removed during removal of the enclosed portions 162 of the sacrificial layer 16 in step (e) (see FIG. 6F).
Preferably, the first metal is selected from the group consisting of Ti, Cu, and Al, and the second metal is selected from the group consisting of Ni, Cu, and Ni�Fe.
In this embodiment, formation of the seed layer 41 is conducted through vapor deposition techniques, and formation of the plating layer 43 is conducted through plating techniques.
Each of the cover caps 18 thus formed has a high mechanical strength by virtue of the metal that forms the cover caps 18, and thereby preventing collapse of the cover caps 18 from occurring during dicing or packaging of the assembly of the device wafer 1, the circuit wafer 5 and the cover caps 18.
By forming the cover caps 18 prior to formation of the active parts 2 in the active units 10 of the device wafer 1 or prior to the release of the active parts 2 from the surrounding walls 3 of the device wafer 1, and by using metal to form the cover caps 18 in the method of this invention, the aforesaid drawbacks associated with the prior art can be eliminated.