Source: http://www.google.com/patents/US5757198?dq=6,455,937
Timestamp: 2018-01-19 00:46:57
Document Index: 402847678

Matched Legal Cases: ['art 306', 'art 306', 'art 306', 'art 15', 'art 306', 'art 306']

Patent US5757198 - Method and apparatus for detecting an IC defect using charged particle beam - Google Patents
Test patterns are applied to an IC under test under a test pattern address by which the first fail is caused and under other test pattern addresses. A defect candidate area is moved to the position where a charged particle beam can scan the area and defect candidate wiring portions are specified. A potential...http://www.google.com/patents/US5757198?utm_source=gb-gplus-sharePatent US5757198 - Method and apparatus for detecting an IC defect using charged particle beam
Publication number US5757198 A
Application number US 08/641,358
Also published as DE19526194A1, DE19526194C2, US5592100, US5821761
Publication number 08641358, 641358, US 5757198 A, US 5757198A, US-A-5757198, US5757198 A, US5757198A
Inventors Soichi Shida, Hiroshi Kawamoto, Hironobu Niijima
Patent Citations (5), Referenced by (62), Classifications (7), Legal Events (4)
Method and apparatus for detecting an IC defect using charged particle beam
US 5757198 A
Test patterns are applied to an IC under test under a test pattern address by which the first fail is caused and under other test pattern addresses. A defect candidate area is moved to the position where a charged particle beam can scan the area and defect candidate wiring portions are specified. A potential data of the specified wiring is acquired for each of the test patterns and stored in a memory. This process is performed by sequentially stepping back the stop test pattern addresses. Then, a potential data of the specified wiring in the specified area is similarly acquired for non-defect IC. The respective potential data of the IC under test and the non-defect IC are compared to locate the mismatch test pattern address and wiring.
a first step of sequentially applying test patterns to an IC under test with the applied test pattern updated by application of a next test pattern, stopping the applied test pattern from being updated at a preset test pattern address, and irradiating a charged particle beam to a specified area of said IC under test while the test pattern stopped from being updated is being applied to detect a secondary electron emission thereby acquiring data of a first potential contrast image;
a second step of sequentially applying the test patterns to said IC under test with the applied test pattern updated by application of the next test pattern, stopping the applied test pattern from being updated at a test pattern address before one address from said preset test pattern address, and irradiating a charged particle beam to the specified area of said IC under test while the test pattern stopped from being updated is being applied to detect the secondary electron emission thereby acquiring data of a second potential contrast image;
a third step of repetitively carrying out said second step by sequentially shifting the test pattern address at which the update of the applied test pattern is stopped one address by one address before the test pattern address at which the update of the applied test pattern was stopped until said test pattern address at which the update of the applied test pattern is stopped reaches a predetermined test pattern address;
a fourth step of sequentially applying test patterns to a second IC with the applied test pattern updated by application of the next test pattern, stopping the applied test pattern from being updated at said preset zest pattern address, and irradiating a charged particle beam to a specified area of said second IC corresponding to that of said IC under test while the test pattern stopped from being updated is applying to detect the secondary election emission thereby acquiring data of a third potential contrast image;
a fifth step of sequentially applying the test patterns to said second IC with the applied test pattern updated by application of the next test pattern, stopping the applied test pattern from being updated at the test pattern address before one address from said preset test pattern address, and irradiating the charged particle beam to the specified area of said second IC while the test pattern stopped from being updated is being applied to detect the secondary electron emission thereby acquiring data of a fourth potential contrast image;
a sixth step of repetitively carrying out said fifth step by sequentially shifting the test pattern address at which the update of the applied test pattern is stopped one address by one address before the test pattern address at which the update of the applied test pattern was stopped until said test pattern address at which the update of the applied test pattern is stopped reaches said predetermined test pattern address;
a seventh step of acquiring a potential data of a specified portion in said specified area of said IC under test from the data of each of the potential contrast images of said IC under test at each of the test pattern addresses at which the update of the test pattern was stopped;
an eighth step of acquiring a potential data of a specified portion corresponding to that of said IC under test in said specified area of said second IC from each of the potential contrast image data of said second IC at each of the test pattern addresses at which the update of the test pattern was stopped;
a ninth step of converting each of the potential data acquired in said seventh step into a binary value;
a tenth step of converting each of the potential data acquired in said eighth step into a binary value; and
an eleventh step of displaying in a waveform the binary value potential data for each of the test pattern addresses acquired in said ninth step and said tenth step, respectively, assuming the test pattern address as a common coordinate axis.
2. The method as recited in claim 1 wherein said preset test pattern address is a test pattern address at which a mismatch is first detected between the applied test pattern to said IC under test and a corresponding expected value.
3. The method as recited in claim 1 wherein said preset test pattern address is a test pattern address at which a mismatch is first detected between the output data from said IC under test and a corresponding expected value.
4. The method as recited in claim 1 wherein the acquisition of the potential contrast image data at each of the test pattern addresses at which the update of the applied test pattern was stopped in said first to third steps is performed under two different conditions of operation for said IC under test thereby to generate a difference between the two potential contrast image data, and the difference image data is used in said seventh step and the following steps as the potential contrast image data of said first to third steps, and
wherein the acquisition of the potential contrast image data at each of the test pattern addresses at which the update of the applied test pattern was stopped in said fourth to sixth steps is performed under said two different conditions of operation for said second IC thereby to generate a difference between the two potential contrast image data, and the difference image data is used in said eighth step and the following steps as the potential contrast image data of said fourth to sixth steps.
5. The method as recited in claim 4 wherein said two conditions of operation are an application of the normal power supply voltage and an application of an abnormal power supply voltage to said IC under test or second IC.
6. The method as recited in claim 4 wherein the potential contrast image data at each of the test pattern addresses at which the update of the applied test pattern was stopped in said first to third steps is once stored for at least one specified area in a memory and then the stored potential contrast image data is used in said seventh step and the following steps as the potential contrast image data of said first to third steps, and
wherein the potential contrast image data at each of the test pattern addresses at which the update of the applied test pattern was stopped in said fourth to sixth steps is once stored for at least one specified area in a memory and then the stored potential contrast image data is used in said eighth step and the following steps as the potential contrast image data of said fourth to sixth steps.
7. The method as recited in claim 4 wherein the potential contrast image data acquired in said first to third steps is displayed in image form on a monitor and said specified portions are determined by viewing the displayed image.
8. The method as recited in claim 4 wherein said specified portions are obtained from a CAD data of said IC under test on the basis of the detected defect data of said IC under test.
9. The method as recited in claim 4 wherein the potential contrast image data of said IC under test and the potential contrast image data of said second IC are converted into respective color data, and the same wiring patterns of the respective ICs are displayed side by side on a monitor using CAD data of the specified area, and at the same time the wiring portions of the specified portions of one of said wiring patterns are displayed in color by means of the converted color data of said IC under test and the wiring portions of the specified portions of the other of said wiring patterns are displayed in color by means of the converted color data of said second IC.
This application is a division of application Ser. No. 08/503,003, filed Jul. 17, 1995, now abandoned.
The present invention relates to a method and an apparatus for detecting an IC defect by irradiating a charged particle bean to an IC which is not packaged, detecting amount of a secondary electron emission caused by the irradiation of a charged particle beam and obtaining data corresponding to the potential state of an irradiated spot.
In order to identify a defect portion in an IC, an IC defect analyzing apparatus utilizing a charged particle beam has been used. In this IC defect analyzing apparatus, a charged particle beam such as an electron beam is irradiated to a chip of an IC under test (DUT=Device Under Test hereinafter), and amount of a secondary electron emission from a wiring pattern portion formed on the IC chip is measured to know a potential of the wiring pattern. Also in the IC defect analyzing apparatus, the surface of the IC chip is scanned by a charged particle beam, and the potential state of the scanned area is acquired as a potential contrast image and displayed such that a low potential portion of the wiring pattern is displayed as white (amount of secondary electron emission is large) and a high potential portion is displayed as black (amount of secondary electron emission is small). Thus a defect portion can be identified from the potential state of a wiring pattern. Such a method for detecting an IC defect using a charged particle beam is shown in U.S. patent application Ser. No. 08/181,584 entitled "IC Analysis System and Electron Beam Probe System and Fault Isolation Method Therefor" filed on Jan. 14, 1994, or U.S. patent application Ser. No. 08/337,230 entitled "Method and Apparatus for Forming a Potential Distribution Image of Semiconductor Integrated Circuit" filed on Nov. 7, 1994, now U.S. Pat. No. 5,528,156.
It is an object of the present invention to provide a method and an apparatus for detecting the mismatch test pattern address and the mismatch wiring portion almost automatically.
FIG. 1 is a block diagram showing an embodiment of an apparatus in accordance with the present invention.
FIG. 1 shows an embodiment of an apparatus of the present invention. An IC defect detecting apparatus 100 of the present invention comprises a test pattern generator 200 and a charged particle beam tester 300. An electron beam is generally used as the charged particle beam but other charged particle beam such as an ion beam may be used.
The test pattern generator 200 furnishes test pattern signals to an IC under test (referred to as DUT=Device Under Test hereinafter) 11 placed in the charged particle beam tester 300. The test pattern generator 200 includes a start switch 201 for starting the generation of the test patterns, a stop switch 202 for stopping the generation of the test patterns at any time, stop pattern setting means 203, pattern holding means 204 for stopping the test pattern update operations upon the detection of the test pattern of the test pattern address set in the stop pattern setting means 203, voltage switching means 205 for allowing the switching of the operation voltage being applied to the DUT 11 between the normal 5V and the abnormal 4V every time the test pattern update is stopped and restarted, and number of patterns controlling means 206 for controlling the number of generated test patterns. In such a configuration, a start control and a stop control of the test pattern signal generation, and a control for stopping the test pattern update at a particular test pattern address can be carried out. When the test pattern update operation is stopped by the pattern holding means 204, stop signal generating means 207 sends a stop signal to the charged particle beam tester 300.
FIG. 2 functionally shows the image data acquisition apparatus 305 and the defect analysis memory 309. The image data acquisition apparatus 305 includes a frame memory 305A for storing an image data from a sensor 304 and the frame memory 305A provides the number of addresses corresponding to the number of pixels sufficient to display full screen of a potential contrast image display part 306A of the monitor 306. A tone signal for each pixel of a potential contrast image data is stored in each of the addresses. In other word, an analog voltage signal corresponding to the number of electrons detected by the sensor 304 is converted, for example, to a digital tone signal of 256 levels of 8 bits, and this digital signal is stored in each address of the frame memory 305A corresponding to the irradiated spot of a charged particle beam to acquire an image data. The acquisition of the image data is performed every time the update of the applied test patterns stops at the predetermined test pattern address and the test pattern address at which the update of the applied test pattern is stopped is stepped back sequentially to the prior test pattern address to acquire a potential contrast image data of the DUT 11 in the respective condition that each update stopped test pattern is applied.
For example, test patterns are sequentially applied to a DUT 11 first by an IC tester. Then, the output of the DUT is compared with the corresponding expected value for each test pattern. Then, a test pattern address by which a first mismatch is detected is identified. Alternatively, test patterns are applied to the DUT 11 from a test pattern generator 200 and then the output is compared with the corresponding expected value. The test patterns are updated until a mismatch (fail) is detected. In this state (the first mismatch is detected), the test pattern update is stopped. Then, a charged particle beam is irradiated to the DUT while the update stopped test pattern is applied to the DUT to acquire the potential contrast image data. In the case that the test pattern address of the first fail is obtained from the IC tester, this update stopped test pattern address is set in the stop pattern setting means 203 and then, the test patterns are applied to the DUT starting from the first test pattern address. When a test pattern address being applied matches the address set in the stop pattern setting means 203, the pattern holding means detects this and stops the test pattern update. Under the condition that the update stopped pattern is applied to the DUT 11, a stop signal is sent to the image data acquisition apparatus 305 from the stop signal generating means 207.
When the potential contrast image data of one screen corresponding to the potential contrast image display part 306A of the monitor 306 is acquired, the image data acquisition apparatus 305 sends an acquisition completion signal to the number of patterns control means 206. Upon receipt of the acquisition completion signal, the number of patterns control means 206 decrements by one the stop address set in the stop pattern setting means 203 and then the test pattern generator 200 generates the test patterns again starting from the first pattern address. Thus, assuming that ADRn is the pattern address of the first fail, as shown in FIG. 3, the test patterns are generated starting the first test pattern address ADR1 and are applied to the DUT 11 sequentially. When the test pattern of address ADRn is generated, the test pattern update is stopped and a potential contrast image data is acquired in that condition. Then, as shown in FIG. 3B, the test patterns are applied to the DUT 11 again starting from ADR1. When the test pattern of address ADRn-1 (which is the previous address of ADRn) is generated, the test pattern update is stopped and a potential contrast image data is acquired in that condition. Similarly, the successive processes are performed by decrementing the stop address by one and a potential contrast image data is acquired each time.
In summary, as shown in FIG. 4, in the method of the invention, a test pattern address of the first fail is obtained from an IC tester (S1). Then the test patterns are applied to the IC 11 up to the pattern address at which the first fail occured thereby to make the fail state of the IC 11 occur again (S2). Then, as described above, the IC 11 is moved so that one of the specified defect candidate area can be scanned by a charged particle beam 12 (S3). In this state, a defect candidate portion which is presumed to be associated with the fail within the defect candidate area is specified (S4). In this process, for example, a potential contrast image data of the specified defect candidate area is acquired and displayed on the potential contrast image display part 306A of the monitor 306 as shown in FIG. 2. Then an operator observes the screen and specifies the checking points as A1, A2, A3 and A4 by input means such as a mouse or a light pen on the wiring images presumed from the first fail output pin. By this operation, the addresses AD1, AD2, AD3 and AD4 of the frame memory 305A corresponding to the checking points A1, A2, A3 and A4 respectively are stored in the memory part 15 of the reading means 305B provided on the frame memory 305A.
The ending point of the pattern address step back is the first pattern address in an extreme case. Alternatively, the ending point could be predetermined based on the experimental data. When the step back of the test pattern address is completed a check is made to see if there is any remaining defect candidate area (S8). If any, a next defect candidate area is specified and the process returns to step S3 (S9). Thus, the DUT 11 is moved to acquire the potential data of the defect candidate portion (wiring) similarly in the next defect candidate area for each test pattern address.
In step S8, if no remaining defect candidate area, the process proceeds to the data acquisition for a non-defect IC. A non-defect IC of the same kind as the DUT 11 is placed on the XY stage 303. The position of the non-defect IC is moved by utilizing the position information obtained for acquiring the potential data of the previous defect IC (DUT 11). That is, the position of the non-defect IC is moved to a position of the area corresponding to the defect candidate area for the defect IC where the potential data can be acquired (S10). The potential data of the non-defect IC is acquired from the same portion corresponding to the defect candidate portion (wiring) of the defect candidate area in the defect IC for each of the same test pattern address and then the data is stored in the mass storage means 308 (S11). Then, a check is made to see if the step back of the test pattern address is completed (S12). If not completed, the stop test pattern address is decremented by one and the process returns to step S11 (S13). In such a manner, when the potential data of the respective wiring in the area of non-defect IC corresponding to the defect candidate area of the defect IC is acquired for each stop test pattern address, a check is made to see if there is any remaining area (S13). If there is any remaining area corresponding to the defect candidate area, a next area is specified and the process returns to step S11 (S15).
In the embodiment shown in FIG. 2, the binary value potential data of the same defect candidate porion in the same defect candidate area is read out for each of the non-defect IC and the defect IC in the order of the test pattern addresses from the data stored in the mass storage means 308 and is stored in a waveform memory 312 as shown in FIG. 7. The variations of the binary value data based on the variations of the test pattern addresses for each of the non-defect IC and the defect IC stored in the waveform memory 312 are displayed up and down on the waveform display part 306B of the monitor 306 as the curves (waveforms) 21 and 22 respectively. In the display part 306B, the horizontal axis indicates the values of the test pattern addresses or the values corresponding to the test pattern addresses. In this example, the waveform of the non-defect IC 21 and the waveform of the defect IC 22 do not match at the test pattern address 3. This mismatch portion may be indicated by a cursor 23, and the mismatch portion on the IC 11 and the associated test pattern address may be displayed on the monitor 306.
FIG. 8 shows a further different embodiment. The binary value potential data from the mass storage means 308 acquired as shown in FIG. 2 are sent to a conversion table 313 and are converted to values changing in response to both of the value of logical H or L and the test pattern address. FIG. 9 shows a conversion example of the conversion table 313. At the pattern address 1, if the input value is logical H, then the output value is "1". If the input value is logical L, then the output value is "10". At the pattern address 2, the output is "100" for the input H and the output is "1,000" for the input L. In such a way, the output values are selected to construct the conversion table 313 such that the sum of the output values (taken dependent on H or L) for all the applied test patterns is different if at least one mismatch between the non-defect and the defect ICs is present. The output values of the conversion table 313 corresponding to the respective binary value data taken out from the mass storage means 308 are summed up by a summing means 314 for all the applied test patterns for each of the non-defect IC and the DUT. Then the summed values for each of the non-defect IC and DUT are compared by defect IC judging means 315. If both values match, the DUT is judged as a non-defect IC. If mismatch, the DUT is considered to be a defect IC. Then, the summing process is tracked back to search the test pattern address by which the mismatch is caused. The mismatch pattern address can be identified as the last mismatch address from the back. This search operation is performed by the mismatch generating address identification means 316 without an operator intervention.
The process sequence in this case is shown in FIG. 11. In FIG. 11, the same step symbol is assigned to a process corresponding to FIG. 4. In this example, the process steps S1, S2 and S3 in FIG. 4 are performed first. In this embodiment, a potential contrast image data representing the potential distribution of the entire area of the moved IC 11 is acquired and stored in the mass storage means 308 (S21) The acquisition of the potential contrast image data is performed every time the test pattern address is stepped back one address by one address (S6, S7). When each potential contrast image data is acquired for each of the target test pattern addresses (step back process is completed), the process returns to step S3 until all the remaining defect candidate areas are processed. Thus, the potential contrast image data for all the defect candidate areas are acquired for each of the test pattern addresses and stored in the mass storage means 308 (S8, S9, S3).
When the necessary potential contrast image data for the DUT 11 are acquired, the process proceeds to the corresponding data acquisition process for the non-defect IC as in FIG. 4. The non-defect IC is moved to the area corresponding to the defect candidate area in step S9 as in FIG. 4, and then the potential contrast image data of that area is acquired similarly to step S21, and is stored in the mass storage means 308 (S22). This potential contrast data data acquisition is performed for each test pattern address by stepping back the pattern address one by one (S12, S13). If there is any remaining area, the non-defect IC is moved to the area and similar data acquisition is performed for each test pattern address (S14, S15). When all the necessary potential contrast image data for a non-defect IC are acquired in such a manner, a potential contrast image data for one area of the DUT for one pattern address is read out from the mass storage means 308 and displayed on the monitor 306. Then, the defect candidate portions (wiring portions) are specified (S4) as in step S4 of FIG. 4 by a cursor pointing by an operator or by an automatic pointing from the CAD data. Incidentally, the defect candidate portions may also be automatically specified using the CAD data in step S4 of FIG. 4.
In the comparison between the non-defect IC and the defect IC, the potential data itself may be used or the processed potential data may be used. For the process of the potential data, for example, the process flow shown in FIG. 12 can be utilized. First, i is initialized to 0 (P0) and the normal power supply voltage 5V (for example) is applied to the DUT 11(P1) and then the test patterns are applied to the DUT until a preset stop pattern address is applied (P2) and a potential contrast image data (referred to as a first potential contrast image data) is acquired (P3). Then the power supply voltage is changed to the abnormal 4V, for example, (P4) and the test patterns of P2 are applied to the DUT again (P5), and then a potential contrast image data (referred to as a second potential contrast image data) is acquired (P6). Then a difference image data between the first potential contrast image data and the second potential contrast image data is generated (P7) and this difference image data is added to the accumulated difference image data to obtain a summed data (P8). Then a check is made to see if i is N (P9) and if i is not N, then 1 is added to i and the process returns to P1 (P9). These steps are repeated N times. When the summed data obtained in such a way is displayed on the monitor 306, if there is a difference between the first potential contrast image data and the second potential contrast image data, the difference is intensified. Thus, a display image shown in FIG. 13 can be obtained. In FIG. 13, a white pattern 23 and a black pattern 24 are displayed. The white pattern 23 indicates a wiring where the first potential contrast image data is high level and the second potential contrast image data is low level. The black pattern 24 indicates a wiring where the first potential contrast image data is low level and the second potential contrast image data is high level. A specific process method shown in FIG. 12 is described, for example, in U.S. patent application Ser. No. 08/337,230.
In each process shown in FIGS. 4 and 11A-11B the summed data obtained in FIG. 12 can be used as the potential data of the specified portion for either of the non-defect IC or the defect IC. For the process shown in FIG. 12, as indicated by a dotted line in FIG. 1, an acquisition completion signal from the image data acquisition apparatus 305 is inputted to the test pattern generator 200 rather than to the number of patterns control means 206. Then, the test patterns are generated starting from the first address and the voltage switching means 205 switches the supply voltage from normal 5V to abnormal 4V or vice versa. When the predetermined number (N) of the summed difference image data are obtained, a number of patterns changing command is supplied to the number of patterns control means 206 from the CPU 311 as shown by a dotted line. Then the stop pattern address set in the stop pattern setting means 203 is decremented by one by the control means 206.
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U.S. Classification 324/754.22, 324/96, 324/762.03
International Classification G01R31/28, G01R31/307