Source: http://www.google.com/patents/US7982281?ie=ISO-8859-1
Timestamp: 2015-05-05 07:44:38
Document Index: 367878230

Matched Legal Cases: ['arts 900', 'art 1104', 'art 1105', 'art 1104', 'art 1105', 'art 1202', 'art 1104']

Patent US7982281 - Method of manufacturing a semiconductor device, method of manufacturing a ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAccording to one embodiment of the present invention, a SOI device includes a first composite structure including a substrate layer, a substrate isolation layer being disposed on or above the substrate layer, a buried layer being disposed on or above the substrate isolation layer, and a semiconductor...http://www.google.com/patents/US7982281?utm_source=gb-gplus-sharePatent US7982281 - Method of manufacturing a semiconductor device, method of manufacturing a SOI device, semiconductor device, and SOI deviceAdvanced Patent SearchPublication numberUS7982281 B2Publication typeGrantApplication numberUS 11/828,268Publication dateJul 19, 2011Filing dateJul 25, 2007Priority dateJul 25, 2007Fee statusPaidAlso published asDE102008034789A1, DE102008034789B4, US20090026572Publication number11828268, 828268, US 7982281 B2, US 7982281B2, US-B2-7982281, US7982281 B2, US7982281B2InventorsGabriel DehlingerOriginal AssigneeInfineon Technologies AgExport CitationBiBTeX, EndNote, RefManPatent Citations (15), Referenced by (1), Classifications (11), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethod of manufacturing a semiconductor device, method of manufacturing a SOI device, semiconductor device, and SOI device
US 7982281 B2Abstract
According to one embodiment of the present invention, a SOI device includes a first composite structure including a substrate layer, a substrate isolation layer being disposed on or above the substrate layer, a buried layer being disposed on or above the substrate isolation layer, and a semiconductor layer being disposed on or above the buried layer; a trench structure being formed within the first composite structure; and a second composite structure provided on the side walls of the trench structure, wherein the second composite structure includes a first isolation layer covering the part of the side walls formed by the semiconductor layer and formed by an upper part of the buried layer; and a contact layer covering the isolation layer and the part of the side walls formed by a lower part of the buried layer.
1. An SOI device, comprising:
a first composite structure comprising:
a substrate isolation layer disposed on or above the substrate layer,
a buried layer disposed on or above the substrate isolation layer,
a semiconductor layer disposed on or above the buried layer, and
a trench structure disposed within the first composite structure,
a second composite structure disposed on side walls of the trench structure, wherein the second composite structure comprises:
a first isolation layer covering the part of the side walls formed by the semiconductor layer, and formed by an upper part of the buried layer, and
a conductive contact layer covering the first isolation layer, and covering the part of the side walls formed by a lower part of the buried layer thereby electrically contacting the part of the side walls formed by the lower part of the buried layer.
2. The SOI device according to claim 1, wherein the trench structure extends to a bottom surface of the buried layer.
3. The SOI device according to claim 1, wherein the second composite structure comprises a second isolation layer which covers a conductive layer.
4. The SOI device according to claim 1, wherein remaining space within the trench structure is filled with filling material.
5. The SOI device according to claim 1, wherein remaining space within the trench structure is filled with conductive material which extends through the substrate isolation layer into the substrate layer.
6. The SOI device according to claim 1, wherein a trench gap in the upper part of the buried layer is wider than the trench gap in the lower part of the buried layer.
7. The SOI device according to claim 1, wherein the trench structure divides the semiconductor layer into a plurality of semiconductor element regions, wherein at least one semiconductor element is formed within each semiconductor element region.
a first composite structure comprising a first buried layer and a second buried layer, the second buried layer disposed above the first buried layer;
a trench structure disposed within the first composite structure; and
a second composite structure disposed on side walls of the trench structure, wherein the second composite structure comprises
a first isolation layer covering at least the part of the side walls formed by third and fourth buried layers disposed above the second buried layer,
a first conductive contact layer covering the first isolation layer, and covering at least a part of the side walls formed by the second buried layer thereby electrically contacting the part of the side walls formed by the second buried layer,
a second isolation layer covering the first contact layer and at least a part of the side walls formed by the first buried layer, and
a second conductive layer covering the second isolation layer, and covering at least a part of the side walls formed by the first buried layer thereby electrically contacting the part of the side walls formed by the first buried layer.
9. The device according to claim 8, wherein the first isolation layer extends down to a top surface of the second buried layer, but does not extend into the second buried layer, and wherein the second isolation layer extends down to a top surface of the first buried layer, but does not extend into the first buried layer.
10. The device according to claim 8, wherein the device is a SOI device or a semiconductor device.
a buried layer disposed above the substrate layer;
a semiconductor layer disposed above the buried layer;
a trench structure disposed within the semiconductor layer and the buried layer, the trench structure having side walls formed by the semiconductor layer, an upper portion of the buried layer, a middle portion of the buried layer and a lower portion of the buried layer;
a first isolation layer within the trench structure covering at least a portion of the side walls formed by the semiconductor layer and by the upper portion of the buried layer;
a conductive contact layer covering the first isolation layer, and covering the side walls formed by the middle portion of the buried layer thereby electrically contacting the side walls formed by the middle portion of the buried layer; and
a second isolation layer covering the contact layer and at least a portion of the side walls formed by the lower portion of the buried layer.
12. The semiconductor device according to claim 11, wherein the trench structure extends into the substrate layer, and wherein the second isolation layer covers side walls of the trench structure formed by the substrate layer.
13. The semiconductor device according to claim 11, wherein the second isolation layer covers a bottom surface of the trench structure.
14. The semiconductor device according to claim 11, further comprising a filling material that fills a remaining space within the trench structure.
15. The semiconductor device according to claim 14, wherein the filling material comprises a conductive material that contacts the substrate layer.
16. The semiconductor device according to claim 11, wherein a trench gap in the upper portion of the buried layer is wider than a trench gap in the middle portion of the buried layer, and wherein the trench gap within the middle portion of the buried layer is wider than a trench gap within the lower portion of the buried layer.
17. The semiconductor device according to claim 11, wherein the trench structure divides the semiconductor layer into a plurality of semiconductor element regions, the device further comprising at least one semiconductor element disposed within each semiconductor element region.
a first composite structure comprising a substrate layer, a buried layer disposed on or above the substrate layer, and a semiconductor layer disposed on or above the buried layer;
a first isolation layer covering at least the part of the side walls formed by the semiconductor layer and the part of the side walls formed by an upper part of the buried layer,
a conductive contact layer covering the first isolation layer, and covering the part of the side walls formed by a middle part of the buried layer thereby electrically contacting the part of the side walls formed by the middle part of the buried layer, and
a second isolation layer covering the contact layer and at least the part of the side walls formed by a lower part of the buried layer.
19. The semiconductor device according to claim 18, wherein the trench structure extends into the substrate layer, and wherein the second isolation layer covers the part of the side walls formed by the substrate layer.
20. The semiconductor device according to claim 18, wherein the second isolation layer covers a bottom surface of the trench structure.
21. The semiconductor device according to claim 18, wherein remaining space within the trench structure is filled with filling material.
22. The semiconductor device according to claim 18, wherein remaining space within the trench structure is filled with conductive material which contacts the substrate layer.
23. The semiconductor device according to claim 18, wherein a trench gap in the upper part of the buried layer is wider than a trench gap in the middle part of the buried layer, and wherein the trench gap within the middle part of the buried layer is wider than a trench gap within the lower part of the buried layer.
24. The semiconductor device according to claim 18, wherein the trench structure divides the semiconductor layer into a plurality of semiconductor element regions, wherein at least one semiconductor element is formed within each semiconductor element region. Description
An embodiment of the present invention generally relates to a method of manufacturing a semiconductor device, a method of manufacturing a SOI device, a semiconductor device, and a SOI device.
It is an ongoing goal to increase the computational power of computing devices. In order to increase the computational power, the integration depth of the computing devices may be increased. In order to keep manufacturing costs low, manufacturing processes may be used which enable the formation of structures of high precision and, at the same time, however, keep the manufacturing effort as low as possible.
FIG. 1 shows a flow chart of a method of manufacturing a semiconductor device according to one embodiment of the present invention;
FIG. 2 shows a possible embodiment indicating how the method shown in FIG. 1 could be carried out in detail;
FIG. 3 shows a flow chart of a method of manufacturing a SOI device according to one embodiment of the present invention;
FIG. 4 shows a flow chart of a method of manufacturing a SOI device according to one embodiment of the present invention;
FIG. 5 shows a cross-sectional view of a processing stage of a method of manufacturing a SOI device according to one embodiment of the present invention;
FIG. 6 shows an enlarged view of the processing stage shown in FIG. 5;
FIG. 7 shows a cross-sectional view of a processing stage of a method of manufacturing a SOI device according to one embodiment of the present invention;
FIG. 8 shows a cross-sectional view of a processing stage of a method of manufacturing a SOI device according to one embodiment of the present invention;
FIG. 9 shows a cross-sectional view of a processing stage of a method of manufacturing a SOI device according to one embodiment of the present invention;
FIG. 10 shows a cross-sectional view of a processing stage of a method of manufacturing a SOI device according to one embodiment of the present invention;
FIG. 11 shows a cross-sectional view of a processing stage of a method of manufacturing a SOI device according to one embodiment of the present invention;
FIG. 12 shows a cross-sectional view of a semiconductor device according to one embodiment of the present invention;
FIG. 13 shows a cross-sectional view of a SOI device according to one embodiment of the present invention;
FIG. 14 shows a cross-sectional view of a SOI device according to one embodiment of the present invention;
FIG. 15 shows a cross-sectional view of a semiconductor device according to one embodiment of the present invention; and
FIG. 16 shows a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
FIG. 1 shows a method 100 of manufacturing a semiconductor device according to one embodiment of the present invention.
At 101, the manufacturing method is started.
At 102, a trench structure is formed within a first composite structure including a substrate layer, a buried layer being disposed on or above the substrate layer, and a semiconductor layer being disposed on or above the buried layer.
At 103, a second composite structure is formed on the side walls of the trench structure. The second composite structure includes a first isolation layer covering at least the part of the side walls formed by the semiconductor layer and the part of the side walls formed by an upper part of the buried layer, a contact layer covering the isolation layer and the part of the side walls formed by a middle part of the buried layer, and a second isolation layer covering the contact layer and at least the part of the side walls formed by a lower part of the buried layer.
At 104, the method 100 is terminated.
The process described at 103 may be repeated several times, i.e., after having formed the second composite structure, a third composite structure may be formed on the side walls of the remaining trench structure. The third composite structure may, for example, include a second contact layer covering at least the second isolation layer (and optionally the part of the side walls formed by an upper part of a further semiconductor layer or a further buried layer disposed below the buried layer), and a third isolation layer covering the second contact layer and the part of the side walls formed by a part (e.g., a lower part) of the further semiconductor or the further buried layer. If necessary, further composite structures may be formed on the third composite structure. In this way, each contact layer contacts an individual semiconductor layer or buried layer. This means that an arbitrary number of layers of a stack of layers can be contacted by one single trench (�multi shell approach�).
According to one embodiment of the present invention, the trench structure may be formed such that at 102 it extends into the substrate layer, wherein the second isolation layer is formed such that it covers the part of the side walls formed by the substrate layer.
According to one embodiment of the present invention, the second isolation layer is formed such that at 103 it covers the bottom surface of the trench structure.
According to one embodiment of the present invention, the remaining space within the trench structure is filled with filling material after having carried out step 103.
According to one embodiment of the present invention, the remaining space within the trench structure is filled with conductive material such that the conductive material contacts the substrate layer after having carried out 103.
FIG. 2 shows a method 200 illustrating how the method 100 could be carried out in detail.
At 201, a first composite structure including a substrate layer, a buried layer being disposed on or above the substrate layer, and a semiconductor layer being disposed on or above the buried layer is formed.
At 202, a trench structure is formed within the first composite structure, wherein a trench structure extends into the buried layer.
At 203, a first isolation layer covering the side walls of the trench structure is formed.
At 204, the depth of the trench structure is enlarged such that the bottom surface of the trench structure still is located within the buried layer.
At 205, a conductive layer is formed such that it covers the isolation layer and the exposed side walls of the enlarged parts of the trench structure.
At 206, the depth of the trench structure is enlarged such that the trench structure extends into the substrate.
At 207, a second isolation layer is formed which covers the conductive layer and the exposed side walls of the enlarged part of the trench structure.
According to one embodiment of the present invention, a first isolation layer is formed at 203 using a thermal oxidization treatment that causes the side walls of the trench structure to be thermally oxidized. The first isolation layer may also be formed using a deposition process.
According to one embodiment of the present invention, in order to form or enlarge the trench structure at 202, 204 and 206, an etching process is used.
FIG. 3 shows a method 300 of manufacturing a SOI (silicon on insulator) device according to one embodiment of the present invention.
At 301, the method is started.
At 302, a trench structure is formed within a first composite structure including a substrate layer, a substrate isolation layer being disposed on or above the substrate layer, a buried layer being disposed on or above the substrate isolation layer, and a semiconductor layer being disposed on or above the buried layer.
At 303, a second composite structure is formed on the side walls of the trench structure, wherein the second composite structure includes: a first isolation layer covering the part of the side walls formed by the semiconductor layer, and formed by an upper part of the buried layer; a contact layer covering the isolation layer and the part of the side walls formed by a lower part of the buried layer.
At 304, the method is terminated.
The process described at 303 may be repeated several times, i.e., after having formed the second composite structure, a third composite structure may be formed on the side walls of the remaining trench structure. The third composite structure may, for example, include a second isolation layer covering the contact layer (and optionally the part of the side walls formed by an upper part of a further semiconductor layer or a further buried layer disposed below the buried layer), and a further contact layer covering the second isolation layer and the part of the side walls formed by a part (e.g., a lower part) of the further semiconductor or the further buried layer. If necessary, further composite structures may be formed on the third composite structure. In this way, each contact layer contacts an individual semiconductor layer or buried layer. This means that an arbitrary number of layers of a stack of layers can be contacted by one single trench.
According to one embodiment of the present invention, the trench structure is formed at 302 such that it extends to the bottom surface of the buried layer, i.e., the bottom surface of the trench structure coincides with the bottom surface of the buried layer.
According to one embodiment of the present invention, the second isolation layer is generated such that at 303 that it covers the conductive layer.
According to one embodiment of the present invention, the remaining space within the trench structure is filled with filling material after having carried out at 303.
According to one embodiment of the present invention, after having carried out at 303, the remaining space within the trench structure is filled with conductive material which extends through the substrate isolation layer into the substrate layer.
FIG. 4 shows a method 400 illustrating how the method 300 shown in FIG. 3 could be carried out in detail.
At 401, a first composite structure is formed including a substrate layer, a substrate isolation layer being disposed on or above the substrate layer, a buried layer being disposed on or above the substrate isolation layer, and a semiconductor layer being disposed on or above the buried layer.
At 402, a trench structure is formed within the first composite structure, wherein the trench structure extends into the buried layer.
At 403, a first isolation layer is formed covering the side walls of the trench structure.
At 404, the depth of the trench structure is enlarged such that the bottom surface of the trench structure coincides with the top surface of the substrate isolation layer.
At 405, a conductive layer is formed such that it covers the isolation layer and the exposed side walls of the enlarged trench structure.
At 406, a second isolation layer is formed which covers the contact layer.
According to one embodiment of the present invention, after having carried out 405, the depth of the trench structure is enlarged such that the trench structure extends into the substrate, wherein the substrate layer is contacted by filling remaining space within the trench structure with conductive material.
According to one embodiment of the present invention, the first isolation layer is formed at 403 using a thermal oxidization of the side walls of the trench structure. The first isolation layer may also be formed using a deposition process.
According to one embodiment of the present invention, the generation or the enlargement of the trench structure is carried out using an etching process.
In the following description, making reference to FIGS. 5 to 11, a method of manufacturing a SOI device will be explained.
FIG. 5 shows SOI base material 510 which is used as a starting point for the processing steps described in the following. The SOI base material 510 includes a semiconductor substrate layer 501, a substrate isolation layer 502 being disposed on the semiconductor substrate layer 501, and a semiconductor buried layer 503 being disposed on the substrate isolation layer 502. A magnified view of an area O is shown in FIGS. 6-11 that follow.
FIG. 6 shows a processing stage A in which a composite structure 500 has been formed including a semiconductor substrate layer 501, a substrate isolation layer 502 being disposed on the semiconductor substrate layer 501, a semiconductor buried layer 503 being disposed on the substrate isolation layer 502, and an EPI substrate layer 504 being disposed on the semiconductor buried layer 503. Further, a masking layer 505 and a resist layer 506 being disposed on the masking layer 505 have been provided. The resist layer 506 has been patterned (using, for example, a light exposure process), i.e., the resist layer 506 has been removed within the area denoted by reference numeral 507.
FIG. 7 shows a processing stage B in which a trench structure 700 has been formed within the composite structure 500. The trench structure 700 has been formed such that its bottom surface 701 falls below the top surface of the semiconductor buried layer 503. The trench structure 700 has been formed using the structured resist layer 506 as an etching mask during an etching process. Instead of a resist layer, other layers like a hard mask layer may be used in order to form the trench structure 700. The structured resist layer 506 has been removed after having carried out the etching process.
In a processing stage C shown in FIG. 8, a first isolation layer 800 has been formed which covers the side walls 702 of the trench structure 700 as well as the bottom surface 701 of the trench structure 700. The first isolation layer 800 may, for example, be formed by oxidizing the side walls 702 and the bottom surface 701 of the trench structure 700, thereby converting semiconductor material into insulation material. As a consequence, the bottom surface of the first isolation layer 800 is located within the semiconductor buried layer 503.
FIG. 9 shows a processing stage D in which the depth of the trench structure 700 has been enlarged such that the bottom surface 701 of the enlarged trench structure 700 coincides with the top surface of the substrate isolation layer 502. The enlargement of the depth of the trench structure 700 may, for example, be carried out using an etching process or other processes.
FIG. 10 shows a processing stage E in which the first isolation layer 800 has been covered by a conductive layer 1000, wherein the conductive layer 1000 also covers the exposed parts 900 of the side walls of the enlarged trench structure shown in FIG. 9. The conductive layer 1000 does not cover the top surface of the substrate isolation layer 502 in order to prevent a short circuit between different side walls of the trench structure 700. The conductive layer 1000 is also known as a �sinker� or as a �buried layer contact� and may consist of materials like metal, poly silicon, or silicide. FIG. 11 shows a processing stage F in which a second isolation layer 1100 has been formed on the conductive layer 1000 and the top surface of the substrate isolation layer 502. Further, remaining space 1101 within the trench structure 700 has been filled with filling material 1102. The first isolation layer 800, the conductive layer 1000 and the second isolation layer 1100 together form a second composite structure 1103.
As can be derived from FIG. 11, the first isolation layer 800 covers the part 1104 of the side walls formed by the semiconductor layer 504, and formed by an upper part of the buried semiconductor layer 503. This ensures that no short circuit between the semiconductor layer 504 and the conductive layer 1000 exists. As a consequence, the lateral dimensions of the conductive layer 1000 covers the isolation layer 800 and the part 1105 of the side walls formed by a lower part of the buried semiconductor layer 503. Thus, the trench structure 700 as shown in FIG. 11 has a first trench gap 1106 in the upper part of the trench structure 700, and has a second trench gap 1107 in the lower part of the trench structure 700, wherein the first trench gap 1106 is larger than the second trench gap 1107.
The semiconductor buried layer 503 may be of the same or the opposite conductive type as that of the EPI substrate layer 504.
FIG. 12 shows a semiconductor device 1200 according to one embodiment of the present invention. The semiconductor device 1200 has the same architecture as the SOI device shown in FIG. 11 except of the following differences: The substrate isolation layer 502 is omitted, i.e., the buried semiconductor layer 503 is directly arranged on the semiconductor substrate layer 501; further, the bottom end of the conductive layer 1000 does not coincide with the bottom surface of the buried semiconductor layer 503, but is located within the buried semiconductor layer 503, i.e., there is a distance between the bottom surface of the conductive layer 1000 and the bottom surface of the buried semiconductor layer 503; last, the bottom surface of the second isolation layer 1100 does not coincide with the bottom surface of the buried layer 503, but is located within the semiconductor substrate layer 501. As a consequence, the trench structure 700 of the semiconductor device 1200 has a first trench gap 1106, a second trench gap 1107, and a third trench gap 1201, wherein the first trench gap 1106 which is located in an upper part of the trench structure 700 is larger than the second trench gap 1107 which is located in a middle part of the trench structure 700, and wherein the second trench gap 1107 is larger than the third trench gap 1201 located in a lower part of the trench structure 700. In other words: The first isolation layer 800 covers the part 1104 of the side walls of the trench structure 700 formed by the semiconductor layer 504 and formed by an upper part of the buried semiconductor layer 503. The conductive layer 1000 covers the first isolation layer 800 and the part 1105 of the side walls formed by a middle part of the buried semiconductor layer 503. The second isolation layer 1100 covers the conductive layer 1000 and the part 1202 of the side walls of the trench structure 700 formed by a lower part of the buried semiconductor layer 503 and an upper part of the semiconductor substrate layer 501.
The semiconductor device 1200 can be manufactured similar to the SOI device shown in FIG. 11. Differences are that the bottom surface of the trench structure 700 is located above the top surface of the semiconductor substrate layer 501 before forming the conductive layer 1000, and that, after having formed the conductive layer 1000, the trench structure is enlarged a second time such that it extends into the semiconductor substrate layer 501.
FIG. 13 shows a SOI device 1300 including a plurality of trench structures 700 which are identical to the trench structure as shown in FIG. 11. The trench structures 700 separate the semiconductor layer 504 into semiconductor element regions 1301, wherein at least one semiconductor element may be formed within each semiconductor element region 1301. The semiconductor element regions 1301 are electrically isolated from each other by the trench structures 700.
FIG. 14 shows a further SOI device 1400 according to one embodiment of the present invention. The architecture of the SOI device 1400 is similar to the architecture of the SOI device 1300. Differences are that the filling material 1102 is not isolated against the semiconductor substrate layer 501 by the second isolation layer 1100 and the substrate isolation layer 502, but extends through the second isolation layer 1100 and the substrate isolation layer 502, thereby contacting the semiconductor substrate layer 501. That is, an electrical contact can be provided (assuming that the filling material 1102 is conductive material) which contacts the semiconductor substrate layer 501 from the top surface of the SOI device 1400. In order to manufacture the SOI device 1400, the trench structure 700 may be enlarged in order to extend through the second isolation layer 1100 and the substrate isolation layer 502 after having formed the second isolation layer 1100 (using, for example, an etching process).
The architectures shown in FIGS. 13 and 14 may also be applied to the case where the semiconductor device only includes one semiconductor element (i.e., includes only one semiconductor element region). In this case, the trench structure 700 may be used to completely or at least partly surround the single semiconductor element.
The semiconductor element may, for example, be a transistor, a diode, or a resistor.
As can be derived from FIG. 13, the first isolation layer 800 covers the part 1104 of the side walls formed by the semiconductor layer 504, and formed by an upper part of the buried semiconductor layer 503. This ensures that no short circuit between a semiconductor element formed within the semiconductor element region and the conductive layer 1000 via the semiconductor layer 504 exists. Instead, the current is �forced� to use the buried semiconductor layer 503 in order to reach the conductive layer 1000. As a consequence, the lateral dimensions between neighboring trench structures 700 can be reduced, compared to solutions which do not use the first isolation layer 800.
FIG. 15 shows a semiconductor device 1500, the architecture of which being similar to the semiconductor device 1200 shown in FIG. 12. A difference is that the filling material 1102 directly contacts the semiconductor substrate layer 501, i.e., is not isolated against the semiconductor substrate layer 501 by the second isolation layer 1100. In order to manufacture the semiconductor device 1500, the trench structure may be enlarged in order to extend through the second semiconductor layer 1100 into the semiconductor substrate layer 501 after having formed the second isolation layer 1100. In this way, an electrical contact can be provided (assuming that the filling material 1102 is conductive material) which contacts the semiconductor substrate layer 501 from the top surface of the semiconductor device 1500.
FIG. 16 shows a device 1600 according to one embodiment of the present invention. The device 1600 includes: a first composite structure 1601 including a first buried layer 1602 and a second buried layer 1603 disposed above the first buried layer 1602; a trench structure 1604 formed within the first composite structure 1601; and a second composite structure 1605 being provided on the side walls of the trench structure 1604, wherein the second composite structure 1605 includes a first isolation layer 1606 covering at least the part of the side walls formed by layers 1607 disposed above the second buried layer 1603, a first contact layer 1608 covering the first isolation layer 1606 and at least a part of the side walls formed by the second buried layer 1603, a second isolation layer 1609 covering the first contact layer 1608 and at least a part of layer(s) 1610 disposed between the first buried layer 1602 and the second buried layer 1603, and a second conductive layer 1611 covering the second isolation layer 1609 and at least a part of the side walls formed by the first buried layer 1602. A third isolation layer 1612 is provided on the second conductive layer 1611.
Following the principle shown in FIG. 16, it is possible to individually contact an arbitrary number of buried layers using a composite structure of isolation layers and contacting layers which alternate with each other.
According to one embodiment of the present invention, the device is a SOI device or a semiconductor device.
According to one embodiment of the present invention, the first isolation layer 1606 extends down to the top surface of the second buried layer 1603, however does not extend into the second buried layer 1603 (in contrast to the embodiment shown in FIG. 16), and wherein the second isolation layer 1609 extends down to the top surface of the first buried layer 1602, however does not extend into the first buried layer 1602 (in contrast to the embodiment shown in FIG. 16). This may also be applied to all other embodiments of the present invention. That is, the isolation layers of the composite structures may stop on the top surfaces of the buried layers, however not extend into the buried layers.
According to one embodiment of the present invention, a method is provided to contact a buried layer and to isolate different devices in one lithography step and one trench etch process.
According to one embodiment of the present invention, a trench is used with a multi-shell structure that requires only one mask step and only one trench etch process for the realization of an isolated sinker and an isolation structure which also may provide a substrate contact. Effects of this embodiment are that the devices are completely shielded, the structure saves die area, and the thermal budget is low. The generation of sinker and isolation which use different mask steps, which are diffused from the surface, and which consume a lot of die area or used separate trench etch processes can be avoided.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5448083 *Jun 15, 1994Sep 5, 1995Kabushiki Kaisha ToshibaInsulated-gate semiconductor deviceUS5614750Jun 29, 1995Mar 25, 1997Northern Telecom LimitedBuried layer contact for an integrated circuit structureUS6429477Oct 31, 2000Aug 6, 2002International Business Machines CorporationShared body and diffusion contact structure and method for fabricating sameUS6689695 *Jun 28, 2002Feb 10, 2004Taiwan Semiconductor Manufacturing CompanyMulti-purpose composite mask for dual damascene patterningUS7485926Jan 30, 2004Feb 3, 2009X-Fab Semiconductor Foundries AgSOI contact structuresUS20020053715 *Nov 8, 2001May 9, 2002Min KimTrench isolation structure having a curvilinear interface at upper corners of the trench isolation region, and method of manufacturing the sameUS20030094654 *Aug 9, 2002May 22, 2003International Business Machines CorporationMethod and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devicesUS20030193077Apr 11, 2003Oct 16, 2003Nec Electronics CorporationBipolar transistor and method of fabricating the sameUS20040262659 *Jun 28, 2004Dec 30, 2004Yoshinori MatsubaraSemiconductor memory with trench capacitor and method of manufacturing the sameUS20060176211 *Mar 20, 2006Aug 10, 2006Farrokh MohamadiWafer scale antenna module with a backside connectivityDE10129846C1Jun 21, 2001Nov 14, 2002Infineon Technologies AgProcess for electrically contacting switching elements used in communications networks comprises applying a first layer on a first switching component, forming a hole in the first layer, and further processingDE10239310B4Aug 27, 2002Nov 3, 2005Infineon Technologies AgVerfahren zur Herstellung einer elektrisch leitenden Verbindung zwischen einer ersten und einer zweiten vergrabenen HalbleiterschichtDE10303643B3Jan 30, 2003Sep 9, 2004X-Fab Semiconductor Foundries AgElectrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stackDE19702121C1Jan 22, 1997Jun 18, 1998Siemens AgVertical chip interconnection productionWO2007016446A2Jul 31, 2006Feb 8, 2007Texas Instruments IncDielectric isolated body biasing of silicon on insulator* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8872281 *Aug 9, 2012Oct 28, 2014International Business Machines CorporationSilicided trench contact to buried conductive layer* Cited by examinerClassifications U.S. Classification257/508, 257/E29.287, 438/295, 438/311, 438/149, 257/347International ClassificationH01L21/40Cooperative ClassificationH01L21/743, H01L21/84European ClassificationH01L21/84, H01L21/74BLegal EventsDateCodeEventDescriptionJan 15, 2015FPAYFee paymentYear of fee payment: 4Oct 13, 2007ASAssignmentOwner name: INFINEON TECHNOLOGIES AG, GERMANYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DEHLINGER, GABRIEL;REEL/FRAME:019958/0663Effective date: 20070817RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services