Source: https://patents.google.com/patent/US20160316567A1/en
Timestamp: 2019-06-18 21:44:57
Document Index: 64850377

Matched Legal Cases: ['art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art) 15', 'art) 15', 'art 11', 'art 11', 'art 11']

US20160316567A1 - Circuit Board Embedding a Power Semiconductor Chip - Google Patents
Circuit Board Embedding a Power Semiconductor Chip Download PDF
US20160316567A1
US20160316567A1 US15/134,984 US201615134984A US2016316567A1 US 20160316567 A1 US20160316567 A1 US 20160316567A1 US 201615134984 A US201615134984 A US 201615134984A US 2016316567 A1 US2016316567 A1 US 2016316567A1
US15/134,984
US10062671B2 (en
2015-04-22 Priority to DE102015106151.1A priority Critical patent/DE102015106151A1/en
2015-04-22 Priority to DE102015106151 priority
2015-04-22 Priority to DE102015106151.1 priority
2016-04-21 Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
2016-05-12 Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GRUBER, MARTIN, KESSLER, ANGELA, SCHARF, THORSTEN
2016-10-27 Publication of US20160316567A1 publication Critical patent/US20160316567A1/en
2018-08-28 Publication of US10062671B2 publication Critical patent/US10062671B2/en
The power terminal connector 30 is electrically connected to the first load electrode 21 of the power semiconductor chip 20. The power terminal connector 30 is configured as an external terminal of the semiconductor module 100A. The power terminal connector 30 may allow to conduct high currents used by external applications to or from the semiconductor module 100A. To that end, the power terminal connector 30 may be designed to have a connector part or element 32 projecting over a first (upper) surface 10 a of the circuit board 10. The connector element 32 of the terminal connector 30 may have engaging means for being assembled or attached to external power circuitry. The engaging means may be designed, e.g., as a hole 33, in particular a threaded hole, or a clamping means (not shown), a threaded bolt (see FIG. 8A), etc. If, e.g., a threaded bolt is used, the threaded bolt may be integral with the connector element 32 or may be fixedly inserted or screwed in the hole 33 thereof and may provide a thread for screwing the semiconductor module 100A to another threaded hole (not shown) or an external application.
The power terminal connector 30 or, more specifically, the connector element 32 thereof may have a height Hi as measured from the first (upper) surface 10 a of the circuit board 10 to an upper surface 32 a of the connector element 32 of the power terminal connector 30 that is equal to or greater than 5 mm, 8 mm, 10 mm, 12 mm, 14 mm, 16 mm, 18 mm, or 20 mm.
The power terminal connector 30 is fixedly secured to the circuit board 10. By way of example, the first electrically conducting layer 11 of the circuit board 10 may comprise holes 12 each configured to receive a press-fit pin 34 of the power terminal connector 30. More specifically, an end face 35 of the power terminal connector 30 may be equipped with an array of press-fit pins 34 protruding from the end face 35 in a direction normal to the end face 35 (and also normal to the first (upper) surface 10 a or the circuit board 10, to which the end face 35 may abut) and configured to establish force-locked connections with a corresponding array of holes 12 in the first electrically conductive layer 10. The press-fit pins 34 may pass through the circuit board 10 and may protrude from a second (bottom) surface 10 b of the circuit board 10.
A press-fit connection between the power terminal connector 30 and the first electrically conductive layer 11 of the circuit board 10 provides for high mechanical stability and high thermal and electrical conductivity. That is, electrical current and heat is effectively transferred from the power semiconductor chip 20 via the first electrically conductive layer 11 to the power terminal connector 30. In addition, as the power terminal connector 30 is positioned directly above the power semiconductor chip 20, heat dissipation paths through the first electrically conductive layer 11 are short. Further, heat removal from the power semiconductor chip 20 may be assisted by direct heat transfer from the power semiconductor chip 20 via the interface between the first (upper) surface 10 a of the circuit board 10 and the end face 35 of the power terminal connector 30 to the power terminal connector 30. Thus, in conclusion, the power semiconductor chip 20 embedded in the circuit board 10 is effectively coupled to the power terminal connector 30 in terms of cooling and current supply.
FIG. 1B illustrates an exemplary semiconductor module 100B. Semiconductor module 100B may be similar or identical to semiconductor module 100A except that except that the hole 33 of the connector element is a blind hole or bore rather than a through-hole. Thus, the (bottom) end face 35 of the connector element 32 may, e.g., be a continuous face which may, e.g., completely cover and/or abut to the area of the first (upper) surface 10 a of the circuit board 10 located under the connector element 32. That way, heat removal from the semiconductor chip 20 is increased by additional heat dissipation from the top of the semiconductor chip 20 via the first (upper) surface 10 a of the circuit board 10 into the bulk connector element 32.
FIG. 3 illustrates an exemplary semiconductor module 300. Features of the semiconductor module 300 may be identical or similar to corresponding features of the semiconductor modules 100A, 100B, 200 described above and vice-versa, and reference is made to the description herein to avoid reiteration. Further, the semiconductor module 300 uses a multi-layer circuit board 10. In the multi-layer circuit board 10 at least a second electrically conductive layer 15 is provided. The second electrically conductive layer 15 may be arranged above the first electrically conductive layer 11, e.g. between the first electrically conductive layer 11 and the power semiconductor chip 20 mounted thereon and the first (upper) surface 10 a of the circuit board 10.
By way of example, as illustrated in FIG. 3, the second electrically conductive layer 15 may be structured to provide for a first conductor trace 15 a which is connected by vias 16 to a control electrode 23, e.g. gate electrode, of the power semiconductor chip 20. As an example, the first conductor trace 15 a of the second electrically conductive layer 15 is interconnected to an external terminal 40 of the semiconductor module 300. The external terminal 40 may, in this example, be a control terminal for, e.g., providing an external control signal to the control electrode 23 of the power semiconductor chip 20.
Further, as will be described in more detail further below, the semiconductor module 300 may be equipped with one or more electronic components. Reference sign 40 may also be interpreted as referring to such electronic component which, in the example of FIG. 3, may be mounted on the first (upper) surface 10 a of the circuit board 10. The electronic component may also be mounted on the second (lower) surface 10 b of the circuit board 10 or may be embedded within the circuit board 10 (see, e.g., FIGS. 5 and 6).
Further, by way of example, the second electrically conductive layer 15 may comprise a second conductor trace 15 b which is configured to be electrically connected to a load electrode 22, e.g., source electrode of the power semiconductor chip 20. Again, the connection between the load electrode 22 and the second conductor trace 15 b of the second electrically conductive layer 15 may be provided by a number of vias 16 penetrating the insulating (dielectric) material provided between the power semiconductor chip 20 (or the first electrically conductive layer 11) and the second electrically conductive layer 15.
In this example but also in the other examples disclosed herein the first electrically conductive layer 11 may be structured. By way of example, a first part 11 a of the first electrically conductive layer 11 may be electrically connected to a load electrode 22, e.g. the source electrode of the power semiconductor chip 20, and a second part 11 b of the first electrically conductive layer 11 may be connected to a control electrode 23, e.g. a gate electrode of the power semiconductor chip 20. The first part 11 a and the second part 11 b of the first electrically conductive layer 11 may be insular, i.e. electrically disconnected or insulated from each other. That way, the first electrically conductive layer 11 may not only be used to serve as a chip carrier and/or heat removal means and/or mounting platform for the power terminal connector 30 but, in addition, as a multi-current or multi-signal (e.g. load current and/or control signal) conductor for routing load currents and/or control signals across the circuit board 10.
Semiconductor module 500 comprises an additional electronic component 50 embedded or encased in the circuit board 10. By way of example, the electronic component 50 may be mounted on a third part 11 c of the first conductive layer 11. However, it is also possible that the electronic component 50 is mounted on another conductive layer of the circuit board 10 or is embedded in the circuit board 10 without any support or carrier. As mentioned previously, it may also be mounted on one of the first (upper) surface 10 a and/or the second (lower) surface 10 b of the circuit board 10.
The electronic component 50 may be electrically connected to a control electrode 23 of the power semiconductor chip 20. By way of example, the electrical connection between an I/O electrode of the electronic component 50 and the control electrode 23 of the power semiconductor chip 20 may be provided by the second electrically conductive layer 15 or, more specifically, by a conductor trace 15 a thereof. Another possibility, as already explained in conjunction with FIG. 4, is to use the first electrically conductive layer 11 or a structured part 11 b thereof to interconnect the control electrode 23 of the semiconductor chip 20 to the electronic component 50.
In FIG. 6, as an example, a conductor trace (or part) 15 b of the second electrically conductive layer 15 is connected to the right-hand power terminal connector 30. The right-hand power terminal connector 30 may, in this example, be a load current terminal for, e.g., providing the source current for the right-hand power semiconductor chip 20. It is to be noted that in the example of FIG. 6, the right-hand power terminal connector 30 may be secured to the second electrically conductive layer 15 rather than to the first electrically conductive layer 11. All connecting techniques described above in relation to the connection between the first electrically conductive layer 11 and the power terminal connector 30, including press-fitting and soldering, may be used.
The left-hand power semiconductor chip 20 may, e.g., be located in a flip-chip orientation on the first electrically conductive layer 11, and an external terminal 70 of the semiconductor module 600 may be connected via a conductor trace (or part) 15 c of the second electrically conductive layer 15 to a load electrode 21, e.g. a drain electrode, of the left-hand side power semiconductor chip 20. Here, by way of example, the left-hand power terminal connector 30 may be secured to the first electrically conductive layer 11 as described previously.
FIG. 7 is an exemplary illustration of another semiconductor module 700. Semiconductor module 700 is similar to semiconductor module 600 except that both power semiconductor chips 20 are mounted in a face-up orientation on the first electrically conductive layer 11. The first conductive layer 11 may be separated into a first part 11 used as a carrier for the left hand power semiconductor chip 20 and a second part 11′ used as a carrier for the right hand semiconductor chip 20. As described before, a structured second electrically conductive layer 15 may optionally be provided for signal routing and/or load current conduction. By way of example, the source electrode of the left hand power semiconductor chip 20 may be connected to the drain electrode of the right hand power semiconductor chip 20 by inter-layer vias 16 connecting the second conductor trace 15 b of the second electrically conductive layer 15 to the second part 11′ of the first conductive layer 11.
In the semiconductor module 800 as shown in FIG. 8A, the power terminal connectors 30 are equipped with a threaded bolt 38. The threaded bolt 38 may be an integral part of the connector element 32. Thus, in this and also in other examples described herein (see, e.g., FIG. 1B), the (bottom) end face 35 of the connector element 32 may, e.g., be a continuous face which, e.g., completely covers and/or abuts to the area of the first (upper) surface 10 a of the circuit board 10 located under the connector element 32.
At the (bottom) second surface 10 b of the circuit board 10, the press-fit pins 34 may pass through the circuit board 10 and may protrude from the second surface 10 b. As apparent in FIG. 8B, the press-fit pins 34 may have a frame-like shape with an inner zone which is void of press-fit pins 34 (the same may apply for any kind of pins or projections 44). The power semiconductor chip 20 (not visible in FIG. 8B) may be positioned within this inner zone and may thus be laterally surrounded by the frame-like array of press-fit pins 34 (or projections 44). That way, the electrical and thermal connection to the power semiconductor chip 20 via the first conductive layer 11 and the press-fit pins 34 (or projections 44) is very close to the power semiconductor chip 20 and may use the entire peripheral region of the power semiconductor chip 20. Thus, together with the location of the power terminal connector 30 directly above the power semiconductor chip 20, optimum conditions for heat and current transfer are created.
It is to be noted that the second (bottom) surface 10 b of the circuit board 10 may remain unobstructed and may still remain available for further cooling equipment such, e.g., the application of one or more heat sinks (not shown) or other cooling tools. In this case, the cooling caused by the power terminal connectors 30 may act as an additional cooling to increase the cooling effected by the heat sinks attached to the second (bottom) surface 10 b of the circuit board 10.
a power semiconductor chip embedded in the circuit board, the power semiconductor chip having a first load electrode; and
a power terminal connector electrically connected to the first load electrode,
wherein the power semiconductor chip is positioned laterally within a footprint zone of the power terminal connector.
a circuit board comprising a first electrically conductive layer and a second electrically conductive layer;
a plurality of power semiconductor chips embedded in the circuit board, each power semiconductor chip having a first main face mounted on the first electrically conductive layer or mounted on the second electrically conductive layer; and
a plurality of power terminal connectors each of which is electrically connected to the first electrically conductive layer or to the second electrically conductive layer,
wherein at least one of the embedded power semiconductor chips is positioned laterally within a footprint zone of at least one of the power terminal connectors.
18. A method of manufacturing a semiconductor module, the method comprising:
embedding a power semiconductor chip into a circuit board, the power semiconductor chip having a first load electrode connecting to a first electrically conductive layer of the circuit board;
placing a power terminal connector over the circuit board so as to be positioned over the power semiconductor chip; and
fixing the power terminal connector to the circuit board so as to electrically connect the power terminal connector to the first electrically conductive layer.
US15/134,984 2015-04-22 2016-04-21 Circuit board embedding a power semiconductor chip Active 2036-08-04 US10062671B2 (en)
DE102015106151.1A DE102015106151A1 (en) 2015-04-22 2015-04-22 Embedded circuit board power semiconductor chip
DE102015106151 2015-04-22
DE102015106151.1 2015-04-22
US20160316567A1 true US20160316567A1 (en) 2016-10-27
US10062671B2 US10062671B2 (en) 2018-08-28
ID=57110832
US15/134,984 Active 2036-08-04 US10062671B2 (en) 2015-04-22 2016-04-21 Circuit board embedding a power semiconductor chip
US (1) US10062671B2 (en)
DE (1) DE102015106151A1 (en)
US20110031611A1 (en) * 2009-08-10 2011-02-10 Infineon Technologies Ag Embedded laminated device
US20130082387A1 (en) * 2011-09-29 2013-04-04 Infineon Technologies Ag Power semiconductor arrangement and method for producing a power semiconductor arrangement
US20130161801A1 (en) * 2011-12-23 2013-06-27 Infineon Technologies Ag Module Including a Discrete Device Mounted on a DCB Substrate
WO2014197917A1 (en) * 2013-06-11 2014-12-18 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Power module
2015-04-22 DE DE102015106151.1A patent/DE102015106151A1/en active Granted
2016-04-21 US US15/134,984 patent/US10062671B2/en active Active
US20160133558A1 (en) * 2013-06-11 2016-05-12 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Power Module
US10062671B2 (en) 2018-08-28
DE102015106151A1 (en) 2016-10-27
US20130214399A1 (en) 2013-08-22 DC/DC Converter Power Module Package Incorporating a Stacked Controller and Construction Methodology
JP4999684B2 (en) 2012-08-15 Integrated transistor module and manufacturing method thereof
US8138587B2 (en) 2012-03-20 Device including two mounting surfaces
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KESSLER, ANGELA;GRUBER, MARTIN;SCHARF, THORSTEN;REEL/FRAME:038555/0776