Source: http://www.google.com/patents/US7936771?dq=5,072,412
Timestamp: 2014-10-25 17:15:22
Document Index: 370142760

Matched Legal Cases: ['Application No. 05798761', 'Application No. 05798761', 'Application No. 200580032948', 'Application No. 200580032948', 'Application No. 200580032948', 'Application No. 200580032888', 'Application No. 200580032947', 'Application No. 200580032947']

Patent US7936771 - Method and system for routing fibre channel frames - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method and system for transmitting frames using a fiber channel switch element is provided. The switch element includes a port having a receive segment and a transmit segment, wherein the fiber channel switch element determines if a port link has been reset; determines if a flush state has been enabled...http://www.google.com/patents/US7936771?utm_source=gb-gplus-sharePatent US7936771 - Method and system for routing fibre channel framesAdvanced Patent SearchPublication numberUS7936771 B2Publication typeGrantApplication numberUS 12/189,502Publication dateMay 3, 2011Filing dateAug 11, 2008Priority dateJul 21, 2003Also published asUS7447224, US20050018701, US20090034550Publication number12189502, 189502, US 7936771 B2, US 7936771B2, US-B2-7936771, US7936771 B2, US7936771B2InventorsFrank R. Dropps, Gary M. PapenfussOriginal AssigneeQlogic, CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (99), Non-Patent Citations (82), Classifications (5), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for routing fibre channel framesUS 7936771 B2Abstract A method and system for transmitting frames using a fiber channel switch element is provided. The switch element includes a port having a receive segment and a transmit segment, wherein the fiber channel switch element determines if a port link has been reset; determines if a flush state has been enabled for the port; and removes frames from a buffer, if the flush state has been enabled for the port. For a flush state operation, frames are removed from a receive buffer of the fiber channel port as if it is a typical fiber channel frame transfer. The removed frames are sent to a processor for analysis. The method also includes, setting a control bit for activating frame removal from the transmit buffer; and diverting frames that are waiting in the transmit buffer and have not been able to move from the transmit buffer.
In the preferred embodiments of switch chassis described herein, the fabric controller is a firmware-programmed microprocessor, also referred to as the input/out processor (�IOP�). TOP 66 is shown in FIG. 1C as a part of a switch chassis utilizing one or more of ASIC 20. As seen in FIG. 1B, bi-directional connection to IOP 66 is routed through port 67, which connects internally to a control bus 60. Transmit buffer 56, receive buffer 58, control register 62 and Status register 64 connect to bus 60. Transmit buffer 56 and receive buffer 58 connect the internal connectionless switch crossbar 50 to IOP 66 so that it can source or sink frames.
Reading from and writing to RBUF 69A are controlled by RBUF read control logic (�RRD�) 319 and RBUF write control logic (�RWT�) 307, respectively. WT 307 specifies which empty RBUF 69A slot will be written into when a frame arrives through the data link via multiplexer (�Mux�) 313B, CRC generate module 313A and EF (external proprietary format) module 314. EF module 314 encodes proprietary (i.e. non-standard) format frames to standard Fibre Channel 8B codes. Mux 313B receives input from Rx Spoof module 314A, which encodes frames to a proprietary format (if enabled) RWT 307 controls RBUF 69A write addresses and provide the slot number to tag writer (�TWT�) 317.
TTAG 330 includes a collection of buffers (for example, buffers based on a first-in first out (�FIFO�) scheme) for each frame source. TTAG 330 writes a tag for a source and TARE 331 then reads the tag. For any given source, there are as many entries in TTAG 33Q as there are credits in RBUF 69A.
A loop look up table �LLUT�) 322 and an address look up table (�ALUT�) 323 is used for private loop proxy addressing and hard zoning managed by firmware.
Top priority is also given to frames that are flushed over controls that prevent frame transfers when active. These controls that prevent frame transfers are a �busy� signal that stops all receive buffer transfers, absence of credit, absence of virtual lane credit/credit and/or bandwidth limiting logic. Everything possible is done to get these frames removed from the source port receive buffers as soon as possible.
When a frame is diverted using the �Force TBUF Revector� control bit, TBUF 70A activates a holding register (not shown) called �Tx_Busy�1�. When �Tx_Busy�1� is active, TARB 331 only accepts frames from control port input buffer 62B, or frames that are being flushed with the source flush state function.
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