Source: https://patents.google.com/patent/CN102543870B/en
Timestamp: 2020-04-01 11:52:09
Document Index: 696484091

Matched Legal Cases: ['art 61', 'art 2', 'art 2', 'art 2', 'art 1', 'art 200', 'art 200']

CN102543870B - For the manufacture of the method for semiconductor subassembly with insulator-semiconductor table top - Google Patents
For the manufacture of the method for semiconductor subassembly with insulator-semiconductor table top Download PDF
CN102543870B
CN102543870B CN201110408395.5A CN201110408395A CN102543870B CN 102543870 B CN102543870 B CN 102543870B CN 201110408395 A CN201110408395 A CN 201110408395A CN 102543870 B CN102543870 B CN 102543870B
insulated trench
CN201110408395.5A
CN102543870A (en
H.格鲁贝尔
A.莫德
A.迈泽
H.罗特莱特纳
2010-12-10 Priority to US12/964,865 priority Critical patent/US9142665B2/en
2010-12-10 Priority to US12/964865 priority
2011-11-03 Priority to US13/288,271 priority patent/US9396997B2/en
2011-11-03 Priority to US13/288271 priority
2011-12-09 Application filed by 英飞凌科技股份有限公司 filed Critical 英飞凌科技股份有限公司
2012-07-04 Publication of CN102543870A publication Critical patent/CN102543870A/en
2016-01-20 Publication of CN102543870B publication Critical patent/CN102543870B/en
For the manufacture of the method for semiconductor subassembly with insulator-semiconductor table top.Method for the manufacture of semiconductor subassembly comprises: provide the semiconductor body with first surface and the second surface relative with first surface; Etching partly enters into the insulated trench of semiconductor body from first surface; The one or more sidewalls of insulated trench form the first insulating barrier; By grinding, polishing and CMP, wherein at least one processes second surface to expose the first insulating barrier; And deposition extends to the second insulating barrier of the first insulating barrier on the second surface of process.
For the manufacture of the method for semiconductor subassembly with insulator-semiconductor table top
Embodiments of the invention relate to method for the manufacture of the semiconductor subassembly with at least two semiconductor mesas insulated from each other and related semiconductor assembly.Other embodiments of the present invention relate to for the manufacture of the semiconductor subassembly with the electrical conductivity through hole extended by semiconductor body method and there is the semiconductor subassembly of through hole.
There is this semiconductor subassembly or device: its comprise in the region of the first surface of semiconductor body its device architecture at least partially and comprise the terminal for electricity contact devices structure at the second surface of semiconductor body.This assembly also comprises the electrical conductivity through hole being extended to first surface by semiconductor body from the terminal of second surface.
Electrical conductivity through hole usually and the peripheral region electrical insulation of semiconductor body.Such through hole can be manufactured by following steps: form groove, at side wall deposition electrical insulation material and the use electrical conductivity material filling residue groove of groove.
There are needs for the method being provided for manufacturing the semiconductor subassembly with the electrical conductivity through hole extended by semiconductor body, the period zones of this through hole and semiconductor body thoroughly insulate.
Moreover, for the integrated circuit (IC) of based semiconductor, usually need the insulation system between different electronic circuit.Therefore, can avoid or at least substantially reduce the Leakage Current of different electronic circuit and undesirable mutual interference.This device can use silicon-on-insulator (SOI) fabrication techniques.But SOI technology is relatively costly.Moreover the material of the buried oxide (BOX) of the SOI wafer of use is typically restricted to silicon dioxide (SiO 2) and sapphire.Therefore, there are needs in the method for the flexible and low cost being provided for manufacturing the semiconductor subassembly with circuit insulated from each other.This also allows the manufacture of the flexible of the semiconductor subassembly of the such as TEDFET with insulated gate structure and low cost, and this insulated gate structure extends along whole drift region and can bear voltage during blocking mode.
According to an embodiment of the method for the manufacture of semiconductor subassembly, the method comprises: provide the semiconductor body with first surface and the second surface relative with first surface; Form the insulated trench entering into semiconductor body from first surface; At least on the one or more sidewalls of insulated trench, form the first insulating barrier; The semi-conducting material of semiconductor body is removed to expose the base section of the first insulating barrier and to form back surface from second surface; And deposit the second insulating barrier on the back surface.Process implementing is make to be formed by the first insulating barrier and the second insulating barrier at least two semiconductor mesas insulated from each other.
According to an embodiment of the method for the manufacture of semiconductor subassembly, the method comprises: provide the semiconductor body with first surface and the second surface relative with first surface; Etching partly enters into the insulated trench of semiconductor body from first surface; The one or more sidewalls of insulated trench form the first insulating barrier; By grinding, polishing and CMP, wherein at least one processes second surface to expose the first insulating barrier; And deposition extends to the second insulating barrier of the first insulating barrier on the second surface of process.
According to an embodiment of semiconductor subassembly, semiconductor subassembly comprises the semiconductor body with first surface and the back surface relative with first surface.Form at least one insulated trench with the first insulating barrier extending to back surface from first surface in the semiconductor body.Semiconductor subassembly also comprises the second insulating barrier be deposited on the back surface of semiconductor body.Second insulating barrier comprise silica, aluminium nitride, diamond-like-carbon, Pyrex, spin-coating glass, organosilicate dielectric, organosilicon, polyimides, parylene or polybenzocyclobutene, synthetic material and cured resin wherein at least one.Form at least two semiconductor mesas in the semiconductor body.These at least two semiconductor mesas are laterally insulated by the first insulating barrier.Wherein at least one is insulated by the second insulating barrier two semiconductor mesas on the back surface completely.
According to an embodiment of the method for the manufacture of semiconductor subassembly, the method comprises: provide the semiconductor body with first surface and the second surface relative with first surface; Formed and to extend to semiconductor body from first surface and in the horizontal plane of semiconductor body, to limit the insulated trench of the via regions of semiconductor body; The one or more sidewalls of insulated trench form the first insulating barrier; The semi-conducting material of semiconductor body is removed at least to expose the part of the first insulating barrier at least to remove the part of the first insulating barrier or to leave the semiconductor layer that between the first insulating barrier and second surface, thickness is less than 1 μm at least in part from second surface; In via regions, the first contact electrode is formed in the region of first surface; And in via regions, the second contact electrode is formed in the region of second surface.
According to an embodiment of semiconductor subassembly, this assembly comprises: the semiconductor body with first surface and second surface; The first contact electrode in the region of first surface; The second contact electrode in the region of second surface; The semiconductor through hole region extended between the first and second contact electrodes; And in the horizontal direction of semiconductor body by the insulating barrier of other region disconnectings of via regions and semiconductor body.
When read below detailed description and when checking accompanying drawing, those skilled in the art will recognize that supplementary features and advantage.
Assembly in accompanying drawing is not necessarily to scale, but focuses in explanation principle of the present invention.In addition, in the accompanying drawings, similar Reference numeral indicates corresponding parts.In the accompanying drawings:
The Fig. 1 comprising Figure 1A to 1H illustrate according to for the manufacture of have semiconductor through hole semiconductor subassembly the first embodiment method during by the vertical section of semiconductor body;
Fig. 2 illustrates the horizontal profile of the semiconductor body by comprising rectangular shaped semiconductor via regions;
Fig. 3 illustrates the horizontal profile of the semiconductor body by comprising circular semiconductor via regions;
Fig. 4 illustrates the horizontal profile of the semiconductor body by comprising cast semiconductor through hole region;
Comprise Fig. 5 explanation of Fig. 5 A to 5C according to the vertical section by semiconductor body during the method step of the method for the second embodiment;
Fig. 6 illustrates after the processing step of the method according to another embodiment by the vertical section of semiconductor subassembly;
The Fig. 7 comprising Fig. 7 A to 7E illustrates except semiconductor through hole, by the vertical section of semiconductor body manufacture the method step of the method for other through hole in semiconductor through hole region during;
Fig. 8 illustrates the vertical section of the semiconductor subassembly manufactured by the amendment of the method according to Fig. 7;
Fig. 9 illustrates the vertical section of the transistor component by comprising semiconductor through hole;
Figure 10 illustrates according to the top view on a surface of the transistor component of the first embodiment;
Figure 11 illustrates according to the top view on a surface of the transistor component of the second embodiment;
Figure 12 illustrates according to the top view on a surface of the transistor component of the 3rd embodiment;
Figure 13 illustrates the top view be wherein integrated with on a surface of the semiconductor body of two transistor components, and these two transistor components include semiconductor through hole;
Figure 14 illustrates the second embodiment being wherein integrated with the semiconductor arrangement of two transistor components, and these two transistor components include semiconductor through hole;
Figure 15 illustrates in cross section C-C by the vertical section according to the assembly of Figure 14;
Figure 16 illustrates a part for the vertical section of the semiconductor body by being integrated with two transistor components;
Figure 17 illustrates the horizontal profile by the layout of Figure 16;
Figure 18 illustrates the horizontal profile of the semiconductor body being wherein integrated with another embodiment of two transistor components by basis;
Figure 19 to 27 illustrates during the method step of the method according to other embodiments by the vertical section of semiconductor body;
Figure 28 to 29 illustrates during the method step of the method according to other embodiment by the vertical section of semiconductor body;
Figure 30 illustrates that each semiconductor mesa includes corresponding electronic circuit according to an embodiment by having the vertical section of the semiconductor body of the integrated circuit of multiple semiconductor mesa.
Figure 31 illustrates that each semiconductor mesa includes corresponding electronic circuit according to another embodiment by having the vertical section of the semiconductor body of the semiconductor device of multiple semiconductor mesa.
Figure 32 illustrates that each semiconductor mesa includes corresponding electronic circuit according to another embodiment by having the vertical section of the semiconductor body of the semiconductor device of multiple semiconductor mesa.
Figure 33 illustrates that each semiconductor mesa includes corresponding electronic circuit according to an embodiment is by having the vertical section of the semiconductor body of the semiconductor device of two semiconductor mesas again.
Figure 1A to 1H illustrates the first embodiment of the method for the manufacture of the semiconductor subassembly with the electrical conductivity through hole extended by semiconductor body.These illustrate during specified method steps or afterwards by the vertical section of semiconductor body.
With reference to Figure 1A, provide semiconductor body 100.Semiconductor body 100 comprises first surface 101 and the second surface 102 relative with first surface 101.The vertical section illustrated in Figure 1A to 1H is perpendicular to the section in the vertical cross-section on the first and second surfaces 101,102.
Semiconductor body 100 can comprise conventional semiconductor material, such as, and silicon (Si), carborundum (SiC), GaAs (GaAs), gallium nitride (GaN) etc.Semiconductor body 100 is single crystal semiconductor body especially.
According to the first embodiment, semiconductor body 100 has uniform basic doping.Depend on the particular type of the semiconductor subassembly that needs realize, basic doping can be n doping or p doping.According to another embodiment, semiconductor body 100 comprises the semiconductor layer of two different doping: the first semiconductor layer 110; And first the second semiconductor layer 120 on semiconductor layer 110 top.First semiconductor layer 110 is such as semiconductor substrate, and the second semiconductor layer 120 is such as the epitaxial loayer of growth on substrate 110.Two semiconductor layers 110,120 can have different doping contents and/or doping type.According to an embodiment, ground floor 110 has the doping content higher than the second layer 120.The doping content of ground floor 110 is such as in 10 18cm -3to 10 21cm -3scope in, and the doping content of the second layer 120 is such as in 10 14cm -3to 10 17cm -3scope in.First and second layer 110, the doping type of the doping of 120 can be identical or can be complementary.
With reference to Figure 1B, form at least one insulated trench extended to from first surface 101 semiconductor body 100.In the horizontal plane of semiconductor body 100, at least one insulated trench 103 forms the ring or circle closed, makes at least one insulated trench 103 around the region 11 of semiconductor body 100.Hereinafter, semiconductor body 100 horizontal direction by insulated trench 103 around region 11 be called as via regions.In a horizontal plane, insulated trench 103 can realize with a lot of different modes, that is, have a lot of different geometries.For illustration of object, explain some examples referring to figs. 2 to 4 embodiments illustrated.
Fig. 2 illustrates the top view after forming insulated trench 103 on semiconductor body 100.In the embodiment illustrated in fig. 2, insulated trench 103 has rectangular geometry.In this case, insulated trench 103 is embodied as rectangular loop or ring in the horizontal plane of semiconductor body 100.Therefore, by insulated trench 103 around semiconductor through hole region 11 be rectangle in a horizontal plane.
In the embodiment illustrated in figure 3, insulated trench 103 has ellipse and especially circular geometry.Therefore, by insulated trench 103 around semiconductor through hole region 11 there is ellipse and especially circular geometry.
In the embodiment illustrated in figs 2 and 3, semiconductor through hole region 11 is limited by an insulated trench 103 around semiconductor through hole region 11.But the insulated trench 103 with rectangular geometry (see figure 2) or oval geometry (see figure 3) is only exemplary embodiment.As long as insulated trench 103 forms the ring closed around semiconductor through hole region 11 or circle, then insulated trench 103 can have arbitrarily other geometries.
According to another embodiment illustrated in fig. 4, semiconductor through hole region 11 by two insulated trenchs all forming closed ring around the first insulated trench 103 1with by the first groove 103 1the second insulated trench 103 arranged in the ring limited 2.First and second grooves 103 1with 103 2spaced apart each other, makes semiconductor through hole region 11 be arranged in two grooves 103 1, 103 2between.In the embodiment illustrated in the diagram, the first and second grooves 103 1, 103 2substantially there is rectangular geometry.But this is only example.These two grooves 103 1, 103 2also the geometry of any ring that other are closed being different from rectangular geometry can be had.
In the embodiment illustrated in figures 2,3, and 4, groove 103(is in a horizontal plane) formed around semiconductor regions close ring, wherein by groove around semiconductor regions formed via regions 11.There is the groove of the geometry of closed ring in the horizontal direction by via regions 11 other region disconnectings with semiconductor body 100.But groove 103 need not have the geometry of closed ring with limited hole region 11.Such as, if groove 103 near semiconductor body 100 edge placement and at the edge termination of semiconductor body 100, then do not need the geometry of the ring closed.This is shown in broken lines in fig. 2.In the figure, Reference numeral 105 indicates the edge of semiconductor body 100, and semiconductor body 100 stops herein.
Groove 103'(illustrates with dotted line) stop at edge 105 and form closed ring together with edge, make groove (together with the edge 105 of semiconductor body) limited hole region 11.Thus, the multiple semiconductor bodies usually used as the part of semiconductor wafer (not shown) are together processed, and wafer is separated to form each semiconductor body at the end of this process.Therefore, when forming groove 103 or 103' respectively, wafer is not separated yet.Now, it is separated wherein that the line (scribe line) on wafer limits wafer, and the edge therefore limiting each wafer will wherein.When processing, groove 103' and scribe line limited hole region 11.Groove 103' can also be formed as the geometry with closed ring, makes groove 103' extend to scribe line.In this case, when wafer is by cutting into each semiconductor body (tube core) along scribe line cutting, the ring closed that this groove 103' limits is open to the outside world.
In figs 2 and 3 with in the embodiment of depicted as solid lines, groove 103 limit by groove around silicon through hole 11.The ring closed limited at groove is outside, can arrange groove active block region, the active region of such as transistor.In the embodiment shown in figs. 2 and 3, by groove around the regional choice of semiconductor body 100 be make to obtain the through hole with suitable/required Ohmic resistance.According to another embodiment, active block region be arranged in by groove 103 around semiconductor regions in and through hole limited by the edge 105 of groove and semiconductor body 100.In this case, through hole 11(is as shown in the dotted line in Fig. 2 and 3) to be arranged between edge 105 and groove 103 and to form the ring closed around groove 103, wherein groove 103 forms the ring closed around active region (field of such as transistor unit).
Figure 1B representative is by the vertical section of each in the embodiment of explanation in Fig. 2,3 and 4.In fig. ib, the Reference numeral representative in bracket is used for the Reference numeral according to the embodiment of Fig. 4.Hereinafter, " at least one insulated trench " expression groove 103 as shown in Figures 2 and 3 or two grooves 103 as shown in Figure 4 1, 103 2.
At least one insulated trench 103 that the vertical direction that engraving method can be used to be manufactured on semiconductor body 100 extends.Known for manufacturing the engraving method of vertical trench in the semiconductor body, so do not need further explanation with regard to this respect." extend in the vertical direction " and represent that at least one groove 103 extends substantially in the vertical direction.But groove also can tilt relative to first surface 101, make the angle between the sidewall of groove 103 and first surface 101 can be different from 90 °.Groove width can reduce along with the degree of depth or increase.Two sidewalls also can tilt in the same direction, wherein groove width along with gash depth be such as constant.The direction that groove 103 tilts such as can change along with wafer.
At least one insulated trench 103 is fabricated to and makes it not exclusively extend to second surface 102 by semiconductor body 100.The degree of depth of insulated trench 103 is such as in the scope of 5 μm to 200 μm, is especially in the scope of 30 μm to 60 μm, than 50 μm according to appointment.The width of groove is such as in the scope of 200nm to 20 μm.
With reference to figure 1C, at least on the sidewall of at least one insulated trench 103, form the first insulating barrier 21.In the embodiment illustrated in fig. 1 c, the sidewall and bottom of at least one insulated trench 103 form the first insulating barrier 21.First insulating barrier 21 is such as oxide skin(coating).Oxide skin(coating) can pass through thermal oxidation technology and/or depositing operation manufacture.But the method is not restricted to and uses oxide as insulating barrier 21.Also insulation or the dielectric substance of any other types can be used, such as nitride, aluminium oxide (Al 2o 3) or low K dielectrics.According to an embodiment, the first insulating barrier 21 is composite beds of two or more layers comprising the insulating material be laminated to each other.
Alternatively, in semiconductor body 100, be adjacent to manufacture doped semiconductor region 12(in insulated trench 103 illustrate with dotted line).Doped semiconductor region 12 has the doping content higher than the basic doping of semiconductor body 100, or semiconductor body 100 comprise the ground floor 110 of higher-doped and the more low-doped second layer 120 time have at least higher than the doping content of the doping content of more low-doped semiconductor layer 120.Doped semiconductor region 12 is at least adjacent to manufacture with groove 103 in via regions 11, but also can manufacture along the complete side walls of insulated trench 103 and bottom.Form highly doped regions 12 such as to comprise: depositing operation, wherein dopant deposition glass or doped polycrystalline silicon are then diffusion technologys; Vapour phase doping process; Or inject and/or diffusion technology, wherein dopant atom injects via the sidewall (and optional bottom) of insulated trench 103 or is diffused into semiconductor body 100.
In the embodiment illustrated in fig. 1 c, insulating barrier 21 manufactures along the sidewall of insulated trench 103 and bottom, makes to remain with residue groove after manufacture insulating barrier 21.With reference to figure 1D, this residue trench fill is with packing material 22.Packing material 22 is such as electrical conductivity material, and such as adulterate amorphous or polycrystalline semiconductor material, all polysilicons in this way, metal, silicide or carbon.According to another embodiment, packing material 22 is insulating material, and insulated trench 21 is filled completely with insulating material.According to another embodiment shown in Fig. 6, insulating barrier 21 is fabricated to and makes it fill insulated trench 103 completely, makes not remain groove after manufacture insulating barrier 21.In other embodiments, if such as before complete filling groove 103 opening of groove 103 between depositional stage close, hole can be sealed in groove 103.
Insulation and packing material are typically also deposited on first surface 101(such as in trench-etch mask) and in fig. 1 c on unshowned second surface 102.After trench fill, these layers can be removed from the first and second surfaces 101,102.
With reference to figure 1E, remove semi-conducting material from second surface 102, the thickness of the vertical dimensions corresponding to semiconductor body 100 is reduced.Such as, the removal of the semi-conducting material of second surface 102 comprise etch process, mechanical polishing process or chemico-mechanical polishing (CMP) technique wherein at least one.In fig. ie, Reference numeral 102' indicates the second surface of semiconductor body 100 after removing technique.Hereinafter, the second surface 102' of semiconductor body 100 is also referred to as back surface 102'.Should mention, complete process first surface after and process second surface before, semiconductor body is upside-down mounting or inverted normally.But, in order to understand better, this upside-down mounting of undeclared semiconductor body 100.
With reference to the embodiment illustrated in figure 1E, removal technique can perform exposes first insulating barrier 21 at second surface 102' for making at the end of removal technique.In the illustrated embodiment, semi-conducting material is removed down to below the bottom of insulated trench 103, and make at the end of removal technique, the first insulating barrier 21 bottom insulated trench exposes at second surface and protrudes from second surface 102'.Thus, second surface is not flattened in the method.
In ensuing method step, second surface 102' forms the second insulating barrier 31, this second insulating barrier 31 covers the exposed area of the first insulating barrier 21.With reference to figure 1F and 1G, manufacture the second insulating barrier 31 and such as comprise formation and cover second surface 102'(completely and see Fig. 1 F) insulating barrier 31' and in insulating barrier 31', form contact openings, this contact openings extends to via regions 11.Contact openings is fabricated to and makes the remainder 31 of insulating barrier 31' form the second insulating barrier 31, and this second insulating barrier 31 covers this at least one insulated trench 103 together with first insulating barrier 21 of second surface 102'.Second insulating barrier 31 is such as oxide skin(coating) or nitride layer.The second layer 31 is especially included in depositing operation the material not requiring high temperature (such as lower than the temperature of 400 DEG C).Other suitable materials are such as spin-coating glass or acid imide.Before the semi-conducting material removing second surface 102, can complete or finally process the device architecture below first surface and first surface.This can comprise the deposition of the metal layer (not shown) on first surface 101.But this metal layer can not bear high temperature, such as higher than the temperature of 400 DEG C.
It is optional for forming the second insulating barrier 31.The insulating barrier 21 of channel bottom can be enough to the bottom of groove by via regions and around semiconductor regions insulate.
In order to form second insulating barrier 31 adjacent with the first insulating barrier 12, in the removal technique illustrated in fig. ie, the first insulating barrier 21 need not be exposed.According to an alternative embodiment, semi-conducting material is not removed down to the first insulating barrier 21, but semi-conducting material (thin) layer that remaining thickness is less than 1 μm below the first insulating barrier 21 in the region of second surface 102'.This illustrates with dotted line in fig. ie.In this case, form insulating barrier 31'(and see Fig. 1 F) relate to the technique semiconductor layer between second surface 102' and the first insulating barrier 21 being changed into insulating barrier.This technique is such as oxidation technology, such as anode oxidation process and/or wherein oxygen be injected into the technique in semiconductor body 100 via second surface 102'.
After the processing step illustrated in Fig. 1 E to 1G, in the horizontal direction semiconductor through hole region 11 had completely the insulated trench of the first insulating barrier 21 and the second insulating barrier 31 around.Semiconductor through hole region 21 forms electrical conductivity between the first surface of semiconductor body 100 and second surface 102' and connects, and with other region electrical insulation of semiconductor body 100.
With reference to figure 1H, in the region of first surface 101, on semiconductor through hole region 11, form the first contact electrode 41 and on semiconductor through hole region 11, form the second contact electrode 42 in the region of second surface 102'.In the region on the first and second surfaces 101,102, form the first and second contact electrodes 41,42 respectively mean that these electrodes 41,42 can be formed in respective surfaces 101,102.But, one or two in these grooves also can be formed in the trench, each wherein in these grooves from surface 101,102 one of them to extend to via regions and comprise contact through hole region in respective groove the first and second electrodes 41,42 one of them.
First contact electrode 41 is such as the highly doped polycrystalline semiconductor material of metal, silicide or such as polysilicon.Alternatively, the contact area 13 of doping is formed in the via regions before formation first contact electrode 41 below first surface 101.This contact area can also be formed before formation second contact electrode 42 below second surface 102'.But, such as in the region of higher-doped first semiconductor layer 110, when semiconductor body have height substantially adulterate time, this contact area can be omitted.
Although describe the method step for the manufacture of the semiconductor through hole 11 with the first and second contact electrodes 41,42 with a certain order, the method is not restricted to and performs these steps with any specific order.But the order of method step can change.Such as, before removing technique or even, the first contact electrode 41 on first surface 101 and optional contact area 13 can be manufactured before manufacturing insulated trench 103.
Fig. 5 A to 5C illustrates another embodiment for manufacturing semiconductor through hole 11 in semiconductor body 100.The method is equal to the method illustrated in Figure 1A to 1H substantially, and difference is at the end of removal technique or during removal technique, second surface 102' is flattened, and the first insulating barrier 21 in the bottom section of insulated trench 103 is removed.Fig. 5 A illustrates the vertical section by semiconductor body 100 after these method steps.After these method steps, the opposing sidewalls of insulated trench 103 exists the first insulating barrier 21 and exposes packing material 22 at second surface 102'.With reference to the explanation provided above, packing material 22 is optional.Like this, insulated trench 103 can be filled completely with the first insulating barrier 21.
What illustrate in Fig. 5 B and 5C is making for forming the second insulating barrier 31 and correspond respectively to for the formation of the method step of the first and second contact electrodes 41,42 on second surface 102' the method step illustrated in Fig. 1 F to 1H quoted.Second insulating barrier 31 covers insulated trench 103 at second surface 102' and leave contact openings on semiconductor through hole region 11.
The method step illustrated in Fig. 4,5A and 5B can also be described as the method for the manufacture of the semiconductor subassembly with multiple semiconductor mesa, and the plurality of semiconductor mesa is by being arranged in one or more insulated trench 103 1, 103 2on the first insulating barrier 21 laterally insulate.The method comprises: provide the semiconductor body 100 with first surface 101 and the second surface 102 relative with first surface 101; Etching partly enters into the one or more insulated trenchs 103 of semiconductor body 100 from first surface 101 1, 103 2; At insulated trench 103 1, 103 2one or more sidewalls on form the first insulating barrier 21; By grinding, polishing, CMP, chemical etching and plasma etching, wherein at least one processes second surface 102 to expose the first insulating barrier 21; And deposition extends to the second insulating barrier 31' of the first insulating barrier 21 on the second surface 102' of process.
In the exemplary embodiment illustrated in figure 5b, 3 semiconductor mesa regions are shown, they are insulated from each other with the second insulating barrier 31' be arranged on back surface 102' by the first insulating barrier 21 be arranged on the sidewall of insulated trench.Subsequently, the second insulating barrier 31' can be partially removed to form via regions in the semiconductor mesa of centre, as shown in Figure 5 C.In other embodiments, all or at least multiple semiconductor mesa region of final semiconductor subassembly keeps insulating completely on back surface 102'.In these embodiments, the remainder 31 of insulating barrier 31' forms the second insulating barrier 31, and this second insulating barrier 31 forms the insulation system of the semiconductor mesa being used for mutually insulated together with the first insulating barrier 21.Typically, the semiconductor mesa of insulation comprises the semiconductor structure of the separation of the part at least forming different electronic circuit.Therefore, the integrated circuit with low crosstalk between different electronic circuit and/or low Leakage Current can be provided.Other examples are explained below with reference to Figure 19 to 33.This semiconductor subassembly also can be manufactured by SOI technology, but cost is higher.This is not mainly because the cost of SOI wafer has 4 to 10 times of the similar wafer of buried oxide layer typically.
With reference to the explanation provided above, the first insulated trench 103 can be filled with the first insulating barrier 21 completely, and wherein the first insulating barrier 21 can also be fabricated to the lamination of different material layer and can comprise hole.Illustrate in figure 6 by having the vertical section of filling completely with the semiconductor body 100 of the insulated trench 103 of the first insulating barrier 21.Fig. 6 to illustrate before removing semi-conducting material from second surface 102 and by the vertical section of semiconductor body 100 before manufacture first and second contact electrode 41,42.
The Ohmic resistance in the semiconductor through hole region 11 between the first and second contact electrodes 41,42 especially depends on the length (this length corresponds to the vertical thickness of semiconductor body 100) of via regions 11, the area of horizontal profile in semiconductor through hole region 11 and the doping content of via regions 11.The Ohmic resistance in semiconductor through hole region 11 can reduce by providing highly doped region 12 along the sidewall of insulated trench 103.
According to another embodiment, the Ohmic resistance in semiconductor through hole region 11 can reduce with the contact trench of electrical conductivity material by additionally providing to fill in semiconductor through hole region 11.This contact trench alternatively or additionally can be provided to highly doped semiconductor regions 12.Following reference diagram 7A to 7E explains the embodiment of the method for the manufacture of the semiconductor through hole region 11 with contact trench.These figure all illustrate the vertical section by semiconductor body 100 during the particular step of method.Although these method steps are described with certain order in the drawings, this order can change.
With reference to figure 7A, except forming insulated trench 103 and filling except insulated trench 103, the method relates to formation and extends to the contact trench 104 semiconductor body from first surface 101 and use electrical conductivity material 23 to fill contact trench 104.Electrical conductivity material 23 is such as doping amorphous or polycrystalline semiconductor material, such as polysilicon, metal, silicide or carbon.According to an embodiment, the layer that contact trench 104 fills to comprise at least two different electrical conductivity layers is stacking.Alternatively, before use electrical conductivity material 23 filling groove 104, the sidewall along contact trench 104 forms diffusion barrier or the 3rd insulating barrier 24.Electrical conductivity material 23 forms the conductive through hole in semiconductor through hole region 11.Contact trench 104 can be fabricated to and it is arranged away from insulated trench 103.Illustrate with dotted line in the embodiment that the position of the contact trench 104 in semiconductor through hole region 11 illustrates in figures 2,3, and 4.
As shown in Figure 7 A, insulated trench can comprise the first insulating barrier 21 and electrical conductivity packing material 22.Alternatively, as shown in Figure 6, insulated trench 103 can be filled completely with the first insulating barrier 21.
Residue method step shown in Fig. 7 B to 7E corresponds respectively to the method step shown in Fig. 1 E to 1H.These method steps comprise partly to be removed the semiconductor body 100(at second surface 102 place and sees Fig. 7 B), form the second insulating barrier 31(adjacent with the first insulating barrier 21 and see Fig. 7 C and 7D).Contact openings in insulating barrier 31' is formed as making contact openings expose contact through hole 23 at second surface 102'.With reference to figure 7E, on first surface 101 He on second surface 102, on contact through hole 23 and semiconductor through hole 11, form the first and second contact electrodes 41,42 respectively.
Formation insulated trench 103 and contact trench 104 can comprise public same method step.According to an embodiment, these grooves 103,104 are by the etching of identical etch process.And when the packing material 22 of insulated trench 103 is electrical conductivity materials, the packing material 22 in insulated trench 103 can by identical method step manufacture with the electrical conductivity material 23 in contact trench 104.
In the method shown in Fig. 7 A to 7E, partly remove the technique of semiconductor body 100 at second surface 102 during, retain at the first insulating barrier 21 of the bottom of insulated trench 103.This method shown in corresponding Figure 1A to 1H.
According to an embodiment, contact trench 104 is fabricated to and extends to semiconductor body 100 darker than insulated trench 103 from first surface 101.When contact trench 104 is wider than insulated trench 103, the contact trench 104 that the manufacture technics identical with manufacturing insulated trench 103 is darker can be used.After contact trench 104 is filled with electrical conductivity material 23 and when removing semi-conducting material from second surface 102, before arrival insulated trench 103, the contact electrode 23 in (darker) contact trench 104 exposes.This allows to expose contact electrode 23 at second surface 102' under the condition of the insulating barrier 21 of the bottom of not removing insulated trench 103.
But, be similar to the method shown in Fig. 5 A to 5C, during removal technique, partly can remove the first insulating barrier 21 of the bottom of insulated trench 103, if make also there is packing material 22 except the first insulating barrier 22, then expose packing material 22 in the bottom of groove 103.The semiconductor subassembly manufactured according to this amendment shown in Figure 8.
Semiconductor through hole region 11 and optional contact through hole 23 can be used in being connected the device region of any type in the region of the first surface 101 being arranged in semiconductor body 100 or second contact electrode 42 of device architecture and second surface 102'.Fig. 9 illustrates the vertical section by transistor, especially vertical MOS transistor.MOS transistor is realized in the semiconductor body 100 comprising highly doped first semiconductor layer 110 and more low-doped second semiconductor layer 120.MOS transistor comprises and being realized and the drain region 54 contacted with the drain electrode 56 be arranged on second surface 102' by the first semiconductor layer 110.Drain electrode 56 forms the drain terminal D of MOS transistor.MOS transistor also comprises the drift region 53 adjacent with drain region 54.Drift region 53 is formed by those parts with the basic doping of the second layer 120 of the first semiconductor layer 120.Transistor also comprises and has source region 51, is arranged in body region 52 between source region 52 and drift region 53 and layout adjacent with body region 52 and by gate-dielectric 62 at least one transistor unit with the gate electrode 61 of body region 52 electrical insulation.
In fig .9, multiple transistor units with source region 51 and body region 52 are described.In the embodiment illustrated in fig .9, gate electrode 661 is embodied as trench gate electrode, and it is arranged gate electrode in the trench and extends to the gate electrode semiconductor body 100 from first surface 101.But, realize gate electrode 61 for trench electrode be only example.Gate electrode 61 can also be embodied as plane electrode, this plane electrode be arranged in semiconductor body 100 first surface 101 above electrode.In fig .9, the different piece of gate electrode 61 is shown.These parts of gate electrode 61 are with the electricity connection each other of unaccounted mode.Such as, gate electrode 61 has grid geometry in a horizontal plane.Or the various piece 61 shown in Fig. 9 is longitudinal electrode part in the direction perpendicular to the cross section shown in Fig. 9.These longitudinal gate electrode parts can electricity be connected each other by being arranged in perpendicular to the connection in the groove (not shown) of gate electrode part 61 extension.
Gate electrode 61 electricity is connected to the first contact electrode 41, wherein the first contact electrode 41 by the region of the semiconductor body 100 outside insulating barrier 71 and via regions 11 and alternatively with trench fill material 22 dielectric insulation.Via contact electrode 41 and semiconductor through hole 11, gate electrode 61 electricity is connected to the second contact electrode 42 be arranged on second surface 102'.Hereinafter, the first contact electrode 41 is also referred to as wiring.In the exemplary embodiment, first surface 101 is only formed a wiring.
Thus, the gate terminal G of MOS transistor is formed by the second contact electrode 42 be arranged on the second surface 102' of semiconductor body.Each source region 51 and body region 52 electricity are connected to the source electrode 55 with gate electrode 61 dielectric insulation.Source electrode 55 is arranged on the top of first surface 101 of semiconductor body.This vertical MOS transistor has the source electrode 55 above first surface 101, and has and be arranged in gate electrode 42 on the second surface 102' of semiconductor body and drain electrode 56.
Source electrode 55 electricity is connected to and is arranged in above source electrode 55 and gate contact electrode 41 and by the electrode layer 57 of another dielectric layer 72 with gate contact electrode 41 dielectric insulation, such as metal layer.Electrode layer 57 forms external source electrode, and by the surface that it is smooth, this external source electrode can be installed to lead frame (not shown).
Alternatively, the one layer metallization with substantially flat surface can be used and the different materials of such as highly doped polysilicon can be used to manufacture gate contact electrode 41.
Thus, should mention, before second surface 102' manufactures gate electrode 42 and drain electrode 56, can perform contact and inject, this is the injection for reducing the Ohmic resistance between via regions 11 and gate electrode 42 and between drain region 54 and drain electrode 56.
In the embodiment illustrated in fig .9, drain region 54 is by highly doped semiconductor layer 110(such as substrate) formed, arrange the comparatively low doped layer 120 of such as epitaxial loayer thereon, wherein in this comparatively low doped layer, realize drift region 53.According to another embodiment, semiconductor body 100 has the basic doping of the doping corresponding to drift region 53.In this case, before manufacture drain electrode 56, by injecting and/or spread and/or annealing process forming the field stop area of drain region 54 and optional IGBT.In this case, the vertical thickness of semiconductor body 100 defines the length of drift region 53.
With reference to figure 9, if passivation layer 73 can manufacture the second insulating barrier at second surface 102' or the second insulating barrier 31() upper formation.Passivation layer 73 has the contact openings above gate electrode 41 and drain electrode 56.Like this, gate electrode 42 and drain electrode can use identical method step manufacture or can be the part of a nanostructured metal layer.
MOS transistor can be embodied as n-type transistor or p-type transistor.In n-type transistor, source region 51 and drift region 53 are n doping, and body region 52 is p doping.In p-type transistor, source region 51 and drift region 53 are p doping, and body region 52 is n doping.MOS transistor can be embodied as MOSFET or IGBT.In a mosfet, drain region 54 has identical doping type with source region 51, and in IGBT, drain region 54(is also referred to as collector region) there is the doping type with the doping type complementation of source region 51.
Second contact electrode or gate electrode 42 and drain electrode 56 can be arranged on the second surface 102' of semiconductor body 100 in many different ways.Next with reference to figures 10 to the embodiment that 12 explanation three is different, wherein each illustrates the horizontal profile by the second contact electrode 42 and drain electrode 56 in the horizontal cross-section B-B illustrated in fig .9.
In the embodiment illustrated in Fig. 10, drain electrode 56 and gate electrode 52 disposed adjacent one another, wherein drain region 56 has gap regions, and gate electrode 42 is arranged in this gap regions.Drain electrode 56 and gate electrode 42 are by the second insulating barrier 31 and/or insulating barrier 21 electrical insulation each other.
In the embodiment illustrated in fig. 11, gate electrode 42 by drain electrode 56 around, gate electrode 42 and drain electrode 45 by the second insulating barrier 31 electrical insulation each other.
In the embodiment illustrated in fig. 12, gate electrode 42 is around drain electrode 56, and these two electrodes 42,56 are by the second insulating barrier 31 and/or insulating barrier 21 electrical insulation each other.According in the embodiment of Figure 12, resemble semiconductor through hole region 11, gate electrode 42 has the geometry of cast.
In other embodiments, gate electrode 42 and via regions 11 have different shapes.Drain electrode 56 can be overlapping with via regions 11.But this requires the insulating regions between gate electrode 42 and drain region and between drain electrode 56 and via regions 11.
Two MOS transistor can be realized in single semiconductor body.Figure 13 and 14 illustrate by a semiconductor body 100 realize the gate electrode of two MOS transistor and the horizontal profile of drain electrode.In the embodiment illustrated in fig. 13, the first grid electrode 42 of the first MOS transistor 1with the first drain electrode 56 1disposed adjacent one another and by the second insulating barrier 31 1electrical insulation each other.And, the second gate electrode 42 of the second MOS transistor 2with the second drain electrode 56 2disposed adjacent one another and by the second insulating barrier 31 2electrical insulation each other.In addition, can at drain electrode 56 1with 56 2between or around one or two MOS transistor provide one or more insulated trench 103 with insulate transverse to each other drain electrode and source potential.Source region can be connected to the source electrode of common source electrode or electrical insulation.Thus public source or public drain electrode device can be realized.
In the embodiment illustrated in fig. 14, the first drain electrode 56 1by first grid electrode 42 1around and the second drain electrode 56 2by second gate electrode 42 2around, the first and second gate electrodes 42 1, 42 2semiconductor body horizontal direction away from each other.
Figure 15 illustrates the vertical section by the semiconductor body 100 of Figure 14 in vertical cross-section C-C.In this vertical section, corresponding first contact electrode 42 is shown 1, 42 2the first and second gate electrodes 42 1, 42 2with semiconductor through hole region 11 1, 11 2.Reference numeral 21 1with 21 2indicate corresponding first insulating barrier.In the embodiment illustrated in fig .15, insulated trench is filled completely with the first insulating barrier 21 1, 21 2.But this is only example.These insulated trenchs can also be embodied as fills with the first insulating barrier and packing material, as shown in figure ip.
First and second semiconductor through hole 11 illustrated in fig. 15 1, 11 2respectively by two insulated trenchs 103 11, 103 12with 103 21, 103 22manufacture (restriction).In the horizontal direction, the first and second through holes 11 1, 11 2by two the first insulating barriers 21 1, 21 2be arranged in two the first insulating barriers 21 1, 21 2between semiconductor regions 13 separated from one another.
Figure 16 illustrates another embodiment, wherein two semiconductor through hole regions 11 1, 11 2by means of only having the first insulating barrier 21 12insulated trench be separated.In this embodiment, semiconductor through hole 11 1, 11 2between insulated trench fill completely with insulating barrier 21 12.But this is only example, this insulated trench can also be filled with the first insulating barrier 21 12and additional filler materials, as shown in figure ip.Figure 17 illustrates in the D-D of horizontal cross-section by the horizontal profile according to the layout of Figure 16.
Figure 18 illustrates another embodiment with the transistor layout of two MOS transistor integrated in semiconductor body 100.Figure 18 illustrates the horizontal profile by gate electrode and drain electrode in horizontal profile.In this embodiment, in semiconductor through hole region 11 1with 11 2between arrange semiconductor regions 13, and in semiconductor through hole region 11 1, 11 2with drain electrode or drain region 54 1, 54 2between arrange additional semiconductor regions 14 1, 14 2, additional semiconductor regions 14 1, 14 2by with insulated trench 103 1, 103 2the supplementary insulation groove of consistent formation and drain region 54 1, 54 2insulation.These supplementary insulation trench fill are with supplemental dielectric layer 24 1, 24 2.Alternatively, the same with the insulated trench 103 illustrated in Fig. 1 D, these supplementary insulation trench fill are with supplemental dielectric layer 24 1, 24 2and packing material.In this embodiment, additional semiconductor regions 14 1, 14 2by drain region and via regions 11 1, 11 2be separated.
According to an embodiment, semiconductor regions 13 and semiconductor regions 14 are connected to the terminal for limiting electromotive force (such as or source potential), and wherein source potential is the electromotive force of source electrode 55.Thus, the capacitive couplings between the grid of two transistors or between the grid of a transistor and drain electrode obviously reduces.
Referring to figures 19 through 27, other embodiments of the method for the semiconductor subassembly 1000 for the manufacture of the semiconductor mesa with at least lateral isolation are described.These illustrate during specified method steps or afterwards by the vertical section of semiconductor body 100.
With reference to Figure 19, provide semiconductor body 100.Semiconductor body 100 comprises first surface 101 and the second surface 102 relative with first surface.
According to an embodiment, semiconductor body 100 comprises the semiconductor layers of two different doping: the second semiconductor layer 120 on the first semiconductor layer 110 and the first semiconductor layer 110 top.Respectively, the first semiconductor layer 110 is such as semiconductor substrate, and the second semiconductor layer 120 such as by substrate 110 growth and the illustrative one or more epitaxial loayers 2 overlie one another formed.As above with reference to figure 1A explain, two semiconductor layers 110,120 can have different doping contents and/or doping type.First and second layer 110 can be identical or can be complementary with the doping type of the doping of 120, makes the pn knot 14 forming basic horizontal between ground floor 110 and the second layer 120.Alternatively, semiconductor body 100 can have uniform basic doping.In the exemplary embodiment, the first semiconductor layer 110 to the second semiconductor layer 120 is more highly doped.
With reference to Figure 20, form at least one insulated trench 103 extended to from first surface 101 semiconductor body 100 1, 103 2.Typically, insulated trench 103 1, 103 2such as use and rich execute (Bosch) technique and etch in semiconductor body 100.
In a horizontal plane, this at least one insulated trench 103 1, 103 2can realize with a lot of different modes, that is, there is a lot of different geometries.As above referring to figs. 2 to the embodiment shown in 4 explained, shown insulated trench 103 1, 103 2it can be basic cast.Therefore, two insulated trenchs 103 separated from one another in vertical section 1, 103 2a connected insulated trench 103 can be corresponded to 1, 103 2part.
Vertical section shown in attention typically only corresponds to the pass a part for semiconductor body 100.Semiconductor subassembly 1000 can be included in semiconductor body 100 multiple insulated trenchs 103 of the array limiting semiconductor mesa region 100a, 100b and 100c in a horizontal plane 1, 103 2.Array can be at least regular in horizontal zone.In other embodiments, depend on the semiconductor structure needing to be formed wherein, semiconductor mesa region 100a, 100b, 100c have different shapes and/or size in a horizontal plane.
As shown in figure 20, insulated trench 103 1, 103 2typically extend and partly to be extended in substrate 110 by epitaxial loayer 120 completely.Therefore, at least in shown vertical section, epitaxial loayer 120 is subdivided into different part 2a, 2b and 2c.When shown insulated trench 103 1, 103 2corresponding to single insulated trench 103 1, 103 2part time, part 2a, the 2c of epitaxial loayer 120 are also typically connected.
In the exemplary embodiment, each semiconductor mesa region 100a, 100b, 100c comprises a part of 14a, 14b, 14c of pn knot 14.Pn ties the part that 14a, 14b, 14c such as can form respective diode structure or transistor arrangement in final semiconductor subassembly 1000.
Especially, the insulated trench 103 of high-aspect-ratio can be form differently 1, 103 2.In a first step, the etching mask of such as photoresist, silica or silicon nitride hard mask can be used to be etched in the horizontal direction of shown vertical section substantially at shown insulated trench 103 1, 103 2exterior side wall between the wide groove that extends.After this, oxide skin(coating) can be formed on the sidewall of wide groove.This completes to remove while the part leaving hard mask on first surface 101 at the base wall of wide groove and the thermal oxide in first surface 101 formation typically via thermal oxidation and anisotropic etching.Oxide skin(coating) on the sidewall of wide groove and the width of thermal oxide mate shown insulated trench 103 substantially 1, 103 2required width or the half of required width.After this, selective epitaxial is used to use semi-conducting material to fill wide groove.Typically such as remove by CMP any semi-conducting material protruded from first surface 101.Can remove etching mask and/or oxide skin(coating) now.This process sequence also causes structure as shown in figure 20.
As above with reference to figure 1E and 5A explain, semiconductor body 100 is at least thinned to insulated trench 103 at second surface 102 after a while 1, 103 2to form semiconductor mesa region 100a, 100b, 100c of being separated.Therefore, insulated trench 103 1, 103 2typically etch into be greater than semiconductor body 100 final vertical thickness about 5% to the vertical depth d of about 30%, more typically about 15% to about 25% 2.The final vertical thickness of semiconductor body 100 can be less than 100 μm or be even less than 50 μm.During processing, this vertically extending wafer is typically supported.Therefore, before thinning, the extends perpendicular d of semiconductor body 100 1typically such as be greater than about 250 μm.Before thinning, the vertical extension d of semiconductor body 100 1typically such as be about 700 μm.
After this, at least at insulated trench 103 1, 103 2a sidewall on, typically at insulated trench 103 1, 103 2all sidewalls on form the first insulating barrier 21.The semiconductor subassembly 1000 of gained is described in Figure 21.
In the exemplary embodiment, insulated trench 103 1fill completely with the first insulating barrier 21, and the first insulating barrier 21 only covers insulated trench 103 2sidewall.But this is only an example.Typically, in public affairs are with technique, form the insulated trench 103 of semiconductor subassembly 1000 1, 103 2to reduce process complexity.Therefore, the insulated trench 103 of semiconductor subassembly 1000 1, 103 2identical structure can be had.
Insulated trench 103 2interior section, namely remain trench fill with packing material 22, as above such as with reference to figure 1C explain, this packing material can be insulating material or electrical conductivity material, such as amorphous or polycrystalline semiconductor material, the metal of such as polysilicon, such as copper or tungsten, silicide or carbon.The material being different from the material of the first insulating barrier 21 is used to fill insulated trench 103 2interior section can reduce mechanical stress.Thus, the risk destroying semiconductor body 100 in further processing can be reduced.
First insulating barrier 21 can be formed by thermal oxidation and/or by deposition and planarization technology subsequently.Packing material 22 is formed typically via deposition and planarization technology subsequently.This allows insulated trench 103 2substantially fill without chamber.Therefore, the risk destroying semiconductor body 100 in further processing can be reduced further.
As shown in figure 22, insulated trench 103 1, 103 2can be tapered.Therefore, compared with the respective upper closer to first surface 101, insulated trench 103 1, 103 2horizontal-extending can at insulated trench 103 1, 103 2bottom in less.This can be realized by rich construction skill.
Depend on the function of semiconductor subassembly 1000, multiple semiconductor regions of such as source electrode or emitter region or semiconductor region can additionally be formed by first surface 101 in the part 2a, 2b and 2c of epitaxial loayer 120.In each semiconductor mesa region 100a, 100b and 100c or on, the active and/or passive electrical component of such as resistor, capacitor, diode and transistor or even complete circuit system can be formed.Such as, MOSFET structure can be formed in semiconductor mesa 100a, 100b and 100c wherein at least one.Except additional semiconductor region, insulated gate electrodes structure can be formed on first surface 101 or in the groove extending to corresponding semiconductor table top 100a, 100b, 100c from first surface 101.For clarity sake, these structures do not illustrate in fig. 22.
After this, on first surface 101, formation has the interlayer dielectric 8 that the conduction contacted with at least some semiconductor region leads directly to such as phosphosilicate glass (PSG) layer contacting 10a, 10b, 10c.The semiconductor subassembly 1000 of gained is described in Figure 23.
Moreover, semiconductor mesa 100a, 100b, 100c wiring wherein between at least two (not shown in fig 23) can be formed on first surface 101.
After this, at least one metallization or terminal 55 can be formed to contact the electronic building brick that formed in semiconductor mesa 100a, 100b and 100c respectively and circuit on first surface 101.The semiconductor subassembly 1000 of gained is described in Figure 24.
For clarity sake, a metallization 55 of only the illustrative examples source metallization that is used for transistor arrangement as formed and/or the emitter metal for IGBT structure and/or diode structure in fig. 24.Depend on the function of final semiconductor subassembly 1000, multiple metallization can be arranged on first surface 101.Such as, drain metallization and gate metalized can additionally be arranged on first surface 101.In other embodiments, drain metallization and/or gate metalized are positioned opposite with source metallization 55 after a while.As above referring to figs. 1 to 18 explain, in these embodiments, additionally can provide the via regions by semiconductor body, for contact near first surface 101 formed gate electrode to the gate metalized that formed relative to first surface 101.In other embodiments, can provide by the additional vias region of semiconductor body to connect other electrodes to the additional metal that will be formed on back surface 102'.Now, the process of the semiconductor subassembly 1000 from first surface 101 is typically completed.
For the process of the thinning and further back side, after this semiconductor body 100 is typically arranged on carrier system 60, and wherein first surface 101 is such as glued to glass substrate or chip glass 60.If the final thickness of semiconductor body 100 is greater than about 200 μm, then semiconductor body 100 can also be arranged on paillon foil or be further processed under the condition not having any carrier system.
After this, the semi-conducting material of semiconductor body 100 is removed from second surface 102 to expose the first insulating barrier 21 and insulated trench 103 respectively 1, 103 2base section and form back surface 102'.Therefore, formed respectively to be at least located in vertical section, few separated from one another and by insulated trench 103 1, 103 2with semiconductor mesa 100a, 100b, 100c that the first insulating barrier 21 laterally insulate.The semiconductor subassembly 1000 of gained is described in Figure 25.In the exemplary embodiment, wherein each comprises re-spective engagement part 1a, 1b, 1c of a part of 2a, 2b and 2c of epitaxial loayer 120 and substrate 110 to semiconductor mesa 100a, 100b, 100c respectively.
By removing the semi-conducting material of semiconductor body, semiconductor body 100 is thinned to the final vertical thickness d between first surface 101 and back surface 102' 3.Insulated trench 103 1, 103 2nethermost part can remove during this technique.Such as, final vertical thickness d 3can than insulated trench 103 1, 103 2vertical etching degree of depth d 2little by about 5% to 30%, be more typically littlely about 15% to about 25%.
According to an embodiment, by removing the semi-conducting material of semiconductor body 100, semiconductor body 100 is thinned to the vertical thickness d between first surface 101 and back surface 102' 3, it is less than about 50 μm, such as about 40 μm.When semiconductor body 100 is attached to the sufficiently stable carrier system 60 of such as chip glass, the semiconductor subassembly 1000 with very thin semiconductor body 100 can be manufactured.This cherishes a special interest for low pressure applications.
The semi-conducting material removing semiconductor body 100 realizes typically via the mechanical reduction of such as grinding or polishing, CMP etc. and the combination of chemistry and/or plasma etching with the enough low surface roughness realizing back surface 102'.Such as, grinding technics is for removing the major part of semi-conducting material.After this, etching may be used for the semi-conducting material such as several micron removing semiconductor body 100 further, until arrive the required final vertical thickness d of semiconductor body 100 3.Semi-conducting material can be etched selective to the first insulating barrier 21 and/or packing material 22.In the present embodiment, the first insulating barrier 21 and/or packing material 22 can protrude from back surface 102' a little.
According to an embodiment, the semi-conducting material removing semiconductor body 100 is embodied as and makes back surface 102' be no marking substantially.Such as, the surface roughness of back surface 102' typically lower than 50nm, more typically lower than 10nm, and even more typically lower than 1nm.Therefore, the deposition after a while on back surface 102' is promoted.
According to another embodiment, the semi-conducting material removing semiconductor body 100 is embodied as and the first insulating barrier 21 and/or packing material 22 is not exposed.In the present embodiment, after the semi-conducting material removing semiconductor body 100, the thin layer of semi-conducting material covers the first insulating barrier 21 and/or packing material 22.Thin layer can in step after a while complete oxidation.
With reference to Figure 26, the second insulating barrier 31' is deposited on back surface 102', makes the second insulating barrier 31' extend to the first insulating barrier 21 respectively and adjoins with the first insulating barrier 21.Therefore, formed by the first insulating barrier 21 and the second insulating barrier 31' semiconductor mesa 100a, 100b, 100c insulated from each other.
Typically, the second insulating barrier 31' is deposited on back surface 102' without mask.Thus, semiconductor mesa 100a, 100b, 100c is insulated completely by the second insulating barrier 31' on back surface 102'.In the exemplary embodiment, at least middle semiconductor mesa 100b is by insulated trench 103 1, 103 2sidewall on the first insulating barrier 21 and the second insulating barrier 31' formed insulation system insulate completely on sidewall and back surface 102'.This is also applied to this embodiment: after the semi-conducting material removing semiconductor body 100, the first insulating barrier 21 and/or packing material 22 protrude back surface 102' a little.In these embodiments, the second insulating barrier 31' is also formed in the first insulating barrier 21 and directly contacts with packing material 22 with the first insulating barrier 21 with on packing material 22.After the semi-conducting material removing semiconductor body 100, the thin layer of semi-conducting material covers in the embodiment of the first insulating barrier 21 and optional packing material 22, second insulating barrier 31' is formed typically via the anodic oxidation of semi-conducting material, makes adjacent first insulating barrier 21 of the second insulating barrier 31' and optional packing material 22.
The same with the second insulating barrier 31, the second insulating barrier 31' can cover the back surface 102' in the final semiconductor subassembly manufactured completely.Alternatively, the second insulating barrier 31' of deposition can partly cave in (recess) after a while, makes the remainder 31 of insulating barrier 31' form the second insulating barrier 31 in the final semiconductor subassembly manufactured.In both cases, semiconductor mesa 100a, 100b, 100c wherein at least one (such as in the middle of semiconductor mesa 100b) covered completely by the second insulating barrier 31 adjoining the first insulating barrier 21 at back surface 102'.Therefore, the semiconductor structure formed in semiconductor mesa 100b and adjacent semiconductor table top 100a, 100c insulate.This at least reduces Leakage Current between semiconductor mesa 100a, 100b and 100c and undesirable crosstalk.Therefore the technique explained in conjunction with Figure 19 to 26 may be used for manufacturing integrated circuit, wherein in insulator-semiconductor table top 100a, 100b and 100c or insulator-semiconductor trap 100a, 100b, 100c, realizes difference in functionality.
After this, the stabilized zone 56' of such as metal level can be deposited on the second insulating barrier 31.The semiconductor subassembly 1000 of gained is described in Figure 27.
In the exemplary embodiment, the semiconductor structure formed in semiconductor mesa 100b is by insulated trench 103 1, 103 2sidewall on the first insulating barrier 21 and the second insulating barrier 31 formed insulation system and adjacent semiconductor table top 100a, 100c insulate.Therefore, the Leakage Current between semiconductor mesa 100a, 100b and 100c and undesirable crosstalk are at least reduced.
Can remove semiconductor subassembly 1000 from carrier system 60 now.Typically, public wafer forms multiple semiconductor subassembly 1000 concurrently, this public wafer can be cut into each semiconductor body (chip) before or after removing public wafer from carrier system 60.
Also SOI technology manufacture similar semiconductor subassembly as shown in figures 26 and 27 can be used.Such as, dark vertical trench may be etched into the buried oxide layer of SOI wafer and fills with dielectric substance.Therefore, isolation wells can also be formed.But due to the price that SOI wafer compared with normal wafer is higher, this manufacture method is more expensive.
Moreover, be not only the material that the silica that uses in SOI technology and sapphire can be used as the second insulating barrier 31 in the method explained herein.Depend on the semi-conducting material of application and semiconductor body, the material of the second insulating barrier 31 can be selected according to machinery and/or hot criterion.Such as, the organosilicate dielectric being known as C doping oxide (CDO) or silicone glass (OSG) of the such as dielectric substance of the high heat conductance of aluminium nitride (AlN), diamond-like-carbon etc. or such as SiCOH etc. can be used as the material of the second insulating barrier 31 to remove superfluous heat from semiconductor subassembly 1000.Moreover, the thermal coefficient of expansion of the material of semi-conducting material and the second insulating barrier 31 can be adjusted better.Therefore, in the operation of semiconductor subassembly 1000 and/or during its back side 102' is welded to lead frame, thermal stress reduces.Such as, aluminium nitride can be used as the material of the second insulating barrier 31 in silicon semiconductor body 100 to realize high heat transfer and low thermal stress in the temperature of change.
As above with reference to figure 1F to 1G explain, typically in relatively low temperature, such as lower than 600 DEG C or even perform deposition second insulating barrier 31 to protect the structure formed near first surface 101 lower than the temperature of 400 DEG C.Other the suitable materials forming the second insulating barrier 31 for low temperature are Pyrex, spin-coating glass, organosilicon (silicone), polyimides, parylene or polybenzocyclobutene, cured resin (such as the cured epoxy resin of such as SU8) or other synthetic materials.Certainly, the other standards dielectric substance of the semiconductor technology of such as silicon nitride also can deposit as the second insulating barrier 31.Moreover the second insulating barrier 31 can be formed by stream electricity (galvanic) oxidation.
According to an embodiment, the semiconductor subassembly 1000 of manufacture comprises the semiconductor body 100 with first surface 101 and the back surface 102' relative with first surface 101 and at least one insulated trench 103 formed in semiconductor body 100 1, 103 2.First insulating barrier 21 is at this at least one insulated trench 103 1, 103 2at least one sidewall on extend to back surface 102' from first surface 101.Second insulating barrier 31 to be deposited on back surface 102' and comprise aluminium nitride, diamond-like-carbon, Pyrex, spin-coating glass, organosilicate dielectric, organosilicon, polyimides, parylene or polybenzocyclobutene and cured resin or other synthetic materials wherein at least one.Second insulating barrier 31 can also be such as by oxide that anodic oxidation is formed.At least two semiconductor mesas 100a, 100b, 100c laterally being insulated by the first insulating barrier 21 are formed in semiconductor body 100.Wherein at least one is insulated on back surface 102' completely by the second insulating barrier 31 for two semiconductor mesas 100a, 100b, 100c.Therefore, the semiconductor subassembly 1000 of low crosstalk and the low Leakage Current had between semiconductor mesa 100a, 100b, 100c is provided, IC typically.
Typically, at least one insulating barrier groove 103 1, 103 2substantially be imperforate.Such as, the first insulating barrier 21 only covers at least one insulated trench 103 1, 103 2sidewall and residue trench fill with different dielectric substances or electric conducting material.
Semiconductor subassembly 1000 is typically formed to be had by being arranged in corresponding insulated trench 103 1, 103 2in and corresponding insulated trench 103 1, 103 2the second insulating barrier 31 of sidewall and the integrated circuit of the first insulating barrier 21 multiple semiconductor mesa 100a, 100b, 100c insulated from each other.Other examples are explained below with reference to Figure 30 to 33.
With reference to Figure 28 and 29, explain other embodiments for the manufacture of semiconductor subassembly.After back surface 102' deposits the second insulating barrier 31, as explained with reference to figure 26 above, the second insulating barrier 31 can partly cave in expose on back surface 102' semiconductor mesa 100a, 100b and 100c wherein at least one.The gained semiconductor subassembly 1002 with the exemplary semiconductor mesa 100b exposed is described in Figure 28.Before or after the second insulating barrier 32 is formed, the contact or emitter injection that use such as P, As, Sb, B can be applied.
After this, 102' can be formed the metallization 56 with the semiconductor mesa 100b ohmic contact exposed overleaf.Therefore, rear-face contact 56 is formed.The semiconductor subassembly 1002 of gained is described in Figure 29.
Rear-face contact 56 such as can form the drain electrode for MOSFET structure or the collector electrode for IGBT structure.Metallization 56 can be formed by deposition and can cover back surface 102' completely.In other embodiments, metallization 56 is structured, and makes the contact that the upper formation of 102' is overleaf different.Such as, as above with reference to figure 9 explain, overleaf 102' can form gate electrode and drain electrode.When insulated trench 103 2when filling with electric conducting material 22, this filling can also 102' depression and contacting as straight-through between the gate metalized be arranged on the 102' of the back side and the one or more gate electrode of layout adjacent with first surface 101 overleaf.
Also SOI technology manufacture similar semiconductor subassembly as shown in Figure 29 can be used.Such as, dark vertical trench may be etched into the local buried oxide layer of SOI wafer and fills with dielectric substance.But due to the relatively high price of SOI wafer, this manufacture method is more expensive.
With reference to Figure 30, explain second half conductor assembly 2000 that the method explained can be used to manufacture herein.Semiconductor subassembly 2000 is similar to semiconductor subassembly 1002, and also comprises two insulated trenchs 103 1, 103 2arrange and the second insulating barrier 31 of portion concave with on back surface 102'.Insulated trench 103 1, 103 2formed insulation system insulated from each other to semiconductor mesa 100a, 100b and 100c with the second insulating barrier 31.But, by the vertical section refinement more of the semiconductor body 100 of semiconductor subassembly 2000.
Due to insulation system, in the appropriate section 200a of semiconductor subassembly 2000,200b, 200c and semiconductor mesa 100a, 100b and 100c, form three different circuit of electricity decoupling (decouple) respectively.In the exemplary embodiment, only semiconductor mesa 100c be formed in metallized back face metalization 56 ohmic contact of the power n-MOSFET formed in part 200c.Back face metalization 56 can be made up of copper (Cu), and it contacts with the drain region 54 that the bottom 1c by semiconductor mesa 100c is formed with barrier layer 54 via optional contact, and layer 54 is such as made up of aluminium, titanium or silver.Arrange in vertical trench from first surface 101 and extend to multiple gate electrodes 61 semiconductor mesa 100c and field plate 63.Gate electrode 61 and field plate 63 are insulated with N-shaped drift region 2c, p-type body region 3c and n+ type source region 51 by grid and field dielectric 62.On first surface 101, interlayer dielectric 8 be furnished with connect source electrode and body region 51, source terminal 55c that 3c to the source metallization 55c on interlayer dielectric 8 is formed or the straight-through of source electrode 55c contact 12c.Source metallization 55c can also be made of copper and can cover the protective layer 11c with such as NiP.For clarity sake, the gate metalized of MOSFET is not shown in fig. 30.
Typically, semiconductor subassembly 2000 forms the IC of other circuit comprised in part 200a and 200b.These circuit can be connected to respective metal 55a(had optional protective layer 11a by straight-through contact 10a, 10b) and 55b(there is optional protective layer 11b) power circuit or logical circuit or measuring circuit.Exemplary semiconductor district 4a and 4b can be N-shaped and exemplary semiconductor district 3a and 3b can be p-type.But doping relation can be inverted.Moreover the detailed construction of semiconductor mesa 100a, 100b typically depends on the required function of IC.In order to promote the front face of IC, metallization 55a, 55b and 55c are separated from one another and be separated with other gate metalized (not shown in fig. 30) typically via the insulating barrier 17 of such as IMID layer.
With reference to Figure 31, explain second half conductor assembly 3000 that the method explained can be used to manufacture herein.Semiconductor subassembly 3000 is similar to semiconductor subassembly 1002, but comprises three insulated trenchs 103 at shown vertical section 1, 103 2, 103 3.Second insulating barrier 31 to be arranged on back surface 102' and portion concave.Insulated trench 103 1, 103 2, 103 3formed insulation system insulated from each other to semiconductor mesa 100a, 100b and 100c with the second insulating barrier 31.
For clarity sake, the active region of the semiconductor subassembly 3000 of right-hand component is only described in Figure 31.In the exemplary embodiment, semiconductor device 3000 can be operating as TEDFET(groove extension drain field effect transistor).Therefore, semiconductor body 100 comprises the vertical MOSFET structure in semiconductor mesa 100a.For clarity sake, in Figure 31, only illustrate the rightmost part of vertical MOSFET structure.The gate electrode 61a insulated by gate dielectric 62a and adjacent semiconducting regions 2a, 3a is extended from first surface 101 by p-type body region 3a and is partly extended to form the n-type drift region 2a that pn ties 14a together with body region 3a.N+ type source region 51 and p+ type body contact area (not shown in Figure 31) to be embedded in body region 3a and with the source metallization ohmic contact represented by symbol S.Drift region 2a is via drain contact areas 1a and drain metallization 56 ohmic contact.Drain contact areas 1a typically after thinning semiconductor body 100 such as by inject and follow-up in drive technique or annealing process is formed by back surface 102'.In another embodiment, as shown in the chain-dotted line in Figure 31, optional n+ type semiconductor regions 1b, 1c are also arranged in semiconductor mesa 100b and semiconductor mesa 100c.As with reference to Figure 19 explain, such as when the semiconductor body 100 initially provided comprises n+ type semiconductor substrate and N-shaped epitaxial loayer disposed thereon, the manufacture of this semiconductor subassembly even can be simpler, because do not need the additional injection technology at back surface 102'.
In addition, in semiconductor mesa 100b, the MOSFET structure formed in adjacent semiconductor table top 100a forms drift channel control structure.Can be the drift control 2b layout adjacent with drift region 2a of n-type or p-type.Drift control 2b is by being arranged in insulated trench 103 1and extend to the first insulating barrier 21 and the drift region 2a dielectric insulation of the second insulating barrier 31.Therefore, drift control 2b also insulate with drain metallization 56.The function of drift control 2b controls in drift region 2a along insulated trench 103 when MOSFET structure is in its conducting shape state 1the conduction of the first insulating barrier 21.Drift control 2b is therefore for reducing the conducting resistance of bulk crystal pipe assembly.
Be unlike in usual MOSFET, no matter how, the drift region 2a of semiconductor subassembly 3000 can be n doping or p doping to the type of mos transistor structure.Such as, if in N-shaped MOSFET structure, drift region 2a is n doping, then accumulation channel is along insulated trench 103 1the first insulating barrier 21 formed and controlled by drift control 2b.In the present embodiment, insulated trench 103 1the first insulating barrier 21 be also called accumulation layer and accumulated oxygen compound.If drift region 2a be in N-shaped MOSFET structure p doping, if then assembly is in conducting state, inversion channel in drift region 2a along insulated trench 103 1the first insulating barrier 21 formed.As conventional MOSFET, if voltage is applied to source region 51 and between the drain region 54 formed by the bottom 1a of semiconductor mesa 100a and between source electrode and drain metallization S, 56, if and suitable electromotive force puts on the conduction in its body region 3a affecting between source region 51 and drift region 2a of gate electrode 61a(), this assembly is in its conducting state.In N-shaped MOSFET structure, be applied to the voltage being in its conducting state with changeover module between drain region 54 and source region 51 is positive voltage, and compared with source potential, grid potential is positive potential.
If semiconductor subassembly 3000 is in its conducting state, need in drift control 2b electric charge carrier with in drift region 2a along insulated trench 103 1first insulating barrier 21 formed accumulation or inversion channel.In the semiconductor subassembly 3000 with N-shaped MOSFET structure, in drift control 2b, need hole for this conduction of formation.These electric charge carriers in drift control 2b are only needed when assembly is in its conducting state.If assembly is in its blocking mode, these electric charge carriers are removed from drift control 2b---be equivalent to drift region 2a, space charge region or depletion region are formed in drift control 2b.Thus, should mention, it can be maybe complementary conductivity type that drift control 2b can have identical conduction type with drift region 2a.
If assembly is in its blocking mode or cut-off, be stored in integrated capacitor arrangement from the electric charge carrier of drift control 2b movement, until assembly conducting next time.This integrated capacitor arrangement is formed in the join domain 3b of p doping at adjacent drift control 2b and for N-shaped assembly.And integrated capacitor arrangement partly can extend to drift control 2b.Join domain 3b and drift control 2b is used as the carrier layer of the electrode 61b of the insulation of integrated capacitor arrangement.Electrode 61b insulated by dielectric layer 62b and hereinafter also referred to as insulation electrode for capacitors.In order to provide electric charge carrier to drift controlled area 2b, if assembly first time conducting, if that is, integrated capacitor arrangement is not also charged, then drift control 2b can be coupled to gate terminal and gate metalized G respectively via join domain 3b.In this case, the gate driver circuit (not shown in Figure 31) being coupled to gate terminal G from the operation at semiconductor subassembly 400 provides electric charge carrier.By insulated trench 103 2the first insulating barrier 21 and the second insulating barrier 31 insulation semiconductor mesa 100c between p-type semiconductor district 3c and n-type semiconductor district 4c, form diode 65.Diode 65 to be coupling between gate terminal G and join domain 3b and to discharge to drift control 2b in the direction of gate terminal G for preventing.Due to insulated trench 103 1, 103 2the first insulating barrier 21 and the second insulating barrier 31 formed insulation system insulator-semiconductor table top 100b, prevent drift control 2b to the electric discharge of adjacent semiconducting regions 1a, 2a and 2c.In the exemplary embodiment, formed by two of the wiring electricity decoupling on first surface 101 different circuit, i.e. TEDTFET and diodes 65 in appropriate section 300a, the 300c of semiconductor subassembly 3000 forming integrated circuit.In other embodiments, gate driver circuit and other circuit also can be integrated, typically formed in the semiconductor mesa of other insulation.Example is explained with reference to Figure 32.
The semiconductor subassembly 3002 illustrated in the vertical section of Figure 32 is similar to semiconductor subassembly 3000 and also uses the method explained to be formed herein.But semiconductor subassembly 3000 also comprises at insulated trench 103 1the circuit of accumulated oxygen compound 21 charging of middle formation.In the exemplary embodiment, at least insulated trench 103 is being passed through 3, 103 4the first insulating barrier 21 and the circuit formed in the insulator-semiconductor table top 100d insulated by the second adjacent insulating barrier 31 and other semiconductor mesas 100a, 100b, 100c for charging to drift control 2b.Circuit for charging to accumulated oxygen compound comprises the electrode 61d insulated by dielectric area 62d.Electrode 61d and p+ type semiconductor region 5d is connected with the drain metallization that Reference numeral D indicates with adjacent n+ type semiconductor region 55d.Diode 67 is formed between the p-type semiconductor region 3d and n-type semiconductor region 2d of adjacent semiconductor district 5d and 55d.As Reference numeral DCR indicates, the n+ type semiconductor region 6d of adjacent n-type semiconductor region 2d is connected to the drift control 2b that the circuit that accumulated oxygen compound is charged charges with by via unshowned wiring.
Insulator-semiconductor table top 100c is included in the Z diode 66 connected between charging gate terminal CHG and source terminal S.Notice that the illustrative circuitry shown in Figure 32 typically comprises other circuit and assembly of arranging in other insulator-semiconductor table top respectively.Such as, another diode 65 as illustrated in Figure 31 is typically also integrated and be connected between gate terminal G and charging gate terminal CHG.Moreover, temperature measuring circuit and/or current measurement circuit can be additionally formed in corresponding insulator-semiconductor table top.Therefore, the complicated IC with low crosstalk and/or low Leakage Current can be provided.
With reference to Figure 33 that the vertical section by semiconductor body 100 is shown, explain other semiconductor subassembly 3004.Semiconductor subassembly 3002 is similar to semiconductor subassembly 3000,3002 and the method explained also can be used herein to be formed.For clarity sake, the rightmost part of semiconductor subassembly 3004 is only shown in fig. 33.Because drift control 2b and drain region (not shown in fig. 33) electrical insulation and be in back surface 102', there is the risk that electric charge carrier is accumulated in drift control 2b.When n adulterates drift control 2b, when assembly is in blocking mode, consider the generation of the Hot charge carriers in drift control 2b, electronics and hole can be produced, hole is left via join domain 3b conduction, and electronics is retained in drift control 2b and can bear charging for a long time and drift about controlled area 21.
In order to prevent this charging of drift control 2b, drift control 2b can be connected to drain metallization 56 via the rectifier element 69 of the such as diode in the fringe region 104 of such as semiconductor body 100 etc.In the exemplary embodiment, insulated trench 103 is being arranged in 2, 103 3between lateral isolation semiconductor mesa 100f in form fringe region 104.The Figure 31 be similar to above with reference to diode 65 explained, rectifier element 69 also can be formed as diode 69 in semiconductor mesa 100f.
Typically, there is multiple lattice defect along edge 13, defect brings the enough conductivity of the semiconductor body along edge 13.Lattice defect comes from segmentation, such as, wafer is cut apart into each semiconductor body.Due to insulated trench 103 3the first insulating barrier 21, avoid lattice defect to the further drift of active region and thus add the reliability of semiconductor subassembly 3004.
Near first surface 101, the fringe region 104 of semiconductor body 100 is typically in the electromotive force identical with the back side, such as, is in drain potential.When semiconductor subassembly 3004 is in blocking mode, join domain 3b is in the electromotive force being starkly lower than drain potentials.When assembly is in blocking mode, thus fringe region 104 is in drain potentials, and join domain 3b is in significantly lower electromotive force.When assembly is in blocking mode, via rectifier element 69, bonding pad 4b is approximately in drain potentials.Electrical potential difference when considering that assembly is in blocking mode between join domain 3b and bonding pad 4b, as dotted line 25 schematically shows, is laterally forming space charge region in drift control 2b.Voltage difference is born in space charge region.In order to affect electric field, can provide field plate 10, one of them field plate is connected to the bonding pad 4b of semiconductor mesa 100b and field plate is connected to the bonding pad 6f of semiconductor mesa 100f via diode 69.
The optional semiconductor regions 1b more highly doped than drift control 2b guarantees that drift control 2b is at drain electrode end, that is, near back surface 102', in all points in identical electromotive force.
Should be understood that, replace the edge termination using field plate 10, other edge termination that can be known in using priciple, such as based on field ring, the doping that partially or completely can exhaust (change of VLD edge, laterally doping), has the combination of insulation, the covering of semi-insulating or electric active layer, their combination and they and field plate 10.
Rectifier element 69 can be embodied as diode, and can not have special high pressure blocking ability in the other direction, but at least prevents from overflowing from drift controlled area 21 at the directional cumulation electric charge of drain electrode.But leave via rectifier element 69 flowing under the condition being conducting state at Component driver to prevent the electric charge carrier (being namely hole when n adulterates assembly) accumulated in drift controlled area 2b, bonding pad 4b can by high doping.
Typically, be similar to and explain for diode 65 with reference to Figure 31, rectifier element 69 is also integrated in semiconductor body 100.Moreover the edge termination structure of semiconductor subassembly 3004 and fringe region 104 also can be integrated in the semiconductor subassembly 3000 and 3002 explained above with reference to Figure 31 and 32 respectively.Method described herein can also be used to manufacture the semiconductor subassembly of gained.
The method for the manufacture of semiconductor subassembly as explained herein has the same technique of following public affairs: provide the semiconductor body with first surface and the second surface relative with first surface; Formation extends at least one insulated trench semiconductor body from first surface; The one or more sidewalls of at least one insulated trench form the first insulating barrier; The semi-conducting material of semiconductor body is removed from second surface; And form in the surface formed by removing semi-conducting material from second surface the second insulating barrier extending to the first insulating barrier.Typically, formed by the first insulating barrier and the second insulating barrier at least two semiconductor mesas insulated from each other.
According to an embodiment of the method for the manufacture of semiconductor subassembly, the method comprises: provide the semiconductor body with first surface and the second surface relative with first surface; Formation extends to the insulated trench semiconductor body from first surface; The one or more sidewalls of insulated trench form the first insulating barrier; The semi-conducting material of semiconductor body is removed at least to expose the part of the first insulating barrier or at least to remove the part of the first insulating barrier from second surface; And form the second insulating barrier extending to the first insulating barrier on a second surface.
Typically, in the vertical section being substantially orthogonal to first surface, at least two insulated trenchs are formed with semiconductor mesa separated from one another.
Alternatively, by etching wide groove, the sidewall by insulator covering wide raceway groove, the bottom from groove remove insulator and use the single-crystal semiconductor material space that fills in the blanks to form 2 parts of two insulated trenchs or an insulated trench typically via selective epitaxial.
According to an embodiment of the method for the manufacture of semiconductor subassembly, the method comprises: provide the semiconductor body with first surface and the second surface relative with first surface; Formed and to extend to semiconductor body from first surface and in the horizontal plane of semiconductor body, to limit the insulated trench of the via regions of semiconductor body; At least on the one or more sidewalls of insulated trench, form the first insulating barrier; The semi-conducting material of semiconductor body is removed at least to expose the part of the first insulating barrier, at least to remove the part of the first insulating barrier or leave the semiconductor layer that thickness is less than 1 μm at least in part between the first insulating barrier and second surface from second surface; In via regions, the first contact electrode is formed in the region of first surface; And in via regions, the second contact electrode is formed in the region of second surface.
According to an embodiment, the method also comprises the second insulating barrier being formed on a second surface and extend to the first insulating barrier.
According to an embodiment, insulated trench is formed as closed ring.
Typically, via regions by insulated trench around.And, via regions can be arranged in by insulated trench around semiconductor regions outside.
According to an embodiment, the edge of insulated trench and semiconductor body or form closed ring together with being arranged on semiconductor body scribe line.
According to another embodiment, remove semi-conducting material from second surface, the first insulating barrier is exposed.
According to an embodiment, the method also comprises formation first insulated trench, and this first insulated trench forms the first ring closed; And forming the second insulated trench, this second insulated trench forms the second ring closed in the first ring closed, and wherein via regions is arranged between the first insulated trench and the second insulated trench.
According to an embodiment, the method also comprises introduces dopant atom to via regions.This dopant atom such as can be introduced via insulated trench and/or first surface.
According to an embodiment, the method also comprises use first insulating barrier and fills insulated trench completely.
According to an embodiment, the sidewall that the method is also included in insulated trench is formed the first insulating barrier and residue groove is retained and uses packing material to fill residue groove.Packing material can be electrical conductivity material.
According to an embodiment, the method is also included in the via regions below first surface and forms doped contact region, and manufactures the first contact electrode, makes its contact doping contact area.
According to an embodiment, the method manufactures insulation after being also included in and exposing the first insulating barrier on a second surface on insulated trench.
According to an embodiment, the method is also included in via regions and manufactures contact trench; Electrical conductivity material is used to fill contact trench at least in part; Electric conducting material is exposed at second surface; And manufacture the second contact electrode, make the second contact electrode contact electric conducting material.Typically, electric conducting material is the polysilicon semiconductor material of metal or doping.
According to an embodiment, insulated trench and contact trench use one or more common method step manufacture.
According to an embodiment, the method also comprises the gate electrode that manufacture electricity is connected to the first contact electrode in the region of first surface; Below first surface, manufacture source region and manufacture on first surface at least in part electricity be connected to source region and with the source electrode of gate electrode electrical insulation; And manufacturing and the drain electrode of the second contact electrode electrical insulation on second surface, thus formation MOS transistor.
According to an embodiment, the method also comprises the second semiconductor layer provided for semiconductor body on the top of the first semiconductor layer and the first semiconductor layer, wherein the first semiconductor layer limits second surface, and the second semiconductor layer limits first surface, and wherein in the second semiconductor layer, form source region.
According to an embodiment, semiconductor subassembly is embodied as MOS transistor, also comprises: electricity is connected to the gate electrode of the first contact electrode in the region of first surface; Be arranged in the source region below first surface; Electricity be connected to source region, with gate electrode electrical insulation and the source electrode be arranged at least in part above first surface; And with the drain electrode of the second contact electrode electrical insulation on second surface.
Although disclosed various exemplary embodiment of the present invention, to those skilled in the art, clearly, can make a variety of changes under condit without departing from the spirit and scope of the present invention and revise, these changes and amendment will realize advantages more of the present invention.To those skilled in the art clearly, other assemblies performing identical function can suitably be replaced.Should mention, even if do not having in specifically mentioned situation, with reference to specific pattern explain feature can with the Feature Combination of other figure.And method of the present invention can use suitable processor instruction with full software realization mode or to utilize the mixing implementation of the combination of hardware logic and software logic to realize to obtain identical result.This amendment for inventive concept is intended to be overwritten by the appended claims.
The space relative terms such as term D score, " below ", " beneath ", " on ", " on " is simple to explain that an elements relative is in the location of another element for what describe.Except the orientation different from the orientation illustrated in figure, these terms are also intended to the different orientation containing device.Such as the term such as " first ", " second " is also for describing various element, region, part etc. but being also not limited thereto.Run through specification, similar term represents similar element.
When using at this, term " has ", " containing ", " comprising ", " comprising " etc. are the element of instruction statement or the existence of feature but do not get rid of the open-ended term of add ons or feature.Unless linguistic context clearly indicates, otherwise article " ", " one " and " being somebody's turn to do " are intended to comprise plural number and odd number.
Consider modification and the application of above-mentioned scope, should be appreciated that the present invention does not limit by above-mentioned specification, also do not limit by accompanying drawing.But the present invention is only limited by claims and legal equivalents thereof.
1., for the manufacture of a method for semiconductor subassembly, comprising:
The semiconductor body with first surface and the second surface relative with first surface is provided;
Form the insulated trench entering into semiconductor body from first surface;
Complete side walls along insulated trench is adjacent to insulated trench form doped semiconductor region in the semiconductor body;
At least on the one or more sidewalls of insulated trench, form the first insulating barrier;
The semi-conducting material of semiconductor body is removed to expose the base section of the first insulating barrier and to form back surface from second surface; And
Deposit the second insulating barrier on the back surface,
Make, formed by the first insulating barrier and the second insulating barrier at least two semiconductor mesas insulated from each other.
2. method according to claim 1, wherein this second insulating barrier comprises at least one in silica, silicon nitride, silicon oxynitride, aluminium nitride, diamond-like-carbon, Pyrex, spin-coating glass, organosilicon, polyimides, parylene or polybenzocyclobutene, organosilicate dielectric and cured resin.
3. method according to claim 1 and 2, wherein the first insulating barrier fills this insulated trench completely.
4. method according to claim 1 and 2, uses filled with conductive material insulated trench before being also included in deposition second insulating barrier.
5. method according to claim 1 and 2, wherein this second insulating barrier is deposited on the back surface by without mask ground.
6. method according to claim 1 and 2, wherein forms insulated trench and comprises rich construction skill.
7. method according to claim 1 and 2, wherein insulated trench forms closed ring.
8. method according to claim 1 and 2, the semi-conducting material wherein removing semiconductor body comprises at least one in grinding, polishing, CMP and etching.
9. method according to claim 1 and 2, wherein by removing the semi-conducting material of semiconductor body, semiconductor body is thinned to the vertical thickness between first surface and back surface being less than 50 μm.
10. method according to claim 1 and 2, wherein this semiconductor body comprises epitaxial loayer and wherein this insulated trench is etched through this epitaxial loayer completely.
11. methods according to claim 1 and 2, wherein by removing the semi-conducting material of semiconductor body, semiconductor body is thinned to the vertical thickness between first surface and back surface, wherein insulated trench is etched to vertical depth, and wherein this vertical thickness than this vertical depth little 5% to 30%.
12. methods according to claim 1 and 2, before being also included in the semi-conducting material removing semiconductor body, carrier system install semiconductor body by first surface.
13. methods according to claim 12, wherein install semiconductor body and comprise semiconductor body is attached to glass substrate on carrier system.
14. methods according to claim 1 and 2, at least one in further comprising the steps of:
Diode structure is formed at least one at least two semiconductor mesas;
In at least one at least two semiconductor mesas or on form capacitance structure;
Transistor arrangement is formed at least one at least two semiconductor mesas;
At least one on the first surface and at least two semiconductor mesas forms gate electrode structure;
Formation extends to the trench gate electrode structure at least one at least two semiconductor mesas from first surface; And
Formed on the first surface between at least two semiconductor mesas and/or to diode structure and/or to capacitance structure and/or to transistor arrangement and/or to gate electrode structure and/or the wiring to trench gate electrode structure.
15. methods according to claim 1 and 2, at least one in further comprising the steps of:
Partly remove the second insulating barrier to expose at least one at least two semiconductor mesas on the back surface; And
Form the metallization with at least one ohmic contact at least two semiconductor mesas on the back surface.
16. 1 kinds, for the manufacture of the method for semiconductor subassembly, comprising:
Etching partly enters into the insulated trench of semiconductor body from first surface;
The one or more sidewalls of insulated trench form the first insulating barrier;
Process second surface comprises at least one in grinding, polishing, CMP and etching to expose the first insulating barrier; And
On the second surface of process, deposition extends to the second insulating barrier of the first insulating barrier.
17. methods according to claim 16, wherein at least two semiconductor mesas are formed in the semiconductor body, and described at least two semiconductor mesas are laterally insulated by the first insulating barrier.
18. method according to claim 17, wherein after completing process semiconductor subassembly, at least one in two semiconductor mesas is insulated on the second surface of process completely by the second insulating barrier.
19. methods according to claim 17 or 18, at least one in further comprising the steps of before process second surface:
In at least one at least two semiconductor mesas or on form electronic building brick; And
To be formed on the first surface between at least two semiconductor mesas and/or to the wiring of electronic building brick.
20. methods according to claim 16 or 17, complete from first surface process semiconductor subassembly before being also included in process second surface.
21. methods according to claim 16 or 17, before being also included in process second surface, form TEDFET structure in the semiconductor body, wherein the first insulating barrier forms the accumulated oxygen compound of TEDFET structure.
22. 1 kinds of semiconductor subassemblies, comprising:
There is the semiconductor body of first surface and the back surface relative with first surface;
Formed in the semiconductor body and comprise at least one insulated trench of the first insulating barrier extending to back surface from first surface;
Complete side walls along insulated trench is adjacent to the doped semiconductor region formed in the semiconductor body with insulated trench;
Be deposited on the second insulating barrier on the back surface of semiconductor body, this second insulating barrier comprises at least one in aluminium nitride, diamond-like-carbon, Pyrex, spin-coating glass, organosilicate dielectric, organosilicon, polyimides, parylene or polybenzocyclobutene and cured resin; And
At least two semiconductor mesas formed in the semiconductor body, these at least two semiconductor mesas are laterally insulated by the first insulating barrier, and at least one in two semiconductor mesas is insulated on the back surface completely by the second insulating barrier.
23. semiconductor subassemblies according to claim 22, wherein this semiconductor subassembly is TEDFET, and wherein the first insulating barrier of this at least one insulated trench forms the accumulated oxygen compound of TEDFET.
24. semiconductor subassemblies according to claim 22 or 23, comprise by corresponding insulated trench and the second insulating barrier multiple semiconductor mesas insulated from each other.
25. semiconductor subassemblies according to claim 22 or 23, wherein this at least one insulated trench is imperforate.
26. 1 kinds, for the manufacture of the method for semiconductor subassembly, comprising:
Form insulated trench, it to extend to semiconductor body from first surface and in the horizontal plane of semiconductor body, has geometry and makes insulated trench limit the via regions of semiconductor body;
The semi-conducting material of semiconductor body is removed at least to expose the part of the first insulating barrier, at least to remove the part of the first insulating barrier or to leave the semiconductor layer that between the first insulating barrier and second surface, thickness is less than 1 μm at least in part from second surface;
In via regions, the first contact electrode is formed in the region of first surface; And
In via regions or partly, in via regions, the second contact electrode is formed in the region of second surface.
27. methods according to claim 26, wherein this at least one insulated trench is imperforate.
28. methods according to claim 26 or 27, wherein insulated trench forms closed ring.
29. methods according to claim 26 or 27, wherein this via regions by insulated trench around.
30. methods according to claim 29, wherein this via regions be arranged in by insulated trench around semiconductor regions outside.
31. the method according to claim 26 or 27, wherein insulated trench and semiconductor body edge or form closed ring together with being arranged on semiconductor body scribe line.
32. methods according to claim 26 or 27, wherein remove semi-conducting material from second surface, the first insulating barrier are exposed.
33. methods according to claim 26 or 27, also comprise:
Form the first insulated trench, this first insulated trench forms the first ring closed; And
Form the second insulated trench, this second insulated trench forms the second ring closed in the first ring closed,
Wherein via regions is arranged between the first insulated trench and the second insulated trench.
34. methods according to claim 26 or 27, also comprise and being incorporated in via regions by dopant atom.
35. methods according to claim 34, wherein dopant atom is introduced via insulated trench and/or first surface.
36. methods according to claim 26 or 27, also comprise use first insulating barrier and fill insulated trench completely.
37. methods according to claim 26 or 27, also comprise:
The sidewall of insulated trench is formed the first insulating barrier, residue groove is retained; And
Packing material is used to fill residue groove.
38. according to method according to claim 37, and wherein packing material is electrical conductivity material.
39. methods according to claim 26 or 27, also comprise:
In via regions, doped contact region is formed below first surface; And
Manufacture the first contact electrode, make its contact doping contact area.
40. methods according to claim 26 or 27, are also included in after exposing the first insulating barrier and on insulated trench, manufacture insulation on a second surface.
41. methods according to claim 26 or 27, also comprise:
Contact trench is manufactured in via regions;
Electrical conductivity material is used to fill contact trench at least in part;
Electric conducting material is exposed at second surface; And
Manufacture the second contact electrode, make the second contact electrode contact electric conducting material.
42. methods according to claim 41, wherein electric conducting material is the polysilicon semiconductor material of metal or doping.
43. methods according to claim 41, wherein insulated trench and contact trench use one or more common method step manufacture.
44. methods according to claim 26 or 27, wherein semiconductor subassembly is MOS transistor, and the method also comprises:
Manufacture the gate electrode that electricity is connected to the first contact electrode in the region of first surface;
Manufacture source region below first surface and electricity be connected to source region and with gate electrode electrical insulation at least partially in the source electrode on first surface; And
Manufacture the drain electrode with the second contact electrode electrical insulation on second surface.
45. methods according to claim 44, also comprise:
For semiconductor body provides the second semiconductor layer on the first semiconductor layer and the first semiconductor layer,
Wherein this first semiconductor layer limits second surface, and this second semiconductor layer limits first surface; And
Wherein this source region is formed in the second semiconductor layer.
CN201110408395.5A 2010-12-10 2011-12-09 For the manufacture of the method for semiconductor subassembly with insulator-semiconductor table top CN102543870B (en)
US12/964,865 US9142665B2 (en) 2010-12-10 2010-12-10 Semiconductor component with a semiconductor via
US12/964865 2010-12-10
US13/288,271 US9396997B2 (en) 2010-12-10 2011-11-03 Method for producing a semiconductor component with insulated semiconductor mesas
US13/288271 2011-11-03
CN102543870A CN102543870A (en) 2012-07-04
CN102543870B true CN102543870B (en) 2016-01-20
ID=46144773
CN201110408395.5A CN102543870B (en) 2010-12-10 2011-12-09 For the manufacture of the method for semiconductor subassembly with insulator-semiconductor table top
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CN (1) CN102543870B (en)
DE (1) DE102011056157A1 (en)
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2011-11-03 US US13/288,271 patent/US9396997B2/en active Active
2011-12-08 DE DE102011056157A patent/DE102011056157A1/en active Pending
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