Source: https://patents.google.com/patent/US9536575B2/en
Timestamp: 2019-10-22 16:40:30
Document Index: 719969829

Matched Legal Cases: ['Application No. 62', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4', 'Art-4']

US9536575B2 - Power source for memory circuitry - Google Patents
US9536575B2
US9536575B2 US14/877,692 US201514877692A US9536575B2 US 9536575 B2 US9536575 B2 US 9536575B2 US 201514877692 A US201514877692 A US 201514877692A US 9536575 B2 US9536575 B2 US 9536575B2
US14/877,692
US20160203845A1 (en
2015-01-14 Priority to US201562103273P priority Critical
2015-10-07 Priority to US14/877,692 priority patent/US9536575B2/en
2016-07-14 Publication of US20160203845A1 publication Critical patent/US20160203845A1/en
2017-01-03 Publication of US9536575B2 publication Critical patent/US9536575B2/en
An integrated circuit comprises a power supply input pin for receiving an off-chip supply voltage which can have a variable current, an on-chip power source to be powered by the off-chip supply voltage and which can provide a regulated current, a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a configuration memory storing a set of one or more memory settings that indicate whether a circuit of said set of one or more circuits is powered by the on-chip power source, and control circuitry responsive to the at least one memory setting to control whether said circuit of said set of one or more circuits is powered by the on-chip power source.
This application claims the benefit of U.S. Provisional Patent Application No. 62/103,273, filed 14 Jan. 2015 entitled Regulate Power Source of Charge Pump for Low Power Application. This application is incorporated by reference herein.
Various embodiments of the technology control the peak power consumption, by providing a regulated current to high current/high power parts of an integrated circuit.
One aspect of the technology is an integrated circuit comprising a power supply input pin, an on-chip power source, a configuration memory storing a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a set of one or more memory settings, and control circuitry.
The power supply input pin is for receiving an off-chip supply voltage, which can have a variable current. The on-chip power source is to be powered by the off-chip supply voltage. The set of one or more memory settings indicate whether at least one circuit of said set of one or more circuits is powered by the on-chip power source. The control circuitry is responsive to the set of one or more memory settings to control whether said at least one circuit is powered by the on-chip power source.
In one embodiment of the technology, the set of one or more circuits includes a charge pump driven by a multi-phase clock signal, the multi-phase clock signal having a voltage-versus-time slope determined by a regulated current, which can be provided by the on-chip power source. In various embodiments of the technology, the charge pump includes a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality. The charge pump stages of the plurality include an input node, an output node, a pass transistor electrically coupling the input node and the output node, a first boost capacitor coupled to the output node, and a second boost capacitor coupled to a gate of the pass transistor.
In some embodiments of the technology, the memory settings indicate whether at least one of: (i) the first boost capacitors, (ii) the second boost capacitors, and (iii) the input node of a first stage are powered by the on-chip power source providing a regulated current.
In some embodiments of the technology, the input node is defined by a first region in the well. The output node is defined by a plurality of second regions in the well. The first region is in between the plurality of second regions.
In some embodiments of the technology, the on-chip power source includes a plurality of parallel current sources. The integrated circuit apparatus includes an additional set of one or more memory settings that indicate whether a particular parallel current source of the plurality of parallel current sources provides current that is included in a regulated current that can be provided by the on-chip power source.
One embodiment further comprises a semiconductor body having a particular conductivity type; a first well in said semiconductor body having said particular conductivity type; a second well in said semiconductor body surrounding said first well and having an opposite conductivity type relative to the particular conductivity type; a plurality of transistors arranged to pump a voltage level from a first transistor to a last transistor in response to one or more clock signals, said last transistor having a voltage level substantially higher than, or negative relative to, a power supply voltage coupled to said plurality of transistors; and at least one of said plurality of transistors having a source and a drain region of said opposite conductivity type formed in said first well, said first well, said second well and said drain region being coupled to a common potential, wherein the set of one or more circuits includes the plurality of transistors.
accessing a set of one or more memory settings that indicate whether at least one circuit of a set of one or more circuits is powered by an on-chip power source providing a regulated current, the on-chip power source powered by an off-chip supply voltage via a power supply input pin having a variable current; and
responsive to the set of one or more memory settings, controlling whether said at least one circuit is powered by the on-chip power source.
FIG. 17 is a schematic diagram of a four-stage charge pump.
FIG. 18 shows timing diagram of clock signals pulses that can be used with the charge pump of FIG. 17.
FIG. 19 shows, schematically, a cross sectional view of a triple well NMOS transistor.
FIG. 20 is the top view of four triple well transistors that can be used in the charge pump of FIG. 17.
FIGS. 21A-21C show voltage profiles at various points of the charge pump of FIG. 17.
The present technology relates to using triple well transistors to increase the efficiency of a charge pump. The inventive charge pump comprises a plurality of pumping transistors arranged to increase the voltage level, or push the voltage lend to a negation valve, from a first pumping transistor to a last pumping transistor in response to clock pulses applied to these pumping transistors. At least one of the plurality of pumping transistors has a source and a drain region of a first conductivity type formed on a first well having an opposite conductivity type.
A second well having the first conductivity type can be formed outside of the first well. The second well is fabricated on a substrate. This transistor design is commonly referred to as a “triple well” transistor. The source region, first well and the second well are preferably set to substantially the same potential. In one embodiment, the second well can be set to the highest positive potential of the charge pump.
The triple well pumping transistor can be used in positive voltage and negative voltage charge pumps.
The present technology related is to a novel charge pump system.
FIG. 17 is a schematic diagram of a four-stage charge pump 2100. Charge pump 2100 comprises nine triple well NMOS transistors 2102-2110 and twelve normal NMOS transistors 2112-2119 and 2132-2135. These normal NMOS transistors are preferably native n-channel devices that have a low threshold voltage. Normal NMOS transistors 2132-2135 function as pull up transistors. Normal NMOS transistors 2112-2119 function as capacitors, and are coupled to clock signals 2122-2129. Regulated current power 2101 has output clock signal buses that generate the clock signals 2122-2129. The clock signals are coupled to the corresponding triple well NMOS transistors via the capacitive action of transistors 2112-2119. Although there are eight clock signals, they are arranged in pairs: (2122,2124), (2123,2125), (2126,2128), and (2127,2129). Each clock signal in a pair has the same signal timing while different pairs have different signal timings. The clock signals are shown in FIG. 18 where timings 2192-2195 correspond to pairs (2127,2129), (2122,2125), (2126, 2128) and (2123, 2125), respectively. The clock signals have a voltage-vs-time slope (such as 2191) that is determined by the regulated current generated by the on-chip power supply. These signals alternatively boost up the gates of these capacitors. This results in an increase in voltage level from stage to stage. The way voltage is being pumped up is similar to a conventional charge pump. In one embodiment, the output voltage at the source terminal of triple well NMOS 2110 is approximately 10.5 volts while the voltage supplied to charge pump 2100 is only 3 volts. As explained in detail below, the use of these triple well transistors (instead of normal NMOS transistors) enhances the performance and efficiency of charge pump 2100 compared to prior art four-stage charge pumps.
FIG. 19 shows, schematically, a cross sectional view of a triple well NMOS transistor 2200 that can be used for transistors 2102-2110 of FIG. 17. Transistor 2200 is fabricated on a p-type substrate 2202. An N well 2204 is formed in substrate 2202, and a P well 2206 is formed in N well 2204. An N+ type drain region 2210 is formed in P well 2206, as is an N+ source region 2212. A channel region 2214 is defined between source and drain regions in P well 2206. A polysilicon gate 2216 is positioned above channel region 2214. A thin gate oxide is deposited between gate 2216 and channel region 2214. Drain region 2210, gate 2216, source region 2212, P well 2206, and N well 2204 are coupled to individual terminals 2220-2224, respectively. Thus, triple well transistor 2200 can be considered a five-terminal device. In one embodiment, the N+ source and N+ drain are interchangeable when the charge pump is activated because either terminal may have higher potential than the other.
In one embodiment, the potential of source region 2212, P well 2206 and N well 2204 are set to the same value. One way to meet this condition is to electrically connecting terminals 2222, 2223 and 2224. The potential of substrate 2202 is normally set to ground. This arrangement creates a PN diode between P well 2206 and drain region 2210. The diode is inherent in this triple well construction, and does not occupy any extra silicon area. This diode is able to conduct significant amount of current after it is turned on, and thus adds an extra low resistance path to the NMOS transistor. In this application, this diode is called an “extra diode.” As explained in more detail below, this extra diode has the following advantageous effects:
(1) The size of the pass gate of the triple well NMOS transistors 2102-2109 can be reduced because some of the current for charging the next stage NMOS capacitors (i.e., transistors 2112-2119) can be conducted by the extra diode.
(2) Because the size of the NMOS transistors 2102-2109 can be reduced, their parasitic capacitance is reduced. As a result, less power is consumed and the pump output current can be increased.
(4) The extra diode conduction path reduces the peak voltage swing at the output transistor 110 from VDD+Vout to 0.7+Vout volts, where VDD is the power supply voltage and Vout is the output voltage at an output terminal 2138 of charge pump 2100. As a result, the internal voltage stress of the charge pump is reduced.
As a result of the above mentioned advantages, the performance of charge pump 2100 improves tremendously by the presence of this diode. This benefit is achieved without requiring any silicon real estate.
It can be seen from the above equation that applying a voltage across a reverse-biased source-substrate junction tends to increase the threshold voltage of a transistor. In the triple well transistor, VBS is limited within the P-N junction cut-in voltage of 0.7 volt. This is because when pumping is activated, charge flows from N+ diffusion region 2212 to N+ diffusion region 2210 through channel 2214 and the extra diode created by well 2206 and region 2210. Thus, the lower potential N+ diffusion region 2210, which is the source, suffers minimized substrate bias around 0.7 volt which is much less as compared to more than 10 volts of substrate bias in prior art regulator NMOS charge pumps. In a charge pump circuit, it is important to generate high forward conduction current so that charges can be build up quickly. A low threshold voltage allows the NMOS channels to be turned on faster, and thus can increase the pumping frequency. Because the threshold voltage of the triple well NMOS transistor is very low, the pumping frequency of the present inventive charge pump can be much higher than prior art charge pumps. In an embodiment, the charge pump can operate efficiently at 22 MHz while prior art charge pump typically operates at 10 MHz.
FIG. 20 shows a top view 2250 of four triple well transistors. It shows two transistors 2252 and 2254 formed inside a P well 2258 and an N well 2256. Transistor 2252 further comprises a gate 2260, a source region 2262 and a drain region 2264. Transistor 2252 could correspond to transistor 2102 of FIG. 17. Transistor 2254 further comprises a gate 2270, a source region 2272 and a drain region 2274. Transistor 2254 could correspond to transistor 2106 of FIG. 17.
FIG. 20 also shows two transistors 2282 and 2284 formed inside a P well 2288 and an N well 2286. Transistor 2282 further comprises a gate 2290, a source region 2292 and a drain region 2294. Transistor 2282 could correspond to transistor 2103 of FIG. 17. Transistor 2284 further comprises a gate 2280, a source region 2282 and a drain region 2284. Transistor 2284 could correspond to transistor 2107 of FIG. 17.
Referring to both FIGS. 17 and 20, the source terminal 2141 of transistor 2102 and source terminal 2142 of transistor 2106 are connected to VDD. Thus, source regions 2262 and 2272 of transistors 2252 and 2254, respectively, have the same potential (i.e., VDD. As explained above, P well 2258 and N well 2256 should have the same potential as source regions 2262 and 2272. Thus these two wells also have the same potential (VDD).
FIG. 17 shows that the gate terminal 2144 of transistor 2102 is connected to the drain terminal 2145 of transistor 2106, the source terminal 2146 of transistor 2103 and the source terminal 2147 of transistor 2107. As explained above, P well 2288 and N well 2286 should have the same potential as source regions 2292 and 2302 (which are coupled to source terminals 2146 and 2147). Thus in FIG. 20, gate 2260, drain region 2274, source regions 2292 and 2302, N well 2286 and P well 2288 all have the same potential.
FIG. 17 shows that the drain terminal 2150 of transistor 2102 is connected to the gate 2151 of transistor 2106. Thus, in FIG. 20, drain region 2264 has the same potential as gate 2270.
FIG. 17 shows that the gate terminal 2153 of transistor 2103 is connected to the drain terminal 2154 of transistor 2107 (in addition to the source terminals 2155 and 2156 of transistors 2104 and 2108). Thus in FIG. 20, gate 2290 has the same potential as drain region 2304. FIG. 17 also shows that the drain terminal 2158 of transistor 2103 is connected to the gate 2159 of transistor 2107. Thus, in FIG. 20, drain region 2294 has the same potential as gate 2300.
In FIG. 20, only four of the nine triple well NMOS transistors comprising a charge pump are shown. The structure of transistors 2104-2105 and 2108-2109 is similar to that shown in FIG. 20. The structure of transistor 2110 is similar to that of transistor 2254 of FIG. 20.
In one embodiment, the channel lengths of all the triple well transistors are 1.2 μm. The channel widths of transistors 2252 and 2282 (corresponding to transistors 2102 and 2103 of FIG. 17) are 6 μm while the channel widths of transistors 2254 and 2284 (corresponding to transistors 2106 and 2107 of FIG. 17) are 18 μm. Transistors 2104 and 2105 have the same structure as transistors 2102 and 2103, respectively. Thus, these two transistors also have a channel length of 1.2 μm and a channel width of 6 μm. Transistors 2108 and 2109 have the same structure as transistors 2106 and 2107, respectively. Thus, these two transistors also have a channel length of 1.2 μm and a channel width of 18 μm. For the output transistor 2110 of FIG. 17, the channel width is 15 μm.
The dimension of normal transistors 2112-2119 and 2132-2135 of the same embodiment is shown in Table 1.
TABLE 1 Transistor Channel Length (μm) Channel Width (μm) 2112 10 18 2113 10 18 2114 20 18 2115 20 24 2116 120 60 2117 120 60 2118 120 60 2119 120 60 2132 1.2 4 2133 1.2 4 2134 1.2 4 2135 1.2 4
I determine the improvement of the triple well transistors over normal transistors in a charge pump, four tables showing the pump load lines are presented below. In each table, the two right hand columns correspond to the load line of a charge pump constructed using the preferred triple well transistor. The two columns to the left of these two right hand columns correspond to the load line of the same charge pump constructed using normal transistors. It is observed that the inventive charge pump has a higher current at almost all voltage levels.
TABLE 2 pump load line, VDD = 2 v, temp = 25 C. Iout measure by root-mean-square, unit in mA Vout/ Prior Art-4- Prior Art-4- Prior Art-4- Prior Art-4- Iout Phase 7.3 MHz Phase 22 MHz Phase 7.3 MHz Phase 22 MHz 10 v 0.0 0.0 0.0 0.0 9 v 0.0 0.0 0.01 0.02 8 v 0.01 0.01 0.04 0.1 7 v 0.04 0.05 0.09 0.24 6 v 0.08 0.12 0.19 0.48 5 v 0.34 0.19 0.27 0.75
TABLE 3 pump load line, VDD = 2 v, temp = 25 C. Iout measure by average, unit in mA Vout/ Prior Art-4- Prior Art-4- Prior Art-4- Prior Art-4- Iout Phase 7.3 MHz Phase 22 MHz Phase 7.3 MHz Phase 22 MHz 10 v 0.0 0.0 0.0 0.0 9 v 0.0 0.0 0.01 0.02 8 v 0.01 0.01 0.03 0.9 7 v 0.04 0.05 0.06 0.17 6 v 0.06 0.11 0.08 0.25 5 v 0.09 0.166 0.10 0.31
TABLE 4 pump load line, VDD = 3 v, temp = 25 C. Iout measure by Root-mean-square, unit in mA Vout/ Prior Art-4- Prior Art-4- Prior Art-4- Prior Art-4- Iout Phase 7.3 MHz Phase 22 MHz Phase 7.3 MHz Phase 22 MHz 10 v 0.11 0.266 0.29 0.75 9 v 0.176 0.396 0.05 1.39 8 v 0.256 0.548 0.75 1.6 7 v 0.341 0.712 0.92 1.75 6 v 0.419 0.799 1.25 1.8 5 v 0.47 0.952 1.35 1.98
TABLE 5 pump load line, VDD = 3 v, temp = 25 C. Iout measure by average, unit in mA Vout/ Prior Art-4- Prior Art-4- Prior Art-4- Prior Art-4- Iout Phase 7.3 MHz Phase 22 MHz Phase 7.3 MHz Phase 22 MHz 10 v 0.078 0.217 0.107 0.302 9 v 0.108 0.300 0.128 0.423 8 v 0.137 0.386 0.157 0.400 7 v 0.167 0.468 0.178 0.496 6 v 0.190 0.520 0.205 0.504 5 v 0.203 0.597 0.222 0.532
(1) The charge pump functions efficiently at low VDD voltage. For example, the performance improvement of the inventive charge pump over prior art charge pumps at VDD=2 volts is greater than that at VDD=3 volts. It is found that the inventive charge pump can operate effectively down to 1.5 volt.
(2) The charge pump can operate efficiently at 22 MHz. For example, Table 2 shows that the output current for the inventive charge pump at 22 MHz is about 2.5 times that at 7.3 MHz (Vout=7 v). On the other hand, there is little difference in the output current of a prior art charge pump at 22 MHz and 7.3 MHz.
The operation of charge pump 2100 is now explained. FIGS. 21A-21C show voltage profiles at nodes 2161-2168 and 2138 of FIG. 17. FIG. 21A shows four clock signals which are the same as signals 2124, 2125, 2128 and 2129 of FIG. 18. These clock signals are shown here again so as to provide a reference to understand the voltage profiles. FIG. 21B shows the voltage profiles 2361-2365 at nodes 2165-2168 and 2138, respectively. FIG. 21C shows the voltage profiles 2366-2369 at nodes 2161-2164, respectively. It can be seen at regions 2371-2373 of FIG. 21B that charges are being pumped to subsequent stages when the triple well transistors 2107-2109 are turned on. As a result, the voltages of the two adjoining stages are equal at these regions. This pumping effect is enhanced by the extra diode and reduced threshold voltage of the corresponding triple well transistor. The improved effect of other triple well transistors can be easily analyzed by person skilled in the art, and will be not explained in detail here.
a power supply input pin for receiving an off-chip supply voltage;
an on-chip power source to be powered by the off-chip supply voltage;
a set of one or more circuits;
a configuration memory storing a set of one or more memory settings that indicates whether each member of the set of one or more circuits is powered by the on-chip power source or by the off-chip supply voltage; and
control circuitry, responsive to the set of one or more memory settings, controlling whether each member of the set of one or more circuits is powered by the on-chip power source or by the off-chip supply voltage.
2. The integrated circuit of claim 1, wherein the set of one or more circuits includes a charge pump driven by a multi-phase clock signal, the multi-phase clock signal having a voltage-versus-time slope determined by a regulated current.
the set of one or more circuits includes components of a charge pump, the components of the charge pump including a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality; and
the charge pump stages of the plurality include an input node, an output node, a pass transistor electrically coupling the input node and the output node, a first boost capacitor coupled to the output node, and a second boost capacitor coupled to a gate of the pass transistor.
the set of one or more circuits includes components of a charge pump, the components of the charge pump including a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality;
a particular stage of the plurality of serially coupled charge pump stages includes:
a first transistor selectively electrically coupling an input node of the particular stage and an output node of the particular stage; and
a second transistor selectively electrically coupling the input node and a gate of the first transistor;
the particular stage is in a well surrounded by a plurality of well contacts; and
the input node is defined by a first region in the well, the output node is defined by a second region in the well, the first region and the second region are on opposite sides of the gate of the first transistor, the first region having a first distance from a nearest well contact of the plurality of well contacts averaged along a first perimeter of the first region, the second region having a second distance from another nearest well contact of the plurality of well contacts averaged along a second perimeter of the first region, the second distance shorter than the first distance.
a particular stage of the plurality of serially coupled charge pump stages includes a first transistor selectively electrically coupling an input node of the particular stage and an output node of the particular stage, and a second transistor selectively electrically coupling the input node and a gate of the first transistor;
the input node is defined by a first region in the well, the output node is defined by a plurality of second regions in the well, and the first region is between the plurality of second regions.
the on-chip power source includes a plurality of parallel current sources; and
the integrated circuit includes an additional set of one or more memory settings that indicates whether a particular parallel current source of the plurality of parallel current sources provides current that is included in a regulated current.
the on-chip power source includes:
a plurality of transistors having at least two different widths;
at least a first transistor of the plurality of transistors is in series with the reference current source; and
wherein at least a second transistor of the plurality of transistors provides an output current determined by a ratio of the at least two different widths of at least the first and the second transistors of the plurality of transistors.
8. The integrated circuit of claim 7, wherein the on-chip power source includes an operational amplifier in a loop from a gate of at least the first transistor of the plurality of transistors to the reference current source.
a semiconductor body having a particular conductivity type;
a first well in the semiconductor body having the particular conductivity type;
a second well in the semiconductor body surrounding the first well and having an opposite conductivity type relative to the particular conductivity type;
a plurality of transistors arranged to pump a voltage level from a first transistor to a last transistor in response to one or more clock signals, the last transistor having a voltage level substantially higher than, or negative relative to, a power supply voltage coupled to the plurality of transistors; and
at least one of the plurality of transistors having a source and a drain region of the opposite conductivity type formed in the first well, the first well, the second well and the drain region being coupled to a common potential,
wherein the set of one or more circuits includes the plurality of transistors.
a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source;
a configuration memory storing a set of one or more memory settings that indicates whether at least one circuit of the set of one or more circuits is powered by the on-chip power source; and
control circuitry, responsive to the set of one or more memory settings, controlling whether the at least one circuit is powered by the on-chip power source, wherein:
the charge pump stages of the plurality including an input node, an output node, a pass transistor electrically coupling the input node and the output node, a first boost capacitor coupled to the output node, and a second boost capacitor coupled to a gate of the pass transistor; and
the memory settings indicate whether at least one of: (i) the first boost capacitors, (ii) the second boost capacitors, and (iii) the input node of a first stage are powered by the on-chip power source.
accessing, from an integrated circuit, a set of one or more memory settings that indicates whether each member of a set of one or more circuits is powered by an on-chip power source or by an off-chip supply voltage, the on-chip power source powered by the off-chip supply voltage via a power supply input pin; and
responsive to the set of one or more memory settings, controlling whether each member of the set of one or more circuits is powered by the on-chip power source or by the off-chip supply voltage.
the memory settings indicate whether at least one of: (i) first boost capacitors, (ii) second boost capacitors, and (iii) an input node of a first stage are powered by the on-chip power source or by the off-chip supply voltage;
the set of one or more circuits includes components of a charge pump, the components of the charge pump including a plurality of serially coupled charge pump stages arranged to pump charge from the first stage to a last stage of the plurality; and
the charge pump stages of the plurality include the input node, an output node, a pass transistor electrically coupling the input node and the output node, the first boost capacitor coupled to the output node, and the second boost capacitor coupled to a gate of the pass transistor.
the input node is defined by a first region in the well, the output node is defined by a second region in the well, the first region and the second region on opposite sides of the gate of the first transistor, the first region having a first distance from a nearest well contact of the plurality of well contacts averaged along a first perimeter of the first region, the second region having a second distance from another nearest well contact of the plurality of well contacts averaged along a second perimeter of the first region, the first distance shorter than the second distance.
at least a second transistor of the plurality of transistors provides an output current determined by a ratio of the at least two different widths of at least the first and the second transistors of the plurality of transistors.
US14/877,692 2015-01-14 2015-10-07 Power source for memory circuitry Active US9536575B2 (en)
US201562103273P true 2015-01-14 2015-01-14
US14/877,692 US9536575B2 (en) 2015-01-14 2015-10-07 Power source for memory circuitry
TW104140996A TWI595494B (en) 2015-01-14 2015-12-07 Integrated circuit memory circuits and the method of its application
CN201510920271.3A CN105788640A (en) 2015-01-14 2015-12-11 Integrated circuit for memory circuitry and method for applying same
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