Source: http://www.google.fr/patents/US5091888?hl=fr
Timestamp: 2013-05-20 20:43:07
Document Index: 211288568

Matched Legal Cases: ['art 1', 'art 2', 'art 3', 'art 1', 'art 2', 'art 1', 'art 1', 'art 2', 'art 2', 'art 2', 'art 4', 'art 5', 'art 6', 'art 4', 'art 6', 'art 4', 'art 4', 'art 6', 'art 6', 'art 4']

Brevet US5091888 - Semiconductor memory device - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Historique Web | Connexion Recherche avanc�e dans les brevets BrevetsA semiconductor memory device comprises memory cells for storing data, reference cells for storing reference data, and an output part supplied with an output signal from the memory cells and a reference signal from the reference cells for comparing the output signal and the reference signal and producing...http://www.google.fr/patents/US5091888?utm_source=gb-gplus-shareBrevet US5091888 - Semiconductor memory device Num�ro de publicationUS5091888 AType de publicationOctroi Num�ro de demande07/552,972 Date de publication25 f�vr. 1992 Date de d�p�t12 juil. 1990 Date de priorit�13 juil. 1989Autre r�f�rence de publicationEP0408037A2EP0408037A3EP0408037B1 InventeursTakao Akaogi Cessionnaire d'origineFujitsu LimitedFujitsu Semiconductor LimitedFujitsu Microelectronics LimitedFujitsu Limited, Classification aux �tats-Unis365/185.21365/189.9 Classification internationaleG11C17/00G11C16/06G11C16/28 Classification coop�rativeG11C16/28 Classification europ�enneG11C16/28R�f�rencesCitations de brevets (2) R�f�renc� par (31)Liens externesUSPTO Cession USPTO EspacenetSemiconductor memory deviceUS 5091888 A R�sum� A semiconductor memory device comprises memory cells for storing data, reference cells for storing reference data, and an output part supplied with an output signal from the memory cells and a reference signal from the reference cells for comparing the output signal and the reference signal and producing an output signal of the semiconductor memory device indicative of the data stored in the memory cell means on the basis of the comparison. In the present invention, the reference cell includes a plurality of reference cell transistors connected in parallel with each other for storing the reference data such that a same reference data is stored in each of the reference cell transistors.
What is claimed is: 1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells for storing data, a plurality of word lines, and a plurality of bit lines, each of said memory cells comprising a memory cell transistor connected to a corresponding work line and a corresponding bit line; addressing means supplied with address data for selecting one of the word lines and one of the bit lines, said addressing means including a word line driver that activates a selected word line by supplying a word line voltage to the selected word line; said memory cell array producing an output signal indicative of the data stored in the memory cell in response to addressing by the addressing means; a reference cell array including a plurality of reference cells for storing reference data, a reference word line, and a reference bit line, each of said reference cells comprising a reference cell transistor that is connected commonly to the reference word line and the reference bit line, said reference cell transistor being further connected in parallel to the reference cell transistors that are connected commonly to the same reference word line; means for activating the reference word line by supplying a word line voltage thereto; said reference cell array producing a reference output signal indicative of the reference data in response to the activation of the reference word line; and output means supplied with the output signal from the memory cell array and the reference output signal from the reference cell array for producing a data output indicative of the data stored in the memory cell array based upon a comparison between the output signal of the memory cell array and the reference output signal of the reference cell array.
7. A semiconductor memory device as claimed in claim 4 wherein said reference cell arrray further comprises a reference bit line driver for activating the reference bit line with a reference bit line voltage that is determined not to cause erroneous wiring in the reference cells, said reference bit line driver comprising: first load means having a first end connected to a voltage source and a second end connected to the reference bit line for supplying said reference bit line voltage to said reference bit line, said bit line driver further comprising second load means having a first end connected to said voltage source and a second end connected to the bit lines for supplying said bit line voltage to said reference bit lines, said memory cell transistor assuming either of first and second states in response to the data that is stored therein, said first and second load means being so provided that said reference output signal has a level intermediate between said first state of the memory cell transistor and said second state of the memory cell transistor.
BACKGROUND OF THE INVENTION The present invention generally relates to semiconductor devices and more particularly to a so-called reference cell type semiconductor memory device for storing data in a memory cell, wherein the content of the data stored in the memory cell is identified by comparing an output of the memory cell with an output of a reference cell.
FIG. 1 shows an example of a conventional erasable programmable read-only memory (EPROM). The memory device comprises a memory part 1 including a memory cell, a reference part 2, and an output part 3, wherein the reading of data from the memory cell is made on the basis of comparison of an output voltage V.sub.M of the memory part 1 with a reference voltage V.sub.R produced by the reference part 2.
Referring to FIG. 1, the memory part 1 includes a p-channel MOS transistor 11 acting as a load resistance, an n-channel MOS transistor 12 for bit line biasing to be described later, an n-channel MOS transistor 13 for the column selection, and a memory cell 14 made of a floating gate type MOS transistor and acting as the memory cell. The MOS transistor 11 has its source connected to a power terminal 15 to which a drain voltage V.sub.DD of typically 5 volts is applied. Further, the MOS transistor 11 has a gate connected to an output terminal 16 of the memory part 1. The MOS transistor 11 has a source connected to its gate and the source of the MOS transistor 11 is connected further to a source of the MOS transistor 12. This MOS transistor 12 is used for biasing a bit line BL which is connected to a source of the memory cell 14 such that the injection of electrons into the floating gate of the memory cell 14 does not occur at the time of reading the data. For this purpose, a gate voltage of 1.2 volts is applied to the gate of the MOS transistor 12 via an input terminal 17 and in response thereto, the voltage of the bit line BL is set to be 0.9 volts. Thereby, the source voltage of the memory cell 14 is also set to be 0.9 volts. The MOS transistor 12 has its drain connected to the source of a MOS transistor 13 which is used for the column selection.
The MOS transistor 11 acting as the load resistance is fabricated to have a gate width such that a voltage of 4 volts appears at the output terminal 16 as the output voltage V.sub.M when the addressed memory cell 14 stores the logic data "0" while an output voltage of 3 volts appears at the output terminal 16 when the logic data "1" is stored in the memory cell 14.
The reference part 2 includes a p-channel MOS transistor 21 acting as a load resistance, an n-channel MOS transistor 22 for bit line biasing to be described later, an n-channel MOS transistor 23 for the column selection, and a memory cell 24 made of a floating gate type MOS transistor and acting as the memory cell. The MOS transistor 21 has its drain connected to a power terminal 25 to which the source voltage V.sub.DD of typically 5 volts is applied. Further, the MOS transistor 21 has a gate connected to an output terminal 26 of the reference part 2. The MOS transistor 21 has a source connected to its gate and the drain of the MOS transistor 21 is connected further to a source of the MOS transistor 22. This MOS transistor 22 is used for biasing a bit line BL.sub.R which is connected to a source of the memory cell 24 such that the injection of electrons into the floating gate of the memory cell 24 does not occur at the time of reading the data. For this purpose, a gate voltage of 1.2 volts is applied to the gate of the MOS transistor 22 via an input terminal 27 and in response thereto, the voltage of the bit line BL is set to be 0.9 volts. Thereby, the source voltage of the memory cell 24 is also set to be 0.9 volts. The MOS transistor 22 has its drain connected to the source of a MOS transistor 23 which is used for the column selection.
The MOS transistor 23 has a gate connected to the source voltage V.sub.DD and a drain connected to the source of the memory cell 24 via the bit line BL.sub.R and supplies the foregoing bit line voltage of 0.9 volts to the source of the memory cell 24. The memory cell 24 is made of a floating gate type MOS transistor similarly to the memory cell 14 and has a control gate connected to the word line WL in addition to the floating gate. The memory cell 24 further has a drain which is connected to the ground and stores the logic data "1". In response to the data "1" stored in the memory cell 24, the MOS transistor forming the cell 24 is turned on. It should be noted that the MOS transistor of the memory cell 24 is always biased by the source voltage V.sub.DD supplied to its gate.
The MOS transistor 21 acting as the load resistance is fabricated to have a gate width such that a voltage of 3.5 volts appears at the output terminal 26 as the output voltage V.sub.R. This voltage of 3.5 volts is the voltage intermediate between the voltage of 4.0 volts which is the value of V.sub.M for the case where the data "0" is stored in the cell 14 and 3.0 volts which is the value of V.sub.M for the case where the data "1" is stored in the memory cell 14. The foregoing relationship between the voltage V.sub.M and the voltage V.sub.R may be obtained by setting the gate width of the MOS transistor 21 twice as large as the gate width of the MOS transistor 11 when the memory cell 14 and the memory cell 24 have a same size with respect to the gate length, gate width and the like.
When reading data from the memory cell 14, the memory cell 14 is addressed in response to the column selection signal on the column bus 18 and the word line voltage on the word line WL, and the voltage on the bit line BL is changed depending on whether the data "1" is stored in the memory cell 14 or the data "0" is stored therein. The differential amplifier 31 produces either a low level output L in response to the output voltage V.sub.M of 4 volts corresponding to the data "0" stored in the memory cell 14 or a high level output H in response to the output voltage V.sub.M of 3 volts corresponding to the data "1" stored in the memory cell 14 on the basis of the comparison with the reference voltage V.sub.R which is set to be 3.5 volts as already described. In other words, the identification of the content of the data stored in the memory cell 14 can be performed on the basis of detection of the variation of the output voltage V.sub.M of only 1 volt. Thereby, a quick identification can be performed with respect to the content of the data and the access time for reading the data out from the memory cell 14 is significantly reduced.
In the foregoing conventional memory device, there arises a problem, associated with the requirement of miniaturization of the transistors forming the memory device, that a slight variation in the size of the memory cell, particularly the memory cell 24 in the reference part 2, with respect to the gate length or gate width, may cause a significant variation in the characteristic of the memory cell. When the reference voltage V.sub.R is changed, there is a substantial risk that an erroneous reading of the data is made or a relatively long time is needed in order to read the data with reliability.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing the construction of a semiconductor memory device;
DETAILED DESCRIPTION Hereinafter, a first embodiment of the present invention will be described with reference to FIG. 2.
Referring to FIG. 2, the memory device includes a memory part 4 including a memory cell, a reference part 5 and an output part 6, wherein data is stored in the memory cell and reading of the data from the memory cell is made on the basis of comparison of an output voltage V.sub.M of the memory part 4 with a reference voltage V.sub.R produced by the reference part 6.
Referring to FIG. 2, the memory part 4 includes a p-channel MOS transistor 31 acting as a load resistance, an n-channel MOS transistor 32 for bit line biasing to be described later, an n-channel MOS transistor 33 for the column selection, and a memory cell 34 made of a floating gate type MOS transistor and acting as the memory cell. The MOS transistor 31 has its drain connected to a power terminal 35 to which a source voltage V.sub.DD of typically 5 volts is applied. Further, the MOS transistor 31 has a gate connected to an output terminal 36 of the memory part 4. The MOS transistor 31 has a source connected to its gate and the source of the MOS transistor 31 is connected further to a source of the MOS transistor 32. This MOS transistor 32 is used for biasing a bit line BL which is connected to a drain of the memory cell 34 such that the injection of electrons into the floating gate of the memory cell 34 does not occur at the time of reading the data. For this purpose, a gate voltage of 1.2 volts is applied to the gate of the MOS transistor 32 via an input terminal 37 and in response thereto, the voltage of the bit line BL is set to be 0.9 volts. Thereby, the source voltage of the memory cell 34 is also set to be 0.9 volts. The MOS transistor 32 has its drain connected to the drain of a MOS transistor 33 which is used for the column selection.
The MOS transistor 31 acting as the load resistance is fabricated to have a gate width such that a voltage of 4 volts appears at the output terminal 36 as the output voltage V.sub.M when the addressed memory cell 34 stores the logic data "0" while an output voltage of 3 volts appears at the output terminal 36 when the logic data "1" is stored in the memory cell 34.
The reference cell 6 includes a p-channel MOS transistor 41 acting as a load resistance, an n-channel MOS transistor 42 for bit line biasing to be described later, an n-channel MOS transistor 43 for the column selection, and a memory cell 44 made of a floating gate type MOS transistor and acting as the memory cell. The MOS transistor 41 has its drain connected to a power terminal 45 to which the source voltage V.sub.DD of typically 5 volts is applied. Further, the MOS transistor 41 has a gate connected to an output terminal 46 of the reference cell 6. The MOS transistor 41 has a connected to its gate and the source of the MOS transistor 41 is connected further to a source of the MOS transistor 42. This MOS transistor 42 is used for biasing a bit line BL.sub.R which is connected to a source of the memory cell 44 of which construction will be described in detailed later, such that the injection of electrons into the floating gate of the memory cell 44 does not occur at the time of reading the data. For this purpose, a gate voltage of 1.2 volts is applied to the gate of the MOS transistor 42 via an input terminal 47 and in response thereto, the voltage of the bit line BL is set to be 0.9 volts. Thereby, the source voltage of the memory cell 44 is also set to be 0.9 volts. The MOS transistor 42 has its source connected to the drain of a MOS transistor 43 which is used for supplying the foregoing bit line voltage to the source of the memory cell 44. The MOS transistor 43 has a gate connected to the drain voltage V.sub.DD and a source connected to the source of the memory cell 44 via the bit line BL.sub.R.
In the present invention, the memory cell 44 includes a number of floating gate type MOS transistors 44a, 44b, 44c, . . . connected parallel with each other, wherein each of the MOS transistors has a source connected commonly to the bit line BL.sub.R, a control gate connected to a common word line WL, and a drain connected to the ground. Further, each of the MOS transistors 44a, 44b, 44c . . . stores the logic data "1". In response to the data "1" thus stored, the MOS transistors 44a, 44b, 44c . . . are turned on. By using a plurality of FETs 44a-44c connected in parallel as such, the variation of characteristic of the FETs in the memory cell 44 is averaged and one can obtain a stabilized voltage at the output terminal 46 as the reference voltage V.sub.R even when the memory device is miniaturized.
The MOS transistor 41 acting as the load resistance is fabricated to have a gate width such that a voltage of 3.5 volts appears at the output terminal 46 as the output voltage V.sub.R. The MOS transistor 41 is fabricated to have a gate width which provides the threshold such that the output voltage V.sub.R of 3.5 volts, which is intermediate between 4.0 volts which is the voltage of V.sub.M for the case where the data "0" is stored in the memory cell 34 and 3.0 volts which is the voltage of V.sub.M for the case where the data "1" is stored in the memory cell 34, is obtained at the output terminal 46.
In the present invention, it should be noted that the increase in the number of FETs forming the memory cell 44 causes an increase of current flowing through the bit line BL.sub.R. Thus, in correspondence to the increase of the current, the gate width of the FET 41 acting as the load resistance has to be increased by a multiple of the number of the FETs used in the memory cell 44 so that the output voltage V.sub.R of 3.5 volts is maintained at the output terminal 46. In the case of the conventional memory device shown in FIG. 1, the gate width of the FET 21 is chosen to be two times as large as the gate width of the MOS transistor 11 as already described. In the case of the present invention where the number of the FETs in the memory cell 44 is three as in the illustrated example, the FET 41 has to have the gate width which is six times as large as the gate width of the FET 31.
In operation, the memory cell 34 is addressed in response to the word line voltage on the word line WL and the column selection signal on the column bus 38, and the change in the output voltage V.sub.M at the output terminal 36 occurring in response to the change of the bit line voltage on the bit line BL, which change in turn occurs in response to the content of the data stored in the memory cell 34, is detected by the differential amplifier 51 on the basis of the comparison with the output voltage V.sub.R at the output terminal 46. This output voltage V.sub.R is obtained by sending the word line voltage on the word line WL simultaneously to the gate of the FETs 44a-44c.
Thus, when the content of the data in the memory cell 34 is "1", the FET forming the memory cell 34 is turned on and the voltage V.sub.M assumes the value of 3 volts, whereby the differential amplifier 51 produces a low level output L at the output terminal indicative of the logic data "1" on the basis of comparison with the voltage V.sub.R at the output terminal 46. On the other hand, when the content of the data in the memory cell 34 is "0", the FET forming the memory cell 34 is turned off and the voltage V.sub.M assumes the value of 4 volts. In response to this, the differential amplifier 51 produces a high level output H at the output terminal indicative of the logic data "0" on the basis of the comparison with the voltage V.sub.R.
As the memory device of the present invention can provide a stabilized voltage for the reference voltage V.sub.R, the memory device can operate effectively even when the transistors forming the device are miniaturized. In other words, the present invention provides a semiconductor memory having a reduced access time and capable of operating with reliability even when the device is miniaturized and the integration density increased.
The bit lines BLl-BLn are connected to a column decoder 102 which is supplied with a second address data ADDRESS2 corresponding to the column selection signal via the column bus 38, and the column decoder 102 supplies the predetermined bit line voltage of 0.9 volts selectively to one of the bit lines specified by the second address data ADDRESS2. Further, the column decoder 102 includes the FETs 31, 32, 33 and 34 connected as shown in FIG. 2 in correspondence to each of the bit lines BLl-BLn. Thus, the source voltage V.sub.DD is supplied to the column decoder 102 via the terminal 35, the gate voltage V.sub.G is supplied to the decoder 102 via the terminal 37 and the output voltage V.sub.M of the memory cell 34 is obtained at the output terminal 36 connected to the column decoder 102.
Further, there is provided a reference drive circuit 103 corresponding to the reference part 6 for supplying the bit line voltage to the field effect transistors 44a-44c forming the memory cell 44 and for producing the reference output voltage V.sub.R at the output terminal 46. It should be noted that each of the word lines WLl-WLn has the transistors 44a-44c connected thereto and the transistor 44a-44c form a part of the memory cell array.
In this embodiment, the gate of the FETs 44a-44c forming the memory cell 44 is connected commonly to an input terminal 51 to which the source voltage V.sub.DD is supplied. As the memory cell 44 is not addressed by the signal on the word line WL, the reference voltage V.sub.R is always at the output terminal 46 and the access time of the memory device can be reduced even further.
In the foregoing embodiments, it should be realized that the number of the MOS transistors forming the memory cell 44 is not limited to three but may be two or more than three. Further, the channel width of the MOS transistor 41 is not limited to two times the integer multiple of the gate width of the MOS transistor 31 with the integer multiplier equal to the number of MOS transistors forming the memory cell 44, but may be any value as long as the current flowing through the bit line BL.sub.R is maintained that the reference voltage V.sub.R at the terminal 46 is set intermediate between the voltage V.sub.M for the case of the data "1" stored in the memory cell 34 and the voltage V.sub.M for the case of the data "0" stored in the memory cell 34.
In this embodiment, the transistor 34 and the transistors 44a-44c are arranged to form a memory cell array similar to FIG. 3 except that the word lines WLl-WL.sub.n in the reference part 6 are disconnected from the word lines in the memory part 4 and connected to the voltage source V.sub.DD at the terminal 48. As other construction and operation are identical to those of FIG. 3, further description with reference to the drawing similar to FIG. 3 will be omitted.
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