Source: http://www.google.com/patents/US7487276?dq=No.+6,411,949
Timestamp: 2016-06-28 22:23:01
Document Index: 770955003

Matched Legal Cases: ['art 40', 'art 40', 'art 40', 'art 60', 'art 60', 'art 60']

Patent US7487276 - Bus arbitration system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically...http://www.google.com/patents/US7487276?utm_source=gb-gplus-sharePatent US7487276 - Bus arbitration systemAdvanced Patent SearchPublication numberUS7487276 B2Publication typeGrantApplication numberUS 12/048,772Publication dateFeb 3, 2009Filing dateMar 14, 2008Priority dateDec 23, 2004Fee statusLapsedAlso published asUS7366811, US20060143349, US20080162771Publication number048772, 12048772, US 7487276 B2, US 7487276B2, US-B2-7487276, US7487276 B2, US7487276B2InventorsRichard NicholasOriginal AssigneeInternational Business Machines CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (11), Referenced by (3), Classifications (5), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetBus arbitration system
US 7487276 B2Abstract
A circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the sequence for a second group of devices, granting access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.
1. A circuit arrangement comprising arbitration logic configured to grant access to a plurality of devices operatively connected to a bus by granting bus access to a first group of the plurality of devices according to a predetermined arbitration scheme for determining in which order the devices of the first plurality receive access to the bus relative to one another, automatically altering the predetermined arbitration scheme, and granting access to the bus for a second group of the plurality of devices according to the altered arbitration scheme, wherein the arbitration logic is configured to grant access to the bus for the first group of the plurality of devices by grouping requests associated with the first group of the plurality of devices to create a first pool and sequencing through each request of the first pool according to the predetermined arbitration scheme until access to the bus has been granted for each request of the first pool, and wherein the arbitration logic is configured to grant access to the bus for the second group of the plurality of devices by grouping requests associated with the second group of the plurality of devices and received subsequent to the requests of the first pool to create a second pool and sequencing through each request of the second pool according to the altered arbitration scheme until access to the bus has been granted for each request of the second pool.
2. The circuit arrangement of claim 1, further comprising an indicator used to determine the altering of the predetermined arbitration scheme, wherein the arbitration logic is further configured to read the indicator.
3. The circuit arrangement of claim 2, wherein the arbitration logic is further configured to adjust the indicator.
4. The circuit arrangement of claim 3, wherein the arbitration logic is further configured to adjust the indicator in response to an arbitration performed by the circuit arrangement.
5. The circuit arrangement of claim 3, further comprising a counter, wherein the arbitration logic is further configured to increment the counter in response to at least one of an arbitration, a number of grants and an expiration of a time period.
6. The circuit arrangement of claim 5, wherein the arbitration logic is further configured to compare a predetermined value to the counter to determine if the indicator should be adjusted.
7. The circuit arrangement of claim 3, wherein the arbitration logic is further configured to reset the counter in response to adjusting the indicator.
8. The circuit arrangement of claim 1, wherein the plurality of devices includes a host bridge configured to access to the bus on behalf of at least one other of the plurality of devices.
a plurality of devices operatively connected to the bus; and
the circuit arrangement of claim 1.
This application is a continuation of U.S. patent application Ser. No. 11/021,534, filed on Dec. 23, 2004 by Richard Nicholas (ROC920040096US1), the entire disclosure of which is incorporated by reference herein.
The present invention relates generally to a method and system for data processing, and more particularly, to a method and system for bus arbitration
Computer systems rely on the cooperative interaction of numerous, specialized devices configured to perform a variety of tasks. Typically, the devices interact by reading or writing data to other components in the system. The successful exchange of data between these components is consequently vital to the operation of computer systems. Such devices commonly include a processor, memory and certain peripheral devices, such as mass storage devices, network adapters, display adapters, audio adapters and workstation controllers. These devices are typically coupled together using a network of address, data and control lines, commonly referred to as a bus.
One common type of bus is known as the Peripheral Component Interconnect (PCI) bus. Under the PCI bus standard, peripheral components can connect to a PCI bus without the need for glue logic. Thus, PCI provides a bus standard on which high performance peripheral devices, such as graphics devices, control panels, tape drives, as well as optical and hard disk drives, can be coupled to a processor. Bus standards more particularly refer to an independent set of protocols, or rules, to conduct data transfers between the various devices attached to it. Each of these protocols is designed into a bus directly and is commonly referred to as the architecture of the bus.
In a data transfer between different bus architectures, data being transferred from the first bus architecture may not be in a form that is usable or intelligible by the receiving second bus architecture. Accordingly, mechanisms have developed for translating data that is required to be transferred from one bus architecture to another. This translation mechanism is normally contained in a hardware device in the form of a bus-to-bus bridge, or interface, through which the two different types of buses are connected.
Various bus-to-bus bridges have consequently been designed to match the communication protocol of one bus with that of another. These bridges thus permit system wide communications between devices on different buses. For example, a bus-to-bus bridge connecting between a system bus and a PCI local bus is called a PCI host bridge. The PCI host bridge contains all the logic and hardware for translating data communications between the system bus and the PCI local bus, and ensures that data is transferred between these two buses intelligibly.
A variant of PCI, PCIX, includes a host bridge through which the respective devices may gain access to the bus. The host bridge performs write back splits, or communicates with the system bus on behalf of requesting devices. For instance, an Ethernet device may send a data request to a host bridge, which in turn, sends a request for the data to a bus coupled to a memory device storing the data. The bridge then receives the data from the memory device and sends it back to the Ethernet device. Each bridge usually has posting buffers for temporary buffering of bus transactions, as these transactions flow through the bridge in both directions.
Multiple devices connected to the different buses must not be allowed access via the host bridge to the processor or a local bus at the same time. Such simultaneous access would confuse computer systems, producing unuseable results. Such confusion is avoided by using a bus arbiter. A bus arbiter controls device access to the bus. Processes used to decide when a device may next access the bus via the host bridge is appropriately called bus arbitration. In a bus arbitration scheme, a device (that may include the host bridge) wanting to use the bus signals a bus request. In response, the arbiter sends a grant signal to the device. After the grant is received, the device may send a request to the host bridge, prompting the host bridge to access the bus on the other side of the bridge on behalf of the device, i.e., to read or write data according to the request. The arbiter can then grant to another device the privilege of having cycles run by the host bridge on its behalf.
Arbitration schemes are usually designed to balance two factors when determining a sequence for granting the bus via the host bridge. First, each device request typically has a bus priority, and the highest priority devices are serviced first. Second, to help avoid instances where low priority devices are locked out, most I/O buses such as PCI also require the arbiter to implement some kind of fairness protocol. The intent of a fairness protocol is to assure that all devices receive a turn on the bus. For instance, one conventional fairness protocol is a round robin scheme. Under a round robin fairness protocol, a device that has just completed a bus operation is not granted access to the bus for a second operation until all other requesting devices have first been granted access to the bus.
Even though a bus may provide a fairness protocol in the arbiter(s) that control access to the bus, acceptable access to the bus can be effectively denied, or locked, to devices. If several or all of the devices are competing for a single resource, such as system memory, and one of the devices is monopolizing the memory, then another device needing access to the memory may be unable to access the monopolized resource. This lockout may occur even though the arbiter fairly grants bus access to all requesting devices. The locked out device is thus unable to capitalize on its bus access allowed by the arbiter, and consequently receives a retry signal, relegating the device to attempting the transaction at some later time.
More particularly, many buses provide a performance feature usually referred to as retry capability that allows a device to disconnect from the bus/host bridge if it is not able to handle the request at that time. If a target device is not able to handle a request when it occurs, that target can issue a retry, which indicates to the device that issued the request on the bus to try again later.
Lockout generally involves interaction between the set of buffers in a bridge, the arbiter, and the bus traffic by devices on the bus. For example, an arbiter may have a round-robin fairness protocol for five devices (Device A, Device B, Device C, Device D and a host bridge). The host bridge is assigned the highest priority (priority 0), Device A is assigned the next highest priority (priority 1), Device B is assigned the next highest priority (priority 2), Device C is assigned the next highest priority (priority 3), and Device D is assigned the next highest priority (priority 4). If all devices ask for the bus at the same time, the fairness protocol will assure that each device gets a chance to try to utilize the bus. The arbitration priority, in this example, simply determines the order in which the devices get a turn to try to utilize the bus.
When all devices request use of the bus, the host bridge is granted first access, then Devices A to D in sequence. In one scenario under this scheme, Device A may be running a large amount of reads to system memory on the other side of the host bridge. Device A will consequently re-request the bus for a new transaction as soon as it completes the current transaction. As such, the host bridge contains four read buffers that are all currently allocated to Device A reads. Device B may subsequently want to do some reads. When Device B gets the bus, however, Device B gets a retry because the bridge's buffers are full with Device A reads. That is, while the host bridge is acquiring the read data for its four buffers, all other devices that run reads to the host bridge will receive retries. Eventually, the bridge empties out one of its buffers onto the bus, completing one of the read transactions to Device A. The host bridge now has one of its four buffers free, but because in the current scheme Device A will always get the bus after the host bridge gets the bus because Device A is always requesting the bus. Device A will consequently get the bus next and queue another read to the host bridge, using the one free buffer slot. Next, the arbiter will grant the bus to Device B, but again, there will be no buffers free to usem and Device B will receive a retry.
Because the host bridge must get a turn on the bus in order to free up a buffer, and because Device A always gets to run right after the host bridge, it is clear that Device A will continue to be able to claim every buffer that frees up, locking out Device B for as long as Device A wants to do reads. A lockout can occur such that each time a specific device gets a turn on the bus and is turned away with a retry (or equivalent, depending on the bus type) because other devices keep filling up the bridge buffers, i.e., saturating the host bridge. A large number of retries could result in significant performance losses or even errors for the device that is being locked out. For example, the device being locked out may be an ethernet controller that has a requirement to deliver the next packet within a certain period of time, or else the packet will time out and be considered lost. The ethernet controller cannot deliver the packet in time because it is being locked out from reading the packet's data from system memory.
The arbiter does not know or care that there are two devices competing for a common resource. The arbiter does not know the destination of the various transactions and how they interrelate. The arbiter is unaware of which devices are retried. As far as the arbiter is concerned, the transaction was successful in that the device was granted access to run on the bus, even though the device was unable to receive the requested data. The arbiter has fulfilled its programmed fairness requirement.
Therefore, what is needed is an improved system for arbitrating device access to a desired bus.
The present invention provides a circuit arrangement, method and program product configured to improve bus arbitration by, in one aspect, automatically altering the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, features of the present invention include an arbiter configured to grant access to a first group of devices according to a predetermined sequence. The arbiter may automatically alter the sequence for a second group of devices, then grant access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.
Moreover, the variance, or altering of the sequences, may occur after differing periods of time, further minimizing conventional arbitration problems. To achieve this benefit, aspects of the invention may include an indicator, such as a pointer used to determine when the altering of the sequence should occur. The indicator may be adjusted from time to time in response to an arbitration and/or the expiration of a period of time. As such, the arbiter may increment and otherwise maintain a counter to keep track of when the indicator should be adjusted. The arbiter will typically grant access to each request in a group according to the appropriate sequence before moving on to a next group.
Another aspect of the invention may include a host bridge configured to access the bus on behalf of another requesting device. Features of the invention thus may apply particularly well in the context of multiple devices attempting to share a common resource, where the shared resource includes a device for retrieving data on behalf the multiple devices.
FIG. 1 is a block diagram of a computer system having a local bus architecture that is configured to automatically alter the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence.
FIG. 2 is a flowchart having steps executable by the arbiter of the system of FIG. 1 for managing device access to the bus.
FIG. 3 is a flowchart having a sequence of steps executable by the arbiter of the system of FIG. 1 for determining the sequence used to grant access to the bus for a plurality of requesting devices.
Features of the present invention include a circuit arrangement, program product and method for arbitrating device access to a bus. Aspects of the invention allow the order in which an arbiter sequences through one or more pools to be automatically varied. Moreover, the variance may occur after differing periods of time, further diminishing the likelihood of lockout. Further aspects of the invention include an arbiter that starts an arbitration period, or tenure, on a clock pulse boundary where one or more requests are pending. Requests are captured in a pool of current requests during the tenure. These requests are serviced one at a time until the pool of current requests is empty. At this point, the arbitration tenure is over, and if any new requests are pending, they are captured into a second pool of current requests, and a new arbitration tenure begins.
During an arbitration tenure, any requests that arrive after the tenure began are latched, or stored as pending, but are not allowed into the pool of current requests until the next arbitration tenure begins. For instance, if four request inputs are received on a first clock pulse, all four request inputs are put into a current pool. On a second clock pulse, three more requests may be received. These three new requests may be latched as pending, but do not enter the pool. The arbiter may give a grant to each of the four requesting devices in the current pool, and consequently removes each request from the pool of current requests. When the last request is removed from the pool of current requests, i.e., the pool is empty, a new arbitration tenure begins, bringing the previously latched three requests into a new pool of current requests. These three requests are then serviced one by one in the current arbitration tenure while subsequent requests become pending and queued up for the next arbitration tenure.
An aspect of the invention mitigates lockout by varying the order that requests are serviced in the pool of current requests. For instance, the arbiter may switch the order in which requests are addressed, e.g., from ascending order to descending order in different arbitration tenures. For example, when a pointer is in the up direction, pending requests may be serviced in ascending order. When the pointer is alternatively in a down direction, pending requests are serviced in descending order. The direction of the pointer may be changed periodically or non-periodically, and in alternating intervals. For instance, the direction of the pointer may change every fourth arbitration tenure for a period, then change to every second arbitration tenure for another period, after which the period may change again. The variance provided by this feature further mitigates instances of lockout. One skilled in the art will appreciate that multiple other algorithms may be employed to change the direction of the pointer. Such a pointer change will further not affect the performance or fairness of the arbiter because neither factor is affected by the order in which requests are serviced once they are inside the pool of current requests. Namely, by varying the pointer as discussed herein, instead of by a fixed amount, there is no chance of the pointer always being in the same direction for a device.
Referring now to the drawings and in particular to FIG. 1, there is depicted a block diagram of an exemplary computer system 10 having a local bus consistent with the principles of the present invention. As shown, a processor 12, a cache memory 13, a memory controller 14, a Dynamic Random Access Memory (DRAM) 15 and the arbiter 30 are connected to a system bus 28 of the computer system 10. Processor 12, cache memory 13, memory controller 14 and DRAM 15 are also coupled to a PCI local bus 20 of computer system 10 through a host bridge 11. Host bridge 11 provides a low latency path through which processor 12 may access devices mapped anywhere within bus memory and/or I/O address spaces. Host bridge 11 also provides a high bandwidth path for allowing devices to access DRAM 15. Host bridge 11 may include various functions such as data buffering and posting.
Also attaching to local bus 20 may be other devices such as a local-area network (LAN) interface 16 and an expansion bus interface 27. LAN interface 16 is for connecting computer system 10 to a LAN, such as Ethernet or Token-Ring. The configuration may also support separate local buses under separate host bridges. For example, PCI-to-PCI bridge 18 allows local bus 20 to connect to another local bus (not shown), which in turn, may connect to a variety of other devices (also not shown).
Expansion bus interface 27 may couple any other non-PCI peripheral buses, such as ISA bus, EISA bus, and/or MicroChannel Architecture (MC-A) bus to local bus 20. Typically, various non-PCI peripheral devices for performing certain basic I/O functions are attached to one of the peripheral buses. As shown in FIG. 1, local bus 20 may connect via add-in board connectors to various devices that include an audio adapter board 22, a motion video adapter board 23 and a graphics adapter board 24.
Bus bridges, such as host bridge 11 and PCI-to-PCI bridge 18, are typically coupled between a primary bus and a secondary bus. A bus bridge enables an access request that initiates on the primary bus to have a destination on the secondary bus, and enables an access request that initiates on the secondary bus to have a destination on the primary bus. For example, after receiving an access request from system bus 28, host bridge 11 will initiate an access request on local bus 20 to communicate with one or more of devices 16, 18, 22, 23, 24, or 27.
Device access to each other may be managed by the arbiter 30. In one respect, the arbiter 30 mitigates the chances of lockout by automatically varying the sequence in which device requests in a pool 34 are serviced. To this end, the arbiter 30 may include a pointer 32 that indicates the order in which the requests are to be addressed. A counter 31 and a preset variable, “x,” may further be used to vary the sequence of arbitration by automatically switching the direction of the pointer 32 after a period of time or number of cycles. Where desired, even that period may be varied to further promote successful access, e.g., successful read and write operations in the absence of prolonged lockouts. After each request in the current pool 34 has been granted access to local bus 20, the arbiter 30 may create a new pool comprised of pending requests 35 received and stored while the first tenure was completed.
One skilled in the art will appreciate that other devices included in system 10 may comprise any of a number of different peripheral devices including video accelerators, audio cards, hard or floppy disk drives, Small Computer Systems Interface (SCSI) adaptors and the like. Moreover, the devices shown in FIG. 1 comprise both initiator and target functions, however, one skilled in the art will appreciate that distinct target and initiator devices may be substituted for the single devices shown in FIG. 1. Furthermore, while each component in FIG. 1 is shown as being a separate device, one skilled in the art will appreciate that many such components may be included on one or more microchips per application specifications.
System 10, or any subset of components therein, may also be referred to hereinafter as an “apparatus”. It should be recognized that the term “apparatus” may be considered to incorporate various data processing systems such as computers and other electronic devices, as well as various components within such systems, including individual integrated circuit devices or combinations thereof. Moreover, within an apparatus may be incorporated one or more logic circuits that circuit arrangements, typically implemented on one or more integrated circuit devices, and optionally including additional discrete components interfaced therewith.
It should also be recognized that circuit arrangements are typically designed and fabricated at least in part using one or more computer data files, referred to herein as hardware definition programs, that define the layout of the circuit arrangements on integrated circuit devices. The programs are typically generated in a known manner by a design tool and are subsequently used during manufacturing to create the layout masks that define the circuit arrangements applied to a semiconductor wafer. Typically, the programs are provided in a predefined format using a hardware definition language (HDL). Thus, while the invention has and hereinafter will be described in the context of circuit arrangements implemented in fully functioning integrated circuit devices, those skilled in the art will appreciate that circuit arrangements consistent with the invention are capable of being distributed as program products in a variety of forms, and that the invention applies equally regardless of the particular type of computer readable signal bearing media used to actually carry out the distribution. Examples of computer readable signal bearing media include but are not limited to recordable type media such as volatile and non-volatile memory devices, floppy disks, hard disk drives, CD-ROM's, and DVD's, among others, and transmission type media such as digital and analog communications links.
Those skilled in the art will thus recognize that the exemplary environment illustrated in FIG. 1 is not intended to limit the present invention. Indeed, those skilled in the art will recognize that other alternative hardware and/or software environments may be used without departing from the scope of the invention.
FIG. 2 is a flowchart 40 having steps executable by the arbiter 30 of the system 10 of FIG. 1 for managing device access to a bus 28. Features of the flowchart 40 allow the arbiter 30 to automatically vary the order in which requests are sequenced to diminish the likelihood of lockout. More particularly, the arbiter 30 receives at block 42 requests from devices 11, 16, 18, 22, 23, 24, and/or 27 to access to the bus 28. For instance, an Ethernet device may require and request data stored in a DRAM 115. The arbiter 30 may limit, or lock, at block 44 of FIG. 2 the pool 34 of requests to those current request(s) received at block 42. The current pool comprises an arbiter tenure. Requests received while current requests remain in the pool 34 will be latched, or temporarily stored. While the timing of the steps of the flowchart 40 may vary as between different applications, the requests of block 42 may be received within a single clock pulse or on different clock pulses.
At block 46 of FIG. 2, the arbiter 30 grants access to the bus for each request according to the sequence dictated by the pointer order. For instance, a request corresponding to a first device 16 will be received by the host bridge 11. The host bridge 11 may access the bus 28 and perform a read or write function on behalf of the requesting device 16. The host bridge 11 may subsequently return data from the target memory 15 to the requesting device 16. The request corresponding to the device 16 will then be removed from the pool 34 at block 48. If any requests remain in the pool at block 50, then the arbiter 30 may grant access to the bus 28 for the next device having a request in the pool 34 according to the scheme dictated by the pointer 32. For instance, the pointer 32 may dictate that the arbiter 30 proceed in descending order from the request of first device 16 in the pool list. One skilled in the art will appreciate that the requesting device may comprise the host bridge 11, itself.
FIG. 3 is a flowchart 60 having a sequence of steps executable by the arbiter 30 of FIG. 1 for determining the sequence used to grant access to a bus for a plurality of requesting devices. The steps of the flowchart 60 may presume for exemplary purposes that the pointer 32 is initially preset as “up,” the counter 31 is “0,” and a variable “x” 33 is set to 4. One skilled in the art will appreciate, however, that other settings may alternatively be used per application specifications. Features of the flowchart 60 allow the order in which the arbiter 30 sequences through one or more pools 34 to be automatically varied. Moreover, the variance may occur after differing periods of time, further diminishing the likelihood of lockout.
Turning more particularly to block 62 of FIG. 3, the arbiter 30 may determine if a device 18 has been granted access to the bus 28. If so, then the arbiter 30 may increment at block 64 the counter 31. As such, the counter 31 may have a value of “1.”
The arbiter 30 may determine at block 66 if the value of the counter 31 equals the value of x, i.e., “4.” If not, then the arbiter 30 may continue to grant bus access and increment the counter 31 at block 64 until the counter 31 increments to a value equal to “x” at block 66. This feature allows the arbiter 30 to continue to sequence through requests in one or more tenures for x times.
Where this counter condition is finally satisfied at block 66, the arbiter 30 may determine at block 68 the direction of the pointer 32. For instance, the arbiter 30 may determine at block 68 if the pointer 32 is down. If not at block 68, then the arbiter 30 may flip the orientation of the pointer 32, i.e, down, at block 70. This change of the pointer's direction will cause the arbiter 30 to sequence through the pool 34 in the opposite direction. By varying the order in which the requests are granted access to the bus via the host bridge 11, the chances of a lockout are diminished. The arbiter 30 may furthermore reset the counter 31 to “0” at block 72. As such, the pointer 32 and associated pointer/sequence direction will be altered on a subsequent cycle beginning back at block 62.
Should the arbiter 30 alternatively determine at block 68 of FIG. 3 that the pointer 32 is down, then the arbiter may set the pointer 32 to be up at block 74. This change of the pointer's direction will cause the arbiter 30 to subsequently sequence through the pool 34 in the opposite direction. The arbiter 30 may additionally reset the counter 31 to 0 at block 76.
The arbiter 30 may determine at block 78 if the value of x 33 is 4. If not, then the arbiter 30 may change the value of x to 4 at block 80. If the stored value of x 33 is alternatively equal to 4 at block 78, then the arbiter 30 may set the value of x 33 to a new value of 2 at block 82. This variation may further mitigate the occurrences of lockout. One skilled in the art will appreciate that the exemplary values of x may vary dramatically in different embodiments consistent with the invention.
In use, a first device has saturated a resource inside the host bridge, but a second device wants to run a cycle using the bus. The host bridge is ready to complete a transaction for the first device so that it can attend to the others in the pool of requests. For purposes of the example, the pointer is initially in the up direction. If the host bridge runs its transaction, then the first requesting device runs and queues another transaction, and the second device would be retried because the resource was being used. This lockout, as described earlier, will continue to happen as long as the pointer remains in the up direction. But under the scheme afforded by the present invention, the pointer changes direction and will soon be in the down direction. If the pointer is in the down direction after the host bridge runs a transaction, freeing up one of its buffers, then it is the second device, not the first device, which will be granted the bus next and will be able to queue its transaction to the free buffer in the host bridge. As such, no lockout occurs. According to an embodiment consistent with the invention, the duration of the pointer values are varied in addition to the direction of the pointer in order to eliminate the possibility that even though the pointer direction is changing, there could still be some repeatable pattern that the system could fall into whereby the pointer is always in the same direction at just the wrong instant to cause a lockout. Varying the pointer duration slides the window of the pointer value with respect to the fixed transactions, avoiding any repeatable relationship between the two.
While the present invention has been illustrated by a description of various embodiments and while these embodiments have been described in considerable detail, it is not the intention of the applicants to restrict, or in any way limit, the scope of the appended claims to such detail. For instance, while embodiments where discussed in the context of PCI and PCIX, aspects of the invention may have equal application in the context of Rapid I/O, and PCI Express, among others. As such, additional advantages and modifications will readily appear to those skilled in the art.
The invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative example shown and described. Furthermore, it will be appreciated that various additional modifications may be made to the illustrated embodiments consistent with the invention. It will also be appreciated that implementation of the functionality described above, and in particular, of the specific sequences of operations illustrated in FIGS. 2 and 3, within logic circuitry disposed on a memory device, a memory controller, and/or other control logic in a memory architecture, would be well within the abilities of one of ordinary skill in the art having the benefit of the instant disclosure. Accordingly, departures may be made from such details without departing from the spirit or scope of applicant's general inventive concept.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5956493Mar 8, 1996Sep 21, 1999Advanced Micro Devices, Inc.Bus arbiter including programmable request latency counters for varying arbitration priorityUS6092137Nov 26, 1997Jul 18, 2000Industrial Technology Research InstituteFair data bus arbitration system which assigns adjustable priority values to competing sourcesUS6178475Dec 19, 1994Jan 23, 2001Advanced Micro Devices Inc.Multimedia system employing timers to properly allocate bus accessUS6718422Jul 29, 1999Apr 6, 2004International Business Machines CorporationEnhanced bus arbiter utilizing variable priority and fairnessUS7062582Mar 14, 2003Jun 13, 2006Marvell International Ltd.Method and apparatus for bus arbitration dynamic priority based on waiting periodUS7093045Feb 5, 2002Aug 15, 2006Ricoh Company, Ltd.Method and apparatus for bus arbitration capable of effectively altering a priority orderUS7107376Jan 26, 2004Sep 12, 2006International Business Machines Corp.Systems and methods for bandwidth shapingUS7120714May 27, 2003Oct 10, 2006Intel CorporationHigh-speed starvation-free arbiter system, rotating-priority arbiter, and two stage arbitration methodUS20030221033May 19, 2003Nov 27, 2003Samsung Electronics Co., Ltd.Bus arbiter for integrated circuit systemsUS20040225767Feb 20, 2004Nov 11, 2004Chih-Ming TsaiSystem bus controller and the method thereofUS20040236889Jan 7, 2004Nov 25, 2004Samsung Electronics Co., Ltd.Bus arbiter and bus arbitrating methodReferenced byCiting PatentFiling datePublication dateApplicantTitleUS9208002 *Jan 6, 2012Dec 8, 2015International Business Machines CorporationEqualizing bandwidth for multiple requesters using a shared memory systemUS20110179212 *Jul 21, 2011Charles Andrew HartmanBus arbitration for sideband signalsUS20130179645 *Jan 6, 2012Jul 11, 2013International Business Machines CorporationEqualizing bandwidth for multiple requesters using a shared memory system* Cited by examinerClassifications U.S. Classification710/118, 710/113International ClassificationG06F13/362Cooperative ClassificationG06F13/362European ClassificationG06F13/362Legal EventsDateCodeEventDescriptionSep 17, 2012REMIMaintenance fee reminder mailedFeb 3, 2013LAPSLapse for failure to pay maintenance feesMar 26, 2013FPExpired due to failure to pay maintenance feeEffective date: 20130203RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services