Source: http://www.google.com/patents/US6147511?dq=7,362,867
Timestamp: 2014-09-30 15:56:20
Document Index: 136771189

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US6147511 - Overvoltage-tolerant interface for integrated circuits - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an "overvoltage condition. " For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output...http://www.google.com/patents/US6147511?utm_source=gb-gplus-sharePatent US6147511 - Overvoltage-tolerant interface for integrated circuitsAdvanced Patent SearchPublication numberUS6147511 APublication typeGrantApplication numberUS 08/863,886Publication dateNov 14, 2000Filing dateMay 27, 1997Priority dateMay 28, 1996Fee statusPaidAlso published asUS6118302, US6252422, US6342794, US6344758, US6433585, US6563343, US6583646, US6724222, US20030117174Publication number08863886, 863886, US 6147511 A, US 6147511A, US-A-6147511, US6147511 A, US6147511AInventorsRakesh H. Patel, John E. Turner, Wilson WongOriginal AssigneeAltera CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (58), Non-Patent Citations (46), Referenced by (38), Classifications (17), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetOvervoltage-tolerant interface for integrated circuitsUS 6147511 AAbstract An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an "overvoltage condition. " For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.
What is claimed is: 1. A circuit to implement an overvoltage-tolerant integrated circuit comprising:a pull-up device coupled between a first supply voltage and an I/O pad; and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; a first clamping device coupled between the first supply voltage and a first node, not directly connected to the voltage bias node; a second clamping device coupled between the I/O pad and the first node; and a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state. 2. The circuit of claim 1 wherein a second body electrode of the first bias device and a third body electrode of the second bias device are coupled to the voltage bias node.
3. The circuit of claim 1 wherein the body bias generator further comprises:a voltage clamp circuit coupled to clamp the voltage bias node to a voltage at or above about a level of the first supply voltage. 4. The circuit of claim 1 further comprising:a predriver to drive the pull-up device; and an isolation device between the predriver and the control electrode of the pull-up device. 5. The circuit of claim 1 further comprising:a resistive device coupled between the I/O pad and the first bias device and between the I/O pad and the second bias device. 6. The circuit of claim 1 further comprising:an input buffer comprising a thick oxide transistor with a control electrode coupled to receive a signal at the I/O pad. 7. The circuit of claim 1 wherein the first bias device and second bias device are thick oxide transistors.
8. The circuit of claim 1 wherein the voltage bias node is coupled to body electrodes of the first bias device, second bias device, third bias device, first clamping device, and second clamping device.
9. An integrated circuit comprising:a pull-up device coupled between a first supply voltage and an I/O pad; and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; a first clamping device coupled between the first supply voltage and a first node; a second clamping device coupled between the I/O pad and the first node; a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state; and a voltage clamp device coupled to clamp the voltage bias node to about a voltage level at the I/O pad. 10. A circuit to implement an overvoltage-tolerant integrated circuit comprising:a pull-up device coupled between a first supply voltage and an I/O pad; and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; and; a third bias device to couple the voltage bias node to a control electrode of the pull-up device whenever the pull-up device is in a nonconducting state. 11. The circuit of claim 10 wherein a second body electrode of the first bias device and a third body electrode of the second bias device are coupled to the voltage bias node.
12. The circuit of claim 10 wherein the body bias generator further comprises:a voltage clamp circuit coupled to clamp the voltage bias node to a voltage at or above about a level of the first supply voltage. 13. The circuit of claim 10 wherein the body bias generator further comprises:a voltage clamp device coupled to clamp the voltage bias node to about a voltage level at the I/O pad. 14. The circuit of claim 10 further comprising:a predriver to drive the pull-up device; and an isolation device between the predriver and the control electrode of the pull-up device. 15. The circuit of claim 10 further comprising:a resistive device coupled between the I/O pad and the first bias device and between the I/O pad and the second bias device. 16. The circuit of claim 10 further comprising:an input buffer comprising a thick oxide transistor with a control electrode coupled to receive a signal at the I/O pad. 17. The circuit of claim 14 wherein the isolation device is a pass transistor having a control electrode coupled to the first supply voltage.
18. The circuit of claim 10 wherein the first bias device and second bias device are thick oxide transistors.
19. The circuit of claim 10 wherein the voltage bias node is coupled to body electrodes of the first bias device, second bias device, and third bias device.
20. The circuit of claim 10 further comprising:a first pass device coupled between the I/O pad and the control electrode of the pull-up device, wherein a control electrode of the first pass device is coupled to the first supply voltage. 21. The circuit of claim 20 wherein a body electrode of the first pass device is coupled to the voltage bias node.
22. The circuit of claim 20 further comprising:a second pass device coupled between a predriver output node and the control electrode of the pull-up device, wherein a control electrode of the second pass device is coupled to the I/O pad. 23. The circuit of claim 20 wherein a body electrode of the second pass device is coupled to the voltage bias node.
24. An intergrated circuit comprising:a pull-up device coupled between a first supply voltage and an I/O pad; a predriver to drive the pull-up device; and an isolation device between the predriver and the control electrode of the pull-up device, wherein the isolation device is a pass transistor having a control electrode coupled to the first supply voltage; and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; a first clamping device coupled between the first supply voltage and a first node; a second clamping device coupled between the I/O pad and the first node; and a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state. 25. An integrated circuit comprising:a pull-up device coupled between a first supply voltage and an I/O pad; a first pass device coupled between the I/O pad and the control electrode of the pull-up device, wherein a control electrode of the first pass device is coupled to the first supply voltage; and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; a first clamping device coupled between the first supply voltage and a first node; a second clamping device coupled between the I/O pad and the first node; and a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state. 26. The circuit of claim 25 wherein a body electrode of the first pass device is coupled to the voltage bias node.
27. The circuit of claim 25 further comprising:a second pass device coupled between a predriver output node and the control electrode of the pull-up device, wherein a control electrode of the second pass device is coupled to the I/O pad. 28. The circuit of claim 25 wherein a body electrode of the second pass device is coupled to the voltage bias node.
29. A circuit to implement an overvoltage-tolerant integrated circuit comprising:a pull-up device coupled between a first supply voltage and an I/O pad; a predriver to drive the pull-up device; and an isolation device between the predriver and the control electrode of the pull-up device, wherein the isolation device is a pass transistor having a control electrode coupled to the first supply voltage, and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; and a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage, wherein the first bias device and the second bias device have a first gate oxide thickness that is thicker than a second gate oxide thickness of transistors used to implement the predriver. 30. The circuit of claim 29 wherein the isolation device has the first gate oxide thickness.
31. The circuit of claim 29 wherein a second body electrode of the first bias device and a third body electrode of the second bias device are coupled to the voltage bias node.
32. The circuit of claim 29 wherein the body bias generator further comprises:a voltage clamp circuit coupled to clamp the voltage bias node to a voltage at or above about a level of the first supply voltage. 33. The circuit of claim 32 wherein the voltage clamp circuit has the first gate oxide thickness.
34. The circuit of claim 29 wherein the body bias generator further comprises:a voltage clamp device coupled to clamp the voltage bias node to about a voltage level at the I/O pad. 35. The circuit of claim 34 wherein the voltage clamp device has the first gate oxide thickness.
36. The circuit of claim 29 wherein the body bias generator further comprises:a third bias device to couple the voltage bias node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state. 37. The circuit of claim 36 wherein the third bias device has the first gate oxide thickness.
38. The circuit of claim 29 further comprising:a resistive device coupled between the I/O pad and the first bias device and between the I/O pad and the second bias device. 39. The circuit of claim 29 further comprising:an input buffer comprising a transistor with the first oxide thickness and a control electrode coupled to receive a signal at the I/O pad. 40. The circuit of claim 29 wherein the body bias generator further comprises:a first clamping device coupled between the first voltage source and a first node; a second clamping device coupled between the I/O pad and the first node; and a third bias device to couple the first node to the control electrode of the pull-up device when the pull-up device is in a nonconducting state. 41. The circuit of claim 40 wherein the first clamping device and third bias device have the first gate oxide thickness.
42. The circuit of claim 41 wherein the voltage bias node is coupled to body electrodes of the first bias device, second bias device, third bias device, first clamping device, and second clamping device.
43. The circuit of claim 29 wherein the pull-up device has the first gate oxide thickness.
44. The circuit of claim 29 further comprising:a first pass device coupled between the I/O pad and the control electrode of the pull-up device, wherein a control electrode of the first pass device is coupled to the first supply voltage. 45. The circuit of claim 44 wherein a body electrode of the first pass device is coupled to the voltage bias node.
46. The circuit of claim 44 further comprising:a second pass device coupled between a predriver output node and the control electrode of the pull-up device, wherein a control electrode of the second pass device is coupled to the I/O pad. 47. The circuit of claim 44 wherein a body electrode of the second pass device is coupled to the voltage bias node.
48. A circuit to implement an overvoltage-tolerant integrated circuit comprising:a pull-up device coupled between a first supply voltage and an I/O pad; a predriver to drive a control electrode of the pull-up device with a pull-up signal; and a body bias generator, having a voltage bias node coupled to a first body electrode of the pull-up device, comprising:a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; and a third bias device, coupled between the voltage bias node and the control electrode of the pull-up device, wherein a control electrode of the third bias device is coupled to an inverted version of the pull-up signal. 49. The circuit of claim 48 further comprising:an isolation device coupled between the predriver and the control electrode of the pull-up device. 50. The circuit of claim 48 wherein the body bias generator further comprises:a voltage clamp circuit coupled to clamp the voltage bias node to a voltage at or above about a level of the first supply voltage. 51. The circuit of claim 48 wherein the body bias generator further comprises:a voltage clamp device coupled to clamp the voltage bias node to about a voltage level at the I/O pad. 52. The circuit of claim 48 further comprising:a resistive device coupled between the I/O pad and the first bias device and between the I/O pad and the second bias device. 53. The circuit of claim 48 further comprising:an input buffer comprising a thick oxide transistor with a control electrode coupled to receive a signal at the I/O pad. 54. The circuit of claim 49 wherein the isolation device has a control electrode coupled to the first supply voltage.
55. The circuit of claim 48 wherein the first bias device and second bias device are thick oxide transistors.
56. The circuit of claim 48 wherein the voltage bias node is coupled to body electrodes of the first bias device, second bias device, and third bias device.
57. The circuit of claim 48 further comprising:a first pass device coupled between the I/O pad and the control electrode of the pull-up device, wherein a control electrode of the first pass device is coupled to the first supply voltage. 58. The circuit of claim 57 wherein a body electrode of the first pass device is coupled to the voltage bias node.
59. The circuit of claim 57 further comprising:a second pass device coupled between a predriver output node and the control electrode of the pull-up device, wherein a control electrode of the second pass device is coupled to the I/O pad. 60. The circuit of claim 57 wherein a body electrode of the second pass device is coupled to the voltage bias node.
This application claims the benefit of U.S. Provisional Application No. 60/018,465, filed May 28, 1996, Provisional Application No. 60/018,494, filed May 28, 1996, Provisional Application No. 60/018,510, filed May 28, 1996, Provisional Application No. 60/022,837, filed Jul. 31, 1996, Provisional Application No. 60/031,617, filed Nov. 27, 1996, and Provisional Application No. 60/046,810, filed May 2, 1997, all of which are incorporated herein by reference.
Process scaling is the dominant method of reducing the die cost. The cost is achieved by receiving higher yields associated with smaller die sizes. Presently, power supply voltages are being reduced as the scaling progresses towards _device dimensions that necessitate the reduction of voltage differences across these dimensions.
SUMMARY OF THE INVENTION The present invention is a technique of interfacing an integrated circuit in a mixed-voltage mode environment. In particular, an input/output driver or buffer of the present invention may interface directly with a voltage at a pad which is above the supply voltage for the input/output driver. This may be referred to as an "overvoltage condition." For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver of the present invention will tolerate this voltage level and prevent leakage current paths when used as an input. The present invention may also be used in a scheme where there is separated noisy and quiet supplies. For example, there may be a noisy power supply and quiet power supply. An I/O driver may be coupled to the noisy supply, and the core would be coupled to the quiet supply. This provides some isolation of noise at the I/O driver from coupling to internal circuitry. In an embodiment, a well-bias generator and level corrector are included in the output driver circuitry to prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit.
In a third option (illustrated in FIG. 6), the integrated circuit will tolerate 5-volt input signals. The power supply will be 5 volts. And the output signal will provide 5-volt compatible drive capability. As an example, the voltage level for a logic high at the output will be about 5 volts--VTN or above. Please note, even in this case, the integrated circuit will be manufactured using 3.3-volt technology. As shown in FIG. 6, the power supply is 5 volts. This voltage is converted using on-chip circuitry to a lower voltage of 3.3 volts. This conversion may be performed using a voltage down converter (VDC) 610. The lower voltage is supplied to the circuitry in core 405 and interface 411. Interface 411 is capable of tolerating 5-volt input signals. Further, in interface 411, the core 3.3-volt signals may be converted to 5-volt output signals by circuitry such as level-shifting predrivers. The circuits used to perform the conversion in the interface are connected to the 5-volt supply voltage.
Transistor M9 and M10 are coupled between a node 1015 and the bias output node 1010. A gate of transistor M9 is coupled to supply 817. A gate of transistor M1O is coupled to bias output node 1010.
On the other hand, when PU is high, the output of inverter XINV1 will be low. In this case, transistor MN1 will be on. Transistor M11 will effectively couple bias output node 1010 to the gate of PU. Essentially, the gate of PU will track the voltage at gate bias output node 1010 in order to prevent current path I1 described above.
In the case when pin 820 goes above VCC, but below about VCC-|VTP|, bias output node 1010 will be about VPIN-|VTP|, where VPIN is a voltage level at pin 820. Bias output node 1010 will be held at this level through transistor M10. Transistor M10 acts like a diode, analogous to transistor M8. Similarly, transistor M8 may also be substituted with a diode structure or other device or component as discussed in the case for transistor M8. For example, such a diode is present in the p-n junctions of transistors M9 and M10. Under these conditions, the gate and n-well of pull-up driver 810 will be about VPIN-|VTP|. The I1 and I2 current paths will not be of concern. If |VTP| were slightly greater than the VF of diode 830 (see FIG. 8), then there may be a relatively small current I2. However, I2 would be zero when |VTP | is less than the VF of diode 830.
In the case when pin 820 goes above about VCC-|VTP |, bias output node 1010 will be VPIN. VPIN will be passed through transistor M9. Transistor M9 will be in a conducting state under these conditions. Under these conditions, the gate and n-well of pull-up driver 810 will be the same as VPIN. In this case, current paths I1 and I2 will also not occur.
Another example where the control electrode of pass transistor 920 should be coupled to VCCN is when VCCQ is about 3.3 volts and VCCN is about 2.5 volts. Under those circumstances, allow for ten percent tolerances on the VCCN and VCCQ, VCCQ may be about 3.6 volts and VCCN may be about 2.5 volts. If the control electrode of pass transistor 920 were coupled VCCQ of 3.6 volts, bias output node 1010 may be 2.5 volts, and node PU will be about VCCQ-VTN, which is approximately 2.6 volts. Then, when node 1020 is zero volts, there will be current flow through M11, since this device is on. This current flow will be from PU (at 2.6 volts) to bias output node 1010 (at 2.5 volts) and to the pin 820. To minimize this current, M11 may be made into a weak transistor (e.g., by sizing the device).
When VPIN is above about VCC, the circuitry will drive PU to about VCC-|VTP|. This is analogous to the operation of transistor M10, which was described above. In this case, the I1 current path will also be prevented since PU will be within a |VTP| of VPIN.
In operation, when VPIN is less than about VCC-|VTP|, transistor M14 will not conduct, and decouples pin 820 from PU. Also, when VPIN is less than about VCC-|VTP|, transistor 1227 will be on and allow a full-rail logic high voltage (e.g., 3.3 volts when VCC is 3.3 volts) to pass to PU. These transistors ensure the I1 current path will not be of a concern. These transistors ensure the voltage level at PU will be within about a |VTP| of VPIN, and consequently, there will be no I1 current path.
When VPIN goes above VCC-|VTP|, PU will track VPIN through transistor M14. Transistor M14 and pass transistor 1227 will not conduct. More specifically, the voltage at VPIN will be about VPIN+|VTP|. Under these conditions, the I1 current path will not be a concern since the VPIN will be within about a |VTP| of the voltage at PU.
For example, VCCext may be 5 volts, the voltage down converter 1330 converts this voltage to a VCCint of about 3.3 volts, or possibly even lower. To users interfacing this integrated circuit, the chip would be appear to be a 5-volt compatible chip, while the internal circuitry operates at 3.3 volts. Moreover, in a PLD integrated circuit, for example, core 1310 may have 3.3-volt logic signals which are passed across a global interconnect through one or more LABs to level shifter 1317. Level shifter 1317 converts these logic into 5volt compatible signals that are passed to the outside world.
When input 2321 is a logic high (e.g., about VCCL), first buffer 2322 will output a logic low will be at about VSS at output 2333. Second buffer 2335 will output a logic high of about VCC1. Consequently, VCC1 will be coupled to a control electrode of first pull-up device 2325, which will turn that device off completely.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4090236 *Jun 4, 1976May 16, 1978Motorola, Inc.N-channel field effect transistor integrated circuit microprocessor requiring only one external power supplyUS4317181 *Dec 26, 1979Feb 23, 1982Texas Instruments IncorporatedFour mode microcomputer power save operationUS4361873 *Apr 8, 1981Nov 30, 1982Texas Instruments IncorporatedCalculator with constant memoryUS4503494 *Jun 26, 1980Mar 5, 1985Texas Instruments IncorporatedNon-volatile memory systemUS4609986 *Jun 14, 1984Sep 2, 1986Altera CorporationProgrammable logic array device using EPROM technologyUS4617479 *May 3, 1984Oct 14, 1986Altera CorporationProgrammable logic array device using EPROM technologyUS4677318 *Apr 12, 1985Jun 30, 1987Altera CorporationProgrammable logic storage element for programmable logic devicesUS4713792 *Jun 6, 1985Dec 15, 1987Altera CorporationProgrammable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuitsUS4837460 *Jan 23, 1984Jun 6, 1989Kabushiki Kaisha ToshibaComplementary MOS circuit having decreased parasitic capacitanceUS4871930 *May 5, 1988Oct 3, 1989Altera CorporationProgrammable logic device with array blocks connected via programmable interconnectUS4899067 *Jul 22, 1988Feb 6, 1990Altera CorporationProgrammable logic devices with spare circuits for use in replacing defective circuitsUS4901283 *Nov 2, 1988Feb 13, 1990International Computers LimitedDynamic random-access memory system with power-up and power-down refresh circuitsUS4912342 *Sep 14, 1989Mar 27, 1990Altera CorporationProgrammable logic device with array blocks with programmable clockingUS5004936 *Mar 31, 1989Apr 2, 1991Texas Instruments IncorporatedNon-loading output driver circuitUS5032742 *Jul 28, 1989Jul 16, 1991Dallas Semiconductor CorporationESD circuit for input which exceeds power supplies in normal operationUS5041964 *Sep 28, 1989Aug 20, 1991Grid Systems CorporationLow-power, standby mode computerUS5045772 *Oct 1, 1990Sep 3, 1991Altera CorporationReference voltage generatorUS5066873 *Dec 4, 1989Nov 19, 1991Altera CorporationIntegrated circuits with reduced switching noiseUS5121006 *Apr 22, 1991Jun 9, 1992Altera CorporationRegistered logic macrocell with product term allocation and adjacent product term stealingUS5132555 *Jan 31, 1991Jul 21, 1992Hitachi, Ltd.Semiconductor integrated circuitUS5144167 *May 10, 1991Sep 1, 1992Altera CorporationZero power, high impedance TTL-to-CMOS converterUS5151619 *Oct 11, 1990Sep 29, 1992International Business Machines CorporationCmos off chip driver circuitUS5160855 *Mar 11, 1992Nov 3, 1992Digital Equipment CorporationFloating-well CMOS output driverUS5162680 *Dec 17, 1991Nov 10, 1992Altera CorporationSense amplifier for programmable logic deviceUS5222044 *Feb 13, 1991Jun 22, 1993Nec CorporationDynamic random access memory device equipped with two-way power voltage supplying systemUS5241224 *Apr 25, 1991Aug 31, 1993Altera CorporationHigh-density erasable programmable logic device architecture using multiplexer interconnectionsUS5260610 *Sep 3, 1991Nov 9, 1993Altera CorporationProgrammable logic element interconnections for programmable logic array integrated circuitsUS5260611 *May 8, 1992Nov 9, 1993Altera CorporationProgrammable logic array having local and long distance conductorsUS5272393 *Nov 12, 1991Dec 21, 1993Hitachi, Ltd.Voltage converter of semiconductor deviceUS5274828 *Feb 24, 1992Dec 28, 1993Texas Instruments IncorporatedComputer including an integrated circuit having an on-chip high voltage sourceUS5309399 *Oct 14, 1992May 3, 1994Nec CorporationSemiconductor memoryUS5315172 *Apr 14, 1992May 24, 1994Altera CorporationReduced noise output bufferUS5331219 *Oct 22, 1992Jul 19, 1994Nec CorporationSemiconductor integrated circuit with selective interfacing on different interface levelsUS5336986 *Feb 7, 1992Aug 9, 1994Crosspoint Solutions, Inc.Voltage regulator for field programmable gate arraysUS5350954 *Mar 29, 1993Sep 27, 1994Altera CorporationProgrammable logic array apparatusUS5359243 *Apr 16, 1993Oct 25, 1994Altera CorporationFast TTL to CMOS level converting buffer with low standby powerUS5402375 *Mar 9, 1994Mar 28, 1995Hitachi, LtdVoltage converter arrangement for a semiconductor memoryUS5414312 *Jul 15, 1993May 9, 1995Altera CorporationAdvanced signal driving buffer with directional input transition detectionUS5416661 *Feb 19, 1993May 16, 1995Nec CorporationSemiconductor integrated circuit deviceUS5417476 *Feb 18, 1994May 23, 1995Central Motor Wheel Company LimitedDisk wheel for automobileUS5432467 *Oct 17, 1994Jul 11, 1995Altera CorporationProgrammable logic device with low power voltage level translatorUS5442277 *Feb 15, 1994Aug 15, 1995Mitsubishi Denki Kabushiki KaishaInternal power supply circuit for generating internal power supply potential by lowering external power supply potentialUS5451889 *Mar 14, 1994Sep 19, 1995Motorola, Inc.CMOS output driver which can tolerate an output voltage greater than the supply voltage without latchup or increased leakage currentUS5508653 *Oct 7, 1994Apr 16, 1996Acc Microelectronics CorporationMulti-voltage circuit arrangement and method for accommodating hybrid electronic system requirementsUS5528548 *Feb 7, 1995Jun 18, 1996Hitachi, Ltd.Voltage converter of semiconductor deviceUS5543733 *Jun 26, 1995Aug 6, 1996Vlsi Technology, Inc.Input/output circuitUS5576635 *Apr 17, 1995Nov 19, 1996Advanced Micro Devices, Inc.Output buffer with improved tolerance to overvoltageUS5589783 *Jul 29, 1994Dec 31, 1996Sgs-Thomson Microelectronics, Inc.Variable input threshold adjustmentUS5604453 *Sep 7, 1994Feb 18, 1997Altera CorporationCircuit for reducing ground bounceUS5646550 *Feb 22, 1996Jul 8, 1997Motorola, Inc.High reliability output buffer for multiple voltage systemUS5661685 *Sep 25, 1995Aug 26, 1997Xilinx, Inc.Programmable logic device with configurable power supplyUS5726589 *Nov 1, 1995Mar 10, 1998International Business Machines CorporationOff-chip driver circuit with reduced hot-electron degradationUS5748010 *Jan 3, 1996May 5, 1998Maxim Integrated ProductsLogic signal level translation apparatus having very low dropout with respect to the powering railsUS5825206 *Aug 14, 1996Oct 20, 1998Intel CorporationInput/output buffer for computer circuitryUS5880602 *Feb 28, 1996Mar 9, 1999Hitachi, Ltd.Input and output buffer circuit *USB14617479 Title not availableWO1996037958A1 *May 23, 1996Nov 28, 1996Nat Semiconductor CorpSupply and interface configurable input/output bufferWO1997021273A1 *Jul 17, 1996Jun 12, 1997Advanced Micro Devices IncA programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pull up/pull down function* Cited by examinerNon-Patent CitationsReference1A. Chandrakasan et al., "Low-Power CMOS Digital Design," IEEE Journal of Solid-State Circuits, p. 473, Apr. 1992.2 *A. Chandrakasan et al., Low Power CMOS Digital Design, IEEE Journal of Solid State Circuits, p. 473, Apr. 1992.3A. Roberts et al., "A 256K SRAM With On-Chip Power Supply Conversion," IEEE International Solid-State Circuits Conference, p. 252, Feb. 1987.4 *A. Roberts et al., A 256K SRAM With On Chip Power Supply Conversion, IEEE International Solid State Circuits Conference, p. 252, Feb. 1987.5Altera Corp., data sheet, "FLEX 8000 Programmable Logic Device Family," pp. 1-22 (version 4, Aug., 1994).6 *Altera Corp., data sheet, FLEX 8000 Programmable Logic Device Family, pp. 1 22 (version 4, Aug., 1994).7B. Davari et al., "CMOS Scaling for High Performance and Low Power--The Next Ten Years," Proceedings of the IEEE, p. 595, Apr. 1995.8 *B. Davari et al., CMOS Scaling for High Performance and Low Power The Next Ten Years, Proceedings of the IEEE, p. 595, Apr. 1995.9B. Prince et al., "IC Voltage Dives," IEEE Spectrum, p. 22, May 1992.10 *B. Prince et al., IC Voltage Dives, IEEE Spectrum, p. 22, May 1992.11C. Hu, "Future CMOS Scaling and Reliability," Proceedings of the IEEE, p. 682, May 1993.12 *C. Hu, Future CMOS Scaling and Reliability, Proceedings of the IEEE, p. 682, May 1993.13D. Dobberpuhl et al., "A 200-MHz 64-b Dual Issue CMOS Microprocessor," IEEE Journal of Solid-State Circuits, p. 1555, Nov. 1992.14 *D. Dobberpuhl et al., A 200 MHz 64 b Dual Issue CMOS Microprocessor, IEEE Journal of Solid State Circuits, p. 1555, Nov. 1992.15Foss R. C. et al., "Application of a High-Voltage Pumped Supply for Low-Power DRAM," Mosaid Technologies Incorporated Publication, Canada, Jan. 24, 1994, two pages.16 *Foss R. C. et al., Application of a High Voltage Pumped Supply for Low Power DRAM, Mosaid Technologies Incorporated Publication, Canada, Jan. 24, 1994, two pages.17Intel Datasheet entitled "Pentium� Processor at iCOMP� Index 815/100 MHz, Pentium Processor at iCOMP Index 735/90 MHz, Pentium Processor at iCOMP Index 610/75 MHz, with Voltage Reduction Technology," Copyright� Intel Corporation 1996, Order No. 242973-001, Mar. 1996, pp. 1-73.18Intel Datasheet entitled "Pentium� Processors with Voltage Reduction Technology," Order No. 242557-005, Aug. 1996, pp. 1-81.19 *Intel Datasheet entitled Pentium Processor at iCOMP Index 815/100 MHz, Pentium Processor at iCOMP Index 735/90 MHz, Pentium Processor at iCOMP Index 610/75 MHz, with Voltage Reduction Technology, Copyright Intel Corporation 1996, Order No. 242973 001, Mar. 1996, pp. 1 73.20 *Intel Datasheet entitled Pentium Processors with Voltage Reduction Technology, Order No. 242557 005, Aug. 1996, pp. 1 81.21J. Williams, "Mixing 3V and 5V ICs," IEEE Spectrum, p. 40, Mar. 1993.22 *J. Williams, Mixing 3V and 5V ICs, IEEE Spectrum, p. 40, Mar. 1993.23K. Ishibashi et al., "A Voltage Down Converter With Submicroampere Standby Current for Low-Power Static RAM's," IEEE Journal of Solid-State Circuits, p. 920, Jun. 1992.24 *K. Ishibashi et al., A Voltage Down Converter With Submicroampere Standby Current for Low Power Static RAM s, IEEE Journal of Solid State Circuits, p. 920, Jun. 1992.25M. Kakumu et al., "Power-Supply Voltage Impact on Circuit Performance for Half and Lower Submicrometer CMOS LSI," IEEE Trans. on Electron Devices, p. 1902, Aug. 1990.26 *M. Kakumu et al., Power Supply Voltage Impact on Circuit Performance for Half and Lower Submicrometer CMOS LSI, IEEE Trans. on Electron Devices, p. 1902, Aug. 1990.27M. Pelgrom et al., "A 3/5 Compatible I/O Buffer," IEEE Journal of Solid-State Circuits, p. 823, Jul. 1995.28 *M. Pelgrom et al., A 3/5 Compatible I/O Buffer, IEEE Journal of Solid State Circuits, p. 823, Jul. 1995.29M. Ueda et al., "A 3.3V ASIC for Mixed Voltage Applications With Shut Down Mode," in Proc. CICC, p. 25.5.1, May 1993.30 *M. Ueda et al., A 3.3V ASIC for Mixed Voltage Applications With Shut Down Mode, in Proc. CICC, p. 25.5.1, May 1993.31R. Moazzami et al., "Projecting Gate Oxide Reliability and Optimizing Reliability Screens," IEEE Trans. on Electron. Devices, p. 1643, Jul. 1990.32 *R. Moazzami et al., Projecting Gate Oxide Reliability and Optimizing Reliability Screens, IEEE Trans. on Electron. Devices, p. 1643, Jul. 1990.33R. Patel et al., "A 90.7MHz--2.5 Million Transistor CMOS CPLD with JTAG Boundry Scan and In-System Programmability," in Proc. CICC, p. 24.5.1, May 1995.34 *R. Patel et al., A 90.7MHz 2.5 Million Transistor CMOS CPLD with JTAG Boundry Scan and In System Programmability, in Proc. CICC, p. 24.5.1, May 1995.35S. Reddy et al., "A High Density Embedded Array Programmable Logic Architecture," in Proc. CICC, May 1994, p. 9.2.1.36 *S. Reddy et al., A High Density Embedded Array Programmable Logic Architecture, in Proc. CICC, May 1994, p. 9.2.1.37T. Chan et al., "The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling," IEDM Tech. Dig., p. 718, 1987.38 *T. Chan et al., The Impact of Gate Induced Drain Leakage Current on MOSFET Scaling, IEDM Tech. Dig., p. 718, 1987.39 *The 2.5 V Power Supply Interface Standard, JEDEC Standard, No. 8 5, Oct. 1995.40The 2.5 V Power Supply Interface Standard, JEDEC Standard, No. 8-5, Oct. 1995.41Xilinx Corp., The Programmable Logic Data Book, "The Best of XCELL," pp. 9-1 to 9-32 (1994).42Xilinx Corp., The Programmable Logic Data Book, "XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families," pp. 2-105 to 2-124 (1994).43Xilinx Corp., The Programmable Logic Data Book, "XC4000, XC4000A, XC4000H Logic Cell Array Families," pp. 2-7 to 2-46 (1994).44 *Xilinx Corp., The Programmable Logic Data Book, The Best of XCELL, pp. 9 1 to 9 32 (1994).45 *Xilinx Corp., The Programmable Logic Data Book, XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families, pp. 2 105 to 2 124 (1994).46 *Xilinx Corp., The Programmable Logic Data Book, XC4000, XC4000A, XC4000H Logic Cell Array Families, pp. 2 7 to 2 46 (1994).* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6369613Apr 26, 2000Apr 9, 2002Altera CorporationInput/output driversUS6369619 *Jul 14, 2000Apr 9, 2002Artisan Components, Inc.Voltage tolerant input/output circuitUS6388499Jan 25, 2001May 14, 2002Integrated Device Technology, Inc.Level-shifting signal buffers that support higher voltage power supplies using lower voltage MOS technologyUS6392488 *Sep 12, 2000May 21, 2002Silicon Laboratories, Inc.Dual oxide gate device and method for providing the sameUS6407582 *Mar 13, 2001Jun 18, 2002International Business Machines CorporationEnhanced 2.5V LVDS driver with 1.8V technology for 1.25 GHz performanceUS6448847Sep 12, 2000Sep 10, 2002Silicon Laboratories, Inc.Apparatus and method for providing differential-to-single ended conversion and impedance transformationUS6459300 *Sep 28, 2000Oct 1, 2002Infineon Technologies AgLevel-shifting circuitry having �high� output during disable modeUS6462620Sep 12, 2000Oct 8, 2002Silicon Laboratories, Inc.RF power amplifier circuitry and method for amplifying signalsUS6529421 *Aug 28, 2001Mar 4, 2003Micron Technology, Inc.SRAM array with temperature-compensated threshold voltageUS6549032Aug 22, 2001Apr 15, 2003Altera CorporationIntegrated circuit devices with power supply detection circuitryUS6549071Sep 12, 2000Apr 15, 2003Silicon Laboratories, Inc.Power amplifier circuitry and method using an inductance coupled to power amplifier switching devicesUS6584030Aug 28, 2001Jun 24, 2003Micron Technology, Inc.Memory circuit regulation system and methodUS6674305Jul 8, 2002Jan 6, 2004Semiconductor Components Industries LlcMethod of forming a semiconductor device and structure thereforUS6727754Apr 26, 2001Apr 27, 2004Silicon Laboratories, Inc.RF power detectorUS6731137Apr 24, 2002May 4, 2004Altera CorporationProgrammable, staged, bus hold and weak pull-up for bi-directional I/OUS6737885Dec 20, 2002May 18, 2004Altera CorporationIntegrated circuit devices with power supply detection circuitryUS6788141Mar 18, 2003Sep 7, 2004Silicon Laboratories, Inc.Power amplifier circuitry and methodUS6809968Feb 18, 2003Oct 26, 2004Micron Technology, Inc.SRAM array with temperature-compensated threshold voltageUS6816011May 30, 2003Nov 9, 2004Silicon Laboratories, Inc.RF power amplifier and method for packaging the sameUS6828859Aug 17, 2001Dec 7, 2004Silicon Laboratories, Inc.Method and apparatus for protecting devices in an RF power amplifierUS6853233Sep 13, 2000Feb 8, 2005Infineon Technologies AgLevel-shifting circuitry having �high� output impedance during disable modeUS6894565Dec 3, 2002May 17, 2005Silicon Laboratories, Inc.Fast settling power amplifier regulatorUS6897730Mar 4, 2003May 24, 2005Silicon Laboratories Inc.Method and apparatus for controlling the output power of a power amplifierUS6917245Mar 13, 2002Jul 12, 2005Silicon Laboratories, Inc.Absolute power detectorUS6927630Sep 29, 2003Aug 9, 2005Silicon Laboratories Inc.RF power detectorUS6985010Jan 6, 2004Jan 10, 2006Altera CorporationIntegrated circuit devices with power supply detection circuitryUS7106137Jun 30, 2004Sep 12, 2006Silicon Laboratories Inc.Method and apparatus for controlling the output power of a power amplifierUS7129745Jun 10, 2004Oct 31, 2006Altera CorporationApparatus and methods for adjusting performance of integrated circuitsUS7145396Sep 29, 2003Dec 5, 2006Silicon Laboratories, Inc.Method and apparatus for protecting devices in an RF power amplifierUS7173473Jan 24, 2005Feb 6, 2007Infineon Technologies AgLevel-shifting circuitry having �high� output impedance during disable modeUS7173491Mar 31, 2004Feb 6, 2007Silicon Laboratories Inc.Fast settling power amplifier regulatorUS7224232Nov 8, 2004May 29, 2007Silicon Laboratories Inc.RF power amplifier and method for packaging the sameUS7345509Jul 29, 2005Mar 18, 2008Altera CorporationIntegrated circuit devices with power supply detection circuitryUS7348827 *May 19, 2004Mar 25, 2008Altera CorporationApparatus and methods for adjusting performance of programmable logic devicesUS7532034Jul 19, 2006May 12, 2009National Chiao Tung UniversityMixed voltage input/output buffer having low-voltage designUS7733159Mar 18, 2004Jun 8, 2010Altera CorporationHigh voltage tolerance emulation using voltage clamp for oxide stress protectionUS8018268 *Nov 15, 2005Sep 13, 2011Cypress Semiconductor CorporationOver-voltage tolerant input circuitUS8149064Mar 30, 2004Apr 3, 2012Black Sand Technologies, Inc.Power amplifier circuitry and method* Cited by examinerClassifications U.S. Classification326/81, 326/86International ClassificationH01L27/04, G11C5/14, H01L21/822, H03K19/0175, H03K19/003, H03K19/00, H03K19/0185Cooperative ClassificationH03K19/00315, H03K19/018585, H03K19/018521, H03K19/0027European ClassificationH03K19/00T4, H03K19/0185P, H03K19/0185B4, H03K19/003CLegal EventsDateCodeEventDescriptionApr 24, 2012FPAYFee paymentYear of fee payment: 12Apr 17, 2008FPAYFee paymentYear of fee payment: 8Mar 29, 2004FPAYFee paymentYear of fee payment: 4Dec 31, 2002CCCertificate of correctionJan 8, 1998ASAssignmentOwner name: ALTERA CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PATEL, RAKESH H.;TURNER, JOHN E.;WONG, WILSON;REEL/FRAME:008894/0774Effective date: 19971120RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google