Source: https://patents.google.com/patent/JP5152133B2/en
Timestamp: 2020-02-19 14:13:10
Document Index: 561771738

Matched Legal Cases: ['art 72', 'arts 72', 'art 72', 'art 700', 'art 720', 'art 700', 'art 720', 'art 71', 'art 71', 'art 71', 'art 73', 'art 73', 'art 73']

JP5152133B2 - Light emitting element - Google Patents
JP5152133B2
JP5152133B2 JP2009217231A JP2009217231A JP5152133B2 JP 5152133 B2 JP5152133 B2 JP 5152133B2 JP 2009217231 A JP2009217231 A JP 2009217231A JP 2009217231 A JP2009217231 A JP 2009217231A JP 5152133 B2 JP5152133 B2 JP 5152133B2
JP2009217231A
JP2011066304A (en
真央 神谷
2009-09-18 Application filed by 豊田合成株式会社 filed Critical 豊田合成株式会社
2009-09-18 Priority to JP2009217231A priority Critical patent/JP5152133B2/en
2011-03-31 Publication of JP2011066304A publication Critical patent/JP2011066304A/en
2013-02-27 Publication of JP5152133B2 publication Critical patent/JP5152133B2/en
The present invention relates to a flip-chip type light emitting element.
Conventionally, a diffusion electrode comprising a diffusion electrode formed on a semiconductor layer, a passivation film that covers the surface of the diffusion electrode and having an opening in part, and a bonding electrode having a solder layer on the upper surface A semiconductor light emitting device is known in which a buffer electrode having a diameter larger than that of the opening and flatter than the surface of the diffusion electrode is formed on the bottom of the opening of the passivation film, and the bonding electrode is connected to the buffer electrode. (For example, refer to Patent Document 1).
In the semiconductor light emitting device described in Patent Document 1, a buffer electrode is formed on the surface of the diffusion electrode, and an opening smaller than the buffer electrode is formed in the passivation film on the buffer electrode, so that the surface of the buffer electrode is flat. Therefore, adhesion between the buffer electrode and the passivation film can be ensured, and when the opening is etched, the progress of the etching in the lateral direction from the interface between the buffer electrode and the passivation film can be suppressed. it can.
JP 2008-288548 A
However, the semiconductor light-emitting device described in Patent Document 1 uses a via provided directly above the p electrode and the n electrode in order to electrically connect the p electrode and the n electrode as the ohmic electrode and the junction electrode. Since the electrode and the n-electrode and the junction electrode are electrically connected, there is a limit in improving the degree of freedom of arrangement of the junction electrode. In particular, when the arrangement of the p-electrode and the n-electrode is complicated, or the shape is complicated, the arrangement of the bonding electrodes is likely to be complicated.
Accordingly, an object of the present invention is to provide a light-emitting element having a high degree of freedom in designing the arrangement and shape of the junction electrode even if the arrangement or shape of the ohmic electrode is complicated.
In order to achieve the above object, the present invention provides a nitride compound semiconductor including a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type. A semiconductor multi-layer structure comprising: an insulating layer provided on the semiconductor multi-layer structure; a first vertical conduction portion extending vertically in the insulating layer, the light emitting layer, and the second semiconductor layer; and A first planar conductive portion extending in a planar direction inside, a first wiring electrically connected to the first semiconductor layer, a second vertical conductive portion extending in the vertical direction inside the insulating layer, A light-emitting element is provided that includes a second planar conductive portion extending in a planar direction inside the insulating layer, and a second wiring electrically connected to the second semiconductor layer.
In the light emitting element, a first bonding electrode provided on the insulating layer and electrically connected to the first wiring, and a first bonding electrode provided on the insulating layer and electrically connected to the second wiring. 2 junction electrodes.
In the above light emitting device, the insulating layer may include a reflective layer that reflects light emitted from the light emitting layer.
In the light emitting device, the first planar conducting portion and the second planar conducting portion may be provided on the same plane.
In the light emitting device, the first planar conducting portion and the second planar conducting portion may be provided on different planes.
In the light emitting device, the first bonding electrode and the second bonding electrode may be provided on the same plane.
The light emitting device includes: a first ohmic electrode that is in ohmic contact with the first semiconductor layer; a transparent conductive layer that is in ohmic contact with the second semiconductor layer; and a second ohmic electrode that is in ohmic contact with the transparent conductive layer; The first wiring may be electrically connected to the first ohmic electrode, and the second wiring may be electrically connected to the second ohmic electrode.
In the above light emitting device, the material constituting the first ohmic electrode and the material constituting the second ohmic electrode may be the same.
In the light-emitting element, the material constituting the first wiring and the material constituting the second wiring may be the same.
In the light emitting element, each of the first bonding electrode and the second bonding electrode may have a cut in a plan view.
The light emitting device according to the present invention can provide a light emitting device having a high degree of freedom in designing the arrangement and shape of the junction electrode even if the arrangement or shape of the ohmic electrode is complicated.
FIG. 1A is a plan view of a light emitting device according to a first embodiment of the present invention. FIG. 1B is a longitudinal sectional view of the light emitting device according to the first embodiment of the present invention. FIG. 1C is a longitudinal sectional view of the light emitting device according to the first embodiment of the present invention. FIG. 2A is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 2B is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 2C is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 3 is a plan view of a light emitting device according to the second embodiment of the present invention. FIG. 4 is a plan view of a light emitting device according to the third embodiment of the present invention. FIG. 5 is a diagram showing the relationship between the area ratio of the p-electrode and the total radiant flux of the light-emitting element. FIG. 6 is a diagram showing the relationship between the area ratio of the n-electrode and the total radiant flux. FIG. 7 is a diagram showing the relationship between current density and external quantum efficiency. FIG. 8A is a diagram illustrating a state of the light emitting element 1 at the time of light emission, and FIG. 8B is a light emission time of the light emitting element according to the first modification in which the number of p electrodes and n electrodes of the light emitting element 1 is changed. FIG. 8C is a diagram illustrating a state at the time of light emission of the light emitting element according to the modified example 2 in which the number of p electrodes and n electrodes of the light emitting element 1 is changed. FIG. 9A is a diagram showing a comparison between a predicted value of luminous intensity and an actual measurement value with respect to an input current to the light emitting element. FIG. 9B is a diagram showing a comparison between a predicted value of a forward voltage and an actually measured value with respect to an input current to the light emitting element. FIG. 10A is a diagram illustrating a comparison between a predicted value of luminous intensity and an actual measurement value with respect to an input current to the first modification of the light-emitting element. FIG. 10B is a diagram showing a comparison between a predicted value and a measured value of a forward voltage with respect to an input current to the light emitting element modification example 1; FIG. 11A is a diagram showing a comparison between a predicted value of luminous intensity and an actually measured value with respect to an input current to the modification 2 of the light emitting element. FIG. 11B is a diagram showing a comparison between a predicted value and a measured value of the forward voltage with respect to the input current to the light emitting element modification example 2.
FIG. 1A shows an outline of the upper surface of the light emitting device according to the first embodiment of the present invention, and FIGS. 1B and 1C show an outline of a longitudinal section of the light emitting device according to the first embodiment of the present invention. Show. Specifically, FIG. 1B shows an outline of a longitudinal section of the light emitting element taken along line AA in FIG. 1A, and FIG. 1C shows an outline of a longitudinal section of the light emitting element taken along line BB in FIG. 1A.
(Configuration of Light-Emitting Element 1)
As illustrated in FIG. 1B and FIG. 1C, the light-emitting element 1 according to the first embodiment of the present invention includes, as an example, a sapphire substrate 10 having a C plane (0001), and a buffer layer provided on the sapphire substrate 10. 20, an n-side contact layer 22 provided on the buffer layer 20, an n-side cladding layer 24 provided on the n-side contact layer 22, a light emitting layer 25 provided on the n-side cladding layer 24, and a light emitting layer 25 A semiconductor laminated structure including a p-side cladding layer 26 provided on the upper surface and a p-side contact layer 28 provided on the p-side cladding layer 26 is provided.
The light emitting element 1 includes a transparent conductive layer 30 provided on the p-side contact layer 28 and a plurality of p electrodes 40 provided in a part of the region on the transparent conductive layer 30. Furthermore, the light-emitting element 1 includes a plurality of vias formed from the p-side contact layer 28 to at least the surface of the n-side contact layer 22, and a plurality of n-electrodes 42 provided in the n-side contact layer 22 exposed by the vias, A lower insulating layer 50 provided on the inner surface of the via and the transparent conductive layer 30 and a reflective layer 60 provided in the lower insulating layer 50 are provided. The reflective layer 60 is provided in a portion excluding the upper part of the p electrode 40 and the n electrode 42.
Furthermore, the lower insulating layer 50 in contact with the transparent conductive layer 30 has a via 50a extending in the vertical direction on each p-electrode 40 and a via 50b extending in the vertical direction on each n-electrode 42. In addition, the light emitting element 1 includes a p wiring 70 and an n wiring 72 on the lower insulating layer 50. The p wiring 70 includes a second planar conductive portion 700 extending in the planar direction on the lower insulating layer 50, and a plurality of second vertical conductive portions 702 that are electrically connected to the p electrodes 40 via the vias 50a. The n wiring 72 is electrically connected to each n electrode 42 via the first planar conductive portion 720 extending in the planar direction on the lower insulating layer 50, the via 50b of the lower insulating layer 50, and the via formed in the semiconductor multilayer structure. And a plurality of first vertical conduction portions 722 connected to each other. Further, the light emitting element 1 is in contact with the p wiring 70, the n wiring 72, and the transparent conductive layer 30, and an upper insulating layer 80 provided on the lower insulating layer 50 and a p-side opening 80 a provided in the upper insulating layer 80. A p-side junction electrode 90 that is electrically connected to the p-line 70 via the n-side and an n-side junction electrode 92 that is electrically connected to the n-line 72 via the n-side opening 80b provided in the upper insulating layer 80. With.
In the present embodiment, the second planar conductive portion 700 of the p wiring 70 and the first planar conductive portion 720 of the n wiring 72 are formed on the surface of the lower insulating layer 50 in contact with the transparent conductive layer 30, respectively. Provided on the same plane. In the present embodiment, the p-side bonding electrode 90 and the n-side bonding electrode 92 are provided on the same plane by being formed on the surface of the upper insulating layer 80.
(Semiconductor laminated structure)
Here, the buffer layer 20, the n-side contact layer 22, the n-side cladding layer 24, the light emitting layer 25, the p-side cladding layer 26, and the p-side contact layer 28 are each made of a group III nitride compound semiconductor. It is a layer. The group III nitride compound semiconductor is, for example, a quaternary group III nitride of Al x Ga y In 1-xy N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). A physical compound semiconductor can be used.
In the present embodiment, the buffer layer 20 is made of AlN. The n-side contact layer 22 and the n-side cladding layer 24 are each formed from n-GaN doped with a predetermined amount of n-type dopant (for example, Si). Moreover, the light emitting layer 25 has a multiple quantum well structure formed including a plurality of well layers and a plurality of barrier layers. The light emitting layer 25 is made of, for example, GaN, InGaN, AlGaN, or the like. Furthermore, the p-side cladding layer 26 and the p-side contact layer 28 are each formed from p-GaN doped with a predetermined amount of p-type dopant (for example, Mg).
(Transparent conductive layer 30, p electrode 40, n electrode 42)
The transparent conductive layer 30 is formed from a conductive oxide. For example, the transparent conductive layer 30 can be formed from ITO (Indium Tin Oxide). The material constituting the p electrode 40 and the material constituting the n electrode 42 are the same. In addition, when forming the p electrode 40 and the n electrode 42 from a multilayer, each layer structure is the same. For example, the p electrode 40 and the n electrode 42 are formed from a metal material containing Ni or Cr, Au, and Al. In particular, when the n-side contact layer 22 is formed of n-type GaN, the n-electrode 42 can be formed including a Ni layer as a contact layer from the n-side contact layer 22 side, or the n-side contact layer It can be formed including a Cr layer as a contact layer from the side of 22. In particular, when the transparent conductive layer 30 is formed of an oxide semiconductor, the p-electrode 40 can be formed including a Ni layer as a contact layer from the transparent conductive layer 30 side, or the transparent conductive layer 30 It can be formed including a Cr layer as a contact layer from the side. Specifically, the p electrode 40 and the n electrode 42 can be formed including a Ni layer, an Au layer, and an Al layer from the transparent conductive layer 30 side and the n side contact layer 22 side, respectively.
In the present embodiment, the plurality of p electrodes 40 are regularly arranged on the transparent conductive layer 30. Similarly, the plurality of n electrodes 42 are regularly arranged on a plane different from the plane on which the plurality of p electrodes 40 are provided in the thickness direction of the light emitting element 1 (for example, the exposed surface of the n-side contact layer 22). Is done. Specifically, as shown by a broken line in FIG. 1A, the plurality of p-electrodes 40 are set so that one side of the light emitting element 1 is set as the first axis in the plan view, and the side orthogonal to the one side is set to the second axis. Assuming that it is an axis, it is periodically arranged along the first axis and the second axis. In the present embodiment, the plurality of p electrodes 40 are arranged at positions corresponding to lattice points of a lattice having a predetermined lattice interval. The plurality of n-electrodes 42 are periodically arranged at positions that do not overlap the p-electrodes 40 in plan view. In the present embodiment, each of the plurality of n electrodes 42 is a square formed by arranging four p electrodes 40 at four corners in a plan view, and has a minimum square face center position (that is, 2 of the squares). At the intersection of the diagonal lines of the book). In other words, the p-electrodes 40 and the n-electrodes 42 are arranged at alternate positions with respect to the first axis and the second axis.
Note that the shape of each p-electrode 40 and each n-electrode 42 in a plan view can be a substantially circular shape or a substantially polygonal shape (for example, a triangle, a quadrangle, a pentagon, a hexagon, etc.). The size of each p-electrode 40 and each n-electrode 42 in plan view can be set in consideration of an improvement in the ratio of the area of the light-emitting region (hereinafter referred to as “light-emitting area”) to the total area of the element 1 in plan view. . For example, when the shape of the p electrode 40 and the n electrode 42 in a plan view is substantially circular, the diameters of the p electrode 40 and the n electrode 42 can be 5 μm or more and 50 μm or less. In particular, for the purpose of improving the ratio of the light emitting area to the total area of the light emitting element 1, the diameter of the n electrode 42 can be set to, for example, about 5 μm to 30 μm, and 5 μm to further increase the light emitting area. It can also be 20 μm or less.
(Lower insulating layer 50, reflective layer 60)
The lower insulating layer 50 is formed including a reflective layer 60 that reflects light emitted from the light emitting layer 25. The lower insulating layer 50 is mainly formed from, for example, silicon dioxide (SiO 2 ) that is an insulating material. The reflective layer 60 is made of a metal material that reflects light emitted from the light emitting layer 25, for example, Al.
(P wiring 70, n wiring 72)
Each of the p wiring 70 and the n wiring 72 can be formed mainly including Ti, Au, and Al. For example, the p wiring 70 and the n wiring 72 can each be formed to include a Ti layer, an Au layer, and an Al layer in this order from the side in contact with the lower insulating layer 50.
Further, as shown in FIG. 1A, the p wiring 70 has an outer peripheral portion 70 a provided near the outer periphery of the light emitting element 1 and along the outer periphery in the plan view of the light emitting element 1. Furthermore, the p wiring 70 has a plurality of p-side thin wire portions 70b extending from one side of the outer peripheral portion 70a toward the opposite side of the one side. The plurality of p-side thin wire portions 70b have substantially the same length in a range that does not contact the opposite side in the longitudinal direction, and are arranged at substantially equal intervals in the width direction.
In addition, the n wiring 72 extends inside the outer peripheral portion 70a in a plan view of the light emitting element 1 and extends in a direction perpendicular to the plurality of p-side thin wire portions 70b, and is disposed in the vicinity of the opposite side of the outer peripheral portion 70a. It has a side part 72a and a plurality of n-side thin wire parts 72b extending from the side part 72a toward the one side. The plurality of n-side thin wire portions 72b are respectively disposed between the outer peripheral portion 70a and the p-side thin wire portion 70b or between the two p-side thin wire portions 70b in the plan view. Are disposed at positions where the distances from the p-side thin wire portion 70b are substantially the same. Therefore, the plurality of p-side thin wire portions 70b and the plurality of n-side thin wire portions 72b are alternately arranged in plan view.
1B and 1C, the upper insulating layer 80 is disposed between the first planar conductive portion 700 and the second planar conductive portion 720 in the planar direction, whereby the p wiring 70 and the n wiring 72 are arranged. And are electrically separated. In addition to the p-electrode 40 and the n-electrode 42 that are in ohmic contact with the compound semiconductor layer, the p-wiring 70 and the n-wiring 72 are provided between the lower insulating layer 50 and the upper insulating layer 80, thereby providing an ohmic electrode function. The wiring function is separated. The upper insulating layer 80 can be formed of the same material as that of the lower insulating layer 50 in contact with the transparent conductive layer 30, and forms an insulating layer integrally with the lower insulating layer 50.
(P-side junction electrode 90 and n-side junction electrode 92)
Each of the p-side bonding electrode 90 and the n-side bonding electrode 92 can be formed including a eutectic material, for example, AuSn. Each of the p-side bonding electrode 90 and the n-side bonding electrode 92 is formed in a substantially rectangular shape in plan view. For example, the size of the p-side junction electrode 90 and the n-side junction electrode 92 in plan view can be such that the area of the p-side junction electrode 90 is larger than the area of the n-side junction electrode 92. Note that the shape and area of the p-side bonding electrode 90 and the n-side bonding electrode 92 in plan view are determined by contacting the probe of the measuring device used when evaluating the characteristics of the light-emitting element 1 and / or mounting the light-emitting element 1. It can change suitably according to the mounting board | substrate etc. to perform.
Further, the p-side bonding electrode 90 and the n-side bonding electrode 92 are formed by, for example, a vacuum evaporation method (for example, an electron beam evaporation method or a resistance heating evaporation method), a sputtering method, a plating method, a screen printing method, or the like. Can do. The p-side bonding electrode 90 and the n-side bonding electrode 92 can also be formed from eutectic solder made of a eutectic material other than AuSn or lead-free solder such as SnAgCu. Furthermore, the p-side bonding electrode 90 and the n-side bonding electrode 92 can be formed to have a barrier layer and a solder layer from the p wiring 70 and the n wiring 72 side.
Specifically, the barrier layer is a first barrier layer that contacts the p wiring 70 and the n wiring 72, and a second barrier that is formed on the first barrier layer and suppresses diffusion of a material constituting the solder layer. And a layer. The first barrier layer is formed of a material having ohmic contact with the material forming the p wiring 70 and the material forming the n wiring 72 and having good adhesion, and is mainly formed of Ti, for example. The second barrier layer is formed of a material capable of suppressing the material constituting the solder layer from diffusing to the p wiring 70 and the n wiring 72 side, and is mainly formed of Ni, for example. The material constituting the p-side junction electrode 90 and the material constituting the n-side junction electrode 92 can be the same.
The light emitting element 1 configured as described above is a flip chip type light emitting diode (LED) that emits light having a wavelength in a blue region. For example, the light emitting element 1 emits light having a peak wavelength of about 455 nm when the forward voltage is about 3 V and the forward current is 350 mA. The light emitting element 1 is formed in a substantially square shape in plan view. For example, the vertical dimension and the horizontal dimension of the light emitting element 1 are approximately 1000 μm, respectively.
Each layer from the buffer layer 20 to the p-side contact layer 28 provided on the sapphire substrate 10 is, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (Molecular Beam). Epitaxy (MBE), Halide Vapor Phase Epitaxy (HVPE), etc. Here, the buffer layer 20 is formed of AlN, but the buffer layer 20 can also be formed of GaN. Further, the quantum well structure of the light emitting layer 30 may be a single quantum well structure or a strained quantum well structure instead of a multiple quantum well structure.
The lower insulating layer 50 and the upper insulating layer 80 are made of metal oxide such as titanium oxide (TiO 2 ), alumina (Al 2 O 3 ), tantalum pentoxide (Ta 2 O 5 ), or electrical insulating properties such as polyimide. It can also be formed from a resin material having And the reflective layer 60 can also be formed from Ag, and can also be formed from the alloy which contains Al or Ag as a main component. The reflective layer 60 may be a distributed Bragg reflector (DBR) formed from a plurality of layers of two materials having different refractive indexes.
Furthermore, the light emitting element 1 may be an LED that emits light having a peak wavelength in the ultraviolet region, the near ultraviolet region, or the green region, but the region of the peak wavelength of the light emitted by the LED is not limited thereto. In other modified examples, the planar dimension of the light emitting element 1 is not limited to this. For example, the planar dimension of the light emitting element 1 can be designed such that the vertical dimension and the horizontal dimension are each 300 μm, and the vertical dimension and the horizontal dimension can be different from each other. Further, by using this structure, it is possible to form a small light-emitting element 1 having a vertical dimension and / or a horizontal dimension of about 100 μm.
In the present embodiment, the first plane conducting portion 700 of the p wiring 70 and the second plane conducting portion 720 of the n wiring 72 are provided on the same plane, but they may be provided on different planes. For example, by changing the thickness of the lower insulating layer 50 in contact with the transparent conductive layer 30, the plane on which the n wiring 72 is provided can be made higher or lower than the plane on which the p wiring 70 is provided. Thereby, it can arrange | position so that the 1st plane conduction | electrical_connection part 700 and the 2nd plane conduction | electrical_connection part 720 may overlap in planar view, and the design freedom of an element improves. Furthermore, the size in plan view of the p-electrode 40 and the n-electrode 42 is not limited to the above example. The arrangement of the p electrode 40 and the n electrode 42 is not limited to the above example.
(Manufacturing process of light-emitting element 1)
2A to 2C show an example of a manufacturing process of the light-emitting element according to the first embodiment. Specifically, (a) of FIG. 2A is a vertical cross-sectional view before etching for forming a via is performed. FIG. 2A (b) is a vertical cross-sectional view after etching for forming a via is performed. Moreover, (c) of FIG. 2A is a longitudinal cross-sectional view in a state where a p-electrode and an n-electrode are formed. 2A to 2C illustrate an example of a manufacturing process of the light-emitting element viewed from a cross section taken along the line CC in FIG. 1A.
First, a sapphire substrate 10 is prepared, and a semiconductor stacked structure including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer is formed on the sapphire substrate 10. Specifically, the buffer layer 20, the n-side contact layer 22, the n-side cladding layer 24, the light emitting layer 25, the p-side cladding layer 26, and the p-side contact layer 28 are formed on the sapphire substrate 10. Epitaxial growth is performed in this order to form an epitaxial growth substrate (semiconductor laminated structure forming step). Subsequently, the transparent conductive layer 30 is formed on the entire surface of the p-side contact layer 28 (FIG. 2A (a), transparent conductive layer forming step). In this embodiment, the transparent conductive layer 30 is formed from ITO. The transparent conductive layer 30 is formed using, for example, a vacuum evaporation method. The transparent conductive layer 30 can also be formed by a sputtering method, a CVD method, a sol-gel method, or the like.
Subsequently, a mask made of a photoresist is formed on the transparent conductive layer 30 using a photolithography technique. And about the area | region except the part in which the mask was formed, after etching from the transparent conductive layer 30 and the p side contact layer 28 to the surface of the n side contact layer 22, a mask is removed (via formation process). Thereby, the substrate with a transparent conductive layer having the via 5 formed by removing the surface of the transparent conductive layer 30 from the n-side contact layer 22 is formed (FIG. 2A (b)). In the via formation step, etching is performed to a part of the n-side contact layer 22 for the purpose of completely removing the portion from the n-side cladding layer 24 to the p-side contact layer 28 where the mask is not formed. You can also.
Thereafter, a mask 200 is formed with a photoresist in a region excluding the region where the p-electrode 40 is to be formed and the via 5. Then, the p-electrode 40 and the n-electrode 42 are formed by using a vacuum deposition method (FIG. 2A (c), electrode forming step). In the present embodiment, the material constituting the p electrode 40 and the material constituting the n electrode 42 are the same material. That is, by simultaneously vacuum-depositing an electrode material on the surface of the transparent conductive layer 30 where the mask 200 is not formed and the surface of the n-side contact layer 22 exposed by the via 5, An n-electrode 42 is formed. In addition, after forming the p electrode 40 and the n electrode 42, in order to ensure the ohmic contact and adhesiveness between the transparent conductive layer 30 and the p electrode 40, and between the n side contact layer 22 and the n electrode 42. In addition, heat treatment can be performed for a predetermined time at a predetermined temperature and in a predetermined atmosphere. In addition, the material constituting the p-electrode 40 and the material constituting the n-electrode 42 can be different materials. In this case, the p electrode 40 and the n electrode 42 are not formed at the same time but are formed separately.
FIG. 2B (a) is a longitudinal sectional view after forming the first insulating layer and the reflective layer. FIG. 2B (b) is a longitudinal sectional view after forming the second insulating layer. Further, FIG. 2B (c) is a longitudinal sectional view after the via is formed.
First, the first insulating layer 52 that covers the p-electrode 40 and the n-electrode 42 is formed. The first insulating layer 52 is formed by a vacuum deposition method (first insulating layer forming step). Then, a reflective layer 60 is formed on the first insulating layer 52 in a predetermined region excluding above the p-electrode 40 and the n-electrode 42 by using a vacuum deposition method and a photolithography technique (FIG. 2B (a)). , Reflective layer forming step).
Next, a second insulating layer 54 is formed on the upper side of the reflective layer 60 and the upper side of the first insulating layer 52 where the reflective layer 60 is not formed by using a vacuum deposition method (FIG. 2B (b), (2) Insulating layer forming step). As a result, the reflective layer 60 is covered with the second insulating layer 54. The first insulating layer 52 and the second insulating layer 54 constitute the lower insulating layer 50 according to this embodiment.
Subsequently, at least a part of the upper portion of the p-electrode 40 and the upper portion of the n-electrode 42 in the lower insulating layer 50 are removed using a photolithography technique and an etching technique. Here, in forming the via 50 b on the n-electrode 42, the lower insulating layer 50 remains on the side surfaces of the n-side cladding layer 24, the light emitting layer 25, the p-side cladding layer 26, the p-side contact layer 28, and the diffusion electrode 30. The via 50b is formed as described above. Thereby, a via-attached substrate having the via 50a on the p-electrode 40 and the via 50b on the n-electrode 42 is formed (FIG. 2B (c), via formation step).
FIG. 2C (a) is a longitudinal sectional view after the p wiring and the n wiring are formed. FIG. 2C (b) is a longitudinal sectional view after forming the upper insulating layer. Further, FIG. 2C (c) is a longitudinal sectional view after the p-side junction electrode and the n-side junction electrode are formed.
Subsequently, by using a vacuum deposition method and a photolithography technique, a part of the surface of the second vertical conductive portion 702 filling the inside of the via 50a on the p electrode 40 and the lower insulating layer 50 in contact with the transparent conductive layer 30 is formed. The p wiring 70 having the second planar conductive portion 700 provided, the first vertical conductive portion 722 filling the inside of the via 50 b on the n electrode 42, and one surface of the lower insulating layer 50 in contact with the transparent conductive layer 30. N wiring 72 having a first plane conduction portion 720 provided in a region different from a region where p wiring 70 is provided (FIG. 2C (a), wiring formation step). The p wiring 70 and the n wiring 72 can also be formed from different materials. In this case, the p wiring 70 and the n wiring 72 are not formed simultaneously but separately.
Next, an upper insulating layer 80 that covers the p wiring 70 and the n wiring 72, specifically, the first planar conductive portion 720 and the second planar conductive portion 700 is formed by a vacuum deposition method (FIG. 2C (b), Insulating layer forming step). The upper insulating layer 80 can be formed of the same insulating material as the lower insulating layer 50 in contact with the transparent conductive layer 30, for example, SiO 2 . Subsequently, a mask is provided with a photoresist on the surface of the upper insulating layer 80, and the upper insulating layer has a via 80 a that exposes a part of the surface of the p wiring 70 and a via 80 b that exposes a part of the surface of the n wiring 72. Layer 80 is formed. Then, using a photolithography method and a vacuum deposition method, a p-side bonding electrode 90 that is electrically connected to the p wiring 70 through the via 80a that exposes a part of the surface of the second planar conductive portion 700, and the first plane An n-side bonding electrode 92 that is electrically connected to the n wiring 72 through the via 80b exposing a part of the surface of the conductive portion 720 is simultaneously formed (FIG. 2C (c), bonding electrode forming step). Note that the p-side junction electrode 90 and the n-side junction electrode 92 can also be formed from different materials. In this case, the p-side junction electrode 90 and the n-side junction electrode 92 are not formed simultaneously but separately. The
In the bonding electrode formation step, first, a barrier layer is simultaneously formed on the via 80a that exposes a part of the surface of the second planar conducting part 700 and the via 80b that exposes a part of the surface of the first planar conducting part 720. After the formation (barrier layer forming step), the p-side bonding electrode 90 and the n-side bonding electrode 92 can also be formed by forming a solder layer on the formed barrier layer (solder layer forming step). Further, the p-side junction electrode 90 and the n-side junction electrode 92 may be formed separately, not simultaneously. Thereby, the light emitting element 1 shown in FIG. 2C (c) is manufactured.
Each of the n electrode 42 and the p electrode 40 can also be formed by a sputtering method. The lower insulating layer 50 and the upper insulating layer 80 that are in contact with the transparent conductive layer 30 can also be formed by a chemical vapor deposition (CVD) method. The light emitting element 1 formed through the above steps is mounted by flip chip bonding on a predetermined position of a substrate made of ceramic or the like in which a wiring pattern of a conductive material is formed in advance. And the light emitting element 1 mounted on the board | substrate can be packaged as a light-emitting device by sealing integrally with sealing materials, such as an epoxy resin or glass.
The light-emitting element 1 according to the present embodiment includes an electrode that is in ohmic contact with the compound semiconductor (that is, the p electrode 40 and the n electrode 42) and a wiring that supplies current to the electrode (that is, the p wiring 70 and the n wiring 72). The light-emitting element 1 can be formed separately in the thickness direction by the lower insulating layer 50 in contact with the transparent conductive layer 30. Thereby, a plurality of p electrodes 40 and a plurality of n electrodes 42 can be independently provided on the semiconductor layer, and each p electrode 40 is connected to the p wiring via the via 50a located on each p electrode 40. The plurality of n electrodes 42 can be electrically connected to each other via the vias 50 b located on the respective n electrodes 42. Therefore, according to the light emitting device 1 according to the present embodiment, the shape and arrangement of the p-side junction electrode 90 and the n-side junction electrode 92 can be freely designed regardless of the shape and arrangement of the p-electrode 40 and the n-electrode 42. .
For example, in the light emitting device 1 according to the present embodiment, the n electrode 42 can be formed in a fine shape and a plurality of n electrodes 42 can be dispersed on the surface of the n side contact layer 22. The increase of the forward voltage can be suppressed and the current distribution to the light emitting layer 25 can be made uniform, and the light emitting area of the light emitting element 1 can be made 70% or more of the total area in the plan view of the light emitting element 1. it can.
Furthermore, in the light emitting element 1 according to the present embodiment, the distances to the plurality of p electrodes 40 closest to the plurality of n electrodes 42 can be unified in a plan view. Accordingly, the light intensity and the forward voltage of the light emitting element 1 can be accurately predicted from the areas of the p electrode 40 and the n electrode 42, the linear distance between the p electrode 40 and the n electrode 42, and the like. It becomes possible to design an optimum electrode according to the use environment of the element 1.
FIG. 3 shows an outline of the upper surface of the light emitting device according to the second embodiment of the present invention.
The light emitting element 2 according to the second embodiment has substantially the same configuration and the same structure as the light emitting element 1 according to the first embodiment except that the shapes of the p-side junction electrode 90 and the n-side junction electrode 92 are different. It has a function. Therefore, a detailed description is omitted except for differences.
The p-side junction electrode 90 included in the light emitting element 2 according to the second embodiment is formed to have a p-side cut 90a in a plan view, and the n-side junction electrode 92 is an n-side cut 92a in a plan view. Formed. For example, the p-side bonding electrode 90 is formed to have a meandering shape by alternately having a plurality of p-side cuts 90a in the longitudinal direction. Similarly, the n-side bonding electrode 92 is formed to have a meandering shape by alternately having a plurality of n-side cuts 92a in the longitudinal direction. Since the light-emitting element 2 includes the p-side junction electrode 90 having the p-side cut 90a and the n-side junction electrode 92 having the n-side cut 92a, when the light-emitting element 2 is mounted on a predetermined substrate or the like, p Bubbles accompanying melting of the side junction electrode 90 and the n-side junction electrode 92 can be released to the outside from the p-side cut 90a and the n-side cut 92a.
FIG. 4 shows an outline of the upper surface of the light emitting device according to the third embodiment of the present invention. In FIG. 4, illustration of the p-side junction electrode and the n-side junction electrode is omitted for convenience of explanation.
The light emitting element 3 according to the third embodiment has substantially the same configuration and function except that the light emitting element 1 according to the first embodiment is different in the shape of the p wiring and the n wiring. Therefore, a detailed description is omitted except for differences.
In the third embodiment, the p wiring 71 has an outer peripheral portion 71 a provided along the outer periphery in the vicinity of the outer periphery of the light emitting element 3 in a plan view of the light emitting element 3. Furthermore, the p wiring 71 extends from the vicinity of the midpoint of one side of the outer peripheral portion 71a toward the opposite side of the one side, and has a length of about one-fourth of one side of the light emitting element 3, and a connecting portion Connected to the end of 71b, extends in a direction parallel to the one side of the outer peripheral part 71a, and has a middle part 71c shorter than the one side and a direction perpendicular to the one side from both ends of the middle part 71c and away from the one side. And a p-side end portion 71d that has a length that is about ½ of the length of the connecting portion 71b.
The n wiring 73 extends along a direction perpendicular to the one side, has a length shorter than the length of one side of the outer peripheral portion 71a, and is provided between the outer peripheral portion 71a and the p-side end portion 71d. 73a, a direction horizontal to the one side from both ends of the side part 73a, an n-side end part 73b extending to the center side of the light emitting element 3, and a direction horizontal to the one side from the vicinity of the center of the side part 73a. And an n-side connecting portion 73c extending to the center side of the light-emitting element 3 and a center portion 73d connected to the end of the n-side connecting portion 73c and having a shape surrounding the vicinity of the center of the light-emitting element 3.
The plurality of p-electrodes 40 are arranged at a predetermined interval on the transparent conductive layer 30 corresponding to immediately below the p-wiring 71. Similarly, the plurality of n electrodes 42 are arranged at a predetermined interval on the n-side contact layer 22 corresponding directly below the n wiring 73.
[Prediction of total radiant flux and forward voltage]
FIG. 5 shows the relationship between the area ratio of the p electrode and the total radiant flux of the light emitting element, and FIG. 6 shows the relationship between the area ratio of the n electrode and the total radiant flux. FIG. 7 shows the relationship between current density and external quantum efficiency.
In the light emitting element 1 shown in the first embodiment, the ratio of the total area of the plurality of p electrodes 40 to the total area in the plan view of the light emitting element 1 (hereinafter referred to as “p electrode area ratio”) is variously changed. The total radiant flux of the light emitting element 1 (see FIG. 5) and the ratio of the total area of the plurality of n electrodes 42 to the total area of the light emitting element 1 in plan view (hereinafter referred to as “n electrode area ratio”) The total radiant flux (see FIG. 6) of the light-emitting element 1 in various cases was measured.
As can be seen with reference to FIGS. 5 and 6, the total radiant flux of the light-emitting element 1 linearly decreased as the p-electrode area ratio and the n-electrode area ratio increased. Further, as can be seen with reference to FIG. 7, it was shown that the external quantum efficiency fluctuates according to a quadratic function of current density.
From the above, based on the p-electrode area ratio, n-electrode area ratio, external quantum efficiency, emission wavelength, input current value, it is possible to accurately predict the total radiant flux of the light-emitting element 1, p-electrode area ratio, and / or It was shown that the light emitting device 1 having a desired total radiant flux can be obtained by adjusting the n electrode area ratio. Moreover, the knowledge that the light emitting element 1 of a desired forward voltage can also be obtained was acquired. That is, the forward voltage of the light emitting element 1 is predicted from the contact resistance of the p electrode 40, the resistance between the p electrode 40 and the n electrode 42, the contact resistance of the n electrode 42, and the resistance of the p wiring 70 and the n wiring 72. The knowledge that it can do was obtained.
FIG. 8A is a diagram illustrating a state at the time of light emission of the light emitting element 1 according to the first embodiment, and FIG. 8B is a diagram in which the number of p electrodes and n electrodes of the light emitting element 1 is changed. FIG. 8C is a diagram illustrating a light emitting element according to Modification Example 1 during light emission. FIG. 8C illustrates the light emitting element according to Modification Example 2 in which the number of p electrodes and n electrodes is changed. It is a figure which shows a state.
9A shows a comparison between the predicted value of the luminous intensity with respect to the input current to the light emitting element 1 and an actual measurement value, and FIG. 9B shows a comparison between the predicted value of the forward voltage with respect to the input current to the light emitting element 1 and the actual measurement value. Show.
When a current of 350 mA was injected into the light-emitting element 1 (however, the emission wavelength was 456 nm), the luminous intensity was predicted to be 344 mW, and the forward voltage was predicted to be 3.14V. When actually measured, the luminous intensity when a current of 350 mA was injected was 353.3 mW and the forward voltage was 3.13 V, which was in good agreement with the prediction. As for other current values, as shown in FIGS. 9A and 9B, the prediction and the actual measurement were in good agreement. In FIG. 9B, when the input current is 1000 mA, the prediction and the actual measurement are slightly different from each other, but this difference is considered to be the influence of heat generated by applying a large current.
10A shows a comparison between the predicted value of the luminous intensity with respect to the input current to the modification 1 of the light-emitting element 1 and the actual measurement value, and FIG. 10B shows the prediction of the forward voltage with respect to the input current to the modification 1 of the light-emitting element 1. The comparison between the measured value and the actual value is shown.
When a current of 350 mA was injected into Modification 1 of the light-emitting element 1 (however, the emission wavelength was 455.7 nm), the luminous intensity was predicted to be 335 mW, and the forward voltage was predicted to be 3.08V. When actually measured, the luminous intensity when a current of 350 mA was injected was 344.6 mW and the forward voltage was 3.06 V, which was in good agreement with the prediction. As for other current values, as shown in FIGS. 10A and 10B, the prediction and the actual measurement were in good agreement. In FIG. 10B, when the input current is 1000 mA, the prediction and the actual measurement are slightly different from each other, but this difference is considered to be the influence of heat generated by supplying a large current.
11A shows a comparison between the predicted value of the luminous intensity with respect to the input current to the modification 2 of the light-emitting element 1 and an actual measurement value, and FIG. 11B shows the prediction of the forward voltage with respect to the input current to the modification 2 of the light-emitting element 1. The comparison between the measured value and the actual value is shown.
When a current of 350 mA was injected into Modification 2 of Light-Emitting Element 1 (however, the emission wavelength was 455.4 nm), the luminous intensity was predicted to be 352 mW, and the forward voltage was predicted to be 3.29V. When actually measured, the luminous intensity when a current of 350 mA was injected was 362 mW and the forward voltage was 3.21 V, which was in good agreement with the prediction. As for other current values, as shown in FIGS. 11A and 11B, the prediction and the actual measurement were in good agreement.
1, 2, 3 Light-emitting element 5 Via 10 Sapphire substrate 20 Buffer layer 22 N-side contact layer 24 n-side cladding layer 25 Light-emitting layer 26 p-side cladding layer 28 p-side contact layer 30 Transparent conductive layer 40 p-electrode 42 n-electrode 50 Insulation Layer 50a, 50b Via 52 First insulating layer 54 Second insulating layer 60 Reflective layer 70 P wiring 70a Outer peripheral portion 70b P-side thin wire portion 71 P wiring 71a Outer peripheral portion 71b P-side connecting portion 71c Intermediate portion 71d P-side end portion 72 n Wiring 72a Side portion 72b N-side thin wire portion 73 n Wiring 73a Side portion 73b N-side end portion 73c n-side connection portion 73d Center portion 80 Insulating layer 80a, 80b Via 90 p-side bonding electrode 92 n-side bonding electrode 90a p-side cut 92a n side cut 200 mask 700 second plane conduction portion 702 second vertical conduction portion 720 first plane conduction portion 722 1 vertical conducting portion
A semiconductor multilayer structure made of a nitride compound semiconductor including a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type;
An insulating layer provided on the semiconductor multilayer structure;
A first vertical conduction portion extending in a vertical direction inside the insulating layer, the light emitting layer, and the second semiconductor layer; and a first planar conduction portion extending in a planar direction inside the insulation layer, A first wiring electrically connected to the semiconductor layer;
A second vertical conductive portion extending in the vertical direction inside the insulating layer; and a second planar conductive portion extending in the planar direction inside the insulating layer, and is electrically connected to the second semiconductor layer. A light emitting device comprising two wirings.
A first bonding electrode provided on the insulating layer and electrically connected to the first wiring;
The light emitting element according to claim 1, further comprising: a second bonding electrode provided on the insulating layer and electrically connected to the second wiring.
The light emitting device according to claim 2, wherein the insulating layer includes therein a reflective layer that reflects light emitted from the light emitting layer.
The light emitting device according to claim 3, wherein the first planar conducting portion and the second planar conducting portion are provided on the same plane.
The light emitting device according to claim 3, wherein the first planar conducting portion and the second planar conducting portion are provided on different planes.
The light emitting device according to claim 4, wherein the first bonding electrode and the second bonding electrode are provided on the same plane.
A first ohmic electrode in ohmic contact with the first semiconductor layer;
A transparent conductive layer in ohmic contact with the second semiconductor layer;
A second ohmic electrode in ohmic contact with the transparent conductive layer,
The first wiring is electrically connected to the first ohmic electrode,
The light emitting device according to claim 6, wherein the second wiring is electrically connected to the second ohmic electrode.
The light-emitting element according to claim 7, wherein a material constituting the first ohmic electrode and a material constituting the second ohmic electrode are the same.
The light emitting element according to claim 8, wherein a material constituting the first wiring is the same as a material constituting the second wiring.
The light emitting device according to claim 9, wherein each of the first bonding electrode and the second bonding electrode has a cut in a plan view.
JP2009217231A 2009-09-18 2009-09-18 Light emitting element Active JP5152133B2 (en)
JP2009217231A JP5152133B2 (en) 2009-09-18 2009-09-18 Light emitting element
KR20100088640A KR101091403B1 (en) 2009-09-18 2010-09-10 Light-emitting element
CN 201010280910 CN102024891B (en) 2009-09-18 2010-09-10 Light-emitting element
TW99131436A TWI434438B (en) 2009-09-18 2010-09-16 Light-emitting element
US12/923,384 US8247823B2 (en) 2009-09-18 2010-09-17 Light-emitting element
JP2011066304A JP2011066304A (en) 2011-03-31
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