Source: http://www.google.com/patents/US6996009?dq=5,889,522
Timestamp: 2014-08-21 12:41:31
Document Index: 359105063

Matched Legal Cases: ['art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1']

Patent US6996009 - NOR flash memory cell with high storage density - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsStructures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region...http://www.google.com/patents/US6996009?utm_source=gb-gplus-sharePatent US6996009 - NOR flash memory cell with high storage densityAdvanced Patent SearchPublication numberUS6996009 B2Publication typeGrantApplication numberUS 10/177,483Publication dateFeb 7, 2006Filing dateJun 21, 2002Priority dateJun 21, 2002Fee statusPaidAlso published asUS7113429, US7348237, US7476586, US20030235079, US20050082599, US20050085040, US20070015331Publication number10177483, 177483, US 6996009 B2, US 6996009B2, US-B2-6996009, US6996009 B2, US6996009B2InventorsLeonard ForbesOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (103), Non-Patent Citations (79), Referenced by (10), Classifications (26), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetNOR flash memory cell with high storage densityUS 6996009 B2Abstract Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.
a vertical floating gate transistor extending outwardly from a substrate, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a sourceline formed in a trench adjacent to the vertical floating gate transistor, wherein the first source/drain region is coupled to the sourceline; a transmission line coupled to the second source/drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate such that the programmed floating gate transistor operates at reduced drain source current. 2. The NOR flash memory cell of claim 1, wherein the first source/drain region of the floating gate transistor includes a source region and the second source/drain region of the floating gate transistor includes a drain region.
a vertical floating gate transistor formed according to a modified DRAM fabrication process, the floating gate transistor having a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a wordline coupled to the control gate; a sourceline formed in a trench adjacent to the vertical floating gate transistor, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate. 6. The NOR flash memory cell of claim 5, wherein the gate insulator has a thickness of at least 10 nanometers (nm).
a number of NOR flash memory cells extending from a substrate and separated by trenches, wherein each flash memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator, and a control gate separated from the floating gate by a second gate insulator; a number of bit lines coupled to the second source/drain region of each flash memory cell along rows of the memory array; a number of word lines coupled to the control gate of each flash memory cell along columns of the memory array; a number of sourcelines along rows in the trenches between the number of flash memory cells extending from a substrate, wherein the first source/drain region of each flash memory cell is coupled to the number of sourcelines; and wherein at least one of the flash memory cells is a programmed cell having a charge trapped in the floating gate. 8. The memory array of claim 7, wherein each NOR flash memory cell includes a vertical NOR flash memory cell.
a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a programmed cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couples to the sourceline in a shared trench. 12. The memory array of claim 11, wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates on opposing sides of the trench opposing the channel regions in column adjacent pillars.
a NOR memory array, wherein the memory array includes a number of vertical NOR flash cells extending outwardly from a substrate and separated by trenches, wherein each NOR flash cell includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a first gate insulator, and a control gate separated from the floating gate by a second gate insulator; a number of bitlines coupled to the drain region of each vertical NOR flash cell along rows of the memory array; a number of wordlines coupled to the control gate of each vertical NOR flash cell along columns of the memory array; a number of sourcelines, wherein the first source/drain region of each vertical NOR flash cell is integrally formed with the number of sourcelines along rows in the trenches between the number of vertical NOR flash cells extending from a substrate; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; and one or more sense amplifiers coupled to the number of bitlines. 23. The memory device of claim 22, wherein the first gate insulator of each NOR flash cell has a thickness of approximately 10 nanometers (nm).
a processor; and a memory device coupled to the processor, wherein the memory device includes a NOR memory array, the NOR memory array including; a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein each vertical pillar comprises a pair of floating gate transistors on opposing sides of each pillar, including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the pillars the trench between column adjacent pillars include a pair of floating gates each one opposing the channel regions of the pillar on a respective side of the trench; a number of bit lines coupled to the second source/drain region of each floating gate transistor along rows of the memory array; a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along rows of the pillars the first source/drain region of each floating gate transistor in column adjacent pillars couples to the sourceline in a shared trench such that each floating gate transistor neighboring the shared trench shares a common sourceline; and wherein at least one of floating gate transistors is a programmed flash cell. 27. The electronic system of claim 26, wherein the programmed flash cell includes a charge of approximately 100 electrons trapped on the floating gate of the programmed flash cell.
CROSS REFERENCE TO RELATED APPLICATIONS This application is related to the following co-pending, commonly assigned U.S. patent applications: �Write Once Read Only Memory Employing Floating Gates,� Ser. No. 10/177,083, �Write Once Read Only Memory Employing Charge Trapping in Insulators,� Ser. No. 10/177,077, �Ferroelectric Write Once Read Only Memory for Archival Storage,� Ser. No. 10/177,082, �Nanocrystal Write Once Read Only Memory for Archival Storage,� Ser. No. 10/177,214, �Write Once Read Only Memory with Large Work Function Floating Gates,� Ser. No. 10/177,213, �Vertical NROM Having a Storage Density of 1 Bit per 1 F2,� Ser. No. 10/177,208, and �Multistate NROM Having a Storage Density Much Greater than 1 Bit per 1F2,� Ser. No. 10/177,211, each of which disclosure is herein incorporated by reference.
FIELD OF THE INVENTION The present invention relates generally to semiconductor integrated circuits and, more particularly, to NOR flash memory cells with high storage density.
REFERENCES B. Dipert and L. Hebert, �Flash Memory goes Mainstream,� IEEE Spectrum, No. 10, pp. 48-52, (October 1993);
R. Goodwins, �New Memory Technologies on the Way,� http://zdnet.com.com/2100-1103-846950.html;
R. Shirota et al., �A 2.3 mu2 memory cell structure for 16 Mb NAND EEPROMs,� Digest of IEEE Int. Electron Device Meeting, San Francisco, 1990, pp. 103-106);
L. Forbes and K. Ahn, �Flash Memory with Ultrathin Vertical Body Transistors,� U.S. Pat. No. 6,424,001.
SUMMARY OF THE INVENTION The above mentioned problems for creating DRAM technology compatible flash memory cells as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. This disclosure describes a high speed NOR type flash memory cell and arrays with high density. Two transistors occupy an area of 4 F squared when viewed from above, or each memory cell consisting of one transistor has an area of 2 F squared. NAND flash memories are ideally as small as 4 F squared in conventional planar device technology, with practical devices having a cell area of 5 F squared. The vertical NOR flash memory cells described here have a higher density than conventional planar NAND cells but they would operate at speeds higher than or comparable to conventional planar NOR flash memories. The NOR flash memories described here then have both high density and high speed.
The inventor, along with others, has previously described programmable memory devices and functions based on the reverse stressing of MOSFET's in a conventional CMOS process and technology in order to form programmable address decode and correction in U.S. Pat. No. 6,521,950 entitled �MOSFET Technology for Programmable Address Decode and Correction.� That disclosure, however, did not describe write once read only memory solutions, but rather address decode and correction issues. The inventor also describes write once read only memory cells employing charge trapping in gate insulators for conventional MOSFETs and write once read only memory employing floating gates. The same are described in co-pending, commonly assigned U.S. patent applications, entitled �Write Once Read Only Memory Employing Charge Trapping in Insulators,� Ser. No. 10/177,077, and �Write Once Read Only Memory Employing Floating Gates,� Ser. No. 10/177,083. The present application, however, describes NOR flash cells formed from conventional flash memory device structures.
Some of these effects have recently been described for use in a different device structure, called an NROM, for flash memories. This latter work in Israel and Germany is based on employing charge trapping in a silicon nitride layer in a non-conventional flash memory device structure. Charge trapping in silicon nitride gate insulators was the basic mechanism used in MNOS memory devices charge trapping in aluminum oxide gates was the mechanism used in MIOS memory devices and the present inventor, along with another, disclosed charge trapping at isolated point defects in gate insulators in U.S. Pat. No. 6,140,181 entitled �Memory Using Insulator Traps.� However, none of the above described references addressed forming NOR flash memory cells.
FIG. 5E illustrates another embodiment of the present invention's floating gate and control gate configuration. As shown in the embodiment of FIG. 5E, a single floating gate 509 is formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. According to the teachings of the present invention, the single floating gate 509 can be either a vertically oriented floating gate 509 or a horizontally oriented floating gate 509 formed by conventional processing techniques, or can be a horizontally oriented floating gate 509 formed by a replacement gate technique such as described in a copending application, entitled �Flash Memory with Ultrathin Vertical Body Transistors,� by Leonard Forbes and Kie Y. Ahn, application Ser. No. 09/780,169, now U.S. Pat. No. 6,424,001. The same is incorporated herein in full. In one embodiment of the present invention, the floating gate 509 has a vertical length facing the channel regions 505-1 and 505-2 of less than 100 nm. In another embodiment, the floating gate 509 has a vertical length facing the channel regions 505-1 and 505-2 of less than 50 nm. In one embodiment, as shown in FIG. 5E, the floating gate 509 is shared, respectively, with the body regions 507-1 and 507-2, including channel regions 505-1 and 505-2, in adjacent pillars 500-1 and 500-2 located on opposing sides of the trench 530.
FIGS. 6A-B and 7 are useful in illustrating the use of charge storage in the floating gate to modulate the conductivity of the NOR flash memory cell according to the teachings of the present invention. That is, FIGS. 6A-6B illustrates the operation of the novel NOR flash memory cell 601 formed according to the teachings of the present invention. And, FIG. 7 illustrates the operation of a conventional DRAM cell 501. As shown in FIG. 7, the gate insulator 702 is made thicker than in a conventional DRAM cell. For example, an embodiment of the gate insulator 610 has a thickness 611 equal to or greater than 10 nm or 100 Å (10−6 cm). In the embodiment shown in FIG. 7A a NOR flash memory cell has dimensions 613 of 0.1 μm (10−5 cm) by 0.1 μm. The capacitance, Ci, of the structure depends on the dielectric constant, ∈i, and the thickness of the insulating layers, t. In an embodiment, the dielectric constant is 0.3�10−12 F/cm and the thickness of the insulating layer is 10−6 cm such that Ci=∈i/t, Farads/cm2 or 3�10−7 F/cm2. In one embodiment, a charge of 1012 electron/cm2 is programmed into the floating gate of the NOR flash memory cell. This produces a stored charge Δ Q=1012 electrons/cm2�1.6�10−19 Coulombs. In this embodiment, the resulting change in the threshold voltage (Δ Vt) of the NOR flash memory cell will be approximately 0.5 Volts (Δ Vt=Δ Q/Ci or 1.6�10−7/3�10−7=� Volt). For Δ Q=1012 electrons/cm3 in an area of 10−10 cm2, this embodiment of the present invention involves trapping a charge of approximately 100 electrons in the floating gate of the NOR flash memory cell. In this embodiment, an original VT is approximately � Volt and the VT with charge trapping is approximately 1 Volt.
FIG. 6B aids to further illustrate the conduction behavior of the novel NOR flash memory cell of the present invention. As one of ordinary skill in the art will understand upon reading this disclosure, if the NOR flash memory cell is being driven with a control gate voltage of 1.0 Volt (V) and the nominal threshold voltage without the floating gate charged is � V, then if the floating gate is charged the floating gate transistor of the present invention will be off and not conduct. That is, by trapping a charge of approximately 100 electrons in the floating gate of the NOR flash memory cell, having dimensions of 0.1 μm (10−5 cm) by 0.1 μm, will raise the threshold voltage of the NOR flash memory cell to 1.0 Volt and a 1.0 Volt control gate potential will not be sufficient to turn the device on, e.g. Vt=1.0 V, I=0.
Conversely, if the nominal threshold voltage without the floating gate charged is � V, then I=μCox�(W/L)�((Vgs−Vt)2/2), or 12.5 μA, with μCox=μCi=100 μA/V2 and W/L=1. That is, the NOR flash memory cell of the present invention, having the dimensions describe above will produce a current I=100 μA/V2�(�)�(�)=12.5 μA. Thus, in the present invention an un-written, or un-programmed NOR flash memory cell can conduct a current of the order 12.5 μA, whereas if the floating gate is charged then the NOR flash memory cell will not conduct. As one of ordinary skill in the art will understand upon reading this disclosure, the sense amplifiers used in DRAM arrays, and as describe above, can easily detect such differences in current on the bit lines.
By way of comparison, in a conventional DRAM cell 750 with 30 femtoFarad (fF) storage capacitor 751 charged to 50 femto Coulombs (fC), if these are read over 5 nS then the average current on a bit line 752 is only 10 μA (I=50 fC/5 ns=10 μA). Thus, storing a 50 fC charge on the storage capacitor equates to storing 300,000 electrons (Q=50 fC/(1.6�10−19)=30�104=300,000 electrons).
According to the teachings of the present invention, the floating gate transistors in the array are utilized not just as passive on or off switches as transfer devices in DRAM arrays but rather as active devices providing gain. In the present invention, to program the floating gate transistor �off,� requires only a stored charge in the floating gate of about 100 electrons if the area is 0.1 μm by 0.1 μm. And, if the NOR flash memory cell is un-programmed, e.g. no stored charge trapped in the floating gate, and if the floating gate transistor is addressed over 10 nS a of current of 12.5 μA is provided. The integrated drain current then has a charge of 125 fC or 800,000 electrons. This is in comparison to the charge on a DRAM capacitor of 50 fC which is only about 300,000 electrons. Hence, the use of the floating gate transistors in the array as active devices with gain, rather than just switches, provides an amplification of the stored charge, in the floating gate, from 100 to 800,000 electrons over a read address period of 10 nS.
CONCLUSION Two transistors occupy an area of 4 F squared when viewed from above, or each memory cell consisting of one transistor has an area of 2 F squared. NAND flash memories are ideally as small as 4 F squared in conventional planar device technology, with practical devices having a cell area of 5 F squared. The vertical NOR flash memory cells described here have a higher density than conventional planar NAND cells but they would operate at speeds higher than or comparable to conventional planar NOR flash memories. The NOR flash memories described here then have both high density and high speed.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3641516Sep 15, 1969Feb 8, 1972IbmWrite once read only store semiconductor memoryUS3665423Mar 13, 1970May 23, 1972Nippon Electric CoMemory matrix using mis semiconductor elementUS3877054Nov 8, 1973Apr 8, 1975Bell Telephone Labor IncSemiconductor memory apparatus with a multilayer insulator contacting the semiconductorUS3964085Aug 18, 1975Jun 15, 1976Bell Telephone Laboratories, IncorporatedMethod for fabricating multilayer insulator-semiconductor memory apparatusUS4152627Jun 10, 1977May 1, 1979Monolithic Memories Inc.Low power write-once, read-only memory arrayUS4217601Feb 15, 1979Aug 12, 1980International Business Machines CorporationNon-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structureUS4507673Sep 21, 1983Mar 26, 1985Tokyo Shibaura Denki Kabushiki KaishaSemiconductor memory deviceUS4661833Oct 29, 1985Apr 28, 1987Kabushiki Kaisha ToshibaElectrically erasable and programmable read only memoryUS4888733Sep 12, 1988Dec 19, 1989Ramtron CorporationNon-volatile memory cell and sensing methodUS4939559Apr 1, 1986Jul 3, 1990International Business Machines CorporationDual electron injector structures using a conductive oxide between injectorsUS5021999Dec 9, 1988Jun 4, 1991Mitsubishi Denki Kabushiki KaishaNon-volatile semiconductor memory device with facility of storing tri-level dataUS5027171Aug 28, 1989Jun 25, 1991The United States Of America As Represented By The Secretary Of The NavyDual polarity floating gate MOS analog memory deviceUS5042011May 22, 1989Aug 20, 1991Micron Technology, Inc.Sense amplifier pulldown device with tailored edge inputUS5111430Jun 21, 1990May 5, 1992Nippon Telegraph And Telephone CorporationNon-volatile memory with hot carriers transmitted to floating gate through control gateUS5253196Jan 9, 1991Oct 12, 1993The United States Of America As Represented By The Secretary Of The NavyDual-writing-polarity, non-volatileUS5280205Apr 16, 1992Jan 18, 1994Micron Technology, Inc.Fast sense amplifierUS5293560Nov 3, 1992Mar 8, 1994Eliyahou HarariMulti-state flash EEPROM system using incremental programing and erasing methodsUS5298447Jul 22, 1993Mar 29, 1994United Microelectronics CorporationMethod of fabricating a flash memory cellUS5317535Jun 19, 1992May 31, 1994Intel CorporationGate/source disturb protection for sixteen-bit flash EEPROM memory arraysUS5388069Mar 18, 1993Feb 7, 1995Fujitsu LimitedNonvolatile semiconductor memory device for preventing erroneous operation caused by over-erase phenomenonUS5399516Sep 21, 1992Mar 21, 1995International Business Machines CorporationMethod of making shadow RAM cell having a shallow trench EEPROMUS5410504May 3, 1994Apr 25, 1995Ward; Calvin B.Memory based on arrays of capacitorsUS5424993Nov 15, 1993Jun 13, 1995Micron Technology, Inc.Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory deviceUS5430670Nov 8, 1993Jul 4, 1995Elantec, Inc.Differential analog memory cell and method for adjusting sameUS5434815Jan 19, 1994Jul 18, 1995Atmel CorporationStress reduction for non-volatile memory cellUS5438544Jan 28, 1994Aug 1, 1995Fujitsu LimitedNon-volatile semiconductor memory device with function of bringing memory cell transistors to overerased state, and method of writing data in the deviceUS5449941Oct 27, 1992Sep 12, 1995Semiconductor Energy Laboratory Co., Ltd.Semiconductor memory deviceUS5457649Aug 26, 1994Oct 10, 1995Microchip Technology, Inc.Semiconductor memory device and write-once, read-only semiconductor memory array using amorphous-silicon and method thereforUS5467306Oct 4, 1993Nov 14, 1995Texas Instruments IncorporatedMethod of using source bias to increase threshold voltages and/or to correct for over-erasure of flash epromsUS5477485Feb 22, 1995Dec 19, 1995National Semiconductor CorporationMethod for programming a single EPROM or FLASH memory cell to store multiple levels of data that utilizes a floating substrateUS5485422Jun 2, 1994Jan 16, 1996Intel CorporationMemory deviceUS5493140Jun 21, 1994Feb 20, 1996Sharp Kabushiki KaishaNonvolatile memory cell and method of producing the sameUS5508543Apr 29, 1994Apr 16, 1996International Business Machines CorporationLow voltage memoryUS5530581May 31, 1995Jun 25, 1996Eic Laboratories, Inc.Protective overlayer material and electro-optical coating using sameUS5530668Apr 12, 1995Jun 25, 1996Ramtron International CorporationFerroelectric memory sensing scheme using bit lines precharged to a logic one voltageUS5539279Dec 22, 1994Jul 23, 1996Hitachi, Ltd.Ferroelectric memoryUS5541871Jan 18, 1995Jul 30, 1996Rohm Co., Ltd.Nonvolatile ferroelectric-semiconductor memoryUS5541872May 26, 1995Jul 30, 1996Micron Technology, Inc.Folded bit line ferroelectric memory deviceUS5550770Jun 2, 1995Aug 27, 1996Hitachi, Ltd.Semiconductor memory device having ferroelectric capacitor memory cells with reading, writing and forced refreshing functions and a method of operating the sameUS5572459Sep 16, 1994Nov 5, 1996Ramtron International CorporationVoltage reference for a ferroelectric 1T/1C based memoryUS5600587Jan 29, 1996Feb 4, 1997Nec CorporationFerroelectric random-access memoryUS5627781Nov 8, 1995May 6, 1997Sony CorporationNonvolatile semiconductor memoryUS5627785Mar 15, 1996May 6, 1997Micron Technology, Inc.Memory device with a sense amplifierUS5670790Sep 19, 1996Sep 23, 1997Kabushikik Kaisha ToshibaElectronic deviceUS5714766Sep 29, 1995Feb 3, 1998International Business Machines CorporationNano-structure memory deviceUS5740104Jan 29, 1997Apr 14, 1998Micron Technology, Inc.Multi-state flash memory cell and method for programming single electron differencesUS5754477Jan 29, 1997May 19, 1998Micron Technology, Inc.Differential flash memory cell and method for programmingUS5768192Jul 23, 1996Jun 16, 1998Saifun Semiconductors, Ltd.Non-volatile semiconductor memory cell utilizing asymmetrical charge trappingUS5801401Jan 29, 1997Sep 1, 1998Micron Technology, Inc.Flash memory with microcrystalline silicon carbide film floating gateUS5828605Oct 14, 1997Oct 27, 1998Taiwan Semiconductor Manufacturing Company Ltd.Snapback reduces the electron and hole trapping in the tunneling oxide of flash EEPROMUS5852306Jan 29, 1997Dec 22, 1998Micron Technology, Inc.Flash memory with nanocrystalline silicon film floating gateUS5856688Sep 30, 1997Jan 5, 1999Samsung Electronics Co., Ltd.Integrated circuit memory devices having nonvolatile single transistor unit cells thereinUS5886368Jul 29, 1997Mar 23, 1999Micron Technology, Inc.Dielectric; reduce write and erase voltageUS5912488 *Jun 24, 1997Jun 15, 1999Samsung Electronics Co., LtdStacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programmingUS5916365Aug 16, 1996Jun 29, 1999Sherman; ArthurSequential chemical vapor depositionUS5936274Jul 8, 1997Aug 10, 1999Micron Technology, Inc.High density flash memoryUS5943262 *Oct 28, 1998Aug 24, 1999Samsung Electronics Co., Ltd.Non-volatile memory device and method for operating and fabricating the sameUS5959896Feb 27, 1998Sep 28, 1999Micron Technology Inc.Multi-state flash memory cell and method for programming single electron differencesUS5973356Jul 8, 1997Oct 26, 1999Micron Technology, Inc.Ultra high density flash memoryUS5989958Aug 20, 1998Nov 23, 1999Micron Technology, Inc.Flash memory with microcrystalline silicon carbide film floating gateUS5991225Feb 27, 1998Nov 23, 1999Micron Technology, Inc.Programmable memory address decode array with vertical transistorsUS6031263Jul 29, 1997Feb 29, 2000Micron Technology, Inc.DEAPROM and transistor with gallium nitride or gallium aluminum nitride gateUS6034882Nov 16, 1998Mar 7, 2000Matrix Semiconductor, Inc.Vertically stacked field programmable nonvolatile memory and method of fabricationUS6072209Jul 8, 1997Jun 6, 2000Micro Technology, Inc.Four F2 folded bit line DRAM cell structure having buried bit and word linesUS6115281Sep 11, 1998Sep 5, 2000Telcordia Technologies, Inc.Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitorsUS6124729Feb 27, 1998Sep 26, 2000Micron Technology, Inc.Field programmable logic arrays with vertical transistorsUS6125062Aug 26, 1998Sep 26, 2000Micron Technology, Inc.Single electron MOSFET memory device and methodUS6140181Sep 10, 1999Oct 31, 2000Micron Technology, Inc.Memory using insulator trapsUS6141237Jul 12, 1999Oct 31, 2000Ramtron International CorporationFerroelectric non-volatile latch circuitsUS6141238Aug 30, 1999Oct 31, 2000Micron Technology, Inc.Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including sameUS6141260Aug 27, 1998Oct 31, 2000Micron Technology, Inc.Single electron resistor memory device and method for use thereofUS6143636Aug 20, 1998Nov 7, 2000Micron Technology, Inc.High density flash memoryUS6150687Jul 8, 1997Nov 21, 2000Micron Technology, Inc.Memory cell having a vertical transistor with buried source/drain and dual gatesUS6153468May 17, 1999Nov 28, 2000Micron Technololgy, Inc.Method of forming a logic array for a decoderUS6166401Aug 20, 1998Dec 26, 2000Micron Technology, Inc.Flash memory with microcrystalline silicon carbide film floating gateUS6185122Dec 22, 1999Feb 6, 2001Matrix Semiconductor, Inc.Vertically stacked field programmable nonvolatile memory and method of fabricationUS6212103Jul 28, 1999Apr 3, 2001Xilinx, Inc.Method for operating flash memoryUS6232643Nov 13, 1997May 15, 2001Micron Technology, Inc.Memory using insulator trapsUS6238976Feb 27, 1998May 29, 2001Micron Technology, Inc.Method for forming high density flash memoryUS6243300Feb 16, 2000Jun 5, 2001Advanced Micro Devices, Inc.Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cellUS6246606Sep 2, 1999Jun 12, 2001Micron Technology, Inc.Memory using insulator trapsUS6249020Aug 27, 1998Jun 19, 2001Micron Technology, Inc.DEAPROM and transistor with gallium nitride or gallium aluminum nitride gateUS6252793Sep 15, 2000Jun 26, 2001Ramtron International CorporationReference cell configuration for a 1T/1C ferroelectric memoryUS6269023Oct 23, 2000Jul 31, 2001Advanced Micro Devices, Inc.Method of programming a non-volatile memory cell using a current limiterUS6294813Feb 15, 2000Sep 25, 2001Micron Technology, Inc.Information handling system having improved floating gate tunneling devicesUS6313518Mar 2, 2000Nov 6, 2001Micron Technology, Inc.Porous silicon oxycarbide integrated circuit insulatorUS6337805Dec 15, 1999Jan 8, 2002Micron Technology, Inc.Discrete devices including EAPROM transistor and NVRAM memory cell with edge defined ferroelectric capacitance, methods for operating same, and apparatuses including sameUS6351411Jun 12, 2001Feb 26, 2002Micron Technology, Inc.Memory using insulator trapsUS6407435Feb 11, 2000Jun 18, 2002Sharp Laboratories Of America, Inc.Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced.US6438031Oct 26, 2000Aug 20, 2002Advanced Micro Devices, Inc.Method of programming a non-volatile memory cell using a substrate biasUS6445030Jan 30, 2001Sep 3, 2002Advanced Micro Devices, Inc.Flash memory erase speed by fluorine implant or fluorinationUS6449188 *Jun 19, 2001Sep 10, 2002Advanced Micro Devices, Inc.Low column leakage nor flash array-double cell implementationUS6456531Jun 19, 2001Sep 24, 2002Advanced Micro Devices, Inc.Method of drain avalanche programming of a non-volatile memory cellUS6456536Jun 19, 2001Sep 24, 2002Advanced Micro Devices, Inc.Method of programming a non-volatile memory cell using a substrate biasUS6459618Jun 13, 2001Oct 1, 2002Advanced Micro Devices, Inc.Method of programming a non-volatile memory cell using a drain biasUS6487121Jul 5, 2001Nov 26, 2002Advanced Micro Devices, Inc.Method of programming a non-volatile memory cell using a vertical electric fieldUS6498362Aug 26, 1999Dec 24, 2002Micron Technology, Inc.Weak ferroelectric transistorUS6504755May 14, 1999Jan 7, 2003Hitachi, Ltd.Semiconductor memory deviceUS6514828Apr 20, 2001Feb 4, 2003Micron Technology, Inc.Method of fabricating a highly reliable gate oxideUS6521911Jul 19, 2001Feb 18, 2003North Carolina State UniversityHigh dielectric constant metal silicates formed by controlled metal-surface reactionsUS6521950Mar 1, 2002Feb 18, 2003The United States Of America As Represented By The Secretary Of The NavyUltra-high resolution liquid crystal display on silicon-on-sapphireUS6521958Aug 26, 1999Feb 18, 2003Micron Technology, Inc.MOSFET technology for programmable address decode and correctionUS6570787 *Apr 19, 2002May 27, 2003Advanced Micro Devices, Inc.Programming with floating source for low power, low leakage and high density flash memory devices* Cited by examinerNon-Patent CitationsReference1Aarik, Jaan , et al., "Phase transformations in hafnium dioxide thin films grown by atomic layer dopositlon at high temperatures", Applied Surface Science, 173(1-2), (Mar. 2001),15-21.2Abbas, S. A., et al., "N-Channel Igfet Design Limitations Due to Hot Electron Trapping", Technical Digest, International Electron Devices Meeting,, Washington, DC,(Dec. 1975),35-38.3Adelmann, C , et al., "Atomic-layer epitaxy of GaN quantum wells and quantum dots on (0001) AlN", Journal of Applied Physics, 91(8), (Apr. 15, 2002),5498-5500.4Ahn, Seong-Deok , et al., "Surface Morphology Improvement of Metalorganic Chemical Vapor Deposition Al Films by Layered Deposition of Al and Ultrathin TiN", Japanese Journal of Applied Physics, Part 1 (Regular Papers, Short Notes & Review Papers), 39(6A), (Jun. 2000),3349-3354.5Akasaki, I. , "Effects of AlN Buffer Layer on Crystallographic Structure and on Electrical and Optical Properties of GaN and Ga(1-x)Al(x)N [0<x (<or =) 0.4] Films Grown on Sapphire Substrate by MOVPE", Journal of Crystal Growth, 98, (1989),209-219.6Alen, Petra , et al., "Atomic Layer Deposition of Ta(Al)N(C) Thin Films Using Trimethylaluminum as a Reducing Agent", Journal of the Electrochemical Society, 148(10), (Oct. 2001),G566-G571.7Asari, K , et al., "Multi-mode and multi-level technologies for FeRAM embedded reconfigurable hardware", Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International, (Feb. 15-17, 1999),106-107.8Benjamin, M. , "UV Photoemission Study of Heteroepitaxial AlGaN Films Grown on 6H-SiC", Applied Surface Science, 104/105, (Sep. 1996),455-460.9Bermudez, V. , "The Growth and Properties of Al and AlN Films on GaN(0001)-(1x1)", Journal of Applied Physics, 79(1), (Jan. 1996),110-119.10Britton, J , et al., "Metal-nitride-oxide IC memory retains data for meter reader", Electronics, 45(22), (Oct. 23, 1972),119-23.11Carter, R J., "Electrical Characterization of High-k Materials Prepared By Atomic Layer CVD", IWGI, (2001),94-99.12Chae, Junghun , et al., "Atomic Layer Deposition of Nickel by the Reduction of Preformed Nickel Oxide", Electrochemical & Solid-State Letters, 5(6), (Jun. 2002),C64-C66.13Chaitsak, Suticai ,et al., "Cu(InGa)Se/sub 2/ thin-film solar cells with high resistivity ZnO buffer layers deposited by atomic layer deposition", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 38(9A), (Sep. 1999),4989-4992.14Chang, C. , "Novel Passivation Dielectrics-The Boron- or Phosphorus-Doped Hydrogenated Amorphous Silicon Carbide Films", Journal of the Electrochemical Society, 132, (Feb. 1985),418-422.15Cricchi, J R., et al., "Hardened MNOS/SOS electrically reprogrammable nonvolatile memory", IEEE Transactions on Nuclear Science, 24(6), (Dec. 1977),2185-9.16Demichelis, F. , "Influence of Doping on the Structural and Optoelectronic Properties of Amorphous and Microcrystalline Silicon Carbide", Journal of Applied Physics, 72, (Aug. 15, 1992),1327-1333.17Demichelis, F. , "Physical Properties of Undoped and Doped Microcrystalline SiC:H Deposited By PECVD", Materials Research Society Symposium Proceedings, 219, Anaheim, CA,(Apr. 30-May 3, 1991),413-418.18Desu, S B., "Minimization of Fatigue in Ferroelectric Films", Physica Status Solidi A, 151(2), (1995),467-480.19Dimaria, D J., "Graded or stepped energy band-gap-insulator MIS structures (GI-MIS or SI-MIS)", Journal of Applied Physics, 50(9), (Sep. 1979),5826-5829.20Dipert, Brian, "Flash Memory Goes Mainstream", IEEE Spectrum, 30(10), (Oct. 1993),48-52.21Eitan, Boaz , "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell", IEEE Electron Device Letters, 21(11), (Nov. 2000),543-545.22Elam, J W., "Kinetics of the WF6 and Si2H6 surface reactions during tungsten atomic layer deposition", Surface Science, 479(1-3), (May 2001),121-135.23Fauchet, P M., et al., "Optoelectronics and photovoltaic applications of microcrystalline SiC", Symp. on Materials Issues in Mecrocrystalline Semiconductors, (1989),291-292.24Ferris-Prabhu, A V., "Amnesia in layered insulator FET memory devices", 1973 International Electron Devices Meeting Technical Digest, (1973),75-77.25Ferris-Prabhu, A V., "Charge transfer in layered insulators", Solid-State Electronics, 16(9), (Sep. 1973),1086-7.26Ferris-Prabhu, A V., "Tunnelling theories of non-volatile semiconductor memories", Physica Status Solidi A, 35(1), (May 16, 1976),243-50.27Fisch, D E., et al., "Analysis of thin film ferroelectric aging", Proc. IEEE Int. Reliability Physics Symp., (1990),237-242.28Forbes, L. , et al., "Field Induced Re-Emission of Electrons Trapped in SiO", IEEE Transactions on Electron Devices, ED-26 (11), Briefs,(Nov. 1979),1816-1818.29Forsgren, Katarina, "Atomic Layer Deposition of HfO2 using hafnium iodide", Conference held in Monterey, California, (May 2001), 1 page.30Frohman-Bentchkowky, D , "An integrated metal-nitride-oxide-silicon (MNOS) memory", Proceedings of the IEEE, 57(6), (Jun. 1969),1190-1192.31Goodwins, Rupert , "New Memory Technologies on the Way", http://zdnet.com.com/2100-1103-846950.html, (Feb. 2002).32Hwang, C G., "Semiconductor Memories for the IT Era", 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers IEEE. Part vol. 1, San Francisco,(2002),24-27.33Hwang, N. , et al., "Tunneling and Thermal Emission of Electrons from a Distribution of Deep Traps in SiO", IEEE Transactions on Electron Devices, 40(6), (Jun. 1993),1100-1103.34Iddles, D M., et al., "Relationships between dopants, microstructure and the microwave dielectric properties of ZrO2-TiO2-SnO2 ceramics", Journal of Materials Science, 27(23), (Dec. 1992),6303-6310.35Juppo, Marika , et al., "Use of 1,1Dimethylhydrazine in the Atomic Layer Deposition of Transition Metal Nitride Thin Films", Journal of the Electrochemical Society, 147(9), (Sep. 2000),3377-3381.36Kim, Y , et al., "Substrate dependence on the optical properties of Al/sub 2/O/sub 3/ films grown by atomic layer deposition", Applied Physics Letters, 71(25, 22 ), (Dec. 1997),3604-3606.37Klaus, J W., et al., "Atomic layer deposition of tungsten nitride films using sequential surface reactions", Journal of the Electrochemical Society, 147(3), (Mar. 2000),1175-81.38Koo, J , "Study on the characteristics of TiAlN thin film deposited by atomic layer deposition method", Journal of Vacuum Science & Technology A-Vacuum Surfaces & Films, 19(6), (Nov. 2001),2831-4.39Kukli, K , et al., "Tailoring the dielectric properties of HfO2-Ta2O3 nanolaminates", Appl. Phys. Lett., 68, (1996),3737-3739.40Lee, L P., et al., "Monolithic 77 K dc SQUID magnetometer", Applied Physics Letters, 59(23), (Dec. 1991),3051-3053.41Lei, T. , "Epitaxial Growth and Characterization of Zinc-Blende Gallium Nitride on (001) Silicon", Journal of Applied Physics, 71(10), (May 1992),4933-4943.42Luan, H. , "High Quality Ta2O5 Gate Dielectrics with Tox,eq<10A",IEDM, (1999),pp. 141-144.43Lusky, Eli, et al., "Characterization of channel hot electron injection by the subthreshold slope of NROM/sup TM/ device", IEEE Electron Device Letters, 22(11). (Nov. 2001),556-55844Maayan, Eduardo , et al., "A 512Mb NROM Flash Data Storage Memory with 8MB/s Data Rate", Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC, (2002),100-101.45Marlid, Bjorn , et al., "Atomic layer deposition of BN thin films", Thin Solid Films, 402(1-2), (Jan. 2002),167-171.46Martins, R , "Transport Properties of Doped Silicon Oxycarbide Microcrystalline Films Produced by Spatial Separation Techniques", Solar Energy Materials and Solar Cells, 41-42, (1996),493-517.47Martins, R. , "Wide Band Gap Microcrystalline Silicon Thin Films", Diffusion and Defect Data : Solid State Phenomena, 44-46, Part 1, Scitec Publications,(1995),299-346.48Min, J. , "Metal-organic atomic-layer deposition of titanium-silicon-nitride films", Applied Physics Letters, 75(11), (1999), 1521-1523.49Min, Jae-Sik , et al., "Atomic layer deposition of TiN films by alternate supply of tetrakis (ethylmethylamino)-titanium and ammonia", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, vol. 37, No. 9A, (Sep. 1998),4999-5004.50Moazzami, R , "Endurance properties of Ferroelectric PZT thin films", Int. Electron Devices Mtg., San Francisco,(1990),417-20.51Moazzami, R , "Ferroelectric PZT thin films for semiconductor memory", Ph.D Thesis, University of California, Berkeley, (1991).52Molnar, R. , "Growth of Gallium Nitride by Electron-Cyclotron Resonance Plasma-Assisted Molecular-Beam Epitaxy: The Role of Charged Species", Journal of Applied Physics, 76(8), (Oct. 1994),4587-4595.53Morishita, S , "Atomic-layer chemical-vapor-deposition of SiO/sub 2/ by cyclic exposures of CH/sub 3/OSi(NCO)/sub 3/ and H/sub 2/O/sub 2/", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, vol. 34, No. 10, (Oct. 1995),5738-42.54Moriwaki, M , "Improved metal gate process by simultaneous gate-oxide nitridation during W/WN/sub x/gate formation", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 39(4B), (Apr. 2000),2177-2180.55Nakajima, Anri , "Soft breakdown free atomic-layer-deposited silicon-nitride/SiO/sub 2/ stack gate dielectrics", International Electron Devices Meeting. Technical Digest, (2001),6.5.1-4.56Niilisk, A , "Atomic-scale optical monitoring of the initial growth of TiO2 thin films", Proceedings of the SPIE-The International Society for Optical Engineering, 4318, (2001),72-77.57Pankove, J. , "Photoemission from GaN", Applied Physics Letters, 25, (1974),53-55.58Papadas, C. , "Modeling of the Intrinsic Retention Charcteristics of FLOTOX EEPROM Cells Under Elevated Temperature Conditions", IEEE Transaction on Electron Devices, 42, (Apr. 1995),678-682.59Park, Jin-Seong , et al., "Plasma-Enhanced Atomic Layer Deposition of Tantalum Nitrides Using Hydrogen Radicals as a Reducing Agent", Electrochemical & Solid-State Letters, 4(4), (Apr. 2001),C17-19.60Puurunen, R L., et al., "Growth of aluminum nitride on porous silica by atomic layer chemical vapour deposition", Applied Surface Science, 165(2-3), (Sep. 12, 2000),193-202.61Renlund, G. M., "Silicon oxycarbide glasses: Part I. Preparation and chemistry", J. Mater. Res., (Dec., 1991),pp. 2716-2722.62Robertson, J. , "Band offsets of wide-band-gap oxides and implications for future electronic devices", Journal of Vacuum Science & Technology B (Microelectronics and Nanometer Structures), 18(3), (May-Jun. 2000),1785-1791.63Sanders, B W., et al., "Zinc Oxysulfide Thin Films Grown by Atomic Layer Deposition", Chemistry of Materials, 4(5), (1992),1005-1011.64She, Min , et al., "Modeling and design study of nanocrystal memory devices", IEEE Device Research Conference, (2001),139-40.65Shimada, H , et al., "Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum layer", IEEE Transactions on Electron Devices, vol. 48, No. 8, (Aug. 200),1619-1626.66Shin, Chang H., et al., "Fabriation and Characterization of MFISFET Using Al2O3 Insulating Layer for Non-volatile Memory", 12th International Symposium in Integrated Ferroelectrics, (Mar. 2000),9 pages.67Shirota, R , et al., "A 2.3 mu m/sup 2/ memory cell structure for 16 Mb NAND EEPROMs", International Electron Devices Meeting 1990. Technical Digest, San Francisco,(1990),103-106.68Sneh, Ofer , et al., "Thin film atomic layer deposition equipment for semiconductor processing", Thin Solid Films, 402(1-2), (Jan. 1, 2002),248-261.69Solanki, Raj , et al., "Atomic Layer Deposition of Copper Seed Layers", Electrochemical & Solid-State Letters, 3(10), (Oct. 2000),479-450.70Sze, S M., "Physics of semiconductor devices", New York: Wiley, (1981),504-506.71Wei, L S., et al., "Trapping, emission and generation in MNOS memory devices", Solid-State Electronics, 17(6), (Jun. 1974),591-8.72White, M H., "Characterization of thin-oxide MNOS memory transistors", IEEE Transactions on Electron Devices, ED-19(12), (Dec. 1972),1280-1288.73White, M H., "Direct tunneling in metal-nitride-oxide-silicon (MNOS) structures", Programmme of the 31st physical electronics conference, (1971),1.74Wilk, G. D., et al., "High-K gate dielectrics: Current status and materials properties considerations", Journal of Applied Physics, 89(10), (2001),5243-5275.75Wood, S W., "Ferroelectric memory design", M.A.Sc. thesis, University of Toronto, (1992).76Yagishita, A , "Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) with low threshold voltage, high drive current and uniform electrical characteristics", International Electron Devices Meeting 2000. Technical Digest. IEDM, (Dec. 2000), 1633-1636.77YODER, M, "Wide Bandgap Semiconductor Materials and Devices", IEEE Transactions on Electron Devices, 43, (Oct. 1996),1633-1636.78Zhu, W J., et al., "Current transport in metal/hafnium oxide/silicon structure", IEEE Electron Device Letters, 23, (2002),97-99.79Zhu. W , et al., "HfO2 and HfAlO for CMOS: Thermal Stability and Current Transport", IEEE International Electron Device Meeting 2001, (2001),463-466.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7190616 *Jul 19, 2004Mar 13, 2007Micron Technology, Inc.In-service reconfigurable DRAM and flash memory deviceUS7271052 *Dec 19, 2006Sep 18, 2007Micron Technology, Inc.Long retention time single transistor vertical memory gain cellUS7476586 *Jul 20, 2006Jan 13, 2009Micron Technology, Inc.NOR flash memory cell with high storage densityUS7838920Dec 4, 2006Nov 23, 2010Micron Technology, Inc.Trench memory structures and operationUS7847341Oct 8, 2008Dec 7, 2010Nanosys, Inc.Electron blocking layers for electronic devicesUS8149610May 12, 2010Apr 3, 2012Macronix International Co., Ltd.Nonvolatile memory deviceUS8284616Nov 22, 2010Oct 9, 2012Micron Technology, Inc.Trench memory structure operationUS8686490Feb 20, 2009Apr 1, 2014Sandisk CorporationElectron blocking layers for electronic devicesCN100470808CFeb 9, 2006Mar 18, 2009茂德科技股份有限公司Dynamic random access memory structure and its making methodCN102263122BMay 28, 2010Dec 12, 2012旺宏电子股份有限公司NV (nonvolatile) storing device* Cited by examinerClassifications U.S. Classification365/185.17, 257/E27.103, 365/185.28, 257/E29.306, 257/E21.682, 365/185.33, 257/E21.693International ClassificationG11C16/04, H01L27/115, H01L21/8247, H01L29/788Cooperative ClassificationH01L29/66825, H01L29/7886, H01L29/7885, G11C16/0416, H01L27/11556, G11C2216/28, H01L27/115, H01L27/11521European ClassificationH01L27/115F10C2, H01L29/788B6C, H01L29/66M6T6F17, G11C16/04F1, H01L29/788B6B, H01L27/115, H01L27/115F4Legal EventsDateCodeEventDescriptionMar 13, 2013FPAYFee paymentYear of fee payment: 8Jul 8, 2009FPAYFee paymentYear of fee payment: 4Aug 22, 2006CCCertificate of correctionJun 21, 2002ASAssignmentOwner name: MICRON TECHNOLOGY, INC., IDAHOFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FORBES, LEONARD;REEL/FRAME:013049/0514Effective date: 20020531RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google