Source: http://www.google.com/patents/US7886212?dq=6,249,7726,249,772
Timestamp: 2017-05-30 06:10:46
Document Index: 635864131

Matched Legal Cases: ['application No. 200680035631', 'Application No. 06796108', 'Application No. 09009022', 'Application No. 09009022', 'Application No. 10', 'Application No. 10', 'Application No. 2008', 'Application No. 06796108']

Patent US7886212 - NAND flash memory controller exporting a NAND interface - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA NAND controller for interfacing between a host device and a flash memory device (e.g. a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being...http://www.google.com/patents/US7886212?utm_source=gb-gplus-sharePatent US7886212 - NAND flash memory controller exporting a NAND interfaceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7886212 B2Publication typeGrantApplication numberUS 12/610,868Publication dateFeb 8, 2011Filing dateNov 2, 2009Priority dateSep 26, 2005Fee statusPaidAlso published asCN101366182A, CN101366182B, EP1929483A2, EP1929483A4, EP2110746A1, US7631245, US20070074093, US20100049909, WO2007034481A2, WO2007034481A3Publication number12610868, 610868, US 7886212 B2, US 7886212B2, US-B2-7886212, US7886212 B2, US7886212B2InventorsMenahem LasserOriginal AssigneeSandisk Il Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (104), Non-Patent Citations (33), Referenced by (10), Classifications (11), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetNAND flash memory controller exporting a NAND interface
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Selinger and Menahem Lasser.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7966547 *Jul 2, 2007Jun 21, 2011International Business Machines CorporationMulti-bit error correction scheme in multi-level memory storage systemUS8050095 *Nov 12, 2010Nov 1, 2011Sandisk Technologies Inc.Flash memory data correction and scrub techniquesUS8205038 *Oct 14, 2009Jun 19, 2012Giga-Byte Technology Co., Ltd.Flash memory accessing apparatus and accessing method thereofUS9257203Dec 6, 2012Feb 9, 2016Micron Technology, Inc.Setting a default read signal based on error correctionUS9443599Apr 6, 2015Sep 13, 2016Samsung Electronics Co., Ltd.Method of controlling erase operation of a memory and memory system implementing the sameUS9582362Dec 21, 2015Feb 28, 2017Micron Technology, Inc.Setting a default read signal based on error correctionUS20060077119 *Jul 29, 2005Apr 13, 2006Sharp Laboratories Of America, Inc.Methods and systems for receiving content at an imaging deviceUS20090013223 *Jul 2, 2007Jan 8, 2009Lam Chung HMulti-bit error correction scheme in multi-level memory storage systemUS20110055468 *Nov 12, 2010Mar 3, 2011Gonzalez Carlos JFlash Memory Data Correction and Scrub TechniquesUS20110087826 *Oct 14, 2009Apr 14, 2011Giga-Byte Technology Co.,Ltd.Flash memory accessing apparatus and accessing method thereof* Cited by examinerClassifications U.S. Classification714/763, 365/200, 714/776, 365/185.09, 365/185.33International ClassificationG11C29/00Cooperative ClassificationG06F11/1072, G06F11/1068, G11C16/04European ClassificationG06F11/10M10, G06F11/10M8Legal EventsDateCodeEventDescriptionJul 9, 2014FPAYFee paymentYear of fee payment: 4Dec 9, 2014ASAssignmentOwner name: INNOVATIVE MEMORY SYSTEMS, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK IL LTD.;REEL/FRAME:034437/0799Effective date: 20140618Jan 19, 2016IPRAia trial proceeding filed before the patent and appeal board: inter partes reviewFree format text: TRIAL NO: IPR2016-00324Opponent name: MICRON TECHNOLOGY, INC.Effective date: 20151216RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services