Source: http://www.google.de/patents/US8089298
Timestamp: 2017-12-14 10:19:47
Document Index: 349199818

Matched Legal Cases: ['Application No. 200780020133', 'Application No. 200780020133', 'Application No. 200780020133', 'Application No. 200780020133', 'Application No. 09163220', 'Application No. 07853485', 'Application No. 09163220', 'Application No. 07853485', 'Application No. 2009']

Patent US8089298 - Integrated circuit device with dynamically selected on-die termination - Google Patentsuche
In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations. A termination control signal input is provided to...http://www.google.de/patents/US8089298?utm_source=gb-gplus-sharePatent US8089298 - Integrated circuit device with dynamically selected on-die termination
Veröffentlichungsnummer US8089298 B2
Anmeldenummer US 13/043,946
Auch veröffentlicht unter CN101460936A, CN101460936B, CN102279833A, CN102279833B, DE202007018730U1, EP1999602A2, EP1999602B1, EP2133799A2, EP2133799A3, EP2133799B1, EP2442232A2, EP2442232A3, EP2442232B1, EP2458508A1, EP2458508B1, EP2860641A1, US7486104, US7602209, US7782082, US7924048, US8188762, US8610455, US8610459, US8981811, US9135206, US9166583, US9225328, US9306564, US9306565, US9306566, US9306567, US9306568, US9337835, US9660648, US20070279084, US20080315916, US20090284281, US20100315122, US20110156750, US20110241727, US20110267101, US20120265930, US20130307584, US20150042378, US20150084672, US20150229306, US20150236694, US20150244364, US20150244365, US20150249451, US20150263733, US20160005489, US20160233863, WO2008030641A2, WO2008030641A3
Veröffentlichungsnummer 043946, 13043946, US 8089298 B2, US 8089298B2, US-B2-8089298, US8089298 B2, US8089298B2
Patentzitate (56), Nichtpatentzitate (50), Klassifizierungen (21), Juristische Ereignisse (2)
Integrated circuit device with dynamically selected on-die termination
US 8089298 B2
This application is a continuation of U.S. patent application Ser. No. 12/861,771, filed Aug. 23, 2010 now U.S. Pat. No. 7,924,048 and entitled “A Memory Controller That Controls Termination in a Memory Device,” which is a continuation of U.S. patent application Ser. No. 12/507,794, filed Jul. 22, 2009 and entitled “Memory-Module Buffer with On-Die Termination” (issued as U.S. Pat. No. 7,782,082), which is a continuation of U.S. patent application Ser. No. 12/199,726, filed Aug. 27, 2008 and entitled “Controlling Memory Devices That Have On-Die Termination” (issued as U.S. Pat. No. 7,602,209), which is a continuation of U.S. patent application Ser. No. 11/422,022, filed Jun. 2, 2006 and entitled “Integrated Circuit with Graduated On-Die Termination” (issued as U.S. Pat. No. 7,486,104). Each of the foregoing applications is hereby incorporated by reference.
US20100226185 * 18. Mai 2010 9. Sept. 2010 Samsung Electronics Co., Ltd. Semiconductor memory module and semiconductor memory system having termination resistor units
US20110057720 * 7. Sept. 2010 10. März 2011 Renesas Electronics Corporation Semiconductor integrated circuit
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Unternehmensklassifikation G06F3/0659, G06F3/0605, G06F3/0685, G11C16/32, G11C16/06, H03K19/0005, G11C11/417, H03K19/017545, G06F13/4086, G11C11/413, G11C11/4063, G11C11/41, G11C16/26, G11C11/419, G11C11/4093, G11C11/401
Europäische Klassifikation G06F13/40E2T, G11C11/4093