Source: http://www.google.com/patents/US7545538?dq=6,233,389
Timestamp: 2017-05-27 22:46:48
Document Index: 618126633

Matched Legal Cases: ['art 106', 'art 41', 'art 43', 'art 44', 'art 45', 'art 46', 'art 47', 'art 48', 'art 49', 'art 41', 'art 45', 'art 46', 'art 47', 'art 48', 'art 49', 'art 41', 'art 44', 'art 45', 'art 46', 'art 45', 'art 45', 'art 46', 'art 46', 'art 46', 'art 45', 'art 46', 'art 44', 'art 61', 'art 63', 'art 64', 'art 67', 'art 68', 'art 44', 'art 41', 'art 41', 'art 41', 'art 41', 'art 44', 'art 41', 'art 44', 'art 44', 'art 44', 'art 67', 'art 44', 'art 44', 'art 44', 'art 67', 'art 44', 'art 67', 'art 44', 'art 61', 'art 41', 'art.76', 'art 77', 'art 78', 'art 80', 'art 82', 'art 76', 'art 76', 'art 71', 'art 78', 'art 77', 'art 77', 'art 78', 'art 78', 'art 79', 'art 80', 'art 81', 'art 80', 'art 81', 'art 45', 'art 61', 'art 44', 'art 45', 'art 91', 'art 12', 'art 82', 'art 12', 'art 91', 'art 82', 'art 12', 'art 4', 'art 12', 'art 92']

Patent US7545538 - Image-processing apparatus, image-processing method and recording medium - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsIn an image-processing apparatus, a digital image signal is stored in a memory, and a memory access control part entirely manages all accesses to the memory with respect to the digital image signal. An image processing part converts the digital image signal stored in the memory into an output image signal...http://www.google.com/patents/US7545538?utm_source=gb-gplus-sharePatent US7545538 - Image-processing apparatus, image-processing method and recording mediumAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7545538 B2Publication typeGrantApplication numberUS 11/313,953Publication dateJun 9, 2009Filing dateDec 22, 2005Priority dateSep 27, 2000Fee statusPaidAlso published asDE60139241D1, EP1202556A2, EP1202556A3, EP1202556B1, EP1947836A2, EP1947836A3, US7027190, US20020036643, US20060098227Publication number11313953, 313953, US 7545538 B2, US 7545538B2, US-B2-7545538, US7545538 B2, US7545538B2InventorsYoshiyuki Namizuka, Rie IshiiOriginal AssigneeRicoh Company, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (32), Classifications (11), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetImage-processing apparatus, image-processing method and recording medium
US 7545538 B2Abstract
In an image-processing apparatus, a digital image signal is stored in a memory, and a memory access control part entirely manages all accesses to the memory with respect to the digital image signal. An image processing part converts the digital image signal stored in the memory into an output image signal to be supplied to an imaging unit outputting a visible image based on the output image signal so that a pixel density of the output image signal is higher than a pixel density of the digital image signal read from the memory and an amount of the output image signal is less than an amount of the digital image signal stored in the memory. Accordingly, the central controlled memory is shared by a plurality of functions so as to effectively use the memory, and a high-quality image can be produced by carrying out a density conversion so as to match the pixel density.
an image processing part converting the digital image signal stored in said memory into an output image signal so that a pixel density of the output image signal is higher than a pixel density of the digital image signal read from said memory; and
a programmable operation processor processing the digital image signal so as to reduce a number of quantization steps of the digital image signal and store the digital image signal having a reduced number of quantization steps in said memory.
2. An image-processing apparatus comprising:
a memory access control part that arranges pixels of the output image signal in a square area while preventing generation of an isolated single pixel of black or white when converting the digital image data into the output image data.
3. An image-processing apparatus comprising:
an image processing part converting the digital image signal stored in said memory into an output image signal so that a pixel density of the output image signal is higher than a pixel density of the digital image signal read from said memory;
a memory access control part that includes a pixel density conversion part converting the digital image signal by using said memory; and
said image processing part includes an edge smoothing part smoothing an edge of black pixels and white pixels,
wherein said edge smoothing part is controlled, separately from said pixel density conversion part, by a write-in control performed by an imaging unit outputting a visible image based on the output image signal.
4. An image-processing apparatus comprising:
a memory storing a digital image signal; and
an image processing part converting the digital image signal stored in said memory into an output image signal so that pixel densities of the output image signal in a main scanning direction and a subscanning direction are higher than pixel densities of the digital image signal in the main scanning direction and the subscanning direction read from said memory,
the output image signal is transmitted from said memory to an imaging unit in a form of code data; and
said imaging unit converts the code data into pixel data so as to perform an image output under a write write-in control of said imaging unit.
5. The image-processing unit as claimed in claim 4, wherein translation of the code data from said memory to said imaging unit is performed in synchronization with a signal indicating a write-in line of the code data.
6. An image-processing method comprising the steps of:
reading the digital image signal from said memory;
converting the read image data into an output image data having pixel densities in a main scanning direction and a subscanning direction higher than pixel densities of the read image data in the main scanning direction and the subscanning direction; and
outputting the output image data to an imaging unit forming a visible image based on the output image data,
wherein a number of quantization steps of the digital image signal is reduced.
7. A program, stored in a computer-usable medium, for causing an image-processing apparatus to perform an image-processing method, the image-processing method comprising:
8. A processor readable medium storing a program for causing an image-processing apparatus to perform an image-processing method, the image-processing method comprising:
wherein a number of quantization steps of the digital image signal is reduced. Description
This is a continuation application of U.S. patent application Ser. No. 09/960,944, filed on Sep. 25, 2001 now U.S. Pat. No. 7,027,190, the entire disclosure of which is incorporated by reference herein.
In the multi-function apparatus. (MFP) 100, after the reading unit 104 optically reads an image of an original and changes the read image into a digital image signal, the reading unit 104 outputs the digital image signal to the image-processing unit 105. The imaging unit 107 forms a reproduction image on a transfer paper based on the digital image signal from the video bus control part 106.
It is a general object of the present invention to provide an image processing apparatus and method in which the above-mentioned problems are eliminated.
Additionally, transmission of the code data from the memory to the imaging unit is performed in synchronization with a signal indicating a write-in line of the code data. Accordingly, the image data can be transmitted only when it is needed in accordance with a request by the imaging unit. Thus, a bus-occupancy time can be reduced, which improves a total efficiency of memory use and bus use.
FIG. 1 is a block diagram of a conventional multi-function apparatus;
FIG. 11A is an illustration showing a data compressing operation of the IMAC shown in FIG. 4; and FIG. 11B is an illustration showing a data decompressing operation of the IMAC shown in FIG. 4;
A description will now be given, with reference to accompanying drawings, of preferred embodiments of the present invention.
As shown in FIG. 4, the IMAC 12 comprises an access control part 41, a system I/F 42, a local bus control part 43, a memory control part 44, a compression/decompression part 45, an image editorial part 46, a network control part 47, a parallel bus control part 48, a serial port control part 49, a serial port 50 and direct memory access control parts (DMAC) 51-55. The direct memory access control parts (DMAC) 51-55 are provided between the access control part 41 and each of the compression/decompression part 45, the image editorial part 46, the network control part 47, the parallel bus control part 48 and the serial port control part 49.
In MFP 1, the system controller 14 manages an interface with each external unit. Then, each DMAC 51-55 in the IMAC 12 manages memory access. In this case, since each DMAC 51-55 performs data transmission independently, the access control part 41 performs priority attachment with respect to the collision of jobs and each access request with respect to the access to the MEM 13. Accesses to the MEM 13 include an access of the system controller, other than the accesses by each DMAC 51-55, through the system I/F 42 for bit map deployment of stores data. The data of DMAC to which the access control to the MEM 13 is permitted, or the data from the system I/F 42 is performed by a direct access to the MEM 13 by the memory control part 44.
The IMAC 12 performs a data processing by the compression/decompression part 45 and the image editorial part 46. That is, the compression/decompression part 45 performs a compression and a decompression of data by a predetermined compression system so as to accumulate image data or code data efficiently to the MEM 13. The data compressed by the compression/decompression part 45 is stored in MEM 13 by the DMAC 51-55 controlling an interface with the MEM 13.
The image editorial part 46 controls the MEM 13 by the DMAC 51-55 so as to clear the memory area in the MEM 13 and perform a data processing such as a rotation of an image or a synthesis of different images. Moreover, the image editorial part 46 performs an address control on the memories of the MEM 13 so as to convert the data to be processed. However, the image editorial part 46 does not perform a conversion of code data after being compressed by the compression/decompression part 45, or conversion into printer code but performs the above-mentioned image processing on a bit map image developed on the MEM 13. That is, the compression process for accumulating data effectively to the MEM 13 is performed after an image edit is performed by the image editorial part 46. The memory control part 44 comprises, as shown in FIG. 5, a data path control part 61, the data buffer 62, a request control part 63, an input-and-output control part 64, an output I/F 65, an input I/F 66, an external memory access control part 67 and a command control part 68. The memory control part 44 transmits and receives data between the access control part 41 and the MEM 13.
The access control part 41 has an interface with each DMAC 51-55. The access control part 41 receives the command for the intervention to the MEM 13 of the system controller 14 to the MEM 13 and access arbitration by being connected to the system I/F 42. Thereby, an access to the MEM 13 is independently attained for the access request to the MEM 13 of the DMACs 51-55 and the system controller 14. Therefore, reading from the MEM 13 and the writing to MEM 13 are attained. Moreover, the access control part 41 judges a priority provided from the system controller 14 with respect to a plurality of competing read requests or write requests, and switching a path to the memory control part 44 and the access control part 41 by a command control from the system controller 14.
Since data maintenance cannot be performed on the DMAC 51-55 which is not permitted to write in the MEM 13, data input from outside cannot be performed, and, therefore, a data input operation of external units is prohibited by a control of the system controller 14.
Output data of the DMAC 51-55 or the system I/F 42 of which access to the MEM 13 is permitted is transmitted to the memory control part 44. Moreover, a command of the permitted system controller 14 is also transmitted to the memory control part 44.
The memory control part 44 generates a MEM control signal by the external memory access control part 67 based on control system data sent from the DMACs 51-55 or the system controller 14 so a to perform an address control of the MEM 13. The memory control part 44 transmits the data and the MEM control signal to the MEM 13, and stores the data in the MEM 13. The memory control part 44 reads the data stored in the MEM 13. That is, based on the control system data from the DMAC 51-55 or the system controller 14 to which an access to the MEM 13 is permitted, the memory control part 44 generates the MEM control signal by the external memory access control part 67, and performs an address control of the MEM 13. Then, the memory control part 44 transmits a control signal to the MEM 13 from the external memory access control part 67, and performs a memory read-out processing, and taken in the access data through the I/F 66. The memory control part 44 temporarily stores the data, which is taken in from the MEM 13, in the data buffer 62 by the data path control part 61, and transmits the data to a requesting channel via the-access control part 41.
The VDC6 comprises, as shown in FIG. 6, a decoding part buffer 71, a line buffer 72, a selector 73, a 9-line buffer 74, an image matrix 75 of a 9-line×3 pixels, a jaggy correction part.76, a processing part 77, an isolated point correction part 78, an error diffusion enhancement 79 a dither smoothing part 80, an edge processing part 82 and a selector 83. The jaggy correction part 76 is provided with a correction code part 76 a and a RAM 76 b. The VDC 6 decodes by the decoding part 71 3-bit encoding data transmitted via the parallel bus 21 from the IMAC 12, and converts the data into pixel data 2×2 pixels. The VDC 6 stores 2 pixels located in the lower row of the converted pixel data in the 1-line buffer 72, and transmits 2 pixels located in the upper row to the selector 73. The selector 73 switches the decoded upper row pixels or lower row pixels in synchronization with a line synchronization signal, and transmits it to the image matrix 75 through the 9-line buffer 74. The VDC 6 performs a control of switching the upper row pixel and the lower row pixel, as shown in FIG. 7. That is, the VDC 6 requests the IMAC 12 to transmit the encoded data for every two lines. At the first line, the decoded upper row pixel is chosen as it is, and the 2 pixels of the lower row are transmitted to the 1-line buffer 72. At the second line which indicates the next image line, the VDC 6 reads the previously stored lower row pixels from the line buffer 72, and uses the pixels for pixel correction.
In the VDC 6, the image matrix 75 creates 13-pixel delay data in the main scanning direction from data of nine lines, respectively, so as to create a 9-line×13-pixel two-dimensional matrix. Although the VDC 6 accesses the matrix data simultaneously so as to carry out a binary value/multi-value conversion processing, the VDC 6 performs, with respect to an edge processing, a process with data on 1 line without using a two-dimensional image matrix.
The isolated point correction part 78 detects an isolated point by pattern matching in an image area of 9×13 containing an attention pixel. By removing the pixel corresponding to an isolated point or adding pixels to the isolated point within two-dimensional range, the processing part 77 constitutes a set of pixels which are not isolated and outputs the set of pixels to the selector 83. In addition, a mode change is available as to whether a masking is carried out by the processing part 77 or whether pixels are added to the circumference. That is, in a case of an isolated dot, depending on the process conditions of a write-in system, there may be a case in which a dot can be reproduced and a case in which a dot cannot be reproduced, and, thus, unevenness occurs in concentration in an input concentration area, and degradation of image quality is caused. Therefore, a mode change is performed so as to not strike any dot or increase a dot density to the range in which dots can be reproduced stably. The isolated point correction part 78 sets up a central pixel as an attention pixel within the range of the image matrix 75 of 9×13 in detection of an isolated point. As an object of a judgment of whether to be an isolated point regarding the attention pixel concerned, the isolated point correction part 78 judges relation to circumference pixels by pattern matching so as to judge an isolated point. The error diffusion enhancement part 79 smoothes a texture by a band-pass filter holding a line image so as to generate a phase signal based on the pixel row of the main scanning direction, and outputs the phase signal to the selector 83.
The dither smoothing part 80 performs low path filter processing of 5×5, 7×7 and 9×9 on a binary value dither pattern so as to approximately convert into a multi-value signal in false, and outputs the dither pattern to the 2-dot processing part 81. Namely, by applying each smoothing filtering processes of 5×5, 7×7, and 9×9 to the 9-line×13-pixel image matrix 75, the dither smoothing part 80 removes a high-band signal component from the input data which is a 1-bit binary value signal, and outputs it to the 2-dot processing part 81.
In the printer mode, the MFP 1 supplies the image data for carrying out a print output to the IMAC12 from the PC 30 connected to the network NW or the general use serial bus 20. After image data is developed on a bit map in the IMAC 12, the image data is transmitted from the IMAC 12 to the VDC 6 via the parallel bus 21. The MFP 1 transmits a control command of the VDC 6 from the system controller 14 to the VDC6 via the IMAC 12. After the control command is converted into serial data in the VDC 6, the control command is transmitted to the process controller 8 via the serial bus 20. Then, MFP 1 shifts to a write-in control by the process controller 8. The MFP 1 carries out a control based on a route as shown in FIG. 10. That is, the MFP 1 uses a data path of exclusive use without going the data transmission from the CDIC. 4 to the VDC 6 via the parallel bus 21 so s to effectively use the parallel bus 21 and improve the performance of the entire MFP 1. Basically, the performance is improved by the role assignment between the system controller 14 and the process controller 8. By the process controller 8 serving as a coprocessor of the system controller 14, a write-in control and an image-processing control centering on the imaging unit 7 are performed. In performing a data compression/decompression operation, as shown in FIGS. 11A and 11B, the MFP 1 performs a compression/decompression processing using the compression/decompression part 45 of the IMAC 12, the data path control part 61 of the memory control part 44, and the DMAC 51. The compression/decompression part 45 is provided with a compressor 45 a and a decompressor 45 b, which are used by being switched between compression and decompression. The DMAC 51 is provided with the DMAC 51 a for images and the DMAC 51 b for codes, which are used by being switched between compression and decompression. That is, the MFP 1 avoids a collision of data on the DMAC 51 by using different channels of the DMAC 51 for the access to MEM 13 based on image data and code data.
As shown in FIG. 12A, a 600 dpi×600 dpi×3 bits image is accumulated in the MEM 13 managed by the IMAC 12 with respect to a size of an original to be read. It should be noted that FIG. 12A shows data of a size of N pixel×N pixel. The IMAC 12 carries out a bit map conversion so as to convert the bit map into a high definition density of 1200 dpi×1200 dpi×1 bit, as shown in FIG. 12B. That is, in the image data of low resolution, 3 bits of concentration information of each pixel are converted into a pixel density of high resolution. In this case, in response to an increase of the number of pixels, concentration information is deleted and is converted into a binary value image. It should be noted that FIG. 12B shows an example in which an area of an original the same as the bit map of FIG. 12A is converted into high-density data of 2N pixels×2N pixels, although the number of pixels of FIG. 12A is merely increased in both the main scanning direction and the subscanning direction. Moreover, the IMAC 12 performs a smoothing processing on the bit map stored in the MEM 13. FIG. 12C shows an example in which a smoothing processing is applied to a binary value bit map after the density conversion shown in FIG. 12B. In the smoothing processing, the binary value data is again converted into multi-value data so as to reproduce fine pixels.
That is, supposing FIG. 12A shows a bit map of a binary value image of 600 dpi×600 dpi×1 bit from the PC 30, each pixel in the bit map is simply doubled in both the main scanning direction and the subscanning direction so s to convert into a pixel density of 1200 dpi×1200 dpi×1 bit. With respect to the smoothing processing shown in FIG. 12C, similar to the read image data, the imaging unit 7 commonly processes the image data irrespective of whether the image data is of a copy mode, a facsimile mode or a printer mode. After converting the bit map on the MEM 13 into the output pixel density of the record engine of the imaging unit 7, the bit map data is treated as bit map data independent of the input device.
For example, when rearranging 1 pixel of 600 dpi to 4 pixels of 1200 dpi, the 4 pixels are arranged in a square area so as to form 2×2 pixels in the main scanning direction and the subscanning direction. In this case, there are only six arrangements of the dots which can be taken, that is, all white, all black and an arrangement in which a pair of two dots are formed. Two consecutive pixels in the a diagonal direction shall not be permitted, and a control of 1-dot in each of the main scanning direction, the subscanning direction and the diagonal direction is assigned to the smoothing processing.
A direction of connection of the pixels is beforehand taken into consideration at the time of the density conversion by the IMAC 12 so that the pattern matching by the smoothing processing can be carried out easily at a high speed. That is, in the original pixel of 600 dpi shown in FIG. 13, a code 0 is assigned to all whites, a code 5 is assigned to all blacks, and codes 1 to 4 are assigned to four kinds of arrangement of a pair of two pixels in vertical and horizontal directions. Therefore, the number of generated patterns after the density conversion is six, and all generation patterns can be represented by 3 bits. Change in the amount of data in this pixel density conversion is as follows. Namely, as for the read image data, image data corresponding to the size of a read original is transmitted to the IMAC 12 with a small value (less than 8 bits) from the IPP 5. With respect to the size of the read original, a generated pattern is 600 dpi×600 dpi×3 bit, and the pixel density conversion with respect to the same size of the original becomes ((1200 dpi×1200 dpi)/4)×3 bits. Here, the reason for dividing by “4” is to assign all 4 pixels to a 3-bit code.
If a ratio of the two above-mentioned equations is taken, the ratio of the data transmitted to the VDC 6 from the MEM 13 to the data transmitted to the MEM 13 from the IPP 5 becomes “1” which indicates the same amount of data. As compared to a case where the converted data is transmitted to the VDC 6 as it is, the amount of data is reduced to three quarters, thereby improving transmission efficiency. Therefore, when a small value level from the IPP 5 is greater than 3 bits, the transmission efficiency from the MEM 13 to the VDC 6 is relatively improved. Moreover, although the transmission efficiency to the VDC 6 deteriorates relatively when the small value level is less than 3 bits, the amount of data can be reduced to three quarters than a case in which the converted pixels of 1200 dpi×1200 dpi is transmitted without change.
FIG. 14 shows an example of a case in which a pattern matching is carried out in a 3×3 pixel area of 600 dpi×600 dpi. In FIG. 14, a thin-color pixel (pixel indicated by a hatched circle) positioned in the center of 3×3 pixels is an attention pixel. In FIG. 14, the attention pixel is converted into 2×2 pixels of 1200 dpi×1200 dpi. That is, in FIG. 14, when the attention pixel is located on an edge and three pixels exist on the right side, the attention pixel is converted into two pixels which are consecutively arranged in the right part in the vertical direction, and a code 2 is assigned thereto. When the attention pixel is located on an edge and three pixels exist on the left side, the attention pixel is converted into two pixels which are consecutively arranged in the left part in the vertical direction, and a code 4 is assigned thereto. When the attention pixel is located on an edge and three pixels exist on the lower side, the attention pixel is converted into two pixels which are consecutively arranged in the lower part in the horizontal direction, and a code 3 is assigned thereto. When the attention pixel is located on an edge and three pixels exist on the upper side, the attention pixel is converted into two pixels which are consecutively arranged in the upper part in the horizontal direction, and a code 1 is assigned thereto. When the attention pixel is located as a convex pixel in any directions, the attention pixel is converted into all black pixels, and a code 5 is assigned thereto. When the attention pixel is located as a concave pixel in any directions, the attention pixel is converted into all white pixels, and a code 0 is assigned thereto. It should be noted that these patterns are examples and a code is assigned to each of pixel arrangements which can be formed. A pixel density conversion is performed by the system controller 14 with respect to image data in the MEM 13 by referring to corresponding pixels by memory access of the IMAC 12.
In the case of read image data, as indicated by a data transmission path (1) shown in FIG. 15, the read image data of 600 dpi×600 dpi, which is read by the light-receiving element of the SBU 3 and is converted into digital data, is transmitted to the IPP 5. In the IPP 5, the read image data is re-quantized into a small value of 3 bits/pixel. The quantized data is stored in the MEM 13 via the CDIC 4, the parallel bus 21 and the IMAC 12. In the IMAC 12 and the system controller 14, the read image data stored in the MEM 13 is density-converted into a binary value image of 1200 dpi×1200 dpi in the IMAC 12 and the system controller 14, and a code of 3 bits is assigned. The above processing is performed so as to grouping four pixels and assign a code, and the amount of data is reduced rather than directly treating as bit data. As indicated by a data transmission path (2) shown in FIG. 15, the converted data is transmitted from the MEM 13 to the VDC 6 via the IMAC 12, the parallel bus 21 and the CDIC 4. In the above-mentioned data transmission, there is no change in the amount of data on the data transmission course (1), and the transmission efficiency of the parallel bus 21 does not decrease due to a highly densification. Then, as mentioned above, the code data transmitted to the VDC 6 is decoded in the VDC 6. Then, after correcting the image data to a high print quality by applying the edge smoothing, the record output of the image is carried out by the imaging unit 7.
FIG. 16 shows a data transmission path in a case in which binary image data, which is facsimile data or print data from the PC 30, is subjected to a density conversion. In the case of binary value image data, as indicated by a data transmission path (3) shown in FIG. 16, the facsimile received binary value image data is developed on the MEM 13 via the IMAC 12. On the other hand, the print data from PC 30 is developed on the MEM 13 via the IMAC 12, as indicated by a data transmission path (4) shown in FIG. 16. The binary value bit map data developed on the MEM 13 via the data transmission path (3) or (4) is density-converted into 1200 dpi×1200 dpi which is the resolution of the record engine of the imaging unit 7. In this case, the image data is converted into code data corresponding to two consecutive pixels which does not generate an isolated single dot of white or black so as to reduce the amount of data transmitted to the parallel bus 21. The bit map data is transmitted from the MEM 13 to the VDC 6 through the parallel bus 21, as indicated by a data transmission path (5) shown in FIG. 14. The VDC 6 decodes the transmitted code data, and performs an edge smoothing processing on the binary value bit map image so as to carry out a record output by the imaging unit 7.
A description will now be given, with reference to FIGS. 17 through 22, of an image-processing apparatus and method according to a second embodiment of the present invention. The image-processing apparatus according to the present embodiment has the same whole composition as the image-processing apparatus according to the first embodiment, and a description thereof will be omitted. FIG. 17 is a block diagram showing an outline composition of a frame memory and an image memory access control part (IMAC) according to the present embodiment. In FIG. 17, data output from a data control part 91 of the CDIC 4 is supplied to the IMAC 12, which is a memory controller, via the parallel bus 21 such as a PCI bus. The IMAC 12 is provided with a high-density conversion part 12 a and a code conversion part 82. The high-density conversion part 12 a converts imaged data of M dpi/N values sent from the data control part 91 into image data of a still higher-density of m dpi/n values (M<m, N>n). The code conversion part 82 performs a code conversion process of data from the MEM 13.
FIG. 18 is an illustration showing a processing operation of a high-density conversion part 12A in the IMAC 12. In FIG. 18, since the data is equivalent to a half dot when the data transmitted from a data control part 4A is 2 of 5-value data, four patterns (3 a-3 d) can be taken as a pattern. However, since a dot position control is not performed here, the data is converted into 4-bit data as it is, and is stored in the MEM 13.
FIG. 19 is an illustration showing a processing operation of a code conversion part 12B in the IMAC 12. In FIG. 19, considering the arrangement of the data stored in the MEM 13, there are patterns a-d in accordance with each size. However, there is a regularity in the dot position control, and when a pixel is enlarged by a dot concentration method so as to strike the dot stably, there is considered a pattern indicated by 401. In this example of the regularity, P corresponds to a single pixel of 600 dpi, and it is represented to enlarge the pixels from positions of d, c, a and b, in that order, when the pixel of 600 dpi is divided into four pixels of 1200 dpi and strike each dot at a quarter power. That is, since the position from which a strike a pixel is started is decided by the position of the input image data, the code, which the IMAC 12 supplies, is merely related with the size of data. Therefore, what is necessary is to encode only five patterns (3 bits) of a instead of 14 patterns (4 bits) including the original patterns of a, b, c and d. Thus, the amount of data, which is transmitted through the bus, decreases, and its transmission efficiency improves.
FIG. 21 is a block diagram showing an example of a composition in the case of changing pixel arrangement according to an image data position. In FIG. 21, the data operation part 92 and CDIC 4 are added in addition to the composition shown in FIG. 17. The code data reduced most efficiently is transmitted to the CDIC 4 through the PCI bus (parallel bus 21). The code is developed to data by deciding whether to change the pixel arrangement for each position according to information (for example, 1-bit information indicating whether it is an edge or non-edge) separately sent from the IPP 5.
FIG. 22 is an illustration showing an example of the development of data encoded as mentioned above. As shown in FIG. 22, although “1110” is obtained if the code is 3 and is developed as it is, a position is shifted so as to obtain “1011” only when a conversion control is performed. In FIG. 22, when the pixel is arranged by the pattern of c, “1011” is obtained by starting a reading operation of 4-bit “1110” data from the position of c.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4084259Oct 11, 1974Apr 11, 1978The Mead CorporationApparatus for dot matrix recordingUS4160279 *Sep 27, 1977Jul 3, 1979Ricoh Company, Ltd.Optoelectronic reading apparatusUS4709274Aug 27, 1984Nov 24, 1987Canon Kabushiki KaishaImage processing apparatusUS5006937Jul 27, 1990Apr 9, 1991Canon Kabushiki KaishaImaging data processing apparatusUS5237675 *Mar 19, 1992Aug 17, 1993Maxtor CorporationApparatus and method for efficient organization of compressed data on a hard disk utilizing an estimated compression factorUS5465160Aug 31, 1994Nov 7, 1995Ricoh Company, Ltd.Composite image forming apparatus for automatically combining document and image charactersUS5532693 *Jun 13, 1994Jul 2, 1996Advanced Hardware ArchitecturesAdaptive data compression system with systolic string matching logicUS5600373 *Jun 27, 1996Feb 4, 1997Houston Advanced Research CenterMethod and apparatus for video image compression and decompression using boundary-spline-waveletsUS5604499 *Dec 14, 1994Feb 18, 1997Matsushita Electric Industrial Co., Ltd.Variable-length decoding apparatusUS5652660 *Apr 27, 1995Jul 29, 1997Canon Kabushiki KaishaImage smoothing using selection among plural pre-stored pixel patterns as smoothed dataUS5684611Jun 6, 1995Nov 4, 1997Accuwave CorporationPhotorefractive systems and methodsUS5715329 *Mar 22, 1994Feb 3, 1998Matsushita Electric Industrial Co., Ltd.Digital copying machine with memory for compressed image dataUS5802209Jun 26, 1996Sep 1, 1998Seiko Epson CorporationApparatus and method for compressing and restoring binary image having multitoneUS5828396 *Jun 29, 1993Oct 27, 1998Canon Kabushiki KaishaInformation recording apparatus for recording images using plural information signals corresponding to respective plural colorsUS5946523 *Mar 12, 1998Aug 31, 1999Fujitsu LimitedPrinting apparatusUS6317220Dec 4, 1997Nov 13, 2001Seiko Epson CorporationImage forming apparatus capable of preventing linear nonuniformity and improving image qualityUS6643031 *Dec 21, 1999Nov 4, 2003Kabushiki Kaisha ToshibaImage processing apparatusUS7245314 *Jan 31, 2002Jul 17, 2007Ricoh Company, Ltd.Image apparatus and method for converting scanned image dataUS20020154327 *Apr 24, 2001Oct 24, 2002Jones Michael J.Incorporating data in hardcopy correspondenceUS20030182605 *Sep 20, 2001Sep 25, 2003Short Robert L.Process and device for identifying and designating radially-oriented patterns of defects on a data-storage mediumUS20050219620 *Nov 1, 2004Oct 6, 2005Masakazu OhshitaImage data processing machineDE2812821A1Mar 23, 1978Oct 5, 1978IbmVerfahren zur reproduktion eines durch abtastung in elemente unterteilen bildesEP0343644A2May 24, 1989Nov 29, 1989Yozan Inc.Image processing methodEP0506379A2Mar 26, 1992Sep 30, 1992Canon Kabushiki KaishaImage processing apparatus and methodEP0555064A1 *Feb 3, 1993Aug 11, 1993Canon Kabushiki KaishaImage processing apparatus and recording apparatusEP0705026A1Sep 29, 1995Apr 3, 1996Xerox CorporationApparatus and method for encoding and reconstructing image dataEP0853419A2Dec 4, 1997Jul 15, 1998Hewlett-Packard CompanyMethod and apparatus for obtaining multiple views from one scan windowJP2002176554A * Title not availableJPH1064429A Title not availableJPH1162055A Title not availableJPH09275494A * Title not availableJPH10226179A Title not available* Cited by examinerClassifications U.S. Classification358/3.1, 358/1.16International ClassificationG06T3/40, H04N1/387, H04N1/40, G06K15/00, H04N1/409, B41J5/30, H04N1/21Cooperative ClassificationH04N1/40European ClassificationH04N1/40Legal EventsDateCodeEventDescriptionOct 1, 2012FPAYFee paymentYear of fee payment: 4Nov 30, 2016FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services