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Timestamp: 2016-09-26 02:04:28
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Matched Legal Cases: ['art 1', 'art 2', 'art 2', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'art 2']

Patent US6376339 - Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn underlying gallium nitride layer on a silicon carbide substrate is masked with a mask that includes an array of openings therein, and the underlying gallium nitride layer is etched through the array of openings to define posts in the underlying gallium nitride layer and trenches therebetween. The...http://www.google.com/patents/US6376339?utm_source=gb-gplus-sharePatent US6376339 - Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on silicon carbide substrates by lateral growth from sidewalls of masked posts, and gallium nitride semiconductor structures fabricated therebyAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6376339 B2Publication typeGrantApplication numberUS 09/780,072Publication dateApr 23, 2002Filing dateFeb 9, 2001Priority dateNov 24, 1998Fee statusPaidAlso published asCA2347425A1, CA2347425C, CN1155993C, CN1348603A, DE1138063T1, DE69940274D1, EP1138063A1, EP1138063B1, US6177688, US6462355, US7378684, US20010008299, US20020179911, WO2000033365A1, WO2000033365A8Publication number09780072, 780072, US 6376339 B2, US 6376339B2, US-B2-6376339, US6376339 B2, US6376339B2InventorsKevin J. Linthicum, Thomas Gehrke, Darren B. Thomson, Eric P. Carlson, Pradeep Rajagopal, Robert F. DavisOriginal AssigneeNorth Carolina State UniversityExport CitationBiBTeX, EndNote, RefManPatent Citations (54), Non-Patent Citations (84), Referenced by (64), Classifications (23), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetPendeoepitaxial methods of fabricating gallium nitride semiconductor layers on silicon carbide substrates by lateral growth from sidewalls of masked posts, and gallium nitride semiconductor structures fabricated thereby
US 6376339 B2Abstract
That which is claimed is: 1. A method of fabricating a gallium nitride semiconductor layer comprising the steps of:
masking an underlying gallium nitride layer on a silicon carbide substrate with a mask that includes an array of openings therein; etching the underlying gallium nitride layer through the array of openings to define a plurality of posts in the underlying gallium nitride layer and a plurality of trenches therebetween, the posts each including a sidewall and a top having the mask thereon; and laterally growing the sidewalls of the posts into the trenches to thereby form a gallium nitride semiconductor layer. 2. A method according to claim 1 wherein the step of laterally growing comprises the step of laterally growing the sidewalls of the posts into the trenches until the laterally grown sidewalls coalesce in the trenches to thereby form a gallium nitride semiconductor layer.
forming a buffer layer on a silicon carbide substrate; and forming an underlying gallium nitride layer on a buffer layer, opposite the silicon carbide substrate. 14. A method of fabricating a gallium nitride semiconductor layer comprising the steps of:
providing a silicon carbide substrate, a gallium nitride layer on the silicon carbide substrate and a capping layer on the gallium nitride layer opposite the silicon carbide substrate, the gallium nitride layer including a plurality of posts and a plurality of trenches therebetween, the trenches defining a plurality of openings in the capping layer; laterally and vertically growing sidewalls of the posts into the trenches and through the openings in the capping layer to thereby form a lateral gallium nitride layer in the trenches that extends vertically through the openings in the capping layer; and laterally overgrowing the lateral gallium nitride layer that extends through the openings in the capping layer onto the capping layer to thereby form an overgrown lateral gallium nitride layer. 15. A method according to claim 14 wherein the steps of laterally and vertically growing the sidewalls and laterally overgrowing the lateral gallium nitride layer are performed without vertically growing gallium nitride on the capping layer.
masking an underlying gallium nitride layer on a silicon carbide substrate with a mask that includes an array of openings therein; etching the underlying gallium nitride layer through the array of openings to define a plurality of posts in the gallium nitride layer and a plurality of trenches therebetween, the posts each including a sidewall and a top having the mask thereon to provide the capping layer. 19. A method according to claim 18 wherein the masking step comprises the step of masking an underlying gallium nitride layer on a buffer layer on a silicon carbide substrate with a mask that includes an array of openings therein.
masking the underlying gallium nitride layer with a make that includes an array of first stripe openings therein that extend along a <11{overscore (2)}0> direction of the underlying gallium nitride layer, and an array of second stripe openings therein that extend along a <1{overscore (1)}00> direction of the underlying nitride layer. 33. A method according to claim 32 wherein the array of first stripe openings and the array of second stripe openings are arranged in a rectangle on the underlying gallium nitride layer, the rectangular having edges of predetermined lengths, and wherein a ratio of the predetermined lengths is proportional to a ratio of growth rates of a {11{overscore (2)}0 } facet and a {1{overscore (1)}01} facet of the underlying gallium nitride layer during the growing up step.
The pendeoepitaxial gallium nitride semiconductor layer may be laterally grown using metalorganic vapor phase epitaxy (MOVPE). For example, the lateral gallium nitride layer may be laterally grown using triethylgallium (TEG) and ammonia (NH3) precursors at about 1000�-1100� C. and about 45 Torr. Preferably, TEG at about 13-39 μmol/min and NH3 at about 1500 sccm are used in combination with about 3000 sccm H2 diluent. Most preferably, TEG at about 26 μmol/min, NH3 at about 1500 sccm and H2 at about 3000 sccm at a temperature of about 1100� C. and about 45 Torr are used. The underlying gallium nitride layer preferably is formed on a substrate such as 6H-SiC(0001), which itself includes a buffer layer such as aluminum nitride thereon. Other buffer layers such as gallium nitride may be used. Multiple substrate layers and buffer layers also may be used.
Referring now to FIGS. 1-6, methods of fabricating gallium nitride semiconductor structures according to the present invention will now be described. As shown in FIG. 1, an underlying gallium nitride layer 104 is grown on a substrate 102. The substrate 102 may include a 6H-SiC(0001) substrate 102 a and an aluminum nitride or other buffer layer 102 b. The crystallographic designation conventions used herein are well known to those having skill in the art, and need not be described further. The underlying gallium nitride layer 104 may be between 0.5 and 2.0 μm thick, and may be grown at 1000� C. on a high temperature (1100� C.) aluminum nitride buffer layer 102 b that was deposited on the 6H-SiC substrate 102 a in a cold wall vertical and inductively heated metalorganic vapor phase epitaxy system using triethylgallium at 26 μmol/min, ammonia at 1500 sccm and 3000 sccm hydrogen diluent. Additional details of this growth technique may be found in a publication by T. W. Weeks et al. entitled “GaN Thin Films Deposited Via Organometallic Vapor Phase Epitaxy on (6H)-SiC(0001) Using High-Temperature Monocrystalline AlN Buffer Layers”, Applied Physics Letters, Vol. 67, No. 3, Jul. 17, 1995, pp. 401-403, the disclosure of which is hereby incorporated herein by reference. Other silicon carbide substrates, with or without buffer layers, may be used.
Continuing with the description of FIG. 1, a mask such as a silicon nitride (SiN) mask 109 is included on the underlying gallium nitride layer 104. The mask 109 may have a thickness of about 1000Å and may be formed on the underlying gallium nitride layer 104 using low pressure chemical vapor deposition (CVD) at 410� C. The mask 109 is patterned to provide an array of openings therein, using conventional photolithography techniques.
Referring now to FIG. 2, the sidewalls 105 of the underlying gallium nitride layer 104 are laterally grown to form a lateral gallium nitride layer 108 a in the trenches 107. Lateral growth of gallium nitride may be obtained at 1000�-1100� C. and 45 Torr. The precursors TEG at 13-39 μmol/min and NH3 at 1500 sccm may be used in combination with a 3000 sccm H2 diluent. If gallium nitride alloys are formed, additional conventional precursors of aluminum or indium, for example, may also be used. As used herein, the term “lateral” means a direction that is parallel to the faces of the substrate 102. It will also be understood that some vertical growth of the lateral gallium nitride 108 a may also take place during the lateral growth from the sidewalls 105. As used herein, the term “vertical” denotes a directional parallel to the sidewalls 105. However, it will be understood that growth and/or nucleation on the top of the posts 106 is reduced and is preferably eliminated by the mask 109.
Continuing with the description of FIG. 6, the lateral gallium nitride layer 108 a extends laterally and vertically from the plurality of sidewalls 105 of the underlying gallium nitride layer 104. The overgrown lateral gallium nitride 108 b extends from the lateral gallium nitride layer 108 a. The lateral gallium nitride layer 108 a and the overgrown lateral gallium nitride layer 108 b may be formed using metalorganic vapor phase epitaxy at about 1000�-1100� C. and about 45 Torr. Precursors of triethygallium (TEG) at about 13-39 μmol/min and ammonia (NH3) at about 1500 sccm may be used in combination with an about 3000 sccm H2 diluent, to form the lateral gallium nitride layer 108 a and the overgrown lateral gallium nitride layer 108 b. As shown in FIG. 6, the lateral gallium nitride layer 108 a coalesces at the interfaces 108 c to form a continuous lateral gallium nitride semiconductor layer 108 a in the trenches. It has been found that the dislocation densities in the underlying gallium nitride layer 104 generally do not propagate laterally from the sidewalls 105 with the same density as vertically from the underlying gallium nitride layer 104. Thus, the lateral gallium nitride layer 108 a can have a relatively low dislocation defect density, for example less than about 104 cm−2. From a practical standpoint, this may be regarded as defect-free. Accordingly, the lateral gallium nitride layer 108 a may form device quality gallium nitride semiconductor material. Thus, as shown in FIG. 6, microelectronic devices 110 may be formed in the lateral gallium nitride semiconductor layer 108 a. Still referring to FIG. 6, the overgrown lateral gallium nitride layer 108 b coalesces at the interfaces 108 d to form a continuous overgrown lateral gallium nitride semiconductor layer 108 b over the masks. It has been found that the dislocation densities in the underlying gallium nitride layer 104 and of the lateral gallium nitride layer 108 a generally do not propagate laterally with the same density as vertically from the underlying gallium nitride layer 104 and the lateral gallium nitride layer 108 a. Thus, the overgrown lateral gallium nitride layer 108 b also can have a relatively low defect density, for example less than about 104 cm−2. Accordingly, the overgrown lateral gallium nitride layer 108 b may also form device quality gallium nitride semiconductor material. Thus, as shown in FIG. 6, microelectronic devices 110 may also be formed in the overgrown lateral gallium nitride semiconductor layer 108 b. Referring now to FIGS. 7 and 8, other embodiments of gallium nitride semiconductor structures and fabrication methods according to the present invention will now be described. Gallium nitride structures are fabricated as was already described in connection with FIGS. 1-6 using different spacings or dimensions for the posts and trenches. In FIG. 7, a small post-width/trench-width ratio is used to produce discrete gallium nitride structures. In FIG. 8, a large post-width/trench-width ratio is used, to produce other discrete gallium nitride structures.
Referring now to FIG. 7, using a small post-width/trench-width ratio, gallium nitride semiconductor structures of FIG. 7 are fabricated as was already described in connection with FIGS. 1-4. Still referring to FIG. 7, growth is allowed to continue until the overgrown lateral fronts coalesce over the mask 109 at the interfaces 108 d, to form a continuous overgrown lateral gallium nitride semiconductor layer over the mask 109. The total growth time may be approximately 60 minutes. As shown in FIG. 7, microelectronic devices 110 may be formed in the overgrown lateral gallium nitride layer 108 b. Referring now to FIG. 8, using a large post-width I trench-width ratio, gallium nitride semiconductor structures of FIG. 8 are fabricated as was already described in connection with FIGS. 1-4. Still referring to FIG. 8, growth is allowed to continue until the overgrown lateral fronts coalesce in the trenches 107 at the interfaces 108 c, to form a continuous gallium nitride semiconductor layer 108 a in the trenches 107. The total growth time may be approximately 60 minutes. As shown in FIG. 8, microelectronic devices 110 may be formed in the pendeoepitaxial gallium nitride layer 108 a. Additional discussion of methods and structures of the present invention will now be provided. The trenches 107 and are preferably rectangular trenches that preferably extend along the <11{overscore (2)}0> and/or <1{overscore (1)}00> directions on the underlying gallium nitride layer 104. Truncated triangular stripes having (1{overscore (1)}01) slant facets and a narrow (0001) top facet may be obtained for trenches along the <11{overscore (2)}0> direction. Rectangular stripes having a (0001) top facet, (11{overscore (2)}0) vertical side faces and (1{overscore (1)}01) slant facets may be grown along the <1{overscore (1)}00> direction. For growth times up to 3 minutes, similar morphologies may be obtained regardless of orientation. The stripes develop into different shapes if the growth is continued.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4127792May 27, 1977Nov 28, 1978Mitsubishi Denki Kabushiki KaishaLuminescent semiconductor display device including gate control electrodesUS4522661Jun 24, 1983Jun 11, 1985The United States Of America As Represented By The Administrator Of The National Aeronautics And Space AdministrationLow defect, high purity crystalline layers grown by selective depositionUS4651407May 8, 1985Mar 24, 1987Gte Laboratories IncorporatedMethod of fabricating a junction field effect transistor utilizing epitaxial overgrowth and vertical junction formationUS4865685Nov 3, 1987Sep 12, 1989North Carolina State UniversityDry etching of silicon carbideUS4876210Mar 4, 1988Oct 24, 1989The University Of DelawareSolution growth of lattice mismatched and solubility mismatched heterostructuresUS4912064Oct 26, 1987Mar 27, 1990North Carolina State UniversityHomoepitaxial growth of alpha-SiC thin films and semiconductor devices fabricated thereonUS4946547Oct 13, 1989Aug 7, 1990Cree Research, Inc.Method of preparing silicon carbide surfaces for crystal growthUS5122845Feb 26, 1990Jun 16, 1992Toyoda Gosei Co., Ltd.Substrate for growing gallium nitride compound-semiconductor device and light emitting diodeUS5156995Apr 12, 1991Oct 20, 1992Cornell Research Foundation, Inc.Method for reducing or eliminating interface defects in mismatched semiconductor epilayersUS5389571Apr 16, 1993Feb 14, 1995Hiroshi AmanoMethod of fabricating a gallium nitride based semiconductor device with an aluminum and nitrogen containing intermediate layerUS5397736Jun 20, 1994Mar 14, 1995Max-Planck-Gesellschaft Zur Foerderung Der WissenschaftenLiquid epitaxial process for producing three-dimensional semiconductor structuresUS5549747Apr 14, 1994Aug 27, 1996Massachusetts Institute Of TechnologyMethod of producing sheets of crystalline material and devices made therefromUS5710057Jul 12, 1996Jan 20, 1998Kenney; Donald M.SOI fabrication methodUS5760426Jul 16, 1996Jun 2, 1998Mitsubishi Denki Kabushiki KaishaHeteroepitaxial semiconductor device including silicon substrate, GaAs layer and GaN layer #13US5786606Dec 12, 1996Jul 28, 1998Kabushiki Kaisha ToshibaSemiconductor light-emitting deviceUS5815520Jun 21, 1996Sep 29, 1998Nec Corporationlight emitting semiconductor device and its manufacturing methodUS5877070May 31, 1997Mar 2, 1999Max-Planck SocietyMethod for the transfer of thin layers of monocrystalline material to a desirable substrateUS5880485Sep 11, 1997Mar 9, 1999Mitsubishi Denki Kabushiki KaishaSemiconductor device including Gallium nitride layerUS5912477May 20, 1997Jun 15, 1999Cree Research, Inc.High efficiency light emitting diodesUS5915194Jul 3, 1997Jun 22, 1999The United States Of America As Represented By The Administrator Of National Aeronautics And Space AdministrationMethod for growth of crystal surfaces and growth of heteroepitaxial single crystal films thereonUS6051849Feb 27, 1998Apr 18, 2000North Carolina State UniversityGallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layerUS6064078May 22, 1998May 16, 2000Xerox CorporationFormation of group III-V nitride films on sapphire substrates with reduced dislocation densitiesUS6100104Sep 21, 1998Aug 8, 2000Siemens AktiengesellschaftMethod for fabricating a plurality of semiconductor bodiesUS6100111Apr 6, 1998Aug 8, 2000Abb Research Ltd.Method for fabricating a silicon carbide deviceUS6121121Jul 27, 1999Sep 19, 2000Toyoda Gosei Co., LtdMethod for manufacturing gallium nitride compound semiconductorUS6153010Apr 9, 1998Nov 28, 2000Nichia Chemical Industries Ltd.Method of growing nitride semiconductors, nitride semiconductor substrate and nitride semiconductor deviceUS6156584Mar 26, 1998Dec 5, 2000Rohm Co., Ltd.Method of manufacturing a semiconductor light emitting deviceUS6255198 *Nov 17, 1999Jul 3, 2001North Carolina State UniversityMethods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed therebyUS6265289 *Jun 7, 1999Jul 24, 2001North Carolina State UniversityMethods of fabricating gallium nitride semiconductor layers by lateral growth from sidewalls into trenches, and gallium nitride semiconductor structures fabricated therebyUSRE34861Oct 9, 1990Feb 14, 1995North Carolina State UniversitySublimation of silicon carbide to produce large, device quality single crystals of silicon carbideCA2258080A1Apr 9, 1998Oct 22, 1998Nichia Kagaku Kogyo KkNitride semiconductor growth method, nitride semiconductor substrate, and nitride semiconductor deviceEP0551721A2Nov 12, 1992Jul 21, 1993Amano, HiroshiGallium nitride base semiconductor device and method of fabricating the sameEP0852416A1Sep 17, 1996Jul 8, 1998Hitachi, Ltd.Semiconductor material, method of producing the semiconductor material, and semiconductor deviceEP0942459A1Apr 9, 1998Sep 15, 1999Nichia Chemical Industries, Ltd.Method of growing nitride semiconductors, nitride semiconductor substrate and nitride semiconductor deviceEP0951055A2Nov 10, 1998Oct 20, 1999Hewlett-Packard CompanyEpitaxial material grown laterally within a trenchJPH057016A Title not availableJPH0541536A Title not availableJPH0818159A Title not availableJPH0864791A Title not availableJPH0993315A Title not availableJPH03132016A Title not availableJPH04188678A Title not availableJPH08116093A Title not availableJPH08125251A Title not availableJPH08153931A Title not availableJPH09174494A Title not availableJPH09181071A Title not availableJPH09201477A Title not availableJPH09277448A Title not availableJPH09290098A Title not availableJPH09324997A Title not availableJPH11145516A Title not availableWO1997011518A1Sep 17, 1996Mar 27, 1997Hitachi, Ltd.Semiconductor material, method of producing the semiconductor material, and semiconductor deviceWO1998047170A1Apr 9, 1998Oct 22, 1998Nichia Chemical Industries, Ltd.Method of growing nitride semiconductors, nitride semiconductor substrate and nitride semiconductor device* Cited by examinerNon-Patent CitationsReference1Akasaki et al., Effects of AlN Buffer Layer on Crystallographic Structure and on Electrical and Optical Properties of GaN and Gal-xAlxN (0<x≲0.4) Films Grown on Sapphire Substrate by MOVPE, Journal of Crystal Growth, vol. 98, 1989, pp. 209-219.2Allegretti et al., In-situ Observation of GaAs Selective Epitaxy on GaAs (111)B Substrates, Journal of Crystal Growth, vol. 146, 1995, pp. 354-358.3Allegretti et al., Periodic Supply Epitaxy: A New Approach for the Selective Area Growth of GaAs by Molecular Beam Epitaxy, Journal of Crystal Growth, vol. 156, 1995, pp. 1-10.4Amano et al., Metalorganic Vapor Phase Epitaxial Growth of a High Quality GaN Film Using an AlN Buffer Layer, Applied Physics Letters, vol. 48, No. 5, Feb. 3, 1986, pp. 353-355.5Boo et al., Growth of Hexagonal GaN Thin Films on Si(111) with Cubic SiC Buffer Layers, Journal of Crystal Growth 189-190, 1998, pp. 183-188.6Chen et al., Dislocation Reduction in GaN Thin Films Via Lateral Overgrowth From Trenches, Applied Physics Letters, vol. 75, No. 14, Oct. 4, 1999, pp. 2062-2063.7Chen et al., Silicon-on-Insulator: Why, How, and When, AIP Conference Proceedings, vol. 167, No. 1, Sep. 15, 1988, pp. 310-319.8Doverspike et al., The Effect of GaN and AlN Buffer Layers on GaN Film Properties Grown on Both C-Plane and A-Plane Sapphire, Journal of Electronic Materials, vol. 24, No. 4, 1995, pp. 269-273.9Gallium Nitride-2000-Technology, Status, Applications, and Market Forecasts, Strategies Unlimited, Report SC-23, May 2000.10Gehrke et al., Pendeo-Epitaxial Growth of Gallium Nitride on Silicon Substrates, Journal of Electronic Materials, vol. 29, No. 3, Mar. 2000, pp. 306-310.11Gehrke et al., Pendeo-Epitaxy of Gallium Nitride and Aluminum Nitride Films and Heterostructures on Silicon Carbide Substrate, MRS Internet J. Semicond. Res. 4S1, G3.2, 1999, 6 pp.12Givargizov, Other Approaches to Oriented Crystallization on Amorphous Substrates, Chapter 4, Oriented Crystallization on Amorphous Substrates, Plenum Press, 1991, pp. 221-264.13Gustafsson et al., Investigations of High Quality GexSil-x Grown by Heteroepitaxial Lateral Overgrowth Using Cathoduluminescence, Inst. Phys. Conf. Ser. No. 134: Section 11, Micros. Semicond. Mater. Conf., Oxford, Apr. 5-8, 1993, pp. 675-678.14Hiramatsu et al., Growth Mechanism of GaN Grown on Sapphire With AlN Buffer Layer by MOVPE, Journal of Crystal Growth, vol. 115, 1991, pp. 628-633.15Hiramatsu et al., Selective Area Growth and Epitaxial Lateral Overgrowth of GaN, Properties, Processing and Applications of Gallium Nitride and Related Semiconductors, EMIS Datareviews Series No. 23, 1998, pp. 440-446.16Honda et al., Selective Area Growth of GaN Microstructures on Patterned (111) and (001) Si Substrates, 4th European Workshop on GaN, Nottingham, UK, Jul. 2-5, 2000.17International Search Report, PCT/US99/04346, Jun. 9, 1999.18International Search Report, PCT/US99/12967, Oct. 18, 1999.19International Search Report, PCT/US99/27358, Apr. 28, 2000.20International Search Report, PCT/US99/28056, Apr. 26, 2000.21Ishiwara et al., Lateral Solid Phase Epitaxy of Amorphous Si Films on Si Substrates With SiO2 Patterns, Applied Physics Letters, vol. 43, No. 11, Dec. 1, 1983, pp. 1028-1030.22Jastrzebski, SOI by CVD: Epitaxial Lateral Overgrowth (ELO) Process-Review, Journal of Crystal Growth, vol. 63, 1983, pp. 493-526.23Joyce et al., Selective Epitaxial Deposition of Silicon, Nature, vol. 4840, Aug. 4, 1962, pp. 485-486.24Kapolnek et al., "Anisotropic Epitaxial Lateral Growth in GaN Selective Area Epitaxy", Appl. Phys. Lett. 71 (9), Sep. 1, 1997, pp. 1204-1206.25Kapolnek et al., "Selective Area Epitaxy of GaN for Electron Field Emission Devices", Journal of Crystal Growth, 5451, 1996, pp. 1-4.26Kato et al., "Selective Growth of Wurtzite GaN and AlxGa1-xN on GaN/Sapphire Substrates by Metalorganic Vapor Phase Epitaxy", Journal of Crystal Growth, 144, 1994, pp. 133-140.27Kinoshita et al., Epitaxial Laterla Overgrowth of Si on Non-Planar Substrate, Journal of Crystal Growth, vol. 115, 1991, pp. 561-566.28Kuznia et al., Influence of Buffer Layers on the Deposition of High Quality Single Crystal GaN Over Sapphire Substrates, J. Appl. Phys., vol. 73, No. 9, May 1, 1993, pp. 4700-4702.29Leo Unmasked by Pendeo-Epitaxy, Compound Semiconductor, Mar. 1999, p 16.30Linthicum et al., Pendeoepitaxy of Gallium Nitride Thin Films, Applied Physics Letters, vol. 75, No. 2, Jul. 12, 1999, pp. 196-198.31Linthicum et al., Process Routes for Low-Defect Density GaN on Various Substrates Employing Pendeo-Epitaxial Growth Techniques, MRS Internet Journal of Nitride Semiconductor Research, Fall Meeting of the Materials Research Society, vol. 4S1, No. G4.9, Nov. 30, 1998-Dec. 4, 1998.32Marchand et al., Microstructures of GaN Laterally Overgrown by Metalorganic Chemical Vapor Deposition, Applied Physics Letters, vol. 73, No. 6, Aug. 10, 1998, pp. 747-749.33Nakamura et al., High-Power, Long-Lifetime InGaN/GaN/AlGaN-Based Laser Diodes Grown on Pure GaN Substrates, Jpn. J. Appl. Phys., vol. 37, Mar. 15, 1998, pp. L309-L312.34Nakamura et al., InGaN/GaN/AlGaN-Based Laser Diodes Grown on GaN Substrates With a Fundamental Transverse Mode, Jpn. J. Appl. Phys., vol. 37, Sep. 15, 1998, pp. L1020-L1022.35Nakamura et al., InGaN/GaN/AlGaN-Based Laser Diodes With Modulation-Doped Strained-Layer Superlattices, Jpn. J. Appl. Phys., vol. 36, Dec. 1, 1997, pp. L1568-L1571.36Nakamura et al., Violet InGaN/GaN/AlGaN-Based Laser Diodes Operable at 50� C. With a Fundamental Transverse Mode, Jpn. J. Appl. Phys. vol. 38, Part 1, No. 3A, Mar. 1, 1999, pp. L226-L229.37Nakamura, GaN Growth Using GaN Buffer Layer, Japanese Journal of Applied Physics, vol. 30, No. 10A, Oct. 1991, pp. L1705-L1707.38Nakamura, InGaN/GaN/AlGaN-Based Laser Diodes, Properties, Processing and Applications of Gallium Nitride and Related Semiconductors, EMIS Datareviews Series No. 23, 1998, pp. 587-595.39Nakamura, InGaN-Based Violet Laser Diodes, Semicond. Sci. Technol., 14, 1999, pp. R27-R40.40Nam et al., "Selective Growth of GaN and Al0.2Ga0.8N on GaN/AlN/6H-SiC(0001) Multilayer Substrates Via Organometallic Vapor Phase Epitaxy", Proceedings MRS, Dec. 1996, 6 pp.41Nam et al., Lateral Epitaxial Overgrowth of GaN Films on SiO2 Areas Via Metalorganic Vapor Phase Epitaxy, Journal of Electronic Materials, vol. 27, No. 4, 1998, pp. 233-237.42Nam et al., Lateral Epitaxy of Low Defect Density GaN Layers Via Organometallic Vapor Phase Epitaxy, Appl. Phys. Lett., vol. 71, No. 18, Nov. 3, 1997, pp. 2638-2640.43Nam, et al., "Growth of GaN and Al0.2Ga0.8N on Patterned Substrates Via Organometallic Vapor Phase Epitaxy", Jpn. J. Appl. Phys., vol. 36, Part 2, No. 5A, May 1, 1997, pp. 532-535.44Naritsuka et al., Epitaxial Lateral Overgrowth of InP by Liquid Phase Epitaxy, Journal of Crystal Growth, vol. 146, 1995, pp. 314-318.45Nishinaga et al., Epitaxial Lateral Overgrowth of GaAs by LPE, Japanese Journal of Applied Physics, vol. 27, No. 6, Jun. 1988, pp. L964-L967.46Rathman et al., Lateral Epitaxial Overgrowth of Silicon on SiO2, Journal of the Electrochemical Society, Oct. 1982, pp. 2303-2306.47Sakai et al., Transmission Electron Microscopy of Defects in GaN Films Formed by Epitaxial Lateral Overgrowth, vol. 73, No. 4, Jul. 27, 1998, pp. 481-483.48Sakai, Defect Structure in Selectively Grown GaN Films With Low Threading Dislocation Density, Appl. Phys. Lett., vol. 71, No. 16, Oct. 20, 1997, pp. 2259-2261.49Sakawa et al., Effect of Si Doping on Epitaxial Lateral Overgrowth of GaAs on GaAs-Coated Si Substrate, Japanese Journal of Applied Physics, Part 2, No. 3B, Mar. 15, 1992, pp. L359-L361.50Shaw, Selective Epitaxial Deposition of Gallium Arsenide in Holes, Journal of Electrochemical Society, Sep. 1966, pp. 904-908.51Steckl et al., SiC Rapid Thermal Corbonization of the (111)Si Semiconductor-on-Insulator Structure and Subsequent Metalorganic Chemical Vapor Deposition, Appl. Phys. Let., 69 (15), Oct. 7, 1996, pp. 2264-2266.52Suzuki et al., Epitaxial Lateral Overgrowth of Si by LPE With Sn Solution and Its Orientation Dependence, Japanese Journal of Applied Physics, vol. 28, No. 3, Mar. 1989, pp. 440-445.53Suzuki et al., Si LPE Lateral Overgrowth From a Ridge Seed, Japanese Journal of Applied Physics, vol. 29, No. 12, Dec., 1990, pp. 2685-2689.54Suzuki et al., The Sources of Atomic Steps in Epitaxial Lateral Overgrowth of Si, Journal of Crystal Growth, vol. 99, 1989, pp. 229-234.55Tausch, Jr. et al., A Novel Crystal Growth Phenomenon: Single Crystal GaAs Overgrowth Onto Silicon Dioxide, Journal of the Electrochemical Society, Jul. 1965, pp. 706-709.56Thomson et al., Ranges of Deposition Temperatures Applicable for Metalorganic Vapor Phase Epitaxy of GaN Films Via the Technique of Pendeo-Epitaxy, MRS Internet J. Semicond. Res. 4S1, G3.37, 1999, 6 pp.57U.S. application No. 09/031,843, Davis et al., filed Feb. 27, 1998.58U.S. application No. 09/198,784, Linthicum et al., filed Nov. 24, 1998.59U.S. application No. 09/327,136, Zhevela et al., filed Jun. 7, 1999.60U.S. application No. 09/441,753, Gehrke et al., filed Nov. 17, 1999.61U.S. application No. 09/441,754, Linthicum et al., filed Nov. 17, 1999.62U.S. application No. 09/468,995, Linthicum et al., filed Dec. 21, 2000.63U.S. application No. 09/501,051, Linthicum et al., filed Feb. 9, 2000.64U.S. application No. 09/512,242, Gehrke et al., filed Feb. 24, 2000.65U.S. application No. 09/525,721, Davis et al., filed Mar. 14, 2000.66U.S. application No. 09/736,569, Gehrke et al., filed Dec. 13, 2000.67U.S. application No. 60/088,761, Linthicum et al., filed Jun. 10, 1998.68U.S. application No. 60/109,674, Linthicum et al., filed Nov. 24, 1998.69U.S. application No. 60/109,860, Gehrke et al., filed Nov. 24, 1998.70U.S. application No. 60/170,433, Gehrke et al., filed Dec. 13, 1999.71Ujiie et al., Epitaxial Lateral Overgrowth of GaAs on a Si Substrate, Jpn. J. Appl. Phys., vol. 28, 1989, p. L337-L339.72Usui et al., "Thick GaN Epitaxial Growth With Low Dislocation Density by Hydride Vapor Phase Epitaxy", Jpn. J. Appl. Phys., vol. 36, Part 2, No. 7B, Jul. 15, 1997, pp. 899-902.73Watanabe et al., The Growth of Single Crystalline GaN on a Si Substrate Using AlN As An Intermediate Layer, Journal of Crystal Growth, vol. 128, 1993, pp. 391-396.74Weeks et al, "GaN Thin Films Deposited Via Organometallic Vapor Phase Epitaxy on alpha(6H)-SiC(0001) Using High-Temperature Monocrystalline AlN Buffer Layers", Appl. Phys. Lett. 67 (3), Jul. 17, 1995, pp. 401-403.75Weeks et al, "GaN Thin Films Deposited Via Organometallic Vapor Phase Epitaxy on α(6H)-SiC(0001) Using High-Temperature Monocrystalline AlN Buffer Layers", Appl. Phys. Lett. 67 (3), Jul. 17, 1995, pp. 401-403.76Wu et al., Growth and Characterization of SiC Films on Large-Area Si Wafers by APCVD-Temperature Dependence, Materials Science Forum, vols. 264-268, 1998, pp. 179-182.77Yamaguchi et al, Lateral Supply Mechanisms in Selective Metalorganic Chemical Vapor Deposition, Jpn. Appl. Phys., vol. 32 (1993), pp. 1523-1527.78Yoshida et al., Improvements on the Electrical and Luminescent Properties of Reactive Molecular Beam Epitaxially Grown GaN Films by Using AlN-Coated Sapphire Substrates, Applied Physics Letters, vol. 42, No. 5, Mar. 1, 1983, pp. 427-429.79Zhang et al., Epitaxial Lateral Overgrowths of GaAs on (001) GaAs Substrates by LPE: Growth Behavior and Mechanism, Journal of Crystal Growth, vol. 99, 1990, pp. 292-296.80Zhang et al., LPE Lateral Overgrowth of GaP, Japanese Journal of Applied Physics, vol. 29,No. 3, Mar. 1990, pp. 545-550.81Zheleva et al., Dislocation Density Reduction Via Lateral Epitaxy in Selectively Grown GaN Structures, Appl. Phys. Lett., vol. 71, No. 17, Oct. 27, 1997, pp. 2472-2474.82Zheleva et al., Pendeo-Epitaxy: A New Approach for Lateral Growth of Gallium Nitride Films, Journal of Electronic Materials, vol. 28, No. 4, Feb. 1999, pp. L5-L8.83Zheleva et al., Pendeo-Epitaxy-A New Approach for Lateral Growth of GaN Structures, MRS Internet Journal of Nitride Semiconductor Research, 1999, Online!, vol. 4S1, No. G3.38, Nov. 30, 1998-Dec. 4, 1998.84Zheleva et al., Pendeo-Epitaxy—A New Approach for Lateral Growth of GaN Structures, MRS Internet Journal of Nitride Semiconductor Research, 1999, Online!, vol. 4S1, No. G3.38, Nov. 30, 1998-Dec. 4, 1998.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6864160 *Apr 3, 2002Mar 8, 2005North Carolina State UniversityMethods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride postsUS6960526Oct 10, 2003Nov 1, 2005The United States Of America As Represented By The Secretary Of The ArmyMethod of fabricating sub-100 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effect transistors (FETs) having multi-watt output power at millimeter-wave frequenciesUS20060208280 *Mar 15, 2005Sep 21, 2006Smith Richard PGroup III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditionsUS20060226412 *Apr 11, 2005Oct 12, 2006Saxler Adam WThick semi-insulating or insulating epitaxial gallium nitride layers and devices incorporating sameUS20060226413 *Apr 11, 2005Oct 12, 2006Saxler Adam WComposite substrates of conductive and insulating or semi-insulating group III-nitrides for group III-nitride devicesUS20060244010 *Apr 29, 2005Nov 2, 2006Saxler Adam WAluminum free group III-nitride based high electron mobility transistors and methods of fabricating sameUS20060244011 *Apr 29, 2005Nov 2, 2006Saxler Adam WBinary group III-nitride based high electron mobility transistors and methods of fabricating sameUS20060267043 *May 27, 2005Nov 30, 2006Emerson David TDeep ultraviolet light emitting devices and methods of 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devices having features with reduced edge curvature* Cited by examinerClassifications U.S. Classification438/479, 257/E21.131, 257/E21.125International ClassificationH01L33/00, H01L21/205, C30B29/38, H01S5/323, C30B25/02, H01L21/20Cooperative ClassificationC30B29/406, H01L21/02378, H01L21/0265, H01L21/0254, H01L21/02458, C30B25/02, H01L21/02639European ClassificationC30B25/02, C30B29/40B2, H01L21/02K4A1A2, H01L21/02K4E3S7P, H01L21/02K4E3S3, H01L21/02K4C1B1, H01L21/02K4B1B1Legal EventsDateCodeEventDescriptionJul 13, 2004ASAssignmentOwner name: NAVY, SECRETARY OF THE UNITED STATE OF AMERICA, VIFree format text: CONFIRMATORY LICENSE;ASSIGNOR:NORTH CAROLINA STATE UNIVERSITY;REEL/FRAME:015552/0166Effective date: 20040326Jul 13, 2004CCCertificate of correctionOct 24, 2005FPAYFee paymentYear of fee payment: 4Oct 23, 2009FPAYFee paymentYear of fee payment: 8Oct 23, 2013FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - 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