Source: https://patents.justia.com/patent/9391143
Timestamp: 2019-10-15 06:04:26
Document Index: 587404987

Matched Legal Cases: ['§120', 'Application No. 2012', 'art 1', 'Application No. 2001', 'art 1', 'Application No. 10', 'Application No. 10', 'Application No. 2012', 'Application No. 2001', 'Application No. 2013', 'Application No. 2001', 'art 1', 'art 1']

US Patent for Method for low temperature bonding and bonded structure Patent (Patent # 9,391,143 issued July 12, 2016) - Justia Patents Search
Justia Patents Having Insulated GateUS Patent for Method for low temperature bonding and bonded structure Patent (Patent # 9,391,143)
Dec 2, 2015 - ZIPTRONIX, INC.
This application is a continuation of, and claims the benefit of priority under 35 U.S.C. §120 from U.S. Ser. No. 14/754,111, filed Jun. 29, 2015, which is a division of U.S. Ser. No. 14/197,070, filed Mar. 4, 2014, which is a division of U.S. Ser. No. 13/341,273, filed Dec. 30, 2011, which is a continuation of U.S. Ser. No. 12/954,740, filed Nov. 26, 2010, now U.S. Pat. No. 8,153,505, which is a continuation of U.S. Ser. No. 12/720,368 filed Mar. 9, 2010, now U.S. Pat. No. 7,871,898, which is a continuation of U.S. Ser. No. 11/980,664 filed Oct. 31, 2007, now U.S. Pat. No. 7,807,549, which is a continuation of U.S. Ser. No. 10/913,441 filed Aug. 9, 2004, now U.S. Pat. No. 7,387,944, which is a continuation of U.S. Ser. No. 09/505,283, filed Feb. 16, 2000, now U.S. Pat. No. 6,902,987, the entire contents of each of which are incorporated herein by reference.
A gas plasma treatment prior to bonding in ambient is known to enhance the bonding energy of bonded silicon pairs at low or room temperature. See, for example, G. L. Sun, Q.-Y. Tong, et al., J. de Physique, 49(C4), 79 (1988); G. G. Goetz, Proc. of 1st Symp. on Semicond. Wafer Bonding: Science, Technol. and Applications, The Electrochem. Soc., 92-7, 65 (1992); S. Farrens et al., J. Electroch. Soc., 142,3950 (1995) and Amirffeiz et al, Abstracts of 5th Symp. on Semi. Wafer Bonding: Science, Tech. and Appl., The Electrochemical Society, 99-2, Abstract No. 963 (1999). Although these treatments have increased the bond energy obtainable at low or room temperature, they have only been demonstrated with planar silicon wafers or with silicon wafers using a plasma process that results in oxide being grown on the wafers during the plasma process. Moreover, these treatments have only been used to increase the bond energy by charging or damaging the surface. Furthermore, these treatments have not been used or shown to be applicable to deposited dielectrics or other materials.
Annealing the bonded wafers during bonding may increase the bonding strength. The annealing temperature should be below 200EC and may be typically in the range of 75-100EC. Storing the bonded wafers under vacuum may facilitate the removal of residual gasses from the bonding surfaces, but is not always necessary.
The hydrogen bonded Si—NH2: Si—OH groups or Si—NH2: Si—NH2 groups across the bonding surfaces can polymerize at room temperature in forming Si—O—Si or Si—N—N—Si (or Si—N—Si) covalent bonds:
Since reaction (2) is reversible only at relatively high temperatures of ˜500EC, the formed siloxane bonds should not be attacked by NH3 at lower temperatures. It is known that H2 molecules are small and diffuse about 50 times quicker than water molecules in oxide. The existence of a damaged layer near the surface of an adequate thickness i.e. a few nm, will facilitate the diffusion or dissolution of NH3, and HF and hydrogen in reactions (2), (3), (4) and/or (5) in this layer and enhancement of the chemical bond. The three reactions result in a higher bonding energy of SiO2/SiO2 bonded pairs at room temperature after a period of storage time to allow NH3 or H2 to diffuse away.
γ = 3 ⁢ ⁢ t b 2 ⁢ E 1 ⁢ t w ⁢ ⁢ 1 3 ⁢ E 2 ⁢ t tw ⁢ ⁢ 2 3 16 ⁢ ⁢ L 4 ⁡ ( E 1 ⁢ t w ⁢ ⁢ 1 3 + E 2 ⁢ t w ⁢ ⁢ 2 3 )
forming a planarized insulating material on a semiconductor wafer;
etching the planarized insulating material in a reaction space;
terminating the planarized insulating material with a nitrogen-containing species by at least one of: a nitrogen-containing plasma during the etching, and a nitrogen-containing solution after the etching;
bringing a first material into direct contact with the terminated and planarized insulating material outside the reaction space; and
forming a chemical bond between the terminated and planarized insulating material and the first material.
2. The method of claim 1, wherein the etching the planarized insulating material is conducted in a vacuum chamber, the reaction space comprising the vacuum chamber.
3. The method of claim 1, wherein the etching the planarized insulating material is conducted in a plasma chamber, the reaction space comprising the plasma chamber.
4. The method of claim 1, wherein the etching and the terminating comprise exposing the planarized insulating material to the plasma etching process in a plasma chamber, the reaction space comprising the plasma chamber.
5. The method of claim 4, wherein the exposing the planarized insulating material to the plasma etching process comprises exposing the planarized insulating material to a reactive ion etching process.
6. The method of claim 4, wherein the exposing the planarized insulating material to the plasma etching process in the plasma chamber comprises using nitrogen gas.
7. The method of claim 1, wherein the terminating comprises exposing the planarized insulating material to a nitrogen-containing solution after the etching.
8. The method of claim 7, wherein the nitrogen-containing solution comprises an ammonia-based solution.
9. The method of claim 1, wherein the first material comprises a second planarized insulating material on a second semiconductor wafer.
10. The method of claim 9, wherein the first material comprises silicon oxide.
11. The method of claim 1, wherein the bringing into direct contact comprises bringing into direct contact the terminated planarized insulating material and a silicon material having a native oxide, the first material comprising the silicon material.
12. The method of claim 1, further comprising, after the terminating, rinsing the insulating material.
13. The method of claim 12, wherein the rinsing comprises immersing the insulating material in deionized water.
14. The method of claim 1, wherein the bringing into direct contact is performed at room temperature.
15. The method of claim 1, wherein the bringing into direct contact is conducted in air.
16. The method of claim 1, wherein the forming the planarized insulating material comprises forming silicon oxide on the semiconductor wafer.
17. The method of claim 1, further comprising forming a bond between the planarized insulating material and the first material with a strength of at least 500 mJ/m2 without annealing at more than about 200° C.
18. The method of claim 1, further comprising forming a bond between the planarized insulating material and the first material with a strength of at least 2000 mJ/m2 without annealing at more than about 200° C.
19. The method of claim 1, further comprising annealing the planarized insulating material and the first material at a temperature of no more than about 200° C. after the bringing into direct contact.
20. The method of claim 1, wherein the planarized insulating material has a surface roughness between about 0.5 and 1.5 nm after the etching and before the bringing into direct contact.
21. A bonded structure comprising:
wherein the first bonding surface is an etched surface terminated with a nitrogen-containing species, and
wherein the first and second bonding surfaces are in direct contact with each other and bonded together with a chemical bond without any intervening adhesive.
22. The structure of claim 21, further comprising at least one integrated circuit in the first semiconductor material.
23. The structure of claim 21, wherein the second material comprises silicon.
24. The structure of claim 21, wherein the chemical bond has a strength of at least 500 mJ/m2.
25. The structure of claim 21, wherein the chemical bond has a strength of at least 2000 mJ/m2.
26. The structure of claim 21, wherein the planarized insulating material comprises silicon oxide.
27. The structure of claim 21, wherein the second bonding surface comprises an etched surface.
28. The structure of claim 27, wherein the etched surface of the second bonding surface is terminated with a nitrogen-containing species.
29. The structure of claim 21, wherein the first bonding surface is terminated with a nitrogen-containing species by at least one of a nitrogen-containing plasma during etching and a nitrogen-containing solution after etching.
30. The structure of claim 21, wherein the chemical bond is a covalent bond.
31. A bonding method, comprising:
etching the planarized insulating material;
bringing a first material into direct contact with the terminated and planarized insulating material; and
32. A bonding method, comprising:
exposing the planarized insulating material to a plasma process in a plasma chamber using a nitrogen-containing gas;
terminating the planarized insulating material with a species;
bringing into direct contact the terminated and planarized insulating material and a first material outside of said plasma chamber; and
33. The bonding method of claim 32, wherein the species comprises nitrogen.
20020055208 May 9, 2002 Ohtani
WO 2004/071700 August 2004 WO
WO 2006/111533 October 2006 WO
First Office Action (English translation) mailed Oct. 6, 2015, issued in Japanese Patent Application No. 2012-107053, 7 pages.
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Patent number: 9391143
Patent Publication Number: 20160086913
Application Number: 14/957,501
International Classification: H01L 21/30 (20060101); H01L 21/46 (20060101); H01L 29/16 (20060101); H01L 21/02 (20060101); H01L 21/20 (20060101); H01L 21/311 (20060101); H01L 21/762 (20060101); H01L 23/00 (20060101); H01L 29/06 (20060101); H01L 21/322 (20060101); H01L 27/085 (20060101);