Source: https://patents.google.com/patent/JP4842719B2/en
Timestamp: 2019-11-15 11:14:32
Document Index: 89170976

Matched Legal Cases: ['art 502', 'art 503', 'art 503', 'art 502', 'art 502', 'art 1101', 'art 1102', 'art 1606', 'art 1605', 'art 1605', 'art 1606']

JP4842719B2 - Storage system and data protection method thereof - Google Patents
Storage system and data protection method thereof Download PDF
JP4842719B2
JP4842719B2 JP2006178487A JP2006178487A JP4842719B2 JP 4842719 B2 JP4842719 B2 JP 4842719B2 JP 2006178487 A JP2006178487 A JP 2006178487A JP 2006178487 A JP2006178487 A JP 2006178487A JP 4842719 B2 JP4842719 B2 JP 4842719B2
JP2006178487A
JP2008009635A (en
2006-06-28 Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
2008-01-17 Publication of JP2008009635A publication Critical patent/JP2008009635A/en
2011-12-21 Publication of JP4842719B2 publication Critical patent/JP4842719B2/en
The present invention relates to a storage system using a flash memory as a recording medium and a data protection method thereof.
A storage system generally includes a non-volatile recording medium that can be randomly accessed. The randomly accessible non-volatile recording medium is, for example, a magnetic disk or an optical disk. Currently, mainstream storage systems have many small disk drives. Along with the progress of semiconductor technology, a batch erasable nonvolatile semiconductor memory has been developed. A non-volatile semiconductor memory that can be collectively erased is, for example, a flash memory. A storage system using a flash memory as a recording medium is superior in life, power saving, access time, and the like as compared with a storage system having a large number of small disk drives.
Here, the flash memory will be described. In a flash memory, a block is a storage area in a unit for erasing data at once, and a page is a storage area in a unit for reading and writing data. Flash memory cannot rewrite data directly due to its characteristics. That is, the flash memory saves the stored effective data when rewriting the stored data. Next, the stored data is erased in units of blocks. Then, data is newly written in the block from which the data has been erased.
More specifically, the flash memory can rewrite “1” to “0”, but cannot rewrite “0” to “1”. Therefore, the flash memory erases the entire block when rewriting data. As described above, rewriting data in the flash memory is accompanied by erasing the block.
However, the time required for erasing one block of the flash memory is approximately one digit longer than the time required for writing one page. Therefore, if one block is erased every time one page is rewritten, the data rewriting performance of the flash memory is extremely lowered. That is, in the flash memory, it is indispensable to write data with an algorithm that can hide the erase time.
In flash memory, the number of times that a block can be erased is limited. For example, an erase count of up to 100,000 times per block is guaranteed. A block in which the number of times of erasing has increased due to concentration of data rewriting has a problem that data cannot be erased and cannot be used. For this reason, in a storage system that uses a flash memory as a recording medium, an erasure count leveling process is required to prevent concentration of erasure processes on specific blocks.
In order to conceal the erasure time and level the number of erasures, address conversion processing is performed in the flash memory module when data is written. The flash memory module includes one or more flash memory chips and a memory controller for controlling data transfer to the flash memory chips. In order to avoid the concentration of writing at a specific physical address, the memory controller transfers the logical address received as the write destination address from the host computer or storage device controller to the physical address that is the write destination address in the flash memory chip. Has a function to convert. At this time, the problem is an address error occurring in the memory controller. If the memory controller generates an error when converting from a logical address to a physical address, data is written to the wrong physical address. That is, there is no problem in the write data itself, but there is a problem that desired data cannot be read at the time of reading because the written physical address is wrong.
As a technique for solving this problem, for example, a technique disclosed in Japanese Patent Laid-Open No. 2001-202295 is known. This technique protects data from address errors in the recording medium when the hard disk drive is used as the recording medium. More specifically, a protection code including a logical address value for each logical data block in the hard disk drive is added to the data and written to the hard disk drive. When data is read from the hard disk drive, the protection code added to each logical data block is checked.
Furthermore, US Patent Publication No. 2004 / 0148461A1 discloses a storage system that ensures compatibility between recording media having different data management units.
JP 2001-202295 A US Published Patent 2004 / 0148461A1
The flash memory virtualizes addresses in units of pages and reads and writes data. The page size varies depending on the chip type and generation. For example, the page size of the current flash memory chip is 528 bytes or 2112 bytes, and the size of the storage area into which data can actually be written is 512 bytes or 2048 bytes, respectively. The remaining part of the page (for example, 16 bytes excluding 512 bytes from 528 bytes or 64 bytes excluding 2048 bytes from 2112 bytes) is used for information and error correction for the memory controller to manage addresses in units of pages. It is used as a management area for storing error correction codes to be performed. As the flash memory capacity increases, the page size is expected to increase in the future.
A flash memory module intended to replace a hard disk drive as a storage medium of a storage system has a hard disk drive compatible interface. The storage controller recognizes a flash memory module having hard disk drive compatibility as, for example, a hard disk drive having 512 bytes per sector. That is, the storage controller cannot recognize the data unit that has been address-converted inside the flash memory module having the hard disk drive compatible interface. Further, the page size differs depending on the type and generation of the flash memory chip mounted in the flash memory module. In the above-described address error countermeasure according to the prior art, it is necessary for the storage controller to add a protection code and write data for each data size to be converted.
However, as described above, in a flash memory module having a hard disk drive compatible interface or a flash memory module in which the specification of the flash memory chip is unknown, the data size to be protected from an address error is unknown. For this reason, it is difficult to protect data from address errors in the flash memory module by the prior art.
Furthermore, in a hard disk drive that requires high reliability, the capacity per sector is set to 520 bytes, and data and a protection code are managed as a set. On the other hand, the data size writable per page of the flash memory is a multiple of 512 bytes, excluding the storage area used for management by the memory controller. If data managed in units of 520 bytes is written to a page of the flash memory as it is, data in units of 520 bytes may be written to the flash memory across page boundaries. This means that the data in 520 bytes and the protection code are written on different pages, and the data separated from the protection code is not protected from an address error. Therefore, in the conventional technology, it is difficult to protect data across page boundaries from address errors.
The present invention has been made in view of the above-described problems, and a storage system capable of correcting an address error in a flash memory module having a data management unit different from the data management unit of a disk drive, and its It is an object to provide a data protection method.
In order to solve the above problems, a storage system according to the present invention includes a flash memory module having a flash memory chip, a memory controller that controls reading and writing of data to the flash memory chip, and reading and writing to the flash memory chip. A storage controller having a cache memory for temporarily storing data to be stored. On the cache memory, data read from and written to the flash memory chip is managed in units of the first data length. Data read from and written to the flash memory chip is managed in units of pages. The storage area per page includes a storage area having a second data length that can be read and written from the storage controller, and a storage area for storing page management information. When writing data to the flash memory chip, the storage controller generates a protection code that can specify address information of the write destination page, and further, the write data and the protection code are combined to become the second data length. The data on the cache memory managed in the first data length unit is divided, and the write data and the protection code are combined and written to the flash memory chip in the second data length unit. The storage controller checks the presence or absence of a read error by comparing the address information specified from the protection code added to the data read from the flash memory chip and the address information of the data to be read. According to this configuration, it is possible to correct an address error in a flash memory module having a data management unit different from the data management unit of the disk drive.
In a preferred aspect of the present invention, the storage controller further includes a database that holds a correspondence relationship between each specification of the flash memory module and the second data length. Since the second data length may differ depending on the specifications of the flash memory module, the storage controller is provided with a database that holds the correspondence between each specification of the flash memory module and the second data length. Can adjust the second data length according to the specification of the flash memory module connected to the storage controller.
In a preferred aspect of the present invention, the storage area provided by the flash memory module is configured in RAID. When an address error occurs in the data in any of the flash memory modules, the storage controller is stored in another flash memory module belonging to the same RAID group as the flash memory module that stores the data in which the address error has occurred. The data having the address error is restored in the second data length unit, and the data having the address error is overwritten with the restored data. With such a configuration, even if an address error occurs in data in any flash memory module, the data can be restored.
In a preferred aspect of the present invention, the protection code includes write time information. With such a configuration, data can be effectively protected from address errors, particularly for sequential data access.
In a preferred aspect of the present invention, the protection code includes an error detection code or a correction code for protecting data having the second data length. As the error detection code or correction code, for example, a CRC code, an LRC code, or a Hamming code is suitable.
A storage system according to another aspect of the present invention includes a flash memory module having a flash memory chip and a memory controller that controls reading and writing of data to and from the flash memory chip, and reading from and writing to the flash memory chip A storage controller having a cache memory for temporarily storing data. On the cache memory, data read from and written to the flash memory chip is managed in units of the first data length. Data read from and written to the flash memory chip is managed in units of pages. The storage area per page includes a storage area having a second data length that can be read and written from the storage controller, and a storage area for storing page management information. The storage controller includes a media determination unit for determining the type of recording medium connected to the storage controller. When the recording medium connected to the storage controller is a flash memory module, the storage controller generates a protection code that can specify address information of the write destination page when writing data to the flash memory chip, and further writes the write data The data in the cache memory managed in the first data length unit is divided so that the second data length is obtained by combining the data and the protection code, and the second data is obtained by combining the write data and the protection code. Write to flash memory chip in long units. The storage controller checks the presence or absence of a read error by comparing the address information specified from the protection code added to the data read from the flash memory chip and the address information of the data to be read. According to this configuration, the storage controller determines the type of the recording medium connected to the storage controller, and corrects an address error in the flash memory module having a data management unit different from the data management unit in the recording medium. be able to.
In a preferred aspect of the present invention, the first data length is a sector length of the hard disk drive.
In a preferred aspect of the present invention, the data having the first data length includes data and a protection code capable of specifying address information of a hard disk drive that is the data write destination.
In a preferred aspect of the present invention, the storage controller further includes a database that holds a correspondence relationship between each specification of the recording medium and the second data length. Since the second data length may be different depending on the specification of the recording medium, the storage controller can be provided with a database that holds the correspondence between each specification of the recording medium and the second data length. The second data length can be adjusted according to the specifications of the recording medium connected to the.
A storage system to which a data protection method according to the present invention is applied includes a flash memory module having a flash memory chip and a memory controller that controls reading and writing of data to and from the flash memory chip, and reading and writing to the flash memory chip. A storage controller having a cache memory for temporarily storing data to be stored, a storage area per page having a second data length that is readable and writable from the storage controller, and page management information And a storage area for storing. In this data protection method, the step of managing the data read / written to / from the flash memory chip in the first data length unit on the cache memory, and the address information of the write destination page can be specified when the data is written to the flash memory chip Generating a secure protection code, dividing the data on the cache memory managed in units of the first data length so that the write data and the protection code are combined into the second data length, and writing The step of writing the data and the protection code together in the second data length unit to the flash memory chip, the address information specified from the protection code added to the data read from the flash memory chip, and the data to be read Read error information by comparing Comprising a step of checking the free, the. According to this data protection method, an address error in a flash memory module having a data management unit different from the data management unit of the disk drive can be corrected.
According to the present invention, an address error in a flash memory module having a data management unit different from the data management unit of the disk drive can be corrected.
FIG. 1 shows a hardware configuration of a storage system 10 according to the present embodiment. The storage system 10 includes a storage controller SC and flash memory modules P00 to P33. The storage controller SC includes channel adapters CA0 and CA1, cache memories CM0 and CM1, storage adapters SA0 and SA1, and interconnection networks NW0 and NW1.
Although the storage controller SC has two channel adapters CA0 and CA1, cache memories CM0 and CM1, and two storage adapters SA0 and SA1, the storage controller SC may have three or more or one each. .
The interconnection networks NW0 and NW1 are, for example, switches or the like, and mutually connect the devices constituting the storage controller SC. Specifically, the interconnection networks NW0 and NW1 connect the channel adapter CA0, the cache memory CM0, and the storage adapter SA0 to each other. Similarly, the interconnection networks NW0 and NW1 interconnect the channel adapter CA1, the cache memory CM1, and the storage adapter SA1.
The channel adapter CA0 is connected to the host computer 100 via channels C00, C01, C02, and C03. Similarly, the channel adapter CA1 is connected to the host computer 100 via channels C10, C11, C12, and C13. The host computer 100 is a computer such as a personal computer, a workstation, or a mainframe computer, and requests the storage system 10 to read / write data. The cache memories CM0 and CM1 temporarily store data received from the channel adapters CA0 and CA1 or the storage adapters SA0 and SA1.
The storage adapter SA0 is connected to the flash memory modules P00 to P33. Specifically, the storage adapter SA0 is connected to the flash memory modules P00 to P03 via the channel D00. The storage adapter SA0 is connected to the flash memory modules P10 to P13 via the channel D01. The storage adapter SA0 is connected to the flash memory modules P20 to P23 via the channel D02. The storage adapter SA0 is connected to the flash memory modules P30 to P33 via the channel D03.
Similarly, the storage adapter SA1 is connected to the flash memory modules P00 to P33. Specifically, the storage adapter SA1 is connected to the flash memory modules P00 to P03 via the channel D10. The storage adapter SA1 is connected to the flash memory modules P10 to P13 via the channel D11. The storage adapter SA1 is connected to the flash memory modules P20 to P23 via the channel D12. The storage adapter SA1 is connected to the flash memory modules P30 to P33 via the channel D13.
The channel adapters CA0 and CA1 and the storage adapters SA0 and SA1 are connected to the maintenance terminal SVP. The maintenance terminal SVP transmits the setting information input from the administrator of the storage system 10 to the channel adapters CA0 and CA1 and / or the storage adapters SA0 and SA1.
The storage system 10 may include one adapter instead of the storage adapter SA0 and the channel adapter CA0. In this case, the one adapter performs processing of the storage adapter SA0 and the channel adapter CA0.
VDEV0 to VDEV3 are RAID (Redundant Arrays of Inexpensive Disks) groups. For example, the RAID group VDEV0 is composed of flash memory modules P00, P10, P20, and P30. If an error occurs in one of the flash memory modules belonging to the RAID group VDEV0, for example, the flash memory module P00, and data cannot be read, the other flash memory modules P10, P20, and P30 belonging to the RIAD group VDEV0 Can play data.
FIG. 2 shows the hardware configuration of the channel adapter CA0. The channel adapter CA0 includes a host channel interface 21, a cache memory interface 22, a network interface 23, a processor 24, a local memory 25, and a processor peripheral control unit 26.
The host channel interface 21 is an interface for connecting the channel adapter CA0 to the host computer 100 via the channels C00, C01, C02, and C03. The host channel interface 21 mutually converts the data transfer protocol on the channels C00, C01, C02, and C03 and the data transfer protocol inside the storage controller SC.
The cache memory interface 22 is an interface for connecting the channel adapter CA0 to the interconnection networks NW0 and NW1.
The network interface 23 is an interface for connecting the channel adapter CA0 to the maintenance terminal SVP.
The host channel interface 21 and the cache memory interface 22 are connected by a signal line 27.
The processor 24 performs various processes by executing programs stored in the local memory 25. More specifically, the processor 24 controls data transfer between the host computer 100 and the interconnection networks NW0 and NW1.
The local memory 25 stores a program executed by the processor 24. The local memory 25 stores a table referred to by the processor 24. The table referred to by the processor 24 is set or changed by the administrator. In this case, the administrator inputs information regarding table settings or table changes to the maintenance terminal SVP. The maintenance terminal SVP transmits the input information to the processor 24 via the network interface 23. The processor 24 creates or changes a table based on the received information. Then, the processor 24 stores the table in the local memory 25.
The processor peripheral control unit 26 controls data transfer among the host channel interface 21, cache memory interface 22, network interface 23, processor 24, and local memory 25. The processor peripheral control unit 26 is, for example, a chip set.
Since the hardware configuration of the channel adapter CA1 is the same as the hardware configuration of the channel adapter CA0, the description of the hardware configuration of the channel adapter CA1 is omitted.
FIG. 3 shows the hardware configuration of the storage adapter SA0. The storage adapter SA0 includes a cache memory interface 31, a storage channel interface 32, a network interface 33, a processor 34, a local memory 35, and a processor peripheral control unit 36.
The cache memory interface 31 is an interface for connecting the storage adapter SA0 to the interconnection networks NW0 and NW1.
The storage channel interface 32 is an interface for connecting the storage adapter SA0 to the channels D00, D01, D02, D03. The storage channel interface 32 mutually converts the data transfer protocol on the channels D00, D01, D02, and D03 and the data transfer protocol inside the storage controller SC.
The cache memory interface 31 and the storage channel interface 32 are connected by a signal line 37.
The network interface 33 is an interface for connecting the storage adapter SA0 to the maintenance terminal SVP.
The processor 34 performs various processes by executing a program stored in the local memory 35.
The local memory 35 stores a program executed by the processor 34. The local memory 35 stores a table referred to by the processor 34. The table referenced by the processor 34 is set or changed by the administrator. In this case, the administrator inputs information regarding table settings or table changes to the maintenance terminal SVP. The maintenance terminal SVP transmits the input information to the processor 34 via the network interface 33. The processor 34 creates or changes a table based on the received information. Then, the processor 34 stores the table in the local memory 35.
The processor peripheral control unit 36 controls data transfer among the cache memory interface 31, the storage channel interface 32, the network interface 33, the processor 34 and the local memory 35. The processor peripheral control unit 36 is, for example, a chip set.
Since the hardware configuration of the storage adapter SA1 is the same as the hardware configuration of the storage adapter SA0, the description of the hardware configuration of the storage adapter SA1 is omitted.
FIG. 4 shows a hardware configuration of the flash memory module P00. The flash memory module P00 includes a memory controller MC and a flash memory MEM. The flash memory MEM stores data. The memory controller MC controls “reading”, “writing”, and “erasing” of data to the flash memory MEM. The memory controller MC includes a processor (μP) 401, an interface unit (I / F) 402, a data transfer unit (HUB) 403, a memory (RAM) 404, and a memory (ROM) 407. The flash memory MEM includes a plurality of flash memory chips 405. The flash memory chip 405 includes a plurality of blocks 406 and stores data in each block 406. A block 406 is a unit in which the memory controller MC erases data. Block 406 includes a plurality of pages. A page is a unit by which the memory controller MC reads and writes data.
The pages are classified into valid pages, invalid pages, unused pages, and defective pages. A valid page is a page that stores valid data. An invalid page is a page that stores invalid data. Unused pages are pages that do not store data. A defective page is a page that cannot be physically used due to reasons such as a broken storage element in the page.
The interface unit 402 is connected to the storage adapter SA0 in the storage controller SC via the channel D00. The interface unit 402 is connected to the storage adapter SA1 in the storage controller SC via the channel D10. The interface unit 402 receives commands from the storage adapter SA0 and the storage adapter SA1. The command from the storage adapter SA0 and the storage adapter SA1 is, for example, a SCSI command.
Specifically, the interface unit 402 receives data from the storage adapter SA0 and the storage adapter SA1. The interface unit 402 stores the received data in the memory 404. Further, the interface unit 402 transmits the data stored in the memory 404 to the storage adapter SA0 and the storage adapter SA1. The interface unit 402 has an interface function having compatibility with a hard disk drive. Therefore, the storage adapters SA0 and SA1 recognize the flash memory modules P00 to P33 as, for example, hard disk drives with a capacity of 512 bytes per sector. The storage system 10 can incorporate a flash memory module and a hard disk drive as a recording medium for storing data.
The memory 404 is, for example, a dynamic random access memory and can read and write at high speed. The memory 404 temporarily stores data transmitted and received by the interface unit 402. On the other hand, the memory 407 is a nonvolatile memory and stores a program executed by the processor 401. A program executed by the processor 401 is loaded from the memory 407 to the memory 404 when the storage system 10 is activated so that the processor 401 can execute the program. In addition, the memory 404 stores a table referred to by the processor 401.
The table referred to by the processor 401 is an address conversion table for converting a logical address and a physical address of the flash memory MEM, for example. The logical address is an address for accessing a page which is a unit for reading and writing to the flash memory MEM from outside the flash memory module P00 (for example, from the storage adapter SA0). The physical address is an address for the memory controller MC to access a page which is a unit for reading and writing the flash memory MEM.
The data transfer unit 403 is, for example, a switch, and connects the processor 401, the interface unit 402, the memory 404, the memory 407, and the flash memory MEM to each other and controls data transfer therebetween.
The processor 401 performs various processes by executing programs stored in the memory 404. For example, the processor 401 refers to an address conversion table stored in the memory 404, converts the logical address of the flash memory MEM and the physical address of the flash memory MEM, and reads / writes data from / to the flash memory MEM. Further, the processor 401 performs a reclamation process (block reproduction process) and a wear leveling process (erasing number leveling process) on the block 406 in the flash memory module P00.
The reclamation process (block reproduction process) is a process of reproducing the invalid page in the block 406 to an unused page so that a block with fewer unused pages can be used. That is, it is assumed that the block (target block) 406 that is the target of the reclamation process includes valid pages, invalid pages, and unused pages, and there are many invalid pages. In this case, in order to increase unused pages, it is necessary to erase invalid pages. However, erasing can be performed only in units of blocks, not in units of pages. For this reason, it is necessary to copy the valid page to an empty block, then erase the target block, and reproduce the block.
More specifically, the processor 401 copies the data stored in the valid page in the block (target block) 406 that is the target of the reclamation process to an unused block. Then, the processor 401 changes the logical block number of the unused block whose data has been copied to the logical block number of the target block. Then, all the data in the target block is erased, and the reclamation process is completed.
For example, when the processor 401 writes data to the block 406, the number of unused pages in the block 406 decreases. When there are not enough unused pages in the block 406, the processor 401 cannot write data to the block 406. Therefore, the processor 401 reproduces the invalid page as an unused page by reclaiming the block 406.
On the other hand, the wear leveling process (erase count leveling process) is a process for leveling the data erase count of each block 406. Thereby, the lifetime of the flash memory MEM can be extended. This is because the flash memory MEM has a lifetime when the number of data erasures increases. In general, the flash memory MEM is guaranteed to erase data about 10,000 to 100,000 times.
Although the hardware configuration of the flash memory module P00 has been described in detail, the other flash memory modules P01 to P33 have the same hardware configuration.
FIG. 5 is an explanatory diagram of the block 406 of the flash memory module P00. Block 406 includes a plurality of pages 501. The block 406 generally includes several tens of pages 501 (for example, 64 pages). A page 501 is a unit in which the memory controller MC or the like reads / writes data. For example, in a NAND flash memory, the memory controller MC or the like reads data in a time of 20 μs to 30 μs per page and writes data in a time of about 0.2 ms to 0.3 ms per page. The memory controller MC or the like erases data in a time of about 2 ms to 4 ms per block.
The page 501 includes a data part 502 and a redundant part 503. For example, for each page, the page 501 has 2112 bytes, the data portion 502 has 2048 bytes, and the redundant portion 503 has 64 bytes. In the present embodiment, a flash memory in which the page 501 is 2112 bytes and the data portion 502 is 2048 bytes per page is exemplified, but the page size is not particularly limited.
The data unit 502 stores user data. The redundancy unit 503 stores management information and error correction information of the page 501. The management information includes an offset address and a page status. The offset address is a relative address in the block 406 to which the page 501 belongs. The page status indicates whether the page 501 is a valid page, an invalid page, an unused page, or a page being processed. The error correction information is information for detecting and correcting an error of the page 501 and is, for example, a Hamming code. The in-page redundant part 503 is normally accessible only by the memory controller MC, and only the page / data part 502 is accessible from the storage adapters SA0 and SA1. In other words, the logical address is for mapping the memory space of the data part 502.
Due to the above-mentioned reclamation processing and wear leveling processing, data written to the flash memory module may move within the flash memory module independently of an instruction from the storage controller SC. The memory controller MC correctly reflects the result of this data movement in the address conversion table, so that the storage controller SC can access the correct data.
However, if there is an error in the correspondence between the logical address and the physical address due to a problem (bug, etc.) in the program for executing reclamation processing or wear leveling processing, or garbled data in the address conversion table due to radiation, etc. In the flash memory module, an error occurs in the data write destination address or the data read destination address, and the storage controller SC cannot read or write correct data. In the present embodiment, data is appropriately protected from address errors occurring in the flash memory module.
Next, an address error detection method will be described with reference to FIGS.
FIG. 6 shows an outline of a process in which the storage controller SC writes data to the flash memory module P00. On the cache memory CM in the storage controller SC, the data 601 is managed in units of sector capacity (for example, 520 bytes) of the hard disk drive. The 520-byte data 601 includes 512-byte user data and an 8-byte hard disk drive protection code. The protection code for the hard disk drive includes information that can specify address information (write address) of the hard disk drive to which data is written.
For the purpose of maintaining compatibility with the conventional architecture, the storage system 10 includes a flash memory module and a hard disk drive as a recording medium for storing data. Manage data in units of hard disk drive sector capacity. Here, an address for accessing the data 601 on the cache memory CM is referred to as a cache address.
When the storage controller SC writes data to the flash memory module P00, it transfers the data 601 on the cache memory CM to the storage adapter SA (step 602). The storage adapter SA checks the size of the page data portion in the write destination flash memory module P00 and calculates the start logical address of the write destination in the flash memory module P00 (details will be described later). . Here, the logical address of the write destination is “A0”. The storage adapter SA generates a protection code 604 that can specify the logical address information of the write destination. The protection code 604 does not necessarily need to be a logical address itself, and may be any information that can specify a write destination logical address. The protection code 604 includes, for example, a part or all of the logical address or information obtained by encoding the logical address.
Then, when writing data to the flash memory module P00, the storage adapter SA adds a protection code 604 for protecting the write data from an address error to the write data 603. At this time, the storage adapter SA sets the data 601 so that the size of the size of the write data 603 and the size of the protection code 604 matches the size of the page data portion in the write destination flash memory module P00. To divide. Specifically, the storage adapter SA adjusts the boundary of the write data 603 so that the data 601 managed in units of 520 bytes on the cache memory CM is combined with the protection code 604 to be 2048 bytes. The storage adapter SA transfers the write data 603 and the protection code 604 adjusted to the size of the page data portion of the flash memory module P00 to the flash memory module P00 (step 605).
The memory controller MC that has received the write data 603 refers to the address conversion table 606 to obtain the physical address of the write destination. According to the address conversion table 606, the physical address corresponding to the logical address “A0” is “b0”, and the physical address corresponding to the logical address “A1” is “b1”. The memory controller MC writes the write data 603 received from the storage adapter SA together with the protection code 604 to the page data portion of the physical address “b0” (step 607).
The memory controller MC treats the protection code 604 as data and writes it to the flash memory MEM. For example, in the case of the SCSI protocol, the memory controller MC executes a write process based on the write destination logical address information received together with the Write command. Similarly, the memory controller MC executes a read process based on the read destination logical address information received together with the Read command.
Specifically, the logical address information received together with the command by the memory controller MC is a sector address when, for example, one sector is 512 bytes because the flash memory module of this embodiment functions as a hard disk drive compatible device. When accessing the flash memory, the memory controller MC converts the received sector address into a logical address and further converts into a physical address. In the present embodiment, the conversion from the sector address to the logical address is performed because the page data portion size (2048 bytes) is an integral multiple (4 times) of the sector size (512 bytes). Corresponding sector address = logical address × 4. Since this sector address is an address used only for data transfer between the storage channel interface and the flash memory module, a description of the sector address is omitted for the sake of simplicity.
Reference numeral 608 denotes a page having the physical address “b0”, and reference numeral 609 denotes a page having the physical address “b1”. Reference numeral 610 denotes a redundant portion used by the memory controller MC.
FIG. 7 shows an outline of processing in which the storage controller SC detects an address error when an address error occurs in the flash memory module P00. In the address conversion table 606, the physical address corresponding to the logical address “A0” should be “b0”, but the physical address corresponding to the logical address “A0” is mistakenly replaced with “b1” (step 1). 710).
Even if the storage controller SC tries to read the data of the page data portion stored in the logical address “A0”, the address error is generated in the address conversion table 606. The page data portion of “b1” is read (step 707) and transferred to the storage adapter SA (step 705).
The storage adapter SA checks the protection code 704 added to the data 703 read from the flash memory module P00. Specifically, the storage adapter SA compares the logical address information “A1” specified from the protection code 704 added to the read data 703 with the logical address “A0” instructed to read to the memory controller MC, It is checked whether or not the data 703 has been read normally. Since an address error has occurred in the address conversion table 606, the logical address information “A1” specified from the protection code 704 does not match the logical address “A0” instructed to read to the memory controller MC. Thereby, the storage adapter SA can detect an address error. When the storage adapter SA detects an address error, the storage adapter SA does not store the read data 703 in the cache memory CM (step 702). This is because the read data 703 is not data to be originally read.
FIG. 8 shows the hardware configuration of the storage channel interface 32. The storage channel interface 32 has a function of adding a protection code to write data and detecting an address error of the read data. The storage channel interface 32 includes a media determination unit 801, an XOR engine 804, a switch (SW1) 805, a switch (SW2) 806, a protection code inspection unit (LA inspection unit) 808, and a protection code addition unit (LA addition unit) 809, And a data aligner 810.
The storage channel interface 32 is connected to the processor peripheral control unit 36 (see FIG. 3) via the channel 812. The media determination unit 801 has information for determining the type of the recording medium connected to the storage system 10 and information for calculating the logical address of the write destination. Specifically, the media determination unit 801 has a media database 803 and a PDEV management table 802. Details of the media database 803 and the PDEV management table 802 will be described later. The XOR engine 804 generates parity data to be stored in the RAID group. The XOR engine 804 reproduces data lost when an error occurs. The XOR engine 804 is connected to each of the switch 805 and the signal line 37.
The switches 805 and 806 switch the data input / output path based on the determination result of the media determination unit 801. For example, when the data write destination or read destination is a hard disk drive, the switches 805 and 806 are switched so that the channel 811 becomes the data input / output path. On the other hand, when the data write destination or read destination is a flash memory module, the switches 805 and 806 are switched so that the channel 807 becomes the data input / output path.
When the data read destination is a flash memory module, the read data passes through the protection code inspection unit 808 and the data aligner 810, respectively. On the other hand, when the data write destination is a flash memory module, the write data passes through the data aligner 810 and the protection code adding unit 809, respectively.
The switch 806 is connected to the channels D00 to D03. When the data aligner 810 writes data to the flash memory module, the page data portion is defined with the data boundary managed in units of 520 bytes on the cache memory CM, with the protection code added to the data boundary. Adjust to match the size of. Further, when reading data from the flash memory module, the data aligner 810 removes the protection code from the read data, and the data boundary of the read data from which the protection code is removed is a management unit on the cache memory CM. Adjust to match (520 bytes).
The protection code adding unit 809 generates a protection code that can specify the logical page address information of the write destination page in the flash memory module based on the information (such as the size of the page data unit) obtained from the media determination unit 801. Then, the protection code is added to the write data.
The protection code checking unit 808 checks whether the logical address specified from the protection code added to the read data matches the logical address of the data that should be read out.
FIG. 9 shows information stored in the PDEV management table 802. The PDEV management table 802 manages information regarding each recording medium (PDEV) connected to the storage system 10. The storage channel interface 32 transmits an inquiry command to each recording medium connected to the storage system 10, and based on the response to the inquiry command, the module name 901, vendor name 902, and model 903 of the recording medium are stored in the PDEV management table. Stored in 802. Further, the storage channel interface 32 searches the media database 803, and stores the media type 904 and the page data portion size 905 having specifications matching the vendor name and model included in the response to the inquiry command. Stored in 802. The storage channel interface 32 holds the PDEV management table 802 so as to grasp the medium type and page data portion size (or sector capacity) of each recording medium connected to the storage system 10.
FIG. 10 shows information stored in the media database 803. The media database 803 stores a vendor name 902, a model 903, a medium type 904, and a page data part size 905 of a recording medium (for example, a flash memory module, a hard disk drive, etc.) that may be connected to the storage system 10. Has been. The medium type 904 is information for identifying whether the recording medium is a flash memory module or a hard disk drive. When the recording medium is a flash memory module, “1” is stored in the medium type 904. When the recording medium is a hard disk drive, “0” is stored in the medium type 904. The page data portion size 905 in the case where the recording medium is a hard disk drive indicates the capacity per sector.
The administrator can correct or add data in the media database 803 by operating the maintenance terminal SVP (see FIG. 1). By adding information about a new specification flash memory module not registered in the media database 803 to the media database 803, when writing data to the new specification flash memory module, the logical address of the write destination is set. An identifiable protection code can be added to the write data.
FIG. 11 is a flowchart showing a data read processing procedure by the storage controller SC. The storage controller SC inputs the read destination cache address LA and the read data length DL to the storage channel interface 32 (step 1101).
Next, the storage channel interface 32 resets the retry counter (step 1102).
Next, the storage channel interface 32 calculates the logical address range (the start logical address PA1, the offset value OS1, the end logical address PA2, and the offset value OS2) of the flash memory module to be read (step 1103). A method of calculating the head logical address PA1, the offset value OS1, the tail logical address PA2, and the offset value OS2 will be described later.
Next, the storage channel interface 32 reads data (data in the range from the head logical address PA1 to the tail logical address PA2) from the flash memory module (step 1104).
Next, the storage channel interface 32 compares the logical address specified from the protection code added to the read data with the logical address of the data to be originally read, and checks whether an address error has occurred. (Step 1105). If an address error is not found (step 1105; YES), the process proceeds to step 1106. If an address error is found (step 1105; NO), the process proceeds to step 1107.
If no address error has occurred, the storage channel interface 32 removes the protection code added to the read data and adjusts so that the data boundary matches the management unit on the cache memory CM (step 1106). Thereafter, the storage channel interface 32 stores the data in the cache memory CM and completes the read operation.
If an address error has occurred, the storage channel interface 32 increments the retry counter by 1 (step 1107), and if the retry counter value has not reached the specified number of times (step 1108; NO), The read operation is repeatedly executed (step 1104). When the value of the retry counter exceeds the specified number of times (step 1108; YES), the storage channel interface 32 executes error correction processing (step 1109).
FIG. 12 illustrates a method for converting a cache address to a logical address. The start logical address PA1, the offset value OS1, the end logical address PA2, and the offset value OS2 can be calculated using Expressions (1) to (4), respectively.
PA1 = int {(LA1 * X) / (PS-Y)} (1)
PA2 = int [{(LA1 + DL) * X-1} / (PS-Y)] (2)
OS1 = LA1 * X-PA1 * (PS-Y) (3)
OS2 = (LA1 + DL) * X-1-PA2 * (PS-Y) (4)
Here, X is a management unit on the cache memory, LA1 is the top cache address of the read or write range, LA2 is the end cache address of the read or write range, DL is the size of the read or write data, PS is the flash memory The page data portion size of the module, Y indicates the size of the protection code. Although the case where data is arranged at the top address side in the page data portion and the protection code is arranged at the end address side is illustrated, the data arrangement and the protection code arrangement are not limited.
For convenience of explanation, FIG. 12 shows the memory space with the cache address LA = 0 in the cache memory and the logical address PA = 0 in the flash memory module aligned. PA1 indicates a logical address of the first page data portion 1101 of data to be read or written in the flash memory module. PA2 indicates the logical address of the last page data portion 1102 of data to be read or written to the flash memory module.
Since the cache memory module and the flash memory module have different data management units, when data from PA1 to PA2 is accessed, the data is accessed in excess of the data size DL to be read / written. In the present specification, this extra portion is referred to as an offset. The first page data portion 1101 has an offset 1103. An offset 1104 exists in the last page data portion 1102. OS1 and OS2 indicate addresses in the page data section. The address space from the address LA1 to the address LA2 on the cache memory is the address page OS1 to the end page data portion in the first page data portion 1101 (page data portion specified by the logical address PA1) in the flash memory module. This corresponds to the address space up to the address OS2 in 1102 (the page data portion specified by the logical address PA2).
The storage controller SC reads the entire page data portion including the offsets 1103 and 1104 from the flash memory module, removes the offsets 1103 and 1104 from the read data, and stores the read data in the cache memory.
It is to be noted that, for each recording medium having different specifications, various expressions can be obtained by storing in the media database 803 an address conversion expression between a logical address and a physical address as shown in the expressions (1) to (4). It is possible to flexibly cope with a recording medium having an address conversion specification.
FIG. 13 is a flowchart showing a data write processing procedure by the storage controller SC. The storage controller SC inputs the write destination head cache address LA and the write data size DL to the storage channel interface 32 (step 1301).
The storage controller SC determines the logical address range (the start logical address PA1, the offset value OS1, the end logical address PA2, and the offset value OS2) of the flash memory module as the write destination based on the equations (1) to (4). Calculate (step 1302).
Next, the storage controller SC checks whether or not the offset 1103 exists in the first page data portion 1101 (that is, whether or not OS1 = 0) (step 1303).
When the offset 1103 exists in the first page data portion 1101 (step 1303; NO), the storage controller SC reads the first page data portion 1101 (step 1304). On the other hand, if the offset 1103 does not exist in the first page data portion 1101 (step 1303; YES), the storage controller SC proceeds to step 1305.
Next, the storage controller SC has an offset 1104 in the end page data portion 1102 (that is, OS2 ≠ PS-Y-1), and the end page data portion is not yet read (that is, OS1 == 0 || It is checked whether (OS1 ≠ 0 && PA1 ≠ PA2)) (step 1305).
When the offset 1104 exists in the last page data portion 1102 and the last page data portion has not been read (step 1305; YES), the storage controller SC reads the last page data portion 1102 (step 1306). On the other hand, if the offset 1104 does not exist in the last page data portion 1102 or the last page data portion has been read (step 1305; NO), the storage controller SC proceeds to step 1307.
When the storage controller SC reads the first page data part 1101 or the last page data part 1102, the data of the offset 1103 and 1104 parts are not updated, and the parts other than the offsets 1103 and 1104 are updated in the cache memory CM. Update to the above write data. Further, the storage controller SC adds a protection code that can specify the write destination logical address to the data on the cache memory CM, and the size of the write data matches the page data portion size with the protection code added. The data boundary is adjusted to (Step 1307).
Next, the storage controller SC transfers the write data from the start logical address PA1 to the end logical address PA2 to the flash memory module (step 1308), and completes the write process.
FIG. 14 is a flowchart showing error correction processing by the storage channel interface 32. As an example, consider a case where an address error occurs in the logical address PA1 of the module P00 in the RAID group VDEV0 composed of the flash memory modules P00, P10, P20, and P30.
The storage channel interface 32 reads data from the logical addresses PA1 of the other flash memory modules P10, P20, and P30 belonging to the same RAID group VDEV00 as the flash memory module P00 (steps 1401a, 1401b, and 1401c).
Next, the storage channel interface 32 removes the protection code for the flash memory that can specify the logical address from the read data (step 1402a, step 1402b, step 1402c).
Next, the storage channel interface 32 divides the read data into management units on the cache memory (steps 1403a, 1403b, and 1403c).
Next, the storage channel interface 32 removes the hard disk drive protection code from the data divided into management units on the cache memory (steps 1404a, 1404b, 1404c).
Next, the XOR engine 804 calculates an exclusive OR for the data from which the protection code for the flash memory and the protection code for the hard disk drive are removed, and reproduces the data that should have been stored in the flash memory module P00. (Step 1405).
Next, the storage channel interface 32 adds a hard disk drive protection code to the reproduction data (step 1406).
Next, the storage channel interface 32 further adds a protection code for the flash memory module (information that can specify the write destination logical address PA1) to the reproduction data, and adjusts so that the data boundary matches the page data portion size. (Step 1407).
Next, the storage channel interface 32 overwrites the reproduction data on the logical address PA1 of the flash memory module P00 (step 1408). Through the above processing, the error correction processing is completed.
When an address error occurs in the hard disk drive, the storage controller SC overwrites and corrects the data in which the address error has occurred in the first data length unit.
FIG. 15 is a diagram for explaining an operation in which the storage controller SC adds another protection code for protecting data from an address error when writing data. For example, when writing the sequential access data to the flash memory module P00, the storage controller SC adds a protection code including write time information to the sequential access data.
On the cache memory CM in the storage controller SC, the data 1401 is managed in units of sector capacity (for example, 520 bytes) of the hard disk drive. When the storage controller SC writes data to the flash memory module P00, it transfers the data 1401 on the cache memory CM to the storage adapter SA (step 1402).
Consider a case where the storage adapter SA writes sequential data 1403 from logical addresses A0 to A2 in the flash memory module P00 to which data is written. The storage adapter SA generates a protection code 1404 that can specify the write destination logical addresses “A0” to “A2” and the write time information “t1”. The storage adapter SA transfers the data 1403 and the protection code 1404 matched to the page data portion size to the flash memory module P00 (step 1405).
The memory controller MC that has received the write data refers to the address conversion table 1406 and obtains the physical address of the write destination. According to the address conversion table 1406, the physical addresses corresponding to the respective logical addresses “A0” to “A2” are “b0” to “b2”. The memory controller MC specifies the protection code that can specify the logical addresses “A0” to “A2” and the write time information “t1” in the page data portion 1408 of the physical addresses “b0” to “b2”. Store possible protection codes together.
Reference numeral 1410 denotes a redundant portion used by the memory controller MC.
FIG. 16 is a diagram for explaining an operation in which the storage controller SC detects an address error based on a protection code including write time information when an address error occurs in the flash memory module. Here, in the address conversion table 1406, the physical address corresponding to the logical address “A1” should be “b1”, but the physical address corresponding to the logical address “A1” is mistakenly replaced with “b4” (step 1510). Further, consider the case where the old data (write time information “t0”) of the logical address A1 remains unerased at the physical address “b4”.
Reference numeral 1508 denotes a page having the physical address “b1”, and reference numeral 1509 denotes a page having the physical address “b4”. Reference numeral 1410 indicates a redundant portion used by the memory controller MC.
The storage controller SC tries to read the sequential data of the logical addresses “A0” to “A2”. Even if the storage controller SC tries to read the data of the page data portion stored at the logical address “A1”, the memory controller MC may detect an incorrect physical address “due to an address error that has occurred in the address conversion table 1406. The page data portion of b4 ″ is read (step 1507), and the read data is transferred to the storage adapter SA (step 1505).
The storage adapter SA checks the protection code 1504 added to the received data 1503. However, since the logical address specified from the protection code included in the data read from the physical address “b4” is “A1”, it is not possible to detect an address error only by checking the logical address.
However, since the read sequential data of the logical addresses “A0” to “A2” are written at the same time, all the time information “t1” specified from the protection code 1504 should be the same. Therefore, the storage adapter SA can detect an address error by finding the protection code “t0” whose time information does not match.
Data whose address error is found is not stored in the cache memory CM (step 1502).
As described above, in the case of sequential data, the reliability of data is further improved by adding information that can specify the write time in addition to information that can specify the logical address to the protection code. Can do.
Instead of the write time information, an identifier of an exchange or sequence to which the write data belongs, or information obtained by encoding the write time information may be included in the protection code. In addition, a table that records the correspondence between the logical address information and write time information for each write data is held in the storage adapter, and the write time information specified from the protection code at the time of data reading is compared with the records in the table. May be.
FIG. 17 is a diagram for explaining another example of the protection code added to the page data portion at the time of data writing. The page includes a page data part 1606 and a redundant part 1605. Since the redundant part 1605 is an area that cannot be written from the storage controller SC, the protection code is written together with the data 1601 in a predetermined area in the page data part 1606. In the page data portion 1606, data 1601 and protection codes 1602, 1603 and 1604 are written.
Here, the protection code 1602 includes information capable of specifying a logical address. The protection code 1603 includes information that can specify the writing time. The protection code 1604 is for detecting or correcting an error in the data 1601 and the protection codes 1602 and 1603 written in the page data portion. The protection code 1604 is, for example, a CRC (Cyclic Redundancy Check) code, an LRC (Longitudinal Redundancy Check) code, or a Hamming code.
In the flash memory module, the memory controller MC stores the protection code for the data written in the page data portion in the redundant portion 1605 to guarantee the data. However, since the protection code in the redundant unit 1605 is removed by data transfer between the memory controller MC and the storage adapter SA, consistent data guarantee cannot be performed between the storage controller SA and the flash memory module. Therefore, the reliability of the storage system is improved by writing error correction information together with data and other protection codes in the page data portion.
According to this embodiment, in the storage system 10 in which there is a capacity difference between the memory management unit in the storage controller SC and the management unit in the recording medium, an address error in the recording medium is detected, and the data is appropriately set. Can be protected.
It is a hardware block diagram of the storage system which concerns on this embodiment. It is a hardware block diagram of a channel adapter. It is a hardware block diagram of a storage adapter. It is a hardware block diagram of a flash memory module. It is explanatory drawing of the block of a flash memory module. It is explanatory drawing which shows the outline | summary of the process in which a storage controller writes data to a flash memory module. FIG. 3 is an explanatory diagram showing an outline of processing in which a storage controller detects an address error when an address error occurs in a flash memory module. It is a hardware block diagram of a storage channel interface. It is explanatory drawing of the information stored in the PDEV management table. It is explanatory drawing of the information stored in the media database. It is a flowchart which shows the process sequence of the data reading by a storage controller. It is explanatory drawing of the method of converting a cache address into a logical address. It is a flowchart which shows the processing procedure of the data writing by a storage controller. It is a flowchart which shows the error correction process by a storage channel interface. It is a figure explaining the operation | movement which adds another protection code for a storage controller to protect data from an address error at the time of data writing. It is a figure explaining the operation | movement in which a storage controller detects an address error based on the protection code containing write time information when an address error arises in a flash memory module. It is a figure explaining the example of the other protection code added to a page data part at the time of data writing.
DESCRIPTION OF SYMBOLS 10 ... Storage system SC ... Storage controller CA ... Channel adapter SA ... Storage adapter NW ... Mutual coupling network P00-P33 ... Flash memory module
And flash memory modules having a memory controller that manages data to be read and written to the flash memory chip and the flash memory chip in units of pages,
Storage for managing data reading from or writing to the cache memory and the flash memory chips for temporarily storing the data you write to the flash memory chip in said sector capacity unit of the hard disk drive is in the cache memory A controller,
The flash memory module is
Configured and managed by the redundant portion for a storage area of one page for storing management information of the page data section and the corresponding page of read-write data length from said storage controller,
A media determination unit for determining a type and specification of a recording medium connected to the storage controller and a data length of the page data portion corresponding to the type and specification, and the media determination unit When the recording medium connected to the storage controller is a flash memory module,
Oite at the time of writing data to the flash memory chips,
Data of the page data portion corresponding to the type and specification of the recording medium generated by generating a protection code that can specify address information of the write destination page and further combining the write data and the protection code determined by the media determination portion The data on the cache memory managed in units of sector capacity of the hard disk drive is divided so as to be long, and the write data and the protection code are combined and the flash data in units of data length of the page data portion. Write to the memory chip,
When reading data from the flash memory chip,
A storage system that checks whether there is a read error by comparing address information specified from the protection code added to data read from the flash memory chip and address information of data to be read.
The storage area provided by the flash memory module is configured in RAID.
When an address error occurs in the data in any of the flash memory modules, the storage controller stores another flash memory belonging to the same RAID group as the flash memory module that stores the data in which the address error has occurred. A storage system that uses data in a module to restore data in which an address error has occurred in units of data length of the page data portion , and overwrites the data in which the address error has occurred with the restored data.
When the address error occurs in the hard disk drive, the storage controller overwrites and corrects the data in which the address error has occurred in the sector capacity unit of the hard disk drive .
The storage system, wherein the protection code includes write time information.
The storage system, wherein the protection code includes an error detection code for protecting data having a data length of the page data portion .
The storage system according to claim 1 ,
The data having the data length of the sector capacity of the hard disk drive includes data and a protection code capable of specifying address information of the hard disk drive to which the data is written.
A flash memory module having a flash memory chip and a memory controller that manages data to be read from and written to the flash memory chip in units of pages, and temporarily stores data to be read from and written to the flash memory chip And a storage controller that manages data to be read from and written to the flash memory chip in units of sector capacity of a hard disk drive on the cache memory, and a data protection method for a storage system comprising:
A first step of configuring and managing a storage area per page by a page data part having a data length that is readable and writable from the storage controller and a redundant part for storing management information of the page;
When writing data to the flash memory chip,
Data of the page data portion corresponding to the type and specification of the recording medium generated by generating a protection code that can specify address information of the write destination page and further combining the write data and the protection code determined by the media determination portion The data on the cache memory managed in units of sector capacity of the hard disk drive is divided so as to be long, and the write data and the protection code are combined and the flash data in units of data length of the page data portion. A second step of writing to the memory chip;
A third step of checking for the presence of a read error by comparing the address information specified from the protection code added to the data read from the flash memory chip and the address information of the data to be read;
JP2006178487A 2006-06-28 2006-06-28 Storage system and data protection method thereof Active JP4842719B2 (en)
JP2006178487A JP4842719B2 (en) 2006-06-28 2006-06-28 Storage system and data protection method thereof
US11/503,050 US7574554B2 (en) 2006-06-28 2006-08-11 Storage system and data protection method therefor
EP06255630A EP1873649A1 (en) 2006-06-28 2006-11-01 Storage system and data protection method therefor
JP2008009635A JP2008009635A (en) 2008-01-17
JP4842719B2 true JP4842719B2 (en) 2011-12-21
JP2006178487A Active JP4842719B2 (en) 2006-06-28 2006-06-28 Storage system and data protection method thereof
KR20090095641A (en) * 2006-12-06 2009-09-09 퓨전 멀티시스템즈, 인크.(디비에이 퓨전-아이오) Apparatus, system and method for managing data using a data pipeline
WO2011024239A1 (en) * 2009-08-31 2011-03-03 Hitachi, Ltd. Storage system having plurality of flash packages
US9141537B2 (en) * 2012-10-30 2015-09-22 Mangstor, Inc. Magnetic random access memory journal
FR3038752B1 (en) * 2015-07-10 2018-07-27 St Microelectronics Rousset Method and circuit for protecting and verifying address data
US20190108122A1 (en) * 2016-04-05 2019-04-11 Hewlett Packard Enterprise Development Lp Unmap to initialize sectors
EP0935255A2 (en) 1989-04-13 1999-08-11 SanDisk Corporation Flash EEPROM system
JP5087347B2 (en) 2012-12-05 Semiconductor memory device and method for controlling semiconductor memory device
US20070233931A1 (en) 2007-10-04 Storage system using flash memories, wear-leveling method for the same system and wear-leveling program for the same system
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