Source: http://www.google.com/patents/US7003680?ie=ISO-8859-1&dq=ELIST
Timestamp: 2015-02-28 23:11:21
Document Index: 534399784

Matched Legal Cases: ['art 2', 'art 25', 'art 26', 'art 28', 'art 25', 'art 26', 'art 28', 'art 28', 'art 28', 'art 28', 'art 28', 'art 28', 'art 28', 'art 28', 'art 28', 'art 28', 'art 28', 'art 68', 'art 68', 'art 68']

Patent US7003680 - Contactless apparatus and card-type device having clock rectifier that is ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn information processing apparatus receives a carrier wave modulated in accordance with information and extracts the information and power therefrom to execute a given process. A receiving circuit receives the carrier wave. A dc power generating circuit rectifies the carrier wave received by the receiving...http://www.google.com/patents/US7003680?utm_source=gb-gplus-sharePatent US7003680 - Contactless apparatus and card-type device having clock rectifier that is independent of power rectifier and demodulator with RC time constant based on selectable resistorAdvanced Patent SearchPublication numberUS7003680 B2Publication typeGrantApplication numberUS 10/060,370Publication dateFeb 21, 2006Filing dateFeb 1, 2002Priority dateFeb 8, 2001Fee statusPaidAlso published asDE60207122D1, DE60207122T2, EP1231557A2, EP1231557A3, EP1231557B1, US20020108066Publication number060370, 10060370, US 7003680 B2, US 7003680B2, US-B2-7003680, US7003680 B2, US7003680B2InventorsShoichi Masui, Yoshiaki KanekoOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (7), Non-Patent Citations (2), Referenced by (4), Classifications (12), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetContactless apparatus and card-type device having clock rectifier that is independent of power rectifier and demodulator with RC time constant based on selectable resistor
US 7003680 B2Abstract
An information processing apparatus receives a carrier wave modulated in accordance with information and extracts the information and power therefrom to execute a given process. A receiving circuit receives the carrier wave. A dc power generating circuit rectifies the carrier wave received by the receiving circuit to thereby generate dc power. A demodulation circuit is structurally independent of the dc power generating circuit, and retrieves the information modulated onto the carrier wave. An information processing circuit is supplied with the dc power as a power source, and processes the information retrieved by the demodulation circuit in a given manner. Since the demodulation circuit and the dc power generating circuit are structurally independent of each other, interference between elements included in these circuits can be eliminated and simple designing is enabled. In addition, power consumed in the apparatus can be reduced because of optimal designing.
1. An information processing apparatus receiving a carrier wave modulated in accordance with information and extracting the information and power from the carrier wave to thereby execute a predetermined process, said information processing apparatus comprising:
a demodulation circuit, structurally independent of the dc power generating circuit, retrieving the information modulated onto the carrier wave, and wherein said demodulation circuit comprises a rectifying element, a plurality of resistors with different resistance valves and a capacitor for demodulation by envelope detection and the envelope detection is performed with a time constant determined by the capacitor and one of the resistors selected in accordance with the frequency of the carrier wave;
an information processing circuit, supplied with the dc power as a power source, processing the information retrieved by the demodulation circuit in a given manner; and
a clock signal generating circuit generating a clock from the carrier wave received by said receiving circuit, wherein said clock signal generating circuit is independent of said dc power generating circuit and said demodulation circuit, and wherein said clock signal generating circuit comprises:
said demodulation circuit comprises a full-wave rectifying circuit for demodulation by envelope detection.
3. A card-type information processing device receiving a carrier wave modulated in accordance with information and extracting the information and power from the carrier wave to thereby execute a predetermined process, said card-type information processing device comprising:
4. The card-type information processing device as claimed in claim 3, wherein:
The present invention relates to information processing apparatuses and card-type information processing devices, and more particularly, to an information processing apparatus and a card-type information processing device, each receiving a carrier wave that has been modulated in accordance with information and extracting information and power therefrom to execute a predetermined process.
Recently, a card-type information processing device with a contactless interface has been developed and expected to be placed for not only the personal use such as a credit card or commuter pass but also the industrial use such as a tag in factory automation and product management.
The physical interface prescribed in the ISO/IEC 14443 Part 2 is known as a radio wave interface of such a card-type information processing device. Particularly, a card equipped with a CPU as an LSI for smart cards needs constant supply of power and clock, and therefore employs the Type B specification of the above-mentioned standard.
FIG. 10 is a diagram of a conventional configuration of the card-type device with the contactless interface that matches the Type B specification.
The card-type information processing device 20 is made up of an antenna 21, a capacitor 22, a full-wave rectifier circuit 23, a capacitor 24, a voltage stabilizing part 25, an ASK demodulator part 26, a capacitor 27, an information processing part 28, a transmitting circuit 29, and a carrier clock extracting circuit 30. The card-type information processing device 20 is driven by power sent by the reader/writer in the form of radio wave. The card-type information processing device 20 retrieves information superimposed in the electric wave, and processes the information in various ways. Resultant information thus obtained is sent back to the reader/writer 10.
The antenna 21 captures the radio wave sent by the reader/writer 10, and radiates the signal from the transmitting circuit 29 toward the reader/writer 10 in the form of radio wave.
The capacitor 22 combines with the inductance component to form parallel resonant circuit, which acts to increase power that can be received by the card-type information processing device 20.
FIG. 11 is a diagram of a conventional configuration of the card-type information processing device 20. As shown in FIG. 11, the full-wave rectifier circuit 23 is composed of diodes 23 a through 23 d. The voltage stabilizing part 25 is composed of a resistor 25 a and a voltage stabilizing circuit 25 b. The ASK demodulation part 26 is composed of a resistor 26 a and an ASK demodulation circuit 26 b. The diodes 23 a through 23 d rectify the full wave of an RF signal from the antenna 21 and result in a dc signal.
The resistor 25 a makes isolation for eliminating interference between the capacitor 24 and the capacitor 27.
The voltage stabilizing circuit 25 b stabilizes the voltage to be supplied to the information processing part 28 at a constant level.
The resistor 26 a cooperates with the capacitor 24 and detects the signals from the diodes 23 a�23 d in envelope detection.
The ASK demodulation circuit 26 b ASK-demodulates the detected signal from the resistor 26 a and the capacitor 24 to thereby extract information therefrom.
FIG. 12 is a circuit diagram of a conventional configuration of the carrier clock extracting circuit 30. As shown in FIG. 12, the carrier clock extracting circuit 30 includes N-channel MOS-FETs (Metal-Oxide Semiconductor Field Effect Transistor) 30 a and 30 b, P-channel MOS FETs 30 c and 30 d, a constant-current source 30 e, and a level shift circuit 30 f. A differential amplifier is formed by the N-channel MOS-FETs 30 a and 30 b, P-channel MOS-FETs 30 c and 30 d, and the constant-current source 30 e. The differential amplifier amplifies the voltage difference between RF signals RF1 and RF2 from the antenna 21, the amplified difference being applied to the level shift circuit 30 f. The level shift circuit 30 f shifts the level of the signal from the differential amplifier to a level of a digital signal. The output signal of the level shift circuit 30 f is a carrier clock.
The conventional device described above operates as follows.
The antenna 21 of the card-type information processing device 20 captures the radio wave emitted by the reader/writer 10, and supplies it to the full-wave rectifier circuit 23. The inductance component of the antenna 21 cooperates with the capacitor 22 to form a parallel resonant circuit, which increase the power that can be received by the card-type information processing device 20.
The diodes 23 a�23 d rectify the RF signals RF1 and RF2 from the antenna 21.
The capacitor 24 and the resistor 26 a eliminate a ripple component overlaid onto the dc signal from the diodes 23 a�23 d, and detect the envelope of the dc signal by envelope detection.
The ASK demodulation circuit 26 b demodulates the envelope-detected signal in ASK to thereby retrieve original information (information item �0� or �1�), which is then supplied to the information processing part 28.
The resistor 25 a prevents interference between the capacitor 24 and the capacitor 27. That is, the resistor 25 a prevents the ASK signal across the capacitor 24 from being supplied to the information processing part 28.
The voltage stabilizing circuit 25 b acts to supply a constant dc voltage to the information processing part 28.
The capacitor 27 eliminates a ripple component contained in the power supply voltage from the voltage stabilizing circuit 25 b. The differential amplifier, which is made up of the N-channel MOS-FETs 30 a and 30 b and the P-channel MOS-FETs 30 c and 30 d amplifies the difference signal between the RF signals RF1 and RF2 with a predetermined gain. This results in a signal of 13.56 MHz. The level shift circuit 30 f converts the signal of 13.56 MHz into the level of the digital signal, which is supplied to the information processing part 28 as a clock.
In the above-mentioned manner, the information processing part 28 is supplied with the power from the voltage stabilizing circuit 25 b, the received information from the ASK demodulation circuit 26 b, and the clock from the carrier clock extracting circuit 30. Then, the information processing part 28 processes the information from the ASK demodulation circuit 26 b in a given manner in synchronism with the clock from the carrier clock extracting circuit 30.
Recently, there has been an increasing demand for improvement in the capability of processing of the card-type information processing device 20, and an increased clock frequency has been needed accordingly. However, this increases current consumed in the information processing part 28.
As the power consumption in the information processing part 28 increases, the capacitor 27 is needed to have an increased capacity as large as 1000 pF or more in order to effectively eliminate the ripple component contained in the power supply voltage. In order to establish sufficient isolation from the capacitor 24 for use in reception, the resistor 25 a is needed to have a larger resistance value. However, the above necessity may not be permitted in terms of the breakdown voltage. For instance, nowadays, it is not unusual to allow current as large as 10 mA to flow in the information processing part 28. Also, the resistor 25 a is often required to have a resistance value equal to or greater than 1 kΩ. When 10 mA current flows through the 1 kΩ resistor, a voltage drop of approximately 10 V occurs. Therefore, the above may not be permitted for circuits consisting of elements with a breakdown voltage approximately equal to 10 V.
If the resistor 25 a having a smaller resistance is used, the capacitor 24 for the envelope detection will have an increased capacitance because of the capacitor 27. This deteriorates the envelope detection.
As described above, the card-type information processing device 20 has various unexpected problems occur due to increase in power consumed in the information processing part 28, and no means for solving these problems has not yet been proposed.
Further, in the above-mentioned conventional art, as shown in FIG. 12, the clock is generated in such a manner that the differential signal between RF1 and RF2 is extracted by the differential amplifier, and is level-shifted by the level shift circuit 30 f. When the analog signal is converted into the digital signal, the duty ratio may not equal to 50% because of noise and dispersion in performance. This causes unstable circuit operation.
Taking the above into consideration, an object of the present invention is to provide an information processing apparatus and a card-type information processing device that receives a carrier wave modulated in accordance with information and extracting the information and power from the carrier wave to thereby execute a predetermined process, wherein the apparatus and device can be easily designed and operate stably.
The above object of the present invention is achieved by an information processing apparatus receiving a carrier wave modulated in accordance with information and extracting the information and power from the carrier wave to thereby execute a predetermined process, wherein the information processing apparatus comprising: a receiving circuit receiving the carrier wave; a dc power generating circuit rectifying the carrier wave received by the receiving circuit to thereby generate dc power; a demodulation circuit, structurally independent of the dc power generating circuit, retrieving the information modulated onto the carrier wave; and an information processing circuit, supplied with the dc power as a power source, processing the information retrieved by the demodulation circuit in a given manner.
The above-mentioned object of the present invention is also achieved by a card-type information processing device receiving a carrier wave modulated in accordance with information and extracting the information and power from the carrier wave to thereby execute a predetermined process, wherein the card-type information processing device comprising: a receiving circuit receiving the carrier wave; a dc power generating circuit rectifying the carrier wave received by the receiving circuit to thereby generate dc power; a demodulation circuit, structurally independent of the dc power generating circuit, retrieving the information modulated onto the carrier wave; and an information processing circuit, supplied with the dc power as a power source, processing the information retrieved by the demodulation circuit in a given manner.
The above and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.
FIG. 1 is a block diagram of the operational principles of the present invention;
FIG. 10 is a block diagram of a card-type information processing device with the conventional type B contactless interface;
FIG. 11 is a block diagram of the card-type information processing device shown in FIG. 10; and
FIG. 12 is a circuit diagram of a carrier clock extraction circuit shown in FIG. 11.
FIG. 1 is a block diagram of the operational principles of the present invention. As shown in FIG. 1, an information processing apparatus 1 includes a receiving circuit 1 b, a dc power generating circuit 1 c, a demodulation circuit 1 d, and an information processing circuit 1 e. The information processing apparatus 1 receives information modulated onto the carrier wave sent by a reader/writer 2 and processes the extracted information in a predetermined manner. Note that, FIG. 1 shows only receiving section of the system for simplicity, and therefore transmitting section is omitted.
The receiving circuit 1 b receives the modulated carrier wave transmitted by the reader/writer 2 via a built-in antenna.
The dc power generating circuit 1 c rectifies the carrier wave received by the receiving circuit 1 b and thereby generates dc power.
The demodulation circuit 1 d is independent of the dc power generating circuit 1 c, and retrieves the information modulated onto the carrier wave.
The information processing circuit 1 e utilizes the dc power generated by the dc power generating circuit 1 c as power source, and processes the information retrieved by the demodulation circuit 1 d in a predetermined manner.
The receiving circuit 1 b of the information processing apparatus 1 receives the modulated carrier wave captured by a built-in antenna, and converts the carrier wave into a corresponding electric signal.
The dc power generating circuit 1 c fully rectifies the carrier wave from the receiving circuit 1 b so that dc power can be generated.
The demodulation circuit 1 d demodulates the carrier wave to retrieve information modulated onto the carrier wave.
The dc power generating circuit 1 c includes rectifying elements for the full-wave rectifying and a capacitor for eliminating the ripple component. The demodulation circuit 1 d includes a capacitor and a resistor for envelope detection of the carrier wave. These elements are independent of each other, so that interference between the elements can be avoided. This makes it possible to separately design the individual elements and simplify the design work.
The information processing circuit 1 e processes the information from the demodulation circuit 1 d in a given manner while utilizing the power from the dc power generating circuit 1 c as power source.
As described above, the dc power generating circuit 1 c and the demodulation circuit 1 d are separated from and independent of each other, and are not interfered. In addition, the designing can be simplified because of the separate arrangement of the dc power generating circuit 1 c and the demodulation circuit 1 d. A description will now be given of embodiments of the present invention.
The reader/writer has the same configuration as that of the conventional one shown in FIG. 10, and a description thereof will be omitted.
The power block 60 is made up of a capacitor 61, N-channel MOS-FETs 62�65, a voltage stabilizing circuit 66, a capacitor 67 and an information processing part 68. The power block 60 extracts dc power serving as a power supply voltage from the RF signal from the antenna 50.
The N-channel MOS-FETs 62�65 form a full-wave rectifier circuit. The gate and drain of the N-channel MOS-FET 62 illustrated on the upper side of FIG. 2 are connected. Similarly, the gate and drain of the N-channel MOS-FET 63 are connected. The N-channel MOS-FETs 62 and 63 allow current to pass from the lower side of the drawing to the upper, and prevent current in the reverse direction.
The gate of one of the N-channel MOS-FETs 64 and 65 shown on the lower side of FIG. 2 is connected to the drain of the other. Basically, for RF1>RF2, the N-channel MOS-FETs 64 and 65 are ON and OFF, respectively. For RF1<RF2, the N-channel MOS-FETs 64 and 65 are OFF and ON, respectively.
FIG. 3 is a circuit diagram of a configuration of the ASK demodulation circuit 75. As shown in FIG. 3, the ASK demodulation circuit 75 is made up of a LPF (low-pass filter) 75 a, a capacitor 75 b, resistors 75 c and 75 d, an operational amplifier 75 e, comparators 75 f and 75 g, and NAND elements 75 h and 75 i. The LPF 75 a eliminates an RF component contained in the signal after the envelope detection.
The capacitor 75 b is a coupling capacitor, which eliminates a dc component contained in the envelope-detected signal.
The resistors 75 c and 75 d and the operational amplifier 75 e form an inverting amplifier with an amplification factor of 1, which amplifier inverts the signal from the capacitor 75 b. For the amplification factor equal to 1, the resistors 75 c and 75 d have an identical resistance value.
The comparator 75 f compares the signal from the operational amplifier 75 e with a reference voltage Vr1. Then, the comparator 75 f outputs the power supply voltage when the input voltage is lower than the reference voltage Vr1, and outputs the ground (GND) voltage when the input voltage is higher than the reference voltage Vr1.
The comparator 75 g compares the output signal of the capacitor 75 b with a reference voltage Vr2. Then, the comparator 75 g outputs the power supply voltage when the input voltage is lower than the reference voltage Vr2, and outputs the ground voltage when the input voltage is higher than the reference voltage Vr2.
The NAND elements 75 h and 75 i form a latch circuit, which makes a set or reset operation in accordance with the signals from the comparators 75 f and 75 g. The output signal of the latch circuit has the level of the digital signal.
An operation of the above-mentioned embodiment of the present invention will now be described.
The reader/writer generates and transmits a radio wave as shown in FIG. 4. As shown in FIG. 4, the radio wave transmitted by the reader/writer includes �0� or �1� bit information ASK-modulated onto the carrier wave of a frequency of 13.56 MHz. More specifically, an amplitude A2, which is a high magnetic-field amplitude, corresponds to �1�, and an amplitude A1, which is a low magnetic-field amplitude, corresponds to �0�. The modulation factor defined as {(A2−A1)/(A1+A2)}�100 is set equal to 8�14%.
For RF1>RF2, the N-channel MOS-FETs 62 and 63 are ON and OFF, respectively. This allows current to flow in the voltage stabilizing circuit 66 from RF1.
For RF1<RF2, the N-channel MOS-FETs 63 and 62 are ON and OFF, respectively. This allows current to flow in the voltage stabilizing circuit 66 from RF2.
Preferably, the capacitor 67 has a capacitance of approximately 1000 pF in order to achieve the aforementioned objects of the invention. In the conventional circuit shown in FIG. 11, it is difficult to avoid interference with the envelope detection circuit when such a large capacitance is employed. In contrast, the present embodiment is capable of eliminating the interference because of an effective resistance of the N-channel MOS-FETs 62, 63, 71 and 72. It is therefore possible to accurately perform the envelope detection even when the capacitor 67 has a large capacitance.
In the case where the diodes 23 a�23 d are employed as in the conventional case shown in FIG. 11, the voltages RF1 and RF2 are fixed to constant levels due to the voltage stabilizing circuit 25 b and the forward voltage drops (ordinary 0.7 V) of the diodes 23 a�23 d. Thus, the ASK demodulation cannot be carried out efficiently. In contrast, the use of the MOS-FETs avoids the above drawback.
Further, if the diodes are fabricated by the ordinary CMOS process, a substrate current may flow to cause latchup. In contrast, the use of the MOS-FETs avoids the occurrence of latchup.
A capacitance approximately equal to 1000 pF is easily realized by utilizing the fabrication process for ferroelectric memories. It is also possible to provide a capacitor associated with the input terminal of the voltage stabilizing circuit 66 and thus eliminate the ripple. With this arrangement, it is also possible to eliminate the interference with the signal block on the contrary to the conventional circuit.
The current output from the information processing part 68 flows out to RF2 via the N-channel MOS FET 64 for RF1>RF2. In contrast, for RF1<RF2, the current flows out to RF1 via the N-channel MOS-FET 65.
In the signal block 70, the N-channel MOS-FETs 71 and 72 rectify the RF signal in the same manner as that of the N-channel MOS-FETs 62 and 63.
Since the N-channel MOS-FETs 71 and 72 are not required to take power, these transistors may be formed by relatively compact elements. Thus, there is no substantial increase in the size of the present embodiment circuit because of the separate arrangement of the N-channel MOS-FETs 71 and 72.
The capacitor 73 and the resistor 74 perform the envelope detection for the rectified RF signal. Thus, as shown in FIG. 5, the envelope connecting the peaks of the rectified RF signal is detected. The element values of the capacitor 73 and the resistor 74 are determined taking into consideration the frequency of the RF signal. Preferably, the resistor 74 has a resistance as large as possible in terms of suppression of power consumption. Our experiments exhibit that it is sufficient for the capacitor 73 to have a capacitance of at most 50 pF. For this capacitance value, it is sufficient for the resistor 74 to have a resistance value of 10 kΩ. In this case, the current value consumed by the resistor 74 is approximately 100 μA, which is sufficiently small.
The LPF 75 a of the ASK demodulation circuit 75 takes only the signal component from the RF signal.
The capacitor 75 b eliminates the dc component from the output signal of the LPF 75 a. The resistors 75 c and 75 d and the operational amplifier 75 e invert the output signal of the capacitor 75 b. The comparator 75 f compares the reference voltage Vr1 and the output of the operational amplifier 75 e, and the comparator 75 g compares the reference voltage Vr2 and the output of the capacitor 75 b. Each of the comparators 75 f and 75 g outputs a positive voltage when the input voltage to be compared is lower than the reference voltage, and outputs a negative voltage when the input voltage is higher than the reference voltage.
The NAND elements 75 h and 75 i form a latch circuit, which is set by the output of the comparator 75 f and is reset by the output of the comparator 75 g. Thus, a waveform-shaped digital-level signal is available from the NAND element 75 h. The digital signal thus generated is supplied to the information processing part 68.
In the clock extraction block 80, the N-channel MOS-FETs 81 and 82 cooperate with the N-channel MOS-FETs 64 and 65 to fully rectify the high-frequency signal. As in the case of the aforementioned N-channel MOS-FETs 71 and 72, the N-channel MOS-FETs 81 and 82 are not required to take power and can be formed by relatively compact elements. Thus, there is no substantial increase in the size of the present embodiment circuit because of the separate arrangement of the N-channel MOS-FETs 81 and 82.
FIG. 6(C) shows an example of the signal that is output by the frequency dividing circuit 86. As shown, the output of the frequency dividing circuit 86 is obtained by dividing the frequency of the output signal of the Schmidt trigger circuit 85 by 2. The signal output of the frequency dividing circuit 86 is 13.56 MHz, which is haft the frequency of 27.12 MHz.
As described above, according to the embodiment of the present invention, the power block 60 and the signal block 70 are independent of each other. This prevents the elements of the power block 60 and those of the signal block 70 from interfering each other, and enables simplified designing. Further, the most suitable elements can be employed as the resistors and capacitors, so that the power consumption can be reduced and the abilities of power supply and demodulation can be improved. This contributes to lengthening the communication distance.
In the present embodiment, the high-frequency signal is full-wave rectified and shaped into the appropriate waveform by the Schmidt trigger circuit 85, and is divided by 2 by the frequency dividing circuit 86. Thus, the clock having the duty ratio 50% can be generated.
Also, according to the present invention, the rectifying elements in each block employ MOS-FETs. This enhances affinity with the semiconductor process and effectively suppresses the occurrence of latchup because of the substrate current, as compared to the case with diodes. Further, each MOS-FET has a given ON resistance, which enhances isolation between blocks and suppresses the interference therebetween.
The resistors 121 and 122 have mutually different resistance values so as to have different time constants defined in connection with the capacitor 73. More specifically, the resistor 121 defines a time constant (large time constant) when the carrier wave has a low frequency, and the resistor 122 defines a time constant (small time constant) when the carrier wave has a high frequency. For example, the resistor 121 has a resistance value of about 40 k Ω, and the resistor 122 has a resistance value of about 20 kΩ in a case where there are two data transmission rates of 105.9375 Kbps and 211.875 Kbps and the capacitor 73 has a capacitance of 50 pF.
In the above-mentioned manner, the resistance is selected in accordance with the frequency of the carrier wave, the envelope detection is performed at the optimal time constant. Thus, the accuracy of the envelope detection can be improved and power consumption at low frequency can be reduced.
Although the above embodiment of the invention employs two resistors, more than two resistors may be provided and selectively used.
For RF1>RF2, the P-channel MOS-FET 140 is turned ON, while the P-channel MOS-FET 141 is turned OFF. Thus, current flows to Vdd from RF1 via the P-channel MOS-FET 140.
Here, the diode connected N-channel MOS-FET 142 is forward biased and is turned ON for GND>RF2, while the diode connected N-channel MOS-FET 143 is reverse biased and is turned OFF. Thus, the current that is input from Vdd and flows in the circuit flows out to RF2 via the N-channel MOS-FET 142.
For RF1<RF2, the P-channel MOS-FET 140 is turned OFF, while the P-channel MOS-FET 141 is turned ON. Thus, current flows to Vdd from RF2 via the P-channel MOS-FET 141.
Here, the diode connected N-channel MOS-FET 143 is forward biased and is turned ON for GND<RF2, while the diode connected N-channel MOS-FET 142 is reverse biased and is turned OFF. Thus, the current that is input from Vdd and flows in the circuit flows out to RF1 via the N-channel MOS-FET 143.
Referring to FIG. 9, the full-wave rectifier circuit is made up of P-channel MOS-FETs 161�166 and N-channel MOS-FETs 167 and 168.
More specifically, the source of the P-channel MOS-FET 161 is connected to RF1, and the gate and drain thereof are connected to Vdd, the substrate thereof being connected to the drain of the P-channel MOS-FET 162, its substrate, the drain of the P-channel MOS-FET 163 and its substrate.
First, a case where RF1>RF2 is described. In this case, the P-channel MOS-FET 161 is forward biased and is turned ON, while the P-channel MOS-FET 164 is reverse biased and is turned OFF.
A case where RF1<RF2 is described below.
As described above, according to the embodiment shown in FIG. 9, the use of the P-channel MOS-FETs avoids the substrate biasing effect, as compared to the rectifying circuit with the N-channel MOS-FETs shown in FIG. 2 and suppresses voltage drop at the time of ON. This improves the rectifying efficiency.
As described above, according to the present invention, there is provided an information processing apparatus receiving a carrier wave modulated in accordance with information and extracting the information and power from the carrier wave to thereby execute a predetermined process, wherein the information processing apparatus includes: a receiving circuit receiving the carrier wave; a dc power generating circuit rectifying the carrier wave received by the receiving circuit to thereby generate dc power; a demodulation circuit, structurally independent of the dc power generating circuit, retrieving the information modulated onto the carrier wave; and an information processing circuit, supplied with the dc power as a power source, processing the information retrieved by the demodulation circuit in a given manner. With the above structure, it is possible to realize higher performance and lower power consumption of the demodulation circuit.
There is also provided a card-type information processing apparatus receiving a carrier wave modulated in accordance with information and extracting the information and power from the carrier wave to thereby execute a predetermined process, wherein the card-type information processing device includes: a receiving circuit receiving the carrier wave; a dc power generating circuit rectifying the carrier wave received by the receiving circuit to thereby generate dc power; a demodulation circuit, structurally independent of the dc power generating circuit, retrieving the information modulated onto the carrier wave; and an information processing circuit, supplied with the dc power as a power source, processing the information retrieved by the demodulation circuit in a given manner. Thus, it is possible to more easily design the card-type information processing device.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5847447Jul 9, 1996Dec 8, 1998Ambient CorporationCapcitively coupled bi-directional data and power transmission systemUS5889273 *Sep 18, 1996Mar 30, 1999Kabushiki Kaisha ToshibaWireless communication data storing medium for receiving a plurality of carriers of proximate frequencies and a transmission/receiving methodUS5914980 *Sep 20, 1996Jun 22, 1999Kabushiki Kaisha ToshibaWireless communication system and data storage mediumUS6784730 *May 21, 2003Aug 31, 2004Sony CorporationContactless IC card systemEP0289136A2Mar 25, 1988Nov 2, 1988Electo-Galil Ltd.Electronic data communications systemEP0764920A2Sep 17, 1996Mar 26, 1997Kabushiki Kaisha ToshibaWireless communication data storing medium for receiving a plurality of carriers of proximate frequencies and a transmission/receiving methodJPH11355367A Title not available* Cited by examinerNon-Patent CitationsReference1 *EM Micoelectronic, "P4150-1 KBit read/write contactless identification device", Dec. 1999.2Patent Abstract of Japan vol. 2000, No. 03, Mar. 30, 2000 & JP 11 355367, Dec. 24, 1999.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7515925 *Dec 29, 2004Apr 7, 2009Kabushiki Kaisha ToshibaWireless communication device for periodically controlling a carrier wave to establish a good communication state with a communication objectUS7978787May 25, 2006Jul 12, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS8094024 *Jul 10, 2009Jan 10, 2012Au Optronics Corp.Amplitude shift keying demodulator and radio frequency identification system using the sameUS8463116Jul 1, 2008Jun 11, 2013Tap Development Limited Liability CompanySystems for curing deposited material using feedback control* Cited by examinerClassifications U.S. Classification713/300, 235/492, 329/347International ClassificationG06K17/00, G06F1/26, H04B1/59, G06F1/04, G06K19/07Cooperative ClassificationG06K19/0701, G06K19/0723European ClassificationG06K19/07A, G06K19/07TLegal EventsDateCodeEventDescriptionMar 14, 2013FPAYFee paymentYear of fee payment: 8Jul 22, 2010ASAssignmentFree format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:024982/0245Effective date: 20100401Owner name: FUJITSU SEMICONDUCTOR LIMITED, JAPANJul 22, 2009FPAYFee paymentYear of fee payment: 4Dec 12, 2008ASAssignmentOwner name: FUJITSU MICROELECTRONICS LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021998/0645Effective date: 20081104Owner name: FUJITSU MICROELECTRONICS LIMITED,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100225;REEL/FRAME:21998/645Feb 1, 2002ASAssignmentOwner name: FUJITSU LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MASUI, SHOICHI;KANEKO, YOSHIAKI;REEL/FRAME:012555/0612Effective date: 20020110RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services