Source: http://www.google.com/patents/US5304502?ie=ISO-8859-1&dq=6948823
Timestamp: 2014-10-01 13:43:41
Document Index: 792392429

Matched Legal Cases: ['art 43', 'art 43', 'art 43', 'art 115', 'art 116', 'art 116']

Patent US5304502 - Process of fabricating semiconductor integrated circuit having conductive ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsIn a process according to the present invention, a polysilicon gate electrode and a high resistive polysilicon strip are simultaneously patterned on an active area and on a thick field oxide film, respectively, and the gate electrode and the polysilicon strip are covered with thin silicon oxide films,...http://www.google.com/patents/US5304502?utm_source=gb-gplus-sharePatent US5304502 - Process of fabricating semiconductor integrated circuit having conductive strips used as resistor and gate electrode of component transistorAdvanced Patent SearchPublication numberUS5304502 APublication typeGrantApplication numberUS 07/887,657Publication dateApr 19, 1994Filing dateMay 26, 1992Priority dateNov 8, 1988Fee statusPaidPublication number07887657, 887657, US 5304502 A, US 5304502A, US-A-5304502, US5304502 A, US5304502AInventorsOsamu HanagasakiOriginal AssigneeYamaha CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (25), Non-Patent Citations (4), Referenced by (38), Classifications (14), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetProcess of fabricating semiconductor integrated circuit having conductive strips used as resistor and gate electrode of component transistorUS 5304502 AAbstract In a process according to the present invention, a polysilicon gate electrode and a high resistive polysilicon strip are simultaneously patterned on an active area and on a thick field oxide film, respectively, and the gate electrode and the polysilicon strip are covered with thin silicon oxide films, respectively, then impurities being doped in the active area to form source and drain regions, then the thin silicon oxide film being removed from the gate electrode, then a refractory metal silicide film being formed on the gate electrode, however, the formation of the refractory metal silicide film does not affect the polysilicon strip, because the thin silicon oxide film is left thereon, which results in maintaining the polysilicon strip in the high resistivity and, accordingly, in that the polysilicon strip provides a resistor with a large resistance but occupies a small amount of area.
What is claimed is: 1. A process of integrating a circuit on a semiconductor substrate, comprising the steps of:a) preparing a semiconductor substrate of a first conductivity type; b) providing a thick field oxide film to define a first active area of a second conductivity type opposite to said first conductivity type and a second active area of said first conductivity type; c) forming first oxide films on said first and second active areas; d) forming first and second gate electrodes of lightly doped polysilicon on said first oxide films and a resistor of the lightly doped polysilicon on said thick field oxide film; e) forming lightly doped source and drain regions of said first conductivity type in a self aligned manner with said first gate electrode; f) forming lightly doped source and drain regions of said second conductivity type in a self aligned manner with said second gate electrode; g) covering said first and second gate electrodes with second oxide films and said resistor with a third oxide film; h) forming a first patterned photoresist layer for covering a part of said third oxide film on said resistor and said second active region and exposing said first active area and the rest of said third oxide film on said resistor; i) forming heavily doped source and drain regions of said first conductivity type partially overlapped with said lightly doped source and drain regions in said first active area by using an ion implantation, thereby forming composite source and drain regions in said first active area; j) removing said first oxide film, said second oxide film and said rest of said third oxide film from surfaces of said heavily doped source and drain regions in said first active area, a surface of said gate electrode and a portion of said resistor to thereby expose said portion of said resistor corresponding to said rest of said third oxide, respectively, and leaving said part of said third oxide film on a surface of said resistor; k) removing said first patterned photoresist layer; l) forming a second patterned photoresist layer covering said part of said third oxide film on said resistor, said portion of said resistor and said first active area, and exposing said second active area; m) forming heavily doped source and drain regions of said second conductivity type partially overlapped with said lightly doped source and drain regions in said second active area by using an ion implantation, thereby forming composite source and drain regions in said second active area; n) removing said first and second oxide films from surfaces of said heavily doped source and drain regions in said second active area and a surface of said second gate electrode, respectively, and leaving said third oxide film on the surface of said resistor; o) removing said second patterned photoresist layer; p) forming silicide films on the exposed source and drain regions, surfaces of said first and second gate electrodes and said portion of said resistor; and q) providing interconnections for said circuit. 2. A process for integrating a circuit on a semiconductor substrate, comprising the steps of:a) preparing a semiconductor substrate of a first conductivity type; b) defining first and second active areas by a thick field oxide film; c) forming first oxide films on said first and second active areas; d) forming first and second gate electrodes of lightly doped polysilicon on said first oxide films and a resistor of the lightly doped polysilicon on said thick field oxide film; e) covering said first and second gate electrodes with second oxide films and said resistor with a third oxide film; f) forming a first patterned photoresist layer covering a part of said third oxide film on said resistor and said second active region and exposing said first active area and the rest of said third oxide film on said resistor; g) implanting first conductivity type ions into said first active area with said first gate electrode to thereby provide doped source and drain regions of said first conductivity type in said first active area; h) removing said first oxide film, said second oxide film and said rest of said third oxide film from surfaces of said doped source and drain regions in said first active area, a surface of said first gate electrode and a portion of said resistor to thereby expose said portion of said resistor corresponding to said rest of said third oxide respectively, and leaving said part of said third oxide film on a surface of said resistor; i) removing said first patterned photoresist layer; j) forming a second patterned photoresist layer for covering said part of said third oxide film on said resistor, said portion of said resistor and said first active area, and exposing said second active area; k) implanting second conductivity type ions into said second active area with said second gate electrode to thereby provide doped source and drain regions of said second conductivity type; l) removing said first and second oxide films from surfaces of said doped source and drain regions in said second active area and a surface of said second gate electrode, respectively, and leaving said third oxide film on the surface of said resistor; m) removing said second patterned photoresist layer; n) forming silicide films on the exposed source and drain regions, surfaces of said first and second gate electrodes and said portion of said resistor; and o) providing interconnections for said circuit. 3. A process as set forth in claim 1, in which said step (e) comprises the sub-step of doping the second active area with impurities of said second conductivity type.
4. A process as set forth in claim 1, in which said step (g) comprises the sub-steps of:g-1) depositing a fourth oxide film over said first and second gate electrodes and said resistor; g-2) anisotropically etching said fourth oxide film to form side spacers on both sides of each of said first and second gate electrodes and on both sides of said resistor; and g-3) oxidizing said substrate to form fifth and sixth oxide films on top surfaces of said first and second gate electrodes and said resistor. Description
This application is a continuation, of application Ser. No. 07/441,911, filed Nov. 28, 1989, now abandoned.
FIELD OF THE INVENTION This invention relates to a process of fabricating a semiconductor integrated circuit and, more particularly, to a process of simultaneously fabricating conductive strips providing a resistor and a gate electrode of a component field effect transistor.
BACKGROUND OF THE INVENTION In the integrated circuit device are fabricated a large number of circuit component elements which are coupled by a conductive pattern so that a predetermined function or functions are achieved in cooperation of the component elements, however, some of the circuit component elements such as, for example, resistors are implemented by the conductive pattern per se.
A typical example of this sort of arrangement is illustrated in FIG. 1. Reference numeral 1 designates a lightly doped p-type single crystalline silicon substrate, and a thick field oxide film 2 is grown on the silicon substrate 1, defining an active area where a component field effect transistor 3 is fabricated. The component field effect transistor 3 has a lightly-doped drain structure (which has been abbreviated as "LDD-structure"), and largely comprises heavily doped n-type source and drain regions 4 and 5, a gate structure 6 formed over that area between the heavily doped n-type source and drain regions 4 and 5, and lightly-doped n-type source and drain regions 7 and 8 extending from the heavily doped n-type source and drain regions 4 and 5. The gate structure is of a self-aligned silicide structure, and largely comprises a thin gate oxide film 9, a multiple-level gate electrode consisting of a lower polysilicon film 10 and an upper refractory metal silicide film 11, and side spacers 12 and 13 provided on both sides of the lower polysilicon film 10. The heavily doped n-type source and drain regions 4 and 5 are overlain by refractory metal silicide films 14 and 15, respectively, and the refractory metal silicide films 11, 14 and 15 aims at improvement in conductivity.
On the thick field oxide film 2 is formed an interconnection which also has a multiple-level structure. Namely, a lower polysilicon film 16 is directly formed on the thick field oxide film 2, and is overlain by a refractory metal silicide film 17. Side spacers 18 and 19 are provided on both sides of the lower polysilicon film 16, and the interconnection is merged into the gate structure 6. The interconnection is adapted to provide a large resistance and serves as a resistor 20. Thus, the polysilicon strip is partially used as the resistor 20 and partially provides the gate structure 6.
The process of fabricating the prior art structure starts with preparation of the lightly doped p-type single crystalline silicon substrate 1. The thick field oxide film 2 is thermally grown on the substrate 1 by using the localized oxidation of silicon technique, and the substrate 1 is placed in a high temperature ambience again to grow a thin silicon oxide film.
On the thin silicon oxide film is deposited a polycrystalline silicon film which is, then, patterned by using the lithographic techniques. Using the polysilicon strip thus patterned as an ion-implantation mask, n-type impurity atoms are introduced into the active area defined in the substrate 1 so that the lightly doped source and drain regions 7 and 8 are formed in the substrate 1. With the n-type impurity atoms, the polysilicon strip is lowered in resistivity.
A silicon oxide film is deposited over the entire surface of the structure, and is anisotropically etched away to form the side spacers 12, 13, 18 and 19. The thin silicon oxide film is simultaneously removed in the anisotropic etching process, and the active area between the thick field oxide film 2 and the side spacers 12 and 13 is exposed. The thin silicon oxide film left on the active area serves as the thin gate oxide film 9.
N-type impurity atoms are implanted into the exposed active area so that the heavily doped source and drain regions 4 and 5 are formed in the active area. The n-type impurity atoms are also introduced in the polysilicon strip, and the polysilicon strip is further improved in the resistivity. After the formation of the heavily doped source and drain regions 4 and 5, a conductive refractory metal is deposited over the entire surface of the structure, and the substrate is placed in a high temperature ambience. In the high temperature ambience, the conductive refractory metal reacts on the polysilicon and the single crystalline silicon, and is converted into a refractory metal silicide film. The non-reactive or residual refractory metal is etched away, and, accordingly, the refractory metal silicide films 11, 14, 15 and 17 are formed on the lower polysilicon film 10, the heavily doped source and drain regions 4 and 5 and the lower polysilicon film 16, respectively.
However, a problem is encountered in the prior art integrated circuit in that the resistor 20 occupies a large amount of area. This is because of the fact that the polysilicon strip is exposed to the ion implantation twice and overlain by the refractory metal silicide. The more impurity atoms a polysilicon strip contains, the lower resistivity it provides. Moreover, a refractory metal silicide is much smaller in resistivity than a polysilicon. The low resistive interconnection should be prolonged to provide an amount of large resistance, and, for this reason, the resistor 20 occupies a large amount of the real estate. This deteriorates the integration density, or the chip size is enlarged so as to fabricate all of the component elements.
A mask layer may provide a solution of this problem. In detail, if a photoresist mask layer is provided on the entire surface of the structure and exposes the upper refractory metal silicide film 17, the upper refractory metal silicide film 17 is selectively removed from the lower polysilicon film. However, this solution makes the process sequence complex and, accordingly, increases the production cost of the integrated circuit. Moreover, a mask pattern is liable to be improperly transferred to the photoresist film, and the resist image tends to deviate from the mask image. This results in fluctuation of resistance due to difference in geometry. The fluctuation may not be material to a digital application, however, it is serious to an analog application. The improper image transfer requests a tolerance, and, for this reason, the occupation area tends to be increased.
SUMMARY OF THE INVENTION It is therefore an important object of the present invention to provide a process through which a semiconductor integrated circuit is fabricated on a relatively small occupation area.
It is also an important object of the present invention to provide a process the sequence of which is less complex to simultaneously form multiple-level conductive structures used as a resistor and a gate structure of a component field effect transistor.
It is another important object of the present invention to provide a process which can exactly adjust the resistance of a conductive strip and is, accordingly, preferable to fabricate an analog circuit.
To accomplish these objects, the present invention proposes to cover a polysilicon resistor with an oxide film during producing silicide films.
In accordance with the present invention, there is provided a process of integrating a circuit on a semiconductor substrate, comprising the steps of: a) preparing a semiconductor substrate of a first conductivity type; b) defining an active area by a thick field oxide film; c) forming a first oxide film on the active area; d) forming a gate electrode of a lightly doped polysilicon on the first silicon oxide film and a resistor of the lightly doped polysilicon on the thick field oxide film; e) forming lightly doped source and drain regions of a second conductivity type opposite to the first conductivity type in a self aligned manner with the gate electrode; f) covering the gate electrode and the resistor with second and third oxide films, respectively; g) forming heavily doped source and drain regions of the second conductivity type partially overlapped with the lightly doped source and drain regions, thereby forming composite source and drain regions in the active area; h) removing the first and second oxide films from the surfaces of the heavily doped source and drain regions and a top surface of the gate electrode, respectively, and leaving the third oxide film on a top surface of the resistor; i) forming conductive refractory metal silicide films on the respective surfaces of the heavily doped source and drain regions and the top surface of the gate electrode, respectively; j) removing the third oxide film from the top surface of the resistor; and k) providing interconnections so as to complete the circuit.
BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of a process of fabricating a semiconductor integrated circuit according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a cross sectional view showing the structure of a semiconductor integrated circuit fabricated through a prior art process sequence;
FIGS. 2A to 2J are cross sectional views showing a process sequence embodying the present invention;
FIG. 3 is a plan view showing the layout of a resistor formed by using the process shown in FIGS. 2A to 2J;
FIG. 4 is a circuit diagram showing the arrangement of an input protection circuit to which a process according to the present invention appertains;
FIG. 5 is a plan view showing the layout of the input protection circuit shown in FIG. 4; and
FIG. 6 is a circuit diagram showing a digital-to-analog converting circuit according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT Referring first to FIG. 2A of the drawings, a process according to the present invention starts with preparation of a lightly doped n-type single crystalline silicon substrate 21. P-type impurities such as, for example, boron atoms are selectively doped into the substrate 21 so that a p-well 22 is formed in the surface portion of the substrate 21. A thick field oxide film 23 is thermally grown on the surface portion by using the localized oxidation of silicon technique, and active areas 24 and 25 are defined by the thick field oxide film 23. The single crystalline silicon substrate 21 is, then, oxidized in a high temperature ambience so that thin silicon oxide films are grown on the active areas 24 and 25, respectively.
On the entire surface of the structure is deposited a polysilicon film which is etched and patterned to form polysilicon strips 26a, 26band 26c. In this instance, the polysilicon film is deposited by using a chemical vapor deposition technique, and the polysilicon is doped with n-type impurities by in-situ doping. However, a post-deposition doping may be carried out in another implementation. The amount of the dopant is adjusted to provide a certain resistivity which allows the polysilicon strip 26b to achieve a predetermined resistance considering the geometry thereof. The polysilicon strip 26b extends on the thick field oxide film 23, and the polysilicon strips 26a an 26c are formed on the thin silicon oxide films in the active areas 24 and 25.
After the formation of the polysilicon strips 26a, 26b and 26c, a photoresist solution is dropped onto the structure, and is spread over the entire surface. The photoresist film is, then, patterned by using lithographic techniques so that a patterned photoresist layer 27 is formed on the substrate 21 and exposes the active area 24. N-type impurities such as, for example, phosphorus atoms or arsenic atoms are implanted into the active area 24 in a self-aligned fashion, and, accordingly, lightly doped source and drain regions 28 and 29 are formed under those areas on both sides of the polysilicon strip 26a. The polysilicon strip 26a in the active area 24 is exposed to the ion implantation, and the conductivity thereof is enhanced by the implanted n-type impurities. However, the polysilicon strip 26b on the thick field oxide film 23 is free from the ion implantation, and, for this reason, the resistivity thereof remains in the aforementioned certain value. The resultant structure of this stage is illustrated in FIG. 2A.
The patterned photoresist layer 27 is stripped off, and a fresh photoresist solution is spun onto the entire surface of the structure. The photoresist film is patterned to form a photoresist layer 30 which covers the active area 24 and the thick field oxide film 23, but exposes the active area 25. Using the patterned photoresist layer 30 and the polysilicon strip 26c in the active area 25 as an ion implantation mask, p-type impurities such as, for example, boron atoms are implanted into the active area 25 to form lightly doped p-type source and drain regions 31 and 32. The polysilicon strip 26b on the thick field oxide film 23 is free from the ion implantation again so that the effective impurity concentration is constant over the doping process. Thus, the impurity concentration and, accordingly, the resistivity are decided by the in-situ doping or the post-deposition doping only, and the patterned photoresist layers 27 and 30 are necessary to form the impurity regions different in the conductivity type. For this reason, the resistivity of the polysilicon strip 26b is precisely adjusted without making the process sequence complex. In other words, if the polysilicon strip 26b on the thick field oxide film 23 is exposed to the ion implantations, the final effective impurity concentration is not controllable, and, accordingly, the resistance is much liable to deviate from the predetermined value. However, the resistance of the polysilicon strip 26b on the thick field oxide film 23 is precisely adjustable by virtue of the patterned photoresist layers 27 and 30. After the formation of the lightly doped source and drain regions 31 and 32, the patterned photoresist layer 30 is removed from the surface, and the resultant structure of this stage is illustrated in FIG. 2B.
The subsequent step is deposition of a silicon oxide film, and a chemical vapor deposition technique is applicable to this step. The silicon oxide film thus deposited is anisotropically etched to form side spacers 33a, 33b, 33c, 33d, 33e and 33f, and the thin silicon oxide films on the active areas are selectively removed from the active areas 24 and 25 to form gate oxide films 35 and 36, respectively. The resultant structure of this stage is illustrated in FIG. 2C.
The resultant structure is placed in an oxidation ambience, and thin silicon oxide films 37, 38, 39a, 39b, 39c, 40 and 41 cover the lightly doped source and drain regions 28, 29, 31 and 32 as well as the top surface of the polysilicon strips 26a, 26b and 26c as shown in FIG. 2D.
A photoresist solution is dropped on the surface of the structure, and is spread over the entire surface to form a photoresist film. The photoresist film is, then, patterned by using the lithographic techniques so that a photoresist layer 42 exposes the active area 24 and a part 43a of the polysilicon strip 26b on the thick field oxide film 23. The part 43a of the polysilicon strip 26 provides a contact area where an interconnection is brought into contact in a later stage. N-type impurities are heavily introduced into the active area 24 and the exposed polysilicon strip 26 through the thin silicon oxide films 37 to 39 by using the ion implantation technique followed by a drive-in process, and the heavily doped source and drain regions 44 and 45 are formed in the active area 24 in a partially overlapping manner with the lightly doped source and drain regions 28 and 29, respectively. Thus, the LDD (Lightly-Doped Drain) structure is fabricated in the active area 24, and the composite drain region is hardly broken down by virtue of the lightly doped region 28 or 29. This improves the withstand voltage of the p-n junction between the composite drain region and the substrate 21. The n-type impurities are also introduced in the exposed polysilicon strip 26b and these n-type impurities decrease the resistivity of the part 43a of the polysilicon strip 26b. The contact area 43a thus increased in the impurity concentration is capable of formation of an ohmic contact. The layout of the polysilicon strip 26b and the arrangement of the contact areas 43a and 43b will be seen from FIG. 3 of the drawings.
However, most of the polysilicon strip 26 on the thick field oxide film 23 is covered with the patterned photoresist layer 42 so that variation in the resistivity is negligible, and, accordingly, the resistance is deemed to be constant. Thus, the patterned photoresist layer 42 is conducive to keeping the resistivity of the polysilicon strip constant. The resultant structure of this stage is illustrated in FIG. 2E.
After the formation of the composite source and drain regions, the silicon oxide films 37, 38 and 39 are removed through an etching process so that the n-type impurity regions 44 and 45 as well as the polysilicon strip 26 on the active area 24 are exposed as will be understood from FIG. 2F. The etching is of either dry or wet process.
After the patterned photoresist layer 42 is stripped off, a fresh photoresist solution is spun onto the entire surface of the structure, and the photoresist film thus formed is patterned to provide a photoresist layer 51 exposing the active area 25. P-type impurities are heavily doped into the active area 25 followed by a drive-in process so that heavily doped source and drain regions 52 and 53 are formed in a self-aligned manner. The heavily doped source and drain regions 52 and 53 are partially overlapped with the lightly doped source and drain regions 31 and 32, respectively, and the LDD or lightly-doped drain structure is also achieved in the active ares 25. While implanting the p-type impurities, the patterned photoresist layer 51 prevents the polysilicon strips 26b and 26c from the p-type impurities, and, accordingly, no fluctuation takes place in the resistivity of the polysilicon strip 26b. The resultant structure of this stage is illustrated in FIG. 2G.
The thin silicon oxide films 40, 41 and 39c are etched away to expose the heavily doped source and drain regions 52 and 53 as well as the polysilicon strip 26c on the active area 25. The etching technique is of the dry process or the wet process, and the resultant structure is shown in FIG. 2H.
When the patterned photoresist layer 51 is stripped off, the polysilicon strips 26a and 26c on the active areas 24 and 25 are exposed, however, the polysilicon strip 26b on the thick field oxide film 23 is covered with the thin silicon oxide film 39b except for the contact areas 43a and 43b. No thin silicon oxide film covers the heavily doped source and drain regions 44, 45, 52 and 53, and the surfaces thereof are exposed. A refractory metal such as titanium is deposited over the entire surface of the structure, and the substrate 21 is placed in a high temperature ambience so that the refractory metal reacts with the polysilicon and the single crystalline silicon. Thus, refractory metal silicide films 61, 62, 63, 64, 65, 66 and 67 are formed on the heavily doped source and drain regions 44, 45, 52, and 53, the exposed polysilicon strip 26, respectively. After the formation of the refractory metal silicide films 61 to 67, the residual refractory metal is removed from the structure. Since the thin silicon oxide film 39 has been left on the polysilicon strip 26 b on the thick field oxide film 23, no refractory metal silicide overlies the polysilicon strip 26b serving as a resistor 75 with a large amount of resistance, and, for this reason, the silicide process does not affect the resistivity of the polysilicon strip 26b on the thick field oxide film 23. The thin gate oxide film 35, the side spacers 33a and 33b, the polysilicon film 26a and the refractory metal silicide film 65 form in combination a multiple-level gate structure 71, and the multiple-level gate structure 71 and the source and drain regions 28, 29, 44 and 45 as a whole constitute an n-channel MOS type field effect transistor 72. Similarly, the thin gate oxide film 36, the side spacers 33e and 33f, the polysilicon strip 26c and the refractory metal silicide film 66 form in combination a multiple-level gate structure 73, and the multiple-level gate structure 73 and the source and drain regions 31, 32, 52 and 53 as a whole constitute a p-channel MOS type field effect transistor. Moreover, the polysilicon strip 26 without any refractory metal silicide film provides the resistor 75. The resultant structure of this stage is shown in FIG. 2I.
After the thin silicon oxide film 39b is removed, a silicon oxide is deposited by using the chemical vapor deposition technique so that an inter-level insulating layer 76 covers the entire surface of the structure. A contact window 77 is formed in the inter-level insulating layer 76, and an aluminum alloy is deposited over the entire surface. The aluminum alloy is patterned to form an interconnection 78. Although the gate structures 71 and 73 are respectively coupled to interconnections, FIG. 2J does not show the interconnections. The resultant structure is shown in FIG. 2J.
Turning to FIGS. 4 and 5 of the drawings, there is shown an input protection circuit which is integrated on a semiconductor substrate 100 through a process sequence according to the present invention. In FIGS. 4 and 5, reference numeral 101 designates a bonding pad coupled to a lead frame via. an aluminum bonding wire (not shown), and the bonding pad 101 is formed on a thick field oxide film and partially covered with a passivation film 102. The bonding pad 101 has a lug portion 103 coupled to a lightly doped n-type impurity region 104 formed in the p-type semiconductor substrate 100, and the n-type impurity region 104 has a generally inversed-L shape. Another n-type impurity region 106 is formed in the semiconductor substrate 100 in a spacing relationship with a part of the impurity region 104. The thick field oxide film extends over that area between the impurity regions 104 and 106, and the bonding pad 100 also extends over the area. The lightly doped n-type impurity region 104 provides a resistor 107 and forms a drain region of a protective transistor 108. The bonding pad 100 provides a gate electrode of the protective transistor 108, and the thick field oxide film serves as a gate oxide film. The n-type impurity region 106 is coupled to a ground line 109 so that the protective transistor 108 turns on to discharge an excess high voltage level due to, for example, a surge current, however, the protective transistor 108 remains in the off state in so far as a signal swings its voltage level in a predetermined range.
The lightly doped n-type impurity region 104 is further coupled to a multi-level conductive wiring 110 extending over the thick filed oxide film, and the multi-level conductive wiring 110 consists of a lower polycrystalline silicon film and an upper refractory metal silicide film. The multi-level conductive wiring 110 partially provides a resistor 111, and is shared with the respective gate electrodes of field effect transistors 112 and 113. Then, the multi-level conductive wiring 110 should be partially high-resistive for the resistor 111 and partially low-resistive for the gate electrodes of the component transistors.
The input protective circuit thus arranged is fabricated through a process sequence similar to that illustrated in FIGS. 2A to 2J except for the ion implantation stages. Namely, no ion implantation is carried out with p-type impurities, however, the polysilicon strip is covered with a thin silicon oxide film similar to the stage shown in FIG. 2D. The thin silicon oxide film is partially removed from a part 115 of the polysilicon strip after the ion implantation for the heavily doped source and drain regions, however, the thin silicon oxide film is left on the other part 116 of the polysilicon strip 110 for the resistor 111. The formation of the refractory metal silicide films are, then, carried out to enhance the conductivity of the gate electrodes of the component transistors, however, the thin silicon oxide film prevents the other portion 116 of the polysilicon strip 110 from the silicide process. Thus, the other part 116 is large in resistivity, and, for this reason, the occupation area is relatively small.
The present invention is applicable to a digital-to-analog converting circuit shown in FIG. 6. The digital-to-analog converting circuit shown in FIG. 6 is supplied with a multi-bit input signal D0, D1, Dn-2 and Dn-1, and the bits of the multi-bit input signal D0 to Dn-1 are transferred to complementary inverter circuits Q1, Q2, . . . , Qn-2 and Qn-1, and the complementary inverter circuits Q1 to Qn-1 are associated with resistors R1, R2, Rn-2 and Rn-1. A series combination of resistors Rv1, Rv2, . . . , Rvm-2, Rvm-1 and Rvm is coupled between an output node OUT and a ground node, and each of the resistors R1, R2, Rn-2 or Rn-1 is coupled between the two adjacent resistors of the series combination. The resistors R1, R2, . . . , Rn-2 and Rn-1 are as large in resistance as the resistor Rvm, however, the resistance of each of the resistors Rv1, Rv2, . . . , Rvm-2 or Rvm-1 is a half of that of the resistor Rvm.
The voltage level V0 at the output node OUT depends on the bit string of the input signal, and is given by the follow equation:
V0=(Vs/3)(Dn-1�20 +Dn-2�2-1 +. . . +D1�2-(n-2) +D0�2-(n-1))
where Vs is a reference voltage level. The resistance of each resistor is selected to be much larger than the channel resistance of the component transistor of each complementary inverter circuit, and the accuracy of the digital-to-analog converting circuit is affected by the difference between a target resistance and an actual resistance of each resistor. According to the present invention, the resistance is precisely adjusted to the target value, and, for this reason, a high accuracy is achieved by the digital-to-analog converting circuit.
As will be understood from the foregoing description, since the thin silicon oxide film protects the polysilicon strip from the silicide process, the resistor occupies a relatively small amount of the real estate without sacrifice of the simple process sequence.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3865649 *Oct 16, 1972Feb 11, 1975Harris Intertype CorpFabrication of MOS devices and complementary bipolar transistor devices in a monolithic substrateUS4057894 *Feb 9, 1976Nov 15, 1977Rca CorporationControllably valued resistorUS4208781 *Jun 15, 1978Jun 24, 1980Texas Instruments IncorporatedSemiconductor integrated circuit with implanted resistor element in polycrystalline silicon layerUS4212083 *Aug 18, 1978Jul 8, 1980Texas Instruments IncorporatedMOS Integrated with implanted resistor elementsUS4246692 *May 28, 1976Jan 27, 1981Texas Instruments IncorporatedMOS Integrated circuits with implanted resistor elementsUS4256515 *Oct 26, 1979Mar 17, 1981Sprague Electric CompanyP-n-p and n-p-n transistorsUS4291328 *Jun 15, 1979Sep 22, 1981Texas Instruments IncorporatedSemiconductorsUS4367580 *Mar 21, 1980Jan 11, 1983Texas Instruments IncorporatedProcess for making polysilicon resistorsUS4370798 *Jul 20, 1981Feb 1, 1983Texas Instruments IncorporatedInterlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline siliconUS4391650 *Dec 22, 1980Jul 5, 1983Ncr CorporationMethod for fabricating improved complementary metal oxide semiconductor devicesUS4408385 *Jun 23, 1980Oct 11, 1983Texas Instruments IncorporatedSemiconductor integrated circuit with implanted resistor element in polycrystalline silicon layerUS4416049 *Jan 8, 1981Nov 22, 1983Texas Instruments IncorporatedSemiconductor integrated circuit with vertical implanted polycrystalline silicon resistorUS4455737 *Mar 11, 1981Jun 26, 1984Rockwell International CorporationProcess for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting linesUS4560583 *Jun 29, 1984Dec 24, 1985International Business Machines CorporationDoping, calibration resistance, forming metal contactors with precise positioningUS4599789 *Jun 15, 1984Jul 15, 1986Harris CorporationProcess of making twin well VLSI CMOSUS4734382 *Feb 20, 1987Mar 29, 1988Fairchild Semiconductor CorporationBipolar complementary metal oxide semiconductorUS4759836 *Aug 12, 1987Jul 26, 1988Siliconix IncorporatedForming thin film resistor of chromium silicide or silicon carbide over insulating surface, forming an insulating film, doping thin film through insulating filmUS4871688 *May 2, 1988Oct 3, 1989Micron Technology, Inc.Sequence of etching polysilicon in semiconductor memory devicesDE3634850A1 *Oct 13, 1986Apr 23, 1987Mitsubishi Electric CorpMethod of producing a VLSI semiconductor circuit device of the standard wafer typeEP0226549A1 *Oct 9, 1986Jun 24, 1987SGS-THOMSON MICROELECTRONICS S.r.l.A monolithic integrated circuit, particularly of either the MOS or CMOS type, and method of manufacturing sameJPS589587A * Title not availableJPS589587B2 * Title not availableJPS624159A * Title not availableJPS5411687A * Title not availableJPS5794562A * Title not available* Cited by examinerNon-Patent CitationsReference1"Design and Characteristics of a Lightly Doped Drain (LDD) Device Fabricated with Self-Aligned Titanium Disilicide", Lai et al, IEEE Transactions on Electron Devices, vol. ED-33, No. 3, Mar. 1986.2"Titanium Disilicide Self-Aligned Source/Drain+Gate Technology", Lau et al, IEDM 82 1982.3 *Design and Characteristics of a Lightly Doped Drain (LDD) Device Fabricated with Self Aligned Titanium Disilicide , Lai et al, IEEE Transactions on Electron Devices, vol. ED 33, No. 3, Mar. 1986.4 *Titanium Disilicide Self Aligned Source/Drain Gate Technology , Lau et al, IEDM 82 1982.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5418179 *Aug 16, 1994May 23, 1995Yamaha CorporationProcess of fabricating complementary inverter circuit having multi-level interconnectionUS5436177 *Aug 12, 1993Jul 25, 1995Sgs-Thomson Microelectronics S.R.L.Process for forming implanted regions with lowered channeling risk on semiconductorsUS5534448 *Jul 28, 1994Jul 9, 1996Sgs-Thomson Microelectronics S.R.L.Process for realizing P-channel MOS transistors having a low threshold voltage in semiconductor integrated circuits for analog applicationsUS5585302 *Aug 10, 1995Dec 17, 1996Sony CorporationFormation of polysilicon resistors in the tungsten strapped source/drain/gate processUS5589701 *Jun 7, 1995Dec 31, 1996Sgs-Thomson Microelectronics S.R.1.Process for realizing P-channel MOS transistors having a low threshold voltage in semiconductor integrated circuits for analog applicationsUS5589702 *Apr 10, 1995Dec 31, 1996Micrel IncorporatedHigh value gate leakage resistorUS5612245 *May 3, 1995Mar 18, 1997Kabushiki Kaisha ToshibaMethod of manufacturing CMOS deviceUS5620922 *Mar 17, 1995Apr 15, 1997Seiko Instruments Inc.Method for fabricating CMOS device having low and high resistance portions and wire formed from a single gate polysiliconUS5767552 *Jun 5, 1997Jun 16, 1998Micron Technology, Inc.Structure for ESD protection in semiconductor chipsUS5879979 *Mar 29, 1995Mar 9, 1999Seiko Epson CorporationMethod of manufacturing a semiconductor device containing CMOS elementsUS5880917 *Aug 4, 1997Mar 9, 1999Micron Technology, Inc.Well resistor for ESD protection of CMOS circuitsUS6083784 *Feb 11, 1998Jul 4, 2000Yamaha CorporationSemiconductor device having MOS transistorUS6137664 *Jan 15, 1999Oct 24, 2000Micron Technology, Inc.Well resistor for ESD protection of CMOS circuitsUS6143613 *Jun 30, 1997Nov 7, 2000Vlsi Technology, Inc.Selective exclusion of silicide formation to make polysilicon resistorsUS6156592 *Aug 27, 1998Dec 5, 2000Seiko Epson CorporationMethod of manufacturing a semiconductor device containing CMOS elementsUS6225655 *Oct 20, 1997May 1, 2001Texas Instruments IncorporatedFerroelectric transistors using thin film semiconductor gate electrodesUS6255700Jan 14, 1997Jul 3, 2001Seiko Instruments Inc.CMOS semiconductor deviceUS6261915 *May 23, 1994Jul 17, 2001Texas Instruments IncorporatedProcess of making polysilicon resistorUS6362499Aug 24, 2000Mar 26, 2002Texas Instruments IncorporatedFerroelectric transistors using thin film semiconductor gate electrodesUS6507074Aug 30, 2001Jan 14, 2003Micron Technology, Inc.Structure for ESD protection in semiconductor chipsUS6586290Jun 15, 1998Jul 1, 2003Micron Technology, Inc.Structure for ESD protection in semiconductor chipsUS6654275 *Mar 15, 2001Nov 25, 2003Micron Technology, Inc.SRAM cell with horizontal merged devicesUS6727133 *Nov 21, 2002Apr 27, 2004Texas Instruments IncorporatedIntegrated circuit resistors in a high performance CMOS processUS6730554 *Nov 21, 2002May 4, 2004Texas Instruments IncorporatedMulti-layer silicide block processUS7020030Nov 17, 2003Mar 28, 2006Micron Technology, Inc.SRAM cell with horizontal merged devicesUS7233531Nov 18, 2005Jun 19, 2007Micro Technology, Inc.SRAM cell with horizontal merged devicesUS7414292 *Jun 16, 2005Aug 19, 2008Fujitsu LimitedSemiconductor device and its manufacturing methodUS7795100Jul 15, 2008Sep 14, 2010Fujitsu Semiconductor LimitedSemiconductor device and its manufacturing methodUS7939893Aug 11, 2010May 10, 2011Fujitsu Semiconductor LimitedSemiconductor device and its manufacturing methodUS8012821 *Feb 3, 2009Sep 6, 2011Samsung Electronics Co., Ltd.Semiconductor embedded resistor generationUS8158483Mar 30, 2011Apr 17, 2012Fujitsu Semiconductor LimitedSemiconductor device and its manufacturing methodEP1422744A2 *Nov 21, 2003May 26, 2004Texas Instruments Inc.Method of manufacturing integrated circuit resistors in a CMOS processWO1995019649A1 *Jan 5, 1995Jul 20, 1995Micrel IncHigh value gate leakage resistorWO1997007544A1 *Aug 6, 1996Feb 27, 1997Micron Technology IncCmos circuit esd protection using well resistorWO2002023612A2 *Jul 26, 2001Mar 21, 2002Advanced Micro Devices IncProcess for removing an oxide during the fabrication of a resistorWO2002084723A1 *Mar 21, 2002Oct 24, 2002Conexant Systems IncLow cost fabrication of high resistivity resistorsWO2002103786A1 *Jun 18, 2002Dec 27, 2002Hasegawa HisashiMethod for manufacturing semiconductor deviceWO2004112139A1 *Jun 10, 2003Dec 23, 2004Anezaki ToruSemiconductor device and its manufacturing method* Cited by examinerClassifications U.S. Classification438/210, 257/E21.004, 438/453, 257/E27.026, 438/227International ClassificationH01L27/02, H01L21/02, H01L27/06Cooperative ClassificationH01L27/0688, H01L28/20, H01L27/0288European ClassificationH01L28/20, H01L27/02B4F8, H01L27/06ELegal EventsDateCodeEventDescriptionSep 23, 2005FPAYFee paymentYear of fee payment: 12Sep 26, 2001FPAYFee paymentYear of fee payment: 8Sep 22, 1997FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google