Source: http://patents.com/us-7342288.html
Timestamp: 2019-10-18 09:22:45
Document Index: 654696874

Matched Legal Cases: ['art.\n3', 'arts 17', 'arts 91', 'arts 17', 'arts 91', 'arts 91', 'arts 91', 'arts 91', 'arts 91', 'arts 91', 'art 91', 'arts 91', 'art 101', 'art 101', 'art 101', 'arts 101', 'arts 111']

US Patent # 7,342,288. Thin film transistor, liquid crystal display apparatus, manufacturing method of thin film transistor, and manufacturing method of liquid crystal display apparatus - Patents.com
United States Patent 7,342,288
Fujii , et al. March 11, 2008
Thin film transistor, liquid crystal display apparatus, manufacturing method of thin film transistor, and manufacturing method of liquid crystal display apparatus
Inventors: Fujii; Akiyoshi (Nara, JP), Nakabayashi; Takaya (Iga, JP)
Appl. No.: 10/524,465
PCT Filed: July 23, 2003
PCT No.: PCT/JP03/09361
PCT Pub. No.: WO2004/023561
Aug 30, 2002 [JP] 2002-255568
Current U.S. Class: 257/401 ; 257/E21.414; 257/E29.117; 257/E29.12
Current International Class: H01L 29/417 (20060101)
Field of Search: 257/E29.039,E29.112,E29.116,E29.117 438/674
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2003/0003231 January 2003 Kiguchi et al.
2003/0008217 January 2003 Kobayashi
2003/0059686 March 2003 Kobayashi
2003/0059984 March 2003 Sirringhaus et al.
2003/0117362 June 2003 An
2005/0071969 April 2005 Sirringhaus et al.
0989778 Mar., 2000 EP
02-275672 Nov., 1990 JP
05-283695 Oct., 1993 JP
11-340129 Dec., 1999 JP
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WO-01/20691 Mar., 2001 WO
WO-01/47045 Jun., 2001 WO
Kawase et al. "Invited Paper: All-Polymer Thin Film Transistors Fabricated by High-Resolution Ink-Jet Printing," SID 01 DIGEST Published on 2001, pp. 40-43. cited by other.
1. A thin film transistor comprising (i) a semiconductor layer, which faces a gate electrode via a gate insulation layer, (ii) a source electrode and a drain electrode, which are electrically connected with the semiconductor layer, and (iii) a channel section between the source electrode and the drain electrode, wherein: the source electrode and the drain electrode are formed by applying a droplet of an electrode raw material, and have a branch section at branching-off parts thereof located off a forming area of the semiconductor layer, the branch section including a plurality of branch electrodes, at least part of which are in a forming area of the semiconductor layer, the branch electrodes of the source electrode and the branch electrodes of the drain electrode being alternately arrayed, and the branching-off parts are located at drop-on positions on which the droplet of the electrode raw material forming the source electrode and the drain electrode is to be dropped, and are positioned removed from the channel section, the position of the branching-off parts removed from the channel position is based on allowance of the drop-on positions.
2. The thin film transistor as set forth in claim 1, wherein: each branch electrode has a parallel part being parallel to each other within the forming area of the semiconductor layer, each branch electrode being linear between the parallel part and the branching-off part.
3. The thin film transistor as set forth in claim 1, wherein: at least one of the source electrode and the drain electrode has a part that gets gradually wider toward the forming area of the semiconductor layer.
4. The thin film transistor as set forth in claim 3, wherein: the source electrode and the drain electrode have ends respectively that are closer to the semiconductor layer; and the part that gets gradually wider is located between one of the branching-off parts and one of the ends.
5. The thin film transistor as set forth in claim 1, wherein: the channel section has a width not longer than a length of the branch electrode sections.
6. The thin film transistor as set forth in claim 1, wherein: the branch electrodes of the source electrode, or the branch electrodes of the drain electrode are so arrayed that a gap between each adjacent pair of the branch electrodes gets wider as the branch electrodes are extended toward the channel section from the branching-off parts.
7. The thin film transistor as set forth in claim 1, wherein: the semiconductor layer has a substantially circular pattern whose diameter is larger than a width part of the gate electrode located on the channel section.
8. The thin film transistor as set forth in claim 1, wherein: the semiconductor layer has a substantially circular pattern whose diameter is larger than a width part of the gate electrode located on the channel section; and an end of each branch electrode is within the width part of the gate electrode, but does not go beyond the width part of the gate electrode.
9. A thin film transistor transistor comprising (i) a semiconductor layer, which faces a gate electrode via a gate insulation layer, (ii) a source electrode and a drain electrode, which are electrically connected with the semiconductor layer, and (iii) a channel section between the source electrode and the drain electrode, wherein: the source electrode and the drain electrode have a branch section at branching-off parts thereof located off a forming area of the seniiconductor layer, the branch section including a plurality of branch electrodes, at least part of which are in a forming area of the semiconductor layer, the branch electrodes of the source electrode and the branch electrodes of the drain electrode being alternately arrayed, and the branching-off parts are located at drop-on positions on which the droplet of the electrode raw material forming the source electrode and the drain electrode is to be dropped, and are positioned removed from the channel section, the position of the branching-off parts removed from the channel position is based on allowance of the drop-on positions.
10. A liquid crystal display apparatus comprising a thin film transistor, wherein: the thin film transistor includes (i) a semiconductor layer, which faces a gate electrode via a gate insulation layer, (ii) a source electrode and a drain electrode, which are electrically connected with the semiconductor layer, and (iii) a channel section between the source electrode and the drain electrode, the source electrode and the drain electrode being formed by applying a droplet of an electrode raw material, and having a branch section at branching-off parts thereof located off a forming area of the semiconductor layer, the branch section including a plurality of branch electrodes, at least part of which are in a forming area of the semiconductor layer, the branch electrodes of the source electrode and the branch electrodes of the drain electrode being alternately arrayed, and the branching-off parts are located at drop-on positions on which the droplet of the electrode raw material forming the source electrode and the drain electrode is to be dropped, and are positioned removed from the channel section, the position of the branching-off parts removed from the channel position is based on allowance of the drop-on positions.
11. A thin film transistor comprising (i) a semiconductor layer, which faces a gate electrode via a gate insulation layer, (ii) a source electrode and a drain electrode, which are electrically connected with the semiconductor layer, and (iii) a channel section between the source electrode and the drain electrode, wherein: the source electrode and the drain electrode are formed by applying a droplet of an electrode raw material, and have a branch section at branching-off parts thereof located off a forming area of the semiconductor layer, the branch section including a plurality of branch electrodes, at least part of which are in a fonning area of the semiconductor layer, the branch electrodes of the source electrode and the branch electrodes of the drain electrode being alternately arrayed, and at least one of the source electrode and the drain electrode has a part that gets gradually wider toward the forming area of the semiconductor layer.
12. A thin film transistor comprising (i) a semiconductor layer, which faces a gate electrode via a gate insulation layer, (ii) a source electrode and a drain electrode, which are electrically connected with the semiconductor layer, and (iii) a channel section between the source electrode and the drain electrode, wherein: the source electrode and the drain electrode are formed by applying a droplet of an electrode raw material, and have a branch section at branching-off parts thereof located off a forming area of the semiconductor layer, the branch section including a plurality of branch electrodes, at least part of which are in a forming area of the semiconductor layer, the branch electrodes of the source electrode and the branch electrodes of the drain electrode being alternately arrayed, the branch electrodes of the source electrode, or the branch electrodes of the drain electrode are so arrayed that a gap between each adjacent pair of the branch electrodes gets wider as the branch electrodes are extended toward the channel section from the branching-off parts, and the semiconductor layer has a substantially circular pattern whose diameter is larger than a width part of the gate electrode located on the channel section.
13. A thin film transistor comprising (i) a semiconductor layer, which faces a gate electrode via a gate insulation layer, (ii) a source electrode and a drain electrode, which are electrically connected with the semiconductor layer, and (iii) a channel section between the source electrode and the drain electrode, wherein: the source electrode and the drain electrode are formed by applying a droplet of an electrode raw material, and have a branch section at branching-off parts thereof located off a forming area of the semiconductor layer, the branch section including a plurality of branch electrodes, at least part of which are in a forming area of the semiconductor layer, the branch electrodes of the source electrode and the branch electrodes of the drain electrode being alternately arrayed, the semiconductor layer has a substantially circular pattern whose diameter is larger than a width part of the gate electrode located on the channel section, and an end of each branch electrode is within the width part of the gate electrode, but does not go beyond the width part of the gate electrode.
Recently suggested is an art of forming wires by an ink jet method, not by using photolithography. In this art, for example, as disclosed in Japanese Publication of Unexamined Patent Application, Tokukaihei, No. 11-204529 (published Jul. 30, 1999), a substrate has an affinity area having affinity for a raw material of wires, and a non-affinity area having no affinity for the raw material of the wires, and the wires are formed by applying (adhering) droplets of the raw material of the wires onto the affinity area on the substrate by the ink jet method (hereinafter, the term "applying" includes meaning of "dropping" and "jetting").
Moreover, disclosed in SID 01 Digest, pages 40 to 43, 6.1: Invited Paper: "All-Polymer Thin Film Transistors Fabricated by High-Resolution Ink-jet Printing" (written by Takeo KAWASE, et al.) is an art in which a TFT is formed by using only an organic raw material by using an ink jet method.
FIG. 2(a) is a plan view schematically illustrating an arrangement of one pixel in the TFT array substrate in a liquid crystal display apparatus of the embodiment of the present invention, while FIG. 2(b) is a cross sectional view taken on line A-A of FIG. 2(a).
FIG. 4 is a flow chart illustrating manufacturing steps of the TFT array substrate shown in FIGS. 2(a) and 2(b).
FIG. 5(a) is a plan view of the TFT array substrate, the plan view explaining a gate preprocessing step shown in FIG. 3. FIG. 5(b) is a plan view of the TFT array substrate, the plan view explaining a droplet-applying gate wire formation step shown in FIG. 3. Further, FIG. 5(c) is a cross sectional view taken on line B-B of FIG. 5(b).
FIGS. 6(a) to 6(c) are cross sectional views of part corresponding to a cross section taken on line B-B of FIG. 5(b). FIG. 6(a) illustrates a gate insulating layer formation/semiconductor layer formation step shown in FIG. 4. FIG. 6(b) illustrates a state after a photolithography step is completed after a step of forming a gate insulation layer and a semiconductor layer in the semiconductor layer formation step shown in FIG. 4. FIG. 6(c) illustrates a step of etching an a-Si film formation layer and an n+ film formation layer in the semiconductor layer formation step. FIG. 6(d) is a cross sectional view taken on line C-C of FIG. 6(e), the FIG. 6(d) illustrating a step of removing a resist in the semiconductor layer formation step. FIG. 6(e) is a plan view of the TFT array substrate that has been subjected to the semiconductor layer formation step.
FIGS. 9(a) to 9(c) are cross sectional views of part corresponding to a cross section taken on line B-B of FIG. 5(b). FIG. 9(a) illustrates a gate insulation layer formation/semiconductor layer formation step, shown in FIG. 4, for a case where the TFT array substrate having the TFT section shown in FIG. 8. FIG. 9(b) illustrates a state after a photolithography step is completed after a step of forming a gate insulation layer and a semiconductor layer in the semiconductor layer formation step shown in FIG. 4. FIG. 9(c) illustrates a step of etching an a-Si layer and an n+ layer in the semiconductor layer formation step. FIG. 9(d) is a cross sectional view taken on line D-D of FIG. 9(e), the FIG. 9(d) illustrating a step of removing a resist in the semiconductor layer formation step. FIG. 9(e) is a plan view of the TFT array substrate that has been subjected to the semiconductor layer formation step.
FIG. 10(a) is a plan view illustrating the TFT section of the TFT array substrate of still another embodiment of the present invention. FIG. 10(b) is a cross sectional view illustrating part corresponding a cross section taken on line E-E of FIG. 10(a), FIG. 10(b) showing the part before a source electrode and a drain electrode are formed.
FIGS. 12(a) to 12(d) are explanation views illustrating a step of forming a wetting pattern in a dewetting area, by wetting process of the substrate by using a photocatalyst.
FIGS. 14(a) to 14(d) are schematic cross sectional views illustrating steps in production process of the channel section of the TFT section. FIGS. 14(e) to 14(g) are schematic cross sectional views, taken on line E-E' of FIG. 13, illustrating steps in production process of the channel section for a case where the splash droplet of the electrode raw material remains on the channel section.
FIG. 16(a) is a plan view illustrating an arrangement in which a leak current hardly occurs between a source electrode and a drain electrode, in case a shape of the semiconductor layer is protruded out of a gate electrode area of the TFT section. FIG. 16(b) is a cross sectional view taken on line G-G' of FIG. 16(a).
FIG. 17(a) is a plan view illustrating an arrangement in which a leak current easily occurs between a source electrode and a drain electrode, in case a shape of the semiconductor layer is protruded out of the gate electrode area of the TFT section. FIG. 17(b) is a cross sectional view taken on line H-H' of FIG. 17(a).
A liquid crystal display apparatus of the embodiment of the present invention is provided with pixels shown in FIG. 2(a). Note that FIG. 2(a) is a plan view schematically illustrating an arrangement of one pixel in a TFT array substrate of a liquid crystal display apparatus. Moreover, a cross sectional view taken on line A-A of FIG. 2(a) is illustrated in FIG. 2(b).
As shown in FIGS. 2(a) and 2(b), in a TFT array substrate 11, gate electrodes 13 (gate wires) and source electrodes 17 (source wires) are provided in matrix on a glass substrate 12. Respectively between adjacent gate electrodes 13 (gate wires), storage capacitance electrodes 14 (storage capacitance wire) are provided.
Between a position of TFT section 22 and a position of a storage capacitance section 23, the TFT array substrate 11 is, as shown in FIG. 2(b), provided with one gate electrode 13 and one storage capacitance electrode 14, on the glass substrate 12.
In the gate preprocessing step 41, preprocess for the droplet-applying gate wire formation step 42 is carried out. In the droplet-applying gate wire formation step 42 following the gate preprocessing step 41, the gate wire is formed by dropping a liquid wire raw material by using the pattern formation apparatus. For this, in the gate preprocessing step 41, performed is process to prepare for attaining more appropriate application of the liquid wire raw material when the liquid wire raw material is jetted (dropped) onto a gate wire formation area 61 (shown in FIG. 5(a)) by the pattern formation apparatus. Note that FIG. 5(a) is a plan view of the glass substrate 12 provided in the TFT array substrate 11.
Here, the photocatalysis using titanium oxide is carried out as follows. A mixture (dewetting raw material) of isopropyl alcohol and ZONYL FSN (product name: made by E. I. du Pont de Nemours and Co.), which is a non-ion type fluorochemical surfactant, is applied on the glass substrate 12 of the TFT array substrate 11. Moreover, onto the mask for the pattern of the gate wire, a mixture of ethanol and a raw material (titanium dioxide particulate dispersion raw material) in which titanium dioxide particulates are dispersed is applied by spin-coating, so as to form a photocatalysis layer. After that the glass substrate thus prepared is baked at a temperature of 150.degree. C. Then, with the mask on, the glass substrate 12 is exposed to UV light. The exposure is carried out for 2 minutes by using ultraviolet light of 356 nm in an intensity of 70 mW/cm2.
Referring to FIGS. 12(a) to 12(d), more detailed explanation is provided below. As shown in FIG. 12(a), by using the spin coat method and the like, the dewetting raw material is applied on the glass substrate 12. By drying the glass substrate 12, a wet layer 2 is formed. Note that silane coupling agent may be used as the dewetting raw material.
Next, as shown in FIG. 12(b), UV exposure is carried out under the above mentioned exposure condition, via a photo mask 3 in which a mask pattern 4 composed of chromium or the like and a photocatalyst layer 5 composed of a titanium oxide or the like are formed in advance.
As a result, as shown in FIGS. 12(c) and 12(d), wetting property of only part that is subjected to the UV exposure is improved. Hereby, a wet pattern 6 corresponding to the gate line formation area 61 is formed.
The droplet-applying gate wire formation step 42 is illustrated in FIGS. 5(b) and 5(c). FIG. 5(b) is a plan view of the glass substrate 12 after the storage capacitance electrode 14 is formed between the gate electrode 13 and the gate electrode 13 adjacent thereto. FIG. 5(c) is a cross sectional view taken on line B-B of FIG. 5(b).
Note that as shown in FIG. 5(b), part of a certain gate electrode 13 is protruded toward the storage capacitance electrode 14 next to the certain gate electrode 13. The part will finally become TFT-section gate electrode 66, as shown in FIGS. 1 and 2(a). However, the TFT section gate electrode 66 of the upper one of the gate electrodes 13 shown in FIG. 5 is omitted for easy explanation.
In the droplet-applying gate wire formation step 42, by using the pattern formation apparatus, the wire raw material is applied (a droplet thereof is applied) on the gate wire formation area 61 on the glass substrate 12, as shown in FIGS. 5(b) and 5(c). As the wire raw material, used is a raw material in which Ag particulates coated with an organic film as a surface coating layer are dispersed in an organic solvent. It is set that a width of the wires is substantially 50 .mu.m and an amount of the wire raw material to be jetted from the ink jet head 33 is 80 pl.
The wire raw material is jetted from the ink jet head 33 onto a wetted surface (a surface subjected to the wetting/dewetting process), and then the wire raw material flows and spreads over and within the gate wire formation area 61. Therefore, a jetting interval to jet the wire raw material onto the gate wire formation area 61 is set to 500 .mu.m approximately. After the application, the glass substrate 12 is baked for one hour at 350.degree. C., thereby forming the gate electrode 13 and the supplement capacitance electrode 14.
The temperature for baking is set at 350.degree. C. because a process temperature of about 300.degree. C. is applied in the next semiconductor layer formation step 44. Therefore, the baking temperature is not limited to the temperature. For example, in case where an organic semiconductor is to be formed, an annealing temperature may be set at a temperature of 100.degree. C. to 200.degree. C. In this case, the baking temperature may be set at a lower temperature of 200.degree. C. to 250.degree. C.
Moreover, as a wire raw material, it is possible to use particulates or a paste raw material in an organic solvent. the particulates or paste raw material may be made of solely a metal or an alloy such as Ag--Pd, Ag--Au, Ag--Cu, Cu, Cu--Ni, or the like, besides Ag. Further, as to the wire raw material, it is possible to obtain a desired resistance value and a surface condition by controlling a dissociation temperature of an organic raw material contained in an organic solvent or the surface coating layer protecting the particulates, in accordance with a baking temperature necessary. Note that the dissociation temperature is a temperature at which the surface coating layer and the organic solvent is evaporated.
The gate insulation layer formation/semiconductor layer formation step 43 is illustrated in FIG. 6(a).
In the gate insulation layer formation/semiconductor layer formation step 43, the gate insulation layer 15, an a-Si film formation layer 64 and an n+ film formation layer 65 are formed sequentially and continuously by CVD on the glass substrate 12 that has been subjected to the droplet-applying gate wire formation step 42. The a-Si film formation layer 64 is formed by a CVD (Chemical Vapor Form) method. The gate insulation layer 15, the a-Si film formation layer 64, and the n+ film formation layer 65 are respectively 0.3 .mu.m, 0.15 .mu.m, and 0.05 .mu.m in thickness, and are formed (deposited) without spoiling a vacuum condition, (that is, with vacuum condition maintained). The layer formation (deposition) is carried out at a temperature of 300.degree. C.
The semiconductor layer formation step 44 is illustrated in FIGS. 6(b) to 6(e). FIG. 6(e) is a plan view illustrating the glass substrate 12 that has been subjected to the semiconductor layer formation step 44. FIG. 6(d) is a perspective view taken on line C-C of FIG. 6(e). FIGS. 6(b) to 6(c) are vertical cross sectional views taken on the same wire as FIG. 6(d), illustrating each step in the semiconductor layer formation step 44.
In the semiconductor layer formation step 44, the resist raw material is applied onto the n+ film formation layer 65, and then the resist raw material is processed via a photolithography step and an etching step, thereby forming a resist layer 67 having a shape of the semiconductor layer 16, as shown in FIG. 6(b).
Next, dry-etching is performed on the n+ film formation layer 65 and the a-Si film formation layer 64 by using a gas (for example SF6+HCl), as shown in FIG. 6(c), thereby forming an n+ film 69 and an a-Si layer 68. Thereafter, the glass substrate 12 is washed with an organic solvent, thereby peeling off and removing the resist layer 67, as shown in FIG. 5(d).
The wire guide is made of a photoresist raw material. Specifically, a photoresist is applied onto the glass substrate 12 that has been subjected to the semiconductor formation step 44. Then, the glass substrate is prebaked. After that, the glass substrate is exposed using a photomask so as to be developed. Next, the wire guide is formed by performing postbaking. The wire guide thus formed has a width of about 10 .mu.m, here. A width of a groove formed by the wire guide (a width of the wire formation area) is about 10 .mu.m.
In the droplet-applying source/drain wire formation step 46, the wire raw material is applied (a droplet thereof is applied), by the pattern formation apparatus, onto the source/drain formation area thus formed by using the wire guide. Hereby, the source electrode 17 and the drain electrode 18 are formed. Here, the amount of the wire raw material to be jetted out from the ink jet head 33 is set at 2 pl. Moreover, Ag particulates are used as the wire raw material. Thickness of the layer to be formed is set at 0.3 .mu.m. Moreover, the baking temperature is set at 200.degree. C. After the baking, the wire guide is removed by using an organic solvent.
Note that the wire raw material may be the same as the one used for the gate electrodes 13. However, because the a-Si layer is formed at a temperature of about 300.degree. C., it is necessary that the baking be carried out at a temperature not more than 300.degree. C.
In the protective layer formation step 48 and the protective layer processing step 49, firstly a SiO.sub.2 layer, which is to be the protective layer 19 (see FIG. 2(b)), is formed by CVD on the glass substrate 12 that has been processed up to formation of the source and drain electrodes. Next, on the SiO.sub.2 layer an acrylic resin, which is to be the photosensitive acrylic resin layer 20, is applied so as to form a pixel electrode formation pattern and electrode processing pattern on the resist layer.
Specifically, the protective layer 19 and the photosensitive acryl resin layer 20 are etched so as to remove the whole resist layer from that part in which an end surface will be formed within the contact hole 24, and so as to reduce the thickness of the resist layer in that part in which the pixel electrode 21 is to be formed. As a result of the reduction of the thickness of the resist layer in this part, the thickness of the resist layer is rendered to be half of the thickness of the thus applied resist layer, so that part surrounding the pixel electrode formation pattern in the photosensitive acryl resin layer 20 will become a guide shown in FIG. 2(b).
On the pixel electrode forming pattern of the photosensitive acryl resin layer 20, an ITO particulate raw material, which is to be a pixel electrode raw material, is applied by using the pattern formation apparatus. Thereafter, the thus processed glass substrate 12 is baked at a temperature of 200.degree. C., thereby forming the pixel electrode 21. In this way, the TFT array substrate 11 is obtained.
The source electrode 17 and the drain electrode 18 are so formed as to cross the TFT-section gate electrode s 66, as shown in FIG. 1 and FIG. 2(a). In the arrangement shown in FIG. 1, the source electrode 17 and the drain electrode 18 are branched into a plurality of branches (branch electrodes) in the TFT section 22. In other words, the source electrode 17 and the drain electrode 18 respectively have a branch section (17a or 18a) having the plurality of branch electrodes. Specifically, the source electrode 17 is provided with the branch electrode section 17a, whereas the drain electrode 18 is provided with the branch electrode section 18b. The branch electrodes of the branch electrode section 17a of the source electrode 17 and the branch electrodes of the branch electrode section 18b of the drain electrode 18 are arrayed alternately. Gaps between adjacent branch electrodes of branch electrode section 17a and 18b are the channel section 72. The branch electrodes of the branch electrode sections 17a and 18a have a width of 10 .mu.m, for example. The channel section 72 has a width (a distance between the branch electrode sections 17a and 18b) of 10 .mu.m, for example.
Here, the wires usually have a width of several .mu.m. In order to realize droplets having a diameter of several .mu.m, it is necessary for the pattern formation apparatus to jet an amount much smaller than 1 pl. However, it is difficult to realize such a diameter of droplets. Moreover, even if such diameter of droplets is realized, it is difficult to drop the minus droplets onto 2 to 3 millions of TFT sections 22 in the liquid panel, considering time required and a life of the ink jet head 33. Therefore, a droplet having a diameter larger than several .mu.m is dropped (applied).
In this case, if the droplet is directly applied onto the electrodes (branch electrodes of the branch electrode sections 17a and 18a) of the channel section 72, the droplets might splash, so that the wire raw material will adhere onto the channel section 72, or the wire raw material will remain.
Production of the channel section 72 is described below, so as to explain the cause of the leakage. FIG. 14(a), which is a cross sectional view taken on line E-E' of FIG. 13, illustrates a condition before the source and drain electrodes are formed. Here, a guide 200 has just formed after a semiconductor layer 16 composed of the a-Si layer 68 and n+ layer 69 is formed. The guide 200 is for separating the source electrode 17 and the drain electrode 18 on the channel section 72.
FIG. 14(b) illustrates a next condition after the raw material of the source electrode 17 and the drain electrode 18 is applied and baking is carried out. FIG. 14(c) shows a following condition after the guide 200 is removed by using an organic solvent, or by ashing. In this condition, the n+ layer 69 still exists on the semiconductor layer 16.If the n+ layer 69 remains as such, application of a voltage on the source electrode 17 and the drain electrode 18 easily causes a current flow due to a carrier that the n+ layer has.
FIG. 14(d) illustrates a condition after the n+ layer 69 is removed. In this way, the production of the channel section 72 is completed.
For example, FIG. 13 shows a case where the electrode raw material remains on part of the channel section 72 on a side associated with the source electrode 17. FIG. 14(e) illustrates a cross section taken on line E-E'. If a residual (Q) of the electrode raw material remains on the guide 200 as shown in FIG. 14(e), there is a possibility that the residual (Q) acts as a mask in the step of removing the guide 200, as shown in FIG. 14(f), so that part of the guide 200 remains. This may occur similarly in case of the process using the organic solvent, or in case of the peeling-off by ashing.
As shown in FIG. 14(f), if part of the guide 200 remains on the channel section 72, the n+ layer 69 cannot be completely removed in an area in which the residual (Q) exists (part of the n+ layer 69 in the area in which the residual (Q) exists is not removed sufficiently), in the next step of removing the n+ layer 69, as shown in FIG. 14(g). Similarly, in the step of converting the n+ layer 69 into a nonconductor by ashing or laser oxidation, the part of the part of the n+ layer 69 in the area in which the residual (Q) exists is not converted into a nonconductor sufficiently.
Therefore, in case where the source and drain electrodes 17 and 18 are formed in the TFT section 22, the droplets of the wire raw material are dropped in part of the area in which the source electrode 17 and the drain electrode 18 are formed, but avoiding part in which the channel section 72 (semiconductor layer 16) are formed. Specifically, in case where the source electrode 17 and the drain electrode 18 have the branch electrode sections 17a and 18a as described above, positions respectively corresponding to branching-off parts 17b and 18b are drop-on positions 81 (on which the droplets are dropped).
Moreover the drop-on positions 81 are set considering how accurately the pattern formation apparatus can apply (drop) the droplet (application accuracy). Within the drop-on positions 81, the branching-off positions 17b and 18b are positioned respectively.
The application accuracy of the pattern formation apparatus, that is, a shift length from the drop-on position that is targeted, to a position to which the droplet is actually applied, depends on (i) production error of the ink jet head 33, (ii) an amount of droplets adhered on a head nozzle, (iii) evenness the droplets in amount, (iv) accuracy of the driving and positioning of the ink jet head 33 repeated by the X-direction driving section 34 and the Y-direction driving section 35, (v) heat expansion of the ink jet head 33, (vi) speed of the movement of the ink jet head 33 in jetting, and (vii) the like factors. Moreover, the application (dropping) of the droplets by the pattern formation apparatus is carried out with, for example, an accuracy of .+-.3 .mu.m to .+-.5 .mu.m in case where one nozzle jets out the droplets while the nozzle is not moved. In case of a multi nozzle, the application of the droplets by the pattern formation apparatus is carried out with, for example, an accuracy of .+-.10 .mu.m to .+-.15 .mu.m while the multi nozzle is not moved.
In the present embodiment, an amount of one droplet is set to 4 pl, considering that a plurality of wires are formed from one droplet, and that the electrode having a width of 10 .mu.m is formed from a droplet having a diameter larger than the width of the electrodes, as well as how long a head life and tact time of the ink jet head 33 are. When one droplet has this amount, the diameter of the droplet in dropping (when the droplet hits the surface of the glass substrate 12) is about 20 .mu.m. Therefore, it is preferable that a ratio between (i) the width of the branch electrode sections 17a and 18a and (ii) the diameter of the droplet in dropping is substantially 1:2.
Moreover, taking those conditions into consideration, the drop-on positions 81 are located in positions respectively distanced by 30 .mu.m from edges of the semiconductor layer 16 (a-Si layer 68), as shown in FIG. 7. Note that in FIG. 7, the reference numeral 82 denotes a drop-on center of the drop-on positions 81, and the reference numeral 83 denotes an drop-on center allowance range, which is within 15 .mu.m from the drop-on center 82. The reference numeral 84 shows a drop-on position (with a diameter of droplet of 20 .mu.m) for a case where the droplet is applied in a position distanced (shifted) by 15 .mu.m from the drop-on position 81 (the drop-on center 82) toward the channel section 72.
In the present embodiment, a TFT section 22 of a TFT array substrate 11 (see FIG. 2(a)) is arranged as shown in FIG. 8. The TFT section 22 is provided with a source electrode 91 and a drain electrode 92, instead of the source electrode 17 and the drain electrode 18 described above. Moreover, a semiconductor layer 93, which replaces the semiconductor layer 16, has a substantially circular shape, that resembles the shape of the droplet applied (dropped on).
The source electrode 91 and the drain electrode 92 are respectively provided with branch electrode sections 91a and 92a, as in the source electrode 17 and the drain electrode 18. The branch electrode sections 91a and 92a are branched, for example, into two branches (having two branch electrodes), respectively at branching-off parts 91b and 92b. Note that the number of branches (branch electrodes) may be set arbitrarily.
As explained so far, in the arrangement shown in FIG. 1, the branch electrodes of the branch electrode section 17a of the source electrode 17 and the branch electrodes of the branch electrode section 18a of the drain electrode 18 are firstly extended, from the branching-off parts 17b and 18b, in parallel to directions along which the TFT-section gate electrode 66 is protruded from the gate electrode 13 (respectively in opposite two directions). Then, the branch electrodes of the branch electrode sections 17a and 18a are extended, above the TFT-section gate electrode 66, in direction perpendicular to the directions along which the TFT-section gate electrode 66 is protruded.
On the other hand, in an arrangement shown in FIG. 8, the branch electrodes of the branch electrode section 91a of the source electrode 91 and the branch electrodes of the branch electrode section 92a of the drain electrode 92 are extended in oblique directions (two directions) so as to widen a gap between the branch electrodes of the branch electrode section 91a, and to widen a gap between the branch electrodes of the branch electrode section 92a. Then, the branch electrodes of the branch electrode sections 91a and 92a are extended, above the TFT-section gate electrode 66, in direction perpendicular to the directions along which the TFT-section gate electrode 66 is protruded.
In other words, the branch electrode sections 91a and 92a have parallel parts being parallel to each other and on the semiconductor layer 93, the branch electrodes of the branch electrode sections 91a and 92a being linear between the parallel parts and the branching-off part (91b or 92b).
This manufacturing method is identical to the method described in the first embodiment, from a gate preprocessing step 41 to a gate insulation layer formation/semiconductor layer formation step 43 (see FIG. 9(a)), and from a source/drain wire preprocessing step 45 after a semiconductor layer formation step 44, to a pixel electrode formation step 50. The semiconductor layer formation step 44 is carried out as follows.
The semiconductor layer formation step 44 is illustrated in FIGS. 9(b) to 9(e). FIG. 9(e) is a plan view illustrating a glass substrate 12 that has been subjected to the semiconductor layer formation step 44. FIG. 9(d) is a cross sectional view taken on line D-D of FIG. 9(e), and FIGS. 9(b) and 9(c) are vertical cross sectional views taken on line D-D of FIG. 9(e), as in FIG. 9(d).
In the semiconductor layer formation step 44, as shown in FIG. 9(b), by a pattern formation apparatus, heat-curable resin is applied as a resist raw material onto an n+ film formation layer 65 located on the TFT-section gate electrode (branch electrode section) 66 branched off from the gate electrode 13, so as to adhere the heat-curable resin thereon. A resist layer 94 formed in this way is a pattern to be used for the process. For example, one droplet of the resist raw material of 10 pl is jetted out. Hereby, formed at a predetermined position on the TFT-section gate electrode 66 is a pattern having a circular shape having a diameter of about 30 .mu.m. The thus prepared substrate is baked at a temperature of 150.degree. C. As the heat-curable resin for the resist layer 94, used is resin in resist TEF series made by Tokyo Ohka Kogyo Co. Ltd. The resin in resist TEF series is used after adjusted in viscosity so as to be suitable for ink jetting.
Next, by using a gas (for example, SF6+HCl), as shown in FIG. 9(c), an n+ film formation layer 65 and an a-Si film formation layer 64 are dry-etched so as to form an n+ layer (film) 69 and an a-Si layer (film) 68. Thereafter, the glass substrate 12 is washed with an organic solution, so as to peel off and remove the resist layer 94 as shown in FIG. 9(d).
Note that, in case the semiconductor layer 93 has such a shape that the semiconductor layer 93 is out of the area of the TFT-section gate electrode 66, as described above, it is necessary that no end of the branch electrodes of the branch electrode sections 91a and 92a be out of an area (forming area) of the TFT-section gate electrode 66 (an area within which the TFT-section gate electrode 66 exists) (in other words, the end be within the area of the TFT gate electrode 66).
In FIG. 8, the semiconductor layer 93 has such a shape that is extended beyond edges of the TFT-section gate electrode 66, unlike the TFT-section gate electrode 66 and the semiconductor layer 16 shown in FIG. 7. Because of this, it is preferable that the ends of the branch electrode sections 91a and 92a (ends of the branch electrodes of the branch electrode sections 91a and 92a) are inside of edge surface lines of the TFT-section gate electrode 66, that is, on the TFT-section gate electrode 66. This is because the leak current is increased and the TFT characteristics are deteriorated, if the source and drain electrodes 17 and 18 are extended out of the TFT-section gate electrode 66.
In the following, mechanism of the occurrence of the leak current shown in the droplet-applying source/drain wire formation step 46 is described, referring to FIGS. 16(a), 16(b), 17(a), and 17(b).
FIG. 16(a) is a plan view of the TFT section in case where the source electrode 17 is inside of the line of the edge of the TFT-section gate electrode 66, and on the TFT-section gate electrode 66. FIG. 16(b) is a cross sectional view taken on line G-G' line of FIG. 16(a). On the other hand, FIG. 17(a) is a plan view of the TFT section in case where the source electrode 17 is extended beyond the line of the edge of the TFT-section gate electrode 66, that is, extended out of the TFT-section gate electrode 66. FIG. 17(b) is a cross sectional view taken on line H-H' line of FIG. 17(a).
Note that, FIGS. 16(a) and 17(a) illustrate cases where a negative potential is applied on the TFT-section gate electrode 66. As shown in FIGS. 16(b) and 17(b), the TFT-section gate electrode 66 faces the a-Si layer 68, sandwiching the gate insulating layer 15 therebetween. Here, the n+ layer 69 is a layer that introduces a carrier into the a-Si layer 68, and a layer that is doped with phosphorus (P) or the like and has excess electrons.
In the TFT in FIGS. 16(a), 16(b), 17(a), and 17(b), a leak current between the source and drain electrodes 17 and 18 was measured when for example a voltage of -4V was applied on the TFT-section gate electrode 66. As a result, the leak current was about 1 pA in the case where the source and drain electrodes 17 and 18 were on the TFT-section electrode 66. On the other hand, in the case where the source and drain electrodes 17 and 18 were extended out of the TFT-section gate electrode 66, the leak current was increased to 20 pA to 30 pA.
On the other hand, in case of FIG. 17(a), even if the TFT-section gate electrode 66 has a negative potential, the electrons do not need pass through the part (P) of the TFT-section gate electrode 66, in which a negative potential is applied, but can move along an outer circumference of the a-Si layer 68, because the source and drain electrodes 17 and 18 are extended beyond an outer edge of the TFT-section gate electrode 66. It is considered that the leak current is easily flowed because of this.
As understood from the above explanation, it is preferable that the source and drain electrodes 17 and 18 are inside of the outer edge of the TFT-section gate electrode 66 (that is, on the TFT-section gate electrode 66). Next, explained is a case where a positive potential is applied on the TFT-gate electrode 66. In case where the TFT-section gate electrode 66 has a positive potential, the electrons of the n+ layer 69 is pulled by the potential of the TFT-section gate electrode 66, and the carriers exist in the channel section. Therefore, the current is easily flowed between the source and drain electrodes 17 and 18, so that the TFT is in an ON state. For example, when a voltage of 10V was applied across the TFT-section gate electrode 66, a current of about 1 .mu.A flowed between the source and drain electrodes 17 and 18. Here, an applied voltage between the source and drain electrodes was 10V. When the TFT is ON, the electrons try to flow in a shortest distance between the source and drain electrodes 17 and 18. Therefore, the extending of the source and drain electrodes 17 and 18 beyond the outer edge of the TFT section electrode 66 does not affect.
As described above, the branch electrode sections 91a and 92a are so formed that parts of the branch electrode sections 91a and 92a are extended in oblique directions with respect to the directions along which the TFT-section gate electrode 66 is protruded, the parts associating with the branching-off parts 91b and 92b, respectively. (In other words, the part are respectively between (i) the branching-off parts 91b and 92b and parallel parts of the branch electrode sections 91a and 92a.) The branch electrode sections 91a and 92a are so formed mainly because of the following reason.
The semiconductor layer 93 thus formed in the similar shape to the shape of the applied droplet may become larger than the semiconductor layer 16. In this case, in order to avoid the adherence of a splash droplet on the channel section 72, the branching-off parts 91b and 92b, which are in the drop-on positions 81, should be located in a further distance from where the TFT-section gate electrode 66 is located, comparing with the arrangement shown in FIG. 1. On the other hand, it is necessary that the electrode raw material applied in positions corresponding to the branching-off parts 91b and 92b (drop-on positions 81) be spread up to the ends of the branch electrodes of the branch electrode sections 91a and 92a. By forming the branch electrode sections 91a and 92a such that the parts associating with the branching-off parts 91b and 92b are oblique, it is possible to locate the branching-off parts 91b and 92b in a farther distance from the TFT-section gate electrode 66, while avoiding the branch electrode sections 91a and 92b from being long between the branching-off part 91b or 92b and the ends.
Moreover, even in case where the droplet from the pattern formation apparatus is applied onto a position (drop-on position 84) shifted from the targeted drop-on position 81 toward the channel section 72, for example, a gap between the branch electrodes of the branch electrode section 91a in the position at which the droplet is applied is narrower than a gap between the branch electrodes of the branch electrode section 17a shown in FIG. 1, because the parts of the branch electrode sections 91a and 92b are oblique, the parts associating with the branching-off parts 91b and 92b. As a result, compared with the arrangement shown in FIG. 1, it is easy to drop the droplet onto the branch electrode sections 91a and 92a. This permits a wider allowance with respect to the drop-on positions 81 at which the electrode raw material is targeted.
Still another embodiment of the present invention is described below, referring to FIGS. 10(a) and 10(b).
In the present embodiment, a TFT section 22 of a TFT array substrate 11 has an arrangement shown in FIG. 10(a). The TFT section 22 is provided with a source electrode 101 and a drain electrode 102, instead of the source electrode 17 and the drain electrode 18, and, for example, a semiconductor layer 16 described above. The TFT array substrate 11 may be manufactured in the same method as in the first embodiment.
The source electrode 101 has the following shape: in a branch electrode section 101a extended over a semiconductor layer 16, part associating with a branching-off part 101b has a large area (is wider). (The branch electrode section 101a gets wider as the branch electrode section 101a gets closer to the branching-off part 101b.) In other words, the branch electrode section 101a is protruded in a trapezium shape from the source electrode 101, and a bottom of the trapezium shape is the branching-off part 101b.
In order to have such arrangement, the source electrode 101 gets gradually wider at part from where the branch electrode section 101a is branched off, so as to be wider toward both sides of the branch electrode section 101a connected to the source electrode 101. In other words, the width of the branch electrode section 101a gets gradually narrower from two bottom angles of the trapezium shape (both the sides of the branch electrode section 101a) to an upper side part thereof, which is protruded on the semiconductor layer 16. Further in other words, where the two bottom angle sections are referred to as a source transition part via which the main line (source wire) of the source electrode 101 is continuous with the part of the source electrode 101 associating the TFT section 22, a width of each source transition part gets wider gradually from the source wire toward the forming area of the semiconductor layer 16 (the area in which the semiconductor layer 16 exists).
Therefore, in the source electrode 101 having such arrangement, drop-on positions 81 described above are located in parts (the two source transition parts) of the source electrode 101, the parts respectively located both sides of the branching-off parts 101b from which the branch electrode section 101a is branched off, whereby a droplet of an electrode raw material is applied out of the area in which the channel section 72 (semiconductor layer 16) exists.
On the other hand, the drain electrode 102 gets gradually wider from a vicinity of the cannel section 72 toward the channel section 72. In other words, supposing that the vicinity is referred to as a drain transition part, via which the wire (drain wire) of the drain electrode 102 is continuous with the part of the drain electrode 102 being closer to the TFT section 22, a width of the drain transition part gets wider gradually from the drain wire toward the forming area of the semiconductor layer 16. Then, an electrode width widening starting section 102a (that is the drain transition part) is the drop-on position 81.
In this arrangement, the electrode raw material is dropped on to an electrode formation area prepared by (i) forming a guide having a mountain-like shape or (ii) wetting/dewetting process, in a source/drain wire preprocessing step 45 described above. Then, in the electrode formation area, a contact angle .theta. shown in FIG. 10(b) causes the electrode raw material to be drawn toward a direction in which the electrode formation area gets wider, and to flow in the direction (spontaneously). Therefore, even in case the drop-on position 81 is set out of the area (forming area) where the channel section 72 (semiconductor layer 16) is located, it is easy to render the thus applied electrode raw material to reach ends of the channel section 72. Thus, the application (dropping) of the wire raw material makes it possible to surely form the source electrode 101 and the drain electrode 102 in the TFT section 22.
In the present embodiment, a TFT section 22 of a TFT array substrate 11 has an arrangement shown in FIG. 11. The TFT section 22 is provided with a source electrode 111 and a drain electrode 112, instead of the source electrode 17 and the drain electrode 18, and for example, a semiconductor layer 93 described above. The semiconductor layer 93 has a substantially circular shape and formed above a linear gate wire (a stem wire of a gate electrode 13) sandwiching a gate insulation layer 15 (see FIGS. 9(a) to (e)) therebetween. The TFT array substrate 11 may be manufactured by the same method as in the second embodiment.
In each arrangement shown in FIGS. 1 to 8, the plurality of electrodes are formed in the TFT section 22, and the branch electrode sections 17a and 18a, or the branch electrode sections 91a and 92a are formed so as to form the wide channel section 72. Such arrangements are effective in case where a charge transfer is large, for example, in case where a large number of pixels are to be driven. Moreover, the arrangements have such an advantage that stable property can be obtained with ease (i) even if the pattern of the TFT-section gate electrode 66 is shifted from the pattern of the source electrode 17 or 91 (branch electrode section 17a or 91a) and the drain electrode 18 or 92 (branch electrode section 18b or 92b) in the direction in which the TFT-section gate electrode 66 is extended, and (ii) especially in the arrangement shown in FIG. 1, even if the pattern of the TFT-section gate electrode 66 is shifted from the pattern of the source electrode 17 or 91 (branch electrode section 17a or 91a) and the drain electrode 18 or 92 (branch electrode section 18b or 92b) further in the direction perpendicular to the direction in which the TFT-section gate electrode s 66 is extended.
In the arrangement of the present embodiment shown in FIG. 11, the branch electrode section 111a, which is branched off from the source electrode 111 and extended above (on) the semiconductor layer 93, and parts of the drain electrode 112 that are closer to the channel section 72 are provided in the direction in which the TFT-section gate electrode is extended, and within an area in which the TFT section electrode 66 is located.
In other words, branch electrodes of the branch electrode section 111a are extended from the source wire crossing the gate wire, and along the gate wire, so as to be extended on the semiconductor layer 93. Whereas, the drain electrode 112 are extended from the drain wire extended perpendicular to the direction in which the gate wire is extended, so as to be extended on the semiconductor layer 93 along the gate wire. Note that a section at which the branch electrode section 111a is branched off from the source wire is referred to a source transit section, whereas a section at which the drain electrode 112 is branched off from the drain wire is referred to as a drain transit section.
In the above arrangement, drop-on positions 81 out of (off) the channel section 72 (semiconductor layer 93) are located in positions (that is, the source transit section) corresponding to branching-off parts 111b of the branch electrode section 111a with respect to the source electrode 111. Moreover, with respect to the drain electrode 112, the drop-on positions 81 are located in positions (that is, the drain transit section) at which the drain electrode 112 is bent toward the channel section 72. With this arrangement, it is possible to prevent that the channel section 72 is adhered with a splash droplet of the electrode raw material applied from the pattern formation apparatus.
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