Source: http://www.google.com/patents/US20020022949?dq=oakley+5,387,949&ei=4yI4T8nkLYa80QG0xqnWAg
Timestamp: 2017-12-11 10:52:51
Document Index: 112218908

Matched Legal Cases: ['art 101', 'art 101', 'art 201', 'art 101', 'art 101', 'art 111', 'art 111', 'art 111', 'art 112', 'art 111', 'art 113', 'art 114', 'art 111', 'art 101', 'art 102', 'art 103', 'art 101', 'art 111', 'art 104', 'art 105']

Patent US20020022949 - Apparatus and method for calculating temporal deterioration margin amount of ... - Google Patents
The present invention makes it possible to obtain an aging deterioration margin amount including an allowance for aging deterioration in a simplified manner. Moreover, in order to allow an appropriate inspection taking aging deterioration into account, a delay deterioration rate predicting part 101 outputs...http://www.google.com/patents/US20020022949?utm_source=gb-gplus-sharePatent US20020022949 - Apparatus and method for calculating temporal deterioration margin amount of LSI, and LSI inspection method
Publication number US20020022949 A1
Application number US 09/810,518
Also published as US6795802
Publication number 09810518, 810518, US 2002/0022949 A1, US 2002/022949 A1, US 20020022949 A1, US 20020022949A1, US 2002022949 A1, US 2002022949A1, US-A1-20020022949, US-A1-2002022949, US2002/0022949A1, US2002/022949A1, US20020022949 A1, US20020022949A1, US2002022949 A1, US2002022949A1
Inventors Hirokazu Yonezawa, Yoshiyuki Kawakami, Nobufusa Iwanishi
Original Assignee Hirokazu Yonezawa, Yoshiyuki Kawakami, Nobufusa Iwanishi
Apparatus and method for calculating temporal deterioration margin amount of LSI, and LSI inspection method
US 20020022949 A1
1. An apparatus for calculating an aging deterioration margin amount of a LSI for calculating an aging deterioration margin amount to be included as a design tolerance with respect to a predetermined property of the LSI so that the LSI can operate even if the property deteriorates, comprising:
beginning-of-life property generating means for obtaining a property before deterioration of the property in an initial state of the LSI with respect to at least a part of a plurality of signal paths constituting the LSI;
end-of-life property generating means for obtaining a property after deterioration of the property when a predetermined operation period has passed under a predetermined operating condition with respect to at least a part of a plurality of signal paths constituting the LSI;
property deterioration degree generating means for obtaining a property deterioration degree which is a ratio of the property after deterioration to the property before deterioration in a signal path having a smallest tolerance of the property after deterioration with respect to a property necessary for the LSI to operate of the plurality of signal paths; and
aging deterioration margin amount generating means for substantially obtaining an aging deterioration margin amount based on the property before deterioration and the property deterioration degree.
2. The apparatus for calculating an aging deterioration margin amount of a LSI according to claim 1, wherein
the aging deterioration margin amount generating means obtains an aging deterioration margin amount that is a difference between a product of the property before deterioration and the property deterioration degree, and the property before deterioration.
3. The apparatus for calculating an aging deterioration margin amount of a LSI according to claim 1, wherein
the aging deterioration margin amount generating means substantially obtains an aging deterioration margin amount by obtaining a product of the property before deterioration and the property deterioration degree.
4. The apparatus for calculating an aging deterioration margin amount of a LSI according to claim 1, wherein
the aging deterioration margin amount generating means obtains the property before deterioration and the property deterioration degree, and further substantially obtains an aging deterioration margin amount based on a predetermined tolerance rate.
5. The apparatus for calculating an aging deterioration margin amount of a LSI according to claim 1, wherein
the end-of-life property generating means for obtaining the property after deterioration with respect to signal paths of a group having a small tolerance of the property before deterioration with respect to a property necessary for the LSI to operate of a plurality of groups into which a plurality of signal paths constituting the LSI are divided.
6. The apparatus for calculating an aging deterioration margin amount of a LSI according to claim 1, wherein
the aging deterioration margin amount generating means obtains the substantial aging deterioration margin amount with respect to a signal path different from the signal paths for which the property deterioration degree is obtained.
7. The apparatus for calculating an aging deterioration margin amount of a LSI according to claim 1, wherein
the property before deterioration is a delay before deterioration,
the property after deterioration is a delay after deterioration,
the property deterioration degree is a delay deterioration rate
the property necessary for the LSI to operate is a design target delay, and
the aging deterioration margin amount is a delay deterioration margin amount.
8. The apparatus for calculating an aging deterioration margin amount of a LSI according to claim 7, wherein
the aging deterioration margin amount generating means uses the property deterioration degree as a derating factor corresponding to aging deterioration of the property to calculate a largest delay including the aging deterioration margin amount by multiplying the delay before deterioration by derating factors corresponding to each of at least a product deviation, a supply voltage variation, and a temperature variation as well as the derating factor corresponding to aging deterioration of the property.
9. The apparatus for calculating an aging deterioration margin amount of a LSI according to claim 7, wherein
a supply voltage condition in the predetermined operating conditions when the end-of-life property generating means obtains the property after deterioration is different from a supply voltage condition under which the beginning-of-life property generating means and the end-of-life property generating means obtain the property before deterioration and the property after deterioration.
10. The apparatus for calculating an aging deterioration margin amount of a LSI according to claim 7, wherein
the beginning-of-life property generating means and the end-of-life property generating means obtain the delay before deterioration and the delay after deterioration, using the property of the element whose delay before deterioration and delay after deterioration are largest in a range of a property deviation of elements constituting the LSI.
11. The apparatus for calculating an aging deterioration margin amount of a LSI according to claim 10, wherein
the property of the element whose delay before deterioration and delay after deterioration are largest is a lowest response of the element.
12. The apparatus for calculating an aging deterioration margin amount of a LSI according to claim 7, wherein
a supply voltage condition in the predetermined operating conditions when the end-of-life property generating means obtains the property after deterioration is different from a supply voltage condition under which the beginning-of-life property generating means and the end-of-life property generating means obtain the property before deterioration and the property after deterioration, and
the beginning-of-life property generating means and the end-of-life property generating means obtain the delay before deterioration and the delay after deterioration, using the property of the element in which a delay before deterioration and a delay after deterioration are largest in a range of a deviation of a property of elements constituting the LSI.
13. An apparatus for calculating an aging deterioration margin amount of a LSI for calculating an aging deterioration margin amount to be included as a design tolerance with respect to a predetermined property of the LSI so that the LSI can operate even if the property deteriorates, comprising:
aging deterioration margin amount generating means for substantially obtaining an aging deterioration margin amount, based on
a property before deterioration of the property in an initial state of the LSI with respect to at least a part of a plurality of signal paths constituting the LSI; and
a property deterioration degree obtained by obtaining a property after deterioration of the property when a predetermined operation period has passed under a predetermined operating condition with respect to at least a part of a plurality of signal paths constituting the LSI, and obtaining a ratio of the property after deterioration to the property before deterioration in a signal path having a smallest tolerance of the property after deterioration with respect to a property necessary for the LSI to operate of the plurality of signal paths, the ratio being the property deterioration degree.
14. A method for calculating an aging deterioration margin amount of a LSI for calculating an aging deterioration margin amount to be included as a design tolerance with respect to a predetermined property of the LSI so that the LSI can operate even if the property deteriorates, comprising:
a beginning-of-life property generating step for obtaining a property before deterioration of the property in an initial state of the LSI with respect to at least a part of a plurality of signal paths constituting the LSI;
an end-of-life property generating step for obtaining a property after deterioration of the property when a predetermined operation period has passed under a predetermined operating condition with respect to at least a part of a plurality of signal paths constituting the LSI;
a property deterioration degree generating step for obtaining a property deterioration degree which is a ratio of the property after deterioration to the property before deterioration in a signal path having a smallest tolerance of the property after deterioration with respect to a property necessary for the LSI to operate of the plurality of signal paths; and
an aging deterioration margin amount generating step for substantially obtaining an aging deterioration margin amount based on the property before deterioration and the property deterioration degree.
15. A method for inspecting a LSI with respect to a predetermined property of the LSI that the LSI can operate even if the property deteriorates, comprising:
obtaining a property before deterioration of the property in an initial state of the LSI with respect to at least a part of a plurality of signal paths constituting the LSI;
obtaining a property after deterioration of the property when a predetermined operation period has passed under a predetermined operating condition with respect to at least a part of a plurality of signal paths constituting the LSI;
obtaining a property deterioration degree which is a ratio of the property after deterioration to the property before deterioration in a signal path having a smallest tolerance of the property after deterioration with respect to a property necessary for the LSI to operate of the plurality of signal paths; and
inspecting an operation of the LSI using a frequency obtained by multiplying the property deterioration degree by a predetermined frequency as an operation frequency.
where t cycle is a cycle time, which is a design target property, Σti is the total of signal propagation delay between input and output terminals of each circuit i (22) between the flip-flops 21, that is, a signal path delay in the LSI, and K is the sum of the setup time of the flip-flops 21 and the skew of the clock signal 23.
t worst=t typ×P×V×T (2)
where t worst is the maximum value (the worst value) of each signal path delay, t typ is a typical value of each signal path delay, P is a delay variation coefficient in accordance with production deviation, V is a delay variation coefficient in accordance with the amount of a supply voltage variation width, and T is a delay variation coefficient in accordance with the amount of a temperature variation width. The difference between the t worst and the t typ is a margin amount for the delay variation to be considered.
where Σ Δti is a variation amount of the signal path delay due to deterioration. Thus, when designing a LSI, it is necessary to make allowance for the influence of delay increments due to deterioration, and to include a design tolerance, that is, an aging deterioration margin amount so that the equation (3) is satisfied.
However, the method for inspecting LSIs using the supply voltage difference ΔV obtained by actual measurement after production of the targeted LSI has the following problems. As shown in FIG. 3, assuming that a signal path A is the critical path in a fresh LSI, based on that path, apparently, it is possible to obtain the supply voltage difference ΔV by simulations and actual measurement as above, and to check an apparent delay increment Δt corresponding to the aging deterioration of the signal path A by controlling the supply voltage based on the difference. (Therefore, in the method of the above reference, an LSI in the initial state is inspected not by using VDD min as the supply voltage as shown in (1) of FIG. 3, but by reducing to (VDD min−ΔV) to increase the delay as shown in (2) of FIG. 3 so that the delay after deterioration of (3) of FIG. 3 is simulated.) However, in reality, the relationship between the supply voltage and the delay and the relationship between the operation time and the delay are non-linear, and these relationships are different between signal paths. Therefore, even if a LSI is determined to be non-defective in an inspection with the supply voltage difference ΔV set at the signal path A, the LSI does not necessarily operate normally during deterioration, and the opposite case can be true. More specifically, with respect to another signal path B that has the same signal path delay as that of the signal path A at a supply voltage VDD min in the initial state as shown in (4) of FIG. 3, even if in an inspection with the supply voltage (VDD min—ΔV) as shown in (5) of FIG. 3, the delay is within a design targeted delay so that it is determined that there is no problem, there is a possibility that the delay after deterioration in reality is beyond the design targeted delay, resulting in the malfunction, as shown in (6) of FIG. 3.
Furthermore, by inspecting the operation of the LSI, using the frequency obtained by multiplying the property deterioration degree obtained in the same manner as the aging deterioration margin amount as above by a predetermined frequency as the operation frequency, errors due to a nonlinear relationship between the supply voltage and the delay cannot occur, for example, compared with the case where inspection is performed with the reduced supply voltage obtained by converting the difference between delays before and after deterioration to a supply voltage difference. Thus, underestimate or overestimate of the aging deterioration margin amount can be avoided without fail.
[0029]FIG. 1 is a circuit diagram showing a general configuration of a signal path.
[0030]FIG. 2 is a graph showing the relationship between the cycle time and the inspection voltage for explaining a conventional inspection method.
[0031]FIG. 3 is a diagram showing an example of delays before and after deterioration together with the supply voltage.
[0032]FIG. 4 is a block diagram showing the entire configuration of an apparatus for calculating an aging deterioration margin amount according to Embodiment 1 of the present invention.
[0033]FIG. 5 is a block diagram showing a detailed configuration of a delay deterioration rate predicting part 101 according to Embodiment 1 of the present invention.
[0034]FIG. 6 is a table showing an example of signal path delays before and after deterioration and signal path delay deterioration rates according to Embodiment 1 of the present invention.
[0035]FIG. 7 is a graph showing an example of the relationship between the signal path delay before deterioration and the signal path delay deterioration rate according to Embodiment 1 of the present invention.
[0036]FIG. 8 is a graph with an envelope curve showing an example of the relationship between the signal path delay before deterioration and the signal path delay deterioration rate according to Embodiment 1 of the present invention.
[0037]FIG. 9 is a graph for explaining an example for obtaining the delay deterioration rate according to Embodiment 1 of the present invention.
[0038]FIG. 10 is a graph for explaining another example for obtaining the delay deterioration rate according to Embodiment 1 of the present invention.
[0039]FIG. 11 is a graph for explaining still another example for obtaining the delay deterioration rate according to Embodiment 1 of the present invention.
[0040]FIG. 12 is a block diagram showing a detailed configuration of a delay deterioration rate predicting part 201 of an apparatus for calculating an aging deterioration margin amount according to Embodiments 2 and 3 of the present invention.
[0041]FIG. 13 is a graph for explaining an example of the supply voltage for obtaining the delay after deterioration of Embodiment 2 of the present invention.
[0042]FIG. 14 is another graph for explaining an example of the supply voltage according to Embodiments 2 of the present invention.
[0043]FIG. 15 is a graph showing an example of the property deviation of transistors constituting a LSI.
[0046]FIG. 4 is a block diagram showing the entire configuration of an apparatus for calculating an aging deterioration margin amount used when designing and inspecting LSIs. In the configuration of FIG. 4, a delay deterioration rate predicting part 101 calculates an (initial) delay before deterioration (beginning-of-life property) of each of the signal paths constituting a LSI, based on LSI design information 301 to output signal path delay information before deterioration 302, and calculates a delay deterioration rate (property deterioration degree) when each signal path has operated over the desired period of the product lifetime to output signal path delay deterioration rate information 303. The LSI design information 301 includes all information necessary for the LSI design such as the types of included logic circuits, the net list indicating the connection relationship between logic circuits, parasitic element information in the connection wiring of logic circuits, mask shape information, production information, operating conditions (supply voltage, temperature, the switching probability, and operation frequency or the like) and a product lifetime target, etc, corresponding to the signal paths 20 shown in FIG. 1, for example. The LSI design information 301 and the following information are stored in a storing part, which is not shown.
More specifically, as shown in FIG. 5 for example, the delay deterioration rate predicting part 101 includes a beginning-of-life circuit analyzing part 111 including a signal path delay calculating part 111 a (beginning-of-life property generating means) for outputting beginning-of-life signal path delay information 302 and a unit circuit stress calculating part 111 b for calculating a stress to a unit circuit such as transistors, a unit circuit deterioration degree analyzing part 112 for analyzing the current vs. voltage property based on information output from the unit circuit stress calculating part 111 b, an end-of-life circuit analyzing part 113 (end-of-life property generating means) for obtaining a delay after deterioration based on the analysis results, and a delay deterioration rate calculating part 114 (property deterioration degree generating means) for outputting the signal path delay deterioration rate information 303 based on the obtained delay after deterioration and the signal path delay information before deterioration 302 output from the signal path delay calculating part 111 a.
Next, the operation of the apparatus for calculating an aging deterioration margin amount configured as above will be described. The operation of this calculating apparatus can be categorized roughly into an operation for first analyzing a certain LSI to obtain the delay deterioration margin 305 and an operation for obtaining a delay deterioration margin amount and an operation frequency for inspection of a LSI other than one that is to be designed (or the above LSI when subjected to a design change), using the obtained delay deterioration margin 305. The operation of the former is performed by the delay deterioration rate predicting part 101, the delay vs. delay deterioration rate analyzing part 102, and the delay deterioration rate extracting part 103. The operation of the latter is performed by a part of the delay deterioration rate predicting part 101 (signal path delay calculating part 111 a), the delay deterioration margin amount calculating part 104, and the inspection operation frequency calculating part 105 (elements included within a broken line in FIG. 4). Hereinafter, these two operations will be described more specifically.
where t fresh and t aged are signal path delays before and after deterioration, respectively. FIG. 6 is a table showing specific examples (e.g., with respect to signal paths 1 to M) of the signal path delay before deterioration, signal path delay after deterioration, and the signal path delay deterioration rate.
t worst=t typ×P×V×T×G (5)
where t worst is the largest value (worst value) of the signal path delays, t typ is a typical value of the signal path delays (signal path delay information before deterioration 302), P is a delay variation coefficient in accordance with production deviation, V is a delay variation coefficient in accordance with the amount of the supply voltage variation width, and T is a delay variation coefficient in accordance with the amount of the temperature variation width. The difference between the cases of multiplying by G and not multiplying by G, that is, t typ×P×V×T× (G−1) is a delay deterioration margin amount.
[0064]f aged=f fresh×G (6)
The operation frequency for inspection obtained in the above described manner is supplied to a LSI, and it is checked whether or not the LSI operates normally, and thus an accurate inspection can be performed. In other words, reduction of a tolerance resulting from an increase of the delay to G times due to deterioration with respect to an operation frequency (cycle time) is equivalent to reduction of a tolerance resulting from an increase of the operation frequency to G times (the cycle time is 1/G times) with respect to the delay before deterioration. Therefore, compared with a conventional case where the difference between the delays before and after deterioration is converted to a supply voltage difference and inspection is performed with a reduced supply voltage, an error caused by the fact that the supply voltage vs. delay has a non-linear relationship cannot be occur, and underestimation or overestimation of the aging deterioration margin amount can be avoided without fail.
Furthermore, in the above example, the delay is used as the property noted as a subject for aging deterioration. However, the present invention can apply to other various properties that are time-dependently deteriorated such as the frequency property. For example, in the case where the present invention applies to the frequency property, the same is true if the horizontal axis of FIG. 7 is indicated by (1/ the frequency).
Setting in the above-described manner results in obtaining a delay deterioration margin, using the maximum supply voltage VDDmax that provides the largest signal path delay deterioration rate information 303 as the voltage for operation up to the end of the product lifetime and the minimum supply voltage VDDnmin that provides the largest signal path delay before deterioration, as shown in FIG. 13. More specifically, as shown in FIG. 14, the signal path delay after deterioration becomes larger as the applied supply (stress) voltage is higher during deterioration. In addition, the signal path delay becomes larger as the supply voltage is lower (e.g., b>a), regardless of before or after deterioration. Therefore, the following signal path delay (c in FIG. 14) is the largest signal path delay: a signal path delay when the deteriorated LSI that has been operated with the maximum supply voltage VDDmax is operated with the minimum supply voltage VDDmin. Thus, the worst value of the delay after deterioration can be obtained. This value is larger than the case the maximum supply voltage VDDmax is used in all the time, and this value can happen in a practical scene.
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International Classification G01R31/3183, G01R31/28
Cooperative Classification G01R31/318342, G01R31/287, G01R31/318371
European Classification G01R31/3183F, G01R31/3183M
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YONEZAWA, HIROKAZU;KAWAKAMI, YOSHIYUKI;IWANISHI, NOBUFUSA;REEL/FRAME:012096/0904