Source: http://www.google.com/patents/US7984266?dq=7200212
Timestamp: 2017-08-18 07:50:28
Document Index: 288662892

Matched Legal Cases: ['Application No. 200580008575', 'Application No. 200780000013', 'Application No. 200780000014', 'Application No. 200780000015', 'Application No. 05723250', 'Application No. 05723250', 'Application No. 07250614', 'Application No. 07250614', 'Application No. 07250614', 'Application No. 07250645', 'Application No. 07250645', 'Application No. 07250645', 'Application No. 07250646', 'Application No. 07250646', 'Application No. 07250646', 'Application No. 07250647', 'Application No. 07250647', 'Application No. 07250647', 'Application No. 07250648', 'Application No. 07250648', 'Application No. 07250648', 'Application No. 07250649', 'Application No. 07250649', 'Application No. 07250649', 'Application No. 07250649', 'Application No. 08251499', 'Application No. 08251499', 'Application No. 08251505', 'Application No. 08251505', 'Application No. 2007', 'Application No. 2007']

Patent US7984266 - Integrated computer array with independent functional configurations - Google Patents
A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits...http://www.google.com/patents/US7984266?utm_source=gb-gplus-sharePatent US7984266 - Integrated computer array with independent functional configurations
Publication number US7984266 B2
Application number US 11/810,183
Also published as CN101421703A, EP1784710A2, EP1784710A4, US7937557, US20050228904, US20070245121, WO2005091847A2, WO2005091847A3
Publication number 11810183, 810183, US 7984266 B2, US 7984266B2, US-B2-7984266, US7984266 B2, US7984266B2
Patent Citations (104), Non-Patent Citations (101), Classifications (9), Legal Events (4)
US 7984266 B2
FIG. 3 is a diagrammatic representation of an example of a computer array 10 a showing one possible allocation of the computers 12 therein. The example of the computer array 10 a of FIG. 3 differs from the first example of the computer array 10 of FIG. 1 in the allocation of the computers 12, as will be discussed in more detail hereinafter. It should be noted that, as with the view of FIG. 1, the view of FIG. 3 is not intended as a layout diagram and, therefore, is not intended to indicate a necessary physical placement of any of the computers 12. Nevertheless, the example of FIG. 3 is indicative of the fact that it is thought that the 5 by 5 computer array 10 a is a useful physical arrangement of the computers 12. According to this arrangement there are sufficiently few computers that not too many are buried deep within the computer array 10 a, such that more than a few “hops” would be required to relay data from one of the exterior computers 12, through others of the computers 12, to an interior computer 12. Further, the quantity of twenty five computers is well suited to maximize the usage of available space on the die 14. It is anticipated that, even in many applications where all twenty five of the computers 12 are not required, it may well be cost efficient to use an array such as the example here described. It should be noted that the 5 by 5 arrangement of the computer array 10 a and the quantity of twenty five of the computers 12, while thought to be a useful arrangement and quantity (as discussed above), is by no means thought to be the only useful arrangement and quantity. Presently, a 6 by 4 matrix having 24 of the computers 12 in the matrix, as discussed previously in relation to FIG. 1, is thought to have some particular advantages. For example, in an array wherein there are even numbers of the computers 12, the array can be made up of a plurality of 2 by 2 blocks of the computers. In such case, each of the computers 12 can be made to be a mirror image of the computers across from it in the block. This might make easier the task of computer design and interconnection layout. Indeed, factors to be discussed in more detail hereinafter dictate that essentially any quantity, from as few as four, up to and including literally thousands of the computers, could be arrayed together according to the present invention. Also, although the example of FIG. 1 shows three of the data lines 16 connecting each of the computers 12 to its neighbors, the inventor believes that another useful arrangement would be to have data lines 16 connecting each of the computers 12 to all of its nearest neighbor computers 12. In such a connection arrangement, the number of data lines 16 connected to each of the computer 12 would vary according to the placement of each computer 12 in the array 10, 10 a.
The example computer array 10 a of FIG. 3 has the computers 12 assigned to tasks such as might be useful to create a global positioning system (“GPS”) receiver. This example of FIG. 3 is presented only as an example of how various tasks might be assigned to the various computers 12. Interconnections are not shown, as they will not be substantially different from the example of FIG. 1, except as might be necessary or desirable to accomplish the specific tasks described.
In the example of FIG. 3, computer 12 i is configured to be a RAM input/output device, while computer 12 j is configured to be a flash memory input/output device. By a comparison to the example of FIG. 1, it can be seen that this example shows a variation in that the computer array 10 of FIG. 1 has a single computer 12 for handling the input and output from both the flash memory 18 and the RAM 20 (FIG. 1), while the present example of the computer array 10 a divides these tasks between computers 12. Such a variation is typical of many such variations that might be applied to the computer array 10, 10 a.
Returning to a discussion of the peripheral computers 12 a through 12 p, the computers 12 a through 12 d are configured for input and output to external devices. In the example shown, computers 12 a through 12 d implement a LAN interface, a USB interface, a Firewire interface, and a wireless interface, respectively. One skilled in the art will be familiar with the pin out and hardware protocols necessary to implement each of these functions in the computers 12 a through 12 d. Alternatively, one of the computers 12 a through 12 d could be used to implement a video output. In some applications fewer than the four input/output computers 12 a through 12 d might be required. For example, in some applications, only a USB interface might be sufficient input/output to external devices.
In the GPS receiver example of FIG. 3, the computer 12 e provides a hardware control (which is a digital input and output) for setting parameters of the remainder of the receiver (not shown) external to the computer array 10 a. The computer 12 f provides hardware monitoring (which is an analog input and output) for monitoring parameters of operational aspects of the receiver. The hardware monitoring and control allows the computer array 10 a to determine how well the rest of the GPS receiver is operating, as well as providing a means to set or modify various operating configurations of the rest of the receiver external to the computer array 10 a.
Computers 12 o and 12 p are configured and programmed to sample and process received RF signals (analog to digital conversion) and the computer 12 n is configured and programmed to provide reference frequencies for frequency down conversion prior to sampling (digital to analog conversion). Computer 12 w and 12 x are configured and programmed to decode the forward error corrected (“FEC”) bit stream from the GPS signal. The FEC used in GPS signals will be familiar to on skilled in the art of GPS receivers.
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U.S. Classification 712/10, 712/16
International Classification G06F15/76, G06F3/00, G06F15/00
Cooperative Classification G06F9/5044, G06F9/5066
European Classification G06F9/50C2, G06F9/50A6H