Source: http://www.google.com/patents/US8023322?dq=6,250,774
Timestamp: 2015-03-29 16:52:23
Document Index: 12591891

Matched Legal Cases: ['Application No. 03825099', 'Application No. 03825099', 'Application No. 03749708', 'Application No. 03749708', 'Application No. 03', 'Application No. 2004', 'Application No. 2004', 'Application No. 2005', 'Application No. 2005', 'Application No. 92126112', 'Application No. 03825099']

Patent US8023322 - Non-volatile memory and method with reduced neighboring field errors - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same word...http://www.google.com/patents/US8023322?utm_source=gb-gplus-sharePatent US8023322 - Non-volatile memory and method with reduced neighboring field errorsAdvanced Patent SearchPublication numberUS8023322 B2Publication typeGrantApplication numberUS 12/749,292Publication dateSep 20, 2011Filing dateMar 29, 2010Priority dateSep 24, 2002Also published asCN1703758A, CN100590741C, EP1543527A2, EP1543527B1, US6987693, US7239551, US8300457, US20040057285, US20060023502, US20070279992, US20100182831, US20120002483, WO2004029983A2, WO2004029983A3Publication number12749292, 749292, US 8023322 B2, US 8023322B2, US-B2-8023322, US8023322 B2, US8023322B2InventorsRaul-Adrain Cernea, Yan LiOriginal AssigneeSandisk Technologies Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (91), Non-Patent Citations (25), Referenced by (1), Classifications (19), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetNon-volatile memory and method with reduced neighboring field errors
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4357685Jul 14, 1980Nov 2, 1982Sgs-Ates Componenti Elettronici S.P.A.Method of programming an electrically alterable nonvolatile memoryUS4785427Jan 28, 1987Nov 15, 1988Cypress Semiconductor CorporationDifferential bit line clampUS5070032Mar 15, 1989Dec 3, 1991Sundisk CorporationConductive strips, isolated floating gatesUS5093806Jun 13, 1989Mar 3, 1992Tran Hiep VSensing and decoding scheme for a bicmos read/write memoryUS5095344Jun 8, 1988Mar 10, 1992Eliyahou HarariHighly compact eprom and flash eeprom devicesUS5172338Apr 11, 1990Dec 15, 1992Sundisk CorporationMulti-state EEprom read and write circuits and techniquesUS5245571Nov 27, 1991Sep 14, 1993Nec CorporationSense amplifier circuit implemented by bipolar transistor and improved in current consumptionUS5313421Jan 14, 1992May 17, 1994Sundisk CorporationMemory structureUS5315541Jul 24, 1992May 24, 1994Sundisk CorporationSegmented column memory arrayUS5343063Dec 18, 1990Aug 30, 1994Sundisk CorporationDense vertical programmable read only memory cell structure and processes for making themUS5418752Oct 20, 1992May 23, 1995Sundisk CorporationFlash EEPROM system with erase sector selectUS5446690May 25, 1994Aug 29, 1995Hitachi, Ltd.Semiconductor nonvolatile memory deviceUS5537356Jun 5, 1995Jul 16, 1996Fujitsu LimitedNonvolatile semiconductor memoryUS5570315Sep 21, 1994Oct 29, 1996Kabushiki Kaisha ToshibaMulti-state EEPROM having write-verify control circuitUS5595924Dec 19, 1994Jan 21, 1997Sandisk CorporationTechnique of forming over an irregular surface a polysilicon layer with a smooth surfaceUS5650970Sep 26, 1995Jul 22, 1997Kabushiki Kaisha Toshibasemiconductor memory device having a flash write functionUS5661053May 25, 1994Aug 26, 1997Sandisk CorporationMethod of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacersUS5768192Jul 23, 1996Jun 16, 1998Saifun Semiconductors, Ltd.Non-volatile semiconductor memory cell utilizing asymmetrical charge trappingUS5774397Sep 10, 1996Jun 30, 1998Kabushiki Kaisha ToshibaNon-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined stateUS5806082Aug 13, 1996Sep 8, 1998Intel CorporationWrap-around mechanism for memory split-wordline readUS5860082Mar 28, 1996Jan 12, 1999Datalight, Inc.Method and apparatus for allocating storage in a flash memoryUS5872739Apr 17, 1997Feb 16, 1999Radiant TechnologiesSense amplifier for low read-voltage memory cellsUS5903495Mar 17, 1997May 11, 1999Kabushiki Kaisha ToshibaSemiconductor device and memory systemUS5920502Nov 21, 1997Jul 6, 1999Sony CorporationNonvolatile semiconductor memory with fast data programming and erasing function using ECCUS5949720Oct 30, 1998Sep 7, 1999Stmicroelectronics, Inc.Integrated circuit chipUS6011287Feb 27, 1998Jan 4, 2000Kabushiki Kaisha ToshibaNon-volatile semiconductor memory deviceUS6011725Feb 4, 1999Jan 4, 2000Saifun Semiconductors, Ltd.Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trappingUS6046935Jan 27, 1999Apr 4, 2000Kabushiki Kaisha ToshibaSemiconductor device and memory systemUS6046940Apr 21, 1999Apr 4, 2000Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS6058042Dec 23, 1998May 2, 2000Sony CorporationSemiconductor nonvolatile memory device and method of data programming the sameUS6061270Dec 28, 1998May 9, 2000Samsung Electronics Co., Ltd.Method for programming a non-volatile memory device with program disturb controlUS6062270Jul 10, 1998May 16, 2000Lindab AbDouble-walled structure in a ventilation duct systemUS6097638Feb 11, 1998Aug 1, 2000Kabushiki Kaisha ToshibaSemiconductor memory deviceUS6222762Aug 7, 1997Apr 24, 2001Sandisk CorporationMulti-state memoryUS6252798Jun 25, 1998Jun 26, 2001Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulseUS6301153Feb 23, 2000Oct 9, 2001Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS6307783Feb 26, 2001Oct 23, 2001Advanced Micro Devices, Inc.Descending staircase read technique for a multilevel cell NAND flash memory deviceUS6353555 *Jun 20, 2000Mar 5, 2002Samsung Electronics Co., Ltd.Flash memory device capable of minimizing a substrate voltage bouncing and a program method thereofUS6373746Sep 22, 2000Apr 16, 2002Kabushiki Kaisha ToshibaNonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cellsUS6407953Feb 2, 2001Jun 18, 2002Matrix Semiconductor, Inc.Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arraysUS6438038Dec 26, 2000Aug 20, 2002Kabushiki Kaisha ToshibaRead circuit of nonvolatile semiconductor memoryUS6490199May 30, 2001Dec 3, 2002Samsung Electronics Co., Ltd.Sense amplifier circuit for a flash memory deviceUS6504757Aug 3, 2001Jan 7, 2003Advanced Micro Devices, Inc.Double boosting scheme for NAND to improve program inhibit characteristicsUS6519180Aug 13, 2001Feb 11, 2003Silicon Storage Technology, Inc.Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit systemUS6535434Apr 5, 2001Mar 18, 2003Saifun Semiconductors Ltd.Architecture and scheme for a non-strobed read sequenceUS6545917Dec 10, 2001Apr 8, 2003Hynix Semiconductor, Inc.Circuit for clamping word-line voltageUS6556508Jul 25, 2002Apr 29, 2003Integrated Memory Technologies, Inc.Integrated circuit memory device having interleaved read and program capabilities and methods of operating sameUS6650570Sep 17, 2001Nov 18, 2003Kabushiki Kaisha ToshibaNon-volatile semiconductor memoryUS6717851Jan 10, 2001Apr 6, 2004Sandisk CorporationMethod of reducing disturbs in non-volatile memoryUS6731539Apr 4, 2003May 4, 2004Sau Ching WongMemory with offset bank select cells at opposite ends of buried diffusion linesUS6738289Feb 26, 2001May 18, 2004Sandisk CorporationNon-volatile memory with improved programming and method thereforUS6744667Sep 27, 2002Jun 1, 2004Sharp Kabushiki KaishaBit line control decoder circuit, virtual ground type nonvolatile semiconductor storage device provided with the decoder circuit, and data read method of virtual ground type nonvolatile semiconductor storage deviceUS6751129May 21, 2002Jun 15, 2004Sandisk CorporationEfficient read, write methods for multi-state memoryUS6829185Nov 7, 2002Dec 7, 2004Infineon Technologies AgMethod for precharging memory cells of a dynamic semiconductor memory during power-up and semiconductor memoryUS6859394Mar 6, 2002Feb 22, 2005Kabushiki Kaisha ToshibaNAND type non-volatile semiconductor memory deviceUS6956770Sep 17, 2003Oct 18, 2005Sandisk CorporationNon-volatile memory and method with bit line compensation dependent on neighboring operating modesUS6983428Sep 24, 2002Jan 3, 2006Sandisk CorporationHighly compact non-volatile memory and method thereofUS6987693Sep 24, 2002Jan 17, 2006Sandisk CorporationNon-volatile memory and method with reduced neighboring field errorsUS7023736Sep 17, 2003Apr 4, 2006Sandisk CorporationNon-volatile memory and method with improved sensingUS7046568Dec 16, 2004May 16, 2006Sandisk CorporationMemory sensing circuit and method for low voltage operationUS7239551Sep 26, 2005Jul 3, 2007Sandisk CorporationNon-volatile memory and method with reduced neighboring field errorsUS20010006479Dec 26, 2000Jul 5, 2001Tamio IkehashiRead circuit of nonvolatile semiconductor memoryUS20020036925Sep 17, 2001Mar 28, 2002Toru TanzawaNon-volatile semiconductor memoryUS20020039322Aug 13, 2001Apr 4, 2002Tran Hieu VanArray architecture and operating methods for digital multilevel nonvolatile memory integrated circuit systemUS20020118574Feb 26, 2001Aug 29, 2002Geoffrey GongwerNon-volatile memory with improved programming and method thereforUS20020126532Mar 6, 2002Sep 12, 2002Kabushiki Kaisha ToshibaNon-volatile semiconductor memory deviceUS20040057285Sep 24, 2002Mar 25, 2004Sandisk CorporationNon-volatile memory and method with reduced neighboring field errorsUS20040057287Sep 24, 2002Mar 25, 2004Sandisk CorporationNon-volatile memory and method with reduced source line bias errorsUS20040057318Sep 24, 2002Mar 25, 2004Sandisk CorporationNon-volatile memory and method with reduced bit line crosstalk errorsUS20040060031Sep 24, 2002Mar 25, 2004Sandisk CorporationHighly compact non-volatile memory and method thereofUS20040109357Sep 17, 2003Jun 10, 2004Raul-Adrian CerneaNon-volatile memory and method with improved sensingUS20050057965Sep 17, 2003Mar 17, 2005Raul-Adrian CerneaNon-volatile memory and method with bit line coupled compensationUS20050169082Dec 16, 2004Aug 4, 2005Raul-Adrian CerneaMemory sensing circuit and method for low voltage operationUS20060034121Oct 13, 2005Feb 16, 2006Shahzad KhalidNon-volatile memory and method with bit line compensation dependent on neighboring operating modesUS20070279992Jul 2, 2007Dec 6, 2007Raul-Adrian CerneaNon-Volatile Memory And Method With Reduced Neighboring Field ErrorsCN1100553AJun 1, 1994Mar 22, 1995株式会社日立制作所Semiconductor nonvolatile momory deviceEP0797212A2Mar 18, 1997Sep 24, 1997Kabushiki Kaisha ToshibaSemiconductor device and memory systemEP1134746A2Mar 8, 2001Sep 19, 2001Kabushiki Kaisha ToshibaNon-volatile semiconductor memoryEP1164595A1Feb 9, 2000Dec 19, 2001Hitachi, Ltd.Semiconductor deviceEP1288964A2Mar 8, 2001Mar 5, 2003Kabushiki Kaisha ToshibaNon-volatile semiconductor memoryJP2001325796A Title not availableJP2002279788A Title not availableJP2004519804A Title not availableJPH09245493A Title not availableJPH09251787A Title not availableJPH10228792A Title not availableKR20020056208A Title not availableWO2002069340A1Feb 15, 2002Sep 6, 2002Gudesen Hans GudeNon-destructive readoutWO2004029984A2Sep 23, 2003Apr 8, 2004Sandisk CorpNon-volatile memory and its sensing methodWO2005029502A1Sep 8, 2004Mar 31, 2005Raul-Adrian CerneaNon-volatile memory and method with bit line to bit line coupled compensationWO2006065501A1Nov 28, 2005Jun 22, 2006Sandisk CorpMemory sensing circuit and method for low voltage operation* Cited by examinerNon-Patent CitationsReference1China State Intellectual Property Office, "Office Action," corresponding Chinese Patent Application No. 03825099.3, mailed on Feb. 23, 2009, 5 pages (including translation.).2China State Intellectual Property Office, "Office Action," corresponding Chinese Patent Application No. 03825099.3, mailed on Jun. 6, 2008, 11 pages (including translation.).3Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.4EPO, "Office Action," corresponding European Patent Application No. 03749708.8, mailed on Apr. 14, 2009, 2 pages.5EPO, "Office Action," corresponding European Patent Application No. 03749708.8, mailed on Jan. 29, 2010, 4 pages.6EPO, "Office Action," mailed in related European Patent Application No. 03 749 708. 8 on Jul. 3, 2007, 3 pages.7EPO/ISA (International Searching Authority), "Notification of Transmittal of the International Search Report or the Declaration", issued in corresponding PCT Application No. PCT/US03/29045, Jul. 28, 2004, 6 pages.8EPO/ISA, "Communication Relating to the Results of the Partial International Search" in PCT/US03/29603, EPO International Searching Authority, Jul. 30, 2004, 2 pages.9EPO/ISA, "International Search Report,"corresponding to PCT/US03/30133, International Searching Authority, European Patent Office, filed Sep. 18, 2003, 4 pages.10EPO/ISA, "Notification of Transmittal fo the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration", mailed in related PCT/US2004/029426 on Jan. 20, 2005, 12 pages.11EPO/ISA, "Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration," mailed in related PCT/US2005/042854 (Publication No. WO 2006/065501 A1) on Apr. 20, 2006, 9 pages.12EPO/ISA, "Notification of Transmittal of the International Search Report or the Declaration", mailed in related PCT/US03/29603 on Nov. 5, 2004, 9 pages.13European Patent Office/International Searching Authority, "Notification of Transmittal of the International Preliminary Examination Report," mailed in related International Application No. PCT/US2004/029426 (Publication No. WO 2005/029502 A1) on Jun. 2, 2006, 8 pages.14Japanese Patent Office, "Notification of Reasons for Refusal," corresponding Japanese Patent Application No. 2004-540088, mailed on Jul. 20, 2010, 8 pages (including translation.).15Japanese Patent Office, "Notification of Reasons for Refusal," corresponding Japanese Patent Application No. 2004-540088, mailed on Jun. 16, 2009, 7 pages (including translation.).16Korean Patent Office, "Notice of Preliminary Rejection," corresponding Korean Patent Application No. 2005-7005118, mailed on Jan. 22, 2011, 5 pages (including translation.).17Korean Patent Office, "Notice of Preliminary Rejection," corresponding Korean Patent Application No. 2005-7005118, mailed on Mar. 29, 2010, 4 pages (including translation.).18Taiwanese Patent Office, "Office Action and Search Report," corresponding Taiwanese Patent Application No. 92126112, mailed on Mar. 13, 2009, 9 pages (including translation.).19Tanaka et al., "A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-Only NAND Flash Memory," IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994, pp. 1366-1373.20The China State Intellectual Property Office, "Office Action," corresponding Chinese Patent Application No. 03825099.3, mailed on Jun. 19, 2009, 11 pages (including translation.).21USPTO, "Notice of Allowance and Fee(s) Due," mailed in related U.S. Appl. No. 10/667,222 on Dec. 30, 2005, 8 pages.22USPTO, "Notice of Allowance and Fee(s) Due," mailed in related U.S. Appl. No. 11/015,199 on Dec. 20, 2005, 11 pages.23USPTO, "Office Action," mailed in related U.S. Appl. No. 10/254,830 on Jul. 12, 2006, 12 pages.24USPTO, "Office Action," mailed in related U.S. Appl. No. 10/254,898 on Apr. 14, 2006, 13 pages.25USPTO, "Office Action," mailed in related U.S. Appl. No. 11/422,034 on Aug. 15, 2006, 11 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8300457Sep 19, 2011Oct 30, 2012Sandisk Technologies Inc.Non-volatile memory and method with reduced neighboring field errorsClassifications U.S. Classification365/185.02, 365/185.24International ClassificationG11C11/34, G11C11/56, G11C16/26, G11C16/34Cooperative ClassificationG11C11/5628, G11C16/3418, G11C16/3454, G11C8/10, G11C8/08, G11C16/3459, G11C16/26European ClassificationG11C8/10, G11C16/34V4, G11C8/08, G11C16/26, G11C11/56D2, G11C16/34V4CLegal EventsDateCodeEventDescriptionMay 23, 2011ASAssignmentOwner name: SANDISK TECHNOLOGIES INC., TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:026327/0396Effective date: 20110404RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services