Source: https://patents.google.com/patent/US10108049B2/en
Timestamp: 2019-05-22 19:58:48
Document Index: 74870578

Matched Legal Cases: ['art 160', 'art 160', 'art 180', 'art 180', 'art 180', 'Application No. 201010552372', 'Application No. 201010552372', 'Application No. 2013', 'Application No. 10', 'Application No. 10']

US10108049B2 - Gray scale inversion reduction or prevention in liquid crystal displays - Google Patents
Gray scale inversion reduction or prevention in liquid crystal displays Download PDF
US10108049B2
US10108049B2 US12/794,623 US79462310A US10108049B2 US 10108049 B2 US10108049 B2 US 10108049B2 US 79462310 A US79462310 A US 79462310A US 10108049 B2 US10108049 B2 US 10108049B2
US12/794,623
US20110298833A1 (en
2010-06-04 Priority to US12/794,623 priority Critical patent/US10108049B2/en
2010-07-14 Assigned to APPLE INC. reassignment APPLE INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, WEI, ZHONG, JOHN Z., CHEN, CHENG, GETTEMY, SHAWN ROBERT, PARK, YOUNG BAE, DORJGOTOV, ENKHAMGALAN, GE, ZHIBING, XU, MING
2011-12-08 Publication of US20110298833A1 publication Critical patent/US20110298833A1/en
2018-10-23 Publication of US10108049B2 publication Critical patent/US10108049B2/en
Devices and methods related to high-contrast liquid crystal displays (LCDs) are provided. For example, such an electronic device may include an LCD with two liquid crystal alignment layers not symmetric to one another and upper and lower polarizing layers respectively above and below the alignment layers. Light transmittance through the plurality of pixels may increase monotonically with gray scale voltage. The display may operate using a gray scale level 0 voltage higher than a minimum gray scale level 0 voltage capability of the display. Additionally or alternatively, liquid crystal molecular alignment axes of the two alignment layers may be offset from one another by an angle other than a multiple of 180 degrees. Additionally or alternatively, a first polarizing axis of the upper polarizing layer or a second polarizing axis of the lower polarizing layer, or both, may be neither parallel nor perpendicular to one of the liquid crystal molecular alignment axes.
The present disclosure relates generally to liquid crystal display (LCD) panels and, more particularly, to high-contrast LCD panels.
Liquid crystal displays (LCDs) are commonly used as screens or displays for a wide variety of electronic devices, including such consumer electronics as televisions, computers, and handheld devices (e.g., cellular telephones, audio and video players, gaming systems, and so forth). Such LCD devices typically provide a flat display in a relatively thin package that is suitable for use in a variety of electronic goods. In addition, such LCD devices typically use less power than comparable display technologies, making them suitable for use in battery-powered devices or in other contexts were it is desirable to minimize power usage.
LCD devices typically include a plurality of picture elements (pixels) arranged in a matrix to display an image. Individual pixels of an LCD device may variably permit light to pass when an electric field is applied to a liquid crystal material in each pixel. This electric field may be generated by a voltage difference between a pixel electrode and a common electrode. The voltage that is applied to the pixel electrode that causes the pixel to transmit the least amount of light may be referred to as a gray scale level 0 voltage (G0). As gray scale level voltages increase beyond G0, the liquid crystal material should gradually allow more light to pass through the pixel. In some cases, however, as the gray scale level voltages increase beyond G0, the amount of light passing through the pixel may at first decrease, in a condition known as gray scale inversion or gray inversion. The condition of gray inversion in LCD panels may reduce contrast and produce image artifacts at low gray scale voltage levels.
Embodiments of the present disclosure relate to devices and methods related to high-contrast liquid crystal displays (LCDs). For example, such an electronic device may include an LCD with two liquid crystal alignment layers not symmetric to one another and upper and lower polarizing layers respectively above and below the alignment layers. Light transmittance through the plurality of pixels may increase monotonically with gray scale voltage. The display may operate using a gray scale level 0 voltage higher than a minimum gray scale level 0 voltage capability of the display. Additionally or alternatively, liquid crystal molecular alignment axes of the two alignment layers may be offset from one another by an angle other than a multiple of 180 degrees. Additionally or alternatively, a first polarizing axis of the upper polarizing layer or a second polarizing axis of the lower polarizing layer, or both, may be neither parallel nor perpendicular to one of the liquid crystal molecular alignment axes.
FIG. 5 is an exploded view of exemplary layers of a pixel of a liquid crystal display (LCD) panel, in accordance with aspects of the present disclosure;
FIG. 6 is a schematic diagram of a portion of an LCD pixel, in accordance with aspects of the present disclosure;
FIG. 7 is a plot modeling liquid crystal director distortion as a function of depth away from pixel electrodes in the pixel, in accordance with aspects of the present disclosure;
FIG. 8 is a plot modeling transmittance of a pixel as a function of voltage, in accordance with aspects of the present disclosure;
FIGS. 9 and 10 are flowcharts describing embodiments of methods for enabling a high contrast LCD panel by selecting a gray level 0 voltage near to a transmittance minimum;
FIG. 11 is a schematic diagram of a pixel having polarizer offset from the liquid crystal molecular alignment axis to improve monotonicity of gray level voltages, in accordance with aspects of the present disclosure;
FIG. 12 is a schematic diagram of a pixel having offset top and bottom liquid crystal molecular alignment axis to improve monotonicity of gray level voltages, in accordance with aspects of the present disclosure; and
FIG. 13 is a plot modeling the transmittance of a pixel of FIG. 11 or 12 as a function of gray level voltage, in accordance with aspects of the present disclosure.
Present embodiments relate to a high-contrast liquid crystal display (LCD) panel. In particular, the development, production, and/or use of such a high-contrast LCD panel may include setting a gray level zero (G0) of the LCD panel to a voltage that causes a transmittance minimum. Additionally or alternatively, the axis of a top or bottom polarizing layer may be offset from a liquid crystal molecular alignment axis of one or both alignment layers of the LCD panel, rather than be parallel or perpendicular to the liquid crystal molecular alignment axis. The term “liquid crystal molecular alignment axis” may also be referred to as a “rubbing axis” or “director axis” and, as used herein, generally refers to an angle that an alignment layer would cause liquid crystal molecules to align with if the alignment layer were planar, in the absence of an electric field. In some embodiments, the top and bottom liquid crystal molecular alignment axes of the liquid crystal alignment layers even may be offset from one another to cause the liquid crystal director to more effectively exclude light at low gray level voltages. These embodiments, alone or in combination, may cause pixels of the LCD panel to monotonically increase (e.g., to increase without decreasing) light transmittance as gray level voltages increase, reducing gray inversion (e.g., when low gray scale level voltages cause greater transmittance than higher gray scale level voltages) as well as enhancing on-axis contrast.
As discussed below, it is believed that these embodiments enable a high contrast ratio by accounting for distortion caused by the non-planarity of liquid crystal alignment layers in certain modern LCD panels. This non-planarity may arise when pixel electrodes occupy space beneath one or more of the alignment layers, causing the alignment layers to protrude into space occupied by liquid crystal material. Pixel electrodes may commonly occupy such space in certain in-plane switching/fringe-field switching (IPS/FFS) LCD panels, as may common electrodes for certain other LCD panels.
Typically, high contrast may be achieved when the axes of polarizing layers above and below the pixels are respectively perpendicular and parallel to a liquid crystal molecular alignment axis of an LCD panel or parallel and perpendicular to the liquid crystal molecular alignment axis of an LCD panel, depending on the mode of operation of the LCD panel. However, it is believed that the non-planarity of the alignment layers in certain LCD panels may produce distortion of the liquid crystal material near the site of the protrusions when the top and bottom polarizer axes are perpendicular or parallel to the liquid crystal molecular alignment axis of an LCD panel. This distortion is believed to induce retardation for light polarized along or perpendicular to the liquid crystal molecular alignment axis direction, resulting in significant light leakage in the dark state for on-axis light, which may effectively reduce the contrast ratio of the LCD panel if not corrected.
To account for these light leakage artifacts, some embodiments involve performing certain gamma correction to ensure the transmittance of the panel increases monotonically with gray level voltages. These embodiments may involve, for example, determining a voltage that produces a minimum transmittance, and setting the gray level 0 (G0) voltage equal to that minimum transmittance voltage. The embodiments also may involve first selecting default gamma settings and testing certain low gray voltage levels (e.g., G0, G3, and G7) for a gray inversion condition. If a gray inversion condition is detected, a new gamma setting may be selected and the LCD panel again tested for gray inversion at the low gray voltage levels. This pattern may repeat until gray inversion is no longer detected, which may imply that the gray scale level 0 voltage (G0) is near the transmittance minimum of the LCD panel. When the gray scale level 0 voltage (G0) is near the transmittance minimum of the LCD panel, the contrast of the LCD display generally may reach a maximum.
Alternatively or in addition to techniques for selecting the gamma settings of the LCD panel, the LCD panel may be designed such that a top or bottom polarizer axis is offset from the liquid crystal molecular alignment axis of an alignment layer of the LCD panel. It is believed that my offsetting the polarizer axes from the liquid crystal molecular alignment axis, slight distortion caused by the protrusion of the pixel electrodes or common electrodes into the liquid crystal material may be corrected. Similarly, in some embodiments, the liquid crystal molecular alignment axis of the upper alignment layer may be different from the liquid crystal molecular alignment axis of the lower alignment layer. It is believed that offsetting the respective liquid crystal molecular alignment axes of the top and bottom alignment layers may result in a similar correction of the distortion of the LCD panel. Offsetting the polarizer axes and/or liquid crystal molecular alignment axes in the manner described herein is expected to produce a substantially monotonic function of transmittance in relation to gray level voltages.
With the foregoing in mind, FIG. 1 represents a block diagram of an electronic device 10 employing such a high-contrast display 18. Among other things, the electronic device 10 may include processor(s) 12, memory 14, nonvolatile storage 16, the display 18, input structures 20, an input/output (I/O) interface 22, network interface(s) 24, and/or a power source 26. In alternative embodiments, the electronic device 10 may include more or fewer components. The various functional blocks shown in FIG. 1 may include hardware elements (including circuitry), software elements (including computer code stored on a computer-readable medium) or a combination of both hardware and software elements. It should further be noted that FIG. 1 is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in the electronic device 8
The display 18 may be a high-contrast liquid crystal display (LCD), such as provided herein. In particular, despite the non-planar nature of the alignment layers in the display 18, the display 18 may not exhibit or may exhibit less gray scale inversion at low gray level voltages and/or may exhibit high on-axis contrast based on the techniques provided herein. The display 18 also may represent one of the input structures 20. Other input structures 20 may include, for example, keys, buttons, and/or switches. The I/O ports 22 of the electronic device 10 may enable the electronic device 10 to transmit data to and receive data from other electronic devices 10 and/or various peripheral devices, such as external keyboards or mice. The network interface(s) 24 may enable personal area network (PAN) integration (e.g., Bluetooth), local area network (LAN) integration (e.g., Wi-Fi), and/or wide area network (WAN) integration (e.g., cellular 3G or 4G). The power source 26 of the electronic device 10 may be any suitable source of power, such as a rechargeable lithium polymer (Li-poly) battery and/or alternating current (AC) power converter.
For example, in the depicted embodiment, the handheld device 30 is in the form of a cellular telephone that may provide various additional functionalities (such as the ability to take pictures, record audio and/or video, listen to music, play games, and so forth). As discussed with respect to the general electronic device of FIG. 1, the handheld device 30 may allow a user to connect to and communicate through the Internet or through other networks, such as local or wide area networks. The handheld device 30 also may communicate with other devices using short-range connections, such as Bluetooth and/or near field communication (NFC). By way of example, the handheld device 30 may be a model of an iPod® or iPhone® available from Apple Inc. of Cupertino, Calif.
As noted briefly above, the display 18 represented in the embodiments of FIGS. 1-3 may be a liquid crystal display (LCD). FIG. 4 represents a circuit diagram of such a display 18, in accordance with an embodiment. As shown, the display 18 may include an LCD display panel 40 including unit pixels 42 disposed in a pixel array or matrix. In such an array, each unit pixel 42 may be defined by the intersection of rows and columns, represented here by the illustrated gate lines 44 (also referred to as “scanning lines”) and source lines 46 (also referred to as “data lines”), respectively. Only six unit pixels 42 a-42 f are shown for purposes of simplicity. However, it should be understood that in an actual implementation, each source line 46 and gate line 44 may include thousands of such unit pixels 42.
As shown in the present embodiment, each unit pixel 42 includes a thin film transistor (TFT) 48 for switching a data signal stored on a respective pixel electrode 50. In the depicted embodiment, a source 52 of each TFT 48 may be electrically connected to a source line 46 and a gate 54 of each TFT 48 may be electrically connected to a gate line 44. A drain 56 of each TFT 48 may be electrically connected to a respective pixel electrode 50. Each TFT 48 serves as a switching element which may be activated and deactivated (e.g., turned on and off) for a predetermined period based upon the respective presence or absence of a scanning signal at the gate 54 of the TFT 48.
When activated, the TFT 48 may store the image signals received via a respective source line 46 as a charge upon its corresponding pixel electrode 50. The image signals stored by the pixel electrode 50 may be used to generate an electrical field between the respective pixel electrode 50 and a common electrode (not shown in FIG. 5). The electrical field between the respective pixel electrode 50 and the common electrode may alter the polarity of a liquid crystal layer above the unit pixel 42. The electrical field may align liquid crystals molecules within the liquid crystal layer to modulate light transmission. As the electrical field changes, the amount of light may increase or decrease. In general, light may pass through the unit pixel 42 at an intensity corresponding to the applied voltage (e.g., from a corresponding source line 46). As will be discussed below, however, an asymmetry between top and bottom liquid crystal alignment layers is believed to cause some distortion that may adversely impact this relationship between the voltage of the pixel electrode 50 and the transmittance of the pixel 42.
The display 18 also may include a source driver integrated circuit (IC) 58, which may include a chip, such as a processor or ASIC, that controls the display panel 40 by receiving image data 60 from the processor(s) 12 and sending corresponding image signals to the unit pixels 42 of the panel 40. The source driver IC 58 also may couple to a gate driver IC 62 that may activate or deactivate rows of unit pixels 42 via the gate lines 44. As such, the source driver IC 58 may send timing information, shown here by reference number 64, to gate driver IC 62 to facilitate activation/deactivation of individual rows of pixels 42. In other embodiments, timing information may be provided to the gate driver IC 62 in some other manner.
In operation, the source driver IC 58 receives the image data 60 from the processor(s) 12 or a separate display controller and, based on the received data, outputs signals to control the pixels 42. For instance, to display image data 60, the source driver IC 58 may adjust the voltage of the pixel electrodes 50 one row at a time. To access an individual row of pixels 42, the gate driver IC 62 may send an activation signal (e.g., an activation voltage) to the TFTs 48 associated with the row of pixels 42, rendering the TFTs 48 of the addressed row conductive. The source driver IC 58 may transmit certain data signals to the unit pixels 42 of the addressed row via respective source lines 46. Thereafter, the gate driver IC 62 may deactivate the TFTs 48 in the addressed row by applying a deactivation signal (e.g., a lower voltage than the activation voltage, such as ground), thereby impeding the pixels 42 within that row from changing state until the next time they are addressed. The above-described process may be repeated for each row of pixels 42 in the panel 40 to reproduce image data 60 as a viewable image on the display 18.
The pixels 42 of the display 18 may include a number of layers, many of which are schematically illustrated in exploded view in FIG. 5. Each pixel 42 may include an upper polarizing layer 66 and a lower polarizing layer 68 to polarize light from a backlight assembly 70 or a light-reflective surface. A lower substrate 72 may be disposed above the polarizing layer 68 and is generally formed from a light-transparent material, such as glass, quartz, and/or plastic.
A thin film transistor (TFT) layer 74 is depicted as being disposed above the lower substrate 72. For simplicity of illustration, the TFT layer 74 is depicted as a generalized structure in FIG. 5. In practice, the TFT layer 74 may itself comprise various conductive, non-conductive, and semiconductive layers and structures which generally form the electrical devices and pathways which drive operation of the pixel 42. For example, in an embodiment in which the pixel 42 is part of an IPS/FFS LCD panel, the TFT layer 74 may include the respective data lines, scanning lines, pixel electrodes, and common electrodes (as well as other conductive traces and structures) of the pixel 42. Such conductive structures may, in light-transmissive portions of the pixel, be formed using transparent conductive materials, such as indium tin oxide (ITO). In addition, the TFT layer 74 may include insulating layers (such as a gate insulating film) formed from suitable transparent materials (such as silicon oxide) and semiconductive layers formed from suitable semiconductor materials (such as amorphous silicon). In general, the respective conductive structures and traces, insulating structures, and semiconductor structures may be suitably disposed to form the respective pixel and common electrodes, a TFT, and the respective data and scanning lines used to operate the pixel 42, as discussed above with reference to FIG. 4.
A lower alignment layer 76 and an upper alignment layer 82 of polyimide (PI) or other suitable materials may generally align molecules of a liquid crystal layer 78 to their liquid crystal molecular alignment axes in the absence of an electric field. The liquid crystal molecular alignment axes of the lower alignment layer 76 and the upper alignment layer 82 may be formed in any suitable manner. For example, the liquid crystal molecular alignment axes may be formed by rubbing the lower alignment layer 76 and/or the upper alignment layer 82 with fiber cloth, using polarized ultraviolet (UV) light to generate photo alignment on the lower alignment layer 76 and/or the upper alignment layer 82, and/or using a lower alignment layer 76 and/or upper alignment layer 82 of obliquely deposited inorganic materials such as silicon oxide (SiOx) or diamond-like carbon.
In the presence of an electric field between the pixel electrode 50 and a common electrode, the liquid crystal particles of the liquid crystal layer 78 may be oriented or aligned in directions other than the liquid crystal molecular alignment axes. The orientation of the liquid crystal particles of the liquid crystal layer 78 may cause the light passing through the liquid crystal layer 78 to become polarized in a manner that allows the light to pass through the upper polarizing layer 66. Thus, modulating the electrical field applied to liquid crystal layer 78 may modulate the amount of light transmitted though the pixel 42.
The lower alignment layer 76 and the upper alignment layer 82 may not be perfectly symmetric. The asymmetry between the lower alignment layer 76 and the upper alignment layer 82 is believed to produce some distortion of the liquid crystal molecules, which may cause gray scale inversion at low voltages. To account for this asymmetry, in some embodiments, the gray scale level voltage 0 (G0) may be selected to be higher than a minimum device voltage, which may prevent gray scale inversion and increase contrast. Additionally or alternatively, in some embodiments, the axes of the polarizing layers 66 and 68 may not be exactly parallel or perpendicular to the liquid crystal molecular alignment axes of the lower alignment layer 76 and the upper alignment layer 82, but rather may be offset by an amount sufficient to reduce or eliminate gray scale inversion and increase contrast. In some embodiments, the liquid crystal molecular alignment axes of the lower alignment layer 76 and the upper alignment layer 82 may be offset from another by a certain amount sufficient to reduce or eliminate gray scale inversion and increase contrast.
An overlying color filter 86 may be a red, green, or blue filter, such that the pixel 42 corresponds to a primary color when light is transmitted from the backlight assembly 70 through liquid crystal layer 78. The color filter 86 may be surrounded by a light-opaque mask or matrix, e.g., a black mask 88, which may circumscribe the light-transmissive portion of the pixel 42. For example, in certain embodiments, the black mask 88 may be sized and shaped to define a light-transmissive aperture over the liquid crystal layer 78 and around the color filter 86 and to cover or mask portions of the pixel 42 that do not transmit light, such as the scanning line and data line driving circuitry, the TFT, and/or the periphery of the pixel 42. In the depicted embodiment, an upper substrate 92 may be disposed between the black mask 88 and color filter 86 and the polarizing layer 66. In such an embodiment, the upper substrate 92 may be formed from light-transmissive glass, quartz, and/or plastic.
As mentioned above, it is believed that were the surfaces of the lower alignment layer 76 and the upper alignment layer 82 both flat and/or symmetric, the least light transmittance of the pixel 42 should occur in the absence of an electric field and when the axes of the upper polarizing layer 66 and the lower polarizing layer 68 are parallel and perpendicular or perpendicular and parallel, respectively, to the liquid crystal molecular alignment axes of the lower alignment layer 76 and the upper alignment layer 82 (depending on the mode of operation of the display 18). However, as shown by a pixel selection 100 of FIG. 6, which represents a portion of a pixel 42, the lower alignment layer 76 and/or the upper alignment layer 82 may be neither symmetric nor flat.
The pixel selection 100 may represent a slice of a pixel 42 from the TFT layer 74 to the black mask layer 88. Specifically, FIG. 6 may illustrate both a side view A and a top view B of the pixel selection 100. As visible in the side view A of FIG. 6, the TFT layer 74 may include a glass substrate 102, a common electrode 104, and fingers of a pixel electrode 50. The fingers of the pixel electrode 50 may cause protrusions 108 of the lower alignment layer 76 into the liquid crystal material 78. As discussed below, these protrusions 108 and the resulting asymmetry between the lower alignment layer 76 and the upper alignment layer 82 are believed to impact the manner in which light is transmitted through the pixel 42.
A liquid crystal molecular alignment axis 110 of the lower alignment layer 76 and/or of the upper alignment layer 82 may generally align certain molecules of the liquid crystal layer 78. In some embodiments, the liquid crystal molecular alignment axis 110 of both the lower alignment layer 76 and the upper alignment layer 82 may be the same or offset from one another by 180°. In other embodiments, the liquid crystal molecular alignment axis 110 of the lower alignment layer 76 may be offset slightly from that of the upper alignment layer 82. Any suitable method may be used to determine the liquid crystal molecular alignment axis 110, which may be set, for example, at an angle of 83°. Depending on design constraints, the liquid crystal molecular alignment axis 110 may be at a different angle. The liquid crystal molecular alignment axis 110, also referred to herein as an alignment axis, may generally cause the liquid crystal molecules of the liquid crystal layer 78 to become aligned in the liquid crystal molecular alignment axis 110 direction.
However, it is believed that the actual alignment direction of these liquid crystal layer 78 molecules may not precisely match the liquid crystal molecular alignment axis 110 of a non-planar alignment layer, such as the lower alignment layer 76 having the protrusions 108. In particular, it is believed that the presence of the protrusions 108 into the liquid crystal material 78 may cause certain distortions near the pixel electrodes 106. A similar effect could be expected if other protrusions 108 were present in the display 18 as caused by other configurations (e.g., a common electrode 104 beneath the lower or upper alignment layers 76 or 82 and/or a pixel electrode 50 beneath the upper alignment layer 82).
As modeled in a plot 120 of FIG. 7, it is believed that when the lower alignment layer 76 includes protrusions 108 due to the fingers of the pixel electrodes 50 but the upper alignment layer 82 remains planar, the liquid crystal director (unit vector alignment direction) of the liquid crystal layer 78 may deviate slightly from the liquid crystal molecular alignment axis 110 nearer to the site of the protrusions 108. In the plot 120, an ordinate 122 represents the liquid crystal director azimuthal angle in units of degrees, and an abscissa 124 represents depth of the liquid crystal material in units of micrometers (μm) from the lower alignment layer 76 to the upper alignment layer 82. From the plot 120, an azimuthal angle of the liquid crystal director within a pixel cavity may be seen to deviate more from the liquid crystal molecular alignment axis 110 angle at lower depths (nearer to the locations of the deviations 108) and to align more to the liquid crystal molecular alignment axis 110 at higher depths.
A curve 126 represents the azimuthal angle of the liquid crystal director of the liquid crystal layer 78 at a location along the x-direction of the pixel selection 100 at or near the pixel electrode 50 fingers. A curve 128 represents the azimuthal angle of the liquid crystal director of the liquid crystal layer 78 at a location along the x-direction of the pixel selection 100 away from the pixel electrode 50 fingers. At depths closer to the lower alignment layer 76, which is non-planar because of the protrusions 108, the liquid crystal director azimuthal angle may increase to more than 84°, or more than one degree higher than the angle of the liquid crystal molecular alignment axis 110, which is here shown as 83°. At depths closer to the upper alignment layer 82, which is planar, the liquid crystal director azimuthal angle may converge to the angle of the liquid crystal molecular alignment axis 110, here shown as 83°.
Comparing the curve 126 to the curve 128 further suggests that the protrusions 108 are responsible for the deviation of the liquid crystal director azimuthal angle from the angle of the liquid crystal molecular alignment axis 110. In particular, it should be recalled that the curve 126 represents a location in the x-direction in the liquid crystal layer 78 that is near to the protrusions 108 and the curve 128 represents a location in the x-direction in the liquid crystal layer 78 that is further from the protrusions 108. The modeled liquid crystal director azimuthal angle is shown to deviate more in the curve 126 (nearer to the protrusions 108) than the curve 128 (further from the protrusions 108).
These deviations in the liquid crystal director azimuthal angle are believed to induce retardation for light polarized along or perpendicular to the liquid crystal molecular alignment axis 110 direction, causing significant light leakage in the dark state for on-axis light. Regardless of the cause, certain LCD panels may exhibit gray inversion of a manner illustrated in FIG. 8. That is, as shown by a plot 140 of FIG. 8 modeling transmittance through a pixel 42 as a function of gray scale voltage, such transmittance may initially drop as a function of voltage instead of increasing monotonically. This gray inversion effect may also result in reduced contrast because the lowest gray level voltages would allow for greater transmittance than a true transmittance minimum through the pixel 42.
The plot 140 includes an ordinate 142 representing transmittance in units of absorbance units (AU) and an abscissa 144 representing gray scale voltage in units of volts (V). In the plot 140, the abscissa 144 is modeled as beginning at 0V because the display 18 is modeled as being capable of supplying 0V to the pixel electrodes 50. However, it should be understood that other embodiments may have other minimum voltages that such other embodiments may be capable of providing.
A curve 146 represents transmittance through a pixel 42 as a function of the gray scale voltage. As can be seen, gray inversion 148 takes place as the voltage initially increases from the minimum voltage the display 18 is capable of providing. At a point 150, the transmittance reaches a true transmittance minimum before the transmittances begins to increase monotonically. This gray inversion 148 may be problematic because pixels 42 of the display 18 at a given gray scale level voltage may be lighter than pixels 42 at a higher gray scale level voltage (e.g., G0 may be lighter than G3).
The gray inversion 148 may also impact the contrast ratio of the display 18, as the lowest gray scale level voltage may not be set to the true transmittance minimum 150 of the display 18. As such, FIGS. 9 and 10 present flowcharts of embodiments of methods for producing a high-contrast display 18 by selecting a gray scale level 0 voltage (G0) at a point at or near the true transmittance minimum 150. Thus, the transmittance of the display 18 may increase monotonically with the gray scale level voltages.
Turning to FIG. 9, a flowchart 160 represents an embodiment of a method for selecting a gray scale level 0 voltage (G0) that results in a high-contrast for the display 18. The flowchart 160 may begin when an initial voltage is applied to pixel electrodes 50 of pixels 42 of the display 18 (block 162). The resulting transmittance of these pixels may be tested using any suitable light metering device (block 164). The voltage currently applied to the pixel electrodes 50 may be increased (block 166) before the transmittance of the pixels 42 is tested once more (block 168).
Next, the transmittances associated with the original and increased voltages may be compared, and if the transmittance is not increasing with voltage (decision block 170), it may be understood that gray inversion is occurring. Thus, the voltage applied to the pixel electrodes 50 may again be increased (block 166) and the transmittance of the pixels 42 may be tested once more (block 168). This process may repeat until the transmittance is no longer increasing (decision block 170), at which point it may be understood that the previous voltage may approximate the true transmittance minimum 150. Also, it may be understood that the transmittance as a function of the voltage applied to the pixel electrodes 50 may be monotonic from that voltage forward. Thus, the gray scale level 0 voltage (G0) may be set equal to that previous voltage.
Another manner of determining the gray scale level 0 voltage (G0) may involve testing one or more defined gamma settings for gray scale inversion. As shown by a flowchart 180 of FIG. 10, the display 18 may be calibrated first by causing the display 18 to operate according to a default gamma setting (block 182). This default gamma setting may define the various gray scale level voltages (e.g., for an 8-bit gray scale, G0-G255). Then, certain low gray scale level voltages may be applied to the pixel electrodes 50 of pixels 42 of the display 18 and the resulting transmittances tested. For example, the G0, G3, and G7 voltages may be applied to pixel electrodes 50 of the pixels 42 of the display 18, and transmittances that result may be tested in any suitable manner (blocks 184-194).
If the G3 voltage produces a lower transmittance than the G0 voltage or the G7 voltage produces a lower transmittance than the G0 or G3 voltage, the display 18 may be exhibiting gray inversion, presumably for the reasons discussed above. If such gray inversion is determined to be occurring (decision block 196), a new gamma setting for the display 18 may instead be selected (block 198). Such a new gamma setting generally may involve a value of the gray scale level 0 voltage (G0) higher than the G0 of the previous gamma setting. Indeed, the increased voltage may equal or exceed 0.2 V, and in some cases, may equal or exceed 0.3 V (e.g., so as to reach a true transmittance minimum 150 as in FIG. 7).
Having selected a new gamma setting, certain low gray scale level voltages again may be applied to the pixel electrodes 50 of pixels 42 of the display 18 and the resulting transmittances tested (blocks 184-194). If gray inversion is still occurring (decision block 196), still another gamma setting may be selected (block 198). This process may repeat until gray inversion is no longer occurring (decision block 196), in which case the flowchart 180 may end 200. When the flowchart 180 ends 200, the selected gamma setting may produce a monotonic gray scale without gray scale inversion.
While the techniques discussed above with reference to FIGS. 9 and 10 may correct for gray scale inversion occurring in the display 18, the embodiments disclosed below may reduce such gray scale inversion or prevent it from occurring in the first place, as well as improve on-axis contrast. As noted above, it is widely accepted as conventional knowledge that the polarizing layers 66 and 68 should be respectively parallel or perpendicular to the liquid crystal molecular alignment axis 110, depending on the mode of operation of the display 18. However, the inventors propose that this conventional knowledge is incorrect. Indeed, as discussed further below, the inventors propose that on-axis contrast may be improved and/or gray scale inversion reduced or eliminated by offsetting the axis of the upper polarizing layers 66 and/or the axis of the lower polarizing layer 68 by some angle from the liquid crystal molecular alignment axis 110 of the lower and upper alignment layers 76 and 82. Additionally or alternatively, some embodiments may involve offsetting the liquid crystal molecular alignment axis 110 of the lower alignment layer 76 from the liquid crystal molecular alignment axis 110 of the upper alignment layer 82 by some angle. It is believed that offsetting the axes of the polarizing layers 66 and/or 68 and/or liquid crystal molecular alignment axes 110 may account for distortion that may result from the non-planar nature of the lower alignment layer 76 (e.g., as caused the protrusions 108).
Specifically, the surface topography of the lower alignment layer 76 is non-planar, and thus asymmetric with the upper alignment layer 82, because of the protrusions 108 caused by the fingers of the pixel electrode 50. As a result of this asymmetric alignment condition, the liquid crystal director of the liquid crystal layer 78 is believed not to be uniformly aligned along the liquid crystal molecular alignment axis 110 throughout the pixel 42, but rather may deviate from top to bottom as it approaches the pixel electrode 50 (e.g., as modeled in FIG. 6). These deviations are believed to induce retardation for light polarized along or perpendicular to the liquid crystal molecular alignment axis 110 direction. Since, for example, linearly polarized propagating through a slightly twisted liquid crystal structure could experience phase retardation and become elliptically polarized, such light passing through an uncorrected pixel 42 may escape the upper polarizing layer 66. Although this effect may be very small, it should be noted that the dark state transmittance of the gray scale level 0 voltage (G0) is also very small, and even the smallest changes could reduce the contrast ratio significantly. In such cases, the techniques of FIGS. 9 and 10 alone may reduce or eliminate gray inversion, but may not be able to maximize the on-axis contrast ratio.
Accordingly, as shown in FIG. 11, the axis of the upper polarizing layer 66 and/or the axis of the lower polarizing layer 68 may be offset slightly from their conventional perpendicular or parallel configuration with the liquid crystal molecular alignment axis 110. Specifically, the liquid crystal molecular alignment axis 110 may be determined using any suitable method. Here, the liquid crystal molecular alignment axis 110 has been determined to be 83°. One or both of the upper and lower polarizing layer 66 and/or 68 axes then may be offset from their conventional configuration relative to the liquid crystal molecular alignment axis 110.
For example, FIG. 11 represents an O-mode configuration, in which the axis 204 of the lower polarizing layer 68 may be offset from being parallel to the liquid crystal molecular alignment axis 110 by a certain amount, and may be determined through experimentation and/or simulation, and may represent an angle at which the least amount of light is transmitted through the pixel 42 at the lowest gray scale level voltage the display 18 is capable of providing. In some embodiments, the axis 204 of the lower polarizing layer 68 may be offset by a relatively small amount such as between 0.3° and 1°, but which may be smaller or larger as determined through experimentation and simulation. The angle of the axis 204 may be offset in a direction toward parallel to an axis of the fingers of the pixel electrode 50 (e.g., closer to 90°). As illustrated, the axis 204 of the lower polarizing layer 68 may have an angle of approximately 83.3°.
In some embodiments, rather than be perpendicular 202 with the liquid crystal molecular alignment axis 110, the axis 206 of the upper polarizing layer 66 may also be offset from being perpendicular 202 with the liquid crystal molecular alignment axis 110. The offset angle of the axis 206 may be determined through experimentation and/or simulation, and may represent an angle at which the least amount of light is transmitted through the pixel 42 at the lowest gray scale level voltage the display 18 is capable of providing. In some embodiments, the axis 206 of the upper polarizing layer 66 may be offset by a relatively small amount such as between 0.3° and 1°, but which may be smaller or larger as determined through experimentation and simulation. The angle of the axis 206 may be offset in a direction toward perpendicular to an axis of the fingers of the pixel electrode 50 (e.g., closer to 0°). As illustrated, the axis 204 of the lower polarizing layer 68 may have an angle of approximately −16.7°. While the offset angles of the axes 204 and 206 are illustrated as being the same, in some embodiments, the offset angles may be different based on experimentation and simulation.
In the embodiment of FIG. 11, both the axis 204 of the lower polarizing layer 68 and the axis 206 of the upper polarizing layer 66 may be offset from the liquid crystal molecular alignment axis 110. In alternative embodiments, only one of these axes 204 or 206 may be offset from their default configurations depending on the mode of operation (e.g., O-mode or E-mode). Also, while the embodiment of FIG. 11 relates to a configuration for O-mode display 18 operation, other embodiments may relate to configurations for E-mode. For example, the axis 204 of the lower polarizing layer 68 may be offset by some angle from the being perpendicular 202 with the liquid crystal molecular alignment axis 110 by some angle, and/or the axis 206 of the upper polarizing layer 66 may be offset by some angle from being parallel with the liquid crystal molecular alignment axis 110.
In addition or alternatively to the embodiments discussed above with reference to FIGS. 9 and 10 and those discussed above with reference to FIG. associated with FIG. 11, gray scale level inversion may be reduced or eliminated and on-axis contrast may be improved by offsetting the liquid crystal molecular alignment axes 110 of the lower alignment layer 76 and the upper alignment layer 82. As shown in FIG. 12, a lower liquid crystal molecular alignment axis 110A associated with the lower alignment layer 76 may be offset from an upper liquid crystal molecular alignment axis 110B associated with the upper alignment layer 82. In particular, the upper liquid crystal molecular alignment axis 110B, being relatively distant from the protrusions 108 of the lower alignment layer 76, may be determined in any suitable manner. As illustrated in FIG. 12, the angle of the upper liquid crystal molecular alignment axis 110B is approximately 83°. Since FIG. 12 illustrates an O-mode configuration, the axis 204 of the lower polarizing layer 68 is parallel to the upper liquid crystal molecular alignment axis 110B, while the axis 206 of the upper polarizing layer 66 is perpendicular to the upper liquid crystal molecular alignment axis 110B.
The lower liquid crystal molecular alignment axis 110A associated with the lower alignment layer 76 may be offset from the upper liquid crystal molecular alignment axis 110B associated with the upper alignment layer 82 by some angle. In other words, the lower liquid crystal molecular alignment axis 110A is not merely 180° different from the upper liquid crystal molecular alignment axis 110B, but rather may be offset by some angle, e.g., less than or more than a multiple of 180°. The offset angle may be determined by experimentation and/or simulation, and may represent an angle at which the least amount of light is transmitted through the pixel 42 at the lowest gray scale level voltage the display 18 is capable of providing. In some embodiments, the lower liquid crystal molecular alignment axis 110A may be offset from the upper liquid crystal molecular alignment axis 110B by a relatively small amount, such as between 0.3° and 1°. This offset angle may be smaller or larger, depending the results of experimentation and/or simulation. In some embodiments, as illustrated by FIG. 12, the lower liquid crystal molecular alignment axis 110A may be offset from the upper liquid crystal molecular alignment axis 110B in a direction toward perpendicular to an axis of the fingers of the pixel electrode 50 (e.g., closer to 0°). As illustrated, lower liquid crystal molecular alignment axis 110A may have an angle of approximately 82.7°.
While the embodiment of FIG. 12 relates to a configuration for O-mode display 18 operation, other embodiments may relate to configurations for E-mode operation. For example, the axis 204 of the lower polarizing layer 68 may be parallel with the upper liquid crystal molecular alignment axis 110B, and the axis 206 of the upper polarizing layer 66 may be perpendicular to the upper liquid crystal molecular alignment axis 110B.
It should be understood that the embodiments described above with reference to FIGS. 11 and 12 may be combined. That is, one or both of the axes 204 and 206 of the lower and upper polarizing layers 68 and 66 may be offset by some angle from their default configurations with the upper liquid crystal molecular alignment axis 110B, even while the lower liquid crystal molecular alignment axis 110A is offset by some angle from the upper liquid crystal molecular alignment axis 110B.
Depending on the size and effect of the protrusions 108, the embodiments associated with FIGS. 11 and 12 may result in a monotonic function of pixel 42 transmittance and gray scale voltage, represented by a plot 210 of FIG. 13. In the plot 210, an ordinate 212 represents transmittance in units of absorbance units (AU) and an abscissa 214 represents gray scale voltage in units of volts (V). The abscissa 210 is modeled as beginning at 0V because the display 18 is modeled as being capable of supplying 0V to the pixel electrodes 50. However, it should be understood that other embodiments may have other minimum voltages that such other embodiments may be capable of providing.
A curve 216 represents transmittance of light through a pixel 42 as a function of the gray scale voltage. As can be seen from the curve 216, the transmittance as a function of gray scale voltage is substantially monotonic. As such, a true transmittance minimum 218 may begin at the minimum voltage the display 18 is capable of providing. On the other hand, if gray scale inversion does occur in embodiments associated with FIGS. 11 and/or 12, and the transmittance of light through a pixel 42 as a function of gray scale voltage is not monotonic, the gray scale level 0 voltage (G0) may be selected in a manner such as discussed above with reference to FIGS. 9 and 10.
a liquid crystal display having a plurality of pixels with a liquid crystal material disposed between two liquid crystal alignment layers not symmetric to one another, and having upper and lower polarizing layers respectively above and below the two liquid crystal alignment layers, wherein light transmittance through the plurality of pixels increases monotonically as gray scale voltages increase and wherein:
the liquid crystal display is configured to operate using a gray scale level 0 voltage that is higher than a minimum gray scale level 0 voltage capability of the liquid crystal display; or
liquid crystal molecular alignment axes of the two liquid crystal alignment layers are offset from one another by an offset angle other than a multiple of 180 degrees; or
at least one of a first polarizing axis associated with the upper polarizing layer and a second polarizing axis associated with the lower polarizing layer is substantially nonparallel and substantially non-perpendicular to one of the liquid crystal molecular alignment axes of the two liquid crystal alignment layers to prevent or reduce gray scale inversion, wherein gray scale inversion causes light transmittance not to increase monotonically with all gray scale voltages, that would otherwise occur if the at least one of the first polarizing axis and the second polarizing axis were parallel or perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis; or
wherein the at least one of the first polarizing axis and the second polarizing axis substantially non-parallel and substantially non-perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis is offset from being parallel or perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis by an angle configured to cause the pixel to transmit a reduced amount of light in the absence of an electric field than that which would be transmitted by the pixel if both the first polarizing axis and the second polarizing axis were parallel or perpendicular to the first liquid crystal molecular alignment axis and the second liquid crystal molecular alignment axis in the absence of the electric field.
2. The electronic device of claim 1, wherein at least one of the two liquid crystal alignment layers of the liquid crystal display is substantially non-planar.
3. The electronic device of claim 1, wherein a first of the two liquid crystal alignment layers of the liquid crystal display is substantially planar and a second of the two liquid crystal alignment layers of the liquid crystal display is substantially non-planar, wherein a liquid crystal director azimuthal angle of the liquid crystal material is substantially aligned to a first liquid crystal molecular alignment axis associated with the first of the two liquid crystal alignment layers but is misaligned to a second liquid crystal molecular alignment axis associated with the second of the two liquid crystal alignment layers.
a lower polarizing layer configured to polarize light on a first polarizing axis;
a lower liquid crystal alignment layer disposed above the lower polarizing layer and configured to generally align liquid crystal molecules along a first liquid crystal molecular alignment axis in the absence of an electric field;
liquid crystal layer disposed above the lower liquid crystal alignment layer that includes the liquid crystal molecules;
an upper liquid crystal alignment layer disposed above the liquid crystal layer and configured to generally align liquid crystal molecules along a second liquid crystal molecular alignment axis in the absence of an electric field, wherein the second liquid crystal molecular alignment axis is equal to or 180 degrees different from the first liquid crystal molecular alignment axis; and
an upper polarizing layer disposed above the upper liquid crystal alignment layer and configured to polarize light on a second polarizing axis;
wherein at least one of the first polarizing axis and the second polarizing axis is substantially non-parallel and substantially non-perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis to prevent or reduce gray scale inversion, wherein gray scale inversion causes light transmittance not to increase monotonically with all gray scale voltages, that would otherwise occur if the at least one of the first polarizing axis and the second polarizing axis were parallel or perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis,
5. The electronic display of claim 4, wherein the at least one of the first polarizing axis and the second polarizing axis substantially non-parallel and substantially non-perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis is offset from being parallel or perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis by an angle less than five degrees.
6. The electronic display of claim 4, wherein the at least one of the first polarizing axis and the second polarizing axis substantially non-parallel and substantially non-perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis is offset from being parallel or perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis by an angle of greater than 0.3 degrees and less than 1 degree.
7. The electronic display of claim 4, wherein the lower liquid crystal alignment layer comprises protrusions into the liquid crystal layer and wherein, when the liquid crystal display is configured to operate in an O-mode, the first polarizing axis is offset from being parallel to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis in a direction toward being more parallel to the protrusions.
8. The electronic display of claim 4, wherein the lower liquid crystal alignment layer comprises protrusions into the liquid crystal layer and wherein, when the liquid crystal display is configured to operate in an O-mode, the second polarizing axis is offset from being perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis in a direction toward being more perpendicular to the protrusions.
9. The electronic display of claim 4, wherein the lower liquid crystal alignment layer comprises protrusions into the liquid crystal layer and wherein, when the liquid crystal display is configured to operate in an E-mode, the first polarizing axis is offset from being perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis in a direction toward being more perpendicular to the protrusions.
10. The electronic display of claim 4, wherein the lower liquid crystal alignment layer comprises protrusions into the liquid crystal layer and wherein, when the liquid crystal display is configured to operate in an E-mode, the second polarizing axis is offset from being parallel to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis in a direction toward being more parallel to the protrusions.
11. The electronic display of claim 4, wherein the lower liquid crystal alignment layer and the upper liquid crystal alignment layer are asymmetric.
12. A liquid crystal display comprising: a pixel comprising:
a first liquid crystal alignment layer having a first liquid crystal molecular alignment axis;
a second liquid crystal alignment layer having a second liquid crystal molecular alignment axis, wherein the second liquid crystal molecular alignment axis is offset from the first liquid crystal molecular alignment axis by an offset angle other than a multiple of 180 degrees to prevent or reduce gray scale inversion, wherein gray scale inversion causes light transmittance not to increase monotonically with all gray scale voltages, that would otherwise occur if the second liquid crystal molecular alignment axis were not offset from the first liquid crystal molecular alignment axis by an offset angle other than a multiple of 180 degrees; and
a liquid crystal layer disposed between the first liquid crystal alignment layer and the second liquid crystal alignment layer;
wherein the first liquid crystal alignment layer or the second liquid crystal alignment layer, or a combination thereof, are at least partially non-planar, wherein the at least one of the first polarizing axis and the second polarizing axis substantially non-parallel and substantially non-perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis is offset from being parallel or perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis by an angle configured to cause the pixel to transmit a reduced amount of light in the absence of an electric field than that which would be transmitted by the pixel if both the first polarizing axis and the second polarizing axis were parallel or perpendicular to the first liquid crystal molecular alignment axis and the second liquid crystal molecular alignment axis in the absence of the electric field.
13. The display of claim 12, wherein the first liquid crystal alignment layer or the second liquid crystal alignment layer, or a combination thereof, includes a plurality of protrusions into the liquid crystal layer.
14. The display of claim 13, wherein the plurality of protrusions are due to fingers of pixel electrodes or a common electrode beneath the first liquid crystal alignment layer or the second liquid crystal alignment layer, or the combination thereof.
15. The display of claim 12, wherein the first liquid crystal alignment layer is substantially planar and wherein the pixel comprises a first polarizing layer having an axis substantially perpendicular or substantially parallel to the first liquid crystal molecular alignment axis.
16. The display of claim 12, wherein the second liquid crystal molecular alignment axis is offset from the first liquid crystal molecular alignment axis by an angle of less than or equal to 1°.
17. The display of claim 12, wherein the second liquid crystal molecular alignment axis is offset from the first liquid crystal molecular alignment axis by an angle of greater than or equal to 0.3°.
18. A method for manufacturing a liquid crystal display comprising:
providing a lower polarizing layer having a first polarizing axis;
providing a lower liquid crystal alignment layer having a first liquid crystal alignment axis, wherein the lower liquid crystal alignment layer is disposed over the lower polarizing layer;
providing a liquid crystal material disposed over the lower liquid crystal alignment layer;
providing an upper liquid crystal alignment layer having a second liquid crystal alignment axis, wherein the lower liquid crystal alignment layer is disposed over the liquid crystal material; and
providing an upper polarizing layer having a second polarizing axis, wherein the upper polarizing layer is disposed over the upper liquid crystal alignment layer;
the first liquid crystal alignment axis is targeted to form a first offset angle that is substantially non-parallel and non-perpendicular to the first polarizing axis, the second polarizing axis, or both to prevent or reduce gray scale inversion, wherein gray scale inversion causes light transmittance not to increase monotonically with all gray scale voltages, that would otherwise occur if the at least one of the first polarizing axis and the second polarizing axis were parallel or perpendicular to the first liquid crystal molecular alignment axis or the second liquid crystal molecular alignment axis; or
the second liquid crystal alignment axis is targeted to form a second offset angle that is substantially non-parallel and non-perpendicular to the first polarizing axis, the second polarizing axis, or both;
19. A method for manufacturing a liquid crystal display comprising:
providing a polarizing layer having a polarizing axis at a first angle; and
providing a liquid crystal alignment layer, wherein the liquid crystal alignment layer has a molecular alignment axis targeted to a second angle that is substantially non-parallel and non-perpendicular to the first angle to prevent or reduce gray scale inversion, wherein gray scale inversion causes light transmittance not to increase monotonically with all gray scale voltages, that would otherwise occur if the second angle were substantially parallel or perpendicular to the first angle,
US12/794,623 2010-06-04 2010-06-04 Gray scale inversion reduction or prevention in liquid crystal displays Active 2034-05-03 US10108049B2 (en)
US12/794,623 US10108049B2 (en) 2010-06-04 2010-06-04 Gray scale inversion reduction or prevention in liquid crystal displays
PCT/US2010/049513 WO2011152849A1 (en) 2010-06-04 2010-09-20 High contrast liquid crystal display
KR1020127025791A KR101449223B1 (en) 2010-06-04 2010-09-20 High contrast liquid crystal display
EP10757917A EP2539764A1 (en) 2010-06-04 2010-09-20 High contrast liquid crystal display
JP2013511139A JP5807059B2 (en) 2010-06-04 2010-09-20 High-contrast LCD display
TW099132473A TWI444728B (en) 2010-06-04 2010-09-24 High contrast liquid crystal display
CN201010552372.7A CN102135679B (en) 2010-06-04 2010-09-25 Liquid crystal display (LCD) with high contrast and electronic device
CN2010206166879U CN201897674U (en) 2010-06-04 2010-09-25 Electronic device, electronic display and liquid crystal display
US20110298833A1 US20110298833A1 (en) 2011-12-08
US10108049B2 true US10108049B2 (en) 2018-10-23
ID=43531100
US12/794,623 Active 2034-05-03 US10108049B2 (en) 2010-06-04 2010-06-04 Gray scale inversion reduction or prevention in liquid crystal displays
US (1) US10108049B2 (en)
EP (1) EP2539764A1 (en)
JP (1) JP5807059B2 (en)
KR (1) KR101449223B1 (en)
CN (2) CN201897674U (en)
TW (1) TWI444728B (en)
WO (1) WO2011152849A1 (en)
JPH07261152A (en) 1994-03-17 1995-10-13 Hitachi Ltd Liquid crystal display device
JPH1138425A (en) 1997-07-15 1999-02-12 Nec Corp The liquid crystal display device
JP2001290152A (en) 2000-04-06 2001-10-19 Advanced Display Inc Liquid crystal display device
CN1322340A (en) 1999-09-27 2001-11-14 精工爱普生株式会社 Method of driving electrooptic device, driving circuit, electrooptic device, and electronic apparatus
KR20030020153A (en) 2001-09-03 2003-03-08 삼성전자주식회사 Liquid crystal display for wide viewing angle, and driving method thereof
KR20050037243A (en) 2003-10-17 2005-04-21 삼성전자주식회사 Setting method for offset and gain value in liquid crystal display device
US20060050216A1 (en) 2004-09-07 2006-03-09 Kazuhiro Joten Liquid crystal display device
JP2006094328A (en) 2004-09-27 2006-04-06 Seiko Epson Corp Input/output characteristics measuring method of and its device of displaying body, image quality adjustment method of and its device of display device
US20060103795A1 (en) * 2004-11-17 2006-05-18 Nec Lcd Technologies, Ltd. Normally-white twisted-nematic-mode LCD device
US20060114389A1 (en) 2004-11-26 2006-06-01 Innolux Display Corp. In-plane switching liquid crystal display having fast response time
US7095394B2 (en) 2001-12-31 2006-08-22 Lg. Philips Lcd Co., Ltd. Driving device of liquid crystal device and driving method thereof
US20060284898A1 (en) 2005-06-17 2006-12-21 Mitac Technology Corp. Brightness correction method and system utilizing the same
KR20070016853A (en) 2005-08-05 2007-02-08 삼성전자주식회사 Liquid crystal display
KR20070023986A (en) 2005-08-25 2007-03-02 이화여자대학교 산학협력단 Manufacturing method for multi-domain twisted nematic grating of liquid crystal using a polarization interference
JP2007093655A (en) 2005-09-27 2007-04-12 Toyo Piano Seizo Kk Upright piano
US20070121048A1 (en) * 2005-10-28 2007-05-31 Che-Ming Hsu Multi-domain vertically aligned liquid crystal display
CN101038411A (en) 2006-03-14 2007-09-19 Nec液晶技术株式会社 Liquid crystal drive means
US20080143930A1 (en) 2006-12-18 2008-06-19 Hyun Suk Jin Liquid crystal display device and method for manufacturing the same
CN101251685A (en) 2007-02-23 2008-08-27 株式会社日立显示器 The liquid crystal display device
JP2009171192A (en) 2008-01-16 2009-07-30 Sharp Corp Display device and method of adjusting optical gradation characteristic
JP2009265114A (en) 2008-04-21 2009-11-12 Sharp Corp Liquid crystal display device
2010-06-04 US US12/794,623 patent/US10108049B2/en active Active
2010-09-20 KR KR1020127025791A patent/KR101449223B1/en active IP Right Grant
2010-09-20 JP JP2013511139A patent/JP5807059B2/en active Active
2010-09-20 WO PCT/US2010/049513 patent/WO2011152849A1/en active Application Filing
2010-09-20 EP EP10757917A patent/EP2539764A1/en active Pending
2010-09-24 TW TW099132473A patent/TWI444728B/en active
2010-09-25 CN CN2010206166879U patent/CN201897674U/en active IP Right Grant
2010-09-25 CN CN201010552372.7A patent/CN102135679B/en active IP Right Grant
US6987499B2 (en) 2001-06-29 2006-01-17 Nec Lcd Technologies, Ltd. Method for driving liquid crystal display, liquid crystal display device and monitor provided with the same
US7205970B2 (en) 2001-09-03 2007-04-17 Samsung Electronics Co., Ltd. Liquid crystal display for wide viewing angle, and driving method thereof
JP4558263B2 (en) 2001-09-03 2010-10-06 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． The liquid crystal display device and a method of driving the same for the wide viewing angle mode
KR20060051043A (en) 2004-09-07 2006-05-19 도시바 마쯔시따 디스플레이 테크놀로지 컴퍼니, 리미티드 Liquid crystal display device
KR20060052245A (en) 2004-10-29 2006-05-19 치 메이 옵토일렉트로닉스 코포레이션 Multi-domain vertically alignment liquid crystal display panel
US20120057117A1 (en) 2004-10-29 2012-03-08 Wang-Yang Li Multi-domain vertically aligned liquid crystal display
US7804567B2 (en) 2004-11-17 2010-09-28 Nec Lcd Technologies, Ltd. Normally-white twisted-nematic-mode LCD device
US7626667B2 (en) 2005-08-05 2009-12-01 Samsung Electronics Co., Ltd. Liquid crystal display
TW200728819A (en) 2006-01-26 2007-08-01 Chi Mei Optoelectronics Corp Multi-domain vertically alignment liquid crystal display panel
US8269934B2 (en) 2006-12-18 2012-09-18 Lg Display Co., Ltd. Liquid crystal display device with first to third subpixels driven in a TN mode and a fourth subpixel drive in ECB mode
KR20080056403A (en) 2006-12-18 2008-06-23 엘지디스플레이 주식회사 Liquid crystal display device and method of fabricating the same
Chinese Office Action for Chinese Application No. 201010552372.7 dated Feb. 28, 2013; 4 pgs.
Chinese Office Action for Chinese Application No. 201010552372.7 dated Oct. 9, 2013; 7 pgs.
International Search Report and Written Opinion for PCT Application No. PCT/US2010/948513 dated Jun. 29, 2011, 18 pgs.
Japanese Office Action for Japanese Application No. 2013-511139 dated Dec. 20, 2013; 5 pgs.
Korean Office Action for Korean Appiicaton No. 10-2012-7025791 dated Nov. 4, 2013; 7pgs.
Korean Office Action for Korean Application No. 10-2012-7025791 dated Feb. 28, 2013; 6 pgs.
Korean Search Report for Application No. 10-2012-7025791 dated Oct. 11, 2012.
Partial International Search Report for PCT/US2010/049513 dated Mar. 10, 2011, 7 pgs.
JP2013534641A (en) 2013-09-05
CN201897674U (en) 2011-07-13
CN102135679B (en) 2015-02-18
KR101449223B1 (en) 2014-10-08
TWI444728B (en) 2014-07-11
WO2011152849A1 (en) 2011-12-08
KR20120120987A (en) 2012-11-02
CN102135679A (en) 2011-07-27
JP5807059B2 (en) 2015-11-10
US20110298833A1 (en) 2011-12-08
TW201207511A (en) 2012-02-16
EP2539764A1 (en) 2013-01-02
CN101008729A (en) 2007-08-01 Display device, liquid crystal display, and method thereof
CN103852944B (en) 2018-07-13 A liquid crystal display and a manufacturing method
CN103257497B (en) 2016-03-30 Oxide thin film transistor having a reduced load (TFT) display pixel
CN101727226B (en) 2013-10-16 Touch sensing device and method for correcting output thereof
US8325309B2 (en) 2012-12-04 Display having a plurality of driver integrated circuits
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