Source: http://www.google.com/patents/US6349377?ie=ISO-8859-1&dq=U.S.+Patent+No.+4,528,643)
Timestamp: 2014-10-02 06:56:51
Document Index: 254851363

Matched Legal Cases: ['art 310', 'art 310', 'art 310', 'art 310', 'art 510', 'art 510']

Patent US6349377 - Processing device for executing virtual machine instructions that includes ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA processing device is disclosed that includes an instruction memory for storing virtual machine instructions, such as Java byte codes. A processor of the processing device includes a predetermined microcontroller core for executing native instructions from a predetermined set of microcontroller specific...http://www.google.com/patents/US6349377?utm_source=gb-gplus-sharePatent US6349377 - Processing device for executing virtual machine instructions that includes instruction refeeding meansAdvanced Patent SearchPublication numberUS6349377 B1Publication typeGrantApplication numberUS 09/161,848Publication dateFeb 19, 2002Filing dateSep 28, 1998Priority dateOct 2, 1997Fee statusPaidAlso published asDE69820027D1, DE69820027T2, EP0950216A2, EP0950216B1, EP1359501A2, EP1359501A3, US6996703, US20020129225, WO1999018484A2, WO1999018484A3Publication number09161848, 161848, US 6349377 B1, US 6349377B1, US-B1-6349377, US6349377 B1, US6349377B1InventorsMenno M. LindwerOriginal AssigneeU.S. Philips CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (4), Non-Patent Citations (2), Referenced by (34), Classifications (26), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetProcessing device for executing virtual machine instructions that includes instruction refeeding meansUS 6349377 B1Abstract A processing device is disclosed that includes an instruction memory for storing virtual machine instructions, such as Java byte codes. A processor of the processing device includes a predetermined microcontroller core for executing native instructions from a predetermined set of microcontroller specific instructions. The native instructions differ from the virtual machine instructions. The processor may request re-feeding of a plurality of native instructions. For instance, the processor may have a pipeline and/or instruction cache which after an interrupt needs to be re-filled. The processing device includes a pre-processor with a converter for converting at least one virtual machine instruction, fetched from the instruction memory, into at least one native instruction. A feeding means of the pre-processor feeds native instructions to the microcontroller core and re-feeds native instructions in response to the processor requesting re-feeding of a number of native instructions.
FIELD OF THE INVENTION The invention relates to a processing device for executing virtual machine instructions; the processing device comprising: an instruction memory for storing instructions including at least one of the virtual machine instructions; a microcontroller comprising a processor comprising a predetermined microcontroller core for executing native instructions from a predetermined set of microcontroller specific instructions; the native instructions being different from the virtual machine instructions; and a pre-processor comprising: a converter for converting at least one virtual machine instruction, fetched from the instruction memory into at least one native instruction; and feeding means for feeding native instructions to the microcontroller core for execution.
Conventionally, programs expressed in virtual machine instructions are executed by means of software interpretation. The processor (CPU) executes a special interpreter program, where in a loop the processor fetches a virtual machine instruction, decodes it into a sequence of native instructions of the microcontroller core of the processor and executes each native instruction. This technique is slow and requires an additional interpreter program, which can be relatively large. To improve the execution speed, the so-called Just-In-Time (JIT) compilation technique is used. Just before starting execution of software module expressed in virtual machine instructions, the module is compiled to native code (expressed in native machine instructions). In this way, the module needs to be stored twice in addition to the code for the compiler. The additional storage requirements of software interpretation are not desired for embedded systems. Instead it is preferred to use a hardware interpreter. In itself a hardware interpreter is known in the form of a Prolog pre-processor for Warren's abstract instruction set. In the paper �A Prolog pre-processor for Warren's abstract instruction set� by B. Kn�dler and W. Rosenstiel, Microprocessing and Microprogramming 18 (1986) pages 71-81, a pre-processor is described for interpreting programs written in the Prolog programming language on a Motorola 68000 processor (MC68000). A compiler is used to translate the Prolog source program into instructions, which have been defined by Mr. Warren and which are generally used for executing Prolog programs. The set of Warren instructions forms a virtual machine designed for executing Prolog programs. The sequence of Warren instructions resulting from the compilation are executed by the MC68000 with the aid of the pre-processor. After power-on, the MC68000 first performs a booting procedure by executing native MC68000 instructions. At the end of the booting procedure, the MC68000 is ready to initiate the execution of a Prolog program. This is started by jumping to a predetermined address range. The pre-processor is a memory-mapped device, which is mapped to this range. When the pre-processor is addressed it reads a Warren instruction (of the translated Prolog program) from its own RAM, adaptively synthesizes a sequence of MC68000 instructions and constants and sends these directly to the CPU for execution. The MC68000 instructions for each Warren instruction are stored in ROM of the pre-processor. In general, the pre-processor translates one Warren instruction into a sequence of MC68000 instructions. The pre-processor contains its own RAM controller and ROM controller, which generate the addresses for the RAM and ROM of the pre-processor. The RAM controller manages the RAM instruction pointer. Each successive read operation of the MC68000 results in the pre-processor sending the next instruction (and optional constants) of the sequence to the CPU. If the sequence has been completed, a next read operation results in the first instruction of the sequence corresponding to the next Warren instruction of the program being send to the CPU. After an interrupt, a repeated read operation of the CPU results in re-sending the last instruction (and optional constants).
SUMMARY OF THE INVENTION It is an object of the invention to provide a processor device of the kind set forth which is suitable for use with a microcontroller which contains more than one instruction at a time.
BRIEF DESCRIPTION OF THE DRAWING FIG. 1 illustrates four possible architectural options of locating the pre-processor in the processing device;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 illustrates four possible architectural options of locating the pre-processor in the processing device 100. Three main components of the processing device 100, are the microcontroller 110, the instruction memory 120 and the pre-processor 130. In all figures the microcontroller 110 comprises the instruction memory 120 and the pre-processor 130. The processing device 100 is not shown explicitly. By combining all main elements in the microcontroller 110, which preferably is a one-chip device, optimum performance can be achieved. It will be appreciated that, if desired, the instruction memory 120 and/or the pre-processor 130 may be located outside the microcontroller 110, where the microcontroller bus 140 is extended outside the microcontroller 110 and, for instance, coupled to an external bus such as PCI.
The converter 132 is used for converting a virtual machine instruction, fetched from the instruction memory 120, into at least one native instruction. As an example, the Java byte code (a virtual machine instruction) for integer addition (0�60) results in adding the two top elements of the stack, removing the two top elements from the stack and pushing the sum on the stack. This virtual machine instruction may be converted to the following sequence of instructions (native instructions) for a MIPS processor (a 32-bits machine), where $tosp is a register pointing to the first empty location of the stack (above the top of stack):
Preferably, the converter 132 comprises a table for converting a virtual machine instruction to a sequence of native instructions. A one dimensional table may be used, where each cell of the table comprises a sequence of native instructions for one corresponding virtual machine instruction. The cell number may correspond to the value of the corresponding virtual machine instruction. As an example, the sequence of native instructions for the Java integer addition (0�60) may be located in cell 96 (=0�60 in hexadecimal notation). Since the length of the sequence of native instructions may vary considerably for the various virtual instructions, preferably the sequences are located in a one-dimensional table without any explicit cells where the sequences immediately follow each other. Such a translation table 200 is shown in FIG. 2, where the implicit cell boundaries are indicated using dotted lines. In order to be able to locate a sequence for a virtual machine instruction a code index table 210 may be used, which for each virtual machine instruction (VMI 1 to VMI N) indicates the starting point of the corresponding sequence in the translation table 200. For the cell of the translation table 200 which corresponds to VMI 3 the related sequence 220 of native instruction NI 1 to NI M are shown.
f tg =rsp+2; f ao 32 rsp+2; f a1 =rsp+1; rsp+=1 add $(rsp+2), $(rsp+2), $(rsp+1) FIG. 3 illustrates an embodiment according to the invention wherein the pre-processor 130 comprises a feeding memory 300. The feeding memory 300 comprises a part 310 for storing at least n instructions which were last fed to the processor (n being the maximum number of native instructions of which the processor could request re-feeding). In response to the processor 112 requesting re-feeding of a number of instructions, the feeding means 136 re-feeds the requested instructions from the feeding memory 300. Preferably, the feeding memory part 310 has a FIFO function 136. Each time an instruction is fed to the processor 112 for the first time, the instruction is loaded into the part 310 and, if the part 310 is full, the oldest instruction is removed. Advantageously, for a microcontroller with a k-stage pipeline n is equal to or larger than k. Similarly, for a processor with an instruction cache for storing up to h instructions n is equal to or larger than h. If both a k-stage pipeline and an instruction cache for storing up to h instructions, n is preferably equal to or larger than k+h.
FIG. 5 illustrates storing part of the state in the instruction pointer. The pre-processor 130 comprises for at least one virtual machine instruction a corresponding translation table for translating the virtual machine instruction into a sequence of native instructions. The translation table may, for instance, be stored in ROM. The translation table may be a cell 220 of the table described earlier and for which an example is shown in FIG. 2. In this alternative embodiment, the least significant part of the instruction pointer of the processor is used to indicate which of the native instructions (e.g. NI 1 to NI n) in the table is required (i.e. the least-significant part of the instruction pointer acts as a translation table offset indicator). This part may, for instance, be 5-bit wide, allowing for a maximum of 32 native instructions for a virtual machine instruction without using further measures. During normal operation, the processor 112 automatically increments the instruction pointer. Advantageously, the pre-processor 130 does not need to store an own counter, like counter 400, and increment this counter for indicating the native instruction expected to be read next. If the processor requests a re-feeding, the processor 112 will automatically set the instruction pointer to a previous value. In this way also re-feeding can be taken care of automatically. FIG. 5 shows a structure of the instruction pointer 500 of the processor 112, where the least significant part 510, starting at the least significant bit (LSB) is used for the translation table offset indicator. The pre-processor 130 comprises means 540 for extracting the translation table offset indicator 510 from the instruction pointer 500 (this may same involve an XOR operation on the instruction pointer 500 with a predetermined bit mask with �1�-bits at the position of the part 510 and �0�-bits for the other part(s). The extracted part may directly be used as a pointer into the translation table or used as an offset.
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