Source: http://www.google.com/patents/US5796792?dq=5,825,242
Timestamp: 2015-05-05 00:51:29
Document Index: 179467102

Matched Legal Cases: ['art 511', 'art 511', 'art 511', 'art 511', 'art 511', 'arts 511', 'art 511', 'art 511', 'art 511', 'arts 511']

Patent US5796792 - Data identifying device and light receiver using the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA device for identifying input data by using a first clock signal includes a first identifying unit which identifies the input data by using the first clock signal to generate first identified data and generates a first phase-relation determination result by determining whether a phase relation between...http://www.google.com/patents/US5796792?utm_source=gb-gplus-sharePatent US5796792 - Data identifying device and light receiver using the sameAdvanced Patent SearchPublication numberUS5796792 APublication typeGrantApplication numberUS 08/581,158Publication dateAug 18, 1998Filing dateDec 29, 1995Priority dateMar 20, 1995Fee statusLapsedAlso published asUS5923455Publication number08581158, 581158, US 5796792 A, US 5796792A, US-A-5796792, US5796792 A, US5796792AInventorsHiroyuki RokugawaOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (14), Referenced by (4), Classifications (10), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetData identifying device and light receiver using the same
1. A device for identifying input data by using a first clock signal, said device comprising:a first identifying unit which identifies said input data by using said first clock signal to generate first identified data, and generates a first phase-relation determination result indicating whether a phase relation between said input data and said first clock signal is such that an identifiable period of said input data is used in identifying said input data; a delay unit for delaying said input data by a predetermined phase amount to generate delayed input data; a second identifying unit which identifies said delayed input data by using said first clock signal to generate second identified data, and generates a second phase-relation determination result indicating whether a phase relation between said delayed input data and said first clock signal is such that an identifiable period of said delayed input data is used in identifying said delayed input data; a selection unit which selects one of said first identified data and said second identified data based on at least one of said first phase-relation determination result and said second phase-relation determination result. 2. A device for identifying input data by using a first clock signal, said device comprising:a first identifying unit which identifies said input data by using said first clock signal to generate first identified data, and generates a first phase-relation determination result by determining whether a phase relation between said input data and said first clock signal is appropriate; a delay unit for delaying said input data by a predetermined phase amount to generate delayed input data; a second identifying unit which identifies said delayed input data by using said first clock signal to generate second identified data, and generates a second phase-relation determination result by determining whether a phase relation between said delayed input data and said first clock signal is appropriate; a selection unit which selects one of said first identified data and said second identified data based on at least one of said first phase-relation determination result and said second phase-relation determination result; wherein each of said first identifying unit and said second identifying unit includes:an identifying unit which identifies corresponding input data by using said first clock signal to generate corresponding identified data, said corresponding input data being corresponding one of said input data and said delayed input data and said corresponding identified data being a corresponding one of said first identified data and said second identified data; a phase-relation detecting unit which generates a pulse signal based on said corresponding input data and said corresponding identified data, said pulse signal having a position in time indicative of said phase relation; a first phase-relation determining unit which makes a coarse determination of said position by using a second clock signal to generate a first phase relation; a second phase-relation determining unit which makes a fine determination of said position by using a third clock signal having a different phase from that of said second clock signal to generate a second phase relation; and a processing unit which generates a corresponding one of said first phase-relation determination result and said second phase-relation determination result based on said first phase relation, said second phase relation, and said corresponding identified data. 3. The device as claimed in claim 2, wherein said predetermined phase amount is generally half of a pulse width corresponding to one bit of said input data.
4. The device as claimed in claim 3, wherein said second clock signal has a phase difference corresponding to half the pulse width compared to said first clock signal, and said third clock signal has a phase difference corresponding to one fourth the pulse width compared to said second clock signal.
5. The device as claimed in claim 4, wherein each of said first identifying unit and said second identifying unit further comprises:a clock distribution unit which generates said second clock signal and said third clock signal based on said first clock signal; and a phase controlling unit which controls a phase of said third clock signal based on said first phase relation. 6. The device as claimed in claim 5, wherein said clock distribution unit comprises delay means for delaying said first clock signal to generate said second clock signal and said third clock signal.
7. The device as claimed in claim 6, wherein said phase controlling unit comprises change means for passing said third clock signal unchanged or changing a phase of said third clock signal according to said first phase relation.
8. The device as claimed in claim 7, wherein said change means changes said phase of said third clock signal by half the pulse width.
9. The device as claimed in claim 8, wherein each of said delay means and said change means comprises one of a gate device, a fixed delay element, and a flexible delay element.
10. A device for identifying input data by using a first clock signal, said device comprising:a first identifying unit which identifies said input data by using said first clock signal to generate first identified data, and generates a first phase-relation determination result by determining whether a phase relation between said input data and said first clock signal is appropriate; a delay unit for delaying said input data by a predetermined phase amount to generate delayed input data; a second identifying unit which identifies said delayed input data by using said first clock signal to generate second identified data, and generates a second phase-relation determination result by determining whether a phase relation between said delayed input data and said first clock signal is appropriate; a selection unit which selects one of said first identified data and said second identified data based on at least one of said first phase-relation determination result and said second phase-relation determination result; a first synchronism-protection unit counting how many times said first identifying unit generates the same first phase-relation determination result; a second synchronism-protection unit counting how many times said second identifying unit generates the same second phase-relation determination result; and an identified-data-selection-signal processing unit sending said selection unit a signal indicating which one of said first identified data and said second identified should be selected, based on results of counting operations of said first synchronism-protection unit and said second synchronism-protection unit. 11. The device as claimed in claim 10, further comprising:a phase-relation monitoring unit monitoring a change in said phase relation to detect a situation in which a current selection of one of said first identified data and said second identified data by said selection unit becomes inappropriate; and a reset-pulse generating unit which generates a reset pulse upon said phase-relation monitoring unit detecting said situation, said reset pulse resetting said first synchronism-protection unit and said second synchronism-protection unit to restart said counting operations. 12. A device for identifying input data by using a first clock signal, said device comprising:a first identifying unit which identifies said input data by using said first clock signal to generate first identified data, and generates a first phase-relation determination result by determining whether a phase relation between said input data and said first clock signal is appropriate; a delay unit for delaying said input data by a predetermined phase amount to generate delayed input data; a second identifying unit which identifies said delayed input data by using said first clock signal to generate second identified data, and generates a second phase-relation determination result by determining whether a phase relation between said delayed input data and said first clock signal is appropriate; a selection unit which selects one of said first identified data and said second identified data based on at least one of said first phase-relation determination result and said second phase-relation determination result; a phase-relation monitoring unit monitoring a change in said phase relation to detect a situation in which a current selection of one of said first identified data and said second identified data by said selection unit becomes inappropriate; a phase-condition extracting unit extracting a condition in which said first identified data and said second identified data have different timing from each other; and a correction unit correcting timing of one of said first identified data and said second identified data based on said condition, which one is newly selected by said selection unit responding to said situation, so that a transition between said first identified data and said second identified data is made in the absence of duplication of data or loss of data. 13. The device as claimed in claim 2, wherein each of said identifying unit, said phase-relation detecting unit, said first phase-relation determining unit, and said second phase-relation determining unit comprises a discrete logic circuit, and other units comprise gate arrays.
14. The device as claimed in claim 1, wherein said delay unit comprises a discrete logic circuit.
15. The device as claimed in claim 14, wherein said delay unit comprises a variable-delay circuit which can adjust a delay amount.
An automatic-phase-adjustment device 21 shown in FIG. 2 is disclosed in a paper by Peter Cochrane et al. (IEEE Journal on Selected Areas in Communications, Vol. SAC-4, No. 9, December, 1986). The automatic-phase-adjustment device 21 includes an S-R latch circuit 22, a delay unit 23, a differential amplifier 24, a D flip-flop 25, an S-R latch circuit 26, a comparator 27, a voltage-controlled phase shifter 28, and a clock extracting circuit 29. Input data is latched by the S-R latch circuit 22, which generates an output signal having a high level during a time duration corresponding to the delay time of the delay unit 23. This output signal is integrated by a resistance R1 and a capacitor C1, and, then, is applied to one input of the differential amplifier 24. Delayed input signal is applied to the D flip-flop 25 to generate identified data.
Accordingly, it is a general object of the present invention to provide a data identifying device and a light receiver which can satisfy the need described above.
The light receiving unit 42 includes a photodiode 44 as a light receiving element and an equalizer/amplifier unit 45. An optical signal transmitted through an optical fiber (not shown) is converted into an electric signal by the photo-diode 44, and the equalizer/amplifier unit 45 amplifies the electric signal to an identifiable level.
In the first identifying unit 32 (34), a D-FF (D flip-flop) 511 (512) is an identifying part which identifies 0s and 1s in the input data by using a below-described clock signal. Here, a coding scheme of an output signal of the D-FF 511 (512) is determined flexibly, so that a coding scheme of following D-FFs are determined accordingly. Thus, signals having any code scheme can be treated.
A processing unit 551 (552) includes an EXOR (exclusive-OR) gate 561 (562), an AND gate 571 (572), and a D-FF 581 (582), for example. The processing unit 551 (552) processes phase-relation determination results provided from the first and second phase-relation determining units 531 and (532) and 541 (542), and generates information for selecting either one of the identified data from the first identifying unit 32 or from the second identifying unit 34.
A clock distribution unit 591 (592) receives the clock signal CLK0, and distributes the clock signals to the identifying part 511 (512), the phase-relation detecting unit 521 (522), the first phase-relation determining unit 531 (532), the AND gate 571 (572) of the processing unit 551 (552), and a phase controlling unit 601 (602). The clock distribution unit 591 (592) will be described with reference to FIG. 6.
FIG. 5A shows a configuration of the phase-relation detecting unit 521 (522) which includes an inverter 63 and an EXOR gate 64. The inverter 63 receives the input data, and the EXOR gate 64 receives an output of the inverter 63 and an output /Q of the identifying part 511 (512). In this circuit configuration, a high-level output is obtained when the input data is "1" and the output /Q is "0".
FIGS. 6A and 6B are block diagrams of the clock distribution unit 591 (592) of FIG. 4. Each of FIGS. 6A and 6B shows a circuit example of the clock distribution unit 591 (592) and an appropriate circuit among these two may be used.
FIG. 6A shows a configuration of the clock distribution unit 591 (592) which includes a first delay unit 67 and a second delay unit 68. The clock signal CLK0 from the timing extraction unit 43 of FIG. 4 is supplied to the clock distribution unit 591 (592), and a clock signal CLK1 having the same phase as the clock signal CLK0 is provided to a clock node (C) of the identifying part (D-FF) 511 (512) and to the AND gate 571 (572) of the processing unit 551 (552).
FIG. 7A shows a configuration of the phase controlling unit 601 (602) which includes an EXOR 70 receiving two inputs and serving as a delay unit also. The EXOR 70 receives the clock signal CLK3 from the clock distribution unit 591 (592) and the output signal of the first phase-relation determining unit 531 (532), and generates a clock signal CLK4. Thus, the EXOR 70 either passes the clock signal CLK3 provided from the clock distribution unit 591 (592) without making any changes, or inverts (delays, in other words) the clock signal CLK3 before outputting an inverted clock signal, depending on the output signal of the first phase-relation determining unit 531 (532). In this manner, the phase controlling unit 601 (602) controls the phase of the clock signal CLK4 which is provided for the second phase-relation determining unit 541 (542).
FIG. 7B shows a configuration of the phase controlling unit 601 (602) which includes a delay unit 71 and a multiplexer (or selector) 72. The first delay unit 71 is made up from a gate device, or made up from fixed or variable delay elements (passive elements). The delay unit 71 delays the clock signal CLK3 provided from the clock distribution unit 591 (592). Then, based on the output signal of the first phase-relation determining unit 531 (532), the multiplexer 72 selects either the clock signal CLK3 or a clock signal delayed by the delay unit 71 so as to control the phase of the clock signal CLK4, which is provided for the second phase-relation determining unit 541 (542).
FIG. 7C shows a configuration of the phase controlling unit 601 (602) in which an inverter 73 serving as a delay unit replaces the delay unit 71 of FIG. 7B. The rest of the configuration is the same as that of FIG. 7B. The inverter 73 inverts the clock signal CLK3 provided from the clock distribution unit 591 (592). Then, based on the output signal of the first phase-relation determining unit 531 (532), the multiplexer 72 selects either the clock signal CLK3 or an inverted clock signal so as to control the phase of the clock signal CLK4, which is provided for the second phase-relation determining unit 541 (542).
In the following, an operation of the data identifying device 31 of FIG. 4 will be described briefly. The photo-diode 44 of the light receiving unit 42 receives a transmitted light, and a received signal is amplified by the equalizer/amplifier unit 45 to be supplied as the input data to the identifying part 511 (512). The timing extraction unit 43 extracts the clock signal CLK0 from the input data, and provides it to the clock distribution unit 591 (592). Then, the clock distribution unit 591 (592) generates a predetermined number of clock signals (i.e., the clock signals CLK1 through CLK3 in FIG. 4).
The identifying unit 32 (34) identifies the input data by using the clock signal CLK1 which is provided from the clock distribution unit 591 (592). Then, a check is made whether the input data is identified while a predetermined phase relation is kept between the clock signal CLK1 and the input data. The identified data and the result of the check are applied to the selection unit 35. Based on the result of the check, the selection unit 35 selects appropriate identified data from the identified data provided from the first identifying unit 32 and the identified data provided from the second identifying unit 34.
The first phase relation (FIG. 8F) and the second phase relation (FIG. 8H) which are generated by the first phase-relation determining unit 531 and the second phase-relation determining unit 541 respectively, are provided to the EXOR gate 561 of the processing unit 551. The EXOR gate 561 generates a signal (FIG. 8I) which is at a high level when these two input signals are at different levels. The AND gate 571 of the processing unit 551 receives the identified data from the identifying part 511 and the clock signal CLK1 from the clock distribution unit 591 at the same timing as the EXOR gate 561 receives its two inputs. This concurrence of timing is brought about by a time delay of one clock cycle occurring through signal propagation. The AND gate 571 generates a checking clock (FIG. 8J), which is the clock signal CLK1 passed through the AND gate 571 when the identified data from the identifying part 511 is at the high level.
The checking clock (FIG. 8J) is applied to a clock node (C) of the D-FF 581 of the processing unit 551 and the output of the EXOR gate 561 is applied to a data node (D) of the D-FF 581. The D-FF 581 supplies a phase-relation determination result (FIG. 8K) to a set node (S) of the SR-FF 61 of the selection unit 35. In FIG. 8K (and FIG. 8L), hatched areas show time periods in which signal levels are not determined in this example. A reset node (R) of the SR-FF 61 receives another phase-relation determination result from the second identifying unit 34, which will be described later. The multiplexer 62 outputs the identified data (FIG. 8L) when the identified data of the first identifying unit 32 is selected according to an output of the SR-FF 61.
In the same manner, the second phase-relation determining unit 54 obtains the second phase relation by using the phase-relation pulse (FIG. 9D) and the clock signal CLK4 (FIG. 9G) from the phase controlling unit 602. Here, the clock signal CLK4 maintains a predetermined phase difference with the clock signal CLK2, except for a time period when the phase difference is changed according to the signal level of the first phase relation. In this example, the second phase relation becomes the high level as shown in FIG. 9H.
The EXOR gate 562 receives the first and second phase relations (FIG. 9F and 9H, respectively), and generates a pulse (FIG. 9I) during a time period when the first and second phase relations have different signal levels because of a difference in the pulse widths thereof.
At the same time, the AND gate 57 of the processing unit 552 generates the checking clock (FIG. 9J) by using the identified data (FIG. 9C) and the clock signal CLK1 (FIG. 9B). The checking clock (FIG. 9J) is delayed by one clock cycle because of a delay in signal propagation. The D-FF 582 identifies the output of the EXOR gate 562 by using the checking clock (FIG. 9J) to generate the phase-relation determination result (FIG. 9K). Since the first and second phase relations have the same signal level when the checking clock (FIG. 9J) has a rising edge, the phase-relation determination result (FIG. 9K) remains at the low level.
The synchronism-protection circuit 81 (82) includes a first counter 91 and a second counter 92 which correspond to the D-FF 581 (582) of the first (second) identifying unit 32 (34).. The synchronism-protection circuit 81 (82) also includes the AND gates 93 through 95 for applying count signals (output signals Q and /Q of the D-FF 581 (582)) to the first and second counters 91 and 92, and for resetting the same. Also, the synchronism-protection circuit 81 (82) includes an AND gate 96 which generates a signal for stopping a counting operation by using /Q outputs of the first and second counters 91 and 92.
The reset-pulse generating unit 102 includes a D-FF 108, a D-FF 109, and a NOR gate 110 connected in series. The NOR gate 110 receives the /Q output of the D-FF 108 and the Q output of the D-FF 109. The D-FFs 108 and 109 receive at clock nodes (C) thereof the clock signal CLK1 from the clock distribution unit 591 (or 592) An output of the NOR gate 110 is provided to reset nodes (R) of the counters 91 and 92 of the first and second synchronism-protection circuits 81 and 82. Other configuration is the same as that shown in FIG. 11.
The correction unit 112 includes D-FFs 119 through 122 forming two shift-registers, two multiplexers 123 and 124, and three-input AND gates 125 and 126. The D-FFs 119 and 121 receive the identified data from the identifying parts 511 and 512, respectively. The D-FFs 120 and 122 receive output signals of the D-FFs 119 and 121 at a preceding stage, respectively. Clock nodes of the D-FFs 119 through 122 receive the clock signal CLK1 from the clock distribution unit 591 and 592 respectively.
FIGS. 14C and 14D show the identified data output from the identifying part 511 and 512, respectively, when the identifying clock pulse is positioned in the period X. FIGS. 14E and 14F show the identified data output from the identifying part 511 and 512, respectively, when the identifying clock pulse is positioned in the period Y. FIGS. 14G and 14H show the identified data output from the identifying part 511 and 512, respectively, when the identifying clock pulse is positioned in the period Z. In periods X and Z (FIGS. 14C and 14D and FIGS. 14G and 14H, respectively), the identified data is displaced by one bit between the identifying parts 511 and 512. Thus, in the periods X and Z, when a transition of the identified data occurs, a duplication of one bit or loss of one bit will be observed in the output data. In the period Y, there will be no duplication or loss of one bit.
In FIG. 15B, at a step S11, the input data is input. At a step S12, the appropriate identified data is selected by counting up the counters 91 and 92 of the synchronism-protection circuits 81 and 82. At a step S13, the phase-relation monitoring unit 101 is activated when the output of the 4-input OR gate 105 becomes the high level At a step S14, the phase-condition extracting unit 111 is activated. At a step S15, the correction unit 112 is activated. At a step S16, a condition (whether the identified data should be corrected) extracted by the phase-condition extracting unit 111 is applied to the correction unit 112. At a step S17, the correction unit 112 generates the corrected identified data.
Also, according to the present invention, the clock distribution units generate the clock signals having various predetermined phases through delay units such as gate elements and delay elements. Also, the phase controlling unit controls the phase of one of the clock signals. In this manner, the first phase-relation determining unit and the second phase-relation determining unit use the clock signals which have half-the-time-slot phase difference from each other. Thus, a simple circuit structure can select an appropriate phase relation between the input data and the identifying clock.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5022056 *Oct 23, 1989Jun 4, 1991National Semiconductor CorporationMethod and structure for digital phase synchronizationUS5127026 *Apr 5, 1990Jun 30, 1992Gazelle Microcircuits, Inc.Circuit and method for extracting clock signal from a serial data streamUS5197062 *Sep 4, 1991Mar 23, 1993Picklesimer David DMethod and system for simultaneous analysis of multiplexed channelsUS5452323 *Dec 6, 1993Sep 19, 1995Hughes Aircraft CompanySimple asynchronous data synchronizer to a faster clockUS5544203 *Oct 18, 1994Aug 6, 1996Texas Instruments IncorporatedFine resolution digital delay line with coarse and fine adjustment stagesUS5550860 *Apr 11, 1995Aug 27, 1996International Business Machines CorporationDigital phase alignment and integrated multichannel transceiver employing sameUS5553104 *Jun 29, 1994Sep 3, 1996Hitachi, Ltd.Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signalUS5588004 *Mar 17, 1995Dec 24, 1996Hitachi, Ltd.Bus synchronizing method and system based thereonUS5619506 *Apr 27, 1995Apr 8, 1997Adtran, Inc.Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communicationsJPH01188050A * Title not availableJPH01233850A * Title not availableJPH02121431A * Title not availableJPH03293833A * Title not availableJPS62130037A * Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6621312Nov 13, 2001Sep 16, 2003Primarion, Inc.High bandwidth multi-phase clock selector with continuous phase outputEP1049257A2 *Mar 9, 2000Nov 2, 2000Vitesse Semiconductor CorporationPhase selection circuitEP1111817A2 *Dec 20, 2000Jun 27, 2001Nec CorporationOptical communication receiverEP1211605A2 *Oct 23, 2001Jun 5, 2002Robert Bosch GmbhMethod for receiving data* Cited by examinerClassifications U.S. Classification375/354, 370/516, 370/517, 370/518International ClassificationH04L7/00, H04L7/033, H03K5/00, H04L7/027Cooperative ClassificationH04L7/0338European ClassificationH04L7/033E2Legal EventsDateCodeEventDescriptionOct 5, 2010FPExpired due to failure to pay maintenance feeEffective date: 20100818Aug 18, 2010LAPSLapse for failure to pay maintenance feesMar 22, 2010REMIMaintenance fee reminder mailedJan 27, 2006FPAYFee paymentYear of fee payment: 8Jan 24, 2002FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services