Source: http://www.google.com/patents/US7913206?dq=7350717
Timestamp: 2017-04-24 18:27:23
Document Index: 514234427

Matched Legal Cases: ['art 1', 'art 10', 'art 11', 'art 12', 'art 13', 'art 14', 'art 2', 'art 3', 'art 4', 'art 5', 'art 6', 'art 8', 'art 9']

Patent US7913206 - Method and mechanism for performing partitioning of DRC operations - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn improved method and mechanism for data partitioning for a DRC tool is disclosed that efficiently and effectively allows parallelization and multithreading to occur for DRC analysis of the IC design. Data partitioning is performed to allow some of the data to be processed in parallel by distributed...http://www.google.com/patents/US7913206?utm_source=gb-gplus-sharePatent US7913206 - Method and mechanism for performing partitioning of DRC operationsAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7913206 B1Publication typeGrantApplication numberUS 11/228,472Publication dateMar 22, 2011Filing dateSep 15, 2005Priority dateSep 16, 2004Fee statusPaidPublication number11228472, 228472, US 7913206 B1, US 7913206B1, US-B1-7913206, US7913206 B1, US7913206B1InventorsEitan CadouriOriginal AssigneeCadence Design Systems, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (90), Non-Patent Citations (57), Referenced by (7), Classifications (5), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethod and mechanism for performing partitioning of DRC operations
US 7913206 B1Abstract
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5299139Jun 21, 1991Mar 29, 1994Cadence Design Systems, Inc.Short locator methodUS5339415 *Nov 9, 1992Aug 16, 1994Cray Research, Inc.Dual level scheduling of processes to multiple parallel regions of a multi-threaded program on a tightly coupled multiprocessor computer systemUS5440720Sep 20, 1993Aug 8, 1995Cadence Design Systems, Inc.Architecture and method for data reduction in a system for analyzing geometric databasesUS5537329Jun 30, 1994Jul 16, 1996At&T Corp.Apparatus and method for analyzing circuitsUS5559718Apr 28, 1994Sep 24, 1996Cadence Design Systems, Inc.System and method for model-based verification of local design rulesUS5581475Aug 13, 1993Dec 3, 1996Harris CorporationMethod for interactively tailoring topography of integrated circuit layout in accordance with electromigration model-based minimum width metal and contact/via rulesUS5613102Oct 19, 1995Mar 18, 1997Lucent Technologies Inc.Method of compressing data for use in performing VLSI mask layout verificationUS5812415Apr 5, 1996Sep 22, 1998Cadence Design Systems, Inc.Method and apparatus for enhancing performance of design verification systemsUS5828880 *Jul 6, 1995Oct 27, 1998Sun Microsystems, Inc.Pipeline system and method for multiprocessor applications in which each of a plurality of threads execute all steps of a process characterized by normal and parallel steps on a respective datumUS5870313Dec 9, 1997Feb 9, 1999Lsi Logic CorporationOptimization processing for integrated circuit physical design automation system using parallel moving windowsUS6003066 *Aug 14, 1997Dec 14, 1999International Business Machines CorporationSystem for distributing a plurality of threads associated with a process initiating by one data processing station among data processing stationsUS6009250Sep 30, 1997Dec 28, 1999Synopsys, Inc.Selective flattening in layout areas in computer implemented integrated circuit designUS6035107Aug 28, 1997Mar 7, 2000International Bunsiness Machines CorporationMethod for performing functional comparison of combinational circuitsUS6047116Mar 18, 1998Apr 4, 2000Kabushiki Kaisha ToshibaMethod for generating exposure data for lithographic apparatusUS6066179Jun 13, 1997May 23, 2000University Of EdinburghProperty estimation of an integrated circuitUS6185583 *Nov 30, 1998Feb 6, 2001Gte Laboratories IncorporatedParallel rule-based processing of formsUS6237128Oct 6, 1997May 22, 2001International Business Machines CorporationMethod and apparatus for enabling parallel layout checking of designing VLSI-chipsUS6289369 *Aug 25, 1998Sep 11, 2001International Business Machines CorporationAffinity, locality, and load balancing in scheduling user program-level threads for execution by a computer systemUS6324673May 28, 1999Nov 27, 2001Princeton UniversityMethod and apparatus for edge-endpoint-based VLSI design rule checkingUS6389451 *Sep 27, 2000May 14, 2002Pasocs, LlcDistributed digital rule processor for single system image on a clustered network and methodUS6401240 *Aug 7, 1998Jun 4, 2002Hewlett-Packard CompanySystem and method for profiling code on symmetric multiprocessor architecturesUS6505327 *Apr 13, 2001Jan 7, 2003Numerical Technologies, Inc.Generating an instance-based representation of a design hierarchyUS6519749 *May 17, 2000Feb 11, 2003Silicon Perspective CorporationIntegrated circuit partitioning placement and routing systemUS6536028Mar 14, 2000Mar 18, 2003Ammocore Technologies, Inc.Standard block architecture for integrated circuit designUS6560766 *Jul 26, 2001May 6, 2003Numerical Technologies, Inc.Method and apparatus for analyzing a layout using an instance-based representationUS6574788Nov 13, 2000Jun 3, 2003Reshape, Inc.Method and system for automatically generating low level program commands as dependency graphs from high level physical design stagesUS6629293 *Feb 23, 2001Sep 30, 2003Cadence Design Systems, Inc.Block based design methodologyUS6701504 *Jan 4, 2001Mar 2, 2004Cadence Design Systems, Inc.Block based design methodologyUS6721928 *Dec 17, 2002Apr 13, 2004Numerical Technologies, Inc.Verification utilizing instance-based hierarchy managementUS6738954Aug 10, 2000May 18, 2004International Business Machines CorporationMethod for prediction random defect yields of integrated circuits with accuracy and computation time controlsUS6829757Feb 12, 2002Dec 7, 2004Cadence Design Systems, Inc.Method and apparatus for generating multi-layer routesUS6996790 *Jan 30, 2003Feb 7, 2006Synopsys, Inc.System and method for generating a two-dimensional yield map for a full layoutUS7047506Nov 19, 2003May 16, 2006International Business Machines CorporationMethod to identify geometrically non-overlapping optimization partitions for parallel timing closureUS7051307Dec 3, 2003May 23, 2006International Business Machines CorporationAutonomic graphical partitioningUS7089511Dec 10, 2003Aug 8, 2006International Business Machines CorporationFramework for hierarchical VLSI designUS7107559Oct 29, 2003Sep 12, 2006Lsi Logic CorporationMethod of partitioning an integrated circuit design for physical design verificationUS7155698Nov 17, 2003Dec 26, 2006The Regents Of The University Of CaliforniaMethod of locating areas in an image such as a photo mask layout that are sensitive to residual processing effectsUS7177859 *Jun 26, 2002Feb 13, 2007Microsoft CorporationProgramming model for subscription servicesUS7266795 *Mar 17, 2005Sep 4, 2007International Business Machines CorporationSystem and method for engine-controlled case splitting within multiple-engine based verification frameworkUS7318214May 7, 2004Jan 8, 2008Invarium, Inc.System and method for reducing patterning variability in integrated circuit manufacturing through mask layout correctionsUS7340742 *Aug 15, 2002Mar 4, 2008Nec CorporationPriority execution control method in information processing system, apparatus therefor, and programUS7401208 *Apr 25, 2003Jul 15, 2008International Business Machines CorporationMethod and apparatus for randomizing instruction thread interleaving in a multi-thread processorUS7421505 *Jun 1, 2001Sep 2, 2008Noatak Software LlcMethod and system for executing protocol stack instructions to form a packet for causing a computing device to perform an operationUS7500240 *Jan 15, 2002Mar 3, 2009Intel CorporationApparatus and method for scheduling threads in multi-threading processorsUS7526740 *Aug 10, 2006Apr 28, 2009Prophicy Semiconductor, Inc.System and method for automated electronic device designUS20010003843Nov 22, 1999Jun 14, 2001Ranko ScepanovicAdvanced modular cell placement systemUS20020049956Jan 19, 1999Apr 25, 2002Zeki BozkusCell based parallel verification of an integrated circuit designUS20020162085 *Apr 25, 2001Oct 31, 2002Zolotykh Andrej A.Parallelization of resynthesisUS20030012147 *Jul 2, 2001Jan 16, 2003Buckman Charles R.System and method for processing network packet flowsUS20030014471 *Apr 29, 2002Jan 16, 2003Nec CorporationMulti-thread execution method and parallel processor systemUS20030014473 *Jul 8, 2002Jan 16, 2003Nec CorporationMulti-thread executing method and parallel processing systemUS20030018684 *Jul 17, 2002Jan 23, 2003Nec CorporationMulti-thread execution method and parallel processor systemUS20030023939 *Jul 26, 2001Jan 30, 2003Numerical TechnologiesMethod and apparatus for analyzing a layout using an instance-based representationUS20030033509 *Aug 7, 2001Feb 13, 2003Sun Microsystems, Inc.Architectural reuse of registers for out of order simultaneous multi-threadingUS20030037117 *Aug 15, 2002Feb 20, 2003Nec CorporationPriority execution control method in information processing system, apparatus therefor, and programUS20040006584 *Aug 8, 2001Jan 8, 2004Ivo VandeweerdArray of parallel programmable processing engines and deterministic method of operating the sameUS20040015256Jul 19, 2002Jan 22, 2004International Business Machines CorporationFeedback method utilizing lithographic exposure field dimensions to predict process tool overlay settingsUS20040019679 *Jul 24, 2002Jan 29, 2004Sandhya EFirst thread lock management for distributed data systemsUS20040019892 *Jul 24, 2002Jan 29, 2004Sandhya E.Lock management thread pools for distributed data systemsUS20040044979Aug 27, 2002Mar 4, 2004Aji Sandeep A.Constraint-based global router for routing high performance designsUS20040098511 *Nov 16, 2002May 20, 2004Lin David H.Packet routing method and system that routes packets to one of at least two processes based on at least one routing ruleUS20040187112 *Mar 7, 2003Sep 23, 2004Potter Kenneth H.System and method for dynamic ordering in a network processorUS20040199887Nov 7, 2003Oct 7, 2004Jawahar JainDetermining one or more reachable states in a circuit using distributed computing and one or more partitioned data structuresUS20040215932 *Apr 24, 2003Oct 28, 2004International Business Machines CorporationMethod and logical apparatus for managing thread execution in a simultaneous multi-threaded (SMT) processorUS20040215939 *Apr 24, 2003Oct 28, 2004International Business Machines CorporationDynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modesUS20040216101 *Apr 24, 2003Oct 28, 2004International Business Machines CorporationMethod and logical apparatus for managing resource redistribution in a simultaneous multi-threaded (SMT) processorUS20040268354 *Mar 25, 2004Dec 30, 2004Tatsunori KanaiMethod and system for performing real-time operation using processorsUS20050038852 *Sep 9, 2004Feb 17, 2005Howard Kevin D.Massive collective network processing system and methodsUS20050091634Oct 27, 2003Apr 28, 2005International Business Machines CorporationRenesting interaction map into design for efficient long range calculationsUS20050097561 *Nov 3, 2003May 5, 2005Schumacher Larry L.System and method for data transformation using dataflow graphsUS20050102681 *Nov 12, 2003May 12, 2005Richardson John J.Automatic serialization for event driven multi-threaded programs in an object structured systemUS20050132320Dec 10, 2003Jun 16, 2005Allen Robert J.Framework for hierarchical VLSI designUS20050138474Nov 22, 2004Jun 23, 2005Jawahar JainCircuit verification using multiple enginesUS20050166173Mar 17, 2005Jul 28, 2005Synopsys, Inc.Design data format and hierarchy management for processingUS20050216870Mar 26, 2004Sep 29, 2005International Business Machines CorporationIc design density checking method, system and program productUS20050216875Mar 28, 2005Sep 29, 2005Youping ZhangSystem for integrated circuit layout partition and extraction for independent layout processingUS20050262510 *May 12, 2005Nov 24, 2005Ittiam Systems (P) LtdMulti-threaded processing design in architecture with multiple co-processorsUS20060005154Aug 22, 2005Jan 5, 2006Mentor Graphics CorporationIntegrated OPC verification toolUS20060062430 *Oct 13, 2004Mar 23, 2006Vallone Robert PFeed-customized processing of multiple video streams in a pipeline architectureUS20060123420 *Nov 30, 2005Jun 8, 2006Naohiro NishikawaScheduling method, scheduling apparatus and multiprocessor systemUS20060200825 *Apr 3, 2006Sep 7, 2006Potter Kenneth H JrSystem and method for dynamic ordering in a network processorUS20060230370Mar 17, 2005Oct 12, 2006International Business Machines CorporationSystem and method for engine-controlled case splitting within a multiple-engine based verification frameworkUS20060253813May 3, 2005Nov 9, 2006Dan RittmanDesign rule violations check (DRC) of IC's (integrated circuits) mask layout database, via the internet method and computer softwareUS20060265675May 20, 2005Nov 23, 2006Synopsys, Inc.Verifying an IC layout in individual regions and combining resultsUS20070079268Sep 30, 2005Apr 5, 2007Jones Kevin DMixed mode verifierUS20070192545 *Feb 10, 2006Aug 16, 2007International Business Machines CorporationLow complexity speculative multithreading system based on unmodified microprocessor coreUS20070220232 *May 23, 2007Sep 20, 2007John RhoadesData Processing ArchitecturesUS20070233805 *Apr 2, 2006Oct 4, 2007Mentor Graphics Corp.Distribution of parallel operationsUS20070271562 *Nov 3, 2003Nov 22, 2007Schumacher Larry LExecution environment for data transformation applicationsUS20090125867Jan 12, 2009May 14, 2009Synopsys, Inc.Handling Of Flat Data For Phase Processing Including Growing Shapes Within Bins To Identify Clusters* Cited by examinerNon-Patent CitationsReference1 *"Mentor Consulting Helps AMD Win Another Race to Market", 2001, Mentor Graphics Corporation, www.mentor.com, 4 pages.2 *"Mentor Graphics Unveils Calibre MTflex to Combat Cost of Nanometer Design Compute Requirements", May 12, 2003, Mentor Graphics Corporation, www.mentor.com, 2 pages.3Banicescu, I. et al. "Overhead Analysis of a Dynamic Load Balancing Library for Cluster Computing" Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05), 2005.4Bender, M.A. et al. "On-the-Fly Maintenance of Series-Parallel Relationships in Fork-Join Multithreaded Programs" Proceedings of the 16th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Barcelona, Spain, 2004, pp. 133-144.5Cadence Design Systems, Inc. "Assura Layout vs. Schematic Verifier" 2003, 4 pgs., Cadence Design Systems, Inc., San Jose, CA.6Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 1 of 14, pp. 1-49.7Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 10 of 14, pp. 450-499.8Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 11 of 14, pp. 500-549.9Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 12 of 14, pp. 550-599.10Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 13 of 14, pp. 600-629.11Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 14 of 14, pp. 630-658.12Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 2 of 14, pp. 50-99.13Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 3 of 14, pp. 100-149.14Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 4 of 14, pp. 150-199.15Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 5 of 14, pp. 200-249.16Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 6 of 14, pp. 250-299.17Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 8 of 14, pp. 350-399.18Cadence Design Systems, Inc. "Diva Reference" Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 9 of 14, pp. 400-449.19Dongarra, J.J. et al. "LAPACK Working Note 37 Two Dimensional Basic Linear Algebra Communication Subprograms" Technical Report University of Tennessee, 1991.20 *Ferguson, "Calibre Mtflex: Reducing the High Cost of Processing Power", Mar. 2004, Mentor Graphics Corporation, pp. 1-5, www.mentor.com.21Final Office Action date Jan. 21, 2010 for U.S. Appl. No. 11/479,600.22Final Office Action dated Dec. 7, 2009, for U.S. Appl. No. 11/225,853.23Final Office Action dated Feb. 2, 2001 for U.S. Appl. No. 11/225,816.24Final Office Action dated Jan. 2, 2009 for U.S. Appl. No. 11/225,853.25Final Office Action dated Jan. 8, 2009 for U.S. Appl. No. 11/520,487.26Fliesler, M. "Mentor Consulting Helps AMD WIN Another Race to Market", 2001, pp. 1-5, Mentor Graphics Corporation, San Jose, CA.27Kalas, I. et al. "FTL: A Multithreaded Environment for Parallel Computation" Proceedings of the 1994 Conference of the Centre for Advanced Studies on Collaborative Research, Toronto, Ontario, Canada, 1994, pp. 1-12.28Krishnaswamy, V. et al. "Actor Based Parallel VHDL Simulation Using Time Warp" Proceedings of the 10th Workshop on Parallel and Distributed Simulation, 1996, pp. 135-142.29Lee, P.M. et al. "A Parallel and Accelerated Circuit Simulator with Precise Accuracy" Proceedings of the 15th International Conference on VLSI Design (VLSI '02), Bangalore, India, Jan. 7-11, 2002, pp. 1-6.30Magarshack, P. et al. "System-on-Chip Beyond the Nanometer Wall" Proceedings of the 40th Conference on Design Automation (DAC '03), Anaheim, CA, Jun. 2-6, 2003, pp. 419-424.31Mentor Graphics Corporation "Calibre LVS: Precise IC Layout Verification with the Schematic Design", 2005, 4 pgs., Mentor Graphics Corporation, San Jose, CA.32Mohapatra, P. et al. "A Lazy Scheduling Scheme for Hypercube Computers" Journal of Parallel and Distributed Computing 27, 26-27 (1995).33Niewczas, M. et al. "A Pattern Matching Algorithm for Verification and Analysis of Very Large IC Layouts" ISPD 98, Apr. 6-8, 1998, pp. 129-134.34Non-Final Office Action dated Feb. 4, 2010 for U.S. Appl. No. 11/225,816.35Non-Final Office Action dated Nov. 24, 2010 for U.S. Appl. No. 11/479, 600.36Notice of Allowance dated Mar. 11, 2008 for U.S. Appl. No. 11/225,815.37Notice of Allowance dated May 29, 2009 for U.S. Appl. No. 11/520,487.38Notice of Allowance dated Sep. 18, 2009 for U.S. Appl. No. 11/520,487.39Office Action dated Apr. 4, 2008 for U.S. Appl. No. 11/520,487.40Office Action dated Apr. 8, 2008 for U.S. Appl. No. 11/225,816.41Office Action dated Dec. 18, 2008 for U.S. Appl. No. 11/225,816.42Office Action dated Feb. 18, 2009 for U.S. Appl. No. 11/228,472.43Office Action dated Jan. 2, 2009 for U.S. Appl. No. 11/225,853.44Office Action dated Jan. 8, 2009 for U.S. Appl. No. 11/520,487.45Office Action dated Jun. 11, 2008 for U.S. Appl. No. 11/225,853.46Office Action dated Mar. 9, 2007 for U.S. Appl. No. 11/225,853.47Office Action dated Sep. 17, 2007 for U.S. Appl. No. 11/225,815.48Office Action dated Sep. 28, 2007 for U.S. Appl. No. 11/225,816.49Office Action dated Sep. 7, 2007 for U.S. Appl. No. 11/225,853.50Ousterhout J.K. "Corner Stitching: A Data-Structure Technique fro VLSI Layout Tools" IEEE Transactions on Computer Aided-Design of Integrated Circuits and Systems, vol. CAD-3, No. 1, pp. 97-100, Jan. 1984.51Prabhu, A.M. "Management Issues in EDA" Proceedings of the 31st Conference on Design Automation (DAC '94), San Diego, CA, Jun. 6-10, 1994, pp. 41-47.52Saavedra-Barrera, R.H. et al. "Analysis of Multithreaded Architectures for Parallel Computing" Proceedings of the Second Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA '90), Island of Crete, Greece, 1990, pp. 169-178.53Schellenberg, F. "Mask EDA Workshop" Copyright 1999-2001, 47 pgs., Mentor Graphics Corporation, San Jose, CA.54Scherber et al., PALACE: A parallel and hierarchical layout analyzer and cirucite extractor, Mar. 1996, European Design and Test Conference.55Spiller, M.D. et al. "EDA and the Network" Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design (CAD '97), San Jose, CA, 1997, pp. 470-476.56Teo, Y.M. et al. "A compensation-based scheduling scheme for Grid Computing" Proceeding of the 7th International Conference on High Performance Computing and Grid, pp. 334-342, IEEE Computer Society Press, Tokyo, Japan, Jul. 20-22, 2004.57Yoo, S-M. et al. "Largest-Job-First-Scan-All Scheduling Policy for 2D mesh-Connected Systems", IEEE, 1996.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8099693Dec 31, 2008Jan 17, 2012Cadence Design Systems, Inc.Methods, systems, and computer program product for parallelizing tasks in processing an electronic circuit designUS8214775Sep 10, 2008Jul 3, 2012Luminescent Technologies, Inc.System for determining repetitive work unitsUS8418094Dec 13, 2011Apr 9, 2013Cadence Design Systems, Inc.Methods, systems, and computer program product for parallelizing tasks in processing an electronic circuit designUS20080235497 *Nov 26, 2007Sep 25, 2008Tomblin Jimmy JParallel Data OutputUS20090077527 *Sep 10, 2008Mar 19, 2009Jordan GergovSystem for Determining Repetitive Work UnitsUS20100115478 *Dec 31, 2008May 6, 2010Cadence Design Systems, Inc.Methods, systems, and computer program prodcut for parallelizing tasks in processing an electronic circuit designCN103646031A *Nov 8, 2013Mar 19, 2014上海华力微电子有限公司Method for contrasting coordinate data of DRC files* Cited by examinerClassifications U.S. Classification716/106, 716/112International ClassificationG06F17/50Cooperative ClassificationG06F17/5081European ClassificationG06F17/50L3Legal EventsDateCodeEventDescriptionJan 10, 2006ASAssignmentEffective date: 20051201Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CADOURI, EITAN;REEL/FRAME:017175/0694Owner name: CADENCE DESIGN SYSTEMS, INC., CALIFORNIASep 22, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services