Source: http://www.google.com/patents/US8073009?dq=645576
Timestamp: 2017-10-20 22:13:48
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Matched Legal Cases: ['Application No. 2006', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 10180758', 'Application No. 10180766', 'Application No. 05', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2011', 'Application No. 05', 'Application No. 05706081', 'Application No. 2006', 'Application No. 2006', 'Application No. 05706081']

Patent US8073009 - Adaptive allocation of I/O bandwidth using a configurable interconnect topology - Google Patents
Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either...http://www.google.com/patents/US8073009?utm_source=gb-gplus-sharePatent US8073009 - Adaptive allocation of I/O bandwidth using a configurable interconnect topology
Publication number US8073009 B2
Application number US 12/177,747
Also published as EP1716474A2, EP1716474A4, EP1716474B1, EP2293198A1, EP2293447A1, US7158536, US7420990, US8149874, US20050165970, US20070071032, US20080276020, US20110219162, WO2005072335A2, WO2005072335A3
Publication number 12177747, 177747, US 8073009 B2, US 8073009B2, US-B2-8073009, US8073009 B2, US8073009B2
Patent Citations (114), Non-Patent Citations (79), Referenced by (4), Classifications (20), Legal Events (1)
Adaptive allocation of I/O bandwidth using a configurable interconnect topology
US 8073009 B2
17. The system of claim 14, wherein the bandwidth-allocation logic alters the first and second numbers when the electronic component has data to be output as a third number of parallel signals to the integrated circuit.
In an embodiment of the present invention, a memory device is a common class of integrated circuit devices that have an array of memory cells, such DRAM, Read Only Memory (“ROM”), Ferroelectric RAM (“FRAM”), Magnetoresistive or Magnetic RAM (“MRAM”), Static Access Memory (“SRAM”), flash memory (“Flash”), double data rate SDRAM (“DDR”) or an equivalent thereof. Examples of memory devices include Direct Rambus® memory devices (“DRDRAM”), XDR™ memory devices or an equivalent thereof.
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JP10090360A Title not available
JP61059585A Title not available
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JP2002101236A Title not available
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JPH02170638A Title not available
JPH05344025A Title not available
JPH06311569A Title not available
JPH08221353A Title not available
JPS6159585A Title not available
JPS62196967A Title not available
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International Classification H04J3/16, G06F13/40, H04L5/18, G06F3/00, H04L25/02, H04L5/14
Cooperative Classification H04L5/18, H04L5/143, H04L25/0272, H04L25/0294, H04L5/14, G06F13/4072, Y02B60/1235, Y02B60/1228
European Classification H04L5/14P, G06F13/40E2B, H04L5/14, H04L5/18