Source: https://patents.google.com/patent/JP2006054540A/en
Timestamp: 2020-02-23 20:51:07
Document Index: 598601100

Matched Legal Cases: ['art 20349', 'art, 20', 'art, 101', 'art, 102', 'art, 103', 'art, 104', 'art, 105', 'art, 106', 'art, 107']

JP2006054540A - Synchronization method of communication - Google Patents
Synchronization method of communication Download PDF
JP2006054540A
JP2006054540A JP2004233072A JP2004233072A JP2006054540A JP 2006054540 A JP2006054540 A JP 2006054540A JP 2004233072 A JP2004233072 A JP 2004233072A JP 2004233072 A JP2004233072 A JP 2004233072A JP 2006054540 A JP2006054540 A JP 2006054540A
JP2004233072A
Kenichi Osaki
健一 大崎
2004-08-10 Application filed by Nakayo Telecommun Inc, 株式会社ナカヨ通信機 filed Critical Nakayo Telecommun Inc
2004-08-10 Priority to JP2004233072A priority Critical patent/JP2006054540A/en
2006-02-23 Publication of JP2006054540A publication Critical patent/JP2006054540A/en
<P>PROBLEM TO BE SOLVED: To provide a communication synchronization technology employing the FH-MMFSK or the FH-M<SP>3</SP>FSK without the need for carrying out correlation arithmetic operations as to each of a plurality of hopping patterns to which information is assigned. <P>SOLUTION: A transmission section 10 attaches a synchronizing signal having a signal waveform with left-right symmetry in a time axis direction to a communication frame and transmits the resulting communication frame. A reception section 20 applies cross-correlation arithmetic operations for calculating the correlation between waveform data of the synchronizing signal stored in advance and the received signal from a communication opposite party and auto-correlation for calculating the left-right symmetry in the time axis direction to the received signal to detect the synchronizing signal from the received signal and recognizes the communication frame on the basis of the detected synchronizing signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI
The present invention, FH-MMFSK about - - (M-ary Multilevel Multitone FSK Frequency Hopping) synchronization technique of communication using (Frequency Hopping M-ary Multilevel FSK ) or FH-M 3 FSK.
As a synchronization technique in spread spectrum communication by frequency hopping (FH: Frequency Hopping), a hopping pattern used by the transmission side device for frequency hopping with respect to the received signal by a frequency hopping synthesizer or matched filter provided in the reception side device. Is generally performed (see, for example, Patent Document 1). In recent years, FH-MMFSK and FH-M 3 FSK have been proposed as radio communication technologies using frequency hopping (see, for example, Non-Patent Document 1).
JP 2003-32244 A Akihiko OSHINOMI, Gen MARUBAYASHI, Shinich TACHIKAWA, and Masanori HAMAMURA, "Trial Model of The M-ray Multilavel FSK Power-line Transmission Modem", ISPL2003, Proceedings of the 7th International Symposium on Power-Line Communications and Its Applications, March 26- 28, 2003, Kyoto, Japan
By the way, in spread spectrum communication by frequency hopping, a hopping pattern is assigned to each user (receiving side device). Therefore, the reception-side apparatus can achieve synchronization by performing a correlation operation with the hopping pattern assigned to itself on the received signal. However, in communication using FH-MMFSK and FH-M 3 FSK, information is given to the hopping pattern itself. That is, even for the same user, the hopping pattern varies depending on information to be held. Therefore, when a technique for performing synchronization by performing a correlation operation with the hopping pattern described above is applied to synchronization in communication by FH-MMFSK and FH-M 3 FSK, information is received with respect to the received signal in the reception side device. It is necessary to perform a correlation operation for each of a plurality of assigned hopping patterns. For this reason, the circuit scale of the receiving device increases.
The present invention has been made in view of the above circumstances, and an object of the present invention is to perform FH-MMFSK or FH-M 3 FSK that does not require correlation calculation for each of a plurality of hopping patterns to which information is assigned. It is to provide a communication synchronization technique used.
In order to solve the above-described problem, in the present invention, a transmission-side apparatus adds a synchronization signal to a communication frame for transmission, and a reception-side apparatus performs a cross-correlation calculation with the waveform of the synchronization signal and a time for the reception signal. The synchronization signal is detected from the received signal using only the combination of the autocorrelation operations of the waveform in the axial direction or the autocorrelation operation of the waveform in the time axis direction, and the communication frame is recognized using the detected synchronization signal.
For example, the first aspect of the present invention is a communication synchronization method using FH-MMFSK or FH-M 3 FSK, in which a transmission side device generates a signal waveform symmetrical in the time axis direction in a communication frame. A cross-correlation operation for performing a transmission step of adding and transmitting a synchronization signal having, and calculating a correlation between the reception-side device and the waveform data of the synchronization signal stored in advance for the reception signal from the transmission-side device; And the autocorrelation calculation which calculates the left-right symmetry of a time-axis direction is performed, a synchronizing signal is detected from the said received signal, and the receiving step which recognizes a communication frame based on the detected synchronizing signal is performed.
Further, the second aspect of the present invention is a communication synchronization method using FH-MMFSK or FH-M 3 FSK, in which a transmission side device uses a frequency or modulation signal that is not used for a modulation signal in a communication frame. Even if the frequency is being used, the sync signal waveforms have different combinations, and when divided into four or more even segments in the time axis direction, a sync signal having multiple combinations of segments having similar waveforms is added. The transmitting device performs a transmission step, and the receiving device performs autocorrelation calculation for calculating the correlation of the waveform in the time axis direction with respect to the received signal from the transmitting device, and obtains a synchronization signal from the received signal. A reception step of detecting and recognizing a communication frame based on the detected synchronization signal is performed.
According to the present invention, since the communication frame is recognized using the synchronization signal added to the communication frame, it is not necessary to perform a correlation operation for each of a plurality of hopping patterns to which information is assigned. For this reason, the circuit scale of the receiving apparatus can be reduced.
FIG. 1 is a schematic diagram of an FH-M 3 FSK modem device to which the first embodiment of the present invention is applied. As shown in the figure, the FH-M 3 FSK modem apparatus according to the present embodiment receives and receives a FH-M 3 FSK signal by transmitting a transmission unit 10 that converts transmission data into an FH-M 3 FSK signal and transmits the FH-M 3 FSK signal. And a receiving unit 20 for converting the data.
The transmission unit 10 includes an S / P (Serial / Parallel) conversion unit 101, a level conversion unit 102, a pattern selection unit 103, a hopping pattern storage unit 104, an addition unit 105, a remainder calculation unit 106, a level- A frequency calculation unit 107, an IFFT (Inverse Fast Fourier Transform) unit 108, a synchronization signal adding unit 109, a DA (Digital Analog) conversion unit 110, and an AFE (Analog Front End) unit 111 are included.
Serial data K bits inputted to the transmitting unit 10 (transmitting data) is converted into parallel data by the S / P conversion unit 101, the upper (or lower) K 1 bit is input to the level conversion unit 102, the remaining K 2 bits are input to the pattern selection unit 103.
The level conversion unit 102 converts the K 1- bit parallel data input from the S / P conversion unit 101 into a level corresponding to the value indicated by the parallel data. Then, a level pattern in which the converted level is continuously formed for the number of chips (symbols) constituting one hopping (the time width of one chip is τ) is output to the adding unit 105. FIG. 2A is a diagram schematically showing the level pattern 1021 output from the level conversion unit 102. In this example, the number of chips for one hopping = 5, the number of bits of K 1 bit = 3, and the parallel data of K 1 bit is “011”. When the number of bits = 3, there are 8 possible values for the bit data. Therefore, the number of levels = 8.
The pattern selection unit 103 reads out the hopping pattern associated with the value indicated by the K 2- bit parallel data input from the S / P conversion unit 101 from the hopping pattern storage unit 104 and outputs the hopping pattern to the addition unit 105. Here, the hopping pattern storing unit 104, the hopping pattern is stored for each possible value is K 2 bits of para data. Note that the number of chips and the number of levels of the hopping pattern are the same as the number of chips and the level of the level pattern output from the level converter 102. FIG. 2B is a diagram schematically showing the hopping pattern 1041 stored in the hopping pattern storage unit 104. The hopping pattern associated with each value that can be taken by the K 2- bit parameter is a combination that can be used as a hopping pattern among the patterns that can be taken as a matrix of the number of chips × the number of levels (there is a variation that can be distinguished from other hopping patterns) A combination).
Adder 105 adds the level of the level pattern input from level converter 102 and the level of the hopping pattern output from pattern selector 103 for each chip. Then, the addition result is output to the remainder calculation unit 106. The remainder calculation unit 106 calculates a remainder of the level number of the level pattern and the hopping pattern with respect to the addition result of each chip input from the addition unit 105. That is, when the addition result is x and the number of levels of the level pattern and the hopping pattern is n, x (mod n) is calculated. Then, the calculation result is output to the level-frequency conversion unit 107. However, when the calculation result is 0, the level number n is output as the calculation result.
The level-frequency conversion unit 107 converts the calculation result of each chip input from the remainder calculation unit 106 into a combination of frequencies (frequency spectrum) using a pre-registered level-frequency conversion table, and the IFFT unit 108 Output to. FIG. 2C is a diagram schematically showing a level-frequency conversion table 1071 registered in the level-frequency conversion unit 107. As shown in the figure, a combination of m frequencies among n predetermined frequencies is associated with each possible value of the calculation result of the remainder calculation unit 106, that is, for each level of the level pattern and the hopping pattern. It has been. In this example, combinations of two frequencies among the five frequencies that are the same as the number of chips of the level pattern and the hopping pattern are associated. The frequency used is an integer multiple of the chip frequency (1 / τ). FIG. 2D is a diagram schematically showing a transmission spectrum 1072 for one hopping (for the number of chips in the level pattern and the hopping pattern) output from the level-frequency conversion unit 107. In this example, the level pattern and hopping pattern input to the adder 105 are the patterns shown in FIGS. 2A and 2B, and the level-frequency conversion table registered in the level-frequency converter 107 is In the case of the table shown in FIG. 2C, the transmission spectrum output from the level-frequency conversion unit 107 is shown.
Next, IFFT section 108 performs IFFT processing on the frequency spectrum of each chip for one hopping input from level-frequency conversion section 107, converts it into waveform data, and outputs the waveform data to synchronization signal adding section 109.
The synchronization signal adding unit 109 adds a cyclic prefix to the waveform data of each chip input from the IFFT unit 108. The cyclic prefix is for avoiding inter-symbol (chip) interference due to the synchronization shift of the FH-M 3 FSK signal. For each chip, the rear data of the waveform data is copied and added as a cyclic prefix to the front of the waveform data. Further, the synchronization signal adding unit 109 adds an AGC (Auto Gain Control) preamble and a synchronization signal to the head of a communication frame composed of at least one hopping waveform data. FIG. 3 is a diagram schematically showing a communication frame of the FH-M 3 FSK signal output from the synchronization signal adding unit 109. As shown in the figure, the communication frame of the FH-M 3 FSK signal used in this embodiment includes an AGC preamble 1091, a synchronization signal 1092, and waveform data 1093 of the chip for at least one hopping (here, two hoppings) , And a cyclic prefix 1094 added in front of each waveform data 1093. In this embodiment, as shown in the figure, a signal having a symmetrical waveform 1095 in the time axis direction (provided that the frequency is not used for the modulation signal (frequency hopping)) is used as the synchronization signal 1092. Yes. As described above, the synchronization signal adding unit 109 outputs the communication frame of the FH-M 3 FSK signal to which the AGC preamble, the synchronization signal, and the cyclic prefix are added to the DA conversion unit 110.
Next, the DA conversion unit 110 converts the communication frame of the FH-M 3 FSK signal output from the synchronization signal addition unit 109 into an analog signal. This analog signal is transmitted from the antenna via the AFE unit 111.
On the other hand, the receiving unit 20 includes an AFE unit 201, an AD (Analog Digital) conversion unit 202, a synchronization unit 203, an FFT (Fast Fourier Transform) unit 204, a frequency-level conversion unit 205, and a hopping pattern storage unit 206. A plurality of subtraction units 207 1 to 207 n , a plurality of remainder calculation units 208 1 to 208 n , a majority decision determination unit 209, and a P / S (Parallel / Serial) conversion unit 210.
The FH-M 3 FSK signal received from the antenna via the AFE unit 201 is converted into a digital signal by the AD conversion unit 202 and input to the synchronization signal detection unit 203. Synchronization unit 203 detects a synchronization signal from the inputted FH-M 3 FSK signal, based on the detected synchronization signal to recognize the communication frame FH-M 3 FSK signal. The waveform data of each chip is output to the FFT unit 204 for each hopping stored in the recognized communication frame. Details of the synchronization unit 203 will be described later.
Next, the FFT unit 204 performs FFT processing on the waveform data of each chip for one hopping input from the synchronization unit 203 to convert it into a frequency spectrum, and outputs the frequency spectrum to the frequency-level conversion unit 205.
In the frequency-level conversion unit 205, the same table as the level-frequency conversion table registered in the level-frequency conversion unit 107 of the communication partner is registered. Then, using this table, the frequency spectrum (combination of frequencies) of each chip input from the FFT unit 204 is converted into a level and output to the subtraction units 207 1 to 207 n .
The hopping pattern storage unit 206 stores the same pattern as the hopping pattern stored in the hopping pattern storage unit 206 of the communication partner in association with the value for each value that can be taken by K 2- bit parallel data. Yes. The subtraction units 207 1 to 207 n and the remainder calculation units 208 1 to 208 n are provided for each hopping pattern stored in the hopping pattern storage unit 206. The subtraction units 207 1 to 207 n subtract the level of the corresponding hopping pattern and the level of one hopping chip output from the frequency-level conversion unit 205 for each chip, and the subtraction result corresponds to the remainder calculation unit Output to 208 1 to 208 n . The remainder calculation units 208 1 to 208 n calculate the remainder of the level number of the level pattern and the hopping pattern used by the communication partner with respect to the subtraction results input from the corresponding subtraction units 207 1 to 207 n . That is, y (mod n) is calculated, where y is the subtraction result and n is the number of levels of the level pattern and hopping pattern used by the communication partner. Then, the calculation result is output to the majority decision determination unit 209.
The majority determination section 209, in association with the residue calculating unit 208 1 ~208 n each, parallel data of K 2 bits corresponding to the hopping pattern to which the remainder calculation unit 208 1 ~208 n is associated with data A value is registered. The majority decision determination unit 209 performs majority decision on the calculation result of one hopping chip input from each of the remainder calculation units 208 1 to 208 n , and one hopping portion including the most chips having the same calculation result. The remainder calculation units 208 1 to 208 n that output the calculation results of the chips are specified. Then, it outputs the parallel data of K 1-bit value corresponding to the specified residue calculating unit 208 1 ~208 n is most output chips of the calculation result (level), identified residue calculating unit 208 1 ~208 n The parallel data of K 2 bits registered in association with is output.
P / S conversion unit 210, K 1 bits output from the majority determining unit 209, a parallel data K 2 bits, the K 1 bits as the upper (or lower) bit data, and the remaining bit data of K 2 bits Converted into K-bit serial data (received data) to be output.
Each configuration of the above-described FH-M 3 FSK modem device may be executed in hardware by an integrated logic IC such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). , A DSP (Digital Signal Processor) or the like executed by a computer by a computer.
Next, details of the synchronization unit 203 will be described.
FIG. 4 is a schematic configuration diagram of the synchronization unit 203. As illustrated, the synchronization unit 203 includes a cross correlation calculation unit 2031, an autocorrelation calculation unit 2033, a synchronization signal detection unit 2035, a buffer unit 2037, and a synchronization control unit 2039.
The cross-correlation calculation unit 2031 performs a cross-correlation calculation for detecting a correlation with the waveform data of the synchronization signal stored in advance for the digital signal of the FH-M 3 FSK signal input from the AD conversion unit 202. Specifically, sample data obtained by A / D conversion of the waveform data of the synchronization signal is set to Y 1 to Y m (number of samples m), and sample data of the FH-M 3 FSK signal sequentially output from the AD conversion unit 202 is obtained. In the case of X i , ((ΣX i · Y i ) / m) / (√ (ΣX i 2 · ΣY i 2 ) / m 2 ), or simply, (ΣX i · Y i ) / (ΣX i 2 · ΣY i 2 ) is calculated. However, (SIGMA) is the sum total of i = 1-m.
FIG. 5 is a diagram illustrating a schematic configuration example of the cross-correlation calculation unit 2031. As shown in the figure, the cross-correlation calculation unit 2031 includes a delay unit 20311, a synchronization signal waveform data storage unit 20312, a plurality of multiplication units 20313 1 to 20313 m , an addition unit 20314, a one-sample delay unit 20315, and a multiplication. A unit 20316, an m sample delay unit 20317, a subtraction unit 20318, an addition unit 20319, a one sample delay unit 20320, a multiplication unit 20321, and a division unit 20322. For example, a shift register is used for each delay unit.
The delay unit 20311 includes a 1-sample delay processing circuit to an m-sample delay processing circuit. Then, 1-sample delay processing to m-sample delay processing is performed on the sample data of the FH-M 3 FSK signal sequentially output from the AD conversion unit 202 according to the sample clock, and the delayed sample data is output from each delay processing circuit. Among them, the delayed sample data output from the m delay processing circuit is output to the autocorrelation calculation unit 2033 and the buffer unit 2037.
Synchronizing signal waveform data storage unit 20312 includes a m number of sample data Y 1 to Y m constituting the waveform data of the sync signal, the sum ΣY i 2 of these sample data each of the square, is stored (provided that , Σ is the sum of i = 1 to m).
Multiplying unit 20313 1 ~20313 m are provided in correspondence to each of the m sample data Y 1 to Y m constituting the waveform data of the synchronization signals stored in the synchronization signal waveform data storage unit 20312 . The multiplier 20313 i (where i = 1 to m) is the i-th sample data Y i constituting the waveform data of the synchronization signal stored in the synchronization signal waveform data storage unit 20312 and the i-sample delay process of the delay unit 20311. Multiplication is performed with the sample data X i output from the circuit, and the multiplication result X i · Y i is output to the adder 20314. The adder 20314 calculates the sum ΣX i · Y i of the multiplication results X 1 · Y 1 to X m · Y m input from the multipliers 20313 1 to 20313 m and outputs the calculation result to the divider 20322. .
The 1-sample delay unit 20315 performs 1-sample delay processing on the sample data of the FH-M 3 FSK signal sequentially output from the AD conversion unit 202 according to the sample clock. The multiplier 20316 squares the sample data X 1 that has been subjected to the 1-sample delay process and is output from the 1-sample delay unit 20315. m sample delay unit 20317 performs m-sample delay processing to the calculation result X 1 2 output from multiplying unit 20317. The subtraction unit 20318 performs subtraction between the calculation result X 1 2 output from the multiplication unit 20317 and the calculation result X m + 1 2 of the addition unit 20317 subjected to m sample delay processing by the m sample delay unit 20317. The adder 20319 compares the calculation result X 1 2 −X m + 1 2 output from the subtractor 20318 and the calculation result ΣX i + 1 2 of the adder 20319 processed by one sample delay by the one sample delay unit 20320. Addition is performed (where Σ is the sum of i = 1 to m). As a result, the output from the adder 20319 is ΣX i 2 (where Σ is the sum of i = 1 to m).
Then, multiplying unit 20321 includes a calculation result .SIGMA.X i 2 of the adder 20319, the sum of the squares of m samples data constituting the waveform data of the synchronization signals stored in the synchronization signal waveform data storage unit 20312 ΣY i 2 (where Σ is the sum of i = 1 to m). Then, division unit 20322 the calculated results and ΣX i · Y i of the adder 20314, performs division of the calculation result ΣX i 2 · ΣY i 2 multiplier 20321, the result (ΣX i · Y i) / (ΣX i 2 · ΣY i 2 ) is output as a cross-correlation value to the synchronization detection unit 2035 (where Σ is the sum of i = 1 to m).
The autocorrelation calculation unit 2033 corresponds to m samples of sample data of the FH-M 3 FSK signal sequentially output from the AD conversion unit 202 (where m is the number of samples of waveform data of the synchronization signal). An autocorrelation calculation is performed to detect the correlation between the sample data for the front m / 2 samples and the sample data for the rear m / 2 samples, that is, left-right symmetry in the time axis direction. Specifically, ((ΣX L-i · X L-i-m / 2 ) / m) / (√ (ΣX L-i 2 · ΣX L-i-m / 2 2 ) / m 2 ), or In brief, (ΣX L-i · X L-i-m / 2 ) / (ΣX L-i 2 · ΣX L-i-m / 2 2 ) is calculated. Where Σ is the sum of i = 1 to m / 2.
FIG. 6 is a diagram illustrating a schematic configuration example of the autocorrelation calculation unit 2033. As illustrated, the autocorrelation calculation unit 2033 includes an m / 2 sample delay unit 20331, a multiplication unit 20332, an m / 2 sample delay unit 20333, a subtraction unit 20334, an addition unit 20335, and a one sample delay unit 20336. A multiplication unit 20337, an m / 2 sample delay unit 20338, a subtraction unit 20339, an addition unit 20340, a 1 sample delay unit 20341, a multiplication unit 20342, an m / 2 sample delay unit 20343, and a subtraction unit 20344. An adder 20345, a 1-sample delay unit 20346, a multiplier 20347, and a divider 20348. For example, a shift register is used for each delay unit.
m / 2 sample delay unit 20331 performs the m / 2 sample delay process to the sample data X L of FH-M 3 FSK signal output from the cross-correlation calculation unit 2031. Multiplying unit 20332, the sample data output from the cross-correlation calculation unit 2031 FH-M 3 FSK signal X L and, m / 2 sample output from the delay unit 20331 the m / 2 sample delay processed sample data X L Multiply with -m / 2 . The m / 2 sample delay unit 20333 performs m / 2 sample delay processing on the calculation result X L · X L-m / 2 output from the multiplication unit 20332. The subtraction unit 20334 outputs the calculation result X L · X L-m / 2 output from the multiplication unit 20332 and the calculation result X L− of the multiplication unit 20332 subjected to m / 2 sample delay processing by the m / 2 sample delay unit 20333. Subtraction with m / 2 · X L−m is performed. The adder 20335 adds the calculation result X L · X L−m / 2 −X L−m / 2 · X L−m output from the subtractor 20334 and the one sample delay unit 20336 delayed by one sample. Addition of the calculation result of the unit 20335 to ΣX L-1 · X L- im / 2-1 (where Σ is the sum of i = 1 to m / 2). As a result, the output from the adder 20335 is ΣX L−i · X L−i−m / 2 (where Σ is the sum of i = 1 to m / 2 ).
Further, the multiplication unit 20337 squares the sample data XL -m / 2 output from the m / 2 sample delay unit 20331. The m / 2 sample delay unit 20338 performs m / 2 sample delay processing on the calculation result X L-m / 2 2 output from the multiplication unit 20337. The subtraction unit 20339 outputs the calculation result X L-m / 2 2 output from the multiplication unit 20337 and the calculation result X L-m 2 of the multiplication unit 20338 subjected to m / 2 sample delay processing by the m / 2 sample delay unit 20338. And subtract. The adder 20340 calculates the calculation result X L−m / 2 2 −X L−m 2 output from the subtractor 20339 and the calculation result ΣX L− of the adder 20340 processed by one sample delay by the one sample delay unit 20341. Addition with im-2 / 12 is performed (where Σ is the sum of i = 1 to m / 2 ). As a result, the output from the adder 20340 is ΣX L- im / 2/2 (where Σ is the sum of i = 1 to m / 2 ).
Further, multiplying unit 20342 performs the square of the sample data X L of FH-M 3 FSK signals sequentially outputted from the cross-correlation calculation unit 2031. The m / 2 sample delay unit 20343 performs m / 2 sample delay processing on the calculation result X L 2 output from the multiplication unit 20342. The subtraction unit 20344 calculates the calculation result X L 2 output from the multiplication unit 20342 and the calculation result X L-m / 2 2 of the multiplication unit 20342 subjected to m / 2 sample delay processing by the m / 2 sample delay unit 20343. Perform subtraction. The addition unit 20345 calculates the calculation result X L 2 -X L-m / 2 2 output from the subtraction unit 20344 and the calculation result ΣX L-i− of the addition unit 20345 processed by one sample delay by the one sample delay unit 20346. performs addition of 1 2 (where, sigma is the sum of i = 1~m / 2). As a result, the output from the adder 20345 is ΣX L−i 2 (where Σ is the sum of i = 1 to m / 2).
Multiplying unit 20347 includes a calculation result ΣX L-i-m / 2 2 of the adder 20340, the calculation result of the adder 20345 multiplies the ΣX L-i 2 (where, sigma of i = 1 to m / 2 Sum). The division unit 20348 includes the calculation result ΣX L−i · X L−i−m / 2 of the addition unit 20335 and the calculation result ΣX L−i 2 · ΣX L−i−m / 2 2 of the multiplication unit 20347. Division is performed, and the result (ΣX L−i · L L−i−m / 2 ) / (ΣX L−i 2 · ΣX L− im − 2 / 2 ) is used as an autocorrelation value as a synchronization detection unit 2035. (Where Σ is the sum of i = 1 to m / 2).
The buffer unit 2037 receives and buffers the sample data of the FH-M 3 FSK signal sequentially output from the AD conversion unit 202 via the cross-correlation calculation unit 2031. The synchronization signal detection unit 2035 is a FH-M 3 FSK that is sequentially output from the AD conversion unit 202 based on the cross-correlation value output from the cross-correlation calculation unit 2031 and the auto-correlation value output from the auto-correlation calculation unit 2033. A synchronization signal is detected from the signal. The synchronization control unit 2039 recognizes the communication frame of the FH-M 3 FSK signal based on the synchronization signal detected by the synchronization signal detection unit 2035, and controls reading of the sample data stored in the buffer unit 2037. Thus, the FH-M 3 FSK signal is synchronized.
FIG. 7 is a diagram for explaining the operation flow of the synchronization signal detection unit 2035. This flow is based on the premise that the cross-correlation calculation unit 2031 and the autocorrelation calculation unit 2033 have the configurations shown in FIGS. 5 and 6, respectively.
The synchronization signal detection unit 2035 compares the cross-correlation value sequentially sent from the cross-correlation calculation unit 2031 with a predetermined threshold value (S101). If the cross-correlation value is equal to or greater than the threshold value, monitoring of the autocorrelation value sequentially sent from the autocorrelation calculation unit 2033 is started, and the peak value of the autocorrelation value is detected (S102). As described above, in this embodiment, waveform data symmetrical in the time axis direction is used as the synchronization signal. The peak value of the autocorrelation value within the time determined from the time when the cross correlation value becomes equal to or greater than the threshold value is detected. For example, since there is a synchronization point within at least one symbol (chip) after the cross-correlation value becomes equal to or greater than the threshold value, the peak value of the autocorrelation value is searched within one symbol.
When the synchronization signal detection unit 2035 detects the peak value of the autocorrelation value, the synchronization signal detection unit 2035 includes m sample components constituting the synchronization signal from the sample data stored in the buffer unit 2037 based on the detection timing. The sample data is specified (S103). Specifically, when the previous value sent from the autocorrelation calculation unit 2033 is detected as a peak value, m + 1 one before the latest sample data registered in the buffer unit 2037. M pieces of sample data up to the sample data are specified as synchronization signals. Then, the synchronization signal detection unit 2035 controls the synchronization control unit 2039 to synchronize the communication frame of the FH-M 3 FSK signal based on the identified synchronization signal, and reads data from the buffer unit 2037 (S104).
FIG. 8 is a diagram for explaining the synchronization signal detection timing of the synchronization signal detection unit 205. This timing is based on the premise that the cross-correlation calculating unit 2031 and the autocorrelation calculating unit 2033 have the configurations shown in FIGS. 5 and 6, respectively.
In FIG. 8, reference numeral 20361 indicates an FH-M 3 FSK signal input to the cross-correlation calculation unit 2031, and reference numeral 20361 indicates an FH-M 3 FSK signal input to the autocorrelation calculation unit 2033. Since the FH-M 3 FSK signal is input to the autocorrelation calculation unit 2033 via the m-sample delay processing circuit of the delay unit 20311 of the cross-correlation calculation unit 2031, it is input to the autocorrelation calculation unit 2033 as illustrated. The FH-M 3 FSK signal to be processed has a delay of m samples with respect to the FH-M 3 FSK signal input to the cross-correlation calculating unit 2031. Now, the cross-correlation value 20363 output from the cross-correlation calculating unit 2031 becomes higher as it approximates the waveform data 20365 of the synchronization signal stored in the synchronization signal waveform data storage unit 20312. When the cross-correlation value 20363 becomes equal to or greater than the predetermined threshold value 20366, the synchronization signal detection unit 205 starts detecting the peak value of the autocorrelation value 20364 output from the autocorrelation calculation unit 2033. The autocorrelation value 20364 output from the autocorrelation calculation unit 2033 increases as the left-right symmetry of the sample data 20367 for consecutive m samples increases. When the synchronization signal detection unit 205 detects the peak value of the autocorrelation value 20364, the synchronization signal detection unit 205 identifies the sample data 20367 for m consecutive samples, which is the target of the peak value detection, as the synchronization signal.
The first embodiment of the present invention has been described above. According to the present embodiment, since the communication frame is recognized using the synchronization signal added to the communication frame of the FH-M 3 FSK signal, it is necessary to perform a correlation operation for each of a plurality of hopping patterns to which information is assigned. Absent. For this reason, the circuit scale of the receiver 20 can be reduced.
In this embodiment, both the cross-correlation calculation and the autocorrelation calculation are used for detecting the synchronization signal. When the reception side holds the same waveform data as that of the synchronization signal and performs cross-correlation calculation with the reception signal, detection accuracy may be impaired due to waveform distortion or noise on the transmission path. Therefore, in the present embodiment, the autocorrelation calculation for detecting the left-right symmetry in the time axis direction of the received signal is used in combination with the above-described cross correlation calculation, using a synchronization signal having a waveform symmetrical in the time axis direction. is doing. Thereby, detection accuracy can be improved.
Next, a second embodiment of the present invention will be described. The FH-M 3 FSK modem device of this embodiment is different from that of the first embodiment shown in FIG. 1 in that a synchronization signal adding unit 109a is provided instead of the synchronization signal adding unit 109 of the transmission unit 10. In addition, a synchronization unit 203 a is provided instead of the synchronization unit 203 of the reception unit 20. Other configurations are the same as those of the first embodiment.
The synchronization signal adding unit 109 of the first embodiment uses a signal having a symmetrical waveform in the time axis direction as the added synchronization signal. On the other hand, the synchronization signal adding unit 109a of the present embodiment has a synchronization signal waveform having a different combination even if it is a frequency that is not used for a modulation signal or a frequency that is used for a modulation signal as a synchronization signal to be added. Thus, a signal having a combination having a similar waveform is used when divided into four or more even numbers in the time axis direction.
FIG. 9 is a diagram schematically showing an example of the synchronization signal used in the second embodiment of the present invention. In this example, when the synchronization signal is divided into four sections 10921 to 10924 by using a combination of frequencies that are 4 times, 8 times, and 16 times the frequency (1 / τ) of the chip as the synchronization signal, The correlation between A10921 and section B10922, the correlation between section C10923 and section D10924, and the correlation between section 10925 consisting of sections A and B and section 10926 consisting of sections C and D are increased (similar). I am doing so. A sync signal composed of frequencies of 4 times, 8 times and 16 times the chip frequency (1 / τ) has three such correlations. However, since the frequencies of 4 times, 8 times and 16 times the chip frequency (1 / τ) are not used for the modulation signal, the correlation between the FH-M 3 FSK signal and the waveform data of each chip is low. .
FIG. 10 is a schematic configuration diagram of the synchronization unit 203a. As illustrated, the synchronization unit 203a includes an autocorrelation calculation unit 2033a, a synchronization signal detection unit 2035a, a buffer unit 2037, and a synchronization control unit 2039.
The autocorrelation calculation unit 2033a uses m samples of sample data of the FH-M 3 FSK signal sequentially output from the AD conversion unit 202 (where m is the number of samples of waveform data of the synchronization signal) as a time axis. The direction is divided into four or more even segments, and autocorrelation is performed for each of a plurality of predetermined segment combinations.
FIG. 11 is a diagram illustrating a schematic configuration example of the autocorrelation calculation unit 2033a. In this example, it is assumed that the synchronization signal has the three correlations shown in FIG. As shown in the figure, the autocorrelation calculation unit 2033a multiplies the calculation results of the three correlation calculation units 2033b to 2033d and the correlation calculation units 2033b to 2033d, and outputs the multiplication result to the synchronization signal detection unit 2035a. Part 20349.
The configuration of each of the three correlation calculation units 2033b to 2033d is basically the same as that of the autocorrelation calculation unit 2033 of the first embodiment shown in FIG. However, the correlation calculation unit 2033b has an autocorrelation value (ΣX L−i · L L−i−m / 4 ) / (ΣX L−i 2 · ΣX l−i− ) between the division A 10921 and the division B 10922 shown in FIG. m / 4 2 ) (where Σ is the sum of i = 1 to m / 4 ). For this reason, each of the delay units 20331, 20333, 20338, and 20343 performs m / 4 sample delay processing instead of m / 2 sample delay processing. Further, the correlation calculation unit 2033c calculates the autocorrelation value (ΣX L- im / 2 · X L-i-3m / 4 ) / (ΣX L-i-m / between the section C10923 and the section D10924 shown in FIG. 2 2 · ΣX L−i−3 m / 4 2 ) (where Σ is the sum of i = 1 to m / 4 ). For this reason, each of the delay units 20333, 20338, and 20343 performs m / 4 sample delay processing instead of m / 2 sample delay processing. The correlation calculation unit 2033d calculates the autocorrelation value (ΣX L−i · X L−i−m / 2 ) / of the section 10925 including the sections A and B and the section 10926 including the sections C and D shown in FIG. (ΣX L-i 2 · ΣX L-i-m / 2 2 ) is calculated (where Σ is the sum of i = 1 to m / 2 ). Therefore, it is exactly the same as the autocorrelation calculating unit 2033 of the first embodiment shown in FIG.
The buffer unit 2037 receives and buffers the sample data of the FH-M 3 FSK signal that is sequentially output from the AD conversion unit 202. The synchronization signal detection unit 2035a detects a synchronization signal from the FH-M 3 FSK signal sequentially output from the AD conversion unit 202 based on the autocorrelation value output from the autocorrelation calculation unit 2033a. The operation flow of the synchronization signal detection unit 2035a is obtained by omitting step S101 from the operation flow of the first embodiment shown in FIG. The synchronization control unit 2039 recognizes the communication frame of the FH-M 3 FSK signal based on the synchronization signal detected by the synchronization signal detection unit 2035, and controls reading of the sample data stored in the buffer unit 2037. Thus, the FH-M 3 FSK signal is synchronized.
The second embodiment of the present invention has been described above. In this embodiment, as a synchronization signal, a signal composed of a combination of frequencies that are not used for a modulation signal (frequency hopping), and a similar waveform is obtained when divided into four or more even segments in the time axis direction. Using a signal having a plurality of combinations, at the receiving side, m samples of sample data of the FH-M 3 FSK signal (where m is the number of samples of waveform data of the synchronization signal) are 4 or more in the time axis direction. Without performing cross-correlation calculation processing by detecting the synchronization signal from the received FH-M 3 FSK signal. A sync signal is detected. Therefore, the circuit scale of the receiving unit 20 can be further reduced as compared with the first embodiment.
In the present embodiment, there is a possibility that the synchronization signal is erroneously detected when the continuous interference wave having a single frequency is 4, 8, or 16 times the chip frequency (1 / τ). Therefore, the cross-correlation calculation process is performed on m samples of the sample data of the FH-M 3 FSK signal in which the autocorrelation value becomes the peak value, and only when the cross-correlation value is equal to or greater than a predetermined threshold value. Sample data for m samples may be detected as a synchronization signal.
FIG. 12 shows a modification of the synchronization unit 203a used in the second embodiment of the present invention, and a cross-correlation calculation unit 2031a is added. The cross-correlation calculation unit 2031a holds m pieces of sample data of the FH-M 3 FSK signal sequentially output from the AD conversion unit 202, and the m pieces of sample data and the waveform data of the synchronization signal stored in advance ( correlation with m sample data).
FIG. 13 is a schematic configuration diagram of the cross-correlation calculation unit 2031a. As illustrated, the cross-correlation calculation unit 2031a includes a shift register 20351, a shift register 20352, a synchronization signal waveform data storage unit 20353, a shift register 20354, a multiplication unit 20355, an addition unit 20356, and a one-sample delay unit. 20357, a multiplier 20358, an adder 20359, a 1-sample delay unit 20360, and a divider 20361.
The shift register 20351 holds the sample data of the FH-M 3 FSK signal sequentially output from the AD conversion unit 202 for m samples (X 1 to X m ) from the latest one. Further, the synchronization signal waveform data storage unit 20353, the sample data Y 1 to Y m of the m constituting the waveform data of the synchronization signals are stored.
When the synchronization signal detection unit 2035a detects the peak value of the autocorrelation value output from the autocorrelation calculation unit 2033a, the synchronization signal detection unit 2035a outputs the sample data of the FH-M 3 FSK signal sequentially output from the AD conversion unit 202 to the shift register 20351. Stop input. Further, the synchronization signal detection unit 2035a corresponds to the shift register 20352, a m samples sample data X 1 to X m of which is held in the shift register 20351 is latched, causes sequentially output to the shift register 20354, the synchronization signal the sample data Y 1 to Y m of m samples constituting the waveform data of the synchronization signals stored in the waveform data storage unit 20353 is latched to output sequentially.
The multiplication unit 20355 includes sample data X i (where i = 1 to m) sequentially output from the shift register 20352 and sample data Y i (where i = 1 to m) sequentially output from the shift register 20353. Multiply The adding unit 20356 adds the calculation result X i · Y i of the multiplying unit 20355 and the addition result of the adding unit 20356 subjected to the one-sample delay processing by the one-sample delay unit 20357. Therefore, the final output value of the adder 20356 is ΣX i · Y i (where Σ is the sum of i = 1 to m).
On the other hand, the multiplication unit 20358 squares the sample data X i (where i = 1 to m) sequentially output from the shift register 20352. Adder 20359 adds calculation result X i 2 of multiplier 20358 and the addition result of adder 20359 subjected to the one-sample delay processing by one-sample delay unit 20360. Therefore, the final output value of the adder 20360 is ΣX i 2 (where Σ is the sum of i = 1 to m).
The division unit 20361 divides the output value of the addition unit 20356 and the output value of the addition unit 20360, and outputs the result as a cross-correlation value to the synchronization signal detection unit 2035a. Therefore, the final cross-correlation value output from the division unit 20361 is (ΣX i · Y i ) / ΣX i 2 (where Σ is the sum of i = 1 to m).
When the synchronization signal detection unit 2035a determines whether or not the final cross-correlation value output from the cross-correlation calculation unit 2031a is equal to or greater than a predetermined threshold, Only, sample data for m samples (sample data for m samples for which the autocorrelation value has reached its peak value) held in the shift register 20351 is detected as a synchronization signal.
According to this modification, the cross-correlation calculation process may be performed only on the sample data for m samples for which the autocorrelation value has reached the peak value. For this reason, as shown in FIG. 13, the circuit scale of the cross-correlation calculation unit 2031a can be made smaller than that of the cross-correlation calculation unit 2031 of the first embodiment.
In addition, this invention is not limited to said embodiment, Many deformation | transformation are possible within the range of the summary. For example, in each of the above embodiments, the case where the present invention is applied to the FH-M 3 FSK modem apparatus has been described as an example. However, the synchronization technique of the present invention can also be applied to the case where the synchronization of the FH-MMFSK signal is achieved.
FIG. 1 is a schematic diagram of an FH-M 3 FSK modem device to which the first embodiment of the present invention is applied. FIG. 2A schematically shows a level pattern 1021 output from the level conversion unit 102, and FIG. 2B schematically shows a hopping pattern 1041 stored in the hopping pattern storage unit 104. FIG. 2C schematically shows a level-frequency conversion table 1071 registered in the level-frequency conversion unit 107, and FIG. 2D is output from the level-frequency conversion unit 107. It is the figure which represented typically the transmission spectrum 1072 for 1 hopping. FIG. 3 is a diagram schematically showing a communication frame of the FH-M 3 FSK signal output from the synchronization signal adding unit 109. FIG. 4 is a schematic configuration diagram of the synchronization unit 203. FIG. 5 is a diagram illustrating a schematic configuration example of the cross-correlation calculation unit 2031. FIG. 6 is a diagram illustrating a schematic configuration example of the autocorrelation calculation unit 2033. FIG. 7 is a diagram for explaining the operation flow of the synchronization signal detection unit 2035. FIG. 8 is a diagram for explaining the synchronization signal detection timing of the synchronization signal detection unit 205. FIG. 9 is a diagram schematically showing an example of the synchronization signal used in the second embodiment of the present invention. FIG. 10 is a schematic configuration diagram of the synchronization unit 203a. FIG. 11 is a diagram illustrating a schematic configuration example of the autocorrelation calculation unit 2033. FIG. 12 is a diagram showing a modification of the synchronization unit 203a used in the second embodiment of the present invention. FIG. 13 is a schematic configuration diagram of the cross-correlation calculation unit 2031a.
DESCRIPTION OF SYMBOLS 10 ... Transmission part, 20 ... Reception part, 101 ... S / P conversion part, 102 ... Level conversion part, 103 ... Pattern selection part, 104 ... Hopping pattern storage part, 105 ... Addition part, 106 ... Remainder calculation part, 107 ... Level-frequency conversion unit, 108 ... IFFT unit, 109 ... synchronization signal addition unit, 110 ... DA conversion unit, 111 ... AFE unit, 201 ... AFE unit, 202 ... AD conversion unit, 203 ... synchronization unit, 203a ... synchronization unit, 204: FFT unit, 205: Frequency-level conversion unit, 206: Hopping pattern storage unit, 207 ... Subtraction unit, 208 ... Remainder calculation unit, 209 ... Majority determination unit, 210 ... P / S conversion unit, 2031 ... Cross correlation calculation , 2031a ... cross-correlation calculator, 2033 ... autocorrelation calculator, 2033a ... autocorrelation calculator, 2035 ... synchronization signal detector, 2035a ... synchronization signal detector , 2037 ... buffer unit, 2039 ... synchronization control unit
FH-MMFSK a - - (M-ary Multilevel Multitone FSK Frequency Hopping) method of synchronizing communication using, (Frequency Hopping M-ary Multilevel FSK) or FH-M 3 FSK
The transmission side device performs a transmission step of transmitting a communication frame by adding a synchronization signal having a symmetrical signal waveform in the time axis direction,
The cross-correlation calculation for the reception side apparatus to calculate the correlation with the waveform data of the synchronization signal stored in advance for the received signal from the transmission side apparatus, and the autocorrelation for calculating the left-right symmetry in the time axis direction A communication synchronization method comprising: performing a reception step of performing an operation to detect a synchronization signal from the reception signal and recognizing a communication frame based on the detected synchronization signal.
The communication synchronization method according to claim 1, comprising:
The reception step performs the cross-correlation operation on the reception signal from the transmission device, and a signal portion having a correlation equal to or greater than a predetermined threshold with the waveform data of the synchronization signal stored in advance from the reception signal. Extracting and identifying a signal part having a peak value as a result of the autocorrelation calculation from the extracted signal part, and identifying a communication frame from the received signal using the identified signal part as a synchronization signal. Communication synchronization method.
The transmission side device divides the communication frame into synchronization signal waveforms with different combinations even if the frequency is not used for the modulation signal or the frequency used for the modulation signal, and is divided into even segments of 4 or more in the time axis direction. In this case, a transmission step is performed in which a synchronization signal having a plurality of combinations of sections having similar waveforms is added and transmitted,
The reception side device performs autocorrelation calculation for calculating the correlation of the waveform in the time axis direction with respect to the reception signal from the transmission side device, detects the synchronization signal from the reception signal, and based on the detected synchronization signal And performing a reception step of recognizing a communication frame.
The communication synchronization method according to claim 3, comprising:
The reception step performs the autocorrelation calculation on the reception signal from the transmission device, extracts a signal portion whose result is a peak value, and extracts the extracted signal portion and waveform data of a synchronization signal stored in advance. When the cross-correlation calculation of the signal portion indicates that the cross-correlation calculation result has a correlation equal to or higher than a predetermined threshold value, the received signal is used as a synchronization signal from the received signal. A communication synchronization method characterized by recognizing.
A - (M-ary Multilevel Multitone FSK Frequency Hopping) modem device, - FH-MMFSK (Frequency Hopping M-ary Multilevel FSK) or FH-M 3 FSK
A transmission unit that adds a synchronization signal having a symmetrical signal waveform in the time axis direction to the communication frame and transmits the frame,
The received signal from the communication partner is subjected to a cross-correlation operation for calculating a correlation with a waveform signal of a synchronization signal stored in advance and an autocorrelation operation for calculating a left-right symmetry in the time axis direction. And a receiving unit that detects a synchronization signal from the signal and recognizes a communication frame based on the detected synchronization signal.
Similar in the case where the communication frame is a synchronization signal waveform having a different combination even if it is a frequency that is not used for the modulation signal or a frequency that is used for the modulation signal, and is divided into four or more even sections in the time axis direction. A transmission unit for adding and transmitting a synchronization signal having a plurality of combinations of sections having the waveform of:
Receives a received signal from a communication partner by performing an autocorrelation operation that calculates the correlation of the waveform in the time axis direction, detects a synchronization signal from the received signal, and recognizes a communication frame based on the detected synchronization signal A modem device.
JP2004233072A 2004-08-10 2004-08-10 Synchronization method of communication Pending JP2006054540A (en)
JP2004233072A JP2006054540A (en) 2004-08-10 2004-08-10 Synchronization method of communication
JP2006054540A true JP2006054540A (en) 2006-02-23
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JP2004233072A Pending JP2006054540A (en) 2004-08-10 2004-08-10 Synchronization method of communication
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