Source: http://www.google.com/patents/US20040116083?dq=6011510
Timestamp: 2014-08-01 14:02:42
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Patent US20040116083 - Linear power amplification method and linear power amplifier - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA combined signal of a digital pilot signal and a digital transmission signal is applied to a digital predistorter (20), wherein it is added with odd-order distortions based on a power series model to generate a predistorted signal, then the predistorted signal is converted by a DA converter (31) to...http://www.google.com/patents/US20040116083?utm_source=gb-gplus-sharePatent US20040116083 - Linear power amplification method and linear power amplifierAdvanced Patent SearchPublication numberUS20040116083 A1Publication typeApplicationApplication numberUS 10/730,141Publication dateJun 17, 2004Filing dateDec 9, 2003Priority dateDec 10, 2002Also published asCN1255938C, CN1510832A, EP1429453A1, EP1429453B1, EP2157692A2, EP2157692A3, EP2157692B1, US7170342Publication number10730141, 730141, US 2004/0116083 A1, US 2004/116083 A1, US 20040116083 A1, US 20040116083A1, US 2004116083 A1, US 2004116083A1, US-A1-20040116083, US-A1-2004116083, US2004/0116083A1, US2004/116083A1, US20040116083 A1, US20040116083A1, US2004116083 A1, US2004116083A1InventorsYasunori Suzuki, Shinji Mizuta, Tetsuo Hirota, Yasushi YamaoOriginal AssigneeNtt Docomo, Inc.Export CitationBiBTeX, EndNote, RefManReferenced by (35), Classifications (9), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetLinear power amplification method and linear power amplifierUS 20040116083 A1Abstract A combined signal of a digital pilot signal and a digital transmission signal is applied to a digital predistorter (20), wherein it is added with odd-order distortions based on a power series model to generate a predistorted signal, then the predistorted signal is converted by a DA converter (31) to an analog signal, then the analog signal is upconverted by a frequency upconverting part (33) to a send frequency band, and the upconverted signal is output after being amplified by a power amplifier (37). A pilot signal component is extracted from the power amplifier output, then odd-order distortion components of the power series model are extracted by a digital predistorter control part (50) from the pilot signal component, and the odd-order distortions in the digital predistorter (20) are controlled to decrease the levels of the distortion components. Images(32) Claims(36)
BRIEF DESCRIPTION OF THE DRAWINGS [0033]FIG. 1 is a graph showing the relationship between amplification efficiency and an output backoff from a 1 dB gain compression point; [0034]FIG. 2 is a graph showing the relationships between amplitude and phase deviations in respect of a third-order distortion component; [0035]FIG. 3 is a graph showing examples of frequency dependent amplitude and phase of a power amplifier; [0036]FIG. 4 is a block diagram illustrating a basic configuration of the linear power amplifier according to the present invention; [0037]FIG. 5 is a block diagram depicting a first embodiment of the linear power amplifier according to the present invention; [0038]FIG. 6 is a diagram schematically showing spectra of signals at respective parts in FIG. 5: [0039]FIG. 7 is a flowchart showing the procedure for implementing the linear power amplification method according to the present invention; [0040]FIG. 8 is a block diagram depicting a second embodiment of the linear power amplifier according to the present invention; [0041]FIG. 9 is a diagram schematically showing spectra of signals at respective parts in FIG. 8; [0042]FIG. 10 is a block diagram depicting a third embodiment of the linear power amplifier according to the present invention; [0043]FIG. 11 is a block diagram depicting a fourth embodiment of the linear power amplifier according to the present invention; [0044]FIG. 12 is a block diagram depicting a modified form of each of the third and fourth embodiments of the linear power amplifier according to the present invention; [0045]FIG. 13 is a block diagram showing a modified form of the FIG. 10 embodiment; [0046]FIG. 14 is a block diagram showing a modified form of the FIG. 12 embodiment; [0047]FIG. 15 is a block diagram illustrating another example of a digital predistorter control part; [0048]FIG. 16A is a diagram depicting an equivalent circuit of a FET; [0049]FIG. 16B is a diagram depicting an equivalent circuit of an amplifier using a FET; [0050]FIG. 17 is a block diagram illustrating a basic configuration of a fifth embodiment of the linear power amplifier according to the present invention; [0051]FIG. 18 is a graph for explaining the operation of the fifth embodiment; [0052]FIG. 19 is a block diagram showing a concrete example of the fifth embodiment; [0053]FIG. 20 is a block diagram depicting the configuration of a sixth embodiment of the present invention; [0054]FIG. 21 is a block diagram depicting the configuration of a seventh embodiment of the present invention; [0055]FIG. 22 is a block diagram showing a modified form of the FIG. 21 embodiment in which a pilot signal generator 12 generates a modulation signal as a pilot signal; [0056]FIG. 23 is a block diagram depicting the configuration of an eighth embodiment of the present invention; [0057]FIG. 24 is a flowchart showing the procedure for calculating characteristics of a frequency characteristic compensator; [0058]FIG. 25 is a frequency chart for explaining the generation of compensated distortions for a third-order distortion; [0059]FIG. 26A is a graph showing a grain-frequency characteristic of a frequency characteristic compensator calculated by linear interpolation; [0060]FIG. 26B is a graph showing a phase-frequency characteristic of the frequency characteristic compensator; [0061]FIG. 27A is a graph showing a gain-frequency characteristic of the frequency characteristic compensator calculated by polynomial interpolation; [0062]FIG. 27B is a graph showing a determined phase-frequency characteristic of the frequency characteristic compensator; [0063]FIG. 28A is a graph showing a combined gain-frequency characteristic of a frequency characteristic compensator and a gain adjuster, calculated by linear interpolation; [0064]FIG. 28B is a graph showing a combined phase-frequency characteristic of the frequency characteristic compensator and a phase adjuster; [0065]FIG. 29A is a graph showing a combined gain-frequency characteristic of the frequency characteristic compensator and the gain adjuster, calculated by polynomial interpolation; [0066]FIG. 29B is a graph showing a combined phase-frequency characteristic of the frequency characteristic compensator and the phase adjuster; [0067]FIG. 30 is a block diagram illustrating the configuration of a ninth embodiment of the present invention; [0068]FIG. 31 is a block diagram illustrating the configuration of a tenth embodiment of the present invention; [0069]FIG. 32 is a block diagram illustrating the configuration of an eleventh embodiment of the present invention; [0070]FIG. 33 is a flowchart showing the procedure for setting characteristics of the frequency characteristic compensator in the FIG. 32 embodiment; and [0071]FIG. 34 is a block diagram showing a modified form of the FIG. 32 embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Basic Constitution of the Invention [0072]FIG. 4 illustrates a basic constitution of the linear power amplifier according to the present invention. A transmission signal S and a pilot signal PL are generated through different digital signal processing by a transmission signal generator 11 and a pilot signal generator 12, respectively, and they are added together by an adder 15, the adder output being provided to a digital predistorter 20. The transmission signal S may be either a baseband or IF signal; but it will hereinafter be assumed as a baseband signal unless otherwise specified. The digital predistorter 20, based on a power series model, performs digital signal processing for predistorting the input signal that is a combined signal of the transmission signal S and the pilot signal PL. [0073] The output signal from the digital predistorter 20 is converted to an analog signal by a digital-to-analog (DA) converter 31 that has a working speed in a band at least twice higher than the band of the combined signal of the pilot signal PL and the transmission signal S. The analog signal is frequency converted by a frequency upconverting part 33 to a high-frequency signal of the transmit frequency band, and the frequency-converted signal is fed to a power amplifier 37. The output signal from the power amplifier 37 is divided by a power dividing part 38 into two, one of which is provided to a frequency downconverting part 40 and the other of which is provided as a linear amplifier output to, for example, an antenna. The one divided portion of power is downconverted in the frequency downconverting part 40, thereafter being fed to a digital predistorter control part 50. The control part 50 extracts an odd-order distortion component of the pilot signal from the downconverted signal, and uses the extracted distortion component to correct coefficients of the digital predistorter 20. [0074] Since the digital predistorter 20 using the pilot signal does not correct the coefficients by use of correction data read out of a memory but instead directly corrects the coefficients by use of the detected distortion component in such a manner as to reduce the distortion component as referred to above, the coefficient correction is free from the influence of secular and temperature variations. Further, as regards a pilot signal feedback time, since the band of the pilot signal is narrower than the band of the transmission signal, the delay time of the digital predistorter in the present invention can be extended longer than the delay time in a conventional digital predistorter. Accordingly, the feedback time does not matter even in the feedback route in which the pilot signal is downconverted as shown in FIG. 4. First Embodiment [0075]FIG. 5 illustrates a first embodiment of a linear power amplifier embodying the digital predistortion scheme according to the present invention. The pilot signal used in this embodiment is two tone signals PL1 and PL2 of the same level. The linear power amplifier of this embodiment comprises: a pilot signal generator 12 composed of tone signal generators 12A and 12B for generating the tone signals PL1 and PL2 through digital signal processing, and a digital adder 14; a digital predistorter 20; a DA converter 31; a frequency upconverting part 33 composed of a local oscillator 33A, a mixer 33B, and a band-pass filter 33C; a power amplifier 37; a directional coupler 38A and a pilot signal extracting band-pass filter 38B that constitute a dividing part 38; a frequency downconverting part 40 composed of a mixer 41, a band-pass filter 42, an amplifier 43, and an analog-to-digital (AD) converter 44; and a digital predistorter control part 50. The digital predistorter 20 is shown to handle distortions of up to the seventh order, but the number of orders may be chosen as desired according to the device configuration used. While in practice a low-pass filter for aliasing cutting use is connected to the output side of the DA converter 31, it is not related directly to the present invention and hence is not shown. [0076] The digital predistorter 20 using a power series model is configured to add output signals from a delay path which passes therethrough the fundamental wave component of the transmission signal and the path for generating each odd-order distortion by use of the power series. That is, the fundamental wave component passes through a delaying memory 21 which provides coincidence between the delay times of the delay path and the distortion generation path. Distortion components of the respective odd orders are produced by distortion generators 22A, 22B and 22C, gain adjusters 24A, 24B and 24C for amplitude adjustment use, and phase adjusters 23A, 23B and 23C for phase adjustment use. The odd-order distortion generators 22A, 22B and 22C each perform processing of raising the input combined signal of the transmission signal A and the pilot signals PL1 and PL2 to the corresponding odd-order power. For instance, letting X represent the sum of the transmission signal S and the pilot signals PL1 and PL2, the third-order distortion generator raises X to 3rd power. The phase- and amplitude-adjusted odd-order distortion components are added together by adders 26 and 27, then the added output is further added by an adder 25 to the delayed fundamental wave component from the delaying memory 21, and the added output is applied as a predistorted signal Y from the digital predistorter 20 to the DA converter 31. [0077] The DA converter 31 converts the predistorted signal Y to an analog signal, which is applied to the mixer 33B, wherein it is mixed with a local signal (a carrier signal) of a frequency fc fed from the local oscillator 33A. The mixed output is provided to the band-pass filter 33C to extract a signal of the transmit frequency band, which is applied to the power amplifier 37. The output high-frequency signal from the power amplifier 37 is transmitted via the directional coupler 38A. [0078] A portion of the transmit output of the high-frequency signal is taken out by the directional coupler 38A and is applied to the band-pass filter 38B to extract a pilot signal component (composed of pilot signals and higher order distortions). The thus extracted pilot signal component is mixed by the mixer 41 with the carrier signal from the local oscillator 33A, and the mixer output is applied to the band-pass filter 42 to detect a downconverted pilot signal component, which is amplified by the amplifier 43. The amplified pilot signal component is converted by the DA converter 44 to a digital signal, which is provided to the digital predistorter control part 50. [0079] The digital predistorter control part 50 comprises a distortion component detecting part 51 and an odd-order distortion characteristic control part 52. The distortion component detecting part 51 is made up of third-, fifth- and seventh-order distortion component extractors 51A, 51B and 51C. The odd-order distortion characteristic control part 52 is made up of third-, fifth- and seventh-order distortion controllers 52A, 52B and 52C. The odd-order distortion component extractors 51A, 51Band 51C can be formed, for example, by band-pass filters, by which third-, fifth- and seventh-order distortion components are extracted. The odd-order distortion controllers 52A, 52B and 52C control the phase adjusters 23A, 23B, 23C and the variable gain adjusters 24A, 24B, 24C that adjust the phases and amplitudes of the outputs from the distortion component generators 22A, 22B and 22C corresponding to the controllers, respectively. [0080] Since the pilot signals PL1 and PL2 used are tone signals of the same level (CW signals), odd-order distortion components appearing in the vicinities of the tone signals are extracted at the output of the power amplifier 37 by the odd-order distortion component extractors 51A, 51B and 51C. While the digital predistorter control part 50 in this embodiment is implemented by digital signal processing, a similar configuration may be implemented by analog circuits. [0081]FIG. 6 shows, in the form of signal spectra, how to inject and extract the pilot signals PL1 and PL2 in this embodiment. The input signal X to the digital predistorter 20 contains the transmission signal S of the baseband and the pilot signals PL1 and PL2 that are tone signals of the same level. The pilot signals PL1 and PL2 of frequencies f1 an f2 are injected into the adjacent band of the transmission signal S as shown in FIG. 6�Row A. The two pilot signals PL1 and PL2 are set with a frequency interval Δf=f2−f1 which is sufficiently narrower than the modulated signal bandwidth of the transmission signal S. The output signal Y from the digital predistorter 20 contains predistorted components SD, PD3L and PD3H resulting from predistortion of the transmission signal S and the pilot signals PL1 and PL2, as shown in FIG. 6�Row B. Here are exemplified the third-order distortion components; for example, the fifth-order distortion components of the pilot signals PL1 and PL2 are a component higher than PD3H by Δf and a component lower than PD3L by Δf, but they are not shown. The seventh-order distortion components are generated further outside than the fifth-order distortion components by Δf, but they are not shown, either. [0082] The input signal to the power amplifier 37 is a signal that the output signal Y from the digital predistorter 20 was upconverted in the frequency upconverting part 33 by the carrier frequency fc as depicted in FIG. 6�Row C. In this case, the predistorted components generated by the digital predistorter 20 are so set as to compensate for distortions over the entire transmission route. Accordingly, no problem arises from a mismatch between the predistorted components in the input signal to the power amplifier 37 and the predistorted components in the output signal of the digital predistorter 20. But the difference is very small since intennodulation distortions in the transmit route mostly occur in the power amplifier 37 at the final stage of the route. As shown in FIG. 6�Row D, the output signal from the power amplifier 37 is a signal with distortions suppressed by the digital predistorter 20, that is, a distortion-compensated signal. [0083] The pilot signal component containing the distortion components is extracted by the directional coupler 38A and the band-pass filter 38B. The extracted pilot signal component is downconverted by the mixer 41 with the local oscillation signal from the local oscillator 33. The input signal to the control part 50, shown in FIG. 6�Row E, is a digitized version of the downconverted signal by the AD converter 44, For example, when distortion compensation for the third-order distortion components PD3H and PD3L is insufficient at the output of the power amplifier 37, they remain unremoved to such an extent as not to be negligible. In the control part 50 one of the third-order distortion components, PD3H in this case, is extracted by the third-order distortion component extractor 51A. The third distortion controller 52A uses the extracted tone signal to control the phase and amplitude of the output from the third distortion signal generator 22A by the phase adjuster 23A and the variable gain adjuster 24A until the compensated amount of distortion reaches such a value that the adjacent channel leakage power ratio (i.e., the level ratio of the distortion component to the transmission signal) goes down below a predetermined value at the output of the power amplifier 37. To perform this, various optimal algorithms can be used. [0084]FIG. 7 is a flowchart showing a linear power amplification procedure including the steps for setting coefficients in the digital predistorter 20 by controlling the phases of the phase adjusters 23A, 23B, 23C and the gains of the variable gain adjusters 24A, 24B, 24C. [0085] Step S1: Generate digital pilot signals PL1 and PL2, and add them with a digital transmission signal S to obtain a combined signal. [0086] Step S2: Generate odd-order distortion components for the digital combined signal. [0087] Step S3: Set the phases and amplitudes of the odd-order distortion components. [0088] Step S4: Add the distortion components and the delayed fundamental wave component to generate a predistorted signal. [0089] Step S5: Convert the predistorted signal to an analog signal. [0090] Step S6: Upconvert the analog predistorted signal to a high-frequency signal. [0091] Step S7: Power amplify the high-frequency predistorted signal by a power amplifier. [0092] Step S8: Extract the pilot signal components from the amplified high-frequency signal and downconvert them. [0093] Step S9: Convert the downconverted pilot signal components to digital form. [0094] Step S10: Extract distortion components from the digital pilot signal components. [0095] Step S11: Make a check to see if the ratio of the distortion component level to the transmission signal level is below a predetermined value, and if so, end the procedure, and if not, return to step S3 and repeat steps S3 through S11. Second Embodiment [0096]FIG. 8 illustrates in block form a second embodiment of the present invention, which is a modified form of the first embodiment. The illustrated embodiment employs one modulated wave signal as the pilot signal instead of using the two tone signals, and is identical in construction with the first embodiment except the configuration of the pilot signal generator 12. And this embodiment is also identical in operation with the first embodiment. [0097]FIG. 9 shows, in the form of signal spectra, the injection and extraction of the pilot signal PL in the second embodiment. Rows A and B schematically show spectra of the input signal X to and the output signal Y from the digital predistorter 20, Rows C and D spectra of the input signal to and the output signal from the power amplifier 37, and Row E spectrum of the input signal to the control part 50. The spectra shown in FIG. 9 are identical with those in FIG. 6 except that the pilot signal PL in the second embodiment is a modulated signal. The pilot signal PL is a modulated signal having a bandwidth, which is distorted by the digital predistorter 20 and has its spectrum spread on both sides accordingly as indicated by PD. As compared with the pilot signals PL1 and PL2 which are tone signals, the detection sensitivity of the pilot signal PL in this embodiment is increased by a decoding circuit which performs error correction or the like in the receiver. The application of a spreading code to the pilot signal permits extraction of a pilot signal below the lowest receiving sensitivity of the receiver. Third Embodiment [0098]FIG. 10 illustrates in block form a third embodiment of the present invention, which differs from the first and second embodiments in that predistorters 20 1, 20 2 and DA converters 31 1 and 31 2 provided separately for the pilot signal and the transmission signal. The digital predistorters 20 1, 20 2 and the digital predistorter control part 50 therefor are identical in construction with those in the first and second embodiments. [0099] In this embodiment there are newly provided a frequency upconverting part 34 composed of a local oscillator 34A, a mixer 34B and a band-pass filter 34C, for frequency converting the output from the second digital predistorter 20 2 to a band different from that of the transmission signal S. This embodiment contemplates widening the band of the transmission signal. The first and second embodiments permits reduction of computational complexities for predistortion, generation and injection of the pilot signals and digital signal processing, but widening the band of the transmission signal is likely to cause shortage of the capacity of the DA converter 31. Further, since the pilot signal is injected into a band different from that of the transmission signal S, the DA converter 31 is required to be capable of performing digital-to-analog conversion of signals in bands above that of the transmission signal. In this respect, the third embodiment uses different digital predistorters 20 1, 20 2 and different DA converters 31 1, 31 2 for the transmission signal and the pilot signal, respectively. The provision of such independent digital-to-analog conversion routes offers increased flexibility in widening of the transmission signal or signal conversion for over sampling. The first and second digital predistorters 20 1 and 20 2 synchronously correct coefficients of each odd order under the control of the digital predistorter control part 50. Fourth Embodiment [0100]FIG. 11 illustrates in block form a fourth embodiment of the present invention, in which the pilot signal generator 12 in the fourth embodiment of FIG. 10 has the same configuration as that of the pilot signal generator 12 for generating a modulated signal in the FIG. 8 embodiment. This embodiment is also identical in operation with the third embodiment. As compared with the pilot signals PL1 and PL2 which are tone signals, the detection sensitivity of the pilot signal PL in this embodiment is increased by a decoding circuit which performs error correction or the like in the receiver. The application of a spreading code to the pilot signal permits extraction of a pilot signal below the lowest receiving sensitivity of the receiver. [0101] In the third and fourth embodiments of FIGS. 10 and 11, the first and second digital predistorters 20 1 and 20 2 may also be replaced with one digital predistorter. In such an instance, a band separator 30 is provided, as shown in FIG. 12, which performs signal processing for separating the transmission signal and the pilot signal at the output of the digital predistorter 20 through utilization of the difference in band between the transmission signal and the pilot signal. The transmission signal S and the pilot signal PL thus separated are processed in the respective routes in the same manner as in FIGS. 10 and 11. [0102] In the embodiments of FIGS. 10, 11 and 12 the transmission signal and the pilot signal are predistorted and converted from digital to analog form separately of each other, and the predistorted pilot signal is upconverted and combined with the predistorted transmission signal. FIG. 13 shows a modified form of the FIG. 10 embodiment. In this embodiment the predistorted transmission signal upconverted in the frequency upconverting part 33 by use of the carrier frequency fc and the predistorted pilot signal upconverted in the frequency upconverting part 34 by use of a carrier frequency fc′ different from the above-mentioned carrier frequency fc are combined by an adder 35, and the combined signal is applied to the amplifier 37. Further, the carrier signal of the carrier frequency fc′ from th local oscillator 34A is applied to the mixer 41 of the pilot signal component detecting part 40 to detect the pilot signal component. The illustrated modification is identical in construction and in operation with the FIG. 10 embodiment except the above. [0103] It is apparent that the embodiments of FIGS. 11 and 12 can also be modified as in the case of FIG. 13. For example, in the FIG. 11 embodiment the pilot signal generator 12 the pilot signal generator 12 for generating two tone signals in FIG. 13 is replaced with a pilot signal generator for generating a modified signal of a band narrower than that of the transmission signal. In the case of the FIG. 12 embodiment the circuit arrangement following the band separator 30 needs only to be the same as shown in FIG. 14; no description will be repeated in this respect. [0104]FIG. 15 shows, by way of example, a circuit configuration for increasing the pilot signal detecting sensitivity of the digital predistorter control part 50 in the first to fourth embodiments and in their modifications. In this case, however, the pilot signal generator 12 is one that combines two tone signals into the pilot signal as referred to previously in respect of FIG. 5. The FIG. 15 example is directed only to the third-order distortion. [0105] The digital predistorter control part 50 comprises a third-order distortion component extractor 50A and a third-order distortion controller 52A. The third-order distortion component extractor 50A comprises: a delay memory 1A11, a phase adjuster 1A12 and a gain adjuster 1A13 which constitute a fundamental wave generating path; a fifth-order distortion generator 1A21, a phase adjuster 1A22 and a gain adjuster 1A23 which constitute a fifth-order distortion generating path; a seventh-order distortion generator 1A31, a phase adjuster 1A32 and a gain adjuster 1A33 which constitute a seventh-order distortion generating path; and subtractors 1A14, 1A24 and 1A34. [0106] From the pilot signal component fed from the pilot signal generator 12 are generated a delayed fundamental wave component, a fifth-order distortion component and a seventh-order distortion component through the fundamental wave path, the fifth-order distortion generating path and the seventh-order distortion generating path, respectively. The delayed fundamental wave component, fifth-order distortion component and seventh-order distortion component of the pilot signal are sequentially subtracted by the subtractors 1A14, 1A24 and 1A34, respectively, from the pilot signal component detected in the frequency downconverting part 40, by which the third-order distortion component is left remaining, and the third-order distortion component is provided to the third-order distortion controller 52A. Based on the third-order distortion component fed thereto, the third-order distortion controller 52Acontrols the phase adjuster 23A and the gain adjuster 24A of the digital predistorter 20 as is the case with the third-order distortion controller 52A in FIG. 5. [0107] To reduce residues of the delayed fundamental wave component, the fifth distortion component and the seventh-order distortion component after the subtraction, the control part 50 of FIG. 15 adjusts the phases and amplitudes of the respective components by the phase adjusters 1A12, 1A22, 1A32 and the gain adjusters 1A13, 1A23, 1A33. These adjustments need only to be made at the time of device initialization because implementation of the digital predistorter control part 50 of FIG. 15 by digital signal processing does not cause any changes in electrical characteristics due to aging or temperature. With the same configuration as that of the digital predistorter control part 50 in FIG. 8, it is possible to extract the fifth- or seventh-order distortion component. The same goes for the case where the pilot signal is a modulated signal. Fifth Embodiment [0108] An equivalent circuit of an intrinsic region of a common FET (Field Effect Transistor) used in the power amplifier can be expressed, for example, as shown in FIG. 16A, in which Cgs represents the gate-source interterminal capacitance, Rg the gate resistance, Gm the transconductance, and Gd the drain conductance. The intermodulation distortion in FET is modeled in the form of power series of Cgs, Gm and Gd from the FIG. 16A equivalent circuit of the intrinsic region (see, for example, J. A. Higgins and R. L. Kuvas, �Analysis and improvement of intermodulation distortion in GaAs power FET's,� IEEE Transaction on Microwave Theory and Techniques, VOL. MTT-28, NO. 1, pp. 9-17, January 1980). Letting an instantaneous gate voltage be represented by Vg and an instantaneous drain voltage by Vd, C m(v g)=G m1 +G m2 V g +G m3 V g 2 +G m4 V g 3 +G m5 V g 4+ . . . (1) G d(V d)=G d1 +G d2 V d +G d3 V d 2 +G d4 V d 3 +G d5 V d 4+ . . . (2) C gs(V g)=C g1 +C g2 V g +C g3 V g 2 +C g4 V g 3 +C g5 V g 4+ . . . (3) [0109] From the above it is understood that the intermodulation distortion in FET occurs at the gate and the drain. [0110] The amplifier can be expressed in the form of such a circuit network as shown in FIG. 16B by use of FET equivalent circuit of FIG. 16A. The circuit network is composed of a gate-side matching circuit 37A, FET and a drain-side matching circuit 37A. The matching circuits 37A and 37B have different frequency characteristics. Because of this, the intermodulation distortion of the amplifier is affected by the frequency characteristics of the both gate- and drain-side matching circuits 37A and 37B. But the frequency characteristics in this case are not so wide in bandwidth as the operating frequency of FET, and they are limited to the bandwidth for amplification by the amplifier. [0111] In the conventional power series type predistorter by digital signal processing, no consideration is given to the frequency characteristics of the intermodulation distortion in FET (see, for instance, UK Patent Application GB2335812A). [0112] With a view to achieving a high degree of distortion suppression over a wide band, this embodiment compensates for the intermodulation distortion taking into account the frequency characteristics of the gate-side matching circuit 37A and the frequency characteristics of the drain-side matching circuit 37B separately of each other. What is important in FIG. 16B is that the input signal to the amplifier is influenced by the frequency characteristics of the gate-side matching circuit 37A and then applied to the FET equivalent circuit, wherein the intermodulation distortion is generated. That is, the input signal to which causes the intermodulation distortion is attributable comes under the influence of the frequency characteristics of the gate-side matching circuit 37A. Similarly, the frequency characteristics of the drain-side matching circuit 37B affects the distortion generated by FET. [0113] Accordingly, to compensate for the frequency characteristics of the distortion generated by FET, a frequency characteristic compensator is provided at the input side of each odd-order distortion generator in the power series predistorter, by which it is possible to compensate for the frequency characteristics of the distortion in conformity to the gate-side frequency characteristics of the amplifier. That is, the provision of the frequency characteristic compensator at the input side of each odd-order distortion generator implements the frequency characteristics that compensate for the frequency characteristics of the gate-side matching circuit 37A at the output of the power amplifier. [0114] Similarly, by placing a frequency characteristic compensator at the output side of each odd-order distortion generator in the digital predistorter, it is possible to provide compensation for the frequency characteristics of the distortion that conforms to the drain-side frequency characteristics of the amplifier. That is, the provision of the frequency characteristic compensator at the output side of each odd-order distortion generator implements the frequency characteristics that compensate for the frequency characteristics of the drain-side matching circuit 37B at the output of the power amplifier. That is, the provision of the frequency characteristic compensator at the output side of each odd-order distortion generator implements the frequency characteristics that compensate for the frequency characteristics of the drain-side matching circuit 37B at the output of the power amplifier. [0115] For example, the frequency characteristics T(f) of the intermodulation distortion by the gate-side matching circuit are expressed by the following equation (4) using Eq. (3). T(f)C g(V g)=T 1(f)C g1 +T 2(f)C g2 V g +T 3(f)C g3 V g 2 +T 4(f)C g4 V g 3 +T 5(f)C g5 V g 4 (4) [0116] From Eq. 84) it will be seen that the digital signal processing type predistorter needs to compensate for the frequency characteristics for each odd-order distortion generator. The same goes for the drain side. Further, the intermodulation distortions occur simultaneously at the gate-side and drain-side of FET, and the power series type predistorter configuration differ with the magnitude of each of the intermodulation distortions defined by Eqs. (1) to (3). The frequency characteristics of the intermodulation distortion by the amplifier described above in respect of FIG. 3 can be considered to be a combined version of the gate-side and drain-side frequency characteristics. The frequency characteristic compensator is provided so that frequency characteristics inverse to the combined frequency characteristics is imparted to the output from each odd-order distortion generator. The frequency characteristic compensator is placed at that one of the input and output terminal sides of FET at which the intermodulation distortion is dominant, or at either side. When it is disposed only at the output or input side of the odd-order distortion generator, the frequency characteristic compensator for compensating for the combined frequency characteristics of the intermodulation distortion cannot always achieve satisfactory compensation; in some cases, however, the compensation performance can be improved by placing the compensator at either of the input and output sides of the odd-order distortion generator. [0117] In this embodiment, the frequency dependence of the distortion suppression by the digital signal processing type predistorter is improved by using a frequency characteristic compensator which compensates for only the frequency characteristics of the gate-side matching circuit 37A and/or frequency characteristic compensator which compensates for the frequency characteristics of both the gate- and drain-side matching circuits 37A and 37B. [0118]FIG. 17 illustrates in block form a basic configuration of the fifth embodiment according to the present invention. The basic configuration includes: a digital predistorter 20 for predistorting the transmission signal S from the transmission signal generator 11; a DA converter 31 for converting the predistorted output to an analog transmission signal; a frequency upconverting part 33 for upconverting the analog transmission signal to a high-frequency transmission signal; a power amplifier 37 for amplifying the upconverted transmission signal; and a dividing part 38 for dividing the amplified output into two; a frequency downconverting part 40 for downconverting one of the two divided outputs; a distortion component detecting part 51 for detecting an odd-order distortion component from the downconverted signal; and a controller 5 for controlling a phase adjuster 23 and a gain adjuster 24 based on the detected odd-order distortion component. The distortion component detecting part 51 and the controller 5 constitute the digital predistorter control part 50. [0119] Moreover, in the digital predistorter 20 there is placed at the output side of a distortion generator 22 a frequency characteristic compensator 28 by which a characteristic inverse to the frequency characteristic of the power amplifier 37, shown in FIG. 3, is imparted to the distortion generated by the distortion generator 22, and the frequency characteristics for the distortion is controlled by he controller 5. [0120] The input signal S from the transmission signal generator 11 is branched to a linear transfer path 2L and a distortion generating path 2D of the predistorter 20. The power-series-model distortion generator 22 generates an odd-order distortion signal D by use of the input signal branched to the distortion generating path 2D. The frequency characteristic compensator 28 adjusts frequency dependent amplitude and phase characteristics of the distortion signal D to be inverse to the frequency characteristics of the amplifier 37. The output from the frequency characteristic compensator 28 is adjusted in phase and in gain by the phase adjuster 23 and the gain adjuster 24 to yield an adjusted distortion signal D′, which applied to the combiner 25. The signal branched to the linear transfer path 2L is provided to the delay memory 21, wherein the amount of delay is corrected relative to the signal on the distortion generating path 2D. The combiner 25 combines the signals S and D′ from the linear transfer path 2L and the distortion generating path 2D. [0121] In this configuration, too, in order to maintain a high degree of distortion compensation for a characteristic change of the power amplifier 37 by a temperature change or aging, the output from the power amplifier 37 is monitored by he distortion compensation detecting part 51 via the dividing part 38, and upon detecting a reduction in the distortion compression effect by the distortion component detecting part 51, the controller 5 changes parameters of the phase adjuster 23, the gain adjuster 24 and the frequency characteristic compensator 28. This ensures constant maintenance of a high degree of distortion compensation. Incidentally, as will be understood from the description given of FIGS. 16A and 16B, the frequency characteristic compensator 28 may be provided at the input side of the distortion generator 22 or at either of the input and output sides thereof as indicated by the broken line in FIG. 17. [0122] Turning now to FIG. 18, a description will be given of the principle on which high-precision distortion compensation can be implemented by the frequency characteristic compensator 28 in FIG. 17. Assume that when supplied with the input signal S shown on Row B, the power amplifier 37 of the frequency characteristics shown on Row A generates such a distortion DS as shown on Row C. To cancel such a distortion DS, the frequency characteristics of the frequency characteristic compensator 28 are rendered inverse to the frequency characteristics of the power amplifier 37 as shown on Row E, by which the frequency dependent amplitude and phase characteristics of the distortion D by the distortion generator 22 shown on Row D are adjusted to obtain a distortion D′ shown on Row F. The gain adjuster 28 adjusts the gain of the distortion produced by the distortion generator so that it has a level at which the distortion DS generated by the power amplifier 37 can be canceled, and the phase adjuster 23 adjusts the frequency characteristics of the frequency characteristic compensator 28 to be inverse to the frequency characteristics of the power amplifier 37. D′ indicates the adjusted characteristics. As a result, the output S+D′ from the combiner 25 is a combined version of the frequency-characteristic-compensated distortion D′ and the signal S as shown on Row G. The combined signal S+D′ applied via the DA converter 31 to the power amplifier 37, by which the frequency characteristics of the power amplifier 37 can be cancelled; accordingly, in the output SA from the power amplifier 37 there is cancelled the distortion as shown on Row H. [0123]FIG. 19 illustrates in block form a concrete embodiment based on the basic configuration depicted in FIG. 17. This embodiment comprises: a digital predistorter 20; a DA converter 31; a frequency upconverting part 33 composed of a local oscillator 33A, a mixer 33B and a band-pass filter 33C; a power amplifier 37; a directional coupler 38A and a signal extracting band-pass filter 38B forming a signal extracting part 38; a mixer 41 and a band-pass filter 42 forming a frequency downconverting part 40; and a digital distorter control part 50. The frequency downconverting part 40 includes an AD converter 44 for converting a downconverted extracted signal to a digital signal. The digital predistorter 20 is shown to handle the third, fifth and seventh-order distortion components, but the number of orders may be chosen as desired according to the device configuration used. [0124] The digital predistorter 20 using a power series model is configured to add output signals from a delay path which passes therethrough the fundamental wave component of the transmission signal and the path for generating each odd-order distortion by use of the power series. The odd-order distortion generators 22A, 22B and 22C each perform processing of raising the input transmission signal to the corresponding odd-order power. For instance, letting x represent the transmission signal, the third-order distortion generator raises x to 3rd power. The frequency characteristic compensators 28A, 28B and 28C are FIR (Finite Impulse Response) filters, and their coefficients are set and controlled by the coefficient controllers 53A, 53B and 53C. The output distortion signals from the distortion generators 22A, 22B and 22C are input to the FIR filters 28A, 28B and 28C, by which frequency dependent amplitude and phase characteristics of the distortion signals can be varied. [0125] The output signal from the power amplifier 37 is extracted by the directional coupler 38A and the band-pass filter 38B, and the extracted signal is downconverted by the frequency downconverting part 40. The input signal to the digital predistorter control part 50 is a digitized version of the downconverted signal by the AD converter 44. The digital predistorter control part 50 is made up of odd-order distortion component extractors 51A, 51B and 51C each formed by a distortion component extracting band-pass filter; distortion controllers 52A, 52B and 52C corresponding to the respective odd-order distortion components; and coefficient controllers 53A, 53B and 53C for controlling the coefficients of the FIR filters 28A, 28B and 28C of the respective odd orders. The odd-order distortion controllers 52A, 52B and 52C each control the corresponding ones of the variable gain adjusters 24A, 24B, 24C and the phase adjusters 23A, 23B, 23C for the outputs from the distortion generators 22A, 22B and 22C in the digital predistorter 20. Incidentally, the odd-order distortion controllers 52A, 52B, 52C and the coefficient controllers 53A, 53B, 53C constitute the distortion characteristic controller 5 in FIG. 17. [0126] The FIR coefficient controllers 53A, 53B and 53C for the respective odd orders each control the coefficients of the corresponding one of the FIR filters 28A, 28B and 28C. The odd-order distortion component extractors 51A, 51B and 51C each extract the corresponding one of the odd-order distortion component signal by a band-pass filter or the like. The odd-order distortion controllers 52A, 52B and 52C use the extracted signals to control, based on the outputs from the odd-order distortion generators 22A, 22B and 22C, the gain adjusters 52A, 52B, 52C and the phase adjusters 23A, 23B, 23C until the compensated amount of distortion reaches such a value that the adjacent channel leakage power ratio (i.e., the level ratio of the distortion component to the transmission signal) goes down below a predetermined value at the output of the power amplifier 37. At the same time, the frequency characteristics of the power amplifier 37 are extracted, and the coefficients of the respective FIR filters 28A, 28B and 28C accordingly. The parameter control can be implemented by use of various optimal algorithms. In the embodiment of FIG. 19, too, the FIR filters 28A, 28B and 28C may connected to only to the inputs or both the inputs and outputs of the third- fifth- and seventh-order distortion generators 22A, 22B and 22C as indicated by the broken lines. Sixth Embodiment [0127]FIG. 20 illustrates in block form an embodiment of a linear power amplifier that uses FFT's as the frequency characteristic compensators 28A, 28B and 28C of the digital predistorter 20. This embodiment is a modified form of the FIG. 19 embodiment, which uses, as each of the frequency characteristic compensators 28A, 28B and 28C (represented by 28A in this case), a set of an FFT (Fast Fourier Transform) part 28A1, a coefficient multiplier 28A2 and an IFFT (Inverse Fast Fourier Transform) part 28A3, instead of using the FIR filter. The same goes for the frequency characteristic compensators 28B and 28C. Except the above this embodiment is identical in construction with the FIG. 19 embodiment. Accordingly, the frequency characteristic control part 53 has the coefficient controllers 53A, 53B and 53C corresponding to the third-, fifth- and seventh-order distortions as is the case wit the frequency characteristic control part 53 in the FIG. 19 embodiment, but they are not shown. The same goes for the embodiments of FIGS. 21, 30 and 31 described later on. [0128] For example, the distortion signal from the third-order distortion generator 22A is applied to the FFT part 28A1, wherein it is Fourier transformed for each of plural samples to frequency domain samples. The amplitude of the sample at each frequency point is multiplied, by the coefficient multiplier 28A2, by the coefficient from the coefficient controller 53A, and the multiplied output is inverse Fast Fourier transformed by the IFFT part 28A3 into a time domain sample. The same goes for the other frequency characteristic compensators 28B and 28C. The frequency characteristic control by FFT is implemented by controlling each multiplication coefficient of FFT as mentioned above. The digital predistorter control part 50 controls the gain adjuster, the phase adjuster and the multiplication coefficient of FFT for each odd order so that the level of the distortion component by the power amplifier 37 relative to the transmission signal goes down below a predetermined value. In this embodiment, too, the frequency characteristic compensators 28A, 28B and 28C may be connected only to the inputs or both of the inputs and outputs of the third-, fifth- and seventh-order distortion generators 22A, 22B and 22C as indicated by the broken lines. Seventh Embodiment [0129]FIG. 21 illustrates in block form a seventh embodiment of the present invention. This embodiment is a modified form of the FIG. 19, which is configured to make an adjustment to the digital predistorter 20 by use of the two pilot signals shown in FIG. 5. The odd-order distortion generators 22A, 22B and 22C of the digital predistorter 20 using a power series model each performs processing of raising the transmission signal and the pilot signal input thereto the corresponding odd order. [0130] The digital predistorter control part 50 is identical in construction with the digital predistorter control part 50 in each of the embodiments of FIGS. 19 and 20. The odd-order distortion controllers 52A, 52B and 52C control the gain adjusters 24A, 24B, 24C and the phase adjusters 23A, 23B, 23C of those of the distortion component generators 22A, 22B and 22C of the digital predistorter 20 which correspond to the controllers 52A, 52B and 52C, respectively. The coefficient controllers 53A, 53B and 53C (not shown) of the frequency characteristic control part 53 control the coefficients of the frequency characteristic compensators 28A, 28B and 28C, respectively. Since two tone signals of the same level as the pilot signal, odd-order distortion components appearing near the tone signals at the output of the power amplifier 37 are extracted by the odd-order distortion component extracting band-pass filters functioning as the distortion component extractors 51A, 51B and 51C of the respective odd orders. While the digital predistorter control part 50 in this embodiment is implemented by digital signal processing, it may also be formed by analog circuits. The frequency characteristic compensation utilizes the distortion components PD3L and PD3H that appear in the bands lower and upper than that of the pilot signal as described previously in respect of FIG. 6. [0131] The frequency characteristic compensators 28A, 28B and 28C may be formed by the FIR filters as in the FIG. 19 embodiment; alternatively, they may each be formed using the FFT parts, the coefficient multiplier and the IFFT part. The frequency characteristic compensation corrects the frequency characteristics by use of the upper and lower distortion signals PD3H and PD3L in FIG. 6. For example, the coefficient controllers 53A, 53B and 53C each interpolate the detected values of the upper and lower distortion components PD3H and PD3L from the corresponding one of the odd-order distortion component extractors 51A, 51B and 51C to thereby estimate the frequency characteristics from a monitor value. The FIR filters or FFT's forming the frequency characteristic compensators 28A, 28B and 28C each set the interpolated value in the corresponding coefficient multiplier. Thereafter each filter or FFT adjusts the multiplication coefficient until a predetermined distortion suppression-frequency characteristic is obtained. The required control can be effected by various optimal algorithms. [0132] Even if modulated waves are used as the pilot signals in place of the tone signals, the same results as mentioned above are obtainable. Furthermore, a different predistorter may also be used for each of the pilot signal and the transmission signal. In this embodiment, too, the frequency characteristic compensators 28A, 28B and 28C may be connected only to the inputs or both of the inputs and outputs of the third-, fifth- and seventh-order distortion generators 22A, 22B and 22C as indicated by the broken lines. [0133]FIG. 22 illustrates in block form a modified form of the FIG. 21 embodiment, in which the pilot signal generator 12 generates a modulated signal as in the FIG. 8 embodiment. Since this embodiment is identical in construction with the FIG. 21 embodiment except the above, no description will be repeated. Besides, the digital predistorter in the FIG. 12 embodiment and the digital predistorters 20 1 and 20 2 in the embodiments of FIGS. 13 and 14 may also be modified to have the same configuration as that of the digital predistorter 20 shown in FIG. 21, for instance, and the digital predistorter control part 50 in each of the embodiments shown in FIGS. 12, 13 and 14 may also be configured similar to the control part 50 in FIG. 21. Eighth Embodiment [0134]FIG. 23 illustrates in block form a basic configuration of a modification of the FIG. 17 embodiment adapted to adjust the digital predistorter 20 by use of two pilot signals shown in FIG. 5. In this embodiment there are additionally provided a pilot signal generator 12 for generating two pilot signals PL1 and PL2 and an adder 15 for adding together the pilot signals and the transmission signal S, and the controller 5 controls the pilot signal generator 12 to vary the frequency interval between the pilot signals PL1 and PL2 of the same amplitude. In the digital predistorter control part 50 there is provided a storage part 55 for storing the gain and phase obtained from the frequency characteristics of the detected distortion component. [0135] As referred to previously, the transmission signal S may be a baseband signal or IF signal. In the latter case, it is recommended that the frequencies of the pilot signals PL1 and PL2 be set at fIF−fi/2 and fIF+fi/2, respectively, with respect to a predetermined intermediate frequency fIF. When the transmission signal S is a baseband signal, a signal A cos πfit of an amplitude A and a frequency fi/2 is subjected to quadrature modulation in the frequency upconverting part 33 by use of a carrier signal of a frequency fc; that is, by obtaining the real part of the result of multiplication of cos πfit by (cos 2πfct+j sin 2πfct), the two pilot signals of frequencies fIF−fi/2 and fIF+f i/2 are generated in the transmission frequency band. Accordingly, the pilot signal generator 12 needs only to generate a tone signal of a frequency fi/2 in practice. Since the signal expressed by cos πfit can be regarded as having positive and negative frequency components, as given by the following equation cos πf i t=(exp jπf i t+exp−jπf i t)/2 (5) [0136] the frequencies of the two pilot signal PL1 and PL2 in the baseband will hereinafter be expressed by −fi/2 and +fi/2, respectively. [0137] The intermodulation distortions, which are created when the pilot signals upconverted in the frequency upconverting part 33 are amplified by the power amplifier 37, are detected in the distortion component detecting part 51 of the digital predistorter control part 50 via the dividing part 38 and the frequency downconverting part 40. The controller 5 adjusts the parameters of the gain adjuster 24, the phase adjuster 23 and the frequency characteristic compensator 28 so that the intermodulation distortions go down below a predetermined value of the adjacent channel leakage power ratio. The use of two pilot signals facilitates extraction of the odd-order distortion components modeled by the power series, allowing ease in adjustment of the frequency characteristic compensator 28, the gain adjuster 24 and the phase adjuster 23 in the digital predistorter 20. [0138] Through variations of the two pilot signal frequencies −fi/2 and +fi/2 by the controller 5, the frequency interval fi between the two upconverted pilot signals in the transmit frequency band undergoes corresponding variations, causing changes in the frequency of occurrence of each intermodulation distortion on the frequency axis accordingly. Thus, by changing the pilot signal frequencies −fi/2 and +fi/2 at fixed intervals, it is possible to determine the gain and phase of each compensation distortion that achieves a predetermined adjacent channel leakage power ratio for the frequency of occurrence of each resulting intermodulation distortion. [0139] By interpolating gains and phases discretely obtained on the frequency axis by the above method, continuous frequency characteristics for the compensation distortions can be obtained. The thus obtained frequency characteristics are implemented by the frequency characteristic compensator 28 and imparted to the compensation distortions. [0140]FIG. 24 is a flowchart showing the procedure for obtaining the characteristics of the frequency characteristic compensator 28, which will be described below with reference to the frequency diagram of FIG. 25. [0141] Step S1: Initialize the value of a variable i at 1. [0142] Step S2: Generate two digital tone signals of baseband frequencies −fi/2 and +fi/2 (hence, spaced fi apart) and equal in amplitude as the pilot signals PL1 and PL2 (FIG. 25�Row A). These signal are combined, then the combined signal is upconverted with the center frequency fc in the frequency upconverting part 33, and when the upconverted signal is input to the power amplifier 37, intermodulation distortions PD3H and PD3L of frequencies fc+3fi/2 and fc−3fi/2, for example, expressed by the following equations occur at the output of the power amplifier 37 (Row B): B 3H cos 2π(f c +f i/2+f i)t=B 3H cos 2π(f c+3f i/2)t (6) B 3L cos 2π(f c −f i/2−f i)t=B 3L cos 2π(f c−3f i/2)t (7) [0143] where B3H and B3L represent the amplitudes of distortions at frequencies upper and lower than the carrier frequency fc, respectively. [0144] To cancel the intermodulation distortions PD3H and PD3L, the predistorter 20 outputs a signal with compensation distortions DL′ and DH′ added to the pilot signals PL1 and PL2 (Row C). This signal is upconverted in the frequency upconverting part 33, and the upconverted signal is applied to the power amplifier 37. The output signal from the power amplifier 37 becomes a signal compensated for by the digital predistorter 20 (Row D). The gain adjuster 24, the phase adjuster 23 and the frequency characteristic compensator 28 are adjusted in a manner to cancel the intermodulation distortions PD3H and PD3L. Incidentally, the gain adjuster 24 impart a fixed gain G to frequency, and the phase adjuster 24 impart a fixed phase change P to frequency. [0145] Step S3: Set the gain G in the gain adjuster 24 and the phase P in the phase adjuster 23. These values may be set as desired, but may preferably be set such that the adjacent channel leakage power ratio becomes relatively small. [0146] Step S4: Extract the third-order intermodulation distortions in the output from the power amplifier 37 by the distortion component detecting part 51, and make a check to see if the upper and lower intermodulation distortions PD3H and PD3L each meet the requirement that the adjacent channel leakage power ratio be smaller than a predetermined value. If only the upper or both the upper and lower distortions do not meet the requirement, go to step S5. When only the lower distortion does not satisfy the requirement, go to step S7, and when either distortion satisfies the requirement, go to step S9. [0147] Step S5: If the upper or both of the upper and lower distortions PD3H and PD3L do not the above-mentioned requirement, the gain Gi and phase Pi corresponding to the frequency fc+3fi/2 of the frequency characteristic compensator 28 are each varied as predetermined. [0148] Step S6: Make a check to see if the upper distortion PD3H meets the requirement, and if not, return to step S5 and repeat the same processing. When the upper distortion satisfies the requirement, go back to step S4 and make the check again. [0149] Step S7: When only the lower distortion PD3L does not satisfy the requirement, the gain Gi′ and phase Pi′ corresponding to the frequency fc−3fi/2 of the frequency characteristic compensator 28 are each varied as predetermined. [0150] Here, assume that the gains Gi and Gi′ of the frequency characteristic compensator 28 represent differences from the gain G of the gain adjuster 24 and that the phases Pi and Pi′ are differences from the phase change P of the phase adjuster 23. [0151] Step S8: Make a check to see if the lower distortion PD3L meets the requirement, and if not, go back to and repeat step S7. If the distortion meets the requirement, make sure in step S4 that the upper and lower distortions both satisfy the requirement, and go to step S9. Alternatively, skip step S4 and proceed directly to step S9. [0152] Step S9: When the upper and lower distortions PD3H and PD3L both satisfy the requirement that the adjacent channel leakage power ratio be smaller than a predetermined value, store the gains G1, G1′ and the phases Pl, Pl′ at that time in a storage part 55, and determine if i=N. [0153] Step S10: If not i=N, then increment i by 1 and return to step S2. And set the frequency intervals between the pilot signals set at f2 (in the examples of FIGS. 26A, 26B, 27A and 27B described later on, the frequency spacing fi decreases with an increase in the variable i), and as is the case with the frequency spacing f1, perform steps S3 through S9 to obtain the gains and phases G2, G2′ and P2, P2′ of the frequency characteristic compensator 28 each of which satisfies the requirement that the adjacent channel leakage power ratio be smaller than a predetermined value, and store them in the storage part 55. In this instance, the values of the gain adjuster 24 and the phase adjuster 23 are fixed at G and P, respectively. [0154] By repeating N rounds of processing while changing the frequency interval between the two pilot signals PL1 and PL2 from i=1 to i=N, G1 to GN, G1′ to GN′, P1 to PN and P1′ to PN′ are stored in the storage part 55. [0155] Step S11: Obtain the frequency characteristics for compensation distortion by use of the values G1 to GN, G1′ to GN′, P1 to PN and P1′ to PN′ obtained as described above. The frequency characteristics can be obtained by interpolating the gains G1 to GN, G1′ to GN′ and the phases P1 to PN and P1′ to PN′ between point as shown FIGS. 26A, 26B, or 27A, 27B. FIGS. 26A and 26B show linear interpolation, and FIGS. 27A and 27B show polynomial interpolation; but other interpolation schemes, such as spline and Lagrangean interpolation schemes can also be used. [0156] By interpolating the discretely obtained gains and phases as mentioned above, the frequency characteristics of the distortion component are implemented by the frequency characteristic compensator 28. The ultimate frequency characteristics for the distortion component are a combined version of the frequency characteristics of the gain adjuster 24, the phase adjuster 23 and the frequency characteristic compensator 28. For higher-precision distortion compensation, the frequency spacing of the pilot signals is further reduced. While the above description has been given of the third-order distortion alone, the above-described method can be used for compensation for fifth- or higher-order distortion as well. Ninth Embodiment [0157]FIG. 30 illustrates a more specific configuration of the FIG. 23 embodiment, which uses the digital predistorter 20 in which the frequency characteristic compensators 28A, 28B and 28C are formed by FIR filters as in the FIG. 19 embodiment. Let is be assumed that the pilot signal generator 12 generates digital tone signals PL1 and PL2 of variable frequencies expressed by −fi/2 and +fi/2. The digital predistorter control part 50 further includes a frequency controller 54 for controlling the oscillation frequency fi of the pilot signal generator 12 in correspondence to the control by the frequency characteristic control part 53. This embodiment is identical in construction with the FIG. 19 embodiment except the above. [0158] The two tone signals spaced fi apart and equal in amplitude are input as the pilot signals PL1 and PL2 to the digital predistorter 20, which outputs a signal with compensation distortions added to the pilot signals. The output signal is converted by the DA converter 31 to an analog signal, which is applied to the frequency upconverting part 33 and upconverted therein to a high-frequency carrier signal of the center frequency fc. The high-frequency signal is amplified by the power amplifier 37. The compensation distortions created by the digital predistorter 20 are so set as to provide distortion compensation throughout the transmission route. Accordingly, the compensation distortions in the input signal to the power amplifier 37 and in the output signals from the digital predistorter may differ from each other. That is, a desired device for changing the phase and amplitude of the signal may be inserted between the output of the digital predistorter 20 and the input of the power amplifier 37. [0159] As is the case with the FIG. 19 embodiment, the intermodulation distortion component is extracted by the directional coupler 38A and the band-pass filter 38B, and downconverted in the frequency downconverting part 40. The input signal to the digital predistorter control part 50 is a digitized signal of the downconverted signal. The compensation for the third-order distortion will be described below by way of example. The third-order distortion component extractor 51A extracts, by upper band-pass filter and a lower band-pass filter, the upper and lower intermodulation distortion signals that are third-order distortion components. The gain adjuster 24A, the phase adjuster 23A and the frequency characteristic compensator 28A use the extracted signals to vary the amplitude and phase of the output from the third-order distortion signal generator until the distortion compensation reaches such a value that the adjacent channel leakage power ratio at the output of the power amplifier 38 goes down below a predetermined value. [0160] The procedure of obtaining these compensation parameters begins with setting the gain G of the gain adjuster 24A and the phase P of the phase adjuster 23A as referred to previously in respect of FIG. 23. These values may be set as desired, but may preferably be set such that the adjacent channel leakage power ratio becomes relatively small. [0161] Next, the gain G1 and the phase P1 of the frequency characteristic compensator 28A at the upper frequency (fc+3f1/2) and the gain G1′ and the phase P1′ at the lower frequency (fc−3f1/2) are adjusted so that the adjacent channel leakage power ratio becomes lower than a predetermined value. This can be done by use of various optimization algorithms such as the least square estimation method and the steepest descent method. Next, the frequency interval between the two pilot signals of the same amplitude is changed to f2, and G2, G2′ and P2, P2′ are calculated. This procedure is repeated N times to obtain those gains and phases G1 to GN, G1′ to GN′, P1 to PN and P1′ to PN′ of the frequency characteristic compensator 28 for the frequencies f1 to fN which satisfy the requirement that the adjacent channel leakage power ratio be smaller than a predetermined value. The thus obtained gain and phase values can be interpolated using the linear, polynomial, Lagrangean, or spline interpolation scheme. The tap coefficients of the FIR filter are se by the controller such that the gain and frequency characteristics obtained by interpolation are implemented. [0162] While the above description has been given only of the third-order distortion, compensation for fifth- higher-order distortion can also be achieved by the above-described method. In such a case, intermodulation distortion corresponding to the odd-order distortion to be compensated for is extracted. The FIR filters 28A, 28B and 28C may also be disposed at the input sides of the odd-order distortion generators 22A, 22B and 22C. [0163] The amplitude and phase of the distortion component in the output from the power amplifier 37 varies due to temperature or aging. Therefore, to provide high-precision compensation for distortions at all times, it is necessary to adaptively control setting of the gain adjusters 24A, 24B, 24C, the phase adjusters 23A, 23B, 23C and the frequency characteristic compensators 28A, 28B, 28C. In this embodiment the use of two pilot signals enables their adaptive control. Tenth Embodiment [0164]FIG. 31 illustrates in block form a modified form of the FIG. 30, in which the frequency characteristic compensators 28A, 28B and 28C are formed using the three sets of FFT part, coefficient multiplier and IFFT part 28A1, 28A2, 28A3-28B1, 28B2, 28B3-28C1, 28C2, 28C3 as in the FIG. 20 embodiment, instead of using the FIR filters. As described previously in respect of FIG. 20, the output signals from the distortion generators 22A, 22B and 22C are converted to frequency domain signals by Fourier transform processing in the FFT parts 28A1, 28B1 and 28C1, then the frequency domain signals are multiplied by the frequency compensation characteristics by the coefficient multipliers 28A2, 28B2 and 28C2, and the multiplied output signals are inversely transformed to time domain signals in the IFFT parts 28A3, 28B3 and 28C3. The digital predistorter control part 50 controls gain adjusters 2A, 24B, 24C, and the phase adjusters 23A, 23B, 23C, and the multiplication coefficients of the frequency characteristic compensators 28A, 28B and 28C so that the distortion components in the output from the power amplifier 37 each achieve the predetermined adjacent channel leakage power ratio. The method for setting the coefficients of the frequency characteristic compensators 28A, 28B and 28C by use of the pilot signal is the same as described previously in respect of the FIG. 30 embodiment. [0165] The configuration of the digital predistorter 20 and the digital predistorter control part 50 shown in FIGS. 10 and 20 (or FIGS. 30 and 31) may also be applied to he two digital predistorters 20 1, 20 2 and the configuration of the digital predistorter control part 50 in the embodiments of FIGS. 10, 22 and 13. Similarly, the configuration of the digital predistorter 20 and the configuration of the digital predistorter control part 50 shown in FIGS. 19 and 20 (or FIGS. 30 and 31) may also be applied to the digital predistorter 20 and the digital predistorter control part 50 in FIGS. 12 and 14. [0166] While in the above FIR filters have been described to be used as the frequency characteristic compensators, they may be replaced with IIR (Infinite Impulse Response ) filters. Eleventh Embodiment [0167] The embodiment FIG. 23 and the embodiments of FIGS. 30 and 31 are configured to determine the frequency characteristics of the frequency characteristic compensators 28 (29A, 28A, 28C) while sequentially changing the frequency intervals Δf between the two pilot signals PL1 and PL2 of the same amplitude. In the embodiment described below, however, the frequencies of the pilot signals are fixed, and the frequencies of the high-frequency pilot signals are sequentially changed by steps of Δf in the working band of the power amplifier by sequentially changing the upconverting frequency, then intermodulation distortions at the respective frequencies are detected, and the characteristics of the frequency characteristic compensator 28 are determined accordingly. [0168] This embodiment will be described below with reference to FIG. 32. [0169] As is the case with the FIG. 30 embodiment, this embodiment comprises: a pilot signal generator 12; an adder 15; a digital predistolter 20; a DA converter 31; a frequency upconverting part 33; a power amplifier 37; a divider 38; a frequency downconverting part 40; and a digital predistorter control part 50. [0170] This embodiment differs from the FIG. 30 embodiment in that instead of changing the frequencies of the pilot signals, a frequency controller 54 controls the local oscillation frequency of the upconverting part to change so that the frequencies of the pilot signals undergo sequential variations in the operating band of the power amplifier 37 while at the same time the controller 54 correspondingly changes the oscillation frequency of the local oscillator 45 in the frequency downconverting part 40 to convert the distortion components of the pilot signals to the base band. In this embodiment the upconverting part 33 is configured to perform upconversion in two stages. That is, a local oscillator 33A1 of a variable frequency fIF, a mixer 33B1 and a band-pass filter 33C1 perform the first-stage upconversion to convert the output from the DA convert 31 to an IF signal. A local oscillator 33A2 of a fixed frequency fc′, a mixer 33B2 and a band-pass filter 33C2 perform the second-stage upconversion to convert the IF signal to a high-frequency signal. [0171] Since the local oscillation frequency fIF for conversion to the IF signal is sufficiently lower than the local oscillation frequency (carrier frequency ) fc for upconversion in the case of FIG. 30, such two-stage upconversion provides increased accuracy in setting the frequency for upconverting the baseband signal that is the output from the DA converter 31. Theoretically, however, the upconverting part 33 may be of a single-stage configuration as in the FIG. 30 embodiment. [0172] Incidentally, in this embodiment a series connection of the phase adjuster 23A the gain adjuster 24A in FIG. 30 is referred to as a vector adjuster 234A in the digital predistorter 20, and also vector adjusters 234B and 234C are each representative of a similar series connection; the same goes for other embodiment. [0173] In this embodiment, too, the frequency characteristic compensators 28A, 28B and 28C may be disposed at the input sides or both of the input and output sides of the third-, fifth- and seventh-order distortion generators 22A, 22B and 22C as indicated by the broken lines. [0174]FIG. 33 is a flowchart showing a control procedure for setting the characteristics of the frequency characteristic compensators 28A, 28B and 28C in the FIG. 32 embodiment. This setting takes place during a non-signal transmission period. [0175] Step S1: The frequency characteristic control part 53 sets the frequency fIF for converting the pilot signals to an IF signal in the local oscillator 33A1 of the frequency upconverting part 33. [0176] Step S2: The pilot signals PL1 and PL2 are input to the digital predistorter 20. The pilot signals are then provided from the digital predistorter 20 to the DA converter 31 for conversion to analog form, after which they are subjected to the two-stage frequency upconversion in the upconverting part 33, thereafter being input as an RF signal to the power amplifier 37. [0177] Step S3: The output RF signal from the power amplifier 37 is divided into two, one of which is provided to the frequency downconverting part 40 to generate pilot signal components containing distortion components in the baseband are generated. [0178] Step S4: The distortion extractors 52A, 52B and 52C extract respective odd-order distortion components. At this time, the distortion components of each odd order are detected at frequencies upper and lower than the fundamental wave. [0179] Step S5: The odd-order distortion controllers 52A, 52B and 52C control the phases and gains of the odd-order distortions by the vector adjusters 234A, 234B,and 234C of the digital predistorter 20 in manner to minimize the odd-order distortion components being detected. The set values in the frequency characteristic compensators 28A, 28B and 28C to minimize the odd-order distortion components are stored in the storage part 55 in correspondence to the respective odd-order distortion components. The odd-order distortion components may be adjusted to be smaller than a certain set value. And the set values may be set by external setting means like a keyboard. [0180] Step S6: The frequency characteristic control part 53 makes a check to determine whether the repeat count of a series of processing in steps S1 through S5 has reached a predetermined value, that is, whether the frequency sweep has been completed, and if so, ends the setting of the frequency characteristics. [0181] Step S7: If it is determined in step S6 that the frequency sweep is not complete, increment the set frequency fIF to fIF+Δf, and return to step S1 to repeat the series of steps S1 through S5. [0182] In the FIG. 32 embodiment, too, the frequency characteristic compensators 28A, 28B and 28C may be disposed at the input sides or both of the input and output sides of the respective odd-order distortion generators 22A, 22B and 22C as indicated by the broken lines. When the frequency characteristic compensators 28A, 28B and 28C are disposed at both input and output sides of the odd-order distortion generator 22A, 22B and 22C, the processing of FIG. 33 is performed separately for the input- and output-side frequency characteristic compensators to set their characteristics. [0183] As referred to previously in respect of FIGS. 16A and 16B, the nonlinearity of the power amplifier is determined by the relationship of nonlinearity dependence between the input and output sides. When the gate side (input side) and the drain side (output side) exert different influence on the frequency characteristics of the intermodulation distortions by the power amplifier, the provision of the frequency characteristic compensator only at the input or output side of each odd-order distortion generator may sometimes make it difficult to render the frequency characteristics of the frequency characteristic compensator obtained by the FIG. 3 procedure sufficiently inverse to the frequency characteristics of the intermodulation distortions by the power amplifier. By disposing the frequency characteristic compensator at either side of each odd-order distortion generator and controlling it independently of the others, it is possible to obtain characteristics for flattening the frequency characteristics at either side of the power amplifier, that is, frequency characteristics inverse to those of the intermodulation distortions by the power amplifier. [0184]FIG. 34 illustrates in block form a modified form of the FIG. 32 embodiment. In this embodiment the pilot signals and the transmission signal are predistorted by independent digital predistorters 20 1 and 20 2 as in the FIG. 10 embodiment. The digital predistorters 20 1 and 20 2 are identical in construction with the predistorter 20 in the FIG. 3 embodiment. The output from the digital predistorter 20 2 for the pilot signals is converted by a DA converter 31 2 to an analog signal, which is frequency converted in a first frequency converting part 34 to a frequency band different from that of the transmission signal. By sweep control of the set frequency of the local oscillator 34A of the frequency upconverting part 34 by the digital predistorter control part 50, the pilot signal frequency in the working band of the power amplifier 37 is sweep-controlled. The two digital predistorters 20 1 and 20 2 simultaneously control parameters in the digital predistorter control part 50. [0185] In this way, the digital predistorter can be configured taking into account the frequency characteristics of the power amplifier. Effect of the Invention [0186] As described above, according to the present invention, the pilot signal components are extracted directly from the output of the power amplifier 37 and the odd-order distortion components of a power series model of the digital predistorter are directly feedback-controlled-this permits implementation of a linear power amplifier with small secular and temperature variations. [0187] Moreover, since the odd-order distortions generated by the odd-order distortion generators are compensated for by frequency characteristics inverse to those of the power amplifier, distortions by the power amplifier can be canceled over a wide band. [0188] The present invention produces such effects as listed below. [0189] (1) High-precision distortion compensation can be achieved. [0190] (2) Simple configuration is possible. [0191] (3) A miniature transmitter can be offered. [0192] (4) The distortion compensation can be held optimal for temperature or secular variations. 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