Source: http://www.google.com/patents/US8058131?dq=5,838,906
Timestamp: 2016-09-26 21:43:44
Document Index: 252401466

Matched Legal Cases: ['application No. 2001', 'Application No. 200710078922', 'Application No. 02', 'Application No. 02290504', 'Application No. 08105801', 'Application No. 2001', 'Application No. 2001']

Patent US8058131 - Semiconductor integrated circuit device and method of producing the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor integrated circuit device includes a substrate, a nonvolatile memory device formed in a memory cell region of the substrate, and a semiconductor device formed in a device region of the substrate. The nonvolatile memory device has a multilayer gate electrode structure including a tunnel...http://www.google.com/patents/US8058131?utm_source=gb-gplus-sharePatent US8058131 - Semiconductor integrated circuit device and method of producing the sameAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8058131 B2Publication typeGrantApplication numberUS 12/949,046Publication dateNov 15, 2011Filing dateNov 18, 2010Priority dateJul 5, 2001Fee statusPaidAlso published asCN1310329C, CN1396660A, CN100459133C, CN101026169A, EP1274132A2, EP1274132A3, EP1274132B1, EP2019430A1, US7538376, US7858463, US20030008458, US20090269893, US20110065248Publication number12949046, 949046, US 8058131 B2, US 8058131B2, US-B2-8058131, US8058131 B2, US8058131B2InventorsHiroshi Hashimoto, Koji TakahashiOriginal AssigneeFujitsu Semiconductor LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (40), Non-Patent Citations (7), Classifications (28), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor integrated circuit device and method of producing the same
US 8058131 B2Abstract
1. A method of producing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a semiconductor structure comprising a tunnel insulating film covering a memory cell region of a substrate and a gate insulating film covering a logic device region of the substrate;
(b) depositing a silicon film on the semiconductor structure formed in said step (a) so that the silicon film covers the tunnel insulating film in the memory cell region and the gate insulating film in the logic device region;
(c) forming a first gate electrode in the memory cell region by selectively patterning the silicon film with the silicon film being left in the logic device region;
(d) forming a protection oxide film so that the protection oxide film covers the first gate electrode in the memory cell region and the silicon film in the logic device region;
(e) forming diffusion regions on both sides of the first gate electrode in the memory cell region by performing ion implantation of an impurity element into the substrate with the first gate electrode and the silicon film being employed as masks;
(f) forming a second gate electrode in the logic device region by patterning the silicon film; and
(g) forming diffusion regions in the logic device region by performing ion implantation with the second gate electrode being employed as a mask,
whereby a nonvolatile memory device is formed in the memory cell region and a semiconductor device is formed in the logic device region.
2. The method as claimed in claim 1, wherein the logic device region comprises first and second device regions;
said step (a) forms first and second gate insulating films in the first and second device regions, respectively, the second insulating film being thicker than the first insulating film;
said step (f) forms third and fourth gate electrodes in the first and second device regions, respectively, by patterning the second silicon film; and
said step (g) forms diffusion regions in the first and second device regions by employing the third and fourth gate electrodes being employed as masks, respectively.
4. The method as claimed in claim 2, wherein each of the third and fourth gate electrodes comprises a polycide or polymetal structure including a silicon film doped with an n-type or p-type dopant.
12. The method as claimed in claim 1, wherein the second gate electrode comprises a polycide or polymetal structure including a silicon film doped with an n-type or p-type dopant. Description
The present application is a Divisional application of U.S. application Ser. No. 12/285,289, filed Oct. 1, 2008, which is a Divisional of U.S. application Ser. No. 10/083,533, filed on Feb. 27, 2002 which is based on Japanese priority application No. 2001-205188 filed on Jul. 5, 2001, the entire contents of which are hereby incorporated by reference.
Next, in the step of FIG. 1L, the resist pattern 19A is removed, and a new resist pattern 19B is formed to cover the regions B and C and leave the region A exposed. Further, in the step of FIG. 1L, by using the resist pattern 19B as a mask, ion implantation of As+ is performed with a dose of 5�1014 to 5�1015 cm−2 at accelerating voltages ranging from 30 to 50 keV. As may be replaced by P+. As a result, an impurity concentration is increased in the n-type diffusion region 11 b and at the same time, a yet another n-type diffusion region 11 c is formed in the flash memory cell region A by using the multilayer gate electrode structure 16F as a self-alignment mask. At this point, the step of FIG. 1K may be deleted.
Further, in the step of FIG. 1O, sidewall insulating films 16 s are formed on both sides of each of the multilayer gate electrode structure 16F, the gate electrode 16B, and the gate electrode 16C by depositing and performing etchback on a CVD oxide film. In the step of FIG. 1P, a resist pattern 19E is formed to cover the flash memory cell region A and leave the low-voltage operation transistor region B and the high-voltage operation transistor region C exposed. Further, by performing ion implantation of a p-type or n-type impurity element with the resist pattern 19E and the gate electrodes B and C serving as a mask, p-type or n-type diffusion regions 11 f are formed on both sides of the gate electrode 16B in the Si substrate 11 in the region B, and similarly, p-type or n-type diffusion regions 11 g are formed on both sides of the gate electrode 16C in the Si substrate 11 in the region C. A low-resistance silicide film of, for instance, WSi or CoSi may be formed as required on the surface of each of the diffusion regions 11 f and 11 g by silicide processing.
Indeed, such a problem is prevented from occurring if the protection oxide film 18 is not formed. However, without formation of the protection oxide film 18, electrons retained in the amorphous silicon pattern 13A (hereinafter, also referred to as a floating gate electrode pattern 13A) are dissipated to the sidewall insulating films 16 s formed by CVD and etchback in the step of FIG. 1O as shown in FIG. 3B so that information stored in the flash memory device is lost in a short period of time. On the other hand, with the protection oxide film 18 that is a high-quality thermal oxide film hardly allowing a leakage current being formed on the sidewalls of the floating gate electrode pattern 13A, the electrons injected into the floating gate electrode pattern 13A are stably retained therein as shown in FIG. 3A.
In the step of FIG. 9G, which corresponds to the above-described step of FIG. 1O, the sidewall insulating films 16 s are formed on each of the multilayer gate electrode structure 16F and the gate electrodes 16B and 16C. In the step of FIG. 9H, which corresponds to the above-described step of FIG. 1P, the flash memory cell region A is covered with the resist pattern 19E. Further, with the gate electrodes 16B and 16C and the sidewall insulating films 16 s being used as self-alignment masks, the diffusion regions 11 f and 11 g are formed in the Si substrate 11 in the regions B and C, respectively, by performing ion implantation of an n-type or p-type impurity element therein.
Further in this embodiment, the amorphous silicon film 13 is not patterned in the regions B and C when the thermal oxidation step of FIG. 12D is performed. Therefore, as shown in FIG. 13B, no bird' beaks of the thermal oxide film penetrate under the gate electrodes 13B and 13C. This stabilizes the threshold characteristic and the operation characteristic of each MOS transistor formed on the Si substrate 11 on which the flash memory device is formed as well. The improvements in the threshold characteristic and the operation characteristic are remarkable in a low-voltage operation transistor having a short gate length and a thin gate oxide film.
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22, 2008, issued in corresponding Application No. 08105801.8-1235.5International Business Machines, "A single-layer Polysilicon EEPROM memory cell using diffusion gate"; Jan. 1, 1999; Research Disclosure. Mason Publications, Hampshire, GB, XP007123866; ISSN: 0374-4353.pOLYSILICON.6Japanese Office Action dated Jun. 1, 2010, issued in corresponding Japanese Patent Application No. 2001-205188 (With Partial English Translation).7Japanese Office Action dated Mar. 15, 2011, issued in corresponding Japanese Patent Application No. 2001-205188.Classifications U.S. Classification438/288, 438/199, 438/211, 438/154, 438/261, 257/E21.423, 438/396, 438/188International ClassificationH01L21/336, H01L21/8234, H01L27/105, H01L29/792, H01L27/088, H01L21/8247, H01L29/788, H01L27/115Cooperative ClassificationH01L29/7883, H01L27/11546, H01L27/105, H01L27/11521, H01L27/11558, H01L27/11526European ClassificationH01L27/105, H01L29/788B4, H01L27/115F4, H01L27/115F6, H01L27/115F6P2, H01L27/115F12Legal EventsDateCodeEventDescriptionApr 29, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services