Source: http://www.google.com/patents/US20060154531?ie=ISO-8859-1&dq=5,838,906
Timestamp: 2015-05-06 09:30:27
Document Index: 588003419

Matched Legal Cases: ['art 121', 'art 122', 'art 123', 'art 121', 'art 122', 'art 123', 'art 122', 'art 121', 'art 122', 'art 123', 'art 121', 'art 161', 'art 113', 'art 113', 'art 113', 'art 113', 'art 113', 'arts 147', 'art 145', 'art 145', 'arts 147', 'art 113', 'art 161', 'art 161', 'art 161', 'arts 162', 'arts 162', 'arts 161', 'arts 162', 'arts 145', 'arts 147', 'arts 147', 'art 121', 'arts 162', 'art 113', 'arts 147', 'arts 145']

Patent US20060154531 - Crosstalk canceling pattern for high-speed communications and modular jack ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsDisclosed herein are a crosstalk canceling pattern for high-speed communications and a modular jack having the same, which includes a compensating capacitor on a transmission line to cancel crosstalk due to parasitic capacitance generated between neighboring insert pins, and includes a second compensating...http://www.google.com/patents/US20060154531?utm_source=gb-gplus-sharePatent US20060154531 - Crosstalk canceling pattern for high-speed communications and modular jack having the sameAdvanced Patent SearchPublication numberUS20060154531 A1Publication typeApplicationApplication numberUS 11/327,897Publication dateJul 13, 2006Filing dateJan 9, 2006Priority dateJan 11, 2005Also published asUS7175476Publication number11327897, 327897, US 2006/0154531 A1, US 2006/154531 A1, US 20060154531 A1, US 20060154531A1, US 2006154531 A1, US 2006154531A1, US-A1-20060154531, US-A1-2006154531, US2006/0154531A1, US2006/154531A1, US20060154531 A1, US20060154531A1, US2006154531 A1, US2006154531A1InventorsDae Kim, Jung Kim, Jung Lee, Su Jong KimOriginal AssigneeDaeun Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManReferenced by (26), Classifications (16), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetCrosstalk canceling pattern for high-speed communications and modular jack having the same
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIGS. 4 a and 4 b are an exploded perspective view and a perspective view, respectively, showing the preferred embodiment of a modular jack, according to the present invention, and FIGS. 5 a and 5 b are perspective views showing the preferred embodiment of an insert pin and an IDC terminal. As shown in the drawings, a modular jack 100 according to this invention includes a housing 110 into which a modular plug 2 is inserted, and a connector which is detachably mounted to the rear surface of the housing 110. In this case, the connector includes a printed circuit board 130, a lower contact block 140, and an upper contact block 150. A plurality of insert pins 120 and IDC terminals 160 pass through the upper surface of the printed circuit board 130. The lower contact block 140 is coupled to the printed circuit board 130, and is detachably mounted to the rear portion of the housing 110. The upper contact block 150 is coupled to the upper portion of the lower contact block 140. In this case, the printed circuit board 130 is electrically connected to the insert pins 120 and the IDC terminals 160. The insert pins 120 are electrically connected to a transmission line of the printed circuit board 130 through contact holes 134 formed in the printed circuit board 130. In order to compensate for parasitic capacitance generated between neighboring insert pins 120, a compensating capacitor 138 generating inverse-phase compensating capacitance is provided on the printed circuit board 130. Referring to FIGS. 4 a and 5 a, two-staged insert pins 120 are inserted into the contact holes 134 of the printed circuit board 130. In this case, each stage comprises 4 insert pins 120. Such an arrangement depends on the positions of the contact holes 134, and minimizes parasitic capacitance and parasitic inductance, which are generated when a high-frequency signal is applied. Each of the insert pins 120 includes an insert part 121, a stop part 122, and a bent part 123. The length of the insert part 121 is set to pass through the printed circuit board. The stop part 122 having the shape of a rectangular plate is stopped by the upper surface of the printed circuit board. The bent part 123 extends from the upper end of the stop part 122. Further, the insert part 121 of each insert pin 120 vertically passes through an associated contact hole 134 of the printed circuit board, and is connected to transmission lines 137 a and 137 b such that a distance therebetween is shortest. The stop part 122 is in surface contact with the upper surface of the printed circuit board 130. The bent part 123 is inclined to be in surface contact with a terminal of the modular plug, and is bent towards the rear portion of the housing 110 at a predetermined angle. Thereby, since the insert pins 120 are connected to the terminal of the modular plug 2 which is inserted into a plug insert hole 115 of the housing 110, and are connected to the printed circuit board 130 such that a distance between the insert pins 120 and a patterned layer of the printed circuit board 130 is shortest, parasitic inductance generated at a position where the modular plug 2 is connected to the insert pins 120 is minimized, thus canceling and minimizing near-end crosstalk. According to this invention, neighboring insert pins 120 are spaced apart from each other by a predetermined distance in front and rear directions. Thus, as shown in FIG. 6, even though the insert pins 120 are pressed rearwards by the terminal of the modular plug 2, the neighboring insert pins 120 have different inclinations, so that they are not arranged in parallel to each other, but instead are staggered. Thereby, parasitic inductance A generated between the neighboring insert pins 120 can be minimized. Further, the insert pins 120 according to this invention are vertically installed on the upper surface of the printed circuit board 130, so that the length of each insert pin 120 is minimized, thus minimizing parasitic inductance B generated in the insert pins 120. FIG. 6 is a view illustrating the connector, according to this invention, in a sectional view and an equivalent circuit diagram. As shown in the drawing, the connector is constructed so that the insert pins 120, each having a short length and a simple shape, are installed on one side of the printed circuit board 130. The insert pins 120 are inserted into the contact holes 134 of the printed circuit board 130 to be connected to a transmission line 137. Further, the compensating capacitor 138 is provided at a position around the insert pins 120 mounted on the printed circuit board 130, and generates inverse-phase compensating capacitance C so as to compensate for parasitic capacitance A generated between the neighboring insert pins 120. As such, the compensating capacitor 138 is installed near the insert pins 120, thus minimizing the magnitude of the first parasitic inductance B generated in the transmission line 137 which is provided between the insert pins 120 and the compensating capacitor 138. Further, a second compensating capacitor 139 is additionally installed on the transmission line 137′ between the compensating capacitor 138 and the IDC terminals 160, more preferably, the transmission line 137′ near the IDC terminals 160, so as to correct phase mismatch caused by the parasitic capacitance, the compensating capacitance, and the parasitic inductance, which are generated in the front end of the transmission line 137′. That is, referring to FIG. 7, a Smith chart representing the progress direction of a real number part and an imaginary number part of crosstalk, according to crosstalk compensation, when a high-frequency signal is applied in the state where the compensating capacitor 138 is not installed, a graph is formed in the lower region of the Smith chart (before compensation). As such, if the imaginary number part is a negative number, it means that a capacitance component exists. Next, when the compensating capacitor 138 is installed and the parasitic capacitor is eliminated, the graph moves upwards in the Smith chart and the real number part is decreased (after compensation). This means that parasitic capacitance is offset by the compensating capacitor 138 and direct-current resistance is reduced. However, the modular jack cannot satisfy performance requirements for Category 6 simply by installing the compensating capacitor 138, because impedance is not matched due to parasitic inductance generated in a high-frequency area, as described above. Thus, when the second compensating capacitor 139 is installed near the IDC terminals 160, like the present invention, the graph in the Smith chart is moved to a region which satisfies the performance required in the category 6. As described above, the present invention is characterized in that the second compensating capacitor 139 is further installed behind the first compensating capacitor 138 so as to correct phase mismatch caused by parasitic capacitance and parasitic inductance generated when a high-frequency signal is applied to the modular jack 100. In this case, the second compensating capacitor 139 is installed as near the IDC terminals 160 as possible, thus compensating for parasitic inductance D generated in the transmission line 137′ between the first compensating capacitor 138 and the second compensating capacitor 139. As shown in the equivalent circuit diagram of FIG. 6, a crosstalk canceling pattern for high-speed communications, according to the present invention, is formed such that the first parasitic capacitance A, generated in the insert pins 120, and the first parasitic inductance B, generated in the transmission line 137 between the insert pins 120 and the first compensating capacitor 138, are symmetrical to the second parasitic inductance D, generated in the transmission line 137′ between the first compensating capacitor 138 and the second compensating capacitor 139, and second compensating capacitance E, generated in the second compensating capacitor 139 installed near the IDC terminals 160, with respect to the compensating capacitance C generated in the first compensating capacitor 138. In order to form such a symmetrical structure, it is necessary to minimize the first parasitic capacitance A generated in the insert pins 120 and the first parasitic inductance B generated in the transmission line 137 between the insert pins 120 and the first compensating capacitor 138. Thus, as described above, the insert pins 120 must have a simple structure, and neighboring insert pins 120 must not be arranged to be parallel to each other. Further, in order to minimize the parasitic inductance B generated in the insert pins 120 and the transmission line 137 between the insert pins 120 and the first compensating capacitor 138, the first compensating capacitor 138 must be formed as near the insert pins 120 as possible. Further, the second compensating capacitor 139 must be installed as near the IDC terminals 160 as possible, and the second parasitic inductance D generated in the transmission line 137′ between the first compensating capacitor 138 and the second compensating capacitor 139 must be adjusted to be identical to the first parasitic inductance B generated in front of the first compensating capacitor 138. Further, the interference between the capacitors and the transmission lines, formed on the printed circuit board 130, must be prevented. FIG. 8 is an exploded perspective view showing the preferred embodiment of the printed circuit board, according to the present invention. As shown in the drawing, the printed circuit board 130 according to this invention has a multi-layered structure. For example, the printed circuit board 130 has three substrates and four patterned layers. Two rows of insert pins 120, arranged in front and rear directions, are inserted into the pin contact holes 134, which are formed in the front portion of the upper surface of the printed circuit board 130 in such a way as to be spaced apart from each other in a zigzag manner. Further, two rows of IDC terminals 160, arranged to the left and right sides, are inserted into terminal contact holes 135, which are formed in the rear portion of the upper surface of the printed circuit board 130. In this case, the insert part 121 of each insert pin 120 and a contact part 161 of each IDC terminal 160 are tightly fitted into an associated pin contact hole 134 and an associated terminal contact hole 135, respectively, without a soldering process. In a detailed description of this invention, the transmission lines 137 a and 137 b, extending from the insert pins 120 to the IDC terminals 160, are provided on the upper surface of an upper substrate 136 a and the lower surface of a lower substrate 136 c. The first compensating capacitor 138, for compensating the first parasitic capacitance generated in the insert pins 120, and the second compensating capacitor 139, for correcting phase mismatch due to the compensating capacitance and the parasitic inductance, are provided on the upper and lower surfaces of a middle substrate 136 b. Further, the upper substrate 136 a and the lower substrate 136 c are compressed to be secured to the upper and lower surfaces of the middle substrate 136 b, respectively. Preferably, the printed circuit board 130 according to the present invention is made of FR4 (glass epoxy) having a dielectric constant of 3.4 or higher so as to prevent capacitive coupling in a high-frequency area. Further, the middle substrate 136 b has ample thickness of 1.6 mm or higher, thus preventing capacitive coupling between the capacitors provided on the upper and lower surfaces of the middle substrate 136 b. Meanwhile, each of the upper and lower substrates 136 a and 136 c has a thickness of about 0.2 mm. Further, each of the IDC terminals 160 has on an end thereof a cutter 163 with two blades so as to strip the insulating sheath from the UTP cable wire. Each IDC terminal 160 is electrically connected to the wire, and serves to maintain firm coupling so as to prevent the printed circuit board 130 from being removed from the lower contact block 140. FIGS. 9 a to 9 d and FIGS. 10 a to 10 d show the preferred embodiment of a crosstalk canceling pattern formed on the printed circuit board, according to the present invention. As shown in the drawings, FIGS. 9 a and 10 a show transmission lines formed on the upper surface of the upper substrate 136 a, and FIGS. 9 b and 10 b show transmission lines formed on the lower surface of the lower substrate 136 c. Further, FIGS. 9 c and 10 c show first and second compensating patterns formed on the upper surface of the middle substrate 136 b, and FIGS. 9 d and 10 d show first and second compensating patterns formed on the lower surface of the middle substrate 136 b. As shown in the drawings, the first compensating pattern is formed very near the pin contact holes into which the insert pins are inserted, and the second compensating pattern is formed near the terminal contact holes into which the IDC terminals are inserted. Turning now to FIGS. 4 a and 4 b, the detailed construction of the crosstalk canceling pattern for high-speed communications and the modular jack having the same will be described below. In a detailed description, the plug insert hole 115 is formed in the front surface of the housing 110 and has a size to allow the modular plug 2 to be tightly inserted thereinto. A locking protrusion 111 and an elastic hook 112 are provided on the upper and lower surfaces of the housing 110, and have sizes which allow the housing 110 to be detachably mounted to a patch panel or an outlet plate. Further, an insert pin locking plate 118 is provided on the lower portion of the plug insert hole 115 so that the insert pins 120 inserted from the rear portion are locked to the insert pin locking plate 118. A coupling guide part 113 is integrally provided on the rear portion of the housing 110 and has a size to allow the lower surface of the lower contact block 140 to be accommodated therein. In this case, the coupling guide part 113 of the housing 110 comprises a �U�-shaped plate which is open at a top thereof. Locking holes 114 and slide grooves 117 are formed on the rear portions of both sidewalls of the coupling guide part 113. While the lower contact block 140 slides along the slide grooves 117, locking hooks 142 of the lower contact block 140 are locked to the locking holes 113. Further, the insert pin locking plate 118 of the housing 110 is provided to be perpendicular to the front surface of the housing 110, and has a height which is suitable for accommodating the height of the stop part of each insert pin 120. Pin guide groves 118 a having different depths are provided on the rear portion of the insert pin locking plate 118 to be staggered, so that the insert pins 120 are locked to the corresponding pin guide grooves 118 a. The lower contact block 140 defines the body of the modular jack 100. The printed circuit board 130 is mounted to the lower surface of the lower contact block 140, and the upper contact block 150 is mounted on the upper portion of the lower contact block 140. In such a state, the assembly is mounted to the coupling guide part 113 of the housing 110. FIG. 11 is a view illustrating the coupling of the lower contact block with the IDC terminals, according to the present invention, in a perspective view and a partial sectional view. Referring to FIGS. 4 a and 4 b and FIG. 11, a plurality of through holes 141, having a number corresponding to that of the IDC terminals 160 secured to the printed circuit board 130, is formed in the lower contact block 140. The through holes 141 are formed at predetermined angles in such a way as to face each other. In order to prevent impurities from entering the IDC terminals 160 when they are coupled to the lower contact block 140, a front rib wall 143 a and rear rib walls 143 b are provided on the lower contact block 140 to be higher than the IDC terminals 160 passing through the through holes 141 and lower than the front surface of the housing 110, and have sizes to be accommodated in the coupling guide part 113 of the housing 110. Further, the locking hooks 142 are provided on the both sidewalls of the lower contact block 140 to be slidably locked to the locking holes 114 of the housing 110. Protruding guide parts 147 are vertically provided on the inner surface of the front rib wall 143 a to allow the upper contact block 150 to be easily coupled to the lower contact block 140. A lower cable insert hole 146 is formed in the rear rib walls 143 b and has a size allowing the UTP cable to be inserted therein. Upper block guides 144 are vertically provided on the inner surfaces of the rear rib walls 143 b. Further, a block locking part 145 is integrally provided to a side of each upper block guide 144, so that a detachable hook 151 of the upper contact block 150 is locked to the block locking part 145. Thus, the printed circuit board 130 is coupled to the lower portion of the lower contact block 140 while the IDC terminals 160 of the printed circuit board 130 pass through the through holes 141. The upper contact block 150 is coupled to the upper portion of the lower contact block 140 along the protruding guide parts 147 and the upper block guides 144. The assembly is mounted along the coupling guide part 113 of the housing 110. First, the insert pins 120 are inserted into the housing 110, and the locking hooks 142 provided on both sidewalls slide along the slide grooves 117 of the housing 110 to be locked to the locking holes 114. In this way, the assembly is coupled to the housing 110. Referring to FIG. 5 b, each of the IDC terminals 160 passing through the through holes 141 of the lower contact block 140 includes a contact part 161, a terminal body 162, and a cutter 163. The contact part 161 has a length which is suitable for passing through an associated terminal contact hole 135 of the printed circuit board 130. The terminal body 162 extends from the contact part 161, and has a size to be held in an associated through hole 141 of the lower contact block 140, with locking parts 162 a protruding from both sides of the terminal body 162. The cutter 163 comprising two blades is provided on the upper end of the terminal body 162, and functions to strip the UTP cable. Therefore, referring to FIG. 11, the size of an outlet of each through hole 141 of the lower contact block 140 is set so that the cutter 163 of each IDC terminal passes through the outlet and the locking parts 162 a of the terminal body are stopped by the outlet. The contact parts 161 of the IDC terminals 160 are inserted into the terminal contact holes 135 of the printed circuit board 130, and the locking parts 162 a of each terminal body are stopped by the corresponding through hole 141, so that the IDC terminals 160 are secured to the printed circuit board 130. Further, the upper contact block 150 electrically connects the UTP cable wires to the printed circuit board 130 through the IDC terminals 160. Referring to FIGS. 4 a and 4 b and FIG. 12, which is a plan view showing the lower portion of the upper contact block according to the present invention, the upper contact block 150 includes an upper plate 155 and side plates 157. The upper plate 155 has a size suitable for covering the lower contact block 140. Terminal insert holes 158 are formed in the lower portions of the side plates 157 so that the IDC terminals 160 are inserted into the terminal insert holes 158. The upper contact block 150 divides the UTP cable wires W, and connects the UTP cable wires W to the IDC terminals 160. In this case, the upper surface of the upper plate 155 of the upper contact block 150 comprises a concave bent surface to allow a user to easily catch and compress the upper contact block 150. A protective cover 153 protrudes from the front end of the upper plate 155 so as to prevent impurities from entering the assembly of the upper contact block 150 with the lower contact block 140. Further, the detachable hook 151 is provided on the rear portion of the upper contact block 150 to be locked to the block locking parts 145 of the lower contact block 140. An upper cable insert hole 156 is formed in the rear surface of the upper contact block 150 so that the UTP cable is inserted into the upper cable insert hole 156. Wire insert holes 152 are formed in the lower portions of the side plates 157 of the upper contact block 150 so that the cable wires W introduced through the cable insert hole 156 are diagonally inserted into both sides of the upper contact block 150. The wire insert holes 152 are at right angles to the terminal insert holes 158 into which the IDC terminals 131 of the printed circuit board 130 are inserted, and have numbers and positions corresponding those of the terminal insert holes 158. Further, a protrusion 154 having a predetermined size is provided on the lower surface of the upper plate 155 to divide the introduced UTP cable wires W and guide the wires W into the wire insert holes 152 which are formed in both sides of the upper plate 155. Preferably, an insert hole having the same size as the upper cable insert hole 156 is formed in the front surface of the upper contact block 150. Guide grooves 154 are provided on the front surface of the upper contact block 150 to correspond to the protruding guide parts 147 of the lower contact block 140, and have sizes to allow the protruding guide parts 147 to slidably engage with the guide grooves. Thus, the UTP cable wires W are introduced through the upper cable insert hole 156 of the upper contact block 150. The introduced cable wires W are divided by the protrusion 154 to be positioned in the wire insert holes 158. Further, the upper contact block 150 is mounted to the upper portion of the lower contact block 140, which has been coupled to the printed circuit board 130. At this time, the UTP cable passes through the lower cable insert hole 146 of the lower contact block 140, which is formed at a position corresponding to the upper cable insert hole 156 of the upper contact block. When the upper plate 155 of the upper contact block 150 is compressed down, insulating sheathes are stripped from the UTP cable wires by the cutters 163 of the IDC terminals 160 inserted into the terminal insert holes 158, so that the UTP cable wires are electrically connected to each other. The assembly and operation of the crosstalk canceling pattern for high-speed communications and the modular jack having the same will be described below with reference to FIGS. 4 a, 4 b, and 6. The insert part 121 of each insert pin 120 is vertically electrically connected to the printed circuit board 130. When the printed circuit board 130 is coupled to the lower portion of the lower contact block 140, the IDC terminals 160 pass through the through holes 141 of the lower contact block 140, and the locking parts 162 a of the IDC terminals 160 are stopped by the through holes 141 having narrow outlets. Further, the locking hooks 142 of the lower contact block 140 slide along the slide grooves 117 of the coupling guide part 113 provided on the rear portion of the housing 110 to be locked to the locking holes 114. The guide grooves 154 of the upper contact block 150 engage with the protruding guide parts 147 of the lower contact block 140, and the detachable hook 151 of the upper contact block 150 is locked to the block locking parts 145 along the upper block guides 144, so that the upper contact block 150 is coupled to the upper portion of the lower contact block 140. At this time, the UTP cable wires connected to the wire insert holes 152 are stripped by the cutters 163 of the IDC terminals of the printed circuit board 130 to be electrically connected to each other. Further, the insert pins 120 have a structure capable of minimizing parasitic capacitance and parasitic inductance which are generated when a high-frequency signal is applied. According to the present invention, neighboring insert pins 120 are spaced apart from each other in front and rear directions by a predetermined distance, thus minimizing the first parasitic capacitance A generated between the insert pins 120. Further, according to this invention, the insert pins 120 are vertically installed on the upper surface of the printed circuit board 130, thus minimizing the length of the insert pins 120, therefore minimizing the first parasitic inductance B generated in the insert pins 120. Further, the first compensating capacitor 138 is installed near the insert pins 120, thus minimizing the magnitude of the first parasitic inductance B generated in the transmission line 137 between the insert pins 120 and the compensating capacitor 138. As such, the first capacitance and the first parasitic inductance B are minimized, thus allowing the crosstalk canceling pattern to have a symmetrical structure. Therefore, after the connector is inserted to be coupled to the rear portion of the modular jack 100, the wires W of the UTP cable are connected to the IDC terminals 160 through the lower contact block 140 and the upper contact block 150. Subsequently, when the modular plug 2 is inserted into the plug insert hole 115 of the modular jack 100, the terminal of the modular plug 2 is electrically connected to the insert pins 120 to be connected to the IDC terminals 160. In such a state, when a predetermined high-frequency signal is applied, the first parasitic capacitance A is generated between the insert pins 120 contacting the terminal of the modular plug 2, and the first parasitic inductance B is generated in the insert pins 120 and the transmission line 137 between the insert pins 120 and the first compensating capacitor 138. At this time, the first parasitic capacitance A and the first parasitic inductance B are minimized, as described above. Next, the inverse-phase compensating capacitance C is generated in the first compensating capacitor 138 to offset the first parasitic capacitance A. Further, the second parasitic inductance D caused by high frequency is generated in the transmission line 137′ between the first compensating capacitor 138 and the second capacitor 139. In this case, the length of the second parasitic inductance D and the first parasitic inductance B is adjusted so that they have a symmetrical structure. Further, the second compensating capacitance E is generated in the second compensating capacitor 139 to correct phase mismatch caused by the first parasitic capacitance A, the second parasitic inductance B, the compensating capacitance C, and the second parasitic inductance D, which are generated in front of the second compensating capacitor 139. Further, the insert pins 120 and the IDC terminals 160 are secured to the printed circuit board 130 without a soldering process, thus increasing contact efficiency. As such, the crosstalk canceling pattern according to this invention provides a canceling pattern having a symmetrical structure to cancel the parasitic capacitance as well as the parasitic inductance generated in the high-frequency area, thus satisfying the performance requirements for Category 6 that is required in high-speed communications. Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. As described above, the present invention provides a crosstalk canceling pattern for high-speed communications and a modular jack having the same, which satisfies performance requirements for Category 6 capable of transmitting up to 250 MHz per pair in UTP 4 pair cable. Further, the present invention provides a crosstalk canceling pattern for high-speed communications and a modular jack having the same, constructed so that first parasitic capacitance and first parasitic inductance generated in front of a first compensating capacitor are symmetrical to second parasitic inductance and second compensating capacitance generated in back of the first compensating capacitor, thus correcting phase mismatch, therefore permitting high-speed communications. Further, wires are connected by hand without using an additional work tool, and the modular jack has a small size, so that the manufacturing process is simple and mass production is convenient. Further, when insert pins and IDC terminals are mounted on a printed circuit board, a soldering process is not used, thus preventing poor contact and enhancing a high quality when being used. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7422467Apr 25, 2007Sep 9, 2008Belden Cdt (Canada), Inc.Balanced interconnectorUS7503810Sep 12, 2007Mar 17, 2009Commscope, Inc. Of North CarolinaBoard edge termination back-end connection assemblies and communications jacks including such assembliesUS7537484Oct 11, 2007May 26, 2009Adc GmbhConnecting hardware with multi-stage inductive and capacitive crosstalk compensationUS7568938Aug 7, 2008Aug 4, 2009Belden Cdt (Canada) Inc.Balanced interconnectorUS7614901Jul 9, 2009Nov 10, 2009Belden Cdt (Canada) Inc.Balanced interconnectorUS7677930 *Jul 7, 2008Mar 16, 2010Commscope, Inc. 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KgPlug system housing for multi-core cablesWO2010120802A1 *Apr 13, 2010Oct 21, 2010Raritan Americas, Inc.Integrated access cable* Cited by examinerClassifications U.S. Classification439/676International ClassificationH01R13/66, H01R24/00Cooperative ClassificationY10S439/941, H01R13/6473, H01R24/64, H05K2201/09236, H01R13/6658, H05K1/0228, H05K2201/10189, H05K1/162, H01R13/6466European ClassificationH05K1/02C2C, H01R23/00B, H01R23/02B, H01R13/66D2Legal EventsDateCodeEventDescriptionJul 18, 2014FPAYFee paymentYear of fee payment: 8Aug 5, 2010FPAYFee paymentYear of fee payment: 4Jan 9, 2006ASAssignmentOwner name: DAE EUN ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, DAE SUNG;KIM, JUNG GON;LEE, JUNG SUK;AND OTHERS;REEL/FRAME:017438/0685Effective date: 20051230RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services