Source: http://www.google.com/patents/US5887162?dq=6,360,693
Timestamp: 2013-12-19 13:15:47
Document Index: 45777348

Matched Legal Cases: ['arts 10', 'art 25', 'arts 10', 'art 25', 'art 20', 'art 15', 'art 10']

Patent US5887162 - Memory device having circuitry for initializing and reprogramming a control ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates an initialization signal in response to the first command and generates...http://www.google.com/patents/US5887162?utm_source=gb-gplus-sharePatent US5887162 - Memory device having circuitry for initializing and reprogramming a control operation featureAdvanced Patent SearchPublication numberUS5887162 APublication typeGrantApplication numberUS 08/783,390Publication dateMar 23, 1999Filing dateJan 13, 1997Priority dateApr 15, 1994Fee statusPaidAlso published asUS5717639, US5896551, US5905909Publication number08783390, 783390, US 5887162 A, US 5887162A, US-A-5887162, US5887162 A, US5887162AInventorsScott Schaefer, Brett WilliamsOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (5), Non-Patent Citations (6), Referenced by (6), Classifications (20), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMemory device having circuitry for initializing and reprogramming a control operation featureUS 5887162 AAbstract A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates an initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a control operation feature and responds to the reprogramming signal to control a reprogramming of the control operation feature.
What is claimed is: 1. A memory device for storing data, comprising:a) a first control circuit having a plurality of input nodes, said first control circuit generating an initialization signal in response to a first command on said plurality of input nodes, said first command comprised of a first plurality of input signals; b) a second control circuit having a plurality of input nodes, said second control circuit generating a reprogramming signal in response to a second command on said plurality of said input nodes of said second control circuit, said second command comprised of a second plurality of input signals; and c) an initialization and reprogramming circuit for receiving said initialization signal and said reprogramming signal, said initialization and reprogramming circuit programming a control operation feature of the memory device, said initialization signal controlling an initial programming of the initialization and reprogramming circuit to have a first control operating option of said operation feature, and said reprogramming signal controlling the reprogramming of the initialization and reprogramming circuit to have a second control operating option of said operation feature, said memory device operating according to said first and said second control operating options. 2. The memory device as specified in claim 1, further comprising:a) a memory bank for storing data; and b) an internal control state machine for monitoring control signals of said memory device and for generating an active state signal in response to a first combination of said control signals and generating an idle state signal in response to a second combination of said control signals, said memory bank accessed in response to said first combination of said control signals, said idle state signal being one of said first plurality of input signals. 3. The memory device as specified in claim 2, wherein said idle state signal is one of said second plurality of input signals.
4. The memory device as specified in claim 2, wherein said active state signal is one of said second plurality of input signals.
5. The memory device as specified in claim 1, wherein said first and said second commands are different.
6. The memory device as specified in claim 1, wherein said initialization and reprogramming circuit comprises an op-code input node for accepting an operation code signal, wherein said first control operating option is determined by a value of said operation code signal.
7. The memory device as specified in claim 6, wherein said initialization and reprogramming circuit generates an internal programming signal for selecting said first operating option during said initial programming in response to said operation code signal, and wherein said internal programming signal toggles in response to said reprogramming signal thereby selecting said second operating option during said reprogramming.
8. The memory device as specified in claim 6, wherein said initialization and reprogramming circuit comprises a reprogramming input node for accepting a reprogramming code, wherein said second control operating options determined by a value of said reprogramming input node.
9. The memory device as specified in claim 1, further comprising a third control circuit having a plurality of input nodes for accepting a third command, said third command comprised of a third plurality of input signals, said third control circuit generating a return signal in response to said third command, said return signal controlling a further reprogramming of said initialization and reprogramming circuit following said reprogramming of said initialization circuit, said memory device programmed to operate according to said first operating option after said further reprogramming.
10. The memory device as specified in claim 1, wherein said first command is an external set mode register command.
11. The memory device as specified in claim 1, wherein said second command is a column address strobe registration command.
12. The memory device as specified in claim 1, wherein said second command is an activate row command.
13. A memory device, comprising:a) a memory bank comprised of memory storage cells for storing electrical data; b) an internal control state machine for monitoring command signals and generating an active state signal in response to a bank activate command, a memory function capable of being performed in said memory bank when said memory bank is accessed in response to said bank activate command; c) a programming means for programing the memory device to have one of a plurality of control operating options for a control operation feature; d) an initializing means in electrical communication with said programing means, said initializing means providing an initial input signal to said programming means, said programming means programming said memory device to a first control operating option in response to said initial input signal; and e) a reprogramming means for providing a reprogramming input signal to said programming means in response to said bank activate signal, said program means programming said memory device to a second control operating option in response to said reprogramming input signal. 14. The memory device as specified in claim 13, wherein said internal control state machine generates an idle state signal to said initializing means during an absence of the bank activate command, said initializing means responding to said idle state signal to provide said initial input signal.
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional of application Ser. No. 08/228,051, filed Apr. 15, 1994.
BACKGROUND OF THE INVENTION The following background information describes the MT48LC2M8S1, a 16 Meg synchronous dynamic random access memory (SDRAM) organized in a configuration. The MT48LC2M8S1 is structured internally as a dual 1 Meg Meg each memory array has 1 Meg (1,048,576) memory cells arranged in a matrix of electrical intersections of rows and columns. SDRAMs offer substantial advances in dynamic memory operating performance.
Each byte is uniquely accessed by registering the 11 row-address bits (A0-A10) via the Active command, followed by registering the 9 column-address bits (A0-A8) via a READ or WRITE command. Internal bank selection is controlled by a bank activate (DA) signal during both row address strobe (RAS) and column address strobe (CAS) registration which allows the bank to be accessed in order that a read/write operation may be performed to the bank. This bank selection is also called activation of the bank. The bank selected is referred to as an active or activated bank.
SDRAMs must be powered-up and initialized in a predefined manner. Operational procedures other than what is specified could produce unwanted and unrepeatable start-up modes. Once power, V.sub.CC and V.sub.CCQ, is simultaneously applied to core logic and DQ buffer power pins, respectively, the SDRAM requires a 100 micro second delay prior to any signals being toggled. It is recommended that all the inputs be held HIGH during this phase of powering-up.
In FIG. 2 the control operating options of each programmable control operation feature are displayed in relation to the op-code 9 used to generate the desired control operating option. The op-code 9 is represented by bits M.sub.0 -M.sub.11. The programmable control operation features are burst length, burst type, and read latency and are shown in charts 10, 15, and 20, respectively. Other programmable control operation features are shown in chart 25. The programmable control operation features shown in charts 10, 15, and 20 are joint electron device engineering counsels (JEDEC) standards. The other programmable control operation features shown in chart 25 are vendor and application specific, except for "test mode entry" which is an agreed upon JEDEC standard.
The control operating option selected for the read latency feature shown in chart 20 is determined by the op-code M4 through M6; the sequential control operating option or the interleave operating option of the burst type feature, shown in chart 15, is determined by bit M3; and the operating option of the burst length feature, shown in chart 10 is determined by bits M.sub.0 through M.sub.2.
The two types of burst type options available for selection are sequential and interleave. Both sequential and. interleave sequencing support bursts of 2, 4, and 8 cycles. Additionally, sequential sequencing supports the full-page length option.
The JEDEC-defined standard requires the type of sequencing to be programed to the mode register. Each time the type of sequencing needs to be changed, the program register must be reprogrammed. Several cycles of overhead are required each time the program register must be reprogrammed. Thus, changing the type of sequencing during operation results in a significant time penalty. Consequently there exists a need to minimize the time required to reprogram the mode register, thereby increasing the processing speed.
SUMMARY OF THE INVENTION The invention is a memory device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates an initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a control operation feature and responds to the reprogramming signal to control a reprogramming of the control operation feature.
The circuit of the invention minimizes the time required to reprogram the mode register since the memory device does not have to return to an original state before reprogramming occurs. A separate command controls reprogramming rather than the command which controls initial programming. Thus the circuit of the invention increases the processing speed of the memory device.
FIG. 5 is a simplified block diagram of one SDRAM 30 of the invention. The SDRAM 30 is a 2 Meg bank 31 and 33 has eight memory arrays. Each memory array is comprised of 1,048,576 memory storage cells for storing electrical data. An initialization and reprogramming circuit 35 receives at least two control signals from a master control circuit 37. The master control circuit 37 receives memory commands and generates internal control signals to control the operation of the memory device in response to the memory commands. The control signals generated by the master control circuit 37 and received by the initialization and reprogramming circuit 35 control the initializing and reprogramming of a control operation feature to have a desired control operating option, also known as a control operating mode. The operating mode initially selected is dependent on an operational code (op-code), or potential, on at least one of the address input pins A0-A10 and BA.
In the circuits of FIGS. 6 and 7 the output of D3 is an input to an exclusive OR logic gate 63, while in the circuit of FIG. 8, the output of D3 is directly connected to the input node 64 of the burst type programing circuit 61. Referring again to FIGS. 6 and 7, the output of the exclusive OR logic gate 63 is connected to the input node 64 of the burst type programming circuit 61. During initialization the exclusive OR logic gate 63 is enabled, and the output potential of the exclusive OR logic gate 63 is the same as the output potential of D3.
FIG. 9 is a is more detailed schematic of the intermediate logic circuit 80 of FIG. 6. The system clock and the internal toggle command are inputs to an AND logic gate 85. The output of AND logic gate 85 clocks a D-flip-flop 87, which was initially reset to have a low potential on output node 90 during initialization in response to the low set mode register command. Output node 90 is connected to exclusive OR input node 66 of FIG. 6. The output potential at output node 90 is inverted by inverter 95 such that when the D-flip-flop is clocked by the output of the AND logic gate 85 the output potential at output node 90 changes state, and the value of the potential on the output node 67 of the exclusive OR logic gate 63 also changes state. The value of the potential of the output node 67 remains unchanged until the next external toggle command initiates reprogramming. Thus the reprogramming is persistent.
D-flip-flop 115 is used to indicate that a toggle command has occurred, since the toggle command can occur while a burst read or write operation the outprocess. D-flip-flop 120 uses the output of D-flip-flop 115 (toggle command occurred) as the input which determines whether or not to toggle the burst type for the ensuing read/write operation. A toggle command affects only the next read/write operation which is defined by the next occurring CAS* registration command. This allows the toggle command to set the burst sequence once for the full burst sequence. The D flip-flop 115 allows the circuit to remember that a toggle command has occurred since the last CAS* registration command. The D-flip-flop 115 sets up the burst sequence for the next read/write operation while the current operation is in process.
FIG. 13 is a simplified block diagram of a further SDRAM 200 of the invention. SDRAM 200 is a 2 meg memory bank has eight memory arrays. Each memory array is comprised of 2,097,152 memory storage cells for storing electrical data. An initialization and reprogramming circuit 220 receives at least two internal control signals generated in a master control circuit 230. The master control circuit 230 receives memory commands and generates internal control signals to control the operation of the SDRAM in response to the memory commands. The two internal control signals generated by the master control circuit 230 and received by the initialization and reprogramming circuit 220 control the initializing and reprogramming of an operation feature to have a desired operating option. The circuit and method of the present embodiment pertains particularly to the initialization and reprogramming of the burst type operation feature. The operating option initially selected is dependent on an op-code, or potential, on at least one of the address input pins A0-A10.
FIG. 14 is a is more detailed circuit of a portion of the SDRAM 200 of FIG. 13. The circuitry shown in the master control circuit 230 is a portion of the total circuitry in the master control circuit 230 and is pertinent to the circuitry of the invention. The initialization and reprogramming circuit 220 comprises 12 D-flip-flops, D0-D11, which form a mode register 250. When the internal control state machine 260 generates an idle state signal at the control state machine output node 265 and when the CKE is high and CS*, WE*, CAS* and RAS* are low the master control circuit 230 generates the set mode register command at output node 270 of NAND logic gate 275. The internal control state machine 260 is similar to the internal control state machine 53 described with respect to the first three embodiments. The set mode register command is an enable signal for the mode register 250 and enables all of the D-flip-flops, D0-D11. When the D-flip-flops are enabled, the potential on each address input pin A0-A10 is latched to a corresponding D-flip-flop output node in response to the system clock transitioning high.
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