Source: http://www.google.com/patents/US5353253?dq=6437692
Timestamp: 2015-05-06 12:13:50
Document Index: 381646051

Matched Legal Cases: ['arts 21', 'arts 21', 'arts 21', 'arts 21', 'art 21', 'arts 21', 'art 21', 'arts 21', 'art 40']

Patent US5353253 - Semiconductor memory device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA smaller, high-speed, semiconductor memory device having redundancy is disclosed which attains an improved mass productivity. Where a main memory (20) includes a defective memory cell, a defective address designating circuit (21) stores the address of the defective memory cell. Defective address detecting...http://www.google.com/patents/US5353253?utm_source=gb-gplus-sharePatent US5353253 - Semiconductor memory deviceAdvanced Patent SearchPublication numberUS5353253 APublication typeGrantApplication numberUS 08/126,636Publication dateOct 4, 1994Filing dateSep 27, 1993Priority dateOct 14, 1992Fee statusLapsedAlso published asDE4334946A1, DE4334946C2Publication number08126636, 126636, US 5353253 A, US 5353253A, US-A-5353253, US5353253 A, US5353253AInventorsMichio NakajimaOriginal AssigneeMitsubishi Denki Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (7), Referenced by (31), Classifications (7), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor memory device
US 5353253 AAbstract
A smaller, high-speed, semiconductor memory device having redundancy is disclosed which attains an improved mass productivity. Where a main memory (20) includes a defective memory cell, a defective address designating circuit (21) stores the address of the defective memory cell. Defective address detecting circuits (22a to 22r) detect whether an address signal received at an address signal input terminal (4) coincides with an address signal from the defective address designating circuit (21). If a signal indicative of the coincidence is given to a redundancy memory circuit (23) from the defective address detecting circuits (22a to 22r), data is written in or read from defective address remedy latch circuit groups (23a to 23r) of the redundancy memory circuit (23) which correspond to the defective address detecting circuits (22a to 22r). A data selector (24) selectively outputs data received from the defective address remedy latch circuit groups (23a to 23r) or data received from the main memory (20). Thus, the redundancy memory circuit (23), which requires less space, quickly replaces the defective memory cell of the main memory (20).
1. A semiconductor memory device comprising:a data input terminal for receiving data for storage; an address signal input terminal for receiving an address signal which designates an address at which said data is written and from which said data is read; a main memory circuit for receiving said data from said data input terminal and said address signal from said address signal input terminal and for thereafter writing said data at an address which is specified by said address signal or otherwise retrieving said data already stored therein; a defective address specifying circuit for outputting defective address specifying information which specifies an address which corresponds to a defective portion of said main memory circuit; a detection circuit for receiving said address signal and said defective address specifying information respectively from said address signal input terminal and said defective address specifying circuit, for detecting whether the address specified by said address signal coincides with the address specified by said defective address specifying information, and for outputting a detection signal indicative of a result of the detection; a redundancy memory circuit for receiving said detection signal and said data respectively from said detection circuit and said data input terminal and thereafter storing said data of the defective address in response to said detection signal which indicates the coincidence or otherwise outputting said data about the defective address already stored therein; and a data select circuit for receiving said data which is read from said main memory circuit, said data which is outputted from said redundancy memory circuit and said detection signal from said detection circuit and for selectively outputting said data received frown said main memory circuit or said data received from said redundancy memory circuit, in accordance with said detection signal. 2. The semiconductor memory device of claim 1, whereinsaid redundancy memory circuit is constructed to be capable of storing said data about a plurality of defective addresses and outputting all of said stored data about said defective addresses, and said data select circuit comprises: a first select circuit for receiving said data about said plurality of defective addresses at one time from said redundancy memory circuit and for selectively outputting one of said data about said plurality of defective addresses in accordance with said detection signal; and a second select circuit for receiving said data which is retrieved from said main memory circuit and said data which is outputted from said first select circuit and for selectively outputting said data received from said main memory circuit or said data received from said main memory circuit in accordance with said detection signal. 3. The semiconductor memory device of claim 1 which is formed on a semiconductor substrate, wherein said defective address specifying circuit comprises:a reference coordinate mark which is formed on said semiconductor substrate to indicate the location of said defective address specifying circuit on said semiconductor substrate; and a fuse element disposed in a predetermined direction with a predetermined distance away from said reference coordinate mark, said fuse element providing said information which specifies the defective portion when selectively conducted or either disconducted by external manipulation. 4. The semiconductor memory device of claim 1, wherein said data select circuit comprises:a plurality of AND circuits for each receiving at one terminal said data which is retrieved from said redundancy memory circuit or said data which is outputted from said main memory circuit and receiving at the other terminal said detection signal, and for generating a logical product of said data received at said one terminal and an noninverted or an inverted logic of said detection signal; and an OR circuit for receiving output signals of said plurality of said AND circuits and for outputting a logical sum of said output signals of said plurality of said AND circuits. 5. The semiconductor memory device of claim 1, wherein said redundancy memory circuit comprises latch circuits, each one of said latch circuits storing each bit of said data in accordance with said detection signal, said latch circuits being provided as many as the bit count of said data which is received at said data input terminal.
FIG. 9 is a block diagram of a conventional semiconductor memory device. In FIG. 9, indicated at numerical reference 1 is a data input terminal for receiving data which is to be stored Din, indicated at 2 is a write signal input terminal for receiving a write enable signal WE under the control of which data is written and read, and indicated at 3 is a data output terminal for outputting stored data Dout. Indicated at 4 is an address signal input terminal for receiving an address signal AD which designates the address of a memory location which is specified by a row and a column of the inputted data Din and the stored data to be outputted Dout. Indicated at 5 is a memory cell array housing arrays of memory cells for storing the data Din which has been stored at an address which is specified with a row and a column by the address signal AD and for outputting the stored data Dout. Indicated at 6 is a row decoder which is connected to the address signal input terminal 4 and which double signs a row address signal of a address signal AD received therein in order to designate the row of an address. At reference number 7 word lines are indicated which are connected to the row decoder 6 and the memory cells of the memory array 5 so as to transfer a signal which controls the memory cells. At reference number 8, a defective row address signal generation circuit is shown which includes a plurality of fuses. By blowing the fuses with a laser or the like, the defective row address signal generation circuit 8 generates a row address signal which tells which row includes a defective memory cell. Indicated at 9 is a defective row address signal detection circuit which is connected to the defective row address signal generation circuit 8 and the address signal input terminal 4. The defective row address signal detection circuit 9 judges whether a row address signal received therein coincides with the defective row address signal and designates a spare row if the two signals coincide with each other. Indicated at 10 is a spare word line connected to both spare row memory cells and the defective row address signal detection circuit 9 and which transmits a signal which controls the spare memory cells. At numerical reference 11 are indicated fuses which are provided in the word lines 7 and the spare word line 10. The fuses 11 are to be blown to prohibit transfer of the control signal from the row decoder 6 or the defective row address signal detection circuit 9 to the memory cells or the spare memory cells. Indicated at 12 is a column decoder which is connected to the address signal input terminal 4 and which double signs a column address signal of an address signal AD received therein in order to designate the column of an address. Indicated at 14 is a column selector connected to the column decoder 12. In response to a signal received from the column decoder 12, the column selector 14 selects a bit line 13 to attain data transfer between the data input terminal 1 and the selected bit line 13 or between the data output terminal 3 and the selected bit line 13. The bit lines 13 are connected to the memory cells of the memory cell array 5 to transmit the data Din or the data Dout to the memory cells. Indicated at 15 is a defective column address signal generation circuit which includes a plurality of fuses. By blowing the fuses with a laser or the like, the defective column address signal generation circuit 15 generates a column address signal which tells which column includes a defective memory cell. Indicated at 16 is a defective column address signal detection circuit which is connected to the defective column address signal generation circuit 15 and the address signal input terminal 4. The defective column address signal detection circuit 16 judges whether a column address signal received therein coincides with the defective column address signal and designates a spare column if the two signals coincide with each other. Indicated at 17 is a spare bit line which is connected to spare column memory cells and the column selector 14. The spare bit line 17 attains transfer of the data Din which is to be stored in the spare memory cells or the data Dout which is to be read from the spare memory cells. At numerical reference 18 fuses are indicated which are provided in the bit lines 13 and the spare bit line 17. The fuses 18 are to be blown to disconnect the column selector 14 from the memory cells or the spare memory cells so that the data Din or the data Dout would not be transferred. A semiconductor memory device is indicated at numerical reference 20a.
Having such a construction, the conventional semiconductor memory device needs a line-basis remedy method in which a row as a whole or a column as a whole has to be replaced to replace a single defective memory cell with a spare memory cell. A semiconductor memory device having a memory capacity of 256K bits can be cited as an example. Suppose that the semiconductor memory device is organized as a 8-bit, 4-column/bit, 16-block memory device, the total bit lines are 512 (8�4�16) and the total spare bit lines are 128 (8�16). Hence, the semiconductor memory device would not comprise redundancy unless the arrays of the memory cells increase in number from 512 to 640, in which case due to the expanded space for the increased memory cell arrays, the chip will become large.
A semiconductor memory device according to a first aspect of the invention comprises: a data input terminal for receiving data for storage; an address signal input terminal for receiving an address signal which designates an address at which the data is written and from which the data is read; a main memory circuit for receiving the data from the data input terminal and the address signal from the address signal input terminal and for thereafter writing the data at an address which is specified by the address signal or otherwise retrieving the data already stored therein; a defective address specifying circuit for outputting defective address specifying information which specifies an address which corresponds to a defective portion of the main memory circuit; a detection circuit for receiving the address signal and the defective address specifying information respectively from the address signal input terminal and the defective address specifying circuit, for detecting whether the address specified by the address signal coincides with the address specified by the defective address specifying information, and for outputting a detection signal indicative of a result of the detection; a redundancy memory circuit for receiving the detection signal and the data respectively from the detection circuit and the data input terminal and thereafter storing the data about the defective address in response to the detection signal which indicates the coincidence or otherwise outputting the data about the defective address already stored therein; and a data select circuit for receiving the data which is read from the main memory circuit, the data which is outputted from the redundancy memory circuit and the detection signal from the detection circuit and for selectively outputting the data received from the main memory circuit or the data received from the redundancy memory circuit, in accordance with the detection circuit.
FIG. 1 is a block diagram showing a structure of a semiconductor memory device according to a first preferred embodiment of the present invention;
A first preferred embodiment of the present invention will be described with FIGS. 1 to 7. FIG. 1 is a block diagram showing a structure of a semiconductor memory device having redundancy according to the first preferred embodiment of the present invention. In FIG. 1, indicated at numerical reference 20 is a main memory in which m bits of data Din received via a data input terminal 1 is stored at or outputted from an address which is designated by an n-bit address signal AD which is received via an address signal input terminal 4, in response to a write enable signal WE which is received via a write signal input terminal 2. Indicated at numerical reference 21 is a defective address designating circuit for designating the address of a defective memory cell of the main memory 20. Defective address generating parts are indicated at 21a to 21r each designating an address which corresponds to a defective memory cell. Indicated at numerical references 22a to 22r are defective address detecting circuits. The defective address detecting circuits 22a to 22r each receive the address signal AD from an address signal input terminal 4 and defective address designating information designating a defective address from an associated one of the defective address generating parts 21a to 21r of the defective address designating circuit 21, and detect whether the received address signal AD corresponds to the defective address. Indicated at numerical reference groups 23a to 23r are defective address remedy latch circuit groups. The defective address remedy latch circuit groups 23a to 23r each receive a detection result from an associated one of the defective address detecting circuits 22a to 22r, the data Din from the data input terminal 1, and the write enable signal WE from the write signal input terminal 2, and judge writing and reading states in accordance with the write enable signal WE as the main memory 20 does. Under the control of the detection result outputted from the associated one of the defective address detecting circuits 22a to 22r, the defective address remedy latch circuit groups 23a to 23r each hold the data Din in m latch circuits which are provided for, for example, each bit. A redundancy memory circuit is labeled 23 which is formed by the defective address remedy latches. A data selector is indicated at numerical reference 24 which receives and stores data Dout which is outputted from the main memory 20 and, for instance, eighteen different data Dout which are outputted from the redundancy memory circuit 23. In accordance with signals S1 to Sr which represent the detection results outputted from the defective address detecting circuits 22a to 22r, the data selector 24 selectively outputs one of the data Dout received therein through a data output terminal 3 as an output of the semiconductor memory device.
Operations of the semiconductor memory device will now be described. First in relation to where the main memory 20 does not include a defective memory cell and hence the redundancy memory circuit 23 needs not to function. In this first case, it is not necessary to blow fuse elements of redundancy memory circuit utilization flags for all of the defective address generating parts 21a to 21r of the defective address designating circuit 21. Instead, "1" is outputted as the redundancy memory circuit utilization flags. Receiving "1" as the redundancy memory circuit utilization flag from an associated one of the defective address generating parts 21a to 21r, the defective address detecting circuits 22a to 22r, regardless of the value of the address signal AD inputted thereto, each give the redundancy memory circuit 23 a signal which indicates that the address signal AD is not a defective address. Hence, the redundancy memory circuit 23 would not write thereinto the data Din which has been received from the data input terminal 1 even though the write enable signal WE demands the data Din to be written into. This is also true of reading of data from the redundancy memory circuit 23. The data selector 24, under the control of the signals S1 to Sr given from the defective address detecting circuits 22a to 22r, always selects the data Dout which is stored in the main memory 20 and outputs the same through the output terminal 3.
Next, where there is a defective memory cell in the main memory 20 will be described. In this case, it is necessary to blow a required number of fuse elements of redundancy memory circuit utilization flags for the defective address generating parts 21a to 21r of the defective address designating circuit 21 such that an address signal will be generated which represents the defective address. For example, if the defective address is an address No. q, an address signal designating the address No. q must be generated in the defective address generating part 21a. Where the semiconductor memory device is set as above, when the address signal input terminal 4 receives an address signal which designates an address No. p which is not defective, the defective address detecting circuits 22a to 22r all confirm that there is no coincidence between the received address signal AD and the address signals generated by the defective address generating parts 21a to 21r, and output a signal representing absence of coincidence to the redundancy memory circuit 23. Hence, the redundancy memory circuit 23 would not write nor read data. In addition, at this stage, if the write enable signal WE calls for the reading mode, the data selector 24 selects and outputs the data Dout which has been outputted from the main memory 20.
On the other hand, when the address signal input terminal 4 receives the address signal AD which designates the defective address No. q, the defective address detecting circuit 22a detects that the address signal AD coincides with the output signal supplied from the defective address generating part 21a, and gives the defective address remedy latch circuit 23a a signal which represents the coincidence. The defective address remedy latch circuit 23a stores the data Din which was inputted from the data input terminal 1 if the write enable signal WE calls for writing of the data. To the contrary, if the write enable signal WE demands the data to be read, the defective address remedy latch circuit 23a outputs the stored data Dout to the data selector 24. The data selector 24 then selects, of the data Dout which has been received therein, the data Dout which was given from the defective address remedy latch circuit 23a, in accordance with the output signals S1 to Sr provided from the defective address detecting circuits 22a to 22r. The data selector 24 thereafter outputs the data it has selected. At this stage, although the main memory 20 is in the process of writing and reading of data in and from the address No. q which is designated by the address signal AD, the data outputted from the main memory 20, failed to be selected by the data selector 24, will never be outputted.
Next, the data selector 24 will be described in detail with FIG. 3 in terms of structure. In FIG. 3, indicated at reference character X2 is an input terminal for receiving the data Dout which is outputted from the main memory 20, and indicated at A2 to R2 are input terminals for receiving the data Dout which are outputted from the defective address remedy latch circuit groups 23a to 23r of the redundancy memory circuit 23. Indicated at Y2 is an output terminal for outputting selected data. Indicated at ST1 to STr are input terminals for receiving the output signals S1 to Sr from the defective address detecting circuits 22a to 22r. Indicated at AN3x is an AND circuit for outputting a logical product of 1 bit of data of the data Dout which is received from the main memory 20 through the input terminal X2 and inverted logics of the signals S1 to Sr which are outputted from the defective address detecting circuits 22a to 22r . Indicated at AN3a is an AND circuit for outputting a logical product of 1 bit of data of the data Dout which is received from the defective address remedy latch circuit 23a through the input terminal A2, inverted logics of the signals S2 to Sr which are outputted from the defective address detecting circuits 22b to 22r, and the signal S1 outputted from the defective address detecting circuit 22a. Indicated at OR1 is an OR circuit for receiving the output signals of the AND circuits AN3x to AN3r and for outputting a logical sum of these signals. Table 2 shows what signal is outputted from the output terminal Y2 in response to what signals given to the input terminals X2, A2 to R2 and ST1 to STr. Signals to be received at the input terminals X2 and A2 to R2 are each 1 bit of information of the data Dout from the defective address remedy latch circuit groups 23a to 23r . Hence, if the data Dout is m-bit data, the number of the circuits of FIG. 3 that are required is m.
TABLE 2______________________________________S1   S2           . . .          Sr                              Y2______________________________________H         L     L . . . L      L   AL         H     L . . . L      L   B.         .     .              .   ..         .     .              .   ..         .     .              .   .L         L     L . . . L      H   R______________________________________
The other embodiment of the data selector 24 is shown in FIG. 4. In FIG. 4, a first data selector is indicated at 26 which receives the data Dout from the defective address remedy latch circuit groups 23a to 23r of the redundancy memory circuit 23 through the input terminals A2 to R2 while receiving the signals S1 to Sr through the input terminals ST1 to STr from the defective address detecting circuits 22b to 22r, and outputs only the data Dout which is outputted from one of the defective address remedy latch circuit groups 23a to 23r. A second data selector is labeled 27 which receives the data Dout which is given from the first data selector and the data Dout which is outputted from the main memory 20 and outputs either one of the two in accordance with the signals S1 to Sr. The structure of the first and the second data selector is shown in FIG. 5. In FIG. 5, indicated at OR2 is an OR gate for receiving the signals S1 to Sr from the input terminals ST1 to STr and outputting a logical sum of the signals. Indicated at AN3 is an AND gate which has one input terminal connected to the input terminal X2 and the other input terminal connected to an output terminal of the OR gate OR2. The AND gate AN3 creates and outputs a logical product of the input signal which are received at the input terminal X2 and an inverted logic of the output signal of the OR gate OR2. Indicated at AN4 is an AND gate which has one input terminal connected to an output terminal of the OR gate OR1 and the other input terminal connected to the output terminal of the OR gate OR2. The AND gate AN4 outputs a logical product of the output signal of the OR gate OR1 and output signal of the OR gate OR2. Indicated at OR3 is an OR gate for outputting a logical sum of the outputs of the AND gates AN 3 and AN4. The AND gates AN3 and AN4 and the OR gates OR2 and OR3 of FIG. 5 correspond to the second data selector 27 of FIG. 4, and the other circuitry portion of FIG. 5 corresponds to the first data selector 26 of FIG. 4.
The reason for forming the data selector 24 by two selectors as shown in FIG. 4 is because the second data selector needs to be simple in structure to ensure that the data Dout is transferred from the main memory 20 without delay since the main memory 20 operates slower than the redundancy memory circuit 23 and hence the data Dout from the main memory 20 is delayed as compared with the data Dout from the redundancy memory circuit 23. Here again, signals to be received at the input terminals X2 and A2 to R2 are each 1 bit of information of the data Dout from the defective address remedy latch circuit groups 23a to 23r. Hence, if the data Dout is m-bit data, the number of the circuits of FIG. 3 that are required is m.
Next, the structure of the defective address designating circuit 21 of FIG. 1 will be described with FIGS. 6, 7A and 7B. FIG. 6 is a conceptual diagram showing the structure of the defective address designating circuit. In FIG. 6, indicated at 28 is a reference coordinates detection mark which is optically read to show the location and the direction of the defective address designating circuit on a semiconductor substrate. Indicated at 29 is a redundancy memory circuit utilization flag which serves as a signal to instruct to the defective address detecting circuits 22a to 22r whether there is need for use of the defective address remedy latch circuit groups 23a to 23r of the redundancy memory circuit 23 of FIG. 1. Indicated at 30 is an address signal which is specified by binary codes A0 to An, indicated at 31 is a fuse circuit array which contains arrays of fuse elements, and indicated at 32 to 35 are each one of the arrays which form the fuse circuit array 31. In the arrays 32 to 35, which correspond to the defective address generating parts 21a to 21r of FIG. 1, respectively, the address of a defective memory cell is generated. A fuse circuit output buffer is indicated at 36 which outputs a signal derived in the fuse circuit array 31 to outside the defective address detecting circuits 22b to 22r and the like. The reference coordinates detection mark 28 is formed on the substrate by etching or other suitable method.
Now, a second preferred embodiment of the present invention will be described with FIG. 8. FIG. 8 is a block diagram showing the structure of a semiconductor memory device having redundancy according to the second preferred embodiment of the present invention. In FIG. 8, indicated at numerical reference 40 is a memory part of a redundancy memory circuit which is formed by a static random access memory (hereinafter "SRAM") and which stores the data about a defective memory cell. Indicated at 41 is an address generating circuit for receiving the output signals of the defective address detecting circuits 22a to 22r and for generating an address signal which designates the address of a memory cell which is to replace the defective memory cell has on the memory cell array 40. Indicated at NOR1 is an NOR gate for receiving the output signals of the defective address detecting circuits 22a to 22r, finding a logical product of these signals and for outputting an inverted logic of the logical product to the data selector 24. A redundancy memory circuit is labeled 42 which is comprised of the memory part 40 and the address generating circuit 41. Parts similar or corresponding to those previously described with FIG. 1 are denoted by like reference characters. In response to an output from the NOR gate NOR1, the data selector 24 of FIG. 8 selects the data Dout which is outputted from the main memory 20 or otherwise the data Dout which is outputted from the redundancy memory circuit 42.
The SRAM 40 operates generally in the same manner as the main memory 20: under the control of the write enable signal WE received at the write signal input terminal 2, the SRAM 40 stores the data Din which is received at the data input terminal 1 at an address which is designated by the address signal which is received from the address generating circuit 41 or outputs the data as the data Dout. These operations are faster than the similar operations performed by the main memory 20. A difference regarding operation between the SRAM 40 and the main memory 20 is that the SRAM 40 requires the data Din to be written at an address which is designated by the address generating circuit 41. Thus, unlike the main memory 20 which demands that the address signal AD received at the address signal input terminal 4 is in charge of the addressing, the SRAM 40 needs much less memory capacity and much less complex structure for the address decoder than those necessary in the case of the main memory 20. There is still other point to be noted as to the SRAM 40. That is, the SRAM 40, receiving the output signal of the NOR gate NOR1 at its input terminal CS, is also governed by the output signal of the NOR gate NOR1. The purpose of this is to inhibit an output from the SRAM 40 when there is no coincidence between the output from the defective address designating circuit 21 and the address signal AD which was inputted from the address signal input terminal 4.
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INTEREST;ASSIGNOR:NAKAJIMA, MICHIO;REEL/FRAME:007067/0134Effective date: 19930902RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services