Source: http://www.google.com/patents/US7443329?dq=6,654,957
Timestamp: 2016-10-26 16:27:46
Document Index: 674292620

Matched Legal Cases: ['Application No. 06016259', 'Application No. 06016268', 'Application No. 06016268', 'Application No. 06015726', 'Application No. 06', 'Application No. 06']

Patent US7443329 - Capacitive digital to analog and analog to digital converters - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA digital to analog converter (DAC) comprises X capacitive DACs that are connected together in series, wherein X is an integer greater than one. Each of the X capacitive DACs comprise M switches wherein M is an integer greater than one; a signal input; a signal output; and M capacitances that communicate...http://www.google.com/patents/US7443329?utm_source=gb-gplus-sharePatent US7443329 - Capacitive digital to analog and analog to digital convertersAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7443329 B2Publication typeGrantApplication numberUS 11/481,476Publication dateOct 28, 2008Filing dateJul 6, 2006Priority dateSep 8, 2005Fee statusPaidAlso published asCN1929313A, CN1929313B, CN1929314A, CN1929314B, CN1929315A, CN1929315B, US7379012, US7439896, US8941529, US20070052566, US20070052567, US20070052574, US20080211706Publication number11481476, 481476, US 7443329 B2, US 7443329B2, US-B2-7443329, US7443329 B2, US7443329B2InventorsSehat SutardjaOriginal AssigneeMarvell World Trade Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (29), Non-Patent Citations (26), Referenced by (2), Classifications (10), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetCapacitive digital to analog and analog to digital converters
US 7443329 B2Abstract
A digital to analog converter (DAC) comprises X capacitive DACs that are connected together in series, wherein X is an integer greater than one. Each of the X capacitive DACs comprise M switches wherein M is an integer greater than one; a signal input; a signal output; and M capacitances that communicate with the M switches, respectively, and that have first and second ends and substantially equal capacitance values. The M switches selectively connect the first ends of the M capacitances to the signal output. The M switches connect the second end of a selected one of the M capacitances to the signal input. A first DAC has a signal output that communicates with the signal input of one of the X capacitive DACs.
Q T = VC f = V RDAC C 3 + V ref ( C 1 + C 2 ) ; V = V RDAC C 3 C f + V ref C 1 + C 2 C f . The value of Cf can be set equal to C1, C2, C3 and C4 or be used to scale the output voltage and not be equal to C1, C2, C3 and C4. If Cf, C1, C2 and C3 are the same, V=VRDAC+2Vref.
As the first step in a binary search algorithm, the capacitive and resistive portions are configured to provide �Vref as described above. In other words, C4M is connected to the common node, C3M, C2M and C1M are connected to Vref and the switch SW1LSB is closed. For example, if Vin is equal to �Vref, the common terminal will be driven to (−�Vref+�Vref) =−�Vref. When this voltage is compared to ground, the output of the comparator 20 yields a logic ‘1’, implying that Vin is greater than �Vref. If Vin is equal to �Vref, the common terminal voltage is (−�Vref+�Vref) =+�Vref, and the output of the comparator 20 is a logic ‘0’. This process continues with the next MSB or LSB depending upon the value of the comparator output until all bits are resolved. While capacitive-resistive implementation is shown, capacitive-capacitive, N-stage capacitive or N-stage capacitive-resistive implementations are also contemplated.
C 1 + C 2 + C 3 C 1 + C 2 + C 3 + C 4 V ref and V ref (“D” in FIG. 12D), the switch 16 is opened, the capacitor C4 is connected in feedback arrangement and the capacitors C1, C2 and C3 are connected to Vref. Note that because the different capacitors are used as the feedback capacitor during residue amplification, the residue gain can perfectly track the capacitor mismatch. The residue voltage now looks as shown in FIG. 16. There is a variable inter-stage gain and a substantially constant maximum residue voltage.
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Heller; A Two-Stage Weighted Capacitor Network for D/A-A/D Conversion; Aug. 1979; 4 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8223056 *Jul 17, 2012Atmel CorporationCyclic digital to analog converterUS20100283651 *Nov 11, 2010Atmel CorporationCyclic digital to analog converter* Cited by examinerClassifications U.S. Classification341/150, 341/144International ClassificationH03M1/66Cooperative ClassificationH03M1/168, H03M1/682, H03M1/765, H03M1/804, H03M1/46, H03M1/806European ClassificationH03M1/68DLegal EventsDateCodeEventDescriptionFeb 17, 2009CCCertificate of correctionApr 30, 2012FPAYFee paymentYear of fee payment: 4Apr 29, 2016FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services