Source: http://www.freepatentsonline.com/9037774.html
Timestamp: 2017-10-18 04:05:36
Document Index: 689991525

Matched Legal Cases: ['Application No. 2012', '§ 42', '§ 42', '§ 42', '§ 42', '§ 42', '§ 42', '§ 1', '§ 42', '§ 42', '§ 42', '§ 1', '§ 42']

Memory module with load reducing circuit and method of operation - Netlist, Inc.
Memory module with load reducing circuit and method of operation
United States Patent 9037774
A memory module includes a plurality of memory devices and is operable in a computer system to perform memory operations in response to memory commands from a memory controller of the computer system. The memory module comprises a register device configured to receive a set of input control/address signals associated with a respective memory command (e.g., a read command or a write command) from the memory controller and to generate a set of output control/address signals in response to the set of input control/address signals. The set of output control/address signals are provided to the plurality of memory devices. The memory module further comprises a circuit to selectively isolate one or more first memory devices among the plurality of memory devices from the memory controller in response to the respective memory command so as to reduce a load of the memory module to the computer system while one or more second memory devices among the plurality of memory devices are communicating with the memory controller in response to the set of output control/address signals.
Solomon, Jefferey C. (Irvine, CA, US)
13/971231
Netlist, Inc. (Irvine, CA, US)
G06F12/00; G06F13/00; G11C5/04
711/5, 711/147
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Zheng, Jamie J.
The present application is a continuation of U.S. patent application Ser. No. 13/287,081, filed Nov. 1, 2011, which is a continuation of U.S. patent application Ser. No. 13/032,470, filed Feb. 22, 2011 and issued as U.S. Pat. No. 8,081,536, which is a continuation of U.S. patent application Ser. No. 12/955,711, filed Nov. 29, 2010 and issued as U.S. Pat. No. 7,916,574, which is a continuation of U.S. patent application Ser. No. 12/629,827, filed Dec. 2, 2009 and issued as U.S. Pat. No. 7,881,150, which is a continuation of U.S. patent application Ser. No. 12/408,652, filed Mar. 20, 2009 and issued as U.S. Pat. No. 7,636,274, which is a continuation of U.S. patent application Ser. No. 11/335,875, filed Jan. 19, 2006 and issued as U.S. Pat. No. 7,532,537, which claims the benefit of U.S. Provisional Appl. No. 60/645,087, filed Jan. 19, 2005 and which is a continuation-in-part of U.S. patent application Ser. No. 11/173,175, filed Jul. 1, 2005 and issued as U.S. Pat. No. 7,289,386, which claims the benefit of U.S. Provisional Appl. No. 60/588,244, filed Jul. 15, 2004 and which is a continuation-in-part of U.S. patent application Ser. No. 11/075,395, filed Mar. 7, 2005 and issued as U.S. Pat. No. 7,286,436, which claims the benefit of U.S. Provisional Appl. No. 60/550,668, filed Mar. 5, 2004, U.S. Provisional Appl. No. 60/575,595, filed May 28, 2004, and U.S. Provisional Appl. No. 60/590,038, filed Jul. 21, 2004. U.S. patent application Ser. Nos. 13/287,081, 13/032,470, 12/955,711, 12/629,827, 12/408,652, 11/335,875, 11/173,175, and 11/075,395, and U.S. Provisional Appl. Nos. 60/550,668, 60/575,595, 60/590,038, 60/588,244, and 60/645,087 are each incorporated in its entirety by reference herein.
1. A memory module operable in a computer system to perform memory operations in response to memory commands from a memory controller of the computer system, the memory module being coupled to the memory controller via a memory bus, the memory bus including a control/address (C/A) bus and a data bus, the data bus including a set of data (DQ) and data strobe (DQS) signal lines, comprising: a plurality of memory devices including a first set of memory devices and a second set of memory devices; a register device to receive from the memory controller a first set of input C/A signals associated with a first memory command via the C/A bus and subsequently a second set of input C/A signals associated with a second memory command via the C/A bus, the first memory command to cause the memory module receive or output a first data burst and the second memory command to cause the memory module receive or output a second data burst, the register to generate a first set of output C/A signals in response to the first set of input C/A signals and a second set of output C/A signals in response to the second set of input C/A signals, the first set of output C/A signals causing the first set of memory devices to receive or output the first data burst, the second set of output C/A signals causing the second set of memory devices to receive or output the second data burst; and a circuit coupled between the data bus and the plurality of memory devices, the circuit being coupled to the first set of memory devices via a first set of module DQ and DQS signal lines and to the second set of memory devices via a second set of module DQ and DQS signal lines, wherein the circuit in response to the first memory command couples the first set of module DQ and DQS signal lines to respective DQ and DQS signal lines of the data bus and isolates the second set of module DQ and DQS signal lines from the data bus as the memory module is receiving or outputting the first data burst in response to the first memory command, and wherein the circuit in response to the second memory command couples the second set of module DQ and DQS signal lines to respective DQ and DQS signal lines of the data bus and isolates the first set of module DQ and DQS signal lines from the data bus as the memory module is receiving or outputting the second data burst in response to the second memory command.
2. The memory module of claim 1, wherein the circuit isolates both the first set of module DQ and DQS signal lines and the second set of module DQ and DQS signal lines from the data bus when the memory module is not being accessed by the memory system.
3. The memory module of claim 1, wherein the memory bus further includes an on-die termination (ODT) bus for conveying an ODT signal from the memory controller, each ODT signal corresponding to a respective memory command from the memory controller, wherein each memory device of the plurality of memory devices includes an ODT control input to allow a signal at the control input to enable or disable an ODT circuit in the memory device, and wherein the plurality of memory devices include at least one memory device having its respective control input configured to keep the ODT circuits in the at least one memory device disabled regardless of the ODT signal from the memory controller.
4. The memory module of claim 1, wherein the circuit is to receive from the memory controller a third set of input C/A signals associated with a third memory command via the C/A bus, the third memory command being one of a refresh or precharge command, wherein the register to generate a third set of output C/A signals in response to the third set of input C/A signals, the third set of output C/A signals causing both the first set of memory devices and the second set of memory devices to perform one of a refresh operation and a pre-charge operation, and wherein the circuit in response to the third memory command couples the first set of module DQ and DQS signal lines to respective DQ and DQS signal lines of the data bus and couples the second set of module DQ and DQS signal lines to respective DQ and DQS signal lines of the data bus.
5. The memory module of claim 1, wherein the circuit further comprises multiple groups of DQ-DQS paths including a first group of DQ-DQS paths corresponding to the first set of module DQ and DQS signal lines and a second group of DQ-DQS paths corresponding to the second set of module DQ and DQS signal lines, wherein the circuit enables the first group of DQ-DQS paths and disabling the second group of DQ-DQS paths in response to the first memory command, and wherein the circuit enables the second group of DQ-DQS paths and disabling the first group of DQ-DQS paths in response to the second memory command.
6. The memory module of claim 5, wherein the register device is to translate between a system memory domain of the computer system and a physical memory device domain of the memory module, the system memory domain having a smaller number of ranks than the physical memory device domain, and wherein the first set of the plurality of memory devices and the second set of the plurality of memory devices belong to a same rank in the system memory domain and to different ranks in the physical memory device domain.
7. The memory module of claim 6, wherein the first set of input C/A signals include at least one chip-select signal and the register device outputs a greater number of chip-select signals than the at least one chip-select signal, the greater number of chip-select signals including a first chip select signal and a second chip select signal, the first chip-select signal being provided to the first set of memory devices and having an active value to select the first set of memory devices to receive or output the first data burst in response to the first memory command, the second chip-select signal being provided to the second set of memory devices and having a non-active value to keep the second set of memory devices from receiving or outputting data as the first set of memory devices are receiving or outputting the first data burst in response to the first memory command.
8. The memory module of claim 1, wherein the first memory command is a first read command and the second memory command is a second read command, wherein the first read command and the second read command are back to back adjacent read commands, and wherein the first set of memory devices output the first data burst together with a first burst of data strobes in response to the first read command, wherein the second set of memory devices output the second data burst together with a second burst of data strobes in response to the second read command, wherein the second data burst follows the first data burst on the data bus, and wherein the circuit prevents the first burst of data strobes and the second burst of data strobes from colliding with each other.
9. The memory module of claim 8, wherein each of the first burst of data strobes and the second burst of data strobes includes a pre-amble interval and a post-amble interval, and wherein the circuit combines the first burst of data strobes and the second burst of data strobes by skipping the post-amble interval of the first burst of data strobes and the pre-amble interval of the second burst of data strobes.
10. The memory module of claim 9, further comprising a termination assembly external to the plurality of memory devices and controlled in response to the ODT signal, wherein one or more DQ pins of the at least one memory device are coupled to the termination assembly so that one or more DQ signal paths between the at least one memory device and the memory controller can be terminated by the termination assembly.
11. A method of operating a memory module in response to memory commands from a memory controller, the memory module having a plurality of memory devices including a first set of memory devices and a second set of memory devices, the memory module being coupled to the memory controller via a memory bus, the memory bus including a control/address (C/A) bus and a data bus, the data bus including a set of data (DQ) and data strobe (DQS) signal lines, the first set of memory devices having a first set of DQ and DQS pins, the second set of memory devices having a second set of DQ and DQS pins, the method comprising: receiving from the memory controller a first set of input C/A signals associated with a first memory command via the C/A bus, the first memory command to cause the memory module to receive or output a first data burst; generating a first set of output C/A signals in response to the first set of input C/A signals, the first set of output C/A signals causing the first set of memory devices to receive or output the first data burst; receiving from the memory controller a second set of input control/address signals associated with a second memory command via the C/A bus, the second memory command to cause the memory module to receive or output a second data burst; generating a second set of output C/A signals in response to the second set of input C/A signals, the second set of output C/A signals causing the second set of memory devices to receive or output the second data burst; in response to the first memory command, coupling the first set DQ and DQS pins to respective DQ and DQS signal lines of the data bus and isolating the second set of module DQ and DQS pins from the data bus as the memory module is receiving or outputting the first data burst in response to the first memory command; and in response to the second memory command, coupling the second set DQ and DQS pins to respective DQ and DQS signal lines of the data bus and isolating the first set of DQ and DQS pins from the data bus as the memory module is receiving or outputting the second data burst in response to the second memory command.
12. The method of claim 11, further comprising isolating both the first set of DQ and DQS pins and the second set of DQ and DQS pins from the data bus when the memory module is not being accessed by the memory system.
13. The method of claim 11, wherein the memory bus further includes an on-die termination (ODT) bus for conveying an ODT signal corresponding to each memory command from the memory controller, wherein each of the plurality of memory devices includes ODT circuits and an ODT control input to allow a signal at the control input to enable or disable the ODT circuits in the memory device, the method further comprising keeping the ODT circuits in at least one of the plurality of memory devices disabled regardless of the ODT signal from the memory controller.
14. The method of claim 11, further comprising: receiving from the memory controller a third set of input C/A signals associated with a third memory command via the C/A bus, the third memory command being one of a refresh or precharge command; generating a third set of output C/A signals in response to the third set of input C/A signals, the third set of output C/A signals causing both the first set of memory devices and the second set of memory devices to perform one of a refresh operation and a pre-charge operation; and in response to the third memory command, coupling the first set of module DQ and DQS signal lines to respective DQ and DQS signal lines of the data bus and coupling the second set of module DQ and DQS signal lines to respective DQ and DQS signal lines of the data bus.
15. The method of claim 11, wherein the memory module further comprises multiple groups of DQ-DQS paths including a first group of DQ-DQS paths corresponding to the first set of DQ and DQS pins and a second group of DQ-DQS paths corresponding to the second set of DQ and DQS pins, the method further comprising enabling the first group of DQ-DQS paths and disabling the second group of DQ-DQS paths in response to the first memory command, and enabling the second group of DQ-DQS paths and disabling the first group of DQ-DQS paths in response to the second memory command.
16. The method of claim 15, further comprising translating between a system memory domain and a physical memory device domain, the system memory domain having a smaller number of ranks than the physical memory device domain, and wherein the first set of the plurality of memory devices and the second set of the plurality of memory devices belong to a same rank in the system memory domain and to different ranks in the physical memory device domain.
17. The method of claim 16, wherein the first set of input C/A signals include at least one chip-select signal and the register device outputs a greater number of chip-select signals than the at least one chip-select signal, the greater number of chip-select signals including a first chip select signal and a second chip select signal, the first chip-select signal being provided to the first set of memory devices and having an active value to select the first set of memory devices to receive or output the first data burst in response to the first memory command, the second chip-select signal being provided to the second set of memory devices and having a non-active value to keep the second set of memory devices from receiving or outputting data as the first set of memory devices are receiving or outputting the first data burst in response to the first memory command.
18. The method of claim 11, wherein the first memory command is a first read command and the second memory command is a second read command, wherein the first read command and the second read command are back to back adjacent read commands, and wherein the first set of memory devices output the first data burst together with a first burst of data strobes in response to the first read command, wherein the second set of memory devices output the second data burst together with a second burst of data strobes in response to the second read command, wherein the second data burst follows the first data burst on the data bus, the method further comprising combining the first burst of data strobes and the second burst of data strobes to form a third burst of data strobes on the data bus.
19. The method of claim 18, wherein each of the first burst of data strobes and the second burst of data strobes includes a pre-amble interval and a post-amble interval, and wherein combining the first burst of data strobes and the second burst of data strobes comprises skipping the post-amble interval of the first burst of data strobes and the pre-amble interval of the second burst of data strobes.
20. The method of claim 19, further comprising controlling a termination assembly external to the plurality of memory devices according to the ODT signal, wherein one or more DQ pins of the at least one memory device are coupled to the termination assembly so that one or more DQ signal paths between the at least one memory device and the memory controller can be terminated by the termination assembly.
The present invention relates generally to memory modules of a computer system, and more specifically to devices and methods for improving the performance, the memory capacity, or both, of memory modules. Description of the Related Art
In certain embodiments, a memory module includes a plurality of memory devices and is operable in a computer system to perform memory operations in response to memory commands from a memory controller of the computer system. The memory module is to be coupled to the memory controller via a memory bus, the memory bus including a control/address (C/A) bus and a data bus. The memory module comprises a register device configured to receive a set of input control/address signals associated with a respective memory command (e.g., a read command or a write command) from the memory controller and to generate a set of output control/address signals in response to the set of input control/address signals. The set of output control/address signals are provided to the plurality of memory devices. The memory module further comprises circuit coupled between the data bus and the plurality of memory devices, the circuit to selectively isolate one or more first memory devices among the plurality of memory devices from the data bus in response to the respective memory command so as to reduce a load of the memory module to the computer system while one or more second memory devices among the plurality of memory devices are communicating with the memory controller in response to the set of output control/address signals.
In certain embodiments, the circuit further comprises DQ-DQS paths, and logic that selectively isolates the one or more first memory devices by disabling at least one first group of DQ-DQS paths. In certain embodiments, the logic is further configured to enable at least one second group of DQ-DQS paths in response to the respective memory command so as to allow the one or more second memory devices to communicate data with the memory controller in response to the output control/address signals. In certain embodiments, the circuit includes a buffer circuit to electrically and selectively isolate the one or more first memory devices from the memory controller and to selectively allow one or more second memory devices to communicate data with the memory controller, the buffer circuit adding a time delay (e.g., one clock cycle) to a data signal from the one or more second memory devices to the memory controller. In certain embodiments, the logic provides functions of a data path multiplexer/demultiplexer using the time delay. In certain embodiments, the logic is further configured to translate between a system memory domain and a physical memory device domain by generating a greater number of output control/address signals than the number of input control/address signals in response to the respective memory command. In certain embodiments, the logic receives one or more input chip select signals associated with the respective memory command, the one or more input chip select signals being less in number than chip-select signals in the output control/address signals.
In certain embodiments, a method of operating a memory module comprises receiving a set of input control/address signals associated with a respective memory command from the memory controller, generating a set of output control/address signals in response to the set of input control/address signals, and providing the set of output control/address signals to a plurality of memory devices operable to perform memory operations in response to memory commands from a memory controller. The method further comprises monitoring the memory commands from the memory controller, and selectively isolating one or more first memory devices among the plurality of memory devices from the memory controller in response to the respective memory command so as to reduce a load of the memory module to the memory controller while one or more second memory devices among the plurality of memory devices are communicating with the memory controller in response to the set of output control/address signals. In certain embodiments, the method further comprises disabling at least one first group of DQ-DQS paths to isolate the one or more first memory devices and selectively enabling at least one second group of DQ-DQS paths to allow the one or more second memory devices to communicate data with the memory controller in response to the output control/address signals. In certain embodiments, the set of input control/address signals include at least one chip-select signal and the set of output control/address signals include a greater number of chip-select signals.
FIG. 2 schematically illustrates a circuit diagram of two memory devices 30a, 30b of a conventional memory module showing the interconnections between the DQ data signal lines 102a, 102b of the memory devices 30a, 30b and the DQS data strobe signal lines 104a, 104b of the memory devices 30a, 30b. Each of the memory devices 30a, 30b has a plurality of DQ data signal lines and a plurality of DQS data strobe signal lines, however, for simplicity, FIG. 2 only illustrates a single DQ data signal line and a single DQS data strobe signal line for each memory device 30a, 30b. The DQ data signal lines 102a, 102b and the DQS data strobe signal lines 104a, 104b are typically conductive traces etched on the printed circuit board of the memory module. As shown in FIG. 2, each of the memory devices 30a, 30b has their DQ data signal lines 102a, 102b electrically coupled to a common DQ line 112 and their DQS data strobe signal lines 104a, 104b electrically coupled to a common DQS line 114. The common DQ line 112 and the common DQS line 114 are electrically coupled to the memory controller 20 of the computer system. Thus, the computer system is exposed to the loads of both memory devices 30a, 30b concurrently.
As schematically illustrated by FIGS. 3A and 3B, an example memory module 10 compatible with certain embodiments described herein comprises a circuit 40 which selectively isolates one or both of the DQ data signal lines 102a, 102b of the two memory devices 30a, 30b from the common DQ data signal line 112 coupled to the computer system. Thus, the circuit 40 selectively allows a DQ data signal to be transmitted from the memory controller 20 of the computer system to one or both of the DQ data signal lines 102a, 102b. In addition, the circuit 40 selectively allows one of a first DQ data signal from the DQ data signal line 102a of the first memory device 30a or a second DQ data signal from the DQ data signal line 102b of the second memory device 30b to be transmitted to the memory controller 20 via the common DQ data signal line 112 (see, e.g., triangles on the DQ and DQS lines of FIGS. 3A and 3B which point towards the memory controller). While various figures of the present application denote read operations by use of DQ and DQS lines which have triangles pointing towards the memory controller, certain embodiments described herein are also compatible with write operations (e.g., as would be denoted by triangles on the DQ or DQS lines pointing away from the memory controller).
For example, in certain embodiments, the circuit 40 comprises a pair of switches 120a, 120b on the DQ data signal lines 102a, 102b as schematically illustrated by FIG. 3A. Each switch 120a, 120b is selectively actuated to selectively electrically couple the DQ data signal line 102a to the common DQ signal line 112, the DQ data signal line 102b to the common DQ signal line 112, or both DQ data signal lines 102a, 102b to the common DQ signal line 112. In certain other embodiments, the circuit 40 comprises a switch 120 electrically coupled to both of the DQ data signal lines 102a, 102b, as schematically illustrated by FIG. 3B. The switch 120 is selectively actuated to selectively electrically couple the DQ data signal line 102a to the common DQ signal line 112, the DQ data signal line 102b to the common DQ signal line 112, or both DQ signal lines 102a, 102b to the common DQ signal line 112. Circuits 40 having other configurations of switches are also compatible with embodiments described herein. While each of the memory devices 30a, 30b has a plurality of DQ data signal lines and a plurality of DQS data strobe signal lines, FIGS. 3A and 3B only illustrate a single DQ data signal line and a single DQS data strobe signal line for each memory device 30a, 30b for simplicity. The configurations schematically illustrated by FIGS. 3A and 3B can be applied to all of the DQ data signal lines and DQS data strobe signal lines of the memory module 10.
In certain embodiments, the circuit 40 selectively isolates the loads of ranks of memory devices 30 from the computer system. As schematically illustrated in FIGS. 4A and 4B, example memory modules 10 compatible with certain embodiments described herein comprise a first number of memory devices 30 arranged in a first number of ranks 32. The memory modules 10 of FIGS. 4A and 4B comprises two ranks 32a, 32b, with each rank 32a, 32b having a corresponding set of DQ data signal lines and a corresponding set of DQS data strobe lines. Other numbers of ranks (e.g., four ranks) of memory devices 30 of the memory module 10 are also compatible with certain embodiments described herein. For simplicity, FIGS. 4A and 4B illustrate only a single DQ data signal line and a single DQS data strobe signal line from each rank 32.
The circuit 40 of FIG. 4A selectively isolates one or more of the DQ data signal lines 102a, 102b of the two ranks 32a, 32b from the computer system. Thus, the circuit 40 selectively allows a DQ data signal to be transmitted from the memory controller 20 of the computer system to the memory devices 30 of one or both of the ranks 32a, 32b via the DQ data signal lines 102a, 102b. In addition, the circuit 40 selectively allows one of a first DQ data signal from the DQ data signal line 102a of the first rank 32a and a second DQ data signal from the DQ data signal line 102b of the second rank 32b to be transmitted to the memory controller 20 via the common DQ data signal line 112. For example, in certain embodiments, the circuit 40 comprises a pair of switches 120a, 120b on the DQ data signal lines 102a, 102b as schematically illustrated by FIG. 4A. Each switch 120a, 120b is selectively actuated to selectively electrically couple the DQ data signal line 102a to the common DQ data signal line 112, the DQ data signal line 102b to the common DQ data signal line 112, or both DQ data signal lines 102a, 102b to the common DQ data signal line 112. In certain other embodiments, the circuit 40 comprises a switch 120 electrically coupled to both of the DQ data signal lines 102a, 102b, as schematically illustrated by FIG. 4B. The switch 120 is selectively actuated to selectively electrically couple the DQ data signal line 102a to the common DQ data signal line 112, the DQ data signal line 102b to the common DQ data signal line 112, or both DQ data signal lines 102a, 102b to the common DQ data signal line 112. Circuits 40 having other configurations of switches are also compatible with embodiments described herein.
//-------------------------DDR 2 FET
assign sel = ~brs0N_R | ~brs1N_R | ~brs2N_R | ~brs3N_R;
assign actv_cmd_R = !rasN_R & casN_R & weN_R; // activate cmd
assign rd_R1 = sel & rd_cmd_R; // rd cmd cyc 1
FIGS. 8A-8D schematically illustrate circuit diagrams of example memory modules 10 comprising a circuit 40 which multiplexes the DQS data strobe signal lines 104a, 104b of two ranks 32a, 32b from one another in accordance with certain embodiments described herein. While the DQS data strobe signal lines 104a, 104b of FIGS. 8A-8D correspond to two ranks 32a, 32b of memory devices 30, in certain other embodiments, the circuit 40 multiplexes the DQS data strobe signal lines 104a, 104b corresponding to two individual memory devices 30a, 30b.
FIG. 8A schematically illustrates a circuit diagram of an exemplary memory module 10 comprising a circuit 40 in accordance with certain embodiments described herein. In certain embodiments, BBARX collisions are avoided by a mechanism which electrically isolates the DQS data strobe signal lines 104a, 104b from one another during the transition from the first read data burst of one rank 32a of memory devices 30 to the second read data burst of another rank 32b of memory devices 30.
In certain embodiments, as schematically illustrated by FIG. 8A, the circuit 40 comprises a first switch 130a electrically coupled to a first DQS data strobe signal line 104a of a first rank 32a of memory devices 30 and a second switch 130b electrically coupled to a second DQS data strobe signal line 104b of a second rank 32b of memory devices 30. In certain embodiments, the time for switching the first switch 130a and the second switch 130b is between the two read data bursts (e.g., after the last DQS data strobe of the read data burst of the first rank 32a and before the first DQS data strobe of the read data burst of the second rank 32b). During the read data burst for the first rank 32a, the first switch 130a is enabled. After the last DQS data strobe of the first rank 32a and before the first DQS data strobe of the second rank 32b, the first switch 130a is disabled and the second switch 130b is enabled.
As shown in FIG. 8A, each of the ranks 32a, 32b otherwise involved in a BBARX collision have their DQS data strobe signal lines 104a, 104b selectively electrically coupled to the common DQS line 114 through the circuit 40. The circuit 40 of certain embodiments multiplexes the DQS data strobe signal lines 104a, 104b of the two ranks 32a, 32b of memory devices 30 from one another to avoid a BBARX collision.
In certain embodiments, as schematically illustrated by FIG. 8B, the circuit 40 comprises a switch 130 which multiplexes the DQS data strobe signal lines 104a, 104b from one another. For example, the circuit 40 receives a DQS data strobe signal from the common DQS data strobe signal line 114 and selectively transmits the DQS data strobe signal to the first DQS data strobe signal line 104a, to the second DQS data strobe signal line 104b, or to both DQS data strobe signal lines 104a, 104b. As another example, the circuit 40 receives a first DQS data strobe signal from the first rank 32a of memory devices 30 and a second DQS data strobe signal from a second rank 32b of memory devices 30 and selectively switches one of the first and second DQS data strobe signals to the common DQS data strobe signal line 114.
In certain embodiments, the circuit 40 also provides the load isolation described above in reference to FIGS. 1-5. For example, as schematically illustrated by FIG. 8C, the circuit 40 comprises both the switch 120 for the DQ data signal lines 102a, 102b and the switch 130 for the DQS data strobe signal lines 104a, 104b. While in certain embodiments, the switches 130 are integral with a logic element of the circuit 40, in certain other embodiments, the switches 130 are separate components which are operatively coupled to a logic element 122 of the circuit 40, as schematically illustrated by FIG. 8D. In certain such embodiments, the control and timing of the switch 130 is performed by the circuit 40 which is resident on the memory module 10. Example switches 130 compatible with embodiments described herein include, but are not limited to field-effect transistor (FET) switches, such as the SN74AUC1G66 single bilateral analog switch available from Texas Instruments, Inc. of Dallas, Tex., and multiplexers, such as the SN74AUC2G53 2:1 analog multiplexer/demultiplexer available from Texas Instruments, Inc. of Dallas, Tex.
The circuit 40 of certain embodiments controls the isolation of the DQS data strobe signal lines 104a, 104b by monitoring commands received by the memory module 10 from the computer system and producing “windows” of operation whereby the appropriate switches 130 are activated or deactivated to enable and disable the DQS data strobe signal lines 104a, 104b to mitigate BBARX collisions. In certain other embodiments, the circuit 40 monitors the commands received by the memory module 10 from the computer system and selectively activates or deactivates the switches 120 to enable and disable the DQ data signal lines 102a, 102b to reduce the load of the memory module 10 on the computer system. In still other embodiments, the circuit 40 performs both of these functions together.
In certain embodiments, the plurality of memory devices 30 are arranged in a first number of ranks 32. For example, in certain embodiments, the memory devices 30 are arranged in four ranks 32a, 32b, 32c, 32d, as schematically illustrated by FIG. 9A. In certain other embodiments, the memory devices 30 are arranged in two ranks 32a, 32b, as schematically illustrated by FIG. 9B. Other numbers of ranks 32 of the memory devices 30 are also compatible with embodiments described herein.
In Logic State 1: CS0 is active low, An+1 is non-active, and Command is active. CSOA is pulled low, thereby selecting Rank 0.
In Logic State 2: CS0 is active low, An+1 is active, and Command is active. CSOB is pulled low, thereby selecting Rank 1.
In Logic State 3: CS0 is active low, An+1 is Don't Care, and Command is active high. CS0A and CSOB are pulled low, thereby selecting Ranks 0 and 1.
In Logic State 7: CS0 and CS1 are pulled non-active high, which deselects all ranks, i.e., CSOA, CS1B, CS1A, and CS1B are pulled high.
0 0 0 I x x REFRESH 0 0
for “× 4”configuration
for “× 8”configuration
for “× 16”configuration
| (~rs0_in_N & ~ras_in_N & cas_in_N & we_in_N &~ba2_in) // activate
if(~reset_N) // reset
if(~reset_N) cl5 <= 1′b0 ;
assign pre_cyc2_enfet = (wr_cmd cyc1 & acs_cyc1 & cl3) // wr brst cl3 preamble
acs_cyc2 <= acs_cycl ; // cs active
| ( rasN_R & 1_a13_00& ~bnk1_R & ~bnk0_R & cas_i)
| ( rasN_R & 1_a13_01& ~bnk1_R & bnk0_R & cas_i)
| ( rasN_R & 1_a13_10& bnk1_R & ~bnk0_R & cas_i)
| ( rasN_R & 1_a13_11& bnk1_R & bnk0_R & cas_i)
FIG. 10A schematically illustrates an exemplary memory module 10 which doubles the rank density in accordance with certain embodiments described herein. The memory module 10 has a first memory capacity. The memory module 10 comprises a plurality of substantially identical memory devices 30 configured as a first rank 32a and a second rank 32b. In certain embodiments, the memory devices 30 of the first rank 32a are configured in pairs, and the memory devices 30 of the second rank 32b are also configured in pairs. In certain embodiments, the memory devices 30 of the first rank 32a are configured with their respective DQS pins tied together and the memory devices 30 of the second rank 32b are configured with their respective DQS pins tied together, as described more fully below. The memory module 10 further comprises a circuit 40 which receives a first set of address and command signals from a memory controller (not shown) of the computer system. The first set of address and command signals is compatible with a second memory capacity substantially equal to one-half of the first memory capacity. The circuit 40 translates the first set of address and command signals into a second set of address and command signals which is compatible with the first memory capacity of the memory module 10 and which is transmitted to the first rank 32a and the second rank 32b.
The first rank 32a of FIG. 10A has 18 memory devices 30 and the second rank 32b of FIG. 10A has 18 memory devices 30. Other numbers of memory devices 30 in each of the ranks 32a, 32b are also compatible with embodiments described herein.
For example, a 1-Gb 128M×8-bit DDR-1 DRAM memory device uses row addresses A13-A0 and column addresses A11 and A9-A0. A pair of 512-Mb 128M×4-bit DDR-1 DRAM memory devices uses row addresses A12-Ao and column addresses A12, A11, and A9-A0. In certain embodiments, a memory controller of a computer system utilizing a 1-GB 128M×8 memory module 10 comprising pairs of the 512-Mb 128M×4 memory devices 30 supplies the address and command signals including the extra row address (A13) to the memory module 10. The circuit 40 receives the address and command signals from the memory controller and converts the extra row address (A13) into an extra column address (A12).
FIG. 10B schematically illustrates an exemplary circuit 40 compatible with embodiments described herein. The circuit 40 is used for a memory module 10 comprising pairs of “×4” memory devices 30 which mimic individual “×8” memory devices. In certain embodiments, each pair has the respective DQS pins of the memory devices 30 tied together. In certain embodiments, as schematically illustrated by FIG. 10B, the circuit 40 comprises a programmable-logic device (PLD) 42, a first multiplexer 44 electrically coupled to the first rank 32a of memory devices 30, and a second multiplexer 46 electrically coupled to the second rank 32b of memory devices 30. In certain embodiments, the PLD 42 and the first and second multiplexers 44, 46 are discrete elements, while in other certain embodiments, they are integrated within a single integrated circuit. Persons skilled in the art can select an appropriate PLD 42, first multiplexer 44, and second multiplexer 46 in accordance with embodiments described herein.
In the exemplary circuit 40 of FIG. 10B, during a row access procedure (CAS is high), the first multiplexer 44 passes the A12 address through to the first rank 32, the second multiplexer 46 passes the A12 address through to the second rank 34, and the PLD 42 saves or latches the A13 address from the memory controller. In certain embodiments, a copy of the A13 address is saved by the PLD 42 for each of the internal banks (e.g., 4 internal banks) per memory device 30. During a subsequent column access procedure (CAS is low), the first multiplexer 44 passes the previously-saved A13 address through to the first rank 32a as the A12 address and the second multiplexer 46 passes the previously-saved A13 address through to the second rank 32b as the A12 address. The first rank 32a and the second rank 32b thus interpret the previously-saved A13 row address as the current A12 column address. In this way, in certain embodiments, the circuit 40 translates the extra row address into an extra column address in accordance with certain embodiments described herein.
FIG. 11A schematically illustrates an exemplary memory module 10 which doubles number of ranks in accordance with certain embodiments described herein. The memory module 10 has a first plurality of memory locations with a first memory density. The memory module 10 comprises a plurality of substantially identical memory devices 30 configured as a first rank 32a, a second rank 32b, a third rank 32c, and a fourth rank 32d. The memory module 10 further comprises a circuit 40 which receives a first set of address and command signals from a memory controller (not shown). The first set of address and command signals is compatible with a second plurality of memory locations having a second memory density. The second memory density is substantially equal to one-half of the first memory density. The circuit 40 translates the first set of address and command signals into a second set of address and command signals which is compatible with the first plurality of memory locations of the memory module 10 and which is transmitted to the first rank 32a, the second rank 32b, the third rank 32c, and the fourth rank 32d.
Each rank 32a, 32b, 32c, 32d of FIG. 11A has 9 memory devices 30. Other numbers of memory devices 30 in each of the ranks 32a, 32b, 32c, 32d are also compatible with embodiments described herein.
To access the additional memory density of the high-density memory module 10, the two chip-select signals (CS0, CS1) are used with other address and command signals to gate a set of four gated CAS signals. For example, to access the additional ranks of four-rank 1-GB 128M×8-byte DDR-1 DRAM memory module, the CS0 and CS1 signals along with the other address and command signals are used to gate the CAS signal appropriately, as schematically illustrated by FIG. 11A. FIG. 11B schematically illustrates an exemplary circuit 40 compatible with embodiments described herein. In certain embodiments, the circuit 40 comprises a programmable-logic device (PLD) 42 and four “OR” logic elements 52, 54, 56, 58 electrically coupled to corresponding ranks 32a, 32b, 32c, 32d of memory devices 30.
In the embodiment schematically illustrated by FIG. 11B, the PLD 42 transmits each of the four “enabled CAS” (ENCAS0a, ENCAS0b, ENCAS1a, ENCAS1b) signals to a corresponding one of the “OR” logic elements 52, 54, 56, 58. The CAS signal is also transmitted to each of the four “OR” logic elements 52, 54, 56, 58. The CAS signal and the “enabled CAS” signals are “low” true signals. By selectively activating each of the four “enabled CAS” signals which are inputted into the four “OR” logic elements 52, 54, 56, 58, the PLD 42 is able to select which of the four ranks 32a, 32b, 32c, 32d is active.
In certain embodiments, the PLD 42 uses sequential and combinatorial logic procedures to produce the gated CAS signals which are each transmitted to a corresponding one of the four ranks 32a, 32b, 32c, 32d. In certain other embodiments, the PLD 42 instead uses sequential and combinatorial logic procedures to produce four gated chip-select signals (e.g., CS0a, CS0b, CS1a, and CS1b) which are each transmitted to a corresponding one of the four ranks 32a, 32b, 32c, 32d.
When connecting the first memory device 310 and, the second memory device 320 together to form a double word width, both the first memory device 310 and the second memory device 320 are enabled at the same time (e.g., by a common CS signal). Connecting the first memory device 310 and the second memory device 320 by tying the DQS pins 312, 322 together, as shown in FIG. 14, results in a reduced effective termination resistance for the DQS pins 312, 322. For example, for the exemplary configuration of FIG. 14, the effective termination resistance for the DQS pins 312, 322 is approximately 37.5 ohms, which is one-half the desired ODT resistance (for 75-ohm internal termination resistors) to reduce signal reflections since the internal termination resistors 352, 354 of the two memory devices 310, 320 are connected in parallel. This reduction in the termination resistance can result in signal reflections causing the memory device to malfunction.
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