Source: http://www.google.com/patents/US6982485?dq=6,034,652
Timestamp: 2018-01-22 19:26:30
Document Index: 567258421

Matched Legal Cases: ['Application No. 2', 'Application No. 3', 'Application No. 60', 'Application No. 62', 'Application No. 62258632', 'Application No. 02133391', 'Application No. 02211544', 'Application No. 02237713', 'Application No. 03183498', 'Application No. 91311873', 'Application No. 03264522', 'Application No. 03297304', 'Application No. 09']

Patent US6982485 - Stacking structure for semiconductor chips and a semiconductor package using it - Google Patents
A semiconductor package and method of producing the same has a substrate having a resin layer with first and second surfaces. A plurality of electrically conductive patterns are formed on the resin layer. An aperture is also formed at the center of the substrate. A first semiconductor chip has first...http://www.google.com/patents/US6982485?utm_source=gb-gplus-sharePatent US6982485 - Stacking structure for semiconductor chips and a semiconductor package using it
Publication number US6982485 B1
Application number US 10/076,701
Publication number 076701, 10076701, US 6982485 B1, US 6982485B1, US-B1-6982485, US6982485 B1, US6982485B1
Inventors Seon Goo Lee, Young Ho Kim, Choon Heung Lee
Patent Citations (108), Non-Patent Citations (23), Referenced by (61), Classifications (62), Legal Events (5)
Stacking structure for semiconductor chips and a semiconductor package using it
US 6982485 B1
In the third step S3, the first semiconductor chip 1 is placed in the aperture 31 of the substrate 20. The first semiconductor chip 1 having the first and second surfaces 1 a and 1 b is attached onto the surface of the adhesive tape 90 formed at the aperture 31 of the substrate 20, as shown in FIG. 6C. The first semiconductor chip 1 has a plurality of input/output pads 1 c formed on the edge of the second surface 1 b.
In the fourth step S4 for wire-bonding the bond finger 28 of the electrically conductive pattern 26 of the substrate 20 and the first semiconductor chip 1, one end of the first conductive wire 40 is ball-bonded 41 to the bond finger 28 of the electrically conductive pattern 26 of the substrate and the other end is stitch-bonded 43 to the input/output pads 1 c of the first semiconductor chip 1. Specifically, the conductive ball 42 is formed on the input/output pads 1 c of the first semiconductor chip 1. The conductive ball 42 is formed of gold, solder or its equivalent, but the material is not limited thereto. Then, one end of the first conductive wire 40 is ball-bonded 41 to the bond finger 28 of the electrically conductive pattern 26 of the substrate 20 and the other end is stitch-bonded 43 to the surface of the conductive ball 42 that was formed in advance. This wire bonding is carried out by using a capillary 80 of a wire bonder, as shown in FIG. 6D. According to this first wire bonding step, the maximum curved portion of the first conductive wire 40 is not placed at the second surface 1 b of the first semiconductor chip 1 but at the electrically conductive pattern 26 of the substrate 20.
US6313519 * Apr 19, 1995 Nov 6, 2001 Lsi Logic Corporation Support for semiconductor bond wires
US6607943 * Aug 2, 2000 Aug 19, 2003 Micron Technology, Inc. Low profile ball grid array package
US6784534 * Feb 6, 2002 Aug 31, 2004 Amkor Technology, Inc. Thin integrated circuit package having an optically transparent window
US6798063 * Aug 29, 2001 Sep 28, 2004 Micron Technology, Inc. Low profile ball grid array package
US20020047213 * Sep 27, 2001 Apr 25, 2002 Mitsuru Komiyama Multi-chip package type semiconductor device
US20020079570 * Aug 7, 2001 Jun 27, 2002 Siliconware Precision Industries Co., Ltd, Semiconductor package with heat dissipating element
1 Abstract 4-56262, English Abstract of Japanese Patent Application No. 2-167207, Published Feb. 24, 1992, Inventor Susumu Sanai.
2 Abstract 5-75015, English Abstract of Japanese Patent Application No. 3-234485, Published Mar. 26, 1993, Inventor Akio Goto.
3 Abstract 62-126661, English Abstract of Japanese Patent Application No. 60-267712, Published Jun. 8, 1987, Inventor Hiromi Sakata.
4 Abstract 63-244654, English Abstract of Japanese Patent Application No. 62-76176, Published Oct. 12, 1988, Inventor Hiromichi Sawatani.
5 Patent No. JP1028856, English Abstract, Published Jan. 31, 1989, Inventor Takeuchi Ryosuke.
6 Patent No. JP1071162, English Abstract, Published Mar. 16, 1989, Inventor Wantanabe Masayuki.
7 Patent No. JP3169062 English Abstract, Published Jul. 22, 1991, Inventor Goto Seiji.
8 Patent No. JP4056252, English Abstract, Published Feb. 24, 1992, Inventor Sanai Susumu.
9 Patent No. JP56062351, English Abstract, Published May 28, 1981, Inventor Sano Yuji.
10 Patent No. JP60182731, English Abstract, Published Sep. 18, 1985, Inventor Kawaguchi Tamotsu.
11 Patent No. JP61117858, English Abstract, Published Jun. 5, 1986, Inventor Takahashi Hidekazu.
12 Patent No. JP62126661, English Abstract, Published Jun. 8, 1987, Inventor Sakata Hiromi.
13 Patent No. JP63128736, English Abstract, Published Jun. 1, 1988, Inventor Nishimura Yoshiro.
14 Patent No. JP64001269, English Abstract, Published Jan. 5, 1989, Inventor Watanabe Masayuki.
15 Publication No. 01099248, English Abstract of Japanese Patent Application No. 62258632, Published Apr. 18, 1989, Inventor Kosugi Ryuichi.
16 Publication No. 04028260, English Abstract of Japanese Patent Application No. 02133391, Published Jan. 30, 1992, Inventor Nakano Katsuhiro.
17 Publication No. 04096358, English Abstract of Japanese Patent Application No. 02211544, Published Mar. 27, 1992, Inventor Fukui Yuichi.
18 Publication No. 04116859 English Abstract of Japanese Patent Application No. 02237713, Published Apr. 17, 1992, Inventor Sawano Hiroshi.
19 Publication No. 05013665, English Abstract of Japanese Patent Application No. 03183498, Published Jan. 22, 1993, Inventor Yamauchi Fushimi and Kawazumi Masaru.
20 Publication No. 0503201, European Patent Application No. 91311873.3, Published Sep. 16, 1992, Inventor Kabushiki Kaisha.
21 Publication No. 05109975, English Abstract of Japanese Patent Application No. 03264522, Published Apr. 30, 1993, Inventor Ryuji et al.
22 Publication No. 05136323, English Abstract of Japanese Patent Application No. 03297304, Published Jun. 1, 1993, Inventor Yoshino Susumu and Chikama Hiroki.
23 Publication No. 10-256470, English Abstract of Japanese Patent Application No. 09-055176, Published Sep. 25, 1998, Inventor Tsubonoya Makoto.
US8441111 * Apr 5, 2012 May 14, 2013 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US20090315130 * Aug 11, 2004 Dec 24, 2009 Young-Hoon Ro Solid-state imaging apparatus and method for manufacturing the same
US20100127402 * Jan 25, 2010 May 27, 2010 Interconnect Portfolio Llc Interconnect System without Through-Holes
US20130083583 * Apr 5, 2012 Apr 4, 2013 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
CN102144291B * Nov 17, 2009 Nov 25, 2015 先进封装技术私人有限公司 半导体基板、封装与装置
U.S. Classification 257/737, 257/780, 257/787, 257/E23.061, 257/738, 257/784, 257/E23.101, 257/E25.013, 257/777
International Classification H01L29/40, H01L23/48, H01L23/28, H01L23/52
Cooperative Classification H01L2924/00014, H01L2924/181, H01L2924/07802, H01L24/48, H01L2224/48471, H01L24/45, H01L2924/15321, H01L2225/06541, H01L2224/85191, H01L2225/06586, H01L24/78, H01L2224/32145, H01L24/49, H01L2924/014, H01L2924/01013, H01L23/36, H01L2924/15153, H01L2924/01033, H01L2224/48479, H01L2924/01074, H01L25/0657, H01L2225/06555, H01L2224/4945, H01L2224/48091, H01L2924/01079, H01L2224/48465, H01L2924/1517, H01L2224/45147, H01L2224/48227, H01L2224/45124, H01L24/85, H01L2224/48475, H01L2224/85051, H01L2225/0651, H01L2924/01014, H01L2924/01047, H01L2224/85001, H01L2225/06575, H01L2224/85986, H01L24/32, H01L2924/01029, H01L2224/78301, H01L2224/73265, H01L2924/14, H01L23/49805, H01L2924/1532, H01L2924/15311, H01L2224/45144, H01L2224/85815
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