Source: http://www.google.com/patents/US20020015293?dq=7,346,539
Timestamp: 2017-09-22 23:03:59
Document Index: 248006729

Matched Legal Cases: ['arts 7', 'arts 7', 'arts 7', 'art 64', 'art 64', 'art 64', 'arts 130']

Patent US20020015293 - Low-EMI electronic apparatus, low-EMI circuit board, and method of ... - Google Patents
A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation of a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure,...http://www.google.com/patents/US20020015293?utm_source=gb-gplus-sharePatent US20020015293 - Low-EMI electronic apparatus, low-EMI circuit board, and method of manufacturing the low-EMI circuit board
Publication number US20020015293 A1
Application number US 09/956,909
Also published as US6353540, US6707682, WO1996022008A1
Publication number 09956909, 956909, US 2002/0015293 A1, US 2002/015293 A1, US 20020015293 A1, US 20020015293A1, US 2002015293 A1, US 2002015293A1, US-A1-20020015293, US-A1-2002015293, US2002/0015293A1, US2002/015293A1, US20020015293 A1, US20020015293A1, US2002015293 A1, US2002015293A1
Inventors Yutaka Akiba, Yasunori Narizuka, Hirayoshi Tanei, Naoya Kitamura
Original Assignee Yutaka Akiba, Yasunori Narizuka, Hirayoshi Tanei, Naoya Kitamura
Referenced by (57), Classifications (73), Legal Events (6)
Low-EMI electronic apparatus, low-EMI circuit board, and method of manufacturing the low-EMI circuit board
US 20020015293 A1
A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation of a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed. This invention can remarkably suppress unwanted radiation by absorbing the potential fluctuation (resonance) which occurs in a power supply loop by equivalently reducing the Q-value of the stray capacitance, absorbing the standing wave by the parallel plate lines matchedly terminated and, closing and shielding the parallel plate lines.
1. A structure comprising a first conductor layer, a second conductor layer, a third conductor layer, a first dielectric material layer, a second dielectric material layer and a resistor layer, wherein:
said resistor layer, said first dielectric material layer, said second dielectric material layer and said third conductor layer are disposed between said first conductor layer and said second conductor layer;
said resistor layer is sandwiched by said first conductor layer and said second conductor layer;
said first dielectric material layer is sandwiched by said first conductor layer and said third conductor layer;
said second dielectric material layer is sandwiched by said third conductor layer and said second dielectric material layer; and
said resistor layer is connected electrically to said first conductor layer and said second conductor layer.
2. A structure according to claim 1, wherein said first conductor layer is a first ground layer, said second conductor layer is a second ground layer and said third conductor layer is a power source layer.
3. A circuit board comprising a first conductor layer, a second conductor layer, a resistor and a dielectric material layer, wherein:
said resistor layer and said dielectric material layer are disposed between said first conductor layer and said second conductor layer; and
said resistor layer is disposed on a peripheral portion of said first conductor layer.
4. A circuit board according to claim 3, wherein said resistor layer reduces a potential fluctuation caused at least in said first conductor layer.
5. A circuit board according to claim 3, wherein said first conductor layer or said second conductor layer is divided.
6. A circuit board comprising a first conductor layer, a second conductor layer, a first resistor, a second resistor and a dielectric material layer, wherein:
said first resistor, said second resistor and said dielectric material layer are disposed between said first conductor layer and said second conductor layer;
said dielectric material layer is disposed between said first resistor and said second resistor;
said first resistor is disposed on a peripheral portion of said first conductor layer; and
said second resistor is disposed on a peripheral portion of said second conductor layer.
7. A circuit board according to claim 6, wherein said first resistor and said second resistor reduce potential fluctuations caused in said first conductor layer and said second conductor layer.
8. A circuit board according to claim 6, wherein said first conductor layer or said second conductor layer is divided.
9. A circuit board according to claim 6, wherein a shape of said first resistor is the same as a shape of said second resistor.
10. A circuit board comprising a ground layer, a power source layer, a first resistor, a second resistor and a dielectric material layer, wherein:
said first resistor, said second resistor and said dielectric material layer are disposed between said ground layer and said power source layer;
said first resistor is disposed on a peripheral portion of said ground layer; and
said second resistor is disposed on a peripheral portion of said power source layer.
11. A circuit board according to claim 10, wherein a shape of said first resistor is the same as a shape of said second resistor.
12. A circuit board comprising a first conductor layer, a second conductor layer, a first resistor, a second resistor and a dielectric material layer, wherein:
said first resistor is disposed on a peripheral portion of said first conductor layer;
said second resistor is disposed on a peripheral portion of said second conductor layer; and
said dielectric material layer is disposed between said first resistor and said second resistor.
13. A circuit board according to claim 12, wherein a shape of said first resistor is the same as a shape of said second resistor.
14. An electronic apparatus having electronic components provided on said structure according to claim 1.
15. An electronic apparatus having electronic components provided on said circuit board according to claim 3.
This is a continuation application of U.S. application Ser. No. 08/860,181, filed Jul. 10, 1997, which is a 371 filing of PCT/JP96/00021, filed on Jan. 10, 1996, and the entire disclosures of which are incorporated herein by reference.
As a technical reference relating thereto, JPA-3-14284 is cited. The JP-A-3-14284 discloses a built-in structure to a printed circuit board in place of discrete parts of a ferrite core and a ferrite beads which are existing countermeasure parts.
In order to enhance the EMC performance of the product, various countermeasure parts such as a common mode choke, a filter and a bypass capacitor for an I/O unit and a power supply have been used from the past but these parts present demerits of {circle over (1)} increase of a cost, {circle over (2)} problem to so-called high packaging density such as minituarization, thinning and weight reduction of a product due to the increase of volume, {circle over (3)} complexity of the countermeasure part, and {circle over (4)} restriction to external view design.
[0011]FIG. 13 shows a sectional structure model of a four-layer circuit board using a bypass capacitor. The four-layer circuit board comprises a signal layer (S1), a power layer (V), a ground layer (G) and a signal layer (S2). In FIG. 13, a dielectric material layer is omitted. As externally connected circuit components, a device equivalent circuit comprising a series connection of an inductance Ld, a load resistor Rd and a switch SW and a power equivalent circuit comprising a series connection of a bypass capacitor having a capacitance of C0, a DC power supply EO and an inductance Lg are included. In the circuit board, a stray capacity C1 by the power layer (V) and the ground layer (G) and inductances L0 and L1 by a wiring pattern and throughholes are formed.
[0013]FIG. 14 shows an equivalent circuit of the sectional structure model shown in FIG. 13.
Since the potential fluctuation VO occurs in a power lead of an IC device at the switching of the IC device (modeled by ON/OFF of SW in FIG. 14), the bypass capacitor is provided to absorb the potential fluctuation V0.
As other countermeasure means, plating may be applied to a plastic housing to form a shield structure to suppress the spurious radiation as seen in a modern notebook type personal computer, but the shield structure has demerits of {circle over (1)} increase of cost and {circle over (2)} the reduction of added value of the product by a problem to recycling the plastic housing.
Alternatively, a structure is provided with a first conductor layer, a second conductor layer, a dielectric material layer provided between said first conductor layer and said second conductor layer, and a resistor layer Specifically, the structure is provided with a first conductor layer, a second conductor layer, a third conductor layer, a first dielectric material layer, a second dielectric material layer and a resistor layer, and characterized in that said second conductor layer sandwiched by said first dielectric material layer and said second dielectric material layer and said resistor layer are arranged between said first conductor layer and said third conductor layer; and a capacitor C formed by a series connection, through said second conductor layer, of a capacitor C1 formed by arranging said first dielectric material layer between said first conductor layer and said second conductor layer and a capacitor C2 formed by arranging said second dielectric material layer between said second conductor layer and said third conductor layer, and a resistor R formed by arranging said resistor layer around said second conductor layer sandwiched by said first dielectric material layer and said second dielectric material layer form a parallel circuit.
In order to achieve the third object of the present invention, a method of manufacturing a circuit board is characterized by steps of forming a multi-layer circuit board having a circuit board comprising at least a ground layer and power layer or a multi-layer structure of said circuit board; and forming a resistor layer on a side of said circuit board or said multilayer circuit board, or at least a portion of an outer periphery of a wiring area in said ground layer and said power layer.
Alternatively, a circuit board is provided with a first conductor layer, a second conductor layer, a third conductor layer, a first dielectric material layer, a second dielectric material layer and a resistor layer, and characterized in that said second conductor layer and said resistor layer are sandwiched between said first dielectric material layer and said second dielectric material layer and arranged between said first conductor layer and said third conductor layer; a metallic layer is used as said conductor layer, an inorganic or organic material is used as said dielectric material layer and an inorganic material layer is used as said resistor layer in forming a low EMI circuit comprising a capacitor component and a resistor component on the circuit board between said first conductor layer and said third conductor layer and said layers are stacked on the circuit board to form a multilayer wiring structure; a wall shape structure made of conductors is formed in a self-closed line shape in an outer periphery of the dielectric material layer on the circuit board on in the dielectric material layer; and a plurality of conductor layers of different structures are electrically connected through the resistor layer.
For example, for the circuit board which is a center of noise sources, the differential mode radiation is created by a current flowing in a loop formed by the conductor pattern and the loop serves as a miniature antenna for generating a magnetic field. On the other hand, the common mode radiation is created by the potential fluctuation of the ground system, and when an external cable in connected, it serves as an antenna for generating an electrical field.
In the electronic apparatus of the present invention, the common mode radiation is suppressed at the level of the circuit board to suppress the spurious radiation from the electronic apparatus. Namely, the circuit board which suppresses the spurious radiation is constructed by “providing first and second ground layers having at least one thereof electrically connected to electrical parts, a power layer provided between said first ground layer and said second ground layer and electrically connected to said electronic parts, a dielectric material layer for joining said second ground layer and said power layer and a resistor layer having said first ground layer and said second ground layer electrically connected” or “a ground layer and a power layer electrically connected to electronic parts, a dielectric material layer for connecting said second ground layer and said power layer, and a first dielectric material layer and a second dielectric material layer sandwiching said ground layer and said power layer therebetween”, and said circuit board is housed in a housing to suppress the common mode radiation at the level of the circuit board to suppress the spurious radiation emitted from the electronic apparatus.
The present invention aims to suppress the spurious radiation at the level of the circuit board, and it eliminates various countermeasure parts such as a common mode choke, a filter and a bypass capacitor for an I/O unit and a power code which have been required in the prior art, and solves the problems of {circle over (1)} the increase of cost of the electronic apparatus, {circle over (2)} problems to so-called high packaging density such as minituarization, thinning and weight reduction of the product due to the increase of volume, {circle over (3)} the complexity of the countermeasure parts, and {circle over (4)} the restriction to the external design.
Further, since a design without the shield structure having plating applied to the plastic housing as seen in the modern notebook type personal computer is allowed, the shield structure is eliminated and {circle over (1)} the reduction of cost and {circle over (2)} the recycling of the plastic housing may be attained.
While the mechanism of the radiation source model for the common mode radiation is not fully investigated, the inventors of the present invention assumed that it is the potential fluctuation caused between the power layer and the ground layer and attempted to absorb the potential fluctuation by providing a resistor (resistive layer). The potential fluctuation depends on a drive frequency of the electronic parts mounted on the circuit board and the structure or the circuit board of the present invention is handled for two major modes, {circle over (1)} a lumped constant circuit and {circle over (2)} a distributed constant circuit although the basic constructions are substantially identical for both circuits.
In the structure or the circuit board of the present invention, in FIG. 14, in order to absorb the potential fluctuation V1 generated between the power layer (V(and the ground layer (G), a resistor Rc formed in the circuit board is connected to the capacitor C1 to form a parallel circuit (see FIG. 2) or a series circuit (see FIG. 12) of the capacitor C1 and the resistor Rc to reduce a Q value (attain Q value of not larger than 10).
Namely, when the structure or the circuit board of the present invention functions as the lamp constant circuit, the low Q-value is attained by providing the resistor to absorb the potential fluctuation.
In FIG. 13, in order to absorb a standing wave generated between the power layer (V) and the ground layers (G, G1), a further ground layer (G2) and the resistor (resistor layer) are used and a parallel plate line is formed by the two ground layers (G1, G2) arranged to sandwich the power layer (V), and a matching termination resistance RO is given by the resistor (resistor layer) arranged at the line end.
In this case, since the two parallel plate lines formed by the power layer (V) and the ground layer (G1) and other ground layer (G2) have the line ends thereof opened, a large potential fluctuation occurs at the end in a particular frequency region. However, since it is arranged in the parallel plate line formed by the two ground layers (G1, G2), the standing wave due to the potential fluctuation is absorbed by the matching termination resistor R0.
R=(h/a)·{square root}{square root over ((μ0·μrl)/(ε0−εr1))}
h: gap length between G1-V
ε0: dielectric constant in vacuum (air)
erl: specific dielectric constant of dielectric material filled between G1-V
R>l/ΩC2
C2=ε0*εr2*S/d
w: angular frequency (area) required for low EMI
εr2: specific dielectric constant of dielectric material filled between G2-V
d: gap length between G2-V
Q÷*C1*R
Ω: angular frequency area required for low EMI
[0076]FIG. 1 shows a sectional view of a five-layer circuit board in accordance with an embodiment of the present invention.
[0077]FIG. 2 shows a sectional view of a structure in accordance with another embodiment of the present invention.
[0078]FIG. 3 shows a model chart of a sectional structure for the structure of FIG. 2.
[0079]FIG. 4 shows an equivalent circuit diagram of the five-layer circuit board of FIG. 1.
[0080]FIG. 5 shows an equivalent circuit diagram when FIG. 4 is given at a particular frequency area.
[0081]FIG. 6 shows a plan view of a structure for reducing an inductance L1 in accordance with other embodiment of the present invention.
[0082]FIG. 7 shows a sectional view of the structure in accordance with other embodiment of the present invention.
[0083]FIG. 8 shows a sectional view of a five-layer circuit board having a symmetric structure for a structure 51 in accordance with other embodiment of the present invention.
[0084]FIG. 9 shows an equivalent circuit diagram of the five-layer circuit board of FIG. 8 when through-hole connection is to be made.
[0085]FIG. 10 shows a sectional view of a five-layer circuit board having a resistor formed on a circuit board surface by a discrete component in accordance with other embodiment of the present invention.
[0086]FIG. 11 shows a sectional vies of a five-layer circuit board having a resistor layer formed on the circuit board surface in accordance with other embodiment of the present invention.
[0087]FIG. 12 shows a sectional view and a plan view of a structure of a series circuit in accordance with other embodiment of the present invention.
[0088]FIG. 13 shows a model chart of a sectional structure in a prior art four-layer circuit board.
[0089]FIG. 14 shows an equivalent circuit diagram of the four-layer circuit board shown in FIG. 13.
[0090]FIG. 15 shows a process chart of one example of a manufacturing method of a multi-layer circuit board for a low EMI circuit board of the present invention.
[0091]FIG. 16 shows a process chart of an example of the manufacturing method of the multi-layer circuit board for the low EMI circuit board of the present invention.
[0092]FIG. 17 shows a process chart of an example of the manufacturing method of the multi-layer circuit board for the low EMI circuit board of the present invention.
[0093]FIG. 18 shows a process chart of an example of the manufacturing method of the multilayer circuit board for the low EMI circuit board of the present invention.
[0094]FIG. 19 shows a process chart of an example of the manufacturing method of the multi-layer circuit board for the low EMI circuit board of the present invention.
[0095]FIG. 20 shows a process chart of a manufacturing method of the circuit board in accordance with the present invention.
[0096]FIG. 21 shows a sectional schematic view of a three-dimensional structure of the circuit board of the present invention.
[0097]FIG. 22 shows a sectional structure of the circuit board of the present invention which uses a plating method.
[0098]FIG. 23-(1) shows a sectional view of a circuit board which is an improvement over the structure of the circuit board of the present invention using the plating method.
[0099]FIG. 23-(2) shows a sectional view of an improvement of the structure shown in FIG. 23-(1).
[0100]FIG. 24-(1) shows a sectional view of a circuit board in accordance with a basic embodiment of the present invention which uses a dielectric material film side of a circuit board end, of the circuit board of the present invention.
[0101]FIG. 24-(2) shows a sectional view of a structure of a simplified circuit board of the structure of FIG. 24-(1).
[0102]FIG. 24-(3) shows a sectional vies of a structure of a simplified circuit board of the structure of FIG. 24-(2).
[0103]FIG. 25 shows a bird's eye view of a circuit board showing planar shape and arrangement of a wall-like structure, of the embodiment of the present invention.
[0104]FIG. 26 shows a sectional view of a structure when the present invention is applied to a semiconductor integrated circuit.
[0105]FIG. 27 shows a sectional view of a five-layer circuit board in accordance with an embodiment of the present invention.
[0106]FIG. 28 shows a sectional view of a five-layer circuit board in accordance with an embodiment of the present invention.
[0107]FIG. 29 shows a sectional view of a five-layer circuit board in accidence with an embodiment of the present invention.
[0108]FIG. 30 shows a sectional view of a five-layer circuit board in accidence with an embodiment of the present invention.
[0109]FIG. 31 shows a sectional view of a five-layer circuit board in accidence with an embodiment of the present invention.
[0110]FIG. 32 shows a sectional view of a five-layer circuit board in accidence with an embodiment of the present invention.
[0111]FIG. 33 shows an example of the electronic apparatus of the present invention.
[0112]FIG. 34 shows an embodiment of the present invention an shows a nine-layer circuit board (sectional structure by simple model) having two power layers V1, and two or more ground layers G1.
[0113]FIG. 35 show other embodiment of the present invention and shows a nine-layer circuit board (sectional structure by simple model) having two power layers V1 and three or more ground layers G1.
[0114]FIG. 36 shows other embodiment of the present invention and shows a nine-layer circuit board (sectional structure by simple model) having two power layers V1 and three ground layers G1 and one of the ground layers having sandwiched by the two power layers.
[0115]FIG. 37 shows other embodiment of the present invention and shows a multi-layer circuit board (sectional structure by simple model) having a plurality of power layers V1 and ground layers G1.
[0116]FIG. 38-(1) shows other embodiment of the present invention and shows a seven-layer circuit board (plan view of the power layer V) when the power layer V is divided into three patterns.
[0117]FIG. 38-(2) shows other embodiment of the present invention and shows a seven-layer circuit board in a section along a line A-A′ (sectional view along line A-A′) when the power layer V is divided into three patterns.
[0118]FIG. 39 shows other embodiment of the present invention and shows a multi-layer circuit board (plan view) when the ground layer and the power layer are not rectangular.
[0119]FIG. 40 shows other embodiment of the present invention and shows a multi-layer circuit board (plan view) when a cut line is provided in one of the two ground layers G1 and G2 between which the power layer V is sandwiched.
[0120]FIG. 41 shows other embodiment of the present invention and shows a five-layer printed circuit board (plan vies and sectional view) when the matching termination and the low-Q are applied.
[0121]FIG. 42 shows a radiation characteristics (characteristic chart) of a prior art circuit board and a novel circuit board.
[0122]FIG. 43 shows a suppression effect (characteristic chart) of the novel circuit board over the prior art circuit board.
[0124]FIG. 33 shows an external view of an electronic apparatus (personal computer) using a low EMI circuit board in accordance with one embodiment of the present invention.
In the electronic apparatus 1 of the present invention, components comprising I/O connectors 4 (4-1, . . . , 4-5), a power code 5, a signal cable 6, a housing 7, an LCD display 8, a keyboard 9, a floppy disk drive 10, a hard disk drive 11, a battery pack 12 and an IC card 13 are electrically and physically connected around a low EMI circuit board 3 on which a high speed CPU 2 is mounted. The low EMI circuit board 3 comprises “first and second ground layers having at least one thereof electrically connected to electrical parts, a power layer provided between said first ground layer and said second ground layer and electrically connected to said electronic parts, a dielectric material layer for joining said second ground layer and said power layer and a resistor layer having said first ground layer and said second ground layer electrically connected” or “a ground layer and a power layer electrically connected to electronic parts, a dielectric material layer for connecting said second ground layer and said power layer, and a first dielectric material layer and a second dielectric material layer sandwiching said ground layer and said power layer therebetween”. The structures thereof will be described later.
In general, as the operating frequency of the electronic apparatus rises (around 50 MHz-1000 MHz) and the spurious radiation (intensity) from the circuit board increases, the suppression of the potential fluctuation generated in the signal ground (SG) is difficult, and as countermeasure therefor, the housing shield for surrounding the entire circuit board which is the noise source may be used. In the present electronic apparatus 1, since the spurious radiation is suppressed at the level of the circuit board, the spurious radiation may be suppressed and eliminated without regard to the increase of the operating frequency in principle, and the method of applying conductive plating to the plastic housing or attaching the thin metal plate is basically not necessary. By applying the structure of the present electronic apparatus 1 to a prior art electronic apparatus in which the spurious radiation is suppressed by applying the conductive plating to the housing, it is not necessary to provide the shield in the housing and a product which realizes the enhancement of the recycling of the housing material, the reduction of weight and the reduction of the number of assembling steps is provided.
The structure comprises “first and second ground layers having at least one thereof electrically connected to electrical parts, a power layer provided between said first ground layer and said second ground layer and electrically connected to said electronic parts, a dielectric material layer for joining said second ground layer and said power layer and a resistor layer having said first ground layer and said second ground layer electrically connected” as shown in FIG. 2 and FIG. 7 and “a ground layer and a power layer electrically connected to electronic parts, a dielectric material layer for connecting said second ground layer and said power layer, and a first dielectric material layer and a second dielectric material layer sandwiching said ground layer and said power layer therebetween” as shown in FIG. 12.
Similarly, in the structure 35 of FIG. 7, the capacitor C1 is formed by the power layer (V) 36 and the ground layer (G1) 37 with the intervention of the dielectric material layer 38 therebetween, the capacitor C2 is formed by the power layer (Y) 36 and the ground layer (G2) 39 with the intervention of the dielectric material layer 40 therebetween, and the resistor Rc is formed by the ground layer (G1) 37 and the ground layer (G2) 39 with the intervention of the resistor layers 41 (41-1, 41-2) therebetween. The levels of one side 42 of the power layer (V) 36 and the connecting sides 43 (431, 43-2) of the ground layer (G2) 39 connected to the resistor layers 43 (43-1, 43-2) are aligned and the resistor layer 41 is arranged around the dielectric material layer 38.
Thus, the structure 35 is separated to a structure 44 comprising the ground layer (G1) 37, the dielectric material layer 38 and the resistor layers 41 (41-1, 41-2), and a structure 45 comprising the ground layer (G2) 39, the dielectric material layer 40 and the power layer (V) 36 so that the formation of the layers is simplified. Further, the parallel plate line structure for connecting the matching termination resistor RO is equivalently given by a simple structure comprising the ground layer (G1) 37, the dielectric material layer 38 and the power layer (V) 36.
[0145]FIG. 12(b) shows a sectional structure of the structure 73 having the resistor layer 70 of FIG. 12(a) formed at a center of the inside of the dielectric material layer 70.
[0150]FIG. 1 shows a sectional structure of a five-layer circuit board to which the structure of FIG. 2 is applied.
The external components such as the IC parts 7 and the bypass capacitor 8 are mounted on the signal layer (S1) 1. The power lead 9 and the ground lead 10 of the IC parts 7 are formed on the signal layer (S1) 1 by the solid etching and they are connected to the power layer (V) 2 and the ground layer (G1) 3, respectively, through the conductor patterns 11-1 and 11-2 formed for the electrical and mechanical connection and the through-holes 12-1 and 12-2 formed between layers, The bypass capacitor 8 is connected in the same manner and it may be mounted on the signal layer (S2) 4.
[0159]FIG. 3 shows modeling of a sectional structure of the structure 13 shown in FIG. 2 into an equivalent circuit of resistors.
The potential fluctuation V1 20 generated in the capacitor C1 19 is divided into a voltage V 221 of the capacitor C 2 and a voltage Vr 22 of a parallel circuit of the resistor Rc 16 and the capacitor Cc 17.
[0161]FIG. 4 shows an equivalent circuit of the five-layer circuit board of FIG. 1 having the structure 13 built therein.
The five-layer circuit board comprises components of a capacitor C1 19, a device equivalent circuit 23 comprising a series connection of an inductance Ld, a load resistor Rd and a switch SW as the IC parts 7, an inductance L1 24 formed by a conductor pattern 11-1 formed on the signal layer (S1) 1 and a through-hole 12-1 partially connecting the conductor pattern 11-1 and the power layer (V) 2, a bypass capacitor equivalent circuit 25 comprising a series connection of a capacitor C0 and an inductance LO having the bypass capacitor 8 connected to the conductor patterns 11-1 and 11-3 formed on the signal layer (S1) 1 and having the conductor pattern 11-3 connected to the ground layer (G1) 3 through the through-hole 12-3, and an impedance Zg 26 (not shown in FIG. 1) by the power layer for supplying a DC voltage EO (not shown in FIG. 4 because it is an AC circuit) to the power layer (V) 2 and the ground layer (G1) 3.
[0164]FIG. 5 shows an equivalent circuit when FIG. 4 is given at a specific frequency region (radiation suppression region).
When the resistor Rc 16 is selected to be sufficiently smaller than the impedance Zcc of the capacitor Cc 17 and sufficiently larger than the impedance Zc2 of the capacitor C2 18, an equivalent circuit 27 of the structure 13 viewed from the power layer (V) 2 and the ground layer (Gi) 3 may be regarded as the parallel circuit of the capacitor C1 19 and the resistor Rc 16. At this time, since a voltage V2 21 generated across the capacitor C2 18 may be regarded as zero, the ground layer (G2) 5 and the power layer (V) 2 match.
Ω1=1/(C2·Rc) (3)
Ω2=1/(Cc·Rc) (4)
Q=ΩC1Rc (5)
[0174]FIG. 5 has three closed loops, a loop 1 28 comprising the device equivalent circuit 23 and the bypass capacitor equivalent circuit 25, a loop 2 29 comprising the bypass capacitor equivalent circuit 25, the inductance L1 24 and the parallel circuit 27, and a loop 3 30 comprising the parallel circuit 27 and the impedance Zg 26. The resonance of the loop 2 and the loop 3 which generate the potential fluctuation V1 as the drive voltage source may be suppressed by setting the Q value of the parallel circuit 27 to a small value.
Further, the potential fluctuation V1 20 is given by the division of the potential fluctuation VO 31 generated across the bypass capacitor equivalent circuit 25 at the switching of the device equivalent circuit 23 by the impedance ratio of the parallel circuit 27 and the inductance L1 24.
The parallel plate line structure (A) is formed by two solid layers of the ground layer (G1) 3 and the ground layer (G2) 5 and the matching termination resistor RO is given by the resistor layer 6 arranged at the line end. The parallel plate line structure (A) is of rectangular shape having a major side length of a0 and a minor side length of b0 and has two lines, a minor side line and a major side line, and the matching termination resistors R0 comprising R01 and R02 is represented as follows:
R0=(dc/a0)·{square root}{square root over ((μ0−μr)/(ε0−εr))} (6)
R02=(a0/b0)·R01 (7)
dc: gap length between ground layer (G1) 3 and ground layer (G2) 5
μr: specific dielectric constant determined by structure and material of the structure 13
εr: specific permeability determined by structure and material of the structure 13
Two further parallel plate line structures (B) and (C) are formed by the ground layer (G1) 3 and the power layer (V) 2 arranged in the ground layer (G2) 5. In this case, since an open end (capacitor termination) is provided, a standing wave due to the potential fluctuation V1 20 or the potential fluctuation VO 31 is generated and the frequency thereof is determined by the structure and the material of the line. Since the two parallel plate line structures (B) and (C) are formed in the parallel plate line structure (A), the generated standing wave is absorbed by the matching termination resistors R0 (R01 and R02).
[0189]FIG. 6 shows a plan structure for reducing the inductance L1 24 in accordance with one embodiment of the present invention.
In order to remove the lamp inductance Lc from the inductance L1, the surface area of the conductor pattern 11-1 formed on the signal layer (S1) 1 is increased and the multi-point through-hole structure 121 having a plurality of single-point through-holes 32-1, 32-2 and 32-3 is employed.
For the values of the surface area (11μ12) 33 and the through-hole pitch p 34, a ratio of the lamp inductance Lc to the inductance L1 is lowered and the impedance ratio of the inductance 11 24 to the parallel circuit 27 shown in FIG. 5 is lowered sufficiently (not larger than 0.1).
In FIG. 5, when the inductance L1 24 is removed by the above means, the parallel circuit 27 and the bypass capacitor equivalent circuit 25 are equivalently connected in parallel. The potential fluctuation VO 31 is equivalently applied directly to the parallel circuit 27 and it is equal to the potential fluctuation V1 20. The Q of the circuit of the parallel connection of the bypass capacitor equivalent circuit 25 and the parallel circuit 27 is lowered sufficiently so that the potential fluctuation VO 31 generated across the device equivalent circuit 23 may be effectively absorbed.
[0195]FIG. 8 shows a sectional structure of a five-layer circuit board to which the structure of the present invention is applied.
When the structure 51 is viewed from the ground layer (G1) 47, the power layer (V) 46, the ground layer (G2) 48 and the power layer (V) 46, the parallel circuit of the capacitor C1 and the resistor Rc, and the parallel circuit of the capacitor C2 and the resistor Rc are formed. When compared with the structure 13 shown in FIG. 1, the structure 51 has the parallel circuit of the capacitor C2 and the resistor Rc in addition to the parallel circuit of the capacitor C1 and the resistor Rc and it effectively forms two structures. Since each of the parallel circuits is of symmetric structure, they have basically the same characteristic and meet the formulas (2)˜(4) at the specific frequency region given by the formula (1).
[0201]FIG. 9 shows an equivalent circuit when the through-hole connection is taken into account in the five-layer circuit board of FIG. 8.
The Q of the parallel circuit 56 is given by:
Q=Rc/(Ω·Ls) (8)
=Ω·C1·Rc (9)
=Rc·{square root}{square root over ((C1/Ls))} (10)
By forming the structure 51 which meets the condition of the formulas (1)˜(4) and makes the Q value of the formulas (8)˜(10) not larger than 10, the potential fluctuation V1 57 generated between the ground layer (G1) 47 and the power layer (V) 46 is absorbed.
A plurality (N) of units with the structure 51 being a basic unit are stacked to form a unit group 58 (58-1, 58-2, . . . , 58-N {N≧2}), and the ground layer (G1) 59-(K-1), the ground layer (G2) 60-(K-1) and the power layer (V) 61-(K-1) of one unit 58-(K-1) {2≦K≦N} are partially connected to the ground layer (G1) 59-K, the ground layer (G2) 60-K and the power layer (V) 61-K, respectively of other unit through the through-hole and a plurality of parallel circuits are formed between the components of the respective units to from the multilayer circuit board 62. In this manner, the potential fluctuation between the ground layer (G1) 59, the ground layer (G2) 60 and the power layer (V) 61 of the unit group 58 is suppressed.
One or more signal layers are formed between the units as required. Further, one or more signal layers (including the dielectric material layer) may be sandwiched by the two adjacent ground layers (G2) 60-(K-1) and the ground layer (G1) 59-K and the resistor layer 63-(K-1) may be arranged in the peripheral ends of the ground layer (G2) 60-(K-1) and the ground layer (G1) 59-K to form the parallel plate line structure (D) comprising the ground layer (G2) 60-(K-1), the ground layer (G1) 59-K and the resistor layer 63-(K-1). In this case, the matching termination resistor R0 is given by the resistor layer 63-(K-1) arranged at the line end. The spurious radiation from the respective signal layers arranged between units is suppressed by the shield structure by the matching terminated parallel plate line structure (D) and the concurrently formed shield structure.
[0207]FIG. 10 shows another embodiment and shows a sectional view of a five-layer circuit board 65 having the resistor layer 50 of the structure 51 shown in FIG. 8 formed on the surface of the circuit board by a discrete part 64 (64-1, 64-2) such as a chip resistor. Namely, two ground layers are extended to the surface of the circuit board by the through-hole and the resistor layer is formed by using the discrete part 64. This offers an advantage that the setting of resistance is facilitated.
[0208]FIG. 11(a) shows other embodiment and shows a sectional view of a five-layer circuit board 67 having the resistor layer 66 formed on the surface of the circuit board instead of the discrete part 64 such as the chip resistor shown in FIG. 10.
[0209]FIG. 11(b) shows a sectional structure of the five-layer circuit board 67 of FIG. 11(a).
[0210]FIG. 34 show an embodiment of the present invention and shows a nine-layer structure 23 of a signal layer S1 14, a ground layer G1 15, a power layer V1 16, a signal layer S2 17, a ground layer G2 18, a signal layer S3 19, a power layer V2 20, a ground layer G3 21 and a signal layer S4 22.
In order to increase the interlayer stray capacity C2 formed by the power layer V1 16 and the ground layer G1 15 and the power layer V2 20 and the ground layer G3 21, a specific dielectric constant εr2 24 (24-1, 24-2) of t he interlayer material is set to be not smaller than 10 and the layer thickness is set to 80 μm.
On the other hand, for the power supply 28, the potential fluctuation of the power layer V2 20 is propagated to the ground layer G3 21, and the potential fluctuation (standing wave resonance) is absorbed by connecting the matching termination resistor Rc 25 (251, 25-2) to the line formed by the ground layer G1 15 and the ground layer G3 21. At the same time, the Q value of the interlayer stray capacitor C1 (the specific dielectric constant of the interlayer material εr1: 4.7) formed by the power layer V1 16 and the power layer V2 20 is reduced (to not larger than 10) to absorb the potential fluctuation (resonance) of the power layer V2 20 to the ground layer G1 15.
[0217]FIG. 35 shows other embodiment of the present invention and shows a nine-layer circuit board of a signal layer S1 30, a ground layer G1 31, a power layer V1 32, a signal layer S2 33, a ground layer G2 34, a signal layer S3 35, a power layer V2 36, a ground layer G3 37 and a signal layer S4 38. In order to increase the interlayer stray capacitance C2 formed by the power layer V1 32 and the ground layer G1 31, and the power layer V2 36 and the ground layer G3 37, the specific dielectric constant εr2 40 (40-1, 40-2) of the interlayer material is set to be not smaller than 10 and the layer thickness t is set to 80 um.
The signal layers Si may be further inserted except between the two interlayers of the ground layer G1 31 and the power layer V1 32, and the power layer V2 36 and the ground layer G3 37.
The matching termination resistor Rc1 41 (411, 41-2) and the matching termination resistor Rc2 42 (42-1, 42-2) are connected to the ends of the two parallel plate lines (two lines for the rectangular shape) formed by the ground layer G1 31 and the ground layer G2 34, and the ground layer G3 37 and the ground layer G2 34 to absorb the standing wave resonance generated by the potential fluctuation of the power layer V1 32 and the power layer V2 36. At the same time, the Q value of the interlayer stray capacitor C1 (the specific dielectric constant of the interlayer material εr1: 4.7) formed by the ground layer G2 34 and the power layer V1 32, and the ground layer G2 34 and the power layer V2 36 is reduced (to not larger than 10). Usually, the Q value may be set to approximately 1 (frequency=30 MHz˜1 GHz) even when the resistance Rci (i=1, 2) of the matching termination is adopted.
On the other hand, for the power supply 45, the potential fluctuation of the power layer is propagated to the ground layer G1 31 and the potential fluctuation (standing wave resonance) is absorbed by connecting the matching termination resistor Rc 41 (41-1, 41-2) to the line formed by the ground layer G1 and the ground layer G2 34. At the same time, the Q value of the interlayer stray capacitance C1 (the specific dielectric constant of the interlayer material εr1: 4.7) formed by the ground layer G2 34 and the power layer V1 32 is reduced (to not larger than 10).
[0224]FIG. 36 shows an embodiment of the present invention and shows a nine-layer circuit board 56 comprising a signal layer S1 47, a ground layer G1 48, a signal layer V2 52, a signal layer S3 53, a ground layer G3 54 and a signal layer S4 55. In order to increase the interlayer capacity C2 formed by the power layer V1 50 and the ground layer G2 51, and the power layer V2 52 and the ground layer G2 51, the specific dielectric constant of the interlayer material εr2 57 is set to be not smaller than 10 and the layer thickness t is set to 80 μm. The capacitance which offers the performance of the bypass capacitor (for example, approximately 0.01 μpF) may be provided and the bypass capacitor as a discrete part may be eliminated.
The matching termination resistors Rc1 58 (581, 58-2) and the matching termination resistor Rc2 59 (59-1, 59-2) are connected to the ends of the two parallel plate lines (two lines for the rectangular shape) formed by the ground layer G1 48 and the ground layer G2 51, and the ground layer G3 54 and the ground layer G2 51 to absorb the standing wave resonance generated by the potential fluctuation of the power layer V1 50 and the power layer V2 52. At the same time, the Q value of the interlayer stray capacity C1 (the specific dielectric constant of the interlayer material εr1: 4.7) formed by the ground layer G1 48 and the power layer V1 50, and the ground layer G3 54 and the power layer 54 is reduced. By setting the Q value to be not larger than 10, the resonance may be effectively suppressed and removed. Usually, the resistance Rci (I=1, 2) of the termination resistor which is determined by the structure and the material (εr, pr) of the line is adopted and the Q value is set to approximately 1 (frequency f=30 MHz˜1 GHz).
On the other hand, for the power supply 60, the potential fluctuation of the power layer V1 50 is propagated to the ground layer G2 51, and the potential fluctuation (standing wave resonance) is absorbed by connecting the matching termination resistor Rc1 58 (581, 58-2) to the line formed by the ground layer G2 51 and the ground layer G1 48. At the same time, the Q value of the interlayer capacitor C1 (the specific dielectric constant of the inter layer material εr1: 4.7) formed by the ground layer G1 48 and the power layer V1 50 is reduced (to not larger than 10).
[0231]FIG. 37 shows other embodiment of the present invention.
[0234]FIG. 38(1) shows an embodiment of the present invention, in which the power layer V88 for supplying various power voltages is divided into three insulated patterns Va 89, Vb 90 and Vc 91. As shown in FIG. 38(2), the power layer V 88 is sandwiched by the ground layer G1 94 and the ground layer G2 95 together with the signal layer S2 92 and the signal layer S3 93, and the dielectric material layer 96 having the specific dielectric constant of εr2: 10 or higher and the thickness of 80 μm is used between the ground layer G2 95 and the power layer V 88.
Further, the dielectric material layer 97 having the specific dielectric constant of εr1: 4.7 is used between the power layer V 88 and the ground layer G1 94 and a high speed wiring is formed in the signal layer S2 92 and the signal layer S3 93. A return current path of the signal line arranged in the signal layer S3 93 adjacent to the power layer V 88 is formed in the power layer V 88, that is, in the two insulated power patterns Vb 90 and Vc 91 as shown in FIG. 38(1). The disturbance of the return current of the signal line (not shown) and the impedance occurs at the insulated portion 98 between patterns, which cause the distortion of the signal waveform and the increase of the spurious radiation. In the embodiment shown in FIG. 38(2), the ground layer G2 95 is arranged closely to the power layer V 88 with the spacing of 80 μm and the dielectric material layer 96 having the specific dielectric constant of Er2: 10 or higher is used to suppress and remove the distortion of the return current path and the impedance.
[0237]FIG. 39 shows an embodiment of the present invention and shows an arrangement structure of the discrete resistor (chip resistor) connected at the end of the line formed by the two ground layers G1 and G2 in which the power layer V is sandwiched.
For the latter, the resonance occurs between the interlayer stray capacitor formed between the power layer and the ground layer and the inductance of the bypass capacitor at the frequency range (10 MHz˜1 GHz) in which the bypass capacitor normally behaves as the inductance. In this case, the inductance component equivalently formed the drive IC and the power filter connected between the power layer and the ground layer and mounted on the circuit board may be neglected with respect to the inductance component of the bypass capacitor. The resonance in this case is the parallel resonance, and since the inductance component is reduced as the number of bypass capacitors increases, the resonance frequency usually tends to increase although it depends on the packaging condition on the circuit board.
As the inductance connected between the power layer and the ground layer is reduced in this manner, the inductance component which is serially connected to the chip resistors by the connection structure of the resistor required for the low Q value cannot be neglected. When the inductance component of the bypass capacitor which is parallelly connected to the interlayer stray capacitor is smaller than the inductance component caused at the connection of the chip resistors, the low Q value of the interlayer stray capacitor is prevented. Namely, it is difficult to attain the low Q value on the circuit for the inductance component of the bypass capacitor in place of the interlayer stray capacitor. In phenomenon, since the electromagnetic energy stored in the interlayer stray capacitor flows to the inductance component of the low impedance bypass capacitor, the conversion to the Joule's heat by the chip resistor is not attained. Accordingly, in this case, in order to meet the low Q value condition, the inductance component of the bypass capacitor is set to be larger than the inductance component.
[0248]FIG. 40 shows an embodiment of the present invention in which a cut line 107 is formed in the ground layer G1 106 which is loosely capacitively coupled to the power layer V and the impedances of the ground area 110 and the ground area 109, and the ground area 109 and the ground area 110 are set to be high. The structure which prevents the propagation of the potential fluctuations of the respective ground areas to each other is formed to secure the noise margin in the signal circuit. On the other hand, for the ground layer G2 which is closely capacitively coupled to the power layer V, the cut line is usually not formed because the potential fluctuation is propagated even if the cut line is formed. When the power layer V is divided, a good characteristic is exhibited in the formation of the return current path of the high speed signal line.
[0250]FIG. 41 shows an embodiment of the present invention and shows a five-layer printed circuit board (new circuit board) 117 having a board dimension of 290 mm×230 mm×1.6 mm.
The layer structure of the new circuit board 117 is of five-layer of a signal layer S1 120, a ground layer G1 121, a power layer V 122, a ground layer G2 123 and a signal layer S2 124. The matching termination and the low Q value are secured by using the dielectric material layer 125 having the specific dielectric constant of εr: 10 and the layer thickness of 80 μm between the power layer V 122 and the ground layer G2 123. For the electrodes 126 (126-1, 126-2) and 127 (127-1, 127-2) formed on the surface signal layer S1 120, the through-holes 128 (128-1, 128-2) and 129 (1291, 129-2) pulled out of the ground layer G2 123 and the ground layer G1 121, respectively, are connected. The shape and the arrangement of the electrode 126 and the electrode 127 are double frame shape along the outer periphery of the circuit board. A plurality of chip parts 130 (130-1, 130-2, ) which are discrete parts are connected between electrodes. In order to form the matching termination resistor, approximately ten chip resistors of approximately 10 are connected to the major side and the minor side. The Q value is not larger than 10 for the frequency region of 30 MHz˜1 GHz and the low Q value is also attained. The through-holes are formed at multiple points at a high density to prevent the affect of the inductance component to the matching termination and the low Q value.
[0256]FIG. 42 shows radiation characteristics of the new circuit board (five-layer printed circuit board) 117 shown in FIG. 41 and the prior art circuit board. While the prior art circuit board is not shown, it is a four-layer printed circuit board which may be compared with the new circuit board 117 under the same condition including the drive condition. The radiation characteristic shows a maximum radiation electric field strength (dBμV/m) for the frequency at a point spaced from the radiation source by 3 m. The characteristic 130 of the new circuit board indicates that the increase of the amount of radiation is not observed near a singular frequency (100, 270 and 310, 510 and 620) to compare with the characteristic 131 of the prior art circuit board, and the amount of radiation is lowered as a whole. The increase of the amount of radiation as seen in the characteristic 131 of the prior art circuit board is due to the resonance, and in the characteristic 130 of the new circuit board, it is eliminated by building the condition of the matching termination and the low Q value into the circuit board.
[0257]FIG. 43 shows a suppression effect in the radiation characteristic of the new substrate with respect to FIG. 42, and shows a difference 132 between the characteristic 130 of the new circuit board and the characteristic 131 of the prior art circuit board. The effect is approximately 5˜25 dB and it indicates that the electric field strength may be suppressed by approximately one order. The characteristic 133 shown by circles shows the effect by the low Q value, and the resonance (standing wave resonance: λ/2, λ, 3λ/2) by the distributed constant circuit is suppressed and removed.
[0260]FIG. 15 to FIG. 19 shows examples in which the above structure is applied to the printed circuit board. When such a printed circuit board is mounted on an electronic apparatus, the low EMI is attained.
[0261]FIG. 15 shows an example in which a resistor layer is provided in the printed circuit board. The structure (f) may be regarded as the structure of FIG. 1 having the mounted parts and the outermost solder resist layer removed therefrom. A manufacturing process thereof is briefly explained below.
The copper foils on both sides are patterned 111 (for ground layer) by using resist while maintaining the conduction with the resistor 109, roughened by the blackening and reduction process to prepare a wiring board 112 as shown in (c). Then, as shown in (c), prepregs 113 and copper foils 114 are stacked on both sides of the circuit board 112 and bonded to prepare a lamination 115 as shown in (d). V1 a-holes 116 and non-via-holes 117 for the connection of layers are formed therein, the layers are connected by panel copper plating, and the outermost layer is patterned 118 by etching to from a signal layer to prepare a five-layer wiring board as shown in (f).
When the resistance of the resistor is set to a predetermined value, the amount of the polymer resistor paste 103 may be changed, and by adjusting the amount of the polymer resistor paste 103 by determining the size ‘width and depth) of the holes 102, a desired resistance may be attained.
[0268]FIG. 16 shows an example in which the resistor layer is provided on the side of the printed circuit board. The structure (f) may be regarded as the structure of FIG. 1 having the mounted parts and the solder resist layer of the outermost layer removed therefrom as it is in FIG. 15. A manufacturing process thereof is briefly explained below.
Thereafter, by the same process (d)˜(e) as the process of FIGS. 15(e)˜(f), a six-layer wiring board comprising two power layers 210 connected by via plated through-holes 208 and non-via plated through holes 209, two ground layers 211, two signal layers 212 and a resistor 206 connected to the ground layers.
[0275]FIG. 17 shows an example in which the structure of the present invention is applied to a build-up system which uses a photosensitive insulation material to the printed circuit board. The printed circuit board which applies the build-up system attains high density packaging. As shown in (a), one side is patterned by etching, and the double-sided copper foil lamination 301 having the copper foils roughened and the prepreg 302 and the copper foil 303 are stacked in the same manner as the manufacturing method 1 and bonded to prepare the lamination 304 comprising three layers of conductors. The both sides of the lamination 304 are protected by the resist and a resistor 305 as shown in (c) is formed on the side by electrolyte nickel-iron alloy plating film, and the same process (c)˜(e) as the process of FIG. 16(c)˜(e) is applied, the via holes 306 and non-via-holes 307 for connecting the layers are formed as shown in (d), the layers are connected by via plated through-holes 308 and non-via plated through-holes 309 as shown in(e) and the outermost layer is patterned 310 to prepare the wiring circuit board 311.
Then, the inside of the via plated through-hole 308 s, the inside of the non-via plated through-holes 309 and the space between the patterning wiring layers 310 of the circuit board 311 having the plated surfaces roughened by the blackening and reduction process are filled by the insulation material in the following manner. First, the circuit board 311 sandwiched between two thermo-setting resin films (either homogeneous or heterogeneous) including uncured inorganic filler is further sandwiched between two mold-processed metal plates having flat and smooth surfaces and they are mounted in a jig. Then, the inside of the jig is evacuated and the thermo-setting resin including the filler is heated and left below a melting point for several minutes, and a bonding pressure to vertically pinch the metal plates and a lateral compression pressure to the thermo-setting resin including the filler between the metal plates are applied by compressed air, and the thermo-setting resin including the filler is heated in this state to cure it. The cured resin on the surface of the circuit board 311 having the holes thereof filled is removed by wet etching by chemical to prepare the wiring circuit board 313 having the filled holes 312 as shown in (f).
A via-hole wiring board 403 is formed by electro-plating in a groove of the patterned resist on a double-sided copper foil lamination 402 having the both sides electrically connected by via plated through-holes 401 as shown in (a), and then the copper foils are patterned 404 by etching to prepare the double-sided wiring circuit board 405 as shown in (b). The plated surface of the through-hole 410, the surface of the via-hole wiring layer 403 and the surface of the patterned wiring 404 are blackened and the same process (b)˜(c) as the process of FIGS. 17(e)˜(f) is applied to the circuit board 405, the inside of the via plated through-hole 401, the space between conductors of the via-hole wiring layer 403 and the space between conductors of the patterned wiring layer 404 are filled as shown in (c), the upper surface of the via-hole wiring layer 403 is exposed by flattening the circuit board and etching by alkaline oxidization liquid, and prepares the wiring circuit board 406 having the surface of the insulation layer roughened.
Then, as shown in (d), the underlying conductive film 407 is formed on the circuit board 406 by the electroless copper plated thin film, and horizontal conductors 408 and via-hole conductors 409 are formed thereon in sequence by electro-copper plating by using the patterned resist as shown in (e). The underlying conductive file which was not used in the formation of the conductors is removed by etching and the horizontal wiring layer 410 and the via-hole wiring layer 411 are formed, those wiring conductors are insulated in the same manner as the process (b)˜(c), and the circuit board is flattened and the upper surface of the via-hole wiring is exposed to prepare the wiring circuit board 412 as shown in (f).
Thereafter, as shown in (g), the polymer resistor 413 is formed on the side of the circuit board 412 by the same process (f)˜(g) as the process of FIGS. 16(b)˜(c), and the horizontal wiring board 414 is formed by using the underlying conductive film in the same manner as the process (d)˜(e) to prepare the six-layer wiring board comprising two power layers 404 connected by a buried hole 401, two ground layers 410, two signal layers 414 and a resistor 413 connected to the ground layers as shown in (h).
[0285]FIG. 19 shows an example of a five-layer wiring board (h) having the structure of FIG. 7 built therein. A manufacturing method thereof is now briefly explained below.
The same process (a)˜(b) as the process of FIGS. 18(a)˜(b) is applied to one side of the doublesided copper foil lamination which serves as a base circuit board as shown in (a) to form the roughened horizontal wiring layer 502 and the via-hole wiring layer 503 electrically connected thereto as shown in (b). These wiring conductors are insulated in the same process (b)˜(c) as the process of FIGS. 17(e)˜(f),the circuit board is flattened, the via-hole wiring layer 503 is exposed and the surface of the insulation layer is roughened to prepare the lamination 504 as shown in (c).
Then, the underlying conductive film 505 is formed on the lamination 504 in the same manner as the process of FIGS. 18(c)˜(d) and the horizontal copper conductor 506 is formed thereon as shown in (d) by electro-plating by using the patterned resist, and the surface thereof is roughened by the buff polishing by the #240 buff. Then, the frame-shape nickel-iron alloy 508 is formed on the peripheries of the via-hole copper conductor 507 and the via-hole conductor 507 on the conductor 506. The underlying conductive film not used in the formation of those conductors are removed by etching to form the horizontal wiring layer 509, the via-hole wiring layer 510 and the resistor 511, and those wiring layers are insulated in the same manner as the process (b)˜(c), the circuit board is flattened, the upper surfaces of the via-hole wiring layer 510 and the resistor 511 are exposed and the insulation layer surface is roughened to prepare the lamination 512 as shown in (e).
Further, for the lamination 512, the nickel-iron alloy plating is not conducted and the process (c)˜(e) is repeated to additionally form the horizontal wiring layer 513 electrically connected to the via-hole wiring layer 510 and the via-hole wiring layer 514, they are insulated, the circuit board is flattened and the upper surface of the via-hole wiring layer 514 is exposed to prepare the lamination as shown in (f).
[0293]FIG. 20 shows an example in which the resistor layer of the present invention is formed simultaneously with the formation of the wiring in the process of manufacturing the wiring circuit board.
As shown in FIG. 20-(1), a metallic layer comprising three layers of Cr 603 a/Cu 604 a/Cr 605 a in the order from the lower layer to the upper layer is formed by sputtering or vapor deposition as the conductor layer for the ground layer on the circuit board 602 having the wiring 601 formed thereon like a printed circuit board or a thick film substrate. Of those, the Cu film 604 a serves as the wiring and the Cr films 603 a and 605 a are formed to prevent the deterioration primarily due to the oxidization of the Cu film and enhance the bonding of the upper and lower layers. After the photo-resist pattern is formed thereon, the above three metallic layers are sequentially etched. The etchant used for the etching is potassium ferri-cyanide or permangannic acid liquid for Cr, and nitric acid liquid for Cu to attain precise etching. By this work, the predetermined power layer pattern and the pad pattern of the through-hole are obtained. Thereafter, the Si3N4 film 606 as a high dielectric material film is formed on the entire surface of the circuit board to the thickness of approximately 2 μm by the CVD method or the sputter method. In this case. The CVD method provides less defect of the Si3N4 film and it is advantageous in forming the multi-layer wiring. The Si3N4 film has the specific dielectric constant of approximately 7 to 10 which is relatively large. The photo-resist pattern is formed to form the through-hole 607 a and the self-closed line groove 608 a along the periphery of the circuit board at predetermined position on the Si3N4 film 606, and then the Si3N4 film 606 is etched. Since the Si3N4 film may be readily etched by fluorine etchant, the structure as shown in FIG. 20-(3) may be readily formed. Further, the three-layer metallic layers 603 b, 604 b and 605 b are sequentially formed on the Si3N4 film 606 in the same manner as that described above, and the metallic film is photo-etched to form the band shape pattern covering the self-closed line groove 608 a of the Si3N4 film and the power layer. Thus, the band pattern 609 a of the self-closed line metal of 10 μm to 10 mm is formed as shown in FIG. 20-(4) simultaneously with the power layer. Since the band pattern 609 a is formed simultaneously by the same martial and process as those of the power layer, the number of steps does not increase. Further, since those metallic layers 603 a, 604 a, 605 a, 603 b, 604 b and 605 b may cover the unevenness of the underlying layer by thicker layer, the integrity of the layer is enhanced, and the thickness of not smaller than 1 μm is preferable, and the thickness of 3 μm or larger does not cause the problem in the integrity. Since such a degree of thickness is frequently used in the wiring, no problem is raised by forming the wiring and the band pattern in the same film forming process. The Hitachi Chemical polyimide pre-drive varnish (trade name PIQ) is applied thereon and it is baked in N2 at 350° C. to form the polyimide dielectric material layer 610 a having the thickness of approximately 6 μm on the wiring. The polyimide film has the specific dielectric constant of 3 to 4 which is approximately one half of that of the Si3N4 film. By the difference between the dielectric constants of the two dielectric materials and the adjustment of the thickness, the ratio of {fraction (1/20)} of the electric capacitance caused by the power layer wiring on the Si3N4 film 606 to the ground layer on the lower polyimide layer to the electric capacitance caused by the power layer wiring on the Si3N4 film 606 to the ground layer on the upper polyimide layer to be formed thereafter may be readily attained. Thereafter, as shown in FIG. 20-(5), the through-hole 607 b for the electrical connection to the predetermined positions is formed by the photo-etching, and at the same time, the polyimide is etched into the groove 608 b. The three-layer metallic layers 603 c, 604 c and 605 c are sequentially formed on the polyimide layer 610 a in the same manner as that described above and the metallic films are photo-etched in the band shape to cover the signal wiring layer and the loop groove 608 b of the polyimide film. In this manner, the self-closed line metallic band pattern 609 b having the width of 10 μm to 10 mm is formed as shown in FIG. 20-(6). The polyimide pre-drive varnish is applied thereon and baked in the same manner as that described above and the polyimide dielectric material layer 610 b having the thickness of approximately 6 μm or larger is formed on the wiring, the through-holes and the groove 608 c are formed to form the structure as shown in FIG. 20-(7). Further, the Cr—SiO2 611 which is the high specific resistance thin film is formed on the polyimide layer 610 b by the sputtering to the predetermined film thickness, and then the three-layer metallic layer of Cr 603 d/Cu 604 d/Cr 605 d is formed in the same manner as that described above. Since this composite layer functions as the ground layer, the pad pattern of the through-hole is formed and the metallic layers 603 d, 604 d and 605 d of the portion corresponding to the inside of the portion of the polyimide etched into groove as shown in FIG. 20-(8) are removed by the predetermined width in the self-closed line loop pattern, and the high specific resistance thin film is exposed. Since this portion serves as the high resistance region 612 to consume the spurious current, the width of the exposed area of the high specific resistance thin film is determined by taking the sheet resistance of the Cr—SiO2 film into consideration such that the predetermined resistance is attained. Further, undesired area of Cr—SiO2 which is the high specific resistance thin film may be readily etched by fluorine etchan. In the above case, the high resistance region 612 is formed in the upper ground layer although it may be formed in the lower ground layer formed on the surface of the circuit board. When the high resistance thin film is formed to form the resistor element in the signal wiring layer, the high resistance region may be formed as a discrete ring pattern in the outer periphery of the signal wiring layer and a plurality of ground layers may be connected through this pattern to attain the same effect. In this case, since it is formed simultaneously with the formation of the resistor element in the wiring, the number of steps does not increase.
[0297]FIG. 21 shows a bird's eye view of a portion of the wiring circuit board thus formed. It is seen from FIG. 21 that the band pattern formed in the groove is stacked up.
While the example of the wiring using Cu as a basic component has been described in the above example, any one of Al, Al—Si, Al—Si—Cu, Ni, W and Mo or a multi-metal wiring having those metallic layers and other material stacked may be used to attain the similar structure.
Further, as shown in FIG. 24-(3), the metallic pattern 616 for soldering on the uppermost layer is also formed to cover the all exposed areas of the metallic band patterns as it is for the metallic pattern 616. Thereafter, the soldering is conducted and the solder 620 flows to the side of the wiring layer and solidified so that the solder walls are formed on the metallic layer in superposition and the sealing to the electromagnetic wave of the wiring circuit board may be more positively maintained.
As the low dielectric constant dielectric material layer, ceramic component comprising 56 wt % of borosilicate glass including 79 wt % of silicon oxide (SiO2), 18 wt % of boron oxide (B2O3), 2 wt % of potassium oxide (KO) and 1 wt % of aluminum oxide (Al2O3), and 24 wt % of aluminum oxide (Al2O3) powder as filler, and 20 wt % of cordielite (2MgO.2Al2O3.5SiO2) powder was used, and the composition, polyvinyl buthyral resin, solvent (buthanol) and plastic material were mixed by an alumina ball mill to produce slurry of glass and filler. From the slurry, low dielectric constant dielectric material green sheet was prepared by doctor blade type casting machine. For the above glass ceramic material, characteristics of sintered body of single body (pressed powder) were measured and the sintered temperature of 900° C., the sintering maintain time of 1 hr, the bending strength of 240 MPa, the thermal expansion coefficient of 3.1×10−6/° C., the specific dielectric constant of 5.0 and the dielectric loss (tan δ) of 0.3% were obtained.
Then, via-thorough-holes 712-1, 712-2 and 712-3 for the conductors and via-through-holes 706-1 and 706-2 for the resistors were formed by an NC punching machine at predetermined position on four low dielectric constant dielectric material green sheets for forming the dielectric material layers 801, 802, 803 and 804 of FIG. 27. The via-through-holes for the resistors were formed in the vicinity of the periphery of the circuit board. The conductor paste of Ag/Pd=95/5 was filled in the via-thorough-holes for the conductors and the resistor paste was filled in the via-through-holes for the resistors. Then, the internal conductor pattern were printed, that is, the ground layer 703 was printed on the green sheet for forming the dielectric material layer 801 and the power layer 702 was printed on the green sheet for forming the dielectric material layer 804 by using the conductor paste of Ag/Pd=95/5 and then those sheets were stacked and pressed and sintered by holding then at 900° C. under atmospheric pressure for one hour. Then, the surface conductor patterns 701, 704, 711-1, 711-2, 711-3 were printed on t he sintered circuit board surface by using the conductor paste of Ag/Pd=70/30 and they were sintered at 850° C. under atmospheric pressure for ten minutes to form the surface conductor patterns. Then, the parts were mounted to prepare the low EMI circuit board of FIG. 27. The dielectric material of the circuit board exhibited the specific dielectric constant of 5.0 and the dielectric loss (tan δ) of 0.4%.
[0318]FIG. 28 shows other embodiment.
The via-through-holes 712-1, 712-2, 712-3 and 712-10 for the conductors and the via-through hole 706-10 for the resistor were formed by the NC punching machine at predetermined positions on four low dielectric constant dielectric material green sheets for forming the dielectric material layers 801, 802, 803 and 804 of FIG. 28. Then, the conductor paste of Ag/Pd=95/5 was filed in the via-through holes for the conductors and the resistor paste was filled in the via-through-hole for the resistor. Subsequently, in the same manner as that of the Embodiment 1, the internal conductor patterns were printed, that is, the ground layer 703 was printed on the green sheet for forming the dielectric material layer 801 by using the conductor paste of Ag/Pd=95/5, power layer 702 was printed on the green sheet for forming dielectric material layer 802 and the ground layer 705 was printed on the green sheet for forming the dielectric material layer 804, and then those sheets were stacked and pressed and sintered by holding them at 900° C. under atmospheric pressure for one hour. Then, the surface conductor patterns 701, 704, 711-1, 711-2, 711-3 and 711-10 were printed on the sintered circuit board surface by using the conductor paste of Ag/Pd=70/30 and they were sintered by holding them at 850° C. under atmospheric pressure for ten minutes to form the surface conductor patterns. The internal via-through-holes for the resistor are connected to the internal ground layer 703 through the via-through-holes for the conductors and the resistance thereof was adjusted by cutting the surface conductor pattern 711-10 shown in FIG. 29. Then, the parts were mounted to prepare the low EMI circuit board of FIG. 28.
[0320]FIG. 30 shows other embodiment.
The via-through-holes 712-1, 712-2 and 712-3 for the conductors were formed by the NC punching machine at predetermined positions on four low dielectric constant dielectric material green sheets for forming the dielectric material layers 801, 802, 803 and 804 of FIG. 30. Then, the conductor paste of Ag/Pd=95/5 was filed in the via-through holes for the conductors. Subsequently, the internal conductor patterns were printed, that is, the ground layer 703 was printed on the green sheet for forming the dielectric material layer 801 by using the conductor paste of Ag/Pd=95/5, the power layer 702 was printed on the green sheet for forming dielectric material layer 802 and the ground layer 705 was printed on the green sheet for forming the dielectric material layer 804, and then those sheets were stacked and pressed and sintered by holding them at 900° C. under atmospheric pressure for one hour. Then, the surface conductor patterns 701, 704, 711-1, 711-2 and 711-3 were printed on the sintered circuit board surface by using the conductor paste of Ag/Pd=70/30 and the above resistor was applied to the ends of the circuit board by the dipping method and then they were sintered by holding them at 850° C. under atmospheric pressure for ten minutes to form the surface conductor patterns and the resistor 706-12. The resistances of the resistors at the ends of the circuit board ware adjusted by the laser trimming method. Then, the parts were mounted to prepare the low EMI circuit board of FIG. 30.
[0322]FIG. 31 shows other embodiment.
The via-through-holes 712-1, 712-2, 712-3, 712-10 and 712-11 for the conductors were formed by the NC punching machine at predetermined positions on four low dielectric constant dielectric material green sheets for forming the dielectric material layers 801, 802, 803 and 804 of FIG. 31. Then, the conductor paste of Ag/Pd=95/5 was filed in the via-through holes for the conductors. Subsequently, in the same manner as that of the Embodiment 1, the internal conductor patterns were printed, that is, the ground layer 703 was printed on the green sheet for forming the dielectric material layer 801 by using the conductor paste of Ag/Pd=95/5, power layer 702 was printed on the green sheet for forming dielectric material layer 802 and the ground layer 705 was printed on the green sheet for forming the dielectric material layer 804, and then those sheets were stacked and pressed and sintered by holding them at 900° C. under atmospheric pressure for one hour. Then, the surface conductor patterns 701, 704, 711-1, 711-2, 711-3 and 711-10 were printed on the sintered circuit board surface by using the conductor paste of Ag/Pd=70/30 and the resistor 706-13 was printed by the above resistor paste, and they were sintered by holding them at 850° C. under atmospheric pressure for ten minutes to form the surface conductor patterns and the surface resistors. The surface resistors are connected to the internal ground layers 703 and 705 through the conductor vias and the resistances thereof were adjusted by the laser trimming of the surface resistor patterns. Then, the parts were mounted to prepare the low EMI circuit board of FIG. 31.
[0324]FIG. 32 shows other embodiment.
The via-through-holes 712-1, 712-2, 712-3 and 712-10 for the conductors and the via-through hole 706-10 for the resistor were formed by the NC punching machine at predetermined positions on three low dielectric constant dielectric material green sheets for forming the dielectric material layers 801, 802 and 804 of FIG. 32. The via 706-10 for the resistor was formed in the vicinity of the periphery of the circuit substrate. Then, the conductor paste of Ag/Pd=95/5 was filed in the vias for the conductors and the resistor paste was filled in the via for the resistor. Subsequently, the internal conductor patterns were printed, that is, the ground layer 703 was printed on the green sheet for forming the dielectric material layer 801 by using the conductor paste of Ag/Pd=95/5, power layer 702 was printed on the green sheet for forming dielectric material layer 802 and the ground layer 705 was printed on the green sheet for forming the dielectric material layer 804. The first high dielectric constant dielectric material paste was further printed on the green sheet for forming the dielectric material layer 802 to form the dielectric material layer 805. The printing was made to the respective vias so that by using the pastes so that the vias for the conductors and the vias for the resistor are connected. Then, those sheets were stacked and pressed and sintered by holding them at 900° C. under atmospheric pressure for one hour. Then, the surface conductor patterns 701, 704, 711-1, 711-2, 711-3 and 711-10 were printed on the sintered circuit board surface by using the conductor paste of Ag/Pd=70/30 and they were sintered by holding them at 850° C. under atmospheric pressure for ten minutes to form the surface conductor patterns. The internal via-through-holes for the resistor are connected to the internal ground layer 703 through the surface conductor 711-10 and the vias for the conductors and the resistances thereof were adjusted by cutting the surface conductor pattern 711-10 shown in FIG. 29. Then, the parts were mounted to prepare the low EMI circuit board of FIG. 32 having the high dielectric material layer 805 formed between the power layer 702 and the ground layer 705. The first high dielectric constant dielectric material in the circuit board exhibited the specific dielectric constant of 500 and the dielectric loss (tan δ) of 2.5%.
[0327]FIG. 33 shows other embodiment.
As a second high dielectric constant dielectric material, PbO, Fe2O3, WO3 and TiO2 were used as raw materials, and the raw material oxide was mixed with 75 mol % of iron-lead tungstate (Pb(Fe2/3Wl/3)O3) and 25 mol % of lead titanate (PbTiO3) in solid solution ratio by a ball mill and the mixed powder was sintered at 800° C. for one hour. The resulting sintered powder of 75 mol % of iron-lead tungstate (Pb(Fe2/3Wl/3)O3) and 25 mol % of lead titanate (PbTiO3), polyvinyl buthyral resin, solvent (buthanol) and plastic agent are mixed by an alumina ball mill to produce slurry of ferrodielectric material including lead. Then, from the slurry, the second high dielectric constant dielectric material green sheet was prepared by a doctor blade type casting machine.
The vias 712-1, 712-2, 712-3 and 712-10 for the conductors and the via 706-10 for the resistor were formed by the NC punching machine at predetermined positions on three low dielectric constant dielectric material green sheets for forming the dielectric material layers 801, 802 and 804 of FIG. 32 and the second high dielectric constant dielectric material green sheet for forming the dielectric material layer 805. The via 706-10 for the resistor was formed in the vicinity of the periphery of the circuit substrate. Then, the conductor paste of Ag/Pd=95/5 was filed in the vias for the conductors and the resistor paste was filled in the via for the resistor. Subsequently, the internal conductor patterns were printed, that is, the ground layer 703 was printed on the green sheet for forming the dielectric material layer 801 by using the conductor paste of Ag/Pd=95/5, power layer 702 was printed on the green sheet for forming dielectric material layer 802 and the ground layer 705 was printed on the green sheet for forming the dielectric material layer 804. Then, those sheets were stacked and pressed and sintered by holding them at 900° C. under atmospheric pressure for one hour. Then, the surface conductor patterns 701, 704, 711-1, 711-2, 711-3 and 711-10 were printed on the sintered circuit board surface by using the conductor paste of Ag/Pd=70/30 and they were sintered by holding them at 850° C. under atmospheric pressure for ten minutes to form the surface conductor patterns. The internal via-through-holes for the resistor are connected to the internal ground layer 703 through the surface conductor 711-10 and the vias for the conductors and the resistances thereof were adjusted by cutting the surface conductor pattern 711-10 shown in FIG. 29. Then, the parts were mounted to prepare the low EMI circuit board of FIG. 32 having the high dielectric material layer 805 formed between the power layer 702 and the ground layer 705. The second high dielectric constant dielectric material in the circuit board exhibited the specific dielectric constant of 1000 and the dielectric loss (tans) of 13%. When the perovskite type ferro-dielectric material including lead was used as the high dielectric constant dielectric material, similar effect was attained.
Since the spurious radiation is suppressed at the level of the circuit board mounted in the electronic apparatus, the present invention can provide the electronic apparatus which eliminates the various countermeasure parts such as the common mode choke of the I/O unit and the power code, filter and the bypass capacitor and eliminates the demerits of {circle over (1)} the rise of cost, {circle over (2)} problems in so-called high packaging density such as miniaturization, thinning and weight reduction due to the increase of the volume {circle over (3)} complexity of the countermeasure parts and {circle over (4)} restriction of external design.
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U.S. Classification 361/793, 174/255, 361/794, 257/E23.114, 361/780
International Classification H05K9/00, H01L23/538, H01L25/16, H05K3/46, H05K1/16, H05K1/09, H01L23/552, H05K1/02, H05K3/40, H05K3/42, H05K1/11
Cooperative Classification H01L2924/00014, Y02P70/611, Y10T29/49155, H01L2924/01019, H05K2201/10446, H05K1/0234, H05K3/467, H05K1/115, H05K3/403, H05K2201/09354, H01L2924/01079, H01L2924/19106, H05K3/4614, H01L23/552, H05K1/113, H01L2924/01057, H05K2201/09518, H05K2201/09309, H05K2201/0209, H05K1/0227, H05K2201/10689, H01L2924/3011, H05K1/162, H01L2224/16, H05K2201/10022, H05K2201/09509, H05K1/167, H05K3/429, H05K3/4053, H01L2924/19105, H05K1/0231, H05K2201/09563, H05K9/0039, H01L2924/16152, H05K3/4652, H05K2201/093, H05K1/092, H01L2924/01078, H01L2924/09701, H05K2201/10636, H05K3/4611, H01L23/5383, H05K2201/10045, H05K2201/0979, H01L25/16, H01L2924/01046, H01L2924/3025, H05K2201/09663, H05K2201/0715, H05K1/0246
European Classification H05K1/02C2E6, H01L25/16, H01L23/538D, H05K9/00B4B, H05K1/02C4R, H01L23/552, H05K1/16R
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KANEMITSU, YUMI;REEL/FRAME:012359/0141