Source: https://patents.google.com/patent/EP0752611A2/en
Timestamp: 2019-09-16 17:32:35
Document Index: 24736929

Matched Legal Cases: ['art 1', 'art 1', 'ART 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art. 16']

EP0752611A2 - LCD with bus lines overlapped by pixel electrodes and photo-imageable insulating layer therebetween - Google Patents
LCD with bus lines overlapped by pixel electrodes and photo-imageable insulating layer therebetween Download PDF
EP0752611A2
EP0752611A2 EP96109003A EP96109003A EP0752611A2 EP 0752611 A2 EP0752611 A2 EP 0752611A2 EP 96109003 A EP96109003 A EP 96109003A EP 96109003 A EP96109003 A EP 96109003A EP 0752611 A2 EP0752611 A2 EP 0752611A2
EP96109003A
EP0752611A3 (en
EP0752611B1 (en
John Z.Z. Zhong
1995-06-06 Priority to US47027195A priority Critical
1995-06-06 Priority to US470271 priority
1996-06-05 Application filed by OIS Optical Imaging Systems Inc filed Critical OIS Optical Imaging Systems Inc
1996-06-05 Priority claimed from SI9630583T external-priority patent/SI0752611T1/en
1997-01-08 Publication of EP0752611A2 publication Critical patent/EP0752611A2/en
1997-11-26 Publication of EP0752611A3 publication Critical patent/EP0752611A3/en
2003-01-15 Publication of EP0752611B1 publication Critical patent/EP0752611B1/en
This invention is related to an active matrix liquid crystal display (AMLCD) having a high pixel aperture ratio. The display has an increased pixel aperture ratio because the pixel electrodes are formed over the insulating layer so as to overlap portions of the array address lines. Both the manufacturability and capacitive cross-talk of the TFT-based device are improved due to the use of a photo-imageable insulating layer between the pixel electrodes and the address lines. According to certain other embodiments, the insulating layer may be BCB (either photo-imageable or not) and/or have a dielectric constant less than about 3.0.
This invention relates to a liquid crystal display (LCD) having an increased pixel aperture ratio. More particularly, this invention relates to a liquid crystal display including an array of TFTs wherein an insulating layer having a plurality of contact vias or apertures disposed therein is located between the address lines and pixel electrodes so that the pixel electrodes are permitted to overlap the row and column address lines without exposing the system to capacitive cross-talk. In certain embodiments, the dielectric constant of the insulating layer is less than about 3.0 to reduce cross-talk. In certain embodiments, the layer is photo-imageable.
It is old and well-known to make TFT arrays for LCDs wherein address lines and overlapping pixel electrodes are insulated from one another by an insulating layer. For example, see U.S. Patent Nos. 5,055,899; 5,182,620; 5,414,547; 5,426,523; 5,446,562; 5,453,857; and 5,457,553.
U.S. Patent No. 5,182,620 discloses an AMLCD including pixel electrodes which at least partially overlay the address lines and additional capacitor lines thereby achieving a larger numerical aperture for the display. The pixel electrodes are insulated from the address lines which they overlap by an insulating layer formed of silicon oxide or silicon nitride.
Unfortunately, the method of making this display as well as the resulting structure are less than desirable because: (i) chemical vapor deposition (CVD) is required to deposit the silicon oxide or silicon nitride insulating film; and (ii) silicon oxide and silicon nitride are not photo-imageable (i.e. contact holes or vias must be formed in such insulating layers by way of etching). As a result of these two problems, the manufacturing process is both expensive and requires more steps than would be otherwise desirable. For example, in order to etch the contact holes in an insulating layer, an additional photo-resist coating step is required and the user must be concerned about layers underneath the insulating layer during etching. With respect to CVD, this is a deposition process requiring expensive equipment.
U.S. Patent No. 5,453,857 discloses an AMLCD having a TFT array with pixel electrodes formed in an overlapping relation with source signal lines through an insulating thin film. The insulating thin film formed between the signal lines and the pixel electrodes is made of either SiNx, SiO2, TaOx or Al2O3. Unfortunately, the method of making the array and resulting display of the '857 patent suffers from the same problems discussed above with respect to the '620 patent. None of the possible insulating layer materials are photo-imageable and etching is required.
U.S. Patent No. 5,055,899 discloses a TFT array including an insulating film disposed between the address lines and pixel electrodes. Again, etching is required to form the vias in the insulating film. This is undesirable.
U.S. Patent No. 5,426,523 discloses an LCD including overlapping pixel electrodes and source bus lines, with a silicon oxide insulating film disposed therebetween. Silicon oxide is not photo-imageable and thus necessitates a prolonged and more difficult manufacturing process for the TFT array and resulting AMLCD.
an array of TFTs disposed on the substrate, the TFTs connected to address lines and acting as switching elements for energizing corresponding pixel electrodes;
wherein the planarization layer includes BCB and has a dielectric constant of less than about 3.0.
This invention still further fulfills the above-described needs in the art by providing a method of making an array of semiconductor based TFTs, the method comprising the steps of:
forming an array of TFTs and corresponding address lines on the substrate;
depositing an organic photo-imageable insulating layer over both the TFT array and corresponding address lines;
photo-imaging the insulating layer in order to form a first array of contact holes therein; and
forming an array of electrode members on the first substrate over the photo-imaged insulating layers so that the electrode members in the array are in communication with the corresponding TFTs through the first array of contact holes.
Figure 1 is a top view of an AMLCD according to this invention, this figure illustrating pixel electrodes overlapping surrounding row and column address lines along their respective lengths throughout the display's pixel area so as to increase the pixel aperture ratio of the display.
Figure 2 is a top view of the column (or drain) address lines and corresponding drain electrodes of Figure 1, this figure also illustrating the TFT source electrodes disposed adjacent the drain electrodes so as to define the TFT channels.
Figure 3 is a top view of the pixel electrodes of Figure 1 except for their extensions.
Figure 4 is a side elevational cross-sectional view of the linear-shaped thin film transistors (TFTs) of Figures 1-2.
Figure 5 is a side elevational cross-sectional view of the liquid crystal display of Figure 1.
Figure 6 is a top or bottom view of the optional black matrix to be located on a substrate of the LCD of Figures 1-5, the black matrix to be located on the substrate not having the TFT array disposed thereon.
Figure 7 is a side cross-sectional view of a portion of the LCD of Figures 1-6, this figure illustrating the pixel electrodes overlapping the column address lines.
Figures 8-11 are side elevational cross-sectional views illustrating how a TFT in an array according to this invention is manufactured.
Figure 1 is a top view of four pixels in an array of an active matrix liquid crystal display (AMLCD) 2 according to an embodiment of this invention. This portion of the display includes pixel electrodes 3, drain address lines 5, gate address lines 7, an array of four thin film transistors (TFTs) 9, and auxiliary storage capacitors 11 associated with each pixel. Each storage capacitor 11 is defined on one side by a gate line 7 and on the other side by an independent storage capacitor electrode 12. Storage capacitor electrodes 12 are formed along with drain electrodes 13. As shown, the longitudinally extending edges of each pixel electrode 3 overlap drain lines 5 and gate lines 7 respectively along the edges thereof so as to increase the pixel aperture ratio (or pixel opening size) of the LCD.
In the areas of overlap 18 between pixel electrodes 3 and address or bus lines 5, 7, a pixel-line (PL) capacitor is defined by an electrode 3 on one side and the overlapped address line on the other. The dielectric disposed between the electrodes of these PL capacitors is insulation layer 33 (see Figures 4 and 7). The parasitic capacitance CPL of these capacitors is defined by the equation: C PL = ε · ε 0 · A d
where "d" is the thickness of layer 33, ε is the dielectric constant of layer 33, ε0 is the constant 8.85 x 10-14 F/cm (permitivity in vacuum), and "A" is the area of the PL capacitor in overlap areas 18. The fringing capacitance may also be taken into consideration in a known manner. See Chart 1 below for certain embodiments. Also, according to certain other embodiments, CPL is less than or equal to about 0.01 pF for a display with a pixel pitch of about 150 µm. When the pixel pitch is smaller, CPL should be scaled to a lower value as well because overlap areas 18 are smaller. Additionally, the pixel aperture ratio of an LCD decreases as the pixel pitch decreases as is known in the art. The pixel pitch of AMLCD 2 may be from about 40 to 5,000 µm according to certain embodiments of this invention. The pixel pitch as known in the art is the distance between centers of adjacent pixels in the array.
Figure 2 is a top view of drain address lines 5 of AMLCD 2 showing how extensions of address lines 5 form drain electrodes 13 of TFTs 9. Each TFT 9 in the array of AMLCD 2 includes source electrode 15, drain electrode 13, and gate electrode 17. Gate electrode 17 of each TFT 9 is formed by the corresponding gate address line 7 adjacent the TFT according to certain embodiments. According to other embodiments, the gate electrode 17 may be formed by a branch extending substantially perpendicular to the gate line.
Figure 3 is a top view illustrating pixel electrodes 3 (absent their extension portions 38) of AMLCD 2 arranged in array form. Figures 2 - 3 are provided so that Figure 1 may be more easily interpreted.
Figure 4 is a side elevational cross-sectional view of a single thin film transistor (TFT) 9 in the TFT array of AMLCD 2, with each TFT 9 in the array being substantially the same according to preferred embodiments. Each linear TFT 9 has a channel length "L" defined by the gap 27 between source electrode 15 and drain electrode 13. Source electrode 15 is connected to pixel electrode 3 by way of via or contact hole 35 so as to permit TFT 9 to act as a switching element and selectively energize a corresponding pixel in AMLCD 2 in order to provide image data to a viewer. An array of TFTs 9 is provided as illustrated in Figure 1 for AMLCD 2.
As shown in Figure 4, drain electrode 13 is made up of drain metal layer 29 (e.g. Mo) which is deposited on substrate 19 over top of doped contact layer 25. Contact film or layer 25 may be, for example, amorphous silicon doped with an impurity such as phosphorous (i.e. n+ a-Si) and is sandwiched between semiconductor layer 23 and drain metal layer 29. Source electrode 15 includes doped semiconductor contact layer 25 and source metal layer 31. Metal layers 29 and 31 may be of the same metal and deposited and patterned together according to certain embodiments of this invention. Alternatively, layer 29 may be deposited and patterned separately from layer 31 so that drain metal layer is of one metal (e.g. Mo) and source metal layer 31 is of another (e.g. Cr).
Substantially transparent insulating layer 33 having a dielectric constant less than about 5.0 is deposited as a sheet on substrate 19 so as to cover TFTs 9 and address lines 5 and 7. Layer 33 is formed of a photo-imageable material such as Fuji Clear™ or a photo-imageable type of BCB. Insulating layer 33 is continuous in the viewing area of the display except for vias or contact holes 35 and 36 formed therein to allow pixel electrodes 3 to contact corresponding TFT source electrodes and the storage capacitor electrodes respectively (i.e. each pixel includes two vias (35 and 36) in insulating layer 33 - one for the source electrode and the other for the storage capacitor).
Layer 33 has a dielectric constant ε less than or equal to about 5.0 according to certain embodiments of this invention. In certain preferred embodiments, layer 33 has a dielectric constant of about 2.7 and is made of a photo-imageable type of Benzocyclobutene (BCB), an organic material available from Dow Chemical, for the purpose of reducing capacitive cross-talk (or capacitive coupling) between pixel electrodes 3 and the address lines in overlap areas 18. Layer 33 has a low dielectric constant and/or a relatively large thickness for the specific purpose of reducing CPL in overlap areas 18. Note that the BCB may be of the non-photo-imageable type according to certain embodiments, this still reducing cross-talk.
Following the deposition of insulation layer 33 on substrate 19 over top of TFTs 9 and address lines 5 and 7, vias 35 and 36 are formed in insulation layer 33 by way of photo-imaging. Layer 33 acts as a negative resist so that UV exposed areas remain on the substrate and areas of layer 33 unexposed to UV during photo-imaging are removed during developing. Following the forming of vias 35 and 36, substantially transparent pixel electrodes 3 (made of indium-tin-oxide or ITO) are deposited and patterned over layer 33 on substrate 19 so that the pixel electrodes 3 contact the corresponding source metal layers 31 of corresponding TFTs 9 through vias 35 as illustrated in Figure 4. Auxiliary vias 36 (see Figure 1) are formed in layer 33 at the same time as vias 35 so that pixel electrodes 3 can contact storage capacitor electrodes 12 via pixel electrode extensions 38. Peripheral lead areas and seal areas are also removed by photo-imaging.
Insulating layer 33 is deposited on substrate 19 over the address lines, storage capacitors, and TFTs to a thickness "d" of at least about 0.5 µm in overlap areas 18. In preferred embodiments, the thickness "d" of insulating layer 33 is from about 1 to 2.5 µm.
Pixel opening sizes or the pixel aperture ratio of AMLCD 2 is at least about 65% (preferably from about 68% to 80%) according to certain embodiments of this invention when the pixel pitch is about 150 µm. This will, of course, vary depending upon the pixel pitch of the display (pixel pitches of from about 40 - 500 µm may be used). Pixel electrodes 3 overlap address lines 5 and 7 along the edges thereof as shown in Figure 1 by an amount up to about 3 µm. In certain preferred embodiments of this invention, the overlap 18 of electrodes 3 over the edges of address lines 5 and 7 is designed to be from about 2 to 3 µm, with the end result after overetching being at least about 0.5 µm. According to certain other embodiments of this invention, the amount of overlap may be designed to be from about 2-3 µm, with the resulting post-processing overlap being from about 0 to 2 µm. The overlap amount may be adjusted in accordance with different LCD applications and pixel pitch sizes as will be appreciated by those of skill in the art.
Referring now to Figures 4-5 and 8-11, it will be described how AMLCD 2 including the array of TFT structures and corresponding address lines is made according to an embodiment of this invention. Firstly, substantially transparent substrate 19 is provided. Next, a gate metal layer or sheet (which results in gate electrodes 17 and lines 7) is deposited on the top surface (surface to be closest to the LC layer) of substrate 19 to a thickness of from about 1,000 - 5,000 Å, most preferably to a thickness of about 2,500 Å. The gate metal sheet is deposited by way of sputtering or vapor deposition. The gate metal may be of tantalum (Ta) according to certain embodiments of this invention. Insulating substrate 19 may be of glass, quartz, sapphire, or the like.
After gate address lines 7 are deposited and patterned on top of substrate 19 in the above-described manner, gate insulating or dielectric layer 21 is deposited over substantially the entire substrate 19 preferably by plasma enhanced chemical vapor deposition (CVD) or some other process known to produce a high integrity dielectric. The resulting structure is shown in Figure 8. Gate insulating layer 21 is preferably silicon nitride (Si3N4) but may also be silicon dioxide or other known dielectrics. Silicon Nitride has a dielectric constant of about 6.4. Gate insulating layer 21 is deposited to a thickness of from about 2,000 - 3,000 Å (preferably either about 2,000 Å or 3,000 Å) according to certain embodiments.
Next, after gate insulating layer 21 has been deposited (Figure 8), semiconductor (e.g. intrinsic a-Si) layer 23 is deposited on top of gate insulating layer 21 to a thickness of about 2,000 Å. Semiconductor layer 23 may be from about 1,000 Å to 4,000 Å thick in certain embodiments of this invention. Then, doped (typically phosphorous doped, that is n+) amorphous silicon contact layer 25 is deposited over intrinsic a-Si layer 23 in a known manner to a thickness of, for example, about 500 Å. Doped contact layer 25 may be from about 200 Å to 1,000 Å thick according to certain embodiments of this invention. The result is the Figure 9 structure.
Following the formation of the Figure 9 structure, the TFT island or area may be formed by way of etching, for example, so that the TFT metal layers can be deposited thereon. Optionally, one of the TFT metal source/drain layers may be deposited before forming the TFT island.
According to preferred embodiments, following the formation of the TFT island from the Figure 9 structure, a source-drain metal sheet or layer (which results in drain metal layer 29 and source metal layer 31) is deposited on substrate 19 over top of semiconductor layer 23 and contact layer 25. This source-drain metal layer may be chromium (Cr) or molybdenum (Mo) according to certain embodiments of this invention. When chromium, the layer is deposited to a thickness of about 500 - 2,000 Å, preferably about 1,000 Å according to certain embodiments. When molybdenum, the layer is deposited to a thickness of from about 2,000 to 7,000 Å, preferably about 5,000 Å. The deposited source drain metal layer sheet is then patterned (masked and etched) to form the source, drain, and storage capacitor electrodes. After patterning of the TFT source and drain electrodes, the result is the Figure 10 TFT structure.
After patterning of drain and source portions 29 and 31, contact layer 25 is etched in the channel 27 area and inevitably a bit of semiconductor layer 23 is etched along with it. The result is TFT 9 with channel 27 as shown in Figures 4 and 10.
Substantially transparent polymer insulating layer 33 is then deposited onto substantially the entire substrate 19 by way of spin-coating according to certain embodiments of this invention. Layer 33 may be of either photo-imageable BCB or Fuji Clear™ according to certain embodiments. Insulating layer 33 fills recesses generated upon formation of TFTs 9 and flattens the surface above substrate 19 at least about 60% according to certain embodiments. The result is the structure of Figure 11.
After vias 35 and 36 are formed in layer 33, a substantially transparent conducting layer (e.g. ITO) which results in pixel electrodes 3 is deposited and patterned (photomasked and etched) on substrate 19 over top of layer 33. After patterning (e.g. mask and etching) of this substantially transparent conducting layer, pixel electrodes 3 are left as shown in Figures 1 and 4. As a result of vias 35 and 36 formed in layer 33, each pixel electrode 3 contacts a TFT source electrode 31 as shown in Figure 4 and a storage capacitor electrode 12 as shown in Figure 1. The result is the active plate of Figures 1 and 4 including an array of TFTs. The pixel electrode layer (when made of ITO) is deposited to a thickness of from about 1,200 to 3,000 Å (preferably about 1,400 Å) according to certain embodiments of this invention. Other known materials may be used as pixel electrode layer 3.
After formation of the active plate, liquid crystal layer 45 is disposed and sealed between the active plate and the passive plate as shown in Figure 5, the passive plate including substrate 51, polarizer 53, electrode 49, and orientation film 47.
As shown in Figure 1, pixel electrodes 3 are patterned to a size so that they overlap both drain address lines 5 and gate address lines 7 along the edges thereof so as to result in an increased pixel aperture ratio for AMLCD 2. The cross-talk problems of the prior art are substantially eliminated due to the presence of layer 33 in overlap areas 18 between pixel electrodes 3 and the address lines. Alternatively, the pixel electrodes may only overlap one group of address lines (e.g. row lines) according to certain embodiments.
Figure 5 is a side elevational cross-sectional view of AMLCD 2 (absent the TFTs, address lines, and black matrix). As shown, the twisted nematic display includes from the rear forward toward the viewer, rear polarizer 41, substantially transparent substrate 19, pixel electrodes 3, rear orientation film 43, liquid crystal layer 45, front orientation film 47, common electrode 49, front substantially transparent substrate 51, and finally front polarizer 53. Polarizers 41 and 53 may be arranged so that their transmission axes are either parallel or perpendicular to each other so as to define a normally black or normally white color AMLCD respectively. Optionally, retarder(s) may also be provided.
Figure 6 illustrates an optional black matrix (BM) pattern 55 to be disposed on front substrate 51 for the purpose of overlaying address lines 5 and 7 and TFT channels 27. When the ITO of the pixel electrodes 3 overlaps the address lines, the address lines themselves are effectively the black matrix blocking light in the interpixel areas. However, low reflectance black matrix 55 with a larger than normal opening is still useful on the top (or passive) plate in order to reduce specular reflectance and to prevent ambient light incidence on the TFT channels. Therefore, the pixel aperture ratio of the display can be made larger because the pixel electrode area is larger and the overlap between the pixel electrodes on the active plate and black matrix 55 on the passive plate can be reduced.
Black matrix structure 55 includes vertically extending regions 56 and horizontally extending regions 57. Regions 56 are aligned with drain lines 5 while regions 57 are aligned with gate lines 7 so as to prevent ambient light from penetrating the display.
Additionally, black matrix 55 includes channel covering portions 58 which are aligned with TFT channels 27 for the purpose of preventing ambient light from reaching amorphous silicon semiconductor layer 23 through the channels. As commonly known in the art, the pixel openings 65 of the display are substantially defined by (i.e. bounded by) black matrix regions 56 and 57.
Figure 7 is a side elevational cross-sectional view of a portion of AMLCD 2. As shown, the central pixel electrode 3 illustrated in Figure 7 overlaps both column or drain address lines 5 by an amount "w" thereby increasing the pixel electrode size relative to that of many prior art displays. Electrodes 3 are spaced from the address lines by a distance "d". Also, black matrix portions 56 line up with address lines 5 so that the pixel aperture or opening for the center electrode 3 is defined in part by the distance between black matrix members 56. Black matrix portions 56 and address lines 5 are both arranged so that their central axes correspond with the gaps between pixel electrodes 3 according to certain embodiments of this invention. The presence of layer 33 substantially reduces the parasitic capacitance of the capacitor created between pixel electrodes 3 and address lines 5 in the overlap areas 18 as set forth above.
This invention will now be described with respect to certain examples set forth below in Chart 1. CHART 1
Insulating Layer 33 Material Overlap distance "w" Distance "d" Line-Pixel Capacitance (fF) Dielectric Constant ε
Example 1 BCB 1 µm 2 µm 4.5 2.7
Example 2 BCB 2 µm 2 µm 6.9 2.7
Example 3 BCB 1 µm 1 µm 6.9 2.7
Example 4 BCB 2 µm 1 µm 11.7 2.7
Example 5 Fuji Clear™ 1 µm 2 µm 7.5 4.5
Example 6 Fuji Clear™ 2 µm 2 µm 11.5 4.5
Example 7 Fuji Clear™ 1 µm 1 µm 11.5 4.5
Example 8 Fuji Clear™ 2 µm 1 µm 19.4 4.5
The values set forth above in Chart 1 are for a display wherein the side of each pixel electrode 3 which overlaps the address line is about 100 µm long. Thus, the area of overlap is about 100 µm long. Also, the dielectric constants ε in Chart 1 above are for insulation layer 33.
Distances "w" and "d" are shown in Figure 7, with distance "w" being the width of the overlap and distance "d" the vertical spacing between the pixel electrodes and the overlapped address lines.
Compare the values in Chart 1 with a conventional coplanar LCD in which the pixel electrodes are substantially coplanar with the address lines and spaced therefrom, such a conventional LCD having a line-pixel capacitance of about 11.8 fF (caused in part by the LC material) when the electrodes are spaced laterally from the address lines by about 5 µm, and about 9.6 fF when the lateral spacing is about 10 µm. Thus, the high aperture LCDs of Examples 1-8 have a higher pixel aperture ratio than conventional LCDs without suffering from substantially higher line-pixel capacitance values. The capacitance values set forth above in Chart 1 were arrived at from the CPL equation above in combination with taking into consideration the fringing capacitance in a known manner.
A high aperture liquid crystal display comprising:
an array of substantially transparent pixel electrodes disposed on said first substrate, a plurality of the pixel electrodes in said array of pixel electrodes overlapping at least one of said address lines thereby increasing the pixel aperture ratio of the LCD;
a photo-imageable insulating layer disposed on said first substrate between said address lines and said pixel electrodes at least in the areas of overlap and areas adjacent source electrodes of the TFTs; and
said photo-imageable insulating layer having a first group of contact vias defined therein by photo-imaging, wherein said pixel electrodes are in electrical communication with corresponding TFT source electrodes through said contact vias of said first group defined in said insulating layer.
The LCD of claim 1, further comprising an auxiliary storage capacitor electrode associated with each pixel electrode, and a second group of contact vias defined in said insulating layer by photo-imaging, and wherein each of said pixel electrodes is in electrical communication with a corresponding storage capacitor electrode through one of the vias in said second group of contact vias.
The LCD of claim 1, wherein said insulating layer is a negative resist layer.
The LCD of claim 1, wherein said insulating layer includes one of 2-Ethoxyethyl acetate and Benzocyclobutene (BCB).
The LCD of claim 1, wherein the dielectric constant ε of said insulating layer is less than about 3.0.
The LCD of claim 1, wherein said insulating layer includes an organic mixture of 2-Ethoxyethyl acetate, methacrylate derivative copolymer, and polyfunctional acrylate.
The LCD of claim 1, wherein said insulating layer is from about 2-3 µm thick.
The LCD of claim 1, wherein said insulating layer covers substantially the entire viewing area of the display except for contact vias formed therein.
The LCD of claim 1, wherein the pixel aperture ratio of the LCD is at least about 68%.
The LCD of claim 1, wherein the overlap distance or width is from about 0-2 µm in the overlap areas and the address line-pixel capacitance is less than about 12.0 fF when the length of the overlap area is about 100 µm.
The LCD of claim 10, wherein the capacitance is less than about 8.0 fF.
A TFT array structure comprising:
an array of TFTs on a substrate, said TFTs being connected to a corresponding array of pixel electrodes;
row and column address lines on said substrate for addressing said TFTs; and
photo-imageable insulating means disposed between (i) said pixel electrodes; and (ii) said address lines so as to reduce crosstalk and permit said means to be photo-imaged.
A liquid crystal display with a large pixel aperture ratio comprising:
an array of thin film transistors and corresponding pixel electrodes mounted on said first substrate, each of said thin film transistors including a semiconductor layer, a gate electrode connected to a gate address line, a drain electrode connected to a drain address line, and a source electrode connected to one of said corresponding pixel electrodes, and wherein said pixel electrode connected to said source electrode overlaps said gate and drain address lines along longitudinal edges thereof; and
a substantially continuous insulating layer having a dielectric constant ε no greater than about 3.0 disposed between said pixel electrode and said address lines in sufficient thickness so as to reduce capacitive cross-talk in the display by reducing the pixel electrode-address line parasitic capacitance CPL in the areas of overlap.
The liquid crystal display of claim 13, wherein CPL is defined by the equation: C PL = ε · ε 0 · A d
where ε0 is 8.85 x 10-14 F/cm, "d" is the insulating layer thickness in the overlap areas, and "A" is the area of the capacitor formed between said pixel electrode and said address lines in the overlap area; and
wherein CPL is less than or equal to about 0.01 pF when the pixel pitch of the display is about 150 µm so as to reduce cross-talk in the display.
The liquid crystal display of claim 13, wherein the insulating layer thickness "d" is at least about 1.5 µm in the overlap areas.
The liquid crystal display of claim 15, wherein "d" is from about 2 to 3 µm in the overlap areas and said insulating layer has a degree of planarization of at least about 90%.
The liquid crystal display of claim 15, wherein the display has a pixel aperture ratio of at least about 65%, and a pixel pitch of from about 40 to 500 µm.
The liquid crystal display of claim 13, wherein said insulating layer includes Benzocyclobutene (BCB) and has a dielectric constant ε of about 2.7 or less.
a substantially transparent substrate adjacent said liquid crystal layer;
an array of thin film transistors disposed on said substrate, said thin film transistors connected to address lines and acting as switching elements for energizing corresponding pixel electrodes;
a substantially transparent planarization layer disposed on said array of transistors, said planarization layer being located between (i) said pixel electrodes; and (ii) said address lines; and
wherein said planarization layer includes Benzocyclobutene (BCB) and has a dielectric constant of less than about 3.0.
A method of making an array of semiconductor based thin film transistors (TFTs), the method comprising the steps of:
forming an array of electrode members on the first substrate over the photo-imaged insulating layer so that the electrode members in the array are in communication with the corresponding TFTs through the first array of vias or contact holes.
The method of claim 20, further comprising the step of overlapping the address lines with the electrode members so that the photo-imaged insulating layer is disposed therebetween so as to reduce cross-talk.
The method of claim 21, further comprising the steps of (i) using the TFT array in one of a liquid crystal display and an image sensor, and (ii) forming the insulating layer so as to include one of photo-imageable BCB and 2-Ethoxyethyl acetate.
The display of claim 19, wherein the BCB layer is non-photo-imageable.
EP19960109003 1995-06-06 1996-06-05 LCD with bus lines overlapped by pixel electrodes and photo-imageable insulating layer therebetween Expired - Lifetime EP0752611B1 (en)
US47027195A true 1995-06-06 1995-06-06
US470271 1995-06-06
SI9630583T SI0752611T1 (en) 1995-06-06 1996-06-05 LCD with bus lines overlapped by pixel electrodes and photo-imageable insulating layer therebetween
EP02016744A EP1256836B1 (en) 1995-06-06 1996-06-05 LCD with bus lines overlapped by pixel electrodes and insulating layer therebetween
EP02016744A Division EP1256836B1 (en) 1995-06-06 1996-06-05 LCD with bus lines overlapped by pixel electrodes and insulating layer therebetween
EP0752611A2 true EP0752611A2 (en) 1997-01-08
EP0752611A3 EP0752611A3 (en) 1997-11-26
EP0752611B1 EP0752611B1 (en) 2003-01-15
EP19960109003 Expired - Lifetime EP0752611B1 (en) 1995-06-06 1996-06-05 LCD with bus lines overlapped by pixel electrodes and photo-imageable insulating layer therebetween
EP02016744A Expired - Lifetime EP1256836B1 (en) 1995-06-06 1996-06-05 LCD with bus lines overlapped by pixel electrodes and insulating layer therebetween
US (15) US5641974A (en)
AT (1) AT231247T (en)
DE (2) DE69625750D1 (en)
PT (1) PT752611E (en)
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CA2178232C (en) 2006-08-01
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