Source: http://www.google.com/patents/US7398455?dq=6,073,142
Timestamp: 2016-09-30 10:44:06
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Matched Legal Cases: ['application No. 10', 'application No. 03146510', 'application No. 03254214', 'application No. 03254214', 'application No. 03254214', 'application No. 03254214', 'application No. 03254214', 'application No. 2003', 'application No. 2003', 'application No. 10']

Patent US7398455 - Method and system for decoding low density parity check (LDPC) codes - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn approach is provided for transmitting messages using low density parity check (LDPC) codes. Input messages are encoded according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The LDPC codes are transmitted over a radio...http://www.google.com/patents/US7398455?utm_source=gb-gplus-sharePatent US7398455 - Method and system for decoding low density parity check (LDPC) codesAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7398455 B2Publication typeGrantApplication numberUS 11/059,938Publication dateJul 8, 2008Filing dateFeb 17, 2005Priority dateJul 3, 2002Fee statusPaidAlso published asUS7020829, US8145980, US20040005865, US20050166133, US20080065947Publication number059938, 11059938, US 7398455 B2, US 7398455B2, US-B2-7398455, US7398455 B2, US7398455B2InventorsMustafa Eroz, Feng-Wen Sun, Lin-nan LeeOriginal AssigneeThe Directv Group, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (73), Non-Patent Citations (55), Referenced by (18), Classifications (49), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for decoding low density parity check (LDPC) codes
US 7398455 B2Abstract
This application is a continuation of U.S. patent application No. 10/454,439 filed Jun. 4, 2003 now U.S. Pat. No. 7,020,829. This application is related to, and claims the benefit of the earlier filing date under 35 U.S.C. �119(e) at U.S. Provisional Patent Application (Ser. No. 60/393,457) filed Jul. 3, 2002, entitled “Code Design and Implementation Improvements for Low Density Parity Check Codes,” U.S. Provisional Patent Application (Ser. No. 60/398,760) filed Jul. 26, 2002, entitled “Code Design and Implementation Improvements for Low Density Parity Check Codes,” U.S. Provisional Patent Application (Ser. No. 60/403,812) filed Aug. 15, 2002, entitled “Power and Bandwidth Efficient Modulation and Coding Scheme for Direct Broadcast Satellite and Broadcast Satellite Communications,” U.S. Provisional Patent Application (Ser. No. 60/421,505), filed Oct. 25, 2002, entitled “Method and System for Generating Low Density Parity Check Codes,” U.S. Provisional Patent Application (Ser. No. 60/421,999), filed Oct. 29, 2002, entitled “Satellite Communication System Utilizing Low Density Parity Check Codes,” U.S. Provisional Patent Application (Ser. No. 60/423,710), filed Nov. 4, 2002, entitled “Code Design and Implementation Improvements for Low Density Parity Check Codes.” U.S. Provisional Patent Application (Ser. No. 60/440,199) filed Jan. 15, 2003, entitled “Novel Solution to Routing Problem in Low Density Parity Check Decoders,” U.S. Provisional Patent Application (Ser. No. 60/447,641) filed Feb. 14, 2003, entitled “Low Density Parity Check Code Encoder Design,” U.S. Provisional Patent Application (Ser. No. 60/451,548) filed Mar. 3, 2003, entitled “System and Method for Advanced Modulation and Coding,” and U.S. Provisional Patent Application (Ser. No. 60/456,220) filed Mar. 20, 2003, entitled “Description LDPC and Encoders”; the entireties of which are incorporated herein by reference.
These and other needs are addressed by the present invention, wherein ad approach for decoding a structured Low Density Parity Check (LDPC) codes is provided. Structure of the LDPC codes is provided by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between processing nodes of the decoder becomes very simple. Also, the approach can advantageously exploit the unequal error protecting capability of LDPC codes on transmitted bits to provide extra error protection to more vulnerable bits of high order modulation constellations (such as 8-PSK (Phase Shift Keying)). The decoding process involves iteratively regenerating signal constellation bit metrics into an LDPC decoder after each decoder iteration or several decoder iterations. The above arrangement provides a computational efficient approach to decoding LDPC codes.
*y j=−ƒ(0,e j) j=0,1,2 where ƒ(a,b)=max(a,b)+LUTf(a,b) with LUTf(a,b)=ln(1+e −|a−b|)
*p 0 =x 0 +x 1 +x 2 p 1 =x 0 +x 1 +y 2 p 2 =x 0 +y 1 +x 2 p 3 =x 0 +y 1 +y 2 p 4 =y 0 +x 1 +x 2 p 5 =y 0 +x 1 +y 2 p 6 =y 0 +y 1 +x 2 p 7 =y 0 +y 1 +y 2 Next, the bit metric generator 307 determines a priori log likelihood ratios of the coded bits as input to LDPC decoder 305, as follows:
u 0=ƒ(d 0 +p 0 ,d 1 +p 1 ,d 2 +p 2 ,d 3 +p 3)−ƒ(d 4 +p 4 ,d 5 +p 5 ,d 6 +p 6 ,d 7 +p 7)−e 0 u 1=ƒ(d 0 +p 0 ,d 1 +p 1 ,d 4 +p 4 ,d 5 +p 5)−ƒ(d 2 +p 2 ,d 3 +p 3 ,d 6 +p 6 ,d 7 +p 7)−e 1 u 2=ƒ(d 0 +p 0 ,d 2 +p 2 ,d 4 +p 4 ,d 6 +p 6)−ƒ(d 1 +p 1 ,d 3 +p 3 ,d 5 +p 5 ,d 7 +p 7)−e 2 It is noted that the function ƒ(.) with more than two variables can be evaluated recursively; e.g. ƒ(a,b,c)=ƒ(ƒ(a,b),c).
Per step 1007, it is determined whether all the parity check equations are satisfied. If these parity check equations are not satisfied, then the decoder 305, as in step 1009, re-derives 8-PSK bit metrics and channel input un. Next, the bit node is updated, as in step 1011. As shown in FIG. 14C, the incoming messages to the bit node n from its dν adjacent check nodes are denoted by wk 1 →n, wk 2 →n, . . . , wk dν →n The outgoing messages from the bit node n are computed back to dν adjacent check nodes; such messages are denoted by
ƒ1=ν1→k ƒ2=g(ƒ1,ν2→k) ƒ3=g(ƒ2,ν3→k) : : : ƒdc=g(ƒdc−1,νdc→k)
wk→1=b2 wk→i=g(ƒi−1,bi+1) i=2,3, . . . ,dc−1 wk→dc=ƒdc−1 Under this approach, only the forward variables, ƒ2, ƒ3, . . . , ƒdc, are required to be stored. As the backward variables bi are computed, the outgoing messages, wk→i, are simultaneously computed, thereby negating the need for storage of the backward variables.
Continuing with the above example, a group of 392 bit nodes and 392 check nodes are selected for processing at a time. For 392 check node processing, q consecutive rows are accessed from the top edge RAM, and 2 consecutive rows from the bottom edge RAM. In this instance, q+2 is the degree of each check node. For bit node processing, if the group of 392 bit nodes has degree 2, their edges are located in 2 consecutive rows of the bottom edge RAM. If the bit nodes have degree d>2, their edges are located in some d rows of the top edge RAM. The address of these d rows can be stored in non-volatile memory, such as Read-Only Memory (ROM). The edges in one of the rows correspond to the first edges of 392 bit nodes, the edges in another row correspond to the second edges of 392 bit nodes, etc. Moreover for each row, the column index of the edge that belongs to the first bit node in the group of 392 can also be stored in ROM. The edges that correspond to the second, third, etc. bit nodes follow the starting column index in a “wrapped around” fashion. For example, if the jth edge in the row belongs to the first bit node, then the (j+1)st edge belongs to the second bit node, (j+2)nd edge belongs to the third bit node, and (j−1)st edge belongs to the 392th bit node.
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