Source: http://www.google.com/patents/US7834648
Timestamp: 2016-02-14 02:23:27
Document Index: 412048859

Matched Legal Cases: ['art 400', 'art 400', 'art 400', 'art 400', 'art 400', 'art 400']

Patent US7834648 - Controlling temperature in a semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsSystems and methods for reducing temperature dissipation during burn-in testing are described. Devices under test are each subject to a body bias voltage. The body bias voltage can be used to control junction temperature (e.g., temperature measured at the device under test). The body bias voltage applied...http://www.google.com/patents/US7834648?utm_source=gb-gplus-sharePatent US7834648 - Controlling temperature in a semiconductor deviceAdvanced Patent SearchPublication numberUS7834648 B1Publication typeGrantApplication numberUS 12/330,324Publication dateNov 16, 2010Filing dateDec 8, 2008Priority dateMar 1, 2004Fee statusPaidAlso published asCN1997904A, CN1997904B, US6900650, US7463050, WO2005085886A1Publication number12330324, 330324, US 7834648 B1, US 7834648B1, US-B1-7834648, US7834648 B1, US7834648B1InventorsEric Chen-Li Sheng, David H. Hoffman, John Laurence NivenOriginal AssigneeEric Chen-Li Sheng, Hoffman David H, John Laurence NivenExport CitationBiBTeX, EndNote, RefManPatent Citations (74), Non-Patent Citations (29), Referenced by (4), Classifications (7), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetControlling temperature in a semiconductor device
US 7834648 B1Abstract
Systems and methods for reducing temperature dissipation during burn-in testing are described. Devices under test are each subject to a body bias voltage. The body bias voltage can be used to control junction temperature (e.g., temperature measured at the device under test). The body bias voltage applied to each device under test can be adjusted device-by-device to achieve essentially the same junction temperature at each device.
a gate, a drain, and a source, each formed within a substrate;
a terminal formed within said substrate and operable for receiving a body bias voltage; and
a temperature monitor operable for measuring a temperature of said semiconductor device, wherein a value for said temperature is adjusted by adjusting said body bias voltage.
2. The semiconductor device of claim 1, wherein said body bias voltage is selected to achieve a particular temperature measured at said semiconductor device.
3. The semiconductor device of claim 1, wherein said semiconductor device comprises a positive-channel metal-oxide semiconductor (PMOS) device.
4. The semiconductor device of claim 3, wherein said body bias voltage is in a range of approximately zero to five volts.
5. The semiconductor device of claim 1, wherein said semiconductor device comprises a negative-channel metal-oxide semiconductor (NMOS) device.
6. The semiconductor device of claim 5, wherein said body bias voltage is in a range of approximately zero to minus ten volts.
7. The semiconductor device of claim 1, wherein said temperature is measured at an interface between a heat sink and a die of said semiconductor device.
a gate formed in a substrate;
a drain formed in said substrate;
a source formed in said substrate; and
a terminal formed in said substrate and coupled to a well comprising said source, wherein said terminal operable is for receiving a body bias voltage, wherein a temperature on said semiconductor device is monitored and wherein an amount of said body bias voltage is selected to achieve a particular value for said temperature.
9. The semiconductor device of claim 8, wherein said semiconductor device comprises a positive-channel metal-oxide semiconductor (PMOS) device.
10. The semiconductor device of claim 9, wherein said amount of body bias voltage is in a range of approximately zero to five volts.
11. The semiconductor device of claim 8, wherein said semiconductor device comprises a negative-channel metal-oxide semiconductor (NMOS) device.
12. The semiconductor device of claim 11, wherein said amount of body bias voltage is in a range of approximately zero to minus ten volts.
applying an operating voltage to a semiconductor device comprising a well that includes a source region; and
applying an amount of body bias voltage to said well, wherein said amount of body bias voltage is selected to achieve a particular value for a temperature measured at said semiconductor device.
14. The method of claim 13, further comprising adjusting said amount of body bias voltage to adjust a value of said temperature measured at said semiconductor device.
15. The method of claim 13, wherein said semiconductor device comprises a positive-channel metal-oxide semiconductor (PMOS) device and said well comprises an N-well.
16. The method of claim 15, wherein said amount of body bias voltage is in a range of approximately zero to five volts.
17. The method of claim 13, wherein said semiconductor device comprises a negative-channel metal-oxide semiconductor (NMOS) device and said well comprises a P-well.
18. The method of claim 17, wherein said amount of body bias voltage is in a range of approximately zero to minus ten volts. Description
This application is a continuation application of the U.S. patent application Ser. No. 11/139,116, filed May 26, 2005, by Sheng et al., and entitled “System and Method for Controlling Temperature During Burn-in,” now U.S. Pat. No. 7,463,050, which in turn is a continuation application of the U.S. patent application Ser. No. 10/791,459, filed Mar. 1, 2004, by Sheng et al., and entitled “System and Method for Controlling Temperature During Burn-in,” now U.S. Pat. No. 6,900,650, both of which are hereby incorporated by reference in entirety.
This application is related to U.S. patent application Ser. No. 10/791,241 by E. Sheng et al., filed on Mar. 1, 2004, entitled “System and Method for Reducing Heat Dissipation During Burn-In,” now U.S. Pat. No. 6,897,671, assigned to the assignee of the present invention, and hereby incorporated by reference in its entirety.
This application is related to U.S. patent application Ser. No. 10/791,099 by E. Sheng et al., filed on Mar. 1, 2004, entitled “System and Method for Reducing Temperature Variation During Burn-In,” now U.S. Pat. No. 7,248,988, assigned to the assignee of the present invention, and hereby incorporated by reference in its entirety.
Embodiments of the present invention relate to burn-in of semiconductor devices.
Semiconductor devices (e.g., microprocessors) are screened for defects by performing burn-in operations that subject the devices to test conditions including an elevated temperature test condition. However, due to variations in burn-in power, ambient temperature, air flow and heat sink performance, all devices under test may not experience the same temperature during testing.
Variation in the wafer fabrication process is a primary cause of variation in burn-in power. Fabrication process variations can cause leakage current to differ from one part to another by as much as 100 percent. While leakage current from a chip is proportional to the number of transistors on the chip, leakage current is inversely proportional to the critical dimension of the transistors. Increasing the number of transistors and decreasing the size of the transistors, which are currently accelerating trends in chip making, aggravate the situation. A solution that can ameliorate problems caused by variations in burn-in power would be advantageous.
Therefore, a system and/or method for controlling temperature during burn-in, so that all devices experience essentially the same temperature during burn-in, would be valuable.
Accordingly, systems and methods for controlling temperature during burn-in testing are disclosed. In one embodiment, devices under test are each subject to a body bias voltage. The body bias voltage can be used to control “junction temperature” (e.g., temperature measured at the device under test). The body bias voltage applied to each device under test can be adjusted device-by-device to achieve essentially the same junction temperature at each device.
FIG. 1 illustrates a top view of a positive-channel field effect transistor (pFET) formed in an N-well in accordance with an embodiment of the present invention.
FIG. 2 illustrates an exemplary arrangement of integrated circuit devices configured for a burn-in testing, in accordance with one embodiment of the present invention.
FIG. 3 is a cross-sectional side view of an integrated circuit device configured for burn-in testing, in accordance with one embodiment of the present invention.
FIG. 4 is a flowchart of a method for controlling temperature during burn-in testing in accordance with one embodiment of the present invention.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as “applying,” “selecting,” “measuring,” “adjusting,” “regulating,” “accessing” or the like, refer to the action and processes (e.g., flowchart 400 of FIG. 4) of a computer system or similar intelligent electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
The following description of embodiments of the present invention describes coupling a body bias voltage to positive-channel field effect transistors (pFETs) or p-type metal-oxide semiconductor field effect transistors (p-type MOSFETS) formed in surface N-wells via a conductive sub-surface region of n-type doping when a p-type substrate and an N-well process are utilized. However, embodiments in accordance with the present invention are equally applicable to coupling a body bias voltage to negative-channel FETs (nFETs) or n-type MOSFETS formed in surface P-wells via a conductive sub-surface region of p-type doping when an n-type substrate and a P-well process are utilized. Consequently, embodiments in accordance with the present invention are well suited to semiconductors formed with and in either p-type or n-type materials.
FIG. 1 illustrates a top view of a pFET 50 (or p-type MOSFET) formed in an N-well 10 when a p-type substrate and an N-well process are utilized in accordance with one embodiment of the present invention. The N-well 10 has an n-type doping. Regions of a semiconductor device that are doped with an n-type dopant have one type of conductivity while regions that are doped with a p-type dopant have another type of conductivity. Typically, various dopant concentrations are utilized in different regions of the semiconductor device.
In the present embodiment, the pFET 50 has a body bias voltage Vnw applied to its bulk or body terminal B. As depicted in FIG. 1, the pFET 50 has gate G, drain D (p-type doping), source S (p-type doping), and bulk/body terminal B. In particular, the bulk/body terminal B is coupled to the N-well 10. Hence, a voltage applied to the bulk/body terminal B is received by the N-well 10. In the case of body biasing, the bulk/body terminal B receives a body bias voltage Vnw. Thus, the body bias voltage Vnw is applied to the N-well 10.
The pFET 50 is body biased to influence its performance. Without body biasing, the source S and bulk/body terminal B are coupled together. With body biasing, the source S and bulk/body terminal B are not coupled together. Body biasing enables the potential difference between the source S and bulk/body terminal B of the pFET 50 to be controlled, thereby providing the ability to control the threshold voltage level of the pFET 50. Other parameters, such as the leakage current associated with pFET 50, can also thereby be controlled. Increasing threshold voltage decreases leakage current. Thus, body biasing to increase threshold voltage can be used to decrease leakage current.
Burn-in operations to detect defects in integrated circuit are generally performed at stressing temperatures (e.g., 150 degrees Celsius), stressing voltage (e.g., 1.5 times nominal operating voltage), and at low operating frequencies (usually orders of magnitude slower than normal operating frequencies).
FIG. 2 illustrates an exemplary apparatus 100 including a number of devices under test (DUTs) 101, 102, . . . , N (e.g., integrated circuit devices) configured for a burn-in operation, in accordance with one embodiment of the present invention. In accordance with embodiments of the present invention, the integrated circuit devices 101, 102, . . . , N are exemplified by pFET 50 of FIG. 1. As noted above, the integrated circuit devices 101, 102, . . . , N may instead be nFETs.
The integrated circuits 101, 102, . . . , N of FIG. 2 may be arrayed on a printed wiring board 110, which may include sockets for accepting the integrated circuit devices 101, 102, . . . , N. Because it is desirable to operate the integrated circuit devices under test at an elevated temperature, wiring board 110 is typically placed in a temperature chamber capable of temperature regulation at test temperatures (e.g., 150 degrees Celsius). A typical burn-in test chamber may include a number of wiring boards.
Wiring board 110 includes, for example, wiring traces to conduct electrical signals between various power supplies, test controllers and/or instrumentation, and integrated circuit devices 101, 102, . . . , N under test. In the present embodiment, wiring board 110 includes an operating voltage supply distribution system 151 and a test control distribution system 152. It is appreciated that the distribution systems 151 and 152 can be configured using bus, point-to-point, individual topologies, or the like.
Test control distribution system 152 couples test controller 150 and the integrated circuit devices 101, 102, . . . , N under test, and delivers signals from the test controller 150 to the integrated circuit devices 101, 102, . . . , N under test. As will be discussed in more detail below, test controller 150 is also coupled to voltage supplies, temperature monitoring devices and an ambient temperature sensor in order to measure and control electrical parameters related to power consumption and temperature of the integrated circuit devices 101, 102, . . . , N under test.
Test controller 150 can be located on wiring board 110. However, due to various factors (e.g., the physical size and/or nature of equipment used to implement test controller 150), embodiments in accordance with the present invention are well-suited to situating test controller 150 components elsewhere within a test environment (e.g., on a separate wiring board coupled to wiring board 110, or outside of the thermal test chamber). For example, if test controller 150 were implemented as a workstation computer, it would generally be impractical to place such a workstation in a thermal test chamber due to its size and operating temperature limits.
A test unit controller, which may or may not be apart of test controller 150, can be used to stimulate the integrated circuit devices 101, 102, . . . , N under test with a test pattern sequence and/or test commands and to access a result. Embodiments in accordance with the present invention are well-suited to a wide variety of test unit controllers and testing methods, including, for example, Joint Test Action Group (JTAG) boundary scan and array built-in self test (ABIST).
Operating voltage supply distribution system 151 couples operating voltage supply 140 and the integrated circuit devices 101, 102, . . . , N under test. Operating voltage supply 140 provides voltage (Vdd) and current to operate the integrated circuit devices 101, 102, . . . , N under test. In the present embodiment, operating supply voltage supply 140 is also coupled to test controller 150 by, for example, a bus 156, so that operating supply voltage supply 140 can receive controlling signals from test controller 150.
In the present embodiment, each of the integrated circuit devices 101, 102, . . . , N under test is coupled to a respective positive body bias voltage generator 121, 122, . . . , N. Positive body bias voltage generators 121, 122, . . . , N provide a positive body biasing voltage to n-type wells disposed beneath pFET devices in the integrated circuit devices 101, 102, . . . , N under test. Such body biasing enables adjustment of threshold voltages of the pFET devices, for example, to reduce leakage current of the pFET devices. In one embodiment, the body bias voltage provided by generators 121, 122, . . . , N is in the range of approximately zero to five volts. In the present embodiment, positive body bias voltage generators 121, 122, . . . , N are also coupled to test controller 150 by, for example, a bus 157, so that the body bias voltage generators can receive control signals from test controller 150.
In a similar manner, each of the integrated circuit devices 101, 102, . . . , N under test is coupled to a respective negative body bias voltage generator 131, 132, . . . , N. Negative body bias voltage generators 131, 132, . . . , N provide a negative body biasing voltage to p-type wells disposed beneath nFET devices in the integrated circuit devices 101, 102, . . . , N under test. Such body biasing enables adjustment of threshold voltages of the nFET devices, for example, to reduce leakage current of the nFET devices. In one embodiment, the body bias voltage provided by generators 131, 132, . . . , N is in the range of approximately zero to minus ten volts. In the present embodiment, negative body bias voltage generators 131, 132, . . . , N are also coupled to test controller 150 by, for example, a bus 157, so that the body bias voltage generators can receive control signals from test controller 150.
It is appreciated that the positive body bias generators 121, 122, . . . , N and the negative body bias voltage generators 131, 132, . . . , N may be located on wiring board 110, or they may be located off of wiring board 110, in accordance with embodiments of the present invention.
In general, body bias voltage generators 121, 122, . . . , N and 131, 132, . . . , N are variable voltage sources. Their output voltage can be set (within a range) to a specific value. It is desirable, but not required, that such specific values be set digitally (e.g., by a command from test controller 150). Body biasing currents are typically on the order of low micro-amps per integrated circuit. Consequently, bias voltage generators 121, 122, . . . , N and 131, 132, . . . , N can be relatively small and inexpensive voltage sources.
In the present embodiment, the apparatus 100 also includes an ambient temperature monitor 160 that measures ambient temperature within the test chamber. Ambient temperature measurements are reported back to test controller 150 via bus 154, for example. Apparatus 100 can include more than one ambient temperature monitor.
Continuing with reference to FIG. 2, each of the integrated circuit devices 101, 102, . . . , N under test is coupled to a respective temperature monitor 111, 112, . . . , N. The temperature monitors 111, 112, . . . , N measure temperature at a respective integrated circuit device 101, 102, . . . , N under test. The temperature measurements are reported back to test controller 150 via bus 153, for example.
FIG. 3 is a cross-sectional side view of an integrated circuit device 101 configured for burn-in testing, in accordance with one embodiment of the present invention. FIG. 3 shows the integrated circuit device 101 connected to wiring board 110 by a number of pins 350. In the present embodiment, the integrated circuit device 101 includes a ball grid array (BGA) 340, a package 330, a die 320, and a heat sink 310. It is appreciated that the elements comprising integrated circuit device 101 are exemplary only, and the present invention is not limited to use with the integrated circuit exemplified by FIG. 3.
In the present embodiment, temperature monitor 111 is situated between the heat sink 310 and the die 320. Temperature monitor 111 can be a thermocouple, for example. Temperature monitor 111 is connected to a trace 315 that in turn may be connected to, or may represent a portion of, the bus 153 of FIG. 2.
The temperature measured at an integrated circuit device under test is referred to herein as “junction temperature.” In the example of FIG. 3, the junction temperature refers to the temperature at the die 320.
Referring to FIG. 2, the junction temperature (Tjunction) of an integrated circuit device 101, 102, . . . , N under test can be approximated according to the following relationship:
T junction =T ambient +Pθ i; [1]
where Tambient is the ambient temperature measured by ambient temperature monitor 160; P is the power consumed by the integrated circuit device; and θi is the thermal resistance of the integrated circuit device (e.g., the thermal resistance associated with the transfer of heat from die 320 of FIG. 3 to the surrounding air).
The power consumed (P) is a function of both the operating voltage supplied to the integrated circuit, as well as the body biasing voltage applied to the integrated circuit. According to the embodiments of the present invention, θi can be treated as a constant for all of the integrated circuit devices 101, 102, . . . , N under test because, as will be seen, power consumption P can be adjusted so that the junction temperature is essentially the same for all of the integrated circuit devices 101, 102, . . . , N under test.
The apparatus 100 of FIG. 2 is now described in operation according to one embodiment of the present invention. In overview, power consumption (P in equation [1]) of an integrated circuit can be adjusted by adjusting the threshold voltage of the integrated circuit, even if the operating voltage of the integrated circuit is held constant. Threshold voltage can be adjusted by adjusting the body bias voltage supplied to body biasing wells disposed beneath active semiconductors of the integrated circuit. Adjusting the threshold voltage of the integrated circuit can increase or decrease the leakage current of the integrated circuit, which is a significant component of an integrated circuit's power consumption P, especially during low frequency operation, for example, during a burn-in process. Thus, controlling the leakage current provides control over power consumption, and controlling body biasing voltage controls leakage current.
In accordance with an embodiment of the present invention, as illustrated by equation [1] above, the junction temperature (Tjunction) of an integrated circuit under test can be controlled by controlling the power consumed (P) by the integrated circuit when ambient temperature (Tambient) and thermal resistance (θi) are essentially constant. The power consumed (P) by the integrated circuit operating at a fixed operating voltage can be controlled by adjusting the body biasing voltage applied to the integrated circuit.
Referring to FIG. 2, a particular junction temperature (e.g., 150 degrees Celsius) is selected for burn-in testing. The ambient temperature of the thermal test chamber can also be specified. The thermal resistance (θi) associated with each of the integrated circuit devices 101, 102, . . . , N under test is also a known quantity, at least to a satisfactory approximation. Also, the voltage supplied by operating voltage supply 140 is known. Using this information, an initial value of the magnitude of body bias voltage to be applied at the beginning of testing to each of the integrated circuit devices 101, 102, . . . , N under test can be approximated.
However, because the temperature at each of the integrated circuit devices 101, 102, . . . , N under test is separately monitored using temperature monitors 111, 112, . . . , N, it is not necessary to determine a magnitude of body bias voltage to be initially applied to the devices under test. Instead, the magnitude of the body bias voltage to be applied can be determined empirically by measuring junction temperature, and then by adjusting the body bias voltage to achieve the junction temperature desired for burn-in testing.
After the burn-in test operation has begun, the junction temperature at each of the integrated circuit devices 101, 102, . . . , N under test is monitored. If any of the devices under test experiences a junction temperature that is different from that desired for burn-in testing, the body bias voltage of the device under test can be adjusted (increased or decreased) until the junction temperature returns to the desired value. In the present embodiment, the integrated circuit devices 101, 102, . . . , N are each associated with a respective positive body bias voltage generator 121, 122, . . . , N and negative body bias voltage generator 131, 132, . . . , N, and so the body bias voltage applied to one device under test can be adjusted without affecting the body bias voltages applied to the other devices under test.
The body bias voltage applied to each of the integrated circuit devices 101, 102, . . . , N under test can be adjusted automatically by test controller 150 based on feedback from the temperature monitors, or it can be adjusted manually.
Thus, the junction temperature at each of the integrated circuit devices 101, 102, . . . , N under test can be individually controlled by controlling the body bias voltage applied to each device. In this manner, variability from one device under test to another can be managed so that each device is subject to the same test temperature.
For instance, the ambient temperature within the test chamber may not be uniform, so that some devices under test are subject to a higher ambient temperature than others. Should this occur, it will be reflected in the measurement of junction temperature, because junction temperature is a function of ambient temperature (refer to equation [1] above). Accordingly, the junction temperature of devices in a higher temperature region of the test chamber can be adjusted by adjusting the body bias voltage applied to those devices, until their respective junction temperatures reach the desired test temperature.
In a similar manner, variations in heat sink performance from one device under test to another can be accounted for. There may be other variables that affect junction temperature and can introduce variability between the various devices under test. In general, by applying different back bias voltages to the different devices under test as needed, the variability from one device to the next can be reduced so that each device under test is subject to essentially the same burn-in test temperature.
In addition, body bias voltages can be adjusted over the course of the burn-in test to account for changes in test conditions that may occur over time. For instance, as the test chamber begins to heat up, body bias voltages can be adjusted to not only maintain the desired junction temperature, but also to control ambient temperature within an acceptable limit.
FIG. 4 is a flowchart 400 of a method for controlling temperature during burn-in testing in accordance with one embodiment of the present invention. Although specific steps are disclosed in flowchart 400, such steps are exemplary. That is, the present invention is well suited to performing various other steps or variations of the steps recited in flowchart 400. It is appreciated that the steps in flowchart 400 may be performed in an order different than presented.
In block 410 of FIG. 4, an operating voltage is applied to a device under test.
In block 420, a body bias voltage is applied to the device under test. The magnitude of the body bias voltage is selected so that a particular test temperature is achieved at the device under test. In one embodiment, the device under test includes a positive-channel metal-oxide semiconductor (PMOS) device, and the body bias voltage is in the range of approximately zero to five volts. In another embodiment, the device under test includes a negative-channel metal-oxide semiconductor (NMOS) device, and the body bias voltage is in the range of approximately zero to minus ten volts.
In block 430, the temperature at the device under test (e.g., the junction temperature) is measured.
In block 440, the magnitude of the body bias voltage applied to the device under test is adjusted if necessary, and by a necessary amount in order to maintain the desired test temperature (e.g., junction temperature) at the device under test. Flowchart 400 then returns to block 430. In this manner, temperature is continuously measured during burn-in and the body bias voltage is adjusted to maintain the correct junction temperature over the duration of the burn-in.
For instance, with reference to FIG. 2, integrated circuit device under test 101 receives a operating voltage supplied by voltage supply 140. Integrated circuit device under test 101 also receives a body bias voltage from either positive body bias voltage generator 121 (if device 101 is an NFET device) or negative body bias voltage generator 131 (if device 101 is a PFET device). The temperature at integrated circuit device under test 101 is measured using temperature monitor 111. The temperature at integrated circuit device under test 101 is provided to test controller 150. If the temperature at integrated circuit device under test 101 is less than or more than the desired test temperature, test controller 150 can adjust the body bias voltage provided to the device by either positive body bias voltage generator 121 or negative body bias voltage generator 131. Similarly, if the temperature measured by ambient temperature monitor 160 increases, then test controller 150 can adjust the body bias voltage provided to the integrated circuit device under test 101 by either positive body bias voltage generator 121 or negative body bias voltage generator 131 to maintain the desired test temperature at the device.
In summary, embodiments of the present invention provide systems and methods for controlling temperature during burn-in, so that all devices experience essentially the same temperature during burn-in. Thus, all devices under test can be subject to essentially the same test conditions. Consequently, one source of uncertainty that would otherwise be introduced into the test results is eliminated.
Although described for testing in which all devices under test are subject to essentially the same test temperature, it is appreciated that embodiments of the present invention can also be used to test devices under a range of temperatures at the same time. For example, by subjecting the various devices under test to different body bias voltages, some devices can be tested at one junction temperature while other devices are tested at another junction temperature.
In addition, although described for testing in which the devices under test are subject to a test temperature that remains essentially constant during the burn-in operation, it is appreciated that embodiments of the present invention can also be used to vary temperature during testing. For example, by varying body bias voltage during burn-in in a controlled manner, the junction temperature during burn-in is also varied in a controlled manner.
Embodiments in accordance with the present invention, system and method for controlling temperature during burn-in, are thus described. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as limited by such embodiments, but rather construed according to the below claims.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3244267Aug 1, 1963Apr 5, 1966Merck & Co IncConvergence apparatusUS3366220Nov 23, 1965Jan 30, 1968Gen Foods CorpMethod and apparatus for single filingUS4265356Aug 20, 1979May 5, 1981The Lodge & Shipley CompanyApparatus for combining articles from plural lanes into a single laneUS4313720Mar 3, 1980Feb 2, 1982Emhart Industries, Inc.Parison transfer meansUS4354813Sep 30, 1980Oct 19, 1982Motosacoche S.A.Plant for producing containers by drawing-blowing of preforms in plastic materialUS4434583Jul 6, 1981Mar 6, 1984Burgess Jr Warren CAutomatically adjustable workpiece guide and feed mechanismUS4938636Nov 14, 1988Jul 3, 1990Aidlin Automation Corp.Method and apparatus for feeding container bodiesUS5119337Apr 16, 1990Jun 2, 1992Kabushiki Kaisha ToshibaSemiconductor memory device having burn-in test functionUS5161665Nov 13, 1990Nov 10, 1992Riverwood International CorporationLane merger apparatusUS5186307Apr 7, 1992Feb 16, 1993SidelTransport device for removing interlocked preformsUS5309090Sep 6, 1990May 3, 1994Lipp Robert JApparatus for heating and controlling temperature in an integrated circuit chipUS5406212Jul 17, 1992Apr 11, 1995Sumitomo Electric Industries, Ltd.Burn-in apparatus and method for self-heating semiconductor devices having built-in temperature sensorsUS5501552Apr 29, 1994Mar 26, 1996Goldco Industries, Inc.Conveying system for unstable articles having a neck ringUS5607706Apr 5, 1995Mar 4, 1997Husky Injection Molding Systems Ltd.Preconditioning preforms on a reheat blow molding systemUS5701666Apr 16, 1997Dec 30, 1997Motorola, Inc.Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located on a product waferUS5772000Mar 28, 1996Jun 30, 1998Serres; Paul J.Hop vine transfer systemUS5834038Dec 11, 1995Nov 10, 1998Nissei Asb Machine Co., Ltd.Blow molding apparatusUS5844429Jul 15, 1996Dec 1, 1998Lg Semicon Co., Ltd.Burn-in sensing circuitUS5897671Nov 7, 1997Apr 27, 1999Diversey Lever, Inc.System and method for washing machine cycle identification and chemical dosing identificationUS5944165Apr 10, 1996Aug 31, 1999Lever Brothers CompanyLane distribution apparatusUS5995428Feb 27, 1998Nov 30, 1999United Microelectronics Corp.Circuit for burn-in operation on a wafer of memory devicesUS6035407Jul 15, 1996Mar 7, 2000Compaq Computer CorporationAccomodating componentsUS6037792Dec 21, 1996Mar 14, 2000Stmicroelectronics, Inc.Burn-in stress test modeUS6100751May 13, 1998Aug 8, 2000Intel CorporationForward body biased field effect transistor providing decoupling capacitanceUS6104061Feb 27, 1998Aug 15, 2000Micron Technology, Inc.Memory cell with vertical transistor and buried word and body linesUS6114866Feb 4, 1998Sep 5, 2000Mitsubishi Electric Systems Lsi Design CorporationSemiconductor device test board and method for evaluating semiconductor devicesUS6137301May 11, 1998Oct 24, 2000Vanguard International Semiconductor CompanyEPROM used as a voltage monitor for semiconductor burn-inUS6157201Jan 28, 1998Dec 5, 2000Sun Microsystems, Inc.Burn-in system for reliable integrated circuit manufacturingUS6218892Feb 24, 1999Apr 17, 2001Intel CorporationDifferential circuits employing forward body biasUS6232827 *May 13, 1998May 15, 2001Intel CorporationTransistors providing desired threshold voltage and reduced short channel effects with forward body biasUS6262588Aug 7, 2000Jul 17, 2001Vanguard International Semiconductor CorporationBias monitor for semiconductor burn-inUS6300819 *May 13, 1998Oct 9, 2001Intel CorporationCircuit including forward body bias from supply voltage and ground nodesUS6310485Jan 27, 2000Oct 30, 2001Stmicroelectronics, Inc.Integrated circuit device having a burn-in mode for which entry into and exit from can be controlledUS6455336Aug 27, 2001Sep 24, 2002International Business Machines CorporationPower reduction method and design technique for burn-inUS6577148Jul 24, 1995Jun 10, 2003Motorola, Inc.Apparatus, method, and wafer used for testing integrated circuits formed on a product waferUS6620352Jul 27, 2000Sep 16, 2003Ball CorporationAutomated material distribution control for stretch blow molded articlesUS6897671Mar 1, 2004May 24, 2005Transmeta CorporationSystem and method for reducing heat dissipation during burn-inUS6900650Mar 1, 2004May 31, 2005Transmeta CorporationSystem and method for controlling temperature during burn-inUS6956437Dec 23, 2003Oct 18, 2005Agere Systems Inc.Metal-oxide-semiconductor device having integrated bias circuitUS6985380 *Mar 26, 2004Jan 10, 2006Intel CorporationSRAM with forward body biasing to improve read cell stabilityUS7242205May 23, 2005Jul 10, 2007Transmeta CorporationSystem and method for reducing heat dissipation during burn-inUS7248988Mar 1, 2004Jul 24, 2007Transmeta CorporationSystem and method for reducing temperature variation during burn inUS7463050 *May 26, 2005Dec 9, 2008Transmeta CorporationSystem and method for controlling temperature during burn-inUS7508251 *Feb 5, 2007Mar 24, 2009Panasonic CorporationSemiconductor integrated circuit apparatusUS7565259 *Jul 24, 2007Jul 21, 2009Eric Chen-Li ShengSystem and method for reducing temperature variation during burn inUS7595652 *Jul 10, 2007Sep 29, 2009Eric Chen-Li ShengSystem and method for reducing heat dissipation during burn-inUS20020005083Jun 29, 2001Jan 17, 2002Voest-Alpine Industrieanlagenbau GmbhProcess for the production of metal meltsUS20020030533Sep 21, 2001Mar 14, 2002De Vivek K.Circuit including forward body bias from supply voltage and ground nodesUS20020050833Jul 14, 1999May 2, 2002Thomas P. JonesTemperature control of electronic devices using power following feedbackUS20020140496Feb 16, 2000Oct 3, 2002Ali KeshavarziForward body biased transistors with reduced temperatureUS20020186031Jul 19, 2002Dec 12, 2002Delta Design, Inc.Method and apparatus for temperature control of a device during testingUS20030001604Jul 2, 2001Jan 2, 2003Intel CorporationIntegrated circuit burn-in methods and apparatusUS20030001605Sep 5, 2002Jan 2, 2003Delta Design, Inc.Temperature control of electronic devices using power following feedbackUS20030091681Oct 25, 2002May 15, 2003Drysdale Barrie LloydMethod and apparatus for handling injection molded articlesUS20040016977May 6, 2003Jan 29, 2004Hitachi, Ltd.Semiconductor integrated circuit deviceUS20040083075Oct 29, 2002Apr 29, 2004Xuejun FanJunction temperatures measurements in semiconductor chip package technologyUS20040108867Dec 4, 2002Jun 10, 2004Butler Richard M.System for and method of assessing chip acceptability and increasing yieldUS20040111231Dec 15, 2003Jun 10, 2004Yoshiyuki AndoIntegrated circuits having post-silicon adjustment controlUS20040140818Nov 26, 2003Jul 22, 2004Martin PernerCircuit and method for determining at least one voltage, current and/or power value for an integrated circuitUS20040183588Apr 3, 2002Sep 23, 2004Massachusetts Institute Of TechnologyAdaptive power supply and substrate control for ultra low power digital processors using triple well controlUS20050048159Jan 28, 2003Mar 3, 2005Yoshino Kogyosho Co LtdPreform conveying deviceUS20050088137Sep 3, 2004Apr 28, 2005Aviad CohenMethods and apparatus for optimal voltage and frequency control of thermally limited systemsUS20050192773 *Mar 1, 2004Sep 1, 2005Sheng Eric C.System and method for reducing temperature variation during burn inUS20050240844Jun 28, 2005Oct 27, 2005Intel CorporationIntegrated circuit burn-in methods and apparatusUS20060020838Jun 30, 2004Jan 26, 2006Tschanz James WMethod, apparatus and system of adjusting one or more performance-related parameters of a processorUS20070271061Jul 24, 2007Nov 22, 2007Transmeta CorporationSystem and method for reducing temperature variation during burn inUS20080024152 *Jul 10, 2007Jan 31, 2008Transmeta CorporationSystem and method for reducing heat dissipation during burn-inUS20080075142 *Sep 22, 2006Mar 27, 2008Robert Carl BeierMethods and systems for protection from over-stressUS20090289654 *Nov 26, 2009Eric Chen-Li ShengSystem and method for reducing temperature variation during burn inUS20090316750 *Jun 19, 2009Dec 24, 2009Eric Chen-Li ShengSystem and method for reducing temperature variation during burn inEP0292126A2Apr 27, 1988Nov 23, 1988AT&amp;T Corp.Superconductive body having improved propertiesEP0292136A1Apr 29, 1988Nov 23, 1988Hewlett-Packard CompanyMethod and process for testing the reliability of integrated circuit (IC) chips and novel IC circuitry for accomplishing sameEP2527530A1May 25, 2012Nov 28, 2012ICOPAL GmbHBituminous roofing sheetWO2003040740A2Oct 18, 2002May 15, 2003Advanced Micro Devices IncFeedforward temperature control of device under test* Cited by examinerNon-Patent CitationsReference1Final Office Action; Mail Date Aug. 14, 2008; U.S. Appl. No. 11/827,290.2Final Office Action; Mail Date Jan. 3, 2008; U.S. Appl. No. 11/139,116.3Final Office Action; Mail Date Jun. 23, 2006; U.S. Appl. No. 11/136,038.4Final Office Action; Mail Date Mar. 28, 2007; U.S. Appl. No. 11/139,116.5Final Office Action; Mail Date Nov. 18, 2008; U.S. Appl. No. 11/881,006.6Final Office Action; Mail Date Oct. 31, 2006; U.S. Appl. No. 10/791,099.7Non Final Office Aciton; Mail Date Jul. 24, 2008; U.S. Appl. No. 11/881,006.8Non Final Office Aciton; Mail Date Nov. 28, 2005; U.S. Appl. No. 10/791,099.9Non Final Office Action, Mail Date Sep. 1, 2004; U.S. Appl. No. 10/791,241.10Non Final Office Action; Mail Date Aug. 29, 2006; U.S. Appl. No. 11/139,116.11Non Final Office Action; Mail Date Dec. 12, 2008; U.S. Appl. No. 11/827,290.12Non Final Office Action; Mail Date Jan. 28, 2008; U.S. Appl. No. 11/827,290.13Non Final Office Action; Mail Date Jan. 5, 2006; U.S. Appl. No. 11/136,038.14Non Final Office Action; Mail Date Jul. 18, 2005; U.S. Appl. No. 11/136,038.15Non Final Office Action; Mail Date Jul. 19, 2007; U.S. Appl. No. 11/139,116.16Non Final Office Action; Mail Date Jun. 13, 2005; U.S. Appl. No. 10/791,099.17Non Final Office Action; Mail Date May 25, 2006; U.S. Appl. No. 10/791,099.18Non Final Office Action; Mail Date Sep. 1, 2004; U.S. Appl. No. 10/791,459.19Notice of Allowance; Mail Date Apr. 13, 2005; U.S. Appl. No. 10/791,459.20Notice of Allowance; Mail Date Aug. 20, 2008; U.S. Appl. No. 11/139,116.21Notice of Allowance; Mail Date Feb. 6, 2007; U.S. Appl. No. 10/791,099.22Notice of Allowance; Mail Date Feb. 6, 2009; U.S. Appl. No. 11/827,290.23Notice of Allowance; Mail Date Jan. 13, 2005; U.S. Appl. No. 10/791,241.24Notice of Allowance; Mail Date Jun. 17, 2009; U.S. Appl. No. 11/881,006.25Notice of Allowance; Mail Date Mar. 1, 2007; U.S. Appl. No. 11/136,038.26Notice of Allowance; Mail Date May 19, 2009; U.S. Appl. No. 11/827,290.27Notice of Allowance; Mail Date May 7, 2008; U.S. Appl. No. 11/139,116.28Notice of Allowance; Mail Date Nov. 9, 2006; U.S. Appl. No. 11/136,038.29Restriction Requirement; Mail Date Jun. 3, 2008; U.S. Appl. No. 11/881,006.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8593148 *Jul 29, 2010Nov 26, 2013Sof-Tek Integrators, Inc.System and method of testing high brightness LED (HBLED)US8628239 *Jul 15, 2010Jan 14, 2014Teradyne, Inc.Storage device temperature sensingUS20110013667 *Jan 20, 2011Merrow Brian SStorage Device Temperature SensingUS20110025337 *Jul 29, 2010Feb 3, 2011Daniel Creighton MorrowSystem and method of testing high brightness led (hbled)* Cited by examinerClassifications U.S. Classification324/750.05International ClassificationG01R31/28, G01R31/02Cooperative ClassificationG01R31/2879, G01R31/2817European ClassificationG01R31/28B5E, G01R31/28G2D2Legal EventsDateCodeEventDescriptionMar 26, 2009ASAssignmentOwner name: TRANSMETA LLC, CALIFORNIAFree format text: MERGER;ASSIGNOR:TRANSMETA CORPORATION;REEL/FRAME:022454/0522Effective date: 20090127Sep 22, 2009ASAssignmentOwner name: INTELLECTUAL VENTURE FUNDING LLC, NEVADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRANSMETA LLC;REEL/FRAME:023268/0771Effective date: 20090128May 24, 2011CCCertificate of correctionApr 24, 2014FPAYFee paymentYear of fee payment: 4Sep 29, 2015ASAssignmentOwner name: INTELLECTUAL VENTURES HOLDING 81 LLC, NEVADAFree format text: MERGER;ASSIGNOR:INTELLECTUAL VENTURE FUNDING LLC;REEL/FRAME:036711/0160Effective date: 20150827Oct 6, 2015ASAssignmentOwner name: INTELLECTUAL VENTURES HOLDING 81 LLC, NEVADAFree format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR S NAME PREVIOUSLY RECORDED AT REEL: 036711 FRAME: 0160. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:INTELLECTUAL VENTURES FUNDING LLC;REEL/FRAME:036797/0356Effective date: 20150827RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services