Source: http://www.google.com/patents/US6500698?dq=6,274,924
Timestamp: 2014-07-12 04:25:43
Document Index: 225991112

Matched Legal Cases: ['Application No. 44721', 'art 70', 'art 70', 'art 70', 'art 110', 'art 70']

Patent US6500698 - Method for fabricating a stacked semiconductor chip package - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA stacked semiconductor chip package includes: a substrate including a plurality of conductive pads; a first semiconductor chip mounted on the substrate; and electrically connected to the conductive pads; a plurality of electrical leads provided about the substrate; a first molding part for sealing the...http://www.google.com/patents/US6500698?utm_source=gb-gplus-sharePatent US6500698 - Method for fabricating a stacked semiconductor chip packageAdvanced Patent SearchPublication numberUS6500698 B2Publication typeGrantApplication numberUS 09/977,313Publication dateDec 31, 2002Filing dateOct 16, 2001Priority dateOct 24, 1998Fee statusPaidAlso published asUS6339255, US20020022300Publication number09977313, 977313, US 6500698 B2, US 6500698B2, US-B2-6500698, US6500698 B2, US6500698B2InventorsMyoung-Jin ShinOriginal AssigneeHynix Semiconductor, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (19), Referenced by (7), Classifications (42), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod for fabricating a stacked semiconductor chip packageUS 6500698 B2Abstract A stacked semiconductor chip package includes: a substrate including a plurality of conductive pads; a first semiconductor chip mounted on the substrate; and electrically connected to the conductive pads; a plurality of electrical leads provided about the substrate; a first molding part for sealing the substrate and the first semiconductor chip; a second semiconductor chip mounted on an upper surface of the first molding part and electrically connected to the electrical leads; and a second molding part for sealing the second semiconductor chip, the second conductive wires and a portion of the leads.
What is claimed is: 1. A method for fabricating a stacked semiconductor chip package, comprising:
mounting a first semiconductor chip on a substrate having electrical connections formed thereon; electrically connecting the first semiconductor chip to the electrical connections formed on the substrate; providing a plurality of electrical leads about the substrate; enclosing the first semiconductor chip and the substrate in a first material to form a first body portion such that the first material is in contact with the first semiconductor chip; mounting a second semiconductor chip on the first body portion; electrically connecting the second semiconductor chip to the plurality of electrical leads; and enclosing the second semiconductor chip and a portion of each electrical lead to form a second body portion stacked on the first body portion. 2. The method according to claim 1, further comprising electrically connecting the electrical connections formed on the substrate to the plurality of leads, such that the first semiconductor chip is electrically connected to the plurality of electrical leads.
3. The method according to claim 1, wherein enclosing the first semiconductor chip and the substrate comprises enclosing the first semiconductor chip and the substrate in the first material which contains an epoxy molding compound.
4. The method according to claim 1, wherein enclosing the second semiconductor chip and the portion of each electrical lead comprises enclosing the second semiconductor chip and the portion of each electrical lead in the first material which contains an epoxy molding compound.
5. The method according to claim 1, wherein mounting the second semiconductor chip on the first body portion comprises mounting the second semiconductor chip on the first body portion with an adhesive.
6. The method according to claim 1, wherein the substrate includes a plurality of conductive pads formed thereon, wherein electrically connecting the first semiconductor chip to the electrical connections formed on the substrate comprises electrically connecting the first semiconductor chip to the plurality of conductive pads.
7. The method according to claim 6, wherein the plurality of conductive pads includes conductive pads provided on opposite surfaces of the substrate.
This application is a divisional of application Ser. No. 09/422,799, filed on Oct. 22, 1999, now U.S. Pat. No. 6,339,255, the entire contents of which are hereby incorporated by reference and for which priority is claimed under 35 U.S.C. � 120; and this application claims priority of Application No. 44721/1998 filed in Korea on Oct. 24, 1998 under 35 U.S.C. � 119.
With reference to FIG. 1, a SOJ semiconductor chip package is provided such that a semiconductor chip 1 is fixed to a paddle 3 of a lead frame (not shown) by an insulating adhesive or paste. Pads (not shown) of the semiconductor chip 1 are electrically connected with corresponding internal leads 2 by conductive wires 4. A package body 6 is formed by using material 5 to seal the semiconductor chip 1, the internal leads 2 and the conductive wires 4. Finally, external leads 2 are extended from the internal leads 2 to an exterior of the package body 6, each external lead 2 being formed in a�J� shape.
FIG. 1 is a vertical cross-sectional diagram of a conventional small outline J-leaded (SOJ) semiconductor chip package;
DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. FIG. 2 illustrates a semiconductor chip package according to a first embodiment of the present invention. As shown therein, a substrate 10 is provided having circuit patterns (not shown) laid therein. A plurality of electrical connections in the form of first conductive pads 20 are provided at both end sides on an upper surface of the substrate 10. A plurality of second conductive pads 30 which respectively correspond to the first conductive pads 20 are provided on a lower surface of the substrate 10. The first conductive pads 20 and the corresponding second conductive pads 30 are electrically interconnected to each other via the circuit patterns provided in the substrate 10. Further, a first semiconductor chip 40 which has a plurality of chip pads (not shown) is attached on the substrate 10 between the first conductive pads 20 provided on the both sides of the upper surface of the substrate 10. The chip pads of the first semiconductor chip 40 and the first conductive pads 20 are electrically connected by corresponding first conductive wires 50. In addition, leads 60 are attached at both end portions of the substrate 10. A first molding part 70 is formed in which the substrate 10, the first conductive pad 20, the second conductive pad 30, the first semiconductor chip 40 and the first conductive wires 50�except for the leads 60�are sealed by a molding epoxy resin 71. Here, surfaces of the first molding part 70 and each of the leads 60 have the same upper and lower surface levels.
A second semiconductor chip 80 which has a plurality of chip pads (not shown) and is attached onto a center portion of an upper surface of the first molding part 70 by an adhesive 90. The chip pads of the second semiconductor chip 80 are electrically connected with end portions of corresponding chip connection leads 61 of the leads 60 by second conductive wires 100. Further, there is formed a second molding part 110 in which a predetermined portion of the first molding part 70, including the second semiconductor chip 80 and the second conductive wires 100, is sealed by a molding epoxy resin 111.
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