Source: http://www.google.com/patents/US8072837?ie=ISO-8859-1&dq=7125605
Timestamp: 2015-03-01 03:10:29
Document Index: 226502892

Matched Legal Cases: ['Application No. 95', 'Application No. 95', 'Application No. 95', 'Application No. 95', 'Application No. 95', 'Application No. 95', 'Application No. 95']

Patent US8072837 - Circuit providing load isolation and memory domain translation for memory module - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select...http://www.google.com/patents/US8072837?utm_source=gb-gplus-sharePatent US8072837 - Circuit providing load isolation and memory domain translation for memory moduleAdvanced Patent SearchPublication numberUS8072837 B1Publication typeGrantApplication numberUS 12/981,380Publication dateDec 6, 2011Filing dateDec 29, 2010Priority dateMar 5, 2004Also published asUS7916574, US8081536, US8516188, US20110085406, US20140040569Publication number12981380, 981380, US 8072837 B1, US 8072837B1, US-B1-8072837, US8072837 B1, US8072837B1InventorsJeffrey C. Solomon, Jayesh R. BhaktaOriginal AssigneeNetlist, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (104), Non-Patent Citations (162), Classifications (10), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetCircuit providing load isolation and memory domain translation for memory module
US 8072837 B1Abstract
A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals. The circuit is further configurable to monitor command signals received by the memory module, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals, and to provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.
1. A circuit configured to be mounted on a memory module configured to be operationally coupled to a computer system, the memory module having a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory circuits that are configured to be activated concurrently with one another in response to a first number of DDR chip-select signals, the first number of ranks comprising a first number of DDR memory circuits, the circuit including at least one configuration in which the circuit is configured to:
receive a set of signals comprising address signals and a second number of DDR chip-select signals, the address signals comprising bank address signals, wherein the received set of signals are capable of controlling a memory module having a second number of ranks, each rank of the second number of ranks comprising a second plurality of DDR memory circuits that are configured to be activated concurrently with one another, the second number of ranks comprising a second number of DDR memory circuits, the second number of ranks smaller than the first number of ranks, the second number of DDR chip-select signals smaller than the first number of DDR chip-select signals, and the second number of DDR memory circuits smaller than the first number of DDR memory circuits;
monitor command signals received by the memory module;
selectively isolate a load of the DDR memory circuits of at least one rank of the first number of ranks from the computer system in response to the command signals; and
generate and provide the first number of DDR chip-select signals to the DDR memory circuits of the first number of ranks in response at least in part to the received bank address signals and the received second number of DDR chip-select signals.
2. The circuit of claim 1, wherein the circuit in the at least one configuration is further configured to respond at least in part to an address signal of the received set of signals received during a row access procedure by generating and providing the first number of DDR chip-select signals to the DDR memory circuits of the first number of ranks during a subsequent column address procedure in response at least in part to the address signal received during the row access procedure.
3. The circuit of claim 1, wherein the received address signals are received during a row access procedure and the first number of DDR chip-select signals are generated and provided to the DDR memory circuits of the first number of ranks during a subsequent column access procedure in response at least in part to the received address signals received during the row access procedure.
5. The circuit of claim 4, wherein the circuit in the at least one configuration is further configured to respond at least in part to the received bank address signals and the received second number of DDR chip-select signals by selecting at least one rank of the first number of ranks and transmitting the output command signal to the DDR memory circuits of the selected at least one rank of the first number of ranks.
6. The circuit of claim 1, wherein the circuit in the at least one configuration is further configured to control isolation of data strobe signal lines in response to the command signals.
7. The circuit of claim 1, wherein the circuit has a load and selectively isolating a load of the DDR memory circuits of the at least one rank from the computer system comprises presenting the load of the circuit to the computer system.
9. The circuit of claim 8, wherein the circuit in the at least on configuration is further configured to provide data paths for the DDR memory circuits of each rank of the first number of ranks, wherein the data paths of each rank of the first number of ranks are isolated from one another.
11. The circuit of claim 1, wherein the circuit in the at least one configuration is further configured to generate control signals in response to one or more control signals of the received set of signals and to transmit the generated control signals to the first number of DDR memory circuits.
12. The circuit of claim 11, wherein the one or more control signals comprises a row address bit and the circuit in the at least one configuration is further configured to latch the row address bit.
14. The circuit of claim 13, wherein the circuit in the at least one configuration is further configured to receive the command signals from the computer system, to select at least one rank of the first number of ranks, and to transmit the command signals to the DDR memory circuits of the selected at least one rank.
18. A method of using a memory module configured to be operationally coupled to a computer system, the memory module having a first number of ranks, each rank of the first number of ranks comprising a plurality of double-data-rate (DDR) memory circuits that are configured to be activated concurrently with one another in response to a first number of DDR chip-select signals, the first number of ranks comprising a first number of DDR memory circuits, the method comprising:
receiving a set of signals comprising address signals and a second number of DDR chip-select signals, the address signals comprising bank address signals, wherein the received set of signals are capable of controlling a memory module with a second number of ranks, each rank of the second number of ranks comprising a second plurality of DDR memory circuits that are configured to be activated concurrently with one another, the second number of ranks comprising a second number of DDR memory circuits, the second number of ranks smaller than the first number of ranks, the second number of DDR chip-select signals smaller than the first number of DDR chip-select signals, and the second number of DDR memory circuits smaller than the first number of DDR memory circuits;
monitoring command signals received by the memory module;
selectively isolating a load of the DDR memory circuits of at least one rank of the first number of ranks from the computer system in response to the command signals; and
generating and providing the first number of DDR chip-select signals to the DDR memory circuits of the first number of ranks in response at least in part to the received bank address signals and the received second number of DDR chip-select signals.
19. The method of claim 18, further comprising responding at least in part to an address signal of the received address signals received during a row access procedure by generating and providing the first number of DDR chip-select signals to the DDR memory circuits of the first number of ranks during a subsequent column access procedure.
20. The method of claim 18, further comprising receiving an input command signal from the computer system and providing an output command signal to the DDR memory circuits of the first number of ranks.
21. The method of claim 20, further comprising responding at least in part to the received bank address signals and the received second number of DDR chip-select signals by selecting at least one rank of the first number of ranks and transmitting the output command signal to the DDR memory circuits of the selected at least one rank of the first number of ranks.
22. The method of claim 18, wherein selectively isolating a load of the DDR memory circuits of the at least one rank from the computer system comprises presenting a smaller load to the computer system.
23. The method of claim 18, further comprising selectively isolating a data signal line of the DDR memory circuits of the first number of ranks from the computer system.
24. The method of claim 18, wherein the memory module has attributes and the method further comprises storing data accessible to the computer system, wherein the data characterizes the memory module as having attributes that are different from the attributes of the memory module.
25. The method of claim 24, wherein the attributes are selected from a group consisting of: a number of row addresses, a number of column addresses, a number of DDR memory circuits, a data width of the DDR memory circuits, a memory density per DDR memory circuit, a number of ranks, and a memory density per rank.
The present application is a continuation of U.S. Pat. Appl. No. 12/629,827, filed Dec. 2, 2009, which is a continuation of U.S. patent application Ser. No. 12/408,652, filed Mar. 20, 2009, which is a continuation of U.S. patent application Ser. No. 11/335,875, filed Jan. 19, 2006, which claims the benefit of U.S. Provisional Appl. No. 60/645,087, filed Jan. 19, 2005 and which is a continuation-in-part of U.S. patent application Ser. No. 11/173,175, filed Jul. 1, 2005, which claims the benefit of U.S. Provisional Appl. No. 60/588,244, filed Jul. 15, 2004 and which is a continuation-in-part of U.S. patent application Ser. No. 11/075,395, filed Mar. 7, 2005, which claims the benefit of U.S. Provisional Appl. No. 60/550,668, filed Mar. 5, 2004, U.S. Provisional Appl. No. 60/575,595, filed May 28, 2004, and U.S. Provisional Appl. No. 60/590,038, filed Jul. 21, 2004. U.S. patent application Ser. Nos. 12/629,827, 12/408,652, 11/335,875, 11/173,175, and 11/075,395 and U.S. Provisional Appl. Nos. 60/550,668, 60/575,595, 60/590,038, 60/588,244, and 60/645,087 are each incorporated in their entirety by reference herein.
//========================== declarations reg rasN_R, casN_R, weN_R; wire actv_cmd_R, pch_cmd_R, pch_all_cmd_R, ap_xfr_cmd_R_R; wire xfr_cmd_R,mrs_cmd,rd_cmd_R; //- - - - - - - - - - - - - - - - - - - - - - - - - DDR 2 FET reg brs0N_R; // registered chip sel reg brs1N_R; // registered chip sel reg brs2N_R; // registered chip sel reg brs3N_R; // registered chip sel wire sel; wire sel_01; wire sel_23; wire rd_Rl; wire wr_cmd_R,wr_Rl; reg rd_R2,rd_R3,rd_R4,rd_R5; reg wr_R2,wr_R3,wr_R4,wr_R5; reg enfetl,enfet2,enfet3,enfet4,enfet5,enfet6; wire wr_01_Rl,wr_23_Rl; reg wr_01_R2,wr_01_R3,wr_01_R4; reg wr_23_R2,wr_23_R3,wr_23_R4; wire rodt0_a,rodt0_b; //========================== logic always @(posedge clk_in) begin brs0N_R <= brs0_in_N; // cs0 brs1N_R <= brs1_in_N; // cs1 brs2N_R <= brs2_in_N; // cs2 brs3N_R <= brs3_in_N; // cs3 rasN_R <= brras_in_N ; casN_R <= brcas_in_N ; weN_R <= bwe_in_N ; end assign sel = ~brs0N_R | ~brs1N_R | ~brs2N_R | ~brs3N_R ; assign sel_01 = ~brs0N_R | ~brs1N_R ; assign sel_23 = ~brs2N_R | ~brs3N_R ; assign actv_cmd_R = !rasN_R & casN_R & weN_R; // activate cmd assign pch_cmd_R = !rasN_R & casN_R & !weN_R ;// pchg cmd assign xfr_cmd_R = rasN_R & !casN_R; // xfr cmd assign mrs_cmd = !rasN_R & !casN_R & !weN_R ; // md reg set cmd assign rd_cmd_R = rasN_R & !casN_R & weN_R ; // read cmd assign wr_cmd_R = rasN_R & !casN_R & !weN_R ; // write cmd //------------------------------------- assign rd_R1 = sel & rd_cmd_R; // rd cmd cyc 1 assign wr_R1 = sel & wr_cmd_R; // wr cmd cyc 1 //---------------------------------------- always @(posedge clk_in) begin rd_R2 <= rd_R1 ; rd_R3 <= rd_R2; rd_R4 <= rd_R3; rd_R5 <= rd_R4; // rd0_o_R6 <= rd0_o_R5; wr_R2 <= wr_R1 ; wr_R3 <= wr_R2; wr_R4 <= wr_R3; wr_R5 <= wr_R4; end //---------------------------------------- assign wr_01_R1 = sel_01 & wr_cmd_R; // wr cmd cyc 1 for cs 2 & cs3 assign wr_23_R1 = sel_23 & wr_cmd_R; // wr cmd cyc 1 for cs 2 & cs3 always @(posedge clk_in) begin wr_01_R2 <= wr_01_R1 ; wr_01_R3 <= wr_01_R2; wr_01_R4 <= wr_01_R3 ; wr_23_R2 <= wr_23_R1 ; wr_23_R3 <= wr_23_R2; wr_23_R4 <= wr_23_R3; end assign rodt0_ab = (rodt0) // odt cmd from sys | (wr_23_R1) // wr 1st cyc to other rnks (assume single dimm per channel) | (wr_23_R2) // wr 2nd cyc to other rnks (assume single dimm per channel) | (wr_23_R3) // wr 3rd cyc to other rnks (assume single dimm per channel) ; assign rodt1_ab = (rodt1) // odt cmd from sys | (wr_01_R1) // wr 1st cyc to other rnks (assume single dimm per channel) | (wr_01_R2) // wr 2nd cyc to other rnks (assume single dimm per channel) | (wr_01_R3) // wr 3rd cyc to other rnks (assume single dimm per channel) ; //---------------------------------------- always @(posedge clk_in) begin if ( | (rd_R2) // pre-am rd | (rd_R3) // 1st cyc of rd brst (c13) | (rd_R4) // 2nd cyc of rd brst (c13) | (wr_R1) // pre-am wr | (wr_R2) // wr brst 1st cyc | (wr_R3) // wr brst 2nd cyc ) begin enfet1 <= 1′b1; // enable fet enfet2 <= 1′b1; // enable fet enfet3 <= 1′b1; // enable fet enfet4 <= 1′b1; // enable fet enfet5 <= 1′b1; // enable fet enfet6 <= 1′b1; // enable fet end else begin enfet1 <= 1′b0; // disable fet enfet2 <= 1′b0; // disable fet enfet3 <= 1′b0; // disable fet enfet4 <= 1′b0; // disable fet enfet5 <= 1′b0; // disable fet enfet6 <= 1′b0; // disable fet end end Back-to-Back Adjacent Read Commands
In certain embodiments, the computer system is configured for a number of ranks per memory module which is smaller than the number of ranks in which the memory devices 30 of the memory module 10 are arranged. In certain such embodiments, the computer system is configured for two ranks of memory per memory module (providing two chip-select signals CS0, CS1) and the plurality of memory modules 30 of the memory module 10 are arranged in four ranks, as schematically illustrated by FIG. 9A. In certain other such embodiments, the computer system is configured for one rank of memory per memory module (providing one chip-select signal CS( ) and the plurality of memory modules 30 of the memory module 10 are arranged in two ranks, as schematically illustrated by FIG. 9B.
4. Command involves a number of command signals that define operations such
as refresh, precharge, and other operations.
Number of column address bits 11
for ��4� configuration
Number of column address bits 10
for ��8� configuration
Number of column address bits 9
for ��16� configuration
rsON_R <= rs0_M_N; // cs0
; // and reg set cmd
assign pre_cyc2_enfet = (wr_cmd_cyc1 & acs_cyc1 &cl3) // wr brst cl3 preamble
acs_cyc2 <= acs_cyc 1 ; // cs active
assign ens_fet2b = dqs_cyc_b | dqs−ncyc_b ;
1_al3_00 <= al3_r ;
1_al3_01 <= al3_r ;
1_al3_10 <= al3_r ;
1_al3_11 <= al3_r ;
| ( rasN_R & ~1_al3_00 & ~bnk1_R & ~bnk0_R & cas_i)
| ( rasN_R & ~1_al3_01 & ~bnk1_R & bnk0_R & cas_i)
| ( rasN_R & ~1_al3_10 & bnk1_R & ~bnk0_R & cas_i)
| ( rasN_R & ~1_al3_11 & bnk1_R & bnk0_R & cas_i)
| ( rasN_R & 1_al3_00 & ~bnk1_R & ~bnk0_R & cas_i)
| ( rasN_R & 1_al3_01 & ~bnk1_R & bnk0_R & cas_i)
| ( rasN_R & 1_al3_10 & bnk1_R & ~bnk0_R & cas_i)
| ( rasN_R & 1_al3_11 & bnk1_R & bnk0_R & cas_i)
assign rd0_o_R1 = rasN_R & cas0_o & weN_R & ~rs0N_R; // mk0 rd cmd cyc
assign rd1_o_R1 = rasN_R & cas1_o & weN_R & ~rs0N_R; // mkl rd cmd cyc
assign wr0_o_R1 = rasN_R & cas0_o & ~weN_R & ~rs0N_R; // mk0 wr cmd cyc
assign wr1_o_R1 = rasN_R & cas1_o & ~weN_R & ~rs0N_R ; // mk1 wr cmd cyc
| (wr1_o_R2 | wr1_o_R2 | wr1_o_R3 | wr1_o_R4 // rank 1 (chgef9)
en_fet_b <= 1′b1 ; //
FIG. 17B schematically illustrates exemplary current-limiting resistors 430, 440 in conjunction with the impedances of the memory devices 410, 420. During an exemplary portion of a data read operation, the memory controller 510 is in a high-impedance condition, the first memory device 410 drives the first DQS pin 412 high (e.g., 2.7 volts), and the second memory device 420 drives the second DQS pin 422 low (e.g., 0 volts). The amount of time for which this condition occurs is approximated by the time between t2 and t3 of FIG. 13, which in certain embodiments is approximately twice the tDQSQ (data strobe edge to output data edge skew time, e.g., approximately 0.8 nanoseconds). At least a portion of this time in certain embodiments is caused by simultaneous switching output (S SO) effects.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4368515May 7, 1981Jan 11, 1983Atari, Inc.Bank switchable memory systemUS4392212Nov 12, 1980Jul 5, 1983Fujitsu LimitedSemiconductor memory device with decoder for chip selection/write inUS4633429Dec 27, 1982Dec 30, 1986Motorola, Inc.Partial memory selection using a programmable decoderUS4670748Aug 9, 1985Jun 2, 1987Harris CorporationProgrammable chip select decoderUS4866603Jan 20, 1988Sep 12, 1989Fujitsu LimitedMemory control system using a single access request for doubleword data transfers from both odd and even memory banksUS4958322Jul 6, 1989Sep 18, 1990Mitsubishi Denki Kabushiki KaishaSemiconductor pseudo memory moduleUS4961172Aug 11, 1988Oct 2, 1990Waferscale Integration, Inc.Decoder for a memory address busUS4980850May 14, 1987Dec 25, 1990Digital Equipment CorporationAutomatic sizing memory system with multiplexed configuration signals at memory modulesUS5247643Jan 8, 1991Sep 21, 1993Ast Research, Inc.Memory control circuit for optimizing copy back/line fill operation in a copy back cache systemUS5345412Jul 17, 1992Sep 6, 1994Mitsubishi Denki Kabushiki KaishaMemory IC and memory device capable of expansion of storage capacityUS5426753Apr 25, 1994Jun 20, 1995Gold Star Co., Ltd.Memory decoding system for portable data terminalUS5483497Jul 19, 1994Jan 9, 1996Fujitsu LimitedSemiconductor memory having a plurality of banks usable in a plurality of bank configurationsUS5495435Nov 14, 1994Feb 27, 1996Nec CorporationSynchronous DRAM memory moduleUS5581498Oct 20, 1994Dec 3, 1996Irvine Sensors CorporationFor use in an electronic host systemUS5590071Nov 16, 1995Dec 31, 1996International Business Machines CorporationMethod and apparatus for emulating a high capacity DRAMUS5699542Sep 30, 1994Dec 16, 1997Intel CorporationAddress space manipulation in a processorUS5702984Nov 14, 1996Dec 30, 1997International Business Machines CorporationIntegrated mulitchip memory module, structure and fabricationUS5703826Mar 18, 1996Dec 30, 1997Micron Technology, Inc.Video random access memory chip configured to transfer data in response to an internal write signalUS5745914Dec 20, 1996Apr 28, 1998International Business Machines CorporationTechnique for converting system signals from one address configuration to a different address configurationUS5802395Jul 8, 1996Sep 1, 1998International Business Machines CorporationHigh density memory modules with improved data bus performanceUS5805520Apr 25, 1997Sep 8, 1998Hewlett-Packard CompanyIntegrated circuit address reconfigurabilityUS5822251Sep 29, 1997Oct 13, 1998Bit Microsystems, Inc.Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllersUS5926827Feb 9, 1996Jul 20, 1999International Business Machines Corp.High density SIMM or DIMM with RAS address re-mappingUS5959930Feb 25, 1998Sep 28, 1999Mitsubishi Denki Kabushiki KaishaMulti-bank synchronous semiconductor memory deviceUS5963464Feb 26, 1998Oct 5, 1999International Business Machines CorporationStackable memory cardUS5966736Mar 7, 1997Oct 12, 1999Advanced Micro Devices, Inc.Multiplexing DRAM control signals and chip select on a processorUS6018787Jan 2, 1998Jan 25, 2000Canon Kabushiki KaishaSystem for generating chip select signals based on coded and uncoded address signalsUS6044032Dec 3, 1998Mar 28, 2000Micron Technology, Inc.Addressing scheme for a double data rate SDRAMUS6070217May 12, 1998May 30, 2000International Business Machines CorporationHigh density memory module with in-line bus switches being enabled in response to read/write selection state of connected RAM banks to improve data bus performanceUS6070227Oct 31, 1997May 30, 2000Hewlett-Packard CompanyMain memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organizationUS6097652Aug 11, 1999Aug 1, 2000Samsung Electronics Co., Ltd.Integrated circuit memory devices including circuits and methods for discharging isolation control lines into a reference voltageUS6108745Oct 31, 1997Aug 22, 2000Hewlett-Packard CompanyFast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemesUS6134638Aug 13, 1997Oct 17, 2000Compaq Computer CorporationMemory controller supporting DRAM circuits with different operating speedsUS6151271Jan 22, 1999Nov 21, 2000Samsung Electronics Co., Ltd.Integrated circuit memory devices having data selection circuits therein which are compatible with single and dual rate mode operation and methods of operating sameUS6154418Feb 14, 2000Nov 28, 2000Micron Technology, Inc.Write scheme for a double data rate SDRAMUS6154419Mar 13, 2000Nov 28, 2000Ati Technologies, Inc.Method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memoryUS6185654Jul 17, 1998Feb 6, 2001Compaq Computer CorporationPhantom resource memory address mapping systemUS6209074Apr 28, 1998Mar 27, 2001International Business Machines CorporationAddress re-mapping for memory module using presence detect dataUS6226709Oct 24, 1997May 1, 2001Compaq Computer CorporationMemory refresh control systemUS6226736Mar 10, 1997May 1, 2001Philips Semiconductors, Inc.Microprocessor configuration arrangement for selecting an external bus widthUS6233650Apr 1, 1998May 15, 2001Intel CorporationUsing FET switches for large memory arraysUS6247088May 8, 1998Jun 12, 2001Lexmark International, Inc.Bridgeless embedded PCI computer system using syncronous dynamic ram architectureUS6317352Sep 18, 2000Nov 13, 2001Intel CorporationApparatus for implementing a buffered daisy chain connection between a memory controller and memory modulesUS6400637Apr 20, 1999Jun 4, 2002Matsushita Electric Industrial Co., Ltd.Semiconductor memory deviceUS6408356Nov 16, 1999Jun 18, 2002International Business Machines CorporationApparatus and method for modifying signals from a CPU to a memory cardUS6414868Jun 7, 1999Jul 2, 2002Sun Microsystems, Inc.Memory expansion module including multiple memory banks and a bank control circuitUS6415374Mar 16, 2000Jul 2, 2002Mosel Vitelic, Inc.System and method for supporting sequential burst counts in double data rate (DDR) synchronous dynamic random access memories (SDRAM)US6446158May 17, 2000Sep 3, 2002Chris KarabatsosMemory system using FET switches to select memory banksUS6446184Jan 30, 2001Sep 3, 2002International Business Machines CorporationAddress re-mapping for memory module using presence detect dataUS6453381Dec 2, 1999Sep 17, 2002Etron Technology, Inc.DDR DRAM data coherence schemeUS6470417Jun 12, 2000Oct 22, 2002International Business Machines CorporationEmulation of next generation DRAM technologyUS6502161Jan 5, 2000Dec 31, 2002Rambus Inc.Memory system including a point-to-point linked memory subsystemUS6518794Mar 27, 2001Feb 11, 2003International Business Machines CorporationAC drive cross point adjust method and apparatusUS6526473Nov 16, 1999Feb 25, 2003Samsung Electronics Co., Ltd.Memory module system for controlling data input and output by connecting selected memory modules to a data lineUS6530007Jul 10, 2001Mar 4, 2003Compaq Information Technologies Group, L.P.Method and apparatus for supporting heterogeneous memory in computer systemsUS6530033Oct 28, 1999Mar 4, 2003Hewlett-Packard CompanyRadial arm memory bus for a high availability computer systemUS6553450Sep 18, 2000Apr 22, 2003Intel CorporationBuffer to multiply memory interfaceUS6618320Dec 11, 2002Sep 9, 2003Fujitsu LimitedSemiconductor memory deviceUS6621496Feb 26, 1999Sep 16, 2003Micron Technology, Inc.Dual mode DDR SDRAM/SGRAMUS6625081Aug 13, 2001Sep 23, 2003Micron Technology, Inc.Synchronous flash memory with virtual segment architectureUS6625687Sep 18, 2000Sep 23, 2003Intel CorporationMemory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexingUS6636935Sep 10, 2001Oct 21, 2003Rambus Inc.Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modulesUS6646949Mar 29, 2000Nov 11, 2003International Business Machines CorporationWord line driver for dynamic random access memoriesUS6658509Oct 3, 2000Dec 2, 2003Intel CorporationMulti-tier point-to-point ring memory interfaceUS6674684Jun 11, 2003Jan 6, 2004Infineon Technologies North America Corp.Multi-bank chip compatible with a controller designed for a lesser number of banks and method of operatingUS6681301Oct 2, 2001Jan 20, 2004Advanced Micro Devices, Inc.System for controlling multiple memory typesUS6683372Nov 18, 1999Jan 27, 2004Sun Microsystems, Inc.Memory expansion module with stacked memory packages and a serial storage unitUS6697888Sep 29, 2000Feb 24, 2004Intel CorporationBuffering and interleaving data transfer between a chipset and memory modulesUS6705877Jan 17, 2003Mar 16, 2004High Connection Density, Inc.Stackable memory module with variable bandwidthUS6717885Sep 18, 2002Apr 6, 2004Via Technologies, Inc.Switching circuit capable of improving memory write timing and method thereofUS6738880Jun 11, 2001May 18, 2004Via Technologies, Inc.Buffer for varying data access speed and system applying the sameUS6742098Oct 3, 2000May 25, 2004Intel CorporationDual-port buffer-to-memory interfaceUS6754797Nov 20, 2001Jun 22, 2004Leadtek Research Inc.Address converter apparatus and method to support various kinds of memory chips and application system thereofUS6785189Sep 16, 2002Aug 31, 2004Emulex Design & Manufacturing CorporationMethod and apparatus for improving noise immunity in a DDR SDRAM systemUS6788592Feb 13, 2003Sep 7, 2004Fujitsu LimitedMemory device which can change control by chip select signalUS6807125Aug 22, 2002Oct 19, 2004International Business Machines CorporationCircuit and method for reading data transfers that are sent with a source synchronous clock signalUS6807650 *Jun 3, 2002Oct 19, 2004International Business Machines CorporationDDR-II driver impedance adjustment control algorithm and interface circuitsUS6813196Jun 28, 2001Nov 2, 2004Hynix Semiconductor, Inc.High speed interface type semiconductor memory deviceUS6834014Jul 19, 2002Dec 21, 2004Samsung Electronics Co., Ltd.Semiconductor memory systems, methods, and devices for controlling active terminationUS6854042Jul 22, 2003Feb 8, 2005Chris KarabatsosHigh-speed data-rate converting and switching circuitUS6880094Jan 14, 2002Apr 12, 2005Micron Technology, Inc.Cas latency select utilizing multilevel signalingUS6889304Nov 22, 2002May 3, 2005Rambus Inc.Memory device supporting a dynamically configurable core organizationUS6912615Sep 6, 2002Jun 28, 2005Koninklijke Philips Electronics N.V.Control means for burst access controlUS6912628Apr 22, 2002Jun 28, 2005Sun Microsystems Inc.N-way set-associative external cache with standard DDR memory devicesUS6925028Mar 6, 2002Aug 2, 2005International Business Machines CorporationDRAM with multiple virtual bank architecture for random row accessUS6944694Jul 11, 2001Sep 13, 2005Micron Technology, Inc.Routability for memory devicesUS6950366Apr 30, 2003Sep 27, 2005Advanced Micro Devices, Inc.Method and system for providing a low power memory arrayUS6961281Sep 12, 2003Nov 1, 2005Sun Microsystems, Inc.Single rank memory module for use in a two-rank memory module systemUS6981089Dec 31, 2001Dec 27, 2005Intel CorporationMemory bus termination with memory unit having termination controlUS6982892May 8, 2003Jan 3, 2006Micron Technology, Inc.Apparatus and methods for a physical layout of simultaneously sub-accessible memory modulesUS6982893Feb 12, 2004Jan 3, 2006Infineon Technologies, AgMemory module having a plurality of integrated memory componentsUS6990043Mar 9, 2005Jan 24, 2006Matsushita Electric Industrial Co., Ltd.Semiconductor integrated circuit device having a common DRAM block accessed by a plurality of logic circuitsUS6996686Dec 23, 2002Feb 7, 2006Sun Microsystems, Inc.Memory subsystem including memory modules having multiple banksUS7007130Feb 13, 1998Feb 28, 2006Intel CorporationMemory system including a memory module having a memory module controller interfacing between a system memory controller and memory devices of the memory moduleUS7007175Dec 4, 2001Feb 28, 2006Via Technologies, Inc.Motherboard with reduced power consumptionUS7046538Sep 1, 2004May 16, 2006Micron Technology, Inc.Memory stacking system and methodUS7054179Oct 30, 2003May 30, 2006Hewlett-Packard Development Company, L.P.Double-high memory system compatible with termination schemes for single-high memory systemsUS7065626Jul 10, 2002Jun 20, 2006Hewlett-Packard Development Company, L.P.Method for changing computer system memory densityUS7073041Oct 30, 2002Jul 4, 2006Motorola, Inc.Virtual memory translation unit for multimedia acceleratorsUS7078793 *Aug 27, 2004Jul 18, 2006Infineon Technologies AgSemiconductor memory moduleUS7124260 *Aug 26, 2002Oct 17, 2006Micron Technology, Inc.Modified persistent auto precharge command protocol system and method for memory devicesUS20110016250 *Apr 15, 2010Jan 20, 2011Netlist, Inc.System and method utilizing distributed byte-wise buffers on a memory moduleUS20110016269 *Jul 16, 2009Jan 20, 2011Hyun LeeSystem and method of increasing addressable memory space on a memory boardUSRE36229Nov 20, 1995Jun 15, 1999Staktek CorporationSimulcast standard multichip memory addressing system* Cited by examinerNon-Patent CitationsReference1"64 & 72 Pin Zip/Simm Sram Module", JEDEC, Standard No. 21-C, www.jedec.com/download/search/4-04-01.pdf, Jun. 1997 pp. 4.4.1-1.2"Bank Striping of Data Across Internal SDRAM Banks," IP.com, IPCOM000013697D, 2000.3"DDR SDRAM RDIMM Features," Micron Technology, Inc., 2002.4"Distributed Memory Mapping," IP.com, IPCOM000014788D, 2000.5"Information Huawei or FPGA-Take Five," Electronic News, 2002, p. 24.6"Method for a high-performance DRAM address mapping mechanism," IP.com, IPCOM000008164D, 2002.7"Method for memory probing on a multiple-DIMM bus," IP.com, IPCOM000019063D, 2003.8"Method for multiple device interface testing using a single device," IP.com, IPCOM000010054D, 2002.9"PC2100 and PC1600 DDR SDRAM Registered DIMM Design Specification" JEDEC, Standard No. 21-C, Revision 1-3, Jan. 2002, pp. 4.20.4-1.10"Quad Band Memory (QBM(TM)): DDR 200/266/333 devices producing DDR 400/533/667," Platform Conference, Jan. 23-24, 2002.11"Quad Band Memory (QBMA(TM)): DDR200/266/333 devices producing DDR400/533/667" (the "QBMA Reference"), published by the QBMA Alliance, Platform Conference, San Jose, California, Jan. 23-24, 2002.12"64 & 72 Pin Zip/Simm Sram Module", JEDEC, Standard No. 21-C, www.jedec.com/download/search/4�04�01.pdf, Jun. 1997 pp. 4.4.1-1.13"Elipida Memory to Speak at Intel's Memory Implementers Forum Roundtable Event", Intel Developer Forum, [Online]. Retrieved from the Internet: <URSL: http://www.elpida.com/en/news/2004/02-18.html>, (Jun. 14, 2011), 1 page.14"Quad Band Memory (QBMA�): DDR200/266/333 devices producing DDR400/533/667" (the "QBMA Reference"), published by the QBMA Alliance, Platform Conference, San Jose, California, Jan. 23-24, 2002.15"Quad Band Memory (QBM�): DDR 200/266/333 devices producing DDR 400/533/667," Platform Conference, Jan. 23-24, 2002.16Abali, B. "Memory Expansion Technology (MXT): Software Support and Performance," IBM J. Res. & Dev., vol. 45, No. 2, 2001, pp. 287-300.17Application No. 95/000,546; filed May 11, 2010; Owned by Netlist, Inc.18Application No. 95/001,337; filed Jun. 4, 2010; Owned by Netlist, Inc.19Application No. 95/001,339; filed Jun. 8, 2010; Owned by Netlist, Inc.20Application No. 95/001,381; filed Jun. 9, 2010; Owned by Netlist, Inc.21Arlington, DL Evans. "Enhancement of Memory Card Redundant Bit Usage Via Simplified Fault Alignment Exclusion," IMB Technical Disclosure Bulletin, 1987.22Arroyo et al. "Method of executing Manufacturing ROM Code Without Removing System ROMS," IP.com, IPCOM000037214D, 1989.23Barr, Michael. "Programmable Logic: What's it to Ya?," Embedded Systems Programming, Jun. 1999, pp. 75-84.24Bennayoun et al. "Input/Output Chip Select Doubler," IBM Technical Disclosure Bulletin, vol. 38, No. 04 1995, pp. 237-240.25Blum et al. "Fast Multichip Memory System With Power Select Signal," IMB Technical Disclosure Bulletin, 1979.26Carvalho, Carlos; "The Gap between Processor and Memory Speeds"; ICCA '02.27Cuppu et al. "A Performance Coparison of Contemporary DRAM Architectures," IEEE Proceedings of the 26th International Symposium on Computer Architectures, May 2-4, 1999, Atlanta, Georgia, pp. 1-12.28Cuppu et al. "Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance?," IEEE, 2001, pp. 62-71.29Cuppu et al. "High-Performance DRAMs in Workstation Environments," IEEE Transactions on Computers, vol. 50, No. 11, 2001, pp. 1133-1153.30Denneau, M. "Logic Processor for Logic Simulation Machine," IBM Technical Disclosure Bulletin, vol. 25, No. 1, 1982.31 *English Abstract for JP 10320270A retrieved from eSpacenet on Oct. 18, 2011.32 *English Machine Translation of JP 10320270A retrieved from PAJ on Oct. 18, 2011.33Fairchild Semiconductor. "DM74LS138 DM74LS139 Decoder/Demultiplexer," Fairchild Semiconductor Corporation, 2000.34Fitzgerald et al. "Chip Select Circuit for Multi-Chip RAM Modules," IP.com, IPCOM000044404D, 1984.35Freedman, Alan. "The Computer Glossary," The Complete Illustrated Dictionary, American Management Association, 2001.36Google, Inc. v. Netlist, Inc., No. 4:08-cv-04144-SBA, Netlist Inc.'s Answer to Complaint and Counterclaim (N.D. Ca. Filed Nov. 18, 2008).37Google, Inc. v. Netlist, Inc., No. C 08-04144 SBA Google Inc.'s Invalidity Contentions Pursuant to PAT. L.F. 3-3, dated Apr. 13, 2009.38Google, Inc. v. Netlist, Inc., No. C08 04144, Complaint for Declaratory Relief, (N.D. Ca Dated Aug. 29, 2008).39Gray, KS. "Fet Ram Chip Double Density Scheme," IP.com, IPCOM000043942D, 1984.40Grimes et al. "Access Rate/Availability Improvement Logic for Dynamic Memories," IBM Technical Disclosure Bulletin, Oct. 1982.41Gupta et al. "Designing and Implementing a Fast Crossbar Scheduler," IEEE Micro, 1999, pp. 20-28.42Hession et al. "Chip Select Technique for Multi Chip Decoding," IP.com, IPCOM000070404D, 1985.43Hewlett-Packard. "Memory technology evolution: an overview of system memory technologies," technology brief, 7th edition. 2003.44Hoare et al. "An 88-Way Multiprocessor Within An FPGA With Customizable Instructions," Proceedings of the 18th International Parallel and Distributed Processing Symposium, 2004.45Intel Corporation, 66/100 MHz PC SDRAM 64-Bit Non-ECC/Parity 144 Pin Unbuffered SO-DIMM Specification, Revision 1.0, Feb. 1999.46Intel Corporation, PC SDRAM Registered DIMM Design Support Document, Revision 1.2, Oct. 1998.47Jacob, Bruce L.; "Synchronous DRAM Architectures, Organizations, and Alternative Technologies". University of Maryland, Dec. 10, 2002.48JEDEC "JEDEC Standard: Double Data Rate (DDR) SDRAM Specification", JESD79C Mar. 2003.49JEDEC Standard JESD79D, "Double Data Rate (DDR) SDRAM Specification," published Feb. 2004.50JEDEC Standard No. 21-C, "PC2100 and PC1600 DDR SDRAM Registered DIMM Design Specification," Revision 1.3, Jan. 2002.51JEDEC Standard No. 21-C, 4.20.5-184 Pin. PC1600/2100 DDR SDRAM Unbuffered DIMM Design Specification, Revision 1.1, Release 11b. Published Apr. 2003.52JEDEC Standard No. 21-C, 4.20.5-184 Pin. PC2700/PC2100/PC1600 DDR SDRAM Unbuffered SO-DIMM Reference Design Specification, Revision 1.1, Release 11b, Apr. 26, 2002.53JEDEC Standard No. 21-C, 4.20-2-168 Pin, PC133 SDRAM Registered Design Specification, Revision 1.4, Release 11a, Feb. 2002.54JEDEC Standard No. 21-C, 4.20-2�168 Pin, PC133 SDRAM Registered Design Specification, Revision 1.4, Release 11a, Feb. 2002.55JEDEC Standard No. 21-C, 4.20-3-144 Pin, PC133 SDRAM Unbuffered SO-DIMM, Reference Design Specification, Revision 1.02, Release 11. Published Oct. 2003.56JEDEC Standard No. 21-C, 4.20-3�144 Pin, PC133 SDRAM Unbuffered SO-DIMM, Reference Design Specification, Revision 1.02, Release 11. Published Oct. 2003.57JEDEC Standard No. 21-C, DDR SDRAM PC2100 and PC1600 DDR SDRAM Registered DIMM Design Specification, Revision 1.3, Release 11b, Jan. 2002.58JEDEC Standard, "Definition of the SSTV16859 2.5 V 13-Bit to 26-Bit SSTL-2 Registered Buffer for Stacked DDR DIMM Applications," JESD82-4B, May 2003.59JEDEC Standard, "Definition of the SSTV16859 2.5 V 13-Bit to 26-Bit SSTL�2 Registered Buffer for Stacked DDR DIMM Applications," JESD82-4B, May 2003.60Jin et al. "Embedded Memory in System-On-Chip Design: Architecture and Prototype Implementation," CCECE, 2003, pp. 141-146.61Jin et al. "Prototype Implementation and Evaluation of a Multibank Embedded Memory Archtecture in Programmable Logic," IEEE, 2003, pp. 13-16.62Kane et al. "Read Only Store Memory Extension," IP.com, IPCOM000082845D, 1975.63Karabatsos, C., "Quad Band Memory (QBM) Technology", Kentron Technologies, Inc., Apr. 2001, pp. 1-5.64Kellog, Mark; "PC133: SDRAM Main Memory Performance Reaches New Heights"; IBM Microelectronics, 1999.65Keltcher et al.; "The AMD Opteron Processor for Multiprocessor Servers"; IEEE Computer Society.66Kirihata et al.; "A 390-mm, 16-Bank, 1-Gb DDR SDRAM with Hybrid Bitline Architecture"; IEEE Journal of Solid-State Circuits, vol. 34, No. 11, Nov. 1999.67Kornaros et al. "A Fully-Programmable Memory Management System Optimizing Queue Handling at Multi Gigabit Rates," DAC, 2003, pp. 54-59.68Lee et al. "A banked-promotion translation lookaside buffer system," Journal of Systems Architecture, vol. 47, 2002, pp. 1065-1078.69Lee et al. "An on-chip cache compression technique to reduce decompression overhead and design complexity." Journal of Systems Architecture, vol. 46, 2000, pp. 1365-1382.70Letter from G. Hopkins Guy III, Orrick, Herrington & Sutcliffe LLP, to R. Scott Oliver, Morrison & Foerster, (Apr. 14, 2009).71Lin et al. "Designing a Modern Memory Hierarchy with Hardware Prefetching," IEEE Transactions on Computers, vol. 50, No. 11, 2001, pp. 1202-1217.72Luthra et al. "Interface Synthesis Using Memory Mapping for an FPGA Platform," Proceedings of the 21st International Conference on Computer Design, 2003.73Matick et al. "Read-Select Capability for Static Random-Access Memory," IMB Technical Disclosure Bulletin, 1985, pp. 6640-6642.74Matick, RE. "Logic and Decoder Arrangement for Controlling Spill/Wrap Boundaries of a Bit-Addressable Memory Decoder," IMB Technical Disclosure Bulletin, 1984.75MetaRAM, Inc. v. Netlist, Inc. No. 3:09-cv-01309-VRW, MetaRAM's Reply to Netlist's Counterclaims, (N.D. Ca. Filed Jun. 3, 2009).76MetaRAM, Inc. v. Netlist, Inc., No. 3:09-cv-01309-VRW, Netlist's Answer to Complaint and Counterclaims, (N.D. Ca, filed May 11, 2009).77MetaRAM, Inc. v. Netlist, Inc., No. C09 01309, Complaint for Patent Infringement, (N.D. Ca. Filed Mar. 25, 2009).78Meyers et al. "Use of Partially Good Memory Chips," IP.com, IPCOM000066246D, 1979.79Micron "DDR SDRAM RDIMM, MT36VDDF12872-1GB, MT36VDDF25672-2GB," 2002 Micron Technology, Inc. 20 pages.80Micron "DDR2 SCRAM Registered DIMM (RDIMM)," 2003 Micron Technology, Inc. 18 pages.81Micron "Synchronous DRAM Module MT18LSDT472," 1998, Micron Technology, Inc., 17 pages.82Micron Technical Note,"Decoupling Capacitor Calculations for a DDR Memory Channel," 2004, 3 pages.83Miles J. Murdocca et al., "Principles of Computer Architecture" , Prentice Hall, 2000, pp. 249-251.84Netlist, Inc. v MetaRAM, Inc., No. 09-165-GMS, MetaRAM, Inc.'s Answer and Affirmative Defenses to Plaintiff's Complaint, dated Apr. 20, 2009.85Netlist, Inc. v. MetaRAM, Inc., No. 1:09-ccv-00165-GMS, Complaint for Patent Infringement, (D. Del. Filed Mar. 12, 2009).86Ofek et al. "Partial Two Way Mapping Technique," IMB Technical Disclosure Bulletin, 1969.87Paldan, David. "Programmable Memory Address Decoding for Microprocessor Memory Device," IP.com, IPCOM000005486D, 1983.88PC133 SDRAM Registered DIMM Design Specification, Revision 1.1, Aug. 1999, 62 pages.89Pellinger et al. "Dual Addressable Memory," IP.com, IPCOM000068610D, 1978.90Plotnick et al. "Shuffle Your Chips for Better Performance," PC Week, 1998, p. 90.91Portion of Request for Inter Partes Reexamination of U.S. Patent No. 7,289,386, corresponding to Reexam Application No. 95/000,577, in 184 pages.92Portion of Request for Inter Partes Reexamination of U.S. Patent No. 7,619,912, corresponding to Reexam Application No. 95/000,578, in 66 pages.93Portion of Request for Inter Partes Reexamination of U.S. Patent No. 7,619,912, corresponding to Reexam Application No. 95/000,579, in 32 pages.94Request for Inter Partes Reexamination; Reexam App. No. 95/000,546 for U.S. Pat. No. 7,289,386 filed May 11, 2010; Owned by Netlist, Inc. and Its Entire Prosecution History.95Request for Inter Partes Reexamination; Reexam App. No. 95/000,577 for U.S. Pat. No. 7,289,386 filed Oct. 20, 2010.96Request for Inter Partes Reexamination; Reexam App. No. 95/000,577 for U.S. Pat. No. 7,289,386 filed Oct. 20, 2010; Owned by Netlist, Inc. and Its Entire Prosecution History.97Request for Inter Partes Reexamination; Reexam App. No. 95/000,578 for U.S. Pat. No. 7,619,912 filed Oct. 20, 2010.98Request for Inter Partes Reexamination; Reexam App. No. 95/000,578 for U.S. Pat. No. 7,619,912 filed Oct. 20, 2010; Owned by Netlist, Inc. and Its Entire Prosecution History.99Request for Inter Partes Reexamination; Reexam App. No. 95/000,579 for U.S. Pat. No. 7,619,912 filed Oct. 20, 2010; Owned by Netlist, Inc. and Its Entire Prosecution History.100Request for Inter Partes Reexamination; Reexam App. No. 95/000,579 for U.S. Pat. No. 7,619,912 filed Oct. 21, 2010.101Request for Inter Partes Reexamination; Reexam App. No. 95/001,337 for U.S. Pat. No. 7,636,274; filed Jun. 4, 2010; Owned by Netlist, Inc. and Its Entire Prosecution History.102Request for Inter Partes Reexamination; Reexam App. No. 95/001,338; for U.S. Pat. No. 7532537; filed Apr. 19, 2010; Owned by Netlist, Inc. and Its Entire Prosecution History.103Request for Inter Partes Reexamination; Reexam App. No. 95/001,381 for U.S. Pat. No. 7,532,537; filed Jun. 9, 2010; Owned by Netlist, Inc. and Its Entire Prosecution History.104Request for Inter Partes Reexamination; Reexam App. No. 95/001,758 for U.S. Pat. No. 7,864,627; filed Sep. 15, 2011; Owned by Netlist, Inc. And Its Entire Prosecution History.105Request for Inter Partes Reexamnation; Reexam App. No. 95/001,339 for U.S. Pat. No. 7619912; filed Jun. 8, 2010; Owned by Netlist, Inc. and Its Entire Prosecution History.106Schubert et al. "Accelerating system integration by enhancing hardware, firmware, and co-simulation," IBM J. Res. & Dev, vol. 48, No. 3/4, May/Jul. 2004, pp. 569-581.107Skelton, MH. "Program Controlled Paging Scheme for Memory Expansion," IP.com. IPCOM000050954D, 1982.108Slegel et al. "IBM's S/390 G5 Microprocessor Design," IEEE Micro, 1999, pp. 12-23.109Smith, BA. "Chip Select Decoder Circuit," IP.com, IPCOM000063400D, 1985.110Stelzer, KC. "Planar Memory Boundary Registers with Remap Feature," IMB Technical Disclosure Bulletin, 1993.111Sunaga et al. "An Enable Signal Circuit for Multiple Small Banks," IP.com, IPCOM000015887D, 2002.112Sunaga et al. "Continuou RAS Access Method in Multiple-bank DRAM Chip," IP.com, IPCOM000123375D, 1998.113Texas Instruments, "TM2SR72EPN 2097152 By 72-Bit, TM4SRT2EPN 4194304 by 72-Bit, Synchronous Dynamic Ram Modules," 1997, 15 pages.114Toal et al. "A 32-Bit SoPC Implementation of a P5." Proceedings of the Eighth IEEE International Symposium on Computers and Communications, 2003, pp. 1530-1346.115Tudruj, Marek. "Dynamically reconfigurable heterogenous multi-processor systems with transputer-controlled communication," Journal of Systems Architecture, vol. 43, 1997, pp. 27-32.116U.S. Appl. No. 12/422,853, filed Apr. 13, 2009; Owned by Netlist, Inc.117U.S. Appl. No. 12/422,925, filed Apr. 13, 2009; Owned by Netlist, Inc.118U.S. Appl. No. 12/774,632, filed May 5, 2010; Owned by Netlist, Inc.119U.S. Appl. No. 12/815,339, filed Jun. 14, 2010; Owned by Netlist, Inc.120U.S. Appl. No. 12/912,623, filed Oct. 26, 2010; Owned by Netlist, Inc.121U.S. Appl. No. 12/954,492, filed Nov. 24, 2010; and its entire prosecution history.122U.S. Appl. No. 12/954,492, filed Nov. 24, 2010; Owned by Netlist, Inc.123U.S. Appl. No. 12/955,711, filed Nov. 29, 2010; Owned by Netlist, Inc.124U.S. Appl. No. 13/032,470, filed Feb. 22, 2011; and its entire prosecution history.125U.S. Appl. No. 13/154,172, filed Jun. 6, 2011; and its entire prosecution history.126U.S. District Court Central District of California, Case No. CV09 06900, Netlist, Inc. vs. Inphi Corporation, Complaint for Patent Infringement, filed Sep. 22, 2009 in 10 pages.127U.S. District Court Central District of California, Case No. CV09 06900, Netlist, Inc. vs. Inphi Corporation, Defendant Inphi Corporation's Answer to Plaintiffs Complaint for Patent Infringement, filed Nov. 12, 2009 in 6 pages.128U.S. District Court Central District of California, Case No. CV09 06900, Netlist, Inc. vs. Inphi Corporation, Defendant Inphi Corporation's Answer to Plaintiff's First Amended Complaint for Patent Infringement, filed Feb. 11, 2010 in 9 pages.129U.S. District Court Central District of California, Case No. CV09 06900, Netlist, Inc. vs. Inphi Corporation, Defendant Inphi Corporation's Notice of Motion and Motion for Stay Pending Reexaminations and Interference Proceeding Regarding the Patents-In-Suit; Memorandum of Points and Authorities in Support Thereof, filed Apr. 21, 2010 in 28 pages.130U.S. District Court Central District of California, Case No. CV09 06900, Netlist, Inc. vs. Inphi Corporation, Plaintiff Netlist Inc's Opposition to Defendant Inphi Corporation's Motion for Stay Pending Reexaminations and Interference Proceedings Regarding the Patents-In-Suit, filed May 3, 2010 in 23 pages.131U.S. District Court Central District of California, Case No. CV09 06900, Netlist, Inc. vs. Inphi Corporation, Plaintiff Netlist, Inc's First Amended Complaint for Patent Infringement, filed Dec. 23, 2009 in 8 pages.132U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., [Redacted] Google Inc.'s Responsive Claim Construction Brief, filed Aug. 25, 2009 in 30 pages.133U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Amended Exhibit A to Joint Claim Construction and Prehearing Statement, filed Oct. 28, 2009 in 1 page.134U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Appendix 1 to Google's Responsive Claim Construction Brief, filed Aug. 25, 2009 in 4 pages.135U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Attachment 1 to Exhibit B to Joint Claim Construction and Prehearing Statement, filed Jun. 12, 2009 in 7 pages.136U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Attachment 2 to Exhibit B to Joint Claim Construction and Prehearing Statement, filed Jun. 12, 2009 in 12 pages.137U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Complaint for Declaratory Relief, filed Aug. 29, 2008 in 49 pages.138U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Defendant Netlist, Inc.'s Opening Claim Construction Brief, filed Jul. 29, 2009 in 21 pages.139U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Defendant Netlist, Inc.'s Opposition to Google Inc's Motion for Summary Judgment of Invalidity, filed Jul. 6, 2010 in 13 pages.140U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Defendant Netlist, Inc's Claim Construction Reply Brief, filed Sep. 22, 2009 in 19 pages.141U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Exhibit A to Joint Claim Construction and Prehearing Statement, filed Jun. 12, 2009 in 2 pages.142U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Exhibit B to Joint Claim Construction and Prehearing Statement, filed Jun. 12, 2009 in 36 pages.143U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Joint Claim Construction and Prehearing Statement, filed Jun. 12, 2009 in 5 pages.144U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Netlist, Inc.'s Answer to Complaint and Counterclaims, filed Nov. 18, 2008 in 9 pages.145U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Order Re Claim Construction, filed Nov. 16, 2009 in 1 page.146U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Plaintiff Google's Reply to Counterclaims, filed Dec. 8, 2008 in 4 pages.147U.S. District Court Northern District of California, Case No. CV08 04144, Google Inc. v. Netlist, Inc., Stipulation Re: Additional Agreed-Upon Claim Constructions, filed Oct. 28, 2009 in 3 pages.148U.S. District Court Northern District of California, Case No. CV09 05718, Netlist, Inc. vs. Google, Inc., Complaint for Patent Infringement, filed Dec. 4, 2009 in 47 pages.149U.S. District Court Northern District of California, Case No. CV09 05718, Netlist, Inc. vs. Google, Inc., Defendant Google Inc's Responsive Claim Construction Brief, filed Aug. 4, 2010 in 27 pages.150U.S. District Court Northern District of California, Case No. CV09 05718, Netlist, Inc. vs. Google, Inc., Exhibit A to Joint Claim Construction and Prehearing Statement under Patent L.R. 4-3, filed Jun. 25, 2010 in 2 pages.151U.S. District Court Northern District of California, Case No. CV09 05718, Netlist, Inc. vs. Google, Inc., Exhibit B to Joint Claim Construction and Prehearing Statement under Patent L.R. 4-3, filed Jun. 25, 2010 in 23 pages.152U.S. District Court Northern District of California, Case No. CV09 05718, Netlist, Inc. vs. Google, Inc., Google's Answer to Plaintiff's Complaint for Patent Infringement; and Assertion of Counterclaims, filed Feb. 12, 2010 in 13 pages.153U.S. District Court Northern District of California, Case No. CV09 05718, Netlist, Inc. vs. Google, Inc., Joint Claim Construction and Prehearing Statement Under Patent Local Rule 4-3, filed Jun. 25, 2010 in 5 pages.154U.S. District Court Northern District of California, Case No. CV09 05718, Netlist, Inc. vs. Google, Inc., Plaintiff Netlist, Inc.'s Reply Claim Construction Brief, filed Aug. 16, 2010 in 17 pages.155U.S. District Court Northern District of California, Case No. CV09 05718, Netlist, Inc. vs. Google, Inc., Plaintiff Netlist, Inc.'s Reply to Defendant Google Inc.'s Counterclaim, filed Mar. 8, 2010 in 11 pages.156U.S. District Court Northern District of California, Case No. CV09 05718, Netlist, Inc. vs. Google, Inc., Plaintiff Netlist, Inc's Opening Claim Construction Brief, filed Jul. 16, 2010 in 29 pages.157US 6,438,062, 08/2002, Curtis et al. (withdrawn)158US District Court Civil Docket; Google Inc. v. Netlist Inc.; 4:08cv04144; Date filed Aug. 29, 2008.159US District Court Civil Docket; Netlist Inc. v. Google Inc.; 4:09cv5718; Date filed Dec. 4, 2009, Retrieved Sep. 1, 2010.160US District Court Civil Docket; Netlist Inc. v. Inphi Corporation; 2:09cv6900; Date filed Sep. 22, 2009.161Vogt, Pete, "Fully Buffered DIMM (FBb-DIMM) Server Memory Architecture: Capacity, Performance, Reliability, and Longevity," Intel, Feb. 18, 2004, 33 pages.162Yao, YL. High Density Memory Selection Circuit,: IP.com, IPCOM000078218D, 1972.* Cited by examinerClassifications U.S. Classification365/230.06, 365/149, 365/233.13, 365/230.03, 365/51International ClassificationG11C8/00Cooperative ClassificationG11C5/04, G06F13/00, G06F12/00European ClassificationG11C5/04Legal EventsDateCodeEventDescriptionJul 18, 2013ASAssignmentOwner name: DBD CREDIT FUNDING LLC, NEW YORKFree format text: SECURITY AGREEMENT;ASSIGNOR:NETLIST, INC.;REEL/FRAME:030830/0945Effective date: 20130718Aug 14, 2012CCCertificate of correctionRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services