Source: https://patents.justia.com/patent/10453757
Timestamp: 2020-08-14 15:37:44
Document Index: 30346313

Matched Legal Cases: ['Application No. 61', 'artz\n5854501', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10']

US Patent for Transistor channel Patent (Patent # 10,453,757 issued October 22, 2019) - Justia Patents Search
Justia Patents With Non-semiconductive Coating ThereonUS Patent for Transistor channel Patent (Patent # 10,453,757)
May 17, 2018 - Taiwan Semiconductor Manufacturing Company, Ltd.
This application is a divisional application of U.S. patent application Ser. No. 14/581,970, filed Jan. 6, 2015, which is a continuation-in-part of U.S. patent application Ser. No. 13/871,465 filed Apr. 26, 2013, entitled “A Semiconductor Device and Fabricating the Same,” which claims the benefit of Provisional Application No. 61/778,693, filed Mar. 13, 2013, the disclosures of which are hereby incorporated by reference in their entirety.
Referring to FIGS. 1 and 6, the method 100 proceeds to step 112 by forming a second gate stack 260 in the gate trench 250. The second gate stack 260 may include a dielectric layer 262 and a gate electrode layer 264. It is understood that the gate stack may include additional layers such as interfacial layers, capping layers, diffusion/barrier layers, dielectric layers, conductive layers, other suitable layers, and/or combinations thereof. For example, the dielectric 262 may include an interfacial layer (IL) and a gate dielectric layer. An exemplary IL includes silicon oxide (e.g., thermal oxide or chemical oxide) and/or silicon oxynitride (SiON). The gate dielectric layer may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material includes HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof.
providing a first wafer comprising a substrate and epitaxially growing a first semiconductor material layer over the substrate;
providing a second wafer, epitaxially growing a second semiconductor material layer on a sacrificial layer of the second wafer;
bonding the first wafer to the second wafer, wherein the bonding the first wafer to the second wafer including bonding the first semiconductor material layer to the second semiconductor material layer;
after the bonding, removing the sacrificial layer by a wet etching process;
patterning the bonded first wafer and second wafer to create a first structure and a second structure;
forming a first type of transistor in the first semiconductor material layer of the first structure wherein the forming the first type of transistor in the first semiconductor material layer includes: removing a portion of the first semiconductor material layer, forming a source/drain material in a first region defined by the removed portion, wherein the first region has a shape with a tip extending toward a channel region under a gate structure of the first type of transistor; and forming a higher concentration of a dopant of boron in the tip of the first region than a remaining portion of the first region; and
2. The method of claim 1, further comprising forming a superlattice structure in the second type of transistor, wherein the superlattice structure alternates between two different semiconductor materials wherein the alternating is in a direction that is substantially parallel to a top surface of the substrate, the two different semiconductor materials having a same type of dopant.
4. The method of claim 1, wherein bonding the first wafer to the second wafer includes applying a bonding layer by atomic layer deposition (ALD) between the first semiconductor material layer and the second semiconductor material layer.
6. The method of claim 1, wherein the forming the second type of transistor in the second semiconductor material layer includes removing a second portion of the second semiconductor material layer and forming another source/drain material in a second region defined by the removed second portion.
providing a first substrate and a first semiconductor material layer;
providing a second substrate and a second semiconductor material layer, the second semiconductor material layer different in composition than the first semiconductor material layer;
bonding the first semiconductor material layer to the second semiconductor material layer by applying a bonding layer between the first and second semiconductor material layers;
patterning the bonded first semiconductor material layer and second semiconductor material layer to create a first structure having the first semiconductor material layer and a second structure having the first semiconductor material layer, the bonding layer, and the second semiconductor material layer;
forming a first type of transistor in the first semiconductor material layer of the first structure including forming a source/drain region for the first type of transistor that has a superlattice structure that alternates between two different semiconductor materials wherein the alternating is in a direction that is substantially parallel to a top surface of the first substrate, the two different semiconductor materials having a same type of dopant; and
8. The method of claim 7, wherein the patterning the bonded first semiconductor material layer and second semiconductor material layer includes removing the second semiconductor material layer from a region including the first structure.
9. The method of claim 7, wherein the forming the source/drain region of the first type of transistor includes etching a recess in the first semiconductor material layer, wherein the recess has a profile providing a tip facing a channel region under a gate of the first type of transistor, the superlattice structure is formed in the recess.
forming a first gate structure on the first semiconductor material layer of the first stack and etching a first set of recesses in the first semiconductor material layer, wherein the etching the first set of recesses includes forming a recess defined by a first edge along a facet of a first crystalline orientation and a second edge along another facet of the first crystalline orientation, the first and second edges meeting in a vertex;
filling each of the first set of recesses and the second set of recesses with source/drain material; wherein the filling the first set of recesses includes filling each of the first set of recesses having a first dopant concentration at a center of the recess and a second dopant concentration the vertex, wherein the second dopant concentration is greater than the first dopant concentration, the first and second dopant concentrations greater than zero and wherein the first dopant concentration and the second dopant concentration are of boron.
11. The method of claim 10, wherein the filling each of the first set of recesses and the second set of recesses includes providing a first material in the first set of recesses and a second material, different than the first material in the second set of recesses.
12. The method of claim 10, wherein the filling the second set of recesses includes forming a superlattice structure in each of the second set of recesses.
13. The method of claim 10, wherein the filling of the second set of recesses includes filling the recess having a higher dopant concentration toward the vertex.
15. The method of claim 10, wherein the first crystalline orientation is (111).
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Patent Publication Number: 20180269111
Inventors: Yu-Hung Cheng (Tainan), Ching-Wei Tsai (Hsinchu), Yeur-Luen Tu (Taichung), Tung-I Lin (Tainan), Wei-Li Chen (Tainan)
Application Number: 15/982,033
Current U.S. Class: With Non-semiconductive Coating Thereon (148/33.3)
International Classification: H01L 29/267 (20060101); H01L 21/8238 (20060101); H01L 27/092 (20060101); H01L 29/78 (20060101); H01L 29/66 (20060101);