Source: http://www.google.com/patents/USRE35921?dq=7,177,838
Timestamp: 2014-08-27 11:46:48
Document Index: 604981180

Matched Legal Cases: ['Application No. 97101926', 'Application No. 97101927', 'Application No. 97101929', 'Application No. 97101930', 'Application No. 97109202', 'Application No. 97109208']

Patent USRE35921 - Dynamic video RAM incorporating single clock random port control - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn architecture for a single chip dynamic video random access memory using a single clock to operate the random port to perform refresh, memory address, and to control the internal circuitry for inputting data and addresses and for outputting data as well as modifying information in the memory circuit...http://www.google.com/patents/USRE35921?utm_source=gb-gplus-sharePatent USRE35921 - Dynamic video RAM incorporating single clock random port controlAdvanced Patent SearchPublication numberUSRE35921 EPublication typeGrantApplication numberUS 08/287,147Publication dateOct 13, 1998Filing dateAug 8, 1994Priority dateNov 29, 1988Also published asUS5142637Publication number08287147, 287147, US RE35921 E, US RE35921E, US-E-RE35921, USRE35921 E, USRE35921EInventorsRoy E. Harlin, Richard A. HerringtonOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (63), Non-Patent Citations (18), Referenced by (3), Classifications (38), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetDynamic video RAM incorporating single clock random port controlUS RE35921 EAbstract An architecture for a single chip dynamic video random access memory using a single clock to operate the random port to perform refresh, memory address, and to control the internal circuitry for inputting data and addresses and for outputting data as well as modifying information in the memory circuit chip having internal circuitry for performing drawing or replacement rule logical operations on an addressed line of stored video information In the RAM and further having the write masking circuitry for modifying selected portions of the line of stored video Information between selected START and STOP bit locations within the like.
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European App. No. 94116991.4, Mar. 8, 1996.11Journal of Electronic Engineering, (1987) No. 251, Tokyo, Japan, "Video RAM Chips Designed for Computer Graphics" by Masayoshi Nakane, Kaoru Tokushige, pp. 28-31.12 *Journal of Electronic Engineering, (1987) No. 251, Tokyo, Japan, Video RAM Chips Designed for Computer Graphics by Masayoshi Nakane, Kaoru Tokushige, pp. 28 31.13 *Motorola Semiconductor Technical Data MCM6605A, Semiconductor Data Library, vol. 7/Series A, 1975.14 *Motorola Semiconductor Technical Data MCM6616L, Semiconductor Data Library, vol. 7/Series A, 1975.15 *Motorola Semiconductor Technical Data, MCM514256A, 1988.16 *Target Specification of the Hitachi, HM53462 Multi Port DRAM Jun. 7, 1985.17Target Specification of the Hitachi, HM53462 Multi Port DRAM-Jun. 7, 1985.18 *U.S. Reissue Patent Application Serial No. 08/306,180, filed Sep. 14, 1994.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6847573 *Jun 26, 2003Jan 25, 2005Silicon7, Inc.Synchronous SRAM-compatible memory device including DRAM array with internal refreshUS8782332 *Jun 24, 2011Jul 15, 2014Mstar Semiconductor, Inc.Control method and controller for DRAMUS20120226852 *Jun 24, 2011Sep 6, 2012Mstar Semiconductor, Inc.Control method and controller for dram* Cited by examinerClassifications U.S. Classification365/189.14, 711/105, 365/189.18, 345/554, 345/519, 365/230.09, 365/230.01, 365/233.11, 711/104, 345/564, 365/233.1International ClassificationG09G5/395, G11C11/408, G09G5/39, G09G5/393, G11C7/22, G11C7/10Cooperative ClassificationG09G5/39, G11C7/22, G09G5/393, G11C7/1006, G09G2360/12, G09G5/395, G11C7/1072, G09G2360/122, G11C7/1075, G11C11/4082, G09G2360/126, G11C7/1015European ClassificationG09G5/395, G09G5/393, G11C7/10S, G11C7/10M, G11C7/10L, G11C11/408B, G11C7/22, G09G5/39, G11C7/10TLegal EventsDateCodeEventDescriptionJul 7, 1995ASAssignmentOwner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SOLBOURNE COMPUTER, INC.;REEL/FRAME:007521/0872Effective date: 19941006RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google