Source: http://www.google.com/patents/US20040001640?ie=ISO-8859-1
Timestamp: 2014-12-18 01:05:08
Document Index: 567336983

Matched Legal Cases: ['Application No. 8', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 24', 'art 24', 'art 24', 'application No. 2002']

Patent US20040001640 - Image processing circuit and image processing method that prevent problems ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn image processing circuit reduces binary data of an original image. At least one line buffer stores data of each line of the original image. At least one line buffer stores data of each line of a reduced image. An operation part performs a logical operation based on data of focused pixels of the original...http://www.google.com/patents/US20040001640?utm_source=gb-gplus-sharePatent US20040001640 - Image processing circuit and image processing method that prevent problems occurring in image reductionAdvanced Patent SearchPublication numberUS20040001640 A1Publication typeApplicationApplication numberUS 10/465,832Publication dateJan 1, 2004Filing dateJun 16, 2003Priority dateJun 26, 2002Also published asEP1377027A1, EP1377027B1, US7295714Publication number10465832, 465832, US 2004/0001640 A1, US 2004/001640 A1, US 20040001640 A1, US 20040001640A1, US 2004001640 A1, US 2004001640A1, US-A1-20040001640, US-A1-2004001640, US2004/0001640A1, US2004/001640A1, US20040001640 A1, US20040001640A1, US2004001640 A1, US2004001640A1InventorsKazumasa KoikeOriginal AssigneeKazumasa KoikeExport CitationBiBTeX, EndNote, RefManReferenced by (2), Classifications (7), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetImage processing circuit and image processing method that prevent problems occurring in image reductionUS 20040001640 A1Abstract An image processing circuit reduces binary data of an original image. At least one line buffer stores data of each line of the original image. At least one line buffer stores data of each line of a reduced image. An operation part performs a logical operation based on data of focused pixels of the original image, data of a peripheral pixel of the focused pixels, and data of peripheral pixels of a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels. Images(10) Claims(15)
What is claimed is: 1. An image processing circuit reducing binary data of an original image, comprising: at least one line buffer storing data of each line of the original image; at least one line buffer storing data of each line of a reduced image; and an operation part performing a logical operation based on data of focused pixels of the original image, data of a peripheral pixel of the focused pixels, and data of peripheral pixels of a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels. 2. The image processing circuit as claimed in claim 1, wherein, when performing a reducing operation in a main scanning direction, the operation part performs the logical operation by using data of a peripheral pixel that is adjacent in a sub-scanning direction to the focused pixels of the original image. 3. The image processing circuit as claimed in claim 1, wherein, when performing a reducing operation in a sub-scanning direction, the operation part performs the logical operation by using data of a peripheral pixel that is adjacent in a main scanning direction to the focused pixels of the original image. 4. The image processing circuit as claimed in claim 1, wherein, when performing a reducing operation in a main scanning direction, the operation part performs the logical operation by using data of a peripheral pixel that is adjacent in a sub-scanning direction to a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels. 5. The image processing circuit as claimed in claim 1, wherein, when performing a reducing operation in a sub-scanning direction, the operation part performs the logical operation by using data of a peripheral pixel that is adjacent in a main scanning direction to a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels. 6. The image processing circuit as claimed in claim 1, wherein the operation part performs a logical operation expressed by: o  ( x , y ) = inv  [ o  ( x , y - 1 ) ] � i  ( x , 2  y ) + o  ( x - 1 , y ) � inv  [ i  ( x - 1 , 2  y + 1 ) ] � i  ( x , 2  y ) + i  ( x , 2  y + 1 ) where �i� is pixel data of the original image (black=1, white=0), �o� is pixel data of the reduced image (black=1, white=0), �x� is a pixel value in a main scanning direction, and �y� is a pixel value in a sub-scanning direction. 7. The image processing circuit as claimed in claim 1, wherein the operation part performs a logical operation expressed by: o  ( x , y ) = inv  [ o  ( x - 1 , y ) ] � i  ( 2  x , y ) + o  ( x , y - 1 ) � inv  [ i  ( 2  x + 1 , y - 1 ) ] � i  ( 2  x , y ) + i  ( 2  x + 1 , y ) where �i� is pixel data of the original image (black=1, white=0), �o� is pixel data of the reduced image (black=1, white=0), �x� is a pixel value in a main scanning direction, and �y� is a pixel value in a sub-scanning direction. 8. An image processing circuit reducing binary data of an original image, comprising: first line buffer means for storing data of each line of the original image; second line buffer means for storing data of each line of a reduced image; and an operation means for performing a logical operation based on data of focused pixels of the original image, data of a peripheral pixel of the focused pixels, and data of peripheral pixels of a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels. 9. The image processing circuit as claimed in claim 8, wherein, when performing a reducing operation in a main scanning direction, the operation means performs the logical operation by using data of a peripheral pixel that is adjacent in a sub-scanning direction to the focused pixels of the original image. 10. The image processing circuit as claimed in claim 8, wherein, when performing a reducing operation in a sub-scanning direction, the operation means performs the logical operation by using data of a peripheral pixel that is adjacent in a main scanning direction to the focused pixels of the original image. 11. The image processing circuit as claimed in claim 8, wherein, when performing a reducing operation in a main scanning direction, the operation means performs the logical operation by using data of a peripheral pixel that is adjacent in a sub-scanning direction to a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels. 12. The image processing circuit as claimed in claim 8, wherein, when performing a reducing operation in a sub-scanning direction, the operation means performs the logical operation by using data of a peripheral pixel that is adjacent in a main scanning direction to a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels. 13. The image processing circuit as claimed in claim 8, wherein the operation means performs a logical operation expressed by: o  ( x , y ) = inv  [ o  ( x , y - 1 ) ] � i  ( x , 2  y ) + o  ( x - 1 , y ) � inv  [ i  ( x - 1 , 2  y + 1 ) ] � i  ( x , 2  y ) + i  ( x , 2  y + 1 ) where �i� is pixel data of the original image (black=1, white=0), �o� is pixel data of the reduced image (black=1, white=0), �x� is a pixel value in a main scanning direction, and �y� is a pixel value in a sub-scanning direction. 14. The image processing circuit as claimed in claim 8, wherein the operation means performs a logical operation expressed by: o  ( x , y ) = inv  [ o  ( x - 1 , y ) ] � i  ( 2  x , y ) + o  ( x , y - 1 ) � inv  [ i  ( 2  x + 1 , y - 1 ) ] � i  ( 2  x , y ) + i  ( 2  x + 1 , y ) where �i� is pixel data of the original image (black=1, white=0), �o� is pixel data of the reduced image (black=1, white=0), �x� is a pixel value in a main scanning direction, and �y� is a pixel value in a sub-scanning direction. 15. An image processing method of reducing binary data of an original image, comprising the steps of: storing data of each line of the original image; storing data of each line of a reduced image; and performing a logical operation based on data of focused pixels of the original image, data of a peripheral pixel of the focused pixels, and data of peripheral pixels of a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels. Description
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to image processing circuits and image processing methods for image reduction of black-and-white images in such as facsimile apparatuses, digital copying machines, image scanners, and printers that can prevent loss of thin lines and generation of solid black images and also prevent image quality degradation in inverted (rotated 180�) T-shaped images and line thickening in laid (rotated 90�) T-shaped images, which cannot be solved by conventional operations. [0003] 2. Description of the Related Art [0004] As for image processing techniques for reducing black-and-white images, generally, the following processes are carried out as the simplest processes: a simple thinning process of selecting one arbitrary line from among focused N lines and rendering the selected line as an output image, and an OR process of rendering a logical sum (OR) of all the N lines as an output image. [0005] In the simple thinning process, however, when a line to be thinned out includes a black pixel and a line including only white pixels is left, for example, a thin line in the main scanning direction is missed. On the other hand, in the OR process, it is possible to prevent a thin line in the main scanning direction from being missed. However, at the same time, if there is one black pixel in N lines, it is determined that the output image at the column position is formed by black pixels. As a result, there is a disadvantage in that the output image is more likely to be a solid black image. [0006] Therefore, as described in Japanese Laid-Open Patent Application No. 8-289137, an image reducing method of using the simple thinning process and the OR process together and selectively carrying out one of the processes in accordance with the quality of an image is known. In addition, a reducing method of selectively carrying out a thinning process according to the number of black pixels is also known. [0007] In a pixel density conversion apparatus using the above-described methods, for example, the OR process is performed on image data of character documents so as to prevent thin lines from being missed, the simple thinning process is performed on image data of photographic documents so as to prevent degradation in reproducibility of halftones, and, in the thinning process according to the number of black pixels, the number of black pixels of each line is counted and lines other than the line having the largest number of black pixels are thinned out so as to prevent thin lines from being missed. [0008] However, such processes do not solve the problem that an output image becomes a solid black image when the OR process is selected. Thus, fundamental solutions for the above-described problems are not provided. [0009] Additionally, the thinning according to the number of black pixels provides an output image of the middle-level between the simple thinning process and the OR process. Thus, the thinning according to the number of black pixels only slightly reduces loss of thin lines and production of solid black images, and does not provide the ultimate solutions. [0010] By the way, methods for compensating for the shortcomings of the OR process include methods of referring to data of a peripheral pixel that is adjacent in the sub-scanning direction to a focused pixel of a reduced image (image after reduction), when performing a reducing process in the sub-scanning direction, as shown in the following Equations 1 and 2. o(x,y)=inv[o(x,y−1)]�i(x,2y−1)+i(x,2y) Equation 1 or o(x,y)=inv[o(x,y−1)]�i(x,2y)+i(x,2y+1) Equation 2 [0011] i: pixel data of original image [0012] (black =1, white =0) [0013] o: pixel data of reduced image [0014] (black =1, white =0) [0015] x: pixel value in main scanning direction [0016] y: pixel value in sub-scanning direction [0017] Hereinafter, the reducing process of Equation 1 is referred to as a �process using conventional technique A�, and the reducing process of Equation 2 is referred to as a �process using conventional technique B�. [0018]FIGS. 1B, 1C, and 1D show the results of performing, on a horizontal-striped input image shown in FIG. 1A, a 50% reducing process by an OR operation, the process using conventional technique A (50% reducing process), and the process using conventional technique B (50% reducing process), respectively. As can be seen from FIG. 1B, a solid black image is produced in the reduction by the OR operation. In addition, as shown in FIGS. 1C and 1D, in the processes using conventional techniques A and B, a solid black image is partially produced. [0019] In addition, FIGS. 2B, 2C, and 2D show the results of performing, on an inverted T-shaped input image shown in FIG. 2A, the 50% reducing process by an OR operation, the process using conventional technique A (50% reducing process), and the process using conventional technique B (50% reducing process), respectively. As can be seen from FIGS. 2B and 2C, there is no defect (good results are obtained) in the reduction by the OR operation and the process using conventional technique A. On the other hand, as shown in FIG. 2D, in the process using conventional technique B, a blank part (missing part)(denoted by the reference numeral 100 in FIG. 2D) is partially produced. [0020] Further, FIGS. 3B, 3C, and 3D show the results of performing, on a laid T-shaped input image shown in FIG. 3A, the 50% reducing process by an OR operation, the process using conventional technique A (50% reducing process), and the process using conventional technique B (50% reducing process), respectively. As can be seen from FIGS. 3B and 3C, in the reduction by the OR operation (FIG. 3B) and the process using conventional technique A (FIG. 3C), line thickening occurs. As shown in FIG. 3E, in the process using conventional technique B, there is no defect (a good result is obtained). SUMMARY OF THE INVENTION [0021] It is a general object of the present invention to provide an improved and useful image processing circuit and image processing method in which the above-mentioned problems are eliminated. [0022] It is another and more specific object of the present invention to prevent loss of thin lines and generation of solid black images and to prevent image quality degradation in inverted T-shaped images and line thickening in laid T-shaped images, which problems cannot be solved by conventional operations. [0023] In order to achieve the above-mentioned objects, according to one aspect of the present invention, there is provided an image processing circuit reducing binary data of an original image, including: [0024] at least one line buffer storing data of each line of the original image; [0025] at least one line buffer storing data of each line of a reduced image; and [0026] an operation part performing a logical operation based on data of focused pixels of the original image, data of a peripheral pixel of the focused pixels, and data of peripheral pixels of a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels of the original image. [0027] Also, in the image processing circuit according to the present invention, when performing a reducing operation in a main scanning direction, the operation part may perform the logical operation by using data of a peripheral pixel that is adjacent in a sub-scanning direction to the focused pixels of the original image. [0028] In addition, when performing a reducing operation in the sub-scanning direction, the operation part may perform the logical operation by using data of a peripheral pixel that is adjacent in the main scanning direction to the focused pixels of the original image. [0029] Further, when performing a reducing operation in the main scanning direction, the operation part may perform the logical operation by using data of a peripheral pixel that is adjacent in a sub-scanning direction to a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels. [0030] Additionally, when performing a reducing operation in the sub-scanning direction, the operation part may perform the logical operation by using data of a peripheral pixel that is adjacent in the main scanning direction to a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels. [0031] More specifically, the operation part may perform a logical operation expressed by: o  ( x , y ) = inv  [ o  ( x , y - 1 ) ] � i  ( x , 2  y ) + o  ( x - 1 , y ) � inv  [ i  ( x - 1 , 2  y + 1 ) ] � i  ( x , 2  y ) + i  ( x , 2  y + 1 ) [0032] where �i� is pixel data of the original image (black=1, white=0), �o� is pixel data of the reduced image (black=1, white=0), �x� is a pixel value in the main scanning direction, and �y� is a pixel value in the sub-scanning direction. [0033] Additionally, the operation part may perform a logical operation expressed by: o  ( x , y ) = inv  [ o  ( x - 1 , y ) ] � i  ( 2  x , y ) + o  ( x , y - 1 ) � inv  [ i  ( 2  x + 1 , y - 1 ) ] � i  ( 2  x , y ) + i  ( 2  x + 1 , y ) [0034] where �i� is pixel data of the original image (black =1, white=0), �o� is pixel data of the reduced image (black=1, white=0), �x� is a pixel value in the main scanning direction, and �y� is a pixel value in the sub-scanning direction. [0035] Further, according to another aspect of the present invention, there is also provided an image processing method of reducing binary data of an original image, including the steps of: [0036] storing data of each line of the original image; [0037] storing data of each line of a reduced image; and [0038] performing a logical operation based on data of focused pixels of the original image, data of a peripheral pixel of the focused pixels, and data of peripheral pixels of a pixel of the reduced image, the pixel of the reduced image corresponding to the focused pixels. [0039] According to the present invention, when reducing an image, it is possible to prevent loss of thin lines and generation of solid black images and to prevent image quality degradation in inverted T-shaped images and line thickening in laid T-shaped images, which problems cannot be solved by conventional operations. [0040] Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the following drawings.
BRIEF DESCRIPTION OF THE DRAWINGS [0041]FIG. 1A is a schematic diagram showing a horizontal-striped input image; [0042]FIG. 1B is a schematic diagram showing the result of a 50% reducing process by an OR operation; [0043]FIG. 1C is a schematic diagram showing the result of a 50% reducing process using a conventional technique A; [0044]FIG. 1D is a schematic diagram showing the result of a 50% reducing process using a conventional technique B; [0045]FIG. 1E is a schematic diagram showing the result of a 50% reducing process according to the present invention; [0046]FIG. 2A is a schematic diagram showing an inverted T-shaped input image; [0047]FIG. 2B is a schematic diagram showing the result of the 50% reducing process by an OR operation; [0048]FIG. 2C is a schematic diagram showing the result of the 50% reducing process using the conventional technique A; [0049]FIG. 2D is a schematic diagram showing the result of the 50% reducing process using the conventional technique B; [0050]FIG. 2E is a schematic diagram showing the result of the 50% reducing process according to the present invention; [0051]FIG. 3A is a schematic diagram showing a laid T-shaped input image; [0052]FIG. 3B is a schematic diagram showing the result of the 50% reducing process by an OR operation; [0053]FIG. 3C is a schematic diagram showing the result of the 50% reducing process using the conventional technique A; [0054]FIG. 3D is a schematic diagram showing the result of the 50% reducing process using the conventional technique B; [0055]FIG. 3E is a schematic diagram showing the result of the 50% reducing process according to the present invention; [0056]FIG. 4 is a block diagram showing an image processing circuit used in one embodiment of the present invention; [0057]FIG. 5 is a timing diagram showing relationships among a line clock LC, input data I, output data O of an operation part, and output data LB1, LB2, and LB3 of line buffers; [0058]FIG. 6 is a block diagram showing the input data, the output of the operation part, and the output of the line buffers by pixel data; [0059]FIG. 7 is a schematic diagram showing focused pixels of an original image and a reference pixel for obtaining reduced image data; [0060]FIG. 8 is a schematic diagram showing a focused pixel and reference pixels of a reduced image for obtaining reduced image data; and [0061]FIG. 9 is a block diagram showing the circuit configuration according to the present invention in a case where reduction in the main scanning direction is performed.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0062]FIG. 4 is a block diagram showing an image processing circuit used in one embodiment of the present invention. An image processing circuit 1 may be used for reduction in the sub-scanning direction and reduction in the main scanning direction, as is described below. [0063] The image processing circuit 1 can reduces binary data of an original image by 50% in the sub-scanning direction or the main scanning direction. As shown in FIG. 4, the image processing circuit 1 includes a line buffer 11 as first line buffer means storing line data (data of each line) of the original image, and two line buffers 12 and 13 as second line buffer means sequentially storing pixel data that form lines of a reduced image (image after reduction) calculated by an operation part 14 as operation means. [0064] Input data I are input to the operation part 14 and also to the line buffer 11. The output of the line buffer 11 is input to the operation part 14. The output data O of the operation part 14 is input to the operation part 14 itself and also to the line buffer 12. Additionally, the output of the line buffer 12 is input to the line buffer 13, and the output of the line buffer 13 is input to the operation part 14. [0065] Accordingly, the operation part 14 performs a logical operation of pixels of the reduced image O (a focused pixel of the reduced image) based on data of two kinds of focused pixels of the original image of the input data I (focused pixels of the original image corresponding to the focused pixel of the reduced image), data of the peripheral pixel, and data of reference pixels in the periphery of the focused pixel of the reduced image. [0066]FIG. 5 shows the relationships among a line clock LC, the input data I, the output data LB1 of the line buffer 11, the output data LB2 of the line buffer 12, the output data LB3 of the line buffer 13, and the output data O of the operation part 14. The line clock LC is indicated by FIG. 5-A, the input data I is indicated by FIG. 5-B, the output data LB1 of the ling buffer 11 is indicated by FIG. 5-C, the output data LB2 of the line buffer 12 is indicated by FIG. 5-D, the output data LB3 of the line buffer 13 is indicated by FIG. 5-E, and the output data O of the operation part 14 is indicated by FIG. 5-F. In FIG. 5, an input line is represented by �. . . , 2y−1, 2y, 2y+1, . . . �, an output line is represented by �. . . , y−1, y, y+1, . . . � input data of each line are represented by �. . . , I(2y−1), I(2y), I(2y+1), . . . �, and the output data are represented by �. . . , O(y−2), O(y−1), O(y), . . . �. [0067] In FIG. 5, line image data O(y) are formed by pixel data o(0, y), o(1, y), o(2, y), . . . o (N−1, y), as is described below. [0068] As shown in FIG. 6, input data i(x−1, 2y+1) and i(x, 2y+1), the output of the line buffer 11: i(x, 2y), the output of the operation part 14: o(x−1, y), the output of the line buffer 13: o(x, y−1) are input to the operation part 14. Thus, the operation part 14 can calculate o (x, y). [0069] In this embodiment, as shown in FIG. 7, in order to obtain reduced image data o(x, y)(the focused pixel of the reduced image), two kinds of focused pixel data i(x, 2y) and i(x, 2y+1), and pixel data i(x−1, 2y+1) that is adjacent in the main scanning direction to i(x, 2y+1) are referred to. At the same time, as shown in FIG. 8, pixel data o(x−1, y) that is adjacent in the main scanning direction to the focused pixel data o(x, y) of the reduced image and pixel data o(x, y−1) that is adjacent in the sub-scanning direction to the focused pixel data o(x, y) are also referred to. [0070] More specifically, the operation part 14 performs calculation of the following Equation 3. o  ( x , y ) = inv  [ o  ( x , y - 1 ) ] � i  ( x , 2  y ) + o  ( x - 1 , y ) � inv  [ i  ( x - 1 , 2  y + 1 ) ] � i  ( x , 2  y ) + i  ( x , 2  y + 1 ) Equation   3 [0071] o: data after reduction [0072] (black=1, white=0) [0073] i: original image data [0074] (black=1, white=0) [0075] x: pixel number in main scanning direction [0076] y: pixel number in sub-scanning direction [0077] Further, in the above embodiment, the output image data o(x, y) of the operation part 14 are output once in two lines with respect to original image data i that is input in accordance with the line clock (synchronization signal of main scanning) LC, when 50% reduction is performed. Hence, in the above embodiment, the two line buffers 12 and 13 are provided for synchronization of o(x, y−1). However, only one line buffer may be provided, and the content of the line buffer may be updated once in two line clocks in synchronization with the line clock LC. [0078] Additionally, the reduction ratio is not limited to 50%. It is possible to perform free reduction at the reduction ratios from 100% to 50% by combining through output of input line data and the method of this embodiment. Also, it is possible to perform free reduction at a reduction ratio less than 50% by applying the method of this embodiment after carrying out thinning of input lines. [0079]FIG. 1E shows the result of the reducing process performed on the horizontal-striped input image. FIG. 2E shows the result of the reducing process performed on the inverted T-shaped input image. FIG. 3E shows the result of the reducing process performed on the laid T-shaped input image. As shown in FIG. 2E, image quality is not degraded with respect to the inverted T-shaped input image. Also, as shown in FIG. 3E, line thickening does not occur in the laid T-shaped input image. [0080] That is, if reduced image data o(x, y−1) of the previous line is white (=0), the term �inv [o(x, y−1)]�i(x, 2y)� of Equation 3 is a simple OR operation. Accordingly, loss of thin lines does not occur and, as shown in FIG. 1E, it is possible to avoid generation of a solid black image. [0081] Additionally, in the term �o (x−1, y) inv [i(x−1, 2y+1)]�i(x, 2y)� of Equation 3, by referring to the peripheral pixel data o(x−1, y) that is adjacent in the main scanning direction to processed reduced image data, as shown in FIG. 2E, it is possible to prevent image quality degradation in an inverted T-shaped image. [0082] Further, in the term �o (x−1, y)�inv [i(x−1, 2y+1)]�i(x, 2y)� of Equation 3, by referring to the peripheral pixel data i(x−1, 2y+1) that is adjacent in the main scanning direction to the original image data, as shown in FIG. 3E, it is possible to prevent line thickening in laid T-shaped images. [0083] The circuit configuration shown in FIG. 4 may be used even when performing reduction in the main scanning direction. Specifically, the image processing circuit shown in FIG. 9 is used. As shown in FIG. 9, input data i(2x, y) and i(2x+1, y), the output data i(2x+1, y−1) of a line buffer 21, the output data o(x−1, y) of an operation part 24, and the output data o(x, y−1) of a line buffer 22 are input to the operation part 24. Thus, the operation part 24 can calculate o(x, y). In this case, the same line clock is used for both input and output, and an input pixel clock becomes twice an output pixel clock. [0084] The following equation expresses o(x, y) on this occasion. o  ( x , y ) = inv  [ o  ( x - 1 , y ) ] � i  ( 2  x , y ) + o  ( x , y - 1 ) � inv  [ i  ( 2  x + 1 , y - 1 ) ] � i  ( 2  x , y ) + i  ( 2  x + 1 , y ) Equation   4 [0085] o: data after reduction [0086] (black=1, white=0) [0087] i: original image data [0088] (black=1, white=0) [0089] x: pixel number in main scanning direction [0090] y: pixel number in sub-scanning direction [0091] According to the present invention, when reducing an image, it is possible to prevent loss of thin lines and generation of solid black images and to prevent image quality degradation in inverted T-shaped images and line thickening in laid T-shaped images, which problems cannot be solved by conventional operations. [0092] The present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the present invention. [0093] The present application is based on Japanese priority application No. 2002-186061 filed on Jun. 26, 2002, the entire contents of which are hereby incorporated by reference. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7782483 *Feb 21, 2006Aug 24, 2010Brother Kogyo Kabushiki KaishaImage forming system, image forming apparatus, image processing apparatus and storage medium readable by computerUS7889392 *Jul 20, 2010Feb 15, 2011Brother Kogyo Kabushiki KaishaImage forming system, image forming apparatus, image processing apparatus and storage medium readable by computer* Cited by examinerClassifications U.S. Classification382/258International ClassificationH04N1/393, G06T3/40Cooperative ClassificationH04N1/3935, G06T3/4007European ClassificationG06T3/40B, H04N1/393MLegal EventsDateCodeEventDescriptionMay 10, 2011FPAYFee paymentYear of fee payment: 4Jun 16, 2003ASAssignmentOwner name: RICOH COMPANY, LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KOIKE, KAZUMASA;REEL/FRAME:014200/0481Effective date: 20030604RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google