Source: http://www.google.com/patents/US6738528?dq=6,373,753
Timestamp: 2014-10-25 17:41:14
Document Index: 199640777

Matched Legal Cases: ['art 19', 'art 18', 'art 17', 'art 19', 'art 19', 'art 19', 'art 23', 'art 21', 'art 23', 'art 24', 'art 23', 'art 19', 'art 24', 'art 321', 'art 321', 'art 321', 'art 321', 'art 412', 'art 413', 'art 412', 'art 413', 'art 416', 'art 418', 'art 418', 'art 416', 'art 417', 'art 418', 'art 422', 'art 423', 'art 422', 'art 423', 'art 426', 'art 428', 'art 428', 'art 426', 'art 427', 'art 428', 'arts 416', 'arts 417', 'art 52', 'art 64', 'art 64', 'art 642', 'art 643', 'art 642', 'art 643', 'art 645', 'art 645', 'art 66']

Patent US6738528 - Block noise detector and block noise eliminator - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA vertical HPF and a horizontal HPF receive a video signal 101, and extract only a high frequency component in the vertical/horizontal directions, respectively. Absolute value taking parts take an absolute value of the high frequency components, respectively, and change their values to positive values....http://www.google.com/patents/US6738528?utm_source=gb-gplus-sharePatent US6738528 - Block noise detector and block noise eliminatorAdvanced Patent SearchPublication numberUS6738528 B1Publication typeGrantApplication numberUS 09/463,215Publication dateMay 18, 2004Filing dateMay 18, 1999Priority dateMay 22, 1998Fee statusPaidAlso published asCN1164116C, CN1233172C, CN1272286A, CN1516473A, CN1527605A, CN100369488C, EP0998146A1, EP0998146A4, EP1775956A1, EP1775956B1, WO1999062264A1Publication number09463215, 463215, US 6738528 B1, US 6738528B1, US-B1-6738528, US6738528 B1, US6738528B1InventorsYutaka Nio, Satoshi Okamoto, Katsumi Terai, Naoji Okumura, Kazuhito TanakaOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (18), Referenced by (29), Classifications (16), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetBlock noise detector and block noise eliminatorUS 6738528 B1Abstract A vertical HPF and a horizontal HPF receive a video signal 101, and extract only a high frequency component in the vertical/horizontal directions, respectively. Absolute value taking parts take an absolute value of the high frequency components, respectively, and change their values to positive values. A horizontal accumulating/adding part and a vertical accumulating/adding part accumulate/add an input signal so as to output a vertical one-dimensional signal and a horizontal one-dimensional signal, respectively, each periodically having a peak value in the respective vertical and horizontal directions. A horizontal peak detecting part detects a horizontal peak position according to the horizontal one-dimensional signal. A vertical peak detecting part detects a vertical peak position according to the vertical one-dimensional signal and identifies a format thereof. A binarization part obtains a block boundary image, according to the horizontal peak position and the vertical peak position, in which pixel positions having a peak are provided with 1 and remaining pixel positions are provided with 0. In this manner, even if a block boundary to eliminate block noise thereon is not clearly identified, it becomes possible to correctly detect and eliminate the block boundary.
TECHNICAL FIELD The present invention relates to block noise detecting apparatuses and block noise eliminating apparatuses, and more particularly to a block noise detecting apparatus and a block noise eliminating apparatus of a type eliminating block noise that arises in digital images as a result of image encoding carried out by compressing the digital images for transferring and recording.
BACKGROUND ART Data compression is conventionally done for digital images, for example, to store the digital images with a lower volume of data. Such data compression includes a lossless encoding method and a lossy encoding method. In the lossless encoding method, encoded data, after decoding, can be completely identical to data before encoding. On the other hand, in the lossy encoding method, encoded data, after decoding, cannot always be identical to data before encoding and may include some degree of error.
SUMMARY OF THE INVENTION The present invention has the following features to attain the objects above.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the structure of a block noise detecting apparatus according to a first embodiment of the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a block noise detecting apparatus and a block noise eliminating apparatus of the present invention are described next below on a functional block basis.
The binarization part 19 receives the horizontal peak position 122 outputted from the horizontal peak detecting part 18 and the vertical peak position 123 outputted from the vertical peak detecting part 17. The binarization part 19 provides, in accordance with the horizontal peak position 122, a logical value of �1� for each pixel position where the peak is, and provides a logical value of �0� for the remaining pixel positions, and then generates a horizontal binary image 124 in the same size as the one-frame image 112 (FIG. 4(a)). Further, the binarization part 19 provides, in accordance with the vertical peak position 123, the logical value of �1� for each pixel position where the peak is, and provides the logical value of �0� for the remaining pixel positions, and then generates a vertical binary image 125 in the same size as the one-frame image 112 (FIG. 4(b)). Thereafter, the binarization part 19 performs an OR operation for the horizontal binary image 124 and vertical binary image 125 so as to determine a block boundary image 103 (FIG. 4(c)).
In the block boundary image 103, a part having the logical value of �1� is the block boundary part, that is, where the block noise 114 arises.
The binarizarion part 23 receives the difference areas outputted from the frame difference taking part 21. Then, in the one-frame image 112, the binarization part 23 provides the logical value of �1� for each pixel position where the difference is (singular point), and the logical value of �0� for the remaining pixel positions without the difference. In this manner, the singular-point-to-be-eliminated image 233 in FIG. 6(a) is obtained. Note that, the shaded and dotted parts in FIG. 6(a) are the pixel positions having the logical value of �1�.
The singular point eliminating part 24 receives the singular-point-to-be-eliminated image 233 (FIG. 6(a)) from the binarization part 23, and a block size from the binarization part 19. Thereafter, the singular point eliminating part 24 eliminates, from the singular-point-to-be-eliminated image 233, data having the logical value of �1� observed in regions smaller than one block size (regions indicated by dashed lines in FIG. 6(a)). In this manner, the singular-point-eliminated image 234 in FIG. 6(b) is obtained.
In the interlace system, generally, the number of lines in the V period is 262. 5. Accordingly, in a case with the interlace system, the bit counter 312 counts 525 times, twice as much as the number of lines, by using the upconverted H pulse. In the progressive system, on the other hand, the number of lines in the V period is 262 or 263. Accordingly, in the case with the progressive system, the bit counter 312 counts 524 times or 526 times, twice as much as the number of lines, by using the upconverted H pulse. Therefore, by judging whether or not the least significant bit of the values counted in every V period is an even number or an odd number, it is known that the odd number (that is, �5�) refers to the interlace system and the even number (that is, �4� or �6�) refers to the progressive system.
In more detail, the format identifying signal 102 outputted from the bit counter 312 is outputted in a form of a binary signal indicating the logical value of �1� (interlace system) and the logical value of �0� (progressive system).
Referring to FIG. 10, the block noise eliminating circuit 32 receives the video signal 101 and the BE signal 203 outputted from the block noise detecting apparatus 20. The smoothing processing part 321 receives the video signal 101 and smoothes the signal. The selector 322 receives the smoothed video signal outputted from the smoothing processing part 321, the video signal 101 without being smoothed, and the BE signal 203. Then, the selector 322 selects the smoothed signal as to a pixel in which the BE signal 203 has the logical value of �1� (block noise observed), and selects the not-smoothed video signal 101 as to a pixel in which the BE signal 203 has the logical value of �0� (block noise not observed). As is known from this, by using the BE signal 203, the block noise eliminating circuit 32 of the present invention executes such smoothing that reduces the block noise, but blurs edges of the video signal at the same time only on the block boundary where the block noise is observed.
FIGS. 11(a) and (b) exemplarily show smoothing executed by the smoothing processing part 321. In FIG. 11, smoothing is executed by using a low-pass filter (hereinafter, referred to as LPF) having �3� taps and each weighs ⅓, ⅓, and ⅓.
In FIG. 11(a), to smooth the block boundary where the BE signal has the logical value of �1�, a pixel a on the right end of a block A and a pixel b on the left end in a block B adjoining to the block A are extracted and smoothed. As a result, as shown in FIG. 11(b), a difference in pixel level around the block boundary can be eliminated. To enhance the effects of the smoothing, the number of pixels to be extracted in the smoothing processing part 321 is set to 2 or more, or the number of taps of the LPF is increased, whereby the smoothing can be more effective.
In FIG. 13, the horizontal HPF 411 receives the video signal 101, and then extracts only high frequency components in the horizontal direction. The absolute value taking part 412 receives a signal outputted from the horizontal HPF 411, and takes an absolute value thereof so as to change the value to a positive value. The vertical accumulating/adding part 413 receives a signal outputted from the absolute value taking part 412, and performs accumulation/addition so as to output the horizontal one-dimensional signal 115 having a peak value at horizontal intervals (see FIG. 2). The HPF 414 extracts high frequency components for the purpose of improving accuracy of the signal outputted from the vertical accumulating/adding part 413, and then detects a horizontal block noise level. The temporal filter 415 extends the horizontal block noise level outputted from the HPF 414 in the temporal direction. The N-point accumulating/adding part 416 accumulates/adds and outputs noise observed in every predetermined N-point (where N indicates the number of pixels in a block), that is, noise observed at the same pixel position in each block. The maximum value detecting part 418 determines a maximum value of the N-point and a block boundary in the horizontal direction. Herein, in a case where the block noise arises at 8 (pixels)�8 (lines) intervals in MPEG2, the maximum value detecting part 418 sets N of the N-point accumulating/adding part 416 to �8�, and determines the horizontal block boundary. The masking part 417 masks the horizontal block noise level outputted from the temporal filter 415 on the horizontal boundaries determined by the maximum value detecting part 418, and then outputs only the horizontal block noise level observed on the horizontal block boundary.
In FIG. 14, the horizontal HPF 421 receives the video signal 101, and extracts only high frequency components in the vertical direction. The absolute value taking part 422 receives a signal outputted from the vertical HPF 421, and takes an absolute value thereof so as to change the value to a positive value. The horizontal accumulating/adding part 423 receives a signal outputted from the absolute value taking part 422, and performs accumulation/addition so as to output the vertical one-dimensional signal 116 having a peak value at vertical intervals (see FIG. 2). The HPF 424 extracts high frequency components for the purpose of improving accuracy of the signal outputted from the horizontal accumulating/adding part 423, and then detects a vertical block noise level. The temporal filter 425 extends the vertical block noise level outputted from the HPF 424 in the temporal direction. The N-point accumulating/adding part 426 accumulates/adds and outputs noise observed in every predetermined N-point. The maximum value detecting part 428 determines a maximum value of the N-point and block boundary in the vertical direction. Herein, in a case where the block noise arises at 8�8 intervals in MPEG2, for example, the maximum value detecting part 428 sets N of the N-point accumulating/adding part 426 to �8�, and determines the vertical block boundary. The masking part 427 masks the vertical block noise level outputted from the temporal filter 425 on the vertical block boundary determined by the maximum value detecting part 428, and then outputs only the vertical block noise level observed on the vertical block boundary.
Typically, a CPU (central processing unit) controls operation of the block noise eliminating apparatus 40 according to the fourth embodiment of the present invention. If this is the case, the CPU may receive output results of the N-point accumulating/adding parts 416 and 426, detect where the block boundary is, and then control the masking parts 417 and 427. Further, the CPU may receive the detected block noise level and the block boundary, and instruct and control picture enhancement level or noise elimination level on a screen. Still further, after the block noise is detected, a judgement result made on types of input sources such as �DVD/DVC/digital� or quality of video signal (MPEG, for example) can be on-screen-displayed (hereinafter, referred to as OSD).
The selector 53 selects either one of the inputted two digital video signals as instructed by a user, and then outputs the same as the video signal 101. Herein, the selector 53 outputs a receiving pulse 531 indicating which digital video signal is selected and outputted. When an output of the AD converter 51 is selected (input is presumably a DVD analog signal), the logical value of �0� is outputted as the receiving pulse 53 1, and when an output of the digital decoding part 52 is selected (input is presumably a digital signal of a digital video camera (DVC)), the logical value of �1� is outputted. The receiving pulse 531 can, for example, be utilized as information for OSD indicating what was received. In the above example, characters such as �DVD� or �DVC� can be OSD on a television screen.
FIGS. 22(a) and (b) are diagrams exemplarily showing an accumulation/addition result of the horizontal block noise outputted from the horizontal block boundary detecting part 64 in FIG. 20. Note that, the accumulation/addition result shown in FIGS. 22(a) and (b) is obtained when N is �8�.
In the horizontal block boundary detecting part 64, the horizontal HPF 641 receives the video signal 601, and then extracts only high frequency components in the horizontal direction. The absolute value taking part 642 receives a signal outputted from the horizontal HPF 641, and takes an absolute value thereof so as to change the signal to a positive value. The vertical accumulating/adding part 643 receives a signal outputted from the absolute value taking part 642, and performs accumulation/addition so as to output the horizontal one-dimensional signal 115 having a peak value at intervals in the horizontal direction (see FIG. 2). The HPF 644 extracts high frequency components for the purpose of improving accuracy of the signal outputted from the vertical accumulating/adding part 643, and detects a horizontal block noise level. The N-point accumulating/adding part 645 accumulates/adds and outputs noise observed in every predetermined N-point (where N indicates the number of pixels in a block), that is, noise observed at the same pixel position in each block. Herein, in a case where the block noise arises at 8 (pixels)�8 (lines) intervals in MPEG2, for example, the N-point accumulating/adding part 645 sets N to �8�, and determines the horizontal block boundary so as to output the same to the controlling part 66.
INDUSTRIAL APPLICABILITY As is described in the foregoing, in a video processing device (a television receiver, for example) using digital video signals subjected to lossy encoding on a predetermined image block basis, the present invention can be applied, first, to correctly detect and eliminate block noise to be arisen when the video signal is decoded, and second, to correctly regenerate a dot clock.
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358/426.14, 382/232, 382/233International ClassificationH04N7/26, G06T9/00Cooperative ClassificationH04N19/00593, H04N19/00909, H04N19/0089, H04N19/00915European ClassificationH04N19/00V1A, H04N7/26F, H04N7/26P4, H04N7/26M2GLegal EventsDateCodeEventDescriptionSep 20, 2011FPAYFee paymentYear of fee payment: 8Oct 26, 2007FPAYFee paymentYear of fee payment: 4Jan 21, 2000ASAssignmentOwner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NIO, YUTAKA;TERAI, KATSUMI;OKAMOTO, SATOSHI;AND OTHERS;REEL/FRAME:010603/0153Effective date: 19991220RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google