Source: http://www.google.com/patents/US7403060?dq=6,970,917
Timestamp: 2016-06-30 06:58:31
Document Index: 109396956

Matched Legal Cases: ['art 100', 'art 100', 'art 100', 'art 100', 'art 100', 'art 100', 'art 100']

Patent US7403060 - Forward biasing protection circuit - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body terminal of the transistor, and a clamping element coupled in parallel to the resistive element and configured to limit a voltage between the...http://www.google.com/patents/US7403060?utm_source=gb-gplus-sharePatent US7403060 - Forward biasing protection circuitAdvanced Patent SearchPublication numberUS7403060 B2Publication typeGrantApplication numberUS 11/390,852Publication dateJul 22, 2008Filing dateMar 28, 2006Priority dateNov 2, 2004Fee statusPaidAlso published asUS7098724, US20060091934, US20060192606Publication number11390852, 390852, US 7403060 B2, US 7403060B2, US-B2-7403060, US7403060 B2, US7403060B2InventorsDong PanOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (7), Non-Patent Citations (2), Classifications (8), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetForward biasing protection circuit
US 7403060 B2Abstract
A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body terminal of the transistor, and a clamping element coupled in parallel to the resistive element and configured to limit a voltage between the source terminal and the body terminal of the transistor. A method of manufacturing the forward biasing protection circuit is also provided.
a transistor comprising a body terminal, a source terminal, and a drain terminal;
a resistive element coupled to the body terminal; and
a clamping element coupled in parallel to the resistive element and configured to limit a voltage between the source terminal and the body terminal, wherein the clamping element comprises a diode.
2. The device, as set forth in claim 1, wherein the diode has a forward voltage of Vdiode.
3. The device, as set forth in claim 1, comprising a current source coupled to the resistive element and the clamping element.
4. The device, as set forth in claim 1, comprising a voltage source coupled to the resistive element and to the source terminal.
5. The device, as set forth in claim 1, wherein the transistor comprises a p-channel enhancement metal-oxide semiconductor field-effect transistor.
6. The device, as set forth in claim 1, wherein the transistor comprises an n-channel enhancement metal-oxide semiconductor field-effect transistor.
7. The device, as set forth in claim 1, wherein the device comprises a voltage regulator.
8. The device, as set forth in claim 1, wherein the device comprises a memory device.
9. The device, as set forth in claim 1, wherein the device comprises a processor.
a transistor comprising a body terminal and a source terminal;
a first node coupled to the body terminal;
a first resistor, coupled to the first node and configured to limit the voltage between the source terminal and the body terminal to no greater than the product of a current at the first resistor times the resistance of the first resistor;
a second resistor being coupled to the first node; and
a diode, being coupled to the first resistor and the second resistor, wherein the diode is configured to limit the voltage between the source terminal and the body terminal to the product of the voltage across the diode times the ratio of the resistance of the first resistor to the sum of the resistance of the first resistor and the resistance of the second resistor.
11. The device, as set forth in claim 10, comprising a current source configured to generate the current at the first resistor.
12. The device, as set forth in claim 10, comprising a voltage source, wherein the voltage source is coupled to the first resistor and coupled to the source terminal of the transistor.
13. The device, as set forth in claim 10, comprising an operational transductance amplifier, wherein the operational transductance amplifier is coupled to the transistor.
14. The device, as set forth in claim 10, wherein the first resistor comprises a transistor configured to operate as a resistor.
a circuit comprising a transistor having a source terminal, a drain terminal, and a body terminal; and
a forward biasing protection circuit coupled to the transistor and comprising:
a clamping element coupled in parallel to the resistive element and configured to limit a voltage across the body terminal of the transistor, wherein the clamping element comprises a diode.
16. The system, as set forth in claim 15, wherein the memory device comprises a synchronous dynamic random access memory (SDRAM) device.
17. The system, as set forth in claim 15, wherein the forward biasing protection circuit comprises a current source, wherein the current source is coupled to the clamping element and wherein the current source generates a current that is proportional to the current between the source terminal and the drain terminal of the transistor.
18. The system, as set forth in claim 15, wherein the circuit is a voltage regulator.
19. The system, as set forth in claim 18, wherein the memory device comprises a second voltage regulator coupled to the forward biasing protection circuit.
This application is a continuation of U.S. application Ser. No. 10/979,269, filed on Nov. 2, 2004, now U.S. Pat. No. 7,098,724.
The present invention relates generally to integrated circuits and, more particularly, to integrated circuits implementing transistors that have been forward biased between the source region and the body to increase the depth of the induced channel.
As most people are aware, an integrated circuit is a highly miniaturized electronic circuit that is typically designed on a semiconductive substrate. Over the last 10 years, there has been considerable attention paid to designing smaller, lower-power integrated circuits. These smaller, lower-power integrated circuits are often used in portable electronic devices that rely on battery power, such as cellular phones and laptop computers. As circuit designers research new ways to lower the power consumption of integrated circuits, they are constantly confronted with new challenges that need to be overcome in order to create the integrated circuits that will be part of the next generation computer, cellular phone, or camera.
The fundamental building block of the modern integrated circuit is the transistor. Transistors are most often created on a substrate composed of a silicon semiconductor, but they may be created using any one of a number of different semiconductors. Silicon transistors are created by altering the electrical properties of silicon by adding other materials called “dopants” to the silicon. This process is known as doping. In n-type doping, dopants are added to the silicon to provide extra electrons that do not bond with the silicon. These free electrons make n-type silicon an excellent conductor. In p-type doping, silicon is doped with elements that cause an empty space, known as a “hole,” to develop in the silicon. Because these holes readily accept electrons from other silicon atoms, p-type silicon is typically also a good conductor.
Even though p-type silicon and n-type silicon are each good conductors, they are not always good conductors when joined. These junctions, called p-n junctions, are essential one way streets for current—allowing it to flow in one direction across the junction but not in the other direction. When current can flow across the p-n junction, it is said to be “forward-biased,” and when current can not flow across the p-n junction, it is considered to be “reverse-biased.”
While there are numerous types of transistors, metal-oxide semiconductor field-effect transistors (“MOSFETs”) have been particularly popular over the past few years. One example of this type of MOSFET is known as an n-channel enhancement type MOSFET or NMOS transistor. The NMOS transistor is created by forming two heavily doped n-type regions in a p-type semiconductive substrate (i.e. NPN). These two n-type regions form regions known as the source and drain regions. Next, a thin layer of an oxide insulator may be grown on the surface of the substrate and metal or another conductor may be deposited on this oxide to create a gate region. Terminals are then attached to the source region, the drain region, the gate region, and the p-type semi-conductive substrate (also known as “the body”) to create a semiconductor device with four terminals: the source (“S”) terminal, the drain (“D”) terminal, the gate (“G”) terminal, and the body (“B”) terminal.
A voltage Vgs placed between the gate terminal and the source terminal of the NMOS transistor will create an electrical field in the semiconductive substrate below the gate terminal. This electrical field causes mobile electrons in the source region, the drain region, and the substrate to accumulate and form an n-type conductive channel in the p-type substrate. This conductive channel is known as the “induced channel.” This n-type induced channel effectively connects the source and drain regions together and allows current to flow from the drain to the source (i.e. opening up the transistor). The voltage Vgs that is sufficient to cause enough electrons to accumulate in the channel to form an induced channel (i.e. to open up the channel) is known as the “threshold voltage.”
A related type of MOSFET, known as p-channel enhancement type MOSFET or PMOS, is created on an n-type substrate with source and drain regions composed of p-type regions (i.e. PNP). PMOS transistors operate very similarly to NMOS transistors except that the threshold voltage is negative and current flows from the source terminal to the drain terminal.
As stated above, MOSFETs have four terminals: the source, the drain, the gate, and the body. Of these, the body terminal is the least well-known. This is the case because in most early applications, the body terminal was electrically coupled to the source terminal. Connecting the source and body regions together creates a constant reverse bias on the p-n junction between the body and the channel. Because current can not flow across this reverse biased p-n junction, no current could flow into the body, and thus the body typically did not affect the operation of the transistor.
Unfortunately, this same concept does not always apply when there are multiple integrated circuits sharing a single body as with an integrated circuit. Because there are many transistors connected to the same body, it is no longer certain that connecting the source region to the body will create a constant reverse bias. One method of ensuring that the reverse bias is maintained is to connect the body to the most negative power supply in the NMOS MOSFET or the most positive power supply in a PMOS MOSFET. However, this large reverse bias can reduce the depth of the induced channel. Disadvantageously, as the channel becomes shallower, the amount of current that can flow through the induced channel is reduced even though the voltage Vgs stays constant. This phenomenon is known as the “body effect.” In order to counter the body effect, the voltage Vgs may be increased. Years ago when power consumption was not a top priority for circuit designers, increasing Vgs did not present a serious problem. In recent years, however, with the rapid growth of mobile technologies that rely on battery power, scientists and engineers have searched for a way to maintain or increase the induced channel current (i.e. deepen the induced channel current) without increasing the voltage Vgs.
One recent method to increase the channel current without increasing the voltage Vgs is to forward bias the p-n junction between the source terminal and the body terminal. In accordance with these techniques, the PMOS body is usually biased lower than the source terminal voltage and the NMOS body is usually biased higher than the source terminal voltage. The forward biasing increases the channel depth, which permits the transistor to conduct more current for a given voltage Vgs. A channel that can conduct more current can be used to make the transistor operate faster on the same voltage or to reduce the size of the transistor without sacrificing performance.
Unfortunately, forward-biasing the source to body p-n junction can have unintended effects on the circuit. Foremost amongst these effects is the potential for body leakage current. As previously discussed, when a p-n junction is forward biased, it is essentially opened up to the flow of current. This may permit the current flowing across the channel to “leak” into the body of the transistor. Because this leakage current reduces the amount of current that flows between the source and the drain, it can have an adverse effect on the performance of the transistor. This is especially the case if the transistor is driving a particularly small load, and the current across the transistor is relatively small. For larger currents, some leakage current may be permitted to maximize the potential induced channel current, but if this leakage current is not limited in some fashion, its effects can overshadow the potential increase in induced channel current. A circuit that can minimize leakage current for small loads and clamp leakage current for higher loads is desirable.
Embodiments of the invention provide a method and an apparatus for increasing the potential induced channel current in a transistor without the risk of excess current leakage. Specifically, embodiments of the invention allow near zero current leakage at lower channel currents while at the same time providing a mechanism to limit the induced channel current such that the leakage current does not exceed a pre-determined threshold.
In one embodiment, this is accomplished by coupling two resistors, a diode, a current source, and a voltage source to the body terminal of the transistor. Specifically, the two resistors, R1 and R2 are coupled directly to the body terminal with the diode coupled in parallel to the resistors R1 and the resistor R2. The current source is then coupled to the resistor R2 and the voltage source, which is also coupled to the source terminal of the transistor, is coupled to resistor R1. In operation, this configuration clamps the voltage between the source terminal and the body terminal of the transistor to
Vdiode ( R 1 R 1 + R 2 ) when the current from the current source is high while providing a voltage between the source and body terminals of only R1 multiplied by the current source's current when the current source's current is low.
FIG. 1 illustrates a circuit diagram of an exemplary forward biasing protection circuit in accordance with embodiments of the present invention;
FIG. 2 illustrates a circuit diagram of an exemplary voltage regulator employing a forward biasing protection circuit in accordance with embodiments of the present invention;
FIG. 3 illustrates a chart depicting simulated performance data for an exemplary voltage regulator employing a forward biasing protection circuit in accordance with embodiments of the present invention; and
FIG. 4 illustrates a block diagram of an exemplary system employing a forward biasing protection circuit in accordance with embodiments of the present invention.
Forward biasing the source to body p-n junction can increase channel depth and thus increase the induced channel current of a transistor. However, if this forward biasing is not carefully controlled, it can result in leakage current that reduces or eliminates the benefits of the forward biasing. For example, where the drain current is relatively small (for example, there is a small load on the transistor), a slight leakage current can greatly reduce the amount of current between the source terminal and the drain terminal. This can have a large effect on the operation of the circuit. Specifically, because the current is small, there may not be enough current to benefit from a deeper channel, and any benefits from the deeper channel may be counteracted by the current lost to leakage current. In this case, keeping the voltage between the source and the body as low as possible is beneficial.
However, as the current at the drain terminal of the transistor increases (i.e. as the load increases), a small amount of leakage current may become an acceptable tradeoff for a deeper channel. In other words, even though some current may be lost to leakage, more overall current may be able to pass between the drain and source than would have otherwise been possible with a shallower channel and no leakage current. For example, properly forward biased, it may be possible to attain an approximately 10% increase in induced channel current with only a 776 nA increase in leakage current. This tradeoff is obviously well worth it. This increase in induced channel current can produce a variety of beneficial results. For example, larger induced channel current can be used to increase the performance of a transistor without increasing the voltage Vgs. Further, larger induced channel current may allow circuit designers to reduce the size of the transistor without a loss of performance.
Unfortunately, the increase in performance from forward biasing the source to body p-n junction is not continuous, and if the voltage between the source and the body exceeds a certain level (typically around 0.4V), the leakage current can rapidly increase to a detrimental level. For this reason, it can be beneficial to limit the voltage between the source and body to a predetermined maximum level.
Turning now to the drawings and referring initially to FIG. 1, a circuit diagram of an exemplary forward biasing protection circuit in accordance with embodiments of the present invention is illustrated and generally designated by a reference numeral 10. The circuit 10 comprises a voltage source Vcc 12. The voltage source 12 may be virtually any type of voltage source and may supply many circuits on a single microchip. The voltage source Vcc 12 may be coupled to a metal-oxide semiconductor field-effect transistor (“MOSFET”) 14. The MOSFET 14 is a PMOS MOSFET, but those in the art will appreciate that in alternate embodiments, the MOSFET 14 may be a different type of MOSFET. The operation of the MOSFET 14 was briefly described in the background section of this document and is well known to those skilled in the art. The MOSFET 14 typically comprises four terminals: the source terminal 16, the gate terminal 18, the drain terminal 20, and the body terminal 22.
The body terminal 22 may be coupled to a first resistor (“R1”) 24 through a first node 25. The resistor R1 24 may also be coupled to the voltage source 12. Both the body terminal 22 and the resistor R1 24 may also be coupled to a second resistor (“R2”) 26 through the first node 25. As illustrated in FIG. 1, a diode 28 (a clamping element) may be coupled in parallel to the resistor R1 24 and the resistor R2 26 (a resistive element), and the voltage source Vcc 12. The diode 28 will typically be “pointing” toward the junction with the resistor R2 26. In an alternate embodiment of the invention, the resistors R1 and R2 24, 26 may be replaced with transistors that are configured to act as resistors.
The R2 resistor 26 and the diode 28 may also be coupled to a current source 30. The current source 30 may create a current Ibias which can be employed to adjust the voltages across various components of the protection circuit 10. The current source 30 may take virtually any form, and the design of the current source 30 is well known to those skilled in the art. In one embodiment, the current source 30 may be comprised of a current mirror that creates an Ibias current that is proportional to the current at the drain terminal 20.
Looking now to the operation of the protection circuit 10, it can be seen that when the current Ibias is small, the voltage at the node 25, known as the body voltage or Vbody, may be approximately the same as the supply voltage Vcc 12. Specifically, the body voltage may be equal to Vcc−Ibias*R1. Because the current Ibias is small, the body voltage will be approximately the same as the supply voltage Vcc 12. Because of this, the voltage between the source terminal 16 and the body terminal 22 (“Vsb”) may be equal to Ibias*R1 (the small voltage difference between the Vcc and Vbody). As described above, this small Vsb can help to limit the leakage current.
Similarly, when Ibias is larger, due to the presence of the diode 28, the voltage Vbody will be clamped to
Vcc - Vdiode ( R 1 R 1 + R 2 ) and Vsb will be limited to
Vdiode ( R 1 R 1 + R 2 ) , where Vdiode is the forward voltage of the diode 28. This feature is advantageous because the value of Vdiode can be selected to ensure that when the current Ibias reaches a predetermined threshold, the voltage Vsb will be clamped to maintain an acceptable level of leakage current. Unlike when the current Ibias is low, the voltage Vsb is not sensitive to either the value of the current Ibias or the value of R1 because only the ratio of R1 to R1 plus R2 is being applied in the protection circuit 10. It is also important to note that the diode 28 will typically match the process, voltage, and temperature (“PVT”) changes of the MOSFET 14. This means that if the PVT characteristics of the MOSFET 14 are altered, the PVT characteristics of the diode 28 will be similarly altered. This can help to keep the leakage current relatively constant at the target level.
Turning next to FIG. 2, a circuit diagram of an exemplary voltage regulator employing a forward biasing protection circuit in accordance with embodiments of the present invention is illustrated and generally referred by a reference numeral 50. The function and operation of a generic voltage regulator is well known in art. Briefly stated, however, voltage regulators are typically used to reduce or eliminate any phase variation present in an incoming signal. This variation typically results from the fact that most power is transmitted over power lines as a sinusoidal waveform, referred to as alternating current, which is converted to a flat waveform, referred to as direct current, in order to be used in many types of devices. Voltage regulators are typically one of the last steps in this conversion process. In integrated circuits, voltage regulators may also be used to convert high voltage direct current from a power supply into lower voltage direct current for use on the integrated circuit. Those skilled in the art, however, will appreciate that voltage regulators can be used for a variety of functions unrelated to converting alternating current to direct current.
The voltage regulator 50 may comprise an operational transductance amplifier (“OTA”) 52. The function of the OTA 52 is well known to those skilled in the art and need not be discussed in detail. The OTA 52 has two inputs: an input voltage 51, referred to as Vin, and a feedback path 53. The OTA 52 is coupled to a MOSFET 56, which is will be referred to as the Transistor M1 56. In one embodiment of the invention, the transistor M1 56 may be a PMOS MOSFET that has four terminals. The source terminal of the transistor M1 56 will typically be coupled to a voltage source Vcc 58 whereas the drain terminal of the transistor M1 56 may be coupled to two load resistors 60 and 62.
The body terminal of the transistor M1 56 may be coupled to the body terminal of a MOSFET 66, which will be referred to as the transistor M2 66. The transistor M2 66 may be located within a protection circuit 64. This connection will typically be made by virtue of a common substrate, but in alternate embodiments, a wired connection could be used.
The gate terminal of the transistor M1 56 may be coupled to the OTA 52 as well as to the gate terminal of the transistor M2 66. This connection may create what is known as a “current mirror” between the transistor M1 56 and the transistor M2 66. Current mirrors, which are well known in the art, are employed to produce a current in a second transistor that is proportional to a current in a first transistor. This mirrored current can either be equal to, larger than, or smaller than the original current depending on the relative sizes of the transistors and the configuration of the circuit. However, regardless of whether the mirrored current is larger or smaller than the original current, the mirrored current will generally follow the changes of the original current. For instance, if the original current increases by 10%, the mirrored current will increase by 10%. Because the current on one side of the current mirror can follow the current on the other side of the current mirror, current mirrors, such as the one created by the transistors M1 and M2 56, 66 are typically used to connect components that are intended to be responsive to each other.
Returning now to the current mirror created by the transistor M1 56 and the transistor M2 66, the current at a node 57 located at the transistor M1's drain terminal (IM1) will typically be approximately one hundred times greater than the current at a node 67 located at the transistor M2's drain terminal (IM2). As will be described in more detail below, this mirroring permits the protection circuit 64 to reduce leakage current by automatically compensating for changes in the current Im1. Those skilled in art will appreciate that the particular attributes of the current mirror created by the transistor M1 56 and transistor M2 66 are part of the circuit design process and may be altered without changing the underlying nature of the invention.
The drain terminal of the transistor M2 66 may be coupled to another current mirror created by the MOSFETs 68 and 70. This current mirror is typically employed to permit the protection circuit 64 to be properly grounded and may be altered or absent in other embodiments of the invention. In the embodiment shown in FIG. 2, the current mirror created by the MOSFETs 68 and 70 creates a current Ibias at a node 71 that is equal to the current IM2. In alternate embodiments, the current Ibias may be different than the current IM1.
The node 71 at the source terminal of the MOSFET 70 may be coupled to a resistor 74, which will be referred to as the resistor R2 74, and a diode 76. The resistor R2 74 is in turn coupled to the body terminal of the transistor M2 66 and another resistor 72, which will be referred to as the resistor R1 74, at a node 73. The resistor R1 72 may be coupled to the voltage source Vcc 58 and to the diode 76.
The protection circuit 64 operates very similarly to the protection circuit 10 depicted in FIG. 1 except that in the protection circuit 64, the current Ibias follows the current IM1. As discussed above, in the protection circuit 64, the current Ibias is equal to the current IM2, which tracks the current IM1. Thus, when the current IM1 increases, the current Ibias will increase, and when the current IM1 decreases, the current Ibias will decrease. Further, as discussed above with reference to FIG. 1, this means that when the current IM1 is small, the body voltage at the node 73 will be equal to Vcc−Ibias*R1 and the voltage between the source terminal and the body terminal (Vsb) of the transistor M2 66 may be equal to Ibias*R1. As described above, this small voltage Vsb may minimize the leakage current. In addition because the body terminal of the transistor M1 56 is coupled to the body terminal of the transistor M2 66 and because the source terminals of both of the transistors should be coupled to the voltage source Vcc 58, the voltage between the source terminal and the body terminal of both the transistor M1 56 and the transistor M2 58 may also be equal to Ibias*R1 when the current IM1 is small.
As the current IM1 increases, the current Ibias will also increase until the voltage between the source terminal and the body terminal of both the M1 and transistor M2 s 56, 66 is clamped at
Vdiode ( R 1 R 1 + R 2 ) by the diode 76 and the R1 and R2 resistors 72 and 74, as described above in relation to the protection circuit 10 shown in FIG. 1. As with the protection circuit 10, this feature is advantageous because Vdiode, the forward voltage of the diode 76, can be selected to ensure that the value of Vsb will not result in larger than acceptable leakage current. In one embodiment Vdiode is selected such that
Vdiode ( R 1 R 1 + R 2 ) will be 0.3V.
For example, FIG. 3 illustrates a chart depicting simulated performance data for an exemplary voltage regulator employing a forward biasing protection circuit in accordance with embodiments of the present invention. The chart is generally designated by a reference numeral 100. The chart 100 depicts Vbody (line 102), the potential induced channel current in M1 (line 104), and leakage current (line 106) as Ibias varies between 0 uA and 30 uA. In the simulation shown in chart 100, Vcc is set to 2.15V, and the temperature is set to 85 C.
Chart 100 shows that when the voltage regulator is in standby mode (i.e. Im1 and Ibias are both close to 0 A), the potential induced channel current in M1 (point 112) is at 10.5 mA, the Vbody (point 108) is at 2.12V (i.e. Vsb is close to 0V), and the leakage current (point 116) is close to 0 A. As the Ibias increases, the chart 100 shows that Vsb increases (because Vbody decreases) until the diode 76 depicted in FIG. 2 clamps Vsb to
Vdiode ( R 1 R 1 + R 2 ) . In the embodiment of the invention depicted in the chart 100, point 110 shows where Vsb is clamped to approximately 0.4 volts (Vcc of 2.15V minus Vbody of 1.76V). Further, the chart 100 shows that as Vbody is clamped, the potential induced channel current in M1 (line 104) levels off at approximately 11.27 mA (point 114) and the leakage current levels off at approximately 776 nA (point 118). Thus, the chart 100 show that the protection circuit 64 depicted in FIG. 2 is able to increase the maximum potential channel current at M1 from 10.5 mA to 11.27 mA while preventing the leakage current from exceeding a predetermined threshold.
It is also important to note that a single forward biasing protection circuit, such as the protection circuit 64 depicted in FIG. 2, can be used in conjunction with multiple voltage regulators in a single computer chip. For example, a computer chip may contain one hundred voltage regulators that could all employ the same forward biasing protection circuit. Because the forward biasing protection circuit may permit a reduction in the size of the transistor M1 within each of these voltage regulators, the forward biasing protection circuit is able to save overall silicon space on the computer chip by reducing the size of each of these regulators.
This configuration is particular useful in the design of memory devices, processors, and computer systems that comprise memory devices. For example, turning back to the drawings and referring to FIG. 4, a block diagram of an exemplary system employing a forward biasing protection circuit in accordance with embodiments of the invention is illustrated and generally designated by a reference numeral 150. The system 150 may include one or more processors or central processing units (“CPUs”) 152. The CPU 152 may be used individually or in combination with other CPUs. While the CPU 152 will be referred to primarily in the singular, it will be understood by those skilled in the art that a system with any number of physical or logical CPUs may be implemented. Examples of suitable CPUs include the Intel Pentium 4 processor and the AMD Athlon processor. In one embodiment of the invention, the CPU 152 may comprise the forward biasing protection circuit.
A chipset 14 may be operably coupled to the CPU 152. The chipset 154 is a communication pathway for signals between the CPU 152 and other components of the system 150, which may include, a memory controller 158, an input/output (“I/O”) bus 164, and a disk drive controller 160. Depending on the configuration of the system, any one of a number of different signals could be transmitted through the chipset 154, and those skilled in the art will appreciate that the routing of the signals throughout the system 150 can be readily adjusted without changing the underlying nature of the system.
As stated above, the memory controller 158 may be operably coupled to the chipset 154. In alternate embodiments, the memory controller 158 may be integrated into the chipset 154. The memory controller 158 may be operably coupled to one or more memory devices 156. In one embodiment of the invention, the memory devices 156 may comprise the forward biasing protection circuit. The memory devices 156 may be any one of a number of industry standard memory types, including but not limited to, single inline memory modules (“SIMMs”) and dual inline memory modules (“DIMMs”). In certain embodiments of the invention, the memory devices 156 may facilitate the safe removal of the external data storage devices by storing both instructions and data.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4256977Dec 26, 1978Mar 17, 1981Honeywell Inc.Alternating polarity power supply control apparatusUS4268843Jan 15, 1980May 19, 1981General Electric CompanySolid state relayUS5689209 *Dec 30, 1994Nov 18, 1997Siliconix IncorporatedLow-side bidirectional battery disconnect switchUS5959488Jan 24, 1998Sep 28, 1999Winbond Electronics Corp.Dual-node capacitor coupled MOSFET for improving ESD performanceUS6404269Sep 17, 1999Jun 11, 2002International Business Machines CorporationLow power SOI ESD buffer driver networks having dynamic threshold MOSFETSUS6501632Aug 4, 2000Dec 31, 2002Sarnoff CorporationApparatus for providing high performance electrostatic discharge protectionUS6538279Mar 9, 2000Mar 25, 2003Richard A. BlanchardHigh-side switch with depletion-mode device* Cited by examinerNon-Patent CitationsReference1Gabriel A. Rincon-Mora and Phillip E. Allen, "A Low-Voltage, Low Quiescent Current, Low Drop-output Regulator," IEEE Journal Solid-State Circuits, vol. 33, No. 1, Jan. 1998, pp. 36-43.2Masayuki Miyazaki, Goichi Ono, and Koichiro Ishibashi, "A 1.2-GIPS/W Microprocessor Using Speed-Adaptive Threshold-Voltage CMOS with Foward Bias," IEEE Journal Solid-State Circuits, vol. 37, No. 2, Feb. 2002, pp. 210-217.Classifications U.S. Classification327/324, 327/534International ClassificationH03K5/08Cooperative ClassificationH03K19/0013, H03K2217/0018, H03K19/00315European ClassificationH03K19/00P4, H03K19/003CLegal EventsDateCodeEventDescriptionSep 21, 2011FPAYFee paymentYear of fee payment: 4Jan 6, 2016FPAYFee paymentYear of fee payment: 8May 12, 2016ASAssignmentOwner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENFree format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001Effective date: 20160426RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services