Source: http://www.google.com/patents/US7728626?ie=ISO-8859-1&dq=6,587,403
Timestamp: 2014-07-11 19:54:37
Document Index: 795203102

Matched Legal Cases: ['art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1']

Patent US7728626 - Memory utilizing oxide nanolaminates - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsStructures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator...http://www.google.com/patents/US7728626?utm_source=gb-gplus-sharePatent US7728626 - Memory utilizing oxide nanolaminatesAdvanced Patent SearchPublication numberUS7728626 B2Publication typeGrantApplication numberUS 12/205,338Publication dateJun 1, 2010Filing dateSep 5, 2008Priority dateJul 8, 2002Fee statusPaidAlso published asUS7221586, US7433237, US8228725, US20040004859, US20060284246, US20090002025, US20100244122Publication number12205338, 205338, US 7728626 B2, US 7728626B2, US-B2-7728626, US7728626 B2, US7728626B2InventorsLeonard Forbes, Kie Y. AhnOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (103), Non-Patent Citations (224), Referenced by (2), Classifications (26), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMemory utilizing oxide nanolaminatesUS 7728626 B2Abstract Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.
one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a transistor cell including:
a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; and
wherein the gate insulator includes oxide insulator nanolaminate layers wherein at least one charge trapping layer in the oxide insulator nanolaminate layers is substantially amorphous.
2. The programmable logic array of claim 1, wherein the insulator nanolaminate layers include transition metal oxides.
3. The programmable logic array of claim 2, wherein the insulator nanolaminate layers including transition metal oxides formed by atomic layer deposition (ALD).
4. The programmable logic array of claim 1, wherein the insulator nanolaminate layers include silicon oxycarbide.
5. The programmable logic array of claim 4, wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.
wherein the gate insulator includes oxide insulator nanolaminate layers and a transition metal oxide layer wherein the transition metal oxide layer is substantially amorphous.
7. The programmable logic array of claim 6, wherein the oxide insulator nanolaminate layers include silicon dioxide layers.
8. The programmable logic array of claim 7, wherein the transition metal oxide layer includes a hafnium oxide layer.
9. The programmable logic array of claim 7, wherein the transition metal oxide layer includes a zirconium oxide layer.
10. The programmable logic array of claim 7, wherein the transition metal oxide layer includes a titanium oxide layer.
11. The programmable logic array of claim 7, wherein the transition metal oxide layer includes a aluminum oxide layer.
one or more NOR arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a transistor cell including:
wherein the gate insulator includes oxide insulator nanolaminate layers and a transition metal oxide layer and wherein approximately 100 electrons stored in the transition metal oxide layer produces a change in threshold voltage of the transistor cell of approximately 0.5 volts.
13. The programmable logic array of claim 12, wherein the insulator nanolaminate layers including transition metal oxides formed by atomic layer deposition (ALD).
14. The programmable logic array of claim 13, wherein the oxide insulator nanolaminate layers include silicon dioxide layers.
15. The programmable logic array of claim 14, wherein the transition metal oxide layer includes a hafnium oxide layer.
16. The programmable logic array of claim 14, wherein the transition metal oxide layer includes a zirconium oxide layer.
17. The programmable logic array of claim 14, wherein the transition metal oxide layer includes a titanium oxide layer.
18. The programmable logic array of claim 14, wherein the transition metal oxide layer includes a aluminum oxide layer.
CROSS REFERENCE TO RELATED APPLICATIONS This application is a Divisional of U.S. application Ser. No. 11/458,854, filed Jul. 20, 2006,now U.S. Pat. No. 7,433,237, which is a Continuation of U.S. application Ser. No. 10/190,717, filed Jul. 8, 2002, now U.S. Pat. No. 7,221,586, which applications are incorporated herein by reference in its entirety.
This application is related to the following co-pending, commonly assigned U.S. patent applications: �Memory Utilizing Oxide-Nitride Nanolaminates,� , Ser. No. 10/190,689, and �Memory Utilizing Oxide-Conductor Nanolaminates,� Ser. No. 10/191,336, each of which disclosure is herein incorporated by reference.
Another type of high speed, low cost memory includes floating gate memory cells. A conventional horizontal floating gate transistor structure includes a source region and a drain region separated by a channel region in a horizontal substrate. A floating gate is separated by a thin tunnel gate oxide. The structure is programmed by storing a charge on the floating gate. A control gate is separated from the floating gate by an intergate dielectric. A charge stored on the floating gate effects the conductivity of the cell when a read voltage potential is applied to the control gate. The state of cell can thus be determined by sensing a change in the device conductivity between the programmed and unprogrammed states.
Multilayer insulators have been previously employed in memory devices. (See generally, U.S. Pat. No. 3,877,054, Boulin et al., Apr. 8, 1975, entitled �Semiconductor memory apparatus with a multi-layer insulator contacting the semiconductor,� and U.S. Pat. No. 3,964,085, Kahng et al., Jun. 15, 1976, entitled �Method for fabricating multilayer insulator-semiconductor memory apparatus�). The devices in the above references employed oxide-tungsten oxide-oxide layers. Other previously described structures described have employed charge-trapping layers implanted into graded layer insulator structures. (See generally, an article by DiMaria, D. J., �Graded or stepped energy band-gap-insulator MIS structures (GI-MIS or SI-MIS),� Journal of Applied Physics, 50(9), 5826-9 (September 1979); U.S. Pat. No. 4,217,601, DeKeersmaecker et al., Aug. 12, 1980, entitled �Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure,� also RE31,083 DeKeersmaecker et al., Nov. 16, 1982, �Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure;� and U.S. Pat. No. 5,768,192 Eitan, Jun. 16, 1998, entitled �Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping�).
More recently oxide-nitride-oxide structures have been described for high density nonvolatile memories. (See generally, Etian, B. et al., �NROM: A novel localized Trapping, 2-Bit Nonvolatile Memory Cell,� IEEE Electron Device Lett., 21(11), 543-545 (November 2000), and Eitan, B. et al., �Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM device, IEEE Electron Device Lett., 22(11), 556-558 (November 2001)). All of these are variations on the original MNOS memory structure (see generally, Frohman-Bentchkowsky, D., �An integrated metal-nitride-oxide-silicon (MNOS) memory,� Proceedings of the IEEE, 57(6), 1190-2 (June 1969)) described by Fairchild Semiconductor in 1969 which was conceptually generalized to include trapping insulators in general for constructing memory arrays. (See generally, U.S. Pat. No. 3,665,423 Nakamuma et al., May 23, 1972, entitled �Memory matrix using MIS semiconductor element�).
Studies of charge trapping in MNOS structures have also been conducted by White and others. (See generally, White, M. H., �Direct tunneling in metal-nitride-oxide-silicon (MNOS) structures,� Conference: Program of the 31st physical electronics conference (abstracts), page: 1 pp., Publisher: U.S. Dept. Commerce, Washington, D.C., USA, 1971, viii+46 Pages, Sponsor: American Phys. Soc., division of electron and atomic phys, 15-17 Mar. 1971, Gaithersburg, Md., USA; White, M. H., Cricchi, J. R., �Characterization of thin-oxide MNOS memory transistors,� IEEE Transactions on Electron Devices, ED-19(12), 1280-8 (December 1972), Wei, L. S., Simmons, J. G. �Trapping, emission and generation in MNOS memory devices,� Solid-State Electronics, 17(6), 591-8 (June 1974), Ferris-Prabhu, A. V., �Charge transfer in layered insulators,� Solid-State Electronics, 16(9), 1086-7 (September 1973); Ferris-Prabhu, A. V., Lareau, L. J., �Amnesia in layered insulator FET memory devices,� Conference: 1973 International Electron Devices Meeting Technical Digest, Page: 75-7, Publisher: IEEE, New York, N.Y., USA, 1973, xvi+575 Pages, Sponsor: IEEE, 3-5 Dec. 1973, Washington, D.C., USA; Ferris-Prabhu, A. V., �Tunneling theories of non-volatile semiconductor memories,� Physica Status Solidi A, 35(1), 243-50 (16 May 1976)).
Some commercial and military applications utilized non-volatile MNOS memories. (See generally, Britton, J. et al., �Metal-nitride-oxide IC memory retains data for meter reader,� Electronics, 45(22); 119-23 (23 Oct. 1972); and Cricehi, J. R. et al., �Hardened MNOS/SOS electrically reprogrammable nonvolatile memory,� IEEE Transactions on Nuclear Science, ns-24(6), 2185-9 (December 1977), Conference: IEEE Annual Conference on Nuclear and Space Radiation Effects, Sponsor: IEEE, 12-15 Jul. 1977, Williamsburg, Va., USA).
SUMMARY OF THE INVENTION The above mentioned problems for creating DRAM technology compatible transistor cells as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. This disclosure describes the use of oxide insulator nanolaminate layers with charge trapping in potential wells formed by the different electron affinities of the insulator layers. Two different types of materials are used for the nanolaminated insulator layers. The two different types of materials are transition metal oxides and silicon oxycarbide. In the case of transition metal oxide layers, these are formed by ALD and have atomic dimensions, or nanolaminates, with precisely controlled interfaces and layer thickness. In the case of silicon oxycarbide, these are deposited using chemical vapor deposition techniques since an ALD process has not yet been developed.
The inventors have previously described programmable memory devices and functions based on the reverse stressing of MOSFET's in a conventional CMOS process and technology in order to form programmable address decode and correction. (See generally, L. Forbes, W. P. Noble and E. H. Cloud, �MOSFET technology for programmable address decode and correction,� application Ser. No. 09/383,804). That disclosure, however, did not describe write once read only memory solutions, but rather address decode and correction issues. The inventors also describe write once read only memory cells employing charge trapping in gate insulators for conventional MOSFETs and write once read only memory employing floating gates. The same are described in co-pending, commonly assigned U.S. patent applications, entitled �Write Once Read Only Memory Employing Charge Trapping in Insulators,� Ser. No. 10/177,077, and �Write Once Read Only Memory Employing Floating Gates,� Ser. No. 10/177,083. The present application, however, describes transistor cells having oxide insulator nanolaminate layers and used in integrated circuit device structures.
FIG. 2C is a graph plotting a current signal (IDS) detected at the second source/drain region 204 versus a voltage potential, or drain voltage, (VDS) set up between the second source/drain region 204 and the first source/drain region 202 (IDS vs. VDS). In one embodiment, VDS represents the voltage potential set up between the drain region 204 and the source region 202. In FIG. 2C, the curve plotted as D1 represents the conduction behavior of a conventional transistor which is not programmed according to the teachings of the present invention. The curve D2 represents the conduction behavior of the programmed transistor, described above in connection with FIG. 2A, according to the teachings of the present invention. As shown in FIG. 2C, for a particular drain voltage, VDS, the current signal (IDS2) detected at the second source/drain region 204 for the programmed transistor (curve D2) is significantly lower than the current signal (IDS1) detected at the second source/drain region 204 for the conventional transistor cell which is not programmed according to the teachings of the present invention. Again, this is attributed to the fact that the channel 206 in the programmed transistor of the present invention has a different voltage threshold.
Some of these effects have recently been described for use in a different device structure, called an NROM, for flash memories. This latter work in Israel and Germany is based on employing charge trapping in a silicon nitride layer in a non-conventional flash memory device structure. (See generally, B. Eitan et al., �Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM device,� IEEE Electron Device Lett., Vol. 22, No. 11, pp. 556-558, (November 2001); B. Etian et al., �NROM: A novel localized Trapping, 2-Bit Nonvolatile Memory Cell,� IEEE Electron Device Lett., Vol. 21, No. 11, pp. 543-545, (November 2000)). Charge trapping in silicon nitride gate insulators was the basic mechanism used in MNOS memory devices (see generally, S. Sze, Physics of Semiconductor Devices, Wiley, N.Y., 1981, pp. 504-506), charge trapping in aluminum oxide gates was the mechanism used in MIOS memory devices (see generally, S. Sze, Physics of Semiconductor Devices, Wiley, N.Y., 1981, pp. 504-506), and the present inventors have previously disclosed charge trapping at isolated point defects in gate insulators (see generally, L. Forbes and J. Geusic, �Memory using insulator traps,� U.S. Pat. No. 6,140,181, issued Oct. 31, 2000). However, none of the above described references addressed forming transistor cells utilizing charge trapping in potential wells in oxide insulator nanolaminate layers formed by the different electron affinities of the insulators.
This disclosure describes the use of oxide insulator nanolaminate layers with charge trapping in potential wells formed by the different electron affinities of the insulator layers. Two different types of materials are used for the nanolaminated insulator layers, transition metal oxides and silicon oxycarbide. (See generally, Wilk, G. D. et al., �High-k gate dielectric: Current status and materials properties considerations,� Jour. Appl. Phys., 89(10), 5243-75 (2001); Robertson, J., �Band offsets of wide-band-gap oxides and implications for future electronic devices,� J. Vac. Sci. Technol. B, 18(3), 1785-91 (2000); Luan, H. F. et al., �High quality Ta2O5 gate dielectrics with Tox, equil. 10 Angstroms,� IEDM Tech. Digest, 141-144 (1999); Zhu, W. J. et al., �Current transport in metal/hafnium oxide/silicon structure,� IEEE Electron Device Letters, 23(2), 97-99 (2002) for discussion on transition metal properties). (See generally, Yoder, M. N., �Wide bandgap semiconductor materials and devices,� IEEE Trans. on Electron Devices, 43, 1633-36 (October 1996); Ahn, K. Y. and Forbes, L., �Porous silicon oxycarbide integrated circuit insulator,� U.S. Pat. No. 6,313,518; Forbes, L. et al., �Transistor with silicon oxycarbide gate and methods of fabrication and use,� U.S. Pat. No. 5,886,368, for discussion on silicon oxycarbide properties).
Embodiments of the present invention use the atomic controlled deposition method to form the gate insulators if transition metal oxides are employed for the electron trapping layer. Atomic Layer Deposition (ALD), developed in the early 70s, is a modification of CVD and can also be called as �alternately pulsed-CVD.� (See generally, Ofer Sneh et al., �Thin film atomic layer deposition equipment for semiconductor processing,� Thin Solid Films, 402, 248-261 (2002)). Gaseous precursors are introduced one at a time to the substrate surface, and between the pulses the reactor is purged with an inert gas or evacuated. In the first reaction step, the precursor is saturatively chemisorbed at the substrate surface, and during the subsequent purging the precursor is removed from the reactor. In the second step, another precursor is introduced on the substrate and the desired films growth reaction takes place. After that the reaction byproducts and the precursor excess are purged out from the reactor. When the precursor chemistry is favorable, i.e., the precursor adsorb and react with each other aggressively, one ALD cycle can be preformed in less than one second in the properly designed flow type reactors.
(See generally, Shunsuke Morishita et al., �Atomic-Layer Chemical-Vapor-Deposition of SiO2 by Cyclic Exposure of CHOSi(NCO)3 and H2O2 ,� Jpn. J. Appl. Phys., 34, 5738-42 (1955)).
FIG. 5 illustrates an energy band diagram for an embodiment of a gate stack according to the teachings of the present invention. As shown in FIG. 5, the embodiment consists of insulator stacks, 501-1, 501-2 and 501-3, e.g. SiO2/oxide insulator nanolaminate layers/SiO2. The first and the last layer, 501-1 and 501-3, are done by atomic layer deposition. In some embodiments, layers 501-1 and 501-3 are deposited by cyclic exposures of CH3OSi(NCO)3 and H2O2 at room temperature. (See generally, Shunsuke Morishita et al., �Atomic-Layer Chemical-Vapor-Deposition of SiO2 by Cyclic Exposure of CHOSi(NCO)3 and H2O2 ,� Jpn. J. Appl. Phys., 34, 5738-42 (1955)). In this embodiment, the deposition rate is saturated at about 2 Å/cycle, i.e., equal to the ideal quasi-monolayer/cycle. In one example the surface roughness for 100 deposition cycles is found to be less than �10 Å by atomic force microscopy.
Recently a special technical meeting on �Atomic Layer Deposition� was held by the American Vacuum Society. (See generally, Forsgren, Katarina et al., �Atomic Layer Deposition of HfO2 using hafnium iodide,� one page summary of work, Conference held in Monterey, Calif., May 14-15, 2001). In the printed form, the above reference showed a summary of HfO2 growth using HfI4 for the first time, which results in a high melting material with a low leakage current and dielectric constant of 16-30. Together with a high chemical stability in contact with silicon, this makes HfO2 a possible replacement for SiO2 as a gate oxide. Previous work in the Forsgren group has shown that iodides can be used as metal sources in ALD of high-purity oxide films, e.g., Ta2O5, TaO2, ZrO2. Their study demonstrates the use of HfI4 in ALD for the first time. In a recent paper by Zhang et al., they published work on thin stacks comprised of alternate layers of Ta2O5/HfO2, Ta2O5/ZrO2, and ZrO2/HfO2. (See generally, Zhang, H. and Solanki, R., �Atomic Layer Deposition of High Dielectric Constant Nanolaminates,� Jour. of the Electrochemical Soc., 148(4) F63-F66 (2001)). Zhang et al. reported the thin stacks as high-permittivity insulators for possible gate applications. These thin layers were deposited on silicon substrates using atomic layer deposition. Nanolaminate with silicon oxide equivalent thickness of about 2 nm had dielectric constants of around ten and leakage current densities at 1 MV/cm of around 10−8 Å/cm2. Of the three kinds of nanolaminates investigated, ZrO2/HfO2 structure showed the highest breakdown field and the lowest leakage current. Zhang et al. report that by growing nanolaminates of high-permittivity thin films, leakage current of about 5�10−7 Å/cm2 and k values of around 10 can be obtained for films of equivalent SiO2 thickness, e.g. less than 3 nm.
In embodiments of the present invention, nanolaminates of HfO2 and ZrO2 are described as a dielectric material in new device structures with silicon oxide-metal oxide-silicon oxide insulator nanolaminates. Films with ALD of HfO2 are prepared with substrate temperature of 225-500� C. using HfI4 as precursor, instead of HfCl4. (See generally, Forsgren, Katarina et al., �Atomic Layer Deposition of HfO2, using hafnium iodide,� one page summary of work, Conference held in Monterey, Calif., May 14-15, 2001). Another process temperature for the HfO2 is at 325� C. as practiced by Kukli et al. (See generally, Kukli, Kaupo et al., �Dielectric Properties of Zirconium Oxide Grown by Atomic Layer Deposition from Iodide Precursor,� Jour. of the Electrochemical Soc., 148(12), F227-F232 (2001)). For deposition of ALD ZrO2, an alternative precursor of ZrI4 would be used instead of ZrCl4. ZrO2 films were previously grown from ZrI4 and H2O�H2O using the same atomic layer deposition technique. (See generally, Carter, R. J. et al., �Electrical Characterization of High-k Materials Prepared by Atomic Layer CVD,� IWGI, 94-99 (2001)). The breakdown field exceeded 2 MV/cm in the films grown at 325-500� C. The relative permittivity measured at 10 kHz was 20-24 in the films deposited at 275-325� C. The dissipation factor of these films was as low as 0.02-0.03. Thus, for the deposition of nanolaminates, a temperature of 250 to 325� C. would be recommended. Other references for ZrO2 may be useful to note. (See generally, Kukli, Kaupo et al., �Tailoring the dielectric properties of HfO2�Ta2O3 nanolaminates,� Appl. Phys. Lett., 68(26), 3737-39 (1996)).
Guha et al. reported on the electrical and microstructural characteristics of La- and Y-based oxides grown on silicon substrates by ultrahigh vacuum atomic beam deposition. (See generally, Guha, S. et al., �Atomic beam deposition of lanthanum- and yttrium-based oxide thin films for gate dielectrics,� Appl. Phys. Lett., 77(17), 2710-2712 (2000)). The Guha et al. group was interested in examining the potential of lanthanum- and yttrium-based oxide-thin films as alternate gate dielectrics for Si complementary metal oxide semiconductor technology. Guha et al. examined the issue of the polycrystallinity and interfacial silicon oxide formation in these films and their effect on the leakage currents and the ability to deposit films with low electrical thinness. They found that the interfacial SiO2 is much thicker at �1.5 nm for the Y-based oxide compared to the La-based oxide where the thickness <0.5 nm. They also showed that while the Y-based oxide films show excellent electrical properties, the La-based films exhibit a large flat band voltage shift indicative of positive charge in the films. In embodiments of the present invention, nanolaminates of HfO2 and ZrO2 are also described as a dielectric material in new device structures with silicon oxide-metal oxide-silicon oxide insulator nanolaminates.
Niilisk et al. studied the initial growth of TiO2 films by ALD. (See generally, Niilisk, A. et al., �Atomic-scale optical monitoring of the initial growth of TiO2 thin films,� Proc. of the SPIE, 4318, 72-77 (2001)). The initial atomic-layer-chemical-vapor-deposition growth of titanium dioxide from TiCl4 and water on quartz glass substrate was monitored in real time by incremental dielectric reflection. In the Niilisk et al. reference an interesting means for beginning the growth from the very beginning into a time-homogeneous mode was proposed and preliminarily studied. The means for beginning the growth from the very beginning into a time-homogeneous mode consists of an in situ TiCl4-treatment procedure. The crystal structure and surface morphology of the prepared ultrathin films were characterized by Niilisk et al. In embodiments of the present invention, nanolaminates of TiO2 are also described as a dielectric material in new device structures with silicon oxide-metal oxide-silicon oxide insulator nanolaminates.
Further, in embodiments of the present invention, nanolaminates of Al2O3 are described as a dielectric material for new device structures with silicon oxide-metal oxide-silicon oxide insulator nanolaminates. In these embodiments, Al2O3 can be deposited by ALD. (See generally, DiMaria, D. J. �Graded or stepped energy band-gap-insulator MIS structures (GI-MIS or SI-MIS),� Journal of Applied Physics, 50(9), 5826-9 (September 1979) for one technique appropriate for performing the ALD deposition).
Silicon oxycarbide is a wide band gap semiconductor, with a band gap energy which can vary between that of silicon carbide and that of silicon oxide. (See generally, Yoder, M. N., Wide bandgap semiconductor materials and devices,� IEEE Trans. on Electron Devices, 43, 1633-1636 (October 1996)). FIG. 6 is a graph which plots electron affinity versus the energy bandgap for various insulators. That is FIG. 6 illustrates the inventors estimates of the variation of the electron affinity with the bandgap energy. If the insulator is crystalline and has a small band gap, near that of silicon carbide, then the insulator can be doped and be conductive, however if undoped and in an amorphous state with a larger band gap, it will be an insulator. The inventors of the present case, Ahn, K. Y. and Forbes, L., have previously described silicon oxycarbide for use as an insulator in integrated circuits. (See generally, U.S. Pat. No. 6,313,518, by Ahn, K. Y. and Forbes, L., entitled �Porous silicon oxycarbide integrated circuit insulator�). The inventors of the present case, Ahn, K. Y. and Forbes, L., have previously described doped and microcrystalline silicon oxycarbide to be conductive for use as a gate material. (See generally, U.S. Pat. No. 5,886,368, by Forbes, L. et al., entitled �Transistor with silicon oxycarbide gate and methods of fabrication and use�). Additionally, silicon oxycarbide has been described for passivation of integrated circuit chips. (See generally, U.S. Pat. No. 5,530,581, by S. F. Cogan, entitled �Protective overlay material and electro-optical coating using same�).
Silicon oxycarbide can be deposited by chemical vapor deposition, CVD, techniques. (See generally, Fauchet, P. M. et al., �Optoelectronics and photovoltaic applications of microcrystalline SiC,� Symp. on Materials Issues in Microcrystalline Semiconductors, pp. 291-2 (1989); Demichelis, F. et al., �Physical properties of undoped and doped microcrystalline SiC:H deposited by PECVD,� Symp. on Amorphous Silicon Technology, pp. 413-18 (1991); Demichelis, F. et al., �Influence of doping on the structural and optoelectronic properties of amorphous and microcrystalline silicon carbine,� J. Appl. Phys., 72(4), 1327-33 (1992); Chang, C. Y. et al., �Novel passivation dielectrics�the boron- or phosphorus-doped hydrogenated amorphous silicon carbide films,� J. Electrochemical Society, 132(2), 418-22 (February 1995); Martins, R. et al., �Transport properties of doped silicon Oxycarbide microcrystalline films produced by spatial separation techniques,� Solar Energy Materials and Solar Cells, 41-42, 493-517 (June, 1996); Martins, R. et al., �Wide band-gap microcrystalline silicon thin films,� Diffusion Defect Data Part B (Solid State Phenomena), Vol. 44-46, pt. 2, p. 299-346 (1995); Renlund, G. M. et al., �Silicon oxycarbide glasses, I. Preparation and chemistry, J. Materials Research, 6(12), 2716-22 (December 1991); Renlund, G. M. et al., �Silicon oxycarbide glasses, II. Structure and properties,� J. Materials Research, 6(12), 2723-34 (December 1991)). In the silicon oxycarbide embodiments of the present invention, an initial gate oxide is grown by thermal oxidation of silicon and then the silicon oxycarbide and final oxide layer is deposited by CVD.
In embodiments of the present invention, the gate structure embodiment of FIG. 5, having silicon oxide-oxide insulator nanolaminates-silicon oxide, is used in place of the gate structure provided in the following commonly assigned pending applications: Forbes, L., �Write once read only memory based on DRAM technology employing charge trapping in gate insulators,� application Ser. No. 10/177,077; Forbes, L., �Write once read only memory based on a modification of DRAM technology employing floating gates,� application Ser. No. 10/177,083; Forbes, L., �Write once read only memory with long retention for archival storage,� application Ser. No. 10/177,213; Forbes, L., �Nanoncrystal write once read only memory with long retention for archival storage,� application Ser. No. 10/177,214; Forbes, L., �Ferroelectric write once read only memory with long retention for archival storage,� application Ser. No. 10/177,082; Forbes, L., �Vertical NROM having a storage density of 1 bit/1F2 flash memory cell,� application Ser. No. 10/177,208; Forbes, L., �Multistate NROM having a storage density much greater than 1 bit/1F2,� application Ser. No. 10/177,211; Forbes, L., �NOR flash memory cell with high storage density,� application Ser. No. 10/177,483.
Further, in embodiments of the present invention, the gate structure embodiment of FIG. 5, having silicon oxide-oxide insulator nanolaminates-silicon oxide, is used in place of the gate structure provided in the following U.S. patents: Etian, B. et al., �NROM: A novel localized Trapping, 2-Bit Nonvolatile Memory Cell,� IEEE Electron Device Lett., 21(11), 543-545 (November 2000); Eitan, B. et al., �Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM device, IEEE Electron Device Lett., 22(11), 556-558 (November 2001); Maayan, E. et al., �A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate,� Dig. IEEE Int. Solid-State Circuits Conf., 100-101 (2002). In these embodiments, the gate structure embodiment of FIG. 5, having silicon oxide-oxide insulator nanolaminates-silicon oxide used in place of the gate structures in those references, can be programmed in the reverse direction and read in the forward direction to obtain more sensitivity in the device characteristics to the stored charge.
FIGS. 7A-B and 8 are embodiments useful in illustrating the use of charge storage in the oxide insulator nanolaminate layers to modulate the conductivity of the transistor cell according to the teachings of the present invention. That is, FIGS. 7A-7B illustrates the operation of an embodiment for a novel transistor cell 701 formed according to the teachings of the present invention. And, FIG. 8 illustrates the operation of a conventional DRAM cell 701. As shown in FIG. 7A, the embodiment consists of a gate insulator stack having insulator layers, 710, 708 and 718, e.g. SiO2/oxide insulator nanolaminate layers/SiO2. In the embodiment of FIG. 7A, the gate insulator stack having insulator layers, 710, 708 and 718, is made thicker than in a conventional DRAM cell, e.g. 801 and is equal to or greater than 10 nm or 100 Å (10−6 cm). In the embodiment shown in FIG. 7A a transistor cell is illustrated having dimensions of 0.1 μm (10−5 cm) by 0.1 μm. The capacitance, Ci, of the structure depends on the dielectric constant, ∈i, (given here as 0.3�10−12 F/cm), and the thickness of the insulating layers, t, (given here as 10−6 cm), such that Ci=∈i/t, Farads/cm2 or 3�10−7 F/cm2. In one embodiment, a charge of 1012 electrons/cm2 is programmed into the oxide insulator nanolaminate layers of the transistor cell. Here the charge carriers become trapped in potential wells in the oxide insulator nanolaminate layers 708 formed by the different electron affinities of the insulators 710, 708 and 718, as shown in FIG. 7A. This produces a stored charge ΔQ=1012 electrons/cm2�1.6�10−19 Coulombs. In this embodiment, the resulting change in the threshold voltage (ΔVt) of the transistor cell will be approximately 0.5 Volts (ΔVt=ΔQ/Ci or 1.6�10−7/3�10−7=� Volt). For ΔQ=1012 electrons/cm3 in the dimensions given above, this embodiment of the present invention involves trapping a charge of approximately 100 electrons in the oxide insulator nanolaminate layers 708 of the transistor cell.
Conversely, if the nominal threshold voltage without the oxide insulator nanolaminate layers charged is � V, then I=μCox�(W/L)�((Vgs−Vt)2/2), or 12.5 μA, with μCox=μCi=100 μA/V2 and W/L=1. That is, the transistor cell of the present invention, having the dimensions describe above will produce a current I=100 μA/V2�(�)�(�)=12.5 μA. Thus, in the present invention an un-written, or un-programmed transistor cell can conduct a current of the order 12.5 μA, whereas if the oxide insulator nanolaminate layers are charged then the transistor cell will not conduct. As one of ordinary skill in the art will understand upon reading this disclosure, the sense amplifiers used in DRAM arrays, and as describe above, can easily detect such differences in current on the bit lines.
According to the teachings of the present invention, the transistor cells, having the gate structure with oxide insulator nanolaminate layers, in the array are utilized not just as passive on or off switches as transfer devices in DRAM arrays but rather as active devices providing gain. In the present invention, to program the transistor cell �off,� requires only a stored charge in the oxide insulator nanolaminate layers of about 100 electrons if the area is 0.1 μm by 0.1 μm. And, if the transistor cell is unprogrammed, e.g. no stored charge trapped in the oxide insulator nanolaminate layers, and if the transistor cell is addressed over 10 nS a current of 12.5 μA is provided. The integrated drain current then has a charge of 125 fC or 800,000 electrons. This is in comparison to the charge on a DRAM capacitor of 50 fC which is only about 300,000 electrons. Hence, the use of transistor cells, having the gate structure with oxide insulator nanolaminate layers, in the array as active devices with gain, rather than just switches, provides an amplification of the stored charge, in the oxide insulator nanolaminate layers, from 100 to 800,000 electrons over a read address period of 10 nS.
In this embodiment, each of the interconnect lines 1014 acts as a NOR gate for the input lines 1012 that are connected to the interconnect lines 1014 through the thin oxide gate transistors, 1001-1, 1001-2, . . . , 1001-N, of the array. For example, interconnection line 1014A acts as a NOR gate for the signals on input lines 1012A and 1012B. That is, interconnect line 1014A is maintained at a high potential unless one or more of the thin oxide gate transistors, 1001-1, 10041-2, . . . , 1001-N, that are coupled to interconnect line 1014A are turned on by a high logic level signal on one of the input lines 1012. When a control gate address is activated, through input lines 1012, each thin oxide gate transistor, e.g. transistors 1001-1, 1001-2, . . . , 1001-N, conducts which performs the NOR positive logic circuit function, an inversion of the OR circuit function results from inversion of data onto the interconnect lines 1014 through the thin oxide gate transistors, 1001-1, 1001-2, . . . , 1001-N, of the array.
Driver transistors, 1102-1, 1102-2, . . . , 1102-N not having their corresponding gate structure with oxide insulator nanolaminate layers charged operate in either an on state or an off state, wherein signals received by the interconnect lines 1114 determine the applicable state. If any of the interconnect lines 1114 are turned on, then a ground is provided to load device transistors 1124 by applying a ground potential to the source line or conductive source plane coupled to the transistors first source/drain region as described herein. The load device transistors 1124 are attached to the output lines 1120. The load device transistors 1124 provide a low voltage level when any one of the driver transistors, 1102-1, 1102-2, . . . , 1102-N connected to the corresponding output line is activated. This performs the NOR logic circuit function, an inversion of the OR circuit function results from inversion of data onto the output lines 1120 through the driver transistors, 1102-1, 1102-2, . . . , 1102-N of the array 1100. When the driver transistors, 1102-1, 1102-2, . . . , 1102-N are in an off state, an open is provided to the drain of the load device transistors 1124. The VDD voltage level is applied to corresponding output lines 1120 for. second logic plane 1122 when a load device transistor 1124 is turned on by a clock signal received at the gate of the load device transistors 1124. In this manner a NOR-NOR electrically programmable logic array is most easily implemented utilizing the normal PLA array structure. Each of the driver transistors, 1102-1, 1102-2, . . . , 1102-N described herein are formed according to the teachings of the present, having a gate structure with oxide insulator nanolaminate layers.
Programming can be achieved by hot electron injection. In this case, the interconnect lines, coupled to the second source/drain region for the transistor cells in the first logic plane, are driven with a higher drain voltage like 2 Volts for 0.1 micron technology and the control gate line is addressed by some nominal voltage in the range of twice this value. Erasure is accomplished by driving the control gate line with a large positive voltage and the sourceline and/or backgate or substrate/well address line of the transistor with a negative bias so the total voltage difference is in the order of 3 Volts causing electrons to tunnel out of the oxide insulator nanolaminate layers of the driver transistors. Writing can be performed, as also described above, by normal channel hot electron injection
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3357961May 24, 1965Dec 12, 1967Exxon Research Engineering CoCopolymers of ethylene and hexadiene 1, 5US3381114Dec 18, 1964Apr 30, 1968Nippon Electric CoDevice for manufacturing epitaxial crystalsUS3641516Sep 15, 1969Feb 8, 1972IbmWrite once read only store semiconductor memoryUS3665423Mar 13, 1970May 23, 1972Nippon Electric CoMemory matrix using mis semiconductor elementUS3877054Nov 8, 1973Apr 8, 1975Bell Telephone Labor IncSemiconductor memory apparatus with a multilayer insulator contacting the semiconductorUS3918033Nov 11, 1974Nov 4, 1975IbmSCR memory cellUS3964085Aug 18, 1975Jun 15, 1976Bell Telephone Laboratories, IncorporatedMethod for fabricating multilayer insulator-semiconductor memory apparatusUS3978577Jun 30, 1975Sep 7, 1976International Business Machines CorporationFixed and variable threshold N-channel MNOSFET integration techniqueUS4058430Nov 25, 1975Nov 15, 1977Tuomo SuntolaMethod for producing compound thin filmsUS4152627Jun 10, 1977May 1, 1979Monolithic Memories Inc.Low power write-once, read-only memory arrayUS4173791Sep 16, 1977Nov 6, 1979Fairchild Camera And Instrument CorporationInsulated gate field-effect transistor read-only memory arrayUS4215156Aug 26, 1977Jul 29, 1980International Business Machines CorporationMethod for fabricating tantalum semiconductor contactsUS4217601Feb 15, 1979Aug 12, 1980International Business Machines CorporationNon-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structureUS4295150Oct 1, 1979Oct 13, 1981Itt Industries, Inc.Storage transistorUS4333808Feb 13, 1981Jun 8, 1982International Business Machines CorporationMethod for manufacture of ultra-thin film capacitorUS4394673Sep 29, 1980Jul 19, 1983International Business Machines CorporationRare earth silicide Schottky barriersUS4399424Oct 5, 1981Aug 16, 1983Itt Industries, Inc.Semiconductor films of tin oxide doped with alumins; hydrogen sulfideUS4412902Jun 18, 1982Nov 1, 1983Nippon Telegraph & Telephone Public CorporationMethod of fabrication of Josephson tunnel junctionUS4413022Jun 21, 1979Nov 1, 1983Canon Kabushiki KaishaVapor reactionsUS4449205Feb 19, 1982May 15, 1984International Business Machines Corp.Dynamic RAM with non-volatile back-up storage and method of operation thereofUS4488262Jun 17, 1982Dec 11, 1984International Business Machines CorporationElectronically programmable read only memoryUS4495219Oct 8, 1982Jan 22, 1985Fujitsu LimitedForming oxides of; tantalum, titanium, niobium, hafnium, zirconium, yttrium, vanadium, siliconUS4507673Sep 21, 1983Mar 26, 1985Tokyo Shibaura Denki Kabushiki KaishaSemiconductor memory deviceUS4590042Dec 24, 1984May 20, 1986Tegal CorporationPlasma reactor having slotted manifoldUS4647947Sep 13, 1985Mar 3, 1987Tokyo Shibaura Denki Kabushiki KaishaOptical protuberant bubble recording mediumUS4661833Oct 29, 1985Apr 28, 1987Kabushiki Kaisha ToshibaElectrically erasable and programmable read only memoryUS4717943Jul 16, 1986Jan 5, 1988International Business MachinesCharge storage structure for nonvolatile memoriesUS4725877Apr 11, 1986Feb 16, 1988American Telephone And Telegraph Company, At&T Bell LaboratoriesMinimized interdiffusion without increase in electrical contact resistanceUS4757360Jul 6, 1983Jul 12, 1988Rca CorporationFloating gate memory device with facing asperities on floating and control gatesUS4767641Jul 3, 1986Aug 30, 1988Leybold-Heraeus GmbhHigh frequency discharge between two electrodesUS4780424Sep 28, 1987Oct 25, 1988Intel CorporationNitriding, oxidation, doping, etchingUS4791604Jul 23, 1986Dec 13, 1988Joseph J. BednarzSheet random access memoryUS4794565Sep 15, 1986Dec 27, 1988The Regents Of The University Of CaliforniaElectrically programmable memory device employing source side injectionUS4829482Oct 18, 1985May 9, 1989Xicor, Inc.Current metering apparatus for optimally inducing field emission of electrons in tunneling devices and the likeUS4870470Oct 16, 1987Sep 26, 1989International Business Machines CorporationSilicon, transistorsUS4888733Sep 12, 1988Dec 19, 1989Ramtron CorporationNon-volatile memory cell and sensing methodUS4920071Aug 18, 1987Apr 24, 1990Fairchild Camera And Instrument CorporationHigh temperature interconnect system for an integrated circuitUS4939559Apr 1, 1986Jul 3, 1990International Business Machines CorporationDual electron injector structures using a conductive oxide between injectorsUS4993358Jul 28, 1989Feb 19, 1991Watkins-Johnson CompanyChemical vapor deposition reactor and method of operationUS5006192Nov 21, 1988Apr 9, 1991Mitsubishi Denki Kabushiki KaishaApparatus for producing semiconductor devicesUS5016215Mar 12, 1990May 14, 1991Texas Instruments IncorporatedHigh speed EPROM with reverse polarity voltages applied to source and drain regions during reading and writingUS5017977Jan 19, 1990May 21, 1991Texas Instruments IncorporatedDual EPROM cells on trench walls with virtual ground buried bit linesUS5021999Dec 9, 1988Jun 4, 1991Mitsubishi Denki Kabushiki KaishaNon-volatile semiconductor memory device with facility of storing tri-level dataUS5027171Aug 28, 1989Jun 25, 1991The United States Of America As Represented By The Secretary Of The NavyDual polarity floating gate MOS analog memory deviceUS5032545Oct 30, 1990Jul 16, 1991Micron Technology, Inc.Process for preventing a native oxide from forming on the surface of a semiconductor material and integrated circuit capacitors produced therebyUS5042011May 22, 1989Aug 20, 1991Micron Technology, Inc.Sense amplifier pulldown device with tailored edge inputUS5043946Mar 7, 1990Aug 27, 1991Sharp Kabushiki KaishaSemiconductor memory deviceUS5049516Dec 15, 1989Sep 17, 1991Mitsubishi Denki Kabushiki KaishaMethod of manufacturing semiconductor memory deviceUS5055319Apr 2, 1990Oct 8, 1991The Regents Of The University Of CaliforniaControlled high rate deposition of metal oxide filmsUS5071782Jun 28, 1990Dec 10, 1991Texas Instruments IncorporatedReduced cell area and channel lengthUS5073519Oct 31, 1990Dec 17, 1991Texas Instruments IncorporatedMethod of fabricating a vertical FET device with low gate to drain overlap capacitanceUS5080928Oct 5, 1990Jan 14, 1992Gte Laboratories IncorporatedHydrolysis of vaprized trimethylalminum to form coatingUS5089084Dec 3, 1990Feb 18, 1992Micron Technology, Inc.Hydrofluoric acid etcher and cascade rinserUS5111430Jun 21, 1990May 5, 1992Nippon Telegraph And Telephone CorporationNon-volatile memory with hot carriers transmitted to floating gate through control gateUS5198029Feb 19, 1992Mar 30, 1993Gte Products CorporationPhosphorsUS5253196Jan 9, 1991Oct 12, 1993The United States Of America As Represented By The Secretary Of The NavyDual-writing-polarity, non-volatileUS5274249Dec 20, 1991Dec 28, 1993University Of MarylandSuperconducting field effect devices with thin channel layerUS5280205Apr 16, 1992Jan 18, 1994Micron Technology, Inc.Fast sense amplifierUS5293560Nov 3, 1992Mar 8, 1994Eliyahou HarariMulti-state flash EEPROM system using incremental programing and erasing methodsUS5298447Jul 22, 1993Mar 29, 1994United Microelectronics CorporationMethod of fabricating a flash memory cellUS5302461Jun 5, 1992Apr 12, 1994Hewlett-Packard CompanyDielectric films for use in magnetoresistive transducersUS5303182Nov 6, 1992Apr 12, 1994Rohm Co., Ltd.Nonvolatile semiconductor memory utilizing a ferroelectric filmUS5317535Jun 19, 1992May 31, 1994Intel CorporationGate/source disturb protection for sixteen-bit flash EEPROM memory arraysUS5332915Oct 21, 1992Jul 26, 1994Rohm Co., Ltd.Semiconductor memory apparatusUS5350738Mar 27, 1992Sep 27, 1994International Superconductivity Technology CenterMethod of manufacturing an oxide superconductor filmUS5388069Mar 18, 1993Feb 7, 1995Fujitsu LimitedNonvolatile semiconductor memory device for preventing erroneous operation caused by over-erase phenomenonUS5391510Apr 7, 1994Feb 21, 1995International Business Machines CorporationA diamond-like-carbon layer is used as masking structure to protect gate dielectric layer from contamination during high temperature annealing, removal by plasma etching, forming metal gate electrode in space vacated by masking layerUS5399516Sep 21, 1992Mar 21, 1995International Business Machines CorporationMethod of making shadow RAM cell having a shallow trench EEPROMUS5409859Apr 22, 1994Apr 25, 1995Cree Research, Inc.Method of forming platinum ohmic contact to p-type silicon carbideUS5410504May 3, 1994Apr 25, 1995Ward; Calvin B.Memory based on arrays of capacitorsUS5418389Nov 9, 1993May 23, 1995Mitsubishi Chemical CorporationField-effect transistor with perovskite oxide channelUS5424993Nov 15, 1993Jun 13, 1995Micron Technology, Inc.Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory deviceUS5426603Jan 25, 1994Jun 20, 1995Hitachi, Ltd.Dynamic RAM and information processing system using the sameUS5430670Nov 8, 1993Jul 4, 1995Elantec, Inc.Differential analog memory cell and method for adjusting sameUS5434815Jan 19, 1994Jul 18, 1995Atmel CorporationStress reduction for non-volatile memory cellUS5438544Jan 28, 1994Aug 1, 1995Fujitsu LimitedNon-volatile semiconductor memory device with function of bringing memory cell transistors to overerased state, and method of writing data in the deviceUS5445984Nov 28, 1994Aug 29, 1995United Microelectronics CorporationMethod of making a split gate flash memory cellUS5449941Oct 27, 1992Sep 12, 1995Semiconductor Energy Laboratory Co., Ltd.Semiconductor memory deviceUS5455792Sep 9, 1994Oct 3, 1995Yi; Yong-WanFlash EEPROM devices employing mid channel injectionUS5457649Aug 26, 1994Oct 10, 1995Microchip Technology, Inc.Semiconductor memory device and write-once, read-only semiconductor memory array using amorphous-silicon and method thereforUS5467306Oct 4, 1993Nov 14, 1995Texas Instruments IncorporatedMethod of using source bias to increase threshold voltages and/or to correct for over-erasure of flash epromsUS5477485Feb 22, 1995Dec 19, 1995National Semiconductor CorporationMethod for programming a single EPROM or FLASH memory cell to store multiple levels of data that utilizes a floating substrateUS5485422Jun 2, 1994Jan 16, 1996Intel CorporationMemory deviceUS5488243Dec 3, 1993Jan 30, 1996Nippondenso Co., Ltd.SOI MOSFET with floating gateUS5493140Jun 21, 1994Feb 20, 1996Sharp Kabushiki KaishaNonvolatile memory cell and method of producing the sameUS5497494Jul 23, 1993Mar 5, 1996International Business Machines CorporationIn a computer systemUS5498558May 6, 1994Mar 12, 1996Lsi Logic CorporationIntegrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making sameUS5508543Apr 29, 1994Apr 16, 1996International Business Machines CorporationLow voltage memoryUS5508544Sep 27, 1994Apr 16, 1996Texas Instruments IncorporatedThree dimensional FAMOS memory devicesUS5510278Sep 6, 1994Apr 23, 1996Motorola Inc.Method for forming a thin film transistorUS5522932May 14, 1993Jun 4, 1996Applied Materials, Inc.Corrosion-resistant apparatusUS5530581May 31, 1995Jun 25, 1996Eic Laboratories, Inc.Protective overlayer material and electro-optical coating using sameUS5530668Apr 12, 1995Jun 25, 1996Ramtron International CorporationFerroelectric memory sensing scheme using bit lines precharged to a logic one voltageUS5539279Dec 22, 1994Jul 23, 1996Hitachi, Ltd.Ferroelectric memoryUS5541871Jan 18, 1995Jul 30, 1996Rohm Co., Ltd.Nonvolatile ferroelectric-semiconductor memoryUS5541872May 26, 1995Jul 30, 1996Micron Technology, Inc.Folded bit line ferroelectric memory deviceUS5550770Jun 2, 1995Aug 27, 1996Hitachi, Ltd.Semiconductor memory device having ferroelectric capacitor memory cells with reading, writing and forced refreshing functions and a method of operating the sameUS5557569May 25, 1995Sep 17, 1996Texas Instruments IncorporatedLow voltage flash EEPROM C-cell using fowler-nordheim tunnelingUS5562952Apr 4, 1995Oct 8, 1996Nissin Electric Co., Ltd.Plasma-CVD method and apparatusUS6377070 *Feb 9, 2001Apr 23, 2002Micron Technology, Inc.In-service programmable logic arrays with ultra thin vertical body transistorsUS20040168145 *Feb 27, 2004Aug 26, 2004Micron Technology, Inc.Service programmable logic arrays with low tunnel barrier interpoly insulatorsUS20060284246 *Jul 20, 2006Dec 21, 2006Micron Technology, Inc.Memory utilizing oxide nanolaminatesUS20090002025 *Sep 5, 2008Jan 1, 2009Micron TechnologyMemory utilizing oxide nanolaminates* Cited by examinerNon-Patent CitationsReference1Aarik, Jaan, "Texture development in nanocrystalline hafnium dioxide thin films grown by atomic layer deposition", Journal of Crystal Growth, 220(1-2), (Nov. 15, 2000), 105-113.2Abbas, S. A., et al., "N-Channel Igfet Design Limitations Due to Hot Electron Trapping", Technical Digest, International Electron Devices Meeting,, Washington, DC, (Dec. 1975), 35-38.3Adelmann, C, et al., "Atomic-layer epitaxy of GaN quantum wells and quantum dots on (0001) AIN", Journal of Applied Physics, 91(8), (Apr. 15, 2002), 5498-5500.4Adler, E., et al., "The Evolution of IBM CMOS DRAM Technology", IBM Journal of Research & Development, 39(1-2), (Jan.-Mar. 1995), 167-188.5Ahn, Seong-Deok, et al., "Surface Morphology Improvement of Metalorganic Chemical Vapor Deposition AI Films by Layered Deposition of AI and Ultrathin TiN", Japanese Journal of Applied Physics, Part 1 (Regular Papers, Short Notes & Review Papers), 39(6A), (Jun. 2000), 3349-3354.6Akasaki, Isamu, et al., "Effects of AIN buffer layer on crystallographic structure and on electrical and optical properties of GaN and Ga 1-x AIx N (0 < x ≰ 0.4) films grown on sapphire substrate by MOVPE", Journal of Crystal Growth, 98(1-2), (Nov. 1, 1989), 209-219.7Akasaki, Isamu, et al., "Effects of AIN buffer layer on crystallographic structure and on electrical and optical properties of GaN and Ga 1-x AIx N (0 < x ≦ 0.4) films grown on sapphire substrate by MOVPE", Journal of Crystal Growth, 98(1-2), (Nov. 1, 1989), 209-219.8Alen, Petra, "Atomic Layer deposition of Ta(AI)N(C) thin films using trimethylaluminum as a reducing agent", Journal of the Electrochemical Society, 148(10), (Oct. 2001), G566-G571.9Alok, D., et al., "Electrical Properties of Thermal Oxide Grown on N-type 6H-Silicon Carbide", Applied Physics Letters, 64, (May 23, 1994), 2845-2846.10Arya, S. P.S., et al., "Conduction properties of thin Al2 03 films", Thin Solid Films, 91 4 , (May 28, 1982), 363-374.11Asari, K, et al., "Multi-mode and multi-level technologies for FeRAM embedded reconfigurable hardware", Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International, (Feb. 15-17, 1999), 106 -107.12Bauer, F, et al., "Design aspects of MOS controlled thyristor elements", International Electron Devices Meeting 1989. Technical Digest, (1989), 297-300.13Benjamin, M., "UV Photoemission Study of Heteroepitaxial AIGaN Films Grown on 6H-SiC", Applied Surface Science, 104/105, (Sep. 1996), 455-460.14Bermudez, V., "The Growth and Properties of AI and AIN Films on GaN(0001)-(1 x 1)", Journal of Applied Physics, 79(1), (Jan. 1996), 110-119.15Bhattacharyya, A., "Physical & Electrical Characteristics of LPCVD Silicon Rich Nitride", ECS Technical Digest, J. Electrochem. Soc., 131(11), 691 RDP, New Orleans, (1984), 469C.16Boeringer, Daniel W., et al., "Avalanche amplification of multiple resonant tunneling through parallel silicon microcrystallites", Physical Rev. B 51, (1995), 13337-13343.17Bright, A A, et al., "Low-rate plasma oxidation of Si in a dilute oxygen/helium plasma for low-temperature gate quality Si/Sio2 interfaces", Applied Physics Letters, 58(6), (Feb. 1991), 619-621.18Britton, J, et al., "Metal-nitride-oxide IC memory retains data for meter reader", Electronics, 45(22), (Oct. 23, 1972), 119-123.19Bunshah, Rointan F, et al., "Deposition Technologies for Films and Coatings: Developments and Applications", Park Ridge, N.J., U.S.A. : Noyes Publications, (1982), 102-103.20Carter, R J, "Electrical Characterization of High-k Materials Prepared by Atomic Layer CVD", IWGI, (2001), 94-99.21Chae, Junghun, et al., "Atomic Layer Deposition of Nickel by the Reduction of Preformed Nickel Oxide", Electrochemical & Solid-State Letters, 5(6), (Jun. 2002), C64-C66.22Chaitsak, Suticai, et al., "Cu(InGa)Se2 thin-film solar cells with high resistivity ZnO buffer layers deposited by atomic layer deposition", Japanese Journal of Applied Physics Part 1-Reqular Papers Short Notes & Review Papers, 38(9A), (Sep. 1999), 4989-4992.23Chang, H R, et al., "MOS trench gate field-controlled thyristor", Technical Digest -International Electron Devices Meeting, (1989), 293-296.24Cheng, Baohong, et al., "The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-100nm MOSFETS's", IEEE Transactions on Electron Devices, 46(7), (Jul. 1999), 1537-1544.25Choi, J D, et al., "A 0.15 um NAND Flash Technology With 0.11 um2 Cell Size for 1 Gbit Flash Memory", IEDM Technical Digest, (2000), 767-770.26Copel, M., et al., "Structure and stability of ultrathin zirconium oxide layers on Si(001)", Applied Physics Letters, 76(4), (Jan. 2000), 436-438.27Cricchi, J R, et al., "Hardened MNOS/SOS electrically reprogrammable nonvolatile memory", IEEE Transactions on Nuclear Science, 24(6), (Dec. 1977), 2185-9.28De Blauwe, J., et al., "A novel, aerosol-nanocrystal floating-gate device for nonvolatile memory applications", IEDM Technical Digest. International Electron Devices Meeting, (Dec. 10-13, 2000), 683-686.29Dekeersmaecker, R., et al., "Electron Trapping and Detrapping Characteristics of Arsenic-Implanted SiO(2) Layers", J. Appl. Phys., 51, (Feb. 1980), 1085-1101.30Demichelis, F., "Influence of Doping on the Structural and Optoelectronic Properties of Amorphous and Microcrystalline Silicon Carbide", Journal of Applied Physics, 72(4), (Aug. 15, 1992), 1327-1333.31Demichelis, F., "Physical Properties of Undoped and Doped Microcrystalline SiC:H Deposited by PECVD", Materials Research Society Symposium Proceedings, 219, Anaheim, CA, (Apr. 30 - May 3, 1991), 413-418.32Desu, S B, "Minimization of Fatigue in Ferroelectric Films", Physica Status Solidi A, 151(2), (1995), 467-480.33Dimaria, D J, "Graded or stepped energy band-gap-insulator MIS structures (GI-MIS or SI-MIS)", Journal of applied Physics, 50(9), (Sep. 1979), 5826-5829.34Dimaria, D., "Graded or stepped energy band-gap-insulator MIS structures (GI-MIS or SI-MIS)", J. Appl. Phys., 50(9), (Sep. 1979), 5826-5829.35Dipert, B., et al., "Flash Memory goes Mainstream", IEE Spectrum, No. 10, (Oct. 1993), 48-50.36Dipert, Brian, "Flash Memory Goes Mainstream", IEEE Spectrum, 30(10), (Oct. 1993), 48-52.37Eierdal, L., et al., "Interaction of oxygen with Ni(110) studied by scanning tunneling microscopy", Surface Science, 312 1-2 , (Jun. 1994), 31-53.38Eitan, Boaz, et al, "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell", IEEE Electron Device Letters, 21(11), (Nov. 2000), 543-545.39Elam, J W, et al., "Kinetics of the WF6 and SI2 H6 surface reactions during tungsten atomic layer deposition", Surface Science, 479(1-3), (May 2001), 121-135.40Eldridge, J. M, et al., "Analysis of ultrathin oxide growth on indium", Thin Solid Films, 12(2), (Oct. 1972), 447-451.41Eldridge, J. M., et al., "Growth of Thin PbO Layers on Lead Films. I. Experiment", Surface Science, 40(3), (Dec. 1973), 512-530.42Eldridge, J., et al., "Measurement of Tunnel Current Density in a Metal-Oxide-Metal System as a Function of Oxide Thickness", Proc. 12th Intern. Conf. On Low Temperature Physics, (1971), 427-428.43Ferguson, J D, et al., "Atomic layer deposition of AI2O3 and SiO2 on BN particles using sequential surface reactions", Applied Surface Science, 162-163, (Aug. 1, 2000), 280-292.44Ferris-Prabhu, A V, "Amnesia in layered insulator FET memory devices", 1973 International Electron Devices Meeting Technical Digest, (1973), 75-77.45Ferris-Prabhu, A V, "Charge transfer in layered insulators", Solid-State Electronics, 16(9) , (Sep. 1973), 1086-7.46Ferris-Prabhu, A V, "Tunnelling theories of non-volatile semiconductor memories", Physica Status Solidi A, 35(1), (May 16, 1976), 243-50.47Fisch, D E, et al., "Analysis of thin film ferroelectric aging", Proc. IEEE Int Reliability Physics Symp., (1990), 237-242.48Forbes, L., et al., "Field Induced Re-Emission of Electrons Trapped in SiO", IEEE Transactions on Electron Devices, ED-26 11 , Briefs, (Nov. 1979), 1816-1818.49Frohman-Bentchkowsky, D, "An integrated metal-nitride-oxide-silicon (MNOS) memory", Proceedings of the IEEE, 57(6), (Jun. 1969), 1190-1192.50Goodwins, Rupert, "New Memory Technologies on the Way", http://zdnet.com.com/2100-1103-846950.html, (Feb. 2002).51Greiner, J., "Josephson Tunneling Barriers by rf Sputter Etching in an Oxygen Plasma", Journal of Applied Physics, 42(12), (Nov. 1971), 5151-5155.52Greiner, J., "Oxidation of lead films by rf sputter etching in an oxygen plasma", Journal of applied Physics, 45(1), (Jan. 1974), 32-37.53Grimblot, J., et al., "II. Oxidation of Aluminum Films", Journal of the Electrochemical Society, 129(10), (1982), 2369-2372.54Grimblot, Jean, et al., "I. Interaction of AI films with O2 at low pressures", Journal Of the Electrochemical Society, 129(10), (1982), 2366-2368.55Gundlach, K., et al., "Logarithmic conductivity of AI-AI2/O3-Al tunneling junctions produced by plasma- and by thermal-oxidation", Surface Science, 27(1), (Aug. 1971,) 125-141.56Guo, X., "High Quality Ultra-thin (1.5 nm) High quality ultra-thin (1.5 nm) TiO2-Si3 Nb4 gate dielectric for deep sub-micron CMOS technology", International Electron Devices Meeting. 1999. Technical Digest, (1999), 137-140.57Han, Kwangseok, "Characteristics of P-Channel Si Nano-Crystal Memory", IEDM Technical Digest, International Electron Devices Meeting, (Dec. 10-13, 2000), 309-312.58Hodges, D. A., "Analysis and Design of Digital Integrated Circuits, 2nd Edition", McGraw-Hill Publishing. New York, (1988), 354-357.59Hodges, D. A., et al., "Analysis and Design of Digital Integrated Circuits", McGraw-Hill Book Company, 2nd Edition, (1988), 394-396.60Hurych, Z., "Influence of Non-Uniform Thickness of Dielectric Layers on Capacitance and Tunnel Currents", Solid-State Electronics, 9, (1966), 967-979.61Hwang, C G, "Semiconductor Memories for the IT Era", 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers IEEE. Part vol. 1, San Francisco, (2002), 24-27.62Hwang, N., et al., "Tunneling and Thermal Emission of Electrons at Room Temperature and Above from a Distribution of Deep Traps in SiO2", Proc. Int'l Elec. Devices and Materials Symp., Taiwan, (Nov. 1992), 559-562.63Inumiya, S, et al., "Conformable formation of high quality ultra-thin amorphous Ta2 O5 gate dielectrics utilizing water assisted deposition (WAD) for sub 50 nm damascene metal gate MOSFETs", IEDM Technical Digest. International Electron Devices Meeting, (Dec. 10-13, 2000), 649-652.64Itokawa, H, "Determination of Bandgap and Energy Band Alignment for HighDielectric-Constant Gate Insulators Using High-Resolution X-ray Photoelectron Spectroscopy", Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, (1999), 158-159.65Juppo, Marika, "Use of 1,1-Dimethylhydrazine in the Atomic Layer Deposition of Transition Metal Nitride Thin Films", Journal of the Electrochemical Society, 147(9), (Sep. 2000), 3377-3381.66Kim, H., "Leakage current and electrical breakdown in metal-organic chemical vapor deposited TiO2 dielectrics on silicon substrates", Applied Physics Letters, 69(25), (Dec. 16, 1996), 3860-3862.67Kim, Y, "Substrate dependence on the optical properties of AI2O3 films grown by atomic layer deposition", Applied Physics Letters, vol. 71, No. 25, (Dec. 22, 1997), 3604-3606.68Kim, Yeong K, et al., "Novel capacitor technology for high density stand-alone and embedded DRAMs", International Electron Devices Meeting 2000. Technical Digest. IEDM, (2000), 369-372.69Kim, Yong S, et al., "Effect of rapid thermal annealing on the structure and the electrical properties of atomic-layer-deposited Ta2O5 films", Journal of the Korean Physical Society, (Dec. 2000), 975-979.70Klaus, J W, et al., "Atomic layer deposition of tungsten nitride films using sequential surface reactions", Journal of the Electrochemical Society, 147(3), (Mar. 2000), 1175-81.71Koo, J, "Study on the characteristics of TiAIN thin film deposited by atomic layer deposition method", Journal of Vacuum Science & Technology A-Vacuum Surfaces & Films, (Nov. 2001), 2831-4.72Kubaschewski, O., et al., "Oxidation of Metals and Alloys", Butterworths, London, (1962), 53-63.73Kubaschewski, O., et al., "Oxidation of Metals and Alloys,", Butterworths, London, Second Edition, (1962), 1-3, 5,6, 8-12, 24, 36-39.74Kukli, Kaupo, "Dielectric Properties of Zirconium Oxide Grown by Atomic Layer Deposition from Iodide Precursor", Journal of the Electrochemical Society, 148(12), (2001), F227-F232.75Kukli, Kaupo, "Tailoring the dielectric properties of HfO2-Ta2O3 nanolaminates", Appl. Phys. Lett., 68, (1996), 3737-3739.76Kukli, Kaupo, et al., "Atomic layer deposition of zirconium oxide from zirconium tetraiodide, water and hydrogen peroxide", Journal of Crystal Growth, 231(1-2), (Sep. 2001), 262-272.77Kukli, Kaupo, et al., "Real-time monitoring in atomic layer deposition of TiO2 from TiI4 and H2O-H2O2", Langmuir, 16(21), (Oct. 17, 2000), 8122-8128.78Kukli, Kukli, et al., "Development of Dielectric Properties of Niobium Oxide, Tantalum Oxide, and Aluminum Oxide Based Nanolayered Materials", Journal of the Electrochemical Society, 148(2), (Feb. 2001), F35-F41.79Kumar, M. Jagadesh, "Lateral Schottky Rectifiers for Power Integrated Circuits", International Workshop on the Physics of Semiconductor Devices,11th, 4746, Allied Publishers Ltd., New Delhi, India, (2002), 414-421.80Kwo, J., "Properties of high k gate dielectrics Gd2O3 and Y2O3 for Si", Journal of Applied Physics, 89(7), (2001), 3920-3927.81Lai, S K, et al., "Comparison and trends in Today's dominant E2 Technologies", IEDM Technical Digest, (1986), 580-583.82Lee, A E, et al., "Epitaxially grown sputtered LaAIO3 films", Applied Physics Letters, 57(19), (Nov. 1990), 2019-2021.83Lee, Cheng-Chung, et al., "Ion-assisted deposition of silver thin films", Thin Solid Films, 359(1), (Jan. 2000), 95-97.84Lee, Dong Heon, et al., "Metalorganic chemical vapor deposition of TiO2:N anatase thin film on Si substrate", Applied Physics Letters, 66(7), (Feb. 1995), 815-816.85Lee, J., et al., "Effect of polysilicon gate on the flatband voltage shift and mobility degradation for ALD-AI2O3 gate dielectric", International Electron Devices Meeting 2000. Technical Digest. IEDM, (2000), 645-648.86Lee, L P, et al., "Monolithic 77 k dc SQUID magnetometer", Applied Physics Letters, 59(23), (Dec. 1991), 3051-3053.87Lee, M., et al., "Thermal Self-Limiting Effects in the Long-Term AC Stress on N-Channel LDD MOSFET's", Proc.: 9th Biennial University/Government/Industry Microelectronics Symp., Melbourne, FL, (Jun. 1991), 93-97.88Lee, Y. K, et al., "Multi-level vertical channel SONOS nonvolatile memory on SOI"2002 Symposium on VLSI Technology, 2002. Digest of Technical Papers., Digest of Technical Vapours, (Jun. 11, 2002), 208-209.89Lei, T., "Epitaxial Growth and Characterization of Zinc-Blende Gallium Nitride on (001) Silicone", Journal of Applied Physics, 71(10), (May 1992), 4933-4943.90Leskela, M, "ALD precursor chemistry: Evolutions and future challenges", Journal de Physique IV (Proccedings), 8(8), (Sep. 1999), 837-752.91Liu, Y C, et al., "Growth of ultrathin SiO2 on Si by surface irradiation with an O2 +Ar electron cyclotron resonance microwave plasma at low temperatures", Journal of Applied Physics, 85(3), (Feb. 1999), 1911-1915.92Liu, Z., et al., "Low Programming Voltages and Long Retention Time in Metal Nanocrystal EEPROM Devices", Digest of the IEEE Device Research Conference, Notre Dame, Indiana, (Jun. 25-27, 2001), 79-80.93Luan, H., "High Quality Ta2O5 Gate Dielectrics with Tox,eq less than 10A", IEDM, (1999), 141-144.94Lucovsky, G, et al., "Microscopic model for enhancing dielectric constants in low concentration SiO2-rich noncrystalline Zr and Hf silicate alloys", Applied Physics Letters, 77(18), (Oct. 2000), 2912-2914.95Lui, C. T., "Circuit Requirement and Integration Challenges of Thin Gate Dielectrics for Ultra Small MOSFETs", International Electron Devices Meeting 1998. Technical Digest, (1998), 747-750.96Lusky, et al., "Characterization of channel hot electron injection by the subthreshold slope of NROM/sup TM/ device", IEEE Electron Device Letters, 22(11), (Nov. 2001), 556-558.97Ma, Yanjun, et al., "Zirconium oxide based gate dielectrics with equivalent oxide thickness of less than 1.0 nm and performance of submicron MOSFET using a nitride gate replacement process", International Electron Devices Meeting 1999. Technical Digest, (1999), 149-152.98Maayan, E., et al., "A 512Mb BROM Flash Data Storage: Memory with 8MB/s Data Rate", ISSCC 2002 / Session 6 / SRAM and Non-Volatile Memories, (Feb. 2002), 4 pgs.99Manchanda, L., "High K Dielectrics for MCOS and Flas"Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, Tokyo, (1999), 150-151.100Manchanda, L., "Si-doped aluminates for high temperature metal-gate CMOS: Zr-AI-Si-O, a novel gate dielectric for low power applications", IEDM Technical Digest. International Electron Devices Meeting, (Dec. 10-13, 2000), 23-26.101Manchanda, L., et al., "High-K Dielectrics for Giga-Scale CMOS and Non-Volatile Memory Technology", Lucent Technologies, Bell Laboratories, (2000), 1 page.102Marlid, Bjorn, et al., "Atomic layer deposition of BN thin films", Thin Solid Films, 402(1-2), (Jan. 2002), 167-171.103Marshalek, R., et al., "Photoresponse Characteristics of Thin-Film Nickel-Nickel Oxide-Nickel Tunneling Junctions", IEEE Journal of Quantum Electronics, QE-19(4), (1983), 743-754.104Martin, P. J, et al., "Ion-beam-assisted deposition of thin films", Applied Optics, 22(1), (Jan. 1983), 178-184.105Martins, R, "Transport Properties of Doped Silicon Oxycarbide Microcrystalline Films Produced by Spatial Separation Techniques", Solar Energy Materials and Solar Cells, 41-42, (1996), 493-517.106Martins, R., "Wide Band Gap Microcrystalline Silicon Thin Films", Diffusion and Defect Data : Solid State Phenomena, 44-46, Part 1, Scitec Publications, (1995), 299-346.107Masuoka, F., et al., "A 256K Flash EEPROM using Triple Polysilicon Technology", IEEE International Solid-State Circuits Conference, Digest of Technical Papers,.108Masuoka, F., et al., "A New Flash EEPROM Cell using Triple Polysilicon Technology", International Electron Devices Meeting, Technical Digest, San Francisco (1985), 168-169.109Min, J., "Metal-organic atomic-layer deposition of titanium-silicon-nitride films", Applied Physics Letters, 75(11), (1999), 1521-1523.110Min, Jae-Sik, et al., "Atomic layer deposition of TiN films by alternate supply of tetrakis (ethylmethylamino)-titanium and ammonia", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 37(9A), (Sep. 1998), 4999-5004.111Moazzami, R, "Endurance properties of ferroelectric PZT thin films", Technical Digest., International Electron Devices Meeting, 1990. IEDM '90., San Francisco, (1990), 417-420.112Moazzami, R, "Ferroelectric PZT thin films for semiconductor memory", Ph.D Thesis, University of California, Berkeley, (1991).113Molnar, R., "Growth of Gallium Nitride by Electron-Cyclotron Resonance Plasma-Assisted Molecular-Beam Epitaxy: The Role of Charged Species", Journal of Applied Physics, 76(8), (Oct. 1994), 4587-4595.114Molodyk, A A, et al., "Volatile Surfactant-Assisted MOCVD: Application to LaAIO3 Thin Film Growth", Chemical Vapor Deposition, 6(3), (Jun. 2000), 133-138.115Molsa, Heinz, et al., "Growth of yttrium oxide thin films from beta -diketonate precursor", Advanced Materials for Optics and Electronics, 4(6), (Nov.-Dec. 1994), 389-400.116Mori, S., et al., "Reliable CVD Inter-Poly Dielectrics for Advanced E&EEPROM", Symposium on VSLI Technology, Digest of Technical Papers, (1985), 16-17.117Morishita, S, "Atomic-layer chemical-vapor-deposition of SiO2 by cyclic exposures of CH3OSi(Nco)3 and H2O2", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 34(10), (Oct. 1995), 5738-5742.118Moriwaki, Masaru, et al., "Improved metal gate process by simultaneous gate-oxide nitridation during W/WN/sub x/gate formation", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 39(4B), (Apr. 2000), 2177-2180.119Muller, D. A., "The electronic structure at the atomic scale of ultrathin gate oxides", Nature, 399, (Jun. 24, 1999), 758-61.120Muller, H., "Electrical and Optical Properties of Sputtered In2O3 Films", Physica Status Solidi, 27(2), (1968), 723-731.121Muller, R. S, et al., "", In: Device Electronics for Integrated Circuits, Second Edition, John Wiley & Sons, New York, (1986), p. 157.122Nakagawara, Osamu, et al., "Electrical properties of (Zr, Sn)TiO4 dielectric thin film prepared by pulsed laser deposition", Journal of Applied Physics, 80(1), (Jul. 1996), 388-392.123Nakajima, Anri, "Soft breakdown free atomic-layer-deposited silicon-nitride/SiO2 stack gate dielectrics", International Electron Devices Meeting. Technical Digest, (2001), 6.5.1-4.124Nakajima, Anri, et al., "NH3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability", Applied Physics Letters, 80(7), (Feb. 2002), 1252-1254.125Nemati, F, et al., "A novel high density, low voltage SRAM cell with a vertical NDR device", 1998 Symposium on VLSI Technology Digest of Technical Papers, (1998), 66-7.126Nemati, F, et al., "A novel thyristor-based Sram cell (T-RAM) for high-speed, low-voltage, giga-scale memories", International Electron Devices Meeting 1999. Technical Digest, (1999), 283-286.127Neumayer, D A, et al., "Materials characterization of ZrO2 -SiO2 and HfO2 -SiO2 binary oxides deposited by chemical solution deposition", Journal of Applied Physics, 90(4), (Aug. 15, 2001), 1801-1808.128Nieminen, Minna, et al., "Formation and stability of lanthanum oxide thin films deposited from B-diketonate precursor", Applied Surface Science, 174(2), (Apr. 16, 2001), 155-165.129Niilisk, A, "Atomic-scale optical monitoring of the initial growth of TiO2 thin films", Proceedings of the SPIE - The International Society for Optical Engineering, 4318, (2001), 72-77.130Ohba, R., et al., "Non-volatile Si quantum memory with self-aligned doubly-stacked dots", IEDM Technical Digest. International Electron Devices Meeting, (Dec. 10-13, 2000), 313-316.131Ohkawa, M., et al., "A 98 mm2 3.3 V 64 Mb flash memory with FN-NOR type 4-level cell", 1996 IEEE International Solid-State Circuits Conference, 1996. Digest of Technical Papers. 43rd ISSCC., (1996), 36-37.132Ohring, Milton, "The Materials Science of Thin Films", Boston : Academic Press, (1992), 118,121,125.133Ohsawa, Takashi, et al., "Memory design using one-transistor gain cell on SOI", IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. 1, (2002), 452-455.134Okhonin, S., et al., "A SOI capacitor-less 1T-DRAM concept", 2001 IEEE International SOI Conference. Proceedings, IEEE. 2001, (2000), 153-154.135Or, S. S.B., et al., "Thermal Re-Emission of Trapped Hot Electrons in NMOS Transistors", IEEE Trans. On Electron Devices, 38(12), (Dec. 1991), 2712.136Osten, H. J., et al., "High-k gate dielectrics with ultra-low leakage current based on praseodymium oxide", International Electron Devices Meeting 2000. Technical Digest IEDM, (2000), 653-656.137Pan, Tung Ming, et al., "High quality ultrathin CoTiO3 high-k gate dielectrics", Electrochemical and Solid-State Letters, 3(9), (Sep. 2000), 433-434.138Pan, Tung Ming, et al., "High-k cobalt-titanium oxide dielectrics formed by oxidation of sputtered Co/Ti or Ti/Co films", Applied Physics Letters, 78(10), (Mar. 5, 2001), 1439-1441.139Pankove, J., "Photoemission from GaN", Applied Physics Letters, 25(1), (Jul. 1, 1974), 53-55.140Papadas, C., "Modeling of the Intrinsic Retention Characteristics of Flotox Eeprom Cells Under Elevated Temperature Conditions", IEEE Transaction on Electron Devices, 42, (Apr. 1995), 678-682.141Paranjpe, Ajit, et al., "Atomic layer deposition of AlOx for thin film head gap applications", Journal of the Electrochemical Society, 148(9), (Sep. 2001), 465-471.142Park, Byung-Eun, et al., "Electrical properties of LaAIO3 Si and Sr0.8Bi2�2Ta2O9/LaAIO3/Si structures", Applied Physics Letters, 79(6), (Aug. 2001), 806-808.143Park, Jin-Seong, et al., "Plasma-Enhanced Atomic Layer Deposition of Tantalum Nitrides Using Hydrogen Radicals as a Reducing Agent", Electrochemical & Solid-State Letters, 4(4), (Apr. 2001), C17-C19.144Pashley, R., et al., "Flash Memories: the best of two worlds", IEEE Spectrum, 26(12), (Dec. 1989), 30-33.145Perkins, Charles M, et al., "Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition", Applied Physics Letters, 78(16), (Apr. 2001), 2357-2359.146Pollack, S., et al., "Tunneling Through Gaseous Oxidized Films of AI2O3", Transactions of the Metallurgical Society of AIME, 233, (1965), 497-501.147Puurunen, R L, et al., "Growth of aluminum nitride on porous silica by atomic layer chemical vapour deposition", Applied Surface Science, 165(2-3), (Sep. 12, 2000), 193-202.148Qi, Wen-Jie, et al., "Performance of MOSFETs with ultra thin ZrO2 and Zr silicate gate dielectrics", 2000 Symposium on VLSI Technology. Digest of Technical Papers, (2000), 40-41.149Qi, Wen-Me, et al., "MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposited directly on Si", Electron Devices Meeting, 1999. IEDM Technical Digest International, (1999), 145-148.150Ramakrishnan, E S, et al., "Dielectric properties of radio frequency magnetron sputter deposited zirconium titanate-based thin films", Journal of the Electrochemical Society, 145(1), (Jan. 1998), 358-362.151Rayner Jr., G, et al., "The structure of plasma-deposited and annealed pseudo-binary ZrO2-SiO2 alloys", Materials Research Society Symposium - Proceedings, 611, (2000), C131-C139.152Renlund, G. M., "Silicon oxycarbide glasses: Part I. Preparation and chemistry", J. Mater. Res., (Dec., 1991), pp. 2716-2722.153Renlund, G. M., "Silicon oxycarbide glasses: Part II. Structure and properties", J. Mater. Res., vol. 6, No. 12, (Dec., 1991), pp. 2723-2734.154Ritala, Mikko, "Atomic Layer Epitaxy Growth of Titanium, Zirconium and Hafnium Dioxide Thin Films", Annales Academiae Scientiarum Fennicae, (1994), 24-25.155Ritala, Mikko, "Zirconium dioxide thin films deposited by ALE using zirconium tetrachloride as precursor", Applied Surface Science, 75, (Jan. 1994), 333-340.156Robertson, J., "Band offsets of wide-band-gap oxides and implications for future electronic devices", Journal of Vacuum Science & Technology B (Microelectronics and Nanometer Structures), 18(3), (May-Jun. 2000), 1785-1791.157Robertson, J., et al., "Schottky Barrier height of Tantalum oxide, barium strontium titanate, lead titanate, and strontium bismuth tantalate", Applied Physics Letters, 74(8), (Feb. 22, 1999), 1168-1170.158Rotondaro, A L, et al., "Advanced CMOS Transistors with a Novel HfSiON Gate Dielectric", Symposium on VLSI Technology Digest of Technical Papers, (2002), 148-149.159Saito, Yuji, et al., "Advantage of Radical Oxidation for Improving Reliability of Ultra-Thin Gate Oxide", 2000 Symposium on VLSI Technology Digest of Technical Papers, (2000), 176-177.160Saito, Yuji, et al., "High-Integrity Silicon Oxide Grown at Low-Temperature by Atomic Oxygen Generated in High-Density Krypton Plasma", Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, (1999), 152-153.161Sanders, B W, et al., "Zinc Oxysulfide Thin Films Grown by Atomic Layer Deposition", Chemistry of Materials, 4(5), (1992), 1005-1011.162Schoenfeld, O., et al., "Formation of Si quantum dots in nanocrystalline silicon", Solid-State Electronics, 40(1-8), Proc. 7th Int. Conf. On Modulated Semiconductor Structures, Madrid, (1996), 605-608.163Shanware, A, et al., "Reliability evaluation of HfSiON gate dielectric film with 12.8 A SiO2 equivalent thickness", International Electron Devices Meeting. Technical Digest, (2001), 6.6.1-6.6.4.164She, Min, et al., "Modeling and design study of nanocrystal memory devices", IEEE Device Research Conference, (2001), 139-140.165Shi, Ying, et al., "Tunneling Leakage Current in Ultrathin (<4 nm) Nitride/Oxide Stack Dielectrics", IEEE Electron Device Letters, 19(10), (Oct. 1998), 388-390.166Shimabukuro, R. L., et al., "Circuitry for Artificial Neural Networks with Non-volatile Analog Memories", IEEE Int'l Symp. On Circuits and Systems, 2, (1989), 1217-1220.167Shimabukuro, R. L., et al., "Dual-Polarity Nonvolatile MOS Analogue Memory (MAM) Cell for Neural-Type Circuitry", Electronics Lett., 24, (Sep. 15, 1988), 1231-1232.168Shimada, Hiroyuki, et al., "Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum layer", IEEE Transactions on Electron Devices, vol. 48, No. 8, (Aug. 200), 1619-1626.169Shin, Chang Ho, "Fabrication and Characterization of MFISFET Using AI2O3 Insulating Layer for Non-volatile Memory", 12th International Symposium in Integrated Ferroelectrics, (Mar. 2000), 9 pages.170Shinohe, T, et al., "Ultra-high di/dt 2500 V MOS assisted gate-triggered thyristors (MAGTs) for high repetition excimer laser system", International Electron Devices Meeting 1989. Technical Digest, (1989), 301-304.171Shirota, R, et al., "A 2.3um2 memory cell structure for 16 Mb NAND EEPROMs", International Electron Devices Meeting 1990. Technical Digest, San Francisco, (1990), 1793-1803.172Simmons, J., "Generalized Formula for the Electric Tunnel Effect between Similar Electrodes Separated by a Thin Insulating Film", Journal of Applied Physics, 34(6), (1963), 1793-1803.173Smith, Ryan C, "Chemical vapour deposition of the oxides of titanium, zirconium and hafnium for use as high-k materials in microelectronic devices. A carbon-free precursor for the synthesis of hafnium dioxide", Advanced Materials for Optics and Electronics, 10(3-5), (May-Oct. 2000), 105-106.174Sneh, Ofer, "Thin film atomic layer deposition equipment for semiconductor processing", Thin Solid Films, 402 (1-2), (2002), 248-261.175Solanki, Raj, et al., "Atomic Layer Deposition of Copper Seed Layers", Electrochemical & Solid-State Letters, 3 10 , (Oct. 2000), 479-480.176Song, Hyun-Jung, et al., "Atomic Layer Deposition of Ta2O5 Films Using Ta(OC2H5)5 and NH3", Ultrathin SiO2 and High-K Materials for ULSI Gate Dielectrics. Symposium, (1999), 469-471.177Suh, Kang-Deog, et al., "A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme", IEEE J. Solid-State Circuits, 30, (Nov. 1995), 1149-1156.178Suntola, T., "Atomic Layer Epitaxy", Handbook of Crystal Growth, 3; Thin Films of Epitaxy, Part B: Growth Mechanics and Dynamics, Amsterdam, (1994), 601-663.179Suntola, Tuomo, "Atomic layer epitaxy", Thin Solid Films, 216(1), (Aug. 28, 1992), 84-89.180Swalin, R., "Equilibrium between Phases of Variable Composition", In: Thermodynamics of solids, New York, J. Wiley, 2nd Edition, (1972), 165-180.181Sze, S M, "Physics of Semiconductor Devices", New York : Wiley, (1981), 431.182Sze, S M, "Physics of Semiconductor Devices", New York : Wiley, (1981), 473.183Sze, S M, "Physics of semiconductor devices", New York : Wiley, (1981), 504-506.184Sze, S. M., "Table 3: Measured Schottky Barrier Heights", In: Physics of Semiconductor Devices, John Wiley & Sons, Inc., (1981), 291.185Sze, S., "Physics of Semiconductor Devices, Second Edition", John Wiley & Sons, New York, (1981), 553-556.186Takemoto, J. H., et al., "Microstrip Resonators and Filters Using High-TC Superconducting Thin Films on LaAIO3", IEEE Transaction on Magnetics, 27(2), (Mar. 1991), 2549-2552.187Takeuchi, K., et al., "A Double-Level-V Select Gate Array Architecture for Multilevel Nanad Flash Memories", IEEE Journal of Solid-State Circuits, 31, (Apr. 1996), 602-609.188Tarre, A, et al., "Comparative study of low-temperature chloride atomic-layer chemical vapor deposition of TiO2 and SnO2", Applied Surface Science, 175-176, (May 2001), 111-116.189Thomas, J., et al., "Electron Trapping Levels in Silicon Dioxide Thermally Grown in Silicon", J. Physics and Chemistry of Solids, 33, (1972), 2197-2216.190Thompson, S., et al., "Positive Charge Generation in SiO(2) by Electron-Impact Emission of Trapped Electrons", J. Appl. Phys., 72, (Nov. 1992), 4683-4695.191Thompson, S., et al., "Tunneling and Thermal Emission of Electrons from a Distribution of Shallow Traps in SiO(2)", Appl. Phys. Lett., 58, (Mar. 1991), 1262-1264.192Tiwari, S., et al., "A silicon nanocrystals based memory", Appl. Physics Lett., 68, (1996), 1377-1379.193Tiwari, Sandip, et al., "Volatile and non-volatile memories in silicon with nano-crystal storage", International Electron Devices Meeting IEEE, (Dec. 1995), 521-524.194Tsu, R., et al., "Tunneling in nanoscale silicon particles embedded in an a-SiO2 matrix", 54th Annual Device Research Conference, Digest. IEEE, Abstract, (1996), 178-179.195Tsu, Raphael, et al., "Slow Conductance oscillations in nanoscale silicon clusters of quantum dots", Appl. Phys. Lett., 65, (1994), 842-844.196Van Dover, R B, "Amorphous lanthanide-doped TiOx dielectric films", Applied Physics Letters, 74(20), (May 1999), 3041-3043.197Van Dover, R. B., "Discovery of a useful thin-film dielectric using a composition-spread approach", Nature, 392, (Mar. 12, 1998), 162-164.198Van Dover, Robert B., et al., "Deposition of Uniform Zr-Sn-Ti-O films by ON-Axis Reactive Sputtering", IEEE Electron Device Letters, 19(9), (Sep. 1998), 329-331.199Van Meer, H, "Ultra-thin film fully-depleted SOI CMOS with raised G/S/D device architecture for sub-100 nm applications", 2001 IEEE International SOI Conference, (2001), 45-46.200Viirola, H, "Controlled growth of antimony-doped tin dioxide thin films by atomic layer epitaxy", Thin Solid Films, 251, (Nov. 1994), 127-135.201Viirola, H, et al., "Controlled growth of tin dioxide thin films by atomic layer epitaxy", Thin Solid Films, 249(2), (Sep. 1994), 144-149.202Visokay, M R, "Application of HfSiON as a gate dielectric material", Applied Physics Letters, 80(17), (Apr. 2002), 3183-3185.203Vuillaume, D., et al., "Charging and Discharging Properties of Electron Traps Created by Hot-Carrier Injections in Gate Oxide of N-Channel Metal Oxide Semiconductor Field Effect Transistor", J. Appl. Phys., 73, (Mar. 1993), 2559-2563.204Wei, L S, et al., "Trapping, emission and generation in MNOS memory devices", Solid-State Electronics, 17(6), (Jun. 1974), 591-8.205White, M H, "Direct tunneling in metal-nitride-oxide-silicon (MNOS) structures", Programme of the 31st physical electronics conference, (1971), 1.206White, M H, et al., "Characterization of thin-oxide MNOS memory transistors", IEEE Transactions on Electron Devices, ED-19(12), (Dec. 1972), 1280-1288.207Wilk, G D, et al., "Hafnium and zirconium silicates for advanced gate dielectrics", Journal Of Applied Physics, 87(1), (Jan. 2000), 484-492.208Wilk, G. D., "High-K gate dielectrics: Current status and materials properties considerations", Journal of Applied Physics, 89(10), (May 2001), 5243-5275.209Wolf, S, "Ion Implantation for VLSI", Silicon Processing for the VLSI Era, vol. 1, (1990), 280.210Wolf, S., "MOS devices and NMOS process integration", In: Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, CA, (1990), 319.211Wolf, S., "Thermal oxidation of single crystal oxidation", In: Silicon Processing for the VLSI Era, vol. 1, Lattice Press, Sunset Beach, CA, (1990), 227.212Wolf, Stanley, et al., "Silicon Processing for the VLSI Era - vol. I: Process Technology", Second Edition, Lattice Press, Sunset Beach, California, (2000), 443.213Wood, S W, "Ferroelectric memory design", M.A.Sc. thesis, University of Toronto, (1992), 174 pgs.214Yagishita, Atsushi, et al., "Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) with low threshold voltage, high drive current and uniform electrical characteristics", International Electron Devices Meeting 2000. Technical Digest. IEDM, (Dec. 2000), 663-666.215Yamaguchi, Takeshi, "Band Diagram and Carrier Conduction Mechanism in ZrO2/Zr-silicate/Si MIS Structure Fabricated by Pulsed-laser-ablation Deposition", Electron Devices Meeting, 2000. Iedm Technical Digest. International, (2000), 19-22.216Yan, J., "Structural and electrical characterization of TiO2 grown from titanium tetrakis-isopropoxide (TTIP) and TTIP/H2O ambients", Journal of Vacuum Science & Technology B (Microelectronics and Nanometer Structures), 14(3), (May-Jun. 1996), 1706-1711.217Ye, Qiu-Yi, et al., "Resonant tunneling via microcrystalline-silicon quantum confinement", Phys Rev B Condens Matter., 44(4), (Jul. 15, 1991), 1806-1811.218Yih, C. M., et al., "A Consistent Gate and Substrate Current Model for Sub-Micron MOSFET'S by Considering Energy Transport", Int'l Symp. On VLSI Tech., Systems and Applic., Taiwan, (1995), 127-130.219Yoder, M, "Wide bandgap semiconductor materials and devices", IEEE Transactions on Electron Devices, 43(10), (Oct. 1996), 1633-1636.220Zhang, H., "Atomic Layer Deposition of High Dielectric Constant Nanolaminates", Journal of the Electrochemical Society, 148(4), (Apr. 2001), F63-F66.221Zhao, X., et al., "Nanocrystalline Si: a material constructed by Si quantum dots", Materials Science and Engineering B, 35(1-2), Proceedings of the First International Conference on Low Dimensional Structures and Devices , Singapore, (Dec. 1995), 467-471.222Zhu, W J, et al., "Current transport in metal/hafnium oxide/silicon structure", IEEE Electron Device Letters, 23, (2002), 97-99.223Zhu, W, et al., "HfO2 and HfAIO for CMOS: Thermal Stability and Current Transport", IEEE International Electron Device Meeting 2001, (2001), 463-466.224Zucker, O, et al., "Application of Oxygen Plasma Processing to Silicon Direct Bonding", Sensors and Actuators A, 36, (1993), 227-231.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8228725 *May 28, 2010Jul 24, 2012Micron Technology, Inc.Memory utilizing oxide nanolaminatesUS20130077398 *Sep 14, 2012Mar 28, 2013Lapis Semiconductor Co., Ltd.Nonvolatile semiconductor memory device and programming method* Cited by examinerClassifications U.S. Classification326/41, 326/44, 257/324International ClassificationH01L25/00, H01L27/115, G11C11/56, H03K19/177, H03K19/094, G11C16/04, H01L29/792, H01L29/51Cooperative ClassificationG11C16/0491, H01L29/792, H01L29/517, H01L29/513, H01L29/518, H01L27/115, G11C11/5671, G11C16/0416, G11C16/0466European ClassificationH01L27/115, G11C16/04F1, G11C11/56M, H01L29/51B2, H01L29/792, G11C16/04MLegal EventsDateCodeEventDescriptionOct 30, 2013FPAYFee paymentYear of fee payment: 4Aug 24, 2010CCCertificate of correctionRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google