Source: https://patents.google.com/patent/JP3914651B2/en
Timestamp: 2020-08-12 06:55:01
Document Index: 536973093

Matched Legal Cases: ['art 14', 'art 43', 'art\n2', 'art\n15', 'art\n34', 'art\n44', 'art\n54']

JP3914651B2 - Memory module and manufacturing method thereof - Google Patents
Memory module and manufacturing method thereof Download PDF
JP3914651B2
JP3914651B2 JP05029299A JP5029299A JP3914651B2 JP 3914651 B2 JP3914651 B2 JP 3914651B2 JP 05029299 A JP05029299 A JP 05029299A JP 5029299 A JP5029299 A JP 5029299A JP 3914651 B2 JP3914651 B2 JP 3914651B2
protruding terminal
JP05029299A
JP2000252418A (en
俊夫 宮本
朝雄 西村
1999-02-26 Application filed by エルピーダメモリ株式会社 filed Critical エルピーダメモリ株式会社
1999-02-26 Priority to JP05029299A priority Critical patent/JP3914651B2/en
2000-09-14 Publication of JP2000252418A publication Critical patent/JP2000252418A/en
2007-05-16 Publication of JP3914651B2 publication Critical patent/JP3914651B2/en
239000004065 semiconductor Substances 0.000 claims description 274
239000000758 substrates Substances 0.000 claims description 169
229920000642 polymers Polymers 0.000 claims description 73
239000011347 resins Substances 0.000 claims description 71
239000011295 pitch Substances 0.000 claims description 65
238000009434 installation Methods 0.000 claims description 50
The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique effective when applied to high-density mounting of semiconductor chips in a memory module.
The technology described below has been studied by the present inventors in researching and completing the present invention, and the outline thereof is as follows.
An example of a module product on which a plurality of semiconductor devices are mounted is a memory module.
In this memory module, a plurality of semiconductor devices having memory chips are mounted on one side or both sides of a module substrate. When a memory to be used is installed in a personal computer or workstation, the personal computer or workstation It is mounted on a mother board provided in and mounted with memory in units of modules.
Therefore, as a semiconductor device mounted on a memory module, a semiconductor chip is sealed with a resin, such as TSOP (Thin Small Outline Package) or TCP (Tape Carrier Package), and the sealing formed by this resin sealing is used. A surface mount type semiconductor device called SMD (Surface Mount Devices) having a lead terminal (external terminal) for drawing out an electrode to the outside of the stop portion is used.
As module products, for example, those having various structures are disclosed in, for example, Japanese Patent Laid-Open Nos. 10-209368, 1-258466, and 7-86492.
Japanese Laid-Open Patent Publication No. 10-209368 describes a CPU (Central Processing Unit) module. Japanese Laid-Open Patent Publication No. 1-258466 describes a memory module on which an SMD component having a DRAM (Dynamic Random Access Memory) chip is mounted. Further, Japanese Patent Application Laid-Open No. 7-86492 describes a technique for applying an underfill resin in an MCM (Multi-Chip-Module).
However, the SMD component mounted on the memory module of the above-described technology has a structure in which the package size is larger than the chip size due to the influence of the sealed package body (semiconductor device body) and the outer lead. .
As a result, there is a problem that the number of semiconductor chips that can be mounted on the module substrate is limited.
Another problem is that it is difficult to design a memory module having a high-speed interface to cope with a high-speed CPU due to the effect of inductance added by sealing.
SUMMARY OF THE INVENTION An object of the present invention is to provide a memory module and a method for manufacturing the same that improve the mounting density of semiconductor chips to increase module capacity and realize high-speed bus compatibility.
In other words, the memory module of the present invention includes a protruding terminal as an external terminal, and is mounted via the protruding terminal, and a wiring portion that extends the installation pitch of the protruding terminal more than the installation pitch of the bonding electrode of the semiconductor chip is provided. A protruding terminal semiconductor device provided, an outer lead as an external terminal, and mounted via the outer lead electrically connected to the bonding electrode of the semiconductor chip, and the protruding terminal semiconductor A module substrate supporting the device and the lead terminal semiconductor device, wherein the protruding terminal semiconductor device and the lead terminal semiconductor device are mounted together, and both are mixedly mounted on the module substrate.
Furthermore, the memory module of the present invention includes a projecting terminal as an external terminal and is mounted via the projecting terminal, so that the installation pitch of the projecting terminal is wider than the installation pitch of the bonding electrodes in the area of the semiconductor chip. A chip-sized protruding terminal semiconductor device provided with a rewiring as a wiring portion, and an outer lead as an external terminal and mounted via the outer lead electrically connected to the bonding electrode of the semiconductor chip A terminal semiconductor device; and a module substrate supporting the protruding terminal semiconductor device and the lead terminal semiconductor device, wherein the protruding terminal semiconductor device and the lead terminal semiconductor device are mounted together, both of which are the module It is mixed on the substrate.
Therefore, since the lead terminal semiconductor device and the protruding terminal semiconductor device are mixedly mounted, the protruding terminal semiconductor device can be mounted with a mounting area similar to that of the semiconductor chip.
As a result, the semiconductor chip can be mounted in the smallest area as long as the semiconductor chip is mounted. Therefore, the mounting density of the semiconductor chip can be improved.
As a result, the module capacity in the memory module can be increased.
Also, the method of manufacturing a memory module according to the present invention includes a protruding terminal semiconductor provided with a protruding terminal as an external terminal, and provided with a wiring portion that expands the installation pitch of the protruding terminal more than the installation pitch of the bonding electrodes of the semiconductor chip. A step of preparing a device, a step of preparing a lead terminal semiconductor device including an outer lead which is an external terminal electrically connected to the bonding electrode of the semiconductor chip, and the protruding terminal semiconductor device and the lead terminal semiconductor A step of disposing a device on a module substrate, and a step of simultaneously reflowing the protruding terminal semiconductor device and the lead terminal semiconductor device and mounting them on the module substrate. And the lead terminal semiconductor device are mixedly mounted on the module substrate.
Furthermore, in the method for manufacturing a memory module of the present invention, the rewiring, which is a wiring portion that includes a protruding terminal as an external terminal and widens the installation pitch of the protruding terminal more than the installation pitch of the bonding electrode in the area of the semiconductor chip. Providing a chip-shaped protruding terminal semiconductor device provided; preparing a lead terminal semiconductor device including an outer lead that is an external terminal electrically connected to the bonding electrode of the semiconductor chip; and A step of disposing the protruding terminal semiconductor device and the lead terminal semiconductor device on a module substrate; a step of simultaneously reflowing the protruding terminal semiconductor device and the lead terminal semiconductor device and mounting them on the module substrate; The projecting terminal semiconductor device and the lead terminal semiconductor device are connected to the module base. It is intended to mixed in.
1A and 1B are diagrams showing an example of the structure of a memory module according to Embodiment 1 of the present invention. FIG. 1A is a plan view, FIG. 1B is a side view, and FIG. 2 is an enlarged partial cross-sectional view showing a portion B in the cross-sectional view of FIG. 1C, FIG. 3 is an example of a block circuit diagram of the memory module shown in FIG. 1, and FIG. FIG. 5 is an external perspective view showing an example of the structure of a wafer process package (protruding terminal semiconductor device) mounted on the memory module shown in FIG. 5, and FIG. 5 shows an SMD (surface mounting type having lead terminals) mounted on the memory module shown in FIG. 2 is a diagram showing an example of the structure of a wafer process package and a semiconductor device, which is hereinafter referred to as a lead terminal semiconductor device), (a) is a plan view of the SMD, and (b) is a plan view of the wafer process package. Figure 6 is a diagram A process flow showing an example of a manufacturing process of a wafer process package mounted on the memory module shown in FIG. 7, and FIGS. 7 (a), (b), (c), (d), (e), and (f) are shown in FIG. FIG. 8 is an enlarged partial sectional view showing an example of the structure of a semiconductor wafer corresponding to the main process of the process flow shown. FIG. 8 shows an example of a wafer process package mounted on the memory module shown in FIG. 9 shows a basic mounting flow, FIG. 9 shows a mounting flow showing an example of a mounting procedure of a wafer process package mounted on the memory module shown in FIG. 1 on a module substrate, and FIG. 10 shows a wafer process mounted on the memory module shown in FIG. FIG. 11 is an enlarged partial perspective view showing an example of a resin coating method in a package underfill, and FIG. 11 shows a case where the resin coating of the underfill shown in FIG. 10 is performed. It is a figure which shows an example of the penetration | invasion process of resin, (a), (c), (e), (g) is a perspective view, (b), (d), (f), (h) is a semiconductor chip. FIG. 12 and FIG. 13 are plan views showing the structure of a modification of the memory module according to the first embodiment of the present invention, and FIG. 14 is a modification of the underfill according to the first embodiment of the present invention. It is a figure which shows the penetration | invasion progress of resin at the time of resin application | coating, (a), (c), (e), (g) is a perspective view, (b), (d), (f), (h ) Is a plan view showing through the semiconductor chip, FIG. 15 is a diagram showing a structure of a modification of the memory module according to the first embodiment of the present invention, (a) is a plan view, (b) is a side view, 16 is a side view showing an example of the warped state of the memory module shown in FIG. 15, FIG. 17 is a plan view showing the structure of a modification of the memory module according to Embodiment 1 of the present invention, and FIG. Is a side view showing an example of a warped state of the memory module shown in FIG. 17.
The memory module 100 according to the first embodiment shown in FIG. 1 includes a protruding terminal as an external terminal, is mounted via the protruding terminal, and is more protruded than the installation pitch of the bonding electrodes 1 a of the semiconductor chip 1. A protruding terminal semiconductor device provided with a wiring portion that widens the installation pitch of the terminals and the semiconductor chip 1, an outer lead 21 as an external terminal, and electrically connected to the bonding electrode 1 a of the semiconductor chip 1 A TSOP (Thin Small Outline Package) 20 which is a lead terminal semiconductor device mounted via an outer lead 21, and a module substrate 2 that supports the protruding terminal semiconductor device and the TSOP 20. Both TSOP20 are mounted by simultaneous reflow, and both are mixed on the module board 2. It is what is listed.
Here, in the protruding terminal semiconductor device, a plurality of bump electrodes 11 (projecting terminals) provided as external terminals are arranged in the area of the package body 13 (semiconductor device body) and the semiconductor chip 1 It has a wiring part that widens the installation pitch of the bump electrodes 11 than the installation pitch of the bonding electrodes 1a.
In the lead terminal semiconductor device, a plurality of outer leads 21 provided as external terminals are arranged so as to protrude from the package body 22 (semiconductor device body).
In the protruding terminal semiconductor device and the lead terminal semiconductor device, the bonding electrode 1a of the semiconductor chip 1 is, for example, an electrode formed of aluminum or the like and is electrically connected to the bonding wire when performing wire bonding or the like. It is an electrode connected to.
The protruding terminal semiconductor device and the external terminal in the lead terminal semiconductor device are electrically connected to the connection electrode on the module substrate 2 side when the semiconductor device is mounted on a mounting substrate such as the module substrate 2. Terminal.
In the first embodiment, the case where the protruding terminal semiconductor device is a wafer process package (hereinafter abbreviated as WPP) 10 which is a chip-sized small semiconductor device will be described as an example.
Therefore, the memory module 100 of the first embodiment includes a WPP 10 that is a chip-sized protruding terminal semiconductor device, a TSOP 20 that is an SMD (surface mount package) component and an example of a lead terminal semiconductor device, and other As an example of the lead terminal semiconductor device, an EEPROM (Electrically Erasable Programmable Read Only Memory) 5 which is a nonvolatile read only memory is mounted on the module substrate 2 in a mixed manner.
Here, as shown in FIG. 4, the WPP 10 includes a bump electrode 11 that is a protruding terminal as an external terminal, is mounted on the module substrate 2 via the bump electrode 11, and is bonded within the area of the semiconductor chip 1. This is a protruding terminal semiconductor device provided with a rewiring 12 that is a wiring portion that widens the installation pitch of the bump electrodes 11 than the installation pitch of the electrodes 1a.
When the bump electrode 11 is used for the WPP 10, since the bump electrode 11 has a small variation in height, the mounting defect when mounted on the substrate can be reduced, and as a result, the mounting yield is improved. Further, the bump electrode 11 has a mounting height of about 0.13 mm, and the mounting height can be reduced.
As shown in FIG. 1, in addition to the WPP 10, TSOP 20, and EEPROM 5, other electronic components such as a capacitor 3 and a small imposition resistor 4 are mounted on the memory module 100.
That is, in the memory module 100 of the first embodiment, 18 WPPs 10, 2 TSOPs 20, 18 capacitors 3, and 36 small imposition resistors 4 are provided on one surface of the front and back surfaces. One EEPROM 5 is mounted, and 18 WPPs 10 are also mounted on the other surface on the opposite side.
Further, the WPP 10 of the memory module 100 according to the first embodiment has a total of 18 WPPs 10 on one side of the module substrate 2 with two TSOPs 20 in between on both sides thereof (10 on one side with the TSOP 20 in between, Eight) are arranged on the opposite side.
One of the two TSOPs 20 (the TSOP 20 disposed on the upper side in FIG. 1) is a PLL (Phase-Locked Loop) 6 that is a frequency control means, and the other (the lower side in FIG. 1). The TSOP 20) arranged in the register 8 is a register 8 having a register function.
That is, in the memory module 100 of the first embodiment, the PLL 6 and the register 8 are also lead terminal semiconductor devices.
One capacitor 3 is arranged in the vicinity of each WPP 10 in the vicinity thereof.
Further, a total of 36 small imposition resistors 4 corresponding to each WPP 10 are arranged in a row. Since the small imposition resistor 4 is provided corresponding to the I / O of the memory module 100, the memory module 100 according to the first embodiment is provided with 36 I / Os on one side. Thirty-six attachment resistors 4 are also mounted. The 36 small imposition resistors 4 are arranged in a row in the vicinity of the connection terminal 2a, which is an external terminal of the module substrate 2, substantially along the connection terminal 2a.
As shown in FIG. 1A, the size of the module substrate 2 of the memory module 100 is, for example, L = 133.35 mm and M = 38.1 mm, and as shown in FIG. The mounting height (Max) is N = 4 mm.
In the memory module 100 of the first embodiment, the TSOP 20 and the WPP 10 are mounted by simultaneous reflow. As shown in FIG. 2, the WPP 10 is resin-sealed by underfill after reflow, Thereby, the sealing part 14 is formed.
That is, the periphery of the bump electrode 11 between the package main body 13 of the WPP 10 and the module substrate 2 is resin-sealed, and a sealing portion 14 is formed there.
The memory module 100 shown in FIG. 1 uses a WPP 10 as a DRAM and uses a module substrate 2 having a 72-bit width bus with error code collection.
Therefore, the memory module 100 is a module in which a total of 36 DRAMs (WPP10) are mounted on both the front and back surfaces of the module substrate 2. For example, if a 64 Mbit (16M × 4) DRAM is used, 16 words × 72 bits × 2 banks This is a DRAM module having a configuration.
Here, FIG. 3 is a block circuit diagram of the memory module 100 shown in FIG. 1, and is a block circuit diagram of a DRAM module having a 16-word × 72-bit × 2-bank configuration.
In FIG. 3, the first bank RS0 system and the RS2 system operate simultaneously, and the second bank RS1 system and the RS3 system operate simultaneously. When the second bank is bank-selected by the register 8 and the first bank is read, the second bank is not read. Similarly, when the second bank is read, the first bank is not read.
The A terminal [S0 to S3] of the register 8 is connected to the chip select (CS) terminal of either the first bank or the second bank DRAM (WPP10), and the register 8 selects the bank. , And input to the CS terminal of the selected semiconductor chip 1.
Further, D0 to D35 of each chip indicate 36 WPPs 10, and the [I (Input) / O (Output) 0 to I / O3] terminal in each chip is an independent terminal, and the connection terminal 2a of the module substrate 2 It is connected to the.
In addition, for all DRAMs, the I / O used as data is 64 bits from DQ0 to DQ63, and the I / O used as a check is 8 bits from CB0 to CB7. Bank configuration.
3 will be described. [A0 to A11] is an address input, [DQ0 to DQ63] is a data input / output, [CB0 to CB7] is a check bit (data input / output), [S0 to S3] is a chip select input, [RE] is a row enable (RAS) input, [CE] is a column enable (CAS) input, [W] is a write enable input, [DQMB0to DQMB7] is a byte data mask, [CK0 to CK3] is a clock input, [CKE0] is a clock enable input, [WP] is a write protect for Serial PD, [REGE] is a register enable, [SDA] is a data input / output for Serial PD, and [SCL] is a Serial PD. Clock input, [SA0 to SA2] is serial Address input, [Vcc] of the high potential power source, [Vss] denotes respectively ground, [NC] are non-connection.
Next, the detailed structure of the WPP 10 will be described. As shown in FIG. 4, a structure in which the bonding electrode 1a of the semiconductor chip 1 of the WPP 10 to the bump electrode 11 of the solder which is an external terminal is electrically connected by the rewiring 12. It has become.
That is, the pitch of the bump electrodes 11 electrically connected to the bonding electrodes 1a arranged at a narrow pitch is widened by the rewiring 12.
In this method, a functional part of an element is formed in a wafer unit, and then dicing is performed to separate each semiconductor chip 1 to obtain a chip size package.
Therefore, even when compared with a small package assembled by the same manufacturing method as the package of SMD (surface mount type) parts, it can be efficiently manufactured at a low cost.
FIG. 5 shows a TSOP 20 that is an example of an SMD component and a WPP 10 that is an example of a chip-sized protruding terminal semiconductor device, and shows the difference in size.
FIG. 5A is a plan view showing the TSOP 20 mounted on the memory module 100 shown in FIG. 1, and FIG. 5B is similarly mounted on the memory module 100 shown in FIG. It is the top view which showed WPP10.
As shown in FIG. 5, for example, the WPP 10 is smaller than the case where the DRAM is an SMD (surface mount type) type package such as TSOP 20, because the inner lead and the outer lead 21 are not provided. it can.
Therefore, by mounting the DRAM based on WPP 10 on the module substrate 2 as in the memory module 100 of the first embodiment, the mounting area can be significantly reduced as compared with the TSOP 20 formed by the piece processing.
That is, by mounting as the WPP 10, it is possible to mount in the smallest area as long as the semiconductor chip 1 is mounted, and as a result, the module capacity can be greatly increased.
In flip chip mounting, which is bare chip mounting, the same capacitance can be realized. However, since the rewiring 12 is not formed in flip chip mounting, the installation pitch of the external terminals is narrow, and at the same time with SMD type components. Reflow mounting is not possible. As a result, bare chip mounting components must be mounted one by one using flip chip bonders, and WPP 10 has higher mounting efficiency.
That is, the mounting of the WPP 10 does not require a special mounting apparatus such as the flip chip bonder, so that the number of mounting steps can be reduced.
In addition, since the WPP 10 can be mounted with a wider pitch of the bump electrodes 11 that are external terminals than the flip-chip mounting, the wiring rule on the module substrate 2 can be widened. Therefore, it is possible to realize the memory module 100 with high-density mounting at a reduced cost without incurring an increase in cost of the module substrate 2.
Further, in the WPP 10, the wiring distance from the bonding electrode 1a of the semiconductor chip 1 to the bump electrode 11 that is an external terminal is connected by a wiring shorter than the distance from the bonding electrode 1a to the outer lead 21 tip in the SMD component such as TSOP20. Therefore, high-speed signal transmission can be handled.
As a result, it is possible to cope with high speed in the memory module 100 and, as a result, it is possible to realize high-speed bus correspondence.
Here, in the memory module 100 of the first embodiment, the reason why all the semiconductor devices (packages) mounted on the memory module 100 are not WPP10, that is, WPP10 which is an example of a chip-sized protruding terminal semiconductor device, and SMD The reason why the components (TSOP 20 in the first embodiment) are mixedly mounted will be described.
The WPP 10 is formed by a pre-process wafer process. Therefore, all the processes for forming each device in the conventional post-process are processed in units of wafers.
In this case, if the number of non-defective products in one wafer is small, the defective product will be processed, resulting in high cost.
As a result, there is no cost merit in a product type in which the yield of semiconductor wafers is not sufficiently increased.
Further, since it is necessary to prepare an exposure reticle for each type, a semiconductor device (package) assembled to a lead frame can use a more versatile component material for products that are not mass-produced. As a result, products that are not mass-produced should not be made WPP10.
Furthermore, physical conditions are also important, and it is better not to use WPP 10 for logic with a small number of extraction terminals due to the relationship between the number of extraction terminals and the chip size. This is because the electrode pad (the diffusion preventing adhesive layer 7c shown in FIG. 7) and the bump electrode 11 after the rewiring 12 is formed from the bonding electrode 1a cannot be installed.
Therefore, a device that should be made WPP10 is a chip with a high yield and a large number of chip acquisitions per wafer, particularly a small memory device.
On the other hand, devices that are difficult to achieve with the WPP 10 include chips with a low yield and a small number of chips acquired per wafer, particularly large chips, advanced devices, or devices that only produce a small amount. In addition, in the case of ASIC (Application Specific Integrated Circuit) having a large number of external terminals with respect to the chip area, when the WPP 10 is used, the installation pitch of the bump electrodes 11 may not be sufficiently wide. It becomes easier to implement.
Next, a method for manufacturing WPP 10 will be described using a process flow of WPP 10 (see FIG. 1) shown in FIG. 6 and a wafer cross-sectional view corresponding to the main steps of the process flow shown in FIG.
First, wafer pre-process processing is performed by step S1 shown in FIG. Thus, the inorganic insulating protective film 7a is formed by exposing the bonding electrode 1a on the main surface of the silicon substrate 7 shown in FIG.
Subsequently, in step S2, WPP-first insulating layer formation is performed. That is, as shown in FIG. 7B, a first insulating layer 7b made of polyimide, fluororesin, or the like is formed on the inorganic insulating protective film 7a of the silicon substrate 7.
Then, WPP-rewiring layer formation is performed by step S3. That is, as shown in FIG. 7C, the rewiring 12 is formed on the first insulating layer 7b so as to be electrically connected to the bonding electrode 1a.
Further, in step S4, WPP-second insulating layer formation is performed. That is, as shown in FIG. 7D, a second insulating layer 7d made of polyimide, epoxy, or the like is formed on the rewiring 12.
Then, WPP-UBM (under bump metal) formation is performed by step S5. That is, as shown in FIG. 7E, the diffusion preventing adhesive layer 7c which is UBM is formed by being electrically connected to the rewiring 12.
Subsequently, in step S6, wafer inspection (W inspection) is performed. In this method, a probe needle is applied to an electrode pad formed in a scribe area of a semiconductor wafer (silicon substrate 7), and whether or not the wafer processing is performed as specified is inspected based on electrical characteristics.
Thereafter, in step S7, the probe inspection (P inspection 1) of the silicon substrate 7 is performed. In this method, a probe needle is applied to the bonding electrode 1a of the silicon substrate 7 to check whether each electrical operation of the semiconductor chip 1 is correct and detect a defective portion.
Further, in step S8, the defective portion is relieved, that is, laser relieved. In this method, a defective portion is relieved by cutting a fuse of a redundant circuit with a laser.
Thereafter, a probe test (P test 2) is performed in step S9. This is to confirm whether or not the defective portion remedied by the P test 1 has been corrected.
Subsequently, in step S10, wafer back surface marking is performed to attach a predetermined mark to the back surface of the silicon substrate 7.
Furthermore, bump formation is performed by step S11. That is, as shown in FIG. 7F, a bump electrode 11 (protrusion) that is an external terminal of the WPP 10 is formed on a diffusion prevention adhesive layer 7c that is a UBM provided at an end drawn from the bonding electrode 1a on the rewiring 12. Shaped terminal).
Here, the bump electrode 11 is formed by, for example, a printing method. Bump electrodes 11 on the wafer are formed at a time by placing a metal mask corresponding to the bump formation position on the wafer (silicon substrate 7), applying solder paste, removing the metal mask and reflowing all at once. Is done.
Thereafter, in step S12, dicing is performed to cut the semiconductor wafer, that is, the silicon substrate 7. As a result, the WPP 10 as shown in FIG. 4 is formed.
Thereafter, in step S13, aging of the WPP 10, that is, a burn-in (BI) test is performed.
Further, in step S14, single item sorting is performed to sort out non-defective WPPs 10.
Thereby, the assembly of the WPP 10 is completed.
In the manufacturing procedure shown in FIG. 6, after performing the probe inspection (P inspection 2) shown in step S9, the back grinding (hereinafter abbreviated as BG) step of polishing the back surface of the silicon substrate 7 is not performed. As described above, the BG process may be performed during the transition from the probe inspection (P inspection 2) process in step S9 to the wafer back surface marking process in step S10.
Here, in the BG process, the back surface of the silicon substrate 7 is polished to make the silicon substrate 7 thinner, thereby reducing the height of the WPP 10 formed thereby.
That is, the semiconductor chip 1 included in the WPP 10 is thinned for the purpose of thinning the WPP 10.
Therefore, by performing the BG process, it becomes possible to reduce the mounting height of the WPP 10 (for example, 1 mm or less).
Furthermore, since the thickness of the silicon substrate 7 can be reduced by performing the BG process, even when the scribe width at the time of dicing is narrowed to increase the number of chips in the silicon substrate 7, the cooling water is scribed into the scribe groove of the cooling water at the time of dicing. Dicing can be performed without hindering the intrusion.
Thereby, damage of the silicon substrate 7 at the time of dicing can be prevented, and the yield of the silicon substrate 7 can be improved. This is particularly effective when dicing the silicon substrate 7 having a diameter of 300 mm.
Further, the steps (wafer inspection (W inspection), probe inspection (P inspection 1), laser relief, probe inspection (P inspection 2)) shown in steps S6 to S9 of the manufacturing procedure shown in FIG. You may perform between a pre-process process and a WPP-first insulating layer formation process of step S2.
That is, the processes shown in steps S6 to S9 are performed after the wafer pre-process shown in step S1.
As a result, a series of probe inspections can be performed before the insulating film is formed on the silicon substrate 7, and the WPP 10 can be assembled without leaving any damage even when the bonding electrode 1a is damaged.
Next, a method for manufacturing the memory module 100 shown in FIG. 1 of the first embodiment will be described with reference to FIGS.
Note that the memory module 100 shown in FIG. 1 is obtained by mounting the WPP 10 on both the front and back surfaces of the module substrate 2 and mounting the TSOP 20 on one surface.
First, the WPP 10 is manufactured based on the process flow shown in FIG.
In other words, the bump electrode 11 (projection terminal) is provided as an external terminal, and the rewiring 12 (wiring portion) is provided in the area of the semiconductor chip 1 so that the installation pitch of the bump electrodes 11 is wider than the installation pitch of the bonding electrodes 1a. A WPP 10 (projection terminal semiconductor device) having a chip size shown in FIG. 4 is formed by wafer pre-process processing and prepared (here, 18 × 2 = 36 are prepared).
In the first embodiment, the semiconductor chip 1 included in the WPP 10 is a DRAM.
On the other hand, in addition to the WPP 10, a lead terminal semiconductor device which is an SMD component mounted on the module substrate 2 is assembled and prepared.
Here, there are two TSOPs 20 (one of which is a PLL 6 and the other is a register 8) which is a lead terminal semiconductor device including an outer lead 21 which is an external terminal electrically connected to the bonding electrode 1a of the semiconductor chip 1. ), EEPROM 5 (lead terminal semiconductor device), and 36 × 2 = 72 small imposition resistors 4.
A general mounting procedure will be described based on the basic flow of component mounting shown in FIG.
First, in step S15, solder printing is performed on the module substrate 2 to form terminals (land pads) for electrical connection with the tips of the outer leads 21 of the lead terminal semiconductor device, the bump electrodes 11 of the WPP 10, and the like.
Thereafter, SMD mounting is performed in step S16, and WPP 10 mounting is performed in step S17.
Subsequently, in step S18, batch reflow is performed, whereby the outer lead 21 of the lead terminal semiconductor device and the land pad are electrically connected, and the bump electrode 11 of the WPP 10 and the land pad are electrically connected.
Thereafter, cleaning is performed in step S19. However, it is not necessary to perform cleaning.
Furthermore, resin sealing by underfill is performed in step S20.
Next, the manufacturing method of the memory module 100 will be described in detail using the detailed mounting flow shown in FIG.
First, solder printing is performed on a predetermined portion of the module substrate 2 in step S21 shown in FIG.
Then, module surface mounting is performed by step S22. Here, a predetermined number of WPPs 10 (18 pieces), TSOP 20 (two pieces), small imposition resistors 4 (36 pieces) and EEPROM 5 (one piece) are arranged on the surface of the module substrate 2 by a mounting machine.
Thereafter, in step S23, all the components on the surface side of the module substrate 2 are mounted by batch (simultaneously) solder reflow.
Then, module backside mounting is performed by step S24. Here, each component is arranged on the back surface of the module substrate 2 by the same method as that on the front surface side using a mounting machine.
Subsequently, in step S25, all the components on the back side of the module substrate 2 are mounted together (simultaneously) by solder reflow.
As a result, it is possible to assemble a memory module 100 in which a predetermined number of WPPs 10 (18 × 2), TSOP20 (2), small imposition resistors 4 and EEPROM 5 are mounted (mixed) on both the front and back surfaces of the module substrate 2. .
Thereafter, cleaning is performed in step S26.
However, the cleaning may not be performed.
Thereafter, a module test is performed in step S27. That is, a predetermined inspection of the memory module 100 is performed to detect a defective chip.
Subsequently, defective chip repair is performed in step S28 to replace the defective chip. At that time, reheating is performed to melt the solder, and the defective chip (defective semiconductor device) is removed and replaced with a non-defective chip (defective semiconductor device).
Thereafter, in step S29, reflow is performed again to mount all components.
Subsequently, cleaning is performed in step S30.
Then, resin sealing by underfill shown in step S31 is performed on the WPP 10. The underfill has a relatively large chip size like a DRAM, and as a result, in the case of the WPP 10 having an insufficient stress buffering function to the bump electrode 11, the resin 9 is formed between the package body 13 of the WPP 10 and the module substrate 2. The stress applied to the bump electrode 11 is reduced.
In other words, the underfill is a resin seal between the package body 13 and the module substrate 2 in the WPP 10, and the periphery of the bump electrode 11 is solidified and protected by the resin 9.
When underfilling is performed, the liquid resin 9 is applied to each side of the module substrate 2 from the nozzle 60a of the dispenser 60 shown in FIG. That is, the resin 9 is applied to each side of the WPP 10 on the front and back surfaces of the module substrate 2.
When the application of both surfaces is completed, the front and back surfaces of the module substrate 2 are collectively heated to simultaneously cure the resin 9 on the front and back surfaces. That is, after the application of the resin 9 to both surfaces is completed, both surfaces are simultaneously cured and baked (cured) by atmospheric heating or the like.
Then, casing is performed by step S32 shown in FIG. 9, and a module final test is further performed by step S33.
Note that predetermined information is written into the EEPROM 5 by a dedicated writer.
Thereby, the assembly of the memory module 100 shown in FIG. 1 is completed.
Here, a description will be given for comparison between the two mountings of the bare chip mounting having the same mounting area as the mounting of the WPP 10.
First, in the bare chip mounting, the bonding electrodes 1a are mounted on the mounting board without being rearranged by the rewiring 12, so that the installation pitch of the external terminals is narrow, the wiring rules of the mounting board become strict, and the cost of the mounting board increases. . In addition, when the module is assembled, in addition to the solder reflow mounting process for mounting other SMD components, a mounting process using a flip chip bonder having a relatively low processing speed must be added.
Therefore, the WPP 10 in the memory module 100 according to the first embodiment can provide more effects than the bare chip mounting in the mounting (the mounting process can be reduced because a special mounting apparatus such as a flip chip bonder is not used). It is done.
Next, an underfill method in the method for manufacturing the memory module 100 of the first embodiment will be described.
FIG. 10 is a view showing a resin application method in the underfill of the WPP 10 mounted on the memory module 100 shown in FIG. 1, and FIG. 11 is a view showing the resin 9 when the resin 9 is applied by the application method shown in FIG. FIG.
In FIG. 10, each arrow represents the traveling direction of the nozzle 60a, and the dispenser 60 and the nozzle 60a move on the short side of the WPP 10 along this arrow.
In the resin coating method of the first embodiment, the dispenser 60 is intermittently and substantially linearly moved along the short side direction of the WPP 10 having a rectangular planar shape, and each WPP 10 is passed from above the WPP 10 via the nozzle 60a. The resin 9 is sequentially dropped on the short side. That is, when the application of one WPP 10 is completed, the nozzle 60a is moved to the front end on the short side of the next WPP 10, and the nozzle 60a is stopped once.
Thereafter, the resin 9 is dropped while moving the nozzle 60a from the front side end portion of the short side of the WPP 10 to the side end portion, and the movement of the one end nozzle 60a and the dripping of the resin 9 are stopped there.
Subsequently, in a state where the dripping of the resin 9 is stopped, the nozzle 60a is moved to the front side end portion of the short side of the WPP 10 arranged next to the resin 9, and the dripping of the resin 9 is similarly performed from there. Sequentially underfill each WPP 10.
FIG. 11 shows the state of wet spreading of the resin 9 when the resin 9 is applied to the WPP 10 of the DRAM with the bump electrodes 11 arranged in 15 rows × 4 columns by the coating method shown in FIG. 11 (a) and 11 (b) are just after short-side application, FIGS. 11 (c) and 11 (d) are after a predetermined time (low) after application, and FIGS. 11 (e) and 11 (f) are applied. 11 (g) and 11 (h) show a state in which the resin 9 is applied by making one turn of the nozzle 60a to form the fillet 9a in the periphery after the predetermined time (large) has elapsed after application. Is shown.
As shown in FIGS. 11 (e) and 11 (f), after the resin 9 wets and spreads between the WPP 10 and the module substrate 2, the dispenser 60 and the nozzle 60a are rotated around the package body 13 of the WPP 10 again. Thus, the fillet 9a shown in FIG. 11 (g) may be reliably formed, thereby further increasing the strength with which the WPP 10 is fixed to the module substrate 2.
Next, FIG. 12 shows the structure of a memory module 200 which is a modification of the memory module 100 according to the first embodiment of the present invention.
In the memory module 200, 18 WPPs 10 (protruding terminal semiconductor devices) are mounted in a line at equal pitch intervals on one side of the module substrate 2, and one TSOP 20 (lead terminal semiconductor device) is mounted in the vicinity of the WPP 10. In this case, TSOP 20 (lead terminal semiconductor device) is arranged near the center of WPP 10 arranged in a line.
That is, a plurality (10 and 8) of WPPs 10 are arranged in a line on both sides of one TSOP 20.
Further, nine SOP (Small Outline Package) 61 (registers 8) as lead terminal semiconductor devices are mounted side by side on the connection terminal 2a side, which is the external terminal, on the module substrate 2, and on the side opposite to the connection terminal 2a (connection Eighteen WPPs 10 are mounted on the side far from the terminal 2a, and each WPP 10 is underfilled.
In the memory module 200 having such a mounting configuration, when the resin 9 for underfill of the WPP 10 is applied, the resin 9 is applied almost linearly to the short sides of the 18 WPPs 10 arranged in a row. .
Thereby, the resin 9 can be efficiently applied.
FIG. 13 shows the structure of a memory module 300 which is a modification of the memory module 100 according to the first embodiment of the present invention.
In the memory module 300 shown in FIG. 13, 18 WPPs 10 are mounted on the module substrate 2 as two groups or four groups of 2 rows × 2 columns matrix arrangement as one group (lumb).
Further, each WPP 10 is mounted with its longitudinal direction parallel to the short side direction of the module substrate 2 of the memory module 300.
Here, a method of applying the resin 9 that is efficiently performed when underfilling the WPP 10 in such a mounted state of the WPP 10 will be described.
That is, when the application temperature of the resin 9 is relatively low, the distance by which the resin 9 penetrates between the package body 13 and the module substrate 2 is greater when the resin 9 is applied to the long side of the package body 13 of the WPP 10. short. As a result, the application time can be shortened.
Therefore, it is desirable to ensure a space for moving the nozzle 60a along at least one long side of each package body 13. From the viewpoint of high-density mounting, the long side on the side where the nozzle 60a is not used is the other side. It is desirable to place it as close as possible to the part.
By using this, when the semiconductor chip 1 has a multi-bit configuration and multiple DRAMs are connected to the same I / O of the memory module 300, 2 × 2 sets of DRAMs in the same plane are arranged as close as possible. The effect is great when the application method is used.
Therefore, in the mounted state of the WPP 10 as shown in FIG. 13, it is preferable to apply the resin 9 along the outer long side of each WPP 10 to the outer periphery of the outer long side. When the resin 9 is applied along the outer long side of the pair of DRAMs (WPP 10), the resin 9 flows into the package body 13 that is not the application target opposite to the package body 13 that is the application target, or the resin 9 is , Can prevent any leaks from spreading.
In the memory module 300, it is preferable to collect four I / Os having a (× 4) configuration to form a 16-bit configuration and mount them as a group. Therefore, in the WPP 10 mounting form shown in FIG. 13, it is preferable to apply the resin 9 along the application locus as indicated by the arrow.
Next, FIG. 14 is a figure which shows the penetration | invasion progress of the resin 9 at the time of performing resin application of another modification.
That is, in the mounting form of the WPP 10 of the memory module 400 as shown in FIG. 15, the underfill resin 9 is applied to the outer peripheral portions of the two opposite sides of the package body 13 as shown in FIG. Here, the resin 9 is applied from one end to the opposite end on both short sides of each WPP 10.
The arrows shown in FIGS. 14A and 14B indicate the movement trajectory of the dispenser 60, and FIGS. 14C and 14D show the state immediately after application of both short sides (two sides), FIG. FIGS. 14 (g) and 14 (h) show the permeation state of the resin 9 after the elapse of a predetermined time (middle) after application, respectively. is there.
In the first embodiment, even in the final stage of the penetration of the resin 9, the resins 9 that have penetrated from both short sides are in a state of being separated from each other, and there is a region where the resin 9 does not penetrate in the middle. The stress acting on the bump electrode 11 due to the difference in thermal expansion between the package body 13 and the module substrate 2 or the warp deformation of the module substrate 2 increases as the distance from the center of the package body 13 increases, and the bumps at the corners It becomes the maximum in the electrode 11. Therefore, if the resin 9 permeates in the vicinity of both short sides of the rectangular package body 13, even if there is a region that does not penetrate in the middle, a certain degree of stress reduction effect of the bump electrode 11 can be obtained.
As a result, an effect close to that applied to the entire surface of the package body 13 can be obtained with less resin 9 and less work time.
That is, it is possible to shorten the application time and reduce the application amount.
In addition, the resin 9 may be simply applied to the four corners of the package body 13. In this case, the stress to the bump electrode 11 disposed on the outermost periphery is reduced, and as a result, the connection life of the bump electrode 11 is extended. be able to.
Next, FIGS. 15A and 15B show the structure of a memory module 400 which is a modified example of the memory module 100, and 16 WPPs 10 are arranged in a line at equal pitch intervals on one side of the module substrate 2. In this memory module 400, the underfill resin 9 is linearly applied to the 16 WPPs 10 arranged in a line. The arrows shown in FIG. 15A indicate the movement trajectory of the dispenser 60 (see FIG. 10).
FIG. 16 shows a state where the memory module 400 shown in FIG. This is a state that may occur when the end of the module substrate 2 is pressed when the socket is inserted when the memory module 400 is inspected.
That is, as shown in FIG. 16, when the memory module 400 shown in FIG. 15 is bent in the longitudinal direction, the adjacent sealing portions 14 of the WPP 10 are not integrated without contacting each other. Since the memory module 400 bends throughout, the stress is distributed substantially uniformly throughout the memory module 400.
Thereby, it can be set as the structure which can also bear the load from the outside, As a result, the reliability of the memory module 400 can be improved.
Furthermore, the memory module 500 shown in FIG. 17 and FIG. 18 is mounted by dividing 16 WPPs 10 into 4 regions each in 4 regions along the arrangement direction of the plurality of connection terminals 2 a of the module substrate 2. The sealing portions 14 of the four WPPs 10 in one region are connected to each other.
That is, when the WPP 10 is mounted separately for each group (lumb) and they are connected to each other by the underfill sealing portion 14, the rigidity of the group (lumb) of the memory module 500 is apparently It becomes high including WPP10.
Thereby, the bending stress of the module substrate 2 is concentrated in the gap between the WPP groups.
In other words, the adjacent sealing portions 14 may be connected depending on factors affecting the application of the underfill resin 9 such as the interval between the WPPs 10. Even in this case, the memory module 500 shown in FIGS. In addition, by having the non-mounting portion 2b that is not partially connected, even when an external force is applied, the non-mounting portion 2b is bent and stress is applied to the connection portion of the bump electrode 11 of the WPP 10 and the semiconductor chip 1. Can be prevented.
As a result, since the stress can be dispersed, the connection reliability of the memory module 500 in the WPP 10 can be improved.
In the memory modules 100, 200, 300, 400, and 500 according to the first embodiment, since the WPP 10 is underfill sealed, the entire chip surface or the main part is more firmly fixed. As a result, the impact resistance is increased. As well as improving the moisture resistance, the moisture resistance can also be improved.
Here, in module products, another means for realizing high-density mounting includes TCP (Tape Carrier Package) stacked mounting. However, in this technique, chip cracks may occur due to chip thinning. On the other hand, in the memory modules 100, 200, 300, 400, and 500 according to the first embodiment, the impact resistance can be improved by fixing the chip by underfill, so that the occurrence of the chip crack is also prevented. Can do.
Further, the WPP 10 is mounted on the module substrate 2 with the underfill sealing and the surface (back surface) opposite to the main surface of the semiconductor chip 1 exposed, and the main chip of the semiconductor chip 1 is sealed by the underfill sealing. Since the whole surface or its main part is fixed to the module substrate 2, the thermal resistance can be lowered.
As a result, the heat dissipation of the memory modules 100, 200, 300, 400, 500 can be improved and the life can be extended.
FIG. 19 is a plan view showing an example of the structure of the memory module according to the second embodiment of the present invention.
In the memory module 600 of the second embodiment, 72 DRAMs WPP10 (protruding terminal semiconductor devices) are mounted in a matrix arrangement of matrices, and connection of input / output signals to each WPP10 is 2 For each row (in the memory module 600 of FIG. 19, the direction parallel to the short side of the module substrate 2 is the row, and the direction perpendicular thereto is the column, but the matrix relationship may be opposite). Nine memory selection means FET (Field Effect Transistor) -bus switch 15 (lead terminal semiconductor device) that switches eight groups and a total of nine WPP 10 groups (lumps) for ECC to one group. ) Are implemented corresponding to the WPP 10 of each group.
That is, in the memory module 600, connection of input / output signals to nine WPPs 10 for two rows is switched in one group (eight) by one FET-bus switch 15 corresponding thereto. Therefore, the number of WPPs 10 is increased without increasing the number of connection terminals 2a of the module substrate 2.
Therefore, in the memory module 600, four times as many WPPs 10 are mounted as compared with the memory module 100 of the first embodiment.
That is, the memory module 600 is configured such that a larger number of DRAMs can be mounted so that the I / O can be individually switched by the FET-bus switch 15.
The FET-bus switch 15 in the memory module 600 is of the SOP type, which is an example of a lead terminal semiconductor device, for example.
Since the other structure of the memory module 600 and the method for manufacturing the memory module 600 according to the second embodiment are the same as those of the memory module 100 according to the first embodiment, redundant description thereof is omitted.
20 is a diagram showing an example of the structure of the memory module according to Embodiment 3 of the present invention, where (a) is a plan view, (b) is a side view, and FIG. 21 is a block circuit diagram of the memory module shown in FIG. FIG. 22 is a bottom view showing an example of the structure of a wafer process package (protruding terminal semiconductor device) mounted on the memory module shown in FIG. 20, and FIG. 23 is a section C of the memory module shown in FIG. FIG. 24, FIG. 25 and FIG. 26 show a variation of the bump arrangement of the wafer process package in the memory module according to the third embodiment of the present invention and the corresponding substrate side wiring. FIG. 27 is a bump arrangement and wiring showing another modification of the bump arrangement of the wafer process package and the substrate side wiring shown in FIG. It is.
A memory module 700 according to the third embodiment shown in FIGS. 20A and 20B includes eight 8-byte 168-pin Unbuffered SDRAM (static DRAM) -DIMM (Dual In-line Memory Module). A WPP 10 (protruding terminal semiconductor device), a small imposition resistor 4, a capacitor 3, and an EEPROM 5 are mixedly mounted.
However, the memory module 700 does not include the register 8 mounted on the memory module 100 of FIG.
FIG. 21 shows an example of a block circuit diagram of the memory module 700 shown in FIG. 20, and shows a two-bank configuration.
Here, the explanation of the symbols shown in each terminal shown in FIG. 21 is the same as that explained in the block circuit diagram of the memory module 100 of the first embodiment, and therefore, the duplicate explanation is omitted.
In the memory module 700 shown in FIG. 21, which one of the S0 system in the first bank and the S1 system in the second bank is read is determined by a direct signal because the register 8 is not mounted. That is, since it is an unbuffered type, a signal directly enters any bank and the semiconductor chip 1 in any bank is selected.
D0 to D15 of each chip indicate 16 WPPs 10 on both sides, and the [I / O0 to I / O3] terminal in each chip is connected to the connection terminal 2a of the module substrate 2 as an independent terminal.
Further, the I / O used as data for all DRAMs is 64 bits from DQ0 to DQ63, and these have a 2-bank configuration.
A memory module 700 shown in FIG. 20 is a low-priced module compared to the memory module 100 shown in FIG.
Further, the size of the module substrate 2 of the memory module 700 is, for example, P = 133.35 mm and Q = 33.02 mm. As shown in FIG. 20B, the mounting height (Max) is R = 4 mm.
As shown in FIG. 20A, in the memory module 700, eight WPPs 10 (protruding terminal semiconductor devices), which are DRAMs, are arranged in a row on one side of the memory module 700. , A capacitor 3 (capacitor) is arranged at a location corresponding to the vicinity of the center in the longitudinal direction.
This is for minimizing the wiring length between the WPP 10 and the capacitor 3.
Here, the structure of the WPP 10 used in the memory module 700 is shown in FIG.
In the semiconductor chip 1 of the WPP 10 shown in FIG. 22, a vacant area 1b where the bump electrode 11 is not disposed is formed near the center in the longitudinal direction.
This is a partial change in the installation pitch of the bump electrodes 11 by the rewiring 12 so that the empty area 1b is formed, and an empty area 1b in which the bump electrode 11 is not provided is provided near the center in the longitudinal direction of the WPP 10. It is a thing.
FIG. 23 shows the board-side wiring of the module board 2 in the part C of FIG.
As shown in FIGS. 22 and 23, a capacitor 3 (lead terminal semiconductor device) is mounted adjacent to the vacant area 1b of the semiconductor chip 1, and the power supply wiring 2c of the capacitor 3 is vacant in the semiconductor chip 1 of the module substrate 2. It is formed as a surface layer wiring 2h on the surface layer facing the region 1b (however, it may be formed as an inner layer wiring 2g on the inner layer).
That is, as shown in FIG. 22, since the empty area 1 b where the bump electrode 11 is not installed is formed near the center in the longitudinal direction of the semiconductor chip 1, the signal line of the WPP 10 corresponds to the chip center of the module substrate 2. Connections can be made without going out to a location, and as a result, the capacitor 3 can be mounted closest to the WPP 10.
As a result, the wiring length between the WPP 10 and the capacitor 3 becomes the shortest, and the operating characteristics can be improved.
As shown in FIG. 23, the module substrate 2 is formed of a total of six metal layers of Vcc and Gnd layers of two core layers and signal lines of two layers on one side, and the bump electrode 11 of the WPP 10 is connected to the module substrate 2 The common wiring 2e for the address / function system is connected to the lower layer via the via hole 2f from the land 2d on the surface layer to be connected to the inner wiring 2g extending in the longitudinal direction of the module substrate 2. ing.
Further, the I / O wiring is connected to a connection terminal 2 a arranged nearby via a surface layer wiring 2 h of the module substrate 2. Therefore, an increase in inductance due to passing through the via hole 2f can be avoided.
In the wiring shown in FIG. 23, Vss (Gnd) and Vdd are formed extending from the capacitor 3 (capacitor) in the lateral direction, but may be immediately connected to the core layer via the via hole 2f.
Next, FIG. 24, FIG. 25, and FIG. 26 are wiring diagrams showing a variation of the bump arrangement of the WPP 10 and a corresponding variation of the substrate-side wiring in the memory module 700 of the third embodiment. FIG. 25 shows another modification of the bump arrangement and substrate side wiring modification of the wafer process package shown in FIG.
Note that the WPP 10 in FIGS. 24, 25, 26, and 27 is a common bump electrode group (a common electrode group such as an address, function, power supply, and Gnd that can be connected to the WPP 10 in common among a plurality of WPPs 10). A common bump terminal group 1c and an independent bump electrode group (independent protrusion terminal group) 1d which is an independent electrode group such as an I / O that is independently connected to each WPP 10 are divided on each WPP 10. This is the case.
Further, the independent bump electrode group 1d is arranged at one end of the short side of the package body 13 in the WPP 10, and eight WPPs 10 are connected to the individual bump electrode group 1d on one side of the memory module 700. It is mounted toward the connection terminal 2 a side of the substrate 2.
As a result, on the module substrate 2, the common wiring 2e, which is a wiring for connecting the eight common bump electrode groups 1c of the WPP 10, is formed by the surface layer wiring 2h.
Here, a wide installation pitch of the common bump electrode group 1c, that is, the address system and functional system bump electrodes 11, is provided, and in particular, a large number of wirings can be formed by passing between the bump electrodes in a direction perpendicular to the longitudinal direction of the package body 13. Thus, the installation pitch is formed large in the chip longitudinal direction.
Further, the installation pitch of the independent bump electrode group 1 d, that is, the I / O-based bump electrodes 11 is narrowed and arranged on one side outer periphery of the package body 13.
Thereby, since the common wiring 2e can be formed only by the surface layer wiring 2h, the number of wiring layers in the module substrate 2 can be reduced.
In the WPP 10 shown in FIG. 24, the common bump electrode group 1 c is provided with regularity by the rewiring 12 and is arranged obliquely with respect to the package body 13.
Accordingly, a plurality of common wirings 2e that connect common electrodes such as an address, a function, a power supply, and Gnd can be formed in parallel to the longitudinal direction of the package body 13.
As a result, the wiring density in the module substrate 2 can be maximized, and the distance of the common wiring 2e can be minimized.
Further, when the number of bump electrodes 11 of the WPP 10 is relatively small with respect to the chip size, or when the module substrate 2 is a substrate having a fine wiring rule such as an additive substrate, the surface layers and the inner layers of Gnd and Vcc By using a part of the layer as a signal layer, the four-layer module substrate 2 can be manufactured, and the memory module 700 can be assembled using this.
In this case, the I / O-based independent wiring 2i is connected from the bump electrode 11 provided on the connection terminal 2a side, and a plurality of common wirings 2e for connecting common electrodes such as address, function, power supply, and Gnd are connected between the chips. It can be formed to pass between.
In the WPP 10 shown in FIG. 25, the common bump electrode group 1c is arranged in a grid pattern by the rewiring 12 (see FIG. 22). At that time, as shown in FIG. 22, by using the rewiring 12 as a power supply / Gnd distribution inside the chip, and electrically connecting one bump electrode 11 and a plurality of bonding electrodes 1a by the rewiring 12, The number of bump electrodes 11 can be reduced (the number of external terminals can be reduced).
In the substrate side wiring shown in FIG. 25, the wiring is performed only by the surface layer of the module substrate 2, and the arrangement of the bump electrodes 11 is not inclined, and therefore wiring is performed using the bending or inclination of the substrate side wiring. .
Further, the WPP 10 shown in FIG. 26 is installed with the installation pitch of the bump electrodes 11 slightly wider than the bump arrangement of the WPP 10 shown in FIG. 25, and this is arranged on the module substrate 2 in the longitudinal direction or short direction thereof. They are arranged in a slanted direction.
As a result, the common wiring 2e on the module substrate 2 side can be inclined with respect to the longitudinal direction of the package body 13, and as a result, the common wiring 2e is linearly formed in the same manner as the common wiring 2e shown in FIG. Can be formed.
FIG. 27 shows another modification in which the installation pitch of the bump electrodes 11 is slightly wider than the bump arrangement of the WPP 10 shown in FIG. In this modification, independent pins other than the I / O system are also drawn from below. This is an example in which the number of pins is reduced by dedicating the bit configuration, thereby increasing the interval between the common wirings 2e, and narrowing the I / O pins and other independent pins (see FIG. 27). d1> d2).
As an effect of the modification shown in FIG. 27, since the interval between the common wires is widened, more wires can be routed between the pins. Therefore, the wiring on the module substrate 2 can be shared only by the surface layer wiring 2h, so that the inner layer wiring 2g (see FIG. 23) of the module substrate 2 is not required. Note that the I / O pins and the independent pins such as the power supply have a narrow pitch, but these do not route the wiring between the pins, and the wiring is taken out to the bottom, that is, the connection terminal 2a.
In FIG. 27, when the wiring layout is D, three surface layer wirings 2h pass between the pins, and when the wiring layout is E, four surface wirings 2h pass between the pins.
In FIG. 24, FIG. 25, FIG. 26, and FIG. 27, the mounting land of the module substrate 2 is not shown in order to increase the wiring density on the module substrate 2 to the limit, and slit-shaped resist openings perpendicular to the common wiring 2e are not shown. The part was a pseudo solder connection land.
The other structure of the memory module 700 according to the third embodiment and the method for manufacturing the memory module 700 are the same as those of the memory module 100 according to the first embodiment, and a duplicate description thereof will be omitted.
For example, in the memory modules 100 to 700 of the first, second, and third embodiments, the case where the EEPROM 5 is used as a lead terminal semiconductor device having the outer lead 21 has been described. However, the EEPROM 5 that is a nonvolatile read-only memory has a protruding shape. A structure similar to that of the terminal semiconductor device, that is, the WPP 10 may be formed and mounted.
However, at that time, the WPP-structure EEPROM 5 does not perform sealing by underfill, but performs only underfill only to the WPP 10 of the DRAM.
That is, the EEPROM 5 having the WPP structure is detachably mounted from the module substrate 2.
This is because the product yield of the EEPROM 5 is low, and when a defect is found at the time of electrical writing, only the EEPROM 5 can be replaced with a non-defective product. In the case of the EEPROM 5, since the chip size is smaller than that of the DRAM, the stress applied to the bump electrode 11 is small, and sufficient reliability can be obtained even without underfill. By mounting the EEPROM 5 having the WPP structure, the mounting area can be reduced as compared with the SOP type, and the cost can be reduced as compared with the SOP type.
In the first, second, and third embodiments, the double-sided mounting type memory module in which the WPP 10 is mounted on both the front and back sides of the module substrate 2 has been described. However, the memory module is a single-sided mounting type. Also good.
Further, the lead terminal semiconductor device mixed with the WPP 10 (protruding terminal semiconductor device) is not limited to the TSOP 20, and other semiconductor devices such as QFP (Quad Flat Package) and TCP (Tape Carrier Package) than the TSOP 20 are used. There may be.
In the first, second, and third embodiments, the case where the protruding terminal semiconductor device is the WPP 10 has been described. However, the protruding terminal semiconductor device has a bump electrode 11 as an external terminal and bonding of the semiconductor chip 1. Other semiconductor devices may be used as long as the semiconductor device includes a wiring portion that expands the installation pitch of the bump electrodes 11 more than the installation pitch of the electrodes 1a.
FIG. 28, FIG. 29, and FIG. 30 show modifications other than the WPP 10 of the protruding terminal semiconductor device.
28A, 28B, and 28C show a CSP (Chip Scale Package) 30 as a modification of the protruding terminal semiconductor device.
The CSP 30 has a chip size that is substantially the same as or slightly larger than the semiconductor chip 1 and has a fan-in structure in which the semiconductor chip 1 is supported by the tape substrate 32 with an elastomer 31 interposed therebetween. .
Further, a plurality of bump electrodes 34 (protruding terminals) made of solder or the like as external terminals are provided in the area in the area of the semiconductor chip 1, and the connection leads 32 a provided on the tape substrate 32 and the bonding electrodes 1 a of the semiconductor chip 1. Are connected to each other, and a terminal pitch expansion wiring 32 b is formed on the tape substrate 32, which is a wiring portion that widens the installation pitch of the bump electrodes 34 than the installation pitch of the bonding electrodes 1 a of the semiconductor chip 1.
Note that a sealing portion 33 is formed on the bonding electrode 1 a of the semiconductor chip 1.
FIGS. 29A and 29B show a chip face-up mounting type BGA (Ball Grid Array) 40 as a modification of the protruding terminal semiconductor device.
The BGA 40 is obtained by fixing the semiconductor chip 1 to the BGA substrate 42 through a die bonding material 45 by a face-up method, and the bonding electrode 1a of the semiconductor chip 1 and the substrate electrode 42f of the BGA substrate 42 are made of gold or the like. Are electrically connected by bonding wires 41.
Further, a plurality of bump electrodes 44 (protruding terminals) made of solder or the like as external terminals are provided on the back side of the BGA substrate 42 in a grid pattern, and the bump electrodes 44 are larger than the installation pitch of the bonding electrodes 1 a of the semiconductor chip 1. A terminal pitch expansion wiring 42a, which is a wiring portion that widens the installation pitch of the BGA substrate 42, is formed on the BGA substrate 42.
The terminal pitch extension wiring 42a includes a signal wiring 42b, a GND plane 42c, a Vdd plane 42d, a through hole 42e, and the like.
Further, a mold part 43 for sealing the semiconductor chip 1 and the bonding wires 41 with a resin is formed.
30A, 30B, and 30C show a chip face-down mounting type BGA (Ball Grid Array) 50 as a modified example of the protruding terminal semiconductor device.
The BGA 50 has a flip chip structure in which the semiconductor chip 1 is mounted on the BGA substrate 52 via the small bumps 51 in a face-down manner. The bonding electrode 1a of the semiconductor chip 1 and the electrode of the BGA substrate 52 are small. The bumps 51 are electrically connected.
Further, bump electrodes 54 (protruding terminals) made of solder or the like are provided as external terminals in a grid-like arrangement on the back side of the BGA substrate 52, and more than the installation pitch of the bonding electrodes 1a (see FIG. 29) of the semiconductor chip 1. A terminal pitch expansion wiring 52a (see FIG. 30C), which is a wiring portion that widens the installation pitch of the bump electrodes 54, is formed on the BGA substrate 52.
Note that a sealing portion 53 is formed between the semiconductor chip 1 and the BGA substrate 52, that is, around the small bump 51 by resin sealing with an underfill.
In the CSP 30 shown in FIG. 28, the BGA 40 shown in FIG. 29, and the BGA 50 shown in FIG. 30 as well, the terminal pitch that is a wiring portion that widens the installation pitch of the bump electrodes 34, 44, and 54 than the installation pitch of the bonding electrodes 1a of the semiconductor chip 1 Since the extended wirings 32b, 42a, and 52a are respectively provided, reflow mounting can be performed when these are mounted on the module substrate 2 or the like.
(1). By mounting the protruding terminal semiconductor device on the module substrate in the memory module, the mounting area can be greatly reduced as compared with the lead terminal semiconductor device having a semiconductor chip formed by individual processing. As a result, the semiconductor chip can be mounted in the smallest area as long as it is mounted, and as a result, the module capacity can be greatly increased.
(2). By mounting WPP as the protruding terminal semiconductor device, the installation pitch of the bump electrodes as external terminals can be mounted with a wider pitch than the flip-chip mounting, so that the wiring rule on the module substrate can be widened. Thereby, it is possible to realize a memory module with high-density mounting at a reduced cost.
(3). It is possible to connect the bonding electrode of the semiconductor chip to the bump electrode of the WPP which is an external terminal with a wiring having a shorter distance than the SMD component such as TSOP. As a result, it is possible to cope with high speed in the memory module, and as a result, it is possible to realize high speed bus correspondence.
(4). Since the WPP is underfill sealed in the memory module, the entire chip surface is more firmly fixed, so that the impact resistance can be improved. Thereby, generation | occurrence | production of a chip crack can also be prevented.
(5). Since the WPP is underfill sealed and mounted on the module substrate with the back surface of the semiconductor chip exposed, the entire main surface of the semiconductor chip is fixed to the module substrate by the underfill sealing. Thermal resistance can be lowered. As a result, the heat dissipation of the memory module can be improved and the life of the memory module can be extended.
FIGS. 1A, 1B, and 1C are views showing an example of the structure of a memory module according to Embodiment 1 of the present invention, FIG. 1A being a plan view, and FIG. 1B being a side view; (C) is sectional drawing which shows the AA cross section of (a).
FIG. 2 is an enlarged partial cross-sectional view showing an enlarged B portion in the cross-sectional view of FIG.
FIG. 3 is an example of a block circuit diagram of the memory module shown in FIG. 1;
4 is an external perspective view showing an example of the structure of a wafer process package (projecting terminal semiconductor device) mounted on the memory module shown in FIG. 1; FIG.
5A and 5B are views showing an example of the structure of an SMD (lead terminal semiconductor device) and a wafer process package mounted on the memory module shown in FIG. 1, and FIG. 5A is a plan view of the SMD. FIG. 4B is a plan view of the wafer process package.
6 is a process flow showing an example of a manufacturing process of a wafer process package mounted on the memory module shown in FIG. 1;
7 (a), (b), (c), (d), (e), and (f) are enlarged portions showing an example of the structure of a semiconductor wafer corresponding to the main steps of the process flow shown in FIG. It is sectional drawing.
8 is a basic mounting flow showing an example of a procedure for mounting a wafer process package and SMD mounted on the memory module shown in FIG. 1 on a module substrate.
9 is a mounting flow showing an example of a mounting procedure of a wafer process package mounted on the memory module shown in FIG. 1 on a module substrate.
10 is an enlarged partial perspective view showing an example of a resin coating method in underfill of a wafer process package mounted on the memory module shown in FIG. 1. FIG.
11 (a), (b), (c), (d), (e), (f), (g), and (h) are obtained when the underfill resin shown in FIG. 10 is applied. It is a figure which shows an example of the penetration | invasion process of resin, (a), (c), (e), (g) is a perspective view, (b), (d), (f), (h) is a semiconductor chip. FIG.
FIG. 12 is a plan view showing the structure of a modification of the memory module according to the first embodiment of the present invention;
FIG. 13 is a plan view showing a structure of a modification of the memory module according to the first embodiment of the present invention;
14 (a), (b), (c), (d), (e), (f), (g), and (h) are variations of the underfill according to the first embodiment of the present invention. It is a figure which shows the penetration | invasion progress of resin at the time of resin application | coating, (a), (c), (e), (g) is a perspective view, (b), (d), (f), (h ) Is a plan view seen through the semiconductor chip.
FIGS. 15A and 15B are diagrams showing the structure of a modification of the memory module according to the first embodiment of the present invention, where FIG. 15A is a plan view and FIG. 15B is a side view;
16 is a side view showing an example of a warped state of the memory module shown in FIG. 15;
FIG. 17 is a plan view showing a structure of a modification of the memory module according to the first embodiment of the present invention;
18 is a side view showing an example of a warped state of the memory module shown in FIG. 17;
FIG. 19 is a plan view showing an example of a structure of a memory module according to the second embodiment of the present invention.
20A and 20B are diagrams showing an example of the structure of a memory module according to Embodiment 3 of the present invention, where FIG. 20A is a plan view and FIG. 20B is a side view.
FIG. 21 is an example of a block circuit diagram of the memory module shown in FIG. 20;
22 is a bottom view showing an example of the structure of a wafer process package (projecting terminal semiconductor device) mounted on the memory module shown in FIG. 20;
23 is a board-side wiring diagram illustrating an example of module board wiring in part C of the memory module shown in FIG. 20;
FIG. 24 is a wiring diagram of a modified example of the bump arrangement of the wafer process package and a corresponding modified example of the substrate side wiring in the memory module according to the third embodiment of the present invention;
FIG. 25 is a wiring diagram of a modified example of the bump arrangement of the wafer process package and a corresponding modified example of the substrate side wiring in the memory module according to the third embodiment of the present invention;
FIG. 26 is a wiring diagram of a modified example of the bump arrangement of the wafer process package and a corresponding modified example of the substrate side wiring in the memory module according to the third embodiment of the present invention;
27 is a bump arrangement and wiring diagram showing another modification of the bump arrangement and substrate side wiring of the wafer process package shown in FIG. 25. FIG.
FIGS. 28A, 28B and 28C are views showing the structure of a CSP which is a modification of the protruding terminal semiconductor device mounted on the memory module of the present invention, and FIG. (B) is sectional drawing, (c) is a bottom view.
FIGS. 29A and 29B are diagrams showing the structure of a chip-face-up mounting type BGA, which is a modification of the protruding terminal semiconductor device mounted on the memory module of the present invention, and FIGS. External perspective view, (b) is a cross-sectional view.
30 (a), (b), and (c) are diagrams showing the structure of a chip face-down mounting type BGA that is a modification of the protruding terminal semiconductor device mounted on the memory module of the present invention; (A) is a plan view, (b) is a cross-sectional view, and (c) is a bottom view.
1a Bonding electrode
1b Free space
1c Common bump electrode group (common protruding terminal group)
1d Independent bump electrode group (independent protruding terminal group)
2 Module board
2a Connection terminal (external terminal)
2b Non-mounting part
2c Power supply wiring
2e Common wiring
2f Beer hole
2g inner layer wiring
2h surface wiring
2i Independent wiring
4 Imposition resistance
5 EEPROM (nonvolatile read-only memory)
6 PLL (frequency control means)
7 Silicon substrate
7a Inorganic insulating protective film
7b First insulating layer
7c Anti-diffusion adhesive layer
7d Second insulating layer
9a fillet
10 WPP (protruding terminal semiconductor device)
11 Bump electrode (protruding terminal)
12 Rewiring (wiring section)
13 Package body (Semiconductor device body)
14 Sealing part
15 FET-bus switch (memory selection means)
20 TSOP (Lead Terminal Semiconductor Device)
21 Outer lead (external terminal)
22 Package body (semiconductor device body)
30 CSP (protruding terminal semiconductor device)
32 Tape substrate
32a Connection lead
32b Terminal pitch expansion wiring (wiring section)
33 Sealing part
34 Bump electrode (protruding terminal)
40 BGA (protruding terminal semiconductor device)
41 Bonding wire
42 BGA substrate
42a Terminal pitch expansion wiring (wiring section)
42b Signal wiring
42c GND plane
42d Vdd plane
42e Through hole
42f Substrate electrode
43 Mold part
44 Bump electrode (protruding terminal)
45 Die bond materials
50 BGA (protruding terminal semiconductor device)
51 Small bump
52 BGA board
52a Terminal pitch expansion wiring (wiring section)
53 Sealing part
54 Bump electrode (protruding terminal)
60 dispensers
61 SOP (Lead Terminal Semiconductor Device)
100, 200, 300, 400, 500, 600, 700 Memory module
Provided with a protruding terminal as an external terminal, mounted via the protruding terminal, and provided with a rewiring that is a wiring portion that extends the installation pitch of the protruding terminal more than the installation pitch of the bonding electrode in the area of the semiconductor chip A chip-sized protruding terminal semiconductor device;
An outer lead as an external terminal, and a lead terminal semiconductor device mounted via the outer lead electrically connected to the bonding electrode of the semiconductor chip;
A module substrate for supporting the protruding terminal semiconductor device and the lead terminal semiconductor device;
The protruding terminal semiconductor device and the lead terminal semiconductor device are mounted together, and both are mounted together on the module substrate,
The semiconductor chip incorporated in the protruding terminal semiconductor device is a DRAM having a rectangular planar shape, and an empty area in which the protruding terminal is not provided is provided near the center in the longitudinal direction of the DRAM. A memory module, wherein a capacitor is mounted adjacent to the empty area, and a power supply wiring of the capacitor is formed on a surface layer or an inner layer of the module substrate facing the empty area of the semiconductor chip.
A module substrate supporting the protruding terminal semiconductor device and the lead terminal semiconductor device, wherein the protruding terminal semiconductor device and the lead terminal semiconductor device are mounted together, and both are mixedly mounted on the module substrate; And
A common protruding terminal group that can be connected to each other in common by the protruding terminal semiconductor devices, and an independent protruding terminal group that is connected and wired independently for each protruding terminal semiconductor device. A plurality of the protruding terminal semiconductor devices, wherein the plurality of protruding terminal semiconductor devices are arranged at one end of the semiconductor device body, and the independent protruding terminal groups are assigned to the independent protruding terminal groups. A wiring that is mounted on the module substrate toward a connection terminal side that is an external terminal of the module substrate and that connects the common protruding terminal group of the plurality of protruding terminal semiconductor devices is formed on the module substrate. Features memory module.
A plurality of protruding terminal semiconductor devices are divided and mounted in a plurality of regions along the arrangement direction of connection terminals which are a plurality of external terminals of the module substrate, and the plurality of protruding terminals in one region are mounted. In a semiconductor device, a memory portion is formed by connecting sealing portions by underfill which is resin sealing between each semiconductor device main body and the module substrate, and non-mounting portions are formed on both sides thereof. module.
A chip-sized projecting terminal semiconductor device having a projecting terminal as an external terminal and provided with a rewiring that is a wiring section that widens the installation pitch of the projecting terminals in the area of the semiconductor chip than the installation pitch of the bonding electrodes. A preparation process;
Preparing a lead terminal semiconductor device having the bonding electrode and the outer lead is electrically connected to the external terminals of the semiconductor chip,
Arranging the protruding terminal semiconductor device and the lead terminal semiconductor device on a module substrate;
Reflowing the protruding terminal semiconductor device and the lead terminal semiconductor device at the same time and mounting them on the module substrate,
The projecting terminal semiconductor device and the lead terminal semiconductor device are mixedly mounted on the module substrate,
A plurality of the protruding terminal semiconductor devices are mounted on the module substrate in groups of two or two in a 2 × 2 matrix arrangement, and the semiconductor device body of the protruding terminal semiconductor device and the module substrate A method for manufacturing a memory module, comprising: applying resin for underfill that is resin-sealing between and to the outer periphery of the plurality of protruding terminal semiconductor devices along the long sides.
Preparing a lead terminal semiconductor device including an outer lead that is an external terminal electrically connected to the bonding electrode of the semiconductor chip;
A plurality of the protruding terminal semiconductor devices are mounted on the module substrate in groups of two or two in a 2 × 2 matrix arrangement, and the semiconductor device body of the protruding terminal semiconductor device and the module substrate A resin for underfilling, which is a resin seal between each of the plurality of protruding terminal semiconductor devices of the group, is applied to the outer peripheral sides of the opposing two sides of the semiconductor device main body. Module manufacturing method.
After the projecting terminal semiconductor device and the lead terminal semiconductor device are arranged on the module substrate, the projecting terminal semiconductor device and the lead terminal semiconductor device are reflowed together, and both are mounted on the front and back surfaces of the module substrate. And a process of
After applying an underfill resin, which is a resin seal between the semiconductor device main body of the protruding terminal semiconductor device and the module substrate, to the protruding terminal semiconductor devices on both sides of the module substrate one by one And simultaneously heating both the front and back surfaces of the module substrate to simultaneously cure the resin on both the front and back surfaces,
A method of manufacturing a memory module, wherein the protruding terminal semiconductor device and the lead terminal semiconductor device are mixedly mounted on the module substrate.
A common protruding terminal group that can be connected to each other in common by the protruding terminal semiconductor devices, and an independent protruding terminal group that is connected and wired independently for each protruding terminal semiconductor device. A plurality of the protruding terminal semiconductor devices, wherein the plurality of protruding terminal semiconductor devices are arranged at one end of the semiconductor device body, and the independent protruding terminal groups are assigned to the independent protruding terminal groups. A wiring that is mounted on the module substrate toward the connection terminal side that is an external terminal of the module substrate and connects the common protruding terminal group of the plurality of protruding terminal semiconductor devices is formed on the module substrate.
The memory module according to claim 1, wherein an interval between the common protruding terminals is larger than an interval between the independent protruding terminals.
JP05029299A 1999-02-26 1999-02-26 Memory module and manufacturing method thereof Expired - Fee Related JP3914651B2 (en)
JP05029299A JP3914651B2 (en) 1999-02-26 1999-02-26 Memory module and manufacturing method thereof
TW089102969A TW498505B (en) 1999-02-26 2000-02-21 A memory-module and a method of manufacturing the same
KR1020000009005A KR100616055B1 (en) 1999-02-26 2000-02-24 A memory-module and a method of manufacturing the same
CNB00102664XA CN1222037C (en) 1999-02-26 2000-02-25 Memory assembly and its making method
US10/029,979 US20030116835A1 (en) 1999-02-26 2001-12-31 Memory-module and a method of manufacturing the same
US10/326,149 US7102221B2 (en) 1999-02-26 2002-12-23 Memory-Module with an increased density for mounting semiconductor chips
JP2000252418A JP2000252418A (en) 2000-09-14
JP3914651B2 true JP3914651B2 (en) 2007-05-16
ID=12854846
JP05029299A Expired - Fee Related JP3914651B2 (en) 1999-02-26 1999-02-26 Memory module and manufacturing method thereof
US (2) US20030116835A1 (en)
JP (1) JP3914651B2 (en)
KR (1) KR100616055B1 (en)
CN (1) CN1222037C (en)
TW (1) TW498505B (en)
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1999-02-26 JP JP05029299A patent/JP3914651B2/en not_active Expired - Fee Related
2000-02-21 TW TW089102969A patent/TW498505B/en not_active IP Right Cessation
2000-02-24 KR KR1020000009005A patent/KR100616055B1/en not_active IP Right Cessation
2000-02-25 CN CNB00102664XA patent/CN1222037C/en not_active IP Right Cessation
2001-12-31 US US10/029,979 patent/US20030116835A1/en not_active Abandoned
2002-12-23 US US10/326,149 patent/US7102221B2/en not_active Expired - Fee Related
US20030089978A1 (en) 2003-05-15
CN1264924A (en) 2000-08-30
US7102221B2 (en) 2006-09-05
JP2000252418A (en) 2000-09-14
KR20000058173A (en) 2000-09-25
KR100616055B1 (en) 2006-08-28
CN1222037C (en) 2005-10-05
US20030116835A1 (en) 2003-06-26
TW498505B (en) 2002-08-11
US8766425B2 (en) 2014-07-01 Semiconductor device
US7982314B2 (en) 2011-07-19 Semiconductor integrated circuit device
2007-01-25 A01 Written decision to grant a patent or to grant a registration (utility model)
2016-02-09 LAPS Cancellation because of no payment of annual fees