Source: http://www.google.com/patents/US20100058094?ie=ISO-8859-1
Timestamp: 2014-12-28 17:51:32
Document Index: 107409974

Matched Legal Cases: ['art. 2', 'Application No. 2008', 'art 3', 'art 6', 'art 3', 'art 6', 'art 6', 'art 6', 'art 16', 'art 16', 'art. 16', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 16', 'art 6', 'art 16', 'art 16', 'art 16']

Patent US20100058094 - Data processing apparatus - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA data processing apparatus includes a CPU including a register, a cache memory, a main memory configured to exchange data with the cache memory, a control part configured to control the exchanging of data between the main memory and the cache memory, and a power supply part configured to supply power...http://www.google.com/patents/US20100058094?utm_source=gb-gplus-sharePatent US20100058094 - Data processing apparatusAdvanced Patent SearchPublication numberUS20100058094 A1Publication typeApplicationApplication numberUS 12/495,991Publication dateMar 4, 2010Filing dateJul 1, 2009Priority dateAug 29, 2008Also published asCN101661435A, US8135971Publication number12495991, 495991, US 2010/0058094 A1, US 2010/058094 A1, US 20100058094 A1, US 20100058094A1, US 2010058094 A1, US 2010058094A1, US-A1-20100058094, US-A1-2010058094, US2010/0058094A1, US2010/058094A1, US20100058094 A1, US20100058094A1, US2010058094 A1, US2010058094A1InventorsSadao Miyazaki, Osamu Ishibashi, Rikizo Nakano, Yoshinori MesakiOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManReferenced by (2), Classifications (5), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetData processing apparatusUS 20100058094 A1Abstract A data processing apparatus includes a CPU including a register, a cache memory, a main memory configured to exchange data with the cache memory, a control part configured to control the exchanging of data between the main memory and the cache memory, and a power supply part configured to supply power to the register, the cache memory, and the main memory. The register, the cache memory, and the main memory are each configured to store data and maintain the stored data therein without being supplied with the power from the power supply part. The control part is configured to stop the CPU from accessing the register, the cache memory, and the main memory where an abnormality occurs in the power supply part.
a CPU including a register; a cache memory; a main memory configured to exchange data with the cache memory; a control part configured to control the exchanging of data between the main memory and the cache memory; and a power supply part configured to supply power to the register, the cache memory, and the main memory; wherein the register, the cache memory, and the main memory are each configured to store data and maintain the stored data therein without being supplied with the power from the power supply part; wherein the control part is configured to stop the CPU from accessing the register, the cache memory, and the main memory where an abnormality occurs in the power supply part. 2. The data processing apparatus as claimed in claim 1, wherein the control part causes the CPU to resume processing of the stored data maintained by the register, the cache memory, and the main memory when the power supply part recovers after the occurrence of the abnormality.
a backup power supply; wherein the register, the cache memory, the main memory are each a volatile memory to which power is supplied from the backup power supply when the abnormality occurs. Description
CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2008-222243 filed on Aug. 29, 2009, the entire contents of which are incorporated herein by reference.
FIELD The embodiments discussed herein are related to a data processing apparatus that does not require saving of data even where abnormality of the power source occurs.
BACKGROUND FIG. 1 is a schematic diagram illustrating a configuration of a data processing apparatus 100 according to a related art example. The data processing apparatus 100 of the related art example includes a CPU (Central Processing Unit) 1, a cache memory 2, a control part 3, a main memory 4, a HDD (hard disk drive) 5, and a power source part 6. The cache memory 2, the control part 3, the main memory 4, and the HDD 5 are connected by a bus.
In a case where the CPU 1 determines that there is a decrease in the value of the voltage supplied from the power supply part 6, the CPU 1 sets a power supply abnormality flag to �1� (Step S2).
After the repairing or replacing of the power supply part 6 is completed, the data processing apparatus 100 is restarted. When the data processing apparatus 100 is restarted, the CPU 1 determines whether the power supply abnormality flag is �1� (Step S7). Step S7 is for determining whether a decrease of the value of the voltage of the power supply part 6 has occurred previous to the restarting of the data processing apparatus 100.
SUMMARY According to an aspect of the invention, there is provided a data processing apparatus including a CPU including a register, a cache memory, a main memory configured to exchange data with the cache memory, a control part configured to control the exchanging of data between the main memory and the cache memory, and a power supply part configured to supply power to the register, the cache memory, and the main memory, wherein the register, the cache memory, and the main memory are each configured to store data and maintain the stored data therein without being supplied with the power from the power supply part, wherein the control part is configured to stop the CPU from accessing the register, the cache memory, and the main memory where an abnormality occurs in the power supply part.
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic diagram illustrating a configuration of a data processing apparatus according to a related art example;
DESCRIPTION OF EMBODIMENTS First Embodiment FIG. 4 lock diagram illustrating a configuration of a data processing apparatus 400 according to a first embodiment of the present invention. In FIG. 4, like components are denoted by like reference numerals as of the above-described data processing apparatuses 100, 300 and are not further described.
In a case where the CPU 10 determines that there is a decrease in the value of the voltage supplied from the power supply part 16, the CPU 10 sets a power supply abnormality flag to �1� (Step S12).
After the recovery (e.g., replacing or repairing) of the power supply part 16 is completed, the data processing apparatus 400 is restarted. When the data processing apparatus 400 is restarted, the CPU 1 determines whether the power supply abnormality flag is �1� (Step S17). Step S17 is for determining whether a decrease of the value of the voltage of the power supply part. 16 has occurred, previous to the restarting of the data processing apparatus 400.
[Operation of Data Processing Apparatus 100, 300 According to Related Art Example] At the time �t=0� of FIG. 6B, the power supply abnormality flag is �0�, the program is in an active (ON) state, the data saving process is not being performed (OFF), and the maintaining of power with the condenser of the power supply part 6 is not being performed (NO).
In a case where an abnormality occurs in the power supply part 6 at the time �t=t1� of FIG. 6A, the power supply abnormality flag is set to �1� at the time �t=t2�. Accordingly, the data saving process is being performed (ON), and the maintaining of power with the condenser of the power supply part 6 is being performed (YES) as illustrated in FIG. 6B.
At the time �t=t3�, the data saving process is completed (OFF) as illustrated in FIG. 6B. At the time �t=t4�, the power maintaining process (backup process) using the condenser of the power supply part 6 is completed (NO) as illustrated in FIG. 6B.
At the time �t=t5�, the voltage value of the power supply part 6 becomes lower than the voltage for operating the CPU 1, the register 1A, the cache memory 2, and the main memory 4 as illustrated in FIG. 6A. At the time �t=t6�, the voltage value of the power supply part 6 becomes approximately zero.
Then, after the power supply part 6 is replaced or repaired, the voltage value of the power supply part 6 gradually increases from the time �t=t7�.
When the CPU 1 is restarted at time �t=t8�, the CPU 1 sets the power supply abnormality flag to �0� and executes the process of deploying the saved data (deploying process �ON�) as illustrated in FIG. 6B.
After the deploying process is completed (deploying process �OFF�) at time �t=t9�, the CPU 1 continues the program by using the deployed data at time �t=t10�.
[Operation of Data Processing Apparatus 400 According to First Embodiment] At the time �t=0� of FIG. 6C, the power supply abnormality flag is �0�, the program is in an active (ON) state, and the power maintained in the power supply part 16 is not being used (NO).
In a case where abnormality occurs in the power supply part 6 at the time �t=t1� of FIG. 6A, the power supply abnormality flag is set to �1� at the time �t=t2�. Accordingly, a program is stopped (OFF). It is to be noted that all processes of the data processing apparatus 400 are stopped together with the stopping of the program.
During a period of approximately several milliseconds after the time �t=t2�, the power remaining in the power supply part 16 is used for stopping the program and all of the processes of the data processing apparatus 400.
Then, after the power supply part 16 is replaced or repaired and the data processing apparatus 400 is restarted at the time �t=t8�, the CPU 10 resumes the program from the step in which the abnormality of the power supply part 16 has occurred.
Second Embodiment FIG. 7 is a block diagram illustrating a configuration of a data processing apparatus 700 according to a second embodiment of the present invention. The data processing apparatus 700 of the second embodiment is different from the data processing apparatus 400 of the first embodiment in that the main memory 24 is a volatile memory which is connected to a backup power supply (e.g., backup battery). Other than such difference, the configuration of the data processing apparatus 700 is substantially the same as that of the data processing apparatus 400. Therefore, in the following description of the second embodiment and in FIG. 7, like components are denoted by like reference numerals as of the above-described data processing apparatus 400 of the first embodiment and are not further described.
Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8601316 *Mar 9, 2011Dec 3, 2013Hon Hai Precision Industry Co., Ltd.Power supply systemUS20120179929 *Mar 9, 2011Jul 12, 2012Hon Hai Precision Industry Co., Ltd.Power supply system* Cited by examinerClassifications U.S. Classification713/340International ClassificationG06F11/30Cooperative ClassificationG06F2212/222, G06F2212/2024, G06F12/0802Legal EventsDateCodeEventDescriptionJul 8, 2009ASAssignmentOwner name: FUJITSU LIMITED,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MIYAZAKI, SADAO;ISHIBASHI, OSAMU;NAKANO, RIKIZO AND OTHERS;SIGNED BETWEEN 20090615 AND 20090617;US-ASSIGNMENT DATABASE UPDATED:20100304;REEL/FRAME:22926/615Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MIYAZAKI, SADAO;ISHIBASHI, OSAMU;NAKANO, RIKIZO;AND OTHERS;SIGNING DATES FROM 20090615 TO 20090617;REEL/FRAME:022926/0615Owner name: FUJITSU LIMITED, JAPANRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google