Source: http://www.google.com.au/patents/US9029945
Timestamp: 2017-12-14 19:10:07
Document Index: 49387324

Matched Legal Cases: ['Application No. 200780029460', 'application No. 09163424', 'application No. 09177558', 'Application No. 07112298', 'Application No. 12782380', 'Application No. 2014', 'art 2']

Patent US9029945 - Field effect transistor devices with low source resistance - Google Patents
A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region...http://www.google.com.au/patents/US9029945?utm_source=gb-gplus-sharePatent US9029945 - Field effect transistor devices with low source resistance
Publication number US9029945 B2
Application number US 13/102,510
Also published as US20120280252
Publication number 102510, 13102510, US 9029945 B2, US 9029945B2, US-B2-9029945, US9029945 B2, US9029945B2
Inventors Sei-Hyung Ryu, Doyle Craig Capell, Lin Cheng, Sarit Dhar, Charlotte Jonas, Anant Agarwal, John Palmour
Patent Citations (297), Non-Patent Citations (194), Referenced by (5), Classifications (18), Legal Events (3)
Field effect transistor devices with low source resistance
US 9029945 B2
A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.
a well region in the drift layer having a second conductivity type opposite the first conductivity type;
a source region in the well region, the source region having the first conductivity type and defining a channel region in the well region, wherein the source region comprises a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region;
a body contact region having the second conductivity type between at least two of the plurality of source contact regions and in contact with the well region; and
a source ohmic contact that is on at least one of the source contact regions and the body contact region, and that is not on the lateral source region, wherein the source ohmic contact is on the at least one of the source contact regions in a source contact region area and the source ohmic contact is on the body contact region in a body contact region area, and wherein a ratio of a minimum dimension p1 of the body contact region area to a minimum dimension w1 of the well region on a same plane as the body contact region area is greater than 0.2, wherein the body contact region comprises a plurality of body contact regions that are interspersed between the source contact regions and contact the source ohmic contact, and wherein ones of the plurality of body contact regions are not physically contacting other ones of the plurality of body contact regions.
2. The semiconductor device of claim 1, wherein the plurality of body contact regions are spaced apart from the channel region by the lateral source region.
3. The semiconductor device of claim 1, wherein a ratio of a minimum dimension n1 of the source contact region area to a minimum dimension w1 of the well region is greater than 0.2.
4. The semiconductor device of claim 3, wherein the ratio of the minimum dimension n1 of the source contact region area to the minimum dimension w1 of the well region is between 0.3 and 1.
5. The semiconductor device of claim 3, wherein the ratio of the minimum dimension n1 of the source contact region area to the minimum dimension w1 of the well region is greater than 0.5.
6. The semiconductor device of claim 1, wherein the ratio of the minimum dimension p1 of the body contact region area to the minimum dimension w1 of the well region is greater than about 0.3.
7. The semiconductor device of claim 1, wherein the ratio of the minimum dimension p1 of the body contact region area to the minimum dimension w1 of the well region is greater than about 0.5.
8. The semiconductor device of claim 1, wherein the drift region comprises a wide bandgap semiconductor material having a baudgap greater than 2.0 V.
9. The semiconductor device of claim 8, wherein the drift region comprises silicon carbide.
10. The semiconductor device of claim 8, wherein the drift region comprises silicon carbide having at least one of a 2H, 4H and 6H polytype.
11. The semiconductor device of claim 8, wherein the drift region comprises silicon carbide having at least one of a 3C and 15R polytype.
12. The semiconductor device of claim 1, wherein the source region has a sheet resistance and the source ohmic contact has a contact resistance, wherein the plurality of source contact regions are arranged in a layout such that a ratio of the sheet resistance in ohms per square to the contact resistance in ohms per square area is greater than 1, wherein the square is equal in size to the square area.
13. The semiconductor device of claim 1, wherein the device has a reverse blocking voltage in excess of 1000 volts and a current density greater than 700 amps per square centimeter.
14. The semiconductor device of claim 1, wherein the semiconductor device comprises a field effect transistor.
15. The semiconductor device of claim 1, wherein the semiconductor device comprises an insulated gate bipolar transistor.
16. The semiconductor device of claim 1, wherein each of the plurality of body contact regions is laterally adjacent to the lateral source region.
17. The semiconductor device of claim 16, further comprising a second lateral source region adjacent to ends of the plurality of body contact regions opposite the lateral source region, wherein the second lateral source region separates the plurality of body contact regions from a second channel.
18. The semiconductor device of claim 1, wherein each of the plurality of body contact regions is in contact with the source ohmic contact.
a well region having a second conductivity type that is opposite the first conductivity type;
a source region in the well region, the source region having the first conductivity type;
a body contact region having the second conductivity type in contact with the well region; and
a source ohmic contact that is on the source region in a source contact region area and that is on the body contact region in a body contact region area;
wherein a ratio of a smallest width dimension n1 of the source contact region area to a smallest width dimension w1 of the well region on a same plane as the source contact region area is greater than 0.3, wherein the body contact region is between both ends of the smallest width dimension w1.
20. The semiconductor device of claim 19, wherein the ratio of the smallest width dimension n1 of the source contact region area to the smallest width dimension w1 of the well region is greater than 0.5.
a source ohmic contact that is on the source region in a source contact area and that is on the body contact region in a body contact region area;
wherein a ratio of a smallest width dimension p1 of the body contact region area to a smallest width dimension w1 of the well region on a same plane as the body contact region area is greater than 0.2, wherein the body contact region is between both ends of the smallest width dimension w1.
22. The semiconductor device of claim 21, wherein the ratio of the smallest width dimension p1 of the body contact region area to the smallest width dimension w1 of the well region is greater than about 0.3.
23. The semiconductor device of claim 21, wherein the ratio of the smallest width dimension p1 of the body contact region area to the smallest width dimension w1 of the well region is greater than about 0.5.
This invention was made with Government support under Contract No. DAAD19-01-C-0067 awarded by Army Research Laboratory. The Government has certain rights in the invention.
The present invention relates to electronic devices and fabrication methods. More particularly, the present invention relates to high power insulated gate transistors and fabrication methods.
A semiconductor device according to some embodiments includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region, and a source ohmic contact is in contact with the source contact regions and the body contact region.
The body contact region may include a plurality of body contact regions that are interspersed between the source contact regions. The plurality of body contact regions may be spaced apart from the channel region by the lateral source region.
The source ohmic contact may be in contact with the source region in a source contact area and the source ohmic contact may be in contact with the body contact region in a body contact region area.
In some embodiments, a ratio of a minimum dimension p1 of the contact region area to a minimum dimension w1 of the well region may be greater than 0.2. In further embodiments, the ratio of the minimum dimension p1 of the contact region area to the minimum dimension w1 of the well region may be greater than about 0.3.
The drift region may include a wide bandgap semiconductor material, such as silicon carbide.
The source region has a sheet resistance and the source ohmic contact has a sheet resistance that is greater than 75% of the contact resistance of the source region, and in some embodiments is greater than the contact resistance of the source region.
The device may have a reverse blocking voltage in excess of 1000 volts and a current density greater than 200 amps per square centimeter.
FIG. 1 is a circuit diagram of a metal-oxide-semiconductor field effect (MOSFET) device.
FIG. 2 is a graph illustrating hypothetical on-state current-voltage characteristics for a MOSFET device.
FIG. 3 is a graph illustrating the effect of source resistance on gate voltage.
FIG. 4 is a partial cross sectional illustration of cell of a conventional power MOSFET device.
FIGS. 5 and 6 are plan views illustrating layouts of conventional power MOSFET devices.
FIGS. 7 and 8 are plan views illustrating layouts of power MOSFET devices according to some embodiments.
FIGS. 9 and 10 are partial cross sectional illustrations of a cell of a power MOSFET device according to some embodiments.
FIG. 11 is a graph on-state current-voltage characteristics for a MOSFET device according to some embodiments.
FIG. 12 is a cross sectional illustration of cell of a power MOSFET device according to some embodiments.
FIG. 13 is a cross sectional illustration of cell of an insulated gate bipolar transistor device according to some embodiments.
Some embodiments of the invention provide silicon carbide (SiC) insulated gate devices that are suitable for high power and/or high temperature applications.
FIG. 1 is a circuit diagram of a metal oxide semiconductor field effect transistor (MOSFET) device 10. As shown therein, a MOSFET device generally includes three terminals, namely, a drain terminal (D), a source terminal (S) and a gate terminal (G). The gate-to-source voltage of the device is denoted VGS, while the drain-to-source voltage of the device is denoted VDS. The device has a built in source resistance RS and a built-in drain resistance RD based on the physical characteristics of the device. The voltage over the built-in source resistance RS is denoted VRs.
FIG. 2 is a graph illustrating hypothetical (curve 102) and actual (104) on-state current-voltage characteristics for a MOSFET device for a given gate-to-source voltage (VGS). As shown in FIG. 2, for a given gate voltage, the current through the device (ID) increases as the voltage between the drain and source (VDS) increases, up to a saturation point. In actual devices, the actual saturation current of a transistor is typically less than the ideal saturation current. Part of the reason for this relates to the source resistance of the device.
In particular, as the drain current ID passing through the device increases, the amount of voltage dropped over the source resistance RS increases in direct proportion. FIG. 3 is a graph illustrating the effect of source resistance on gate voltage. In FIG. 3, the voltage from the gate terminal to the source terminal is denoted VGS. A portion of the gate voltage VGS applied to the device across the gate and source terminals is dropped over the internal source resistance RS of the device. That portion of the gate voltage is denoted VRs in FIG. 3. The remainder of the gate-to-source voltage appears as a voltage across the gate insulator, denoted VGS,int in FIG. 3. Thus, VGS is equal to the sum of VRs and VGS,int.
As shown in FIG. 3, the gate-to-source voltage may remain constant as the drain current increases. However, the portion of the gate voltage VGS that is dropped over the internal source resistance of the device, VRs, increases as the drain current ID increases, while the portion of the gate-to-source voltage that appears as a voltage across the gate insulator, VGS,int, decreases as the drain current ID increases.
A unit cell 10 of a MOSFET structure according to some embodiments is shown in FIG. 4. The device 10 of FIG. 1 includes an n− drift epitaxial layer 14 on an n-type, 8° off-axis 4H—SiC substrate 12. The n− drift layer 14 may have a thickness of about 100 μm to about 120 μm, and may be doped with n-type dopants at a doping concentration of about 2×1014 cm−3 to about 6×1014 cm−3 for a blocking capability of about 10 kV. Other doping concentrations/voltage blocking ranges are also possible.
In some embodiments, the dry O2 oxide growth may be performed at a temperature of about 1175° C. in dry O2 for about 4 hours. The resulting oxide layer may be annealed at a temperature of up to about 1175° C. in an inert atmosphere. In particular, the resulting oxide layer may be annealed at a temperature of about 1175° C. in Ar for about a time duration ranging from 30 min to 2 hours. Then the oxide layer receives an anneal in NO ambient at a temperature ranging from 1175 C to 1300 C, for a duration ranging from 30 minutes to 3 hours. The resulting gate oxide layer may have a thickness of about 500 Å.
Referring to FIG. 4, the source resistance of a MOSFET device has two primary components, namely, the contact resistance RC between the source ohmic contact 34 and the source region 20, and the sheet resistance Rsheet in the source region 20 between the source ohmic contact 34 and the channel. Thus, RS=RC+Rsheet. In a conventional silicon-based MOSFET device, the sheet resistance Rsheet is the dominant factor in determining the source resistance, because it is possible to form very low resistivity ohmic contacts to silicon and other narrow-bandgap semiconductors. However, in wide bandgap semiconductors (i.e., semiconductors having a bandgap greater than about 2.0 V), including compound semiconductor materials, such as silicon carbide and gallium nitride, diamond, and ZnO, the contact resistance RC may be the dominant contributor to the source resistance. In particular, it is difficult to form very low resistivity ohmic contacts to silicon carbide and other wide bandgap materials because of the high energy barrier associated with such materials.
FIGS. 5 and 6 are plan views illustrating layouts of conventional power MOSFET devices. In a conventional power MOSFET device, the layout is designed to reduce or minimize sheet resistance under the assumption that contact resistance is less important than sheet resistance. Thus, referring to FIG. 5, a conventional power MOSFET device typically includes a p-well 18 formed in a drift layer 14, an n+ source region 20 in the p-well 18, and a p+ contact region 22 in the n+ source region 20. Referring to FIG. 6, a source contact 34 is formed on the n+ source region 20 and the p+ contact region 22. A gate 32 is formed over the p-well 18 and overlaps the periphery of the n+ source region 20 and adjacent portions of the drift layer 14. Current flow from the drain to the source is indicated by the arrows 42 in FIG. 5.
FIGS. 7 and 8 are plan views illustrating layouts of MOSFET device cells 100 according to some embodiments, and FIGS. 9 and 10 are partial cross sectional illustrations of a cell of a MOSFET device according to some embodiments. In particular, FIG. 9 is a cross section taken along line A-A′ of FIG. 8, while FIG. 10 is a cross section taken along line B-B′ of FIG. 8.
The device 100 shown in FIGS. 7-10 includes an n− drift epitaxial layer 114 on an n-type, 8° off-axis 4H—SiC substrate 112. The n− drift layer 114 may have a thickness of about 100 μm to about 120 μm, and may be doped with n-type dopants at a doping concentration of about 2×1014 cm−3 to about 6×1014 cm−3 for a blocking capability of about 10 kV.
Referring to FIG. 7, the n+ source region 120 includes a pair of lateral source regions 120A that are parallel to opposing channel regions 125 in the p-well 118. A plurality of source contact regions 120B extend between the lateral source regions 120A, and the plurality of p+ contact regions 122 are provided between the source contact regions 120B.
Referring to FIG. 8, gate contacts 132 are formed over the channel regions 125 and overlap the lateral source regions 120A. A source ohmic contact 134 is formed across the source contact regions 120B and the p+ contact regions 122. The source ohmic contact 134 overlaps the source contact regions 120B in a source contact region 136. The source ohmic contact 134 overlaps the p+ contact regions 122 in a body contact region 138.
The portion of the source contact regions 120B contacted by the source ohmic contact 134 may have a minimum dimension that is larger than the minimum dimension that can be obtained for a conventional layout such as the layout shown in FIGS. 5 and 6 for a similar pitch/p-well size. Accordingly, the source contact resistance may be reduced without substantially increasing the device pitch/p-well size. The “minimum dimension” of a feature refers to the smallest width of the feature in any cross section of the feature. For example, the minimum dimension p1 of the body contact region 138, the minimum dimension n1 of the n-type contact region 136 and the minimum dimension w1 of the p-well region 118 are shown in FIG. 8.
In a device having a layout as shown in FIGS. 7 and 8, current flow to the source contact flows through the source contact regions 120B, as indicated by the arrows 142 in FIG. 7. The source contact regions 120B may have an increased sheet resistance compared to the source region of a device having a conventional layout as shown in FIGS. 5 and 6. However, the increase in sheet resistance may be more than compensated by the decrease in contact resistance, thus providing an overall decrease in the source resistance of the device.
FIG. 11 is a graph of on-state current-voltage characteristics for a 7 mm×8 mm 1200 V silicon carbide MOSFET device according to some embodiments. In the device characteristics illustrated in FIG. 11, a drain current (ID) of 377 A was measured at a forward voltage drain-to-source voltage (VDS) of 3.8 V. The current density, normalized to the active area, was over 750 A/cm2.
FIG. 12 is an idealized cross section of a device having a layout in accordance with some embodiments. In particular, FIG. 12 illustrates some dimensions of a device having a layout in accordance with some embodiments. For example, as shown in FIG. 12, the minimum dimension of the implanted cell area (i.e. the p-well 118) is denoted as width w1 in FIG. 12. It will be appreciated, however, that the minimum dimension of the p-well 118 may occur in a dimension that is different from the plane of the device illustrated in FIG. 12. For example, the minimum dimension of the p-well 118 may occur in a dimension that is perpendicular to the plane of the device illustrated in FIG. 12.
The minimum dimension of the n-type contact area is denoted as width n1 in FIG. 12, while the minimum dimension of the p-type contact area is denoted as width p1 in FIG. 12. The n-type contact area may be defined as the area of overlap between the source ohmic contact 134 and the n+ source region 120, while the p-type contact area may be defined as the area of overlap between the source ohmic contact 134 and the p+ contact regions 122.
An insulated gate bipolar transistor (IGBT) device 200 according to some embodiments is illustrated in FIG. 13. As shown therein, the IGBT device includes an n− drift epitaxial layer 214 on a p-type epitaxial layer 212. The p-type epitaxial layer 212 is formed on a p-type, 8° off-axis 4H—SiC substrate 210. The n− drift layer 214 may have a thickness of about 100 μm to about 120 μm, and may be doped with p-type dopants at a doping concentration of about 2×1014 cm−3 to about 6×1014 cm−3 for a blocking capability of about 10 kV.
Some embodiments provide transistor devices having increased current densities. Current density is defined as the total current divided by the cross sectional area of the chip. For example, a wide bandgap transistor device according to some embodiments may be capable of current densities in excess of 200 A/cm2 and a blocking voltage of 1000 V or more. A wide bandgap transistor device according to further embodiments may be capable of a current of 100 A or greater at current densities in excess of 200 A/cm2, a forward voltage drop of less than 5 V and a blocking voltage of 1000 V or more. A wide bandgap transistor device according to still further embodiments may be capable of a current of 100 A or greater at current densities in excess of 300 A/cm2, a forward voltage drop of less than 5 V and a blocking voltage of 1000 V or more.
An IGBT device according to some embodiments with a voltage blocking capability of 10 kV or greater may have a specific on-resistance of less than 14 mOhm-cm2 with a forward voltage drop of 5.2 V or less at a current density of 100 A/cm2.
It will be appreciated that although some embodiments of the invention have been described in connection with silicon carbide IGBT and MOSFET devices having n-type drift layers, the present invention is not limited thereto, and may be embodied in devices having p-type substrates and/or drift layers. Furthermore, the invention may be used in many different types of devices, including but not limited to insulated gate bipolar transistors (IGBTs), MOS controlled thyristors (MCTs), insulated gate commutated thyristors (IGCTs), junction field effect transistors (JFETs), high electron mobility transistors (HEMTs), etc.
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U.S. Classification 257/341, 257/342, 257/E21.054, 257/E21.065, 257/77
International Classification H01L31/0312, H01L29/66, H01L29/15, H01L29/739, H01L29/06, H01L29/16, H01L29/04, H01L29/78
Cooperative Classification H01L29/7802, H01L29/1608, H01L29/7395, H01L29/045, H01L29/0696
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