Source: http://www.google.com/patents/US6531768?ie=ISO-8859-1&dq=6650327
Timestamp: 2014-08-22 10:46:05
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Patent US6531768 - Semiconductor integrated circuit device with optical wave guides - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA laser beam is irradiated onto a photocurable resin layer formed on an electrode part before rearrangement. By scanning the resin on the periphery of a metal wiring formation area extending from the electrode part before rearrangement to a bump electrode contact area, is cured. As a result, a cured...http://www.google.com/patents/US6531768?utm_source=gb-gplus-sharePatent US6531768 - Semiconductor integrated circuit device with optical wave guidesAdvanced Patent SearchPublication numberUS6531768 B2Publication typeGrantApplication numberUS 09/951,981Publication dateMar 11, 2003Filing dateSep 14, 2001Priority dateMar 14, 2000Fee statusLapsedAlso published asUS6518664, US6656829, US20010024872, US20020013043, US20030124830Publication number09951981, 951981, US 6531768 B2, US 6531768B2, US-B2-6531768, US6531768 B2, US6531768B2InventorsToshio MiyamotoOriginal AssigneeHitachi, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (10), Referenced by (1), Classifications (50), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor integrated circuit device with optical wave guidesUS 6531768 B2Abstract A laser beam is irradiated onto a photocurable resin layer formed on an electrode part before rearrangement. By scanning the resin on the periphery of a metal wiring formation area extending from the electrode part before rearrangement to a bump electrode contact area, is cured. As a result, a cured resin part is formed which works as a guide layer and a protection film for protecting the metal wire in which the metal wiring formation area has a hollow shape. Thereafter, the metal wire is formed inside the cured resin part.
BACKGROUND OF THE INVENTION The present invention relates to a technique for manufacturing a semiconductor integrated circuit device. The invention particularly relates to a technique effective for application to a CSP (chip size package) that is electrically connected via a metal wire between a bump electrode disposed on a chip and an electrode part before rearrangement.
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device having a stress relaxing force and being capable of forming both a metal wiring part and a guide layer in a relatively simple process and in high precision by utilizing a photocurable resin. The guide layer also works as a protection film for protecting a metal wire.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a key part of a substrate showing a method of manufacturing a semiconductor integrated circuit device relating to embodiment 1 of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be explained in detail below with reference to the drawings. In explaining the embodiments, components having the same function will be denoted by the same reference numbers or symbols, and repetitive explanation of the components will be omitted.
Embodiment 1 A method of manufacturing a semiconductor integrated circuit device, which is embodiment 1 of the present invention, will be explained with reference to FIG. 1 to FIG. 6 in sequence.
Embodiment 2 Next, a method of manufacturing a semiconductor integrated circuit device, which is embodiment 2 of the present invention, will be explained with reference to FIG. 7 to FIG. 16 in sequence.
Embodiment 3 A method of manufacturing a semiconductor integrated circuit device, which is embodiment 3 of the present invention, will be explained with reference to FIG. 17 to FIG. 26 in sequence.
Embodiment 4 Next a method of manufacturing a semiconductor integrated circuit device, which is embodiment 4 of the present invention will be explained with reference to FIG. 27 to FIG. 32 in sequence.
Embodiment 5 Next a method of manufacturing a semiconductor integrated circuit device, which is embodiment 5 of the present invention, will be explained with reference to FIG. 33 to FIG. 37 in sequence.
Embodiment 6 When the Embodiments 1 to 5 in common have the same layout of the electrode parts before rearrangement as that of the layout of the bump electrodes and the same copper wires in shape, it is possible to install an optical system for branching a laser beam into a plurality of beams and to form a plurality of cured resin parts 6 simultaneously, in order to increase the throughput of the cured resin parts 6. In this case, the optical system of the device is designed so that intervals of the laser beams match pitches between the bump electrodes.
Embodiment 7 Next, each shape of the cured resin parts 6 will be explained with reference to FIG. 28 explained in the embodiment 4, and FIGS. 38(a) and 38(b) and FIGS. 39(a) to 39(c). FIGS. 38(a) and 38(b) show cross-sectional views taken along a line A-A′ in FIG. 28, respectively. As shown in FIG. 38(a),each cross section of the cured resin parts 6 formed on the resist film 41 taken along the line A-A′ (FIG. 28), can have a square shape. Further, as shown in FIG. 38(b), each cross section of the cured resin parts 6 taken along the line A-A′ (FIG. 28), may have a semicircle shape (an inverse U shape). Further, it is also possible to form each cross section of the cured resin parts 6 in a U shape not shown.
Embodiment 8 Further, it is also possible to provide radiating plates 81 by using a photocurable resin as shown in FIG. 40. In other words, after forming the photocurable resin layer on the resist film 52 and the electrode parts before rearrangement BP of FIG. 33 described in the embodiment 5, the scanning is performed with the laser beam to form the cured resin parts 6. At this time, the laser beam is irradiated onto the photocurable resin positioned at a portion other than the peripheral portions of the metal wiring formation area, thereby forming the uneven surface portions (81) (FIG. 40). These uneven surface portions play roles of the radiating plates. By forming these uneven surface portions, it is possible to effectively radiate heat created on active element formation surfaces of the substrate. Further, it is possible to form the radiating plates 81 in the same process as that for forming the cured resin parts 6 that become the guide parts of the metal wires. Therefore, it is possible to obtain the above-mentioned effects in a simple process.
Embodiment 9 In the Embodiments 1 to 5, the laser beam is irradiated onto the photocurable resin layer, and each of the cured resin parts 6 (the guide layers), in which the metal wiring formation area has a hollow shape, is provided. Then, the copper wires 7 are formed in these hollow-shaped parts. In stead of this, each of the above-mentioned photocurable resin parts can be used as the wiring layer if an electroplating is performed on each surface of the photocurable resin parts, each of which plays a role of a core.
Embodiment 10 Further, when this photocurable resin is used, it is possible to easily form an optical signal transmission path of a semiconductor integrated circuit device having an optical input/output part.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4699449 *Mar 5, 1985Oct 13, 1987Canadian Patents And Development Limited-Societe Canadienne Des Brevets Et D'exploitation LimiteeOptoelectronic assembly and method of making the sameUS5049978 *Sep 10, 1990Sep 17, 1991General Electric CompanyConductively enclosed hybrid integrated circuit assembly using a silicon substrateUS5119451 *Dec 31, 1990Jun 2, 1992Texas Instruments IncorporatedOptical waveguides as interconnects from integrated circuit to integrated circuit and packaging method using sameUS5159700 *Mar 13, 1991Oct 27, 1992Texas Instruments IncorporatedSubstrate with optical communication systems between chips mounted thereon and monolithic integration of optical I/O on silicon substratesUS5476211Nov 16, 1993Dec 19, 1995Form Factor, Inc.Method of manufacturing electrical contacts, using a sacrificial memberUS6014313 *Dec 19, 1997Jan 11, 2000Telefonaktiebolgey Lm EricssonPackaging structure for integrated circuitsUS6274391 *Oct 26, 1992Aug 14, 2001Texas Instruments IncorporatedHDI land grid array packaged device having electrical and optical interconnectsUS6301401 *Mar 1, 2000Oct 9, 2001Convergence Technologies, Ltd.Electro-optical package for reducing parasitic effectsJPH08293509A Title not availableJPH08340002A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6690090 *Jan 28, 2002Feb 10, 2004Nec Electronics CorporationSemiconductor device having reliable coupling with mounting substrate* Cited by examinerClassifications U.S. Classification257/687, 257/E21.174, 257/E23.021, 257/E21.175, 257/E21.508, 257/E21.576International ClassificationH01L23/12, H01L23/52, H01L21/3205, H01L23/473, H01L23/36, H01L21/60, H01L23/485, H01L21/768, H01L21/288Cooperative ClassificationH01L2224/45147, H01L2224/45124, H01L21/2885, H01L2924/01056, H01L2924/01079, H01L2924/01013, H01L2224/13016, H01L24/13, H01L2924/01006, H01L2224/1357, H01L2924/014, H01L2224/13082, H01L24/11, H01L2924/01005, H01L2224/13147, H01L2924/01075, H01L2924/01078, H01L2224/1134, H01L2924/01029, H01L2924/14, H01L2924/3011, H01L2224/131, H01L2224/1308, H01L2924/00013, H01L21/76802, H01L2224/1369, H01L2224/16105, H01L21/288, H01L2924/01033, H01L2924/01004, H01L2924/00014European ClassificationH01L24/11, H01L24/10, H01L21/288, H01L21/288ELegal EventsDateCodeEventDescriptionMay 3, 2011FPExpired due to failure to pay maintenance feeEffective date: 20110311Mar 11, 2011LAPSLapse for failure to pay maintenance feesOct 18, 2010REMIMaintenance fee reminder mailedAug 18, 2006FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google