Source: http://www.google.es/patents/US9164933
Timestamp: 2017-11-23 20:38:19
Document Index: 658575443

Matched Legal Cases: ['Application No. 10178139', 'Application No. 10178143', 'Application No. 10177780', 'Application No. 10177780', 'Application No. 10178143', 'Application No. 10177780', 'Application No. 10177780', 'Application No. 10178143', 'Application No. 07119986', 'Application No. 10177780', 'Application No. 10178567', 'Application No. 10178143', 'Application No. 10178139', 'Application No. 00972087', 'Application No. 10177780', 'Application No. 07119986', 'Application No. 05', 'Application No. 10177780', 'Application No. 10177780', 'Application No. 10178143', 'Application No. 07119986', 'Application No. 10178567']

Patente US9164933 - Memory system with calibrated data communication - Google Patentes
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing...http://www.google.es/patents/US9164933?utm_source=gb-gplus-sharePatente US9164933 - Memory system with calibrated data communication
Número de publicación US9164933 B2
Número de solicitud US 14/613,276
Fecha de presentación 3 Feb 2015
También publicado como DE20023766U1, DE60027038D1, DE60027038T2, DE60045399D1, EP1226507A1, EP1226507A4, EP1226507B1, EP1624362A2, EP1624362A3, EP1624362B1, EP1879095A2, EP1879095A3, EP1879095B1, EP2264612A2, EP2264612A3, EP2264612B1, EP2264613A2, EP2264613A3, EP2264614A2, EP2264614A3, EP2264614B1, EP2278473A1, EP2278473B1, US6643787, US6950956, US7042914, US7535933, US8170067, US8630317, US8948212, US9405678, US9785589, US20040076192, US20040098634, US20060120409, US20090327789, US20120204054, US20140229667, US20150169478, US20160011973, US20170031854, WO2001029680A1, WO2001029680A9
Número de publicación 14613276, 613276, US 9164933 B2, US 9164933B2, US-B2-9164933, US9164933 B2, US9164933B2
Citas de patentes (138), Otras citas (42), Clasificaciones (20), Eventos legales (1)
US 9164933 B2
1. A memory sub-system comprising:
a plurality of flash memory devices coupled to a bus; and
a set of bus transceiver devices coupled to the bus, each individual bus transceiver device in the set comprising:
an interface circuit for coupling the bus transceiver device to a memory controller;
circuitry to receive a signal to individually address the individual bus transceiver device by the memory controller;
a reference voltage register to store a device-specific value; and
a receiver circuit to receive a data signal transmitted by the memory controller to the individual bus transceiver device;
wherein the device-specific value stored in the reference voltage register of each individual bus transceiver device controls a reference voltage used by the corresponding receiver circuit when receiving the data signal transmitted by the memory controller to the individual bus transceiver device.
2. The memory sub-system of claim 1, wherein the device-specific value stored in the reference voltage register of each individual bus transceiver device is determined during a calibration mode of operation of the individual bus transceiver device.
3. The memory sub-system of claim 1, wherein each individual bus transceiver device in the set of bus transceiver devices includes a write offset register to store a device-specific offset value corresponding to a receive timing adjustment; and
wherein the receiver circuit of each bus transceiver device is configured to sample the received data signal with a timing offset corresponding to the device-specific offset value stored in the write offset register.
4. The memory sub-system of claim 3, further comprising one of a flash memory device and a dynamic random access memory (DRAM) device.
5. The memory sub-system of claim 1, wherein each individual bus transceiver device in the set of bus transceiver devices includes:
a read offset register to store a device-specific offset value corresponding to a transmit timing adjustment; and
a transmit circuit to transmit a data signal from the individual bus transceiver device to the memory controller with a timing offset corresponding to the device-specific offset value stored in the read offset register.
6. The memory sub-system of claim 5, wherein the device-specific offset value stored in the read offset register is determined during a calibration mode of operation of each individual bus transceiver device.
7. The memory sub-system of claim 5, wherein each individual bus transceiver device in the set of bus transceiver devices includes a delay-locked-loop (DLL) or phase-locked-loop (PLL) circuit operable to produce a transmit clock signal coupled to a clock input of the transmit circuit, or a receive clock signal coupled to a clock input of the receiver circuit.
8. The memory sub-system of claim 1, wherein each individual bus transceiver device in the set of bus transceiver devices includes calibration circuitry operable in a calibration mode and comprising a phase detector, the phase detector of a respective individual bus transceiver device comprising:
a second input to receive a calibration sequence via a signal path associated with transmitting write data between the memory controller and the respective individual bus transceiver device, and
wherein the respective individual bus transceiver device further includes a transmitter to transmit the phase data to the memory controller.
9. The memory sub-system of claim 1, wherein each individual bus transceiver device in the set of bus transceiver devices includes calibration circuitry operable in a calibration mode, the calibration circuitry including a first input to receive a clock signal and a second input to receive a calibration sequence via a signal path associated with transmitting write data between the memory controller and the memory sub-system.
10. The memory sub-system of claim 9, wherein the calibration sequence is a data pattern received from the memory controller.
11. The memory sub-system of claim 1, wherein each individual bus transceiver device in includes a delay-locked-loop (DLL) or phase-locked-loop (PLL) circuit operable to produce a receive clock signal coupled to a clock input of the receiver circuit.
12. A method of operating a memory sub-system having a set of bus transceiver devices and a plurality of flash devices, the method comprising:
individually addressing, by a memory controller, each individual bus transceiver device in the set of bus transceiver devices;
storing, in each individual bus transceiver device of the set of bus transceiver devices, a device-specific value in a reference voltage register of the bus transceiver of the individual bus transceiver device; and
at a respective individual bus transceiver device in the set of bus transceiver devices, receiving a data signal, the data signal transmitted by the memory controller to the respective individual bus transceiver device;
wherein receiving the data signal includes receiving the data signal using a reference voltage controlled by the device-specific value stored in the reference voltage register of the respective individual bus transceiver device.
13. The method of claim 12, further including, storing the device-specific value in the reference voltage register of each individual bus transceiver device during a calibration mode of operation.
14. The method of claim 12, wherein each individual bus transceiver device in the set of bus transceiver devices includes a write offset register to store a device-specific offset value corresponding to a receive timing adjustment; and
the method includes sampling the data signal with a timing offset corresponding to the device-specific offset value stored in the write offset register of each respective individual bus transceiver device.
15. The method of claim 14, including storing the device-specific offset value in the write offset voltage register of each bus transceiver device during a calibration mode of operation.
16. The method of claim 14, including internally generating, within each individual bus transceiver device, a receive clock signal using a delay-locked-loop (DLL) or phase-locked-loop (PLL) circuit, and providing the receive clock signal to an input of the device's receiver circuit.
17. The method of claim 12, wherein each individual bus transceiver device in the set of bus transceiver devices includes a transmit circuit and a read offset register to store a device-specific offset value corresponding to a transmit timing adjustment; and
the method further includes, using the transmit circuit of a respective individual bus transceiver device, transmitting a data signal to the memory controller according to a timing offset corresponding to the device-specific offset value stored in the read offset register of the respective individual bus transceiver device.
18. The method of claim 17, including storing the device-specific value in the read offset register of each individual bus transceiver device during a calibration mode of operation.
19. The method of claim 12, wherein each individual bus transceiver device in the set of bus transceiver devices includes calibration circuitry operable in a calibration mode, the method further including, at each of the bus transceiver devices, while operating in the calibration mode, receiving a calibration sequence via a signal path associated with transmitting write data between the memory controller and the memory sub-system, generating phase data representing a phase difference between a clock signal and the received calibration sequence, and transmitting the phase data to the memory controller.
a set of transceiver devices coupled to the bus, each individual bus transceiver device in the set comprising:
The present application is a continuation of U.S. application Ser. No. 14/154,068, filed Jan. 13, 2014, now U.S. Pat. No. 8,948,212, issued Feb. 3, 2015, which is a continuation of U.S. application Ser. No. 13/447,080, filed Apr. 13, 2012, now U.S. Pat. No. 8,630,317, issued Jan. 14, 2014, which is a continuation of U.S. patent application Ser. No. 12/430,836, filed Apr. 27, 2009, now U.S. Pat. No. 8,170,067, issued May 1, 2012, which is a divisional of U.S. patent application Ser. No. 11/327,213, filed Jan. 5, 2006, now U.S. Pat. No. 7,535,933, issued May 19, 2009, which is continuation of U.S. patent application Ser. No. 10/684,618, filed Oct. 13, 2003, which is now U.S. Pat. No. 7,042,914, issued May 9, 2006, which is a continuation of U.S. patent application Ser. No. 09/421,073, filed Oct. 19, 1999, which is now U.S. Pat. No. 6,643,787, issued on Nov. 4, 2003, which are hereby incorporated by reference in their entireties.
FIG. 36A illustrates an output driver 700 that includes temporal equalization circuitry according to one embodiment of the present invention. A data signal, Dataj, is used to gate a weighted driver 701. When Data is a logical 1, the weighted driver 701 is turned ON to a degree determined by a current control value (CCTL) in register 703 so that a current ISIG flows through driver 701. Weighted equalization drivers 702A-702K are similarly gated by respective prior versions of the data signal (Dataj-1, Dataj-2, . . . , Dataj-K) to sink equalization currents IEQ1 through IEQK. Thus, the total current that flows through RTERM is given by: IOL=ISIG+IEQ1+IEQ2+ . . . IEQK, with each of the IEQ terms being controlled by equalization coefficients stored in respective equalization registers 704A-704K. Because the output voltage VOUT is equal to VTERM−IOL*RTERM, VOUT can be equalized to compensate for prior outputs by appropriate setting of equalization coefficients.
Equalization driver 702A includes a multiplexer 709, a set of additive logic gates 712A-712R and corresponding binary weighted transistors (1x, 2x, . . . , 2R−1x), and a set of subtractive logic gates 711A-711R and corresponding binary weighted transistors −1x, −2x, . . . , −2R−1x). In the embodiment shown in FIG. 36B, each of the equalization registers 704A-704K contains a signed value formed by a coefficient sign (bit S) and a coefficient magnitude (e.g., C1, C2, . . . , CK). Referring specifically to equalization register 704A, the coefficient sign is used to select between inverted and non-inverted versions of the data value Dataj, while each bit of the coefficient magnitude is input to a logic gate pair. Each logic gate pair consists of an additive and a subtractive logic gate both having a multiplier that corresponds to the bit position of the coefficient magnitude, but with opposite signs. For example, bit 1 of the coefficient magnitude is input to logic gates 712A and 711A which, depending on the state of Dataj-1, activate the 1x and the −1x transistors, respectively. Similarly, bit 2 of the coefficient magnitude is input to logic gates 712B and 711B to control activation of the 2x and −2x transistors, and bit R of the coefficient magnitude is input to logic gates 712R and 711R to control activation of the 2R−1x and −2R−1x transistors. Although FIG. 36B indicates that the coefficient magnitude includes at least three bits (i.e., R=3), the coefficient magnitude may include more or fewer than three bits without departing from the scope of the present invention.
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JPS3087907A2 Título no disponible
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16 EP Response dated Jul. 11, 2011 to the Official Communication dated Mar. 14, 2011 and to the European Search Opinion dated Feb. 8, 2011 re EP Application No. 10177780.3. 17 pages.
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19 EP Response dated Jul. 21, 2011 to the Official Communication dated Jan. 31, 2011 re EP Application No. 10178139.1. 19 pages.
20 EP Response dated Jun. 18, 2012 to the Official Communication pursuant Article 15(1) of the Rules of Procedure of the Boards of Appeal dated Feb. 17, 2012 in EP Application No. 00972087.1-2212, Includes Sixth and Seventh Auxiliary Requests (Clear and Highlighted copies). 45 pages.
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Clasificación internacional G06F13/42, G06F13/16, G06F1/10, G06F12/02
Clasificación cooperativa G06F13/4282, G06F13/404, G06F13/364, G06F12/0246, G06F3/0679, G06F3/0659, G06F3/061, G06F2212/7201, G06F13/1689, G06F2212/7207, H04L7/033, G06F1/10, G11C7/1045, G06F13/1694, G06F13/4243, H04L7/0008