Source: http://www.google.com/patents/US5301193?dq=6335678
Timestamp: 2015-05-23 04:20:44
Document Index: 316152278

Matched Legal Cases: ['art.\n1', 'art 46', 'art 57', 'art 54', 'art 57', 'art 15', 'art 15', 'art 18', 'art 15', 'art 15', 'art 950', 'art 950', 'art 950', 'art 107', 'art 951', 'art 951', 'art 108', 'art 951', 'art 950', 'art 951', 'art 950', 'art 950', 'art 108', 'art 108', 'art 951', 'art 108', 'art 109', 'art 109']

Patent US5301193 - Delay distortion suppressing system for ATM communication system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA delay distortion suppressing system is for use in an asynchronous transfer mode communication system which includes at least a transmitting end and a receiving end which are connected via transmission paths. The delay distortion suppressing system includes a first part provided in the transmitting...http://www.google.com/patents/US5301193?utm_source=gb-gplus-sharePatent US5301193 - Delay distortion suppressing system for ATM communication systemAdvanced Patent SearchPublication numberUS5301193 APublication typeGrantApplication numberUS 07/791,524Publication dateApr 5, 1994Filing dateNov 14, 1991Priority dateNov 14, 1990Fee statusPaidAlso published asCA2055396A1, CA2055396C, DE69128924D1, DE69128924T2, EP0485971A2, EP0485971A3, EP0485971B1Publication number07791524, 791524, US 5301193 A, US 5301193A, US-A-5301193, US5301193 A, US5301193AInventorsHidetoshi Toyofuku, Masanori Kajiwara, Takeshi Tanaka, Hideki Mase, Atsuyuki Mukai, Tomonobu TakashimaOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (7), Referenced by (34), Classifications (11), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetDelay distortion suppressing system for ATM communication system
US 5301193 AAbstract
A delay distortion suppressing system is for use in an asynchronous transfer mode communication system which includes at least a transmitting end and a receiving end which are connected via transmission paths. The delay distortion suppressing system includes a first part provided in the transmitting end for transmitting information in the form of cells in an asynchronous transfer mode, a second part provided in the receiving end for delaying each cell which is received via a transmission path by a predetermined delay time relative to a reference point, a third part provided in the receiving end for varying the reference point depending on an arrival time of the cell which is received at the receiving end via the transmission path, so that a delay distortion of the cells is suppressed, and a fourth part including a decoding part for decoding the cells output from the second part.
1. A delay distortion suppressing system for an asynchronous transfer mode communication system, having a transmission path carrying cells having a header and an information field, comprising:a transmitting end; first means, provided in the transmitting end, for transmitting information over the transmission path in the form of cells in the asynchronous transfer mode, and for inserting a cell transmission time in the header of each cell; second means for delaying each cell transmitted over the transmission path to, and received by, receiving means by a predetermined delay time relative to a selectively variable reference point, wherein the second means further comprises:storage means for storing each cell transmitted over the transmission path, inserting means for inserting a cell reception time in the header of each cell transmitted over the transmission path, control means for controlling write and read operations of the storage means based on the cell transmission time and the cell reception time stored in the header of each cell which is read out from the storage means, and the control means for controlling a delay distortion suppressing range and the predetermined delay time so that the cell, which arrives first, is written into the storage means and read out after a time which corresponds to the delay distortion suppressing range; third means, coupled to the second means, for varying the reference point depending on the cell reception time of the received cell, so that delay distortion of the cells is suppressed, whereinthe third means varies the reference point if a difference between the cell transmission time and the cell reception time is smaller than the predetermined delay time; and fourth means coupled to the second means, for decoding the cells output from the second means, 2. The delay distortion suppressing system as claimed in claim 1, wherein the predetermined delay time is a minimum delay time of the cell.
The present invention generally relates to delay distortion suppressing systems, and more particularly to a delay distortion suppressing system for use in an asynchronous transfer mode (ATM) communication system.
FIG. 2 shows an essential part of an example of a conventional ISDN employing the ATM. In FIG. 2, those parts which are basically the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted. In this example, a terminal 510 is telephone set, but various other kinds of terminals may be used as the terminal 510. The multiplexed cells are transmitted to the transmission line (not shown) via a switch 5201 of an ATM switch 520, and this ATM switch 520 carries out a switching operation so that the multiplexed cells are transmitted to an ATM switch (not shown) which is connected to a destination terminal (not shown) via the transmission line. On the other hand, the multiplexed cells which are received from the transmission line are supplied to the demultiplexer part 46 via a switch 5202 of the ATM switch 520.
Accordingly, it is a general object of the present invention to provide a novel and useful delay distortion suppressing system in which the problems described above are eliminated.
FIG. 1 is a system block diagram showing an essential part of an example of a conventional ATM communication system;
First, a description will be given of a first embodiment of a delay distortion suppressing system according to the present invention, by referring to FIG. 4. In this embodiment, the absolute delay time is reduced by writing the received cell into a FIFO memory and immediately reading out the cell for decoding.
Since the next cell Ca is an unvoiced cell and is not transmitted, the cell C5 having the next cell transmission time ST=50 is written into the FIFO memory 51, and a header H5 of the cell C5 is read out as shown in (d) of FIG. 4 when the counted value TT of the timer 52 is "40". The cell transmission time ST added to this header H5 is "50", and thus, TT<ST. During the read waiting time shown in (e) of FIG. 4 until the relationship TT=ST is obtained, no read clock signal RCK is supplied to the FIFO memory 51 and the supply of the information field of the cell C5 to the decoding part 57 is waited.
When the cell C8 having the cell transmission time ST=90 arrives at a point A, this cell C8 is written into the FIFO memory 51 and the empty flag EP becomes "0". The header of this cell C8 is read out from the FIFO memory 51 and the cell transmission time ST=90 is set in the register 55. The set control part 54 compares the cell transmission time ST in the register 55 and the counted value TT of the timer 52, and in this case, a reference point of the minimum delay time is changed because (ST-TT)<0. In addition, the information field of the cell C8 is supplied from the FIFO memory 51 to the decoding part 57 and decoded. The cells C9 and C10 which arrive after the cell C8 are read out from the FIFO memory 51 so that the difference between the counted value TT of the timer 52 and the cell transmission time ST becomes "15" and constant.
When the cell C11 having the cell transmission time ST=130 arrives at a point B when the counted value TT of the timer 52 is "150", the reference point of the minimum delay time is changed because (ST-TT)<-15. In addition, the information read out from the FIFO memory 51 is controlled so that the difference between the counted value TT of the timer 52 and the cell transmission time ST thereafter becomes "20".
The header H2 of the next received cell C2 is read out from the FIFO memory 11 after the decoding time of the received cell C1. As in the case of the received cell C1 described above, the cell transmission time ST=10 and the cell reception time TT=5 of the received cell C2 are set in the register 16. The judgement and read control part 15 obtains D2=TT-ST=-5 and compares D2 with D1=TT-ST=0 for the previous received cell C1. In this case, D1>D2, and thus, the judgement and read control part 15 changes the reference point of the minimum delay time. The information field of the received cell C2 is read out from the FIFO memory 11 to be decoded in the decoding part 18, after a time corresponding to D1-D2. Similarly, the header H3 of the next received cell C3 is read out from the FIFO memory 11 after the decoding time of the received cell C2. The cell transmission time ST=20 and the cell reception time TT=12 of this received cell C3 are set in the register 16. The judgement and read control part 15 obtains D3=TT-ST=-8. In this case, D2>D3, and thus, the judgement and read control part 15 changes the reference point of the minimum delay time. The information field of the received cell C3 is read out from the FIFO memory 11 to be decoded after a time corresponding to D2-D3.
The next received cell C4 has the cell transmission time ST=30 and the cell reception time TT=20. Hence, D4=TT-ST=-10, and D3>D4. For this reason, the reference point of the minimum delay time is changed, and the information field of the received cell C4 is read out from the FIFO memory 11 to be decoded after a time corresponding to D3-D4.
An unvoiced cell Ca exists after the received cell C4, and the received cell C5 exists after this unvoiced cell Ca. The received cell C5 has the cell transmission time ST=50 and the cell reception time TT=32. Hence, D5=TT-ST=-18, and D4>D5. Accordingly, the reference point of the minimum delay time is changed, and the information field of the received cell C5 is read out from the FIFO memory 11 to be decoded after a time corresponding to D4-D5. For the next received cell C6, D6=-20 and D5>D6, and the reference point of the minimum delay time is also changed in this case. For the next received cell C7, D7=-18 and D6<D7. In this case, the information field of the received cell C7 is read out from the FIFO memory 11 without changing the reference point of the minimum delay time. Therefore, the reference point of the minimum delay time is changed at the changed points 31 through 35 in (g) of FIG. 7.
D8=-15 and D6<D8 for the received cell C8. Hence, the reference point of the minimum delay time is not changed, but it can be detected from the cell transmission time ST that an unvoiced cell Ca exists next to the received cell C7. Thus, the information field of the received cell C8 is read out from the FIFO memory 11 to be decoded after a time TD corresponding to one cell decoding.
The delay distortion suppressing operation carried out at the receiving end will now be described with reference to FIG. 16. When the first one of the cells following the priority cell arrives at the receiving end, the distortion time detecting part 950 measures arrival time of this first cell with reference to the arrival time of the priority cell. The arrival times of the other following cells are measured similarly by the distortion time detecting part 950 so as to detect the delay time of each cell. The time intervals with which the normal cells, that is, the cells other than the priority cell, are generated, is known at the receiving end because the cell generation intervals at the transmitting end is known. Hence, the delay time of each cell can be calculated by determining the difference between the actual reception time of the cell and the predicted reception time of the cell with respect to the reception time of the priority cell. The distortion time I shown in FIG. 16 can be obtained for each cell by obtaining the delay time for each cell. The distortion times for a predetermined number of cells are measured, and a maximum distortion time Imax shown in FIG. 16 is obtained from the measured distortion times. In FIG. 16, tx denotes the reception time of the priority cell.
When the maximum distortion time Imax is obtained, the distortion time detecting part 950 of the cell disassembling part 107 supplies the distortion times I of each of the following cells to the distortion suppressing time calculating part 951. The distortion suppressing time calculating part 951 calculates the difference between the maximum distortion time Imax and the distortion.time of each cell, that is, calculates Imax -I=y shown in FIG. 16 for each cell. The calculation result y for each cell is supplied to the distortion suppressing part 108 which delays each cell by the corresponding delay time y. As a result, each cell is delayed by the constant time Imax in total, and the delay distortion is effectively suppressed.
A maximum distortion time detector 720 of the distortion suppressing time calculating part 951 detects and holds a maximum suppressing time Imax out of a predetermined number of suppressing times I, which are received from the suppressing time detecting part 950. Thereafter, the suppressing time detecting part 951 is started to calculate Imax -I=y with respect to the suppressing time I, which is received from the suppressing time detecting part 950. In other words, a subtracting circuit 721 subtracts the suppressing time I received from the suppressing time detecting part 950 from the maximum suppressing time Imax received from the maximum suppressing time detector 720. The result y output from the subtracting circuit 721 is supplied to the distortion suppressing part 108. The distortion suppressing part 108 delays the disassembled cell (that is, only the data of the information field) in a delay circuit 180 in response to the output signal of the distortion suppressing time calculating part 951 indicating the calculated result y. The output data of the distortion suppressing part 108 is supplied to the decoding part 109, which decodes the cell delayed by a predetermined delay time and therefore eliminates the delay distortion. The decoded data output from the decoding part 109 is transmitted to the terminal via the hybrid circuit 111.
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low power idle* Cited by examinerClassifications U.S. Classification370/395.4, 370/517, 370/474International ClassificationH04L12/931, H04L12/70, H04J3/06Cooperative ClassificationH04L49/206, H04J3/0632, H04L2012/5649European ClassificationH04L49/20C1, H04J3/06B6Legal EventsDateCodeEventDescriptionSep 9, 2005FPAYFee paymentYear of fee payment: 12Sep 20, 2001FPAYFee paymentYear of fee payment: 8Sep 22, 1997FPAYFee paymentYear of fee payment: 4Sep 13, 1994CCCertificate of correctionNov 14, 1991ASAssignmentOwner name: FUJITSU LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:TOYOFUKU, HIDETOSHI;KAJIWARA, MASANORI;TANAKA, TAKESHI;AND OTHERS;REEL/FRAME:005915/0843Effective date: 19911105RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services