Source: http://www.google.com/patents/US8076235?dq=5,941,947
Timestamp: 2015-05-25 09:42:42
Document Index: 558933980

Matched Legal Cases: ['art 224', 'art 224', 'art 224', 'art 224', 'art 224', 'art 224']

Patent US8076235 - Semiconductor device and fabrication method thereof - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsSemiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends...http://www.google.com/patents/US8076235?utm_source=gb-gplus-sharePatent US8076235 - Semiconductor device and fabrication method thereofAdvanced Patent SearchPublication numberUS8076235 B2Publication typeGrantApplication numberUS 12/913,142Publication dateDec 13, 2011Filing dateOct 27, 2010Priority dateJul 7, 2005Also published asUS7846832, US20070010085, US20110039408Publication number12913142, 913142, US 8076235 B2, US 8076235B2, US-B2-8076235, US8076235 B2, US8076235B2InventorsKuan-Chi Tsai, Chih-Hsun Lin, Sheng-Wen Su, Shaw-Jang LiouOriginal AssigneeTaiwan Semiconductor Manufacturing Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (9), Classifications (11), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and fabrication method thereof
US 8076235 B2Abstract
Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric layer and the first etch stop layer, and exposes parts of the substrate. The anti-diffusion layer overlies at least sidewalls of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer.
providing a substrate comprising a first etch stop layer overlying the substrate, a dielectric layer overlying the first etch stop layer, and an opening through the dielectric layer and the first etch stop layer, exposing parts of the substrate, wherein the opening comprises a narrow portion and a wide portion exposing the narrow portion; and
performing plasma treatment on the exposed first etch stop layer and dielectric layer, forming an insulating anti-diffusion layer overlying at least sidewalls of the narrow portion of the opening and overlying the dielectric layer beyond the wide portion of the opening, but not overlying sidewalls of the wide portion of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the insulating anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer.
2. The method as claimed in claim 1, wherein the substrate further comprises a second etch stop layer overlying the dielectric layer, and the opening further extends through the second etch stop layer.
3. The method as claimed in claim 2, wherein the second etch stop layer is treated by plasma simultaneously with the exposed first etch stop layer and dielectric layer, further extending the anti-diffusion layer to overlie the second etch stop layer.
4. The method as claimed in claim 1, wherein the plasma treatment utilizes hydrogen, helium, nitrogen, oxygen, or argon.
5. The method as claimed in claim 1, wherein the plasma treatment is performed at between approximately 10� C. and room temperature.
6. The method as claimed in claim 1, wherein the plasma treatment is performed at a power between approximately 250 and approximately 500 watts.
providing a substrate comprising a first etch stop layer overlying the substrate, a dielectric layer overlying the first etch stop layer, and an opening through the dielectric layer and the first etch stop layer, exposing parts of the substrate; and
performing plasma treatment on the exposed first etch stop layer and dielectric layer, forming an anti-diffusion layer overlying at least sidewalls of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer and wherein the plasma treatment is performed at between approximately 10� C. and room temperature.
8. The method as claimed in claim 7, wherein the substrate further comprises a second etch stop layer overlying the dielectric layer, and the opening further extends through the second etch stop layer.
9. The method as claimed in claim 8, wherein the second etch stop layer is treated by plasma simultaneously with the exposed first etch stop layer and dielectric layer, further extending the anti-diffusion layer to overlie the second etch stop layer.
10. The method as claimed in claim 7, wherein the plasma treatment utilizes hydrogen, helium, nitrogen, oxygen, or argon.
11. The method as claimed in claim 7, wherein the plasma treatment is performed at a power between approximately 250 and approximately 500 watts. Description
This application is a divisional of U.S. patent application Ser. No. 11/176,924, filed Jul. 7, 2005, entitled, “Semiconductor Device and Fabrication Method Thereof,” the entirety of which is incorporated herein by reference.
The invention relates to semiconductor technology, and more specifically to plasma applications.
Thus, embodiments of the invention provide semiconductor devices and methods for fabricating the same, preventing formation of resist scum, thereby improving device reliability and process cost.
An opening 225, such as a via for interconnection, is formed through the layers 221 and 222 and exposes parts of the substrate 200. An anti-diffusion layer 224, preventing contamination molecule, i.e. the alkaline molecules, diffusion from at least the first etch stop layer 221, overlies at least sidewalls of the opening 225. When the dielectric layer 222 comprises the potential contamination molecules, the anti-diffusion layer 224 preferably extends to overlie other exposed surfaces of the layer 222 as shown in FIG. 2A. Further, the layer comprises a first part 224 a overlying the first etch stop layer 221 and a second part 224 b overlying the dielectric layer 222. The first part 224 a is denser than the first etch stop layer 221, and the second part 224 b is denser than the dielectric layer 222. The first part 224 a is a densified part of the first etch stop layer 221, and comprises the same material as the first etch stop layer 221. The second part 224 b is a densified part of the dielectric layer 222, and comprises the same material as the dielectric layer 222.
In an alternative embodiment, the substrate 200 may further comprise a conductive region 210 exposed by the opening 225 as shown in FIG. 2C. The conductive region 210 may be doped substrate 200, doped polycrystalline silicon, or metal, such as copper, aluminum, copper-aluminum alloys, tungsten, or transparent electrodes. In some embodiments, the conductive region 210 may comprise conductive metal oxide, metal silicide, or metal nitride.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6013581Oct 5, 1998Jan 11, 2000United Microelectronics Corp.Method for preventing poisoned vias and trenchesUS6537896Dec 4, 2001Mar 25, 2003Lsi Logic CorporationProcess for treating porous low k dielectric material in damascene structure to form a non-porous dielectric diffusion barrier on etched via and trench surfaces in the porous low k dielectric materialUS6613666Dec 7, 2001Sep 2, 2003Applied Materials Inc.Method of reducing plasma charging damage during dielectric etch process for dual damascene interconnect structuresUS6656841Dec 10, 2002Dec 2, 2003Hynix Semiconductor Inc.Method of forming multi layer conductive line in semiconductor deviceUS6677251Jul 29, 2002Jan 13, 2004Taiwan Semiconductor Manufacturing Co., LtdMethod for forming a hydrophilic surface on low-k dielectric insulating layers for improved adhesionUS20010016418Dec 28, 2000Aug 23, 2001Hyundai Electronics Industries Co., Ltd.Method for forming interconnection of semiconductor deviceUS20050059232Sep 17, 2003Mar 17, 2005Andreas Michael T.Method for the post-etch cleaning of multi-level damascene structures having underlying copper metallizationUS20050230831Apr 19, 2004Oct 20, 2005International Business Machines CorporationStructure to improve adhesion between top CVD low-k dielectiric and dielectric capping layerUS20060151887Jan 5, 2006Jul 13, 2006Samsung Electronics Co., Ltd.Interconnection structure having double diffusion barrier layer and method of fabricating the sameClassifications U.S. Classification438/627, 438/637International ClassificationH01L21/768, H01L23/528, H01L21/108Cooperative ClassificationH01L21/76814, H01L21/76808, H01L21/76831European ClassificationH01L21/768B2D2, H01L21/768B10B, H01L21/768B2FLegal EventsDateCodeEventDescriptionOct 27, 2010ASAssignmentOwner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TSAI, KUAN-CHI;LIN, CHIH-HSUN;SU, SHENG-WEN;AND OTHERS;REEL/FRAME:025202/0870Effective date: 20050622RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services