Source: https://patents.google.com/patent/US8149874B2/en
Timestamp: 2018-06-18 23:51:09
Document Index: 43191557

Matched Legal Cases: ['Application No. 2006', 'Application No. 2011', 'Application No. 10180758', 'Application No. 10180766', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05706081', 'Application No. 05', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2011', 'application No. 05', 'Application No. 05706081', 'Application No. 2006', 'Application No. 05706081']

US8149874B2 - Adaptive-allocation of I/O bandwidth using a configurable interconnect topology - Google Patents
US8149874B2
US8149874B2 US13110217 US201113110217A US8149874B2 US 8149874 B2 US8149874 B2 US 8149874B2 US 13110217 US13110217 US 13110217 US 201113110217 A US201113110217 A US 201113110217A US 8149874 B2 US8149874 B2 US 8149874B2
US13110217
US20110219162A1 (en )
US13110217 2004-01-28 2011-05-18 Adaptive-allocation of I/O bandwidth using a configurable interconnect topology Active US8149874B2 (en)
US12177747 Continuation US8073009B2 (en) 2004-01-28 2008-07-22 Adaptive allocation of I/O bandwidth using a configurable interconnect topology
US8149874B2 true US8149874B2 (en) 2012-04-03
EP0154551A2 (en) 1984-03-06 1985-09-11 Codex Corporation Apparatus for enabling a first processor to cause a second processor to effect a transfer of data between said processors
US20020071431A1 (en) 2000-12-13 2002-06-13 Chakravarthy Kosaraju Method and an apparatus for a re-configurable processor
US20020078280A1 (en) 2000-12-19 2002-06-20 International Business Machines Corporation Apparatus for connecting circuit modules
US20020083359A1 (en) 1999-12-31 2002-06-27 Dow Keith E. Method and apparatus for increasing timing margin under control of processor executable instructions
EP1043662B1 (en) 1999-04-08 2002-07-31 Microchip Technology Inc. Apparatus and method for reconfiguring the pin assignments of one or more functional circuits in a microcontroller
EP1450223A1 (en) 2003-02-24 2004-08-25 Hartmut B. Dr. Brinkhus Universal configurable interface circuit for I/O interfacing to a process
US20050078530A1 (en) 2003-10-10 2005-04-14 Jonghee Han Method and circuit configuration for digitizing a signal in an input buffer of a DRAM device
Appeal Brief dated Jul. 1, 2011 in JP Application No. 2006-551401.
Appeal Brief submitted May 24, 2010 re U.S. Appl. No. 12/177,747. 24 Pages.
Cerisola, M. et al., "CORD-a WDM Optical Network: Control Mechanism Using Subcarrier Multiplexing and Novel Synchronization Solutions," Communications, 1995. ICC 95 Seattle, Gateway to Globalization, 1995 IEEE International Conference on, vol. 1, Jun. 18-22, 1995, pp. 261-265, vol. 1.
Cerisola, M. et al., "CORD—a WDM Optical Network: Control Mechanism Using Subcarrier Multiplexing and Novel Synchronization Solutions," Communications, 1995. ICC 95 Seattle, Gateway to Globalization, 1995 IEEE International Conference on, vol. 1, Jun. 18-22, 1995, pp. 261-265, vol. 1.
English Translation of Claims as amended in JP Voluntary Amendment dated May 26, 2011 re JP Application No. 2011-116969.
EP Extended Search Report dated Feb. 4, 2011 and with EP Search Report completed Jan. 19, 2011, re EP Application No. 10180758.4. 4 Pages.
EP Extended Search Report dated Feb. 7, 2011 and with EP Search Report completed Jan. 19, 2011, re EP Application No. 10180766.7. 4 pages.
EP Official Communication dated Apr. 5, 2011 re Result of Consultation of Mar. 28, 2011 for EP Application No. 05706081.6. 8 pages.
EP Official Communication dated May 20, 2011 re the minutes of the oral proceedings re EP Application No. 05706081.6. 4 Pages.
EP Response dated Apr. 8, 2011 to the Official communications dated Apr. 5, 2011 re EP Application No. 05706081.6. 28 Pages.
EP Response dated Feb. 3, 2011 to the Official Communication dated Jan. 27, 2011 re EP Application No. 05706081.6. 2 Pages.
EP Response dated Mar. 1, 2011 to the Official Communication dated Feb. 23, 2011 re EP Application No. 05706081.6 includes Decision T. 22 Pages.
EP Response dated Mar. 15, 2011 re EP Application No. 05706081.6 to the Official Communication dated Jan. 27, 2011 and Feb. 23, 2011, included highlighted amendments and clear copy. 49 Pages.
EP Response dated Mar. 28, 2011 to the Official Communication dated Jan. 27, 2011 and Feb. 23, 2011 re EP Application No. 05706081.6. 3 Pages.
EP Summons to Attend Oral Proceedings dated Jan. 27, 2011 re EP Application No. 05706081.6. 5 pages.
Examination Report, European Patent Office, European Patent Application No. 05 706 081.6, Nov. 6, 2007.
Final Office Action with mail date of Jan. 21, 2011 re U.S. Appl. No. 12/177,747 includes Information Disclosure Statement. 12 Pages.
Information Disclosure Statement dated Jan. 25, 2011 re U.S. Appl. No. 12/177,747. 4 Pages.
Information Disclosure Statement submitted Nov. 12, 2010 re U.S. Appl. No. 12/177,747. 4 Pages.
Japanese Office Action dated Aug. 16, 2010, Japanese Patent Office, Japanese Patent Application No. 2006-551401 filed Jan. 25, 2005.
JP Office Action dated Jan. 25, 2011 re Decision of Rejection for JP Application No. 2006-551401. 7 Pages.
JP Response to the Office Action dated Dec. 16, 2010, re Japanese Patent Application No. 2006-551401 filed Jan. 25, 2005. 55 Pages.
JP Voluntary Amendment dated May 26, 2011 and Request for Examination re JP Application No. 2011-116969. 48 Pages.
Lewis, Dave, "Easy-to-Use LVDS Serdes for the Serdes Neophyte," National Semiconductor, Jun. 16, 2003, 8 pages.
Non-Final Office Action with mail date of Aug. 3, 2010, in U.S. Appl. No. 12/177,747. 9 pages.
Notice of Allowance and Fee(s) Due dated Apr. 5, 2011 re U.S. Appl. No. 12/177,747 includes Information Disclosure Statement. 13 Pages.
Notice of Appeal dated Mar. 23, 2010 re U.S. Appl. No. 12/177,747. 2 Pages.
Office Action with mail date of Feb. 17, 2010 for U.S. Appl. No. 12/177,747 re Advisory Action. 3 Pages.
Office Action, European Patent Office, application No. 05 706 081.6-2212 filed Jan. 25, 2005, Feb. 13, 2009.
Official Communication dated Feb. 23, 2011 re EP Application No. 05706081.6. 1 page.
Philips Semiconductors, "Data Sheet MB2245 16-bit transceivers with directions pins (3-State), Product specification supersedes data of Aug. 18, 1993," Integrated Circuits, Jan. 16, 1998, 12 pages.
Rambus "Direct Rambus Long Channel Design Guide" (2000), 48 pages.
Rambus "Direct Rambus Short Channel Layout Guide, Version 0.95" (Aug. 2001), 52 pages.
RDRAM® Overview, "High Performance Memory Interface Solution," Copyright 2003 Rambus, Inc., all rights reserved, 8 pages.
Request for Appeal dated May 25, 2011 to the No. 2011-11021 against the Decision of Rejection and Amendment re JP Application No. 2006-551401. 11 Pages.
Response dated Mar. 17, 2011 to the Final Office Action re U.S. Appl. No. 12/177,747. 7 Pages.
Response dated Oct. 29, 2010 to the Office Action Aug. 3, 2010 re U.S. Appl. No. 12/177,747. 10 Pages.
Supplementary European Search report in European Patent Application No. 05706081.6, Apr. 17, 2007 (3 pages).
Texas Instruments SN54LS620 Aug. 1979, Revised 1988, 10 pages.
Widmer, A.X. and Franaszek, P.A., "A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code," IBM J. Res. Develop., vol. 27, No. 5, Sep. 1983, pp. 440-451.
Zerbe, Jared et al., U.S. Appl. No. 09/976,170, filed Oct. 21, 2001, entitled "Method and Apparatus for Evaluating and Optimizing a Signaling System."