Source: https://patents.google.com/patent/US9134370B2/en
Timestamp: 2019-02-23 22:15:43
Document Index: 373733427

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 09170518', 'Application No. 09170518', 'Application No. 2001', 'Application No. 2005']

US9134370B2 - Continuous application and decompression of test patterns and selective compaction of test responses - Google Patents
Continuous application and decompression of test patterns and selective compaction of test responses Download PDF
US9134370B2
US9134370B2 US14/021,800 US201314021800A US9134370B2 US 9134370 B2 US9134370 B2 US 9134370B2 US 201314021800 A US201314021800 A US 201314021800A US 9134370 B2 US9134370 B2 US 9134370B2
US14/021,800
US20140006888A1 (en
1999-11-23 Priority to US16713199P priority Critical
1999-11-23 Priority to US16744599P priority
1999-11-23 Priority to US16713699P priority
1999-11-23 Priority to US16744699P priority
1999-11-23 Priority to US16713799P priority
2000-07-20 Priority to US09/619,988 priority patent/US6557129B1/en
2000-07-20 Priority to US09/620,021 priority patent/US7493540B1/en
2000-07-20 Priority to US09/620,023 priority patent/US6353842B1/en
2000-07-20 Priority to US09/619,985 priority patent/US6327687B1/en
2001-09-04 Priority to US09/947,160 priority patent/US6543020B2/en
2001-09-18 Priority to US09/957,701 priority patent/US6539409B2/en
2003-01-16 Priority to US10/346,699 priority patent/US6708192B2/en
2003-01-29 Priority to US10/354,576 priority patent/US6829740B2/en
2003-01-29 Priority to US10/354,633 priority patent/US7478296B2/en
2003-01-31 Priority to US10/355,941 priority patent/US7111209B2/en
2004-02-17 Priority to US10/781,031 priority patent/US7260591B2/en
2004-10-25 Priority to US10/973,522 priority patent/US7500163B2/en
2006-09-18 Priority to US11/523,111 priority patent/US7509546B2/en
2007-08-20 Priority to US11/894,393 priority patent/US8024387B2/en
2009-01-13 Priority to US12/352,994 priority patent/US7877656B2/en
2009-03-02 Priority to US12/396,377 priority patent/US7805649B2/en
2009-03-17 Priority to US12/405,409 priority patent/US7900104B2/en
2010-09-27 Priority to US12/891,498 priority patent/US8108743B2/en
2011-01-03 Priority to US12/983,815 priority patent/US20110167309A1/en
2011-01-25 Priority to US13/013,712 priority patent/US8533547B2/en
2013-09-09 Priority to US14/021,800 priority patent/US9134370B2/en
2013-09-09 Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
2014-01-02 Publication of US20140006888A1 publication Critical patent/US20140006888A1/en
2015-09-15 Publication of US9134370B2 publication Critical patent/US9134370B2/en
2015-10-02 Assigned to MENTOR GRAPHICS CORPORATION reassignment MENTOR GRAPHICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KASSAB, MARK, MUKHERJEE, NILANJAN, RAJSKI, JANUSZ, TYSZER, JERZY
A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
This application is a divisional of U.S. patent application Ser. No. 13/013,712, filed on
Jan. 25, 2011, which is a continuation-in-part of U.S. patent application Ser. No. 12/891,498, filed on Sep. 27, 2010, now U.S. Pat. No. 8,108,743, which is a continuation of U.S. patent application Ser. No. 12/396,377, filed Mar. 2, 2009, now U.S. Pat. No. 7,805,649, which is a continuation of U.S. patent application Ser. No. 10/973,522, filed Oct. 25, 2004, now U.S. Pat. No. 7,500,163, which is a continuation of U.S. patent application Ser. No. 10/354,576, filed Jan. 29, 2003, now U.S. Pat. No. 6,829,740, which is a continuation of U.S. patent application Ser. No. 09/619,988, filed Jul. 20, 2000, now U.S. Pat. No. 6,557,129, which claims the benefit of U.S. Provisional Application No. 60/167,136, filed Nov. 23, 1999, all of which are hereby incorporated herein by reference.
This application is also a divisional of U.S. patent application Ser. No. 13/013,712, filed on Jan. 25, 2011, which is continuation-in-part of U.S. patent application Ser. No. 12/352,994, filed Jan. 13, 2009, now U.S. Pat. No. 7,877,656, which is a continuation of U.S. patent application Ser. No. 10/354,633, filed Jan. 29, 2003, now U.S. Pat. No. 7,478,296, which is a continuation of U.S. patent application Ser. No. 09/620,021, filed Jul. 20, 2000, now U.S. Pat. No. 7,493,540, which claims the benefit of U.S. Provisional Application No. 60/167,131, filed Nov. 23, 1999, all of which are hereby incorporated herein by reference.
This application is also a divisional of U.S. patent application Ser. No. 13/013,712, filed on Jan. 25, 2011, which is a continuation-in-part of U.S. patent application Ser. No. 12/983,815, filed on Jan. 3, 2011, which is a continuation of U.S. patent application Ser. No. 12/402,880, filed Mar. 12, 2009, now U.S. Pat. No. 7,865,794, which is a continuation of U.S. patent application Ser. No. 11/502,655, filed Aug. 11, 2006, now U.S. Pat. No. 7,506,232, which is a continuation of U.S. patent application Ser. No. 10/736,966, filed Dec. 15, 2003, now U.S. Pat. No. 7,093,175, which is a continuation of U.S. patent application Ser. No. 09/713,664, filed Nov. 15, 2000, now U.S. Pat. No. 6,684,358, which claims the benefit of U.S. Provisional Application No. 60/167,137, filed Nov. 23, 1999, all of which are hereby incorporated herein by reference.
This application is also a divisional of U.S. patent application Ser. No. 13/013,712, filed on Jan. 25, 2011, which is a continuation-in-part of U.S. patent application Ser. No. 11/894,393, filed on Aug. 20, 2007, now U.S. Pat. No. 8,024,387, which is a continuation of U.S. patent application Ser. No. 10/781,031, filed Feb. 17, 2004, now U.S. Pat. No. 7,260,591, which is a continuation U.S. patent application Ser. No. 10/346,699, filed Jan. 16, 2003, now U.S. Pat. No. 6,708,192, which is a continuation of U.S. patent application Ser. No. 09/957,701, filed Sep. 18, 2001, now U.S. Pat. No. 6,539,409, which is a continuation of U.S. patent application Ser. No. 09/620,023, filed, Jul. 20, 2000, now U.S. Pat. No. 6,353,842, which claims the benefit of U.S. Provisional Application No. 60/167,445, filed Nov. 23, 1999, all of which are hereby incorporated herein by reference.
This application is also a divisional of U.S. patent application Ser. No. 13/013,712, filed on Jan. 25, 2011, which is continuation-in-part of U.S. patent application Ser. No. 12/405,409, filed on Mar. 17, 2009, now U.S. Pat. No. 7,900,104, which is a continuation of 11/523,111 filed Sep. 18, 2006, now U.S. Pat. No. 7,509,546, which is a continuation of U.S. patent application Ser. No. 10/355,941 filed Jan. 31, 2003, now U.S. Pat. No. 7,111,209, which is a continuation of U.S. patent application Ser. No. 09/947,160 filed Sep. 4, 2001, now U.S. Pat. No. 6,543,020, which is a continuation of U.S. patent application Ser. No. 09/619,985 filed Jul. 20, 2000, now U.S. Pat. No. 6,327,687, which claims the benefit of U.S. Provisional Application No. 60/167,446 filed Nov. 23, 1999, all of which are hereby incorporated herein by reference.
This invention relates generally to testing of integrated circuits and, more particularly, to the generation and application of test data in the form of patterns, or vectors, to scan chains within a circuit-under-test. This invention also relates generally to testing of integrated circuits and more particularly relates to compaction of test responses used in testing for faults in integrated circuits.
These limitations of time and storage can be overcome to some extent by adopting a built-in self-test (BIST) framework, as shown in the U.S. Pat. No. 4,503,537 and FIG. 13. In BIST, additional on-chip circuitry is included to generate test patterns, evaluate test responses, and control the test. For example, a pseudo-random pattern generator 121 is used to generate the test patterns, instead of having deterministic test patterns. Additionally, a multiple input signature register (MISR) 122 is used to generate and store a resulting signature from test responses. In conventional logic BIST, where pseudo-random patterns are used as test patterns, 95-96% coverage of stuck-at faults can be achieved provided that test points are employed to address random-pattern resistant faults. On average, one to two test points may be required for every 1000 gates. In BIST, all responses propagating to observable outputs and the signature register have to be known. Unknown values corrupt the signature and therefore must be bounded by additional test logic. Even though pseudo-random test patterns appear to cover a significant percentage of stuck-at faults, these patterns must be supplemented by deterministic patterns that target the remaining, random pattern resistant faults. Very often the tester memory required to store the supplemental patterns in BIST exceeds 50% of the memory required in the deterministic approach described above. Another limitation of BIST is that other types of faults, such as transition or path delay faults, are not handled efficiently by pseudo-random patterns. Because of the complexity of the circuits and the limitations inherent in BIST, it is extremely difficult, if not impossible, to provide a set of specified test patterns that fully covers hard-to-test faults.
Further, some of the DFT techniques include compactors to compress the test responses from the scan chains. There are generally two types of compactors: time compactors and spatial compactors. Time compactors typically have a feedback structure with memory elements for storing a signature, which represents the results of the test. After the signature is completed it is read and compared to a fault-free signature to determine if an error exists in the integrated circuit. Spatial compactors generally compress a collection of bits (called a vector) from scan chains. The compacted output is analyzed in real time as the test responses are shifted out of the scan chains. Spatial compactors can be customized for a given circuit under test to reduce the aliasing phenomenon, as shown in the U.S. Pat. No. 5,790,562 and in few other works based on multiplexed parity trees or nonlinear trees comprising elementary gates such as AND, OR, NAND, and NOR gates.
Undoubtedly, the most popular time compactors used in practice are linear feedback shift registers (LFSRs). In its basic form, the LFSR (see FIG. 14) is modified to accept an external input in order to act as a polynomial divider. An alternative implementation (called type II LFSR) is shown in FIG. 15. The input sequence, represented by a polynomial, is divided by the characteristic polynomial of the LFSR. As the division proceeds, the quotient sequence appears at the output of the LFSR and the remainder is kept in the LFSR. Once testing is completed, the content of the LFSR can be treated as a signature.
FIG. 16 shows another time compactor (which is a natural extension of the LFSR-based compactor) called a multiple-input LFSR, also known as a multiple-input signature register (MISR). The MISR is used to test circuits in the multiple scan chain environment such as shown in the U.S. Pat. No. 4,503,537. MISRs feature a number of XOR gates added to the flip-flops. The CUT scan chain outputs are then connected to these gates.
FIG. 17 shows an example of a pipelined spatial compactor with a bank of flip-flops separating stages of XOR gates. A clock (not shown) controls the flip-flops and allows a one-cycle delay before reading the compacted output.
The limitation of spatial compactors, such as the one shown in FIG. 17, is that unknown states can reduce fault coverage. Time compactors, such as shown in FIGS. 14, 15, and 16, are completely unable to handle unknown states since an unknown state on any input can corrupt the compressed output generated by the compactor. With both time compactors and spatial compactors, multiple fault effects can reduce fault coverage. Additionally, if a fault effect is detected within the integrated circuit, these compactors have limited ability to localize the fault.
In another embodiment, a compactor is disclosed that selects test responses in one or more scan chains to compact into a compressed output, while one or more other test responses are masked. Thus, test responses containing unknown states may be masked to ensure that the compactor generates a valid compressed output. Additionally, test responses can be masked to ensure fault masking does not occur. The compactor can also analyze test responses from individual scan chains to diagnostically localize faults in an integrated circuit.
In yet another embodiment, a control register is used that individually identifies each scan chain included in compaction. In this embodiment, a variable number (e.g., 1, 2, 3, 4 . . .) of test responses within scan chains may be included in compaction. Alternatively, the control register may store a unique identifier that is decoded to select one test response that is compacted.
FIG. 7 shows the logical expressions for the bits stored in each scan cell in the scan chain of FIG. 5
FIG. 13 is a block diagram of a prior art system using a built-in-test system.
FIG. 14 is a circuit diagram of a prior art type I LFSR compactor.
FIG. 15 is a circuit diagram of a prior art type II LFSR compactor.
FIG. 16 is a circuit diagram of a prior art architecture of a multiple input signature register (MISR) compactor shown receiving input from scan chains.
FIG. 17 is a circuit diagram of a prior art pipelined spatial compactor.
FIG. 18 is a block diagram of a selective compactor according to the invention.
FIG. 19 shows one embodiment of a selective compactor, including selection circuitry and a spatial compactor, for masking test responses from scan chains.
FIG. 20 is another embodiment of a selective compactor including selection circuitry and a time compactor for masking test responses from scan chains.
FIG. 21 is yet another embodiment of a selective compactor including selection circuitry and a cascaded compactor for masking individual bits of test responses from scan chains.
FIG. 22 is another embodiment of a selective compactor including selection circuitry and multiple compactors for masking test responses.
FIG. 23 is another embodiment of a selective compactor with selection circuitry that masks any variable number of test responses from the scan chains.
FIG. 24 is another embodiment of a selective compactor with programmable selection of scan chains.
FIG. 25 is a flowchart of a method for selectively compacting test responses from scan chains.
Continuous Application and Decompression of Test Patterns to a Circuit-Under-Test FIG. 2 is a block diagram of a system 30 according to the invention for testing digital circuits with scan chains. The system includes a tester 21 such as external automatic testing equipment (ATE) and a circuit 34 that includes as all or part of it a circuit-under-test (CUT) 24. The tester 21 provides from storage a set of compressed test patterns 32 of bits, one pattern at a time, through tester channels 40 to the circuit 34 such as an IC. A compressed pattern, as will be described, contains far fewer bits than a conventional uncompressed test pattern. A compressed pattern need contain only enough information to recreate deterministically specified bits. Consequently, a compressed pattern is typically 2% to 5% of the size of a conventional test pattern and requires much less tester memory for storage than conventional patterns. As importantly, compressed test patterns require much less time to transmit from a tester to a CUT 24.
where Ci is the ith output channel and sk indicates the kth stage of the LFSR. Assume that the LFSR is fed every clock cycle through its two input channels 37 a, 37 b and input injectors 48 a, 48 b (XOR gates) to the second and the sixth stages of the register. The input variables “a” (compressed test pattern bits) received on channel 37 a are labeled with even subscripts (a0, a2, a4, . . . ) and the variables “a” received on channel 37 b are labeled with odd subscripts (a1, a3, a5, . . . ). Treating these external variables as Boolean, all scan cells can be conceptually filled with symbolic expressions being linear functions of input variables injected by tester 21 into the LFSR 52. Given the feedback polynomial, the phase shifter 50, the location of injectors 48 a,b as well as an additional initial period of four clock cycles during which only the LFSR is supplied by test data, the contents of each scan cell within the scan chains 26 in FIG. 6 can be logically determined. FIG. 7 gives the expressions for the 64 scan cells in FIG. 6, with the scan chains numbered 0 through 7 in FIG. 6 corresponding to the scan chains C7, C1, C6, . . . identified in FIG. 6. The expressions for each scan chain in FIG. 7 are listed in the order in which the information is shifted into the chain, i.e., the topmost expression represents the data shifted in first.
As can be observed, the achieved compression ratio (defined as the number of scan cells divided by the number of compressed pattern bits) is 64/(2×8+2×4)≈2.66. The fully specified test pattern is then compressed into a compressed pattern of bits using any of a number of known methods.
FIGS. 8A-D illustrate various embodiments for the LFSM 46 of FIG. 5. FIG. 8A is a Type I LFSR 60. FIG. 8B is a Type II LFSR 62. FIG. 8C is a transformed LFSR 64. And FIG. 8D is a cellular automaton 66. All of them implement primitive polynomials. Except for the cellular automaton 66, in each case the LFSM includes a number of memory elements connected in a shift register configuration. In addition, there are several feedback connections between various memory cells that uniquely determine the next state of the LFSM. The feedback connections are assimilated into the design by introducing injectors in the form of XOR gates near the destination memory elements. The input channels 37 provide the bits of a compressed pattern to the LFSM through input injectors 48 a,b. The injectors are handled similarly as the other feedback connections within the LFSM except that their sources of bits are the input channels. The input channels 37 may have multiple fan-outs driving different LFSM injectors 48 to improve the encoding efficiency.
Selectively Compacting Test Responses
FIG. 18 shows a block diagram of an integrated circuit 124 that includes multiple scan chains 126 in a circuit under test 128. A selective compactor 130 is coupled to the scan chains 126 and includes a selector circuit 132 and a compactor 136. The illustrated system is a deterministic test environment because the scan chains 126 are loaded with predetermined test patterns from an ATE (not shown). The test patterns are applied to the core logic of the integrated circuit to generate test responses, which are also stored in the scan chains 126 (each scan chain contains a test response). The test responses contain information associated with faults in the core logic of the integrated circuit 124. Unfortunately, the test responses may also contain unknown states and/or multiple fault effects, which can negatively impact the effective coverage of the test responses. For example, if a memory cell is not initialized, it may propagate an unknown state to the test response. The test responses are passed to the selector circuit 132 of the selective compactor 130. The selector circuit 132 includes control logic 134 that controls which of the test responses are passed through the selector circuit to the compactor 136. The control logic 134 can control the selector circuit 132 such that test responses with unknown states or multiple fault effects are masked. The control logic is controlled by one or more control lines. Although not shown, the control lines may be connected directly to a channel of an ATE or they may be connected to other logic within the integrated circuit. For example, the control lines may be coupled to a Linear Finite State Machine (e.g., LSFR type 1, LSFR type 2, cellular automata, etc.) in combination with a phase shifter. The compactor 136 receives the desired test responses from the selector circuit 132 and compacts the responses into a compressed output for analysis. The compressed output is compared against a desired output to determine if the circuit under test contains any faults. The selection circuitry, compactor, and circuit under test are all shown within a single integrated circuit. However, the selection circuitry and compactor may be located externally of the integrated circuit, such as within the ATE.
FIG. 19 shows one example of an integrated circuit 140 that includes a selective compactor 142 coupled to multiple scan chains 144 within a circuit under test. Although only 8 scan chains are shown, the test circuit 140 may contain any number of scan chains. The selective compactor 142 includes a selector circuit 146 and a compactor 148. The compactor 148 is a linear spatial compactor, but any conventional parallel test-response compaction scheme can be used with the selector circuit 146, as further described below. The selector circuit 146 includes control logic 150, which includes an input register 152, shown in this example as a shift register. The input register 152 has a clock input 154 and a data input 156. Each cycle of a clock on the clock input 154, data from data input 156 shifts into the input register 152. The register 152 has multiple fields including a scan identification field 158, a “one/not one” field 160 and a “not all/all” field 162. A control register 164 has corresponding bit positions to input register 152, and upon receiving an update signal on an update line 166, the control register 164 loads each bit position from input register 152 in parallel. Thus, the control register 164 also contains fields 158, 160, and 162. Although the control register 164 is shown generically as a shift register, the update line 166 is actually a control line to a multiplexer (not shown) that allows each bit position in register 164 to reload its own data on each clock cycle when the update line deactivated. When the update line is activated, the multiplexer passes the contents of register 152 to corresponding bit positions of the control register 164. The control register 164 is then loaded synchronously with the clock.
The selector circuit 146 includes logic gates, shown generally at 168, coupled to the control register 164. The logic gates 168 are responsive to the different fields 158, 160, 162 of the control register 164. For example, the scan identification field 158 contains a sufficient number of bits to uniquely identify any of the scan chains 144. The scan identification field 158 of the control register 164 is connected to a decoder, shown at 170 as a series of AND gates and inverters. The decoder 170 provides a logic one on a decoder output depending on the scan identification field, while the other outputs of the decoder are a logic zero.
The one/not one field 160 of the control register 164 is used to either pass only one test response associated with the scan chain identified in the scan identification field 158 or pass all of the test responses except for the scan chain identified in the scan identification field. The all/not all field 162 is effectively an override of the other fields. In particular, field 162 controls whether all of the test responses in the scan chains 144 are passed to the compactor 148 or only the test responses as controlled by the scan identification field 158 and the one/not one field 160. With field 162 cleared, only test responses as controlled by the scan identification field 158 and field 160 pass to the compactor 148. Conversely, if the field 162 is set to a logic one, then all of the test responses from all of the scan chains 144 pass to the compactor 148 regardless of the scan identification field 58 and the one/not one field 160.
FIG. 20 shows another embodiment of a selective compactor 180 that is coupled to scan chains 182. The selective compactor includes a selector circuit 184, which is identical to the selector circuit 146 described in relation to FIG. 19. The selective compactor 180 also includes a time compactor 184, which is well understood in the art to be a circular compactor. The time compactor includes multiple flip-flops 186 and XOR gates 188 coupled in series. A reset line 190 is coupled to the flip-flops 186 to reset the compactor 184. The reset line may be reset multiple times while reading the scan chains. Output register 192 provides a valid output of the compactor 84 upon activation of a read line 194.
Referring to both FIGS. 19 and 20, in operation the scan chains 182 are serially loaded with predetermined test patterns by shifting data on scan channels (not shown) from an ATE (not shown). Simultaneously, the input register 152 is loaded with a scan identification and the controlling flags in fields 160, 162. The test patterns in the scan chains 144, 182 are applied to the circuit under test and test responses are stored in the scan chains. Prior to shifting the test responses out of the scan chains, the update line 166 is activated, thus moving fields 158, 160, 162 to the control register 164. The control register thereby controls the logic gates 168 to select the test responses that are passed to the compactors 148, 184. If the field 162 is in a state such that selection is not overridden, then certain of the test responses are masked. In the example of FIG. 19, the spatial compactor 148 provides the corresponding compressed output serially and simultaneously with shifting the test responses out of the scan chains. Conversely, in FIG. 20 the selective compactor 180 does not provide the appropriate compressed output until the read line 194 is activated. The selective compactor 180 provides a parallel compressed output as opposed to serial. The selective compactor 180 may be read multiple times (e.g., every eighth clock cycle) while reading out the test responses.
FIG. 21 shows another embodiment of a selective compactor 200. Again, the selective compactor includes a selector circuit 202 and a compactor 204. The compactor 204 is a type of spatial compactor called a cascaded compactor. N scan chains 206 include M scan cells 208, each of which stores one bit of the test response. The selector circuit 202 includes logic gates 210, in this case shown as AND gates, coupled to a control line 212. The compactor 204 is a time compactor with a single serial output 214. The control line 212 is used to mask the test responses. In particular, the control line 212 either masks all corresponding scan cells in the scan chains or allows all of the scan cells to pass to the compactor 180. The control line 212 operates to mask each column of scan cells, rather than masking an entire scan chain. Thus, individual bits from any scan chain can be masked on a per clock-cycle basis and the remaining bits of that scan chain applied to the compactor 204. With control line 212 activated, all bits from the scan chains pass to the compactor. With control line 212 deactivated, all bits from the scan chains are masked. Although FIG. 21 shows only a single control line, additional control lines can be used to mask different groups of scan chains. Additionally, although control line 212 is shown as active high, it may be configured as active low.
FIG. 22 shows yet another embodiment of the selective compactor 220. Automated test equipment 222 provides test patterns to the scan chains 224. The scan chains 224 are a part of the circuit under test 226. The patterns that are loaded into the scan chains 224 by the ATE are used to detect faults in the core logic of the circuit 226. The test responses are stored in the scan chains 224 and are clocked in serial fashion to the selective compactor 220. The selective compactor includes a selector circuit 228 and a compactor 230. The selector circuit 228 includes control logic including an input register 232, multiple control registers 234, 236, and multiple decoders 237 and 239. The register 232 is loaded with a pattern of bits that are moved to the control registers 234, 236 upon activation of an update line (not shown). The control registers 234, 236 are read by the decoders 237 and 239 and decoded to select one or more logic gates 238. A flag 240 is used to override the decoders 237 and 239 and pass all of the test responses to the compactor 230. Although only a single flag 240 is shown, multiple flags may be used to separately control the decoders. In this example, the compactor 230 includes multiple spatial compactors, such as compactors 242 and 244. Each control register may be loaded with different data so that the compactors 242, 244 can be controlled independently of each other.
FIG. 23 shows yet another embodiment of the present invention with a selective compactor 250. Control logic 252 variably controls which test responses are masked and which test responses are compacted. Thus, activating the corresponding bit position in the control logic 252 activates the corresponding logic gate associated with that bit and allows the test response to pass to the compactor. Conversely, any bit that is not activated masks the corresponding test response.
FIG. 24 shows another embodiment of a selective compactor 256 including a selector circuit 258 and compactor 260. In this case, an input shift register 262 having a bit position corresponding to each scan chain 264 is used to selectively mask the scan chains. A clock is applied to line 266 to serially move data applied on data line 268 into the shift register 262. At the appropriate time, an update line 265 is activated to move the data from the shift register to a control register 269. Each bit position that is activated in the control register 269 allows a test response from the scan chains 264 to pass to the compactor. All other test responses are masked. Thus, the selective compactor can mask any variable number of test responses.
FIG. 25 shows a flowchart of a method for selectively compacting test responses. In process block 270, an ATE loads predetermined test patterns into scan chains within an integrated circuit. This loading is typically accomplished by shifting the test patterns serially into the scan chains. The test patterns are applied to the circuit under test (process block 272) and the test responses are stored in the scan chains (process block 274). In process block 276, the selector circuit controls which test responses are masked. In particular, the selector circuit controls which scan chains are masked or which bits in the scan chains are masked. For example, in FIG. 19, the selector circuit masks the entire scan chain that is identified in the scan identification field 158. In FIG. 21, only individual bits of a scan chain are masked. In any event, in process block 276, the selector circuit typically masks unknown data or multiple fault effects so that the desired fault effect can propagate to the output (in some modes of operation, all of the test responses may pass to the output). In the event that the selector circuit includes a control register, the control register may be loaded concurrently with loading the test patterns in the scan chains or it can be loaded prior to reading the test responses. In process block 278, the test responses (one or more of which have been masked) are passed to the compactor and the compactor generates a compressed output associated with the test responses. In process block 280, the compressed output generated by the compactor is compared to an ideal response. If they match, the integrated circuit is assumed to be fault free.
a parallel-in serial-out register; and
a decompressor comprising a phase shifter and a linear feedback shift register (LFSR), the LFSR being coupled between an output of the register and an input of the phase shifter,
the parallel-in serial-out register being configured to load compressed test pattern bits in parallel and apply the compressed test pattern bits serially to the LFSR of the decompressor, and
the decompressor being configured to decompress the compressed test pattern bits into decompressed test pattern bits.
2. The circuit of claim 1, wherein the parallel-in-serial-out register is coupled to automatic testing equipment (ATE) located externally to the circuit.
3. The circuit of claim 1, further including scan chains coupled to the phase shifter.
4. The circuit of claim 1, wherein the phase shifter is formed from only XOR gates.
5. The circuit of claim 1, wherein the parallel-in serial-out register is coupled to automatic testing equipment (ATE) located externally to the circuit, the parallel-in serial-out register being configured to load the compressed test pattern from the ATE and output the compressed test pattern to the LFSR.
6. The apparatus of claim 1, wherein the parallel-in serial-out register is a shift register.
7. The apparatus of claim 1, wherein the parallel-in serial-out register is configured to apply the compressed test pattern bits serially to an XOR gate of the LFSR that is interposed between two respective memory elements of the LFSR.
8. The apparatus of claim1, wherein the parallel-in serial-out register is clocked such that its contents are shifted out before a next set of compressed test pattern bits is applied to the parallel-in serial-out register.
9. The apparatus of claim 1, wherein the parallel-in serial-out register is a first parallel-in serial-out register, the apparatus further comprising a second parallel-in serial-out register that is also configured to load respective compressed test pattern bits in parallel and apply the respective compressed test pattern bits serially to the LFSR of the decompressor.
US14/021,800 1999-11-23 2013-09-09 Continuous application and decompression of test patterns and selective compaction of test responses Active US9134370B2 (en)
US16744599P true 1999-11-23 1999-11-23
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US09/619,988 US6557129B1 (en) 1999-11-23 2000-07-20 Method and apparatus for selectively compacting test responses
US09/620,021 US7493540B1 (en) 1999-11-23 2000-07-20 Continuous application and decompression of test patterns to a circuit-under-test
US09/620,023 US6353842B1 (en) 1999-11-23 2000-07-20 Method for synthesizing linear finite state machines
US09/619,985 US6327687B1 (en) 1999-11-23 2000-07-20 Test pattern compression for an integrated circuit test environment
US09/947,160 US6543020B2 (en) 1999-11-23 2001-09-04 Test pattern compression for an integrated circuit test environment
US09/957,701 US6539409B2 (en) 1999-11-23 2001-09-18 Method for synthesizing linear finite state machines
US10/346,699 US6708192B2 (en) 1999-11-23 2003-01-16 Method for synthesizing linear finite state machines
US10/354,633 US7478296B2 (en) 1999-11-23 2003-01-29 Continuous application and decompression of test patterns to a circuit-under-test
US10/354,576 US6829740B2 (en) 1999-11-23 2003-01-29 Method and apparatus for selectively compacting test responses
US10/355,941 US7111209B2 (en) 1999-11-23 2003-01-31 Test pattern compression for an integrated circuit test environment
US10/781,031 US7260591B2 (en) 1999-11-23 2004-02-17 Method for synthesizing linear finite state machines
US10/973,522 US7500163B2 (en) 1999-11-23 2004-10-25 Method and apparatus for selectively compacting test responses
US11/523,111 US7509546B2 (en) 1999-11-23 2006-09-18 Test pattern compression for an integrated circuit test environment
US11/894,393 US8024387B2 (en) 1999-11-23 2007-08-20 Method for synthesizing linear finite state machines
US12/352,994 US7877656B2 (en) 1999-11-23 2009-01-13 Continuous application and decompression of test patterns to a circuit-under-test
US12/396,377 US7805649B2 (en) 1999-11-23 2009-03-02 Method and apparatus for selectively compacting test responses
US12/405,409 US7900104B2 (en) 1999-11-23 2009-03-17 Test pattern compression for an integrated circuit test environment
US12/891,498 US8108743B2 (en) 1999-11-23 2010-09-27 Method and apparatus for selectively compacting test responses
US15/608,716 US20180017622A1 (en) 1999-11-23 2017-05-30 Continuous application and decompression of test patterns and selective compaction of test responses
US13/013,712 Division US8533547B2 (en) 1999-11-23 2011-01-25 Continuous application and decompression of test patterns and selective compaction of test responses
US09/620,023 Continuation US6353842B1 (en) 1999-11-23 2000-07-20 Method for synthesizing linear finite state machines
US09/619,988 Continuation US6557129B1 (en) 1999-11-23 2000-07-20 Method and apparatus for selectively compacting test responses
US09/620,021 Continuation US7493540B1 (en) 1999-11-23 2000-07-20 Continuous application and decompression of test patterns to a circuit-under-test
US09/713,664 Continuation US6684358B1 (en) 1999-11-23 2000-11-15 Decompressor/PRPG for applying pseudo-random and deterministic test patterns
US09/957,701 Continuation US6539409B2 (en) 1999-11-23 2001-09-18 Method for synthesizing linear finite state machines
US10/354,576 Continuation US6829740B2 (en) 1999-11-23 2003-01-29 Method and apparatus for selectively compacting test responses
US10/354,633 Continuation US7478296B2 (en) 1999-11-23 2003-01-29 Continuous application and decompression of test patterns to a circuit-under-test
US10/736,966 Continuation US7093175B2 (en) 1999-11-23 2003-12-15 Decompressor/PRPG for applying pseudo-random and deterministic test patterns
US14/853,412 Continuation US9664739B2 (en) 1999-11-23 2015-09-14 Continuous application and decompression of test patterns and selective compaction of test responses
US20140006888A1 US20140006888A1 (en) 2014-01-02
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US14/021,800 Active US9134370B2 (en) 1999-11-23 2013-09-09 Continuous application and decompression of test patterns and selective compaction of test responses
US (1) US9134370B2 (en)
JPS63286780A (en) 1987-05-20 1988-11-24 Hitachi Ltd Fault detecting system and fault detecting device
JPH032579B2 (en) 1981-04-30 1991-01-16 Concast Ag
JPH0312573B2 (en) 1984-07-19 1991-02-20 Toyoda Gosei Kk
JPH04236378A (en) 1990-09-15 1992-08-25 Internatl Business Mach Corp <Ibm> Method and device for testing logic device
JPH05249197A (en) 1992-03-05 1993-09-28 Nippon Telegr & Teleph Corp <Ntt> Incorporated self-test circuit
JPH07174822A (en) 1993-12-21 1995-07-14 Kawasaki Steel Corp Semiconductor integrated circuit device
JPH07198791A (en) 1993-12-28 1995-08-01 Nippon Telegr & Teleph Corp <Ntt> Shared testing register and incorporated self-testing circuit using the same
JPH0815382B2 (en) 1987-06-18 1996-02-14 三菱電機株式会社 Magnet generator
JPH09130378A (en) 1995-09-15 1997-05-16 Thomson Multimedia Sa Method for ensuring data by secure data exchange protocol
US5663966A (en) 1996-07-24 1997-09-02 International Business Machines Corporation System and method for minimizing simultaneous switching during scan-based testing
JPH116852A (en) 1997-05-22 1999-01-12 Hewlett Packard Co <Hp> Test data impressing circuit
JPH11153655A (en) 1997-08-26 1999-06-08 Samsung Electron Co Ltd Ic chip inspection device using compressed digital test data and ic chip inspection method using the device
US5945875A (en) * 1997-03-26 1999-08-31 Yozan Inc. π/n shift phase-shift keying demodulator
JPH11264860A (en) 1998-03-17 1999-09-28 Nec Corp Output circuit of semiconductor device with test mode
WO2001038981A1 (en) 1999-11-23 2001-05-31 Mentor Graphics Corporation Test pattern compression for an integrated circuit test environment
WO2001038891A1 (en) 1999-11-23 2001-05-31 Mentor Graphics Corporation Phase shifter with reduced linear dependency
WO2001038955A1 (en) 1999-11-23 2001-05-31 Mentor Graphics Corporation Method for synthesizing linear finite state machines
WO2001038890A1 (en) 1999-11-23 2001-05-31 Mentor Graphics Corporation Decompressor/prpg for applying pseudo-random and deterministic test patterns
WO2001039254A3 (en) 1999-11-23 2001-12-13 Mentor Graphics Corp Continuous application and decompression of test patterns to a circuit-under-test
JP2003526778T5 (en) 2005-04-14
2013-09-09 US US14/021,800 patent/US9134370B2/en active Active
JP2006078493A5 (en) 2006-06-15
JP2004500558A (en) 1999-11-23 2004-01-08 メンター・グラフィクス・コーポレーション Method and apparatus for selectively compressing test responses
JP3845016B2 (en) 1999-11-23 2006-11-15 メンター・グラフィクス・コーポレーション Successive applications and decompression of test patterns to the circuit art under test
European Communication dated Apr. 23, 2007, from European Application No. EP 00 99 1744.
European Communication dated Feb. 13, 2006, from European Application No. EP 00 99 1744.
European Communication dated Mar. 14, 2008, from European Application No. EP 00 99 1744.
European Communication dated Mar. 17, 2005, from European Application No. EP 00 99 1744.
European Communication pursuant to Article 94(3) EPC dated Jul. 1, 2010, including the European Search Report, from European Patent Application No. 09170518.6, 8pp.
European Communication pursuant to Article 94(3) EPC dated Jun. 6, 2012, from European Patent Application No. 09170518.6, 5 pp.
European Search Report dated Nov. 15, 2004, from European Application No. EP 00 99 1744.
Hellebrand et al., "Built-in Test for Circuits With Scan Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers,"IEEE Trans. on Computers, vol. C-44, pp. 223-233 (Feb. 1995).
International Preliminary Examination Report dated Feb. 10, 2003, from International Application No. PCT/US00/42211.
International Preliminary Examination Report from International Application No. PCT/US00/31376.
International Search Report dated May 31, 2001, from International Application No. PCT/US00/42211.
International Search Report from International Application No. PCT/US00/31376.
Japanese Notice of Rejection dated Mar. 24, 2005, including an English-language translation, from Japanese Patent Application No. 2001-540825.
Japanese Official Action dated Jan. 27, 2009, including an English-language translation, from Japanese Patent Application No. 2005-284623.
Rajski, J.; Tyszer, J.; Zacharia, N., "Test data decompression for multiple scan designs with boundary scan," Computers, IEEE Transactions on , vol. 47, No. 11, pp. 1188,1200, Nov. 1998. *
Written Opinion dated Jun. 26, 2002, from International Application No. PCT/US00/42211.
Written Opinion from International Application No. PCT/US00/31376.
US20140006888A1 (en) 2014-01-02
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