Source: http://www.google.com/patents/US20040170224?dq=5920316
Timestamp: 2018-01-22 01:07:21
Document Index: 356116200

Matched Legal Cases: ['art.\n5', 'art 223', 'art 223', 'art 223', 'art 223', 'art 42', 'art 42', 'art 42', 'art 51']

Patent US20040170224 - Communication system and communication device - Google Patents
A communication system for transmitting a transmission signal in digital form from a transmitter to a receiver is disclosed. The transmitter includes a modulation part modulating a carrier wave in accordance with the transmission signal according to frequency modulation, a digital conversion part performing...http://www.google.com/patents/US20040170224?utm_source=gb-gplus-sharePatent US20040170224 - Communication system and communication device
Publication number US20040170224 A1
Application number US 10/779,415
Also published as US7359456
Publication number 10779415, 779415, US 2004/0170224 A1, US 2004/170224 A1, US 20040170224 A1, US 20040170224A1, US 2004170224 A1, US 2004170224A1, US-A1-20040170224, US-A1-2004170224, US2004/0170224A1, US2004/170224A1, US20040170224 A1, US20040170224A1, US2004170224 A1, US2004170224A1
Original Assignee Toshikazu Ogino
US 20040170224 A1
a transmission part transmitting digital data into which the modulated signal is converted in the digital conversion part; and
a demodulation part demodulating the digital data received by the reception part according to the frequency modulation.
the transmitter further comprises an identification information insertion part inserting identification information into the transmission signal; and
a transmission part transmitting digital data into which the modulated signal is converted in the digital conversion part.
5. The communication device as claimed in claim 4, wherein the transmitted digital data is received by a receiver; and
the identification information is preset in the receiver.
6. A communication device for receiving transmitted digital data, the digital data being obtained by modulating a carrier wave in accordance with a transmission signal according to frequency modulation and performing 1-bit quantization on a modulated signal obtained as a result of the modulation, the communication device comprising:
a reception part receiving the transmitted digital data; and
a demodulation part demodulating the digital data received by the reception part according to the frequency modulation, and restoring the transmission signal.
7. The communication device as claimed in claim 6, further comprising:
an identification information extraction part extracting identification information from a demodulated signal obtained as a result of the demodulation in the demodulation part; and
8. The communication device as claimed in claim 7, wherein the digital data is transmitted from a transmitter; and
the identification information is pre-inserted in the transmission signal in the transmitter.
[0015]FIG. 1 is a schematic diagram showing a video transmission system according to an embodiment of the present invention;
[0016]FIG. 2 is a block diagram showing a signal processing circuit of a transmitter according to the embodiment of the present invention;
[0017]FIG. 3 is a wave form diagram for illustrating the operation of an ID insertion part of the signal processing circuit according to the embodiment of the present invention;
[0018]FIG. 4 is a diagram showing the frequency layout of the output signal of a mixer of the signal processing circuit according to the embodiment of the present invention;
[0019]FIG. 5 is a block diagram showing an A/D conversion part of the transmitter according to the embodiment of the present invention;
[0020]FIG. 6 is a diagram showing the operation waveforms of the A/D conversion part according to the embodiment of the present invention;
[0021]FIG. 7 is a block diagram showing a D/A conversion part of a receiver according to the embodiment of the present invention; and
[0022]FIG. 8 is a block diagram showing a signal processing circuit of the receiver according to the embodiment of the present invention.
[0025]FIG. 1 is a diagram showing a video transmission system 1 according to the embodiment of the present invention.
[0031]FIG. 2 is a block diagram showing the signal processing circuit 41.
[0038]FIG. 3 is a diagram for illustrating the operation of the ID insertion part 223. In FIG. 3, (a) indicates the input luminance signal supplied to the ID insertion part 223, (b) indicates ID signals inserted into the input luminance signal, and (c) indicates the output luminance signal of the ID insertion part 223.
The pre-emphasis circuit 222 supplies the ID insertion part 223 with the luminance signal as shown in (a) of FIG. 3. A portion of a vertical blanking interval V.blank is extracted from the luminance signal and shown in (a) of FIG. 3. The vertical blanking interval V.blank, which is set to 20H (H=63.5 μs), includes equivalent pulses P1 and P2, vertical synchronizing pulses V.SYNC, and a burst signal Sb. The equivalent pulses P1 are a signal for causing interlacing to be performed with accuracy, and are provided for 3H. The vertical synchronizing pulses V.SYNC are a signal for establishing vertical synchronization of scanning lines, and are provided for 3H after the equivalent pulses P1. The equivalent pulses P2 are provided for 3H after the vertical synchronizing pulses V.SYNC. The burst signal Sb is inserted in the remaining period after the equivalent pulses P2.
[0054]FIG. 4 is a diagram showing the frequency layout of the output signal of the mixer 215.
[0058]FIG. 5 is a block diagram showing the A/D conversion part 42. The A/D conversion part 42 includes a compactor 251, a D-type flip-flop 252, and a clock generator circuit 253.
[0059]FIG. 6 is a diagram showing the operation waveforms of the A/D conversion part 42. In FIG. 6, (a) indicates the frequency-modulated signal supplied from the signal processing circuit 41, (b) indicates the output of the comparator 251, (c) indicates clock pulses generated in the clock generator circuit 253, (d) indicates sampling outputs in the D-type flip-flop 252, and (e) indicates the output of the D-type flip-flop 252.
[0069]FIG. 7 is a block diagram showing the D/A conversion part 51.
[0074]FIG. 8 is a block diagram showing the signal processing circuit 52.
U.S. Classification 375/242, 348/E07.031, 348/E07.042
International Classification H04L12/28, H04N7/06, H04N7/088, H04L27/10
Cooperative Classification H04N7/06, H04N7/088, H04W4/18, H04W88/02
European Classification H04N7/088, H04N7/06