Source: http://www.google.es/patents/US8071983?dq=flatulence
Timestamp: 2013-06-19 02:35:34
Document Index: 525439013

Matched Legal Cases: ['Application No. 200680021817', 'Application No. 200680023301', 'Application No. 094136197', 'Application No. 03817697', 'Application No. 10', 'Application No. 10', 'Application No. 200680023301', 'Application No. 200580009823', 'Application No. 200680021817', 'Application No. 05711376', 'Application No. 112006001735', 'Application No. 10', 'Application No. 0724762', 'Application No. 200680023301', 'Application No. 03817699', 'Application No. 06815547', 'Application No. 11', 'Application No. 2006', 'Application No. 200580007279', 'Application No. 95122087', 'Application No. 95122087', 'Application No. 95123858', 'Application No. 95123858', 'Application No. 95123858', 'Application No. 95135820', 'Application No. 95135820', 'Application No. 95135820', 'Application No. 200680021817', 'Application No. 200410050129', 'Application No. 200580032314', 'Application No. 200580032314', 'Application No. 2005070131', 'Application No. 200604766']

Patente US8071983 - Semiconductor device structures and methods of forming semiconductor structures - Google PatentesB�squeda Im�genes Maps Play YouTube Noticias Gmail Drive M�s » B�squeda avanzada de patentes | Historial web | Iniciar sesi�n B�squeda avanzada de patentesPatentesA method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal...http://www.google.es/patents/US8071983?utm_source=gb-gplus-sharePatente US8071983 - Semiconductor device structures and methods of forming semiconductor structures N�mero de publicaci�nUS8071983 B2Tipo de publicaci�nConcesi�n N�mero de solicitud12/463,309 Fecha de publicaci�n6 Dic 2011 Fecha de presentaci�n8 May 2009 Fecha de prioridad21 Jun 2005Tambi�n publicado comoCN101199042A, CN101199042B, DE112006001589B4, DE112006001589T5, US7547637, US20070001173, US20090218603, US20120032237, WO2007002426A2, WO2007002426A3 N�mero de publicaci�n12463309, 463309, US 8071983 B2, US 8071983B2, US-B2-8071983, US8071983 B2, US8071983B2 InventoresJustin K. Brask, Robert S. Chau, Suman Datta, Brian S. Doyle, Jack Kavalieros, Amlan Majumdar, Uday Shah Cesionario originalIntel CorporationCitas de patentes (99), Otras citas (144), Citada por (2), Clasificaciones (17) Enlaces externos: USPTO, Cesi�n de USPTO, EspacenetSemiconductor device structures and methods of forming semiconductor structuresUS 8071983 B2 Resumen A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
Citas de patentes Patente citada Fecha de presentaci�n Fecha de publicaci�n Solicitante T�tuloUS423114910 Oct 19784 Nov 1980Texas Instruments IncorporatedNarrow band-gap semiconductor CCD imaging device and method of fabricationUS448765230 Mar 198411 Dic 1984Motorola, Inc.Slope etch of polyimideUS471170116 Sep 19868 Dic 1987Texas Instruments IncorporatedSelf-aligned transistor methodUS48187159 Jul 19874 Abr 1989Industrial Technology Research InstituteMethod of fabricating a LDDFET with self-aligned silicideUS490506321 Jun 198827 Feb 1990American Telephone And Telegraph Company, At&T Bell LaboratoriesFloating gate memoriesUS49065896 Feb 19896 Mar 1990Industrial Technology Research InstituteInverse-T LDDFET with self-aligned silicideUS490704823 Nov 19876 Mar 1990Xerox CorporationDouble implanted LDD transistor self-aligned with gateUS499487326 Dic 198919 Feb 1991Motorola, Inc.Local interconnect for stacked polysilicon deviceUS499657430 Jun 198926 Feb 1991Fujitsu LimitedMIS transistor structure for increasing conductance between source and drain regionsUS502320323 Jun 198911 Jun 1991Korea Electronics & Telecommunications Research Institute Et Al.Method of patterning fine line width semiconductor topology using a spacerUS51206662 May 19909 Jun 1992Fujitsu LimitedManufacturing method for semiconductor deviceUS51247773 Ene 199123 Jun 1992Samsung Electronics Co., Ltd.Dielectric medium for capacitor of semiconductor deviceUS517903724 Dic 199112 Ene 1993Texas Instruments IncorporatedIntegration of lateral and vertical quantum well transistors in the same epitaxial stackUS521627127 Sep 19911 Jun 1993Kabushiki Kaisha ToshibaBiCMOS device with low bandgap CMOS contact regions and low bandgap bipolar base regionUS527810212 Feb 199311 Ene 1994Fujitsu LimitedSOI device and a fabrication process thereofUS530899924 Feb 19933 May 1994Fujitsu LimitedMOS FET having a thin film SOI structureUS532881025 Nov 199212 Jul 1994Micron Technology, Inc.Method for reducing, by a factor or 2.sup.-N, the minimum masking pitch of a photolithographic processUS533895930 Mar 199316 Ago 1994Samsung Electronics Co., Ltd.Thin film transistor with three dimensional multichannel structureUS534683617 Ago 199313 Sep 1994Micron Technology, Inc.Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnectsUS53468398 Ene 199313 Sep 1994Texas Instruments IncorporatedSidewall doping technique for SOI transistorsUS535711919 Feb 199318 Oct 1994Board Of Regents Of The University Of CaliforniaField effect devices having short period superlattice structures using Si and GeUS539150627 Ene 199321 Feb 1995Kawasaki Steel CorporationManufacturing method for semiconductor devices with source/drain formed in substrate projection.US539864127 Jul 199321 Mar 1995Texas Instruments IncorporatedMethod for p-type doping of semiconductor structures formed of group II and group VI elementsUS542823729 Nov 199327 Jun 1995Canon Kabushiki KaishaSemiconductor device having an insulated gate transistorUS546662125 Oct 199314 Nov 1995Hitachi, Ltd.Method of manufacturing a semiconductor device having silicon islandsUS547586927 May 199412 Dic 1995Nec CorporationRadio base station capable of distinguishing between interference due to collisions of outgoing call signals and an external interference noiseUS547903327 May 199426 Dic 1995Sandia CorporationComplementary junction heterostructure field-effect transistorUS548287716 Feb 19949 Ene 1996Samsung Electronics Co., Ltd.Method for making a semiconductor device having a silicon-on-insulator structureUS551488513 Ene 19957 May 1996Myrick; James J.SOI methods and apparatusUS552185917 Ene 199528 May 1996Fujitsu LimitedSemiconductor memory device having thin film transistor and method of producing the sameUS554335131 Oct 19946 Ago 1996Matsushita Electric Industrial Co., Ltd.Method of producing electrically insulated silicon structureUS554558613 May 199413 Ago 1996Nec CorporationMethod of making a transistor having easily controllable impurity profileUS55548702 Ago 199510 Sep 1996Motorola, Inc.Integrated circuit having both vertical and horizontal devices and process for making the sameUS556307720 Jun 19958 Oct 1996Hyundai Electronics Industries Co., Ltd.Method of fabricating a thin film transistor having vertical channelUS55762272 Nov 199419 Nov 1996United Microelectronics Corp.Process for fabricating a recessed gate MOS deviceUS557851320 Abr 199526 Nov 1996Mitsubishi Denki Kabushiki KaishaMethod of making a semiconductor device having a gate all around type of thin film transistorUS559591920 Feb 199621 Ene 1997Chartered Semiconductor Manufacturing Pte Ltd.Method of making self-aligned halo process for reducing junction capacitanceUS559594127 Feb 199521 Ene 1997Mitsubishi Denki Kabushiki KaishaMethod of forming fine patternsUS56524543 Jul 199629 Jul 1997Iwamatsu; ToshiakiSemiconductor device on an SOI substrateUS565880626 Oct 199519 Ago 1997National Science CouncilMethod for fabricating thin-film transistor with bottom-gate or dual-gate configurationUS566520328 Abr 19959 Sep 1997International Business Machines CorporationSilicon etching methodUS568204817 May 199628 Oct 1997Nissan Motor Co., Ltd.Groove-type semiconductor deviceUS569886913 Sep 199516 Dic 1997Kabushiki Kaisha ToshibaInsulated-gate transistor having narrow-bandgap-sourceUS570101624 Nov 199523 Dic 1997Kabushiki Kaisha ToshibaSemiconductor device and method for its manufactureUS571687913 Ene 199710 Feb 1998Goldstar Electron Company, Ltd.Method of making a thin film transistorUS573954412 Dic 199514 Abr 1998Matsushita Electric Industrial Co., Ltd.Quantization functional device utilizing a resonance tunneling effect and method for producing the sameUS576044229 Sep 19952 Jun 1998Kabushiki Kaisha ToshibaSemiconductor device of a silicon on insulator metal-insulator type with a concave featureUS57705132 May 199523 Jun 1998Mitsubishi Denki Kabushiki KaishaMethod for producing semiconductor device with heat dissipation structureUS577333117 Dic 199630 Jun 1998International Business Machines CorporationMethod for making single and double gate field effect transistors with sidewall source-drain contactsUS577682122 Ago 19977 Jul 1998Vlsi Technology, Inc.Method for forming a reduced width gate electrodeUS579308818 Jun 199611 Ago 1998Integrated Device Technology, Inc.Structure for controlling threshold voltage of MOSFETUS580484831 Oct 19978 Sep 1998Sony CorporationField effect transistor having multiple gate electrodes surrounding the channel regionUS581132428 Feb 199722 Sep 1998Lg Semicon Co., Ltd.Method for manufacturing thin film transistorUS58145454 Mar 199729 Sep 1998Motorola, Inc.Semiconductor device having a phosphorus doped PECVD film and a method of manufactureUS581489519 Dic 199629 Sep 1998Sony CorporationStatic random access memory having transistor elements formed on side walls of a trench in a semiconductor substrateUS582162912 Jul 199513 Oct 1998United Microelectronics CorporationBuried structure SRAM cell and methods for fabricationUS582776920 Nov 199627 Oct 1998Intel CorporationMethod for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrodeUS584427813 Sep 19951 Dic 1998Kabushiki Kaisha ToshibaSemiconductor device having a projecting element regionUS585622524 Nov 19975 Ene 1999Chartered Semiconductor Manufacturing LtdCreation of a self-aligned, ion implanted channel region, after source and drain formationUS58594569 Sep 199612 Ene 1999Texas Instruments IncorporatedMultiple transistor integrated circuit with thick copper interconnectUS588001514 Oct 19949 Mar 1999Sgs-Thomson Microelectronics, Inc.Method of producing stepped wall interconnects and gatesUS588830929 Dic 199730 Mar 1999Taiwan Semiconductor Manufacturing Company, Ltd.Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasmaUS588930427 Jun 199730 Mar 1999Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS589971025 Feb 19984 May 1999Sony CorporationMethod for forming field effect transistor having multiple gate electrodes surrounding the channel regionUS590528526 Feb 199818 May 1999Advanced Micro Devices, Inc.Ultra short trench transistors and process for making sameUS590831331 Dic 19961 Jun 1999Intel CorporationMethod of forming a transistorUS595270118 Ago 199714 Sep 1999National Semiconductor CorporationDesign and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor valueUS596591423 Dic 199712 Oct 1999Mitsubishi Denki Kabushiki KaishaThin film transistor having a branched gate and channelUS59767679 Oct 19972 Nov 1999Micron Technology, Inc.Ammonium hydroxide etch of photoresist masked siliconUS59857266 Nov 199816 Nov 1999Advanced Micro Devices, Inc.Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFETUS601392618 Abr 199711 Ene 2000Mitsubishi Denki Kabushiki KaishaSemiconductor device with refractory metal elementUS60181768 Sep 199725 Ene 2000Samsung Electronics Co., Ltd.Vertical transistor and memory cellUS60312498 Jul 199729 Feb 2000Semiconductor Energy Laboratory Co., Ltd.CMOS semiconductor device having boron doped channelUS60514526 Ene 199818 Abr 2000Kabushiki Kaisha ToshibaMethod for manufacturing a semiconductor device with ion implantationUS605435529 Jun 199825 Abr 2000Kabushiki Kaisha ToshibaMethod of manufacturing a semiconductor device which includes forming a dummy gateUS606367524 Oct 199716 May 2000Texas Instruments IncorporatedMethod of forming a MOSFET using a disposable gate with a sidewall dielectricUS606367724 Oct 199716 May 2000Texas Instruments IncorporatedMethod of forming a MOSFET using a disposable gate and raised source and drainUS60668696 Oct 199723 May 2000Micron Technology, Inc.Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitorUS608720831 Mar 199811 Jul 2000Advanced Micro Devices, Inc.Method for increasing gate capacitance by using both high and low dielectric gate materialUS60936215 Abr 199925 Jul 2000Vanguard International Semiconductor Corp.Method of forming shallow trench isolationUS61142011 Jun 19985 Sep 2000Texas Instruments-Acer IncorporatedMethod of manufacturing a multiple fin-shaped capacitor for high density DRAMsUS61142066 Nov 19985 Sep 2000Advanced Micro Devices, Inc.Multiple threshold voltage transistor implemented by a damascene processUS61177415 Ene 199912 Sep 2000Texas Instruments IncorporatedMethod of forming a transistor having an improved sidewall gate structureUS612084623 Dic 199719 Sep 2000Advanced Technology Materials, Inc.Method for the selective deposition of bismuth based ferroelectric thin films by chemical vapor depositionUS614407215 Ene 19997 Nov 2000Mitsubishi Denki Kabushiki KaishaSemiconductor device formed on insulating layer and method of manufacturing the sameUS61502227 Ene 199921 Nov 2000Advanced Micro Devices, Inc.Method of making a high performance transistor with elevated spacer formation and self-aligned channel regionsUS61534859 Nov 199828 Nov 2000Chartered Semiconductor Manufacturing Ltd.Salicide formation on narrow poly lines by pulling back of spacerUS61630535 Nov 199719 Dic 2000Ricoh Company, Ltd.Semiconductor device having opposite-polarity region under channelUS616588015 Jun 199826 Dic 2000Taiwan Semiconductor Manufacturing CompanyDouble spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuitsUS617482016 Feb 199916 Ene 2001Sandia CorporationUse of silicon oxynitride as a sacrificial material for microelectromechanical devicesUS61909759 Dic 199820 Feb 2001Matsushita Electric Industrial Co., Ltd.Method of forming HCMOS devices with a silicon-germanium-carbon compound semiconductor layerUS62008654 Dic 199813 Mar 2001Advanced Micro Devices, Inc.Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gateUS621830930 Sep 199917 Abr 2001Lam Research CorporationMethod of achieving top rounding and uniform etch depths while etching shallow trench isolation featuresUS625172915 Dic 199926 Jun 2001U.S. Philips CorporationMethod of manufacturing a nonvolatile memoryUS625176329 Jun 199826 Jun 2001Kabushiki Kaisha ToshibaSemiconductor device and method for manufacturing sameUS62522849 Dic 199926 Jun 2001International Business Machines CorporationPlanarized silicon fin deviceUS625913524 Sep 199910 Jul 2001International Business Machines CorporationMOS transistors structure for reducing the size of pitch limited circuitsUS626192114 Sep 199917 Jul 2001Taiwan Semiconductor Manufacturing Co., Ltd.Method of forming shallow trench isolation structureUS62624566 Nov 199817 Jul 2001Advanced Micro Devices, Inc.Integrated circuit having transistors with different threshold voltagesOtras citasReferencia1Auth, Christopher P., et al., "Vertical, Fully-Depleted, Surrounding Gate MOSFETs on sub-0.1 um Thick Silicon Pillars," 54th Annual Device Research Conference Digest, 1996, 4 pgs.2Buchanan, D. A., et al., "Fabrication of Midgap Metal Gates Compatible with Ultrathin Dielectrics," Applied Physics Letters, vol. 73.12,Sep. 21, 1998, 3 pgs.3Burenkov, A. , et al., "Corner Effect in Double and Triple Gate FinFETs," European Solid-State Device Research 2003, 33rd Conference on ESSDERC, 4pgs.4Chang, L. , et al., "CMOS Circuit Performance Enhancement by Surface Orientation Optimization," IEEE Transactions on Electron Devices, vol. 51, No. 10, Oct. 2004, 7 pgs.5Chang, S. T., et al., "3-D Simulation of Strained Si/SiGe Heterojunction FinFets, Semiconductor Device Research Symposium," Dec. 2003, 2 pgs.6Chau, R., et al., "Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate and Tri-gate (Invited Paper)", Components Reserach, Logic Technolgoy Development, Intel Corporation, Hillsboro, OR, 2 pages.7Chau, Robert , "Advanced Metal Gate/High-K Dielectric Stacks for High-Performance CMOS Transistors," Components Research, Intel Corporation, 2004, 3 pgs.8Choi, Yang-Kyu , et al., "A Spacer Patterning Technology for Nanoscale CMOS," IEEE, (49)3, XP-001102694, Mar. 2002, 6 pgs.9Choi, Yang-Kyu , et al., "Sub-20nm CMOS FinFET Technologies," IEEE, IEDM, 2001, 4 pgs.10Claflin, B. , et al., "Interface Studies of Tungsten Nitride and Titanium Nitride Composite Metal Gate Electrodes With Thin Dielectric Layers," Journal of Vacuum Science and Technology A 16.3, May/Jun. 1998, 5 pgs.11Collaert, N. , et al., A Functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node, IEEE Electron Device Letters, vol. 25, No. 8, Aug. 2004, 3 pgs.12Final Office Action for U.S. Appl. No. 11/154,138 mailed Dec. 8, 2009, 12 pgs.13Final Office Action for U.S. Appl. No. 11/322,795 Mailed Jan. 13, 2010, 12 Pages.14Final Office Action for U.S. Appl. No. 11/335,103 mailed May 26, 2010, 14 pgs.15Final Office Action from U.S. Appl. No. 11/080,765 mailed Nov. 13, 2007, 13 pgs.16Final Office Action from U.S. Appl. No. 11/158,661 mailed Jan. 15, 2008, 25 pgs.17Final Office Action from U.S. Appl. No. 11/240,487 mailed Sep. 21, 2009, 22 Pages.18Final Office Action from U.S. Appl. No. 11/828,290 mailed Feb. 17, 2010, 18 pages.19Final Office Action from U.S. Appl. No. 12/025,665 mailed Jun. 10, 2009, 10 pgs.20Final Office Action from U.S. Appl. No. 12/893,753 mailed Jun. 28, 2011, 27 pages.21First Office Action from Chinese Patent Application No. 200680021817.0 mailed Jun. 12, 2009, 11 pgs.22First Office Action from Chinese Patent Application No. 200680023301.X mailed Jun. 26, 2009, 21 pgs.23Fried, David M., et al., "High-Performance P-Type Independent-Gate FinFETs," IEEE 25(4), 2004, 3 pgs.24Fried, David M., et al., "Improved Independent Gate N-Type FinFET Fabrication and Characterization," IEEE 24(9), Sep. 2003, 3 pgs.25Guo, Jing , et al., "Performance Projections for Ballistic Carbon Nanotube Field-Effect Transistors," Applied Physics Letters 80(17), Apr. 29, 2002, 3 pgs.26Hisamoto, Digh , et al., "A Folded-Channel MOSFET for Deepsub-tenth Micron Era," 1998 IEEE International Electron Device Meeting Technical Digest, 3 pgs.27Hisamoto, Digh , et al., "A Fully Depleted Lean-Channel Transistor (DELTA)-A Novel Vertical Ultrathin SOI MOSFET," IEEE Electron Device Letters, V. 11 (1), Jan. 1990, 4 pgs.28Hisamoto, Digh , et al., "FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm," IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, 6 pgs.29Huang, Xuejue , et al., "Sub 50-nm FinFET: PMOS," 1999 IEEE International Electron Device Meeting Technical Digest, 4 pgs.30Hwang, Jeong-Mo , et al., "Novel Polysilicon/Tin Stacked-Gate Structure for Fully-Depleted SOI/CMOS," International Electronic Devices Meeting Technical Digest, 1992, 4 pgs.31Ieong, M. , et al., "Three Dimensional CMOS Devices and Integrated Circuits," IEEE CICC, San Jose, CA Sep. 21-24, 2003, 8 pgs.32International Preliminary Report on Patentability from Application No. PCT/US2006/024516 mailed Jan. 10, 2008, 11 pgs.33International Search Report & Written Opinion from PCT/US2005/000947 mailed on May 3, 2005, 14 pgs.34International Search Report & Written Opinion from PCT/US2005/033439 mailed on Jan. 31, 2006, 7 pgs.35International Search Report & Written Opinion from PCT/US2005/035380 mailed on Feb. 13, 2006, 14 pgs.36International Search Report & Written Opinion from PCT/US2005/037169 mailed on Feb. 23, 2006, 11 pgs.37International Search Report & Written Opinion from PCT/US2006/000378 mailed on May 24, 2006, 11 pgs.38International Search Report & Written Opinion from PCT/US2006/024516 mailed on Jan. 17, 2007, 18 pgs.39International Search Report & Written Opinion from PCT/US2006/025751 mailed on Dec. 6, 2006, 14 pgs.40International Search Report & Written Opinion from PCT/US2006/037634 mailed on May 31, 2007, 21 pgs.41International Search Report & Written Opinion from PCT/US2006/037643 mailed on Jan. 24, 2007, 14 pgs.42International Search Report and Written Opinion from PCT/US2004/032442 mailed Jun. 16, 2005, 22 pgs.43International Search Report and Written Opinion from PCT/US2005/010505 mailed Aug. 26, 2005, 24 pgs.44International Search Report and Written Opinion from PCT/US2005/010505 mailed on Aug. 26, 2005, 24 pgs.45International Search Report and Written Opinion from PCT/US2005/020339 mailed on Oct. 4, 2005, 12 pgs.46International Search Report from PCT/US 03/26242 mailed on Jan 26, 2004, 8 pgs.47International Search Report from PCT/US 03/39727 mailed on Apr. 27, 2004, 6 pgs.48International Search Report from PCT/US 03/40320 mailed Jun. 2, 2004, 6 pgs.49International Search Report PCT/US2003/40320 mailed Jun. 2, 2004, 6 pgs.50Invitation to Pay Additional Fees from PCT/US2004/032442 mailed on Apr. 12, 2005, 5 pgs.51IPO Search Report for Application No. 094136197, date mailed Sep. 19, 2008, 1 pg.52Javey, Ali , et al., "Ballistic carbon nanotube field-effect transistors," Nature, vol. 424, Aug. 7, 2003, 4 pgs.53Javey, Ali , et al., "High-k dielectrics for advanced carbon-nanotube transistors and logic gates," www.nature.com/naturematerials.com, 2002, 6 pgs.54Jin, B., Mobility Enhancement in Compressively Strained Sige Surface Channel PMOS Transistors with HFO2/TIN Gate Stack, Components Research, Intel Corporation, Oct. 2004, 12 pgs.55Jones, E. C., et al., Doping Challenges in Exploratory Devices for High Performance Logic, 14th Int'l Conference, Piscataway, NJ, Sep. 22-27, 2002, 6 pgs.56Kim, Sung M., et al., A Novel Multi-channel Field Effect Transistor (McFET) on Bulk Si for High Performance Sub-80nm Application, IEEE, 2004, 4 pgs.57Kuo, Charles, et al., "A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications", IEEE 50(12):, (2003), 2408-2416.58Kuo, Charles, et al., A Capacitorless Double-Gate DRAM Cell Design for High Density Applications, IEEE, 2002, 4 pgs.59Ludwig, et al., FinFET Technology for Future Microprocessors, IEEE Int'l. SOI Conference, New Port Beach, CA, Sep. 29-Oct. 2, 2003, 2 pgs.60Martel, Richard, et al., "Carbon Nanotube Field Effect Transistors for Logic Applications", IEEE 2001, 4 pgs.61Mayer, T. M., et al., "Chemical Vapor Deposition of Flouroalkylsilane Monolayer Films for Adhesion Control in Microelectromechanical Systems", J. Vac. Sci. Technol. B. 18(5), 2000, 8 pgs.62Nackaerts, et al., "A 0.314um2 6T-SRAM Cell build with Tall Triple-Gate Devices for 45nm node applications using 0.75NA 193nm lithography", IEEE, 2004, 4 pgs.63Non-Final Office Action for European Application No. 03817697.0 Mailed Mar. 9, 2010, 5 Pages.64Non-Final Office Action for Korean Patent Application No. 10-2007-7030988 Mailed Mar. 12, 2010, 3 Pages.65Non-Final Office Action for U.S. Appl. No. 10/973,228 mailed Feb. 2, 2010, 8 pages.66Non-Final Office Action for U.S. Appl. No. 11/240,440 Mailed May 12, 2010, 8 pages.67Non-Final Office Action for U.S. Appl. No. 11/240,487 mailed Dec. 11, 2009, 10 pgs.68Non-Final Office Action for U.S. Appl. No. 11/335,103 mailed Nov. 13, 2009, 17 pages.69Non-final Office Action for U.S. Appl. No. 11/855,823 mailed Mar. 15, 2010 31 pages.70Non-Final Office Action for U.S. Appl. No. 11/855,823, Mailed Jul. 23, 2009, 31 pages.71Non-Final Office Action for U.S. Appl. No. 12/114,227 mailed Mar. 30, 2010, 30 pages.72Non-Final Office Action for U.S. Appl. No. 12/259,464, Mailed Oct. 20, 2009, 41 pgs.73Non-Final Office Action for U.S. Appl. No. 12/369,642 mailed Apr. 27, 2010, 15 pgs.74Non-Final Office Action from U.S. Appl. No. 11/322,795 Mailed Jul. 28, 2009, 18 pgs.75Non-final Office Action from U.S. Appl. No. 11/828,290 mailed Aug. 19, 2009, 32 pgs.76Notice of Preliminary Rejection mailed Sep. 14, 2009 for Korean Application No. 10-2007-7030988 incl. translation, (Sep. 14, 2009), 4 pages.77Nowak, E. J., et al., "A Functional FinFET-DGCMOS SRAM Cell", Int'l. Electron Devices Meeting, San Francisco, CA Dec. 8-11, 2002, 4 pgs.78Nowak, E. J., et al., "Scaling Beyond the 65 nm Node with FinFET-DGCMOS", IEEE CICC, San Jose, CA Sep. 21-24, 2003, 4 pgs.79Nowak, Edward J., et al., "Turning Silicon On Its Edge", IEEE Circuits & Devices Magazine vol. 1, Jan./Feb. 2004, 12 pgs.80Office Action for Application No. 200680023301.X dated May 23, 2011, 11 pages.81Office Action for Chinese Patent Application No. 200580009823.X mailed Jun. 21, 2010, 5 pages.82Office Action for Chinese Patent Application No. 200680021817.0 mailed Jun. 12, 2009, 11 pages.83Office Action for EP Application No. 05711376.3 mailed Jan. 11, 2010, 5 pages.84Office Action for German Application No. 112006001735.7 with translation mailed Oct. 20, 2009, 6 pages.85Office Action for Korean Patent Application No. 10-2007-7030988 mailed Aug. 10, 2010, 12 pages.86Office Action for U.S. Appl. No. 11/064,996 mailed Jun. 27, 2008, 28 pages.87Office Action for U.S. Appl. No. 11/064,996 mailed Mar. 13, 2007, 27 pages.88Office Action for U.S. Appl. No. 11/064,996 mailed Mar. 14, 2008, 13 pages.89Office Action for U.S. Appl. No. 11/064,996 mailed Sep. 4, 2007, 30 pages.90Office Action for U.S. Appl. No. 11/332,189 mailed Jul. 8, 2010, 12 pgs.91Office Action for U.S. Appl. No. 12/333,248 mailed Nov. 30, 2009, 24 pgs.92Office Action for U.S. Appl. No. 12/333,248, mailed Jun. 21, 2011, 15 pages.93Office Action for U.S. Appl. No. 12/343,400 mailed Dec. 30, 2009, 27 pages.94Office Action for United Kingdom Patent Application No. 0724762.0 mailed Jul. 15, 2010, 10 pgs.95Office Action from Chinese Patent Application No. 200680023301.X mailed Jun. 26, 2009, 21 pgs.96Office Action from European Patent Application No. 03817699.6 mailed Aug. 29, 2007, 3 pgs.97Office Action from European Patent Application No. 06815547.2, mailed Sep. 9, 2008, 14 pgs.98Office Action from German Patent Application No. 11 2006 003 576.2-33 mailed Nov. 11, 2008, 6 pgs.99Office Action from Japanese Application No. 2006-549560 mailed Apr. 13, 2010, 6 pgs.100Office Action from PRC Application No. 200580007279.5, PCT/US05/ 000947, mailed Apr. 4, 2008, 2 pgs.101Office Action from Taiwan Patent Application No. 95122087 mailed Dec. 16, 2008, 6 pgs.102Office Action from Taiwan Patent Application No. 95122087 mailed Jun. 20, 2008, 8 pgs.103Office Action from Taiwan Patent Application No. 95123858, dated Oct. 9, 2008, 10pgs.104Office Action from Taiwan Patent Application No. 95123858-translation, mailed Mar. 3, 2009, 10 pgs.105Office Action from Taiwan Patent Application No. 95123858�translation, mailed Mar. 3, 2009, 10 pgs.106Office Action from Taiwan Patent Application No. 95135820 mailed Jun. 4, 2009, 18 pgs.107Office Action from Taiwan Patent Application No. 95135820 mailed Oct. 22, 2009, 6 pgs.108Office Action from Taiwan Patent Application No. 95135820 mailed on Jan. 9, 2009, 14 pgs.109Office Action from U.S. Appl. No. 10/227,068 mailed Dec. 18, 2006, 25 pgs.110Office Action from U.S. Appl. No. 10/703,316 mailed Dec. 15, 2006, 22 pgs.111Office Action from U.S. Appl. No. 11/080,765 mailed May 2, 2007, 47 pgs.112Office Action from U.S. Appl. No. 11/154,138 mailed Jun. 23, 2009, 15 pgs.113Office Action from U.S. Appl. No. 11/234,014 mailed Jan. 23, 2008, 9 pgs.114Office Action from U.S. Appl. No. 11/240,487 mailed Mar. 17, 2009, 13 pgs.115Office Action from U.S. Appl. No. 11/322,795 mailed Mar. 4, 2009, 12 pgs.116Office Action from U.S. Appl. No. 11/855,823, mailed Dec. 30, 2008, 18 pgs.117Office Action from U.S. Appl. No. 12/025,665 mailed on Nov. 12, 2008, 21 pgs.118Office Action from U.S. Appl. No. 12/893,753 mailed Jan. 21, 2011 27 pages.119Ohsawa, Takashi , et al., "Memory Design Using a One-Transistor Gain Cell on SOI", IEEE 37(11), Nov. 2002, 13 pgs.120Park, Donggun , et al., 3-dimensional nano-CMOS Transistors to Overcome Scaling Limits, IEEE 2004, ISBN 0-7803-8511-X, 6 pgs.121Park, Jae-Hyoun , et al., Quantum-Wired MOSFET Photodetector Fabricated by Conventional Photolighography on SOI Substrate, Nanotechnology, 4th IEEE Conference on Munich, Germany, Aug. 16-19, 2004, Piscataway, NJ, 3 pgs.122Park, Jong-Tae , et al., "Pi-Gate SOI MOSFET", IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001, 2 pgs.123Park, T. , et al., "Fabrication of Body-Tied FinFETs (Omega MOSFETS) Using Bulk Si Wafers", 2003 Symposia on VLSI Technology Digest of Technical Papers, (Jun. 2003), pp. 135-136.124Park, T. , et al., "PMOS Body-Tied FinFET (Omega MOSFET) Characteristics", IEEE Device Research Conference, Piscataway, NJ, Jun. 23-25, 2003, 2 pgs.125Second Office Action for Chinese Application No. 200680021817.0 mailed Dec. 11, 2009, 8 pgs.126Second Office Action from Chinese Patent Application No. 200410050129.X mailed Jul. 24, 2009, 4 pgs.127Second Office Action from Chinese Patent Application No. 200580032314.9 mailed May 8, 2009, 14 pgs.128Seevinck, Evert , et al., Static-Noise Margin Analysis of MOS SRAM Cells, IEEE, Journal of Solid-State Circuits, (SC-22)5, Oct. 1987, 7 pgs.129Stadele, M. , et al., A Comprehensive Study of Corner Effects in Tri-gate Transistors, IEEE 2004, 4 pgs.130Stolk, Peter A., et al., Device Modeling Statistical Dopant Fluctuations in MOS Transistors, IEEE Transactions on Electron Devices, (45)9, 1997, 4 pgs.131Subramanian, V. , et al., "A Bulk-Si-compatible Ultrathin-body SOI Technology for sub-100nm MOSFETs", IEEE, 1999, 4 pgs.132Sugizaki, T. , et al., Novel Multi-bit SONOS Type Flash Memory Using a High-k Charge Trapping Layer, VLSI Technology, 2003. Digest of Technical Papers. Symposium on Jun. 10-12, 2003, 2 pgs.133Tanaka, T. , et al., Scalability Study on a Capacitorless IT-DRAM: From Single-gate PD-SOI to Double-gate FinDRAM, IEEE, 2004, 4 pgs.134Tang, Stephen H., et al., FinFET-A Quasi-Planar Double-Gate MOSFET, IEEE International Solid-State Circuits Conference, Feb. 6, 2001, 3 pgs.135Tang, Stephen H., et al., FinFET�A Quasi-Planar Double-Gate MOSFET, IEEE International Solid-State Circuits Conference, Feb. 6, 2001, 3 pgs.136Third Office Action for Chinese Application No. 200580032314.9 mailed Jan. 29, 2010, 13 pgs.137Tokoro, Kenji , et al., Anisotropic Etching Properties of Silicon in KOH and TMAH Solutions, International Symposium on Micromechatronics and Human Science, IEEE, 1998, 6 pgs.138Wang, X., et al., "Band alignments in sidewall strained Si/strained SiGe heterostructures", (May 28, 2002), 1-5.139Wolf, Stanley , et al., Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, Sep. 1986, 3 pgs.140Written Opinion from Patent Application No. 2005070131 mailed Mar. 18, 2007, 4 pgs.141Written Opinion from Singapore Patent Application No. 200604766-6 mailed Apr. 4, 2008, 4 pgs.142Xiong, W. , et al., Corner Effect in Multiple-Gate SOI MOSFETs, IEEE, 2003, 3 pgs.143Xiong, Weize , et al., Improvement of FinFET Electrical Characteristics by Hydrogen Annealing, IEEE Electron Device Letters, 25(8), Aug. 2004, 3 pgs.144Yang, Fu-Liang , et al., 5nm-Gate Nanowire FinFET, IEEE, 2004, 2 pgs. Citada por Patente citante Fecha de presentaci�n Fecha de publicaci�n Solicitante T�tuloUS8349692 *8 Mar 20118 Ene 2013Globalfoundries Singapore Pte. Ltd.Channel surface technique for fabrication of FinFET devicesUS20120228676 *8 Mar 201113 Sep 2012Globalfoundries Singapore PTE, LTD.CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES* Citada por examinadorClasificaciones Clasificaci�n de EE.UU.257/66, 438/717 Clasificaci�n internacionalH01L29/10 Clasificaci�n cooperativaH01L29/78681, H01L21/30617, H01L21/84, H01L29/045, H01L21/30608, H01L29/78684, H01L29/66795, H01L29/7853 Clasificaci�n europeaH01L21/306B4B, H01L21/84, H01L21/306B3, H01L29/04B, H01L29/78S4, H01L29/66M6T6F16FGirarImagen originalP�gina principal de Google - Sitemap - Descargas masivas de USPTO - Pol�tica de privacidad - Condiciones de servicio - Acerca de Google Patentes - Danos tu opini�nDatos proporcionados por IFI CLAIMS Patent Services©2012 Google