Source: http://www.google.com/patents/US8156285?ie=ISO-8859-1&dq=oakley+D523,461
Timestamp: 2014-12-26 12:17:59
Document Index: 380454280

Matched Legal Cases: ['art 12', 'art 12', 'Application No. 200510023015', 'Application No. 200510023015', 'Application No. 200510023015', 'Application No. 200810186367', 'Application No. 112005002364']

Patent US8156285 - Heterogeneous processors sharing a common cache - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA multi-core processor providing heterogeneous processor cores and a shared cache is presented....http://www.google.com/patents/US8156285?utm_source=gb-gplus-sharePatent US8156285 - Heterogeneous processors sharing a common cacheAdvanced Patent SearchPublication numberUS8156285 B2Publication typeGrantApplication numberUS 12/459,683Publication dateApr 10, 2012Filing dateJul 6, 2009Priority dateNov 19, 2004Also published asCN1783033A, CN1783033B, CN101470691A, CN101470691B, DE112005002364T5, US7577792, US8402222, US8799579, US20060112226, US20060112227, US20100011167, US20120215984, US20130275681, WO2006055477A1Publication number12459683, 459683, US 8156285 B2, US 8156285B2, US-B2-8156285, US8156285 B2, US8156285B2InventorsFrank T. Hady, Mason B. Cabot, John Beck, Mark B. RosenbluthOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (25), Non-Patent Citations (9), Referenced by (3), Classifications (7) External Links: USPTO, USPTO Assignment, EspacenetHeterogeneous processors sharing a common cacheUS 8156285 B2Abstract A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
processor cores including heterogeneous processor cores, the heterogeneous processor cores comprising a central processing unit (CPU) core and a graphics engine core; and
a cache connected to and shared by the central processing unit (CPU) core and the graphics engine core, the heterogeneous processor cores and the cache integrated on a single integrated die, the cache comprising a multi-ported cache, the multi-ported cache comprising at least one port to support transactions generated by the CPU core and at least one port to support transactions generated by the graphics core.
2. The processor of claim 1, wherein the processor core and the graphics engine core have a different set of instructions.
3. The processor of claim 1, wherein the ports are configured based on one or more of: command types, sizes, and alignments of a respective processor core type.
4. The processor of claim 3, wherein the multi-ported cache provides a different port type for the CPU core and the graphics engine core.
5. The processor of claim 1, wherein the processor cores include translation logic to translate transactions specific to each processor core to core-independent transactions.
6. The processor claim 1, wherein the cache includes logic to handle transactions generated by the different types of processor cores.
7. The processor of claim 1, wherein the heterogeneous processor cores use commands that allow different maximum transfer sizes, where one of the different maximum transfer sizes allows transfers that span multiple cache lines.
8. The processor of claim 1, wherein at least one of the heterogeneous processor cores is operable to lock a portion of the cache for extended private modification.
using a cache connected to and shared by heterogeneous processor cores to pass information between the heterogeneous cores, the heterogeneous processor cores comprising a central processing unit (CPU) core and a graphics engine core, the heterogeneous processor cores and the cache integrated on a single integrated die, the cache comprising a multi-ported cache, the multi-ported cache comprising at least one port to support transactions generated by the CPU core and at least one port to support transactions generated by the graphics core.
10. The method of claim 9, wherein the ports are configured to operate based on the respective processor core types that the ports support.
11. The method of claim 9, wherein the heterogeneous processor cores include translation logic to translate transactions specific to such processor cores to core-independent transactions.
12. The method of claim 9, wherein the cache includes logic to handle transactions generated by different types of processor cores.
13. The method of claim 9, wherein at least one of the heterogeneous processor cores is operable to lock a portion of the cache for extended private modification.
14. The method of claim 9, wherein the processor core and the graphics engine core have a different set of instructions.
This U.S. Patent application is a continuation of U.S. patent application Ser. No. 11/270,932 filed Nov. 10, 2005 now U.S. Pat. No. 7,577,792 which is a continuation of U.S. patent application Ser. No. 10,993,757 filed Nov. 19, 2004 now abandoned.
BACKGROUND Modern general purpose processors often access main memory (typically implemented as dynamic random access memory, or �DRAM�) through a hierarchy of one or more caches (e.g., L1 and L2 caches). Relative to main memory, caches (typically static random access memory, or �SRAM�, based) return data more quickly, but use more area and power. Memory accesses by general purpose processors usually display high temporal and spatial locality. Caches capitalize on this locality by fetching data from main memory in larger chunks than requested (spatial locality) and holding onto the data for a period of time even after the processor has used that data (temporal locality). This behavior often allows requests to be served very rapidly from cache, rather than more slowly from DRAM. Caches also generally can satisfy a much higher read/write load (for higher throughput) than main memory so previous accesses are less likely to be queued and slow current accesses.
DESCRIPTION OF DRAWINGS FIGS. 1A-1C show an exemplary heterogeneous multi-core processor having a bus-based shared cache architecture.
DETAILED DESCRIPTION FIGS. 1A-1C show a multi-processor system 10 that includes a multi-processor 12 coupled to a main memory 14 by a memory bus 16. The multi-processor 12 includes a cache (�shared cache�) 18 and multiple processor �cores� (collectively, processor cores 20) that are connected to and share the cache 18. The shared cache 18 in this figure is intended to represent a unit that includes both cache memory and associated control logic. The cache control logic includes logic to map memory addresses (�cache tags�) currently cached with their associated cache lines.
The special purpose processor cores may include, for example, at least one network processor unit (NPU) core and/or a graphics engine core. In the illustrated embodiment, the processor cores 20 include multiple NPU cores, shown as NPU cores 22 a, 22 b, . . . , 22 k, as well as a CPU core 24. The NPU cores 22 may be programmable Reduced Instruction Set Computing (RISC) cores that feature hardware support for multi-threaded operation. The NPU cores 22 may lack instructions typically found in other processors such as integer multiplication or division or floating point operations since these operation occur relatively infrequently in processing network packets. The CPU core 24 may be based on the architecture of any type of general purpose processors, e.g., an Intel� Architecture processor (�IA processor�) such as the Intel� Xeon processor, or the Intel Pentium� 4 processor or Xscale� processor.
As mentioned earlier, other core-to-cache interconnect mechanisms are possible. For example, and as shown in FIG. 2, the cache 18 may be a multi-ported cache with a port for each core, or a single port for each processor core type. Thus, in the case of the NPU 22 and CPU 24 cores, and as shown in the figure, the NPU cores 20 a, 20 b, . . . , 20 k connect to a port 50 of a first port type (shown as �type A�) and the CPU core 24 uses a port 52 of a second port type (shown as �type B�). Although port 50 is shown as a shared port, it will be appreciated that each NPU core could be connected to a respective port 50 over a separate channel. In this approach, the type of core generating an access request would be known by the port through which the request was received. In a multi-ported architecture such as this, the ports of each type (that is, ports supporting the different processor core types) may be �tuned� for the traffic patterns and other characteristics or features (such as commands, sizes, alignments and so forth) of those different processor core types. For example, NPU cores are bandwidth sensitive whereas CPU cores are more latency sensitive. Data returned by the cache for NPU requests may be batched on return to optimize through-put for fixed overhead. The tuning may take into account the types of transactions to be performed by a specific core type. Certain types of cores may perform mostly reads (e.g., graphics engines) while other core types may perform a more balanced mix of reads and writes.
The shared cache mechanism may support different cache policies and features, such as cache line alignment, cacheability and cache line locking. Cache line alignment converts a memory transaction that affects more than one shared cache line to multiple memory accesses that each fall within a single cache line. Cacheability of data involved in a memory transfer may be determined based on instruction type (e.g., an instruction that specifies a non-cached transaction) and/or based on memory type, e.g., as specified in a Memory Type Range Register (MTTR). With this feature at least one of the heterogeneous processor cores, e.g., the NPU core, is capable of generating reads and writes to the main memory 14 that bypass the shared cache 16 in the event of a cache miss. Cache line locking refers to the locking of individual cache lines by a core. With the cache line locking feature at least one of the heterogeneous processor cores can lock a portion (e.g., a single cache line, multiple cache lines, or all cache lines) of the shared cache lines for use as a private memory, possibly to extend local resources (such as scratch memory) already available to the core(s), or for extended private modification. By locking one, some or all of the cache lines, a core can utilize the locked memory space as extended local memory, while the cores continue coherent operation on any remaining portion of the shared cache. When only one of the heterogeneous processor cores is actively using the shared cache, that processor core receives the full benefit of the entire shared cache�effectively using the chip area to maximize performance. This cache locking may be implemented in the same manner as locking for atomic operations, e.g., using a cache line lock status field.
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