Source: http://www.google.com/patents/US8119925?dq=5319712
Timestamp: 2016-05-06 03:57:53
Document Index: 619770588

Matched Legal Cases: ['Application No. 2008', 'Application No. 200910126964', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 098104959']

Patent US8119925 - Core substrate and printed wiring board - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThe core layer of a core substrate is made of carbon fibers impregnated with resin. When the temperature of the core layer increases, the core layer suffers from an increase in the thickness because of thermal expansion of the resin. The core layer is sandwiched between the insulating layers containing...http://www.google.com/patents/US8119925?utm_source=gb-gplus-sharePatent US8119925 - Core substrate and printed wiring boardAdvanced Patent SearchPublication numberUS8119925 B2Publication typeGrantApplication numberUS 12/390,010Publication dateFeb 21, 2012Filing dateFeb 20, 2009Priority dateMay 30, 2008Fee statusPaidAlso published asCN101593750A, CN101593750B, US20090294161Publication number12390010, 390010, US 8119925 B2, US 8119925B2, US-B2-8119925, US8119925 B2, US8119925B2InventorsHideaki Yoshimura, Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Takashi Nakagawa, Shin HiranoOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (45), Non-Patent Citations (11), Referenced by (1), Classifications (12), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetCore substrate and printed wiring board
US 8119925 B2Abstract
The core layer of a core substrate is made of carbon fibers impregnated with resin. When the temperature of the core layer increases, the core layer suffers from an increase in the thickness because of thermal expansion of the resin. The core layer is sandwiched between the insulating layers containing glass fibers. The insulating layers serve to suppress an increase in the thickness of the core layer resulting from the thermal expansion of the core layer. Thermal stress is suppressed in the core substrate.
1. A core substrate comprising:
a core layer including an electrically-conductive layer made of carbon fibers impregnated with resin and core insulating layers overlaid on front and back surfaces of the electrically-conductive layer, the core insulating layers made of glass fibers impregnated with resin;
a through hole formed in the core layer, the through hole penetrating through the core layer from a front surface of the core layer to a back surface of the core layer;
a cylindrical filling material filling the through hole;
a pair of overlying insulating layers made of glass fibers impregnated with resin, the overlying insulating layers being overlaid on the front and back surfaces of the core layer, respectively, so that the core layer and the cylindrical filling material are sandwiched between the overlying insulating layers;
a through bore formed in and penetrating through at least one of the overlying insulating layers along a longitudinal axis of the through hole; and
an electrically-conductive via formed in a shape of a cylinder along an inward wall surface of the through bore.
2. The core substrate according to claim 1, wherein the overlying insulating layers cover over the filling material.
3. The core substrate according to claim 1, wherein the glass fibers form a woven cloth or a nonwoven cloth.
4. A printed wiring board comprising:
5. The printed wiring board according to claim 4, wherein the overlying insulating layers cover over the filling material.
6. The printed wiring board according to claim 4, wherein the glass fibers form a woven cloth or a nonwoven cloth.
7. The printed wiring board according to claim 4, further comprising a build-up layer overlaid on at least one of the overlying insulating layers. Description
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-143450 filed on May 30, 2008, the entire contents of which are incorporated herein by reference.
The embodiment discussed herein is related to a printed wiring board including a core substrate containing carbon fibers.
A printed wiring board such as a probe card is well known. The probe card is utilized to examine a semiconductor wafer and an LSI (large-scale integrated circuit) chip package, for example. A semiconductor wafer or an LSI chip package is set on the probe card. A high temperature operation test such as a burn-in test, or a low temperature operation test such as screening is executed. The probe card is subjected to a thermal stress such as a change in the temperature, namely a heat cycle. The temperature is forced to change in a range set for the high temperature test or the low temperature test.
The LSI chip includes a silicon substrate, for example. Silicon has a relatively low coefficient of thermal expansion, so that the LSI chip is allowed to have a relatively low coefficient of thermal expansion. On the other hand, the core substrate of the probe card is made of carbon fiber cloth impregnated with a resin material, for example. The carbon fiber cloth serves to reduce the coefficient of thermal expansion of the core substrate. The coefficient of thermal expansion of the probe card can be equalized to that of the LSI chip. The electrically-conductive pads of the probe card can thus be prevented from shifting from the corresponding electrode pins of the LSI chip, respectively, for example.
Through holes are formed in the core substrate of the probe card. A cylindrical large-sized via having a large diameter is formed on the inner wall surface of the individual through hole. A filling material made of a resin material fills an inner space within the large-sized via. A small-diameter through hole is formed to penetrate through the filling material. A cylindrical small-sized via having a diameter smaller than that of the large-sized via is formed on the inner wall surface of the small-diameter through hole. A filling material fills an inner space within the small-sized via. The filling material serves to electrically insulate the small-sized via and the large-sized via from each other. The filling material is made of epoxy resin, for example.
The carbon fiber cloth of the core substrate is a woven or nonwoven cloth, for example. The carbon fiber cloth extends along the front and back surfaces of the core substrate. This results in significant restriction of the thermal expansion of the resin material occurring in the in-plane direction of the core substrate during the heat cycle test, for example. The thermal expansion of the resin material thus tends to cause an increase in the thickness of the core substrate. The thermal expansion induces cracks in the probe card. Such cracks may cause break of an electrically-conductive pattern.
According to a first aspect of the present invention, there is provided a core substrate comprising: a core layer made of carbon fibers impregnated with resin; a through hole formed in the core layer, the through hole penetrating through the core layer from the front surface of the core layer to the back surface of the core layer; a cylindrical filling material filling the through hole; a pair of insulating layers made of glass fibers impregnated with resin, the insulating layers being overlaid on the front and back surfaces of the core layer, respectively, so that the core layer is sandwiched between the insulating layers; a through bore formed in the cylindrical filling material, the through bore penetrating through the core layer along the longitudinal axis of the through bore from one of the insulating layers up to the other of the insulating layers; and an electrically-conductive via formed in a shape of a cylinder along the inward wall surface of the through bore.
According to a second aspect of the invention, there is provided a printed wiring board comprising: a core layer made of carbon fibers impregnated with resin; a through hole formed in the core layer, the through hole penetrating through the core layer from the front surface of the core layer to the back surface of the core layer; a cylindrical filling material filling the through hole; a pair of insulating layers made of glass fibers impregnated with resin, the insulating layers being overlaid on the front and back surfaces of the core layer, respectively, so that the core layer is sandwiched between the insulating layers; a through bore formed in the cylindrical filling material, the through bore penetrating through the core layer along the longitudinal axis of the through bore from one of the insulating layers up to the other of the insulating layers; and an electrically-conductive via formed in a shape of a cylinder along the inward wall surface of the through bore.
FIG. 1 is an enlarged partial sectional view schematically illustrating the sectional structure of a printed wiring board according to an embodiment of the present invention;
FIG. 2 is an enlarged partial sectional view schematically illustrating a process of overlaying prepregs on one another;
FIG. 3 is an enlarged partial sectional view schematically illustrating the process of overlaying the prepregs on one another;
FIG. 4 is an enlarged partial sectional view schematically illustrating a process of forming through holes in a core layer;
FIG. 5 is an enlarged partial sectional view schematically illustrating a process of forming a copper plating layer on the core layer;
FIG. 6 is an enlarged partial sectional view schematically illustrating a process of pouring a resin material into the through holes;
FIG. 7 is an enlarged partial sectional view schematically illustrating a process of overlaying a prepreg and a copper foil on each of the front and back surfaces of the core layer;
FIG. 8 is an enlarged partial sectional view schematically illustrating the process of overlaying the prepreg and the copper foil on each of the front and back surfaces of the core layer;
FIG. 9 is an enlarged partial sectional view schematically illustrating a process of forming through holes in the core layer;
FIG. 10 is an enlarged partial sectional view schematically illustrating a process of forming a copper plating layer;
FIG. 12 is an enlarged partial sectional view schematically illustrating a process of forming electrically-conductive lands;
FIG. 13 is an enlarged partial sectional view schematically illustrating a process of forming an insulating layer on the surface of the core substrate;
FIG. 14 is an enlarged partial sectional view schematically illustrating a process of forming a copper plating layer on the insulating layer; and
FIG. 15 is an enlarged partial sectional view schematically illustrating a process of forming an electrically-conductive pattern on the insulating layer.
Through holes 17 are formed in the core layer 13. The through holes 17 penetrate through the core layer 13 from the front surface to the back surface of the core layer 13. The through holes 17 each define a columnar space. The longitudinal axis of the columnar space is set perpendicular to the front and back surfaces of the core layer 13. The individual through hole 17 defines circular openings on the front and back surfaces of the core layer 13, respectively.
A large-sized via 18 having a large diameter is formed in the individual through hole 17. The large-sized via 18 is electrically conductive. The large-sized via 18 is formed in the shape of a cylinder along the inward wall surface of the through hole 17. The large-sized via 18 is connected to annular electrically-conductive lands 19 on the front and back surfaces of the core layer 13. The electrically-conductive lands 19 extend on the front and back surface of the core layer 13. The large-sized via 18 and the electrically-conductive lands 19 are made of an electrically-conductive material such as copper.
The inner space of the large-sized via 18 in the through hole 17 is filled with a filling material 21 made of a resin material. The filling material 21 takes the form of a cylinder along the inward wall surface of the large-sized via 18. The filling material 21 is a thermosetting resin such as epoxy resin. A ceramic filler is embedded in the epoxy resin, for example.
Through holes 24 are formed in the core substrate 12. The through holes 24 penetrate through the core layer 13 and the insulating layers 22, 23. The individual through hole 24 is located inside the corresponding through hole 17. The through bore 24 penetrates through the corresponding filling material 21. Here, the through holes 24 each define a columnar space. The individual through hole 24 is coaxial with the corresponding through hole 17. The individual through hole 24 defines circular openings on the front and back surfaces of the core substrate 12, respectively.
Build-up layers 28, 29 are formed on the surfaces of the insulating layers 22, 23, respectively. The back surfaces of the build-up layers 28, 29 are received on the surfaces of the insulating layers 22, 23, respectively. The core layer 13 and the insulating layers 22, 23 are sandwiched between the build-up layers 28, 29. The build-up layers 28, 29 cover over the corresponding electrically-conductive lands 26, 26.
The build-up layers 28, 29 are a multilayered structure body including insulating layers 31 and electrically-conductive patterns 32. The insulating layers 31 and the electrically-conductive patterns 32 are alternatively overlaid on one another. Electrical connection is established between the electrically-conductive patterns 32 formed in different layers through vias 33. The insulating layers 31 are made of a thermosetting resin such as epoxy resin. The electrically-conductive patterns 32 and the vias 33 are made of an electrically-conductive material such as copper.
Electrically-conductive pads 34 are exposed on the surfaces of the build-up layers 28, 29. The electrically-conductive pads 34 are made of an electrically-conductive material such as copper. An overcoat layer 35 is overlaid on the surface of each of the build-up layers 28, 29 at positions off the electrically-conductive pads 34. The overcoat layer 35 is made of epoxy resin, for example. The electrically-conductive pads 34 on the back surface of the printed wiring board 11 are connected to the electrode terminals on a probe apparatus, for example. The electrically-conductive pads 34 on the front surface of the printed wiring board 11 are mounted on the electrode bumps of a semiconductor wafer, for example. A heat cycle test is then executed so as to examine the semiconductor wafer, for example.
In the printed wiring board 11, the fibers of the carbon fiber cloth extends in the in-plane direction of the electrically-conductive layer 14. The electrically-conductive layer 14 suffers from an increase in the thickness because of the thermal expansion of the resin material in the electrically-conductive layer 14 during the heat cycle test, for example. The electrically-conductive layer 14 is sandwiched between the insulating layers 22, 23. Since the insulating layers 22, 23 contain glass fiber cloth, the insulating layers 22, 23 have a relatively high strength. The insulating layers 22, 23 thus serve to suppress an increase in the thickness resulting from the thermal expansion of the electrically-conductive layer 14. This results in suppression of thermal stress in the printed wiring board 11. Cracks are thus avoided in the build-up layers 28, 29, for example. Break of the electrically-conductive patterns 32 is avoided. Moreover, the insulating layers 22, 23 cover over the exposed surfaces of the filling material 21, respectively. The insulating layers 22, 23 extend across the boundaries between the electrically-conductive layer 14 and the filling material 21. This results in a significant suppression of generation of cracks along the boundaries between the electrically-conductive layer 14 and the filling material 21. In the case where a printed wiring board does not include the aforementioned insulating layers 22, 23, the electrically-conductive layer 14 suffers from an increase in the thickness of the electrically-conductive layer 14 resulting from the thermal expansion. Cracks can be generated in a build-up layer, for example. Break of an electrically-conductive pattern can be caused.
Next, description will be made on a method of making the printed wiring board 11. The core substrate 12 is first prepared. As shown in FIG. 2, four prepregs 41 are prepared, for example. The individual prepreg 41 contains carbon fiber cloth. Simultaneously, a pair of prepregs 42 is prepared, for example. The individual prepreg 42 contains glass fiber cloth. The carbon fiber cloth is impregnated with epoxy resin varnish for forming the prepregs 41. Likewise, the glass fiber cloth is impregnated with epoxy resin varnish for forming the prepregs 42. The epoxy resin varnish is then dried. The prepregs 41, 42 are in this manner formed.
The prepregs 41 are sandwiched between the prepregs 42, 42. The prepregs 42 are urged against each other while being subjected to a heating process. A vacuum press is employed to urge the prepregs 42, for example. The peak temperature of the heating process and the pressure of the vacuum press are set in accordance with predetermined conditions. The prepregs 41, 42 are bonded together based on the molten epoxy resin. In this manner, the core layer 13 is formed, as shown in FIG. 3. The prepregs 41 provides form the electrically-conductive layer 14. The prepregs 42 form the core insulating layers 15, 16, respectively.
As shown in FIG. 4, the through holes 17 are formed in the core layer 13 at predetermined positions. A drill may be utilized to form the through holes 17, for example. The through holes 17 penetrate through the core layer 13 from the front surface to the back surface of the core layer 13. Electrolytic plating or electroless plating is effected on the entire surface of the core layer 13, for example. A copper plating layer 43 is thus formed over the entire surface of the core layer 13, as shown in FIG. 5. The copper plating layer 43 is formed along the front and back surfaces of the core layer 13 and the inward wall surfaces of the through holes 17 at a predetermined thickness. In this manner, the large-sized vias 18 are formed inside the through holes 17.
As shown in FIG. 6, a resin material 44 is filled in the large-sized vias 18. The resin material 44 is a solvent epoxy resin, for example. The resin material 44 is subjected to a heating process. The resin material 44 is thus hardened or cured. Buffing is employed to remove the resin material 44 overflowing from the large-sized vias 18, for example. A resist film, not shown, is then formed on each of the front and back surfaces of the core layer 13 in a predetermined pattern. Etching is effected on the copper plating layer 43 outside the contour of the resist film. The resist film is removed after the etching. The electrically-conductive lands 19 are thus formed on the front and back surfaces of the core layer 13.
As shown in FIG. 7, a pair of prepregs 45, 45 and a pair of copper foils 46, 46 are prepared. The prepregs 45 have the same structure as that of the aforementioned prepregs 42. The prepreg 45 and the copper foil 46 are in this sequence overlaid on the front and back surfaces of the core layer 13. The copper foils 46 and the prepregs 45 are urged against the front and back surfaces of the core layer 13 while being subjected to a heating process. A vacuum press is employed to urge the copper foils 46 and the prepregs 45. The peak temperature of the heating process and the duration of the vacuum press are set in accordance with predetermined conditions. The prepregs 45 and the copper foils 46 are bonded to the front and back surfaces of the core layer 13, as shown in FIG. 8, based on the molten epoxy resin. The prepregs 45 form the insulating layers 22, 23. The insulating layers 22, 23 cover over the exposed surfaces of the resin material 44 on the front and back surfaces of the core layer 13, respectively.
As shown in FIG. 9, the through holes 24 are formed in the resin material 44 inside the through holes 17 of the core layer 13. The through holes 24 may be coaxial with the corresponding through holes 17. A drill may be utilized to form the through holes 24, for example. The through holes 24 penetrate through the core layer 13 from the front surface to the back surface of the core layer 13. Electrolytic plating or electroless plating is effected on the entire surface of the core layer 13, for example. A copper plating layer 47 is thus formed over the entire surface of the core layer 13, as shown in FIG. 10. The copper plating layer 47 is formed along the front and back surfaces of the core layer 13 and the inward wall surfaces of the through holes 24 at a predetermined thickness. The small-sized vias 25 are in this manner formed inside the through holes 24.
A resin material 48 is filled in the small-sized vias 25. The resin material 48 is a solvent epoxy resin, for example. The resin material 48 is subjected to a heating process. The resin material 48 is thus hardened or cured. Buffing is employed to remove the resin material 48 overflowing from the small-sized vias 25, for example. Electrolytic plating or electroless plating is effected on the entire surface of the core layer 13, for example. In this manner, a copper plating layer 49 is formed on each of the front and back surfaces of the core layer 13, as shown in FIG. 11. The openings of through holes 24 are closed with the copper plating layer 49. A resist film, not shown, is formed on each of the front and back surfaces of the core layer 13 in a predetermined pattern. Etching is effected on the copper plating layer 49 outside the contour of the resist film. The electrically-conductive lands 26 are thus formed on the front and back surfaces of the core layer 13, as shown in FIG. 12. In this manner, the core substrate 12 is formed.
Next, the build-up layers 28, 29 are formed on the front and back surfaces of the core substrate 12, respectively. The build-up layers 28, 29 are simultaneously formed. As shown in FIG. 13, a resin sheet 51 is overlaid on each of the front and back surfaces of the core substrate 12. The resin sheets 51 are urged against the front and back surfaces of the core substrate 12 while being subjected to a heating process. A vacuum press is executed to urge the resin sheets 51. The peak temperature of the heating process and the pressure of the vacuum press are set in accordance with predetermined conditions. The resin sheets 51 are hardened or cured through the heating process. The resin sheets 51 thus provide the insulating layers 31.
A UV-YAG laser is applied to the individual insulating layer 31 at predetermined positions, for example. Holes 52 are thus formed in the insulating layer 31, as shown in FIG. 14. The electrically-conductive lands 26 are exposed at the bottoms of the holes 52, for example. A copper plating layer 53 is formed on the surface of the insulating layer 31 and inside the holes 52. Electroless plating is effected for forming the copper plating layer 53, for example. A resist film, not shown, is formed on the surface of the copper plating layer 53 in a predetermined pattern. Etching is effected on the copper plating layer 53 outside the contour of the resist film. The resist film is then removed. The electrically-conductive pattern 32 is thus formed on the surface of the insulating layer 31, as shown in FIG. 15. The vias 33 are formed in the holes 52.
The process of overlaying the insulating layer 31 and the process of forming the electrically-conductive pattern 32 are repeated. The aforementioned electrically-conductive pads 34 are formed on the uppermost or exposed one of the insulating layers 31 on the front and back surfaces of the core layer 13. An overcoat layer, not shown, is formed on the surface of the uppermost one of the insulating layers 31. The overcoat layer may be made of a resin material, for example. Screen printing or photolithography may be effected for forming the overcoat layer, for example. Openings are formed in the overcoat layer at predetermined positions. The electrically-conductive pads 34 are exposed at the bottoms of the openings. The build-up layers 28, 29 are in this manner formed on the front and back surfaces of the core substrate 12, respectively. The printed wiring board 11 is produced.
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No. 12/390,168.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS20120211270 *Aug 23, 2012Fujitsu LimitedMethod of manufacturing printed wiring board and printed wiring board* Cited by examinerClassifications U.S. Classification174/258International ClassificationH05K1/00Cooperative ClassificationH05K2201/0281, H05K3/4608, H05K2201/09809, H05K2201/0323, H05K2201/09536, Y10T428/24331, H05K3/4641, H05K3/445European ClassificationH05K3/46B8, H05K3/46A4Legal EventsDateCodeEventDescriptionFeb 24, 2009ASAssignmentOwner name: FUJITSU LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YOSHIMURA, HIDEAKI;IIDA, KENJI;ABE, TOMOYUKI;AND OTHERS;SIGNING DATES FROM 20090108 TO 20090121;REEL/FRAME:022298/0766Aug 5, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services