Source: https://www.google.de/patents/US8386972
Timestamp: 2017-11-22 03:49:33
Document Index: 691929079

Matched Legal Cases: ['Application No. 00808458', 'Application No. 00808459', 'Application No. 00808460', 'Application No. 00808462', 'Application No. 200510053551', 'Application No. 200510084318', 'Application No. 00808459', 'Application No. 200510084318', 'Application No. 200510084318', 'Application No. 99958445', 'Application No. 00928970', 'Application No. 00930707', 'Application No. 00930707', 'Application No. 00930707', 'Application No. 00930707', 'Application No. 00930707', 'Application No. 00930715', 'Application No. 00930715', 'Application No. 00930715', 'Application No. 00930715', 'Application No. 99958445', 'Application No. 99958445', 'Application No. 99958445', 'Application No. 99958445', 'Application No. 170671', 'Application No. 142342', 'Application No. 142342', 'Application No. 10', 'Application No. 10', 'Application No. 10']

Patent US8386972 - Method and apparatus for managing the configuration and functionality of a ... - Google Patentsuche
A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of...https://www.google.de/patents/US8386972?utm_source=gb-gplus-sharePatent US8386972 - Method and apparatus for managing the configuration and functionality of a semiconductor design
Veröffentlichungsnummer US8386972 B2
Anmeldenummer US 12/639,911
Auch veröffentlicht unter US6862563, US9171114, US20050149898, US20100299647, US20130152031
Veröffentlichungsnummer 12639911, 639911, US 8386972 B2, US 8386972B2, US-B2-8386972, US8386972 B2, US8386972B2
Erfinder James Robert Howard Hakewill, Mohammed Noshad Khan, Edward Plowman
Patentzitate (102), Nichtpatentzitate (112), Klassifizierungen (9), Juristische Ereignisse (2)
US 8386972 B2
1. A computer-implemented method of producing at least a portion of an integrated circuit design, said design including at least one of a processor or processor peripheral device and a graphical user interface for interacting with a user, the method comprising:
providing the user with an integrated circuit design for the processor or processor peripheral device, the integrated circuit design associated with a hardware description language model;
assigning a set of default design parameters to the hardware description language model associated with the integrated circuit design, the set of design parameters including at least one of a clock parameter, a memory parameter and a cache parameter;
receiving one or more inputs from the user for at least one design parameter for processor or processor peripheral device, for customizing the integrated circuit design to be generated;
automatically generating a customized hardware description language model for the integrated circuit design of the processor or processor peripheral device based on at least one design parameter and the associated hardware description language model, wherein the at least one design parameter includes one of processor cache size, processor cache length, size of external memory space to be cached, clock period and clock skew;
generating test code associated with the customized hardware description language model based at least in part on the at least one design parameter; and
conducting a hardware/software co-verification of said at least a portion of said integrated circuit design by using a debugger to run software on at least a portion of the customized hardware description language model using a hardware description language simulator;
conducting core verification by verifying an integrated circuit synthesized from the customized description language model.
3. The method of claim 2, wherein the integrated circuit is synthesized on a Field Programmable Gate Array.
4. The method of claim 1, wherein the one or more inputs comprises at least one input selected from the group consisting of (i) overall device or system configuration, (ii) width of the external memory system data bus, and (iii) cache type/size.
5. The method of claim 1, wherein generating test code comprises generating configuration register test code.
6. The method of claim 1, wherein generating test code comprises generating test code based at least in part on one or more extensions added to said customized description language model.
7. The method of claim 1, wherein the processor or processor peripheral device comprises a RISC processor, and the hardware description language model comprises a VHDL model.
8. The method of claim 7, further comprising causing a first computer program to write a second computer program adapted to perform a specific task based at least in part on the user inputs.
9. The method of claim 8, further comprising executing the second program to perform the specific task.
10. The method of claim 1, further comprising evaluating the acceptability of the hardware description language model using the test code.
testing the description language through simulation or synthesis using the test code; and
if a different testing outcome is desired, receiving one or more additional inputs from the user and generating a second customized hardware description language model.
This application is a continuation of U.S. patent application Ser. No. 11/067,086, filed on Feb. 25, 2005, which is a continuation of U.S. patent application Ser. No. 09/418,663, filed on Oct. 14, 1999, now U.S. Pat. No. 6,862,563, which claims the benefit of U.S. Provisional Application Ser. No. 60/104,271, filed Oct. 14, 1998. Each of these applications is hereby incorporated in their entirety herein by reference.
FIG. 21 is a logical flowchart illustrating one embodiment of the method 2100 of checking for “in” or “out” signals as shown generally in FIG. 20. For a given block and signal, the signal type is checked in step 2102 to determine whether the signal is an “inout” type; if the signal is not an “inout” type, the algorithm returns to FIG. 20. If it is an “inout” type, the signal's source is checked in step 2104 to determine if it is outside of the block, then whether it has destinations inside the block (step 2106). If both conditions are met, the signal is added to the inout list per step 2108. If either one of the conditions is not met, the signal's source is checked in step 2110 to determine if it is inside of the block; if so, then the destination is checked in step 2112 to determine if it is outside of the block.
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GB2309803A Titel nicht verfügbar
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US-Klassifikation 716/104
Internationale Klassifikation G06F9/318, G06F9/38, G06F17/50, G06F9/32
Unternehmensklassifikation G06F9/30145, G06F17/5045, G06F17/50, G06F17/505