Source: https://patents.google.com/patent/JP2007228589A/en
Timestamp: 2020-02-17 08:01:06
Document Index: 490885729

Matched Legal Cases: ['art 14', 'art 16', 'art 18', 'art 20', 'art 24', 'art 30', 'art 32']

JP2007228589A - Delay locked loop apparatus - Google Patents
Delay locked loop apparatus Download PDF
JP2007228589A
JP2007228589A JP2007043017A JP2007043017A JP2007228589A JP 2007228589 A JP2007228589 A JP 2007228589A JP 2007043017 A JP2007043017 A JP 2007043017A JP 2007043017 A JP2007043017 A JP 2007043017A JP 2007228589 A JP2007228589 A JP 2007228589A
JP2007043017A
Won Joo Yun
元 柱 尹
鉉 雨 李
2006-02-22 Priority to KR20060016986A priority Critical patent/KR100954117B1/en
2007-02-22 Application filed by Hynix Semiconductor Inc, 株式会社ハイニックスセミコンダクターＨｙｎｉｘ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｉｎｃ． filed Critical Hynix Semiconductor Inc
2007-09-06 Publication of JP2007228589A publication Critical patent/JP2007228589A/en
230000000630 rising Effects 0 abstract 7
230000001360 synchronised Effects 0 abstract 2
<P>PROBLEM TO BE SOLVED: To compensate for skew between an external clock and data or between the external clock and an internal clock by adopting single replica-delay unit. <P>SOLUTION: The delay locked loop apparatus includes: delay means delaying a reference clock to generate a rising clock and a falling clock, synchronizing the replica-delayed rising clock with the reference clock and synchronizing the falling clock with the rising clock synchronized with the reference clock; a replica delay unit providing the replica-delayed rising clock; a control means controlling the synchronization of the rising clock and controlling the synchronization of the falling clock; and a DCC output unit transporting the rising clock of the delay mens to the replica-delay unit and generating an output pulse by adjusting the pulse width of the rising clock and the falling clock synchronized with each other by the delay means. <P>COPYRIGHT: (C)2007,JPO&INPIT
The present invention relates to a delay locked loop device, and more particularly, a delay locked loop device embodying a circuit for compensating for a skew between an external clock and data or an external clock and an internal clock by employing a single replica delay unit. It is about.
Generally, a delay locked loop (DLL) is used to perform synchronization between digital signals such as an external clock and data or an external clock and an internal clock in a semiconductor device or a computer system using the clock. .
A conventional DLL device related to this has been disclosed in Japanese Patent Application Laid-Open No. H10-228707.
As described above, the conventional DLL device employs two replica delay units.
That is, the conventional DLL device usually includes a first loop for generating a rising clock and a second loop for generating a falling clock, and feedback is performed through a reference clock and a replica delay unit input through a clock buffer in each loop. The phase difference from the clock is detected by the phase detector, the delay is corrected as a result of the detection, and the clock is locked in the corrected state (Locking).
Normally, a rising clock and a falling clock are applied to the two loops, and the digital DCC synchronizes the rising edges of the two clocks that are opposite in phase to each other.
The concept of the conventional digital DCC is as shown in FIG.
When the clock signals CLK and / CLK are input, a reference clock REF is generated using them. The reference clock REF is delayed by the first loop and converted to the rising rising clock R_CLK, and delayed by the second loop and converted to the falling clock F_CLK. The rising clock R_CLK and the falling clock F_CLK are opposite in phase to each other, but the pulse widths (tck / 2−Δ, tck / 2 + Δ) are other signals. The pulse width is adjusted to half phase blending. Thereby, an output clock CLK_OUT having a duty ratio of 50% is generated.
The conventional DLL circuit described above uses a dual loop, and each loop has a replica delay related configuration. Before the DCC operation, all the two loops are operated. However, after the clock is corrected, after the start of the DCC operation, the replica delay unit included in one loop (the loop corresponding to the falling clock), the phase Replica delay related circuits such as detectors, dummy digital DCC circuits, and dummy loads are not used.
Therefore, the conventional DLL circuit has a problem that unnecessary current consumption occurs due to the presence of an unnecessary circuit after the start of the DCC operation, and the design area is further increased due to the unnecessary circuit.
In addition, the replica delay unit corresponding to the falling clock is turned off, but at this time, instantaneous current is consumed, jitter is generated, and additional locking time (Locking Time) is required. There is a problem.
Korea Patent Publication No. 2004-95981 Specification
An object of the present invention is to provide a delay locked loop device for compensating for a skew between an external clock and data or an external clock and an internal clock using a loop including one replica delay unit.
Another object of the present invention is to reduce the area occupied by the replica delay while reducing the amount of current consumption by applying one replica delay unit.
A further object of the present invention is to suppress instantaneous current consumption by applying one replica delay unit.
Still another object of the present invention is to lock the rising clock by comparing the reference clock and the rising clock in the first loop operation, and to lock the falling clock by comparing the rising clock and the falling clock in the second loop operation. This is to compensate for the skew between the clocks.
A further object of the present invention is to correct the duty in the DCC circuit after the rising clock and falling clock are locked.
The present invention delays the reference clock to generate a rising clock and a falling clock, synchronizes the replica-delayed rising clock with the reference clock, and converts the falling clock into a rising clock synchronized with the reference clock. A delay means for synchronizing; a replica delay unit for delaying the rising clock to provide the replica delayed rising clock; and comparing the phases of the reference clock and the replica delayed rising clock to synchronize the rising clock. Control means for controlling the synchronization of the falling clock by comparing phases of the rising clock synchronized with the reference clock and the falling clock; and the delay The rising clock of the stage is transmitted to the replica delay unit, and the rising clock synchronized with each other by the delay means and the DCC output unit for adjusting the pulse width of the falling clock and generating an output pulse are provided. This is a delay locked loop device characterized by the following.
Here, the delay means delays the reference clock to generate the rising clock, and the first delay means for synchronizing the replica delayed rising clock with the reference clock under the control of the control means, and the reference clock. Second falling means for delaying and generating the falling clock and synchronizing the falling clock with a rising clock synchronized with the reference clock may be provided.
The first delay means delays the reference clock with mutually different delay times, and outputs the first delay signal and the second delay signal, and the first delay signal and the second delay signal are unit units. A first coarse delay unit having a delay time difference within a cell delay time range is synchronized with the reference clock by complementarily adjusting a delay time difference between the first delay signal and the second delay signal. And a first fine delay unit for generating the rising clock.
The second delay means delays the reference clocks with different delay times and outputs the delayed signals to the first delay signal and the second delay signal. The first delay signal and the second delay signal are unit cell units. And a second coarse delay unit having a delay time difference within the delay time range, and the delay time difference between the first delay signal and the second delay signal is complementarily adjusted to synchronize with the rising clock. And a second fine delay unit for generating the falling clock.
Further, the control means detects a phase difference between the reference clock and the replica delayed rising clock and provides a first detection signal, and between the rising clock and the falling clock. A second phase detector for detecting a phase difference of the second phase detector to provide a second detection signal, and a loop for providing a selection signal for a loop currently to be performed based on the first detection signal and the second detection signal A selector, an update enhanced phase detector for detecting a phase difference between the reference clock and the replica delayed rising clock and providing an enhanced detection signal; the first detection signal; the second detection signal; and the enhanced detection An update mode generator for providing an update mode signal based on the signal; It may have a performing controller synchronous control for the object selected on the basis of the Tomodo signal and the selection signal.
The DCC output unit adjusts the pulse width of the rising clock output from the delay means and the falling clock, and outputs the buffered pulse output from the DCC unit. And an output unit.
Here, the DCC unit can provide an output to the replica delay unit.
The present invention converts a reference clock into a rising clock, delays the rising clock in a replica, and then adjusts a delay of the rising clock that is delayed in the replica to adjust the rising edge of the rising clock to the rising edge of the reference clock. A rising clock synchronizing means for synchronizing the rising clock, converting the reference clock into a falling clock, adjusting a delay of the falling clock and adjusting a rising edge of the falling clock at a rising edge of the rising clock synchronized with the reference clock Falling clock synchronization means for synchronizing edges; comparing a phase difference between the reference clock and the replica-delayed rising clock; The phase difference between the rising clock and the falling clock is compared and controlled by the rising clock synchronization means and the falling clock synchronization means, and is synchronized by the rising clock synchronization means. A delay locked loop apparatus comprising: DCC means for generating an output clock using the falling clock synchronized with the rising clock and the falling clock synchronization means to perform DCC.
Here, the rising clock synchronization means delays the reference clock to generate a rising clock, and a first delay means for synchronizing the replica delayed rising clock to the reference clock, and a rising clock provided as the DCC means And a replica delay unit that delays the replica.
Further, the DCC output unit buffers a pulse output from the DCC unit for adjusting and outputting a pulse width between the rising clock output from the first delay means and the falling clock, and a pulse output from the DCC unit. Output unit.
According to the present invention, a delay locked loop device for compensating for a skew between an external clock and data or an external clock and an internal clock using one replica delay unit can be implemented.
Therefore, as compared with the conventional apparatus to which the dual replica delay is applied, unnecessary current consumption can be reduced, and the area occupied by the replica delay is reduced, so that the area is more secured.
In addition, by applying one replica delay unit, instantaneous current consumption is suppressed, so that there is an effect that jitter generation and an additional locking time for solving the jitter are unnecessary.
FIG. 2 is a block diagram showing a delay locked loop device according to the present invention. FIG. 2 includes one replica delay unit.
Specifically, in FIG. 2, the clocks CLK and / CLK are inputted and the clock buffer (10) provided by the reference clock REF and the reference clock REF are sequentially delayed and converted to the rising clock R_CLK. The first coarse delay unit (12) and the first fine delay unit (14) that constitute the first delay unit, and the second delay unit that sequentially delays the reference clock and converts it into a falling clock F_CLK. A second coarse delay section (16) and a second fine delay section (18), and the first and second coarse delay sections (12, 16) and the first and second fine delay sections (14, 18). The control unit (20) for controlling the operation, the replica delay unit (22), and the output of the replica delay unit (22) and the phase of the reference clock are compared to detect the signal. The phase detector (24) that outputs the signal PD1 and the update enhancer phase detector (Update enhancer phase detector) that outputs the enhanced detection signal UPD by comparing the phase of the output of the replica delay unit (22) and the reference clock REF ( 26), an update mode generation unit (Undate) for outputting an update mode signal to the control unit (20) as detection signals PD1 and PD2 (described later) and an enhancement detection signal UPD
mode generator) (28) and outputs (rising clock R_CLK and falling clock F_CLK) of the first fine delay unit (14) and the second fine delay unit (18) are input to adjust the pulse width (DCC unit ( 30) and a phase detector that outputs a detection signal PD2 by comparing the phase difference between the outputs (the rising clock R_CLK and the falling clock F_CLK) of the first fine delay unit (14) and the second fine delay unit (18). 32), a loop selector (34) for providing a loop selection signal to the control unit (20) as detection signals PD1 and PD2 of the phase detector (24, 32), and an output of the DCC unit (30). And an output buffer (40) for buffering and outputting to the output clock CLK_OUT.
In FIG. 2 described above, the rising clock R_CLK is primarily generated by the first coarse delay unit (12) and the first fine delay unit (14), and the rising clock R_CLK is passed through the DCC unit (30) through the replica delay unit ( 22) and the phase of the rising clock R_CLK fed back by the replica delay unit (22) is compared with the reference clock REF by the phase detector (24) and the update enhancement phase detector (26), and the result is the phase. The detection signal PD1 and the enhancement detection signal UPD are detected by the detector (24) and the update enhancement phase detector. The detection signal PD1 and the enhancement detection signal UPD have a logical high or low value, as will be described later, and are output to the update mode generator (28).
Here, the update enhancement phase detector (26) provides the update mode generator (28) with an enhancement detection signal UPD for early control when the phase difference between the reference clock REF and the rising clock R_CLK is large, so that the update mode is generated. The device (28) provides an update mode control signal for controlling the phase of the rising clock R_CLK based on the detection signal PD1 and the enhanced detection signal UPD to the control unit (20), and the control unit (20) thereby provides the first coarse signal. The rising clock R_CLK is locked by controlling the delays of the delay unit (12) and the first fine delay unit (14).
With the above operation, the phase difference between the rising edge of the rising clock R_CLK and the rising edge of the reference clock REF is adjusted to a large value by the first coarse delay unit (12) and finely adjusted by the second coarse delay unit (16). . If the phase difference between the rising edges is large, the update mode generator (28) has an update mode control signal so that the state is detected by the update enhancement phase detector (26). Is supplied to the control unit (20), and the first coarse delay unit (12) is controlled to delay the rising clock R_CLK for a long time.
As described above, when the locking of the rising clock R_CLK is completed, the phase detector 32 detects the phase difference between the rising clock R_CLK and the falling clock F_CLK. The phase detector (32) compares the phase difference between them and provides a detection signal PD2 corresponding to the phase difference to the loop selector (34) and the update mode generator (28).
The loop selector (34) provides a loop selection signal so that the control unit (20) controls the second coarse delay unit (16) and the second fine delay unit (18), and the control unit (20) detects the detection signal. The delay mode of the falling clock F_CLK is adjusted by controlling the delay states of the second coarse delay unit (16) and the second fine delay unit (18) by the update mode control signal of the update mode generation unit (28) referring to the PD2. To do.
By controlling the delay of the falling clock F_CLK as described above, the edge of the falling clock F_CLK is synchronized with the edge of the rising clock R_CLK.
As described above, when the rising clock R_CLK is synchronized with the reference clock REF as a reference, and then the falling clock F_CLK is synchronized with the rising clock R_CLK as a reference, the DCC unit (30) synchronizes the falling clock F_CLK with the rising clock R_CLK. To perform the DCC operation.
At this time, the DCC unit (30) controls the DCC phase detector (36) for comparing the inverted phases of the rising clock R_CLK and the falling clock F_CLK and providing a detection signal for the inverted phase, and the DCC phase detector. The DCC control unit (38) generates a control signal according to the detection signal provided from (36), and the output of the DCC unit (30) is output to the output clock CLK_OUT through the output buffer (40).
As described above, the first coarse delay section (12) and the second coarse delay section (16) are configured as shown in FIG.
Specifically, these coarse delay units are delayed so that the upper delay part that outputs the reference clock REF to the first delay signal DL1 and the reference clock REF corresponds to the delay time of the unit unit cell from the first delay signal DL1. It is divided into lower delay parts to be output to the second delay signal DL2.
The upper delay part includes a shift register (202), a plurality of NAND gates (206, 208, 210), a plurality of unit unit cells (D1, D2, D3), and output of delayed signals. It has a NAND gate (212).
In the above configuration, the shift register (202) receives the shift right control signal UP_SR and the shift left control signal UP_SL from the control unit (20) and outputs the shift signals SL11, SL12,.
The plurality of NAND gates (206, 208, 210) are supplied with a reference clock REF and one shift signal SL11, SL12,... SL1n, respectively, and send NAND operation signals to each unit unit cell (D1, D2, D3). provide.
The unit unit cells (D1, D2, D3) have a delay chain structure, and the output of the first NAND gate enabled by the signal input from the NAND gate (206, 208, 210) is input to the second NAND gate, The second NAND gate has a configuration for inverting it and outputting it.
The delayed signal output from the final end unit cell (D3) is inverted through the NAND gate (212) whose one end is fixed at the high level, and output to the first delayed signal DL1.
The lower delay part includes a shift register (204) that receives the shift right control signal UP_SR and the shift left control signal UP_SL from the control unit (20) and outputs the shift signals SL11, SL12,... SL1n, and a reference clock REF. And a NAND gate (214, 216, 218) that performs NAND operation on the output of the shift register (204), and is enabled by a signal output from the NAND gate (214, 216, 218) It further has a chain of cells (D4, D5, D6). The lower delay part further includes a unit unit cell (D7) between the unit unit cell (D6) and the NAND gate (220) that outputs the second delay signal DL2.
In the first and second coarse delay units (12, 16) having the above-described configuration, the delay is adjusted by the delay unit of the unit unit cell. The first and second coarse delay units (12, 16) One delay signal DL1 and the second delay signal DL2 of the lower delay part have a delay time difference corresponding to the delay time of the unit unit cell because the first and second fine delay units (14 18) to adjust the delay.
Referring to FIG. 4, the first and second fine delay units (14, 18) include a second delay group and an inverter group (IV1) in which a plurality of inverters to which the first delay signal DL1 is input are connected in parallel. A second inverter group (IV2) in which a plurality of inverters to which the signal DL2 is input are connected in parallel; a common output of the first inverter group (IV1) and a common output of the second inverter group (IV2); Is further included as a common input. Here, the number of inverters included in the first inverter group (IV1) and the second inverter group (IV2) is the same, and each inverter is driven by a complementary control signal provided from the control unit (20). The control signals are complementarily input to the first inverter group (IV1) and the second inverter group (IV2).
That is, when a predetermined number of inverters are driven in the first inverter group (IV1), the total number of inverters in the second inverter group (IV2) is the number selected in the first inverter group (IV1). This is selected by driving the number of inverters excluding. Therefore, the delay time of the unit unit cell is divided into the number (n) belonging to each group of the first and second fine delay units (14, 18), and the delay time is divided according to the number of inverters selected. Adjusted to the unit.
On the other hand, the feedback clock FBCLK and the reference clock REF are compared by the update delay phase detector (26) of FIG. 5 by the replica delay unit (22), and a signal corresponding to the result is output.
In FIG. 5, the update enhancement phase detector (26) includes a delay unit (500, 502) for delaying the clock FBCLK fed back after being delayed by the replica delay unit (22) at different times, and a delay unit (500). ), A phase detector (504) that compares the phases of the delayed clock and the reference clock REF, a phase detector (506) that compares the phases of the delayed clock and the reference clock REF of the delay unit (502), and a phase detector ( 506) an inverter (508) for inverting the output, a NAND gate (510) for NANDing the outputs of the phase detector (504) and the inverter (508), and the output of the NAND gate is selectively selected by a DCC enable signal. And an AND gate (512) for outputting the enhancement detection signal UPD.
Here, in the delay unit (500, 502), when the rising edge of the clock FBCLK that is fed back out of a certain range with respect to the rising edge of the reference clock REF is located, an upper limit delay time for detecting this is detected. And the lower limit delay time are applicable.
The output of the NAND gate (510) is tested in a state where the rising edge of the clock FBCLK fed back by the above configuration can be distinguished from the case where the rising edge of the clock FBCLK is located within a certain reference with respect to the rising edge of the reference clock REF. Accordingly, the enhancement detection signal UPD is determined and output.
FIG. 6 illustrates a detailed circuit of the loop selector (34).
When the detection signal PD2 of the phase detector (32) is input to the low-pass filter (600), the low-pass filter (600) outputs a selection signal SEL to the multiplexer (602) when the detection signal PD2 is detected to detect a phase difference. Control is performed to select the output A of the low-pass filter (600). In the opposite case, the multiplexer (602) is set to select the output B of the exclusive OR (618).
The output of the multiplexer (602) is latched by the latch (604), and the signal obtained by inverting the detection signal PD1 by the inverter (608) and the signal obtained by inverting the signal of the latch (604) by the inverter (606) are exclusive. A logical operation is performed by the logical OR (610) and output to the loop selection signal SEL_L.
On the other hand, if the first coarse delay unit (14) and the second delay unit (18) repeatedly perform the phase adjustment in the same direction, the loop selector (34) controls the control signal UP_DOWNNB (n− 1) and the current control signal UP_DOWNNB (n) are logically operated by the exclusive OR (612), and the exclusive OR (612) provides its output to the input stage of the D flip-flop (614). The output of the group (614) is input to the exclusive OR (618). The exclusive OR (618) performs a logical operation on the output of the D flip-flop (616) that inverts the output of the D flip-flop (614) and the output latched by the latch (604) and outputs the result. ) Input B.
Accordingly, the loop selector (34) must perform the current delay (the first coarse delay unit (12) and the first fine delay unit (14) or the second coarse delay unit (16) and the second fine delay). A selection signal is provided for the control unit (20) to select the unit (18)).
On the other hand, the DCC unit (30) can be configured as shown in FIG. 7. In FIG. 7, the DCC unit (30) is connected in parallel to the inverter group (IV71) in which the rising clock R_CLK is input to the inverter connected in parallel. Inverter group (IV72) to which falling clock F_CLK is input to the inverter, inverter (702) to which rising clock R_CLK is input, inverter (704) to which falling clock F_CLK is input, and inverter (702) An inverter (706) to which an output from the inverter (704) is input in common, and an inverter (708) to which a common output from the inverter group (IV71) and the inverter group (IV72) is input in common. (706) and the output of the inverter (708) Is output to the to the output clock CLK_OUT. Here, the inverter group (IV71) and the inverter group (IV72) are configured to be operated in a complementary number by the enable signals EN1, EN2, and EN3 provided from the DCC control unit (38), and the inverter (702). ) And the inverter (704) are also configured to be complementarily operated by an enable signal EN4 provided from the DCC controller (38).
That is, the DCC unit (30) performs the role of adjusting the pulse width by half-blending the falling edges of the rising clock R_CLK and the falling clock F_CLK. This is performed between the inverter group (IV71) and the inverter group (IV72). And half blending between the inverter (702) and the inverter (704). Here, the inverter group (IV71, IV72) adjusts the pulse width, and the inverter (702, 704) plays an auxiliary role.
It is a wave form diagram explaining the concept of general digital DCC. 1 is a block diagram illustrating a preferred embodiment of a delay locked loop device according to the present invention. FIG. FIG. 3 is a circuit diagram illustrating first and second coarse delay units in FIG. 2. FIG. 3 is a circuit diagram illustrating first and second fine delay units in FIG. 2. FIG. 3 is a circuit diagram illustrating the update enhanced phase detector of FIG. 2. FIG. 3 is a circuit diagram illustrating the loop selector of FIG. 2. FIG. 3 is a detailed circuit diagram of a DCC unit in FIG. 2.
DESCRIPTION OF SYMBOLS 10 Clock buffer 12 1st coarse delay part 14 1st fine delay part 16 2nd coarse delay part 18 2nd fine delay part 20 Control part 24 Phase detector 26 Update enhancement phase detector 28 Update mode generation part 30 DCC part 32 Phase Detector 34 Loop selector 36 DCC phase detector 38 DCC control unit 40 Output buffer 202, 204 Shift register 206, 208, 210, 212, 214, 216, 218, 220 NAND gate 300 Inverter 500, 502 Delay unit 504, 506 Phase Detector 508 Inverter 510 NAND gate 512 AND gate 600 Low pass filter 602 Multiplexer 604 Latch 606, 608 Inverter 610, 612, 618 Exclusive OR 614, 616 D flip-flop 702, 704, 706, 708 Inverter D1, D2, D3, D4, D5, D6, D7 Unit unit cell DL1 First delay signal DL2 Second delay signal IN1 First inverter group IN2 Second inverter group IV71, IV72 Inverter group
Delay means for delaying the reference clock to generate a rising clock and a falling clock, synchronizing the replica-delayed rising clock with the reference clock, and synchronizing the falling clock with the rising clock synchronized with the reference clock When,
A replica delay unit for delaying the rising clock and providing the replica-delayed rising clock;
The phase of the reference clock and the replica-delayed rising clock are compared to control the synchronization of the rising clock, and the phase of the rising clock synchronized with the reference clock and the falling clock are compared. Control means for controlling the synchronization of
A DCC output unit for transmitting the rising clock of the delay unit to the replica delay unit, and generating an output pulse by adjusting a pulse width of the rising clock and the falling clock synchronized with each other in the delay unit; A delay locked loop device comprising:
The delay means is
First delay means for delaying the reference clock to generate the rising clock, and synchronizing the replica delayed rising clock with the reference clock under the control of the control means;
2. The delay according to claim 1, further comprising: second delay means for delaying the reference clock to generate the falling clock, and synchronizing the falling clock with a rising clock synchronized with the reference clock. Fixed loop device.
The first delay means includes
The reference clocks are delayed by different delay times and output to the first delay signal and the second delay signal, and the first delay signal and the second delay signal have a delay time difference within the delay time range of the unit unit cell. A first coarse delay unit having
And a first fine delay unit that generates the rising clock synchronized with the reference clock by complementarily adjusting a delay time difference between the first delay signal and the second delay signal. Item 3. The delay locked loop device according to Item 2.
The second delay means includes
The reference clocks are delayed by different delay times and output to the first delay signal and the second delay signal, and the first delay signal and the second delay signal have a delay time difference within the delay time range of the unit unit cell. A second coarse delay unit having
A second fine delay unit that generates the falling clock synchronized with the rising clock by complementarily adjusting a delay time difference between the first delay signal and the second delay signal. The delay locked loop device according to claim 2.
A first phase detector for detecting a phase difference between the reference clock and the replica-delayed rising clock to provide a first detection signal;
A second phase detector for detecting a phase difference between the rising clock and the falling clock and providing a second detection signal;
A loop selector that provides a selection signal for a loop that is currently to be performed based on the first detection signal and the second detection signal;
An update enhanced phase detector that detects a phase difference between the reference clock and the replica delayed rising clock to provide an enhanced detection signal;
An update mode generator for providing an update mode signal based on the first detection signal, the second detection signal, and the enhanced detection signal;
The delay locked loop device according to claim 2, further comprising a control unit that performs synchronization control on a target selected based on the update mode signal and the selection signal.
The DCC output unit includes:
A DCC unit for adjusting and outputting a pulse width of the rising clock output from the delay means and the falling clock;
The delay locked loop device according to claim 1, further comprising: an output unit that buffers and outputs a pulse output from the DCC unit.
The delay locked loop device according to claim 6, wherein the DCC unit provides an output to a replica delay unit.
After the reference clock is converted into a rising clock and the rising clock is replica-delayed, the rising of the rising clock that is delayed by the replica is adjusted to synchronize the rising edge of the rising clock with the rising edge of the reference clock Clock synchronization means;
Falling clock synchronization that converts the reference clock into a falling clock, adjusts the delay of the falling clock, and synchronizes the rising edge of the falling clock with the rising edge of the rising clock synchronized with the reference clock. Means,
Compare the phase difference between the reference clock and the replica delayed rising clock, compare the phase difference between the rising clock synchronized with the reference clock and the falling clock, and compare the rising clock synchronization means with the rising clock Control means for controlling each synchronization operation of the falling clock synchronization means;
DCC means for generating an output clock using the rising clock synchronized by the rising clock synchronization means and the falling clock synchronized by the falling clock synchronization means, and performing DCC. Delay-fixed loop device.
The rising clock synchronization means includes
First delay means for delaying the reference clock to generate a rising clock, and synchronizing the replica-delayed rising clock with the reference clock;
9. The delay locked loop device according to claim 8, further comprising: a replica delay unit that replica-delays the rising clock provided as the DCC means.
9. The delay locked loop apparatus according to claim 8, further comprising a control unit that performs synchronization control on a target selected based on the update mode signal and the selection signal.
A DCC unit for adjusting and outputting a pulse width between the rising clock output from the first delay means and the falling clock;
The delay locked loop device according to claim 9, further comprising: an output unit that buffers and outputs a pulse output from the DCC unit.
The delay locked loop apparatus according to claim 11, wherein the DCC unit provides an output to a replica delay unit.
JP2007043017A 2006-02-22 2007-02-22 Delay locked loop apparatus Pending JP2007228589A (en)
KR20060016986A KR100954117B1 (en) 2006-02-22 2006-02-22 Delay Locked Loop Apparatus
JP2007228589A true JP2007228589A (en) 2007-09-06
ID=38443395
JP2007043017A Pending JP2007228589A (en) 2006-02-22 2007-02-22 Delay locked loop apparatus
US (2) US7830186B2 (en)
JP (1) JP2007228589A (en)
KR (1) KR100954117B1 (en)
JP2009290859A (en) * 2008-05-30 2009-12-10 Hynix Semiconductor Inc Duty cycle correcting circuit and method
US8269534B2 (en) 2009-11-09 2012-09-18 Samsung Electronics Co., Ltd. Delay locked loop circuit and semiconductor device having the delay locked loop circuit
JP2013066229A (en) * 2007-09-28 2013-04-11 Sk Hynix Inc Duty ratio correction circuit
US8836397B2 (en) 2007-09-28 2014-09-16 SK Hynix Inc. Duty cycle ratio correction circuit
JP2016127602A (en) * 2014-12-31 2016-07-11 致茂電子股▲分▼有限公司Ｃｈｒｏｍａ Ａｔｅ Ｉｎｃ． Clock generation device
KR100668852B1 (en) * 2005-06-30 2007-01-16 주식회사 하이닉스반도체 Duty Cycle Correction Device
KR100954117B1 (en) * 2006-02-22 2010-04-23 주식회사 하이닉스반도체 Delay Locked Loop Apparatus
KR100800144B1 (en) * 2006-05-12 2008-02-01 주식회사 하이닉스반도체 Delay locked loop apparatus and delay locked method
KR100837822B1 (en) * 2007-01-10 2008-06-16 주식회사 하이닉스반도체 Dll circuit and method for controlling the same
KR100945793B1 (en) * 2008-04-11 2010-03-08 주식회사 하이닉스반도체 DLL Circuit and Semiconductor Integrated Circuit with the Same
KR100937949B1 (en) * 2008-04-30 2010-01-21 주식회사 하이닉스반도체 Delay locked loop circuit
KR100930415B1 (en) * 2008-05-09 2009-12-08 주식회사 하이닉스반도체 A clock control circuit and a semiconductor memory device including the same
KR100933805B1 (en) * 2008-06-30 2009-12-24 주식회사 하이닉스반도체 Duty cycle correction circuit and delay locked loop circuit including the same
CN101621337B (en) * 2008-06-30 2013-08-07 华为技术有限公司 Delay adjustment device and method
KR20100044625A (en) * 2008-10-22 2010-04-30 삼성전자주식회사 Semiconductor device comprising delay locked loop having periodically activated replica path
KR101094932B1 (en) * 2009-07-01 2011-12-15 주식회사 하이닉스반도체 Delay locked loop circuit
WO2011021313A1 (en) * 2009-08-18 2011-02-24 パナソニック株式会社 Semiconductor integrated circuit
KR101092996B1 (en) * 2009-12-29 2011-12-12 주식회사 하이닉스반도체 Delay locked loop
JP5433432B2 (en) * 2010-01-18 2014-03-05 株式会社日立製作所 Phase frequency comparator and serial transmission device
KR101685630B1 (en) * 2010-03-02 2016-12-13 삼성전자주식회사 DLL having 2-phase delay line and duty correction circuit and duty correction method thereof
KR20120088136A (en) * 2011-01-31 2012-08-08 에스케이하이닉스 주식회사 Synchronization circuit
KR101262322B1 (en) * 2011-12-23 2013-05-09 연세대학교 산학협력단 A delay locked loop
TWI448081B (en) * 2012-01-20 2014-08-01 Nat Univ Chung Cheng All-digital clock correction circuit and method thereof
KR20140012312A (en) * 2012-07-19 2014-02-03 에스케이하이닉스 주식회사 Delay locked loop circuit and method of driving the same
KR102013840B1 (en) 2013-03-15 2019-08-23 삼성전자주식회사 multi-phase generator
US9634678B1 (en) 2016-02-25 2017-04-25 Silicon Laboratories Inc. Feedback control system with rising and falling edge detection and correction
US9584105B1 (en) * 2016-03-10 2017-02-28 Analog Devices, Inc. Timing generator for generating high resolution pulses having arbitrary widths
KR101997988B1 (en) * 2017-11-20 2019-10-17 전자부품연구원 Hybrid Type Transceiver for Broadband Large Area Beamforming
JP2003242779A (en) * 2001-12-12 2003-08-29 Hynix Semiconductor Inc Register controlled relay locked loop circuit
JP2004328721A (en) * 2003-04-29 2004-11-18 Hynix Semiconductor Inc Delay locked loop circuit
JP2004364252A (en) * 2003-05-31 2004-12-24 Hynix Semiconductor Inc Digital delay-locked loop
JP2005018739A (en) * 2003-06-27 2005-01-20 Hynix Semiconductor Inc Delay fixed loop, and clock delay fixation method for delay fixed loop
JP2005135567A (en) * 2003-10-30 2005-05-26 Hynix Semiconductor Inc Delay locked loop and clock generation method therefor
JP2005318520A (en) * 2004-04-27 2005-11-10 Hynix Semiconductor Inc Duty cycle calibrating apparatus for semiconductor memory device and method therefor
US177348A (en) * 1876-05-16 Improvement in hay-elevators
KR100507873B1 (en) * 2003-01-10 2005-08-17 주식회사 하이닉스반도체 Analog delay locked loop having duty correction circuit
KR100605604B1 (en) * 2003-10-29 2006-07-28 주식회사 하이닉스반도체 Delay locked loop and its cotrol method
KR100645461B1 (en) * 2004-06-30 2006-11-15 주식회사 하이닉스반도체 A digital delay locked loop able to correct duty cycle and its cotrol method
JP2006129180A (en) * 2004-10-29 2006-05-18 Elpida Memory Inc Clock delay circuit
DE102005036559B3 (en) * 2005-08-03 2007-01-04 Infineon Technologies Ag Input clock signal synchronizing device, for dynamic RAM, has control devices regulating time delays of clock signals based on phase determined by respective phase comparison devices
KR100711547B1 (en) * 2005-08-29 2007-04-27 주식회사 하이닉스반도체 Delay Locked Loop
KR100800150B1 (en) * 2006-06-30 2008-02-01 주식회사 하이닉스반도체 Delay locked loop apparatus
KR100857436B1 (en) * 2007-01-24 2008-09-10 주식회사 하이닉스반도체 DLL Circuit and Method for Controlling the Same
2006-02-22 KR KR20060016986A patent/KR100954117B1/en not_active IP Right Cessation
2007-02-22 JP JP2007043017A patent/JP2007228589A/en active Pending
2007-02-22 US US11/677,619 patent/US7830186B2/en active Active
2010-09-16 US US12/883,730 patent/US8120397B2/en active Active
US7830186B2 (en) 2010-11-09
US8120397B2 (en) 2012-02-21
KR20070084784A (en) 2007-08-27
US20110074479A1 (en) 2011-03-31
KR100954117B1 (en) 2010-04-23
US20070200604A1 (en) 2007-08-30
KR100477808B1 (en) 2005-03-21 Digital dll apparatus for correcting duty cycle and method thereof
TWI300228B (en) 2008-08-21 Duty cycle correction device
KR100437539B1 (en) 2004-06-26 Clock synchronization circuit
KR100515071B1 (en) 2005-09-16 Delay locked loop device
KR101030275B1 (en) 2011-04-20 Duty cycle correcting circuit and clock correcting circuit including the same
CN1612266B (en) 2010-09-22 Delay locked loop
US5875219A (en) 1999-02-23 Phase delay correction apparatus
US20040119521A1 (en) 2004-06-24 Adaptive frequency clock signal
KR100645461B1 (en) 2006-11-15 A digital delay locked loop able to correct duty cycle and its cotrol method
KR100776906B1 (en) 2007-11-19 Delay locked loop with a function for implementing locking operation periodically during power down mode and locking operation method of the same
KR100477809B1 (en) 2005-03-21 Digital dll apparatus for correcting duty cycle and method thereof
US5969551A (en) 1999-10-19 Clock generator having DLL and semiconductor device having clock generator
US7137022B2 (en) 2006-11-14 Timing adjustment circuit and semiconductor device including the same
US7423462B2 (en) 2008-09-09 Clock capture in clock synchronization circuitry
KR100639616B1 (en) 2006-10-30 Delay locked loop in semiconductor memory device and its clock locking method
JP2006285950A (en) 2006-10-19 Clock duty regulation circuit, delay fixed loop circuit using it, and its method
KR100605577B1 (en) 2006-07-31 Register controlled delay locked loop and its control method
2012-01-18 A131 Notification of reasons for refusal
2012-04-28 RD03 Notification of appointment of power of attorney
2012-10-24 A02 Decision of refusal