Source: http://www.google.com/patents/US7769911?dq=7,346,539
Timestamp: 2016-05-02 20:02:57
Document Index: 262456975

Matched Legal Cases: ['art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 2', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3']

Patent US7769911 - Data reading method and data reading apparatus - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA data reading method includes the steps of: a reading request issuing step of issuing a reading request for reading predetermined stored data; and a reading request re-issuing step of re-issuing a reading request when read data responsive to the reading request has not arrived within a predetermined...http://www.google.com/patents/US7769911?utm_source=gb-gplus-sharePatent US7769911 - Data reading method and data reading apparatusAdvanced Patent SearchPublication numberUS7769911 B2Publication typeGrantApplication numberUS 11/457,483Publication dateAug 3, 2010Priority dateMar 16, 2006Fee statusPaidAlso published asUS20070220178, US20070220179Publication number11457483, 457483, US 7769911 B2, US 7769911B2, US-B2-7769911, US7769911 B2, US7769911B2InventorsYuji Hanaoka, Hidenori MatsumotoOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (28), Non-Patent Citations (2), Classifications (11), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetData reading method and data reading apparatus
US 7769911 B2Abstract
A data reading method includes the steps of: a reading request issuing step of issuing a reading request for reading predetermined stored data; and a reading request re-issuing step of re-issuing a reading request when read data responsive to the reading request has not arrived within a predetermined time period, wherein: in the reading request re-issuing step, a flag is attached to the re-reading request, and thus, the re-reading request is differed from the first issued reading request.
PCI-Express was proposed by Intel Corporation, and creation of a specification thereof has been carried on by PCI-SIG. PCI-Express corresponds to a serial interface known by a name ‘3GIO (3rd generation I/O)’.
According to the PCI-Express interface, an order of read data responsive to respective reading requests is not guaranteed as mentioned above. Therefore, when a reading request is issued again after time out is detected as mentioned above (referred to as ‘retry’ hereinafter), it may not be possible to determine whether the resultant read data is one responsive to the first reading request or one responsive to the second reading request (retry) issued after the time out detection.
The present invention has been devised in consideration of the above-mentioned problem, and, an object of the present invention is to provide a system such that, even an interface such as PCI-Express in which an order of read data responsive to reading requests is not guaranteed, desired read data can be positively identified.
An embodiment of the present invention is described in detail with reference to figures.
FIG. 5 shows one example illustrating functions and operations of DMA engines DE0 through DE3 and queuing buffers (simply referred to as ‘queues’, hereinafter) Q0 through Q3 included in the DMA controller 3 of the central module 10-0.
A queue management part 3 c of the DMA controller 3 receiving it reads the requester ID, tag, address (on this occasion, ‘row address’), byte count and so forth, written in corresponding fields of the header of the completion packet, and compares them with the corresponding information which was written in the queue as mentioned above when the corresponding reading request was issued. Thus, identification is determined. This identification determination means a determination as to whether or not the completion packet is one obtained from the corresponding reading request.
That is, when both the completion packets responsive to the first reading request and responsive to the re-issued reading request are obtained, the queue management part 3 c may not properly recognize the situation. The reason therefor is described now. Generally speaking, the address compared in the above-mentioned identification determination may be simplified in such a manner that, from an original one of 64 bits or 32 bits, only the least 7 bits are extracted partially (the resultant address being referred to as a ‘row address’).
The DMA engine DE0 receiving this return notifies the queue management part 3 c and the request control part 3 b of the address and byte count concerning the reading request (Step S67). The queue management part 3 c receiving it stores, in the queue, the information concerning the reading request thus notified of, and further, the tag of the requester, the DMA engine DE0, i.e., the number ‘0 ’(Step S68).
The DMA engine DE0 receiving this return notifies the queue management part 3 c and the request control part 3 b of the address and byte count concerning the reading request (Step S86). The queue management part 3 c receiving it stores, in the queue, the information concerning the reading request thus notified of, and further, the tag of the requester, the DMA engine DE0, i.e., the number ‘0’ (Step S87). Further, the request control part 3 b issues, to MCH 2, a corresponding reading request (Step S88). In this case, the number of the flag counter of the queue is embedded in the reading request as the flag. The value of the flag is also stored in the queue.
In this case, the flag counter has not yet been incremented yet, and is left as ‘0’. Accordingly, the flag, ‘0’ is embedded. After that, the queue management part 3 c increments the queue's flag counter by one (Step S90). The reading request issued by the request control part 3 b of the DMA controller 3 is received by the DMA receiving part 2 a of MCH 2 (Step S89).
The DMA engine DE0 receiving this return notifies the queue management part 3 c and the request control part 3 b of the address and byte count concerning the reading request (Step S99). The queue management part 3 c receiving it stores, in the queue, the information concerning the reading request thus notified of, and further, the tag of the requester, the DMA engine DE0, i.e., the number ‘0 ’(Step S102). Further, the request control part 3 b issues, to MCH 2, a corresponding reading request (Step S103). In this case, the number of the flag counter of the queue is embedded in the reading request as the flag. The value of the flag is also stored in the queue.
It is noted that the queue's flag counter has already been incremented by one from 0 to 1 in Step S90 when the initial reading request was issued. As a result, the flag embedded in this case is ‘1’ on this occasion. This flag value is stored in the queue as mentioned above. After that, the queue management part 3 c increments the queue's flag counter by one (Step S105).
Here, a case is assumed, for example, in which the completion packet read from the memory 4 responsive to the initial reading request thus having the flag ‘0’ embedded therein, i.e., the completion packet having the same flag ‘0’ embedded therein is at this time returned to the DMA controller, the requester, from MCH 2 (Step S106).
In this case, as mentioned above, the information concerning the reading request initially issued and once stored in the queue such as the flag and so forth was discarded (Step S92). As a result, in the queue, the information such as the flag after the updating due to the above-mentioned re-issuance is stored actually (Step S102). As a result, the completion packet currently obtained which has the flag number ‘0’ as mentioned above responsive to the initial reading request is different from the current updated flag number, and the identification determination results in ‘disagreement’ accordingly. As a result, the completion packet currently obtained is determined as improper, and thus, is then discarded (Step S109).
Next, it is assumed that, after that, the completion packet of the data read out from the memory 4 responsive to the re-issued reading request, i.e., the reading request having the flag ‘1’ embedded therein, which completion packet thus also has the flag ‘1’ accordingly, is returned to the requester, the DMA controller 3, from MCH 2 (Step S106).
In the configuration of FIG. 5, when a reading request is issued by the DMA engine, the DMA arbiter 3 a makes arbitration, and a reading request which has been selected by the arbitration is transferred to the request control part 3 b. The request control part 3 b receives it, checks the current used states of the queues, and assigns a spare queue therefor. In the example of FIG. 12, all the queues are not used, i.e., are spare. In this case, ‘queue not used occasion’ operation, described later, is carried out.
Further, when reading requests are received by the request control part successively in this state, ‘successive request receiving occasion’ operation, also described later, is carried out. FIG. 12 shows a state of the above-mentioned queues and flag counters in an initial state before any reading request has come.
The above-mentioned ‘queue not used occasion’ operation is described first with reference to FIGS. 13 through 18.
Further, the request control part 3 b generates a reading request in which the information concerning the reading request received from the DMA engine and the value ‘0’ of the flag counter C0 before the incrementing are embedded, and issues the same to MCH 2 (Step S130). The same is received by MCH 2 (Step S131).
Next, the above-mentioned ‘successive request receiving occasion’ operation will now be described with reference to FIGS. 19 through 27.
Also in this case, operation the same as that described above for the initial reading request issuance (Steps S181 through S200 of FIGS. 24 through 25) is carried out. However, in this case, the queue Q0 is already in the used state (FIG. 19), and thus, the queue having the smallest number from among the remaining spare ones, i.e., the queue Q1 is assigned (Step S192). Then, after this second reading request issuance, the corresponding flag counter C1 is incremented into 1 (FIG. 20) (Step S200). In this case, the value of the flag counter C1 corresponding to the currently assigned queue Q1 had not been incremented and was ‘0’ when the corresponding reading request was issued (Step S190), and thus, this value ‘0’ is embedded in this reading request.
Also in this case, operation the same as that described above for the initial reading request issuance is carried out (Steps S201 through S220 of FIGS. 25 through 26). However, in this case, the queues Q0 and Q1 are already in the used states (FIG. 20), and thus, the queue having the smallest number from among the remaining spare ones, i.e., the queue Q2 is assigned (Step S212). Then, after this third reading request issuance, the corresponding flag counter C2 is incremented into 1 (Step S220). In this case, the value of the flag counter C2 corresponding to the currently assigned queue Q2 had not been incremented and was ‘0’ when the corresponding reading request was issued (Step S210), this value ‘0’ is embedded in this reading request.
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