Source: http://www.freepatentsonline.com/8997099.html
Timestamp: 2018-09-21 21:20:04
Document Index: 319827224

Matched Legal Cases: ['Application No. 2006', 'Application No. 2006', 'Application No. 06253930', 'Application No. 95124380', 'Application No. 2010', 'Application No. 2011', 'Application No. 2012']

Virtualization event processing in a layered virtualization architecture - Intel Corporation
Virtualization event processing in a layered virtualization architecture
United States Patent 8997099
Bennett, Steven M. (Hilsboro, OR, US)
Anderson, Andrew V. (Hilsboro, OR, US)
Rodgers, Dion (Hillsboro, OR, US)
Smith, Lawrence O. (Beaverton, OR, US)
Huntley, Barry E. (Hillsboro, OR, US)
13/837737
703/13, 703/20, 703/21, 703/22, 710/260, 710/261, 710/262, 710/263, 710/264, 712/244, 719/318
G06F9/455; G06F9/38; G06F9/44; G06F9/48; G06F13/00; G06F13/12; G06F13/24
Download PDF 8997099 PDF help
7191440 Tracking operating system process and thread execution and virtual machine execution in hardware or in a virtual machine monitor 2007-03-13 Cota-Robles et al.
20060206892 Systems and methods for multi-level intercept processing in a virtual machine environment 2006-09-14 Vega et al.
20050081199 Systems and methods for using synthetic instructions in a virtual machine 2005-04-14 Traut
20050080965 Mechanism to control hardware interrupt acknowledgement in a virtual machine system 2005-04-14 Bennett et al.
20050071840 Use of multiple virtual machine monitors to handle privileged events 2005-03-31 Neiger et al.
20040003324 Handling faults associated with operation of guest software in the virtual-machine architecture 2004-01-01 Uhlig et al.
20030037089 Tracking operating system process and thread execution and virtual machine execution in hardware or in a virtual machine monitor 2003-02-20 Cota-Robles et al.
20020082824 Virtual translation lookaside buffer 2002-06-27 Neiger et al.
4253145 Hardware virtualizer for supporting recursive virtual computer systems on a host computer system 1981-02-24 Goldberg
JP2002041305A 2002-02-08 ALLOCATING METHOD OF COMPUTER RESOURCE IN VIRTUAL COMPUTER SYSTEM, AND VIRTUAL COMPUTER SYSTEM
JP2007505402A 2007-03-08
TW502162B 2002-09-11 Method and system for device virtualization based on an interrupt request in a dos-based environment
TW200403586A 2004-03-01
WO2004061645A2 2004-07-22 METHODS AND SYSTEMS TO CONTROL VIRTUAL MACHINES
WO2005029326A1 2005-03-31 USE OF MULTIPLE VIRTUAL MACHINE MONITORS TO HANDLE PRIVILEGED EVENTS
WO2005033937A1 2005-04-14 MECHANISM TO CONTROL HARDWARE INTERRUPT ACKNOWLEDGEMENT IN A VIRTUAL MACHINE SYSTEM
Goldberg, “Survey of Virtual Machine Research”, IEEE Computer, vol. 7, No. 6, Jun. 1974, pp. 34-45.
Office Action received for Japanese Patent Application No. 2006-203447, mailed on Jan. 20, 2009, 6 pages of Japanese Office Action and 3 pages of English translation.
Office Action received for Japanese Patent Application No. 2006-203447, mailed on Jul. 19, 2011, 21 pages of Japanese Office Action and 6 pages of English translation.
Office Action received for European Patent Application No. 06253930.9, mailed on Sep. 5, 2007, 6 pages.
Office Action received for Taiwan Patent Application No. 95124380, mailed on Apr. 19, 2010, 12 pages of Taiwan Office Action and 6 pages of English translation.
Office Action received for Japanese Patent Divisional Application No. 2010-047518, mailed on Jul. 3, 2012, 4 pages of Japanese Office Action and 2 pages of English translation.
Office Action received for Japanese Patent Divisional Application No. 2011-263341, mailed on Apr. 23, 2013, 6 pages of Japanese Office Action and 3 pages of English translation.
Office Action received for Japanese Patent Divisional Application No. 2012-219381, mailed on Sep. 10, 2013, 3 pages of Japanese Office Action and 3 pages of English translation.
This application is a continuation of U.S. patent application Ser. No. 13/595,838, filed Aug. 27, 2012, which is a continuation of U.S. patent application Ser. No. 13/590,001, filed Aug. 20, 2012, which is a continuation of U.S. patent application Ser. No. 12/858,461, filed Aug. 18, 2010 and issued as U.S. Pat. No. 8,271,978, which is a continuation of U.S. patent application Ser. No. 11/191,827, which was filed on Jul. 27, 2005.
1. A processor, comprising: an instruction decode logic to decode instructions; and an execution unit to execute the instructions, wherein execution of at least one instruction is to cause an interrupt; a first logic to determine whether the interrupt is a top-down virtualization event or a bottom-up virtualization event; a second logic to determine whether to transfer control of the processor from a first child guest to an intervening virtual machine monitor hosting the first child guest in response to the recognized virtualization event, by checking, if the virtualization event is recognized as a top-down virtualization event, a control structure of the first child guest before checking a control structure of the intervening virtual machine monitor hosting the first child guest, and by checking, if the virtualization event is recognized as a bottom-up virtualization event, the control structure of the intervening virtual machine monitor hosting the first child guest before checking the control structure of the first child guest.
2. The processor as in claim 1 wherein the interrupt is responsive to the guest attempting to access a privileged resource.
Guest 240 is itself a VMM, with two children, guests 250 and 260, each with a VMCS, 251 and 261, respectively. Both parent pointer 252 and parent pointer 262 point to VMCS 241.
// guest state in the walk VMCS.
// operating VM, starting at the VMCS pointed to by the child pointer of
the root-VMCS,
// Start with the lowest controlling VMCS above the root-VMCS. walk
// is initialized to the root-VMCS and it will be bumped at the top of
// Either (1) the root-VMM is running or (2) no VMM wants control on
<- Previous Patent (Hypervisor-based ser...) | Next Patent (Systems and method f...) ->