Source: http://www.google.com/patents/US7133940?dq=7350717
Timestamp: 2017-03-29 21:11:37
Document Index: 439801829

Matched Legal Cases: ['§120', '§120', '§ 119', '§120', '§ 119', '§120', '§120', '§1']

Patent US7133940 - Network interface device employing a DMA command queue - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA network interface device couples a host computer to a network. The network interface device includes a processor and a DMA controller. The processor causes the DMA controller to perform multiple DMA commands before the processor takes a particular software branch. The processor issues the DMA commands...http://www.google.com/patents/US7133940?utm_source=gb-gplus-sharePatent US7133940 - Network interface device employing a DMA command queueAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7133940 B2Publication typeGrantApplication numberUS 09/855,979Publication dateNov 7, 2006Filing dateMay 14, 2001Priority dateOct 14, 1997Fee statusPaidAlso published asUS20010021949Publication number09855979, 855979, US 7133940 B2, US 7133940B2, US-B2-7133940, US7133940 B2, US7133940B2InventorsStephen E. J. Blightman, Daryl D. Starr, Clive M. PhilbrickOriginal AssigneeAlacritech, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (104), Non-Patent Citations (74), Referenced by (90), Classifications (36), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetNetwork interface device employing a DMA command queue
US 7133940 B2Abstract
means for maintaining a DMA command queue and a DMA command complete queue on a network interface device and for causing values to be pushed onto the DMA command queue and for causing values to be popped from the DMA command complete queue, each of the values pushed onto the DMA command queue being indicative of one of a plurality of DMA commands; and
a DMA controller that executes the plurality of DMA commands such that the DMA commands are completed in a particular order, the DMA controller pushing values onto the DMA command complete queue, each of the values pushed onto the DMA command complete queue indicating completion of one of the plurality of DMA commands.
2. The apparatus of claim 1, wherein the means comprises a processor.
3. The apparatus of claim 1, wherein the means further comprises a hardware queue manager.
4. A network interface device, comprising:
queue manager hardware that maintains a DMA command queue and a DMA command complete queue;
a processor coupled to the queue manager hardware, the processor causing values to be pushed onto the DMA command queue, the processor causing values to be popped from the DMA command complete queue;
a DMA controller coupled to the queue manager hardware, the DMA controller executing DMA commands, the DMA commands executed being indicated by values popped off the DMA command queue, the DMA controller pushing values onto the DMA command complete queue;
5. The network interface device of claim 4, wherein the local memory is dynamic random access memory (DRAM).
6. The network interface device of claim 5, wherein the queue manager hardware stores at least part of the DMA command queue and the DMA command complete queue in static random access memory (SRAM).
(a) pushing values onto a DMA command queue in an order, each of the values being indicative of a different one of a plurality of DMA commands, wherein the DMA command queue is maintained on a network interface device (NID), and wherein the NID performs fast-path transport and network layer protocol processing;
(b) popping the DMA command queue such that a DMA controller on the NID executes the plurality of DMA commands in the order in which the associated values were pushed onto the DMA command queue, the DMA controller being a part of the NID;
(c) the DMA controller pushing values onto a DMA command complete queue, each of the values pushed onto the DMA command complete queue indicating completion of one of the plurality of DMA commands; and
(d) popping the DMA command complete queue.
8. The method of claim 7, wherein the NID includes a first memory and a second memory, the method further comprising:
(e) receiving multiple frames of a session layer network message onto the NID and storing the frames in the first memory, wherein execution of one of the plurality of DMA commands in (b) results in a move of at least a part of one of the frames from the first memory to the second memory, and wherein execution of another of the plurality of DMA commands in (b) results in a move of at least a part of another of the frames from the first memory to the second memory.
9. The method of claim 7, wherein the NID is integrated into an integrated circuit taken from the group consisting of: a memory controller integrated circuit, a graphics controller integrated circuit, an input/output integrated circuit, and a bridge integrated circuit, and wherein the integrated circuit of which the NID is a part is realized on a motherboard of a host computer.
10. The method of claim 8, wherein the DMA command complete queue is used to determine that the at least a part of one of the frames and the at least a part of another of the frames are both present in the second memory.
(b) outputting at least part of the information from the network interface device, wherein a first of the plurality of DMA moves is a move of at least a part of a frame of a session layer message, and wherein a second of the plurality of DMA moves is a move of at least a part of a subsequent frame of the session layer message, wherein a processor pushes values onto the DMA command queue, each of the values being indicative of a different DMA command, and wherein the processor analyzes at least a part of the information moved in the first move, the processor doing the analyzing after the first move is complete.
12. The method of claim 11, wherein said one location on the network interface device is a dynamic random access memory (DRAM) and wherein said another location on the network interface device is a static random access memory (SRAM), wherein the first move is a move of information from a first buffer in the DRAM to a first buffer in the SRAM, and wherein the second move is a move of information from a second buffer in the DRAM to a second buffer in the SRAM.
13. The method of claim 11, wherein the processor does the analyzing before the second move is complete.
(a) using a DMA command queue to ensure that a plurality of DMA moves are completed in a particular sequence, each of the DMA moves being a move of information from one location on a network interface device to another location on the network interface device, the DMA command queue being maintained by queue manager hardware on the network interface device, the DMA moves being carried out by a DMA controller, the DMA controller being a part of the network interface device;
(b) the DMA controller pushing values onto a DMA command complete queue, each value indicating that one of the DMA moves has been carried out by the DMA controller;
(c) a processor on the network interface device popping values off the DMA command complete queue; and
(d) outputting at least part of the information from the network interface device.
15. The method of claim 14, wherein the information output in (b) is output from the network interface device to a host computer, the host computer being coupled to the network interace device.
16. The method of claim 14, wherein the information output in (b) is output from the network interface device to a network.
17. The method of claim 14, wherein a first of the plurality of DMA moves is a move of at least a part of a frame of a session layer message, and wherein a second of the plurality of DMA moves is a move of at least a part of a subsequent frame of the session layer message.
(e) after both the first portion and the second portion are present in the local memory, outputting the first and second portions of data from the network interface device to a network, the first and second portions making up at least a part of a data payload of a network communication, wherein the pushing of (b) occurs twice before the popping of (c) occurs once.
(d) repeating (b) and (c) such that a first portion of data is transferred from host storage to a local memory on the network interface device and such that a second portion of data is transferred from the host storage to the local memory on the network interface device;
(e) maintaining a DMA command complete queue on the network interface device, the DMA controller pushing values onto the DMA command complete queue, the processor popping values off the DMA command complete queue; and
(f) after both the first portion and the second portion are present in the local memory, outputting the first and second portions of data from the network interface device to a network, the first and second portions making up at least a part of a data payload of a network communication.
20. The method of claim 19, wherein the processor uses the DMA command complete queue to determine that the first and the second portions of data are both present in local memory on the network interface device.
21. The method of claim 19, wherein the network interface device comprises queue manager hardware, the queue manager hardware maintaining the DMA command queue and the DMA command complete queue in static random access memory (SRAM), wherein the processor, the queue manager hardware, the SRAM, and the DMA controller are all part of the same integrated circuit.
22. The method of claim 19, wherein each of the values on the DMA command queue is a DMA command.
23. The method of claim 19, wherein each of the values on the DMA command queue comprises a pointer to a DMA command.
24. The method of claim 19, wherein each of the values on the DMA command queue is a number that identifies a location where a DMA command is stored.
25. The method of claim 19, wherein the network interface device is an expansion card coupled to a host computer, the host storage being part of the host computer.
26. The method of claim 19, wherein the network interface device is a part of a host computer.
(d) repeating (b) and (c) such that a first portion of data is transferred from a first place on the network interface device to a second place on the network interface device, and such that a second portion of data is transferred from the first place on the network interface device to the second place on the network interface device;
(e) maintaining a DMA command complete queue on the network interface device, the DMA controller pushing values onto the DMA command complete queue, the processor popping values off the DMA command complete queue;
(f) after both the first portion and the second portion have been transferred to the second place in (d), the processor taking a software branch; and
(g) after taking the software branch, the processor outputting the first and second portions of data from the network interface device.
28. The method of claim 27, wherein the processor outputs the first and second portions of data in (f) to a network.
29. The method of claim 27, wherein the processor outputs the first and second portions of data in (f) to a host computer.
30. The method of claim 27, wherein the first place is a dynamic random access memory (DRAM) and wherein the second place is a bus interface.
31. The method of claim 27, wherein the first place is a bus interface and wherein the second place is a dynamic random access memory (DRAM).
32. The method of claim 27, wherein the first place is a bus interface and wherein the second place is a static random access memory (SRAM).
33. The method of claim 27, wherein the first place is a static random access memory (SRAM) and wherein the second place is a bus interface.
This application is a continuation of and claims the benefit under 35 U.S.C. §120 of U.S. patent application Ser. No. 09/464,283, filed Dec. 15, 1999, by Laurence B. Boucher et al., now U.S. Pat. No. 6,427,173, which in turn is a continuation of and claims the benefit under 35 U.S.C. §120 of U.S. patent application Ser. No. 09/439,603, filed Nov. 12, 1999, by Laurence B. Boucher et al., now U.S. Pat. No. 6,247,060, which in turn claims the benefit under 35 U.S.C. § 119(e)(1) of the Provisional Application Ser. No. 60/061,809, filed on Oct. 14, 1997. This application also is a continuation of and claims the benefit under 35 U.S.C. §120 of U.S. patent application Ser. No. 09/384,792, filed Aug. 27, 1999, now U.S. Pat. No. 6,434,620, which in turn claims the benefit under 35 U.S.C. § 119(e)(1) of the Provisional Application Ser. No. 60/098,296, filed Aug. 27, 1998.
This application also is a continuation of and claims the benefit under 35 U.S.C. §120 of U.S. patent application Ser. No. 09/067,544, filed Apr. 27, 1998, now U.S. Pat. No. 6,226,680. This application also is a continuation of and claims the benefit under 35 U.S.C. §120 of U.S. patent application Ser. No. 09/416,925, filed Oct. 13, 1999, now U.S. Pat. No. 6,470,415. The subject matter of all the above-identified patent applications, and of the two above-identified provisional applications, is incorporated by reference herein.
FIG. 1 (Prior Art) is a diagram of a network interface device (NID) 100 that couples a host computer 101 to a network 102. The particular NID 100 of FIG. 1 is an expansion card that is coupled to host computer 101 via PCI bus 103. NID 100 includes an integrated circuit 104, physical layer interface circuitry 105, and dynamic random access memory (DRAM) 106. Integrated circuit 104 includes a media access controller 107, queue manager hardware 108, a processor 109, sequencers 110, an SRAM controller 111, static random access memory (SRAM) 112, a DRAM controller 113, a PCI bus interface 114, a DMA controller 115, a DMA command register 116, and a DMA command complete register 117. For additional detail on one such integrated circuit 104, see U.S. patent application Ser. No. 09/464,283, filed Dec. 15, 1999 (the subject matter of which is incorporated herein by reference).
In one example, NID 100 is used to retrieve three portions of data 118–120 from host storage 121 and to output them to network 102 in the form of a data payload of a packet. In the situation where the three portions 118–120 are stored on different pages in host storage 121, it may be necessary to move the data to DRAM 106 individually. The three portions 118–120 are to all be present in DRAM 106 before packet transmission begins.
In the example of FIG. 1, each of the three data portions 118–120 is moved into DRAM 106 in two moves. In a first move, the data is moved from host storage 121 and to a buffer in SRAM 112. In a second move, the data is moved from the buffer in SRAM 112 and to DRAM 106.
To move the first portion of data 118 from host storage 121 to DRAM 106, processor 109 writes a DMA command into SRAM 112. DMA controller 115 retrieves the DMA command from SRAM 112 via SRAM controller 111 and lines 124. DMA controller 115 then executes the command by sending a request to PCI bus interface 114 via lines 125. PCI bus interface 114 responds by retrieving data 118 from a particular address X1 and supplying that data to SRAM controller 111 via lines 126. PCI bus interface 114 reports completion of this action by returning an acknowledge signal to DMA controller 115 via line 127. SRAM controller 111 writes the data into the buffer in SRAM 112. DMA controller 115 then issues a request to DRAM controller 113 via lines 128. Data from SRAM 112 is then transferred via SRAM controller 111, lines 129, and DRAM controller 113 to a location 130 (address Z1) in DRAM 106. When this action is complete, DRAM controller 113 returns an acknowledge signal to DMA controller 115 via line 131. DMA controller 115 sets a bit corresponding to this completed DMA command in the DMA command complete register 117. In this way, each of the three portions of data 118–120 is moved through SRAM 112 and into DRAM 106. Although the three data portions are illustrated being stored in DRAM 106 at different locations Z1, Z2 and Z3, this need not be the case. All three data portions are sometimes stored in one continuous block.
In the particular NID 100 of FIG. 1, DMA controller 115 may execute DMA commands in an order different from the order in which the DMA commands were placed in SRAM 112 by processor 109. For example, while DMA controller 115 is moving the first portion 118 to DRAM 106, the processor 109 may place additional DMA commands into SRAM 112. When DMA controller 115 finishes moving first portion 118, the DMA controller 115 may fetch a DMA command to move the third portion 120 next. Because all three data portions 118–120 are to be in DRAM 106 before transmission of the packet begins, processor 109 cannot only check that the last move in the sequence is completed. Rather, processor 109 must check to make sure that all the moves are completed before processor 109 goes on in its software to execute the instructions that cause the ultimate packet to be formed and output from NID 100.
FIG. 1 (Prior Art) is a simplified diagram of one particular prior art network interface device.
FIG. 2 is a diagram of a network interface device (NID) in accordance with one embodiment of the present invention.
FIG. 3 is a flowchart of a method in accordance with one embodiment of the present invention.
FIG. 2 is a diagram of a network interface device 200 in accordance with one embodiment of the present invention. Network interface device 200, in this example, is an intelligent network interface card (INIC) that is used to couple host computer 201 to a network 202. The network interface device (NID) 200 is coupled to host computer 201 via bus 203. Bus 203 in this example is a PCI bus.
In one example, processor 210 proceeds down a software thread whereby a first portion of data 219 (at address X1) and a second portion of data 220 (at address X2) respectively in host storage 204 are to be moved into local memory 207 to locations Z1 and Z2, respectively. Only after both of the data portions 219–220 are present in local memory 207 does the software executed by processor 210 branch into the instructions that cause the two data portions to be output from the network interface device 200. After the branch, the two data portions 219 and 220 are output in the form of a data payload (or a portion of a data payload) of a network communication such as a TCP/IP packet. The network communication is output via media access control circuitry 208 and physical layer interface circuitry 205.
FIG. 3 is a flow chart that illustrates a method in accordance with an embodiment of the invention. Processor 210, as it proceeds down the thread, places a set of multiple (in this case two) DMA commands into SRAM 213. The first DMA command is to move first portion of data 219 from address X1 in host storage 204 to address Z1 in local memory 207. After placing the first DMA command into SRAM 213 via lines 222 and SRAM controller 212, processor 210 causes a value that points to the first DMA command in SRAM 213 to be pushed (step 300) onto DMA command queue 217. Processor 210 does this by first writing a queue identifier into a queue control register (not shown) in queue manager 209. This queue identifier indicates the queue onto which a subsequently written 32-bit queue data value is to be pushed. Processor 210 then writes a 32-bit queue data value onto a queue data register (not shown) in queue manager 209. The 32-bit queue data value contains: a 16-bit address where the DMA command is located in SRAM 213, a 5-bit termination queue identifier, an 8-bit termination value to be pushed onto the queue identified by the termination queue identifier upon completion of the DMA command, a one-bit DMA chain bit value, a one-bit dummy DMA value, and one unused bit. If the DMA chain bit is set, this indicates that when the DMA controller has completed the DMA command, that the DMA controller is not to push a termination value onto any queue. If the dummy DMA bit is set, this indicates that the DMA controller is not to perform a DMA command per se but is nevertheless to push the 8-bit termination value onto the queue identified by the 5-bit termination queue identifier.
Only after both portions of data 219 and 220 are present on the network interface device 200, does processor 210 branch to the instructions that cause the data of portions 219 and 220 to be output from the network interface device in the form of a data payload of a network communcation. To ensure that all of the necessary data portions have been moved to the network interface device 200, processor 210 need not monitor the complete status of all the DMA commands involved as in the prior art example of FIG. 1. Rather, processor 210 polls a 32-bit queue-out-ready register (not shown) in queue manager 209. Each bit in the queue-out-ready register indicates whether there is a value present in a corresponding queue. Processor 210 therefore polls the queue-out-ready register, determines that the bit for the DMA command complete queue is set, and then pops the DMA command complete queue 218. Processor 210 repeats this process until the value popped off the DMA command complete queue 218 is the value indicative of the last DMA command in the set of DMA commands. When the value popped off the DMA command complete queue is the value indicative of the last DMA command in the set of DMA commands, then it is known that all the proceeding DMA commands in the set have been executed.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4366538Oct 31, 1980Dec 28, 1982Honeywell Information Systems Inc.Memory controller with queue control apparatusUS4589063Aug 4, 1983May 13, 1986Fortune Systems CorporationData processing system having automatic configurationUS4991133Oct 7, 1988Feb 5, 1991International Business Machines Corp.Specialized communications processor for layered protocolsUS5056058Mar 5, 1990Oct 8, 1991Hitachi, Ltd.Communication protocol for predicting communication frame type in high-speed processing systemUS5058110May 3, 1989Oct 15, 1991Ultra Network TechnologiesProtocol processorUS5097442Jan 21, 1988Mar 17, 1992Texas Instruments IncorporatedProgrammable depth first-in, first-out memoryUS5163131Sep 8, 1989Nov 10, 1992Auspex Systems, Inc.Parallel i/o network file server architectureUS5212778May 27, 1988May 18, 1993Massachusetts Institute Of TechnologyMessage-driven processor in a concurrent computerUS5280477Aug 17, 1992Jan 18, 1994E-Systems, Inc.Network synchronous data distribution systemUS5289580May 10, 1991Feb 22, 1994Unisys CorporationProgrammable multiple I/O interface controllerUS5303344Feb 25, 1991Apr 12, 1994Hitachi, Ltd.Protocol processing apparatus for use in interfacing network connected computer systems utilizing separate paths for control information and data transferUS5412782Jul 2, 1992May 2, 19953Com CorporationProgrammed I/O ethernet adapter with early interrupts for accelerating data transferUS5418912Oct 18, 1993May 23, 1995International Business Machines CorporationSystem and method for controlling buffer transmission of data packets by limiting buffered data packets in a communication sessionUS5448566Nov 15, 1993Sep 5, 1995International Business Machines CorporationMethod and apparatus for facilitating communication in a multilayer communication architecture via a dynamic communication channelUS5485579Apr 8, 1994Jan 16, 1996Auspex Systems, Inc.Multiple facility operating system architectureUS5506966Nov 5, 1992Apr 9, 1996Nec CorporationSystem for message traffic control utilizing prioritized message chaining for queueing control ensuring transmission/reception of high priority messagesUS5511169Jan 25, 1993Apr 23, 1996Mitsubishi Denki Kabushiki KaishaData transmission apparatus and a communication path management method thereforUS5517668Jan 10, 1994May 14, 1996Amdahl CorporationDistributed protocol frameworkUS5524250Dec 23, 1994Jun 4, 1996Silicon Graphics, Inc.Central processing unit for processing a plurality of threads using dedicated general purpose registers and masque register for providing access to the registersUS5535375Oct 11, 1994Jul 9, 1996International Business Machines CorporationFile manager for files shared by heterogeneous clientsUS5548730Sep 20, 1994Aug 20, 1996Intel CorporationIntelligent bus bridge for input/output subsystems in a computer systemUS5566170Dec 29, 1994Oct 15, 1996Storage Technology CorporationMethod and apparatus for accelerated packet forwardingUS5588121May 9, 1996Dec 24, 1996International Computers LimitedParallel computer having MAC-relay layer snooped transport header to determine if a message should be routed directly to transport layer depending on its destinationUS5590328Mar 6, 1995Dec 31, 1996Mitsubishi Denki Kabushiki KaishaProtocol parallel processing apparatus having a plurality of CPUs allocated to process hierarchical protocolsUS5592622May 10, 1995Jan 7, 19973Com CorporationNetwork intermediate system with message passing architectureUS5598410Dec 29, 1994Jan 28, 1997Storage Technology CorporationMethod and apparatus for accelerated packet processingUS5619650Sep 21, 1995Apr 8, 1997International Business Machines CorporationNetwork processor for transforming a message transported from an I/O channel to a network by adding a message identifier and then converting the messageUS5629933Jun 7, 1995May 13, 1997International Business Machines CorporationMethod and system for enhanced communication in a multisession packet based communication systemUS5633780 *Apr 18, 1996May 27, 1997Polaroid CorporationElectrostatic discharge protection deviceUS5634099Dec 9, 1994May 27, 1997International Business Machines CorporationDirect memory access unit for transferring data between processor memories in multiprocessing systemsUS5634127Nov 30, 1994May 27, 1997International Business Machines CorporationMethods and apparatus for implementing a message driven processor in a client-server environmentUS5642482Dec 21, 1993Jun 24, 1997Bull, S.A.System for network transmission using a communication co-processor comprising a microprocessor to implement protocol layer and a microprocessor to manage DMAUS5664114May 16, 1995Sep 2, 1997Hewlett-Packard CompanyAsynchronous FIFO queuing system operating with minimal queue statusUS5671355Sep 13, 1996Sep 23, 1997Predacomm, Inc.Reconfigurable network interface apparatus and methodUS5678060Oct 28, 1994Oct 14, 1997Hitachi, Ltd.System for executing high speed communication protocol processing by predicting protocol header of next frame utilizing successive analysis of protocol header until successful header retrievalUS5682534Sep 12, 1995Oct 28, 1997International Business Machines CorporationTransparent local RPC optimizationUS5692130Dec 7, 1995Nov 25, 1997Ricoh Company, Ltd.Method for selectively using one or two communication channel by a transmitting data terminal based on data type and channel availabilityUS5699317Oct 6, 1994Dec 16, 1997Ramtron International CorporationEnhanced DRAM with all reads from on-chip cache and all writers to memory arrayUS5701434Mar 16, 1995Dec 23, 1997Hitachi, Ltd.Interleave memory controller with a common access queueUS5701516Jan 19, 1996Dec 23, 1997Auspex Systems, Inc.High-performance non-volatile RAM protected write cache accelerator system employing DMA and data transferring schemeUS5708779 *Sep 24, 1996Jan 13, 1998International Business Machines CorporationMultimedia system and method of controlling data transfer between a host system and a network adapter using a DMA engineUS5727142May 3, 1996Mar 10, 1998International Business Machines CorporationMethod for a non-disruptive host connection switch after detection of an error condition or during a host outage or failureUS5742765 *Jun 19, 1996Apr 21, 1998Pmc-Sierra, Inc.Combination local ATM segmentation and reassembly and physical layer deviceUS5749095Jul 1, 1996May 5, 1998Sun Microsystems, Inc.Multiprocessing system configured to perform efficient write operationsUS5751715Aug 8, 1996May 12, 1998Gadzoox Microsystems, Inc.Accelerator fiber channel hub and protocolUS5752078Jul 10, 1995May 12, 1998International Business Machines CorporationSystem for minimizing latency data reception and handling data packet error if detected while transferring data packet from adapter memory to host memoryUS5758084Feb 27, 1995May 26, 1998Hewlett-Packard CompanyApparatus for parallel client/server communication having data structures which stored values indicative of connection state and advancing the connection state of established connectionsUS5758089Nov 2, 1995May 26, 1998Sun Microsystems, Inc.Method and apparatus for burst transferring ATM packet header and data to a host computer systemUS5758186Oct 6, 1995May 26, 1998Sun Microsystems, Inc.Method and apparatus for generically handling diverse protocol method calls in a client/server computer systemUS5758194Jul 3, 1997May 26, 1998Intel CorporationCommunication apparatus for handling networks with different transmission protocols by stripping or adding data to the data stream in the application layerUS5771349Jan 28, 1997Jun 23, 1998Compaq Computer Corp.Network packet switch using shared memory for repeating and bridging packets at media rateUS5778013Jan 11, 1996Jul 7, 1998Hewlett-Packard CompanyMethod and apparatus for verifying CRC codesUS5778419Feb 23, 1996Jul 7, 1998Microunity Systems Engineering, Inc.DRAM with high bandwidth interface that uses packets and arbitrationUS5790804Feb 5, 1996Aug 4, 1998Mitsubishi Electric Information Technology Center America, Inc.Computer network interface and network protocol with direct deposit messagingUS5794061Nov 22, 1996Aug 11, 1998Microunity Systems Engineering, Inc.General purpose, multiple precision parallel operation, programmable media processorUS5802258May 3, 1996Sep 1, 1998International Business Machines CorporationLoosely coupled system environment designed to handle a non-disruptive host connection switch after detection of an error condition or during a host outage or failureUS5802580Mar 5, 1997Sep 1, 1998Mcalpine; Gary L.High performance digital electronic system architecture and memory circuit thereofUS5809328Dec 21, 1995Sep 15, 1998Unisys Corp.Apparatus for fibre channel transmission having interface logic, buffer memory, multiplexor/control device, fibre channel controller, gigabit link module, microprocessor, and bus control deviceUS5812775Jul 12, 1995Sep 22, 19983Com CorporationMethod and apparatus for internetworking buffer managementUS5815646Oct 11, 1994Sep 29, 1998C-Cube MicrosystemsDecompression processor for video applicationsUS5848293Nov 3, 1995Dec 8, 1998Sun Microsystems, Inc.Method and apparatus for transmission and processing of virtual commandsUS5872919May 7, 1997Feb 16, 1999Advanced Micro Devices, Inc.Computer communication network having a packet processor with an execution unit which is variably configured from a programmable state machine and logicUS5878225Jun 3, 1996Mar 2, 1999International Business Machines CorporationDual communication services interface for distributed transaction processingUS5892903Sep 12, 1996Apr 6, 1999Internet Security Systems, Inc.Method and apparatus for detecting and identifying security vulnerabilities in an open network computer communication systemUS5898713Aug 29, 1997Apr 27, 1999Cisco Technology, Inc.IP checksum offloadUS5913028Oct 6, 1995Jun 15, 1999Xpoint Technologies, Inc.Client/server data traffic delivery system and methodUS5920566Jun 30, 1997Jul 6, 1999Sun Microsystems, Inc.Routing in a multi-layer distributed network elementUS5930830Jan 13, 1997Jul 27, 1999International Business Machines CorporationSystem and method for concatenating discontiguous memory pagesUS5931918Jul 30, 1997Aug 3, 1999Auspex Systems, Inc.Parallel I/O network file server architectureUS5935205Jun 21, 1996Aug 10, 1999Hitachi, Ltd.Computer system having a plurality of computers each providing a shared storage access processing mechanism for controlling local/remote access to shared storage devicesUS5937169Oct 29, 1997Aug 10, 19993Com CorporationOffload of TCP segmentation to a smart adapterUS5941969Oct 22, 1997Aug 24, 1999Auspex Systems, Inc.Bridge for direct data storage device accessUS5941972Dec 31, 1997Aug 24, 1999Crossroads Systems, Inc.Storage router and method for providing virtual local storageUS5950203Dec 31, 1997Sep 7, 1999Mercury Computer Systems, Inc.Method and apparatus for high-speed access to and sharing of storage devices on a networked digital data processing systemUS5991299Sep 11, 1997Nov 23, 19993Com CorporationHigh speed header translation processingUS5996024Jan 14, 1998Nov 30, 1999Emc CorporationMethod and apparatus for a SCSI applications server which extracts SCSI commands and data from message and encapsulates SCSI responses to provide transparent operationUS6005849Sep 24, 1997Dec 21, 1999Emulex CorporationFull-duplex communication processor which can be used for fibre channel framesUS6009478Nov 4, 1997Dec 28, 1999Adaptec, Inc.File array communications interface for communicating between a host computer and an adapterUS6016513Feb 19, 1998Jan 18, 20003Com CorporationMethod of preventing packet loss during transfers of data packets between a network interface card and an operating system of a computerUS6021446Jul 11, 1997Feb 1, 2000Sun Microsystems, Inc.Network device driver performing initial packet processing within high priority hardware interrupt service routine and then finishing processing within low priority software interrupt service routineUS6021507May 19, 1997Feb 1, 2000International Business Machines CorporationMethod for a non-disruptive host connection switch after detection of an error condition or during a host outage or failureUS6026452Aug 31, 1998Feb 15, 2000Pitts; William MichaelNetwork distributed site cache RAM claimed as up/down stream request/reply channel for storing anticipated data and meta dataUS6034963Oct 31, 1996Mar 7, 2000Iready CorporationMultiple network protocol encoder/decoder and data processorUS6038562Sep 5, 1996Mar 14, 2000International Business Machines CorporationInterface to support state-dependent web applications accessing a relational databaseUS6041058Sep 11, 1997Mar 21, 20003Com CorporationHardware filtering method and apparatusUS6044438Jul 10, 1997Mar 28, 2000International Business Machiness CorporationMemory controller for controlling memory accesses across networks in distributed shared memory processing systemsUS6047323Jun 27, 1996Apr 4, 2000Hewlett-Packard CompanyCreation and migration of distributed streams in clusters of networked computersUS6047356Apr 18, 1994Apr 4, 2000Sonic SolutionsMethod of dynamically allocating network node memory's partitions for caching distributed filesUS6049528Jun 30, 1997Apr 11, 2000Sun Microsystems, Inc.Trunking ethernet-compatible networksUS6057863Oct 31, 1997May 2, 2000Compaq Computer CorporationDual purpose apparatus, method and system for accelerated graphics port and fibre channel arbitrated loop interfacesUS6061368Nov 5, 1997May 9, 2000Xylan CorporationCustom circuitry for adaptive hardware routing engineUS6065096Sep 30, 1997May 16, 2000Lsi Logic CorporationIntegrated single chip dual mode raid controllerUS6067569Jul 10, 1997May 23, 2000Microsoft CorporationFast-forwarding and filtering of network packets in a computer systemUS6070200Jun 2, 1998May 30, 2000Adaptec, Inc.Host adapter having paged data buffers for continuously transferring data between a system bus and a peripheral busUS6078733 *Mar 8, 1996Jun 20, 2000Mitsubishi Electric Information Technolgy Center America, Inc. (Ita)Network interface having support for message processing and an interface to a message coprocessorUS6097734Apr 30, 1997Aug 1, 2000Adaptec, Inc.Programmable reassembly of data received in an ATM networkUS6101555Jan 12, 1998Aug 8, 2000Adaptec, Inc.Methods and apparatus for communicating between networked peripheral devicesUS6115615Feb 25, 1997Sep 5, 2000Fuji Xerox Co., Ltd.Cellular communication network and its communication methodUS6122670Oct 30, 1997Sep 19, 2000Tsi Telsys, Inc.Apparatus and method for constructing data for transmission within a reliable communication protocol by performing portions of the protocol suite concurrentlyUS6141705Jun 12, 1998Oct 31, 2000Microsoft CorporationSystem for querying a peripheral device to determine its processing capabilities and then offloading specific processing tasks from a host to the peripheral device when neededUS6145017Aug 7, 1998Nov 7, 2000Adaptec, Inc.Data alignment system for a hardware accelerated command interpreter engineUS6157955Jun 15, 1998Dec 5, 2000Intel CorporationPacket processing system including a policy engine having a classification unitUS6172980Sep 11, 1997Jan 9, 20013Com CorporationMultiple protocol supportUS6393487 *Mar 12, 2001May 21, 2002Alacritech, Inc.Passing a communication control block to a local device such that a message is processed on the device* Cited by examinerNon-Patent CitationsReference1 *"DMA Command Chaining to Support Bus Master Interleaved Memory and I/O Transfers on a Micro Channel" IBM TDB n1 Jun. 1991 pp. 236-237.2"File System Design for an NFS File Server Appliance," by Dave Hitz, et al., 13 pages, copyright 1996.3"Second Supplemental Information Disclosure Statement per 37 C.F.R. §1.97(i)", dated Jul. 29, 2002 relating to Exelan Inc. as submitted in U.S. Appl. No. 09/464,283.4"Two-Way TCP Traffic over Rate Controlled Channels: Effects and Analysis," by Lampros Kalampoukas, Anujan Varma and K.K. Ramakrishnan, IEEE Transactions on Networking, vol. 6, No. 6, 17 pages, Dec. 1998.5Adaptec article entitled, "EtherStorage Frequently Asked Questions," 5 pages, downloaded Jul. 19, 2000.6Adaptec article entitled, "EtherStorage White Paper," 7 pages, downloaded Jul. 19, 2000.7Adaptec press release, "Adaptec Announces EtherStorage Technology", 2 pages May 4, 2000, printed Jun. 14, 2000.8Andrew S. Tanenbaum, Computer Networks, Third Edition, ISBN 0-13-349945-6 (1996).9 *Application Note DMA Mode Operation of the T711A Synchronous Packet Data Formatter, Copyright 1988 AT&T.10Article entitled, "Computers; Storage," by James Berlino and Ananda Baruah, CIBC World Markets Equity Research, 9 pages, Aug. 7, 2000.11Article from Rice University entitled "LRP: A New Network Subsystem Architecture for Server Systems", by Peter Druschel and Gaurav Banga, Rice University, Oct. 1996, 8 pages.12Beach, Bob, IEEE Computer Society Press publication entitled, "UltraNet: An Architecture for Gigabit Networking", from 15<SUP>th </SUP>Conference on Local Computer Networks, 18 pages, Sep. 30-Oct. 3, 1990.13CBS Market Watch article entitled "Montreal start-up battles data storage bottleneck," by Susan Taylor, 2 pages, dated Mar. 5, 2000, 2 pages printed Mar. 7, 2000.14Chesson et al., IEEE Syposium Record entitled, "The Protocol Engine Chipset", from Hot Chips III, 16 pages, Aug. 26-27, 1991.15David Lammers, EETimes, Jun. 13, 1997, Tuner for Toshiba, Toshiba Taps iReady For Internet Tuner, 3 pages, printed Nov. 2, 1998.16EETIMES article entitled: Enterprise System Uses Flexible Spec, by Christopher Harrer and Pauline Schulman, dated Aug. 10, 1998, Issue 1020, printed Nov. 25, 1998.17Form 10-K for Exelan, Inc., for the fiscal year Dec. 31, 1988 (10 pages).18Form 10-K for Exelan, Inc., for the fiscal year ending Dec. 31, 1987 (10 Pages).19 *Fryer, Ron; "Teradata Version 2: Critical Success Factors for Data Warehouses", NCR Mar. 11, 1996, pp. 1-21.20Gigabit Ethernet Technical Brief, Achieving End-to-End Performance. Alteon Networks, Inc., First Edition, Sep. 1996.21Info Work, "Toshiba , iReady shipping internet chip," by Rob Gruth, 1 page , printed Nov. 28, 1998.22Intel article entitled "Solving Server Bottlenecks with Intel Server Adapters", Intel Corporation, Copyright 1999, 8 pages.23Internet pages directed to; Technical Brief on Alteon Ethernet Gigabit NIC technology, www.alteon.com, 14 pages, printed Mar. 15, 1997.24Internet pages entitled : Hardware Assisted Protocol Processing, which Eugene Feinberg is working on, printed Nov. 25, 1998.25Internet pages entitled: "Comparison of Novell Netware and TCP/IP Protocol Architectures," by Janique Carbone, Jul. 16, 1995, 19 pages Apr. 10, 1998.26Internet pages entitled: A Guide to the Paragon XP/S-A7 Supercomputer at Indiana University, printed Dec. 21, 1998.27Internet pages entitled: Asante and 100BASE-T Fast Ethernet, printed May 27, 1997.28Internet pages entitled: DART Fast Application-Level Networking Via Data-Copy Avoidance, by Robert J. Walsh, printed Jun. 3, 1999.29Internet pages entitled: iReady About Us and iReady Products, printed Nov. 25, 1998.30Internet pages entitled: Northridge/Southbridge vs. Intel Hub Architecture, 4 pages, printed Feb. 19, 2001.31Internet pages entitled: Smart Ethernet Network Interface Card, which Berend Ozceri is developing, printed Nov. 25, 1998.32Internet pages entitled: Technical White Paper-Xpoint's Disk-to-LAN Acceleration Solution for Windows NT Server, printed Jun. 5, 1997.33Internet pages of InterProphet entitled: Frequently Asked Questions, by Lynne Jolitz, printed Jun. 14, 1999.34Internet pages of XaQti Corporation entitled: Giga POWER Protocol Processor Product Preview, printed Nov. 25, 1998.35Internet pages of Xpoint Technologies, Inc. entitled "Smart LAN Work Requests", 5 pages, printed Dec. 19, 1997.36Internet pages of Xpoint Tecnologies www.xpoint.com web site (5 pages), printed Dec. 19, 1997.37Internet pages relating to iReady Corporation and the iReady Internet Tuner Module, printed Nov. 2, 1998.38Internet RFC/STD/FYI/BCP Archives article with heading "RFC2140" entitled "TCP Control Block Interdependence", web address http://www.faqs.org/rfcs/rfc2140.html, 9 pages, printed Sep. 20, 2002.39Internet site www.interprophet.com, 17 pages, printed Mar. 1, 2000.40Internet web pages from "Adaptec.com" website directed to the Adaptec, AEA-7110C iSCSI Host Bus Adapter . . . 11 pages, downloaded Oct. 1, 2001.41Internet web pages from the "iSCSI HBA.com" website that mention QLogic HBAs including the "SANblade 2300 Series", 8 pages download Oct. 1, 2001.42Internet web pages from the "iSCSI Storage .com" website that mention an Emulex HBA, 2 pages downloaded Oct. 1, 2001.43Internet-Draft article entitled "SCSI/TCP (SCSI over TCP)," by Satran et al., 38 pages, dated Feb. 2000. printed May 19, 2000.44IReady New Archive, "Revolutionary Approach to Consumer Electronics Internet Connectivity Funded", San Jose, CA, 2 pages, Nov. 20, 1997.45iReady News Archive, "Toshiba Delivers First Chips to Make Consumer Devices Internet-Ready Based on iReady Design," 3 pages, downloaded Nov. 2, 1998.46IReady News Archive, Seiko Instrument s Inc. (SII) Introduces World's First Internet-Ready Intelligent LCD Modules Based on IReady Technology, by Endo, Brogan and Johnson, printed Nov. 2, 1998.47iSCSI HBA article entitled "FCE-3210/6410 32 and 64-bit PCI-to-Fibre Channed HBA", 6 pages, printed Oct. 1, 2001.48Jato Technologies Internet pages entitled: Network Accelerator Chip Architecture, twelve-slide presentation, printed Aug. 19, 1998.49Koufopavlou et al., IEEE Global Telecommunications Conference, Globecom '92, presentation entitled, "Parallel TCP for High Performance Communication Subsystems", 7 pages, Dec. 6-9, 1992.50Lilienkamp et al., Publication entitled "Proposed Host-Front End Protocol", 56 pages, Dec. 1984.51 *Mackenzie, et al. "An Intel IPX1200-Based Network Interface", http://www.cc.gatech.edu/~kenmac/asan/asan-san-2.pdf.52Maclean et al., IEEE Global Telecommunications Conference, Globecom '91, presentation entitled, "An Outboard Processor for High Performance Implementation of Transport Layer Protocols", 7 pages, Dec. 2-5, 1991.53Merrill Lynch article entitled, "Storage Futures," by Steven Milunovich, 22 pages, May 10, 2000.54NEWSwatch-Iready Internet Tuner to Web Enable Devices, Nov. 5, 1996, 2 pages, printed Nov. 2, 1998.55Publication entitled "Protocol Engine Handbook", 44 pages, Oct. 1990.56Richard Stevens, "TCP/IP Illustrated, vol. 1, The Protocols", pp. 325-326 (1994).57 *Rockwell Fact Sheet (80 pages), ISDN/DMI Link Layer Controller VLSI Device, dated Jul. 23, 1986.58Ross et al., IEEE article entitled "FX1000: A high performance single chip Gigabit Ethernet NIC", from Compcon '97 Proceedings, 7 pages, Feb. 23-26, 1997.59Schwaderer et al., IEEE Computer Society Press publication entitled, "XTP in VLSI Protocol Decomposition for ASIC Implementation", from 15<SUP>th </SUP>Conference on Local Computer Networks, 5 pages, Sep. 30-Oct. 3, 1990.60Strayer et al., "Ch. 9: The Protocol Engine" from XTP: The Transfer Protocol, 12 pages, Jul. 1992.61The I-1000 Internet Tuner, iReady Corporation, 2 pages, date unknown.62Thia, Y.H. Publication entitled "A Reduced Operational Protocol Engine (ROPE) for a multiple-layer bypass architecture", Protocols for High Speed Networks, pp. 224-239, 1995.63Thia, Y.H. Publication entitled "High-Speed OSI Protocol Bypass Algorithm with Window Flow Control", Protocols for High Speed Networks, pp. 53-68, 1993.64Toshiba, "Toshiba Delivers First Chips To Make Consumer Devices Internet-Ready Based On iReady 's Design," Press Release Oct. 14, 1998, 3 pages.65U.S. Appl. No. 08/964,304, Napolitano et al.66U.S. Provisional Appl. No. 60/053,240, by Jolitz et al. (listed filing date Jul. 18, 1997).67VT8501 Apollo MVP4 Documentation, VIA Technologies, Inc., pp. i-iv, 1-11, cover and copyright page, revision 1.3 (Feb. 1, 2000).68Web pages entitled "iReady Rounding Out Management Team With Two Key Executives", 2 pages (printed Nov. 28, 1998).69Web pages from www.ireadyco.com, "Introduction," 3 pages, downloaded Nov. 25, 1998.70Web pages, www.ireadyco.com, iReady, "Products," 2 pages. Printed Nov. 25, 1998.71 *Willmann et al, "An Efficient Programmable 10 Gigabit Ethernet Network Interface", The International Symposium on High-Performance, http://www-ece.rice.edu/~willmann/pubs/willmannp<SUB>-</SUB>ethernet.pdf.72WindRiver article entitled "Tornado: For Intelligent Network Acceleration", copyright 2001, 2 pages.73WindRiver White Paper entitled "Complete TCP/IP Offload for High-Speed Ethernet Networks", Copyright 2002, 7 pages.74Zilog Product Brief entitled "Z85C30 CMOS SCC Serial Communication Controller", Zilog Inc., 3 pages (1997).* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7447795Apr 11, 2002Nov 4, 2008Chelsio Communications, Inc.Multi-purpose switching network interface controllerUS7472205 *Apr 17, 2003Dec 30, 2008Nec CorporationCommunication control apparatus which has descriptor cache controller that builds list of descriptorsUS7664868Jan 23, 2007Feb 16, 2010Alacritech, Inc.TCP/IP offload network interface deviceUS7664883Oct 16, 2006Feb 16, 2010Alacritech, Inc.Network interface device that fast-path processes solicited session layer read commandsUS7673072Jun 25, 2007Mar 2, 2010Alacritech, Inc.Fast-path apparatus for transmitting data corresponding to a TCP connectionUS7694024Jan 22, 2007Apr 6, 2010Alacritech, Inc.TCP/IP offload device with fast-path TCP ACK generating and transmitting mechanismUS7738500Dec 14, 2005Jun 15, 2010Alacritech, Inc.TCP timestamp synchronization for network connections that are offloaded to network interface devicesUS7743191Dec 20, 2007Jun 22, 2010Pmc-Sierra, Inc.On-chip shared memory based device architectureUS7809847Jan 4, 2005Oct 5, 2010Alacritech, Inc.Network interface device that can transfer control of a TCP connection to a host CPUUS7826350May 11, 2007Nov 2, 2010Chelsio Communications, Inc.Intelligent network adaptor with adaptive direct data placement schemeUS7831720May 16, 2008Nov 9, 2010Chelsio Communications, Inc.Full offload of stateful connections, with partial connection offloadUS7844743Dec 16, 2004Nov 30, 2010Alacritech, Inc.Protocol stack that offloads a TCP connection from a host computer to a network interface deviceUS7853723Feb 2, 2007Dec 14, 2010Alacritech, Inc.TCP/IP offload network interface deviceUS7907624 *Jun 4, 2008Mar 15, 2011Oracle America, Inc.Switch matrixUS7924840Dec 22, 2009Apr 12, 2011Chelsio Communications, Inc.Virtualizing the operation of intelligent network interface circuitryUS7941574Aug 11, 2008May 10, 2011International Business Machines CorporationCKD partial record handlingUS7945699Dec 1, 2008May 17, 2011Alacritech, Inc.Obtaining a destination address so that a network interface device can write network data without headers directly into host memoryUS7962654Feb 24, 2010Jun 14, 2011Circadence CorporationSystem and method for implementing application functionality within a network infrastructureUS7975066Feb 3, 2006Jul 5, 2011Circadence CorporationSystem and method for implementing application functionality within a network infrastructureUS8019901Sep 30, 2002Sep 13, 2011Alacritech, Inc.Intelligent network storage interface systemUS8024481Dec 23, 2008Sep 20, 2011Circadence CorporationSystem and method for reducing traffic and congestion on distributed interactive simulation networksUS8032655Oct 21, 2008Oct 4, 2011Chelsio Communications, Inc.Configurable switching network interface controller using forwarding engineUS8060644May 11, 2007Nov 15, 2011Chelsio Communications, Inc.Intelligent network adaptor with end-to-end flow controlUS8065399Dec 23, 2008Nov 22, 2011Circadence CorporationAutomated network infrastructure test and diagnostic system and method thereforUS8131880Jun 19, 2003Mar 6, 2012Alacritech, Inc.Intelligent network interface device and system for accelerated communicationUS8139482Sep 25, 2009Mar 20, 2012Chelsio Communications, Inc.Method to implement an L4-L7 switch using split connections and an offloading NICUS8155001Apr 1, 2010Apr 10, 2012Chelsio Communications, Inc.Protocol offload transmit traffic managementUS8180928 *Jun 17, 2005May 15, 2012Broadcom CorporationMethod and system for supporting read operations with CRC for iSCSI and iSCSI chimneyUS8195823Sep 14, 2009Jun 5, 2012Circadence CorporationDynamic network link accelerationUS8213427Dec 21, 2009Jul 3, 2012Chelsio Communications, Inc.Method for traffic scheduling in intelligent network interface circuitryUS8224885Jan 26, 2010Jul 17, 2012Teradici CorporationMethod and system for remote computing session managementUS8230134 *Apr 22, 2010Jul 24, 2012Lsi CorporationFast path SCSI IOUS8248939Oct 11, 2005Aug 21, 2012Alacritech, Inc.Transferring control of TCP connections between hierarchy of processing mechanismsUS8339952Mar 6, 2012Dec 25, 2012Chelsio Communications, Inc.Protocol offload transmit traffic managementUS8341286Jul 16, 2009Dec 25, 2012Alacritech, Inc.TCP offload send optimizationUS8356112Sep 29, 2011Jan 15, 2013Chelsio Communications, Inc.Intelligent network adaptor with end-to-end flow controlUS8386641Jun 8, 2011Feb 26, 2013Circadence CorporationSystem and method for implementing application functionality within a network infrastructureUS8417770Jun 16, 2011Apr 9, 2013Circadence CorporationData redirection system and method thereforUS8447803May 14, 2003May 21, 2013Alacritech, Inc.Method and apparatus for distributing network traffic processing on a multiprocessor computerUS8463935Jun 17, 2011Jun 11, 2013Circadence CorporationData prioritization system and method thereforUS8510468Aug 10, 2010Aug 13, 2013Ciradence CorporationRoute aware network link accelerationUS8539112May 16, 2011Sep 17, 2013Alacritech, Inc.TCP/IP offload deviceUS8539513Mar 24, 2009Sep 17, 2013Alacritech, Inc.Accelerating data transfer in a virtual computer system with tightly coupled TCP connectionsUS8566652 *Apr 6, 2012Oct 22, 2013Marvell International Ltd.Command queuing in disk drivesUS8589587May 11, 2007Nov 19, 2013Chelsio Communications, Inc.Protocol offload in intelligent network adaptor, including application level signallingUS8621101Sep 29, 2000Dec 31, 2013Alacritech, Inc.Intelligent network storage interface deviceUS8631140Oct 18, 2000Jan 14, 2014Alacritech, Inc.Intelligent network interface system and method for accelerated protocol processingUS8686838Apr 6, 2011Apr 1, 2014Chelsio Communications, Inc.Virtualizing the operation of intelligent network interface circuitryUS8750320Jan 21, 2003Jun 10, 2014Broadcom CorporationFibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in costUS8767756Nov 19, 2008Jul 1, 2014Broadcom CorporationFibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in costUS8774199Jan 21, 2003Jul 8, 2014Broadcom CorporationFibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in costUS8782199Oct 18, 2002Jul 15, 2014A-Tech LlcParsing a packet headerUS8798091Apr 30, 2008Aug 5, 2014Broadcom CorporationFibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in costUS8805948Sep 26, 2013Aug 12, 2014A-Tech LlcIntelligent network interface system and method for protocol processingUS8856379Sep 27, 2013Oct 7, 2014A-Tech LlcIntelligent network interface system and method for protocol processingUS8893159Sep 9, 2013Nov 18, 2014Alacritech, Inc.Accelerating data transfer in a virtual computer system with tightly coupled TCP connectionsUS8898340Jun 1, 2012Nov 25, 2014Circadence CorporationDynamic network link acceleration for network including wireless communication devicesUS8935406Apr 16, 2007Jan 13, 2015Chelsio Communications, Inc.Network adaptor configured for connection establishment offloadUS8935593Jan 23, 2013Jan 13, 2015Marvell International Ltd.Method and apparatus for flexible buffers in an XOR engineUS8977711Nov 3, 2011Mar 10, 2015Circadence CorporationSystem and method for implementing application functionality within a network infrastructure including wirelessly coupled devicesUS8977712Nov 3, 2011Mar 10, 2015Circadence CorporationSystem and method for implementing application functionality within a network infrastructure including a wireless communication linkUS8996705Mar 19, 2014Mar 31, 2015Circadence CorporationOptimization of enhanced network linksUS9009223May 21, 2013Apr 14, 2015Alacritech, Inc.Method and apparatus for processing received network packets on a network interface for a computerUS9021147Oct 4, 2013Apr 28, 2015Marvell International Ltd.Command queuing in disk drivesUS9055104May 22, 2009Jun 9, 2015Alacritech, Inc.Freeing transmit memory on a network interface device prior to receiving an acknowledgment that transmit data has been received by a remote deviceUS9137179 *Jul 26, 2006Sep 15, 2015Hewlett-Packard Development Company, L.P.Memory-mapped buffers for network interface controllersUS9148293Nov 21, 2011Sep 29, 2015Circadence CorporationAutomated network infrastructure test and diagnostic system and method thereforUS9185185Nov 14, 2013Nov 10, 2015Circadence CorporationSystem and method for implementing application functionality within a network infrastructureUS9244762Dec 29, 2014Jan 26, 2016Marvell International Ltd.Method and apparatus for flexible buffers in an XOR engineUS9306793Oct 19, 2009Apr 5, 2016Alacritech, Inc.TCP offload device that batches session layer headers to reduce interrupts as well as CPU copiesUS9380129Apr 5, 2013Jun 28, 2016Circadence CorporationData redirection system and method thereforUS9413788Dec 17, 2012Aug 9, 2016Alacritech, Inc.TCP offload send optimizationUS9436542Sep 28, 2015Sep 6, 2016Circadence CorporationAutomated network infrastructure test and diagnostic system and method thereforUS9537878Dec 12, 2014Jan 3, 2017Chelsio Communications, Inc.Network adaptor configured for connection establishment offloadUS9578124Mar 30, 2015Feb 21, 2017Circadence CorporationOptimization of enhanced network linksUS9582272Jun 14, 2012Feb 28, 2017Teradici CorporationMethod and system for remote computing session managementUS20040024915 *Apr 17, 2003Feb 5, 2004Nec CorporationCommunication controller and communication control methodUS20040172485 *Apr 11, 2002Sep 2, 2004Kianoosh NaghshinehMulti-purpose switching network interface controllerUS20040230979 *Nov 17, 2003Nov 18, 2004Quadrics LimitedCommand scheduling in computer networksUS20050144223 *Oct 20, 2004Jun 30, 2005Rhode Island Board Of Governors For Higher EducationBottom-up cache structure for storage serversUS20050160139 *Jan 4, 2005Jul 21, 2005Boucher Laurence B.Network interface device that can transfer control of a TCP connection to a host CPUUS20050198198 *Jan 28, 2005Sep 8, 2005Craft Peter K.Protocol stack that offloads a TCP connection from a host computer to a network interface deviceUS20060015655 *Jun 17, 2005Jan 19, 2006Zur Uri EMethod and system for supporting read operations with CRC for iSCSI and iSCSI chimneyUS20070118665 *Jan 22, 2007May 24, 2007Philbrick Clive MTCP/IP offload device with fast-path TCP ACK generating and transmitting mechanismUS20080028103 *Jul 26, 2006Jan 31, 2008Michael Steven SchlanskerMemory-mapped buffers for network interface controllersUS20080040519 *May 1, 2007Feb 14, 2008Alacritech, Inc.Network interface device with 10 Gb/s full-duplex transfer rateUS20080317025 *Jun 4, 2008Dec 25, 2008Sun Microsystems, Inc.Switch matrixUS20100036977 *Aug 11, 2008Feb 11, 2010International Business Machines CorporationCkd partial record handlingUS20100306420 *Apr 22, 2010Dec 2, 2010Lsi CorporationFast path scsi ioUSRE45009Oct 2, 2013Jul 8, 2014Circadence CorporationDynamic network link acceleration* Cited by examinerClassifications U.S. Classification710/22, 710/310, 710/308, 711/154, 709/200, 710/39International ClassificationG06F13/00, H04L12/56, G06F5/10, H04L29/06, H04L29/08, G06F3/00Cooperative ClassificationH04L69/166, H04L67/325, H04L69/32, H04L67/327, H04L69/163, H04L69/22, H04L69/161, H04L69/16, H04L69/08, H04L69/12, H04L29/06, H04L49/9063, G06F5/10, H04L49/90European ClassificationH04L29/06J13, H04L29/06J7, H04L29/06J3, H04L49/90, H04L49/90Q, H04L29/06, H04L29/08N31Y, G06F5/10, H04L29/06J, H04L29/08N31TLegal EventsDateCodeEventDescriptionMay 14, 2001ASAssignmentOwner name: ALACRITECH, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BLIGHTMAN, STEPHEN E. J.;STARR, DARYL D.;PHILBRICK, CLIVE M.;REEL/FRAME:011813/0395Effective date: 20010514May 5, 2010FPAYFee paymentYear of fee payment: 4Nov 15, 2013ASAssignmentOwner name: A-TECH LLC, DELAWAREFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ALACRITECH INC.;REEL/FRAME:031644/0783Effective date: 20131017Jun 20, 2014REMIMaintenance fee reminder mailedOct 21, 2014FPAYFee paymentYear of fee payment: 8Oct 21, 2014SULPSurcharge for late paymentYear of fee payment: 7Jun 22, 2016ASAssignmentOwner name: ALACRITECH, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:A-TECH LLC;REEL/FRAME:039068/0884Effective date: 20160617RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services