Source: http://www.google.com/patents/US7153784?dq=patent:6161142
Timestamp: 2015-05-29 14:24:34
Document Index: 531944413

Matched Legal Cases: ['art 101', 'art 102', 'art 101', 'art 102', 'art 119', 'art 126', 'art 118', 'art 127', 'art 119', 'art 126', 'art 126', 'art 130', 'art 126', 'art 131', 'art 131', 'art 131', 'art 126']

Patent US7153784 - Method for making a semiconductor device having a high-k gate dielectric ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first...http://www.google.com/patents/US7153784?utm_source=gb-gplus-sharePatent US7153784 - Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrodeAdvanced Patent SearchPublication numberUS7153784 B2Publication typeGrantApplication numberUS 10/828,958Publication dateDec 26, 2006Filing dateApr 20, 2004Priority dateApr 20, 2004Fee statusPaidAlso published asCN1947242A, CN1947242B, CN101916771A, CN101916771B, DE112005000854B4, DE112005000854T5, US7355281, US7671471, US20050233527, US20060180878, US20080135952, WO2005106950A1Publication number10828958, 828958, US 7153784 B2, US 7153784B2, US-B2-7153784, US7153784 B2, US7153784B2InventorsJustin K. Brask, Jack Kavalieros, Mark L. Doczy, Uday Shah, Chris E. Barns, Matthew V. Metz, Suman Datta, Annalisa Cappellani, Robert S. ChauOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (41), Non-Patent Citations (7), Referenced by (37), Classifications (16), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US 7153784 B2Abstract
forming a trench within the first dielectric layer, wherein the trench is formed by removing a mask layer and a polysilicon layer, and wherein the mask layer protects the polysilicon layer during a silicide process;
forming a first metal layer on the first part of the second dielectric layer but not covering the second part of the second dielectric layer; and
forming a second metal layer on the first metal layer and on the second part of the second dielectric layer, the second metal layer covering the first metal layer and covering the second part of the second dielectric layer.
2. The method of claim 1 wherein the second dielectric layer comprises a high-k gate dielectric layer.
3. The method of claim 2 wherein the high-k gate dielectric layer comprises a material that is selected form the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
4. The method of claim 1 wherein the first metal layer comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide, and the second metal layer comprises a material that is selected form the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.
5. The method of claim 1 wherein the first metal layer comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide and the second metal layer comprises a material that is selected form the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide.
8. The method of claim 1 further comprising forming a fill metal within the trench and on the second metal layer.
9. The method of claim 8 wherein the fill metal is subsequently polished back.
10. The method of claim 1 further comprising forming an underlayer metal on the second dielectric layer prior to forming the first metal layer.
11. The method of claim 1 further comprising forming the first metal layer on the first part of the second dielectric layer by forming a metal layer on both the first and second parts of the second dielectric layer, then removing the metal layer from the second part of the dielectric layer.
12. The method of claim 11 wherein the first metal layer is formed on the first part of the second dielectric layer by:
forming a metal layer on both the first and second parts of the second dielectric layer;
forming a spin on glass layer on the metal layer, a first part of the spin on glass layer covering the first part of the second dielectric layer and a second part of the spin on glass layer covering a second part of the second dielectric layer;
removing the second part of the spin on glass layer while retaining the first part of the spin on glass layer, exposing part of the metal layer;
removing the exposed part of the metal layer to generate the first metal layer that covers the first part of the second dielectric layer but does not cover the second part of the second dielectric layer; then
removing the first part of the spin on glass layer.
13. The method of claim 1 wherein the second part of the second dielectric layer is formed at the bottom of the same trench as the first part of the second dielectric layer.
14. The method of claim 13 wherein the semiconductor device comprises a P/N junction at the vertical interface formed where the first metal layer and the second metal layer meet at the bottom of the trench.
15. The method of claim 1 wherein the first metal layer is formed subsequent to removing impurities from the second dielectric layer and increasing the oxygen content of the second dielectric layer.
16. The method of claim 15 wherein removing impurities from the second dielectric layer and increasing the oxygen content of the second dielectric layer comprise exposing the second dielectric layer to an aqueous solution that contains between about 2% and about 30% hydrogen peroxide by volume between about 15� C. and about 40� C. for at least about 1 minute.
forming a metal layer on both the first and second parts of the high-k gate dielectric layer;
forming a spin on glass layer on the metal layer, a first part of the spin on glass layer covering the portion of the metal layer that covers the first part of the high-k gate dielectric layer in the trench and a second part of the spin on glass layer covering the portion of the metal layer that covers the second part of the high-k gate dielectric layer;
removing the exposed part of the metal layer to generate a first metal layer that covers the first part of the high-k gate dielectric layer but does not cover the second part of the high-k gate dielectric layer;
removing the first part of the spin on glass layer; and
forming a second metal layer on the first metal layer and on the second part of the high-k gate dielectric layer, the second metal layer covering the first metal layer and covering the second part of the high-k gate dielectric layer.
18. The method of claim 17 wherein the high-k gate dielectric layer comprises a material that is selected form the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
19. The method of claim 18 wherein the first metal layer is formed subsequent to removing impurities from the high-k gate dielectric layer.
20. The method of claim 18 wherein the first metal layer is formed subsequent to increasing the oxygen content of the high-k gate dielectric layer.
21. The method of claim 17 wherein the first and second metal layers are each between about 25 and about 300 angstroms thick, the first metal layer has a workfunction that is between about 3.9 eV and about 4.2 eV and comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide, and the second metal layer has a workfunction that is between about 4.9 eV and about 5.2 eV and comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide, and further comprising forming a fill metal within the trench and on the second metal layer.
22. The method of claim 21 wherein the fill metal is subsequently polished back.
23. The method of claim 17 wherein the first and second metal layers are each between about 25 and about 300 angstroms thick, the first metal layer has a workfunction that is between about 4.9 eV and about 5.2 eV and comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide and the second metal layer has a workfunction that is between about 3.9 eV and about 4.2 eV and comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide, and further comprising forming a fill metal within the trench and on the second metal layer.
24. The method of claim 23 wherein the fill metal is subsequently polished back.
25. The method of claim 17 wherein the second part of the high-k gate dielectric layer is formed at the bottom of the same trench as the first part of the high-k gate dielectric layer.
26. The method of claim 25 wherein the semiconductor device comprises a P/N junction at the vertical interface formed where the first metal layer and the second metal layer meet at the bottom of the trench.
27. A method for making a semiconductor device comprising:
forming a high-k gate dielectric layer on the substrate, the high-k gate dielectric layer having a first part that is formed at the bottom of the trench and a second part, the high-k gate dielectric layer comprising a material that is selected from the group consisting of hafnium oxide, zirconium oxide, and aluminum oxide;
forming a metal layer on both the first and second parts of the high-k gate dielectric layer, the metal layer being between about 25 and about 300 angstroms thick;
forming a second metal layer on the first metal layer and on the second part of the high-k gate dielectric layer, the second metal layer being between about 25 and about 300 angstroms thick and covering the first metal layer and the second part of the high-k gate dielectric layer.
28. The method of claim 27 wherein the first metal layer has a workfunction that is between about 3.9 eV and about 4.2 eV and comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide, and the second metal layer has a workfunction that is between about 4.9 eV and about 5.2 eV and comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.
29. The method of claim 27 wherein the first metal layer has a workfunction that is between about 4.9 eV and about 5.2 eV and comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide and the second metal layer has a workfunction that is between about 3.9 eV and about 4.2 eV and comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide.
30. The method of claim 27 further comprising forming a fill metal within the trench and on the second metal layer.
31. The method of claim 30 wherein the fill metal comprises a material that is selected from the group consisting of tungsten, aluminum, titanium, and titanium nitride.
32. The method of claim 31 wherein the fill metal is subsequently polished back.
33. The method of claim 27 wherein the second part of the high-k gate dielectric layer is formed at the bottom of the same trench as the first part of the high-k gate dielectric layer.
34. The method of claim 27 wherein the semiconductor device comprises a P/N junction at the vertical interface formed where the first metal layer and the second metal layer meet at the bottom of the trench.
35. The method of claim 27 wherein the first metal layer is formed subsequent to removing impurities from the high-k gate dielectric layer.
36. A method for making a semiconductor device comprising:
subsequent to forming said dielectric layer, forming a trench within said dielectric layer, wherein said trench is formed by removing a mask layer and a polysilicon layer, and wherein said mask layer protects said polysilicon layer during a previous suicide process; and
subsequent to forming said trench, forming a high-k gate dielectric layer on said substrate, said high-k gate dielectric layer having a first part that is formed at the bottom of said trench and a second part; and
subsequent to forming said high-k gate dielectric layer, forming a first metal layer on said first part of said high-k gate dielectric layer but not covering said second part of said high-k gate dielectric layer; and
subsequent to forming said first metal layer, forming a second metal layer on said first metal layer and on said second part of said high-k gate dielectric layer, wherein said second metal layer comprises a different material than said first metal layer.
37. The method of claim 36 wherein said second part of said high-k gate dielectric layer is formed at the bottom of said trench, and wherein said semiconductor device comprises a P/N junction at the vertical interface formed where said first metal layer and said second metal layer meet at the bottom of said trench.
38. The method of claim 36 wherein patterning said first metal layer comprises using a spin on glass layer.
39. The method of claim 36 wherein said first metal layer is formed subsequent to removing impurities from said high-k gate dielectric layer and increasing the oxygen content of said high-k gate dielectric layer, wherein removing impurities from said high-k gate dielectric layer and increasing the oxygen content of said high-k gate dielectric layer comprise exposing said high-k gate dielectric layer to an aqueous solution that contains between about 2% and about 30% hydrogen peroxide by volume between about 15� C. and about 40� C. for at least about 1 minute.
40. A method for making a semiconductor device comprising:
subsequent to forming said dielectric layer, forming a trench within said dielectric layer; and
subsequent to forming said trench, forming a high-k gate dielectric layer on said substrate, said high-k gate dielectric layer having a first part that is formed at the bottom of said trench and a second part that is formed at the bottom of said trench; and
41. The method of claim 40 wherein said semiconductor device comprises a P/N junction at the vertical interface formed where said first metal layer and said second metal layer meet at the bottom of said trench.
42. The method of claim 40 wherein said high-k gate dielectric layer comprises a material that is selected form the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
43. The method of claim 42 wherein said first metal layer is formed subsequent to removing impurities from said high-k gate dielectric layer and increasing the oxygen content of said high-k gate dielectric layer, wherein removing impurities from said high-k gate dielectric layer and increasing the oxygen content of said high-k gate dielectric layer comprise exposing said high-k gate dielectric layer to an aqueous solution that contains between about 2% and about 30% hydrogen peroxide by volume between about 15� C. and about 40� C. for at least about 1 minute.
44. A method for making a semiconductor device comprising:
forming a first trench and a second trench within said dielectric layer;
forming a first metal layer at the bottom of said first trench and at the bottom of said second trench;
forming a spin on glass layer on said first metal layer at the bottom of said first trench and said second trench;
removing the portion of said spin on glass layer that covers said first metal layer in said second trench to expose the portion of said first metal layer at the bottom of said second trench and to retain the portion of said spin on glass layer that covers said first metal layer in said first trench;
removing the exposed portion of said first metal layer from the bottom of said second trench;
removing the portion of said spin on glass layer that covers said first metal layer in said first trench to expose the portion of said first metal layer at the bottom of said first trench; and
forming a second metal layer at the bottom of said second trench and on said first metal layer at the bottom of said first trench, wherein said second metal layer comprises a different material than said first metal layer.
45. The method of claim 44 further comprising forming a fill metal within said first and said second trench and on said second metal layer, wherein said fill metal comprises a material that is selected from the group consisting of tungsten, aluminum, titanium, and titanium nitride, and wherein said fill metal is subsequently polished back.
46. A method for making a semiconductor device comprising:
forming a trench within said dielectric layer;
forming a first metal layer at the bottom of said trench;
forming a spin on glass layer on said first metal layer at the bottom of said trench;
removing a portion of said spin on glass layer so as to leave covered a first portion of said first metal layer at the bottom of said trench and to expose a second portion of said first metal layer in said trench;
removing said second portion of said first metal layer from the bottom of said trench to expose a portion of the bottom of said trench;
removing the portion of said spin on glass layer that covers said first portion of said first metal layer in said trench to expose said first portion of said first metal layer at the bottom of said trench; and
forming a second metal layer that covers said portion of the bottom of said trench and said first portion of said first metal layer at the bottom of said trench, wherein said second metal layer comprises a different material than said first metal layer.
47. The method of claim 46 wherein said semiconductor device comprises a P/N junction at the vertical interface formed where said first metal layer and said second metal layer meet at the bottom of said trench.
48. The method of claim 46 further comprising forming a fill metal within said trench and on said second metal layer, wherein said fill metal comprises a material that is selected from the group consisting of tungsten, aluminum, titanium, and titanium nitride, and wherein said fill metal is subsequently polished back.
FIGS. 1 a–1 f represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention.
FIGS. 2 a–2 f represent cross-sections of structures that may be formed when carrying out the embodiment of FIGS. 1 a–1 f to generate a device that includes a P/N junction within a trench.
FIGS. 3 a–3 b represent cross-sections of structures that may be formed when carrying out a second embodiment of the method of the present invention.
FIGS. 4 a–4 b represent cross-sections of structures that may be formed when carrying out the embodiment of FIGS. 3 a–3 b to generate a device that includes a P/N junction within a trench.
FIGS. 1 a–1 f illustrate structures that may be formed, when carrying out an embodiment of the method of the present invention. FIG. 1 a represents an intermediate structure that may be formed when making a CMOS device. That structure includes first part 101 and second part 102 of substrate 100. Isolation region 103 separates first part 101 from second part 102. First polysilicon layer 104 is formed on dielectric layer 105, and second polysilicon layer 106 is formed on dielectric layer 107. First polysilicon layer 104 is bracketed by a pair of sidewall spacers 108, 109, and second polysilicon layer 106 is bracketed by a pair of sidewall spacers 110, 111. Dielectric 112 lies next to the sidewall spacers.
In this embodiment, second metal layer 120 is then deposited on first metal layer 117 and exposed second part 119 of high-k gate dielectric layer 115 generating the structure illustrated by FIG. 1 e. If first metal layer 117 comprises an n-type metal, e.g., one of the n-type metals identified above, then second metal layer 120 preferably comprises a p-type metal, e.g., one of the p-type metals identified above. Conversely, if first metal layer 117 comprises a p-type metal, then second metal layer 120 preferably comprises an n-type metal.
FIGS. 2 a–2 f represent cross-sections of structures that may be formed when carrying out the embodiment of FIGS. 1 a–1 f to generate a device that includes a P/N junction. Such a device may, for example, comprise an SRAM, which may be used in process development work. FIGS. 2 a–2 f represent structures that are oriented perpendicular to the plane of the cross-sections represented in FIGS. 1 a–1 f. In this respect, FIGS. 2 a–2 f represent cross-sections that result when the device is rotated 90� from the position shown in FIGS. 1 a–1 f. FIGS. 2 a–2 f correspond to the structures built within trench 113, as FIGS. 1 a–1 f illustrate.
In the embodiment represented by FIGS. 2 a–2 f, a first metal layer is formed on a first part of the high-k gate dielectric layer, followed by forming a second metal layer on the first metal layer and on a second part of the high-k gate dielectric layer. The metal layers are of different conductivity type. If first metal layer 117 is n-type, then second metal layer 120 is p-type. If first metal layer 117 is p-type, then second metal layer 120 is n-type. In the resulting device, P/N junction 124 resides where first metal layer 117 meets second metal layer 120.
In devices with the FIG. 2 f structure, an adjacent trench (e.g., trench 114 of FIGS. 1 a–1 f—not shown in FIG. 2 f) may have a P/N junction with the reverse orientation. Within such an adjacent trench, second metal layer 120 may contact high-k gate dielectric layer 115 where first metal layer 117 contacts that dielectric layer in FIG. 2 f, while first metal layer 117 may contact high-k gate dielectric layer 115 where second metal layer 120 contacts that dielectric layer in FIG. 2 f. Although the embodiment of FIGS. 2 a–2 f illustrates a method for forming a structure with a P/N junction, other embodiments may form devices that do not include a P/N junction. For example, in other devices, the combination of first metal layer 117 and second metal layer 120, shown in FIG. 1 f, may coat trench 113 along its entire width, while second metal layer 120, shown in FIG. 1 f, coats trench 114 along its entire width. The method of the present invention is thus not limited to forming devices with P/N junctions.
FIGS. 3 a–3 b represent cross-sections of structures that may be formed when carrying out a second embodiment of the method of the present invention. In this second embodiment, an SOG material is used to mask a metal layer prior to etching the metal layer. As shown in FIG. 3 a, SOG layer 125 may be formed on metal layer 116. First part 126 of SOG layer 125 covers first part 118 of high-k gate dielectric layer 115, while second part 127 of SOG layer 125 covers second part 119 of high-k gate dielectric layer 115. Mask 128 (e.g., a patterned layer of photoresist) covers first part 126 of SOG layer 125. SOG layer 125 may be deposited on metal layer 116, and mask 128 may be generated, using conventional processes, as will be apparent to those skilled in the art.
FIGS. 4 a–4 b represent cross-sections of structures that may be formed when carrying out the embodiment of FIGS. 3 a–3 b to generate a device that includes a P/N junction. FIGS. 4 a–4 b have a similar orientation with respect to FIGS. 3 a–3 b that FIGS. 2 a–2 f have with respect to FIGS. 1 a–1 f. As shown in FIG. 4 a, SOG layer 125 may be formed on metal layer 116. Mask 128 covers first part 126 of SOG layer 125. Second part 130 of SOG layer 125 is removed, while first part 126 of SOG layer 125 is retained, exposing part 131 of metal layer 116. Exposed part 131 is then removed, as FIG. 4 b illustrates. After removing exposed part 131 of metal layer 116, mask 128, and first part 126 of SOG layer 125, a second metal layer—like second metal layer 120 of FIG. 2 e—may be deposited onto the remaining part of metal layer 116 and the adjacent exposed part of the high-k gate dielectric layer to generate a structure like the structure of FIG. 2 e. Although FIGS. 4 a–4 b illustrate an embodiment of the present invention in which an SOG masking layer is used to form a device with a P/N junction, this embodiment is not limited to forming devices with P/N junctions.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6063698Jun 30, 1997May 16, 2000Motorola, Inc.Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuitsUS6184072May 17, 2000Feb 6, 2001Motorola, Inc.Process for forming a high-K gate dielectricUS6255698Apr 28, 1999Jul 3, 2001Advanced Micro Devices, Inc.Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuitUS6303418Jun 30, 2000Oct 16, 2001Chartered Semiconductor Manufacturing Ltd.Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layerUS6365450Mar 15, 2001Apr 2, 2002Advanced Micro Devices, Inc.Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gateUS6410376Mar 2, 2001Jun 25, 2002Chartered Semiconductor Manufacturing Ltd.Method to fabricate dual-metal CMOS transistors for sub-0.1 μm ULSI integrationUS6420279Jun 28, 2001Jul 16, 2002Sharp Laboratories Of America, Inc.Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrateUS6475874Dec 7, 2000Nov 5, 2002Advanced Micro Devices, Inc.Damascene NiSi metal gate high-k transistorUS6514828Apr 20, 2001Feb 4, 2003Micron Technology, Inc.Method of fabricating a highly reliable gate oxideUS6544906Oct 25, 2001Apr 8, 2003Texas Instruments IncorporatedAnnealing of high-k dielectric materialsUS6586288Oct 18, 2001Jul 1, 2003Hynix Semiconductor Inc.Method of forming dual-metal gates in semiconductor deviceUS6617209Feb 22, 2002Sep 9, 2003Intel CorporationMethod for making a semiconductor device having a high-k gate dielectricUS6617210May 31, 2002Sep 9, 2003Intel CorporationMethod for making a semiconductor device having a high-k gate dielectricUS6620713Jan 2, 2002Sep 16, 2003Intel CorporationInterfacial layer for gate electrode and high-k dielectric layer and methods of fabricationUS6642131Apr 16, 2002Nov 4, 2003Matsushita Electric Industrial Co., Ltd.Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant filmUS6667246Dec 4, 2002Dec 23, 2003Matsushita Electric Industrial Co., Ltd.Wet-etching method and method for manufacturing semiconductor deviceUS6689675Oct 31, 2002Feb 10, 2004Intel CorporationMethod for making a semiconductor device having a high-k gate dielectricUS6696327Mar 18, 2003Feb 24, 2004Intel CorporationMethod for making a semiconductor device having a high-k gate dielectricUS6696345Jan 7, 2002Feb 24, 2004Intel CorporationMetal-gate electrode for CMOS transistor applicationsUS6727130Dec 6, 2001Apr 27, 2004Samsung Electronics Co., Ltd.Method of forming a CMOS type semiconductor device having dual gatesUS6794234Dec 9, 2002Sep 21, 2004The Regents Of The University Of CaliforniaDual work function CMOS gate technology based on metal interdiffusionUS6794281 *Sep 10, 2002Sep 21, 2004Freescale Semiconductor, Inc.Dual metal gate transistors for CMOS processUS6858483 *Dec 20, 2002Feb 22, 2005Intel CorporationIntegrating n-type and p-type metal gate transistorsUS6893927 *Mar 22, 2004May 17, 2005Intel CorporationMethod for making a semiconductor device with a metal gate electrodeUS20010027005Mar 28, 2001Oct 4, 2001Masaru MoriwakiSemiconductor device and method for fabricating the deviceUS20020058374Oct 18, 2001May 16, 2002Tae-Kyun KimMethod of forming dual-metal gates in semiconductor deviceUS20020197790May 30, 2002Dec 26, 2002Kizilyalli Isik C.Method of making a compound, high-K, gate and capacitor insulator layerUS20030032303Aug 13, 2001Feb 13, 2003Taiwan Semiconductor Manufacturing Co., Ltd.Ozone-enhanced oxidation for high-k dielectric semiconductor devicesUS20030045080Aug 30, 2002Mar 6, 2003Visokay Mark R.Gate structure and methodUS20030201121 *Apr 25, 2002Oct 30, 2003Pei-Ren JengMethod of solving the unlanded phenomenon of the via etchUS20050101113 *Nov 6, 2003May 12, 2005Brask Justin K.Method for making a semiconductor device having a metal gate electrodeUS20050101134 *Nov 6, 2003May 12, 2005Brask Justin K.Method for etching a thin metal layerUS20050136677 *Dec 18, 2003Jun 23, 2005Brask Justin K.Method for making a semiconductor device that includes a metal gate electrodeUS20050148130 *Dec 29, 2003Jul 7, 2005Doczy Mark L.Method for making a semiconductor device that includes a metal gate electrodeUS20050148136 *Dec 29, 2003Jul 7, 2005Brask Justin K.Cmos device with metal and silicide gate electrodes and a method for making itUS20050214987 *Mar 24, 2004Sep 29, 2005Uday ShahReplacement gate process for making a semiconductor device that includes a metal gate electrodeEP0899784A2Aug 27, 1998Mar 3, 1999Texas Instruments IncorporatedSemiconductor device and method of fabricating thereofEP1032033A2Feb 24, 2000Aug 30, 2000Texas Instruments IncorporatedMethod of forming dual metal gate structures for CMOS devicesGB2358737A Title not availableJP2002118175A Title not availableWO2001097257A2May 10, 2001Dec 20, 2001Motorola IncDual metal gate transistors for cmos process* Cited by examinerNon-Patent CitationsReference1 *"Electron Work Function of the Elements", in CRC Handbook of Chemistry and Physics, Internet Version 2005, David R. Lide, ed., <http://www.hbcpnetbase.com>, CRC Press, Boca Raton, FL, 2005.2Doug Barlage et al., "High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics", 2001 IEEE, 4 pages.3International Search Report PCT/US2005/010920.4Lu et al., "Dual-Metal Gate Technology for Deep-Submicron CMOS Devices", dated Apr. 29, 2003, 1 page.5Metz et al., "A Method for Making a Semiconductor Device Having a High-K Gate Dielectric Layer and a Metal Gate Electrode", U.S. Appl. No. 10/839,077, filed May 4, 2004.6Polishchuk et al., "Dual Workfunction CMOS Gate Technology Based on Metal Interdiffusion", www.eesc.berkeley.edu, 1 page.7Schwantes et al., "Performance Improvement of Metal Gate CMOS Technologies with Gigabit Feature Sizes", Technical University of Hanburg-Harburg, 5 pages.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7763943Dec 26, 2007Jul 27, 2010Intel CorporationReducing external resistance of a multi-gate device by incorporation of a partial metallic finUS7776755Dec 18, 2008Aug 17, 2010Taiwan Semiconductor Manufacturing Company, Ltd.Solution for polymer and capping layer removing with wet dipping in HK metal gate etching processUS7785958Jun 12, 2008Aug 31, 2010Intel CorporationMethod for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrodeUS7838946Mar 28, 2008Nov 23, 2010United Microelectronics Corp.Method for fabricating semiconductor structure and structure of static random access memoryUS7880236Jul 28, 2008Feb 1, 2011Advanced Micro Devices, Inc.Semiconductor circuit including a long channel device and a short channel deviceUS7915127Jul 27, 2009Mar 29, 2011United Microelectronics Corp.Manufacturing method of semiconductor deviceUS8030163Dec 26, 2007Oct 4, 2011Intel CorporationReducing external resistance of a multi-gate device using spacer processing techniquesUS8193050Oct 18, 2010Jun 5, 2012United Microelectronics Corp.Method for fabricating semiconductor structureUS8193641May 9, 2006Jun 5, 2012Intel CorporationRecessed workfunction metal in CMOS transistor gatesUS8198685Dec 23, 2008Jun 12, 2012Taiwan Semiconductor Manufacturing Co., Ltd.Transistors with metal gate and methods for forming the sameUS8202780Jul 31, 2009Jun 19, 2012International Business Machines CorporationMethod for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regionsUS8211775Mar 9, 2011Jul 3, 2012United Microelectronics Corp.Method of making transistor having metal gateUS8252675Nov 9, 2010Aug 28, 2012Samsung Electronics Co., Ltd.Methods of forming CMOS transistors with high conductivity gate electrodesUS8264048Feb 15, 2008Sep 11, 2012Intel CorporationMulti-gate device having a T-shaped gate structureUS8304349Feb 6, 2009Nov 6, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Method to integrate gate etching as all-in-one process for high K metal gateUS8349680Aug 6, 2009Jan 8, 2013Taiwan Semiconductor Manufacturing Company, Ltd.High-k metal gate CMOS patterning methodUS8377771May 23, 2012Feb 19, 2013Intel CorporationRecessed workfunction metal in CMOS transistor gatesUS8486790Jul 18, 2011Jul 16, 2013United Microelectronics Corp.Manufacturing method for metal gateUS8513740Sep 1, 2010Aug 20, 2013Samsung Electronics Co., Ltd.Complementary metal oxide semiconductor device having metal gate stack structure and method of manufacturing the sameUS8519487Mar 21, 2011Aug 27, 2013United Microelectronics Corp.Semiconductor deviceUS8574990Feb 24, 2011Nov 5, 2013United Microelectronics Corp.Method of manufacturing semiconductor device having metal gateUS8580625Jul 22, 2011Nov 12, 2013Tsuo-Wen LuMetal oxide semiconductor transistor and method of manufacturing the sameUS8580641Jul 26, 2011Nov 12, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Techniques providing high-k dielectric metal gate CMOSUS8658487Nov 17, 2011Feb 25, 2014United Microelectronics Corp.Semiconductor device and fabrication method thereofUS8674452Jun 24, 2011Mar 18, 2014United Microelectronics Corp.Semiconductor device with lower metal layer thickness in PMOS regionUS8704294Jun 13, 2011Apr 22, 2014United Microelectronics Corp.Semiconductor device having metal gate and manufacturing method thereofUS8723274May 22, 2013May 13, 2014United Microelectronics Corp.Semiconductor device and method for fabricating the sameUS8735269Jan 15, 2013May 27, 2014United Microelectronics Corp.Method for forming semiconductor structure having TiN layerUS8765588Sep 28, 2011Jul 1, 2014United Microelectronics Corp.Semiconductor processUS8802524Mar 22, 2011Aug 12, 2014United Microelectronics Corp.Method of manufacturing semiconductor device having metal gatesUS8816439Oct 19, 2010Aug 26, 2014United Microelectronics Corp.Gate structure of semiconductor deviceUS8836049Jun 13, 2012Sep 16, 2014United Microelectronics Corp.Semiconductor structure and process thereofUS8860135Feb 21, 2012Oct 14, 2014United Microelectronics Corp.Semiconductor structure having aluminum layer with high reflectivityUS8860181Mar 7, 2012Oct 14, 2014United Microelectronics Corp.Thin film resistor structureUS8921947Jun 10, 2013Dec 30, 2014United Microelectronics Corp.Multi-metal gate semiconductor device having triple diameter metal openingUS8952451Dec 20, 2013Feb 10, 2015United Microelectronics Corp.Semiconductor device having metal gate and manufacturing method thereofUS8999830Dec 19, 2013Apr 7, 2015United Microelectronics Corp.Semiconductor device having metal gate and manufacturing method thereofClassifications U.S. Classification438/761, 257/E21.637, 438/778, 257/E21.623International ClassificationH01L21/44, H01L21/8234, H01L21/8238Cooperative ClassificationH01L21/82345, H01L29/517, H01L21/823842, H01L21/28229, H01L29/513, H01L29/66545European ClassificationH01L29/66M6T6F8, H01L21/8234G4, H01L21/8238G4Legal EventsDateCodeEventDescriptionMay 28, 2014FPAYFee paymentYear of fee payment: 8Jun 28, 2010FPAYFee paymentYear of fee payment: 4Nov 13, 2007CCCertificate of correctionApr 20, 2004ASAssignmentOwner name: INTEL CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BRASK, JUSTIN K.;KAVALIEROS, JACK;DOCZY, MARK L.;AND OTHERS;REEL/FRAME:015257/0581Effective date: 20040409RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services