Source: http://www.google.com/patents/US7479673?ie=ISO-8859-1
Timestamp: 2014-03-17 18:40:19
Document Index: 189429842

Matched Legal Cases: ['Application No. 2004', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10']

Patent US7479673 - Semiconductor integrated circuits with stacked node contact structures - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsSemiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on...http://www.google.com/patents/US7479673?utm_source=gb-gplus-sharePatent US7479673 - Semiconductor integrated circuits with stacked node contact structuresAdvanced Patent SearchPublication numberUS7479673 B2Publication typeGrantApplication numberUS 11/033,432Publication dateJan 20, 2009Filing dateJan 11, 2005Priority dateJan 12, 2004Fee statusPaidAlso published asCN1641878A, CN100541801C, DE102005000997A1, DE102005000997B4, US20050179061, US20080023728Publication number033432, 11033432, US 7479673 B2, US 7479673B2, US-B2-7479673, US7479673 B2, US7479673B2InventorsJae-Hoon Jang, Soon-Moon Jung, Kun-Ho Kwak, Byung-Jun HwangOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (18), Non-Patent Citations (5), Referenced by (3), Classifications (27), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor integrated circuits with stacked node contact structuresUS 7479673 B2Abstract Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.
5. The integrated circuit as recited in claim 1, wherein the node plug forms an ohmic contact with respect to both P-type semiconductor and N-type semiconductor materials.
6. The integrated circuit as recited in claim 5, wherein the metal plug comprises a tungsten plug.
7. The integrated circuit as recited in claim 6, wherein the metal plug further comprises a barrier metal layer surrounding the tungsten plug.
8. The integrated circuit as recited in claim 1, wherein the lower node semiconductor plug and the first impurity region of the first transistor are of the same conductivity type.
a third interlayer insulating layer on the third transistor opposite the second interlayer insulating layer;
a node plug penetrating the first, second and third interlayer insulating layers to
electrically connect the first impurity region of the first transistor, the first impurity region of the second transistor and the first impurity region of third transistor to one another;
wherein the node plug also is electrically connected to the lower and upper node semiconductor plugs, and
wherein the lower node semiconductor plug and the first impurity region of the first transistor have different conductivity types, and wherein the node plug is in direct contact with the first impurity region of the first transistor.
10. A static random access memory (SRAM) cell comprising:
a first node plug penetrating the first, second and third interlayer insulating layers to electrically connect the first impurity region of the first bulk transistor, the first impurity region of the first lower thin film transistor and the first impurity region of the first upper thin film transistor to one another;
a second node plug penetrating the first, second and third interlayer insulating layers to electrically connect the first impurity region of the second bulk transistor, the first impurity region of the second lower thin film transistor and the first impurity region of the second upper thin film transistor to one another;
wherein the first node plug is electrically connected to the first lower node semiconductor plug and the first upper node semiconductor plug, and wherein the second node plug is electrically connected to the second lower node semiconductor plug and the second upper node semiconductor plug,
wherein the first and second upper node semiconductor plugs and the first and second lower node semiconductor plugs each comprise single crystalline semiconductor plugs, and wherein the first and second node plugs each comprise metal plugs.
11. The SRAM cell as recited in claim 10, wherein the first lower thin film transistor overlaps the first bulk transistor and wherein the second lower thin film transistor overlaps the second bulk transistor, and wherein the first upper thin film transistor overlaps the first lower thin film transistor, and wherein the second upper thin film transistor overlaps the second lower thin film transistor.
12. The SRAM cell as recited in claim 10, wherein the first and second lower thin film transistors and the first and second upper thin film transistors each comprise single crystalline thin film transistors.
13. The SRAM cell as recited in claim 10, wherein the first and second node plugs each form an ohmic contact with respect to both P-type semiconductor and N-type semiconductor materials.
14. The SRAM cell as recited in claim 10, wherein the first and second node plugs each comprise a tungsten plug.
15. The SRAM cell as recited in claim 14, wherein each of the first and second node plugs further comprises a barrier metal layer surrounding the tungsten plug.
16. The SRAM cell as recited in claim 10, wherein the first lower node semiconductor plug has the same conductivity type as the first impurity region of the first bulk transistor and the second lower node semiconductor plug has the same conductivity type as the first impurity region of the second bulk transistor.
17. The SRAM cell as recited in claim 10, wherein the first lower node semiconductor plug has a different conductivity type than does the first impurity region of the first bulk transistor, and wherein the second lower node semiconductor plug has a different conductivity type than does the first impurity region of the second bulk transistor, and wherein the first node plug is in direct contact with the first impurity region of the first bulk transistor, and wherein the second node plug is in direct contact with the first impurity region of the second bulk transistor.
18. The SRAM cell as recited in claim 10, wherein the first and second bulk transistors comprise first and second N-channel driver transistors, respectively, and wherein the first impurity region of the first bulk transistor comprises the drain region of the first bulk transistor, and wherein the first impurity region of the second bulk transistor comprises the drain region of the second bulk transistor.
19. The SRAM cell as recited in claim 18, wherein the first N-channel driver transistor has a gate electrode that is electrically connected to the second node plug, and wherein the second N-channel driver transistor has a gate electrode that is electrically connected to the first node plug.
20. The SRAM cell as recited in claim 19, wherein the first and second lower thin film transistors comprise first and second P-channel load transistors, respectively, and wherein the first and second upper thin film transistors comprise first and second N- channel transfer transistors, respectively, and wherein the first impurity region of the first lower thin film transistor comprises a drain region of the first lower thin film transistor, and wherein the first impurity region of the second lower thin film transistor comprises a drain region of the second lower thin film transistor, and wherein the first impurity region of the first upper thin film transistor comprises a source region of the first upper thin film transistor and wherein the first impurity region of the second upper thin film transistor comprises a source region of the second upper thin film transistor.
21. The SRAM cell as recited in claim 20, wherein the first P-channel load transistor has a gate electrode that is electrically connected to the second node plug, and the second P-channel load transistor has a gate electrode that is electrically connected to the first node plug.
22. The SRAM cell as recited in claim 20, wherein the first and second N-channel transfer transistors have gate electrodes that are electrically connected to each other to act as a word line.
23. The SRAM cell as recited in claim 20, further comprising:
wherein the ground line and the power line are substantially in parallel with a gate electrode of the first N-channel driver transistor and with a gate electrode of the second N- channel driver transistor.
24. The SRAM cell as recited in claim 21, further comprising:
a second bit line that is electrically connected to the drain region of the second N- channel transfer transistor;
25. The SRAM cell as recited in claim 24, wherein the first bit line is substantially perpendicular to a gate electrode of the first N-channel driver transistor, a gate electrode of the first P-channel load transistor and a gate electrode of the first N-channel transfer transistor when viewed from an axis that is perpendicular to the primary plane of the semiconductor substrate, and the second bit line is substantially perpendicular to a gate electrode of the second N-channel driver transistor, a gate electrode of the second P-channel load transistor and a gate electrode of the second N-channel transfer transistor when viewed from an axis that is perpendicular to the primary plane of the semiconductor substrate.
26. The SRAM cell as recited in claim 19, wherein the first and second lower thin film transistors comprise first and second N-channel transfer transistors, respectively, and wherein the first and second upper thin film transistors comprise first and second P-channel load transistors, respectively, and wherein the first impurity region of the first lower thin film transistor comprises a source region of the first lower thin film transistor, and wherein the first impurity region of the second lower thin film transistor comprises a source region of the second lower thin film transistor, and wherein the first impurity region of the first upper thin film transistor comprises a drain region of the first upper thin film transistor and wherein the first impurity region of the second upper thin film transistor comprises a drain region of the second upper thin film transistor.
27. The SRAM cell as recited in claim 26, wherein the first P-channel load transistor has a gate electrode that is electrically connected to the second node plug, and wherein the second P-channel load transistor has a gate electrode that is electrically connected to the first node plug.
28. A static random access memory (SRAM) cell comprising:
a first node plug penetrating the first, second and third interlayer insulating layers to electrically connect a first impurity region of the first bulk transistor, a first impurity region of the first lower thin film transistor and a first impurity region of the first upper thin film transistor to one another;
a second node plug penetrating the first, second and third interlayer insulating layers to electrically connect a first impurity region of the second bulk transistor, a first impurity region of the second lower thin film transistor and a first impurity region of the second upper thin film transistor to one another;
a first ground active region extending from a first end of the first active region in a direction perpendicular to the first active region;
a second ground active region extending from a first end of the second active region in a direction perpendicular to the second active region and
a ground line that is electrically connected to the first and second around active regions,
wherein the ground line crosses over the first and second active regions,
wherein the first and second bulk transistors comprise first and second N-channel driver transistors, respectively,
wherein the first impurity region of the first bulk transistor comprises the drain region of the first bulk transistor, and
wherein the first impurity region of the second bulk transistor comprises the drain region of the second bulk transistor.
29. The SRAM cell as recited in claim 28, wherein the first N-channel driver transistor has a gate electrode that is electrically connected to the second node plug, and wherein the second N-channel driver transistor has a gate electrode that is electrically connected to the first node plug.
30. The SRAM cell as recited in claim 28, wherein the first and second lower thin film transistors are first and second P-channel load transistors, respectively, and wherein the first and second upper thin film transistors are first and second N-channel transfer transistors, respectively, and wherein the first impurity region of the first lower thin film transistor comprises a drain region of the first lower thin film transistor, and wherein the second lower thin film transistor comprises a drain region of the second lower thin film transistor, and wherein the first impurity region of the first upper thin film transistor comprises a source region of the first upper thin film transistor, and wherein the first impurity region of the second upper thin film transistor comprises a source region of the second upper thin film transistor.
31. The SRAM cell as recited in claim 30, wherein the first lower body pattern overlaps the first active region, and wherein the second lower body pattern overlaps the second active region, and wherein the first upper body pattern overlaps the first lower body pattern, and wherein the second upper body pattern overlaps the second lower body pattern.
32. The SRAM cell as recited in claim 31, wherein a gate electrode of the first load transistor overlaps a gate electrode of the first driver transistor, and wherein a gate electrode of the second load transistor overlaps the gate electrode of the second driver transistor, and wherein the gate electrode of the first load transistor is electrically connected to the second node plug, and wherein the gate electrode of the second load transistor is electrically connected to the first node plug.
33. The SRAM cell as recited in claim 30, wherein a gate electrode of the first transfer transistor is electrically connected to a gate electrode of the second transfer transistor to act as a word line.
34. A static random access memory (SRAM) cell comprising:
a first lower thin film transistor and a second lower thin film transistor at the first and second lower body patterns. respectively;
a first upper thin film transistor and a second upper thin film transistor at the first and second upper body patterns. respectively;
a first ground active region extending from a first end of the first active region in a direction perpendicular to the first active region,
a second ground active region extending from a first end of the second active region in a direction perpendicular to the second active region,
wherein the first impurity region of the second bulk transistor comprises the drain region of the second bulk transistor, and
wherein the first and second lower thin film transistors are first and second P-channel load transistors, respectively, and wherein the first and second upper thin film transistors are first and second N-channel transfer transistors, respectively, and wherein the first impurity region of the first lower thin film transistor comprises a drain region of the first lower thin film transistor, and wherein the second lower thin film transistor comprises a drain region of the second lower thin film transistor, and wherein the first impurity region of the first upper thin film transistor comprises a source region of the first upper thin film transistor, and wherein the first impurity region of the second upper thin film transistor comprises a source region of the second upper thin film transistor,
wherein the first lower body pattern overlaps the first active region, and wherein the second lower body pattern overlaps the second active region. and wherein the first upper body pattern overlaps the first lower body pattern, and wherein the second upper body pattern overlaps the second lower body pattern.
wherein the first lower body pattern further includes an extension that overlaps a portion of the first ground active region, and wherein the second lower body pattern further includes an extension that overlaps a portion of the second ground active region.
35. The SRAM cell as recited in claim 34, further comprising:
36. A static random access memory (SRAM) cell comprising:
37. The SRAM cell as recited in claim 36, wherein the first bit line is substantially perpendicular to a gate electrode of the first N-channel driver transistor, a gate electrode of the first P-channel load transistor and a gate electrode of the first N-channel transfer transistor when viewed from an axis that is perpendicular to the primary plane of the semiconductor substrate, and wherein the second bit line is substantially perpendicular to a gate electrode of the second N-channel driver transistor, a gate electrode of the second P- channel load transistor and a gate electrode of the second N-channel transfer transistor when viewed from an axis that is perpendicular to the primary plane of the semiconductor substrate.
CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C. � 119 from Korean Patent Application No. 2004-0002088, filed on Jan. 12, 2004, the disclosure of which is incorporated herein by reference as if set forth in its entirety.
FIELD OF THE INVENTION The present invention relates to semiconductor integrated circuits and, more particularly, to contact structures for semiconductor integrated circuits.
BACKGROUND OF THE INVENTION As is known by those of skill in the art, static random access memory (SRAM) integrated circuits may exhibit relatively low power consumption and high operating speeds as compared to dynamic random access memory (DRAM) integrated circuits. As a result, SRAM circuits are widely used to implement cache memories in computers and portable consumer electronic devices.
The unit cells of an SRAM integrated circuit can be implemented, for example, as either a high load resistor SRAM cell or as a complementary metal oxide semiconductor (CMOS)SRAM cell. Typically, the high load resistor SRAM cells use a high resistance resistor as the load device, and the CMOS SRAM cells use a p-channel or �p-type� metal oxide semiconductor (PMOS) transistor as the load device.
Semiconductor devices that include TFTs stacked over a semiconductor substrate are disclosed in U.S. Pat. No. 6,022,766 to Chen et al., entitled �Semiconductor Structure Incorporating Thin Film Transistors and Methods for Its Manufacture.� In particular, Chen et al. discloses a semiconductor device in which a conventional bulk transistor is formed at a single crystalline silicon substrate, and a thin film transistor is then stacked over the bulk transistor. In Chen et al., the body layer of the TFT is formed by depositing an amorphous silicon layer on the semiconductor substrate and a metal plug. This amorphous silicon layer is then crystallized via a thermal treatment process. This thermal treatment process converts the amorphous silicon layer into a polycrystalline or �polysilicon� layer having large grains. The electrical characteristics of these TFTs that are formed with a polysilicon body layer may not be as good as the electrical characteristics of bulk transistors formed at a single crystalline silicon substrate.
SUMMARY OF THE INVENTION Pursuant to embodiments of the present invention, integrated circuits are provided which include a first transistor having first and second impurity regions that is formed at a semiconductor substrate. A first interlayer insulating layer is on the first transistor, and a second transistor having first and second impurity regions is on the first interlayer insulating layer opposite the first transistor. A second interlayer insulating layer is on the second transistor opposite the first interlayer insulating layer, and a third transistor having first and second impurity regions is on the second interlayer insulating layer opposite the second transistor. Finally, a third interlayer insulating layer on the third transistor opposite the second interlayer insulating layer. The integrated circuit further includes a node plug that penetrates the first, second and third interlayer insulating layers to electrically connect the first impurity region of the first transistor, the first impurity region of the second transistor and the first impurity region of third transistor to one another.
First and second driver gate patterns 10 a and 10 b are provided that cross over the first and second active regions 3 a and 3 b, respectively. The first driver gate patterns 10 a may be disposed parallel to the second driver gate patterns 10 b. As shown in FIG. 17 a, the first driver gate pattern 10 a may include a first driver gate electrode 7 a and a first capping insulating layer pattern 9 a which are sequentially stacked. As shown in FIG. 17 b, the second driver gate pattern 10 b may include a second driver gate electrode 7 b and a second capping insulating layer pattern 9 b which are sequentially stacked. A gate insulating layer 5 may be interposed between the driver gate patterns 10 a and 10 b and the respective active regions 3 a and 3 b. As shown in FIG. 17 a, a first drain region 13 d′ is provided at a surface of the first active region 3 a. The first drain region 13 d′ may be adjacent to the first driver gate pattern 10 a and located opposite the first ground active region 3 s′. A first source region 13 s′ may be provided at a surface of the first ground active region 3 s′ and at a surface of the first active region 3 a. The first source region 13 s′ may be adjacent to the first driver gate pattern 10 a and located opposite the first drain region 13 d′. Similarly, as shown in FIG. 17 b, a second drain region 13 d″ is provided at a surface of the second active region 3 b. The second drain region 13 d″ may be adjacent to the second driver gate pattern 10 b and located opposite the second ground active region 3 s″. A second source region 13 s″ may be provided at a surface of the second ground active region 3 s″ and at a surface of the second active region 3 b. The second source region 13 s″ may be adjacent to the second driver gate pattern 10 b and located opposite the second drain region 13 d″. The first and second source regions 13 s′ and 13 s″ and the first and second drain regions 13 d′ and 13 d″ may be lightly doped drain (LDD) type impurity regions. Additionally, driver gate spacers 11 may be provided on sidewalls of the first and second driver gate patterns 10 a and 10 b. The first driver gate pattern 10 a may extend to be adjacent to the second drain region 13 d″. Similarly, the second driver gate pattern 10 b may extend to be adjacent to the first drain region 13 d′. The first driver gate pattern 10 a, the first drain region 13 d′ and the first source region 13 s′ constitute a first bulk transistor such as, for example, the first driver transistor TD1 in FIG. 1. Likewise, the second driver gate pattern 10 b, the second drain region 13 d″ and the second source region 13 s″ constitute a second bulk transistor such as, for example, the second driver transistor TD2 of FIG. 1. Thus, in embodiments of the present invention, the first and second driver transistors TD1 and TD2 may be N-type bulk transistors that are formed at the semiconductor substrate. As shown in FIGS. 2, 17A and 17B, the area occupied by the first and second driver transistors TD1 and TD2 may comprise a substantial percentage of the area of the SRAM cell. Accordingly, pursuant to embodiments of the present invention, SRAM cells may be provided that have a significantly reduced cell area as compared to the area occupied by a conventional SRAM cell that has four or six bulk MOS transistors.
Referring to FIGS. 4, 17A and 17B, a first load gate pattern 26 a may be formed on and crossing over the first lower body pattern 21 a, and a second load gate pattern 26 b may be formed on and crossing over the second lower body pattern 21 b. The first load gate pattern 26 a may include a first load gate electrode 23 a and a first capping insulating layer pattern 25 a which are sequentially stacked. The second load gate pattern 26 b may include a second load gate electrode 23 b and a second capping insulating layer pattern 25 b which are sequentially stacked. The first and second load gate patterns 26 a and 26 b may be insulated from the lower body patterns 21 a and 21 b by a gate insulating layer (shown, but not numbered, in FIGS. 17A and 17B). The first load gate patterns 26 a may overlap the first driver gate pattern 10 a and the second load gate pattern 26 b may overlap the second driver gate pattern 10 b. A first impurity region 29 d′ is provided in a portion of the first lower body pattern 21 a that is adjacent to the first load gate pattern 26 a. The portion of the first lower body pattern 21 a that comprises the first impurity region 29 d′ may include a portion of the first lower body pattern 21 a that is in contact with the first lower node semiconductor plug 19 a. A second impurity region 29 s′ is provided in another portion of the first lower body pattern 21 a that is adjacent to the first load gate pattern 26 a and opposite the first impurity region 29 d′. The first load gate pattern 26 a and the first and second impurity regions 29 d′ and 29 s′ may together constitute a first lower TFT such as, for example, the first load transistor TL1 of FIG. 1. The first and second impurity regions 29 d′ and 29 s′ may act as drain and source regions of the first lower TFT, respectively.
The first and second load transistors TL1 and TL2 may correspond to P-type transistors. The source and drain regions 29 s′, 29 s″, 29 d′ and 29 d″ may be LDD type impurity regions. Load gate spacers 27 may be provided on sidewalls of the first and second load gate patterns 26 a and 26 b. A second interlayer insulating layer 33 may be formed on the semiconductor substrate having the first and second load transistors TL1 and TL2. The second interlayer insulating layer 33 may have a planarized top surface. In addition, a second etch stopper 31 may be interposed between the second interlayer insulating layer 33 and the semiconductor substrate having the load transistors TL1 and TL2. The second etch stopper 31 may, for example, comprise an insulating layer that has an etch selectivity with respect to the second interlayer insulating layer 33. For instance, when the second interlayer insulating layer 33 is a silicon oxide layer, the second etch stopper 31 may be a silicon nitride layer or a silicon oxynitride layer.
As shown in FIGS. 17A and 17B, a fourth interlayer insulating layer 53 may be provided on the semiconductor substrate having the first and second node plugs 51 a and 51 b. As shown FIGS. 7, 17A and 17B, the extension of the first lower body pattern 21 a (i.e., the source region 29 s″ of the first load transistor TL1) is electrically connected to a first power line contact plug 55 c′ that penetrates the second etch stopper 31, the second interlayer insulating layer 33, the third etch stopper 47, the third interlayer insulating layer 49 and the fourth interlayer insulating layer 53. Similarly, the extension of the second lower body pattern 21 b (i.e., the source region 29 s″ of the second load transistor TL2) is electrically connected to a second power line contact plug 55 c″ that penetrates the second etch stopper 31, the second interlayer insulating layer 33, the third etch stopper 47, the third interlayer insulating layer 49 and the fourth interlayer insulating layer 53.
The power line contact plugs 55 c′ and 55 c″ and the ground line contact plugs 55 s′ and 55 s″ may, for example, be metal plugs such as tungsten plugs. Furthermore, each of the power line contact plugs 55 c′ and 55 c″ and the ground line contact plugs 55 s′ and 55 s″ may include a tungsten plug and a barrier metal layer surrounding the tungsten plug. A fifth interlayer insulating layer 57 is provided on the semiconductor substrate having the power line contact plugs 55 c′ and 55 c″ and the ground line contact plugs 55 s′ and 55 s″. FIG. 8 is a plan view illustrating power lines 59 c and ground lines 59 s for CMOS SRAM cells in accordance with embodiments of the present invention. In FIG. 8, the ground active regions 3 s′ and 3 s″, the lower body patterns 21 a and 21 b, and the node plugs 51 a and 51 b that are shown in FIG. 7 are not included to reduce the complexity of the drawing.
First and second parallel bit lines 65 b′ and 65 b″ may be disposed on the sixth interlayer insulating layer 61. The first bit line 65 b′ is disposed to be in contact with the first bit line contact plug 63 b′, and the second bit line 65 b″ is disposed to be in contact with the second bit line contact plug 63 b″. The first and second bit lines 65 b′, 65″ are disposed to cross over the power line 59 c and the ground line 59 s. In other embodiments of the present invention, the first and second node contact structures described with reference to FIGS. 6, 17A and 17B may be modified in many different forms. For example, FIG. 14C is a cross-sectional view illustrating a first node contact structure of CMOS SRAM cells according to further embodiments of the present invention.
A lower body layer may then be formed on the top surface of the semiconductor substrate having the first and second lower node semiconductor plugs 19 a and 19 b. By way of example, if the lower node semiconductor plugs 19 a and 19 b are single crystalline silicon plugs, the lower body layer may be formed as an amorphous silicon layer or a polycrystalline silicon layer. As shown best in FIGS. 1A and 11B, the lower body layer may then be patterned to form first and second lower body patterns 21 a and 21 b. The first lower body pattern 21 a may overlap the first active region 3 a and may cover the first and second lower node semiconductor plugs 19 a. The second lower body pattern 21 b may overlap the second active region 3 b and may cover the second lower node semiconductor plug 19 b. The first lower body pattern 21 a may include an extension that overlaps a portion of the first ground active region 3 s′ and the second lower body pattern 21 b may include an extension that overlaps a portion of the second ground active region 3 s″. The first and second lower body patterns 21 a and 21 b may be crystallized using, for example, a solid phase epitaxial (SPE) technique that is well known in the art. For example, the SPE technique may include annealing at a temperature of about 500� C. to 800� C. to crystallize the lower body patterns 21 a and 21 b. When an SPE process is used to crystallize the lower body patterns 21 a and 21 b, the lower node semiconductor plugs 19 a and 19 b may act as seed layers during the SPE process. As a result, if the lower node semiconductor plugs 19 a and 19 b are single crystalline silicon plugs, then the lower body patterns 21 a and 21 b may be converted to have a single crystalline structure through the SPE process.
Referring to FIGS. 5, 13A and 13B, first and second upper body patterns 37 a and 37 b may be formed on the semiconductor substrate having the first and second upper node semiconductor plugs 35 a and 35 b. The first and second upper body patterns 37 a and 37 b may be formed using, for example, the same methods as the methods (described above) used to form the first and second lower body patterns 21 a and 21 b. Thus, the first and second upper body patterns 37 a and 37 b may be formed to be in contact with the first and second upper node semiconductor plugs 35 a and 35 b respectively, and may be crystallized using an SPE technique. In addition, the first and second upper body patterns 37 a and 37 b may be formed to overlap the first and second lower body patterns 21 a and 21 b, respectively. However, as shown in FIGS. 13A and 13B, the first and second upper body patterns 37 a and 37 b may be formed such that they do not overlap extensions of the first and second lower body patterns 21 a and 21 b. An insulated transfer gate pattern 42 may be formed to cross over the first and second upper body patterns 37 a and 37 b. The insulated transfer gate pattern 42 may comprise a word line pattern 42. The word line pattern 42 may comprise a word line 39 and a capping insulating layer pattern 41 which are sequentially stacked. Impurity ions may be implanted into the upper body patterns 37 a and 37 b using the word line pattern 42, for example, as an ion implantation mask. As a result, a first source region 45 s′ and a first drain region 45 d are formed in spaced apart portions of the first upper body pattern 37 a, and a second source region 45 s″ and a second drain region 45 d″ are formed in spaced apart portions of the second upper body pattern 37 b. The first source region 45 s′ and the first drain region 45 d′ may be self-aligned with the word line pattern 42. The second source region 45 s″ and the second drain region 45 d″ may also be self-aligned with the word line pattern 42. When, for example, the first and second drain regions 45 d′ and 45 d″ and the first and second source regions 45 s′ and 45 s″ have an LDD type structure, a word line spacer 43 may be formed on a sidewall of the word line pattern 42. The first and second drain regions 45 d′ and 45 d″ and the first and second source regions 45 s′ and 45 s″ may be N-type impurity regions.
As a result, a first inverter composed of the first driver transistor TD1 and the first load transistor TL1 is cross-coupled with a second inverter composed of the second driver transistor TD2 and the second load transistor TL2 by the node plugs 51 a and 51 b. A fourth interlayer insulating layer 53 may be formed on a top surface of the semiconductor substrate having the node plugs 51 a and 51 b. Alternatively, the first and second node plugs 51 a and 51 b may be formed to have another configuration which is different from the first and second node plugs 51 a and 51 b. FIG. 14C is a cross-sectional diagram that illustrates methods of forming first node plugs of SRAM cells in accordance with further embodiments of the present invention.
First and second ground line contact plugs 55 s′ and 55 s″ are formed in the first and second ground line contact holes 53 s′ and 53 s″ respectively. During formation of the ground line contact plugs 55 s′ and 55 s″, first and second power line contact plugs 55 c′ and 55 c″ may be formed in the first and second power line contact holes 53 c′ and 53 c″ respectively. The ground line contact plugs 55 s′ and 55 s″ and the first and second power line contact plugs 55 c′ and 55 c″ may be formed, for example, of a conductive layer that forms an ohmic contact with both P-type and N-type semiconductor materials. For example, the ground line contact plugs 55 s′ and 55 s″ and the first and second power line contact plugs 55 c′ and 55 c″ may be formed using the same methods as the methods described above with reference to FIGS. 14A and 14B for forming the node plugs 51 a and 51 b. A fifth interlayer insulating layer 57 may hten be formed on a top surface of the semiconductor substrate having the ground line contact plugs 55 s′ and 55 s″ and the power line contact plugs 55 c′ and 55 c″. As shown in FIGS. 8, 16A and 16B, ground lines 59 s and power lines 59 c may be formed in the fifth interlayer insulating layer 57 using, for example, a damascene technique. The ground lines 59 s and the power lines 59 c may be formed to be substantially parallel to the word line pattern 42. The ground lines 59 s may be formed over the unit cells arranged in odd rows (parallel with the x-axis), and the power lines 59 c may be formed over unit cells arranged in even rows. In further embodiments of the present invention, the ground lines 59 s may be formed over unit cells arranged in even rows and the power lines 59 c may be formed over the unit cells arranged in odd rows. The ground lines 59 s may cover the first and second ground line contact plugs 55 s′ and 55 s″, and the power lines 59 c may cover the first and second power line contact plugs 55 c′ and 55 c″. A sixth interlayer insulating layer 61 may then be formed on a top surface of the semiconductor substrate having the ground lines 59 s and the power lines 59 c. Referring to FIGS. 9, 17A and 17B, the third to sixth interlayer insulating layers 49, 53, 57 and 61 and the third etch stopper 47 may be etched to form first and second bit line contact holes 61 b′ and 61 b″. The first bit line contact hole 61 b′ may expose the first drain region 45 d′ of the first transfer transistor TT1, and the second bit line contact hole 61 b″ may expose the second drain region 45 d″ of the second transfer transistor TT2. First and second bit line contact plugs 63 b′ and 63 b″ may be formed in the first and second bit line contact holes 61 b′ and 61 b″ respectively. First and second parallel bit lines 65 b′ and 65 b″ may be formed on the sixth interlayer insulating layer 61. The first and second bit lines 65 b′ and 65 b″ may cross over the ground lines 59 s and the power lines 59 c. The first bit line 65 b′ may cover the first bit line contact plug 63 b′, and the second bit line 65 b″ may cover the second bit line contact plug 63 b″. Herein, reference is made to transistors (or other elements) that are �at� or �formed at� a semiconductor substrate (or other region). These terms are used to indicate that the transistor (or other element) is provided on and/or in the semiconductor substrate (or other region). Thus, for example, in some embodiments of the present invention, portions of the transistor (e.g., a source region, a drain region and/or a channel region) may be provided in the semiconductor substrate while other portions (e.g., a gate) is provided on the semiconductor substrate. In other embodiments, the transistor may be formed in its entirety on the substrate (such as may be the case with a semiconductor-on-insulator transistor). In each instance, the transistor would be �at� or �formed at� the semiconductor substrate.
Herein, reference is also made to a first transistor that �overlaps� a second transistor. A first transistor �overlaps� a second transistor if an axis exists that is perpendicular to the semiconductor substrate on which the transistors are formed that passes through any portion of both transistors (e.g., the gate, source and/or drain). In certain embodiments of the present invention, various of the transistors may have a more complete overlap of one or more additional transistors such that an axis exists that is perpendicular to the semiconductor substrate on which the transistors are formed that passes through the controlled terminal (e.g., the gate) of the first transistor and any portion of the second transistor. Herein, a second transistor that is configured in this matter is said to �overlap the gate� of the first transistor.
Herein, reference is further made to first and/or second �impurity regions� of various transistors. By the term �impurity region� it is meant a region of the transistor that includes intentionally doped or added impurities such as, for example, a semiconductor region that includes implanted impurity ions. The source and drain regions of a transistor, however formed, would each comprise an �impurity region.�
Various embodiments of the present invention that are described and claimed herein include �etch stopper� layers. These etch stopper layers may, for example, be provided to facilitate the etching of a first interlayer insulating layer that is provided on the etch stopper layer. It will be appreciated that the etch stopper may be implemented as a second interlayer insulating layer that is provided below the first interlayer insulating layer that is to be etched.
Herein reference is also made to �single crystalline� layers. By �single crystalline� it is meant that the material generally has the structure of a single crystal (i.e., has long range in its structure). �Single crystalline� layers are in contrast to polycrystalline layers, which are materials that have the structure of a collection of small crystals (somewhat similar to a honeycomb structure) and amorphous materials, which are materials that have no (long-range) order in its structure whatsoever (or combinations of polycrystalline and amorphous materials). Reference is also made herein to �single crystalline transistors.� This phrase refers to transistors having a channel that is formed in a single crystalline semiconductor layer or region.
Reference is also made herein to �bulk� transistors and �thin film� transistors. It will be appreciated by those of skill in the art that �bulk� transistors refer to transistors that include source/drain regions that are formed in a semiconductor substrate, whereas �thin film� transistors refer to transistors that are formed at layers of the device that are above the substrate.
Herein reference is also made to various types of �node plugs.� Herein, the term �node plug� refers to a conductive plug that electrically interconnects two or more electrical elements (e.g., transistors, capacitors, etc.) in a device.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5278459 *Nov 14, 1991Jan 11, 1994Kabushiki Kaisha ToshibaStatic semiconductor memory using thin film FETUS5308782Oct 26, 1992May 3, 1994MotorolaSemiconductor memory device and method of formationUS5554870Aug 2, 1995Sep 10, 1996Motorola, Inc.Integrated circuit having both vertical and horizontal devices and process for making the sameUS5675185 *Sep 29, 1995Oct 7, 1997International Business Machines CorporationSemiconductor structure incorporating thin film transistors with undoped cap oxide layersUS6022766Feb 10, 1997Feb 8, 2000International Business Machines, Inc.Semiconductor structure incorporating thin film transistors, and methods for its manufactureUS6172381 *Dec 22, 1998Jan 9, 2001Advanced Micro Devices, Inc.Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewallUS6429484 *Aug 7, 2000Aug 6, 2002Advanced Micro Devices, Inc.Multiple active layer structure and a method of making such a structureUS6888198 *Jun 4, 2001May 3, 2005Advanced Micro Devices, Inc.Straddled gate FDSOI deviceUS7109071 *Dec 8, 2003Sep 19, 2006Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and manufacturing method thereofUS7157305 *Mar 29, 2006Jan 2, 2007Micron Technology, Inc.Forming multi-layer memory arraysUS7276421 *Aug 5, 2005Oct 2, 2007Samsung Electronics Co., Ltd.Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated therebyUS20060197117 *Mar 7, 2006Sep 7, 2006Hyun-Su KimStacked semiconductor device and method of fabricationUS20060234487 *Apr 4, 2006Oct 19, 2006Samsung Electronics Co., Ltd.Method of forming semiconductor device having stacked transistorsUS20060237725 *Feb 28, 2006Oct 26, 2006Samsung Electronics Co., Ltd.Semiconductor devices having thin film transistors and methods of fabricating the sameKR20020058644A Title not availableKR20030002328A Title not availableKR20030060142A Title not availableKR20030063076A Title not available* Cited by examinerNon-Patent CitationsReference1English translation of Korean Office Action for corresponding Korean Patent Application No. 10-2004-0002088 mailed Dec. 22, 2006.2English translation of Korean Office Action for corresponding Korean Patent Application No. 10-2004-0002088 mailed Mar. 24, 2006.3Korean Office Action for corresponding Korean Patent Application No. 10-2004-0002088 mailed Dec. 22, 2006.4Korean Office Action for corresponding Korean Patent Application No. 10-2004-0002088 mailed Mar. 24, 2006.5Translation of German Office Action, Oct. 11, 2006, Application No. 10 2005 000 997.2-33.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7642555 *Apr 4, 2008Jan 5, 2010Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS7994582Oct 16, 2009Aug 9, 2011Samsung Electronics Co., Ltd.Stacked load-less static random access memory deviceUS20110101467 *Jan 7, 2011May 5, 2011Samsung Electronics Co., Ltd.Stacked semiconductor device and method of manufacturing the same* Cited by examinerClassifications U.S. Classification257/278, 257/E21.661, 438/153, 257/E27.026, 257/E27.111, 257/E27.1International ClassificationH01L27/11, H01L21/8244, H01L27/12, H01L27/06, H01L21/84, H01L27/02, H01L29/417, H01L21/768, H01L21/77, H01L29/41, H01L29/786Cooperative ClassificationH01L27/0688, H01L27/1108, H01L27/1214, H01L27/11, H01L27/12European ClassificationH01L27/11, H01L27/12T, H01L27/12, H01L27/06E, H01L27/11F2Legal EventsDateCodeEventDescriptionJun 26, 2012FPAYFee paymentYear of fee payment: 4May 13, 2005ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JANG, JAE-HOON;JUNG, SOON-MOON;KWAK, KUN-HO;AND OTHERS;REEL/FRAME:016217/0475Effective date: 20050103RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google