Source: http://www.google.com/patents/US20020056922?dq=4200770
Timestamp: 2013-12-10 23:55:16
Document Index: 740778979

Matched Legal Cases: ['arts 48', 'art 69', 'art 69', 'arts 73', 'arts 73', 'arts 74', 'arts 74', 'arts 74', 'arts 73', 'arts 75', 'arts 75', 'arts 75']

Patent US20020056922 - Semiconductor device, production method thereof, and coil spring cutting jig ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsA metal layer is formed on each surface of topside substrate electrodes on a substrate. Another metal layer is formed on each surface of chip electrodes on a function element chip. Both ends of vertical coil springs are connected to the topside substrate electrodes and the chip electrodes through the...http://www.google.com/patents/US20020056922?utm_source=gb-gplus-sharePatent US20020056922 - Semiconductor device, production method thereof, and coil spring cutting jig and coil spring guiding jig applied theretoPublication numberUS20020056922 A1Publication typeApplicationApplication numberUS 10/014,074Publication dateMay 16, 2002Filing dateNov 13, 2001Priority dateNov 15, 2000Publication number014074, 10014074, US 2002/0056922 A1, US 2002/056922 A1, US 20020056922 A1, US 20020056922A1, US 2002056922 A1, US 2002056922A1, US-A1-20020056922, US-A1-2002056922, US2002/0056922A1, US2002/056922A1, US20020056922 A1, US20020056922A1, US2002056922 A1, US2002056922A1InventorsTakuo Funaya, Sakae Kitajyo, Naoji Senba, Yuzo Shimada, Nobuaki TakahashiOriginal AssigneeNec CorporationExport CitationBiBTeX, EndNote, RefManReferenced by (9), Classifications (63), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device, production method thereof, and coil spring cutting jig and coil spring guiding jig applied theretoUS 20020056922 A1Abstract A metal layer is formed on each surface of topside substrate electrodes on a substrate. Another metal layer is formed on each surface of chip electrodes on a function element chip. Both ends of vertical coil springs are connected to the topside substrate electrodes and the chip electrodes through the metal layers, respectively. In this way, the topside substrate electrodes are connected to the chip electrodes through the vertical coil springs by means of flip hip bonding. Thereby, there is provided a semiconductor device having flip chip bonding structure, a production method thereof, a coil spring cutting jig and a coil spring guiding jig applied thereto, wherein: it is possible to prevent faulty connection caused by the thermal expansion difference between a function element device and a substrate; after a function element device and a substrate that are connected through a connection formation is separated from each other because a faulty point has been found in an electrical inspection after the tentative connection, it is possible to easily reconnect the function element device and the substrate; the configuration is simple and the packaging cost is low; and even if a high-power-consumption-type function element device is applied, it is possible to realize low thermal resistibility and high reliability of connection. Images(19) Claims(44)
DESCRIPTION OF THE PREFERRED EMBODIMENTS [0118] Referring now to the drawings, embodiments of the present invention will be explained in detail. First, an explanation will be given of a first embodiment of the present invention. FIG. 2 is a side view showing a configuration of a semiconductor device 46 a according to the first embodiment. The semiconductor device 46 a comprises a plurality of topside substrate electrodes 5 on a top surface of a substrate 6. A metal layer 3 about 0.01 to 0.1 μm thick is formed on each of the topside substrate electrodes 5. On each of the metal layers 3, there is made a vertical coil spring 4, which is connected to the topside substrate electrode 5 through the metal layer 3. The vertical coil spring 4 has spiral shape, and the axial thereof is vertical to the substrate 6. [0119] On an undersurface of a function element chip 1, a plurality of chip electrodes 2 are made. Besides, a metal layer 3 is formed under the chip electrode 2. Each of the chip electrodes 2 is connected to the vertical coil spring 4 through the metal layer 3. In this way, the function element chip 1 is connected to the substrate 6 through the chip electrodes 2, vertical coil springs 4 and topside substrate electrodes 5 by means of flip chip bonding. The function element chip 1 has a configuration wherein wiring is formed on a backing material that is, made of Si, GaAs, LiTaO3, LiNbO3, or crystal etc. Besides, it is preferable to use one selected from a printed board, organic material board or alumina board such as a flexible board, glass ceramic board, and ceramic board such as a glass board for the substrate 6, but not limited to those. Further, a thin membrane layer that comprises Ti and Pd, Cr and Pd, or Cr and Cu etc. are preferably used as the metal layer 3. Moreover, a conductive adhesive layer may be applied thereto. [0120] Next, an explanation will be given of a cutting jig 29 and a coil holder 37 used in manufacturing the semiconductor device 46 a according to this embodiment. FIGS. 3A to 3C show a configuration of the cutting jig 29 used in manufacturing the semiconductor device 46 a. FIG. 3A shows the plan view thereof, FIG. 3B shows the cross sectional view thereof, and FIG. 3C shows the front view thereof. The cutting jig 29 cuts a plurality of continuous coil springs, which are more than several times longer than the width of the chip electrode 2, into the width corresponding to that of the chip electrode 2 formed on the undersurface of the function element chip 1 or the width corresponding to distance between the function element chip 1 and the substrate 6 shown in FIG. 2. Thereby, plenty of divided coil springs (not shown) are made. [0121] As shown in FIGS. 3A to 3C, the cutting jig 29 is provided with a box 43 whose internal height is larger than an external diameter of a continuous coil spring 31. A plurality of jig holes 32 each of whose diameter is larger than the external diameter of the continuous coil spring 31 are made on one side 43 a of the box 43. The jig holes 32 are arranged in a line corresponding to the forming pitch of the chip electrodes 2 on the function element chip 1. Besides, a plurality of slit-shaped jig openings 30 are formed on a top surface 43 b that is vertical to the side 43 a and parallel to the arrangement direction of the jig holes 32. The plural jig openings 30 are formed at regular intervals in the arrangement direction of the jig holes 32. The intervals are approximately equal to the width of the chip electrode 2 or the distance between the function element chip 1 and the substrate 6. [0122]FIGS. 4A and 4B are cross sectional views each showing a configuration of the coil holder 37 used as the coil spring guiding jig according to this embodiment. FIG. 4A shows an operation of housing divided coil springs 44 into the coil holder 37. FIG. 4B shows an operation of guiding the divided coil springs 44 to the function element chip 1 from the coil holder 37. The coil holder 37 serves as a jig for guiding the divided coil springs 44 to the function element chip 1 or the substrate 6 in order to form the vertical coil springs 4. [0123] As shown in FIG. 4A, the coil holder 37 is provided with a housing 45. In the housing 45, a plurality of guide holes 36 each of which has cylindrical shape are made in parallel to each other. The diameter of the guide hole 36 is a little larger than the external diameter of the coil spring 44. The intervals of the guide holes 36 are equal to those of the jig holes 32 in the cutting jig 29 shown in FIGS. 3A to 3C, and equal to those of the chip electrodes 2. The guide hole 36 penetrates the housing 45. Besides, each guide holes 36 has an upper side opening 36 a and a bottom side opening 36 b at both ends thereof. As shown in FIG. 4A, the housing 45 houses and holds the plural coil springs 44 in each of the guide holes 36. Besides, a stopper 38 is placed at the foot of the housing 45. The stopper 38 functions so as not to drop the coil springs 44 held in the guide holes 36 from the bottom side openings 36 b. The stopper 38 has a backing 38 a and a plurality of projections 38 b. The plurality of projections 38 b are placed on one side of the backing 38 a so as to be matched with the guide holes 36. Further, the projections 38 b can be put into the guide holes 36. The stopper 38 is fixed to the housing 45 by intruding the projections 38 b into the bottom side openings 36 b. [0124] Besides, the stopper 38 can be detached from the housing 45. Further, it is possible to fit on a boost-up pin 40 to the housing 45 as a substitute for the stopper 38. As shown in FIG. 4B, the boost-up pin 40 has a flat backing 40 a and a plurality of pins 40 b. The plurality of pins 40 b are placed on one side of the backing 40 a so as to be matched with the guide holes 36. Further, the pins 40 b can be intruded into the guide holes 36. The boost-up pin 40 is inserted into the guide holes 36 from the bottom side openings 36 b. Then, the boost-up pin 40 pushes up the coil springs 44 by pressing the lower ends of the coil springs 44 housed in the guide holes 36. Thereby, the coil springs 44 are stuck out of the upper side openings 36 a of the guide holes 36. [0125] Next, an explanation will be given of a production method of the semiconductor device 46 a according to this embodiment. As shown in FIGS. 3a to 3 c, first, the continuous coil springs 31 are inserted into the box 43 of the cutting jig 29 through the jig holes 32. After that, laser 28 such as YAG (Yttrium Aluminum Garnet) laser or carbon dioxide laser is scanned at the position of the jig openings 30 or irradiated on all over the top surface 43 b from above the top surface 43 b of the box 43. Then, the laser 28 is taken in the inside of the box 43 through the jig openings 30. Thereby, the continuous coil springs 31 housed in the box 43 are cut into some pieces, and the plurality of coil springs 44 are made. [0126] Secondly, as shown in FIG. 4a, the stopper 38 is mounted at the foot of the coil holder 37. After that, the side where the upper side openings 36 a of the coil holder 37 are formed is contacted on the side 43 a of the cutting jig 29 so as to match the position of the upper side openings 36 a of the coil holder 37 with that of the jig holes 32 (refer to FIG. 3C) of the cutting jig 29. Then, the coil springs 44 are shifted from the box 43 of the cutting jig 29 to the guide holes 36 of the coil holder 37 through the jig holes 32 and the upper side openings 43 a. Thereby, a plurality of the coil springs 44 are housed in each of the guide holes 36, and piled up in a line along the axial of the guide holes 36. [0127] Thirdly, as shown in FIG. 4B, the stopper 38 is detached from the housing 45. After that, as a substitute for the stopper 38, the boost-up pin 40 is attached to the housing 45. [0128]FIG. 5 is a plan view showing a configuration of a wafer 24, on which plenty of the function element chips 1 are formed. A plurality of the chip electrodes 2, each on which barrier metal is formed, are set on the surface of each of the function element chips 1. [0129] As shown in FIG. 4B, fist, a heating-absorbing head 39 executes heating, pressurization and positioning to the wafer 24 while absorbing and holding the wafer 24. Thereby, the wafer 24 is absorbed and positioned above the coil holder 37. Secondly, by shifting the boost-up pin 40 upward on the coil holder 37, the pins 40 b press the foot of the coil springs 44 piled up in a line in the guide holes 36 and boost up the coil springs 44. Thereby, the coil springs 44 put in the top position in the guide holes 36 are stuck out of the upper side openings 36 a of the guide holes 36. [0130] Thirdly, the stuck-out coil springs 44 are contacted to the chip electrodes 2 on the function element chip 1 on the wafer 24. Then, the heating-absorbing head 39 executes heating reflow to the metal layers 3. Then, the coil springs 44 are joined to the chip electrodes 2. Thereby, the vertical coil springs 4 are formed on the chip electrodes 2. By repeating the above operations, the vertical coil springs 4 are formed on the plenty of the function element chips 1 on the wafer 24. [0131] Fourthly, the wafer 24 is diced and divided into each of the function element chips 1. FIG. 6 is a side view showing a configuration of the function element chip 1 that has the vertical coil springs 4 on the face thereof formed by the above operations. A plurality of the chip electrodes 2 are formed on the face of the function element chip 1. The metal layers 3 are formed on the chip electrodes 2. The vertical coil springs 4 are connected to the chip electrodes 2 through the metal layers 3. [0132] Fifthly, the vertical coil springs 4 on the function element chip 1 shown in FIG. 6 is contacted to the metal layers 3 on the substrate 6 that has the top side substrate electrodes 5 on which the metal layers 3 are formed as shown in FIG. 2. After that, heating reflow is executed to the metal layers 3 on the topside substrate electrodes 5. Then, the vertical coil springs 4 are connected to the topside substrate electrodes 5 through the metal layers 3. Thereby, there is obtained the semiconductor device 46 a. [0133] In this embodiment, the function element chip 1 is connected to the substrate 6 through the vertical coil springs 4. Thereby, it is possible to absorb the stress concentration caused by the thermal expansion difference between the materials forming the function element chip 1 and forming the vertical coil springs 4 by the spring characteristics of the vertical coil springs 4. Therefore, it is possible to obtain flip chip bonding structure wherein reliability of connection is high. Besides, in selecting materials used for the function element chips 1 and the substrate 6, there is no need to take account of the difference of thermal expansion coefficient. Therefore, it is possible to enhance design flexibility of a semiconductor device and to make it easy to design a semiconductor device. [0134] Besides, by the cutting jig 29, the continuous coil springs 31 can be cut into divided coil springs 44 at a time. Therefore, it is possible to produce the coil springs 44 of equal length with a high degree of accuracy and efficiency. [0135] Further, by the coil holder 37, the microscopic coil springs 44 can be guided onto the chip electrodes 2 of the function element chip 1 easily and efficiently. Thereby, it is possible to connect a plurality of the coil springs 44 to the function element chips 1 at a time. Consequently, it is possible to form the vertical coil springs 4 efficiently with a low cost. [0136] In this embodiment, there is shown an example that the wafer 24 is diced into each of the function element chips 1 after the vertical coil springs 4 are formed on the function element chips 1. Incidentally, it is also possible to form the vertical coil springs 4 on the function element chips 1 after the wafer 24 is diced into each of the function element chips [0137] In addition, in this embodiment, there is shown an example that the vertical coil springs 4 are connected to the substrate 6 after the vertical coil springs 4 are formed on the function element chips 1. Incidentally, by the same method as shown in this embodiment, it is possible to connect the function element chips 1 to the vertical coil springs 4 after forming the vertical coil springs 4 on the top side substrate electrodes 5 on the substrate 6. [0138] Further, in this embodiment, there is shown an example of connecting the coil springs 44 to the metal layers 3 by means of the heating reflow. Incidentally, it is possible to connect them by means of thermal compression bonding, ultrasonic or scrub etc. other than the heating reflow. [0139] Next, an explanation will be given of a second embodiment of the present invention. FIG. 7 is a side view showing a configuration of a semiconductor device 46 b according to this embodiment. Besides, FIG. 8A is a plan view showing a shape of a coil spring 67 in the semiconductor device 46 b, and FIG. 8B is the side view thereof. As shown in FIG. 7, in the semiconductor device 46 b, there are placed the coil springs 67 cut into length not greater than 1 pitch as substitutes for the vertical coil springs 4 in the semiconductor 46 a of the first embodiment shown in FIG. 2. The chip electrodes 2 of the function element chip 1 are connected to the topside substrate electrodes 5 of the substrate 6. [0140] As shown in FIGS. 8A and 8B, as viewed from the axial, the angle between the both ends of the coil spring 67 (hereinafter, referred to as the center angle θ) is not greater than 360 degrees. Namely, when 1 pitch is 360 degrees, the center angle θ of the coil spring is not greater than 1 pitch, which is used in this embodiment. As viewed from the axial, the shape of the coil spring 67 shows a sectoral circumference as shown in FIG. 8A. On the other hand, as viewed from the direction vertical to the axial, the shape of the coil spring 67 shows a V-shaped one as shown in FIG. 8B. The configuration of the semiconductor device 46 b is the same as that of the semiconductor 46 a in the above-described first embodiment except for the coil spring 67. [0141] The coil spring 67 is formed by cutting the continuous coil spring 31 into the length not greater than 1 pitch by, for example, the cutting jig 29 shown in FIGS. 3A to 3C. The production method of the semiconductor device 46 b of this embodiment is the same as that of the semiconductor device 46 a of the first embodiment except for the production method of the coil spring 67. [0142] According to this embodiment, the coil spring 67 is cut into not greater than 1 pitch. Thereby, it is possible to connect the function element chip 1 to the substrate 6 wherein less inductance and less electric noise are generated compared to the first embodiment. [0143] Besides, FIG. 9 is a side view showing a configuration of a semiconductor device 46 c as a deformed example of this embodiment. In the semiconductor device 46 c, coil springs 68 are provided as substitutes for the coil springs 67 for the semiconductor device 46 b shown in FIG. 7. The coil springs 68 are the same as the coil springs 67 except that the axial runs in the parallel direction (hereinafter, referred to as in the horizontal direction) to the face of the substrate 6. Hereby, it is possible to connect the function element chip 1 to the substrate 6 in the semiconductor device 46 c wherein much less inductance and much less electric noise are generated compared to the semiconductor device 46 b. [0144] Next, an explanation will be given of a third embodiment of the present invention. FIG. 10 is a side view showing a configuration of a semiconductor device 46 d according to this embodiment. In the semiconductor device 46 d, there is provided a configuration that a mother board 9 is connected to the semiconductor device 46 a shown in FIG. 2. The mother board 9 of the semiconductor device 46 a is provided with mother board electrodes 8 on its top surface. The metal layers 3 about 0.01 to 0.1 μm thick are formed on each of the mother board electrodes 8. The mother board 9 is used in order to mount the substrate 6 to which the function element chip 1 is connected. The substrate 6 is set above the mother board 9. A plurality of the topside substrate electrodes 5 and a plurality of backside substrate electrodes 7 are formed on the top surface and under surface of the substrate 6, respectively. The metal layers about 0.01 to 0.1 μm thick are formed on the top side substrate electrodes 5 and the backside substrate electrodes 7. The vertical coil springs 4 are placed between the mother board electrodes 8 and the backside substrate electrodes 7. The both ends of the vertical coil springs 4 are connected to the metal layers 3 formed on the mother board electrodes 8 and those formed on the backside substrate electrodes 7, respectively. Each of the vertical coil springs 4 has spiral shape, and the axial thereof runs in the vertical direction. [0145] Besides, other vertical springs 4 are placed on the metal layers 3 formed on the topside substrate electrodes 5. The vertical springs 4 are connected to the topside substrate electrodes 5 through the metal layers 3. The function element chip 1 is set above the vertical coil springs 4. A plurality of the chip electrodes 2 are formed on the undersurface of the function element chip 1. The metal layers 3 are formed under the chip electrodes 2. The chip electrodes 2 are connected to the vertical coil springs 4 through the metal layers 3. In this way, the function element chip 1 is connected to the substrate 6 through the chip electrodes 2, vertical coil springs 4 and topside substrate electrodes 5 by means of flip chip bonding. [0146] Incidentally, the materials for the function element chip 1, substrate 6 and metal layers 3 in this embodiment are the same as those in the above-described first embodiment. [0147] Next, an explanation will be give of a cutting jig 47 used in producing the semiconductor device 46 d according to this embodiment. FIGS. 11A and 11B show a configuration of the cutting jig 47. FIG. 11A shows a cross sectional view thereof. FIG. 11B shows a front view thereof. The cutting jig 47 cuts the continuous coil springs 31 into the length corresponding to the width of the chip electrode 2 formed on the undersurface of the function element chip 1, the distance between the function element chip 1 and the substrate 6, the width of the mother board electrode 8, or the distance between the substrate 6 and the mother board 9 shown in FIG. 10. Thereby, the cutting jig 47 forms plenty of the divided coil springs 44 shown in FIG. 4A. [0148] As shown in FIGS. 11A and 11B, the cutting jig 47 comprises a plurality of cutting jig transparent tubes 33 within a tube holder 35. The internal diameter of the cutting jig transparent tube 33 is a little larger than the external diameter of the coil spring 44. The cutting jig transparent tubes 33 are arranged in a line and in parallel to each other. The arranging pitch thereof is the same as the forming pitch of the chip electrodes 2 of the function element chip 1. The tube holder 35 and the cutting jig transparent tubes 33 are made of a transparent material through which the laser 28 can transmit. Each shape of the cutting jig transparent tubes 33 is tube like shape and has openings at the both sides thereof. Inside the cutting jig transparent tube 33 forms a tube hole 34. [0149] Next, an explanation will be given of the production method of the semiconductor device 46 d according to this embodiment. First, as shown in FIG. 11, the continuous coil springs 31 are inserted into the tube holes 34 of the cutting jig 47. [0150] Secondly, the laser 28 is irradiated on the tube holder 35 from the direction orthogonal to the side of the cutting jig transparent tubes 33 in the axial direction of the cutting jig transparent tubes 33 at prescribed pitch. For one thing concerned with an irradiating method of the laser 28, there is a method to scan the laser 28 in the direction orthogonal to the axial of the cutting jig transparent tubes 33. The laser 28 is arranged in several lines and in the axial direction of the cutting jig transparent tubes 33. For another, there is a method to set a shielding mask (not shown) so as to cover a face of the tube holder 35 that is irradiated by the laser 28. The shielding mask has slit-shaped openings and stretches in the direction orthogonal to the axial of the cutting jig transparent tubes 33. Then, the laser 28 is irradiated on the whole shielding mask. The laser 28 transmits through the tube holder 35 and the cutting jig transparent tubes 33, reaches to the continuous coil springs 31, and cuts the continuous coil springs 31. Thereby, the coil springs 44 cut into several pieces shown in FIG. 4A are made up. [0151] Thirdly, the upper side openings 36 a of the coil holder 37 shown in FIGS. 4A and 4B are contacted to the tube holes 34 of the cutting jig 47. Then, the coil springs 44 housed in the tube holes 34 are shifted to the guide holes 36 of the coil holder 37. [0152] Fourthly, as shown in FIG. 4B and FIG. 10, by using the coil holder 37 in the same way as the above-described first embodiment, the coil springs 44 are connected to the mother board electrodes 8 on the mother board 9 through the metal layers 3, and thereby, the vertical coil springs 4 are formed. Fifthly, the substrate 6 is set above the vertical coil springs 4. Then, the backside substrate electrodes 7 having metal layers 3 and formed on the undersurface of the substrate 6 are connected to the top of the vertical coil springs 4. [0153] Sixthly, by applying the same method as the above-described first embodiment, the vertical coil springs 4 are formed on the substrate 6. The function element chip 1 is set above the coil springs 4. Then, the chip electrodes 2 formed on the undersurface of the function element chip 1 are connected to the vertical coil springs 4 formed above the substrate 6 through the metal layers 3. In this way, the semiconductor device 46 d according to this embodiment is formed. [0154] The semiconductor device 46 d according to this embodiment has vertical coil springs 4 between the function element chip 1 and the substrate 6, and between the substrate 6 and the mother board 9. Thereby, it is possible to relieve stress caused by the thermal expansion difference between the function element chip 1 and the substrate 6, and between the substrate 6 and the mother board 9. Therefore, it is possible to enhance reliability of connection between the function element chip 1 and the substrate 6, and between the substrate 6 and the mother board 9. Further, it is possible to enhance design flexibility of a semiconductor device. [0155] Besides, the cutting jig 47 is used in this embodiment. Thereby, it is possible to form the coil springs 44 with a high degree of accuracy at a time. Further, by shifting all of the plenty of coil springs 44 housed in the tube holes 34 of the cutting jig 47 into the coil holder 37, it is possible to easily handle the coil springs 44 that are hard to handle because of their imperceptibility. [0156] Incidentally, while there is shown an example of using the cutting jig 47 in order to cut the continuous coil springs 31 and form the coil springs 44 in this embodiment, it is also possible to use the cutting jig 29 as shown in FIGS. 3A to 3C. Besides, it is possible to use the cutting jig 47 in the above-described first and second embodiments. [0157] Next, an explanation will be given of a fourth embodiment of the present invention. FIG. 12 is a side view showing a configuration of a semiconductor device 46 e according to this embodiment. The semiconductor device 46 e has a configuration that horizontal coil springs 10 are used as substitutes for the vertical coil springs 4 used in the semiconductor device 46 a in the first embodiment shown in FIG. 2. The horizontal coil springs 10 are the same as the coil springs 44 except that the axial runs in the horizontal direction. The function element chip 1 is connected to the substrate 6 through the horizontal coil springs 10. The configuration of the semiconductor device 46 e is the same as that of the semiconductor device 46 a in the first embodiment shown in FIG. 2 except for the horizontal coil springs 10. [0158] Next, an explanation will be given of the production method of the semiconductor device 46 e according to this embodiment. FIGS. 13A to 13C are side views that shows the production method of the semiconductor device 46 e in order of its manufacturing process. First, as shown in FIG. 13A, the chip electrodes 2 are formed on the function element chip 1 on the wafer 24 shown in FIG. 5 and the metal layers 3 are formed thereon. Then, the horizontal coil springs 10 connected to each other by coil spring connecting leads 25 are arranged so that the axial runs in a direction parallel to the face of the function element chip 1 (namely, in a horizontal direction). After that, by executing heating reflow to the metal layers 3, the horizontal coil springs 10 are connected to the chip electrodes 2. [0159] Secondly, as shown in FIG. 13B, photosensitive resist 26 is embrocated on the function element chip 1 so as to cover the chip electrodes 2, the metal layers 3 and a plurality of the horizontal coil springs 10 connected to each other by the coil spring connecting leads 25. Then, by developing the photosensitive resist 26 after exposing it, the coil spring connecting leads 25 are exposed from the photosensitive resist 26. [0160] Thirdly, as shown in FIG. 13C, the coil spring connecting leads 25 are eliminated by etching. Thereby, each of the horizontal coil springs 10 is separated. In this process, the horizontal coil springs 10 are shielded from etching by the photosensitive resist 26. Then, the photosensitive resist 26 is eliminated, and the wafer 24 is diced into function element chips 1. [0161] After that, as shown in FIG. 12, the semiconductor device 46 e is formed by connecting the substrate 6 to the horizontal coil springs 10. [0162] The materials for the function element chip 1, substrate 6 and metal layers 3 used in the semiconductor device 46 e shown in this embodiment are the same as those in the first embodiment. Besides, in this embodiment, there is shown an, example of connecting the horizontal coil springs 10 to the metal layers 3 by heating reflow. However, it is as well possible to make the connection by means of thermo compression bonding, ultrasonic, scrub etc. [0163] In this embodiment, the function element chip 1 is connected to the substrate 6 through the horizontal coil springs 10. Thereby, stress concentration on connecting areas caused by the thermal expansion difference between the function element chip 1 and the substrate 6 is absorbed by the spring characteristics of the horizontal coil springs 10. Therefore, it is possible to enhance reliability of flip chip bonding between the function element chip 1 and the substrate 6. In addition, it becomes easy to select the materials for the function element chip 1 and the substrate 6. [0164] Besides, compared to the first embodiment, the horizontal coil springs 10 are connected to the chip electrodes 2 and the topside substrate electrodes 5 at several points, respectively. Thereby, it is possible to absorb stress acting in a horizontal direction effectively. Besides, it is possible to enhance reliability of connection between the horizontal coil springs 10 and the chip electrodes 2, and between the horizontal coil springs 10 and the topside substrate electrodes 5. Further, electric noise generated at the horizontal coil springs 10 is reduced. [0165] Further, in this embodiment, the horizontal coil springs 10 connected to each other by the coil spring connecting leads 25 can be joined to a plurality of the chip electrodes 2 at a time. After that, the coil springs connecting leads 25 are eliminated. Thereby, it is possible to form the horizontal coil springs 10 on each of the chip electrodes 2 with a high degree of accuracy and efficiency at a lower cost. [0166] Next, an explanation will be given of a fifth embodiment of the present invention. FIG. 14 is a side view showing a configuration of a semiconductor device 46 f in this embodiment. The semiconductor device 46 f has the same configuration as that of the semiconductor device 46 d except for the horizontal coil springs 10 substituting for the vertical coil springs 4 in the semiconductor device 46 d in the third embodiment shown in FIG. 10. [0167] Next, an explanation will be given of a production method of the semiconductor device 46 f according to this embodiment. FIG. 15 is a diagram illustrating the production method of the semiconductor device 46 f. First, as shown in FIG. 15, the chip electrodes 2 are formed on the function element chip 1 on the wafer 24 shown in FIG. 5. Then, the metal layers 3 are formed on the chip electrodes 2. Secondly, on the metal layers 3, a plurality of the horizontal coil springs 10 connected to each other by the coil spring connecting leads 25 are set so that the axial runs in a horizontal direction. Thirdly, the horizontal coil springs 10 are connected to the chip electrodes 2 by executing heating reflow to the metal layers 3. [0168] Fourthly, by irradiating the laser 28 such as YAG laser or carbon dioxide laser to the coil spring connecting leads 25, the coil spring connecting leads 25 are cut. Thereby, the horizontal coil springs 10 are separated. Fifthly, the wafer 24 is diced into each of the function element chips 1. [0169] On the other hand, by the same method as that shown in FIG. 15, other horizontal coil springs 10 are formed on the mother board electrodes 8 (refer to FIG. 10) on the mother board 9. [0170] Sixthly, as shown in FIG. 14, the substrate 6 is set above the mother board 9. Then, the backside substrate electrodes 7 formed on the undersurface of the substrate 6 are connected to the horizontal coil springs 10 on the mother board electrodes 8. Seventhly, the function element chip 1 on which the horizontal coil springs 10 are formed by the above-described process is set above the substrate 6. Then, the horizontal coil springs 10 are connected to the top side substrate electrodes 5 formed on the top surface of the substrate 6. Thereby, the semiconductor device 46 f is formed. [0171] According to this embodiment, the mother board 9 is connected to the substrate 6 through the horizontal coil springs 10. Thereby, the horizontal coil springs 10 can absorb the thermal expansion difference between the mother board 9 and the substrate 6. Therefore, it is possible to enhance reliability of connection. Besides, compared to the semiconductor device 46 d in the third embodiment, there is obtained a semiconductor device capable of absorbing stress acting in a horizontal direction in which generation of electric noise is reduced, and further, reliability of connection is excellent. [0172] Besides, in this embodiment, the laser 28 cuts the coil spring connecting leads 25. Thereby, compared to the fourth embodiment, it is possible to simplify the necessary process in cutting the coil spring connecting leads 25. [0173] Incidentally, in this embodiment, there is shown a method of cutting the coil spring connecting leads 25 by the laser 28. Further, it is possible to produce the semiconductor device 46 f by means of cutting the coil spring connecting leads 25 by etching shown in the fourth embodiment. Besides, it is also possible to produce the semiconductor device 46 e shown in the fourth embodiment by the method of cutting the coil spring connecting leads 25 by the laser 28 as shown in this embodiment. [0174]FIG. 16 is a pattern diagram showing a production method of a semiconductor device as a deformed example of the fifth embodiment. In this deformed example, metal that has good wettability is previously plated on the connecting areas of the horizontal coil springs 10, namely, plating parts 48 shown in FIG. 16. It is preferable to use a metal or a metal alloy comprising more than one selected from Au, Cu, Pb, Ag, Sn and Pd to the plating metal. Further, it is also preferable to use a double-layer membrane of Sn and Pb etc. to the plating metal. The preferable thickness of the plating is about 0.2 to 10 μm. Besides, there are some plating methods applicable to this deformed example, for example, an electrolytic plating method, dip method, vapor deposition method etc. Thereby, it is possible to further improve the connection between the horizontal coil springs 10 and the chip electrodes 2, topside substrate electrodes 5, backside substrate electrodes 7 and mother board electrodes 8. [0175] Next, an explanation will be given of a sixth embodiment of the present invention. FIG. 17 is a side view showing a configuration of a semiconductor device 46 g in this embodiment. The semiconductor device 46 g is made by substituting some pieces of vertical coil springs 4 used in the semiconductor 46 a in the first embodiment with the horizontal coil springs 10, and substituting the substrate 6 with the mother board 9. The semiconductor device 46 g has the mother board 9 on which a plurality of the mother board electrodes 8 are formed. The metal layer 3 is formed on each of the mother board electrodes 8. Besides, the vertical coil springs 4 are formed on some of the mother board electrodes 8. The horizontal coil springs 10 are formed on the rest of the mother board electrodes 8. Further, the function element chip 1, which has the chip electrodes 2 on the undersurface thereof, is set above the vertical coil springs 4 or the horizontal coil springs 10. The metal layers 3 are formed under the chip electrodes 2 of the function element chip 1. Besides, the metal layers 3 are connected to the mother board electrodes 8 through the vertical coil springs 4 or the horizontal coil springs 10. Incidentally, the function element chip 1 and the metal layers 3 are made of the same materials as those in the first embodiment. [0176] Next, an explanation will be given of a production method of the semiconductor device 46 g in the sixth embodiment. FIG. 18 is a cross sectional view showing the production method of the semiconductor device 46 g in this embodiment. As shown in FIG. 18, first, V-shaped grooves 41 are formed on a surface of a silicon substrate by lithography or anisotropic etching. Thereby, a silicon template 42 that has the V-shaped grooves 41 on the surface of the silicon substrate is manufactured. The arranging pattern of the V-shaped grooves 41 is the pattern that the arranging pattern of the chip electrodes 2 of the function element chip 1 is reversed. [0177] Secondly, the horizontal coil springs 10 connected to each other by the coil spring connecting leads 25 are placed in some of the V-shaped grooves 41 on the silicon template 42 so that each axial runs in a horizontal direction. Thirdly, by using the heating-absorbing head 39 shown in FIG. 4B, the function element chip 1 having the chip electrodes 2 on the undersurface thereof is absorbed. Then, the function element chip 1 is placed above the horizontal coil springs 10 and the chip electrodes 2 are contacted to the horizontal coil springs 10. Then, some of the chip electrodes 2 are connected to the horizontal coil springs 10 by executing heating reflow to the metal layers 3 formed on the surface of the chip electrodes 2. [0178] Fourthly, the coil spring connecting leads 25 are cut by applying the method shown in FIGS. 13B and 13C, or FIG. 15. [0179] Fifthly, the vertical coil springs 4 are formed on the rest of the chip electrodes 2 by the same method as shown in the first embodiment. Then, the horizontal coil springs 10 and the vertical coil springs 4 formed by the above means are connected to the mother board electrodes 8 on the mother board 9. Thereby, there is formed the semiconductor device 46 g shown in FIG. 17. [0180] In this invention, the function element chip 1 is connected to the mother board 9 through the vertical coil springs 4 and the horizontal coil springs 10. Thereby, stress, which is generated by the thermal expansion difference between the materials for the function element chip 1 and the mother board 9, and whose intensity and direction vary according to the positions of connected areas, can be absorbed by the spring characteristics of the vertical coil springs 4 and the horizontal coil springs 10 effectively. Therefore, it is possible to enhance reliability of the flip chip bonding between the function element chip 1 and the mother board 9. Besides, it becomes easy to select materials for the function element chip 1 and the mother board 9. [0181] Besides, in this embodiment, the silicon template 42 having the V-shaped grooves 41 thereon is applied. Thereby, it is possible to locate the horizontal coil springs 10 with high degree of accuracy. Therefore, the horizontal coil springs 10 are connected to the function element chip 1 with a high degree of accuracy at a time. [0182] Incidentally, the use of the silicon template 42 shown in this embodiment may be applied to the above-described fourth and fifth embodiment. Besides, by using the silicon template 42, it is possible to connect the horizontal coil springs 10 not only to the function element chip 1 but also to the mother board 9 and the substrate 6. [0183] Next, an explanation will be given of a seventh embodiment of the present invention. FIG. 19 is a side view showing a configuration of a semiconductor device 46 h in this embodiment. As shown in FIG. 19, the semiconductor device 46 h has a configuration that the function element chip 1 is connected to the mother board 9 through two or more different kinds of coil springs arranged in two or more different direction by means of flip chip bonding. Namely, the chip electrodes 2 are connected to the mother board electrodes 8 electrically and mechanically through the vertical coil springs 4, another kind of vertical coil springs 69, and the horizontal coil springs 10 etc. [0184]FIG. 20 is a side view showing the shape of the vertical coil spring 69. As shown in FIG. 20, the vertical coil spring 69 has two parts that radii are different, namely, a small radial part 69 a and a large radial part 69 b. The production method of the semiconductor device 46 h in this embodiment is the same as that shown in the sixth embodiment. [0185] In the seventh embodiment, the function element chip 1 is connected to the mother board 9 through two or more different kinds of coil springs arranged in two or more different direction. Thereby, it is possible to effectively relax stress concentration on connecting areas, whose intensity and direction vary according to the positions of connecting areas. Besides, by arranging a plurality of coil springs in various directions, it is possible to relieve stress added to the connecting areas from whole of the semiconductor device in either direction isotropically. In this embodiment, it is also possible to use two or more springs whose elastic constants are different. [0186]FIGS. 21A and 21B are side views showing shapes of coil springs as a first deformed example of the seventh embodiment. A coil spring 70 a shown in FIG. 21A has a triangular shape by joining three horizontal coil springs 10. Besides, a coil spring 70 b shown in FIG. 21B has a quadrangular shape joining four horizontal coil springs 10. In this deformed embodiment, in the process of manufacturing the semiconductor device 46 h shown in FIG. 19, after the coil spring 70 a and the coil spring 70 b are connected to the chip electrode 2, the coil spring 70 a and the coil spring 70 b are cut. Thereby, it is possible to connect a plurality of horizontal coil springs 10 each of which has different axial to the chip electrodes 2 at a time. Incidentally, the configuration of the semiconductor device in this deformed embodiment is the same as that of the semiconductor device 46 h shown in FIG. 19. [0187] Besides, FIGS. 22A to 22C and FIGS. 23A to 23C are pattern diagrams showing shapes of vertical coil springs as a second deformed example of the seventh embodiment. A pitch of a narrow-pitched coil spring 71 shown in FIG. 22A is narrower than that of the vertical coil spring 4. On the other hand, a pitch of a wide-pitched coil spring 72 shown in FIG. 22B is wider than that of the vertical coil spring 4. An intermittent coil spring 73 shown in FIG. 22C has coil parts 73 a and liner parts 73 b. An intermittent coil spring 74 shown in FIG. 23A also has coil parts 74A and liner parts 74 b. However, the position of the liner parts 74 b is different from that of the liner parts 73 b viewed from each axial thereof. An intermittent coil spring 75 shown in FIG. 23B has narrow-pitched parts 75 a, wide-pitched parts 75 b, and liner parts 75 c. Concerned with an intermittent coil spring 76 shown in FIG. 23C, the radius changes periodically and continuously. By using these various shapes of coil springs, it is possible to optimize the spring constants of the coil springs, not fixed value, according to the intensity and direction of the stress added to the coil springs. [0188] Next, an explanation will be given of an eighth-embodiment of the present invention. FIG. 24 is a side view showing a configuration of a semiconductor device 46 i in this embodiment. The configuration of the semiconductor device 46 i is the same as that of the semiconductor device 46 d shown in FIG. 10 except for conductive bumps 11 substituting for the vertical coil springs 4 between the substrate 6 and the mother board 9. [0189] When the stress caused by the thermal expansion difference between the substrate 6 and the mother board 9 is not too large, the substrate 6 is connected to the mother board 9 through the conductive bumps 11 as shown in the eighth embodiment. Thereby, it is possible to enhance shockproof between the substrate 6 (carrier substrate) and the mother board 9. Therefore, there is obtained a semiconductor device having the flip chip bonding structure wherein shockproof and reliability of connection are high. In addition, it becomes easy to select the configuration, materials etc. for the function element chip 1, substrate 6 and mother board 9. Incidentally, in this embodiment, while there is shown an example of using the vertical coil springs 4 in connecting the function element chip 1 and the substrate 6, it is also possible to use the horizontal coil springs. [0190] Next, an explanation will be given of a ninth embodiment of the present invention. FIG. 25 is a cross sectional view showing a configuration of a semiconductor device 46 j in this embodiment. As shown in FIG. 25, the semiconductor device 46 j is configured with a heatsink 12 and the semiconductor device 46 e shown in FIG. 12. Namely, the horizontal coil springs 10 are placed on the substrate 6. The function element chip 1 is set above the horizontal coil springs 10. The function element chip 1 is connected to the substrate 6 through the horizontal coil springs 10. Then, the heatsink 12 is connected to the backside of the function element chip 1, namely, the side to which the horizontal coil springs 10 are not connected with a jointing material such as a highly thermal conductive resin, solder or Au�Si (not shown). The jointing material is not limited to the material whose thermal expansion coefficient is low or matched to a thermal expansion coefficient of the material for connecting bumps. The jointing material may be the one having an arbitrary characteristic. [0191] Besides, the package structure between the heatsink 12 and the substrate 6 is that a spacer 14 is fixed by a bolt 13 in order to adjust the interval between the heatsink 12 and the substrate 6. Namely, the spacer 14 is placed between the heatsink 12 and the substrate 6 so that the bolt 13 can penetrate the substrate 6 and the spacer 14 in this order and reach to the heatsink 12. Thereby, the substrate 6 and the spacer 14 are joined to the heatsink 12. Further, the space sealed by the heatsink 12, spacer 14 and substrate 6 is filled up with inert gas. [0192] In the ninth embodiment, the heatsink 12 is directly joined to the backside of the function element chip 1. Thereby, even if the function element chip 1 is high power consumption type, the heatsink 12 can give off heat generated by the function element chip 1 effectively. Besides, the horizontal coil springs 10 can absorb stress caused by the thermal expansion difference between the heatsink 12 and the substrate 6, and between the function element chip 1 and the substrate 6. Thereby, with this configuration, there is no need to take account of the stress. Therefore, it becomes unnecessary to subtly adjust the size of the spacer 14 and change the material applied thereto in consideration of the thermal expansion difference. Thereby, it is possible to broaden the options on the structure of the function element chip 1, substrate 6, heatsink 12 etc. In addition, it becomes easier to fit them and thus enabling the simplification of the structure of a semiconductor device with a heatsink. Further, there is obtained a flip-chip type semiconductor device whose packaging cost is low and in which high-power-consumption-type function element is mounted. Incidentally, the vertical coil springs 4 may be used as substitutes for the horizontal coil springs 10. [0193] Next, an explanation will be given of a tenth embodiment of the present invention. FIG. 26 is a cross sectional view showing a configuration of a semiconductor device 46 k in this embodiment. As shown in FIG. 26, a package 15 having a cavity 15 a is set in the semiconductor device 46 k. The substrate 6 is mounted at the bottom of the cavity 15 a of the package 15. The horizontal coil springs 10 are placed on the substrate 6. The function element chip 1 is set above the horizontal coil springs 10. The function element chip 1 is connected to the substrate 6 through the horizontal coil springs 10. The configuration between the substrate 6 and the function element chip 1 are the same as that of the semiconductor device 46 e shown in FIG. 12. [0194] Besides, the heatsink 12 is connected to the backside of the function element chip 1, namely, the side to which the horizontal coil springs 10 are not connected with a jointing material such as a highly thermal conductive resin, solder or Au�Si (not shown). The jointing material is not limited to the material whose thermal expansion coefficient is low or matched to a thermal expansion coefficient of the material for connecting bumps. The jointing material may be the one having an arbitrary characteristic. [0195] Further, the semiconductor device 46 k has a package configuration wherein the heatsink 12 is adhered or mechanically joined to the package 15. The package 15 has a plurality of lead pins 16 that are connected to the substrate 6. Besides, the space sealed by the heatsink 12 and the package 15 is filled up with inert gas. [0196] In this embodiment, the package 15 having the cavity 15 a is used in the semiconductor device 46 k. Thereby, compared to the semiconductor device 46 j in the ninth embodiment shown in FIG. 25, a simpler configuration can be achieved. Besides, the horizontal coil springs 10 can absorb stress caused by the thermal expansion difference between the function element chip 1 and the substrate 6, and between the heatsink 12 and the package 15. Thereby, there is no need to take account of the stress. Therefore, it becomes unnecessary to subtly adjust the depth of the cavity 15 a of the package 15 and change the material applied thereto in consideration of thermal expansion difference. Thereby, it becomes possible to simplify structure of the function element chip 1, substrate 6, heatsink 12 etc. and fit them easily. Incidentally, the vertical coil springs may be used in this embodiment. [0197] Next, an explanation will be given of an eleventh embodiment of the present invention. FIGS. 27A and 27B are side view showing a configuration and a production method of a semiconductor device in this embodiment, respectively. As shown in FIG. 27B, the function element chip 1 is connected to the substrate 6 through two vertical coil springs, namely, the vertical coil spring 4 and the vertical coil spring 69. The configuration of the semiconductor device in this embodiment is the same as that of the semiconductor device 46 a in the first embodiment shown in FIG. 2 except for the vertical coil spring 4 and the vertical coil spring 69. [0198] Next, an explanation will be given of a production method of the semiconductor device in the eleventh embodiment. First, as shown in FIG. 27A, by the same method as that shown in the first embodiment, the vertical coil spring 69 is connected to the chip electrodes 2 formed on the undersurface of the function element chip 1 through the metal layer 3. Besides, in the same way, the vertical coil spring 4 is connected to the topside substrate electrode 5 formed on the top surface of the substrate 6 through the metal layer 3. [0199] Secondly, load is applied to the function element chip 1 and the substrate 6 in the vertical direction so that the vertical coil spring 4 and the vertical coil spring 69 are pressed mutually. Further, scrub or vibration is given in the horizontal direction. Thereby, the vertical coil spring 4 and the vertical coil spring 69 get intertwined mutually. [0200] Consequentially, as shown in FIG. 27B, even if the load added in the vertical direction is removed, the vertical coil spring 4 and the vertical coil spring 69 are electrically connected mutually by the elastic force to restitute. [0201] In this state, an electrical inspection is executed for checking the inside of the function element chip 1 and the connection between the function element chip 1 and the substrate 6. By this inspection, if it is observed that the connection areas are not connected electrically, upward and downward forces are applied thereto so as to detach the function element chip 1 from the substrate 6. Then, the intertwined vertical coil spring 4 and vertical coil spring 69 are separated. [0202] On the contrary, if it is confirmed that the connection areas are connected electrically as a result of the inspection, the function element chip 1 and the substrate 6 are heated up. Then, the vertical coil spring 4 is joined to the vertical coil spring 69. Thereby, there is obtained the semiconductor device in the eleventh embodiment. [0203] According to the production method of this embodiment, when it is observed that the connection areas are not connected electrically as a result of the inspection, it is possible to separate the function element chip 1 from the substrate 6 easily without applying heat to the function element chip 1 and the substrate 6. Thereby, it is possible to prevent damages to the function element chip 1 and the substrate 6. Further, the separated function element chip 1 and the substrate 6 can be reconnected to be used for a semiconductor device again. [0204] Incidentally, in this embodiment, there is shown an example of using the vertical coil spring 4 and the vertical coil spring 69 in order to connect the function element chip 1 and the substrate 6. However, the vertical coil springs used in this embodiment are not limited to these coils. For example, it is possible to arbitrarily select two kinds from the narrow-pitched coil spring 71, wide-pitched coil spring 72, intermittent coil springs 73 to 76 etc. shown in FIGS. 20A and 20B, FIGS. 22A to 22C and FIGS. 23A to 23C. [0205] In addition to the present invention, the sectional shape of the wire forming the coil spring is not limited particularly. For example, the shape may be circular form, elliptical form, square, rectangular, triangle or trapezoid. [0206] As set forth hereinabove, according to this invention, in the semiconductor device having the flip chip bonding structure, the coil springs serve as a means of connecting the function element device to the substrate electrically and mechanically. Thereby, the coil springs can absorb stress concentration caused by the thermal expansion difference between the function element device and the substrate, which was a major problem in the bumps in the conventional semiconductor device. Consequentially, there is no need to consider the configuration, process and materials taking account of the stress concentration to the bumps. Therefore, there is provided a semiconductor device having the flip chip bonding structure wherein the configuration and process are simple, packaging cost is low, and reliability is high. Besides, even if a high-power-consumption-type function element device is applied, the function element device can be connected to the heatsink directly. Thereby, there is obtained a semiconductor device wherein it is possible to realize low thermal resistibility at record level. Further, in the case where a faulty point is found in a connection formation that has a function element device and a substrate as a result of an electrical inspection, the function element device can be mechanically peeled from the substrate or the mother board etc. without heating. Thereby, it is possible to prevent damages to the function element device and the substrate in peeling them. Further, it is possible to connect the once-peeled function element device and the substrate again. Consequentially, it is possible to enhance the reliability of connection of the reconnected function element device and the substrate. [0207] While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by those embodiments but only by the appended claims. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the present invention. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7253514 *Jan 21, 2005Aug 7, 2007Infineon Technologies, AgSelf-supporting connecting element for a semiconductor chipUS7447041 *Mar 1, 2007Nov 4, 2008Delphi Technologies, Inc.Compression connection for vertical IC packagesUS7692280 *Mar 21, 2006Apr 6, 2010St-Ericsson SaPortable object connectable packageUS7810701 *Mar 25, 2009Oct 12, 2010Alps Electric Co., Ltd.Method for bonding metallic terminals by using elastic contactUS8084348 *Jun 4, 2008Dec 27, 2011Oracle America, Inc.Contact pads for silicon chip packagesUS8407888May 7, 2010Apr 2, 2013Oracle International CorporationMethod of assembling a circuit board assemblyUS8440506 *Jul 11, 2012May 14, 2013Intel CorporationMicroelectronic package and method for a compression-based mid-level interconnectUS20120279059 *Jul 11, 2012Nov 8, 2012Roberts Brent MMicroelectronic package and method for a compression-based mid-level interconnectUS20130062749 *Jul 20, 2012Mar 14, 2013Toyota Jidosha Kabushiki KaihsaSemiconductor module* Cited by examinerClassifications U.S. Classification257/778, 257/E23.078, 257/E23.021, 257/E21.508, 438/117, 257/688, 257/E23.068, 257/E21.511International ClassificationH01L23/498, H01L23/485, H01L23/48, H01L23/12, H05K1/14, H01L21/60Cooperative ClassificationH01L2224/13099, H01L2924/30107, H01L2924/01033, H01L2924/01039, H01L2924/01005, H01L2924/01075, H01L24/16, H01L2224/81205, H01L2224/73253, H01L2924/01079, H01L2924/01022, H01L2924/01082, H01L24/12, H01L2924/12044, H01L2924/01047, H01L24/81, H01L24/72, H01L2224/81801, H01L2924/15165, H01L2924/15312, H01L2924/01024, H01L2924/01013, H01L2924/01029, H01L2924/01004, H01L2224/81203, H01L24/11, H01L2924/01019, H01L23/49811, H01L2224/16, H01L2924/01006, H01L2924/0105, H01L2924/01078, H01L2924/01023, H01L2924/014, H01L2924/10329, H01L2924/16152, H01L24/17, H01L2924/09701, H01L2924/01046, H01L2924/3025, H01L2924/16195, H01L2924/15153European ClassificationH01L24/72, H01L24/16, H01L24/17, H01L24/12, H01L24/11, H01L24/81, H01L23/498CLegal EventsDateCodeEventDescriptionNov 13, 2001ASAssignmentOwner name: NEC CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUNAYA, TAKUO;SENBA, NAOJI;TAKAHASHI, NOBUAKI;AND OTHERS;REEL/FRAME:012401/0771Effective date: 20011102RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google