Source: http://www.google.com/patents/US20020043692?dq=2040248
Timestamp: 2016-02-12 14:51:50
Document Index: 149669653

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Patent US20020043692 - Semiconductor storage device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA memory cell which is capable of reducing the memory cell size in SRAM using a field-shield isolation on an SOI substrate. An isolation oxide film is provided between a field-shield isolation plate for n-type transistors and a field-shield isolation plate for p-type transistors....http://www.google.com/patents/US20020043692?utm_source=gb-gplus-sharePatent US20020043692 - Semiconductor storage deviceAdvanced Patent SearchPublication numberUS20020043692 A1Publication typeApplicationApplication numberUS 09/289,719Publication dateApr 18, 2002Filing dateApr 12, 1999Priority dateOct 26, 1998Also published asUS6441448Publication number09289719, 289719, US 2002/0043692 A1, US 2002/043692 A1, US 20020043692 A1, US 20020043692A1, US 2002043692 A1, US 2002043692A1, US-A1-20020043692, US-A1-2002043692, US2002/0043692A1, US2002/043692A1, US20020043692 A1, US20020043692A1, US2002043692 A1, US2002043692A1InventorsShigenobu Maeda, Yasuo Yamaguchi, Hirotada KuriyamaOriginal AssigneeShigenobu Maeda, Yasuo Yamaguchi, Hirotada KuriyamaExport CitationBiBTeX, EndNote, RefManReferenced by (15), Classifications (14), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor storage device
US 20020043692 A1Abstract
A memory cell which is capable of reducing the memory cell size in SRAM using a field-shield isolation on an SOI substrate. An isolation oxide film is provided between a field-shield isolation plate for n-type transistors and a field-shield isolation plate for p-type transistors. Images(15) Claims(4)
What is claimed is: 1. A semiconductor storage device having a memory cell comprising: a first driver transistor; a second driver transistor; a first load transistor that forms a flip-flop circuit together with said first and said second driver transistors; a second load transistor that forms a flip-flop circuit together with said first and said second driver transistors; a first access transistor connected to a drain active region of said first driver transistor and a drain active region of said first load transistor; and a second access transistor connected to a drain active region of said second driver transistor and a drain active region of said second load transistor, wherein device isolation in said memory cell includes field-shield isolation, and isolation between active regions of said first driver transistor and active regions of said first load transistor and isolation between active regions of said second driver transistor and active regions of said second load transistor are effected by oxide film isolation. 2. A semiconductor storage device having a memory cell comprising: a first driver transistor; a second driver transistor; a first load transistor that forms a flip-flop circuit together with said first and said second driver transistors; a second load transistor that forms a flip-flop circuit together with said first and said second driver transistors; a first access transistor connected to a drain active region of said first driver transistor and a drain active region of said first load transistor; and a second access transistor connected to a drain active region of said second driver transistor and a drain active region of said second load transistor, wherein device isolation in said memory cell includes field-shield isolation, and at least part of isolation regions that are in contact with the drain active regions of said first and said second driver transistors and the drain active regions of said first and said second load transistors are isolated by oxide film isolation. 3. The semiconductor storage device according to claim 2, wherein the drain active region of said first driver transistor and the drain active region of said first load transistor are in contact with each other, and wherein the drain active region of said second driver transistor and the drain active region of said second load transistor are in contact with each other. 4. A semiconductor storage device having a memory cell comprising: a first driver transistor; a second driver transistor; a first load transistor that forms a flip-flop circuit together with said first and said second driver transistors; a second load transistor that forms a flip-flop circuit together with said first and said second driver transistors; a first access transistor connected to a drain active region of said first driver transistor and a drain active region of said first load transistor; and a second access transistor connected to a drain active region of said second driver transistor and a drain active region of said second load transistor, wherein device isolation in said memory cell includes field-shield isolation, active regions of said first access transistor and the drain active region of said first driver transistor are isolated from each other by field-shield isolation and connected to each other via a metal interconnection, and active regions of said second access transistor and the drain active region of said second driver transistor are isolated from each other by field-shield isolation and connected to each other via a metal interconnection. Description
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a static semiconductor storage device (hereinafter referred to as SRAM) using field-shield isolation. [0003] 2. Description of Related Art [0004] In general, an SRAM memory cell is constituted of six transistors. FIG. 13 is an equivalent circuit diagram of an SRAM memory cell. In FIG. 13, reference symbols 1 a and 1 b denote access transistors each being an n-type transistor; 2 a and 2 b, driver transistors each being an n-type transistor; 3 a and 3 b, load transistors each being a p-type transistor; 4 a and 4 b, bit lines; and 5, a word line. In the memory cell, the driver transistors 2 a and 2 b and the load transistors 3 a and 3 b form a flip-flop circuit. [0005] [0005]FIGS. 14 and 15 show patterns of a related SRAM memory cell in which polysilicon interconnections in one level and metal interconnections in two levels and field-shield isolation plates are used on an SOI (silicon on insulator) substrate. Specifically, FIG. 14 shows a pattern of field-shield isolation plates, active regions, polysilicon interconnections, first-level metal interconnections, and first contact portions that connect the first-level metal interconnections to the polysilicon interconnections or the active regions. FIG. 15 shows a pattern of the field-shield isolation plates, the active regions, the polysilicon interconnections, second-level metal interconnections, and second contact portions that connect the second-level metal interconnections to the active regions or the field-shield isolation plates. [0006] The term “field-shield isolation” as used in this specification means, in simple terms, device isolation that utilizes off-states of MOS transistors having a high threshold voltage. The term “field-shield isolation plate” corresponds to the gate of an ordinary transistor. In the following description, the field-shield isolation will be explained in a case where it is effected by field-shield isolation plates. [0007] To reduce the resistivity of active regions on an SOI substrate, usually the surface portions of the active regions are converted to a refractory metal silicide. [0008] In the related SRAM memory cell pattern of FIG. 14, 11a-11 c denote field-shield isolation plates for n-type transistors; 11 d, a field-shield isolation plate for p-type transistors; 12 a-12 f, n-type active regions; 12 g-12 j, p-type active regions; 12 x-12 z, active regions that are not clearly judged to be of an n-type or of a p-type; and 13 a-13 c, polysilicon interconnections or interconnections having a laminated structure of polysilicon and a silicide (hereinafter represented by polysilicon interconnections). Reference symbols 14 a-14 c denote first-level metal interconnections, and 15 a-15 h denote first contact portions that connect the first-level metal interconnections to the active regions or the polysilicon interconnections. [0009] In FIG. 15, reference symbols 16 a-16 d denote second-level metal interconnections, and 17 a-17 f denote second contact portions that connect the second-level metal interconnections to the active regions or the field-shield isolation plates. [0010] Next, the components shown in the equivalent circuit diagram of FIG. 13 will be correlated with the parts shown in FIGS. 14 and 15. As for the access transistors, for the sake of convenience, the active regions connected to the bit lines will be called drain active regions and the active regions connected to the driver transistors will be called source active regions. First, as for the transistors, the drain active region, the gate, and the source active region of the access transistor 1 a are the parts 12 a, 13 a, and 12 b, respectively; those of the access transistor 1 b are the parts 12 d, 13 a, and 12 e, respectively; those of the driver transistor 2 a are the parts 12 b, 13 b, and 12 c, respectively; those of the driver transistor 2 b are the parts 12 e, 13 c, and 12 f; those of the load transistor 3 a are the parts 12 g, 13 b, and 12 h; and those of the load transistor 3 b are the parts 12 i, 13 c, and 12 j. The bit line 4 a corresponds to the part 16 a, the bit line 4 b corresponds to the part 16 b, and the word line 5 corresponds to the part 13 a. The part 14 c in FIG. 14 corresponds to the Vcc interconnection and the parts 16 c and 16 d in FIG. 15 correspond to the GND interconnection. [0011] [0011]FIG. 16 is a sectional view taken along line I-I in FIGS. 14 and 15. In FIG. 16, reference symbols 21-23 denote a silicon portion, an insulating layer, and an interlayer insulating film, respectively. [0012] The above-described SRAM formed on the SOI substrate by using the field-shield isolation have the following three problems. [0013] The first problem is data destruction at storage nodes that occurs being influenced by floating potential regions. In FIG. 14, although the active regions 12 x-12 z are divided from each other by the field-shield isolation plates 11 b and 11 d and the polysilicon interconnections 13 b and 13 c, their potentials are not fixed. Therefore, the active regions 12 x-12 z are rendered in a floating potential state and influence the active regions 12 b, 12 e, 12 g, and 12 i as storage node portions in memory cell operation, and possibly cause data destruction through noise, latch-up, or the like. [0014] The second problem is a large memory cell size. As shown in FIG. 14, the potentials of the field-shield isolation plate 11 b for n-type transistors and the field-shield isolation plate 11 d for p-type transistors are fixed at the GND potential and the Vcc potential, respectively. Therefore, intervals are needed between the n-type transistors and the p-type transistors. Specifically, if each of a minimum field-shield isolation width (or a minimum polysilicon interconnection width) and a minimum isolation interval (or a minimum polysilicon interval) is W, it is desirable that an interval X between the same storage nodes (see FIG. 14) be equal to 3W. However, actually, since the active regions 12 x-12 z between the n-type transistors and the p-type transistors are electrically unstable (the first problem mentioned above), there may occur latch-up or the like. For this reason, to make the memory cell less prone to data destruction, the interval X between the same storage nodes is set at a large value 3W+α. This necessarily increases the memory cell size. [0015] The third problem is severe hole forming conditions of the second contact portions. FIG. 17 shows a pattern of field-shield isolation plates in a case where related memory cells 40 as shown in FIGS. 14 and 15 are arranged in a 4�4 (vertical/horizontal) array. Where the field-shield isolation plates 11 b and 11 d are arranged in array form, they assume a continuous pattern and hence the plate potentials can be fixed at ends of the array. [0016] On the other hand, where the field-shield isolation plates 11 a and 11 c are solitary patterns, the plate potentials need to be fixed at the respective positions. As shown in FIG. 15, it is necessary to fix the potentials by connecting the field-shield isolation plates 11 a and 11 c to the second-level metal interconnections 16 d and 16 c via the second contact portions 17 d and 17 c, respectively. [0017] Therefore, as shown in FIG. 15, it is necessary to form, in the memory cell, two kinds of second contact portions having different depths, that is, the contact portions 17 a, 17 b, 17 e, and 17 f for the active regions and the contact portions 17 c and 17 d for field-shield isolation plates, which leads to severe contact hole opening conditions. SUMMARY OF THE INVENTION [0018] The present invention has been made to solve the above problems in the art, and a first object of the invention is therefore to eliminate floating potential active regions. [0019] A second object of the invention is to reduce the memory cell size. [0020] A third object of the invention is to realize a memory cell configuration in which second contact portions have only one kind of depth. [0021] According to a first aspect of the present invention, there is provided a semiconductor storage device having a memory cell comprising: a first driver transistor; a second driver transistor; a first load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a second load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a first access transistor connected to a drain active region of the first driver transistor and a drain active region of the first load transistor; and a second access transistor connected to a drain active region of the second driver transistor and a drain active region of the second load transistor, wherein device isolation in the memory cell includes field-shield isolation, and isolation between active regions of the first driver transistor and active regions of the first load transistor and isolation between active regions of the second driver transistor and active regions of the second load transistor are effected by oxide film isolation. [0022] According to a second aspect of the present invention, there is provided a semiconductor storage device having a memory cell comprising: a first driver transistor; a second driver transistor; a first load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a second load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a first access transistor connected to a drain active region of the first driver transistor and a drain active region of the first load transistor; and a second access transistor connected to a drain active region of the second driver transistor and a drain active region of the second load transistor, wherein device isolation in the memory cell includes field-shield isolation, and at least part of isolation regions that are in contact with the drain active regions of the first and the second driver transistors and the drain active regions of the first and the second load transistors are isolated by oxide film isolation. [0023] According to a third aspect of the present invention, there is provided a semiconductor storage device having a memory cell comprising: a first driver transistor; a second driver transistor; a first load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a second load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a first access transistor connected to a drain active region of the first driver transistor and a drain active region of the first load transistor; and a second access transistor connected to a drain active region of the second driver transistor and a drain active region of the second load transistor, wherein device isolation in the memory cell includes field-shield isolation, active regions of the first access transistor and the drain active region of the first driver transistor are isolated from each other by field-shield isolation and connected to each other via a metal interconnection, and active regions of the second access transistor and the drain active region of the second driver transistor are isolated from each other by field-shield isolation and connected to each other via a metal interconnection. [0024] According to a fourth aspect of the present invention, there is provided a semiconductor storage device having a memory cell comprising: a first driver transistor; a second driver transistor; a first load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a second load transistor that forms a flip-flop circuit together with the first and the second driver transistors; a first access transistor connected to a drain active region of the first driver transistor and a drain active region of the first load transistor; and a second access transistor connected to a drain active region of the second driver transistor and a drain active region of the second load transistor, wherein device isolation in the memory cell includes field-shield isolation, first and second active regions of the first access transistor and active regions of the second access transistor are arranged substantially on a straight line, and a word line that is connected to the first and the second access transistors is formed on a portion of a field-shield isolation plate that is located between the first active region of the first access transistor and a source active region of the first driver transistor. [0025] The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS [0026] [0026]FIGS. 1 and 2 show patterns of an SRAM memory cell according to a embodiment 1 of the present invention. [0027] [0027]FIG. 3 is a sectional view taken along line I-I in FIGS. 1 and 2. [0028] [0028]FIG. 4 shows a pattern of an SRAM memory cell according to a embodiment 2 of the invention. [0029] [0029]FIG. 5 shows a pattern of field-shield isolation plates in a case where memory cells 40 of this embodiment are arranged in a 4�4 (vertical/horizontal) array. [0030] [0030]FIGS. 6 and 7 show patterns of an SRAM memory cell according to a embodiment 3 of the present invention. [0031] [0031]FIG. 8 is a sectional view taken along line I-I in FIGS. 6 and 7. [0032] [0032]FIG. 9 shows a pattern of an SRAM memory cell according to a embodiment 4 of the invention. [0033] [0033]FIGS. 10 and 11 show patterns of an SRAM memory cell according to a embodiment 5 of the invention. [0034] [0034]FIG. 12 is a sectional view taken along line I-I in FIGS. 9 and 10. [0035] [0035]FIG. 13 is an equivalent circuit diagram of a related SRAM memory cell. [0036] [0036]FIGS. 14 and 15 show patterns of a related SRAM memory cell in which polysilicon interconnections in one level and metal interconnections and field-shield isolation plates in two levels are used on an SOI (silicon on insulator) substrate. [0037] [0037]FIG. 16 is a sectional view taken along line I-I in FIGS. 14 and 15. [0038] [0038]FIG. 17 shows a pattern of field-shield isolation plates in a case where related memory cells 40 as shown in FIGS. 14 and 15 are arranged in a 4�4 (vertical/horizontal) array.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0039] Embodiments of the present invention will be described below with reference to the accompanying drawings. It is noted that the same reference symbols in the drawings denote the same or corresponding components. [0040] Embodiment 1 [0041] [0041]FIGS. 1 and 2 show patterns of an SRAM memory cell according to a embodiment 1 of the present invention. The memory cell is configured by polysilicon interconnections in one level and metal interconnections and field-shield isolation plates in two levels. Specifically, FIG. 1 shows a pattern of field-shield isolation plates, active regions, polysilicon interconnections, first-level metal interconnections, and first contact portions that connect the first-level metal interconnections to the polysilicon interconnections or the active regions. FIG. 2 shows a pattern of the field-shield isolation plates, the active regions, the polysilicon interconnections, second-level metal interconnections, and second contact portions that connect the second-level metal interconnections to the active regions or the field-shield isolation plates. [0042] In FIG. 1, 11a-11 c denote field-shield isolation plates for n-type transistors; 11 d, a field-shield isolation plate for p-type transistors; 12 a-12 f, n-type active regions; 12 g-12 j, p-type active regions; and 13 a-13 c, polysilicon layers. Reference symbols 14 a-14 c denote first-level metal interconnections, and 15 a-15 g denote first contact portions that connect the first-level metal interconnections to the active regions or the polysilicon layers. Reference symbol 31 a denotes an isolation oxide film. [0043] In FIG. 2, reference symbols 16 a-16 d denote second-level metal interconnections, and 17 a-17 f denote second contact portions that connect the second-level metal interconnections to the active regions or the field-shield isolation plates. [0044] Next, the components shown in the equivalent circuit diagram of FIG. 13 will be correlated with the parts shown in FIGS. 1 and 2. First, as for the transistors, the drain active region, the gate, and the source active region of the access transistor 1 a are the parts 12 a, 13 a, and 12 b, respectively; those of the access transistor 1 b are the parts 12 d, 13 a, and 12 e, respectively; those of the driver transistor 2 a are the parts 12 b, 13 b, and 12 c, respectively; those of the driver transistor 2 b are the parts 12 e, 13 c, and 12 f; those of the load transistor 3 a are the parts 12 g, 13 b, and 12 h; and those of the load transistor 3 b are the parts 12 i, 13 c, and 12 j. The bit line 4 a corresponds to the part 16 a, the bit line 4 b corresponds to the part 16 b, and the word line 5 corresponds to the part 13 a. The part 14 c in FIG. 1 corresponds to the Vcc interconnection and the parts 16 c and 16 d in FIG. 2 correspond to the GND interconnection. [0045] [0045]FIG. 3 is a sectional view taken along line I-I in FIGS. 1 and 2. In FIG. 3, reference symbols 21-23 denote a silicon portion, an insulating layer, and an interlayer insulating film, respectively. [0046] The embodiment 1 is different from the conventional example in that the isolation oxide film 31 a (enclosed by a thick-line frame in FIG. 1) provided between the field-shield isolation plate 11 b for n-type transistors and the field-shield plate 11 d for p-type transistors. This makes it possible to eliminate the floating potential regions in the conventional example. [0047] Further, the embodiment 1 makes it possible to reduce the memory size. Specifically, if each of a minimum polysilicon layer width and a minimum polysilicon interval is W, an interval X between the same storage nodes (see FIG. 1) becomes 3W, which is shorter than the interval X=3W+α in the conventional memory cell by a. The memory cell size can thus be reduced. [0048] Embodiment 2 [0049] [0049]FIG. 4 shows a pattern of an SRAM memory cell according to a embodiment 2 of the invention. Specifically, FIG. 4 shows a pattern of field-shield isolation plates, active regions, polysilicon interconnections, first-level metal interconnections, and first contact portions that connect the first-level metal interconnections to the polysilicon interconnections or the active regions. [0050] The pattern of FIG. 4 is different from the pattern of FIG. 1 (embodiment 1) in the arrangement of the field-shield isolation plates for n-type transistors, the n-type active regions, the first-level metal interconnections, and the first contact portions. [0051] First, the field-shield isolation plates 11 a-11 c for n-type transistors in FIG. 1 are integrated into a field-shield isolation plate 11 e in FIG. 4. [0052] Second, as for the n-type active regions, while in FIG. 1 the source active regions of the access transistors 1 a and 1 b are integrated with the drain active regions of the driver transistors 2 a and 2 b to form the n-type active regions 12 b and 12 e, respectively, in FIG. 4 they are divided to form separate active regions for the respective transistors, that is, a source active region 12 k of the access transistor 1 a, a source active region 12 m of the access transistor 1 b, a drain active region 12 p of the driver transistor 2 a, and a drain active region 12 n of the driver transistor 2 b. [0053] Since the n-type active regions are divided, the patterns of the first-level metal interconnections 14 a and 14 b are changed, the first contact portion 15 a is changed to first contact portions 15 i and 15 j and the first contact portion 15 b is changed to first contact portions 15 k and 15 p, whereby the access transistors and the driver transistors are connected to each other. [0054] [0054]FIG. 5 shows a pattern of field-shield isolation plates in a case where memory cells 40 of this embodiment are arranged in a 4�4 (vertical/horizontal) array. Where the field-shield isolation plates 11 e and 11 d are arranged in array form, they assume a continuous pattern and hence the plate potentials can be fixed at ends of the array. [0055] Therefore, unlike the case of the conventional memory cell, it is no longer necessary to fix the plate potentials by means of the second contact portions 17 c and 17 d that are connected to the field-shield plates (see FIG. 15). As a result, the second contact portions only connect the second-level metal interconnections to the active regions in the memory cell. [0056] Embodiment 3 [0057] [0057]FIGS. 6 and 7 show patterns of an SRAM memory cell according to a embodiment 3 of the present invention. Specifically, FIG. 6 shows a pattern of field-shield isolation plates, active regions, polysilicon interconnections, first-level metal interconnections, and first contact portions that connect the first-level metal interconnections to the polysilicon interconnections or the active regions. FIG. 7 shows a pattern of the field-shield isolation plates, the active regions, the polysilicon interconnections, second-level metal interconnections, and second contact portions that connect the second-level metal interconnections to the active regions. [0058] [0058]FIG. 8 is a sectional view taken along line I-I in FIGS. 6 and 7. [0059] The same reference symbols in FIGS. 6-8 (this embodiment) and FIGS. 1-4 (first and embodiment 2 s) denote the same or corresponding parts. [0060] A large difference between this embodiment and the first and embodiment 2 s is the direction of part of the polysilicon interconnections that serve as the gates of the driver and load transistors. That is, while in the first and embodiment 2 s those polysilicon interconnections are substantially perpendicular to the polysilicon interconnection 13 a that serves as the gates of the access transistors, in this embodiment the former are substantially parallel with the latter. This greatly changes the pattern of the isolation oxide film 31 a. Further, the source active regions 12 c and 12 f of the driver transistor in the embodiments 1 and 2 are combined into a source active region 12 q. Still further, while in the first and embodiment 2 s the GND lines 16 c and 16 d are located at the two side positions of the memory cell (see FIG. 2), in this embodiment a GND line 16 e is located at a central position of the memory cell (see FIG. 7). [0061] This embodiment provides the same effects as the first and embodiment 2; that is, the floating potential active regions can be eliminated, the memory cell size can be reduced, and the number of kinds of second contact portions can be reduced to one. [0062] Further, since the GND interconnection 16 e is located between the bit lines 16 a and 16 b in the memory cell, inter-bit-line noise in the memory cell can be reduced. [0063] Embodiment 4 [0064] [0064]FIG. 9 shows a pattern of an SRAM memory cell according to a embodiment 4 of the invention. Specifically, FIG. 9 shows a pattern of field-shield isolation plates, active regions, polysilicon interconnections, first-level metal interconnections, and first contact portions that connect the first-level metal interconnections to the polysilicon interconnections or the active regions. [0065] This embodiment is different from the embodiment 3 in the pattern of isolation oxide films. In the embodiment 3, the isolation oxide film 31 a is continuous and have protrusions and recesses in a plane as shown in FIG. 6. In contrast, in this embodiment, three separate isolation oxide films 31 b-31 d are provided as shown in FIG. 9. In this connection, the n-type active regions 12 p and 12 n are in contact with the p-type active regions 12 g and 12 i, respectively. [0066] As described in the conventional example, in SOI devices surface portions of active regions are usually converted to a refractory metal silicide. Therefore, even if an n-type active region and a p-type active region are in contact with each other, no PN junction is formed on the surface and no problems occur. [0067] In this embodiment, there is no isolation oxide film that is interposed between an n-type active region and a p-type active region and hence the memory cell size can further be reduced. [0068] Embodiment 5 [0069] [0069]FIGS. 10 and 11 show patterns of an SRAM memory cell according to a embodiment 5 of the invention. This embodiment is different from the embodiment 4 in that the arrangement of the active regions of the access transistor 1 b is changed and the word line is of a bent shape rather than a straight shape. [0070] In the embodiment 4, the field-shield isolation width between the n-type active regions 12 k and 12 m is wide as shown in FIG. 9. In this embodiment, this portion is used as an n-type active region, whereby the memory cell area is effectively utilized and the memory cell size is reduced. With this measure, as shown in FIG. 10, the drain active region 12 d and the source active region 12 m of the access transistor 1 b and the source active region 12 k of the access transistor 1 a are arranged approximately on a straight line. Since the word line 13 a runs on the portion of the field-shield isolation plate that is located between the drain active region 12 d of the access transistor 1 b and the source active region 12 q of the driver transistors, it assumes a bent shape (see FIG. 10) rather than a straight shape (see FIG. 9). [0071] Next, a description will be made of a specific memory cell size reduction effect. Here, a length A between a memory cell boundary and an end of the source active regions of the driver transistors in the memory cell of FIG. 9 is compared with that in the memory cell of FIG. 10. The other portions have the same length in the two embodiments. With an assumption that the access transistors have a gate length W, a gate width 1.5W, and a minimum isolation width W, the length A is equal to 5W in the embodiment 4 as shown in FIG. 9. In contrast, in this embodiment, the length A is equal to 4W as shown in FIG. 10. The shortening of the length A leads to memory size reduction. [0072] Broken line patterns in the top portion of FIG. 10 are active regions of access transistors and a word line in an adjacent memory cell that are point-symmetrical with the active regions the access transistors and the word line in the memory cell concerned. [0073] [0073]FIG. 12 is a sectional view taken along line I-I in FIGS. 9 and 10. [0074] In the first to third and embodiment 5 s, the SOI substrate can be replaced by an ordinary silicon substrate. [0075] Although the oxide film isolation in the first to embodiment 5 s generally means isolation using a silicon oxide film such as LOCOS isolation and trench isolation, it may be in any form as long as active regions can be isolated from each other by using an insulating film. [0076] Having the above constitution, the invention provides the following advantages. [0077] According to the first and second aspects of the invention, the memory cell size can be reduced by combining field-shield isolation and oxide film isolation to effect isolation through enclosure of the active regions of the driver transistors and the active regions of the load transistors. [0078] In the semiconductor storage device, the drain active region of the first driver transistor and the drain active region of the first load transistor may be in contact with each other, and the drain active region of the second driver transistor and the drain active region of the second load transistor may be in contact with each other. In the semiconductor storage device, the memory cell size can further be reduced by bringing the drain active regions of the driver transistors in contact with the drain active regions of the load transistors, respectively. [0079] According to the third aspect of the invention, since the source active regions of the access transistors are isolated from the drain active regions of the driver transistors, respectively, by field-shield isolation, solitary isolation regions are eliminated. Therefore, the fourth aspect of the invention dispenses with second contact portions to be connected to the field-shield isolation plates in the memory cell and facilitates hole formation of the second contact portions. [0080] According to the fourth aspect of the invention, the memory cell size can further be reduced by arranging the drain active region and the source active region of the first access transistor and the source active region of the second access transistor substantially on a straight line. [0081] The present invention has been described in detail with respect to various embodiments, and it will now be apparent from the foregoing to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects, and it is the invention, therefore, in the appended claims to cover all such changes and modifications as fall within the true spirit of the invention. [0082] The entire disclosure of Japanese Patent Application No. 10-304027 filed on Oct. 26, 1998 including specification, claims, drawings and summary are incorporated herein by reference in its entirety. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7045449Feb 10, 2003May 16, 2006Micron Technology, Inc.Methods of forming semiconductor constructionsUS7087478Jul 21, 2003Aug 8, 2006Micron Technology, Inc.Methods of forming semiconductor constructionsUS7157775 *Feb 13, 2003Jan 2, 2007Micron Technology, Inc.Semiconductor constructionsUS7227227Aug 24, 2005Jun 5, 2007Micron Technology, Inc.Reduced leakage semiconductor deviceUS7274056Aug 24, 2005Sep 25, 2007Micron Technology, Inc.Semiconductor constructionsUS7285468Jul 21, 2003Oct 23, 2007Micron Technology, Inc.Methods of forming semiconductor constructionsUS7719056 *Mar 16, 2007May 18, 2010Kabushiki Kaisha ToshibaSemiconductor memory device having a floating body and a plate electrodeUS20040036117 *Feb 13, 2003Feb 26, 2004Tran Luan C.Semiconductor constructionsUS20040038483 *Feb 10, 2003Feb 26, 2004Tran Luan C.Methods of forming semiconductor constructionsUS20040070016 *Jul 21, 2003Apr 15, 2004Tran Luan C.Methods of forming semiconductor constructionsUS20050280033 *Aug 24, 2005Dec 22, 2005Tran Luan CSemiconductor constructionsUS20050280057 *Aug 24, 2005Dec 22, 2005Tran Luan CSemiconductor constructionsUS20060019440 *Aug 24, 2005Jan 26, 2006Tran Luan CSemiconductor constructionsUS20060121712 *Jan 23, 2006Jun 8, 2006Micron Technology, Inc.Semiconductor constructions and methods of forming semiconductor constructionsUS20080032474 *Mar 16, 2007Feb 7, 2008Kabushiki Kaisha ToshibaSemiconductor memory device and semiconductor memory device manufacturing method* Cited by examinerClassifications U.S. Classification257/392, 257/E27.112, 257/E27.099International ClassificationG11C11/412, H01L21/8244, H01L27/11, H01L27/12, H01L29/786Cooperative ClassificationH01L27/1104, H01L27/1203, G11C11/412European ClassificationH01L27/12B, H01L27/11F, G11C11/412Legal EventsDateCodeEventDescriptionApr 12, 1999ASAssignmentOwner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MAEDA, SHIGENOBU;YAMAGUCHI, YASUO;KURIYAMA, HIROTADA;REEL/FRAME:009895/0522;SIGNING DATES FROM 19990315 TO 19990317Feb 3, 2006FPAYFee paymentYear of fee payment: 4Apr 5, 2010REMIMaintenance fee reminder mailedAug 27, 2010LAPSLapse for failure to pay maintenance feesOct 19, 2010FPExpired due to failure to pay maintenance feeEffective date: 20100827RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services