Source: http://www.google.com/patents/US7333372?ie=ISO-8859-1
Timestamp: 2014-03-08 16:17:56
Document Index: 121535001

Matched Legal Cases: ['art) 132', 'art 132', 'art 132', 'art 132', 'art 132', 'art 132', 'art 132', 'art 132', 'art 132', 'art 132', 'art) 432', 'art 132', 'art 432', 'art 432', 'art 432', 'art 432', 'art 432', 'art 432', 'art 432', 'art 432', 'art 432', 'art 432', 'arts 132']

Patent US7333372 - Reset circuit and integrated circuit device with reset function - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a predetermined expected value data; a second register holding data which was auto-loaded; and a data comparison...http://www.google.com/patents/US7333372?utm_source=gb-gplus-sharePatent US7333372 - Reset circuit and integrated circuit device with reset functionAdvanced Patent SearchPublication numberUS7333372 B2Publication typeGrantApplication numberUS 10/958,658Publication dateFeb 19, 2008Filing dateOct 6, 2004Priority dateOct 10, 2003Fee statusPaidAlso published asUS20050105348Publication number10958658, 958658, US 7333372 B2, US 7333372B2, US-B2-7333372, US7333372 B2, US7333372B2InventorsHitoshi Tanaka, Hiroyuki Fukuyama, Takeru YonagaOriginal AssigneeOki Electric Industry Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (5), Classifications (7), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetReset circuit and integrated circuit device with reset functionUS 7333372 B2Abstract A reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a predetermined expected value data; a second register holding data which was auto-loaded; and a data comparison circuit which performs a comparison between the data held in the second register and the expected value data stored in the first register, and generates the reset signal based on a result of the comparison.
1. A reset circuit which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, said reset circuit comprising:
a first memory which stores a predetermined expected value data;
a second memory holding data which was auto-loaded; and
a reset controller which performs a comparison between said data held in said second memory and said expected value data stored in said first memory, and generates said reset signal based on a result of said comparison,
wherein said auto-loaded data is data auto-loaded from a ROM.
2. The reset circuit according to claim 1, wherein said reset controller includes a measurement part which measures time;
when said measurement part has measured a predetermined time after power supply to said integrated circuit device is switched on, said reset controller performs said comparison between said data held in said second memory and said expected value data stored in said first memory, and generates said reset signal as a result of said comparison when said reset controller determines that said data held in said second memory coincides with said expected value data stored in said first memory.
3. The reset circuit according to claim 2, wherein said measurement part includes a counter which measures an internal clock of said integrated circuit device.
said reset controller includes a first measurement part which repeatedly measures a predetermined time, and a second measurement part which measures number of times said first measurement part has measured said predetermined time; and
when said second measurement part has measured said predetermined number of times, said reset controller performs said comparison between said data held in said second memory and said expected value data stored in said first memory, and generates said reset signal as a result of said comparison when said data held in said second memory coincides with said expected value data stored in said first memory.
said first measurement part includes a first counter which cyclically counts an internal clock of said integrated circuit device up to a fixed value; and
said second measurement part includes a second counter which measures number of times said first counter has cyclically counted up to said fixed value.
said reset controller includes a first measurement part which repeatedly measures a predetermined time, and a second measurement part which measures the number of times said first measurement part has measured said predetermined time; and
said reset controller performs said comparison between said data held in said second memory and said expected value data stored in said first memory each time said measurement part measures said predetermined time until said second memory has measured a predetermined number of times, and generates said reset signal based on a result of said plural comparisons.
7. The reset circuit according to claim 6, wherein:
8. The reset circuit according to claim 1, wherein said reset circuit is formed from an ASIC chip.
9. An integrated circuit device having an auto-loading function, comprising:
a reset circuit which generates a reset signal for initializing said internal circuit;
a first memory which stores predetermined expected value data;
a second memory which holds auto-loaded data; and
a reset controller which performs a comparison between said data held in said second memory and said expected value data stored in said first memory, and generates said reset signal based on a result of said comparison;
the integrated circuit device further comprising a ROM which holds said auto-loaded data, wherein the auto-loading by said reset circuit is an auto-loading from said ROM.
10. The integrated circuit device according to claim 9, wherein said reset circuit is connected to a ROM, and the auto-loading by said reset circuit is an auto-loading from said ROM.
an oscillator which generates an internal clock; and
a read command/address generating circuit which generates an address and a read command for data auto-loaded according to said internal clock.
12. The integrated circuit device according to claim 9, wherein
said reset controller includes a measurement part which measures time; and
13. The integrated circuit device according to claim 12, wherein said measurement part includes a counter which measures an internal clock of said integrated circuit device.
14. The integrated circuit device according to claim 9, wherein
15. The integrated circuit device according to claim 14, wherein
16. The integrated circuit device according to claim 9, wherein
17. The integrated circuit device according to claim 9, wherein:
18. The integrated circuit device according to claim 9, wherein said reset circuit is formed from an ASIC chip.
The present invention relates to a reset circuit which generates a reset signal for initializing a predetermined circuit in an LSI, and to an integrated circuit device having a reset function.
In general, an LSI which does not have an external reset terminal for inputting a reset signal from outside, has a power reset circuit which resets a predetermined circuit in the LSI when the power supply is switched on. For example, Japanese Patent Kokai (Laid-Open) Publication No. 5-299993 discloses an example of a power reset circuit including a resistance, a capacitance and a buffer gate circuit.
In this prior art power-on reset circuit, in order to generate a reset signal having a desired waveform (for example, a desired pulse width), it is necessary to adjust the composition and the size (dimension) of the transistors forming the resistance and capacitance. However, when disigning SOG (Sea of Gates) type ASIC (Application Specific Integrated Circuits), although it is possible to change the gate connection by adjusting a wiring layer, the composition and size (specifically, a gate length and a gate width) of the gate of a transistor cannot be adjusted. Therefore, it is difficult to form a power-on reset circuit having the desired resistance and capacitance in an SOG type ASIC. For this reason, an SOG type ASIC has to be provided with an external reset terminal, and the reset signal generated in the external circuit had to be inputted to the ASIC throught the external reset terminal.
SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a reset circuit and an integrated circuit device having a reset function which can provide a power-on reset function to an integrated circuit device without an external reset terminal.
According to one aspect of the present invention, a reset circuit which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, the reset circuit includes a first memory which stores a predetermined expected value data; a second memory holding data which was auto-loaded; and a reset controller which performs a comparison between the data held in the second memory and the expected value data stored in the first memory, and generates the reset signal based on a result of the comparison.
According to another aspect of the present invention, an integrated circuit device having an auto-loading function, includes an internal circuit; and a reset circuit which generated a reset signal for initializing the internal circuit. The reset circuit includes a first memory which stores predetermined expected value data; a second memory which holds auto-loaded data; and a reset controller which performs a comparison between the data held in the second memory and the expected value data stored in the first memory, and generated the reset signal based on a result of the comparison.
FIG. 1 is a diagram showing the construction and operation of an integrated circuit device according to a first embodiment of the present invention;
FIG. 2 is a block diagram showing the construction of the integrated circuit device according to the first embodiment;
FIG. 3 is a timing chart showing the operation of the integrated circuit device according the the first embodiment;
FIG. 4 is a block diagram showing a modification of the integrated circuit device according the the first embodiment;
FIG. 5 is a block diagram showing another modification of the integrated circuit device according to the first embodiment;
FIG. 6 is a diagram showing the construction and operation of an integrated circuit device according to a second embodiment of the present invention;
FIG. 7 is a block diagram showing the construction of the integrated circuit device according to the second embodiment;
FIG. 8 is a timing chart showing the operation of the integrated circuit device according the the second embodiment; and
FIG. 9 is a timing chart showing the operation of modification of the integrated circuit device according to the second embodiment.
First Embodiment FIG. 1 is a diagram showing the construction and operation of an integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the construction of the integrated circuit device according to the first embodiment. As shown in FIGS. 1 and 2, an integrated circuit device 100 includes an SOG type ASIC chip 110 and a ROM chip 120.
As shown in FIG. 2, the ASIC chip 110 has a reset circuit 130 which generates a reset signal RS, a logic circuit (internal circuit) 140, an oscillator 150 which generates an internal clock CLK, and an input/output port 160. The logic circuit 140 is either in a reset state (i.e., an initialized state before starting the normal operation of the logic circuit 130), or a reset release state (i.e., a state after starting the normal operation of the logic circuit 130), according to the reset signal RS generated by the reset circuit 130.
As shown in FIGS. 1 and 2, the reset circuit 130 includes a read command/address generating circuit 131 which generates an address ADR and a read command COM of data which is auto-loaded according to the internal clock CLK, a first register (expected value data storage part) 132 which stores predetermined expected value data, a second register (load data register) 133 holding the data which was auto-loaded, a data comparison circuit (reset controller) 134 which compares the data held in the second register 133 and the expected value data stored in the first register 132, and generates the reset signal RS based on the result of this comparison, and an internal counter 135. The integrated circuit device 100 may be, for example, a semiconductor memory device, but if the integrated circuit device 100 is a semiconductor device having the function of loading data, the present invention can be applied also to a device other than a semiconductor memory device.
FIG. 3 is a timing chart showing the operation of the integrated circuit device 100, mainly the operation of the reset circuit 130. As shown in FIG. 3, after power is supplied to the integrated circuit device 100 (after a time t10), a supply voltage Vd rises and is stabilized at a predetermined voltage. After power starts to be supplied, when the supply voltage Vd reaches a voltage at which oscillation of the oscillator 150 is possible (a time t11), an oscillator 11 oscillates and the internal clock CLK is outputted. A read command/address generating circuit 12 performs a cyclic count of the internal clock CLK by an internal counter 135 to a steady value (for example, in the case of a twenty-bit configuration, �FFFFF� (hexadecimal notation)), and sends the address ADR and read command COM to the ROM chip 120 according to this count. Due to this, preprogrammed data (16 bits�4 words) stored in a domain specified in the address ADR of the ROM chip 120 is read out. The data read by this auto-loading operation (from the time t11 to the time t12, i.e., the period AL in FIG. 3) is held in the load data register 133 (16 bits�4 words) of the ASIC chip 110.
Identical data to the data stored in the predetermined domain of the ROM chip 120 is hard set (0/1 fixation) beforehand in the expected value data storage part 132. When the internal counter 135 counts a steady value (for example, �FFFFF� (hexadecimal notation (a time t12)), the data comparison circuit 134 compares the data held in the load data register 133 with the expected value data which is hard set in the expected value data storage part 132. When, as a result of this comparison, the data held in the load data register 133 and the expected value data set in the expected value data storage part 132 do not coincide, it is determined that the ASIC chip 110 is in a transient state and that it has not yet reached a stable state which performs normal operation. On the other hand, when the data held in the load data register 133 and the expected value data set in the expected value data storage part 132 coincide, it is determined that the ASIC chip 110 has reached the stable state.
Therefore, the data comparison circuit 134 generates the reset signal RS which, when the data held in the load data register 133 and the expected value data set in the expected value data storage part 132 do not coincide, changes over the logic circuit 140 in the ASIC chip 110 to the reset state, and when the data held in the load data register 133 and the expected value data set in changes over the logic circuit 140 in the ASIC chip 110 to the reset release state. At the time t12, went the data held in the load data register 133 and the expected value data set in the expected value data storage part 132 coincide, the expected value data storage part 132 coincide, the reset signal RS is low level before the time t12, and high-level after the time t12, for example as shown in FIG. 3. Also at the time t12, when the data held in the load data register 133 and the expected value data set in the expected value data storage part 132 do not coincide, the reset signal RS continues to be maintained at a low level, and the logic circuit 140 maintains the reset state.
As described above, according to the first embodiment, before verifying that the supply voltage has reached the state where the internal circuit can be stably operated, the internal circuit of the internal circuit is in a reset state using the load data register 133, the expected value data storage part 132 and the data comparison circuit 134, and after making the aforesaid verification, the reset state of the internal circuit is in a reset release state. Hence, if the integrated circuit device 100 or reset circuit 130 according to the first embodiment is used, after the supply voltage reaches the state where operational stability of the internal circuit can be achieved, the internal circuit can be changed over to the normal operation state (i.e., reset release state) in the same way as an integrated circuit device which has an external reset terminal.
FIG. 4 is a block diagram showing the construction of a modification of the integrated circuit device according to the first embodiment. In FIG. 4, parts which are identical or corresponding to those shown in FIG. 2 are given identical symbols. In the integrated circuit device 100 shown in FIG. 2, the ROM chip 120 is a part of the integrated circuit device 100, but in an integrated circuit device 200 shown in FIG. 4, a ROM device 220 is not a part of the integrated circuit device 200, and is connected to the integrated circuit device 200 by an input/output port 160. The integrated circuit device 200 shown in FIG. 4 is identical to the integrated circuit device 100 shown in FIG. 2 except that the ROM device 220 is external.
FIG. 5 is a block diagram showing the construction of another modification of the integrated circuit device according to the first embodiment. In FIG. 5, parts which are identical or corresponding to those shown in FIG. 2 are given identical symbols. In the integrated circuit device 100 shown in FIG. 2, the ROM chip 120 is a separate chip from the ASIC chip 110 of the integrated circuit device 100, but in the integrated circuit device 300 shown in FIG. 5, a ROM 320 is formed as a part of the ASIC chip 310 of the integrated circuit device 300. The integrated circuit device 300 shown in FIG. 5 is identical to the integrated circuit device 100 shown in the aforesaid FIG. 2 except that the ROM 320 is formed as part of the ASIC chip 310.
Second Embodiment FIG. 6 is a diagram showing the construction and operation of an integrated circuit device according to a second embodiment of the present invention. FIG. 7 is a block diagram showing the construction of the integrated circuit device according to the second embodiment. As shown in FIGS. 6 and 7, and integrated circuit device 400 includes an SOG type ASIC chip 410 and a ROM chip 420.
As shown in FIG. 6, the ASIC chip 410 has a reset circuit 430 which generates a reset signal RS, a logic circuit (internal circuit) 440, an oscillator 450 which generates an internal clock CLK, and an input/output port 460. The logic circuit 440 is either in a reset state (i.e., an initialized state before starting normal operation of the logic circuit 430), or a reset release state (i.e., a state after starting normal operation of the logic circuit 430) according to the reset signal RS generated by the reset circuit 430.
As shown in FIGS. 6 and 7, the reset circuit 430 includes a read command/address generating circuit 431 which generates an address ADR and a read command COM for data which is auto-loaded according to the internal clock CLK, a first register (expected value data storage part) 432 which stores predetermined expected value data, a second register (load data register) 433 holding data which was auto-loaded, a data comparison circuit (reset controller) 434 which compares the data held in the second register 433 and the expected value data stored in the first register 432, and generates a reset signal RS based on a result of this comparison, a first counter 135, and a second counter 136.
The first counter 435 performs a cyclic count of the internal clock CLK to a fixed value (for example, in the case of a twenty-bit configuration, �FFFFF� (hexadecimal notation)), and the second counter 436 measures the number of times the first counter 435 performed the cyclic count. In the second embodiment, at a time (i.e., time t22) when the second counter 436 has measured a predetermined number of times, a comparison between the data held in the second register 433 and the expected value data stored by the first register 432 is performed, and the reset signal RS is generated based on a result of this single comparison. In the aforesaid first embodiment, when the data held in the load data register 133 and the expected value data which is hard set in the expected value data storage part 132 coincide, the data comparison circuit 134 unconditionally performs reset release, but in the second embodiment, before the second counter 436 reaches the predetermined value (e.g., all bits are �1�, i.e., the count value is �63�), reset release is not performed.
Although the integrated circuit device 400 may, for example, be a semiconductor memory device, if the present invention is a semiconductor device other than a semiconductor memory device having a function to load data, it can also be applied also to a device other than a semiconductor memory device.
FIG. 8 is a timing chart showing the operation of the integrated circuit device 400 and the operation of the reset circuit 430. As shown in FIG. 8, after power is supplied to the integrated circuit device 400 (after a time t20), the supply voltage Vd rises and is stabilized at a predetermined voltage. After power starts to be supplied, when the supply voltage Vd reaches the voltage at which oscillation of the oscillator 150 is possible (time t21), the oscillator 450 oscillates and the internal clock CLK is outputted. The read command/address generating circuit 431 performs a cyclic count of this internal clock CLK up to a steady value (for example, in the case of a twenty-bit configuration, �FFFFF� (hexadecimal notation)) with the first counter 435, and sends the address ADR and a read command COM to the ROM chip 420 according to this count. In this way, read-out of the preprogrammed data (16 bits�4 words) stored in the domain specified in the address ADR of the ROM chip 420 is performed. The data read by this auto-loading operation (period AL) is held in the load data register 433 (16 bits�4 words) of the ASIC chip 410. In the second embodiment, as shown in FIG. 8, the auto-load AL is repeated plural times (in FIG. 8, sixty four times), and at the time t22, the data held in the lead data register 433 and the expected value data which is hard set in the expected value data storage part 432 are compared.
When the data held in the load data register 433 and the expected value data set in the expected value data storage part 432 do not coincide, it is determined that the ASIC chip 410 is in a transient state and the stable state in which normal operation is performed has not been reached. On the other hand, when the data held in the load data register 133 and the expected value data set in the expected value data storage part 432 coincide, it is determined that the ASIC chip 410 has reached the stable state.
Therefore, the data comparison circuit 434 generates the reset signal RS which, when the data held in the load data register 433 and the expected value data set in the expected value data storage part 432 do not coincide, changes over the logic circuit 140 in the ASIC chip 410 to the reset state, and when the data held in the load data register 433 and the expected value data set in the expected value data storage part 432 coincide, changes over the logic circuit 440 in the ASIC chip 110 to the reset release state. At the time t22, when the data held in the load data register 433 and the expected value data set in the expected value data storage part 432 coincide, the reset signal RS is low-level before the time t22, and high-level after the time t22, for example as shown in FIG. 8. Also at the time t22, when the data held in the load data register 433 and the expected value data set in the expected value data storage part 432 do not coincide, the reset signal RS continues to be maintained at a low level, and the logic circuit 440 maintains the reset state.
As described above, according to the second embodiment, before verifying that the supply voltage has reached the state where the internal circuit can be stably operated, using the load data register 433, the expected value data storage part 432 and the data comparison circuit 434, the internal circuit is in a reset state, and after the aforesaid verification, the reset state of the internal circuit is released. Hence, if the integrated circuit device 400 or reset circuit 430 according to the first embodiment is used, after the supply voltage reaches the state where operational stability of the internal circuit can be achieved, the internal circuit can be changed over to the normal operation state (reset release state) in the same way as an integrated circuit device which has an external reset terminal.
FIG. 9 is a timing chart showing the operation of a modification of the integrated circuit device according to the second embodiment. A difference from the operation shown in FIG. 8 is that a comparison between the data stored in the second register 433 and the expected value data stored in the first register 432 is performed each time the internal clock CLK is counted up to a fixed value (for example, in the case of a twenty-bit configuration, �FFFFF�(hexadecimal notation) (times t101, . . . , t164) and the reset signal RS is generated based on these plural comparison results. In the example shown in FIG. 9, the reset signal is generated such that, if the data held in the load register 433 and the expected value data set in the expected value data storage part 432 do not coincide for at least one of the times t101, . . . , t164, the logic circuit 440 in the ASIC chip 410 is changed over to the reset state, and when the data held in the load data register 433 and the expected value data set in the expected value data storage part 432 coincide at all the times t101, . . . , t164, the logic circuit 440 in the ASIC chip 410 is changed over to the reset release state.
In the operation of FIG. 9, in addition to the effect of the operation of FIG. 8, incorrect reset release due to a ROM read-out fault when power starts to be supplied, and incorrect reset release due to accidental coincidence between the initial value of the load data register 433 and the expected value data, can be prevented.
In the first and second embodiments described above, an auto-loading operation was performed when power was switched on by the oscillators 150, 450, and the load command/address generating circuits 131, 431, but the invention is not limited to this construction, and can be applied to any construction where data stored in a ROM is read when power is switched on.
Moreover, in the first and second embodiments, although the data read by auto-load, the load data registers 133,433 and the expected value data storage parts 132, 432 were considered to have a bit width of 16 bits�4 words, and a six-bit construction where the counters 135, 435, 436 can count from �0� to �63� was assumed, the invention is not limited to this construction and may be any construction depending on the magnitude of noise or the usage situation of the ASIC.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6026034 *May 7, 1998Feb 15, 2000Fujitsu LimitedBit line reset circuit of memoryUS6111805 *Nov 19, 1998Aug 29, 2000Mitsubishi Denki Kabushiki KaishaPower-on-reset circuit for generating a reset signal to reset a DRAMUS6826114 *Jul 22, 2003Nov 30, 2004Samsung Electronics Co., Ltd.Data path reset circuit using clock enable signal, reset method, and semiconductor memory device including the data path reset circuit and adopting the reset methodUS20040090830 *Jul 22, 2003May 13, 2004Samsung Electronics Co., Ltd.Data path reset circuit using clock enable signal, reset method, and semiconductor memory device including the data path reset circuit and adopting the reset methodJPH05299993A Title not available* Cited by examinerClassifications U.S. Classification365/189.07, 365/189.04, 365/230.01International ClassificationG11C7/00, G06F1/24Cooperative ClassificationG06F1/24European ClassificationG06F1/24Legal EventsDateCodeEventDescriptionJul 21, 2011FPAYFee paymentYear of fee payment: 4Dec 24, 2008ASAssignmentOwner name: OKI SEMICONDUCTOR CO., LTD., JAPANFree format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022052/0797Effective date: 20081001Owner name: OKI SEMICONDUCTOR CO., LTD.,JAPANFree format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100225;REEL/FRAME:22052/797Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100413;REEL/FRAME:22052/797Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100420;REEL/FRAME:22052/797Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100511;REEL/FRAME:22052/797Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:22052/797Jan 11, 2005ASAssignmentOwner name: OKI ELECTRIC INDUSTRY CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TANAKA, HITOSHI;FUKUYAMA, HIROYUKI;YONAGA, TAKERU;REEL/FRAME:016144/0958Effective date: 20041029RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google