Source: https://patents.google.com/patent/US6081036
Timestamp: 2018-02-21 01:13:48
Document Index: 500557545

Matched Legal Cases: ['arts 76', 'arts 71', 'arts 81', 'arts 81', 'arts 81', 'arts 86', 'arts 81', 'arts 88']

US6081036A - Semiconductor device - Google Patents
US6081036A
US6081036A US08973891 US97389198A US6081036A US 6081036 A US6081036 A US 6081036A US 08973891 US08973891 US 08973891 US 97389198 A US97389198 A US 97389198A US 6081036 A US6081036 A US 6081036A
US08973891
A semiconductor device is provided wich includes a first wiring and second wirings in which end portions of the second wirings connected to the first wiring are bent parallel to that forms a predetermined angle with respect to the first direction. The first wiring extends along a first direction and has a wiring width direction in a second direction perpendicular to the first direction, where stresses are generated inside. The second wirings are situated above the first wiring, connected to the first wiring through a contact hole, and affected by the stresses of the first wiring.
The present invention relates to a semiconductor device and, more particularly, to a construction for suppressing deterioration of performance and reliability due to thermal stresses that are generated in its composing material.
Conventionally, there is a semiconductor device which has a multilayer wiring structure. In such a semiconductor device, lower layer wirings and upper layer wirings are electrically connected through contact holes that are formed in an interlayer insulating film.
In order to achieve the object, a semiconductor device of claim 1 includes a first wiring extending along a first direction and having a wiring width direction in a second direction perpendicular to the first direction, where stresses are generated inside, and second wirings electrically connected to the first wiring and affected by the stresses of the first wiring, wherein end portions of the second wirings connected to the first wiring are bent parallel to a direction that forms a predetermined angle with respect to the first direction.
FIG. 1(a) is a plan view illustrating a wiring structure of a semiconductor device in accordance with a first embodiment of the present invention, and
In this case, the lower layer wiring 51 is formed by patterning a platinum layer that is formed on a silicon substrate 5 via an insulating film, and has six bent portions 52a˜52f in a region between the contact holes 7a and 7b. More specifically, a body 51c of the lower layer wiring 51, except the both end portions 51a and 51b, comprises first to fourth lateral side portions 51c11 ˜51c14 parallel to the first direction D1, and first to third longitudinal side portions 51c21 ˜51c23 parallel to a second direction D2 perpendicular to the first direction D1, and has a structure in which the lateral side portions and the longitudinal side portions are alternately connected. Connection portions of the adjacent lateral side portions and longitudinal side portions are the bent portions 52a˜52f, respectively. As a result, the lower layer wiring 51 has a zigzag-shaped plan as a whole.
In the fifth embodiment with such a construction, the lower layer wiring 51 has more bent portions 52a˜52f than those of the lower layer wiring 31 of the third embodiment. Therefore, the tensile stresses in the lateral direction of the lower layer wiring are reduced by the transformation of the six bent portions. As a result, as compared with the third embodiment, the reduction in stresses can be realized more satisfactory.
FIG. 5(b) illustrates a wiring structure according to a modification example of the fifth embodiment of the invention. In the wiring structure of this modification example, in place of the longitudinal side portions 51c21 ˜51c23 of the lower layer wiring 51 of the fifth embodiment, a lower layer wiring has a plurality of oblique side portions parallel to a direction between first and second directions.
In this case, the lower layer wiring 56 is formed by patterning a platinum layer that is formed on a silicon substrate 5 via an insulating film, and has eight bent portions 57a˜57h in a region between the contact holes 7a and 7b. More specifically, a body 56c of the lower layer wiring 56 comprises first to fifth lateral side portions 56c11 ˜56c15 parallel to the first direction D1, second and third longitudinal side portions 56c22 and 56c23 parallel to a direction that forms an angle of about +45° with respect to the first direction D1, and first and fourth longitudinal side portions 56c21 and 56c24 parallel to a direction that forms an angle of about -45° with respect to the first direction D1, and has a structure in which the lateral side portions and the oblique side portions are alternately connected. Connection portions of the adjacent lateral side portions and oblique side portions are the bent portions 57a˜57h, respectively. As a result, the lower layer wiring 56 has a zigzag-shaped plan as a whole.
In the modification example of the fifth embodiment with such a construction, the lower layer wiring 56 having the zigzag plan shape is constituted by alternately arranging the lateral side portions parallel to the first direction D1 and the oblique side portions that form angles of 45° with respect to the first direction. Therefore, the size of the lower layer wiring 56 having the zigzag plan shape in the second direction D2 perpendicular to the first direction D1 is reduced. As a result, the area of the lower layer wiring 56 on the substrate can be reduced, as compared with the area in the fifth embodiment.
In this case, the lower layer wiring 71 is formed by patterning a platinum layer that is formed on a silicon substrate 5 via an insulating film, and has narrow wiring width portions 71c10, 71c20, 71c30 and 71c40 with narrower wiring widths than those of the other portions, the narrow portions being formed by chipping portions of a body 71c, except the end portions 71a and 71b connected to the upper layer wirings 2a and 2b. The narrow wiring width portions 71c10 ˜71c40 are formed by chipping the body 71c of the lower layer wiring 71 at from both sides at predetermined positions in the wiring path. Reference characters 71c11, 71c22, 71c33 and 71c44 designate chipped parts of rectangular shapes at the respective narrow wiring width portions 71c10 ˜71c40.
In the seventh embodiment with such a construction, the lower layer wiring 71 in which the thermal stresses are generated has the narrow wiring width portions 71c10 ˜71c40 with narrower wiring widths than those of the other portions, at its portions. Therefore, the lower layer wiring 71 is probable to be transformed by stretching at the narrow wiring width portions, whereby the thermal stresses generated in the lower layer wiring 71 are satisfactorily reduced by the transformation of the narrow wiring width portions. Consequently, breaking of the upper layer wirings 2a and 2b, connection portions of the upper layer wirings and the lower layer wiring 71 and the like due to the tensile stresses being generated in the lower layer wiring 71 can be suppressed, leading to improved reliability of the semiconductor device.
In this case, the lower layer wiring 76 is formed by patterning a platinum layer that is formed on a silicon substrate 5 via an insulating film, and has narrow wiring width portions 76c10, 76c20, 76c30 and 76c40 with narrower wiring widths than those of the other portions, the narrow portions being formed by chipping portions of a body 76c, except the end portions 76a and 76b connected to the upper layer wirings 2a and 2b. The narrow wiring width portions 76c10 ˜76c40 are formed by chipping the body 76c of the lower layer wiring 76 from both sides at predetermined positions in the wiring path. Reference characters 76c11, 76c22, 76c33 and 76c44 designate chipped parts of V shapes at the respective narrow wiring width portions 76c10 ˜76c40.
In the modification example of the seventh embodiment with such a construction, the shapes of the chipped parts 76c11 ˜76c44 of the narrow wiring width portions 76c10 ˜76c40 are V shapes. Therefore, as compared with the chipped parts 71c11 ˜71c44 of rectangular shapes according to the seventh embodiment, the areas of the chipped parts in the lower layer wiring 76 can be reduced, whereby it is more advantageous when elements, such as capacitors, are disposed on the lower layer wiring 76.
In this case, the lower layer wiring 81 is formed by patterning a platinum layer that is formed on a silicon substrate 5 via an insulating film. A body 81c, except end portions 81a and 81b that are connected to the upper layer wirings 2a and 2b, has first narrow wiring width portions 81c10 and 81c30 with narrower wiring widths than those of the other portions, the narrow portions being formed by chipping one side of the body 81c, and second narrow wiring width portions 81c20 and 81c40 with narrower wiring widths than those of the other portions, the narrow portions being formed by chipping the other side of the body 81c. The first narrow wiring width portions 81c10 and 81c30, and the second narrow wiring width portions 81c20 and 81c40 are alternately arranged along the first direction D1. Reference characters 81c11, 81c22, 81c33 and 81c44 designate chipped parts of rectangular shapes at the respective narrow wiring width portions 81c10 ˜81c40.
In the eighth embodiment with such a construction, the lower layer wiring 81 in which the thermal stresses are generated has the narrow wiring width portions 81c10 ˜81c40 with narrower wiring widths than those of the other portions, at its portions. Therefore, the lower layer wiring 81 can be easily transformed by stretching at the narrow wiring width portions, whereby the thermal stresses generated in the lower layer wiring 81 are satisfactorily reduced by the transformation of the narrow wiring width portions. Consequently, breaking of the upper layer wirings 2a and 2b, connection portions of the upper layer wirings and the lower layer wiring 81 and the like due to the tensile stresses being generated in the lower layer wiring 81 can be suppressed, leading to improved reliability of the semiconductor device.
Further, in the eighth embodiment of the invention, the chipped parts 81c11 and 81c33 at one side of the lower layer wiring 81, and the chipped parts 81c22 and 81c44 at the other side of the lower layer wiring 81 are alternately arranged along the wiring path. Therefore, the lower layer wiring 81 is transformed by stretching at the narrow wiring width portions 81c10 ˜81c40 due to the tensile stresses, as well as the chipped parts 81c11 ˜81c44 are transformed by curving so that their openings become wider. Accordingly, by the transformation by stretching and the transformation by curving, the tensile stresses in the lower layer wiring are exceedingly reduced. As a result, production of breaking of the upper layer wirings 2a and 2b connected to the lower layer wiring 81, connection portions of the lower layer wiring and the upper layer wirings and the like can be exceedingly reduced.
In this case, the lower layer wiring 86 is formed by patterning a platinum layer that is formed on a silicon substrate 5 via an insulating film. A body 86c of this lower layer wiring 86, except the end portions 86a and 86b connected to the upper layer wirings 2a and 2b, has first narrow wiring width portions 86c10 and 86c30 with narrower wiring widths than those of the other portions, the narrow portions being formed by chipping one side of the body 86c, and second narrow wiring width portions 86c20 and 86c40 with narrower wiring widths than those of the other portions, the narrow portions being formed by chipping the other side of the body 86c. The first narrow wiring width portions 86c10 and 86c30, and the second narrow wiring width portions 86c20 and 86c40 are alternately arranged along the first direction D1. Reference characters 86c11, 86c22, 86c33 and 86c44 designate chipped parts of V shapes at the respective narrow wiring width portions 86c10 ˜86c40.
In the modification example of the eighth embodiment with such a construction, the shapes of the chipped parts 86c11 ˜86c44 of the narrow wiring width portions 86c10 ˜86c40 are V shapes. Therefore, as compared with the chipped parts 81c11 ˜81c44 of rectangular shapes according to the eighth embodiment, the areas of the chipped parts in the lower layer wiring 86 can be reduced. It is more advantageous when elements, such as capacitors, are disposed on the lower layer wiring 86.
In this case, the lower layer wiring 88 is formed by patterning a platinum layer that is formed on a silicon substrate 5 via an insulating film. A body 88c of this lower layer wiring 88, except the end portions 88a and 88b connected to the upper layer wirings 2a and 2b, has first narrow wiring width portions 88c10 and 88c30 with narrower wiring widths than those of the other portions, the narrow portions being formed by chipping one side of the body 88c, and second narrow wiring width portions 88c20 and 88c40 with narrower wiring widths than those of the other portions, the narrow portions being formed by chipping the other side of the body 88c. The first narrow wiring width portions 88c10 and 88c30, and the second narrow wiring width portions 88c20 and 88c40 are alternately arranged along the first direction D1. The wiring widths of the respective narrow wiring width portions 88c10 ˜88c40 are smaller than 1/2 of the wiring widths of portions of the wiring body 88c, except the narrow wiring width portions. In other words, the current path along the center line of the lower layer wiring 88 is divided into parts by chipped parts 88c11, 88c22, 88c33 and 88c44 of rectangular shapes at the respective narrow wiring width portions 88c10, 88c20, 88c30 and 88c40.
In the second modification example of the eighth embodiment with such a construction, the wiring widths of the respective narrow wiring width portions 88c10 ˜88c40 are smaller than 1/2 of the wiring widths of portions of the wiring body 88c, except the narrow wiring width portions. Therefore, in the narrow wiring width portions at which the chipped parts are formed, there occurs not only transformation by stretching but transformation by curving due to the thermal stresses of the lower layer wiring. As a result, as compared with the narrow portions of the eighth embodiment, the narrow wiring width portions can be very easily transformed by the thermal stresses of the lower layer wiring, whereby breaking of the upper layer wirings and connection portions of the upper layer wirings and the lower layer wiring due to the thermal stresses can be further suppressed.
In this case, the lower layer wiring 91 is formed by patterning a platinum layer that is formed on a silicon substrate 5 via an insulating film. A body 91c, except the end portions 91a and 91b connected to the upper layer wirings 2a and 2b, has a plurality of through openings 91c1 ˜91c4 at predetermined intervals along the first direction D1. These through openings 91c1 ˜91c4 have rectangular shapes, and its longitudinal direction matches with the first direction D1.
In the ninth embodiment with such a construction, the lower layer wiring 91 in which the thermal stresses are generated has the plurality of through openings 91c1 ˜91c4 that are disposed along the longitudinal direction of the wiring (first direction) D1. Therefore, portions of the body 91c of the lower layer wiring 91 in which the through openings are formed can be easily transformed by stretching due to the thermal stresses being generated in the lower layer wiring 91, whereby the thermal stresses in the lower layer wiring 91 are satisfactorily reduced. Consequently, breaking of the upper layer wirings 2a and 2b, connection portions of the upper layer wirings and the lower layer wiring 91 and the like due to the thermal stresses in the lower layer wiring 91 can be suppressed, leading to improved reliability of the semiconductor device.
In this case, the lower layer wiring 96 is formed by patterning a platinum layer that is formed on a silicon substrate 5 via an insulating film. A body 96c, except the end portions 96a and 96b connected to the upper layer wirings 2a and 2b, has a plurality of through openings 96c1 ˜96c4 at predetermined intervals along the first direction D1. These through openings 96c1 ˜96c4 have rectangular shapes, and its longitudinal direction matches with the second direction D2 perpendicular to the first direction D1.
In the modification example of the ninth embodiment with such a construction, the lower layer wiring 96 in which the thermal stresses are generated has the plurality of through openings 96c1 ˜96c4 of rectangular shapes that are disposed along its wiring direction, and the longitudinal direction of the through openings 96c1 ˜96c4 of rectangular shapes matches with the second direction D2 perpendicular to the wiring direction of the lower layer wiring 96 (first direction) D1. Therefore, at portions of the body 96c of the lower layer wiring 96 in which the through openings are formed, substantial wiring widths are smaller than those in the ninth embodiment, whereby the portions can be more easily transformed by stretching due to the thermal stresses being generated in the lower layer wiring 96. Thereby, the thermal stresses in the lower layer wiring 96 are reduced more effectively. Consequently, breaking of the upper layer wirings 2a and 2b, connection portions of the upper layer wirings and the lower layer wiring 96 and the like due to the thermal stresses in the lower layer wiring 96 can be further suppressed, leading to further improved reliability of the semiconductor device.
According to a semiconductor device of claim 1, the semiconductor device includes a first wiring extending along a first direction, where stresses are generated inside, and second wirings connected to the first wiring, and end portions of the second wirings connected to the first wiring are bent parallel to a second direction that forms a predetermined angle with respect to the first direction. Therefore, the end portions of the second wirings can be easily transformed by the thermal stresses in the first direction that are generated in the first wiring, thereby effectively reducing the thermal stresses. Consequently, breaking of connection portions of the first and second wirings and breaking of the second wirings due to the thermal stresses being generated in the first wiring can be suppressed, resulting in improved reliability of the semiconductor device.
a first wiring extending along a first direction and having a wiring width direction in a second direction perpendicular to the first direction, where stresses are generated inside; and
second wirings which are situated above the first wiring, connected to the first wiring through a contact hole, and affected by the stresses of the first wiring;
said second wirings including end portions which are connected to the first wiring, said end portions of said second wirings being bent in a direction which is parallel to a direction that forms a predetermined angle with respect to the first direction and on a plane including the first direction and the second direction.
2. The semiconductor device as defined in claim 1, wherein;
the end portions of the second wirings connected to the first wiring are bent parallel to the second direction perpendicular to the first direction.
3. The semiconductor device as defined in claim 1, wherein the first wiring comprises at least one member selected from the group consisting of platinum, iridium, titanium and tungsten.
a first wiring extending along a first direction and having a wiring width direction and a second direction perpendicular to the first direction, where stresses are generated inside; and
second wirings which are situated above the first wiring, connected to end portions of the first wiring through a contact hole, and affected by the stresses of the first wiring;
wherein the second wirings include end portions which are bent with respect to the remainder of the second wirings, said end portions being on a plane which is parallel to a plane defined by said first wiring and includes the first direction and the second direction, wherein tip parts of the end portions of the second wirings are connected to the first wiring and are disposed to extend along the first wiring and toward the inside of the first wiring.
6. The semiconductor device as defined in claim 5, wherein the first wiring comprises at least one member selected from the group consisting of platinum, iridium, titanium and tungsten.
a first wiring extending along a first direction and having a wiring width which is planarly perpendicular to the first direction; and
second wirings which are situated above the first wiring, connected to the first wiring through a contact hole and affected by the stresses of the first wiring;
wherein the first wiring has a bent portion formed at a portion of the first wiring; and
the second wirings having end portions connected to the first wiring, said end portions being bent parallel to a direction that forms a predetermined angle with respect to the first direction on a plane including the first direction and the second direction.
9. The semiconductor device as defined in claim 8, wherein;
a body of the first wiring, except end portions that are connected to the second wirings, is bent at a plurality of positions to have a zigzag plan shape.
10. The semiconductor device as defined in claim 9, wherein;
the first wiring body comprises only oblique wiring parts parallel to directions, except a direction perpendicular to a first direction, or only the oblique wiring parts and wiring parts parallel to the first direction.
11. The semiconductor device as defined in claim 8, wherein the first wiring comprises at least one member selected from the group consisting of platinum, iridium, titanium and tungsten.
second wirings which are situated above the first wiring, connected to the first wiring through a contact hole, and affected by the stresses of the first wiring
wherein the whole of the first wiring is divided into a plurality of wiring parts; and
the respective wiring parts of the first wiring are electrically connected by the second wirings to form a predetermined current path extending from one end of the first wiring to the other end, the respective wiring parts of the first wiring having wiring lengths, each wiring length being not more than twenty times that of a corresponding wiring width.
14. A ferroelectric memory device having a plurality of ferroelectric capacitors, said device including:
a first wiring, which extends along a first direction and having a wiring width direction in a second direction perpendicular to the first direction, where stresses are generated inside; and
second wirings, which are electrically connected to the first wiring and are affected by the stresses of the first wiring, said first wiring and said second wirings constituting the ferroelectric capacitors,
wherein the first wiring has narrow wiring width portions formed by chipping portions of a first wiring body, with the exception of end portions that are connected to the second wirings, the wiring width of each of the narrow wiring width portions being narrower than that of remaining wiring width portions except the end portions, and the length of the narrow wiring width portions being shorter than that of the remaining wiring width portions.
15. The semiconductor device as defined in claim 14, wherein;
the narrow wiring width portions are formed by chipping the first wiring body from the both sides at predetermined positions in the wiring path.
16. The semiconductor device as defined in claim 15, wherein;
sides of the narrow wiring width portions are parallel to directions, except a direction perpendicular to the first direction.
17. The semiconductor device as defined in claim 14, wherein;
the first wiring body has at least a first narrow wiring width portion that is formed by chipping the body from one side, and at least a second narrow wiring width portion that is formed by chipping the body from the other side.
18. The semiconductor device as defined in claim 17, wherein;
the wiring widths of the first and second narrow wiring width portions are smaller than 1/2 of those of the portions of the first wiring body, except the narrow wiring width portions, and the current path along the center line of the first wiring is divided by the chipped parts at the first and second narrow wiring width portions.
19. The semiconductor device as defined in claim 17, wherein;
sides of the first and second narrow wiring width portions at the chipped part sides are parallel to directions, except a direction perpendicular to the first direction.
20. The semiconductor device as defined in claim 8, wherein the first wiring comprises at least one member selected from the group consisting of platinum, iridium, titanium and tungsten.
22. A ferroelectric memory device having ferroelectric capacitors including:
a first wiring which extends along a first direction and having a wiring width direction in a second direction perpendicular to the first direction, where stresses are generated inside; and
second wirings which are situated above the first wiring, connected to the first wiring through a contact hole, and affected by the stresses of the first wiring, said first wiring and said second wirings constituting ferroelectric capacitors,
said first wiring having through openings that are formed in a first wiring body, said body including end portions which are connected to the second wirings.
23. The semiconductor device as defined in claim 22, wherein;
the plan shapes of the through openings are made a rectangular shape in which the length in the first direction is smaller than the length in the second direction perpendicular to the first direction.
24. The semiconductor device as defined in claim 14, wherein the first wiring comprises at least one member selected from the group consisting of platinum, iridium, titanium and tungsten.
26. A semiconductor device constituting a ferroelectric memory device with a plurality of memory cells comprising transistors and ferroelectric capacitors, wherein:
the ferroelectric capacitor comprises a first electrode where stresses are generated inside, a second electrode positioned opposite to this first electrode, and a ferroelectric layer positioned between the first and second electrodes;
the first electrode having a bent portion formed at its portion.
27. The semiconductor device as defined in claim 26, wherein;
a body of the first electrode, except both end portions, is bent at a plurality of positions to have a zigzag plan shape.
28. The semiconductor device as defined in claim 19, including:
first and second memory cell groups each comprising a plurality of memory cells;
first and second bit line groups corresponding to the first and second memory cell groups;
first and second word line groups provided corresponding to the first and second memory cell groups, and comprising a plurality of word lines for controlling ON and OFF of transistors constituting the memory cells of the corresponding memory cell groups; and
sense amplifiers connected to the respective bit lines of the first and second bit line groups, for sensing storage data on the bit lines, wherein:
the first electrode of the ferroelectric capacitor constituting each memory cell is connected to a cell plate line for applying a predetermined driving voltage to the electrode;
the second electrode of the ferroelectric capacitor constituting each memory cell of the first memory cell group is connected to the corresponding bit line of the first bit line group through the transistor of the first memory cell group;
the second electrode of the ferroelectric capacitor constituting each memory cell of the second memory cell group is connected to the corresponding bit line of the second bit line group through the transistor of the second memory cell group; and
the word line of the first word line group and the word line of the second word line group are simultaneously selected so that complementary data is read out onto the corresponding bit lines of both of the bit line groups.
29. A semiconductor device constituting a ferroelectric memory device with a plurality of memory cells comprising transistors and ferroelectric capacitors, wherein:
the ferroelectric capacitor comprises a first electrode that extends along a first direction, where stresses are generated inside, a second electrode positioned opposite to this first electrode, and a ferroelectric layer positioned between the first and second electrodes;
the whole of the first electrode being divided into a plurality of electrode parts, and the respective electrode parts being electrically connected to form a predetermined current path extending from one end of the first electrode to the other end.
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