Source: http://www.google.com/patents/US7859991?dq=5251294
Timestamp: 2017-08-17 06:50:27
Document Index: 417012371

Matched Legal Cases: ['art 3', 'art 3', 'art 3', 'art 2', 'art 3', 'art 3', 'art 2', 'art 3', 'art 2', 'art 2', 'art 3', 'art 2', 'art 3', 'art 1012', 'art 1011', 'art 1015', 'art 1011', 'art 1013', 'art 1042', 'arts 1011', 'art 1043', 'arts 1015', 'art 1015', 'art 1013', 'art 1042', 'art 1042', 'art 1011', 'art 1043', 'art 1015', 'art 1042', 'art 1012', 'art 1043', 'art 1015', 'art 1013', 'art 1022', 'art 1042', 'art 1031', 'art 1043', 'art 1015', 'art 1013', 'art 1032', 'art 2013', 'art 2013', 'art 2013', 'art 2014', 'art 2014']

Patent US7859991 - Signal transmitting apparatus, power supplying system, and serial ... - Google Patents
A signal transmitting apparatus includes a sending part and a receiving part. The sending part converts each width of a plurality of digital input signals into a voltage in accordance with a predetermined weight, generates a send signal by adding voltages converted from the plurality of digital input...http://www.google.com/patents/US7859991?utm_source=gb-gplus-sharePatent US7859991 - Signal transmitting apparatus, power supplying system, and serial communication apparatus
Publication number US7859991 B2
Application number US 10/552,688
PCT number PCT/JP2004/005376
Also published as CN1795635A, CN1795635B, EP1614249A1, EP1614249A4, US20060280112, WO2004093377A1
Publication number 10552688, 552688, PCT/2004/5376, PCT/JP/2004/005376, PCT/JP/2004/05376, PCT/JP/4/005376, PCT/JP/4/05376, PCT/JP2004/005376, PCT/JP2004/05376, PCT/JP2004005376, PCT/JP200405376, PCT/JP4/005376, PCT/JP4/05376, PCT/JP4005376, PCT/JP405376, US 7859991 B2, US 7859991B2, US-B2-7859991, US7859991 B2, US7859991B2
Patent Citations (24), Referenced by (1), Classifications (29), Legal Events (4)
Signal transmitting apparatus, power supplying system, and serial communication apparatus
US 7859991 B2
Next, the receiving part 3 a includes voltage comparators CMP11 and CMP12 and resistors R13 through R15. The resistors R13 through R15 configure reference voltage generating circuits, the voltage comparators CM11 and CMP12 configure voltage generating circuits, and the voltage comparators CMP11 and CMP12 configure voltage comparing circuits. Each wiring line connected to each output terminal of the voltage comparators CMP11 and CMP12 configures a pseudo logic circuit. A signal input to a receiving terminal INa is input to each inverting input terminal of the voltage comparators CMP11 and CMP12. The resistors R13 through R15 are connected in series between the power voltage Vdd and the earth ground. A connection portion of the resistor R13 and the resistor R14 is connected to a non-inverting input terminal of the voltage comparator CMP11, and a connection portion of the resistor R14 and the resistor R15 is connected to a non-inverting input of the voltage comparator CMP12. The output terminal of the voltage comparator CMP11 configures one output terminal of the receiving part 3 a and the output terminal of the voltage comparator CMP12 configures another output terminal of the receiving part 3 a.
In this configuration described above, in a case in that the power voltage Vdd is set to be 4V and a resistance value of the resistor R11 is the same as a resistance value of the resistor R12, an output voltage VoA corresponding to each combination of signal levels of the digital input signal Ai and Bi becomes as shown in FIG. 13. As seen from FIG. 13, by setting the resistance value of the resistor R11 to be the same as the resistance value of the resistor R12, amplitudes of the digital input signals Ai and Bi are evenly changed.
That is, in FIG. 13, in a case of a state M4 a in that both the digital input signals Ai and Bi are the low level, the output voltage VoA becomes 4V of a predetermined value V3 a. And in a case of a state M3 a in that the digital input signal Ai is the Low level and the digital input signal Bi is the high level, the output voltage VoA becomes 2V of a predetermined value V2 a. Moreover, in a case of a state M2 a in that the digital input signal Ai is the high level and the digital input signal Bi is the high level an in a case of a state M1 a in that both the digital input signals Ai and Bi are the high level, the output voltage VoA becomes 0V of a predetermined value V1 a.
FIG. 14 is a timing chart diagram showing 2 waveform of a signal of each part shown in FIG. 12. Each operation of parts shown in FIG. 12 will be described in detail with reference to FIG. 14.
Different from FIG. 12, in FIG. 15, an NMOS transistor M3 and a resistor R21 are additionally provided to the sending part 2 a shown in FIG. 12 as a switching device. Moreover, instead of the resistors R13 through R15 in the receiving part 3 a shown in FIG. 12, resistors R22 through R26 are additionally provided, and the voltage comparators CMP13 and CMP14 and a logic circuit 11 are additionally provided to the receiving part 3 a.
In FIG. 15, the signal transmitting apparatus 1 b includes a sending part 2 b and a receiving part 3 b. The sending part 2 b converts amplitude of each of the digital input signals Bi and Ci when the digital input signal Ai is the low level, into each voltage in accordance with a predetermined weight, in which the amplitude is converted by a greatest weight in three digital input signals Ai, Bi, and Ci. And the sending part 2 b generates a send signal SoB by adding each voltage of the digital input signals Bi and Ci to a voltage at the low level of the converted digital input signal Ai, and outputs the send signal SoB. The receiving part 3 b receives the send signal SoB from the sending part 2 b through the signal line 5, compares the send signal SoB with each of predetermined Vt6 through Vt9, generates the digital input signal Ai, Bi, and Ci based on the comparison result, and outputs the digital input signal Ai, Bi, and Ci.
Moreover, a connection portion of the resistor R24 and the resistor R25 is connected to a non-inverting input terminal of the voltage comparator CMP13, a connection portion of the resistor R25 and the resistor R26 is connected to a non-inverting input terminal of the voltage comparator CMP14. Each output terminal of the voltage comparators CMP 11 through CMP14 is connected to the logic circuit 11. The logic circuit 11 generates each of the digital input signal Ai, Bi, and Ci from each output signal of the four voltage comparators CMP11 through CMP14 and outputs each of the output signals Ao, Bo, and Co from corresponding output terminals of the receiving part 3 b.
In this circuit configuration, in a case in that the power voltage Vdd is set to be 4V the resistor R11 is set to be 10kΩ, the resistor R11 is 15 kΩ, and the resistor R21 is set to be 30 kΩ, output voltages VoB corresponding to combinations of the signal levels of the digital input signal Ai, Bi, and Ci. As seen from FIG. 16, a resistance ratio of the resistance R12 and the resistance R21 is set to be 1:2, the resistor R12 is connected to the resistor R21 in parallel, and a combined resistance value is set to be approximately equal to a resistance value of the resistor R11, so that a voltage change of the output voltage VoB output from the sending terminal OUTb is made to be relatively greater.
Different from the configuration shown in FIG. 18, in FIG. 19, the controlling part 1012 of the first power supplying unit 1002 is separately configured as a controlling unit 1041, an interface part for connecting the power supplying unit 1002 and the controlling unit 1041 is provided to each of the first power supplying unit 1002 and the controlling unit 1041. Accordingly, the first power supplying unit 1002 shown in FIG. 18 is configured as a first power supplying unit 1002 a shown in FIG. 18, and the power supplying system 1001 shown in FIG. 18 is configured as a power supplying system 1001 a.
In FIG. 19, the power supplying system 1001 a includes the first power supplying unit 1002 a, the second power supplying unit 1003, the third power supplying unit 1004, and a function unit including the first, second, and third power supplying part 1011, 1021, and 1031 and a predetermined function. The power supplying unit 1002 a includes a first interface part 1015 for interfacing between the first power supplying part 1011 and the controlling unit 1041, and a first communicating part 1013. In addition, a controlling part 1042 for conducting operation controls of the first, second, and third power supplying parts 1011, 1021, and 1031, and the function unit 1045, and a second interface part 1043 for interfacing with the first power supplying unit 1002 a.
The first and second interface parts 1015 and 1043 are connected each other and the first interface part 1015 and the first communicating part 1013 are connected each other. The controlling part 1042 and the function unit 1045 send and receive a signal directly each other. The controlling part 1042 sends and receives a signal to and from the first power supplying part 1011 through the second interface part 1043 and the first interface part 1015. Moreover, the controlling part 1042 sends and receives a signal to and from the second power supplying part 1012 through the second interface part 1043, the first interface part 1015, the first communicating part 1013, the communication line 1004, and the second communicating part 1022. Also, the controlling part 1042 sends and receives a signal to and from the third power supplying part 1031 through the second interface part 1043, the first interface part 1015, the first communicating part 1013, the communication line 1004, and the third communicating part 1032.
Differently from the configuration in FIG. 26, in FIG. 31, the circuit configuration of the superimposing pulse generating circuit 2052 in FIG. 26 is changed to be a superimposing pulse generating circuit 2052 a, and the circuit configuration of the output signal generating circuit 2053 is changed to be an output signal generating circuit 2053 a. Thus, the second sending circuit part 2013 in FIG. 26 is shown as a second sending circuit part 2013 a, and the slave sending/receiving circuit 2003 is shown as a slave sending/receiving circuit 2003 a.
In FIG. 31, the slave sending/receiving circuit 2003 a Includes the second sending circuit part 2013 a and the second receiving circuit part 2014. The second receiving circuit part 2014 is the same as that in FIG. 7 and an explanation thereof will be omitted.
US4739309 Mar 13, 1986 Apr 19, 1988 Robert Bosch Gmbh Method and system for indicating and display information in response to electrical signals
JP2002101044A Title not available
JPH0491637A Title not available
JPH0879075A Title not available
JPH01309448A Title not available
JPH02185132A Title not available
JPH03221696A Title not available
JPH05122759A Title not available
JPH11355255A Title not available
JPS5744209A Title not available
JPS61235246A Title not available
U.S. Classification 370/212, 370/535, 370/532, 375/260
International Classification H02J1/10, H04Q9/00, H04L7/00, H04J7/00, H04L25/02, H04L25/03, H04L5/04, H02J13/00, H03M9/00, G06F1/26
Cooperative Classification H04L25/4902, H02J1/10, H04L5/18, H04L25/02, H04N5/23241, H02J13/0003, H04L5/16, H04J3/06
European Classification H04L25/49A, H02J13/00E, H04L5/16, H02J1/10, H04L25/02, H04L5/18, H04N5/232P
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJII, TATSUYA;REEL/FRAME:017832/0282