Source: http://www.google.com/patents/US7925808?dq=3984803
Timestamp: 2014-08-27 13:06:02
Document Index: 398444507

Matched Legal Cases: ['Application No. 60', 'Application No. 200810098473', 'Application No. 2006', 'Application No. 200480003983', 'Application No. 200480003983', 'Application No. 2006', 'Application No. 200810098473', 'Application No. 2006', 'Application No. 200810098473']

Patent US7925808 - Memory system and device with serialized data transfer - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory...http://www.google.com/patents/US7925808?utm_source=gb-gplus-sharePatent US7925808 - Memory system and device with serialized data transferAdvanced Patent SearchPublication numberUS7925808 B2Publication typeGrantApplication numberUS 12/116,439Publication dateApr 12, 2011Filing dateMay 7, 2008Priority dateJan 13, 2003Also published asCN1748204A, CN1748204B, CN101281508A, US6826663, US7216187, US7313639, US7478181, US7921245, US8347047, US20040139253, US20040139288, US20050232020, US20070073926, US20080209141, US20100131725, US20110276733Publication number116439, 12116439, US 7925808 B2, US 7925808B2, US-B2-7925808, US7925808 B2, US7925808B2InventorsRichard E Perego, Frederick A WareOriginal AssigneeRambus Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (42), Non-Patent Citations (21), Classifications (12), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMemory system and device with serialized data transferUS 7925808 B2Abstract A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.
1. A method of operation within a memory device, comprising:
receiving a block of data values;
determining whether any of the data values represent a mask key; and
writing to memory those data values that do not represent a mask key.
2. The method of claim 1, wherein determining includes comparing the block of data values to at least one mask key that is predetermined and identifying masked data values as those data values that correspond to the at least one mask key that is predetermined.
the method further comprises receiving two copies of the block of data values in a two-phase operation; and
masked data values are adapted for detection based upon data mismatch between the two copies.
4. The method of claim 1, wherein determining whether any of the data values represent a mask key includes detecting from the data values one of a predetermined set of codes.
5. The method of claim 1, wherein determining whether any data values represent a mask key includes detecting a code that cannot correspond to a valid data value.
an interface that receives a block of data values; and
a circuit that identifies from the data values whether any data values in the block of data values denote a masking operation, and that responsively writes all data values to the storage array except those data values that denote a masking operation.
7. The memory device of claim 6, wherein the circuit is adapted to filter each data value to detect correspondence to one of a predetermined set of codes, and to responsively write the data value to the storage array when there is no correspondence.
8. The memory device of claim 7, wherein the circuit further includes a mask key table and a comparator, and wherein the circuit identifies whether any data values in the block of data values denote a masking operation by comparing each data value to each one of plural predetermined values in the mask key table to detect correspondence.
9. The memory device of claim 8, wherein the memory device is adapted to receive two copies of the block of data values as part of a two-phase operation, and to write to the storage array values that are identical across the two copies.
10. The memory device of claim 6, wherein the circuit is adapted to detect as a mask key any value in the block of data values that cannot correspond to a valid data value.
11. The memory device of claim 6, further comprising a mask key table, wherein the circuit is coupled to the mask key table to determine whether a predetermined mask key value identified in the mask key table is present in the block of data values.
an interface that receives a coded block of data values; and
logic that identifies any mask key values present in the coded block of data values, and that responsively writes all data values present in the coded block of data values to the storage array except those values that correspond to a mask key value.
13. The memory device of claim 12, wherein the logic is adapted to identify by analysis of the coded block of data values whether a mask key is present, to identify which data in the coded block of data values is to be masked, and to responsively update the storage array with all other data.
14. The memory device of claim 12, wherein the logic includes at least one predetermined mask key value and a comparator that compares the at least one predetermined mask key value with the coded block of data values to identify unmasked data.
15. In a memory device that includes an array of storage cells, and an interface adapted to receive a block of data values that are to be written to memory, an improvement comprising:
for each data value in the block of data values, detecting whether the data value corresponds to a code representing a mask key;
for each data value that does not correspond to a code representing a mask key, writing the data value into the array of storage cells; and
for each data value that does correspond to a code representing a mask key, not writing the data value into the array of storage cells, so as to not overwrite existing content of the array associated with a position of the data value within the block of data values. Description
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of Ser. No. 11/549,841 filed on Oct. 16, 2006, now pending, which is a continuation of U.S. patent application Ser. No. 10/385,908 filed Mar. 11, 2003, now U.S. Pat. No. 7,313,639, which application claims priority from U.S. Provisional Application No. 60/439,666 filed Jan. 13, 2003.
FIG. 2 illustrates a method of operation within a memory controller according to an embodiment of the invention. At 153, the memory controller receives a write data block 150 containing X write data values, WD0-WD(X−1), and a corresponding mask word 152 containing X mask values, M0−M(X−1), each mask value corresponding to a respective one of the write data values. The write data values may be any size (e.g., 8-bit, 16-bit, 32-bit, etc.) but, at least in the embodiment of FIG. 2, include a sufficient number of constituent bits to ensure that there are at least X possible bit patterns. That is, if the write data value size is N bits, then N is large enough to ensure that 2N≧X. This arrangement ensures that there is at least one pattern of N bits that will not match any of the X−1 possible bit patterns of the unmasked data values in a masked-write operation (i.e., because at least one of the X write data values in the write data block is masked). For the remainder of this description, the mask values are assumed to be single-bit values and are referred to as mask bits, though multi-bit mask values may alternatively be used.
FIG. 9 illustrates an embodiment of a key generator 350 that operates according to the alternative arrangement illustrated by operations 313-ALT and 323-ALT in FIG. 8. For purposes of illustration only, the key generator 350 is assumed to operate in a byte-masking memory controller that receives 64-byte write data blocks. Other mask granularities and block sizes may be used in alternative embodiments. Initially, the bytes of an incoming write data block are logically ANDed with the complements of their respective mask bits to generate a pool of mask-qualified bytes, BYTE00& M00, BYTE01& M01, . . . , BYTE63& M63. By this operation, each masked data value in the mask-qualified byte pool is forced to zero; an operation that corresponds to the masked byte removal operation 311 of FIG. 8. A summing circuit 351 is used to generate a 1's tally (i.e., sum of is) for bit 0 of each byte within the mask-qualified byte pool. Because at least one byte of the write data block is masked, the 1's tally generated by summing circuit 351 may range from 0 to 63 and therefore yields a 6-bit value, T0[5:0], in which the most significant bit, T0[5], if set, indicates that more than half the bytes in the mask-qualified byte pool have a 1 in the 0th bit position. Accordingly, bit zero of the mask key, MK[0], is set to the complement of T0[5] by the operation of inverter 353.
The circuitry for generating bit 1 of the mask key, MK[1], includes two summing circuits 3610 and 3611, and an elimination circuit 360. The elimination circuit includes 64 bitwise elimination circuits, E0, each of which corresponds to a respective mask-qualified byte and generates two signals that correspond to the two possible elimination results according to the state of the 0th bit of the mask key, MK[0]. For example, if MK[0] is 0, then all bytes of the mask-qualified byte pool for which bit 0 (b0) is 1 are to be eliminated, and if MK[0]=1, then all bytes for which b0=0 are to be eliminated. Accordingly, each of the bitwise elimination circuits, E0, generates a first qualified bit 1 (qb1 0) which is forced to 0 if b0=1, and set according to b1 if b0=0; and a second qualified bit 1 (qb1 1) which is forced to if b0=0, and equal to b1 if b0=1. In Boolean notation (�&� indicating a bitwise AND operation):
qb10 =b1&/b0; andqb11=b1&b0.
qb20 =b2&/b1&/b0;qb21=b2&b1&b0;qb22=b2&b1&b0; andqb23=b2&b1&b0.
Summing circuit 3710 sums the qb20 values for each byte in the mask-qualified byte pool to generate a 1's tally, T2 0[3:0] that corresponds to the elimination result when MK[1:0]=00, and summing circuits 371 1-371 3 similarly generate three separate 1's tallies, T2 1[3:0]-T2 3[3:0], that correspond to the elimination result when MK[1:0] is 01, 10, and 11, respectively. Because of the eliminations performed in elimination circuit 370, the 1's tally that corresponds to the actual state of MK[1:0] ranges from 0 to 15 and therefore yields a 4 bit value in which the most significant bit is set if more than half the 15 possible non-eliminated bytes in the mask-qualified byte pool have a 1 in the bit 2 position. The most significant bits (MSBs) of the four tally values, T2 0[3]-T2 3[3], are input to a multiplexer 372 which selects one of the four tally MSBs according to the MK[1:0] value. The selected tally MSB is then inverted by inverter 373 to form bit 2 of the mask key value, MK[2]. Thus, MK[2] is set to 0 if b2=1 for more than half the possible number of non-eliminated bytes in the mask-qualified byte pool, and MK[2] is set to 1 otherwise.
In the embodiment of FIG. 9, the circuitry for generating mask key bits MK[3], MK[4] and MK[5] is similar to the circuitry for generating MK[2], except that, at each stage, the number of summing circuits and the number of qualified bit values generated by the elimination circuit is doubled. Thus, the circuitry for generating MK[5] includes 32 summing circuits, 391 0-391 31, and the elimination circuit 390 includes 64 bitwise elimination circuits, E5, each of which generates 32 qualified bit values, qb50-qb531, that correspond to the 32 possible elimination results according to the 32 possible states of MK[4:0]. The summing circuits 391 0-391 31 generate 32 separate 1's tallies, T5 0[0]-T5 31[0], that correspond to the 32 possible elimination results (i.e., according to MK[4:0]). Because of the eliminations performed in elimination circuit 390, the 1's tally that corresponds to the actual state of MK[4:0] ranges from 0 to 1 and therefore yields a single-bit tally which is set to 1 if the single possible remaining byte in the mask-qualified byte pool has a 1 in the bit 5 position. The 32 tally bits, T5 0[0]-T2 32[0], are input to a multiplexer 392 which selects one of the 32 tally bits according to the MK[4:0] value. The selected tally bit is then inverted by inverter 393 to form bit 5 of the mask key value, MK[5]. Thus, MK[5] is set to 0 if b5=1 for the single possible remaining byte in the mask-qualified byte pool, and MK[5] is set to 1 otherwise. As discussed above, the mask key may be padded with 1s or 0s in any remaining bit positions (e.g., bit positions MK[6:7] in a byte-masking embodiment). Alternatively, the remaining bit positions may be left at arbitrary values.
FIG. 18 illustrates a two-phase masked-write operation applied to an exemplary write data block (WDB) and corresponding mask word (MSK). For purposes of example only, byte-mask granularity is assumed, and mask keys A and B are assumed to be hexadecimal values 55 (binary value 01010101) and AA (binary value 10101010), respectively. A mask conflict exists in the scenario shown because the write data block contains unmasked values that match both mask key A and mask key B (i.e., unmasked values of 55 and AA, respectively). Accordingly, mask key A is assigned to be the selected mask key for purposes of generating a coded data block, CDB-A, to be written in a first phase of a two-phase masked-write operation. As shown by the shaded �55� entries in coded data block CDB-A, mask key A is substituted for masked bytes within the write data block (i.e., 12, 70 and FF) to generate the coded data block, CDB-A. Also, as shown by the bold box 511 in coded data block CDB-A, the unmasked 55 value in the write data block, by happenstance, matches mask key A and therefore will be treated like a masked data value within the storage subsystem. FIG. 19 illustrates the content of the storage subsystem before and after each phase of the two-phase masked-write operation. For purposes of example, the storage area to which the masked-write operation is directed is assumed to contain zero-valued entries. Accordingly, after the first phase of the two-phase masked-write operation, all the storage locations are updated with write data bytes except for those locations for which the corresponding write data byte matches mask key A. Consequently, the storage location 515 which corresponds to the unmasked 55 value in the original write data block is not updated in the first phase of the two-phase masked-write operation, even though the intent of the host-requested write operation was to write the value 55 into storage location 515.
It should be noted that execution of a two-phase masked-write operation, though effective for resolving a mask conflict, has the undesirable characteristic of requiring two masked-write accesses to the storage subsystem instead of one. Consequently, the greater the frequency of two-phase masked-write operations, the lower the effective memory bandwidth of the memory system. One direct way to reduce the frequency of two-phase masked-write operations is to increase the number of predetermined mask keys from which the mask key is selected. As a statistical matter, assuming a set of R predetermined mask keys and a population of X write data values each having a unique pattern of N constituent bits, each additional mask key decreases the likelihood of a mask conflict by a factor of (X−R)/(2N−R). For example, in a system having a population of 64 write data values (one masked), byte-mask granularity, and two predetermined mask keys, the likelihood of a mask conflict in the population is (63/256)*(62/255)=�6%. If two additional predetermined mask keys are provided, the likelihood of a mask conflict is reduced to (63/256)*(62/255)* (61/254)*(60/253)=0.34%. Letting P represent the number of predetermined mask keys, the number of constituent bits required in the key selector is log2(P). In general, so long as log2(P) is smaller than the mask granularity, a bandwidth savings is achieved over a mask-key-transfer embodiment.
MD 0 ⁢ : QM ⁢ ⁢ 0 0 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 0 = MK ⁢ ⁢ 0 ) & / M ⁢ ⁢ 0 QM ⁢ ⁢ 0 1 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 0 = MK ⁢ ⁢ 1 ) & / M ⁢ ⁢ 0 QM ⁢ ⁢ 0 2 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 0 = MK ⁢ ⁢ 2 ) & / M ⁢ ⁢ 0 QM ⁢ ⁢ 0 3 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 0 = MK ⁢ ⁢ 3 ) & / M ⁢ ⁢ 0 MD 1 ⁢ : QM ⁢ ⁢ 1 0 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 1 = MK ⁢ ⁢ 0 ) & / M ⁢ ⁢ 1 QM ⁢ ⁢ 1 1 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 1 = MK ⁢ ⁢ 1 ) & / M ⁢ ⁢ 1 QM ⁢ ⁢ 1 2 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 1 = MK ⁢ ⁢ 2 ) & / M ⁢ ⁢ 1 QM ⁢ ⁢ 1 3 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 1 = MK ⁢ ⁢ 3 ) & / M ⁢ ⁢ 1 ⁢ ⋮ MD X - 1 ⁢ : QM ⁡ ( X - 1 ) 0 ⁢ : ⁢ ( WD ⁡ ( X - 1 ) = MK ⁢ ⁢ 0 ) & / M ⁡ ( X - 1 ) QM ⁡ ( X - 1 ) 1 ⁢ : ⁢ ( WD ⁡ ( X - 1 ) = MK ⁢ ⁢ 1 ) & / M ⁡ ( X - 1 ) QM ⁡ ( X - 1 ) 2 ⁢ : ⁢ ( WD ⁡ ( X - 1 ) = MK ⁢ ⁢ 2 ) & / M ⁡ ( X - 1 ) QM ⁡ ( X - 1 ) 3 ⁢ : ⁢ ( WD ⁡ ( X - 1 ) = MK ⁢ ⁢ 3 ) & / M ⁡ ( X - 1 ) Still referring to FIG. 22, the qualified signals QM0 0, QM1 0, . . . , QM(X−1)0 all correspond to mask key MK0 (each indicating whether MK0 matches a respective unmasked data value within the write data block), and are supplied to respective inverting inputs of AND logic gate 585 0. Thus, if all the qualified match signals corresponding to MK0 are low, the output of AND logic gate 585 0 (i.e., S0) will be high to indicate that MK0 does not match any unmasked data values within the write data block. Similarly, qualified match signals QM0 1, QM1 1, . . . QM(X−1)1 all correspond to MK1 and are supplied to inverting inputs of AND logic gate 585 1; qualified match signals QM0 2, QM1 2, . . . , QM(X−1)2 all correspond to MK2 and are supplied to inverting inputs of AND logic gate 585 2; and qualified match signals QM0 3, QM1 3, . . . , QM(X−1)3 all correspond to MK3 and are supplied to inverting inputs of AND logic gate 585 3. Thus each of the AND logic gates 585 0-585 3 will output a logic high signal if the corresponding mask key, MK0-MK3, does not match any unmasked data values within the write data block. The outputs of the AND logic gates 585 0-585 3 (i.e., signals S0-S3, respectively) are supplied to the encoder 587 where they are used to set the states of the key selector 552 and conflict signal 556. In one embodiment, the encoder 587 generates a key selector 552 that corresponds to the lowest numbered match key for which the output of the corresponding one of signals S0-S3 is high. That is, KSEL[1:0] is set to 00 to select MK0 if S0 is high; 01 to select MK1 if S0 is low and S1 is high; 10 to select MK2 if S0 is low, S1 is low and S2 is high; and 11 to select MK3 if S0 is low, S1 is low, S2 is low and S3 is high. If signals S0-S3 are all low, then none of the mask keys MK0-MK3 are unique relative to the write data block and a conflict condition exists. In the embodiment of FIG. 22, the encoder 587 asserts the conflict signal 556 to indicate the mask conflict condition, and sets the key selector 552 to select mask key MK0 to be the default mask key for a first phase of a two-phase masked-write. After the first phase of the two-phase masked-write, the encoder 557 sets the key selector to select mask key MK1 to be the default mask key for the second phase of the two-phase masked-write. Other key table selections may be used as the default mask keys for the first and/or second phases of the two-phase masked-write in alternative embodiments.
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