Source: http://www.google.com/patents/US8069102?dq=patent:7076806
Timestamp: 2017-08-19 14:26:56
Document Index: 119566914

Matched Legal Cases: ['Application No. 03729000', 'Application No. 03729000', 'Application No. 03729000', 'Application No. 03729000', 'Application No. 03729000', 'Application No. 03729000']

Patent US8069102 - Method and apparatus for processing financial information at hardware speeds ... - Google Patents
A method and apparatus use decision logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The decision logic can be configured to perform data reduction operations on the financial information stream. Examples of such data reductions operations...http://www.google.com/patents/US8069102?utm_source=gb-gplus-sharePatent US8069102 - Method and apparatus for processing financial information at hardware speeds using FPGA devices
Publication number US8069102 B2
Application number US 11/561,615
Also published as CA2486359A1, CA2486359C, EP1506501A2, US7139743, US20030018630, US20070078837, US20120116998, US20120130922, WO2003100662A2, WO2003100662A3
Publication number 11561615, 561615, US 8069102 B2, US 8069102B2, US-B2-8069102, US8069102 B2, US8069102B2
Inventors Ronald S. Indeck, Ron Kaplan Cytron, Mark Allen Franklin, Roger D. Chamberlain
Patent Citations (315), Non-Patent Citations (178), Referenced by (42), Classifications (14), Legal Events (3)
Method and apparatus for processing financial information at hardware speeds using FPGA devices
US 8069102 B2
wherein the executing step comprises the processor processing an inquiry to select one of the stored pre-compiled hardware templates for communication from the memory to the FPGA to thereby transform the FPGA to perform the data processing operation defined by the selected pre-compiled hardware template.
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International Classification G06Q40/00, G06F11/00, G06F17/30, G06F3/06
Cooperative Classification Y10S707/99931, Y10S707/99933, Y10S707/99936, G06Q40/00, G06Q40/06, G06F17/30477
European Classification G06F17/30S4P4, G06Q40/00, G06Q40/06
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:INDECK, RONALD S.;CYTRON, RON KAPLAN;FRANKLIN, MARK ALLEN;AND OTHERS;REEL/FRAME:018543/0169;SIGNING DATES FROM 20020712 TO 20020805
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:INDECK, RONALD S.;CYTRON, RON KAPLAN;FRANKLIN, MARK ALLEN;AND OTHERS;SIGNING DATES FROM 20020712 TO 20020805;REEL/FRAME:018543/0169