Source: http://www.google.com/patents/US6972964?dq=6,360,693
Timestamp: 2014-07-12 17:08:56
Document Index: 209859552

Matched Legal Cases: ['arts 16', 'arts 16', 'art 50', 'art 50', 'art 50', 'art 50']

Patent US6972964 - Module board having embedded chips and components and method of forming the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA module board has embedded chips and components. A substrate has at least one large cavity and at least one small cavity, in which the large cavity passes through the substrate and a passive component is set in the small cavity. A heat-dissipation sheet is set at the bottom of the substrate. A first...http://www.google.com/patents/US6972964?utm_source=gb-gplus-sharePatent US6972964 - Module board having embedded chips and components and method of forming the sameAdvanced Patent SearchPublication numberUS6972964 B2Publication typeGrantApplication numberUS 11/042,638Publication dateDec 6, 2005Filing dateJan 25, 2005Priority dateJun 27, 2002Fee statusPaidAlso published asUS20050122698Publication number042638, 11042638, US 6972964 B2, US 6972964B2, US-B2-6972964, US6972964 B2, US6972964B2InventorsKwun-Yao Ho, Moriss KungOriginal AssigneeVia Technologies Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (10), Referenced by (39), Classifications (32), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetModule board having embedded chips and components and method of forming the sameUS 6972964 B2Abstract A module board has embedded chips and components. A substrate has at least one large cavity and at least one small cavity, in which the large cavity passes through the substrate and a passive component is set in the small cavity. A heat-dissipation sheet is set at the bottom of the substrate. A first adhesion layer bonds the bottom of the substrate to the heat-dissipation sheet. At least one IC chip is fixed in the large cavity of the substrate by a second adhesion layer. A dielectric filling layer covers the entire surface of the module board and fills all gaps, in which the dielectric filling layer has a plurality of micro vias to expose partial areas of the IC chip, the passive component and the substrate. At least one wiring pattern layer is formed on the dielectric filling layer and provide electrical connection among the IC chip, the passive component, and the substrate.
a substrate having at least one large cavity and at least one small cavity, in which the large cavity passes through the substrate and at least one passive component is set in the small cavity;
a heat-dissipation sheet set at the bottom of the substrate;
a first adhesion layer which bonds the bottom of the substrate to the heat-dissipation sheet;
at least one IC chip fixed in the large cavity of the substrate by a second adhesion layer, wherein the IC chip comprises a plurality of metal pads formed on the surface of the IC chip, wherein a plurality of electrical-test metal parts formed on the metal pads, respectively;
a dielectric filling layer covering the entire surface of the substrate and filling all gaps at the surface of the substrate and in all of the cavities, wherein the dielectric filling layer has a plurality of micro vias to expose partial areas of the IC chip, the passive component and the substrate; and
at least one wiring pattern layer formed on the dielectric filling layer to make the IC chip, the passive component and the substrate electrically connect.
2. The module board having embedded chips and components according to claim 1, further comprising an adhesion layer which bonds the passive component in the small cavity.
3. The module board having embedded chips and components according to claim 1, further comprising a plurality of solder balls, pins, electrical connection pads, or opto-electronic connectors placed on the wiring pattern layer.
4. The module board having embedded chips and components according to claim 1, wherein the dielectric filling layer comprises a polymer and a dielectric material.
5. The module board having embedded chips and components according to claim 1, further comprising an electrical conduction part passing through the first adhesion layer to connect the substrate with the heat-dissipation sheet, wherein the heat-dissipation sheet is coupled to ground.
6. The module board having embedded chips and components according to claim 1, wherein the small cavity passes through the substrate and the passive component set in the small cavity is connected to the heat-dissipation sheet through an electrical conduction part in the first adhesion layer to couple to ground.
7. The module board having embedded chips and components according to claim 1, further comprising at least one passive component, set in the large cavity, adjacent to the IC chip, wherein the passive component set in the large cavity is connected to the heat-dissipation sheet through an electrical conduction part in the first adhesion layer to couple to ground.
8. The module board having embedded chips and components according to claim 1, further comprising an integrated passive component, set in the large cavity, adjacent to the IC chip, wherein the integrated passive component set in the large cavity is connected to the heat-dissipation sheet through an electrical conduction part in the first adhesion layer to couple to ground.
9. The module board having embedded chips and components according to claim 1, wherein the at least one IC chip is a plurality of IC chips fixed in the large cavity and disposed on the heat-dissipation sheet.
10. The module board having embedded chips and components according to claim 1, wherein the at least one IC chip is a plurality of IC chips fixed in the large cavity and stacked each other.
11. The module board having embedded chips and components according to claim 10, wherein the IC chips are electrically connected each other.
12. A method of forming a module board having embedded chips and components, comprising steps of:
providing a substrate having at least one large cavity and at least one small cavity, in which the large cavity passes through the substrate and a passive component is set in the small cavity;
providing a heat-dissipation sheet;
providing a first adhesion layer to bond the bottom of the substrate to the heat-dissipation sheet;
providing at least one IC chip, wherein the IC chip comprises a plurality of metal pads formed on the surface of the IC chip, wherein a plurality of electrical-test metal parts formed on the metal pads, respectively;
providing a second adhesion layer to bond the bottom of the IC chip to the large cavity of the substrate;
forming a dielectric filling layer to cover the entire surface of the substrate and fill all gaps at the surface of the substrate and in all of the cavities;
forming a plurality of micro vias in the dielectric filling layer to expose partial areas of the IC chip, the passive component and the substrate; and
forming at least one wiring pattern layer on the dielectric filling layer to provide electrical connection among the IC chip, the passive component and the substrate.
13. The method of forming a module board having embedded chips and components according to claim 12, wherein the passive component is fixed in the small cavity by an adhesion layer.
14. The method of forming a module board having embedded chips and components according to claim 12, further comprising a plurality of solder balls, pins, electrical connection pads, or opto-electronic connectors placed on the wiring pattern layer.
15. The method of forming a module board having embedded chips and components according to claim 12, wherein the step of forming the dielectric filling layer comprises:
proving a polymer to fill all gaps on the surface of the substrate and in all of the cavities; and
forming a dielectric material to cover the entire surface of the substrate.
16. The method of forming a module board having embedded chips and components according to claim 12, wherein at the step of forming the dielectric filling layer, a polymer and a dielectric material are provided at the same time to fill all gaps on the surface of the substrate and in all of the cavities and cover the entire surface of the substrate.
17. The method of forming a module board having embedded chips and components according to claim 12, wherein the first adhesion layer comprises an electrical conduction part therethrough to connect the substrate with the heat-dissipation sheet, and the heat-dissipation sheet is coupled to ground.
18. The method of forming a module board having embedded chips and components according to claim 12, wherein the small cavity passes through the substrate and the passive component set in the small cavity is connected to the heat-dissipation sheet through an electrical conduction part in the first adhesion layer to couple to ground.
19. The method of forming a module board having embedded chips and components according to claim 12, further comprising providing at least one passive component set in the large cavity, adjacent to the IC chip, wherein the passive component set in the large cavity is connected to the heat-dissipation sheet through an electrical conduction part in the first adhesion layer to couple to ground.
20. The method of forming a module board having embedded chips and components according to claim 12, further comprising providing an integrated passive component set in the large cavity, adjacent to the IC chip, wherein the integrated passive component set in the large cavity is connected to the heat-dissipation sheet through an electrical conduction part in the first adhesion layer to couple to ground.
21. The method of forming a module board having embedded chips and components according to claim 12, wherein the at least one IC chip is a plurality of IC chips fixed in the large cavity and disposed on the heat-dissipation sheet.
22. The method of forming a module board having embedded chips and components according to claim 12, wherein the at least one IC chip is a plurality of IC chips fixed in the large cavity and stacked each other.
23. The method of forming a module board having embedded chips and components according to claim 22, wherein the IC chips are electrically connected each other.
This application is a continuation-in-part of application Ser. No. 10/431,458 filed on May 8, 2003, now U.S. Pat. No. 6,865,089.
The present invention relates to a module board and a method of forming the same. More particularly, the present invention relates to an integrated module board, with a structure similar to a cavity-down plastic ball grid array (CD-PBGA) substrate or a substrate having various cavities, in which all kinds of chips and components are embedded or mounted onto the module board.
This process encounters the following problems. First, the packaging of IC chips, the assembly of passive components' surface mount technology (SMT) must proceed individually, resulting in a lengthy procedure, low yield, and high product costs. Second, since the assembly of passive components and the SMT cannot be integrated at the same packaging level, it is impossible to reduce the product to a desired thickness. Third, in order to achieve heat dissipation, a heat sink/fan and an electromagnetic interference (EMI) shielding sheet must be further provided on the main board to enhance the electrical performance, also causing increased costs. Fourth, since the IC chips, the passive components, and the heat-dissipation device cannot all be integrated on the same substrate during the same packaging level, the circuit route of the product layout is extremely long, interfering with electrical properties.
SUMMARY OF THE INVENTION The present invention provides an integrated module board, with structure similar to a cavity-down plastic ball grid array (CD-PBGA) substrate or a substrate having various cavities, constituting a substrate having cavities and a heat-dissipation sheet adhering to each other. Also, a plurality of passive components (or integrated passive module) and IC chips are formed in the cavities of the substrate. Moreover, a multi-layered interconnection process can directly proceed on the module board to provide electrical connection to other circuit boards in a cavity down manner.
A module board having embedded chips and components comprises a substrate having at least one large cavity and at least one small cavity, in which the large cavity passes through the substrate and a passive component is set in the small cavity. A heat-dissipation sheet is set at the bottom of the substrate. A first adhesion layer bonds the bottom of the substrate to the heat-dissipation sheet. At least one IC chip is fixed in the large cavity of the substrate by a second adhesion layer. A dielectric filling layer covers the entire surface of the module board and fills all gaps, in which the dielectric filling layer has a plurality of micro vias to expose partial areas of the IC chip, the passive component and the substrate. At least one wiring pattern is formed on the dielectric filling layer and electrically connects to the IC chip, the passive component (or integrated passive module) and the substrate.
FIGS. 10 to 16 are sectional diagrams of the module board according to embodiments of the invention.
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a module board, similar to a cavity-down plastic ball grid array (CD-PBGA) substrate or a substrate having various cavities, constituting a substrate having cavities and a heat-dissipation sheet adhering to each other. A plurality of passive components (or integrated passive module) and IC chips are formed in the cavities of the substrate. A multi-layered interconnection process can directly proceed on the module board to provide electrical connection to other circuit boards in a cavity down manner. In accordance with the number of the IC chips and variations in the packaging process, the module board may serve as a module component, a multi-chip module (MCM) substrate or a main board to be applied to every fabricating level in the electrical packaging technology.
As shown in FIG. 3, at least one IC chip 12 is provided with a plurality of metal pads 14, electrical-test metal parts 16 and alignment marks 17 formed on the surface. Then, using a second adhesion layer 18, the bottom of the IC chip 12 is bonded to the module board 30 within the large cavity 19, and the gap between the IC chip 12 and the module board 30 serves as a trench 34. Preferably, the thickness of the IC chip 12 is approximately equal to the height of the substrate 22 to benefit subsequent processes. The second adhesion film 18 may be conventional adhesive tape, epoxy-based prepreg tape, thermal conductive film, adhesive film having conductive particles, or metal conductive paste.
Next, a sealing process is performed to protect the IC chip 12 and passive components 24. As shown in FIG. 4, a dielectric filling layer 36 is deposited on the entire surface of the module board 30 to fill the trench 34 surrounding the IC chip 12 and other gaps surrounding the passive components 24. Preferably, the dielectric filling layer 36 comprises a polymer such as epoxy material and a dielectric material. In one case, the epoxy material flows into the trench 34 and gaps, and then the dielectric material is deposited on the entire surface of the module board 30. In another case, the epoxy material and the dielectric layer are provided on the entire surface of the module board 30 at the same time, such that the polymer such as epoxy material fills the trench 34 and gaps.
Next, a first interconnection process is performed to electrically connect the IC chip 12 and passive components 24 to the outside. As shown in FIG. 5, using laser drilling, plasma etching or photolithography, a plurality of micro vias 38 are formed in the dielectric filling layer 36 to expose the electrical-test metal parts 16, the metal pads 26 and passive components 24, respectively. Then, as shown in FIG. 6, using sputtering, vapor deposition, plating or printing, a first metal layer 40 is deposited on the entire surface of the module board 30 to fill the micro vias 38. Then, as shown in FIG. 7, using photolithography and etching or semi-additive process, the first metal layer 40 is patterned as a plurality of first metal wiring layers 40A.
Next, a second interconnection process is performed to electrically connect the IC chip 12 and passive components 24 to outside. As shown in FIG. 8, in accordance with the aforementioned interconnection process, a dielectric layer 42, a plurality of micro vias 43 and a second metal layer are successively formed on the first metal wiring layers 40A. Then, using photolithography and etching or semi-additive process, the second metal layer is patterned as a plurality of second metal wiring layers 44A electrically connected to the first metal wiring layers 40A through the micro vias 43.
As shown in FIG. 9, using printing or photolithography/etching, a mask layer 46 is formed on the entire surface of the module board 30 to expose predetermined positions of the second metal wiring layers 44A. After coating a solder mask material on the predetermined positions, a plurality of solder balls 48 are placed on the predetermined positions, respectively. Finally, using reflowing, the solder ball 48 is fixed in the predetermined position. Thus, the solder ball 48 can electrically connect to other circuit boards in a cavity down manner. If the integrated module board is a system or sub-system one, then there will be no necessity to place solder balls or pins. The module board can use electrical conduction pads or opto-electronical connectors.
Furthermore, in embodiments of the invention, the substrate 22 can be further connected to the heat-dissipation sheet 31 through an electrical conduction part 50 in the first adhesion layer 28, as shown in FIG. 10, wherein the heat-dissipation sheet 31 is coupled to ground GND.
Referring to FIG. 11, the small cavity also can pass through the substrate, leading the passive component 24 bonded to the heat-dissipation sheet 31 via the first adhesion layer 28. The passive component 24 can be further connected to the heat-dissipation sheet 31 through an electrical conduction part 50 in the first adhesion layer 28, wherein the heat-dissipation sheet 31 is coupled to ground GND.
In embodiments of the invention, the module board 30 can further comprise additional passive components 24′ set in the large cavity 19, and the additional passive components 24′ can be adjacent to the IC chip 12, as shown in FIG. 12. The additional passive components 24′ are bonded on the heat-dissipation sheet 31 by the second adhesion layer 18 and connected to the heat-dissipation sheet 31 through an electrical conduction part 50 in the second adhesion layer 18 to couple to ground GND.
In embodiments of the invention, the module board 30 can also comprise an integrated passive component (or module) 52 set in the large cavity 19, and the integrated passive component (or module) 52 can be deposed in the small cavity or be adjacent to the IC chip 12, as shown in FIG. 13. The integrated passive component (or module) 52 are bonded on the heat-dissipation sheet 31 by the second adhesion layer 18 and connected to the heat-dissipation sheet 31 through an electrical conduction part 50 in the second adhesion layer 18 to couple to ground GND.
In embodiments of the invention, the module board 30 can comprise at least two Ic chips 12, fixed in the large cavity 19 of the substrate 22 by the second adhesion layer 18. The IC chips 12 can be disposed on the heat-dissipation sheet 31, as shown in FIG. 14. Furthermore, the at least two IC chips can be also fixed in the large cavity and stacked with each other, as shown in FIG. 15. According to embodiments of the invention, the stacked IC chips can be electrically connected to each other, as shown in FIG. 16.
The multi-chip module can include light emitting die or opto-electronical die, and there is cavity or wave guide (or the both) formed over the lighting surface of that to guide the light transmission. The wave guide can be any designed pattern built in the substrate and connected to the surface or other opto-electronical die.
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ClassificationH01L24/82, H01L24/24, H01L23/538V, H05K1/18C6Legal EventsDateCodeEventDescriptionMay 15, 2013FPAYFee paymentYear of fee payment: 8Jun 8, 2009FPAYFee paymentYear of fee payment: 4Jan 25, 2005ASAssignmentOwner name: VIA TECHNOLOGIES, INC., TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HO, KWUN-YAO;KUNG, MORISS;REEL/FRAME:016223/0497Effective date: 20050103RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google