Source: http://www.google.com/patents/US7745232?dq=6,243,373
Timestamp: 2017-09-22 05:18:01
Document Index: 138963017

Matched Legal Cases: ['Application No. 02', 'application No. 2001', 'application No. 2001', 'Application No. 2007', 'application No. 10', 'application No. 10', 'application No. 91105789']

Patent US7745232 - Semiconductor device and method of manufacturing the same - Google Patents
According to the present invention, contact plugs are formed by a CVD method without deteriorating the properties of the ferroelectric capacitor in a semiconductor device having a fine ferroelectric capacitor. Adhesive film is formed in a contact hole, which exposes an upper electrode of the ferroelectric...http://www.google.com/patents/US7745232?utm_source=gb-gplus-sharePatent US7745232 - Semiconductor device and method of manufacturing the same
Publication number US7745232 B2
Application number US 12/285,748
Also published as EP1313141A2, EP1313141A3, EP1313141B1, US7456454, US20030089954, US20090068764
Publication number 12285748, 285748, US 7745232 B2, US 7745232B2, US-B2-7745232, US7745232 B2, US7745232B2
Inventors Naoya Sashida
Patent Citations (71), Non-Patent Citations (9), Referenced by (7), Classifications (19), Legal Events (4)
US 7745232 B2
15. A method of manufacturing a semiconductor device as claimed in claim 14, wherein said step of removing said conductive nitride film is performed by dry etching using a conductive pattern formed on said conductive nitride film as a self-aligned mask.
A ferroelectric capacitor having a consecutively layered structure is formed on the planarized surface of the interlayer insulation film 26, wherein this structure includes a lower electrode 27 in which a Ti film with a thickness of between 10 to 30 nm, preferably about 20 nm and a Pt film with a thickness of between 100 to 300 nm, preferably about 175 nm are consecutively layered; a ferroelectric capacitor insulation film 28 consisting of PZT(Pb(Zr,Ti)O3) or PZLT((Pb,La)(Zr,Ti)O3) with a thickness of between 100 to 300 nm, preferably about 240 nm; and an upper electrode 29 consisting of IrOx with a thickness of between 100 to 300 nm, preferably about 200 nm and formed on the ferroelectric capacitor insulation film 28. The Ti film and Pt film are formed typically by sputtering, and the ferroelectric capacitor insulation film 28 is crystallized typically by conducting rapid heat treatment for 20 seconds at 725° C. in an oxidizing atmosphere after sputtering. Preferably, ferroelectric film 28 is added with Ca and Sr, and can be formed by methods other than sputtering such as the spin-on method, sol-gel method, metal organic deposition (MOD) method or MOCVD method. It is also possible to use other films such as SBT(SrBi2(Ta,Nb)2O9) film, or BTO(Bi4Ti2O12) film for ferroelectric capacitor insulation film 28 instead of PZT or PLZT film. Furthermore, it is possible to form DRAM by using high dielectric film such as BST ((Ba,Sr)TiO3) film or STO(SrTiO3) film instead of ferroelectric capacitor insulation film 28. IrOx film constituting the upper electrode 29 is then formed typically by sputtering. It is still possible to use Pt film or SRO (SrRuO3) film for the upper electrode 29 instead of IrOx film.
Referring to FIG. 3A, SiO2 interlayer insulation film 26 is formed with a thickness of about 1 μm on a Si substrate 21, which is formed with diffusion regions 21 a through 21 d and having polycide gate electrodes 24A, 24B, by plasma CVD method using TEOS as the precursor so as to cover the gate electrodes 24A, 24B. The interlayer insulation film 26 is planarized by CMP method. Ti film and Pt film with a thickness of 20 nm and 175 nm respectively are consecutively deposited, and as previously mentioned, ferroelectric film with a thickness of 240 nm added preferably with Ca and Sr is formed thereon by sputtering. The PLZT film formed in this way is crystallized by conducting rapid heat treatment for 20 seconds at 725° C. with a temperature rise of 125° C./sec. in an oxidizing atmosphere.
IrOx formed in this way is patterned by a resist process, and the upper electrode 29 is formed. After the resist process, the ferroelectric film is subjected to heat treatment for 60 minutes at 650° C. in the oxidizing atmosphere again, and defects produced in the ferroelectric film during the sputtering stage and the patterning stage of IrOx film are compensated for.
Furthermore, encapsulating layer 330A for protecting ferroelectric capacitor insulation film 28 from H2 is formed by sputtering Al2O3 film at ordinary temperature so as to cover the ferroelectric capacitor insulation film 28 and the upper electrode 29. It is also possible to deposit PZT film, PLZT film or TiOx film instead of Al2O3 film for the encapsulating layer film 330A. After encapsulating layer 330A is formed, heat treatment is conducted for 60 minutes at 550° C. in an oxidizing atmosphere enhancing the film property of strong encapsulating layer 330A.
The resist pattern used during patterning of lower electrode 27 is removed, and the lower electrode is subjected to heat treatment for 30 minutes at 350° C. The encapsulating layer 330 is formed on the interlayer insulation layer 26 by sputtering Al2O3 in a manner so that encapsulating layer 330 covers the underlying encapsulating layer 330A.
In the step shown in FIG. 3A, after forming the encapsulating layer 330, heat treatment is conducted for 30 minutes at 650° C. in the oxidizing atmosphere, compensating for the damage caused in the ferroelectric capacitor insulation film 28. Furthermore, as previously described, interlayer insulation film 30 with a thickness of about 1200 nm is formed on the encapsulating layer 330 through a plasma CVD method using a polysilane compound such as SiH4, Si2F6, Si3F8 or Si2F3Cl, or SiF4 as precursors. It is also possible to form interlayer insulation film 30 using TEOS as the precursor. Moreover, the thermal excitation CVD method and laser excitation CVD method may be used besides plasma CVD method. After the interlayer insulation film 30 is formed, it is polished until the thickness measured from the surface of the upper electrode 29 amounts to about 400 nm, and then planarized.
In the step shown in FIG. 3B, the structure formed is subjected to heat treatment for 60 minutes at 550° C. in the oxidizing atmosphere, and the deterioration in quality of the insulation film 28 of ferroelectric capacitor that accompanies the formation of contact holes 30A and 30B is recovered.
In the step shown in FIG. 5E, contact holes 30C through 30F exposing diffusion regions 21 a through 21 d, respectively, are formed through the interlayer insulation film 30. In the step shown in FIG. 5F, Ti/TiN film 31 b consecutively layered with a Ti film with a thickness of 20 nm and a TiN film with a thickness of 50 nm is formed on the structure in FIG. 5E to a thickness of about 70 nm (=20+50 nm) by sputtering so as to cover the contact holes 30C through 30F as well as the TiN pattern 31 a.
In the step shown in FIG. 5G, W layer 32 is formed on the Ti/TiN layer 31 b by a CVD method to fill the contact holes 30A through 30F. In the step shown in FIG. 5H, W plugs 32A through 32F are formed in correspondence to contact holes 30A through 30F by removing W layer 32 on the interlayer insulation film 30 with a CMP method. Consequently, W plug 32A or 32B includes a consecutively layered layer system of TiN film, Ti film, TiN film and W film.
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U.S. Classification 438/3, 257/E21.664, 438/253
International Classification H01L27/115, H01L21/8239, H01L21/8246, H01L21/768, H01L27/105, H01L21/02
Cooperative Classification H01L21/7687, H01L27/11507, H01L27/11502, H01L28/55, H01L21/76877, H01L28/60
European Classification H01L21/768C4, H01L27/115C, H01L27/115C4, H01L21/768C3K