Source: http://www.google.es/patents/US7161218?hl=es&amp;dq=flatulence
Timestamp: 2017-11-23 02:08:39
Document Index: 114113670

Matched Legal Cases: ['§119', 'Application No. 60', 'art 3036', 'art 3000', 'art 3008', 'art 3000', 'art 3000', 'art 3000', 'art 3004', 'art 3008', 'art 3036', 'art 3000', 'art 3000']

Patente US7161218 - One-time programmable, non-volatile field effect devices and methods of ... - Google Patentes
One-time programmable, non-volatile field effect devices and methods of making same. Under one embodiment, a one-time-programmable, non-volatile field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. Each of the source, drain, and gate has...http://www.google.es/patents/US7161218?utm_source=gb-gplus-sharePatente US7161218 - One-time programmable, non-volatile field effect devices and methods of making same
Número de publicación US7161218 B2
Número de solicitud US 10/864,572
Fecha de presentación 9 Jun 2004
Fecha de prioridad 9 Jun 2003
También publicado como CA2528804A1, EP1634296A2, EP1634296A4, US6982903, US7112493, US7115901, US7211854, US7268044, US7280394, US7301802, US7569880, US7649769, US7928523, US8125039, US8699268, US20050056825, US20050056866, US20050062035, US20050062062, US20050062070, US20050063244, US20050074926, US20070020859, US20070108482, US20070121364, US20070296019, US20080225572, US20100025659, US20120181621, US20130134393, WO2005001899A2, WO2005001899A3
Número de publicación 10864572, 864572, US 7161218 B2, US 7161218B2, US-B2-7161218, US7161218 B2, US7161218B2
Inventores Claude L. Bertin, Thomas Rueckes, Brent M. Segal, Bernhard Vogeli, Darren K. Brock, Venkatachalam C. Jaiprakash
Citas de patentes (45), Otras citas (34), Citada por (52), Clasificaciones (85), Eventos legales (7)
One-time programmable, non-volatile field effect devices and methods of making same
US 7161218 B2
Imágenes(69)
1. A one-time-programmable, non-volatile field effect device, comprising:
an electromechanically-deflectable, nanotube switching element electrically coupled to one of the source, drain and gate and having an electromechanically-deflectable nanotube element that is positioned to be deflectable in response to electrical stimulation to form an electrically conductive path between the one of the source, drain and gate and its corresponding terminal and thus to form a non-volatile closed electrical state between the one of the source, drain and gate and its corresponding terminal.
This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 60/476,976, filed on Jun. 9, 2003, entitled Non-Volatile Electromechanical Field Effect Transistors and Methods of Forming Same, which is incorporated herein by reference in its entirety.
U.S. patent application Ser. No. 10/810,962, filed Mar. 26, 2004, entitled NRAM BIT SELECTABLE TWO-DEVICE NANOTUBE ARRAY;
U.S. patent application Ser. No. 10/810,963, filed Mar. 26, 2004, entitled NRAM BYTE/BLOCK RELEASED BIT SELECTABLE ONE-DEVICE NANOTUBE ARRAY;
U.S. patent application Ser. No. 10/811,191, filed Mar. 26, 2004, entitled SINGLE TRANSISTOR WITH INTEGRATED NANO TUBE (NT-FET); and
U.S. patent application Ser. No. 10/811,373, filed Mar. 26, 2004, entitled NANOTUBE-ON-GATE FET STRUCTURES AND APPLICATIONS.
An ASIC (Application Specific Integrated Circuit) chip is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. The use of ASICs can improve performance over general-purpose CPUs, because ASICs are “hardwired” to do a specific job and are not required to fetch and interpret stored instructions.
DRAM (dynamic random access memory) stores charge on capacitors but must be electrically refreshed every few milliseconds complicating system design by requiring separate circuitry to “refresh” the memory contents before the capacitors discharge. SRAM does not need to be refreshed and is fast relative to DRAM, but has lower density and is more expensive relative to DRAM. Both SRAM and DRAM are volatile, meaning that if power to the memory is interrupted the memory will lose the information stored in the memory cells.
Recently, memory devices have been proposed which use nanoscopic wires, such as single-walled carbon nanotubes, to form crossbar junctions to serve as memory cells. See WO 01/03208, Nanoscopic Wire-Based Devices, Arrays, and Methods of Their Manufacture; and Thomas Rueckes et al., “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing,” Science, vol. 289, pp. 94–97, 7 Jul., 2000. Electrical signals are written to one or both wires to cause them to physically attract or repel relative to one another. Each physical state (i.e., attracted or repelled wires) corresponds to an electrical state. Repelled wires are an open circuit junction. Attracted wires are a closed state forming a rectified junction. When electrical power is removed from the junction, the wires retain their physical (and thus electrical) state thereby forming a non-volatile memory cell.
Under one aspect of the invention, the nanotube resistance can be controlled by the deposition technique and tuned to between 10–10000 Ohms.
The present invention provides a radiation hard nonvolatile electromechanical switch that can be used in any transistor, and particularly in logic memory units, CMOS, ASIC, FPGAs etc. More specifically, the present invention provides for the integration of a nano-electro-mechanical two-state switch constructed of carbon nanotubes (CNTs) interfaced with a semiconductor field-effect transistor. The present invention can use an energy conserving mechanism—specifically, the van der Walls forces between a metal MOSFET electrode and CNT—to store and retain binary information in a conventional transistor circuit, without energy dissipation. It is contemplated that ionic bonding, covalent bonding, etc. may also by used in creating bistable states for the nanotube electromechanical field effect transistors (NEMFETs) and for the hybrid nanotube fabric-on-source or nanotube fabric-on-drain/nanotube programmable read only memories (NPROMs) of the present invention. This combination of features makes it possible to design reliable and stable, yet reversible and/or re-configurable, connections in transistor circuits. In the present invention, an electromechanical switch is located at the gate, source or drain of a transistor. Whether the switch is in the bit ON or the bit OFF position will determine the conductivity of the transistor. Once the switch is biased “on” it remains in that state even upon the absence of applied voltage, therefore there is no need for periodic recharging, and i.e. it is non-volatile.
The present invention allows such ROM chips to store far more information in a non-volatile state, while preserving costs. Such a BIOS could conceivably store the entire “suspended” state of a computer operating system, including resident memory, allowing for an “instant-on” at power up.
The prior art has addressed the desire of “non-volatile” operation with the construction of semiconductor memories built upon floating gate or “flash” transistor circuits. These configurations rely upon the assembly of charge on an ungrounded (i.e. floating) piece of metal to represent the stored information. Specialized techniques are required to fabricate such devices. Moreover, their ability to retain a charge (i.e. memory state), is transient, although it may extend into the multi-year range. The total number of reconfigurations or rewrites of data are also finite in such devices, due to eventual degradation of the capacitor oxide upon which charge is assembled or depleted.
Field programmable gate arrays use SRAM cells (pass transistors) to program the interconnects between CLBs (configurable logic blocks). Specialized software is needed for this and is required every time the chip is operated. The use of NPROM/NEMFET interfaces to fashion programmable interconnects could allow such FPGA chips to run without this software. (See also Nanoaddressing patent application of Nantero Inc., U.S. Ser. Nos. 09/915,173 and 09/915,095.
The present invention extends the FPGA paradigm, allowing a single transistor-gate-array chip to be configured and re-configured, at will, for applications such as rapid prototyping and in-field real-time adaptive filtering. Furthermore, the present invention is compatible with the ASIC paradigm, in that the electromechanical switch described herein can be used in a “hard-wired” ASIC array.
The present invention differs from the electromechanical bi-stable device for digital information storage recited in U.S. Pat. No. 4,979,149 in that the present invention does not necessitate the use of a transient charge assembly to create a deflecting force for the electromechanical element, nor does it necessarily rely on stresses or tensions in the electromechanical element to maintain the configuration.
FIGS. 1A–C depict circuit diagrams for Non-volatile Electro-Mechanical Field Effect Transistors, NPROMs;
FIG. 35A is a schematic of the capacitance network and associated voltages for the write “1” mode of operation for an NT Transistor (NT switches from OFF to ON state);
FIG. 35B is a schematic of the capacitance network and associated voltages for the write “0” mode of operation for an NT Transistor (NT remains in the OFF state);
Referring conjointly to FIGS. 2A–B, junction 106 illustrates the memory cell or switch in a first physical and electrical state in which the nanotube ribbon 101 is separated from corresponding trace 104. Junction 105 illustrates the cell in a second physical and electrical state in which the nanotube ribbon 101 is deflected toward corresponding trace 104. In the first state, the junction is an open circuit which may be sensed as such on either the ribbon 101 or on the trace 104 when so addressed. In the second state, the junction is a rectified junction (e.g., Schottky or PN), which may be sensed as such on either the ribbon 101 or on the trace 104 when so addressed.
Under certain embodiments, the nanotube ribbon 101 may be held in position at the supports by friction. In other embodiments the ribbon 101 may be held by other means, such as by anchoring the ribbons to the supports 102 using any of a variety of techniques. This friction can be increased through the use of chemical interactions including covalent bonding through the use of carbon compounds such as pyrenes or other chemically reactive species. Evaporated or spin-coated material such as metals, semiconductors or insulators especially silicon, titanium, silicon oxide or polyimide could also be added to increase the pinning strength. The nanotube ribbons or individual nanotubes can also be pinned through the use wafer bonding to the surface. See R. J. Chen et al., “Noncovalent Sidewall Functionalization of Single-Walled Carbon Nanotubes for Protein Immobilization,” J. Am. Chem. Soc., 123, 2001, 3838–39 and Dai et al., Appl. Phys. Lett., 77, 2000, 3015–17 for exemplary techniques for pinning and coating nanotubes by metals. See also WO 01/03208 for techniques.
Under certain preferred embodiments as shown in FIGS. 2A–B, a nanotube ribbon 101 has a width of about 180 nm and is pinned to a support 102 preferably fabricated of silicon oxide, silicon nitride or appropriate insulating material. The local area of metallic or semiconducting trace 104 under ribbon 101 is positioned close to the supports 102 and preferably is no wider than the belt, e.g., 180 nm. The trace may be formed from an n-doped or p-doped silicon electrode or any other suitable conducting or semiconducting material. The relative separation 208 from the top of support 102 to the deflected position where nanotube ribbon 101 attaches to electrode 104 (see FIGS. 2A–B) should be approximately 5–50 nm. The magnitude of the separation 208 is designed to be compatible with electromechanical switching capabilities of the memory device. For this embodiment, the 5–50 nm separation is preferred (i.e. for certain embodiments utilizing ribbons 101 made from carbon nanotubes, but other separations may be preferable when using other materials). This magnitude arises from the interplay between strain energy and adhesion energy of the deflected nanotubes. These feature sizes are suggested in view of modern manufacturing techniques. Other embodiments may be made with much smaller (or larger) sizes to reflect the manufacturing equipment's capabilities.
A matted layer 312 of nanotubes is then created to form a non-woven fabric of preferably single-walled carbon nanotubes (SWNTs) to form a third intermediate structure 314. Nanofabrics may be created by chemical vapor deposition (CVD) or by applying prefabricated nanotubes onto a substrate, e.g. by spin coating a suspension of nanotubes onto a substrate, as described in applications: U.S. Pat. Nos. 6,574,130, 6,643,165, 6,706,402; and U.S. patent application Ser. Nos. 09/915,093, 10/033,323, 10/033,032, 10/128,117, 10/341,005, 10/341,055, 10/341,054, 10/341,130, 10/776,059, and 10/776,572, the contents of which are hereby incorporated by reference in their entireties. While SWCNTs are preferred, multi-walled CNTs may be used. For example, the second intermediate structure 310 may be placed into an oven and heated to a high temperature (for example, about 800–1200° C.) while gases containing a carbon source, hydrogen and inert gas, such as argon or nitrogen, are flowed over the upper surface. This environment facilitates the generation or growth of the matted layer or film 312 of single-walled carbon nanotubes. Layer 312 is primarily one nanotube thick and the various tubes adhere to one another via van der Waals forces. Occasionally, one nanotube grows over or rests upon the top of another nanotube, though this growth is relatively infrequent due to the tendencies of the material. Under some embodiments (not shown), the catalyst 308 may be patterned to assist in growing the nanotubes with specific densities either more or less dense as is desired. When conditions of catalyst composition and density, growth environment, and time are properly controlled, nanotubes can be made to evenly distribute over a given field that is primarily a monolayer of nanotubes. Proper growth requires control of parameters including but not limited to catalyst composition and concentration, functionalization of the underlying surface, spin coating parameters (length, nanotube suspension concentration and RPM), growth time, temperature and gas concentrations.
A silicon wafer 400 is provided with an oxide layer 402. The oxide layer is preferably a few nanometers in thickness but could be as much 1 μm. A silicon nitride (Si3N4) layer 404 is deposited on top of the oxide surface 402. The silicon nitride layer is preferably at least 30 nm thick. The silicon nitride layer 404 is then patterned and etched to generate one or more cavities 406 to form support structure 407. With modern techniques the cavity width may be about 180 nm wide or perhaps smaller. The remaining silicon nitride material defines the supports 102 (e.g., as rows, or perhaps columns). A covering 408 of metallic or semiconducting material is then deposited to fill the cavities 406. This material may be made from n- or p-doped silicon or other suitable material known in the art. The covering 408 for exemplary embodiments may be about 1 μm thick but may be as thin as 30 nm. The covering 408 is then processed, for example by self-flattening of thick silicon layers or by annealing, to produce a planar surface 306, discussed above, to form structure 411. In the case of self-flattening, reactive ion etching (RIE) with end-point detection (EPD) may be utilized until the upper surface 410 of the etched silicon nitride is reached. The structure 411 is then oxidized to form and define sacrificial layers 304 of SiO2 about 10–20 nm deep into planar surface 306. The unconverted, remaining portions of silicon form traces 104.
FIG. 6 shows another approach for forming an alternative first intermediate structure 302′. In this embodiment, a silicon substrate 600 is covered with a layer 602 of silicon nitride having a height 604 of at least 30 nm. The silicon nitride layer 602 is then patterned and etched to generate spacings 606 and to define supports 102. The etching process exposes a portion 608 of the surface of silicon substrate 600. The exposed silicon surface 608 is oxidized to generate a silicon dioxide (SiO2) layer 610 having a thickness of a few nm. These layers 610 eventually insulate traces 104 analogously to the way insulating layer 109 did for the above-described structures 302. Once the insulating layers 610 have been created, the traces 104 may be created in any of a variety of manner. FIG. 6 illustrates the processing steps of FIGS. 4–5 used to create such traces to illustrate this point.
FIG. 11 shows an approach for forming an alternative first intermediate structure 302′″. Under this approach a silicon substrate 1100 is layered with a thin film 1104 of Si3N4 as a starting structure. On top of the silicon nitride layer 1104, a trace is created, e.g. by depositing and patterning metallic contacts or semiconducting silicon. The patterning can be done by, e.g. RIE. The surfaces of traces 104 are oxidized to form the SiO2 layer 1106 which acts as an alternative form of sacrificial layer 304′, thereby forming intermediate structure 1107. Intermediate structure 1107 is overgrown with Si3N4 1108 and back etched to form a planar surface 306 and to form alternative first intermediate structure 302′″. As will be evident to those skilled in the art, under this approach, when the sacrificial layer is subsequently removed, traces 104 will be separated from supports 102. Other variations of this technique may be employed to create alternative transverse cross-sections of trace 104. For example, the traces 104 may be created to have a rounded top, or to have a triangular or trapezoidal cross section. In addition, the cross section may have other forms, such as a triangle with tapered sides. As was explained above, once a first intermediate structure is formed, e.g., 302, a matted nanotube layer 312 is provided over the planar surface 306 of intermediate structure 302. In preferred embodiments, the non-woven fabric layer 312 is applied by spin coating a suspension of nanotubes as described in U.S. patent application Ser. Nos. 10/341,005, 10/341,055, 10/341,054 and 10/341,130, all incorporated by reference in their entireties. In other embodiments of the present invention, nanofabric layer 312 is grown over the structure through the use of a catalyst 308 and through the control of a growth environment. Other embodiments may provide the matted nanotube layer 312 separately and apply it directly over structure 302. Though structure 302 under this approach preferably includes the sacrificial layer to provide a planar surface to receive the independently grown or spun fabric, the sacrificial layer may not be necessary under such an approach.
Because the nanofabric application/creation processes cause the underside of such nanotubes to be in contact with planar surface 306 of intermediate structure 302, they exhibit a “self-assembly” trait as is suggested by FIG. 12. In particular, individual nanotubes tend to adhere to the surface on which they are applied or grown whenever energetically favorable, such that they form substantially as a “monolayer.” Some nanotubes may grow over or become situated over another so the monolayer is not expected to be perfect. The individual nanotubes do not “weave” with one another but do adhere with one another as a consequence of van der Waals forces. FIG. 12 is a depiction of an actual nanotube non-woven fabric. Nanofabrics appropriate for use in the present invention may be more or less dense than that shown in FIG. 12. Because of the small feature sizes of nanotubes, even modern scanning electron microscopy cannot “photograph” an actual fabric without loss of precision; nanotubes have feature sizes as small as 1–2 nm which is below the precision of SEM. FIG. 12 for example, suggests the fabric's matted nature; not clear from the figure, however, is that the fabric may have small areas of discontinuity with no tubes present. Each tube typically has a diameter 1–2 nm (thus defining a fabric layer about 1–2 nm) but may have lengths of a few microns but may be as long as 200 microns. The tubes may curve and occasionally cross one another.
As explained above, once the matted nanotube layer 312 is provided over the surface 306, the layer 312 is patterned and etched to define ribbons 101 of nanotube fabric that cross the supports 102. (See applications: U.S. Pat. Nos. 6,574,130, 6,643,165, 6,706,402; and U.S. patent application Ser. Nos. 09/915,093, 10/033,323, 10/033,032, 10/128,117, 10/341,005, 10/341,055, 10/341,054, 10/341,130, 10/776,059, and 10/776,572 for patterning techniques.) The sacrificial layer is then removed (e.g., with acid) forming the array 322 described above in connection with FIG. 3. Because the matted layer of nanotubes 312 form a non-woven fabric that is not a contiguous film, etchants or other chemicals may diffuse between the individual nanotube “fibers” and more easily reach the underlying components, such as the sacrificial layer.
FIGS. 2–16 illustrate carbon nanotube structures that may be combined with FET devices as illustrated in FIGS. 1A, 1B, and 1C. For the device illustrated in FIG. 1B, the electromechanical nanotube integration results in a nanotube transistor, or in this case, a nanotube PROM (NPROM). While the FETs used in these illustrations are NMOS, PMOS devices may also be used. In operation, if activated, these carbon nanotube structures will switch from an OFF state (or open position) as fabricated, to an activated switched ON state (or closed position). The OFF and ON states are non-volatile, and once activated to the ON state, the carbon nanotube remains in the ON state. Memory arrays may be formed using the elements illustrated schematically in FIGS. 1A, 1B, and 1C, and are referred to as one-time programmable (OTP) memory arrays using carbon nanotube ribbons or filaments integrated with FET devices. Memory products using these array structures are referred to as nanotube electromechanically programmable read only memories (NPROMs). Since each bit may only be programmed once, they are referred to as OTP NPROMs. The OFF state may be assigned the logical value of “1” or “0”, and the ON state may be assigned the logical value of “0” or “1”. Carbon nanotube programming requires exceeding the threshold voltage between the nanotube (an electrical conductor), and a reference electrode. Typical nanotube threshold voltages (VNT TH) are in the range of 0.5 to 1.5 volts. Reading and programming voltages applied to the arrays are typically 1.8 volts or less, and memory arrays using nanotubes are scalable to less than 1 volt. These low-voltage, scalable nanotube devices enable the integration of these non-volatile nanotubes in industry standard, low voltage, single polysilicon CMOS semiconductor processes. “The International Technology Road Map for Semiconductors” (ITRS) 2002 Edition and 2002 updates, project product designs using a minimum (half-pitch) dimension of 130 nm and operating at an internal (core) voltage of 1.8 volts in 2002, a goal that has been achieved by the most advanced semiconductor manufacturers. The smallest OTP NPROM cell is 6 F2, or 0.1 um2 for present 130 um technology. The ITRS Road Map projects 100 nm semiconductor technologies operating at 1.2 volts in 2005. Corresponding OTP NPROM cell area is 0.06 um2. These OTP NPROMs may be electrically programmed (written) at nanosecond rates in a single pass. The carbon nanotube switching speed is on the order of 1 ns, so the programming (write) time is therefore determined by delays in the array. Such array write (programming) delays may range in the 25 to 100 ns range, depending on memory array size. These electromechanical carbon nanotube switches are virtually insensitive to the adverse effects of radiation. In addition to stand-alone OTP NPROM memory products, the compatibility of carbon nanotube technology with the dense, low voltage, single poly CMOS logic technology, facilitates the embedding of fast read and fast OTP write, low voltage, non-volatile memory cores in logic chips, such as used in system-on-a-chip (SOC) applications.
The low voltage, scalable, fast read and programming (write), radiation insensitive, single polysilicon gate CMOS logic-compatible OTP NPROM technology compares favorably with traditional OTP EPROMs (for a description of OTP EPROMs, see Sharma, A. K., “Semiconductor Memories, Technology, Testing, and Reliability”, IEEE Press, 1997, page 103) that require a dual polysilicon gate structure, high-voltage and high-current hot electron write-compatible semiconductor technology. Programming (write) time for hot electron transition to the floating gate to increase the threshold voltage (VTH) of the dual gate structure is in the 10 microsecond to 1 millisecond range. The requirements of the optimized specialized dual poly OTP EPROM technology is not compatible with the requirements of the low voltage CMOS logic technology, and does not support optimized embedded macros or cores in system-on-a chip applications.
FIGS. 17 and 18 illustrate steps for fabricating a first preferred embodiment of the invention; such steps are described in detail below. FIG. 19 and FIGS. 20A–F illustrate integrated carbon nanotube and CMOS semiconductor structures corresponding to FIGS. 17 and 18. FIG. 18′ illustrates steps for fabricating a second preferred embodiment of the invention; such steps are described in detail below. FIG. 19′ and FIGS. 20G–J illustrate integrated carbon nanotube and CMOS semiconductor structures corresponding to FIG. 18′. In general, a partially completed semiconductor structure is formed using known industry techniques, through at least the FET device definition level, so as to form a base layer on which to fabricate the carbon nanotube (CNT or NT) structure. The fabrication steps for the carbon nanotube structure are described. Known semiconductor processing continues until the pre-wiring level. In regard to the first preferred embodiment of the invention, reference is made to the flow charts of FIGS. 21 and 22 for showing fabrication steps, and the corresponding structures of FIGS. 23A–F, that illustrate gap formation in the NT device (switch) region of the integrated nanotube—semiconductor structure to enable operation of the NT switch. Insulation is then applied and planarized, via holes are etched as needed, and wiring is deposited and patterned as illustrated in FIGS. 23G, 23H 23H′, 23I, 23I′, 23J, 23K, and 23L. Semiconductor fabrication continues and ends with final passivation (not shown) using known industry techniques. In regard to the second preferred embodiment of the invention, reference is made to the flow chart of FIG. 21′ that has been added for illustrating the fabrication steps, and the corresponding structures of FIGS. 23F′, 23F″, 23F′″, and 23F″″, that illustrate a second preferred method of gap formation in the NT device (switch) region of the integrated nanotube—semiconductor structure to enable operation of the NT switch. Insulation is then applied and planarized, via holes are etched as needed, and wiring is deposited and patterned as illustrated in FIGS. 23G′, 23H″, and 23I″. Semiconductor fabrication continues and ends with final passivation (not shown) using known industry techniques.
The nanotube integration with semiconductor technology is described in terms of bulk silicon technology, including CMOS, BiCMOS or bipolar technologies. However, nanotube integration is also compatible with silicon-on-insulator (SOI) technology, and strained silicon combined with bulk or SOI silicon technology. Nanotube structures also scale with geometry and voltage and are compatible with more advance transistor structures such as non-planar double and triple gate transistors (See Geppert, L., “The Amazing Vanishing Transistor Act”, IEEE Spectrum, October 2002, pages 28 to 33; “Triple Gate Double Play”, IEEE Spectrum, November 2002, page 18) implemented with or without strained silicon. Nanotubes may also be integrated with non-silicon, or mixed silicon and non-silicon semiconductor technologies. Some examples of these are SiGe, or SiC technology; GaAs technology and GaAs-on-Silicon technology; GaAlAs technology and GaAlAs-on-Silicon technology; InP technology and InP-on-Silicon technology; or InGaAs technology and InGaAs-on-Silicon technology, and still others such as combined Si, Ge, GaAs, GaAlAs, HgTe, InP technology. These structures of the present invention are also compatible with any suitable Group III/Group V or Group II/Group VI semiconductor technology, or combinations of such technologies.
The semiconductor industry standard fabrication is the same for nanotube embodiment 1 and nanotube embodiment 2. FIG. 19 illustrates a cross section of intermediate structure 3107 of the semiconductor structure after completion of step 3002, including nanotube embodiment 1 formed after completion of the standard semiconductor fabrication steps. The cross section of the semiconductor cell region of intermediate structure 3107 consists of NMOS FET devices with N+ drain regions 3126, and N+ doped source regions 3124 in p-type monocrystalline silicon substrate 3128. NMOS FET polysilicon gates 3120 control the FET channel region fabricated in the conventional manner. Shared conductive stud 3118 contacts drain 3126 in contact region 3123. Contact studs 3122, one for each nanotube structure, physically and electrically connect NT electrode 3106 to FET source 3124 at contacting region 3121. The NT structure rests on (is supported by) the planar oxide region 3116. The NT structure consists of electrode 3106, the nanotube fabric layer (filament or ribbon) 3114 in contact with supports 3112 (contact region is not visible in this cross sectional view), a sacrificial layer 3108 above and below NT ribbon in the NT device or switch region. Film thicknesses are in the range of 100 to 200 nm, typical of 130 nm minimum dimension (half-period) semiconductor technology. nanotube fabric layer 3114 film thickness is on the order of 1–5 nm, nanotube fabric layer 3114 minimum dimension is typically 130 nm, nanotube fabric layer 3114 length in the NT device region (suspended length after removal of sacrificial layer 3108) is on the order of 100 to 150 nm, and the thickness of lower portion of sacrificial layer 3108A situated between nanotube fabric layer 3114 and electrode 3106 is typically in the range of 5 to 15 nm. The NMOS FET channel length can be on the order of 100 to 130 nm as defined by polysilicon gate 3120 and diffusions 3124 and 3126. The cross section incorporating all semiconductor structures between the bottom layer of p-substrate 3128 and the top layer of insulator 3116 forms the base 3102′ upon which the NT structure is fabricated. Base layer 3102′ having planar top surface 3104′.
FIG. 19′ illustrates a cross section of intermediate structure 3107′. Intermediate structure 3107′ is a semiconductor structure after completion of step 3002 including nanotube embodiment 2 formed after completion of the standard semiconductor fabrication steps. Intermediate structure 3107′ shows a semiconductor cell region consisting of NMOS FET devices with N+ drain regions 3126, and N+ doped source regions 3124 in p-type monocrystalline silicon substrate 3128. NMOS FET polysilicon gates 3120 control the FET channel region which can be fabricated in a conventional manner. Shared conductive stud 3118 contacts drain 3126 in contact region 3123. Contact studs 3122, one for each nanotube structure, physically and electrically connect NT electrode 3106 to FET source 3124 at contact region 3121. The NT structure rests on (is supported by) the planar oxide region 3116. The NT structure consists of electrode 3106, the nanotube fabric layer (filament or ribbon) 3114 in contact with supports 3112 (contact region is not visible in this cross sectional view), a sacrificial layer 3108A between NT ribbon and switch electrode 3106, a second sacrificial layer 3117; in the case of intermediate structure 3107′, sacrificial layer 3117 is a thin conductive layer, in some embodiments of the present invention, sacrificial layer may be constructed of insulator and in other embodiments, semiconductor. The material from which sacrificial layer 3117 is chosen depends up on the physical characteristics of the final product. Sacrificial layer 3117 is disposed between nanotube fabric layer 3114 and conductor 3119. Combined electrical conductors 3117 and 3119 form a low resistance local and a low resistance interconnect NT structure. Film thicknesses are in the range of 100 to 200 nm, typical of 130 nm minimum dimension (half-period) semiconductor technology. Nanotube fabric layer 3114 film thickness is on the order of 1–5 nm, nanotube fabric layer 3114 minimum dimension is typically 130 nm. Nanotube fabric layer 3114 length in the NT device (switch) region (suspended length after removal of portions of the sacrificial layers) formed later in the process, and is on the order of 25 to 75 nm (sub-minimum lithographic dimensions), and the thickness of the portion of sacrificial layer 3108A between nanotube fabric layer 3114 and electrode 3106 is typically in the range of 5 to 15 nm. The NMOS FET channel length is on the order of 100 to 130 nm as defined by polysilicon gate 3120 and diffusions 3124 and 3126. The cross section incorporating all semiconductor structures between the bottom layer of p-substrate 3128 and the top layer of insulator 3116 forms the base 3102′ upon which the NT structure is fabricated. Base layer 3102′ having planar top surface 3104′. The second step according to FIG. 17 depends upon the desired composition of the final product. If a carbon nanotube structure (nanotube embodiment 1) is desired then the next step is 3004 (fabricate the carbon nanotube structure) if another nanotube structure (i.e. nanotube embodiment 2) is desired, then use step 3004′ (fabricate nanotube structure). The substeps of step 3004, (fabricate the carbon nanotube structure) are more fully described in the flow chart of FIG. 18. The substeps of step 3004′, (fabricate the nanotube structure) are more fully described in the flow chart of FIG. 18′.
The next step according to FIG. 17 is step 3006; fabricate the semiconductor structure to the pre-wiring level. Fabrication is continued using conventional semiconductor processing techniques to a pre-wiring level. The integrated carbon nanotube structure—semiconductor structure 3111, after completion of Step 3006, is illustrated in FIG. 23A. FIG. 23A shows structure 3111 much like structure 3107 in FIG. 19 which has been processed to include encapsulation over the nanotube structures in an insulator, structure 3111 having top surface 3116A.
FIG. 18 illustrates the substeps of step 3004 in flow chart form; the chart describes steps used to fabricate nanotube structure 3105, nanotube embodiment 1, on surface layer 3104, as illustrated in FIGS. 20A–F, where 3005A, 3005B, and 3005C are different views of nanotube structure 3105. Surface 3104 is the top surface of base 3102 that may contain a variety of structures with a variety of top surface layers. For example, the top surface layer 3104 may be a conductor, semiconductor, or insulating layer, or a combination of all three. (For example, intermediate structure 3107, shown in cross section in FIG. 19 contains a particular combination of materials and layers, with base region 3102′ corresponding to 3102, and top surface 3204′ corresponding to 3204.)
The first substep of step 3004 according to FIG. 18 is substep 3010; deposit conductor on partially fabricated semiconductor surface . . . . This first step describes the deposition of conductor layer 3103 on surface 3104, as shown in FIG. 20A. By way of example, conductor layer 3103 may be tungsten, aluminum, copper, gold, nickel, chrome, polysilicon, or combinations of conductors such as chrome-copper-gold. Conductor thickness may be in the range of 50 to 150 nm.
The next step according to FIG. 18 is substep 3022; form the carbon nanotube layer by spin-on technique or other appropriate technique as described in incorporated references: U.S. Pat. Nos. 6,574,130, 6,643,165, 6,706,402; and U.S. patent application Ser. Nos. 09/915,093, 10/033,323, 10/033,032, 10/128,117, 10/341,005, 10/341,055, 10/341,054, 10/341,130, 10/776,059, and 10/776,572, the contents of which are hereby incorporated by reference in their entireties. The carbon nanotube layer has a thickness of approximately 1–5 nm for devices using single-walled nanotubes and 5–20 nm and greater for devices using multiwalled nanotubes.
The next step according to FIG. 18 is substep 3028; deposit the sacrificial gap material layer over the carbon nanotube. One example is a layer of Si3N4, of thickness 5–50 nm depending upon the performance specifications required for the nanotube device.
Illustrations of the completed carbon nanotube structures for embodiment 1 are shown in FIGS. 20D–F. FIG. 20D shows plan view of intermediate structure 3105, FIG. 20E shows a cross section of intermediate structure 3105 taken at A–A′ as shown in FIG. 20D, and FIG. 20F shows a cross section of intermediate structure 3105 taken along the line of B–B′ as shown in FIG. 20D. The elements in FIGS. 20A–F correspond to elements of FIG. 3. For example, base 3102 corresponds to a combination of layers 110 and 109; planar surface 3104 corresponds to planar surface 316. Also, electrode 3106 corresponds to conductive trace 104, support 3112 corresponds to support structure 108, and the portion 3108A of sacrificial layer 3108 corresponds to sacrificial layer 304.
FIG. 18′ illustrates step 3004′ which describes substeps used to fabricate nanotube structure 3105′, nanotube embodiment 2, on surface 3104, illustrated in FIGS. 20A–C, and FIGS. 20G–J.
The next substep of step 3004′ is substep 3025; deposit a second sacrificial gap material layer 3117. One example is thin conductor layer of TiW, of approximate thickness 5–50 nm depending upon the performance specifications required for the nanotube device. Sacrificial gap material layer 3117 is illustrated in FIG. 20G.
The next substep of step 3004′ is substep 3031; etch to pattern conductive layer 3119, as illustrated in FIGS. 20I–J.
The next substep of step 3004′ is substep 3033; etch to pattern gap material layer 3117, as illustrated in FIG. 20I.
The next substep of step 3004′ is substep 3035; etch to pattern the carbon nanotube fabric layer 3114, illustrated in FIG. 20I, using appropriate methods and techniques as described in previous patent applications of Nantero, Inc.: U.S. Pat. Nos. 6,574,130, 6,643,165, 6,706,402; U.S. patent application Ser. Nos. 09/915,093, 10/033,323, 10/033,032, 10/128,117, 10/341,005, 10/341,055, 10/341,054, 10/341,130, 10/776,059, and 10/776,572, the contents of which are hereby incorporated by reference in their entireties.
Illustrations of the completed carbon nanotube structures for embodiment 2 are shown in FIGS. 20H–J. FIG. 20J shows a plan view of intermediate structure 3105′. FIG. 20I shows a cross sectional view of intermediate structure 3105′ taken at AA–AA′ as shown in FIG. 20J, and FIG. 20H shows a cross sectional view of intermediate structure 3105′ taken at BB–BB′ as shown in FIG. 20J. The elements in FIGS. 20A–C, and FIGS. 20G–J, correspond to elements of FIG. 3. For example, base 3102 corresponds to a combination of layers 110 and 109; planar surface 3104 corresponds to planar surface 316. Also, electrode 3106 corresponds to conductive trace 104, support 3112 corresponds to support structure 108, and the portion 3108A of sacrificial layer 3108 corresponds to sacrificial layer 304.
Next, perform substep 3036; embed sub-photolithographic images 3132 or 3134 in a sacrificial layer 3130 as illustrated in FIGS. 23D–F, all described in flow chart form in FIG. 22. The material for sacrificial layer 3130 is selected such that it is impervious to the etch chosen (RIE, for example) for SiO2 oxide 3116, and sacrificial layer 3108 nitride etch. Examples Al2O3, photoresist, polyimide, etc.
Flow Chart 3036, FIG. 22, illustrates steps to form the sub-lithographic images 3132 or 3134 in sacrificial layer 3130 used in etching insulating layer 3116 to form opening 3136 in the dielectric layer, SiO2 for example, reaching sacrificial layer 3108, as illustrated in FIGS. 23D,E, and F. The FIG. 23D, E, and F illustrations incorporate nanotube 3105, embodiment 1, however, nanotube 3105′, embodiment 2 may be substituted instead. Sub-lithographic image 3132 has two approximately orthogonal sub-lithographic dimensions W2 and W3 and may be used with nanotube embodiments 1 and 2. Sub-lithographic image 3134 has one sub-lithographic dimension W2 and may be used with nanotube embodiment 1.
FIG. 23F illustrates the embodiment 1 nanotube structure 3105 integrated in a semiconductor structure prior to etching to remove the sacrificial gap material and suspend the nanotube.
The next substep of substep 3008 is substep 3040; etch (remove) sacrificial gap material 3130 to form gaps 3108. The etch may be done by any appropriate method, e.g. by wet etch. This releases the electromechanical carbon nanotube structure in the NT switch region by creating separation or gap regions 3141A and 3141B. Gap 3141A between nanotube fabric layer 3114 and electrode 3106 is 13 nm. Gap 3141B between nanotube fabric layer 3114 and oxide 3116 is preferably between 5–50 nm but can be adjusted depending upon performance specifications desired. Such elements are illustrated in FIG. 23G, the released embodiment 1 nanotube structure 3105G. The released nanotube structure of embodiment 1 is referred to as 3105G, as distinguished from the unreleased embodiment 1 nanotube structure 3105.
FIG. 23I illustrates intermediate structure 3150 (a memory or storage cell) in plan view. The cross section shown in FIG. 23H is taken along bit line 3138 (AA′) of plan view in FIG. 23I. The storage (memory) cell shown in FIG. 23I includes word line 3120, bit line 3138, and nanotube fabric layer 3114. Vertical stud 3122 contacts source diffusion 3124 and electrode 3106 of NT structure 3105G, nanotube embodiment 1. Nanotube fabric layer 3114 and NT structure 3105G (nanofabric switch) overlay word line 3120 for greater cell density. Bit line 3138 contacts stud 3118 at contact 3140, and stud 3118 connects bit line 3138 to diffusion 3126, shared between two devices in adjacent cells. The cell layout pitch along the bit line requires 3 minimum features (3F), and the cell pitch along the word line requires 2 minimum features (2F), so the cell area is 6F2.
In embodiments of the present invention using high resistivity nanotube fabric, e.g. 10 to 100,000 Ohms per square, stitching electrodes may be used. In order to use the embodiment 1 nanotube structure 3105G for both a switching device and an array wire, as illustrated in FIGS. 23H and 23I, it is necessary to reduce the Ohms per square of the nanotube fabric. One approach to reduce such resistance is to use metal strapping of the nanotube layer. FIGS. 23H′ and 23I′ illustrates metal strapping line 3143 connected to nanotube fabric layer 3114 used in this instance as an array line in the region between memory cells by contact 3145. Metal strapping line 3143 may have a thickness in the range of approximately 100 to 200 nm. For a tungsten (W) strapping line, the sheet resistance is in the range of 0.15 to 0.60 Ohms per square, depending on line thickness and width. For an aluminum (Al) strapping line, the sheet resistance is in the range of 0.05 to 0.18 Ohms per square, depending on line thickness and width, (see Itoh, K., “VLSI Memory Chip Design”, Springer 2001, Table 2.3, page 61). In order to minimize the risk of shorting between strapping line 3143 and bit line 3138, bit line 3138 may be coated with a conformal insulating layer 3139, such as Si3N4, resistant to the SiO2 etch used to form the via hole for contact 3145.
FIGS. 23J–L show structures resulting from fabrication steps used to coat the top and sides of bit line 3138 with an insulator, Si3N4 for example, resistant to SiO2 process etch when forming via holes 3145 (shown in FIG. 23I′). FIG. 23J illustrates a portion of insulating layer 3116, supporting metal layer 3138′ and insulating layer 3139′
The first substep of step 3008′ is substep 3037; execute process steps 3034 and 3036 of step 3008, (see FIG. 21). These process steps result in combined nanotube and semiconductor structures illustrates in FIGS. 23A–F, except that nanotube embodiment 1 3105 is replaced with nanotube embodiment 2 3105′. FIG. 23F, showing nanotube embodiment 2 3105′ instead of nanotube embodiment 1 3105 is illustrated in FIG. 23F′, just prior to etching of the nanotube structure. FIG. 23D′ is the same as FIG. 23D, except that sub-lithographic mask layer opening 3132′ is selected to optimize the characteristics of nanotube structure 3105′. Hole 3136′ in the dielectric layer reaches conductor 3119 of nanotube embodiment 2 3105′. FIG. 20I illustrates a cross sectional view of nanotube embodiment 2 3105′ taken at AA–AA′ (see FIG. 20J).
FIGS. 20A–F, and associated fabrication steps, illustrate a nanotube embodiment 1 structure 3105 that integrates with semiconductor technology, independent of cell type or structure. Nanotube structure 3105 is formed on surface 3104 of base layer 3102, where base layer 3102 accommodates a wide variety of structures. In the specific example of the integration of nanotube structure 3105 into a cell structure, the preferred NT-on-Source cell has been illustrated in detail. In FIG. 19, base 3102 becomes base 3102′ corresponding to a partially processed NT-on-Source cross section with nanotube electrode 3106 and NPROM source 3124 electrically connected by stud 3122. FIGS. 23A–G, and FIGS. 23H, H′, I, I′ and FIGS. 23J–L, (along with associated fabrication steps) describe a process for the formation of the NT-on-Source cell. FIG. 23G illustrates released embodiment 1 nanotube structure 3105G. FIG. 23H illustrates the NT-on-Source cell cross section prior to passivation. FIG. 23H′ illustrates the NT-on-Source cell with nanotube fabric layer 3114 strapped with metal line 3143 for low resistance array wiring. FIG. 23I illustrates a plan view of the NT-on-Source cell layout corresponding to FIG. 23H. FIG. 23I′ illustrates a plan view of NT-on-Source cell layout corresponding to FIG. 23H′.
FIGS. 20A–C and FIGS. 20G–J, and associated fabrication steps, illustrate a nanotube embodiment 2 structure 3105′ that integrates with semiconductor technology, independent of cell type or structure. Nanotube structure 3105′ is formed on surface 3104 of base layer 3102, where base layer 3102 accommodates a wide variety of structures. In the specific example of the integration of nanotube structure 3105′ into a cell structure, the preferred NT-on-Source cell has been illustrated in detail. In FIG. 19′, base 3102 becomes base 3102′ corresponding to a partially processes NT-on-Source cross section, with nanotube electrode 3106 and NMOS FET source 3124 electrically connected by stud 3122. FIGS. 23D′, 23F′, 23F″, 23F′″, 23F″″ 23G′, and FIGS. 23H″, 23I″, and also associated fabrication steps describe a process for the formation of the NT-on-Source cell. FIG. 23G′ illustrates released embodiment 2 nanotube structure 3105GG. FIG. 23H″ illustrates the NT-on-Source cell cross section prior to passivation. FIG. 23I″ illustrates a top view of the NT-on-Source cell layout corresponding to FIG. 23H″.
After fabrication, all nanotubes in array 3250 are in the OFF or open position. The OTP memory allows for unlimited read operations, but only one write operation per bit location. For a write operation, transistor TS0 is activated by WL0, and the voltage Vw of BL0 is applied through transistor TS0 to select node SN0. If the applied voltage Vw between nodes SN0 and REF0 (ground) exceeds the nanotube threshold voltage VNT TH, the nanotube structure switches to the ON state or logic “1” state, that is, nanotube REF0 and source SN0 are electrically connected. The near-Ohmic connection between SN0 and REF0 represents the ON state. If the applied voltage VW is zero, the cell remains in the OFF or “0” state, with no electrical connection between SN0 and REF0.
For a read operation, BL0 is driven high and allowed to float. WL0 is driven to a high voltage and transistor TS0 turns on. BL0 is connected by the conductive channel of transistor TS0 to select node SN0. If cell 3254 is in the ON state, then there will a conductive path between SN0 and REF0 (ground), and the bit line voltage Vrd will decrease as the bit line is discharged through TS0, to SN0, to REF0 (ground). If, however, cell 3254 is in the OFF state, then the path from BL0 through the TS0 channel to SN0 will indicate high impedance (high megaOhm to terraOhm) to REF0 (ground) and bit line voltage Vrd will be unchanged. The sense amplifier/latch circuit (not shown) detects changes in BL0 voltage. If the voltage Vrd on BL0 has decreased, the latch is set to a logic “1” state. If the voltage Vrd is unchanged, then the latch is set to a logic “0” state. The read operation is nondestructive read out (NDRO) of the cell information. Also, if external power is lost, the information in the array is preserved (nonvolatile storage).
FIG. 26 illustrates the operational waveforms 3280 of memory system 3250, illustrated in FIG. 25, during read and write-once (OTP) operations. During the read operation, cell 3254 is selected by charging BL0 to a voltage Vrd=0.8 volts, for example, and driving WL0 high, 1.25 volts, for example. If the cell is in the OFF (logic “0”) state, Vrd is unchanged. If the cell is in the ON (logic “1”) state, then the voltage Vrd decreases. The difference in BL0 voltage Vrd between ON and OFF states is typically 200 mv. This difference is amplified and latched (circuit not shown).
All cells in OTP memory array 3250 are in the OFF or open position after fabrication. At the start of the write-once cycle, cell 3254 is in the OFF state. Cell 3254 is selected when BL0 is driven to voltage Vw, which is typically in the 0.8 to 1.5 volt range for writing a logical “1” state (cell transition from OFF to ON) and WL0 is driven to a high voltage, typically 1.8 volts. If BL0 voltage is zero when WL0 is driven to a high voltage, the cell remains in the OFF or logical “0” state. The NT threshold voltage is set in the range of 0.8<VNT TH<1.5 volts.
The NT-on-Source OTP NPROM memory system 3250′ illustrated in FIG. 25′ is a modification of NT-on-Source array memory system 3250 of FIG. 25, with the same memory cell array, but with a different read and write architecture. More specifically, unlike the memory system 3250, memory system 3250′ has no sense amplifier/latch sensing scheme. Each bit lines is connected through a pass device 3265 to a chip data bus 3267 that connects directly with I/O buffers 3269 that interface off-chip to receive and transmit data. I/O buffer 3269 includes a pre-driver circuit and a tri-state OCD for transmitting data off-chip in the conventional manner. I/O buffer 3269 also includes a receiver circuit and a tri-state driver to receive off-chip data in the conventional manner. There are N pass devices, labeled 1, 2, 3 . . . N. One terminal of pass device 3265 connects to each of the N bit lines, BL0 to BLN−1. The other terminal of pass device 3265 connects to the eight data lines (1–8) shared by the N bit lines. Each bit line is also connected through a resistor R, typically 100 to 10,000 Ohms for example, to the bit line voltage source VBL. VBL value varies depending on the operation performed. In write mode, VBL is set at Vw=1.5 volts, for example. In read mode, VBL is set at Vrd=0.8 volts, for example.
For the memory system 3250′ non-destructive read operation, WL0 is selected and N transistors, TS0 to TSN−1 are activated. If NT0 is in the ON state, then current flows from VBL, through resistor R, through the channel of transistor TS0, through NT0 to ground and the bit line voltage drops near zero. If NT0 is in the OFF state, then current cannot flow through NT0 to ground and the voltage remains in the high state. N bit lines BL0–BLN−1 are in a low or high voltage state depending on whether the corresponding nanotube NT0 to NT-N−1 is in the ON or OFF state. Bit line decoder/driver 3264 drives I/O select logic circuit 3273 which selects 8 of the N transfer devices. Each of the eight data bus lines 3267 are connected to one of the N bit lines, transmitting the eight selected bits from 8 bit lines to data bus 3267. The pre-driver circuit and tri-state OCD are used to transmit the high or low voltage off-chip for each of the eight I/O terminals. A sense amplifier/latch is not required.
FIG. 26′ illustrates the operational waveforms 3280′ of memory system 3250′ during read and write-once (OTP) operations. The write operation waveforms are the same as those of FIG. 26. During the non-destructive read-out read operation, transistor TS0 is selected by driving word line WL0 to a high voltage, 1.5 volts for example. If NT0 is in the ON state, bit line BL0 current flows from VBL, through resistor R, through the channel of transistor TS0, through NT0 to ground. For a bit line of 250 fF, as a non-limiting example and a resistance value of 10,000 ohms, as a non-limiting example (circuit element R, resistance as illustrated in FIG. 25′), for example, the bit line discharge time constant RC=2.5 ns. The bit line discharge time≈2.2 RC=5.5 ns as illustrated in FIG. 26′. If NT0 is OFF, the bit line remains at a high voltage.
A carbon nanotube-on-drain (NT-on-Drain) structure is fabricated using the processes outlined in the flow chart in FIG. 17 (flow chart 3000 and included substeps), the processes outlined in FIG. 18′ (step 3000′ and included substeps) the processes outlined in the flow chart in FIG. 21′ (flow chart 3008′ and associated substeps), and the processes outlined in the flow chart in FIG. 22, (step 3036 and associated substeps). The embodiment 2 carbon nanotube structure 3105′, illustrated in views 3105AA, 3105BB, and 3105CC of FIGS. 20H–J, is applied on surface 3104 of base 3102. FIG. 27A illustrates nanotube structure 3105GG, which is nanotube 3105′ after further processing to define nanotube suspended length and gap regions, applied to the surface 3104″ of base region 3102″, where base region 3102″ is a partially processed NT-on-Drain semiconductor structure and corresponds to 3102 for FIGS. 20H–J. Base region 3102″ is the cross section incorporating all semiconductor structures between the bottom layer of p-substrate 3318 and the top layer of insulator 3116. The 3102″ partially processed structure is formed during step 3002 of flow chart 3000 when fabricating a NT-on-Drain cell structure.
FIG. 27A illustrates a cross sectional view of structure 3300 after completion of substep 3009 of flow chart 3000 (see FIG. 17); (final passivation layer is not shown). FIG. 27A illustrates a cross section of structure 3300, the semiconductor cell region consisting of NMOS FET devices with N+ drain regions 3314, and N+ doped shared source region 3316 in p-type monocrystalline silicon substrate 3318. NMOS FET polysilicon gates 3308 control the FET channel region fabricated in the conventional manner. Shared conductive stud 3310 contacts shared source 3316 and stitching conductor 3304. Stitching conductor 3304 and stud 3310 are optional, depending on the performance requirements of the array. Contact stud 3306, one for each nanotube structure 3105GG, physically and electrically connect NT electrode 3106 to FET drain 3314. The NT structure 3105GG rests on (is supported by) surface 3104″ of semiconductor base structure 3102″. The embodiment 2 nanotube fabric layer (filament or ribbon) 3114 and metal layers 3117 and 3119 form the array bit line 3302. The embodiment 2 nanotube switch region 3105GG is embedded and is a part of nanotube bit line 3302. Void region 3312 is the partially filled remnant of the vertical via used to create gaps 3141A′ and 3141B′ in NT structure 3105GG. Film thicknesses are in the range of 100 to 200 nm, typical of 130 nm minimum dimension (half-period) semiconductor technology. The NT bit line 3302 total film thickness is on the order of 100–200 nm, of which 1–5 nm is the thickness of the nanotube fabric layer 3114. The NT fabric layer 3114 suspended region length in the NT device region is on the order of 25 to 75 nm, and the switching region segment nanotube fabric layer 3114 of bit line 3302 is separated from the electrode 3106 by a gap 3141A in the range of 2.5 to 10 nm. The NMOS FET channel length is on the order of 100 to 130 nm as defined by polysilicon gate 3308 and diffusions 3314 and 3316. The cross sectional view of structure 3300 of FIG. 27A is taken along bit line 3302 (AA′) as illustrated in FIG. 27B.
FIG. 28A is a schematic of single NT-on-Drain cell 3350. Comparing cell schematic 3350 with structure 3330 illustrated in FIG. 27B, word line 3352 corresponds to 3308, NT bit line 3354 corresponds to 3302, drain connection 3358 connects the electrode of NT 3356 to drain 3360, where drain 3360 corresponds to drain 3314. Source 3362 corresponds to 3316, and is grounded. The switching region of nanotube wire 3354 is labeled NT 3356. The select transistor is labeled TS. NT is illustrated in FIGS. 20D–F as 3105, showing different views of nanotube structure 3105. FIG. 28A is a more detailed schematic representation of the FIG. 1A schematic.
After fabrication, all nanotubes in memory array system 3370 are in the OFF or open position. The OTP memory allows for unlimited read operations, but only one write operation per bit location. For a write operation, transistor TS0 is activated by WL0, and the voltage Vw of nanotube bit line BL0 is applied directly to NT0. If WL0 is high, then TS0 will connect drain node SN0 to ground. If the applied voltage Vw between nodes SN0 and nanotube BL0 exceeds the nanotube threshold voltage VNT TH, the nanotube structure switches to the ON state or logic “1” state, that is, the switching region of nanotube BL0 connects to select node SN0. The near-Ohmic connection between BL0 and SN0 represents the ON state. If the applied voltage VW is zero, the cell remains in the OFF or “0” state.
For a read operation, BL0 is driven high and allowed to float. WL0 is driven to a high voltage and transistor TS0 turns on. If NT0 is in the ON state, BL0 is connected by the nanotube switch to SN0. If conductive channel of transistor TS0 is activated, then SN0 is connected to ground through transistor ST0. If cell 3374 is in the ON state, then there will a conductive path between BL0 and ground, and the bit line voltage Vrd will decrease as the bit line is discharged through TS0, to ground. If, however, cell 3374 is in the OFF state, then BL0 is not connected to SN0, and the path from BL0 through the TS0 channel to ground will indicate a high impedance (high megaOhms to terraOhm) to ground, and bit line voltage Vrd will be unchanged. The sense amplifier/latch circuit (not shown) detects changes in BL0 voltage. If the voltage Vrd on BL0 has decreased, the latch is set to a logic “1” state. If the voltage Vrd is unchanged, then the latch is set to a logic “0” state. The read operation is nondestructive read out (NDRO) of the cell information. Also, if external power is lost, the information in the array is preserved (nonvolatile storage).
FIG. 30 illustrates the operational waveforms 3280 of memory array system 3370 illustrated in FIG. 29 during read and write-once (OTP) operations. During the read operation, cell 3374 is selected by charging BL0 to a voltage Vrd=0.8 volts, for example, and driving WL0 high, 1.25 volts, for example. If the cell is in the OFF (logic “0”) state, Vrd is unchanged. If the cell is in the ON (logic “1”) state, then the voltage Vrd decreases. The difference in BL0 voltage Vrd between ON and OFF states is typically 200 mv. This difference is amplified and latched (circuit not shown). Alternatively, the read operation may be performed without using a sense amplifier/latch scheme as described for memory array 3250′, FIG. 25′, and timing diagram 3280′, FIG. 26′. The capacitance network of FIG. 28B determines the fraction of the BL0 voltage that appears across NT0 of FIG. 29. If, for example, CNT=2 CDEP, then during read, the voltage applied to drain 3360 is 0.5 volts.
All cells in OTP memory array system 3370 are in the OFF or open position after fabrication. At the start of the write-once cycle, cell 3374 is in the OFF state. Cell 3374 is selected when BL0 is driven to voltage Vw, 1.5 volts for writing a logical “1” state (cell transition from OFF to ON), and WL0 is driven to a high voltage, typically 1.8 volts. If BL0 voltage is zero when WL0 is driven to a high voltage, the cell remains in the OFF or logical “0” state. The capacitance network illustrated in FIG. 28B determines the fraction of the BL0 voltage that appears across NT0 of FIG. 29. If, for example, CNT=2 CDEP, then during write, the 1.5 volts on BL0 is reduced to 1.0 volts across NT0, between the nanotube and the select electrode.
FIG. 31A is a schematic representation of FIG. 1B with the coupling capacitances added. Capacitance C12 is the NT switch capacitance between the control gate node 1 and node 2, the floating gate. Node 3 indicates the channel region of the transistor TR1. Node 4 is the drain, and node 5 is the source (connected to ground 6) of the transistor TR1. C23 is the capacitance between the polysilicon gate and the channel region 3 (gate oxide capacitance). C36 is the depletion capacitance between the channel 3 and substrate 6′. For the capacitance network, nodes 6 and 6′ are equivalent. When incorporating the schematic of FIG. 31A into a memory array, write disturb can occur. Accordingly, FIG. 31A is modified by adding a second series transistor TR2 between source node 5 and ground node 6 as illustrated in FIG. 31B. The source node 7 of transistor TR2 is connected to ground node 6. The drain node of TR2 and source node of TR1 are common node 5. Gate node 8 is used to select transistor TR2. When TR2 is turned off, sensitivity to bit disturb during write is eliminated. FIG. 31C is a redrawn schematic of FIG. 31B, with TR1 used as the storage node and transistor TR2 as the select transistor.
A carbon nanotube transistor structure is fabricated using process flow chart 3000 of FIG. 17, flow chart 3004′ of FIG. 18′, flow chart 3008′ of FIG. 21′, and flow chart 3036 of FIG. 22. The embodiment 2 carbon nanotube structure 3105′, illustrated in FIGS. 20H–J as structure 3105′, is applied on surface 3104 of base 3102. FIG. 32A illustrates nanotube structure 3105GG, which is nanotube 3105′ after further processing to define nanotube suspended length and gap regions, applied to the surface 3104′″ of base region 3102′″, where base region 3102′″ is a partially processed NT-on-Gate semiconductor structure. Base region 3102′″ is the cross section incorporating all semiconductor structures between the bottom layer of p-substrate 3420 and the top layer of insulator 3116. The 3102′″ partially processed structure is formed during step 3002 of flow chart 3000 when fabricating a NT-on-Gate cell structure. FIG. 32A illustrates intermediate structure 3410 in cross sectional view after completion of step 3009 of flow chart 3000 (final passivation layer is not shown). FIG. 32A illustrates a semiconductor cell region 3410 in cross sectional view, consisting of NMOS FET devices with N+ drain regions 3422, N+ channel continuity diffusion 3424, and N+ doped shared source region 3426 in p-type monocrystalline silicon substrate 3420. NMOS FET polysilicon gates 3414 and 3412 control the FET channel region fabricated in the conventional manner. Shared conductive stud 3428 contacts shared source 3426 and stitching conductor 3430. Stitching conductor 3430 and stud 3428 are optional, depending on the performance requirements of the array. Shared contact stud 3418 contacts shared drain diffusion 3422 and bit line 3416. Each nanotube structure 3105GG overlaps polysilicon gate 3414, physically and electrically connecting NT 3105GG electrode 3106 to FET gate 3414. The NT structure 3105GG rests on (is supported by) the surface 3104′″ of semiconductor base structure 3102′″. The embodiment 2 nanotube fabric layer (filament or ribbon) 3114 and metal layers 3117 and 3119 form the array word line 3415. The embodiment 2 NT switch region 3105GG is embedded as part of nanotube word line 3415. Film thicknesses are in the range of 100 to 200 nm, typical of 130 nm minimum dimension (half-period) semiconductor technology. The NT word line 3415 total film thickness is on the order of 100–200 nm, of which 1–5 nm is the thickness of the nanotube fabric layer 3114. The nanotube fabric layer 3114 suspended region length in the NT device region is on the order of 25 to 75 nm, and the switching region segment of nanotube fabric layer 3114 of word line 3415 is separated from the electrode 3106 by gap 3141A in the range of 2.5 to 10 nm. The NMOS FET channel length for the storage device is on the order of 100 to 130 nm as defined by polysilicon gate 3414 and diffusions 3422 and 3424. The NMOS FET channel length for the select device is on the order of 100 to 130 nm as defined by polysilicon gate 3412 and diffusions 3424 and 3426. Void region 3312 is the partially filled remnant of the vertical via used to create gap 3141A of NT structure 3105GG.
FIG. 32B shows a plan view of intermediate structure 3440. Note that FIG. 32A illustrates a cross sectional view of intermediate structure 3410, the cross section is taken along bit line 3416 (line A–A′) as shown in FIG. 32B.
FIG. 35A illustrates the capacitor network, relative capacitance values, and voltages for write “1”, NT switches from OFF to ON. FIG. 35B illustrates the capacitor network, relative capacitance values, and voltages for write “0”, with NT switch remaining in the OFF state. For nanotube fabric layer 3114 control gate voltage VCG=1.8 volts, if diffusion 3422 VD=0, then FG 3414 voltage VFG=0.4 V or 0.4 volts. The voltage between nanotube fabric layer 3114 and FG 3414 (electrically connected to electrode 3106), referred to as NT switching voltage VNT SEL=1.4 volts. If, however, diffusion 3422 voltage VD=0.5 to 1.5 volts, then the NT switching voltage VNT SEL=0.8 volts. Nanotube fabric layer 3114 switching threshold voltage is therefore selected as 0.8 volts<VNT TH<1.4 volts.
After fabrication, all nanofabric switches in array 3470 are in the OFF or open position. The OTP memory allows for unlimited read operations, but only one write operation per bit location. For a write operation, transistor TST0 is activated by WL0, and the voltage Vw of BL0 is applied to the drain of transistor TST0. Select transistor TSEL0 is off, isolating the node of transistor TST0. If the applied bit line voltage Vw=0, nanotube threshold voltage VNT TH is exceeded and the nanotube structure switches to the ON or logic “1” state, that is, nanotube WL0 electrically connects to the gate of transistor TST0. The near-Ohmic connection between WL0 and the gate of TST0 represents the ON state. If the applied voltage VW=0.5–1.5 volts, the cell remains in the OFF or “0” state. The switching mechanism for NT-on-Gate is as explained in FIGS. 34A, 34B, 35A, and 35B.
For a read operation, BL0 is driven high and allowed to float. Select transistor TSEL0 is turned on, WL0 is driven to a high voltage. If the NT0 is in the ON state, then WL0 is connected to the floating gate FG0 (not floating when connected), transistor TST0 turns on, BL0 is connected to ground through the FET channels of transistor TST0 and transistor TSEL0, and the bit line voltage Vrd will decrease as the bit line is discharged. If, however, cell 3476 is in the OFF state, then WL0 is not connected to floating gate FG0, the voltage coupled to the floating gate remains below the threshold voltage of FET device TST0, and BL0 is not discharged, and voltage Vrd is unchanged. The sense amplifier/latch circuit (not shown) detects changes in BL0 voltage. If the voltage Vrd on BL0 has decreased, the latch is set to a logic “1” state. If the voltage Vrd is unchanged, then the latch is set to a logic “0” state. The read operation is nondestructive read out (NDRO) of the cell information. Also, if external power is lost, the information in the array is preserved (nonvolatile storage).
FIGS. 38A–E illustrate the operation of the NT transistor 3800. FIG. 38A is a schematic of NT transistor 3800 with the nanotube in the ON position, as also illustrated in FIG. 35A. FIG. 38B is a more detailed schematic representation of NT transistor 3800 with the nanotube in the ON position. FIG. 38C is a schematic of NT transistor 3800 with the nanotube in the OFF position, as also illustrated in FIG. 35B. FIG. 38D is a more detailed schematic representation of NT transistor 3800 with nanotube in the OFF position. FIG. 38E illustrates the operation 3802 of Nanotube Transistor 3800 in both the ON and OFF position. NT transistor 3800 is in the OFF state as fabricated and can be changed once to the ON state. It can be read an unlimited number of times in the ON or OFF state. If NT transistor 3800 has the nanotube in the ON state (NT-ON), then the control gate CG is in physical and electrical contact with polysilicon gate 3804 which is therefore a non-floating gate (NON-FG). The nanotube control gate CG directly controls the FET channel region between the FET drain (D) and source (S) diffusions. The current flow from drain to source IDS as a function of control gate voltage VCG is illustrated by 3806, FIG. 38E. VCG=1.2 volts is applied directly across the gate oxide COX, illustrated as C23 in FIGS. 35A&B. If VCG=1.2 volts is applied, for example, then current flows between source and drain. Typical IDS current in is 10–25 microamperes, multiplied by the width to length ration (W/L) of the FET device, for example. If, however, NT transistor 3800 has the nanotube in the OFF state (NT-OFF), then the electrical characteristics 3808 of NT Transistor 3800 illustrate that no current IDS will flow between source and drain with control gate voltage VCG=1.2 volts. This is because VCG is now capacitively coupled to polysilicon gate 3804. This capacitance C12 is illustrated in FIGS. 35A&B. The capacitance of gate 3804 to channel region C23 is modulated by the state of the channel region. When the VCG voltage results in the FET device near threshold voltage Vth, the capacitance of gate 3804 is reduced to 0.25×COX (see Itoh, K. “VLSI Memory Chip Design”, Springer, 2001, page 58, FIG. 2.9a), or 0.25×C23, where C23 is defined in FIGS. 35A&B. VGS applied to the channel region at the onset of conduction is therefore ½ VGS. Therefore, if a nanotube in the OFF state, 0.5 VCG, or in this example 0.6 volts, is applied to the channel region, and the FET with a Vth=0.7 volts will not conduct. In a memory application, if a selected NT transistor 3800 is in the ON state, and has a voltage 1.2 volts applied to the control gate CG, it will conduct. If NT transistor 3800 is in the OFF state, it will not conduct with 1.2 volts applied to the control gate CG. If the transistor is unselected, then zero volts is applied and the NT transistor and will not conduct current in either ON of OFF state.
Transistor 3800 illustrated in FIGS. 38A–E is in the OFF state when fabricated. The nanotube transistor control gate may be programmed (written) once to the ON state. It may be read an indefinite number of times in either the ON state or the OFF state. It is desirable to enhance the function of transistor 3800 such that the control gate may be programmed (written) an indefinite number of times, while retaining the ability to read an indefinite number of times. This may be accomplished by introducing a release electrode that restores the nanotube from the ON state to the OFF state.
FIGS. 39A–D illustrate sequential cross sectional views of process steps for fabricating embodiment 3 nanotube structure 3900, with a release gate (node), creating a nanofabric that may be switched (written) from the OFF state to the ON state, and released from the ON state to the OFF state, for an unlimited number of times.
Embodiment 3 nanotube switch structure 3009 may be incorporated in transistor structure 4000, illustrated in FIGS. 40A–40E, creating a transistor that can be programmed (written) from OFF to ON, and released from ON to OFF and unlimited number of times. Instead of embedding structure 3900 in the transistor structure; structure 3900 may be used separately with a select transistor and an array release line to enhance memory system operation from an OTP function, to a read/program/write NRAM function by using structure 3900. An example is the NT-on-Source OTP memory array/system illustrated in FIGS. 23H″, 23I″, 25, and 25′ that may be changed to random access non-volatile nanotube random access memory (NRAM) 5000 illustrated schematically in FIG. 41. Memory system 5000 timing diagram 5500 illustrating the additional release-before-write feature is illustrated if FIG. 42.
FIG. 39A illustrates a modification of the structure illustrated in FIG. 20I. In FIG. 39A conductor 3902 is deposited directly on nanotube fabric layer 3114. Conductor 3902 may be aluminum or tungsten, for example, with a thickness in the range of 100–200 nm. If desirable, conductor 3902 may consist of at least two conductive layers, such as 3117 and 3119 as in FIG. 20I, however, for FIG. 39A conductive layer 3117 is not a second sacrificial gap layer. Sub-lithographic image 3904 is defined using fabrication methods similar to those used when etching conductor 3119, FIG. 23F″. Second sacrificial gap layer 3906 is conformally deposited as illustrated in FIG. 39B. Second sacrificial gap layer 3906 may be TiW, for example, of thickness 1.5 nm, for example. Conductor 3908 may then be deposited and planarized as illustrated in FIG. 39C. Second sacrificial gap layer 3906 may be etched (removed) creating gap region 3910 between conductors 3908 and 3902, and gap 3910′ between conductor 3902 and nanotube fabric layer 3114. Gap region 3910′ is of sub-minimum dimensions. The portion of first sacrificial gap layer 3108A just below gap region 3910′ is then etched forming gap region 3912. Nanotube fabric layer 3114 switch region 3914 is thus released, with a sub-lithographic minimum of 25 to 75 nm, for example, and a gap to switch electrode 3106 of 1.5 to 10 nm, for example, resulting in embodiment 3 nanotube structure 3900. The gap between nanotube switch region 3914 and release electrode 3908 may be 5 to 20 nm, for example.
FIGS. 40A–E illustrate nanotube transistor (NT Transistor) 4000. Transistor 4000 is similar to transistor 3800, except that release gate RG has been added to provide the nanotube release function ON to OFF to permit re-programming (re-writing) of transistor 4000 for an unlimited number of times. Polysilicon gate 4004 corresponds to polysilicon gate 3804 for transistor 3800. A typical release threshold voltage range is 1.5 to 2.5 volts, for example. The electrical characteristics 4002 of transistor 4000 are illustrated in FIG. 40E. The description of the electrical characteristics 4002 are the same as those for electrical characteristics 3802. NT Transistor 4000 ON state (NT-ON) characteristics 4006 and OFF state (NT-OFF) characteristics 4008 are illustrated in FIG. 40E. The read and write operation for NT Transistor 4000 are the same as for NT Transistor 3800. NT Transistor 4000 has the additional release operation to release transistor 4000 from the OFF to the ON state.
Memory subsystem schematic 5000, illustrated in FIG. 41, is similar to memory system 3250′ illustrated in FIG. 25′, with OTP embodiment 2 nanotube structure 3105GG replaced by read/release/write NRAM embodiment 3 nanotube structure 3900 and the addition of N memory array release lines RL0–RL N−1, as illustrated in FIG. 39D. The word decoder/word & reference line drivers 3271′ to select word lines using row (word) address bits has been modified to also select reference lines to prevent release lines from releasing nanotubes associated with unselected word lines. Bit line decoder/driver 3264′ decodes the column (bit or data) line address bits in the conventional manner. I/O select logic 3273 has been modified I/O and RL select logic to include selecting bit lines or release line transistors using the bit line decoder 3264′ output, and timing/control signals that identify the mode of operation and thus I/O select logic 3273′ is shown in FIG. 41. The outputs of I/O select logic 3273′ connect eight of the N bit lines to data bus 3267′ using transistors 3265 for read and write operations, or connect eight of the N release lines to corresponding release pulses using transistors 3265′ for the release operation. RL timing pulses are synchronized to chip other chip timing pulses by the timing/control input. I/O buffer 3269′ controls the data input and output of the NRAM memory subsystem. The memory system outlined in schematic 5000 is expected to use redundant bit and word lines (not shown) for yield enhancement purposes in the conventional manner (see Itoh, K., “VLSI Memory Chip Design”, Springer 2001, chapter 3, section 3.9, pages 178 to 183).
US3448302 16 Jun 1966 3 Jun 1969 Itt Operating circuit for phase change memory devices
US4044343 29 Abr 1976 23 Ago 1977 Tokyo Shibaura Electric Co., Ltd. Non-volatile random access memory system
US4845533 26 Nov 1986 4 Jul 1989 Energy Conversion Devices, Inc. Thin film electrical devices with amorphous carbon electrodes and method of making same
US4853893 2 Jul 1987 1 Ago 1989 Ramtron Corporation Data storage device and method of using a ferroelectric capacitance divider
US4876667 22 Jun 1987 24 Oct 1989 Energy Conversion Devices, Inc. Data storage device having a phase change memory medium reversible by direct overwrite
US4888630 21 Mar 1988 19 Dic 1989 Texas Instruments Incorporated Floating-gate transistor with a non-linear intergate dielectric
US5198994 8 Nov 1991 30 Mar 1993 Kabushiki Kaisha Toshiba Ferroelectric memory device
US5834818 29 May 1997 10 Nov 1998 International Business Machines Corporation Structure for making sub-lithographic images by the intersection of two spacers
US5920101 1 Sep 1998 6 Jul 1999 International Business Machines Corporation Structure for making sub-lithographic images by the intersection of two spacers
US6044008 18 Jun 1998 28 Mar 2000 Hyundai Electronics Industries Co., Ltd. Ferroelectric RAM device
US6048740 5 Nov 1998 11 Abr 2000 Sharp Laboratories Of America, Inc. Ferroelectric nonvolatile transistor and method of making same
US6159620 31 Mar 1998 12 Dic 2000 The Regents Of The University Of California Single-electron solid state electronic device
US6198655 10 Dic 1999 6 Mar 2001 The Regents Of The University Of California Electrically addressable volatile non-volatile molecular-based switching devices
US6430511 20 Ene 2000 6 Ago 2002 University Of South Carolina Molecular computer
US6459095 29 Mar 1999 1 Oct 2002 Hewlett-Packard Company Chemically synthesized and assembled electronics devices
US6462977 9 May 2001 8 Oct 2002 David Earl Butz Data storage device having virtual columns and addressing layers
US6518156 25 Abr 2000 11 Feb 2003 Hewlett-Packard Company Configurable nanoscale crossbar electronic circuits made by electrochemical reaction
US6548841 7 Jun 2002 15 Abr 2003 Texas Instruments Incorporated Nanomechanical switches and circuits
US6559468 26 Oct 2000 6 May 2003 Hewlett-Packard Development Company Lp Molecular wire transistor (MWT)
US6707098 15 Jun 2001 16 Mar 2004 Infineon Technologies, Ag Electronic device and method for fabricating an electronic device
US6803840 1 Abr 2002 12 Oct 2004 California Institute Of Technology Pattern-aligned carbon nanotube growth and tunable resonator apparatus
US6809465 24 Ene 2003 26 Oct 2004 Samsung Electronics Co., Ltd. Article comprising MEMS-based two-dimensional e-beam sources and method for making the same
US6982903 * 9 Jun 2004 3 Ene 2006 Nantero, Inc. Field effect devices having a source controlled via a nanotube switching element
US20020130353 24 Oct 2001 19 Sep 2002 Lieber Charles M. Nanoscopic wire-based devices, arrays, and methods of their manufacture
US20030021141 25 Jul 2001 30 Ene 2003 Segal Brent M. Hybrid circuit having nanotube electromechanical memory
US20030021966 25 Jul 2001 30 Ene 2003 Segal Brent M. Electromechanical memory array using nanotube ribbons and method for making same
US20030124325 28 Dic 2001 3 Jul 2003 Thomas Rueckes Electromechanical three-trace junction devices
US20030165074 5 Mar 2003 4 Sep 2003 Nantero, Inc. Hybrid circuit having nanotube electromechanical memory
US20030170930 10 Feb 2003 11 Sep 2003 Samsung Electronics Co., Ltd. Memory device utilizing carbon nanotubes and method of fabricating the memory device
US20030199172 23 Abr 2002 23 Oct 2003 Thomas Rueckes Methods of nanotube films and articles
US20040027889 25 Feb 2003 12 Feb 2004 Stmicroelectronics S.R.L. Optically readable molecular memory obtained using carbon nanotubes, and method for storing information in said molecular memory
US20040043148 4 Sep 2002 4 Mar 2004 Industrial Technology Research Institute Method for fabricating carbon nanotube device
US20040085805 24 Oct 2003 6 May 2004 Nantero, Inc. Device selection circuitry constructed with nanotube technology
US20040095837 17 Nov 2003 20 May 2004 Choi Won-Bong Nonvolatile memory device utilizing a vertical nanotube
US20050041465 26 Mar 2004 24 Feb 2005 Nantero, Inc. Nram bit selectable two-device nanotube array
US20050041466 26 Mar 2004 24 Feb 2005 Nantero, Inc. Non-volatile RAM cell and array using nanotube switch position for information state
US20050047244 26 Mar 2004 3 Mar 2005 Nantero, Inc. Four terminal non-volatile transistor device
US20050056877 26 Mar 2004 17 Mar 2005 Nantero, Inc. Nanotube-on-gate fet structures and applications
US20050062035 9 Jun 2004 24 Mar 2005 Nantero, Inc. Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
1 Appenzeller J. et al., "Carbon Nanotube Electronics", IEEE Transactions on Nanotechnology, 2002. 1 (4) 184-189.
2 Appenzeller J. et al., "Field-Modulated Carrier Transport in Carbon Nanotube Transistors" Physical Review Letters, 2002. 89 (2) 126801-1-126801-6.
3 Appenzeller, J., et al., "A 10 nm MOSFET Concept", Microelectronic Engineering, 2001. 56, 213-219.
4 Appenzeller, J., et al., "Optimized contact configuration for the study of transport phenomena in ropes of single-wall carbon nanotubes", Applied Physics Letters, 2001. 78 (21) 3313-3315.
5 Avouris Ph., "Carbon nanotube electronics", Chemical Physics, 2002. 281, 429-445.
6 Avouris, Ph., "Molecular Electronics with Carbon Nanotubes", Accounts of Chemical Research, vol. 35 No. 12 2002.
7 Bachtold, A. et al., "Logic Circuits with Carbon Nanotube Transistors", Science, 2001. 294, 1317-1320.
8 Brehob, M. et al., "The Potential of Carbon-based Memory Systems", 1-5., Aug. 1999 pp. 110-114.
9 Choi, W.B. et al., "Carbon-Nanotube-Based Nonvolatile Memory with Oxide-Nitride-Oxide Film and Nanoscale Channel", Applied Physics Letters, 2003. 82 (2) 275-277.
10 Collins, P.G., "Current Saturation and Electrical Breakdown in Multiwalled Carbon Nanotubes", Physical Review Letters, 2001. 86 (14) 3128-3131.
11 Collins, P.G., "Nanotubes for Electronics", Scientific American, Dec. 2000. 62-69.
12 Collins, P.G., et al., "Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown", Science, 2001. 292, 706-709.
13 Cui, J.B. et al., "Carbon Nanotube Memory Devices of High Charge Storage Stability". Applied Physics Letters, 2002. 81 (17) 3260-3262.
14 Derycke, V., "Controlling Doping and Carrier Injection in Carbon NanotubeTransistors", Applied Physics Letters, 2002. 80 (15) 2773-2775.
15 Derycke, V., et al., "Carbon Nanotube Inter- and Intramolecular Logic Gates", Nano Letters, 2001. 1 (9) 453-456.
16 Fuhrer, M.S. et al., "High-Mobility Nanotube Transistor Memory", Nano Letters, 2002. 2 (7) 755-759.
17 Heinze, S., "Carbon Nanotubes as Schottky Barrier Transistors" Physical Review Letters, 2002. 89 (10) 106801-1-106801-4.
18 Heinze, S., et al., "Electrostatic engineering of nanotube transistors for improved performance", Applied Physics Letters, 2003. 83 (24) 5038-5040.
19 Heinze, S., et al., "Unexpected Scaling of the Performance of Carbon Nanotube Transistors", published on the web Feb. 2003.
20 Javey, Ali et al., "Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and Ring Oscillators", Nano Letters, 2002. 2 (9) 929-932.
21 Kinaret, J.M. et al., "A carbon-nanotube-based nanorelay", Applied Physics Letters, 2003. 82 (8) 1287-1289.
22 Luyken, R.J. et al., "Concepts for hybrid CMOS-molecular non-volatile memories", Nanotechnology, 2003. 14, 273-276.
23 Martel, R. et al., "Ambipolar Electrical Transport in Semiconducting Single-Wall Carbon Nanotubes", Physical Review Letters, 2001. 87 (25) 256805-1-256805-4.
24 Martel, R. et al., "Carbon Nanotube Field-Effect Transistor and Logic Circuits", DAC, 2002. 7.4 94-98.
25 Martel, R., et al., "Single- and Multi-Wall Carbon Nanotube Field-Effect Transistors", Applied Physics Letters, 1998. 73 (17) 2447-2449.
26 Radosavljevic et al., "Drain Voltage Scaling in Carbon Nanotube Transistors", Applied Physics Letters, 2003. 83 (12) 2435-2437.
27 Radosavljevic et al., "High Performance of Potassium n-Doped Carbon Nanotube Field Effect Transistors", Applied Physics Letters, 2004. 84 (18) 3693-3695.
28 Radoslavljevic, M. et al., "Nonvolatile Molecular Memory Elements Based on Ambipolar Nanotube Field Effect Transistors", Nano Letters, 2002. 2 (7) 761-764.
29 Rochefort, A. et al., "Switching Behavior of Seminconducting Carbon Nanotubes Under an External Electric Field", Applied Physics Letters, 2001. 78 (17) 2521-2523.
30 Rueckes, T. et al., "Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing", Science, 2000. 289, 94-97.
31 Sapmaz, S. et al., "Carbon Nanotubes as Nanoelectromechanical Systems", Physical Review B, 2003. 67 23514-1-23514-7.
32 Wind, S.J. et al., "Lateral Scaling in Carbon-Nanotube Field-Effect Transistors", Physical Review Letters, 2003. 91 (5) 058301-1-058301-4.
33 Wind, S.J. et al., "Transistor Structures for the Study of Scaling in Carbon Nanotubes", J. Vac. Sci. Technol. B, 2003. 21 (6) 2856-2859.
34 Yoneya N. et al., "Charge transfer control by gate voltage in crossed nanotube junction", Applied Physics Letters, 2002. 81 (12) 2250-2252.
US7306990 * 28 Nov 2003 11 Dic 2007 Japan Science & Technology Agency Information storage element, manufacturing method thereof, and memory array
US7447056 * 31 Jul 2006 4 Nov 2008 Sandisk 3D Llc Method for using a multi-use memory cell and memory array
US7450414 31 Jul 2006 11 Nov 2008 Sandisk 3D Llc Method for using a mixed-use memory array
US7486537 31 Jul 2006 3 Feb 2009 Sandisk 3D Llc Method for using a mixed-use memory array with different data states
US7535016 * 31 Ene 2005 19 May 2009 International Business Machines Corporation Vertical carbon nanotube transistor integration
US7687841 * 2 Ago 2005 30 Mar 2010 Micron Technology, Inc. Scalable high performance carbon nanotube field effect transistor
US7701013 * 10 Jul 2007 20 Abr 2010 International Business Machines Corporation Nanoelectromechanical transistors and methods of forming same
US7709880 * 30 Abr 2007 4 May 2010 Nantero, Inc. Field effect devices having a gate controlled via a nanotube switching element
US7725858 * 27 Jun 2007 25 May 2010 Intel Corporation Providing a moat capacitance
US7903444 * 26 Jun 2008 8 Mar 2011 Chrong-Jung Lin One-time programmable memory and operating method thereof
US7943464 * 4 Sep 2009 17 May 2011 Nantero, Inc. Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
US8421060 * 8 Ene 2010 16 Abr 2013 Korea Institute Of Science And Technology Reconfigurable logic device using spin accumulation and diffusion
US8455305 * 6 Ago 2009 4 Jun 2013 Texas Instruments Incorporated Programmable circuit with carbon nanotube
US8553455 * 27 Sep 2006 8 Oct 2013 Cornell Research Foundation, Inc. Shape memory device
US8611129 * 30 Ene 2012 17 Dic 2013 Sony Corporation Semiconductor device and operation method thereof
US8699268 * 5 Oct 2007 15 Abr 2014 Nantero Inc. Field effect devices controlled via a nanotube switching element
US8797782 * 14 Feb 2012 5 Ago 2014 Sony Corporation Semiconductor device and operation method thereof
US9128669 22 Dic 2009 8 Sep 2015 Qualcomm Incorporated System and method of managing security between a portable computing device and a portable computing device docking station
US9152196 31 Ene 2013 6 Oct 2015 Qualcomm Incorporated System and method of managing power at a portable computing device and a portable computing device docking station
US9201593 22 Dic 2009 1 Dic 2015 Qualcomm Incorporated System and method of managing displays at a portable computing device and a portable computing device docking station
US9601498 23 May 2011 21 Mar 2017 Nantero Inc. Two-terminal nanotube devices and systems and methods of making same
US20060051920 * 28 Nov 2003 9 Mar 2006 Shinya Yamaguchi Information storage element, manufacturing method thereof, and memory array
US20060169972 * 31 Ene 2005 3 Ago 2006 International Business Machines Corporation Vertical carbon nanotube transistor integration
US20070029612 * 2 Ago 2005 8 Feb 2007 Micron Technology, Inc. Scalable high performance carbon nanotube field effect transistor
US20070069276 * 31 Jul 2006 29 Mar 2007 Scheuerlein Roy E Multi-use memory cell and memory array
US20070070690 * 31 Jul 2006 29 Mar 2007 Scheuerlein Roy E Method for using a multi-use memory cell and memory array
US20070086237 * 27 Sep 2006 19 Abr 2007 Sandip Tiwari Shape memory device
US20080025062 * 31 Jul 2006 31 Ene 2008 Scheuerlein Roy E Method for using a mixed-use memory array with different data states
US20080025069 * 31 Jul 2006 31 Ene 2008 Scheuerlein Roy E Mixed-use memory array with different data states
US20080025118 * 31 Jul 2006 31 Ene 2008 Scheuerlein Roy E Method for using a mixed-use memory array
US20080192014 * 8 Feb 2007 14 Ago 2008 Tyco Electronics Corporation Touch screen using carbon nanotube electrodes
US20080284463 * 17 May 2007 20 Nov 2008 Texas Instruments Incorporated programmable circuit having a carbon nanotube
US20090001512 * 27 Jun 2007 1 Ene 2009 Fern Nee Tan Providing a moat capacitance
US20090014803 * 10 Jul 2007 15 Ene 2009 International Business Machines Corporation Nanoelectromechanical transistors and methods of forming same
US20090315081 * 6 Ago 2009 24 Dic 2009 Texas Instruments Incorporated Programmable circuit with carbon nanotube
US20090323387 * 26 Jun 2008 31 Dic 2009 Art Talent Industrial Limited One-Time Programmable Memory and Operating Method Thereof
US20100075467 * 4 Sep 2009 25 Mar 2010 Bertin Claude L Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
US20100251361 * 22 Dic 2009 30 Sep 2010 Qualcomm Incorporated System and method of managing security between a portable computing device and a portable computing device docking station
US20110042648 * 8 Ene 2010 24 Feb 2011 Hyun Cheol Koo Reconfigurable logic device using spin accumulation and diffusion
US20110122123 * 28 Ene 2011 26 May 2011 Au Optronics Corporation Gate Driving Circuit of Liquid Crystal Display
US20120181621 * 5 Oct 2007 19 Jul 2012 Bertin Claude L Field effect devices controlled via a nanotube switching element
US20120212991 * 30 Ene 2012 23 Ago 2012 Sony Corporation Semiconductor device and operation method thereof
US20120212992 * 14 Feb 2012 23 Ago 2012 Sony Corporation Semiconductor device and operation method thereof
US20120282858 * 17 Jul 2012 8 Nov 2012 Qualcomm Incorporated System and Method of Providing Wireless Connectivity Between a Portable Computing Device and a Portable Computing Device Docking Station
US20120319729 * 8 Feb 2011 20 Dic 2012 Meinolf Blawat Field programmable gate array
WO2008144607A1 * 19 May 2008 27 Nov 2008 Texas Instruments Incorporated Programmable circuit having a carbon nanotube
Clasificación de EE.UU. 257/415, 257/E27.102, 977/742, 257/E21.666, 257/E27.103, 257/296, 257/E27.016
Clasificación internacional H01L27/115, H01L27/28, G11C23/00, H01L51/05, H01L29/76, G11C11/00, H01L21/82, H01L, H03K17/16, H01L29/745, G11C16/02, G11C7/06, H01L51/30, G11C8/02, H01L29/423, G11C11/50, H01L29/06, H01J1/62, H01H59/00, H01L21/336, H01L51/00, G11C16/04, H01L29/739, H01L21/8246, H01L29/96, G11C17/16, G11C13/02, H01L27/112
Clasificación cooperativa B82Y10/00, Y10S977/94, Y10S977/943, Y10S977/762, Y10S977/724, Y10S977/938, Y10S977/742, Y10S977/708, Y10S977/936, G11C16/0416, H01L51/0052, G11C17/165, H01L51/0508, H01L29/78, H01L27/11206, G11C2213/17, G11C7/065, H01L29/42324, G11C2213/16, G11C13/025, H01L27/112, B82Y99/00, H01H1/0094, H01L29/0673, G11C23/00, H01L27/115, H01L27/10, G11C17/16, H01L29/0665, H01L27/286, G11C2213/79, H01L51/0048, H01L27/1052
Clasificación europea B82Y10/00, H01L27/112P, H01L51/05B2, H01L29/06C6W2, H01L29/06C6, H01L29/423D2B2, H01L27/28G, G11C23/00, G11C7/06L, H01H1/00N, H01L27/115, H01L27/10, G11C17/16R, H01L21/8239, H01L27/112, G11C13/02N, G11C17/16
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