Source: https://patents.google.com/patent/US7608468B1/en
Timestamp: 2019-10-23 21:06:32
Document Index: 386117468

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

US7608468B1 - Apparatus and methods for determining overlay and uses of same - Google Patents
Apparatus and methods for determining overlay and uses of same Download PDF
US7608468B1
US7608468B1 US10/950,172 US95017204A US7608468B1 US 7608468 B1 US7608468 B1 US 7608468B1 US 95017204 A US95017204 A US 95017204A US 7608468 B1 US7608468 B1 US 7608468B1
US10/950,172
Michael E. Adel
Jorge Poplawski
2003-07-02 Priority to US48462703P priority Critical
2003-09-26 Priority to US50628103P priority
2004-02-20 Priority to US54654604P priority
2004-06-01 Priority to US10/858,836 priority patent/US7346878B1/en
2004-09-23 Application filed by KLA Tencor Technologies Corp filed Critical KLA Tencor Technologies Corp
2004-09-23 Priority to US10/950,172 priority patent/US7608468B1/en
2005-01-03 Assigned to KLA-TENCOR TECHNOLOGIES CORPORATION reassignment KLA-TENCOR TECHNOLOGIES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SELIGSON, JOEL L., ADEL, MICHAEL E., GHINOVKER, MARK, POPLAWSKI, JORGE
2009-10-27 Publication of US7608468B1 publication Critical patent/US7608468B1/en
101700060978 C7BL2 family Proteins 0 description 9
101700039334 C7BL3 family Proteins 0 description 9
230000004075 alteration Effects 0 claims description 14
238000001459 lithography Methods 0 claims description 58
238000000034 methods Methods 0 abstract claims description 135
This is a continuation-in-part of U.S. patent application Ser. No. 10/858,836, filed Jun. 1, 2004 now U.S. Pat. No. 7,346,878 by Avi Cohen, et al., which application claims priority of U.S. Provisional Application No. 60/484,627, filed Jul. 2, 2003 by Avi Cohen, et al., which applications are incorporated herein by reference in their entirety for all purposes.
This application also claims priority of U.S. Provisional Patent Application No. 60/506,281 filed 26 Sep. 2003 by Michael E. Adel, et al. and U.S. Provisional Patent Application No. 60/546,546 filed 20 Feb. 2004 by Michael E. Adel, et al. which applications are incorporated herein by reference in their entirety for all purposes.
FIG. 1 is a diagrammatic top view of a wafer 102 having a plurality of field areas 104 across which targets are distributed in accordance with one embodiment of the present invention. Each field generally corresponds to a field of a lithography tool which is used to pattern the various portions of the die and target structures as explained further below. Each field may include one or more die. As shown, field 104 a includes die 106 a through 1061. The die are separated by streets 108. For example, street 108 a separates a first row of die from a second row of die. Likewise, street 108 b separates the second row of die from a third row of die. Although only four fields are shown on a single wafer in the illustration of FIG. 1, of course, any suitable number of fields may be present on each wafer. Likewise, any suitable number of die may be present in a single field.
The IC designer then typically generates a layout pattern from the IC circuit design. The layout pattern may be composed of a plurality of electronic representations of IC layers that are later converted into a plurality of reticles that are used to fabricate a plurality of physical layers of an IC device and target. Each physical layer of the fabricated IC device corresponds to one of the reticles and an associated one of the electronic representations from the layout pattern. For example, one electronic representation may correspond to a diffusion pattern on a silicon substrate, another to a gate oxide pattern, another to a gate polysilicon pattern, another to a contact pattern on an interlayer dielectric, another to a line pattern on a metallization layer, and so on. The targets may be formed from any combination of one or more layers. For example, a special layer may be reserved for the target structures, or the targets may be formed from the dummy layer. Each electronic representation is composed of a plurality of polygons or other shapes (herein, referred to as “figures”), which together define the layout or reticle pattern.
The reticles are produced using the layout patterns. Each reticle corresponds to one or more electronic representation(s) from the circuit pattern database. The reticles may be produced by any suitable pattern generator or reticle writer equipment, such as a MEBES” 4500, commercially available from ETEC of Hayward, Calif.
Any suitable inspection, review, or metrology tool may be utilized during any stage of the fabrication. Each tool may take the form of an optical system, such as a bright field or dark field optical system. The tool may also utilize both bright field and dark field modes. Examples of bright field systems include the 2350, 2351, 2360, and 2370 from KLA-Tencor, Corp. of San Jose, Calif. Examples of dark field system include the AIT II, AIT XP, Fusion, Fusion UV, and SP1 PatternPro available from KLA-Tencor, Corp. of San Jose, Calif. The KLA 301 or 351 Reticle Inspection Tool may be used to inspect reticles. Each tool may also take the form of an electron beam (ebeam) system, such as a scanning, snapshot, or step-and-repeat type ebeam system. Examples of ebeam systems include the eV300 and eS20XP available from KLA Tencor, Corp. of San Jose, Calif. A tool may be designed to detect special types of defects, such as macro defects across a large area of the sample, defects on a bare substrate, or defects within solder bums (e.g., ball grid array bumps). Each tool may also be stand alone or integrated within a processing tool.
The term “correctables” generally refers to data that may be used to correct the alignment of the lithography or scanner tool to improve the control of subsequent lithographic patterning with respect to overlay performance. In essence, the correctables allow the wafer process to proceed within desired limits, i.e., provides feedback and feed forward to get the tool better aligned.
A relationship may be formed between the targets including both process robust and device representing targets. In most cases, the relationship is between process robust and device representing targets, and more particularly process robust targets located in the scribeline (or four corners) and device representing targets located across the field. The relationship may be in the form of direct offsets at given locations in the field, by extrapolation at given points of the field, or based on a mathematical transformation of the overlay at a given points of the field based on a parameterization.
Alternatively, the higher order terms may be thrown away so that only the linear terms are used as correctables for the scanner tool in operation 316. In the above example, the “Bx2” term is thrown out and the “Ax” term is used for the correctable to adjust magnification of the scanner.
Any suitable technique may be used for determining overlay or PPE's dependency on position and resulting correctables. In a “2-layer PPE” approach, double layer segmented marks are placed in 4 corners of the field (or distributed across the field, as standard sampling requires). In addition, the same targets are distributed across the slit. In this example technique, stepper correctables are computed on the full set of the data from all of the targets. However, the model for correctables will include only terms, which will be corrected by (or input into) the scanner tool. Maximum predicted overlay (MPO) can also be computed on the full data set, but this in-field model will include terms, which fits the data in the best way. This technique is applicable for the layers where the target's OMF and process robustness are very high and scribe line space is a crucial.
Step1: Model selection. If the analysis is done for the first time, a wafer and field model is first selected. This model selection may be done as follows:
Step1.A A model, which describes field-by-field or wafer level variations (model1) in overlay, is selected in compliance with control knobs of the scanner/stepper. Model1 depends upon the particular requirements of the exposure tool.
Step1.B For the in-field variations, two field level models for overlay may be chosen. The first model (sub-model2) for overlay is a sub-model of the full model (model2):
ovl = β 0 + ∑ i = 1 p ⁢ ⁢ β i * x i + ∑ i = 1 p ⁢ α i ⁢ cos ⁡ ( ix ) + ∑ i = 1 p ⁢ δ i ⁢ sin ⁡ ( ix ) + ∑ i = 1 p ⁢ ∑ i = 1 p ⁢ η ij ⁢ x i * sin ⁡ ( jx ) + ∑ i = 1 p ⁢ ∑ i = 1 p ⁢ φ ij ⁢ x i * cos ⁡ ( jx ) + f ⁡ ( y ) ( 3.1 ⁢ .1 )
Where x is the coordinate across the slit, f(y) is the term which describes overlay perpendicular to the slit coordinates. This model may be used for MPE (Maximum Predicted Error) computations.
The terms of Sub-model2 may be selected based on any suitable criteria. For instance, over constraining of the data may be minimized and insignificant or noise terms thrown out. In one implementation, the terms of Sub-model2 are selected to achieve a maximum of adjusted R2 (a measurement of goodness of fit) and a minimum of RMS or by other statistical criteria. Maximum adjusted R2 may be determined by:
Adjusted — ⁢ R 2 = ( R 2 - k - 1 n - 1 ) * ( n - 1 n - k )
Where k is total number of parameters in model; n is number of the measurements. Minimum RMS may determined by:
RMS = ∑ i = 1 n ⁢ ( residual i ) 2 n - k
Where k is total number of parameters in model; n is number of the measurements
Step1.C The second model (model3) is selected in compliance with knobs of the scanner/stepper and will be used for scanner/stepper correction. For example, only the linear terms are selected for a scanner tool that has linear correctables.
minΣ(ovli−modeled_ovli)2 (3.1.2)
Where B is vector of correctables, Ovl is a vector of measurements and X is matrix of coordinates, their powers and sines/cosines. The models are computed at this step are the model1 and the model3
Step 3: MPE computations. In order to compute MPE (maximum predicted error) or MPO, model parameters may be computed as described in step2. When minimization is done on model1 and sub-model2. Then MPE may be computed as:
MPE=max(|XB±3*stdev|) (3.1.4)
stdev2=σ2 *X(X′X)−1 X′ (3.1.5) and
σ 2 = ∑ ⁢ ⁢ residuals 2 n - m ( 3.1 ⁢ .6 )
n is number of measurements, m is total number of model parameters.
In a “Simultaneous PPE” approach, double Layer non-segmented marks are placed in the 4 corners of the field (or distributed across the field, as standard sampling requires). Resist-resist and etch-etch simultaneous targets are then distributed across the slit. In general, stepper correctables may be computed by a cascade method. In the first stage, wafer correctables and in-field correctables may be computed on the double-layer data set (4 corners). Then in-field correctables can be computed on simultaneous sets separately for resist and etch or on differences between two layers. The final correctables may then be computed as sum of results. MPO can also be computed by a cascade method. In the first stage, wafer MPO can be computed on the double-layer data set (4 corners). Then using simultaneous sets and engineering models separately for resist and etch or on differences between two layers MPO's contribution of PPE can be computed. The final MPO can be computed as the sum of results. This technique is generally applicable for the layers where the target's Overlay Mark Fidelity and process robustness are very low for double-layer segmented targets.
Step1: Model selection. If the analysis is done for the first time, a wafer and field model is first selected. This model selection may be done in follow way:
Step1.A A model, which describes field-by-field or wafer level variations (model4) in overlay, is selected in compliance with knobs of the scanner/stepper. Model1 depends upon the particular requirements of the exposure tool.
Step1.B For the in-field variations, a first model (model5) is selected in compliance with knobs of the scanner/stepper for the two layer targets (e.g., non-segmented two layer four corner targets).
Step1.C For the in-field variations, a second model and a third model that describe PPE behavior of a current and a previous layer, respectively, across the field are also selected for the simultaneous layer targets (e.g., 1 layer targets distributed across the scribe line, slit, or dies). Both models (sub-model6.1 and sub-model6.2) are sub-models of the full model (model6):
ovl = β 0 + ∑ i = 1 p ⁢ ⁢ β i * x i + ∑ i = 1 p ⁢ α i ⁢ cos ⁡ ( ix ) + ∑ i = 1 p ⁢ δ i ⁢ sin ⁡ ( ix ) + ∑ i = 1 p ⁢ ∑ i = 1 p ⁢ η ij ⁢ x i * sin ⁡ ( jx ) + ∑ i = 1 p ⁢ ∑ i = 1 p ⁢ φ ij ⁢ x i * cos ⁡ ( jx ) + f ⁡ ( x ) ( 3.2 ⁢ .1 )
Where x is coordinate across the slit and f(x) is the correctables which is defined in model5 Unlike the 2-layer PPE Approach outlined above, overlay in a particular direction, such as x, does not depend on the scanner movement in another direction, such as y, but only the scanner aberrations in a same direction, such as the x direction. Any suitable criteria may be used to select appropriate terms to be used from model6, such as Maximum of Adjusted R2 and Minimum of RMS.
Step 2.A At this step only data of standard sampling (4 corners) is used for the computations. The wafer and field correctables of model4 and model5 are combined by a MLE method. This MLE technique works if the values have a normal distribution. However, a different minimization algorithm may be used for non-normal distributions. The results are:
B4—wafer correctables; B5—field correctables.
Step 2.B The correctables of the model5, which are dependent in the across the slit coordinate, may then be computed using the data of the simultaneous targets from current and previous layers separately for each dataset. The method of minimization may be LMS (Least Maximum of Squares) or any other appropriate minimization algorithm such as MLE. The minimization technique chosen generally minimizes maximum-ordered squared residual or in the other words minimizes maximum residuals:
min(maxi=1 n(ovl i−modeled— ovl i)2) (3.2.2)
Step 4.A Predicted overlay (modeled_overlay—4—5) using model4 and model5 is computed.
Step 4.B Parameters of the model6.1 and model6.2 are computed by MLE methods (see 3.1.3) using the data sets of the previous and current layer. The results are:
B6.1—model parameters of the current layer; B6.2—model parameters of the previous layer
σtotal 2=σmodel4&model5 2+σmodel6.1 2+σmodel6.2 2
Step 4.D MPO is then computed:
MPO=max(|(B4*X+B5*X+B6.1*X+B6.2*X)+3*σtotal 2|)
Example models for use in the above model selection operations may be found in “Modern Regression Methods” by Thomas Ryan or Matlab code, which is incorporated by reference in its entirety.
The target rules may include any number and type of rules for facilitating inspection, review, or metrology on the target structures. Particular target types are designed to detect defects or problems with one or more process or exposure tools. The targets are preferably placed so as to capture a maximum number of defects or problems without utilizing an unreasonable amount of die area for the targets. The selection of the number and density of the targets is referred to as a “sample plan.” In one implementation, the sample plan includes a minimum spacing and a maximum spacing between targets of a same type.
By way of example, rules may be developed for an overlay type target based on the types of measurements made on such a target type. Overlay type targets are used to measure misalignment between two different layers. Of course, misalignment may be measured between more than two layers, e.g., all the layers of the device. In a two layer example, each overlay target is formed from a first layer structure and a second subsequent layer structure. Additionally, the structures on the different layers of an overlay target would be designed to have a same center of symmetry. Thus, in a two layer target, the first layer target structures would have a same center of symmetry as the second layer target structures. Additionally, the target portions in the two different layers are preferably proximate to each other so that they may be measured together, e.g., within a single field. Although not required, the two different layer structures of each overlay target are preferably not on top of each other. In one implementation, the first layer structures are at a different rotational position with respect to the center of symmetry than the second layer structures. In another embodiment, the targets may be over the top of one another for Moiré or scatterometry measurements.
A further method of target layout placement could be with respect to modification of dummy structures to comply with specific metrology/inspection target design requirements. By way of example, if overlay was to be measured by scatterometry, then a layout rule could be implemented which requires that periodic dummy structures be placed above one another on subsequent layers. Furthermore, these dummy structures could be designed with specific offsets between them as disclosed in U.S. Provisional Applications: (1) Application No. 60/431,314 filed 5 Dec. 2002 by Walter Mieher et al., (2) Application No. 60/441,077 filed 17 Jan. 2003 by Walter Mieher, and (3) Application No. 60/440,970 filed 17 Jan. 2003 by Walter Mieher, which applications are herein incorporated by reference in their entirety. For example, adjacent areas could be designed to have equal but opposite offsets relative to the dummy structures on the underlying layer. Many other offset configurations could be implemented.
Whether the targets are placed within the active die areas, across one or more streets or the scanner slit, the targets may be formed in any suitable manner. In order to further enhance the overlay error and/or PPE obtained from the target structures, any one of the targets may correspond to process robust targets and/or device representing targets. Process robust targets generally refer to targets that can withstand a wide range of process conditions so that they can be measured with optimal performance under production conditions, i.e., the process has little effect on the process robust target measurement results. In essence, the process robust target is the target that gives the most consistent metrology results across the widest range of process conditions (e.g., CMP, Sputter, film thickness, exposure). Device representing targets, on the other hand, generally refer to targets that produce an overlay error similar to an actual device formed on a product wafer for a given set of process conditions. That is, device representing targets typically change in a similar manner as the device structure itself across the widest range of parameters (lens aberrations, focus, exposure, etc.). For example, if the device structure shifts 10 nm to the right then so does the device representing target. Several suitable process robust and device representative targets are described further in co-pending U.S. patent application Ser. No. 10/367,124, filed 13 Feb. 2003, entitled “OVERLAY METROLOGY AND CONTROL METHOD”, by Michael E. Adel et al., which application is incorporated herein in its entirety.
The pitches of the two overlayed feature sets of the first and second layer may be judicially selected so as to create multiple areas of light and dark contrast, instead of a single area, therefore improving the signal to noise and allowing the application of algorithms already disclosed in the above described U.S. application Ser. No. 10/185,737. Furthermore this configuration allows the application of these algorithms which leverage the “center of symmetry” techniques described in the current application.
In this example, the structures in the regions-of-interest (ROIs) 1202 and 1204 are identical up to 180° rotation around the point called center of symmetry (COS). Overlay (or pattern placement errors) leads to separation between the COSs of inner and outer patterns. The overlay is defined as this misregistration between the COSs of inner and outer patterns. In general, the overlay is measured by locating the COSs of both inner and outer patterns.
In this method, each particular junction in the ROI (“SEM image”) is analyzed to detect the edges (see FIG. 13B). Comparing between the edge from the ROI 1202 and its complementary couple from the ROI 1204 gives their COS position. Although absolute position of the COS cannot be measured, relative position of COSs for inner and outer edges can be detected, thus producing the overlay result.
Utilization of multiple edges from the whole ROI improves the statistics thus reducing random error contribution to the measurement. Separate treatment of physically different edges (“L” vs. “R”, for example) enables monitoring overlay effect on chosen lines/edges. Measuring overlay at various wafer orientations (0, 90°, 180°) allows discrimination of the real overlay from the tool influence—tool induced shifts (TIS; 0° vs. 180°) or rotation induced shift (RIS; 0° vs. 90°).
Another method is based upon correlation. This SEM overlay target also has both Layer1 and Layer2 structures that are to be symmetric with coinciding—by design—centers of symmetry. FIG. 14 is a top view photographic image of a portion of an SEM overlay pattern for correlation based overlay measurements in accordance with one embodiment of the present invention. The whole signals grabbed from the ROIs (boxes 1402, 1404, 1406, and 1408 of FIG. 14) are analyzed.
The signals in complementary ROIs (box 1404 vs. rotated box 1408; box 1406 vs. rotated box 1402) can be compared (either by two-dimensional correlation or by summing up in the vertical direction with subsequent one-dimensional correlation) to locate the COSs of Layer1 and Layer2 structures. The misregistration between the COSs may be defined as the overlay result.
Another method for SEM overlay measurements is based upon the standard optical imaging-like overlay mark designs. In FIG. 15, a photographic image of an SEM design relate, segmented type target is shown. This mark is built of fine pitch gratings on both inner and outer layers. Similarly to standard (optical imaging) design-related, segmented mark, this mark is designed in a way that centers of symmetry (COSs) of inner and outer structures coincide. The overlay is measured as misregistration between these COSs. The algorithms for finding COSs can be similar to standard algorithms described in the above U.S. application Ser. No. 10/185,737. This enables automation of the SEM overlay measurements. In addition, an SEM design-related, segmented mark overlay measurement is less sensitive to image rotation appearing in the SEM. Also, 90° and 180° rotational symmetry allows easy TIS and RIS measurements and their (TIS and RIS) clear separation from the effects cause by imperfectness of the target itself.
1. A method of monitoring or adjusting a process for fabricating a product specimen, the method comprising:
providing a plurality of targets on a product specimen having a plurality of active devices, wherein at least some of the targets are distributed across a field of a lithography tool which was used to fabricate the product specimen and wherein the number and positions of the targets are selected such that a nonlinear dependence curve for a lithography tool and a characteristic of the targets can be determined as a function of field position across the field by measuring the characteristic of each of the targets that are distributed across the field, wherein the targets are distributed across the field by distributing the targets along a street that separates two rows or columns of dies of the field and/or integrating the targets within a plurality of dies that are distributed across the field;
2. A method as recited in claim 1, wherein the product specimen is a semiconductor wafer having a plurality of die.
3. A method as recited in claim 1, wherein the measured characteristic comprises overlay information.
4. A method as recited in claim 3, wherein using the nonlinear dependence curve includes using the nonlinear dependence curve to determine a disposition of a plurality of product specimens which are being fabricated together.
5. A method as recited in claim 4, wherein the targets include four corner targets placed at four corners of the field as well as the targets distributed across the field, the method further comprising measuring overlay on the four corner targets, wherein the nonlinear dependence curve is further based on the overlay of the four corner targets.
6. A method as recited in claim 5, further comprising determining a linear function of the overlay of the four corner targets as a function of field position and using the linear function as correctables for the lithography tool.
7. A method as recited in claim 3, wherein using the nonlinear dependence curve further comprises using only the linear terms of the nonlinear dependence curve as correctables for the lithography tool.
8. A method as recited in claim 7, wherein the targets include four corner targets placed at four corners of the field and targets distributed across the field, the method further comprising measuring overlay of the four corner targets, wherein the nonlinear dependence curve is further based on the overlay of the four corner targets.
9. A method as recited in claim 3, wherein using the nonlinear dependence curve includes using the nonlinear dependence curve as correctables for the lithography tool.
10. A method as recited in claim 9, wherein the targets include four corner targets placed at four corners of the field and targets distributed across the field, the method further comprising measuring overlay on the four corner targets, wherein the nonlinear dependence curve is further based on the overlay of the four corner targets.
11. A method as recited in claim 3, wherein using the nonlinear dependence curve includes using the nonlinear dependence curve to monitor the lithography tool.
12. A method as recited in claim 11, wherein the targets include four corner targets placed at four corners of the field and targets distributed across the field, the method further comprising measuring overlay on the four corner targets, wherein the nonlinear dependence curve is further based on the overlay of the four corner targets.
13. A method as recited in claim 12, further comprising determining a linear function based on the overlay of the four corner targets and using the linear function as correctables for the lithography tool.
14. A method as recited in claim 1, wherein the targets are distributed across the field by distributing the targets along a street that separates two rows or columns of dies of the field.
15. A method as recited in claim 1, wherein the targets are integrated within a plurality of dies that are distributed across the field.
16. A method of monitoring or adjusting a process for fabricating a product specimen, the method comprising:
providing a plurality of targets on a product specimen having a plurality of active devices, wherein a field of a lithography tool includes a first set of process robust targets formed in at least the four corners of the field and in streets in the field and wherein a second set of device representing targets are distributed across the field of the lithography tool by distributing the targets along a street that separates two rows or columns of dies of the field and/or integrating the targets within a plurality of dies that are distributed across the field, wherein the lithography tool was used to fabricate the product specimen and wherein the number and positions of the first and second sets of targets are selected such that a nonlinear dependence curve for a lithography tool and a characteristic of the targets can be determined as a function of field position across the field by measuring the characteristic of each of the targets;
determining a nonlinear dependence curve for the lithography tool as a function of field position across the field, wherein the nonlinear dependence curve is determined by fitting a nonlinear function to at least the second set of device representing targets' measured characteristics; and
17. A method as recited in claim 16, wherein the measured characteristic comprises overlay information.
18. A method as recited in claim 1, wherein the targets are distributed across a center of the field.
19. A method as recited in claim 1, wherein the number and positions of the targets are selected such that a minimum placement distance of the targets is selected so as to capture a known rate of process variation across the field in the determined nonlinear dependence curve.
20. A method as recited in claim 1, wherein the number and positions of the targets are selected such that a minimum placement distance of the targets is selected so as to capture a known rate of aberrations across the field of the lithography tool in the determined nonlinear dependence curve.
21. A method as recited in claim 1, wherein the number and positions of the targets are selected such that a minimum placement distance of the targets is selected so as to capture a known variation of lithography errors produced by the lithography tool in the determined nonlinear dependence curve.
22. A method as recited in claim 1, wherein the number and positions of the targets are selected such that a minimum placement distance is selected so as to capture a minimum variation spacing of process variations, lithography aberrations, and lithography errors in the determined nonlinear dependence curve.
23. A method as recited in claim 22, wherein the number of targets are selected to result in a measurement uncertainty equal to or greater than a required measurement uncertainty.
US10/950,172 2003-07-02 2004-09-23 Apparatus and methods for determining overlay and uses of same Expired - Fee Related US7608468B1 (en)
US48462703P true 2003-07-02 2003-07-02
US50628103P true 2003-09-26 2003-09-26
US54654604P true 2004-02-20 2004-02-20
US10/858,836 US7346878B1 (en) 2003-07-02 2004-06-01 Apparatus and methods for providing in-chip microtargets for metrology or inspection
US10/950,172 US7608468B1 (en) 2003-07-02 2004-09-23 Apparatus and methods for determining overlay and uses of same
US12/560,229 US7876438B2 (en) 2003-07-02 2009-09-15 Apparatus and methods for determining overlay and uses of same
US10/858,836 Continuation-In-Part US7346878B1 (en) 2003-07-02 2004-06-01 Apparatus and methods for providing in-chip microtargets for metrology or inspection
US12/560,229 Division US7876438B2 (en) 2003-07-02 2009-09-15 Apparatus and methods for determining overlay and uses of same
US7608468B1 true US7608468B1 (en) 2009-10-27
ID=41211059
US10/950,172 Expired - Fee Related US7608468B1 (en) 2003-07-02 2004-09-23 Apparatus and methods for determining overlay and uses of same
US12/560,229 Active US7876438B2 (en) 2003-07-02 2009-09-15 Apparatus and methods for determining overlay and uses of same
US (2) US7608468B1 (en)
US20110207247A1 (en) * 2010-02-19 2011-08-25 Chan Hwang Method of correcting overlay and semiconductor device manufacturing method using the same
WO2012126684A1 (en) * 2011-03-24 2012-09-27 Asml Netherlands B.V. Substrate and patterning device for use in metrology, metrology method and device manufacturing method
WO2013033322A1 (en) * 2011-09-01 2013-03-07 Kla-Tencor Corporation Method and system for detecting and correcting problematic advanced process control parameters
US20130342831A1 (en) * 2012-06-26 2013-12-26 Kla-Tencor Corporation Device-like scatterometry overlay targets
US20140375793A1 (en) * 2012-02-17 2014-12-25 Hitachi High-Technologies Corporation Method for measuring overlay and measuring apparatus, scanning electron microscope, and gui
US20150153268A1 (en) * 2013-05-29 2015-06-04 Kla-Tencor Corporation Multi-layered target design
US20150356232A1 (en) * 2014-06-06 2015-12-10 Synopsys, Inc. Method and System for Generating a Circuit Design, Method for Calibration of an Inspection Apparatus and Method for Process Control and Yield Management
US20160061589A1 (en) * 2014-08-29 2016-03-03 Asml Netherlands B.V. Metrology method, target and substrate
US9372078B1 (en) * 2014-06-20 2016-06-21 Western Digital (Fremont), Llc Detecting thickness variation and quantitative depth utilizing scanning electron microscopy with a surface profiler
US10107765B2 (en) 2014-05-12 2018-10-23 KLA—Tencor Corporation Apparatus, techniques, and target designs for measuring semiconductor parameters
US10387608B2 (en) * 2013-03-04 2019-08-20 Kla-Tencor Corporation Metrology target identification, design and verification
JPWO2011004534A1 (en) * 2009-07-09 2012-12-13 株式会社日立ハイテクノロジーズ Semiconductor defect classification method, semiconductor defect classification apparatus, semiconductor defect classification program
TWI603216B (en) * 2012-11-21 2017-10-21 Kla-Tencor Corp Segmented target process and design methods compatible
US8969870B2 (en) * 2013-03-12 2015-03-03 Macronix International Co., Ltd. Pattern for ultra-high voltage semiconductor device manufacturing and process monitoring
US20150192404A1 (en) * 2013-03-31 2015-07-09 Kla-Tencor Corporation Reducing registration error of front and back wafer surfaces utilizing a see-through calibration wafer
US9163928B2 (en) * 2013-04-17 2015-10-20 Kla-Tencor Corporation Reducing registration error of front and back wafer surfaces utilizing a see-through calibration wafer
WO2015009619A1 (en) 2013-07-15 2015-01-22 Kla-Tencor Corporation Producing resist layers using fine segmentation
US10228320B1 (en) 2014-08-08 2019-03-12 KLA—Tencor Corporation Achieving a small pattern placement error in metrology targets
US20190219930A1 (en) * 2018-01-12 2019-07-18 Globalfoundries Inc. Self-referencing and self-calibrating interference pattern overlay measurement
US5863680A (en) 1995-10-13 1999-01-26 Nikon Corporation Exposure method utilizing alignment of superimposed layers
US20010055720A1 (en) 2000-06-08 2001-12-27 Kabushiki Kaisha Toshiba Alignment method, overlay deviation inspection method and photomask
US20030102440A1 (en) * 2001-12-03 2003-06-05 Taek-Soo Sohn Method of aligning a wafer in a photolithography process
US6612159B1 (en) 1999-08-26 2003-09-02 Schlumberger Technologies, Inc. Overlay registration error measurement made simultaneously for more than two semiconductor wafer layers
US6734971B2 (en) * 2000-12-08 2004-05-11 Lael Instruments Method and apparatus for self-referenced wafer stage positional error mapping
US6753120B2 (en) * 2001-11-27 2004-06-22 Samsung Electronics Co., Ltd. Alignment measuring method of photolithography process
JPH0251214A (en) 1988-08-12 1990-02-21 Sanyo Electric Co Ltd Manufacture of semiconductor device
US7346878B1 (en) * 2003-07-02 2008-03-18 Kla-Tencor Technologies Corporation Apparatus and methods for providing in-chip microtargets for metrology or inspection
2004-09-23 US US10/950,172 patent/US7608468B1/en not_active Expired - Fee Related
2009-09-15 US US12/560,229 patent/US7876438B2/en active Active
US20060177120A1 (en) 2000-08-30 2006-08-10 Kla-Tencor Corporation Overlay marks, methods of overlay mark design and methods of overlay measurements
US20060204073A1 (en) 2000-08-30 2006-09-14 Kla-Tencor Corporation Overlay marks, methods of overlay mark design and methods of overlay measurements
Adel, et al., "Overlay Metrology and Control Method", U.S. Appl. No. 10/367,124, filed Feb. 13, 2003.
Claims from U.S. Appl. No. 10/858,836, filed Jun. 1, 2004.
Ghinovker, et al., "Overlay Marks, Methods of Overlay Mark Design and Methods of Overlay Measurements", U.S. Appl. No. 09/894,987, filed Jun. 27, 2001.
Notice of Allowance mailed Sep. 5, 2007, from related U.S. Appl. No. 10/858,836.
U.S. Appl. No. 10/367,124, filed Feb. 13, 2003; Office Action mailed Apr. 23, 2007.
U.S. Appl. No. 10/367,124, filed Feb. 13, 2003; Office Action mailed Oct. 4, 2007.
U.S. Office Action mailed Oct. 10, 2006, from related U.S. Appl. No. 10/950,172.
US8773153B2 (en) * 2010-02-19 2014-07-08 Samsung Electronics Co., Ltd. Method of correcting overlay and semiconductor device manufacturing method using the same
US8709687B2 (en) 2011-03-24 2014-04-29 Asml Netherlands B.V. Substrate and patterning device for use in metrology, metrology method and device manufacturing method
US9331022B2 (en) 2011-03-24 2016-05-03 Asml Netherlands B.V. Substrate and patterning device for use in metrology, metrology method and device manufacturing method
US9799112B2 (en) * 2012-02-17 2017-10-24 Hitachi High-Technologies Corporation Method for measuring overlay and measuring apparatus, scanning electron microscope, and GUI
US9841370B2 (en) * 2013-05-29 2017-12-12 Kla-Tencor Corporation Multi-layered target design
TWI624025B (en) * 2013-05-29 2018-05-11 克萊譚克公司 Multi-layered target design
CN105279302A (en) * 2014-06-06 2016-01-27 新思科技有限公司 Method and system for generating a circuit design, method for calibration of an inspection apparatus and method for process control and yield management
US10386176B2 (en) * 2014-08-29 2019-08-20 Asml Netherlands B.V. Metrology method, target and substrate
US10304178B2 (en) * 2015-09-18 2019-05-28 Taiwan Semiconductor Manfacturing Company, Ltd. Method and system for diagnosing a semiconductor wafer
US10337991B2 (en) * 2015-12-08 2019-07-02 Kla-Tencor Corporation Control of amplitude and phase of diffraction orders using polarizing targets and polarized illumination
US7876438B2 (en) 2011-01-25
US20100005442A1 (en) 2010-01-07
TWI576675B (en) 2017-04-01 Metrology methods, systems and computer products
US20050010890A1 (en) 2005-01-13 Design-based monitoring
KR20120058572A (en) 2012-06-07 Metrology method and apparatus, lithographic apparatus, lithographic processing cell and substrate comprising metrology targets
USRE45245E1 (en) 2014-11-18 Apparatus and methods for determining overlay of structures having rotational or mirror symmetry
EP1006413A2 (en) 2000-06-07 Alignment method and exposure apparatus using the same
US10331041B2 (en) 2019-06-25 Metrology method and apparatus, lithographic system and device manufacturing method
JP4593236B2 (en) 2010-12-08 Evaluation system and method for dimension measurement scanning electron microscope system and the circuit pattern
CN104350424A (en) 2015-02-11 Metrology method and apparatus, substrate, lithographic system and device manufacturing method
US6975382B2 (en) 2005-12-13 Method and apparatus for self-referenced dynamic step and scan intra-field lens distortion
TWI599853B (en) 2017-09-21 Focus determination method, test apparatus, and device manufacturing method
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GHINOVKER, MARK;ADEL, MICHAEL E.;POPLAWSKI, JORGE;AND OTHERS;REEL/FRAME:016121/0857;SIGNING DATES FROM 20041213 TO 20041222