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Timestamp: 2019-10-18 13:37:37
Document Index: 539145040

Matched Legal Cases: ['Application No. 10', 'art 2111', 'art 2111', 'art 2111', 'art 2111', 'art 21113', 'art 2111', 'art 2111', 'art 2112', 'art 2111', 'art 2112', 'art 2112', 'art 2112']

Built-in self-test circuit and semiconductor device including the same - SK hynix Inc.
United States Patent 9405648
Kang, Hee-won (Gyeonggi-do, KR)
14/286748
G11C29/00; G01R31/3187; G06F11/27; G11C29/16; G11C29/44
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KR1020100084572 July, 2010
KR20100084572A 2010-07-26
1. A built-in self-test circuit comprising: a command storage unit suitable for storing commands inputted from an external device; an input/output control unit suitable for controlling the command storage unit to sequentially store the commands and sequentially output stored commands as internal commands in a test operation; and a command decoder unit suitable for decoding the internal commands outputted from the command storage unit and outputting a test command, wherein the commands include a command signal including CS, RAS, CAS, WE, and CKE.
2. The built-in self-test circuit of claim 1, wherein the command storage unit includes a flash memory.
3. The built-in self-test circuit of claim 1, wherein the input/output control unit comprises: an input control section suitable for outputting a plurality of input control signals for controlling the commands to be sequentially stored in the command storage unit in response to a clock signal; and an output control section suitable for outputting a plurality of output control signals for controlling the internal commands to be sequentially outputted from the command storage unit in response to the clock signal and an output enable signal in the test operation.
4. The built-in self-test circuit of claim 3, wherein the input control signal comprises: an internal write command signal for controlling the commands to be stored in the command storage unit; and a plurality of write address signals for designating positions in which the commands are to be sequentially stored, wherein the output control signal comprises: an internal read command signal for controlling the internal commands to be outputted from the command storage unit; and a plurality of read address signals for designating positions in which the internal commands are sequentially stored.
5. The built-in self-test circuit of claim 4, wherein the command storage unit comprises: a command latch section suitable for latching the commands in synchronization with a buffering signal of the clock signal; a multiplexer section suitable for outputting latched commands, which are outputted from the command latch section, in synchronization with the internal write command signal; a storage section suitable for sequentially storing commands, which are outputted from the multiplexer section, in response to the internal write command signal and the plurality of write address signals, and sequentially outputting stored commands in response to the internal read command signal and the plurality of read address signals; and a command multiplexer section suitable for outputting commands, which are outputted from the storage section, as the internal commands in synchronization with the internal read command signal.
6. The built-in self-test circuit of claim 5, wherein the input control section comprises: a clock buffer part suitable for buffering the clock signal and outputting the buffering signal; a clock repeater suitable for compensating for the buffering signal level outputted from the clock buffer part and generating an internal clock signal; a write command generation part suitable for generating the internal write command signal in response to the internal clock signal; and a write address generation part suitable for generating the plurality of write address signals in response to the internal clock signal.
7. The built-in self-test circuit of claim 6, wherein the input control section further comprises: a delay part suitable for delaying the internal write command signal for a predetermined time and transmitting a delayed internal write command signal to the storage section as the internal write command signal.
8. The built-in self-test circuit of claim 5, wherein the output control section comprises: a read command generation part suitable for generating the internal read command signal in response to the buffering signal of the clock signal and the output enable signal; and a read address generation part suitable for generating the plurality of read address signals in response to the buffering signal of the clock signal and the output enable signal.
9. The built-in self-test circuit of claim 8, wherein the output control section further comprises: a first delay part suitable for delaying the internal read command signal for a predetermined time and transmitting a delayed first internal read command signal to the command multiplexer section as the internal read command signal; and a second delay part suitable for delaying the delayed first internal read command signal for a predetermined time and controlling the command decoder unit.
10. The built-in self-test circuit of claim 1, wherein the external device includes a memory controller.
The present application claims priority of Korean Patent Application No. 10-2013-0149202, entitled “BUILT-IN SELF-TEST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME” and filed on Dec. 3, 2013, which is incorporated herein by reference in its entirety.
Exemplary embodiments of the present invention are directed to a semiconductor device that recognizes sequences of all commands without an external controller and includes a test logic substantially the same as various test applications of a test device.
Since the semiconductor memory 2000 initially receives the external commands EX_CMD from the memory controller 1000 only once, stores the internal commands INT_CMD in the command storage unit 2120, and uses the internal commands INT_CMD in the test operation, the stored internal commands INT_CMD are not erased. Accordingly, nonvolatile flash memory may be used as the command storage unit 2120.
Referring to FIG. 2, the built-in self-test circuit 2100 may include an input/output control unit 2110 having an input control section 2111 and an output control section 2112, a command storage unit 2120 and a command decoder unit 2130.
The input control section 2111 receives the dock signal CLK and generates a plurality of input control signals IN_CTRL for controlling the external commands EX_CMD to be sequentially stored in the command storage unit 2120. The configuration and operation of the input control section 2111 will be described in detail with reference to FIG. 3.
Referring to FIG. 3, the input control section 2111 may include a clock buffer part 2111_1, a clock repeater 2111_2, a write command generation part 2111_3, a write address generation part 2111_4, and a delay part 2111_5 and the command storage unit 2120 may include a command latch section 2121, a multiplexer section 2122, and a storage section 2123.
The write command generation part 21113 generates an internal write command WT_CMD for controlling the latched internal command INT_CMD to be stored in the multiplexer section 2122 in response to the internal clock signal INT_CLK. The internal write command WT_CMD is generated at each rising edge of the internal clock signal INT_CLK.
The write address generation part 2111_4 generates an address increment signal at each rising edge of the internal clock signal INT_CLK. The write address generation part 2111_4 may generate the signals in the sequence of the row address WT_ROW_ADD, the column address WT_COLUMN_ADD and the bank address WT_BANK_ADD, and designate positions in which the internal commands INT_CMD are to be stored.
The read command generation part 2112_1 generates an internal read command signal RD_CMD for controlling the internal commands INT_CMD stored in the storage section 2123 to be outputted in response to the buffered clock signal CLK_RPT and the output enable signal OUT_EN. The buffered clock signal CLK_RPT is outputted through the dock buffer part 2111_1 among the elements of the input control section 2111, and the output enable signal OUT_EN is activated in the test operation and controls the internal commands INT_CMD to be outputted.
The read address generation part 2112_2 generates an address increment signal at each rising edge of the buffered clock signal CLK_RPT. The read address generation part 2112_2 may generate the signals in the sequence of the row address RD_ROW_ADD, the column address RD_COLUMN AD D, and the bank address RD_BANK_ADD, designate the positions in which the internal commands INT_CMD have been stored, and control the internal commands INT_CMD to be sequentially outputted.
The command multiplexer section 2124 outputs the internal commands INT_CMD, which are outputted from the storage section 2123, in synchronization with the delayed first read command signal RD_CMD_DLY.
The command decoder unit 2130 decodes the internal commands INT_CMD, which are outputted from the command multiplexer section 2124, in response to a delayed second read command signal RD_CMD_DLY2 delayed through the second delay part 2112_4 and outputs the test command OP_CMD.
The one slave chip 621 of the plurality of slave chips stores the external commands EX_CMD in the command storage unit 621_1 by the input/output control signal CTRL, and decodes the stored internal commands INT_CMD through the command decoder unit 621_2 and outputs the test command OP_CMD in the test operation.
While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
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