Source: http://www.google.com/patents/US7606016?ie=ISO-8859-1&dq=7,339,580
Timestamp: 2015-04-19 10:39:36
Document Index: 564246683

Matched Legal Cases: ['Application No. 60', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11']

Patent US7606016 - Power amplifier protection - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA power amplifier protection circuit that includes protection circuitry to variably shunt an input radio frequency (RF) signal to AC ground, turn off bias to an output transistor of a power amplifier, and turn off the output transistor. The power amplifier protection circuit features an asymmetrical...http://www.google.com/patents/US7606016?utm_source=gb-gplus-sharePatent US7606016 - Power amplifier protectionAdvanced Patent SearchPublication numberUS7606016 B1Publication typeGrantApplication numberUS 11/845,660Publication dateOct 20, 2009Filing dateAug 27, 2007Priority dateMay 15, 2003Fee statusPaidAlso published asUS7268990, US7864498, US8179648Publication number11845660, 845660, US 7606016 B1, US 7606016B1, US-B1-7606016, US7606016 B1, US7606016B1InventorsWayne A. Loeb, Alireza Shirvani-MahdaviOriginal AssigneeMarvell International Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (18), Non-Patent Citations (8), Referenced by (1), Classifications (13), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetPower amplifier protection
US 7606016 B1Abstract
A power amplifier protection circuit that includes protection circuitry to variably shunt an input radio frequency (RF) signal to AC ground, turn off bias to an output transistor of a power amplifier, and turn off the output transistor. The power amplifier protection circuit features an asymmetrical control that can quickly shut off a power amplifier, and turn on the power amplifier at a steady, controlled rate when an output transistor exceeds a predetermined threshold voltage.
shunt circuitry operable to shunt an RF input signal toward ground, the shunt circuitry including,
a shunt switch operable to shunt the RF input signal to ground and release the RF input signal from ground, the shunt switch being controlled by control circuitry; and
the control circuitry including ramp circuitry, the ramp circuitry operable to control the shunt switch so that the shunt switch releases the RF signal from ground, the control circuitry including a delay stage so that the shunt circuitry continues to shunt the RF input signal to ground until after an associated circuit has turned back on after a shutdown event; and
bias shutdown circuitry operable to shut off a bias voltage or a bias current being supplied to an output transistor of the associated circuit.
7. The protection circuit of claim 1, further comprising peak detection circuitry operable to monitor an output voltage of the associated circuit and provide a protection signal to the shunt circuitry and the bias shutdown circuitry when the output voltage of the associated circuit exceeds a threshold voltage level.
shunting means for shunting an RF input signal to ground and releasing the RF input signal from ground, the shunting means being controlled by control means; and
the control means for controlling the shunting means so that the shunting means releases the RF signal from ground for input to an associated circuit, the control means including a delaying means for delaying a release of the RF input signal until after the associated circuit has turned back on after a shutdown event; and
biasing means for shutting off a bias voltage or a bias current being supplied to an output transistor of the associated circuit.
17. The protection circuit of claim 12, further comprising detecting means for monitoring an output voltage of the associated circuit and providing a protection signal to the shunting means and the biasing means when the output voltage exceeds a threshold voltage level.
21. A method for protecting a circuit from elevated output voltages, the method comprising:
defining a threshold voltage level for a peak detection;
detecting an output voltage of a circuit exceeding the threshold voltage level;
reducing a bias to the circuit when the output voltage exceeds the threshold voltage level; and
separately from reducing the bias circuit, shunting to ground an input of the circuit when the output voltage exceeds the threshold voltage level, until after an output transistor has turned back on.
shunting an RF input signal to an RF power amplifier in the circuit to ground when the output voltage exceeds the threshold voltage level.
supplying bias to the output transistor of the circuit and turning on the output transistor when the output voltage is reduced to a level below the threshold voltage level.
gradually releasing the RF input signal from ground when the output voltage is reduced to a level below the threshold voltage level.
delaying the release of the RF input signal from ground until a time after the output transistor has turned on.
29. The method of claim 21 wherein shunting to ground an input of the circuit comprises shutting off the output.
This application is a continuation application of U.S. patent application Ser. No. 10/767,045, filed on Jan. 28, 2004, which claims the benefit of U.S. Provisional Application No. 60/470,629, filed May 15, 2003. The entire disclosure of each of these prior applications is incorporated herein by reference.
In general, in one aspect, this specification describes a protection circuit for a radio frequency (RF) power amplifier. The RF power amplifier is operable to receive an RF input signal and amplify the RF input signal. The RF power amplifier includes shunt circuitry operable to shunt an RF input signal to AC ground. The shunt circuitry includes a shunt switch operable to shunt the RF input signal to AC ground and release the RF input signal from AC ground, and control circuitry to control the shunt switch. The control circuitry includes ramp circuitry operable to control the shunt switch so that the shunt switch gradually releases the RF signal from AC ground for input to an RF amplifier.
FIG. 2 illustrates an RF power amplifier 200. RF power amplifier 200 includes power amplifier circuitry 202 for amplifying an RF input signal (RF IN) 204 to provide an amplified RF output signal (RF OUT) 206. Power amplifier circuitry 202 can be implemented using transistors, for example, GaAs HBTs or SiGe bipolar transistors. Power amplifier circuitry 202 can also be implemented using CMOS transistor technologies and other transistor technologies, including silicon and gallium nitrite.
Bias network 208 further includes transistors M1 and M2 to turn off transistors Q1 and Q2 to shut off their respective bias (base) current being supplied in response to receiving protection signal 216. Transistor M1, in the presence of protection signal 216, couples the base node of Q1 to ground. Transistor M2, in the presence of protection signal 216, couples the base node of Q2 to ground. When RF OUT 206 drops below the predefined threshold, the base nodes of transistors Q1 and Q2 are released (i.e., transistors M1 and M2 are turned off. Transistors Q1 and Q2 turn back on after capacitors C2 and C3 have charged to the threshold voltage of transistors Q1 and Q2, respectively.
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Draft3 R3-Oct. 25, 1998.2IEEE Computer Society, "IEEE Standard for Information Technology-DRAFT Supplement to STANDARD [for] Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Further Higher Data Rate Extension in the 2.4 GHz Band", IEEE P802.11g/D8.2, Apr. 2003.3IEEE Computer Society, "IEEE Standard for Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Amendment 5: Spectrum and Transmit Power Management Extensions in the 5 GHz Band in Europe", IEEE P802.11h-2003.4IEEE Computer Society, "IEEE Standard for Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Amendment 6: Medium Access Control (MAC) Security Enhancements", IEEE Std 802.11i-2004.5IEEE Computer Society, "IEEE Standard for Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifictions: Amendment 7: Medium Access Control (MAC) Quality of Service (QoS) Enhancements", IEEE P802.11e/D11.0, Oct. 2004.6IEEE Computer Society, "Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications", IEEE Std 802.11-First Edition, 1999.7IEEE Computer Society, "Supplement to IEEE Standard for Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher-speed Physical Layer Extension in the 2.4 GHZ Band", IEEE Std 802.11b-1999 (Supplement to IEEE Std 802.11-1999).8IEEE Computer Society, "Supplement to IEEE Standard for Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-speed Physical Layer in the 5 GHZ Band", IEEE Std 802.11a-1999 (Supplement to IEEE Std 802.11-1999).Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8135364 *Aug 5, 2009Mar 13, 2012Motorola Solutions, Inc.Method and apparatus for controling output power of communication equipment* Cited by examinerClassifications U.S. Classification361/111, 361/56, 361/91.1International ClassificationH02H3/20, H02H9/04Cooperative ClassificationH03F1/52, H02H9/025, H03F2200/27, H03F3/191, H03F2200/435, H03F2200/231European ClassificationH03F3/191, H03F1/52Legal EventsDateCodeEventDescriptionApr 22, 2013FPAYFee paymentYear of fee payment: 4Jun 2, 2008ASAssignmentOwner name: MARVELL INTERNATIONAL LTD., BERMUDAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL SEMICONDUCTOR, INC.;REEL/FRAME:021030/0344Effective date: 20040127Owner name: MARVELL SEMICONDUCTOR, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LOEB, WAYNE A;SHIRVANI, ALIREZA;REEL/FRAME:021030/0366Effective date: 20040126RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services