Source: http://www.google.com/patents/US5233219?ie=ISO-8859-1
Timestamp: 2014-10-20 18:03:11
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Patent US5233219 - Three-dimensional semiconductor device structure - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device and a method of manufacture thereof by which circuit elements are readily formed as a three-dimensional structure without increasing the device size are provided. An N31 type epitaxially grown layer (4) is first formed on a P30 type silicon substrate (2), and then a P30 type diffusion...http://www.google.com/patents/US5233219?utm_source=gb-gplus-sharePatent US5233219 - Three-dimensional semiconductor device structureAdvanced Patent SearchPublication numberUS5233219 APublication typeGrantApplication numberUS 07/863,266Publication dateAug 3, 1993Filing dateApr 3, 1992Priority dateOct 30, 1991Fee statusPaidPublication number07863266, 863266, US 5233219 A, US 5233219A, US-A-5233219, US5233219 A, US5233219AInventorsNoriyuki Shimoji, Hidemi TakasuOriginal AssigneeRohm Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (1), Referenced by (9), Classifications (24), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetThree-dimensional semiconductor device structureUS 5233219 AAbstract A semiconductor device and a method of manufacture thereof by which circuit elements are readily formed as a three-dimensional structure without increasing the device size are provided. An N31 type epitaxially grown layer (4) is first formed on a P30 type silicon substrate (2), and then a P30 type diffusion layer (31), an emitter layer (32) (P30 type) and an N30 type diffusion layer (33) are formed in the N31 type epitaxially grown layer (4). Next, an underside of the substrate (2) is etched to form a bottom recessed part (6), from which a collector region (8) (P+ type) is formed in such a manner that it reaches the P+ type diffusion layer (31). Thus, a vertical PNP type transistor is obtained readily. In this method, the collector region (8) is formed at a latter step, so that redistribution of the collector region (8) due to epitaxial growth can be avoided.
What is claimed is: 1. A semiconductor device, comprising:a substrate having an upper main surface and a bottom surface; a first layer having a first impurity concentration formed on said upper main surface of said substrate, and first layer having a top surface and a bottom surface; an opening formed in said substrate exposing said bottom surface of said first layer; a first region having a second impurity concentration, different from said first impurity concentration, formed in said top surface of said first layer above the exposed said bottom surface; a top insulating layer formed on said top surface of said first layer; a second region having said second impurity concentration formed in substantially all of the exposed said bottom surface of said first layer; and a bottom insulating layer formed covering said bottom surface of said substrate, sidewalls of said substrate exposed in said opening, and the exposed said bottom surface of said first layer, wherein said first impurity concentration of said first layer interposes said first and second regions in a direction normal to said substrate. 2. The semiconductor device according to claim 1, whereinsaid first impurity concentration is an N-type conductivity and said second impurity concentration is a P-type conductivity, and said first and second regions, and said first layer comprise an PNP transistor. 3. The semiconductor device according to claim 1, further comprising a third region of P-type conductivity formed in said top surface of said first layer above the exposed said bottom surface, whereinsaid first region is formed in said third region, said first and second impurity concentrations are N-type conductivity, and said first, second and third regions, and said first layer comprise an NPN transistor. 4. The semiconductor device according to claim 1, whereinsaid first impurity concentration is an N-type conductivity and said second impurity concentration is a P-type conductivity, and said first and second regions, and said first layer comprise a pinch resistor. Description
The present invention relates to a semiconductor device and a method of manufacture thereof, and more particularly, to a technique to readily form a three-dimensional structure of the device.
In semiconductor devices used in semiconductor integrated circuits or the like, the way of forming a desired circuit is usually such that impurities like ions are first implanted into the surface of a silicon substrate, and then diffused to form the device. The devices thus obtained are generally formed only on the surface of the silicon substrate, arranged in the lateral direction (lateral device). As a result, a current conducting region is limited to the surface area of the silicon substrate, allowing the resulting circuit to have a low efficiency in device forming and wiring. In order to solve this problem, a way of forming devices in the vertical direction (vertical device) has been proposed. This method is to form devices at a right angle to the surface of the substrate, thus obtaining a high efficiency in device forming and wiring.
FIG. 1 shows a method for manufacturing a conventional vertical PNP type transistor. According to this method, impurities are first implanted into a P type silicon substrate 75 through an oxide layer 79. The implanted ions are then diffused to form an N30 type separation layer 81 which acts as buried layer for use in device separation (FIG. 1A).
The N+ type separation layer 81 is next subjected to impurities implantation, and thereafter heated at a high temperature. This heat treatment allows the implanted ions to be diffused to form a P+ type buried layer 77 on the N+ type separation layer 81, whereas an N31 type epitaxially grown layer 4 is grown on the P type silicon substrate 75. Thus, the P30 type buried layer 77 acting as collector layer is provided between the P type silicon substrate 75 and the N- type epitaxially grown layer 4.
Further, by means of photoetching method (photoresist), a P+ type diffusion layer 82, an emitter layer (P30 type) 84 and an N+ type diffusion layer 86 are formed in the N- type epitaxially grown layer 4. Thereafter, a collector electrode 83, an emitter electrode 85 and a base electrode 87 are attached to the P30 type diffusion layer 82, the emitter layer (P30 type) 84 and the N+ type diffusion layer 86, respectively.
By these processes, the PNP type transistor having the P+ type buried layer 77, the N- type epitaxially grown layer 4 and the emitter layer (P+ type) 84 is obtained. In this transistor, each device is arranged in the vertical direction so as to stand at a right angle (FIG. 1C, arrow 90) to the surface of the substrate, thus formed as a three-dimensional structure. This structure allows an efficient circuit.
The conventional semiconductor device, however, has the following disadvantages. The N+ type separation layer 81 and the P+ type buried layer 77 are lain between the P type silicon substrate 75 and the N- type epitaxially grown layer 4, as shown in FIG. 1C. In order to construct this structure, the N+ type separation layer 81 and the P+ type buried layer 77 are first formed, and thereafter the N- type epitaxially grown layer 4 are grown on the P type silicon substrate 75. The epitaxial growth at this step usually requires heating at 1000� C. or more. The heat treatment, however, is responsible for the following problem. Namely, impurities, contained in the N+ type separation layer 81 and the P+ type buried layer 77, are again made to diffuse and redistribute by the heat treatment. The effect of redistribution is such that it changes electrical characteristics of the transistor. Also, it increases the device size. Accordingly, a fine-tuned control is necessary to obtain the transistor of which circuit elements are constructed in three dimensions, having desired electrical characteristics.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of manufacture thereof by which circuit elements are readily formed as a three-dimensional structure without increasing the device size.
a semiconductor substrate having a substrate surface and a bottom recessed part;
a top face region which is formed in the substrate surface so as to confront the bottom recessed part; and
a bottom face region which is formed from the bottom recessed part.
providing a semiconductor substrate having a substrate surface with a bottom recessed part;
forming a top face region in the substrate surface so as to confront the bottom recessed part; and
forming a bottom face region from the bottom recessed part.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A-1C are cross-sectional views illustrating steps in a manufacturing method of a conventional PNP type transistor.
FIG. 2 is a cross-sectional view illustrating a PNP type transistor which is an embodiment of a semiconductor device of the present invention.
FIGS. 3A-3C are cross-sectional views illustrating steps for manufacturing the PNP type transistor shown in FIG. 2.
FIGS. 4A-4C are cross-sectional views illustrating further steps for manufacturing the PNP type transistor shown in FIG. 2.
FIGS. 5A and 5B are cross-sectional views illustrating a NPN type transistor and a pinch resistor, respectively, which are other embodiments of semiconductor devices of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT A semiconductor device and a method of manufacture thereof according to an embodiment of the present invention is described below. FIG. 2 shows a cross-sectional view illustrating a PNP type transistor. FIGS. 3A-3C and FIGS. 4A-4C show a method for manufacturing the PNP type transistor shown in FIG. 2, which will be explained below in detail.
First, an N- type epitaxially grown layer 4 is grown on a P+ type silicon substrate 2, as shown in FIG. 3A. Next, a top face insulating layer 18 and a bottom face insulating layer 17 are formed on a top face of the N- type epitaxially grown layer 4 and on a bottom face of the P+ type silicon substrate 2, respectively. Further, a P+ type diffusion layer 31, an emitter layer 32 (P+ type) acting as top face region and an N+ type diffusion layer 33 are formed in the N- type epitaxially grown layer 4 by ion diffusion, as shown in FIG. 3B. The purpose of forming the N+ type diffusion layer 33 is to relieve the great difference in resistance value between the N- type epitaxially grown layer 4 and a base electrode 43 (FIG. 2) which will be formed later on.
Also, photoetching method (photoresist) is used in order to form the P+ type diffusion layer 31, the emitter layer 32 and the N+ type diffusion layer 33. In this method, a pattern is first formed on the surface of the N- type epitaxially grown layer 4 (not shown), and then impurities such as ions are implanted using the photoresist as a mask. The impurities, some of them being blocked by the mask, are implanted into the N- type epitaxially grown layer 4 according to the precedent pattern. The impurities thus reliably implanted into the desired position are then thermally diffused to form the P+ type diffusion layer 31, the emitter layer 32 and the N+ type diffusion layer 33.
Next, a part of the bottom face insulating layer 17 on the P+ type silicon substrate 2 is removed to thereby an opening L1 is patterned (FIG. 3C). Further, a bottom recessed part 6 is formed from the opening L1 in the direction of the emitter layer 32 as shown in FIG. 4A, so that the emitter layer 32 acting as top face region is allowed to face the bottom recessed part 6. This is carried out by etching (chemical etching) by the use of such an alkaline solution as a KOH solution, or a mixed solution of hydrofluoric acid and nitric acid. Here, it is possible to strictly control an etched depth L2 of the bottom recessed part 6, because the etching rate varies depending on the density of impurities in the silicon substrate. This fact means that only the P+ type silicon substrate 2 can be etched. As a result, it can be realized to accurately adjust a base width L3 (FIG. 2) as compared with a conventional transistor having lateral devices of which the base width varies according to a measurement error by lithography.
Subsequent to the bottom recessed part 6, a collector region 8 (P+ type) which acts as bottom face region is formed in such a manner that it reaches the P+ type diffusion layer 31 (FIG. 4B). Implantation of impurities and thermal diffusion are performed again to form the collector region 8. Thereafter, the bottom recessed part 6 is provided with a recess insulating layer 19 (FIG. 4C). Furthermore, a collector electrode 41, an emitter electrode 42 and a base electrode 43 are attached to the P+ type diffusion layer 31, the emitter layer 32 and the N+ type diffusion layer 33, respectively. This is followed by forming a passivation film 50 on the top face of the transistor, so that the PNP transistor shown in FIG. 2 is obtained.
In the embodiment described above, the collector region 8 is formed from the bottom recessed part 6, enabling the three-dimensional structure of the device (vertical device) to be obtained readily. Further, contrary to the conventional vertical transistor shown in FIG. 1, there is no need to lay the P+ type buried layer 77 between the N- type epitaxially grown layer 4 and the P+ type silicon substrate 2 (FIG. 1B). This is because, in this embodiment, formation of the collector region 8 is already completed prior to the epitaxial growth and, therefore, it is possible to prevent impurities in the collector region 8 from redistributing.
Moreover, the P+ type silicon substrate 2 which borders on the collector region 8 is removed by forming the bottom recessed part 6, so that parasitic capacitance resulting from a pn junction is avoided. In addition, this method does not allow the P+ type silicon substrate 2 to be formed thin throughout, partly providing the substrate 2 with the bottom recessed part 6, and so the resulting semiconductor device holds a sufficient strength.
FIGS. 5A and 5B show other semiconductor devices manufactured in a similar manner. A vertical NPN type transistor is shown in FIG. 5A, and a pinch resistor is illustrated in FIG. 5B.
The vertical NPN type transistor in FIG. 5A have a structure in which the N- type epitaxially grown layer 4 is formed on the P+ type silicon substrate 2, the N+ type diffusion layer 60 being formed in the epitaxially grown layer 4. In addition, the base layer 61 (P type), in which the emitter layer 62 (N+ type) is provided, is formed in the surface of the epitaxially grown layer 4. In the method for manufacturing the conventional NPN type transistor, antimony or the like is used as impurities for the buried layer in order to suppress the redistribution of the diffusion layer due to epitaxial growth. The diffusion layer of antimony, however, does not allow a satisfactory crystallinity, with the result that the reliability of the resulting transistor product is suppressed. On the contrary, the NPN type transistor shown in FIG. 5A does not need antimony or the like as impurities, thus overcoming the above-mentioned problem.
In FIG. 5B, diffusion layers 63 and 64, and elements 65 and 66 are formed as P+ type and N+ type, respectively.
In the semiconductor device of the present invention and the method of manufacture thereof of the present invention, the bottom face region is formed from the bottom recessed part, being placed under the top face region. Forming circuit elements in the bottom face region and the top face region, therefore, may allow easier process to obtain the semiconductor device having the circuit elements as a three-dimensional structure. Moreover, there is no need to perform epitaxial growth after a buried layer or the like is formed. Consequently, redistribution due to epitaxial growth can be avoided, the semiconductor device being prevented from increasing in size. Further, the bottom face region is formed from the bottom recessed part, so that the interface area of the bottom face region with the semiconductor substrate is reduced. As a result, parasitic capacitance resulting from a pn junction can be avoided, and so a high-speed device is realized.
Also, this method does not allow the semiconductor substrate to be formed thin throughout, partly providing the substrate with the bottom recessed part. As a result, the semiconductor device holds a sufficient strength, allowing the reliability of the resulting product to be improved.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4772929 *Jan 9, 1987Sep 20, 1988Sprague Electric CompanyHall sensor with integrated pole pieces* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5739067 *Dec 7, 1995Apr 14, 1998Advanced Micro Devices, Inc.Method for forming active devices on and in exposed surfaces of both sides of a silicon waferUS5753537 *Jan 31, 1997May 19, 1998U.S. Philips CorporationMethod of manufacturing a semiconductor device for surface mountingUS6696711 *Apr 12, 2002Feb 24, 2004Renesas Technology CorporationSemiconductor device and power amplifier using the sameUS7001819Jan 5, 2004Feb 21, 2006Renesas Technology Corp.Semiconductor device and power amplifier using the sameUS7282753 *Sep 22, 2006Oct 16, 2007The United States Of America As Represented By The Secretary Of The NavyVertical conducting power semiconducting devices made by deep reactive ion etchingUS7825440 *Dec 29, 2005Nov 2, 2010Hrl Laboratories, LlcSuspended-membrane/suspended-substrate monolithic microwave integrated circuit modulesUS8426290Sep 22, 2010Apr 23, 2013Hrl Laboratories, LlcSuspended-membrane/suspended-substrate monolithic microwave integrated circuit modulesWO1996003772A2 *Jul 5, 1995Feb 8, 1996Philips Electronics NvMethod of manufacturing a semiconductor device for surface mounting, and semiconductor device for surface mountingWO2009071493A1 *Nov 28, 2008Jun 11, 2009Thales SaSchottky diode for high-power application and method for making same* Cited by examinerClassifications U.S. Classification257/623, 257/536, 257/621, 257/618, 257/E21.363, 257/E29.022, 257/626, 257/E29.183, 257/E21.375International ClassificationH01L21/761, H01L21/331, H01L21/329, H01L21/76, H01L29/06, H01L29/73, H01L29/732Cooperative ClassificationH01L29/732, H01L29/66166, H01L29/0657, H01L29/66272European ClassificationH01L29/66M6D4, H01L29/66M6T2U, H01L29/732, H01L29/06CLegal EventsDateCodeEventDescriptionJan 4, 2005FPAYFee paymentYear of fee payment: 12Jan 11, 2001FPAYFee paymentYear of fee payment: 8Jan 21, 1997FPAYFee paymentYear of fee payment: 4May 7, 1992ASAssignmentOwner name: ROHM CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:SHIMOJI, NORIYUKI;TAKASU, HIDEMI;REEL/FRAME:006101/0658;SIGNING DATES FROM 19920224 TO 19920226RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google