Source: http://www.google.com/patents/US5162788?ie=ISO-8859-1&dq=6,202,008
Timestamp: 2015-03-30 09:28:48
Document Index: 233625514

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Patent US5162788 - Chunky planar data packing apparatus and method for a video memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn apparatus and method for taking data that is presented on a NUBUS in NUBUS format and writing it into a video memory in chunky planar format, is described. The present invention is also useful for performing RGB reads wherein video data is read from the video memory in chunky planar format and is...http://www.google.com/patents/US5162788?utm_source=gb-gplus-sharePatent US5162788 - Chunky planar data packing apparatus and method for a video memoryAdvanced Patent SearchPublication numberUS5162788 APublication typeGrantApplication numberUS 07/368,379Publication dateNov 10, 1992Filing dateJun 16, 1989Priority dateJun 16, 1989Fee statusPaidPublication number07368379, 368379, US 5162788 A, US 5162788A, US-A-5162788, US5162788 A, US5162788AInventorsJames A. Lundblad, Mohammed Sriti, Anthony D. MastersonOriginal AssigneeApple Computer, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (3), Classifications (11), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetChunky planar data packing apparatus and method for a video memory
US 5162788 AAbstract
An apparatus and method for taking data that is presented on a NUBUS in NUBUS format and writing it into a video memory in chunky planar format, is described. The present invention is also useful for performing RGB reads wherein video data is read from the video memory in chunky planar format and is translated into NUBUS format for transmission across the NUBUS. The apparatus comprises a data format translator which is coupled to the NUBUS for translating the RGB data from NUBUS format to chunky planar format. The translated RGB data in chunky planar format is compressed and rearranged as compared to the NUBUS format--resulting in a more efficient utilization of video memory space. An address generator is also coupled to the video memory for calculating the address location in the video memory where the translated RGB data is to be written. The address location is derived from the NUBUS address according to the formula Nstart =(3*NAD/4) where Nstart is the start address in video memory and NAD represents the NUBUS address from which the RGB data to be translated is obtained.
1. In a computer providing a video signal to a monitor for display thereon, said computer including a bus coupling a central processing unit (CPU) to a video memory, an apparatus for writing red, green and blue (RGB) data supplied from said bus in a bus format into said video memory in a video memory format, said RGB data in the bus format including a series of words, each word including a red byte, a green byte, and a blue byte, said apparatus comprising:data format translation means coupled to said bus for translating said RGB data from the bus format to the video memory format, the translated RGB data in said video memory format being rearranged as compared to said bus format so that within each block of said video memory format, a first word includes only red bytes, a second word includes only green bytes, and a third word includes only blue bytes; address generator means coupled to said bus for calculating the address location in said video memory where said translated RGB data is written; and control means for controlling said translation means and said address generator means. 2. The apparatus of claim 1, wherein said address generator means includes calculating means for calculating a start address in said video memory according to the formula Nstart =(3*Addr /4) where Nstart represents said start address in said video memory and Addr represents the destination address provided on said bus for a word of said block. 3. The apparatus of claim 2, wherein said bus comprises a NUBUS.
4. In a computer providing a video signal to a monitor for display thereon, said computer including a bus coupling a central processing unit (CPU) to a video memory having 32-bit words and a block defined by 3 words each having 4 bytes in a video memory format in which a first word includes only red bytes, a second word includes only green bytes, and a third word includes only blue bytes an apparatus for reading red, green and blue (RGB) data from said video memory in the video memory format to said bus in a bus format comprising:data format translation means coupled to said bus for translating said RGB data stored in said video memory format in said video memory to the bus format in which each word includes a red byte, a green byte, and a blue byte; address generator means coupled to said bus and data format translation means for calculating the address location in said video memory where said translated RGB data is read; and control means for controlling said translation means and said address generator means. 5. The apparatus of claim 4, wherein said address generator means includes calculating means for calculating a start address in said video memory according to the formula Nstart =(3*Addr /4) where Nstart represents said start address in said video memory and Addr represents the destination address provided on said bus for a word of said block. 6. The apparatus of claim 5, wherein said bus comprises a NUBUS.
7. In a computer providing display of red, green and blue (RGB) video data on a CRT monitor, an apparatus for writing said RGB data from a NUBUS format in which each word includes a red byte, a green byte, and a blue byte to a video memory in chunky planar format in which a first word includes only red bytes, a second word includes only green bytes, and a third words includes only blue bytes said apparatus comprising:a data format translator having a plurality of input multiplexers for receiving said RGB data from the byte lanes of said NUBUS, a plurality of latches coupled to said input multiplexers for separately storing individual bytes of said RGB data, and a plurality of output multiplexers coupling said latches to said video memory, said translator providing one of said individual bytes to said video memory during a memory cycle; a red, green and blue (RGB) address generator for calculating an address location in said video memory where said individual byte is to be written, said address location being derived from a start address in said video memory according to the formula Nstart =(3*NAD(20:2)/4) where Nstart represents its start address in said video memory and NAD represents the destination address provided on the NUBUS for the first word of a block of video memory; and control means for controlling said translator and said generator. 8. The apparatus according to claim 7, wherein said RGB address generator further comprisesincrementing means for incrementing said start address to obtain the next address in said video memory for the storage of the next of said individual bytes in the next word of video memory. 9. In a computer providing a display of red, green and blue (RGB) video data on a CRT monitor, an apparatus for reading said RGB data from a video memory in a chunky planar format in which a first word includes only red byes, a second word includes only green bytes, and a third word includes only blue bytes, to a NUBUS in NUBUS format in which each word includes a red byte, a green byte, and a blue byte, said apparatus comprising:a data format translator having a plurality of input multiplexers for receiving said RGB data from said video memory, a plurality of latches coupled to said input mulitplexers for separately storing individual bytes of said RGB data, and a plurality, of output multiplexers coupling said latches to said NUBUS; a red, green and blue (RGB) address generator for calculating the address location in said video memory where said individual byte is to be read from, said address location being derived from a start address in said video memory according to the formula Nstart =3*NAD(20:2)/4) where Nstart represents said start address in video memory and NAD represents the source address provided on the NUBUS for the first word of a block of video memory to be read; and control means for controlling said translator and said generator. 10. The apparatus according to claim 9, wherein said RGB address generator further comprises incrementing means for incrementing said start address in video memory to obtain the next address in said video memory for reading the next of said individual bytes.
11. In a computer providing a video display signal, a method of writing red, green and blue (RGB) data presented on a bus in a bus format in which each word includes a red byte, a green byte, and a blue byte into a video memory in a series of words in chunky planar format in which a block of memory is defined by a first word that includes only first color bytes, a second word that includes only second color bytes, and a third word that includes only third color bytes, said method comprising the steps of:(a) receiving a destination address from said bus; (b) translating said destination address to a start address for said video memory, according to the formula Nstart =(3*Addr /4) where Nstart is said start address of a block of said video memory and Addr is said destination address provided by said bus; (c) obtaining a word of said RGB data from said bus; (d) initiating a memory cycle to write the first color byte of said RGB data into said video memory using said start address; (e) sequencing said start address to produce a second address of a second word in video memory; (f) initiating a memory cycle to write the second color byte of said RGB data into said video memory using said second address; and (g) sequencing said second address to produce a third address of a third word in video memory; (h) initiating a memory cycle to write the third color byte of said RGB data into said video memory using said third address. 12. The method according to claim 11 further comprising the step of:(h) repeating steps (a) through (h) for a next destination address provided by said bus and next RGB data. 13. The method according to claim 12, wherein said bus comprises a NUBUS.
14. In a computer providing a video display signal in which red, green and blue (RGB) data is stored in a video memory in a series of words in a chunky planar format in blocks defined by a first word that includes only first color bytes, a second word that includes only second color bytes, and a third word that includes only third color bytes, a method of reading said RGB data from said memory, and providing it to a bus in a bus format in which each word includes a red byte, a green byte, and a blue byte, comprising the steps of:(a) receiving a source address from said bus for the block of RGB data to be read from video memory; (b) translating said source address to a start address for said video memory, according to the formula Nstart =3*(Addr /4) where Nstart is said address of a block in said video memory and Addr is said source address provided by said bus; (c) initiating a memory cycle at said start address to obtain a first byte of said RGB data from said memory; (d) sequencing said start address to produce a second address of a second word in video memory; (e) initiating a memory cycle at said second address to obtain a second byte of said RGB data from said memory; p1 (f) repeating steps (d) and (e) to obtain a third address and a third byte of said RGB data; (g) presenting said first, second and third bytes to said bus. 15. The method according to claim 14, wherein said bus is a NUBUS.
16. In a computer providing a video signal coupled to a CRT monitior for display thereon, said computer having a NUBUS bus coupling a CPU to a video memory, a method of packing red, green and blue (RGB) video data presented on said NUBUS on a block in said video memory in an efficient manner so as to eliminate vacancies of data in said memory, said method reorganizing said video memory into blocks having a first word, a seocond word, and a third word, and also having bytes lanes defined by bytes in said words, said method comprising the steps of:(a) calculating a start address for a first word of a block in said memory from a NUBUS address provided by said NUBUS for the destination of the RGB video data; (b) writing a first byte of said RGB data to an appropriate byte lane of said memory in said first word; (c) writing a second byte of said RGB data to said appropriate byte lane of said second word of said block of video memory; and (d) writing a third byte of said RGB data to said appropriate byte lane of siad third word of said block of video memory. 17. The method according to claim 16, wherein said start address is calculated in step (a) according to the formula Nstart =(3*NAD(20:2)/4) where Nstart is said start address of said block in said video memory and NAD is said NUBUS address provided by said bus for the destination of the RGB data. 18. The method of claim 16, further comprising the step of:(e) repeating steps (a) through (d) until the block is fillled with RGB data, so that the first word in video memory contains data for a first color, the second word contains data for a second color, and third word contains data for a third color. Description
This invention relates to the field of semiconductor memories; in particular, to the packing of video data in those memories.
Video random-access memories (VRAMs) have recently found widespread use in microprocessor-based computers providing video graphics signals. These VRAMs are commonly incorporated into a video card which is coupled to the central processing unit (CPU) which is located on the motherboard of the computer. Such a video card is described in co-pending application Ser. No. 07/027,847, filed Mar. 19, 1987, entitled "Video Apparatus Employing VRAMs", which is assigned to the assignee of the present invention.
For bit-mapped graphics applications, each atomic position in the graphical display is called a "pixel", and each pixel itself has a unique address. Pixel data can be any length ranging from one to any finite number of bits. The addressing space in bit-mapped graphics is referred to as row and column indexes. A typical CRT display is a 640�400 pixel array, with a black and white pixel being represented as 1-bit, and a color pixel as a plurality of bits. According to this method the individual memory locations are referenced by their VRAM position in the addressing space.
An apparatus and method for taking data that is presented on a 32-bit bus (e.g., NUBUS) in one format and writing it into a video memory in chunky planar format, is described. The present invention is also useful for performing RGB reads wherein video data is read from the video memory in chunky planar format and is translated into NUBUS format for transmission across the NUBUS. Chunky planar format represents a more efficient way of packing data in video memory to eliminate vacancies in the sequence of bytes.
An address generator is also coupled to the video memory for calculating the address location in the video memory where the translated RGB data is to be written. The address location is derived from the NUBUS address according to the formula Nstart =(3*NAD/4) where Nstart is the start address in video memory and NAD represents the NUBUS address from which the RGB data to be translated is obtained. Control logic coupled to both the translator and the address generator controls the operation of the apparatus so that a single byte is translated in a single memory cycle.
An apparatus and method for taking data that is presented on a 32-bit bus and packing it into video memory in a more efficient manner is described. In the preferred embodiment, the 32-bit bus coupled to the presently invented apparatus is a NUBUS. However, it should be understood that other 32-bit buses, having other associated formats, could also be used without departing from the spirit or scope of the present invention.
According to the present invention, the four bytes stored in NUBUS byte lane 1 (e.g., R0, R1, R2 and R3) are rearranged and stored in a single word of video memory; for example, at start address Nstart. Arrow 52 depicts how byte lane 1 of NUBUS block 50 is translated into address location Nstart of memory block 51. In a similar manner, NUBUS byte lane 2, containing green video data, is packed into address location Nstart+1, as shown by arrow 53. Arrow 54 illustrates how byte lane 3, containing blue color information, is translated to address location Nstart+2.
Essential to the operation of the currently preferred embodiment of the present invention is that each NUBUS address is translated to a start address in video memory according to a certain algorithm. In the algorithm, the NUBUS address is first divided modulo 4 and then multiplied by 3. Mathematically, this operation can be written as Nstart =(3* NAD/4), where Nstart represents the start address in memory and NAD is the NUBUS address.
Next, the video memory address is incremented to Nstart+1 and another memory cycle is performed. This transfers the byte corresponding to G0 from NUBUS block 50 to byte lane 0 of address location Nstart+1. The third memory cycle transfers the byte B0 to byte lane 0 at address location Nstart+2. The entire process is repeated for NUBUS address locations 1, 2 and 3 to fill the remaining portions of video memory block 51. (Because of the integer nature of the division in the above algorithm, it is appreciated that the start address for each NUBUS address in block 50 is zero.)
Consider the situation in which packing unit 12 begins translating data from the base of the NUBUS. In this case, the start address is going to be the first location in memory. In other words, there is always a correspondence between address 0 in the NUBUS and address 0 in video memory. The first four locations on the NUBUS, e.g., words 0, 1, 2 and 3, always have a start address of 0 in the video memory since the data that is to be transferred is simply R0, R1, R2, R3, G0, G1, G2, G3, etc. A new start address will not be generated until the NUBUS increments beyond the first four words. After the first block of NUBUS data has been packed into the video memory, translation of the second block--containing addresses 4, 5, 6 and 7--may proceed. For the second block, the correct start address for the next translation is the third word in memory, i.e., Nstart+3, as shown in FIG. 3.
When calculating the start address for translation, blocks 100 and 101 select paths B to C and A to B, respectively. In this way the address provided by bits 4 through 20 of bus 40 is multiplied by 1/2 and also multiplied by 1/4. Adding the quantities on line 103 and 104 produces an address which is 3 times the NUBUS address divided by 4 (i.e., Nstart =(3*NAD/4)). This result is provided by adder 102 on line 114, which is then presented to register 105. Thus, line 112 contains the primary address bus bits 20 through 2. This start address is buffered from bus 15 by buffer 110. Primary address bus 15 combines the address information on line 112 and line 113 to produce the start and byte lane information needed for the address location in video memory.
To calculate the next address location in memory all that needs to be done is to add 1-word, i.e., Nstart+1. This is accomplished by the feedback connection of line 112 back to the A input of block 100. After the start path from input A-to-C. In other words the start address is transferred from line 112 to line 103. At the same time the multiplexer in block 100 selects the path which transfers the constant 4 to the output B on line 104. Therefore, adder 102 adds the start address plus 4 (i.e., 4 bytes) to produce the next memory address in the sequence, i.e., Nstart+1, on line 114. The upper order bits are then combined with the lower order bits on primary address bus 15 as described above.
First, the address is obtained from the NUBUS and translated into the start address Nstart and a memory cycle is initiated. That memory cycle produces a byte from memory. Another memory cycle is then initiated using the next address Nstart+1. As the data bytes are read from video memory 13 they are provided to the translator 26 within packing unit 12 along bidirectional bus 14. These data bytes are then translated and presented to the NUBUS.
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