Source: http://www.google.com/patents/US7382142?dq=7751826
Timestamp: 2016-05-24 15:05:28
Document Index: 528236973

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'art 1']

Patent US7382142 - High density interconnect system having rapid fabrication cycle - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises...http://www.google.com/patents/US7382142?utm_source=gb-gplus-sharePatent US7382142 - High density interconnect system having rapid fabrication cycleAdvanced Patent SearchPublication numberUS7382142 B2Publication typeGrantApplication numberUS 11/133,021Publication dateJun 3, 2008Filing dateMay 18, 2005Priority dateMay 23, 2000Fee statusPaidAlso published asUS7872482, US7884634, US20050275418, US20080246500, US20090153165, WO2005115068A2, WO2005115068A3, WO2005115068A8Publication number11133021, 133021, US 7382142 B2, US 7382142B2, US-B2-7382142, US7382142 B2, US7382142B2InventorsFu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui ShanOriginal AssigneeNanonexus, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (101), Non-Patent Citations (99), Referenced by (19), Classifications (15), Legal Events (9) External Links: USPTO, USPTO Assignment, EspacenetHigh density interconnect system having rapid fabrication cycle
US 7382142 B2Abstract
An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
This Application claims priority to U.S. Provisional Application No. 60/573,541, entitled Quick-Change Probe Chip, filed 20 May 2004; U.S. Provisional Application No. 60/592,908, entitled Probe Card Assembly with Rapid Fabrication Cycle, filed 29 Jul. 2004; and U.S. Provisional Application No. 60/651,294, entitled Nano-Contactor Embodiments for IC Packages and Interconnect Components, filed 8 Feb. 2005.
The invention relates generally to the field of semiconductor wafer testing utilizing probe card assembly systems for testing one or more die on a wafer. More particularly, the invention relates to probe card assembly systems incorporating microfabricated probe tips and improvements thereto, which improve the performance, ease of use and lower the cost of ownership.
Probe card assembly systems are used in integrated circuit (IC) manufacturing to translate electrical signal paths from the tightly spaced electrical interconnection pads on ICs to the coarsely spaced electrical interconnection pads on printed circuit boards that interface to IC test systems.
In probe card assembly systems according to Eldridge et al (e.g. U.S. Pat. Nos. 6,624,648 and 5,974,662, parallelism errors between their probe tips and the semiconductor wafer are corrected by adjusting the orientation of a space transformer using multiple ball tipped linear actuators. The space transformer also serves as the support substrate for composite probe elements fabricated as described in the patent specification, each of which are individually mounted on the space transformer. Eldridge et al state that an object of their invention is that the space transformer, and hence, the tips of their elongate resilient probe elements can be “oriented without changing the position of the probe card”.
A Precision Point VX probe card measurement tool, available through Applied Precision, LLC, of Issaquah, Wash., is capable of measuring parallelism error between the probe tips and the mounting surface of a probe card by measuring the relative “Z height” of each individual probe tip on the probe card through a measurement of the electrical conductivity between the probe tips and a highly polished electrically conductive tungsten surface of a so called checkplate. In order to obtain planarity measurements with the Precision Point VX that are accurate to within the manufacturers specification of 0.1 mils (2.5 microns) across the full X and Y dimensions of the checkplate, the parallelism between the checkplate and the “Support Plate” which holds the probe card “Mother Board” must be mechanically adjusted following a procedure specified by the manufacturer and referred to as the “Fine Leveling calibration procedure.” Because the reference surface on the “Mother Board” may be different for the Precision Point VX and a wafer prober, it is necessary to perform the fine leveling procedure or else significant errors may be introduced into the planarity measurement.
An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly for establishing electrical connections to a semiconductor wafer mounted in a semiconductor wafer prober. The probe card interface assembly comprises a mother board having an upper surface and a lower planar mounting surface opposite the upper surface and parallel to the semiconductor wafer, a reference plane defined by a least three points located between the lower surface of the motherboard and the semiconductor wafer, at least one component having an upper mounting surface located below the motherboard mounting surface and a lower mounting surface opposite the upper mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the semiconductor wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the probe card interface assembly, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
FIG. 1 is a system diagram of a complete system for testing semiconductor wafers including an IC tester and a probe card assembly installed in a wafer prober;
Introductory disclosure regarding structures, processes and systems disclosed herein is seen in: U.S. Provisional Application No. 60/136,636, entitled Wafer Interface for High Density Probe Card, filed 27 May 1999; U.S. Provisional Application No. 60/146,241, entitled Method of Massively Parallel Testing of Circuits, filed 28 Jul. 1999; U.S. Provisional Application No. 60/573,541, entitled Quick-Change Probe Chip, filed 20 May 2004; U.S. Provisional Application No. 60/592,908, entitled Probe Card Assembly with Rapid Fabrication Cycle, filed 29 Jul. 2004; U.S. Provisional Application No. 60/651,294, entitled Nano-Contactor Embodiments for IC Packages and Interconnect Components, filed 8 Feb. 2005; U.S. patent application Ser. No. 10/870,095, entitled Enhanced Compliant Probe Card Systems Having Improved Planarity, US Filing Date 16 Jun. 2004; U.S. patent application Ser. No. 10/178,103, entitled Construction Structures and Manufacturing Processes for Probe Card Assemblies and Packages Having Wafer Level Springs, US Filing Date 24 Jun. 2002; U.S. patent application Ser. No. 09/980,040, entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date 27 Nov. 2001; PCT Patent Application Serial No. PCT/US00/21012, filed 27 Jul. 2000; PCT Patent Application Serial No. PCT/US00/14164, entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date 23 May 2000; and U.S. patent application Ser. No. 10/069,902, entitled Systems for Testing and Packaging Integrated Circuits, filed 28 Jun. 2002, which is incorporated herein in its entirety by this reference thereto.
FIG. 12 is a perspective view of quick-change probe card system 110 having a Probe Chip 68 having back side pads 278 (FIG. 14) soldered to a Z-bock 134. The Z-block 134 is maintained in electrical contact with the probe card motherboard 32 through an intermediate connector 136, such as an interposer 136, e.g. 136 a,136 b. The Z-block 134 substrate 163 (FIG. 9) preferably comprises a material with a high elastic modulus and good electrical insulating qualities, such as a ceramic, a multilayered ceramic, and/or a co-fired ceramic. The flange 178 typically comprises a metal, such as any metal with a good thermal coefficient of expansion (TCE) match to the Z-Block substrate 163. In an exemplary Z-block 134 substrate 163, candidate flange materials include titanium, titanium alloys, Invar™, or Covar™.
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