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Timestamp: 2014-03-17 11:02:56
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Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US7720444 - Adaptive radio transceiver with a local oscillator - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including...http://www.google.com/patents/US7720444?utm_source=gb-gplus-sharePatent US7720444 - Adaptive radio transceiver with a local oscillatorAdvanced Patent SearchPublication numberUS7720444 B2Publication typeGrantApplication numberUS 11/340,038Publication dateMay 18, 2010Filing dateJan 26, 2006Priority dateOct 21, 1999Fee statusPaidAlso published asUS6404293, US6417737, US6608527, US7031668, US7555263, US7970358, US8041294, US20030042984, US20030067359, US20060205374, US20090286487, US20100295598Publication number11340038, 340038, US 7720444 B2, US 7720444B2, US-B2-7720444, US7720444 B2, US7720444B2InventorsHooman Darabi, Ahmadreza Rofougaran, Maryam RofougaranOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (71), Non-Patent Citations (1), Referenced by (4), Classifications (28), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetAdaptive radio transceiver with a local oscillatorUS 7720444 B2Abstract An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
a first oscillator configured to generate a first signal having a first frequency,
a first mixer configured to mix the first signal and the second signal to produce a third signal having a third frequency;
a transmitter having a second mixer configured to mix the third signal and a fourth signal; and
wherein the first oscillator comprises a voltage controlled oscillator,
wherein the local oscillator comprises a phase locked loop configured to control the first frequency of the first signal generated by the voltage controlled oscillator,
wherein the second frequency divider is operatively coupled to the second oscillator,
wherein the voltage controlled oscillator is phase locked to an output of the second frequency divider,
wherein the second frequency divider comprises a programmable divisor input,
2. The wireless communications device according to claim 1, wherein the first oscillator, the frequency divider, the first mixer and the second mixer are each quadrature.
3. The wireless communications device according to claim 1, wherein the third frequency comprises a sum of the first frequency and the second frequency.
4. The wireless communications device according to claim 1, wherein the fourth signal comprises a baseband signal.
5. The wireless communications device according to claim 1, wherein the frequency divider is programmable.
6. The wireless communications device according to claim 1, wherein the wireless communications device performs orthogonal frequency division multiplexing.
7. The wireless communications device according to claim 1, wherein the wireless communications device performs spread spectrum modulation.
8. The wireless communications device according to claim 1, wherein the wireless communications device performs frequency hopping.
9. The wireless communications device according to claim 1, wherein the wireless communications device performs direct sequence spread spectrum modulation.
10. The wireless communications device according to claim 1, wherein the local oscillator and the transmitter are integrated on a single integrated circuit chip.
11. The wireless communications device according to claim 1, wherein the local oscillator or the transmitter is integrated on an integrated circuit chip.
12. The wireless communications device according to claim 1, wherein the local oscillator employs CMOS technology.
13. The wireless communications device according to claim 1, wherein the transmitter employs CMOS technology.
14. The wireless communications device according to claim 1, wherein the transmitter and the local oscillator employ CMOS technology.
15. The wireless communications device according to claim 1, wherein the wireless communications device can be programmed to support a plurality of different wireless spread spectrum modulation techniques.
16. The wireless communications device according to claim 1, wherein the wireless communications device supports a plurality of different wireless spread spectrum modulation techniques.
17. The wireless communications device according to claim 1, wherein the wireless communications device supports wireless communications using orthogonal frequency division multiplexing and wireless communications using spread spectrum modulation.
18. The wireless communications device according to claim 1, wherein the wireless communications device supports wireless communications using orthogonal frequency division multiplexing and wireless communications using direct sequence spread spectrum modulation.
19. The wireless communications device according to claim 1, wherein the wireless communications device supports wireless communications using orthogonal frequency division multiplexing and wireless communications using frequency hopping.
20. The wireless communications device according to claim 1, wherein the wireless communications device supports wireless communications using orthogonal frequency division multiplexing, wireless communications using frequency hopping and wireless communications using direct sequence spread spectrum modulation.
21. A wireless spread spectrum communications device, comprising:
22. The device according to claim 21, comprising:
23. A wireless communications device, comprising:
a receiver having a third mixer configured to mix the third signal and a fifth signal with a first control signal applied to the programmable divisor input, wherein the third signal and the fourth signal are mixed by the second mixer with a second control signal applied to the programmable divisor input, and wherein the second control signal is different from the first control signal.
24. The device according to claim 21, wherein the device performs orthogonal frequency division multiplexing.
25. The device according to claim 21, wherein the device performs frequency hopping.
26. The device according to claim 21, wherein the device performs direct sequence spread spectrum modulation.
27. The device according to claim 21, wherein the local oscillator and the transmitter are integrated on a single integrated circuit chip.
28. The device according to claim 21, wherein the local oscillator or the transmitter is integrated on an integrated circuit chip.
29. The device according to claim 21, wherein the local oscillator employs CMOS technology.
30. The device according to claim 21, wherein the transmitter employs CMOS technology.
31. The device according to claim 21, wherein the transmitter and the local oscillator employ CMOS technology.
32. The device according to claim 21, wherein the device can be programmed to support a plurality of different wireless spread spectrum modulation techniques.
33. The device according to claim 21, wherein the device supports a plurality of different wireless spread spectrum modulation techniques.
34. The device according to claim 21, wherein the device supports wireless communications using orthogonal frequency division multiplexing and wireless communications using spread spectrum modulation.
35. The device according to claim 21, wherein the device supports wireless communications using orthogonal frequency division multiplexing and wireless communications using direct sequence spread spectrum modulation.
36. The device according to claim 21, wherein the device supports wireless communications using orthogonal frequency division multiplexing and wireless communications using frequency hopping.
37. The device according to claim 21, wherein the device supports wireless communications using orthogonal frequency division multiplexing, wireless communications using frequency hopping and wireless communications using direct sequence spread spectrum modulation.
38. The device according to claim 23, wherein the device performs orthogonal frequency division multiplexing.
39. The device according to claim 23, wherein the device performs frequency hopping.
40. The device according to claim 23, wherein the device performs direct sequence spread spectrum modulation.
41. The device according to claim 23, wherein the local oscillator and the transmitter are integrated on a single integrated circuit chip.
42. The device according to claim 23, wherein the local oscillator or the transmitter is integrated on an integrated circuit chip.
43. The device according to claim 23, wherein the local oscillator employs CMOS technology.
44. The device according to claim 23, wherein the transmitter employs CMOS technology.
45. The device according to claim 23, wherein the transmitter and the local oscillator employ CMOS technology.
46. The device according to claim 23, wherein the device can be programmed to support a plurality of different wireless spread spectrum modulation techniques.
47. The device according to claim 23, wherein the device supports a plurality of different wireless spread spectrum modulation techniques.
48. The device according to claim 23, wherein the device supports wireless communications using orthogonal frequency division multiplexing and wireless communications using spread spectrum modulation.
49. The device according to claim 23, wherein the device supports wireless communications using orthogonal frequency division multiplexing and wireless communications using direct sequence spread spectrum modulation.
50. The device according to claim 23, wherein the device supports wireless communications using orthogonal frequency division multiplexing and wireless communications using frequency hopping.
51. The device according to claim 23, wherein the device supports wireless communications using orthogonal frequency division multiplexing, wireless communications using frequency hopping and wireless communications using direct sequence spread spectrum modulation.
CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of application Ser. No. 10/165,464, filed Jun. 7, 2002 now U.S. Pat. No. 7,031,668 which is a continuation of application Ser. No. 09/691,633, filed Oct. 18, 2000, now issued U.S. Pat. No. 6,404,293 B1, which is a continuation of co-pending application Ser. No. 09/634,552, filed Aug. 8, 2000, which claims priority to and benefit from provisional Application No. 60/160,806, filed Oct. 21, 1999; Application No. 60/163,487, filed Nov. 4, 1999; Application 60/163,398, filed Nov. 4, 1999; Application No. 60/164,442, filed Nov. 9, 1999, Application No. 60/164,194, filed Nov. 9, 1999; Application No. 60/164,314, filed Nov. 9, 1999; Application No. 60/165,234, filed Nov. 11, 1999; Application No. 60/165,239, filed Nov. 11, 1999; Application No. 60/165,356, filed Nov. 12, 1999; Application No. 60/165,355, filed Nov. 12, 1999; Application No. 60/172,348, filed Dec. 16, 1999; Application No. 60/201,335, filed May 2, 2000; Application No. 60/201,157, filed May 2, 2000; Application No. 60/201,179, filed May 2, 2000; Application No. 60/202,997, filed May 10, 2000; and Application No. 60/201,330, filed May 2, 2000. The above-identified applications are hereby incorporated herein by reference in their entirety.
This application is also a continuation of co-pending application Ser. No. 09/634,552, filed Aug. 8, 2000, which claims priority to and benefit from provisional Application No. 60/160,806, filed Oct. 21, 1999; Application No. 60/163,487, filed Nov. 4, 1999; Application 60/163,398, filed Nov. 4, 1999; Application No. 60/164,442, filed Nov. 9, 1999, Application No. 60/164,194, filed Nov. 9, 1999; Application No. 60/164,314, filed Nov. 9, 1999; Application No. 60/165,234, filed Nov. 11, 1999; Application No. 60/165,239, filed Nov. 11, 1999; Application No. 60/165,356, filed Nov. 12, 1999; Application No. 60/165,355, filed Nov. 12, 1999; Application No. 60/172,348, filed Dec. 16, 1999; Application No. 60/201,335, filed May 2, 2000; Application No. 60/201,157, filed May 2, 2000; Application No. 60/201,179, filed May 2, 2000; Application No. 60/202,997, filed May 10, 2000; and Application No. 60/201,330, filed May 2, 2000.
Transceivers have a wide variety of applications ranging from low data rate wireless applications (such as mouse and keyboard) to medium data rate Bluetooth and high data rate wireless LAN 802.11 standards. However, due to the high cost, size and power consumption of currently available transceivers, numerous applications are not being fully commercialized. A simplified architecture would make a transceiver more economically viable for wider applications and integration with other systems. The integration of the transceiver into a single integrated circuit (IC) would be an attractive approach. However, heretofore, the integration of the transceiver into a single IC has been difficult due to process variations and mismatches. Accordingly, there is a need for an innovative transceiver architecture that could be implemented on a single IC, or alternatively, with a minimum number of discrete off chip components that compensate for process variations and mismatches.
FIG. 11 is a graphical depiction of the frequency response of the modified biquad stage of FIG. 10 accordance with an exemplary embodiment of the present invention;
FIG. 12( b) is an electrical diagram of to tunable array of resistors in accordance with an exemplary embodiment of the present invention;
FIG. 34 is a block diagram of a wide tuning range voltage controlled oscillator (VCO in accordance with an exemplary embodiment of the present invention;
DETAILED DESCRIPTION Exemplary Embodiments of a Transceiver In accordance with an exemplary embodiment of the present invention, a transceiver utilizes a combination of frequency planning, circuit design, layout and implementation, differential signal paths, dynamic calibration, and self tuning to achieve robust performance over process variation and interference. This approach allows for the full integration of the transceiver onto a single IC for a low cost, low power, reliable and more compact solution. This can be achieved by (I) moving external bulky and expensive image reject filters, channel select filters, and balms onto the chip; (2) reducing the number of off-chip passive elements such as capacitors, inductors, and resistors by moving them onto the chip; and (3) integrating all the remaining components onto the chip. As those skilled in the art will appreciate, the described exemplary embodiments of the transceiver do not require integration into a single IC and may be implemented in a variety of ways including discrete hardware components.
The self testing unit 18 generates test signals with different amplitudes and frequency ranges. The test signals are coupled to the receiver 10, transmitter 12 and LO generator 14 where they are processed and returned to the self-testing unit 18. The return signals are used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver 10, transmitter 12 and LO generator 14. This is accomplished by measuring the strength of the signals output from the self-testing unit 18 against the returned signals over the tested frequency ranges. In an exemplary embodiment of the self-testing unit 18, these measurements can be made with different transceiver parameters by sweeping the output of the controller 16 through its entire calibrating digital range, or alternatively making measurements with the controller output set to a selected few points, by way of example, at the opposite ends of the digital range.
In the described exemplary embodiment, the self testing unit 18 is in communication with the external processing device (not shown) via the control bus 17. During self-test, the external processing device provides programming data to both the controller 16 and the self-testing unit 18. The self testing unit 18 utilizes the programming data used by the controller 16 to set the parameters of the transceiver to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver 10, transmitter 12 and LO generator 14.
FIG. 2 shows a block diagram of the transceiver in accordance with an embodiment of the invention. The described exemplary embodiment is integrated into a single IC. For ease of understanding, each component coupled to the controller is shown with a �program� designation or a �calibration� designation. These designations indicate whether the component is programmed by the controller or calibrated by the controller. In practice, in accordance with the described exemplary embodiment of the present invention, the components that are programmed receive the most significant bits (MSBs) and the components that are calibrated receive the least significant bits (LSBs). The components requiring both programming and calibration receive the entire digital output from the controller. As those skilled in the art will appreciate, any number of methodologies may be used to deliver programming and calibration information to the individual components. By way of example, a single controller bus could be used having the programming and or calibration data with the appropriate component addresses.
The LO generator 14 provides the infrastructure for frequency planning. The LO generator 14 includes an IF clock generator and an RF clock generator. The IF clock generator includes an oscillator 38 operating at a ratio of the RF signal (fOSC). High stability and accuracy can be achieved in a number of ways including the use of a crystal oscillator.
In the described exemplary embodiment, the VCO frequency is sufficiently separated (in frequency) from the RF frequency generated by the transmitter 12 to prevent VCO pulling and injection lock of the VCO. Transmitter leakage can pull the VCO frequency toward the RF frequency and actually cause the VCO to lock to the RF signal if their frequencies are close to each other. The problem is exasperated if the gain and tuning range of the VCO is large. If the frequency of the RF clocks is fLO, then the VCO frequency can be defined as: fVCO=NfLO/(N+1). This methodology is implemented with a divide by N circuit 50 coupled to the output of the VCO 48 in the PLL 43. The output of the VCO 48 and the output of the divide by N circuit 50 are coupled to a complex mixer 52 where they are multiplied together to generate the RF clocks. A filter 53 can be positioned at the output of the complex mixer to remove the harmonics and any residual mixing images of the RF clocks. The divide by N circuit can be programmable via the controller through the select input. For example, if N=2, then fVCO=(⅔) fLO, and if N=3, then fVCO=(�) fLO.
A VCO the frequency set at ⅔ the frequency of the RF clocks works well in the described exemplary embodiment because the transmitter output is sufficiently separated (in frequency) from the VCO frequency. In addition, the frequency of the RF clocks is high enough so that its harmonics and any residual mixing images such as fVCO�1−(1/N)), 3 fVCO�1+(1/N), and 3 fVCO�1−(1/N)) are sufficiently separated (in frequency) from the transmitter output to relax the filtering requirements of the RF clocks. The filtering requirements do not have to be sharp because the filter can better distinguish between the harmonics and the residual images when they are separated in frequency. Programming the divide by N circuit 50 also provides for the quadrature outputs of the divide by N circuit. Otherwise, with an odd number programmed, the outputs of the divide by N circuit 50 would not be quadrature. For an odd number, the divider 50 outputs will be differential, but will not be 90 degrees out of phase, i.e., will not be I-Q signals.
In the described exemplary embodiment, the RF clocks are generated in the LO generator 14. This can be accomplished in various fashions including, by way of example, either generating the RF clocks in the VCO or using a polyphase circuit to generate the RF clocks. Regardless of the manner in which the RF clocks are generated, the mixer 52 will produce a spectrum of frequencies including the sum and difference frequencies, specifically, fVCO�(1(+(1/N)) and its image fVCO�(1−(1/N)). To reject the image, the mixer 52 can be configured as a double quadrature mixer as depicted in FIG. 3. The double quadrature mixer includes one pair of mixers 55, 57 to generate the Q-clock and a second pair of mixers 59, 61 to generate the I-clock. The Q-clock mixers utilizes a first mixer 55 to mix the I output of the VCO 48 (see FIG. 2) with the Q output of the divider 50 and a second mixer 57 to mix the Q output of the VCO with the I output of the divider. The outputs of the first and second mixers are connected together to generate the Q-clock. Similarly, the I-clock mixers utilizes a first mixer 59 to mix the I output of the divider with the I output of the VCO and a second mixer 61 to mix the Q output of the divider with the Q output of the VCO. The outputs of the first and second mixers are connected together to generate the I-clock. This technique provides very accurate I-Q clocks by combination of quadrature VCO and filtering. Because of the quadrature mixing, the accuracy of the I-Q clocks is not affected by the VCO inaccuracy, provided that the divide by N circuit generates quadrature outputs. This happens for even divide ratios, such as N=2.
The output of cascoded transistor 481 is coupled to the supply voltage through a first inductor 490. The output of the cascoded transistor 486 is coupled to the supply voltage through a second inductor 492. The LNA is tuned to the operating frequency by the output inductors 490, 492. More particularly, these inductors 490, 492 resonate with the LNA output parasitic capacitance, and the input capacitance of the next state (not shown). Embodiments of the present invention integrated into a single integrated circuit do not require a matching network at the LNA output.
The described complex filter can be integrated into a single chip transceiver or used in other low noise applications. In the case of transceiver chip integration, the off-chip filters used for image rejection and channel selection can be eliminated. A low-IF receiver architecture enables the channel-select feature to be integrated into the on-chip filter. However, if the IF lies within the bandwidth of the received signal, e.g., less than 80 MHz in the Bluetooth standard, the on-chip filter should be a complex filter (which in combination with the complex mixers) can suppress the image signal. Thus, either a passive or an active complex filter with channel select capability should be used. Although a passive complex filter does not dissipate any power by itself, it is lossy, and loads the previous stage significantly. Thus, an active complex filter with channel select capability is preferred. The channel select feature of the active complex filter can achieve comparable performance to conventional band-pass channel-select filters in terms of noise figure, linearity, and power consumption.
H ⁡ ( jω ) = V o V I ⁢ ( jω ) = A 1 + j ⁢ ⁢ RC ⁢ ⁢ ω - j2 ⁢ ⁢ Q ( 3 ) This shows a passband gain of A 122 at a center frequency of 2Q/RC 124, with a 3-dB bandwidth of 2RC 126. Thus, the quality factor of the second-order stage will be Q. For the image signal however, the signal at the I branch leads, and as a result:
H ⁡ ( jω ) = A 1 + j ⁢ ⁢ RC ⁢ ⁢ ω + j ⁢ ⁢ 2 ⁢ Q ( 4 ) which shows that the image located at 2Q/RC is rejected by
H ⁡ ( jω ) = R � Y 1 + j ⁢ ⁢ RC ⁢ ⁢ ω - j ⁢ ⁢ 2 ⁢ Q ( 10 ) FIG. 8 shows Yi having resistor RZ 128 and capacitor CZ 130.
In order to have a zero located at jω axis in the frequency response, Yi should contain a term such as 1−ω/ωz. If Yi is simply made of a resistor R, in parallel with a capacitor Cz, then the input admittance will be equal to:
Y i = 1 V = 1 R z - C z ⁢ ω ( 13 ) which indicates that the filter will have a zero equal to 1/RzCz at the jΦ axis.
FIG. 10 shows a single biquad stage modified to have a zero at the jω axis. The biquad stage includes capacitors 138, 140, 142, 144. The combination of capacitors 138, 140, 142, 144 and resistors 116, 118 determines a complex zero with respect to the center frequency. The transfer function for the received signal will be:
H ⁡ ( jω ) = A ⁢ 1 - RC z A ⁢ ω 1 + jRC ⁢ ⁢ ω - j ⁢ ⁢ 2 ⁢ Q ( 14 ) Equation (14) is analogous to equation (3), with the difference that now a zero at A/RCz is added to the biquad stage of the complex filter. By knowing the LP equivalent characteristics of the biquad stage, the poles are calculated based on equation (6). The value of Q and RC in each biquad stage is designed by using equation (7) and equation (8). If the normalized LP zeros are at �ωz,LP, then the biquad stage should be realized with two biquad stages cascoded, and the frequency of zeros in the biquad stages will be (equation (5)):
Referring to FIG. 12( b), each resistor can be implemented with a series of switchable resistors 158, 160, 162, 164, 166. Resistor 166 provides a resistance of R. Resistor 164 provides a resistance of 2 R. Resistor 162 provides a resistance of 4 Ru. Resistor 160 provides a resistance of 8 Ru. Resistor 158 provides a resistance of 16 R. In the described exemplary embodiment, the resistance can be varied between Ru and 31�Ru in incremental steps equal to Ru by selectively bypassing the resistor based on a five-bit binary code.
The center frequency of the complex filter can be adjusted by setting 1/RuCu equal to a reference frequency generated, by way of example, the crystal oscillator in the controller. The filter is automatically tuned by monotonic successive approximation as described in detail in Section 4.0 herein. Once the value of RuCu is set, the complex filter characteristics depends only on four-bit code for the capacitors and the four-bit code for the resistors For example, assume that the value of the resistors in the biquad stage of FIG. 6 is as following: Ri=nARu, Rf=nQRu, and Rc=nQRu. Likewise, assume that C=ncCu, where nc is a constant, and that 1/RuCu=ωu. The value of ωu is set to a reference crystal by a successive approximation feedback loop. The filter frequency response for the received signal will be:
H ⁡ ( jω ) = n F n A 1 + jn c ⁢ n F ⁢ R u ⁢ C u ⁢ ω - j ⁢ n F n Q ( 16 ) Therefore, the biquad stage gain (A), center frequency (ω0), and bandwidth (BW) will be equal to:
In one embodiment of the programmable gain amplifier, the type I and type III amplifiers can be the same. FIG. 15 shows one possible construction of these amplifiers. This configuration, transistors 952, 954 provide amplification of the differential input signal. The differential input signal is fed to the gates of transistor amplifiers 952, 954, and the amplified differential output signal is taken from the drains. The gain of the transistor amplifiers 952, 954 is set by load resistors 956, 958. Transistors 960, 962 provide a constant current source for the transistor amplifiers 952, 954. The load resistors 956, 958, connected between the drain of their respective transistor amplifiers 952, 954 and a common gate connection of transistors 960, 962, provides a bias current source to common mode feedback.
Turning back to FIG. 14, the type II core amplifier 902 includes a direct-coupled cascade of seven differential amplifiers 930, 931, 932, 933, 934, 935, 936, each with a voltage gain, by way of example, 12 dB, The voltage at the output of each differential amplifier 930, 931, 932, 933, 934, 935, 936 is coupled to a rectifier 937, 938, 939, 940, 941, 942, 943, 944, respectively. The outputs of the rectifiers are connected to ground through a common resistor 945. The summation of the currents from each of the rectifiers flowing through the common resistor provides a successive logarithmic approximation of the input IF voltage. With a 12 dB gain per each differential amplifier, a total cascaded gain of 84 dB is obtained. As those skilled in the art will appreciate, any number of differential amplifiers, each with the same or different gain, may be employed.
Ideal ⁢ ⁢ ⁢ Dynamic ⁢ ⁢ Range = 20 ⁢ log ⁢ S S A n = 20 ⁢ log ⁢ ⁢ A n = 20 ⁢ ( n ) ⁢ log ⁢ ⁢ A ( 22 ) However, in the case of a large amount of gain, the input level will be limited with the input noise and the dynamic range will also be limited to:
Dynamic ⁢ ⁢ Range = 20 ⁢ log ⁢ S σ n ⁢ ⁢ σ n = total ⁢ ⁢ noise ⁢ ⁢ rms ⁢ ⁢ σ n = ( BW ) � Noise ⁢ ⁢ Factor ( 23 ) If each differential amplifier has the same input dynamic range VL and each full-wave rectifier has similar input dynamic range Vi, then the dynamic range of the logarithmic differential amplifier and the total RSSI circuitry are the same.
A 2β2νin 2 +A 4β4νin 4 + . . . +A 2(n-m)β2(n-m)νin 2(n-m) +mβ 2 S 2=RSSI (25)
RSSI = ( A ⁢ ⁢ β ) 2 ( A ⁢ ⁢ β ) 2 - 1 ⁢ V in 2 ⁡ [ ( A ⁢ ⁢ β ) 2 ⁢ ( n - m - 1 ) - ] + m ⁢ ⁢ β 2 ⁢ S 2 ( 26 ) RSSI = 1 ( A ⁢ ⁢ β ) 2 - 1 ⁢ V in 2 ⁡ ( A ⁢ ⁢ β ) 2 ⁢ ( n - m ) + m ⁢ ⁢ β 2 ⁢ S 2 ( 27 ) The above equation is a first order approximation to the logarithmic function shown in equation (28) according to the first two terms of the Taylor expansion at a given operating point.
Max RSSI−Min RSSI=C log A 2n (29)ΔRSSI=C log A2n (30)
V in ⁢ ⁢ 1 = S ( A ) n - m ( 33 ) V in ⁢ ⁢ 2 = S ( A ) n - m - 1 ( 34 ) (Ideal)RSSI2−RSSI1=log (A)2 (35)(Approximated)RSSI2−RSSI1=β2 S 2 (36)
RSSI = 1 ( A ⁢ ⁢ β ) 2 - 1 ⁢ ( A ⁢ ⁢ β ) 2 ⁢ ( n - m ) ⁢ V in 2 + m ⁢ Δ ⁢ ⁢ RSSI n ; S A n - m < V in < S A n - m - 1 ( 39 ) FIG. 16( a) shows a schematic diagram for an exemplary embodiment of the differential amplifier used in the type II core amplifier. The differential input signal is fed to the gates of transistor amplifiers 955, 957. The amplified differential output signal is provided at the drains of the transistor amplifiers 955, 957. The gain of the transistor amplifiers is set by load transistors 958, 860, each connected between the drain of one of the transistor amplifiers and a power source. More particularly, the gain of the differential amplifier is determined by the ratio of the square root of transistor amplifiers-to-load transistors.
Gain ⁡ ( A ) = ⁢ w in w in = ⁢ 200 6 = 5.8 ( 40 ) The sources of the transistor amplifiers 955, 957 are connected in common and coupled to a constant current source transistor 952. In the described exemplary embodiment, the controller provides the bias to the gate of the transistor 952 to set the current.
if ⁢ ⁢ Δ ⁢ ⁢ I SQMI = ⁢ ( I D ⁢ ⁢ 1 + I D ⁢ ⁢ 4 ) - ( I D ⁢ ⁢ 2 + I D ⁢ ⁢ 3 ) = ⁢ 2 ⁢ ( I DC + I SQ ) = ⁢ 2 ⁢ k - 1 k + 1 ⁢ I o - 4 ⁢ k ⁡ ( k - 1 ) ⁢ β N ( k + 1 ) 2 ⁢ V I 2 ( 41 ) The input dynamic range of the full rectifier is then:
if ⁢ ⁢ Δ ⁢ ⁢ I SQMI = O , V i = � I o β N ⁢ k + 1 2 ⁢ k ( 42 ) The full-wave rectifier includes two unbalanced differential pairs with a unidirectional current output. One rectifier taps each differential pair and sums their currents into a 10 kW resistor RL.
The outputs of the limiters are coupled to the quadrature clocks of the IF mixers (I_in for mixer 322, I_in for mixer 323, (Q_in for mixer 324, Q_in for mixer 325) and the IF clocks are coupled to the data input of the IF mixers. This configuration minimizes spurs at the output of the IF mixers because the signal being mixed is the IF clocks which is a clean sine wave, and therefore, has minimal harmonics. The limiting action of the programmable multiple stage amplifier on the I and Q data will have essentially no effect on the spurs at the output of the IF mixers. FIG. 17 b shows the IF mixer clock signal spectrum which contains only odd harmonics. The IF signals do not have even harmonics in embodiments of the present invention using a fully differential configuration. The bandwidth of the m'th(=2n+1) harmonic is directly proportional to mfs, whereas its amplitude is inversely proportional to mfs. FIG. 17 c shows the sinusoidal input spectrum of the IF clocks. FIG. 17 d shows the IF mixer output spectrum.
FIG. 20 shows a baseband spectrum filtering before the discriminator. FIG. 20( a) shows the signal spectrum at polyphase input, i.e., the frequency spectrum of the polyphase filter.
FIG. 20( b) shows the signal spectrum at polyphase output, i.e. the frequency spectrum of the low pass filter. FIG. 20( c) shows the signal spectrum at the low pass filter output.
The frequency discrimination can be performed using a differentiator as shown in FIG. 22. A differential input signal is coupled to the input of an amplifier 340 through capacitors 341, 342. A feedback resistor 343, 344 is coupled between each differential output. Its operation is based on generating an output signal level linearly proportional to the incoming signal frequency. In other words, the higher the incoming frequency, the larger signal amplitude output by the differentiator. Therefore, it is desirable to have a spur free signal at the input of this stage. High frequency spurs can degrade the performance of the differentiator. By using the polyphase filter in conjunction with the lowpass filter (see FIG. 2) before the demodulator, a nearly ideal baseband signal is input to the differentiator. The capacitors 341, 342 in the signal path with the resistive feedback operation of the amplifier is proportional to the time derivative of the input. For a sinusoidal input, V(in)=A. sin (ωt), the output will be V(out): d/dt(V(in))=to.A. cos (ωt). Thus, the magnitude of the output increases linearly with increasing frequency.
In the output stage of the PA, the current level is higher and the size of the current source should be increased to maintain the same bias situation. However, large tail devices can lower the common mode rejection. Accordingly, instead of a current source, an inductor 640 can be used to improve the headroom. The inductor 640 is a good substitute for a current source. The inductor 640 is almost a short circuit at low frequencies and provides up to 1 Kohm of impedance at RF. By way of example, a 15nH inductor with proper shielding (to increase the Q) and a self-resonance frequency close to 4.5 GHz can be used for optimum high frequency impedance and sufficient self-resonance.
Capacitances associated with bias resistors may also be addressed. Consider a typical distributed model for a polysilicon (�poly� for short) resistor. Around 4fF to substrate can be associated with every kilo-ohm of resistance in a poly resistor. This means that, for example in a 2 OKohm resistor, around 80fF of distributed capacitance to the substrate exists. This can contribute to power loss because part of the power will be drained into the substrate. One way of biasing the input stage and the output stage is through a resistive voltage divider as shown in FIG. 26( a). The biasing of the input stage is shown for the transistor 616 in FIG. 25, however, those skilled in the art will readily appreciate that the same biasing circuit can be used for the transistor 614 (FIG. 25). One drawback from this approach, however, is that the gate of the transistor will see the capacitance from the two resistors 658, 660 of the voltage divider. Capacitor 662 is a coupling capacitor, which couples the previous stage to the voltage divider. Switch 664 is for powering down the stage of the power amplifier that is connected to the voltage divider. The switch 664 is on in normal operation and is off in power down mode.
2.3. Digitally Programmable CMOS PA with On-C& Matching
In embodiments of the present invention utilizing a low-IF or direct conversion architecture, techniques are implemented to deal with the potential disturbance of the local oscillator by the PA . Since the LO generator has a frequency which coincides with the RF signal at the transmitter output, the large modulated signal at the PA output may pull the VCO frequency. The potential for this disturbance can be reduced by setting the VCO frequency far from the PA output frequency. To this end, an exemplary embodiment of the LO generator produces RF clocks whose frequency is close to the PA output frequency, as required in a low-IF or direct-conversion architectures, with a VCO operating at a frequency far from that of the RF clocks. One way of doing so is to use two VCO 864, 866, with frequencies of f1 and f2 respectively, and mix 868 their output to generate a clock at a higher frequency of f1+f2 as shown in FIG. 31( a). With this approach, the VCO frequency will be away from the PA output frequency with an offset equal to f1 (or f2). A bandpass filter 876 after the mixer can be used to reject the undesired signal at f1−f2. The maximum offset can be achieved when f1 is close to f2.
An alternative embodiment for generating RF clocks far away in frequency from the VCO is to generate f2 by dividing the VCO output by N as shown in FIG. 31( b). The output of the VCO 864 (at f1) is coupled to a divider 872. The output of to divider 872 (at f2) is mixed with the VCO at mixer 868 to produce an RF clock frequency equal to: fLO=f1′(1+1/N), where f1 is the VCO frequency. A bandpass filter 874 at the mixer output can be used to reject the lower sideband located at f1−f1/N.
Because of the hard switching action of the buffers, the mixers will effectively be switched by a square-wave signal. Thus, the divider output will be upconverted by the main harmonic of VCO (f1), as well as its odd harmonics (n�f1), with a conversion gain of 1/n. In addition, at the input of the mixer, because of the nonlinearity of the mixers, and the buffers preceding the mixers, all the odd harmonics of the input signals to the mixers will exist. Even harmonics, both at the LO and the input of the mixers can be neglected if a fully balanced configuration is used. Therefore, all the harmonics of VCO (n�f1) will mix with all the harmonics of input (m�f2), where f2 is equal to f1/N. Because of the quadrature mixing, at each upconversion only one sideband appears at the mixer output. Upper or lower sideband rejection depends on the phase of the input and LO at each harmonic. For instance, for the main harmonics mixed with each other, the lower sideband is rejected, whereas when the main harmonic of the VCO mixes with the third harmonic of the divider output signal, the upper sideband is rejected.
Table 1 gives a summary of the cross-modulation products up to the 5th harmonic of the VCO and input. In each product, only one sideband is considered, since the other one is attenuated due to quadrature mixing, and is negligible.
1st: f1N
3rd: f1N
3rd: f1 f1 � (3 − 1/N)
The maximum filtering is obtained by choosing N=1. Moreover, in this case, the frequency divider is eliminated. This lowers the power consumption and reduces the system complexity of the LO generator. However, the choice of N=1 may not be practical for certain embodiments of the present invention employing a low-IF receiver architecture with quadrature LO signals. The problem arises from the fact that the third harmonic of the VCO (at mixed with the divider output (at f1) also produces a signal at 2f1 which has the same frequency as the main component of the RF clock output from the LO generator. With the configuration shown in FIG. 33, the following relations hold for the main harmonics:
−Cos(ω1 t)�⅓Cos(3ω1 t)−Sin(ω1 t)�⅓Sin(3ω1 t)→−⅓Cos(2ω1 t) (47)andCos(ω1 t)�⅓Sin(3ω1 t)−Sin(ω1 t)�⅓Cos(3ω1 t)→−⅓Sin(2ω1 t) (48)
The factor ⅓ appears in the above equations because the third harmonic of a square-wave has an amplitude which is one third of the main harmonic. Comparing equation (46) with equation (48), the two products are added in equation (46), while they are subtracted in equation (47). The reason is that for the main harmonic of the VCO, quadrature outputs have phases of 0 and 90�, whereas for the third harmonic, the phases are 0 and 270�. The same holds true for equation (45) and equation (47). The two cosines in equation (45) and equation (47), when added, give a cosine at 2ωi with an amplitude of 2/3, yet the two sinewaves in equation (46) and equation (48) when added, give a component at 2ωi with an amplitude of 4/3. Therefore, a significant amplitude imbalance exists at the I and Q outputs of the mixers. When these signals pass through the nonlinear buffer at the mixers output, the amplitude imbalance will be reduced. However, because of the AM to PM conversion, some phase inaccuracy will be introduced. The accuracy can be improved with a quadrature generator, such as a polyphase filter, after the mixers. A polyphase filter, however, is lossy, especially at high frequency, and it can load its previous stage considerably. This increases the LO generator power consumption significantly, and renders the choice of N=1 unattractive for embodiments of the present invention employing a low-IF receiver architecture with quadrature LO signals.
 H ⁡ ( f )  = f Qf 0 [ 1 - ( f f 0 ) 2 ] 2 + ( f Qf 0 ) 2 ( 48 ) The following discussion changes based on the Q value. Considering a Q of about 5 for the inductor, with f0=1.5f1, the spur located at 2.5f1 is rejected by about 15 dB by each LC a circuit. This spur is produced at the LO generator output due to the mixing of the VCO third harmonic (at 3f1) with the divider output (at 0.5f1). This signal is attenuated by 10 dB since the third harmonic of a square-wave is one third of the main harmonic, 15 dB at the LC resonator at the mixers output tuned to 1.5f1, and another 15 dB at the output of the buffers (893, 895 in FIG. 33). This gives a total rejection of 40 dB. When applied to the mixers in the transmitter, this LO generator output will upconvert the baseband data to 2.5f1. With LC filters (not shown) positioned at the upconversion mixers and PA output in the transmitter, another 15+15=30 dB rejection is obtained (FIG. 33).
The spur located at 0.5f1 is produced because of the third harmonic of the divider output (at 1.5f1) is mixed with the VCO output (at f1). Because of the hard switching action at the divider output, the third harmonic is about 10 dB lower than the main harmonic at 0.5f1. The buffer at the divider output tuned to 0.5f1 (891, 894 in FIG. 33), rejects this signal by about 22 dB (equation (24)). This spur can be further attenuated by LC circuits at the mixer and its buffer output by (2)(22)=44 dB. The total rejection is 76 dB.
FIG. 33( a) shows a signal passing through a limiting buffer 910 (such as the buffers implemented in the LO generator). When a large signal at a frequency off accompanied with a small interferer at a frequency of Δf 902 away pass through a limiting buffer, at the limiter output the interferer produces two tones �Δf 914, 916 away from the main signal, each with 6 dB lower amplitude. Therefore, the spur at 2.5f1 will actually be 10+15+15+6=46 dB attenuated when it passes through the buffer, instead of the 40 dB calculated above. It will also produce an image at 0.5f1, which is 10+15+22+6 53 dB lower than the main signal. This will dominate the spur at 0.5f1, because of the third harmonic of the divider mixed with the VCO signal, which is more than 75 dB lower than the main signal.
Since the buffer is nonlinear, another major spur at the LO generator output is the third harmonic of the main signal located at 3�1.5f1 This signal will be 10+22=32 dB lower than the main harmonic. The 22 dB rejection results from an LC circuit (not shown) tuned to 1155f1 (equation (49)) in the buffer. This undesired signal will not degrade the LO generator performance, since even if a perfect sinewave is applied to upconversion (or downconversion) mixers, due to hard switching action of the buffer, the mixer is actually switched by a square-wave whose third harmonic is only 10 dB lower. Thus, if a nonlinear PA is used in the transmitter, even with a perfect input to the PA, the third harmonic at the transmitter output will be 10+22+10=42 dB lower. The first 10 dB is because the third harmonic of a square-wave is one third of the main one, the 22 dB is due to the LC filter at the PA output, and the last 10 dB is because the data is spread in the frequency domain by three times. Any DC offset at the mixer input in the transmitter is upconverted by the LO, and produces a spur at f1. This spur can be attenuated by 13 dB for each LC circuit used (equation (49)). In addition, the signal at the mixer input in the transmitter is considerably larger (about 10-20 times) than the DC offset. Thus the spur at f1 will be about 13+13+26=52 dB lower than the main signal. All other spurs given in Table 1 are more than 55 dB lower at the LO generator output. The dominant spur is the one at 2.5f1 which is about 46 dB lower than the main signal.
V out ⁢ ⁢ _ ⁢ ⁢ I = - Sin ⁡ ( θ 2 ) � Sin ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 2 ) + Cos ⁡ ( θ 2 ) � Cos ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 2 ) ⁢ ⁢ and ( 52 ) V out ⁢ ⁢ _ ⁢ ⁢ Q = - Sin ⁡ ( θ 2 ) � Cos ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 2 ) + Cos ⁡ ( θ 2 ) � Sin ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 2 ) ( 53 ) The above equations show that regardless of the value of θ, the outputs are always in quadrature. However, other effects should be evaluated. First, a spur at ω1−ω2=0.5ω1 is produced at the output. This spur can be attenuated by 2�22=44 dB by the LC filters at the mixer and its buffer outputs. Thus, for 60 dB rejection, the single sideband mixers need to provide an additional 16 dB of rejection (about 0.158). Based on equation (53), tan (θ/2)=0.158, or θ≈18�, phase accuracy of better than 18� can generally be achieved. Second, phase error at the VCO output lowers the mixer gain (term Cos (θ/2) in equation (52) or (53)). For a phase error of 18�, the gain reduction is, however, only 0.1 dB, which is negligible. For θ=90� (a single-phase VCO), both sidebands are equally upconverted at the mixer output. However, the LC filters reject the lower sideband by about 44 dB. The mixer gain will also be 3 dB lower. This will slightly increase the power consumption of the LO generator. If θ=180� (the VCO I and Q outputs are switched), the lower sideband is selected, and the desired sideband is completely rejected.
V out ⁢ ⁢ _ ⁢ ⁢ I = - Sin ⁡ ( θ 1 - θ 2 2 ) � Sin ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 1 - θ 2 2 ) + Cos ⁡ ( θ 1 + θ 2 2 ) � Cos ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 1 + θ 2 2 ) ⁢ ⁢ and ( 54 ) V out ⁢ ⁢ _ ⁢ ⁢ Q = - Sin ⁡ ( θ 1 + θ 2 2 ) � Cos ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 1 - θ 2 2 ) + Cos ⁡ ( θ 1 - θ 2 2 ) � Sin ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 1 + θ 2 2 ) ( 55 ) This shows that the outputs still have phases of 0 and 90�, but their amplitudes are not equal. The amplitude imbalance is equal to:
Δ ⁢ ⁢ A A = 2 ⁢ Cos ⁡ ( θ 1 + θ 2 2 ) - Cos ⁢ ⁢ ( θ 1 - θ 2 2 ) Cos ⁡ ( θ 1 + θ 2 2 ) + Cos ⁢ ⁢ ( θ 1 - θ 2 2 ) = 2 ⁢ ⁢ tan ⁢ ⁢ ( θ 1 2 ) � tan ⁢ ⁢ ( θ 2 2 ) ( 56 ) If θ1 and θ2 are small and have an equal standard deviation, that is, the phase errors in the VCO and divider are the same in nature, then the output amplitude standard deviation will be:
FIG. 37( a) shows how the VCO of FIG. 34 can be connected to the divider before being upconverted to the R.F clock frequency in the LO generator. The I output signal of the VCO is coupled to buffer 884 and the Q output signal of the VCO is coupled to buffer 886. Buffer 888 combines the I-Q data from the buffer 884 and the buffer 886 to obtain a larger signal. The large signal is coupled to a divider 50 where it is divided in frequency by N to get quadrature signals.
σ A = ( σ α ) 2 2 ( 58 ) The reason phase inaccuracy is more emphasized here is that because of the limiting stages in the LO generator and the hard switching at the mixers LC input, most of the errors will be in phase, rather than amplitude.
Transistors 172, 174, 176, 178, 180, 182 form a cascode current source with a reference current IREF 184. With the gates of the transistors 172 and 178 tied to their respective sources, a fixed reference current IREF 184 can be established. By tying the gates of the transistors 174, 180 to the gates of the transistors 172, 178, respectively, the current through resistor Rc 186 can be mirrored to IREF 184. Similarly, by tying the gates of the transistors 176, 182 to the gates of the transistors 174, 180, respectively, the current through resistor Rc 186 can be mirrored to a tunable capacitor Cc 188. The calibration circuit tunes the absolute value of the RC to a desired frequency by using this cascode-current source to provide identical currents to the on-chip reference resistor Rc 186 and to the tunable capacitor Cc 188 generating the voltages VRES 190 and VCAP 192, respectively. Embodiments of the present invention that are integrated into a single IC can use an off chip reference resistor Rc to obtain greater calibration accuracy. The current through the tunable capacitor is controlled by a logic control block 195 via switch S2 193. During the charging phase, switch S2 193 is closed and switch S1 is open to charge the tunable capacitor Cc 188 to VCAP. The voltage held on the tunable capacitor 188 VCAP is then compared, using a latched comparator 198, to a voltage generated across the reference resistor 186. The value of the tunable capacitor Cc 188 is incremented in successive steps by the logic control block 195 until the voltage held by the tunable capacitor Cc matches the voltage across the reference resistor 186, at which point the 4-bit control word for optimal calibration of the RC circuits for the transmitter, receiver, and LO generator is obtained. More particularly, once the voltage VCAP reaches the voltage VRES, the output of the comparator output 198 switches. The switched comparator output is detected by the control logic 195. The control logic 195 opens switch S2 193 and closes switch S1 194 causing the tunable capacitor 188 Cc to discharge. The resultant 4-bit control word is latched by the control logic 195 and coupled to the transceiver, receiver, and LO generator.
Cp 200 compensates for the parasitic capacitance loading of the capacitive branch. By choosing Cc 188 to be much larger than Cr 200, the voltage error at node VCAP 192 caused by charging the parasitic capacitance becomes negligible.
Two branches of polyphase filtering are used in this algorithm. Two 4-bit control words are used to control the value of the capacitances in each polyphase filter. The initial control words set the capacitance in the first filter (Polyphase A) to its maximum value and the capacitance in the second filter (Polyphase B) to its minimum value. This provides an initial condition in which the filters have maximum signal suppression set at frequencies (ωlow and ωhigh) that are approximately �40% of the frequency of the input signal XIN for the case of nominal process variation. For a sinusoidal input XIN the calibration circuit depicted in FIG. 40 would require only a single-stage polyphase filter in each branch. The single-stage filters would attenuate the sinusoid input signal, generating outputs at XA and XB with the dominant one still at the same frequency as the input signal. However, the reference clock from the LO generator is a digital rail-to-rail clock. Because the input is not a pure sinusoid, multiple-stage filters may provide greater calibration accuracy. In the case of a single-stage filter with a digital clock, the filter would suppress the fundamental frequency component at ωin to a significant degree but the harmonics would pass through relatively unaffected. The RSSI block would then detect and limit the third harmonic component of the input signal at 3ωin, as it becomes the dominant frequency component after the fundamental is suppressed. This could result in an inaccurate calibration code.
A three-stage polyphase filter can be used in each branch to suppress the fundamental frequency component of XIN as well as the 3rd and 5th harmonics. The first stage of the polyphase filter can provide rejection of the fundamental frequency component. The second stage can provide rejection of the 3rd harmonic. The third stage can provide rejection of the 5th harmonic. At the same time, the higher harmonics of the input signal XIN can be suppressed with an RC lowpass filter in a buffer (not shown) preceding the polyphase filters. As a result, the dominant frequency component of the signals XA and XA remains at the input frequency ωin, which is then properly detected by the RSSI blocks.
FIG. 42 shows an exemplary embodiment of the bandgap calibration circuit. The bandgap calibration circuit uses the reference clock provided from the LO generator and a reference resistor RREF 236 to adjust a tunable resistance value RPOLY 238 in a compare-and-increment loop until an optimum value is obtained. In embodiments of the present invention which are integrated into a single IC, the reference resistor RREF 236 can be off-chip to provide improved calibration accuracy. A 4-bit control word is output to accurately calibrate the resistors in the transmitter, receiver and LO generator within �2%. Transistors 224, 226, 228, 230, 232, 234 form a cascode current with a reference current IREF. The transistors 224, 230 each have their gates tied to their respective sources to set up the reference current IREF. By tying the gates of the transistors 224, 230, respectively to the gates of the transistors 226, 232, the reference current IREF is mirrored to the reference resistor RREF 236. Similarly, by tying the gates of the transistors 228, 234, respectively to the gates of the transistors, the reference current IREF is also mirrored to the tunable resistor RPOLY 238. The voltage generated across the tunable resistor RPOLY 238 is compared, using a latched comparator 240, to the voltage generated across the reference resistor RREF 236. The value of the tunable resistor RPOLY 238 is incremented in successive steps, preferably, every 0.5 μs, through the utilization of control logic 242 that is clocked, by way of example, at 2 MHz. This process continues until the voltage VPOLY across the tunable resistor RPOLY 238 matches the voltage VREF across the off chip reference resistor RREF 236 causing the output of the comparator to change states and disable the control logic 242. Once the control logic is disabled, the 4-bit control word can be used to accurately calibrate the resistors in the transmitter, receiver and LO generator.
The clock signals used by the calibration circuit are generated by first dividing the reference clock input into the controller from the LO generator down in frequency, and then converting the result into different phases for the comparison and increment phases of calibration. This bandgap calibration circuit provides accurate resistance values for use in various on-chip circuit implementations because resistor scaling and matching on the same integrated circuit can be well controlled with proper layout techniques. The bandgap calibration circuit provides a resistor tuning range of approximately �30%, which is sufficient to cover the range of process variation typical in semiconductor fabrication. With a 4-bit control word generating 24 possible resistance values, the calibration is completed within (2 MHz)−1(24−1)=7.5 ms. The calibration circuit can be powered down when the optimal resistance value has been obtained.
The bandgap calibration circuit can be used for numerous applications. By way of example, FIG. 43 shows a bandgap calibration circuit 244 used in an application for calibrating a bandgap reference current that is independent of temperature. The 4-bit control word from the bandgap calibration circuit is coupled, by way of illustration, to the receiver. The 4-bit control word is used to calibrate resistances in a proportional-to-absolute-temperature (PTAT) bias circuit 246, and also in a VBE (negative temperature coefficient) bias circuit 248. The outputs of these blocks are two bias voltages, VP 250 and VN, 252 that generate currents exhibiting a positive temperature coefficient, and a negative temperature coefficient, respectively. When these currents are summed together using the cascode current minor formed by transistors 254, 256, 258, 260, the result is a current IOUT displays a (ideally) zero temperature coefficient.
In the transmitter, receiver and LO generator non-silicided polysilicon resistors can be used. As those skilled in the art will appreciate, other resistor technologies can also be used. Non-silicided polysilicon resistors have a high sheet resistance of 200-Ω/square along with desirable matching properties. A switching resistor array as shown in FIG. 44 can be used to calibrate a resistor. The array includes serial connected resistors 208, 210, 212, 214, 216, which, by way of example, have resistances of 2200Ω, 1100Ω, 550Ω, 275Ω, and 137Ω, respectively. The resistors 210, 212, 214, 216 include a bypass switch for switching the resistors in and out of the array. The switch positions are nominally selected to produce an equivalent of 3025Ω. This resistance value has been chosen as a convenience to match the value used in generating an accurate bandgap reference current. A 4-bit calibration code is used to control the total resistance in this array. As seen in FIG. 44, the resistances are binary-weighted in value and the accurate scaling of each incremental resistance results by placing the largest resistor (2200Ω) 208 in series to generate each value. In the described embodiment, the incremental resistances shown in FIG. 44 are chosen so that the total resistance in the array covers a range 30% above and below its nominal value, with a maximum resistance error of �2% determined by the incremental resistance switched by the LSB. The range of resistance covered by the array is sufficient to cover typical process variations in a semiconductor process. A series resistive array may be desirable as opposed to a parallel resistive array because of the smaller area occupied on the wafer.
In operation, during the transmit mode, a differential voltage across the drains of the PA transistors 634, 632 is generated. The two drains assert 180-degree out of phase voltages and they are combined through the LC and CL matching circuits to yield a single-ended voltage at the output. The LC circuit shifts the phase of the output signal from the transistor 634 by 90 degrees. The CL circuit shifts the phase of the signal output from the transistor 632 by 90 degrees in the opposite direction. Consequently, both signals are in-phase when combined at the output of to matching circuits.
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