Source: http://www.google.com/patents/US8132076?dq=5,241,671
Timestamp: 2016-06-30 12:44:02
Document Index: 608139093

Matched Legal Cases: ['art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 16']

Patent US8132076 - Method and apparatus for interleaving portions of a data block in a ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsCircuit, method, and computer program for reordering data units of a data block in accordance with a first pre-determined function. The method includes, for each data unit of the data block—(i) generating an address corresponding to a memory location of a single-port memory module into which the data...http://www.google.com/patents/US8132076?utm_source=gb-gplus-sharePatent US8132076 - Method and apparatus for interleaving portions of a data block in a communication systemAdvanced Patent SearchPublication numberUS8132076 B1Publication typeGrantApplication numberUS 12/645,593Publication dateMar 6, 2012Filing dateDec 23, 2009Priority dateJul 8, 2005Fee statusPaidAlso published asUS7644340Publication number12645593, 645593, US 8132076 B1, US 8132076B1, US-B1-8132076, US8132076 B1, US8132076B1InventorsPeter Tze-Hwa LiuOriginal AssigneeMarvell International Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (9), Non-Patent Citations (20), Referenced by (2), Classifications (14), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMethod and apparatus for interleaving portions of a data block in a communication system
US 8132076 B1Abstract
Circuit, method, and computer program for reordering data units of a data block in accordance with a first pre-determined function. The method includes, for each data unit of the data block—(i) generating an address corresponding to a memory location of a single-port memory module into which the data unit is to be stored, and (ii) storing the data unit in the memory location based on the address generated for the data unit. Each address is generated in accordance with the first pre-determined function, and each memory location of the single-port memory has a different delay associated with the memory location. The method further includes reading each data unit out of the single-port memory in accordance with the first pre-determined function, wherein data units of the data block are reordered based on each different delay associated with each memory location.
1. A circuit for reordering data units of a data block in accordance with a first pre-determined function, the circuit comprising:
a single-port memory module having a plurality of memory locations, wherein (i) each memory location has a corresponding address and (ii) each memory location corresponds to a different delay;
a first address generator configured to, for each data unit of the data block, generate an address corresponding to a memory location into which the data unit is to be stored, wherein the first address generator generates each address in accordance with the first pre-determined function,
wherein as the data units are read out of the plurality of memory locations of the single-port memory, the data units of the data block are reordered in accordance with (i) the first pre-determined function and (ii) the different delays associated with the plurality of memory locations;
a dual-port memory module having a plurality of memory locations, wherein each memory location of the dual-port memory module has a corresponding address; and
a second address generator configured to, for each data unit read out of a memory location of the single-port memory module, generate an address corresponding to a memory location of the dual-port memory module into which the data unit is to be stored,
wherein the second address generator generates each address in accordance with a second pre-determined function.
2. The circuit of claim 1, wherein the first pre-determined function implements, at least in part, a general convolutional interleaving scheme.
3. The circuit of claim 2, wherein the general convolutional interleaving scheme is compliant with one or more of the following International Telecommunication Union (ITU) specifications: 992.1, 992.3, or 993.1.
4. The circuit of claim 2, wherein the general convolutional interleaving scheme comprises a triangular convolutional interleaving scheme.
5. The circuit of claim 1, wherein each data unit corresponds to a byte of the data block.
6. The circuit of claim 1, wherein the second pre-determined function is different from the first pre-determined function.
7. A method for reordering data units of a data block in accordance with a first pre-determined function, the method comprising:
for each data unit of the data block,
generating an address corresponding to a memory location of a single-port memory module into which the data unit is to be stored, wherein each address is generated in accordance with the first pre-determined function, and wherein each memory location of the single-port memory has a different delay associated with the memory location, and
storing the data unit in the memory location based on the address generated for the data unit;
reading each data unit out of the single-port memory in accordance with the first pre-determined function, wherein data units of the data block are reordered based on each different delay associated with each memory location; and
for each data unit read out of a memory location of the single-port memory, generating a storage address corresponding to a memory location of a dual-port memory module into which the data unit is to be stored, wherein the storage addresses are generated in accordance with a second pre-determined function.
8. The method of claim 7, wherein the first pre-determined function implements, at least in part, a general convolutional interleaving scheme.
9. The method of claim 8, wherein the general convolutional interleaving scheme is compliant with one or more of the following International Telecommunication Union (ITU) specifications: 992.1, 992.3, or 993.1.
10. The method of claim 8, wherein the general convolutional interleaving scheme comprises a triangular convolutional interleaving scheme.
11. The method of claim 7, wherein each data unit corresponds to a byte of the data block.
12. A computer program, tangibly stored on a computer readable medium, for reordering data units of a data block in accordance with a first pre-determined function, the computer program being executable by a processor and comprising instructions for:
for each data unit read out of a memory location of the single-port memory, generating a storage address corresponding to a memory location of a dual-port memory module into which the data unit is to be stored, wherein the storage addresses are generated win accordance with a second pre-determined function.
13. The computer program of claim 12, wherein the first pre-determined function implements, at least in part, a general convolutional interleaving scheme.
14. The computer program of claim 13, wherein the general convolutional interleaving scheme is compliant with one or more of the following International Telecommunication Union (ITU) specifications: 992.1, 992.3, or 993.1.
15. The computer program of claim 13, wherein the general convolutional interleaving scheme comprises a triangular convolutional interleaving scheme.
16. The computer program of claim 12, wherein each data unit corresponds to a byte of the data block.
This application is a continuation of U.S. patent application Ser. No. 11/361,930, filed Feb. 24, 2006, now U.S. Pat. No. 7,644,340, which claims the benefit of U.S. Provisional Application Nos. 60/727,659, filed Oct. 18, 2005, 60/698,881, filed Jul. 13, 2005, 60/698,226, filed Jul. 11, 2005, and 60/697,666, filed Jul. 8, 2005. The disclosures of the above applications are incorporated herein by reference in their entirety.
Bursty noise may exist on channel 20 that corrupts some of the interleaved bytes as they propagate to a receiver 22. A deinterleaver 24 receives the corrupted and interleaved bytes from receiver 22 and deinterleaver them according to an inverse of the interleaving method employed by interleaver 16. A decoder 26 receives the deinterleaved bytes and performs an error correction operation to recover data from the corrupted bytes and reproduce the data block at output 28. Whether decoder 26 succeeds in recovering the data is based on the type of error correcting code being used, the duration and frequency of the bursty noise in channel 20, and the interleaving depth, which is described below.
The memory space of interleaver 16 is shown as matrices 32-1 and 32-2 having D=2 columns and N=3 rows. Interleaver 16 writes bytes (b0 . . . b5) from data block 30 to matrix 32-1 in column-by-column fashion until matrix 32-1 is full. After matrix 32-1 is full, interleaver 16 writes bytes (b6 . . . b11) from data block 30 to matrix 32-2 in column-by-column fashion. While interleaver 16 is writing bytes (b6 . . . b11) into matrix 32-2, interleaver 16 also reads bytes (b0 . . . b5) out from matrix 32-1 in row-by-row fashion to be transmitted in the order shown at 34. After data bytes (b6 . . . b11) have been written into matrix 32-2 and data bytes (b0 . . . b5) have been read from matrix 32-1, interleaver starts writing data into matrix 32-1 column-by-column and reading data out from 32-2 row-by-row. Interleaver 16 repeats the writing and reading processes via respective ones of the matrices 32 until the entire data block 30 has been interleaved. These processes are repeated every N*D period.
In other features each reading step executes immediately prior to each writing step for each of the address locations. Each reading step and writing step is associated with the same address location. The interleaving function includes a triangular convolutional interleaving (TCI) function.
FIG. 3 is a functional block diagram of a general convolutional interleaver (GCI);
Control begins in block 202 and immediately proceeds to block 204 and initializes an index i to zero. This i corresponds to the ith row in FIG. 5. Control then proceeds to block 206 and computes an index ith_F based on the equation ith_F=(dm1*i) mod I. Control then proceeds to block 208 and computes an index ith_I based on the equation ith_I=((dm1*i)−ith_F)/I. Control then proceeds to block 210 and computes an index ith_offset to the sum of delay bytes in the delay paths (FIG. 5) preceding the ith delay path whose indices are currently being computed. Control then proceeds to block 212 and increments i before proceeding to decision block 214 and determining whether i=I. If i≠I, then control returns to block 206 to compute another set of parameters for the next delay path. If i=I, then control proceeds to block 215 and determines whether input data stream 104 has been interleaved. If there are still left over data in input data stream 104 then control returns to block 204. Otherwise, control exits through block 216.
Control begins in block 252 and immediately proceeds to block 253 and clears the contents of index RAM 232 address locations 0 through (I−1). Control then proceeds to block 254 and initializes i to zero. Control then proceeds to decision block 258 and determines whether i=0. If i=0, then control is starting a new cycle through the delay paths (FIG. 5) and proceeds to block 262. In block 262, control resets ith_F, ith_I, and ith_offset to zero. Control also copies the byte appearing at input 104 directly to the input port of F-RAM 108. This copying step implements the digital delay of zero in delay path P0 (FIG. 5). Control then proceeds to decision block 268. If i≠0 in decision block 258, then control proceeds to block 266 to increment ith_I by M and increment ith_F by N. Control then proceeds to decision block 268 and determines whether ith_F is greater than or equal to I. If so, then control branches to block 270 to decrement ith_F by I and then branches to block 272 to increment ith_I by 1. Control then proceeds to block 274. Control also arrives at block 274 when ith_F is less than 1 in decision block 268.
In block 274, control determines the byte address in address space 230 based on the equation Address=ith_offset+ith_index, where ith_index is the contents of index RAM 232 at row i. Control then proceeds to decision block 276 and determines whether ith_I is equal to zero. If so, then control branches to block 278 and copies the byte appearing at input 104 directly to the input port of F-RAM 108. Control then proceeds to block 276. If ith_I≠I≠0 in decision block 276, then control branches to block 280.
In block 280, control copies the byte from I-RAM 102 at location Address to the input of F-RAM 108 and copies the byte appearing at input 104 to location Address of I-RAM 102. Control then proceeds to block 282 and updates ith_index based on the equation ith_index=(ith_index+1) mod ith_I. Control then proceeds to block 284 and updates ith_offset based on the equation ith_offset=ith_offset+ith_I. Control then returns to block 256.
During interleaving F-RAM address generator 110 generates the Read Address in accordance with a mod I counter. That is, the Read Address follows a pattern 0, 1, 2, . . . , (I−1), 0, 1, 2, . . . , (I−1), . . . throughout the interleaving process. The Write address is generated in accordance with the equation Write Address=(Read Address+ith_F) mod I. When Write Address and Read Address are unequal, the effective delay between input port 292 and output port 294 is ith_F.
Control then proceeds to block 308 and determines an integer Y based on the equation dm1*(I−1) mod I, where Y represents a fractional part of the longest length of the delay lines (FIG. 5). Control then proceeds to block 310 and determines an integer X based on the equation X=(dm1*(I−1)−Y)/I, where X represents an integer part of the longest length of the delay lines (FIG. 5).
Control then proceeds to block 312 and sets i equal to zero. Control then proceeds to decision block 313 and determines whether i=Y. If so, control branches to block 314 and sets j equal to I−1 before continuing to block 315. If the result in decision block 313 was negative, then control branches to block 315 and decrements j. Control then proceeds to block 316 and determines ith_F in accordance with the equation ith_F=(dm1*j) mod I. Control then proceeds to block 317 and determines ith_I in accordance with the equation ((dm1*j)−ith_F)/I. Control then proceeds to block 318 and determines index ith_offset based on the sum of delay bytes in the delay paths (FIG. 5) preceding the jth delay path currently being processed. Control then proceeds to block 319 and increments i. Control then continues to decision block 320 and determines whether i=I. If not, then control branches back to decision block 313. If so, then control branches to decision block 321 and determines whether method 300 has processed all of input data stream 104. If not, then control returns to block 312. Otherwise control exits through block 322.
F-RAM address generator 126 generates a Write Address 323 and Read Address 324 based on methods described below. Data arriving at input port 124 is written to respective Write Addresses 323 and data generated at output port 127 is read from respective Read Addresses 324. F-RAM address generator 126 also generates the variable ith_F and a synchronization signal 325, such as index i, that are communicated to I-RAM address generator 130 of deinterleaver 120.
The addresses generated by the F-RAM address generator 126 during deinterleaving will now be described. Read Addresses 324 are generated accordance with a mod I counter, e.g. 0, 1, 2, . . . , (I−1), 0, 1, 2, . . . , (I−1), . . . throughout the deinterleaving process. Write Addresses 323 are initialized to Y upon deinterleaver 120 receiving the beginning of each interleaved data stream 104. Write Addresses 323 are then generated with each received byte based on Write Address=Write Address+Z. If Write Address>=I, then Write Address is reset to Write Address−I. The effective delay between input port 124 and output port 127 is ith_F when Write Address 323 and Read Address 324 are unequal. When Write Address 323 and Read Address 324 are equal, the data appearing at input port 124 is immediately provided at output port 127 to provide zero delay as symbolized by line 326.
In block 358, control copies the byte from I-RAM 128 at location Address to output 132 and copies the byte appearing at input 127 to location Address of I-RAM 128. Control then proceeds to block 360 and updates ith_index based on the equation ith_index=(ith_index+1) mod ith_I. Control then stores ith_index at row i in index RAM 232. Control then proceeds to block 362 and updates ith_offset based on the equation ith_offset=ith_offset+ith_I. Control then returns to block 336.
GCI 100 and GCD 120 can also support an existing triangular convolutional interleaver (TCI) by choosing TCI is specified in ITU standard ITU-G.993.1, which is hereby incorporated by reference in its entirety, for VDSL-1. In this case, I is chosen to be divisible by (D−1) and (D−1)/I=M. ith_F is zero for all paths (FIG. 5) and ith_I=0, M, 2M, 3M, . . . , which implements TCI. Since ith_F=0 for all paths, the Write Address and Read Address are always equal from F-RAM address generator 110 and F-RAM 108 is effectively bypassed. Implementing the TCI allows GCI 100 and GCD 120 to communicate with existing devices that also use TCI.
RAT module 410 also receives a function ID signal 416 that indicates which functional block 402 is currently being accessed. A software input 418 allows data in RAT module 410 to be read and/or written. This makes the SW capable of maintaining and modifying the shared memory resource to be dynamically re-allocated if some dynamically changing requirements happened. Examples of data include the free memory tags and desired size of a functional block 402, respectively, and/or other data related to managing memory space 400 GCI 100 and GCD 120 can also be implemented for use with a wireless channel. For wireless network applications, please refer to IEEE standards 802.11, 802.11a, 802.11b, 802.11g, 802.11h, 802.11n, 802.16, and 802.20. Also refer to Bluetooth if applicable. The aforementioned specifications are hereby incorporated by reference in their entirety.
The HDD 500 may communicate with a host device (not shown) such as a computer, mobile computing devices such as personal digital assistants, cellular phones, media or MP3 players and the like, and/or other devices via one or more wired or wireless communication links 508. The HDD 500 may be connected to memory 509 such as random access memory (RAM), low latency nonvolatile memory such as flash memory, read only memory (ROM) and/or other suitable electronic data storage. The HDD 500 may also include a power supply 503 Referring now to FIG. 17B, the present invention can be implemented in a digital versatile disc (DVD) drive 510. The present invention may be implemented in either or both signal processing and/or control circuits, which are generally identified in FIG. 17B at 512. The signal processing and/or control circuit 512 and/or other circuits (not shown) in the DVD 510 may process data, perform coding and/or encryption, perform calculations, and/or format data that is read from and/or data written to an optical storage medium 516. In some implementations, the signal processing and/or control circuit 512 and/or other circuits (not shown) in the DVD 510 can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive.
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