Source: http://www.google.de/patents/US20050020020
Timestamp: 2013-12-11 09:45:01
Document Index: 561083232

Matched Legal Cases: ['art 13', 'art 13', 'art 13', 'art 13', 'art 12', 'art 26', 'art 26']

Patent US20050020020 - Integrated semiconductor fin device and a method for manufacturing such device - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr » Erweiterte Patentsuche | Anmelden Erweiterte Patentsuche PatenteA CMOS circuit for and method of forming a FinFET device is disclosed. The method includes providing a substrate comprising a semiconductor layer, forming on the semiconductor layer active areas insulated from each other by field areas, forming at least one dummy gate on at least one of said active areas...http://www.google.de/patents/US20050020020?utm_source=gb-gplus-sharePatent US20050020020 - Integrated semiconductor fin device and a method for manufacturing such device Ver�ffentlichungsnummerUS20050020020 A1PublikationstypAnmeldung AnmeldenummerUS 10/621,044 Ver�ffentlichungsdatum27. Jan. 2005Eingetragen15. Juli 2003 Priorit�tsdatum16. Juli 2002Auch ver�ffentlicht unterUS6974729 Ver�ffentlichungsnummer10621044, 621044, US 2005/0020020 A1, US 2005/020020 A1, US 20050020020 A1, US 20050020020A1, US 2005020020 A1, US 2005020020A1, US-A1-20050020020, US-A1-2005020020, US2005/0020020A1, US2005/020020A1, US20050020020 A1, US20050020020A1, US2005020020 A1, US2005020020A1 ErfinderNadine Collaert, Kristin De MeyerUrspr�nglich Bevollm�chtigterNadine Collaert, Kristin De MeyerZitat exportierenBiBTeX, EndNote, RefMan Referenziert von (41), Klassifizierungen (38), Juristische Ereignisse (4) Externe Links: USPTO, USPTO-Zuordnung, EspacenetIntegrated semiconductor fin device and a method for manufacturing such deviceUS 20050020020 A1 Zusammenfassung A CMOS circuit for and method of forming a FinFET device is disclosed. The method includes providing a substrate comprising a semiconductor layer, forming on the semiconductor layer active areas insulated from each other by field areas, forming at least one dummy gate on at least one of said active areas and forming source and drain regions on the at least one of the active areas. The method also includes covering the substrate with an insulating layer leaving said dummy gate exposed and forming an open cavity by patterning the dummy gate to form a dummy fin and a semiconductor fin aligned to said dummy fin, both fins extending from the source to the drain regions. Bilder(13) Anspr�che(33)
DETAILED DESCRIPTION OF CERTAIN INVENTIVE EMBODIMENTS In relation to the appended drawings, embodiments of the invention are described in detail in the sequel. It is apparent, however, that a person skilled in the art can imagine several other equivalent embodiments or other ways of executing the present invention, the spirit and scope of the present invention being limited only by the terms of the appended claims. The double or triple gate MOSFET is considered as the most promising device architecture for scaling CMOS into the deep sub-100 nm regime. Improved short channel effects and current drive capability are important features of this device. The fabrication of this device architecture is not straightforward and several attempts have been made to fabricate these devices in an economically acceptable way. As already outlined in the related technology section a variety in double gate devices exist and there are different process sequences for manufacturing such double gate MOSFET's each sequence having its associated advantages and disadvantages. Hence the particular order and specific steps in each process can be important to describe the fabrication of a particular device. Altering a step or sequence in a process flow may therefore result in a MOSFET or CMOS device with different characteristics. For the purpose of teaching the invention the process for forming a CMOS inverter circuit will be outlined. FIG. 1 shows a top view of a CMOS inverter according to one aspect of the invention. The field oxide region 5 isolates the active areas 4 in which respectively the nMOS device 40 and the pMOS device 41 of the CMOS inverter are formed. Both devices 40, 41 have the gate electrode 24 in common. This gate electrode 24 straddles the semiconductor fin 17 connecting the source 6 and the drain 7 of the MOSFET. As shown in the figure the gate electrode 24 extends beyond the active area 4 and overlaps the field region 5. The semiconductor fin 17, the source 6 and the drain 7 area of the transistors are formed in the same, continuous, layer 2 (not indicated). Against the sidewalls of the area 8 inside the active area 4 and outlined by the source 6, the drain 7 and the field region 5, sidewall spacers 21 are formed (FIG. 6 a). These sidewall spacers 21 are formed 20 a in this area 8 adjacent to the semiconductor fin 17, and above 20 b the semiconductor fin 17 thereby offsetting the gate electrode 24 from the edges of the source 6 and drain 7 regions (FIG. 8 a). These sidewall spacers 21 also decrease the unwanted capacitive coupling between the gate electrode 24 and the source and drain regions 6, 7. Cross-sectional drawings of this inverter will be used to illustrate various process steps. In figures �a� the section AA made along the channel of a MOSFET is shown while in figures �b� the section BB along the fin perpendicular to section AA is shown. Referring to FIGS. 2 a and 2 b, the processing starts with a substrate 1. Typically this substrate 1 is a semiconductor substrate such as a silicon or germanium wafer. In one embodiment, this substrate is a Silicon-On-Insulator (SOI) wafer 1, with a top layer of silicon 2 upon an underlying oxide layer 3. However, a semiconductor wafer 1 can be used on which only locally SOI regions are created by, e.g., only forming a stack of the semiconductor layer 2 on top of the dielectric layer 3 on top of the substrate 1 in selected areas. This stack can be obtained, for example, by locally forming the dielectric layer 3 in the selected areas, e.g., by growing an oxide, and then locally forming the semiconductor layer 2 on this dielectric layer 3, e.g., by selective atomic layer CVD (Chemical Vapor Deposition), as appreciated by a person skilled in the art. Within these selected areas devices according to one aspect of the invention are formed while in the non-selected areas, i.e. the non-SOI regions, classical bulk planar CMOS devices can be made in this substrate 1. A person skilled in the art will understand that for a bulk FET the channel region or at least the space charge region of the channel area formed during operation of the device will extend into the bulk of the semiconductor substrate 1, whereas in case of a SOI device the dielectric layer 3 separates the device layer 2 from the bulk of the substrate 1. For the purpose of teaching the invention an SOI wafer is used as starting substrate. In the semiconductor top layer 2, active area regions 4 are defined by forming field regions 5 that laterally isolate these active area regions 4. Later on in the processing transistors will be formed within the perimeter of these active area regions 4. The field regions 5 can be created using standard isolation methods, such as growing a field oxide or forming trenches in the substrate 1 filled with a dielectric as is known in the shallow trench isolation (STI) method, while protecting the active area regions 4 with a nitride masking layer. In one embodiment of the invention, field insulation is used instead of mesa insulation. In the latter a semiconductor layer is formed on top of an insulation layer and active areas are defined within this semiconductor layer yielding islands of semiconductor on top of the insulating layer. A second insulating layer can be used to cover these semiconductor islands and the regions in between, but an interface between these two insulating layers is unavoidable and might lead to a leakage path between the semiconductor islands. Field insulation techniques on the other hand offer the formation of an insulation layer extending above the level of the semiconductor layer comprising the active area's prior to forming transistors in these active area regions. Appropriate doping of the active area regions 4 can be done to result in the desired doping profiles within the semiconductor layer 2. For example, pwell and nwell regions for respectively receiving the nMOS and pMOS devices are formed by doping the active area regions 4 using e.g. ion implantation of boron and phosphorous, respectively. In some of the thus formed active areas, FinFETs, according to planar CMOS and/or BiCMOS devices, can be formed. As will be clear from the description, one embodiment of the invention allows to combine the formation of FinFET devices with classical planar devices without impacting the processing of these standard planar devices. Within each active area 4 that is selected to have a FinFET 40,41 to be formed therein, a source region 6, a drain region 7 and a gate region 8 are outlined by forming a dummy gate structure 9 on top of this selected active areas as shown in FIG. 2 c. The source 6 and drain 7 region are abutted by and aligned to this dummy gate structure 9, whereas the gate region 8, i.e., the region in between and separating the source 6 and drain 7 region, is covered by this dummy gate structure 9. The dummy gate structure 9 can comprise a single layer or a stack of layers whatever is appropriate. The dummy gate structure 9 can be formed using conventional semiconductor processing techniques, such as thermally growing an oxide 10 on top of the active area region 4 followed by a conformal deposition, e.g., by means of Chemical Vapor Deposition (CVD) process, of a top layer 11. This layer 11 can comprise a polysilicon 12 and/or a nitride layer 13. The deposited layers, in the example of a dual gate device being nitride 13 on top of polysilicon 12 on top of an oxide layer 10, are then patterned to yield the dummy gate structure 9. In one embodiment, patterning the dummy gate stack 9 uses optical lithography and dry etching. One purpose of this dummy gate structure 9 is to determine the lateral spacing �s� between the source 6 and drain 7 region as shown in FIG. 2 c, hence a more relaxed lithographic technology can be used for this patterning process. For example, 248 nm or 193 nm DUV technologies, which are used to define dimensions in the range of 100 to 400 nanometer in the photosensitive resist layer, can be applied. The dummy gate structure 9 will be removed later on in the process sequence and is at this stage in the process sequence only used to space apart the source 6 and drain 7 area. In one embodiment, the material or materials composing the dummy gate structure 9 has the ability to remove this material or these materials selective to the underlying layers or surrounding layer. In the example given above, the nitride layer 13 is selectively removable with respect to the polysilicon layer 12 of the dummy gate 9. This polysilicon layer 12 in its turn can be removed selective to the underlying oxide layer 10 using a dry etching process, while on its turn this oxide layer 10 of the dummy gate 9 can be removed selectively from the semiconductor material 2 by wet etching the oxide employing an HF-based solution. Other materials known to a person skilled in the art can be used to form the dummy gate structure 9. In another embodiment, the layer 11 or at least the top part 13 of this layer 11 can be used as a polish stop layer when planarizing the semiconductor using Chemical Mechanical Polishing (CMP). The standard CMOS devices, not shown in the drawings, formed on active areas 4 other than the active areas 4 in which the devices according to one aspect of the invention are formed, can use this oxide 10 as the gate dielectric and this polysilicon layer 12 as the gate electrode layer. Patterning the dummy gate 9 also includes then patterning the gate stack of the planar CMOS devices. In one embodiment, dedicated gate dielectric and gate electrode layers are formed for these classical CMOS devices in which case the layers 10,11 used to form the dummy gate stack 9 are only applied to make the FinFET device according to one aspect of the invention. This dummy gate stack 9 can also serve as a dummy gate stack in order to create replacement gate devices. U.S. patent application publication No. 20010049183 A1, hereby incorporated by reference in its entirety, illustrates methods for forming such replacement gate devices. FIGS. 2 a and 2 b show the cross-sections AA and BB of the inverter after the patterning of the dummy gate 9 of the nMOS 40 and pMOS 41 transistor. It is obvious for a person skilled in the art that the alignment of the dummy gate 9 as shown in FIG. 2 a is a theoretical example whereas in processing the dummy gate 9 might overlap on the field regions 5 so as to compensate for misalignment errors. In case of a planar device the channel region between source and drain will stop at the border of the field region. An overlap of the gate electrode 24 over the field region will offer a control over parasitic transistors, which are present at the border between the field region 5 and the active region 4. In case of a FinFET device such border between a channel region 17 and the field region 5 can be present depending on the layout of the transistor. If the dummy gate 9 and consequently the gate electrode 24 can be patterned to overlay the active area 4, a good control of the gate electrode 24 over the underlying transistors can be obtained regardless of the layout and position of the individual channel regions 17 (FIG. 1). If a thin film SOI wafer is used as starting substrate 1, the initial thickness of the thin SOI layer 2 might result in a very high series resistance within the finished transistor or might impede the growth of a silicide layer on the source 6 and drain 7 areas. For these and other reasons the thickness of the SOI layer 2 within the source 6 and drain 7 areas can be increased resulting in so-called elevated source and drain regions. In one embodiment the height of the silicon layer in the source 6 and drain 7 regions is increased by epitaxially growing a silicon layer 14 (FIG. 3 b) selective on the exposed silicon starting substrate 2. As the dummy gate structure 9 is still present during this epitaxial growth, only the source 6 and drain 7 regions are exposed while the gate region 8 is protected and covered by the dummy gate 9. In one embodiment, the material or materials used for the dummy gate 9, or at least for the parts of the dummy gate 9 that are exposed during the growth, are also chosen to not allow any substantial growth of semiconductor material on them during forming elevated source and drain areas. The dummy gate 9 masks the gate area 8 during selectively growing semiconductor material in the exposed source 6 and drain 7 regions. The source 6 and drain regions 7 are doped to obtain n- or p-type source and drain junctions with the desired doping profile for respectively the nMOS 40 and pMOS 41 transistor. In one embodiment, ion implantation is used to create a Highly Doped Drain (HDD) profile within the source 6 and drain regions 7. The doping profile is preferably uniform within the source 6 and drain 7 regions both in lateral as well as in vertical direction resulting in a uniform electrical current flow from the junctions 6,7 towards the gate area 8. As the dummy gate structure 9 is still present during implanting the source 6 and drain 7 regions the doping of the exposed source 6 and drain 7 regions is self-aligned to this dummy gate structure 9. Incorporating of the dopants within the source 6 and drain 7 regions of the FinFET devices according to one aspect of the invention can be done simultaneously with doping their counterparts of the planar MOS devices. Optionally a silicide 15 (FIG. 3 b), e.g. TiSi2, CoSi2, can be formed on the source 6 and drain 7 areas prior to covering the substrate surface with a dielectric layer. Methods for forming silicides are known to persons skilled in the art. The dummy gate 9 allows forming selectively silicides on the exposed source 6 and drain 7 areas. A dielectric layer or stack of layers 16 is formed over the substrate comprising the field regions 5 and the active area regions 4 which comprise doped source 6 regions, doped drain 7 regions and the dummy gate structure 9 which covers the gate region 8 (FIGS. 3 a, 3 b). This dielectric layer 16 is sometimes referred to as the premetal dielectric (PMD) as it concludes in conventional CMOS processing the front end processing of the active devices being the planar CMOS and/or BiCMOS transistors. In one embodiment, this dielectric layer 16 is an oxide or oxide-like layer formed using CVD processes, such as plasma-enhanced CVD. After forming this planarizing dielectric 16 the substrate is polished, layer 11 of the dummy gate structure 9 is substantially exposed. This planarization by CMP will provide a surface having topography typically within 10 to 5%. The top layer 11 of the dummy gate 9 will act as a polish-stop layer during this polishing in order to have a polishing process that uses endpoint detection rather than a timed polishing step. During this polishing process, only the dummy gates 9 are exposed while the remainder of the substrate is covered with the dielectric 16 (FIGS. 3 a, 3 b). FIG. 3 a and 3 b show the cross-sections AA and BB of the inverter after polishing of the insulating dielectric 16 and exposure of the top surface of the dummy gate 9. The active areas in which the classical planar devices are made, preferably remains covered with the insulating dielectric 16. After forming the lateral isolation 5 of the active areas 4 and planarizing the dielectric 16 covering the substrate 1, thereby exposing the top layer 11 of the dummy gate 9, the fin-part of the FinFET will be defined. In the active areas 4 in which FinFETs will be formed, patterning of the homogeneous semiconductor layer 2 is done to yield the semiconductor fin 17 having the desired cross-sectional width �w� (FIGS. 4 a, 4 b). The semiconductor fin 17 connects the source 6 and drain 7 regions. In other active areas where the dummy gate structure 9 is still present but where replacement gate MOSFETs are to be formed, this additional patterning will be omitted because the dummy gate 9 will be completely removed, while in some active area's classical devices are formed without dummy gate and hence this patterning is also obsolete in these areas. In the course of the proposed process flow the dummy layers 10 and 11 which optionally comprise layers 12,13, that constitute the dummy gate stack 9, are patterned twice to finally form the semiconductor fin 17. In a first pattering step the dummy gate 9 is formed to outline and to separate and space apart the source 6 and drain 7 regions. The spacing �s� between the source 6 and drain 7 regions corresponds to the length of the semiconductor fin 17. The second patterning that is now introduced, defines the cross-sectional width �w� of the fin 17 orthogonal to the spacing �s� (FIG. 6 c). The dummy gate 9 and the semiconductor layer 2 underneath it are patterned to define the fin 18 (FIG. 6 b) which comprises a top element 19 (FIG. 6 a) formed in the dummy stack materials, e.g., the oxide 10 and polysilicon 12 and/or nitride 13 and a bottom element 17 which is the semiconductor fin. The selective removal of the exposed dummy gate stack 9 and the underlying semiconductor material 2 can be done in a single step. Both the exposed parts of the dummy gate 9 and the semiconductor material 2 are then removed using the resist pattern as a masking layer. FIG. 4 a shows the cross-section AA in case the dummy gate 9 and the underlying semiconductor layer 2 are patterned in a single step, self aligned to each other, to create an open cavity 25 in which respectively the dummy fin 19 and the semiconductor fin 17 are present. The selective removal of the exposed dummy gate stack 9 and the underlying semiconductor material 2 can also be done in a two-step process. First the dummy gate 9 is patterned to yield the top element 19 using the resist pattern as a masking layer as shown in FIG. 4 b. By patterning the dummy gate a part of the open cavity 25 is now created in the dielectric 16 whose dimensions correspond to those of the dummy gate 9. Within the cavity 25 a dummy pattern 18 (FIG. 6 b) remains extending from the source 6 to the drain 7. After removing this patterned resist layer the patterned dummy gate stack or dummy fin 19 serves as a hardmask for the etching, self-aligned to the dummy fin 19 and the semiconductor layer 2, to yield the semiconductor fin 17. In this second etching the partially formed open cavity 25 is extended from the planarized dielectric 16 into the underlying semiconductor layer 2 to finally yield the complete open cavity 25 separating the source 6 and drain 7 area. The patterning of the fin 18 can be done using any lithographic technology. For example, photolithographic technologies such as 248 nm or 193 nm DUV technology, which are used to define dimensions in the range of 100 to 400 nanometer in the photosensitive resist layer, can be applied. In one embodiment of the invention, e-beam lithography is applied to define dimensions in the photosensitive resist layer of 100 nm or less, typically 50 nm or less. The thus formed resist pattern then masks the underlying layer or layers during the subsequent etching. Preferably, this etching is a dry etching because sub 100 nm features are to be formed in the dummy gate stack 9 and in the underlying semiconductor material 2. FIG. 4 a shows the cross-sectional view AA of the inverter circuit after the dummy and semiconductor fin patterned and before the dummy fin 19 is at least partially removed. FIG. 4 b shows the cross-sectional view AA of the inverter circuit after the dummy fin 19 is patterned. FIG. 4 c shows a cross-sectional view BB of FIG. 4 a. FIG. 4 d is a top view of the inverter circuit at this stage of the processing. The substrate 1 is covered with the dielectric 16. Only the cavity 25 between the source 6 and drain 7 region is exposed. Within this cavity 25 the fin 17 (only the dummy fin 19 is shown in FIG. 4 c) extends from the source side 6 to the drain side 7. For the purpose of teaching the perimeter of the active area 4 is indicated by a dashed line in FIG. 4 d. At this stage of the processing the cavity 25 is not filled. As can be seen in FIG. 4 d, the source 6, drain 7 and the semiconductor fin 17 underneath the dummy fin 19 are formed in the same semiconductor layer 2. Both source 6 and drain 7 stretch out on the left and on the right side of the semiconductor fin 17. Because the width of source 6 and drain 7 region is larger than the width of the semiconductor fin 2, contacting of the source 6 and drain 7 during the back-end-of-line processing is made easier. In case of double gate devices, the dummy fin 19 is partly removed. As shown in FIGS. 5 a and 5 b, a top part 13 of the patterned dummy gate stack 19 is removed to have the surface of the fin 18 (FIG. 6 b) below the level of the planarized dielectric 16. In FIG. 5 a the dashed square shows the removed part 13 of the dummy fin 19 whereby the as-deposited thickness d is reduced to the thickness d′. In the example given the nitride part 13 is selectively removed and the polysilicon part 12 is exposed. In case of triple gate devices the complete dummy fin 19 on top of the patterned semiconductor film 17 is selectively removed thereby exposing not only the sides but also the top surface of the semiconductor fin 17 as shown in FIGS. 7 a and 7 b. After patterning the semiconductor fin 17 and lowering the surface of the fin 18 below the level of the planarizing dielectric 16, a short thermal oxidation can be performed to oxidize the exposed surfaces of the semiconductor fin 17. The thus-formed sacrificial oxide will be removed using a wet etching, e.g., a HF-based solution. This sequence of thermally oxidizing and wet etching of the thus formed oxide will remove the etching damage from the surface of the semiconductor fin 17. The width �w� of the semiconductor fin 17 can also be reduced, as a controlled part, i.e., the oxidized part, of the semiconductor fin 17 will be removed thereby thinning the semiconductor fin 17 below its lithographic defined width. At this stage in the processing in the selected active area regions 4, a monolithic structure is present comprising a homogeneous semiconductor layer 2 in which a doped source 6 and drain regions 7 and a semiconductor fin 17 in between are formed. A dielectric layer 14 covers this monolithic structure only exposing the spacing 8 between the source 6 and drain 7 regions. Within this cavity having lateral dimensions corresponding to the spacing 8 the fin 18 having lateral dimensions �s� and �w� connects the source 6 and the drain 7. Referring to FIGS. 6 a and 6 b, sidewall spacers 21 are now formed against the side walls of the cavity 25 formed in the dielectric 16 and the semiconductor layer 2. A dielectric layer 20 typically nitride, or a stack of layers, is deposited in a uniform way over the surface of the substrate, followed by anisotropically etching, e.g., dry etching, this dielectric layer 20 to form spacers 21. This etching creates the spacers 21 against the walls of the cavity 25 also on top of the lowered fin 18. No spacers 21 are formed on the sides of the fin 17. So the sides of the fin 17, including the sides of the dummy fin 19, are essentially free from the spacer dielectric 20 and remain exposed. These inside spacers 21 hence overlap the sidewalls of the source 6 and drain regions 7 adjacent to the fin 17 and form an insulating layer over these sidewalls. On the top surface of the fin 17 adjacent to the source 6 and drain 7 region also spacers 21 are formed. At this stage of the processing the source and drain regions 6, 7 are wrapped by dielectric material: in lateral direction at three sides by the field 5 dielectric surrounding the active area 4 and by the sidewall spacers 21, in vertical direction by the planarizing dielectric 16 and by the oxide layer 3. The height of this inside spacer 21 depends on the thickness of the deposited layers 20, the thickness of the semiconductor layer 2, including the epitaxial layer 14 if present, the planarizing dielectric layer 16 and on the spacer. By offsetting the top of the fin 18 by at least partially removing the dummy fin 19 process latitude is created to free the sides of the fin 17 from the spacer material 20 and still have spacers 21 formed against the sides of the cavity. These inside spacers reduce the parasitic coupling between the gate electrode 24 and the source 6/drain 7 regions thereby improving the operation of the device. If replacement gate transistors are to be formed, the complete dummy gate 9 of these replacement gate transistors is now selectively removed to expose the unpatterned semiconductor layer 2 in between the source 6 and drain 7 region. FIGS. 6 a and 6 b show the cross-sections of the inverter circuit after forming the inside spacers 21 for dual gate transistors. FIGS. 7 a and 7 b show the cross-sections of the inverter circuit for triple gate transistors after forming the inside spacers 21. In this case the dummy gate stack 19 is completely removed from the semiconductor fin 17. After forming the doped source 6, the doped drain 7 and defining the semiconductor fin 17 in the same layer 2 of semiconductor material of the insulated active area region 4 and covering the surfaces of the source and drain regions with dielectric layers 16 and sidewall spacers 21, the final gate stack is formed. This gate stack is used for both the FinFET devices according to one aspect of the invention as well as for the replacement gate devices. First the gate dielectric 22 (FIG. 8 b) is formed at least on the exposed surfaces of the semiconductor fin 17 and of the exposed surface of the unpatterned semiconductor layer 2 in case of the replacement gate device. This gate dielectric 22 can be an oxide, formed by thermal oxidation of the exposed semiconductor material. High-k materials allowing a small equivalent-oxide-thickness (EOT) for thicker layers can also be applied. Such layers can be deposited over the surface of the substrate or selectively formed on the exposed surfaces of the semiconductor fin 17, e.g., by atomic layer CVD. Then conductive material 23 is deposited, typically to conformably cover the surface of the substrate 1, to form, after patterning, the gate electrode 24. The workfunction of this conductive material 23 must be selected or modified to yield the desired threshold voltage of the FinFET. Polycrystalline silicon can be used and its workfunction can be modified by incorporating the desired amount and type of dopants such as B, P, As, Sb, or by adding alloys such as Ge. Metals can be applied as gate electrode material if these metals posses the desired workfunction. In case CMOS devices are formed appropriate metals are to be selected to form respectively the nMOS and the pMOS gate electrode. Midgap metals can be used to serve as gate electrode for both the nMOS and the pMOS transistor. The invention allows the use of high-k dielectrics and/or metal gates as the insulating layer 16 is only removed in those areas 8 where these high-k dielectrics 22 and/or metals 23 should be applied whereas the other regions remains protected by this layer 16. In this embodiment the cavity, formed in the planarizing dielectric 14 and in the semiconductor layer 2 by patterning the dummy gate 9 and the underlying semiconductor layer 2, is filled with the stack of gate dielectric 22 and gate electrode material 23. If no gate dielectric 22 is present and the gate electrode 24 is directly contacting the semiconductor fin 17 a planar BiCMOS device instead of a CMOS device can be formed. The source 6 and drain 7 region are then used as emitter and collector regions while the gate electrode 24 acts as base electrode. The gate of the FinFET is then defined by patterning the gate electrode material 23 in such a way that the gate electrode 24 extends over the cavity 25. This T-shaped gate electrode 24 will overlap the source 6 and drain 7 regions, but by selecting an appropriate thickness for the planarizing dielectric layer 14 the parasitic capacitance between the gate electrode 24 and the source 6 and drain 7 regions is kept low compared to the capacitance of the gate dielectric 21. FIGS. 8 a and 8 b show the cross-section of the inverter circuit for triple gate transistors with a T-shaped gate electrode using oxide as gate dielectric 22. Alternatively chemical-mechanical-polishing (CMP) can be used to locally remove the gate electrode material 23 and to create a gate electrode 24. In case high-k gate dielectrics 21 and/or metals 23 are used, CMP is applied to planarize the substrate surface and to remove at least the gate electrode material 23 outside the cavity 25 in the planarizing dielectric layer 16. FIGS. 9 a and 9 b show the cross-section of the inverter circuit for triple gate transistors using oxide as gate dielectric 22 when gate electrode material 23 is polished down to the insulating dielectric 16. In one embodiment the semiconductor fin 17 is not doped. Optionally a high temperature anneal step can be given to diffuse dopants out of the doped source 6 and drain 7 regions into the semiconductor fin 17. The dopant diffusion into the semiconductor fin 17 is preferably limited to the region underneath the inside spacer 21 on top of the semiconductor fin 17 and should essentially not diffuse in the channel region 26 of the fin. FIG. 7 b shows for the pMOS device 41 the channel region 26 having a length �l� located in between the sidewall spacers 21 on top of the semiconductor fin 17. The thus doped part of the semiconductor fin 17 forms a good conductive connection between the channel part 26 of the transistor and the source 6 and drain 7 regions resulting in a lower overall series resistance of the transistor. This high temperature annealing can be a separate step, but preferably this high temperature anneal process also activates the dopants incorporated in all semiconductor elements of the device or circuit. In case of a metal 23 or high-k dielectric 22 this anneal process is given prior to the deposition of the metal 23 or high-k dielectric gate 21 whatever comes first. If a semiconductor material is used as gate material 23 is formed, this outdiffusion can be done after the deposition and doping of the semiconductor gate. The diffusion of dopants into the semiconductor fin 17 is also needed to compensate for the offset between source 6 and drain 7 regions and channel area 26. Fine-tuning of the source/drain and well implantations, and anneal conditions is needed in order to provide sufficient outdiffusion and avoid misalignment between the channel 26 and the source 6 and drain 7 areas. The process sequence according to one aspect of the invention is a gate last process. Additional process steps can be performed such as additional local manipulation and modification of at least of the channel part 26 of the semiconductor fin 17. Examples of such extra local processing are incorporating of Ge in the channel region 26 or nitridation of the channel region to prevent outdiffusion of dopants from underneath the spacers 21 into the channel region 26. A standard back-end-of-line (BEOL) processing will complete the processing. This BEOL process comprises forming insulating layers, defining vias and trenches in these insulating layers to contact underlying devices and interconnect levels, filing these vias and trenches with conductive materials to obtain the desired interconnect scheme. A person skilled in the art knows this part of a CMOS process flow and the various alternatives, such as dual damascene processing. While the above description has pointed out novel features of the invention as applied to various embodiments, the skilled person will understand that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made without departing from the scope of the invention. Therefore, the scope of the invention is defined by the appended claims rather than by the foregoing description. All variations coming within the meaning and range of equivalency of the claims are embraced within their scope. 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Sept. 2011International Business Machines CorporationA p-fet with a strained nanowire channel and embedded sige source and drain stressors* Vom Pr�fer zitiertKlassifizierungen US-Klassifikation438/300, 257/E29.137, 257/E27.111, 257/E21.635, 257/E21.703, 438/303, 257/E27.112, 257/E21.444, 257/E29.283, 257/E21.43, 438/268Internationale KlassifikationH01L21/84, H01L21/336, H01L29/786, H01L21/8238, H01L27/12, H01L29/423 UnternehmensklassifikationH01L29/66545, H01L21/823821, H01L21/845, H01L21/823828, H01L29/66553, H01L29/78636, H01L27/12, H01L27/1211, H01L29/66628, H01L29/785, H01L29/42384 Europ�ische KlassifikationH01L21/84F, H01L27/12B4, H01L21/8238F, H01L29/66M6T6F9, H01L29/66M6T6F8, H01L27/12, H01L21/8238G, H01L29/786B6, H01L29/423D2B8, H01L29/78SJuristische Ereignisse DatumCodeEreignisBeschreibung8. M�rz 2013FPAYFee paymentYear of fee payment: 88. Juni 2009FPAYFee paymentYear of fee payment: 428. Nov. 2006CCCertificate of correction8. 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