Source: http://www.google.com/patents/US7556985?ie=ISO-8859-1&dq=5,963,646
Timestamp: 2016-02-12 05:46:05
Document Index: 515175299

Matched Legal Cases: ['art 40', 'art 25', 'art 25', 'art 40', 'arts 40', 'arts 25', 'arts 25', 'arts 40']

Patent US7556985 - Method of fabricating semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge...http://www.google.com/patents/US7556985?utm_source=gb-gplus-sharePatent US7556985 - Method of fabricating semiconductor deviceAdvanced Patent SearchPublication numberUS7556985 B2Publication typeGrantApplication numberUS 11/249,334Publication dateJul 7, 2009Filing dateOct 14, 2005Priority dateFeb 27, 1998Fee statusPaidAlso published asUS6455920, US6657282, US6784542, US6987054, US7064047, US20010011772, US20020089040, US20020089054, US20040012088, US20040259346, US20060030127Publication number11249334, 249334, US 7556985 B2, US 7556985B2, US-B2-7556985, US7556985 B2, US7556985B2InventorsNorio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu MoriokaOriginal AssigneeFujitsu Microelectronics LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (44), Referenced by (7), Classifications (48), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod of fabricating semiconductor device
US 7556985 B2Abstract
forming a resin layer on a principal surface of a semiconductor substrate carrying thereon a plurality of bump electrodes, such that said resin layer seals said principal surface of said semiconductor substrate, said bump electrodes projecting from a main surface of said resin layer in a direction away from said semiconductor substrate;
grooving said resin layer along a dicing line on said semiconductor substrate by a first blade having a first blade width, to form a groove such that said groove penetrates through said resin layer and reaches said semiconductor substrate; and
dicing, after said step of grooving, said semiconductor substrate along said groove by a second blade having a second blade width smaller than said first blade width, such that said semiconductor substrate is divided into individual semiconductor chips. Description
This application is a division of prior application Ser. No. 10/097,817, filed Mar. 15, 2002, now U.S. Pat. No. 6,987,054 which is a division of prior application Ser. No. 09/160,135, filed Sep. 25, 1998, now U.S. Pat. No. 6,455,920.
FIGS. 5A-5D are diagrams showing an example of the fabrication process of a conventional semiconductor device.
Further, the process of forming the semiconductor substrate 12A shown in FIGS. 5A-5D has a drawback in that the substrate 12A tends to show an undulation formed at the time of sawing the semiconductor crystal ingot by a wire saw machine. Such an undulation is difficult to be removed by a mere grinding process conducted by using the surface 13 as a reference surface.
a chamfer surface formed in a side wall of said semiconductor chip as a part of said side wall such that said chamfer surface surrounds said semiconductor chip along a top edge thereof,
FIGS. 5A-5D are diagrams showing a conventional process of forming a semiconductor substrate;
FIGS. 10A-10F are diagrams showing the fabrication process of a semiconductor device according to a fifth embodiment of the present invention;
FIGS. 11A-11F are diagrams showing the fabrication process of a semiconductor device according to a sixth embodiment of the present invention;
FIGS. 15A-15F are diagrams showing the fabrication process of a semiconductor device according to a ninth embodiment of the present invention;
FIGS. 17A-17E are diagrams showing the construction of a semiconductor device according to an eleventh embodiment of the present invention and the fabrication process thereof according to a twelfth embodiment of the present invention;
FIGS. 18A-18D are diagrams showing the fabrication process of a semiconductor device according to a thirteenth embodiment of the present invention;
FIGS. 19A-19C are diagrams showing the construction of a transportation tray according to a fourteenth embodiment of the present invention;
FIGS. 20A-20C are diagrams showing the construction of a transportation tray according to a fifteenth embodiment of the present invention;
FIGS. 21A-21C are diagrams showing the construction of a transportation tray according to a sixteenth embodiment of the present invention;
FIGS. 22A-22C are diagrams showing the construction of a transportation tray according to a seventeenth embodiment of the present invention;
FIGS. 27A-27C are diagrams showing the construction of a semiconductor device according to a twenty-second embodiment of the present invention;
FIGS. 32A-32C are diagrams showing the construction of a semiconductor device according to twenty-seventh and twenty-eighth embodiments of the present invention;
FIGS. 36A-36C are further diagrams showing the fabrication process of the thirty-first embodiment of the present invention;
FIGS. 38A-38C are further diagrams showing the fabrication process of the thirty-first embodiment of the present invention;
FIGS. 40A-40G are diagrams showing the fabrication process of a semiconductor device according to a thirty-third embodiment of the present invention;
FIGS. 42A-42G are diagrams showing the fabrication process of a semiconductor device according to a thirty-fifth embodiment of the present invention;
FIGS. 44A-44D are diagrams showing the fabrication process of a semiconductor device according to a thirty-seventh embodiment of the present invention.
Next, the fabrication process of the semiconductor device 20A according to a fifth embodiment of the present invention will be described with reference to FIGS. 10A-10F.
According to the present embodiment, the saw blade 27A acts directly on the wafer 51 exposed by the groove 56, and the efficiency of dicing of the wafer 51 is improved substantially as compared with the case in which the saw blade 27A cuts into the semiconductor wafer 51 through the resin layer as in the case of forming the conventional semiconductor device 10A. Associated with this, the problem of damaging of the semiconductor chip 21 or the resin layer 22, which tends to occur when cutting a structure in which a resin layer is formed on a semiconductor substrate by a saw blade, is successfully eliminated. As a result of the process of FIGS. 10A-10F, the semiconductor devices 20A each carrying the chamfer surface 24A on the top edge part thereof are mass produced efficiently.
FIGS. 11A-11F show another fabrication process of the semiconductor device 20A according to a sixth embodiment of the present invention.
Referring to FIGS. 11A-11F, the saw blade 27A explained with reference to FIG. 10D is applied to the resin layer 22 covering the semiconductor wafer 51 in the step of FIG. 11A such that the wafer 51 is divided to form the semiconductor chips 21, wherein the semiconductor wafer 51 is adhered to a dicing stage not illustrated in the step of FIG. 11B, and thus, the semiconductor chips 21 formed as a result of the dicing process maintain the position thereof as indicated in FIG. 11C, with a dicing groove 50 formed between adjacent semiconductor chips 21.
According to the process of FIGS. 11A-11E, in which the grinding process of FIG. 11E conducted by the saw blade 26 after the dicing process of FIG. 11D, the problem of wear of the V-shaped saw blade 26 is avoided successfully, by grinding along the dicing line 50 already formed. As a result of the process of FIGS. 11A-11F, the semiconductor devices 20A each carrying the chamfer surface 24A on the top edge part thereof are mass produced efficiently.
z 2<2(z 1�tan(θ/2)) (1)
in order that the chamfer surface 24A or 24B is to be formed. Thus, the cut-in depth z1 of the V-shaped saw blade 26 is controlled, in view of the edge angle θ or width z2 of the saw blade 27A, so as to satisfy the relationship of Eq. (1) during the grinding process of FIG. 10B or 11E or FIG. 12A or 14A, in order to form the desired chamfer surface 24A or 24B in any of the semiconductor devices 20A and 20C.
Next, the fabrication process according to a ninth embodiment of the present invention for forming the semiconductor device 20B of FIGS. 7A and 7B will be described with reference to FIGS. 15A-15F, wherein those parts corresponding to the parts described previously with reference to any preceding embodiments will be designated by the same reference numerals and the description thereof will be omitted.
According to the process of FIGS. 15A-15F, the semiconductor devices 20B explained previously are mass produced easily with a high yield of production, by switching the use of the saw blade 27A and the saw blade 27B having respective widths z2 and z4. Further, it should be noted that, while the saw blade 27A is used to cut the semiconductor wafer 51 including the resin layer 22 thereon, the depth of cutting the resin layer 22 by the saw blade 27A is reduced substantially as the saw blade 27A is applied along the groove 53 already formed by the saw blade 27B. Thereby, the disadvantageous effect, caused by the resin layer 22, on the cutting action of the saw blade 27A is successfully minimized and the dicing process of FIG. 15E is conducted efficiently and with high reliability.
FIGS. 17B-17E show the fabrication process of the semiconductor device 20E according to a twelfth embodiment of the present invention.
Next, the dicing process of FIGS. 10A-10F is applied to the wafer 51 in the step of FIG. 17D and the semiconductor devices 20E are formed as indicated in FIG. 17E. While not illustrated, each of the semiconductor devices 20E is defined by the chamfer surface 24A as represented in FIG. 17A.
FIGS. 18A-18D show the fabrication process of the semiconductor wafer 51 used in the previous embodiments, according to a thirteenth embodiment of the present invention.
FIGS. 19A-19C show the construction of a transportation tray 35A according to a fourteenth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIGS. 19A-19C, the transportation tray 35A is adapted to carry the semiconductor device 20A of the first embodiment and generally includes a tray main-body 36A and a cap 37A provided thereon, wherein the tray main-body 36A includes a chamfered surface 38A corresponding to the chamfered surface 24A of the semiconductor device 20A as indicated in FIG. 19A or 19C, and the semiconductor device 20A settles on the tray main-body 36A as indicated in FIG. 19B by engaging the chamfered surface 24A with the chamfered surface 38A of the tray main-body 36A.
FIGS. 20A-20C show the construction of a transportation tray 35B according to a fifteenth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIGS. 20A-20C, the transportation tray 35B is adapted to carry the semiconductor device 20B of the second embodiment and generally includes a tray main-body 36B and a cap 37B provided thereon, wherein the tray main-body 36B includes a stepped part 40A corresponding to the stepped part 25A of the semiconductor device 20B as indicated in FIG. 20A or 20C, and the semiconductor device 20B settles on the tray main-body 36B as indicated in FIG. 20B by engaging the stepped part 25A with the stepped part 40A of the tray main-body 36B.
FIGS. 21A-21C show the construction of a transportation tray 35C according to a sixteenth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIGS. 21A-21C, the transportation tray 35C is adapted to carry the semiconductor device 20C of the third embodiment and generally includes a tray main-body 36C and a cap 37C provided thereon, wherein the tray main-body 36C includes chamfer surfaces 38B corresponding to the chamfer surfaces 24B at the four corners of the semiconductor device 20B as indicated in FIG. 21A or 16C, and the semiconductor device 20C settles on the tray main-body 36C as indicated in FIG. 21B by engaging the chamfer surfaces 24B with the corresponding chamfer surfaces 38B of the tray main-body 36C.
FIGS. 22A-22C show the construction of a transportation tray 35D according to a seventeenth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIGS. 22A-22C, the transportation tray 35D is adapted to carry the semiconductor device 20D of the fourth embodiment and generally includes a tray main-body 36D and a cap 37D provided thereon, wherein the tray main-body 36D includes stepped parts 40B corresponding to the stepped parts 25B on the four corners of the semiconductor device 20D as indicated in FIG. 22A or 22C, and the semiconductor device 20D settles on the tray main-body 36D as indicated in FIG. 22B by engaging the stepped parts 25B with the corresponding stepped parts 40B of the tray main-body 36D.
Referring to FIGS. 23A and 23B, the semiconductor device 20F has a construction similar to that of the semiconductor device 20A except that a resin layer 41 is provided also on the rear or bottom surface of the semiconductor chip 21. The resin layer 41 is made of a material identical with to the material forming the resin layer 22 such as polyimide or epoxy and is formed by a compressive molding process so as to cover the entire bottom surface of the semiconductor chip 21.
FIGS. 27A-27C show the construction of a semiconductor device 20J according to a twenty-second embodiment of the present invention respectively in a side view, top view and a bottom view, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIGS. 27A-27C, the semiconductor device 20J has a construction similar to that of the semiconductor device 20A except that the semiconductor chip 21 is formed with another chamfer surface 42 such that the chamfer surface 42 surrounds the bottom surface of the semiconductor chip 21 similarly to the chamfer surface 24A, which surrounds the top surface of the semiconductor chip 21.
FIGS. 32A-32C show the construction of semiconductor devices 20P and 20Q according to twenty-seventh and twenty-eighth embodiments of the present invention, wherein FIG. 32A shows the semiconductor device 20P in a side view and FIG. 32B shows the semiconductor device 20Q in a side view, while FIG. 32C shows any of the semiconductor devices 20P and 20Q in a plan view. In the drawings, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Next, a fabrication process of any of the semiconductor devices 20L-20S will be described according to a thirty-first embodiment of the present invention with reference to FIG. 35 and further with reference to FIGS. 36A-36C.
Next, in the step of FIGS. 36A-36C, the wafer 51 is subjected to a dicing process along dicing lines 46X extending in the X-direction and further along dicing lines 46Y extending in the Y-direction, wherein the first dicing process conducted along the dicing lines 46X is carried out such that only the resin layer 22 and the semiconductor wafer 51 are cut by the dicing saw while the set film 45 is maintained substantially intact. Thus, after the foregoing first dicing process in the X-direction, the semiconductor wafer 51 maintains the integral state on the set film 45.
In each of the strips 47, it should be noted that the side walls of the semiconductor chip 21 are exposed at both lateral edges of the strip 47. Thus, the chamfer surface 44 is formed by applying the V-shaped saw blade 26 to the side walls of the semiconductor chips 21 from the lateral direction as indicated in FIGS. 38A-38C, wherein it can be seen that the saw blade 26 is pointed to the dicing groove formed in the first dicing process conducted in the X-direction between a pair of semiconductor chips 21 located adjacent with each other on the set film 45 as indicated in FIG. 38A. As a result of the process of FIG. 38B conducted subsequently to the step of FIG. 38A, a pair of chamfer surfaces 44 are formed simultaneously on the foregoing adjacent semiconductor chips 21 as indicated in FIG. 38C.
FIGS. 40A-40G are diagrams showing the fabrication process of the semiconductor device 20T according to a thirty-third embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Next, the resin layer 22 is applied to the semiconductor wafer 51 in the step of FIG. 40D so as to fill the foregoing V-shaped groove 49 and so as to protect the monolithic electronic circuits, and the saw blade 27A having a flat cutting edge surface is applied in the step of FIG. 40E in alignment with the center of the V-shaped groove 49. By dicing the wafer 51 in the step of FIG. 40F, the semiconductor wafer 51 is divided into a number of semiconductor devices each having the structure of the semiconductor device 20T. Similarly as before, the saw blade 27A has a blade width smaller than a width of the V-shaped groove 49 formed by the saw blade 26.
FIGS. 42A-42G show the fabrication process of a semiconductor device according to a thirty-fifth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
FIGS. 44A-44D are diagrams showing the fabrication process of the semiconductor device 20V according to a thirty-seventh embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
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H01L2924/01006, H01L23/3114, H01L2924/01005, H01L2224/73203, H01L2224/274, H01L2924/10158, H01L2924/01033, H01L21/78, H01L21/563, H01L2224/16225, H01L2924/10157, H01L2924/01023, H01L29/0657, H01L23/3107, H01L2924/01074, H01L2224/73204, H01L2924/01004, H01L2924/14, H01L2224/83191, H01L2924/04953, H01L21/56European ClassificationH01L24/28, H01L23/31H1, H01L23/562, H01L23/31H, H01L21/56, H01L21/56F, H01L21/78Legal EventsDateCodeEventDescriptionDec 9, 2008ASAssignmentOwner name: FUJITSU MICROELECTRONICS LIMITED,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021976/0089Effective date: 20081104Jul 9, 2010ASAssignmentOwner name: FUJITSU SEMICONDUCTOR LIMITED, JAPANFree format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:024651/0744Effective date: 20100401Dec 12, 2012FPAYFee paymentYear of fee payment: 4Apr 27, 2015ASAssignmentOwner name: SOCIONEXT INC., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU SEMICONDUCTOR LIMITED;REEL/FRAME:035508/0637Effective date: 20150302RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services