Source: http://www.google.com/patents/US6730966?dq=5998925
Timestamp: 2016-06-28 15:12:43
Document Index: 132773122

Matched Legal Cases: ['Application No. 10', 'Application No. 10', 'Application No. 8', 'Application No. 8', 'Application No. 9', 'Application No. 10', 'art 2', 'art 2', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'Application No. 09', 'Application No. 09', 'Application No. 09', 'Application No. 09', 'Application No. 09', 'Application No. 09', 'Application No. 09', 'Application No. 10', 'art 2']

Patent US6730966 - EL display using a semiconductor thin film transistor - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThere is provided an electric device which can prevent a deterioration in a frequency characteristic due to a large electric power external switch connected to an opposite electrode and can prevent a decrease in the number of gradations. The electric device includes a plurality of source signal lines,...http://www.google.com/patents/US6730966?utm_source=gb-gplus-sharePatent US6730966 - EL display using a semiconductor thin film transistorAdvanced Patent SearchPublication numberUS6730966 B2Publication typeGrantApplication numberUS 09/725,798Publication dateMay 4, 2004Filing dateNov 29, 2000Priority dateNov 30, 1999Fee statusPaidAlso published asCN1304182A, CN1722921A, CN1722921B, CN102176303A, CN102176303B, EP1107220A2, EP1107220A3, EP1107220B1, US6982462, US7525119, US8017948, US8890149, US20010002703, US20050001215, US20060033161, US20090218573, US20120061674Publication number09725798, 725798, US 6730966 B2, US 6730966B2, US-B2-6730966, US6730966 B2, US6730966B2InventorsJun KoyamaOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (60), Non-Patent Citations (43), Referenced by (212), Classifications (27), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetEL display using a semiconductor thin film transistor
US 6730966 B2Abstract
What is claimed is: 1. An electric device comprising:
a plurality of source signal lines; a plurality of gate signal lines; a plurality of power source supply lines; a plurality of power source control lines; and a plurality of pixels, each of the plurality of pixels including: a switching thin film transistor having a multi-gate structure, an EL driving thin film transistor, a power source controlling thin film transistor, and an EL element, and wherein the power source controlling thin film transistor controls a potential difference between a cathode and an anode of the EL element. 2. An electric device comprising:
a plurality of source signal lines; a plurality of gate signal lines; a plurality of power source supply lines; a plurality of power source control lines; and a plurality of pixels, each of the plurality of pixels including: a switching thin film transistor having a multi-gate structure, an EL driving thin film transistor, a power source controlling thin film transistor, and an EL element, wherein a light emitting period in one frame period is controlled by a digital data signal, said light emitting period being defined as a period in which the EL element emits a light and wherein the power source controlling thin film transistor controls a potential difference between a cathode and an anode of the El element. 3. An electric device comprising:
a plurality of source signal lines; a plurality of gate signal lines; a plurality of power source supply lines; a plurality of power source control lines, and a plurality of pixels, each of the plurality of pixels including: a switching thin film transistor having a multi-gate structure, an EL driving thin film transistor, a power source controlling thin film transistor, and an EL element, wherein one frame period includes n subframe periods SF1, SF2, . . . , SFn, wherein the n subframe periods include write-in periods Ta1, Ta2, . . . , Tan and display periods Ts1, Ts2, . . . , Tsn, wherein a plurality of digital data signals are inputted to all of the plurality of pixels in the write-in periods Ta1, Ta2, . . . , Tan, whether or not the plurality of EL elements emit a light in the display periods Ts1, Ts2, . . . , Tsn is selected by the digital data signals, wherein lengths of the write-in periods Ta1, Ta2, . . . , Tan are all identical, wherein a ratio of lengths of the display periods Ts1, Ts2, . . . , Tsn is expressed by 20:2−1: . . . : 2−(n-1), and wherein the power source controlling thin film transistor controls a potential difference between a cathode and an anode of the EL element. 4. A device according to claim 1,
wherein one of a source region and a drain region of the switching thin film transistor is connected to one of the plurality of source signal lines, and the other is connected to a gate electrode of the EL driving thin film transistor, wherein one of a source region and a drain region of the EL driving thin film transistor is connected to one of the plurality of power source supply tines, and the other is connected to one of a source region and a drain region of the power source controlling thin film transistor, wherein the other of the source region and the drain region of the power source controlling thin film transistor is connected to one of a cathode and an anode of the EL element, and wherein a gate electrode of the power source controlling thin film transistor is connected to one of the plurality of power source control lines. 5. A device according to claim 1,
wherein one of a source region and a drain region of the switching thin film transistor is connected to one of the plurality of source signal lines, and the other is connected to a gate electrode of the EL driving thin film transistor, wherein one of a source region and a drain region of the EL driving thin film transistor is connected to one of a source region and a drain region of the power source controlling thin film transistor, and the other is connected to one of a cathode and an anode of the EL element, wherein the other of the source region and the drain region of the power source controlling thin film transistor is connected to one of the plurality of power source supply lines, and wherein a gate electrode of the power source controlling thin film transistor is connected to one of the plurality of power source control lines. 6. A device according to claim 1, further comprising a capacitor between a gate electrode of the EL driving thin film transistor and one of the plurality of power source supply lines.
wherein each of the plurality of EL elements includes an EL layer between the anode and the cathode, and wherein the EL layer includes one selected from group consisting of a low molecular organic material and a polymer organic material. 8. A device according to claim 7,
wherein the low molecular organic material is one selected from the group consisting of Alq3 (tris-8-quinolilite-aluminum) and TPD (triphenyl amine derivative). 9. A device according to claim 7,
wherein the polymer organic material is one selected from the group consisting of PPV (polyphenylenevinylene), PVK (polyvinylcarbazole), and polycarbonate. 10. A device according to claim 1,
wherein one frame period is {fraction (1/60)}s or less. 11. A computer using the electric device of claim 1.
12. A video camera using the electric device of claim 1.
13. A DVD player using the electric device of claim 1.
14. A device according to claim 2,
wherein one of a source region and a drain region of the switching thin film transistor is connected to one of the plurality of source signal lines, and the other is connected to a gate electrode of the EL driving thin film transistor, wherein one of a source region and a drain region of the EL driving thin film transistor is connected to one of the plurality of power source supply lines, and the other is connected to one of a source region and a drain region of the power source controlling thin film transistor, wherein the other of the source region and the drain region of the power source controlling thin film transistor is connected to one of a cathode and an anode of the EL element, and wherein a gate electrode of the power source controlling thin film transistor is connected to one of the plurality of power source control lines. 15. A device according to claim 2,
wherein one of a source region and a drain region of the switching thin film transistor is connected to one of the plurality of source signal lines, and the other is connected to a gate electrode of the EL driving thin film transistor, wherein one of a source region and a drain region of the EL driving thin film transistor is connected to one of a source region and a drain region of the power source controlling thin film transistor, and the other is connected to one of a cathode and an anode of the EL element, wherein the other of the source region and the drain region of the power source controlling thin film transistor is connected to one of the plurality of power source supply lines, and wherein a gate electrode of the power source controlling thin film transistor is connected to one of the plurality of power source control lines. 16. A device according to claim 2, further comprising a capacitor between a gate electrode of the EL driving thin film transistor and one of the plurality of power source supply lines.
wherein each of the plurality of EL elements includes an EL layer between the anode and the cathode, and wherein the EL layer includes one selected from group consisting of a low molecular organic material and a polymer organic material. 18. A device according to claim 17,
wherein the low molecular organic material is one selected from the group consisting of Alq3 (tris-8-quinolilite-aluminum) and TPD (triphenyl amine derivative). 19. A device according to claim 17,
wherein the polymer organic material is one selected from the group consisting of PPV (polyphenylenevinylene), PVK (polyvinylcarbazole), and polycarbonate. 20. A device according to claim 2,
wherein one frame period is {fraction (1/60)}s or less. 21. A computer using the electric device of claim 2.
22. A video camera using the electric device of claim 2.
23. A DVD player using the electric device of claim 2.
24. A device according to claim 3,
wherein one of a source region and a drain region of the switching thin film transistor is connected to one of the plurality of source signal lines, and the other is connected to a gate electrode of the EL driving thin film transistor, p1 wherein one of a source region and a drain region of the EL driving thin film transistor is connected to one of the plurality of power source supply lines, and the other is connected to one of a source region and a drain region of the power source controlling thin film transistor, wherein the other of the source region and the drain region of the power source controlling thin film transistor is connected to one of a cathode and an anode of the EL element, and wherein a gate electrode of the power source controlling thin film transistor is connected to one of the plurality of power source control lines. 25. A device according to claim 3,
wherein one of a source region and a drain region of the switching thin film transistor is connected to one of the plurality of source signal lines, and the other is connected to a gate electrode of the EL driving thin film transistor, wherein one of a source region and a drain region of the EL driving thin film transistor is connected to one of a source region and a drain region of the power source controlling thin film transistor, and the other is connected to one of a cathode and an anode of the EL element, wherein the other of the source region and the drain region of the power source controlling thin film transistor is connected to one of the plurality of power source supply lines, and wherein a gate electrode of the power source controlling thin film transistor is connected to one of the plurality of power source control lines. 26. A device according to claim 3, further comprising a capacitor between a gate electrode of the EL driving thin film transistor and one of the plurality of power source supply lines.
27. A device according to claim 3,
wherein each of the plurality of EL elements includes an EL layer between the anode and the cathode, and wherein the EL layer includes one selected from group consisting of a low molecular organic material and a polymer organic material. 28. A device according to claim 27,
wherein the low molecular organic material is one selected from the group consisting of Alq3 (tris-8-quinolilite-aluminum) and TPD (triphenyl amine derivative). 29. A device according to claim 27,
wherein the polymer organic material is one selected from the group consisting of PPV (polyphenylenevinylene), PVK (polyvinylcarbazole), and polycarbonate. 30. A device according to claim 3,
wherein one frame period is {fraction (1/60)}s or less. 31. A computer using the electric device of claim 3.
32. A video camera using the electric device of claim 3.
33. A DVD player using the electric device of claim 3.
The length of the display periods is set so as to become Ts1: Ts2: Ts3: . . . : Ts(n-1): Tsn=20: 2−1: 2−2: . . . : 2−(n-2): 2−(n-1). Note that SF1 to SFn may appear in any order. A desired gradation display, from among the 2n gradations, can be performed by combining the display periods.
The display period is any period from Ts1 to Tsn. Predetermined pixels are turned on for the Tsn 1 period here.
Similar operations are repeated in the remaining (n−2) subframe periods, Ts(n-2), Ts(n-3), . . . , and Ts1 are set, in order, to be the display period, and predetermined pixels are turned on in the respective subframe periods.
In the EL display device, in the case where a light emission amount of 200 cd/m2 is obtained, a current of several mA/cm2 is required. For example, in the case where an EL material of 5 mA/cm2is used and a display device of 40 inches is formed, a current value necessary for a display becomes about 25 A, which is a considerable value.
According to the present invention, there is provided an electric device comprising a plurality of source signal lines, a plurality of gate signal lines, a plurality of power source supply lines, a plurality of power source control tines, and a plurality of pixels, characterized in that
a ratio of lengths of the display periods Ts1, Ts2, . . . , Tsn is expressed by 20:2−1: . . . :2−(n-1); and
An electric device according to the present invention may have such a structure that one frame period is {fraction (1/60)}s or less.
Note that a resistor may be provided between the drain region or the source region of the power source controlling TFT 112 and the EL element 111. By providing the resistor, it becomes possible to control an amount of current supplied from the power source controlling TFT to the EL element and to prevent the influence of fluctuation in characteristics of the power source controlling TFT and the EL driving TFT. The resistor has only to be an element showing a resistant value sufficiently larger than the on resistance of the power source controlling TFT 112 and the EL driving TFT 109, and has no limitation in structure or the like. Note that the on resistance means a value obtained by dividing a drain voltage of a TFT, when the TFT is in an on state, by a drain current flowing at that time. The resistance value of the resistor may be selected in the range of 1 kΩ to 50 MΩ (preferably, 10 kΩ to 10 MΩ, more preferably, 50 kΩ to 1 MΩ. When a semiconductor layer having a high resistance value is used as the resistor, its formation is easy and such a semiconductor layer is preferable.
First, in the write-in period, the power source controlling TFT 112 is in an off state, and an EL driver voltage is held 0 V. Note that although the EL driver voltage can have a minute value by a leak current caused by an off current (drain current flowing although a TFT as a switch is in an off state) of the EL driving TFT 109 or the power source controlling TFT 112, there is no problem if the value is so small that the EL element does not emit light. Then a gate signal is inputted to the gate signal line G1 and all switching TFTs 105 connected to the gate signal line G1 are turned on. Then digital data signals are inputted to the source signal lines (S1 to Sn). The digital data signal includes information of “0” or “1”. The digital data signal of “0” or “1” means a signal having a voltage of Hi or Lo.
The lengths of the display periods are set as to become Ts1:Ts2:Ts3: . . . :Ts(n-1):Tsn:20:2−1: . . . :2−(n-2):2−(n-1). However, the sequence of appearance of SF1 to SFn may be arbitrary. By the combination of the display periods, a desired gradation display among 2n gradations can be performed.
Similar operations are repeated in the remaining n−2 subframe periods, Ts(n-2), Ts(n-3), . . . , and Ts1 are set, in order, to be the display period, and predetermined pixels are turned on in the respective subframe periods.
Note that in this embodiment of the invention, in the write-in period, since the power source controlling TFT is in the off state and the EL driver voltage is kept 0 V, the EL element does not emit light. However, the present invention is not limited to this structure. Such a modification may be made that the power source controlling TFT is kept the on state, and an EL driver voltage having such magnitude that the EL element emits light is always supplied to the EL element in which the emission state is selected, so that even in the write-in period, a display is made similarly to the display period. However, in this case, since the whole subframe period becomes a period in which light emission is actually made, the lengths of the subframe periods are set so as to become SF1:SF2:SF3 . . . SF(n-1):SFn==20:2−1:2−2: . . . :2−(n-2):2−(n-1). By the above structure, as compared with a driving method in which light emission is not made in the write-in period, a picture image of high brightness can be obtained.
Then, ones of the source regions and the drain regions of the EL driving TFTs 1204 and 1214 are connected to the power source supply line 1220, while the other ones are connected to the source regions or the drain regions of the power source control TFT 1209 and 1219, respectively. The rest ones of the source regions and the drain regions of the power source control TFTs 1209 and 1219 are connected to the EL elements 1205 and 1215, respectively. The gate electrodes of the power source control TFT 1209 and 1219 are connected to the power source control line 1207. The capacitors 1208 and 1218 are connected to the power source supply line 1220. In this manner, in this embodiment, two adjacent pixels share one power source supply line 1220. As a consequence, as compared with the structure shown in FIG. 7A, number of the power source supply lines can be decreased. When the ratio of the wiring with respect to the whole pixel portion is small, the light shielding by the wiring can be suppressed in the case where the wiring is provided in a direction of the light emission of the EL layer.
Next, FIG. 8B shows another example of a circuit diagram of a pixel according to the present invention. In FIG. 8B, the pixel 1300 and the pixel 1310 are provided adjacent to each other. In FIG. 8B, reference numerals 1301 and 1311 denote the switching TFTs. Note that, in the present invention, as the switching TFT 1301 and 1311, either the n-channel type TFT or the p-channel type TFT can be used. In FIG. 8B, the n-channel type TFT is used as each of the switching TFTs 1301 and 1311. The gate electrodes of the switching TFTs 1301 and the 1311 are connected to the gate signal lines 1302 and 1312 for inputting the gate signal, respectively. One of the source region and the drain region of the switching TFT 1301 is connected to the source signal line 1303 for inputting digital video signal, while the other is connected to the gate electrode of the EL driver TFT 1304 and the capacitor 1308. One of the source region or the drain region of the switching TFT 1311 is connected to the source signal line 1303 for inputting the digital video signal, while the other is connected to the gate electrode of the EL driver TFT 1314 and the capacitor 1318. In this embodiment, the capacitor 1308 and 1318 can be omitted.
Then, ones of the source regions and the drain regions of the EL driving TFTs 1304 and 1314 are connected to the power source supply line 1320, while the other ones are connected to the source regions or the drain regions of the power source control TFTs 1309 and 1319, respectively. Ones of the source regions and the drain regions of the power source control TFTs 1309 and 1319 are connected to the EL elements 1305 and 1315, respectively. The gate electrode of the power source control TFTs 1309 and 1319 are connected to the power source control line 1307. And the capacitors 1308 and 1318 are connected to the power source supply line 1320. In this manner, in this embodiment, two adjacent pixels share one power source supply line 1320. As a consequence, as compared with the structure shown in FIG. 7B, number of the power source supply lines can be decreased. When the ratio of the wiring with respect to the whole pixel portion is small, the light shielding by the wiring can be suppressed in the case where the wiring is provided in a direction of the light emission of the EL layer.
Next, FIG. 4A shows another example of a circuit diagram of a pixel according to the present invention. In FIG. 4A, the pixel 1400 and the pixel 1410 are provided adjacent to each other. In FIG. 4A, reference numerals 1401 and 1411 denote the switching TFTs. Note that, in the present invention, as the switching TFT 1401 and 1411, either the n-channel type TFT or the p-channel type TFT can be used. In FIG. 4A, the n-channel type TFT is used as each of the switching TFTs 1401 and 1411. The gate electrodes of the switching TFTs 1401 and the 1411 are connected to the gate signal lines 1402 for inputting the gate signal. Ones of the source regions and the drain regions of the switching TFTs 1401 and 1411 are connected to the source signal lines 1403 and 1413 for inputting digital video signal, respectively, while the other ones are connected to the gate electrodes of the EL driver TFTs 1404 and 1414, the capacitors 1408 and 1418, respectively. In this embodiment, the capacitors 1408 and 1418 can be omitted.
Next, FIG. 4B shows another example of a circuit diagram of a pixel according to the present invention. In FIG. 4B, the pixel 1500 and the pixel 1510 are provided adjacent to each other. In FIG. 4B, reference numerals 1501 and 1511 denote the switching TFTs. Note that, in the present invention, as the switching TFT 1501 and 1511, either the n-channel type TFT or the p-channel type TFT can be used. In FIG. 4B, the n-channel type TFT is used as each of the switching TFTs 1501 and 1511. The gate electrodes of the switching TFTs 1501 and 1511 are connected to the gate signal lines 1502 and 1512 for inputting the gate signal, respectively. Ones of the source regions and the drain regions of the switching TFTs 1501 and 1511 are connected to the source signal line 1503 for inputting digital video signal, while the other ones are connected to the gate electrodes of the EL driver TFTs 1504 and 1514, the capacitors 1508 and 1518, respectively. In this embodiment, the capacitors 1508 and 1518 can be omitted.
Then, ones of the source regions and the drain regions of the EL driving TFTs 1504 and 1514 are connected to the power source supply line 1507, while the other ones are connected to the source regions or the drain regions of the power source control TFTs 1509 and 1519, respectively. The other ones of the source regions and the drain regions of the power source control TFTs 1509 and the 1519 are connected to the EL elements 1505 and 1515, respectively. The gate electrodes of the power source control TFTs 1509 and 1519 are connected to the power source control line 1520. And the capacitors 1508 an 1518 are connected to the power source supply line 1507. In this manner, in this embodiment, two adjacent pixels share one power source control line 1520. As a consequence, as compared with the structure shown in FIG. 7A, number of the power source control lines can be decreased. When the ratio of the wiring with respect to the whole pixel portion is small, the light shielding by the wiring can be suppressed in the case where the wiring is provided in a direction of the light emission of the EL layer.
Note that, in a circuit diagram shown in FIGS. 8A, 8B, 4A, 4B, 6A and 6B, an LDD region is provided in the active layer of the EL driving TFT, so that a region (referred to as the Lov region) may be formed wherein the LDD region and the gate electrode are overlapped via the gate insulating film. When the EL driving TFT is either an n-channel type TFT or a p-channel type TFT, the Lov region is formed on the side of the drain region of the active layer, with the result that a capacity can be further formed between the gate electrode of the EL driving TFT and the Lov region, and the gate electrode of the EL driving TFT can be retained. .
Note that, in a circuit diagram shown in FIGS. 8A, 8B, 4A, 4B, 6A and 6B, one or more among the switching TFT, the EL driving TFT and the power source control TFT may be formed into a multi-gate structure. By forming the switching TFT into a multi-gate structure, the off current can be decreased. Besides, in the case where the EL driving TFT and the power source control TFT are formed into the multi-gate structure, the deterioration of the EL driving TFTs or the power source control TFT by heat can be suppressed.
A gate electrode of the switching TFT 1801 is connected to a gate signal line 1802 to which a gate signal is inputted. One of a source region and a drain region of the switching TFT 180l is connected to a source signal line (also referred to as data signal line) 1803 to which a digital video signal is inputted and the other is connected to a gate electrode of an EL driving TFT 1804 and a capacitor 1808.
Furthermore, reference numeral 43 denotes a pixel electrode (EL element cathode) made from a conducting film with high reflectivity, and this is electrically connected to a drain region of the power source control TFT 3504. It is preferable to use a low resistance conducting film, such as an aluminum alloy film, a copper alloy film, and a silver alloy film, or a laminate of such films. Of course, a lamination structure with another conducting film may also be used.
In addition, a light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44 a and 44 b, which are formed by insulating films (preferably resins). Note that only one pixel is shown in the figures here, but the light emitting layer may be formed and divided to correspond to each of the colors R (red), G (green), and B (blue). A π conjugate polymer material is used as an organic EL material. Polyparaphenylene vinylenes (PPVs), polyvinyl carbazoles (PVKs), and polyfluoranes can be given as typical polymer materials.
For example, this embodiment shows an example of using a polymer material as a light emitting layer, but a low molecular weight organic EL material may also be used. Further, it is possible to use inorganic materials such as silicon carbide, as an electric charge transporting layer or an electric charge injecting layer. Known materials can be used for these organic EL materials and inorganic materials. A laminar structure EL layer, in which a hole injecting layer 46 made from PEDOT (polythiophene) or PAni (polyaniline) is formed on the light emitting layer 45, is used in this embodiment. An anode 47 is then formed on the hole injecting layer 46 from a transparent conducting film. The light generated by the light emitting layer 45 is radiated toward the upper surface (toward the top of the TFT) in this embodiment, and therefore the anode must be transparent to light. An indium oxide and tin oxide compound, or an indium oxide and zinc oxide compound can be used for the transparent conducting film. However, because it is formed after forming the low heat resistance light emitting and hole injecting layers, it is preferable to use a material which can be deposited at as low a temperature as possible.
By sealing the EL element in the filler 807 using the method as described above, the EL element can be completely shut off from the outside, and it is possible to prevent a material which promotes oxidation of an organic material, such as moisture or oxygen the outside of the outside, from entering. Thus, it is possible to fabricate an EL display device with high reliability.
In this embodiment, n-channel TFTs are used as a power source controlling TFT 902 and an EL driving TFT (not shown) in a pixel portion 901. Besides, a pixel electrode 903 is electrically connected to a drain of the power source controlling TFT 902, and this pixel electrode 903 is formed of a conductive film having a light shielding property. In this embodiment, the pixel electrode 903 becomes a cathode of the EL element.
The polysilicon film 509 can be thus obtained that is crystallized by a catalyst and is decreased to the level in which the catalyst does not obstruct the operation of a TFT. Thereafter, active layers 510-513 that use the polysilicon film 509 only are formed by a patterning process. At this time, a marker to conduct mask alignment in the following patterning should be formed by using the above polysilicon film. (FIG. 13D)
Thereafter, a silicon nitride oxide film 50 nm thick is formed by the plasma CVD method as shown in FIG. 13E, heating processing at 950� C. for 1 hour is then performed in an oxidation atmosphere, and a thermal oxidation process is performed. The oxidation atmosphere can be an oxygen atmosphere or another oxygen atmosphere in which halogen is added.
In this embodiment, boron is added by the ion doping method in which plasma excitation is performed without the mass separation of diborane (B2H6). The ion implantation method that performs the mass separation can be used, of course. According to this process, impurity regions 516 and 517 are formed that includes boron at the concentration of 1�1015 -1�10 18 atoms/cm3 (5�1016-5�1017 atoms/cm3 representatively).
Since the crystallization glass with high heat resistance is used in this embodiment, the activating process is performed by the furnace annealing processing at 800� C. for 1 hour. The thermal oxidation can be performed keeping a processing atmosphere in an oxidizing atmosphere, or the heat processing can be performed in an inert atmosphere.
Thereafter, with the gate electrodes 522-525 as masks, an n-type impurity element (phosphorus in this embodiment) is added in a self-alignment manner, as shown in FIG. 15A. At this time, an adjustment is performed so that phosphorus is added to the thus formed impurity regions 526-533 at the concentration of 1/2-1/10 (1/3-1/4 representatively) of that of the n-type impurity regions 520. Practically, the concentration is 1�1016-5�1018 atoms/cm3 (3�1017-3�1018 atoms/cm3 typically).
Thereafter, as shown in FIG. 15B, resist masks 534 a-534 d are formed to cover the gate electrode, an n-type impurity element (phosphorus in this embodiment) is then added, and impurity regions 535-539 including a high concentration of phosphorus are formed. The ion doping method using phosphine (PH3) is applied also herein, and an adjustment is performed so that the concentration of phosphorus in these regions is 1�1020-1�1021 atoms/cm3 (2�1020-5�1020 atoms/cm3 representatively).
Thereafter, as shown in FIG. 15C, the resist masks 534 a-534 d are removed, and a resist mask 542 is newly formed. A p-type impurity element (boron in this embodiment) is then added, and impurity regions 540, 541, 543 a, 543 b, 544 a and 544 b including a high concentration of boron are formed. Herein, according to the ion dope method using diborane (B2H6), boron is added to obtain a concentration of 3�1020-3�1021 atoms/cm3 (5�1020-1�1021 atoms/cm3 representatively).
Phosphorus has been already added to the impurity regions 540, 541, 543 a, 543 b, 544 a and 544 b at a concentration of 1�1020-1�1021 atoms/cm3. Boron added herein has at least three times as high concentration as the added phosphorus. Therefore, the impurity region of the n-type formed beforehand is completely changed into that of the p-type, and functions as an impurity region of the p-type.
Heat treatment is further performed at 300-450� C. for 1-12 hours in an atmosphere that includes hydrogen of 3-100% for hydrogenation. This is a process to hydrogen-terminate unpaired bonds of a semiconductor film by thernally excited hydrogen. As another means for hydrogenation, plasma hydrogenation (hydrogen excited by plasma is used) can be performed.
Regarding a detailed structure of the latches (A) 802, an example of a portion 804 of the latches (A) 802 which store the digital data signal corresponding to the source signal line SLine_a is explained. The portion 804 of the latches (A) 802 has two clocked invertors and two invertors.
As the electronic apparatuses, there are an EL display, video camera, digital camera, head mounted type display, car-navigator, personal computer, portable information terminal (mobile computer, mobile phone, electronic book, etc.), and picture reproducer provided with recording media (specifically, device which can reproduce a recording medium and equip a display capable of displaying the image such as compact disk (CD), laser disc (LD), or digital video disc (DVD)). Examples of the electronic apparatuses are shown in FIGS. 17A to 17E.
FIG. 17C depicts a part of a head mounted type EL display (right side), which includes a main body 2301, signal cable 2302, head fixation band 2303, display monitor 2304, optical system 2305, and display device 2306. The EL display pf the present invention can be used as the display portion.
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by examinerClassifications U.S. Classification257/350, 257/59, 257/72International ClassificationH01L27/32, G09G3/32, G09G3/30, G09G3/20Cooperative ClassificationG09G2300/0861, G09G2300/0417, H01L27/3244, H01L51/5253, G09G3/3291, G09G3/3275, G09G3/2022, G09G3/2018, G09G2300/0809, G09G2300/0842, G09G2300/0426, H01L27/1214, H01L51/5231, H01L27/12, G09G2320/0233, H01L27/124European ClassificationG09G3/32A14, H01L27/12, H01L27/12T, G09G3/32A14VLegal EventsDateCodeEventDescriptionNov 29, 2000ASAssignmentOwner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KOYAMA, JUN;REEL/FRAME:011316/0266Effective date: 20001030Sep 20, 2007FPAYFee paymentYear of fee payment: 4Sep 19, 2011FPAYFee paymentYear of fee payment: 8Oct 21, 2015FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS 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