Source: http://www.patentgenius.com/patent/6936519.html
Timestamp: 2018-09-22 22:22:53
Document Index: 272959530

Matched Legal Cases: ['art.\n3', 'art 136', 'art 138', 'art 138', 'art 136', 'art 136']

Double polysilicon bipolar transistor and method of manufacture therefor - Patent # 6936519 - PatentGenius
6936519 Double polysilicon bipolar transistor and method of manufacture therefor
Application: 10/224,111
Inventors: Chu; Shao-fu Sanford (Singapore, SG)
U.S. Class: 257/E21.379; 257/E29.03; 257/E29.034; 257/E29.183; 257/E29.191; 438/309; 438/312; 438/361
Field Of Search: 438/309; 438/310; 438/311; 438/312; 438/313; 438/314; 438/315; 438/316; 438/317; 438/318; 438/319; 438/320; 438/321; 438/322; 438/323; 438/324; 438/325; 438/326; 438/327; 438/331; 438/332; 438/333; 438/334; 438/335; 438/336; 438/337; 438/338; 438/339; 438/340; 438/341; 438/342; 438/343; 438/344; 438/345; 438/346; 438/347; 438/348; 438/349; 438/350; 438/351; 438/352; 438/353; 438/354; 438/355; 438/356; 438/357; 438/358; 438/359; 438/360; 438/361; 438/362; 438/363; 438/364; 438/365; 438/366; 438/367; 438/368; 438/369; 438/370; 438/371; 438/372; 438/373; 438/374; 438/375; 438/376
U.S Patent Documents: 4903104; 5365090; 5494836; 5773350; 6169007
Other References: EOhue, K. Oda, R. Hayami, and K. Washio, "A 7.7-ps CML Using Selective-Epitaxial SiGe HBTs", Proc. IEEE BCTM, pp. 97-100. 1998..
K. Washio, M. Kondo, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, and T. Harada, "A 0.2-.mu.m Self-Aligned SiGe HBT Featuring 107-GHz f.sub.max and 6.7-ps ECL", IEDM Tech Dig. Of Papers, pp. 557-560, 1999..
D.L. Harame, H.H. Comfort, J.D. Cressler, E.F. Crabbe, J. Y.-C. Sun, B.S. Meyerson, and T. Tice, "Si/SiGe Epitaxial-Base Transistors--Part I: Materials, Physics, and Circuits", IEEE Transactions on Electronic Devices, vol. 42, No. 3, pp. 455-468,Mar. 1995..
D.L. Harame, H.H. Comfort, J.D. Cressler, E.F. Crabbe, J. Y.-C. Sun, B.S. Meyersonn, and T. Tice, "Si/SiGe Epitaxial-Base Transistors--Part II: Process Integration and Analog Applications", IEEE Transactions on Electronic Devices, vol. 42, No. 3,pp. 469-482, Mar. 1995..
Abstract: A bipolar transistor, and manufacturing method therefor, with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector region beside and spaced from the emitter structure. A dielectric layer is deposited over the substrate and connections are formed to the extrinsic base structure, the emitter structure and the collector region.
1. A method of manufacturing a bipolar transistor comprising: forming a substrate having a collector region; forming a base structure over the collector region; depositing a first polysilicon layer over the base structure; doping the first polysilicon layer to form an emitter polysilicon layer; depositing a thin dielectric layer over the emitter polysilicon layer; forming the emitter polysilicon layer to forman emitter structure having the thin dielectric layer over the emitter structure; forming a spacer around the emitter structure; depositing a second polysilicon layer over the emitter structure and the extrinsic base region; doping the secondpolysilicon layer to form a base polysilicon layer; planarizing the base polysilicon layer down to the first thin dielectric layer to remove the base polysilicon layer from over the emitter structure; forming the base polysilicon layer to form anextrinsic base structure over the collector region beside and spaced from the emitter structure by the spacer; depositing an interlayer dielectric layer over the substrate; and forming connections through the interlayer dielectric layer to theextrinsic base structure, the emitter structure, and the collector region.
2. The method as claimed in claim 1 wherein: forming the emitter structure is performed before forming the extrinsic base structure and after forming the base structure; and forming the extrinsic base structure includes: doping the basestructure to form an extrinsic base part on the collector region of the substrate; and depositing the second polysilicon layer over the extrinsic base part.
3. The method as claimed in claim 1 additionally comprising: depositing first and second dielectric layers over the substrate; exposing the collector region through the first and second dielectric layers; forming silicon germanium over thecollector region exposed through the first and second dielectric layers; forming an extrinsic base part of the silicon germanium using a rapid thermal anneal; and wherein: depositing the first polysilicon layer deposits the first polysilicon layer overthe first and second dielectric layers and the silicon germanium; depositing the second polysilicon layer deposits the second polysilicon layer over the first polysilicon layer; and forming an intrinsic base part of the silicon germanium using therapid thermal anneal.
4. The method as claimed in claim 1 wherein additionally comprising: forming a selective elevated source/drain as part of the extrinsic base structure and around the emitter structure and the spacer; and performing a rapid thermal anneal afterforming the emitter structure and the extrinsic base structure.
5. The method as claimed in claim 1 wherein: forming the substrate having a collector region includes: forming a collector tap, forming a buried collector, and forming a sub collector region; and
additionally comprising: forming a selectively implanted collector in the sub collector region of the substrate.
The present invention provides a bipolar transistor, and a method of manufacturing therefor, with a substrate having a collector region and a base structure thereon. An emitter structure is formed over the base structure and an extrinsic basestructure is formed over the base structure and over the collector region beside and spaced from the emitter structure. A dielectric layer is deposited over the substrate and connections are formed to the extrinsic base structure, the emitter structureand the buried collector. The bipolar transistor has faster operation, reduced size, consistent current driving capability, improved performance, and/or reduced cost over the prior art. The manufacturing method reduces the number of processing steps,provides for a smooth substrate over the intrinsic base region, reduces capacitance between the emitter and base structures, and eliminates emitter shadowing effect.
In one embodiment for an NPN transistor, the semiconductor substrate 102 is lightly P-doped and the sub collector region 114 is the semiconductor substrate 102 with lightly N- doped (5E16 to 8E17/cm.sup.3). The buried collector 104 and thecollector tap 112 have a N+ doping. The first and second STI's 108 and 110 can be conventional STI trenches with grown silicon oxide liners filled with deposited silicon oxide. The first and second thin dielectric layers 116 and 118 can be of siliconoxide and silicon nitride of a thickness less than about 600 .ANG..
It should be noted that the base material 122 is slightly trenched at shoulders 132 beside the emitter structure 134. The shoulders 132 form an extrinsic base part 136 of the base material 122 beside the emitter structure 134 and integral with athicker, intrinsic base part 138 of the base material 122 under the emitter structure 134. In the NPN example, the intrinsic base part 138 is moderately P- doped while the extrinsic base part 136 is heavily P- doped.
Also shown in FIG. 5 is an optional a selective elevated source/drain 144 and 146. An epitaxial layer is deposited selectively to form the elevated source/drains 144 and 146. In one embodiment, the elevated source/drains 144 and 146 are heavilyP- doped (1E19 to 1E20/cm.sup.3). This has the advantage that the collector epitaxial layer can be thinner as the extrinsic base part 136 of the base material 122 gets lifted up.
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