Source: http://www.google.com/patents/US6883053?dq=6,073,142
Timestamp: 2014-12-27 16:05:55
Document Index: 175724131

Matched Legal Cases: ['ARTs 16', 'ART 16', 'ARTs 16', 'ARTs 16', 'ART 16', 'ART 16', 'ART 16', 'ART 16']

Patent US6883053 - Data transfer control circuit with interrupt status register - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA data transfer control circuit includes several data receiver-transmitters, each having an interrupt identification register. Interrupt signals from the data receiver-transmitters are combined into a single interrupt signal by an interrupt controller. One of the data receiver-transmitters has an interrupt...http://www.google.com/patents/US6883053?utm_source=gb-gplus-sharePatent US6883053 - Data transfer control circuit with interrupt status registerAdvanced Patent SearchPublication numberUS6883053 B2Publication typeGrantApplication numberUS 09/975,323Publication dateApr 19, 2005Filing dateOct 12, 2001Priority dateDec 5, 2000Fee statusLapsedAlso published asUS20020078287Publication number09975323, 975323, US 6883053 B2, US 6883053B2, US-B2-6883053, US6883053 B2, US6883053B2InventorsNoriaki Shinagawa, Shusaku MaedaOriginal AssigneeOki Electric Industry Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (8), Non-Patent Citations (4), Referenced by (19), Classifications (10), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetData transfer control circuit with interrupt status registerUS 6883053 B2Abstract A data transfer control circuit includes several data receiver-transmitters, each having an interrupt identification register. Interrupt signals from the data receiver-transmitters are combined into a single interrupt signal by an interrupt controller. One of the data receiver-transmitters has an interrupt status register with bits indicating the logic levels of the interrupt signals from each of the data receiver-transmitters. A host device that receives the interrupt signal from the interrupt controller can read the interrupt status register to determine which data receiver-transmitter caused the interrupt, then read the interrupt identification register of that data receiver-transmitter to identify the interrupt source, without having to search through the interrupt identification registers of other data receiver-transmitters.
BACKGROUND OF THE INVENTION The present invention relates to a data transfer control circuit for transferring data between, for example, a personal computer and a card installed in the personal computer.
SUMMARY OF THE INVENTION An object of the present invention is to enable a host device to determine the source of an interrupt from a data transfer control circuit quickly.
When no interrupt source in any of the UARTs 16A, 16-1, . . . , 16-7 is active, all of the interrupt signals INT0, INT1, . . . , INT7 are at the inactive (high) logic level, so all bits in the interrupt status register ISR are in the low or �0� state. If INTR is also inactive (high), then all inputs to the AND gate 17 are high, so the interrupt signal INT output by the AND gate 17 is in the inactive (high) state.
If an interrupt request is triggered by some event in one of the UARTs, the corresponding interrupt signal (one of INT0 to INT7) goes low, setting the corresponding bit in the interrupt status register ISR in UART 16A to the �1� state. One of the eight signals output by inverter 19 then goes low, so the interrupt signal INT output by the AND gate 17 goes low, notifying the personal computer 1 that an interrupt has been requested.
The personal computer 1 now reads the interrupt status register ISR. By noting which bit in the interrupt status register ISR is set to �1� the personal computer 1 can tell which UART requested the interrupt. Next, the personal computer 1 reads the interrupt identification register IIR of that UART to identify the specific interrupt source, and performs processing to respond to the interrupt.
The interrupt signal INT output by the AND gate 17 also goes low if interrupt request signal INTR goes low. In this case, when the personal computer 1 reads the interrupt status register ISR, it finds all bits cleared to �1� indicating that the interrupt source is external to the UARTs and must therefore be the INTR signal. The personal computer then performs processing to respond to the INTR interrupt request.
The interrupt mask register IMR is an eight-bit register, the eight bits corresponding to UARTs 16A, 16B, 16-2, . . . , 16-7. When one of these bits is set to �1� interrupts from the corresponding UART are disabled. Only UARTs with bits cleared to �0� in the interrupt mask register can request interrupts of the personal computer 1.
When no interrupt source in any of the UARTs 16A, 16B, 16-2, . . . , 16-7 is active, all of the interrupt signals INT0, INT1, . . . , INT7 are at the high logic level, so all bits in the interrupt status register ISR are in the �0� state and the outputs of all of the AND gates 21-0 to 21-7 are low. The output of the NOR gate 23 is accordingly high. If the INTR interrupt request signal is also high, then both inputs to the AND gate 25 are high, so the interrupt signal INT output by the AND gate 25 is in the inactive (high) state.
If, for example, an interrupt source is triggered in UART 16A, but the mask bit (b0) of UART 16A is set to �1� in the interrupt mask register IMR, then the output of inverter 22-0 is low, so the output of AND gate 21-0 remains low, the output of NOR gate 23 remains high, and the interrupt signal INT sent to the personal computer 1 remains inactive (high).
If an interrupt source is triggered in UART 16A and the mask bit (b0) of UART 16A is cleared to �0� in the interrupt mask register IMR, then both inputs to AND gate 21-0 are high, so the output of AND gate 21-0 goes high and the output of NOR gate 23 goes low. The output signal INT of AND gate 25 therefore also goes low, notifying the personal computer 1 of an interrupt request.
As in the first embodiment, the personal computer 1 reads the interrupt status register ISR to identify the UART from which the interrupt originates, then reads the interrupt identification register IIR of that UART to identify the specific interrupt source. If all bits in the interrupt status register ISR are cleared to �0� the personal computer 1 recognizes that the interrupt is due to interrupt request signal INTR.
The UARTs or other data receiver-transmitters need not all be alike. For example, the PC may include a data receiver-transmitter having a so-called �doorbell register� for exchanging parallel message data with the personal computer 1.
The logic of the interrupt status register ISR can be reversed so that �0� indicates an interrupt request and �1� indicates that an interrupt is not requested. Similarly, the logic of the interrupt mask register IMR can be reversed so that �0� indicates the masked and �1� the unmasked state. In this case too, corresponding changes should be made in the logic gates shown in FIGS. 2, 3, and 4.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4420806 *Jan 15, 1981Dec 13, 1983Harris CorporationInterrupt coupling and monitoring systemUS5109513 *May 24, 1989Apr 28, 1992Fanuc Ltd.Interrupt control circuit for multi-master busUS5805929 *Jan 29, 1996Sep 8, 1998International Business Machines CorporationMultiple independent I/O functions on a PCMCIA card share a single interrupt request signal using an AND gate for triggering a delayed RESET signalUS5832277 *Mar 8, 1996Nov 3, 19983 Com CorporationSystem for arbitrating demand on memory during configuration of a computer add-on cardUS5937199 *Jun 3, 1997Aug 10, 1999International Business Machines CorporationUser programmable interrupt mask with timeout for enhanced resource locking efficiencyUS6272452 *Apr 2, 1998Aug 7, 2001Ati Technologies, Inc.Universal asynchronous receiver transmitter (UART) emulation stage for modem communicationUS6317819 *Feb 24, 1999Nov 13, 2001Steven G. MortonDigital signal processor containing scalar processor and a plurality of vector processors operating from a single instructionUS6732298 *Jul 31, 2000May 4, 2004Hewlett-Packard Development Company, L.P.Nonmaskable interrupt workaround for a single exception interrupt handler processor* Cited by examinerNon-Patent CitationsReference1 *"Four Port RS-232 Serial PCMCIA Card." Interworld Electronics. Online Jan. 27, 2002. Retrieved from Internet Dec. 7, 2004. <http://web.archive.org/web/20020127022820/http://www.ieci.com.au/products/Product_Page2.asp?Product_ID=90>.*2 *"Technical Data on 16550." Byterunner Technologies. Online Oct. 7, 1997. Retrieved from Internet Dec. 7, 2004. <http://web.archive.org/web/19971007042444/http://www.byterunner.com/16550.html>.*3 *"The Free On-Line Dictionary of Computing" [entry 'scratch']. Online Dec. 15, 1994. Retrieved Mar. 25, 2004. <http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?query=scratch>.4 *"UART Details." University of Colorado Electrical and Computer Engineering Department. Online Oct. 8, 1999. Retrieved from Internet Dec. 7, 2004. <http://web.archive.org/web/19991008124827/http://ece-www.colorado.edu/~ecen2120/Manual/uart/UART.html>.** Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7181596May 9, 2002Feb 20, 2007Ip-First, LlcApparatus and method for extending a microprocessor instruction setUS7185180May 9, 2002Feb 27, 2007Ip-First, LlcApparatus and method for selective control of condition code write backUS7302551Oct 29, 2002Nov 27, 2007Ip-First, LlcSuppression of store checkingUS7315921Aug 22, 2002Jan 1, 2008Ip-First, LlcApparatus and method for selective memory attribute controlUS7328328Aug 22, 2002Feb 5, 2008Ip-First, LlcNon-temporal memory reference control mechanismUS7373483May 9, 2002May 13, 2008Ip-First, LlcMechanism for extending the number of registers in a microprocessorUS7380103May 9, 2002May 27, 2008Ip-First, LlcApparatus and method for selective control of results write backUS7380109Aug 22, 2002May 27, 2008Ip-First, LlcApparatus and method for providing extended address modes in an existing instruction set for a microprocessorUS7389496 *Jul 2, 2003Jun 17, 2008Agere Systems Inc.Condition management system and a method of operation thereofUS7395412Aug 22, 2002Jul 1, 2008Ip-First, LlcApparatus and method for extending data modes in a microprocessorUS7415557Jun 6, 2006Aug 19, 2008Honeywell International Inc.Methods and system for providing low latency and scalable interrupt collectionUS7529912Mar 18, 2005May 5, 2009Via Technologies, Inc.Apparatus and method for instruction-level specification of floating point formatUS7543134Dec 1, 2004Jun 2, 2009Ip-First, LlcApparatus and method for extending a microprocessor instruction setUS7546446 *Mar 10, 2003Jun 9, 2009Ip-First, LlcSelective interrupt suppressionUS7596779 *Feb 19, 2004Sep 29, 2009Agere Systems Inc.Condition management callback system and method of operation thereofUS7647478Jun 5, 2007Jan 12, 2010Ip First, LlcSuppression of store checkingUS7647479Jun 5, 2007Jan 12, 2010Ip First, LlcNon-temporal memory reference control mechanismUS7707341 *Feb 25, 2005Apr 27, 2010Advanced Micro Devices, Inc.Virtualizing an interrupt controllerUS20100293314 *May 13, 2010Nov 18, 2010International Business Machines CorporationComputer system and method of controlling computer system* Cited by examinerClassifications U.S. Classification710/263, 710/262, 710/260International ClassificationG06F13/24, G06F13/14, G06K19/07, G06F13/12, G06F9/48Cooperative ClassificationG06F13/24European ClassificationG06F13/24Legal EventsDateCodeEventDescriptionJun 11, 2013FPExpired due to failure to pay maintenance feeEffective date: 20130419Apr 19, 2013LAPSLapse for failure to pay maintenance feesDec 3, 2012REMIMaintenance fee reminder mailedDec 4, 2008ASAssignmentOwner name: OKI SEMICONDUCTOR CO., LTD., JAPANFree format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022043/0739Effective date: 20081001Owner name: OKI SEMICONDUCTOR CO., LTD.,JAPANFree format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100216;REEL/FRAME:22043/739Sep 24, 2008FPAYFee paymentYear of fee payment: 4Oct 12, 2001ASAssignmentOwner name: OKI ELECTRIC INDUSTRY CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHINAGAWA, NORIAKI;MAEDA, SHUSAKU;REEL/FRAME:012254/0429Effective date: 20010921Owner name: OKI ELECTRIC INDUSTRY CO., LTD. 7-12, TORANOMON 1-Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHINAGAWA, NORIAKI /AR;REEL/FRAME:012254/0429RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google