Source: https://patents.google.com/patent/US9837528B2/en
Timestamp: 2019-10-21 13:08:42
Document Index: 17286742

Matched Legal Cases: ['application No. 2005', 'art 11', 'art 11', 'art 40', 'art 40', 'art 40', 'art 41', 'art 41', 'art 41']

US9837528B2 - Semiconductor device and manufacturing method of the same - Google Patents
US9837528B2
US9837528B2 US15/333,430 US201615333430A US9837528B2 US 9837528 B2 US9837528 B2 US 9837528B2 US 201615333430 A US201615333430 A US 201615333430A US 9837528 B2 US9837528 B2 US 9837528B2
US15/333,430
US20170040445A1 (en
2010-09-01 Priority to US12/873,495 priority patent/US8232610B2/en
2012-06-01 Priority to US13/486,738 priority patent/US8604563B2/en
2013-12-09 Priority to US14/100,462 priority patent/US9013006B2/en
2015-04-20 Priority to US14/690,783 priority patent/US9245973B2/en
2016-01-20 Priority to US15/001,767 priority patent/US9478530B2/en
2016-10-25 Priority to US15/333,430 priority patent/US9837528B2/en
2016-10-25 Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
2017-02-09 Publication of US20170040445A1 publication Critical patent/US20170040445A1/en
2017-12-05 Publication of US9837528B2 publication Critical patent/US9837528B2/en
229920005591 polysilicon Polymers 0 claims 4
230000001681 protective Effects 0 claims description 124
239000004065 semiconductor Substances 0 abstract claims description title 168
A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.
This application is a continuation of U.S. Ser. No. 15/001,767, filed on Jan. 20, 2016, which is a continuation U.S. Ser. No. 14/690,783, filed on Apr. 20, 2015, which is a continuation of U.S. Ser. No. 14/100,462, filed on Dec. 9, 2012, which, in turn, is a divisional of U.S. application Ser. No. 13/486,738, filed Jun. 1, 2012, which, in turn, is a second Continuation application of U.S. application Ser. No. 12/873,495, filed Sep. 1, 2010 (now U.S. Pat. No. 8,232,610), which, in turn, is a Continuation application of U.S. application Ser. No. 12/471,680, filed May 26, 2009 (now U.S. Pat. No. 7,834,407), which, in turn, is a Continuation application of U.S. application Ser. No. 11/432,491, filed May 12, 2006 (now abandoned), and the contents of which are hereby incorporated by reference into this application. This application is also related to Ser. No. 13/486,676 (U.S. Pat. No. 8,592,920) filed on Jun. 1, 2012, the same date as the present application of the parent application Ser. No. 13/486,738, and which shares the same inventors and parent applications as Ser. No. 13/486,738. The present application claims priority from Japanese patent application No. 2005-147914 filed on May 20, 2005, the content of which is hereby incorporated by reference into this application.
Then, as shown in FIG. 10, p-type impurities, such as boron (B), are introduced into the polycrystalline silicon film 8 formed over the semiconductor substrate 1 using the ion implantation method to form a p−-type semiconductor region 8 a. Thereafter, as shown in FIG. 11, a high concentration of n-type impurities is introduced into the p−-type semiconductor region 8 a of the power MISFET using the photolithography technique and the ion implantation method to form an n+-type semiconductor region 8 b. The n-type impurities include, for example, phosphorus (P), arsenic (As), and antimony (└). Subsequently, heat treatment (annealing process) is applied to the semiconductor substrate 1 at a temperature of, for example, 1100 degrees (L) or more. This heat treatment is carried out so as to increase a grain size (crystal grain size) of the polycrystalline silicon film 8 constituting the p−-type semiconductor region 8 a and the n+-type semiconductor region 8 b. As mentioned later, because the grain size of the p−-type semiconductor region 8 a, which is a part of the protective diode, is increased, the p−-type semiconductor region 8 a can decrease a leakage current from the protective diode. This is because the grain size of the semiconductor region 8 a is increased by high-temperature heat treatment, which leads to reduction in grain boundary across the pn junction of the protective diode (a boundary of the crystal grain). That is, since the grain boundary which may be the path of the leakage current, is reduced, the leakage current of the protective diode can be decreased. This high-temperature heat treatment is desirably carried out before forming the semiconductor region for the channel formation, as mentioned later. If the high-temperature heat treatment were carried out after forming the semiconductor region for the channel formation, the semiconductor region for the channel formation would be diffused, thus failing to achieve shallow junction of the channel part, which might be at a disadvantage in enhancing the performance of the power MISFET.
The polycrystalline silicon film (second polycrystalline silicon film) is formed over the semiconductor substrate 1 as well as on the gate insulating film 10. This polycrystalline silicon film is formed by, for example, the CVD method, with the n-type impurities added thereinto. That is, in forming the polycrystalline silicon film, for example, the n-type impurities, such as phosphorus or arsenic, are introduced into the polycrystalline silicon film. Thereafter, using the photolithography and etching techniques, the polycrystalline silicon film is subjected to patterning to form the gate electrode 11 a in the trench 6. The gate electrode 11 a has a recessed structure lower than the top part on the main surface side of the semiconductor substrate 1. By the application of patterning to the polycrystalline silicon film, the lead-out part 11 b for the gate electrode is formed. The lead-out part 11 b for the gate electrode is electrically connected to the gate electrode 11 a.
FIG. 20 is a plan view of the chip region CR subjected to the above-mentioned steps. As shown in FIG. 20, in the protective diode forming region, the p−-type semiconductor region 8 a and the n+-type semiconductor region 15 are formed to create the protective diode having the pn junction. As shown in the figure, in the power MISFET forming region, the source region 14 is formed.
More specifically, when the width of the trench 6 is 0.8 μm, the thickness of the insulating film 7 is 200 nm, and the thickness of the gate insulating film 10 is 50 nm, at least the polycrystalline silicon film for the dummy gate electrode 9 a may be deposited to a thickness of 200 nm or more so that the dummy gate electrode 9 a can be filled in the trench region having the width of 0.4 μm. In contrast, the polycrystalline silicon film for the gate electrode 11 a needs to be deposited to a thickness of 350 nm or more so that the gate electrode 11 a is required to be filled in the trench region having a width of 0.7 μm.
In forming the protective diode having the n+p− junction, the p−-type semiconductor region 8 a is formed by forming the intrinsic polycrystalline silicon film, and then implanting the boron ions into the entire surface of the intrinsic polycrystalline silicon film in a dose amount of about 1×1013/cm2 to 1×1014/cm2. In contrast, the n+-type semiconductor region 15 needs to be selectively formed. The n+-type semiconductor region 15 of the protective diode is formed at the same ion implantation step in which the source region of the power MISFET is selectively formed (at the step of introducing arsenic in an amount of about 1×1015/cm2 to 1×1016/cm2). This can form the protective diode without increasing the number of steps.
Referring to FIG. 25, the contact holes 17 connected to the lead-out part for the gate electrode and the contact holes 21 connected to the lead-out part for the dummy gate electrode are arranged linearly. The contact hole 17 is connected to the gate interconnection 25, while the contact hole 21 is connected to the source electrode 24. A part of the gate interconnection 25 which is connected to the contact hole 17 is a convex part 40 a. A part of the source electrode 24 opposite to the convex part 40 a is a recessed part 40 b. That is, in a position where the source electrode 24 on the contact hole 21 is formed in a recessed shape, the gate interconnection 25 on the contact hole 17 is formed in a convex shape. In contrast, a part of the source electrode 24 which is connected to the contact hole 21 is a convex part 41 a. A part of the gate interconnection 25 opposite to the convex part 41 a is a recessed part 41 b. That is, in a position where the source electrode 24 is formed in a convex shape, the gate interconnection 25 is formed in a recessed shape. With this layout arrangement, the effective area of the semiconductor chip CP can be increased. Note that in FIG. 25, parts of the source electrode 24 and the gate interconnection 25 are omitted so that the contact holes 17 and the contact holes 21 positioned under the gate interconnection 25 can be viewed.
1. A semiconductor device including a semiconductor chip, the semiconductor chip comprising:
a field-effect transistor including a drain region, a source region, a first gate electrode and a second gate electrode; and
a protective diode,
wherein the source region is electrically connected to one electrode of the protective diode,
wherein the second gate electrode is electrically connected to another electrode of the protective diode,
wherein a trench is formed in a semiconductor substrate,
wherein a first gate insulating film is formed in the trench and disposed at a lower part of the trench,
wherein the first gate electrode is formed over the first gate insulating film in the trench and disposed at the lower part of the trench,
wherein a second gate insulating film is formed in the trench and disposed at an upper part of the trench,
wherein a second gate electrode is formed over the second gate insulating film in the trench and disposed at the upper part of the trench, and
wherein a thickness of the first gate insulating film is thicker than a thickness of the second gate insulating film.
wherein each of the first gate electrode and the protective diode includes a first polysilicon film, and
wherein the second gate electrode includes a second polysilicon film.
wherein the protective diode is located outside of the trench.
wherein the first polysilicon film is formed of an n-type impurity,
wherein the second polysilicon film is formed of the n-type impurity, and
wherein the protective diode includes an n-type impurity region and a p-type impurity region.
wherein the source region is formed of the n-type impurity, is formed in the semiconductor substrate and is formed near the upper part of the trench, and
wherein the drain region is formed of the n-type impurity, is formed in the semiconductor substrate and is formed near the lower part of the trench.
6. A semiconductor device according to claim 1, wherein the one electrode of the protective diode is coupled to an anode region of the protective diode and wherein the other electrode of the protective diode is coupled to a cathode region of the protective diode.
7. A semiconductor device according to claim 6, wherein a plurality of protective diodes are connected between the second gate electrode and the source region of the field-effect transistor.
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