Source: http://www.google.com/patents/US7339935?dq=6859936
Timestamp: 2016-07-29 18:51:29
Document Index: 632054647

Matched Legal Cases: ['Application No. 10', 'Application No. 10', 'Application No. 10', 'art 62', 'art 64', 'art 60', 'art 62', 'art 64', 'art 62', 'art 62', 'art 1']

Patent US7339935 - ATM switch for distributing cells to avoid blocking in the ATM switch - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input...http://www.google.com/patents/US7339935?utm_source=gb-gplus-sharePatent US7339935 - ATM switch for distributing cells to avoid blocking in the ATM switchAdvanced Patent SearchPublication numberUS7339935 B2Publication typeGrantApplication numberUS 10/971,676Publication dateMar 4, 2008Filing dateOct 22, 2004Priority dateAug 21, 1998Fee statusLapsedAlso published asCA2280580A1, CA2280580C, EP0982970A2, EP0982970A3, EP0982970B1, US7136391, US7292576, US7474664, US20050053067, US20050053096, US20050083939Publication number10971676, 971676, US 7339935 B2, US 7339935B2, US-B2-7339935, US7339935 B2, US7339935B2InventorsSeisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki YamanakaOriginal AssigneeNippon Telegraph And Telephone CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (23), Non-Patent Citations (15), Referenced by (4), Classifications (17), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetATM switch for distributing cells to avoid blocking in the ATM switch
This application claims the benefit and priority of and is a division of U.S. patent application Ser. No. 09/376,904, filed Aug. 18, 1999, which claims foreign priority benefits under 35 U.S.C. � 119 of Japanese Patent Application No. 10-235957, filed Aug. 21, 1998; Japanese Patent Application No. 10-266802, filed Sep. 21, 1998 and Japanese Patent Application No. 10-266930, filed Sep. 21, 1998, all of which are incorporated herein by reference.
FIG. 8 shows an LSI chip configuration when transferring cells by splitting cells spatially. As shown in FIG. 8, when cells are split spatially by using a bit slicing technique, 160 G/3 throughput can be realized by one chip (16�2�(20/3)≈230, with 50 control lines). Therefore, a 160-G bits/s throughput can be realized with 3 chips at the minimum. In addition, hardware logic in the chip is used effectively since high speed lines for interconnecting between chips can be eliminated.
First, the general outline of a first embodiment of the present invention for cell resequencing in an ATM switch will be described. FIG. 11 shows a block diagram of the ATM switch according to the first embodiment of the present invention. As shown in FIG. 11, the ATM switch includes m basic switches ISW#1-ISW#m at a first stage, m basic switches TSW#1-TSW#m at a second stage and m basic switches OSW#1-OSW#m at a third stage, each of the basic switches having m input lines and m output lines and each of the basic switches of a stage being connected to basic switches of a next stage, thereby forming an m�m input and m�m output ATM switch.
FIG. 44 shows a modification of the third embodiment of the present invention. As shown in the figure, the ATM switch has a delay time inferring part 62 instead of the counter 50 0-50 N−1 and a comparing part 64 instead of the comparing part 60. The delay time inferring part 62 obtains an inferred delay time t of the switches 40 0-40 N−1, and the comparing part 64 compares bit information of short cells output from the switches 40 0-40 N−1 within a delay time t�τ. In addition, the delay time inferring part 62 compares between an input time of a timing cell which is a specific cell input to the switches and an output time of the timing cell output from the switches so as to obtain the inferred delay time t. In addition, the delay time inferring part 62 sends the timing cell periodically.
As shown in FIG. 56, when a cell arrives at the ATM switch in step 1, the cell distribution part determines a destination group of the switch in step 2. Here, the destination group represents an output basic switch of the third stage. Therefore, there are the same number of groups as that of the basic switches of the third stage. For example, there are N groups in a three-stage ATM switch using N N�N basic switches in a stage. For example, cells for output ports 1−N are grouped into group 1, cells for output ports N+1−2N are grouped into group 2, . . . , cells for output ports N2−N−N2 are grouped into group N. FIG. 56 shows a cell for the output port 2 which is grouped into group 1.
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New York, US, vol. 73, No. 9 Part 1, Sep. 1, 1990, pp. 1-11.13Sying-Jyan Wang "Load-Balancing in Multistage Interconnection Networks under Multiple-Pass Routing" Journal of Parallel and Distributed Computing, Academic Press, Duluth, MN, US, vol. 36, No. 2, Aug. 1, 1996, pp. 189-194.14Tom Chaney, J. Andrew Fingerhut, Margaret Flucke, Jonathan S. Turner "Design of a Gigabit ATM Switch" IEEE Infocom'97, 1997.15Yasukawa, et al., "Multi-Route ATM Switch Which Conserve Cell Sequence in Tournament Manner", IEICE General Conference, B-6-19 1998.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7644308 *Jan 5, 2010Hewlett-Packard Development Company, L.P.Hierarchical timestampsUS9331929Mar 29, 2012May 3, 2016Juniper Networks, Inc.Methods and apparatus for randomly distributing traffic in a multi-path switch fabricUS20070208839 *Mar 6, 2006Sep 6, 2007Voigt Douglas LHierarchical timestampsUSRE42600Aug 9, 2011Polytechnic UniversityScheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme* Cited by examinerClassifications U.S. Classification370/395.41, 370/396, 370/388International ClassificationH04L12/54, H04L12/933, H04L12/70, H04Q11/04Cooperative ClassificationH04L2012/5652, H04L12/5601, H04L2012/5681, H04Q11/0478, H04L2012/568, H04L49/1553, H04L2012/565European ClassificationH04L49/15E, H04Q11/04S2, H04L12/56ALegal EventsDateCodeEventDescriptionOct 17, 2011REMIMaintenance fee reminder mailedMar 4, 2012LAPSLapse for failure to pay maintenance feesApr 24, 2012FPExpired due to failure to pay maintenance feeEffective date: 20120304RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services