Source: http://www.google.com/patents/US8031156?dq=5920316
Timestamp: 2015-08-03 10:41:16
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Matched Legal Cases: ['art 123', 'art 122', 'art 123', 'art 122', 'art 123', 'art 122', 'art 123', 'art 122', 'art 123', 'art 122', 'art 123', 'art 122', 'art 123', 'art 122', 'art 123', 'art 122', 'art 230', 'art 220', 'art 220', 'art 220', 'art 220', 'art 220', 'art 232', 'art 220', 'art 220', 'art 220', 'art 232', 'art 220', 'art 220', 'art 220', 'art 232', 'art 220', 'art 220', 'art 220', 'art 232', 'art 220', 'art 220', 'art 220', 'art 232', 'art 220', 'art 220', 'art 220', 'art 232', 'art 220', 'art 220', 'art 220', 'art 232', 'art 220', 'art 220', 'art 220', 'art 232', 'art 220', 'art 220']

Patent US8031156 - Data driving circuit of liquid crystal display for selectively switching and ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA data driving circuit of a liquid crystal display for selectively switching and multiplexing voltages in accordance with a bit order of input data is disclosed. The data driver circuit includes: a voltage distributor that selects one of a first voltage and a second voltages as first output voltage in...http://www.google.com/patents/US8031156?utm_source=gb-gplus-sharePatent US8031156 - Data driving circuit of liquid crystal display for selectively switching and multiplexing voltages in accordance with a bit order of input dataAdvanced Patent SearchPublication numberUS8031156 B2Publication typeGrantApplication numberUS 11/819,939Publication dateOct 4, 2011Filing dateJun 29, 2007Priority dateJun 29, 2006Fee statusPaidAlso published asUS20080001149Publication number11819939, 819939, US 8031156 B2, US 8031156B2, US-B2-8031156, US8031156 B2, US8031156B2InventorsChul Sang Jang, Jin Chul ChoiOriginal AssigneeLg Display Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (7), Referenced by (2), Classifications (6), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetData driving circuit of liquid crystal display for selectively switching and multiplexing voltages in accordance with a bit order of input data
US 8031156 B2Abstract
A data driving circuit of a liquid crystal display for selectively switching and multiplexing voltages in accordance with a bit order of input data is disclosed. The data driver circuit includes: a voltage distributor that selects one of a first voltage and a second voltages as first output voltage in accordance with the most significant bit of input data including a plurality of n data bits, that multiplexes the first voltage and the second voltage to be output as one of more multiplexed output voltage is one of the first voltage and the second voltage selected in accordance with bits of the input data lower in significance than the most significant bit, and that outputs the first voltage as a final output voltage; and an output buffer that is driven by the first output voltage, the one or more multiplexed output voltages, and the final output voltage.
4. The data driving circuit of the liquid crystal display according to claim 3, wherein when ‘000’ data are received by the voltage distributor,
the switch connects the first voltage in response to the most significant bit of 0 of the received ‘000’ data to output the first voltage to the output buffer via the first output terminal, and
the multiplexing part multiplexes the first voltage and the second voltage in response to the lower 2 bits ‘00’ of the received ‘000’ data to output the first voltage to each of the second to fourth output terminals,
when ‘001’ data are received by the voltage distributor,
the switch connects the first voltage in response to the most significant bit 0 of the received ‘001’ data to output the first voltage to the output buffer via the first output terminal, and
the multiplexing part multiplexes the first voltage and the second voltage in response to lower 2 bits ‘01’ of the received ‘001’ data to output the second voltage and the two first voltages to the output buffer via the second to fourth output terminals, respectively,
when ‘010’ data are received by the voltage distributor,
the switch connects the first voltage in response to the most significant bit 0 of the received ‘010’ data to output the first voltage to the output buffer via the first output terminal, and
the multiplexing part multiplexes the first voltage and the second voltage in response to lower 2 bits ‘10’ of the received ‘010’ data to output the two second voltages and the first voltage to the output buffer via the second to fourth output terminals, respectively,
when ‘011’ data are received by the voltage distributor,
the switch connects the first voltage in response to the most significant bit 0 of the received ‘011’ data to output it to output the first voltage to the output buffer via the first output terminal, and
the multiplexing part multiplexes the first voltage and the second voltage in response to lower 2 bits ‘11’ of the received ‘011’ data to output three the second voltage to the output buffer via each of the second to fourth output terminals,
when ‘100’ data are received by the voltage distributor,
the switch connects the second voltage in response to the most significant bit 1 of the received ‘100’ data to output the second voltage to the output buffer via the first output terminal, and
the multiplexing part multiplexes the first voltage and the second voltage in response to lower 2 bits ‘00’ of the received ‘100’ data to output the first voltage to the output buffer via each of the second to fourth output terminals,
when ‘101’ data are received by the voltage distributor,
the switch connects the second voltage in response to the most significant bit 1 of the received ‘101’ data to output the second voltage to the output buffer via the first output terminal, and
the multiplexing part multiplexes the first voltage and the second voltage in response to lower 2 bits ‘01’ of the received ‘101’ data to output the second voltage level and the two first voltages to the output buffer via the second to fourth output terminals, respectively,
when ‘110’ data are received by the voltage distributor,
the switch connects the second voltage in response to the most significant bit 1 of the received ‘110’ data to output the second voltage to the output buffer via the first output terminal, and
the multiplexing part multiplexes the first voltage and the second voltage in response to lower 2 bits ‘10’ of the received ‘110’ data to output the two second voltages and the first voltage to the output buffer via respective ones of the second to fourth output terminals, respectively, and
when ‘111’ data are received by the voltage distributor,
the switch connects the second voltage in response to the most significant bit 1 of the received ‘111’ data to output the second voltage to the output buffer via the first output terminal, and
the multiplexing part multiplexes the second voltage of the first voltage and the second voltage in response to lower 2 bits ‘11’ of the received ‘111’ data to output three the second voltage to the output buffer via each of the second to fourth output terminals.
A typical liquid crystal display controls light transmittance of liquid crystal cells in accordance with video signals to thereby display a picture. An active matrix type of liquid crystal display that includes a switching device for each liquid crystal cell is particularly suited for displaying moving pictures through active control of the switching devices. A thin film transistor (hereinafter, referred to as “TFT”) is typically used as the switching device in active matrix liquid crystal displays as shown in FIG. 1.
Referring to FIG. 4, if ‘000’ data are received, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output eight first voltages V1, using the first to eighth output terminals Vo1 to Vo8, to the output buffer 124.
If ‘001’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output seven first voltages V1, via the first to seventh output terminals Vo1 to Vo7, to the output buffer 124, respectively and, at the same time output one second voltage V2, via the eighth output terminal Vo8, to the output buffer 124.
If ‘010’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output six first voltages V1, via the first to sixth output terminals Vo1 to Vo6, to the output buffer 124 respectively and, at the same time output two second voltage V2, via the seven and eighth output terminals Vo7 and Vo8, to the output buffer 124, respectively.
If ‘011’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output five first voltages V1, via the first to fifth output terminals Vo1 to Vo5, to the output buffer 124, respectively and, at the same time output three second voltages V2, via the sixth to eighth output terminals Vo6 to Vo8, to the output buffer 124, respectively.
If ‘100’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output four first voltages V1, via the first to fourth output terminals Vo1 to Vo4, to the output buffer 124, respectively and, at the same time output four second voltages V2, via the fifth to eighth output terminals Vo5 to Vo8, to the output buffer 124, respectively.
If ‘101’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output three first voltages V1, via the first to third output terminals Vo1 to Vo3, to the output buffer 124, respectively and, at the same time output five second voltages V2, via the fourth to eighth output terminals Vo4 to Vo8, to the output buffer 124.
If ‘110’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output two first voltages V1, via the first and second output terminals Vo1 and Vo2, to the output buffer 124, respectively and, at the same time output six second voltages V2, via the third to eighth output terminals Vo3 to Vo8, to the output buffer 124, respectively.
If ‘111’ data are input, the multiplexing part 123 multiplexes the first voltage V1 and the second voltage V2 from the switching part 122 to output one first voltage V1, via the first output terminal Vo1, to the output buffer 124 and, at the same time output seven second voltages V2, via the second to eighth output terminals Vo2 and Vo8, to the output buffer 124, respectively.
Accordingly, the present invention is directed to a data driving circuit of a liquid crystal display that substantially obviates one or more of the problems due to limitations and disadvantages of the related art
The inverter IV1 inverts a level of the input most significant bit to output the inverted bit to a gate of the NMOS transistor N_TR17. In other words, the inverter IV1 inverts a supplied most significant bit ‘0’ to output a ‘1’ and inverts a supplied most significant bit ‘1’ to output a ‘0’.
For example, if a data of the most significant bit ‘0’ is input to the inverter IV2, the most significant bit ‘0’ is inverted and output as a ‘1’ by inverter IV1. The ‘1’ is then applied to the NMOS transistor N_TR17 of the transmission gate 231-1. The NMOS transistor N_TR17 of the transmission gate 231-1 is turned on by the inverted most significant bit of ‘1’ and the first voltage V1 from the switching part 230 is conducted to the first output terminal Vo1. In addition, the input most significant bit ‘0’ is directly applied to the gate of the NMOS transistor N_TR18 of the transmission gate 231-1 to turn off the NMOS transistor N_TR18. Accordingly, the NMOS transistor N_TR18 of the transmission gate 231-1 isolates the second voltage V2 applied from the switching part 220 from the first output terminal Vo1.
If data having a most significant bit of ‘1’ is input, the NMOS transistor N_TR18 of the transmission gate 231-1 is turned on by the input most significant bit ‘1’ to output a second voltage V2 with which a drain of the switching part 220 is applied from the switching part 220 via the first output terminal Vo1. The input most significant bit ‘1’ is inverted to a ‘0’ by the inverter IV1 to be applied to the NMOS transistor N_TR17 of the transmission gate 231-1. Accordingly, the NMOS transistor N_TR17 of the transmission gate 231-1 is turned-off by the inverted most significant bit ‘0’ to isolate the first voltage V1 applied from the switching part 220 from the first output terminal Vo1.
Referring to FIG. 7, if ‘000’ data is input to the voltage distributor 230, the switch 231 switches a first voltage V1 from the switching part 220 in accordance with the most significant bit ‘0’ to output the switched voltage V1 to the output buffer 240 via the first output terminal Vo1. Furthermore, the multiplexing part 232 multiplexes only first voltage V1 of a first voltage V1 and a second voltage V2 from the switching part 220 in accordance with lower 2 bits ‘00’ to output the three first voltages V1 to the output buffer 240 via the second to fourth output terminals Vo2 to Vo4, respectively. In this case, the voltage distributor 230 outputs a first voltage V1 from the switching part 220 to the output buffer 240 via the fifth output terminal Vo5 irrespective of the input data bits.
If ‘001’ data is input to the voltage distributor 230, the switch 231 switches a first voltage V1 from the switching part 220 in accordance with the most significant bit ‘0’ to output the switched voltage V1 to the output buffer 240 via the first output terminal Vo1. Furthermore, the multiplexing part 232 multiplexes a first voltage V1 and a second voltage V2 from the switching part 220 in accordance with lower 2 bits ‘01’ to output two first voltages V1 and one second voltage V2 to the output buffer 240 via the second to fourth output terminals Vo2 to Vo4, respectively. In this case, the voltage distributor 230 outputs a first voltage V1 from the switching part 220 to the output buffer 240 via the fifth output terminal Vo5 irrespective of the input ‘001’ data.
If ‘010’ data is input to the voltage distributor 230, the switch 231 switches a first voltage V1 from the switching part 220 in accordance with the most significant bit ‘0’ to output the switched voltage V1 to the output buffer 240 via the first output terminal Vo1. Furthermore, the multiplexing part 232 multiplexes a first voltage V1 and a second voltage V2 from the switching part 220 in accordance with lower 2 bits ‘10’ to output two second voltages V2 and the one first voltage V1 to the output buffer 240 via the second to fourth output terminals Vo2 to Vo4, respectively. In this case, the voltage distributor 230 outputs a first voltage V1 from the switching part 220 to the output buffer 240 via the fifth output terminal Vo5 irrespective of the input ‘010’ data.
If ‘011’ data is input to the voltage distributor 230, the switch 231 switches a first voltage V1 from the switching part 220 in accordance with the most significant bit ‘0’ to output the switched voltage V1 to the output buffer 240 via the first output terminal Vo1. Furthermore, the multiplexing part 232 multiplexes only second voltage V2 of a first voltage V1 and a second voltage V2 from the switching part 220 in accordance with lower 2 bits ‘11’ to output three second voltages V2 to the output buffer 240 via the second to fourth output terminals Vo2 to Vo4, respectively. In this case, the voltage distributor 230 outputs a first voltage V1 from the switching part 220 to the output buffer 240 via the fifth output terminal Vo5 irrespective of the input ‘011’ data.
If ‘100’ data is input to the voltage distributor 230, the switch 231 switches a second voltage V2 from the switching part 220 in accordance with the most significant bit ‘1’ to output the switched voltage V2 to the output buffer 240 via the first output terminal Vo1. Furthermore, the multiplexing part 232 multiplexes only first voltage V1 of a first voltage V1 and a second voltage V2 from the switching part 220 in accordance with lower 2 bits ‘00’ to output the three first voltages V1 to the output buffer 240 via the second to fourth output terminals Vo2 to Vo4, respectively. In this case, the voltage distributor 230 outputs a first voltage V1 from the switching part 220 to the output buffer 240 via the fifth output terminal Vo5 irrespective of the input ‘100’ data.
If ‘101’ data is input to the voltage distributor 230, the switch 231 switches a second voltage V2 from the switching part 220 in accordance with the most significant bit ‘1’ to output the switched voltage V2 to the output buffer 240 via the first output terminal Vo1. Furthermore, the multiplexing part 232 multiplexes a first voltage V1 and a second voltage V2 from the switching part 220 in accordance with lower 2 bits ‘01’ to output the two first voltages V1 and the one second voltage V2 to the output buffer 240 via the second to fourth output terminals Vo2 to Vo4, respectively. In this case, the voltage distributor 230 outputs a first voltage V1 from the switching part 220 to the output buffer 240 via the fifth output terminal Vo5 irrespective of the input ‘101’ data.
If ‘110’ data is input to the voltage distributor 230, the switch 231 switches a second voltage V2 from the switching part 220 in accordance with the most significant bit ‘1’ to output the switched voltage V2 to the output buffer 240 via the first output terminal Vo1. Furthermore, the multiplexing part 232 multiplexes a first voltage V1 and a second voltage V2 from the switching part 220 in accordance with lower 2 bits ‘10’ to output the two second voltages V2 and the one first voltage V1 to the output buffer 240 via the second to fourth output terminals Vo2 to Vo4, respectively. In this case, the voltage distributor 230 outputs a first voltage V1 from the switching part 220 to the output buffer 240 via the fifth output terminal Vo5 irrespective of the input ‘110’ data.
If ‘111’ data is input to the voltage distributor 230, the switch 231 switches a second voltage V2 from the switching part 220 in accordance with the most significant bit ‘1’ to output the switched voltage V2 to the output buffer 240 via the first output terminal Vo1. Furthermore, the multiplexing part 232 multiplexes only second voltage V2 of a first voltage V1 and a second voltage V2 from the switching part 220 in accordance with lower 2 bits ‘11’ to output the three second voltages V2 to the output buffer 240 via the second to fourth output terminals Vo2 to Vo4, respectively. In this case, the voltage distributor 230 outputs a first voltage V1 from the switching part 220 to the output buffer 240 via the fifth output terminal Vo5 irrespective of the input ‘111’ data.
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