Source: https://patents.google.com/patent/US7424604?oq=645576
Timestamp: 2018-05-27 18:35:21
Document Index: 540367155

Matched Legal Cases: ['Application No. 03813629', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 031813629']

US7424604B2 - Weighted processor selection apparatus and method for use in multiprocessor systems - Google Patents
Weighted processor selection apparatus and method for use in multiprocessor systems Download PDF
US7424604B2
US7424604B2 US11402704 US40270406A US7424604B2 US 7424604 B2 US7424604 B2 US 7424604B2 US 11402704 US11402704 US 11402704 US 40270406 A US40270406 A US 40270406A US 7424604 B2 US7424604 B2 US 7424604B2
US11402704
US20060190713A1 (en )
Todd A. Schelling
A processor programmed to write to a memory location a first weighted value corresponding to the processor to overwrite a second weighted value stored in the memory location and associated with another processor. The processor is also programmed to compare the first weighted value of the processor with the second weighted value associated with the other processor and to select the processor if the first weighted value of the processor is better than the second weighted value.
FIG. 1 is a block diagram of an example of a multiprocessor system 10 that uses the example processor selection technique described herein. As shown in FIG. 1, the multiprocessor system 10 includes a plurality of processors 12, 14 and 16 that are coupled to each other via an interconnection bus or network 18. The processors 12-16 may be any suitable processor, processing unit or microprocessor such as, for example, Intel Itanium™ processors, Intel X-Scale™ processors, Intel Pentium™ processors, etc.
In the case where the processors 12-16 are Intel Itanium™ processors, an Intel 870 chipset may be used for the chipset 20. The Intel 870 chipset provides a plurality of scratchpad registers, any of which are capable of performing the functions of the shared resource 26 as described in greater detail herein. However, it should be recognized that while scratchpad registers, such as those provided by the 870 chipset, are well-suited for use as the shared resource 26, any other register with acceptable side-effects could be used instead. In other words, any register that could be used in conjunction with the technique described in connection with FIGS. 2 a-2 c below without adversely affecting the operation of the system 10 is a suitable alternative. Thus, any register could be used as the shared resource 26 if access to that register (i.e., reading from and/or writing to that register) by the processors 12-16 would not cause an undesirable consequence or side-effect. For example, the base address register associated with a fixed peripheral component interconnect (PCI) device that is not otherwise being used by the system 10 while carrying out the processor selection technique described herein could be used as the shared resource 26.
As is also depicted in FIG. 1, the processors 12-16 include respective interval timer/counter (ITC) registers 38-42 that count at a known frequency. For example, in the case where the processors 12-16 are Intel Itanium™ processors, the ITC registers 38-42 are sixty-four bit registers that can be reset and then continuously count up from zero at a rate of 1 billion counts per second. Due to the large size of the ITC registers (i.e., the number of counter bits) within Intel Itanium™ processors, these ITC registers can count continuously, without rollover, for more than 580 years.
In the case where the processors 12-16 are Intel Itanium™ processors, the processors 12-16 preferably establish their timers using the ITC registers provided therein. In particular, the processors 12-16 may establish their timers by reading a current value of the ITC register (block 56) and then determining, based on the known clocking rate of the ITC register, a future count value of the ITC register that corresponds to a future time that is a worst case time delay later. Of course, the specific manner in which the processors 12-16 establish their timers will vary to suit the particular hardware platform or processor type used by the system 10.
After establishing their timers, each of the processors 12-16 reads the shared resource 26 (block 58) and returns a value represented by a digital word having a number of bits equal to the maximum number of bits used to represent the weighted values associated with the processors 12-16. Each of the processors 12-16 then determines whether value returned by the shared resource 26 is equal to a default value (block 60). As noted above, the shared resource 26 is preferably a register or the like within the chipset 20 that has a known default value such as, for example, zero, following a reset of the system 10. Each of the processors 12-16 then determines whether its timer (set at block 56) has expired (block 62). In the case where the processors 12-16 are Intel Itanium™ processors, expiration of a timer occurs when a calculated future count value is reached. Of course, timer expiration may occur in different manners depending on the particular hardware platform (e.g., processor type) used within the multiprocessor system 10. In any case, if any one of the processors 12-16 determines that its timer has expired, then it writes a worst case weighted value (which is not equal to the default value) to the shared resource 26 (block 64) and then initializes its loop counter to zero (block 66) for use by the second phase or routine depicted in FIG. 2 b. Otherwise, processors having unexpired timers read the shared resource 26 again and determine whether the value returned by the shared resource 26 equals the default value (blocks 58 and 60). If the value stored in the shared resource 26 is not equal to the default value, then all processors having unexpired timers exit their wait loops and initialize their respective loop counters (block 66). While the example embodiment described herein writes a worst case weighted value to the shared resource (block 64), a processor at block 64 could instead write its own weighted value to the shared resource to carry out the system and method described herein with identical or similar results.
FIG. 2 b depicts an example of the second phase or routine that can be used by the processor selection technique of FIGS. 2 a-c to enable the processor having the best weighted value to store that weighted value in the shared resource 26. Following execution of the first phase or routine shown in FIG. 2 a, the processors 12-16 begin execution of the second phase or routine in a substantially synchronized manner (i.e., all of the processors 12-16 begin execution of the second phase or routine at approximately the same time). As shown in FIG. 2 b, each of the processors 12-16 establishes a timer to measure a predetermined period of time that is greater than or equal to the longest (i.e., worst case) time period required by any one of the processors 12-16 (i.e., the slowest processor) to execute the computer code or firmware associated with the second phase or routine shown in FIG. 2 b.
The processors 12-16 then read the shared resource 26 (block 70) and compare their weighted value to the value stored in the shared resource 26 (block 72). The weighted value used by each of the processors 12-16 in the example shown in FIG. 1 is a unique numerical identifier associated with the processor concatenated with a numerical value representative of the health or operating condition of the processor.
FIG. 3 depicts an example of one manner in which the processors 12-16 may be programmed to generate their respective weighted values. Using the example technique shown in FIG. 3, each of the processors 12-16 generates a unique numerical identifier (block 100). The unique identifier for each of the processors 12-16 is retrieved from a respective general purpose register or any other similar storage device or memory within the processors 12-16. For example, in the case where the processors 12-16 are Intel Itanium™ processors, the processor abstraction layer (PAL) within each of the processors 12-16 provides a unique identifier for its respective processor. For example, the processors 12-16 may have respective unique numerical identifiers 1, 2 and 3.
US11402704 2002-06-13 2006-04-12 Weighted processor selection apparatus and method for use in multiprocessor systems Active US7424604B2 (en)
US10171164 US7065641B2 (en) 2002-06-13 2002-06-13 Weighted processor selection apparatus and method for use in multiprocessor systems
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US7065641B2 (en) 2006-06-20 grant
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KR100844614B1 (en) 2008-07-07 grant
WO2003107134A3 (en) 2004-03-11 application
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