Source: http://www.google.com/patents/US7115521?dq=6,970,917
Timestamp: 2015-03-03 23:25:33
Document Index: 741666240

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'application No. 60']

Patent US7115521 - Epitaxial semiconductor deposition methods and structures - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsMethods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded...http://www.google.com/patents/US7115521?utm_source=gb-gplus-sharePatent US7115521 - Epitaxial semiconductor deposition methods and structuresAdvanced Patent SearchPublication numberUS7115521 B2Publication typeGrantApplication numberUS 10/993,024Publication dateOct 3, 2006Filing dateNov 18, 2004Priority dateMar 13, 2003Fee statusPaidAlso published asUS7238595, US7402504, US20040219735, US20050092235, US20060281322Publication number10993024, 993024, US 7115521 B2, US 7115521B2, US-B2-7115521, US7115521 B2, US7115521B2InventorsPaul D. Brabant, Joseph P. Italiano, Chantal J. Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias BauerOriginal AssigneeAsm America, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (31), Non-Patent Citations (40), Referenced by (7), Classifications (35), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetEpitaxial semiconductor deposition methods and structures
US 7115521 B2Abstract
1. A process for forming a strained semiconductor layer over a substrate, the process comprising:
forming an epitaxial Ge-containing layer on a substrate, wherein the epitaxial Ge-containing layer has a germanium content in the range of about 50 atomic percent to about 100 atomic percent; and
depositing a strained epitaxial semiconductor layer over the epitaxial Ge-containing layer by chemical vapor deposition using a deposition gas comprising trisilane.
2. The process of claim 1 in which depositing the strained epitaxial semiconductor layer comprises depositing a strained epitaxial Si layer.
3. The process of claim 2 in which depositing the strained epitaxial semiconductor layer comprises depositing the strained epitaxial Si layer onto a cure Ge layer.
4. The process of claim 1 in which depositing comprises maintaining the substrate at a temperature in the range of about 325� C. to about 475� C.
5. The process of claim 1 in which depositing comprises maintaining a deposition pressure in the range of about 1 Torr to about 100 Torr.
6. The process of claim 1 comprising depositing the strained epitaxial semiconductor layer at a deposition rate in the range of about 5 Å/minute to about 50 Å/minute.
7. The process of claim 1 in which depositing is conducted in a single-wafer, horizontal gas flow reactor.
8. The process of claim 1 in which the substrate comprises a single crystal Si layer.
9. A process for forming a strained semiconductor layer over a substrate, the process comprising:
providing a single crystal Si substrate in a single-wafer, horizontal gas flow reactor;
depositing an epitaxial Ge-containing layer on the single crystal Si substrate; and
depositing a strained epitaxial semiconductor layer onto the epitaxial Ge-containing layer by chemical vapor deposition using a deposition gas comprising trisilane, wherein the substrate is maintained at a temperature between about 325� C. and about 475� C. during deposition of the strained epitaxial semiconductor layer.
10. The process of claim 9, further comprising heating the substrate after depositing the strained epitaxial semiconductor layer, wherein heating the substrate comprises increasing the temperature of the substrate to a temperature in the range of about 400� C. to about 525� C.
11. The process of claim 9 in which depositing the strained epitaxial semiconductor layer comprises maintaining a deposition pressure in the range of about 1 Torr to about 100 Torr.
12. The process of claim 1, wherein the epitaxial Ge-containing layer has a germanium content of about 99 atomic percent or higher.
13. The process of claim 9, wherein the deposited epitaxial Ge-containing layer has a germanium content in the range of about 50 atomic percent to about 100 atomic percent.
14. The process of claim 9, wherein the deposited epitaxial Ge-containing layer has a germanium content of about 99 atomic percent or higher.
providing a substrate in a reaction chamber, wherein an epitaxial germanium-containing layer is provided on the substrate; and
depositing a strained epitaxial semiconductor layer over the germanium-containing layer by chemical vapor deposition using a deposition gas comprising trisilane, wherein the strained epitaxial semiconductor layer is deposited at a deposition rate between about 5 Å min−1 and about 50 Å min−1, and at a temperature between about 325� C. and about 475� C.
16. The method of claim 15, wherein the epitaxial germanium-containing layer has a germanium content in the range of about 50 atomic percent to about 100 atomic percent.
17. The method of claim 15, wherein the epitaxial germanium-containing layer has a germanium content greater than about 99 atomic percent.
18. The method of claim 15, wherein depositing the strained epitaxial semiconductor layer comprises delivering trisilane to the reaction chamber at a flow rate between about 5 mg min−1 and about 50 mg min−1.
This application is a continuation of U.S. application Ser. No. 10/800,390, filed Mar. 12, 2004, which claims priority under 35 U.S.C. �119(e) to U.S. Provisional Patent Application No. 60/455,226, filed Mar. 13, 2003, U.S. Provisional Patent Application No. 60/470,584, filed May 14, 2003, and to U.S. Provisional Application No. 60/545,442, filed Feb. 17, 2004, all of which are hereby incorporated by reference in their entireties.
This application is also related to U.S. Provisional Patent Application No. 60/548,269, filed Feb. 27, 2004, entitled GERMANIUM DEPOSITION, and to U.S. Provisional Application No. 60/556,752, filed Mar. 26, 2004.
SixGe1-x films are used in a wide variety of semiconductor applications. An issue that often arises during the production of these materials is the lattice strain that may result from heteroepitaxial deposition. A �heteroepitaxial� deposited layer is an epitaxial or single crystal film that has a different composition than the single crystal substrate onto which it is deposited. A deposited epitaxial layer is said to be �strained� when it is constrained to have a lattice structure in at least two dimensions that is the same as that of the underlying single crystal substrate, but different from its inherent lattice constant. Lattice strain occurs because the atoms in the deposited film depart from the positions that they would normally occupy in the lattice structure of the free-standing, bulk material when the film deposits in such a way that its lattice structure matches that of the underlying single crystal substrate. For example, heteroepitaxial deposition of a Ge-containing material such a SiGe or Ge itself onto a single crystal Si substrate generally produces compressive lattice strain because the lattice constant of the deposited Ge-containing material is larger than that of the Si substrate. The degree of strain is related to the thickness of the deposited layer and the degree of lattice mismatch between the deposited material and the underlying substrate.
Strain is in general a desirable attribute for active device layers, since it tends to increase the mobility of electrical carriers and thus increase device speed. In order to produce strained layers on conventional silicon structures, however, it is often helpful to create a strain relaxed, intermediate heteroepitaxial layer to serve as a template for a further strained layer that is to remain strained and serve as an active layer with increased carrier mobility. These intermediate films are often provided by a relaxed SixGe1-x �buffer� layer over single crystal unstrained silicon (e.g., wafer surface), which can be engineered to provide the desired strain of an overlying layer (e.g., strained silicon layer).
Many microelectronic devices incorporate Ge-containing layers such as SiGe. To provide increased device performance, it is usually advantageous to have a relatively high germanium content in the SiGe layer. When deposited onto a single crystal Si substrate or layer, greater amounts of germanium generally increase the amount of strain. Generally, the higher the Ge content, the greater the lattice mismatch with underlying Si, up to pure Ge, which has a 4% greater lattice constant compared to silicon. As the thickness of the SiGe layer increases above a certain thickness, called the critical thickness, the SiGe layer relaxes automatically to its inherent lattice constant, which requires the formation of misfit dislocations at the film/substrate interface. The critical thickness depends upon temperature (the higher the temperature, the lower the critical thickness) and mismatch due to germanium content (the higher [Ge], the lower the critical thickness). For example, SiGe containing about 10% germanium has a critical thickness of about 300 Å at about 700� C. for an equilibrium (stable) strained film and about 2,000 Å for a metastable, strained film on Si<100>. If it is desirable to maintain the strain, the thickness is kept below the critical thickness and a cap layer is often applied to the strained heteroepitaxial layer to maintain the (metastable) strain of the SiGe layer during subsequent processing steps, e.g., to facilitate the formation of an emitter-base junction at the desired depth within the structure.
The quality of a deposited epitaxial layer generally depends on the cleanliness and crystal quality of the substrate onto which it is deposited. Since the substrate surface acts as a template for the deposited layer, any substrate surface contamination tends to degrade the quality of the deposited layer. Many epitaxial deposition processes employ a so-called �bake� step in which the substrate is heated to drive off surface contaminants such as oxygen and carbon immediately prior to epitaxial deposition.
One aspect of the invention provides a process for forming a strained semiconductor layer over a substrate, comprising:
forming an epitaxial Ge-containing layer on a substrate; and depositing a strained epitaxial semiconductor layer over the epitaxial Ge-containing layer by chemical vapor deposition using a deposition gas comprising trisilane. Another aspect provides a method for depositing an epitaxial Ge-containing layer, comprising
heating a single crystal Si structure to a first temperature; cooling the single crystal Si structure to a second temperature during a cooling time period; contacting the single crystal Si structure with a surface active compound during at least a portion of the cooling time period; and depositing an epitaxial layer over the single crystal Si structure at the second temperature. Another aspect provides a process for forming a strained semiconductor layer over a substrate, comprising:
forming a relaxed epitaxial Ge layer over the substrate; depositing a relaxed epitaxial SiGe alloy layer onto the relaxed epitaxial Ge layer, the relaxed SiGe alloy layer having an increasing Si content with distance from an interface with the relaxed epitaxial Ge layer; and depositing a strained epitaxial semiconductor layer onto the relaxed epitaxial SiGe alloy layer. Another aspect provides a semiconductor structure, comprising
a single crystal Si structure; an epitaxial Ge layer deposited on the single crystal Si layer; and a SiGe alloy layer deposited on the epitaxial Ge layer. Another aspect provides an epitaxial semiconductor deposition system, comprising
a deposition chamber configured to support at least one workpiece; a surface active compound source vessel containing a surface active compound, the surface active compound source vessel being operatively connected to the chamber to allow the surface active compound to flow into chamber; a germanium source vessel containing a germanium precursor, the germanium source vessel being operatively connected to the chamber to allow the germanium precursor flow into the chamber; a heater configured to heat the at least one workpiece; and a computer operatively connected to and set to control flow of the surface active compound and the germanium precursor, and to control the temperature of the workpiece to conduct in sequence a high temperature process step, a cooling step and a low temperature Ge-containing epitaxial deposition step, wherein the controls provide the surface active compound to the at least one workpiece during at least a lower temperature portion of the cooling step. Another aspect provides a method for depositing an epitaxial Ge layer, comprising
providing substrate having a single crystal semiconductor surface disposed within a reactor; heating the substrate to a first temperature of about 450� C. or higher; cooling the substrate to a second temperature during a cooling time period, the reactor having a reactor pressure in the range of about 0.001 Torr to about 760 Torr during said cooling period; contacting the single crystal semiconductor surface with a surface active compound selected from the group consisting of Si precursors and Ge precursors during at least a portion of the cooling time period; and depositing an epitaxial Ge layer onto the single crystal semiconductor surface at the second temperature. Another aspect provides a method for depositing an epitaxial Ge layer. The method includes:
providing a single crystal Si substrate disposed within a single wafer reactor; heating the single crystal Si substrate to a first temperature of about 600� C. or higher; cooling the single crystal Si substrate to a second temperature of about 450� C. or less during a cooling time period, the reactor having a reactor pressure in the range of about 1 Torr to about 100 Torr during said cooling time period; and depositing an epitaxial Ge layer over the single crystal Si substrate at the second temperature. Another aspect provides a multi-layer semiconductor structure comprising:
an underlying single crystal silicon structure; and an overlying epitaxial germanium layer directly over the silicon structure having an as-deposited threading dislocation density of about 107 defects/cm2 or less, as measured by an etch pit decoration method, and an as-deposited surface roughness of about 20 Å rms or less, as measured by atomic force microscopy across at least a 10 micron�10 micron window. These and other aspects are described in greater detail below.
FIG. 1 is a partially schematic cross-sectional view of a single wafer chamber for processing wafers in accordance with one embodiment of the present invention.
FIG. 2 shows a schematic cross sectional view of a preferred multilayer film.
FIG. 3 shows a schematic cross sectional view of a batch deposition system in accordance with another embodiment of the present invention.
FIG. 4 shows a flowchart for a preferred deposition process.
FIG. 5 shows a flowchart for a more particular preferred epitaxial Ge deposition process.
FIG. 6 is a transmission electromicrograph (TEM) of a low temperature, smooth 50 nm germanium seed layer within an overlying high temperature 1 μm germanium bulk film formed by the methods described herein.
FIG. 7 is a TEM of a 75-nm germanium seed layer formed by the methods described herein.
FIG. 8 is a surface scan of an etch pit decorated (EPD) germanium film deposited in accordance with a preferred embodiment, illustrating about 107 defects/cm2. The film was etched by using 35 mL AcOH, 10 mL HNO3, 5 mL HF and 8 mg I2, and shown in 1000� magnification of a surface 108�82 μm2.
FIGS. 9�13 are surface scans of EPD germanium films deposited in accordance with the preferred embodiments having various levels and types of doping, illustrating less than 103 defects/cm2.
FIG. 14 is a surface roughness analysis of a germanium film deposited in accordance with the preferred embodiments, illustrating about 2.8 Å rms surface roughness.
This invention provides a number of embodiments involving methods for depositing Si1-xGex films and the Si1-xGex films deposited thereby, in which x is in the range from zero to one. Several embodiments provide a solution to the problem of single crystal Si surface contamination during deposition. For example, various semiconductor fabrication processes involve the deposition of a Ge-containing material onto a Si-containing substrate. �Substrate,� as used herein, can refer to a bare wafer or to such a workpiece with layers already formed on it. Frequently, the Si-containing substrate is heated during a preceding process step (e.g., to deposit or clean an epitaxial Si layer) to a much higher temperature than that used for the subsequent deposition of the Ge-containing material, so that there is a cooling period between the two steps. In many cases, the difference in temperature between the two steps results from the higher decomposition temperatures used for the silicon precursor (e.g., silane) used to deposit a prior layer of Si-containing material, or the higher temperatures used during an initial reducing or bake step, and the lower decomposition temperatures used for the germanium precursor (e.g., germane) used to deposit the Ge-containing material. During this cooling period, it is highly desirable for the surface of the Si-containing substrate to be kept free of contamination by e.g., oxygen or carbon. Thus, traditional low pressure chemical vapor deposition systems have not been widely used for this purpose because of the contamination potential. Ultra-high vacuum systems have been used to prevent contaminants from contacting the surface, but such systems are not always convenient and may represent additional costs.
To prepare a single crystal Si substrate for epitaxial Ge deposition, the Si substrate is typically cleaned by baking at about 450� C. or higher, often 900� C. or higher. Since Ge films deposited at high temperatures generally have a high degree of surface roughness, the single crystal Si substrate is desirably cooled to a temperature of less than 600� C., more preferably about 450� C. or less. To minimize surface contamination, the cleaned Si substrate is generally maintained under vacuum during cooling, and subsequent Ge deposition is typically conducted at very low pressures by Ultra High Vacuum Chemical Vapor Deposition (UHVCVD) or Molecular Beam Epitaxy (MBE).
In one embodiment of the instant invention, the high temperature Si-containing surface is protected from contamination during cooling by contacting the Si-containing surface (e.g., epitaxial Si substrate) with a surface active compound, preferably a Si or Ge source chemical, during a least part of the time that the surface is cooling. The term �surface active compound� refers to a chemical compound that protects a single crystal Si-containing surface from contamination without interfering with the epitaxial or heteroepitaxial deposition of the subsequent layer. The surface active compound is most preferably a Si compound.
As mentioned above, the high temperature Si-containing surface is preferably protected from contamination during cooling by contacting the Si-containing surface (e.g., epitaxial Si layer) with a surface active compound during at least part of the time that the surface is cooling. This embodiment is preferably conducted by first heating an epitaxial Si layer or bare wafer to a first preferred temperature of about 450� C. or higher, more preferably about 600� C. or higher, and in the illustrated embodiment is about 900� C. or higher. Such heating may take place during deposition of the epitaxial Si layer using a silicon precursor, e.g., silane, or during baking to sublime native oxides and/or drive off surface contaminants. In either case, a single crystal Si substrate is then cooled to a second temperature during a cooling period. The second temperature may be any temperature that is lower than the first temperature, and is preferably in a range that is appropriate for a subsequent heteroepitaxial deposition. In a preferred embodiment, the subsequent deposition forms a Ge-containing layer, e.g., an epitaxial Ge layer. For example, it has been found that the deposition of epitaxial Ge onto single crystal Si at temperatures higher than 450� C. using germane tends to result in incomplete surface coverage (for very thin films) and rough surfaces (for thicker films), possibly resulting from the formation of clusters or islands of deposited Ge atoms. Therefore, deposition using germane is preferably conducted at temperatures in the range of about 300� C. to about 450� C., more preferably in the range of about 300� C. to about 350� C. Temperature dependence of the islanding effect is illustrated, e.g., in Sch�llhorn et al., �Coalescence of germanium islands on silicon,� Thin Solid Films, Vol. 336 (1998), pp. 109�111.
To reduce or prevent contamination during the cooling period (e.g., between a bake step or the epitaxial Si deposition using silane and the later time that the epitaxial Ge or SiGe is deposited using germane), the epitaxial Si surface is preferably contacted with a surface active compound during at least part of the cooling period. Depending on the cooling conditions, preferred surface active compounds for this purpose include silanes (e.g., silane, disilane, and trisilane), halosilanes (e.g., chlorosilane, dichlorosilane, trichlorosilane, and tetrachlorosilane), alkylsilanes (e.g., methylsilane, dimethylsilane, trimethylsilane and tetramethylsilane), germanes (e.g., germane, digermane) and halogermanes (e.g., dichlorogermane, trichlorogermane, tetrachlorogermane). For example, in a preferred embodiment, an epitaxial silicon substrate is cooled to a temperature in the range of about 300� C. to about 450� C. During cooling, the single crystal silicon substrate is preferably contacted with a surface active compound that undergoes little or no thermal decomposition under the cooling conditions (e.g., temperature, pressure, cooling rate). Dichlorosilane and trichlorosilane are examples of particularly preferred surface active compounds suitable for use in this embodiment. The contacting of the surface active compound with the Si-containing substrate during the cooling period is preferably carried out by flowing or diffusing the surface active compound across the surface of the substrate. Routine experimentation may be used to select a flow rate that supplies an amount of surface active compound to the surface that is effective to reduce or avoid contamination during cooling.
After cooling to the second temperature, the deposition of the Ge-containing layer is preferably carried out by contacting the epitaxial Si surface with a germanium precursor. Preferred germanium precursors include germane, digermane and trigermane. Preferably, the second temperature is in the range of about 300� C. to about 450� C. The Ge-containing layer is preferably an epitaxial Ge-containing layer having a Ge content in the range of about 50 atomic % to about 100 atomic %, more preferably about 99 atomic % Ge or higher. In a preferred embodiment, the Ge-containing layer is epitaxial Ge (doped or undoped). The Ge-containing layer may be a SiGe layer, in which case the germanium precursor preferably further comprises a silicon precursor that can be different from the surface active compound, such as disilane or trisilane (which tend to have lower decomposition temperatures than silane). Typically, the silicon precursor decomposes or otherwise reacts during deposition, e.g., during epitaxial chemical vapor deposition (CVD). The relative amounts of germanium precursor and silicon precursor may be held relatively constant during the deposition, or varied to provide a graded SiGe layer.
Heating of the single crystal Si structure (including deposition, if desired), cooling, contacting with a surface active compound, contacting with a germanium precursor (and silicon precursor, if any) and subsequent deposition of the Ge-containing layer are all preferably conducted in a suitable chamber. Examples of suitable chambers include batch furnaces and single wafer reactors. An example of a preferred chamber is a single-wafer, horizontal gas flow reactor, preferably radiatively heated. Suitable reactors of this type are commercially available, and preferred models include the Epsilon� series of single wafer epitaxial reactors commercially available from ASM America, Inc. of Phoenix, Ariz. FIG. 1 illustrates such a reactor. While the processes described herein can also be employed in alternative reactors, such as a showerhead arrangement, benefits in increased uniformity and deposition rates have been found particularly effective in the horizontal, single-pass, laminar gas flow arrangement of the Epsilon� chambers. A suitable manifold may be used to supply the silicon precursor, surface active compound, and germanium precursor to the thermal chemical vapor deposition chamber in which the deposition is preferably conducted. Preferred gas flow rates can be determined by routine experimentation, depending on the size of the deposition chamber.
FIG. 1 illustrates a preferred single wafer chemical vapor deposition (CVD) reactor 10, including a quartz process or reaction chamber 12, constructed in accordance with a preferred embodiment, and for which the methods disclosed herein have particular utility. While originally designed to optimize epitaxial deposition of silicon on a single substrate at a time, the inventors have found the superior processing control to have utility in CVD of a number of different materials, including SiGe and Ge films. Moreover, the illustrated reactor 10 can safely and cleanly accomplish multiple deposition steps in the same chamber 12, as will be apparent from the discussion of the preferred processes, discussed below. As noted below, the basic configuration of the reactor 10 is available commercially under the trade name Epsilon� from ASM America, Inc. of Phoenix, Ariz.
A plurality of radiant heat sources is supported outside the chamber 12 to provide heat energy in the chamber 12 without appreciable absorption by the quartz chamber 12 walls. While the preferred embodiments are described in the context of a �cold wall� CVD reactor for processing semiconductor wafers, it will be understood that the processing methods described herein will have utility in conjunction with other heating/cooling systems, such as those employing inductive or resistive heating.
An inlet component 50 is fitted to the reaction chamber 12, adapted to surround the inlet port 40, and includes a horizontally elongated slot 52 through which the wafer 16 can be inserted. A generally vertical inlet 54 receives gases from gas sources and communicates such gases with the slot 52 and the inlet port 40. While not separately illustrated in FIG. 1, the skilled artisan will readily appreciate in view of the disclosure herein that the gas sources preferably include hydrogen, silicon and germanium precursors, and that controls (e.g., preprogrammed computer) are provided and configured to conduct a sequence of steps as described herein, including bleeding the surface active compound into the chamber during a cool down step prior to Ge-containing deposition. The inlet 54 can include gas injectors as described in U.S. Pat. No. 5,221,556, issued Hawkins et al., or as described with respect to FIGS. 21�26 in U.S. Pat. No. 6,093,252, issued to Wengert et al., the disclosures of which are hereby incorporated by reference. Such injectors are designed to maximize uniformity of gas flow for the single-wafer reactor.
Routine experimentation can be used to determine the deposition conditions (e.g., deposition temperature and deposition pressure) for any particular Si1-xGex layer. As discussed above, deposition temperatures for the Ge-containing layer are typically in the range of about 250� C. to 600� C., more preferably about 300 to about 450� C., depending on the nature of the germanium precursor. For example, lower deposition temperatures tend to be more appropriate as the thermal stability of the precursor decreases. The total pressure in the CVD chamber is in the range of about 10−5 Torr to about 800 Torr. In the case of the single wafer chamber of FIG. 1, the pressure is preferably in the range of about 200 mTorr to about 760 Torr, even more preferably about 1 Torr to about 200 Torr, most preferably in the range of about 1 Torr to about 60 Torr.
FIG. 2 illustrates a semiconductor structure 100 that can be provided in accordance with one embodiment. The structure 100 comprises a single crystal Si structure 105 (e.g., epitaxial Si layer or single crystal Si wafer surface), a thin epitaxial Ge-containing layer 110 deposited on the single crystal Si structure 105, and a Si1-xGex layer 115 deposited on the epitaxial Ge-containing layer 110, where x is in the range from zero to one. As discussed below, the epitaxial Ge-containing layer 110 preferably has a high Ge content, more preferably 50 at. % to 100 at. % Ge, particularly pure Ge, and the Si1-xGex layer 115 preferably comprises a lower Ge content SiGe alloy that serves as a relaxed buffer. It has been found that such films allow the Si1-xGex layer to have a reduced defect density, both for a given thickness and absolutely. A preferred application for the combined thin epitaxial Ge layer and Si1-xGex layer is as a relaxed buffer layer between an underlying unstrained single crystal Si structure 105 and an overlying strained Si epitaxial layer 120. The combined thin epitaxial Ge-containing layer 110 and Si1-xGex layer 115 may also be used in other applications.
It has now been found that thinner Si1-xGex (preferably. SiGe) buffer layers may be used in such applications by placing a thin epitaxial Ge-containing layer with high Ge content (e.g., about 40 at. % or higher, more preferably 50 at. % or higher) between the underlying unstrained epitaxial Si layer and the Si1-xGex buffer layer. This invention is not bound by theory, but it is believed that the thin epitaxial high Ge content layer provides a medium in which the gliding propagation of dislocations in the Si1-xGex can proceed at a high velocity. �Horizontal� or gliding propagation velocity of the dislocations is higher when the Ge content is higher, so that the thin epitaxial Ge-containing layer (between the underlying unstrained single crystal Si structure and the Si1-xGex layer) preferably has a higher Ge content than the overlying Si1-xGex layer. See R. Hull, �Metastable strained layer configurations in the SiGe/Si system,� (1999) EMIS Datareviews. Series No. 24: Properties of SiGe and SiGe:C, edited by Erich Kasper et al., INSPEC (2000), London, UK. Preferably, the thin epitaxial Ge-containing layer is an epitaxial Ge layer. The thickness of the thin epitaxial Ge-containing layer may be varied, depending on the defect density and thickness that can be tolerated in the overlying Si1-xGex layer, but is preferably in the range of from about 10 Å to 1 μm, more preferably about 10 Å to about 500 Å, and most preferably about 15 Å to about 300 Å.
The multilayer structure 100 (including the thin epitaxial Ge-containing layer) is preferably deposited as described herein, e.g., by depositing a high [Ge] Ge-containing layer 110 (e.g., epitaxial Ge) onto a single crystal Si substrate 105 after cooling the Si substrate in contact with a surface active compound. It will be understood, however, that the benefits of the structures and sequences for forming buffers as described below can be obtained without the surface active compound during cooling. The Si1-xGex layer 115 deposited onto the thin epitaxial Ge-containing layer 110 preferably has a lower dislocation density than a comparable Si1-xGex layer deposited directly onto the single crystal Si structure 105. The Si1-xGex layer 115 is preferably an epitaxial SiGe layer having a Ge content in the range of about 1 atomic % to about 99 atomic %, more preferably about 40 atomic % to about 80 atomic %. The Si1-xGex layer 115 in accordance with this embodiment contains both Si and Ge (a SiGe alloy), such that the deposition is preferably conducted using a germanium precursor and a silicon precursor (e.g., silane, disilane, trisilane) as discussed above. The relative amounts of germanium precursor and silicon precursor may be held relatively constant during the deposition, or, preferably, varied to provide a graded SiGe layer.
As will be understood by the skilled artisan in view of the present disclosure, by starting with a high Ge content, dislocations generated by the lattice mismatch between the buffer structure and the underlying single crystal Si are largely taken up in the initial high Ge content (e.g., pure Ge) layer 110 and more readily glide out of the layer. This benefit is obtained even without a separate anneal step, though annealing can also be performed. The higher the initial Ge content, the greater the benefit, such that a �pure� Ge layer (with or without electrical doping) is most preferred. Such pure Ge has a very low critical thickness, which in combination with the ability to deposit thin, smooth continuous Ge films with minimal dislocation density, as described elsewhere herein, allows a very thin Ge film that relaxes naturally upon deposition. The overlying SiGe portion 115 of the buffer layer can then be graded to reduce Ge content until the desired proportion of Ge is left at the upper surface to set the crystal mismatch for an overlying strained layer. Grading can be accomplished by grading the deposition temperature, adjusting the deposition pressure, adjusting relative Ge- and Si-precursor flows, or by a combination of the three. For example, for a high Ge content, low temperatures are preferably used to avoid islanding, and high pressure (e.g., 100 Torr) initially employed to aid in maintaining both high deposition rates and high Ge content. As the deposition proceeds and lower Ge content is desired, for some reactant combinations (e.g., DCS and GeH4) temperature is preferably increased and pressure decreased (to, e.g., 20 Torr). The SiGe layer 115 can be made thinner for a given density of dislocations, compared to known buffer deposition techniques. The described buffer can be described as �retrograde,� since the Ge concentration is inverted relative to conventional graded SiGe buffers. Grading can be more abrupt than with a conventional SiGe buffer, since the high Ge content at the underlying Si/Ge interface allows dislocations to glide out more readily, such that the overall buffer thickness can be reduced without higher dislocation densities.
At 50% Ge concentration, the lattice constant of the relaxed buffer is symmetrically larger and smaller than the lattice constant of pure Si and pure Ge, respectively. Thus, the strained semiconductor layer 120 can comprise both a strained Si and a strained Ge layer over the buffer, in accordance with a dual channel CMOS design, described by Lee et al. of the Massachusetts Institute of Technology, for example in Lee et al. �Growth of strained Si and strained Ge heterostructures on relaxed Si1-xGex by ultrahigh vacuum chemical vapor deposition,� J. Vac. Sci. Technol. B 22(1) (January/February 2004), the disclosure of which is incorporated herein by reference. As described by Lee et al., the strained Ge lower channel provides highly enhanced hole or positive carrier mobility, while the strained Si upper channel provides highly enhanced electron or negative carrier mobility.
One of the problems described by Lee et al. is the ability to produce thin, smooth Ge films. Ge deposition techniques prior to the present disclosure have been found difficult, even with the UHVCVD techniques described by Lee et al. The Ge deposition techniques described hereinabove have been found to produce excellent film quality under commercially viable, including pressures above 200 mTorr. Thus, in a particularly preferred embodiment, after formation of the relaxed SiGe buffer layer 115, as described above, the substrate can again be cooled, surface active compound (preferably a Si or Ge precursor) is provided during at least part of the cool down (e.g., from 600�800� C. down to the Ge deposition temperature), and the strained Ge layer is deposited at the lower temperature.
Furthermore, Lee et al. found difficulties keeping their strained Ge films (which must be kept extremely thin to avoid relaxation) smooth during subsequent high temperature processing. Lee et al. accordingly deposited their strained Si layer over the Ge layer at very low temperatures, such that a 3 nm Si layer took 1.5 hours to deposit. As a solution to this issue, in accordance with a preferred embodiment, after deposition of a strained Ge layer and prior to further processing at temperature that would cause agglomeration of the Ge film, a Si cap layer is formed in situ over the Ge film at low temperatures. Preferably trisilane is employed as the Si precursor for this deposition, such that commercially reasonable deposition speeds can be obtained even at low temperatures. Preferably the substrate temperature is kept between about 325� C. and 475� C. during the Si deposition, more preferably between about 400� C. and 450� C. Despite the low temperatures, using trisilane at pressures in the preferred range of 1 Torr to 100 Torr with trisilane mass flow rates of about 5 mg/min to 50 mg/min can deposit Si at rates of 5 Å/min to 50 Å/min. Advantageously, if deposited with high quality crystallinity, the Si cap layer can be used as the strained epitaxial Si layer of a dual channel device, and will serve as protection against Ge agglomeration during subsequent processing at higher temperatures whether the Si is epitaxial, amorphous or polycrystalline. For example, after a sufficiently thick Si cap layer has been formed, temperatures can be increased to about 400� C. to 525� C. to increase deposition speed.
In summary, methods described herein can be employed to produce high quality epitaxial semiconductor films using the preferred process flow set forth in bullet point below. It will be understood that variations to or omissions from the list below can be made while still obtaining benefits of the process. It will be understood that the entire sequence can be conducted in situ within a single deposition chamber, such as an Epsilon� 3000 reactor from ASM America, Inc.
high temperature processing (e.g., hydrogen baking or Si/SiGe deposition) cooling while bleeding surface active compound to the substrate (e.g., DCS) epitaxially deposit relaxed Ge layer at lower temperatures epitaxially deposit relaxed SiGe, retrograded from Ge to SiGe with 50% Ge content optionally in situ anneal to drive out defects and smooth compositional grading cooling while bleeding surface active compound to the substrate (e.g., DCS) epitaxially deposit strained Ge layer at lower temperatures deposit Si cap layer using trisilane (could serve as strained epi-Si of dual channel device) The optional anneal can be a spike anneal. For example, in the Epsilon� reactors, temperature can be ramped as quickly as 200�/sec until a peak temperature of 950�1150� C. is reached. Even without any plateau annealing, such a spike anneal can be sufficient to drive out defects, particularly given the high Ge content at the lower interface. If the buffer layer is thin and sharply graded (e.g., 50 nm), even such a rapid anneal will diffuse Ge out of the lower seed layer into the overlying SiGe alloy and generally flatten the Ge profile. A thicker buffer layer (e.g., 500 nm) will maintain the Ge seed layer and distinctive retrograde profile after such rapid annealing.
The methods described herein also have particular benefit for depositing Si and Ge in a batch furnace. Batch furnaces typically have an elongated process chamber that is generally in the shape of a tube and is surrounded by heating elements. Typically, semiconductor wafers are loaded into the furnace with the wafer faces oriented perpendicular to the elongate axis of the tube. Inside the furnace, the wafers are spaced apart, with limited spacing between the wafers to allow for gas diffusion between and contact with the wafers. Typically, process gases are supplied to the interior of the furnace from one end of the furnace. In some arrangements, the gases flow in a direction parallel to the elongate axis and are exhausted from a furnace end opposite to the end from which they entered. Process gases enter the space between adjacent wafers by diffusion. In this way, a large number of wafers (typically 50�100 wafers) can be processed simultaneously, making processing using these batch furnaces an efficient and economical production method. Suitable batch furnaces are commercially available, and preferred models include the Advance� 400 and Advance� 412 Series batch furnaces commercially available from ASM International N.V. of Bilthoven, the Netherlands.
The batch furnace is preferably equipped with a localized gas injector configured to inject precursor gases into the batch furnace chamber at various locations where wafers are positioned. Batch furnaces equipped with localized gas injectors are commercially available, and preferred models include the Advance� 400 and Advance� 412 Series batch furnaces. A preferred batch furnace is equipped with vessels containing a silicon precursor, a surface active compound that can be different from the silicon precursor, and a germanium precursor. A preferred batch furnace further comprises at least one localized gas injector.
FIG. 3 schematically illustrates a preferred Si and Ge deposition system 200 comprising a batch furnace 201 having a chamber 205, a first reactant source or vessel 210 containing a silicon precursor 215, a second reactant source or vessel 220 containing a surface active compound 225, and a third reactant source or vessel 230 containing a germanium precursor 235. In the illustrated embodiment, the silicon precursor 215 is silane, the surface active compound 225 is trichlorosilane (TCS), and the germanium precursor 235 is germane, but those skilled in the art will understand that various silicon precursors, surface active compounds, and germanium precursors may be used as described elsewhere herein. The surface active compound can also double as the silicon precursor or germanium precursor in other arrangements.
In the illustrated embodiment, the batch furnace 201 is also equipped with an injector tube 240 operatively connected to the first, second and third vessels 210, 220, 230 to allow passage of the silicon precursor 215, the surface active compound 225, and the germanium precursor 235 to the interior of the chamber 205 via localized gas injectors 245, which are essentially small orifices in the injector tube 240. The density of injector orifices 245 per unit length can increase with distance from the feed end, as disclosed in U.S. patent Publication No. 2003/0111013 A1, published Jun. 19, 2003, the disclosure of which is incorporated herein by reference. In this embodiment, the single injector tube 240 is used to supply the silicon precursor 215, the surface active compound 225, and the germanium precursor 235 to the interior of the chamber 205. In alternative embodiments (not shown in FIG. 3), two or more injector tubes are used, e.g., separate injector tubes are operatively connected to each of the first, second and third vessels 210, 220, 230. Additional vessels (not shown) containing, e.g., carrier gases, dopant precursor gases, etc., may also be operatively connected to the injector tube(s) 240 in a similar fashion. The first, second and third vessels 210, 220, 230 may be tanks containing the respective pressurized or unpressurized sources, and may comprise a bubbler and/or heater to facilitate delivery of the sources that are liquid under standard conditions in a vapor or gaseous form.
For the embodiment illustrated in FIG. 3, first, second, and third valves 247, 250, 255 are used to control the passage of the silicon precursor 215, the surface active compound 225 and the germanium precursor 235, respectively, from the respective first, second and third vessels 210, 220, 230 into the injector tube(s) 240. The valves 247, 250, 255 may be controlled manually, but are preferably controlled by a computer 260. The batch furnace 201 is also equipped with a heater 265 configured to heat the interior of chamber 205. The heater 265 is shown schematically as structure surrounding the chamber 205 FIG. 3, but it will be understood that various types of heaters known to those skilled in the art may be used, and may be located inside or outside the chamber 205. The heater is also preferably controlled by the computer 260 as illustrated in FIG. 3. The computer 260 is preferably preprogrammed to conduct a sequence of steps as described herein, including bleeding the surface active compound 225 into the chamber during a cool down step prior to Ge-containing deposition. For purposes of illustration, three wafers 270 are shown in the interior of the batch furnace 201, but it is understood that the batch furnace 201 may contain larger or smaller numbers of wafers (typically 50�100 wafers). Excess gases and byproduct are removed via vacuum pump (not shown) through an exhaust 275.
In the first step 305, after a hydrogen bake step to clean the silicon surface, the silicon precursor is used to deposit the Si-containing layer. In the illustrated embodiment, employing the system 200, the Si-containing layer is epitaxial silicon and is deposited onto the wafers 270 by first heating the substrates 270 to a first deposition temperature of about 600� C., then opening the first valve 247 and allowing the silicon precursor 215 (in this example silane) to flow from the first vessel 210 into the interior of the chamber 205 via the injector tube 240 and the localized gas injectors 245. After the desired thickness of epitaxial silicon has been deposited, the first valve 247 is closed and the first stage of the deposition is terminated. In an alternative embodiment (not illustrated), the Si-containing layer is formed outside the deposition system 200, e.g., the wafers 270 already comprise a single crystal Si surface layer when they are placed into the chamber 205. In this alternative embodiment, the first high temperature step 305 comprises only the bake step that is used to clean the single crystal Si surface.
In the second step 310, the single crystal Si left by the first step (e.g., deposited epitaxial Si layer or the single crystal substrate cleaned by baking) is cooled to a second temperature of about 400� C., while concurrently contacting the single crystal Si structure with the surface active compound 225 (in this case trichlorosilane). Cooling is accomplished by controlling the output of the heater 265. The contacting of the epitaxial Si substrate with the trichlorosilane is accomplished by opening the second valve 250 and allowing the trichlorosilane to flow from the second vessel 220 into the interior of the chamber 205 via the injector tube 240 and the localized gas injectors 245. In an alternative embodiment, the flow of the trichlorosilane is initiated before cooling begins, e.g., near the end of the first step 305.
FIG. 5 illustrates an embodiment for depositing an epitaxial Ge film (doped or undoped) onto a single crystal silicon structure (doped or undoped) in accordance with the methods described herein. Deposition may be carried out in a batch furnace by the process described above. The embodiment of FIG. 5, however, is described and has been demonstrated by the inventors for germanium deposition in a single wafer processing tool. In the past, germanium films deposited onto single crystal silicon substrates at higher pressures typical of single wafer tools, in the range of about 200 mTorr to about 760 Torr, had a relatively high level of defects, e.g., high threading dislocation density. The defects were believed to result from contamination of the single crystal silicon surface during cool down after high temperature deposition or cleaning, possibly due to imperfect sealing of the chamber. It was found that the contamination could be mitigated somewhat by shortening the cool down and depositing the germanium at a higher temperature, but germanium deposition at such higher temperatures typically produced rougher surfaces. Contamination could also be mitigated by conducting the cool down and subsequent germanium deposition at extremely low pressures, but deposition rates at such low pressures were slower than desired and often impractical for most single wafer tool designs.
It has now been discovered that high quality epitaxial germanium films may be deposited onto single crystal silicon substrates at pressures in the range of about 200 mTorr to about 760 Torr by contacting the single crystal Si substrate with a surface active compound during at least a portion of the cooling time period. Germanium films deposited in accordance with this embodiment preferably have a threading dislocation density of about 107 defects/cm2 or less, more preferably about 105 defects/cm2 or less, and/or a preferred surface roughness of about 25 Å or less, more preferably about 20 Å or less, as measured by atomic force microscopy. The defect densities and roughness measurements described herein obtain across at least a 10 micron�10 micron window. Germanium deposition at pressures in the range of about 1 Torr to about 760 Torr preferably permits deposition rates of about 250 Å per minute or higher, more preferably about 400 Å per minute or higher. In contrast, germanium deposition rates at very low pressures are typically about 100 Å per minute or less.
Epitaxial germanium deposition at pressures in the range of about 0.001 Torr to about 760 Torr is preferably conducted in a single-wafer, horizontal gas flow reactor, preferably radiatively heated. Suitable reactors of this type are commercially available, and preferred models include the Epsilon� series of single wafer epitaxial reactors commercially available from ASM America, Inc. of Phoenix, Ariz., as described above with respect to FIG. 1.
FIG. 5 illustrates a more particular embodiment, relative to the general sequence of FIG. 4, in which the sequence 400 includes a H2 bake 410, cool down with surface active compound 420, �pure� Ge deposition 430 and optional further SiGe alloy deposition 440 thereover. In the first step 410 of the illustrated embodiment, a single crystal silicon substrate is heated in a single wafer reactor to a first temperature effective for desorption of any hydrogen termination of the silicon and removal of contaminants, e.g., about 900� C. As discussed above, in other arrangements, the single crystal Si surface provided at the first temperature may result from deposition conducted at or near the first temperature. The first temperature may be 450� C. or greater, or 650� C. or greater, as desired, in order to accomplish the desired deposition or cleaning. In the illustrated embodiment, during step 410 a single crystal Si substrate is placed into the single wafer reactor and heated to about 900� C. for two minutes under flowing ultrapure hydrogen at a pressure of 10 Torr to remove surface contaminants, such as carbon and native oxide.
In the next step 420, the single crystal Si substrate is cooled to a second temperature during a cooling time period. In the illustrated embodiment, the single crystal Si substrate is cooled from the bake temperature to the germanium deposition temperature, which tends to be lower due to the tendency of the most common precursor, germane, to decompose at higher temperatures prior to reaching the substrate, and due to the tendency of germanium to migrate and agglomerate on oxide, leading to a high degree of surface roughness. In experiments, the substrate was cooled from a bake temperature of about 900� C. to about 350� C. at a cooling rate of about 4� C. per second, while maintaining the reactor pressure at about 10 Torr. Those skilled in the art will understand from the disclosure herein that the pressure within the reactor during the cooling time period can generally be in the range of about 0.001 Torr to about 760 Torr, but is more preferably about 1 Torr to about 100 Torr, and that the cooling rate is preferably in the range of about 1� C. per second to about 10� C. per second.
Thus, in the illustrated embodiment, the dichlorosilane is contacted with the single crystal surface during the entire cooling period, resulting in the deposition of about 500 Å of epitaxial silicon on the single crystal silicon surface during the cooling period. Preferably, such deposition is minimized so that the thickness of the material deposited during cooling is about 500 Å or less, more preferably about 200 Å or less. It has been found that smaller amounts of silicon are deposited during an exemplary cooling step 420 from 900� C. to 350� C. when the dichlorosilane is contacted with the single crystal silicon during only a portion of the cooling period, e.g., from about an intermediate temperature of 700� C. to about 350� C. Preferably, contact between the single crystal silicon and the dichlorosilane begins during cooling at an intermediate temperature of about 600� C.�800� C., more preferably 650� C. or higher, to avoid contamination during the lower temperature period from the intermediate temperature down to the Ge deposition temperature, in which cooling tends to be slower and desorption/reduction of contaminants tends to be less effective.
In the next step 430, an epitaxial Ge layer is deposited over the single crystal silicon substrate at a second temperature by introducing a germanium source to the single wafer reactor. In the illustrated embodiment, the epitaxial germanium layer is deposited at a second temperature of about 350� C., a deposition rate of about 20�100 Å per minute, and a pressure of about 10 Torr, by introducing germane to the single wafer reactor at a flow rate of about 20 sccm. Those skilled in the art will understand that other germanium sources (e.g., digermane, trigermane, chlorinated germanium sources) may be used in place of germane, with appropriate adjustment of flow rate, deposition temperature and pressure as discussed above.
Deposition may be continued at this temperature, or, preferably, the deposition temperature may then be increased in order to increase the deposition rate and decrease defect density as-deposited. For example, during a first stage of step 430, germane may be introduced to the chamber at 350� C. for about 2 minutes to produce an initial smooth continuous layer of epitaxial germanium having a thickness of about 600 Å. The initial epitaxial germanium layer is then preferably heated to about 650� C. during a second stage of step 430 and the germane flow continued to deposit an additional 9,400 Å of epitaxial germanium at a deposition rate of about 500�700 Å per minute, onto the initial germanium layer. The resulting epitaxial germanium film forms in this two-stage process in about 21 minutes. Overall, the epitaxial Ge layer is preferably deposited at a rate of at least about 300 Å per minute, more preferably at least about 500 Å per minute. Layers deposited by the method described above exhibited a threading dislocation density of about 107 defects/cm2, and a surface roughness of about 13 Å rms, as measured by atomic force microscopy on a 10 micron by 10 micron window. To obtain desirable smoothness, e.g., about 25 Å rms or less, more preferably about 20 Å rms or less, it is preferred that deposition of the germanium begin at a temperature in the range of about 300� C. to about 400� C. and continue until a smooth continuous layer of germanium has been deposited.
FIGS. 6�8 illustrate actual films deposited by the methods described above, where FIG. 6 shows the Ge seed and bulk layers of the above-described two-stage deposition, FIG. 7 shows another Ge seed layer deposited with excellent uniformity at low temperature, and FIG. 8 illustrates the low defect densities produced by Ge deposition in accordance with the preferred embodiments.
Pure germanium deposition has been demonstrated in the Epsilon� reactor with even better results than those noted above. With deposition rates in the range of 700�900 Å/min, resultant Ge films exhibited surface roughness of 2.8 Å rms and defect densities, as measured by etch pit decoration (EPD) of 103 defects/cm2. Particular process conditions used to obtain these results include the general process sequences taught herein, including provision of a surface active compound during cool down. In addition, the process conditions included use of a three-step germanium deposition, in which a Ge seed layer was deposited at low temperature (e.g., 350� C. for germane), followed by temperature ramping to a higher temperature (e.g., approximately 600�800� C.) while continuing to flow germane, and continued deposition at the higher temperature. Additionally, hydrogen gas was supplied to the reactor at high flow rates (e.g., about 5 slm or greater) with pressures in the range of 10�100 Torr. Further details on the actual process conditions are disclosed in U.S. provisional patent application No. 60/548,269, filed Feb. 27, 2004, entitled GERMANIUM DEPOSITION, the disclosure of which is incorporated herein by reference.
FIGS. 9�14 illustrate results from the above-described process. In each deposition, process conditions in an Epsilon� chamber included provision of 17 sccm DCS bled into the chamber during a prior cool down; low temperature Ge seed deposition, temperature ramping with continued deposition, and higher temperature bulk Ge deposition; 30 slm H2; 200 sccm of GeH4 (10% in H2); and a chamber pressure of 20 Torr. Using these conditions, As, P, and intrinsic films were developed. The scans with �100ה magnification represent a wafer surface 0.93�1.23 mm; scans with �200ה magnification represent 0.46�0.63 mm; and FIG. 8 (�1000ה) represents 0.093�0.123 mm. By counting the black spots on the surfaces, representing defects that are �decorated� or stand out due to the etch process (conditions noted on FIG. 8), a defect density in EPD/cm2, can be calculated. All of FIGS. 9�13 show densities on the order of 103 EPD/cm2 or lower, and many trials showed less than 102 EPD/cm2. FIG. 14 also illustrates a surface roughness measured at 2.8 Å rms. Several wafers deposited in accordance with the methods described herein, at various in situ doping levels, demonstrated better than 3 Å rms surface roughness.
Thus the methods provide a multilayer structure comprising an underlying single crystal silicon layer and an overlying epitaxial germanium layer having a threading dislocation density of about 107 defects/cm2 or less, more preferably about 105 defects/cm2 or less, and most preferably about 103 defects/cm2 or less; and a surface roughness of about 20 Å rms or less, more preferably about 10 Å rms or less, and most preferably about 3 Å rms or less, as measured by atomic force microscopy; these values preferably hold true across at least a 10 micron�10 micron window. Such multilayer structures are preferably made by the processes described herein. Preferably, the overlying epitaxial germanium layer has a thickness in the range of about 500 Å to about 2 microns. Preferably, the underlying single crystal silicon structure is a wafer.
Following epitaxial Ge deposition, an epitaxial SiGe alloy can optionally be deposited 440 thereover, as described above with respect to FIG. 2. As noted above, the SiGe alloy, together with the deposited epitaxial Ge layer, preferably provides a relaxed buffer for subsequent strained Si deposition. Moreover, the SiGe alloy can be �retrograded� from the pure Ge layer with increasing Si concentration as deposition proceeds until a suitable SiGe composition is reached for the desired strain in the layer to be deposited.
For example, in a preferred embodiment, a commercially available single crystal silicon wafer substrate may be heated to a first temperature in a reactor to drive off contaminants, cooled to a second temperature during a cooling time period during at least part of which the cleaned silicon surface is contacted with a surface active agent, then an epitaxial germanium layer may be deposited on the single crystal surface at the second temperature. The resulting Ge/Si wafers, comprising an epitaxial Ge layer on an underlying Si wafer, have substantial utility as substrates for the manufacture of optoelectronic and microelectronic devices. Pure germanium wafers would be desirable substrates, but their manufacture thus far has been cost-prohibitive due to the relative scarcity of germanium as compared to silicon. However, a Ge/Si wafer having a high quality epitaxial germanium overlayer as described herein provides substantially the same utility as a germanium wafer at a significantly reduced cost. The thickness of the epitaxial germanium overlayer depends on the ultimate application, but is preferably in the range of about 500 Å to about 2 microns, more preferably, about 1,000 Å to about 1 micron. As noted, the overlying epitaxial germanium layer preferably has a threading dislocation density of about 107 defects/cm2 or less, more preferably about 105 defects/cm2 or less, as measured by the etch pit decoration (EPD) method, and thus is suitable as a substrate for the manufacture of a wide variety of optoelectronic devices.
Those skilled in the art will understand that terms such as �silicon,� �silicon-germanium,� �Si,� and �SiGe,� are terms of art used to show that the material comprises the indicated elements, and are not to be construed as limiting the relative proportions of those elements nor as excluding the presence of other elements. Thus, for example, a �SiGe� film may contain Si and Ge in various proportions and may contain other elements as well, e.g., electrically active dopants such as antimony, boron, arsenic and phosphorous. Those skilled in the art will understand that single crystal Ge (e.g., epitaxial Ge) is highly pure (>99.9% Ge) and that single crystal Si (e.g., epitaxial Si) is also highly pure (>99.9% Si), and that both may be undoped or doped with electrically active dopants.
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