Source: http://www.google.de/patents/US8825924
Timestamp: 2017-11-22 03:50:57
Document Index: 535030403

Matched Legal Cases: ['Application No. 200580008575', 'Application No. 200780000013', 'Application No. 200780000014', 'Application No. 200780000015', 'Application No. 05723250', 'Application No. 05723250', 'Application No. 07250614', 'Application No. 07250614', 'Application No. 07250614', 'Application No. 07250645', 'Application No. 07250645', 'Application No. 07250646', 'Application No. 07250646', 'Application No. 07250646', 'Application No. 07250647', 'Application No. 07250647', 'Application No. 07250647', 'Application No. 07250648', 'Application No. 07250648', 'Application No. 07250648', 'Application No. 07250649', 'Application No. 07250649', 'Application No. 07250649', 'Application No. 07250649', 'Application No. 08251499', 'Application No. 08251499', 'Application No. 08251505', 'Application No. 08251505', 'Application No. 2007', 'Application No. 07250645']

Patent US8825924 - Asynchronous computer communication - Google Patentsuche
A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other...http://www.google.de/patents/US8825924?utm_source=gb-gplus-sharePatent US8825924 - Asynchronous computer communication
Veröffentlichungsnummer US8825924 B2
Anmeldenummer US 12/932,713
Auch veröffentlicht unter CN101341454A, CN101410823A, CN101438260A, US7904615, US20070192504, US20110185088
Veröffentlichungsnummer 12932713, 932713, US 8825924 B2, US 8825924B2, US-B2-8825924, US8825924 B2, US8825924B2
Erfinder Charles H. Moore
Ursprünglich Bevollmächtigter Array Portfolio Llc
Patentzitate (202), Nichtpatentzitate (133), Klassifizierungen (8), Juristische Ereignisse (2)
Asynchronous computer communication
US 8825924 B2
a plurality of computers, each of said computers including a processor for executing instructions and a memory; and
a plurality of bidirectional data paths connecting said computers, each of said data paths dedicated between a pair of said computers and including a read line, a write line, and a plurality of data lines; and wherein
one of said data paths connects a first computer and a second computer; said first computer is configured to indicate its readiness to communicate with said second computer by asserting a first signal on one of said read line and said write line of said data path connecting said first computer and said second computer;
said second computer is configured to indicate its readiness to communicate with said first computer by asserting a second signal on the other of said read line and said write line;
said first computer and said second computer being configured such that when both said read line and said write line have signals asserted thereon, then data is transferred between said first computer and said second computer via said data lines of said data path connecting said first computer and said second computer;
and further such that when said data is transferred between said first computer and said second computer, then said first signal and said second signal change; and
the changing of said first signal and said second signal is an acknowledgement to at least one of said first computer and said second computer that said data has been successfully transferred between said first computer and said second computer.
2. A computer array according to claim 1, wherein:
said first computer is configured to indicate its readiness to communicate by asserting a logical high signal on one of said write line and said read line; and
said second computer indicates its readiness to communicate by asserting a logical high signal on the other of said write line and said read line.
3. A computer array according to claim 2, wherein said first computer and said second computer are configured such that when said data is transferred between said first computer and said second computer, then said read line and said write line are pulled low.
4. A computer array according to claim 1, wherein said first computer is configured to indicate a readiness to write said data to said second computer by asserting said first signal on said write line.
5. A computer array according to claim 4, wherein said second computer is configured to indicate a readiness to read said data from said first computer by asserting said second signal on said read line.
6. A computer array according to claim 5, wherein:
said first computer and said second computer are configured such that after said first signal and said second signal are asserted, said first computer releases said write line; and said second computer causes said first signal and said second signal to change.
7. A computer array according to claim 1, wherein:
said first computer and said second computer are configured such that after said first signal and said second signal are asserted, said first computer and said second computer release said read line and said write line; and further such that whichever of said first computer and said second computer had asserted a signal on the read line causes said first signal and said second signal to change.
8. A computer array according to claim 1, wherein said first computer and said second computer are each configured such that the direction of data transfer between said first computer and said second computer is determined by programs executed by said first computer and said second computer.
9. A computer array according to claim 1, wherein:
each of said computers includes its own sequencer, said sequencer being responsive to input from at least one of an instruction word and said acknowledgement and operative to selectively produce a timing pulse for causing the execution of a subsequent instruction by the computer associated with said sequencer; and
further such that said first computer is configured such that when said first computer indicates its readiness to communicate with said second computer, then said first computer stops operation by suspending production of said timing pulse from said sequencer of said first computer.
10. A computer array according to claim 9, wherein said second computer is configured such that when said second computer indicates its readiness to communicate with said first computer, then said second computer stops operation by suspending the triggering of said timing pulse from said sequencer of said second computer.
11. A computer array according to claim 10, wherein said first computer and said second computer are configured such that when said first signal and said second signal change, then said sequencer of said first computer produces another said timing pulse such that said first computer resumes operation and further such that said sequencer of said second computer produces another said timing pulse such that said second computer resumes operation.
12. A computer array according to claim 9, wherein:
said sequencer is configured to automatically suspended producing another said timing pulse when said computer executes one of a read instruction and a write instruction.
13. A computer array according to claim 1, wherein said plurality of computers is integrated on a single die.
14. A computer array according to claim 1, wherein said first computer is configured to simultaneously indicate its readiness to communicate with said second computer and at least one other computer.
15. A method for communicating between a first computer and a second computer connected via a dedicated data path therebetween, said data path including a read line, a write line, and a plurality of data lines, said method comprising:
causing said first computer to indicate its readiness to communicate with said second computer by asserting a first signal on one of said read line and said write line;
causing said second computer to indicate its readiness to complete a communication with said first computer by asserting a second signal on the other of said read line and said write line;
transferring data between said first computer and said second computer via said plurality of data lines when said first computer and said second computer have indicated their readiness to communicate; and
causing one of said first computer and said second computer to generate an acknowledgement to the other of said first computer and said second computer that said data has been transferred by changing the values of said first signal and said second signal.
said step of causing said first computer to indicate its readiness to communicate includes causing said first computer to assert a logical high signal on one of said write line and said read line; and
said step of causing said second computer to indicate its readiness to complete said communication includes causing said second computer to assert a logical high signal on the other of said write line and said read line.
17. A method according to claim 16, wherein said step of causing one of said first computer and said second computer to generate said acknowledgement includes causing said one of said first computer and said second computer to cause a logical low signal to be asserted on said read line and said write line.
18. A method according to claim 15, wherein said step of causing said first computer to indicate its readiness to communicate includes causing said first computer to indicate its readiness to write said data to said second computer by asserting said first signal on said write line.
19. A method according to claim 18, wherein said step of causing said second computer to indicate its readiness to complete said communication includes causing said second computer to indicate its readiness to read said data from said first computer by asserting said second signal on said read line.
causing said first computer to release said write line after said first signal and said second signal are asserted; and wherein
said second computer causes said first signal and said second signal to change.
causing said first computer and said second computer to release said read line and said write line after said first signal and said second signal have been asserted; and wherein said step of causing one of said first computer and said second computer to generate an acknowledgement includes causing the reading one of said first computer and said second computer to cause said first signal and said second signal to change.
22. A method according to claim 15, wherein the direction of data transfer between said first computer and said second computer is determined by programs executed by said first computer and said second computer.
causing said first computer to simultaneously indicate its readiness to communicate with said second computer and at least one other computer.
24. A computer array, comprising:
a plurality of computers, each of said computers including a processor for executing instructions and a memory;
a plurality of bidirectional data paths connecting said computers, each of said data paths dedicated between a pair of said computers and including a read line, a write line, and a plurality of data lines;
means for causing said first computer to indicate its readiness to communicate with said second computer via one of said read line and said write line;
means for causing said second computer to indicate its readiness to complete a communication with said first computer by via the other of said read line and said write line;
means for transferring data between said first computer and said second computer when said first computer and said second computer have indicated their readiness to communicate; and
means for acknowledging to at least one of said first computer and said second computer that said communication has been completed, said acknowledgment occurring via at least one of said read line and said write line.
25. A computer array, comprising:
a plurality of computers, each of said computers including a processor for executing instructions; and
a bidirectional data path connecting a first computer and a second computer in the computer array, said data path including a read line, a write line, and a plurality of data lines; wherein
said first computer is configured to set the write line when it is ready to write to the second computer and further to set the read line high when it is ready to read from the second computer;
said second computer is configured to set the write line high when it is ready to write to the first computer and further to set the read line high when it is ready to read from the second computer; and
said first computer and said second computer are configured such that when both the read line and the write line are simultaneously high then data is transferred via the data lines from whichever of the first computer or the second computer had set the write line high to whichever of the first computer or the second computer had set the read line high.
26. The computer array of claim 25, wherein:
both the first computer and the second computer are configured to release both the read line and the write line when data is transferred.
27. The computer array of claim 26, wherein:
both the first computer and the second computer are configured such that whichever of the first computer or the second computer had set the read line high pulls both the read line and the write line low when the data has been transferred.
28. The computer array of claim 25, wherein:
the first computer is configured to set either the read line or the write line high by asserting a predetermined voltage on either the read line or the write line; and
the second computer is configured to set either the read line or the write line high by asserting a predetermined voltage on either the read line or the write line.
29. The computer array of claim 27, wherein:
both the first computer and the second computer are configured to set the read line and the write linen low by asserting a predetermined voltage on both the read line and the write line, said predetermined voltage being different from the voltage thereon when the read line and the right line are pulled high.
30. The computer array of claim 29, wherein:
the predetermined voltage is zero volts.
This application is a continuation of U.S. patent application Ser. No. 11/355,495 (now U.S. Pat. No. 7,904,615) filed Feb. 16, 2006 by the same inventor, which is incorporated herein by reference in its entirety.
In the present example, only a programming error would cause both computers 12 on the opposite ends of one of the buses 16 to try to set high the read line 18 therebetween. Also, it would be error for both computers 12 on the opposite ends of one of the buses 16 to try to set high the write line 20 there-between at the same time. Similarly, as discussed above, it is not currently anticipated that it would be desirable to have a single computer 12 set more than one of its four write lines 20 high. However, it is presently anticipated that there will be occasions wherein it is desirable to set different combinations of the read lines 18 high such that one of the computers 12 can be in a wait state awaiting data from the first one of the chosen computers 12 to set its corresponding write line 20 high.
In the example discussed above, computer 12 e was described as setting one or more of its read lines 18 high before an adjacent computer (selected from one or more of the computers 12 a, 12 b, 12 c or 12 d) has set its write line 20 high. However, this process can certainly occur in the opposite order. For example, if the computer 12 e were attempting to write to the computer 12 a, then computer 12 e would set the write line 20 between computer 12 e and computer 12 a to high. If the read line 18 between computer 12 e and computer 12 a has then not already been set to high by computer 12 a, then computer 12 e will simply wait until computer 12 a does set that read line 18 high. Then, as discussed above, when both of a corresponding pair of write line 20 and read line 18 are high the data awaiting to be transferred on the data lines 22 is transferred. Thereafter, the receiving computer 12 (computer 12 a, in this example) sets both the read line 18 and the write line 20 between the two computers (12 e and 12 a in this example) to low as soon as the sending computer 12 e releases it.
The inventor believes that a key feature for enabling efficient asynchronous communications between devices is some sort of acknowledge signal or condition: In the prior art, most communication between devices has been clocked and there is no direct way for a sending device to know that the receiving device has properly received the data. Methods such as checksum operations may have been used to attempt to insure that data is correctly received, but the sending device has no direct indication that the operation is completed. The present inventive method, as described herein, provides the necessary acknowledge condition that allows, or at least makes practical, asynchronous communications between the devices. Furthermore, the acknowledge condition also makes it possible for one or more of the devices to “go to sleep” until the acknowledge condition occurs. Of course, an acknowledge condition could be communicated between the computers 12 by a separate signal being sent between the computers 12 (either over the interconnecting data bus 16 or over a separate signal line), and such an acknowledge signal would be within the scope of this aspect of the present invention. However, according to the embodiment of the invention described herein, it can be, appreciated that there is even more economy involved here, in that the method for acknowledgement does not require any additional signal, clock cycle, timing pulse, or any such resource beyond that described, to actually affect the communication.
In light of the above discussion of the procedures and means for accomplishing. them, the following brief description of an example of the inventive method can now be understood. FIG. 6 is a flow diagram, designated by the reference character 74, depicting this method example. In an ‘initiate communication’ operation 76 one computer 12 executes an instruction 53 that causes it to attempt to communicate with another computer 12. This can be either an attempt to write or an attempt to read. In a ‘set first line high’ operation 78, which occurs generally simultaneously with the ‘initiate communication’ operation 76, either a read line 18 or a write line 20 is set high (depending upon whether the first computer 12 is attempting to read or to write). As a part of the ‘set first line high’ operation, the computer 12 doing so will, according the presently described embodiment of the operation, cease operation, as described in detail previously herein. In a ‘set second line high’ operation 80 the second line (either the write line 20 or read line 18) is set high by the second computer 12. In a ‘communicate data operation’ data (or instructions, or the like) is transmitted and received over the data lines 22. In a ‘pull lines low’ operation 84, the read line 18 and the write line 20 are released and then pulled low. In a ‘continue’ operation 86 the acknowledge condition causes the computers 12 to resume their operation. In the case of the present inventive example, the acknowledge condition causes an acknowledge signal 86 (FIG. 5) which, in this case, is simply the “high” condition of the acknowledge line 72.
As discussed previously herein, the applicability of the present invention is such that many types of inter-device computer communications can be improved thereby. It is anticipated that the inventive method; wherein some computers can be allowed to “go to sleep” when not in use, will be used to reduce power consumption, reduce heat production, and improve the efficiency of communication between computers and computerized devices in a great variety of applications and implementations.
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Unternehmensklassifikation G06F1/3209, H04L67/10