Source: http://www.google.com/patents/US5666064?dq=6,202,008
Timestamp: 2015-05-05 15:46:41
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Matched Legal Cases: ['art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'arts 21', 'arts 21', 'arts 21', 'arts 21', 'art 8', 'art 8', 'art 21', 'art 8', 'art 8', 'arts 21', 'art 8', 'arts 21', 'arts 21', 'art 8', 'arts 43', 'art 42', 'arts 43', 'arts 43', 'art 8', 'art 8', 'arts 55', 'art 56', 'art 57', 'art 58', 'art 63', 'art 8', 'arts 43', 'art 8']

Patent US5666064 - Semiconductor device, carrier for carrying semiconductor device, and method ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads...http://www.google.com/patents/US5666064?utm_source=gb-gplus-sharePatent US5666064 - Semiconductor device, carrier for carrying semiconductor device, and method of testing and producing semiconductor deviceAdvanced Patent SearchPublication numberUS5666064 APublication typeGrantApplication numberUS 08/441,462Publication dateSep 9, 1997Filing dateMay 15, 1995Priority dateOct 17, 1991Fee statusLapsedAlso published asEP0538010A2, EP0538010A3, EP0689241A2, EP0689241A3, US5475259, US5637923, US5736428, US5750421Publication number08441462, 441462, US 5666064 A, US 5666064A, US-A-5666064, US5666064 A, US5666064AInventorsJunichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi TakenakaOriginal AssigneeFujitsu Limited, Kyushu Fujitsu Elecronics Limited, Fujitsu Automation LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (30), Non-Patent Citations (1), Referenced by (14), Classifications (54), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device, carrier for carrying semiconductor device, and method of testing and producing semiconductor device
US 5666064 AAbstract
1. A method of testing a semiconductor device which comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a substantially rectangular package encapsulating at least the inner leads and the semiconductor chip, wherein the outer leads extend outwardly from the package, said package having an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts due to the different sizes, each of said outer leads having a part which is exposed at the stepped part of the package, said method comprising the steps of:(a) placing the semiconductor device in a testing position on a socket, wherein probes of the socket make contact with the parts of corresponding ones of the outer leads which are exposed at the stepped part of the package of the semiconductor device, and the outer leads do not contact the socket other than through the probes; and (b) checking performance of the semiconductor device by supplying signals from a testing equipment to the outer leads via the probes of the socket. 2. The method of testing the semiconductor device as claimed in claim 1, wherein said step (a) places the semiconductor device on the socket so that in the testing position the stepped part and a smaller one of the upper and lower parts of the package are supported by the socket.
3. The method of testing the semiconductor device as claimed in claim 1, wherein said step (a) accommodates the semiconductor device within a carrier when placing the semiconductor device in the testing position on the socket, said carrier comprising a sidewall part which has a hollow rectangular column shape which opens to top and bottom thereof and locking parts provided on the sidewall part for locking at least corners of the stepped part of the semiconductor device which is accommodated within the sidewall part, said sidewall part surrounding sides of the semiconductor device to protect the outer leads.
4. The method of testing the semiconductor device as claimed in claim 3, wherein said step (a) positions the semiconductor device relative to the socket by pushing against a larger one of the upper and lower parts of the package by a lid of the socket.
5. The method of testing the semiconductor device as claimed in claim 1, wherein each of said outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package, and said step (a) places the semiconductor device in the testing position on the socket so that each probe contacts the wide part of each outer lead.
6. A method of testing a semiconductor device which comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a substantially rectangular package encapsulating at least the inner leads and the semiconductor chip, wherein the outer leads extend outwardly from the package, said package having an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts due to the different sizes, each of said outer leads having a part which is exposed at the stepped part of the package, said method comprising the steps of:(a) placing the semiconductor device in a testing position on a socket, wherein probes of the socket make contact with the parts of corresponding ones of the outer leads exposed at the stepped part of the package of the semiconductor device and supported by the ones of the upper and lower part having a larger size; and (b) checking performance of the semiconductor device by supplying signals from a testing equipment to the outer leads via the probes of the socket. 7. A method of testing a semiconductor device which comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a substantially rectangular package encapsulating at least the inner leads and the semiconductor chip, wherein the outer leads extend outwardly from the package, said package having an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts due to the different sizes, each of said outer leads having a part which is exposed at the stepped part of the package, said method comprising the steps of:(a) placing the semiconductor device in a testing position on a socket, wherein probes of the socket make contact with the parts of corresponding ones of the outer leads which are exposed at the stepped part of the package of the semiconductor device, and the parts of the outer leads extending beyond the stepped part of the package of the semiconductor device do not contact the socket; and (b) checking performance of the semiconductor device by supplying signals from a testing equipment to the outer leads via the probes of the socket. Description
This application is a division of application Ser. No. 07/961,161, filed Oct. 16, 1992, now U.S. Pat. No. 5,475,259.
The present invention generally relates to semiconductor devices, carriers for carrying semiconductor devices and methods of testing producing semiconductor devices, and more particularly to a resin encapsulated semiconductor device having a plurality of pins, a carrier for carrying such a semiconductor device and methods of testing and producing such a semiconductor device.
The number of pins of semiconductor devices has increased due to the improved integration density, and there are demands to further reduce the size of the semiconductor devices. As a result, the width and thickness of the outer leads which are arranged at an extremely fine pitch have become small, and the strength of the outer leads has become poor. For this reason, it is important that no stress is applied to the outer leads during the production stages and up to the mounting of the semiconductor device.
FIG. 1 shows an example of a conventional semiconductor device. FIG. 1(A) shows a plan view of this semiconductor device with a top part thereof omitted, and FIG. 1(B) shows a cross section of this semiconductor device along a line A--A in FIG. 1(A).
A semiconductor device 130 shown in FIG. 1 is the so-called quad flat package type in which a semiconductor chip 133 is mounted on a stage 132 which is provided at a central part of a lead frame 131. The semiconductor chip 133 and inner leads 134 of the lead frame 131 are bonded by wires 135, and are encapsulated by molding a resin 136. In addition, outer leads 137 of the lead frame 131 are respectively formed into an approximate S-shape.
Because the width and thickness of the outer lead 137 have become small, it is necessary to form a solder fillet on the tip end of the outer lead 137 in order to obtain a sufficiently large strength at the time of mounting the semiconductor device 130 on a substrate. Accordingly, the tip end of the outer lead 137 is usually subjected to a plating process before the mounting so as to form the solder, tin or the like on the tip end of the outer lead 137.
The characteristic of the semiconductor device 130 described above is tested when forwarded by the manufacturer or received by the user. When making this test, tip ends of the outer leads 137 of the semiconductor device 130 are contacted by probes or sockets of a test equipment.
However, the width and thickness of the outer lead 137 have become small and the outer lead 137 has become weak as described above. For this reason, there is a problem in that the outer lead 137 may become deformed when contacted by the probe or socket of the test equipment in order to make the test.
In addition, when testing the semiconductor device 130, the length of the signal path from the contact of the probe or socket to the semiconductor chip 133 and including the length of the external lead 137 becomes relatively long. As a result, there is a problem in that the characteristic of the semiconductor device 130 is easily affected by the impedance of this relatively long signal path particularly when the semiconductor device 130 includes an element which operates at a high speed.
Another and more specific object of the present invention is to provide a semiconductor device comprising a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package, where the package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package. According to the semiconductor device of the present invention, it is possible to prevent deformation of the outer leads when testing the performance of the semiconductor device by contacting probes or the like to the outer leads.
Still another object of the present invention is to provide a carrier for carrying a semiconductor device which comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a generally rectangular package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package, where the package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a part which is exposed at the stepped part of the package. The carrier comprises a sidewall part which has a hollow rectangular column shape which opens to top and bottom thereof, and locking parts provided on the sidewall part for locking at least corners of the stepped part of the semiconductor device which is accommodated within the sidewall part, where the sidewall part surrounds sides of the semiconductor device to protect the outer leads. According to the carrier of the present invention, it is possible to protect the outer leads from deformation when handling the semiconductor device.
A further object of the present invention is to provide a method of testing a semiconductor device which comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a generally rectangular package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package, where the package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a part which is exposed at the stepped part of the package. The method comprises the steps of (a) placing the semiconductor device in a testing position on a socket so that probes of the socket make contact with corresponding outer leads which are exposed at the stepped part of the package of the semiconductor device, and (b) checking performance of the semiconductor device by supplying signals from a testing equipment to the outer leads via the probes of the socket. According to the method of testing the semiconductor device of the present invention, it is possible to easily test the performance of the semiconductor device without deforming the outer leads.
Another object of the present invention is to provide a method of producing a semiconductor device which comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a generally rectangular package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package, where the package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a part which is exposed at the stepped part of the package. The method comprises the steps of (a) placing the semiconductor device on a support so that the semiconductor device is supported by the stepped part and a smaller one of the upper and lower parts of the package, and (b) plating a metal on the outer leads. According to the method of producing the semiconductor device of the present invention, it is possible to carry out the plating process with respect to the outer leads without applying an external force on the outer leads which may result in the deformation of the outer leads.
Still another object of the present invention is to provide a method of producing a semiconductor device comprising the steps of (a) placing a semi-completed device having leads in a molding position within a cavity which is formed by first and second dies which connect via a palette, where the cavity is formed by a recess of the first die and an opening of the palette, the first die has a first gate which communicates to the recess, the palette has a second gate which communicates to the opening, and at least one of the first die and the palette has a runner which communicates with the first and second gates, and (b) injecting a resin into the cavity via the runner and the first and second gates to mold a resin package which encapsulates the semi-completed device so that the leads extend outwardly from the resin package, where the recess is larger than the opening so that one half of the package above the leads is larger than the remaining half of the package below the leads and the leads are exposed at a stepped part which is formed by a difference between the sizes of the two halves forming the package. According to the method of producing the semiconductor device of the present invention, it is possible to easily form the package which has one half larger than the other, without forming a mark of the gate of the die.
A further object of the present invention is to provide a semiconductor device comprising a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package, where the package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the exposed part of the package, and a radiator member provided on the stepped part so as to improve thermal conduction of heat generated from the semiconductor chip, where the radiator member is made of a material having a thermal conductivity higher than that of the package. According to the semiconductor device of the present invention, it is possible to efficiently radiate the heat generated from the semiconductor chip.
FIG. 1 shows an example of a conventional semiconductor device in a plan view and a cross sectional view for explaining the problems thereof;
FIG. 2 shows a first embodiment of a semiconductor device according to the present invention in a side view and a bottom view;
FIG. 5 shows modifications of the shape of outer leads;
FIG. 7 shows a third embodiment of the semiconductor device according to the present invention in a side view, a bottom view and an enlarged bottom view in part;
FIG. 14 shows an eighth embodiment of the semiconductor device according to the present invention in a plan view and a side view;
FIG. 15 shows a side view and a bottom view for explaining the forwarding of the eighth embodiment of the semiconductor device;
FIG. 16 shows a side view and a bottom view for explaining the mounting of the eighth embodiment of the semiconductor device;
FIG. 18 shows an embodiment of a carrier according to the present invention which is used to transport the third embodiment of the semiconductor device in a plan view, a bottom view and cross sectional views;
FIG. 19 shows the third embodiment of the semiconductor device inserted into the carrier shown in FIG. 18 in a plan view, a bottom view and cross sectional views;
FIG. 20 is a diagram for explaining an embodiment of a method of producing the semiconductor device according to the present invention;
FIG. 21 is a diagram for explaining the forwarding and packing of the carrier having the semiconductor device inserted therein;
FIG. 23 is a side view in cross section showing a socket which is used in a third embodiment of the method of testing the semiconductor device according to the present invention;
FIG. 24 is a diagram for explaining the operation of the socket shown in FIG. 23;
FIG. 25 is a diagram for explaining a method of mounting the semiconductor device;
FIG. 26 is a ninth embodiment of the semiconductor device according to the present invention in a view;
FIG. 27 shows the ninth embodiment of the semiconductor device into another embodiment of the carrier according to the present invention in a plan view and a bottom view;
FIG. 28 shows cross sectional views respectively along a line e-e' and a line f-f' in FIG. 27 (A);
FIG. 31 is a diagram for explaining a general resin molding of the tape carrier;
FIG. 32 is a diagram for explaining a resin holding of the tape carrier shown in FIG. 30;
FIG. 33 is a diagram for explaining a gate shown in FIG. 32;
FIG. 36 is a side view in cross section showing another example of the conventional semiconductor device having a hetat radiator structure;
A description will be given of a first embodiment of a semiconductor device according to the present invention, by referring to FIG. 2. FIG. 2(A) shows a side view of the first embodiment in partial cross section, and FIG. 2(B) shows a bottom view of the first embodiment.
A semiconductor device 1A shown in FIG. 2 has a chip 4 mounted on a stage 3 of a lead frame 2. The chip and inner leads 5 of the lead frame 2 are bonded by wires 6. A package 7 is formed by molding a resin which encapsulates the chip 4, the stage 3 and the inner leads 5. Outer leads 8 of the lead frame 2 are bent in an approximate S-shape to suit the mounting of the semiconductor device 1A on a circuit substrate (not shown).
FIG. 3 is a cross sectional view for explaining a method of producing the semiconductor device 1A. First, the chip 4 is mounted on the stage 3 of the lead frame 2, and the chip 4 and the inner leads 5 are bonded by the wires 6. Thereafter, the molding part on the periphery of the chip 4 is positioned within a cavity 10 which is formed by an upper and lower metal dies 9a and 9b.
Next, a description will be given of a first method of testing the semiconductor device according to the present invention, by referring to FIG. 4. In this embodiment of the method, it is assumed for the sake of convenience that the first embodiment of the semiconductor device shown in FIG. 2 is tested.
In FIG. 4, a socket 14 of a testing equipment 13 is provided with a number of probes 15 corresponding to the number of outer leads 8 of the semiconductor device 1A. When testing the characteristic of the semiconductor device 1A, the semiconductor device 1A is placed on the socket 14 so that the exposed part 8a of the outer leads 8 of the semiconductor device 1A make electrical contact with the corresponding probes 15. In this testing position, the exposed part 8a and the smaller one of the upper and lower resins 7a and 7b (that is, the lower resin 7b in this case) of the package 7 are supported by the socket 14.
On the other hand, the length of the probe 15 which forms the signal path can be shortened compared to the conventional case. In addition, the signal path can be shortened because the probe 15 makes contact with the corresponding outer lead 8 at a position close to the chip 4, and thus, it is possible to avoid the increase of the impedance which would occur if the signal path were long. As a result, it is possible to carry out an accurate test of the characteristic of the semiconductor device 1A because there is no increase in the impedance which would affect the characteristic of the semiconductor device 1A.
Next, a description will be given of modifications of the shape of the outer leads, by referring to FIG. 5.
In the first embodiment of the semiconductor device shown in FIG. 2, the outer leads 8 have the approximate S-shape. However, according to a first modification shown in FIG. 5(A), each outer lead 8A is bent to an approximate L-shape. Furthermore, according to a second modification shown in FIG. 5(B), each outer lead 8B is not bent and thus has a linear shape. In the modifications shown in FIG. 5(A) and (B), the outer leads 8A and 8B also have the exposed part 8a, and the effects obtained by these modifications are the same as those obtainable by the first embodiment of the semiconductor device.
A semiconductor device 1B shown in FIG. 6 has the exposed part 8a formed on the lower surface of the outer leads 8 and the upper resin 7a is larger than the lower resin 7b, similarly to the first embodiment of the semiconductor device. But in this second embodiment of the semiconductor device, a projection 16 is formed on both sides of each outer lead 8 at the exposed part 8a. The projection 16 is integrally formed on the upper resin 7a.
In FIG. 6, the upper resin 7a of the package 7 is larger than the lower resin 7b. However, it is also possible to make the lower resin 7b of the package 7 larger than the upper resin 7b. In this case, the exposed part 8a is formed at the upper surfaces of the outer leads 8, and the projections 16 are integrally formed on the lower resin 7b. The probes may in this case be arranged above the semiconductor device 1B, so that each probe makes positive electrical contact with the corresponding outer lead 8 at the exposed part 8a by being restricted of its position by the projections 16.
The outer leads 8 shown in FIG. 6 may be shaped in any of the manners shown in FIGS. 2 and 5.
Next, a description will be given of a third embodiment of the semiconductor device according to the present invention, by referring to FIG. 7. FIG. 7(A) shows a side view of the third embodiment in partial cross section, FIG. 7(B) shows a bottom view of the third embodiment, and FIG. 7(C) shows an enlarged bottom view of outer leads at an exposed part. In FIG. 7, those parts which are the same as those corresponding parts in FIG. 2 are designated by the same reference numerals, and a description thereof will be omitted.
A semiconductor device 1C shown in FIG. 7 has a chip 4 mounted on a stage 3 of a lead frame 2. The chip and inner leads 5 of the lead frame 2 are bonded by wires 6. A package 7 is formed by molding a resin which encapsulates the chip 4, the stage 3 and the inner leads 5. Outer leads 8 of the lead frame 2 are bent in an approximate S-shape to suit the mounting of the semiconductor device 1C on a circuit substrate (not shown).
For example, the width of the outer lead 8 is 0.1 mm, the outer leads 8 are arranged at a pitch of 0.3 mm, and the difference between the sizes of the upper and lower resins 7a and 7b is 1.0 mm, as shown in FIG. 7 (C). At the exposed part 8a within the 1.0 mm wide part of the upper resin 7a, the wide parts 21 respectively having the size of 0.3�0.35 mm are arranged in a zigzag or checker-board pattern. This arrangement of the wide parts 21 can easily be realized by forming the wide parts 21 in the process of forming the lead frame 2.
By the provision of the wide parts 21, it becomes possible to align the probes to the corresponding outer leads 8 so as to make positive contact to the corresponding outer leads 8 when making the test, even if the number of leads increases and the width of the lead becomes narrow.
FIG. 8 is a cross sectional view for explaining a method of producing the semiconductor device 1C. First, the chip 4 is mounted on the stage 3 of the lead frame 2, and the chip 4 and the inner leads 5 are bonded by the wires 6. Thereafter, the molding part on the periphery of the chip 4 is positioned within a cavity 10 which is formed by an upper and lower metal dies 9a and 9b.
Next, a description will be given of a second method of testing the semiconductor device according to the present invention, by referring to FIG. 9. In this embodiment of the method, it is assumed for the sake of convenience that the third embodiment of the semiconductor device shown in FIG. 7 is tested.
In FIG. 9, a socket 14 of a testing equipment 13 is provided with a number of probes 15 corresponding to the number of outer leads 8 of the semiconductor device 1C. When testing the characteristic of the semiconductor device 1C, the semiconductor device 1C is placed on the socket 14 so that the exposed part 8a of the outer leads 8 of the semiconductor device 1C make electrical contact with the corresponding probes 15.
In other words, when testing the characteristic of the semiconductor device 1C, it is simply necessary to place the semiconductor device 1C in the testing position on the socket 14. In addition, the contact between the probes 15 and the outer leads 8 is not made via the tip ends of the outer leads, but is made at the exposed part 8a where the three sides of each outer lead 8 are embedded in the upper resin 7a. Accordingly, it is possible to prevent unwanted deformation of the outer leads 8 even if the outer leads 8 are weak, and the test can be carried out with ease. Furthermore, the contact between the probe 15 and the corresponding outer lead 8 is particularly satisfactory if the probe 15 is positioned to make contact with the wide part 21 of the corresponding outer lead 8.
On the other hand, the length of the probe 15 which forms the signal path can be shortened compared to the conventional case. In addition, the signal path can be shortened because the probe 15 makes contact with the corresponding outer lead 8 at a position close to the chip 4, and thus, it is possible to avoid the increase of the impedance which would occur if the signal path were long. As a result, it is possible to carry out an accurate test of the characteristic of the semiconductor device 1A because there is no increase in the impedance which would affect the characteristic of the semiconductor device 1C.
In the third embodiment of the semiconductor device shown in FIG. 7, the outer leads 8 have the approximate S-shape. However, the outer leads 8 may be shaped as shown in the modifications of FIG. 5(A) and (B) described above. The effects obtained by such modifications are the same as those obtainable by the third embodiment of the semiconductor device.
In FIG. 7, the upper resin 7a of the package 7 is larger than the lower resin 7b. However, it is also possible to make the lower resin 7b of the package 7 larger than the upper resin 7b. In this case, the exposed part 8a is formed at the upper surfaces of the outer leads 8, and the projections 16 are integrally formed on the lower resin 7b. The probes may in this case be arranged above the semiconductor device 1C, so that each probe makes positive electrical contact with the corresponding outer lead 8 at the exposed part 8a.
Next, a description will be given of a fourth embodiment of the semiconductor device according to the present invention, by referring to FIG. 10. In FIG. 10, those parts which are the same as those corresponding parts in FIG. 7 are designated by the same reference numerals, and a description thereof will be omitted.
In a semiconductor device 1E shown in FIG. 11, the chip 4 is bonded to the inner ends of a pattern 33 which is made of copper, for example. The outer leads 8 are bonded to the outer ends of the pattern 33 by OLB, laser welding or the like. In this case, in order to prevent the scattering of the pattern 33 during the production stage, a film carrier 35 is mounted on the pattern 33.
Next, a description will be given of a sixth embodiment of the semiconductor device according to the present invention, by referring to FIG. 12. In FIG. 12, those parts which are the same as those corresponding parts in FIG. 7 are designated by the same reference numerals, and a description thereof will be omitted.
Next, a description will be given of a seventh embodiment of the semiconductor device according to the present invention, by referring to FIG. 13. In FIG. 13, those parts which are the same as those corresponding parts in FIG. 7 are designated by the same reference numerals, and a description thereof will be omitted.
Next, a description will be given of an eighth embodiment of the semiconductor device according to the present invention, by referring to FIG. 14. FIG. 14(A) shows a plan view and FIG. 14(B) shows a side view of the eighth embodiment of the semiconductor device. In FIG. 14, those parts which are the same as those corresponding parts in FIG. 7 are designated by the same reference numerals, and a description thereof will be omitted.
A semiconductor device 1H shown in FIG. 14(A) is shown as a tape carrier package. Sprocket holes 92 are provided along both sides of a tape carrier 91 of the lead member. For example, the tape carrier 91 has a thickness of 125 nm or 75 nm and is made of polyimide. Leads 93 having a predetermined pattern and made of a metal film are bonded at a part of the tape carrier 91 between the sprocket holes 92 where one semiconductor device 1H is to be formed. As shown in FIG. 14(B), the lead 93 is bonded on the tape carrier 91 by an adhesive agent 93 having a thickness of 20 nm, for example. The metal film forming the leads 93 may be made of copper which is plated by tin, solder, gold and the like.
In addition, as shown in FIG. 14(B), the tip end of the inner lead 93 of the lead 93 and the chip 4 are connected by a bump 96 which is made of gold or the like. An upper resin 7a and a lower resin 7b which are not shown in FIG. 14 are formed by molding the resin, and the package 7 is formed thereby. In this case, the lower resin 7b of the package 7 is made smaller than the upper resin 7a, similarly to the package 7 shown in FIG. 7. In addition, the wide parts 21 are formed in the zigzag or checker-board arrangement on the upper resin 7a at the exposed part 8a, similarly to the wide parts 21 shown in FIG. 7.
In FIG. 14(B), the leads 93 are bonded on the tape carrier 91 by the adhesive agent 94. However, the leads 93 may be formed in the tape carrier 91 using techniques such as vapor deposition and etching.
The tape carrier 91 is cut along a dotted line A in FIG. 14(A) when the semiconductor device 1H is forwarded. Furthermore, the tape carrier 91 is cut along a dotted line B in FIG. 14(A) when the semiconductor device 1H is mounted. The outer leads 93b after being cut along the dotted line B (and bent where applicable) form the outer leads 8.
Next, a description will be given of the forwarding of the eighth embodiment of the semiconductor device shown in FIG. 14, by referring to FIG. 15. FIG. 15 (A) shows the side view and FIG. 15(B) shows the bottom view of the eighth embodiment of the semiconductor device when it is forwarded.
FIG. 15 shows the semiconductor device 1H which is obtained when the tape carrier 91 is cut along the dotted line A in FIG. 14 and the outer leads 93b are bent. The tip ends of the outer leads 93b are fixed to a tape 91a of the tape carrier 91. In other words, because the outer leads 93b are made of the metal film and are weak, the deformation of the outer leads 93b is prevented by forwarding the semiconductor device 1H in the state where the outer leads 93b are fixed to the tape 91a.
Next, a description will be given of the mounting of the eighth embodiment of the semiconductor device shown in FIG. 14, by referring to FIG. 16. FIG. 16 (A) shows the side view and FIG. 16(B) shows the bottom view of the eighth embodiment of the semiconductor device when it is mounted.
FIG. 16 shows the semiconductor device 1H which is obtained when the tape carrier 91 is cut along the dotted line B in FIGS. 14 and 15. The semiconductor device 1H shown in FIG. 16 is mounted on a circuit substrate or the like.
FIG. 17 is a flow chart for explaining the production steps of the eighth embodiment of the semiconductor device according to the present invention shown in FIG. 14.
Thereafter, a step ST3 cuts a part of the outer leads 93b and the tape carrier 91 as indicated by the dotted line A in FIG. 14, and a step ST4 bends the outer leads 93b as shown in FIG. 15. The cutting of the step ST3 and the bending of the step ST4 may be carried out simultaneously.
A step ST5 inserts the semiconductor device 1H shown in FIG. 15 into a carrier which will be described later. A step ST6 tests the characteristic of the semiconductor device 1H by contacting the probes of the testing equipment to the wide parts 21 at the exposed part 8a, and the semiconductor device 1H is forwarded in a step ST7. A step ST8 cuts the outer leads 93b as indicated by the dotted line B in FIGS. 14 and 15, and the semiconductor device 1H shown in FIG. 16 is mounted on the printed circuit substrate or the like.
FIG. 18 shows an embodiment of the carrier according to the present invention which is used when transporting the third embodiment of the semiconductor device 1C described above. FIG. 18(A) shows a plan view of the carrier, FIG. 18(B) shows a bottom view of the carrier, FIG. 18(C) shows a cross sectional view of the carrier along a line A--A' in FIG. 18(A), and FIG. 18(D) shows a cross sectional view of the carrier along a line B-B' in FIG. 18(A).
In FIG. 18, a carrier 4 has locking parts 43a through 43d which extend from respective upper four corners of a sidewall part 42 which has a hollow rectangular column shape. The locking parts 43a through 43d respectively have pushing claws 44a through 43d on the lower ends thereof.
FIG. 19 shows the carrier 41 having the semiconductor device 1C inserted therein. FIG. 19(A) shows a plan view of the carrier, FIG. 19(B) shows a bottom view of the carrier, and FIG. 19(C) and (D) show cross sectional views of the carrier respectively corresponding to FIG. 18(C) and (D) described above.
In FIG. 19, the four corners of the upper resin 7a of the semiconductor device 1H are fixed by the pushing claws 44a through 44d of the locking parts 43a through 43d of the carrier 41.
As shown in FIG. 19(A), at least a part of each side of the upper resin 7a becomes exposed in the plan view. In addition, the lower resin 7b and the exposed part 8a can be seen in their entirety without being obstructed, as shown in FIG. 19(B). In other words, the state shown in FIG. 19(A) ensures that there is a sufficiently large part of the semiconductor device 1H to be pushed downwardly from above when testing and mounting the semiconductor device 1H. Furthermore, the state shown in FIG. 19(B) enables contact of the probes (socket) to the outer leads 8 at the exposed part 8a.
Next, a description will be given of an embodiment of a method of producing the semiconductor device according to the present invention, by referring to FIG. 20. This embodiment of the producing method produces the semiconductor device 1C by inserting the semiconductor device 1C into the carrier 41. FIG. 20(A) shows a producing machine, and FIG. 20(B) shows the state of the semiconductor device 1C at various parts of the producing machine.
In FIG. 20(A), parts P1 through P4 respectively include dies 51a and 52a and a press 52, and each die 51b is positioned within a belt conveyer 53. A part P5 includes a press 54, carrier combining parts 55a and 55b and a supply part 56 for supplying the carrier 41. In addition, parts P6 and P7 respectively include a driving part 57 and a hand 58 which holds the carrier 41 on a support 59. The part P7 is additionally provided with an ejecting part 58.
In FIG. 20(A) and (B), a lead frame 61 is cut from a package 62 at the part P1, and bars 63 are cut off at the part P2. The outer leads 8 are subjected to a first bending process at the part P3, and are then subjected to a second bending process at the part P4, so that the outer leads 8 have the approximate S-shape or the so-called gull-wing shape.
FIG. 20 shows the production of the third embodiment of the semiconductor device 1C shown in FIG. 7. However, the production of the eighth embodiment of the semiconductor device 1H shown in FIGS. 14 through 16 having the form of the tape carrier package may be produced similarly as described above.
Next, a description will be given of the forwarding and packing of the carrier having the semiconductor device inserted therein, by referring to FIG. 21.
Furthermore, the unwanted parts are cut off as shown in FIG. 20 and the semiconductor device 1C is carried out on the carrier 41 before carrying out the final plating process shown in FIG. 22.
Next, a description will be given of a third embodiment of the method of testing the semiconductor device, by referring to FIGS. 23 and 24. FIG. 23 shows a socket which is used for the test, and FIG. 24 is a diagram for explaining the operation of the socket shown in FIG. 23.
In FIG. 23, a socket 61 which is used as a testing jig is made up of a body 62 which has a box shape slightly larger than the external size of the carrier 41. The carrier 41 is generally positioned by a side part 63 of the body 62. A base 64 is for positioning the lower rein 7b of the semiconductor device 1C is provided at the bottom of the body 62. Probes 66 which are electrically connected to terminals 65 are provided in the periphery of the base 64 in correspondence with the outer leads 8 of the semiconductor device 1C. In addition, a lid 67 for pushing the upper resin 7a of the semiconductor device 1 1C is pivotally supported on the body 62.
In FIG. 24(A), the carrier 41 is generally positioned when the carrier 41 is inserted into the body 62, and in this state, the lower resin 7b of the semiconductor device 1C is placed on and is positioned by the base 64. In this state, the outer leads 8 make contact with the corresponding probes 66 at the exposed part 8a shown in FIG. 7.
Next, a description will be given of a method of mounting the semiconductor device 1C, for example, on a substrate, by referring to FIG. 25.
Then, only the empty carrier 41 is removed by the hand 71 as shown in FIG. 25(C), and the upper resin 7a is held by a hand 75. Furthermore, the semiconductor device 1C is placed at a predetermined position on a substrate 76 by the hand 75 as shown in FIG. 25 (D), and the mounting of the semiconductor device 1C is completed by carrying out a solder reflow process or the like.
Next, a description will be given of a ninth embodiment of the semiconductor device according to the present invention, by referring to FIG. 26. In FIG. 26, those parts which are the same as those corresponding parts in FIG. 7 are designated by the same reference numerals, and a description thereof will be omitted.
In this embodiment, the outer leads 8 of a semiconductor device 1C' shown in FIG. 26 are bent in a direction opposite to those of the semiconductor device 1C shown in FIG. 7(A). Otherwise, the semiconductor device 1C' is the same as the semiconductor device 1C. It is of course possible to make the lower resin 7b of the package 7 larger than the upper resin 7a, as described above. In this case, the construction of the semiconductor device will be identical to that of the semiconductor device 1C shown in FIG. 7 except that the lower resin would have the size of the upper resin 7a shown in FIG. 7 and the upper resin would have the size of the lower resin 7b shown in FIG. 7.
FIG. 27 shows another embodiment of a carrier having the semiconductor device 1C' shown in FIG. 26 inserted therein. FIG. 27(A) shows a plan view of a carrier 41A and FIG. 27(B) shows a bottom view of the carrier 41A. In FIG. 27, those parts which are basically the same as those corresponding parts in FIG. 19 are designated by the same reference numerals, and a description thereof will be omitted.
As may be seen from FIGS. 27 and 28, the carrier 41A does not have locking parts 43a through 43a of the carrier 41 shown in FIG. 19. Instead, the carrier 41A supports the semiconductor device 1C' by the pushing claws 44a through 44d alone. Hence, both the upper resin 7a and the lower resin 7b of the semiconductor device 1C' becomes exposed in bottom view and the top view of the carrier 41A, respectively.
Next, a description will be given of a fourth embodiment of the method of testing the semiconductor device, by referring to FIG. 29. FIG. 29 shows a socket which is used for the test. In FIG. 29, those parts which are the same as those corresponding parts in FIG. 24 are designated by the same reference numerals, and a description thereof will be omitted.
In FIG. 29, a socket 61A which is used as a testing jig has a construction which is basically the same as the socket 61 shown in FIG. 24. The difference between the socket 61 shown in FIG. 24 is that in FIG. 29 the outer leads 8 of the semiconductor device 1C' curve upwardly within the carrier 41A.
Next, a description will be given of a resin molding process with respect to the tape carrier 91 shown in FIG. 14, by referring to FIG. 30. FIG. 30 shows the tape carrier 91 before the chip 4 is mounted thereof. In FIG. 30, those parts which are the same as those corresponding parts in FIG. 14 are designated by the same reference numerals, and a description thereof will be omitted.
FIG. 31 is a diagram for explaining the general resin molding process for the tape carrier. In FIG. 31 (A), the tape carrier 91 is positioned in a cavity 115 which is formed by an upper metal die 114a and a lower metal die 114b. The resin is injected to the cavity 115 of the lower metal die 114b via a runner 117 and a lower gate 116b shown in FIG. 31(C). In this case, a communication hole 118a is formed in the tape carrier 91, and the molding is carried out by supplying the resin from the runner 117 to an upper gate 116a of the upper metal die 114a via the communication hole 118a.
In either case, the molding is carried out by supplying the resin to the upper part of the cavity by forming the communication hole 118a or 118b in the tape carrier 91. However, when the sizes of the upper and lower resins 7a and 7b of the package 7 are different as shown in FIG. 7, for example, problems occur. First, in the case shown in FIG. 31(A), the mark of the upper gate 116a or the lower gate 116b will remain at the exposed part 8a of the upper resin 7a if the size of the cavity 115 is simply made different at the top and bottom. On the other hand, in the case shown in FIG. 31(B), the formation of the communication hole 118b will be limited by the size of the chip 4, and the molding process will be difficult to carry out.
FIG. 32 is a diagram for explaining a resin molding of the tape carrier 91 shown in FIG. 30 according to this embodiment of the method of producing the semiconductor device. FIG. 32(A) is a plan view of a metal die which is used for the resin molding, FIG. 32 (B) shows a cross section along a line A--A in FIG. 32 (A), and FIG. 32(C) shows a cross section along a line B--B in FIG. 32(A).
In FIG. 32, a palette 121 is interposed between an upper metal die 120a and a lower metal die 120b. An upper runner 122a for supplying melted resin is formed at a part (upper gate which will be described later) of the upper metal die 120a making contact with the palette 121. In addition, the lower metal die 120b includes a recess 123a which forms the cavity 123, and a lower gate 124 which communicates to the recess 123a. Rods 125a and 125b are used for separating the upper and lower metal dies 120a and 120b after the resin molding.
The palette 121 includes an opening 123b which forms the cavity 123, a lower runner 122b which forms the runner 122 together with the upper runner 122a, and an upper gate 126 which communicates the opening 123b and the lower runner 122b. In other words, the cavity 123 is formed by the opening 123b of the palette 121 and the recess 123a of the lower metal die 120b which contacts the upper metal die 120a. The recess 123a forms the upper resin 7a, and the opening 123b forms the lower resin 7b. In addition, as shown in FIG. 32(B), a communication hole 127 is formed in the palette 121 to communicate the upper runner 122a to the lower gate 124 of the lower metal die 120b.
FIG. 33 is a diagram for explaining the gate shown in FIG. 32. FIG. 33(A) shows a plan view of the palette 121, and FIG. 33(B) shows a plan view of the lower metal die 120b. As shown in FIG. 33, the lower runner 122b and the opening 123b of the palette 121 communicate at the upper gate 126, and the communication hole 127 of the lower runner 122b communicates to the lower gate 124 of the lower metal die 120b. It is of course possible to provide the runner 123 in only the palette 121 or in only the upper metal die 120a.
By positioning the tape carrier 91 shown in FIG. 30 within the cavity 123 using the palette described before and injecting the resin from the runner 122, the resin flows to the lower gate 124 from the communication hole 127 of the palette 121 via the second hole 113 of the tape carrier 91. Furthermore, the resin within the cavity 123 flows into the recess 123a via the first holes 112 and flows to the upper gate 126. Hence, the resin molding process can be carried out smoothly in a satisfactory manner.
of course, the upper and lower metal dies 120a and 120b may be reversed in FIG. 32.
FIGS. 35 and 36 show an example of a conventional semiconductor device having a radiator member. A semiconductor device 501 shown in FIGS. 35 and 36 generally includes a package 502 and radiator fins 503. The package 502 is made of a resin, and the radiator fins 503 are made of a metal having a satisfactory radiator efficiency.
In other words, the pin grid array package described above was generally used as the package structure having the improved radiator characteristic. However, due to the recent trend to employ the surface mounting, there are demands to realize a surface mounting type package having an improve radiator efficiency. In addition, there are also demands to reduce the thickness of the semiconductor device, and it is thus desirable to improve the radiator characteristic without the use of the bulky radiator fins 503.
FIG. 37 shows another example of the conventional semiconductor device which was developed to satisfy the above described demands. A semiconductor device 505 shown in FIG. 37 generally includes a semiconductor chip 506, leads 507, a package 508, a radiator plate 509, and a stage 510. The semiconductor chip 506 is die-bonded on the lower surface of the stage 510, and the semiconductor chip 506 and the leads 507 are connected by Au wires 511. Outer lead parts of the leads 107 extend outside the package 508 which is made of a resin, and are formed into a gull-wing shape, for example, to suit surface mounting of the semiconductor device 505.
The package 508 encapsulates the semiconductor chip 506, inner lead parts of the leads 507, the stage 510 and the like. In addition, a cavity 512 is formed on top of the package 508. The radiator plate 509 is fixed within the cavity 512 by an adhesive agent 513 having a high thermal conductivity.
FIGS. 38 and 39 respectively are a perspective view and a side view in cross section of the tenth embodiment of the semiconductor device. A semiconductor device 220 shown in FIGS. 38 and 39 generally includes a package 221 and a radiator member 222. The radiator member 222 is made of a material having a thermal conductivity higher than that of the package 221.
The package 221 is formed from an epoxy resin, for example, and encapsulates a semiconductor chip 223, a stage 224 and inner leads 225a of leads 225. That is, the package 221 is the so-called surface mounting type package. The semiconductor chip 223 is die-bonded on the stage 224 and is resin-encapsulated, so that the stage 224 is completely embedded and encapsulated within the package 221 as shown in FIG. 39. Accordingly, compared to the conventional semiconductor device 505 shown in FIG. 37, it is possible to positively prevent moisture from entering within the package 221 by the structure of the package 221. Even if the package 221 is subjected to a heating process thereafter, it is possible to suppress the generation of vapor and accordingly prevent the package 221 from cracking or breaking. In other words, it is possible to improve the reliability of the semiconductor device 220.
The package 221 has a shape such that an upper body 221a which is located above the leads 225 becomes smaller with respect to a lower body 221b which is located below the leads 225. In addition, as shown in FIG. 40 which shows the semiconductor device 220 with the radiator member 222 removed, a stepped part is formed between the upper and lower bodies 221a and 221b due to the difference between the sizes of the upper and lower bodies 221a and 221b. The outer leads 225b of the leads 225 are exposed at the upper surface of the stepped part, that is, at the upper surface of the lower body 221b. The outer leads 225b are shaped into the gull-wing shape on the outside of the lower body 221b to suit mounting of the semiconductor device 220 on the circuit substrate or the like.
Next, a description will be given of a method of producing the package 221 having the upper body 21a which is smaller than the lower body 21b, by referring to FIG. 41. In FIG. 41, the semiconductor chip 223 is die-bonded on the stage 224 of a lead frame 226 which already has the stage 224 and the leads 225 formed thereon. The semiconductor chip 223 and the inner leads 225a are bonded by wires 227. The lead frame 226 having the semiconductor chip 223 mounted thereon is inserted into a metal die 228 which is made up of upper and lower dies 228a and 228b. A cavity 228a-1 formed in the upper die 228a is smaller than a cavity 228a-2 formed in the lower die 228b.
Returning now to the description of FIGS. 38 and 39, the radiator member 222 is made of an aluminum plate and has a height which is approximately the same as a projecting length L of the lower body 221b from the upper body 221a. In addition, the shape of the radiator member 222 in the plan view viewed from above the semiconductor device 220 is approximately the same as the shape of the lower body 221b in the plan view. An inserting hole 230 is formed at a central part of the radiator member 222. The position of the inserting hole 230 corresponds to the position and shape of the upper body 221a.
Next, a description will be given of the radiator function of the semiconductor device 220, by referring to FIG. 39. The radiator member 222 surrounds the upper body 221a. Furthermore, the radiator member 222 is also bonded to the leads 225 via the adhesive agent 231. For this reason, the heat which is generated from the semiconductor chip 223 mainly conducts to the outside via the package 221 and the leads 225. The heat conducting through the package 221 is transferred to the radiator member 222 at the connecting part where the inserting hole 230 and the upper body 221a meet. On the other hand, the heat conducting through the leads 225 is transferred to the radiator member 222 where the leads 225 and the radiator member 222 connect via the adhesive agent 231.
On the other hand, the height of the radiator member 222 is approximately the same as the projecting length L of the lower body 221b from the upper body 221a. In addition, the shape of the radiator member 222 in the plan view is approximately the same as the shape of the lower body 221b in the plan view. Accordingly, in the state where the radiator member 222 is mounted on the package 221, the overall height and size of the semiconductor device 220 can be kept approximately the same as those 0f the semiconductor device having no radiator member 222. In other words, the thickness of the semiconductor device 220 can be kept the same even if the radiator member 222 is provided. Therefore, it is possible to realize a thin semiconductor device having the improved radiator efficiency.
Next, a description will be given of an eleventh embodiment of the semiconductor device according to the present invention, by referring to FIG. 42. In FIG. 42, those parts which are the same as those corresponding parts in FIGS. 38 and 39 are designated by the same reference numerals, and a description thereof will be omitted.
But in this eleventh embodiment of the semiconductor device, a support bar 233 also extends outside a package 228 of a semiconductor device 232 together with outer leads 225a of the leads 225. In addition, the support bar 233 is bonded to the radiator member 222 via the adhesive agent 231.
The semiconductor chip 223 is mounted on the stage 224, and this stage 224 most conducts the heat generated from the semiconductor chip 223. Hence, by extending the support bar 233 which is integrally formed on the stage 224 outside the package 221 and bonding the support bar 233 to the radiator member 222 via the adhesive agent 231, it becomes possible to more efficiently radiate the heat which is generated from the semiconductor chip 223.
Of course, the tenth and eleventh embodiments of the semiconductor device is not limited to the surface mounting type package, but is also applicable similarly to other package structures.
FIGS. 42 through 45 respectively show modifications of the fourth through seventh embodiments of the semiconductor device shown in FIGS. 10 through 13. In FIGS. 42 through 45, those parts which are the same as those corresponding parts in FIGS. 10 through 13 are designated by the same reference numerals, and a description thereof will be omitted. These modifications also have a radiator member.
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