Source: http://www.google.com/patents/US7970987?dq=inassignee:google
Timestamp: 2017-06-26 02:29:08
Document Index: 132193430

Matched Legal Cases: ['Application No. 05', 'Application No. 06', 'application No. 02703078', 'Application No. 2002', 'Application No. 2002', 'Application No. 2008', 'Application No. 2003', 'Application No. 2008', 'Application No. 2008', 'Application No. 02703078', 'Application No. 2002', 'Application No. 200610142358', 'Application No. 200610142359', 'Application No. 02803882']

Patent US7970987 - Partial block data programming and reading operations in a non-volatile memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsData in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of...http://www.google.com/patents/US7970987?utm_source=gb-gplus-sharePatent US7970987 - Partial block data programming and reading operations in a non-volatile memoryAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7970987 B2Publication typeGrantApplication numberUS 12/900,397Publication dateJun 28, 2011Filing dateOct 7, 2010Priority dateJan 19, 2001Fee statusPaidAlso published asCN1290021C, CN1514971A, CN1924830A, CN1924831A, CN100485641C, CN100485642C, DE60211653D1, DE60211653T2, EP1352394A2, EP1352394B1, EP1645964A2, EP1645964A3, EP1653323A2, EP1653323A3, EP1653323B1, EP2953030A1, US6763424, US6968421, US7657702, US7818490, US8316177, US20020099904, US20040210708, US20060031627, US20090150601, US20110029724, US20110258386, WO2002058074A2, WO2002058074A3, WO2002058074A9Publication number12900397, 900397, US 7970987 B2, US 7970987B2, US-B2-7970987, US7970987 B2, US7970987B2InventorsKevin M. ConleyOriginal AssigneeSandisk CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (93), Non-Patent Citations (65), Referenced by (13), Classifications (19), Legal Events (10) External Links: USPTO, USPTO Assignment, EspacenetPartial block data programming and reading operations in a non-volatile memory
US 7970987 B2Abstract
Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.
providing a plurality of blocks of memory storage elements that are individually erasable as a unit and which are individually organized into a plurality of pages of memory storage elements that are individually programmable together,
programming at least one page of data in one of the plurality of blocks;
programming at least one page of new data in one of said one or another of the plurality of blocks, the at least one page of new data rendering the at least one page of data to become at least one page of superceded data
identifying the at least one page of superceded data and the at least one page of new data by a common logical address,
recording an indication of a relative time of programming the at least one page of new data and the at least one page of superceded data; and
wherein the at least one page of superceded data is less than all the data contained in said one block.
2. The method of claim 1, wherein the indication of a relative time of programming is recorded for the individual pages in which the new and superceded data are programmed, whereby the at least one page of new data is distinguishable from the at least one page of superceded data by their recorded indications of relative time of programming.
3. A method of operating a non-volatile memory system, comprising:
programming at least one page of new data in one of said one or another of the plurality of blocks, the at least one page of new data rendering the at least one page of data to become at least one page of superceded data,
wherein the data in at least another page of said one block that is not replaced are not copied into said one or another block as part of substituting the new data for the superceded data.
4. The method of claim 1, wherein nothing is written into the at least one page of superceded data as part of substituting the new data for the superceded data.
5. The method of claim 1, wherein recording an indication of a relative time of programming the new and superceded data includes storing a value of a clock at each of the times that the new and superceded data are programmed.
6. The method of claim 1, wherein recording an indication of a relative time of programming the new and superceded data includes storing a different value of a sequence of numbers at each of the times that the new and superceded data are programmed.
7. The method of either of claim 5 or 6, wherein storing the value indicating a relative time of programming the new and superceded data includes storing the individual values within the same pages as the new and superceded data to which the values relate.
8. The method of claim 1, wherein programming the new data into at least one page of another said one or another of the plurality of blocks includes programming the new data into a first available unused pages within said one or another block in a predefined order.
9. The method of claim 1, wherein identifying the at least one page of superceded data and the at least one page of new data by a common logical address includes recording at least part of the common logical address in the individual pages as overhead data.
10. The method of claim 9, including building a table in volatile memory including multiple physical block addresses for the common logical address.
11. A method of reading data that has been updated according to claim 2, comprising:
reading pages of data from said one block and, if new data has been programmed thereinto, said another block,
identifying any multiple pages of data that have the same logical address,
utilizing the recorded relative time of programming the new and superceded data to identify a most current of any pages having the same logical address, and
assembling data in the most current of any pages having the same logical address along with pages in said at least another page of said one block that have not been updated.
12. A method of operating a non-volatile memory system, comprising:
programming at least one page of new data in one of said one or another of the plurality of blocks, the at least one page of new data rendering the at least one page of data to become at least one page of superceded data, wherein pages within the individual blocks are programmed in a designated order,
reading pages of data within said one and, if new data has been programmed thereinto, another block in a reverse order from which they were programmed, and
passing over any pages of data so read which have the same logical page address as a page whose data has already been read; and
13. The method of either one of claim 11 or 12, additionally comprising operating the individual memory storage elements with more than two storage states, thereby storing more than one bit of data in each storage element, and reading pages of data includes reading the more than two storage states from the individual memory storage elements.
14. The method of claim 1, additionally comprising operating storage elements of the individual memory cells with more than two storage states, thereby storing more than one bit of data in each storage element.
15. The method of claim 14, wherein the storage elements include individual floating gates.
16. The method of claim 1, wherein the non-volatile memory system is formed within an enclosed card having an electrical connector along one edge thereof that operably connects with a host system. Description
This application is a continuation of application Ser. No. 11/250,238, filed Oct. 13, 2005, now U.S. Pat. No. 7,818,490, which is a continuation of application Ser. No. 10/841,388, filed May 7, 2004, now U.S. Pat. No. 6,968,421, which in turn is a continuation of application Ser. No. 09/766,436, filed Jan. 19, 2001, now U.S. Pat. No. 6,763,424, which applications are incorporated herein in their entirety by this reference. This application is related to application Ser. No. 12/371,460, filed on Feb. 13, 2009, now U.S. Pat. No. 7,657,702.
This invention pertains to the field of semiconductor non-volatile data storage system architectures and their methods of operation, and has application to data storage systems based on flash electrically erasable and programmable read-only memories (EEPROMs).
In one commercial form, each block contains enough cells to store one sector of user data plus some overhead data related to the user data and/or to the block in which it is stored. The amount of user data included in a sector is the standard 512 bytes in one class of such memory systems but can be of some other size. Because the isolation of individual blocks of cells from one another that is required to make them individually erasable takes space on the integrated circuit chip, another class of flash memories makes the blocks significantly larger so there is less space required for such isolation. But since it is also desired to handle user data in much smaller sectors, each large block is often further partitioned into individually addressable pages that are the basic unit for reading and programming user data (unit of programming and/or reading). Each page usually stores one sector of user data, but a page may store a partial sector or multiple sectors. A “sector” is used herein to refer to an amount of user data that is transferred to and from the host as a unit.
According to one principal aspect of the present invention, briefly and generally, both the copying of unchanged data from the original to the new blocks and the need to update flags within the original block are avoided when the data of fewer than all of the pages within a block are being updated. This is accomplished by maintaining both the superceded data pages and the updated pages of data with a common logical address. The original and updated pages of data are then distinguished by the relative order in which they were programmed. During reading, the most recent data stored in the pages having the same logical address are combined with the unchanged pages of data while data in the original versions of the updated pages are ignored. The updated data can be written to either pages within a different block than the original data, or to available unused pages within the same block. In one specific implementation, a form of time stamp is stored with each page of data that allows determining the relative order that pages with the same logical address were written. In another specific implementation, in a system where pages are programmed in a particular order within the blocks, a form of time stamp is stored with each block of data, and the most recent copy of a page within a block is established by its physical location within the block.
Another principal aspect of the present invention groups together two or more blocks positioned in separate units of the memory array (also termed “sub-arrays”) for programming and reading together as part of a single operation. Such a multiple block group is referenced herein as a “metablock.” Its component blocks may be either all located on a single memory integrated circuit chip, or, in systems using more than one such chip, located on two or more different chips. When data in fewer than all of the pages of one of these blocks is updated, the use of another block in that same unit is normally required. Indeed, the techniques described above, or others, may be employed separately with each block of the metablock. Therefore, when data within pages of more than one block of the metablock are updated, pages within more than one additional block are required to be used. If there are four blocks of four different memory units that form the metablock, for example, there is some probability that up to an additional four blocks, one in each of the units, will be used to store updated pages of the original blocks. One update block is potentially required in each unit for each block of the original metablock. In addition, according to the present invention, updated data from pages of more than one of the blocks in the metablock can be stored in pages of a common block in only one of the units. This significantly reduces the number of unused erased blocks that are needed to store updated data, thereby making more efficient use of the available memory cell blocks to store data. This technique is particularly useful when the memory system frequently updates single pages from a metablock.
FIG. 1 is a block diagram of a typical prior art flash EEPROM memory array with memory control logic, data and address registers;
DESCRIPTION OF EXISTING LARGE BLOCK MANAGEMENT TECHNIQUES
FIG. 1 shows a typical flash memory device internal architecture. The primary features include an input/output (I/O) bus 411 and control signals 412 to interface to an external controller, a memory control circuit 450 to control internal memory operations with registers for command, address and status signals. One or more arrays 400 of flash EEPROM cells are included, each array having its own row decoder (XDEC) 401 and column decoder (YDEC) 402, a group of sense amplifiers and program control circuitry (SA/PROG) 454 and a data register 404. Presently, the memory cells usually include one or more conductive floating gates as storage elements but other long term electron charge storage elements may be used instead. The memory cell array may be operated with two levels of charge defined for each storage element to therefore store one bit of data with each element. Alternatively, more than two storage states may be defined for each storage element, in which case more than one bit of data is stored in each element.
CS—Chip Select. Used to activate flash memory interface. RS—Read Strobe. Used to indicate the I/O bus is being used to transfer data from the memory array. WS—Write Strobe. Used to indicate the I/O bus is being used to transfer data to the memory array. AS—Address Strobe. Indicates that the I/O bus is being used to transfer address information. AD[7:0]—Address/Data Bus This I/O bus is used to transfer data between controller and the flash memory command, address and data registers of the memory control 450. This interface is given only as an example as other signal configurations can be used to give the same functionality. FIG. 1 shows only one flash memory array 400 with its related components, but a multiplicity of such arrays can exist on a single flash memory chip that share a common interface and memory control circuitry but have separate XDEC, YDEC, SA/PROG and DATA REG circuitry in order to allow parallel read and program operations.
In other prior art systems, flags are recorded with the user data in pages and are used to indicate that pages of data in the original block that are being superceded by the newly written data are invalid. Only the new data is written to the newly assigned block. Thus the data in pages of the block not involved in the write operation but contained in the same physical block as the superceded data need not be copied into the new block. This operation is illustrated in FIG. 6, where pages 3-5 of data within an original block 21 (PBN0) are again being updated. Updated pages 3-5 of data 23 are written into corresponding pages of a new block 25. As part of the same operation, an old/new flag 27 is written in each of the pages 3-5 to indicate the data of those pages is old, while the flag 27 for the remaining pages 0-2, 6 and 7 remains set at “new”. Similarly, the new PBN1 is written into another overhead data field of each of the pages 3-5 in the block 21 to indicate where the updated data are located. The LBN and page are stored in a field 31 within each of the physical pages.
FIGS. 7A and 7B are tables of the correspondence between the data LBN/page and the PBN/page before (FIG. 7A) and after (FIG. 7B) the data update is complete. The unchanged pages 0-2, 6 and 7 of the LBN remain mapped into PBN0 while the updated pages 3-5 are shown to reside in PBN1. The table of FIG. 7B is built by the memory controller by reading the overhead data fields 27, 29 and 31 of the pages within the block PBN0 after the data update. Since the flag 27 is set to “old” in each of pages 3-5 of the original block PBN0, that block will no longer appear in the table for those pages. Rather, the new block number PBN1 appears instead, having been read from the overhead fields 29′ of the updated pages. When data are being read from LBN0, the user data stored in the pages listed in the right column of FIG. 7B are read and then assembled in the order shown for transfer to the host.
There are many different types of flash EEPROM, each of which presents its own limitations that must be worked around to operate a high performance memory system formed on a small amount of integrated circuit area. Some do not provide for writing any data into a page that has already been programmed, so updating flags in a page that contains superceded data, as described above, is not possible. Others allow such flags to be written but doing so in pages whose data is being superceded can disturb data in other pages of the same block that remain current.
It will be noted that, in the example of FIG. 8, the new data pages 37 are stored in the first three pages 0-2 of the new block PBN1, rather than in the same pages 3-5 which they replace in the original block PBN0. By keeping track of the individual logical page numbers, the updated data need not necessarily be stored in the same page offset of the new block as that of the old block where superceded data is contained. Page(s) of updated data can also be written to erased pages of the same block as the page of data being superceded.
An efficient way to organize pages of data being read from a physical block, where one or more of the pages has been updated, is illustrated by FIG. 13. Enough space is provided in a volatile memory of the controller to buffer at least several pages of data at a time, and preferably a full block of data. That is what is shown in FIG. 13. Sixteen pages of data, equal to the amount stored in a non-volatile memory block, are stored in the controller memory. Since the pages are most commonly read out of order, each page of data is stored in its proper position with respect to the other pages. For example, in the reverse page read operation of FIG. 11, logical page 8 if the first to be read, so it is stored in position 8 of the controller memory, as indicated by the “1” in a circle. The next is logical page 7, and so forth, until all pages of data desired by the host are read and stored in the controller memory. The entire set of page data is then transferred to the host without having to manipulate the order of the data in the buffer memory. The pages of data have already be organized by writing them to the proper location in the controller memory.
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No. 09/620,544, filed Jul. 21, 2000, 48 pages.41Photo International, Digital: SanDisk Introduces 64, 80, 96 and 160 MB CompactFlash Memory, Feb. 1999, 1 page.42SanDisk Corporation, Preliminary MultiMediaCard Product Manual, Apr. 28, 1998, 96 pages.43SanDisk Corporation, SDP-32 Mbit "Mizer" Low Cost HD, Logical Format 20-10-00050, Rev. 8, Dec. 5, 1997, 32 pages.44Sandisk Israel, MediaClip Memory Card MMC Controller Top Level Design, Version 0.1, Nov. 13, 1996, 74 pages.45The Patent Office of the People's Republic of China, "Notification of the First Office Action," corresponding Chinese Patent Application No. 200610142358.3 on Dec. 14, 2007, 3 pages.46The Patent Office of the People's Republic of China, "Notification of the First Office Action," corresponding Chinese Patent Application No. 200610142359.8 on Dec. 14, 2007, 8 pages (including translation.47The Patent Office of the People's Republic of China, "Notification of the First Office Action," mailed in related Chinese Application No. 02803882.7 on Jan. 27, 2006, 14 pages, including translation.48United States International Trade Commission, "In the Matter of Certain Flash Memory Controllers, Drives, Memory Cards and Media Players, and Products Containing Same," Inv. No. 337-TA-619, Initial Determination on Violation of Section 337 and Recommended Determination on Remedy and Bond, Administrative Law Judge Charles E. Bullock, Public Version, May 5, 2009, 398 pages.49United States International Trade Commission, In the Matter of Certain Flash Memory Controllers, Drivers, Memory Cards, and Media Palyers and Products Containing same, Inv. No. 337-TA-619, Order No. 33: Order Construing the Terms of the Asserted Claims of the Patents at Issue, Jul. 15, 2008, pp. i-iii, 1-10 and 54-67.50United States International Trade Commission, Investigation No. 337-TA-619, Dr. Subramanian's testimony dated Oct. 30, 2008, 60 pages.51United States International Trade Commission, Investigation No. 337-TA-619, Dr. Subramanian's testimony dated Oct. 31, 2008, 59 pages.52United States International Trade Commission, Investigation No. 337-TA-619, Dr. Thomas Rhyne's testimony dated Oct. 27, 2008, 86 pages.53United States International Trade Commission, Investigation No. 337-TA-619, Dr. Thomas Rhyne's testimony dated Oct. 28, 2008, 84 pages.54United States International Trade Commission, Investigation No. 337-TA-619, Dr. Thomas Rhyne's testimony dated Oct. 29, 2008, 34 pages.55United States International Trade Commission, Investigation No. 337-TA-619, Niles Kynett's testimony dated Oct. 29, 2008, 22 pages.56United States International Trade Commission, Investigation No. 337-TA-619, Niles Kynett's testimony dated Oct. 30, 2008, 23 pages.57United States International Trade Commission, Investigation No. 337-TA-619, Notice of Prior Art of Respondents Apacer Technology, Inc. and Apacer Memory America, Inc., Silicon Motion Technology Corporation, Silicon Motion, Inc. (Taiwan), Silicon Motion, Inc. (California) and Silicon Motion International, Inc., Transcend Information, Inc. (Taiwan), Transcend Information, Inc. (California) and Transcend Information Maryland, Inc., dated Jul. 11, 2008, 17 pages.58United States International Trade Commission, Investigation No. 337-TA-619, Professor M. Ray Mercer's testimony dated Nov. 3, 2008, 30 pages.59United States International Trade Commission, Investigation No. 337-TA-619, Respondents Kingston Technology Co., Inc., Kingston Technology Corporation, Memosun, Inc., Payton Technology Corporation, and Phison Electronics Corporation's Notice of Prior Art, dated Jul. 11, 2008, 19 pages.60United States International Trade Commission, Investigation No. 337-TA-619, Respondents LG Electronics, Inc. and LG Electronics U.S.A., Inc's Notice of Prior Art, Jul. 11, 2008, 16 pages.61United States International Trade Commission, Investigation No. 337-TA-619, The Heller Respondents' Notice of Prior Art, dated Jul. 11, 2008, 23 pages.62United States International Trade Commission, Investigation No. 337-TA-619, witness statement of Kevin Conley dated Oct. 9, 2008, 9 pages.63USPTO, "Notice of Allowance and Fee(s) Due," mailed in related U.S. Appl. No. 12/371,460 on Nov. 16, 2009, 24 pages.64V. Niles Kynett, "Expert Report on the Invalidity of the '424 Patent," dated Aug. 8, 2008, 99 pages (including Exhibit 4.).65Wells et al. "Flash Solid State Drive with 6MB/s Read/Write Channel and Data Compression," ISSCC 93/Session 3/Non-Volatile, Dynamic, and Experimental Memories/Paper WP 3.6, 4 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8346051 *May 22, 2008Jan 1, 2013Panasonic CorporationRecording apparatus and recording methodUS9116793Jun 12, 2012Aug 25, 2015International Business Machines CorporationMaintaining versions of data in solid state memoryUS9122581Jun 12, 2012Sep 1, 2015International Business Machines CorporationData versioning in solid state memoryUS9122582Jun 12, 2012Sep 1, 2015International Business Machines CorporationFile system for maintaining data versions in solid state memoryUS9122584Sep 14, 2012Sep 1, 2015International Business Machines CorporationFile system for maintaining data version in solid state memoryUS9135161Jun 12, 2012Sep 15, 2015International Business Machines CorporationFlash translation layer system for maintaining data versions in solid state memoryUS9135162Sep 14, 2012Sep 15, 2015International Business Machines CorporationData versioning in solid state memoryUS9135163Sep 14, 2012Sep 15, 2015International Business Machines CorporationMaintaining versions of data in solid state memoryUS9229852Sep 14, 2012Jan 5, 2016International Business Machines CorporationFlash translation layer system for maintaining data versions in solid state memoryUS9460802Jul 15, 2015Oct 4, 2016International Business Machines CorporationMaintaining versions of data in solid state memoryUS9575682Aug 10, 2016Feb 21, 2017International Business Machines CorporationMaintaining versions of data in solid state memoryUS9582511Sep 8, 2016Feb 28, 2017International Business Machines CorporationMaintaining versions of data in solid state memoryUS20100177250 *May 22, 2008Jul 15, 2010Hiromasa HoshinoRecording apparatus and recording method* Cited by examinerClassifications U.S. Classification711/103, 711/115International ClassificationG06F12/00, G11C16/02, G06F12/02, G11C16/10, G11C16/06Cooperative ClassificationG06F2212/7209, G06F2212/1032, G06F2212/1016, G11C2216/16, G11C16/105, G11C16/102, G06F2212/7208, G06F12/0246, G06F2212/7202European ClassificationG06F12/02D2E2, G11C16/10E, G11C16/10E2Legal EventsDateCodeEventDescriptionAug 6, 2013ASAssignmentOwner name: INTELLIGENT INTELLECTUAL PROPERTY HOLDINGS LLC., DFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:030953/0253Effective date: 20130801Aug 21, 2013ASAssignmentOwner name: SANDISK CORPORATION, CALIFORNIAFree format text: SECURITY AGREEMENT;ASSIGNOR:INTELLIGENT INTELLECTUAL PROPERTY HOLDINGS LLC;REEL/FRAME:031074/0651Effective date: 20130820Dec 5, 2013ASAssignmentOwner name: PS3 LUXCO SARL, LUXEMBOURGFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTELLIGENT INTELLECTUAL PROPERTY HOLDINGS LLC;REEL/FRAME:031723/0836Effective date: 20130821Dec 6, 2013ASAssignmentOwner name: PS2 LUXCO SARL, LUXEMBOURGFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PS3 LUXCO SARL;REEL/FRAME:031734/0555Effective date: 20130821Dec 12, 2013ASAssignmentOwner name: LONGITUDE FLASH MEMORY SYSTEMS S.A.R.L., LUXEMBOURFree format text: CHANGE OF NAME;ASSIGNOR:PS2 LUXCO S.A.R.L.;REEL/FRAME:031814/0068Effective date: 20131112Dec 3, 2014FPAYFee paymentYear of fee payment: 4Oct 20, 2015IPRAia trial proceeding filed before the patent and appeal board: inter partes reviewFree format text: TRIAL NO: IPR2015-01931Opponent name: APPLE INC.Effective date: 20150918Mar 31, 2016ASAssignmentOwner name: SANDISK TECHNOLOGIES, INC., TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LONGITUDE FLASH MEMORY SYSTEMS SARL;REEL/FRAME:038166/0445Effective date: 20160318May 25, 2016ASAssignmentOwner name: SANDISK TECHNOLOGIES LLC, TEXASFree format text: CHANGE OF NAME;ASSIGNOR:SANDISK TECHNOLOGIES INC;REEL/FRAME:038807/0850Effective date: 20160516May 27, 2016ASAssignmentOwner name: SANDISK CORPORATION, CALIFORNIAFree format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNORS:SANDISK CORPORATION;SANDISK TECHNOLOGIES, INC.;REEL/FRAME:038825/0137Effective date: 20160427RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services