Source: http://www.google.fr/patents/US20080158958
Timestamp: 2013-05-25 05:52:13
Document Index: 130880397

Matched Legal Cases: ['art.\n2', 'art.\n3', 'art.\n10', 'art.\n20', 'art.\n21', 'art.\n28', 'art.\n38', 'art.\n39']

Brevet US20080158958 - Memory device with reduced reading - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Historique Web | Connexion Recherche avanc�e dans les brevets BrevetsA method for data storage includes providing a memory, which includes first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency. An item of data intended for storage in the memory is divided into first and second...http://www.google.fr/patents/US20080158958?utm_source=gb-gplus-shareBrevet US20080158958 - Memory device with reduced reading Num�ro de publicationUS20080158958 A1Type de publicationDemande Num�ro de demande11/958,011 Date de publication3 juil. 2008 Date de d�p�t17 d�c. 2007 Date de priorit�17 d�c. 2006Autre r�f�rence de publicationUS7593263 Num�ro de publicationUS 2008/0158958 A1US2008/0158958A1 InventeursGil SemoOfir ShalviDotan Sokolov Cessionnaire d'origineAnobit Technologies Ltd. Classification aux �tats-Unis365/185.8365/185.9365/185.18 Classification internationaleG11C16/04G11C16/06 Classification coop�rativeG11C16/26 Classification europ�enneG11C16/26R�f�rences R�f�renc� par (8)Liens externesUSPTO Cession USPTO EspacenetMemory device with reduced readingUS 20080158958 A1 R�sum� A method for data storage includes providing a memory, which includes first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency. An item of data intended for storage in the memory is divided into first and second parts. The first part is stored in the first memory cells and the second part is stored in the second memory cells. In response to a request to retrieve the item of data from the memory, the first part is read from the first memory cells and provided as output. The second part is read from the second memory cells, and provided as output subsequently to outputting the first part.
providing a memory, which comprises first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency; dividing an item of data intended for storage in the memory into first and second parts; storing the first part in the first memory cells and the second part in the second memory cells; and in response to a request to retrieve the item of data from the memory, reading the first part from the first memory cells and outputting the read first part, reading the second part from the second memory cells, and outputting the read second part subsequently to outputting the first part.
2. The method according to claim 1, wherein reading the second part comprises reading the second part concurrently with outputting the first part.
3. The method according to claim 1, wherein the first and second memory cells are formed using respective, different first and second memory device technologies.
4. The method according to claim 3, wherein the first memory cells comprise NOR Flash cells and wherein the second memory cells comprise NAND Flash cells.
5. The method according to claim 1, wherein the memory comprises an array of analog memory cells, and wherein the first and second memory cells comprise respective first and second groups of the memory cells in the array.
6. The method according to claim 1, wherein storing the first part comprises programming the first memory cells using a first number of nominal analog values to assume a respective first number of possible memory states, and wherein storing the second part comprises programming the second memory cells using a second number of the nominal analog values, which is greater than the first number, to assume a respective second number of the memory states.
7. The method according to claim 6, wherein the first memory cells comprise Single-Level Cells (SLC), and wherein the second memory cells comprise Multi-Level Cells (MLC).
8. The method according to claim 6, wherein the first number of the nominal analog values comprises four, and the second number of the nominal analog values comprises eight.
9. The method according to claim 6, wherein reading the first part comprises comparing first analog values stored in the first memory cells to a first set of reading thresholds, wherein reading the second part comprises comparing second analog values stored in the second memory cells to a second set of the reading thresholds, and comprising adjusting the second set of the reading thresholds responsively to the read first part.
10. The method according to claim 9, wherein storing the first part comprises encoding the first part using an Error Correction Code (ECC), wherein reading the first part comprises decoding the ECC, and wherein adjusting the second set of the reading thresholds comprises detecting errors in the read first part that were corrected by the ECC and adjusting the second set responsively to the detected corrected errors.
11. The method according to claim 1, wherein the first memory cells comprise Random Access Memory (RAM) cells.
12. The method according to claim 1, wherein the item of data comprises user data of a given type, and wherein dividing the item of the data comprises dividing the user data of the given type such that each of the first and second parts comprises a portion of the user data.
13. The method according to claim 1, wherein the first and second memory cells are arranged in respective first and second sets of memory pages, wherein dividing the item of the data comprises dividing the item into multiple fragments, assigning a number of the fragments to the first part and a remaining number of the fragments to the second part, and wherein storing the first and second parts comprises storing the number of the fragments in a subset of the first set of the memory pages and storing the remaining number of the fragments in a subset of the second set of the memory pages.
14. The method according to claim 1, wherein storing the first and second parts comprise encoding the first part of the item using a first Error Correction Code (ECC) scheme having a first decoding latency, and encoding the second part of the item using a second ECC scheme having a second decoding latency, which is greater than the first decoding latency.
15. The method according to claim 14, wherein encoding the first part comprises applying a first ECC, and wherein encoding the second part comprises applying a second ECC that is different from the first ECC.
16. The method according to claim 14, wherein the first ECC scheme has a first ECC block size, and wherein the second ECC scheme has a second ECC block size that is larger that the first block size.
17. The method according to claim 14, wherein storing the first part comprises selecting the first memory cells responsively to a level of distortion in the cells.
18. The method according to claim 17, wherein selecting the first memory cells comprises selecting the cells based on a number of previous programming and erasures cycles of the cells.
19. Apparatus for data storage, comprising:
a memory, which comprises first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency; and a processor, which is coupled to divide an item of data intended for storage in the memory into first and second parts, to store the first part in the first memory cells and the second part in the second memory cells, and, in response to a request to retrieve the item of data from the memory, to read the first part from the first memory cells and output the read first part, to read the second part from the second memory cells, and to output the read second part subsequently to outputting the first part.
20. The apparatus according to claim 19, wherein the processor is coupled to read the second part concurrently with outputting the first part.
21. The apparatus according to claim 19, wherein the first and second memory cells are formed using respective, different first and second memory device technologies.
22. The apparatus according to claim 21, wherein the first memory cells comprise NOR Flash cells and wherein the second memory cells comprise NAND Flash cells.
23. The apparatus according to claim 19, wherein the memory comprises an array of analog memory cells, and wherein the first and second memory cells comprise respective first and second groups of the memory cells in the array.
24. The apparatus according to claim 19, wherein the processor is coupled to program the first memory cells using a first number of nominal analog values to assume a respective first number of possible memory states, and to program the second memory cells using a second number of the nominal analog values, which is greater than the first number, to assume a respective second number of the memory states.
25. The apparatus according to claim 24, wherein the first memory cells comprise Single-Level Cells (SLC), and wherein the second memory cells comprise Multi-Level Cells (MLC).
26. The apparatus according to claim 24, wherein the first number of the nominal analog values comprises four, and the second number of the nominal analog values comprises eight.
27. The apparatus according to claim 24, wherein the processor is coupled to read the first part by comparing first analog values stored in the first memory cells to a first set of reading thresholds, to read the second part by comparing second analog values stored in the second memory cells to a second set of the reading thresholds, and to adjust the second set of the reading thresholds responsively to the read first part.
28. The apparatus according to claim 27, wherein the processor is coupled to encode the first part using an Error Correction Code (ECC) when storing the first part, to decode the ECC when reading the first part, to detect errors in the read first part that were corrected by the ECC, and to adjust the second set responsively to the detected corrected errors.
29. The apparatus according to claim 19, wherein the first memory cells comprise Random Access Memory (RAM) cells.
30. The apparatus according to claim 19, wherein the item of data comprises user data of a given type, and wherein the processor is coupled to divide the user data of the given type such that each of the first and second parts comprises a portion of the user data.
31. The apparatus according to claim 19, wherein the first and second memory cells are arranged in respective first and second sets of memory pages, and wherein the processor is coupled to divide the item into multiple, fragments, to assign a number of the fragments to the first part and a remaining number of the fragments to the second part, to store the number of the fragments in a subset of the first set of the memory pages and to store the remaining number of the fragments in a subset of the second set of the memory pages.
32. The apparatus according to claim 19, wherein the processor is coupled to encode the first part of the item using a first Error Correction Code (ECC) scheme having a first decoding latency, and to encode the second part of the item using a second ECC scheme having a second decoding latency, which is greater than the first decoding latency.
33. The apparatus according to claim 32, wherein the processor is coupled to encode the first part with a first ECC, and to encode the second part with a second ECC that is different from the first ECC.
34. The apparatus according to claim 32, wherein the first ECC scheme has a first ECC block size, and wherein the second ECC scheme has a second ECC block size that is larger that the first block size.
35. The apparatus according to claim 32, wherein the processor is coupled to select the first memory cells responsively to a level of distortion in the cells.
36. The apparatus according to claim 35, wherein the processor is coupled to select the cells based on a number of previous programming and erasures cycles of the cells.
an interface, which is coupled to communicate with a memory that includes first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency; and a processor, which is coupled to divide an item of data intended for storage in the memory into first and second parts, to store the first part in the first memory cells and the second part in the second memory cells, and, in response to a request to retrieve the item of data from the memory, to read the first part from the first memory cells and output the read first part, to read the second part from the second memory cells, and to output the read second part subsequently to outputting the first part.
38. A method for operating a memory that includes a plurality of analog memory cells, comprising:
storing first data in a first group of the analog memory cells by programming the cells of the first group using a first number of nominal analog values to assume a respective first number of possible memory states; storing second data in a second group of the analog memory cells by programming the cells of the second group using a second number of the nominal analog values to assume a respective second number of the possible memory states, which is greater than the first number; reading the first data by comparing first analog values stored in the cells of the first group to a first set of reading thresholds; reading the second data by comparing second analog values stored in the cells of the second group to a second set of the reading thresholds; and adjusting the second set of the reading thresholds responsively to the read first part.
39. The method according to claim 38, wherein storing the first data comprises encoding the first data using an Error Correction Code (ECC), wherein reading the first data comprises decoding the ECC, and wherein adjusting the second set of the reading thresholds comprises detecting errors in the read first data that were corrected by the ECC and adjusting the second set responsively to the detected corrected errors.
40. A method for data storage, comprising:
providing a memory comprising a plurality of memory cells, wherein each memory cell stores at least first and second bits, such that the first bits of the memory cells have a first reading latency and the second bits of the memory cells have a second reading latency, which is higher than the first reading latency; dividing an item of data intended for storage in the memory into first and second parts; storing the first part in the first bits and the second part in the second bits of the memory cells; and in response to a request to retrieve the item of data from the memory, reading the first part from the first bits and outputting the read first part, reading the second part from the second bits, and outputting the read second part subsequently to outputting the first part. Description
CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application 60/870,399, filed Dec. 17, 2006, and U.S. Provisional Patent Application 60/992,246, filed Nov. 30, 2007, whose disclosures are incorporated herein by reference.
FIELD OF THE INVENTION The present invention relates generally to memory devices, and particularly to methods and systems for reducing the latency of reading data from memory devices.
BACKGROUND OF THE INVENTION Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, such as an electrical charge or voltage, which represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some known data storage methods store certain parts of the data in single-level cells and other parts of the data in multi-level cells. Such configurations are described, for example, in U.S. Pat. Nos. 5,541,886, 6,717,847 and 7,177,184, and in U.S. Patent Application Publication 2007/061502, whose disclosures are incorporated herein by reference.
SUMMARY OF THE INVENTION Embodiments of the present invention provide a method for data storage, including:
providing a memory, which includes first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency;
dividing an item of data intended for storage in the memory into first and second parts;
storing the first part in the first memory cells and the second part in the second memory cells; and
in response to a request to retrieve the item of data from the memory, reading the first part from the first memory cells and outputting the read first part, reading the second part from the second memory cells, and outputting the read second part subsequently to outputting the first part.
In some embodiments, reading the second part includes reading the second part concurrently with outputting the first part.
In an embodiment, the first and second memory cells are formed using respective, different first and second memory device technologies. In a disclosed embodiment, the first memory cells include NOR Flash cells and the second memory cells include NAND Flash cells. In another embodiment, the memory includes an array of analog memory cells, and the first and second memory cells include respective first and second groups of the memory cells in the array.
In another embodiment, storing the first part includes programming the first memory cells using a first number of nominal analog values to assume a respective first number of possible memory states, and storing the second part includes programming the second memory cells using a second number of the nominal analog values, which is greater than the first number, to assume a respective second number of the memory states. In an embodiment, the first memory cells include Single-Level Cells (SLC), and the second memory cells include Multi-Level Cells (MLC). In another embodiment, the first number of the nominal analog values is four, and the second number of the nominal analog values is eight.
In another embodiment, reading the first part includes comparing first analog values stored in the first memory cells to a first set of reading thresholds, reading the second part includes comparing second analog values stored in the second memory cells to a second set of the reading thresholds, and the method includes adjusting the second set of the reading thresholds responsively to the read first part. In some embodiments, storing the first part includes encoding the first part using an Error Correction Code (ECC), reading the first part includes decoding the ECC, and adjusting the second set of the reading thresholds includes detecting errors in the read first part that were corrected by the ECC and adjusting the second set responsively to the detected corrected errors.
In a disclosed embodiment, the first memory cells include Random Access Memory (RAM) cells. In an embodiment, the item of data includes user data of a given type, and dividing the item of the data includes dividing the user data of the given type such that each of the first and second parts includes a portion of the user data.
In another embodiment, the first and second memory cells are arranged in respective first and second sets of memory pages, dividing the item of the data includes dividing the item into multiple fragments, assigning a number of the fragments to the first part and a remaining number of the fragments to the second part, and storing the first and second parts includes storing the number of the fragments in a subset of the first set of the memory pages and storing the remaining number of the fragments in a subset of the second set of the memory pages.
In yet another embodiment, storing the first and second parts includes encoding the first part of the item using a first Error Correction Code (ECC) scheme having a first decoding latency, and encoding the second part of the item using a second ECC scheme having a second decoding latency, which is greater than the first decoding latency. In still another embodiment, encoding the first part includes applying a first ECC, and encoding the second part includes applying a second ECC that is different from the first ECC. Additionally or alternatively, the first ECC scheme has a first ECC block size, and the second ECC scheme has a second ECC block size that is larger that the first block size.
In an embodiment, storing the first part including selecting the first memory cells responsively to a level of distortion in the cells. Selecting the first memory cells may include selecting the cells based on a number of previous programming and erasures cycles of the cells.
a memory, which includes first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency; and
a processor, which is coupled to divide an item of data intended for storage in the memory into first and second parts, to store the first part in the first memory cells and the second part in the second memory cells, and, in response to a request to retrieve the item of data from the memory, to read the first part from the first memory cells and output the read first part, to read the second part from the second memory cells, and to output the read second part subsequently to outputting the first part.
There is also provided, in accordance with an embodiment of the present invention apparatus for data storage, including:
an interface, which is coupled to communicate with a memory that includes first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency; and
There is further provided, in accordance with an embodiment of the present invention, a method for operating a memory that includes a plurality of analog memory cells, including:
storing first data in a first group of the analog memory cells by programming the cells of the first group using a first number of nominal analog values to assume a respective first number of possible memory states;
storing second data in a second group of the analog memory cells by programming the cells of the second group using a second number of the nominal analog values to assume a respective second number of the possible memory states, which is greater than the first number;
reading the first data by comparing first analog values stored in the cells of the first group to a first set of reading thresholds;
reading the second data by comparing second analog values stored in the cells of the second group to a second set of the reading thresholds; and
adjusting the second set of the reading thresholds responsively to the read first part.
There is also provided, in accordance with an embodiment of the present invention, a method for data storage, including:
providing a memory including a plurality of memory cells, wherein each memory cell stores at least first and second bits, such that the first bits of the memory cells have a first reading latency and the second bits of the memory cells have a second reading latency, which is higher than the first reading latency;
storing the first part in the first bits and the second part in the second bits of the memory cells; and
in response to a request to retrieve the item of data from the memory, reading the first part from the first bits and outputting the read first part, reading the second part from the second bits, and outputting the read second part subsequently to outputting the first part.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are block diagrams that schematically illustrate systems for data storage and retrieval, in accordance with embodiments of the present invention;
FIG. 3 is a diagram that schematically illustrates a memory, in accordance with an embodiment of the present invention;
FIG. 4 is a flow chart that schematically illustrates a method for data storage and retrieval, in accordance with an embodiment of the present invention;
FIG. 5 is a timing diagram that schematically illustrates a method for data storage and retrieval, in accordance with an embodiment of the present invention;
FIGS. 6A-6D are diagrams that schematically illustrate voltage distributions in a memory cell array, in accordance with an embodiment of the present invention; and
FIG. 7 is a flow chart that schematically illustrates a method for data storage and retrieval, in accordance with another embodiment of the present invention.
DETAILED DESCRIPTION OF EMBODIMENTS Overview Retrieving data from memory devices inevitably involves some reading latency. The reading latency is typically measured from the moment the host requests a particular data item (e.g., a file) to the moment the requested data begins to appear on the host interface. Since some memory controllers and host applications are sensitive to high reading latency values, it is desirable to reduce the reading latency to a minimum.
In principle, low reading latency can be achieved by using expensive and/or low density memory devices. For example, SLC devices typically have smaller reading latencies than MLC devices, but at the expense of higher cost per bit and lower storage density. As another example, NOR Flash devices typically have smaller reading latencies than NAND Flash cells, but are more expensive.
Embodiments of the present invention that are described hereinbelow provide improved methods and systems for storing and retrieving data, which provide both low reading latency and low device cost. In some embodiments, a memory comprises two types of memory cells, one type having lower reading latency than the other. For example, the lower-latency cells may comprise NOR Flash cells, and the higher-latency cells may comprise NAND Flash cells. As another example, an array of Flash memory cells can be partitioned so that some cells are used as SLC to serve as lower-latency cells, and other cells are used as MLC to serve as higher-latency cells. Typically, most of the memory cells comprise higher-latency lower-cost cells, and only a small portion of the total memory comprises higher-cost low-latency cells.
A processor or controller interacts with the host application and with the memory. The processor stores data items accepted from the host in the memory, and retrieves data items from the memory and sends them to the host. When storing a data item in the memory, the processor divides the data item into two parts. The processor stores the first part in the lower-latency cells, and the second part in the higher-latency cells. When retrieving the data item from the memory, the processor initially reads the first part of the data item from the lower-latency cells and sends the first part to the host. After reading the first part and concurrently with outputting the first part to the host, the processor reads the second part of the data item from the higher-latency cells.
Using this technique, the reading latency seen by the host is reduced to the latency of the lower-latency cells, even though only a relatively small portion of the total memory comprises such low-latency cells. Thus, the methods and systems described herein achieve low reading latency and low cost simultaneously.
System Description FIG. 1 is a block diagram that schematically illustrates a system 20 for data storage and retrieval, in accordance with an embodiment of the present invention. System 20 can be used in various host systems and devices, such as in computing devices, cellular phones or other communication terminals, removable memory modules (such as �disk-on-key� devices), Multi-Media Cards (MMC), systems and applications based on embedded MMC (eMMC�), Secure Digital (SD) cards, digital cameras, Solid State Drives (SSD), music and other media players such as MP3 or MP4 players, and/or any other system or device in which data is stored and retrieved.
System 20 comprises a memory device 24, which stores data in a memory cell array 28. The memory array comprises multiple analog memory cells 32. In the context of the present patent application and in the claims, the term �analog memory cell� is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. Array 28 may comprise analog memory cells of any kind, such as, for example, NAND, NOR and CTF Flash cells, PCM, NROM, FRAM, MRAM and DRAM cells. The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values.
In some embodiments, unit 60 encodes the data to be written into the memory cells using an Error Correction Code (ECC), and decodes the ECC of the retrieved data. Unit 60 may use any suitable type of ECC. ECC schemes that may be used by unit 60 may comprise, for example, various block codes such as Bose-Chaudhuri-Hocquenghem (BCH) codes, Reed-Solomon (RS) codes, Low Density Parity Check (LDPC) codes, turbo codes or a turbo product codes (TPC). Alternatively, unit 60 may use a convolutional ECC, a concatenated ECC, a trellis code or other signal-space code, or a multi-level ECC.
In particular, MSP 52 carries out methods for reducing the latency of reading data from memory cells 32 of array 28, as will be described in detail below.
Memory cells 32 of array 28 are arranged in a grid having multiple rows and columns. Each cell 32 typically comprises a floating gate Metal-Oxide Semiconductor (MOS) transistor. A certain amount of electrical charge (electrons or holes) can be stored in a particular cell by applying appropriate voltage levels to the transistor gate, source and drain. The value stored in the cell can be read by measuring the threshold voltage of the cell, which is defined as the minimal voltage that needs to be applied to the gate of the transistor in order to cause the transistor to conduct. The read threshold voltage is indicative of the charge stored in the cell.
The rows are commonly referred to as word lines and the columns are commonly referred to as bit lines of the memory array. The memory cell array is typically divided into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Pages are sometimes sub-divided into sectors. In some embodiments, each page comprises an entire row of the array. In alternative embodiments, each row (word line) can be divided into two or more pages. For example, in some SLC devices each row is divided into two pages, one comprising the odd-order cells and the other comprising the even-order cells. In a typical implementation, a two-bit-per-cell memory device may have four pages per row, a three-bit-per-cell memory device may have six pages per row, and a four-bit-per-cell memory device may have eight pages per row.
Low-Latency Storage and Retrieval When retrieving data from memory, the host processor or application inevitably encounters some reading latency. Some memory controllers and host applications are sensitive to high reading latency values, and it is therefore desirable to keep the reading latency at a minimum.
As noted above, low reading latency can be achieved by using expensive and/or low density memory devices, such as NOR Flash cells instead of NAND cells, or SLC instead of MLC. The methods and systems described herein provide both low reading latency and low device cost simultaneously by splitting the storage of each data item between two types of memory cells, one type having lower reading latency than the other. The beginning of each data item is stored in low-latency cells and the remaining part of the data item is stored in higher-latency cells. When retrieving a data item, the beginning of the data item is first read from the low-latency cells and provided as output. In parallel to preparing and outputting the beginning of the data item, the remaining part is read from the higher-latency cells.
Each Data item that is stored using the methods described herein comprises data of a given type, such as text, binary data, digital video or audio media, digital voice, or any other suitable data type. This data is often referred to as user data or payload. The data item may also comprise metadata or header information. The methods described herein do not differentiate between headers, metadata and user data of the given type when dividing the data item between the lower-latency and higher-latency cells. Thus, parts of the user data are stored in both cell types.
The description that follows refers to a processor or controller, which carries out the methods described herein. The processor may comprise an MSP, such as in the configuration of FIG. 1 above, a dedicated memory controller device, a processor of the host system, or any other suitable processor or controller.
FIG. 2 is a block diagram that schematically illustrates a system 78 for data storage and retrieval, in accordance with an embodiment of the present invention. System 78 comprises a memory 80, which comprises a fast memory 82 and a slower memory 84. Memory 84 is also referred to as a �regular latency memory.� Memory 82 comprises lower-latency memory cells, while memory 84 comprises higher-latency memory cells. Typically, the number of lower-latency cells is considerably smaller than the number of higher-latency cells. A processor 86 stores and retrieves data in and out of memories 82 and 84 of memory 80.
The terms �slow,� �fast,� �regular,� �lower-latency� and �higher-latency� refer to the latency encountered by processor 86 when retrieving data that is stored in the cells of memories 82 and 84. These terms do not imply any absolute latency figures, but are used in a relative sense to define that memory 82 has a smaller reading latency than memory 84.
In some embodiments, memory 82 and memory 84 comprise memory cells of different technologies. For example, memory 82 may comprise a NOR Flash memory and memory 84 may comprise a NAND Flash memory. Alternatively, memory 82 may comprise a SLC memory and memory 84 may comprise a MLC memory. Further alternatively, any other suitable types of memory cells can be used as lower- and higher-latency cells. Memories 82 and 84 may comprise separate packaged memory devices, or separate dies that are packaged in a single device package.
In an alternative embodiment, memory 82 and memory 84 comprise cells of the same technology (e.g., different cells in the same memory cell array), which are configured or programmed differently and thus have different reading latencies. For example, memory cells that are physically similar to one another can be operated as either SLC or MLC, as appropriate.
More generally, the reading latency of analog memory cells often depends on the number of levels used for programming the cells. In other words, dense analog memory cells that are programmed with a large number of levels usually have a high reading latency, and vice versa. The dependence of the reading latency on the number of levels is explained in detail further below. Thus, analog memory cells (in the same array or in different arrays) can be programmed using different numbers of levels to provide different latency/density trade-offs.
In some multi-level memory cells, different bits within a given cell may have different reading latencies, such as because of the different number of threshold comparison operations carried out for reading different bits. In some embodiments, the processor writes data that is intended to have low reading latency in the lower-latency bits, and data that is intended to have higher reading latency in the higher-latency bits. In some memory configurations, some memory pages are mapped to the Least Significant Bits (LSB) of the memory cells, and other memory pages are mapped to bits of higher significance. Thus, the processor can write the first part of each data item in pages that are mapped to lower-latency bits.
The methods and systems described herein are not limited to the use of non-volatile memory technologies. For example, memory 82 may comprise a Random Access Memory (RAM), such as a Static RAM (SRAM). In these embodiments, processor 86 caches the beginning of each data item in memory 82. When retrieving the data item, the beginning of the data item is read from the SRAM with small latency, and the remaining part of the data item is fetched from memory 84 in parallel.
In some embodiments, the processor encodes the data using an Error Correction Code (ECC) prior to storing it in memory 80. In these embodiments, the processor may encode the parts of the data intended to have lower and higher reading latencies using different ECC schemes having different decoding latencies. For example, the first part of each data item can be encoded with relatively small ECC blocks, thus achieving low reading latency at the expense of higher error probability. The remaining part of the data item is encoded with larger ECC blocks, thus providing better error correction capability but higher reading latency.
Alternatively, the processor may use different codes for lower-latency and higher-latency storage. For example, the processor may encode the first part of each data item with a BCH code, and the second part with LDPC.
ECC schemes having higher decoding latencies often have better error correction capabilities, and vice versa. In some embodiments, the processor stores the low-latency data in memory cells that are expected to have less distortion, so as to match the strength of the ECC scheme with the properties of the cells. Any suitable criterion can be used for selecting the lower-distortion cells.
For example, cells that have gone through a smaller number of programming and erasure cycles are expected to have less distortion. Thus, the processor may assign memory cells for storing the data encoded with the different coding schemes based on the amount of wear the cells have gone through. The processor may designate the cells whose number of previous programming and erasure cycles is lower than a certain threshold (e.g., 100 cycles) for storing the first part of each data item. For this purpose, the processor may allow only limited access to a certain area of the memory, so as to preserve a certain number of �fresh� cells throughout the lifetime of the memory device.
FIG. 3 is a diagram that schematically illustrates a memory 90, which can be used to implement memory 80 of FIG. 2 above, in accordance with an embodiment of the present invention. Memory 90 comprises K fast pages 94 (i.e., pages of lower-latency cells) and N regular pages 98 (i.e., pages of higher-latency cells). Typically, K and N are chosen so that K<<N. The fast and regular pages may reside in a single cell array or in different arrays, in the same erasure block or in different blocks, or on separate dies.
When storing a certain data item Di, such as a file, in array 90, the processor assigns this data item Ki fast pages and Ni regular pages. The number of assigned fast and/or regular pages may differ from one data item to another. Typically, the total number of fast pages is considerably smaller than the total number of regular pages when summed over the collection of files stored in memory 90, i.e.,
∑ i  K i  ∑ i  N i . FIG. 4 is a flow chart that schematically illustrates a method for data storage and retrieval, in accordance with an embodiment of the present invention. The method begins with processor 86 accepting a data item Di (e.g., a file) for storage in memory 90, at an input step 100. The processor divides the data item into fragments, at a partitioning step 104. In the present example, each fragment contains an amount of data suitable for storage in a single page of memory 90. Alternatively, fragments may correspond to sectors, erasure blocks or any other suitable group of cells.
The processor stores the first Ki fragment of the data item in Ki fast pages of memory 90, at a fast page storage step 108. The processor stores the remaining fragment of the data item in Ni regular pages of memory 90, at a regular page storage step 112.
When the host requests processor 86 to retrieve data item Di, the processor first reads the data stored in the fast pages, and then the data stored in the regular pages, at a retrieval step 116. The processor initially reads the data stored in the fast pages, prepares them for output and outputs their content to the host. This operation has low reading latency. In parallel to preparing and outputting the data read from the fast pages, the processor reads the data stored in the regular pages. The processor then prepares and outputs the data read from the regular pages to the host. Thus, the reading latency seen by the host is the reading latency of the fast pages, even though most of the data of Di is stored in regular pages.
FIG. 5 is a timing diagram that schematically illustrates a method for data storage and retrieval, in accordance with an embodiment of the present invention. The top of the figure (above the horizontal time axis) shows the timing of memory access and data output operations performed by processor 86 when using a combination of fast and regular pages, as explained above. The bottom of the figure (below the horizontal axis) shows a scheme that uses only regular pages, as a reference.
The timing scheme at the top of the figure shows the process of retrieving a data item, which is stored in two fast pages 120A and 120B and three regular pages 120C . . . 120E. When the processor is requested to retrieve this data item, it initially fetches fast page 120A from the lower-latency memory, and then prepares and outputs this page to the host as an output page 124A. The first output page appears on the host interface at a reading latency denoted T1. In parallel to preparing and outputting output page 124A, the processor fetches fast page 120B from the lower-latency memory. The processor outputs this page as an output page 124B, immediately following output page 124A.
From this stage, the processor fetches and prepares regular pages 120C . . . 120E from the higher-latency memory, and outputs them as output pages 124C . . . 124E, respectively. Thus, the host is provided with a sequence of output pages 124A . . . 124E, which begins at a reading latency T1, the reading latency of the fast pages.
The bottom of FIG. 5 demonstrates the higher latency achieved when using only regular pages. In this scheme, the processor fetches a data item, which is stored in regular pages 128A . . . 128D, and outputs the data in respective output pages 132A . . . 132D. The data begins to appear on the host interface at a reading latency of T2, which is higher than T1. Note that in some embodiments, such as when the fast pages comprise SLC and the regular pages comprise MLC, the technique described above also reduces programming latency.
Adjusting Read Thresholds of Regular Pages Using Previously-Retrieved Fast Pages FIGS. 6A-6D are diagrams that schematically illustrate voltage distributions in a memory cell array, in accordance with an embodiment of the present invention. FIGS. 6A and 6B show the voltage distributions in the higher-latency cells, while FIGS. 6C and 6D show the voltage distributions in the lower-latency cells. In the present example, the processor programs the higher-latency cells using eight possible levels, thus storing three bits per cell. The lower-latency cells are programmed using only four possible levels, thus storing two bits per cell.
Referring to FIG. 6A, data is stored in the higher-latency cells by programming the cells to eight possible levels denoted L0 . . . L7. The actual analog values (e.g., threshold voltages) of the cells vary statistically around these levels, in accordance with distributions 136A . . . 136H. Distributions 136A . . . 136H reflect the distribution of analog values immediately after the cells are programmed. Data is read from the higher-latency cells by comparing the analog values read from the cells to a set of seven reading thresholds denoted TH1 . . . TH7, which are positioned between the voltage distributions.
FIG. 6B shows the analog value distribution in the higher-latency cells, after the cells have aged, i.e., have gone through a certain retention period and/or various impairment effects (e.g., multiple programming and erasure cycles, interference from neighboring cells and/or temperature shift effects). The figure shows eight distributions 140A . . . 140H, which are typically wider than distributions 136A . . . 136H and are also shifted with respect to the nominal levels L0 . . . L7. Consequently, the optimal positions of the reading thresholds have also shifted, and are now denoted TH1′ . . . TH7′.
FIG. 6C shows the voltage distributions in the lower-latency cells, immediately after the cells are programmed. The figure shows four voltage distributions 144A . . . 144D, which correspond to the four levels used for programming these cells.
FIG. 6D shows the voltage distributions in the lower-latency cells after the cells have aged. The figure shows four distributions 148A . . . 148D, which are shifted with respect to the corresponding distributions 144A . . . 144D.
The error performance of the data retrieval process is highly sensitive to the correct positioning of the reading thresholds. As can be clearly seen in FIGS. 6A . . . 6D, the sensitivity to the positions of the reading thresholds increases sharply with the number of levels.
In some implementations, the positions of the reading thresholds are determined and possibly adjusted before data can be read successfully. When the number of levels is small, threshold adjustment may be coarse and can sometimes be omitted. When the number of levels is high, on the other hand, the reading thresholds are adjusted with high accuracy in order to successfully decode the data. The higher reading latency associated with cells having a large number of levels is partly due to the accurate threshold adjustment process that is needed for proper data retrieval.
In some embodiments of the present invention, the processor uses the decoding results of the lower-latency cells, which are decoded first, to adjust the reading thresholds of the higher-latency cells. Thus, the latency of the higher-latency cells can be reduced considerably.
FIG. 7 is a flow chart that schematically illustrates a method for data storage and retrieval, in which the decoding results of the higher-latency cells are adjusted based on the decoding results of the lower-latency cells, in accordance with an embodiment of the present invention.
The method begins with processor 86 programming the lower-latency cells using M levels, at a first programming step 150. The processor programs the higher-latency cells using N levels, N>M, at a second programming step 154. Specifically, the processor programs the lower-latency cells using a subset of the levels used for programming the higher-latency cells.
When retrieving a certain data item, the processor first retrieves and decodes the part of the data item that is stored in the low-latency cells, at a first decoding step 158. The processor decodes the data using a subset of the reading thresholds used for reading the higher-latency cells.
Referring to the example of FIGS. 6A-6D, the processor programs the higher-latency cells using eight levels and the lower-latency cells using four levels. The processor reads the data from the higher-latency cells using seven thresholds TH1 . . . TH7, and from the lower-latency cells using three thresholds TH2, TH4 and TH6.
Since the lower-latency cells are programmed with only four levels, the processor is likely to successfully decode the data from these cells, even when the reading thresholds are not set to their optimal positions. Typically, the number of errors resulting from non-optimal threshold positions is within the correction capability of the ECC.
In the higher-latency cells that are programmed with eight levels, however, the ECC may not be able to correct the errors caused by the non-optimal threshold positions. For example, in a certain implementation, an ECC having a correction capability of 16 errors per page is able to overcome �60 mV threshold deviations in the four-level cells, but only �20 mV threshold deviations in the eight-level cells.
Thus, processor 86 adjusts the reading thresholds of the higher-latency cells based on the decoding results of the low-latency cells, at a threshold adjustment step 162. This technique assumes that the impairment mechanisms, e.g., aging, are similar in the two cell types.
In some embodiments, the processor determines the desired threshold adjustment based on the errors in the low-latency cells that were corrected by the ECC. For example, the processor may adjust the reading thresholds based on a comparison between (1) the number of errors in which �1� data was corrected to �0� and (2) the number of errors in which �0� data was corrected to �1�. This comparison may indicate a non-optimal threshold position, as well as the direction and size of the desired adjustment. Alternatively, the processor may compare the number of �1� bits with the number of �0� in the decoded data. Assuming the stored data is balanced, an imbalance in the decoded data may indicate a non-optimal threshold position, and/or the direction and size of the appropriate correction.
Some aspects of threshold adjustment based on ECC results are described in PCT Application PCT/IL2007/001315, entitled �Reading Memory Cells using Multiple Thresholds,� filed Oct. 30, 2007, whose disclosure is incorporated herein by reference. Further alternatively, the processor may use any other suitable method for adjusting the reading thresholds of the higher-latency cells based on the data read from the lower-latency cells.
The processor reads the data from the high-latency cells using the adjusted reading thresholds. Since the threshold positions are improved by the adjustment process of step 162 above, the reading latency of the higher-latency cells can be reduced considerably. In some embodiments, the processor uses the adjusted thresholds as is. In an alternative embodiment, the processor carries out a short threshold adaptation process before reading the data from the higher-latency cells. The threshold adaptation process uses the adjusted thresholds produced at step 162 as initial conditions, and therefore its length is significantly reduced.
In some embodiments, the lower-latency memory cells can be programmed more accurately than the higher-latency memory cells. For example, when the cells are programmed using an iterative Program and Verify (P&V) process, as is known in the art, the lower-latency cell can be programmed using a smaller P&V step size. Programming of cells with high accuracy reduces the reading latency of these cells, as it relaxes the requirements from processes such as ECC decoding, threshold setting and interference cancellation.
Although the embodiments described herein mainly address storing data in solid-state memory devices, the principles of the present invention can also be used for storing and retrieving data in Hard Disk Drives (HDD) and other data storage media and devices. For example, the methods and systems described herein can be used in a system for accelerating file retrieval from HDDs. In such a configuration, data is stored in a system that combines a HDD (used as higher-latency memory) and a non-volatile memory device (used as lower-latency memory. Such a system would store a first part of each data item in the non-volatile memory, and a second part of the data item in the HDD. Thus, the data item can be rapidly retrieved by first reading the first part from the non-volatile memory, and reading the second part from the HDD in parallel to outputting the first part.
In some embodiments, such as in the HDD acceleration system described above, the entire data item may be stored in the higher-latency memory, in addition to storing the first part of the data item in the lower-latency memory.
R�f�renc� par Brevet citant Date de d�p�t Date de publication D�posant TitreUS818580212 f�vr. 200922 mai 2012Kabushiki Kaisha ToshibaData memory systemUS823452016 sept. 200931 juil. 2012International Business Machines CorporationWear leveling of solid state disks based on usage information of data and parity received from a raid controllerUS826115815 mars 20104 sept. 2012Fusion-Io, Inc.Apparatus, system, and method for using multi-level cell solid-state storage as single level cell solid-state storageUS82665031 juil. 201111 sept. 2012Fusion-IoApparatus, system, and method for using multi-level cell storage in a single-level cell modeUS831509227 janv. 201120 nov. 2012Fusion-Io, Inc.Apparatus, system, and method for determining a read voltage threshold for solid-state storage mediaUS838091522 juil. 201119 f�vr. 2013Fusion-Io, Inc.Apparatus, system, and method for managing solid-state storage mediaUS2009021077212 f�vr. 200920 ao�t 2009Kabushiki Kaisha ToshibaData memory systemUS2010025083622 mars 201030 sept. 2010Anobit Technologies LtdUse of Host System Resources by Memory ControllerFaire pivoterImage d'origineAccueil Google - Plan du site - T�l�chargements par lot sur l'USPTO - R�gles de confidentialit� - Conditions d'utilisation - � propos de Google�Brevets - Envoyer des commentairesDonn�es fournies par IFI CLAIMS Patent Services©2012 Google