Source: http://www.google.com/patents/US6002851?dq=5726663
Timestamp: 2014-07-13 18:50:17
Document Index: 775443793

Matched Legal Cases: ['application No. 08', 'application No. 5', 'application No. 08', 'application No. 08', 'application No. 08', 'arts              41', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08']

Patent US6002851 - Method and apparatus for node pruning a multi-processor system for maximal ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA method and apparatus for achieving maximal, full connection in a multi-processor system having a plurality of processors. Each of the multiple processors has a respective memory. The invention includes communicatively connecting the processors. Following a disruption in the communicative connection,...http://www.google.com/patents/US6002851?utm_source=gb-gplus-sharePatent US6002851 - Method and apparatus for node pruning a multi-processor system for maximal, full connection during recoveryAdvanced Patent SearchPublication numberUS6002851 APublication typeGrantApplication numberUS 08/790,030Publication dateDec 14, 1999Filing dateJan 28, 1997Priority dateJan 28, 1997Fee statusPaidAlso published asCA2275241A1, CA2279175A1, CA2279185A1, EP0954783A1, EP0954783A4, EP1012717A1, EP1012717A4, EP1012728A2, EP1012728A4, US5884018, US5991518, WO1998033120A1, WO1998033121A1, WO1998034457A2, WO1998034457A3Publication number08790030, 790030, US 6002851 A, US 6002851A, US-A-6002851, US6002851 A, US6002851AInventorsMurali Basavaiah, Karoor S. KrishnakumarOriginal AssigneeTandem Computers IncorporatedExport CitationBiBTeX, EndNote, RefManPatent Citations (7), Non-Patent Citations (8), Referenced by (40), Classifications (13), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetMethod and apparatus for node pruning a multi-processor system for maximal, full connection during recoveryUS 6002851 AAbstract A method and apparatus for achieving maximal, full connection in a multi-processor system having a plurality of processors. Each of the multiple processors has a respective memory. The invention includes communicatively connecting the processors. Following a disruption in the communicative connection, the invention collects connectivity information on one of the processors and selects certain of the processors to cease operations, based on the connectivity information collected. The invention further communicates the selection to each of the processors communicatively coupled to the one processor. The selected processors cease operations.
What is claimed is: 1. In a multi-processor system having a plurality of processors each having a respective memory, a method for achieving maximal, full connection, said method comprising:communicatively connecting said plurality of processors; collecting connectivity information on a first of said plurality of processors following a disruption in said communicative connection; ceasing to collect connectivity information on said first of said plurality of processors; and selecting on said first of said plurality of processors certain of said plurality of processors to cease operations, based on said connectivity information collected. 2. The method of claim 1 further comprising the step of:communicating said selection to each of said plurality of processors communicatively coupled to said first of said plurality of processors. 3. The method of claim 2 further comprising the step of:communicating said selection from each of said plurality of processors communicatively coupled to said first processor. 4. The method of claim 1 further comprising the step of:ceasing operations on said certain processors. 5. The method of claim 1 wherein said step of collecting comprisescollecting connectivity information on each of said plurality of processors. 6. The method of claim 1 wherein said step of ceasing to collect comprisesceasing to collect connectivity information on said first of said plurality of processors when said connectivity information indicates that said plurality of processors is fully connected. 7. The method of claim 1 wherein said step of ceasing to collect comprisesceasing to collect connectivity information on said first of said plurality of processors when a predetermined amount of time has elapsed. 8. The method of claim 1 wherein said step of selecting comprisesselecting said first of said plurality of processors as one of said certain processors to cease operations. 9. The method of claim 8 further comprising the step ofselecting another of said plurality of processors to next function as said first of said plurality of processors. 10. The method of claim 1 wherein said step of selecting comprisesrepresenting said multi-processor system as a graph; then listing all maximal, fully connected subgraphs;and then selecting one of said maximal, fully connected subgraphs. 11. The method of claim 10 wherein said step of listing compriseslisting all disconnects in said graph, based on said connectivity information collected; initializing a solution set to include said graph, fully connected and with all vertices; successively applying each of said listed disconnects to each member of said solution set. 12. The method of claim 11 wherein said step of collecting comprisescollecting connectivity information in an N�N matrix, where N is the number of said plurality of processors; andsaid steps of initializing and successively applying comprise computing a set including all dead processors among said plurality of processors; converting said matrix into canonical form. 13. The method of claim 10 wherein said step of selecting comprisesselecting the one of said maximal, fully connected subgraphs with the greatest number of vertices. 14. The method of claim 10 wherein said step of selecting comprisesselecting the largest of said maximal, fully connected subgraphs that also contains a predetermined, preferred processor. 15. The method of claim 10 wherein said step of selecting comprisesselecting one of said maximal, fully connected subgraphs based on a predetermined survival priority. 16. The method of claim 1 wherein said step of selecting comprisesrepresenting said multi-processor system as a graph; counting a count of disconnects in said graph; determining said count of disconnects as more than a predetermined number; and then selecting a fully connected subgraph on a criterion other than maximum connectivity. 17. The method of claim 16 wherein said step of determining comprisesdetermining said count of disconnects as more than 8. 18. The method of claim 1 wherein said step of collecting comprisescollecting connectivity information in an N�N matrix, where N is the number of said plurality of processors. 19. A computer system comprising:a communications network; a plurality of processors, communicatively connected by means of said communications network; each of said plurality of processors having a respective memory wherein is located a computer program for causing said computer system to achieve maximal, full connection bycollecting connectivity information on a first of said plurality of processors following a disruption in said communicative connection; ceasing to collect connectivity information on said first of said plurality of processors; and selecting on said first of said plurality of processors certain of said plurality of processors to cease operations, based on said connectivity information collected. 20. The method of claim 19 further comprising the step of:communicating said selection to each of said plurality of processors communicatively coupled to said first of said plurality of processors. 21. The method of claim 20 further comprising the step of:communicating said selection from each of said plurality of processors communicatively coupled to said first of said plurality of processors. 22. The method of claim 19 wherein said step of collecting comprisescollecting connectivity information on each of said plurality of processors. 23. An article of manufacture comprising a medium for data storage wherein is located a computer program for causing a multiprocessor system having a plurality of processors to achieve maximal, full connection bycommunicatively connecting said plurality of processors; collecting connectivity information on a first of said plurality of processors following a disruption in said communicative connection; ceasing to collect connectivity information on said first plurality of processors; and selecting on said first of said plurality of processors certain of said plurality of processors to cease operations, based on said connectivity information collected. 24. An article of manufacture comprising a medium for data storage wherein is located a computer program for causing a multiprocessor system having a plurality of processors, including a first processor, to achieve maximal, full connection bycommunicatively connecting said plurality of processors; collecting connectivity information on each of said plurality of processors following a disruption in said communicative connection; ceasing to collect connectivity information on said first processors; and selecting on said first processor certain of said plurality of processors to cease operations, based on said connectivity information collected. 25. The method of claim 24 further comprising the step of:communicating said selection to each of said plurality of processors communicatively coupled to said first processor. 26. The method of claim 25 further comprising the step of:communicating said selection from each of said plurality of processors communicatively coupled to said first processor. 27. The method of claim 24 wherein said step of selecting comprisesselecting said first processor as one of said certain processors to cease operations. 28. The method of claim 27 further comprising the step ofselecting another of said plurality of processors to next function as said first processor. Description
RELATED PATENT APPLICATIONS U.S. patent application No. 08/265,585 entitled, "Method and Apparatus for Fault-Tolerant Multi-processing System Recovery from Power Failure or Drop-outs," filed Jun. 23, 1994, naming as inventors Robert L. Jardine, Richard M. Collins and Larry D. Reeves, under an obligation of assignment to the assignee of this invention, with Attorney Docket No. 010577-031900/TA 271;
U.S. patent application No. 5,687,308, issued Nov. 11, 1997, entitled, "A Method to Improve Tolerance of Non-Homogeneous Power Outages," filed Jun. 7, 1995, naming as inventors Robert L. Jardine, Richard M. Collins and A. Richard Zacher, under an obligation of assignment to the assignee of this invention;
U.S. patent application No. 08/790269 entitled, "Method and Apparatus for Split-Brain Avoidance in a Multi-Processor System," filed on the same date as the instant application, naming as inventors Robert L. Jardine, Murali Basavaiah and Karoor S. Krishnakumar, under an obligation of assignment to the assignee of this invention;
U.S. patent application No. 08/790268 entitled, "Method and Apparatus for Toleration of Lost Timer Ticks During Recovery of a Multi-Processor System," filed on the same date as the instant application, naming as inventors Murali Basavaiah, Karoor S. Krishnakumar and Srinivasa D. Murthy, under an obligation of assignment to the assignee of this invention; and
U.S. patent application No. 08/789257 entitled, "Method and Apparatus for Distributed Agreement on Processor Membership in a Multi-Processor System," filed on the same date as the instant application, naming as inventors Robert L. Jardine, Murali Basavaiah, Karoor S. Krishnakumar, and Srinivasa D. Murthy, under an obligation of assignment to the assignee of this invention.
BACKGROUND OF THE INVENTION Distributed, shared-nothing multi-processor architectures and fault-tolerant software using process pairs require that all processors in a system have a consistent image of the processors making up the system. (The NonStop� Kernel operating system (NonStop� is a registered trademark and NonStop� Kernel is a trademark of Tandem Computers Incorporated), available from the assignee of this application is an example of such fault-tolerant software.) This consistent system image is crucial for maintaining global system tables required for system operation and for preventing data corruption caused by, say, an input/output process pair (IOP) of primary and backup processes on different processors accessing the same I/O device through dual-ported I/O controllers or a shared bus (such as SCSI).
Each processor regrouping according to the pre-existing algorithm maintains an EVENT-- HANDLER() procedure and a data structure herein termed the regroup control template #-- 700 shown in FIG. 7. A variable herein termed SEQUENCE-- NUMBER contains the current regroup sequence number.
If the sequence number in the packet is the same as the SEQUENCE-- NUMBER #-- 710, then the processor simply accepts the packet data. Accepting the data consists of logically O-Ring the KNOWN-- STAGE-- n fields in the packet with the corresponding processor variables #-- 750 to merge the two processors' knowledge into one configuration.
Stage 1 ends in either of two ways. First, all processors account for themselves. That is to say, when a processor notices that its KNOWN-- STAGE-- 1 variable #-- 750a includes all processors previously known (that is, equals the OUTER-- SCREEN #-- 730), then the processor goes to Stage 2. However, in the event of processor failure(s), the processors never all account for themselves. Therefore, Stage 1 ends on a time out. The time limit is different for cautious and non-cautious modes, but the processor proceeds to Stage 2 when that time expires--whether all processors have accounted for themselves or not.
Packets that make it past the INNER-- SCREEN and the OUTER-- SCREEN #-- 740, #-- 730 are merged into the KNOWN-- STAGE-- n variables #-- 750. When KNOWN-- STAGE-- 3 #-- 750c equals KNOWN STAGE-- 2 #-- 750b, all processors in the new configuration have completed similar cleanup and are all in Stage 3. FIG. #-- 14 summarizes conditions at the end of Stage 3.
Packets that make it past the INNER-- SCREEN and the OUTER-- SCREEN #-- 740, #-- 730 are merged into the KNOWN-- STAGE-- n variables #-- 750. When KNOWN-- STAGE-- 4 #-- 750d equals KNOWN-- STAGE-- 3 #-- 750c, all processors in the new configuration have completed similar cleanup and are all in Stage 4. FIG. 16 summarizes conditions at the end of Stage 4.
The pre-existing regroup algorithm works well for processor failures and malatose processors. There are, however, certain communications failure scenarios for which it does not work well. In understanding these scenarios, conceive of a working multi-processing system (such as a Nonstop� Kernel system) logically as a connected graph in which a vertex represents a functioning processor and an edge represents the ability for two processors to communicate directly with each other. For a system to operate normally, the graph must be fully connected, i.e., all processors can communicate directly with all other processors. A logical connection must exist between every pair of processors.
SUMMARY OF THE INVENTION Herein is disclosed a method and apparatus for achieving maximal, full connection in a multi-processor having a plurality of processors. Each of the multiple processors has a respective memory. In one embodiment, the invention includes communicatively connecting the multiple processors. Following a disruption in the communicative connection, the invention collects connectivity information on a first of the multiple processors and selects certain of the multiple processors to cease operations, based on the connectivity information collected.
The invention further communicates the selection to each of the multiple processors communicatively coupled to the first processor. The invention further communicates the selection to any processor coupled directly or indirectly to the first processor. The selected certain processors cease operations.
In preferred embodiments, the connectivity information includes an NxN matrix (where N is the number of the multiple processors) passed in possibly multiple copies among the multiple processors and becoming increasingly more accurate as a result of the passing.
The connectivity information is collected on each of the multiple processors. The collection of the connectivity information ceases on the first processor when a predetermined amount of time has elapsed.
The first processor can be selected as one of the certain processors to cease operations. If so, another of the multiple processors is selected to next function as the first processor according to the invention.
The selection of the certain processors to continue operations includes representing the multi-processor as a graph; then listing all maximal, fully connected subgraphs; and then selecting one of the maximal, fully connected subgraphs.
The listing of maximal, fully connected subgraphs includes listing all disconnects in the graph, based on the connectivity information collected; initializing a solution set to include the graph, fully connected and with all vertices; and successively applying each of the listed disconnects to each member of the solution set.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified block diagram of a multiple processing system;
DESCRIPTION OF THE PREFERRED EMBODIMENT ______________________________________TABLE OF CONTENTS______________________________________Definitions             20Overview                22Data Structures         24Protocols               25 Tie-breaker processor Selection                   25 Regroup and Split-Brain Avoidance                   26  Stage I               26  Stage II              29 Regroup and Node Pruning                   32  Stage III             38  Stage IV              39  Stages V and VI       40  Restarts              41 Regroup and Detection of Timer Failures                   42Scenarios Revisted      43WHAT IS CLAIMED IS      49______________________________________
Definitions canonical matrix: a connectivity matrix C is in canonical form if and only if:
The multi-processor systems of the invention may be constructed, using the teachings of the U.S. Pat. No. 4,817,091, issued Mar. 28, 1989 and U.S. Pat. No. 5,751,932, issued May 12, 1998 entitled "Fail-Fast, Fail-Functional, Fault-Tolerant Multiprocessor System." Therefore, U.S. Pat. Nos. 4,817,091 and 5,751,932 are incorporated herein by reference to the extent necessary.
FIG. 1 is a simplified block diagram of a multi-processor system incorporating the present invention. The processors #-- 112 are interconnected by a network #-- 114 and connections #-- 116 that provide the processors #-- 112 with inter-processor communication via transceivers #-- 117. The network #-- 114 may be implemented by a standard communications interconnect such as an Ethernet LAN or by a bus system that interconnects processors #-- 112, in parallel, and is independent from any input/output (I/O) system that the processors may have, such as is taught by U.S. Pat. No. 4,817,091, mentioned above. Alternatively, the network #-- 114 could be implemented as part of a joint I/O system that provides the processors #-- 112 not only with access to various I/O units (e.g., printers, secondary storage, and the like not shown) but also provides communication paths for inter-processor communication for the processors #-- 112. The network #-- 114 can also be any point-to-point network such as rings, fully-connected stars and trees.
In one embodiment, internal to or otherwise associated with each of the processors #-- 112 is a configuration option register #-- 119. The use of the configuration option register #-- 119 is taught in U.S. patent application No. 08/487,941 entitled, "Method to Improve Tolerance of Non-Homogeneous Power outages," naming as inventors Robert L. Jardine, Richard N. Collins and A. Richard Zacher, under an obligation of assignment to the assignee of the instant invention, with Attorney Docket No. 010577-033000/TA 272. U.S. patent application No. 08/487,941 is incorporated herein by reference.
One of the processors #-- 112 has a special role in the regroup process of the invention. This processor #-- 112 is designated the tie breaker. As described below, the split brain avoidance process favors this processor #-- 112 in case of ties. Further, the node pruning process (described below) used to ensure full connectivity between all surviving processors is run on the tie-breaker processor #-- 112. This process also favors the tie breaker in case of large numbers of connectivity failures.
At step #-- 666 each of the processors #-- 112 sends per-processor, per-redundant-path Regroup messages, containing the processor's view of the system, including its own identity, a connectivity matrix C, and the optional cautious bit. (The processors #-- 112 set and use the cautious bit according to the teachings of U.S. patent application No. 08/265,585 entitled, "Method and Apparatus for Fault-Tolerant Multi-processing System Recovery from Power Failure or Drop-Outs," filed Jun. 23, 1994, naming as inventors Robert L. Jardine, Richard M. Collins and Larry D. Reeves, under an obligation of assignment to the assignee of this invention, with Attorney Docket No. 010577-031900/TA 271. U.S. patent application No. 08/265,585 is incorporated herein by reference.) This Regroup message prompts all other processors #-- 112--if they have not already done so on noting the failure of a processor #-- 112 to send an IamAlive message--to also enter the regroup operation.
In one embodiment, the connectivity matrix in a Regroup message is an N�N bit matrix. This bit matrix is OR-ed with an N�N bit matrix that a processor #-- 112 receiving the Regroup message maintains in its memory #-- 118. Thus, for any processor i marked in any Regroup message as present, i.e., C(i,i) is set to TRUE in the Regroup message connectivity matrix, the processor #-- 112 marks that processor i as present in the memory-resident matrix, i.e., C(i,i) is set to TRUE in the memory-resident connectivity matrix.
3.2: If its group does not have the tiebreaker processor, then the processor halts itself immediately, step #-- 1850.
______________________________________groups := live-- processors;              /* groups is an array              of SET's*/numgroups := 1; /* number of elements in the           array*/______________________________________
Following is sample C code to perform this methodology. The sample code assumes a function group-- exists-- or-- is-- subset ( ) to check if a given group is a member of the current set of groups or is a subset of an existing group. It also assumes a function library that implements the set type (a type SET and functions SetMember(), SetCopy(), SetDelete() and SetSwap()).
______________________________________for (i=0; i&lt;D; i++) /* go through the disconnects*/for (j=0; j &lt; numgroups; j++)            /* go through the groups            generated so far */{/* Split group j if it has both vertices ofdisconnect i.*/if (SetMember(groups[j],disconnects[i] [0]) &amp;&amp;SetMember(groups[j],disconnects[i] [1])){/* We need to remove group j and replace itwith two new groups. This is done by modifyinggroup j in place and adding a new group at theend of *the array.*/numgroups ++;/* copy group j to the end of the array*/SetCopy(groups[j],groups[numgroups-1]);/* remove the first vertex from group j */SetDelete(groups[j], disconnects[i] [0]);/* remove the second vertex from group added atthe end of the array*/SetDelete(groups [numgroups-1], disconnects[i] [1]);/* Check if the new groups already exist or aresubgroups of existing groups.*//* First check the group added at the end.*/if (group-- exists-- or-- is-- subset(groups,   numgroups-1, groups[numgroups-1]))   numgroups--;/* Now check the updated group j. First,switch it with the last element of the array.To remove it, simply decrement the arraycount.*//* The j-th entry has been switched; it has tobe examined again */Setswap(groups[j], groups [numgroups-1]);j--;if (group-- exists-- or-- is-- subset(groups,   numgroups-1, groups[numgroups-1]))   numgroups--;}}}______________________________________
Staqes V and VI
The processor 1 applies the pruning process and determines the group of processors #-- 112 that are to survive the regroup operation. Using its memory-resident connectivity matrix C as input, the tie breaker computes the set of all dead processors, {2}, and converts its matrix C into canonical form. This conversion leaves a lxi matrix C including only the processor 1. The tie breaker computes the set of disconnects as the set {(1, 2), (2, 1)}, with D=2. However, as the set of live processors {I} does not include the processor 2, applying these disconnects to that set has no effect. The number of maximal, fully connected graphs is one, and the tie breaker sets its pruning result variable to indicate that only it will survive. The tie breaker communicates this result in its subsequent Regroup messages and thus passes through Stages III and IV. The system #-- 500 completes the regroup operation and continues operations with only the processor 1 running.
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19, 2001Jun 27, 2002Legato Sys IncMethod of 'split-brain' prevention in computer cluster systems* Cited by examinerClassifications U.S. Classification714/4.5, 714/E11.016, 712/15, 709/221, 714/E11.007International ClassificationG06F11/00, G06F13/00, G06F11/20, G06F11/14Cooperative ClassificationG06F11/0757, G06F11/142, G06F11/0724European ClassificationG06F11/14A8CLegal EventsDateCodeEventDescriptionMay 31, 2011FPAYFee paymentYear of fee payment: 12Apr 26, 2011ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;HEWLETT-PACKARD COMPANY;REEL/FRAME:026198/0139Effective date: 20101019Jun 14, 2007FPAYFee paymentYear of fee payment: 8Mar 16, 2004ASAssignmentOwner name: COMPAQ COMPUTER CORPORATION, A DELAWARE CORPORATIOFree format text: MERGER;ASSIGNOR:TANDEM COMPUTERS INCORPORATED;REEL/FRAME:014506/0598Effective date: 19981231Owner name: COMPAQ INFORMATION TECHNOLOGIES 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