Source: http://www.google.com/patents/US8009454?dq=U.S.+Patent+%23+5,723,324
Timestamp: 2015-06-03 17:01:23
Document Index: 246092338

Matched Legal Cases: ['Application No. 10', 'Application No. 2006101701004', 'Application No. 20061017100', 'Application No. 20061017100', 'Application No. 2007', 'Application No. 20061017100', 'Application No. 20061017100']

Patent US8009454 - Resistance random access memory device and a method of manufacturing the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsProvided is a resistance random access memory (RRAM) device and a method of manufacturing the same. A resistance random access memory (RRAM) device may include a lower electrode, a first oxide layer on the lower electrode and storing information using two resistance states, a current control layer made...http://www.google.com/patents/US8009454?utm_source=gb-gplus-sharePatent US8009454 - Resistance random access memory device and a method of manufacturing the sameAdvanced Patent SearchPublication numberUS8009454 B2Publication typeGrantApplication numberUS 11/654,003Publication dateAug 30, 2011Filing dateJan 17, 2007Priority dateMar 10, 2006Fee statusPaidAlso published asCN101034732A, CN101034732B, US20070215977Publication number11654003, 654003, US 8009454 B2, US 8009454B2, US-B2-8009454, US8009454 B2, US8009454B2InventorsMyoung-Jae Lee, Yoon-dong Park, Hyun-sang Hwang, Dong-Soo LeeOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (23), Non-Patent Citations (7), Referenced by (7), Classifications (18), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetResistance random access memory device and a method of manufacturing the same
US 8009454 B2Abstract
Provided is a resistance random access memory (RRAM) device and a method of manufacturing the same. A resistance random access memory (RRAM) device may include a lower electrode, a first oxide layer on the lower electrode and storing information using two resistance states, a current control layer made of a second oxide on the first oxide layer and an upper electrode on the current control layer.
1. A RRAM (resistance random access memory device) device comprising:
a first oxide layer on the lower electrode and storing information using two resistance states, wherein the first oxide layer is made of one selected from the group consisting of NiOx, ZrOx, Nb2O5-x, HfO, ZnO, WO3, CoO, CuO2, and TiO2;
a current control layer made of a second oxide on the first oxide layer; and
an upper electrode on the current control layer,
wherein the current control layer has a resistance within a range between about 10 ohm and about 10 kohm, and
wherein the first oxide layer directly contacts the lower electrode, and the current control layer directly contacts the upper electrode.
2. The RRAM device of claim 1, wherein the current control layer is made of one of ZnOx and RuOx which are doped with transition metals.
3. The RRAM device of claim 1, wherein the current control layer is made of a transition metal oxide.
4. The RRAM device of claim 1, wherein the current control layer is made of one of ZnO and RuOx which are doped with one of Al and In.
5. The RRAM device of claim 1, wherein the current control layer is made of one of SiO2 and Zr-rich ZrO2 which are doped with metals.
6. A method of manufacturing a RRAM (resistance random access memory device) device comprising:
forming a first oxide layer on the lower electrode and storing information using two resistance states, wherein the first oxide layer is made of one selected from the group consisting of NiOx, ZrOx, Nb2O5-x, HfO, ZnO, WO3, CoO, CuO2, and TiO2;
forming a current control layer made of a second oxide on the first oxide layer; and
forming an upper electrode on the current control layer,
wherein the first oxide layer directly contacts the lower electode, and the current control layer directly contacts the upper electrode.
7. The method of claim 6, wherein the current control layer is made of one of ZnOx and RuOx which are doped with transition metals.
8. The method of claim 6, wherein the current control layer is made of a transition metal oxide.
9. The method of claim 6, wherein the current control layer is made of one of ZnO and RuOx which are doped with one of Al and In.
10. The method of claim 6, wherein the current control layer is made of one of SiO2 and Zr-rich ZrO2 which are doped with metals. Description
This application claims priority under 35 USC �119 to Korean Patent Application No. 10-2006-0022728, filed on Mar. 10, 2006, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.
Example embodiments relate to a resistance memory device and a method of manufacturing the same. Other example embodiments relate to a resistance random access memory (RRAM) device driven at a lower power and a method of manufacturing the same.
RRAMs mainly use characteristics (resistance change characteristics) by which resistance values vary with voltages of transition metal oxides and include central oxide layers and upper and lower electrodes. Referring to FIG. 1A, a memory device 10 may include a lower electrode 11, an oxide layer 12, and an upper electrode 13 sequentially stacked. The oxide layer 12 may operate as a memory node and may be made of a metal oxide having a variable resistance characteristic, for example, ZnO, TiO2, Nb2O5, ZrO2 and/or NiOx.
A RRAM using NiOx, ZrOx and/or Nb2O5-x may be a volatile memory having a higher switching endurance characteristic, retention characteristic, and other similar characteristics. Various materials for the RRAM have been studied. FIG. 1B is a graph illustrating a current-voltage characteristic of a conventional resistance memory device using NiOx as a memory node. As shown in FIG. 1B, a current of about 3 mA or more may be required to operate the conventional resistance memory device. In other words, the conventional resistance memory device may operate at a voltage and current having predetermined or given values and/or values higher than the predetermined or given values. The current may be lowered and if this occurs, the conventional resistance memory device may consume a smaller amount of power. Accordingly, there may be a need for lower power consumption of resistance memory devices, as is true for other types of memory devices.
Example embodiments provide a lower power resistance random access memory (RRAM) device and a method of manufacturing the same.
According to example embodiments, a RRAM (resistance random access memory device) device may include a lower electrode, a first oxide layer on the lower electrode and storing information using two resistance states, a current control layer made of a second oxide on the first oxide layer and an upper electrode stacked on the current control layer.
According to example embodiments, a method of manufacturing a RRAM (resistance random access memory device) device may include providing a lower electrode, forming a first oxide layer on the lower electrode and storing information using two resistance states, forming a current control layer made of a second oxide on the first oxide layer and forming an upper electrode on the current control layer.
The first oxide layer may be made of one selected from the group consisting of NiOx, ZrOx, Nb2O5-x, HfO, ZnO, WO3, CoO, CuO2, and TiO2. The current control layer may be made of one of ZnOx and RuOx doped with transition metals or a transition metal oxide. The current control layer may be made of one of ZnO and RuOx doped with one of Al and In or one of SiO2 and Zr-rich ZrO2 doped with metals. The current control layer may have a resistance within a range of between about 10 ohm and about 10 k ohm.
FIG. 1A is a diagram of a conventional resistance random access memory (RRAM) device;
FIG. 1B is a graph illustrating a current-voltage characteristic of a conventional RRAM device;
FIG. 2A is a diagram of a RRAM device according to example embodiments;
FIG. 2B is an electrical equivalent circuit diagram of the RRAM device shown in FIG. 2A;
FIG. 2C is a graph illustrating current-voltage characteristics of RRAM devices according to example embodiments;
FIG. 3 is a graph illustrating a current-voltage characteristic of a RRAM according to example embodiments; and
FIG. 4 is a graph illustrating switching cycles of a RRAM device of example embodiments and a conventional RRAM device with respect to variations in resistances in higher and lower resistance states.
Hereinafter, a RRAM device according to example embodiments will be described in detail with reference to the attached drawings. In the drawings, the thicknesses and widths of layers are exaggerated for clarity. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art.
FIG. 2A is a diagram of a RRAM device 20 according to example embodiments. Referring to FIG. 2A, the RRAM device 20 may include a lower electrode 21, a first oxide layer 22, a current control layer 23 and an upper electrode 24. The first oxide layer 22 may have a variable resistance characteristic and may be a memory node made of a transition metal oxide having two resistance states. The transition metal oxide may be NiOx, ZrOx, Nb2O5-x, HfO, ZnO, WO3, CoO, CuO2 and/or TiO2. In example embodiments, the first oxide layer 22 may be made of NiOx, ZrOx, Nb2O5-x, HfO, ZnO, WO3, CoO, CuO2 and/or TiO2.
As a characteristic of example embodiments, the current control layer 23 may be made of a second oxide on the first oxide layer 22. The current control layer 23 may be made of a metal oxide. According to example embodiments, the current control layer 23 may be made of ZnOx and/or RuOx doped with In, Al and/or a transition metal. According to example embodiments, the current control layer 23 may be made of SiO2 and/or Zr-rich ZrO2 doped with a metal. The current control layer 23 may have a resistance within a range of between about 10 ohm and about 10 k ohm. The lower electrode 21 and/or the upper electrode 24 may be made of a metal and/or a metal oxide having electrical conductivity. For example, the lower and/or upper electrode 21 or 24 may be made of Ir, Ru, Pt and/or an oxide of Ir, Ru, or Pt.
The current control layer 23 may have a resistance within the range of between about 10 ohm and about 10 kohm. The RRAM device 20 according to example embodiments may have an equivalent circuit as shown in FIG. 2B. Referring to FIG. 2B, RTE, RR, RNiO, and RBE may denote resistances of the upper electrode 24, the current control layer 23, the first oxide layer 22, and the lower electrode 21, respectively. The resistances RTE, RR, RNiO, and RBE may be connected to one another in series, and 1-bit information may be stored according to a state of the resistance RNiO of the first oxide layer 22.
FIG. 2C is a graph illustrating a current-voltage characteristic with respect to variations (about 1, 10, 56, 120, 220, and 300 ohm) in resistance of a current control layer when a first oxide layer may be made of NiO and the current control layer may be made of ZnO doped with Al in a RRAM device according to example embodiments. As shown in FIG. 2C, current may decrease with an increase in the resistance of the current control layer when in a lower resistance state. Current may not flow regardless of the resistance when in a higher resistance state.
FIG. 3 is a graph illustrating a current-voltage characteristic of a RRAM device, according to example embodiments, as the measurement result of a switching operation after a ZnO layer doped with Al may be deposited on a NiO layer to a thickness of about 15 nm. As shown in FIG. 3, switching may occur at a peak current of about 100 A or less. The peak current may be adjusted through an optimization process.
FIG. 4 is a graph illustrating switching cycles of a RRAM device of example embodiments and a conventional RRAM device with respect to variations in resistances in higher and lower resistance states. As shown in FIG. 4, an on current may be reduced at least about 100 times or more according to the result of a comparison of a resistance value measured when an existing NiO RRAM may be turned on and/or off and a resistance value measured when a ZnO layer doped with Al used for controlling a current may be deposited on the NiO.
According to example embodiments, a higher on-current (peak current>about 3 mA) of a thin film made of NiO, ZrOx and/or Nb2O5-x for realizing two resistance states may be lowered to about 100 μA in a RRAM which is being developed as memory technology. A lower power memory device may be realized to solve the problem of higher power consumption in a conventional resistance memory device. A doped oxide thin film having a specific resistance value between specific resistance values of an oxide and an insulator may contribute to reducing a higher on-current of a conventional memory device having a RRAM thin film made of NiO, ZrOx and/or Nb2O5-x at least about 100 times or more. An on-current may be substantially lowered to hundreds of μA so as to realize a lower power memory device.
A process of fabricating a RRAM device according to example embodiments may be a generally known semiconductor process of fabricating a general DRAM. Although an existing RRAM device made of NiOx, ZrOx and/or Nb2O5-x has a higher switching endurance characteristic, a higher retention characteristic, a higher operation voltage, and other similar characteristics, the existing RRAM device may not be realized as a lower power device due to a higher on-current (peak current>about 3 mA). A doped oxide layer for controlling a current may be made on a RRAM material to realize a lower power memory device.
A higher on-current of a RRAM thin film made of NiO, ZrOx and/or Nb2O5-x may be reduced at least about 100 times or more using a doped oxide layer having a specific resistance value between specific resistance values of an oxide and an insulator. The on-current may be reduced to several hundreds of μA. Example embodiments may be applied to a RRAM device using an oxide having two resistance states.
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capacitor and method for making the sameUS8908415Mar 1, 2013Dec 9, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Resistive memory resetUS8952347Mar 8, 2013Feb 10, 2015Taiwan Semiconductor Manfacturing Company, Ltd.Resistive memory cell array with top electrode bit lineUS8963114Mar 6, 2013Feb 24, 2015Taiwan Semiconductor Manufacturing Company, Ltd.One transistor and one resistive (1T1R) random access memory (RRAM) structure with dual spacersUS9019743Nov 29, 2012Apr 28, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Method and structure for resistive switching random access memory with high reliable and high densityUS20130336041 *Sep 21, 2012Dec 19, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Structure and Method for a Forming Free Resistive Random Access Memory with Multi-Level Cell* Cited by examinerClassifications U.S. Classification365/148, 257/4, 257/5, 257/E27.104, 355/46, 257/E29.17International ClassificationG11C11/00Cooperative ClassificationG11C13/0007, G11C2213/56, H01L45/04, H01L45/1233, G11C2213/32, H01L45/146, G11C11/5685, H01L45/12European ClassificationG11C13/00R3, G11C11/56Q, H01L45/14CLegal EventsDateCodeEventDescriptionJan 28, 2015FPAYFee paymentYear of fee payment: 4Jan 17, 2007ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, MYOUNG-JAE;PARK, YOON-DONG;HWANG, HYUN-SANG;AND OTHERS;REEL/FRAME:018808/0248Effective date: 20070116RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services