Source: http://www.google.com/patents/US6236194?dq=6263352
Timestamp: 2017-04-29 05:06:43
Document Index: 767017804

Matched Legal Cases: ['art 29', 'art 29', 'art 29', 'art 29', 'art 29', 'art 29', 'art 29', 'art 29', 'art 29', 'art 29']

Patent US6236194 - Constant voltage power supply with normal and standby modes - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA first constant voltage circuit includes an operational amplifier having a reference voltage applied to a first input terminal thereof and a voltage obtained as a result of an output voltage being divided applied to a second input terminal thereof, and controls an output transistor with an output of...http://www.google.com/patents/US6236194?utm_source=gb-gplus-sharePatent US6236194 - Constant voltage power supply with normal and standby modesAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6236194 B1Publication typeGrantApplication numberUS 09/633,148Publication dateMay 22, 2001Filing dateAug 4, 2000Priority dateAug 6, 1999Fee statusPaidAlso published asUSRE39374Publication number09633148, 633148, US 6236194 B1, US 6236194B1, US-B1-6236194, US6236194 B1, US6236194B1InventorsShinya Manabe, Kohji YoshiiOriginal AssigneeRicoh Company, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (3), Referenced by (97), Classifications (10), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetConstant voltage power supply with normal and standby modes
The output terminals 15 a and 15 b of the high-speed VR 5 a and low-speed VR 5 b are connected to the load 3 through a switching unit 17. The load 3 has an active mode in which the power consumption is tens of mA and a sleep mode in which the power consumption is tens of μA switched to one another. A switching logic circuit (switching LOGIC) 19 which outputs switching signals to the switching unit 17 is connected to the load 3. The switching logic circuit 19 outputs to the switching unit 17 a switching signal “H” when the load 3 is in the active mode but a switching signal “L” when the load 3 is in the sleep mode. The switching unit 17 connects the output terminal 15 a of the high-speed VR 5 a to the load 3 when having the switching signal “H” input thereto, but connects the output terminal 15 b of the low-speed VR 5 b to the load 3 when having the switching signal “L” input thereto. Thus, the high-speed VR 5 a or low-speed VR 5 b is selected in accordance with the condition of the load 3.
The operational amplifier 33 b has current consumption smaller than that of the operational amplifier 33 a, and the low-speed voltage stabilizing part 29 b has the PSRR and load transient responsivity interior to those of the high-speed voltage stabilizing part 29 a. A switching logic circuit (switching LOGIC) 39 outputting switching signals to the switching units 37 a and 37 b is connected to the load 3. The switching units 37 a and 37 b control connection/disconnection between the output terminals of the operational amplifiers 33 a and 33 b, and the gate electrode of the output transistor 25. Each of the units 37 a and 37 b makes the connection when having a switching signal “H” input thereto but the disconnection when having a switching signal “L” input thereto. The switching logic circuit 39 is also connected to the interrupting circuit 35 a and 35 b, and controls the operations of the interrupting circuits 35 a and 35 b correspondingly to the signals input to the switching units 37 a and 37 b. The VR 21 enclosed by a broken line is formed on one chip.
When the load 3 is in the active mode (operation condition), the switching logic circuit 39 outputs the switching signal “H” to the switching unit 37 a and interrupting circuit 35 a, while outputs the switching signal “L” to the switching unit 37 b and interrupting circuit 35 b. Thereby, the connections are made by the switching unit 37 a and interrupting circuit 35 a, and, thereby, the high-speed voltage stabilizing part 29 a is turned on, while the disconnections are made by the switching unit 37 b and interrupting circuit 35 b, and, thereby, the low-speed voltage stabilizing part 29 b is turned off (standby condition). Thereby, the voltage applied to the gate electrode of the output transistor 25 is controlled by the high-speed voltage stabilizing part 29 a. The current consumption of the low-speed voltage stabilizing part 29 b in the standby condition is equal to or smaller than 1 μA.
When the load 3 is in the sleep mode (standby condition), the switching logic circuit 39 outputs the switching signal “L” to the switching unit 37 a and interrupting circuit 35 a, while outputs the switching signal “H” to the switching unit 37 b and interrupting circuit 35 b. Thereby, the disconnections are made by the switching unit 37 a and interrupting circuit 35 a, and, thereby, the high-speed voltage stabilizing part 29 a is turned off (standby condition), while the connections are made by the switching unit 37 b and interrupting circuit 35 b, and, thereby, the low-speed voltage stabilizing part 29 b is turned on. Thereby, the voltage applied to the gate electrode of the output transistor 25 is controlled by the low-speed voltage stabilizing part 29 b. The current consumption of the high-speed voltage stabilizing part 29 a in the standby condition is equal to or smaller than 1 μA.
A switching logic circuit (switching LOGIC) 55 outputting switching signals to the switching circuit 53 is connected to the load 3. The switching circuit 53, based on the switching signal input to a control input terminal CTR1 from the switching logic circuit 55, turns the switch SW1 to the bias-voltage applying terminal (BIAS) when the signal input to the terminal CTR1 is “H” (in a high level) but to the ground when the signal input to the terminal CTR1 is “L” (in a low level). Similarly, The switching circuit 53, based on the switching signal input to a control input terminal CTR2 from the switching logic circuit 55, turns the switch SW2 to the bias-voltage applying terminal (BIAS) when the signal input to the terminal CTR2 is “H” (in the high level) but to the ground when the signal input to the terminal CTR2 is “L” (in the low level). Thus, the voltages applied to the gate electrodes of the NMOS transistors NCH5 and NCH6 are controlled. Thereby, one of the NMOS transistors NCH5 and NCH6 is selected, and, thereby, the bias current flowing though the operation amplifier 49 can be switched.
When the load 3 is in the active mode, the switching signal “H” is output to the terminal CTR1 and the switching signal “L” is output to the terminal CTR2. Thereby, the gate of the NMOS transistor NCH5 is connected to the bias-voltage applying terminal (BIAS) and is turned on, while the gate of the NMOS transistor NCH6 is connected to the ground and is turned off. As mentioned above, the NMOS transistors NCH5 and NCH6 have different current capacities, and the current iH flowing through the NMOS transistor NCH5 is larger than the current iL flowing through the NMOS transistor NCH6. Accordingly, a larger bias current flows through the operational amplifier 49, and, thereby, the operational amplifier 49 operates with increased (higher or superior) PSRR and load transient responsivity.
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