Source: http://www.google.com/patents/US7484093?dq=6985872
Timestamp: 2013-12-08 20:09:39
Document Index: 598944905

Matched Legal Cases: ['art 20', 'art 20', 'art 22', 'art 23', 'art 22', 'art 23', 'art 24', 'art 24', 'art 21', 'art 21', 'art 20', 'art 22', 'art 23', 'art 21', 'art 21']

Patent US7484093 - Information processor and information processing method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsAn information processor including a processing device for recording information on a recording medium or reproducing the information recorded on the recording medium, is provided with: an encrypting/decrypting device which is capable of an encrypting operation for encrypting the information to be recorded...http://www.google.com/patents/US7484093?utm_source=gb-gplus-sharePatent US7484093 - Information processor and information processing methodPublication numberUS7484093 B2Publication typeGrantApplication numberUS 10/840,257Publication dateJan 27, 2009Filing dateMay 7, 2004Priority dateMay 9, 2003Fee statusLapsedAlso published asCN1551193A, EP1480212A2, EP1480212A3, US20040223613Publication number10840257, 840257, US 7484093 B2, US 7484093B2, US-B2-7484093, US7484093 B2, US7484093B2InventorsKoichiro Kakutani, Yuji Matsumoto, Yasuyuki Umehara, Takashi Irisawa, Takeshi Nonaka, Yukiyoshi Haraguchi, Kyoko Oishi, Shinya Sasatani, Hayato Watanabe, Yuji ShimizuOriginal AssigneePioneer CorporationPatent Citations (2), Non-Patent Citations (3), Classifications (13), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetInformation processor and information processing methodUS 7484093 B2Abstract An information processor including a processing device for recording information on a recording medium or reproducing the information recorded on the recording medium, is provided with: an encrypting/decrypting device which is capable of an encrypting operation for encrypting the information to be recorded when the information is recorded on the recording medium and a decrypting operation for decrypting the information to be reproduced from the recording medium when the information is reproduced from the recording medium; the processing device which includes the two or more encrypting/decrypting devices; a control device which controls the encrypting/decrypting device so as to perform one of the encrypting operation and the decrypting operation; and a switching device which switches a transmission path of the information to the encrypting/decrypting device in response to one of the operations performed by the encrypting/decrypting device.
SUMMARY OF THE INVENTION The present invention is devised in view of the above-described inconveniences. For example, an object of the present invention is to provide an information processor, an information processing method, an information processing program, and an information recording medium for recording the information processing program whereby miniaturization/low cost is achieved by reducing the overall circuit size as compared with the case where encryption and decrypting are carried out by separate circuits or devices, and high-speed information processing is also achieved.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the schematic configuration of an information processor according to an embodiment;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in accordance with accompanying drawings. In the embodiments described below, the present invention is applied to an information processor is provided with both of an optical pickup which records or reproduces information on a recordable optical disc such as a CD (Compact Disc) or a DVD (Digital Versatile Disc) and a magnetic head which records or reproduces information on a recordable magnetic disc such as a hard disc.
First when the processing section 5 is used to encrypt the processing section information S11 and generate the processing section information S1, the operation part 20 generates encryption information Sp (which is equivalent to the information L of FIG. 2A and temporarily has a value of �L�) for encrypting the processing section information S11 according to predetermined processing, and the operation part 20 outputs the information to the reversing part 22 and one of the input terminals of the first selecting part 23.
Then, the reversing part 22 reverses the sign of the inputted encryption information Sp to generate inverse encryption information Spi (having a value of �−L�) and outputs the information to the other input terminal of the first selecting part 23.
Based on the control information outputted from the CPU 12 via the bus B, the second selecting part 24 selects the terminal having been fed with the processing section information S11 when the processing section information S11 is encrypted, and the second selecting part 24 outputs the processing section information S11 (which is equivalent to the information K of FIG. 2A and temporarily has a value of �K�) as selection information Ss2 to the second operation part 21.
With these operations, the second operation part 21 performs predetermined encryption/decrypting operations (e.g. an addition (L+K)) by using information included in the selection information Ss1 (in this case, the encryption information Sp (having a value of �L�)) and information included in the selection information Ss2 (in this case, the processing section information S11 (having a value of �K�)) generates the encrypted processing section information S1 as a result, and outputs the information to the interface 2.
Subsequently when the processing section 5 is used to decrypte the processing section information S1 (which is equivalent to the information M of FIG. 2A and temporarily has a value of �M�) and generate the processing section information S11, the first operation part 20 generates the encryption information Sp as in the encryption of the processing section information S11, and outputs the information Sp to the reversing part 22 and one of the input terminals of the first selecting part 23.
With these operations, the second operation part 21 performs encryption/decrypting operations (e.g. a subtraction (M−L)) as in the encryption of the processing section information S11, by using information included in the selection information Ss1 (in this case, the inverse encryption information Spi (having a value of �−L�)) and information included in the selection information Ss2 (in this case, the processing section information S1 (having a value of �M�)), and the second operation part 21 generates the encrypted processing section information S11 as a result and outputs the information to the path switching section 9.
(I) Embodiment 1 of the Switching Operation Referring to FIGS. 3 and 4, Embodiment 1 of the switching operation will be discussed first.
(II) Embodiment 2 of the Switching Operation Referring to FIGS. 5 and 6, Embodiment 2 of the switching operation will be discussed below.
(III) Embodiment 3 of the Switching Operation Referring to FIGS. 7 and 8, Embodiment 3 of the switching operation will be discussed below.
(IV) Embodiment 4 of the Switching Operation Referring to FIGS. 9 and 10, Embodiment 4 of the switching operation will be discussed below.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6408074Oct 22, 1998Jun 18, 2002Lucent Technologies Inc.Hardware architecture for a configurable cipher deviceUS20020064370Jun 14, 2001May 30, 2002John BerkheimerDual deck multimedia deviceNon-Patent CitationsReference1 *Copyright protection for the electronic distribution of text documents Brassil, J.T.; Low, S.; Maxemchuk, N.F.; Proceedings of the IEEE vol. 87, Issue 7, Jul. 1999 pp. 1181-1196.2 *Novel types of analogic CNN algorithms for recognizing bank-notes Zarandy, A.; Werblin, F.; Roska, T.; Chua, L.O.; CNNA-94, Proceedings of the Third IEEE International Workshop on Cellular Neural Networks and their Applications Dec. 18-21, 1994 pp. 273-278.3 *Toward zero-effort perosnal document management Hull, J.J.; Hart, P.E.; Computer vol. 34, Issue 3, Mar. 2001 pp. 30-35.* Cited by examinerClassifications U.S. Classification713/165, 713/150, 713/164International ClassificationG06F12/14, H04L9/00, H04L9/10, G11B20/10, G11B20/00, G06F21/24Cooperative ClassificationG11B20/00086, G11B20/0021European ClassificationG11B20/00P5, G11B20/00PLegal EventsDateCodeEventDescriptionMar 19, 2013FPExpired due to failure to pay maintenance feeEffective date: 20130127Jan 27, 2013LAPSLapse for failure to pay maintenance feesSep 10, 2012REMIMaintenance fee reminder mailedMay 7, 2004ASAssignmentOwner name: PIONEER CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KAKUTANI, KOICHIRO;MATSUMOTO, YUJI;UMEHARA, YASUYUKI;ANDOTHERS;REEL/FRAME:015307/0136;SIGNING DATES FROM 20040407 TO 20040413RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google