Source: http://www.google.com/patents/US6218318?ie=ISO-8859-1
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Patent US6218318 - Semiconductor device having a porous insulation film - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor device includes a porous interlayer insulation film including therein a stacking of SiO2 particles having a diameter in the range between about 5 nm and about 50 nm and stacked so as to form a void between adjacent particles, wherein the interlayer insulation film has a porosity in the...http://www.google.com/patents/US6218318?utm_source=gb-gplus-sharePatent US6218318 - Semiconductor device having a porous insulation filmAdvanced Patent SearchPublication numberUS6218318 B1Publication typeGrantApplication numberUS 09/018,855Publication dateApr 17, 2001Filing dateFeb 4, 1998Priority dateFeb 5, 1997Fee statusPaidPublication number018855, 09018855, US 6218318 B1, US 6218318B1, US-B1-6218318, US6218318 B1, US6218318B1InventorsYoshiyuki Ohkura, Hideki HaradaOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (17), Non-Patent Citations (3), Referenced by (60), Classifications (50), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device having a porous insulation film
US 6218318 B1Abstract
What is claimed is: 1. A method of fabricating a semiconductor device having a multilayer interconnection structure including an interlayer insulation film, comprising the steps of:
applying a film-forming liquid on an underlying structure, said film-forming liquid including therein SiO2 particles and a binder; and heating said underlying structure applied with said film-forming liquid to form an insulation film thereon as said interlayer insulation film, such that said insulation film includes said SiO2 particles and voids formed between said SiO2 particles, wherein said SiO2 particles have a diameter in the range between about 5 nm and about 50 nm, and wherein said step of heating is conducted at a temperature in the range between about 350� C. and about 400� C., in an inert gas atmosphere containing oxygen with a concentration of 1% or less. 2. A method of fabricating a semiconductor device having a multilayer interconnection structure containing an interlayer insulation film, comprising the steps of:
forming an insulation film above a semiconductor structure as a part of said interlayer insulation film; and forming a CVD insulation film on said insulation film in contact with said insulation film as a part of said interlayer insulation film; said step of forming said insulation film including the steps of: applying a film-forming liquid above said semiconductor structure, said film-forming liquid containing therein SiO2 particles and a binder, each of said SiO2 particles being substantially a filled particle; and heating said semiconductor structure applied with said film-forming liquid to form an insulation film thereon such that said insulation film includes said SiO2 particles and a void is formed between said SiO2 particles. 3. A method as claimed in claim 2, wherein said step of heating is conducted at a temperature of about 350� C.-about 400� C.
5. A method as claimed in claim 2, wherein said step of forming said CVD insulation film includes a step of forming an SiO2 film by a CVD process using SiH4 and N2O as source materials.
forming a first insulation film above an underlying semiconductor structure; forming a first CVD film on said first insulation film by a CVD process, said first insulation film being in intimate contact with said first CVD film; forming a first opening in said first CVD film; forming a second insulation film on said first CVD film; forming a second CVD film on said second insulation film in intimate contact with said second insulation film; forming a second opening in said second CVD film in correspondence to said first opening, such that said second opening has a size larger than said first opening; forming a groove in said second insulation film in correspondence to said second opening, by applying a dry etching process acting selectively to said second insulation film through said second opening, such that said groove penetrates through said second insulation film; forming a through-hole in said first insulation film in correspondence to said first opening, by applying a dry etching process acting selectively to said first insulation film through said groove and through said first opening; and filling said groove and said through-hole by a conductor pattern; wherein said first insulation film is formed by: applying a film-forming liquid containing therein SiO2 particles having a diameter in the range between about 5nm and about 50 nm and a binder, above said semiconductor structure; and heating said semiconductor structure applied with said film-forming liquid to form said first insulation film such that said first insulation film includes a void therein between said SiO2 particles; and wherein said second insulation film is formed by: applying a film-forming liquid containing therein SiO2 particles having a diameter in the range between about 5 nm and about 50 nm and a binder, on said first CVD film; and heating said first CVD film applied with said film-forming liquid to form said second insulation film such that said second insulation film includes a void therein between said SiO2 particles; said step of forming said through-hole in said first insulation film being conducted continuously to said step of forming said groove in said second insulation film. 7. A method of fabricating a semiconductor device, comprising the steps of:
forming a first interlayer insulation film on an underlying semiconductor structure; forming a first CVD film on said first interlayer insulation film by a CVD process; forming a second interlayer insulation film on said first CVD film; forming a second CVD film on said second interlayer insulation film; forming an opening consecutively through said second CVD film, said second interlayer insulation film, said first CVD film and said first interlayer insulation film; and forming a groove in said second CVD film and said second interlayer insulation film in correspondence to said opening, by applying a dry etching process to said second interlayer insulation film while using said first CVD film as an etching stopper, such that said groove penetrates through said second interlayer insulation film, wherein said first interlayer insulation film is formed by: applying a film-forming liquid containing therein SiO2 particles having a diameter in the range between about 5 nm and about 50 nm and a binder, on said semiconductor structure; and heating said semiconductor structure applied with said film-forming liquid to form said first interlayer insulation film such that said first interlayer insulation film includes a void therein between said SiO2 particles; and wherein said second interlayer insulation film is formed by: applying a film-forming liquid containing therein SiO2 particles having a diameter in the range between about 5 nm and about 50 nm and a binder, on said first CVD film; and heating said first CVD film applied with said film-forming liquid to form said second interlayer insulation film such that said second interlayer insulation film includes a void therein between said SiO2 particles. 8. A method as claimed in claim 2, wherein said step of forming said CVD insulation film is conducted such that CVD insulation film does not penetrate into said void inside said insulation film substantially.
9. A method as claimed in claim 8, wherein said step of forming said insulation film includes a step of forming an SiO2 film by a CVD process using SiH4 and N2O as source materials.
Further, it is proposed to use a film-forming organic silica known as SOG for the interlayer insulation film. An SOG is a liquid formed of a partial hydrolysis of alkoxysilane. In this case, too, a silica film having a permittivity of about 2.5 is obtained. However, such an SOG film also suffers from the problem of poor adhesion to the underlying layer. In a typical case of the conventional SOG film that is formed of a hydrolysate of alkoxysilane or halonagated silane, the density of the Si—O—Si bonds in the film is reduced due to the existence of a hydrogen atom, fluorine atom or organic group bonded to the Si atoms, and there appears various problems, although the film may have a low permittivity as noted before, such as poor thermal stability caused as a result of poor thermal stability of the functional groups forming the film, in addition to the problem of the poor adherence to the underlying layer.
wherein said step of heating is conducted at a temperature in the range between about 350� C. and about 400� C., in an inert gas atmosphere containing oxygen with a concentration of 1% or less.
The silica particles 2 may be formed by a hydrolysis and polycondensation of alkoxysilane or a silica compound represented by a general formula of (I) XnSi(OR′)4−n (X may be a hydrogen atom, a fluorine atom or any of an alkyl group, an allyl group or a vinyl group containing 1-8 carbon atoms, R′ represents a hydrogen atom or any of an alkyl group, an allyl group or a vinyl group containing 1-8 carbon atoms, n is an integer of 0-3), while the bonding part 3 is formed of a hydrolysate of alkoxysilane represented by the foregoing formula (I) or halogenated silane represented by a general formula (II) XnSiX′4−n (X represents a hydrogen atom, a fluorine atom or any of an alkyl group, an allyl group or a vinyl group containing 1-8 carbon atoms, X′ represents a halogen atom such as a fluorine atom, a chlorine atom, a bromine atom or an iodine atom, and n is an integer in the range of 0-3).
When forming the silica particles, it is preferable to use the water with a proportion of 0.5-50 moles, preferably 1-25 moles with respect to one mole of Si—OR group forming the foregoing alkoxysilane. Further, the ammonia is used with a proportion of 0.01-1 mole, preferably 0.05-0.8 moles with respect to one mole of SiO2.
It should be noted that the hydrolysis reaction is conducted at a temperature below the boiling point of the solvent, preferably at the temperature lower than the boiling point by 5-10� C. As a result of the hydrolysis reaction at such a low temperature, the polycondensation reaction of the alkoxysilane proceeds three-dimensionally to form the ultrafine silica particles. By curing the silica particles thus formed at the foregoing reaction temperature or at a higher temperature, the polycondensation reaction proceeds further and the silica particles have a more dense structure.
It should be noted that such a sintering is conducted generally at a temperature of 450� C. or higher in the case of an SOG film. However, it has been discovered that, when the sintering process is conducted at such a high temperature in the case of the insulation film 10 of FIG. 1, the adherence between the interconnection pattern 1B and the insulation film 10 becomes poor and there tends to develop a void 1X between the conductor pattern 1B and the insulation film 10 as indicated in FIG. 3B due to the poor adhesion. The void 1X appears also when the sintering temperature is too low. In such a case, the sintering reaction does not proceed sufficiently.
TABLE I below shows the relationship between the sintering temperature and adhesion for the structure of FIG. 3B.
bad with void good with some void excellent no void Referring to TABLE I, it can be seen that a substantial formation of the void 1X occurs between the conductor pattern 1B and the insulation film 10 when the sintering process of the insulation film 10 is conducted at a temperature lower than about 300� C. or higher than about 480� C. When the sintering process is conducted at about 450� C., a slight formation of the void 1X can be seen. By setting the sintering temperature between about 350� C. and 400� C., on the other hand, it was discovered that there is no formation of the void 1X in the multilayer interconnection structure, indicating the maximum adherence of the insulation film 10.
Referring to FIG. 4, the sintering process is conducted in a nitrogen atmosphere while changing the oxygen content in the nitrogen atmosphere variously. The relationship of FIG. 4 indicates that the permittivity of the insulation film 10 increases generally with increasing oxygen content in the nitrogen atmosphere at the time of the sintering process. It is believed that this tendency of FIG. 4 indicates an oxidation reaction occurring in the hydrolysates of alkoxysilane or halogenated silane on the surface of the bonding part 3 or the silica particles 2. As a result of such an oxidation reaction, the surface of the bonding part 3 or the silica particles absorbs a substantial amount of H2O.
From the relationship of FIG. 4, it can be seen that the oxygen content in the nitrogen atmosphere at the time of the sintering process has to be suppressed below 1% in order to suppress the permittivity of the insulation film below about 3.0. It should be noted that the relationship of FIG. 4 is for the case in which the sintering temperature is set to 400� C. The permittivity of the film 10 was obtained by measuring the capacitance of the film 10 by using a mercury probe.
Referring to FIG. 5A, a conductor pattern 12 of Al or W is formed on a Si substrate 11 in which one or more semiconductor devices (not shown) are formed, and a film-forming liquid containing: silica particles formed by a hydrolysis and polycondensation of alkoxysilane or a silica compound represented by a general formula of (I) XnSi(OR′)4−n (X may be a hydrogen atom, a fluorine atom or any of an alkyl group, an allyl group or a vinyl group containing 1-8 carbon atoms, R′ represents a hydrogen atom or any of an alkyl group, an allyl group or a vinyl group containing 1-8 carbon atoms, n is an integer of 0-3); and a binder formed of a hydrolysate of alkoxysilane represented by the foregoing formula (I) or halogenated silane represented by a general formula (II) XnS/X′4−n (X represents a hydrogen atom, a fluorine atom or any of an alkyl group, an allyl group or a vinyl group containing 1-8 carbon atoms, X′ represents a halogen atom such as a fluorine atom, a chlorine atom, a bromine atom or an iodine atom, and n is an integer of 0-3), is coated on the surface of the Si substrate 11. It should be noted that the Si substrate 11 may include various diffusion regions in an active region defined by a field oxide film not illustrated. Further, the surface of the Si substrate 11 may be covered by a thin thermal oxide film. Thereby, the foregoing conductor pattern 12 may form an electrode or an interconnection pattern.
The structure of FIG. 5B is then sintered at 400� C. for about 30 minutes in an inert atmosphere of nitrogen or argon containing oxygen with a concentration smaller than 1%. As a result of the sintering, the silica binder in the interlayer insulation film 13 forms a neck structure similar to the bonding part 3 explained with reference to FIG. 1. As a result of the sintering process, a void similar to the void 4 explained in FIG. 1 is formed in the interlayer insulation film 13.
The structure of FIG. 6C is then sintered at 400� C. for about 30 minutes in an inert atmosphere of nitrogen or argon containing oxygen with a concentration smaller than 1%. As a result of the sintering, the silica binder in the interlayer insulation film 24 forms a neck structure similar to the bonding part 3 explained with reference to FIG. 1. As a result of the sintering process, a void similar to the void 4 explained in FIG. 1 is formed in the interlayer insulation film 24.
The structure of FIG. 7B is then sintered at 400� C. for about 30 minutes in an inert atmosphere of nitrogen or argon containing oxygen with a concentration smaller than 1%. As a result of the sintering, the silica binder in the interlayer insulation film 24 forms a neck structure similar to the bonding part 3 explained with reference to FIG. 1. As a result of the sintering process, a void similar to the void 4 explained in FIG. 1 is formed in the interlayer insulation film 33.
The structure of FIG. 8C is then sintered at 400� C. for about 30 minutes in an inert atmosphere of nitrogen or argon containing oxygen with a concentration smaller than 1%. As a result of the sintering, the silica binder in the interlayer insulation film 24 forms a neck structure similar to the bonding part 3 explained with reference to FIG. 1. As a result of the sintering process, a void similar to the void 4 explained in FIG. 1 is formed in the interlayer insulation film 44.
TABLE II below show the condition of deposition used normally when forming an SiO2 film by a plasma CVD process.
300 W, 13.56 MHz
N2 2000 sccm
Thus, in the present embodiment, the penetration of the CVD-SiO2 film into the porous interlayer insulation film is minimized, when forming the CVD-SiO2 film from the source gases of SiH4 and TEOS, by increasing the deposition pressure as compared with the normal deposition pressure and by increasing the flow rate of the N2O source gas as indicated in TABLE III below.
5.0-7.0 Torr
gas fluorite
1000-1500 sccm
Of course, it is possible to form the CVD-SiO2 film on the porous interlayer insulation film while using a high-density plasma CVD process. TABLE IV below represents an example of the deposition condition for forming such a CVD-SiO2 film while using a high-density plasma CVD process.
200-45O� C.
5.0-10.0 mmTorr
2000-4000 W, 13.56 MHz
SiH4 78 sccm
O2 100-400 sccm
400-480 sccm
In the present embodiment, it is also possible to form the foregoing insulation film 62B used for the etching mask from SiN in place of SiO2, which shows an excellent resistance to a dry etching process of SiO2. In this case, the dry etching process of FIG. 11E is advantageously conducted in an Ar atmosphere by using a mixture of C48 and CH2F2 as an etching gas, under a pressure of 5 mmTorr while using a bias RF power of 1000 W and a source RF power of 1000W.
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H01L21/02K2C5, H01L21/02K2T8H, H01L21/02K2C7C4B, H01L21/02K2T2F, H01L21/02K2E3L, H01L21/768B2D, H01L21/768B6, H01L21/316P, H01L21/768B8P, H01L21/768B2, H01L21/768B8T, H01L21/768B2D4Legal EventsDateCodeEventDescriptionJun 15, 1998ASAssignmentOwner name: FUJITSU LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OHKURA, YOSHIYUKI;HARADA, HIDEKI;REEL/FRAME:009269/0176Effective date: 19980603Sep 16, 2004FPAYFee paymentYear of fee payment: 4Sep 24, 2008FPAYFee paymentYear of fee payment: 8Dec 5, 2008ASAssignmentOwner name: FUJITSU MICROELECTRONICS LIMITED,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021976/0876Effective date: 20081104Aug 2, 2010ASAssignmentOwner name: FUJITSU SEMICONDUCTOR LIMITED, JAPANFree format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:024804/0269Effective date: 20100401Sep 19, 2012FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO 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