Source: http://www.google.com/patents/US8134156?dq=7,181,690
Timestamp: 2017-03-30 22:08:24
Document Index: 242909323

Matched Legal Cases: ['Application No. 2000', 'Application No. 200910129859', 'Application No. 2009', 'Application No. 2009', 'Application No. 2009', 'Application No. 2009', 'Application No. 2009', 'Application No. 2009', 'Application No. 2009', 'Application No. 2009', 'Application No. 2009', 'Application No. 2006', 'Application No. 200680037580', 'Application No. 200680037580', 'Application No. 200910129860']

Patent US8134156 - Semiconductor device including zinc oxide containing semiconductor film - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsTo provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode. The semiconductor device includes...http://www.google.com/patents/US8134156?utm_source=gb-gplus-sharePatent US8134156 - Semiconductor device including zinc oxide containing semiconductor filmAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8134156 B2Publication typeGrantApplication numberUS 11/598,669Publication dateMar 13, 2012Filing dateNov 14, 2006Priority dateNov 15, 2005Fee statusPaidAlso published asCN101283444A, CN101283444B, CN101577231A, CN101577231B, CN101577256A, CN101577256B, CN101577281A, CN101577281B, CN101577282A, CN101577293A, CN101577293B, CN101667544A, CN101667544B, CN101707212A, CN101707212B, US8158464, US8368079, US8525165, US20070108446, US20090186437, US20090186445, US20090189155, US20090189156, US20100003783, US20100038639, WO2007058329A1Publication number11598669, 598669, US 8134156 B2, US 8134156B2, US-B2-8134156, US8134156 B2, US8134156B2InventorsKengo AkimotoOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (200), Non-Patent Citations (41), Referenced by (54), Classifications (28), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device including zinc oxide containing semiconductor film
US 8134156 B2Abstract
To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode. The semiconductor device includes a gate insulating film formed by using a silicon oxide film or a silicon oxynitride film over a gate electrode, an Al film or an Al alloy film over the gate insulating film, a ZnO film to which an n-type or p-type impurity is added over the Al film or the Al alloy film, and a ZnO semiconductor film over the ZnO film to which an n-type or p-type impurity is added and the gate insulating film.
a metal film over the gate insulating film;
a conductive film comprising an oxide over and in contact with the metal film; and
a semiconductor film over and in contact with the conductive film and the gate insulating film,
wherein the conductive film has been etched in a portion over the metal film,
wherein the portion is not in contact with the semiconductor film.
2. The semiconductor device according to claim 1, wherein the gate insulating film comprises silicon oxide or silicon oxynitride.
3. The semiconductor device according to claim 1, wherein the conductive film comprises zinc oxide.
4. A liquid crystal display device comprising the semiconductor device according to claim 1.
5. The semiconductor device according to claim 1, wherein the metal film includes an Al film or an Al alloy film.
6. The semiconductor device according to claim 1, wherein the metal film includes a Ti film.
7. The semiconductor device according to claim 1, wherein the metal film includes a first metal layer comprising aluminum and a second metal layer comprising titanium where the second metal layer contacts the conductive film.
8. The semiconductor device according to claim 1, further comprising a pixel electrode in direct contact with the metal film.
9. The semiconductor device according to claim 1, wherein the conductive film further comprises a n-type or p-type impurity.
10. The semiconductor device according to claim 1, wherein the semiconductor film comprises zinc oxide.
a metal film over a substrate;
a conductive film comprising an oxide over and in contact with the metal film;
a semiconductor film over and in contact with the conductive film; and
a gate electrode adjacent to the semiconductor film with a gate insulating film interposed therebetween,
12. The semiconductor device according to claim 11, wherein the gate insulating film comprises silicon oxide or silicon oxynitride.
13. The semiconductor device according to claim 11, wherein the conductive film comprises zinc oxide.
14. A liquid crystal display device comprising the semiconductor device according to claim 11.
15. The semiconductor device according to claim 11, wherein the metal film includes an Al film or an Al alloy film.
16. The semiconductor device according to claim 11, wherein the metal film includes a Ti film.
17. The semiconductor device according to claim 11, wherein the metal film includes a first metal layer comprising aluminum and a second metal layer comprising titanium where the second metal layer contacts the conductive film.
18. The semiconductor device according to claim 11, further comprising a pixel electrode in direct contact with the metal film.
19. The semiconductor device according to claim 11, wherein the conductive film further comprises a n-type or p-type impurity.
20. The semiconductor device according to claim 11, wherein the semiconductor film comprises zinc oxide.
a gate electrode over a substrate;
a semiconductor film over and in contact with the conductive film and the gate insulating film;
an inorganic film over the semiconductor film; and
an organic resin film over the inorganic film,
22. The semiconductor device according to claim 21, wherein the gate insulating film comprises silicon oxide or silicon oxynitride.
23. The semiconductor device according to claim 21, wherein the conductive film comprises zinc oxide.
24. A liquid crystal display device comprising the semiconductor device according to claim 21.
25. The semiconductor device according to claim 21, wherein the metal film includes an Al film or an Al alloy film.
26. The semiconductor device according to claim 21, wherein the metal film includes a Ti film.
27. The semiconductor device according to claim 21, wherein the metal film includes a first metal layer comprising aluminum and a second metal layer comprising titanium where the second metal layer contacts the conductive film.
28. The semiconductor device according to claim 21, further comprising a pixel electrode in direct contact with the metal film.
29. The semiconductor device according to claim 21, wherein the conductive film further comprises a n-type or p-type impurity.
30. The semiconductor device according to claim 21, wherein the semiconductor film comprises zinc oxide.
The present invention relates to a semiconductor device using ZnO (Zinc Oxide) and a manufacturing method thereof.
A semiconductor device used for a display panel of a liquid crystal display device or an EL (Electroluminescent) display device, for example, a semiconductor portion of a TFT (Thin Film Transistor), is generally formed by using a-Si (amorphous silicon) or poly-Si (polycrystalline silicon).
Si (silicon) does not have a large band gap (for example, single-crystalline Si is 1.1 eV), and absorbs visible light. By irradiation with the light, electrons and holes (carriers) are formed in Si. If a Si film is used for a channel formation region of a TFT, a carrier is generated in the channel formation region by irradiation with the light even in an OFF state. Then, current flows between a source region and a drain region. The current which flows in an OFF state is called “OFF-leak current”. If the current value is high, a display panel does not operate normally. Consequently, a light shielding film is formed so as not to irradiate the Si film with light. However, a process becomes complex when the light shielding film is formed, because a deposition step, a photolithography step, and an etching step are required.
For the source electrode 1001 and the drain electrode 1002, a conductive ZnO is used. The conductive ZnO is doped with one of the following: B(boron), Al (aluminum), Ga (gallium), In (indium), or Tl (thallium), which are III group elements; F(fluorine), Cl (chlorine), Br (bromine), or I (iodine), which are VII group elements; Li (lithium), Na (sodium), K (potassium), Rb (rubidium), or Cs (caesium), which are I group elements; and N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), or Bi (bismuth), which are V group elements.
[Reference 1] Japanese Published Patent Application No. 2000-150900 DISCLOSURE OF INVENTION
According to the examination by the present inventor, it was revealed that the substrate 1000 is etched in some cases when the source electrode 1001 and the drain electrode 1002 of the top gate semiconductor device shown in FIG. 7A is formed by etching. Even in the case of forming a base film 1006 formed by using a silicon oxide film or a silicon oxynitride film on the substrate 1000, the surface of the substrate 1000 is exposed in some cases when the base film is etched. In addition, in the case of a bottom gate semiconductor device shown in FIG. 7B, it is revealed that a gate insulating film 1004 formed by using a silicon oxide film or a silicon oxynitride film is etched when a source electrode 1001 and a drain electrode 1002 are formed by etching.
An aspect of a semiconductor device of this invention has an Al film or an Al alloy film over a silicon oxide film or a silicon oxynitride film, and a ZnO film to which an n-type or p-type impurity is added over the Al film or the Al alloy film. “A silicon oxide film”, “a silicon oxynitride film”, “an Al film”, “an Al alloy film” and “a ZnO film” in this specification means a film containing silicon oxide, a film containing silion oxynitride, a film containing Al, a film containing Al alloy, a film containing ZnO, respectively.
Here, a bottom gate semiconductor device is described.
A gate electrode can be formed by using an Al (aluminum) film, a W (tungsten) film, a Mo (molybdenum) film, a Ta (tantalum) film, a Cu (copper) film, a Ti (titanium) film, an alloy material containing the elements as a main component (for example, an Al alloy film, a MoW (molybdenum tungsten) alloy film), or the like. A semiconductor film represented by a polycrystalline silicon film doped with an impurity element such as P (phosphourus) may be used. The gate electrode 3 may be a single layer or a layered film in which two or more layers are stacked.
Here, a top gate semiconductor device is described.
A manufacturing method of the bottom gate semiconductor device is described, in which a silicon oxide film or a silicon oxynitride film is formed as a gate insulating film over the gate electrode, an Al film or an Al alloy film is formed as a first conductive film, and a ZnO film to which an n-type or p-type impurity is added is formed as a second conductive film, and then, the second conductive film is etched to have an island-like shape by a first etching and the first conductive film is etched to have an island-like shape by a second etching to form source and drain electrodes, and a ZnO semiconductor film is formed.
The insulating film 2 may be formed by processing the surface of the substrate 1 with high density plasma. For example, the high density plasma can be generated using a microwave of 2.45 GHz, and it is only required that electron density ranges from 1×1011 to 1×1013/cm3, and electron temperature is 2 eV or less. Such high density plasma has a low kinetic energy of active species and a film with fewer defects can be formed with less damage caused by plasma compared to a conventional plasma treatment.
After cleaning the surface of the gate electrode 3 and the surface of the substrate 1 or the insulating film 2, a gate insulating film 5 is formed with a thickness of 10 to 200 nm using a known CVD or sputtering over the gate electrode 3 (FIG. 2A and 2B). The surface cleaning step and the formation step of the gate insulating film 5 may be carried out continuously without being exposed to air. In the case where an Al film is used for the gate electrode 3, when the gate insulating film 5 is formed at a high temperature, a hillock is generated in some cases. Thus, it is preferable to form the film at a low temperature of 500° C. or less, preferably 350° C. or less.
A second conductive film 7 is formed with a thickness of 10 to 200 nm on the first conductive film 6 (FIG. 2C). The second conductive film 7 can be formed by using the material shown in Embodiment 1. Here, ZnO (zinc oxide) to which an impurity such as Al or Ga is added is used. Consequently, an ohmic contact can be easily created between the second conductive film 7 and a ZnO film which is formed as a semiconductor layer later. The second conductive film 7 can be formed by sputtering. For example, the following methods can be used for adding Al or Ga: sputtering using a ZnO target to which 1 to 10 weight % of Al or Ga is added; or sputtering in which an Al or Ga chip is mounted on a ZnO target at 200 to 300° C.
In the case of using an AlNi film for the first conductive film 6 and TMAH for etching solution, the etching ratio is approximately 300 nm/min at 30° C. On the other hand, the second conductive film 7 or the gate insulating film 5 to which the above-mentioned material is used is not etched with TMAH. Consequently, the source electrode 10 and the drain electrode 11 can be formed without damaging the gate insulating film 5. Further, the island-like shaped second conductive films 10 b and 11 b are not reduced in size. In this invention, the first conductive film 6 can be etched using a developer which is used when a resist mask is formed without using a special etching solution. Consequently, cost is reduced and efficiency is increased.
A ZnO film is formed as a semiconductor film 12 with a thickness of 20 to 200 nm by sputtering over the source electrode 10, the drain electrode 11, and the gate insulating film 5 (FIG. 3D). For example, the film can be formed by sputtering using a ZnO target with a flow ratio of oxygen/argon ranging from 30 to 20, at 200 to 300° C.
Zno is commonly used in the semiconductor film 12 and the second conductive films 10 b and 11 b, and it is difficult to obtain a sufficient etching selectivity. However, since the second conductive film 7 is required to be formed in a portion in contact with the semiconductor film 12, the second conductive film 7 may be etched in a portion out of contact with the semiconductor film 12, for example, a wire portion. In the above-mentioned etching method, the second conductive films 10 b and 11 b may be etched, but the first conductive films 10 a and 11 a are not etched. Consequently, the first conductive films 10 a and 11 a serve as wires, and the electrical connection with the semiconductor device is ensured.
An insulating film 14 is formed with a thickness of 50 nm to 1 μm over a semiconductor film 13 by CVD or sputtering (FIG. 4B). An insulating film containing silicon as a main component can be formed as the insulating film 14. An organic resin film or the like may be stacked over the insulating film containing silicon. The insulating film 14 functions as a planarization film or a passivation film. Since Al is included in the source electrode 10 and the drain electrode 11, a hillock is occasionally generated when the insulating film 14 is formed at high temperature. Thus, it is preferably formed at low temperature, 500° C. or less, preferably 350° C. or less.
Here, a manufacturing method of a top gate semiconductor device is described, in which an Al film or an Al alloy film is formed as a first conductive film on a silicon oxide film or a silicon oxynitride film, and a ZnO film to which an n-type or p-type impurity is added is formed as a second conductive film, and then, the second conductive film is formed to have an island-like shape by a first etching, the first conductive film is formed to have an island-like shape by a second etching to form source and drain electrodes, a ZnO semiconductor film is formed, a gate insulating film is formed, and a gate electrode is formed. Note that it is needless to say that materials and methods for manufacture described in Embodiments 1 to 3 can be applied to those used for the present embodiment.
A second conductive film 22 is formed with a thickness of 10 to 200 nm by sputtering on the first conductive film 21 (FIG. 5A). As the second conductive film 22, ZnO (zinc oxide) to which a p-type or n-type impurity such as B (boron), Al (aluminum), Ga (gallium), P (phosphourus), or As (arsenic) is added can be used. After forming the first conductive film 21, the second conductive film 22 may be formed continuously without being exposed to the air. Therefore, the steps of forming the insulating film 20 to the second conductive film 22 may be carried out continuously without being exposed to the air.
The first conductive film 21 is etched to form the source electrode 25 and the drain electrode 26 (FIG SD). Wet etching using a developer for a photoresist, TMAH is used as an etching method. Thus, the source electrode 25 and the drain electrode 26 can be formed without etching the insulating film 20. Further, the sizes of the island-like shaped second conductive films 25 b and 26 b are not reduced because the ZnO film is not etched by TMAH. Etching can be performed with a developer which is used in formation of a resist mask without a special etching solution for the first conductive film 21, which leads to cost reduction and improvement in efficiency.
A gate electrode 29 is formed over the gate insulating film 28 (FIG. 6B). The gate electrode 29 can be formed by using the material shown in the above-mentioned embodiment, and may be a single layer or a layered film including two or more layers. A known CVD sputtering, evaporation, or the like can be employed as a method for film formation. Dry etching or wet etching method can be used for processing the gate electrode 29 into an island-like shape with a photolithography method.
An insulating film 30 is formed with a thickness of 50 nm to 1 μm by CVD or sputtering over the gate electrode 29 and the gate insulating film 28 (FIG. 6C). The insulating film 30 can be formed by using an insulating film containing silicon. An organic resin film or the like may be stacked over the insulating film containing silicon. The insulating film 30 functions as a planarization film or a passivation film. Since Al is included in the source electrode 25 and the drain electrode 26, a hillock is occasionally generated when the gate insulating film 28, the gate electrode 29, and the insulating film 30 are formed at a high temperature. Thus, they are preferably formed at a low temperature, at 500° C. or less, preferably 350° C. or less.
Here, a description is made of a method of manufacturing a liquid crystal display device using a bottom gate semiconductor device which is shown in Embodiments 1 and 3 referring to FIGS. 8A and 8B and 9A and 9B. Note that it is needless to say that the top gate semiconductor device which is shown in Embodiments 2 and 4 can be applied. FIGS. 8A and 9A show cross-sectional views taken along line X-Y in FIG. 8B.
A transparent conductive film is formed by sputtering, and then, a pixel electrode 50 is formed using a photolithography method and etching. For example, ITO (Indium Tin Oxide), ITSO (Indium Tin Oxide containing silicon oxide), or IZO (Indium Zinc Oxide) may be used.
As an alignment mode of the liquid crystal composition 52, TN mode in which the alignment of liquid crystal molecules is twisted at 90° from the side of light incidence to the side of light emission, FLC mode, IPS mode, or the like can be used. Note that an electrode pattern is different from one shown in FIG. 8B and is a comb-like shape in the case of the IPS mode.
Then, an FPC (Flexible Printed Circuit) is attached to the the substrate 1 with an anisotropic conductive layer interposed therebetween using a known technique.
Here, a description is made of a method for manufacturing a light-emitting device with using the bottom gate semiconductor device shown in Embodiments 1 and 3 referring to FIGS. 10A and 10B and 11A and 11B. Note that it is needless to say that the semiconductor device of Embodiments 2 and 4 can be applied.
In the EL display device, the pixel electrode 50 functions as an anode or a cathode. As the material for the pixel electrode 50, the following can be employed: a conductive metal such as aluminum (Al), silver (Ag), gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), lithium (Li), caesium (Cs), magnesium (Mg), calcium (Ca), strontium (Sr), or titanium (Ti); an alloy such as aluminum-silicon (Al—Si), aluminum-titanium (Al—Ti), or aluminum-silicon-copper (Al—Si—Cu); nitride of a metal material such as titanium nitride (TiN); a metal compound such as ITO, ITO containing silicon, or IZO.
Next, an insulating film formed by using an organic material or an inorganic material is formed so as to cover the insulating film 49 and the pixel electrode 50. Then, the insulating film is processed to expose the pixel electrode 50 partially, thereby forming partition walls 81. As the material of the partition walls 81, a photosensitive organic material (such as acrylic or polyimide) is preferable. Alternatively, a non-photosensitive organic material or inorganic material may also be used. Further, the partition walls 81 may be used as a black matrix by coloring the partition walls 81 black in such a way that a black pigment or dye such as titanium black or carbon nitride is dispersed into the material of the partition wall 81 with the use of a dispersant. It is desirable that the partitions wall 81 have a tapered shape and those end surfaces 81 a toward the pixel electrode have curvatures changing continuously (FIG. 10B).
As an organic compound, the following can be employed: an organic material having an arylamino group such as 4,4′-bis[N-(1-napthyl)-N-phenylamino]biphenyl (NPB), 4,4′-bis[N-(3-methylphenyl]-N-phenylaminolbiphenyl (TPD), 4,4′,4″-tris(N,N-diphenylamino)triphenylamine (TDATA), 4,4′,4″-tris[N-(3-methylphenyl)-N-phenylamino]triphenylamine (MTDATA), 4,4′-bis{N-[4-(N,N-di-m-tolylamino)phenyl]-N-phenylamino}biphenyl (DNTPD), 1,3,5-tris[N,N-di(m-tolyl)amino] benzene (m-MTDAB), and 4,4′,4″-tris(N-carbazolyl) triphenylamine (TCTA); phthalocyanine (H2Pc); copper phthalocyanine (CuPc); vanadyl phthalocyanine (VOPc); or the like.
The hole transporting layer is provided between the anode and a light-emitting layer, or between the hole injecting layer and the light-emitting layer when the hole injecting layer is provided. The hole transporting layer is formed by using a layer which has an excellent property of transporting a hole, for example, a layer formed by using a compound of aromatic amine (that is, having a benzene ring-nitrogen bond) such as NPB, TPD, TDATA, MTDATA, and BSPB. The substances mentioned here have the hole mobility of 1×10−6 to 10 cm2/Vs mainly. Note that a substance having higher transporting property of holes than electrons may be used as well as the materials. Note that the hole transporting layer may be formed by not only a single layer but also a layered film in which two or more layers formed from the above mentioned substances are stacked.
An electron transporting layer is provided between the light-emitting layer and the cathode, or between the light-emitting layer and an electron injecting layer when the electron injecting layer is provided. The electron transporting layer is a layer having an excellent electron transporting property, and for example, a layer formed using a metal complex having a quinoline skeleton or a benzoquinoline skeleton such as tris(8-quinolinolato)aluminum (Alq3), tris(5-methyl-8-quinolinolato)aluminum (Almq3), bis(10-hydroxybenzo[h]-quinolinato)beryllium (BeBq2), and bis(2-methyl-8-quinolinolato)-4-phenylphenolato-aluminum (BAlq). In addition, a metal complex having an oxazole ligand or a thiazole ligand such as bis[2-(2-hydroxyphenyl)-benzoxazolato]zinc (Zn(BOX)2), bis[2-(2-hydroxyphenyl)-benzothiazolato]zinc (Zn(BTZ)2), or the like can be used. In addition to the metal complexes, 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (PBD); 1,3-bis[5-(p-tert-butylphenyl)-1,3,4-oxadiazole-2-yl]benzene (OXD-7); 3-(4-tert-butylphenyl)-4-phenyl-5-(4-biphenylyl)-1,2,4-triazole (TAZ); 3-(4-tert-butylphenyl)-4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole (p-EtTAZ); bathophenanthroline (BPhen); bathocuproine (BCP); or the like can be used. These substances mentioned here mainly have the electron mobility of 1×10−6 to 10 cm2/Vs. Note that other substance may be used for the electron transporting layer so long as it has a higher electron transporting property than a hole transporting property. Further, the electron transporting layer may be formed by not only a single layer but also a layered film in which two or more layers made from the above mentioned substances are stacked.
Subsequently, a case will be described in which a diode is provided as a protective circuit on the scan line and the signal line with the use of an equivalent circuit shown in FIG 12E.
In FIG. 13, the switching TFT 1401, the driving TFT 1403, the auxiliary capacitor 1402, and the light-emitting element 1405 are provided in a pixel area 1500. Diodes 1561 and 1562 are provided on the signal line 1410. In the similar way to the switching TFT 1401 and the driving TFT 1403, the diodes 1561 and 1562 are manufactured based on the above embodiments, and have a gate electrode, a semiconductor layer, a source electrode, a drain electrode, and the like. The diodes 1561 and 1562 are operated as diodes by connecting the gate electrode with the drain electrode or the source electrode.
A top view of a pixel portion in the case of using an equivalent circuit shown in FIG. 12E is described in FIG. 14A. In addition, the same equivalent circuit as that in FIG. 12E is shown in FIG. 14B. Each semiconductor device shown in FIGS. 10A, 10B, 11A, and 11B is corresponds to each driving TFT 1403. FIGS. 10A, 10B, 11A and 11B show cross-sectional views taken along line X-Y in FIG. 14A and 14B. The power source line 1411, the signal line 1410, and the source electrode and the drain electrode of the switching TFT 1401 are formed by using the first conductive film, and the source electrode and the drain electrode of the driving TFT 1403 are formed by using the second conductive film.
As an electronic device having semiconductor devices according to this invention mounted with modules shown as examples in the above embodiments, a camera such as a video camera or a digital camera; a goggle type display (a head mounted display); a navigation system; an audio reproducing device (e.g., a car audio component); a computer; a game machine; a portable information terminal (e.g., a mobile computer, a cellular phone, a portable game machine, an electronic book, or the like); an image reproducing device equipped with a recording medium (specifically, a device which can reproduce the content of a recording medium such as a digital versatile disc (DVD) and which has a display for displaying an image stored therein); and the like can be given. Specific examples of these electronic appliances are shown in FIGS. 15A to 15E, and FIG. 16.
FIG. 15B shows a cellular phone, including a main body 3101, a housing 3102, a display area 3103, an audio input portion 3104, an audio output portion 3105, operation keys 3106, an antenna 3108, and the like. An active matrix display device is provided in the display area 3103. Each pixel of the display area 3103 includes a semiconductor device manufactured in accordance with this invention. By using the semiconductor device of this invention with this structure, a cellular phone with less characteristic deterioration can be obtained.
1: substrate, 2: insulating film, 3: gate electrode, 5: gate insulating film, 6: first conductive film, 7: second conductive film, 8: third conductive film, 9: resist mask, 10: source electrode, 10 a: source electrode, first conductive film, 10 b: source electrode, second conductive film, 11: drain electrode, 11 a: drain electrode, first conductive film, 11 b: drain electrode, second conductive film, 12: semiconductor film, 13: island-like shaped semiconductor film, 14: insulating film, 20: insulating film, 21: first conductive film, 22: second conductive film, 23: third conductive film, 24: resist mask, 25: source electrode, 25 a: source electrode, first conductive film, 25 b: source electrode, second conductive film, 26: drain electrode, 26 a: drain electrode, first conductive film, 26 b: drain electrode, second conductive film, 27: semiconductor film, 28: gate insulating film, 29: gate electrode, 30: insulting film, 40: gate electrode, gate wire, 41: auxiliary capacitor wire, 42: gate insulating film, 45: source electrode, 45 a: source electrode, 45 b: source electrode, 46: drain electrode, 46 a: drain electrode, 46 b: drain electrode, 47: source wire, 48: semiconductor film, 49: insulating film, 50: pixel electrode, 51: alignment wire, 52: liquid crystal composition, 53: alignment film, 54: protective insulating film, 55: color filter, 56: opposing substrate, 61: substrate, 62: gate wire driver circuit, 62 a: shift register, 62 b: buffer, 63: source wire driver circuit, 63 a: shift register, 63 b: buffer, 64: active matrix portion, 65: semiconductor device, 66: liquid crystal portion, 67: auxiliary capacitor, 68: video line, 69: analog switch, 71: source wire, 72: gate wire, 73: auxiliary capacitor wire, 75: sealant, 81: partition wall, 81 a: end surface, 82: layer including light-emitting substance, 83: opposing electrode, 84: drying agent, 85: resin, 86: opposing substrate, 87: protective film, 88: polarizing plate, 100: auxiliary capacitor, 1000: substrate, 1001: source electrode, 1002: drain electrode, 1003: semiconductor film, 1004: gate insulating film, 1005: gate electrode, 1006: base film, 1401: switching TFT, 1402: auxiliary capacitor, 1403: driving TFT, 1404: current control TFT, 1405: light-emitting element, 1406: TFT, 1410: signal line, 1411: power source line, 1412: power source line, 1414: scan line, 1415: scan line, 1420: light-emitting region, 1500: pixel portion, 1554: common potential line, 1555: common potential line, 1561: diode, 1562: diode, 1563: diode, 1564: diode, 1565: common potential line, 1566: common potential line, 3001: housing, 3003: display area, 3004: speaker, 3101: main body, 3102: housing, 3102: housing, 3103: display area, 3104: audio input portion, 3105: audio output portion, 3106: operation keys, 3107: infrared communication port, 3108: antenna, 3110: main body, 3111: pixel portion, 3112: driver IC, 3113: receiving device, 3114: film buttery, 3201: main body, 3202: housing, 3203: display area, 3204: keyboard, 3205: external connection port, 3206: pointing mouse, 3301: main body, 3302: display area, 3303: switch, 3304: operation keys, 3305: infrared port, 3401: housing, 3402: display area, 3403: speakers, 3404: operation keys, 3405: recording medium insert portion
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ClassificationH01L29/04, G02F1/1368, G02F1/1333, H01L29/786, H05B33/10, H01L21/28, G09F9/30, H01L51/50, H01L21/336, H01L21/316Cooperative ClassificationH01L27/1214, H01L29/78621, H01L29/7869, H01L29/41733, H01L29/4908, H01L29/45European ClassificationH01L29/417D2, H01L29/45, H01L29/786K, H01L29/49B, H01L29/786B4BLegal EventsDateCodeEventDescriptionNov 14, 2006ASAssignmentOwner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AKIMOTO, KENGO;REEL/FRAME:018609/0967Effective date: 20061108Owner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AKIMOTO, KENGO;REEL/FRAME:018609/0967Effective date: 20061108Aug 26, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services