Source: https://patents.google.com/patent/US8811917B2/en
Timestamp: 2019-07-17 05:46:14
Document Index: 747448100

Matched Legal Cases: ['Application No. 2010', 'Application No. 2010', 'Application No. 2010', 'Application No. 2012', 'Application No. 10', 'Application No. 200880021049', 'Application No. 08746721', 'Application No. 2010', 'Application No. 2010', 'Application No. 200880021049', 'Application No. 2010', 'Application No. 200880021049']

US8811917B2 - Digital hybrid mode power amplifier system - Google Patents
Digital hybrid mode power amplifier system Download PDF
US8811917B2
US8811917B2 US12/108,502 US10850208A US8811917B2 US 8811917 B2 US8811917 B2 US 8811917B2 US 10850208 A US10850208 A US 10850208A US 8811917 B2 US8811917 B2 US 8811917B2
US12/108,502
US20080265996A1 (en
2002-05-01 Priority to US10/137,556 priority Critical patent/US6985704B2/en
2005-10-27 Priority to US11/262,079 priority patent/US8326238B2/en
2007-04-23 Priority to US92560307P priority
2007-04-23 Priority to US92557707P priority
2007-04-30 Priority to US11/799,239 priority patent/US8064850B2/en
2007-08-30 Priority to US96912707P priority
2007-08-30 Priority to US96913107P priority
2008-01-28 Priority to US12/021,241 priority patent/US8380143B2/en
2008-03-31 Priority to US4116408P priority
2008-04-23 Priority to US12/108,502 priority patent/US8811917B2/en
2008-04-23 Application filed by Dali Systems Co Ltd filed Critical Dali Systems Co Ltd
2008-08-07 Assigned to DALI SYSTEMS CO. LTD. reassignment DALI SYSTEMS CO. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHO, KYOUNG JOON, KIM, JONG HEON, KIM, WAN JONG, STAPLETON, SHAWN PATRICK, YANG, DALI
2008-10-30 Publication of US20080265996A1 publication Critical patent/US20080265996A1/en
2010-04-26 Priority claimed from US12/767,669 external-priority patent/US9026067B2/en
2011-08-16 Priority claimed from US13/211,247 external-priority patent/US8737300B2/en
2014-08-19 Publication of US8811917B2 publication Critical patent/US8811917B2/en
This is a continuation-in-part of U.S. patent application Ser. No. 12/021,241, filed Jan. 28, 2008, entitled Power Amplifier Time-Delay Invariant Predistortion Methods and Apparatus, which in turn is a continuation-in-part of U.S. patent application Ser. No. 11/799,239, filed Apr. 30, 2007, entitled High Efficiency Linearization Power Amplifier For Wireless Communication, which in turn is a continuation-in-part of U.S. patent application Ser. No. 11/262,079, filed Oct. 27, 2005, entitled System and Method for Digital Memorized Predistortion for Wireless Communication, which in turn is a continuation of U.S. patent application Ser. No. 10/137,556, filed May 1, 2002 now U.S. Pat. No. 6,985,704, entitled System and Method for Digital Memorized Predistortion for Wireless Communication, all of which are incorporated herein by reference. This application claims the benefit of U.S. patent application Ser. No. 11/961,969 filed Dec. 20, 2007, entitled A Method for Baseband Predistortion Linearization in Multi-Channel Wideband Communication Systems. This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/925,603, filed Apr. 23, 2007, and having the same inventors as the present case with the exception of Dali Yang, and also claims the benefit of U.S. Provisional Application Ser. No. 61/041,164, filed Mar. 31, 2008, entitled An Efficient Peak Cancellation Method For Reducing The Peak-To-Average Power Ratio In Wideband Communication Systems, and also claims the benefit of U.S. Provisional Application Ser. No. 61/012,416, filed Dec. 7, 2007, entitled Baseband Derived RF Digital Predistortion, and also claims the benefit of U.S. Provisional Application Ser. No. 60/925,577, filed Apr. 23, 2007, entitled N-Way Doherty Distributed Power Amplifier. Further, this application claims the benefit of U.S. patent application Ser. No. 11/962,025, filed Dec. 20, 2007, entitled Power Amplifier Predistortion Methods and Apparatus, U.S. Provisional Patent Application Ser. No. 60/969,127, filed Aug. 30, 2007, entitled Analog Power Amplifier Predistortion Methods and Apparatus, and U.S. Provisional Patent Application Ser. No. 60/969,131, entitled Power Amplifier Predistortion Methods and Apparatus Using Envelope and Phase Detector. All of the foregoing are incorporated herein by reference.
1. A digital hybrid mode power amplifier system comprising:
a down-converted RF input;
a multi-channel digital input;
a digital predistortion module for receiving at least one of the down-converted RF input or multi-channel digital input, wherein the digital predistortion module utilizes a predistortion polynomial;
a power amplifier portion responsive to signals representative of an output of the digital predistortion module;
a down-converted feedback portion adapted to monitor signals representative of adjacent channel power for feeding back to the digital predistortion module signals representative of an output of one or more channels of the power amplifier portion, in response to which the digital predistortion module computes the predistortion polynomial and modifies its output to reduce adjacent channel power level; and
wherein the digital predistortion module searches locations of a main channel signal to determine a value representative of adjacent channel power, and implements a multi-directional search algorithm comprising evaluation, rotation, expansion, and contraction using the adjacent channel power value or an adjacent channel power ratio as an evaluation function to develop coefficients for modifying its output.
2. The digital hybrid mode power amplifier system of claim 1 wherein the digital predistortion module comprises at least one of a digital field programmable gate array, digital-to-analog converters, analog-to-digital converters, or a phase-locked loop.
3. The digital hybrid mode power amplifier system of claim 2 wherein:
the power amplifier system is configured for base station applications, and
the digital field programmable gate array comprises at least one of a digital up-converter, a crest factor reduction, a predistorter, or a digital quadrature modulator.
4. The digital hybrid mode power amplifier system of claim 2 wherein:
the power amplifier system is configured for repeater applications, and
the digital field programmable gate array comprises at least one of a digital quadrature demodulator, a crest factor reduction, a predistorter, or a digital quadrature modulator.
5. The digital hybrid mode power amplifier system of claim 2 wherein the digital field programmable gate array provides predistortion that compensates adaptively for both nonlinearity and memory effects of the power amplifier portion by generating asymmetric distortion of a power amplifier.
6. The digital hybrid mode power amplifier system of claim 5 wherein the adaptive compensation for predistortion further comprises:
updating coefficients by detecting adjacent channel powers; and
using the adjacent channel power in performing an evaluative function.
7. The digital hybrid mode power amplifier system of claim 2 wherein the digital field programmable gate array comprises an adaptation algorithm to determine an optimum gate bias voltage of a power amplifier for stabilizing linearity fluctuations due to temperature changes of the power amplifier.
8. The digital hybrid mode power amplifier system of claim 1 wherein the power amplifier portion comprises at least one of an up-converter for real signal and an analog quadrature modulator for real and complex signals, a high power amplifier with multi-stage drive amplifiers, or a temperature sensor.
9. The digital hybrid mode power amplifier system of claim 8 wherein the power amplifier portion uses efficiency boosting techniques comprising at least one of Doherty, Envelope Elimination and Restoration, Envelope Tracking, Envelope Following, or Linear amplification using Nonlinear Components.
10. The digital hybrid mode power amplifier system of claim 1 wherein the down-converted feedback portion comprises at least one of a directional coupler, a mixer, a low pass filter, gain amplifiers, a band pass filter, or detectors.
11. The digital hybrid mode power amplifier system of claim 1 wherein in-band distortion resulting from a clipped signal at the output of the power amplifier portion caused by crest factor reduction is compensated by a DAC and UPC responsive to an output of the digital predistortion module.
12. A digital hybrid mode power amplifier system comprising:
a digital predistortion module for receiving multi-channel digital input, wherein the digital predistortion module utilizes a predistortion polynomial;
13. The digital hybrid mode power amplifier system of claim 12 wherein the digital predistortion module comprises at least one of a digital field programmable gate array, digital-to-analog converters, analog-to-digital converters, or a phase-locked loop.
14. The digital hybrid mode power amplifier system of claim 13 wherein:
15. The digital hybrid mode power amplifier system of claim 13 wherein the digital field programmable gate array provides predistortion that compensates adaptively for both nonlinearity and memory effects of the power amplifier portion by generating asymmetric distortion of a power amplifier.
16. The digital hybrid mode power amplifier system of claim 15 wherein the adaptive compensation for predistortion further comprises:
17. The digital hybrid mode power amplifier system of claim 13 wherein the digital field programmable gate array comprises an adaptation algorithm to determine an optimum gate bias voltage of a power amplifier for stabilizing linearity fluctuations due to temperature changes of the power amplifier.
18. The digital hybrid mode power amplifier system of claim 12 wherein the power amplifier portion comprises at least one of an up-converter for real signal and an analog quadrature modulator for real and complex signals, a high power amplifier with multi-stage drive amplifiers, or a temperature sensor.
19. The digital hybrid mode power amplifier system of claim 18 wherein the power amplifier portion uses efficiency boosting techniques comprising at least one of Doherty, Envelope Elimination and Restoration, Envelope Tracking, Envelope Following, or Linear amplification using Nonlinear Components.
20. The digital hybrid mode power amplifier system of claim 12 wherein the down-converted feedback portion comprises at least one of a directional coupler, a mixer, a low pass filter, gain amplifiers, a band pass filter, or detectors.
21. The digital hybrid mode power amplifier system of claim 12 wherein in-band distortion resulting from a clipped signal at the output of the power amplifier portion caused by crest factor reduction is compensated by a DAC and UPC responsive to an output of the digital predistortion module.
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