Source: http://www.google.com/patents/US8080869?dq=6,163,776
Timestamp: 2017-05-25 13:52:51
Document Index: 670410123

Matched Legal Cases: ['Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 10', 'Application No. 095143570', 'Application No. 2005', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 06', 'Application No. 095143554', 'Application No, 12']

Patent US8080869 - Wafer level package structure and production method therefor - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA wafer level package structure, in which a plurality of compact sensor devices with small variations in sensor characteristics are formed, and a method of producing the same are provided. This package structure has a semiconductor wafer having plural sensor units, and a package wafer bonded to the semiconductor...http://www.google.com/patents/US8080869?utm_source=gb-gplus-sharePatent US8080869 - Wafer level package structure and production method thereforAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8080869 B2Publication typeGrantApplication numberUS 12/094,600PCT numberPCT/JP2006/323445Publication dateDec 20, 2011Filing dateNov 24, 2006Priority dateNov 25, 2005Fee statusPaidAlso published asEP1953814A1, EP1953814A4, US20090159997, WO2007061047A1Publication number094600, 12094600, PCT/2006/323445, PCT/JP/2006/323445, PCT/JP/6/323445, PCT/JP2006/323445, PCT/JP2006323445, PCT/JP6/323445, PCT/JP6323445, US 8080869 B2, US 8080869B2, US-B2-8080869, US8080869 B2, US8080869B2InventorsTakafumi Okudo, Yuji Suzuki, Yoshiyuki Takegawa, Toru Baba, Kouji Gotou, Hisakazu Miyajima, Kazushi Kataoka, Takashi SaijoOriginal AssigneePanasonic Electric Works Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (91), Non-Patent Citations (28), Referenced by (4), Classifications (31), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetWafer level package structure and production method therefor
First, as shown in FIG. 14A, the sensor substrate 1, the first package substrate 2 and the second package substrate 3 are placed in a chamber CH, and the air in the chamber is exhausted to be not greater than a predetermined degree of vacuum (e.g., 1×10−5 Pa). Subsequently, under a reduced atmosphere, surfaces of the sensor substrate 1, the first package substrate 2 and the second package substrate 3 are cleaned up by means of sputter etching, and then a surface activation treatment is performed. That is, the surface activation treatment is performed to the surfaces of the first and second metal layers (18, 19) of the sensor substrate 1, the surface of the frame portion 11 to be bonded to the second package substrate 3, the metal layers (28, 29) of the first package substrate 2, and the surface of the second package substrate 3 to be bonded to the sensor substrate. As the surface activation treatment, an argon ion beam is irradiated to the surfaces to be treated for a predetermined time period (e.g., 300 seconds). During the surface activation treatment, the internal pressure of the chamber is maintained at a lower degree of vacuum (e.g., approximately 1×10−2 Pa) than the above-described degree of vacuum. In place of the argon ion beam, an atomic beam or a plasma of argon may be used. The gas used for the surface activation treatment is not limited to argon. Alternatively, an inert gas such as nitrogen and helium may be used.
As an example, the first package substrate 2 having a preferred layout of the pad electrodes 25 and the intermediate wiring layers 27 is shown in FIG. 22. In this example, a plurality of pad electrodes 25 each having a square shape are arranged on each of lattice points of a 6×6 square lattice. In addition, the second metal layer 19 is formed at 11 locations with respect to each of the four sides of the sensor substrate 1, and the wiring layer 29 is formed at a position facing each of the second metal layers 19. For example, with respect to each of the second metal layers 19 formed at 5 locations along the right side of the square lattice, the wiring layer 29 facing the second metal layer 19 is electrically connected to the through-hole wiring 24 formed in the inner bottom surface of the concave portion 21 of the first package substrate 2 through the intermediate wiring layer 27. Thus, since the layout of the pad electrodes 25 and the through-hole wirings 24 is not restricted by the layout of the wiring layers 29 facing the second metal layers 19, the entire surface of the first package substrate 2 can be efficiently utilized. In addition, even when the wiring layers 29 facing the second metal layers 19 are arranged on the first package substrate 2 at a relatively narrow pitch or interval suitable for flip-chip mounting, the pad electrodes 25 can be arranged on the opposite surface of the first package substrate 2 at a relatively wide pitch or interval suitable for reflow soldering.
In the present embodiment, the sensor substrate 101 is formed by use of a silicon substrate having a resistivity of 0.2 Ω·cm. Each of the first and second package substrates (102, 103) is formed by use of a silicon substrate having a resistivity of 20 Ω·cm. These resistivity values are illustrative only, and therefore the present invention is not limited to them.
After micromachining is appropriately performed to the sensor substrate 101, and the sensor substrate 102 is bonded to the second package substrate 103 at room temperature, an etching step for separating a portion used as the movable portion of the sensor substrate 101 from the other portion and a metal layer formation step for forming the first and second metal layers (126, 128) are performed. In the present embodiment, the sensor substrate 101 is bonded to the second package substrate 103 by the room-temperature bonding between Si and SiO2. Subsequently, the sensor substrate 101 integrated with the second package substrate 103 and the first package substrate 102 are placed in the chamber, and the chamber is vacuum exhausted to a predetermined degree of vacuum (e.g., 1×10−5 Pa). Then, a surface activation treatment is performed. That is, the surfaces to be bonded to each other of the sensor substrate 101 and the first package substrate 102 are cleaned up and activated by means of sputter etching in vacuum. The degree of vacuum in the chamber during the surface activation treatment is approximately 1×10−2 Pa, which is a lower degree of vacuum, as compared with the predetermined degree of vacuum in the chamber before the surface activation treatment.
After the surface activation treatment, an atmosphere adjusting step is performed to adjust the interior atmosphere of the chamber, in which the sensor substrate 101 and the second package substrate 103 are placed, to a designed atmosphere determined according to gyro sensor characteristics. In this regard, the gyro sensor of the present embodiment is designed in a predetermined degree of vacuum (a high vacuum of 1×10−4 Pa or less), in order to increase a mechanical Q value (mechanical quality coefficient Qm) indicative of a mechanical vibration level in the vicinity of the resonance frequency, and achieve an improvement in sensitivity. In the atmosphere adjustment step of the present embodiment, after the surface activation treatment is finished, the interior atmosphere of the chamber is adjusted to the designed atmosphere by performing vacuum pumping until the degree of vacuum in the chamber reaches a predetermined degree of vacuum.
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No. 12/094,772 from U.S. Patent and Trademark Office mailed Jun. 8, 2010.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS9309106Feb 13, 2015Apr 12, 2016Motion Engine Inc.3D MEMS device and method of manufacturingUS9491867 *Sep 29, 2015Nov 8, 2016Ngk Spark Plug Co., Ltd.Wiring substrate and multi-piece wiring substrateUS20130155629 *May 10, 2012Jun 20, 2013Tong Hsing Electronic Industries, Ltd.Hermetic Semiconductor Package Structure and Method for Manufacturing the sameUS20160095217 *Sep 29, 2015Mar 31, 2016Ngk Spark Plug Co., Ltd.Wiring substrate and multi-piece wiring substrate* Cited by examinerClassifications U.S. Classification257/704, 257/E23.193, 438/125International ClassificationH01L23/12Cooperative ClassificationG01P2015/0842, H01L2224/83896, H01L2224/83895, B81B7/0048, B81C2203/019, H01L21/50, H01L23/10, G01P15/18, B81B2201/0242, G01P15/123, G01P15/0802, B81B2201/0235, B81C1/00269, G01P1/023, B81C2203/038, B81C2203/0109, G01P15/125, H01L2924/01079, H01L2924/0002European ClassificationG01P15/08A, B81C1/00C14B, G01P15/12D, G01P15/125, G01P15/18, H01L23/10, H01L21/50, G01P1/02BLegal EventsDateCodeEventDescriptionJun 10, 2008ASAssignmentOwner name: MATSUSHITA ELECTRIC WORKS, LTD.,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OKUDO, TAKAFUMI;SUZUKI, YUJI;TAKEGAWA, YOSHIYUKI;AND OTHERS;REEL/FRAME:021075/0073Effective date: 20080527Owner name: MATSUSHITA ELECTRIC WORKS, LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OKUDO, TAKAFUMI;SUZUKI, YUJI;TAKEGAWA, YOSHIYUKI;AND OTHERS;REEL/FRAME:021075/0073Effective date: 20080527Jan 28, 2009ASAssignmentOwner name: PANASONIC ELECTRIC WORKS CO., LTD.,JAPANFree format text: CHANGE OF NAME;ASSIGNOR:MATSUSHITA ELECTRIC WORKS, LTD.;REEL/FRAME:022206/0574Effective date: 20081001Owner name: PANASONIC ELECTRIC WORKS CO., LTD., JAPANFree format text: CHANGE OF NAME;ASSIGNOR:MATSUSHITA ELECTRIC WORKS, LTD.;REEL/FRAME:022206/0574Effective date: 20081001Jun 3, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services