Source: https://patents.google.com/patent/US20100225355A1/en
Timestamp: 2018-03-20 21:45:25
Document Index: 521453978

Matched Legal Cases: ['§120', '§120', '§120', '§120', '§120', '§119']

US20100225355A1 - Current-controlled CMOS logic family - Google Patents
US20100225355A1
US20100225355A1 US12784713 US78471310A US20100225355A1 US 20100225355 A1 US20100225355 A1 US 20100225355A1 US 12784713 US12784713 US 12784713 US 78471310 A US78471310 A US 78471310A US 20100225355 A1 US20100225355 A1 US 20100225355A1
US12784713
US9112487B2 (en )
1. U.S. Utility application Ser. No. 12/363,202, entitled “Current-controlled CMOS logic family,” (Attorney Docket No. BP1645C5), filed Jan. 30, 2009, pending, and scheduled to be issued as U.S. Pat. No. 7,724,057 on May 25, 2010, which claims priority pursuant to 35 U.S.C. §120, as a continuation, to the following U.S. Utility Patent Application which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility Patent Application for all purposes:
2. U.S. Utility application Ser. No. 11/729,679, entitled “Current-controlled CMOS logic family,” (Attorney Docket No. BP1645C4), filed Mar. 29, 2007, now U.S. Pat. No. 7,486,124 B2, issued on Feb. 3, 2009, which claims priority pursuant to 35 U.S.C. §120, as a continuation, to the following U.S. Utility Patent Application which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility Patent Application for all purposes:
3. U.S. Utility application Ser. No. 11/385,632, entitled “Current-controlled CMOS logic family,” (Attorney Docket No. BP1645C3), filed Mar. 21, 2006, now U.S. Pat. No. 7,215,169 B2, issued on May 8, 2007, which claims priority pursuant to 35 U.S.C. §120, as a continuation, to the following U.S. Utility Patent Application which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility Patent Application for all purposes:
4. U.S. Utility application Ser. No. 11/114,969, entitled “Current-controlled CMOS logic family,” (Attorney Docket No. BP1645C2), filed Apr. 26, 2005, now U.S. Pat. No. 7,038,516 B2, issued on May 2, 2006, which claims priority pursuant to 35 U.S.C. §120, as a continuation, to the following U.S. Utility Patent Application which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility Patent Application for all purposes:
5. U.S. Utility application Ser. No. 10/143,087, entitled “Current-controlled CMOS logic family,” (Attorney Docket No. BP1645C1), filed May 9, 2002, now U.S. Pat. No. 6,900,670 B2, issued on May 31, 2005, which claims priority pursuant to 35 U.S.C. §120, as a continuation, to the following U.S. Utility Patent Application which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility Patent Application for all purposes:
6. U.S. Utility application Ser. No. 09/484,856, entitled “Current-controlled CMOS logic family,” (Attorney Docket No. BP1645), filed Jan. 18, 2000, now U.S. Pat. No. 6,424,194 B1, issued on Jun. 23, 2002, which claims priority pursuant to 35 U.S.C. §119(e) to the following U.S. Provisional Patent Application which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility Patent Application for all purposes:
a circuit block, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C3MOS) logic, for serializing a plurality of signals thereby generating a serialized signal.
a CMOS logic block, within the circuit block, for providing at least one of the plurality of signals; and
a C3MOS logic block, within the circuit block, for receiving the plurality of signals and outputting the serialized signal.
a plurality of CMOS logic blocks, within the circuit block, for respectively providing the plurality of signals; and
each of the plurality of signals having a first frequency; and
the serialized signal having a second frequency.
the second frequency being greater than the first frequency.
the second frequency being an integer multiple of the first frequency.
the plurality of signals and the serialized signal being electrical signals including data compliant with a fiber channel.
the serialized signal being a differential signal.
the C3MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein:
the current source being coupled to at least one additional power supply.
current steering being performed within the current steering circuit in response to at least one of the plurality of signals, being a differential signal, being provided to the first gate and the second gate.
an input for receiving a serialized signal from a first stage; and
a second stage, including current-controlled complementary metal-oxide semiconductor (C3MOS) logic, for processing the serialized signal, wherein:
the first stage including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C3MOS) logic.
the first stage including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated.
the second stage deserializing the serialized signal thereby generating a deserialized signal including a plurality of signals.
a third stage, coupled to the second stage, for processing the deserialized signal thereby generating at least one additional deserialized signal that includes at least one additional plurality of signals.
the third stage including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated.
a fourth stage, coupled to the third stage, for serializing the at least one additional deserialized signal thereby generating at least one additional serialized signal.
the fourth stage including at least one additional C3MOS circuit having a third MOS transistor with a third drain, a third gate, and a third source and a fourth MOS transistor with a fourth drain, a fourth gate, and a fourth source, wherein:
at least one additional current steering circuit including the third source and the fourth source;
the third source and the fourth source being coupled together and to at least one additional current source; and
the serialized signal being an electrical signal including data compliant with a fiber channel.
29. The apparatus of claim 15, wherein:
an input for receiving a serialized signal from a first stage including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated; and
the first drain and the second drain being coupled to a power supply; and wherein:
US12784713 1999-06-28 2010-05-21 Current-controlled CMOS logic family Active 2022-01-16 US9112487B2 (en)
US12363202 Continuation US7724057B2 (en) 1999-06-28 2009-01-30 Current-controlled CMOS logic family
US14826557 Continuation US9831853B2 (en) 1999-06-28 2015-08-14 Current-controlled CMOS logic family
US20100225355A1 true true US20100225355A1 (en) 2010-09-09
US9112487B2 US9112487B2 (en) 2015-08-18