Source: http://www.google.com/patents/US7960833?dq=6,712,702
Timestamp: 2017-07-27 18:00:38
Document Index: 194456889

Matched Legal Cases: ['Application No. 60', 'Application No. 050002849', 'Application No. 06011395', 'Application No. 06011396', 'Application No. 04', 'Application No. 04', 'Application No. 05', 'Application No. 2005', 'Application No. 2007', 'Application No. 2005', 'Application No. 06', 'Application No. 06', 'Application No. 2004']

Patent US7960833 - Integrated circuits and interconnect structure for integrated circuits - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn integrated circuit comprises N plane-like metal layers, where N is an integer greater than one. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively, where M is an integer greater than one. The first plane-like metal layer and...http://www.google.com/patents/US7960833?utm_source=gb-gplus-sharePatent US7960833 - Integrated circuits and interconnect structure for integrated circuitsAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7960833 B2Publication typeGrantApplication numberUS 12/049,533Publication dateJun 14, 2011Filing dateMar 17, 2008Priority dateOct 22, 2003Fee statusPaidAlso published asUS7982280, US7989852, US8026550, US20080157209, US20080237649, US20080258240, US20080258241Publication number049533, 12049533, US 7960833 B2, US 7960833B2, US-B2-7960833, US7960833 B2, US7960833B2InventorsSehat SutardjaOriginal AssigneeMarvell World Trade Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (69), Non-Patent Citations (17), Classifications (53), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetIntegrated circuits and interconnect structure for integrated circuits
US 7960833 B2Abstract
An integrated circuit comprises N plane-like metal layers, where N is an integer greater than one. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively, where M is an integer greater than one. The first plane-like metal layer and the N plane-like metal layers are located in separate planes. At least two of a first source, a first drain and a second source communicate with at least two of the N plane-like metal layers. A first gate is arranged between the first source and the first drain. A second gate is arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions.
wherein first and second ones of the M contact portions are generally “C”-shaped and wherein a third one of the M contact portions is arranged between the first and second ones of the M contact portions.
This application claims the benefit of U.S. Provisional Application No. 60/895,022, filed Mar. 15, 2007, and is a continuation-in-part of U.S. patent application Ser. No. 11/386,276 filed on Mar. 22, 2006, which is a divisional of U.S. patent application Ser. No. 10/765,474 filed on Jan. 26, 2004. This application is also a continuation in part of U.S. patent application Ser. No. 11/524,113 filed on Sep. 20, 2006, which claims the benefit of U.S. Provisional Application Nos. 60/825,517, filed Sep. 13, 2006, 60/824,357, filed Sep. 1, 2006, 60/823,332, filed on Aug. 23, 2006, 60/821,008, filed Aug. 1, 2006 and 60/798,568, filed on May 8, 2006 and is a continuation-in-part of U.S. patent application Ser. No. 11/252,010 filed on Oct. 17, 2005, which is a continuation of U.S. patent application Ser. No. 10/691,237 filed on Oct. 22, 2003. The disclosures of the above applications are incorporated herein by reference in their entirety.
The present invention relates to integrated circuits, and more particularly to integrated circuits and interconnect structures for integrated circuits.
Power integrated circuits (ICs) or power ICs may be used to supply power in variety of different applications. For example, power ICs may be used to supply power in pulse width modulation circuits. A drive IC may be used to provide input voltages and control signals to the power IC. Therefore, the drive IC and the power IC must be connected together. However, the drive IC and the power IC may be implemented using different IC technology. For example, the power IC may be implemented using MOSFET technology and the drive IC may employ standard IC technology. Therefore, packaging of the power IC and the drive IC may be problematic.
An integrated circuit comprises N plane-like metal layers, where N is an integer greater than one. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively, where M is an integer greater than one. The first plane-like metal layer and the N plane-like metal layers are located in separate planes. At least two of a first source, a first drain and a second source communicate with at least two of the N plane-like metal layers. A first gate is arranged between the first source and the first drain. A second gate is arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the first drain. The first and second gates are arranged farther apart in the first regions than in the second regions.
In other features, at least two of the N plane-like metal layers are coplanar. The N plane-like metal layers are located in separate planes. A plurality of local interconnects communicate with the first and second sources and the first drain. At least one of the M contact portions has an elliptical shape. First and second ones of the M contact portions have a base portion and wings that extend from the base portion. A third one of the M contact portions is received between the wings of the first and second ones of the M contact portions. First and second ones of the M contact portions are generally “C”-shaped. A third one of the M contact portions is arranged between the first and second ones of the M contact portions.
In other features, first and second ones of the M contact portions have a base portion and wings that extend from the base portion, and a third one of the M contact portions is received between the wings of the first and second ones of the M contact portions. First and second ones of the M contact portions are generally “C”-shaped. A third one of the M contact portions is arranged between the first and second ones of the M contact portions.
In other features, at least two of the N plane-like metal layers are coplanar. The N plane-like metal layers are located in separate planes. A plurality of local interconnects communicate with the first, second, third and fourth source regions and the first drain region. At least one of the M contact portions has an elliptical shape. The first, second, third and fourth source regions communicate with a first one of the N plane-like metal layers and the first drain region communicates with a second one of the N plane-like metal layers. First and second ones of the M contact portions have a base portion and wings that extend from the base portion, and a third one of the M contact portions is received between the wings of the first and second ones of the M contact portions. First and second ones of the M contact portions are generally “C”-shaped. A third one of the M contact portions is arranged between the first and second ones of the M contact portions.
In other features, the method includes arranging at least two of the N plane-like metal layers in the same plane. The method includes arranging the N plane-like metal layers in separate planes. The method includes providing a plurality of local interconnects that communicate with the first, second, third and fourth source regions and the first drain region. At least one of the M contact portions has an elliptical shape. The first, second, third and fourth source regions communicate with a first one of the N plane-like metal layers and the first drain region communicates with a second one of the N plane-like metal layers. First and second ones of the M contact portions have a base portion and wings that extend from the base portion, and a third one of the M contact portions is received between the wings of the first and second ones of the M contact portions. First and second ones of the M contact portions are generally “C”-shaped and wherein a third one of the M contact portions is arranged between the first and second ones of the M contact portions.
In other features, first and second ones of the M contact portions are generally “C”-shaped. A third one of the M contact portions is arranged between the first and second ones of the M contact portions. The integrated circuit implements a power IC, a first one of the M contact portions supplies a first voltage potential to the power IC, a second one of the M contact portions supplies a second voltage potential to the power IC and a third one of the M contact portions receives an output voltage of the power IC.
In other features, first and second ones of the M contact portions have a base portion and wings that extend from the base portion, and a third one of the M contact portions is received between the wings of the first and second ones of the M contact portions. First and second ones of the M contact portions are generally “C”-shaped and wherein a third one of the M contact portions is arranged between the first and second ones of the M contact portions.
In other features, the first and second drain regions and the first, second and third source regions are arranged in a first row and further comprising N additional rows. Drain regions of at least one of the N additional rows share one of the fourth and fifth source regions. At least two of the N plane-like metal layers are coplanar. The N plane-like metal layers are located in separate planes. A plurality of local interconnects communicate with the first, second, third, fourth and fifth source regions and the first and second drain regions. At least one of the M contact portions has an elliptical shape. First and second ones of the M contact portions have a base portion and wings that extend from the base portion, and a third one of the M contact portions is received between the wings of the first and second ones of the M contact portions. First and second ones of the M contact portions are generally “C”-shaped and wherein a third one of the M contact portions is arranged between the first and second ones of the M contact portions.
In other features, the method includes arranging the first and second drain regions and the first, second and third source regions in a first row; and providing N additional rows, wherein drain regions of at least one of the N additional rows share one of the fourth and fifth source regions. The method includes arranging at least two of the N plane-like metal layers in the same plane. The method includes arranging the N plane-like metal layers in separate planes. The method includes providing a plurality of local interconnects that communicate with the first, second, third, fourth and fifth source regions and the first and second drain regions. At least one of the M contact portions has an elliptical shape. First and second ones of the M contact portions have a base portion and wings that extend from the base portion, and a third one of the M contact portions is received between the wings of the first and second ones of the M contact portions. First and second ones of the M contact portions are generally “C”-shaped and wherein a third one of the M contact portions is arranged between the first and second ones of the M contact portions.
The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein.
Referring now to FIG. 10, an exemplary implementation of the metal layer 242 is shown in further detail. The metal layer 242 includes a first plane-like conducting portion 320 that is in electrical contact with the set of vias 308. The metal layer 254 includes a second plane-like conducting portion 324 that is in electrical contact with the set of vias 304. The metal layer 254 includes a third plane-like conducting portion 326 that is in electrical contact with the set of vias 306. The metal layer 254 includes an additional plane-like conducting portions 330-1, 330-2, 330-3, . . . , 330-8 that are in electrical contact with the vias 310-1, 310-2, 310-3, . . . , 310-8. In a preferred embodiment, the additional plane-like conducting portions 330 are generally pear-shaped, although other shapes maybe used. As used herein, the term “generally” means approximately and may include rounding of corners and other variations from the shape. The plane-like conducting portions in FIG. 10 are electrically isolated from each other.
Referring now to FIG. 16, the alignment and orientation of the dielectric layer 374 (on top) and the metal layer 370 (on bottom) is shown. The alignment and orientation is similar to the dielectric layer 244 and the metal layer 242 that are shown in FIG. 12. Since the dielectric layers 244 and 374 are similar, the same reference numerals are used followed by “′”. A similar approach will be used for the metal layers 242 and 370.
In FIG. 20, Vdd is associated with a first outer contact portion 412, which has a generally “C”-shaped configuration. Vss is associated with a second outer contact portion 414, which also has generally “C”-shaped configuration. A middle contact portion 418 is located between the first and the second outer contact portions 412 and 414, respectively. One or more additional contact portions 419 may be arranged along one or more sides or ends of the buildup layer 250 and/or between contact portions 412 and 414 to accommodate control signals, such as gate control signals.
Referring now to FIG. 22, a decoupling capacitor 440 can be attached to the interconnect structure 236 between Vdd and Vss in addition to an IC 444, which is mounted on the metal buildup layer 250 of the interconnect structure 236. The decoupling capacitor 440 includes first and second conducting plates 450 and 452 that are separated by an insulating material 456. The plates 450 and 452 are connected by conductive arms 460 and 462, respectively, to the interconnect structure 236. In one implementation, the conductive arms 460 and 462 are connected to Vdd and Vss. Ends of the arms 460 and 462 are connected to the buildup layer 250 of the interconnect structure 236. Since the buildup layer 250 is relatively thin, it has a relatively high impedance. In one embodiment, the arms 460 and 462 have a generally “L”-shaped configuration.
Groups of transistors 1230-11, 1230-12, . . . , and 1230-55 (collectively groups of transistors 1230) are arranged adjacent to each other. While a 5×5 array is shown, an X by Y array may be used, where X and Y are integers greater than one. Adjacent groups of transistors 1230 share R N-well contacts 1260, where R is an integer greater than one. The R N-well contacts 1260 can be located between the adjacent groups of transistors 1230 in regions 1210 where the gates 1200 are spaced further apart.
Each of the drain regions 1306 may have an area that is greater than or equal to two times the area of each of the source regions 1304. In FIG. 41A, the drain regions 1306 have a width “b” and a height “a”. The source regions 1304 have a width (or height) “d” and a height (or width) “c”. The drain regions 1306 may have substantially the same length as the source regions 1304. The drain regions 1306 may have greater than or equal to two times the width of the source regions 1304.
In some implementations, the substrate contacts 1347-11, 1347-12, 1347-21, 1347-22, 1347-23, . . . may be arranged in some, none or all of the second areas 1345-B1, 1345-B2, 1345-B3 and 1345-B4 of the source regions 1344-1, 1344-2, . . . and 1344-R, for example as shown in FIG. 41D. The substrate contacts 1347-11, 1347-12, 1347-21, 1347-22, 1347-23, . . . are shown arranged in the elongated substrate regions 1344-1 and 1344-2 and tend to lower RDS_ON. The substrate contacts 1347-11, 1347-12, 1347-21, 1347-22, 1347-23, . . . may have a height that is less than or equal to a width “c” of the source regions 1304 (as shown in FIG. 41A) and a width that is less than or equal to a width “d” of the source regions 1304 (as shown in FIG. 41A).
Referring now to FIGS. 42-44, transistor layouts 1347-1, 1347-2 and 1347-3 (collectively 1347), respectively, are shown. Drain, source and gate regions can have other shapes that can be used to minimize RDSON. For example, drain regions 1348 can have a circular shape as shown in the transistor layout 1347-1 in FIG. 42, an elliptical shape as shown in the transistor layout 1347-2 of FIG. 43 and/or other suitable shapes. Gate regions 1349 include circular-shaped gate regions 1350 that are connected by linear gate connecting regions 1352. Similar elements are identified in FIG. 43 using a prime symbol (“′”). The drain regions 1348 are located in the circular-shaped gate regions 1350. Source regions 1360 are located in between the gate regions 1349 in areas other than the inside of the circular shaped gate regions 1350. Substrate contacts 1364 are located in the source regions 1360. The drain regions 1348 may also include a contact region 1366. The linear gate regions 1352 may have a vertical spacing “g” that is minimized to increase density. Likewise, lateral spacing identified at “f” between adjacent circular-shaped gate regions 1350 may be minimized to increase density.
Drain regions 1368 can also have polygon shapes. For example, the drain regions can have a hexagon shape as shown in the transistor layout 1347-3 of FIG. 44, although other polygon shapes can be used. Gate regions 1369 include hexagon-shaped gate regions 1370 that are connected by linear gate connecting regions 1372. The drain regions 1368 are located in the hexagon-shaped gate regions 1370. Source regions 1380 are located in between the gate regions 1369 in areas other than the inside of the hexagon-shaped gate regions 1370. Substrate contacts 1384 are located in the source regions 1380. The drain regions may also include a contact region 1386. The linear gate connecting regions 1372 preferably have a vertical spacing “j” that is minimized to increase density. Likewise lateral spacing identified at “i” between adjacent hexagon-shaped gate regions 1370 is minimized to increase density.
The HDD PCB 1502 includes a read/write channel module (hereinafter, “read channel”) 1509, a hard disk controller (HDC) module 1510, a buffer 1511, nonvolatile memory 1512, a processor 1513, and a spindle/VCM driver module 1514. The read channel 1509 processes data received from and transmitted to the preamplifier device 1508. The HDC module 1510 controls components of the HDA 1501 and communicates with an external device (not shown) via an I/O interface 1515. The external device may include a computer, a multimedia device, a mobile computing device, etc. The I/O interface 1515 may include wireline and/or wireless communication links.
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