Source: http://www.google.com/patents/US7863880?dq=5,779,924
Timestamp: 2017-09-24 02:38:57
Document Index: 729673199

Matched Legal Cases: ['Application No. 04023251', 'Application No. 04023259', 'Application No. 04023192', 'Application No. 04023249', 'Application No. 04023234', 'Application No. 04023247', 'Application No. 04023256', 'Application No. 04023257', 'Application No. 04023258', 'Application No. 03763431', 'Application No. 04023256', 'Application No. 200410088916', 'Application No. 200410088920', 'Application No. 03805465', 'Application No. 200410088921', 'Application No. 200410088922', 'Application No. 200410088917', 'Application No. 200410088923', 'Application No. 200410088924', 'Application No. 200410088924', 'Application No. 200410088918', 'Application No. 2005', 'Application No. 03805465', 'Application No. 200410088921', 'Application No. 200410088922', 'Application No. 200410088917', 'Application No. 200410088923', 'Application No. 200410088924', 'Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 2004', 'Application No. 2004', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 03805465', 'Application No. 200410088923', 'Application No. 200410088922']

Patent US7863880 - Adaptive control loop - Google Patents
A controller comprises a duty cycle estimator to determine a nominal duty cycle. An adjustment determiner determines an adjustment value to combine with the nominal duty cycle to generate an adjusted duty cycle. A pulse width adjuster varies a pulse width signal based on the adjusted duty cycle. Transfer...http://www.google.com/patents/US7863880?utm_source=gb-gplus-sharePatent US7863880 - Adaptive control loop
Publication number US7863880 B1
Application number US 12/082,825
Also published as CN1603998A, CN1603999A, CN1604000A, CN1604001A, CN1604001B, CN1604002A, CN1604445A, CN1607716A, CN1607717A, CN1639659A, CN1664737A, CN100380798C, CN100392551C, CN100392552C, CN100392971C, CN100407086C, CN100416442C, CN100416998C, CN100440097C, CN100440098C, DE60323498D1, DE60323499D1, DE60323501D1, DE60324148D1, DE60334102D1, DE60336816D1, DE60336817D1, DE60336818D1, DE60337012D1, EP1532501A2, EP1532501B1, US6894465, US6933711, US6977492, US6979988, US7009372, US7023192, US7042202, US7053594, US7358711, US7368898, US7411377, US7573249, US7609043, US7622904, US20040008016, US20040155640, US20040178785, US20040183510, US20040196015, US20040196016, US20040196017, US20040196018, US20040239300, US20050156581, US20060022657, US20080030176, US20080030182, US20080186014, WO2004006037A2, WO2004006037A3
Publication number 082825, 12082825, US 7863880 B1, US 7863880B1, US-B1-7863880, US7863880 B1, US7863880B1
Patent Citations (106), Non-Patent Citations (80), Referenced by (3), Classifications (33), Legal Events (1)
US 7863880 B1
A controller comprises a duty cycle estimator to determine a nominal duty cycle. An adjustment determiner determines an adjustment value to combine with the nominal duty cycle to generate an adjusted duty cycle. A pulse width adjuster varies a pulse width signal based on the adjusted duty cycle. Transfer of energy between an input and a regulated output is based on the pulse width signal.
a duty cycle estimator to determine a nominal duty cycle;
an adjustment determiner to determine an adjustment value to combine with the nominal duty cycle to generate an adjusted duty cycle; and
a pulse width adjuster to vary a pulse width signal based on the adjusted duty cycle;
wherein transfer of energy between an input and an output of an output regulator is based on the pulse width signal.
2. The controller of claim 1 wherein the adjustment determiner includes a selectable loop gain for determining the adjustment value.
3. The controller of claim 2 wherein the selectable loop gain is adjustable at a rate greater than a switching frequency of the output regulator.
4. The controller of claim 2 wherein the selectable loop gain is controlled based on a regulator parameter of the output regulator.
5. The controller of claim 4 wherein the regulator parameter is selected from a group consisting of a voltage range of an error signal corresponding to the output, a voltage range of the output, the nominal duty cycle, and the adjusted duty cycle.
6. The controller of claim 1 further comprising a counter to generate an initial pulse width based on the adjusted duty cycle.
7. The controller of claim 6 further comprising a controller to generate a delay control signal as a function of the nominal duty cycle and the initial pulse width.
8. The controller of claim 7 further comprising a delay line to generate the pulse width signal having an adjusted pulse width based on the initial pulse width and the delay control signal.
9. The controller of claim 8 further comprising a duty cycle limiter to limit the adjusted duty cycle as a function of a regulator characteristic.
10. The controller of claim 9 wherein the duty cycle limiter operates on the adjusted pulse width.
11. The controller of claim 1 wherein the pulse width signal has a variable frequency.
12. The controller of claim 1 wherein the adjustment determiner includes a loop compensator to stabilize a loop response of the output regulator using loop compensation.
13. The controller of claim 12 wherein the loop compensation is controllable at a rate ranging from a switching frequency of the output regulator to a sampling frequency of the controller.
14. The controller of claim 12 wherein the loop compensator varies a ratio of an error portion and a trend portion of the loop compensation.
15. The controller of claim 1 wherein the adjustment value is based on an estimated trend of an error and wherein the error is based on a difference between a reference and the output.
16. The controller of claim 15 wherein the estimated trend of the error is based on a mathematical function of the error, wherein the mathematical function is selected from a group consisting of a running average, a mean, a peak value, and a weighted average.
17. The controller of claim 1 wherein the adjustment value is based on a predetermined slope constant.
18. The controller of claim 1 wherein the adjustment value is based on a slope constant that is adjustable at a rate greater than a switching frequency of the output regulator.
19. The controller of claim 1 wherein the adjustment value is based on an error history of an error, wherein the error is based on a difference between a reference and the output.
20. The controller of claim 19 wherein the error history is based on a mathematical function of prior values of the error, wherein the mathematical function is selected from a group consisting of a running average, a mean, a peak value, and a weighted average.
This application is a continuation of U.S. patent application Ser. No. 10/827,634, filed Apr. 19, 2004, which application is a divisional of U.S. patent application Ser. No. 10/460,825, filed Jun. 12, 2003 which claims the benefit of the filing date of U.S. provisional application Nos. 60/395,115 filed Jul. 10, 2002, and 60/395,697 filed Jul. 12, 2002, the entire contents of which are herein incorporated by reference.
FIG. 1 shows a power regulator 10 for supplying regulated power to a load 12. The power regulator 10 may include a digital controller 14 to receive a feedback signal 16 and to generate one or more control signals 18 to drive a power stage 20. The power stage 20 converts an unregulated voltage, such as Vin 22, to a chopped waveform that is filtered by an output filter 24 to generate a regulated output 26. The regulated output 26 is preferably a direct current (DC) output and may be any output characteristic including voltage, current, and power. The unregulated voltage may be any form of input power such as alternating current (AC) voltage and DC voltage. For an AC input voltage a rectification stage (not shown) may be included to convert the AC voltage to the DC input voltage, Vin, 22. An output sensor 28 senses the regulated output 26 and sends the feedback signal to the digital controller 14. The power regulator 10 may employ any topology such as buck, boost, flyback (buck-boost), Cuk, .Sepic, and Zeta.
A delay line 120 may finetune the estimated duty cycle computed by the digital controller 102. The delay line 120 may generate a delay signal to lengthen the estimated duty cycle. For example, the estimated duty cycle may be computed as an integer multiple of a clock pulse width and the delay line 120 may vary the estimated duty cycle by increments that are less than the clock pulse width. The delay line 120 may receive a digital signal of one or more bits such as a multibit digital signal, and generate a pulse with a controlled pulse width. Any type of pulse stretching technique may be employed. In addition, the delay line 120 may include dithering to generate fractional increments. In an exemplary system, delay line 120 may generate a minimum increment resolution that is equal to “ti”, and by applying dithering, the average of the generated pulse may be pulse stretched by any fractional portion of “ti”. In one dithering method, a selected number of pulses within the continuing series of pulses may be stretched by an integer “N” number of increments, and the remaining pulses in the series of pulses may be stretched by an integer “N−1” or “N+I” number of increments to generate a pulse that is fractionally stretched.
A driver array 505 buffers drive signals from a switch controller 504 to the power switches QI-Q8. The driver array 505 may include several drivers 506. Each of the drivers 506 preferably drives a single power switch, however each driver 506 may drive more than one of the power switches QI-Q8. The drivers 506 improve the switching speed of the power switches Q1-Q8 to reduce switching losses as the power switches transition between the on state and off state. Any type of circuits and devices may be used for the drivers 506 to improve the switching speed of the power switches Q1-Q8.
FIG. 21 shows an aspect of an operation for suppressing the generation of noise by a power stage of a power regulator. The power stage may include at least two ° switch arrays having a common node, step 750. The switch arrays may be arranged in any topology such as buck, boost, sepic, and zeta. Each of the switch arrays may include one or more power switches connected in parallel and individually controlled so that the quantity of switches that conduct within each switch array may be controlled on a cycle-by-cycle basis. The power switches are preferably MOSFETs, however any type of power switch having a variable output capacitance may be used such as BJTs, IGBTs, and MCTs. Controlling the quantity of power switches that conduct within each switch array causes the impedance of the common node to be controlled. An exemplary operation may include an upper switch array and a lower switch array connected in a buck configuration where the upper switch array operates during a conduction phase and the lower switch array operates during a free-wheeling phase. At step 752, a noise characteristic of the common node, such as voltage and current, may be monitored. At step 754, the noise characteristic may be compared to one or more reference levels to generate an impedance control signal. At step 756, the switch arrays may be controlled in response to the impedance control signal. For example, an upper switch array having four power switches in parallel may be operated so that the four power switches are sequentially turned-off one-by-one so that the impedance of the common node may change from a low impedance to a high impedance over a controlled time period, thereby damping noise spikes occurring during the switch transition.
ADJK =G(ek)+h(trendk)
g ( e k ) = { 0 if  e k  < A 1 sign ( e k ) * Δ if A 1 ≤  e k  < A 2 sign ( e k ) * Δ if A 2 ≤  e k  < A 3
h ( trend k ) = { 0 if  trend k  < 1 trend k if trend k  ≥ 1 trend k = F slope * e k - e k - n
Where Fslope is a constant,
e k - e k - n _
is an average of the error from the “n” prior cycles where “n” is the number of samples in a switching period, and AI, A2, and A3 are defined in FIG. 29 which shows voltage levels of a voltage slicer for generating the error signal.
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JPH0549252A Title not available
JPH09140126A Title not available
JPH09149637A Title not available
WO2002019507A Title not available
WO2003001314A Title not available
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International Classification G05F1/56, H02M3/335, G05F1/40, H02M1/12, H02M1/088, H02M3/155, H02M3/137, G05F1/575, H02M3/158
Cooperative Classification H02M2001/0009, H02M2001/0048, Y02B70/1491, H02M1/38, H03K17/167, Y02B70/1466, H02M1/088, H02M3/158, H02M3/1588, H03K17/122, H02M2001/0012, H02M3/157, H03K5/1565, H02M2001/0025, H03K17/6871
European Classification H02M3/158S, H02M1/088, H02M3/158, H03K17/12B, H02M3/157, H03K17/16B4B2, H03K5/156D, H02M1/38