Source: http://www.google.com/patents/US7565738?dq=7,013,345/
Timestamp: 2016-10-28 12:29:00
Document Index: 257026024

Matched Legal Cases: ['art 25', 'art 25', 'art 25', 'art 25', 'art 65', 'art 65']

Patent US7565738 - Method for manufacturing circuit device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating...http://www.google.com/patents/US7565738?utm_source=gb-gplus-sharePatent US7565738 - Method for manufacturing circuit deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7565738 B2Publication typeGrantApplication numberUS 11/138,932Publication dateJul 28, 2009Filing dateMay 25, 2005Priority dateMay 31, 2004Fee statusPaidAlso published asUS7854062, US20050263905, US20090119915Publication number11138932, 138932, US 7565738 B2, US 7565738B2, US-B2-7565738, US7565738 B2, US7565738B2InventorsRyosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Nobuhisa Takakusaki, Hayato AbeOriginal AssigneeSanyo Electric Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (11), Classifications (80), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethod for manufacturing circuit device
US 7565738 B2Abstract
A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.
The present invention was made in consideration for the foregoing problems. The main object of the present invention is to provide a method for manufacturing a circuit device which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer.
FIGS. 1A to 1C are cross-sectional views showing a hybrid integrated circuit device of the preferred embodiment of the present invention.
In this embodiment, a description will be given of a method for manufacturing a hybrid integrated circuit device as an example of a circuit device.
First, with reference to FIG. 5A, a first insulating layer 17A is applied onto the surface of a circuit board 16, and a first conductive film 28A is laminated thereon. As the circuit board 16, a metal plate having a thickness of about 1.5 mm can be used. Moreover, as the first conductive film 28A, a material mainly made of copper or a material mainly made of Fe—Ni or Al can be used. For a thickness of the first conductive film 28A, more than a thickness obtained by adding a thickness of a wiring layer 18 to be formed and a height of a first connection part 25A is required. To be more specific, the thickness of the first conductive film 28A is, for example, about 20 μm to 150 μm. A resist 29A covers the surface of the first conductive film 28A in a region where the first connection part 25A will be formed. In a state where the resist 29A covers the surface, etching is performed. Moreover, as the first insulating layer 17A, one obtained by mixing inorganic fillers in an insulating resin such as an epoxy resin can be used. Here, as the inorganic fillers to be mixed in, SiO2, Al2O3, SiC, AlN, or the like can be used.
With reference to FIG. 11B, next, a description will be given of another method for forming the second connection part 25B. Here, a canopy top 13 is provided in a peripheral portion of the through-hole 32. Thus, the second connection part 25B is easily formed by electrolytic plating. Here, the “canopy top” means a part which is formed of the second conductive film 28B and is protruded so as to cover the peripheral portion of the through-hole 32. A specific method for forming the canopy top 13 can be performed by increasing output of a laser when the through-hole 32 is formed by use of the laser. By increasing the output of the laser, removal of the second resin film 17B2 by use of the laser is advanced horizontally, and the resin below the canopy top 13 is removed. Under the conditions described above, electrolytic plating is performed by use of the second conductive film 28B as the cathode electrode. Accordingly, the plated film is grown preferentially from the canopy top 13. Since the plated film is grown from the canopy top 13, the plated film can be grown preferentially downward compared to the case of FIG. 11A. Therefore, it is possible to surely fill the through-hole 32 with the plated film.
In this embodiment, a description will be given of a circuit device as shown in FIGS. 15A to 15C and the like as an example of a circuit device.
In this embodiment, a description will be given of a method for manufacturing a circuit device 50 described above as an example.
First, with reference to FIG. 17A, a first conductive film 68A is prepared. As the first conductive film 68A, a material mainly made of copper or a material mainly made of Fe—Ni or Al can be used. For a thickness of the first conductive film 68A, more than a thickness obtained by adding a thickness of a wiring layer 58 to be formed and a height of a first connection part 65A is required. To be more specific, the thickness of the first conductive film 68A is, for example, about 20 μm to 150 μm. A resist 69 covers the surface of the first conductive film 68A in a region where the first connection part 65A will be formed. In a state where the resist 69 covers the surface, etching is performed.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4372804 *Apr 2, 1981Feb 8, 1983Fujitsu LimitedMethod for making multilayer printed wiring boardUS6010768 *May 12, 1997Jan 4, 2000Ibiden Co., Ltd.Multilayer printed circuit board, method of producing multilayer printed circuit board and resin fillerUS6432748 *Sep 24, 2001Aug 13, 2002Phoenix Precision Technology Corp.Substrate structure for semiconductor package and manufacturing method thereofUS6912779 *Aug 22, 2003Jul 5, 2005Sony Chemicals Corp.Method of manufacturing flexible wiring boardUS20060001166 *Jun 24, 2005Jan 5, 2006Yusuke IgarashiCircuit device and manufacturing method thereofJP2001339151A Title not availableJP2002185097A Title not availableJP2004063722A Title not availableJP2004140176A Title not availableJPH06177295A Title not availableJPH09321432A Title not available* Cited by examinerClassifications U.S. Classification29/852, 174/262, 29/847, 29/830International ClassificationH05K1/02, H05K3/28, H01K3/10, H01L25/16, H05K3/42, H01L21/48, H05K1/05, H01L23/498, H01L23/48, H05K3/00, H05K3/46, H01L23/31, H01L23/538Cooperative ClassificationH01L2924/181, H01L2924/14, H01L24/73, H01L2924/12042, H01L2924/351, Y10T29/49126, Y10T29/49165, Y10T29/49156, H01L2924/1301, H01L2924/07802, H01L2924/01079, H05K3/4652, H05K2201/09563, H01L25/165, H01L2924/01046, H01L23/5383, H01L2224/48227, H05K2201/0195, H01L23/3121, H01L2924/01019, H05K2201/09509, H01L2924/0103, H05K3/423, H05K1/056, H01L2924/01078, H05K2203/0369, H05K3/4647, H05K2201/09881, H01L2924/01013, H05K3/421, H01L2224/48465, H01L23/49822, H01L24/97, H01L2924/01047, H05K2203/1476, H01L2924/0102, H01L23/49827, H01L2924/15311, H01L2224/32225, H05K2203/0554, H01L2224/48472, H01L2924/01082, H01L2224/48091, H01L2924/01033, H01L2224/97, H05K2201/0209, H01L25/16, H01L21/486, H05K1/0206, H01L2924/19105, H01L2924/01012, H05K3/284, H05K3/4655, H01L2924/01029, H05K3/0035, H05K2201/096, H01L2224/73265, H01L2924/13055European ClassificationH05K3/46C4B, H01L24/97, H05K3/46C2, H05K3/42B, H01L21/48C4ELegal EventsDateCodeEventDescriptionMay 25, 2005ASAssignmentOwner name: SANYO ELECTRIC CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:USUI, RYOSUKE;MIZUHARA, HIDEKI;IGARASHI, YUSUKE;AND OTHERS;REEL/FRAME:016620/0921Effective date: 20050513Oct 2, 2012FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services