Source: https://patents.google.com/patent/US6492737B1/en
Timestamp: 2019-09-20 12:09:36
Document Index: 58142080

Matched Legal Cases: ['arts 5', 'arts 5', 'arts 5', 'arts 5', 'art 5', 'art 5', 'art 5', 'art 5', 'art 5', 'arts 6']

US6492737B1 - Electronic device and a method of manufacturing the same - Google Patents
Electronic device and a method of manufacturing the same Download PDF
US6492737B1
US6492737B1 US09/921,919 US92191901A US6492737B1 US 6492737 B1 US6492737 B1 US 6492737B1 US 92191901 A US92191901 A US 92191901A US 6492737 B1 US6492737 B1 US 6492737B1
US09/921,919
2000-08-31 Priority to JP2000262511A priority Critical patent/JP3822040B2/en
2000-08-31 Priority to JP2000-262511 priority
2001-08-06 Assigned to HITACHI, LTD. reassignment HITACHI, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KADO, YOSHIYUKI, KISHIKAWA, NORIO, NAITO, TAKAHIRO, SATO, TOSHIHIKO, TAGUCHI, KAZUYUKI, IMASU, SATOSHI, YOSHIDA, IKUO
2002-12-10 Publication of US6492737B1 publication Critical patent/US6492737B1/en
The stud bumps 11 are connected in the opening 9 a formed in the insulating film 9 to the connection parts 5 a disposed in the bottom of the opening 9 a. That is, the stud bumps 11 are connected to the connection parts 5 a which are disposed at a deeper position than one main surface 2X of the wiring board 2 in the depth direction from one main surface 2X. By thus disposing the connection parts 5 a at a position deeper than the one main surface 2X of the wiring board 2, the volume of the anisotropic conductive resin 20 between one main surface 2X of the wiring board 2 and the circuit-formed surface 10X of the buffer chip 10 can be diminished by an amount corresponding to the depth from one main surface 2X to the connection parts 5 a.
The recess of each connection part 5 a is formed by an elastic deformation of the connection part 5 a and the soft layer 4. The recess thus based on such an elastic deformation can be formed with a compression-bonding force used at the time of mounting the buffer chip 10 onto one main surface of the wiring board 2. In case of forming the recess by an elastic deformation of each connection part 5 a and the soft layer 4, an elastic force of the connection part 5 a and the soft layer 4 acts on the associated stud bump 11, so that the compression-bonding force between the stud bump 11 and the connection part 5 a increases.
The stud bumps 13 used in this embodiment are of a two-stage bump structure to increase their height, but according to the depth from one main surface 2X of the wiring board 2 to the connection parts 6 a and a plane size of each electrode pad 12 a, there may be adopted such a three-stage bump structure as shown in FIG. 17 wherein a stud bump 13 comprises a base bump 13 a connected to an electrode pad 12 a, a stack bump 13 b stacked on the base bump 13 a, and a stack bump 13 c stacked on the stack bump 13 b.
Although in the two-stage bump structure adopted in this embodiment the base bump 13 a and the stack bump 13 b are almost equal in diameter, there may be adopted such a two-stage bump structure as shown in FIG. 18 which uses a stud bump 13 comprising a base bump 13 a and a stack bump 13 b different in diameter. In this case, by using Au wires of different diameters at the time of forming stud bumps in accordance with the ball bonding method there can be obtained a base bump 13 a and a stack bump 13 b different in diameter.
a first semiconductor chip having a plurality of first electrode pads arranged at a first array pitch on one main surface of the chip;
a second semiconductor chip having a plurality of second electrode pads arranged at a second array pitch smaller than the first array pitch on one main surface of the chip;
a wiring board having in a first area of a surface thereof a plurality of first connection parts arranged correspondingly to the plural first electrode pads and in a second area of said surface thereof different from the first area a plurality of second connection parts arranged correspondingly to the plural second electrode pads;
a plurality of first salient electrodes disposed respectively between the first electrode pads and the first connection parts and providing electric connections between the two; and
a plurality of second salient electrodes disposed respectively between the second electrode pads and the second connection parts and providing electric connections between the two;
the plural first connection parts and the plural second connection parts being disposed at a deeper position than one main surface of the wiring board in a depth direction from said one main surface of the wiring board, and
the plural second salient electrodes being of a multi-stage bump structure having a larger number of stages than the plural first salient electrodes.
2. An electronic device according to claim 1, wherein the wiring board has an insulating film providing said one main surface of said wiring board, a first opening formed in the insulating film in a first area of said one main surface of said wiring board, and a second opening formed in the insulating film in a second area of said one main surface of said wiring board, the plural first connection parts are disposed in a bottom of the first opening, and the plural second connection parts are disposed in a bottom of the second opening.
a first semiconductor chip having a first electrode pad on one main surface thereof;
a second semiconductor chip having a second electrode pad on one main surface thereof, the second electrode pad having a plane area smaller than that of the first electrode pad;
a wiring board having: an insulating film; a first opening formed in the insulating film in a first area; a second opening formed in the insulating film in a second area different from the first area; a first connection part disposed in a bottom of the first opening; and a second connection part disposed in a bottom of the second opening;
a first salient electrode disposed between the first electrode pad and the first connection part to provide an electrical connection between the two; and
a second salient electrode disposed between the second electrode pad and the second connection part to provide an electrical connection between the two,
wherein the second salient electrode has a multi-stage bump structure larger in the number of stages than the first salient electrode.
a plurality of salient electrodes arranged on one main surface of the semiconductor chip;
an opening formed in one main surface of the wiring board; and
a plurality of connection parts formed in a bottom of the opening and connected to the plural salient electrodes respectively,
the plural salient electrodes being disposed along a first center line on said one main surface of the semiconductor chip.
US09/921,919 2000-08-31 2001-08-06 Electronic device and a method of manufacturing the same Active US6492737B1 (en)
JP2000262511A JP3822040B2 (en) 2000-08-31 2000-08-31 Electronic device and manufacturing method thereof
JP2000-262511 2000-08-31
US10/279,865 US20030102570A1 (en) 2000-08-31 2002-10-25 Electronic device and a method of manufacturing the same
US10/279,865 Continuation US20030102570A1 (en) 2000-08-31 2002-10-25 Electronic device and a method of manufacturing the same
US6492737B1 true US6492737B1 (en) 2002-12-10
ID=18750182
US09/921,919 Active US6492737B1 (en) 2000-08-31 2001-08-06 Electronic device and a method of manufacturing the same
US10/279,865 Abandoned US20030102570A1 (en) 2000-08-31 2002-10-25 Electronic device and a method of manufacturing the same
US (2) US6492737B1 (en)
JP (1) JP3822040B2 (en)
KR (1) KR100776867B1 (en)
CN (1) CN1235286C (en)
SG (1) SG99937A1 (en)
TW (1) TW563214B (en)
EP2950359A1 (en) * 2014-05-28 2015-12-02 LG Innotek Co., Ltd. For wafer bonding optimized contact structure of a light emitting device
KR100642765B1 (en) 2004-09-15 2006-11-10 삼성전자주식회사 Microelectronic device chip including hybrid bump, package thereof, LCD apparatus having the same and method for fabricating the microelectronic device chip
CN100499096C (en) 2006-08-15 2009-06-10 南茂科技股份有限公司;百慕达南茂科技股份有限公司 Encapsulation structure for high frequency integrated circuit and its making method
JP2009094353A (en) * 2007-10-10 2009-04-30 Furukawa Electric Co Ltd:The Semiconductor device and method of manufacturing the same
JP6067408B2 (en) * 2013-02-20 2017-01-25 スタンレー電気株式会社 Flip-chip type semiconductor light emitting device, a semiconductor device and a manufacturing method thereof
KR20170116461A (en) * 2016-04-11 2017-10-19 삼성전기주식회사 Substrate for camera module and camera module having the smae
US20020050652A1 (en) * 1999-09-02 2002-05-02 Salman Akram Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer
JP3019511B2 (en) * 1991-08-21 2000-03-13 富士ゼロックス株式会社 Sheet guide device to the transfer material carrying member
2000-08-31 JP JP2000262511A patent/JP3822040B2/en not_active Expired - Fee Related
2001-08-06 US US09/921,919 patent/US6492737B1/en active Active
2001-08-08 SG SG200104737A patent/SG99937A1/en unknown
2001-08-08 TW TW090119334A patent/TW563214B/en not_active IP Right Cessation
2001-08-31 CN CNB011253703A patent/CN1235286C/en not_active IP Right Cessation
2001-08-31 KR KR1020010053225A patent/KR100776867B1/en not_active IP Right Cessation
2002-10-25 US US10/279,865 patent/US20030102570A1/en not_active Abandoned
US7221058B2 (en) 2003-11-27 2007-05-22 Denso Corporation Substrate for mounting semiconductor chip, mounting structure of semiconductor chip, and mounting method of semiconductor chip
US7928566B2 (en) * 2006-12-27 2011-04-19 Panasonic Corporation Conductive bump, method for manufacturing the conductive bump, semiconductor device and method for manufacturing the semiconductor device
US9472742B2 (en) 2014-05-28 2016-10-18 Lg Innotek Co., Ltd. Light emitting device and light unit having the same
KR20020018591A (en) 2002-03-08
CN1340857A (en) 2002-03-20
SG99937A1 (en) 2003-11-27
KR100776867B1 (en) 2007-11-16
TW563214B (en) 2003-11-21
US20030102570A1 (en) 2003-06-05
JP3822040B2 (en) 2006-09-13
CN1235286C (en) 2006-01-04
JP2002076057A (en) 2002-03-15
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:IMASU, SATOSHI;YOSHIDA, IKUO;KISHIKAWA, NORIO;AND OTHERS;REEL/FRAME:012055/0125;SIGNING DATES FROM 20010618 TO 20010619