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Timestamp: 2018-08-21 13:36:49
Document Index: 176654626

Matched Legal Cases: ['Application No. 10003084', 'Application No. 06', 'Application No. 10002884', 'Application No. 06800414', 'art 2', 'art 1', 'art 1', 'art 2']

Semiconductor sensor structures with reduced dislocation defect densities - Patent # 8253211 - PatentGenius
8253211 Semiconductor sensor structures with reduced dislocation defect densities
Application: 12/565,863
Inventors: Cheng; Zhiyuan (Lincoln, MA)
Fiorenza; James G. (Wilmington, MA)
Sheen; Calvin (Derry, NH)
Lochtefeld; Anthony (Ipswich, MA)
U.S. Class: 257/431; 257/E31.079; 257/E33.002
Field Of Search: 257/292; 257/184; 257/E31.079; 257/E31.002; 257/E21.09; 257/414; 257/428; 257/431
International Class: H01L 21/14
Foreign Patent Documents: 2550906; 101268547; 101300663; 10017137; 10320160; 0352472; 0600276; 0817096; 1551063; 1796180; 2215514; 2062090; 7230952; 10126010; 10284436; 10284507; 11251684; 11307866; 2000021789; 2000216432; 2000286449; 2000299532; 2001007447; 2001102678; 3202223; 2001257351; 2002118255; 2002141553; 2002241192; 2002293698; 2003163370; 3515974; 2004200375; 2009177167; 20030065631; 20090010284; 544930; WO0072383; WO0101465; WO0209187; WO02086952; WO02088834; WO03073517; WO2004004927; WO2004023536; WO2005013375; WO2005048330; WO2005098963; WO2005122267; WO2006025407; WO 2006/125040; WO 2006/125040; WO 2007/014294; WO2008124154
Other References: European Patent Office, Extended European Search Report and Search Opinion dated Jan. 26, 2011 in EP Patent Application No. 10003084.0-2203 (9pages). cited by other.
Kwok K. Ng, "Resonant-Tunneling Diode," Complete Guide to Semiconductor Devices, Chapter 10. Nov. 3, 2010, pp. 75-83. cited by other.
"Communication pursuant to Article 94(3) EPC," Application No. 06 770 525.1-2203, Applicant: Taiwan Semiconductor Company, Ltd., Feb. 17, 2011, 4 pages. cited by other.
68 Applied Physics Letters 7, 1999, pp. 774-779 (trans. of relevant portions attached). cited by other.
Ames, "Intel Says More Efficient Chips are Coming," PC World, available at: http://www.pcworld.com/printable/article/id,126044/printable.html (Jun. 12, 2006); 4 pages. cited by other.
Asano et al., "AIGaInN laser diodes grown on an ELO-GaN substrate vs. on a sapphire substrate," Semiconductor Laser Conference (2000) Conference Digest, IEEE 17.sup.th International, 2000, pp. 109-110. cited by other.
Asaoka, et al., "Observation of 1 f .sup.x/noise of GaInP/GaAs triple barrier resonant tunneling diodes, " AIP Conf. Proc., vol. 780, Issue 1, 2005, pp. 492-495. cited by other.
Ashby, et al., "Low-dislocation-density GaN from a single growth on a textured substrate," Applied Physics Letters, vol. 77, No. 20, Nov. 13, 2000, pp. 3233-3235. cited by other.
Ashley, et al., "Heternogeneous InSb Quantum Well Transistors on Silicon for Ultra-High Speed, Low Power Logic Applications," 43 Electronics Letters 14, Jul. 2007, 2 pages. cited by other.
Bai et al., "Study of the Defect Elimination Mechanisms in Aspect Ratio Trapping Ge Growth," Applied Physics Letters, vol. 90, 2007, 3 pages. cited by other.
Bakkers et al., "Epitaxial Growth on InP Nanowires on Germanium," Nature Materials, vol. 3, Nov. 2004, pp. 769-773. cited by other.
Baron et al., "Chemical Vapor Deposition of Ge Nanocrystals on SiO.sub.2," Applied Physics Letters, vol. 83, No. 7, Aug. 18, 2003, pp. 1444-1446. cited by other.
Bean et al., "Ge.sub.xSi.sub.1-x/Si strained-later Superlattice grown by molecular beam Epitaxy," Journal of Vacuum Science Technology A2 (2), Jun. 1984, pp. 436-440. cited by other.
Beckett et al., "Towards a reconfigurable nanocomputer platform," ACM International Conference Proceeding Series, vol. 19, 2002, pp. 141-150. cited by other.
Beltz et al., "A Theoretical Model for Threading Dislocation Reduction During Selective Area Growth," Materials Science and Engineering, A234-236, 1997, pp. 794-797. cited by other.
Belyaev, et al., "Resonance and current instabilities in AIN/GaN resonant tunneling diodes," 21 Physica E 2-4, 2004, pp. 752-755. cited by other.
Berg, J., "Electrical Characterization of Silicon Nanogaps," Doktorsavhandlingar vid Chalmers Tekniska Hagskola, 2005, No. 2355, 2 pages. cited by other.
Bergman et al., "RTD/CMOS Nanoelectronic Circuits: Thin-Film InP-based Resonant Tunneling Diodes Integrated with CMOS circuits," 20 Electron Device Letters 3, 1999, pp. 119-122. cited by other.
Blakeslee, "The Use of Superlattices to Block the Propagation of Dislocations in Semiconductors," Mat. Res. Soc. Symposium Proceedings 148, 1989, pp. 217-227. cited by other.
Bogumilowicz et al., "Chemical Vapour Etching of Si, SiGe and Ge with HCL: Applications to the Formation of Thin Relaxed SiGe Buffers and to the Revelation of Threading Dislocations," 20 Semicond. Sci. Tech. 2005, pp. 127-134. cited by other.
Borland, "Novel Device structures by selective epitaxial growth (SEG)," Electron Devices Meeting, vol. 33, 1987, pp. 12-15. cited by other.
Bryskiewicz, "Dislocation filtering in SiGe and InGaAs buffer layers grown by selective lateral overgrowth method," Applied Physics Letters, vol. 66, No. 10, Mar. 6, 1995, pp. 1237-1239. cited by other.
Burenkov et al., "Corner Effect in Double and Triple Gate FinFETs "European solid-state device research, 33rd Conference on Essderc '03 Sep. 16-18, 2003, Piscataway, NJ, USA, IEEE, vol. 16, pp. 135-38, XPo10676716. cited by other.
Bushroa et al., "Lateral epitaxial overgrowth and reduction in defect density of 3C-SiC on patterned Si substrates," Journal of Crystal Growth, vol. 271, No. 1-2, Oct. 15, 2004, pp. 200-206. cited by other.
Calado, et al., "Modeling of a resonant tunneling diode optical modulator," University of Algarve, Department of Electronics and Electrical Engineering, 2005, pp. 96-99. cited by other.
Campo et al., "Comparison of Etching Processes of Silicon and Germanium in SF6-O2 Radio-Frequency Plasma," 13 Journal of Vac. Sci. Tech., B-2, 1995, pp. 235-241. cited by other.
Cannon et al., "Monolithic Si-based Technology for Optical Receiver Circuits," Proceedings of SPIE, vol. 4999, 2003, pp. 145-155. cited by other.
Chan et al., "Influence of Metalorganic Sources on the Composition Uniformity of Selectively Grown Ga.sub.xIn.sub.1-xP," Japan Journal of Applied Physics, vol. 33, 1994, pp. 4812-4819. cited by other.
Chang et al. "3-D simulation of strained Si/SiGe heterojunction FinFETs" Semiconductor Device Research Symposium, Dec. 10-12, 2003, pp. 176-177. cited by other.
Chang et al., "Effect of growth temperature on epitaxial lateral overgrowth of GaAs on Si substrate," Journal of Crystal Growth, vol. 174, No. 1-4, Apr. 1997, pp. 630-634. cited by other.
Chang et al., "Epitaxial Lateral Overgrowth of Wide Dislocation-Free GaAs on Si Substrates," Electrochemical Society Proceedings, vol. 97-21, May 13, 1998, pp. 196-200. cited by other.
Chau et al., Opportunities and Challenges of III-V Nanoelectronics for Future High-Speed, Low Power Logic Applications, IEEE CSIC Digest, 2005, pp. 17-20. cited by other.
Chen et al., "Dislocation reduction in GaN thin films via lateral overgrowth from trenches," Applied Physics Letters, vol. 75, No. 14, Oct. 4, 1999, pp. 2062-2063. cited by other.
Chengrong, et al., "DBRTD with a high PVCR and a peak current density at room temperature," Chinese Journal of Semiconductors vol. 26, No. 10, Oct. 2005, pp. 1871-1874. cited by other.
Choi et al., "Monolithic Integration GaAs/AlGaAs LED and Si Driver Circuit," 9 Electron Device Letters 10, Oct. 1988, 3 pages. cited by other.
Choi et al., "Monolithic Integration of GaAs/AlGaAs Double-Heterostructure LEDs and Si MOSFETs," Electron Device Letters, vol. EDL-7, No. 9, Sep. 1986, 3 pages. cited by other.
Choi et al., "Monolithic Integration of Si MOSFETs and GaAs MESFETs," Electron Device Letters, vol. EDL-7, No. 4, Apr. 1986, 3 pages. cited by other.
Choi, et al., "Low-voltage low-power K-band balanced RTD-based MMIC VCO," 2006 IEEE, Department of EECS, Korea Advanced Institute of Science and Technology, 2006, pp. 743-746. cited by other.
Cloutier et al., "Optical gain and stimulated emission in periodic nanopatterned crystalline silicon," Nature Materials, Nov. 2005, 5 pages. cited by other.
Currie et al., "Carrier Mobilities and Process Stability of Strained Si n- and p-MOSFETs on SiGe Virtual Substrates," J.Vacuum Science Technology, B, vol. 19, No. 6, 2001, pp. 2268-2279. cited by other.
Dadgar et al., "MOVPE growth of GaN on Si (111) substrates," Journal of Crystal Growth, vol. 248, Feb. 1, 2003, pp. 556-562. cited by other.
Datta et al., "Silicon and III-V Nanoelectronics," IEEE International Conference on Indium Phosphide & Related Materials, 2005, pp. 7-8. cited by other.
Datta et al., "Ultrahigh-Speed 0.5 V Supply Voltage In0.7Ga0.3As Quantum-Well Transistors on Silicon Substrate," 28 Electron Device Letters 8, 2007, pp. 685-687. cited by other.
Davis et al., "Lateral epitaxial overgrowth of and defect reduction in GaN thin films," Lasers and Electro-Optics Society Annual Meeting (1998) LEOS '98. IEEE, vol. 1, Dec. 1-4, 1998, pp. 360-361. cited by other.
De Boeck et al., "The fabrication on a novel composite GaAs/SiO.sub.2 nucleation layer on silicon for heteroepitaxial overgrowth by molecular beam Epitaxy," Material Science and Engineering, B9, 1991, pp. 137-141. cited by other.
Donaton et al., "Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure," 2006 IEDM, pp. 465-468. cited by other.
Dong, Y., et al, "Selective area growth of InP through narrow openings by MOCVD and its application to InP HBT," 2003 International Conference on Indium Phosphide and Related Materials, May 12-16, 2003, pp. 389-392. cited by other.
European Search Report issued by the European Patent Office on Dec. 15, 2010 in European Patent Application No. 10002884.4 (10 pages). cited by other.
Examination Report in European Patent Application No. 06800414.2, mailed Mar. 5, 2009, 3 pages. cited by other.
Fang et al., "Electrically pumped hybrid AlGalnAs-silicon evanescent laser," 14 Optics Express 20, 2006, pp. 9203-9210. cited by other.
Feltin et al., "Epitaxial lateral overgrowth of GaN on Si (111)," Journal of Applied Physics, vol. 93, No. 1, Jan. 1, 2003, pp. 182-185. cited by other.
Feng et al., "Integration of Germanium-on Insulator and Silicon Substrate," 27 Electron Device Letters 11, 2006, pp. 911-913. cited by other.
Fiorenza et al., "Film Thickness Constraints for Manufacturable Strained Silicon CMOS," 19 Semiconductor Science Technology, 2004, p. L4. cited by other.
Fischer et al., "Elastic stress relaxation in SiGe epilayers on patterned Si substrates," 75 Journal of Applied Physics 1, 1994, pp. 657-659. cited by other.
Fischer et al., "State of stress and critical thickness of Strained small-area SiGe layers, "Phys. Stat. Sol. (a) vol. 171, 1999, pp. 475-485. cited by other.
Fitzgerald et al., "Elimination of Dislocations in Heteroepitaxial MBE and RTCVD Ge.sub.xSi.sub.1-x Grown on Patterned Si Substrates," Journal of Electronic Materials, vol. 19, No. 9, 1990, pp. 949-955. cited by other.
Fitzgerald et al., "Epitaxial Necking in GaAs Growth on Pre-patterned Si Substrates," Journal of Electronic Materials, vol. 20, No. 10, 1991, pp. 839-853. cited by other.
Fitzgerald et al., "Nucleation Mechanisms and the Elimination of Misfit Dislocations at Mismatched Interfaces by Reduction in Growth Areas," Journal of Applied Physics, vol. 65, No. 6, Mar. 15, 1989, pp. 2220-2237. cited by other.
Fitzgerald et al., "Structure and recombination in InGaAs/GaAs heterostructures," 63 Journal of Applied Physics, vol. 3, 1988, pp. 693-703. cited by other.
Fitzgerald et al., "Totally relaxed Ge.sub.xSi.sub.1-x layers with low threading dislocation densities grown on Si Substrates," vol. 59, Applied Physics Letters 7, 1991, pp. 811-813. cited by other.
Fitzgerald, "The Effect of Substrate Growth Area on Misfit and Threading Dislocation Densities in Mismatched Heterostructures," Journal of Vacuum Science Technology, vol. 7, No. 4, Jul./Aug. 1989, pp. 782-788. cited by other.
Gallagher et al., "Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip," 50 IBM J. Research & Dev. 1, Jan. 2006, pp. 5-23A. cited by other.
Gallas et al., "Influence of Doping on Facet Formation at the SiO.sub.2/Si Interface," Surface Sci. 440, 1999, pp. 41-48. cited by other.
Geppert, "Quantum transistors: toward nanoelectronics," IEEE Spectrum, Sep. 2000, pp. 46-51. cited by other.
Gibbon et al., "Selective-area low-pressure MOCVD of GaInAsP and related materials on planar InP substrates,"Semicond. Sci. Tech. vol. 8, 1993, pp. 998-1010. cited by other.
Glew et al., "New DFB grating structure using dopant-induced refractive index step," J. Crystal Growth 261, 2004, pp. 349-354. cited by other.
Golka, et al., "Negative differential resistance in dislocation-free GaN/AlGan double-barrier diodes grown on bulk GaN," 88 Applied Physics Letters 17, Apr. 2006, pp. 172106-1-172106-3. cited by other.
Goodnick, S.M., "Radiation Physics and Reliability Issues in III-V Compound Semiconductor Nanoscale Heterostructure Devices," Final Technical Report, Arizona State Univ. Dept. Electrical & Computer Eng, 80 pages, 1996-1999. cited by other.
Gould et al., "Magnetic resonant tunneling diodes as voltage-controlled spin selectors," 241 Phys. Stat. Sol. (B), vol. 3, 2004, pp. 700-703. cited by other.
Groenert et al., "Monolithic integration of room-temperature cw GaAs/AlGaAs lasers on Si substrates via relaxed graded GeSi buffer layers," 93 Journal of Applied Physics, No. 362, Jan. 2003, pp. 362-367. cited by other.
Gruber, et al., "Semimagnetic Resonant Tunneling Diodes for Electron Spin Manipulation," Nanostructures: Physics & Technology, 8th International Symposium, 2000, pp. 483-486. cited by other.
Gustafsson et al., "Cathodoluminescence from relaxed Ge.sub.xSi.sub.1-x grown by heteroepitaxial lateral overgrowth," Journal of Crystal Growth 141, 1994, pp. 363-370. cited by other.
Gustafsson et al., "Investigations of high quality Ge.sub.xSi.sub.1-x grown by heteroepitaxial lateral overgrowth using cathodoluminescence," Inst. Phys. Conf. Ser., No. 134, Section 11, Apr. 1993, pp. 675-678. cited by other.
Hammerschmidt, "Intel to Use Trigate Transistors from 2009 on," EETIMES Online, available at: http://www.eetimes.com/showArticle.jhtml?articlelD=189400035 (Jun. 12, 2006). 1 page. cited by other.
Hasegawa, et al., "Sensing Terahertz Signals with III-V Quantum Nanostructures," Quantum Sensing: Evolution and Revolution from Past to Future, SPIE 2003, pp. 96-105. cited by other.
Hayafuji et al., Japan, Journal of Applied Physics, vol. 29, 1990, pp. 2371. cited by other.
Hersee et al., "The Controlled Growth of GaN Nanowires," Nano Letters, vol. 6, No. 8, 2006, pp. 1808-1811. cited by other.
Hiramatsu et al., "Fabrication and characterization of low defect density GaN using facet-controlled epitaxial lateral overgrowth (FACELO)," Journal of Crystal Growth, vol. 221, Dec. 2000, pp. 316-326. cited by other.
Hollander et al., "Strain and Misfit Dislocation Density in Finite Lateral Size Si.sub.1-xGe.sub.x/Si Films Grown by Selective Epitaxy," Thin Solid Films, vol. 292, 1997, pp. 213-217. cited by other.
Hu et al., "Growth of Well-Aligned Carbon Nanotube arrays on Silicon Substrates Using Porous Alumina Film as a Nanotemplate," 79 Applied Physics Letters 19, 2001, 3 pages. cited by other.
Yanlong, et al., "Monolithically fabricated OEICs using RTD and MSM," Chinese Journal Semiconductors vol. 27, No. 4, Apr. 2006, pp. 641-645. cited by other.
Huang et al., "Electron and Hole Mobility Enhancement in Strained SOI by Wafer Bonding," 49 IEEE Transactions on Electron Devices 9, 2002, pp. 1566-1570. cited by other.
Ying-Long, et al., "Resonant tunneling diodes and high electron mobility transistors integrated on GaAs substrates,"Chinese Physics Letters 23, vol. 3, Mar. 2006, pp. 697-700. cited by other.
Hydrick et al., "Chemical Mechanical Polishing of Epitaxial Germanium on Si0.sub.2-patterned Si(001) Substrates," ECS Transactions, 16 (10), 2008, (pp. 237-248). cited by other.
Intel Press Release, "Intel's Tri-Gate Transistor to Enable Next Era in Energy-Efficient Performance," Intel Corporation (Jun. 12, 2006). 2 pages. cited by other.
Intel to Develop Tri-Gate Transistors Based Processors, available at: http://news.techwhack.com/3822/tri-gate-transistors/ (Jun. 13, 2006) 6 pages. cited by other.
International Preliminary Report on Patentability for International Application No. PCT/US2006/019152 mailed Nov. 29, 2007, 2 pages. cited by other.
International Preliminary Report on Patentability for International Application No. PCT/US2006/029247 mailed Feb. 7, 2008, 12 pages. cited by other.
International Preliminary Report on Patentability for International Application No. PCT/US2006/033859 mailed Mar. 20, 2008, 14 pages. cited by other.
International Preliminary Report on Patentability for International Application No. PCT/US2007/019568 mailed Mar. 19, 2009, 10 pages. cited by other.
International Preliminary Report on Patentability for International Application No. PCT/US2007/020181 mailed Apr. 2, 2009, 9 pages. cited by other.
International Preliminary Report on Patentability for International Application No. PCT/US2007/020777 mailed Apr. 9, 2009, 12 pages. cited by other.
International Preliminary Report on Patentability for International Application No. PCT/US2007/021023 mailed Apr. 9, 2009, 8 pages. cited by other.
International Preliminary Report on Patentability for International Application No. PCT/US2007/022392 mailed Apr. 30, 2009, 14 pages. cited by other.
International Search Report and Written Opinion for International Application No. PCT/US2006/019152 mailed Oct. 19, 2006, 11 pages. cited by other.
International Search Report and Written Opinion for International Application No. PCT/US2006/029247 mailed May 7, 2007, 19 pages. cited by other.
International Search Report and Written Opinion for International Application No. PC/US2008/068377, mailed Jul. 6, 2009, 19 pages. cited by other.
International Search Report and Written Opinion for International Application No. PCT/US2006/033859 mailed Sep. 12, 2007, 22 pages. cited by other.
International Search Report and Written Opinion for International Application No. PCT/US2007/007373, dated Oct. 5, 2007, 13 pages. cited by other.
International Search Report and Written Opinion for International Application No. PCT/US2007/019568 mailed Feb. 6, 2008, 13 pages. cited by other.
International Search Report and Written Opinion for International Application No. PCT/US2007/020181 mailed Jan. 25, 2008, 15 pages. cited by other.
International Search Report and Written Opinion for International Application No. PCT/US2007/020777 mailed Feb. 8, 2008, 18 pages. cited by other.
International Search Report and Written Opinion for International Application No. PCT/US2007/021023 mailed Jun. 6, 2008, 10 pages. cited by other.
International Search Report and Written Opinion for International Application No. PCT/US2007/022392 mailed Apr. 11, 2008, 20 pages. cited by other.
International Search Report for International Application No. PCT/US2006/019152, mailed May 17, 2005. 11 pages. cited by other.
International Technology Roadmap for Semiconductors--Front End Processes, pp. 1-62 (2005). cited by other.
Ipri et al., "MONO/POLY technology for fabricating low-capacitance CMOS integrated circuits," Electron Devices, IEEE Transactions, vol. 35, No. 8, Aug. 1988 pp. 1382-1383. cited by other.
Ishibashi, et al., "3rd Topical Workshop on Heterostructure Microelectronics for Information Systems Application," Aug.-Sep. 1998, 115 pages. cited by other.
Ishitani et al., "Facet Formation in Selective Silicon Epitaxial Growth," 24 Japan, Journal of Applied Physics, vol. 10, 1985, pp. 1267-1269. cited by other.
Ismail et al., "High-quality GaAs on Sawtooth-patterned Si Substrates," 59 Applied Physics Letters 19, 1991, pp. 2418-2420. cited by other.
Jain et al., "Stresses in strained GeSi stripes and quantum structures: calculation using the finite element method and determination using micro-Raman and other measurements," Thin Solid Films 292, 1997, pp. 218-226. cited by other.
Jeong, et al., "Performance improvement of InP-based differential HBT VCO using the resonant tunneling diode,"2006 International Conf. on Indium Phosphide and Related Mat. Conf. Proc., pp. 42-45. cited by other.
Ju et al., "Epitaxial lateral overgrowth of gallium nitride on silicon substrate," Journal of Crystal Growth, vol. 263, No. 1-4, Mar. 1, 2004, pp. 30-34. cited by other.
Kamins et al., "Kinetics of Selective Epitaxial Depostion of Si1-xGex," Hewlett-Packard Company, Palo Alto, CA, Appl. Phys. Lett. 61 (6), Aug. 10, 1992 (pp. 669-671). cited by other.
Kamiyama, et al., "UV laser diode with 350.9-nm-lasing wavelength grown by hetero-epitaxial-lateral overgrowth technology," Selected Topics in Quantum Electronics, IEEE Journal of Selected Topics in Quantum Electronics, vol. 11, No. 5, Sep.-Oct.2005, pp. 1069-1073. cited by other.
Kamiyama, et al., "UV light-emitting diode fabricated on hetero-ELO-grown Al.sub.0.22Ga.sub.0.78N with low dislocation density," Physica Status Solidi A, vol. 192, No. 2, Aug. 2002, pp. 296-300. cited by other.
Kawai, et al., "Epitaxial Growth of InN Films and InN Nano-Columns by RF-MBE," The Institute of Electronics, Information and Communication Engineers, Gijutsu Kenkyu, vol. 13, No. 343 (CPM2003 102-116), 2003, pp. 33-37. cited by other.
Kazi et al., "Realization of GaAs/AlGaAs Lasers on Si Substrates Using Epitaxial Lateral Overgrowth by Metalorganic Chemical Vapor Deposition," Japan, Journal of Applied Physics, vol. 40, 2001, pp. 4903-4906. cited by other.
Kidoguchi et al., "Air-bridged lateral epitaxial overgrowth of GaN thin Films," Applied Physics Letters, vol. 76, No. 25, Jun. 19, 2000, pp. 3768-3770. cited by other.
Kim et al., "Silicon-Based Field-Induced Band-to-Band Tunneling Effect Transistor," IEEE Electron Device Letters, No. 25, No. 6, 2004, pp. 439-441. cited by other.
Kim et al., "GaN nano epitaxial lateral overgrowth on holographically patterned substrates," School of Physics and Inter-University Semiconductor Research Center, Seoul National University, Aug. 25-27, 2003, pp. 27-28. cited by other.
Kimura et al., "Vibronic Fine Structure Found in the Blue Luminescence from Silicon Nanocolloids," Japan, Journal of Applied Physics, vol. 38, 1999, pp. 609-612. cited by other.
Klapper, "Generation and Propagation of Dislocations During Crystal Growth," Mat. Chem. and Phys. vol. 66, 2000, pp. 101-109. cited by other.
Knall et al., "Threading Dislocations in GaAs Grown with Free Sidewalls on Si mesas," Journal of Vac. Sci. Technol. B, vol. 12, No. 6, Nov./Dec. 1994, pp. 3069-3074. cited by other.
Kollonitsch, et al., "Improved Structure and Performance of the GaAsSb/InP Interface in a Resonant Tunneling Diode," Journal of Crystal Growth, vol. 287, 2006, pp. 536-540. cited by other.
Krishnamurthy, et al., "I-V characteristics in resonant tunneling devices: Difference Equation Method," Journal of Applied Physics, vol. 84, Issue 9, Condensed Matter: Electrical and Magnetic Properties (PACS 71-76), 1998, 9 pages. cited by other.
Krost et al., "GaN-based Optoelectronics on Silicon Substrates," Materials Science & Engineering, B93, 2002, pp. 77-84. cited by other.
Sudirgo et al., "Si-Based Resonant Interband Tunnel Diode/CMOS Integrated Memory Circuits," Rochester Institute of Technology, IEEE, 2006, pp. 109-112. cited by other.
Kusakabe, K. et al., Characterization of Overgrown GaN layers on Nano-Columns Grown by RF-Molecular Beam Epitaxy, Japan, Journal of Applied Physics, Part 2, vol. 40, No. 3A, 2001, pp. L192-194. cited by other.
Kushida et al., "Epitaxial growth of PbTiO.sub.3 films on SrTiO.sub.3 by RF magnetron sputtering," Ultrasonics, Ferroelectrics and Frequency Control, IEEE Transactions on Ultrasonics Ferroelectrics and Frequency Control, vol. 38, No. 6, Nov. 1991,pp. 656-662. cited by other.
Kwok, "Barrier-Injection Transit Time Diode," Complete Guide to Semiconductor Devices, 2.sup.nd ed., Chapter 18, 2002, pp. 137-144. cited by other.
Lammers, "Trigate and High-k stack up vs. planar," EETIMES Online, available at: http://www.eetimes.com/showArticle.jhtml?articlelD=188703323&pgno=2&print- able=true (Jun. 12, 2006). 2 pages. cited by other.
Langdo et al., "High Quality Ge on Si by Epitaxial Necking," Applied Physics Letters, vol. 76, No. 25, Jun. 19, 2000, pp. 3700-3702. cited by other.
Langdo, "Selective SiGe Nanostructures," PhD Thesis, Massachusetts Institute of Technology, Jun. 2001, 215 pages. cited by other.
Lee et al., "Growth of GaN on a nanoscale periodic faceted Si substrate by metal organic vapor phase epitaxy," Compound Semiconductors: Post-Conference Proceedings, Aug. 25-27, 2003, pp. 15-21. cited by other.
Lee et al., "Strain-relieved, Dislocation-free In.sub.xGa.sub.1-xAs/GaAs(001) Heterostructure by Nanoscale-patterned Growth," Applied Physics Letters, vol. 85, No. 18, Nov. 1, 2004, pp. 4181-4183. cited by other.
Li et al., "Defect Reduction of GasAs Epitaxy on Si (001) Using Selective Aspect Ratio Trapping," 91 Applied Physics Letters, 2007, pp. 021114-1-021114-3. cited by other.
Li et al., "Heteroepitaxy of High-quality Ge on Si by Nanoscale Ge seeds Grown through a Thin Layer of SiO.sub.2," Applied Physics Letters, vol. 85, No. 11, Sep. 13, 2004, pp. 1928-1930. cited by other.
Li et al., "Monolithic Integration of GaAs/InGaAs Lasers on Virtual Ge Substrates via Aspect-Ratio Trapping," Journal of The Electrochemical Society, vol. 156, No. 7, 2009, pp. H574-H578. cited by other.
Li et al., "Morphological Evolution and Strain Relaxation of Ge Islands Grown on Chemically Oxidized Si (100) by Molecular-Beam Epitaxy," Journal of Applied Physics, vol. 98, 2005, pp. 073504-1-073504-8. cited by other.
Li et al., "Selective Growth of Ge on Si (100) through Vias of Si.sub.02 Nanotemplate Using Solid Source Molecular Beam Epitaxy," Applied Physics Letters, vol. 83, No. 24, Dec. 15, 2003, pp. 5032-5034. cited by other.
Liang et al., "Critical Thickness enhancement of Epitaxial SiGe films Grown on Small Structures," Journal of Applied Physics, vol. 97, 2005, pp. 043519-1-043519-7. cited by other.
Lim et al., "Facet Evolution in Selective Epitaxial Growth of Si by cold-wall ultrahigh vacuum chemical vapor deposition," Journal of Vac. Sci. Tech., vol. B 22, No. 2, 2004, pp. 682. cited by other.
Liu et al., "High Quality Single-crystal Ge on Insulator by Liquid-phase Epitaxy on Si Substrates," Applied Physics Letters, vol. 84, No. 14, Apr. 4, 2004, pp. 2563-2565. cited by other.
Liu et al., "Rapid Melt Growth of Germanium Crystals with Self Aligned Microcrucibles on Si Substrates," Journal of the Electrochemical Society, vol. 152, No. 8, 2005, pp. G688-G693. cited by other.
Loo et al., "Successful Selective Epitaxial Si.sub.1-xGe.sub.x Deposition Process for Hbt-BiCMOS and High Mobility Heterojunction pMOS Applications," 150 Journal of Electrochemical Society 10, 2003, pp. G638-G647. cited by other.
Lourdudoss et al., "Semi-insulating epitaxial layers for optoelectronic devices," Semiconducting and Insulating Materials Conference, SIMC-XI, 2000, pp. 171-178. cited by other.
Luan et al., "High-quality Ge Epilayers on Si with Low Threading-dislocation Densities," Applied Physics Letters, vol. 75, No. 19, Nov. 8, 1999, pp. 2909-2911. cited by other.
Luan, "Ge Photodetectors for Si Microphotonics," PhD Thesis, Massachusetts Institute of Technology, Department of Materials Science & Engineering, Jan. 12, 2001, 155 pages. cited by other.
Lubnow et al., "Effect of III/V-Compound Epitaxy on Si Metal-Oxide-Semiconductor Circuits," Japan, Journal of Applied Physics, vol. 33, 1994, pp. 3628-3634. cited by other.
Luo et al., Enhancement of (IN,Ga)N Light-Emitting Diode Performance by Laser Liftoff and Transfer From Sapphire to Silicon, IEEE Photonics Technology Letters, vol. 14, No. 10, 2002, pp. 1400-1402. cited by other.
Luryi et al., "New Approach to the High Quality Epitaxial Growth of Latticed-Mismatched Materials," Applied Physics Letters, vol. 49, No. 3, Jul. 21, 1986, pp. 140-142. cited by other.
Ma, et al., "A small signal equivalent circuit model for resonant tunneling diode," Chinese Physics Letters, vol. 23, No. 8, Aug. 2006, pp. 2292-2295. cited by other.
Ma, et al., "Fabrication of an AlAs/In0.53/Ga0.47/As/InAs resonant tunneling diode on InP substrate for high-speed circuit applications," 27 Chinese J. Semiconductors 6, Jun. 2006, pp. 959-962. cited by other.
Maekawa, et al., "High PVCR Si/Si1-x/Gex DW RTD formed with a new triple-layer buffer," Materials Science in Semiconductor Processing, vol. 8, 2005, pp. 417-421. cited by other.
Maezawa, et al., "Metamorphic resonant tunneling diodes and its application to chaos generator ICs,"44 Jap. J. Applied Physics, Part 1, No. 7A, Jul. 2005, pp. 4790-4794. cited by other.
Maezawa, et al., "InP-based resonant tunneling diode/HEMT integrated circuits for ultrahigh-speed operation," IEEE Nagoya University, Institute for Advanced Research, 2006, pp. 252-257. cited by other.
Martinez et al., "Characterization of GaAs Conformal Layers Grown by Hydride Vapour Phase Epitaxy on Si Substrates by Microphotoluminescence Cathodoluminescence and MicroRaman," Journal of Crystal Growth, vol. 210, 2000, pp. 198-202. cited by other.
Matsunaga et al., "A New Way to Achieve Dislocation-Free Heteroepitaxial Growth by Molecular Beam Epitaxy: Vertical Microchannel Epitaxy," Journal of Crystal Growth, vol. 237-239, 2002, pp. 1460-1465. cited by other.
Matthews et al., "Defects in Epitaxial Multilayers--Misfit Dislocations," Journal of Crystal Growth, vol. 27, 1974, pp. 118-125. cited by other.
Monroy, et al., "High UV/visible Contrast Photodiodes Based on Epitaxial Lateral Overgrown GaN layers," Electronics Letters, vol. 35, No. 17, Aug. 19, 1999, pp. 1488-1489. cited by other.
Nakano et al., "Epitaxial Lateral Overgrowth of AIN Layers on Patterned Sapphire Substrates," Source: Physica Status Solidi A, vol. 203, No. 7, May 2006, pp. 1632-1635. cited by other.
Nam et al., "Lateral Epitaxy of Low Defect Density GaN Layers via Organometallic Vapor Phase Epitaxy," Applied Physics Letters, vol. 71, No. 18, Nov. 3, 1997, pp. 2638-2640. cited by other.
Naoi et al., "Epitaxial Lateral Overgrowth of GaN on Selected-area Si (111) Substrate with Nitrided Si Mask," Journal of Crystal Growth, vol. 248, 2003, pp. 573-577. cited by other.
Naritsuka et al., "InP Layer Grown on (001) Silicon Substrate by Epitaxial Lateral Overgrowth," Japan, Journal of Applied Physics, vol. 34, 1995, pp. L1432-L1435. cited by other.
Naritsuka et al., "Vertical Cavity Surface Emitting Laser Fabricated on GaAs Laterally Grown on Si Substrate,"Electrochemical Society Proceedings, vol. 97, No. 21, pp. 86-90. cited by other.
Neudeck, et al., "Novel silicon Epitaxy for advanced MOSFET devices," Electron Devices Meeting, IEDM Technical Digest International, 2000, pp. 169-172. cited by other.
Neumann et al., "Growth of III-V Resonant Tunneling Diode on Si Substrate with LP-MOVPE," Journal of Crystal Growth, vol. 248, 2003, pp. 380-383. cited by other.
Noborisaka, J., et al., "Catalyst-free growth of GaAs nanowires by selective-area metalorganic vapor-phase epitaxy," Applied Physics Letters, vol. 86, May 16, 2005, pp. 213102-1-213102-3. cited by other.
Noborisaka, J., et al., "Fabrication and characterization of freestanding GaAs/AlGaAs core-shell nanowires and AlGaAs nanotubes by suing selective-area metalorganic vapor phase epitaxy," Applied Physics Letters, vol. 87, Aug. 24, 2005, pp.093109-1-093109-3. cited by other.
Noda, et al., "Current-voltage characteristics in double-barrier resonant tunneling diodes with embedded GaAs quantum rings," Physica E 32, 2006, pp. 550-553. cited by other.
Norman, et al., "Characterization of MOCVD Lateral Epitaxial Overgrown III-V Semiconductor Layers on GaAs Substrates," Compound Semiconductors, Aug. 25-27, 2003, pp. 45-46. cited by other.
Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority for PCT/US2010/029552, Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., May 26, 2010, 14 pages. cited byother.
Oehrlein et al., "Studies of the Reactive Ion Etching of SiGe Alloys," J. Vac. Sci. Tech, A9, No. 3, May/Jun. 1991, pp. 768-774. cited by other.
Orihashi, et al., "Experimental and theoretical characteristics of sub-terahertz and terahertz oscillations of resonant tunneling diodes integrated with slot antennas," 44 Jap. J. Applied Physics, Part 1, No. 11, Nov. 2005, pp. 7809-7815. cited byother.
Parillaud et al., "High Quality InP on Si by Conformal Growth," Applied Physics Letters, vol. 68, No. 19, May 6, 1996, pp. 2654-2656. cited by other.
Park et al., "Defect Reduction and its Mechanism of Selective Ge Epitaxy in Trenches on Si(001) Substrates Using Aspect Ratio Trapping," Mat. Res. Society Symp. Proc., vol. 994, 2007, 6 pages. cited by other.
Park et al., "Defect Reduction of Selective Ge Epitaxy in Trenches on Si (001) Substrates Using Aspect Ratio Trapping,"Applied Physics Letters 90, 052113, Feb. 2, 2007, 3 pages. cited by other.
Park et al., "Fabrication of Low-Defectivity, Compressively Strained Geon Si.sub.0.2G.sup.e.sub.0.8 Structures Using Aspect Ratio Trapping," Journal of the Electrochemical Society, vol. 156, No. 4, 2009, pp. H249-H254. cited by other.
Park et al., "Growth of Ge Thick Layers on Si (001) Substrates Using Reduced Pressure Chemical Vapor Deposition," 45 Japan, Journal of Applied Physics, vol. 11, 2006, pp. 8581-8585. cited by other.
Partial International Search for International Application No. PCT/US2006/033859 mailed Jun. 22, 2007, 7 pages. cited by other.
Partial International Search Report for International Application No. PCT/US2008/004564 completed Jul. 22, 2009, mailed Oct. 16, 2009, 5 pages. cited by other.
Partial International Search Report for International Application No. PCT/US2008/068377, completed Mar. 19, 2008, mailed Apr. 22, 2008, 3 pages. cited by other.
PCT International Search Report of PCT/US2009/057493, from PCT/ISA/210, mailed Mar. 22, 2010, Applicant: Amberwave System Corporation et al., 2 pages. cited by other.
Pidin et al., "MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer for 65-nm Technology Node," Symposium on VLSI Technology, Dig. Tech. Papers, 2004, pp. 54-55. cited by other.
Piffault et al., "Assessment of the Strain of InP Films on Si Obtained by HVPE Conformal Growth," Indium Phosphide and Related Materials, Conference Proceedings, Sixth International Conference on Mar. 27-31, 1994, pp. 155-158. cited by other.
Pribat et al., "High Quality GaAs on Si by Conformal Growth," Applied Physics Letters, vol. 60, No. 17, Apr. 27, 1992, pp. 2144-2146. cited by other.
Prost, ed. "QUDOS Technical Report," 2002-2004, 77 pages. cited by other.
Prost, et al., "High-speed InP-based resonant tunneling diode on silicon substrate," Proceedings of the 31st European Solid-State Device Research Conf., 2005, pp. 257-260. cited by other.
Radulovic, et al., "Transient Quantum Drift-Diffusion Modelling of Resonant Tunneling Heterostructure Nanodevices," Physics of Semiconductors: 27.sup.th International Conference on the Physics of Semiconductors--ICPS-27, Jun. 2005 AIP Conf. Proc.,pp. 1485-1486. cited by other.
Reed et al., "Realization of a Three-Terminal Resonant Tunneling Device: The Bipolar Quantum Resonant Tunneling Transistor," 54 Applied Physics Letters 11, 1989, p. 1034. cited by other.
Ren et al., "Low-dislocation-density, Nonplanar GaN Templates for Buried Heterostructure Lasers Grown by Lateral Epitaxial Overgrowth," Applied Physics Letters, vol. 86, No. 11, Mar. 14, 2005, pp. 111901-1-3. cited by other.
Rim et al., "Enhanced Hole Mobilities in Surface-Channel Strained-Si p-MOSFETs," 1995 IEDM, pp. 517-520. cited by other.
Rim et al., "Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs," IEDM Tech. Dig., 2003, pp. 49-52. cited by other.
Ringel et al., "Single-junction InGaP/GaAs Solar Cells Grown on Si Substrates with SiGe Buffer Layers," Prog. Photovolt., Res. & Applied, vol. 10, 2002, pp. 417-426. cited by other.
Rosenblad et al., "A Plasma Process for Ultrafast Deposition of SiGe Graded Buffer Layers," 76 Applied Physics Letters 4, 2000, pp. 427-429. cited by other.
Sakai, "Defect Structure in Selectively Grown GaN Films with Low Threading Dislocation Density," Applied Physics Letters 71, vol. 16, 1997, pp. 2259-2261. cited by other.
Sakai, "Transmission Electron Microscopy of Defects in GaN Films Formed by Epitaxial Lateral Overgrowth," 73 Applied Physics Letters 4, 1998, pp. 481-483. cited by other.
Sakawa et al., "Effect of Si Doping on Epitaxial Lateral Overgrowth of GaAs on GaAs-Coated Si Substrate," Japan, Journal of Applied Physics, vol. 31, 1992, pp. L359-361. cited by other.
Pae, et al., "Multiple Layers of Silicon-on-Insulator Islands Fabrication by Selective Epitaxial Growth," Electron Device Letters, IEEE, vol. 20, No. 5, May 1999, pp. 194-196. cited by other.
Sass, et al., "Strain in GaP/GaAs and GaAs/GaP resonant tunneling heterostructures," Journal of Crystal Growth, vol. 248, Feb. 2003, pp. 375-379. cited by other.
Schaub, et al., "Resonant-Cavity-Enhanced High-Speed Si photodiode Grown by Epitaxial Lateral Overgrowth," Photonics Technology Letters, IEEE, vol. 11, No. 12, Dec. 1999, pp. 1647-1649. cited by other.
Seabaugh et al., Promise of Tunnel Diode Integrated Circuits,' Tunnel Diode and CMOS/HBT Integration Workshop, Naval Research Laboratory, Dec. 9, 1999, 13 pages. cited by other.
Shahidi, et al., "Fabrication of CMOS on Ultrathin SOI Obtained by Epitaxial Lateral Overgrowth and Chemical-Mechanical Polishing," Electron Devices Meeting, Technical Digest, International, Dec. 9-12, 1990, pp. 587-590. cited by other.
Shichijo et al., "Co-Integration of GaAs MESFET & Si CMOS Circuits," 9 Elec. Device Letters 9, Sep. 1988, pp. 444-446. cited by other.
Shubert, E.F., "Resonant tunneling diode (RTD) structures," Rensselear Polytechnic Institute, 2003, pp. 1-14. cited by other.
Siekkinen, et al., "Selective Epitaxial Growth Silicon Bipolar Transistors for Material Characterization," Electron Devices, IEEE Transactions on Electron Devices, vol. 35, No. 10, Oct. 1988, pp. 1640-1644. cited by other.
Su et al., "Catalytic Growth of Group 111-nitride Nanowires and Nanostructures by Metalorganic Chemical Vapor Deposition," Applied Physics Letters, vol. 86, 2005, pp. 013105-1-013105-3. cited by other.
Su et al., "New Planar Self-Aligned Double-Gate Fully-depleted P-MOSFETs Using Epitaxial Lateral Overgrowth (ELO) and selectively grown source/drain (S/D)," 2000 IEEE Int'l SOIi Conf., pp. 110-111. cited by other.
Suhara, et al, "Characterization of argon fast atom beam source and its application to the fabrication of resonant tunneling diodes," 2005 International Microprocesses and Nanotechnology Conf. Di. of Papers, 2005, pp. 132-133. cited by other.
Sun et al., Electron resonant tunneling through InAs/GaAs quantum dots embedded in a Schottky diode with an AlAs insertion layer,' 153 J. Electrochemical Society 153, 2006, pp. G703-706. cited by other.
Sun et al., "Room-temperature observation of electron resonant tunneling through InAs/AlAs quantum dots," 9 Electrochemical and Solid-State Letters 5, May 2006, pp. G167-170. cited by other.
Sun et al., "InGaAsP Multi-Quantum Wells at 1.5 /splmu/m Wavelength Grown on Indium Phosphide Templates on Silicon," Indium Phosphide and Related Materials, May 12-16, 2003, pp. 277-280. cited by other.
Sun et al., "Selective Area Growth of InP on InP Precoated Silicon Substrate by Hydride Vapor Phase epitaxy," Indium Phosphide and Related Materials Conference, IPRM. 14.sup.th, 2002, pp. 339-342. cited by other.
Sun et al., "Sulfur Doped Indium Phosphide on Silicon Substrate Grown by Epitaxial Lateral Overgrowth," Indium Phosphide and Related Materials 16.sup.th IPRM, May 31-Jun. 4, 2004, pp. 334-337. cited by other.
Sun et al., "Temporally Resolved Growth of InP in the Opening Off-Oriented from [110] Direction," Idium Phosphide and Related Materials, Conference Proceedings, 2000 International Conference, pp. 227-230. cited by other.
Sun et al., "Thermal Strain in Indium Phosphide on Silicon Obtained by Epitaxial Lateral Overgrowth," 94 Journal of Applied Physics 4, 2003, pp. 2746-2748. cited by other.
Suryanarayanan et al., "Microstructure of Lateral Epitaxial Overgrown InAs on (100) GaAs Substrates," Applied Physics Letters, vol. 83, No. 10, Sep. 8, 2003, pp. 1977-1979. cited by other.
Suzuki, et al., "Mutual injection locking between sub-THz oscillating resonant tunneling diodes," Japan Science and Technology Agency, IEEE, Joint 30.sup.th International Conference on Infrared and Millimeter Waves & 13.sup.th InternationalConference on Terahertz Electronics, 2005, pp. 150-151. cited by other.
Takasuka et al., "AlGaAs/InGaAs DFB Laser by One-Time Selective MOCVD Growth on a Grating Substrate," 43 Japan, Journal of Applied Physics, 4B, 2004, pp. 2019-2022. cited by other.
Takasuka et al., "InGaAs/AlGaAs Quantum Wire DFB Buried HeteroStructure Laser Diode by One-Time Selective MOCVD on Ridge Substrate," 44 Japan, Journal of Applied Physics, 4B, 2005, pp. 2546-2548. cited by other.
Tamura et al., "Heteroepitaxy on High-Quality GaAs on Si for Optical Interconnections on Si Chip," Proceedings of the SPIE, vol. 2400, 1995, pp. 128-139. cited by other.
Tamura et al., "Threading Dislocations in GaAs on Pre-patterned Si and in Post-patterned GaAs on Si," Journal of Crystal Growth, vol. 147, 1995, pp. 264-273. cited by other.
Tanaka et al., "Structural Characterization of GaN Lateral Overgrown on a (111) Si Substrate," Applied Physics Letters, vol. 79, No. 7, Aug. 13, 2001, pp. 955-957. cited by other.
Thean et al., "Uniaxial-Biaxial Hybridization for Super-Critical Strained-Si Directly on Insulator (SC-SSOI) PMOS with Different Channel Orientations," IEEE, 2005, pp. 1-4. cited by other.
Thelander, et al., "Heterostructures incorporated in one-dimensional semiconductor materials and devices," Physics of Semiconductors, vol. 171, 2002, 1 page. Abstract Only. cited by other.
Thompson et al., "A Logic Nanotechnology Featuring Strained-Silicon," 25 IEEE Electron Device Letters 4, 2004, pp. 191-193. cited by other.
Tomiya et al., "Dislocation Related Issues in the Degradation of GaN-Based Laser Diodes," Selected Topics in Quantum.Electronics, IEEE Journal of Selected Topics in Quantum Electronics, vol. 10, No. 6, Nov./Dec. 2004, pp. 1277-1286. cited by other.
Tomiya, "Dependency of crystallographic tilt and defect distribution of mask material in epitaxial lateral overgrown GaN layers," Applied Physics Letters vol. 77, No. 5, pp. 636-638. cited by other.
Tran et al., "Growth and Characterization of InP on Silicon by MOCVD," Journal of Crystal Growth, vol. 121, 1992, pp.365-372. cited by other.
Tsai, et al., "InP/InGaAs resonant tunneling diode with six-route negative differential resistances," 13th European Gallium Arsenide and other Compound Semiconductors Application Symp., 2006, pp. 421-423. cited by other.
Tsang et al., "The heteroepitaxial Ridge-Overgrown Distributed Feedback Laser," Quantum Electronics, IEEE Journal of Quantum Electronics, vol. 21, No. 6, Jun. 1985, pp. 519-526. cited by other.
Tsaur, et al., "Low-Dislocation-Density GaAs epilayers Grown on Ge-Coated Si substrates by Means of Lateral Epitaxial Overgrowth," Applied Physics Letters, vol. 41, No. 15, Aug. 1982, pp. 347-349. cited by other.
Tseng et al., "Effects of Isolation Materials on Facet Formation for Silicon Selective Epitaxial Growth," 71 Applied Physics Letters 16, 1997, pp. 2328. cited by other.
Tsuji et al., Selective Epitaxial Growth of GaAs on Si with Strained Sort-period Superlattices by Molecular Beam Epitaxy under Atomic Hydrogen Irradiation, J. Vac. Sci. Technol. B, vol. 22, No. 3, May/Jun. 2004, pp. 1428-1431. cited by other.
Ujiie, et al., Epitaxial Lateral Overgrowth of GaAs on a Si Substrate, 28, Japan, Journal of Applied Physics, vol. 3, Mar. 1989, pp. L337-L339. cited by other.
Usuda et al., "Strain Relaxation of Strained-Si Layers on SiGe-on-Insulator (SGOI) Structures After Mesa Isolation,"Applied Surface Science, vol. 224, 2004, pp. 113-116. cited by other.
Usui et al., "Thick GaN Epitaxial Growth with Low Dislocation Density by Hydride Vapor Phase Epitaxy," vol. 36, Japan, Journal of Applied Physics, 1997, pp. L899-L902. cited by other.
Vanamu et al., "Epitaxial Growth of High-Quality Ge Films on Nanostructured Silicon Substrates," Applied Physics Letters, vol. 88, 2006, pp. 204104.1-204-104.3. cited by other.
Vanamu et al., "Growth of High Quality Ge/Si.sub.1-xGe.sub.x on Nano-scale Patterned Si Structures," J. Vac. Sci. Technology B, vol. 23, No. 4, Jul./Aug. 2005, pp. 1622-1629. cited by other.
Vanamu et al., "Heteroepitaxial Growth on Microscale Patterned Silicon Structures," Journal of Crystal Growth, vol. 280, 2005, pp. 66-74. cited by other.
Vanamu et al., "Improving Ge Si.sub.sGe.sub.1-x Film Quality through Growth onto Patterned Silicon Substrates," Advances in Electronics Manufacturing Technology, Nov. 8, 2004, pp. 1-4. cited by other.
Vescan et al., "Lateral Confinement by Low Pressure Chemical Vapor Deposition-Based Selective Epitaxial Growth of Si.sub.1-xGe.sub.x/Si Nanostructures," No. 81, Journal of Applied Physics 10, 1997, pp. 6709-6715. cited by other.
Vetury et al., "First Demonstration of AIGaN/GaN Heterostructure Field Effect Transistor on GaN Grown by Lateral Epitaxial Overgrowth (ELO)," Inst. Phys. Conf. U.S. Appl. No. 162: Ch. 5, Oct. 1998, pp. 177-183. cited by other.
Walker, et al., "Magnetotunneling spectroscopy of ring-shaped (InGa)As quantum dots: Evidence of excited states with 2pz character," 32 Physica E 1-2, May 2006, pp. 57-60. cited by other.
Wang et al, "Fabrication of Patterned Sapphire Substrate by Wet Chemical Etching for Maskless Lateral Overgrowth of GaN," Journal of Electrochemical Society, vol. 153, No. 3, Mar. 2006, pp. C182-185. cited by other.
Ting, et al., "Modeling Spin-Dependent Transport in InAS/GaSb/AISb Resonant Tunneling Structures," 1 J.Computational Electronics, 2002, pp. 147-151. cited by other.
Watanabe, et al., "Fluoride resonant tunneling diodes on Si substrates," IEEE International Semiconductor Device Research Symp. Dec. 2005, pp. 177-178. cited by other.
Wernersson et al., "InAs Epitaxial Lateral Growth of W Marks," Journal of Crystal Growth, vol. 280, 2005, pp. 81-86. cited by other.
Williams et al., "Etch Rates for Micromachining Processing--Part II," Journal of Microelectromechanical Systems, vol. 4, 1996, pp. 761-778. cited by other.
Williams et al., "Etch Rates for Micromachining Processing--Part II," Journal of Microelectromechnical Systems, vol. 5, No. 4, Dec. 1996, pp. 256-269. cited by other.
Wu et al., "Enhancement-mode InP n-channel metal-oxide-semiconductor field-effect-transistors with atomic-layer-deposited A12O3 dielectrics," Applied Physics Letters 91, 022108-022110 (2007). cited by other.
Wu et al., Gross-Sectional Scanning/Tunneling Microscopy Investigations of Cleaned III-V Heterostructures, Technical report, Dec. 1996, 7 pages. cited by other.
Wu et al., "Inversion-type enhancement-mode InP MOSFETs with ALD Al2O3, HfAlO nanolaminates as high-k gate dielectrics," Proceedings of the 65th Device Research Conf., 2007, pp. 49-52. cited by other.
Wuu et al., "Defect Reduction and Efficiency Improvement of Near-Ultraviolet Emitters via Laterally Overgrown GaN on a GaN/Patterned Sapphire Template," Applied Physics Letters, vol. 89, No. 16, Oct. 16, 2006, pp. 161105-1-3. cited by other.
Xie et al., "From Porous Si to Patterned Si Substrate: Can Misfit Strain Energy in a Continuous Heteropitaxial Film Be Reduced?" Journal of Vacuum Science Technology, B, vol. 8, No. 2, Mar./Apr. 1990, pp. 227-231. cited by other.
Xu et al., "Spin-Filter Devices Based on Resonant Tunneling Antisymmetrical Magnetic Semiconductor Hybrid Structures," vol. 84, Applied Physics Letters 11, 2004, pp. 1955-1957. cited by other.
Yamaguchi et al., "Analysis for Dislocation Density Reduction in Selective Area Growth GaAs Films on Si Substrates," Applied Physics Letters, vol. 56, No. 1, Jan. 1, 1990, pp. 27-29. cited by other.
Yamaguchi et al., "Defect Reduction Effects in GaAs on Si Substrates by Thermal Annealing," Applied Physics Letters vol. 53, No. 23, 1998, pp. 2293. cited by other.
Yamaguchi et al., GaAs Solar Cells Grown on Si Substrates for Space Use: Prog. Photovolt.: Res. Appl., vol. 9, 2001; pp. 191-201. cited by other.
Yamaguchi et al., "Super-High-Efficiency Multi-junction Solar Cells," Prog. Photovolt.: Res. Appl., vol. 13, 2005, pp. 125-132. cited by other.
Yamamoto et al., "Optimization of InP/Si Heteroepitaxial Growth Conditions Using Organometallic Vapor Phase Epitaxy," Journal of Crystal Growth, vol. 96, 1989, pp. 369-377. cited by other.
Yang et al., "High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations," IEDM Tech Dig., 2003, pp. 453-456. cited by other.
Yang et al., "Selective Area Deposited Blue GaN-InGaN Multiple-quantum Well Light Emitting Diodes over Silicon Substrates," Applied Physics Letter, vol. 76, No. 3, Jan. 17, 2000, pp. 273-275. cited by other.
Yili, et al., "Physics-based hydrodynamic simulation of direct current characteristics in DBRTD," 29 Chinese J. Electron Devices 2, Jun. 2006, pp. 365-368. cited by other.
Yin et al., "Ultrathin Strained-SOI by Stress Balance on Compliant Substrates and Fet Performance," 52 IEEE Trans On Electron Devices 10, 2005, pp. 2207-2214. cited by other.
Dong et al., "Selective area growth of InP through narrow openings by MOCVD and its application to inP HBT," Indium Phosphide and Related Materials, International Conference, May 12-16, 2003, pp. 389-392. cited by other.
Yoon et al., "Selective Growth of Ge Islands on Nanometer-scale Patterned SiO.sub.2/Si Substrate by Molecular Beam Epitaxy," Applied Physics Letters, vol. 89, 2006, pp. 063107.1-063107.3. cited by other.
Yoshizawa et al., "Growth of self-Organized GaN Nanostructures on Al 2O3 (0001) by RF-Radial Source Molecular Beam Epitaxy", Japan, Journal of Applied Physics, Part 2, vol. 36, No. 4B, 1997, pp. L459-462. cited by other.
Zamir et al., Thermal Microcrack Distribution Control in GaN Layers on Si Substrates by Lateral Confined Epitaxy, Applied Physics Letters, vol. 78, No. 3, Jan. 15, 2001, pp. 288-290. cited by other.
Zang et al., "Nanoheteroepitaxial lateral overgrowth of GaN on nanoporous Si (111)," Applied Physics Letters, vol. 88, No. 14, Apr. 3, 2006, pp. 141925. cited by other.
Zang et al., "Nanoscale lateral epitaxial overgrowth of GaN on Si (111)," Applied Physics Letters, vol. 87, No. 19 (Nov. 7, 2005) pp. 193106.1-193106.3. cited by other.
Zela et al., "Single-crystalline Ge Grown Epitaxially on Oxidized and Reduced Ge/Si (100) Islands," Journal of Crystal Growth, vol. 263, 2004, pp. 90-93. cited by other.
Zhang et al., "Removal of Threading Dislocations from Patterned Heteroepitaxial Semiconductors by Glide to Sidewalls," Journal of Electronic Materials, vol. 27, No. 11, 1998, pp. 1248-1253. cited by other.
Zhang et al., "Strain Status of Self-Assembled InAs Quantum Dots," Applied Physics Letters, vol. 77, No. 9, Aug. 28, 2000, pp. 1295-1297. cited by other.
Zheleva et al., "Lateral Epitaxy and Dislocation Density Reduction in Selectively Grown GaN Structures," Journal of Crystal Growth, vol. 222, No. 4, Feb. 4, 2001, pp. 706-718. cited by other.
Zubia et al., "Initial Nanoheteroepitaxial Growth of GaAs on Si (100) by OMVPE," Journal of Electronic Materials, vol. 30, No. 7, 2001, pp. 812-816. cited by other.
1. A sensor, comprising: a substrate configured with at least one depression in the substrate; an insulator in the at least one depression in the substrate and configured to form atleast two openings to the substrate, the insulator overlying sides of the at least one depression to form the at least two openings; a first epitaxial crystalline structure in at least a portion of a first of the at least two openings; a secondepitaxial crystalline structure in at least a portion of a second of the at least two openings, the first and second epitaxial crystalline structures interfacing at a coalesced portion over the insulator; a sensing region formed at or in the coalescedportion to output electrons generated by light absorption therein; and contacts coupled to receive the electrons to obtain an output electric signal.
4. The sensor of claim 1, wherein at least two openings include trenches formed in a crystalline substrate.
5. The sensor of claim 1, wherein the sensing region comprises a p-n junction or a p-i-n structure.
6. The sensor of claim 1, wherein the sensor is a photodetector pixel of a semiconductor device; the photodetector pixel is a complementary-metal-oxide-semiconductor photodetector; and the photodetector comprises a p-n junction or a p-i-nstructure and a metal-oxide-semiconductor transistor, wherein the p-n junction or a p-i-n structure is formed in the sensing region, and wherein the photodetector is an IR or UV detector.
7. The sensor of claim 1, wherein the coalesced portion has a width of 1 micron or larger.
8. The sensor of claim 1, comprising: a p-i-n structure formed within the substrate; and an intrinsic region of the p-i-n structure is positioned to receive light in the sensing region.
9. The sensor of claim 1, wherein the first and second epitaxial crystalline structures comprise semiconductor materials among a group II-VI compound, a group III-V compound, group III-N compound or ternary and quaternary compounds thereof or agroup IV material.
10. The sensor of claim 1, wherein each of the first and second epitaxial crystalline structures are lattice mismatched to the substrate.
11. The sensor of claim 10, wherein an aspect ratio of at least one of the at least two openings is 0.5 or greater, wherein each of the openings is a trench, recess or hole.
12. The sensor of claim 10, wherein each of said first and second epitaxial crystalline structures comprise an epitaxial lateral overgrowth (ELO) region, wherein said ELO region is at least 2 times a width of the opening.
13. A semiconductor sensor, comprising: a crystalline substrate having a recessed portion from a top surface of the crystalline substrate; an insulator in the recessed portion of the crystalline substrate, the insulator having a plurality ofopenings to the crystalline substrate in the recessed portion; a first crystalline material within the openings in the insulator, the first crystalline material being lattice-mismatched with the substrate; a second different buffer crystalline materialbeing lattice-mismatched with the crystalline substrate between the crystalline substrate and the first crystalline material; a light-sensing device in a least a portion of the first crystalline material to output electrons generated by light absorptiontherein; and contacts coupled to receive the electrons generated by light absorption to obtain an output electric signal.
14. The sensor of claim 13, wherein the second different buffer crystalline material has a thickness over the substrate less than 100 nm.
15. The sensor of claim 13, wherein the first crystalline material comprises a group II-VI compound or ternary and quaternary compounds thereof, a group III-V compound or ternary and quaternary compounds thereof, group III-N compound or ternaryand quaternary compounds thereof or a group IV material.
There is a constant drive within the semiconductor industry to increase the performance and reduce the cost of semiconductor devices, such as photodetectors, diodes, light-emitting diodes, transistors, latches, and many other semiconductordevices. This drive has resulted in continual demands for integrating one type of semiconductor devices into another semiconductor process.
For example in photodetectors that are comprised of an array of p-n junctions or p-i-n structures, it is advantages to make the p-n junctions and/or p-i-n structures with low band-gap materials, such as germanium (Ge) and InGaAs, because thephotodetectors are able to detect infrared light. In favor of the cost-efficiency, it is desired to produce a thin film of III-V or other non-silicon materials on low-cost large-size silicon wafers to reduce the cost of high performance III-V devices. It is further desired to integrate non-silicon p-n junctions and/or p-i-n structures (e.g. Ge or InGaAs based) into a silicon process such that other circuitry in a systems, such as a photodetector, can be fabricated using a standard silicon process,such as a standard CMOS (complementary-metal-oxide-semiconductor) process. It is also desirable to fabricate the non-silicon devices and silicon CMOS in a co-planar manner, so that the interconnection and integration of the whole system can be conductedin a manner compatible with standard and low-cost CMOS process. Further, it is desirable to increase a size of non-silicon regions configured to output electrons generated by light absorption therein.
FIG. 1a diagrammatically illustrates a first step of an exemplary method of making a semiconductor device;
FIG. 1b diagrammatically illustrates a second step of the exemplary method of making the semiconductor device;
FIG. 1c diagrammatically illustrates a third step of the exemplary method of making the semiconductor device;
FIG. 1d diagrammatically illustrates a fourth step of the exemplary method of making the semiconductor device;
FIG. 19a diagrammatically illustrates a cross-sectional view of a portion of an exemplary array of non-silicon photodetectors integrated in a silicon substrate, wherein the photodetector is capable of detecting light incident thereto from thetop;
FIG. 20a diagrammatically illustrates a cross-sectional view of a portion of an exemplary array of non-silicon photodetectors integrated in a silicon substrate, wherein the photodetector is capable of detecting light incident thereto from theside;
FIG. 21a diagrammatically illustrates a first view of an exemplary configuration of electrical connections of photodetectors to electrical contacts;
FIG. 21b diagrammatically illustrates a second view of the exemplary configuration of electrical connections of photodetectors to electrical contacts; and
The method enables integration of non-silicon semiconductor devices into a silicon process such that silicon circuitry of the semiconductor device can be formed through standard silicon processes. This integration capability can be of greatimportance in using low band-width or high band-width semiconductor materials for making semiconductor device having p-n and p-i-n structures in silicon processes.
The method also enables forming ART (aspect-ratio-trapping) crystalline structures in a trench structure, such as a trench structure patterned by a trench patterning-process (e.g. a standard complementary-metal-oxide-semiconductor (CMOS) STI(shallow-trench-insulation) process) or a STI-like trench patterned structure. The semiconductor devices formed at or in the ART structure(s) can have any desired lateral and/or vertical dimensions that are substantially free from the aspect-ratiorequirements or process limitations in most current ART techniques. For demonstration and simplicity purposes, the method will be discussed with reference to selected examples wherein ART crystalline structures are formed on STI process trenchstructures in some of the examples. It will be appreciated by those skilled in the art that the exemplary methods as discussed in the following can also be implemented to form ART structures on other types of trenches.
Aspect Ratio Trapping (ART) is a defect reduction and heteroepitaxy growth technique. As used herein, "ART" or "aspect ratio trapping" refers generally to the technique(s) of causing defects to terminate at non-crystalline, e.g., dielectricsidewalls during heteroepitaxy growth, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects. ART utilizes high aspect ratio openings, such as trenches or holes, to trapdislocations, preventing them from reaching the epitaxial film surface, and greatly reduces the surface dislocation density within the ART opening. Further details of example ART devices and ART techniques in which this invention are described in U.S. patent application Ser. No. 11/436,198 filed May 17, 2006, Ser. No. 11/493,365 filed Jul. 26, 2006 and Ser. No. 11/852,078 filed Sep. 7, 2007, all of which are hereby incorporated by reference.
Furthermore, with customized ART growth parameters, an enhanced lateral epitaxy overgrowth (ELO) mode may be realized for expanded epitaxy beyond the trenched region, e.g., regions with openings formed therein, which yields bulky "free-standing"high quality materials centered above the initial trenched seed layer. Therefore, a combined ART and ELO technology greatly increases the quality and applicable film surface area of lattice-mismatched materials on substrates such as Si substrates. Therelatively simple process enables reliable and reproducible results.
The method further enables forming a large-scale ART structure in the presence of STI process trenches, which in turn enables forming a semiconductor device or an element of a semiconductor device with desired lateral or vertical dimension. Inparticular, a large-scale intrinsic semiconductor region can be formed in the large-scale ART structure.
The method enables forming a semiconductor device or an element of a semiconductor device on a buffer layer disposed on a semiconductor crystalline substrate, whereas the buffer layer can be graded. The buffer layer can be disposed within anopening formed in a dielectric layer or can be disposed in a trench formed in a crystalline substrate.
In a particular implementation, the method is capable of being used for making a semiconductor device having complementary-metal-oxide-semiconductor device with a photodetector that is formed at or in an ART structure. Other non-silicon orsilicon based circuitry can also be formed along with the photodetector.
The method and semiconductor devices made thereof will be discussed in the following with selected examples. It will be appreciated by those skilled in the art that the following discussion is for demonstration purposes and should not beinterpreted as a limitation. Other variations within the scope of this disclosure are also applicable.
Referring to the drawings, FIG. 1a through FIG. 1d diagrammatically illustrate an exemplary method of making an epitaxial structure using an aspect-ratio-trapping (ART) technique. Referring to FIG. 1a, substrate 100 is provided, which can be asemiconductor crystalline substrate, such as a silicon substrate. Dielectric layer 102 comprised of a dielectric material is deposited on substrate 100. The dielectric material can be any suitable materials, which is preferably, though not required, anoxide or nitride of a semiconductor element, such as SiO.sub.x and SiN.sub.x. Other materials are also applicable, such as an oxide or nitride of a metal element, a metal alloy, or a ceramic material.
Screen layer 104 is deposited on dielectric layer 102. The screen layer is comprised of a material that is highly selective to the etching process to be used for etching substrate 100. For example, screen layer 104 can be comprised ofTiN.sub.x when a dry etching process is to be performed for forming trenches in substrate 100.
The substrate (100) can be etched by a selected etching process so as to form openings, such as opening 106 in FIG. 1b. Due to the selectivity of the screen layer (104) to the etching process, the trench (e.g. 106) in the substrate (100) canhave a larger depth or width while still maintaining the desired aspect ratio for the following ART growth. In one example, the opening (106) can have a depth of 100 nanometers or larger, 200 nanometers or larger, 500 nanometers or larger, 1 micron orlarger, such as 1.5 micron or larger, 2 microns or larger, 3 microns or larger, or 5 microns or larger. The opening (106) may have a width of 20 nanometers or larger, 100 nanometers or larger, 500 nanometers or larger, 1 micron or larger, such as 1.5micron or larger, 2 microns or larger, 3 microns or larger, or 5 microns or larger. The aspect ratio of the opening (106) can be 0.5 or higher, such as 1 or higher, 1.5 or higher.
The opening can then be filled with a selected dielectric material so as to coat the sidewalls (108) of the opening for the following ART growth in the opening. In one example, dielectric layer (108) at the sidewalls of the opening can becomprised of an oxide (e.g. SiO.sub.x), a nitride, (e.g. TiN.sub.x), or other suitable materials. In another example, the dielectric layer (108) at the sidewall of the opening can be comprised of TiN.sub.x or a material having a free-surface energysubstantially equal to or higher than that of TiN.sub.x.
After coating the sidewalls of the opening (106), the dielectric layer can be etched so as to remove the dielectric material at the bottom portion (110) of the opening for exposing the underneath substrate (100), as diagrammatically illustratedin FIG. 1c.
In the formed opening 106 as shown in FIG. 1c, an ART process can be performed so as to form epitaxial material 112 as diagrammatically illustrated in FIG. 1d. Exemplary methods for ART processes are set forth in U.S. patent application Ser. Nos. 11/436,198 filed May 17, 2006, Ser. No. 11/493,365 filed Jul. 26, 2006 and Ser. No. 11/852,078 filed Sep. 7, 2007, all of which are hereby incorporated by reference in entirety. The ART structure is comprised of a semiconductor material. Forexample, the ART structure may be comprised of a group IV element or compound, a III-V or III-N compound, or a II-VI compound. Examples of group IV elements include Ge and Si; and examples of group IV compounds include SiGe (examples of III-V compoundsinclude aluminum phosphide (AlP), gallium phosphide (GaP), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), indium arsenide (InAs), aluminum antimonide (AlSb), gallium antimonide (GaSb), indium antimonide (InSb), and theirternary and quaternary compounds. Examples of III-N compounds include aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), and their ternary and quaternary compounds. Examples of II-VI compounds includes zinc selenide (ZnSe), zinctelluride (ZnTe), cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS), and their ternary and quaternary compounds.
The above method of forming ART epitaxial structures and the epitaxial ART structures made thereof have many advantages. For example wherein the substrate is a silicon substrate, a non-silicon crystalline material, such as germanium or othersemiconductor materials, can be formed in the trench of the substrate. As a consequence, a non-silicon semiconductor device can be formed at or in the non-silicon crystalline ART material, such as a germanium based p-n or p-i-n structure. Other siliconcircuitry of the semiconductor device can thus be formed in or at the silicon substrate using standard silicon processes, as example of which will be described afterwards with reference to FIG. 5.
In another example, the above method enables photodetector pixels to be integrated into a silicon process. A photodetector pixel comprises a p-n or p-i-n structure and associated circuitry, such as signal converting circuits. In someapplications, it is desired to make the p-n or p-i-n structure using a low band-gap material, such as Ge, InGaAs, SiGe, and InP for detecting infrared light. In some other examples, a p-n junction made from a high band-gap semiconductor material, suchas GaN and InP) is desired for detecting ultra-violet light. The non-silicon semiconductor elements (e.g. the p-n junction or p-i-n structure) can be formed at or in the ART epitaxial structure comprised of the non-silicon semiconductor material, suchas Ge and InGaAs. Other circuitry of the photodetector can be formed by using standard silicon processes, such as a standard CMOS process. When the photodetector is desired to have a size larger than a critical threshold, such as equal to or largerthan 2 microns, or from 2 to 5 microns, an opening in the silicon substrate can be made to have a width equal to or larger than the desired size of the photodetector, such as equal to or larger than 2 microns, or from 2 to 5 microns. The ART epitaxialcrystalline structure formed in the opening can thus have a width equal to or larger than the desired size of the photodetector. Further, desired A/R can simultaneously be maintained.
In addition to forming an ART epitaxial crystalline structure within a wide opening in a substrate, an ART with a large dimension can alternatively be obtained through overgrowing, as diagrammatically illustrated in FIG. 2. Referring to FIG. 2,an opening can have a width W.sub.b is formed in a substrate using, for example a STI technique. By overgrowing the ART crystalline structure (114) within the opening, an overgrown crystalline portion (116) can be obtained. The overgrown crystallineportion (116) can have a height H that is 1.5 times or more, 2 times or more, 5 times or more, 10 times or more, or from 5 to 10 times of the height of the opening formed in the substrate. The overgrown crystalline portion (116) can have a width W thatis 1.5 times or more, 2 times or more, 5 times or more, 10 times or more, or from 5 to 10 times of the width W.sub.b of the opening formed in the substrate.
The large lateral dimension of the overgrown portion (116) can also be obtained from ELO (epitaxial-lateral-overgrowth). The ELO can be isotropic or anisotropic. For obtaining a flat surface of the overgrown portion (116), a CMP (chemicalmechanical polishing) process can be performed. The overgrown portion (116) can further be patterned so as to obtain desired dimensions (lateral and vertical dimensions and/or the shape) using for example, a photolithography process.
A semiconductor device or an element of a semiconductor device having a large size (e.g. equal to or larger than 2 microns) can then be formed in the overgrown crystalline portion (116). For example, a p-n or p-i-n structure with a size of 100nanometers or more, 500 nanometers or more, 1 micron or more, 2 microns or more, 5 microns or more, or 10 microns or more, or from 5 to 10 microns can be formed at or in the overgrown crystalline portion (116).
Large ART crystalline structures can alternatively be obtained by forming the ART crystalline structure within a large trench formed in a substrate, as diagrammatically demonstrated in FIG. 3. Referring to FIG. 3, an opening with a large width,such as 100 nanometers or larger, 500 nanometers or larger, 1 micron or larger, 2 microns or larger, 5 microns or larger, 10 microns or larger, or 100 microns or larger, and more preferably from 100 nanometers to 20 microns, and more preferably, from 2to 5 microns, is formed in substrate 100 that can be a semiconductor crystalline substrate, such as a silicon substrate. Dielectric patterns, such as dielectric sidewall 101 and dielectric isolators 120 and 124 can be formed in the opening. Thedielectric patterns are provided for enabling the following ART processes for forming ART epitaxial crystalline structures 118, 122, 126, and 128. Specifically, the dielectric patterns 101 and 120 define an opening with an aspect ratio commensurate withthe aspect ratio needed for forming an ART epitaxial crystalline structure in the opening between patterns 101 and 120. The dielectric patterns 120 and 124 define an opening with an aspect ratio commensurate with the aspect ratio needed for forming anART epitaxial crystalline structure in the opening between patterns 120 and 124. The dielectric patterns 124 and 103 define an opening with an aspect ratio commensurate with the aspect ratio needed for forming an ART epitaxial crystalline structure inthe opening between patterns 124 and 103. Such dielectric patterns can be formed in multiple layers (e.g., stacked three or more vertically).
The dielectric patterns can be formed in many ways. In one example, after forming the large trench in substrate 100 by for example, a STI process, a dielectric layer having a dielectric material for dielectric patterns is deposited in the largeopening. The deposited dielectric layer can be patterned to have a depth H.sub.d measured from the bottom of the large opening to the top surface of the patterned dielectric layer. The depth H.sub.d can have any suitable values, which is preferablyequal to or larger than the threshold height within which the ART epitaxial structure formed in an opening (e.g. the opening between dielectric pattern 101 and 120) has dislocation defects.
The patterned dielectric layer in the large opening can be further patterned so as to form dielectric patterns 101, 120, 124, and 103. The bottom portions of the openings between dielectric patterns 101 and 120, between 120 and 124, and between124 and 103 are removed so as to expose the substrate 100.
With the dielectric patterns formed in the large opening, an ART process can be performed so as to form ART epitaxial structures 118, 122, and 126. By overgrowing the ART structures 118, 122, and 126, overgrown crystalline portion 128 with alarge size can be obtained. The overgrown crystalline portion (128) can have a width W.sub.in that is substantially equal to the width of the large opening formed in substrate 100. For example, the overgrown crystalline portion (128) can have a widthW.sub.in of 100 nanometers or larger, 500 nanometers or larger, 1 micron or larger, 2 microns or larger, 5 microns or larger, 10 microns or larger, or 20 microns or larger, and more preferably, from 2 to 5 microns. A semiconductor device or an elementof a semiconductor device with a desired large size (e.g. 100 nanometers or larger, 500 nanometers or larger, 1 micron or larger, 2 microns or larger, 5 microns or larger, 10 microns or larger, or 20 microns or larger, and more preferably, from 2 to 5microns) can thus be formed at or in the overgrown crystalline portion (128).
The openings formed in a substrate by using trenches, recesses, openings or the like as described above can have any desired shapes or layouts, an exemplary of which is diagrammatically illustrated in a top view in FIG. 4. Referring to FIG. 4,an opening can have other shapes such as a 90.degree. angle shape, such as opening 130. Of course, an opening can have other shapes, such as circular, donut, polygonal, and many other possible shapes. Multiple openings can be formed in the openingwith any desired layouts. For example, rectangular openings 134 and 132 can be perpendicular or parallel or can be arranged to have any desired angles therebetween.
Exemplary methods as described above with reference to FIG. 1a through FIG. 1d or FIG. 2 can enable integration of non-silicon semiconductor devices into a silicon process. For demonstration purposes, FIG. 5 diagrammatically illustrates one ofthe examples. Referring to FIG. 5, openings are formed by using a STI process in silicon substrate 100. Germanium (or InGaAs or other semiconductor materials such as a III-V group semiconductor material) ART crystalline structures 138 and 140 areformed in the STI openings in silicon substrate 100. Germanium based (or InGaAs or other semiconductor materials such as a III-V group semiconductor material based) semiconductor devices 146 and 150, such as photodetectors are formed at ART structures138 and 140. A buffer layer (e.g., 10-100 nm) can be between the substrate 100 and the ART crystalline structures 138 and 140 for bonding, adhesion or improved device characteristics purposes. Silicon based devices or elements of semiconductor devices144, 148 and 152 are formed at the patterns of substrate 100 using standard silicon processes, such as CMOS processes. As such, non-silicon semiconductor devices of elements of non-silicon based semiconductor devices are integrated (e.g., co-planar) inthe silicon process.
In examples of forming ART epitaxial structures in STI trenches that are formed in a substrate, such as a silicon substrate, the substrate patterns, such as the silicon patterns around the openings, can be treated. For example, the substratepatterns can be intentionally passivated for protecting the substrate patterns and the ART structures. This can be of great importance when the thermal and/or mechanical properties of the substrate and the ART structures mismatch, which may causephysical and/or chemical damages to the ART structures and/or to the substrate patterns due to the mismatch. For example, physical damages may occur to the ART structures and/or the substrate patterns when the CET (coefficient-of-thermal-expansion) ofthe ART structures and the substrate patterns do not match. In one example, the substrate patterns can be passivated by oxidization or nitridization so as to form a protection layers on the exposed surfaces of the substrate patterns or the interfacesbetween the substrate patterns and the ART structures.
As an exemplary implementation of the method and the structure as described above with reference to FIG. 2, an exemplary structure having a p-i-n structure formed in an ART epitaxial crystalline structure is diagrammatically illustrated in FIG.6. Referring to FIG. 6, STI trench 107 is formed in semiconductor substrate 100, which can be a silicon substrate or other semiconductor substrates. Isolation patterns 154 and 155 are formed within the STI trench (107) and define opening 157therebetween. Opening 157 can have a height that is substantially equal to or larger than the critical height under which the ART crystalline structure formed in the opening 157 has dislocation defects and above which the ART crystalline structure issubstantially free from dislocation defects. An ART epitaxial crystalline structure can be grown in opening 157. By overgrowing the ART structure in opening 157, a large ART overgrown portion 156 is obtained.
A p-i-n structure having p-type region 158, intrinsic region 160, and n-region 162 is formed in overgrown crystalline portion 156. The p-type region 158 and the n-type region 162 can be obtained by doping. Because the overgrown crystallineportion 160 can have a large size, such as 100 nanometers or larger, 500 nanometers or larger, 1 micron or larger, 2 microns or larger, 5 microns or larger, 10 microns or larger, or 20 microns or larger, and more preferably, from 2 to 5 microns, theintrinsic i region 160 can be large, such as 100 nanometers or larger, 500 nanometers or larger, 1 micron or larger, 2 microns or larger, 5 microns or larger, 10 microns or larger, and more preferably, from 2 to 5 microns.
Other circuitry can be formed on the patterned semiconductor substrate 100, such as the transistor having source 164, gate 166, and drain 168, the transistor having source 170, gate 172, and drain 174, and the transistor having source 178, gate180, and drain 182. The source, gate, and drain of a transistor can be formed by a standard silicon process, such as a CMOS process. For example, the sources and drains of the transistors can be formed by doping; and the gates of the transistors can beformed by a standard silicon based lithography process. Other features can also be formed in the substrate (100). For example, isolation unit 176 can be formed between transistors so as to isolating the transistors. In one example, the semiconductordevice (e.g. 156) formed on the ART structure can be substantially coplanar with one or more other semiconductor devices (e.g. transistors) on substrate 100. For example, the top surfaces of 158, 160, and 162 of device 156 can be made substantiallycoplanar with the transistors formed on substrate 100.
As an exemplary implementation of the method and the structure as described above with reference to FIG. 3, an exemplary structure having a p-i-n structure formed in an ART epitaxial crystalline structure is diagrammatically illustrated in FIG.7. Referring to FIG. 7, STI trench 109 is formed in semiconductor substrate 100, which can be a silicon substrate or other semiconductor substrates. Multiple isolation patterns, such as dielectric pattern 154 are formed within the STI trench (109)using for example the method as described above with reference to FIG. 3, which will not be repeated herein. Openings 184, 186, and 188 are defined by the isolation patterns.
ART epitaxial crystalline growth can be performed in the openings 184, 186, and 188. By overgrowing or through the combination of overgrowing and coalescing of ELO portions of the ART structures in openings 184, 186, and 188, overgrowncrystalline portion 196 is obtained. The overgrown crystalline portion 196 can have a large dimension, such as a lateral and/or vertical dimensions of 100 nanometers or larger, 500 nanometers or larger, 1 micron or larger, 2 microns or larger, 5 micronsor larger, 10 microns or larger, and preferably, from 2 to 5 microns.
A p-i-n structure having p-type region 192, intrinsic region 190, and n-region 194 is formed in overgrown crystalline portion 196. The p-type region 192 and the n-type region 194 can be obtained by doping. Because the overgrown crystallineportion 196 can have a large size, the intrinsic i region 190 can be large, such as 100 nanometers or larger, 500 nanometers or larger, 1 micron or larger, 2 microns or larger, 5 microns or larger, 10 microns or larger, and more preferably from 100nanometers to 200 microns, and preferably, from 2 to 5 microns.
Other circuitry can be formed on the patterned semiconductor substrate 100, such as the transistor having source 164, gate 166, and drain 168. The source, gate, and drain of a transistor can be formed by a standard silicon process, such as aCMOS process. For example, the sources and drains of the transistors can be formed by doping; and the gates of the transistors can be formed by a standard silicon based lithography process. Other features can also be formed in the substrate (100). Forexample, isolation unit 176 can be formed between transistors so as to isolating the transistors. In one example, the semiconductor device (e.g. 196) formed on the ART structure can be substantially coplanar with one or more other semiconductor devices(e.g. transistors) on substrate 100. For example, the top surfaces of 192, 190, and 194 of device 196 can be made substantially coplanar with the transistors formed on substrate 100.
As can be seen in the examples as illustrated in FIG. 6 and FIG. 7, lateral p-i-n structures or p-n junctions can be made in ART epitaxial crystalline semiconductor structures, wherein the semiconductor structures can be comprised of non-siliconmaterials. For example, the carrier channel from the p region to the n region of a lateral p-i-n or p-n junction is parallel to the major surface of the substrate (100) or is substantially perpendicular to the direction along which the ART epitaxialcrystalline materials are formed.
The method of making a semiconductor device can be of great importance in making photodetector pixels that are comprised of an array of p-i-n structures. For demonstration purposes, FIG. 8 through FIG. 14 diagrammatically demonstrate a portionof an array of photodetector pixels that are formed by exemplary methods as described above. In particular, non-silicon semiconductor devices (e.g. non-silicon semiconductor sensor 214) can be integrated with silicon semiconductor devices (e.g. silicontransistors 208, 209, 202, and 204) using the method as discussed above. Referring to FIG. 8, four photodetector pixels of the photodetector array are shown for simplicity purposes. In general, the photodetector array may comprise any desired number ofphotodetector pixels, which is referred to as the native resolution of the photodetector array. In one example, the photodetector array may have a native resolution of 640.times.480 (VGA) or higher, such as 800.times.600 (SVGA) or higher, 1024.times.768(XGA) or higher, 1280.times.1024 (SXGA) or higher, 1280.times.720 or higher, 1400.times.1050 or higher, 1600.times.1200 (UXGA) or higher, and 1920.times.1080 or higher, or integer multiples and fractions of these resolutions. Of course, otherresolutions are also applicable depending upon specific applications.
Each photodetector can have a characteristic size of less than 500 nanometers, 500 nanometers or larger, 1 micron or larger, such as 1.5 microns or larger, 2 microns or larger, 5 microns or larger, 10 microns or larger, or from 5 to 10 microns. The pitch, which is referred to as the distance between adjacent photodetectors in the array, can be any suitable values, such as 500 nanometers or larger, 1 micron or larger, such as 1.5 microns or larger, 2 microns or larger, 5 microns or larger, 10microns or larger, or from 5 to 10 microns.
The portion of the exemplary photodetector array 200 comprises transistors 202, 204, 206, 208, 209, 210, 212, 218, 220, 224, 226, 230, and 232, and photo-sensors 214, 216, 222, and 228. The photo-sensors convert the light energy into voltagesignals, and a group of transistors amplify the voltage signals (and convert the amplified voltage signals into digital signals if necessary). Another group of transistors can be provided for addressing and reading out the outputs of individualphotodetector pixels in the columns and rows of the array by column and row addressing/reading signals.
For example, sensor 214 converts the received light intensity into a voltage signal. When an active signal (column signal) is delivered to transistor 209 through transistor 204 from a column decoder (which not shown in the figure), the outputvoltage signal from sensor 214 is amplified by transistor 208. When a row signal (row active signal) is delivered to the gate of transistor 209 through transistor 230, the amplified voltage signal V.sub.DD is read out through the output of transistor208. The output voltage signal V.sub.DD can be digitized by other devices, such as an ADC unit, which is not shown in the figure.
The sensors (214, 216, 222, and 228) each can be a p-i-n structure as diagrammatically illustrated in FIG. 9. Referring to FIG. 9, sensor 214 comprises p region 234, i region 236, and n region 238. The p-i-n structure (214) can be formed inmany ways, such as those described above with reference to FIG. 5, FIG. 6, and FIG. 7. Electron transportations properties of the p-i-n structure can be interpreted by energy band diagrams as diagrammatically illustrated in FIG. 9 and FIG. 10.
Referring to FIG. 9, the conductive and covalence bands of the p region 234, i region 236, and n region 238 are substantially flat in the absence of external voltages. Fermi energy E.sub.f is close to the covalence band of the p region suchthat the p region is a hole-rich region. Because the i region is an intrinsic semiconductor region, the Fermi energy E.sub.f is around the center of the gap between the covalence and conductive bands. Fermi energy E.sub.f is close to the conductiveband of the n region such that the n region is an electron-rich region.
In the presence of external voltage V+ and V- respectively applied to the n and p regions, as diagrammatically illustrated in FIG. 10, the conductive and covalence bands of the p region is elevated; while the conductive and covalence bands ofthe n region is declined. As a consequence, the conductive and covalence bands of the intermediate i region inclines. The Fermi energy E.sub.f also inclines the energy gap of the i region. The inclined Fermi energy drives electrons in the i regiontowards the n region; and holes in the i region toward the p region. This transportation of electrons and holes forms current in a carrier channel connecting the p and n regions.
The transistors and sensors of the photodetectors illustrated in FIG. 8 can be formed on ART epitaxial crystalline structures, which can be better illustrated in FIG. 11. For simplicity purposes, sensor 214 and the transistors around sensor 214are shown in FIG. 11. The exemplary connection of sensor 214 to the transistors is also applicable to other sensors and transistors.
Referring to FIG. 11, sensor 214 has p, i, and n regions; and sensor 214 can be a non-silicon semiconductor device. The transistors 202, 204, 208, and 209 can be silicon based transistors. The p region is grounded and is connected to the drainof transistor 202. The source of transistor 202 is connected to reset signal p region V.sub.RST. The p region of sensor 214 is connected to the gate of transistor 208. The source of transistor 208 acts as an output for outputting amplified voltagesignal V.sub.DD. The drain of transistor 208 is connected to the source of transistor 209. The gate of transistor 209 is connected to the source of row selection transistor 230, whose gate is connected to the row signal from a row decoder. The drainof transistor 230 is connected to amplified voltage signal V.sub.DD.
The transistors in FIG. 11 can have any suitable configurations. In particular, the non-silicon semiconductor sensor (214) can be integrated with the silicon-based transistors (e.g. 202, 208, 209, 204, and 230). Alternatively, the transistorssuch as transistor 202 can be other types of transistors, such as germanium (or other silicon or non-silicon) based transistors as diagrammatically illustrated in FIG. 12. Referring to FIG. 12, a trench 235 or an opening is formed in a siliconsubstrate. The sidewalls of the trench are covered with a dielectric layer, such as an oxide layer 243. The sidewall cover layer (243) can be formed in many ways. For example, the sidewall cover layer (243) can be formed by depositing or growing thesidewall cover layer in the trench followed by removing the cover layer on the bottom surface of the trench. Alternatively, the trench can be filled with the sidewall cover layer followed by patterning/etching to form the desired sidewall cover layer inthe trench. A germanium (or other silicon or non-silicon semiconductor materials) epitaxial crystalline structure 234 is formed in the trench of the silicon substrate using, for example, the method as discussed above with reference to FIG. 6. Source236 and drain 238 of the transistor are formed in the germanium epitaxial crystalline structure (234) by doping. Gate 241 is formed on the germanium crystalline structure with an oxide layer laminated therebetween.
Another exemplary configuration of the transistors in FIG. 11 is diagrammatically illustrated in FIG. 13. Referring to FIG. 13, the transistor is formed on a silicon substrate. Dielectric patterns 242 are formed so as to define an opening onthe silicon substrate. The dielectric patterns can be formed by depositing a layer of a selected dielectric material, such as TiN.sub.x on the silicon substrate followed by patterning the deposited dielectric layer.
The opening defined by the dielectric patterns has an appropriate aspect ratio, such as 0.5 or larger, 1 or larger, 1.5 or larger or 3 or larger, such that an ART growth process can be performed within the opening. Germanium epitaxialcrystalline structure 148 can then be formed in the opening through an ART process. By doping portions of the germanium crystalline structure, source 236 and drain 238 can be obtained with an intrinsic region being laminated therebetween. Gate 241 canbe formed above the germanium epitaxial crystalline structure with an oxide layer disposed therebetween.
In examples wherein the sensors of the photodetectors illustrated in FIG. 11 desired large areas, such as 1 micron or larger, 2 microns or larger, 5 microns or larger, 10 microns or larger, or from 5 to 10 microns, the p-i-n structure of thesensor can be formed using methods as described above with reference to FIG. 1, FIG. 2 or FIG. 7 or the like. For demonstration purposes, FIG. 14 diagrammatically illustrates an exemplary electrical connection of the p-i-n structure of the sensor to atransistor. This connection scheme is also applicable to connections of other sensors and transistors.
Referring to FIG. 14, an array of STI process trench structures (or other types of trench structures) 244, 246, 248, 250, and 252 are formed in a silicon substrate. The STI process trench structures can be formed by multiple patterningprocesses. For example, a patterning process can be performed so as to define the STI process opening from the top surface of the silicon substrate to the top surfaces of STI process patterns 214 and 254. Within the defined opening, another patterningprocess can be performed so as to define STI process patterns 244, 246, 248, 250, and 252 within the previously defined opening 214.
The adjacent STI patterns of the array of STI patterns 244, 246, 248, 250, and 252 define a series of openings, each of which has an aspect ratio commensurate with the aspect-ratio(s) desired for the following ART processes. With the series ofopenings between STI patterns 244, 246, 248, 250, and 252, an ART process is performed using a germanium (or other semiconductor materials, such as InGaAs and III-V group materials) so as to form an ART epitaxial crystalline structure. As describedabove with reference to FIG. 1d or FIG. 7, a large ART portion can be formed above the openings and STI patterns by overgrowing the ART structures or by coalescing the ELO portions of the adjacent ART structures. Regardless of the growing process, theART portion (264) can have the top surface that is substantially coplanar to the substrate (e.g. the silicon substrate) or can be above the top surface of the silicon substrate. Accordingly, the semiconductor device (or structure) formed on the ARTstructure (e.g. 264) can be substantially coplanar to another semiconductor device (e.g. the transistor having source 256, gate 258, and drain 260) formed at the top surface of the substrate. The p-i-n structures can then be formed in the large ARTportion. Specifically, the p and n regions can be obtained by doping the intrinsic large ART portion with appropriate dopants. The intrinsic i region can have a large size, such as 1 micron or larger, 1.5 microns or larger, 2 microns or larger, 5microns or larger, 10 microns or larger, or from 5 to 10 microns.
An insulation structure 254 can be formed by a STI process. Transistors having source 256, drain 260, and gate 258 can be formed on the silicon substrate by using a standard silicon process, such as a CMOS process. The p region of the p-i-nstructure of the sensor (214) is grounded. The n region of the p-i-n structure is connected to the gate of transistor 208.
Other than forming a semiconductor device, such as a photodetector, a transistor, a LED or a laser, on a dislocation-free region in an epitaxial crystalline ART structure, the semiconductor device can alternatively be formed on a coalescedregion between adjacent ART structures, an example of which is diagrammatically illustrated in FIG. 15. Referring to FIG. 15, substrate 269, which can be a semiconductor substrate, such as a silicon substrate is provided. Dielectric layer 270 isdeposited on the substrate followed by patterning so as to generate openings in the dielectric layer. An ART process can be performed to form ART epitaxial crystalline structures 280 and 282. By overgrowing the ART structures, the ELO portions of theadjacent ART structures 280 and 282 can be coalesced to form a coalesced region 272. Semiconductor device 276, such as a p-i-n structure or p-n junction, a transistor, or other semiconductor devices can be formed at or in the coalesced region (272). Element 276 can alternatively be a member of semiconductor device 274 that further comprises member 278, which can be formed at the non-coalesced ART region, such as the non-coalesced region of ART structure 280.
Alternative to forming semiconductor devices on coalesced region of adjacent ART structures that are formed in openings defined by dielectric patterns as described above with reference to FIG. 15, a semiconductor device can be formed at or in acoalesced region of adjacent ART structures that are formed in substrates, trenches, STI trenches or openings, an example of which is diagrammatically illustrated in FIG. 16.
Referring to FIG. 16, ART epitaxial crystalline structures 286 and 288 are formed from STI trenches in substrate 269, which can be a semiconductor substrate, such as a silicon substrate, wherein the sidewalls of the trenches are covered bydielectric layers 271 and 273, which may be comprised of an oxide material or other suitable materials. The dielectric layer can be formed in the same way as the dielectric layer 243 in FIG. 12. The ELO portions of ART structures 286 and 288 coalesceresulting in coalesced region 290. Semiconductor device 294, such as a p-i-n or p-n junction, a transistor, or other semiconductor devices can be formed at or in the coalesced region (290). Element 294 can alternatively be a member of semiconductordevice 292 that further comprises member 296, which can be formed at the non-coalesced ART region, such as the non-coalesced region of ART structure 286.
In addition to the methods described above, integration of a non-silicon based semiconductor device into a silicon process can alternatively be achieved by using buffer layers. Graded buffer layers can be of great value for heteroepitaxygrowth, such as heteroepitaxy growth on silicon. As a way of example, graded buffer layers can be used for heteroepitaxy (e.g. in silicon) in relatively larger areas as compared to the narrow trench areas (e.g. STI trench structures as in examples ofART). FIG. 17 diagrammatically illustrates an example. Referring to FIG. 17, in order to form a non-silicon based semiconductor device, such as a germanium (or other semiconductor materials, such as InGaAs and III-V group semiconductor materials)semiconductor device (e.g. a p-n or p-i-n structure) on a silicon substrate, a graded buffer layer comprised of a selected semiconductor material is deposited on the silicon substrate. The graded buffer layer may have a size (e.g. the lateral orvertical dimension) such as 100 nanometers or larger, 500 nanometers or larger, 1 micron or larger, 2 microns or larger, 5 microns or larger, 10 microns or larger, or 100 microns or larger, 1 millimeter or larger, 200 millimeters or larger, 500millimeters or larger, 1 centimeter or larger, or from 10 microns to several centimeters, such as from 10 microns to 500 microns, from 10 microns to 1 millimeter, from 10 microns to 500 millimeters or from 10 microns to 1 centimeter. The graded bufferlayer may have other suitable lateral/vertical dimensions in other examples. In the particular example as illustrated in FIG. 17, dielectric patterns 302 of a selected dielectric material, such as TiN.sub.x are formed on silicon substrate 304 and definean opening. In order to form a germanium p-n diode on the silicon substrate (304), graded buffer layer 298 for germanium is deposited in the opening on the silicon substrate (304). In other examples, the buffer can be comprised of other suitablematerials, such as GaAs, a III-V group semiconductor material (e.g. SiGe, InGaAs, and InP), or a laminate of GaAs/InP/InGaAs. The graded buffer layer can be formed in may ways such as epitaxial techniques and other suitable techniques.
Germanium p-n diode 300 can then be formed on the graded buffer layer (298) for germanium. It is noted that depending upon different semiconductor devices to be formed on the silicon substrate (304), the graded buffer layer can be comprised ofdifferent materials to match the semiconductor device to be formed thereon.
The graded buffer layer can also be used for making semiconductor devices in trenches such as STI trenches formed in a semiconductor substrate, as diagrammatically illustrated in FIG. 18. Referring to FIG. 18, a STI trench is formed in siliconsubstrate 304. The sidewalls of the trench are covered by dielectric layer 299, which can be comprised of an oxide material or other suitable materials. The dielectric layer can be formed in the same way as the dielectric layer 243 in FIG. 12. Agraded buffer layer 298 is disposed in the STI trench. Depending upon the semiconductor device to be formed on the buffer layer and the silicon substrate, the graded buffer layer can be comprised different materials. In the example as illustrated inFIG. 18 wherein a germanium p-n diode is to be formed, the graded buffer layer is correspondingly comprised of a material for matching germanium. Germanium p-n diode 300 is formed on buffer layer 298.
A graded buffer layer may itself comprise a substantially defect (e.g. dislocation defect) free layer; and a device layer for forming a semiconductor device (e.g. a transistor, a photodetector, a solar cell, or other devices) can be formed onsuch defect free layer. The graded buffer layer may have a size (e.g. the lateral or vertical dimension) such as 100 nanometers or larger, 500 nanometers or larger, 1 micron or larger, 2 microns or larger, 5 microns or larger, 10 microns or larger, or100 microns or larger, 1 millimeter or larger, 200 millimeters or larger, 500 millimeters or larger, 1 centimeter or larger, or from 10 microns to several centimeters, such as from 10 microns to 500 microns, from 10 microns to 1 millimeter, from 10microns to 500 millimeters or from 10 microns to 1 centimeter. The graded buffer layer may have other suitable lateral/vertical dimensions in other examples. The graded buffer layer can be formed on a substrate (e.g. a silicon substrate), or in aregion, such as a trench (e.g. a STI trench or other types trenches) that is formed in a substrate or in a dielectric or insulator layer above a substrate.
Referring to FIG. 19a, a cross-sectional view of a portion of an exemplary array of photodetectors is diagrammatically illustrated therein. A heavily doped p+ region is formed in a silicon substrate. The p+ region can then be used as a lowercontact for the photodetectors. A dielectric layer, which is comprised of a low-temperature-oxide (LTO) material in this example, is deposited on the silicon substrate (e.g. on the p+ region in the silicon substrate). The deposited LTO layer ispatterned so as to form openings and expose the silicon substrate, especially, the p+ region in the silicon substrate. ART epitaxial crystalline structures of a selected material, such as germanium or a III-V group semiconductor material are formed inthe openings. The ART structures can be grown with in-situ doping until past the defect regions. The in-situ doped defect-regions can be formed as p-type regions. The ART process can continue until the thickness (e.g. L) is sufficient to allow fordesirable levels of absorption of incident light that the photodetector is designed for detecting, such as visible light, ultraviolet light, and/or infrared light. The top portion of the ART structures can then be doped with an appropriate material soas to form n-type regions.
A top view of the photodetectors in FIG. 19a is diagrammatically illustrated in FIG. 19b. Referring to FIG. 19b, three photodetectors are shown for simplicity and demonstration purposes. As discussed above, the photodetector array may compriseany desired number of photodetectors.
The photodetectors in FIGS. 19a and 19b are configured such that the p, i, and n regions of each photo sensor (e.g. the p-i-n structures) are vertically aligned along the growth direction of the ART structures. In photo detection application,light to be detected is directed toward the top of the sensors. In an alternative example, the light to be detected can be directed along the side of the sensors, as diagrammatically illustrated in FIG. 20a.
Referring to FIG. 20a, a heavily doped p+ region is formed in an intrinsic silicon substrate. An ART epitaxial crystalline material comprised of germanium or a III-V semiconductor material is grown in openings of a dielectric layer, such as thedielectric layer comprised of a LTO material in FIG. 19a. With in-situ implantation, p region can be formed in the ART structures, especially the defect regions of the ART structures. The ART structures continue to form the intrinsic regions. Byin-situ or other doping techniques, n-regions can be formed in the top regions of the ART structures. A metal contact then can be formed on and physically contact to the n-regions.
A top view of the photodetectors is diagrammatically illustrated in FIG. 20b. Referring to FIG. 20b, germanium (or other semiconductor materials, such as a III-V semiconductor material) epitaxial crystalline ART structures are formed on asubstrate (e.g. on the heavily doped p+ region formed in the silicon substrate). The germanium ART structures in this example are deployed such that the lengths (in the top view) of the germanium ART structures are aligned to the <110> directionof the silicon substrate, however the application is not intended to be so limited as other alignments are considered available. The incident light to be detected is directed toward the side of the germanium ART structures.
The electrical connection of the photodetectors as illustrated in FIG. 20a and FIG. 20b can have many suitable configurations, one of which is diagrammatically illustrated in FIG. 21a and FIG. 21b. Referring to FIG. 21a, the exemplaryelectrical connection scheme is illustrated in a top view. A contact to n region and a contact to p region are provided. Each contact comprise at least an elongated contact beam that spans across and electrically connected to substantially all regionsof a particular type (e.g. the n or the p type) of the photodetectors. For example, metal contact 310 for contacting to n regions comprises contact beam 312. Contact beam 312 spans across substantially all ART structures; and is connected to the nregions of the ART structures. This connection is better illustrated in FIG. 21b that diagrammatically illustrates the connection of the metal contacts to the p and n regions of a p-i-n structure in a photodetector.
Metal contact 314 comprises at least one contact beam, such as contact beam 316. The contact beam spans across substantially all photodetectors; and is electrically connected to the p regions of the photodetectors. This connection is betterillustrated in FIG. 21b.
In order to improve the quality and reliability of the electrical connection between the metal contacts to their designated regions, each contact may comprise multiple contact beams as diagrammatically illustrated in FIG. 21a. In the example asillustrated in FIG. 21a, the contact beams of each metal contact are uniformly deployed across the photodetectors within the light absorption range L. Contact beams of different contacts can be alternately disposed. Other configurations are alsoapplicable. For example, multiple (e.g. 2 or more) contact beams of one metal contact can be disposed between two adjacent contact beams of the other contact.
In another exemplary configuration, a contact beam of a metal contact can be connected to a group of photodetectors but not all photodetectors. The photodetectors not electrically connected to one contact beam can be electrically connected toanother contact beam. In other words, a metal contact can have at least two contact beams that are electrically connected to two different groups of photodetectors; whereas the two different groups have at least one different photodetector.
The method as described above can be applied to make semiconductor devices formed in or at ART structures, wherein the defect regions of the ART structures are not electrically isolated from rest of the semiconductor device. As a way ofexample, FIG. 22 diagrammatically illustrates a cross-sectional view of an exemplary photodetector having an n-p-n junction formed in an ART structure.
Referring to FIG. 22, a non-silicon ART material, which is a germanium (or III-V semiconductor material) in this example, is grown within an opening on a silicon substrate. The opening can be formed from patterning of a dielectric layerdeposited on the silicon substrate or can be a STI trench formed in the silicon trench.
The germanium ART structure has a defect region, such as a region comprising dislocation defects, at the bottom. The n and p regions can be formed at the dislocation-defect-free top portion of the germanium ART structure. Specifically, ann-p-n junction can be formed near the top surface of the germanium ART structure. In this example, the bottom defect region in the germanium ART structure is not electrically isolated from the n-p-n junction or the germanium intrinsic region. Light tobe detected is directed from the side of the photodetector.
It is noted that the semiconductor devices, such as the photodectors as discussed above with reference to FIG. 19a through FIG. 22 can be formed in trench structures, such as STI trenches or other types of trenches. The trenches can be formedin a substrate (e.g. with dielectric layers on the sidewalls of the trenches when necessary) or can be formed in a dielectric (or insulator) layer over the substrate.
As noted above, teachings of this disclosure have a wide variety of applications. While not limited to ART technology, teachings of this disclosure have many applications within ART technology. For example, examples of the methods disclosed inthis disclosure may be used to create photodetectors (e.g., IR, UV) for semiconductor devices. Further, examples of the methods disclosed in this disclosure may be used to create sensors using a p-n junction or a p-i-n structure in the sensing region(e.g., IR, UV) for semiconductor devices. A wide variety of devices may incorporate the invention. While not limiting to these devices, the invention may be particularly applicable to mixed signal applications, field effect transistors, quantumtunneling devices, light emitting diodes, laser diodes, resonant tunneling diodes and photovoltaic devices, especially those using ART technology. application Ser. No. 11/857,047 filed Sep. 18, 2007 entitled "Aspect Ratio Trapping for Mixed SignalApplications"; application Ser. No. 11/861,931 filed Sep. 26, 2007 entitled "Tri-Gate Field-Effect Transistors formed by Aspect Ratio Trapping"; application Ser. No. 11/862,850 filed Sep. 27, 2007 entitled "Quantum Tunneling Devices and Circuits withLattice-mismatched Semiconductor Structures"; application Ser. No. 11/875,381 filed Oct. 19, 2007 entitled "Light-Emitter--Based Devices with Lattice-mismatched Semiconductor Structures"; and application Ser. No. 12/100,131 filed Apr. 9, 2007entitled "Photovoltaics on Silicon" are all hereby incorporated by reference as providing examples to which aspects of this invention may be particularly suited.
A silicon CMOS device may be processed prior to embodiments of the invention, therefore, embodiment of devices such as LEDs or photovoltaic devices according to the invention integrated with CMOS process may be fabricated. Further, structuresand/or methods according to disclosed embodiments can be used for integration of non-Si channel or active regions for next generation CMOS and for a wide variety of other applications.
Any reference in this specification to "one embodiment," "an embodiment," "example embodiment," "example," etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at leastone embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described inconnection with any embodiment, it is submitted that it is within the purview of one skilled in the art to affect such feature, structure, or characteristic in connection with other ones of the embodiments. Furthermore, for ease of understanding,certain method procedures may have been delineated as separate procedures; however, these separately delineated procedures should not be construed as necessarily order dependent in their performance. That is, some procedures may be able to be performedin an alternative ordering, simultaneously, etc. In addition, exemplary diagrams illustrate various methods in accordance with embodiments of the present disclosure. Such exemplary method embodiments are described herein using and can be applied tocorresponding apparatus embodiments, however, the method embodiments are not intended to be limited thereby.
Although few embodiments of the present invention have been illustrated and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of theinvention. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoingdescription, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein. As used in this disclosure, the term "preferably" is non-exclusive and means "preferably, but not limited to." Termsin the claims should be given their broadest interpretation consistent with the general inventive concept as set forth in this description. For example, the terms "coupled" and "connect" (and derivations thereof) are used to connote both direct andindirect connections/couplings. As another example, "having" and "including", derivatives thereof and similar transitional terms or phrases are used synonymously with "comprising" (i.e., all are considered "open ended" terms)--only the phrases"consisting of" and "consisting essentially of" should be considered as "close ended". Claims are not intended to be interpreted under 112 sixth paragraph unless the phrase "means for" and an associated function appear in a claim and the claim fails torecite sufficient structure to perform such function.
System and method for shading graphic images using an accessibility factor to simulate tarnish accumulation for realistic rendering
Unsharp masking for image enhancement
Ring-opened polynorbornenes
Heat exchanger, in particular cooling apparatus
Merocyanine dye-donor element used in thermal dye transfer
Passive venting device