Source: http://www.google.com/patents/US20030020102?dq=3798359
Timestamp: 2016-08-27 18:43:45
Document Index: 139598911

Matched Legal Cases: ['art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'arts 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'arts 510', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 18', 'art 11', 'art 11', 'art 18', 'art 18', 'art 18', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11']

Patent US20030020102 - Trench-gate semiconductor devices, and their manufacture - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThe trench-gate (11) of, for example, a cellular power MOSFET comprises doped poly-Si or other semiconductor material (11 a) adjacent to the gate dielectric layer (17) adjacent to the channel-accommodating region (15) of the device. The gate (11) also comprises a sizeable silicide part (11 b) that reduces...http://www.google.com/patents/US20030020102?utm_source=gb-gplus-sharePatent US20030020102 - Trench-gate semiconductor devices, and their manufactureAdvanced Patent SearchPublication numberUS20030020102 A1Publication typeApplicationApplication numberUS 10/197,651Publication dateJan 30, 2003Filing dateJul 17, 2002Priority dateJul 24, 2001Also published asEP1415348A2, US6707100, US6855601, US20040124461, WO2003010827A2, WO2003010827A3Publication number10197651, 197651, US 2003/0020102 A1, US 2003/020102 A1, US 20030020102 A1, US 20030020102A1, US 2003020102 A1, US 2003020102A1, US-A1-20030020102, US-A1-2003020102, US2003/0020102A1, US2003/020102A1, US20030020102 A1, US20030020102A1, US2003020102 A1, US2003020102A1InventorsMark GajdaOriginal AssigneeKoninklijke Philips Electronics N.V.Export CitationBiBTeX, EndNote, RefManPatent Citations (12), Referenced by (21), Classifications (23), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetTrench-gate semiconductor devices, and their manufacture
[0033] It should be noted that all the Figures are diagrammatic, with the relative dimensions and proportions of various parts of these drawings being shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same and/or related reference signs are generally used to refer to the same or corresponding or similar features in modified and different embodiments. [0034] Device Embodiment of FIGS. 1 and 2 [0035] [0035]FIG. 1 illustrates an example of a trench-gate cellular power MOSFET device in accordance with the invention. The device comprises a semiconductor body 10 having a body surface 10 a from which a gate trench 20 extends into the body, through a channel-accommodating region 15 between a source region 13 and into an underlying drain region 14. Thus, in the transistor cell areas of this device, a channel-accommodating region 15 of a second conductivity type (i.e. p-type in this example) separates source and drain regions 13 and 14, respectively, of a first conductivity type (n-type in this example). The drain region 14 is common to all the cells. [0036] The gate 11 is present in the trench 20 and is capacitively coupled to the region 15 by an intermediate dielectric layer 17 at the walls of the trench 20. A voltage signal applied to the gate 11 in the on-state of the device serves in known manner for inducing a conduction channel 12 in the region 15 and for controlling current flow in this conduction channel 12 between regions 13 and 14. [0037] The source region 13 is located adjacent to the surface 10 a, where regions 13 and 15 are contacted by a source electrode 33. The trench-gate 11 is insulated from the overlying electrode 33 by an intermediate insulating overlayer 18. FIG. 1 shows a vertical power device structure. The region 14 is a drain-drift region, formed by an epitaxial layer of high resistivity on a more highly-doped substrate 14 a of the same conductivity type. This substrate 14 a is contacted at the bottom major surface 10 b of the device body 10 by a drain electrode 34. [0038] No plan view of the cellular layout geometry is shown in the drawings, because the present invention may be used for quite different, known cell geometries. Thus, for example the cells may have any polygonal shape, for example a square geometry or a close-packed hexagonal geometry, or an elongate stripe geometry. In each case, the gate trench 20 extends around the boundary of each cell. The cell pitch (centre-to-centre spacing of the cells) is denoted as Yt in FIG. 1. FIG. 1 shows only a few cells, but typically the device comprises many thousands of these parallel cells between the electrodes 33 and 34. The active cellular area of the device may be bounded around the periphery of the device body 10 by various known peripheral termination schemes (also not shown). Such schemes normally include a thick field-oxide layer, formed in the peripheral device area at the surface 10 a before the transistor cell fabrication steps. Furthermore, various known circuits (such as gate-control circuits) may be integrated with the device, between the active cellular area and the peripheral termination scheme. Typically their circuit elements may be fabricated using some of the same masking and processing steps as are used for the transistor cells. [0039] Typically the device body 10 is of monocrystalline silicon, and the gate dielectric layer 17 is of thermally grown silicon dioxide or deposited silicon dioxide. The gate 11 comprises a part 11 a of doped semiconductor material 11′ adjacent to the gate dielectric layer 17 adjacent to the channel-accommodating region 15. This semiconductor material 11′ is typically highly-doped polycrystalline silicon (poly-Si), for example having a phosphorus or arsenic doping concentration (in an n-channel device) with a sheet resistance of about 10 Ω/□ (ohms per square). [0040] In accordance with the present invention, the gate 11 protrudes upwardly from the trench 20 in the form of a silicide upstanding part 11 b. This upstanding (i.e. proud) part 11 b is of a metal silicide material between its top and sidewalls above the level of the body surface 10 a. At least adjacent to the channel-accommodating region 15, the gate dielectric layer 17 is protected from the metal silicide material by the poly-Si part 11 a and by the protrusion z of the silicide part 11 b above the level of the body surface 10 a. The poly-Si (or other semiconductor material) of the gate part 11 a can in-fill even a narrow trench 20 without void formation and with good adhesion to the gate dielectric 17. The poly-Si part 11 a acts as a buffer against contamination of the gate dielectric 17 when the silicide material is deposited or grown. Thus, the inclusion of the silicide as upstanding part 11 b does not prejudice the field-effect control characteristics of the gate 11 and its dielectric 17 at the area where the channel 12 is formed in the region 15. [0041] Typically, the protrusion z of the proud silicide part 11 b may be at least as large as the width w of the trench 20 or larger. The protrusion z may be defined by a window in a mask whose thickness (and hence window depth) is in the range of, for example, about 0.4 μm (micrometers) to 1.5 μm. The width w of the gate trench 20 (which may be etched at this mask layer window) may be in the range of, for example, 0.7 μm to about 0.2 μm, or even 0.1 μm. Thus, the resulting ratio of z/w can be in the range of, for example, about 1 to 5, or more. [0042] Such a protrusion z permits the inclusion of a large volume of the silicide material, thereby reducing significantly the gate resistance. The resistivity of the silicide material is typically an order of magnitude less than the doped poly-Si which is typically 800 Ω.cm (ohm.centimeter). Thus, for example, the upstanding part 11 b may be of titanium silicide having a resistivity in the range of 14 to 20 Ω.cm, or tungsten silicide of 30 to 70 Ω.cm. [0043] The silicide part 11 b may be located wholly above the level of the body surface 10 a, because its upward protrusion z permits the inclusion of a large volume of the silicide material, thereby reducing the gate resistance as desired. However, as indicated in FIG. 2, the silicide part 11 b may extend slightly below the level of the body surface 10 a, and hence into the trench 20. This extension into the trench 20 is small, i.e. less than the depth of the source region 13. [0044] The silicide part 11 b may be deposited, or it may comprise a silicide-forming metal alloyed into the polycrystalline silicon 11′ from the top and sidewalls of the upstanding part 11 b. By way of example, FIG. 2 shows the bottom of the part 11 b with a dimpled shape that is indicative of its formation by alloying metal into its top and sidewalls. [0045] Regardless of whether its suicide part 11 b is formed by deposition or alloying, the device of FIG. 1 is manufactured in accordance with the present invention by a method which includes the following sequence of steps: [0046] (a) providing at surface 10 a of a semiconductor wafer body 100 (that provides the device body 10) a masking pattern 51,52 or 510,520 having therein a window 51 a or 510 a that is used for self-aligning the trench 20 and parts 11 a and 11 b of the gate 11 formed in the subsequent steps (b) to (d); [0047] (b) etching the trench 20 into the body 100 within the window 51 a or 510 a, and forming the gate dielectric layer 17 at the walls of the trench 20, [0048] (c) depositing and then etching back semiconductor gate material 11′ to provide the semiconductor gate part 11 a on the dielectric layer 17 in the trench 20 without protruding above the masking pattern 51,52 or 510,520 at the window 51 a or 510 a, and [0049] (d) then providing at the window 51 a or 510 a a sufficient thickness of metal silicide material at the top of the semiconductor gate material 11 a in the trench 20 as to form the silicide upstanding part 11 b having a top and sidewalls that protrude upward above the level of the body surface 10 a. [0050] During step (d) and thereafter, the gate dielectric layer 17 at least adjacent to the channel-accommodating region 15 is protected from the metal suicide material by the semiconductor part 11 a and by the protrusion z of the suicide part 11 b above the level of the body surface 10 a. [0051] Specific process embodiments will now be described. [0052] Process Embodiment of FIGS. 3 to 5 [0053] This embodiment is one example of a modification in accordance with the present invention of the advantageous self-aligned process of U.S. Pat. No. 6,087,224, involving sidewall extensions (commonly termed “spacers”). [0054] In this embodiment, the window provided in step (a) is a wide window 51 a that is narrowed to a narrower window 52 a by providing spacers 52 (for example of silicon dioxide) at the sidewalls of the wide window 51 a in mask 51 (for example of silicon nitride). The cell pitch and the layout geometry of the device is determined by the layout pattern of the mask 51 that is defined in known manner by photolithographic and etching techniques. Spacers 52 are self-aligned with the sidewalls of the wide window 51 a, as in U.S. Pat. No. 6,087,224. The gate trench 20 is etched in step (b) at the narrower window 52 a. [0055] Typically, the nitride mask 51 may be about 0.5 μm (micrometer) thick on a very thin (about 40 nm thick) oxide 50. In a device having a cellular pitch Yt of about 1 μm or less, the width w of the trench 20 may be about 0.2 μm. In this case, the window 51 a may be 0.5 μm wide, as well as 0.5 μm deep. The oxide spacers 52 may each be from 0.1 μm to 0.2 μm wide, so that the window 52 a is 0.2 μm wide. [0056] [0056]FIG. 3 illustrates the structure resulting from the etching of the trench 20 and the provision of the gate dielectric 17. The gate dielectric layer 17 can be formed by either deposition or oxidation. Channel-accommodating region 15 and source region 13 are not shown in FIG. 3, because of the various options as to how and when the doping for these regions 13 and 15 can be provided, as disclosed in U.S. Pat. No. 6,087,224. Thus, for example, the doping for the region 13 and/or region 15 may be provided either before or after forming the trench-gate 11, and either a shallow or deep more highly-doped contact region 35 may be provided (also in a self-aligned manner) in the channel-accommodating region 15. In all cases, the source region 13 is self-aligned with the trench-gate by means of the spacers 52, in accordance with the teaching in U.S. Pat. No. 6,087,224. [0057] Depending on how the source region 13 is defined, the spacers 52 may be removed after or before filling the insulated trench 20 with the poly-Si gate material 11′. The poly-Si gate part 11 a is defined by etching back the material 11′ to the level shown in FIG. 4, i.e. to about the level of the surface 10 a. A desired conductivity doping of the semiconductor gate part 11 a may be done during the deposition of material 11′ or subsequently before providing the silicide. [0058] Because the oxide spacers 52 may be thinned (i.e. the window 52 a may be widened) slightly by the etching processes used to form the trench 20 and the gate part 11 a, these spacers 52 are preferably replaced before providing the silicide part 11 b. By etching away the oxide spacers 52 the wide window 51 a is re-opened in the nitride mask 51. Further spacers 52 x, for example of silicon dioxide, may then be formed at the sidewalls of this wide window 51 a to form a further window 52 y which defines at least the lateral extent of the gate part 11 b. [0059] A metal silicide material 11 b′ is then deposited and etched back to the level shown in FIG. 5, so as to leave the silicide upstanding part 11 b of the trench-gate 11 in the window 52 y. This further window 52 y is preferably narrower than the width w of the trench 20 so that the silicide part 11 b is spaced from the insulated walls of the trench 20. The deposited silicide material may be a silicide of, for example, tungsten, tantalum, zirconium, titanium or cobalt. [0060] The insulating overlayer 18 is then provided. This may be effected by removing the further spacers 52 x to form a new window between the masking pattern 51 and the upstanding silicide part 11 b, and then depositing insulating material (for example silicon dioxide 18) over the silicide upstanding part 11 b and in the new window. Alternatively, the oxide spacers 52 y could be kept as side parts of the insulating overlayer 18. In this case, further insulating material is deposited (or otherwise provided) on top of the silicide part 11 b in the window 52 y to complete the insulating overlayer 18. [0061] The nitride masking pattern 51 is then removed before providing a highly-doped contact region 35 of the channel-accommodating region 15 and deposting the source electrode 33 to contact this region 35 and the source region 13. Typically, this electrode comprises a thick layer of aluminium on a silicide contact layer 33 a. Its layout is defined (by known photo-lithographic and etching techniques) into separate metallisation areas forming source electrode 33 and also a gate bondpad that is connected to the trench-gate 11. The gate bondpad metallisation and its connection are outside the plane of the FIG. 1 drawing. [0062] The back surface 10 b is then metallised to form the drain electrode 34, after which the wafer body 100 is divided into the individual device bodies 10. [0063] Process Embodiment of FIGS. 3, 6 and 7 [0064] This embodiment is a different example in accordance with the present invention, using the advantageous self-aligned process of U.S. Pat. No. 6,087,224, with spacers 52 to form a narrow trench 20. This embodiment may use the same two-part mask 51 and 52 of different, selectively etchable materials (nitride and oxide), as in FIGS. 3 to 5. However, preferably the oxide spacer 52 is formed on an additional thin nitride layer 52 z. [0065] The two-part mask 51 and 52 is used when etching the trench 20, as in FIG. 3 of the previous embodiment. It is also used when filling the insulated trench 20 with poly-Si gate material. Thus, the poly-Si material 11′ for the gate 11 is deposited in the insulated trench 20 at the narrow window 52 a in this two-part mask 51 and 52 and over this two-part mask 51 and 52. FIG. 6 illustrates that the etch-back of the poly-Si 11′ in this embodiment is stopped at a higher level (compared with FIG. 4) so as to leave an upstanding poly-Si part 11 z integral with the part 11 a. This part 11 z protrudes above the level of the surface 10 a, i.e. it is bounded by the spacers 52. Although shown lower in FIG. 6, the part 11 z may protrude as high as the top of the mask 51 and 52. [0066] The two-part mask 51 and 52 has a further use in this embodiment, as illustrated in FIG. 7. As in the previous embodiment of FIGS. 3 to 5, the oxide spacers 52 are removed before providing the metal silicide material in step (d). However, in this embodiment of FIGS. 3, 6 and 7, the silicide part 11 b is not deposited. Instead, a silicide-forming metal 110 is deposited and is alloyed into the upstanding poly-Si part 11 z. This metal 110 may be, for example, tungsten, tantalum, zirconium, titanium or cobalt. [0067] Thus, as illustrated in FIG. 7, the removal of the oxide spacers 52 creates a space for the silicide-forming metal 110 to contact the sidewalls as well as the top of the upstanding part 11 z. If desired, this space may be increased by a short dip etch of the upstanding poly-Si part 11 z after removal of the spacers 52. The metal 110 is then deposited and alloyed into the poly-Si upstanding part 11 z from its top and from its sidewalls. This alloying can be effected quickly and efficiently using RTA (rapid thermal annealing, using high-intensity light pulses) to heat the metal layer 110 over the device structure. By using RTA, the extent to which the metal is alloyed below the upstanding part 11 z can be precisely controlled, while also avoiding significant heating of the device structure (especially the regions 13, 14 and 15) under the metal layer 110. During the alloying the thin nitride layer 21 z protects the source-region area. With a thickness of, for example, at least 0.5 μm for the mask 51, the protrusion z of the alloyed silicide part 11 b above the level of the surface 10 a can easily be made larger than the narrow trench width w. [0068] Thereafter the un-silicided metal 110 is etched away so as to leave the protruding partially-silicided gate 11 b and 11 a. The device structure is then further processed as in the previous embodiment. [0069] Process Embodiment of FIGS. 8 to 10 [0070] This embodiment is similar in outcome to that of FIGS. 3, 6 and 7, in producing a partially-silicided trench-gate 11 b and 11 a, protruding from the semiconductor body 100. It uses a two-part mask 510 and 520 of different, selectively etchable materials (nitride and oxide). However, it does not use the self-aligned spacer process of U.S. Pat. No. 6,087,224. Thus, in this embodiment, window 510 a at which the trench 20 is etched is present in both parts 510 and 520 of the two-part mask. [0071] [0071]FIG. 8 shows a vertical arrangement of an upper layer 520 of, for example, silicon dioxide on a lower layer 510 of, for example, silicon nitride on a thin oxide layer 50 on the silicon body surface 10 a. A comparison can be made with oxide 52 on nitride 52 z on oxide 50 in FIG. 6. The thickness of the upper layer 520 determines the height of the silicide part 11 b. In order to provide a good volume of silicide material, the upper layer 520 is made thicker, for example at least 5 times thicker, than the lower layer 510. As a result, the protrusion z of the suicide part 11 b above the level of the surface 10 a can easily be made larger than the trench width w. [0072] In step (a) of this embodiment, photolithographic and etching techniques are employed to provide a window 510 a through both layers 520 and 510 where the trench-gate 11 is to be formed in the body 100. This window 510 a may first be used, for example, for providing the source-region dopant in the body 100 a. This dopant can be diffused laterally beyond where the trench 20 is to be etched, so defining the source region 13 in a self-aligned manner with respect to the gate trench. However, the source region 13 can be provided in other known ways at earlier or later stages in the manufacture. [0073] At this window 510 a, the gate trench 20 is etched into the body 100. By deposition or oxidation, the gate dielectric layer 17 is provided at the walls of the trench 20. The resulting structure is shown in FIG. 8. [0074] Poly-Si gate material 11′ is then deposited and etched back so as to remain in the trench 20 and in the window 510 a, as shown in FIG. 9. In this case, the etch-back is a planarising process, i.e. it is stopped when the upstanding poly-Si upper part 11 z is level with the upper surface of the upper layer 520 of the mask. The oxide upper layer 520 is then etched away from the nitride lower layer 510. This exposes the sidewalls of the upstanding poly-Si upper part 11 z that protrudes above the adjacent surface of the nitride layer 510. Thereafter, a silicide-forming metal 110 is deposited over the silicon gate material and nitride layer 510. [0075] Then, as illustrated in FIG. 10, at least the metal 110 is heated (preferably by RTA) to grow the metal silicide into the silicon gate material from the top and side-walls of the upstanding upper part 11 z. The silicide-forming metal 110 may be, for example, tungsten, tantalum, zirconium, titanium or cobalt. The nitride mask layer 510 protects the underlying device structure against alloying with the metal 110. After converting the poly-Si part 11 z into the silicide gate part 11 b in this manner, the remaining un-silicided metal 110 is removed from the device structure. The device structure is then further processed as in the previous embodiment. [0076] Further Embodiments with Other Modifications [0077] It will be evident that many other modifications and variations are possible for devices and manufacturing methods in accordance with the invention. [0078] In the embodiments as described so far, the insulating over-layer 18 is deposited over the top and side-walls of the silicide upstanding part 11 b of the trench-gate 11. However, as indicated by broken outlines in FIG. 2, overlayer 18 may comprise an insulating oxidised surface part 18 b of the silicide material, adjacent to the top and sidewalls of the silicide upstanding part 11 b. [0079] Several metal silicides suitable for forming the upstanding gate part 11 b are also suitable for oxidation to form insulator part 18 b, for example, silicides of refractory metals titanium, zirconium, niobium and tungsten. Another part 18 a may be, for example, deposited silicon dioxide. In some cases, the whole of the over-layer 18 may be an insulating oxidised part 18 b of the metal silicide material of the upstanding gate part 11 b. The nitride layer 520 can be used to mask the underlying silicon body surface 10 a from oxidation during the growth of the insulating oxide 18 b from the silicide part 11 b. [0080] In the process embodiments of FIGS. 3 to 7, the insulating overlayer 18 may even be formed by insulating spacers 52,52 x at the sidewalls of the silicide upstanding part 11 b and by an oxidised silicide layer 18 b′ grown into the top of the silicide upstanding part 11 b in the window 52,52 y. Nitride layer 51 (and 52 z, when present) can be used to mask the underlying body surface 10 a from oxidation during the growth of this insulating oxide 18 b′. [0081] In the embodiments of FIGS. 3 to 7, the source region 13 is formed most conveniently by dopant ion implantation and/or diffusion at windows formed by removing the spacers 52. However, the spacers 52 may be used in other ways to provide self-alignment of the source region 13 with the trench-gate 11. Thus, the source region 13 may be diffused into the body 100 from an arsenic or phosphorus doping in the spacers 52 themselves. In another alternative, the source region 13 may be formed by etching through an n-type layer 13′ provided at the surface 10 a before the mask 51. This layer 13′ can be etched through to the underlying region 15 after providing the insulating overlayer 18 over the protruding gate 11. In these cases and others (for example, FIGS. 8 to 10), the insulating overlayer 18 can be subsequently etched back slightly to increase the exposed area of source region 13 for contacting with the electrode 33. [0082] In the FIG. 10 embodiment, the poly-Si part 11 z can be dip-etched in an isotropic etchant before depositing the metal layer 110, thereby laterally spacing the silicide part 11 b from the walls of the trench. It is also possible to add spacers 52 x to a two-layer mask 510,520 so as to narrow the area of the trench-etch window 510 a where the silicide part 11 b is provided, thereby laterally spacing this silicide from the walls of the trench. [0083] The devices so far described are MOSFETs in which the higher-doped region 14 a is of the same conductivity type (n-type in this example) as the drain drift region 14. However, the higher-doped region 14 a may be of opposite conductivity type (p-type in this example) to provide an IGBT. The electrode 34 is called an anode electrode in the case of an IGBT. [0084] Instead of forming the drain-drift region 14 by an epitaxial layer on a higher-doped substrate 14 a, the higher doped region 14 a of some devices may be formed by dopant diffusion into the back surface 10 b of a high-resistivity substrate that provides the drift region 14. [0085] A vertical discrete device has been illustrated with reference to FIG. 1, having its second main electrode 34 contacting the substrate or other region 14 a at the back surface 10 b of the body 10. However, an integrated device is also possible in accordance with the invention. In this case, the region 14 a may be a doped buried layer between a device substrate and the epitaxial low-doped drain region 14. This buried layer region 14 a may be contacted by an electrode 34 at the front major surface 10 a, via a doped peripheral contact region which extends from the surface 10 a to the depth of the buried layer. [0086] The particular examples described above are n-channel devices, in which regions 13 and 14 are of n-type conductivity, region 15 is of p-type, and an electron inversion channel 12 is induced in the region 15 by the gate 11. In this case, the semiconductor gate part 11 a is n-type. By using opposite conductivity type dopants, a p-channel device can be manufactured by a method in accordance with the invention. In this case, regions 13 and 14 are of p-type conductivity, region 15 is of n-type, the gate part 11 a is p-type, and a hole inversion channel 12 is induced in the region 15 by the gate 11. [0087] Semiconductor materials other than silicon may be used for devices in accordance with the invention, for example silicon carbide. [0088] From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the art and which may be used instead of or in addition to features already described herein. [0089] Although claims have been formulated in this Application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. [0090] The Applicants hereby give notice that new claims may be formulated to any such features and/or combinations of such features during the prosecution of the present Application or of any further Application derived therefrom. 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semiconductor field effect transistor, a method for fabricating same and power conversion systemCN103165669A *Dec 9, 2011Jun 19, 2013上海华虹Nec电子有限公司Trench power metal oxide semiconductor (MOS) device and manufacturing method thereofWO2005029570A1 *Sep 16, 2004Mar 31, 2005Micron Technology, IncDram access transistor and method of formation* Cited by examinerClassifications U.S. Classification257/244, 257/242, 257/E29.156, 257/E29.201, 438/270, 438/589, 257/E21.384International ClassificationH01L29/739, H01L21/331, H01L29/41, H01L29/78, H01L29/423, H01L29/49, H01L21/28, H01L21/336Cooperative ClassificationH01L29/66348, H01L29/4933, H01L29/7813, H01L29/7397European ClassificationH01L29/66M6T2W4T, H01L29/78B2T, H01L29/739C2B2, H01L29/49C2BLegal EventsDateCodeEventDescriptionJul 17, 2002ASAssignmentOwner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., NETHERLANDSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GAJDA, MARK A.;REEL/FRAME:013122/0554Effective date: 20020606Dec 15, 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