Source: http://www.google.com/patents/US5457803?ie=ISO-8859-1
Timestamp: 2014-07-10 19:46:31
Document Index: 259506878

Matched Legal Cases: ['art 10', 'art 12', 'art 12', 'art 12', 'art 14', 'art 14', 'art 10', 'art 10', 'art 16', 'art 16', 'art 18']

Patent US5457803 - Bit-field logic operation unit - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA bit field logic operation unit which performs a logic operation accompanied by a masking operation comprises a logic operation part, a mask pattern generation part, and a bit map operation part. All parts are constituted by dynamic circuit constructions where the processes are performed in a preset...http://www.google.com/patents/US5457803?utm_source=gb-gplus-sharePatent US5457803 - Bit-field logic operation unitAdvanced Patent SearchPublication numberUS5457803 APublication typeGrantApplication numberUS 08/202,876Publication dateOct 10, 1995Filing dateFeb 28, 1994Priority dateJul 13, 1989Fee statusLapsedAlso published asDE69028583D1, EP0408464A2, EP0408464A3, EP0408464B1Publication number08202876, 202876, US 5457803 A, US 5457803A, US-A-5457803, US5457803 A, US5457803AInventorsYoshiyasu Sato, Taizo SatoOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (3), Non-Patent Citations (2), Referenced by (2), Classifications (13), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetBit-field logic operation unitUS 5457803 AAbstract A bit field logic operation unit which performs a logic operation accompanied by a masking operation comprises a logic operation part, a mask pattern generation part, and a bit map operation part. All parts are constituted by dynamic circuit constructions where the processes are performed in a preset period and an active period. The preset periods of the logic operation part and the mask pattern generation part are carried out simultaneously, and the active periods of the logic operation part and the mask pattern generation part and the preset period of the bit map operation part are carried out simultaneously.
We claim: 1. A bit field logic operation unit, comprising:a logic operation means for performing a specified logic operation on source data and destination data to output a logic operation result; a mask pattern generation means, operably coupled to said logic operation means, for generating, simultaneous and in parallel with an operation of said logic operation means, a bit mask pattern from mask information; and a bit map operation means, operably coupled to said logic operation means and said mask pattern generation means, for selecting one of a logic operation result and a destination data in each bit position according to the bit mask pattern to output a masked logic operation result, wherein the logic operation means and the mask pattern generation means are comprised of dynamic circuits having circuit nodes, wherein said logic operation means and said mask pattern generation means simultaneously operate within a preset period, based on a timing signal inputted to said logic operation means and said mask pattern generation means, for simultaneously presetting potentials of said circuit nodes of said logic operation means and said mask pattern generation means, and wherein said logic operation means and said mask pattern generation means operate at an active period for outputting processed data therefrom according to input signals inputted therein. 2. A bit field logic operation unit as claimed in claim 1, wherein the preset period of the logic operation means and the preset period of the mask pattern generation means are carried out simultaneously.
SUMMARY OF THE INVENTION An object of the present invention is to provide a bit field logic operation unit which can perform a logic operation accompanied by a mask operation, within one machine cycle.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a construction of an example of a microprocessor comprising a bit field logic operation unit according to the present invention;
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a construction of an example of monolithic microprocessor, formed in a single semiconductor body comprising a logic operation unit according to the present invention. An instruction prefetching part 10 sends an instruction address to an address translation part 12 and issues an instruction prefetch request to the address translation part 12. The address translation part 12 translates the logical address into a physical address and transfers the translated address to an I/O control part 14. The I/O control part 14 prefetches an instruction and transfers it to the instruction prefetching part 10. The instruction prefetching part 10 transfers the prefetched instruction to an instruction decoding part 16. The instruction decoding part 16 decodes the instruction and transfers decoded information such as an origin address of microinstructions to an operation control part 18.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4400794 *Nov 17, 1981Aug 23, 1983Burroughs CorporationMemory mapping unitUS4945472 *Mar 25, 1988Jul 31, 1990Mitsubihsi Denki Kabushiki KaishaData processor with I/O area detectionEP0171190A2 *Jul 8, 1985Feb 12, 1986Advanced Micro Devices, Inc.Extended-function arithmetic-logic unit* Cited by examinerNon-Patent CitationsReference1 *Digital Processes, vol. 4, No. 2, 1978, St. Saphorin CH, pp. 67 81; D. Gajski et al: High Speed Masking Rotator , p. 69, line 8 15; Figure 2, Table 1.2Digital Processes, vol. 4, No. 2, 1978, St.-Saphorin CH, pp. 67-81; D. Gajski et al: "High-Speed Masking Rotator", p. 69, line 8--15; Figure 2, Table 1.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5657484 *Dec 27, 1994Aug 12, 1997Sgs-Thomson Microelectronics S.R.L.Method for carrying out a boolean operation between any two bits of any two registersWO2013095642A1 *Dec 23, 2011Jun 27, 2013Intel CorporationSystems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate* Cited by examinerClassifications U.S. Classification326/37, 712/E09.019, 712/E09.018International ClassificationG06F7/00, G06F9/308, G06F7/76, G06F9/305Cooperative ClassificationG06F7/764, G06F9/30018, G06F9/30029European ClassificationG06F9/30A1B, G06F9/30A1L, G06F7/76MLegal EventsDateCodeEventDescriptionNov 27, 2007FPExpired due to failure to pay maintenance feeEffective date: 20071010Oct 10, 2007LAPSLapse for failure to pay maintenance feesApr 25, 2007REMIMaintenance fee reminder mailedMar 17, 2003FPAYFee paymentYear of fee payment: 8Mar 29, 1999FPAYFee paymentYear of fee payment: 4Jul 11, 1990ASAssignmentOwner name: FUJITSU LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SATO, YOSHIYASU;SATO, TAIZO;REEL/FRAME:007261/0926Effective date: 19900629RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google