Source: http://www.google.com/patents/US6015983
Timestamp: 2018-01-18 04:54:26
Document Index: 288095788

Matched Legal Cases: ['application No. 07', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08']

Patent US6015983 - Bitline contact structures and DRAM array structures - Google Patents
The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor constructions. The invention includes a method of forming a contact to a node location comprising: a) forming an electrically...http://www.google.com/patents/US6015983?utm_source=gb-gplus-sharePatent US6015983 - Bitline contact structures and DRAM array structures
Publication number US6015983 A
Application number US 09/093,956
Also published as US6140172, US6214727, US6323080
Publication number 09093956, 093956, US 6015983 A, US 6015983A, US-A-6015983, US6015983 A, US6015983A
Patent Citations (31), Non-Patent Citations (24), Referenced by (30), Classifications (21), Legal Events (4)
Bitline contact structures and DRAM array structures
US 6015983 A
a first node location, a second node location and a third node location; the second node location being electrically coupled to the first node location through a first transistor gate and being electrically coupled to the third node location through a second transistor gate;
a first electrically conductive pedestal in electrical connection with the first node location, a second electrically conductive pedestal in electrical connection with the second node location, and a third electrically conductive pedestal in electrical connection with the third node location;
a storage node layer against a lateral surface of the first pedestal, a lateral surface of the second pedestal, and a lateral surface of the third pedestal;
a dielectric layer and a cell layer laterally against the storage node layer and laterally adjacent the first, second and third pedestals; the dielectric layer, cell layer and storage node layer forming a first capacitor electrically connected to the first node location through the first pedestal, and forming a second capacitor electrically connected to the third node location through the third pedestal;
an electrically conductive bitline plug physically contacting the second pedestal, the bitline plug also physically contacting the storage node layer, cell layer and dielectric layer;
a bitline over the first and second capacitors and electrically connected to the second pedestal through the bitline plug;
the second pedestal and first capacitor together forming a first DRAM cell electrically connected to the bitline; and
the second pedestal and second capacitor together forming a second DRAM cell electrically connected to the bitline.
This patent resulted from a divisional application of U.S. patent application Ser. No. 08/798,251 Feb. 11, 1997.
For the above-discussed reasons, defined electrical node locations 25a, 27a, and 29a need not be electrically conductive at the preliminary step of FIG. 3. Node locations 25a, 27a and 29a can be conductive at the step of FIG. 3 if formed by ion implanting of dopant into semiconductive material 12a. On the other hand, node locations 25a, 27a and 29a can be substantially non-conductive at the preliminary step of FIG. 3 in, for example, embodiments in which node locations 25a, 27a and 29a are ultimately doped by out-diffusion of dopant from conductively doped pedestals, such as the pedestals 116, 117 and 118 of FIG. 11.
Referring, to FIG. 7, openings 38a, 39a and 40a are etched through patterned polysilicon layer 36a and into BPSG layer 34a, typically using a timed anisotropic dry etch. Openings 38a, 39a, and 40a preferably comprise a depth "X" of about 10,000 Angstroms. Openings 38a, 39a, and 40a also preferably comprise a minimum cross-sectional width approximately equal to the minimum capable photolithographic dimension obtainable during fabrication, which can be about 0.3 microns. If the minimum capable dimension decreases in the future, smaller dimensions will be utilized in accordance with preferred aspects of the invention.
Referring next to FIG. 13, sacrificial layer 104 (shown in FIG. 12) is removed. Although methods for removal of sacrificial layer 104 will vary depending on the material used for layer 104, methods for removal of various types of layer 104 are readily apparent to persons of ordinary skill in the art. Example conditions for removal of layer 104 when layer 104 consists of the preferred undoped polysilicon include etching with a tetramethyl ammonium hydroxide (TMAH) solution (2.5% in water), at 30° C. Such etch conditions are selective for undoped polysilicon relative to doped polysilicon, with selectivity commonly being about 40:1 when the doped polysilicon comprises greater than 1×1019 ions of dopant/cm3. Thus, the conditions are selective for removing the undoped polysilicon of sacrificial layer 104 relative the doped polysilicon of pedestals 116, 117 and 118. However, although the conditions are selective for removal of undoped polysilicon relative to doped polysilicon, there will be some removal of the doped polysilicon. Thus, in the illustrated preferred embodiment of FIG. 13, the etch rounds upper exposed surfaces of doped polysilicon pedestals 116, 117 and 118.
In preferred embodiments, pedestals 116, 117 and 118 will comprise a circular or curvaceous horizontal cross-sectional shape (as shown in FIG. 16), such that the shown lateral surfaces 128, 129 and 130 are continuous around the pedestals. However, for purposes of the following discussion the shown lateral surfaces on opposing sides of the pedestals may be referred to as opposing lateral surfaces, as they appear to be opposing surfaces in the cross-sectional views of FIGS. 11-21. Use of the term "opposing lateral surfaces" in either this disclosure or the claims that follow is not to be understood as being limited to embodiments of the pedestals having non-curvaceous horizontal cross-sectional shapes.
A second embodiment method of the present invention is described with reference to FIG. 22. In referring to FIG. 22, like numerals from the preceding discussion of the embodiment of FIGS. 2-21 are utilized where appropriate, with differences being indicated by the suffix "b" or with different numerals. FIG. 22 illustrates a wafer 10b at process step subsequent to the process step of FIG. 12, wherein sacrificial layer 104 (shown in FIG. 12) comprises silicon nitride rather than the polysilicon of the embodiment shown in FIGS. 2-21. Pedestals 116b, 117b and 118b comprise conductively doped polysilicon, as did pedestals 116, 117 and 118 in the embodiment shown in FIGS. 2-21.
An etch of silicon nitride is typically more selective relative to doped polysilicon than is an etch of undoped polysilicon. Accordingly, pedestals 116b, 117b and 118b are essentially unetched during removal of silicon nitride layer 104. Thus, the pedestals 116b, 117b and 118b of FIG. 22 lack the rounded upper surfaces of the pedestals 116, 117 and 118 in FIG. 13. Instead, pedestals 116b, 117b and 118b generally comprise a flared upper region with flat upper surfaces 170, 171 and 172, respectively. Conditions for removing the silicon nitride selectively relative to doped polysilicon are known to persons of ordinary skill in the art. An example of such conditions is a wet etch utilizing H3 PO4.
In the shown preferred embodiment of forming pedestals 116b, 117b, and 118b, BPSG layer 34a and etch restriction layer 102 are first etched to below the original planarized upper surface 126 (shown in FIG. 12) to form an upper surface 126b below upper surfaces 170, 171, and 172. Such prior etching insures that there will be adequate clearance around the upper corners of pedestals 116b, 117b and 118b for providing subsequent storage node, capacitor dielectric and cell plate layers during further processing, such as processing analogous to that described above with reference to FIGS. 14-21.
After formation of the pedestals 116b, 117b and 118b, subsequent processing to form a bitline over capacitor DRAM structure can be accomplished with procedures analogous to the processing described above with reference to FIGS. 14-21. Persons of ordinary skill in the art can readily accomplish the processing from such above description. Accordingly, further description, specific to the embodiment of FIG. 22, is not provided herein.
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U.S. Classification 257/296, 257/309, 257/E27.089, 257/E21.658, 257/E21.648, 257/E21.019, 257/E21.013, 257/E27.087, 257/306
International Classification H01L27/108, H01L21/02, H01L21/8242
Cooperative Classification H01L27/10811, H01L28/91, H01L27/10817, H01L27/10888, H01L27/10852, H01L28/84
European Classification H01L27/108M4B2, H01L27/108M4D4, H01L27/108F2M