Source: http://www.google.com/patents/US8028186?dq=oakley+D523,461&ei=qiI4T-CjGqXf0QHz_PSUCA
Timestamp: 2017-11-20 06:08:38
Document Index: 785420911

Matched Legal Cases: ['Application No. 10', 'application No. 07', 'application No. 07', 'application No. 08836238', 'application No. 07', 'application No. 07', 'Application No. 10', 'Application No. 2006800130653']

Patent US8028186 - Skew management in an interconnection system - Google Patents
An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through...http://www.google.com/patents/US8028186?utm_source=gb-gplus-sharePatent US8028186 - Skew management in an interconnection system
Publication number US8028186 B2
Application number US 11/975,269
Also published as CN101611452A, CN101611452B, EP2076903A1, EP2076903B1, EP2498257A1, EP2498257B1, US8090973, US8806262, US20090043933, US20110060857, US20120079163, WO2008051467A1
Publication number 11975269, 975269, US 8028186 B2, US 8028186B2, US-B2-8028186, US8028186 B2, US8028186B2
Inventors Jon C. R. Bennett
Original Assignee Violin Memory, Inc.
Patent Citations (185), Non-Patent Citations (67), Referenced by (4), Classifications (19), Legal Events (8)
Skew management in an interconnection system
US 8028186 B2
FIGS. 2 a, b show how different approaches to signal routing may be used to mitigate the differential propagation time problem. FIG. 2 a shows a situation where the traces are fanned out directly from the CSE, or other device, which may be an AMB, to the connector. FIG. 2 b shows a situation where the signal lines with longer traces are routed on the opposing ends of the board and then another set of signal lines are routed from the middle. In such a circumstance, the propagation distances for some traces are greater than in FIG. 2 a, however the difference in trace length between groups of signals, such as between 0, 1, 2 and 3, or between 4, 5, 6 and 7 can be reduced. While there may still be a difference between in length between groups of traces, the process of delay management and signal de-skew may be simplified by reducing the delay variation from, N different delays for N signals to 2 different approximately equal delays in the example of FIG. 2 b.
FIG. 3 shows an example of transmission from a module controller MC, shown at the left-hand-side of the figure through five modules, for lines 0-4. The data being transmitted from the MC has been designated as A, B, C, D, and E, corresponding to the input data lanes. At each of the downstream modules a table shows the logical name of the input “I”, the delay “D” experienced by the data on that line, the total delay “T” from the MC to the present position along the data transmission path and the logical name of the output data “O”. The rows of the table correspond to the order of the lines; thus the upper row shows line 0 and the bottom row shows line 4. In this example, a delay is associated with each line, and the delay may be different for each line. The delay may be interpreted as a differential delay with respect to a notional line with no excess delay or of the delay from the transmitter on the previous module, or the MC, to the receiver on the receiving module.
FIG. 16 shows an example of an arrangement of components in a CSE. In this example I/O pads may be located on the perimeter of the chip that may correspond to a CSE such as shown in FIG. 12 a where the arrangement is configured to produce a full swap of the signals, while the output traces may be routed similarly to the input traces show in FIG. 12 a rather than as shown in FIG. 12 b.
A light grey line surrounds groups of components which may operate within a local clock domain. Operation in differing clock domains may result from internal signal propagation delays, or even when the same clock domain may be buffered prior to use with each of the areas within a local clock domain. A signal crossing a box edge may be experience a greater delay than a signal entirely within a box.
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U.S. Classification 713/503, 710/38, 327/152, 327/149, 327/153, 327/270, 710/317, 714/700, 710/316, 327/271
Cooperative Classification G11C5/06, G06F13/4243, H03K19/17736, H03K19/17764
European Classification G11C5/06, H03K19/177F, G06F13/42C3S, H03K19/177H4
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BENNETT, JON C. R.;REEL/FRAME:021748/0539
Owner name: VIOLIN MEMORY INC, ILLINOIS
Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:TRIPLEPOINT CAPITAL LLC;REEL/FRAME:033474/0454