Source: https://patents.justia.com/patent/6928015
Timestamp: 2019-10-19 06:40:26
Document Index: 427559518

Matched Legal Cases: ['art 530', 'art 540', 'art 530', 'art 540', 'art 530', 'art 540']

US Patent for Thin film magnetic memory device and semiconductor integrated circuit device including the same as one of circuit blocks Patent (Patent # 6,928,015 issued August 9, 2005) - Justia Patents Search
Justia Patents US Patent for Thin film magnetic memory device and semiconductor integrated circuit device including the same as one of circuit blocks Patent (Patent # 6,928,015)
May 20, 2003 - Renesas Technology Corp.
Shape dummy cells that are designed to have the same dimensions and structures as MTJ memory cells are additionally provided in the peripheral portion of an MTJ memory cell array in which normal MTJ memory cells for storing data are arranged in a matrix. The MTJ memory cells and the shape dummy cells are sequentially arranged so as to have a uniform pitch throughout the entirety. Accordingly, non-uniformity between MTJ memory cells in the center portion and in border portions of the MTJ memory cell array, respectively, after manufacture due to high and low densities of the surrounding memory cells can be eliminated.
In particular, rapid progress in the performance of MRAM devices due to the use of a thin film magnetic material, wherein a magnetic tunnel junction is utilized, as a memory cell has been announced in recent years in, for example, “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell” by Roy Scheuerlein, et al., 2000 IEEE ISSCC Digest of Technical Papers, TA7.2 and in “Nonvolatile RAM based on Magnetic Tunnel Junction Elements” by M. Durlam, et al., 2000 IEEE ISSCC Digest of Technical Papers, TA7.3.
With reference to FIG. 40, tunneling magneto-resistance element TMR has a magnetic layer FL (hereinafter, simply referred to as a fixed magnetic layer FL) having a fixed direction of magnetization and a magnetic layer VL (hereinafter, simply referred to as a free magnetic layer VL) that is magnetized in the direction in accordance with a data write magnetic field generated by a data write current. A tunneling barrier TB formed of an insulating film is provided between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as, or in the opposite direction to, (positive direction or negative direction) fixed magnetic layer FL in accordance with the level of memory data to be written in.
The direction of fixed magnetization of fixed magnetic layer FL is along the easy axis while free magnetic layer VL is magnetized in the (same) direction parallel to fixed magnetic layer FL or in the (opposite) direction anti-parallel to fixed magnetic layer FL along the easy axis in the MTJ memory cell. In the following, the electric resistances of tunneling magneto-resistance element TMR corresponding to the two magnetic directions of free magnetic layer VL, respectively, are denoted as R1 and R0 (here R1>R0) in the present specification. The MTJ memory cell can store data of one bit (“1” and “0”) corresponding to these two magnetic directions of free magnetic layer VL.
A memory cell array (hereinafter also referred to as “MTJ memory cell array”) wherein MTJ memory cells, as shown in FIGS. 39 to 43, are arranged in an integrated manner is arranged in MRAM circuit block 360. In FIG. 44, for example, an MTJ memory cell array is arranged in the hatched region.
Processing of strap layer 410 is, in general, carried out by means of etching in accordance with the design pattern. At the time of etching, however, the film at the time of removal of the resist after etching in a region (hereinafter also referred to as “low density region of the pattern”) having a low density of MTJ memory cells tends to become thin in comparison with that in a region (hereinafter also referred to as “high density region of the pattern”) having a high density of MTJ memory cells. As a result of this, non-uniformity occurs in the thickness of the finished strap SRP. Here, the high density region of the pattern corresponds to the center of the MTJ memory cell array while the low density region of the pattern corresponds to the border portion of the MTJ memory cell array.
Next, with reference to FIG. 45B, magnetic layers for forming tunneling magneto-resistance element TMR are formed in step (b) on strap SRP that has formed. That is to say, magnetic layers 420, 422 and 424 are layered, with buffer layers 425, 427 and 429 intervened therebetween, as layers above strap SRP formed in step (a). Magnetic layer 422 corresponds to fixed magnetic layer FL shown in FIG. 40 and magnetic layer 424 corresponds to free magnetic layer VL shown in FIG. 40. Magnetic layer 420 is formed of antiferromagnetic material which fixes the direction of magnetization of fixed magnetic layer FL. Buffer layers 425, 427 and 429 are formed of, for example, polysilicon.
In addition, the region to be removed and the region that is to remain in resist film 440 are, in general, selected by transcribing a mask pattern embodying the memory cell pattern to the resist film by means of exposure to light. Accordingly, in the “positive-type,” for example, wherein the resist film in the exposed portion remains, the width of the remaining resist film tends to be thicker than in the originally designed pattern due to interference and reflection of light used to expose the resist corresponding to the MTJ memory cells in the periphery in the low density region of the pattern. Contrarily, such reflection and interference of light do not occur in the low density region of the pattern and, therefore, the width of the remaining resist film becomes relatively thin. As a result of this, non-uniformity in the planar memory cell form occurs between the high density region of the pattern and the low density region of the pattern in the above described manner.
An object of the present invention is to make uniform the dimensions, shapes and structures of MTJ memory cells which become access targets in a thin film magnetic memory device and to provide a semiconductor integrated circuit device including the thin film magnetic memory device.
FIG. 1 is a schematic block diagram for describing the entirety of the configuration of an MRAM device according to an embodiment of the present invention;
FIGS. 27-30 are first to fourth conceptual diagrams for describing a wire design rule according to a fifth embodiment, respectively;
In the following, the embodiments of the present invention are described in detail with reference to the drawings. Here, the same symbols indicate the same, or the corresponding, parts in the drawings.
With reference to FIG. 1, an MRAM device according to the embodiment of the present invention is provided with an MTJ memory cell array 10 wherein MTJ memory cells MC for data storage are arranged in sequence in a matrix. Here, in the following, MTJ memory cells arranged within MTJ memory cell array 10 that becomes an access object in accordance with an address signal ADD is specifically referred to as “normal memory cells” in order to be distinguished from the shape dummy cells described below in the present specification.
With reference to FIG. 2, digit lines WDL are provided so as to correspond to the respective rows (hereinafter, also referred to as “memory cell rows”) of the normal memory cells while bit lines BL are arranged so as to correspond to the respective columns (hereinafter, also referred to as “memory cell columns”) of the normal memory cell in MTJ memory cell array 10. Furthermore, though not show in the drawings, word lines WL and source lines SL shown in FIGS. 39 to 43 are arranged so as to correspond to the respective memory cell rows.
In such a configuration, shape dummy cells SDC located in the outer area are arranged in the “low density region of the pattern,” shown in FIGS. 45A to 45E while normal memory cells MC arranged in the peripheral portion (border portion) of the MTJ memory cell array are arranged in the “high density region of the pattern” in FIGS. 45A to 45E.
At least one of circuit blocks 110, making up a plurality, is designed as an MRAM circuit block in each system LSI 100 and an MTJ memory cell array, as shown in FIG. 1, is provided inside of the MRAM circuit block. A structure having, at least, a plurality of layers with the same structure as the plurality of MTJ memory cells, is arranged in the MTJ memory cell array. Accordingly, shape dummy cells provided to ensure the uniformity of the MTJ memory cells can be arranged in a region 150a between circuit blocks, in a region 150b within another circuit block, in a region 150c bordering another system LSI along a dicing line, or the like.
In particular, region 150c along a dicing line is a vacant region wherein no circuit elements, or the like, for forming a circuit block are arranged and, therefore, increase in chip area can be avoided in the case where shape dummy cells are arranged in this region. In addition, in the case where shape dummy cells are arranged within a circuit block other than the MRAM circuit block, dispersion into areas of high and low density of MTJ memory cells can be reduced over the entirety of the chip.
Straps SRP arranged as signal lines in the column direction are provided so as to correspond to row blocks RB(1) to RBM), respectively, in each memory cell column. Furthermore, an access transistor ATR is arranged so as to correspond to each strap SRP. That is to say, M access transistors ATR and M straps SRP, respectively, are arranged in each memory cell column so as to correspond to the row groups.
At the time of data read, one word line from among word lines WL(1) to WL(M) corresponding to the selected memory cell is selectively activated in accordance with the result of row selection. The strap (hereinafter also referred to as “selected strap”) coupled to the selected memory cell is coupled to fixed voltage Vss due to the activation of word line WL. As a result of this, L tunneling magneto-resistance elements TMR, including the selected memory cell, connected to the above selected strap (hereinafter also referred to as “selected memory cell group”) make connections between corresponding bit line BL and fixed voltage Vss.
Accordingly, at the time of data read, data read current Is flows through bit line BL in the selected column in accordance with the electric resistance of the entirety of the selected memory cell group. Therefore, current passing through one selected memory cell (electric resistance) included in this selected memory cell group is sensed according to data read in the MRAM device provided with the MTJ memory cells shown in FIG. 6, which is carried out in a so-called “self-reference read” manner wherein no reference cells are provided based on data read current Is passing through the above selected memory cell group.
With reference to FIG. 10, a normal memory cell MC located at an outermost portion of memory block 11 is shown on the W side in the cross section along line V-W. As described above, normal memory cell MC has a tunneling magneto-resistance element TMR and an access transistor ATR.
With reference to FIG. 16, the magnetic field application apparatus according to the modification of the third embodiment is provided with a solenoid coil 520a having a gap portion greater than the diameter of wafers 500. Solenoid coil 520a is formed so as to have a thickness that allows a predetermined magnetic field to be simultaneously applied to a plurality of wafers 500 in a stack.
In such a configuration, at least one of a magnetic field application apparatus position control part 530 and a wafer position control part 540 is provided in the same manner as in FIG. 14 and, thereby, either wafers 500 or solenoid coil 520a is moved so that a predetermined magnetic field 525 can be simultaneously applied to a plurality of wafers. Accordingly, the throughput of the magnetization process for MRAM devices is increased and productivity is increased.
Alternately, as shown in FIG. 17, a configuration can be provided wherein predetermined magnetic field 525 is applied by another type of solenoid coil 520b that is thinner than the above. That is to say, in the configuration according to FIG. 17, solenoid coil 520b is formed to have a thickness that allows the application of a predetermined magnetic field to a portion of the plurality of wafers 500 in the stack.
In the configuration according to FIG. 17, solenoid coil 520b is moveable in two axis directions by means of magnetic field application apparatus position control part 530 while wafers 500 are moveable in the two axis directions in the same manner by means of wafer position control part 540. In addition, only one of magnetic field application apparatus position control part 530 and wafer position control part 540 is arranged in the configuration in the same manner as in FIGS. 15 and 16.
With reference to FIG. 18, a system LSI 100, shown as the first example of the configuration of a semiconductor integrated circuit device according to the fourth embodiment, is provided with a plurality of MRAM circuit blocks 110a to 110f. MRAM circuit blocks 110a to 110f, respectively, include MTJ memory cell arrays 10a to 10f, wherein the MTJ memory cells are arranged in the matrix, formed in the same manner as is MTJ memory cell array 10, shown in FIG. 1.
Peripheral circuit portions are arranged in each of MTJ memory cell arrays 10a to 10f in the same manner as described in FIG. 1 and FIG. 18 shows a layout of row decoder 13 and column decoder 14 in a representative manner. The configuration according to the fourth embodiment does not necessarily require the provision of dummy structural cells for each of MTJ memory cell arrays 10a to 10f.
As described above, a normal memory cell MC, which is an MTJ memory cell, is provided with a tunneling magneto-resistance element TMR that is magnetized in either the positive direction or the negative direction along easy axis (EA) in accordance with the level of write data. In addition, a bit line BL for providing a data write magnetic field in the easy axis direction and a write digit line WDL for generating a magnetic field in the hard axis direction are provided to each normal memory cell MC. That is to say, a data write current is selectively made to flow through bit line BL in a direction differing according to the level of the write data at the time of data write while a data write current is selectively made to flow through write digit line WDL in a fixed direction, regardless of the level of the write data.
In system LSI 100, row decoder 13 and column decoder 14 for selecting write digit line WDL and bit line BL, respectively, are stably arranged in each of MRAM circuit blocks 110a to 110f. In the example of FIG. 18, row decoder 13 is arranged on the left side of each of the corresponding MTJ memory cell arrays while column decoder 14 is arranged on the upper side of each of the corresponding MTJ memory cell arrays.
In such a configuration, the directions of currents flowing through write digit lines WDL and bit lines BL at the time of data write as well as the directions of write digit lines WDL and bit lines BL become the same in each of the MRAM circuit blocks 110a to 110f. As a result of this, the layout pattern of memory cells is determined so that the easy magnetization axes of the MTJ memory cells (tunneling magneto-resistance elements TMR) are oriented in the same direction in each of the plurality of MTJ memory cell arrays 10a to 10f arranged in the same system LSI 100 (that is to say, in the same chip).
MTJ memory cells having a line symmetric and point symmetric form (also referred to as a “fully symmetric form”) such as a rectangle or an ellipse, are arranged in each of MTJ memory cell arrays 10a to 10f in system LSI 101.
There is no limitation in the rotational direction of the magnetic poles of tunneling magneto-resistance element TMR (free magnetic layer VL) at the time of data write in an MTJ memory cell in a fully symmetric form and, therefore, there is no specific limitation to the combinations of directions of data write currents that flow through bit line BL and write digit line WDL, respectively. Accordingly, as shown in FIG. 19, the layout pattern of memory cells is determined in each of MTJ memory cell arrays 10a to 10f in the same chip so that the easy magnetization axes of MTJ memory cells (tunneling magneto-resistance elements TMR) are oriented in the same direction by placing write digit lines WDL and bit lines BL in the same direction.
FIG. 20A shows an MTJ memory cell in the form of a rectangle having a protrusion in order to achieve the stabilization of magnetization characteristics. In such an MTJ memory cell, the easy axis is in the direction parallel to the long sides of the rectangle. In some cases in a system LSI wherein is arranged an MTJ memory cell with a form that is neither point symmetric nor line symmetric (also referred to as “asymmetric form”), such as the above, the rotational direction of the magnetic poles is restricted in tunneling magneto-resistance element TMR at the time of data write. Even in such a case, MTJ memory cells can be arranged in each MTJ memory cell array so that the easy magnetization axes of the MTJ memory cells (tunneling magneto-resistance elements TMR) are oriented in the same direction by implementing the layout shown in FIG. 18. Though not shown, boomerang-shaped or L-shaped MTJ memory cells can be used as MTJ memory cells in asymmetric forms.
FIGS. 20B and 20C examples of MTJ memory cells having forms that are point symmetric but are not line symmetric (also referred to as “point symmetric form”). In these MTJ memory cells, the easy magnetization axes are in the direction parallel to the long sides of the figures. In the MTJ memory cells in point symmetric forms, the rotational direction of the magnetic poles in tunneling magneto-resistance elements TMR can be limited at the time of data write. That is to say, there is a possibility that it may become necessary to set the direction of the data write current through write digit line WDL relative to the direction of the data write current in bit line BL at each level of the write data.
System LSI 102 has a configuration that takes into consideration the limitation of direction of the data write current in the above described MTJ memory cell in a point symmetric form. That is to say, the directions of row decoder 13 and column decoder 14 relative to a plurality of MTJ memory cell arrays 10a to 10f arranged in the same chip is limited to either of two types (directions in which MTJ memory cell arrays 10a and 10f, respectively, are arranged in FIG. 19), which are point symmetric with each other.
Here, as for the form of the MTJ memory cells, forms that are line symmetric but not point symmetric (also referred to as “line symmetric forms”), such as the T-shape shown in FIG. 20D or U-shaped, not shown, may be used. An outline that is the same as any of those in FIGS. 18, 19 and 21 may be used for MTJ memory cells in a line symmetric form so that an arrangement wherein the easy magnetization axes of the MTJ memory cells (tunneling magneto-resistance elements TMR) are oriented in the same direction can be used in accordance with the restrictions in the rotational directions of the magnetic poles of tunneling magneto-resistance elements TMR.
FIG. 23 is a conceptual diagram for describing magnetic noise sources that affect memory arrays. Wires arranged so as to correspond to other internal circuits 620a and 620b exist in a system LSI, or the like, on which an MRAM device is mounted. Wires 610a and 610b, from among the above described wires, provided in the same direction as bit lines BL or write digit lines WDL in the upper, or lower, region of a memory cell array 10 are representative magnetic noise sources. Wires 610a and 610b generally indicate a power supply line (wire), a signal line (wire), a data line (wire), and the like, through which constant, or transient, currents flow.
Wire 610 in the vicinity of the MTJ memory cell array represents, for example, wires 610a and 610b, shown in FIG. 23, and represents the wires other than the wires for generating data write magnetic fields, that is to say, other than bit lines BL and write digit lines WDL.
Such a constant, or transient, current Ins (hereinafter also referred to as “noise current”) passing through wire 610 generates magnetic noise H(ns). That is to say, magnetic noise H(ns) caused by noise current Ins affects each normal memory cell MC. As a result of this, the risk of erroneous data write is enhanced, in particular, in non-selected memory cells in the proximity of wire 610 belonging to the same memory cell column or to the same memory cell row as selected memory cell MC#.
Wire 610# is arranged using metal wire layer ML0 or ML1, which is a layer below write digit line WDL, in the same manner as above. The distance between wire 610# and tunneling magneto-resistance element TMR is denoted as r2 and magnetic noise H(ns)# affects tunneling magneto-resistance element TMR due to noise current Ins# flowing through wire 610#.
(Ins/r1)+(Ins#/r2)<Hnr (2)
In FIG. 28, an angle θ formed between the line connecting wire 610 and tunneling magneto-resistance element TMR, and the direction of the normal of tunneling magneto-resistance element TMR becomes a parameter indicating relative angular shift between the two in the application of a data write magnetic field. For example, bit line BL for the application of a sufficient data write magnetic field to tunneling magneto-resistance element TMR is arranged directly beneath (i.e., θ=0°) tunneling magneto-resistance element TMR.
When angle θ is a parameter, a component of magnetic noise H(ns), from wire 610, that causes erroneous data write, that is to say, component H(ns)w that works in the easy axis direction is provided as H(ns)w=H(ns) cosθ. Accordingly, wire 610 arranged in a region above or below the memory cell array is arranged so as to, at least, avoid the region directly above or directly below an MTJ memory cell, that is to say, is arranged so that the above described angle θ≠0° and, thereby, magnetic noise that affects the MTJ memory cell can be reduced.
Σ{H(ns)w}=Σ{(Ins/rn)·cos θ}<Hnr (3)
In such a configuration, the effects of magnetic noise from power supply wire 725, which becomes a noise source, on the MTJ memory cells can be reduced.
At this time, electrical paths 761 to 769, respectively, formed between pads 741 to 749 and lead frames 751 to 759 in order to couple system LSI 700 and die 730 are arranged so as to avoid regions above and below MRAM circuit block 710. On the other hand, electrical paths, such as electrical paths 761 to 763, 767 and 768 provided in the above described manner, may pass through regions above and below circuit blocks 701 and 702 other than MRAM circuit block 710. Electrical paths 761 to 769 are, in general, formed of metal wires and, therefore, the positions of these metal wires are taken into consideration so as to implement the above described positioning of electrical paths.
1. A thin film magnetic memory device comprising: wherein
a memory cell array in which a plurality of magnetic memory cells is sequentially arranged,
each of said magnetic memory cells including a magnetic memory element having a plurality of magnetic layers at least one of which is magnetized in the direction in accordance with storage data;
a plurality of shape dummy cells sequentially arranged with said plurality of magnetic memory cells in the outside of said memory cell array,
each of said shape dummy cells including a dummy magnetic memory element designed to have the same structure and the same dimensions as said magnetic memory element; and
said memory cell array is divided into a plurality of memory blocks, and
said plurality of shape dummy cells is sequentially arranged with said plurality of magnetic memory cells within each of said memory blocks around the periphery of each of said plurality of memory blocks.
each of said shape dummy cells including a dummy magnetic memory element designed to have the same structure and the same dimensions as said magnetic memory element; and further comprising:
a circuit element formed in the same planer region as of said dummy magnetic memory element and in a layer differing from that of said dummy magnetic memory element, in at least one of said plurality of shape dummy cells.
a memory cell array in which a plurality of magnetic memory cells is sequentially arranged, each of said magnetic memory cells including a magnetic memory element having a plurality of magnetic layers at least one of which is magnetized in the direction in accordance with storage data; a plurality of shape dummy cells sequentially arranged with said plurality of magnetic memory cells in the outside of said memory cell array, each of said shave dummy cells including a dummy magnetic memory element designed to have the same structure and the same dimensions as said magnetic memory element; and
wherein each of said memory cells further includes an access element formed in a layer differing from that of said magnetic memory element for controlling a current passing through said magnetic memory element at the time of data read, said thin film magnetic memory device further comprises a plurality of dummy shape elements sequentially arranged with said access element outside of said memory cell array, each of said shape dummy elements has the same structure and the same dimensions as of said access element, at least a part of said plurality of shape dummy cells is formed in the same planar region as of one of said plurality of dummy shape elements, and said dummy magnetic memory element and each of said dummy shape elements, respectively, are formed in different layers in said same planar region.
the number of said dummy magnetic memory elements arranged in the same direction and the number of said dummy shape elements arranged in the same direction are different from each other outside of said memory cell array.
6104633 August 15, 2000 Abraham et al.
6317376 November 13, 2001 Tran et al.
6324093 November 27, 2001 Perner et al.
6795335 September 21, 2004 Hidaka
“A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell”, Scheuerlein et al., IEEE ISSCC Digest of Technical Papers, TA7.2, Feb. 2000, pp. 94-95, 128-129, 409-410.
“Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, Durlam et al., IEEE ISSCC Digest of Technical Papers, TA 7.3, Feb. 2000,pp. 96-97, 130-131, 410-411.
Patent number: 6928015
Patent Publication Number: 20030235070
Inventor: Tsukasa Ooishi (Hyogo)
Application Number: 10/441,016
Current U.S. Class: 365/210; Magnetoresistive (365/158); Magnetic Thin Film (365/171); Multiple Magnetic Storage Layers (365/173); Plural Blocks Or Banks (365/230.03)