Source: http://www.google.com.au/patents/US9418011
Timestamp: 2018-01-24 09:56:27
Document Index: 10874073

Matched Legal Cases: ['Application No. 201180041024', 'Application No. 201180041024', 'application No. 11798876', 'Application No. 201180041024', 'application No. 100121833', 'application No. 100121833']

Patent US9418011 - Region based technique for accurately predicting memory accesses - Google Patents
In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load...http://www.google.com.au/patents/US9418011?utm_source=gb-gplus-sharePatent US9418011 - Region based technique for accurately predicting memory accesses
Publication number US9418011 B2
Application number US 12/821,935
Also published as CN103038748A, CN103038748B, CN106294212A, EP2585916A2, EP2585916A4, US20110320762, WO2011163407A2, WO2011163407A3
Publication number 12821935, 821935, US 9418011 B2, US 9418011B2, US-B2-9418011, US9418011 B2, US9418011B2
Inventors Livio B. Soares, Naveen Cherukuri, Akhilesh Kumar, Mani Azimi
Patent Citations (42), Non-Patent Citations (8), Classifications (9), Legal Events (1)
US 9418011 B2
US5941981 3 Nov 1997 24 Aug 1999 Advanced Micro Devices, Inc. System for using a data history table to select among multiple data prefetch algorithms
US5960454 * 19 Dec 1996 28 Sep 1999 International Business Machines Corporation Avoiding cache collisions between frequently accessed, pinned routines or data structures
US6047363 * 14 Oct 1997 4 Apr 2000 Advanced Micro Devices, Inc. Prefetching data using profile of cache misses from earlier code executions
US6317810 * 25 Jun 1997 13 Nov 2001 Sun Microsystems, Inc. Microprocessor having a prefetch cache
US6535966 17 May 2000 18 Mar 2003 Sun Microsystems, Inc. System and method for using a page tracking buffer to reduce main memory latency in a computer system
US6678795 * 15 Aug 2000 13 Jan 2004 International Business Machines Corporation Method and apparatus for memory prefetching based on intra-page usage history
US6804769 18 Feb 2000 12 Oct 2004 Hewlett-Packard Development Company, L.P. Unified buffer for tracking disparate long-latency operations in a microprocessor
US7480769 * 11 Aug 2006 20 Jan 2009 Mips Technologies, Inc. Microprocessor with improved data stream prefetching
US7496730 * 15 Apr 2005 24 Feb 2009 Microsoft Corporation System and method for reducing the number of translation buffer invalidates an operating system needs to issue
US7975108 * 25 Mar 2004 5 Jul 2011 Brian Holscher Request tracking data prefetcher apparatus
US8332587 * 28 May 2009 11 Dec 2012 International Business Machines Corporation Cache line use history based done bit modification to I-cache replacement scheme
US20070198779 * 15 Dec 2006 23 Aug 2007 Qufei Wang System and method for cache management
US20080235458 29 Apr 2008 25 Sep 2008 Red Hat, Inc. Method for tracking of non-resident pages
US20080282032 * 18 Jul 2006 13 Nov 2008 Xiaowei Shen Adaptive mechanisms and methods for supplying volatile data copies in multiprocessor systems
US20090006800 * 26 Jun 2007 1 Jan 2009 International Business Machines Corporation Configurable memory system and method for providing atomic counting operations in a memory device
US20090182947 20 Mar 2009 16 Jul 2009 Red Hat, Inc. Method of tuning a cache
US20100235579 * 18 Sep 2006 16 Sep 2010 Stuart David Biles Cache Management Within A Data Processing Apparatus
US20100262750 * 13 Apr 2009 14 Oct 2010 Advanced Micro Devices, Inc. Region prefetcher and methods thereof
US20100306473 * 28 May 2009 2 Dec 2010 International Business Machines Corporation Cache line use history based done bit modification to d-cache replacement scheme
US20100306474 * 28 May 2009 2 Dec 2010 International Business Machines Corporation Cache line use history based done bit modification to i-cache replacement scheme
US20120198176 * 6 Mar 2012 2 Aug 2012 Via Technologies, Inc. Prefetching of next physically sequential cache line after cache line that includes loaded page table entry
US20150309936 * 2 Jul 2015 29 Oct 2015 Via Technologies, Inc. Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry
JP2005302034A Title not available
JP2007122667A Title not available
JP2008102745A Title not available
JPH04259048A Title not available
WO2001088717A2 24 Apr 2001 22 Nov 2001 Sun Microsystems, Inc. System and method for using a page tracking buffer to reduce main memory latency in a computer system
WO2011163407A2 22 Jun 2011 29 Dec 2011 Intel Corporation Region based technique for accurately predicting memory accesses
1 China State Intellectual Property Office, Third Office Action mailed Mar. 21, 2016 in Chinese Patent Application No. 201180041024.6.
2 Chinese Patent Office, Chinese Office Action mailed Apr. 30, 2015 in Chinese Patent Application No. 201180041024.6.
3 European Patent Office, Office Action mailed Mar. 4, 2014 in European application No. 11798876.6.
4 International Search Report and Written Opinion for PCT Patent Application No. PCT/US2011/041511, mailed on Feb. 17, 2012, 9 pages.
5 Japanese Patent Office, "Decision of Rejection," in Patent Application 2013-516745, Translation by Ryuka Law Firm, Aug. 12, 2014.
6 State Intellectual Property Office of the People's Republic of China, Second Chinese Office Action mailed Nov. 25, 2015 Application No. 201180041024.6.
7 Taiwanese Patent Office, Office Action dated Nov. 5, 2014 in Taiwan application No. 100121833.
8 Taiwanese Patent Office, Office Action mailed Apr. 8, 2014 in Taiwan application No. 100121833.
International Classification G06F12/10, G06F12/00, G06F13/00, G06F13/28, G06F12/08
Cooperative Classification G06F12/1027, G06F12/0862, G06F2212/6024, G06F12/10