Source: https://patents.google.com/patent/KR950002956B1/en
Timestamp: 2020-07-06 03:28:09+00:00
Document Index: 25610482

Matched Legal Cases: ['art 11', 'art) 11', 'art 11', 'art 11', 'art 11', 'art 11']

KR950002956B1 - Semiconductor memory device and fabricating method thereof - Google Patents
KR950002956B1
KR950002956B1 KR91001238A KR910001238A KR950002956B1 KR 950002956 B1 KR950002956 B1 KR 950002956B1 KR 91001238 A KR91001238 A KR 91001238A KR 910001238 A KR910001238 A KR 910001238A KR 950002956 B1 KR950002956 B1 KR 950002956B1
KR91001238A
KR920000136A (en
히데아끼 아리마
나쓰오 아시가
가또시 하찌스
미쓰비시뎅끼 가부시끼가이샤
1991-01-25 Application filed by 시기 모리야, 미쓰비시뎅끼 가부시끼가이샤 filed Critical 시기 모리야
1992-01-10 Publication of KR920000136A publication Critical patent/KR920000136A/en
1995-03-28 Publication of KR950002956B1 publication Critical patent/KR950002956B1/en
239000004065 semiconductor Substances 0.000 title claims description 79
239000010410 layers Substances 0.000 claims description 373
239000003990 capacitor Substances 0.000 claims description 172
238000002955 isolation Methods 0.000 claims description 51
238000004519 manufacturing process Methods 0.000 description 30
XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound 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[Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 20
229910052710 silicon Inorganic materials 0.000 description 20
Semiconductor Memory and Manufacturing Method
1 is a plan view of a memory cell array of a DRAM according to a first embodiment of the present invention.
2 is a cross-sectional structural view of the memory cell from the direction along the cutting line II-II in FIG.
3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h, 3i, 3j, 3k, 3l and 3m Fig. 2 is a cross sectional view of the production process of the memory cell of DRAM shown in Fig. 2;
4 is a cross-sectional structure diagram of a memory cell of a DRAM according to a second embodiment of the present invention.
5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H are cross-sectional views of the main manufacturing process of the memory cell shown in FIG.
6 is a cross-sectional structure diagram of a memory cell of a DRAM showing a third embodiment of the present invention.
7A, 7B, 7C, 7D, 7E, and 7F are sectional views of the main manufacturing process of the memory cell shown in FIG.
8 is a plan view of a memory cell array according to a fourth embodiment of the present invention.
9 is a cross-sectional structural view from the direction along cut line VII-VII in FIG. 8;
10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i, 10j, 10k, 10l, 10m 10 and 10n are sectional views of the manufacturing process of the memory cell shown in FIG.
11 is a block diagram of a conventional DRAM.
12 is an equivalent circuit diagram of a memory cell of a conventional DRAM.
Fig. 13 is a cross-sectional structure diagram of a memory cell provided with a stacked type capacitor of a DRAM showing a conventional example.
14 is a cross-sectional structure diagram of a memory cell of a DRAM showing another conventional embodiment.
15A, 15B, 15C, 15D, 15E, and 15F are cross-sectional views of a manufacturing process of a memory cell of a DRAM shown in FIG.
1: silicon substrate 3: transfer gate transistor
4a, 4b, 4c, 4d: word line (gate electrode) 5: gate insulating film
6: source / drain area 10: capacitor
11: lower pole 11a: base of lower electrode
11b: Partial wall of lower electrode 12 Dielectric layer
13: upper electrode 15: bit line
16 bit line contact portion 17 capacitor contact portion
21 nitride film 25 polycrystalline silicon film
31: The capacitor isolation layer is shown.
In the drawings, the same reference numerals indicate the same or equivalent parts.
The present invention relates to a semiconductor memory device, and more particularly, to a structure capable of improving the capacitor capacity associated with miniaturization of a dynamic random access memory (DRAM) and a manufacturing method thereof.
In recent years, the demand for semiconductor memory devices has been rapidly expanding due to the remarkable spread of information devices such as computers.
Again, it is required to have a large storage capacity functionally and to be capable of high speed operation. In connection with this, the development of the technology regarding the high integration of a semiconductor memory device, high-speed response, or high reliability is progressing.
Among semiconductor memory devices, there is a DRAM capable of random input and output of memory information. In general, a DRAM is composed of a memory cell array, which is a storage area for storing a large amount of storage information, and peripheral circuits required for input and output to and from the outside.
11 is a block diagram showing the structure of a general DRAM. In this figure, the DRAM 50 includes a memory cell array 51 for accumulating data signals of stored information, and a low-end column for receiving address signals for selecting memory cells constituting a unit memory circuit from the outside. An address buffer 52, a row decoder 53 and a column decoder 54 for designating a memory cell by decoding the address signal, and a sense refresh amplifier for amplifying and reading out the signals accumulated in the designated memory cell 55, a data inbuffer 56 for data input / output, a data outbuffer 57, and a clock generator 58 for generating a clock signal.
A plurality of memory cell arrays 51 occupying a large area on a semiconductor chip are formed in a plurality of arrays in a matrix of memory cells for storing unit memory information.
FIG. 12 shows an equivalent circuit diagram of four bits of the memory cells constituting the memory cell array 51. As shown in FIG. The illustrated memory cell represents a so-called one transistor one capacitor type emery cell composed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto. Since this type of memory cell is poor in structure, it is easy to improve the integration degree of the memory cell array, and is widely used for large-capacity DRAM. In addition, DRAM memory cells can be divided into some types depending on the structure of capacitors.
FIG. 13 is a cross-sectional structure diagram of a memory cell having a typical stacked capacitor, and is shown in, for example, Japanese Patent Laid-Open No. 60-2784.
Referring to FIG. 13, a memory cell includes one transfer gate transistor and one stacked type capacitor (hereinafter, referred to as a stacked type capacitor).
The transfer gate transistor includes a pair of source / drain regions 6 and 6 formed on the surface of the silicon substrate 1 and a gate electrode 4 formed on the silicon substrate surface with an insulating layer interposed therebetween. .
The stacked capacitor extends from the top of the gate electrode 4 to the top of the field separation film 2 and has a lower electrode connected to one of the source and drain regions 6 and 6. A toray node 11, a dielectric layer 12 formed on the surface of the lower electrode 11, and an upper electrode (cell plate) 13 formed on the surface again.
Again, a bit line 15 is formed on top of the capacitor with the interlayer insulating layer 20 interposed therebetween, and the bit line 15 has the bit source contact portion 16 therebetween and the other source of the transfer gate transistor. It is connected to the drain area 6. The feature of this stacked capacitor is that the capacitors are secured by increasing the counter area between the electrodes of the capacitor by extending the main portion of the capacitor up to the gate electrode or the field separator.
In general, the capacitance of the capacitor is proportional to the opposing area between the electrodes and inversely proportional to the thickness of the dielectric layer.
Therefore, it is desirable to increase the counter area between capacitor electrodes in terms of increasing the capacitor capacity.
On the other hand, with the high integration of DRAMs, memory cell sizes have been deflated on a large scale.
Therefore, the capacitor formation area also tends to reduce the planar footprint.
However, the amount of charges that can be accumulated in a 1-bit memory cell cannot be reduced in view of the stable dynamics and reliability of the DRAM as the storage device.
In order to satisfy such conflicting constraints, the structure of the capacitor has been proposed in various forms to reduce the planar footprint of the capacitor and to increase the counter area between the electrodes.
Figure 14 shows "Symposium on VLSI Tech. p65 (1989) 'is a cross-sectional structure diagram of a memory cell having a so-called cylindrical stacked capacitor.
Referring to FIG. 14, the transfer gate transistor has a gate electrode (word line) 4c covered with an insulating layer 22 around it. The source and drain regions are not shown.
Again, the word line 4d is covered by the insulating layer 22 around it, and on the surface of the shield electrode 40 formed with the shield gate insulating film 41 therebetween on the surface of the silicon substrate 1. Formed.
The lower electrode 11 of the capacitor is vertically upward from the surface of the base portion 11a formed on the surface of the insulating layer 22 covering the surfaces of the gate line electrode 4c and the word line 4d and the base portion 11a. It consists of the cylindrical part 11b extended cylindrically.
Again, a dielectric layer and an upper electrode are sequentially stacked on the surface of the lower electrode 11 (not shown).
The cylindrical stacked capacitor can use not only the base portion 11a but also the cylindrical portion 11b as a telephone accumulation region, and in particular, the cylindrical portion 11b allows the capacitor capacity to be increased without increasing the planar footprint of the capacitor. It becomes possible to increase. In addition, the nitride film 42 remains partially on the surface of the insulating layer 22.
Next, a manufacturing process of the memory cell shown in FIG. 14 will be described with reference to FIGS. 15A to 15F.
First, referring to FIG. 15A, the shield gate insulating film 41, the shield electrode 40, the word lines 4c and 4d, the insulating layer 22 and the nitride film 42 are formed on the surface of the silicon substrate 1 in a predetermined shape. Is formed.
Next, referring to FIG. 15B, a polycrystalline silicon layer is deposited on the surface of the silicon substrate 1 and patterned into a predetermined shape. As a result, the base portion 11a of the lower electrode 11 of the capacitor is formed.
Again, referring to FIG. 15C, a thick insulating layer 43 is formed on the entire surface. Then, an opening 44 reaching the base portion 11a of the lower electrode is formed in the insulating layer 43 by etching. Again, a polycrystalline silicon layer 11b is deposited on the inner surface of the opening 44 and the surface of the insulating layer 43.
Again, referring to FIG. 15D, the polycrystalline silicon layer 110b is selectively etched away by anisotropic etching. As a result, the cylindrical portion 11b is formed vertically upward from the surface of the base portion 11a of the lower electrode 11 of the capacitor, and the lower electrode 11 is completed.
Again, as shown in FIG. 15E, the dielectric layer 12 and the upper electrode 13 are sequentially formed on the surface of the lower electrode 11.
Again, as shown in FIG. 15F, after covering the entire surface of the silicon substrate 1 with the interlayer insulating layer 20, a contact hole is formed at a predetermined position, and the bit line contact portion 16 is formed inside the contact hole. ). Thereafter, a bit line to be connected with the bit line contact portion 16 is formed on the surface of the interlayer insulating layer 20 (not shown).
However, if the capacity of the DRAM is excessively increased again, in the cylindrical stacked capacitor, the reduction in the plane occupancy area of the base portion 11a of the lower electrode 11 is inevitable. This base portion 11a has many flat surface areas which decrease in proportion to the rate of decrease of the planar footprint area. In the cylindrical portion 11b, both the inner surface and the outer surface of the cylindrical portion 11b are used as the capacitive portion, and the proportion of the capacitor portion in the full capacity region of the capacitor increases. Therefore, it is important to use the cylindrical portion as much as possible in the reduced capacitor plane occupancy area.
In addition, the conventional cylindrical stacked capacitor is formed in a manufacturing process different from the base portion 11a and the cylindrical portion 11b of the lower electrode 11. Therefore, a plurality of film forming processes or mask patterning processes are required and the manufacturing process is complicated.
Again, a problem arises in that the insulation reliability of the dielectric layer formed on the surface of the lower electrode 11 is degraded at the connection portion between the base portion 11a and the cylindrical portion 11b of the lower electrode 11. In addition, the conventional semiconductor memory device requires a plurality of photolithography steps in order to manufacture a cylindrical stacked capacitor, and requires a high-precision mast joint. Therefore, the manufacturing process is complicated and includes the manufacturing problem that a lot of siege water becomes.
Accordingly, the present invention has been made to solve the above problems, and an object thereof is to provide a structure of a semiconductor memory device having a capacitor capable of high integration and having a predetermined capacitor capacity and a manufacturing method thereof.
A semiconductor memory device according to claim 1, comprising a semiconductor substrate of a second conductive type having a main surface and having a gate bit line having an impurity region of a first conductivity type on the main surface, and a semiconductor substrate of a semiconductor substrate. And an insulating layer having an opening reaching the impurity region.
Again, the first portion formed on the surface of the impurity depot and on the surface of the insulating layer, and the upwardly extending inclination with respect to the outermost surface of the first portion and also with respect to the main surface of the semiconductor substrate. A first electrode layer having a portion of 2 is provided.
A dielectric layer is formed on the surface of the first electrode layer, and a second electrode layer is formed again on the surface of the dielectric layer.
The semiconductor memory device according to claim 2 includes a first portion in which a first electrode layer of a capacitor is formed on a surface of an impurity region formed on a semiconductor substrate and on a surface of an insulating layer, and an outermost portion of the first portion. It also has a second portion extending perpendicularly upward with respect to the main surface of the semiconductor substrate.
The film thickness in the direction parallel to the main surface of the semiconductor substrate of the second part of the first electrode layer is thinner than the film thickness in the direction perpendicular to the main surface of the semiconductor substrate of the first part.
The semiconductor memory device according to claim 3 includes a memory cell array in which a plurality of memory cells for storing unit memory information are arranged. A semiconductor substrate having a main surface, a plurality of word lines extending in parallel to each other on the main surface of the semiconductor substrate, a plurality of bit lines extending in a direction perpendicular to the plurality of word lines on the spherical surface of the semiconductor substrate, And a memory cell arranged near an intersection with the word line. Each of the memory cells includes one transfer gate transistor and one capacitor.
Again, the transfer gate transistor has a gate insulating layer formed on the main surface of the semiconductor substrate between the pair of impurity regions and the pair of impurity regions formed in the direction along the bit lines on the main surface of the semiconductor substrate positioned between adjacent bit lines. And a gate electrode formed of a portion of a word line formed therebetween.
Again, the capacitor includes a first portion formed on one surface of the pair of impurity regions of the transfer gate transistor, and a first impurity region connected to the first portion, and above the adjacent word line and a pair of impurity regions of the transfer gate transistor. A second portion extending in an upper section of the bit line connected to the other side of the second line and a third portion extending vertically upwardly with respect to the main surface of the semiconductor substrate according to the outermost circumference of the second portion. A first electrode layer, a dielectric layer covering the surface of the first electrode layer, and a second electrode layer covering the surface of the dielectric layer are provided.
The semiconductor memory device according to claim 4 has a first and a second stacked capacitor, which are mounted on a surface of an insulating layer covering a main surface of a semiconductor substrate and formed separately from each other. Includes the following steps.
First, an insulating layer is formed on the main surface of the semiconductor substrate, and a capacitor isolation layer having almost vertical sides is formed on the isolation region of the first and second capacitors on the surface of the insulating layer. A contact hole reaching the main surface of the semiconductor substrate is formed at a predetermined position of the insulating layer, and a first conductive layer is formed on the inner surface of the contact hole, on the surface of the insulating layer, and on the surface of the capacitor isolation layer.
Next, an etch back layer having a different etching ratio from the first conductive layer is formed on the surface of the first conductive layer, and the etching back layer is etched to expose the surface of the first conductive layer on which the capacitor isolation layer is located on the upper surface. . Again, the first conductive layer exposed from the etch back layer is partially etched away, and the first conductive layer is separated into the first capacitor portion and the second capacitor portion.
Thereafter, the capacitor isolation layer and the etch back layer are removed, and a dielectric layer and a second electrode layer are formed on the surface of the first conductive layer.
Again, the semiconductor memory device according to claim 5 has the first and second stacked capacitors mounted on the surface of the insulating layer covering the main surface of the semiconductor substrate and formed separately from each other. The manufacturing method includes the following steps.
After the insulating layer is formed on the main surface of the semiconductor substrate, an etching stop layer is formed on the surface of the insulating layer.
Then, a capacitor isolation layer having vertical sides is formed on the isolation region of the first and second capacitors on the surface of the etch stop layer.
In addition, a contact hole reaching the main surface of the semiconductor substrate is formed at predetermined positions of the insulating layer and the etching stop layer, and the first conductive layer is formed on the inner surface of the contact hole, on the surface of the etching stop layer, and on the surface of the capacitor isolation layer. To form.
Again, an etch back layer having a different etching ratio from the first conductive layer is formed on the surface of the first conductive layer, and the etch back layer is etched to expose the surface of the first conductive layer located on the upper surface of the capacitor isolation layer.
Again, the first conductive layer exposed from the etch back layer is partially etched away, and the first conductive layer is separated into a first capacitor portion and a second capacitor portion. The capacitor isolation layer and etch back layer are then removed. Again, a dielectric layer is formed on the surface of the first conductive layer.
The semiconductor memory device according to claim 6 has the first and second stacked capacitors mounted on the surface of the insulating layer covering the main substrate main surface and formed separately from each other. It includes the following process.
A first formation is formed on the main surface of the semiconductor substrate with open holes reaching the main surface of the semiconductor substrate at predetermined positions. A first conductive layer is formed on the surface of the first insulating layer and inside the open hole.
Again, a second insulating layer having a predetermined film thickness is formed on the surface of the first conductive layer. Then, the second insulating layer is patterned, and the second insulating layer has a substantially vertical sidewall surface only in the isolation region consisting of the second insulating layer having a substantially vertical sidewall surface only in the isolation regions of the first and second capacitors. Form a capacitor isolation layer.
Again, a second conductive layer is formed on the surface of the first conductive layer and on the top surface and side surfaces of the capacitor isolation layer. Thereafter, the second conductive layer formed on the upper surface of the capacitor isolation layer is selectively removed.
After removing the capacitor isolation layer and a part of the first conductive layer attached to the lower portion of the capacitor isolation layer, a dielectric layer is formed on the surface of the second conductive layer. Again, a third conductive layer is formed on the surface of the dielectric layer.
In the manufacturing method of the semiconductor memory device according to claim 7, the step of forming the capacitor isolation layer in the manufacturing method according to claim 5 is performed by the following steps.
First, a first insulating layer is formed on the main surface of the semiconductor substrate. And a second insulating layer having a side surface inclined with respect to the main surface of the semiconductor substrate by forming a second insulating layer on the surface of the first insulating layer and etching the second insulating layer using a mask of a predetermined shape. A capacitor layer is formed.
In the method of manufacturing a semiconductor memory device according to claim 8, the step of forming a capacitor isolation layer in the manufacturing method according to claim 6 is constituted by the following steps.
First, a first insulating layer is formed on the main surface of the semiconductor substrate. Again, an etching stop layer is formed on the surface of the first insulating layer. Then, by forming a second insulating layer on the surface of the etching stop layer and etching the second insulating layer using a mask of a predetermined shape, the main surface of the semiconductor substrate on the separation region of the first and second capacitors. A capacitor isolation layer formed of a second insulating layer having an inclined side with respect to the interlayer is formed.
In the invention according to claim 1, the second portion of the first electrode of the capacitor is formed to extend upwardly inclined from the outermost circumference of the first portion formed relatively relatively brilliantly. By forming this second part along the outermost part of the first part and inclined upward, the area of the inner and outer surfaces of the second part is enlarged, and the effective capacitance area of the second part is increased. This makes it possible to secure or increase the capacity of the capacitor even though the plane occupancy area of the capacitor is reduced.
In the method according to claim 2, the film thickness of the second portion of the first electrode layer of the capacitor is thin. As a result, the area of the inner circumferential wall surface of the vertical portion of the second portion is increased to increase the capacitor capacity. In addition, the film thickness of the first portion of the first electrode is formed to be thick, thereby reducing the resistance as the electrode layer and preventing the deterioration of the responsiveness of the capacitor.
In the invention according to claim 3, by arranging the lower electrodes of the capacitors in a row above the bit lines, the bit line contacts between the capacitors of adjacent memory cells are prevented from being disposed. As a result, it is possible to reduce the isolation region between capacitors adjacent to each other, to reduce the device structure, or to increase the planar footprint of the capacitor.
In the invention according to claim 4 and 7, the capacitor isolation layer is formed in a region corresponding to the separation region between the capacitors adjacent to each other, and the lower electrode of the capacitor can be integrally formed by using the side wall of the capacitor separation layer. I'm letting you.
Again, in the inventions of claims 5 and 8, by forming an etch stop layer between the insulating layer and the capacitor separation layer, the end point detection accuracy at the time of etch back used in the formation of the capacitor separation layer is improved. have.
In the invention according to claim 6, a patterned capacitor isolation layer is formed at a predetermined position on the surface of the first conductive layer, and the second portion of the first electrode layer of the capacitor is positioned using the surface of the capacitor isolation layer. And formed.
Again, after removing the capacitor isolation layer, only the region of the first conductive layer covered by the capacitor isolation layer is selectively removed, so that the first electrode layers of adjacent capacitors are separated from each other. Therefore, the first electrode layer is formed by itself by one lithography process, and the process is simplified.
Below, one embodiment of this invention is described in detail using drawing.
FIG. 1 is a planar structural diagram of a memory cell array of a DRAM according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional structural view from the direction along the cutting line II-II in FIG.
First, referring to FIG. 1, mainly on the surface of the silicon substrate 1, a plurality of word lines 4a, 4b, 4c, 4d extending in parallel in the row direction and a plurality of bit lines extending in parallel in the column direction (15, 15, 15) and a plurality of memory cells MC arranged near the intersection of the word line and the bit line are formed.
Referring to FIGS. 1 and 2, the memory cell is composed of one transfer gate transistor 3 and one capacitor 10.
The transfer gate transistor 3 is formed on the surface of the silicon substrate 1 positioned between the pair of source / drain regions 6 and 6 and the source / drain regions 6 and 6 formed on the surface of the silicon substrate 1. Gate electrodes (word lines) 4b and 4c formed with the gate insulating film 5 interposed therebetween. The periphery of the gate electrodes 4b and 4c is covered by the insulating layer 22.
Again, a thick interlayer insulating layer 20 is formed on the surface of the silicon substrate 1 on which the transfer gate transistor 3 is formed. In the predetermined region of the interlayer insulating layer 20, a contact hole 14 reaching one source / drain region 6 of the transfer gate transistor 3 is formed.
The capacitor 10 has a stacked structure of a lower electrode (storage node) 11, a dielectric layer 12, and an upper electrode (cell plate) 13.
The lower electrode 11 has a base portion (first portion) 11a formed on the inner surface of the contact hole 14 and on the surface of the nitride film 21 formed on the surface of the interlayer insulating layer 20; It consists of two parts of the input part (2nd part) 11b extended vertically upward along the outermost periphery of this base part 11a. The base portion 11a and the input portion 11b are integrally formed by a polycrystalline silicon layer into which impurities are introduced.
The dielectric layer 12 is formed on the surface of the lower electrode 11. In particular, the dielectric layer 12 is formed to cover both sides of the inner side and the outer side of the input portion 11b of the lower electrode 11. Accordingly, the input portion 11b of the lower electrode 11 constitutes the capacitive portion on both the inner and outer sides.
As the dielectric layer 12, an oxide film, a nitride film or a composite film of an oxide film and a nitride film or a metal oxide film is used.
The upper electrode 13 is formed on the surface of the dielectric layer 12. The upper electrode 13 is formed to cover almost the entire surface of the memory cell array. As the upper electrode 13, a metal layer such as polycrystalline silicon or a high melting point metal into which impurities are introduced is used.
The upper surface of the upper electrode 13 is covered by the insulating layer 23. On the surface of the insulating layer 23, wiring layers 24 and 24 of a predetermined shape are formed.
The bit line 15 is connected to the source / drain region 6 on one side of the transfer gate transistor 3. The bit line 15 is formed at a position lower than the main portion of the input portion 11b or the base portion 11a of the lower electrode 11 of the capacitor 10.
Referring again to FIG. 1, the line width of the bit line 15 is partially formed in the bit line contact portion 16.
In addition, one side of the source / drain region 6 of the transfer gate transistor 3 extends to the lower region of the bit line 15 in the region in contact with the bit line 15. The contact with the bit line is formed by the extended source / drain region 6 and the contact portion 16 of the bit line 15 whose line width is enlarged.
As described above, since the contact is formed by mutually extending the contact portion between the source and drain regions 6 and the bit line 15, the pair of impurity regions 6 and 6 of the bit line 15 and the transfer gate transistor. Can be configured parallel to each other.
In addition, referring to FIG. 2, the isolation region 18 between the capacitors 10 and 10 adjacent to each other can be configured as narrow as possible. In other words, it is possible to enlarge the planar region of the base portion 11a of the lower electrode 11 of the capacitor 10. Accordingly, the planar occupancy area of the base portion 11a of the lower electrode is enlarged, and the circumferential length of the input portion 11b located at its outermost circumference is also enlarged, thereby increasing the capacitor capacity of the entire capacitor 10.
In addition, as shown in FIG. 1, the planar shape of the capacitor 10 is shown as a rectangular shape, but this is only a typical surface, and in practice, the rectangular angle is formed in a round ellipse or a cylindrical shape.
Next, a manufacturing process of the cross-sectional structure of the memory cell shown in FIG. 2 will be described using FIGS. 3A to 3M.
First, as shown in FIG. 3A, a field oxide film 2 and a channel stop region (not shown) are formed in a predetermined region on the main surface of the silicon substrate 1.
Again, the thermal oxide film 5, the polycrystalline silicon layer 4 by the CVD method, and the oxide film 22a are sequentially formed on the surface of the silicon substrate 1.
Next, as shown in FIG. 3B, word lines 4a, 4b, 4c, and 4d are formed using photolithography and etching methods. The patterned oxide film 22a remains on the surfaces of the word lines 4a to 4d.
Again, as shown in FIG. 3C, the oxide film 22b is deposited on the entire surface of the silicon substrate 1 by the CVD method.
Again, as shown in FIG. 3D, by performing anisotropic etching on the oxide film 22b, the insulating layer 22 of the oxide film is formed around the word lines 4a to 4d. The impurity ions 30 are ion-implanted on the surface of the silicon substrate 1 by using the word lines 4a to 45d covered by the insulating layer 22 as a mask, and the source and drain regions 6 and 6 of the transfer gate transistor. ).
Again, as shown in FIG. 3E, a conductive layer, for example, a doped polysilicon layer or a metal layer, a metal silicide layer, or the like is formed on the surface of the silicon substrate 1 and patterned into a predetermined shape. As a result, the bit line 15 and the bit line contact 16 are formed.
Next, as shown in FIG. 3F, an interlayer insulating film 20 is formed on the silicon substrate 1 surface. Again, a nitride film 21 having a film thickness of 100 GPa or more is formed on the interlayer insulating film 20, for example.
Again, an oxide film 31a having a film thickness of 5000 kPa or more is formed on the surface of the nitride film 21, for example. The film thickness of the oxide film 31a defines the height of the mouth wall portion 11b of the lower electrode 11 of the capacitor 10 in a later step.
Therefore, this film thickness varies with the set value of the capacitance of the capacitor of the DRAM as a product. In addition, the combination of the nitride film 21 and the oxide film 31a is selected by the combination of materials so that the selectivity with respect to both etching may differ.
Again, as shown in FIG. 3G, the oxide film 31a is patterned using an etching method to form a capacitor isolation layer 31 for separating capacitors adjacent to each other. In this etching step, the nitride film 21 has a different etching rate with respect to the oxide film 31.
Therefore, the etching rate decreases as the etching proceeds to the surface of the nitride film 21. Taking this opportunity, the etching of the oxide film 31a is terminated. In this etching, the region remaining as the capacitor isolation layer 31 is finer than the region to be etched away. In the etching technique, there are technical limitations in microprocessing with regard to fine hole drilling or grooving, but when such a residual portion is made fine, such technical limitations are small.
Therefore, it is possible to finely process the width of the capacitor isolation layer 31, and finally to make the separation width between the capacitors fine.
Again, as shown in FIG. 3H, contact holes 14 and 14 that reach the soot / drain regions 6 are formed using photolithography and etching methods.
Again, as shown in FIG. 3i, the polycrystalline silicon layer 110 is deposited on the inner surface of the contact hole 14, on the surface of the nitride film 21 and on the surface of the capacitor isolation layer 31 using the CVD method. Deposit Then, a resist (ach back layer) 32 is thickly coated on the surface of the polycrystalline silicon layer 110.
Again, as shown in FIG. 3j, the resist 32 is etched back to expose a portion of the polycrystalline silicon layer 110. As shown in FIG.
Again, as shown in FIG. 3K, the exposed polycrystalline silicon 110 surface is selectively removed using anisotropic etching or the like. As a result, the polycrystalline silicon layer 110 is separated on the surface of the capacitor isolation layer 31, and the lower electrode 11 of the capacitor is formed, respectively.
Again, as indicated by 3 l and the like, the resistor 32 is etched away, and the capacitor isolation layer 31 is removed again with hydrofluoric acid or the like. Then, a dielectric layer 12 such as a nitride film is formed on the surface of the lower electrode 11. As shown in 3m, the upper electrode 13 such as a polycrystalline silicon layer is formed on the surface of the dielectric layer 12 by CVD. Thereafter, the insulating layer 23, the wiring layer 24, and the like are formed to complete the manufacturing process of the memory cell of the DRAM.
Next, a memory cell of a DRAM according to a second embodiment of the present invention will be described. FIG. 4 is a cross-sectional structure diagram of the memory cell corresponding to FIG. 2 showing the first embodiment.
Referring to FIG. 4, the feature of the second embodiment is that the polycrystalline silicon layer 25 is used as the etch stop layer formed on the interlayer insulating layer 20 and the surface. This polycrystalline silicon layer 25 is used to prevent overetching in the manufacturing process described later. However, after completion, the polycrystalline silicon layer 25 is integrated with the lower electrode 11 of the capacitor and constitutes the lower electrode 11.
Next, a manufacturing process of the memory cell of the DRAM shown in FIG. 4 will be described.
In addition, since the manufacturing process of the memory cell according to the second embodiment overlaps with the manufacturing process of the memory cell of the DRAM according to the first embodiment shown in FIGS. 3A to 3M, the characteristic manufacturing process is characterized here. Will be described only, and the description thereof will be omitted by referring to the first embodiment.
First, as shown in FIG. 5A (corresponding to FIG. 3F), the polycrystalline silicon layer 25 is deposited on the surface of the interlayer insulating layer 20 by the CVD method. Again, an oxide film 31a is formed on the surface.
This polycrystalline silicon layer 25 has a large etching selectivity with respect to the oxide film 31a formed on the upper layer. Next, as shown in FIG. 5B (corresponding to FIG. 3G), the oxide film 31a is selectively etched to form the capacitor isolation layer 31. At this time, the polycrystalline silicon layer 25 is used to detect the etching end point of the oxide film 31a, and prevents the lower interlayer insulating layer 20 from overetching.
Next, as shown in FIG. 5C (corresponding to FIG. 3H), the source / drain regions 6 and 6 in the polycrystalline silicon layer 25 and the interlayer insulating layer 20 using the photolithography method and the etch method. To form a contact hole (14).
In addition, as shown in FIG. 5D (corresponding to FIG. 3I), the polycrystalline silicon layer 110 is formed on the inner surface of the contact hole 14, on the surface of the polycrystalline silicon layer 25, and on the surface of the capacitor isolation layer 31. ) Is deposited. The resist 32 is thickly coated on the surface of the polycrystalline silicon layer 10.
Again, as shown in FIG. 5E (corresponding to FIG. 3J), the resist 32 is etched back to expose the surface of the polycrystalline silicon layer 110.
Again, as shown in FIG. 5F (corresponding to FIG. 3K), the exposed surface of the polycrystalline silicon layer 110 is selectively removed. As a result, the polycrystalline silicon layer 110 on the surface of the capacitor nitride film 31 is removed, and the lower electrodes 11 and 11 of the capacitors which are independent of each other are formed.
Again, as shown in FIG. 5G, the capacitor nitride film 31 and the polycrystalline silicon layer 25 located below the capacitor isolation layer 31 are selectively removed. As a result, the lower electrodes 11 and 11 of the capacitor adjacent to each other are separated from each other.
Then, as shown in FIG. 5h. The dielectric layer 12 is formed on the surface of the patterned lower electrode 11. Incidentally, in the first and second embodiments, the case where the resist 32 is used as the etch back layer is shown. However, the present invention is not limited thereto, and the same applies to using a CVD silicon oxide film or the like. It can be effective.
Again, a memory cell of a DRAM in the third embodiment of the present invention will be described.
6 is a cross-sectional structural view of the memory cell corresponding to FIG. 2 showing the first embodiment.
Referring to Fig. 6, the characteristic point of the third embodiment is that the mouth wall portion 11b of the lower electrode 11 of the capacitor 10 extends in the oblique direction with respect to the substrate main surface. Specifically, the input 11b is formed in the hollow inclined elliptical column shape, the hollow inclined cylinder column shape, or the hollow inclined angle column shape. The inner surface and the outer surface of the inclined mouth wall portion 11b are also used as capacitive portions.
For example, if the height in the direction perpendicular to the substrate main surface of the mouth wall portion 11b of the lower electrode 11 is made constant, the mouth wall portion 11b of the capacitor of the third embodiment shows the inclined surface to perform the first embodiment. Compared with the example wall part 11b, the surface area is increasing. In addition, the inclination direction and angle of the wall part part 11b can be arbitrarily controlled in the manufacturing process demonstrated below.
Next, a manufacturing process of the memory cell of the DRAM shown in FIG. 6 will be described.
In addition, since the manufacturing process of this third embodiment is overlapped in many parts with the manufacturing process of the memory cells of the DRAM according to the first embodiment shown in FIGS. 3A to 3M, only the characteristic manufacturing process will be described here. In addition, the other description is referred to 1st Embodiment, and description is abbreviate | omitted.
First, as shown in FIG. 7A (corresponding to FIG. 3F), the polycrystalline silicon layer 25 is deposited on the surface of the interlayer insulating layer 20 by the CVD method. Again, an oxide film 31a is formed on the surface. This polycrystalline silicon layer 25 has a large etching selectivity with respect to the oxide film 31a formed on the upper layer.
Next, as shown in FIG. 7B (corresponding to FIG. 3G), the oxide film 31a is selectively etched to form a capacitor isolation layer 31 inclined to the substrate surface. As the etching method, for example, plasma etching is used. The semiconductor substrate is supported by inclining the main surface of the substrate with respect to the ion flight direction in the plasma. When the oxide film 31a is etched in this state, the capacitor nitride film 31 can be formed by tilting the substrate main surface at an arbitrary direction and angle. The inclination direction and angle are set so that the inclined surface of the mouth wall portion 11b of the lower electrode is maximized.
Again, as shown in FIG. 7C (corresponding to FIG. 3H), the source / drain regions 6 and 6 in the polycrystalline silicon layer 25 and the interlayer insulating layer 20 using the photolithography method and the etching method. The contact hole 14 reaching reaches is formed.
In addition, as shown in FIG. 7D (corresponding to 3i), polycrystalline silicon on the inner surface of the resist 14, on the surface of the polycrystalline silicon layer 25, and on the surface of the capacitor nitride film 31 having the inclined side surface. Layer 110 is deposited. Then, 32 is thickly applied on the surface of the polycrystalline silicon layer 110 again.
Again, as shown in FIG. 7E (corresponding to FIG. 3J), the resist 32 is etched back to expose the surface of the polycrystalline silicon layer 110.
Again, as shown in FIG. 7F (corresponding to FIG. 3K), the surface of the exposed polycrystalline silicon layer 110 is selectively removed. As a result, the polycrystalline silicon layer 110 on the surface of the capacitor nitride film 31 is removed, and the lower electrodes 11 and 11 of the capacitors which are independent of each other are formed. Thereafter, the memory cells shown in FIG. 6 are completed through processes equivalent to FIGS. 3L and 3M. Also in the above embodiment, a nitride film may be formed instead of the polycrystalline silicon layer 25 on the surface of the interlayer insulating layer 20.
Next, this invention is demonstrated about 4th Example.
FIG. 8 is a planar structure diagram of the memory cell array in the fourth embodiment, and FIG. 9 is a cross-sectional structure diagram from the direction along the cutting line VII-VII in FIG.
Referring to the drawings, the structural feature of the memory cell according to the third embodiment is that the film thickness is different from the base portion 11a and the mouth wall portion 11b of the lower electrode 11 of the capacitor 10. Is the point. The film thickness t 1 of the base part 11a of the lower electrode 11 is formed relatively thick so that the resistance as an electrode layer can be reduced mainly. As an example, it is formed with a film thickness of about 2000 kPa. The film thickness t 2 of the mouth wall portion 11b of the lower electrode 11 of the capacitor 3 is determined in consideration of two factors.
The first point is to make the inner circumferential diameter L of the mouth wall portion 11b of the lower electrode 11 as large as possible and as thin as possible to increase the area of the inner circumferential wall surface.
The second point is that the wall portion 11b becomes high in resistance due to the depletion layer widened to the mouth wall portion 11b during operation, and the film thickness is secured so as not to function as a capacitance region. . For example, it is formed to about 500 kHz. In addition, the mouth wall portion 11b has one surface with the outermost peripheral portion of the base portion 11a as in the first and second embodiments, and protrudes in the vertical direction.
In addition, in FIG. 6, although the 1st electrode layer 11 is shown in rectangular shape, it may actually be formed in the shape which rounded four grooves, or an elliptical shape again, and may be formed in a cylindrical shape.
Next, a manufacturing process of the memory cell shown in FIG. 9 will be described.
10 to 10n are cross-sectional views of the manufacturing process of the memory cell shown in FIG.
First, as shown in FIG. 10A, a field oxide film 2 and a channel stop region (not shown) are formed in a predetermined region on the main surface of the silicon substrate 1. The field oxide film is formed using the LOCOS method.
Next, as shown in FIG. 10B, after forming the gate insulating layer 5 by thermal oxidation or the like, gate electrodes (word lines) 4b, 4c, 4d, and 4e made of a polycrystalline silicon layer are selectively formed. do.
Again, the insulating layer 22 is formed around the gate electrodes 4b to 4c by the deposition process of the oxide film of 2 degrees and the etching process.
Again, with the gate electrodes 4b and 4c covered by the insulating layer 22 as a mask, impurity ions are introduced into the surface of the silicon substrate 1 using the ion implantation method, and the source and drain regions 6 and 6 are removed. Form.
Again, as shown in FIG. 10C, for example, high melting point metal layers such as tungsten, molybdenum, and peat are deposited and patterned into a predetermined shape. Thereby, the bit line 15 which directly contacts one source-drain region 6 of a transfer gate transistor is formed. In addition, as the material of the bit line 15, a high melting point metal silicide, a flipside, or the like may be used. Again, the circumference of the bit line 15 is covered with the insulating layer 27.
Again, as shown in FIG. 10D, the polycrystalline silicon layer 11a into which impurities are introduced is deposited on the entire surface on the surface of the silicon substrate 1 by the CVD method. 10 20 / cm 3 or more of impurities are introduced into the polycrystalline silicon layer 110a.
Again, as shown in FIG. 10, for example, the insulating layer 35 of the silicon oxide film is thickly deposited. The height of the mouth wall portion 11b of the lower electrode 11 of the capacitor is defined by the film thickness of the insulating layer 35.
Again, as shown in FIG. 10F, a resist 36 is applied on the surface of the insulating layer 35, and patterned into a predetermined shape using a lithography method or the like. As a result, a resist pattern (capacitor isolation layer) 36 made of the resist 36 is formed. The width of the resist pattern 36 defines the separation interval between capacitors adjacent to each other.
Again, as shown in FIG. 10C, the insulating layer 35 is selectively removed using the resist pattern 35 as a mask. This etching method is performed using anisotropic etching, for example. In addition, when the width of the insulating layer 35 is made smaller than the width of the resist pattern 36, wet etching or the like may be performed again.
Again, as shown in FIG. 10H, after removing the resist pattern 36, the polycrystalline silicon layer 110b into which impurities are introduced is deposited on the entire surface by the CVD method. The film thickness of this polycrystalline silicon layer 110b is formed thinner than the first polycrystalline silicon layer 110a formed below. In other words, the film thickness of the second polycrystalline silicon layer 110b is formed so that the inner diameter shown by L in the figure can be made as large as possible.
For example, a film thickness of about 500 GPa is formed.
In addition, impurities having a concentration of 10 20 / cm 3 or more are introduced into the polycrystalline silicon layer 110b.
Again, as shown in FIG. 10I, a thick resist 37 is applied so that the surface of the second polycrystalline silicon layer 110b is completely covered. The resist 37 is etched back to expose a portion of the second polycrystalline silicon layer 110b covering the upper surface of the insulating layer 35.
Again, as shown in FIG. 10J, the second polycrystalline silicon layer 110b exposed on the surface of the resist 37 is etched, and then the insulating layer 35 is etched away by itself. By the etching, the surface of the first polycrystalline silicon layer 110a is exposed inside the opening where the insulating layer 35 is removed.
Again, as shown in FIG. 10K, only an exposed region of the polycrystalline silicon layer 110a is removed by itself using anisotropic etching. Thereafter, the resist 37 is removed. By this process, the base portion 11a and the mouth wall portion 11b of the lower electrode 11 of the capacitor are formed.
Again, as shown in FIG. 10L, as a dielectric layer on the surface of the lower electrode 11 or the like, a silicon nitride film, a silicon oxide film or a composite film thereof, tantalum pentoxide (Ta 2 O 5 ), and a hafnium oxide film (HaO) 2 ) A thin insulating layer is deposited.
Again, as shown in FIG. 10m, an upper electrode (cell plate) 13 such as a conductive polycrystalline silicon layer is formed on the entire surface. In addition, the cell plate may use, for example, a high melting point metal.
Again, as shown in FIG. 10N, the upper portion of the upper electrode 13 is covered with a thick interlayer insulating layer 20. As shown in FIG. A contact hole is formed in a predetermined region of the interlayer insulating layer 20, and a conductor such as, for example, a polycrystalline silicon layer or tungsten is embedded in the contact hole (not shown). Then, a wiring layer 24 having a predetermined shape made of aluminum or the like is formed on the surface of the interlayer insulating layer 20.
Again, the surface is covered with the protective film 26.
The memory cell is manufactured by the above.
As described above, in the fourth embodiment, the lower electrodes 11 of the capacitors separated from each other by using the insulating layer (capacitor isolation layer) 35 formed by one patterning may be formed by themselves. The distance between adjacent capacitors can be determined to be well controlled by the width of the insulating layer 35.
Again, it is manufactured by a deposition process different from the base portion 11a and the mouth wall portion 11b of the lower electrode 11 of the capacitor 10. Therefore, each film thickness can be easily set. Again, it is also possible to easily change the material of the base portion 11a and the mouth wall portion 11b.
For example, a combination of a high melting point metal, a high melting point metal silicide, or the like is used for the base portion 11a, and a combination using a polycrystalline silicon layer or the like for the mouth wall portion 11b, or the reverse combination. . In addition, impurities of high concentration (10 −20 / cm 3 or more) are introduced into the lower electrode 11 of the capacitor 10. This is to prevent a depletion layer from the lower electrode 11 side widening at the time of operation of the capacitor 3 to increase the resistance, thereby reducing the operation of charge / charge of the charge.
As described above, the semiconductor memory device according to the present invention includes a first capacitor portion formed along the surface of an insulating layer on a substrate, and a second capacitor portion extending in an oblique direction from the outermost circumference of the first portion. Since the capacitor structure is constituted, the capacitance can be increased and secured despite the reduction in the planar footprint of the capacitor.
Again, by arranging the bit lines downward from the main portion of the electrode layer of the capacitor, it becomes possible to separate adjacent capacitors without considering the bit line contact portion, and to refine the separation region, thereby reducing the planar footprint of the capacitor. It becomes possible to increase.
In addition, since the capacitor of the semiconductor memory device according to the present invention is formed to form and pattern a lower electrode layer at a step portion formed of a contact hole and a capacitor isolation layer, separation between adjacent capacitors is easy and integrally integrated. It is possible to form the lower electrode of the electrode, and to improve the reliability of the insulating layer of the capacitor formed thereon.
An insulating layer having a major surface, the second conductive semiconductor substrate having a first conductive type impurity region, and an insulating layer formed on the major surface of the semiconductor substrate and having an opening reaching the impurity region; And a first portion formed in contact with the surface of the impurity region and on the surface of the insulating layer, and a second extending upwardly inclined away from the surface of the insulating layer by rising from an outer periphery of the first portion. And a second electrode layer covering the surface of the first electrode layer, and a second electrode layer covering the surface of the dielectric layer.
An insulating layer having a major surface, the second conductive semiconductor substrate having a first conductive type impurity region, and an insulating layer formed on the major surface of the semiconductor substrate and having an opening reaching the impurity region; And a first portion formed in contact with the surface of the impurity region and on the surface of the insulating layer, extending upwardly from an outer periphery of the first portion and away from the surface of the insulating layer, wherein the semiconductor substrate A first electrode layer having a second portion thinner than the film thickness in the direction perpendicular to the main surface of the semiconductor substrate in the direction parallel to the main surface of the first electrode layer, and the first electrode And a second electrode layer covering the surface of the dielectric layer and a second electrode layer covering the surface of the dielectric layer.
A method of manufacturing a semiconductor memory device having a first and a second stack type capacitor which are mounted on a surface of an insulating layer covering a main surface of a semiconductor substrate and formed separately from each other, wherein the main surface of the semiconductor substrate is provided. Forming a first insulating layer on the surface of the first insulating layer and inside the opening, the first insulating layer having an opening reaching a main surface of the semiconductor substrate at a predetermined position thereon; Forming a first conductive type on the surface of the first insulating layer and in the opening; forming a second insulating layer having a predetermined film thickness on the surface of the first conductive layer; Patterning the insulating layer, and forming a capacitor isolation layer comprising the second insulating layer having a sidewall surface that is substantially vertical only in the isolation regions of the first and second capacitors, the first conductive layer and the Kerr Forming a second conductive layer on the top surface and side surfaces of the sheet separation layer, selectively removing the second conductive layer formed on the top surface of the capacitor separation layer, the capacitor separation layer and Removing a portion of the first conductive layer positioned below the capacitor isolation layer, and forming a dielectric layer on the surface of the second conductive layer; and forming a third conductive layer on the surface of the dielectric layer. A method of manufacturing a semiconductor memory device having a.
A method of manufacturing a semiconductor memory device having a first and a second stack type capacitor which are mounted on a surface of an insulating layer covering a main surface of a semiconductor substrate and formed separately from each other, wherein the main surface of the semiconductor substrate is provided. Forming a first insulating layer on the surface, and forming a second insulating layer on the surface of the first insulating layer. Forming a capacitor isolation layer comprising a second insulating layer having a side surface inclined with respect to a main surface of the semiconductor substrate by etching the second insulating layer using a mask having a predetermined shape; and the first insulating layer. Forming a contact hole reaching a main surface of the semiconductor substrate at a predetermined position of the layer; and forming a first conductive layer on the inner surface of the contact hole, on the surface of the first insulating layer, and on the surface of the capacitor isolation layer. Forming a step, forming an etch back layer having a different etching ratio from the first conductive layer on the surface of the first conductive layer, etching the etch back layer, and placing the etch back layer on an upper surface of the capacitor isolation layer. Exposing the surface of the first conductive layer, partially etching away the first conductive layer exposed from the etch back layer, and forming the first conductive layer and the first capacitor. Separating a portion from the second capacitor portion, removing the capacitor isolation layer and the etch back layer, forming a dielectric layer on the surface of the first conductive layer, and forming a dielectric layer on the surface of the dielectric layer. Forming a second conductive layer in the semiconductor memory device;
A method of manufacturing a semiconductor memory device having first and second stack type capacitors mounted on a surface of an insulating layer covering a main surface of a semiconductor substrate and formed separately from each other, the method comprising: Forming a first insulating layer on the substrate; forming an etch stop layer on the surface of the first insulating layer; forming a second insulating layer on the surface of the etch stop layer; Etching the second insulating layer to form a capacitor isolation layer comprising a second insulating layer having a side inclined with respect to a main surface of the semiconductor substrate on the separation regions of the first and second capacitors. Forming a contact hole reaching a main surface of the semiconductor substrate at a predetermined position of the first insulating layer and the etching stop layer; and an inner surface of the contact hole and the etching Forming a first conductive layer on the surface of the top layer and on the surface of the capacitor isolation layer; forming an etch back layer having a different etching ratio from the first conductive layer on the surface of the first conductive layer; Forming an etch back layer, exposing a surface of the first conductive layer on the upper surface of the capacitor isolation layer, partially etching away the first conductive layer exposed from the epi back layer, and Separating the first conductive layer into the first capacitor portion and the second capacitor portion, removing the capacitor separation layer and the etch back layer, and forming a dielectric layer on the surface of the first conductive layer. And forming a second conductive layer on the surface of the dielectric layer.
A second conductive semiconductor substrate having a major surface and having an impurity region of a first conductivity type thereon, and an upper surface and the impurity formed on a major surface of the semiconductor substrate and substantially parallel to the major surface An insulating layer having an opening reaching a region, a first portion extending from the surface of the impurity region to an upper surface of the insulating layer, and rising from an outer periphery of the first portion to an upper surface of the insulating layer. A semiconductor memory device comprising a first electrode layer having a second portion extending upwardly inclined away from each other, a dielectric layer covering the surface of the first electrode layer, and a second electrode layer covering the surface of the dielectric layer.
A semiconductor memory device having a memory cell array in which a plurality of memory cells for storing unit memory information are arranged, comprising: a semiconductor substrate having a main surface, a plurality of word lines extending in parallel to each other on a main surface of the semiconductor substrate, and the semiconductor A plurality of bit lines extending in a direction orthogonal to the plurality of word lines on the main surface of the substrate, an insulating film formed to cover the word lines and the bit lines, and disposed in the vicinity of an intersection of the bit lines and the word lines. A memory cell, each of the memory cells including one transfer gate transistor and one capacitor, wherein the transfer gate transistor is formed on a main surface of the semiconductor substrate positioned between the bit lines adjacent to each other. The pair of impurity regions formed in the direction along the bit line and the pair of impurity regions A gate electrode formed from a portion of said word line formed on said main surface of said semiconductor substrate via a gate insulating layer, said insulating film having an upper surface substantially parallel to a main surface of said semiconductor substrate, said pair of And an opening for exposing one of the impurity regions of the capacitor, wherein the capacitor includes a first portion formed on the surface of the exposed impurity region of the transfer gate transistor and a first portion of the word line in succession. A second portion extending up to an upper surface of the insulating film located above and above the bit line connected to the other side of the pair of impurity regions of the transfer gate transistor, and an outer periphery of the second portion A first electrode layer having a third portion that rises from and extends upwardly away from the upper surface of the insulating film; A semiconductor memory device provided with a covering and a surface of the dielectric layer and the second electrode covers the side surface of the dielectric layer.
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