Source: https://patents.google.com/patent/US9640458B2/en
Timestamp: 2019-04-20 15:26:07
Document Index: 75651905

Matched Legal Cases: ['Application No. 200505312', 'Application No. 06801011', 'Application No. 10', 'Application No. 095130498', 'Application No. 2008', 'Application No. 200505312', 'Application No. 200505312', 'Application No. 200505312', 'Application No. 200505312']

US9640458B2 - Stacked microelectronic devices - Google Patents
Stacked microelectronic devices Download PDF
US9640458B2
US9640458B2 US14/470,831 US201414470831A US9640458B2 US 9640458 B2 US9640458 B2 US 9640458B2 US 201414470831 A US201414470831 A US 201414470831A US 9640458 B2 US9640458 B2 US 9640458B2
US14/470,831
US20150137364A1 (en
Wang Lai Lee
2005-08-19 Priority to SG200505312-9 priority Critical
2005-08-19 Priority to SG200505312-9A priority patent/SG130055A1/en
2005-08-31 Priority to US11/217,627 priority patent/US7557443B2/en
2009-05-20 Priority to US12/469,455 priority patent/US8507318B2/en
2013-07-02 Priority to US13/933,607 priority patent/US8823159B2/en
2014-08-27 Application filed by Micron Technology Inc filed Critical Micron Technology Inc
2014-08-27 Priority to US14/470,831 priority patent/US9640458B2/en
2015-05-21 Publication of US20150137364A1 publication Critical patent/US20150137364A1/en
2017-05-02 Publication of US9640458B2 publication Critical patent/US9640458B2/en
This application is a continuation of U.S. application Ser. No. 12/469,455 filed May 20, 2009, which is a divisional of U.S. application Ser. No. 11/217,627 filed Aug. 31, 2005, now U.S. Pat. No. 7,557,443, which claims foreign priority benefits of Republic of Singapore Application No. 200505312-9 filed Aug. 19, 2005, now Republic of Singapore Patent No. 130055, each of which is incorporated herein by reference in its entirety.
Another aspect of the invention is directed to methods for manufacturing a plurality of microelectronic devices. In one embodiment, a method includes mounting a plurality of microelectronic dies to a first interposer substrate with the dies arranged in an array, attaching a plurality of second interposer substrates to corresponding microelectronic dies with the microelectronic dies positioned between the first interposer substrate and the associated second interposer substrate, and electrically coupling the second interposer substrates to the first interposer substrate.
FIGS. 6A-6D illustrate stages in another embodiment of a method for manufacturing a plurality of microelectronic devices. For example, FIG. 6A is a schematic side cross-sectional view of an assembly 400 including a plurality of microelectronic dies 410 (only three are shown) arranged in an array on a first interposer substrate 420. The individual microelectronic dies 410 include an integrated circuit 112, an active side 414 attached to the first interposer substrate 420, a plurality of terminals 416 on the active side 414, and a backside 418 opposite the active side 414.
a first interposer substrate having a first side and a second side facing away from the first side;
a microelectronic die having an active side and a backside, wherein the microelectronic die includes a plurality of terminals arranged in an array on the active side, and wherein the backside is attached to the first side of the first interposer substrate, and wherein the microelectronic die has a first lateral surface;
a plurality of interconnect elements positioned corresponding to and electrically coupled to the plurality of terminals;
a second interposer substrate having a first side facing away from the microelectronic die, a second side facing the microelectronic die, a plurality of contacts on the second side corresponding to the plurality of terminals, and a circuitry extending through the second interposer and electrically coupled to the contacts on the second side, and wherein the microelectronic die is positioned between the first and second interposer substrates, and wherein the first interposer substrate is electrically coupled to the microelectronic die via the plurality of terminals, the plurality of contacts of the second interposer substrate, the plurality of interconnect elements, and the circuitry through the second interposer, and wherein the second interposer substrate has a second lateral surface; and
an underfill material positioned between the microelectronic die and the second interposer substrate, wherein the underfill material at least partially bears stress between the microelectronic die and the second interposer substrate, wherein the underfill material is formed with an outmost surface, and wherein the outmost surface is substantially flush with the first lateral surface and the second lateral surface.
a casing around a perimeter portion of the first side of the second interposer substrate and an opening through the casing through which a central region of the first side of the second interposer substrate is exposed.
3. The device of claim 1, wherein the microelectronic die is a first microelectronic die, the plurality of terminals are first terminals, the plurality of interconnect elements are first interconnect elements, and the plurality of contacts are first contacts, and wherein the device further comprises:
a third interposer substrate having a first side and a second side facing away from the first side, the second side facing the second interposer substrate;
a second microelectronic die having a plurality of second terminals arranged corresponding to the array of terminals of the first microelectronic die, wherein the second microelectronic die is attached to the first side of the second interposer substrate;
a plurality of second interconnect elements electrically coupled to the plurality of second terminals;
a fourth interposer substrate attached to the second microelectronic die, wherein the fourth interposer substrate includes a plurality of second contacts, and wherein the second microelectronic die is positioned between the third and fourth interposer substrates, wherein the third interposer substrate is electrically coupled to the second microelectronic die via the plurality of second contacts and the plurality of second interconnect elements; and
an electrical coupling between the second and third interposer substrates.
4. The device of claim 3, wherein the electrical coupling between the second and third interposer substrates includes an array of solderballs.
5. The device of claim 3, wherein the fourth interposer substrate has a first side facing away from the second microelectronic die and a second side opposite from the first side, and wherein the device further comprises:
a casing around a perimeter portion of the first side of the fourth interposer substrate having an opening through which a central region of the first side of the fourth interposer substrate is exposed.
a first contact positioned on the first side of the second interposer substrate and configured to electrically couple to a first corresponding contact of the first interposer substrate; and
a second contact positioned on the first side of the second interposer substrate and configured to electrically couple to a second corresponding contact of the first interposer substrate.
a plurality of pads positioned on the first side of the second interposer substrate and configured to electrically couple to the first contact.
8. The device of claim 6, wherein the second interposer substrate includes:
a conductive trace electrically coupling the first contact to a corresponding one of the contacts positioned on the second side of the second interposer substrate.
9. The device of claim 6, wherein the second interposer substrate includes:
a conductive trace electrically coupling the second contact to a corresponding pad positioned on the first side of the second interposer substrate.
10. The device of claim 1, further comprising a wire-bond for electrically connecting the first interposer substrate and the second interposer substrate.
11. The device of claim 1, wherein the first interposer substrate includes a slot extending between the first side of the first interposer substrate and the second side of the first interposer substrate.
12. The device of claim 1, further comprising a wire-bond for electrically connecting the microelectronic die and the first interposer substrate.
the circuitry through the second interposer substrate is coupled to a plurality of first contacts at the first side of the second interposer substrate;
the first contacts at the first side of the second interposer substrate are electrically coupled to at least one contact at the second side of the second interposer substrate; and
the wire-bond is connected to the first interposer substrate and one of the first contacts at the first side of the second interposer substrate.
14. The device of claim 1, wherein the first interposer substrate is electrically coupled to the second interposer substrate by at least one wire-bond.
US14/470,831 2005-08-19 2014-08-27 Stacked microelectronic devices Active US9640458B2 (en)
SG200505312-9 2005-08-19
SG200505312-9A SG130055A1 (en) 2005-08-19 2005-08-19 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US11/217,627 US7557443B2 (en) 2005-08-19 2005-08-31 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US12/469,455 US8507318B2 (en) 2005-08-19 2009-05-20 Method for manufacturing microelectronic devices
US13/933,607 US8823159B2 (en) 2005-08-19 2013-07-02 Stacked microelectronic devices
US14/470,831 US9640458B2 (en) 2005-08-19 2014-08-27 Stacked microelectronic devices
US15/583,826 US20170301598A1 (en) 2005-08-19 2017-05-01 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US13/933,607 Continuation US8823159B2 (en) 2005-08-19 2013-07-02 Stacked microelectronic devices
US15/583,826 Continuation US20170301598A1 (en) 2005-08-19 2017-05-01 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US20150137364A1 US20150137364A1 (en) 2015-05-21
US9640458B2 true US9640458B2 (en) 2017-05-02
ID=38787675
US11/217,627 Active 2026-12-18 US7557443B2 (en) 2005-08-19 2005-08-31 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US12/469,455 Active 2026-05-22 US8507318B2 (en) 2005-08-19 2009-05-20 Method for manufacturing microelectronic devices
US13/933,607 Active US8823159B2 (en) 2005-08-19 2013-07-02 Stacked microelectronic devices
US14/470,831 Active US9640458B2 (en) 2005-08-19 2014-08-27 Stacked microelectronic devices
US15/583,826 Pending US20170301598A1 (en) 2005-08-19 2017-05-01 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US (5) US7557443B2 (en)
EP (1) EP1929521A2 (en)
JP (1) JP2009508324A (en)
KR (1) KR101021761B1 (en)
SG (1) SG130055A1 (en)
TW (1) TWI333267B (en)
WO (1) WO2007024483A2 (en)
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2005-08-19 SG SG200505312-9A patent/SG130055A1/en unknown
2005-08-31 US US11/217,627 patent/US7557443B2/en active Active
2006-08-08 WO PCT/US2006/030969 patent/WO2007024483A2/en active Application Filing
2006-08-08 EP EP06801011A patent/EP1929521A2/en not_active Ceased
2006-08-08 KR KR1020087005359A patent/KR101021761B1/en active IP Right Grant
2006-08-08 JP JP2008526996A patent/JP2009508324A/en active Pending
2006-08-18 TW TW095130498A patent/TWI333267B/en active
2009-05-20 US US12/469,455 patent/US8507318B2/en active Active
2013-07-02 US US13/933,607 patent/US8823159B2/en active Active
2014-08-27 US US14/470,831 patent/US9640458B2/en active Active
2017-05-01 US US15/583,826 patent/US20170301598A1/en active Pending
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US20170301598A1 (en) 2017-10-19
US20150137364A1 (en) 2015-05-21
KR101021761B1 (en) 2011-03-15
US8823159B2 (en) 2014-09-02
US20130292853A1 (en) 2013-11-07
US20070045796A1 (en) 2007-03-01
WO2007024483A2 (en) 2007-03-01
SG130055A1 (en) 2007-03-20
US8507318B2 (en) 2013-08-13
EP1929521A2 (en) 2008-06-11
TWI333267B (en) 2010-11-11
US7557443B2 (en) 2009-07-07
JP2009508324A (en) 2009-02-26
WO2007024483A8 (en) 2008-11-27
US20090239337A1 (en) 2009-09-24
WO2007024483A3 (en) 2007-05-31
KR20080031510A (en) 2008-04-08