Source: https://patents.google.com/patent/JP5490330B1/en
Timestamp: 2020-06-02 11:41:12
Document Index: 44474300

Matched Legal Cases: ['art 28', 'art 301', 'art 301', 'art 301', 'art 301', 'art 301', 'art 302', 'art 302', 'art 302', 'art 302', 'art 302', 'arts 301', 'arts 301', 'arts 301', 'art 301', 'art 301', 'art 302', 'art 302', 'art 301', 'art 301', 'art 302', 'art 302', 'Application No. 2012']

JP5490330B1 - Image data receiving apparatus and image data transmission system - Google Patents
Image data receiving apparatus and image data transmission system Download PDF
JP5490330B1
JP5490330B1 JP2013544046A JP2013544046A JP5490330B1 JP 5490330 B1 JP5490330 B1 JP 5490330B1 JP 2013544046 A JP2013544046 A JP 2013544046A JP 2013544046 A JP2013544046 A JP 2013544046A JP 5490330 B1 JP5490330 B1 JP 5490330B1
JP2013544046A
JPWO2013176055A1 (en
晋 川田
貴博 田邊
2012-05-24 Priority to JP2012118777 priority Critical
2012-05-24 Priority to JP2012118777 priority
2013-05-17 Application filed by オリンパスメディカルシステムズ株式会社 filed Critical オリンパスメディカルシステムズ株式会社
2013-05-17 Priority to JP2013544046A priority patent/JP5490330B1/en
2013-05-17 Priority to PCT/JP2013/063803 priority patent/WO2013176055A1/en
2014-05-14 Publication of JP5490330B1 publication Critical patent/JP5490330B1/en
2016-01-12 Publication of JPWO2013176055A1 publication Critical patent/JPWO2013176055A1/en
The image data receiving apparatus receives a first signal receiving a first signal including serial data corresponding to the image data, and a second signal including serial data different from the serial data included in the first signal. A second receiving unit for receiving, a first converting unit for converting serial data included in the first signal into parallel data and outputting the parallel data, and converting serial data included in the second signal into parallel data; A second conversion unit that outputs, a bit shift amount detection unit that acquires information indicating how much the parallel data output from the second conversion unit is shifted from a predetermined bit pattern, and a bit shift amount detection A bit shift unit that shifts parallel data output from the first conversion unit according to the information obtained by the unit.
The present invention relates to an image data receiving apparatus and an image data transmission system, and more particularly to an image data receiving apparatus and an image data transmission system related to transmission of image data obtained by imaging a subject.
An endoscope that captures an image of a subject in a subject and acquires an image, and an endoscope signal processing device that performs various signal processing on the image acquired by the endoscope are provided as main parts. Endoscopic systems are conventionally used.
Further, in the endoscope system as described above, for example, as disclosed in Patent Document 1, A / D conversion processing is performed on an analog image obtained by imaging a subject inside the endoscope. In recent years, a configuration in which digital data (image data) obtained by the A / D conversion processing is transmitted to an endoscope signal processing device is being adopted.
Specifically, Japanese Patent Application Laid-Open No. 2009-233178 discloses that an A / D conversion process is performed on an analog tool imaging signal obtained by imaging a subject inside an endoscope, and the A / D conversion process is performed. A configuration is disclosed in which an obtained digital signal is transmitted as a digital transmission signal to an endoscope signal processing device.
However, according to the configuration disclosed in Japanese Patent Application Laid-Open No. 2009-233178, a predetermined insertion signal is inserted in the non-signal period of the digital transmission signal, which is a period corresponding to the blanking period of the analog imaging signal. As a result, there is a problem that the signal quality when receiving the digital transmission signal transmitted from the endoscope may be deteriorated.
The present invention has been made in view of the above-described circumstances, and provides an image data receiving apparatus and an image data transmission system capable of improving the signal quality when receiving a signal including image data as compared with the prior art. The purpose is to do.
According to another aspect of the present invention, there is provided an image data receiving device that captures a first signal including serial data obtained by serializing image data obtained by capturing an image of a subject with an operation clock corresponding to a predetermined clock signal. A first receiving unit that receives from the device and second serial data that is different from the serial data included in the first signal, wherein the second clock signal generated according to the clock signal is serial data. A second receiving unit that receives the second signal including the converted second serial data from the imaging device, and the serial data included in the first signal received by the first receiving unit is parallel data. a first serial / parallel converter for converting and outputting the said second included in the received second signal in said second receiver Based on the second serial / parallel converter that converts the real data into parallel data and outputs the parallel data, the parallel data output from the second serial / parallel converter, and a predetermined bit pattern, the second A bit shift amount detection unit for acquiring information indicating how much each bit value included in parallel data output from the serial / parallel conversion unit is shifted from each bit value of the predetermined bit pattern; and A bit shift unit that bit-shifts the parallel data output from the first serial / parallel conversion unit according to the information obtained by the bit shift amount detection unit.
An image data transmission system according to an aspect of the present invention includes: an imaging unit that captures an image of a subject and acquires image data; and first serial data obtained by converting the image data into serial data using an operation clock corresponding to a predetermined clock signal . A first transmission unit for transmitting the second signal and second serial data different from the serial data included in the first signal, wherein the second clock signal generated according to the clock signal is serialized. A second transmission unit for transmitting a second signal including the converted second serial data ; and receiving the first signal transmitted from the first transmission unit. Included in the first signal received by the first receiver, the second receiver that receives the second signal transmitted from the second transmitter, and the first receiver Be Converting a first serial / parallel converter for converting the real data to parallel data, said second serial data included in the received second signal in said second receiver into parallel data And output from the second serial / parallel converter, the parallel data output from the second serial / parallel converter, and a predetermined bit pattern, from the second serial / parallel converter. A bit shift amount detection unit that acquires information indicating how much each bit value included in the output parallel data is shifted from each bit value of the predetermined bit pattern, and obtained by the bit shift amount detection unit. A bit shift unit for bit-shifting the parallel data output from the first serial / parallel conversion unit according to the received information; Having the image data receiving device provided with a.
The block diagram which shows the structure of the principal part of the image data transmission system containing the image data receiver which concerns on the Example of this invention. The flowchart for demonstrating an example of the control performed by the transmission / reception control part which concerns on a present Example. The figure which shows an example of the structure which can be integrated in the receiving circuit which concerns on a present Example. 1 is a diagram illustrating an example of a configuration of a connection interface that can be employed in an image data transmission system according to an embodiment.
1 and 2 relate to an embodiment of the present invention. FIG. 1 is a block diagram showing a configuration of a main part of an image data transmission system according to an embodiment of the present invention.
As shown in FIG. 1, the imaging system 101 is a camera that exchanges various signals and data with an imaging apparatus 1 that includes a video scope or a rigid endoscope camera head. The image data transmission system includes a control unit (hereinafter referred to as CCU) 2.
An imaging device 1 having a function as an image data transmission device includes an imaging unit 11, a timing generator 12, a frequency multiplication unit 13, a frequency dividing circuit 14, and P / S (parallel / serial) conversion units 15A and 15B. And the transmission circuits 16A and 16B and the emphasis adjustment unit 17.
The imaging unit 11 includes an imaging element 11a made of a CCD or the like and an A / D (analog / digital) conversion unit 11b.
The image sensor 11a is driven according to an HD (horizontal drive) signal and a VD (vertical drive) signal output from the timing generator 12, and photoelectrically converts a subject imaged on a light receiving surface by an optical system (not shown). It is configured to output an analog imaging signal (take an image) (acquire an image).
The A / D conversion unit 11b samples the imaging signal output from the imaging element 11a every predetermined period, thereby changing the signal level of each pixel in the imaging signal to a 0 or 1 bit value of a predetermined number of bits. It is configured to convert into digital data and output.
In other words, the imaging unit 11 is configured to acquire an image by capturing an image of a subject and acquire digital data (image data) of the image.
The timing generator 12 generates and outputs an HD signal and a VD signal for defining the drive timing of the image sensor 11a based on the clock signal and the synchronization signal output from the CCU 2.
The frequency multiplier 13 includes an error detection function capable of detecting an error in the clock signal output from the CCU 2. The frequency multiplication unit 13 resets the clock signal based on the error detection result by the error detection function, multiplies the frequency of the reset clock signal by a predetermined magnification, and divides the multiplied clock signal. The circuit 14, the P / S conversion unit 15 </ b> A, and the transmission circuit 16 </ b> A are each output.
The divider circuit 14 generates a divided clock signal by dividing the clock signal output from the frequency multiplier 13 according to the number of bits of digital data for one pixel output from the imaging unit 11. It is configured to output to the P / S converter 15B.
Specifically, for example, in the case where N-bit data is output from the imaging unit 11 as data for one pixel, the frequency divider circuit 14 divides the clock signal output from the frequency multiplier 13 by N. The frequency-divided clock signal generated by the rounding is output to the P / S converter 15B.
The P / S conversion unit 15A includes a serializer and the like, and operates each bit value of the digital data output (in parallel) from the imaging unit 11 in accordance with the frequency of the clock signal output from the frequency multiplication unit 13. Are converted into serial data and output to the transmission circuit 16A.
The P / S conversion unit 15B includes a serializer and the like, and is configured to convert the divided clock signal output from the frequency dividing circuit 14 into serial data and output the serial data to the transmission circuit 16B.
The transmission circuit 16A includes a buffer, a driver, and the like, and is configured to convert digital data output (serially) from the P / S conversion unit 15A into a differential transmission signal of a predetermined method such as an LVDS method. ing.
Further, the transmission circuit 16A can adjust the emphasis amount of the differential transmission signal transmitted to the reception circuit 24A (described later) of the CCU 2 based on the control signal output from the transmission / reception control unit 28 (described later) of the CCU 2. The emphasis adjusting unit 17 is provided.
According to the configuration of the transmission circuit 16A as described above, digital data output (serially) from the P / S conversion unit 15A is converted into a differential transmission signal of a predetermined system, and the converted differential signal The transmission signal is modulated so as to add a preset emphasis amount under the control of a transmission / reception control unit 28 (described later), and the differential transmission signal subjected to the modulation is output from the frequency multiplication unit 13. Can be transmitted to the CCU 2 at a transmission rate corresponding to the frequency of the clock signal to be transmitted.
The transmission circuit 16B includes a buffer, a driver, and the like, and converts the divided clock signal (converted into serial data) output from the P / S conversion unit 15B into a differential transmission signal of a predetermined system such as the LVDS system. And transmitted to the CCU 2.
Then, according to the configuration of the frequency dividing circuit 14, the transmission circuit 16A, and the transmission circuit 16B as described above, the transmission rate of the differential transmission signal output from the transmission circuit 16B is the difference output from the transmission circuit 16A. It is set to be 1 / N times the transmission rate of the dynamic transmission signal.
On the other hand, the CCU 2 having a function as an image data receiving device includes a clock generation unit 21, a synchronization signal generation unit 22, a frequency multiplication unit 23, reception circuits 24A and 24B, and S / P (serial / parallel) conversion. 25A and 25B, a bit shift amount detection unit 26, a bit shift unit 27, a transmission / reception control unit 28, and a clock phase adjustment unit 29.
The clock generation unit 21 generates a clock signal having a predetermined frequency used for the operation of each unit of the imaging device 1 and the CCU 2 and outputs the clock signal to the imaging device 1 and the synchronization signal generation unit 22.
The synchronization signal generation unit 22 generates a synchronization signal used to generate the HD signal and the VD signal based on the clock signal output from the clock generation unit 21 and outputs the synchronization signal to the imaging device 1.
The frequency multiplier 23 multiplies the frequency of the clock signal output from the clock generator 21 by a predetermined magnification (same as the magnification of the frequency multiplier 13), and outputs it to the receiving circuit 24A and the S / P converter 25A. Is configured to do.
The reception circuit 24A includes a pulse transformer or the like so that the differential transmission signal transmitted from the transmission circuit 16A of the imaging apparatus 1 can be received with an operation clock corresponding to the frequency of the clock signal output from the frequency multiplication unit 23. It is configured.
The reception circuit 24A converts the differential transmission signal demodulated as described above into (serial) digital data, and outputs the converted digital data to the S / P conversion unit 25A and the transmission / reception control unit 28. It is configured.
Further, the reception circuit 24A can adjust the phase of the operation clock that defines the reception timing of the differential transmission signal transmitted from the transmission circuit 16A based on the control signal output from the transmission / reception control unit 28. An adjustment unit 29 is provided.
According to the configuration of the reception circuit 24A as described above, the differential transmission signal transmitted from the transmission circuit 16A of the imaging device 1 is converted into an operation clock corresponding to the frequency of the clock signal output from the frequency multiplication unit 23, And it can receive at the timing corresponded to the phase of the clock signal preset by control of the transmission / reception control part 28. FIG.
The reception circuit 24B includes a pulse transformer and the like, receives the differential transmission signal transmitted from the transmission circuit 16B of the imaging device 1, and further, converts the divided clock signal corresponding to the received differential transmission signal to serial data. Is restored and output to the S / P converter 25B.
The S / P converter 25A includes a deserializer and the like, and operates each bit value of the digital data output (serially) from the receiving circuit 24A according to the frequency of the clock signal output from the frequency multiplier 23. Are converted to parallel data and output to the bit shift unit 27.
The S / P conversion unit 25B includes a deserializer and the like, and is configured to convert the divided clock signal (converted into serial data) output from the reception circuit 24A into parallel data and output the parallel data to the bit shift amount detection unit 26. ing.
The bit shift amount detection unit 26 holds a predetermined bit pattern having the same number of bits as the frequency-divided clock signal output from the S / P conversion unit 25B (converted into parallel data). Then, the bit shift amount detection unit 26 compares the predetermined bit pattern with the frequency-divided clock signal output from the S / P conversion unit 25B, and outputs it from the S / P conversion unit 25B (parallel). A bit shift amount indicating how much each bit value included in the frequency-divided clock signal (which has been converted into data) is shifted from each bit value included in the predetermined bit pattern is detected, and the detected bit shift amount Is output to the bit shift unit 27.
The bit shift unit 27 performs a correction process in which each bit value included in the parallel data output from the S / P conversion unit 25A is bit-shifted according to the bit shift amount information output from the bit shift amount detection unit 26. The parallel data subjected to the correction processing can be output to an image processing circuit (not shown) located at the subsequent stage of the CCU 2.
When the bit shift unit 27 detects that the bit shift amount is 0 based on the information of the bit shift amount output from the bit shift amount detection unit 26, the bit shift unit 27 outputs the bit shift amount from the S / P conversion unit 25A. That is, the parallel data output from the S / P converter 25A is output as it is to an image processing circuit (not shown).
The transmission / reception control unit 28 is configured to generate and output a control signal for controlling the transmission circuit 16A and the reception circuit 24A based on the digital data output (serially) from the reception circuit 24A. Yes. Details of the control performed by the transmission / reception control unit 28 on the transmission circuit 16A and the reception circuit 24A will be described later.
Next, the operation and the like of the imaging system 101 of this embodiment will be described. In the following description, unless otherwise specified, the description will be given with an example in which 8-bit data is generated as data for one pixel. FIG. 2 is a flowchart for explaining an example of control performed by the transmission / reception control unit according to the present embodiment.
First, almost immediately after the power of each unit of the imaging system 101 is turned on, the clock signal generated by the clock generation unit 21 is transmitted to the frequency multiplication units 13 and 23, and the clock signal multiplied by the frequency multiplication unit 13 is transmitted. The clock signal output to the transmission circuit 16A and multiplied by the frequency multiplier 23 is output to the reception circuit 24A.
Thereafter, the transmission / reception control unit 28 transmits a control signal for starting transmission of a predetermined data string having a predetermined bit value to the transmission circuit 16A (step S1 in FIG. 2) and is transmitted from the transmission circuit 16A. A control signal for sequentially changing the phase of the operation clock that defines the reception timing of the differential transmission signal (by the operation of the clock phase adjustment unit 29) is transmitted to the reception circuit 24A (step S2 in FIG. 2).
The transmission / reception control unit 28 compares the digital data sequentially output from the reception circuit 24A in accordance with the fluctuation of the phase of the operation clock by the clock phase adjustment unit 29 with a predetermined data string transmitted by the control of the transmission circuit 16A. Thus, the phase margin as a phase range in which the predetermined data string can be normally received by the receiving circuit 24A is measured, and it is further determined whether or not the measured phase margin is a predetermined threshold value or more. This is performed (step S3 in FIG. 2).
When the transmission / reception control unit 28 obtains a determination result that the phase margin is less than the predetermined threshold value in step S3 in FIG. 2, the transmission / reception control unit 28 sets the emphasis amount to be added to the differential transmission signal (the emphasis adjustment unit 17). After the control signal for increasing the predetermined amount is transmitted to the transmission circuit 16A (step S4 in FIG. 2), the process returns to step S2 in FIG.
In addition, when the transmission / reception control unit 28 obtains a determination result that the phase margin is equal to or larger than the predetermined threshold in step S3 of FIG. 2, the transmission / reception control unit 28 is within the range of the phase margin measured immediately before obtaining the determination result. A control signal for setting the phase of the operation clock (the reception timing of the differential transmission signal transmitted from the transmission circuit 16A) to be the center value is transmitted to the reception circuit 24A (step S5 in FIG. 2), and the determination After the control signal for adding the emphasis amount immediately before obtaining the result to the differential transmission signal is transmitted to the transmission circuit 16A, the control signal for stopping the transmission of the predetermined data string is transmitted to the transmission circuit 16A (FIG. 2 step S6).
2 is performed, the signal level of the differential transmission signal output from the transmission circuit 16A is set to an appropriate signal level according to the transmission distance from the imaging device 1 to the CCU 2. As a result, it is possible to optimize the power consumption related to the transmission of the differential transmission signal in various combinations of the imaging device 1 and the CCU 2.
On the other hand, after the series of controls shown in FIG. 2 is performed, the clock signal generated by the clock generation unit 21 and the synchronization signal generated by the synchronization signal generation unit 22 are output to the timing generator 12. .
The image pickup device 11a is driven according to the HD signal and the VD signal supplied from the timing generator 12, thereby picking up an image of the subject and outputting an analog image pickup signal.
The A / D converter 11b samples the imaging signal output from the imaging element 11a every predetermined period, thereby converting the signal level of each pixel in the imaging signal into 8-bit digital data and outputting the digital data.
The frequency dividing circuit 14 outputs the divided clock signal generated by dividing the clock signal output from the frequency multiplying unit 13 by 8 to the P / S converting unit 15B.
The P / S conversion unit 15A serializes each bit value of the 8-bit digital data output (in parallel) from the imaging unit 11 with an operation clock corresponding to the frequency of the clock signal output from the frequency multiplication unit 13. To the transmission circuit 16A.
The P / S conversion unit 15B converts the divided clock signal output from the frequency dividing circuit 14 into serial data and outputs the serial data to the transmission circuit 16B.
The transmission circuit 16A converts the digital data output (serially) from the P / S conversion unit 15A into a differential transmission signal of a predetermined method, and the emphasis amount set through the series of controls shown in FIG. The converted differential transmission signal is modulated so as to be added, and the modulated differential transmission signal is received at a transmission speed corresponding to the frequency of the clock signal output from the frequency multiplier 13. Transmit to circuit 24A.
The transmission circuit 16B converts the frequency-divided clock signal (converted into serial data) output from the P / S conversion unit 15B into a differential transmission signal of a predetermined system such as the LVDS system, and transmits it to the reception circuit 24B. .
The reception circuit 24A is an operation clock corresponding to the frequency of the clock signal output from the frequency multiplication unit 23 for the differential transmission signal transmitted from the transmission circuit 16A of the imaging device 1, and the series of the series of the series illustrated in FIG. The received differential transmission signal is received at a reception timing set through control, and the received differential transmission signal is converted into (serial) digital data. Further, the converted digital data is output to the S / P converter 25A.
The reception circuit 24B receives the differential transmission signal transmitted from the transmission circuit 16B of the imaging device 1, restores the divided clock signal corresponding to the received differential transmission signal as serial data, and converts the S / P converter. Output to 25B.
The S / P converter 25A converts each bit value of the digital data output (serially) from the receiving circuit 24A into parallel data at an operation speed corresponding to the frequency of the clock signal output from the frequency multiplier 23. To the bit shift unit 27.
The S / P converter 25B converts the divided clock signal output from the receiving circuit 24A (converted into serial data) into parallel data and outputs the parallel data to the bit shift amount detector 26.
The bit shift amount detection unit 26 outputs an output from the S / P conversion unit 25B by comparing a predetermined bit pattern of 8 bits with the divided clock signal output by 8 bits from the S / P conversion unit 25B. A bit shift amount indicating how much each bit value included in the divided clock signal is shifted from each bit value included in the predetermined bit pattern is detected, and information on the detected bit shift amount is obtained. Output to the bit shift unit 27.
The bit shift unit 27 bit-shifts each bit value included in the parallel data output by 8 bits from the S / P conversion unit 25A according to the information of the bit shift amount output from the bit shift amount detection unit 26. Correction processing is performed, and the parallel data subjected to the correction processing is output to an image processing circuit (not shown).
Specifically, when the bit shift unit 27 detects that a shift of one bit has occurred based on the information of the bit shift amount output from the bit shift amount detection unit 26, for example, Correction processing is performed such that each bit value of 8-bit parallel data input at the timing when the occurrence of the shift is detected is shifted by one bit, and the parallel data subjected to the correction processing is converted into an image processing circuit (not shown). Output).
Then, by performing the processing and operations as described above in the bit shift unit 27 and the like, the parallel data that has been subjected to correction processing (bit-shifted) so that the imaging device 1 and the CCU 2 are appropriately synchronized with each other. Can be output to an image processing circuit (not shown) located at the subsequent stage of the CCU 2.
As described above, according to the present embodiment, when a differential transmission signal is transmitted from the transmission circuit 16A to the reception circuit 24A, data such as a synchronization pattern used for synchronization between the imaging device 1 and the CCU 2 is superimposed. Not. As a result, according to the present embodiment, it is possible to improve the signal quality when receiving a signal including image data as compared with the conventional case.
Further, as described above, according to the present embodiment, the imaging device 1 and the CCU 2 can be connected without superimposing data such as a synchronization pattern on the differential transmission signal transmitted from the transmission circuit 16A to the reception circuit 24A. It can be synchronized properly.
Further, as described above, according to the present embodiment, correction is performed so that the imaging apparatus 1 and the CCU 2 are appropriately synchronized at each timing when the information on the bit shift amount is output from the bit shift amount detection unit 26. Processing (bit shift) is performed in the bit shift unit 27. As a result, according to the present embodiment, even when a sudden bit shift due to a disturbance or the like occurs, the bit shift can be corrected immediately, so that the imaging apparatus 1 and the CCU 2 are appropriately configured. The period not synchronized can be shortened as much as possible.
Note that the receiving circuit 24A according to the present embodiment includes, for example, each unit as illustrated in FIG. 3 so that the duty cycle distortion generated in the differential transmission signal is reduced while relaxing the restriction on the transition time in the differential transmission signal. You may comprise so that digital data (image data) can be received in the suppressed state. FIG. 3 is a diagram illustrating an example of a configuration that can be incorporated into the receiving circuit according to the present embodiment.
Specifically, for example, as shown in FIG. 3, the receiving circuit 24A of the present embodiment is connected to an insulating circuit 241 to which a differential transmission signal transmitted from the transmitting circuit 16A is input, and a subsequent stage of the insulating circuit 241. A bias circuit 242, a termination circuit 243 connected to a subsequent stage of the bias circuit 242, and a D / S (differential / single end) conversion circuit 244 that converts a differential transmission signal that has passed through the termination circuit 243 into a single-ended signal; , A data receiving unit 245 that receives digital data corresponding to a single-end signal output from the D / S conversion circuit 244, a reception control unit 246, and a D / A conversion circuit 247. Also good.
The bias circuit 242 applies a bias voltage corresponding to the power supply voltage Vcc to one signal line (hereinafter also referred to as a first signal line) of the two signal lines related to the transmission of the differential transmission signal. The connected resistor R1, the resistor R2 connected between the first signal line and the ground voltage GND, and the other signal line of the two signal lines (hereinafter also referred to as the second signal line). On the other hand, a resistor R3 connected to apply a bias voltage corresponding to the output voltage of the D / A conversion circuit 247 and a resistor R4 connected between the second signal line and the ground voltage GND are provided. doing.
Termination circuit 243 has a termination resistor R5 connected between the first signal line and ground voltage GND, and a termination resistor R6 connected between the second signal line and ground voltage GND. ing.
The reception control unit 246 is configured to output a control signal for changing the bias voltage applied to the second signal line by the bias circuit 242 to the D / A conversion circuit 247. The bias voltage applied to the second signal line via the resistor R3 of the bias circuit 242 as the output voltage of the D / A conversion circuit 247 changes according to the control signal output from the reception control unit 246. Is changed.
In addition, for example, every time the above-described control signal is output to the D / A conversion circuit 247, the reception control unit 246 sequentially changes the phase of the operation clock of the data reception unit 245 while the data reception unit 245 The phase margin of the data receiving unit 245 when an arbitrary bias voltage is applied to the second signal line of the bias circuit 242 by performing an operation for determining whether or not data can be normally received. It is comprised so that it can measure.
Further, the reception control unit 246 applies a control signal D for applying a bias voltage that maximizes the phase margin to the second signal line of the bias circuit 242 based on the measurement result of the phase margin measured as described above. / A conversion circuit 247 is configured to be able to output.
The operation related to the measurement of the phase margin and the change of the bias voltage by the reception control unit 246 is transmitted almost immediately after the power of each unit of the imaging system 101 is turned on, for example, as a series of processes shown in FIG. It is desirable to use a predetermined data string transmitted from the circuit 16A.
Therefore, the reception circuit 24A having the configuration described above reduces the duty cycle distortion caused by variations in the D / S conversion circuit 244 while relaxing restrictions on the transition time in the differential transmission signal. Digital data (image data) can be received in a suppressed state.
By the way, according to the present embodiment, for example, by adopting the configuration of the connection interface as shown in FIG. 4, the electrical connection between the imaging device 1 and the CCU 2 is performed before the operation related to the imaging of the subject is performed. It may be possible to notify the user that an abnormality has occurred in the general connection. FIG. 4 is a diagram illustrating an example of the configuration of a connection interface that can be employed in the image data transmission system according to the present embodiment.
Specifically, according to the present embodiment, for example, the electrical connection unit 301 as shown in FIG. 4 is provided around the connector (not shown) at the end of the cable extending from the imaging device 1, and the CCU 2 A configuration of a connection interface in which an electrical connection portion 302 as shown in FIG. 4 is provided around a connector insertion port (not shown) may be adopted.
The electrical connection part 301 relates to switching of each switch of the contact part 301A having a plurality of electrical contacts, the relay switch part 301B having the same number of switches as the number of electrical contacts of the contact part 301A, and the relay switch part 301B. A connection control unit 301C that performs control and a resistor R11 connected between the node N11 and the ground voltage GND are provided.
Based on the control of the connection control unit 301C, the relay switch unit 301B is in a conductive state in which each electrical contact of the contact unit 301A is connected to the original connection destination, or each electrical contact of the contact unit 301A is different from the original connection destination. Each switch can be operated so as to be in a non-conducting state connected to another connection destination.
In addition, the relay switch unit 301B is configured to maintain a non-conductive state when the electrical connection units 301 and 302 are not connected.
The connection control unit 301C includes a timer or the like that starts an operation according to the voltage applied to the node N11, and when it detects that a predetermined time has elapsed since the timer started the operation, It is configured to perform control to switch the state (for each switch) of the unit 301B from the non-conductive state to the conductive state.
The electrical connection part 302 relates to switching of each switch of the contact part 302A having a plurality of electrical contacts, the relay switch part 302B having the same number of switches as the number of electrical contacts of the contact part 302A, and the relay switch part 302B. A connection control unit 302C that performs control and a resistor R12 connected between the node N12 and the power supply voltage Vcc are provided.
Based on the control of the connection control unit 302C, the relay switch unit 302B is in a conductive state in which each electrical contact of the contact unit 302A is connected to the original connection destination, or each electrical contact of the contact unit 302A is different from the original connection destination. Each switch can be operated so as to be in a non-conducting state connected to another connection destination.
Further, the relay switch unit 302B is configured to maintain a non-conductive state when the electrical connection units 301 and 302 are not connected.
When the connection control unit 302C detects that the voltage at the node N12 is greater than a predetermined value TH (<Vcc) by monitoring the voltage at the node N12, the connection control unit 302C changes the state (for each switch) of the relay switch unit 302B. When the non-conductive state is detected and it is detected that the voltage of the node N12 is equal to or lower than the predetermined value TH, the relay switch unit 302B is controlled to be in the conductive state (for each switch).
On the other hand, as shown in FIG. 4, when the contact switch parts 301A and 302A are connected while the relay switch parts 301B and 302B are both in a non-conductive state, the electrical connection parts 301 and 302 are changed from the node N11 to the node N12. Each part existing in the middle (each electrical contact of the contact part 301A, each switch of the relay switch part 301B, each electrical contact of the contact part 302A, and each switch of the relay switch part 302B) is connected in series. Wired to
Therefore, when the electrical connection portions 301 and 302 are connected, the potential difference between the power supply voltage Vcc of the electrical connection portion 302 and the ground voltage GND of the electrical connection portion 301, the resistance values of the resistors R11 and R12, Depending on the resistance value of each electrical contact of the part 301A, the resistance value of each switch of the relay switch part 301B, the resistance value of each electrical contact of the contact part 302A, and the resistance value of each switch of the relay switch part 302B The divided voltages are applied to the node N11 and the node N12, respectively.
Here, the voltage applied to the node N11 when the electrical connection portions 301 and 302 are connected increases in resistance value due to the formation of an oxide film among the electrical contacts included in the contact portions 301A and 302A. It decreases as the number of electrical contacts increases (approaching the voltage value of the ground potential).
Therefore, the connection control unit 301C monitors the voltage of the node N11 using the timer as described above, so that the voltage applied to the node N11 when the electrical connection units 301 and 302 are connected is less than the operating voltage of the timer. If this is detected, it is estimated that the number of electrical contacts whose resistance value has increased due to the formation of an oxide film or the like is a predetermined number or more, and the state of each relay switch unit 301B (for each switch) Is controlled so as to be maintained in a non-conductive state.
Further, the connection control unit 301C monitors the voltage of the node N11 using the timer as described above, so that the voltage applied to the node N11 when the electrical connection units 301 and 302 are connected becomes equal to or higher than the operating voltage of the timer. If it is detected that a predetermined time has passed, the number of electrical contacts whose resistance value has increased due to the formation of an oxide film or the like is estimated to be less than the predetermined number, and the relay switch section Control is performed to switch the state of 301B (of each switch) from the non-conductive state to the conductive state.
On the other hand, the resistance value of the voltage applied to the node N12 when the electrical connection portions 301 and 302 are connected is increased due to the formation of an oxide film among the electrical contacts included in the contact portions 301A and 302A. It rises as the number of electrical contacts increases (approaching the voltage value of the power supply voltage Vcc).
Therefore, when the connection control unit 302C detects that the voltage applied to the node N12 when the electrical connection units 301 and 302 are connected is monitored by monitoring the voltage of the node N12, the oxide film It is presumed that the number of electrical contacts whose resistance value has increased due to the formation of the switch is greater than or equal to a predetermined number, and control is performed so that the state (for each switch) of the relay switch unit 302B is made non-conductive. And an image processing circuit (not shown) that generates a signal having information capable of notifying that an abnormality has occurred in the electrical connection between the imaging apparatus 1 and the CCU 2 (positioned after the CCU 2). Output). Then, a signal having such information is subjected to image processing by an image processing circuit (not shown), and the image-processed signal is output to a display device (not shown) such as a monitor. It is possible to notify the user that an abnormality has occurred in the electrical connection between 1 and CCU2.
In addition, the connection control unit 302C monitors the voltage at the node N12 to detect that the voltage applied to the node N12 when the electrical connection units 301 and 302 are connected is equal to or lower than the predetermined value TH. It is estimated that the number of electrical contacts whose resistance value has increased due to the formation of a film or the like is less than a predetermined number, and the relay switch unit 302B (each switch) is controlled to be in a conductive state. Do.
Note that, according to the configuration of the connection interface as described above, for example, the voltage value of the power supply voltage Vcc is adjusted according to the total number of electrical contacts included in the contact portions 301A and 302A. And the oxide film may be broken when 302 and 302 are connected.
According to the configuration of the connection interface as described above, the user is informed that an abnormality has occurred in the electrical connection between the imaging device 1 and the CCU 2 before the operation related to imaging of the subject is performed. Since it can notify, it can suppress that the imaging system 101 is used exceeding the preset number of times of use.
In addition, this invention is not limited to the Example mentioned above, Of course, a various change and application are possible within the range which does not deviate from the meaning of invention.
This application is filed on the basis of the priority claim of Japanese Patent Application No. 2012-118777 filed in Japan on May 24, 2012. It shall be cited in the drawing.
A first receiving unit that receives, from the imaging device, a first signal including serial data obtained by converting image data obtained by imaging an object in the imaging device into serial data using an operation clock corresponding to a predetermined clock signal ;
Second serial data that is different from serial data included in the first signal, and includes second serial data obtained by converting the second clock signal generated according to the clock signal into serial data . A second receiving unit that receives the signal from the imaging device;
A first serial / parallel converter that converts serial data included in the first signal received by the first receiver into parallel data and outputs the parallel data;
A second serial / parallel converter that converts the second serial data contained in the second signal received by the second receiver into parallel data and outputs the parallel data;
Based on the parallel data output from the second serial / parallel converter and a predetermined bit pattern, each bit value included in the parallel data output from the second serial / parallel converter is the predetermined data A bit shift amount detection unit for acquiring information indicating how much the bit pattern is shifted with respect to each bit value;
A bit shift unit for bit-shifting parallel data output from the first serial / parallel conversion unit according to the information obtained by the bit shift amount detection unit;
An image data receiving apparatus comprising:
Based on the serial data included in the first signal received by the first receiving unit, the period in which the predetermined data string can be normally received by the first receiving unit is equal to or greater than a predetermined threshold value. Control for performing control for adjusting the amount of emphasis added to the first signal transmitted to the first reception unit and the reception timing of the first signal in the first reception unit, respectively. The image data receiving apparatus according to claim 1, further comprising a unit.
When the first reception unit receives a differential transmission signal including a predetermined data string from the imaging apparatus, the first reception unit normally receives the bias data applied to the received differential transmission signal. The image data receiving apparatus according to claim 1, wherein the image data receiving apparatus is adjusted so as to maximize a possible period.
An imaging unit that images a subject and acquires image data;
A first transmitter that transmits a first signal including serial data obtained by converting the image data into serial data using an operation clock corresponding to a predetermined clock signal ;
Second serial data that is different from serial data included in the first signal, and includes second serial data obtained by converting the second clock signal generated according to the clock signal into serial data . A second transmitter for transmitting the signal of
An image data transmission device comprising:
A first receiver for receiving the first signal transmitted from the first transmitter;
A second receiver for receiving the second signal transmitted from the second transmitter;
An image data receiving device comprising:
An image data transmission system comprising:
The image data receiving device has a predetermined period during which a predetermined data string can be normally received by the first receiving unit based on serial data included in the first signal received by the first receiving unit. The emphasis amount added to the first signal transmitted from the first transmission unit and the reception timing of the first signal in the first reception unit are adjusted so as to be equal to or greater than a threshold value. The image data transmission system according to claim 4, further comprising a control unit that performs control to perform the control.
When the first receiving unit receives a differential transmission signal including a predetermined data string from the image data transmitting apparatus, the first receiving unit applies a bias voltage applied to the received differential transmission signal to normalize the predetermined data string. The image data transmission system according to claim 4, wherein adjustment is performed so that a period during which the signal can be received is maximized.
The image data transmission device determines a transmission rate of the second signal transmitted from the second transmission unit when the data for one pixel included in the image data is N bits, in the first transmission. 5. The image data transmission system according to claim 4, wherein the image data transmission system is set to be 1 / N times the transmission rate of the first signal transmitted from the unit.
When electrical connection portions provided respectively in the image data transmitting device and the image data receiving device are connected, the presence or absence of an abnormality in the electrical connection portion is detected, and further, an abnormality in the electrical connection portion is detected. 5. The image data transmission system according to claim 4, wherein an occurrence of an abnormality in electrical connection between the image data transmission device and the image data reception device is notified.
JP2013544046A 2012-05-24 2013-05-17 Image data receiving apparatus and image data transmission system Active JP5490330B1 (en)
JP2012118777 2012-05-24
JP2013544046A JP5490330B1 (en) 2012-05-24 2013-05-17 Image data receiving apparatus and image data transmission system
PCT/JP2013/063803 WO2013176055A1 (en) 2012-05-24 2013-05-17 Image data receiver and image data transmission system
JP5490330B1 true JP5490330B1 (en) 2014-05-14
JPWO2013176055A1 JPWO2013176055A1 (en) 2016-01-12
ID=49623749
JP2013544046A Active JP5490330B1 (en) 2012-05-24 2013-05-17 Image data receiving apparatus and image data transmission system
US (1) US9007436B2 (en)
EP (1) EP2745766A4 (en)
JP (1) JP5490330B1 (en)
CN (1) CN103930014B (en)
WO (1) WO2013176055A1 (en)
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2013-05-17 WO PCT/JP2013/063803 patent/WO2013176055A1/en active Application Filing
2013-05-17 EP EP13794141.5A patent/EP2745766A4/en not_active Withdrawn
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