Source: http://www.google.com/patents/US5517470?dq=6076065
Timestamp: 2013-12-09 01:05:25
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Patent US5517470 - Nonvolatile control architecture - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsA digital rheostat or potentiometer which provides both increment and decrement operations from a single input such as a pushbutton. A certain pattern of input actuations will cause the direction of change to reverse. Settings of the potentiometer are stored in nonvolatile memory....http://www.google.com/patents/US5517470?utm_source=gb-gplus-sharePatent US5517470 - Nonvolatile control architecturePublication numberUS5517470 APublication typeGrantApplication numberUS 08/388,042Publication dateMay 14, 1996Filing dateFeb 10, 1995Priority dateMar 30, 1990Fee statusPaidAlso published asUS5544063, US5548550, US5717935Publication number08388042, 388042, US 5517470 A, US 5517470A, US-A-5517470, US5517470 A, US5517470AInventorsKevin E. Deierling, Francis A. Scherpenberg, Gary V. ZandersOriginal AssigneeDallas Semiconductor CorporationPatent Citations (5), Referenced by (5), Classifications (22), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetNonvolatile control architectureUS 5517470 AAbstract A digital rheostat or potentiometer which provides both increment and decrement operations from a single input such as a pushbutton. A certain pattern of input actuations will cause the direction of change to reverse. Settings of the potentiometer are stored in nonvolatile memory.
What is claimed is: 1. A nonvolatile memory cell, comprising:(a) a tunneling node; (b) a control node; (c) a floating node; (d) a tunneling capacitor coupling said tunneling node to said floating node; (e) a control capacitor coupling said control node to said floating node, said control capacitor of capacitance larger than the capacitance of said tunneling capacitor; (f) a voltage polarity switch connected to said tunneling node and to said control node, said switch having at least a first state and a second state of operation with the voltage from said tunneling node to said control node being positive when said switch is in said first state and with said voltage being negative when said switch is in said second state; (g) whereby programming and erasing said floating node may both are performed through said tunneling capacitor by selection of the polarity of the voltage from said tunneling node to said control node. Description
DESCRIPTION OF THE PREFERRED EMBODIMENTS Overview of Architecture FIG. 1 shows in block form the overall circuit architecture of the first preferred embodiment control unit, generally denoted by reference numeral 100. Control unit 100 takes the form of an integrated circuit with terminals R.sub.H (resistor high end), R.sub.L (resistor low end), R.sub.W (resistor wiper), +V and -V (power supply voltage inputs), UC (up contact input), D (digital input), and DC (down contact input). Tapped resistor string 140 provides a voltage output, at wiper output terminal R.sub.W, which can be selected to fall at any one of many points between the voltage applied at "high" terminal R.sub.H and "low" terminal R.sub.L. (It is not actually necessary for the polarity of the applied voltage to be higher at R.sub.H than at R.sub.L ; this relationship could be reversed if desired. However, the following description assumes that this is the case, so that an increase in the value stored in counter 130 will correspond to an increase in the voltage at output terminal R.sub.W.) In other words, the resistance between output R.sub.W and R.sub.L or R.sub.H varies as the value stored in counter 130 varies. In the presently preferred embodiment, resistor string 140 is tapped at sixty-four separate points along its length. However, it is contemplated that for future versions it may well be preferable to use 128 or 256 tap points. Each of the sixty-four resistors 142 has a resistance which depends upon the total resistance from R.sub.L to R.sub.H. For example, if the total resistance were 10K, then each resistor 142 would have a resistance of about 156 ohms, and this would be the resolution of control unit 100. Similarly, if there were 256 tap points for a 100K total resistance, then the resolution would be 390 ohms.
Thus, only one of the gates 134 will be turned on at a given instant, and the state of the counter 130 determines which gate that will be. Whichever one of the gates 134 is currently active will connect a respective tap point in resistor string 140 to "wiper" output terminal R.sub.W. Thus, the value stored in counter 130 will determine the value of the resistance seen between R.sub.W and R.sub.H (and between R.sub.W and R.sub.L).
Overview of Operation FIG. 4 is a flowchart for the operation of control unit 200 which has terminal DC connected to +V and a pushbutton between UC and -V. In particular, a low going pulse of duration at least 1 millisecond input at either of terminals D or UC ("Contact closure" in the upper lefthand portion of FIG. 4) results in an increment or decrement by 1 of the value held in counter 130 and a consequent change in the resistance between terminals R.sub.W and -V (R.sub.L) by one resistor 142 resistance. Note that each of the terminals D, UC, and DC is pulled up to the internal power supply (+V which is about +5 volts) by 100 Kohm resistors (see FIG. 6 described in the following section). Subsequent input low going pulses will increment or decrement for each pulse. However, if the input remains active (low) for greater than 1 second, then increments or decrements will be automatically generated at intervals of 100 msec for as long as the input is active or until an end of the resistor string is reached; see the bottom lefthand portion of FIG. 4. Anytime that input activity stops for a period of time greater than 1 second, the direction of change will be reversed; that is, if a series of increments have been input followed by a 1 second pause, then the next input pulse will yield a decrement. The direction also reverses when an end of the resistor string is reached. See the righthand portion of FIG. 4. The total time to move from one end to the other end of the resistor string by holding an input continuously active is about 7.4 seconds: 1 second to begin automatic generation plus 6.4 seconds for 64 intervals of 100 msec each.
Nonvolatile Wiper Settings The wiper setting of control units 100 or 200 is maintained in shadow memory 120 or 220 when the control unit is powered down. During normal operation the position of the wiper is determined by decoder 130 or multiplexer 230. Shadow memory 120 or 220 is periodically updated by the multiplexer during normal operation. The manner in which an update occurs has been optimized for reliability, durability, and performance and is totally transparent to the user. When power is applied to a control unit the wiper setting is set at the last value recorded in the shadow memory. On an initial power up for the first time, the wiper position may, therefore, be random. If the control unit setting is changed after power is applied, the new value will be stored in the shadow memory after a delay of about two seconds. The initial storing of a new value after power up always occurs if a change is made and this change is not related to time. After the initial change, subsequent changes in the control unit setting of less than 12.5% are not copied in the shadow memory. Since the control unit contains a 64 to 1 multiplexer, a change in the 3 LSBs is not copied into the shadow memory except for change after power up or if the change is large enough to effect the 4th LSB or greater. Changes greater than 12.5% are always copied into the shadow memory. As on power up, the copy from the multiplexer to shadow memory allows for a two second delay to guarantee that the new setting changes are finalized, and all shadow updates are transparent to the user. On power down (loss of power) the shadow memory is not changed and retains the most recent update resulting from a setting change. This value is used to set the control unit counter value on power up. The shadow memory is made with EEPROM type memory cells that will accept at least 20,000 writes before wear out. If the EEPROM cells ever reach a wearout condition, the control unit will still continue to operate properly while power is applied, but will return to the last accepted value of the shadow memory on power up.
Test Mode Application of 8-10 volts to the D input terminal triggers test mode of operation in which a test clock may be fed into the wiper output terminal R.sub.W and this test clock will clock in test bits from the high output terminal R.sub.H into a test register and then run tests.
Block Diagram FIG. 6 shows in functional block format control unit 100 of FIG. 1, and FIGS. 7-56 provide details of circuitry within the blocks. In particular, FIG. 6 illustrates control unit 100 as composed of the following blocks: control logic CNTL 610 (FIGS. 7-10 including state diagrams), clock CLK 6 12 (FIGS. 11-12), shadow memory EE 620 (FIGS. 13-38), shadow memory control EE.sub.-- CNTL 622 (FIG. 39), counter WIPER.sub.-- COUNTER 630 (FIGS. 40-43), counter decoder DECODER64 632 (FIG. 44), resistor array R.sub.-- ARRAY 640 (FIGS. 45-46), input logic INPUTS 650 (FIGS. 47-49), up/down counter UD.sub.-- CNTL 652 (FIG. 50), timer TIMER 660 (FIGS. 51-52), TFL input buffer INBUFTTL 670 (FIG. 53), test mode buffer IN.sub.-- BUF 672 (FIG. 54), test mode detector HV 674 (FIG. 55), and power up reset circuitry PU 676 (FIG. 56), plus terminals UC (up count), DC (down count), D (data), R.sub.-- low (resistor string low end R.sub.L), R.sub.W (resistor string wiper R.sub.W), R.sub.-- hi (resistor string high end R.sub.H), V +, and V-. Terminals HVD and HVS connect to the drain and source of high voltage FET with gate driven by the HV output of block EE 620 and used for testing the high voltage generator.
Control Logic FIG. 7 shows control logic CNTL 610 as a state machine with three latches 701-703 (each latch made of cross-coupled NAND gates) with six feedback lines 710 plus three input lines 711-713. The six feedback lines are labelled with the corresponding latch output (Y1, Y1.sub.--, Y2, Y2.sub.--, Y3, and Y3.sub.--) and the three input lines are labelled D (an inversion of the DONE.sub.-- input) and T and T.sub.-- (the TOUCHF input and its complement). Also, DONE.sub.-- directly feeds one of the NAND gates which drive latch 702. Note that a trailing underscore (".sub.-- ") generally denotes the complement of a signal, so Y 1.sub.-- is the complement of Y1. Six logical combinations of the nine lines generate the COUNT.sub.-- PULSE, START0.sub.-- 1.sub.--, START1.sub.--, RSTC.sub.--, REVERSE1, and IDLE outputs. A power up reset (RST and RST.sub.--) will directly drive the latches 701-703 to Y 1.sub.--, Y2.sub.--, and Y3.sub.-- all high and also drive D low (see FIG. 16a for DONE.sub.--) and T low (see FIG. 47). Thus a power up reset puts the state machine in the 000 state where the notation represents the values of Y1,Y2,Y3 with 1 indicating high and 0 low; the reset also sets D and T low and T.sub.-- high. And the outputs are then COUNT.sub.-- PULSE low, START0.sub.-- I.sub.-- and START1.sub.-- both high, RSTC.sub.-- high, REVERSE1 low, and IDLE high. Each combination of the DONE.sub.-- and TOUCHF signals determines the transitions among the eight states of the state machine as follows:
______________________________________DONE.sub.-- =1, TOUCHF=0:000 and 100 are stable         010 &#8594; 100         001 &#8594; 101 &#8594; 100         011 &#8594; 111 &#8594; 110 &#8594; 100DONE.sub.-- =1, TOUCHF=1 001 and 111 are stable         000 &#8594; 001         011 &#8594; 111         110, 010 &#8594; 100 &#8594; 101 &#8594; 001DONE.sub.-- =0, TOUCHF=0 000 and 110 are stable         010 &#8594; 110         001 &#8594; 101 &#8594; 100 &#8594; 000         011 &#8594; 111 &#8594; 110DONE.sub.-- =0, TOUCHF=1 111 and 110 are stable         000 &#8594; 001 &#8594; 011 &#8594; 111         100 &#8594; 101 &#8594; 001 &#8594; 011 &#8594; 111         010 &#8594; 110______________________________________
Note that a transition takes about 2-5 nsec and thus various short pulses may be generated within the logic generating the outputs COUNT.sub.-- PULSE, START0.sub.-- 1.sub.--, START1.sub.--, RSTC.sub.--, REVERSE1, and IDLE. In particular, FIG. 8 shows the structure of each of the pulse generators 721-723 as three flip-flops 731-733 with a feedback from flip-flop 732 to the reset input of flip-flop 731. A low-to-high transition at the IN node sets flip-flop 731 high and drives the OUT node high two CLK cycles later and also resets flip-flop 731 low. The high at OUT persists for one CLK cycle, and flip-flop 731 remains low until the next low-to-high at IN. A short high pulse (e.g., 2-5 nsec) at IN suffices to set flip-flop 731 high and thereby generate the one CLK cycle high pulse at OUT when CLK is active.
As detailed below, the UC, DC, and D inputs drive TOUCHF; and DONE.sub.-- goes low (active) for one CLK cycle when a selected time interval completes and the selection signal (e.g., START1.sub.--) remains active. FIG. 9 is a state diagram showing DONE.sub.-- and TOUCHF driving the state changes and essentially distills out the stable states from the foregoing list of state transitions.
FIG. 10 provides an alternative format state diagram which indicates the actions taking place in control unit 100. Control unit 100 essentially operates in four modes: The Idle mode with no incrementing/decrementing (state 000); a first waiting mode starting when a button has been pushed (to generate a single increment/decrement) and waiting to see if the button will be held down (state 001); the fast count mode which generates an increment/decrement every 0.1 second while the button is held down (state 111); and a second waiting mode to see if a direction reversal is intended when the button has been released (state 100). In particular, the broken line box in the upper lefthand portion of FIG. 10 represents the Idle state which is state 000. As shown, the Idle state persists until there is "contact" which means one of the terminals UC, DC, D has gone low and driven TOUCHF high. TOUCHF going high has two immediate effects: (1) NAND gate 741 goes low and thus NAND gate 743 goes high to set pulse generator 721 and (2) latch 703 switches to Y3=1 so the state changes to 001. Now Y3 going high drives NAND gate 757 high and output IDLE low which turns on the oscillator in block CLK 612 to start a stream of CLK and CLK.sub.-- pulses. The CLK and CLK.sub.-- pulses drive pulse generator 721 to output a high COUNT.sub.-- PULSE pulse (which increments or decrements the position counter in block WIPER.sub.-- COUNTER 630). The box labelled "inc/dec" between state 000 and state 001 in FIG. 10 represents this COUNT.sub.-- PULSE pulse. Y3 going high also switches NAND gate 746 low and thus NAND gate 757 high and output START1.sub.-- low to start timing a 1 second interval. Lastly, Y3 going high returns NAND gate 741 high and thus NAND gate 742 applies a low to pulse generator 721 to ready it for another pulse generation.
The broken line box in the top center portion of FIG. 10 shows state 001 persisting while "contact" continues (TOUCHF remains high) and the 1 second time interval has not expired. First consider the case of"contact" continuing for more than 1 second; this implies entry into the fast count mode as suggested by the feedback in the broken line box showing state 111 in the righthand portion of FIG. 10. Indeed, when the 1 second time interval expires DONE.sub.-- goes low (active) for one CLK period and this drives a transition from state 001 through state 011 and into state 111. That is, first Y2 switches from 0 to 1, and then Y1 switches from 0 to 1.
Y2 switching from 0 to 1 means output START0.sub.-- 1.sub.-- goes low to start timing a 0.1 second interval. And then Y1 switching high means NAND gate 742 goes low and pulse generator 721 outputs another high pulse at COUNT.sub.-- PULSE which again increments or decrements the counter in WIPER.sub.-- COUNTER. As before, a box labelled "inc/dec" indicates this pulse. Y1 going high also drives NAND gate 746 high which switches NAND gate 747 low and output START1.sub.-- high (inactive). The broken line box in the righthand portion of FIG. 10 shows state 111 persisting while "contact" continues (TOUCHF remains high); this is the fast count mode which generates a COUNT.sub.-- PULSE pulse every 0.1 second until "contact" terminates as follows. When the 0.1 second time interval expires DONE.sub.-- goes low (active) for one CLK cycle and this drives NAND gate 742 low and NAND gate 743 high to generate a high pulse at output COUNT.sub.-- PULSE which increments or decrements the counter in WIPER.sub.-- COUNTER (see the "inc/dec" box within state 111). DONE.sub.-- going low also resets the timer (see FIG. 51 ) to restart the 0.1 second interval. That is, the 0.1 second interval completion drives DONE.sub.-- low for one CLK cycle, generates a COUNT.sub.-- PULSE pulse, and restarts another 0.1 second interval. This repeats as long as TOUCHF remains high. TOUCHF going low (e.g., the held down button is released) drives a transition from state 111 to state 100 to wait to see if direction reversal occurs.
The case of state 001 with the "contact" terminating prior to the 1 second time interval completion (the button is released prior to fast count mode) is as follows. TOUCHF going low leads to a transition from state 001 through state 101 to state 100; that is, first Y1 goes high, then Y3 goes low. Now Y1 going high switches NAND gate 745 low and NAND gate 746 high (note that Y1 goes high just prior to Y1.sub.-- going low so there is no glitch) so NAND gate 747 remains high and output START1.sub.-- remains low (active) so the time interval continues. Then when Y3 goes low there is no change and START1.sub.-- persists low.
Release of a button drives the control unit into state 100 which persists as long as TOUCHF is low (no "contact" occurring) and the 1.0 second time interval has not completed. The broken line box at the bottom of FIG. 10 illustrates state 100. If a button is pushed prior to completion of the 1.0 second time interval which began when the button was released, thus generates a COUNT.sub.-- PULSE pulse to again increment/decrement the counter in WIPER.sub.-- COUNTER and the control unit transitions into state 001. Conversely, if the 1.0 second time interval completes without any button pushing, then the increment/decrement direction changes and control unit reverts to the idle state 000.
FIG. 10 omits one aspect of the operation of control unit 100: the control unit reverses increment/decrement direction upon reaching the end of the resistor string, that is, when the count in the WIPER.sub.-- COUNTER equals 0 or 63.
(a) When UC goes low block INPUTS 650 (see FIG. 47) immediately turns on oscillator OSC in block CLK 612 (FIG. 11 below) to begin the CLK and CLK.sub.-- signals cycling at 8 KHz, and if UC remains low for at least three CLK cycles (about 375 microsecond): this filters out short UC inputs, then TOUCHF goes high and switches state machine from state 000 to state 001. That is, in addition to T and T.sub.-- switching, Y3 and Y3.sub.-- also switch. The outputs then change as follows: IDLE goes low and this keeps OSC oscillating and CLK cycles (see FIG. 11 ); START1.sub.-- goes low and starts TIMER dividing CLK cycles; and COUNT.sub.-- PULSE generates a high pulse. Note that the COUNT.sub.-- PULSE pulse comes from T switching high and driving NAND gate 711 low for about 2 nanoseconds (nsec) until the switching of Y3.sub.-- from high to low reaches NAND gate 711 and drives it back high. This 2 nsec pulse suffices to drive the input IN of pulse generator 721 and trigger its output high. The first CLK cycle resets the output of pulse generator 721 low and completes the COUNT.sub.-- PULSE pulse which has a duration of about 250 microseconds. The COUNT.sub.-- PULSE pulse clocks counter 1101 (see FIG. 40) to increment or decrement, depending upon the CNTL signal from UD.sub.-- CNTL 652.
(b) If UC persists low for one second, then TIMER 660 will drive DONE.sub.-- low and this will switch the state machine from state 001 through state 011 to state 111 and the outputs will change.
(c) Conversely, if UC returns high within one second, then DONE.sub.-- will remain high and TOUCHF will switch back low. This drives the state machine from state 001 to state 100, and Y1 goes high about 4 nsec prior to Y3 going low, so IN has a high pulse at pulse generator 722 and RSTC.sub.-- has a low output pulse which resets divider 1602 in TIMER (FIG. 51)
(d) While in state 100, the state machine outputs a low IDLE and OSC keeps running until another UC (or DC or DIG.sub.-- IN) input or until a one second timeout expires.
(e) Analogous to the UC going low case, when DC goes low INPUTS also turns on OSC and if DC remains low for three CLK cycles, then TOUCHF goes high and the state machine switches from state 000 to 001. Similarly, DIG.sub.-- IN going low also turns on OSC and drives TOUCHF high but without the necessity of a three CLK cycle duration to filter out short pulses.
Clock Generator FIG. 11 illustrates clock generator CLK 612 which includes an oscillator OSC and a divider CLK.sub.-- DIV6 to divide the output of OSC by 64 (26). FIG. 12 shows OSC as two cross-coupled five-inverter ring oscillators (one in the upper half of FIG. 12 and the other in the lower half) with the frequency of oscillation primarily determined by the resistance in and the capacitance loading on inverters 811-812 in the lefthand portion of FIG. 12; that is, the RC time constant determines the frequency of oscillation. The resistance can be selected by metal layer options during fabrication of the control unit; also, the four bits on bus SET&lt;3:0&gt; control futher capacitive loading for programmable control of the frequency of oscillation. The resistance can be selected in the range of 16K to 92K and the capacitance with 0000 on bus SET &lt;3:0&gt; is about 0.14 pF and this roughly triples with 1111 on the bus. Thus the frequency of oscillation can be initially selected in the range of about 900 KHz to 1 MHz and lowered by programming up to a factor of three. Oscillator OSC outputs a symmetrical square wave ranging between the high and low power supply voltages (e.g., +5 volts and ground).
The input at EN controls oscillator OSC, and EN is high (and OSC running) when any of INPUTS.sub.-- HI, IDLE, or TIMER.sub.-- NOT.sub.-- RUNNING is low. INPUTS.sub.-- HI derives from input block INPUTS 650 and goes low when any of the three inputs UP.sub.--, DOWN.sub.--, or DIG.sub.-- IN goes low; that is, when control unit 100 recieves an input to changes the resistor setting (see FIG. 47). Thus a resistor change input starts up oscillator OSC. And INPUTS.sub.-- HI continues low as long as the UP.sub.--, DOWN.sub.--, or DIG.sub.-- IN stays low; for example, when the pushbutton in FIG. 3 is held down.
IDLE derives from control CNTL and goes low when any of Y1.sub.--, Y2.sub.--, or Y3.sub.-- switches low which means any change from the idle state 000; see FIGS. 7, 8 and 9.
TIMER.sub.-- NOT.sub.-- RUNNING derives from timer TIMER 660 and goes low when any of START0.sub.-- 1.sub.--, START1.sub.--, or START1.sub.-- EE.sub.-- switches low. Now START0 1 and START1.sub.-- derive from control CNTL and switch low when the state machine changes from state 001 to state 111 for START0.sub.-- 1.sub.-- and from state 000 to state 001 or to state 100 for START1.sub.--. Such state changes arise from input TOUCHF changing.
START1.sub.-- EE.sub.-- derives from EE.sub.-- CNTL 622 and goes low if both (i) REVERSE 1 is high (see FIG. 7) and (ii) either latch 1005 is high (the power up reset case) or any of the three most significant bits stored in EE and differ from the corresponding bits currently in WIPER.sub.-- COUNTER so that the EEPROM must be updated.
EEPROM Array Architecture FIG. 13 shows the shadow memory block EE 620 as including four nonvolatile 6-bit registers NOVREG0, NOVREG1, NOVREG2, and NOVREG3 in parallel (i.e., redundant) on 6-bit data bus EE&lt;5:0&gt; and which also connects to 6-bit bus COUNT&lt;5:0&gt; through a transmission gate. Shadow memory block EE 620 also includes nonvolatile register selection decoder EEBANKDEC to select one of the four nonvolatile registers NOVREGj for current use, 4-bit cycler NPOINT to rotate selection among the four nonvolatile registers NOVREGj, high voltage generator PROGSTOP, controller EECNTL, main clock timing trim CLKSET, input/output pad driver RH.sub.-- IOPAD, test register TESTREG, test decoder EEDEC8, and test logic gates fed from 8-bit test bus TESTEN&lt;7:0&gt;. Block EE 620 basically operates as follows.
Each of the four nonvolatile registers NOVREGj is the same as the 6-bit register illustrated in FIG. 14 and includes six flip-flops EEFF with one flip-flop for each bit of bus DBUS&lt;5:0&gt; which connects to bus EE&lt;5:0&gt;.
A low-to-high transition by CLK isolates node D from memory cell 903 and effectively transfers the bit held by memory cell 903 to memory cell 904, and a subsequent high-to-low CLK transition reverts to the isolation of the memory cells 903-904 plus writes the input at node D into memory cell 903. FIG. 14 shows that repeated clocking by CLK transitions permits a data stream at input DIN to be serially loaded into nonvolatile register NOVREG because the Q output of each flip-flop EEFF ties to the subsequent input node D of the adjacent flip-flop. Further, FIG. 13 shows that the four nonvolatile registers NOVREGj are serially connected with NOVREG0 having its DIN input connected to output Q3 of 4-bit cycler NPOINT and with NOVREG3 havings its QOUT connected to the DIN input of . . . CLKSET. FIG. 16 shows CLKSET to just be a four bit register made of four flip-flops EEFF. Thus all four nonvolatile registers NOVREGj plus CLKSET can be serially loaded by CLK clocking. Note that the four bits held in CLKSET feed bus SETC&lt;3:0&gt; which connects to four bit bus SET&lt;3:0&gt; and controls the capacitors in oscillator OSC as illustrated in FIG. 12 to set the frequency of oscillation. Thus CLKSET sets the speed of the clock.
FIG. 18 shows 4-bit cycler NPOINT as including four nonvolatile flip-flops PEB0, . . . PEB3 each of which has the structure shown in FIG. 19. The outputs of the flip-flops PEB0 . . . PEB3 appear as Q0 . . . Q3 on the bus Q&lt;3:0&gt;. Note that the structure in FIG. 19 duplicates that in FIG. 15 with the omission of the read and write busses. 4-bit cycler NPOINT has a feedback loop from the output of PEB3 to the input of PEB0 via transmission gate 1810 and inverter 1812. 4-bit cycler NPOINT operates as follows.
CLK clocking (during test mode) drives PEB0 . . . PEB3 to shift a serial bit stream at input D of 4-bit cycler NPOINT through to output Q3 in the same manner as described in connection with flip-flop EEFF of FIG. 15 and nonvolatile registers NOVREGj. Also, note that the Q3 output of NPOINT connects to the D input of NOVREG0, and the D input of NPOINT connects to the DIN output of buffer RH.sub.-- IOPAD. FIG. 23 shows buffer RH.sub.-- IOPAD has node DQ connected through a NAND gate and an inverter to output DIN; thus a serial bit stream at node DQ may be clocked through RH.sub.-- IOPAD (when TESTMODE is high), NPOINT, top to bottom NOVREGs, and CLKSET by CLK. This permits initialization of the memories in NPOINT, the four NOVREGj, and CLKSET; and each of these subcircuits has a nonvolatile memory for retaining the initialization bits.
EEPROM Cell Architecture FIG. 22 illustrates EEPROM-storage cell EECELL in schematic form. Cell EECELL includes floating gate NMOS device 2201 with floating gate 2211 coupled by a small tunneling capacitor 2221 to tunneling node 2225 and coupled by a large control capacitor 2231 to control node 2235. Thus capacitors 2221 and 2231 form a series coupling of tunneling node 2225 to control node 2235 with floating gate 2211 connecting the capacitors. The capacitor dielectric in both capacitors is 100 Angstrom of silicon dioxide, and the area of the large control capacitor is about twenty-five times that of the small tunneling capacitor. CMOS inverters 2240 and 2250 are cross coupled to form a latch with the output of inverter 2240 (and input to inverter 2250) being tunneling node 2225 and the output of inverter 2250 (and input to inverter 2240) being control node 2235. Inverters 2240 and 2250 are powered by the voltage at node HV which ramps up from about +4 volts to +20 volts during programming of the cell but which is at ground otherwise. NMOS device 2260 is a pass gate from the DATA input node to the input of inverter 2240, and NMOS device 2270 connects the floating gate NMOS device 2201 to the data output node OUT. Cell EECELL operates as follows; first consider the case of the floating gate 2211 with no net charge.
High Voltage Programmer FIG. 26 schematically illustrate the high voltage programmer PROGSTOP that ramps node HV from high minus a threshold (about +4 volts) to +20 volts, detects programming completion, and then drops HV back to ground upon completion. Generator PROGSTOP includes charge pump NEWPUMP, programmable cells ROTSTOP, comparator EECOMP, diode-connected NMOSs 2610, NOR gate latch 2620, NAND gate 2630, and inverters. In turn, programmable cells ROTSTOP (FIG. 27) includes four programmable flip-flops PROGFF0 . . . PROGFF3, decoder PROGDEC, and four transmission gate pairs PROGTG0 . . . PROGTG3. FIG. 28 shows programmable flip-flop PROGFFj as including latches 2801 and 2802 and EEPROM memory cell PROGCELL which is shown in FIG. 29. PROGCELL is analogous to EECELL (FIG. 22) but with the two floating gates oppositely connected; that is, the floating gate connected to the gates of FETs 2901 and 2902 has the small tunneling capacitor connected to node tgate and the large control capacitor connected to node cgate, but the floating gate connected to the gates of FETs 2911 and 2912 has the small tunneling capacitor connected to node cgate and the large control capacitor connected to node tgate.
Counter Control FIG. 39 shows that control block EE CNTL 622 includes block UPDATE 3901 which NANDs the bitwise exclusive NOR of the three most significant bits on busses COUNT&lt;5:0&gt; and EE&lt;5:0&gt;, NOR gate 3911, flip-flop 3921, and RS flip-flop 3931. EE.sub.-- CNTL 622 operates as follows. First, the power up reset RST high pulse resets flip-flop 3921 to Q=0 and Q.sub.-- =1 which puts STORE.sub.-- REQ low. The RST high pulse further sets the NOR gate latch 3905 to output a high to NOR gate 3902; latch 3905 remains in this state until STORE.sub.-- REQ goes high. The RST high pulse also drives NOR gate 3922 to send a low to reset RS flip-flop 3931 and thereby set START1.sub.-- EE.sub.-- high (inactive).
When a high pulse arrives at REVERSE1 (from block CNTL, see FIG. 7) it drives NAND gate 3904 to output a low pulse to set RS flip-flop 393 1 high and thereby make START1.sub.-- EE.sub.-- active low. Note that a change from state 100 to state 000 (see FIGS. 9 and 10) when DONE.sub.-- goes low leads to the REVERSE1 high pulse. Next, when DONE EE (from block TIMER and FIG. 51) goes low it drives NOR gate 3911 high which sets flipflop 3721 high when clocked by CLK to thereby put STORE.sub.-- REQ high. Note that DONE.sub.-- EE.sub.-- goes low after a one second delay from START1 (from block CNTL and FIG. 7) going low, and START1.sub.-- goes low due to a change from state 000 to state 001 or on to state 100.
STORE.sub.-- REQ high both triggers a storage of the bits on COUNT&lt;5:0&gt; in the EEPROM memory and a switching of latch 3905 to a low output to NOR gate 3902. Latch 3905 continues to output a low regardless of STORE.sub.-- REQ until another power up reset RST pulse resets it. Thus after the first STORE.sub.-- REQ high following a power up reset, latch 3905 has no influence.
When any of the three most significant bits on busses COUNT&lt;5:0&gt; and EE &lt;5:0&gt; differ, UPDATE 3701 outputs a high to NOR gate 3702 which inverts it as does inverter 3903 to feed a high to NAND gate 3904. Then a high pulse at REVRESE 1 will again set RS flip-flop 3931 to put START1.sub.-- EE.sub.-- low (active) and again drive STORE.sub.-- REQ high when DONE.sub.-- EE.sub.-- goes low following START1.sub.-- going low. In short, each REVERSE1 high pulse will lead to a STORE.sub.-- REQ either when one or more of the three most significant bits on busses COUNT &lt;5:0&gt; and EE &lt;5:0&gt; differ or when a power up reset has just occurred.
Wiper Counter FIG. 40 shows that counter block WIPER.sub.-- COUNTER 630 includes 6-bit counter 4001 connecting to 6-bit bus COUNT&lt;5:0&gt; as output and 6-bit bus EE&lt;5:0&gt;, as input. COUNT.sub.-- PULSE clocks counter 4001 except when all bits on bus COUNT&lt;5:0&gt; are 0 (this indicates that the wiper is at the low end of the resistor array and NOR gate 4011 goes high) and CNTL is high or when all bits are 1 (the wiper at the high end of the resistor array and NAND gate 4012 goes low) and CNTL is low. In either of these cases REVERSE2 goes high. FIG. 41 shows counter 4001 made of six parallel counter bit devices 4 1204 125 with each counter bit device illustrated in FIG. 42; the storage flip-flop of each counter bit is shown in FIG. 43. Except during power up reset RST is low and RST.sub.-- is high, so the transmission gates connecting DATA to the two memory cells 435 14352 of the storage flip-flops are nonconducting to isolate DATA and the upper transmission gates within the memory cells are conducting. When COUNT.sub.-- PULSE is low (and the counter is neither 000000 nor 111111) elk is low into counter 4001 so the lower transmission gate in memory cell 4352 is conducting and the bit at node 4355 is held by the feedback of the inverters; this bit appears at output Q and thus on bus COUNT &lt;5:0&gt;. Clk low also implies that the transmission gate connecting memory cells 4351 and 4352 is nonconducting to isolate the memory cells, that the lower tranmission gate within memory cell 4351 is nonconducting to prevent the inverter feedback, and that the transmission gate connecting memory cell 4351 to input D is conducting so the bit at D controls memory cell 4351. Now FIG. 42 shows that the output Q feeds back through an XOR (made of XNOR gate 4231 plus inverter 4232) to the D input. The other input to the XOR is the carry in node CI which connects to the carry out node CO of the next less significant bit device 4120-4124 in counter 4001, and CI connects to high for the least significant bit device 4120. Thus when CNTL is low (WIPER.sub.-- COUNTER is counting up) and COUNT.sub.-- PULSE makes a low to high transition, the expected addition and carry happens: if CI is low (no carry in), then CO is low (no carry out because inverter 4233 drives NOR gate 4234 low, and Q feeds back to D because the XOR of Q and a low is Q, and the stored bit remains unchanged. Contrarily, if CI is high (carry in a 1), then the XOR of CI and Q complements Q to D, so the stored bit switches (i.e., 1+0 is 1 and 1+1 is 0 plus a carry out 1), and XNOR gate 4236 complements Q because CNTL is low. Thus CO is high if Q is high (i.e., 1+1 generates a carry out 1) because both inputs to NOR gate 4234 are low, and CO is low if Q is low (i.e., 1+0 does not generate a carry out).
Conversely, if CNTL is high (WIPER.sub.-- COUNTER is counting down) then the expected subtraction and borrow occurs: CI high indicates that the next less significant bit needd to borrow, so in addition to the complementing of Q to switch the stored bit, XNOR gate 4236 passes Q and CO goes high if Q is low to indicate to the next more significant bit that a borrow is needed, but CO stays low if Q is high and can supply the borrow needed by next less significant bit.
FIG. 43 also shows that on a reset (RST high and RST.sub.-- low) the 6 bits stored in nonvolatile memory EE and available on bus EE&lt;5:0&gt; (which connects to the DATA inputs of bit devices 4120-4125) are stored in counter 4001 because RST, RST.sub.-- make conducting the transmission gates connecting DATA to the memory cells 4351-4352.
Counter Decoder FIG. 44 schematically show decoder block DECODER64 632 which is a straightforward binary decoder of 6 bits to 64 lines.
Resistor Array FIGS. 45 and 46 schematically show the resistor array block R.sub.-- ARRAY 640.
Input Logic FIGS. 47, 48, and 49 schematically show logic INPUTS 650 with FIG. 47 the overall schematic diagram and digital filters 4701 and 4702 shown in FIG. 48 and rejection blocks 4711 and 4712 shown in FIG. 49. INPUTS operates as follows. First, input nodes UP.sub.-- and DOWN.sub.-- are pulled up by 100 Kohm resistors (see the lefthand portion of FIG. 6), node RST is low and node RST.sub.-- is high except during a power up reset (see FIG. 56), node REVERSE1 is low as seen from FIG. 7, and node DIG.sub.-- IN is pulled up by a 100 Kohm resistor on the input side of TTL-level input buffer INBUFFFL. Now consider a low-going pulse at either input node UP.sub.-- or input node DOWN.sub.--. The pulse will drive NAND gate 4703 high and this will be inverted to drive NAND gate 4705 high and output INPUTS.sub.-- HI low. Similarly, a low pulse at input node DIG.sub.-- IN will direct drive NAND gate 4705 high and output INPUTS.sub.-- HI low. This low at INPUTS.sub.-- HI drives NAND gate 801 in clock CLK 612 high (see FIG. 11) and turns on oscillator OSC. (Presume that IDLE and TIMER.sub.-- NOT.sub.-- RUNNING were high so OSC was not already running.) OSC continues running until INPUTS.sub.-- HI returns high, and this also resets divider CI . . . K.sub.-- DIV6 which has been counting the periods of OSC. If the low going pulse at UP.sub.--, DOWN.sub.--, or DIG.sub.-- IN lasts for at least 64 OSC periods (which is selectable as previously described), then CLK.sub.-- DIV6 outputs a low which drives CLK low and CLK.sub.-- and CLKOUT both high. And if the low pulse persists, then every 64 periods of OSC CLK.sub.-- DIV6 will switch as will CLK and CLK.sub.--.
Reject memory 4712, schematic shown in FIG. 47, resets to high outputs at A.sub.-- OUT.sub.-- and B.sub.-- OUT.sub.--, so consider the case of these outputs high. Inverter 4713 will then feed highs to NOR gates 4706 and 4707 and inverter 4714 will feed a high to NOR gate 4708. Thus the low pulse at either UP.sub.-- or DOWN.sub.-- will, in addition to switching CLK and CLK.sub.-- as described in the preceding paragraph, provide a low input to the IN.sub.-- input node of either digital filter 4701 or 4702, respectively. FIG. 47 schematically shows digital filters 4701 and 4702 which reset to OUT as high. Now the three flip-flops 4871-4873 reset to the Q=0 state, so digital filters 4701 and 4702 each have NAND gate 4875 initially with three 0 inputs and NAND gate 4876 with three 1 inputs; this put the latch formed by NAND gates 4877-4878 into the OUT.sub.-- high state. Now the high at IN.sub.-- propagates through flipflops 4871-4873 in three cycles of CLK/CLK.sub.-- and switches latch 4877-4878 to the OUT.sub.-- low state. Hence, digital filters 4801 and 4802 filter out short low pulses at UP.sub.-- or DOWN.sub.--, and OUT.sub.-- goes low only if the low going pulse at UP.sub.-- or DOWN.sub.-- persists for at least 375 microseconds.
Once a low pulse at UP.sub.-- or DOWN.sub.-- persists low enough to pass digital filter 4701 or 4702, the corresponding low going OUT.sub.-- from this filter along with the still high OUT.sub.-- from the other filter passes reject memory 4711 to have A.sub.-- OUT.sub.-- or B.sub.-- OUT.sub.-- low, respectively, and thus UPF.sub.-- or DOWNF.sub.-- low, respectively, plus TOUCHF high in either case. A low pulse at DIG.sub.-- IN passes NOR gate 4708 to also drive TOUCHF high without any minimum pulse duration required. In the event that a low pulse appears at both UP.sub.-- and DOWN.sub.-- approximately simultaneously, both filter 4701 and 4702 will have OUT.sub.-- going low and reject memory 4711 will only pass the first OUT.sub.-- going low and reject the second as long as the first OUT.sub.-- persists, and once the first returns high then the second low passes through reject memory 4711. If filters 4701 and 4702 both switch OUT.sub.-- low on the same CLK cycle, then reject memory 4711 will not pass either. Hence, this prevents driving counter in both directions at once.
The R.sub.-- and RST.sub.-- inputs to RS flip-flops 4721 and 4722 are both high, so these block digital inputs while pushbuttons are processed, and vice versa.
Up/Down Control FIG. 50 shows up/down controller UD.sub.-- CNTL 652 which includes flip-flop 1501 that stores the up/down control bit: if Q is low, then CNTL is low and WIPER.sub.-- COUNTER counts up, and if Q is high, the CNTL is high and WIPER.sub.-- COUNTER counts down. Note that a reset puts Q low and thus the initial condition after a power up has WIPER.sub.-- COUNTER counting up. When the inputs REVERSE 1, . . . , UPF.sub.-- in the lefthand portion of FIG. 50 provide a signal to clock flip-flop 1501, inverter 1503 feeding Q back to the D input insures that Q switches: from low to high or from high to low, and thereby reverses the count direction of WIPER.sub.-- COUNTER. The inputs REVERSE1, . . . ., UPF.sub.-- provide a clocking signal when:
Timer FIG. 51 timer TIMER 660 as made of multiplexer 1601 which can pass the CLK signal or a high, divider 1602 (FIG. 52) which divides the output of multiplexer by four and sixteen at output nodes 0.1s and Is, respectively, pulse generator 1603 which has the same structure as that of FIG. 8, and logic gates. When any of the inputs START0.sub.-- I.sub.--, START1.sub.--, and START1.sub.-- EE.sub.-- goes low, then NAND gate 1605 goes high to select CLK to pass through multiplexer 1601 to divider. Timer TIMER operates as follows. First, when the inputs START0.sub.-- 1.sub.--, START1.sub.--, and START1.sub.-- EE.sub.-- are all inactive high, inverter 1609 and NAND gate 1610 are both low, so NAND gates 1611 and 1612 are both high and NAND gate 1614 applies a low to the IN of pulse generator 1603. Multiplexer passes the power supply constant high to divider 1602, so the 0.1s and 1s outputs are both low (presuming a reset upon power up) and these lows feed the other inputs of NAND gates 1611-1612. Now when one of the inputs START0.sub.-- 1.sub.--, START1.sub.--, and START1.sub.-- EE.sub.-- goes active low, then multiplexer 1601 switches to pass CLK to divider 1602 and either inverter 1609 or NAND gate 1610 goes high. This high feeds one of NAND gates 1611-1612, but the other inputs are lows from divider 1602. However, as soon as four or sixteen CLK cycles have passed to divider 1602, its 01.s or 1s output goes high and one of NAND gates 1611-1612 goes low to drive NAND gate 1614 high and thus trigger pulse generator to output a high which the next CLK cycle resets to low. However, inverter 1620 inverts this high pulse to drive a low pulse at node DONE.
TTL Input Buffer FIG. 53 shows input buffer INBUFTFL 670 as a buffer with hystersis centered about a TTL level (1.5 volts). The larger total gate width of the n-channel FETs (about seven times the total gate width of the p-channels) in the left inverter leads to the symmetrical switching about 1.5 volts.
Test Mode Buffer FIG. 54 shows test mode buffer IN.sub.-- BUF 672 as a simple enable buffer which will pass signals from IN to OUT when EN is high; otherwise OUT is held low.
Test Mode Detector FIG. 55 shows test mode detector HV 674 as a high voltage detector which switches OUT from low to high when the input IN rises to about 7 volts. Detector HV has diode connected n-channel FET 5501 with a large gate width to length, so once the voltage across the diode reaches the threshold voltage (about 1 volt) there is very small resistance. Similarly, the p-channel FET 5504 also has a large gate width to length ratio and low resistance when turned on, whereas the n-channel FET 5505 has a very small gate width to length ratio to provide a resistive path to ground. Thus when the voltage at IN is two thresholds (about 2 volts) above the power supply, FETs 5501 and 5504 turn on to pull up the input of inverter 5510 and thereby drive OUT high. Inverter 5510 has a low threshold (width n-channel and narrow p-channel) to insure rapid switching of OUT when the voltage at IN reaches two thresholds above the power supply.
The switching of OUT from low to high disables decoder DECODER64 632, puts memory EE 620 into test mode, and enables input buffer IN.sub.-- BUF 672 to pass signals from R.sub.W to the TESTCLK input of clock CLK 612.
Power Up Reset FIG. 56 shows power up reset circuit PU 676 which includes the power up reset pulse generator in the upper half of FIG. 56 and the two-button operation circuit in the lower half. In particular, the 1 Mohm resistor 5605 plus 100 Kohm resistor 5610 and capacitor 5611 insure that when power is first turned on inverter 5620 will have a low input and a high output so that RST goes high, but after capacitor 5611 charges up through resistor 5610, inverter 5620 switches low and thus RST returns low.
Further, when terminal DC is connected to the power supply (see broken line in FIG. 2) to implement one-button operation, then on power up when the reset RST has a high pulse, transmission gate 5630 conducts and the high from terminal DC through node DOWN sets memory cell 5633 to have a high output. Once the reset pulse drops back low the memory cell 5633 is isolated and holds TWO.sub.-- BUTTON low to indicate one-button operation.
Process Implementation Control unit 100 may be fabricated in standard CMOS processing provided with the extra dopings to achieve the diodes of FIG. 37. Variations in the circuitry will permit use of NMOS or PMOS devices alone, and alternatives to the diodes of FIG. 37 may be used. BiCMOS processing may be used.
Packing FIG. 3 shows three views of the package preferably used to house the presently preferred embodiment. Note that this package includes pushbutton 302 on its topside.
The presently preferred embodiment uses a Ryton� tub 310. This provides high-temperature durability. Pushbutton 302 includes a conductive portion on its underside, which contacts a contact wiring grid when the pushbutton is depressed. The pushbutton includes a deformable concave portion at its bottom, which provides a flexible elastic support to define the button's position.
Features Some notable features of the Electronic Digital Rheostat of the presently preferred embodiment include the following.
Control Section Features Following is a brief summary of some of the features of the control organization of the presently preferred embodiment:
Overall Description of Preferred IC Embodiment The preferred embodiments include a digital rheostat or potentiometer which is adjusted to a desired value by a contact closure input. Alternatively, the desired setting can be achieved from a digital source input. When supplied as a 6 pin device, the contact closure is provided on the top of the package. In this configuration, -V is connected to R.sub.L on the bottom side of the package, and R.sub.W, +V, D and R.sub.H are single connections on the bottom side of the package. The 6 pin embodiment is a self contained substitute for rheostat and potentiometer applications. Any time the pushbutton on the top of the package is depressed the resistance setting between pins -V and R.sub.W will increase or decrease provided that a potential of +4.5 V to +8 V exist between -V and +V inputs. The 8 pin packaged version can be used in a similar manner as the 6 pin version with -V connected to R.sub.L ; +V is connected to a positive source greater than + 4.5 volts relative to V, and a contact closure is between the inputs and -V. Under this condition, the wiper pin (R.sub.W) provides a variable resistance relative to -V and is increased or decreased based on a sequence of contact closures between UC, DC or D, and -V.
Operation The main elements of the preferred embodiment are shown on the block diagram of FIG. 1. The block diagram shows that the rheostat or variable resistor setting is determined by the value of a 64 to 1 multiplexer which is controlled by the input interpreter. The input interpreter takes a UC, DC, or D input, and sends control information to the multiplexer. The way the interpreter derives the control information is key to the operation. The dotted lines shown in the block diagram are included in one embodiment device and serve as a typical application example for the use of the DIP and SOIC embodiments. As shown, a pushbutton contact is between UC and -V and pulls the inputs of an "OR" gate to the negative supply. Note that "D" assumes a logic high level when not connected. When the input of the OR gate is first connected low, the interpreter sends one pulse to the multiplexer which will either increment or decrement the rheostat wiper position 1/64 of the total taper. See flow diagram FIGS. 4 and 5. Increment or decrement determination is based on prior activity. A single input from contact closure of a duration of greater than 1 msec is sufficient to cause a wiper position change of 1/64 of total. Subsequent inputs will increment or decrement of 1/64 of total for each additional contact closure. However, if the contact input remains active for greater than 1 second, subsequent increments/ decrements of 1/64 of total occur at intervals of 100 msec for as long as the input is active or until the top or bottom of the rheostat taper is reached. Anytime that input activity stops for a period of time greater than 1 second, the next action taken as a result of subsequent input activity will be reversed; i.e., if it was incrementing, it will decrement, and if decrement was the prior action, the next action taken will be increment. If input activity is maintained for a period of time such that the upper or lower limits of the rheostat are reached, successive action is in the opposite direction. Total time of movement from one end of the taper to the other requires 64 +1 second or 7.4 seconds. The 8 pin version can be configured for two button operation such that the DC input can be used for decrementing and the UC input is then used only for incrementing. Upon power up, the device wilt internally sense the impedance between the DC input and V +. For this reason, the DC input must be connected to +V when not is use. Otherwise, the pushbutton packaged version (FIG. 3) performs as described above with the contact input attached external to the device package. Connection between contacts inputs and -V of less than 10 Kohm is all that is required to be interpreted as activity. Alternatively, the D input accepts a low going signal of 0.8 volts maximum with respect to -V. The input pulse width must exceed 1 μsec to guarantee recognition. Successive input pulses can be any length apart provided that they are not separated by more than 1 second. If the D input is held low for more than 1 second, incrementing/decrementing occurs automatically on 1/64 of total intevals. The flow chart for electronic control is shown in FIG. 4, as the D input acts the same as the UC input. When the 8 pin version is used, the rheostat low end and wiper may be connected to voltages sources other than -V or +V. The voltage applied to any rheostat element must not exceed -V -0.5 volts on the low end or +V +0.5 volts on the high end. If -V is connected to ground, then all other input voltages are referenced to ground.
Nonvolatile Wiper Settings The wiper setting of the DALLASTAT is maintained in the absence of power in the shadow memory. During normal operation the position of wiper is determined by the multiplexer. The shadow memory is periodically updated by the multiplexer during normal operation. The manner in which an update occurs has been optimized for reliability, durability, and performance and is totally transparent to the user. When power is applied to the DALLASTAT, the wiper setting is set at the last value recorded in the shadow memory. On an initial power up for the first time, the wiper position may, therefore, be random. If the DALLASTAT setting is changed after power is applied, the new value will be stored in the shadow memory after a delay of about 2 seconds. The initial storing of a new value after power up always occurs when the first change is made regardless of when this change occurs after power up. After the initial change, subsequent changes in the DALLASTAT setting of less than 12.5% are not copied in the shadow memory. Since the DALLASTAT contains a 64 to 1 multiplexer, a change in the 3 LSB's is not copied into the shadow RAM except for change after power up. Changes greater than 12.5% or changes large enough to affect the 4 LSB or greater are always copied into the shadow memory. As on power up, the copy from the multiplexer to shadow memory allows for a 2 second delay to guarantee that the new setting changes are finalized, and all shadow updates are transparent to the user. On power down (loss of power) the shadow memory is not changed and retains the most recent update resulting from a setting change. This value is used to set the DALLASTAT value on power up. The shadow memory is made with EEPROM type memory cells that will accept at least 80,000 value changes before wear out. If the EEPROM cells ever reach a wearout condition, the DALLASTAT will still continue to operate properly while power is applied, but will return to the last accepted value of the shadow memory on power up.
__________________________________________________________________________Absolute Maximum Ratings__________________________________________________________________________Voltage on any pin relative to -V:                -V-0.5 Volts to -V+8.0 VoltsOperating Temperature Range:                -10Storage Temperature Range            �                -55Soldering Temperature Range                260__________________________________________________________________________Parameter  Symbol Min  Typ                     Max   Units                              Notes__________________________________________________________________________Recommended DC Operating Conditions (-10+Supply Voltage      +V     -V+4.5  -V+8.0                           V-Supply Voltage      -V     +V-8.0  +V-4.5                           VRheostat Inputs      R.sub.H,R.sub.W,R.sub.L             -V-0.5  +V+0.5                           VLogic Input 1      V.sub.IH             +2.4          V  1,2Logic Input 0      V.sub.IL       +8,0  V  1,2DC Electrical Characteristics (-104.5V to 7.0 V)+,- Supply Current      Icc.sub.1   1  2     mA 3Supply Current, idle      Icc.sub.2      100   nA 9Wiper Resistance      R.sub.W     500                     1000  &#937;Wiper Current      I.sub.W        2     mA 5Rheostat Current      I.sub.W, I.sub.L                     2     mA 5AC Electrical Characteristics (-104.5V to 7.0 V)Input Pulse Width      t.sub.pw             1       DC    &#956;S                              1,7.8Contact Pulse Width      t.sub.cpw             1       DC    mS 1,7,8Capacitance      C.sub.in    5  10    pF 6__________________________________________________________________________
6) Capacitance values apply at 25
7) Input pulse width is the minimum time required for an input to cause an increment or decrement. If the UC, DC, or D input is held active for longer than 1 second, subsequent increments or decrements will occur on 100 mS intervals until the inputs UC, DC, and/or D is released to V.sub.IH.
9) Idle state supply current is measured with no pushbutton depressed and with the wiper R.sub.W tied to a CMOS load.
Process Specification __________________________________________________________________________Device ParametersProcess           Nchannel PchannelParameter         related  related__________________________________________________________________________Low Voltage Device Parameters:Well rho, ohm/sq  1300 +/- 150                      340 +/- 50Delta Width from drawn, um             2.7 +/- 0.3                      1.5 +/- 0.3Well rho, Kohm/sq 4.2 +/- 0.5                      No data(w/o field implant)Saturated Vt, Volts             0.80 +/- 0.25                      0.80 +/- 0.25Gate oxide cap, 1e-4 pF/um**2             13.8 to 17.3                      13.8 to 17.3(225 +/- 25 Angstroms)High Voltage Device Parameters:Well rho, ohm/sq  1650 +/- 200                      No dataDelta Width from drawn, um             1.9 +/- 0.3                      No dataWell rho, Kohm/sq 4.9 +/- 1.1                      No data(w/o field implant)Saturated Vt, Volts             1.10 +/- 0.25                      1.10 +/- 0.25Gate oxide cap, 1e-4 pF/um**2             3.29 to 3.63                      3.29 to 3.63(1000 +/- 50 Angstroms)Parameters Common to both Low and High Voltage Devices:Tunnel Gate oxide 30.0 to 40.6                      30.0 to 40.6Capacitance, 1e-4, pF/um**2(100 +/- 15 Angstroms)Poly rho, ohm/sq  30 +/- 6 &amp;lt; 100 (usually &amp;lt; 50)Poly/Field cap, 1e-4 pF/um**2             0.863 to 0.987                      0.863 to 0.987(3750 +/- 250 Angstroms)Active sheet rho, ohm/sq             63 +/- 5 82 +/- 5Tempco, ppm       1700 +/- 50                      1450 +/- 50Active Contact resistance             &amp;lt; 75 ohm/ct                      &amp;lt; 50 ohm/ct(1.2 Poly Contact resistance             &amp;lt; 25 ohm/ct                      Not allowed(1.2 Metal rho, milliohm/sq             &amp;lt; 40 milliohm/sqMetal/Act cap, 1e-4 pF/um**2             0.576 to 0.691                      0.576 to 0.691(5500 +/- 500 Angstroms)Metal/Poly cap, 1e-4 pF/um**2             0.576 to 0.691                      0.576 to 0.691(5500 +/- 500 Angstroms)Metal/Field cap, 1e-4 pF/um**2             0.345 to 0.406                      0.345 to 0.406(9250 +/- 750 Angstroms)__________________________________________________________________________
3.00.mu. LV width
10.00.mu. HV width
4.50.mu. LV width when used as a resistor without field implant
15.00.mu. HV width when used as a resistor without field implant
6.00.mu. LV space when wells are at different potentials
10.00.mu. HV space when wells are at different potentials
3.00.mu. space when wells are at same potential
1.20.mu. width
50.00.mu. maximum width simultaneously in two directions
2.00.mu. minimum transistor width
1.50.mu. minimum source/drain width (from poly to active edge)
3.20.mu. minimum width for combined low voltage N+ source/drain and P+ well/sub strap (from poly edge to active edge; this is allowed only if the N+ and P+ regions are shorted out by metal).
5.00.mu. minimum width for combined high voltage N+ source/drain and P+ well/sub strap (from poly edge to active edge; this is allowed only if the N+ and P +regions are shorted out by metal).
3.20.mu. minimum width for combined low voltage P+ source/drain and N+ well/sub strap (from poly edge to active edge; the is allowed only if the N+ and P+ regions are shorted out by metal).
5.00.infin. minimum width for combined high voltage P+ source/drain and N+ well/sub strap (from poly edge to active edge; this is allowed only if the N+ and P+ regions are shorted out by metal).
2.00.mu. space (same doping type; low voltage active)
10.00.mu. space (same doping type; high voltage active)
20.00.mu. space (same doping type; low voltage active to high voltage active)
1.80.mu. N+ active space to P+ active, both low voltage active
5.00.mu. N+ active space to P+ active, both high voltage active
20.00.mu. N+ active space to P+ active, one low voltage active and one high voltage)
1.80.mu. N+ active space to P+ active if both are at same potential 0 or and both are low voltage active
5.00.mu. N+ active space to P+ active if both are at same potential 0 or and both are high voltage active
20.00.mu. N+ active space to P+ active if both are at same potential and are of different voltage types (low/high)
0.80.mu. LV: P+ active well strap enclosure by Pwell
2.50.mu. HV: P+ active well strap enclosure by Pwell
0.80.mu. LV: P+ active substrate strap space to Nwell
2.50.mu. HV: P+ active substrate strap space to Nwell
3.20.mu. LV: N+ active enclosure by Pwell
10.00.mu. HV: N+ active enclosure by Pwell
3.20.mu. LV: N+ active space to Nwell
10.00.mu. HV: N+ active space to Nwell
3.20.mu. LV: P+ active space to Pwell
10.00.mu. HV: P+ active space to Pwell
3.20.mu. LV: P+ active enclosure by Nwell
10.00.mu. HV: P+ active enclosure by Nwell
1.20.mu. LV: N+ active substrate strap space to Pwell
2.50.mu. HV: N+ active substrate strap space to Pwell
1.20.mu. LV: N+ active well strap enclosure by Nwell
2.50.mu. HV: N+ active well strap enclosure by Nwell
3.00.mu. width
3.00.mu. space
2.50.mu. enclosure of HV N+ active (HV N+ active MUST be enclosed by nfnot)
3.00.mu. enclosure of Nwell resistor (when a Nwell resistor is formed by removing the PF implant)
2.50.mu. enclosure of HV P+ active (HV P+ active MUST be enclosed by pfnot)
2.00.mu. width
2.00.mu. space
1.00.mu. enclosure of transistor (the area defined by the intersection of poly and active: poly AND active)
1.80.mu. space to transistor (poly AND active) of different threshold type IN THE DIRECTION OF ACTIVE
2.70.mu. space to transistor (poly AND active) of different threshold type IN THE DIRECTION OF POLY
2.70.mu. space to unrelated active
1.10.mu. ndepletion enclosure of n+not mask
3.00.mu. n+not enclosure of p+(n+not and p+mash are not coinddent in the base-emitter region of the bipolar structure; the space between them defines the `base` region of the bipolar transistor.)
1.10.mu. pdepletion enclosure of the base region of the transistor
3.00.mu. n+ not separation from p+(n +not and p+masks are not coincident in the base-emitter region of the bipolar structure; the space between them defines the "base" region of the bipolar transistor.)
NB: The n+ not and p+ geometries should be drawn as two `donuts`. The outer edge of both donuts should coincide, and should enclose the active region (in which the n+/pdepletion dime resides). The inner hole of the n+ not donut defines the n+ emitter region. The innner hole of the p+ donut should enclose the inner hole of the n+.sub.-- not donut, to form the base region. The pdepletion mask (which is NOT drawn as a donut) should then enclose the inner hole of the p+ donut.
1.00.mu. enclosure of transistor (the area defined by the intersection of poly AND active. A HV Pch transistor must be enclosed by this mask in order to have a threshold voltage in the ≈1 Volt range. Without this mask, the threshold voltage will be in the ≈2 Volt range.)
1.40.mu. space to transistor (poly AND active) of different threshold type
10.00.mu. enclosure of high voltage active (high voltage active MUST be enclosed by the Thick GOX mask)
10.00.mu. space to low voltage active (low voltage active AND Thick Gox NOT allowed)
3.00.mu. enclosure by well
3.00.mu. space to well
10.00.mu. enclosure of well
1.00.mu. enclosure of poly AND active
2.4.mu..sup.2 minimum intersection with poly AND active
1.80.mu. space to transistor (poly AND active) with different gate oxide thickness
1.20.mu. width (low voltage transistors)
10.00.mu. width (high voltage nch transistors)
5.00.mu. width (high voltage pch transistors)
1.80.mu. space
1.20.mu. extension beyond active for LV active (overlap of field)
1.20.mu. extension beyond nfnot for HV active
1.20.mu. extension beyond pfnot for HV active
0.90.mu. space to unrelated LV active (preferred)
1.20.mu. space to unrelated nfnot for HV active (manditory)
1.20.mu. space to unrelated pfnot for HV active (mahditory)
1.20.mu. space to related HV active (manditory)
3.00.mu. width (rain and max)
0.90.mu. tent beyond laserglass in the direction of poly
3.40.mu. space
8.50.mu. space between blast coordinates
1.70.mu. width
0.80.mu. enclosure of P+ active
0.80.mu. space to N+ active
1.70.mu. enclosure of p-channel transistor (poly AND active) in the direction of active
1.70.mu. space to n-channel tranaistor (poly AND active) in the direction of active
1.50.mu. minimum P+ well/sub strap width defined by N- not mask and active edge
1.50.mu. minimum N+ well/sub strap width defined by N- not mask and active edge
3.00.mu. enclosure of HV Nch transistor (poly AND active) IN THE DIRECTION OF ACTIVE (this defines the HV Nch LDD length)
1.00.mu. enclosure of HV Nch transistor (poly AND active) IN THE DIRECTION OF POLY
1.00.mu. space to LV N+ active
2.00.mu. space to P+ /N+ not masks
1.70.mu. minimum N+ source/drain width defined by HV N+ not mask and active edge
2.00.mu. minimum N+ source/drain width defined by HV N+ not mask and the P+ /N+ not masks
1.70.mu. space to LV n-channel transistor (poly AND active) in the direction of active
3.50.mu. space to HV n-channel transistor (poly AND active) in the direction of active
1.50.mu. minimum P+ web/sub strap width defined by N+ not mask and active edge
1.50.mu. minimum N+ weB/sub strap width defined by N+ not mask and active edge
1.50.mu. minimum P+ well/sub strap width defined by P+ mask and active edge
1.50.mu. minimum N+ well/sub strap width defined by P+ mask and active edge
1.20.mu. width (rain and max, except for split contact)
1.00.mu. enclosure by active
1.20.mu. space to LV poly for LV gates
1.20.mu. space to HV N+ not for HV gates
1.20.mu. P+ contact enclosure by P+ mask
1.20.mu. P+ contact enclosure by N+ not mask
1.20.mu. N+ contact space to P+ mask
1.20.mu. N+ contact space to N+ not mask
1.20.mu. split contact width (rain and max)
4.00.mu. split contact length (rain and max)
2.00.mu. split contact length on either side of the P+ /N+ not masks
0.70.mu. enclosure by poly
1.00.mu. space to active
0.70.mu. space to P+ /N+ not masks
25.00.mu. maximum width simultaneously in two directions
0.70.mu. enclosure of contact
0.00.mu. bond pad width
0.00.mu. bond pad space
40.00.mu. bond pad space to active
40.00.mu. bond pad space to poly
40.00.mu. bond pad space to unrelated metal
5.00.mu. bond pad enclosure by pwell, nf, and pfnot for laser fusable circuits (laser fusable circuits on an n-type substrate MUST have all bond pad metal enclosed by pwell, nf, and pfnot)
5.00.mu. bond pad enclosure by nwell, nfnot, and pf for laser fusable circuits (laser fusable circuits on a p-type substrate MUST have all bond pad metal enclosed by nwell, nfnot, and pf)
3.00.mu. bond pad enclosure by poly for laser fusable circuits (laser fusable circuits MUST have all bond pad metal enclosed by poly)
6.00.mu. width
3.50.mu. space
3.00.mu. enclosure of poly
9.00.mu. length in the direction of poly
4.50.mu. enclosure of blast coordinate in the direction of poly
2.40.mu. space to well (intersection of well and laser opening NOT ALLOWED)
2.20.mu. space to active (intersection of active and laser opening NOT ALLOWED)
2.00.mu. space to unrelated poly
2.40.mu. space to metal (intersection of metal and laser opening NOT ALLOWED, except metal bond pad)
5.00.mu. enclosure by metal bond pad
10.00.mu. width
10.00.mu. space
Integrated Circuit Including Multilinear Resistor One contemplated class of alternative embodiments uses a resistor string which is not strictly linear. Such an integrated circuit resistor string is not included in the presently preferred embodiment described above, but has been implemented as a simple programmable resistor integrated circuit.
BACKGROUND AND SUMMARY OF THE INVENTION The present invention relates to electronic devices, and particularly semiconductor potentiometers and systems incorporating such devices and methods of use.
Digital Potentiometers Analog potentiometers have long been used to provide variable resistances in applications such as audio volume control and speaker balancing, light dimmer control, and CRT brightness control. Such potentiometers may take the form of a movable wiper which can traverse a wire wound resistor and short out a variable portion of the resistor. However, such mechanical devices are bulky and awkward to combine with integrated circuits on circuit boards.
One-Touch Control Architecture According to the present invention, there is provided a control input, for effectuating an analog variation, which provides both increment and decrement operations from a single input (e.g., from a single button or a single touch contact plate). A certain pattern of input actuations will cause the direction of change to reverse. For example, when this control input is used as a volume control, a continuous input on the actuator, or a very rapid series of touches on the actuator, can cause the volume to increase; but a touch on the actuator, followed by a certain minimum duration, without actuation (for example, one-half second), followed by a continuous actuation or series of actuations, can cause the volume to decrease.
Compact Control Module The present application discloses a new control module architecture. A drop-in electronic replacement component includes both a digitally-controlled potentiometer (or variable resistance to ground. This component includes an integrated circuit variable resistor), and also includes the control logic which will increment or decrement the value of the variable resistance in accordance with touches received on a pushbutton (or other actuator). The control logic is preferably integrated on the same integrated circuit as the digital resistor.
Systems Incorporating the Control Architecture This control relationship can be advantageously applied to a wide variety of systems contexts, such as volume, tone, fade, and balance controls in audio systems; contrast and brightness controls in video display terminals; hue and tint controls in television receivers, and many others. This control relationship can be particularly useful with remote controls and automotive accessory controls, where space is at a premium and other demands will compete for operator attention.
Trimming for Precision Applications In the presently preferred embodiment, the transmission gate which selects the tap point in the resistor string will itself have a significant series resistance. Thus, while the incremental resistance is constant for each increment, the offset resistance means that the total resistance will not be exactly proportional to the tap setting. This is normally not a problem; but for some applications, stricter full-scale linearity may be desirable. Thus, in an alternative embodiment, trimming resistances may be added to equalize the offset resistance value. Alternatively, a user can use two commonly-controlled digital potentiometers with differential sensing circuits.
Conventional Shadow RAMS A technique which has long been familiar in the memory art is the use of shadow RAM. This is a technique where voaltile memory is used for the primary memory, and a nonvolatile memory is used to backup the volatile memory. In some versions of this technique, data will be rapidly copied over from volatile to nonvolatile memory when a power failure occurs. (Some local energy source, such as a battery or a large capacitor, can be used to ensure that sufficient energy for this copying process will be available at such times.) On power restoration, the data can be copied from the nonvolatile RAM back into the volatile RAM.
Control Memory The present application discloses a control unit which includes a nonvolatile shadow RAM to locally store the current value of the control parameter when power goes down. To avoid unnecessary writes to the shadow RAM, a write is performed only when the control parameter is changed for the first time after power comes on or, thereafter, only if one or more of the three most significant control bits (MSB) are changed.
An advantage of the disclosed innovations is the combination of nonvolatility and long lifetime in a low-cost electronic control. EEPROM memories typically have a modest lifetime limit (e.g. 10.sup.4 to 10.sup.5) on the number of write cycles which can be performed. This would be an unacceptable limit on the total number of control setting changes which could be made during the lifetime of a control.
Use Of Power-On Flip-flop The presently preferred chip embodiment includes a flip-flop which comes up in a particular logic state at power-on. When the flip-flop is in this stage, any change will be stored. However, since even a large change will be received as a series of increments, the chip waits for a quiet period of 2 seconds before transferring the updated value into nonvolatile memory. As soon as such a transfer to nonvolatile memory is made, the state of the flip-flop is changed.
EEPROM Background An EEPROM is a type of semiconductor memory which has been known for about two decades. The central part of a classic EEPROM cell is typically a floating-gate transistor, i.e. a MOS transistor which has two gates stacked on top of each other, so that the two gates are capacitively coupled to each other and to the channel. The lower gate is called a "floating" gate, because it is electrically isolated. By injecting charges into the floating gate, the effective threshold voltage of the MOS transistor (as seen from the upper gate) can be changed.
Hot Carrier Injection To get charge into or out of the floating gate, two methods can be used. The most common method is to generate "hot" carriers, that is electrons or holes which have more energy than the minimum for a carrier. A sufficiently energetic hot carrier will pass through a thin dielectric layer. Hot carriers can be generated by flowing a current across a strong electric field. The drain profiles for the device can be shaped to produce such strong electric fields, as is well known to those skilled in the art of the semiconductor device fabrication. Thus, this version of EEPROM has a write mechanism which is closely analogous to that of a conventional FAMOS EEPROM. However, the EEPROM differs in its erase mechanism: the voltage on the floating gate of this type of EEPROM cell can not only be shifted to be more negative (by injecting electrons into it); it can also be shifted to be more positive (by injecting holes into it). This requires not only strong capacitive coupling between the floating gate and the control gate (so that the needed voltages can be developed between the control gate and the substrate), but also requires the ability to withstand the large voltage swings needed to provide a significant hole injection current.
Tunnelling A slightly different EEPROM device structure uses tunneling rather than hot carrier injection. Tunnelling is a well known quantum-mechanical effect where a particle can travel through a potential barrier, with a probability which not only depends on the potential across the barrier, but also decreases exponentially with the thickness of the barrier. Thus, for tunnelling-mode injection, the thickness of the dielectric barrier is critical. Such dielectric barriers are typically made thinner than a normal gate oxide, to enhance the tunnelling current. Tunnelling typically produces slower carrier injection to the floating gate, and may require higher applied voltages, but has the advantage that it is not necessary to provide large currents.
Problems These EEPROM technologies have shared two common difficulties: the write and erase times tend to be slow, and the cells are likely to be worn out after only a relatively small number of write or erase cycles. Recent papers in the literature typically boast of 100,000 cycles or 1,000,000 cycles of endurance; this is an advance on the 10,000 read-write cycle lifetime which used by characteristic of EEPROM cells, but also falls very far short of the durability which would be expected of any modern SRAM or DRAM cell. A further, and more minor, disadvantage of EEPROM cells is their relatively large area.
Redundancy EEPROMs, like other commodity memories, have increasingly been manufactured with redundancy. Various designs have used row redundancy, column redundancy, or both. In addition, there has even been some study given to the idea of in-service replacement of worn out EEPROM cells. For example, U.S. Pat. No. 4,733,394 to Giebel discusses the use of a microprocessor-controlled system, which would periodically survey the state of cells in an EEPROM memory, and code out the defective cells with redundant cells. However, the present invention, by providing automatic rotation or replacement of EEPROM cells, provides a cheaper and simpler local solution which does not require high level software supervision.
EEPROM Array Architecture The present invention provides an architecture which facilitates use of EEPROM cells for many applications where they have not hitherto been practical. According to the present invention, EEPROM cell arrays are provided with more than 100% redundancy. In service, a cell which has begun to wear out is replaced with another cell. This is particularly advantageous for applications where only a relatively small number of bits of memory is needed. In many control applications, the availability of even a few dozen or few hundred bits of memory can be very advantageous. For example, even a very small commercial EEPROM memory will typically contain 16K bits or more. This is configured with 4 to 1 redundancy, as in the presently preferred embodiment, this memory space can be used as a 4K memory with a much longer lifetime. Naturally, this use of memory cells means that the cost per bit is higher, but for many applications the lifetime limitations of conventional EEPROM technology are simply unacceptable.
Partial Summary of Disclosed Innovations Among the inventions disclosed in the present application is: An electronic subsystem, comprising: a voltage input terminal, for receiving a system power supply, and a voltage output terminal, connected to provide a control voltage as output; an integrated circuit potentiometer, comprising a first terminal thereof connected to ground, a second terminal thereof connected to said voltage input terminal, a resistor ladder connected between said first and second terminals, and a wiper terminal connected to said voltage output terminal, and connected to a selectable intermediate point of said resistor ladder; exactly one externally-accessible input receptor, dimensioned to be actuated by contact with a user's fingertip; and control logic, integrated with said resistor string, configured and connected to selectably increment and decrement the position of said intermediate point on said resistor string in accordance with actuations of said input receptor.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5218225 *Mar 30, 1990Jun 8, 1993Dallas Semiconductor Corp.Thin-film resistor layoutUS5243535 *Mar 30, 1990Sep 7, 1993Dallas Semiconductor Corp.Digital potentiometer with stackable configurationUS5253196 *Jan 9, 1991Oct 12, 1993The United States Of America As Represented By The Secretary Of The NavyMOS analog memory with injection capacitorsUS5297056 *Mar 30, 1990Mar 22, 1994Dallas Semiconductor Corp.Directly-writable digital potentiometerUS5331590 *Oct 15, 1991Jul 19, 1994Lattice Semiconductor CorporationSingle poly EE cell with separate read/write paths and reduced product term coupling* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5841701 *Jan 21, 1997Nov 24, 1998Advanced Micro Devices, Inc.Method of charging and discharging floating gage transistors to reduce leakage currentUS6208559Nov 15, 1999Mar 27, 2001Lattice Semiconductor CorporationMethod of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturbUS6737912Mar 7, 2003May 18, 2004Kabushiki Kaisha ToshibaResistance division circuit and semiconductor deviceUS8327068 *Mar 1, 2006Dec 4, 2012Panasonic CorporationMemory module, memory controller, nonvolatile storage, nonvolatile storage system, and memory read/write methodUS20080307152 *Mar 1, 2006Dec 11, 2008Matsushita Electric Industrial Co., Ltd.Memory Module, Memory Controller, Nonvolatile Storage, Nonvolatile Storage System, and Memory Read/Write Method* Cited by examinerClassifications U.S. Classification365/185.28, 365/185.23, 257/E27.26, 257/321International ClassificationG05B24/02, H04R25/00, H03M1/66, H03M1/76, H01L27/06Cooperative ClassificationH03M1/765, H04R25/00, H03M1/007, H03M1/662, H01L27/0688, H03M1/682, H03M1/804, G05B24/02European ClassificationH03M1/00R4, H03M1/66M, G05B24/02, H03M1/76S, H01L27/06ELegal EventsDateCodeEventDescriptionJul 17, 2008ASAssignmentOwner name: MAXIM INTEGRATED PRODUCTS, INC., CALIFORNIAFree format text: MERGER;ASSIGNOR:DALLAS SEMICONDUCTOR CORPORATION;REEL/FRAME:021253/0637Effective date: 20080610Nov 2, 2007FPAYFee paymentYear of fee payment: 12Oct 15, 2003FPAYFee paymentYear of fee payment: 8Nov 15, 1999FPAYFee paymentYear of fee payment: 4Apr 15, 1997CCCertificate of correctionRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google