Source: https://patents.google.com/patent/JP4193805B2/en
Timestamp: 2020-01-22 11:40:43
Document Index: 308519011

Matched Legal Cases: ['art 10', 'art 2', 'art 2', 'art 2', 'art 2', 'art 10']

JP4193805B2 - Light emitting device and image forming apparatus - Google Patents
JP4193805B2
JP4193805B2 JP2005050324A JP2005050324A JP4193805B2 JP 4193805 B2 JP4193805 B2 JP 4193805B2 JP 2005050324 A JP2005050324 A JP 2005050324A JP 2005050324 A JP2005050324 A JP 2005050324A JP 4193805 B2 JP4193805 B2 JP 4193805B2
JP2005050324A
JP2006065280A (en
2004-07-27 Priority to JP2004218272 priority Critical
2005-02-25 Application filed by セイコーエプソン株式会社 filed Critical セイコーエプソン株式会社
2005-02-25 Priority to JP2005050324A priority patent/JP4193805B2/en
2006-03-09 Publication of JP2006065280A publication Critical patent/JP2006065280A/en
2008-12-10 Publication of JP4193805B2 publication Critical patent/JP4193805B2/en
The present invention relates to a light emitting device and an image forming apparatus using a light emitting element that emits light having a magnitude corresponding to the amount of current flowing from an anode to a cathode, such as an organic light emitting diode element.
In recent years, organic light emitting diodes (Organic Light Emitting), called organic electroluminescent elements and light emitting polymer elements, are the next generation of light emitting devices that can replace liquid crystal elements.
Diodes (hereinafter referred to as “OLED elements” where appropriate) are drawing attention. This OLED
An image forming apparatus using a line head provided with a large number of elements per line as an exposure means has been developed. In such a line head, a plurality of pixel circuits including an OLED element and a transistor for driving the OLED element are arranged. For example, Patent Document 1 discloses a one-line OLED.
A line head composed of elements is disclosed.
JP-A-4-363264
By the way, the resolution of the printer depends on the pitch of the pixel circuit, and the brightness of the line head is OL.
Depends on the area of the ED element. For this reason, the optimal arrangement of the elements constituting the pixel circuit is an important problem. Furthermore, the power source impedance is preferably low.
The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a light emitting device capable of narrowing the pitch of pixel circuits and an image forming apparatus using the light emitting device.
In order to solve the above-described problem, a light-emitting device according to the present invention includes a plurality of pixel circuits arranged in one direction, and each of the plurality of pixel circuits has a size corresponding to the amount of drive current. A light emitting element that emits the light, a driving transistor that supplies the driving current to the first electrode, a holding transistor that supplies a data signal supplied via the data line to the driving transistor, and the driving transistor; The holding transistor, the light emitting element, and the driving transistor are arranged in a direction crossing an arrangement direction of the plurality of pixel circuits, and the holding transistor, the driving transistor, The light emitting element is arranged between the two.
According to the present invention, since the holding transistor, the light emitting element, and the driving transistor are arranged in this order in the pixel circuit, the pitch between the pixel circuits can be reduced and the resolution can be improved.
In the light emitting device described above, a first power supply voltage is supplied to the drive transistor via a first power supply wiring, and the light emitting element includes a first electrode connected to the drive transistor and a second power supply voltage. Has a second electrode supplied via a second power supply wiring, and the first power supply wiring and the second power supply wiring are outside the region where the plurality of pixel circuits are formed, It is preferable to dispose on the transistor side. According to this layout, since the first power supply wiring and the second power supply wiring are arranged close to the drive transistor, it is possible to eliminate unnecessary wiring related to power supply. As a result, the pixel circuit can be configured with a small area.
Here, the light emitting elements are preferably arranged in a staggered manner in adjacent pixel circuits. In order to increase the light emission luminance of the light emitting element, it is necessary to increase the area. By arranging in a staggered manner, the area of the light-emitting elements can be increased, and light-emitting elements that emit light with high luminance can be formed.
Furthermore, it is preferable that a length of the light emitting element in the arrangement direction of the pixel circuits is longer than a pitch between the plurality of pixel circuits. In this case, since the light emitting elements having a large area are arranged in a staggered manner, the pitch between the pixel circuits can be narrowed and the resolution of the light emitting device can be improved while increasing the light emission luminance.
In the above light-emitting device, the driving transistor and the light-emitting element have a stacked structure including a plurality of layers, and the plurality of layers include a first layer wiring, a second layer wiring, and the second layer. A third layer wiring constituting the electrode, a first interlayer insulating layer provided between the first layer wiring and the second layer wiring, and between the second layer wiring and the third layer wiring. A second interlayer insulating layer provided, wherein the first power supply wiring is formed using the first layer wiring and the second layer wiring, and the second power supply wiring is the second layer wiring. Further, it is preferable to form the third layer wiring. In this case, since the first power supply wiring and the second power supply wiring have a two-layer structure, the power supply impedance can be reduced. Furthermore, since the second layer wiring is shared by the first power supply wiring and the second power supply wiring, the chip area can be reduced. The first power supply wiring and the second power supply wiring
In the portion where the power supply wiring intersects, the second layer power supply wiring may be deleted from at least one of the power supply wirings.
In the above light-emitting device, the driving transistor and the light-emitting element have a stacked structure including a plurality of layers, and the plurality of layers include a first layer wiring, a second layer wiring, and the second layer. A third layer wiring constituting the electrode, a fourth layer wiring constituting the first electrode, a first interlayer insulating layer provided between the first layer wiring and the second layer wiring, And a second interlayer insulating layer provided between the second layer wiring and the third layer wiring, and the first power supply wiring is formed using the first layer wiring and the second layer wiring. The second power wiring is preferably formed using the second layer wiring, the third layer wiring, and the fourth layer wiring. In this case, since the first electrode and the second power supply wiring have a two-layer structure, the power supply impedance can be reduced. Furthermore, since the second layer wiring is shared by the first electrode and the second power supply wiring, it is not necessary to provide a dedicated layer in order to make the power supply wiring a laminated structure, and a simple structure can be achieved.
In the light emitting device described above, it is preferable that the first electrode is an anode of the light emitting element and the second electrode is a cathode of the light emitting element. In this case, for example, the holding transistor is composed of a p-channel TFT, the driving transistor is composed of an n-channel TFT, the high potential side power supply is supplied to the source of the driving transistor, and the drain is connected to the anode of the light emitting element. It is preferable that the low potential side power supply is supplied to the cathode.
The light-emitting device described above is provided in parallel with the arrangement direction of the plurality of pixel circuits, and includes a plurality of data lines connected to each of the plurality of pixel circuits, a first end surface, and a second end surface. A substrate on which the plurality of data lines, the holding transistor, the light emitting element, the driving transistor, the first power supply wiring, and the second power supply wiring are sequentially formed, and the plurality of data lines, It is preferable that the holding transistor, the light emitting element, the driving transistor, the second power supply wiring, and a sealing member connected to the substrate so as to cover the first power supply wiring are provided.
In general, the performance of a light-emitting element deteriorates when it comes into contact with oxygen. For this reason, the light-emitting device employs a sealing structure for the purpose of blocking outside air and protecting the internal circuit. For sealing structure, methods such as can sealing, thin film sealing, and substrate bonding sealing are known, but in any case, external gas penetrates into the sealing in the actual sealing structure. To do. For this reason, the light emitting element is preferably formed near the center of the substrate. According to the present invention, the substrate includes a plurality of data lines →
Since the holding transistor → the light emitting element → the driving transistor → the power supply line are formed in this order, the light emitting element can be arranged near the center of the substrate. Thereby, the reliability of the light emitting device can be improved.
The light-emitting device described above is provided in parallel with the arrangement direction of the plurality of pixel circuits, and includes a plurality of data lines connected to each of the plurality of pixel circuits, a first end surface, and a second end surface. A substrate on which the plurality of data lines, the holding transistor, the light emitting element, the driving transistor, the second power supply wiring, and the first power supply wiring are sequentially formed, and the plurality of data lines; A sealing member connected to the substrate so as to cover the holding transistor, the light emitting element, the driving transistor, the first power supply wiring, and the second power supply wiring, and the first electrode of the light emitting element It is an anode, and the second electrode is preferably a cathode of the light emitting element. Since the cathode easily reacts with oxygen, it is preferable that the cathode is arranged in the central portion of the substrate as much as possible. According to the present invention, the second power supply line connected to the cathode is arranged closer to the center and away from the second end face than the first power supply line, so that the cathode can be arranged further in the center. Thereby, the reliability of the light emitting device can be improved.
Next, in the image forming apparatus according to the present invention, the light emitting device described above includes a photoconductor on which an image is formed by irradiation of light and a head unit that forms the image by irradiating the photoconductor with light. Is preferably used for the head portion. As described above, the light emitting device has a narrow pitch of pixel circuits and emits high-luminance light, so that a high resolution image can be formed on the photoconductor.
FIG. 1 is a block diagram showing a configuration of a light emitting device according to an embodiment of the present invention. This light emitting device is used as a head unit 10 of a printer as an image forming apparatus. The head unit 10 is a line type optical head, and includes an input protection circuit 20, a buffer unit 30, and 128 data lines L.
0 to L127, output protection circuit 40, shift register 50, and pixel blocks B1 to B40
Is provided. In addition to the data signals D0 to D127, various control signals and power signals are supplied to the head unit 10, and the input protection circuit 20 includes a plurality of input ESD protection units Ua, And a power protection unit Ua ′ provided between a plurality of power supplies for supplying power signals. As the control signal, the shift pulse signal SP
, Clock signal CLK, and enable signal EN. The buffer unit 30 includes a plurality of inverters 31 and functions as a driver that supplies the data signals D0 to D127 to the data lines L0 to L127. .
The shift pulse signal SP is a pulse that becomes active at the start of the main scanning period, and the enable signal EN is a signal that allows the selection signals SEL1 to SEL40 output from the shift register 50 to be output. The shift register 50 is supplied with power supply voltage signals VHH and VLL.
The power supply voltage signal VHH is supplied via the wiring 50b, and the power supply voltage signal VLL is supplied via the wiring 50a. The shift register 50 shifts the shift pulse signal SP according to the clock signal CLK in a state where the enable signal EN is active, and selects the selection signals SEL1 to SEL4.
0 is output sequentially. Each of the selection signals SEL1 to SEL40 becomes active during a period of 1/40 of the main scanning period. The clock signal CLK is supplied to the shift register 50 via the wiring 50c.
The first to forty pixel blocks B1 to B40 are exclusively and sequentially selected by the selection signals SEL1 to SEL40. In this way, the main scanning period is divided into a plurality of selection periods (writing periods),
Since time-division driving is performed, the number of data lines L0 to L127 can be reduced. 1st to 4th
Each of the pixel blocks B1 to B40 includes 128 pixel circuits P corresponding to the data lines L0 to L127. These pixel circuits P are supplied with a first power supply voltage signal VDDEL and a second power supply voltage signal VSSEL. Then, the data signals D0 to D127 supplied via the data lines L0 to L127 in each selection period are taken into the pixel circuit P. The data signals D0 to D127 in this example are binary signals for instructing to turn on / off the OLED element.
FIG. 2 shows a circuit diagram of the input ESD protection unit Ua used in the input protection circuit 20, and FIG. 3 shows a circuit diagram of the output ESD protection unit Ub used in the output protection unit 40. Input ESD
In the protection unit Ua and the output ESD protection unit Ub, diodes d1 and d2 are connected in series between the high potential side power source and the low potential side power source, and the input ESD protection unit Ua.
A resistor R is provided. Note that the inter-power supply protection unit Ua ′ is configured by connecting a diode in the reverse direction between the power supply wires. The reason why the protective circuits for countermeasures against electrostatic discharge are provided at both the input and output ends of the data lines L0 to L127 is that the head unit 10 in this example corresponds to the A4 vertical print size, and therefore the data lines L0 to L127. This is because the length of is about 215 mm. For the same reason, a protective circuit for countermeasures against electrostatic discharge is provided in the power supply. further,
The reason why the buffer unit 30 is provided is that the input ESD protection unit Ua includes the resistor R. Therefore, if the buffer unit 30 is not provided and the external ESD driving unit Ua is driven from the outside, the signal delay time increases.
FIG. 4 shows a circuit diagram of the pixel circuit P. The pixel circuit P includes a holding transistor 61, a driving transistor 62, and an OLED element 64. One of the selection signals SEL1 to SEL40 is supplied from the shift register 50 to the gate of the holding transistor 61, the source thereof is connected to one of the data lines L0 to L127, and one of the data signals D0 to D127 is supplied. The drain of the holding transistor 61 and the gate of the driving transistor 62 are connected by a connection wiring 63. As will be described later, the connection wiring 63 is accompanied by a stray capacitance, and this capacitance acts as a storage capacitor C. In the storage capacitor C, a binary voltage is written in the selection period, and the written voltage is held until the next selection period. Therefore, in the period in which the holding transistors are selected by the selection signals SEL1 to SEL40, the data signals D0 to D
The OLED element 64 emits light only during a period in which 127 is a signal for instructing lighting of the OLED element 64.
The first power supply voltage signal VDDEL is supplied to the drain of the driving transistor 62, and the anode of the OLED element 64 is connected to the source thereof. The drive transistor 62 supplies a drive current corresponding to the voltage written in the storage capacitor C to the OLED element 64. The second power supply voltage signal VSSEL is supplied to the cathode of the OLED element 64. The OLED element 64 emits light of an amount corresponding to the current value of the drive current. In the pixel circuit P of the present embodiment, the holding transistor 61 is configured by a P-channel TFT (thin film transistor), and the driving transistor 62 is configured by an N-channel TFT. Since the P-channel transistor is excellent in current sink, the rising waveform of the drive current becomes steep and the falling waveform becomes gentle as shown in FIG. As a result, OLE
Although the gradation characteristics of the D element 64 at the time of low gradation are deteriorated, the peak luminance can be increased. Since the sensitivity of the photoreceptor is generally low, it is important to increase the peak luminance. On the other hand, OLED
If the amount of light emitted is close to the threshold current of the element 64, the sensitivity of the photosensitive member is extremely low, and there is no adverse effect on the image quality. Accordingly, it is desirable to prioritize peak luminance and to configure the holding transistor 61 with a P channel and the driving transistor 62 with an N channel.
FIG. 6 shows a wiring structure of the pixel block and the data line. As shown in FIG.
L127 is arranged in parallel along the X direction (the arrangement direction of the pixel circuits P). A plurality of pixel circuits P are arranged in the X direction. The pixel circuit P includes a holding transistor 61, a driving transistor 62, a connection wiring 63, and an OLED element 64. These are arranged along the Y direction (direction intersecting with the arrangement direction of the pixel circuits P). The gates of the holding transistors 61 are commonly connected by a wiring La and are connected to the shift register 50. The data lines L0 to L127 are formed using source lines. A connection wiring 60 using a gate line is used to connect each holding transistor 61 to the data lines L0 to L127. An OLED element 64 is provided between the holding transistor 61 and the driving transistor 62. The OLED elements 64 are arranged in a staggered manner.
In the pixel circuit P, the holding transistor 61, the driving transistor 62, and the OLED
The element 64 occupies a large area. Therefore, the pitch W of the pixel circuits P can be narrowed by laying out these components along the Y direction. As a result, the resolution can be increased.
In general, since the sensitivity of the photosensitive member is low, it is important to increase the light emission luminance in the head unit 10. The light emission luminance of the OLED element 64 is proportional to its area. However, OLED element 6
When the area of 4 is increased, the pitch W of the pixel circuits P becomes longer. That is, the light emission luminance and the resolution are in a trade-off relationship. In this example, since the OLED elements 64 are arranged in a staggered manner, the length Q of the OLED elements can be made longer than the pitch W. As a result, high brightness and O
The LED element 64 can emit light, and the pitch W can be narrowed to improve the resolution.
Further, the first power supply line Ld and the second power supply line Ls are laid out in the vicinity of the drive transistor 62 of each pixel circuit P. The source of the drive transistor 62 is connected to the first power supply line L
Since the first power supply voltage signal VDDEL is supplied via d, by bringing both close together,
Useless wiring can be eliminated. On the other hand, the second power supply voltage signal VSSEL supplied via the second power supply line Ls is supplied to the cathode 645 (see FIG. 7) of the OLED element 64.
FIG. 7 is a cross-sectional view taken along the line Z1-Z1 ′ shown in FIG. The drive transistor 62 is composed of SiO.
2 is provided on the surface of the substrate 1 through a base protective layer 11 mainly composed of 2 . Base protective layer 11
A silicon layer 621 is formed on the upper layer. For this reason, the drive transistor 62 is an N-channel transistor. The gate insulating layer 12 is provided on the base protective layer 11 so as to cover the silicon layer 621. A gate electrode 623 is provided on a portion of the upper surface of the gate insulating layer 12 facing the silicon layer 621. The silicon layer 62 is interposed through the gate electrode 623.
1 is doped with a group V element to form a drain region 621a and a source region 621c. Here, a region that is not doped with a group V element is a channel region 621b. The first interlayer insulating layer 13 is formed on the gate insulating layer 12 so as to cover the gate electrode 623. Further, the drain electrode 622 is connected to the drain region 621a through a contact hole that opens through the gate insulating layer 12 and the first interlayer insulating layer 13. On the other hand, the source electrode 624 is provided at a position facing the drain electrode 622 with the gate electrode 623 interposed therebetween, and is connected to the source region 621c through a contact hole opened through the gate insulating layer 12 and the first interlayer insulating layer 13. . The second interlayer insulating layer 14 is provided on the first interlayer insulating layer 13 so as to cover the drain electrode 622 and the source electrode 624.
Similarly, the holding transistor 61 includes the silicon layer 611, the gate insulating layer 12, the gate electrode 613, the first interlayer insulating layer 13, the first drain / source electrode 612, the second
Drain / source electrode 614. However, the silicon layer 611 is doped with a group III element through the gate electrode 613 to form a first drain / source 611a and a second drain / source region 611c. Here, a region that is not doped with a group III element is a channel region 611b. The holding transistor 61 is a P-channel transistor.
Further, the gate electrode 623 of the driving transistor 62 is connected to the first drain / source electrode 612 of the holding transistor 61 through the connection wiring 63. Connection wiring 6 in this example
3 includes a first wiring 631 and a second wiring 632 (see FIG. 6). The first wiring 631 is a wiring formed in the same layer as the first drain / source electrode 612 and the second drain / source electrode 614 of the holding transistor 61 and the drain electrode 622 and the source electrode 624 of the driving transistor 62. The second wiring 632 is formed using a wiring formed using the same layer as the gate electrodes 623 and 613.
The OLED element 64 includes an anode 641, a hole transport layer 642 capable of transporting holes, a light-emitting layer 643 containing an organic EL material having light-emitting ability, and an electron transport layer 644 provided on the upper surface of the light-emitting layer 643. And a cathode 645 provided on the upper surface of the electron transport layer 644. Anode 641
Is connected to the source electrode 624 of the driving transistor 62 through the wiring 625a and the wiring 625b. Note that the wiring 625b may be extended below the anode 641, and the anode 641 and the wiring 625b may be connected to each other through a contact hole so that the anode has a two-layer structure. Furthermore, the wiring 6
25a is extended below the anode 641, and the wiring 625a is connected to the wiring 62 through the contact hole.
The anode may have a three-layer structure connected to 5b. In these cases, the impedance of the anode can be lowered.
A partition 15 made of a synthetic resin or the like is provided between a portion of the surface of the first interlayer insulating layer 13 other than the portion where the OLED element 64 is provided and the cathode 645. The partition 15 is formed so as to separate the OLED elements 64 provided for each drive transistor 62. The anode 641 has a function of supplying holes to the light emitting layer 60, and includes ITO (indium tin oxide), indium oxide / zinc oxide based amorphous transparent conductive film (Indium Zin
c Oxide: A transparent conductive material such as IZO (registered trademark) is used. The anode 641 includes alloys of the above-described materials and laminated ones. The cathode 645 is composed of a low work function metal element (for example, alkali metal, alkaline earth metal, magnesium, rare earth element (excluding Pm), aluminum) in order to increase electron injection efficiency. The cathode 645 is preferably a light-reflective or opaque conductive material. In this example, the light from the light emitting layer 643 is used as the anode 641.
Although it is configured to be extracted from the side (bottom emission type), it may be configured to be extracted from the cathode 645 side (top emission type).
Here, the cathode 645 is formed not to cover the entire second insulating layer 14 but to cover a part thereof. Specifically, the cathode 645 is formed in the area of the arrow A shown in FIGS. 6 and 7, and is not formed in the areas of the data lines L0 to L127 and the holding transistor 61. Thus, the reason why the cathode 645 does not overlap the data lines L0 to L127 and the holding transistor 61 is to reduce the stray capacitance. The data lines L0 to L127 are formed in the same manufacturing process as the first drain / source electrode 612 and the second drain / source electrode 614 of the holding transistor 61 and the drain electrode 622 and the source electrode 624 of the driving transistor 62. Accordingly, if the cathode 645 covers the entire surface of the second insulating layer 14, stray capacitance is generated between the cathode 645 and the data lines L0 to L127.
Since the light emitting device of this embodiment is used as the head unit 10 of the printer, the data line L0 is used.
The length of ~ L127 is long, and the accompanying stray capacitance is large. Due to the stray capacitance, the load viewed from the buffer unit 30 is increased. Therefore, the cathode 645 is not formed in the area of the data lines L0 to L127. As a result, the data signals D0 to D127 can be reliably written during the limited selection period, and further, the data signals D0 to D12 can be written.
7 delay time is greatly reduced.
On the other hand, since the cathode 645 faces a part of the connection wiring 63, a stray capacitance is generated between them. A storage capacitor C is formed by this stray capacitance. During the selection period, the holding transistor 61 is turned on, and a data signal is written into the holding capacitor C. Even when the selection period ends and the holding transistor 61 is turned off, the voltage of the data signal is held in the holding capacitor C. Accordingly, the drive transistor 62 can supply a predetermined current to the OLED element 64 even during a period from the end of a certain selection period to the start of the next selection period. In this example, the cathode 645 is opposed to a part of the connection wiring 63, but how much the two are overlapped depends on the capacity value of the storage capacitor C determined by the length of the storage period. For this reason, the cathode 645 may be opposed to the entire connection wiring 63.
Note that a resistance element may be provided in the connection wiring 63 from the viewpoint of removing noise. in this case,
The resistance element is desirably provided in a range B shown in FIG. That is, a resistance element is provided in a region that does not face the cathode 645. If a resistance element is provided in the region A where the connection wiring 63 and the cathode 645 face each other, the capacitance value of the storage capacitor C decreases. Therefore, it is possible to efficiently form the storage capacitor C by providing a resistance element in a region where the two do not face each other.
8 is a cross-sectional view taken along line Z2-Z2 ′ shown in FIG. As shown in this figure, the first power supply wiring Ld is composed of a first layer wiring F1 and a second layer wiring F2, which are connected via a contact hole. The second power supply wiring Ls is composed of a second layer wiring F2 and a third layer wiring F3, which are connected via a contact hole. Here, the first layer wiring F1 is
This corresponds to the layer constituting the gate electrode in the holding transistor 61 and the driving transistor 62. Here, the second layer wiring F2 includes the holding transistor 61 and the driving transistor 62.
Corresponds to the layers constituting the source / drain electrodes. Third layer wiring F3 is OLED
This corresponds to the cathode 645 of the element 64. The partition wall 15 is provided between the second layer wiring F2 and the third layer wiring F3, and functions as a second interlayer insulating layer that insulates both. First layer wiring F1, second
The layer wiring F2 is formed while forming transistors such as the holding transistor 61 and the driving transistor 62, and the third layer wiring F3 is formed while forming the OLED element 64. As described above, the first power supply wiring Ld and the second power supply wiring Ls have a laminated structure.
The impedance of the power supply wiring can be reduced, and the stable first power supply voltage signal VDDEL and second power supply voltage signal VSSEL can be supplied. Here, the second layer wiring F2 is shared by the first power supply wiring Ld and the second power supply wiring Ls. Accordingly, the first layer wiring F1, the second layer wiring F2, and the third layer wiring F3 are formed together with the transistor and the OLED element 64, and therefore, without increasing the number of steps, the first power wiring Ld and the second layer wiring F3 are formed. The power supply wiring Ls can be formed as a laminated structure including two wiring layers. As a result, it is not necessary to provide a dedicated layer for the power supply wiring to have a laminated structure, and a simple structure can be achieved. The second power supply line Ls may further include a layer corresponding to the anode 641 of the OLED element 64. Thereby, the impedance of the power supply wiring can be further reduced.
FIG. 11 shows an external configuration of the head unit 10. The external structure of the head part 10 is shown. In this example, the head unit 10 (light emitting device) has a substrate 1 and a sealing member 2 provided on the upper surface thereof.
FIG. 12 is a cross-sectional view showing an example of a cross section of the head unit 10 taken along line SS ′. Data lines L0 to L127 are formed in the region E1 shown in this figure. In the region E2, a wiring 50a for supplying the power supply voltage signal VLL on the low potential side is formed. A data line driving circuit 50 is formed in the region E3. In the region E4, a wiring 50b for supplying the power supply voltage signal VHH on the high potential side is formed.
As shown in FIG. 12, the substrate 1 includes a first end face F1 and a second end face F2. And
On the upper surface of the substrate 1, a data line driving circuit 5 is provided between the first end face F1 and the second end face F2.
0, data lines L0 to L127, holding transistor 61, OLED element 64, driving transistor 62, power supply line Ld, and power supply line Ls are arranged in this order. Further, the sealing member 2 includes the data line driving circuit 50, the data lines L0 to L127, the holding transistor 61, and the OLED element 6.
4, connected to the substrate 2 so as to cover the drive transistor 62, the power supply line Ld, and the power supply line Ls. As shown in FIG. 12, the sealing member 2 has a plate portion 2a and a frame portion 2b. The plate portion 2 a is provided at a position facing the OLED element 64 provided on the substrate 1. The frame part 2 b has a frame part 2 b that is joined to the substrate 1 via an adhesive 22. Moreover, the board | substrate 1 and the sealing member 2 are joined only by the flame | frame part 2b, and the sealing space 23 is provided between the OLED element 64 provided in the board | substrate 1, and the plate part 2b. In this space, an inert gas such as dry nitrogen or a liquid is sealed, and the light emitting layer 60 or the cathode 64 is filled.
5 is prevented from being deteriorated by oxygen or moisture. Further, a desiccant or the like may be disposed in the sealed space 23. In this example, so-called can sealing is employed in this way. Moreover, you may employ | adopt thin film sealing and board bonding sealing. In the thin film sealing, for example, a thin film such as silicon oxide or silicon nitride formed by chemical vapor deposition or the like may be formed on the OLED element 64 as the sealing member 2. In the substrate bonding and sealing, for example, a substrate such as glass as the sealing member 2 and the substrate 1 may be bonded to each other through an adhesive disposed on the OLED element 64. Here, the board | substrate 1 and the sealing member 2 are joined in the part in which organic materials, such as the partition 15, are not formed. By doing so, it is possible to prevent oxygen and moisture from entering the sealed space from the outside.
The light emitting layer 643 of the OLED element 64 includes a light emitting material such as a conductive polymer or a monomer. This luminescent material is easily oxidized and has the property of deteriorating characteristics when exposed to oxygen.
For the cathode 645, a material having a low work function is selected to inject electrons. Such a material contains, for example, calcium and easily reacts with water entering from the outside to form a hydroxide film. When a hydroxide film is formed, inconvenience occurs in electron injection.
The sealing member 2 is for protecting an internal structure from external air, and has a function of blocking gas. However, in the case of can sealing or substrate bonding sealing, a slight amount of gas enters the inside from the adhesive bonded to the sealing member 2 and the substrate 1. In the case of thin film sealing, a slight amount of gas enters the inside from the joint surface between the sealing member 2 and the substrate 1. For this reason, it is desirable that the OLED element 64 and the cathode 641 that are easily affected by gas be arranged as far as possible from the first and second end faces F1 and F2 of the substrate 1.
In the arrangement shown in FIG. 12, the OLED element 64 is arranged between the holding transistor 61 and the driving transistor 62. Further, the data lines L0 to L127 and the data line are arranged between the holding transistor 61 and the first end face F1. The drive circuit 50 is disposed, and power supply lines Ld and Ls are disposed between the drive transistor 62 and the second end face F2. Therefore, the OLED element 6
4 can be arranged near the center of the substrate 1. As a result, reliability can be improved.
Further, since the cathode 645 is not disposed in the holding transistor 61 and the regions E1 to E4, the cathode 645 is hardly affected by gas entering from the first end face F1 side. Therefore, it is possible to reduce the deterioration of the characteristics of the cathode 645 and improve the reliability.
FIG. 13 shows another example of a cross section obtained by cutting the head unit 10 along line SS ′. This example is shown in FIG.
2 is that the arrangement of the power supply line Ls and the power supply line Ld is reversed. That is, the power supply line Ls to which the cathode 645 is connected is disposed at a position farther from the second end face F2 than the power supply line Ld. In this case, the power supply line Ld and the drain electrode 622 of the driving transistor 62 are connected via the gate wiring. According to this arrangement, it is difficult to be influenced by gas entering from the second end face F2. Therefore, it is possible to reduce the deterioration of the characteristics of the cathode 645 and improve the reliability.
FIG. 9 is a longitudinal side view showing an example of an image forming apparatus using the head unit 10 described above.
This image forming apparatus includes four organic EL array exposure heads 10K, 10C, 1 having the same configuration.
0M, 10Y, corresponding four similar photosensitive drums (image carriers) 110K,
Arranged at the exposure positions 110C, 110M, and 110Y, respectively, is configured as a tandem image forming apparatus. Organic EL array exposure heads 10K, 10C, 10
M and 10Y are comprised by the head part 10 mentioned above.
As shown in FIG. 9, the image forming apparatus is provided with a driving roller 121 and a driven roller 122, and includes an intermediate transfer belt 120 that is circulated and driven in the direction of the arrow in the drawing. Photosensitive members 110K, 110C, 110M, and 110Y having photosensitive layers are arranged on the outer peripheral surface as four image carriers arranged at predetermined intervals with respect to the intermediate transfer belt 120. K, C, M, and Y added after the reference sign mean black, cyan, magenta, and yellow, respectively, and indicate that the photoconductors are black, cyan, magenta, and yellow, respectively. The same applies to other members. The photoreceptors 110K, 110C, 110M, and 110Y are the intermediate transfer belt 120.
It is driven to rotate in synchronization with the drive.
Around each photoconductor 110 (K, C, M, Y), the photoconductor 110 (K, C, M,
Y) is uniformly charged by a charging means (corona charger) 111 (K, C, M, Y) for uniformly charging the outer peripheral surface and the charging means 111 (K, C, M, Y). The outer peripheral surface of the photoconductor 1
An organic EL array exposure head 10 (K, C, M, Y) as described above of the present invention that sequentially scans lines in synchronization with rotation of 10 (K, C, M, Y) is provided.
Further, a developing device 114 (K) that applies toner as a developer to the electrostatic latent image formed by the organic EL array exposure head 10 (K, C, M, Y) to form a visible image (toner image). , C, M,
Here, in each organic EL array exposure head 10 (K, C, M, Y), the array direction of the organic EL array exposure head 10 (K, C, M, Y) is the photosensitive drum 110 (K, C, M). , Y) along the bus. Then, each organic EL array exposure head 10 (K, C, M,
The light emission energy peak wavelength of Y) and the sensitivity peak wavelength of the photoconductor 110 (K, C, M, Y) are set to substantially coincide.
The developing device 114 (K, C, M, Y) uses, for example, a non-magnetic one-component toner as a developer, and the one-component developer is conveyed to the developing roller by a supply roller, for example, and adhered to the developing roller surface. The film thickness of the developer is regulated by a regulating blade, and the developing roller is moved to the photosensitive member 110 (K
, C, M, Y) to contact or push the photosensitive member 110 (K, C, M, Y).
The toner is developed as a toner image by attaching a developer according to the potential level.
The black, cyan, magenta, and yellow toner images formed by the four-color single-color toner image forming station are sequentially primary-transferred onto the intermediate transfer belt 120 and sequentially superimposed on the intermediate transfer belt 120 to form a full color. It becomes. The recording medium 102 fed one by one from the paper feed cassette 101 by the pickup roller 103 is transferred to the secondary transfer roller 12.
6 is sent. The toner image on the intermediate transfer belt 120 is secondarily transferred to the recording medium 102 such as a sheet by the secondary transfer roller 126 and is fixed on the recording medium 102 by passing through the fixing roller pair 127 as a fixing unit. Thereafter, the recording medium 102 is discharged onto a paper discharge tray formed in the upper part of the apparatus by a paper discharge roller pair 128.
As described above, since the image forming apparatus of FIG. 9 uses the organic EL array as the writing means, the apparatus can be made smaller than when the laser scanning optical system is used.
Next, another embodiment of the image forming apparatus according to the present invention will be described.
FIG. 10 is a vertical side view of the image forming apparatus. In FIG. 10, the image forming apparatus includes, as main constituent members, a rotary developing device 161, a photosensitive drum 165 functioning as an image carrier, an exposure head 167 provided with an organic EL array, an intermediate transfer belt 169, and a sheet. A conveyance path 174, a fixing roller heating roller 172, and a paper feed tray 178 are provided. The exposure head 167 is configured by the head unit 10 described above.
In the developing device 161, the developing rotary 161a rotates counterclockwise about the shaft 161b. The inside of the development rotary 161a is divided into four parts, yellow (Y),
Four color image forming units of cyan (C), magenta (M), and black (K) are provided. The developing rollers 162a to 162d and the toner supply rollers 163a to 163 are the four
Each of the color image forming units is arranged. Further, the toner is regulated to a predetermined thickness by the regulation flades 164a to 164d.
The photosensitive drum 165 is charged by a charger 168, and a drive motor (not shown),
For example, it is driven in the opposite direction to the developing roller 162a by a step motor. The intermediate transfer belt 169 is stretched between the driven roller 170b and the drive roller 170a, and the drive roller 170a is connected to the drive motor of the photosensitive drum 165 to transmit power to the intermediate transfer belt. The driving roller 170 of the intermediate transfer belt 169 is driven by the driving motor.
a is rotated in the opposite direction to the photosensitive drum 165.
The paper conveyance path 174 is provided with a plurality of conveyance rollers, a pair of paper discharge rollers 176, and the like, and conveys the paper. An image (toner image) on one side carried by the intermediate transfer belt 169 is
Transfer is performed on one side of the sheet at the position of the secondary transfer roller 171. The secondary transfer roller 171 is separated from and brought into contact with the intermediate transfer belt 169 by a clutch, and is brought into contact with the intermediate transfer belt 169 when the clutch is turned on, so that an image is transferred onto the sheet.
The sheet on which the image has been transferred as described above is then subjected to a fixing process by a fixing device having a fixing heater. The fixing device is provided with a heating roller 172 and a pressure roller 173. The sheet after the fixing process is drawn into the discharge roller pair 176 and proceeds in the arrow F direction. When the paper discharge roller pair 176 rotates in the opposite direction from this state, the paper reverses its direction and advances along the double-sided printing conveyance path 175 in the direction of arrow G. The sheets are picked up one by one from the paper feed tray 178 by the pickup roller 179.
For example, a low-speed brushless smoke is used as a drive motor for driving the conveyance roller in the sheet conveyance path. The intermediate transfer belt 169 uses a step motor because it requires color misregistration correction. Each of these motors is controlled by a signal from a control means (not shown).
In the state shown in the drawing, a yellow (Y) electrostatic latent image is formed on the photosensitive drum 165, and a high voltage is applied to the developing roller 128a, whereby a yellow image is formed on the photosensitive drum 165. When all of the yellow back side and front side images are carried on the intermediate transfer belt 169, the development rotary 161a rotates 90 degrees.
The intermediate transfer belt 169 rotates once and returns to the position of the photosensitive drum 165. Next, cyan (C
2) is formed on the photosensitive drum 165, and this image is carried on the yellow image carried on the intermediate transfer belt 169. Hereinafter, development rotary 161 is similarly performed.
90 degree rotation, and one rotation process after the image is held on the intermediate transfer belt 169 is repeated.
For carrying four color images, the intermediate transfer belt 169 rotates four times, and then the rotation position is further controlled to transfer the image onto the sheet at the position of the secondary transfer roller 171. The paper fed from the paper feed tray 178 is transported by the transport path 174, and the color image is transferred to one side of the paper at the position of the secondary transfer roller 171. As described above, the paper having the image transferred on one side is a pair of paper discharge rollers 1
It is reversed at 76 and is waiting on the conveyance path. Thereafter, the sheet is conveyed to the position of the secondary transfer roller 171 at an appropriate timing, and the color image is transferred to the other side. Housing 1
80, an exhaust fan 181 is provided.
It is a block diagram which shows the structure of the light-emitting device of this invention. It is a circuit diagram which shows the input ESD protection unit of the same apparatus. It is a circuit diagram which shows the output ESD protection unit of the same apparatus. It is a circuit diagram of a pixel circuit of the same device. It is a wave form diagram which shows the relationship between a data signal and a drive current. It is a top view which shows the wiring structure of a pixel block and a data line. It is sectional drawing of the Z1-Z1 'line shown in FIG. It is sectional drawing of the Z2-Z2 'line | wire shown in FIG. It is a vertical side view which shows an example of an image forming apparatus. It is a vertical side view which shows the other example of an image forming apparatus. It is a perspective view which shows the external appearance structure of a light-emitting device. It is sectional drawing which shows an example of the cross section which cut | disconnected the apparatus by line | wire S-S '. It is sectional drawing which shows the other example of the cross section which cut | disconnected the apparatus by line | wire S-S '.
DESCRIPTION OF SYMBOLS 10 ... Light-emitting device (head part), 13 ... 1st interlayer insulation layer, 14 ... 2nd interlayer insulation layer, F1 ...
First layer wiring, F2 ... second layer wiring, F3 ... third layer wiring, VDDEL ... first power supply voltage signal, VSSEL
2nd power supply voltage signal, 103 Data line, P Pixel circuit, 645 Cathode (first electrode), 6
41 ... anode (second electrode), 61 ... holding transistor, 62 ... driving transistor, 63 ... connection wiring, 64 ... OLED element (light emitting element), 110Y, 110M, 110C, 110K ...
A light emitting device in which a plurality of pixel circuits are arranged in one direction,
A light emitting element that emits light of a size according to the amount of drive current;
A drive transistor for supplying the drive current to the first electrode;
A holding transistor for supplying a data signal supplied via the data line to the driving transistor;
A connection wiring for connecting the driving transistor and the holding transistor;
The holding transistor, the light emitting element, and the driving transistor are arranged in a direction crossing an arrangement direction of the plurality of pixel circuits, and the light emitting element is arranged between the holding transistor and the driving transistor. Light-emitting device.
A first power supply voltage is supplied to the driving transistor via a first power supply wiring,
The light emitting element includes a first electrode connected to the driving transistor, and a second electrode to which a second power supply voltage is supplied via a second power supply wiring,
2. The light emitting device according to claim 1, wherein the first power supply wiring and the second power supply wiring are arranged outside the region where the plurality of pixel circuits are formed and on the driving transistor side.
The light emitting device according to claim 1, wherein the light emitting elements are arranged in a staggered manner in adjacent pixel circuits.
4. The light emitting device according to claim 3, wherein a length of the light emitting element in the arrangement direction of the pixel circuits is longer than a pitch between the plurality of pixel circuits.
The first power supply wiring and the second power supply wiring have a laminated structure composed of a plurality of layers,
The plurality of layers are formed of a first layer wiring formed in the same layer as a layer constituting the gate electrode of the driving transistor and a same layer as a layer constituting the source and drain electrodes of the driving transistor. A second layer wiring, a third layer wiring constituting the second electrode, a first interlayer insulating layer provided between the first layer wiring and the second layer wiring, and the second layer wiring. And a second interlayer insulating layer provided between the third-layer wiring, and
The first power supply wiring is formed using the first layer wiring and the second layer wiring,
The light emitting device according to claim 2, wherein the second power supply wiring is formed using the second layer wiring and the third layer wiring.
The plurality of layers are formed of a first layer wiring formed in the same layer as a layer constituting the gate electrode of the driving transistor and a same layer as a layer constituting the source and drain electrodes of the driving transistor. a second layer wirings, and the third layer wiring constituting the second electrode, and the fourth layer wiring formed at the same layer as the layer constituting the first electrode, the said first layer wiring first A first interlayer insulating layer provided between two-layer wiring, and a second interlayer insulating layer provided between the second-layer wiring and the third-layer wiring,
The light emitting device according to claim 2, wherein the second power supply wiring is formed using the second layer wiring, the third layer wiring, and the fourth layer wiring.
7. The light-emitting device according to claim 1, wherein the first electrode is an anode of the light-emitting element, and the second electrode is a cathode of the light-emitting element.
A plurality of data lines provided in parallel with the arrangement direction of the plurality of pixel circuits and connected to each of the plurality of pixel circuits;
A plurality of data lines, the holding transistor, the light emitting element, the driving transistor, the first power supply wiring, and the second power supply wiring are sequentially formed between the first end face and the second end face. A substrate,
A sealing member connected to the substrate so as to cover the plurality of data lines, the holding transistor, the light emitting element, the driving transistor, the second power supply wiring, and the first power supply wiring. The light emitting device according to claim 2, 5, or 6.
A plurality of data lines, the holding transistor, the light emitting element, the driving transistor, the second power supply wiring, and the first power supply wiring are sequentially formed between the first end face and the second end face. A substrate,
A sealing member connected to the substrate so as to cover the plurality of data lines, the holding transistor, the light emitting element, the driving transistor, the first power supply wiring, and the second power supply wiring;
The light emitting device according to claim 2, 5 or 6, wherein the first electrode is an anode of the light emitting element, and the second electrode is a cathode of the light emitting element.
A photoreceptor on which an image is formed by irradiation of light;
A head unit that irradiates the photosensitive member with light and forms the image;
An image forming apparatus using the light emitting device according to claim 1 for the head portion.
JP2005050324A 2004-07-27 2005-02-25 Light emitting device and image forming apparatus Active JP4193805B2 (en)
JP2005050324A JP4193805B2 (en) 2004-07-27 2005-02-25 Light emitting device and image forming apparatus
US11/113,192 US7397491B2 (en) 2004-07-27 2005-04-25 Light-emitting device and image forming apparatus
KR20050043064A KR100655875B1 (en) 2004-07-27 2005-05-23 Light-emitting device and image forming apparatus
TW94118204A TWI298475B (en) 2004-07-27 2005-06-02 Light-emitting device and image forming apparatus
CN 200810145428 CN101330781B (en) 2004-07-27 2005-06-13 Light-emitting device
CN 200510078040 CN100421144C (en) 2004-07-27 2005-06-13 Light-emitting device, image forming apparatus
US12/155,446 US20090002287A1 (en) 2004-07-27 2008-06-04 Light-emitting device and image forming apparatus
US12/222,704 US7663655B2 (en) 2004-07-27 2008-08-14 Light-emitting device and image forming apparatus
JP2006065280A JP2006065280A (en) 2006-03-09
JP4193805B2 true JP4193805B2 (en) 2008-12-10
JP2005050324A Active JP4193805B2 (en) 2004-07-27 2005-02-25 Light emitting device and image forming apparatus
CN (2) CN101330781B (en)
TW (1) TWI298475B (en)
JP5862404B2 (en) * 2012-03-26 2016-02-16 富士ゼロックス株式会社 Light emitting element array chip, light emitting element head, and image forming apparatus
JP6225666B2 (en) * 2013-11-27 2017-11-08 コニカミノルタ株式会社 Optical writing apparatus and image forming apparatus
JP4550958B2 (en) * 1999-11-16 2010-09-22 株式会社沖データ Driving circuit
JP5019677B2 (en) 2001-06-25 2012-09-05 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
JP4103373B2 (en) 2001-11-08 2008-06-18 松下電器産業株式会社 Electroluminescence display device and method of manufacturing electroluminescence display device
JP3799266B2 (en) * 2001-11-15 2006-07-19 富士通株式会社 Noise light removal method, noise light removal apparatus and optical transmission system using stimulated Brillouin scattering
TWI338186B (en) * 2002-02-01 2011-03-01 Seiko Epson Corp
2005-02-25 JP JP2005050324A patent/JP4193805B2/en active Active
2005-04-25 US US11/113,192 patent/US7397491B2/en active Active
2005-05-23 KR KR20050043064A patent/KR100655875B1/en active IP Right Grant
2005-06-02 TW TW94118204A patent/TWI298475B/en active
2005-06-13 CN CN 200810145428 patent/CN101330781B/en active IP Right Grant
2005-06-13 CN CN 200510078040 patent/CN100421144C/en active IP Right Grant
2008-06-04 US US12/155,446 patent/US20090002287A1/en not_active Abandoned
2008-08-14 US US12/222,704 patent/US7663655B2/en active Active
CN100421144C (en) 2008-09-24
TWI298475B (en) 2008-07-01
TW200605005A (en) 2006-02-01
US20090002287A1 (en) 2009-01-01
US7663655B2 (en) 2010-02-16
JP2006065280A (en) 2006-03-09
KR100655875B1 (en) 2006-12-11
KR20060049436A (en) 2006-05-19
US20090002473A1 (en) 2009-01-01
CN101330781A (en) 2008-12-24
CN1728221A (en) 2006-02-01
US7397491B2 (en) 2008-07-08
US20060022601A1 (en) 2006-02-02
CN101330781B (en) 2010-10-27
US20030178551A1 (en) 2003-09-25 Image sensor apparatus having additional display device function
CN101009308B (en) 2012-05-30 Light-emitting device and electronic apparatus
TWI317169B (en) 2009-11-11 Light-emitting device and electronic apparatus
TW577241B (en) 2004-02-21 Display device
TWI457899B (en) 2014-10-21 Display device
KR100529077B1 (en) 2005-11-15 Image display apparatus, display panel and driving method thereof
JP4085963B2 (en) 2008-05-14 Image forming apparatus
US8785948B2 (en) 2014-07-22 Light-emitting device and electronic apparatus
US8125506B2 (en) 2012-02-28 Electro-optical device and electronic apparatus
CN1897090A (en) 2007-01-17 Semiconductor device and a driving method
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