Source: http://www.google.com/patents/US20020000613?dq=3657699
Timestamp: 2017-11-22 21:36:55
Document Index: 137920655

Matched Legal Cases: ['Application No. 7', 'art 2002', 'art 2003', 'art 2103', 'art 2106', 'art 2202', 'art 2203', 'art 2303']

Patent US20020000613 - Semiconductor device - Google Patents
A semiconductor device and a process for producing the same, the semiconductor device comprising two conductive layers provided as separate layers, and an insulating layer sandwiched by the two conductive layers, in which the two conductive layers are electrically connected to each other with an embedded...http://www.google.com/patents/US20020000613?utm_source=gb-gplus-sharePatent US20020000613 - Semiconductor device
Publication number US20020000613 A1
Application number US 09/197,767
Also published as US7192865, US7202497, US8440509, US20070161236
Publication number 09197767, 197767, US 2002/0000613 A1, US 2002/000613 A1, US 20020000613 A1, US 20020000613A1, US 2002000613 A1, US 2002000613A1, US-A1-20020000613, US-A1-2002000613, US2002/0000613A1, US2002/000613A1, US20020000613 A1, US20020000613A1, US2002000613 A1, US2002000613A1
Inventors Hisashi Ohtani, Misako Nakazawa, Satoshi Murakami
Original Assignee Hisashi Ohtani, Misako Nakazawa, Satoshi Murakami
Patent Citations (93), Referenced by (59), Classifications (14), Legal Events (3)
US 20020000613 A1
two conductive layers provided as separate layers;
an insulating layer sandwiched by said two conductive layers; and
an embedded conductive layer provided to fill an opening formed in said insulating layer,
wherein said two conductive layers are electrically connected to each other with said embedded conductive layer and
wherein said embedded conductive layer comprises an organic resin film containing a conductive material dispersed therein or an inorganic film containing a conductive material dispersed therein.
an oxide conductive layer provided to fill an opening formed in said insulating layer,
wherein said two conductive layers are electrically connected to each other with said oxide conductive layer.
wherein said two conductive layers are electrically connected to each other with said embedded conductive layer,
wherein said embedded conductive layer comprises an organic resin film containing a conductive material dispersed therein or an inorganic film containing a conductive material therein, and
wherein a shape of said opening is in accordance with a shape of said embedded conductive layer embedded in said opening.
wherein said two conductive layers are electrically connected to each other with said oxide conductive layer, and
wherein a shape of said opening is in accordance with a shape of said oxide conductive layer embedded in said opening.
wherein said embedded conductive layer comprises an organic resin film containing a conductive material dispersed therein or an inorganic film containing a conductive material dispersed therein, and
wherein one of said two conductive layers is provided on a flat surface formed by said embedded conductive layer.
wherein one of said two conductive layers is provided on a flat surface formed by said oxide conductive layer.
7. A semiconductor device according to claim 1, wherein said conductive material is a carbon material.
8. A semiconductor device according to claim 3, wherein said conductive material is a carbon material.
9. A semiconductor device according to claim 5, wherein said conductive material is a carbon material.
10. A semiconductor device according to claim 1, wherein said conductive material is selected from the group consisting of zinc oxide, aluminum flakes and nickel flakes.
11. A semiconductor device according to claim 3, wherein said conductive material is selected from the group consisting of zinc oxide, aluminum flakes and nickel flakes.
12. A semiconductor device according to claim 5, wherein said conductive material is selected from the group consisting of zinc oxide, aluminum flakes and nickel flakes.
13. A semiconductor device according to claim 2, wherein said oxide conductive layer comprises indium tin oxide.
14. A semiconductor device according to claim 4, wherein said oxide conductive layer comprises indium tin oxide.
15. A semiconductor device according to claim 6, wherein said oxide conductive layer comprises indium tin oxide.
16. A semiconductor device according to claim 1, wherein one of said two conductive layers is in contact with an alignment film.
17. A semiconductor device according to claim 2, wherein one of said two conductive layers is in contact with an alignment film.
18. A semiconductor device according to claim 3, wherein one of said two conductive layers is in contact with an alignment film.
19. A semiconductor device according to claim 4, wherein one of said two conductive layers is in contact with an alignment film.
20. A semiconductor device according to claim 5, wherein one of said two conductive layers is in contact with an alignment film.
21. A semiconductor device according to claim 6, wherein one of said two conductive layers is in contact with an alignment film.
22. A semiconductor device according to claim 1, 2, 3, 4, 5 or 6 is applied to a display device of a cellular phone.
23. A semiconductor device according to claim 1, 2, 3, 4, 5 or 6 is applied to a display device of a camcorder.
24. A semiconductor device according to claim 1, 2, 3, 4, 5 or 6 is applied to a display device of a portable computer.
25. A semiconductor device according to claim 1, 2, 3, 4, 5 or 6 is applied to a display device of a head mounting display.
26. A semiconductor device according to claim 1, 2, 3, 4, 5 or 6 is applied to a display device of a rear type projector.
27. A semiconductor device according to claim 1, 2, 3, 4, 5 or 6 is applied to a display device of a front type projector.
28. A method for producing a semiconductor device comprising:
a step of forming a first conductive layer;
a step of forming an insulating layer over said first conductive layer;
a step of forming an opening in said insulating layer to expose said first conductive layer at a bottom of said opening;
a step of forming an embedded conductive layer to cover said insulating layer and said opening;
a step of etching or polishing said embedded conductive layer to make a state in that only said opening is filled with said embedded conductive layer; and
a step of forming a second conductive layer on said insulating layer and said embedded conductive layer.
29. A method for producing a semiconductor device comprising:
a step of forming an oxide conductive layer by a spin coating method to cover said insulating layer and said opening;
a step of etching or polishing said oxide conductive layer to make a state in that only said opening is filled with said oxide conductive layer; and
a step of forming a second conductive layer on said insulating layer and said oxide conductive layer.
30. A method for producing a semiconductor device comprising:
a step of forming a second conductive layer on said embedded conductive layer;
a step of patterning said second conductive layer to a desired pattern; and
a step of etching said embedded conductive layer by using said second conductive layer as a mask in a self alignment manner.
31. A method for producing a semiconductor device comprising:
a step of forming a second conductive layer on said oxide conductive layer;
a step of patterning said second conductive layer to a desired pattern, and
a step of etching said oxide conductive layer by using said second conductive layer as a mask in a self alignment manner.
32. A method for producing a semiconductor device according to claim 28, wherein said embedded conductive layer comprises an organic resin film containing a conductive material dispersed therein or an inorganic film containing a conductive material dispersed therein.
33. A method for producing a semiconductor device according to claim 30, wherein said embedded conductive layer comprises an organic resin film containing a conductive material dispersed therein or an inorganic film containing a conductive material dispersed therein.
34. A method for producing a semiconductor device according to claim 32, wherein said conductive material is a carbon material.
35. A method for producing a semiconductor device according to claim 33, wherein said conductive material is a carbon material.
36. A method for producing a semiconductor device according to claim 32, wherein said conductive material is selected from the group consisting of zinc oxide, aluminum flakes and nickel flakes.
37. A method for producing a semiconductor device according to claim 33, wherein said conductive material is selected from the group consisting of zinc oxide, aluminum flakes and nickel flakes.
38. A method for producing a semiconductor device according to claim 29, wherein said oxide conductive layer comprises indium tin oxide.
39. A method for producing a semiconductor device according to claim 31, wherein said oxide conductive layer comprises indium tin oxide.
The invention further relates to, as a eighth aspect, a process for producing a semiconductor device comprising a step of forming a first conductive layer,
The invention further relates to, as a ninth aspect, a process for producing a semiconductor device comprising a step of forming a first conductive layer,
The invention further relates to, as a tenth aspect, a process for producing a semiconductor device comprising a step of forming a first conductive layer,
Therefore, the material providing conductivity is preferably in the form of fine particles having a particle diameter of ½ or less (more preferably {fraction (1/10)} or less, particularly preferably {fraction (1/100)} or less) of the opening width of the opening provided in the insulating layer. For example, in the case where the opening has a diameter of 1 μm (contact hole) to connect the wiring (conductive layers), the material dispersed in the embedded conductive layer preferably has a diameter of 0.5 μm or less (more preferably 0.1 μm or less, particularly preferably 0.01 μm or less).
[0066]FIGS. 1A, 1B and 1C are schematic cross sectional views showing the production process of the connection structure of wiring according to one embodiment of the invention.
[0067]FIGS. 2A, 2B and 2C are schematic cross sectional views showing the production process of the connection structure of wiring in Example 1 according to the invention.
[0068]FIGS. 3A, 3B, 3C and 3D are schematic cross sectional views showing the production process of a pixel matrix circuit in Example 2 according to the invention.
[0069]FIGS. 4A, 4B, 4C and 4D are schematic cross sectional views showing the production process of a pixel matrix circuit in Example 2 according to the invention.
[0070]FIGS. 5A, 5B and 5C are schematic cross sectional views showing the production process of a pixel matrix circuit in Example 2 according to the invention.
[0071]FIGS. 6A, 6B, 6C and 6D are schematic cross sectional views showing the production process of a pixel matrix circuit in Example 3 according to the invention.
[0072]FIGS. 7A, 7B, 7C and 7D are schematic cross sectional views showing the production process of a pixel matrix circuit in Example 3 according to the invention.
[0073]FIGS. 8A, 8B and 8C are schematic cross sectional views showing the production process of a pixel matrix circuit in Example 3 according to the invention.
[0074]FIGS. 9A, 9B and 9C are schematic cross sectional views showing the production process of a pixel matrix circuit in Example 7 according to the invention.
[0075]FIGS. 10A, 10B and 10C are schematic cross sectional views showing the production process of a pixel matrix circuit in Example 8 according to the invention.
[0076]FIGS. 11A and 11B are schematic perspective views of electro-optical device of Example 11 according to the invention.
[0077]FIGS. 12A to 12F are schematic perspective views of electronic apparatuses of Example 13 according to the invention.
After forming the embedded conductive layer 104 by the spin coating method, an excess of the solvent is removed by a baking (curing) step to improve the film quality depending on necessity. The conditions for the curing step are not limited, and baking (heat treatment) at 300° C. for 30 minutes is generally required.
The first conductive layer 201 is covered with an insulating layer (interlayer insulating layer) 202. As the insulating layer 202, an insulating film containing silicon such as silicon oxide, silicon nitride and silicon oxidenitride, or an organic resin layer is used as a single layer or as having a multilayer structure.
After forming the oxide conductive layer 204, a drying step at a temperature of from 150 to 170° C. and a baking step at 300° C. or higher are conducted, and further an annealing step is conducted depending on necessity, to improve the film quality. The conditions of the curing step are not limited to the above, and the optimum conditions may be determined through experiments.
A quartz substrate 301 having an insulating surface is prepared. In this example, because a heat treatment at a temperature of from 900 to 1,1000° C. is conducted, a material having high heat resistance must be used. A crystalline glass (glass ceramics) substrate provided with an underlayer film and a silicon substrate provided with a thermal oxidized film may be used.
After thus obtaining the state of FIG. 3A, removal of hydrogen is conducted at 450° C. for 1 hour, and a heat treatment is conducted at 570° C. for 14 hours, to obtain a lateral growing region 306. After thus finishing the crystallization step, an addition step of phosphorus is conducted by using the mask insulating film 303 itself as a mask, through which a phosphorus-added region 307 is formed.
After thus obtaining the state of FIG. 3B, a heat treatment at 600° C. for 12 hours is conducted, so that nickel remaining in the lateral growing region 306 is subjected to gettering into the phosphorous-added region 307. As a result, a region in which the nickel concentration is lowered to 5×1017 atoms/cm3 (called a gettered region) 308 is obtained as shown in FIG. 3C.
After forming the gate insulating film 311, a heat treatment at 950° C. for 30 minutes in an oxygen atmosphere is conducted to form a thermal oxidized film at the interface between the active layer and the gate insulating film, by which the interface properties can be largely improved. The active layer 309 and 310 are oxidized to be thinned through the thermal oxidation step. In this example, the thickness of the active layers is finally adjusted to 50 nm. That is, the thickness of the initial film (amorphous silicon film) is 65 nm, and oxidation is conducted for 15 nm, to result in a thermal oxidized film having a thickness of 30 nm. The gate insulating film 311 has a total thickness of 150 nm. The state until this step is shown in FIG. 3D. An aluminum film containing 0.2% by weight of scandium (not shown in figure) is formed, and an island pattern as a base of a gate electrode is formed by patterning. After forming the island pattern, the technique described in Unexamined Published Japanese Patent Application No. 7-135318 is applied, the details of which can be referred to the publication.
The porous anodic oxidized films 312 and 313 are removed by the wet etching method. The etching is conducted by using a mixed solution of phosphoric acid, acetic acid and nitric acid, the concentrations of which are 72.3% by weight ±0.1, 9.5% by weight ±1.0 and 2.0% by weight ±0.4, respectively, with water as a solvent.
A quartz substrate 601 having an insulating surface is prepared. In this example, because a heat treatment at a temperature of from 900 to 1,100° C. is conducted, a material having high heat resistance must be used. A crystalline glass (glass ceramics) substrate provided with an underlayer film and a silicon substrate provided with a thermal oxidized film may be used.
After thus obtaining the state of FIG. 6A, removal of hydrogen is conducted at 450° C. for 1 hour, and a heat treatment is conducted at 570° C. for 14 hours, to obtain a lateral growing region 606. After thus finishing the crystallization step, an addition step of phosphorus is conducted by using the mask insulating film 603 itself as a mask, through which a phosphorus-added region 607 is formed.
After thus obtaining the state of FIG. 6B, a heat treatment at 600° C. for 12 hours is conducted, so that nickel remaining in the lateral growing region 606 is subjected to gettering into the phosphorus-added region 607. As a result, a region in which the nickel concentration is lowered to 5×1017 atoms/cm3 (called a gettered region) 608 is obtained as shown in FIG. 6C.
After forming the gate insulating film 611, a heat treatment at 950° C. for 30 minutes in an oxygen atmosphere is conducted to form a thermal oxidized film at the interface between the active layer and the gate insulating film, by which the interface properties can be largely improved.
The porous anodic oxidized films 612 and 613 are removed by the wet etching method. The etching is conducted by using a mixed solution of phosphoric acid, acetic acid and nitric acid, the concentrations of which are 72.3% by weight ±0.1, 9.5% by weight ±1.0 and 2.0% by weight ±0.4, respectively, with water as a solvent.
In this example, a coating type ITO film having a viscosity of from 10 to 30 cps (produced by Asahi Denka Kogyo K. K.) is used as the oxide conductive layer 640. After coating the solution by the spin coating method, it is subjected to a drying step at a temperature of from 150 to 200° C. for from 5 to 10 minutes and a baking step at a temperature of from 300 to 400° C. for from 1 to 2 hours, to improve the film quality. The treatments for improving the film quality is not limited to those conducted in this example.
Since a material mainly composed of aluminum is used as the gate electrode and the source/drain electrode in Example 3, the heat resistance of that material should be considered. However, when a material having high heat resistance is used as the material for the electrodes, an annealing treatment at a high temperature exceeding 500° C. can be conducted.
In the AMLCD shown in FIG. 11A, the active matrix substrate 1101 and the counter substrate 1105 are joined in such a manner that the edges thereof are arranged, provided that a part of the counter electrode 1105 is removed to expose the active matrix substrate 1101, and an FPC (flexible printed circuit) 1106 is connected thereto.
Signals from outside are transferred to the inner circuit by the FPC 1106.
[0206]FIG. 12A shows a cellular phone, which is composed of a main body 2001, a sound output part 2002, a sound input part 2003, a display device 2004, an operation switch 2005 and an antenna 2006. The invention can be applied to the display device 2004.
[0207]FIG. 12B shows a camcorder, which is composed of a main body 2101, a display device 2102, a sound input part 2103, an operation switch 2104, a battery 2105 and an image receiving part 2106. The invention can be applied to the display device 2102.
[0208]FIG. 12C shows a portable computer, which is composed of a main body 2201, a camera part 2202, an image receiving part 2203, an operation switch 2204 and a display device 2205. The invention can be applied to the display device 2205.
[0209]FIG. 12D shows a head mounting display, which is composed of a main body 2301, a display device 2302 and a belt part 2303. The invention can be applied to the display device 2302.
[0210]FIG. 12E shows a rear type projector, which is composed of a main body 2401, a light source 2402, a display device 2403, a polarized beam splitter 2404, reflectors 2405 and 2406, and a screen 2406. The invention can be applied to the display device 2403.
[0211]FIG. 12F shows a front type projector, which is composed of a main body 2501, a light source 2502, a display device 2503, an optical system 2504 and a screen 2505. The invention can be applied to the display device 2503.
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International Classification H01L21/77, G02F1/1362, H01L27/12, H01L21/84
Cooperative Classification H01L21/76877, H01L27/124, G02F1/136227, G02F1/1362
European Classification H01L27/12T, G02F1/1362, H01L27/12, G02F1/1362H
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OHTANI, HISASHI;NAKAZAWA, MISAKO;MURAKAMI, SATOSHI;REEL/FRAME:009628/0956