Source: http://www.google.com/patents/US20040153612?dq=6233389
Timestamp: 2016-05-04 23:48:31
Document Index: 433089599

Matched Legal Cases: ['arts 21', 'arts 21', 'art 48', 'art 49', 'arts 50', 'art 51', 'art 49']

Patent US20040153612 - Method and system for accelerated access to a memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsMethod of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of: producing access requests (46, 47) defining each time a type of access and designating one or several memory locations (46 a-d , 47 a-b) arranged in accordance with...http://www.google.com/patents/US20040153612?utm_source=gb-gplus-sharePatent US20040153612 - Method and system for accelerated access to a memoryAdvanced Patent SearchPublication numberUS20040153612 A1Publication typeApplicationApplication numberUS 10/478,725PCT numberPCT/IB2002/001794Publication dateAug 5, 2004Filing dateMay 21, 2002Priority dateMay 22, 2001Also published asEP1395908A1, US7487301, WO2002095601A1Publication number10478725, 478725, PCT/2002/1794, PCT/IB/2/001794, PCT/IB/2/01794, PCT/IB/2002/001794, PCT/IB/2002/01794, PCT/IB2/001794, PCT/IB2/01794, PCT/IB2001794, PCT/IB2002/001794, PCT/IB2002/01794, PCT/IB2002001794, PCT/IB200201794, PCT/IB201794, US 2004/0153612 A1, US 2004/153612 A1, US 20040153612 A1, US 20040153612A1, US 2004153612 A1, US 2004153612A1, US-A1-20040153612, US-A1-2004153612, US2004/0153612A1, US2004/153612A1, US20040153612 A1, US20040153612A1, US2004153612 A1, US2004153612A1InventorsStephane Mutz, Eric Desmicht, Thierry NouvetOriginal AssigneeStephane Mutz, Eric Desmicht, Thierry NouvetExport CitationBiBTeX, EndNote, RefManPatent Citations (11), Referenced by (34), Classifications (5), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for accelerated access to a memory
[0047] In the drawings: [0048] [0048]FIG. 1 shows diagrammatically a data processing system according to the invention, [0049] [0049]FIG. 2 shows diagrammatically a programmable memory interface circuit according to the invention, [0050] [0050]FIG. 3 shows a sequence of bits coding a memory address of the system of FIG. 1, [0051] [0051]FIG. 4 is an address mapping of the memory of the system shown in FIG. 1, [0052] [0052]FIGS. 5a to 5 c illustrate three steps of pre-processing a request for access by the memory interface circuit shown in FIG. 2, [0053] [0053]FIGS. 5d and 5 e illustrate two steps of post-processing a read request by the memory interface circuit shown in FIG. 2, [0054] [0054]FIG. 6a shows the development with respect to time of two access operations processed without the pre-processing steps shown in FIGS. 5a to 5 c, [0055] [0055]FIG. 6b shows the development with respect to time of two access operations processed with the pre-processing steps of FIGS. 5a to 5 c, [0056] [0056]FIG. 7 shows the development of a preload of a bank designated by an access request of a central unit during the realization of an access operation of a data processing circuit within the system shown in FIG. 1, [0057] [0057]FIG. 8 shows the development of a write access operation by the central unit interrupting a write access operation by a data processing circuit, [0058] [0058]FIG. 9 shows the development of a read access operation by the central unit interrupting a read access operation by a data processing circuit, [0059] [0059]FIG. 10 shows the development of a write access operation by the central unit interrupting a read access operation by a data processing circuit, [0060] [0060]FIG. 11 shows the development of a read access operation by the central unit interrupting a write access operation by a data processing circuit. [0061] The data processing system shown in FIG. 1 comprises a memory 1 of the SDRAM type comprising four banks A, B, C and D. The memory 1 is connected to a memory interface circuit 2 comprising a buffer memory 3. The interface circuit 2 is connected to a central unit 4 comprising a logic and arithmetic unit 5 and a controller 6, and to a data processing circuit 7. For example, the data processing circuit 7 is a processor dedicated to processing audio, video and graphic (AVG) data such as data in the MPEG format (Motion Picture Expert Group). [0062] The central unit 4 is connected to the interface circuit 2 by connection means 8 comprising a data bus, an address bus and command lines. The data processing circuit 7 is connected to the interface circuit 2 by connection means 9 also comprising a data bus 15, an address bus and command lines 16, which can be seen in FIG. 2. A data interface module 40 is connected to the data bus 15 and ensures the reception and transmission of AVG data from the interface circuit 2. [0063] The interface circuit 2 is connected to the memory 1 by connection means 17 comprising a data bus 10, an address bus 11, two bank selection lines 12 and 13 and command lines 14. A mask command DQM also allows selection of a part of each memory location which is accessed when the data to be read or written are shorter than the memory word. A memory word is made up of, for example, 32 bits. [0064] The memory 1 is a collective memory in which the central unit 4 performs access operations for reading and writing data and instruction codes and in which the data processing circuit 7 performs access operations for reading and writing the AVG data. Per design of the memory 1, a single access operation may be performed simultaneously. The central unit 4 and the data processing circuit 7 access the memory 1, both for writing and reading, by way of the interface circuit 2 by producing an access request sent to the interface circuit 2, i.e. a transfer command to be executed by the interface circuit 2. [0065] In a variant, several analog data processing circuits each produce requests for access to the memory 1. In this case, the different data processing circuits communicate with the interface circuit 2 via a common data central unit which transmits in known manner the access requests and the corresponding data between the data processing circuit transmitting the request and the interface circuit 2. In this case, the block 7 of FIG. 1 is considered to represent a set of data processing circuits and their common data central unit. [0066] Per design of the memory 1, an access operation is performed in one or several bursts of consecutive locations in one or several banks. In the embodiment under consideration, the requests of the data processing circuit 7 refer each time to 16 memory words representing, for example, pixel values of a portion of the image. The requests by the central unit may refer to 1, 4 or 8 memory words. [0067] An access request designates a set of memory locations that must form the subject of an access and defines a series of data to be transferred and a transfer direction to be effected. For example, the transfer direction is defined by the high or low positioning of one or several specific input registers of the interface circuit 2. A series of data to be read is designated by an address in the memory 1. A series of data to be written is designated by a signal on a data bus at the input of the interface circuit 2. The memory locations that form the subject of an access are defined by the following parameters: an address of a first location of a first block to be read or written in the memory 1, a number of blocks to be read or written, a number of locations to be skipped between each block and a number of consecutive memory locations to be read or written in each block. Of course there may also be a single block of contiguous locations. An address comprises a bank number, a row number and a column number. [0068] The interface circuit 2 treats each access request in such a way that the defined series of data is transferred from the source of the request to the memory locations thus defined, or from the locations thus defined to the source of the request, according to whether a write or a read request is concerned. [0069] The operation of the memory interface circuit 2 will now be described with reference to FIG. 2. A processing phase which is specific for the access requests sent by the data processing circuit 7 will be described first. [0070] The interface circuit 2 comprises an arbitration module 18 connected to the command lines 16 and dedicated to the arbitration of the access requests sent by the processing circuit or circuits 7. The arbitration module 18 applies a certain arbitration procedure so as to determine the order in which the access requests that are in the queue and emanate from the processing circuit or circuits 7 must be executed. At the start of this procedure, an access request 42 is accepted and transmitted to a pre-processing module 19 by means of a command register, whereafter the remaining requests in the queue are re-arbitrated. [0071] For example, the accepted access request 42 is coded in this command register in the following manner: the eight least significant bits designate a number of memory words to be skipped between each block of data to be read or written, the four subsequent bits designate a number of consecutive memory words per block, the next bit designates the type of access among the types of reading and writing and the subsequent bits designate the address of a first memory word of a first block to be read or written in the memory 1. [0072] The pre-processing module 19 applies a procedure in two steps to the access request 42 received from the circuit or from one of the circuits 7: [0073] in a regrouping step, the number of different banks concerned for the access request is computed. When the access request concerns several banks, it is divided into as many parts of access requests. Each request part designates all the memory locations designated by the request and belonging to a different bank. [0074] in a sequencing step, the pre-processing module 19 sequences the request parts produced from the pre-processed request so as to prevent that two parts of the executed request successively concern one and the same bank. To this end, it determines the bank concerned for the last part of the request immediately preceding the request during pre-processing and places a part of the request designating a different bank at the first location. [0075] As soon as the part or parts of the request 21 supplied from the access request are available, each with a designated bank number, the number of the row designated in the bank, the number and the list of columns designated in the row and an indicator of the access type, they are transmitted to a column generator 20 in the order determined above. The column generator 20 is dedicated to the access requests of the data processing circuit 7. [0076] The pre-processing module 19 sends a signal 23 to a collision manager 22, which signal indicates the presence of a part of the request ready to be executed. [0077] A processing phase which is specific for the access requests sent by the central unit 4 will now be described. An access request from the central unit 4 is received by a central unit interface module 28 connected to the connection means 8. The interface module 28 comprises a queue which contains only a single request waiting to be processed. The interface module 28 waits until the request which is in the process of being processed is ended before it accepts the next request. A request for access to the memory 1 coming from the central unit 4 always concerns a series of consecutive addresses, i.e. it does not comprise a skipped location. When it accepts a request, the interface module 28 transmits a signal 29 to the collision manager 22 indicating the presence of a central unit request which is ready to be executed and it transmits the accepted request 33 to a column generator 30 dedicated to the access requests of the central unit 4. [0078] The collision manager 22 has the function of arbitrating between the parts of the request and the central unit requests which are ready to be executed. The collision manager 22 manages the realization of access operations requested by the central unit 4 and the data processing circuit or circuits 7 so as to process the requests which have first priority. Indeed, the AVG data are considered as ordinary data, in contrast to the data and instruction codes of the central unit 4 which are considered as priority data. In order to operate, the collision manager 22 generates activation signals 24 and 34 destined for the column generators 20 and 30, respectively, in accordance with a predetermined method. [0079] A processing phase which is common for all the requests will now be described. The column generators 20 and 30 are activated by the reception of the activation signal 24 or 34 of the collision manager 22. Upon reception of the corresponding activation signal, the column generator 20 or 30 processes the part or parts 21 of the request of the data processing circuit or the request of the central unit 33, respectively, by translating it into a series of column numbers 31, or into a series of column numbers 32, respectively, so as to form access demands at an appropriate detailed level for a command generator 25 (numbers of bank, row and column of each memory location concerned by the part of the request or by the request of the central unit, respectively). In co-operation with the activated column generator 20 or 30, the command generator 25 also generates a succession of elementary access commands, each elementary command defining an operation of access to a single address. [0080] The command generator 25 also produces commands which are necessary for preparing access operations to be performed, such as preload commands for the bank concerned and activation of the row forming the subject of an access operation. The command generator 25 also ensures the production of commands which are necessary for regular refreshing of the memory 1, for example, of the order of 64 refreshes per millisecond. [0081] A signal generator 26 generates command signals on the lines 14, which signals are specific for the memory 1, for example, RAS, CAS and WE signals which are known to those skilled in the art, as a function of the commands 27 sent by the command generator 25. Each data item of the series defined by the request is transferred by the data bus 10 between a memory location of the memory 1 and the buffer memory 3. For each data item, the bank is selected by positioning the bank selection lines 12 and 13, and the row and column numbers are selected by the address bus 11. The interface 2 also comprises a module for monitoring the state of the banks 54, which module generates signals indicating the state of each bank and its activity. [0082] Other characteristic features of the data processing system shown in FIG. 1 will now be described with reference to FIGS. 3 and 4. [0083] [0083]FIG. 3 shows a sequence 35 of 24 coding bits of an address of the memory 1 as designated in an access request received by the interface circuit 2. Each coding bit is individually marked by a weight ranging from 0 to 23, respectively. FIG. 3 also shows the interpretation of each bit of the sequence 35 by the interface circuit 2. In the example shown, the memory 1 is supposed to be a SDRAM memory having a total capacity of 64 Mo, with four banks of 256 columns by 2048 rows each. Consequently, a column number is coded at 8 bits, a row number at 11 bits and a bank number at 2 bits, a complete address being coded at 2+11+8=21 bits. It is of course also possible to use banks having a different row and/or column number by adapting the number of bits used for coding the corresponding number. It is also possible to use two identical SDRAM memory units for the memory 1, having four banks each and, in a corresponding way, to lengthen the addresses of a selection bit of the memory unit. In practice, the addresses are normalized at 32 bits, in which the excess most significant bits denoted by the reference numeral 36 are not used. [0084] As is shown in FIG. 3, the interface circuit 2 converts an address in an access request coming from the processing circuit 7 or from the central unit 4 by means of the following method: the bank is determined by a binary code of two bits formed, in a decreasing order of weight, by bits having a weight of 20 and 3, respectively, of the sequence 35, hereinafter denoted by B1 and B0, respectively. The column number is determined by a binary code of eight bits formed, in a decreasing order of weight, from bits having weights of 8, 7, 6, 5, 4, 2, 1 and 0, respectively, of the sequence 35. The row number is determined by a binary code of eleven bits formed, in a decreasing order of weight, from bits having weights of 19 to 9, respectively, of the sequence 35. [0085] The banks are selected in the following manner: the selection bit of the bank B1 designates either the couple of banks A-B (low value) or the couple of banks C-D (high value). Within the respective couples, the selection bit of the bank B0 designates either the bank A, or C (low value), respectively, or the bank B or D (high value), respectively. [0086] In the system of FIG. 1, the data processing circuit 7 and the central unit 4 are designed in such a way that they read or write the data which belong to them in a different couple of A-B or C-D banks. For example, the AVG data belonging to the data processing circuit 7 are written, read and memorized in the couple of banks A-B, the bit B1 being always positioned at its low value in the addresses designated by the access requests of the data processing circuit 7. Reciprocally, the data belonging to the central unit 4, for example, command instructions, are written, read and memorized in the couple of banks C-D, the bit B1 being always positioned at its high value in the addresses designated by the corresponding access requests of the central unit 4. [0087] Consequently, with reference to FIG. 4, the address mapping of the memory 1 is as follows. In an increasing order of addresses, represented by the axis 37, the memory 1 has a first zone 38 dedicated to the data belonging to the data processing circuit 7 and constituted by an alternation of blocks of banks A and B, each block having a length L of 8 words, and a second zone 39 dedicated to the data belonging to the central unit 4 and constituted by an alternation of blocks of the banks C and D of the same length L. [0088] A request of the data processing circuit 7 designates a series in a sequence of sixteen addresses of the first zone 38 of the memory, for example, in the form of a number of blocks, a number of words per block and a number of locations to be skipped between each block. Because of the mapping of the memory 1, these sixteen addresses may be distributed in an arbitrary manner between the banks A and B. In the frequent case where a request designates sixteen consecutive addresses, they always correspond to locations which have been evenly distributed between the banks A and B. This particular feature reduces the probability of occurrence of a sequence of two requests or two consecutive parts of requests designating one and the same bank. [0089] As the conversion of the addresses in memory locations is effected by the interface circuit 2, the addressing mode used by the central unit 4 and the processing circuit 7 do not need to be modified for realizing the mapping of memory 1. This addressing mode may thus remain compatible with other components with which the central unit 4 and the processing circuit 7 must communicate. [0090] The pre-processing of the requests by the pre-processing module 19 will now be explained in greater detail with reference to FIGS. 5a to 5 c. [0091] [0091]FIG. 5a diagrammatically shows the access request 42 received from the arbitration module 18 by the pre-processing module 19. The first line indicates the number of columns that form the subject of an access operation in a certain row specified by the request. The second line indicates the bank to which each column belongs. It is supposed that the columns designated c1 to c16 of the memory 1 comprise data d1 to d16. [0092] With reference to FIG. 5b, the pre-processing module 19 reads the numbers of the sixteen columns designated by the request 42 in the order in which they are designated and, for each column, sends a number encoded on one bit of the bank in which the column is present (for example 0 for the bank A and 1 for the bank B) to the interface module 40 through a queue 41. The pre-processing module 19 also determines the number of different banks designated in the request. [0093] With reference to FIG. 5c, the pre-processing module 19 comprises a state indicator 44 indicating the number of the bank in which the last column is situated which is designated by the last request or part of the request which it has pre-processed previously, which is now being processed by the command processor 25 or is queuing behind an access request of the central unit. The state indicator 44 indicates the bank A in FIG. 5c. When the request 42 designates several banks, i.e. A and B in the example shown, the pre-processing module 19 re-sequences the columns of the request 42 by regrouping them per associated bank into as many column series. The column series belonging to a bank different from that indicated by the state indicator 44, i.e. belonging to bank B in the example shown, is placed first. The series of column numbers c2 and c4 to c16 designated, in this order, in the request 42 and belonging to bank B is thus processed as a first part of the request 21 a. The series of column numbers c1 and c3 designated, in this order, in the request 42 and belonging to bank A is processed as a second part of the request 21 b. The request parts 21 a and 21 b are transmitted, in this order, to the column generator 20, as has been explained hereinbefore. [0094] A phase of post-processing requests of the read type of the data processing circuit 7 by the interface module 40 will now be elucidated with reference to FIGS. 5d and 5 e. It is supposed that the request 42 processed is of the read type. [0095] With reference to FIG. 5d, the processing of the first part of the request by the command generator 25 involves reading of the data in the order in which the columns have been designated to the column generator 20. The first data item transferred to the interface circuit 2 is thus d2, which was memorized in the column c2. As from the arrival of a data item read, the interface module 40 reads an address available from the buffer memory 3 in a queue 43 comprising all the available addresses and temporarily stores the received data item d2 at this address @1. The interface module 40 also comprises two address queues 45 a and 45 b dedicated to the data from the banks A and B, respectively. The state indicator 44 now indicates the bank B in which the data are being read. The interface module 40 thus copies the storage address @1 in the queue 45 b dedicated to the data from the bank B. This process is repeated for the whole series of data d1 to d16 defined by the request 42. [0096] With reference to FIG. 5e it is supposed that all the data have been transferred from the memory 1 into the buffer memory 3 of the interface circuit 2. The address queues 45 a and 45 b are shown in their final state. The interface module 40 ensures the re-sequencing of the received data. To this end, the queue 41 is read. At each bank number read, the interface module 40 reads the first address of the queue dedicated to the data from the corresponding bank, i.e. first the address 15 in queue 45 a, because the first bank number read is 0. It reads the data item stored at the address @15, which is the data item d1, and transmits it on the data bus 15 to the processing circuit 7. The address @15 is released and reset in the queue 43. This process is repeated for all the bank numbers of the queue 41 until a signal is read which indicates that the last column of the request has been reached. The request is then terminated. The data are thus transferred to the processing circuit 7 in the order of the memory locations defined by the request 42. [0097] For a write request, the interface module 40 performs a pre-processing operation which is symmetrical to the post-processing operation described hereinbefore. During the execution of a part of the request or of a request from the current central unit (current access), the command generator 25 examines the parameters of a part of the request or of a subsequent request of the central unit under preparation (subsequent access). When the subsequent access refers to a bank which is different from the bank concerned by the current access, the command generator 25 generates the preload and activation commands of the bank concerned by the subsequent access during the execution of the current access in such a way that no clock cycle is lost for preparing the subsequent access. To this end, the command generator 25 generates the commands which correspond to the signals which it receives simultaneously from the column generators 20 and 30 and from the collision manager 22 in the following order of decreasing priority: [0098] 1—preload of a bank designated by a request of the central unit, [0099] 2—activation of a bank designated by a request of the central unit, [0100] 3—generation of an elementary access command for the central unit, [0101] 4—generation of an elementary access command for the processing circuit 7, [0102] 5—activation of a bank designated by a request of the processing circuit 7, [0103] 6—preload of an arbitrary bank, [0104] 7—neutral command. [0105] [0105]FIGS. 6a and 6 b illustrate a reduction of the access times obtained by virtue of pre-processing requests by the interface circuit 2. It is supposed that two requests 46 and 47 of the processing circuit 7 are processed consecutively without a request from the central unit 4 occurring. The request 46 designates, in this order, a batch 46 a of eight columns of the bank A, a batch 46 b of three columns of the bank B, a batch 46 c of two columns of the bank A and a batch 46 d of three columns of the bank B. The request 47 designates, in this order, a batch 47 a of eight columns of the bank B and a batch 47 b of eight columns of the bank A. [0106] [0106]FIG. 6a illustrates the progress with respect to time of processing the requests 46 and 47 if the requests are executed without pre-processing. The realization of an access operation to a bank necessitates an operation of preparing the access by pre-loading of the bank and by activating the row forming the subject of an access operation. This preparation requires a time At which has a value of, for example, 6 clock cycles of the SDRAM memory. The preparation of the subsequent access operation is performed from the start of the transfer of data corresponding to the current access. However, the transfers corresponding to the batches of the columns 46 b and 46 c are shorter than the preparation time Δt, such that a delay is lost before the transfers corresponding to the batches 46 c and 46 d. Moreover, the request 47 starts with an access operation in the bank B in which the last column accessed in the course of the access operation 46 is present. A delay At is thus lost during the preparation of the bank B between the processing of two requests. [0107] [0107]FIG. 6b illustrates the progress with respect to time of processing of the requests 46 and 47 with the pre-processing operation by the module 19. The transfer commands of data corresponding to the column batches 46 a and 46 c are regrouped into a first request part 48 and are consecutively processed in such a way that the delay lost before processing of the batch 46 c is suppressed. The commands for data transfers corresponding to the column batches 46 b and 46 d are regrouped into a second request part 49 and are consecutively processed in such a way that the delay lost before processing the batch 46 d is suppressed. The request 47 is processed in two request parts 50 and 51 designating the column batch 47 a and the column batch 47 b, respectively, by starting with the part 51 designating the column batch 47 b, such that the operation of the corresponding transfer of data between the bank A and the interface circuit 2 is prepared during the realization of the transfer corresponding to the request part 49. The delay lost between processing of the two requests 46 and 47 is thus also suppressed. The time required for processing the two requests is thus substantially reduced, for example, by the order of 30% with respect to the case where the pre-processing operation is not performed. [0108] The arbitration of the access operations by the collision manager 22 will now be described in greater detail with reference to FIGS. 7 to 11. All of these Figures show the development as a function of time t of one or several access operations of different types. Each column of the tables shown corresponds to a clock cycle of, for example, 8 ns of the SDRAM memory. The first line of the tables represents the transmission of certain preparation commands of the SDRAM on the command lines 14. A preload command is symbolized by PRE. An activation command is symbolized by ACT. The second line of the tables represents the transmission of elementary read or write commands on the command lines 14. An elementary read or write command requested by the data processing circuit is symbolized by TR and TW, respectively. An elementary read command or write command required by the central unit is symbolized by CR and CW, respectively. An access request designating several memory locations is translated into several successive elementary commands enumerated as from 0. The third line of the tables represents the data in the course of their transfer on the data bus 10. A data item transferred while executing an elementary read or write command is symbolized by the letter D followed by the symbol of the corresponding elementary command. [0109] With reference to FIG. 7, when the collision manager 22 receives the signal 29 during realization of an access operation of the data processing circuit 7 and the bank designated by the request of the central unit 33 must be pre-loaded, it gives the command generator 25 a command to insert a preload command between two elementary commands for the access operation which is in progress, as is shown by means of the arrow 59. The collision manager 22 suspends the generation of the elementary access commands so as to release the command lines of the memory in order that a preload command can be transmitted. To this end, the column generator 20 activates a standby signal 52 throughout the duration by which the generation of the elementary commands must be suspended, i.e. for example, during a clock cycle. The collision manager 22 commands the restart of generating the elementary access commands by transmitting the activation signal 24 to the column generator 20 one clock cycle before said restart, which reinitializes the standby signal 52. [0110] With reference to FIG. 8, it is supposed that a write access of the data processing circuit 7 is activated by the activation signal 24 and is being realized when the central unit 4 requests a write access. An activation command of the bank designated by the request of the central unit is produced during the realization of the access operation in progress, i.e. during the transmission of the elementary command TW3 in the example shown. It is noted that an activation command produces the copy of a row of the SDRAM in a register in which the individual columns can be subsequently read or written and that its execution takes several, for example, two clock cycles. As soon as the activation is terminated, i.e. at the third clock cycle subsequent to the activation command in the example shown, the access operation which is in progress is suspended by the standby signal 52. In the example shown, the access operation which is in progress is suspended after the transmission of the elementary command TW5. The write access of the central unit is launched by the activation signal 34. During production of the last elementary access command for the access operation requested by the central unit, i.e. the elementary command CW7, the column generator 30 sends an end-of-access signal 53 to the manager 22, which leads to the transmission of an activation signal 24 and the re-initialization of the standby signal 52. The generation of the elementary access commands for the suspended access operation is resumed as from the subsequent clock cycle, with the subsequent elementary command TW6. By this sequence of elementary commands, a transfer of data is effected at each clock cycle without any loss of passband. [0111] With reference to FIG. 9, a read access operation of the data processing circuit 7 is launched by the transmission of the activation signal 24, and then the collision manager receives the signal 29. As in the previous case, an activation command of the bank designated by the request of the central unit 4 is transmitted during the realization of the access operation of the circuit 7, i.e. during the transmission of the elementary command TR2. The signals 24, 34 and 52 are then managed as described previously for inserting the access operation of the central unit by temporarily suspending the access operation of the circuit 7. During a write access operation, the data to be written are sent on to the data bus 10 in the same clock-cycle as the transmission of the corresponding elementary commands. In contrast, during a read access operation, there is a delay between the transmission of an elementary command and the transfer of the corresponding data item because of a delay of access to the individual columns LC which are intrinsic in the memory 1, and referred to as latency CAS. This delay is, for example, 3 clock cycles. [0112] The module 54 for monitoring the state of the banks comprises, for each bank, an access indicator which is activated at the start of each access operation in this bank and reinitialized at the end of the access operation. In the example shown, the access indicator 55 is that for the bank, for example, A in which the data are read by the data processing circuit 7 and the access indicator 56 is that for the bank, for example, C designated by the request of the central unit 4. [0113] With reference to FIG. 10, an elementary command sequence is shown which is produced in the case where a write access request of the central unit 4 is produced during a read access operation of the circuit 7. To allow transition of a read access to a write access, the data bus 10 of the memory must pass from an output state to an input state. This change of states is performed by transistors of the bus 10 which, to avoid any risk of short-circuit, pass through a state of strong impedance represented by the symbol HIZ in which no transfer of data can be effected on the bus 10. This transmission requires a delay of one clock cycle. The access of the central unit starts as soon as the activation is terminated at the third clock cycle subsequent to the command ACT, while the transition through the state HIZ is effected just before, i.e. at the second clock cycle subsequent to the command ACT. The last data item read which can thus be transferred on the bus 10 is that transferred at the first clock cycle subsequent to the command ACT. As the latency CAS is three clock cycles, this data item corresponds to the elementary command transmitted in the second clock cycle preceding the command ACT, i.e. the command TR0 in the example shown. Consequently, it is useless to produce read commands from the first cycle preceding the transmission of the command ACT. In fact, the elementary access commands for the access operation to be suspended are replaced by neutral commands NOP based on the command ACT until the start of the access operation of the central unit. However, the elementary access command immediately preceding the command ACT, i.e. TR1, is produced without having the time to be executed before the suspension of the access operation. Consequently, in this case, the suspended access operation is resumed as soon as the completion of the access operation of the central unit by the retransmission of the command TR1 that has not been executed. To this end, the collision manager 22 updates counters of the column generator 20 during its reactivation. The number of elementary commands to be retransmitted must evidently be adapted as a function of the characteristic features of the memory used in each particular realization. [0114] [0114]FIG. 11 shows a sequence of elementary commands produced when a read access operation of the central unit 4 suspends a write access operation of the circuit 7. In this case, the transition to the state HIZ must be effected at the end of the access operation of the central unit. However, to allow the transfer of all the data read by the central unit, a delay which is equal to the latency CAS, i.e. three clock cycles in the example shown, must be left between the production of the last read command CR7 and the transition to the state HIZ. During this delay, the column generator 20 is in a standby position. The suspended access operation is resumed immediately after the transition. [0115] To respect this delay, the module 54 for monitoring the state of the banks is provided with a counter 58 whose value at each clock cycle is indicated in the third line of the table in FIG. 11. The counter 58 is positioned at a value which is equal to LC+1, i.e. the value 4 in the example shown, whenever an elementary read command is transmitted. The counter 58 is decremented by one unit every time when no elementary read command is transmitted. As soon as it reaches the value of zero, a signal 57 is produced by the module 54, as is shown in FIG. 2, so as to indicate to the command generator 25 that the transition to the state HIZ may be effected, and this immediately. [0116] Although the invention has been described with reference to a particular embodiment, it will be evident that it is by no means limited and that it comprises all the equivalent techniques of the means described as well as their combinations if they are within the scope of the invention. There are actually numerous ways of performing the functions by means of hardware elements and/or computer program elements. In this respect, the Figures are very diagrammatic, each Figure representing a single embodiment. Although a Figure may show various functions in the form of separate blocks, it does not exclude that a function may be performed by several separate blocks. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5893136 *Oct 24, 1997Apr 6, 1999Intel CorporationMemory controller for independently supporting Synchronous and Asynchronous DRAM memoriesUS5953743 *Sep 12, 1997Sep 14, 1999Micron Electronics, Inc.Method for accelerating memory bandwidthUS6253297 *Oct 13, 1998Jun 26, 2001Texas Instruments IncorporatedMemory control using memory state information for reducing access latencyUS6297832 *Jan 4, 1999Oct 2, 2001Ati International SrlMethod and apparatus for memory access scheduling in a video graphics systemUS6298370 *Apr 4, 1997Oct 2, 2001Texas Instruments IncorporatedComputer operating process allocating tasks between first and second processors at run time based upon current processor loadUS6434649 *Oct 14, 1998Aug 13, 2002Hitachi, Ltd.Data streamerUS6744472 *Nov 9, 1999Jun 1, 2004Broadcom CorporationGraphics display system with video synchronization featureUS6798420 *Aug 18, 2000Sep 28, 2004Broadcom CorporationVideo and graphics system with a single-port RAMUS6927783 *Nov 9, 1999Aug 9, 2005Broadcom CorporationGraphics display system with anti-aliased text and graphics featureUS20040212734 *May 17, 2004Oct 28, 2004Broadcom CorporationGraphics display system with video synchronization featureUS20050012759 *Jul 16, 2003Jan 20, 2005Broadcom CorporationVideo and graphics system with an MPEG video decoder for concurrent multi-row decoding* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7296130Mar 22, 2004Nov 13, 2007International Business Machines CorporationMethod and apparatus for providing hardware assistance for data access coverage on dynamically allocated dataUS7299319Mar 22, 2004Nov 20, 2007International Business Machines CorporationMethod and apparatus for providing hardware assistance for code coverageUS7421684Mar 22, 2004Sep 2, 2008International Business Machines CorporationMethod and apparatus for autonomic test case feedback using hardware assistance for data coverageUS7480899Mar 22, 2004Jan 20, 2009International Business Machines CorporationMethod and apparatus for autonomic test case feedback using hardware assistance for code coverageUS7926041Dec 16, 2008Apr 12, 2011International Business Machines CorporationAutonomic test case feedback using hardware assistance for code coverageUS7937691Sep 30, 2003May 3, 2011International Business Machines CorporationMethod and apparatus for counting execution of specific instructions and accesses to specific data locationsUS7987453Mar 18, 2004Jul 26, 2011International Business Machines CorporationMethod and apparatus for determining computer program flows autonomically using hardware assisted thread stack tracking and cataloged symbolic dataUS8042102Jun 11, 2008Oct 18, 2011International Business Machines CorporationMethod and system for autonomic monitoring of semaphore operations in an applicationUS8135915Mar 22, 2004Mar 13, 2012International Business Machines CorporationMethod and apparatus for hardware assistance for prefetching a pointer to a data structure identified by a prefetch indicatorUS8141099May 16, 2008Mar 20, 2012International Business Machines CorporationAutonomic method and apparatus for hardware assist for patching codeUS8171457May 1, 2012International Business Machines CorporationAutonomic test case feedback using hardware assistance for data coverageUS8191049May 29, 2012International Business Machines CorporationMethod and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer programUS8255880May 1, 2008Aug 28, 2012International Business Machines CorporationCounting instruction and memory location rangesUS8615619Jan 11, 2011Dec 24, 2013International Business Machines CorporationQualifying collection of performance monitoring events by types of interrupt when interrupt occursUS8689190Jan 29, 2008Apr 1, 2014International Business Machines CorporationCounting instruction execution and data accessesUS20040123882 *Sep 30, 2003Jul 1, 2004Olmer Leonard JIn-situ removal of surface impurities prior to arsenic-doped polysilicon deposition in the fabrication of a heterojunction bipolar transistorUS20050071516 *Sep 30, 2003Mar 31, 2005International Business Machines CorporationMethod and apparatus to autonomically profile applicationsUS20050071609 *Sep 30, 2003Mar 31, 2005International Business Machines CorporationMethod and apparatus to autonomically take an exception on specified instructionsUS20050071611 *Sep 30, 2003Mar 31, 2005International Business Machines CorporationMethod and apparatus for counting data accesses and instruction executions that exceed a thresholdUS20050071612 *Sep 30, 2003Mar 31, 2005International Business Machines CorporationMethod and apparatus for generating interrupts upon execution of marked instructions and upon access to marked memory locationsUS20050071816 *Sep 30, 2003Mar 31, 2005International Business Machines CorporationMethod and apparatus to autonomically count instruction execution for applicationsUS20050071817 *Sep 30, 2003Mar 31, 2005International Business Machines CorporationMethod and apparatus for counting execution of specific instructions and accesses to specific data locationsUS20050071821 *Sep 30, 2003Mar 31, 2005International Business Machines CorporationMethod and apparatus to autonomically select instructions for selective countingUS20050071822 *Sep 30, 2003Mar 31, 2005International Business Machines CorporationMethod and apparatus for counting instruction and memory location rangesUS20050154812 *Jan 14, 2004Jul 14, 2005International Business Machines CorporationMethod and apparatus for providing pre and post handlers for recording eventsUS20050155019 *Jan 14, 2004Jul 14, 2005International Business Machines CorporationMethod and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer programUS20050155026 *Jan 14, 2004Jul 14, 2005International Business Machines CorporationMethod and apparatus for optimizing code execution using annotated trace information having performance indicator and counter informationUS20050210339 *Mar 22, 2004Sep 22, 2005International Business Machines CorporationMethod and apparatus for autonomic test case feedback using hardware assistance for code coverageUS20050210439 *Mar 22, 2004Sep 22, 2005International Business Machines CorporationMethod and apparatus for autonomic test case feedback using hardware assistance for data coverageUS20050210450 *Mar 22, 2004Sep 22, 2005Dimpsey Robert TMethod and appartus for hardware assistance for data access coverageUS20050210452 *Mar 22, 2004Sep 22, 2005International Business Machines CorporationMethod and apparatus for providing hardware assistance for code coverageUS20050210454 *Mar 18, 2004Sep 22, 2005International Business Machines CorporationMethod and apparatus for determining computer program flows autonomically using hardware assisted thread stack tracking and cataloged symbolic dataUS20090100414 *Dec 16, 2008Apr 16, 2009International Business Machines CorporationMethod and Apparatus for Autonomic Test Case Feedback Using Hardware Assistance for Code CoverageEP2980704A1 *Jul 29, 2015Feb 3, 2016Huawei Technologies Co., Ltd.Memory bank accessing method, apparatus and system* Cited by examinerClassifications U.S. Classification711/154International ClassificationG06F12/06, G06F13/16Cooperative ClassificationG06F13/1626European ClassificationG06F13/16A2RLegal EventsDateCodeEventDescriptionNov 24, 2003ASAssignmentOwner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., NETHERLANDSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MUTZ, STEPHANE;DESMICHT, ERIC;NOUVET, THIERRY;REEL/FRAME:015280/0970Effective date: 20031124Aug 17, 2007ASAssignmentOwner name: NXP B.V., NETHERLANDSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KONINKLIJKE PHILIPS ELECTRONICS N.V.;REEL/FRAME:019719/0843Effective date: 20070704Owner name: NXP B.V.,NETHERLANDSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KONINKLIJKE PHILIPS ELECTRONICS N.V.;REEL/FRAME:019719/0843Effective date: 20070704Jul 25, 2012FPAYFee paymentYear of fee payment: 4Mar 7, 2016ASAssignmentOwner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLANDFree format text: SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:038017/0058Effective date: 20160218RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services