Source: http://www.google.com/patents/US7245821?dq=5,815,794
Timestamp: 2016-10-26 05:59:23
Document Index: 658170718

Matched Legal Cases: ['Application No. 02122065', 'Application No. 02122053', 'Application No. 0212054', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000']

Patent US7245821 - Image processing using shared frame memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsWhen a reverse reproduction is instructed, an MPEG video stream is once decoded and is again recoded by an MPEG video encoder so as to generate a recoded data sequence which will be overwritten on a storage area in a hard disk. An MPEG video decoder reads out this recoded data sequence in a reverse time-series...http://www.google.com/patents/US7245821?utm_source=gb-gplus-sharePatent US7245821 - Image processing using shared frame memoryAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7245821 B2Publication typeGrantApplication numberUS 10/156,912Publication dateJul 17, 2007Filing dateMay 28, 2002Priority dateMay 31, 2001Fee statusPaidAlso published asCN1214630C, CN1390046A, US20020196858Publication number10156912, 156912, US 7245821 B2, US 7245821B2, US-B2-7245821, US7245821 B2, US7245821B2InventorsShigeyuki OkadaOriginal AssigneeSanyo Electric Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (11), Non-Patent Citations (9), Referenced by (16), Classifications (17), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetImage processing using shared frame memory
US 7245821 B2Abstract
When a reverse reproduction is instructed, an MPEG video stream is once decoded and is again recoded by an MPEG video encoder so as to generate a recoded data sequence which will be overwritten on a storage area in a hard disk. An MPEG video decoder reads out this recoded data sequence in a reverse time-series manner and decodes it successively, and then converts it to a video signal so as to be outputted to a display.
Information handled in the multimedia is of a vast amount and is multifarious, thus a fast processing of the information is necessary in the course of planning to put the multimedia to practical use. In order to process information at high speed, compression and expansion of data become indispensable. The “MPEG” method is one of data compression and expansion techniques. This MPEG method is being standardized by the MPEG Committee (ISO/IEC JTC1/SC29/WG11) under the ISO (International Organization for Standardization)/IEC (International Electro-technical Commission). An image processing apparatus utilizing the MPEG method is built into various image related devices such as movie camera, still camera, television set, video CD reproduction equipment, DVD reproduction equipment and so forth.
The present invention has been made in view of foregoing circumstances, and an object thereof is to provide an image processing technique capable of obtaining smooth reverse-reproduced pictures. In order to achieve this object and other objects which will become clear in this patent specification, the present invention intends to solve problems in the technique relating principally to the coding and decoding processing of images.
It is to be noted here that the terms “I picture”, “B picture” and “P picture” used in the patent specification correspond to and encompass the concept of “I-VOP (Video Object Plane)”, “B-VOP” and “P-VOP”, respectively, in MPEG-4.
FIG. 1 shows a hierarchical structure of an MPEG video bit stream.
The invention will now be described based on the preferred embodiments, which do not intend to limit the scope of the present invention, but exemplify the invention. All of the features and the combination thereof described in the embodiment are not necessarily essential to the invention.
The processings common to some of the embodiments are forward image reproduction and reverse image reproduction. For the convenience of description, “forward” and “reverse” and their synonyms in the following description should be understood to apply to the order when pictures comprising an image are finally put in a form for display. Hence, unless otherwise indicated, the order of pictures represents the state of display.
As will be described later, even in reverse reproduction, the pictures in each GOP of an MPEG data stream are first decoded in the forward direction, namely, in a time series manner. They are recoded and the reverse order is realized for the first time at a stage of a subsequent redecoding. Thus, “reverse” in reverse reproduction concerns mainly a second decoding. The MPEG bit stream may be realized in a variety of combinations in terms of the order of I, P and B pictures. Frame memories to be included and used in the structure of each embodiment of the present invention may be SDRAM (Synchronous Dynamic RAM), DRAM, Rambus DRAM or the like.
Various component members appear in the following embodiments. In terms of hardware, those embodiments can be realized by a CPU, memory and other LSIs and combined circuit. In terms of software, they are realized by memory-loaded programs or the like with image processing functions. The following description mainly concerns functions that are realized in cooperation with such components. Therefore, it should be understood by those skilled in the art that these functions can be realized in a variety of forms by hardware only, software only or by the combination thereof. An image reproduction apparatus is an example of an “image processing apparatus” according to the present invention.
This first embodiment exemplifies a structure considered in a case where each block constituting the structure of an image processing apparatus is, for example, made to a single chip. The structure for this embodiment does not particularly take into consideration a correspondence thereof to the present invention, and merely presents examples to be compared and referred to the subsequent embodiments.
In FIG. 2, the image reproducing apparatus 1 comprises a hard disk (HD) 4, an MPEG video decoder 5 (hereinafter referred to simply as a “decoder 5” also), an MPEG video encoder 6 (hereinafter referred to simply as an “encoder 6” also), a second MPEG video decoder 7 (hereinafter referred to simply as a “second decoder 7” also), a first frame memory 52, a second frame memory 62, a third frame memory 72, a first display circuit 54, an image input circuit 64, a second display circuit 74, a switching circuit 8 and a control core circuit 10. The control core circuit 10 controls the operation of the decoder 5, the second decoder 7, the encoder 6 and each component of the image reproducing apparatus 1. The hard disk 4, which is comprised of a magnetic disk, stores the video stream transferred from the transfer medium 2 successively. The hard disk 4 is provided with a special storage area 4 a within it.
FIG. 3 is a block diagram showing a structure of the decoder 5. In FIG. 3, the decoder 5 is comprised of a Huffman decoding circuit 14, an inverse quantization circuit 15, an IDCT (Inverse Discrete Cosine Transform) circuit 16, an MC (Motion Compensated prediction) circuit 17 and ROMs (Read Only Memories) 18 and 19. It is to be noted that the decoder 5 is an example of a “front-end decoder” in the other embodiments of the present invention.
In this manner, the decoder 5 generates a reproduced image data sequence continuous in a time series manner by decoding the inputted MPEG video stream. It is to be noted that the MPEG video stream is an example of a “first coded data sequence” in the other embodiments of the present invention.
FIG. 4 is a block diagram showing a structure of the encoder 6. In FIG. 4, the encoder 6 is comprised of an MC circuit 20, a DCT circuit 21, a quantization circuit 22, a Huffman coding circuit 23 and ROMs 24 and 25. It is to be noted that the encoder 6 is an example of an “encoder” in the other embodiments of the present invention.
In this manner, the encoder 6 generates an MPEG video stream by recoding a reproduced image data sequence continuous in a time series. It is to be noted here that this MPEG video stream is one example of a “second coded data sequence” in the other embodiments of the present invention.
FIG. 5 is a block diagram showing a structure of the second decoder 7. In FIG. 5, the second decoder 7 is comprised of a Huffman decoding circuit 26, an inverse quantization circuit 27, an IDCT circuit 28, an MC circuit 29 and ROMs 30 and 31. It is to be noted that the second decoder 7 is one example of a “back-end decoder” in the other embodiments of the present invention.
This and subsequent embodiments have structures corresponding to the present invention. The second embodiment represents a more compact design version of the first embodiment. The second embodiment differs from the first embodiment in that the frame memories are so structured as to have a less capacity as a whole. That is, the first frame memory 52 and second frame memory 62 of the first embodiment are combined into one which is structured such that the total capacity thereof is for four frames.
(1) The frame memory used both as a display buffer and as a work area for coding and decoding can be of a capacity for four frames only. This realizes a memory capacity smaller than the structure of the first embodiment, and lower cost. (2) Unlike the case with the first embodiment, there is no need for the second frame memory 62 and the image input circuit 64. This realizes smaller size and lower cost. (3) That the second decoder 7 decodes the coded data sequence read out in a reverse time series realizes reverse reproduction. THIRD EMBODIMENT
A third embodiment represents a more compact design version of the second embodiment. The third embodiment differs from the second embodiment in that the frame memories are so structured as to have even less capacity as a whole. That is, the first frame memory 80 and second frame memory 90 of the second embodiment are combined into one which is structured such that the total capacity is for three frames only.
(4) The frame memory used both as a display buffer and as a work area for coding and decoding can be of a capacity for three frames only. This realizes a memory capacity even smaller, thus contributing to lower cost. (5) Unlike the case with the first embodiment, there is no need for the second frame memory 62, image input circuit 64, third frame memory 72, second display circuit 74 and switching circuit 8. This realizes even smaller size and lower cost. FOURTH EMBODIMENT
A fourth embodiment has a structure as an example of modification from the third embodiment. The fourth embodiment differs from the image reproducing apparatus 1 according to the third embodiment in that reproduced image data sequences directly read out from the decoder 5, instead of reproduced image data sequences read out from the frame memory 100, are coded. Similar to the frame memory 100 of the third embodiment, the frame memory 100 according to the fourth embodiment is structured with a capacity for three frames.
(6) Similar to the third embodiment, the frame memory used both as a display buffer and as a work area for coding and decoding can be of a capacity for three frames only. This realizes a memory capacity even smaller, thus contributing to lower cost. (7) Similar to the third embodiment and in contrast to the first embodiment, there is no need for the second frame memory 62, image input circuit 64, third frame memory 72, second display circuit 74 and switching circuit 8. This realizes even smaller size and lower cost. (8) Coding by the encoder 6 is started without waiting for the reproduced image data sequence generated by the decoder 5 to be written into the frame memory 100. This realizes higher-speed processing as a whole as long as an adequate processing speed is maintained for the coding processing by the encoder 6. GENERAL EXAMINATION AND VIEW ON THE EMBODIMENTS
As is naturally understood by those skilled in the art, arbitrary combinations of the embodiments, which have not been described herein, are also possible. For example, the following consideration or modifications are possible:
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