Source: http://www.google.com/patents/US20040031004?ie=ISO-8859-1
Timestamp: 2015-07-31 10:32:12
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Matched Legal Cases: ['art 33', 'art 33', 'art 33', 'art 33', 'art 33', 'art 33', 'art 33', 'art 33', 'art 35', 'art 35', 'art 35', 'art 35', 'arts 33', 'art 33', 'art 37', 'art 37', 'art 37', 'arts 33', 'art 43', 'art 43', 'art 43', 'art 45', 'art 45', 'art 45', 'art 51', 'art 51', 'art 51', 'art 51', 'art 55', 'art 55', 'art 55', 'art 55', 'art 55', 'art 55', 'application No. 2002']

Patent US20040031004 - Semiconductor integrated circuit device and fabrication method thereof - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor integrated circuit device and a fabrication method thereof are disclosed, for effective suppression of a temperature increase therein that is caused by heat generation of a semiconductor element. The semiconductor integrated circuit device includes a semiconductor element, a multi-layer...http://www.google.com/patents/US20040031004?utm_source=gb-gplus-sharePatent US20040031004 - Semiconductor integrated circuit device and fabrication method thereofAdvanced Patent SearchPublication numberUS20040031004 A1Publication typeApplicationApplication numberUS 10/633,681Publication dateFeb 12, 2004Filing dateAug 5, 2003Priority dateAug 9, 2002Also published asUS7446417, US7930658, US20090044162Publication number10633681, 633681, US 2004/0031004 A1, US 2004/031004 A1, US 20040031004 A1, US 20040031004A1, US 2004031004 A1, US 2004031004A1, US-A1-20040031004, US-A1-2004031004, US2004/0031004A1, US2004/031004A1, US20040031004 A1, US20040031004A1, US2004031004 A1, US2004031004A1InventorsKeiichi YoshiokaOriginal AssigneeKeiichi YoshiokaExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (16), Classifications (22), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor integrated circuit device and fabrication method thereof
BRIEF DESCRIPTION OF THE DRAWINGS [0049]FIGS. 1A through 1D are cross-sectional views of a conventional MOS transistor and three types of conventional SOI transistors; [0050]FIG. 2 is a cross-sectional view of a semiconductor integrated circuit device according to one embodiment of the present invention; [0051]FIGS. 3A and 3B are plan views of regions where dummy metals are formed; [0052]FIG. 4 is a cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention; [0053]FIG. 5 is a cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention; [0054]FIGS. 6A and 6B are diagrams illustrating standard cells of a standard cell type semiconductor integrated circuit device according to one embodiment of the present invention; [0055]FIGS. 6C and 6D are diagrams illustrating conventional standard cells; [0056]FIGS. 7A and 7B are diagrams illustrating a field cell having a heat conduction part according to one embodiment of the present invention; [0057]FIG. 8 is a diagram illustrating an exemplary arrangement of the field cell in FIGS. 7A and 7B; [0058]FIG. 9 is a diagram illustrating another exemplary arrangement of the field cell in FIGS. 7A and 7B; [0059]FIGS. 10A and 10B are diagrams illustrating a field cell having a heat conduction part according to another embodiment of the present invention; [0060]FIGS. 11A and 11B are diagrams illustrating a field cell having a heat conduction part according to another embodiment of the present invention; and [0061]FIG. 12 is a flowchart of a method of fabricating a standard cell type semiconductor integrated circuit device according to one embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0062] In the following, embodiments of the present invention will be described with reference to the accompanying drawings. [0063]FIG. 2 is a cross-sectional view of a semiconductor integrated circuit device according to one embodiment of the present invention. The semiconductor integrated circuit device includes a semiconductor element such as a fully-depletion type SOI transistor. The semiconductor integrated circuit device comprises a six-layer metal wiring structure. In FIG. 2, individual metal wiring layers are illustrated to have certain sizes, for example, as shown in widths thereof. However, it will be understood that the semiconductor integrated circuit device according to the present invention is not limited to this illustration. [0064] A buried oxide film 3 is formed on a SOI substrate 1, and a plurality of fully-depletion type SOI transistors are formed on a single crystal silicon layer 5 on the buried oxide film 3. Each of the fully-depletion type MOS transistors are electrically separated by separation oxide films 15. The separation oxide films 15 are formed, for example, in accordance with a STI (Shallow Trench Isolation) technique for separating a semiconductor element from another semiconductor element. In accordance with the STI technique, an insulator is buried in shallow trenches for the separation. The fully-depletion type MOS transistor comprises two source regions or two drain regions 9 and a gate electrode 13. The source regions or the drain regions 9 are formed at an interval on the single crystal silicon layer 5 of the SOI substrate 1. The gate electrode 13 is formed of a polysilicon film, for example, between the source regions or the drain regions 9 on the single crystal silicon layer 5 via a gate oxide film 11. Two fully-depletion type SOI transistors in the regions A and B have a common gate electrode 13. [0065] An insulation layer 17 is formed by layering a plurality of insulation layers on the fully-depletion type SOI transistors and the SOI substrate 1 including the element separation film 15. From the bottom layer, metal wiring layers M1, M2, M3, M4, M5 and M6 are sequentially formed in the insulation layer 17. [0066] In the regions A and D, in which the fully-depletion type SOI transistors are formed, the gate electrode 13 is electrically connected to the metal wiring layer M1, which is the bottom layer, via a contact layer 19 and then is electrically connected to the metal wiring layer M2 via a via layer 21. [0067] In the region C, the metal wiring layer M2 is electrically connected to the metal wiring layer M6, which is the top layer, via a via layer 23, the metal wiring layer M3, a via layer 25, the metal wiring layer M4, a via layer 27, the metal wiring layer M5 and a via layer 29. A pad aperture 31 is formed in the insulation layer 17 just above the metal wiring layer M6. Hence, connection holes and metal wiring layers to transmit a signal comprise the components in the wiring path between the contact layer 19 in the region A and the metal wiring layer M6 in the region C. [0068] In the region A, in which the fully-depletion type SOI transistor is formed, a heat conduction part 33 is provided. The heat conduction part 33 comprises a via layer 23, a metal wiring layer M3, a via layer 25, a metal wiring layer M4, a via layer 27, a metal wiring layer M5, a via layer 29 and a metal wiring layer M6. The heat conduction part 33 is formed on the metal wiring layer M2 in a path different from signal transmission path provided by the above-mentioned connection holes and metal wiring layers. [0069] When heat is generated in the region A by the gate operation of the fully-depletion type SOI transistor, the heat is conducted to the contact layer 19, the metal wiring layer M1, the via layer 21 and the metal wiring layer M2 sequentially. Then, the heat is conducted to the metal wiring layer M6 in the region A via the heat conduction part 33 and is released from the upper surface of the insulation layer 17. Thereby, it is possible to prevent a temperature increase of the semiconductor integrated circuit device. [0070] In this embodiment, the heat conduction part 33 comprises the metal wiring layers M3, M4, M5 and M6 and the via layers 23, 25, 27 and 29 in the region A. Also, the heat conduction part 33 is connected to the gate electrode 13 via the components for signal transmission: the contact layer 19, the metal wiring layer M1, the via layer 21 and the metal wiring layer M2. However, the heat conduction part 33 according to the present invention is not limited to this configuration. For instance, neither of conductive components in the region A between the contact layer 19 and the metal wiring layer M6 may be connected to the metal wiring layers for signal transmission and the heat conduction part 33 may be connected to the gate electrode 13 directly. [0071] In the region E adjacent to the region D where a fully-depletion type SOI transistor is formed, a heat conduction part 35 is formed. The heat conduction part 35 comprises a via layer 23, a metal wiring layer M3, a via layer 25, a metal wiring layer M4, a via layer 27 and a metal wiring layer M5. The heat conduction part 35 is formed on the metal wiring layer M2 in a path different from the connection holes and the metal wiring layers for signal transmission. [0072] When heat is generated in the regions D and E by the gate operation of the fully-depletion type SOI transistor, the heat is conducted to a contact layer 19, a metal wiring layer M1, a via layer 21, the metal wiring layer M2 in the region D. Then, the heat is conducted to the metal wiring layer M5 via the heat conduction part 35 and is released from the upper surface of the insulation layer 17. As seen in this embodiment, a heat conduction part according to the present invention need not necessarily contain the metal wiring layer M6. Also, the heat conduction part may be formed in the region E different from the gate electrode 13 in the region D of the fully-depletion type SOI transistor. [0073] The metal wiring layers M3, M4, M5 and M6, which constitute the heat conduction parts 33 and 35, may be dummy metals that are not used as electric wires. Alternatively, the metal wiring layers M3, M4, M5 and M6 may be metal wiring layers dedicated to form the heat conduction part 33. [0074] In the region F, a heat conduction part 37 is formed. The heat conduction part 37 comprises a metal wiring layer M3, a via layer 25, a metal wiring layer M4, a via layer 27, a metal wiring layer M5, a via layer 29 and a metal wiring layer M6. The heat conduction part 37 is not connected to the metal wiring layer M2, which serves as the metal wiring layer for signal transmission. In this embodiment, the metal wiring layers M3, M4, M5 and M6 are formed of dummy metals. [0075]FIGS. 3A and 3B are plan views of a region where dummy metals are formed. FIG. 3A shows dummy metals that constitute a heat conduction part, and FIG. 3B shows dummy metals that do not constitute a heat conduction part. [0076] Referring to FIG. 3B, for example, a dummy metal 39 is formed at the same coordinate from the top viewpoint of a semiconductor integrated circuit device for each of the metal wiring layers M3 through M6. [0077] Referring to FIG. 3A and the region F in FIG. 2, when the dummy metals 39 are used as the heat conduction part, the individual metal wiring layers M3 through M6 are connected to each other via the via layers 25, 27 and 29. In this configuration, it is possible to conduct heat between the metal wiring layers to the upper layer side and further prevent a temperature increase of the semiconductor integrated circuit device. [0078]FIG. 4 is a cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention wherein the same parts as those in FIG. 2 are designated by the same reference numerals and the description thereof is omitted. [0079] The semiconductor integrated circuit device according to this embodiment differs from the above-mentioned semiconductor integrated circuit device in FIG. 2 in that a heat release aperture 41 is formed in the insulation layer 17 on the metal wiring layer M6 in each of the regions A and F. It is preferable that the heat release apertures 41 be formed simultaneously with a pad aperture 31 so as to prevent an increase in the number of fabrication steps. [0080] When the heat release apertures 41 are provided on the metal wiring layers M6, which constitute the heat conduction parts 33 and 35, it is possible to improve efficiency of heat release. In addition, if a semiconductor integrated circuit device, such as a BGA (Ball Grid Array) or a CSP (Chip Size Package), includes an external connection terminal, such as a solder ball, on a pad electrode (the metal wiring layer M6 in the pad aperture 31), the semiconductor integrated circuit device is configured to have additional external connection terminals on the metal wiring layers M6 in the heat release apertures 41. In this configuration, it is possible to increase the number of contact areas between the heat conduction parts including the external connection terminals and the exterior of the semiconductor integrated circuit device. As a result, it is possible to further improve the efficiency of heat release. [0081]FIG. 5 is a cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention wherein the same parts as those in FIG. 2 and FIG. 4 are designated by the same reference numerals and the description thereof is omitted. [0082] In the region G, in which the fully-depletion type SOI transistor is formed, a heat conduction part 43 is formed on the source region or the drain region 9. The heat conduction part 43 comprises a contact layer 19, a metal wiring layer M1, a via layer 21, a metal wiring layer M2, a via layer 23, a metal wiring layer M3, a via layer 25, a metal wiring layer M4, a via layer 27, a metal wiring layer M5, a via layer 29 and a metal wiring layer M6. In this configuration, it is possible to release heat generated in the gate electrode 13 from the source region or the drain region 9 via the heat conduction part 43. [0083] In the region H adjacent to the region G, a heat conduction part 45 is formed on an element separation film 15. The heat conduction part 45 comprises a contact layer 19, a metal wiring layer M1, a via layer 21, a metal wiring layer M2, a via layer 23, a metal wiring layer M3, a via layer 25, a metal wiring layer M4, a via layer 27, a metal wiring layer M5, a via layer 29 and a metal wiring layer M6. In this configuration, it is also possible to release heat generated in the gate electrode 13 from the element separation film 15 via the heat conduction part 45. [0084] In this embodiment, the semiconductor integrated circuit device includes the fully-depletion type SOI transistor as a semiconductor element. The semiconductor integrated circuit device according to the present invention is not limited to this embodiment. The semiconductor integrated circuit device may include another type of a semiconductor element: for example, a partially-depletion type SOI transistor, a SON transistor, a conventional MOS transistor, a capacitor and a resistor. [0085]FIGS. 6A through 6D show standard cells of a standard cell type semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 6A is a plan view of the standard cells. FIG. 6B is a cross-sectional view of a heat conduction part in FIG. 6A. FIG. 6C is a plan view of conventional standard cells. FIG. 6D is a circuit diagram of the conventional standard cells. Here, two inverter cells are used as the standard cells (function modules). [0086] First, conventional standard cells A′ and B′ are described with reference to FIGS. 6C and 6D. In inverter cells A′ and B′, the source regions or the drain regions 9 are formed in activation regions enclosed by element separation films 15 on the semiconductor substrate, and gate electrodes 13 are formed of polysilicon films between the source regions or the drain regions 9 on the semiconductor substrate via gate oxide films (not illustrated). In each of the inverter cells A′ and B′, the gate electrode 13 is shared amongst a plurality of MOS transistors. [0087] A power supply line VDD and a ground line GND are configured from a metal wiring layer M1, which is the bottom layer, on the semiconductor substrate via an insulation layer. The power supply line VDD and the ground line GND partially extend to the source regions or the drain regions 9 and are connected thereto via a contact layer (not illustrated). [0088] In addition, an input line and an output line are configured from a metal wiring layer M1. An input line IN1 of the inverter cell A′ is connected to the gate electrode 13 of the inverter cell A′ via a contact layer (not illustrated), and an output line OUT1 of the inverter cell A′ is connected to the source region or the drain region 9 different from that connected to the power supply line VDD or the ground line GND via the contact layer (not illustrated). An input line IN2 of the inverter cell B′ is connected to the gate electrode 13 of the inverter cell B′ via a contact layer (not illustrated), and an output line OUT2 of the inverter cell B′ is connected to a source region or a drain region 9 different from the source region or the drain region 9 connected to the power supply line VDD or the ground line GND via a contact layer (not illustrated). The output line OUT1 of the inverter cell A′ is connected to the input line IN2 of the inverter cell B′. [0089] Standard cells A and B according to the present invention are described with reference to FIGS. 6A and 6B. In this embodiment, the inverter cell A has the same configuration as the inverter cell A′ in FIG. 6C. The inverter cell B further comprises a heat conduction part 51 connected to the input line IN2 in addition to the configuration of the inverter cell B′. The heat conduction part 51 comprises via layers 21, 23, 25, 27 and 29 and metal wiring layers M2, M3, M4, M5 and M6 (FIG. 6B). [0090] As mentioned above, when the heat conduction part 51 is connected to the input line IN2 connected to the gate electrode 13, in which heat is generated, of the inverter cell B, it is possible to realize a standard cell type semiconductor integrated circuit device that can release the heat through the heat conduction part. [0091] The above-mentioned standard cell type semiconductor integrated circuit device includes a single heat conduction part 51. However, the standard cell type semiconductor integrated circuit device according to the present invention is not limited to this configuration. The standard cell type semiconductor integrated circuit device may include a plurality of heat conduction parts in one standard cell. Also, the heat conduction part according to the present invention is not limited to a signal line connected to a gate electrode. The heat conduction part may be connected to a gate electrode directly. Alternatively, the heat conduction part may be connected to a source region or a drain region directly or via a connection hole and a metal wiring layer for signal transmission. Alternatively, the heat conduction part may be connected to an element separation film directly. [0092]FIGS. 7A and 7B show a field cell of a standard cell type semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 7A is a plan view of the field cell, and FIG. 7B is a cross-sectional view of a heat conduction part. [0093] A power supply line VDD, a ground line GND and a signal line 53 are configured from a metal wiring layer M1, which is the bottom layer, on an element separation film 15 (not illustrated) of a field cell 57, for example, of a minimum wiring grid. The field cell 57 comprises a heat conduction part 55 connected to the signal line 53. The heat conduction part 55 comprises via layers 21, 23, 25, 27 and 29 and metal wiring layers M2, M3, M4, M5 and M6. [0094]FIG. 8 is a plan view of an exemplary arrangement of the field cell 57 in FIG. 7A. In this arrangement, the inverter cells A′ and B′ in FIG. 6C are used as the standard cells. The field cell 57 is arranged between the inverter cells A′ and B′. The output line OUT1 of the inverter cell A′ is connected to the input line IN2 of the inverter cell B′ via the signal line 53. [0095] When heat is generated in the gate electrode 13 of the inverter cell B′, the heat is conducted to a heat conduction part 55 via the input line IN2 and the signal wire 53 and then released from the upper surface side of the semiconductor integrated circuit device. Since the heat conduction part 55 of the semiconductor integrated circuit device is provided in the field cell 57, it is possible to prevent a temperature increase of the semiconductor integrated circuit device. In addition, if the heat conduction part 55 is arranged in the field cell 57, it is possible to realize a standard cell type semiconductor integrated circuit device that can release heat through the heat conduction part 55 without modification of the conventional standard cells A′ and B′. [0096] In FIG. 8, a single field cell 57 is arranged between the inverter cells A′ and B′. However, two field cells 57 may be arranged between the inverter cells A′ and B′, as illustrated in FIG. 9. Furthermore, any desirable number of field cells 57 may be arranged between prepared standard cells. [0097]FIGS. 10A and 10B show another exemplary field cell. FIG. 10A is a plan view of the field cell, and FIG. 10B is a cross-sectional view of a heat conduction part. As shown in FIG. 10B, the heat conduction part may have greater sizes of metal wiring layers M4 and M5, which are upper layer sides, than metal wiring layers M3 and M2 so as to improve efficiency of heat release. [0098] Also, the size of a field cell is not limited to the minimum wiring grid. A field cell may have any suitable grid width, for example, as illustrated in FIG. 11A. [0099] Also, the metal wiring layers M2 through M6 which constitute a heat conduction part may be od any suitable size. [0100] In the above-mentioned embodiments in FIG. 6 through FIG. 11, the semiconductor integrated circuit device according to the present invention is applied to the standard cell type semiconductor integrated circuit device. However, the semiconductor integrated circuit device according to the present invention is not limited to these embodiments. The semiconductor integrated circuit device may be applied to another type of a semiconductor integrated circuit device and a fabrication method thereof. A semiconductor integrated circuit device, such as a gate array type semiconductor integrated circuit device, may be configured by modularizing a plurality of semiconductor elements for each function and arranging the function modules. Furthermore, the semiconductor integrated circuit device according to the present invention is applicable to another type semiconductor integrated circuit device other than the above-mentioned type semiconductor integrated circuit devices (a standard cell type semiconductor integrated circuit device and a gate array type semiconductor integrated circuit device). [0101]FIG. 12 is a flowchart of a fabrication method of a standard cell type semiconductor integrated circuit device according to the present invention. Referring to FIG. 12, each standard cell is disposed on a chip based on a standard cell library, a netlist, timing constraints and other information at step S1. [0102] At step S2, a wiring layout is approximately determined by dividing a wiring area into rectangular areas (channels) such that each of the rectangular areas does not overlap other areas and determining which channel a wiring path of each net (a set of terminals to be connected to each other at the same potential) passes through. Then, the wiring layout is determined in detail by determining a detailed wiring path in each channel. [0103] At step S3, a field cell is arranged in an empty space between standard cells and wires in the determined wiring layout. In an ECO (Engineering Change Order) process, which is performed through layout modification for the purpose of improvement of timing trouble such as delay due to the wiring layout, the field cell is replaced with another field cell, for example, as illustrated in FIG. 6, FIG. 9 and FIG. 10, that includes a heat conduction part according to the present invention corresponding to heat capacity of a gate electrode in an arranged standard cell. Furthermore, at the same time, a standard cell is replaced with another standard cell, as the inverter B illustrated in FIG. 6A, that includes a heat conduction part according to the present invention corresponding to heat capacity of a gate electrode in the standard cell. [0104] After the layout modification at step S4, a back-annotation process is performed at step S5. Namely, the capacity and resistance of a wire between cells is detected by means of software, and logic simulation is performed by using the detected capacity and resistance so as to improve accuracy. [0105] If the back-annotation process gives a negative result (step S5: N), the control returns to the standard cell arrangement at step S1, the approximate and detail wiring arrangement at step S2 or the wiring modification at step S4. On the other hand, if the back-annotation process gives a satisfactory result (step S5: Y), the wiring layout is determined. [0106] In this embodiment, a semiconductor integrated circuit device, which includes the heat conduction part, according to the present invention is fabricated in accordance with the above-mentioned fabrication method of a standard cell type semiconductor integrated circuit device. However, the fabrication method of the semiconductor integrated circuit device according to the present invention is not limited to the above-mentioned standard cell type fabrication method. The semiconductor integrated circuit device according to the present invention is applicable to a semiconductor integrated circuit device fabricated in accordance with any suitable fabrication method, sa will be appreciated by those skilled in the art. [0107] The present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the present invention. [0108] The present application is based on Japanese priority application No. 2002-232551 filed Aug. 9, 2002, the entire contents of which are hereby incorporated by reference. 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