Source: http://www.google.com/patents/US8189372?dq=6861155
Timestamp: 2017-01-17 14:18:12
Document Index: 420805479

Matched Legal Cases: ['art 300', 'art 300', 'art 300', 'art 300', 'art 360', 'art 360', 'art 360', 'art 370', 'art 370', 'art 370']

Patent US8189372 - Integrated circuit including electrode having recessed portion - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode....http://www.google.com/patents/US8189372?utm_source=gb-gplus-sharePatent US8189372 - Integrated circuit including electrode having recessed portionAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8189372 B2Publication typeGrantApplication numberUS 12/025,898Publication dateMay 29, 2012Filing dateFeb 5, 2008Priority dateFeb 5, 2008Fee statusPaidAlso published asCN102024838A, CN102024838B, US20090196094Publication number025898, 12025898, US 8189372 B2, US 8189372B2, US-B2-8189372, US8189372 B2, US8189372B2InventorsMatthew Breitwisch, Shihhung Chen, Thomas Happ, Eric JosephOriginal AssigneeInternational Business Machines Corporation, Macronix International Co., Ltd., Qimonda AgExport CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (7), Classifications (7), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetIntegrated circuit including electrode having recessed portion
US 8189372 B2Abstract
An integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode.
a first electrode including an etched recessed portion having a planar bottom surface;
a resistivity changing material filling the recessed portion and contacting the planar bottom surface, the resistivity changing material coupled to the second electrode, and the resistivity changing material having a first width at the planar bottom surface of the recessed portion between sidewalls of the recessed portion; and
a dielectric material laterally surrounding and directly contacting sidewalls of the resistivity changing material,
wherein the resistivity changing material has a second width between the sidewalls of the resistivity changing material laterally surrounded and directly contacted by the dielectric material, the second width greater than the first width,
wherein the first electrode includes a first electrode material layer and a second electrode material layer, the recessed portion provided in the first electrode material layer and extending through the first electrode material layer, and
wherein the planar bottom surface of the recessed portion is a top surface of the second electrode material layer.
2. The integrated circuit of claim 1, wherein a thermal conductivity of the first electrode material layer is less than a thermal conductivity of the second electrode material layer, and
wherein a resistivity of the first electrode material layer is greater than a resistivity of the second electrode material layer.
3. The integrated circuit of claim 1, wherein the dielectric material layer defines a pore comprising a bottom having a critical dimension,
wherein the resistivity changing material fills the pore, and
wherein the recessed portion has a depth greater than 10% of the critical dimension of the pore.
4. The integrated circuit of claim 1, wherein the dielectric material layer defines a pore comprising a bottom having a critical dimension,
wherein the recessed portion has a depth within a range of 30-70% of the critical dimension of the pore.
a memory device communicatively coupled to the host, the memory device including a recessed pore phase change memory cell comprising:
an electrode including an etched recessed portion having a planar bottom surface;
a phase change material deposited in the recessed portion and contacting the planar bottom surface, the phase change material having a first width at the planar bottom surface of the recessed portion between sidewalls of the recessed portion; and
a dielectric material laterally surrounding and directly contacting sidewalls of the phase change material,
wherein the phase change material has a second width between the sidewalls of the phase change material laterally surrounded and directly contacted by the dielectric material, the second width greater than the first width,
wherein the electrode includes a first electrode material layer and a second electrode material layer, the recessed portion provided in the first electrode material layer and extending through the first electrode material layer, and
6. The system of claim 5, wherein a thermal conductivity of the first electrode material layer is less than a thermal conductivity of the second electrode material layer, and
7. The system of claim 5, wherein the memory device further comprises:
a write circuit configured to write a resistance state to the recessed pore phase change memory cell;
a sense circuit configured to read a resistance state of the recessed pore phase change memory cell; and
a dielectric material layer including an etched pore; and
phase change material in the recessed portion and the pore, the phase change material contacting the planar bottom surface, and the phase change material having a first width at the planar bottom surface of the recessed portion between sidewalls of the recessed portion,
wherein the dielectric material layer laterally surrounds and directly contacts sidewalls of the phase change material,
9. The memory of claim 8, wherein the pore has tapered sidewalls.
10. The memory of claim 8, wherein the pore has vertical sidewalls.
11. The memory of claim 8, wherein the recessed portion has vertical sidewalls.
12. The memory of claim 8, wherein the recessed portion has curved sidewalls.
a first electrode including a first electrode material layer and a second electrode material layer, the first electrode material layer comprising a recessed portion extending through the first electrode material layer;
a resistivity changing material filling the recessed portion and directly contacting the first electrode material layer and a top surface of the second electrode material layer, the resistivity changing material coupled to the second electrode.
a dielectric material laterally surrounding and directly contacting sidewalls of the resistivity changing material.
15. The integrated circuit of claim 14, wherein the recessed portion comprises vertical sidewalls, and
wherein the dielectric material comprises tapered sidewalls.
16. The integrated circuit of claim 13, wherein a thermal conductivity of the first electrode material layer is less than a thermal conductivity of the second electrode material layer, and
a phase change material filling the recessed portion and directly contacting sidewalls of the first electrode material layer and a top surface of the second electrode material layer;
a dielectric material comprising sidewalls directly contacting the phase change material; and
a second electrode directly contacting a top surface of the phase change material.
18. The memory of claim 17, wherein the sidewalls of the first electrode material layer comprise vertical sidewalls, and
wherein the sidewalls of the dielectric material comprise tapered sidewalls.
19. The memory of claim 17, wherein a thermal conductivity of the first electrode material layer is less than a thermal conductivity of the second electrode material layer, and
wherein a resistivity of the first electrode material layer is greater than a resistivity of the second electrode material layer. Description
A phase change memory including a memory array having a plurality of memory cells that are made of phase change material may be programmed to store data utilizing the memory states of the phase change material. One way to read and write data in such a phase change memory device is to control a current and/or a voltage pulse that is applied to the phase change material. The temperature in the phase change material in each memory cell generally corresponds to the applied level of current and/or voltage to achieve the heating. The power used to program a memory cell is based on the electrical and thermal interface between the phase change material and at least one electrode contacting the phase change material.
To achieve higher density phase change memories, a phase change memory cell can store multiple bits of data. Multi-bit storage in a phase change memory cell can be achieved by programming the phase change material to have intermediate resistance values or states, where the multi-bit or multilevel phase change memory cell can be written to more than two states. If the phase change memory cell is programmed to one of three different resistance levels, 1.5 bits of data per cell can be stored. If the phase change memory cell is programmed to one of four different resistance levels, two bits of data per cell can be stored, and so on. To program a phase change memory cell to an intermediate resistance value, the amount of crystalline material coexisting with amorphous material and hence the cell resistance is controlled via a suitable write strategy. For both single bit and multi-bit applications, process fluctuations between the individual cells should be minimized.
One embodiment provides an integrated circuit. The integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode.
FIG. 3A illustrates a cross-sectional view of one embodiment of a phase change memory cell.
FIG. 4A illustrates a cross-sectional view of one embodiment of a phase change memory cell including an indication of current density.
FIG. 4B illustrates a cross-sectional view of one embodiment of a phase change memory cell including an indication of heat loss.
FIG. 4C illustrates a cross-sectional view of one embodiment of a phase change memory cell including an indication of an active region.
FIG. 5B illustrates a cross-sectional view of another embodiment of a preprocessed wafer.
FIG. 6 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, a first dielectric material layer, a second dielectric material layer, and a third dielectric material layer.
FIG. 7 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, the first dielectric material layer, the second dielectric material layer, and the third dielectric material layer after etching the third dielectric material layer and the second dielectric material layer.
FIG. 8 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, the first dielectric material layer, the second dielectric material layer, and the third dielectric material layer after etching the second dielectric material layer.
FIG. 9 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, the first dielectric material layer, the second dielectric material layer, the third dielectric material layer, and a keyhole formed in a polysilicon layer.
FIG. 10 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, the first dielectric material layer, the second dielectric material layer, and the polysilicon layer after etching the polysilicon layer and the first dielectric material layer.
FIG. 11 illustrates a cross-sectional view of one embodiment of the preprocessed wafer and the first dielectric material layer after removing the polysilicon layer and the second dielectric material layer.
FIG. 12A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, the first dielectric material layer, and a bottom electrode including a recessed portion.
FIG. 12B illustrates a cross-sectional view of one embodiment of a preprocessed wafer, the first dielectric material layer, and a bottom electrode including a recessed portion.
FIG. 13 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, the first dielectric material layer, the bottom electrode including the recessed portion, and a phase change material layer.
FIG. 14 is a chart illustrating one embodiment of the relationship between the reset current and the bottom electrode recess for a phase change memory cell.
FIG. 15 is a chart illustrating another embodiment of the effect of process variations on a phase change memory cell.
FIG. 16 is a chart illustrating another embodiment of the effect of process variations on a phase change memory cell.
Each of the memory cells 106 a-106 d is a recessed pore memory cell. A pore is formed in a dielectric material and then recessed into a first electrode. The recessed pore is filled with resistivity changing material or phase change material, which contacts the first electrode and a second electrode. The cross-section of the recessed pore and the depth of the recess in the first electrode define the current through each memory cell and the power used to reset each memory cell. In one embodiment, the pore is formed by first using a keyhole process to define an initial opening in a dielectric material layer and then by etching a recess into the first electrode.
Controller 118 controls the operation of write circuit 102, sense circuit 108, and distribution circuit 104. Controller 118 includes a microprocessor, microcontroller, or other suitable logic circuitry for controlling the operation of write circuit 102, sense circuit 108, and distribution circuit 104. Controller 118 controls write circuit 102 for setting the resistance states of memory cells 106 a-106 d. Controller 118 controls sense circuit 108 for reading the resistance states of memory cells 106 a-106 d. Controller 118 controls distribution circuit 104 for selecting memory cells 106 a-106 d for read or write access. In one embodiment, controller 118 is embedded on the same chip as memory cells 106 a-106 d. In another embodiment, controller 118 is located on a separate chip from memory cells 106 a-106 d. In one embodiment, write circuit 102 provides voltage pulses to distribution circuit 104 through signal path 110, and distribution circuit 104 controllably directs the voltage pulses to memory cells 106 a-106 d through signal paths 112 a-112 d. In another embodiment, write circuit 102 provides current pulses to distribution circuit 104 through signal path 110, and distribution circuit 104 controllably directs the current pulses to memory cells 106 a-106 d through signal paths 112 a-112 d. In one embodiment, distribution circuit 104 includes a plurality of transistors that controllably direct the voltage pulses or the current pulses to each of the memory cells 106 a-106 d. Sense circuit 108 reads each of the two or more states of memory cells 106 a-106 d through signal path 114. Distribution circuit 104 controllably directs read signals between sense circuit 108 and memory cells 106 a-106 d through signal paths 112 a-112 d. In one embodiment, distribution circuit 104 includes a plurality of transistors that controllably direct read signals between sense circuit 108 and memory cells 106 a-106 d. In one embodiment, to read the resistance of one of the memory cells 106 a-106 d, sense circuit 108 provides current that flows through one of the memory cells 106 a-106 d and sense circuit 108 reads the voltage across that one of the memory cells 106 a-106 d. In another embodiment, sense circuit 108 provides voltage across one of the memory cells 106 a-106 d and reads the current that flows through that one of the memory cells 106 a-106 d. In another embodiment, write circuit 102 provides voltage across one of the memory cells 106 a-106 d and sense circuit 108 reads the current that flows through that one of the memory cells 106 a-106 d. In another embodiment, write circuit 102 provides current through one of the memory cells 106 a-106 d and sense circuit 108 reads the voltage across that one of the memory cells 106 a-106 d. To program a memory cell 106 a-106 d within memory device 100, write circuit 102 generates one or more current or voltage pulses for heating the phase change material in the target memory cell. In one embodiment, write circuit 102 generates appropriate current or voltage pulses, which are fed into distribution circuit 104 and distributed to the appropriate target memory cell 106 a-106 d. The amplitude and duration of the current or voltage pulses are controlled depending on whether the memory cell is being set or reset. Generally, a “set” operation of a memory cell is heating the phase change material of the target memory cell above its crystallization temperature (but usually below its melting temperature) long enough to achieve the crystalline state or a partially crystalline and partially amorphous state. Generally, a “reset” operation of a memory cell is heating the phase change material of the target memory cell above its melting temperature, and then quickly quench cooling the material, thereby achieving the amorphous state or a partially amorphous and partially crystalline state.
FIG. 3A illustrates a cross-sectional view of one embodiment of a phase change memory cell 200 a. In one embodiment, each of the phase change memory cells 106 a-106 d is similar to phase change memory cell 200 a. Phase change memory cell 200 a includes a first electrode 202, a dielectric material layer 204, a phase change material 208, and a second electrode 210. First electrode 202 contacts dielectric material layer 204 and phase change material 208. Phase change material 208 contacts second electrode 210. Dielectric material layer 204 and bottom electrode 202 define a recessed pore into which phase change material 208 is deposited. The recessed pore includes a recessed portion 207 defined by a recess in bottom electrode 202 and a pore portion 209 defined by a pore or opening in dielectric material layer 204. In one embodiment, the depth of recessed portion 207 is greater than approximately 10% of the critical dimension of the bottom of pore portion 209. In another embodiment, the depth of recessed portion 207 is within a range between approximately 30-70% of the critical dimension of the bottom of pore portion 209.
In one embodiment, recessed portion 207 has vertical sidewalls. In other embodiments, recessed portion 207 has curved sidewalls. In one embodiment, pore portion 209 has tapered sidewalls. In other embodiments, pore portion 209 has vertical sidewalls. In one embodiment, recessed portion 207 and the top and bottom of pore portion 209 have sublithographic cross-sections. First electrode 202 and second electrode 210 include any suitable electrode material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, C, or Cu. Dielectric material layer 204 includes any suitable dielectric material, such as SiN.
Phase change material 208 may be made up of a variety of materials in accordance with the present invention. Generally, chalcogenide alloys that contain one or more elements from group VI of the periodic table are useful as such materials. In one embodiment, phase change material 208 of phase change memory cell 200 a is made up of a chalcogenide compound material, such as GeSbTe, SbTe, GeTe, or AgInSbTe. In another embodiment, phase change material 208 is chalcogen free, such as GeSb, GaSb, InSb, or GeGaInSb. In other embodiments, phase change material 208 is made up of any suitable material including one or more of the elements Ge, Sb, Te, Ga, As, In, Se, and S.
Phase change material 208 provides a storage location for storing one or more bits of data. Read and write signals are provided to phase change material 208 via first electrode 202 and second electrode 210. During a write operation, the current path through phase change material 208 is from one of first electrode 202 and second electrode 210 through recessed portion 207 and pore portion 209 and to the other of first electrode 202 and second electrode 210.
FIG. 3B illustrates a cross-sectional view of another embodiment of a phase change memory cell 200 b. In one embodiment, each of the phase change memory cells 106 a-106 d is similar to phase change memory cell 200 b. Phase change memory cell 200 b is similar to phase change memory cell 200 a previously described and illustrated with reference to FIG. 3A, except that first electrode 202 of phase change memory cell 200 b includes a first electrode material 201 and a second electrode material 206. In this embodiment, first portion 207 of the recessed pore is defined by second electrode material 206. The thickness or height of second electrode material 206 defines the depth of the recessed portion 207. In one embodiment, the thickness of second electrode material 206 is greater than approximately 10% of the critical dimension of the bottom of pore portion 209. In another embodiment, the thickness of second electrode material 206 is within a range between approximately 30-70% of the critical dimension of the bottom of pore portion 209.
First electrode material 201 includes any suitable electrode material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, C, or Cu. Second electrode material 206 includes any suitable electrode material different than first electrode material 201, such as dielectric doped phase change material, TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, C, or Cu. In one embodiment, the thermal conductivity of second electrode material 206 is less than the thermal conductivity of first electrode material 201. In one embodiment, the resistivity of second electrode material 206 is greater than the resistivity of first electrode material 201.
FIG. 4A illustrates a cross-sectional view of one embodiment of phase change memory cell 200 a including an indication of current density. FIG. 4A is also applicable to phase change memory cell 200 b. As indicated at 203, current flows from both the bottom and sidewalls of first electrode 202 of recessed portion 207 into phase change material 208. Recessed portion 207 increases the current density through phase change material 208 compared to a pore memory cell not having a recessed portion 207. The current density is increased at the interface between recessed portion 207 and pore portion 209. By increasing the current density, the current used to reset the memory cell to an amorphous state is reduced.
FIG. 4B illustrates a cross-sectional view of one embodiment of phase change memory cell 200 a including an indication of heat loss. FIG. 4B is also applicable to phase change memory cell 200 b. As indicated at 205, heat flows from phase change material 208 to the sidewalls of first electrode 202 of recessed portion 207. Recessed portion 207 reduces the heat loss from phase change material 208 to bottom electrode 202 compared to a pore memory cell not having a recessed portion 207. By reducing the heat loss, the current used to reset the memory cell to an amorphous state is reduced.
FIG. 4C illustrates a cross-sectional view of one embodiment of phase change memory cell 200 a including an indication of an active region. FIG. 4C is also applicable to phase change memory cell 200 b. Due to the current density increase and the reduction in heat loss as previously described and illustrated with reference to FIGS. 4A and 4B, the hot spot, which defines the active or phase change region in phase change material 208, is indicated at 211. The active region 211 is closer to the bottom of pore portion 209 compared to a pore memory cell not having a recessed portion 207. By moving the active region 211 closer to the bottom of pore portion 209, the current and power used to reset the memory cell to an amorphous state is reduced. In addition, by moving the active region 211 closer to the bottom of pore portion 209, fabrication process variations have a smaller effect on the current and power used to reset the memory cell to the amorphous state.
The following FIGS. 5A-13 illustrate embodiments of a process for fabricating phase change memory cells 200 a and 200 b previously described and illustrated with reference to FIGS. 3A and 3B.
FIG. 5A illustrates a cross-sectional view of one embodiment of a preprocessed wafer 212. Preprocessed wafer 212 includes a dielectric material 214, a first electrode 202 a, and lower wafer layers (not shown). Dielectric material 214 includes SiO2, SiOx, SiN, fluorinated silica glass (FSG), boro-phosphorus silicate glass (BPSG), boro-silicate glass (BSG), or other suitable dielectric material. First electrode 202 a includes TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, C, Cu, or other suitable electrode material. Dielectric material 214 laterally surrounds first electrode 202 a and isolates first electrode 202 a from adjacent device features.
FIG. 5B illustrates a cross-sectional view of another embodiment of a preprocessed wafer 213. Preprocessed wafer 213 is similar to preprocessed wafer 212 previously described and illustrated with reference to FIG. 5A, except that first electrode 202 a of preprocessed wafer 213 includes a first electrode material layer 201 and a second electrode material layer 206 a. Second electrode material layer 206 a contacts the top of first electrode material layer 201. Dielectric material 214 laterally surrounds first electrode material layer 201 and second electrode material layer 206 a and isolates first electrode 202 a from adjacent device features. The thickness of second electrode material layer 206 a defines the depth of recessed portion 207 in subsequent fabrication processes.
First electrode material layer 201 includes any suitable electrode material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, C, or Cu. Second electrode material layer 206 a includes any suitable electrode material different than first electrode material layer 201, such as dielectric doped phase change material, TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, C, or Cu. In one embodiment, the thermal conductivity of second electrode material layer 206 a is less than the thermal conductivity of first electrode material layer 201. In one embodiment, the resistivity of second electrode material layer 206 a is greater than the resistivity of first electrode material layer 201.
FIG. 6 illustrates a cross-sectional view of one embodiment of preprocessed wafer 212, a first dielectric material layer 204 a, a second dielectric material layer 216 a, and a third dielectric material layer 218 a. A dielectric material, such as SiN or another suitable dielectric material is deposited over preprocessed wafer 212 to provide first dielectric material layer 204 a. First dielectric material layer 204 a is deposited using chemical vapor deposition (CVD), high density plasma-chemical vapor deposition (HDP-CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), plasma vapor deposition (PVD), jet vapor deposition (JVD), or other suitable deposition technique.
A third dielectric material, such as SiN or another suitable dielectric material is deposited over second dielectric material layer 216 a to provide third dielectric material layer 218 a. In one embodiment, this third dielectric material layer is similar to the dielectric material of dielectric material layer 204 a. Third dielectric material layer 218 a is thinner than second dielectric material layer 216 a. In one embodiment, third dielectric material layer 218 a has substantially the same thickness as first dielectric material layer 204 a. Third dielectric material layer 218 a is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique.
FIG. 7 illustrates a cross-sectional view of one embodiment of preprocessed wafer 212, first dielectric material layer 204 a, second dielectric material layer 216 b, and third dielectric material layer 218 b after etching third dielectric material layer 218 a and second dielectric material layer 216 a. Third dielectric material layer 218 a and second dielectric material layer 216 a are etched to provide opening 220 exposing first dielectric material layer 204 a and to provide second dielectric material layer 216 b and third dielectric material layer 218 b. In one embodiment, opening 220 is substantially centered over first electrode 202 a. FIG. 8 illustrates a cross-sectional view of one embodiment of preprocessed wafer 212, first dielectric material layer 204 a, second dielectric material layer 216 c, and third dielectric material layer 218 b after etching second dielectric material layer 216 b. Second dielectric material layer 216 b is selectively recess etched using a selective wet etch or other suitable etch to create overhang of third dielectric material layer 218 b as indicated at 222.
FIG. 9 illustrates a cross-sectional view of one embodiment of preprocessed wafer 212, first dielectric material layer 204 a, second dielectric material layer 216 c, third dielectric material layer 218 b, and a keyhole 226 formed in a polysilicon layer 224 a. Polysilicon or another suitable material is conformally deposited over exposed portions of third dielectric material layer 218 b, second dielectric material layer 216 c, and first dielectric material layer 204 a. Due to overhang 222, the conformal deposition of polysilicon pinches itself off forming a void or keyhole 226. Keyhole 226 is substantially centered over first electrode 202 a. Polysilicon layer 224 a is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique.
FIG. 10 illustrates a cross-sectional view of one embodiment of preprocessed wafer 212, first dielectric material layer 204, second dielectric material layer 216 c, and polysilicon layer 224 b after etching polysilicon layer 224 a and first dielectric material layer 204 a. Third dielectric material layer 218 b is removed. Polysilicon layer 224 a is etched to expose keyhole 226. Keyhole 226 is then transferred into first dielectric material layer 204 a as indicated by opening 228 to provide polysilicon layer 224 b and first dielectric material layer 204. In one embodiment, opening or pore 228 has a sublithographic cross-section such that the exposed portion of first electrode 202 a has a sublithographic cross-section.
FIG. 11 illustrates a cross-sectional view of one embodiment of preprocessed wafer 212 and first dielectric material layer 204 after removing polysilicon layer 224 b and second dielectric material layer 216 c. Second dielectric material layer 216 c and polysilicon layer 224 b are etched to expose first dielectric material layer 204. In one embodiment, opening 228 provides pore portion 209 and has vertical sidewalls. In another embodiment, opening 228 has tapered sidewalls.
FIG. 12A illustrates a cross-sectional view of one embodiment of preprocessed wafer 212, first dielectric material layer 204, and bottom electrode 202 including a recessed portion 207. The exposed portion of first electrode 202 a is etched to provide recessed portion 207 and bottom electrode 202. In one embodiment, pore portion 209 and recessed portion 207 are etched using a single etching process. In another embodiment, a two step etching process is used. In the two step etching process, a first selective etching process is used to provide pore portion 209 and a second selective etching process is used to provide recessed portion 207.
In one embodiment, bottom electrode 202 a is etched to a depth greater than approximately 10% of the critical dimension of the bottom of pore portion 209 to provide recessed portion 207. In another embodiment, bottom electrode 202 a is etched to a depth within a range between approximately 30-70% of the critical dimension of the bottom of pore portion 209. In one embodiment, bottom electrode 202 a is etched to provide a recessed portion 207 having vertical sidewalls. In other embodiments, bottom electrode 202 a is etched to provide a recessed portion 207 having curved sidewalls.
FIG. 12B illustrates a cross-sectional view of one embodiment of preprocessed wafer 213, first dielectric material layer 204, and bottom electrode 202 including a recessed portion 207. In this embodiment, the exposed portion of second electrode material layer 206 a (FIG. 5B) is etched to expose first electrode material layer 201 to provide recessed portion 207 and bottom electrode 202. In one embodiment, pore portion 209 and recessed portion 207 are etched using a single etching process. In another embodiment, a two step etching process is used. In the two step etching process, a first selective etching process is used to provide pore portion 209 and a second selective etching process is used to provide recessed portion 207.
In this embodiment, the thickness of second electrode material layer 206 a defines the depth of recessed portion 207. In one embodiment, the depth of recessed portion 207 is greater than approximately 10% of the critical dimension of the bottom of pore portion 209. In another embodiment, the depth of recessed portion 207 is within a range between approximately 30-70% of the critical dimension of the bottom of pore portion 209. In one embodiment, second electrode material layer 206 a is etched to provide a recessed portion 207 having vertical sidewalls. In other embodiments, second electrode material layer 206 a is etched to provide a recessed portion 207 having curved sidewalls.
FIG. 13 illustrates a cross-sectional view of one embodiment of preprocessed wafer 212, first dielectric material layer 204, bottom electrode 202 including recessed portion 207, and a phase change material 208. A phase change material, such as a chalcogenide compound material or other suitable phase change material is deposited over exposed portions of dielectric material layer 204 and first electrode 202 to provide phase change material 208. Phase change material 208 is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique.
An electrode material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, C, Cu, or other suitable electrode material is deposited over phase change material 208 to provide second electrode 210 and phase change memory cell 200 a as previously described and illustrated with reference to FIG. 3A. The electrode material is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. In another embodiment, where preprocessed wafer 213 is used in place of preprocessed wafer 212, phase change memory cell 200 b as previously described and illustrated with reference to FIG. 3B is fabricated.
FIG. 14 is a chart 300 illustrating one embodiment of the relationship between the reset current and the bottom electrode recess for a phase change memory cell. Chart 300 includes the bottom electrode recess divided by the critical dimension on x-axis 302 and normalized reset current (i.e., the reset current for a recessed pore memory cell divided by the reset current for a pore memory cell without a bottom electrode recess) on y-axis 304. Curve 306 illustrates simulation data for a recessed pore having vertical pore sidewalls. Curve 308 illustrates simulation data for a recessed pore having 60° pore sidewalls and a pore bottom critical dimension of 40 nm. Curve 310 illustrates simulation data for a recessed pore having 60° pore sidewalls and a pore bottom critical dimension of 20 nm.
As illustrated by chart 300, the reset current decreases in response to an increase in the bottom electrode recess. The decrease in reset current is exhibited for both a recessed pore having vertical sidewalls and tapered sidewalls, although the decrease in reset current is more pronounced for a recessed pore having tapered sidewalls. The decrease in reset current is also independent of the bottom critical dimension of the pore as indicated by the similarity between curve 308 and 310. As illustrated by chart 300, by recessing the bottom electrode by an amount equal to approximately 20% of the bottom critical dimension of the pore, the reset current is reduced by approximately 8%. The decrease in reset current is exhibited by memory cells including bottom electrode recesses having vertical sidewalls and bottom electrode recesses having curved sidewalls.
FIG. 15 is a chart 360 illustrating another embodiment of the effect of process variations on a phase change memory cell. Chart 360 includes bottom electrode recess in nanometers on x-axis 322 and reset current in microamps on y-axis 324. Curve 362 illustrates simulation data for a recessed pore having a pore top critical dimension of 35 nm and a pore bottom critical dimension of 20 nm.
In one embodiment, the process variation for etching the recess in the bottom electrode is +/−2.5 nm. As illustrated by chart 360, the reset current of a memory cell may vary by up to approximately 9.3% as indicated at 364 for a target recess of 2.5 nm. For a target recess of 7.5 nm, the reset current of a memory cell may vary by up to approximately 2.1% as indicated at 366. Therefore, by increasing the target depth of the recess in the bottom electrode, the reset current variation of a memory cell can be reduced from 9.3% to 2.1%, thus improving the manufacturability of the memory cell.
FIG. 16 is a chart 370 illustrating another embodiment of the effect of process variations on a phase change memory cell. Chart 370 includes bottom electrode recess in nanometers on x-axis 322 and reset power in milliwatts on y-axis 352. Curve 370 illustrates simulation data for a recessed pore having a pore top critical dimension of 35 nm and a pore bottom critical dimension of 20 nm.
In one embodiment, the process variation for etching the recess in the bottom electrode is +/−2.5 nm. As illustrated by chart 370, the reset power of a memory cell may vary by up to approximately 7.5% as indicated at 374 for a target recess of 2.5 nm. For a target recess of 7.5 nm, the reset power of a memory cell may vary by up to approximately 2.9% as indicated at 376.
Therefore, by increasing the target depth of the recess in the bottom electrode, the reset power variation of a memory cell can be reduced from 7.5% to 2.9%, thus improving the manufacturability of the memory cell.
Embodiments provide a phase change memory cell having a recessed pore into which phase change material is deposited. In one embodiment, the pore is defined using a keyhole process and then further recessed into an electrode. The recess in the electrode improves the current density and the thermal insulation of the active region of the memory cell and reduces both the current and power used to program the memory cell. The recess also reduces the variation in the reset current and power used to program the memory cell due to fabrication process variations.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6791102 *Dec 13, 2002Sep 14, 2004Intel CorporationPhase change memoryUS7067837Mar 31, 2004Jun 27, 2006Samsung Electronics Co., Ltd.Phase-change memory devicesUS20050045915 *Oct 24, 2003Mar 3, 2005Se-Ho LeePhase changeable layers including protruding portions in electrodes thereof and methods of forming sameUS20060211165 *Apr 28, 2006Sep 21, 2006Young-Nam HwangMethods for forming phase-change memory devicesUS20060246712 *Dec 19, 2005Nov 2, 2006Stmicroelectronics S.R.I.Dual resistance heater for phase change devices and manufacturing method thereofUS20070025226Jul 20, 2006Feb 1, 2007Park Young SPhase change memory device and method of manufacturing the sameUS20070164266 *Dec 27, 2006Jul 19, 2007Dongbu Electronics Co., Ltd.Semiconductor device and method of manufacturing the sameUS20070205406 *May 9, 2007Sep 6, 2007Taiwan Semiconductor Manufacturing Company, Ltd.Phase Change Memory Device and Method of Manufacture ThereofUS20080054323 *Aug 29, 2006Mar 6, 2008International Business Machines CorporationThin film phase change memory cell formed on silicon-on-insulator substrate* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8395192Jan 11, 2011Mar 12, 2013International Business Machines CorporationSingle mask adder phase change memory elementUS8415653Mar 14, 2012Apr 9, 2013International Business Machines CorporationSingle mask adder phase change memory elementUS8471236Jul 16, 2012Jun 25, 2013International Business Machines CorporationFlat lower bottom electrode for phase change memory cellUS8492194 *May 6, 2011Jul 23, 2013International Business Machines CorporationChemical mechanical polishing stop layer for fully amorphous phase change memory pore cellUS9059394Feb 9, 2012Jun 16, 2015International Business Machines CorporationSelf-aligned lower bottom electrodeUS20110121252 *Jan 11, 2011May 26, 2011International Business Machines CorporationSingle mask adder phase change memory elementUS20110210307 *May 6, 2011Sep 1, 2011International Business Machines CorporationChemical mechanical polishing stop layer for fully amorphous phase change memory pore cell* Cited by examinerClassifications U.S. Classification365/163, 257/202, 438/95International ClassificationG11C11/00Cooperative ClassificationG11C13/0004, G11C8/10European ClassificationG11C13/00R1Legal EventsDateCodeEventDescriptionAug 6, 2008ASAssignmentOwner name: MACRONIX INTERNATIONAL CO., LTD., TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, SHIHHUNG;REEL/FRAME:021344/0296Effective date: 20080107Owner name: QIMONDA NORTH AMERICA CORP., NORTH CAROLINAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HAPP, THOMAS;REEL/FRAME:021344/0329Effective date: 20071220Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BREITWISCH, MATTHEW J.;JOSEPH, ERIC;REEL/FRAME:021344/0369;SIGNING DATES FROM 20071220 TO 20080104Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BREITWISCH, MATTHEW J.;JOSEPH, ERIC;SIGNING DATES FROM 20071220 TO 20080104;REEL/FRAME:021344/0369Apr 18, 2011ASAssignmentOwner name: QIMONDA AG, GERMANYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA NORTH AMERICA CORP.;REEL/FRAME:026144/0905Effective date: 20110221May 8, 2015ASAssignmentOwner name: INFINEON TECHNOLOGIES AG, GERMANYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001Effective date: 20141009Jan 8, 2016REMIMaintenance fee reminder mailedMar 24, 2016ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: CONFIRMATORY PATENT ASSIGNMENT;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:038238/0941Effective date: 20151231May 2, 2016SULPSurcharge for late paymentMay 2, 2016FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services