Source: http://www.google.com/patents/US7761066?dq=oakley+5,387,949&ei=4yI4T8nkLYa80QG0xqnWAg
Timestamp: 2017-09-25 07:24:43
Document Index: 238825869

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 07', 'Application No. 07', 'art 11', 'art 11', 'art 11', 'art 11', 'art 16']

Patent US7761066 - Variable power adaptive transmitter - Google Patents
A circuit comprises an analog output module that receives a bias signal and a control signal. A delay module receives a first signal and that generates a delayed first signal. A control module receives the delayed first signal and generates the control signal based thereon. An envelope generating module...http://www.google.com/patents/US7761066?utm_source=gb-gplus-sharePatent US7761066 - Variable power adaptive transmitter
Publication number US7761066 B2
Application number US 11/649,658
Also published as EP1814220A1, EP1814220B1, US20070178854
Publication number 11649658, 649658, US 7761066 B2, US 7761066B2, US-B2-7761066, US7761066 B2, US7761066B2
Patent Citations (18), Non-Patent Citations (16), Referenced by (2), Classifications (10), Legal Events (1)
Variable power adaptive transmitter
US 7761066 B2
an analog output module that receives a bias signal and a control signal;
a delay module that receives a first signal and that generates a delayed first signal;
a control module that receives said delayed first signal and that generates said control signal based thereon; and
an envelope generating module that receives a second signal including amplitude information related to said first signal,
wherein said envelope generating module generates an envelope signal to selectively increase said bias signal to said analog output module when said first signal exceeds a voltage supply reference and before a corresponding portion of said first signal is received by said analog output module,
wherein said envelope generating module selectively increases voltage of said bias signal to a voltage level that is greater than or equal to a voltage level of said envelope signal when said envelope signal exceeds said voltage supply reference, and
a switch that is connected to said analog output module and that receives said voltage supply reference; and
a capacitance that is connected between a first digital to analog converter and said switch.
2. The circuit of claim 1, wherein said first signal includes a digital modulated carrier signal.
3. The circuit of claim 2, further comprising a rectifier module that rectifies said digital modulated carrier signal and that outputs said rectified modulated carrier signal to said envelope generating module.
4. The circuit of claim 2, wherein said delay circuit delays said modulated carrier signal and further comprising an upconverter that upconverts said delayed modulated carrier signal.
5. The circuit of claim 1, further comprising a digital to analog converter that converts said envelope signal to an analog envelope signal.
6. The circuit of claim 1, wherein said envelope signal has a slower rise time than a fastest rise time of said first signal.
7. The circuit of claim 1, wherein said analog output module comprises a power amplifier.
8. The circuit of claim 1, wherein said control module includes a transmitter module.
9. The circuit of claim 1, further comprising an inductance that communicates with said analog output module and said capacitance,
said switch communicates with a first reference voltage and is controlled by said envelope generating module; and
said capacitance communicates with an output of said envelope generating module and said switch.
a matching network that communicates with said analog output module; and
an antenna that communicates with said matching network.
11. The circuit of claim 1, wherein said envelope generating module receives said first signal and generates said envelope signal based on said first signal.
12. The circuit of claim 1, wherein said envelope generating module supplies said bias signal,
wherein said envelop generating module sets said bias signal equal to said voltage supply reference when said voltage level of said envelope signal is less than said voltage supply reference, and
wherein said envelop generating module sets said bias signal equal to a voltage level that is greater than or equal to said voltage level of said envelope signal when said voltage level of said envelope signal is greater than said voltage supply reference.
13. The circuit of claim 1, wherein said switch is in a first state when said control module biases said analog output module with said voltage supply reference, and
wherein said switch is in a second state when said control module biases said analog output module with said voltage level that is greater than said voltage level of said envelope signal.
14. The circuit of claim 1, wherein said switch is directly connected to said capacitance.
15. The circuit of claim, wherein said switch and said capacitance are directly connected to said analog output module.
16. The circuit of claim 1, wherein said capacitance is directly connected to said first digital to analog converter.
analog output means for receiving a bias signal and a control signal;
delay means for receiving a first signal and for generating a delayed first signal;
control means for receiving said delayed first signal and for generating said control signal based thereon; and
envelope generating means for receiving a second signal including amplitude information related to said first signal and for generating an envelope signal to selectively increase said bias signal to said analog output means when said first signal exceeds a voltage supply reference and before a corresponding portion of said first signal is received by said analog output means,
wherein said envelope generating means selectively increases voltage of said bias signal to a voltage level that is greater than or equal to a voltage level of said envelope signal when said envelope signal exceeds said voltage supply reference, and
18. The circuit of claim 17, wherein said first signal includes a digital modulated carrier signal.
19. The circuit of claim 18, further comprising rectifier means for rectifying said digital modulated carrier signal and for outputting said rectified digital modulated carrier signal to said envelope generating means.
20. The circuit of claim 18, wherein said delay means delays said modulated carrier signal and further comprising upconverting means for upconverting said delayed modulated carrier signal.
21. The circuit of claim 17, further comprising digital to analog converting means for converting said envelope signal to an analog envelope signal.
22. The circuit of claim 17, wherein said envelope signal has a slower rise time than a fastest rise time of said first signal.
23. The circuit of claim 17, wherein said analog output means comprises power amplifying means for amplifying.
24. The circuit of claim 17, wherein said control means includes transmitting means for transmitting.
25. The circuit of claim 17, further comprising inductance means for providing inductance and that communicates with said capacitance means and said analog output means,
said switching means communicates with a first reference voltage and is controlled by said envelope generating means;
said capacitance means communicates with an output of said envelope generating means and said switching means.
26. The circuit of claim further comprising:
matching network means for matching that communicates with said analog output means; and
an antenna that communicates with said matching network means.
27. The circuit of claim 17, wherein said envelope generating means receives said first signal and generates said envelope signal based on said first signal.
a first switch that is connected to said analog output module and that receives said voltage supply reference at a first polarity;
a second switch that is connected to said analog output module and that receives said voltage supply reference at a second polarity;
a first capacitance that is connected between a first digital to analog converter and said first switch; and
a second capacitance that is connected between a second digital to analog converter and said second switch.
This application is a continuation of U.S. patent application Ser. No. 11/368,308 filed on Mar. 3, 2006, which application claims the benefit of U.S. Provisional Application No. 60/773,033 filed on Feb. 14, 2006, and U.S. Provisional Application No. 60/763,041, filed on Jan. 27, 2006. The disclosures of the above applications are hereby incorporated by reference in their entirety.
The present invention relates to communication systems, and more particularly to transmitters in network interfaces and other devices.
Referring now to FIG. 1, an exemplary network 10 is shown to include one or more wireless network devices 20-1, 20-2, . . . , and 20-X (collectively wireless network devices 20) and/or one or more wired network devices 24-1, 24-2, . . . , and 24-Y (collectively wired network devices 24). The wireless network devices 20 wirelessly communicate data packets with an access point 30. The wired network devices 24 communicate data packets over cable, fiber or other media with a router 40. The access point 30 also communicates with the router 40. The router 40, in turn, communicates with a broadband modem 44, which communicates with a service provider 48. The service provider 48, in turn, provides access to a distributed communications network 50 such as the Internet.
A circuit comprises a delay module that receives a digital transmit signal and that generates a delayed transmit signal. A first digital to analog converter converts the delayed transmit signal to an analog transmit signal. An analog output circuit amplifies the analog transmit signal. An envelope generating module generates an envelope signal based on amplitude information related to the digital transmit signal. A supply adjustment module supplies a voltage supply reference when the envelope signal is less than a threshold and boosts the bias voltage of the amplifier above the voltage supply reference when the envelope signal is greater than the threshold.
FIG. 7B is an exemplary functional block diagram and electrical schematic of an asymmetrical supply adjustment module;
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U.S. Classification 455/127.1, 330/10
Cooperative Classification H03F2200/504, H03F1/0266, H03F3/24, H03F1/0222
European Classification H03F1/02T1C1, H03F3/24, H03F1/02T2E