Source: https://patents.google.com/patent/CN1228824C/en
Timestamp: 2020-07-14 22:58:15+00:00
Document Index: 58536891

Matched Legal Cases: ['art 103', 'art 103', 'art 103', 'art 103', 'art 103', 'art 103']

CN1228824C - Method for producing semiconductor device and semiconductor device - Google Patents
CN1228824C
CN1228824C CNB021002452A CN02100245A CN1228824C CN 1228824 C CN1228824 C CN 1228824C CN B021002452 A CNB021002452 A CN B021002452A CN 02100245 A CN02100245 A CN 02100245A CN 1228824 C CN1228824 C CN 1228824C
CNB021002452A
CN1365140A (en
真条直宽
2001-01-10 Priority to JP2001002152A priority Critical patent/JP3535461B2/en
2001-01-10 Priority to JP002152/2001 priority
2002-01-10 Application filed by 新光电气工业株式会社 filed Critical 新光电气工业株式会社
2002-08-21 Publication of CN1365140A publication Critical patent/CN1365140A/en
2005-11-23 Publication of CN1228824C publication Critical patent/CN1228824C/en
239000010408 films Substances 0.000 claims abstract description 283
239000011133 lead Substances 0.000 claims description 72
238000000227 grinding Methods 0.000 claims description 11
XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nMzAwcHgnIGhlaWdodD0nMzAwcHgnIHZpZXdCb3g9JzAgMCAzMDAgMzAwJz4KPCEtLSBFTkQgT0YgSEVBREVSIC0tPgo8cmVjdCBzdHlsZT0nb3BhY2l0eToxLjA7ZmlsbDojRkZGRkZGO3N0cm9rZTpub25lJyB3aWR0aD0nMzAwJyBoZWlnaHQ9JzMwMCcgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJzdGFydCIgeD0nMTMyLjY1NScgeT0nMTU2JyBzdHlsZT0nZm9udC1zaXplOjQwcHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7ZmlsbDojM0I0MTQzJyA+PHRzcGFuPlNpPC90c3Bhbj48L3RleHQ+CjxwYXRoIGQ9J00gMzIuNzI3MywxMTMuNjM2IEwgMzIuNjk3LDExMi45MzMgTCAzMi42MDYzLDExMi4yMzUgTCAzMi40NTYsMTExLjU0NyBMIDMyLjI0NzEsMTEwLjg3NSBMIDMxLjk4MTIsMTEwLjIyMyBMIDMxLjY2MDMsMTA5LjU5NiBMIDMxLjI4NjYsMTA5IEwgMzAuODYzMSwxMDguNDM3IEwgMzAuMzkyOCwxMDcuOTE0IEwgMjkuODc5MiwxMDcuNDMyIEwgMjkuMzI2MSwxMDYuOTk2IEwgMjguNzM3NiwxMDYuNjEgTCAyOC4xMTgxLDEwNi4yNzYgTCAyNy40NzIxLDEwNS45OTYgTCAyNi44MDQ0LDEwNS43NzMgTCAyNi4xMjAxLDEwNS42MDcgTCAyNS40MjQsMTA1LjUwMiBMIDI0LjcyMTUsMTA1LjQ1NiBMIDI0LjAxNzcsMTA1LjQ3MiBMIDIzLjMxNzcsMTA1LjU0NyBMIDIyLjYyNjksMTA1LjY4MyBMIDIxLjk1MDMsMTA1Ljg3NyBMIDIxLjI5MjgsMTA2LjEyOSBMIDIwLjY1OTUsMTA2LjQzNiBMIDIwLjA1NDksMTA2Ljc5NyBMIDE5LjQ4MzYsMTA3LjIwOCBMIDE4Ljk0OTgsMTA3LjY2NyBMIDE4LjQ1NzMsMTA4LjE3IEwgMTguMDEsMTA4LjcxNCBMIDE3LjYxMSwxMDkuMjk0IEwgMTcuMjYzNCwxMDkuOTA2IEwgMTYuOTY5NywxMTAuNTQ2IEwgMTYuNzMyMSwxMTEuMjA5IEwgMTYuNTUyMywxMTEuODg5IEwgMTYuNDMxNywxMTIuNTgzIEwgMTYuMzcxMiwxMTMuMjg0IEwgMTYuMzcxMiwxMTMuOTg4IEwgMTYuNDMxNywxMTQuNjkgTCAxNi41NTIzLDExNS4zODMgTCAxNi43MzIxLDExNi4wNjQgTCAxNi45Njk3LDExNi43MjcgTCAxNy4yNjM0LDExNy4zNjcgTCAxNy42MTEsMTE3Ljk3OSBMIDE4LjAxLDExOC41NTkgTCAxOC40NTczLDExOS4xMDIgTCAxOC45NDk4LDExOS42MDUgTCAxOS40ODM2LDEyMC4wNjQgTCAyMC4wNTQ5LDEyMC40NzYgTCAyMC42NTk1LDEyMC44MzYgTCAyMS4yOTI4LDEyMS4xNDQgTCAyMS45NTAzLDEyMS4zOTYgTCAyMi42MjY5LDEyMS41OSBMIDIzLjMxNzcsMTIxLjcyNiBMIDI0LjAxNzcsMTIxLjgwMSBMIDI0LjcyMTUsMTIxLjgxNiBMIDI1LjQyNCwxMjEuNzcxIEwgMjYuMTIwMSwxMjEuNjY1IEwgMjYuODA0NCwxMjEuNSBMIDI3LjQ3MjEsMTIxLjI3NyBMIDI4LjExODEsMTIwLjk5NyBMIDI4LjczNzYsMTIwLjY2MyBMIDI5LjMyNjEsMTIwLjI3NiBMIDI5Ljg3OTIsMTE5Ljg0MSBMIDMwLjM5MjgsMTE5LjM1OSBMIDMwLjg2MzEsMTE4LjgzNSBMIDMxLjI4NjYsMTE4LjI3MyBMIDMxLjY2MDMsMTE3LjY3NiBMIDMxLjk4MTIsMTE3LjA1IEwgMzIuMjQ3MSwxMTYuMzk4IEwgMzIuNDU2LDExNS43MjYgTCAzMi42MDYzLDExNS4wMzggTCAzMi42OTcsMTE0LjM0IEwgMzIuNzI3MywxMTMuNjM2IEwgMjQuNTQ1NSwxMTMuNjM2IFonIHN0eWxlPSdmaWxsOiMwMDAwMDA7ZmlsbC1ydWxlOmV2ZW5vZGQ7ZmlsbC1vcGFjaXR5PTE7c3Ryb2tlOiMwMDAwMDA7c3Ryb2tlLXdpZHRoOjEwcHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MTsnIC8+CjxwYXRoIGQ9J00gMjgzLjYzNiwxMTMuNjM2IEwgMjgzLjYwNiwxMTIuOTMzIEwgMjgzLjUxNSwxMTIuMjM1IEwgMjgzLjM2NSwxMTEuNTQ3IEwgMjgzLjE1NiwxMTAuODc1IEwgMjgyLjg5LDExMC4yMjMgTCAyODIuNTY5LDEwOS41OTYgTCAyODIuMTk2LDEwOSBMIDI4MS43NzIsMTA4LjQzNyBMIDI4MS4zMDIsMTA3LjkxNCBMIDI4MC43ODgsMTA3LjQzMiBMIDI4MC4yMzUsMTA2Ljk5NiBMIDI3OS42NDcsMTA2LjYxIEwgMjc5LjAyNywxMDYuMjc2IEwgMjc4LjM4MSwxMDUuOTk2IEwgMjc3LjcxNCwxMDUuNzczIEwgMjc3LjAyOSwxMDUuNjA3IEwgMjc2LjMzMywxMDUuNTAyIEwgMjc1LjYzMSwxMDUuNDU2IEwgMjc0LjkyNywxMDUuNDcyIEwgMjc0LjIyNywxMDUuNTQ3IEwgMjczLjUzNiwxMDUuNjgzIEwgMjcyLjg1OSwxMDUuODc3IEwgMjcyLjIwMiwxMDYuMTI5IEwgMjcxLjU2OSwxMDYuNDM2IEwgMjcwLjk2NCwxMDYuNzk3IEwgMjcwLjM5MywxMDcuMjA4IEwgMjY5Ljg1OSwxMDcuNjY3IEwgMjY5LjM2NiwxMDguMTcgTCAyNjguOTE5LDEwOC43MTQgTCAyNjguNTIsMTA5LjI5NCBMIDI2OC4xNzMsMTA5LjkwNiBMIDI2Ny44NzksMTEwLjU0NiBMIDI2Ny42NDEsMTExLjIwOSBMIDI2Ny40NjEsMTExLjg4OSBMIDI2Ny4zNDEsMTEyLjU4MyBMIDI2Ny4yOCwxMTMuMjg0IEwgMjY3LjI4LDExMy45ODggTCAyNjcuMzQxLDExNC42OSBMIDI2Ny40NjEsMTE1LjM4MyBMIDI2Ny42NDEsMTE2LjA2NCBMIDI2Ny44NzksMTE2LjcyNyBMIDI2OC4xNzMsMTE3LjM2NyBMIDI2OC41MiwxMTcuOTc5IEwgMjY4LjkxOSwxMTguNTU5IEwgMjY5LjM2NiwxMTkuMTAyIEwgMjY5Ljg1OSwxMTkuNjA1IEwgMjcwLjM5MywxMjAuMDY0IEwgMjcwLjk2NCwxMjAuNDc2IEwgMjcxLjU2OSwxMjAuODM2IEwgMjcyLjIwMiwxMjEuMTQ0IEwgMjcyLjg1OSwxMjEuMzk2IEwgMjczLjUzNiwxMjEuNTkgTCAyNzQuMjI3LDEyMS43MjYgTCAyNzQuOTI3LDEyMS44MDEgTCAyNzUuNjMxLDEyMS44MTYgTCAyNzYuMzMzLDEyMS43NzEgTCAyNzcuMDI5LDEyMS42NjUgTCAyNzcuNzE0LDEyMS41IEwgMjc4LjM4MSwxMjEuMjc3IEwgMjc5LjAyNywxMjAuOTk3IEwgMjc5LjY0NywxMjAuNjYzIEwgMjgwLjIzNSwxMjAuMjc2IEwgMjgwLjc4OCwxMTkuODQxIEwgMjgxLjMwMiwxMTkuMzU5IEwgMjgxLjc3MiwxMTguODM1IEwgMjgyLjE5NiwxMTguMjczIEwgMjgyLjU2OSwxMTcuNjc2IEwgMjgyLjg5LDExNy4wNSBMIDI4My4xNTYsMTE2LjM5OCBMIDI4My4zNjUsMTE1LjcyNiBMIDI4My41MTUsMTE1LjAzOCBMIDI4My42MDYsMTE0LjM0IEwgMjgzLjYzNiwxMTMuNjM2IEwgMjc1LjQ1NSwxMTMuNjM2IFonIHN0eWxlPSdmaWxsOiMwMDAwMDA7ZmlsbC1ydWxlOmV2ZW5vZGQ7ZmlsbC1vcGFjaXR5PTE7c3Ryb2tlOiMwMDAwMDA7c3Ryb2tlLXdpZHRoOjEwcHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MTsnIC8+Cjwvc3ZnPgo= data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nODVweCcgaGVpZ2h0PSc4NXB4JyB2aWV3Qm94PScwIDAgODUgODUnPgo8IS0tIEVORCBPRiBIRUFERVIgLS0+CjxyZWN0IHN0eWxlPSdvcGFjaXR5OjEuMDtmaWxsOiNGRkZGRkY7c3Ryb2tlOm5vbmUnIHdpZHRoPSc4NScgaGVpZ2h0PSc4NScgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJzdGFydCIgeD0nMjUuMjQ2OCcgeT0nNDcuNzk1NScgc3R5bGU9J2ZvbnQtc2l6ZTozOHB4O2ZvbnQtc3R5bGU6bm9ybWFsO2ZvbnQtd2VpZ2h0Om5vcm1hbDtmaWxsLW9wYWNpdHk6MTtzdHJva2U6bm9uZTtmb250LWZhbWlseTpzYW5zLXNlcmlmO2ZpbGw6IzNCNDE0MycgPjx0c3Bhbj5TaTwvdHNwYW4+PC90ZXh0Pgo8cGF0aCBkPSdNIDguNzcyNzMsMTguMDQ1NSBMIDguNzY0MTUsMTcuODQ2MiBMIDguNzM4NDYsMTcuNjQ4NCBMIDguNjk1ODcsMTcuNDUzNSBMIDguNjM2NjksMTcuMjYzIEwgOC41NjEzNSwxNy4wNzgzIEwgOC40NzA0MSwxNi45MDA4IEwgOC4zNjQ1NSwxNi43MzE3IEwgOC4yNDQ1NCwxNi41NzI0IEwgOC4xMTEyOSwxNi40MjQgTCA3Ljk2NTc3LDE2LjI4NzYgTCA3LjgwOTA1LDE2LjE2NDIgTCA3LjY0MjMyLDE2LjA1NDcgTCA3LjQ2Njc4LDE1Ljk1OTkgTCA3LjI4Mzc2LDE1Ljg4MDcgTCA3LjA5NDU5LDE1LjgxNzQgTCA2LjkwMDY4LDE1Ljc3MDYgTCA2LjcwMzQ3LDE1Ljc0MDcgTCA2LjUwNDQyLDE1LjcyNzggTCA2LjMwNSwxNS43MzIxIEwgNi4xMDY2OSwxNS43NTM1IEwgNS45MTA5NSwxNS43OTE5IEwgNS43MTkyNCwxNS44NDcgTCA1LjUzMjk3LDE1LjkxODMgTCA1LjM1MzUyLDE2LjAwNTQgTCA1LjE4MjIzLDE2LjEwNzYgTCA1LjAyMDM1LDE2LjIyNDIgTCA0Ljg2OTEsMTYuMzU0MiBMIDQuNzI5NTgsMTYuNDk2OCBMIDQuNjAyODMsMTYuNjUwOCBMIDQuNDg5NzksMTYuODE1MSBMIDQuMzkxMywxNi45ODg2IEwgNC4zMDgwOCwxNy4xNjk5IEwgNC4yNDA3NiwxNy4zNTc2IEwgNC4xODk4MiwxNy41NTA1IEwgNC4xNTU2NiwxNy43NDcgTCA0LjEzODUxLDE3Ljk0NTcgTCA0LjEzODUxLDE4LjE0NTIgTCA0LjE1NTY2LDE4LjM0MzkgTCA0LjE4OTgyLDE4LjU0MDQgTCA0LjI0MDc2LDE4LjczMzMgTCA0LjMwODA4LDE4LjkyMTEgTCA0LjM5MTMsMTkuMTAyMyBMIDQuNDg5NzksMTkuMjc1OCBMIDQuNjAyODMsMTkuNDQwMSBMIDQuNzI5NTgsMTkuNTk0MSBMIDQuODY5MSwxOS43MzY3IEwgNS4wMjAzNSwxOS44NjY3IEwgNS4xODIyMywxOS45ODMzIEwgNS4zNTM1MiwyMC4wODU1IEwgNS41MzI5NywyMC4xNzI2IEwgNS43MTkyNCwyMC4yNDM5IEwgNS45MTA5NSwyMC4yOTkgTCA2LjEwNjY5LDIwLjMzNzQgTCA2LjMwNSwyMC4zNTg4IEwgNi41MDQ0MiwyMC4zNjMxIEwgNi43MDM0NywyMC4zNTAyIEwgNi45MDA2OCwyMC4zMjAzIEwgNy4wOTQ1OSwyMC4yNzM1IEwgNy4yODM3NiwyMC4yMTAzIEwgNy40NjY3OCwyMC4xMzEgTCA3LjY0MjMyLDIwLjAzNjIgTCA3LjgwOTA1LDE5LjkyNjcgTCA3Ljk2NTc3LDE5LjgwMzMgTCA4LjExMTI5LDE5LjY2NjkgTCA4LjI0NDU0LDE5LjUxODUgTCA4LjM2NDU1LDE5LjM1OTIgTCA4LjQ3MDQxLDE5LjE5MDEgTCA4LjU2MTM1LDE5LjAxMjYgTCA4LjYzNjY5LDE4LjgyNzkgTCA4LjY5NTg3LDE4LjYzNzQgTCA4LjczODQ2LDE4LjQ0MjUgTCA4Ljc2NDE1LDE4LjI0NDcgTCA4Ljc3MjczLDE4LjA0NTUgTCA2LjQ1NDU1LDE4LjA0NTUgWicgc3R5bGU9J2ZpbGw6IzAwMDAwMDtmaWxsLXJ1bGU6ZXZlbm9kZDtmaWxsLW9wYWNpdHk9MTtzdHJva2U6IzAwMDAwMDtzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjE7JyAvPgo8cGF0aCBkPSdNIDc5Ljg2MzYsMTguMDQ1NSBMIDc5Ljg1NTEsMTcuODQ2MiBMIDc5LjgyOTQsMTcuNjQ4NCBMIDc5Ljc4NjgsMTcuNDUzNSBMIDc5LjcyNzYsMTcuMjYzIEwgNzkuNjUyMywxNy4wNzgzIEwgNzkuNTYxMywxNi45MDA4IEwgNzkuNDU1NSwxNi43MzE3IEwgNzkuMzM1NSwxNi41NzI0IEwgNzkuMjAyMiwxNi40MjQgTCA3OS4wNTY3LDE2LjI4NzYgTCA3OC45LDE2LjE2NDIgTCA3OC43MzMyLDE2LjA1NDcgTCA3OC41NTc3LDE1Ljk1OTkgTCA3OC4zNzQ3LDE1Ljg4MDcgTCA3OC4xODU1LDE1LjgxNzQgTCA3Ny45OTE2LDE1Ljc3MDYgTCA3Ny43OTQ0LDE1Ljc0MDcgTCA3Ny41OTUzLDE1LjcyNzggTCA3Ny4zOTU5LDE1LjczMjEgTCA3Ny4xOTc2LDE1Ljc1MzUgTCA3Ny4wMDE5LDE1Ljc5MTkgTCA3Ni44MTAxLDE1Ljg0NyBMIDc2LjYyMzksMTUuOTE4MyBMIDc2LjQ0NDQsMTYuMDA1NCBMIDc2LjI3MzEsMTYuMTA3NiBMIDc2LjExMTMsMTYuMjI0MiBMIDc1Ljk2LDE2LjM1NDIgTCA3NS44MjA1LDE2LjQ5NjggTCA3NS42OTM3LDE2LjY1MDggTCA3NS41ODA3LDE2LjgxNTEgTCA3NS40ODIyLDE2Ljk4ODYgTCA3NS4zOTksMTcuMTY5OSBMIDc1LjMzMTcsMTcuMzU3NiBMIDc1LjI4MDcsMTcuNTUwNSBMIDc1LjI0NjYsMTcuNzQ3IEwgNzUuMjI5NCwxNy45NDU3IEwgNzUuMjI5NCwxOC4xNDUyIEwgNzUuMjQ2NiwxOC4zNDM5IEwgNzUuMjgwNywxOC41NDA0IEwgNzUuMzMxNywxOC43MzMzIEwgNzUuMzk5LDE4LjkyMTEgTCA3NS40ODIyLDE5LjEwMjMgTCA3NS41ODA3LDE5LjI3NTggTCA3NS42OTM3LDE5LjQ0MDEgTCA3NS44MjA1LDE5LjU5NDEgTCA3NS45NiwxOS43MzY3IEwgNzYuMTExMywxOS44NjY3IEwgNzYuMjczMSwxOS45ODMzIEwgNzYuNDQ0NCwyMC4wODU1IEwgNzYuNjIzOSwyMC4xNzI2IEwgNzYuODEwMSwyMC4yNDM5IEwgNzcuMDAxOSwyMC4yOTkgTCA3Ny4xOTc2LDIwLjMzNzQgTCA3Ny4zOTU5LDIwLjM1ODggTCA3Ny41OTUzLDIwLjM2MzEgTCA3Ny43OTQ0LDIwLjM1MDIgTCA3Ny45OTE2LDIwLjMyMDMgTCA3OC4xODU1LDIwLjI3MzUgTCA3OC4zNzQ3LDIwLjIxMDMgTCA3OC41NTc3LDIwLjEzMSBMIDc4LjczMzIsMjAuMDM2MiBMIDc4LjksMTkuOTI2NyBMIDc5LjA1NjcsMTkuODAzMyBMIDc5LjIwMjIsMTkuNjY2OSBMIDc5LjMzNTUsMTkuNTE4NSBMIDc5LjQ1NTUsMTkuMzU5MiBMIDc5LjU2MTMsMTkuMTkwMSBMIDc5LjY1MjMsMTkuMDEyNiBMIDc5LjcyNzYsMTguODI3OSBMIDc5Ljc4NjgsMTguNjM3NCBMIDc5LjgyOTQsMTguNDQyNSBMIDc5Ljg1NTEsMTguMjQ0NyBMIDc5Ljg2MzYsMTguMDQ1NSBMIDc3LjU0NTUsMTguMDQ1NSBaJyBzdHlsZT0nZmlsbDojMDAwMDAwO2ZpbGwtcnVsZTpldmVub2RkO2ZpbGwtb3BhY2l0eT0xO3N0cm9rZTojMDAwMDAwO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MTsnIC8+Cjwvc3ZnPgo= [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 109
229910052802 copper Inorganic materials 0.000 abstract description 51
RYGMFSIKBFXOCR-UHFFFAOYSA-N copper Chemical compound data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nMzAwcHgnIGhlaWdodD0nMzAwcHgnIHZpZXdCb3g9JzAgMCAzMDAgMzAwJz4KPCEtLSBFTkQgT0YgSEVBREVSIC0tPgo8cmVjdCBzdHlsZT0nb3BhY2l0eToxLjA7ZmlsbDojRkZGRkZGO3N0cm9rZTpub25lJyB3aWR0aD0nMzAwJyBoZWlnaHQ9JzMwMCcgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJzdGFydCIgeD0nMTIzLjMxNicgeT0nMTU2JyBzdHlsZT0nZm9udC1zaXplOjQwcHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7ZmlsbDojM0I0MTQzJyA+PHRzcGFuPkN1PC90c3Bhbj48L3RleHQ+Cjwvc3ZnPgo= data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nODVweCcgaGVpZ2h0PSc4NXB4JyB2aWV3Qm94PScwIDAgODUgODUnPgo8IS0tIEVORCBPRiBIRUFERVIgLS0+CjxyZWN0IHN0eWxlPSdvcGFjaXR5OjEuMDtmaWxsOiNGRkZGRkY7c3Ryb2tlOm5vbmUnIHdpZHRoPSc4NScgaGVpZ2h0PSc4NScgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJzdGFydCIgeD0nMTYuMjI1NCcgeT0nNDcuNzk1NScgc3R5bGU9J2ZvbnQtc2l6ZTozOHB4O2ZvbnQtc3R5bGU6bm9ybWFsO2ZvbnQtd2VpZ2h0Om5vcm1hbDtmaWxsLW9wYWNpdHk6MTtzdHJva2U6bm9uZTtmb250LWZhbWlseTpzYW5zLXNlcmlmO2ZpbGw6IzNCNDE0MycgPjx0c3Bhbj5DdTwvdHNwYW4+PC90ZXh0Pgo8L3N2Zz4K [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 49
238000005498 polishing Methods 0.000 abstract description 3
PBCFLUZVCVVTBY-UHFFFAOYSA-N Tantalum pentoxide Chemical compound data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nMzAwcHgnIGhlaWdodD0nMzAwcHgnIHZpZXdCb3g9JzAgMCAzMDAgMzAwJz4KPCEtLSBFTkQgT0YgSEVBREVSIC0tPgo8cmVjdCBzdHlsZT0nb3BhY2l0eToxLjA7ZmlsbDojRkZGRkZGO3N0cm9rZTpub25lJyB3aWR0aD0nMzAwJyBoZWlnaHQ9JzMwMCcgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHBhdGggY2xhc3M9J2JvbmQtMCcgZD0nTSAzOS43Mzc1LDExMi43NDEgTCA0OS43Mzc3LDExOC41MTQnIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiNFODQyMzU7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC0wJyBkPSdNIDQ5LjczNzcsMTE4LjUxNCBMIDU5LjczNzksMTI0LjI4OCcgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6IzNCNDE0MztzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTAnIGQ9J00gNDYuOTYxMywxMDAuMjI5IEwgNTYuOTYxNSwxMDYuMDAyJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojRTg0MjM1O3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMCcgZD0nTSA1Ni45NjE1LDEwNi4wMDIgTCA2Ni45NjE3LDExMS43NzYnIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiMzQjQxNDM7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC0xJyBkPSdNIDgwLjIxNjgsMTUxLjIwNCBMIDgwLjIxNjgsMTY4LjA1OScgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6IzNCNDE0MztzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTEnIGQ9J00gODAuMjE2OCwxNjguMDU5IEwgODAuMjE2OCwxODQuOTE1JyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojRTg0MjM1O3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMScgZD0nTSA5NC42NjQzLDE1MS4yMDQgTCA5NC42NjQzLDE2OC4wNTknIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiMzQjQxNDM7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC0xJyBkPSdNIDk0LjY2NDMsMTY4LjA1OSBMIDk0LjY2NDMsMTg0LjkxNScgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6I0U4NDIzNTtzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTInIGQ9J00gMTExLjUzMSwxMTguMDMyIEwgMTIxLjUzMSwxMTIuMjU4JyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojM0I0MTQzO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMicgZD0nTSAxMjEuNTMxLDExMi4yNTggTCAxMzEuNTMyLDEwNi40ODUnIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiNFODQyMzU7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC0zJyBkPSdNIDE2OC40NjgsMTA2LjQ4NSBMIDE3OC40NjksMTEyLjI1OCcgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6I0U4NDIzNTtzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTMnIGQ9J00gMTc4LjQ2OSwxMTIuMjU4IEwgMTg4LjQ2OSwxMTguMDMyJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojM0I0MTQzO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtNCcgZD0nTSAyNDAuMjYyLDEyNC4yODggTCAyNTAuMjYyLDExOC41MTQnIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiMzQjQxNDM7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC00JyBkPSdNIDI1MC4yNjIsMTE4LjUxNCBMIDI2MC4yNjIsMTEyLjc0MScgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6I0U4NDIzNTtzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTQnIGQ9J00gMjMzLjAzOCwxMTEuNzc2IEwgMjQzLjAzOSwxMDYuMDAyJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojM0I0MTQzO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtNCcgZD0nTSAyNDMuMDM5LDEwNi4wMDIgTCAyNTMuMDM5LDEwMC4yMjknIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiNFODQyMzU7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC01JyBkPSdNIDIwNS4zMzYsMTUxLjIwNCBMIDIwNS4zMzYsMTY4LjA1OScgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6IzNCNDE0MztzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTUnIGQ9J00gMjA1LjMzNiwxNjguMDU5IEwgMjA1LjMzNiwxODQuOTE1JyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojRTg0MjM1O3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtNScgZD0nTSAyMTkuNzgzLDE1MS4yMDQgTCAyMTkuNzgzLDE2OC4wNTknIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiMzQjQxNDM7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC01JyBkPSdNIDIxOS43ODMsMTY4LjA1OSBMIDIxOS43ODMsMTg0LjkxNScgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6I0U4NDIzNTtzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+Cjx0ZXh0IGRvbWluYW50LWJhc2VsaW5lPSJjZW50cmFsIiB0ZXh0LWFuY2hvcj0iZW5kIiB4PSczMy43MTc3JyB5PSc5OS40MzM4JyBzdHlsZT0nZm9udC1zaXplOjI0cHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7ZmlsbDojRTg0MjM1JyA+PHRzcGFuPk88L3RzcGFuPjwvdGV4dD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJtaWRkbGUiIHg9Jzg3LjQ0MDUnIHk9JzEzNS41NTMnIHN0eWxlPSdmb250LXNpemU6MjRweDtmb250LXN0eWxlOm5vcm1hbDtmb250LXdlaWdodDpub3JtYWw7ZmlsbC1vcGFjaXR5OjE7c3Ryb2tlOm5vbmU7Zm9udC1mYW1pbHk6c2Fucy1zZXJpZjtmaWxsOiMzQjQxNDMnID48dHNwYW4+VGE8L3RzcGFuPjwvdGV4dD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJzdGFydCIgeD0nNzguNjAzOCcgeT0nMjA3Ljc5JyBzdHlsZT0nZm9udC1zaXplOjI0cHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7ZmlsbDojRTg0MjM1JyA+PHRzcGFuPk88L3RzcGFuPjwvdGV4dD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJtaWRkbGUiIHg9JzE1MCcgeT0nOTkuNDMzOCcgc3R5bGU9J2ZvbnQtc2l6ZToyNHB4O2ZvbnQtc3R5bGU6bm9ybWFsO2ZvbnQtd2VpZ2h0Om5vcm1hbDtmaWxsLW9wYWNpdHk6MTtzdHJva2U6bm9uZTtmb250LWZhbWlseTpzYW5zLXNlcmlmO2ZpbGw6I0U4NDIzNScgPjx0c3Bhbj5PPC90c3Bhbj48L3RleHQ+Cjx0ZXh0IGRvbWluYW50LWJhc2VsaW5lPSJjZW50cmFsIiB0ZXh0LWFuY2hvcj0ibWlkZGxlIiB4PScyMTIuNTU5JyB5PScxMzUuNTUzJyBzdHlsZT0nZm9udC1zaXplOjI0cHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7ZmlsbDojM0I0MTQzJyA+PHRzcGFuPlRhPC90c3Bhbj48L3RleHQ+Cjx0ZXh0IGRvbWluYW50LWJhc2VsaW5lPSJjZW50cmFsIiB0ZXh0LWFuY2hvcj0ic3RhcnQiIHg9JzI2Ni4yODInIHk9Jzk5LjQzMzgnIHN0eWxlPSdmb250LXNpemU6MjRweDtmb250LXN0eWxlOm5vcm1hbDtmb250LXdlaWdodDpub3JtYWw7ZmlsbC1vcGFjaXR5OjE7c3Ryb2tlOm5vbmU7Zm9udC1mYW1pbHk6c2Fucy1zZXJpZjtmaWxsOiNFODQyMzUnID48dHNwYW4+TzwvdHNwYW4+PC90ZXh0Pgo8dGV4dCBkb21pbmFudC1iYXNlbGluZT0iY2VudHJhbCIgdGV4dC1hbmNob3I9InN0YXJ0IiB4PScyMDMuNzIzJyB5PScyMDcuNzknIHN0eWxlPSdmb250LXNpemU6MjRweDtmb250LXN0eWxlOm5vcm1hbDtmb250LXdlaWdodDpub3JtYWw7ZmlsbC1vcGFjaXR5OjE7c3Ryb2tlOm5vbmU7Zm9udC1mYW1pbHk6c2Fucy1zZXJpZjtmaWxsOiNFODQyMzUnID48dHNwYW4+TzwvdHNwYW4+PC90ZXh0Pgo8L3N2Zz4K data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nODVweCcgaGVpZ2h0PSc4NXB4JyB2aWV3Qm94PScwIDAgODUgODUnPgo8IS0tIEVORCBPRiBIRUFERVIgLS0+CjxyZWN0IHN0eWxlPSdvcGFjaXR5OjEuMDtmaWxsOiNGRkZGRkY7c3Ryb2tlOm5vbmUnIHdpZHRoPSc4NScgaGVpZ2h0PSc4NScgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHBhdGggY2xhc3M9J2JvbmQtMCcgZD0nTSA4LjcxMjI0LDMwLjI2MTUgTCAxMy41OTI0LDMzLjA3OScgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6I0U4NDIzNTtzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTAnIGQ9J00gMTMuNTkyNCwzMy4wNzkgTCAxOC40NzI1LDM1Ljg5NjYnIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiMzQjQxNDM7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC0wJyBkPSdNIDEwLjc1OSwyNi43MTY0IEwgMTUuNjM5MSwyOS41MzQnIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiNFODQyMzU7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC0wJyBkPSdNIDE1LjYzOTEsMjkuNTM0IEwgMjAuNTE5MiwzMi4zNTE1JyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojM0I0MTQzO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMScgZD0nTSAyMi4yMjgxLDQwLjI5NDQgTCAyMi4yMjgxLDQ3LjExNjgnIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiMzQjQxNDM7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC0xJyBkPSdNIDIyLjIyODEsNDcuMTE2OCBMIDIyLjIyODEsNTMuOTM5Mycgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6I0U4NDIzNTtzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTEnIGQ9J00gMjYuMzIxNSw0MC4yOTQ0IEwgMjYuMzIxNSw0Ny4xMTY4JyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojM0I0MTQzO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMScgZD0nTSAyNi4zMjE1LDQ3LjExNjggTCAyNi4zMjE1LDUzLjkzOTMnIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiNFODQyMzU7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC0yJyBkPSdNIDI5LjA1MzgsMzQuMTI0IEwgMzMuOTMzOSwzMS4zMDY1JyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojM0I0MTQzO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMicgZD0nTSAzMy45MzM5LDMxLjMwNjUgTCAzOC44MTQsMjguNDg5JyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojRTg0MjM1O3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMycgZD0nTSA0NS4xODYsMjguNDg5IEwgNTAuMDY2MSwzMS4zMDY1JyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojRTg0MjM1O3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMycgZD0nTSA1MC4wNjYxLDMxLjMwNjUgTCA1NC45NDYyLDM0LjEyNCcgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6IzNCNDE0MztzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTQnIGQ9J00gNjUuNTI3NSwzNS44OTY2IEwgNzAuNDA3NiwzMy4wNzknIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiMzQjQxNDM7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC00JyBkPSdNIDcwLjQwNzYsMzMuMDc5IEwgNzUuMjg3OCwzMC4yNjE1JyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojRTg0MjM1O3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtNCcgZD0nTSA2My40ODA4LDMyLjM1MTUgTCA2OC4zNjA5LDI5LjUzNCcgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6IzNCNDE0MztzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTQnIGQ9J00gNjguMzYwOSwyOS41MzQgTCA3My4yNDEsMjYuNzE2NCcgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6I0U4NDIzNTtzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTUnIGQ9J00gNTcuNjc4NSw0MC4yOTQ0IEwgNTcuNjc4NSw0Ny4xMTY4JyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojM0I0MTQzO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtNScgZD0nTSA1Ny42Nzg1LDQ3LjExNjggTCA1Ny42Nzg1LDUzLjkzOTMnIHN0eWxlPSdmaWxsOm5vbmU7ZmlsbC1ydWxlOmV2ZW5vZGQ7c3Ryb2tlOiNFODQyMzU7c3Ryb2tlLXdpZHRoOjJweDtzdHJva2UtbGluZWNhcDpidXR0O3N0cm9rZS1saW5lam9pbjptaXRlcjtzdHJva2Utb3BhY2l0eToxJyAvPgo8cGF0aCBjbGFzcz0nYm9uZC01JyBkPSdNIDYxLjc3MTksNDAuMjk0NCBMIDYxLjc3MTksNDcuMTE2OCcgc3R5bGU9J2ZpbGw6bm9uZTtmaWxsLXJ1bGU6ZXZlbm9kZDtzdHJva2U6IzNCNDE0MztzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjEnIC8+CjxwYXRoIGNsYXNzPSdib25kLTUnIGQ9J00gNjEuNzcxOSw0Ny4xMTY4IEwgNjEuNzcxOSw1My45MzkzJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojRTg0MjM1O3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJlbmQiIHg9JzkuMDUzMzYnIHk9JzI3LjY3MjknIHN0eWxlPSdmb250LXNpemU6NnB4O2ZvbnQtc3R5bGU6bm9ybWFsO2ZvbnQtd2VpZ2h0Om5vcm1hbDtmaWxsLW9wYWNpdHk6MTtzdHJva2U6bm9uZTtmb250LWZhbWlseTpzYW5zLXNlcmlmO2ZpbGw6I0U4NDIzNScgPjx0c3Bhbj5PPC90c3Bhbj48L3RleHQ+Cjx0ZXh0IGRvbWluYW50LWJhc2VsaW5lPSJjZW50cmFsIiB0ZXh0LWFuY2hvcj0ibWlkZGxlIiB4PScyNC4yNzQ4JyB5PSczNy45MDY1JyBzdHlsZT0nZm9udC1zaXplOjZweDtmb250LXN0eWxlOm5vcm1hbDtmb250LXdlaWdodDpub3JtYWw7ZmlsbC1vcGFjaXR5OjE7c3Ryb2tlOm5vbmU7Zm9udC1mYW1pbHk6c2Fucy1zZXJpZjtmaWxsOiMzQjQxNDMnID48dHNwYW4+VGE8L3RzcGFuPjwvdGV4dD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJzdGFydCIgeD0nMjEuNzcxMScgeT0nNTguMzczOCcgc3R5bGU9J2ZvbnQtc2l6ZTo2cHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7ZmlsbDojRTg0MjM1JyA+PHRzcGFuPk88L3RzcGFuPjwvdGV4dD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJtaWRkbGUiIHg9JzQyJyB5PScyNy42NzI5JyBzdHlsZT0nZm9udC1zaXplOjZweDtmb250LXN0eWxlOm5vcm1hbDtmb250LXdlaWdodDpub3JtYWw7ZmlsbC1vcGFjaXR5OjE7c3Ryb2tlOm5vbmU7Zm9udC1mYW1pbHk6c2Fucy1zZXJpZjtmaWxsOiNFODQyMzUnID48dHNwYW4+TzwvdHNwYW4+PC90ZXh0Pgo8dGV4dCBkb21pbmFudC1iYXNlbGluZT0iY2VudHJhbCIgdGV4dC1hbmNob3I9Im1pZGRsZSIgeD0nNTkuNzI1MicgeT0nMzcuOTA2NScgc3R5bGU9J2ZvbnQtc2l6ZTo2cHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7ZmlsbDojM0I0MTQzJyA+PHRzcGFuPlRhPC90c3Bhbj48L3RleHQ+Cjx0ZXh0IGRvbWluYW50LWJhc2VsaW5lPSJjZW50cmFsIiB0ZXh0LWFuY2hvcj0ic3RhcnQiIHg9Jzc0Ljk0NjYnIHk9JzI3LjY3MjknIHN0eWxlPSdmb250LXNpemU6NnB4O2ZvbnQtc3R5bGU6bm9ybWFsO2ZvbnQtd2VpZ2h0Om5vcm1hbDtmaWxsLW9wYWNpdHk6MTtzdHJva2U6bm9uZTtmb250LWZhbWlseTpzYW5zLXNlcmlmO2ZpbGw6I0U4NDIzNScgPjx0c3Bhbj5PPC90c3Bhbj48L3RleHQ+Cjx0ZXh0IGRvbWluYW50LWJhc2VsaW5lPSJjZW50cmFsIiB0ZXh0LWFuY2hvcj0ic3RhcnQiIHg9JzU3LjIyMTQnIHk9JzU4LjM3MzgnIHN0eWxlPSdmb250LXNpemU6NnB4O2ZvbnQtc3R5bGU6bm9ybWFsO2ZvbnQtd2VpZ2h0Om5vcm1hbDtmaWxsLW9wYWNpdHk6MTtzdHJva2U6bm9uZTtmb250LWZhbWlseTpzYW5zLXNlcmlmO2ZpbGw6I0U4NDIzNScgPjx0c3Bhbj5PPC90c3Bhbj48L3RleHQ+Cjwvc3ZnPgo= O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 5
229910001937 tantalum pentoxide Inorganic materials 0.000 description 5
238000003701 mechanical milling Methods 0.000 description 4
229910000599 Cr alloys Inorganic materials 0.000 description 2
229910001362 Ta alloys Inorganic materials 0.000 description 2
In order that the yield can be enhanced, the method of manufacturing a semiconductor device comprises the steps of: forming first holes 101a not penetrating a support side silicon wafer 101; forming a ground insulating film 102; forming primary connection plugs 105a by charging copper into the first holes 101a; forming a semiconductor film 108 on one face side of the support side silicon wafer 101 through an intermediate insulating film 109; forming elements on the semiconductor film 108; exposing bottom faces of the primary connection plugs 105a by polishing the other face of the support side silicon wafer 101; forming second holes 111 extending from an element forming face of the semiconductor film 108 to the primary connection plugs 105; and forming auxiliary connection plugs 112a for electrically connecting the elements with the primary connection plugs 105a by charging copper into the second holes.
Make the method and the semiconductor device of semiconductor device
The present invention relates to the method for semiconductor device and manufacturing semiconductor device.More particularly, the present invention relates to a kind of technology, this technology is used for reducing the damage to the element of semiconductor device effectively in the process of making semiconductor device.
Various semiconductor devices are installed on electronic equipment.Recently, electronic equipment has reduced size.According to the situation that the electronic equipment size reduces, proposed a kind of semiconductor device with three-dimensional mounting structure.The three-dimensional mounting structure example of prior art is disclosed in Japanese unexamined patent publication 10-223833 and 10-303364 number.
According to above-mentioned patent publications, it was suggested a kind of three-dimensional mounting structure, wherein a plurality of semiconductor elements are lamination vertically.Each semiconductor element that constitutes this three-dimensional mounting structure mainly comprises a silicon chip (substrate), forms element on this substrate surface, for example transistor.On this silicon chip, the metal pin that is electrically connected with said elements is along the thickness direction of silicon chip.Provide power supply and input signal by these metal pin to these elements.
In this respect, according to above-mentioned patent publications, metal pin in silicon chip is to form like this: after having formed element on the surface at silicon chip, on this surface, form the hole that does not penetrate silicon chip, promptly form the hole that does not penetrate silicon chip, all then metal filled these holes forming on the silicon chip surface of element.
Yet the above-mentioned this method that forms the hole after the element again in substrate that formed on silicon chip, its shortcoming be, the element that forms around in the hole when forming the hole is damaged.So the output of making semiconductor device has been lowered.
The present invention is designed the problem that exists in the prior art in order to solve.
Therefore, an object of the present invention is to provide a kind of method of making semiconductor device, can improve the output of making semiconductor device with the method.
According to the present invention, a kind of method of making semiconductor device is provided, described method comprises following steps: form the first group of hole that does not penetrate this support side semiconductor chip on a surface supporting the side semiconductor chip; On a surface supporting the side semiconductor chip, and on the sidewall and bottom in first group of hole, form underlayer insulating film (ground insulating film); First metal filled in first group of hole, thereby form the basic pin that connects; Via an intermediate insulating film (intermediate insulating film), on a face side supporting the side semiconductor chip, form semiconductor film (semiconductor film); On this semiconductor film, form element; Support another surface of side semiconductor chip to be come out in the bottom surface of basic connection pin by grinding; Formation extends to second group of hole of basic connection pin from the surface of semiconductor film formation element; And second metal filled in second group of hole, thereby form the auxiliary pin that connects, be used for element and be connected being electrically connected of slotting limb substantially.
According to a further aspect in the invention, provide a kind of method of making semiconductor device, described method comprises following steps: form the first group of hole that does not penetrate this support side insulating substrate on a surface supporting the side insulating substrate; First metal filled in first group of hole, thereby form the basic pin that connects; Via an intermediate insulating film, on a face side supporting the side insulating substrate, form the semiconductor film; On this semiconductor film, form element; Support another surface of side insulating substrate to be come out in the bottom surface of basic connection pin by grinding; Formation forms second group of hole that the surface extends to basic connection pin from an element of semiconductor film; And second metal filled in second group of hole, thereby form the auxiliary pin that connects, be used for element and the electrical connection that is connected pin substantially.
Next, will explain operation of the present invention hereinafter.
The method of manufacturing semiconductor device of the present invention comprises the steps that (a) is to (h).
(a) step: form first group of hole on a surface supporting the side semiconductor chip, they do not penetrate supports the side semiconductor chip.
(b) step: on a surface supporting the side semiconductor chip, also on the sidewall and bottom in first group of hole, form a underlayer insulating film.
(c) step: after forming underlayer insulating film,, thereby form basic connection pin first metal filled in first group of hole.
(d) step: after forming basic connection pin, on a face side supporting the side semiconductor chip,, form the semiconductor film by an intermediate insulating film.
(e) step: after forming semiconductor film, on semiconductor film, form element.
(f) step: after forming element,, come out in the bottom surface of basic connection pin by grinding another surface of supporting the side semiconductor chip.
(g) step: form from the element of halfbody film and form second group of hole that the surface extends to basic connection pin.
(h) step: second metal filled, thereby form the auxiliary pin that connects, be used for element and the electrical connection that is connected pin substantially to second group of hole.
According to above-mentioned manufacture method, in the step (above-mentioned steps (a)) that forms first group of hole afterwards, carry out the step (above-mentioned steps (e)) that forms element.So, when forming first group of hole, do not have element to be damaged.Therefore can improve the output of making semiconductor device.
In above-mentioned steps (a), on a surface supporting the side semiconductor chip, can form metallic channel.In the step (above-mentioned steps (c)) that forms basic connection pin, these metallic channels can be filled first metal and be become primary traverse.Yet this primary traverse is to embed to support the side semiconductor chip.So, and supporting to provide the situation of lead to compare on the side semiconductor chip, supporting that the scrambling (unevenness) on the side semiconductor chip is little.
Have again, in above-mentioned steps (b), after forming underlayer insulating film, can on underlayer insulating film, form the lead embed insulating film that has the opening portion that is used for little lead.In the step (above-mentioned steps (c)) that forms basic connection pin, first metal is inserted the opening portion that these are used for little lead, so these opening portions that are used for little lead become little lead.These opening portions that are used for little lead form on the lead embed insulating film, and the thickness of this dielectric film is less than the thickness of supporting the side semiconductor chip.So these opening portions that are used for little lead are compared significantly little with the metallic channel that is split on support side semiconductor chip.For above-mentioned reasons, to compare with primary traverse be very little to this little lead.
At this on the one hand, semiconductor film forms in above-mentioned steps (d), yet, also can form semiconductor film and make it that soi structure can be arranged.In order to form semiconductor film with soi structure, at first to prepare a component side semiconductor chip, form an intermediate insulating film in its surface.Then, intermediate insulating film one side with the component side semiconductor chip is attached on the surface supporting the side semiconductor chip.After this, the thickness of component side semiconductor chip is reduced, thereby the component side semiconductor chip can be formed among the above-mentioned semiconductor film.
By above-mentioned steps, can on intermediate insulating film, form the semiconductor film of little thickness.This structure is SOI (silicon on a insulator) structure itself.In other words, above-mentioned intermediate insulating film plays a part embed insulating film, and above-mentioned semiconductor film plays the effect of soi film.
The step that can provide formation one to have an even surface dielectric film on a surface supporting the side semiconductor chip forms before the semiconductor film in the step (abovementioned steps (d)) that forms semiconductor film, the step that also can provide formation one to have an even surface dielectric film.Since above-mentioned, semiconductor film can on flat surfaces, be formed.Particularly when as above-mentioned when sticking the component side semiconductor chip, the component side semiconductor chip is close on the dielectric film that has an even surface, can between them, not stay any slit.
At this on the one hand, in above-mentioned situation, used support side semiconductor chip, yet, as the other method of manufacturing semiconductor device of the present invention, can use and support the side insulating substrate to replace supporting the side semiconductor chip.In this case, on supporting the side insulating substrate, form after first group of hole, a step that forms a film can be provided, to strengthen the adhesiveness between first metal of supporting on side insulating substrate and the first group of hole sidewall.Since above-mentioned, can prevent that first metal breaks away from from supporting the side insulating substrate, thereby strengthen the reliability of line.
Or use to support the side semiconductor chip or use in the situation of supporting the side insulating substrate, in forming basic connection pin step (above-mentioned steps (c)), can provide a step, wherein, after forming basic connection pin, form the surface that a metal barrier is used for the exposure of topped basic connection pin.When forming this metal barrier, can prevent that first metal is diffused into the film that is formed on the metal barrier from basic connection pin.
According to another aspect of the invention, provide a kind of semiconductor device, it comprises: a support side semiconductor chip that has first hole that penetrates; A semiconductor film that is combined as a whole with an element, described semiconductor film have second hole therefrom to penetrate and are stacked on the described support side semiconductor chip; A basic connection pin that includes first metal of inserting in described first hole, and an auxiliary connection pin that includes second metal of inserting in described second hole, described auxiliary connection pin is electrically connected described basic connection pin with described element.
In accordance with a further aspect of the present invention, provide a kind of semiconductor device, it comprises: a support side insulating substrate that has first hole that penetrates; A semiconductor film that is combined as a whole with an element, described semiconductor film have second hole therefrom to pass and be stacked on the described support side insulating substrate; A basic connection pin that includes first metal of inserting in described first hole; And an auxiliary connection pin that includes second metal of inserting in described second hole, described auxiliary connection pin is electrically connected described basic connection pin with described element.
Fig. 1 (a) is a sectional view to 1 (d), the phase I of the method for the manufacturing semiconductor device of demonstration first embodiment of the invention;
Fig. 2 (a) is a sectional view to 2 (d), the second stage of the method for the manufacturing semiconductor device of demonstration first embodiment of the invention;
Fig. 3 (a) is a sectional view to 3 (c), the phase III of the method for the manufacturing semiconductor device of demonstration first embodiment of the invention;
Fig. 4 (a) is a sectional view to 4 (c), the quadravalence section of the method for the manufacturing semiconductor device of demonstration first embodiment of the invention;
Fig. 5 (a) is a sectional view to 5 (d), the five-stage of the method for the manufacturing semiconductor device of demonstration first embodiment of the invention;
Fig. 6 (a) is a sectional view to 6 (c), the 6th stage of the method for the manufacturing semiconductor device of demonstration first embodiment of the invention;
Fig. 7 (a) is a sectional view to 7 (c), the 7th stage of the method for the manufacturing semiconductor device of demonstration first embodiment of the invention;
Fig. 8 is a sectional view, another example of the method for the manufacturing semiconductor device of demonstration first embodiment of the invention;
Fig. 9 (a) is a sectional view to 9 (c), the method for the manufacturing semiconductor device of demonstration second embodiment of the invention;
Figure 10 (a) is a sectional view to 10 (d), the phase I of the method for the manufacturing semiconductor device of demonstration third embodiment of the invention;
Figure 11 (a) is a sectional view to 11 (d), the second stage of the method for the manufacturing semiconductor device of demonstration third embodiment of the invention;
Figure 12 (a) is a sectional view to 12 (c), the phase III of the method for the manufacturing semiconductor device of demonstration third embodiment of the invention;
Figure 13 (a) is a sectional view to 13 (c), the quadravalence section of the method for the manufacturing semiconductor device of demonstration third embodiment of the invention;
Figure 14 (a) is a sectional view to 14 (d), the five-stage of the method for the manufacturing semiconductor device of demonstration third embodiment of the invention;
Figure 15 (a) is a sectional view to 15 (c), the 6th stage of the method for the manufacturing semiconductor device of demonstration third embodiment of the invention;
Figure 16 is a sectional view, the 7th stage of the method for the manufacturing semiconductor device of demonstration third embodiment of the invention;
Figure 17 (a) is a sectional view to 17 (b), another example of the method for the manufacturing semiconductor device of demonstration third embodiment of the invention;
Figure 18 (a) is a sectional view to 18 (c), the phase I of the method for the manufacturing semiconductor device of demonstration fourth embodiment of the invention;
Figure 19 (a) is a sectional view to 19 (c), the second stage of the method for the manufacturing semiconductor device of demonstration fourth embodiment of the invention;
Figure 20 is a sectional view, the phase III of the method for the manufacturing semiconductor device of demonstration fourth embodiment of the invention.
To Fig. 8, hereinafter will explain the method for the manufacturing semiconductor device of first embodiment of the invention with reference to figure 1 (a).
At first, as shown in Fig. 1 (a), go up formation at a surperficial 101d who supports side silicon wafer (supporting the side semiconductor chip) 101 and do not penetrate first group of hole 101a, the 101a that supports side silicon wafer 101 ...These first group of hole 101a formed by well-known technology, processes, sandblasts and plasma etching as laser beam, and the diameter of each hole 101a is about 5 to 100 μ m, and the degree of depth of each hole 101a is about 5 to 500 μ m.
Next, as shown in Fig. 1 (b), on a surperficial 101d who supports side silicon wafer 101, form metallic channel 101b, 101b ...As shown in FIG., metallic channel 101b, 101b ... in have some to communicate with first group of hole 101a, other are then isolated with first group of hole 101a.Identical with the mode that forms first group of hole 101a, this metallic channel 101b is formed by well-known technology, processes, sandblasts and plasma etching as laser beam.The degree of depth of each metallic channel 101b is about 5 to 200 μ m, and the width of each metallic channel 101b is about 1 to 100 μ m.
In this respect, in the step afterwards copper is filled among the metallic channel 101b, so metallic channel 101b becomes primary traverse.Yet,, can not form metallic channel 101b not needing to provide in the situation of lead.
Next, as shown in Fig. 1 (c), on a surperficial 101d who supports the side silicon wafer,, form by SiO on the sidewall of first group of hole 101a and the bottom and on the sidewall and bottom at metallic channel 101b 2The underlayer insulating film of making 102.This underlayer insulating film 102 is formed by CVD method (chemical vapour sedimentation method), and film thickness about 50 is to 300nm.In this respect, underlayer insulating film 102 can be formed by thermal oxidation method, with replaced C VD method.
As described in hereinafter wanting, copper is filled among first group of hole 101a and the metallic channel 101b.Yet underlayer insulating film 102 plays a part electrical insulator, makes copper and supports 101 insulation of side silicon wafer.
Next, as shown in Fig. 1 (d), formation is by SiO above the underlayer insulating film 102 that forms on a surperficial 101d who supports side silicon wafer 101 2The lead embed insulating film of making 103.Lead embed insulating film 103 is formed by the CVD method, and the film thickness of lead embed insulating film 103 about 10 is to 5000nm.As shown in FIG., be used for little lead opening portion 103a, 103a ... open on lead embed insulating film 103.These be used for little lead opening portion 103a, 103a ... in have some to communicate with first group of hole 101a or metallic channel 101b, other are then independently of one another with them.Be used for little lead these opening portions 103a, 103a ... be to form by the means of on lead embed insulating film 103, making wiring pattern.
Next, as shown in Fig. 2 (a), plated film feed body layer (plated feeder layer) 104 is formed on underlayer insulating film 102 and the lead embed insulating film 103.This plated film feed body layer 104 is to form like this: by copper film or the chromium film (not drawing among the figure) of the about 0.1 μ m of sputter formation thickness, form the no electrolytic copper plated film (electrolesscopper plating film) of about 1 to the 3 μ m of thickness then on this copper film or chromium film.
Next, as shown in Fig. 2 (b),, make and on relevant plated film feed body layer 104, form electrolytic copper plated film 105 by supplying electric current on plated film feed body layer 104.
Next, as shown in Fig. 2 (c), plated film feed body layer 104 and electrolytic copper plated film 105 are ground (polishing), come out until the surface of lead embed insulating film 103 with CMP method (CMP method).By above-mentioned steps, can finish such structure, therein copper (first metal) the opening portion 103a that is filled into first group of hole 101a, metallic channel 101b and is used for little lead.Like this, just formed the basic connection pin 105a that constitutes by the copper of inserting first group of hole 101a, primary traverse 105b that constitutes by the copper of inserting metallic channel 101b and the little lead 105c that constitutes by the copper of inserting the opening portion 103a that is used for little lead.
In this structure, primary traverse 105b is embedded into and supports in the side silicon wafer 101.So, compare with the situation that on support side silicon wafer 101, forms lead, supporting that the scrambling on the side silicon wafer 101 is little here.Because above-mentioned, on silicon wafer 101, can form dielectric film and can not reduce the flatness on surface.In this embodiment, described in hereinafter, the component side silicon wafer sticks on the surperficial 101d who supports side silicon wafer 101.In this situation of pasting the component side silicon wafer, when surface is good, above the component side silicon wafer can stick on high attachment characteristic.
On the other hand, when noticing the opening portion 103a (having embedded little lead 105c therein) that is used for little lead (with reference to dashed circle shown in the figure 2 (c)), these opening portion 103a that are used for little lead form on dielectric film 103, embedded this lead in this dielectric film 103, the thickness of dielectric film 103 is significantly less than the thickness of supporting side silicon wafer 101.So the opening portion 103a that is used for little lead is more much smaller than metallic channel 101b.Therefore, might realize irrealizable little lead 105c by primary traverse 105b.In this respect, when this little lead must not be arranged, can form lead embed insulating film 103.
In this respect, also can use tungsten, aluminium, tantalum, titanium, nickel and chromium Alloy instead of Copper as first metal.State in the use under the situation of metal, can select suitable film formation method, as plating, flame coating or sputter every kind of metal.
In this respect, in said structure, connect pin 105a and primary traverse 105b substantially and be included in the support side silicon wafer 101, yet, when in supporting side silicon wafer 101, being formed for the hole (not shown) of capacity cell, can further including capacity cell in and support in the side silicon wafer 101.
Next, as shown in Fig. 2 (d), metal barrier (barrier metal layer) 106 has formed, and it covers the basic exposed surface that connects pin 105a, primary traverse 105b and little lead 105c.This metal barrier 106 is made by for example tantalum or tantalum pentoxide, and the thickness of its film about 50 is to 500nm.Adopt sputter to form metal barrier 106.
Next, as shown in Fig. 3 (a), on lead embed insulating film 103 and metal barrier 106, form 107 (being used to make the dielectric film that has an even surface) of coating glass-film (coating glass film).
In this case, as previously mentioned, primary traverse 105b and little lead 105c embed respectively and support in side silicon wafer 101 and the lead embed insulating film 103.So, compare with the situation that on support side silicon wafer 101, forms lead, can on the surface of coating glass-film 107, form scrambling hardly here.
In addition, because lead can be by in the glass-film 107 of embedding coating easily, so might obtain smooth basically surface configuration.About 0.1 to the 3 μ m of film thickness of this coating glass-film 107.
Have again, should note such fact, be positioned at metal barrier 106 protection that metal barrier 106 following copper had before been formed, it can not be diffused in the coating glass-film 107.Since above-mentioned, might prevent copper migration in coating glass-film 107.In this respect, even in coating glass-film 107, also can not cause in the situation of problem, can save metal barrier 106 at copper migration.This coating glass-film 107 can form with the CVD method.
Next, as shown in Fig. 3 (b), coating glass-film 107 is ground (polishing) with mechanical milling method or CMP method, thereby makes having an even surface of coating glass-film 107.Because the surface configuration of this coating glass-film 107 is smooth basically as previously mentioned, so amount of grinding in this course can reduce.After the surface of grinding coating glass-film 107 by this way, coating glass-film 107 lip-deep inhomogeneous (unevenness) is reduced to and is no more than 1nm.
Next, as shown in Fig. 3 (c), prepared a component side silicon wafer 116 (component side semiconductor chip), formed by SiO in its surface 2The intermediate insulating film of making 109.Intermediate insulating film 109 forms the about 50nm to 400nm of its film thickness at the component side silicon wafer during by thermal oxidation.In this respect, in the present embodiment, be on two surfaces of component side silicon wafer 116, to form intermediate insulating film 109, yet, might not do like this, but prepare a component side silicon wafer, only on one surface, form intermediate insulating film 109.
Next, as shown in Fig. 4 (a), component side silicon wafer 116 is secured on the surface supporting side silicon wafer 101.Using the component side silicon wafer and only forming on one surface in the situation of intermediate insulating film 109, intermediate insulating film one side of component side silicon wafer is secured on surface one side supporting side silicon wafer 101.
In this case, stickup is following carrying out.In the time of on component side silicon wafer 116 being put into surface one side supporting side silicon wafer 101, this wafer is annealed.
In this case, should note following content.In process shown in Fig. 3 (b), the surface of coating glass-film 107 has been flattened smooth.Since above-mentioned, when carrying out above-mentioned stickup,, make them closely to paste each other supporting not form the slit between side silicon wafer 101 and the component side silicon wafer 116.
Next, as shown in Fig. 4 (b), component side silicon wafer 116 is ground with the CMP method, and its thickness is reduced to about 0.5 to 50 μ m.Its thickness as the above-mentioned component side silicon wafer 116 that has reduced be known as semiconductor film 108 hereinafter.In this case, it should be noted that soi structure is made of this semiconductor film 108 and intermediate insulating film 109.In other words, the effect of intermediate insulating film 109 is the oxide-films that embed, and the effect of semiconductor film 108 is soi films.
In this respect, in order to reduce the thickness of component side silicon wafer 116, can this component side silicon wafer 116 be divided into two along thickness direction with well-known wafer-separate method shown in Figure 8.An example of well-known wafer-separate method be side from the component side silicon wafer to component side silicon wafer 116 injection waters, thereby component side silicon wafer 116 is divided into two along thickness direction.
When being divided into two as above-mentioned component side silicon wafer 116, can be reused for the process shown in Fig. 1 (a) from the component side silicon wafer 116 of supporting side silicon wafer 101 to separate, this can reduce the cost of supporting side silicon wafer 101.
As above-mentioned formed semiconductor film 108 after, process shown in the execution graph 4 (c).In this course, on semiconductor film 108, form as transistor and other elements.In the drawings, one deck of (combining) said elements has been included in reference number 108a representative in.Hereinafter, reference number 108a is called the element cambium layer, and its surface is called element hereinafter and forms surperficial 108b.As previously mentioned, the effect of semiconductor film 108 is soi films.So, can on element cambium layer 108a, form element, and the parasitic capacitance between this element and the semiconductor film 108 has been suppressed.
In this respect, can carry out the process (Fig. 4 (c) shown in) of following process to replace the forming process (Fig. 3 (c) is to shown in 4 (b)) of semiconductor film 108 and to replace on semiconductor film 108, forming element.In other words, prepare a silicon wafer (not shown), on one surface, form semiconductor element, and can allow the opposed surface (not forming the side of semiconductor element thereon) of this silicon wafer stick with glue on coating glass-film 107, the surface of coating glass-film 107 is done into smooth.
Next, as shown in Fig. 5 (a), support that the another side of side silicon wafer 101 is ground with mechanical milling method or CMP method, thereby can be come out in the bottom surface of basic connection pin 105a.
Next, as shown in Fig. 5 (b), on the another side of supporting side silicon wafer 101, form by SiO 2The surface insulating film of making 110.This surface insulating film 110 is formed by the CVD method usually, and the thickness of film about 10 is to 5000nm.After this, this surface insulating film 110 is formed pattern, thereby forms opening portion 110a in the position corresponding to basic pin 105a.
Next, as shown in Fig. 5 (c), by etching form second group of hole 111,111 ..., they form surperficial 108b from element and extend to metal barrier 106.In this respect, as preamble was explained, metal barrier 106 was made by tantalum or tantalum pentoxide.In the situation that metal barrier 106 is made by tantalum pentoxide and so on dielectric, metal barrier 106 is also etched, thus make second group of hole 111,111 ... can arrive basic pin 105a of connection and primary traverse 105b.
In the situation that does not form metal barrier 106, form second group of hole 111, thereby make them can arrive basic connection pin 105a and primary traverse 105b.As shown in FIG., form second group of hole 111, thereby make them can penetrate different parts, as coating glass-film 107, intermediate insulating film 109 and semiconductor film 108.In this case, when each part was selected the most suitable well-known etching technique, above-mentioned second group of hole 111 formed.
After second group of hole 111 forms, go up the recessed portion 108c that formation communicates with second group of hole 111 by being etched in element cambium layer 108a.Though do not draw in the drawings, 108a provides intermediate insulating film and conductor layer to the element cambium layer, and they form by laminating various films.When each film was used the most suitable well-known etching technique, recessed portion 108c had formed.Though do not draw in the drawings, formed each recessed portion 108c makes the conductor layer of element cambium layer 108a can be exposed on the sidewall or bottom surface of recessed portion 108c.
Next, as shown in Fig. 5 (d),, copper is inserted second group of hole 111 and recessed portion 108c as an example of second metal.
In this case, insert copper as follows.At first, form a feed body layer (not shown) by sputter or electroless copper in sidewall and bottom that element forms surperficial 108b and second group of hole 111 and recessed portion 108c.When this plated film feed body layer is added electric current, just on plated film feed body layer, form the electrolytic copper plating layer (not shown), till second group of hole 111 and recessed portion 108c are filled up by copper.After this, by grinding, remove element and form plated film feed body layer and the electrolytic copper plated film that surperficial 108b goes up formation with the CMP method.Finished structure shown in Fig. 5 (d) by this way.
In this manual, a copper that is filled in second group of hole 111 is called auxiliary connection pin 112a hereinafter, and a copper that is filled in the recessed portion is called top electrode pad (upper electrode pad) 112b hereinafter.
As mentioned above, formed recessed portion 108c makes the conductor layer of element cambium layer 108a can be exposed on the sidewall and bottom surface of recessed portion.So the element on element cambium layer 108a is electrically connected with top electrode pad 112b and the auxiliary pin 112a that is connected.Have again, auxiliary connect pin 112a via metal barrier 106 be connected pin 105a electrical connection substantially.So, the element on element cambium layer 108a be connected pin 105a substantially and be electrically connected.
In this respect, in this embodiment, use copper as second metal, yet, can use tungsten, aluminium, tantalum, titanium, nickel and chromium as second metal with Alloy instead of Copper.
Next, as shown in Fig. 6 (a), on surface insulating film 110, form the bottom electrode pad of making by copper 113,113 ...These bottom electrode pads 113,113 ... form by subraction, semi-additive process or full additive method.So, bottom electrode pad 113,113 ... via the opening portion 110a of surface insulating film 110 be connected pin 105a substantially and be electrically connected.
Next, as shown in Fig. 6 (b), solder-coating protective layer on surface insulation layer 110 and bottom electrode 113 (solder resist) 117.This scolder protective layer 117 has opening portion 117a, and the surface of bottom electrode pad 113 is exposed to these opening portions 117a.
Next, as shown in Fig. 6 (c), by opening portion 117a bottom electrode pad 113,113 ... on load onto solder bump 114,114 ...Though do not draw among the figure, in the stage of finishing this process, a slice support to form on the side silicon wafer 101 a plurality of semiconductor devices 115,115 ..., they all are to have used the method for the manufacturing semiconductor device of present embodiment to make.
After this, by section make semiconductor device 115,115 ... make each monolithic.Semiconductor device 115,115 ... be made into after each monolithic, by solder bump 114,114 ... they are installed on the mounted substrate (not shown), motherboard for example, these solder bumps provide in each semiconductor device 115.
In this respect, can be used as monomer by the semiconductor device of the method manufacturing of present embodiment uses.The another kind of practice is, as shown in Figure 7, can be a plurality of semiconductor devices 115 vertically stacked (as shown in Figure 7), thus make them can form three-dimensional mounting structure.
With reference to figure 7, when noticing at vertical direction semiconductor device adjacent one another are 115,115, the solder bump 114 that provides in upside semiconductor device 115 combines with the upper electrode pad 112b that provides in downside semiconductor device 115.So in this structure, the basic connection pin 105a of upside semiconductor device 115 is connected pin 112a electricity in succession with the auxiliary of downside semiconductor device 115.
When as thereby above-mentioned semiconductor device 115,115 is stacked when making them form three-dimensional mounting structure, erection space can be reduced, make erection space when arranging at grade to semiconductor device 115,115, this can have big contribution to reducing the electronic equipment size, and it is desired recently just to reduce the electronic equipment size.
According to the method for the manufacturing semiconductor device of present embodiment, the process (shown in Fig. 4 (c)) that forms element is to carry out afterwards in the basic forming process (shown in Fig. 1 (a)) that connects first group of used hole 101a of pin 105a.In this example example, about 5 to the 500 μ m of the degree of depth of first group of hole 101a, in other words, the degree of depth of first group of hole 101a is dark, yet,, even when forming first group of hole 101a, can not damage element owing to after first group of hole 101a formed, just form element yet.
On the other hand, being used for the auxiliary forming process (shown in Fig. 5 (c)) that connects second group of hole 111 of pin 112a is to carry out after the process that forms element, yet, because about 0.5 to the 20 μ m of the degree of depth in second hole, in other words, according to component side silicon wafer 116, the about 5 μ m of the general degree of depth in second group of hole, in other words, the degree of depth in second hole is shallow, even, element is damaged so after forming element, form these shallow bore holes again.
As previously mentioned, in this embodiment, when forming these holes, there is not element impaired.Therefore, compare, can improve the output of semiconductor device with the situation of using conventional method to make semiconductor device.
Fig. 8 shows an embodiment, and it is to obtain when the part of previous embodiment is carried out following change.In process shown in Fig. 4 (a), after component side silicon wafer 116 has pasted on the surface supporting side silicon wafer 101, component side silicon wafer 116 is separated and do not resemble the process of lapping shown in Fig. 4 (b), and the semiconductor film 108 of about 0.05 to the 0.1 μ m of thickness is left on the surface supporting side silicon wafer 101.
Next with reference to figure 9, the method for the manufacturing semiconductor device of second embodiment of the invention will be explained.
The difference of this embodiment and first embodiment is Fig. 1 (a) to the process shown in 1 (c), and other processes of this embodiment are identical with those processes of first embodiment.
In this embodiment, at first, as shown in Fig. 9 (a), when supporting that side silicon wafer 101 is subjected to laser beam irradiation in oxygen atmosphere, just formed first group of hole 101a.At this moment, because sidewall and the bottom of first group of hole 101a be heated in oxygen atmosphere, so the silicon in these parts is oxidized, so generate heat oxide film 101c.
Next, as shown in Fig. 9 (b), form metallic channel 101b when in oxygen atmosphere, carry out laser radiation with aforementioned the same manner.In this course, generate heat oxide film 101c on the sidewall of metallic channel 101b and the bottom.
In this case, in the process that forms first group of hole 101a and metallic channel 101b,, formed heat oxide film 101c with first group of hole 101a of formation and metallic channel 101b while.In this case, should note such fact, the effect of the underlayer insulating film 102 among the effect of the heat oxide film 101c that is promptly provided and first embodiment is identical.In other words, the effect of heat oxide film 101c is to make basic connection pin 105a and primary traverse 105b (as shown in Fig. 2 (c)) the two realizes electric insulations with supporting side silicon wafer 101.
Next, as shown in Fig. 9 (c), only on a surperficial 101d who supports side silicon wafer 101, form by SiO 2The underlayer insulating film 102 that constitutes.Owing in first group of hole 101a and metallic channel 101b, formed heat oxide film 101c, there is no need in these parts, to form underlayer insulating film 102.
This underlayer insulating film 102 can form with thermal oxidation method or CVD method, and its thickness about 50 is to 300nm.
After this, by each process (explaining in first embodiment) after the process shown in Fig. 1 (d), semiconductor device 115 (being shown among Fig. 6 (c)) has formed.
According to the method for the manufacturing semiconductor device of present embodiment, first group of hole 101a and metallic channel 101b form by the laser beam irradiation in the oxygen atmosphere.Since aforementioned, on the sidewall of first group of hole 101a and metallic channel 101b He in the bottom, formed heat oxide film 101c.So, can only on a surface supporting side silicon wafer 101, form underlayer insulating film 102.Since aforementioned, compare (in first embodiment, also in first group of hole 101a and metallic channel 101b, forming underlayer insulating film) with first embodiment, and the advantage of present embodiment has been to reduce the cost that forms underlayer insulating film 102.
(3) the 3rd embodiment
Next, to Figure 17 (b), will explain the method for the manufacturing semiconductor device of third embodiment of the invention with reference to Figure 10 (a) hereinafter.
Different with first and second embodiment, present embodiment is supporting side to use glass substrate 201 to replace silicon wafer 101.
At first, as shown in Figure 10 (a), a surperficial 201d who supports side glass substrate 201 (supporting the side insulating substrate) go up formation do not penetrate first group of hole 201a, 201a supporting side glass substrate 201 ...These first group of hole 201a, 201a ... be to form, process, sandblast or plasma etching as laser beam with well-known technology.About 5 to the 200 μ m of the diameter in each hole, about 5 to the 500 μ m of the degree of depth.
Next, as shown in Figure 10 (b), on a surperficial 201d who supports side glass substrate 201, form metallic channel 201b, 201b ...As shown in FIG., metallic channel 201b, 201b ... in have some to communicate with first group of hole 201a, other are then isolated with first group of hole 201a.Identical with the generation type of first group of hole 201a, these metallic channel 201b form with well-known technology, process, sandblast and plasma etching as laser beam.About 5 to the 200 μ m of the degree of depth of each metallic channel 201b, and about 1 to the 100 μ m of the width of each metallic channel 201b.
In this respect, in the same manner as in the first embodiment copper is inserted metallic channel 201b, so metallic channel 201b becomes primary traverse.Yet,, can not form metallic channel 201b not needing to provide in the situation of lead.
Next, as shown in Figure 10 (c), on a surperficial 201d who supports side glass substrate 201, form by SiO 2The lead embed insulating film of making 103.Lead embed insulating film 103 is to form with the CVD method, and its film thickness about 10 is to 5000nm.As shown in FIG., little wire openings part 103a, 103a ... open on lead embed insulating film 103.Be used for little lead these opening portions 103a, 103a ... in have some to communicate with first group of hole 201a or metallic channel 202b, other are then independently of one another with them.These little wire openings part 103a, 103a ... be to form by the means that on lead embed insulating film 103, form pattern.
Next, as shown in Figure 10 (d), on the sidewall of first group of hole 201a and metallic channel 201b and in the bottom, also on the sidewall of little wire openings part 103a, form glass adhesive film (glassadherence film) 202.Identical with the mode of first embodiment, in process thereafter, copper (first metal) is inserted first group of hole 201a, metallic channel 201b and little wire openings part 103a.Utilize glass adhesive film 202, support side glass substrate 201 closely to be attached on the copper.Since aforementioned, can prevent that copper from coming off from supporting side glass substrate 201, thereby strengthen reliability.
This glass adhesive film 202 is made by chromium and tantalum, with the method formation of plating, flame coating or sputter.
Next, as shown in Figure 11 (a), on glass adhesive film 202 and lead embed insulating film 103, form plated film feed body layer 104.This plated film feed body layer 104 is to form like this: by copper film or the chromium film (not drawing among the figure) of the about 0.1 μ m of sputter formation thickness, form the no electrolytic copper plated film of about 1 to the 3 μ m of thickness then on this copper film or chromium film.
Next, as shown in Figure 11 (b), supplying electric current on plated film feed body layer 104, thus on relevant plated film feed body layer 104, form electrolytic copper plated film 105.
Next, as shown in Figure 11 (c), plated film feed body layer 104 and electrolytic copper plating layer 105 are ground, come out up to the surface of lead embed insulating film 103 with the CMP method.By above-mentioned steps, can finish such structure, copper (first metal) is filled among first group of hole 201a, metallic channel 201b and the little wire openings part 103a therein.Like this, the primary traverse 105b that has just formed the basic connection pin 105a that constitutes by the copper of inserting first group of hole 201a, constituted by the copper of inserting metallic channel 201b, and the little lead 105c that constitutes by the copper of inserting little wire openings part 103a.
Identical with the mode of first embodiment, primary traverse 105b is embedded into and supports in the side glass substrate 201.So, compare with the situation that on support side glass substrate 201, forms lead, supporting that the scrambling (unevenness) on the side glass substrate 201 is little.Because above-mentioned, on glass substrate 201, can form dielectric film and can not reduce the flatness on surface.
When as above-mentioned surface when high, the component side silicon wafer can highly closely stick on the surface supporting side glass substrate 201 in process thereafter.
On the other hand, when noticing the opening portion 103a (having embedded little lead 105c therein) that is used for little lead (with reference to dashed circle shown in Figure 11 (c)), the opening portion 103a that is used for little lead forms on dielectric film 103, embedded this lead in this dielectric film 103, the thickness of dielectric film 103 is significantly less than the thickness of supporting side glass substrate 201.So the opening portion 103a that is used for little lead is more much smaller than metallic channel 201b.So, can realize irrealizable little lead 105c by primary traverse 105b.In this respect, when this little lead must not be arranged, can form lead embed insulating film 103.
In this respect, also can use tungsten, aluminium, tantalum, titanium, nickel and chromium Alloy instead of Copper as first metal.State in the use in the situation of metal, can select suitable film formation method, as plating, flame coating or sputter every kind of metal.
In this respect, in said structure, basic pin 105a of connection and primary traverse 105b are included into and support in the side glass substrate 201, yet, when in supporting side glass substrate 201, being formed for the hole (not shown) of capacity cell, can further including capacity cell in and support in the side glass substrate 201.
Next, as shown in Figure 11 (d), metal barrier 106 has formed, the exposed surface of its topped basic connection pin 105a, primary traverse 105b and little lead 105c.This metal barrier 106 is made by for example tantalum or tantalum pentoxide, and the thickness of its film about 50 is to 500nm.Adopt sputter to form metal barrier 106.
Next, as shown in Figure 12 (a), on lead embed insulating film 103 and metal barrier 106, form coating glass-film 107 (being used to make the dielectric film that has an even surface).
In this case, as previously mentioned, primary traverse 105b and little lead 105c are embedded respectively supports side glass substrate 201 and lead embed insulating film 103.So, compare with the situation that on support side glass substrate 101, forms lead, can on the surface of coating glass-film 107, form scrambling hardly.
As explaining among first embodiment, because lead can easily embed coating glass-film 107, so can obtain smooth basically surface configuration (profile), the surface configuration here is subjected to bottom (ground layer) to go up the influence of inhomogeneities hardly.So, can obtain the surface configuration of substantially flat.About 0.1 to the 3 μ m of the film thickness of this coating glass-film 107.
Have again, be positioned at metal barrier 106 protection that metal barrier 106 following copper had before been formed, it can not be diffused in the coating glass-film 107.Since above-mentioned, can prevent copper to migration in coating glass-film 107.In this respect, even in coating glass-film 107, also can not cause in the situation of problem, can save metal barrier 106 at copper migration.
Next, as shown in Figure 12 (b), coating glass-film 107 is ground with mechanical milling method or CMP method, thereby makes having an even surface of coating glass-film 107.Because the surface configuration of this coating glass-film 107 is smooth basically as previously mentioned, so amount of grinding in this course can reduce.After the surface of grinding coating glass-film 107 by this way, coating glass-film 107 lip-deep inhomogeneities are reduced to and are no more than 1nm.
Next, as shown in Figure 12 (c), prepared a component side silicon wafer 116 (component side semiconductor chip), formed by SiO in its surface 2The intermediate insulating film of making 109.This intermediate insulating film 109 forms the about 50nm to 400nm of its film thickness at component side silicon wafer 116 during by thermal oxidation.In this respect, in this embodiment, be on two surfaces of component side silicon wafer 116, to form intermediate insulating film 109, yet, might not do like this, but prepare a component side silicon wafer, only on one surface, form intermediate insulating film 109.
Next, as shown in Figure 13 (a), component side silicon wafer 116 is secured on the surface supporting side glass substrate 201.Using the component side silicon wafer and only forming on the one surface under the situation of intermediate insulating film 109, intermediate insulating film one side of component side silicon wafer is secured on surface one side supporting side glass substrate 201.
In this case, stickup is following carrying out: in the time of on component side silicon wafer 116 being put into surface one side supporting side glass substrate 201, this wafer is annealed.
In this case, should note following content.In process shown in Figure 12 (b), the surface of coating glass-film 107 has been flattened smooth.Since above-mentioned, when carrying out above-mentioned stickup, supporting not form the slit between side glass substrate 201 and the component side silicon wafer 108, so they can be pasted closely each other.
Next, as shown in Figure 13 (b), component side silicon wafer 116 is ground with the CMP method, and its thickness is reduced.The semiconductor film 108 of about 0.5 to the 50 μ m of thickness like this, just is provided.
In this case, as explaining among first embodiment, constituted a soi structure by this semiconductor film 108 and intermediate insulating film 109.
In this respect, can carry out process shown in Figure 17 (a) and 17 (b), to replace process shown in Figure 13 (a) and 13 (b).
In the process shown in Figure 17 (a), support a surface of one of side glass substrates 201 to paste on the surface of component side silicon wafer 116 for two, and these two supported another the surface in the side glass substrate 201 to paste on another surface of component side silicon wafer 116.After this, utilize well-known wafer cutting techniques that component side silicon wafer 116 is divided into two along the A-B cross section among the figure.
Figure 17 (b) shows the state after as described above the component side silicon wafer being divided into two.As seen in Fig., when the wafer application cutting techniques, might produce two structures, wherein semiconductor film 108 forms on a surface supporting side glass substrate 201.So, when adopting this method, can reduce half to the cost of making component side silicon wafer 116.
After forming semiconductor film 108 in such a way, carry out process shown in Figure 13 (c).In this course, formed element cambium layer 108a, on it, formed element, as transistor.
In this respect, can carry out following process by mode identical among first embodiment, with the process that replace to form semiconductor film 108 (as Figure 12 (c) to as shown in 13 (b)) with replace on semiconductor film 108, forming the process (as shown in Figure 13 (c)) of element.Prepare a silicon wafer, on one surface, form semiconductor element, and can allow the opposed surface (not forming the side of semiconductor element thereon) of this silicon wafer stick with glue on coating glass-film 107, the surface of coating glass-film 107 is done into smooth.
Next, support that the another side of side glass substrate 201 is ground with mechanical milling method or CMP method, as shown in Figure 14 (a), thereby come out in the bottom surface of basic connection pin 105a.
Next, as shown in Figure 14 (b), on the another side of supporting side glass substrate 201, form by the SiO that makes 2Surface insulating film 110.This surface insulating film 110 is formed by the CVD method, and the thickness of film about 10 is to 1000nm.
Next, as shown in Figure 14 (c), by etching form second group of hole 111,111 ..., they form surperficial 108b from element and extend to metal barrier 106.In the situation that metal barrier 106 is made by tantalum pentoxide and so on dielectric, metal barrier 106 is also etched, thus make second group of hole 111,111 ... can arrive basic pin 105a of connection and primary traverse 105b.In this respect, in the situation that does not form metal barrier 106, form second group of hole 111, thereby make them can arrive basic connection pin 105a and primary traverse 105b.
After the second group of hole 111 that has formed, go up the recessed portion 108c that formation communicates with second group of hole 111 by being etched in element cambium layer 108a.In the same manner as in the first embodiment, form recessed portion 108c, thereby make the conductor layer of element cambium layer 108a can be exposed to sidewall or the bottom surface of recessed portion 108c.
Next, as shown in Figure 14 (d), utilize the same quadrat method of explaining among first embodiment,, copper is inserted second group of hole 111 and recessed portion 108c as an example of second metal.Since above-mentioned, can form by inserting the auxiliary connection pin 112a that second group of copper in the hole 111 constitutes.Can also form the top electrode pad 112a that constitutes by the copper of inserting recessed portion 108c.In this respect, can use tungsten, aluminium, tantalum, titanium, nickel and chromium as second metal, with Alloy instead of Copper.
Next, as shown in Figure 15 (a), the bottom electrode pad 113,113 that formation is made by copper on surface insulating film 110 ...These bottom electrode pads 113,113 ... form by subraction, semi-additive process or full additive method.So, bottom electrode pad 113,113 ... via the opening portion 110a of surface insulating film 110 be connected pin 105a substantially and be electrically connected.
Next, as shown in Figure 15 (b), solder-coating protective layer 117 on surface insulation layer 110 and bottom electrode 113.This scolder protective layer 117 has opening portion 117a, and the surface of bottom electrode pad 113 is exposed to these opening portions 117a.
Next, as shown in Figure 15 (c), by opening portion 117a bottom electrode pad 113,113 ... on load onto solder bump 114,114 ...Though do not draw among the figure, in the stage of finishing this process, a slice support to form on the side glass substrate 201 a plurality of semiconductor devices 203,203 ..., they all are to have used the method for the manufacturing semiconductor device of present embodiment to make.
After this, by section make semiconductor device 203,203 ... make each monolithic.Semiconductor device 203,203 ... be made into after each monolithic, by solder bump 114,114 ... they are installed on the mounted substrate (not shown), motherboard for example, these solder bumps provide in each semiconductor device 203.
In this respect, can be used as monomer by the semiconductor device of the method manufacturing of present embodiment uses.Another kind method is, as shown in Figure 16, can be a plurality of semiconductor devices 203 vertically stacked (as shown in Figure 16), thus make them can form three-dimensional mounting structure.
In the structure shown in Figure 16, the solder bump 114 that provides in upside semiconductor device 203 combines with the upper electrode pad 112b that provides in downside semiconductor device 203.So in this structure, the basic connection pin 105a of upside semiconductor device 203 is electrically connected with the auxiliary pin 112a that is connected of downside semiconductor device 203.
When as thereby above-mentioned semiconductor device 203,203 is stacked when making them form three-dimensional mounting structure, erection space can be reduced, make erection space when arranging at grade to semiconductor device 203,203, this can have big contribution to reducing the electronic equipment size, and it is desired recently just to reduce the electronic equipment size.
Method according to the manufacturing semiconductor device of present embodiment, identical with the mode among first embodiment, the process (shown in Figure 13 (c)) that forms element is to carry out afterwards in the basic forming process (shown in Figure 10 (a)) that connects first group of used hole 201a of pin 105a.So, when forming first group of hole 201a, do not have element impaired.Therefore, compare, in the present embodiment, can improve the output of semiconductor device with the situation of using conventional method to make semiconductor device.
(4) the 4th embodiment
Next, referring to figs. 18 to 20, will explain the method for the manufacturing semiconductor device of fourth embodiment of the invention below.In this respect, with similar parts among the indication of similar reference number and first to the 3rd embodiment, and will omit explanation here to like.
The difference of this embodiment and first to the 3rd embodiment is to form the process of semiconductor film 108.Except this process, other processes are all identical with process among first to the 3rd embodiment.So, will only explain the process that forms semiconductor film 108 here.
At first, after process as shown in Fig. 2 (d), as shown in Figure 18 (a), a process is provided, on lead embed insulating film 103 and metal barrier 106, apply glass in this course, and to grinding and make it smooth in the glassy layer surface, thereby SiO formed 2Film 118 (film has an even surface).
Next, as shown in Figure 18 (b), use the CVD method at SiO 2Form SiO on the film 118 2Film 119.This SiO 2The thickness of film 119 about 5 is to 500nm.
Next, as shown in Figure 18 (c), prepare component side silicon wafer 116 (component side semiconductor chips), form by SiO in its surface 2The intermediate insulating film of making 109.Intermediate insulating film 109 forms the about 50nm to 400nm of its thickness by component side silicon wafer 116 being carried out thermal oxidation.In this respect, it is just enough to form intermediate insulating film 109 at least on a surface of component side silicon wafer 116, in other words, does not need to form like that in the structure shown in the image pattern intermediate insulating film 109 on the both sides of component side silicon wafer 116.
Next, as shown in Figure 19 (a), component side silicon wafer 116 sticks on the face side supporting side silicon wafer 101.Using the component side silicon wafer and only forming in the situation of intermediate insulating film 109 in the one side, intermediate insulating film one side of component side silicon wafer sticks on the face side supporting side silicon wafer 101.
In this case, stickup is carried out as follows: after on component side silicon wafer 116 being put into a surface supporting side silicon wafer 101, integral body is annealed.
Next, as shown in Figure 19 (b), component side silicon wafer 116 is come off.Because intermediate insulating film 109 forms by component side silicon wafer 116 is carried out thermal oxidation, so the adhesion strength between intermediate insulating film 109 and component side silicon wafer 116 is very high.Therefore, even come off, still on the surface of intermediate insulating film 109, stay next thin Si (silicon) film as the above-mentioned component side silicon wafer 116 that makes.In other words, Si (silicon) film near component side silicon wafer 116 surfaces is transferred on the support side silicon wafer 101.In this embodiment, the Si that is transferred like this (silicon) film is as semiconductor film 108.
After this, to the process shown in 6 (c), semiconductor device 120 has just been finished shown in Figure 19 (c) by Fig. 4 (c).In this respect, in semiconductor device 120, form second group of hole 111,111 ... thereby, make these holes can penetrate top CVD SiO 2Film 119.
Said process can not only be applied to use the situation of supporting side silicon wafer 101, and can be applied to use the situation of supporting side glass substrate 201.In this case, it is just enough to carry out above-mentioned identical process.So, omit it here and explain, just in Figure 20, demonstrate the sectional view of the semiconductor device of finishing 121.As shown in Figure 20, also formed in this case second group of hole 111,111 ... thereby, make these holes can penetrate top SiO 2Film 119.
1. method of making semiconductor device, described method comprises following steps:
On a surface supporting the side semiconductor chip, form the first group of hole that does not penetrate this support side semiconductor chip;
On the surface that is formed with first group of hole of supporting the side semiconductor chip, also on the sidewall and bottom in first group of hole, form underlayer insulating film;
By in first group of hole, filling first metal, form the basic pin that connects;
Via intermediate insulating film, form semiconductor film in surface one side supporting the side semiconductor chip;
On this semiconductor film, form element;
By grinding another surface of supporting the side semiconductor chip, come out in the bottom surface of basic connection pin;
Formation forms second group of hole that the surface extends to basic connection pin from the element of semiconductor film; And
By in second group of hole, filling second metal, form the auxiliary pin that connects, be used for element and the electrical connection that is connected pin substantially.
2. according to the method for the manufacturing semiconductor device of claim 1, further comprise following steps:
Side by side on a surface supporting the side semiconductor chip, form metallic channel with the step that forms first group of hole;
Side by side on the sidewall of metallic channel and bottom, form a underlayer insulating film with the step that forms underlayer insulating film; And
By to filling first metal in the metallic channel, in metallic channel, form primary traverse.
3. according to the method for the manufacturing semiconductor device of claim 1, further comprise following steps:
After forming underlayer insulating film, on underlayer insulating film, form lead embed insulating film with the opening portion that is used for little lead; And
Substantially be connected pin side by side with formation,, form little lead by filling first metal at the opening portion that is used for little lead.
4. according to the method for the manufacturing semiconductor device of claim 1, the step that wherein forms semiconductor film comprises following steps:
Prepare a component side semiconductor chip, form intermediate insulating film thereon;
Intermediate insulating film one side of component side semiconductor chip is sticked on surface one side supporting the side semiconductor chip; And
After the component side semiconductor chip is stuck, reduces the thickness of component side semiconductor chip, thereby form semiconductor film.
5. according to the method for the manufacturing semiconductor device of claim 1, further comprise following steps:
Before forming semiconductor film, on surface one side supporting the side semiconductor chip, form one and be used to make the dielectric film that has an even surface; And
Make this surface that is used to make the dielectric film that has an even surface become smooth.
6. method of making semiconductor device comprises following steps:
On a surface supporting the side insulating substrate, form the first group of hole that does not penetrate this support side insulating substrate;
Via intermediate insulating film, form semiconductor film in surface one side supporting the side insulating substrate;
By grinding another surface of supporting the side insulating substrate, come out in the bottom surface of basic connection pin;
7. according to the method for the manufacturing semiconductor device of claim 6, the step that wherein forms first group of hole is included in the step that forms a film on the inwall in first group of hole, and this film is used to strengthen the sticking property of supporting the side insulating substrate and first metal.
8. according to the method for the manufacturing semiconductor device of claim 6, further comprise following steps:
Side by side on a surface supporting the side insulating substrate, form metallic channel with the step that forms first group of hole; And
With form is connected pin substantially step side by side, by filling first metal in metallic channel, formation primary traverse.
9. according to the method for the manufacturing semiconductor device of claim 6, further comprise following steps:
On a surface supporting the side insulating substrate, form lead embed insulating film with the opening portion that is used for little lead; And
Side by side fill first metal with forming the step that is connected pin substantially, thereby form little lead at the opening portion that is used for little lead.
10. according to the method for the manufacturing semiconductor device of claim 6, the step that wherein forms semiconductor film comprises following steps:
Prepare a component side semiconductor chip, form intermediate insulating film in its surface;
Intermediate insulating film one side of component side semiconductor chip is sticked on the side on a surface supporting the side insulating substrate; And
After the component side semiconductor chip is adhered on surface one side supporting the side insulating substrate, reduces the thickness of component side semiconductor chip, thereby form semiconductor film.
11. the method according to the manufacturing semiconductor device of claim 6 further comprises following steps:
Before forming semiconductor film, on surface one side supporting the side insulating substrate, form one and be used to make the dielectric film that has an even surface; And
12. method according to the manufacturing semiconductor device of one of claim 1 to 11, wherein form the basic step that connects pin and comprise a step that forms metal barrier, after forming basic pin, the surface of the exposure of the topped basic connection pin of this metal barrier.
Support side semiconductor chip with first hole of therefrom passing;
Be combined with the semiconductor film of element thereon, described semiconductor film has second hole of therefrom passing and is stacked on the described support side semiconductor chip;
Substrate connects pin, contains first metal of inserting in described first hole; And
The auxiliary pin that connects contains second metal of inserting in described second hole, and described auxiliary connection pin is electrically connected described basic connection pin with described element.
14. a semiconductor device comprises:
Support side insulating substrate with first hole of therefrom passing;
Be combined with the semiconductor film of element thereon, described semiconductor film has second hole of therefrom passing and is stacked on the described support side insulating substrate;
CNB021002452A 2001-01-10 2002-01-10 Method for producing semiconductor device and semiconductor device CN1228824C (en)
JP2001002152A JP3535461B2 (en) 2001-01-10 2001-01-10 Semiconductor device manufacturing method and semiconductor device
JP002152/2001 2001-01-10
CN1365140A CN1365140A (en) 2002-08-21
CN1228824C true CN1228824C (en) 2005-11-23
ID=18870700
CNB021002452A CN1228824C (en) 2001-01-10 2002-01-10 Method for producing semiconductor device and semiconductor device
US (1) US6661077B2 (en)
JP (1) JP3535461B2 (en)
CN (1) CN1228824C (en)
TW (1) TW531843B (en)
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FR2965397A1 (en) * 2010-09-23 2012-03-30 Soitec Silicon On Insulator Method for manufacturing semi-conductor structure during manufacturing of e.g. semiconductor devices, involves replacing sacrificial material by conductor material, and forming portion of via across wafer in contact with another portion
JP5598420B2 (en) * 2011-05-24 2014-10-01 株式会社デンソー Manufacturing method of electronic device
TWI482240B (en) 2011-12-19 2015-04-21 Nat Univ Tsing Hua A method for fabricating interconnects in through-semiconductor-via
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