Source: http://www.google.com/patents/US7745285?dq=6008737
Timestamp: 2016-02-08 19:14:10
Document Index: 620586819

Matched Legal Cases: ['Application No. 02815618', 'Application No. 2003', 'Application No. 2004', 'Application No. 2004', 'Application No. 02815618', 'Application No. 03813980']

Patent US7745285 - Methods of forming and operating NAND memory with side-tunneling - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms...http://www.google.com/patents/US7745285?utm_source=gb-gplus-sharePatent US7745285 - Methods of forming and operating NAND memory with side-tunnelingAdvanced Patent SearchPublication numberUS7745285 B2Publication typeGrantApplication numberUS 11/693,765Publication dateJun 29, 2010Filing dateMar 30, 2007Priority dateMar 30, 2007Fee statusPaidAlso published asUS8248859, US20080239827, US20100226182Publication number11693765, 693765, US 7745285 B2, US 7745285B2, US-B2-7745285, US7745285 B2, US7745285B2InventorsNima MokhlesiOriginal AssigneeSandisk CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (108), Non-Patent Citations (27), Classifications (13), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethods of forming and operating NAND memory with side-tunneling
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5043940Jul 17, 1989Aug 27, 1991Eliyahou HarariFlash EEPROM memory systems having multistate storage cellsUS5053839Aug 21, 1990Oct 1, 1991Texas Instruments IncorporatedFloating gate memory cell and deviceUS5070032Mar 15, 1989Dec 3, 1991Sundisk CorporationMethod of making dense flash eeprom semiconductor memory structuresUS5095344Jun 8, 1988Mar 10, 1992Eliyahou HarariHighly compact eprom and flash eeprom devicesUS5168465Jan 15, 1991Dec 1, 1992Eliyahou HarariHighly compact EPROM and flash EEPROM devicesUS5172338Apr 11, 1990Dec 15, 1992Sundisk CorporationMulti-state EEprom read and write circuits and techniquesUS5198380Jul 17, 1989Mar 30, 1993Sundisk CorporationMethod of highly compact EPROM and flash EEPROM devicesUS5268318Oct 15, 1991Dec 7, 1993Eliyahou HarariHighly compact EPROM and flash EEPROM devicesUS5268319Oct 15, 1991Dec 7, 1993Eliyahou HarariHighly compact EPROM and flash EEPROM devicesUS5279982Jul 23, 1991Jan 18, 1994Sgs-Thomson Microelectronics S.R.L.Method for fabricating memory cell matrix having parallel source and drain interconnection metal lines formed on the substrate and topped by orthogonally oriented gate interconnection parallel metal linesUS5297148Oct 20, 1992Mar 22, 1994Sundisk CorporationFlash eeprom systemUS5313421Jan 14, 1992May 17, 1994Sundisk CorporationEEPROM with split gate source side injectionUS5315541Jul 24, 1992May 24, 1994Sundisk CorporationSegmented column memory arrayUS5343063Dec 18, 1990Aug 30, 1994Sundisk CorporationDense vertical programmable read only memory cell structure and processes for making themUS5380672Sep 3, 1993Jan 10, 1995Sundisk CorporationDense vertical programmable read only memory cell structures and processes for making themUS5471423May 16, 1994Nov 28, 1995Nippon Steel CorporationNon-volatile semiconductor memory deviceUS5512505Apr 17, 1995Apr 30, 1996Sandisk CorporationMethod of making dense vertical programmable read only memory cell structureUS5534456Mar 30, 1995Jul 9, 1996Sandisk CorporationMethod of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with sidewall spacersUS5554553Jun 6, 1995Sep 10, 1996Harari; EliyahouHighly compact EPROM and flash EEPROM devicesUS5579259May 31, 1995Nov 26, 1996Sandisk CorporationLow voltage erase of a flash EEPROM system having a common erase electrode for two individually erasable sectorsUS5595924Dec 19, 1994Jan 21, 1997Sandisk CorporationTechnique of forming over an irregular surface a polysilicon layer with a smooth surfaceUS5604032Oct 13, 1994Feb 18, 1997Matsushita Electric Industrial Co., Ltd.Fluorine-containing carboxylic acid amine salt and a magnetic recording medium with the same thereonUS5621233Jun 5, 1995Apr 15, 1997Motorola Inc.Electrically programmable read-only memory cellUS5637897Mar 4, 1996Jun 10, 1997Nec CorporationNonvolatile semiconductor memory device with dual insulation layers between adjacent gate structuresUS5640032Sep 7, 1995Jun 17, 1997Nippon Steel CorporationNon-volatile semiconductor memory device with improved rewrite speedUS5654217Mar 30, 1995Aug 5, 1997Sandisk CorporationDense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacersUS5661053May 25, 1994Aug 26, 1997Sandisk CorporationMethod of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacersUS5665987Mar 31, 1995Sep 9, 1997Toyo Denki Seizo Kabushiki KaishaInsulated gate static induction thyristor with a split gate type shorted cathode structureUS5677872Jul 8, 1996Oct 14, 1997Sandisk CorporationLow voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectorsUS5680345Jun 6, 1995Oct 21, 1997Advanced Micro Devices, Inc.Nonvolatile memory cell with vertical gate overlap and zero birds beaksUS5688705Aug 21, 1996Nov 18, 1997National Semiconductor CorporationMethod for reducing the spacing between the horizontally adjacent floating gates of a flash EPROM arrayUS5712179Oct 31, 1995Jan 27, 1998Sandisk CorporationMethod of making triple polysilicon flash EEPROM arrays having a separate erase gate for each row of floating gatesUS5712180Feb 28, 1996Jan 27, 1998Sundisk CorporationEEPROM with split gate source side injectionUS5747359Jan 23, 1997May 5, 1998Sandisk CorporationMethod of patterning polysilicon layers on substrateUS5751038Nov 26, 1996May 12, 1998Philips Electronics North America CorporationElectrically erasable and programmable read only memory (EEPROM) having multiple overlapping metallization layersUS5756385Nov 22, 1995May 26, 1998Sandisk CorporationDense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacersUS5786988Jul 2, 1996Jul 28, 1998Sandisk CorporationIntegrated circuit chips made bendable by forming indentations in their back surfaces flexible packages thereof and methods of manufactureUS5847425Nov 17, 1994Dec 8, 1998Sandisk CorporationDense vertical programmable read only memory cell structures and processes for making themUS5851881Oct 6, 1997Dec 22, 1998Taiwan Semiconductor Manufacturing Company, Ltd.Method of making monos flash memory for multi-level logicUS5867429Nov 19, 1997Feb 2, 1999Sandisk CorporationHigh density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gatesUS5883409Aug 7, 1997Mar 16, 1999Sandisk CorporationEEPROM with split gate source side injectionUS5923976Mar 17, 1997Jul 13, 1999Lg Semicon Co., Ltd.Nonvolatile memory cell and method of fabricating the sameUS5943572Jul 2, 1996Aug 24, 1999Siemens AktiengesellschaftElectrically writable and erasable read-only memory cell arrangement and method for its productionUS5962889Jul 31, 1996Oct 5, 1999Sharp Kabushiki KaishaNonvolatile semiconductor memory with a floating gate that has a bottom surface that is smaller than the upper surfaceUS5965913Apr 18, 1997Oct 12, 1999Sandisk CorporationDense vertical programmable read only memory cell structures and processes for making themUS5981335Nov 20, 1997Nov 9, 1999Vanguard International Semiconductor CorporationMethod of making stacked gate memory cell structureUS5999448Dec 30, 1998Dec 7, 1999Fujitsu LimitedNonvolatile semiconductor memory device and method of reproducing data of nonvolatile semiconductor memory deviceUS6028336Aug 7, 1997Feb 22, 2000Sandisk CorporationTriple polysilicon flash EEPROM arrays having a separate erase gate for each row of floating gates, and methods of manufacturing such arraysUS6046935Jan 27, 1999Apr 4, 2000Kabushiki Kaisha ToshibaSemiconductor device and memory systemUS6048768Mar 11, 1999Apr 11, 2000United Semiconductor Copr.Method of manufacturing flash memoryUS6057580Jul 7, 1998May 2, 2000Kabushiki Kaisha ToshibaSemiconductor memory device having shallow trench isolation structureUS6069382Feb 11, 1998May 30, 2000Cypress Semiconductor Corp.Non-volatile memory cell having a high coupling ratioUS6072721Apr 23, 1998Jun 6, 2000Sony CorporationSemiconductor nonvolatile memory, method of data programming of same, and method of producing sameUS6103573Jun 30, 1999Aug 15, 2000Sandisk CorporationProcessing techniques for making a dual floating gate EEPROM cell arrayUS6151248Jun 30, 1999Nov 21, 2000Sandisk CorporationDual floating gate EEPROM cell array with steering gates shared by adjacent cellsUS6159801Apr 26, 1999Dec 12, 2000Taiwan Semiconductor Manufacturing CompanyMethod to increase coupling ratio of source to floating gate in split-gate flashUS6180457Sep 24, 1999Jan 30, 2001Samsung Electronics Co., Ltd.Method of manufacturing non-volatile memory deviceUS6208545Nov 17, 1997Mar 27, 2001Glenn J. LeedyThree dimensional structure memoryUS6222762Aug 7, 1997Apr 24, 2001Sandisk CorporationMulti-state memoryUS6235586Jul 13, 1999May 22, 2001Advanced Micro Devices, Inc.Thin floating gate and conductive select gate in situ doped amorphous silicon material for NAND type flash memory device applicationsUS6256225Feb 26, 1999Jul 3, 2001Micron Technology, Inc.Construction and application for non-volatile reprogrammable switchesUS6258665Mar 21, 2000Jul 10, 2001Kabushiki Kaisha ToshibaNon-volatile semiconductor memory device and method for manufacturing the sameUS6281075Jan 27, 1999Aug 28, 2001Sandisk CorporationMethod of controlling of floating gate oxide growth by use of an oxygen barrierUS6295227Nov 24, 1999Sep 25, 2001Kabushiki Kaisha ToshibaNon-volatile semiconductor memory deviceUS6297097Dec 8, 1998Oct 2, 2001Hyundai Electronics Industries Co., Ltd.Method for forming a semiconductor memory device with increased coupling ratioUS6391717Nov 27, 2000May 21, 2002Hyundai Electronics Industries Co., Ltd.Method of manufacturing a flash memory deviceUS6406961Dec 7, 2000Jun 18, 2002Winbond Electronics CorporationProcess for producing flash memory without mis-alignment of floating gate with field oxideUS6417538Jul 22, 1999Jul 9, 2002Samsung Electronics Co., Ltd.Nonvolative semiconductor memory device with high impurity concentration under field oxide layerUS6426529Jan 10, 2001Jul 30, 2002Mitsubishi Denki Kabushiki KaishaSemiconductor memoryUS6429072Jun 14, 1999Aug 6, 2002Nec CorporationMethod of forming a floating gate memory cell structureUS6509222Nov 22, 2000Jan 21, 2003Stmicroelectronics S.R.L.Process for manufacturing electronic devices comprising nonvolatile memory cells of reduced dimensionsUS6512263Sep 22, 2000Jan 28, 2003Sandisk CorporationNon-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of formingUS6518618Dec 3, 1999Feb 11, 2003Intel CorporationIntegrated memory cell and method of fabricationUS6522580Jun 27, 2001Feb 18, 2003Sandisk CorporationOperating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data statesUS6529410Sep 20, 2000Mar 4, 2003Advanced Micro Devices, Inc.NAND array structure and method with buried layerUS6559009Mar 29, 2001May 6, 2003Macronix International Co. Ltd.Method of fabricating a high-coupling ratio flash memoryUS6614684Jan 28, 2000Sep 2, 2003Hitachi, Ltd.Semiconductor integrated circuit and nonvolatile memory elementUS6624464Oct 29, 2001Sep 23, 2003Samsung Electronics Co., Ltd.Highly integrated non-volatile memory cell array having a high program speedUS6720610Dec 11, 2000Apr 13, 2004Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device and its manufacturing methodUS6738289Feb 26, 2001May 18, 2004Sandisk CorporationNon-volatile memory with improved programming and method thereforUS6762092Aug 8, 2001Jul 13, 2004Sandisk CorporationScalable self-aligned dual floating gate memory cell array and methods of forming the arrayUS6768161May 31, 2002Jul 27, 2004Kabushiki Kaisha ToshibaSemiconductor device having floating gate and method of producing the sameUS6770932May 13, 2003Aug 3, 2004Kabushiki Kaisha ToshibaSemiconductor memory device having a memory region and a peripheral region, and a manufacturing method thereofUS6806132Dec 8, 2003Oct 19, 2004Kabushiki Kaisha ToshibaSemiconductor device having two-layered charge storage electrodeUS6807095Dec 18, 2002Oct 19, 2004Sandisk CorporationMulti-state nonvolatile memory capable of reducing effects of coupling between storage elementsUS6888755Oct 28, 2002May 3, 2005Sandisk CorporationFlash memory cell arrays having dual control gates per memory cell charge storage elementUS6894930Jun 19, 2002May 17, 2005Sandisk CorporationDeep wordline trench to shield cross coupling between adjacent cells for scaled NANDUS6898121Jan 28, 2003May 24, 2005Sandisk CorporationDeep wordline trench to shield cross coupling between adjacent cells for scaled NANDUS6953970Mar 12, 2004Oct 11, 2005Sandisk CorporationScalable self-aligned dual floating gate memory cell array and methods of forming the arrayUS6974746Nov 20, 2003Dec 13, 2005Kabushiki Kaisha ToshibaMethod of manufacturing a nonvolatile semiconductor memory device having a stacked gate structureUS6987047Jun 8, 2005Jan 17, 2006Kabushiki Kaisha ToshibaMethod of manufacturing a nonvolatile semiconductor memory device having a stacked gate structureUS7026684Sep 15, 2004Apr 11, 2006Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS7078763Aug 27, 2003Jul 18, 2006Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device including improved gate electrodeUS7170786Mar 21, 2005Jan 30, 2007Sandisk CorporationDeep wordline trench to shield cross coupling between adjacent cells for scaled NANDUS7211866Apr 20, 2005May 1, 2007Sandisk CorporationScalable self-aligned dual floating gate memory cell array and methods of forming the arrayUS7355237Feb 13, 2004Apr 8, 2008Sandisk CorporationShield plate for limiting cross coupling between floating gatesUS7385015Sep 6, 2005Jun 10, 2008Exxonmobil Chemical Patents Inc.Trialkylaluminum treated supportsUS7582928Aug 3, 2007Sep 1, 2009Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device and its manufacturing methodUS20010001491Jan 10, 2001May 24, 2001Koji SakuiSemiconductor memory device having memory cells each having a conductive body of booster plate and a method for manufacturing the sameUS20020093073Oct 30, 2001Jul 18, 2002Kabushiki Kaisha ToshibaSemiconductor device having two-layered charge storage electrodeUS20050157549Jan 21, 2004Jul 21, 2005Nima MokhlesiNon-volatile memory cell using high-k material and inter-gate programmingUS20050199939Mar 12, 2004Sep 15, 2005Lutze Jeffrey W.Self aligned non-volatile memory cells and processes for fabricationUS20070161191Mar 22, 2007Jul 12, 2007Yuan Jack HScalable Self-Aligned Dual Floating Gate Memory Cell Array And Methods Of Forming The ArrayUS20070166919Mar 13, 2007Jul 19, 2007Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device and its manufacturing methodUS20080076217 *Sep 21, 2006Mar 27, 2008Henry ChienMethods of Reducing Coupling Between Floating Gates in Nonvolatile MemoryUS20080079059Apr 20, 2007Apr 3, 2008Eon Silicon Solution Inc.Method of manufacturing a nonvolatile semiconductor memory device and select gate device having a stacked gate structureEP0780902B1Jul 31, 1996Feb 18, 2004Sharp Kabushiki KaishaNonvolatile semiconductor memory and method for fabricating the sameEP1104023A1Nov 26, 1999May 30, 2001SGS-THOMSON MICROELECTRONICS S.r.l.Process for manufacturing electronic devices comprising non-volatile memory cells* Cited by examinerNon-Patent CitationsReference1Aritome et al, "A Novel Side-Wall Transfer-Transistor Cell (SWATT Cell) for Multi-Level NAND EEPROMs", 1995 IEEE International Solid-State Circuits Conference, IEDM 95, pp. 275-278.2Aritome et al., "A 0.67 um2 Self-Aligned Shallow Trench Isolation Cell (SA-STI CELL) for 3V-only 256 Mbit NAND EEPROMs", IEDM Technical digest, pp. 61-64 (1994).3Aritome, "Advanced Flash Memory Technology and Trends for File Storage Application," IEDM Technical Digest, International Electronic Devices Meeting, IEEE, San Francisco, California, Dec. 10-13, 2000, pp. 33.1.1-33.1.4.4Chan et al., A True-Single-Transistor Oxide-Nitide-Oxide EEPROM Device, IEEE Electron Device Letters, vol. EDL-8, No. 3, Mar. 1987, pp. 93-95.5Cho et al., A Dual-Mode NAND Flash Memory: 1Gb Multilevel and High-Performance 512-Mb Single-Level Modes, IEEE Journal of Solid-State Circuits, vol. 36, No. 11, pp. 1700-1706 (2001).6DiMaria et al., Electrically-alterable read-only-memory using Si-rich SI02 Injectors and a floating polycrystalline silicon storage layer, J.Appl. Phys. 52(7), Jul. 1981m pp. 4825-4842.7Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.8EPOIISA, "International Search Report", mailed in PCT/US02/25025 on Apr. 4, 2003, 4 pages.9Hori et al., "A MOSFET with Si-implanted Gate-Sin, Insulator for Nonvolatile Memory Applications," IDEM 92, Apr. 1992, pp. 469-472.10Image File Wrapper for U.S. Appl. No. 09/925,102, filed Aug. 08, 2001, now U.S. Patent No. 6,762,092, issued Jul. 13, 2004.11Image File Wrapper for U.S. Appl. No. 10/175,764, filed Jun. 19, 2002, now U.S. Patent No. 6,894,930, issued May 17, 2005.12Image File Wrapper for U.S. Appl. No. 10/353,570, filed Jan. 28, 2003, now U.S. Patent No. 6,898,121, issued May 24, 2003.13Image File Wrapper for U.S. Appl. No. 10/799,180, filed Mar. 12, 2004, now U.S. Patent No. 6,953,970, issued Oct. 11, 2005.14Image File Wrapper for U.S. Appl. No. 11/086,648, filed Mar. 21, 2005, now U.S. Patent No. 7,170,786, issued Jan. 30, 2007.15Image File Wrapper for U.S. Appl. No. 11/111,129, filed Apr. 20, 2005, now U.S. Patent No. 7,211,866, issued May 1, 2007.16Image File Wrapper for U.S. Appl. No. 11/689,775, filed Mar. 22, 2007.17Image File Wrapper for U.S. Appl. No. 11/693,769, filed Mar. 30, 2007 now U.S. Patent No. 7,512,005, issued Mar. 31, 2009.18Image File Wrapper for U.S. Appl. No. 12/363,165, filed Jan. 30, 2009.19Lee, Jae-Duk, et al., "Effects of Parasitic Capacitance on NAND Flash Memory Cell Operation," NonVolatile Semiconductor Memory Workshop, IEEE, Monterey, California, Aug. 12-16, 2001, pp. 90-92.20Nozaki et al., "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application," IEEE Journal o/Solid State Circuits, vol. 26, No. 4, Apr. 1991, pp. 497-501.21Office Action for corresponding PRC Patent Application No. 02815618.8, mailed May 16, 2006, 9 pages.22Office Action in related Japanese Patent Application No. 2003-519998 mailed May 29, 2009.23Office Action in related Korean Application No. 2004-7002026 Action mailed Nov. 3, 2008.24Office Action in related Korean Application No. 2004-7020775 Action mailed Sep. 30, 2009.25Office Action in related PRC (China) Patent Application No. 02815618.8 mailed Jun. 5, 2009.26Office Action in related PRC (China) Patent Application No. 03813980.4 mailed Oct. 13, 2006.27Takeuchi, Y., et al., "A Self-Aligned STI Process Integration for Low Cost and Highly Reliable 1 Gbit Flash Memories," 1998 Symposium on VLSI Technology; Digest of Technical Papers, IEEE, Honolulu, Hawaii, Jun. 9-11, 1998, pp. 102-103.Classifications U.S. Classification438/257, 438/266, 438/263, 438/264International ClassificationH01L21/336Cooperative ClassificationH01L27/11524, G11C16/0483, H01L27/115, H01L27/11521European ClassificationH01L27/115F4N, H01L27/115, G11C16/04N, H01L27/115F4Legal EventsDateCodeEventDescriptionAug 14, 2007ASAssignmentOwner name: SANDISK CORPORATION,CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOKHLESI, NIMA;REEL/FRAME:019693/0847Effective date: 20070626May 11, 2011ASAssignmentOwner name: SANDISK TECHNOLOGIES INC., TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:026259/0619Effective date: 20110404Nov 27, 2013FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services