Source: http://www.google.com/patents/US20010005618?dq=645576
Timestamp: 2014-03-10 14:13:46
Document Index: 753472366

Matched Legal Cases: ['art 5', 'art 5', 'art 5', 'art 5', 'art 1', 'art 1', 'art 1', 'art 1', 'art 5']

Patent US20010005618 - Process for fabricating a network of nanometric lines made of single-crystal ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall...http://www.google.com/patents/US20010005618?utm_source=gb-gplus-sharePatent US20010005618 - Process for fabricating a network of nanometric lines made of single-crystal silicon and device obtainedAdvanced Patent SearchPublication numberUS20010005618 A1Publication typeApplicationApplication numberUS 09/738,870Publication dateJun 28, 2001Filing dateDec 15, 2000Priority dateDec 16, 1999Also published asEP1109209A1, US6583451Publication number09738870, 738870, US 2001/0005618 A1, US 2001/005618 A1, US 20010005618 A1, US 20010005618A1, US 2001005618 A1, US 2001005618A1, US-A1-20010005618, US-A1-2001005618, US2001/0005618A1, US2001/005618A1, US20010005618 A1, US20010005618A1, US2001005618 A1, US2001005618A1InventorsThomas Skotnicki, Malgorzata Jurczak, Didier DutartreOriginal AssigneeStmicroelectronics S.A.Export CitationBiBTeX, EndNote, RefManClassifications (19), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetProcess for fabricating a network of nanometric lines made of single-crystal silicon and device obtainedUS 20010005618 A1Abstract The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other. Images(3) Claims(14)
That which is claimed is: 1. Process for fabricating a network of nanometric lines made of single-crystal silicon on an insulating substrate, characterized in that it comprises: (a) the production of a substrate comprising a silicon body (1), a lateral isolation (2) defining in the body (1) a central part, a recess (3) formed in the central part having a bottom wall made from dielectric material, preferably SiO2, a first pair of opposed parallel sidewalls made from dielectric material, preferably SiO2, and a second pair of opposed parallel sidewalls, at least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon (5); (b) the growth by epitaxy in the recess (3), from the sidewall made from single-crystal silicon (5) of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy (6) and of single-crystal silicon (7); and (c) the etching of the lines made of single-crystal SiGe alloy (7), in order to form in the recess (3) a network of parallel lines made of single-crystal silicon (7) insulated from each other. 2. Process according to claim 1 , characterized in that the two opposed parallel sidewalls of the second pair of sidewalls of the recess are formed from single-crystal silicon (5, 5′) and in that the epitaxial growth of the alternating lines (6, 7) is carried from the two opposed parallel sidewalls made of single-crystal silicon. 3. Process according to claim 1 or 2 , characterized in that the alternating lines (6, 7) have a width less than 100 nm. 4. Process according to claim 3 , characterized in that the alternating lines (6, 7) have a width of 5 to 20 nm. 5. Process according to any one of the preceding claims, characterized in that the production of the substrate of step (a) comprises: obtaining a solid substrate made of single-crystal silicon (1) comprising a lateral isolation (2) defining a central part of the solid substrate; masking and etching of the central part in order to form therein a recess (3) having a bottom wall, a first pair of opposed parallel sidewalls made of dielectric material and a second pair of opposed parallel sidewalls, at least one of the walls of which is formed by single-crystal silicon (5); treatment of the bottom wall of the recess in order to increase the silicon oxidation rate therein; formation, on the bottom wall and the opposed parallel sidewalls of the second pair, of a silicon oxide layer (4) which is thicker on the bottom wall than on the opposed sidewalls; and isotropic etching of the silicon oxide in order to remove the silicon oxide layer from the opposed parallel sidewalls of the second pair, while leaving a silicon oxide layer on the bottom wall of the recess (3). 6. Process according to claim 5 , characterized in that the step of treating the bottom wall comprises a vertical implantation of a high dose of an element or of a compound which accelerates the oxidation of the single-crystal silicon. 7. Process according to claim 6 , characterized in that the elements are chosen from Si, In and As and the compound is BF2. 8. Process according to any one of claims 1 to 4 , characterized in that production of the substrate of step (a) comprises: obtaining a so-called SOI substrate comprising a stack of a lower layer made of single-crystal silicon (1 a), a silicon oxide interlayer (1 b) and an upper layer comprising a central part made of single-crystal silicon (1 c) bounded by a lateral isolation (2); the formation on the upper layer of a thin silicon oxide layer (8); the formation on the thin silicon oxide layer (8) of a mask (9); the etching through the mask (9) of the thin silicon oxide layer (8) and of the central part (1 c) of the upper layer of the SOI substrate, stopping on the silicon oxide interlayer (1 b), so as to form a recess (3) having a bottom wall made of silicon oxide, a first pair of opposed parallel sidewalls made of dielectric material and a second pair of opposed parallel sidewalls, at least one of which is formed from single-crystal silicon (5); and the removal of the mask (9). 9. Device comprising a substrate having a single-crystal silicon body (1) and a lateral isolation (2) defining in the body a central part, characterized in that the central part of the body (1) comprises a recess (3) and, in this recess, a network of parallel lines made of single-crystal silicon (7), which lines are spaced apart and insulated from each other. 10. Device according to claim 9 , characterized in that the recess comprises a bottom wall (4) made of dielectric material and in that the lines (7) of the network lie on this bottom wall. 11. Device according to claim 10 , characterized in that the bottom wall (4) is made of SiO2. 12. Device according to any one of claims 9 to 11 , characterized in that the network of lines (7) is buried. 13. Device according to anyone of claims 9 to 12 , characterized in that the lines (7) of the network are insulated from each other by a gaseous or solid dielectric material. 14. Device according to any one of claims 9 to 13 , characterized in that the single-crystal silicon lines (7) have a width of from 5 to 20 nm. Description
FIELD OF THE INVENTION [0001] The present invention generally relates to semiconductor manufacturing, and, more particularly to processes for fabricating a network of nanometric lines made of single-crystal silicon on an insulating substrate. BACKGROUND OF THE INVENTION [0002] A network of lines made of single-crystal silicon on an insulating substrate may be a very promising structure for applications in the fabrication of transistors, memories, optoelectronic devices and others. A network of lines made of single-crystal silicon on an insulating substrate may be obtained, of course, by photolithography and etching of a substrate of the SOI (silicon on insulator) type. However, this approach can only provide lines and interline spacings within the resolution limit of the photolithography process. Photolithography processes provide, at the very best, lines having a width of 100 nanometers or more to be obtained. [0003] It would therefore be desirable to have available a process for making lines made of single-crystal silicon of very small width, in particular less than 100 nanometers, to be obtained, so as to increase the integration of the devices obtained and also to promote mechanical and optoelectronic transport effects. SUMMARY OF THE INVENTION [0004] A feature of the present invention is therefore a process for fabricating a network of nanometric lines made of single-crystal silicon on an insulating substrate, and in particular of parallel nanometric lines of a width less than 100 nanometers. [0005] According to the invention, the process for fabricating a network of nanometric lines made of single-crystal silicon on an insulating substrate includes: (a) the production of a substrate comprising a single-crystal silicon body, a lateral isolation defining a central part in the body, a recess formed in the central part having a bottom wall made of dielectric material, preferably SiO2, a first pair of opposed parallel sidewalls made of dielectric material, preferably SiO2, and a second pair of opposed parallel sidewalls, at least one of the sidewalls of the second pair being formed from single-crystal silicon; (b) the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon; and (c) the etching of the lines made of single-crystal SiGe alloy, to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other. [0006] Use of the epitaxial growth technique to construct the lines of the structure according to the invention makes it possible to chose, virtually as required, the fineness of the lines. Furthermore, the use of the etching selectivity between the SiGe alloy and silicon allows the network of single-crystal silicon lines to be constructed on the insulating substrate having well-defined dimensions and virtually any fineness required by the designer. [0007] Another major advantage of the process of the invention is that it can be implemented either from a solid single-crystal silicon substrate or from a conventional so-called SOI (Silicon On Insulator) substrate. [0008] In an alternative embodiment of the invention, the opposed parallel sidewalls of the second pair of sidewalls of the recess formed in the central part of the silicon body of the substrate are formed by single-crystal silicon and the epitaxial growth of the alternating network of parallel lines made of single-crystal SiGe alloy and of lines made of single-crystal silicon is carried out from these two opposed parallel sidewalls. [0009] Preferably, the width (fineness) of the alternating lines of the network is from 5 to 20 nanometers. [0010] Because of the use of epitaxial growth to form the network of alternating lines, it is possible to choose, as required, the periodicity of the lines made of single-crystal silicon and of the interline spaces, as well as their width. However, care should be taken not to exceed the critical thicknesses (known to those skilled in the art), to avoid the risk of impairing the stress relaxation of the layers. [0011] In a first embodiment of the invention, the substrate of step (a) is obtained from a solid substrate made of single-crystal silicon comprising a lateral isolation defining a central part of the solid substrate; masking and etching of the central part to form therein a recess having a bottom wall, a first pair of opposed parallel sidewalls made of dielectric material and a second pair of opposed parallel sidewalls, at least one of the walls of which is formed by single-crystal silicon; treatment of the bottom wall of the recess to increase the silicon oxidation rate therein; formation, on the bottom wall and the opposed parallel sidewalls of the second pair, of a silicon oxide layer which is thicker on the bottom wall than on the opposed sidewalls; and isotropic etching of the silicon oxide in order to remove the silicon oxide layer from the opposed parallel sidewalls of the second pair, while leaving a silicon oxide layer on the bottom wall of the recess. [0012] In a second embodiment of the invention, the substrate of step (a) is obtained from a so-called SOI substrate including: a stack of a lower layer made of single-crystal silicon, a silicon oxide interlayer and an upper layer comprising a central part made of single-crystal silicon bounded by a lateral isolation; the formation on the upper layer of a thin silicon oxide layer; the formation on the thin silicon oxide layer of a mask; the etching through the mask of the thin silicon oxide layer and of the central part of the upper layer of the SOI substrate, stopping on the silicon oxide interlayer, so as to form a recess having a bottom wall made of silicon oxide, a first pair of opposed parallel sidewalls made of dielectric material and a second pair of opposed parallel sidewalls, at least one of which is formed from single-crystal silicon; and the removal of the mask. [0013] Preferably, the opposed parallel sidewalls made of dielectric material of the first pair of sidewalls are formed by walls of the lateral isolation, generally made of silicon oxide (SiO2) Preferably, when one of the sidewalls of the second pair of sidewalls is not made of single-crystal silicon, this sidewall is formed by a wall of the lateral isolation, generally made of silicon oxide (SiO2). [0014] The present invention also relates to a device comprising a substrate having a single-crystal silicon body and a lateral isolation defining in the body a central part. The central part comprises a recess. This device includes, in the recess, a network of parallel lines made of single-crystal silicon, which lines are spaced apart and insulated from each other. Preferably, these single-crystal silicon lines lie on a bottom wall, made of dielectric material such as SiO2, of the recess. Preferably, also, the single-crystal silicon lines are buried with respect to the upper surface of the single-crystal silicon body, i.e. the upper surfaces of these lines lie in the plane of the upper surface of the single-crystal silicon body or below this surface. [0015] The spaces between the single-crystal silicon lines may be formed from a gaseous dielectric material such as air or from a solid dielectric material such as, for example, SiO2 or Si3N4. The width of the single-crystal silicon lines and of the interline spaces is generally from 5 to 20 nanometers. BRIEF DESCRIPTION OF THE DRAWINGS [0016] The rest of the description refers to the appended figures which show respectively: [0017]FIGS. 1a to 1 c are cross-sectional views illustrating the main steps of the process for fabricating the network of nanometric lines made of single-crystal silicon according to the invention; [0018]FIGS. 2a to 2 e are cross-sectional views illustrating the main steps of a process for obtaining a substrate corresponding to the substrate of FIG. 1a starting from a solid substrate made of silicon; and [0019]FIGS. 3a to 3 c are cross-sectional views illustrating the main steps of a process for obtaining a substrate similar to that of Figure la starting from a conventional SOI substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0020] The steps in the fabrication of a network of nanometric lines made of single-crystal silicon on an insulating substrate according to the invention are shown with reference to the figures, and in particular to FIGS. 1a to 1 c. [0021] As shown in FIG. 1a, the first step includes obtaining a substrate having a single-crystal silicon body 1 and a lateral isolation 2 defining a central part in the body. As is well known, the lateral isolation 2 generally defines a parallelepipedal central part. This central part is provided with a recess 3, generally of parallelepipedal shape, having a horizontal bottom wall and vertical sidewalls. The bottom wall of the recess 3 is coated with a silicon oxide layer 4. A sidewall of the recess 3 is defined by a single-crystal silicon layer 5, whereas the opposite vertical sidewall may be formed by a wall of the lateral isolation 2 or by a vertical layer 5′ (shown in dotted lines in FIG. 1a) similar to the layer 5. The vertical layer 5 and possibly the vertical single-crystal silicon layer 5′ are coated generally on their upper surface with a thin silicon oxide layer. The two other opposed sidewalls of the recess are formed from a dielectric material and preferably by a wall of the lateral isolation 2. [0022] The next step, as shown in FIG. 1b, is the epitaxial growth, from the vertical sidewall made of single-crystal silicon 5, of parallel lines alternating between a silicon and germanium alloy 6 and single-crystal silicon 7 in the recess 3 on the silicon oxide layer 4. Any conventional process can be used for the epitaxial growth of the alternating lines. Naturally, depending on the epitaxial growth conditions, both the width of the lines and the pitch of the alternating lines can be adjusted. This formation of alternating lines can be made to fill the recess 3 partially or completely. [0023] The silicon/germanium alloys used in the present invention are well known. Among these alloys, mention may be made of the alloys Si1-xGex where 0<x<1 and the alloys Si1-x-yGexCy where 0<x≦0.95 and 0<y≦0.5. Preferably, to facilitate the selective etching of SiGe alloys having a relatively high germanium content, preferably alloys for which x≧0.1, for example 0.1≦x≧0.3, will be chosen. [0024] The final step of the process include selective etching of the SiGe alloy lines, either by isotropic plasma etching or by etching using a well-known oxidizing chemistry. By way of example, a selective etching solution such as a solution of 40 ml 70% HNO3+1 ml H2O2+5 ml 0.5% HF can be used. [0025] SiGe alloys and their selective etching are described in French Patent 99/03470. [0026] The substrate described in FIG. 1a may, as previously indicated, be obtained either from a conventional solid single-crystal silicon substrate or from a conventional so-called SOI (Silicon On Insulator) substrate. [0027]FIGS. 2a to 2 e show the main steps for obtaining a substrate as shown in FIG. 1a from a conventional solid single-crystal silicon substrate. As is well known, the conventional solid single-crystal silicon substrate comprises a single-crystal silicon body 1 and a lateral isolation (STI) defining a central part in the body. [0028] As FIG. 2b shows, the process starts by conventionally forming, via a mask and by etching, a recess 3 in the central part of the single-crystal silicon body 1 so as to leave, on a wall of the isolation 2 bounding the central part, a single-crystal silicon part 5. The opposed parallel sidewall of the recess may be made either directly as shown in FIG. 2b by the lateral isolation 2 or by a silicon part similar to the part 5. [0029] Next, as shown in FIG. 2c, the bottom wall of the recess 3 is then treated to modify this single-crystal silicon bottom wall and provide it with a higher oxidation rate than the single-crystal silicon vertical part 5 forming one of the sidewalls of the recess 3. This treatment may advantageously be a high-dose implantation of an appropriate element or compound. Among appropriate elements promoting the oxidation rate of single-crystal silicon, mention may be made of silicon, indium and arsenic. Among compounds, boron fluoride BF2 may be mentioned. This implantation is carried out perpendicularly to the bottom wall of the recess 3 so that only the latter, and not the vertical wall 5 of the recess, is modified. [0030] This process for modifying the oxide growth rate of a single-crystal silicon surface is known and is described, for example, in the article by M. JURCZAK et al. �Investigation on the suitability of vertical MOSFET's for high speed (RF) CMOS applications�, ESSDERC Proceedings 1998, pp. 172-175, Editions Frontieres, Bordeaux 1998. [0031] The structure obtained at step 2 c is then subjected to a conventional oxidation as shown in FIG. 2d in order to form, on the bottom wall and on the sidewalls of the recess 3, a silicon oxide layer 4. Because of the previous treatment, the layer thus formed is thicker on the bottom wall of the recess than on the sidewalls of the recess, and in particular thicker than on the untreated single-crystal silicon wall 5 and on the opposed sidewall of the recess. Of course, the upper surface of the single-crystal silicon sidewall 5 is also covered with a silicon oxide layer with a thickness similar to that covering the bottom wall of the recess, since this surface is also treated during the previous treatment. [0032] Next follows the removal by etching, for example conventional chemical etching, of the silicon oxide layer covering the opposed sidewalls of the recess. Given that the silicon oxide layer 4 covering the bottom wall of the recess 3 is thicker than that covering the opposed sidewalls of this recess, the etching step makes it possible to expose the opposed sidewalls of the recess and in particular the wall formed by the single-crystal silicon part 5, while keeping a silicon oxide layer on the bottom wall of the recess, and thus to obtain the substrate as shown in FIG. 1a. [0033] With reference to Figures to 3 a to 3 c, the production of a substrate as shown in FIG. 1a from a conventional so-called SOI substrate, will now be described. As shown in FIG. 3a, the conventional SOI substrate comprises a stack of a lower single-crystal silicon layer 1 a, an silicon oxide interlayer 1 b and an upper layer formed by a central single-crystal silicon part 1 c bounded by a lateral isolation 2. Initially, a thin silicon oxide layer 8 is formed on the upper layer, then a resin mask 9 is formed on this silicon layer. [0034] As shown in FIG. 3b, the mask 9 has an opening which is off-centred with respect to the central part 1 c, so as to cover a portion of the central single-crystal silicon part 1 c adjacent to a sidewall of the isolation 2. Next, the etching of the thin silicon oxide layer 8 and of the central single-crystal silicon part 1 c are carried out via the mask, the etching stopping on the silicon oxide interlayer 1 b, to form a recess 3 whose bottom wall is formed by silicon oxide (the silicon oxide of the interlayer 1 b) and two opposed sidewalls of which are formed, one by the unetched single-crystal silicon part 5 since it is under a part of the mask 9 and the other by the lateral isolation 2. After conventional removal of the mask 9, a substrate similar to that described in connection with FIG. 1a is obtained. [0035] Of course, in the processes described in connection with FIGS. 2a to 2 e and 3 a to 3 c, it is also possible to construct two opposed sidewalls of the recess 3 which are formed from single-crystal silicon by providing an etching mask of the appropriate shape. Classifications U.S. Classification438/479, 257/E21.562, 257/E21.131, 438/481, 438/149International ClassificationH01L21/762, H01L29/06, H01L21/20Cooperative ClassificationH01L29/0673, B82Y10/00, H01L21/2018, H01L29/0665, H01L21/76262, H01L29/0676European ClassificationB82Y10/00, H01L29/06C6W2, H01L29/06C6W4, H01L29/06C6, H01L21/762D10Legal EventsDateCodeEventDescriptionNov 30, 2010FPAYFee paymentYear of fee payment: 8Dec 5, 2006FPAYFee paymentYear of fee payment: 4Mar 8, 2004ASAssignmentOwner name: STMICROELECTRONICS SA, FRANCEFree format text: CORRECTED ASSIGNMENT DOCUMENT TO PROVIDE CORRECT ASSIGNEE ENTITY ON REEL 011587, FRAME 0368;ASSIGNORS:SKOTNICKI, THOMAS;JURCZAK, MALGORZATA;DUTARTRE, DIDIER;REEL/FRAME:015044/0266;SIGNING DATES FROM 20040129 TO 20040202Owner name: STMICROELECTRONICS SA 29, BOULEVARD ROMAIN ROLLANDFree format text: CORRECTED ASSIGNMENT DOCUMENT TO PROVIDE CORRECT ASSIGNEE ENTITY ON REEL 011587, FRAME 0368;ASSIGNORS:SKOTNICKI, THOMAS /AR;REEL/FRAME:015044/0266;SIGNING DATES FROM 20040129 TO 20040202Mar 14, 2001ASAssignmentOwner name: STMICROELECTRONICS S.A., FRANCEFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SKOTNICKI, THOMAS;JURCZAK, MALGORZATA;DUTARTRE, DIDIER;REEL/FRAME:011587/0368;SIGNING DATES FROM 20010129 TO 20010202Owner name: STMICROELECTRONICS S.A. 7, AVENUE GALLIENI F-94250Owner name: STMICROELECTRONICS S.A. 7, AVENUE GALLIENIF-94250Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SKOTNICKI, THOMAS /AR;REEL/FRAME:011587/0368;SIGNING DATES FROM 20010129 TO 20010202RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google