Source: http://www.google.com/patents/US20050166207?dq=inassignee:Temic
Timestamp: 2016-06-30 14:39:42
Document Index: 136125582

Matched Legal Cases: ['art 400', 'art 500', 'art 600', 'art 700', 'art 300', 'art 200', 'art 401', 'art 501', 'art 601', 'art 701', 'art 301', 'art 201', 'art 400', 'art 500', 'art 600', 'art 400', 'art 300', 'art 300', 'art 700', 'art 400']

Patent US20050166207 - Self-optimizing computer system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsProvided is a self-optimizing computer system that can achieve ultimate optimization (improvement in the speed) by preparing a mechanism that can observe the behavior of the program execution in the self-optimizing computer system and optimize dynamically depending on the execution behavior of program....http://www.google.com/patents/US20050166207?utm_source=gb-gplus-sharePatent US20050166207 - Self-optimizing computer systemAdvanced Patent SearchPublication numberUS20050166207 A1Publication typeApplicationApplication numberUS 11/020,153Publication dateJul 28, 2005Filing dateDec 27, 2004Priority dateDec 26, 2003Publication number020153, 11020153, US 2005/0166207 A1, US 2005/166207 A1, US 20050166207 A1, US 20050166207A1, US 2005166207 A1, US 2005166207A1, US-A1-20050166207, US-A1-2005166207, US2005/0166207A1, US2005/166207A1, US20050166207 A1, US20050166207A1, US2005166207 A1, US2005166207A1InventorsTakanobu Baba, Takashi Yokota, Kanemitsu OtsuOriginal AssigneeNational University Corporation Utsunomiya UniversityExport CitationBiBTeX, EndNote, RefManPatent Citations (13), Referenced by (46), Classifications (8), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetSelf-optimizing computer system
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to computer system, and more specially self-optimizing computer system comprising multiple processing units. [0003] 2. Related Art Statement [0004] The multiple processing units are incorporated in single computer system, and a role depending on execution situation of a program is assigned to each of the processing units so that effective optimization can be performed and resulting processing speed can be improved. [0005] As a first conventional technology, there is a multi-computer/multi-thread processor technology as described in JP 2003-30050 “multi-thread execution method and parallel processor system”. This technology realizes improvement of the speed by utilizing two kinds of parallelism using the multiple processing units. Specifically, these are the instruction level parallelism which executes two or more instructions simultaneously in a single processing unit, and the thread level parallelism which parallelizes using a instruction sequence (thread) as a unit. Improvement in the speed is realized by the combination of these two kinds of parallelism. In the parallel computer or the multithread computer system, in order to use effectively the multiple processing units incorporated so as to achieve improvement in the speed, it is indispensable to fully exploit the parallelism in each of a instruction level and a thread level (or parallel processing). However, since the general application program is not described to fully exploit the parallelism in these levels, there is a problem that parallelism extraction by the compiler cannot fully be performed. That is, even if there are the multiple processing units, it is a problem that it is difficult to realize high-speed processing or to maintain the high-speed processing by working them simultaneously in parallel. [0006] As a second conventional technology, there is a static optimization/optimization compiler technology as described in JP2001-147820 “code optimization method and storing medium.” This technology realizes improvement in the speed by analyzing logically procedures described as a program, and applying said two kinds of parallelizing technology (the instruction level parallelism and the thread level parallelism). Another compiler technology is also used which improves the optimization effect by once executing the program and recording (profiling) the behavior of the program at that time. Although the optimization compiler tries to solve the parallelism extraction problem, there is a problem that the effect of optimization is limited, because the range analyzable at the time of compilation is limited generally. Moreover, although the method of acquiring the more advanced optimization effect based on the result of profiling is also used. However, since the program execution behavior information collected is the cumulative result through an observation period, the method just performs average improvement in the speed through the whole execution time is possible, and there is a problem that it cannot respond to the small change of the behavior. Moreover, when the execution in the program is dependent on input data, there is a problem that the speed improvement effect according to this technology may not be obtained. [0007] As a third conventional technology, there is a dynamic optimization technology as described in JP 2002-222088 “compilation system, compilation method and program.” Also there is a technology that optimizes (or recompiles) the program code based on the information extracted during program execution. There is a technology that in order to perform the optimization depending on the dynamic behavior of the program, the behavior during the program execution is observed and a more suitable program code is generated if needed. Since this technology needs to add a process for behavior observation to the original application program, or to run a program for observation separately, the efficiency is degraded due to the overhead of observation cost in both cases. Furthermore, since the overhead for performing the optimization process is imposed during execution, there is a problem that the performance improvement according to the optimization is canceled. [0008] It is desired that the performance is improved by changing the internal configuration of the computer or the code of the program depending on the execution behavior of the program. An object of the invention is to provide a self-optimizing computer system that can achieve ultimate optimization (improvement in the speed) by preparing a mechanism that can observe the program performed concurrently in the self-optimizing computer system and by performing dynamically the optimization depending on the execution behavior of program. In the invention, the computer system is assumed in that the multiple processing units having two or more arithmetic units respectively are arranged. The instruction level parallelism can be applied within the processing unit, and the parallel processing or the thread level parallelism can be applied by using the multiple processing units. The invention solves the problems about the conventional multithread type computer system mentioned above, and realizes the self-optimizing computer system for performing the optimization dynamically efficiently. SUMMARY OF THE INVENTION [0009] The foregoing objects are achieved by a self-optimizing computer system comprising multiple processing units, characterized in that each of the processing units operates as at least one of an operation processing unit for executing a program, an observation processing unit for observing the behavior of the program under execution, an optimization processing unit for performing an optimization process according to the observation result of the observation processing unit, and a resource management processing unit for performing a resource management process of whole of the system such as a change of the contents of execution. That is, the observation processing unit group that does not execute the application program but performs behavior observation, observes state of the operation processing unit group that is in charge of execution of the application program originally made into the purpose, the optimization processing unit group performs optimization using the observation result of the observation processing unit group, and the resources management processing unit group performs the management and the control of the whole operation of the computer system. [0010] An embodiment of a self-optimizing computer system according to the invention is characterized in that each of the processing units has a function that allows changing dynamically an execution state of the operation processing unit and the executed program itself, and the optimization processing unit generates an optimal program code in real time based on the observation result of the behavior of the program observed by the observation processing unit, and changes dynamically the execution procedures of the operation processing unit. Thereby, the application program can be executed with the optimal efficient code always. [0011] Another embodiment of a self-optimizing computer system according to the invention is characterized in that a ratio of the numbers of the operation processing unit, the observation processing unit, the optimization processing unit, and resource management processing unit is changed depending on the optimization state of the program. In the state that the optimization less advanced yet, it can obtain the optimization code having an improved execution efficiency at an early stage by assigning the many processing units to observation processing and optimization processing, and optimization time is shortened. In the stage that the optimization more advanced, since there is no necessity of performing optimization more than it not much, the number of the processing units which are assigned to execution of the application program is increased more so that the processing speed can be improved more. In this way, the optimal role distribution depending on the execution state of the program can be performed. Moreover, even if once it becomes in the optimal state, the optimal state does not necessarily continue depending on the program, in this case, the observation processing unit group detects change of the behavior of the program, responds to the change at an early stage, and assigns the many processing units to the observation processing and the optimization processing again so that it can respond to the behavior change of the program at an early stage and obtain the optimal program code. The resources management processing unit group performs processing of such dynamic role changes. [0012] Since the optimization can be performed while observing the execution state of the program in real time, the control for always taking out the maximum capability of hardware can be performed. The maximum extraction of the instruction level parallelism and thread level parallelism which are the purpose of the invention becomes possible by using the multiple identical processing units and maintaining always them in the optimal state by said optimization function. Furthermore, the function and the capability of the processing units in the system can be availed maximally by performing the role distribution of the processing units for executing the application program and the other processing units for observation, optimization and resources management, and allowing to change the role distribution depending on the state of the optimization. That is, in the state that the optimization advanced less, it is possible to obtain the optimization code at an early stage by concentrating on the observation processing of the program behavior and the optimization processing, and in the state that the optimization advanced more, it is possible to realize the maximum execution performance by concentrating on the execution of the application program which is original purpose. Moreover, by assigning the processing units which are not used for the operation processing to the functions of observation, optimization, and resources management, it becomes possible to perform dynamic optimization, without affecting the execution performance of the application program at all.
BRIEF DESCRIPTION OF THE DRAWINGS [0013] FIG. 1 is a block diagram showing a construction of an embodiment of a self-optimizing computer system according to the invention. [0014] FIG. 2 is a block diagram showing a construction of a variation of the self-optimizing computer system shown in FIG. 1. [0015] FIG. 3 is a block diagram explaining a fundamental concept of the self-optimizing computer system according to the invention. [0016] FIG. 4 shows operation of each processing unit group of the self-optimizing computer system according to the invention in order of time. [0017] FIG. 5 show the change of a role assignment of each processing unit of the self-optimizing computer system according to the invention. [0018] FIG. 6 shows each organization shown in FIG. 5 based on FIG. 1. [0019] FIG. 7 shows each organization shown in FIG. 5 based on FIG. 1. [0020] FIG. 8 shows each organization shown in FIG. 5 based on FIG. 1. [0021] FIG. 9 shows an example of arrangement of each processing unit group of the self-optimizing computer system according to the invention. [0022] FIG. 10 shows another example of arrangement of each processing unit group of the self-optimizing computer system according to the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0023] FIG. 1 is a block diagram showing an organization of an embodiment of a self-optimizing computer system according to the invention. This self-optimizing computer system comprises multiple processing units 100, 101 . . . For the sake of clarity, only the processing units 100 and 101 are shown in FIG. 1. The multiple processing units operate in parallel to extract both the instruction level parallelism and the thread level parallelism. [0024] Typically, the processing unit 100 comprises a procedure storing part 400, an operation processing part 500, a memory control part 600, an inter-unit communication part 700, a profile information correction part 300, and a unit control part 200. Other unit processing units 101 and . . . comprises also the same composition elements, for example, the processing unit 101 comprises a process contents storing part 401, an operation processing part 501, a memory control part 601, an inter-unit communication part 701, a profile information correction part 301, and a unit control part 201. Hereinafter, only with reference to the processing unit 100 and its composition elements, it explains typically. The processing units are connected mutually via a control bus 800 and inter-unit communication path 820-1, 2 . . . , and each of the processing unit is connected to a storing device (not shown) via a memory bus 810. [0025] For example, a group comprised of the process contents storing part 400, the operation processing part 500, and the memory control part 600 can act as a usual processor (VLIW: Very Long Instruction Word processor). For example, it is also possible to realize the same function by the “flexible hardware” using the same technology as FPGA (Field Programmable Gate Array). [0026] The operation of the processing unit can be changed according to the process contents (program) stored in the procedure storing part 400 of the processing unit itself. Specifically, there are four kinds of threads, i.e., a resources management thread (RC (resource core)) which performs resources management of the whole system, an optimization thread (OF (optimizing fork)) which performs optimization processing, an observation thread (PF (profiling fork)) which observes the behavior of the program, and collects and analyzes profile information, and an operation thread (CF (computing fork)) which performs execution of an application program. Each thread corresponds to four functions which can be carried out in the processing unit, i.e., a function that performs the contents management such as change of execution, a function that generates optimized code, a function that observes behavior of the program, and a function that executes the application program, respectively. [0027] The processing unit 100 comprises a circuit for collecting the profile information (the profile information collection part 300). The profile information collection part 300 may have an operation function and a memory function, or have only a function to send information to the adjoining processing unit. The profile information collected in the part can be transferred to the other processing unit via the inter-unit communication path 820-1, 2 . . . by the inter-unit communication part 700. [0028] The processing unit 100 while performing the resource management thread (RC) has a function that can change the internal state of the other processing units by accessing to the process control part of the other processing units via the control bus 800. For example, each of the processing units can be changed into arbitrary roles by changing the contents of the procedure storing part 400. Moreover, it is also possible to change the code (operation thread) of the application program performed in the processing unit into the code optimized more. [0029] Although the role of the processing unit can also be statically decided before execution, it can also be dynamically changed during program execution by using said change function. [0030] The observation thread (PF) observes the state of execution of the program in the operation processing thread (CF). The optimization thread (OF) obtains the more suitable program (object code) and processing form by using the profile result obtained by the observation thread (PF). Consequently, if it is judged that execution efficiency improves, the resources management thread (RC) uses said change function to change the system into the state that is more suitable for execution. On the contrary, if it is judged as a result of the observation by the observation thread (PF) that the execution efficiency in the operation thread (CF) is lowered, the resources management thread (RC) changes the role assignment of each processing unit so that it can change into the composition which is suitable for behavior observation and optimization of the program. [0031] FIG. 2 is a block diagram showing an organization of a variation of the self-optimizing computer system shown in FIG. 1. [0032] FIG. 3 is a block diagram explaining a fundamental concept of the self-optimizing computer system according to the invention. The processing units 100-115 are the unit processing units with internal organization as shown in FIG. 1. The sign (RC, PF, OF, CF) written in the round mark in this figure is the abbreviated name of the thread corresponding to the processing function currently performed in each processing unit. Ellipses 900-920 express the groups (processing unit groups) of the processing units divided for every processing function. The groups are comprised of a resources management processing unit group 900, an optimization processing unit group 910, an observation processing unit group 920, and an operation processing unit group 930. The resources management processing unit group 900 has a function which controls each processing unit in the system. For this purpose, each processing unit is accessed via a control bus (800-1, 2, . . . ). The application program is executed by the operation processing unit group 930. The behavior information of the program under execution is reported in detail to the observation processing unit group 920 via the inter-unit communication path 820-1. The observation processing unit group 920 analyzes this information to observe the state of execution of the program. If the execution efficiency in the operation processing unit group 930 is inadequate and there is room to optimize further, the collected profile information is transmitted to the optimization processing unit group 910 via the inter-unit communication path 820-2. The optimization processing unit group 910 generates the code for executing the program more efficiently. The generated code is transmitted to the operation processing unit group 930 under control of the resources management processing unit group 900. Then, if it is judged that the role assignment of each processing unit needs to be changed, the processing units belonging to each processing unit group are changed by control of the resources management processing unit group 900. Since each processing unit group stores information required in order to perform predetermined processing, it can access the memory storage 1000 via the memory bus 810-1, -2, and -3. [0033] FIG. 4 shows operation of each of the processing unit groups of the self-optimizing computer system according to the invention in order of time. Reference numbers 100, 101-1-n, 102-1-n, 103-1-n, 104-1-n, 105-1-n, 106-1-n indicate said processing units respectively in this figure. The functional thread currently performed in each processing unit is outlined in a round mark like the above explanation. In this figure, an ellipse 900 is the resources management processing unit group, 930-1,930-2 are the operation processing unit groups, 920-1,920-2 are the observation processing unit groups, and 930-1, 930-2 are the optimization processing unit groups. The processing units are drawn in each of the processing unit groups. By drawing in piles the processing units assigned to each of the processing unit groups, it is expressing being processed in parallel inside the processing unit group concerned. Moreover, the change in the degree of pile is expressing increase and decrease of the number of the processing units assigned to the processing unit group. FIG. 4 is shown from the state when starting execution of the application program within the system. It is assumed that the application program is compiled beforehand and that the executable object code is prepared. First, the resources management processing unit group 900 operates to determine the role assignment of each of other processing unit, and to determine the unit processing units belonging to each of the operation processing unit group 930-1, the observation processing unit group 920-1, and the optimization processing unit group 910-1, respectively. Then the resources management processing unit group 900 determines the thread performed by other processing unit groups via the control bus, and prepares required setup etc. (b100). If preparation is completed, instructions (b110-1, b110-2) are sent to the operation processing unit group 930-1 and the observation processing unit group 920-1, and execution of each of the processing unit groups is started (b101). After the execution starts, since there is no role of the resources management processing unit group for the time being, the processing thread of the group is suspended (b102). The operation processing unit group 930-1 performs the given program (b120), and sends the information under execution to the observation processing thread (b130-1-n). The observation processing unit group 920-1 analyzes in detail the execution information sent from the operation processing unit group 930-1, and decides whether it became the situation that optimization is required (b140). If it is decided that optimization is required (b141), its information is sent to the resources management processing unit group 900 (b111-1). If this information is received, the resources management processing unit group 900 return from hibernation (b103), and activates of the optimization processing unit group 910-1 (b111-2). Then, the resources management processing unit group 900 is in hibernation, and it waits until the following event occurs (b104). After starting, the optimization processing unit group 910-1 receives the profile information of the program (b10-1-n) from the observation processing unit group 920-1, and performs optimization processing based on this information (b160). After optimization processing finishes (b-161), the optimization processing unit group notifies that to the resources management processing unit group 900 (b112-1), and is in hibernation (b162). The operation processing unit group 930-1 and the observation processing unit group 920-1 continue each execution as it is, while performing optimization processing by the optimization processing unit group 910-1 (b120, b142). If the resources management processing unit group 900 receives the notice of the optimization processing finish, it returns from hibernation (b105), and stops the operation processing unit 930-1 and the observation processing unit 920-1 temporarily (b112-2, b112-3). Then, the role assignment of each of the processing units is changed under management of the resources management processing unit group 900 (b121, b143). Consequently, it is changed into new composition and the operation processing unit group 930-2 and the observation processing unit group 920-2 are constructed. In this way, after changing so that the program can be performed more efficiently, operation of each of the processing unit groups 930-2,920-2 is started (b122, b144). Here, the application program performs the continuation from the time of being interrupted in b121. The operation (b131-1-n) which transmits the information under execution of the operation processing unit group 930-2 to the observation processing unit group 920-2 in detail is performed in like manner. If the observation processing unit group 920-2 detects the situation that the optimization is needed again (b145), in the same way as the operation after b141, the optimization processing unit group 930-2 sends the optimization request information to the resources management processing unit group 900 (b113-1), the resources management processing unit group 900 responds to the information, recovers from hibernation (b107), sends directions to the optimization processing unit group (910-2) (b113-2), and starts processing (b163). The optimization processing unit group 910-2 receives the required profile information from the observation processing unit group 920-2 (b151-1), and performs optimization processing (b163). In the meantime, the operation processing unit group 930-2 and the observation processing unit group 920-2 continue to perform (b122, b146). [0034] FIG. 5 illustrates the situation of change of the role assignment of each of the processing units shown in FIG. 4. This drawing consists of three drawings which show the situation of the role assignment of the processing unit of the system respectively. The upper drawing shows the situation that the optimization is not advanced much in the initial stage of the program. By assigning the many processing units to the observation processing unit group 920-1 and the optimization processing unit group 910-1, at the early stage of program execution, the object for optimization can be specified, and the optimization processing result can be obtained. The lower left-hand side drawing shows the situation that the optimization progressed to the degree in the middle. By assigning a little many processing units to the operation processing unit group 930-2, the processing performance is improved, at the same time, the point where optimization is further possible is looked for and optimized by the observation processing unit group 920-2 and the optimization processing unit group 910-2. The lower right-hand side drawing shows the situation that the optimization advanced highly. As a result of being optimized highly, a possibility of optimizing more becomes low. For this reason, the number of the processing units assigned to the observation processing unit group (920-3) and the optimization processing unit group (910-3) is decreased. The part is assigned to the operation processing unit group (930-3) so that the greatest processing performance is attained. As a result of observation by the observation processing unit group (920-3), if it is judged that the execution efficiency in the operation processing unit group (930-3) is getting worse, the resources management processing unit group 900 controls to change the assignment of each of the processing unit groups so that the optimal processing form according to the situation is attained by changing between these three drawings (as shown by bi-directional arrows in this figure). [0035] FIGS. 6-8 show each organization shown in FIG. 5 based on FIG. 1. In this figure, 100-111 show the unit processing unit respectively. In this figure, the number of each part in the processing unit is omitted. However, the contents of the functional processing currently performed in each of the processing unit is shown on the position of the procedure storing part of processing (400, 401 in FIG. 1) as the abbreviated name of the processing thread. For example, since the processing unit 100 of FIG. 6 executes the resources management thread, “RC” is written in the contents storing part. When starting execution of the application program (in the initial state), the role assignment as shown in FIG. 6 is performed. That is, the processing units are divided into the optimization processing unit group 910, the observation processing unit group 920, and the operation processing unit group 930 under management of the resources management processing unit group 900. If optimization processing advanced, as shown in FIG. 7, the ratio of the operation processing unit group 930 is increased, and the ratios of the observation processing unit group 920 and the optimization processing unit group 910 are decreased relatively. When there are few totals of the processing units, one processing unit is able to share two or more roles. In the case of FIG. 7, the processing unit 100 takes two roles; the resources management thread (RC) and the optimization thread (OF). By this reason, a resources management/optimization processing unit group 940 is created. FIG. 8 shows the state where the optimization advanced further and it is optimized to the maximum extent. Here, as a result of optimizing to the maximum extent, the situation which most of the processing units are assigned to the operation processing unit group 930 which manages execution of the program is shown. A few remaining processing units (one in FIG. 8) are assigned to the processes (RC, OF, PF) of resources management, optimization, and observation (a resources management/optimization/observation processing unit group 950). [0036] FIGS. 9 and 10 show examples of arrangement of each of the processing unit groups. For the sake of clarity, the area of the processing unit group is hatched. In the above explanation, only the number of the processing unit assigned to the processing unit group is mentioned, but a way of arrangement of these is not mentioned. In the embodiment of the invention mentioned above, since communication between the processing units is performed via the inter-unit communication path (820 in FIG. 1), if the processing unit groups are not arranged in consideration of the communicative situation, the information passing through the inter-unit communication path may carry out congestion, and it may become the factor which disturbs the improvement in the performance. For this reason, actually, it is necessary to consider the arrangement of the processing unit groups by which the load of the inter-unit communication path is decreased most. FIG. 9 is the example of arrangement of the processing unit groups in the state where the optimization less advanced (i.e. the initial state). Here, the two processing units are assigned to the operation processing unit group 930, and are communicating mutually. The observation processing unit group 920 is arranged so that the operation processing unit group 930 may be surrounded. Since the information on the execution behavior in the operation processing unit group flows toward an outside from the operation processing unit group 930, it does not disturb the communication inside the operation processing unit group. Furthermore, in the case of this figure, the result of the observation processing unit group 920 is considered as flowing without resistance to the optimization processing unit group 910. FIG. 10 is the example of the arrangement of the processing unit groups in the state where the optimization progressed more. In this example, the operation processing unit group 930 forms an annular communication path. The observation processing unit group 920 and the resources management/optimization processing unit group 940 are arranged so that communication along this annular communication path may not be disturbed. [0037] According to the invention, in the computer system which realizes improvement in the speed of the application program by using the multiple processing units, dynamic optimization can be performed by using the information acquired during this application program execution, and, much more improvement in the speed can be achieved. Therefore, the invention is applicable in large fields which requires a high-speed processing performance, such as high-performance computer, general-purpose microprocessor, and embedded processors. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6622300 *Apr 21, 1999Sep 16, 2003Hewlett-Packard Development Company, L.P.Dynamic optimization of computer programs using code-rewriting kernal moduleUS6820255 *Apr 18, 2001Nov 16, 2004Elbrus InternationalMethod for fast execution of translated binary code utilizing database cache for low-level code correspondenceUS6848099 *Oct 11, 2001Jan 25, 2005Intel CorporationMethod and system for bidirectional bitwise constant propogation by abstract interpretationUS6938247 *May 19, 2003Aug 30, 2005Sun Microsystems, Inc.Small memory footprint system and method for separating applications within a single virtual machineUS6954923 *Jul 7, 1999Oct 11, 2005Ati International SrlRecording classification of instructions executed by a computerUS7013459 *Nov 12, 2004Mar 14, 2006Microsoft CorporationProfile-driven data layout optimizationUS7140006 *Oct 11, 2001Nov 21, 2006Intel CorporationMethod and apparatus for optimizing codeUS7146607 *Sep 17, 2002Dec 5, 2006International Business Machines CorporationMethod and system for transparent dynamic optimization in a multiprocessing environmentUS7203935 *Dec 5, 2002Apr 10, 2007Nec CorporationHardware/software platform for rapid prototyping of code compression technologiesUS7210129 *Sep 28, 2001Apr 24, 2007Pact Xpp Technologies AgMethod for translating programs for reconfigurable architecturesUS7275242 *Oct 4, 2002Sep 25, 2007Hewlett-Packard Development Company, L.P.System and method for optimizing a programUS7278137 *Dec 26, 2002Oct 2, 2007Arc InternationalMethods and apparatus for compiling instructions for a data processorUS20030117971 *Dec 21, 2001Jun 26, 2003Celoxica Ltd.System, method, and article of manufacture for profiling an executable hardware model using calls to profiling functions* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7546588 *Sep 9, 2004Jun 9, 2009International Business Machines CorporationSelf-optimizable code with code path selection and efficient memory allocationUS7777748Sep 18, 2007Aug 17, 2010Lucid Information Technology, Ltd.PC-level computing system with a multi-mode parallel graphics rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphics applicationsUS7779223Aug 17, 2010International Business Machines CorporationMemory leakage managementUS7796129Sep 14, 2010Lucid Information Technology, Ltd.Multi-GPU graphics processing subsystem for installation in a PC-based computing system having a central processing unit (CPU) and a PC busUS7796130Oct 23, 2007Sep 14, 2010Lucid Information Technology, Ltd.PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operationUS7800610Oct 23, 2007Sep 21, 2010Lucid Information Technology, Ltd.PC-based computing system employing a multi-GPU graphics pipeline architecture supporting multiple modes of GPU parallelization dymamically controlled while running a graphics applicationUS7800611Oct 23, 2007Sep 21, 2010Lucid Information Technology, Ltd.Graphics hub subsystem for interfacing parallalized graphics processing units (GPUs) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC busUS7800619Sep 21, 2010Lucid Information Technology, Ltd.Method of providing a PC-based computing system with parallel graphics processing capabilitiesUS7808499Nov 19, 2004Oct 5, 2010Lucid Information Technology, Ltd.PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a routerUS7808504Oct 26, 2007Oct 5, 2010Lucid Information Technology, Ltd.PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applicationsUS7812844Jan 25, 2006Oct 12, 2010Lucid Information Technology, Ltd.PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics applicationUS7812845Oct 12, 2010Lucid Information Technology, Ltd.PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics applicationUS7812846Oct 26, 2007Oct 12, 2010Lucid Information Technology, LtdPC-based computing system employing a silicon chip of monolithic construction having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operationUS7834880Mar 22, 2006Nov 16, 2010Lucid Information Technology, Ltd.Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic constructionUS7843457Nov 30, 2010Lucid Information Technology, Ltd.PC-based computing systems employing a bridge chip having a routing unit for distributing geometrical data and graphics commands to parallelized GPU-driven pipeline cores supported on a plurality of graphics cards and said bridge chip during the running of a graphics applicationUS7940274Sep 25, 2007May 10, 2011Lucid Information Technology, LtdComputing system having a multiple graphics processing pipeline (GPPL) architecture supported on multiple external graphics cards connected to an integrated graphics device (IGD) embodied within a bridge circuitUS7944450Sep 26, 2007May 17, 2011Lucid Information Technology, Ltd.Computing system having a hybrid CPU/GPU fusion-type graphics processing pipeline (GPPL) architectureUS7961194Aug 30, 2007Jun 14, 2011Lucid Information Technology, Ltd.Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing systemUS8085273Dec 27, 2011Lucid Information Technology, LtdMulti-mode parallel graphics rendering system employing real-time automatic scene profiling and mode controlUS8125487Sep 26, 2007Feb 28, 2012Lucid Information Technology, LtdGame console system capable of paralleling the operation of multiple graphic processing units (GPUS) employing a graphics hub device supported on a game console boardUS8134563Oct 30, 2007Mar 13, 2012Lucid Information Technology, LtdComputing system having multi-mode parallel graphics rendering subsystem (MMPGRS) employing real-time automatic scene profiling and mode controlUS8266606May 13, 2008Sep 11, 2012International Business Machines CorporationSelf-optimizable code for optimizing execution of tasks and allocation of memory in a data processing systemUS8284207Oct 9, 2012Lucid Information Technology, Ltd.Method of generating digital images of objects in 3D scenes while eliminating object overdrawing within the multiple graphics processing pipeline (GPPLS) of a parallel graphics processing system generating partial color-based complementary-type images along the viewing direction using black pixel rendering and subsequent recompositing operationsUS8497865Dec 31, 2006Jul 30, 2013Lucid Information Technology, Ltd.Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUSUS8754894Nov 8, 2010Jun 17, 2014Lucidlogix Software Solutions, Ltd.Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applicationsUS8754897Nov 15, 2010Jun 17, 2014Lucidlogix Software Solutions, Ltd.Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystemUS9275430 *Jan 6, 2011Mar 1, 2016Lucidlogix Technologies, Ltd.Computing system employing a multi-GPU graphics processing and display subsystem supporting single-GPU non-parallel (multi-threading) and multi-GPU application-division parallel modes of graphics processing operationUS20060053421 *Sep 9, 2004Mar 9, 2006International Business Machines CorporationSelf-optimizable codeUS20060232590 *Jan 25, 2006Oct 19, 2006Reuven BakalashGraphics processing and display system employing multiple graphics cores on a silicon chip of monolithic constructionUS20060279577 *Mar 22, 2006Dec 14, 2006Reuven BakalashGraphics processing and display system employing multiple graphics cores on a silicon chip of monolithic constructionUS20070279411 *Nov 19, 2004Dec 6, 2007Reuven BakalashMethod and System for Multiple 3-D Graphic Pipeline Over a Pc BusUS20070291040 *Apr 23, 2007Dec 20, 2007Reuven BakalashMulti-mode parallel graphics rendering system supporting dynamic profiling of graphics-based applications and automatic control of parallel modes of operationUS20080068389 *Sep 18, 2007Mar 20, 2008Reuven BakalashMulti-mode parallel graphics rendering system (MMPGRS) embodied within a host computing system and employing the profiling of scenes in graphics-based applicationsUS20080074431 *Sep 18, 2007Mar 27, 2008Reuven BakalashComputing system capable of parallelizing the operation of multiple graphics processing units (GPUS) supported on external graphics cardsUS20080088631 *Sep 18, 2007Apr 17, 2008Reuven BakalashMulti-mode parallel graphics rendering and display system supporting real-time detection of scene profile indices programmed within pre-profiled scenes of the graphics-based applicationUS20080117217 *Jan 18, 2007May 22, 2008Reuven BakalashMulti-mode parallel graphics rendering system employing real-time automatic scene profiling and mode controlUS20080117219 *Oct 26, 2007May 22, 2008Reuven BakalashPC-based computing system employing a silicon chip of monolithic construction having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operationUS20080129744 *Oct 26, 2007Jun 5, 2008Lucid Information Technology, Ltd.PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics applicationUS20080129745 *Oct 26, 2007Jun 5, 2008Lucid Information Technology, Ltd.Graphics subsytem for integation in a PC-based computing system and providing multiple GPU-driven pipeline cores supporting multiple modes of parallelization dynamically controlled while running a graphics applicationUS20080158236 *Dec 31, 2006Jul 3, 2008Reuven BakalashParallel graphics system employing multiple graphics pipelines wtih multiple graphics processing units (GPUs) and supporting the object division mode of parallel graphics rendering using pixel processing resources provided therewithinUS20080168444 *Mar 20, 2008Jul 10, 2008Marc Alan DickensonMemory leakage managementUS20080222637 *May 13, 2008Sep 11, 2008Marc Alan DickensonSelf-Optimizable CodeUS20080238917 *Oct 23, 2007Oct 2, 2008Lucid Information Technology, Ltd.Graphics hub subsystem for interfacing parallalized graphics processing units (GPUS) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC busUS20110169840 *Jul 14, 2011Lucid Information Technology, LtdComputing system employing a multi-gpu graphics processing and display subsystem supporting single-gpu non-parallel (multi-threading) and multi-gpu application-division parallel modes of graphics processing operationUS20130290688 *Apr 22, 2013Oct 31, 2013Stanislav Victorovich BratanovMethod of Concurrent Instruction Execution and Parallel Work Balancing in Heterogeneous Computer SystemsUS20150026660 *Jul 18, 2013Jan 22, 2015Software AgMethods for building application intelligence into event driven applications through usage learning, and systems supporting such applications* Cited by examinerClassifications U.S. Classification718/105International ClassificationG06F9/46, G06F9/38, G06F9/50Cooperative ClassificationG06F9/5066, G06N99/005European ClassificationG06N99/00L, G06F9/50C2Legal EventsDateCodeEventDescriptionApr 6, 2005ASAssignmentOwner name: NATIONAL UNIVERSITY CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BABA, TAKANOBU;YOKOTA, TAKASHI;OTSU, KANEMITSU;REEL/FRAME:016021/0062Effective date: 20050301RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - 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