Source: http://www.google.com/patents/US7921245?dq=6,757,682
Timestamp: 2017-05-25 08:21:26
Document Index: 10694973

Matched Legal Cases: ['Application No. 200810098473', 'Application No. 2006', 'Application No. 0514229', 'Application No. 2006', 'Application No. 200810098473', 'Application No. 2006', 'Application No. 200810098473']

Patent US7921245 - Memory system and device with serialized data transfer - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory...http://www.google.com/patents/US7921245?utm_source=gb-gplus-sharePatent US7921245 - Memory system and device with serialized data transferAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7921245 B2Publication typeGrantApplication numberUS 12/696,807Publication dateApr 5, 2011Filing dateJan 29, 2010Priority dateJan 13, 2003Fee statusPaidAlso published asCN1748204A, CN1748204B, CN101281508A, US6826663, US7216187, US7313639, US7478181, US7925808, US8347047, US20040139253, US20040139288, US20050232020, US20070073926, US20080209141, US20100131725, US20110276733Publication number12696807, 696807, US 7921245 B2, US 7921245B2, US-B2-7921245, US7921245 B2, US7921245B2InventorsRichard E Perego, Frederick A WareOriginal AssigneeRambus Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (37), Non-Patent Citations (14), Classifications (12), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMemory system and device with serialized data transfer
FIG. 10 illustrates an exemplary timing diagram for the transfer of byte-sized write data values over a 32-line data path between the memory controller and storage subsystem of FIG. 4. As shown, four bytes are transferred in parallel over the data path during each of sixteen transmit intervals, thereby achieving transfer of a complete 64-byte write data block over sixteen transmit intervals. As discussed in reference to FIGS. 4 and 5, mask keys are compared to each write data value received within a constituent memory device of the storage subsystem. Thus, if the parallel data transfer scheme of FIG. 10 is used, each memory device generally requires a data interface at least as wide as the size of a write data value (i.e., at least as wide as the mask granularity). Accordingly, as shown in FIG. 11, the maximum storage capacity that can be achieved in a single-rank of memory devices 401 according to the constraints of FIG. 10 (i.e., 32-line data path and byte-mask granularity) is 4×SC bits, where SC is the maximum storage capacity of a given generation of memory devices 401. More generally, the maximum storage capacity of a single rank of memory devices is SC×(DPW)/(MG), where DPW is the width of the data path between memory controller and storage subsystem, and MG is the mask granularity. Additional ranks of memory devices may be added to increase the capacity of the storage subsystem, but the added signal drops generally result in degraded signaling performance on the data path.
FIG. 12 illustrates a data transfer scheme in an alternative embodiment of the invention that enables the per-rank storage capacity of the storage subsystem to be substantially increased. As shown, rather than transfer write data values over the data path in parallel, each write data value is transferred to the storage subsystem serially via a single data line. For example, during transmit interval 0, bit 0 of each of 32 bytes (B0-B31) is transferred to the storage subsystem via a respective line of the data path. Referring specifically to data line DQ00, bits 0-7 of byte B0 are transferred serially over data line DQ00 during respective transmit intervals 0 through 7. Bytes B1-B31 are similarly transferred serially over data lines DQ01-DQ31, respectively, during transmit intervals 0-7. During transmit intervals 8-15, the remaining bytes of the write data block, B32-B63, are transferred serially over data lines DQ00-DQ31, respectively. By serially transferring write data values in this manner, the data interface of each memory device within the storage subsystem may be made as narrow as a single bit and coupled to a corresponding one of the 32 data lines (more or fewer data lines may be used in an alternative embodiment). As shown in FIG. 13, such an arrangement enables 32 SC-sized memory devices 403 to be used per rank of the storage subsystem, effectively multiplying the per-rank storage capacity of the storage subsystem by the size of a write data value. For example, in a byte-masking memory system having a 32-line data path, the per-rank storage capacity of the storage subsystem is increased by a factor of 8, from the 4×SC capacity of FIG. 11 to the 32×SC capacity of FIG. 13. The increase in per-rank storage capacity becomes even more pronounced at larger mask granularities.
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Copyright Jul. 2000, Rambus Inc. 66 pages.Classifications U.S. Classification710/71, 710/74, 365/221, 711/155International ClassificationG06F13/16, G06F13/00, G11C16/06, G06F13/12, G06F13/38, G06F12/00Cooperative ClassificationG06F13/1684European ClassificationG06F13/16D6Legal EventsDateCodeEventDescriptionOct 6, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services