Source: https://patents.google.com/patent/US9912469B2/en
Timestamp: 2020-01-24 12:29:14
Document Index: 201371484

Matched Legal Cases: ['§ 371', 'Application No. 60', 'Application No. 07853389', 'Application No. 07853389', 'Application No. 07853389', 'Application No. 07853389', 'Application No. 07353389']

US9912469B2 - Phase control block for managing multiple clock domains in systems with frequency offsets - Google Patents
US9912469B2
US9912469B2 US15/369,806 US201615369806A US9912469B2 US 9912469 B2 US9912469 B2 US 9912469B2 US 201615369806 A US201615369806 A US 201615369806A US 9912469 B2 US9912469 B2 US 9912469B2
US15/369,806
US20170214515A1 (en
2009-01-12 Priority to US22599909A priority
2012-12-10 Priority to US13/710,404 priority patent/US8774337B2/en
2014-07-01 Priority to US14/321,723 priority patent/US9106399B2/en
2015-08-06 Priority to US14/820,266 priority patent/US9515814B2/en
2016-12-05 Priority to US15/369,806 priority patent/US9912469B2/en
2016-12-05 Application filed by Rambus Inc filed Critical Rambus Inc
2016-12-14 Assigned to RAMBUS INC. reassignment RAMBUS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WERNER, CARL WILLIAM, LEE, HAE-CHANG, ZERBE, JARED LEVAN
2017-07-27 Publication of US20170214515A1 publication Critical patent/US20170214515A1/en
2018-03-06 Publication of US9912469B2 publication Critical patent/US9912469B2/en
This application is a continuation of U.S. application Ser. No. 14/820,266, filed Aug. 6, 2015, which is continuation of U.S. application Ser. No. 14/321,723, filed Jul. 1, 2014, now U.S. Pat. No. 9,106,399, which is a continuation of U.S. application Ser. No. 13/710,404, filed Dec. 10, 2012, now U.S. Pat. No. 8,774,337, which is a continuation of U.S. patent application Ser. No. 12/225,999, filed Jan. 12, 2009, now U.S. Pat. No. 8,331,512, which is a United States National stage application filed under 35 U.S.C. § 371 of PCT Patent Application Serial No. PCT/US2007/008493, filed Apr. 4, 2007, which claims the benefit of the filing date of U.S. Provisional Patent Application No. 60/789,406 filed Apr. 4, 2006, all of which are incorporated herein by reference in their entireties.
FIG. 2 shows a preferred embodiment of deserializer and phase detector 120′ along with associated data sampling circuitry 500. The deserializing portion of the deserializer and phase detector is indicated generally as element 122. The phased detecting portion of the deserializer and phase detector is indicated generally as element 126.
a data sampler and an edge sampler for sampling the digital signal, each sampler having a clock input;
a clock signal supply circuit for providing a first clock signal having a first phase to the data sampler clock input and a second clock signal having a second phase to the edge sampler clock input, wherein the first and second phases are offset with respect to each other;
temporary storage for receiving a first plurality of samples of the digital signal sampled by the data sampler and a second plurality of samples of the digital signal sampled by the edge sampler; and
determining whether a transition between first and second samples of the first plurality of samples is detected;
comparing a timing between corresponding first samples of the first and second pluralities of samples; and
providing a phase correction value based on a result of said determining whether a transition between the first and second samples of the first plurality of samples is detected, and based on a result of the timing comparison between the corresponding first samples of the first and second pluralities of samples;
wherein the clock signal supply circuit is operative to selectively vary the first and second phases based on the phase correction value.
2. The circuit of claim 1, wherein the logic circuit is configured to provide the phase correction value by:
using a result of the timing comparison between respective first samples of the first and second pluralities of samples to update the phase correction value if a transition is detected between the first and second samples of the first plurality of samples; and
ignoring a result of the timing comparison between respective first samples of the first and second plurality of samples if a transition is not detected between the first and second samples of the first plurality of samples.
3. The circuit of claim 2, wherein using a result of the timing comparison between respective first samples of the first and second pluralities of samples to update the phase correction value comprises:
in accordance with a determination that the corresponding first samples of the first and second plurality of samples represent different logic values, performing one of an incrementing or a decrementing of the phase correction value; and
in accordance with a determination that the corresponding first samples of the first and second plurality of samples represent the same logic value, performing the other of an incrementing or a decrementing of the phase correction value.
4. The circuit of claim 1, further comprising a threshold detection circuit for comparing at least one of a first-order component of the phase correction value representing substantially instantaneous clock signal lead or lag and a second-order component of the phase correction value representing an integral of a clock lead or lag over time with a threshold, and adjusting the phase correction value in accordance with a result of the comparison.
5. The circuit of claim 4, wherein the threshold detection circuit is configured to compare a combination of the first-order component and the second-order component to a threshold.
6. The circuit of claim 1, further comprising an adaptive sampler for sampling the digital signal, the adaptive sampler having a clock input, wherein the clock signal supply circuit is further for providing a third clock signal having a third phase to the adaptive sampler clock input.
7. The circuit of claim 6, wherein the third phase comprises a selectively variable offset; wherein the adaptive sampler is configured to sample the digital signal according to the third phase; and wherein samples obtained from the adaptive sampler are used for measuring a data eye of the digital signal while the data sampler and edge sampler continue to sample the digital signal according to the first and second phases, respectively.
8. The circuit of claim 6, further comprising an adaptation circuit for using samples from the adaptive sampler to optimize a feedback equalizer.
9. The circuit of claim 1, further comprising a decision feedback equalization (DFE) circuit comprising a clock input, wherein the clock signal supply circuit is further for providing a fourth clock signal having a fourth phase to the DFE circuit clock input.
10. The circuit of claim 9, wherein the fourth phase comprises a selectively variable offset; and wherein the DFE circuit is configured to produce an equalized signal according to an optimized timing based on the fourth phase.
11. A method of receiving a digital signal comprising:
providing a first clock signal having a first phase to a data sampler and obtaining a first plurality of samples from the data sampler;
providing a second clock signal having a second phase to an edge sampler, wherein the first phase and the second phase are offset with respect to each other, and obtaining a second plurality of samples from the edge sampler;
comparing a timing between corresponding first samples of the first and second pluralities of samples;
providing a phase correction value based on a result of said determining whether a transition between the first and second samples of the first plurality of samples is detected, and based on a result of the timing comparison between the corresponding first samples of the first and second pluralities of samples; and
selectively varying the first and second phases based on the phase correction value.
12. The method of claim 11, wherein providing the phase correction value comprises:
13. The method of claim 12, wherein using a result of the timing comparison between respective first samples of the first and second pluralities of samples to update the phase correction value comprises:
14. The method of claim 11, further comprising comparing at least one of a first-order component of the phase correction value representing substantially instantaneous clock signal lead or lag and a second-order component of the phase correction value representing an integral of a clock lead or lag over time with a threshold, and adjusting the phase correction value in accordance with a result of the comparison.
15. The method of claim 14, wherein comparing at least one of the first-order component and the second-order component comprises comparing a combination of the first-order component and the second-order component to a threshold.
16. The method of claim 11, further comprising: providing a third clock signal having a third phase to an adaptive sampler and obtaining a third plurality of samples from the adaptive sampler.
17. The method of claim 16, wherein the third phase comprises a selectively variable offset; and wherein at least two samples of the third plurality of samples are used for measuring a data eye of the digital signal while the data sampler and edge sampler continue to sample the digital signal according to the first and second phases, respectively.
18. The method of claim 16, further comprising optimizing a feedback equalizer using at least two samples of the third plurality of samples.
19. The method of claim 11, further comprising: performing decision feedback equalization (DFE) using a fourth clock signal having a fourth phase.
20. The method of claim 19, wherein the fourth phase comprises a selectively variable offset, and wherein performing DFE comprises producing an equalized signal according to an optimized timing based on the fourth phase.
US15/369,806 2006-04-04 2016-12-05 Phase control block for managing multiple clock domains in systems with frequency offsets Active US9912469B2 (en)
US22599909A true 2009-01-12 2009-01-12
US13/710,404 US8774337B2 (en) 2006-04-04 2012-12-10 Phase control block for managing multiple clock domains in systems with frequency offsets
US14/321,723 US9106399B2 (en) 2006-04-04 2014-07-01 Phase control block for managing multiple clock domains in systems with frequency offsets
US14/820,266 US9515814B2 (en) 2006-04-04 2015-08-06 Phase control block for managing multiple clock domains in systems with frequency offsets
US15/369,806 US9912469B2 (en) 2006-04-04 2016-12-05 Phase control block for managing multiple clock domains in systems with frequency offsets
US15/913,764 US10454667B2 (en) 2006-04-04 2018-03-06 Phase control block for managing multiple clock domains in systems with frequency offsets
US14/820,266 Continuation US9515814B2 (en) 2006-04-04 2015-08-06 Phase control block for managing multiple clock domains in systems with frequency offsets
US15/913,764 Continuation US10454667B2 (en) 2006-04-04 2018-03-06 Phase control block for managing multiple clock domains in systems with frequency offsets
US20170214515A1 US20170214515A1 (en) 2017-07-27
US9912469B2 true US9912469B2 (en) 2018-03-06
US15/913,764 Active US10454667B2 (en) 2006-04-04 2018-03-06 Phase control block for managing multiple clock domains in systems with frequency offsets
2018-03-06 US US15/913,764 patent/US10454667B2/en active Active
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EP Office Communication dated Nov. 8, 2011 in EP Application No. 07853389.0. 7 pages.
EP Response dated Dec. 29, 2010 in EP Application No. 07853389.0. 38 pages.
EP Response dated May 15, 2012 re EP Application No. 07353389.0, Includes New Claims (Highlighted and Clear copies). 15 pages.
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US8331512B2 (en) 2012-12-11
US10454667B2 (en) 2019-10-22
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, HAE-CHANG;ZERBE, JARED LEVAN;WERNER, CARL WILLIAM;SIGNING DATES FROM 20060601 TO 20060602;REEL/FRAME:040737/0729