Source: https://patents.google.com/patent/JP2014154800A/en
Timestamp: 2020-07-13 02:56:12+00:00
Document Index: 594941

Matched Legal Cases: ['art 1', 'art 2', 'art 1', 'art 3', 'art 4', 'art 5', 'art 2', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art, 10']

JP2014154800A - Wiring board and manufacturing method thereof - Google Patents
JP2014154800A
JP2014154800A JP2013025210A JP2013025210A JP2014154800A JP 2014154800 A JP2014154800 A JP 2014154800A JP 2013025210 A JP2013025210 A JP 2013025210A JP 2013025210 A JP2013025210 A JP 2013025210A JP 2014154800 A JP2014154800 A JP 2014154800A
JP2013025210A
JP2014154800A5 (en
渉 金田
2013-02-13 Application filed by Shinko Electric Ind Co Ltd, 新光電気工業株式会社 filed Critical Shinko Electric Ind Co Ltd
2013-02-13 Priority to JP2013025210A priority Critical patent/JP2014154800A/en
2014-08-25 Publication of JP2014154800A publication Critical patent/JP2014154800A/en
2016-01-28 Publication of JP2014154800A5 publication Critical patent/JP2014154800A5/ja
238000007747 plating Methods 0.000 claims abstract description 52
238000001312 dry etching Methods 0.000 claims description 14
XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nMzAwcHgnIGhlaWdodD0nMzAwcHgnIHZpZXdCb3g9JzAgMCAzMDAgMzAwJz4KPCEtLSBFTkQgT0YgSEVBREVSIC0tPgo8cmVjdCBzdHlsZT0nb3BhY2l0eToxLjA7ZmlsbDojRkZGRkZGO3N0cm9rZTpub25lJyB3aWR0aD0nMzAwJyBoZWlnaHQ9JzMwMCcgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJzdGFydCIgeD0nMTMyLjY1NScgeT0nMTU2JyBzdHlsZT0nZm9udC1zaXplOjQwcHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7ZmlsbDojM0I0MTQzJyA+PHRzcGFuPlNpPC90c3Bhbj48L3RleHQ+CjxwYXRoIGQ9J00gMzIuNzI3MywxMTMuNjM2IEwgMzIuNjk3LDExMi45MzMgTCAzMi42MDYzLDExMi4yMzUgTCAzMi40NTYsMTExLjU0NyBMIDMyLjI0NzEsMTEwLjg3NSBMIDMxLjk4MTIsMTEwLjIyMyBMIDMxLjY2MDMsMTA5LjU5NiBMIDMxLjI4NjYsMTA5IEwgMzAuODYzMSwxMDguNDM3IEwgMzAuMzkyOCwxMDcuOTE0IEwgMjkuODc5MiwxMDcuNDMyIEwgMjkuMzI2MSwxMDYuOTk2IEwgMjguNzM3NiwxMDYuNjEgTCAyOC4xMTgxLDEwNi4yNzYgTCAyNy40NzIxLDEwNS45OTYgTCAyNi44MDQ0LDEwNS43NzMgTCAyNi4xMjAxLDEwNS42MDcgTCAyNS40MjQsMTA1LjUwMiBMIDI0LjcyMTUsMTA1LjQ1NiBMIDI0LjAxNzcsMTA1LjQ3MiBMIDIzLjMxNzcsMTA1LjU0NyBMIDIyLjYyNjksMTA1LjY4MyBMIDIxLjk1MDMsMTA1Ljg3NyBMIDIxLjI5MjgsMTA2LjEyOSBMIDIwLjY1OTUsMTA2LjQzNiBMIDIwLjA1NDksMTA2Ljc5NyBMIDE5LjQ4MzYsMTA3LjIwOCBMIDE4Ljk0OTgsMTA3LjY2NyBMIDE4LjQ1NzMsMTA4LjE3IEwgMTguMDEsMTA4LjcxNCBMIDE3LjYxMSwxMDkuMjk0IEwgMTcuMjYzNCwxMDkuOTA2IEwgMTYuOTY5NywxMTAuNTQ2IEwgMTYuNzMyMSwxMTEuMjA5IEwgMTYuNTUyMywxMTEuODg5IEwgMTYuNDMxNywxMTIuNTgzIEwgMTYuMzcxMiwxMTMuMjg0IEwgMTYuMzcxMiwxMTMuOTg4IEwgMTYuNDMxNywxMTQuNjkgTCAxNi41NTIzLDExNS4zODMgTCAxNi43MzIxLDExNi4wNjQgTCAxNi45Njk3LDExNi43MjcgTCAxNy4yNjM0LDExNy4zNjcgTCAxNy42MTEsMTE3Ljk3OSBMIDE4LjAxLDExOC41NTkgTCAxOC40NTczLDExOS4xMDIgTCAxOC45NDk4LDExOS42MDUgTCAxOS40ODM2LDEyMC4wNjQgTCAyMC4wNTQ5LDEyMC40NzYgTCAyMC42NTk1LDEyMC44MzYgTCAyMS4yOTI4LDEyMS4xNDQgTCAyMS45NTAzLDEyMS4zOTYgTCAyMi42MjY5LDEyMS41OSBMIDIzLjMxNzcsMTIxLjcyNiBMIDI0LjAxNzcsMTIxLjgwMSBMIDI0LjcyMTUsMTIxLjgxNiBMIDI1LjQyNCwxMjEuNzcxIEwgMjYuMTIwMSwxMjEuNjY1IEwgMjYuODA0NCwxMjEuNSBMIDI3LjQ3MjEsMTIxLjI3NyBMIDI4LjExODEsMTIwLjk5NyBMIDI4LjczNzYsMTIwLjY2MyBMIDI5LjMyNjEsMTIwLjI3NiBMIDI5Ljg3OTIsMTE5Ljg0MSBMIDMwLjM5MjgsMTE5LjM1OSBMIDMwLjg2MzEsMTE4LjgzNSBMIDMxLjI4NjYsMTE4LjI3MyBMIDMxLjY2MDMsMTE3LjY3NiBMIDMxLjk4MTIsMTE3LjA1IEwgMzIuMjQ3MSwxMTYuMzk4IEwgMzIuNDU2LDExNS43MjYgTCAzMi42MDYzLDExNS4wMzggTCAzMi42OTcsMTE0LjM0IEwgMzIuNzI3MywxMTMuNjM2IEwgMjQuNTQ1NSwxMTMuNjM2IFonIHN0eWxlPSdmaWxsOiMwMDAwMDA7ZmlsbC1ydWxlOmV2ZW5vZGQ7ZmlsbC1vcGFjaXR5PTE7c3Ryb2tlOiMwMDAwMDA7c3Ryb2tlLXdpZHRoOjEwcHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MTsnIC8+CjxwYXRoIGQ9J00gMjgzLjYzNiwxMTMuNjM2IEwgMjgzLjYwNiwxMTIuOTMzIEwgMjgzLjUxNSwxMTIuMjM1IEwgMjgzLjM2NSwxMTEuNTQ3IEwgMjgzLjE1NiwxMTAuODc1IEwgMjgyLjg5LDExMC4yMjMgTCAyODIuNTY5LDEwOS41OTYgTCAyODIuMTk2LDEwOSBMIDI4MS43NzIsMTA4LjQzNyBMIDI4MS4zMDIsMTA3LjkxNCBMIDI4MC43ODgsMTA3LjQzMiBMIDI4MC4yMzUsMTA2Ljk5NiBMIDI3OS42NDcsMTA2LjYxIEwgMjc5LjAyNywxMDYuMjc2IEwgMjc4LjM4MSwxMDUuOTk2IEwgMjc3LjcxNCwxMDUuNzczIEwgMjc3LjAyOSwxMDUuNjA3IEwgMjc2LjMzMywxMDUuNTAyIEwgMjc1LjYzMSwxMDUuNDU2IEwgMjc0LjkyNywxMDUuNDcyIEwgMjc0LjIyNywxMDUuNTQ3IEwgMjczLjUzNiwxMDUuNjgzIEwgMjcyLjg1OSwxMDUuODc3IEwgMjcyLjIwMiwxMDYuMTI5IEwgMjcxLjU2OSwxMDYuNDM2IEwgMjcwLjk2NCwxMDYuNzk3IEwgMjcwLjM5MywxMDcuMjA4IEwgMjY5Ljg1OSwxMDcuNjY3IEwgMjY5LjM2NiwxMDguMTcgTCAyNjguOTE5LDEwOC43MTQgTCAyNjguNTIsMTA5LjI5NCBMIDI2OC4xNzMsMTA5LjkwNiBMIDI2Ny44NzksMTEwLjU0NiBMIDI2Ny42NDEsMTExLjIwOSBMIDI2Ny40NjEsMTExLjg4OSBMIDI2Ny4zNDEsMTEyLjU4MyBMIDI2Ny4yOCwxMTMuMjg0IEwgMjY3LjI4LDExMy45ODggTCAyNjcuMzQxLDExNC42OSBMIDI2Ny40NjEsMTE1LjM4MyBMIDI2Ny42NDEsMTE2LjA2NCBMIDI2Ny44NzksMTE2LjcyNyBMIDI2OC4xNzMsMTE3LjM2NyBMIDI2OC41MiwxMTcuOTc5IEwgMjY4LjkxOSwxMTguNTU5IEwgMjY5LjM2NiwxMTkuMTAyIEwgMjY5Ljg1OSwxMTkuNjA1IEwgMjcwLjM5MywxMjAuMDY0IEwgMjcwLjk2NCwxMjAuNDc2IEwgMjcxLjU2OSwxMjAuODM2IEwgMjcyLjIwMiwxMjEuMTQ0IEwgMjcyLjg1OSwxMjEuMzk2IEwgMjczLjUzNiwxMjEuNTkgTCAyNzQuMjI3LDEyMS43MjYgTCAyNzQuOTI3LDEyMS44MDEgTCAyNzUuNjMxLDEyMS44MTYgTCAyNzYuMzMzLDEyMS43NzEgTCAyNzcuMDI5LDEyMS42NjUgTCAyNzcuNzE0LDEyMS41IEwgMjc4LjM4MSwxMjEuMjc3IEwgMjc5LjAyNywxMjAuOTk3IEwgMjc5LjY0NywxMjAuNjYzIEwgMjgwLjIzNSwxMjAuMjc2IEwgMjgwLjc4OCwxMTkuODQxIEwgMjgxLjMwMiwxMTkuMzU5IEwgMjgxLjc3MiwxMTguODM1IEwgMjgyLjE5NiwxMTguMjczIEwgMjgyLjU2OSwxMTcuNjc2IEwgMjgyLjg5LDExNy4wNSBMIDI4My4xNTYsMTE2LjM5OCBMIDI4My4zNjUsMTE1LjcyNiBMIDI4My41MTUsMTE1LjAzOCBMIDI4My42MDYsMTE0LjM0IEwgMjgzLjYzNiwxMTMuNjM2IEwgMjc1LjQ1NSwxMTMuNjM2IFonIHN0eWxlPSdmaWxsOiMwMDAwMDA7ZmlsbC1ydWxlOmV2ZW5vZGQ7ZmlsbC1vcGFjaXR5PTE7c3Ryb2tlOiMwMDAwMDA7c3Ryb2tlLXdpZHRoOjEwcHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MTsnIC8+Cjwvc3ZnPgo= data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nODVweCcgaGVpZ2h0PSc4NXB4JyB2aWV3Qm94PScwIDAgODUgODUnPgo8IS0tIEVORCBPRiBIRUFERVIgLS0+CjxyZWN0IHN0eWxlPSdvcGFjaXR5OjEuMDtmaWxsOiNGRkZGRkY7c3Ryb2tlOm5vbmUnIHdpZHRoPSc4NScgaGVpZ2h0PSc4NScgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJzdGFydCIgeD0nMjUuMjQ2OCcgeT0nNDcuNzk1NScgc3R5bGU9J2ZvbnQtc2l6ZTozOHB4O2ZvbnQtc3R5bGU6bm9ybWFsO2ZvbnQtd2VpZ2h0Om5vcm1hbDtmaWxsLW9wYWNpdHk6MTtzdHJva2U6bm9uZTtmb250LWZhbWlseTpzYW5zLXNlcmlmO2ZpbGw6IzNCNDE0MycgPjx0c3Bhbj5TaTwvdHNwYW4+PC90ZXh0Pgo8cGF0aCBkPSdNIDguNzcyNzMsMTguMDQ1NSBMIDguNzY0MTUsMTcuODQ2MiBMIDguNzM4NDYsMTcuNjQ4NCBMIDguNjk1ODcsMTcuNDUzNSBMIDguNjM2NjksMTcuMjYzIEwgOC41NjEzNSwxNy4wNzgzIEwgOC40NzA0MSwxNi45MDA4IEwgOC4zNjQ1NSwxNi43MzE3IEwgOC4yNDQ1NCwxNi41NzI0IEwgOC4xMTEyOSwxNi40MjQgTCA3Ljk2NTc3LDE2LjI4NzYgTCA3LjgwOTA1LDE2LjE2NDIgTCA3LjY0MjMyLDE2LjA1NDcgTCA3LjQ2Njc4LDE1Ljk1OTkgTCA3LjI4Mzc2LDE1Ljg4MDcgTCA3LjA5NDU5LDE1LjgxNzQgTCA2LjkwMDY4LDE1Ljc3MDYgTCA2LjcwMzQ3LDE1Ljc0MDcgTCA2LjUwNDQyLDE1LjcyNzggTCA2LjMwNSwxNS43MzIxIEwgNi4xMDY2OSwxNS43NTM1IEwgNS45MTA5NSwxNS43OTE5IEwgNS43MTkyNCwxNS44NDcgTCA1LjUzMjk3LDE1LjkxODMgTCA1LjM1MzUyLDE2LjAwNTQgTCA1LjE4MjIzLDE2LjEwNzYgTCA1LjAyMDM1LDE2LjIyNDIgTCA0Ljg2OTEsMTYuMzU0MiBMIDQuNzI5NTgsMTYuNDk2OCBMIDQuNjAyODMsMTYuNjUwOCBMIDQuNDg5NzksMTYuODE1MSBMIDQuMzkxMywxNi45ODg2IEwgNC4zMDgwOCwxNy4xNjk5IEwgNC4yNDA3NiwxNy4zNTc2IEwgNC4xODk4MiwxNy41NTA1IEwgNC4xNTU2NiwxNy43NDcgTCA0LjEzODUxLDE3Ljk0NTcgTCA0LjEzODUxLDE4LjE0NTIgTCA0LjE1NTY2LDE4LjM0MzkgTCA0LjE4OTgyLDE4LjU0MDQgTCA0LjI0MDc2LDE4LjczMzMgTCA0LjMwODA4LDE4LjkyMTEgTCA0LjM5MTMsMTkuMTAyMyBMIDQuNDg5NzksMTkuMjc1OCBMIDQuNjAyODMsMTkuNDQwMSBMIDQuNzI5NTgsMTkuNTk0MSBMIDQuODY5MSwxOS43MzY3IEwgNS4wMjAzNSwxOS44NjY3IEwgNS4xODIyMywxOS45ODMzIEwgNS4zNTM1MiwyMC4wODU1IEwgNS41MzI5NywyMC4xNzI2IEwgNS43MTkyNCwyMC4yNDM5IEwgNS45MTA5NSwyMC4yOTkgTCA2LjEwNjY5LDIwLjMzNzQgTCA2LjMwNSwyMC4zNTg4IEwgNi41MDQ0MiwyMC4zNjMxIEwgNi43MDM0NywyMC4zNTAyIEwgNi45MDA2OCwyMC4zMjAzIEwgNy4wOTQ1OSwyMC4yNzM1IEwgNy4yODM3NiwyMC4yMTAzIEwgNy40NjY3OCwyMC4xMzEgTCA3LjY0MjMyLDIwLjAzNjIgTCA3LjgwOTA1LDE5LjkyNjcgTCA3Ljk2NTc3LDE5LjgwMzMgTCA4LjExMTI5LDE5LjY2NjkgTCA4LjI0NDU0LDE5LjUxODUgTCA4LjM2NDU1LDE5LjM1OTIgTCA4LjQ3MDQxLDE5LjE5MDEgTCA4LjU2MTM1LDE5LjAxMjYgTCA4LjYzNjY5LDE4LjgyNzkgTCA4LjY5NTg3LDE4LjYzNzQgTCA4LjczODQ2LDE4LjQ0MjUgTCA4Ljc2NDE1LDE4LjI0NDcgTCA4Ljc3MjczLDE4LjA0NTUgTCA2LjQ1NDU1LDE4LjA0NTUgWicgc3R5bGU9J2ZpbGw6IzAwMDAwMDtmaWxsLXJ1bGU6ZXZlbm9kZDtmaWxsLW9wYWNpdHk9MTtzdHJva2U6IzAwMDAwMDtzdHJva2Utd2lkdGg6MnB4O3N0cm9rZS1saW5lY2FwOmJ1dHQ7c3Ryb2tlLWxpbmVqb2luOm1pdGVyO3N0cm9rZS1vcGFjaXR5OjE7JyAvPgo8cGF0aCBkPSdNIDc5Ljg2MzYsMTguMDQ1NSBMIDc5Ljg1NTEsMTcuODQ2MiBMIDc5LjgyOTQsMTcuNjQ4NCBMIDc5Ljc4NjgsMTcuNDUzNSBMIDc5LjcyNzYsMTcuMjYzIEwgNzkuNjUyMywxNy4wNzgzIEwgNzkuNTYxMywxNi45MDA4IEwgNzkuNDU1NSwxNi43MzE3IEwgNzkuMzM1NSwxNi41NzI0IEwgNzkuMjAyMiwxNi40MjQgTCA3OS4wNTY3LDE2LjI4NzYgTCA3OC45LDE2LjE2NDIgTCA3OC43MzMyLDE2LjA1NDcgTCA3OC41NTc3LDE1Ljk1OTkgTCA3OC4zNzQ3LDE1Ljg4MDcgTCA3OC4xODU1LDE1LjgxNzQgTCA3Ny45OTE2LDE1Ljc3MDYgTCA3Ny43OTQ0LDE1Ljc0MDcgTCA3Ny41OTUzLDE1LjcyNzggTCA3Ny4zOTU5LDE1LjczMjEgTCA3Ny4xOTc2LDE1Ljc1MzUgTCA3Ny4wMDE5LDE1Ljc5MTkgTCA3Ni44MTAxLDE1Ljg0NyBMIDc2LjYyMzksMTUuOTE4MyBMIDc2LjQ0NDQsMTYuMDA1NCBMIDc2LjI3MzEsMTYuMTA3NiBMIDc2LjExMTMsMTYuMjI0MiBMIDc1Ljk2LDE2LjM1NDIgTCA3NS44MjA1LDE2LjQ5NjggTCA3NS42OTM3LDE2LjY1MDggTCA3NS41ODA3LDE2LjgxNTEgTCA3NS40ODIyLDE2Ljk4ODYgTCA3NS4zOTksMTcuMTY5OSBMIDc1LjMzMTcsMTcuMzU3NiBMIDc1LjI4MDcsMTcuNTUwNSBMIDc1LjI0NjYsMTcuNzQ3IEwgNzUuMjI5NCwxNy45NDU3IEwgNzUuMjI5NCwxOC4xNDUyIEwgNzUuMjQ2NiwxOC4zNDM5IEwgNzUuMjgwNywxOC41NDA0IEwgNzUuMzMxNywxOC43MzMzIEwgNzUuMzk5LDE4LjkyMTEgTCA3NS40ODIyLDE5LjEwMjMgTCA3NS41ODA3LDE5LjI3NTggTCA3NS42OTM3LDE5LjQ0MDEgTCA3NS44MjA1LDE5LjU5NDEgTCA3NS45NiwxOS43MzY3IEwgNzYuMTExMywxOS44NjY3IEwgNzYuMjczMSwxOS45ODMzIEwgNzYuNDQ0NCwyMC4wODU1IEwgNzYuNjIzOSwyMC4xNzI2IEwgNzYuODEwMSwyMC4yNDM5IEwgNzcuMDAxOSwyMC4yOTkgTCA3Ny4xOTc2LDIwLjMzNzQgTCA3Ny4zOTU5LDIwLjM1ODggTCA3Ny41OTUzLDIwLjM2MzEgTCA3Ny43OTQ0LDIwLjM1MDIgTCA3Ny45OTE2LDIwLjMyMDMgTCA3OC4xODU1LDIwLjI3MzUgTCA3OC4zNzQ3LDIwLjIxMDMgTCA3OC41NTc3LDIwLjEzMSBMIDc4LjczMzIsMjAuMDM2MiBMIDc4LjksMTkuOTI2NyBMIDc5LjA1NjcsMTkuODAzMyBMIDc5LjIwMjIsMTkuNjY2OSBMIDc5LjMzNTUsMTkuNTE4NSBMIDc5LjQ1NTUsMTkuMzU5MiBMIDc5LjU2MTMsMTkuMTkwMSBMIDc5LjY1MjMsMTkuMDEyNiBMIDc5LjcyNzYsMTguODI3OSBMIDc5Ljc4NjgsMTguNjM3NCBMIDc5LjgyOTQsMTguNDQyNSBMIDc5Ljg1NTEsMTguMjQ0NyBMIDc5Ljg2MzYsMTguMDQ1NSBMIDc3LjU0NTUsMTguMDQ1NSBaJyBzdHlsZT0nZmlsbDojMDAwMDAwO2ZpbGwtcnVsZTpldmVub2RkO2ZpbGwtb3BhY2l0eT0xO3N0cm9rZTojMDAwMDAwO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MTsnIC8+Cjwvc3ZnPgo= [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 31
238000001039 wet etching Methods 0.000 description 8
ORTQZVOHEJQUHG-UHFFFAOYSA-L Copper(II) chloride Chemical compound data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nMzAwcHgnIGhlaWdodD0nMzAwcHgnIHZpZXdCb3g9JzAgMCAzMDAgMzAwJz4KPCEtLSBFTkQgT0YgSEVBREVSIC0tPgo8cmVjdCBzdHlsZT0nb3BhY2l0eToxLjA7ZmlsbDojRkZGRkZGO3N0cm9rZTpub25lJyB3aWR0aD0nMzAwJyBoZWlnaHQ9JzMwMCcgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHBhdGggY2xhc3M9J2JvbmQtMCcgZD0nTSA2Ny42NzQ0LDE1MCBMIDg4LjI0NzcsMTUwJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojNUJCNzcyO3N0cm9rZS13aWR0aDozcHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMCcgZD0nTSA4OC4yNDc3LDE1MCBMIDEwOC44MjEsMTUwJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojM0I0MTQzO3N0cm9rZS13aWR0aDozcHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMScgZD0nTSAxOTEuMTc5LDE1MCBMIDIxMS43NTIsMTUwJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojM0I0MTQzO3N0cm9rZS13aWR0aDozcHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMScgZD0nTSAyMTEuNzUyLDE1MCBMIDIzMi4zMjYsMTUwJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojNUJCNzcyO3N0cm9rZS13aWR0aDozcHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJlbmQiIHg9JzUyLjIzODcnIHk9JzE1NS43ODgnIHN0eWxlPSdmb250LXNpemU6MzhweDtmb250LXN0eWxlOm5vcm1hbDtmb250LXdlaWdodDpub3JtYWw7ZmlsbC1vcGFjaXR5OjE7c3Ryb2tlOm5vbmU7Zm9udC1mYW1pbHk6c2Fucy1zZXJpZjtmaWxsOiM1QkI3NzInID48dHNwYW4+Q2w8L3RzcGFuPjwvdGV4dD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJtaWRkbGUiIHg9JzE1MCcgeT0nMTU1Ljc4OCcgc3R5bGU9J2ZvbnQtc2l6ZTozOHB4O2ZvbnQtc3R5bGU6bm9ybWFsO2ZvbnQtd2VpZ2h0Om5vcm1hbDtmaWxsLW9wYWNpdHk6MTtzdHJva2U6bm9uZTtmb250LWZhbWlseTpzYW5zLXNlcmlmO2ZpbGw6IzNCNDE0MycgPjx0c3Bhbj5DdTwvdHNwYW4+PC90ZXh0Pgo8dGV4dCBkb21pbmFudC1iYXNlbGluZT0iY2VudHJhbCIgdGV4dC1hbmNob3I9InN0YXJ0IiB4PScyNDcuNzYxJyB5PScxNTUuNzg4JyBzdHlsZT0nZm9udC1zaXplOjM4cHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7ZmlsbDojNUJCNzcyJyA+PHRzcGFuPkNsPC90c3Bhbj48L3RleHQ+Cjwvc3ZnPgo= data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nODVweCcgaGVpZ2h0PSc4NXB4JyB2aWV3Qm94PScwIDAgODUgODUnPgo8IS0tIEVORCBPRiBIRUFERVIgLS0+CjxyZWN0IHN0eWxlPSdvcGFjaXR5OjEuMDtmaWxsOiNGRkZGRkY7c3Ryb2tlOm5vbmUnIHdpZHRoPSc4NScgaGVpZ2h0PSc4NScgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHBhdGggY2xhc3M9J2JvbmQtMCcgZD0nTSAxNS42Mzk5LDQyIEwgMjQuNjY1LDQyJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojNUJCNzcyO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMCcgZD0nTSAyNC42NjUsNDIgTCAzMy42OTAxLDQyJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojM0I0MTQzO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMScgZD0nTSA1MC4zMDk5LDQyIEwgNTkuMzM1LDQyJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojM0I0MTQzO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHBhdGggY2xhc3M9J2JvbmQtMScgZD0nTSA1OS4zMzUsNDIgTCA2OC4zNjAxLDQyJyBzdHlsZT0nZmlsbDpub25lO2ZpbGwtcnVsZTpldmVub2RkO3N0cm9rZTojNUJCNzcyO3N0cm9rZS13aWR0aDoycHg7c3Ryb2tlLWxpbmVjYXA6YnV0dDtzdHJva2UtbGluZWpvaW46bWl0ZXI7c3Ryb2tlLW9wYWNpdHk6MScgLz4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJlbmQiIHg9JzE0LjU1NjYnIHk9JzQzLjYyNDknIHN0eWxlPSdmb250LXNpemU6MTBweDtmb250LXN0eWxlOm5vcm1hbDtmb250LXdlaWdodDpub3JtYWw7ZmlsbC1vcGFjaXR5OjE7c3Ryb2tlOm5vbmU7Zm9udC1mYW1pbHk6c2Fucy1zZXJpZjtmaWxsOiM1QkI3NzInID48dHNwYW4+Q2w8L3RzcGFuPjwvdGV4dD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJtaWRkbGUiIHg9JzQyJyB5PSc0My42MjQ5JyBzdHlsZT0nZm9udC1zaXplOjEwcHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7ZmlsbDojM0I0MTQzJyA+PHRzcGFuPkN1PC90c3Bhbj48L3RleHQ+Cjx0ZXh0IGRvbWluYW50LWJhc2VsaW5lPSJjZW50cmFsIiB0ZXh0LWFuY2hvcj0ic3RhcnQiIHg9JzY5LjQ0MzQnIHk9JzQzLjYyNDknIHN0eWxlPSdmb250LXNpemU6MTBweDtmb250LXN0eWxlOm5vcm1hbDtmb250LXdlaWdodDpub3JtYWw7ZmlsbC1vcGFjaXR5OjE7c3Ryb2tlOm5vbmU7Zm9udC1mYW1pbHk6c2Fucy1zZXJpZjtmaWxsOiM1QkI3NzInID48dHNwYW4+Q2w8L3RzcGFuPjwvdGV4dD4KPC9zdmc+Cg== Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
A wiring board on which high-performance electronic components can be mounted without using a silicon interposer is provided.
A wiring layer, an insulating layer in which the wiring layer is buried and a via hole VH1 is formed under the wiring layer, and a via conductor in the via hole VH1 are formed under the insulating layer. A base wiring board 2 having a wiring layer 22 connected to the wiring layer 21; an insulating layer 34 formed on the base wiring board 2 and having a via hole VH4 formed on the wiring layer 21; 34 and a rewiring portion 3 including a rewiring layer 41 connected to the wiring layer 21 via a via conductor in the via hole VH4. The rewiring layer 41 includes a seed layer 41a and It is formed from the upper metal plating layer 41b, and the width of the seed layer 41a includes the same or wider than the width of the metal plating layer 41b.
The present invention relates to a wiring board and a manufacturing method thereof.
Conventionally, there is a wiring board for mounting electronic components such as a semiconductor chip. In recent years, with higher performance of electronic components, wiring boards are being further densified and multilayered.
Japanese Patent Laid-Open No. 11-126978
As will be described later in the preliminary section, a high-performance semiconductor chip is pitch-converted via a silicon interposer and mounted on a wiring board.
When manufacturing a silicon interposer, it is necessary to form a through hole in a silicon substrate by dry etching or the like, to form a through electrode therein by electrolytic plating, and to form fine wiring layers on both sides.
The manufacture of such a silicon interposer has a problem that technical hurdles are high and manufacturing costs are high.
An object of the present invention is to provide a wiring board on which high-performance electronic components can be mounted without using a silicon interposer, and a method for manufacturing the same.
According to one aspect of the disclosure below, a first wiring layer, a first insulating layer in which the first wiring layer is embedded and a first via hole is formed under the first wiring layer, and the first insulation A base wiring board having a second wiring layer formed under the layer and connected to the first wiring layer via a via conductor in the first via hole; and formed on the base wiring board; A second insulating layer having a second via hole formed on the first wiring layer; and a second insulating layer formed on the second insulating layer and connected to the first wiring layer through a via conductor in the second via hole. A redistribution portion having a redistribution layer formed, and the redistribution layer is formed of a seed layer and a metal plating layer thereon, and the width of the seed layer is the same as the width of the metal plating layer or A wider wiring board is provided.
According to another aspect of the disclosure, a step of forming a first wiring layer on a metal plate, and a first via hole provided on the first wiring layer on the metal plate. Forming a first insulating layer; forming a second wiring layer connected to the first wiring layer via a via conductor in the first via hole; and the metal plate. Removing a step, forming a second insulating layer having a second via hole provided on the first wiring layer on the first insulating layer, and in the second via hole and the second insulating layer. Forming a seed layer on the layer; forming a plating resist having an opening in a region including the second via hole; and electrolytic plating to form the second via hole and the opening of the plating resist. Forming a metal plating layer and the plating resist; Removing the by anisotropic dry etching, by removing the seed layer by the metal plating layer as a mask, manufacturing method of the wiring substrate and a step of forming the rewiring layer is provided.
According to the following disclosure, a fine redistribution layer is directly formed on a base wiring substrate, so that a semiconductor chip is pitch-converted in the rewiring layer and connected to the base wiring substrate without using a silicon interposer. be able to.
When forming the rewiring layer, a semi-additive method is used, and anisotropic dry etching is employed when the seed layer is etched using the metal plating layer as a mask. For this reason, unlike the method of removing the seed layer by wet etching, the width of the seed layer can be made equal to or wider than the width of the metal plating layer, so that a fine rewiring layer can be formed.
FIG. 1 is a sectional view showing a semiconductor device according to a preliminary matter. 2A to 2D are cross-sectional views (part 1) illustrating the method for manufacturing the wiring board according to the embodiment. 3A to 3C are cross-sectional views (part 2) illustrating the method for manufacturing the wiring board according to the embodiment. 4A to 4C are cross-sectional views (part 1) showing a method of forming the second wiring layer of FIG. FIGS. 5A and 5B are sectional views (No. 2) showing a method of forming the second wiring layer of FIG. 6A to 6D are cross-sectional views (part 3) illustrating the method for manufacturing the wiring board according to the embodiment. 7A to 7C are cross-sectional views (part 4) illustrating the method of manufacturing the wiring board according to the embodiment. 8A to 8C are cross-sectional views (part 5) illustrating the method for manufacturing the wiring board according to the embodiment. 9A to 9C are cross-sectional views (No. 1) showing a method for forming the first redistribution layer in FIG. 8C. FIGS. 10A and 10B are cross-sectional views (part 2) illustrating the method of forming the first redistribution layer in FIG. 11A to 11C are cross-sectional views (No. 6) showing the method for manufacturing the wiring board according to the embodiment. 12A and 12B are sectional views (No. 7) showing the method for manufacturing the wiring board according to the embodiment. FIG. 13 is a cross-sectional view showing the wiring board of the embodiment. 14 is a cross-sectional view showing an example of a semiconductor device in which a semiconductor chip is mounted on the wiring board of FIG.
Prior to describing the embodiment, preliminary items that serve as a basis will be described. In recent years, as the performance of a semiconductor chip has been improved, the pitch of connection pads has been reduced, and it has become difficult to directly mount the semiconductor chip on a wiring board.
For this reason, as shown in FIG. 1, a technique for connecting the semiconductor chip 300 to the wiring substrate 100 via the silicon interposer 200 has been developed.
The wiring board 100 includes connection pads 120 on the upper surface side and external connection terminals 140 on the lower surface side.
In the silicon interposer 200, the through hole TH is provided in the silicon substrate 220, and the through electrode TE is formed therein. On both sides of the silicon substrate 220, wiring layers 240 interconnected through the through electrodes TE are formed.
Insulating layers 260 each having an opening on the wiring layer 240 are formed on both sides of the silicon substrate.
The wiring layer 240 on the lower surface side of the silicon interposer 200 is connected to the connection pads 120 of the wiring substrate 100 via the connection terminals 280. Further, the bump electrode 320 of the semiconductor chip 300 is connected to the wiring layer 240 on the upper surface side of the silicon interposer 200.
In this manner, the narrow pitch bump electrodes 320 of the semiconductor chip 300 are connected to the silicon interposer 200 having fine wiring, and the pitch is converted from the silicon interposer 200 to the wiring substrate 100.
When manufacturing the silicon interposer 200, the through hole TH is formed in the silicon substrate 220 by dry etching, the through electrode TE is formed in the through hole TH by electrolytic plating, and the fine wiring layer 240 is formed on both sides. There is a need to.
Such a method is technically difficult and the number of manufacturers that can be manufactured is limited. Moreover, since it is necessary to introduce an expensive manufacturing apparatus and perform a complicated manufacturing process, there is a problem that the manufacturing cost increases.
In the embodiment described below, the above-described problems can be solved.
2 to 12 are cross-sectional views showing a method for manufacturing a wiring board according to the embodiment, and FIG. 13 is a cross-sectional view showing the wiring board according to the embodiment. Hereinafter, the structure of the wiring board will be described while explaining the manufacturing method of the wiring board.
In the wiring board manufacturing method of the embodiment, as shown in FIG. 2A, first, a first metal plate 10 is prepared as a temporary board. As an example of the first metal plate 10, a copper plate or a copper foil having a thickness of 1 mm to 10 mm is used.
Next, as shown in FIG. 2B, a plating resist 11 having an opening 11 a is formed on the first metal plate 10. The plating resist 11 is formed by sticking a dry film resist on the first metal plate 10 and exposing and developing by photolithography.
2C, the first wiring layer 21 is formed by performing metal plating on the opening 11a of the plating resist 11 by electrolytic plating using the first metal plate 10 as a plating power feeding path. .
Thereafter, as shown in FIG. 2D, the plating resist 11 is removed. In FIG. 2D, connection pads are drawn as the first wiring layer 21. The first wiring layer 21 may be a connection pad arranged in an island shape, or may be arranged with a connection pad connected to one end of the lead-out wiring.
As shown in the partial cross-sectional view of FIG. 2D, the first wiring layer 21 is formed of a laminated film, and in order from the bottom, a gold (Au) layer 21a having a thickness of 0.5 μm / nickel (Ni) having a thickness of 1 μm. ) Layer 21b / a copper (Cu) layer 21c having a thickness of 10 μm.
The lowermost layer of the first wiring layer 21 is formed of a metal that serves as a stopper when the first metal plate 10 is removed by wet etching. In the example described above, the first metal plate 10 is made of copper, and the gold layer 21a is formed as the lowermost layer of the first wiring layer 21, but other metal combinations may be employed.
Next, as shown in FIG. 3A, an uncured resin film such as an epoxy resin or a polyimide resin is applied on the first metal plate 10 and the first wiring layer 21, and is subjected to a hot press, whereby the first Interlayer insulating layer 31 is formed. The thickness of the first interlayer insulating layer 31 is 20 μm to 40 μm. The first interlayer insulating layer 31 may be formed from a resin containing glass cloth.
Subsequently, as shown in FIG. 3B, the first via hole VH <b> 1 reaching the first wiring layer 21 is formed by processing the first interlayer insulating layer 31 with a laser. As the laser, a CO 2 laser, a UV-YAG laser, an excimer laser, or the like is used. The diameter of the first via hole VH1 is 20 μm to 60 μm.
The first via hole VH1 is formed in a tapered shape whose diameter decreases from the upper surface of the first interlayer insulating layer 31 in the thickness direction.
Thereafter, as shown in FIG. 3C, a second wiring layer 22 connected to the first wiring layer 21 via the via conductor in the first via hole VH1 is formed. The second wiring layer 22 is formed by a semi-additive method.
More specifically, as shown in FIG. 4A, first, a seed layer 22a made of copper or the like having a thickness of about 1 μm is formed in the first via hole VH1 and on the first interlayer insulating layer 31 by electroless plating. To do.
Further, as shown in FIG. 4B, a plating resist 13 having an opening 13a in a region including the first via hole VH1 is formed on the seed layer 22a.
Next, as shown in FIG. 4C, a metal plating layer 22b made of copper or the like is formed in the opening 13a of the plating resist 13 from the first via hole VH1 by electrolytic plating using the seed layer 22a as a plating power feeding path. To do.
Further, as shown in FIG. 5A, the plating resist 13 is removed to expose the seed layer 22a.
Subsequently, the seed layer 22a is removed by wet etching using the metal plating layer 22b as a mask. Thereby, as shown in FIG. 5B, the second wiring layer 22 is formed from the seed layer 22a and the metal plating layer 22b.
At this time, the seed layer 22a formed by electroless plating has a much higher etching rate than the metal plating layer 22b formed by electrolytic plating. For this reason, the seed layer 22a is etched in an undercut shape that bites inward from the side surface of the metal plating layer 22b. Further, since the wet etching is isotropic etching, the second wiring layer 22 is formed in a state where the width of the metal plating layer 22b is narrow.
Next, as shown in FIG. 6A, the first interlayer insulating layer 31 and the second wiring layer 22 are formed on the first interlayer insulating layer 31 by the same method as the method for forming the first interlayer insulating layer 31 shown in FIG. A second interlayer insulating layer 32 is formed. Further, a second via hole VH2 reaching the second wiring layer 22 is formed in the second interlayer insulating layer 32 as in the case of FIG.
Subsequently, as shown in FIG. 6 (b), it is connected to the second wiring layer 22 through the via conductor in the second via hole VH2 by the same method as in FIGS. 4 (a) to 5 (b). A third wiring layer 23 is formed on the second interlayer insulating layer 32.
Further, as shown in FIG. 6C, on the second interlayer insulating layer 32 and the third wiring layer 23 by the same method as the method for forming the first interlayer insulating layer 31 of FIG. A third interlayer insulating layer 33 is formed. Further, a third via hole VH3 reaching the third wiring layer 23 is formed in the third interlayer insulating layer 33 as in the case of FIG.
Further, as shown in FIG. 6D, the second connection to the third wiring layer 23 through the via conductor in the third via hole VH3 by the same method as in FIGS. 4A to 5B. A four wiring layer 24 is formed on the third interlayer insulating layer 33. The thicknesses of the second to fourth wiring layers 22, 23, 24 are set to about 15 μm, for example. The line (wiring width): space (wiring interval) of the first to fourth wiring layers 21 to 24 is selected from a range of 10 μm: 10 μm to 50 μm: 50 μm, for example.
Thereafter, as shown in FIG. 7A, the solder resist 12 having the opening 12a provided on the connection portion of the fourth wiring layer 24 is formed on the third interlayer insulating layer 33 as a protective insulating layer. .
As described above, the base wiring board 2 including the first to fourth wiring layers 21 to 24 is formed on the first metal plate 10.
Subsequently, as shown in FIG. 7B, the first metal plate 10 is removed by wet etching. An ammonium-based alkaline aqueous solution is used as an etchant for wet etching.
At this time, the lowermost gold layer 21a (FIG. 2D) and the first interlayer insulating layer 31 of the first wiring layer 21 are exposed, and they function as a wet etching stopper. Corrosion of the nickel layer 21b and the copper layer 21c (FIG. 2 (d)) is prevented.
Thus, the first metal plate 10 is removed from the structure of FIG. 7A, and the base wiring board 2 is obtained. The base wiring board 2 is manufactured as a coreless board that does not have a core board. The lower surface of the first wiring layer 21 of the base wiring board 2 and the lower surface of the first interlayer insulating layer 31 are flush with each other and exposed.
Next, as shown in FIG. 7C, a second metal plate 10a such as a copper plate is prepared. Then, the base wiring board 2 shown in FIG. 7B is turned upside down, and the base wiring board 2 is disposed on the second metal plate 10a via an epoxy adhesive 14. At this time, the adhesive 14 is disposed only on the outer peripheral portion of the base wiring board 2.
Furthermore, the laminated body is hot-pressed in a vacuum state to cure the adhesive 14 and partially bond them together.
As a result, the peripheral edge portion of the second metal plate 10 a is bonded to the base wiring board 2, and the central portion of the second metal plate 10 a is simply placed on the base wiring board 2.
On the upper surface of the base wiring board 2, the metal 21a (FIG. 2D) of the first wiring layer 21 is exposed. The upper surface of the first wiring layer 21 of the base wiring board 2 and the upper surface of the first interlayer insulating layer 31 are flush with each other.
In this embodiment, instead of using the silicon interposer 200 described in the preliminary matter, a rewiring portion having fine wiring similar to the silicon interposer 200 is directly formed on the base wiring substrate 2.
First, as shown in FIG. 8A, a photosensitive liquid resin layer 34 a is applied to the flat upper surface of the base wiring board 2. Further, after exposure through a photomask (not shown) based on photolithography, development is performed, and baking is performed to cure.
Thereby, as shown in FIG. 8B, a fourth interlayer insulating layer 34 provided with the fourth via hole VH <b> 4 reaching the first wiring layer 21 is formed on the upper surface of the base wiring substrate 2.
In order to form a fine rewiring portion on the base wiring board 2, the thickness of the fourth interlayer insulating layer 34 is set to be thinner than the thicknesses of the first to third interlayer insulating layers 31 to 33 of the base wiring board 2. The
For example, the thickness of the fourth interlayer insulating layer 34 is 2 μm to 10 μm, preferably about 5 μm, and the diameter of the fourth via hole VH4 is 10 μm to 20 μm.
Since the upper surface of the base wiring board 2 is flat and the fourth interlayer insulating layer 34 is thin, a sufficient depth of focus for photolithography can be secured. Therefore, the fine fourth via hole VH4 is formed in the base wiring board 2. It can be formed uniformly and accurately.
The fourth via hole VH4 of the fourth interlayer insulating layer 34 is disposed on the base wiring board 2 that is turned upside down during the manufacturing process, and is formed in a tapered shape whose diameter decreases from the upper surface in the thickness direction. For this reason, the fourth via hole VH4 is arranged in a tapered shape opposite to the first via hole VH1 of the base wiring board 2.
Next, as shown in FIG. 8C, a first rewiring layer 41 connected to the first wiring layer 21 through the via conductor in the fourth via hole VH4 is formed on the fourth interlayer insulating layer 34. . The first redistribution layer 41 is formed by a semi-additive method.
More specifically, as shown in FIG. 9A, first, a seed layer 41a is formed in the fourth via hole VH4 and on the fourth interlayer insulating layer 34 by sputtering. As shown in the partial cross-sectional view of FIG. 9A, the seed layer 41a is formed of a titanium (Ti) layer 41x having a thickness of 20 nm / a copper (Cu) layer 41y having a thickness of 300 nm in order from the bottom.
The titanium layer 41x functions as an adhesion layer that adheres the fourth interlayer insulating layer 34 (resin) and the copper layer 41y.
By forming the seed layer 41a by the sputtering method, the film formation is more reliable than when the electroless plating is employed, so that the thickness can be set thin. For this reason, the seed layer 41a can be easily etched, and the rewiring layer can be made finer.
Thereafter, as shown in FIG. 9B, a plating resist 15 having an opening 15a in a region including the fourth via hole VH4 is formed on the seed layer 41a.
At this time, since the upper surface of the base wiring board 2 is flat, a sufficient depth of focus of photolithography can be secured, and therefore the opening 15a of the plating resist 15 can be formed uniformly and accurately in the base wiring board 2. it can.
Next, as shown in FIG. 9C, a metal plating layer 41b made of copper or the like is formed from the fourth via hole VH4 to the opening 15a of the plating resist 15 by electrolytic plating using the seed layer 41a as a plating power feeding path. To do. The thickness of the metal plating layer 41b is set to 1 μm to 4 μm, for example.
Further, as shown in FIG. 10A, the plating resist 15 is removed to expose the seed layer 41a. Subsequently, the seed layer 41a is etched and removed by anisotropic dry etching using a chlorine-based gas using the metal plating layer 41b as a mask.
Thereby, as shown in FIG. 10B, the first redistribution layer 41 is formed from the seed layer 41a and the metal plating layer 41b. The total thickness of the first rewiring layer 41 is about 5 μm or less, preferably 2 μm to 3 μm.
The anisotropic dry etching is performed by a dry etching apparatus such as an RIE (Reactive Ion Etching) apparatus or an ICP (Inductively Coupled Plasma) apparatus.
By employing anisotropic dry etching, the metal plating layer 41 can be kept from being thinned, and the seed layer 41a is not side-etched from the side surface of the metal plating layer 41b. In addition, by employing the sputtering method, the seed layer 41a can be thinned, which is advantageous for miniaturization.
Therefore, a fine rewiring layer 41 having a line: space of 1 μm: 1 μm to 5 μm: 5 μm can be formed within a design specification with a high yield.
When the seed layer 41a is formed from copper, the copper chloride generated during dry etching has low volatility, so the etching apparatus stage temperature is set to 100 ° C. to 200 ° C. and etched in a high temperature atmosphere. Is preferred.
As described above with reference to FIGS. 4A to 5B, when the seed layer is removed by wet etching, the first redistribution layer 41 is likely to be thinned or skipped, and the fine first It is difficult to form the rewiring layer 41 with a high yield.
In this way, the width of the first rewiring layer 41 can be set narrower than the widths of the first to fourth wiring layers 21 to 24 of the base wiring board 2.
Further, since the seed layer 41a is removed by anisotropic dry etching when forming the first redistribution layer 41, the width of the seed layer 41a is equal to or wider than the width of the metal plating layer 41b. In the example of FIG. 10B, the width of the seed layer 41a is the same as the width of the metal plating layer 41b.
In addition to this, depending on the dry etching conditions, the side surface of the seed layer 41a has a skirt shape that widens from the lower end to the lower side of the metal plating layer 41b, and the width of the seed layer 41a is larger than the width of the metal plating layer 41b. It may become wide.
Next, as shown in FIG. 11A, a fifth interlayer insulation in which a fifth via hole VH5 is provided on the first redistribution layer 41 by the same method as in FIGS. 8A and 8B described above. A layer 35 is formed on the fourth interlayer insulating layer 34.
Subsequently, as shown in FIG. 11B, the first redistribution layer 41 is connected through the via conductor in the fifth via hole VH5 by the same method as in FIGS. 9A to 10B. A second redistribution layer 42 is formed on the fifth interlayer insulating layer 35.
Further, as shown in FIG. 11C, a sixth interlayer insulating layer in which a sixth via hole VH6 is provided on the second redistribution layer 42 by the same method as in FIGS. 8A and 8B described above. 36 is formed on the fifth interlayer insulating layer 35.
Next, as shown in FIG. 12A, the third redistribution layer 43 connected to the second redistribution layer 42 in the sixth via hole VH6 by the same method as in FIGS. 9A to 10B. Form. The third redistribution layer 43 is formed as a post electrode protruding upward from the sixth via hole VH6. The third redistribution layer 43 is formed with a height of about 10 μm from the upper surface of the sixth interlayer insulating layer 36.
As described above, the rewiring part 3 including the first to third rewiring layers 41, 42, 43 and the fourth to sixth interlayer insulating layers 34, 35, 36 is formed on the base wiring board 2.
Thereafter, as shown in FIG. 12B, the second metal plate is formed from the upper surface of the sixth interlayer insulating layer 36 at a position inside the region where the adhesive 14 of the structure of FIG. Cut to the bottom of 10a. At this time, in the structure shown in FIG. 12B, the second metal plate 10a and the base wiring board 2 are not bonded to each other in the region inside the position of the adhesive 14, so that both can be easily separated. it can.
Thereby, as shown in FIG. 13, the wiring board 1 of this embodiment is obtained.
As described above, in the method for manufacturing a wiring board according to the present embodiment, after the base wiring board 2 is formed on the first metal plate 10, the first metal plate 10 is removed. Next, the rewiring portion 3 connected to the first wiring layer 21 is formed on the flat exposed surface of the base wiring board 2.
In the rewiring section 3, a photosensitive resin material is patterned by photolithography to form thin first to third interlayer insulating layers 35, 36, and 37 having a fine via hole and a thickness of about 5 μm. can do.
Further, when the first redistribution layer 41 or the like is formed by a semi-additive method, the seed layer 41a is formed as a thin film by a sputtering method, and the seed layer 41a is removed using the metal plating layer 41b as a mask. Uses dry etching.
By using such a dry process, the fine first to third redistribution layers 41 to 43 equivalent to the silicon interposer can be formed.
In the above-described embodiment, the first to third rewiring layers 41 to 43 are formed by a semi-additive method. As another form, a metal layer such as a titanium layer / copper layer is formed on one surface by sputtering, a resist pattern is formed by photolithography, and then the metal layer is etched by anisotropic dry etching, thereby rewiring. A layer may be formed.
As shown in FIG. 13, the wiring board 1 of this embodiment includes a base wiring board 2 and a rewiring unit 3 formed thereon.
Since the wiring substrate 1 of this embodiment is manufactured by the manufacturing method described above, the first interlayer insulating layer 31 is disposed on the base wiring substrate 2 in the lateral direction and the lower side of the first wiring layer 21. The lower surface and side surfaces of the first wiring layer 21 are embedded in the first interlayer insulating layer 31, and the upper surface of the first wiring layer 21 is exposed from the first interlayer insulating layer 31. The upper surface of the first wiring layer 21 and the upper surface of the first interlayer insulating layer 31 are flush with each other.
The first interlayer insulating layer 31 includes a first via hole VH 1 below the first wiring layer 21. The first via hole VH 1 is formed so as to reach the lower surface of the first wiring layer 21 from the lower surface of the first interlayer insulating layer 31.
A second wiring layer 22 connected to the first wiring layer 21 via a via conductor in the first via hole VH1 is formed under the first interlayer insulating layer 31.
Similarly, a second interlayer insulating layer 32 is formed in the lateral direction and the lower side of the second wiring layer 22. The second interlayer insulating layer 32 includes a second via hole VH <b> 2 below the second wiring layer 22. Under the second interlayer insulating layer 32, a third wiring layer 23 connected to the second wiring layer 22 via a via conductor in the second via hole VH2 is formed.
Similarly, a third interlayer insulating layer 33 is formed in the lateral direction and below the third wiring layer 23. In the third interlayer insulating layer 33, a third via hole VH 3 is formed under the third wiring layer 23. A fourth wiring layer 24 connected to the third wiring layer 23 through the via conductor in the third via hole VH3 is formed under the third interlayer insulating layer 33.
Further, below the third interlayer insulating layer 33, a solder resist 12 having an opening 12a provided on the connection portion of the fourth wiring layer 24 is formed as a protective insulating layer.
The second to fourth wiring layers 22 to 24 are formed so as to protrude downward from the lower surfaces of the first, second, and third interlayer insulating layers 31 to 33, respectively.
The first to third via holes VH1 to VH3 of the base wiring board 2 have a tapered shape whose diameter decreases from the lower surface of the first, second, and third interlayer insulating layers 31, 32, and 33 in the thickness direction. Is formed.
In addition, a fourth interlayer insulating layer 34 of the rewiring portion 3 is formed on the first interlayer insulating layer 31 of the base wiring board 2. The fourth interlayer insulating layer 34 includes a fourth via hole VH 4 on the first wiring layer 21 of the base wiring board 2.
On the fourth interlayer insulating layer 34, a first rewiring layer 41 connected to the first wiring layer 21 via a via conductor in the fourth via hole VH4 is formed. On the fourth interlayer insulating layer 34, a fifth interlayer insulating layer 35 having a fifth via hole VH5 is formed on the first redistribution layer 41.
On the fifth interlayer insulating layer 35, a second redistribution layer 42 connected to the first redistribution layer 41 through a via conductor in the fifth via hole VH5 is formed. On the fifth interlayer insulating layer 35, a sixth interlayer insulating layer 36 having a sixth via hole VH6 is formed on the second redistribution layer 42.
In the sixth via hole VH6, a third rewiring layer 43 connected to the second rewiring layer 42 and protruding upward from the sixth interlayer insulating layer 36 is formed as a post electrode.
Since the rewiring part 3 is formed on the base wiring board 2 that is turned upside down during the manufacturing, the fourth to sixth via holes V4 to V6 of the rewiring part 3 are the first to third via holes of the base wiring board 2. It is arranged in a tapered shape opposite to VH1 to VH3.
A rewiring portion 3 is formed from the first to third rewiring layers 41 to 43 and the fourth to sixth interlayer insulating layers 34 to 36.
The wiring board 1 of this embodiment has a structure in which the rewiring part 3 is directly formed on the flat surface where the first wiring layer 21 of the coreless type base wiring board 2 is exposed. The widths of the first to third rewiring layers 41 to 43 of the rewiring unit 3 are set to be narrower than the widths of the first to fourth wiring layers 21 to 24 of the base wiring board 2.
Preferably, each of the rewiring layers 41 to 43 of the rewiring portion 3 is a fine wiring having a line: space of 1 μm: 1 μm-5 μm: 5 μm, and can serve as a silicon interposer. The thicknesses of the fourth to sixth interlayer insulating layers 34 to 36 of the redistribution part 3 are set to be thinner than the thicknesses of the first to third interlayer insulating layers 31 to 33 of the base wiring board 2.
Thus, in the wiring board 1 of the present embodiment, the base wiring board 2 and the rewiring portion 3 that functions as a silicon interposer are integrally formed.
For this reason, it is not necessary to use a silicon interposer that has high technical hurdles and high manufacturing costs.
When using a silicon interposer, the thickness of the silicon substrate alone is about 100 μm or more, and considering the formation of multilayer wiring layers on both sides thereof, there is a limit in reducing the thickness.
However, in the wiring substrate 1 of the present embodiment, a silicon substrate is not used for the rewiring part 3, and the thickness of the interlayer insulating layer can be set as thin as about 5 μm, and the thickness of the rewiring layer can be set as thin as 2 μm to 3 μm. The thickness can be reduced as compared with the case where a silicon interposer is used.
FIG. 14 shows an example of a semiconductor device in which a semiconductor chip is mounted on the wiring board 1 of FIG. As shown in FIG. 14, the bump electrode 52 of the semiconductor chip 50 is flip-chip connected to the third rewiring layer 43 of the rewiring part 3 of the wiring board 1 of FIG. Further, the underfill resin 54 is filled in the gap between the semiconductor chip 50 and the rewiring portion 3 of the wiring board 1.
Further, the external connection terminals 56 are formed by mounting solder balls on the fourth wiring layer 24 below the base wiring board 2 of the wiring board 1.
In this way, the narrow pitch bump electrodes 52 of the semiconductor chip 50 are connected to the rewiring unit 3 having fine wiring, and the pitch is converted from the rewiring unit 3 to the base wiring board 2.
When the silicon interposer is used, a series of steps of mounting the silicon interposer on the base wiring substrate and further mounting the semiconductor chip on the silicon interposer is necessary. However, in this embodiment, it is only necessary to mount the semiconductor chip 50 on the rewiring part 3 of the wiring board 1, and the mounting process can be simplified.
Although the semiconductor chip 50 is illustrated as an electronic component mounted on the wiring board 1, it can be used as a mounting substrate for various electronic components.
DESCRIPTION OF SYMBOLS 1 ... Wiring board, 2 ... Base wiring board, 3 ... Rewiring part, 10 ... 1st metal plate, 10a ... 2nd metal plate, 11, 13, 15 ... Plating resist, opening ... 11a, 12a, 13a, 15a , 12 ... Solder resist, 14 ... Adhesive, 21 ... First wiring layer, 22 ... Second wiring layer, 22a, 41a ... Seed layer, 22b, 41b ... Metal plating layer, 23 ... Third wiring layer, 24 ... First 4 wiring layers, 31 ... first interlayer insulating layer, 32 ... second interlayer insulating layer, 33 ... third interlayer insulating layer, 34 ... fourth interlayer insulating layer, 35 ... fifth interlayer insulating layer, 36 ... sixth interlayer insulating Layer 41... First redistribution layer 42. Second redistribution layer 43 43 third redistribution layer 50 semiconductor chip 52 bump electrode 54 underfill resin 56 external connection terminal VH1, VH2, VH3, VH4, VH5, VH6 ... via holes.
A first insulating layer in which the first wiring layer is embedded and a first via hole is formed under the first wiring layer;
A base wiring board comprising: a second wiring layer formed under the first insulating layer and connected to the first wiring layer via a via conductor in the first via hole;
A second insulating layer formed on the base wiring substrate and having a second via hole formed on the first wiring layer;
A redistribution portion including a redistribution layer formed on the second insulating layer and connected to the first wiring layer via a via conductor in the second via hole,
The rewiring layer is formed of a seed layer and a metal plating layer thereon, and the width of the seed layer is the same as or wider than the width of the metal plating layer.
The upper surface of the first wiring layer and the upper surface of the first insulating layer of the base wiring substrate are flush with each other, and the second wiring layer protrudes from the lower surface of the second insulating layer. The wiring board according to claim 1.
The first via hole has a tapered shape whose diameter decreases from the lower surface of the first insulating layer in the thickness direction, and the second via hole has a tapered shape opposite to the first via hole. The wiring board according to claim 1 or 2.
The width of the rewiring layer is narrower than the width of the first and second wiring layers, and the thickness of the second insulating layer is thinner than the thickness of the first insulating layer. The wiring board as described in any one of Claims.
5. The wiring board according to claim 1, wherein the line: space of the rewiring layer is selected from a range of 1 μm: 1 μm to 5 μm: 5 μm.
Forming a first wiring layer on the metal plate;
Forming a first insulating layer provided with a first via hole on the first wiring layer on the metal plate;
Forming a second wiring layer on the first insulating layer connected to the first wiring layer via a via conductor in the first via hole;
Removing the metal plate;
Forming a second insulating layer provided with a second via hole on the first wiring layer on the first insulating layer;
Forming a seed layer in the second via hole and on the second insulating layer;
Forming a plating resist having an opening in a region including the second via hole;
Forming a metal plating layer on the opening of the second via hole and the plating resist by electrolytic plating;
And a step of forming a rewiring layer by removing the seed layer by anisotropic dry etching using the metal plating layer as a mask.
In the step of removing the metal plate,
The method of manufacturing a wiring board according to claim 6, wherein the lower surface of the first wiring layer and the lower surface of the first insulating layer are exposed in a flush manner.
8. The method of manufacturing a wiring board according to claim 6, wherein in the step of forming the seed layer, the seed layer is formed by a sputtering method.
The width of the redistribution layer is narrower than the width of the first and second wiring layers, and the thickness of the second insulating layer is set to be thinner than the thickness of the first insulating layer. The manufacturing method of the wiring board as described in any one of thru | or 8.
10. The method of manufacturing a wiring board according to claim 6, wherein the line: space of the rewiring layer is selected from a range of 1 μm: 1 μm to 5 μm: 5 μm.
JP2013025210A 2013-02-13 2013-02-13 Wiring board and manufacturing method thereof Pending JP2014154800A (en)
JP2013025210A JP2014154800A (en) 2013-02-13 2013-02-13 Wiring board and manufacturing method thereof
US14/141,765 US9455219B2 (en) 2013-02-13 2013-12-27 Wiring substrate and method of manufacturing the same
JP2014154800A true JP2014154800A (en) 2014-08-25
JP2014154800A5 JP2014154800A5 (en) 2016-01-28
ID=51296947
JP2013025210A Pending JP2014154800A (en) 2013-02-13 2013-02-13 Wiring board and manufacturing method thereof
US (1) US9455219B2 (en)
JP (1) JP2014154800A (en)
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2013-02-13 JP JP2013025210A patent/JP2014154800A/en active Pending
2013-12-27 US US14/141,765 patent/US9455219B2/en active Active
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US9455219B2 (en) 2016-09-27
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