Source: http://www.google.com/patents/US7721341?ie=ISO-8859-1&dq=6,957,233
Timestamp: 2014-07-30 15:40:06
Document Index: 12114203

Matched Legal Cases: ['Application No. 01127346', 'Application No. 01127346', 'Application No. 01127346', 'art.6', 'Application No. 2001', 'Application No. 2001']

Patent US7721341 - Method and system for allowing code to be securely initialized in a computer - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA memory controller prevents CPUs and other I/O bus masters from accessing memory during a code (for example, trusted core) initialization process. The memory controller resets CPUs in the computer and allows a CPU to begin accessing memory at a particular location (identified to the CPU by the memory...http://www.google.com/patents/US7721341?utm_source=gb-gplus-sharePatent US7721341 - Method and system for allowing code to be securely initialized in a computerAdvanced Patent SearchPublication numberUS7721341 B2Publication typeGrantApplication numberUS 11/152,909Publication dateMay 18, 2010Filing dateJun 15, 2005Priority dateNov 22, 2000Fee statusPaidAlso published asEP1209563A2, EP1209563A3, EP1209563B1, US6938164, US7543335, US20050144476, US20050235166Publication number11152909, 152909, US 7721341 B2, US 7721341B2, US-B2-7721341, US7721341 B2, US7721341B2InventorsPaul England, Bryan WillmanOriginal AssigneeMicrosoft CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (106), Non-Patent Citations (20), Referenced by (6), Classifications (13), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for allowing code to be securely initialized in a computerUS 7721341 B2Abstract A memory controller prevents CPUs and other I/O bus masters from accessing memory during a code (for example, trusted core) initialization process. The memory controller resets CPUs in the computer and allows a CPU to begin accessing memory at a particular location (identified to the CPU by the memory controller). Once an initialization process has been executed by that CPU, the code is operational and any other CPUs are allowed to access memory (after being reset), as are any other bus masters (subject to any controls imposed by the initiated code).
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