Source: http://www.google.com/patents/US6239488?dq=6,073,142
Timestamp: 2014-12-28 12:43:46
Document Index: 626575415

Matched Legal Cases: ['art 200', 'art 200', 'art 200', 'art 200', 'art 201', 'art 701', 'art 702', 'art 701', 'art 701', 'art 702']

Patent US6239488 - Method for mounting a semiconductor chip on a substrate, and semiconductor ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device is adapted for mounting on a substrate that has a chip-mounting region provided with a plurality of solder points. The semiconductor device includes a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads which are disposed on the pad-mounting...http://www.google.com/patents/US6239488?utm_source=gb-gplus-sharePatent US6239488 - Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrateAdvanced Patent SearchPublication numberUS6239488 B1Publication typeGrantApplication numberUS 09/520,719Publication dateMay 29, 2001Filing dateMar 8, 2000Priority dateJan 14, 2000Fee statusLapsedAlso published asDE10027852A1, DE10101948A1, DE10101948B4, DE10110453A1, DE10117239A1, US6333561, US20020072148Publication number09520719, 520719, US 6239488 B1, US 6239488B1, US-B1-6239488, US6239488 B1, US6239488B1InventorsI-Ming ChenOriginal AssigneeI-Ming ChenExport CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (7), Classifications (41), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetMethod for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrateUS 6239488 B1Abstract A semiconductor device is adapted for mounting on a substrate that has a chip-mounting region provided with a plurality of solder points. The semiconductor device includes a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads which are disposed on the pad-mounting surface at locations that are offset from locations of corresponding ones of the solder points on the chip-mounting region. Conductive bodies are formed on the pad-mounting surface to establish the required electrical connection among the bonding pads and the corresponding ones of the solder points.
I claim: 1. A semiconductor device adapted for mounting on a substrate, the substrate having a chip-mounting region provided with a plurality of solder points, said semiconductor device comprising:
a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads which are disposed on said pad-mounting surface at locations that are offset from locations of corresponding ones of the solder points on the chip-mounting region; and a plurality of conductive bodies, each of which has an extension portion that is connected electrically to a registered one of said bonding pads and that serves as a circuit trace, and an electrical connection portion that is formed on one end of said extension portion and that extends to a location corresponding to that of a respective one of the solder points on the chip-mounting region of the substrate, said conductive bodies being formed by: superimposing a steel plate on said pad-mounting surface of said semiconductor chip, said steel plate being formed with a plurality of holes at positions registered with said bonding pads on said pad-mounting surface, each of said holes including a first hole part that exposes at least a part of the registered one of said bonding pads on said pad-mounting surface, and a second hole part that exposes a respective portion of said pad-mounting surface and that extends from said first hole part to a location corresponding to that of the respective one of the solder points on the chip-mounting region of the substrate, said holes being confined by walls that cooperate with said pad-mounting surface to form contact receiving spaces; and using a conductive metal paste as printing material, printing on said steel plate to form said conductive bodies in said contact receiving spaces, said extension portions of said conductive bodies being disposed in said first hole parts of said holes, said electrical connection portions of said conductive bodies being disposed in said second hole parts of said holes. 2. The semiconductor device of claim 1, further comprising a plurality of conductive balls, each of which is disposed on said electrical connection portion of a respective one of said conductive bodies.
3. The semiconductor device of claim 1, further comprising a protective layer formed on said pad-mounting surface to enclose connections formed among said extension portions of said conductive bodies and said bonding pads on said pad-mounting surface.
4. The semiconductor device of claim 3, wherein said protective layer is formed from an epoxy resin.
5. The semiconductor device of claim 1, wherein said conductive bodies are non-intersecting.
6. A semiconductor device adapted for mounting on a substrate, the substrate having a chip-mounting region provided with a plurality of solder points, said semiconductor device comprising:
a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads which are disposed on said pad-mounting surface at locations that are offset from locations of corresponding ones of the solder points on the chip-mounting region; a photoresist layer formed on said pad-mounting surface of said semiconductor chip, said photoresist layer being formed with a plurality of contact receiving cavities at positions registered with said bonding pads on said pad-mounting surface, each of said contact receiving cavities including a first cavity part that exposes at least a part of the registered one of said bonding pads on said pad-mounting surface, and a second cavity part that exposes a respective portion of said pad-mounting surface and that extends from said first cavity part to a location corresponding to that of a respective one of the solder points on the chip-mounting region of the substrate; and a plurality of conductive bodies formed respectively in said contact receiving cavities, each of said conductive bodies having an extension portion that is disposed in said first cavity part so as to connect electrically with the registered one of said bonding pads and that serves as a circuit trace, and an electrical connection portion that is formed in said second cavity part on one end of said extension portion and that extends to the location corresponding to that of the respective one of the solder points on the chip-mounting region of the substrate. 7. The semiconductor device of claim 6, further comprising a plurality of conductive balls, each of which is disposed on said electrical connection portion of a respective one of said conductive bodies.
8. The semiconductor device of claim 6, further comprising a protective layer formed on said photoresist layer to cover connections formed among said extension portions of said conductive bodies and said bonding pads on said pad-mounting surface.
9. The semiconductor device of claim 8, wherein said protective layer is formed from an epoxy resin.
10. The semiconductor device of claim 6, wherein said conductive bodies are non-intersecting.
The invention relates to a method for mounting a semiconductor chip on a substrate and to a semiconductor device that is adapted for mounting on a substrate.
With the rapid advancement in semiconductor fabrication technology, the bonding pads on the surface of a semiconductor chip are getting smaller in size, and the distances between adjacent bonding pads are getting shorter. These can create difficulty when connecting the semiconductor chip to an external circuit, and can affect adversely the production yield.
SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for mounting a semiconductor chip on a substrate so as to overcome the aforesaid drawback.
Another object of the present invention is to provide a semiconductor device adapted for mounting on a substrate and capable of overcoming the aforesaid drawback.
According to one aspect of the invention, there is provided a method for mounting a semiconductor chip on a substrate having a chip-mounting region provided with a plurality of solder points. The semiconductor chip has a pad-mounting surface provided with a plurality of bonding pads, which are to be connected to corresponding ones of the solder points and which are disposed on the pad-mounting surface at locations that are offset from locations of the corresponding ones of the solder points on the chip-mounting region. The method comprises the steps of:
superimposing a steel plate on the pad-mounting surface of the semiconductor chip, the steel plate being formed with a plurality of holes at positions registered with the bonding pads on the pad-mounting surface, each of the holes including a first hole part that exposes at least a part of the registered one of the bonding pads on the pad-mounting surface, and a second hole part that exposes a respective portion of the pad-mounting surface and that extends from the first hole part to a location corresponding to that of a respective one of the solder points on the chip-mounting region of the substrate, the holes being confined by walls that cooperate with the pad-mounting surface to form contact receiving spaces; and
using a conductive metal paste as printing material, printing on the steel plate to form conductive bodies in the contact receiving spaces, each of the conductive bodies having an extension portion that is disposed in the first hole part so as to connect electrically with the registered one of the bonding pads and that serves as a circuit trace, and an electrical connection portion that is formed in the second hole part on one end of the extension portion and that extends to the location corresponding to that of the respective one of the solder points on the chip-mounting region of the substrate.
According to another aspect of the present invention, there is provided a method for mounting a semiconductor chip on a substrate having a chip-mounting region provided with a plurality of solder points. The semiconductor chip has a pad-mounting surface provided with a plurality of bonding pads, which are to be connected to corresponding ones of the solder points and which are disposed on the pad-mounting surface at locations that are offset from locations of the corresponding ones of the solder points on the chip-mounting region. The method comprises the steps of:
forming a photoresist layer on the pad-mounting surface of the semiconductor chip;
forming a plurality of contact receiving cavities in the photoresist layer at positions registered with the bonding pads on the pad-mounting surface, each of the contact receiving cavities including a first cavity part that exposes at least a part of the registered one of the bonding pads on the pad-mounting surface, and a second cavity part that exposes a respective portion of the pad-mounting surface and that extends from the first cavity part to a location corresponding to that of a respective one of the solder points on the chip-mounting region of the substrate; and
forming conductive bodies in the contact receiving cavities, each of the conductive bodies having an extension portion that is disposed in the first cavity part so as to connect electrically with the registered one of the bonding pads and that serves as a circuit trace, and an electrical connection portion that is formed in the second cavity part on one end of the extension portion and that extends to the location corresponding to that of the respective one of the solder points on the chip-mounting region of the substrate.
According to still another aspect of the present invention, a semiconductor device is adapted for mounting on a substrate having a chip-mounting region provided with a plurality of solder points. The semiconductor device comprises:
a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads which are disposed on the pad-mounting surface at locations that are offset from locations of corresponding ones of the solder points on the chip-mounting region; and
a plurality of conductive bodies, each of which has an extension portion that is connected electrically to a registered one of the bonding pads and that serves as a circuit trace, and an electrical connection portion that is formed on one end of the extension portion and that extends to a location corresponding to that of a respective one of the solder points on the chip-mounting region of the substrate. The conductive bodies are formed by:
superimposing a steel plate on the pad-mounting surface of the semiconductor chip, the steel plate being formed with a plurality of holes at positions registered with the bonding pads on the pad-mounting surface, each of the holes including a first hole part that exposes at least a part of the registered one of the bonding pads on the pad-mounting surface, and a second hole part that exposes a respective portion of the pad-mounting surface and that extends from the first hole part to a location corresponding to that of the respective one of the solder points on the chip-mounting region of the substrate, the holes being confined by walls that cooperate with the pad-mounting surface to form contact receiving spaces; and
using a conductive metal paste as printing material, printing on the steel plate to form the conductive bodies in the contact receiving spaces, the extension portions of the conductive bodies being disposed in the first hole parts of the holes, the electrical connection portions of the conductive bodies being disposed in the second hole parts of the holes.
According to a further aspect of the present invention, a semiconductor device is adapted for mounting on a substrate having a chip-mounting region provided with a plurality of solder points. The semiconductor device comprises:
a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads which are disposed on the pad-mounting surface at locations that are offset from locations of corresponding ones of the solder points on the chip-mounting region;
a photoresist layer formed on the pad-mounting surface of the semiconductor chip, the photoresist layer being formed with a plurality of contact receiving cavities at positions registered with the bonding pads on the pad-mounting surface, each of the contact receiving cavities including a first cavity part that exposes at least a part of the registered one of the bonding pads on the pad-mounting surface, and a second cavity part that exposes a respective portion of the pad-mounting surface and that extends from the first cavity part to a location corresponding to that of a respective one of the solder points on the chip-mounting region of the substrate; and
a plurality of conductive bodies formed respectively in the contact receiving cavities, each of the conductive bodies having an extension portion that is disposed in the first cavity part so as to connect electrically with the registered one of the bonding pads and that serves as a circuit trace, and an electrical connection portion that is formed in the second cavity part on one end of the extension portion and that extends to the location corresponding to that of the respective one of the solder points on the chip-mounting region of the substrate.
FIG. 1 is a sectional view illustrating a semiconductor chip to be mounted on a substrate according to the first preferred embodiment of a mounting method of the present invention;
FIG. 2 is a schematic view illustrating a steel plate used in the mounting method of the first preferred embodiment;
FIG. 3 is a schematic view illustrating the steel plate of FIG. 2 when superimposed upon the semiconductor chip of FIG. 1 in accordance with the mounting method of the first preferred embodiment;
FIG. 4 is a sectional view taken along lines IV�IV in FIG. 3;
FIG. 5 is a schematic view illustrating the semiconductor chip of FIG. 3 after undergoing a printing step according to the mounting method of the first preferred embodiment;
FIG. 7 is a schematic view illustrating a mask for the semiconductor chip of FIG. 5;
FIG. 8 is a sectional view illustrating a semiconductor device prepared according to the mounting method of the first preferred embodiment;
FIG. 9 is a sectional view illustrating the semiconductor device of FIG. 8 when mounted on a substrate in accordance with the mounting method of the first preferred embodiment;
FIG. 10 is a sectional view illustrating how a semiconductor device is mounted on a substrate in accordance with the second preferred embodiment of a mounting method according to the present invention;
FIG. 11 is a sectional view illustrating a semiconductor device prepared according to the third preferred embodiment of a mounting method of this invention;
FIG. 12 is a schematic view illustrating a semiconductor chip after undergoing a printing step according to the fourth preferred embodiment of a mounting method of this invention;
FIG. 13 is a schematic view illustrating a semiconductor chip after undergoing a printing step according to the fifth preferred embodiment of a mounting method of this invention;
FIG. 14 is a sectional view illustrating a semiconductor chip to be mounted on a substrate according to the sixth preferred embodiment of a mounting method according to the present invention;
FIG. 15 is a schematic view illustrating a steel plate used in the mounting method of the sixth preferred embodiment;
FIG. 16 is a schematic view illustrating the steel plate of FIG. 15 when superimposed upon the semiconductor chip of FIG. 14 in accordance with the mounting method of the sixth preferred embodiment;
FIG. 17 is a sectional view taken along lines XVII�XVII in FIG. 16;
FIG. 18 is a schematic view illustrating the semiconductor chip of FIG. 17 after undergoing an etching step according to the mounting method of the sixth preferred embodiment; and
FIG. 19 is a sectional view illustrating a semiconductor device prepared according to the mounting method of the sixth preferred embodiment.
Referring to FIG. 1, in the first preferred embodiment of a mounting method according to the present invention, there is provided a semiconductor chip 1 having a pad-mounting surface 10 with a plurality of bonding pads 11 (only one is shown in this Figure) provided thereon. The semiconductor chip 1 is to be mounted on a substrate 9 (see FIG. 9). The substrate 9, such as a system board, has a chip-mounting region provided with a plurality of solder points 90. The bonding pads 11 are to be connected to corresponding ones of the solder points 90, but are disposed on the pad-mounting surface 10 at locations that are offset from locations of the corresponding ones of the solder points 90 on the chip-mounting region.
Referring to FIGS. 2 to 4, there is provided a steel plate 2 that is superimposed on the pad-mounting surface 10 of the semiconductor chip 1. In this embodiment, the steel plate 2 is a printing screen plate, and is formed with a plurality of non-intersecting holes 20 at positions registered with the bonding pads 11 on the pad-mounting surface 10. Each of the holes 20 includes a first hole part 200 that exposes at least a part of the registered one of the bonding pads 11 on the pad-mounting surface 10, and a second hole part 200 that exposes a respective portion of the pad-mounting surface 10 and that extends from the first hole part 200 to a location corresponding to that of a respective one of the solder points 90 on the chip-mounting region of the substrate 9 (see FIG. 9). Each of the holes 20 is confined by a wall that cooperates with the pad-mounting surface 10 to form a contact receiving space.
Thereafter, as shown in FIGS. 5 and 6, non-intersecting conductive bodies 3 are formed respectively in the contact receiving spaces via a printing technique that uses a conductive metal paste as printing material. Upon removal of the steel plate 2 from the pad-mounting surface 10, the conductive bodies 3 are processed by heating and drying to harden the same. Preferably, the conductive metal paste is one that contains silver, gold, copper, iron, aluminum, tin or other conductive metal materials. Each of the conductive bodies 3 has an elongate extension portion 300 that is disposed in the first hole part 200 so as to connect electrically with the registered one of the bonding pads 11 and that serves as a circuit trace, and an electrical connection portion 301 that is formed in the second hole part 201 on one end of the extension portion 300 and that extends to the location corresponding to that of the respective one of the solder points 90 on the chip-mounting region of the substrate 9 (see FIG. 9) for electrical connection therewith.
Referring to FIGS. 7 and 8, after hardening the conductive bodies 3, a mask 4 is superimposed subsequently on the pad-mounting surface 10 of the semiconductor chip 1. The mask 4 is formed with an opening 40 to expose connections formed among the extension portions 300 of the conductive bodies 3 and the bonding pads 11 on the pad-mounting surface 10. The opening 40 is confined by a wall that cooperates with the pad-mounting surface 10 to form a protective-layer forming space. An insulator material, such as epoxy resin, fills the protective-layer forming space to form a protective layer 41 that encloses the connections formed among the extension portions 300 of the conductive bodies 3 and the bonding pads 11 on the pad-mounting surface 10. The mask 4 is removed from the semiconductor chip 1 thereafter. A semiconductor device is thus obtained, as shown in FIG. 8.
As shown in FIG. 9, the semiconductor device of FIG. 8 is mounted on the chip-mounting region of the substrate 9. The electrical connection portions 301 of the conductive bodies 3 are connected to the corresponding ones of the solder points 90 via conductive paste 91 on the latter, thereby establishing electrical connection between the semiconductor chip 1 and the substrate 9. Preferably, an adhesive layer 5 adheres the semiconductor device of FIG. 8 to the chip-mounting region of the substrate 9 to prevent relative movement therebetween prior to heating of the assembly of the semiconductor device and the substrate 9 so as to harden the conductive paste 91.
Referring to FIG. 10, in the second preferred embodiment of a mounting method according to the present invention, the electrical connection portions 301 of the conductive bodies 3 on the semiconductor device of FIG. 8 are connected to the corresponding ones of the solder points 90 on the chip-mounting region of the substrate 9 via solder paste 91′ on the latter, thereby establishing electrical connection between the semiconductor chip 1 and the substrate 9. The adhesive layer used in the first preferred embodiment can be eliminated due to the use of the solder paste 91′.
It should be understood that, by controlling the sizes of the holes 20 in the steel plate 2 (see FIGS. 2 to 4), the thickness of the electrical connection portions 301 of the conductive bodies 3 can be controlled accordingly. Referring to FIG. 11, in the third preferred embodiment of a mounting method according to the present invention, the electrical connection portions 301 of the conductive bodies 3 of this embodiment are thinner than the electrical connection portions 301 of the conductive bodies 3 of the embodiment shown in FIG. 8. Thus, after forming the conductive bodies 3 in the mounting method of the third preferred embodiment, a conductive ball 6, such as a solder ball, is provided on the electrical connection portion 301 of each of the conductive bodies 3. The conductive balls 6 are used to establish both mechanical and electrical connection between the semiconductor device of FIG. 11 and a substrate (not shown). When it is desired to replace the semiconductor device of FIG. 11 on the substrate, such as when replacing a defective semiconductor device or during upgrading, the assembly of the semiconductor device and the substrate is heated to melt the conductive balls 6, thereby permitting removal of the semiconductor device from the substrate.
Referring to FIG. 12, in the fourth preferred embodiment of a mounting method according to the present invention, the bonding pads 11 of the semiconductor chip 1 are disposed on opposite side portions of the pad-mounting surface 10.
Referring to FIG. 13, in the fifth preferred embodiment of a mounting method according to the present invention, the bonding pads 11 of the semiconductor chip 1 are disposed on four side portions of the pad-mounting surface 10.
Referring to FIG. 14, in the sixth preferred embodiment of a mounting method according to the present invention, there is provided a semiconductor chip 1 having a pad-mounting surface 10 with a plurality of bonding pads 11 (only one is shown in this Figure) provided thereon. Like the previous embodiments, the semiconductor chip 1 is to be mounted on a substrate 9, such as the system board of FIG. 9. As mentioned hereinbefore, the substrate 9 has a chip-mounting region provided with a plurality of solder points 90, and the bonding pads 11 are to be connected to corresponding ones of the solder points 90, but are disposed on the pad-mounting surface 10 at locations that are offset from locations of the corresponding ones of the solder points 90 on the chip-mounting region of the substrate 9. In this embodiment, a positive photoresist film layer 7 is formed on the pad-mounting surface 10 of the semiconductor chip 1.
Referring to FIGS. 15 to 17, there is provided a patterned mask 8 that is superimposed on the photoresist film layer 7. The patterned mask 8 is formed with a plurality of light transmissive portions 80 at positions registered with the bonding pads 11 on the pad-mounting surface 10. Using known lithography techniques, including exposure to ultraviolet light and chemical developing, the exposed portions of the photoresist film layer 7 are removed to form non-intersecting contact receiving cavities 70 therein, as shown in FIG. 18. The contact receiving cavities 70 are disposed at positions registered with the bonding pads 11 on the pad-mounting surface 10. Each of the contact receiving cavities 70 includes a first cavity part 701 that exposes at least a part of the registered one of the bonding pads 11 on the pad-mounting surface 10, and a second cavity part 702 that exposes a respective portion of the pad-mounting surface 10 and that extends from the first cavity part 701 to a location corresponding to that of a respective one of the solder points 90 on the chip-mounting region of the substrate 9 (see FIG. 9).
Thereafter, as shown in FIG. 19, non-intersecting conductive bodies 3 are formed respectively in the contact receiving cavities 70, such as by printing with the use of a conductive metal paste as printing material. Like the previous embodiments, each of the conductive bodies 3 has an extension portion 300 that is disposed in the first cavity part 701 so as to connect electrically with the registered one of the bonding pads 11 and that serves as a circuit trace, and an electrical connection portion 301 that is formed in the second cavity part 702 on one end of the extension portion 300 and that extends to the location corresponding to that of the respective one of the solder points 90 on the chip-mounting region of the substrate 9 (see FIG. 9). A protective layer 41, which is made from an insulator material, such as epoxy resin, is formed on the photoresist film layer 7 to cover the connections formed among the extension portions 300 of the conductive bodies 3 and the bonding pads 11 on the pad-mounting surface 10. A semiconductor device is thus obtained.
As to how the semiconductor device of FIG. 19 is mounted on the chip-mounting region of the substrate 9, this can be accomplished in a manner similar to that taught in the embodiments of FIGS. 9 and 10 and will not be detailed further for the sake of brevity.
Like the embodiment of FIG. 11, the electrical connection portions 301 of the conductive bodies 3 of this embodiment can be made thinner. Thus, after forming the conductive bodies 3 in the mounting method of this embodiment, a conductive ball, similar to the conductive ball 6 of FIG. 11, can be provided on the electrical connection portion 301 of each of the conductive bodies 3.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5990546 *Dec 29, 1995Nov 23, 1999Nitto Denko CorporationChip scale package type of semiconductor deviceUS6075712 *Jan 8, 1999Jun 13, 2000Intel CorporationFlip-chip having electrical contact pads on the backside of the chipUS6114754 *Nov 25, 1998Sep 5, 2000Nec CorporationTape automated bonding filmUS6143991 *May 28, 1996Nov 7, 2000Nec CorporationBump electrode with adjacent pad and insulation for solder flow stopping* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6437448 *Jan 18, 2001Aug 20, 2002I-Ming ChenSemiconductor device adapted for mounting on a substrateUS6602732 *Apr 11, 2002Aug 5, 2003Computech International Ventures LimitedMethod for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrateUS6610558 *Apr 17, 2002Aug 26, 2003Computech International Ventures LimitedMethod for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrateUS6707159 *Feb 16, 2000Mar 16, 2004Rohm Co., Ltd.Semiconductor chip and production process thereforUS7057292May 19, 2000Jun 6, 2006Flipchip International, LlcSolder bar for high power flip chipsUS20130026623 *Jul 29, 2011Jan 31, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor Devices, Packaging Methods and StructuresWO2001091183A1 *May 17, 2001Nov 29, 2001Flip Chip Technologies L L CSolder bar for high power flip chips* Cited by examinerClassifications U.S. Classification257/737, 257/773, 257/E21.508, 257/E23.166, 257/E23.021, 257/779, 257/E21.511, 257/738International ClassificationH05K3/12, H01L21/60, H01L23/532, H01L23/485, H01L23/12Cooperative ClassificationH01L24/48, H01L2224/11334, H01L2924/01029, H01L2924/01005, H01L24/81, H01L2924/01004, H01L2924/01033, H01L2224/81801, H01L2224/13099, H01L2224/48225, H01L2924/01006, H01L2924/01047, H01L24/11, H01L2924/01027, H01L23/5328, H01L2924/01082, H01L2924/014, H01L2924/01079, H01L24/13, H01L2924/01068, H01L2924/0105, H01L2224/13147, H01L2924/01013, H01L2224/13008European ClassificationH01L24/10, H01L24/11, H01L24/81, H01L23/532M4Legal EventsDateCodeEventDescriptionJul 16, 2013FPExpired due to failure to pay maintenance feeEffective date: 20130529May 29, 2013LAPSLapse for failure to pay maintenance feesJan 7, 2013REMIMaintenance fee reminder mailedOct 30, 2008FPAYFee paymentYear of fee payment: 8Feb 1, 2005ASAssignmentOwner name: EVERGRAND HOLDING LIMITED, VIRGIN ISLANDS, BRITISHFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:COMPUTECH INTERNATIONAL VENTURES LIMITED;REEL/FRAME:015640/0741Effective date: 20041110Owner name: EVERGRAND HOLDING LIMITED P.O. BOX 3152, ROAD TOWNFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:COMPUTECH INTERNATIONAL VENTURES LIMITED /AR;REEL/FRAME:015640/0741Nov 18, 2004FPAYFee paymentYear of fee payment: 4Sep 5, 2002ASAssignmentOwner name: COMPUTECH INTERNATIONAL VENTURES LIMITED, VIRGIN IFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, I-MING;REEL/FRAME:013258/0373Effective date: 20020801Owner name: COMPUTECH INTERNATIONAL VENTURES LIMITEDDRAKE CHAMFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, I-MING /AR;REEL/FRAME:013258/0373RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google