Source: http://www.google.com/patents/US7659902?dq=5572193
Timestamp: 2014-03-17 04:36:26
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Matched Legal Cases: ['art/9612', 'art4', 'art/9606', 'art4', 'art/9606', 'art7', 'art/9606', 'art6', 'art/9606', 'art8', 'art/9606', 'art5', 'art 2']

Patent US7659902 - API communications for vertex and pixel shaders - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized...http://www.google.com/patents/US7659902?utm_source=gb-gplus-sharePatent US7659902 - API communications for vertex and pixel shadersAdvanced Patent SearchPublication numberUS7659902 B2Publication typeGrantApplication numberUS 11/426,485Publication dateFeb 9, 2010Filing dateJun 26, 2006Priority dateMar 7, 2000Fee statusPaidAlso published asUS6819325, US6963345, US7116332, US7142216, US7280111, US20020003541, US20050030312, US20050128207, US20050140669, US20050280654, US20060244753Publication number11426485, 426485, US 7659902 B2, US 7659902B2, US-B2-7659902, US7659902 B2, US7659902B2InventorsCharles N. Boyd, Michael A. ToelleOriginal AssigneeMicrosoft CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (19), Non-Patent Citations (76), Classifications (17), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetAPI communications for vertex and pixel shadersUS 7659902 B2Abstract A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.
CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 10/937,031, filed Sep. 9, 2004, entitled �API COMMUNICATIONS FOR VERTEX AND PIXEL SHADERS�, which is a continuation of U.S. patent application Ser. No. 09/801,079, filed Mar. 6, 2001, now U.S. Pat. No. 6,819,325, entitled, �API COMMUNICATIONS FOR VERTEX AND PIXEL SHADERS�, which claims priority to U.S. Provisional Patent Application Ser. No. 60/187,535, filed Mar. 7, 2000, entitled, �ASSEMBLY LANGUAGE FOR PROCEDURAL SHADERS IN AN IMMEDIATE MODE GRAPHICS API�. The entireties of the aforementioned applications are incorporated herein by reference.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS The present invention provides a 3-D graphics application programming interface (API) enabling software applications to control hardware in a way that is intuitive to software designers. This new method represents the hardware registers that control fixed function logic as a set of procedural instructions. This enables it to provide a consistent programming model for fixed-function hardware as well as for hardware that actually supports programmability.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4805098May 5, 1986Feb 14, 1989Mips Computer Systems, Inc.Write bufferUS4953073Feb 6, 1986Aug 28, 1990Mips Computer Systems, Inc.Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memoriesUS4959779Nov 28, 1988Sep 25, 1990Mips Computer Systems, Inc.Dual byte order computer architecture a functional unit for handling data sets with differnt byte ordersUS5027270Oct 11, 1988Jun 25, 1991Mips Computer Systems, Inc.Processor controlled interface with instruction streamingUS5398328Sep 27, 1993Mar 14, 1995Silicon Graphics, Inc.System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory ordersUS5580232May 4, 1995Dec 3, 1996Kobelco Compressors (America), Inc.Rotor assembly having a slip joint in the shaft assemblyUS5590294May 24, 1995Dec 31, 1996Silicon Graphics, Inc.Method and apparatus for retarting pipeline processingUS5673377Sep 2, 1994Sep 30, 1997Ray Dream, Inc.Method and system for displaying a representation of a three-dimensional object with surface features that conform to the surface of the three-dimensional objectUS5801717Apr 25, 1996Sep 1, 1998Microsoft CorporationMethod and system in display device interface for managing surface memoryUS5812136Oct 30, 1996Sep 22, 1998Microsoft CorporationSystem and method for fast rendering of a three dimensional graphical objectUS5822570Oct 30, 1996Oct 13, 1998Microsoft CorporationSystem and method for parsing and executing a single instruction stream using a plurality of tightly coupled parsing and execution unitsUS5844569Apr 25, 1996Dec 1, 1998Microsoft CorporationDisplay device interface including support for generalized flipping of surfacesUS5864703Oct 9, 1997Jan 26, 1999Mips Technologies, Inc.Method for providing extended precision in SIMD vector arithmetic operationsUS5880736Jun 20, 1997Mar 9, 1999Silicon Graphics, Inc.Method system and computer program product for shadingUS5949424Feb 28, 1997Sep 7, 1999Silicon Graphics, Inc.Method, system, and computer program product for bump mapping in tangent spaceUS5964843Apr 25, 1996Oct 12, 1999Microsoft CorporationSystem for enhancing device driversUS6008816Apr 25, 1996Dec 28, 1999Microsoft CorporationMethod and system for managing color specification using attachable palettes and palettes that refer to other palettesUS6452595Nov 27, 2000Sep 17, 2002Nvidia CorporationIntegrated graphics processing unit with antialiasingUS6525737Aug 20, 1999Feb 25, 2003Apple Computer, Inc.Graphics processor with pipeline state storage and retrievalNon-Patent CitationsReference1Abrash, M., "Inside Box Graphics," Dr. Dobb's J., Aug. 2000, 21-22, 24-26.2Antinori, F. et al., "Experience with a 30 cm2 silicon pixel plane in CERN experiment WA97," Nucl. Imtr. Meth. Phys. Res. A., 1995, 360, 91-97.3Bachstein, W. et al., "Single-Chip erledigt Multimedia," Elektronik, 1996, 17, 58-62.4Bajaj, C. et al., "Making 3D Textures Practical," IEEE: Proceedings-Seventh Pacific Conference on Computer Graphics and Applications, Oct. 5-7, 1999, 259-269.5Bakalash, R. et al., "A Barrel Shift Microsystem for Parallel Processing," in Micro 23 Microprogramming and Microarchitecture, IEEE: Proceedings of the 23rd Annual Workshop and Symposium, Orlando Florida, Nov. 27-29, 1990, 223-229.6Bankston, J. et al., "Pipeline Processing with Modula-2," J. Pascal, Ada, & Modula-2, 1986,5(5), 46-51.7Biernat, M.J. et al., "Approximate Shadow Generation," IEEE Montech Conferences, Nov. 9-12, 1987, 97-101.8Brechbiihler, CH. et al., "Parametrization of Closed Surfaces for 3-D Shape Description," Comp. Vision Image Understanding, Mar. 1995, 61(2), 154-170.9Chen, Li, "Generalization Discrete Object Tracking Algorithms and Implementation," in Vision Geometry VI, Proceedings of SPIE, Melter, RA. et al, (eds.), Jul. 28-29, 1997, 3168, 184-195.10Chiarulli, D.M. et al., "Draft: A Dynamically Reconfigurable Processor for Integer Arithmetic," IEEE: Proceedings-7TH Symposium on Computer Arithmetic, University of Illinois, Hwang, K. (ed.), Jun. 4-6, 1985, 309-317.11Conference Paper, "A Shading and Compositing Processor based on Crossbar Switches and SRAM Memory," 1999, 4 pages.12Corrie, B. et al., "Data Shaders," Proceedings Visualization '93, San Jose, CA, Oct. 25-29, 1993, 275-282.13Cox, M. et al., "Multi-Level Texture Caching for 3D Graphics Hardware," IEEE: Proceedings-The 25th Annual International Symposium on Computer Architecture, Barcelona, Spain, Jun. 27-Jul. 1, 1998, 86-97.14Dietz, P.H. et al., "Simple Networks for Pixel Plane Median Filtering," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Dec., 1993, 40(12), 799-801.15Glazzard, N. et al., "Implementing a Shading Language," Computer Graphics 90, London, UK, Nov. 6-8, 1990, 111-121.16Gomes, J. et al., "Graphical Objects," The Visual Computer, 1996, 22, 269-282.17Gordon, R.L., Ph.D. et al., Window Management, Graphics, and Operating Systems, Operating Systems Review, Jul. 1987, 21(3), 5-8.18Goris, A. et al., "A Configurable Pixel Cache for Fast Image Generation," IEEE Computer Graphics and Applications, Mar. 1987, 24-32.19Grimes, J., et al., "A New Processor With 3-D Graphics Capabilities," NCGA '89 Conference Proceedings: 10th Annual Conference and Exposition Dedicated to Computer Graphics, Philadelphia, Pennsylvania, Apr. 17-20, 1989, vol. I, 275-284.20Grimes, J., et al., "The Intel i860 64-Bit Processor: A General-Purpose CPU with 3D Graphics Capabilities," IEEE Computer Graphics and Applications, Jul. 1989, 85-194.21Haig, T., "How to program in machine language," Electronics, Aug. 1982, 94-96, 98, 100-103.22Hanrahan, P. et al., "A Language for Shading and Lighting Calculations," Computer Graphics, 1990, 24(4), 289-298.23Harrison, J.P. et al., "The Role of Microcomputers in Interactive Graphical Planning," Engin. Software for Microcomputers, Proc., Apr. 1984, 631-641.24Ho, C-H et al., Efficient Point-Based Rendering Techniques for Haptic Display of Virtual Objects: Presence, Oct. 1999, 8(5), 477-491.25Hoffman, C. et al., "Automatic Surface Generation in Computer Aided Design." supported by the National Science Foundation, Department of Computer Science, Cornell University, Ithaca, New York, Jan. 1985, I-22.26Hummel, R., "Render Benders: 26 Graphics Cards for Fast 3-D," Byte, Mar. 1998, 112-119.27James, M., "3-D graphics to become accessible to all," Scientific Computing World, Feb. 1997, 41 and 43.28Johnson, S.P., "Direct3D Revealed: Microsoft's 3-D API provides device-independent access to acceleration hardware. Here's how it works," Core Technologies, http:/byte.com/art/9612/sec5/art4.htm. Dec. 1996, 5 pages.29Jones, M. et al., "High-Performance Graphics Via Silicon Compilation," VLSI Systems Design, Mar. 1987, 32, 33, 36 and 38.30Kaya, E.M., "New Trends in Graphic Display System Architecture," in Frontiers in Computer Graphics, Proceedings of Computer Graphics, Tokyo '84, Kunii, T.L. (ed.), 1985, 310-320.31Kumar, S. et al., "Efficient rendering of trimmed NURBS surfaces," Computer-Aided Disign, Jul., 1995, 27(7), 509-521.32Labsik, U. et al., "Progressive transmission of subdivision surfaces," Computational Geometry, 2000, 15, 25-39.33Lachaud, J-O. et al., "Continuous Analogs of Digital Boundaries: A Topological Approach to Iso-Surfaces," Graphical Models, 2000, 62, 129-164.34Lapidous, E. et al., "Optimal Depth Buffer for Low-Cost Graphics Hardware," Trident Microsystems, Inc., 1999, 67-73.35Lastra, A. et al., "Real-Time Programmable Shading," Proceedings: 1995 Symposium on Interative 3D Graphics, Monterey, California, Apr. 9-12, 1995, 59-66.36Lee, J-A. et al., "SPARP: a single pass antialiased rasterization processor," Comput. & Graphics, 2000, 24, 233-243.37Leech, J., "OpenGL Extensions and Restrictions for PixelFlow," The University of North Carolina at Chapel Hill, 1995, I-39.38Lichten, L., "A Solution to Surface Connectivity Problems in Computer-Aided Design," Computer Graphics, Mar. 1981, 14(4), 168-199.39Mabin, F.H. et al., "A Parallel Algorithm to Reconstruct Bounding Surfaces in 3D Images," J. Supercomputing, 1998, 12, 137-155.40McManus, D. et al., "Optimal Static 2-Dimensional Screen Subdivision for Parallel Rasterization Architectures," Comput. & Graphics, 1997, 21(2), 159-169.41Meyers, D. et al., "Surfaces from Contours," ACM Transactions on Graphics, Jul. 1992, 11(3), 228-258.42Micikevicius, P. et al., "Teaching a Computer Graphics Class Using DirectX," J. Comput. in Small Colleges; Proceedings of the Ninth Annual CCSC South Central Conference, (Jackson, Mississippi, Apr. 17-18), Meinke, J.G. (ed.), Mar. 1998, 13(4), 61-66.43Molnar, S. et al., "PixelFlow: High-Speed Rendering Using Image Composition," Computer Graphics' 26(2), 231-240, Jul. 2, 1992.44Molnar, S. et al., "PixelFlow: The Continuing Saga," 1995 Parallel Rendering Symposium, Atlanta, GA, Oct. 30-31, 1995, p. 79.45Molnar, S., "The PixelFlow Texture and Image Subsystem," Computers & Graphics, 1996, 20(4), 491-502.46Nishimura, H., et al., "A Multicomputer System Links: Its Architecture and Graphics Applications," IECON '84: International Conference on Industrial Electronics, Control and Instrumentation, Tokyo, Japan, Oct. 22-26, 1984, 1, 270-274.47NVIDIA Corporation, "System Platform Porcessor (SPP) / Integrated Graphics Processor (IGP): Redefining System and Graphics Performance," nForce SPP/IGP Product Overview, Jan. 2002, Version 1, 2 pages.48NVIDIA Corporation, "Technical Brief: NVIDIA nfiniteFX II Engine From Research to Real Time," Jan. 16, 2002, 7 pages.49NVIDIA Corporation, "Technical Brief: NVIDIA nForce Platform Processing Architecture," 2001, 1-9.50Ohbuchi, R., et al., "Embedding Data in 3D Models," in Interactive Distributed Multimedia Systems and Telecammunication Services, 4th International Workshop, IDMS '97, Darmstadt, Germany, Sep. 10-12, 1997, 1-10.51Ohhashi, M., et al., "A 32b 3-D Graphic Processor Chip with 10M Pixels/s Gouraud Shading," 1988 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 1988, 168-169 and 352.52Olano, M. et al., "A Shading Language on Graphics Hardware: The PixelFlow Shading System," Proceedings of SIGGRAPH 98, Orlando, Florida, Jul. 19-24, 1998, 1-10.53Olano, M. et al., "Procedural Primitives in a High Performance, Hardware Accelerated, Z-Buffer Renderer," UNC Computer Science Technical Report 97-040, Department of Computer Science, University of North Carolina, Chapel Hill, North Carolina, 1997, I-10.54Olano, M., "A Programmable Pipeline for Graphics Hardware," PhD Dissertation, Department of Computer Science, University of North Carolina at Chapel Hill, 1998, 1-168.55Pountain, D., PixelFlow-Scalable Image Processing-It Divides and Conquers Rendering by Drawing the Objects First, Then Combining Them, Byte, 1995, 20(11), 6 pages.56Pountain, D., PixelFlow�Scalable Image Processing�It Divides and Conquers Rendering by Drawing the Objects First, Then Combining Them, Byte, 1995, 20(11), 6 pages.57Proudfoot, K. et al., "A Real-Time Procedural Shading System for Programmable Graphics Hardware," Computer Graphics Proceedings, SIGGRAPH, 2001, 159-170.58Rowlan, J.S., et al., "A distributed, parallel, interactive volume rendering package," IEEE: Proceedings-Visualition '94, Washington, D.C., Oct. 17-21, 1994, 21-30.59Schneider, B-O., et al., "An adaptive framework for 3D graphics over networks," Comput. & Graphics, 1999, 23, 867-874.60Schneider, B-O., et al., "M-Buffer: A Flexible MISD Architecture for Advanced Graphics," Comput. & Graphics, 1995, 19(2), 239-246.61Senthinathan, R., et al., "A 650-MHz, IA-32 Microprocessor with Enhanced Data Streaming for Graphics and Video," IEEE J. Solid-State Circuits, Nov. 1999, 34(11), 1454-1465.62Shinya, M., "Improvements on the Pixel-tracing Filter: Reflection/Refraction, Shadows, and Jittering," Proceedings: Graphics Interface 95, May 7-19, 1995, 92-102.63Shirali, N.S., et al., "A Parallel Architecture Graphics Processor," IEEE Southeastcon: Conference Proceedings, Knoxville, Tennessee, Apr. 11-13, 1998, 108-111.64Slusallek, P. et al., "Implementing RenderMan-Practice, Problems and Enhancements," Eurographics '94, 1994, 13(3), 443-454.65Smith, D.R., et al., "A Circuit-Switched Shared-Memory Multiprocessor," International J. Mini Microcomputers, 1995, 17(3), 108-118.66Sussman, H., et al., "Graphics Memory Architectures," Wescon/.86 Conference Record, 1986, I-6.67Swanson, R.W., et al., "A Fast Shaded-Polygon Rendered," Computer Graphics, Aug. 1986, 20(4), 95-101.68Teonnies, K.D., et al., "Volume rendering for interactive 3-d segmentation," in Image Display, Proceeding of SPIE, Newport Beach, California, Feb. 23-25, 1997, 3031, 602-609.69Thompson, T., "An inside look at the most popular 3-D environments: OpenGL, QuickDraw 3D, and Direct3D," Must-See 3-D Engines, Jun. 1996, http://byte.com/art/9606/sec11/art4.htm, 7 pages.70Thompson, T., "Direct3D's Engine," Must-See 3-D Engines, Jun. 1996, http://byte.com/art/9606/sec11/art7.htm, 1 page.71Thompson, T., "QuickDraw 3D's Command Structure," Must-See 3-D Engines, Jun. 1996, http://byte.com/art/9606/sec11/art6.htm, 1 page.72Thompson, T., "Three Ways to Tackle Multithreading," Must-See 3D Engines, Jun. 1996, http://byte.com/art/9606/sec11/art8.htm, 1 page.73Thompson, T., Open GL's Command Structure: Must-See 3-D Engines, Jun. 1996, http://byte.com/art/9606/sec11/art5.htm, 1 page.74Wilson, J. L., et al., "Designing a Graphics Application Interface," Proceedings Graphics Interface '85, Montreal, Quebec, May 27-31, 1985, 373-380.75Yoshida, M., et al., "Trend of the computer graphics hardware," Information Processing Soc. of Japan, Oct. 1988, 29(10), 1109-1115.76Zheng, Y., et al., "Three-dimensional unstructured mesh generation: Part 2. Surface meshes," Comput. Methods Appl. Mech. Engrg., 1996, 134, 269-284.Classifications U.S. Classification345/522, 345/519, 345/537, 345/426International ClassificationG06T15/00, G06T15/80, G06F13/00, G06T1/00, G06F13/14, G06T15/50Cooperative ClassificationG06T15/80, G06T15/00, G06T15/005, G06T2210/32European ClassificationG06T15/00A, G06T15/80, G06T15/00Legal EventsDateCodeEventDescriptionMar 18, 2013FPAYFee paymentYear of fee payment: 4Jun 26, 2006ASAssignmentOwner name: MICROSOFT CORPORATION, WASHINGTONFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BOYD, CHARLES N.;TOELLE, MICHAEL A.;REEL/FRAME:017844/0944Effective date: 20010227Owner name: MICROSOFT CORPORATION,WASHINGTONFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BOYD, CHARLES N.;TOELLE, MICHAEL A.;US-ASSIGNMENT DATABASE UPDATED:20100209;REEL/FRAME:17844/944RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google