Source: http://www.google.es/patents/US4926247?dq=flatulence
Timestamp: 2013-05-19 23:04:24
Document Index: 175155925

Matched Legal Cases: ['art 175', 'art) 174', 'art 174', 'art 175', 'art 175', 'art 175', 'art 174', 'art 174']

Patente US4926247 - Color imaging apparatus including a means for electronically non-linearly ... - Google PatentesB�squeda Im�genes Maps Play YouTube Noticias Gmail Drive M�s » B�squeda avanzada de patentes | Historial web | Iniciar sesi�n B�squeda avanzada de patentesPatentesA color imaging apparatus includes means for electronically non-linearly expanding or compressing the dynamic range of an image signal output therefrom. Separate output signals of respective brightness for different colors are logarithmically compressed, inverse-logarithmically converted, then linear-matrix-converted...http://www.google.es/patents/US4926247?utm_source=gb-gplus-sharePatente US4926247 - Color imaging apparatus including a means for electronically non-linearly expanding and compressing dynamic range of an image signal N�mero de publicaci�nUS4926247 ATipo de publicaci�nConcesi�n N�mero de solicitud07/108,516 Fecha de publicaci�n15 May 1990 Fecha de presentaci�n14 Oct 1987 Fecha de prioridad15 Oct 1986 InventoresHiroyoshi FujimoriTatsuo NagasakiHidetoshi Yamada Cesionario originalOlympus Optical Co., Ltd. Clasificaci�n de EE.UU.348/262257/291386/E09.26257/258348/E09.53257/232348/E09.35 Clasificaci�n internacionalH04N9/82H04N9/77H04N9/68 Clasificaci�n cooperativaH04N9/68H04N9/82H04N9/77H04N2005/2255 Clasificaci�n europeaH04N9/68H04N9/77H04N9/82ReferenciasCitas de patentes (20)Otras citas (2) Citada por (56)Enlaces externosUSPTO Cesi�n de USPTO EspacenetColor imaging apparatus including a means for electronically non-linearly expanding and compressing dynamic range of an image signalUS 4926247 A Resumen A color imaging apparatus includes means for electronically non-linearly expanding or compressing the dynamic range of an image signal output therefrom. Separate output signals of respective brightness for different colors are logarithmically compressed, inverse-logarithmically converted, then linear-matrix-converted and multipled by a compression factor of brightness level for the respective color signals to produce a logarithmically compressed color signal without varying the tone.
What is claimed is: 1. A logarithmic color imaging apparatus comprising: an imaging device for converting a light image of an object to at least one electric output signal; a color separating means for separating each output signal of said imaging device into separate output signals for different primary colors or auxiliary colors; a first logarithmic compressing means for logarithmically compressing the output signals of said color separating means for the different primary colors or auxiliary colors; an inverse-logarithmic converting means for inverse-logrithmically converting output signals of said first logarithmic compressing means; a matrix-converting means for linear-matrix-converting output signals of said inverse-logarithmic converting means; a second logarithmic compressing means for logarithmically compressing output signals of said matrix-converting means; and a color signal compounding means for producing a logarithmically compressed brightness signal from output signals of said second logarithmic compressing means.
7. A logarithmic color imaging apparatus comprising: a field sequential type illuminating means for sequentially illuminating an object with light of a plurality of different colors; an imaging device for converting a light image of said object to at least one electric output signal in coordination with said field sequential type illuminating means; a memory means for switching each signal of said imaging device in synchronism with said field sequential type illuminating means to produce separate output signals for the different colors and memorizing the same; a first logarithmic compressing means for logarithmically compressing output signals of said memory means; an inverse-logarithmic converting means for inverse-logarithmically converting output signals of said first logarithmic compressing means; a matrix-converting means for linear-matrix-converting output signals of said inverse-logarithmic converting means; a second logarithmic compressing means for logarithmically compressing output signals of said matrix-converting means; and a color signal compounding means for producing a logarithmically compressed brightness signal from output signals of said second logarithmic compressing means.
20. A logarithmically compressed color signal processing apparatus comprising: a first logarithmic compressing means for logarithmically compressing input color signals for respective primary colors or auxiliary colors; an inverse-logarithmic converting means for inverse-logarithmically converting output signals of said first logarithmic compressing means; a matrix-converting means for linear-matrix-converting output signals of said inverse-logarithmic converting means; a second logarithmic compressing means for logarithmically compressing output signals of said matrix-converting means; and a color signal compounding means for producing a logarithmically compressed brightness signal from output signals of said second logarithmic compressing means.
21. An electronic camera reproducer comprising: a first logarithmic compressing means for logarithmically compressing signals for respective primary colors of a video signal recorded in a recording medium; an inverse-logarithmic converting means for inverse-logarithmically converting output signals of said first logarithmic compressing means; a matrix-converting means for linear-matrix-converting output signals of said inverse-logarithmic converting means; a second logarithmic compressing means for logarithmically compressing output signals of said matrix-converting circuit; and a color signal compounding means for compounding output signals of said second logarithmic compressing circuit and output signals of said first logarithmic compressing circuit.
The respective outputs of the window circuits 36, 37 and 38 shown in FIG. 3 are input into the inverse-logarithmic amplifiers 41, 42 and 43 having a dynamic range of 50 dB, are converted to be of linear values for the inputs and are then input into a matrix-converting circuit 44. The output of the matrix-converting circuit 44 is represented by the formulae: ##EQU1## Here, log.sup.-1 is a range of 50 dB. That is to say ##EQU2## wherein M is (R outputs of this matrix-converting circuit 44 are again input into logarithmic amplifiers 45, 46 and 47 of 50 dB, are logarithmically compressed and then have the above mentioned average value log M added by adders 48, 49 and 50. Thereby, log Y, log (R-Y) and log (B-Y) having a dynamic range of 100 dB can be compounded. Thereafter, log Y has the gain adjusted and the automatic gain controlled by an adder 51 and has the dynamic range adjusted by a multiplier 52 to be given a coefficient S. In this respect, the technical means disclosed in the above mentioned gazette of Japanese patent laid open No. 52171/1985 is used.
log Y/Y
log R&#947;=&#947;
log G&#947;=
log B&#947;=
Now, as usually γ&lt;1, the γ-correcting circuit can be simply formed of subtracters by the resistance division respectively using resistances R1 and R2 as shown by 72, 73 and 74 in FIG. 10. However, so that the maximum amplitude value (saturation value) after the γ-correction may coincide with that before the correction as shown in FIG. 12, the reference voltage V.sub.R of the attenuation is set to be equal to the maximum amplitude value (saturation value) before the correction. Then, the γ-corrected signals log R.sup.γ, log G.sup.γ and log B.sup.γ are input into the average value operating circuit 40 having three input terminals and are input respectively into the subtracters 33, 34 and 35 and adders 75, 76 and 77. The operations of the average value operating circuit 40, subtracters 33, 34 and 35, window circuits 36, 37 and 38, inverse logarithmic amplifiers 41, 42 and 43, matrix circuit 78, logarithmic amplifier 45 and adder 48 are the same as in the above described first embodiment. The matrix circuit 78 is to make only the Y signal. The log Y (having a dynamic range of 100 dB) which is an output of the adder 48 has then the gain or automatic gain adjusted by the adder 79 and has the dynamic range or automatic dynamic range adjusted by a multiplier 80. If the gain adjusting voltage applied to the adder is represented by log b and the dynamic range adjusting voltage applied to the multiplier is represented by a, the output of the multiplier 80 will be a log (b Y). Switching switches 81 and 82 are to switch and select the automatic control and manual control respectively of the gain adjustment and dynamic range adjustment.
Now, in the above mentioned first embodiment, by multiplying the color signal R-Y and B-Y by the compressed degree log Y/Y of the brightness signal Y, only the brightness signal Y is compressed without influencing the hue and colored degree. In this respect, even if R, G and B are multiplied by the compressed degree log Y/Y of the brightness signal Y so as to be respectively log Y/Y Y/Y fact that, when log Y, log Y /Y (R-Y) and log Y/Y (B-Y) are passed through an inverse matrix circuit, they will become respectively log Y /Y this embodiment, the output of the multiplier 80, that is, a log (bY) is once compressed by a logarithmic amplifier 92 of 100 dB so as to be in the form of log (a log b Y). Then, by subtracting the output log Y of the adder 48 from this signal, a signal of log (a log bY/Y) is obtained. When the output of this subtracter 88 is added to log R, log G and log B respectively by the adders 75, 76 and 77, log (a log b Y/Y log (a log bY/Y Then, a log bY/Y bY/Y amplifiers 89, 90 and 91 of 100 dB and, as a result, only the brightness signal can be compressed without influencing the hue and colored degree. Here, the feature of the second embodiment as compared with the above mentioned first embodiment shall be described. In the first embodiment, as the color signals R-Y and B-Y have positive and negative amplitudes, the logarithmic amplifiers 46 and 47, adders 45 and 50, subtracters 53 and 54 and inverse-logarithmic amplifiers 55 and 56 must respectively calculate the signals as divided into positive and negative signals and the circuit is somewhat complicate, because the inverse-logarithm of the logarithm can take only a positive value mathematically. Now, in this second embodiment, as the process is made by only the signals R, G and B taking only positive values, the circuit is simple.
The log Y signal is subtracted from the Y' signal having passed through the logarithmic amplifier 125 by a subtracter 133 to obtain log (Y'/Y). This signal is added to log Mg, log G, log Cy and log Ye respectively by adders 134 to 137 to be signals obtained by multiplying the respective auxiliary color signals by Y'/Y. Then, four linear signals Mg G inverse-logarithmic amplifiers 138 to 141 and are applied to adders and subtracters 142 and 143 of four inputs to obtain visually corrected color difference signals (R-Y)' and (B-Y)'.
In the above mentioned IL-CCD 145, vertical shift registers 147 are arranged alternately with light receiving element rows in the vertical direction and a transfer gate signal φ.sub.TG is applied to transfer gates 148 arranged between the light receiving element rows 146 and vertical shift register 147 so that the signal charge accumulated in the adjacent light receiving element rows 146 may be transferred to the respective vertical shift registers 147. By applying the vertical transfer clock φ.sub.v to the vertical shift registers 147, the signal charge can be transferred in the vertical direction to a horizontal shift register 149. By applying the horizontal shift clock φ.sub.H for the number of picture elements in the horizontal direction to this horizontal shift register 149, a CCD output signal can be output through an output amplifier 150. By the way, the overflow drains 144 formed adjacently to the respective light receiving element rows usually have a positive voltage applied at a proper value (in the case of n channels) and have the electric charge accumulated in excess by the light receiving elements overflowed. In this embodiment, the voltage applied to these overflow drains 144 is controlled to make the output characteristic a logarithmic characteristic. By the way, the drains are earthed through a resistance R.
=A log{dV(t)/dt
p(t.sub.1)=dV(t.sub.1)/dt =V(t.sub.1)}. . .                                         (2)
Q(T)=dV(t.sub.1)/dt
P(T)=dV(t.sub.1)/dt -V(t.sub.1)}. . .                                         (4)
(that is, equivalent to shifting the ordinate of the photoelectric conversion characteristic of the device by 1 rightward.) Also, to vary the gain is to enable T to be varied. For example, T may be multiplied by B and T in the formulae (3) and (4) may be replaced with B
On the actual circuit, in case a dynamic range, for example, of 100 dB is to be compressed, the constant A is so determined that the accumulated amount of such noise charge as, for example, a dark current at t=T may be, for example, 1/10.sup.5 of the maximum saturated level E max of the device and the gain B is so determined that the light signal of 100 dB may be E max.
In the above mentioned IL-CCD 145, the depth of the potential well is varied by a method wherein the OFD gate voltage is continuously varied according to the above mentioned formula (1) from the level V.sub.2 on which the barrier of the OFD gate becomes lowest and all the electric charge accumulated in the light receiving area is made to flow to the OFD to the level V.sub.0 on which the barrier of the OFD gate becomes highest.
However, in fact, as the electric charge is negative, the voltage applied to the OFD gate reverses the polarity of the above mentioned formula (1), becomes a decreasing function decreasing V.sub.2 and is as shown by the broken line in FIG. 22. By the way, the abscissa represents the time t and T is, for example, 1/30 sec. or 1/60 sec.
First of all, a fundamental system in which the gain and dynamic range are fixed shall be explained with the flow represented by the broken line in FIG. 23. A saw tooth-like wave S.sub.1 shown in FIG. 24 (a) is output from a saw tooth-like wave generating circuit 152 in which the phase is synchronized by a timing signal output from a system controller 151. This saw tooth-like wave S.sub.1 is of a frequency of 60 Hz (when the field is read out) or 30 Hz (when the frame is read out) and a voltage, for example, of V.sub.1. However, the length part of the upper side produced when the saw tooth-like wave S.sub.1 is limited by a voltage level V.sub.2 lower than this peak voltage V.sub.1 is so set as to correspond to a vertical blanking. This saw tooth-like wave S.sub.1 is input into a function generating circuit 153 and a reverse output S.sub.3 of a function curve V(t) according to the above mentioned formula (1) is produced. This output S.sub.3 is of a waveform shown in FIG. 24(c) in which the signal S.sub.2 before being reversed shown in FIG. 24(b) is reversed. That is to say, this signal S.sub.3 is of a voltage level V.sub.2 when t=0 and is of a waveform clamped by V.sub.0. By the way, by considering the γ characteristic of the imaging device in the characteristic of this function generating circuit 153, the value of A in the formula (1) is made to have a characteristic obtained by correcting the γ characteristic and γ can be corrected within the device. For example, by making a control signal S.sub.3 ' shown by the solid line from the control signal S.sub.3 shown by the broken line in FIG. 22, a signal having had γ corrected can be output. When γ is thus corrected within the device, the γ-correcting circuit provided in the video signal processing part will become unnecessary and the circuit can be simplified. (In this case, the broken line parts B in FIGS. 25 and 43 will become unnecessary.)
The above mentioned gain control can be made by controlling the exposure time and B in the formula (1) may be made variable. In the control circuit for this gain control, as shown in FIG. 23, the output signal S.sub.1 of the saw tooth-like wave generating circuit 152 is input into a limiter 154, is limited by the voltage level V.sub.2, is then input into a subtracter 155 and is subtracted from the voltage V.sub.2. This subtraction output is input into a multiplier 156, is multiplied by a gain controlling signal S.sub.4, is again input into a limiter 157, is limited with the voltage V.sub.2, is input into a subtracter 158 and is subtracted from the voltage V.sub.2. The output signal S.sub.1 ' of this subtracter 158 is input into a function generating circuit 153. At this time, the gain controlling signal S.sub.4 is a log Y signal from a color logarithmically imaging signal processing part (See FIG. 25.) in the later step. An integrated value for one field (or for one frame) is determined by passing this log Y signal through LPF 161 and is input into the other input terminal of a comparing amplifier 163 in which a voltage set on a proper level by a variable resistance 162 is applied to one input terminal and the compared amplified output signal S.sub.4 is input into the multiplier 156 through a switching switch 164, is multiplied and is controlled by AGC. When the imager switches this switching switch 164, the gain can be controlled manually by multiplying the voltage set at any value by the variable resistance 165.
First of all, the same as the gain controlling signal S.sub.4, the log Y signal passed through the LPF 161 and the log Y signal before being passed through this LPF 161 are input into a standard deviation producing circuit represented by the reference numeral 100 in FIG. 10 (or 100' in FIG. 11) to obtain a signal output from this circuit 100.
This signal is applied to the other input terminal of a comparing amplifier 167 (which is provided independently of the gain control and in which a variable resistance 166 capable of being set on a proper level is applied to one input terminal and the compared output which has been passed through this comparing amplifier 167 and which is a dynamic range controlling signal S.sub.5 passed through a switching switch 168 is input into the function generating circuit 153 to control the dynamic range by ADC. Also, instead of controlling it by ADC, the imager may switch the switching switch 168 to the manual side and may manually control it with a value set freely by a variable resistance 169. Here, the signal S.sub.5 corresponds to A of the formula (1).
Therefore, the dynamic range controlling signal S.sub.5 is used. First, 1/S.sub.5 is made by a divider 171 for the inverse-logarithmic amplifiers 41 to 43 and 89 to 91 and the characteristics of the inverse-logarithmic amplifiers 41 to 43 and 89 to 91 are controlled by using this signal 1/S.sub.5 to make the correction.
The color signals MR, MG, MB passed through the above mentioned inverse-logarithmic amplifiers 41 to 43 have the brightness signal MY produced by the matrix circuit 78 and are input into the logarithmic amplifier 45. By the way, in the case of correcting γ characteristic within the device, that is, in the case of using S.sub.3 ' instead of the signal S.sub.3, the broken line B will be unnecessary.
In FIG. 26, the FT-CCD 173 is provided with a transferring part 175 adjacently to the light receiving part (or accumulating part) 174 and, in an ordinary using method, the signal charge accumulated in the light receiving part 174 is transferred to the transferring part 175 by the application of a high speed vertical transferring signal CK.sub.1. After the charge is transferred to this transferring part 175, a part of it is transferred in the vertical direction by a vertical transferring clock φV.sub.2 shown in FIG. 27(i c), then it is repeated to apply a horizontal shifting clock φH (See FIG. 27(d).) of the number of picture elements in the horizontal direction to the horizontal shift register 176 and a CCD signal is output through the output amplifier.
Now, in this embodiment, before the above mentioned vertical transferring clock CK.sub.1 is applied, an accumulated potential controlling signal S.sub.6 is applied as shown in FIG. 27(b) to be made an electric charge signal of a logarithmic compression characteristic and then the high speed transferring clock CK.sub.1 is applied as described above and is transferred to the transferring part 175. That is to say, in this embodiment, the accumulated potential controlling signal S.sub.6 and vertical transferring clock CK.sub.1 are applied to the light receiving part 174 and are combined to be represented by a control signal φV.sub.1.
As shown in FIG. 26, the above mentioned control signal φV.sub.1 obtained by subtracting (however, in the case of applying it to the IL-CCD, it is not necessary to subtract the CCD driving signal CK.sub.1) the CCD driving vertical transfer signal CK.sub.1 from the signal S.sub.6 (See FIG. 27(b).) provided by subtracting the signal S3 (See FIG. 27(a).) from the voltage V.sub.2 by the subtracter 177 is applied to the accumulating gate of the light receiving part 174. In this case, instead of subtracting the signal S3 from the voltage V.sub.2, the signal (shown in FIG. 24(b) before being reversed within the function generating circuit 153 shown in FIG. 23 may be added to V.sub.2.
Also, φV.sub.1 has been converted to a proper level when output from the subtracter 177.
FIG. 28 shows how the above mentioned control signal φV.sub.1 is produced. That is to say, the signal CK.sub.1 shown in FIG. 28(a) is subtracted from the signal S.sub.6 shown in FIG. 28(b) and produced by subtracting the signal S.sub.3 from the voltage V.sub.2 by the subtracter 177 to produce the signal φV.sub.1.
In this logarithmically compressed IL-CCD 178 within the device, a positive voltage V.sub.0 is applied to the OFD gate of the IL-CCD and, in case the signal charge accumulated in the light receiving part becomes in excess, it will be made to flow to the OFD gate side (when above the voltage V.sub.2 level). In the ordinary using method, the signal charge accumulated in the light receiving part is transferred to the vertical shift registers by the application of the transfer gate clock φ.sub.TG and, except at the transferring time, is prevented from leaking to the vertical shift register side. However, in this embodiment, the logarithmically compressed characteristic is made by applying such control signal as leaks a part to the vertical shift register side at the time of accumulating the electric charge.
Therefore, the control signal S.sub.3 shown in FIG. 30(a) and the transfer gate signal φ.sub.TG shown in FIG. 30(b) are added by the adder 179 and such logarithmic compression controlling signal φ.sub.TG ' as is shown in FIG.(c) is produced and is applied to the transfer gate terminal. By the way, the above mentioned transfer gate signal φ.sub.TG is output from a system controller.
The V.sub.TG ' has been converted to a proper level when it is output from the adder 179.
The control signal S.sub.3 shown in FIG. 30(a) is applied at the time of accumulating the electric charge (exposure time) and the electric charge part leaking to the vertical shift register side due to this control signal S.sub.3 is swept out by the vertical transfer clock φV.sub.1 shown in FIG. 30(d). Therefore, it is preferable to give this vertical transfer clock φV.sub.1 the maximum clock velocity within the allowable range of the imaging device. On the other hand, the signal charge transferred to the vertical shift register by the transfer gate signal φ.sub.TG output after one exposure time is logarithmically compressed through the output amplifier by the vertical transfer clock φV.sub.2 and horizontal shift register clock φH shown in FIGS. 30(d) and (e) to output a logarithmically compressed CCD signal. In this case, the clock φV.sub.2 and clock φH are output as synchronized with each other. (However, φV.sub.2 and φH are applied as displaced from each other by 1/2 in the phase.)
In the control signal generating circuit in the eighth embodiment, as shown in FIG. 31, the output signal of a system controller 151 is applied to the address terminal of a look-up table (such as a ROM table) 180, the read-out data are converted to an analogue signal by a D/A converter 181 and this analogue signal is passed through an LPF 182 having a proper cut-off characteristic to be smoothed to produce a control signal S.sub.3. The signal input into the above mentioned D/A converter 181 is a fine step-like signal shown by the solid line in FIG. 32 and is converted to an analogue signal by the D/A converter. The signal passed through the LPF 182 is a control signal S3 shown by the broken line in the same FIG. 32.
In the above mentioned eighth embodiment, the gain is controlled by varying the clock velocity in response to the above mentioned signal S.sub.4 in the system controller 151 and the dynamic range is controlled the same by controlling the address to the look-up table 180 in response to the above mentioned signal S.sub.5 and reading out the information of the corresponding curve.
As shown in FIG. 34(a), just after the respective exposure times t.sub.1, t.sub.2, . . . the transfer gate clock φ.sub.TG is applied, the signal charge accumulated during the respective exposure times is transferred to the vertical shift registers and is added by the shift registers. (Explained as applied to the IL-CCD in FIG. 18.) Just after the addition of the signal charge for the exposure time of N times, as shown in FIGS. 34(b) and (c), the vertical transfer clock φV and the horizontal shift register clock φH are applied to output a CCD signal from the output terminal.
Now, the unnecessary signal charge accumulated in the light receiving part while the CCD signal is being output the same as in ordinary reading out after N transfer gate clocks φ.sub.TG are applied is swept out by applying one of the transfer gate clocks (shown by φ in FIG. 34(a)) and then applying the vertical transfer clock φV.sub.2 for the number of the picture elements in the vertical direction as shown in FIG. 34(b) (then applying clocks for the number of the horizontal picture elements not illustrated to the horizontal shift register). By the way, the voltage V.sub.1 in which the gate height is 1/N (here, for example, 1/5) for the voltage V.sub.0 when the gate height is 1 is applied to the OFD gate as shown in FIG. 34 (d).
In FIG. 37, φS represents a pulse output from the horizontal scanning circuit 192. φ.sub.G1, φ.sub.G2, φ.sub.Gn represent pulses output from the vertical scanning circuit 191. φ.sub.RS represents a pulse to be applied to the resetting circuit 193.
In the respective pulses φ.sub.G1, φ.sub.G2, . . . , φ.sub.Gn, the voltage V.sub.RD is a voltage for reading out the corresponding line 189-i. The timing to which this voltage V.sub.RD is applied is given by the vertical shift register 194. The voltage V.sub.OF is a voltage applied every horizontal blanking period and given by the analogue shift register 195. The signal mixing circuit 196 mixes the outputs of the vertical shift register 194 and analogue shift register 195 at a proper timing and produces pulses φ.sub.G1, φ.sub.G2, . . . In the horizontal scanning circuit 192, as the horizontal shift register 197 Operates every horizontal scanning period, the horizontal selecting switches 198, . . . , 198 open successively and the signals of the columns 190-1, 190-2 and 190-n are read out successively by the video line 199. In the resetting circuit 193, the resetting switch 200 opens as synchronized with the pulse V.sub.Rs every horizontal blanking period. Now, the picture element 183 connected to the line 189-1 shall be considered. When the pulse φ.sub.G1 becomes V.sub.RD, the signals of the respective picture elements 183 will be read out successively by the operation of the horizontal scanning circuit 192. During the succeeding horizontal blanking period, V.sub.OF will be applied at a value high enough to perfectly reset the respective picture elements 183 and, by the opening of the resetting switch 200, the picture element 183 will be reset and the gate of the picture element 183 will be of a low value as of the time of starting the integration. During the next horizontal blanking period after one horizontal scanning period, V.sub.OF will be of a rather low value. On the other hand, the gate potential of each picture element will have risen in response to the incident light amount. The gate potential will be clipped for the picture element 183 whose light amount has been large and the potential of the picture element of a small light amount will be kept unclipped as it is. Therefore, only the signal of the picture element 183 whose light amount has been large will be compressed. Even during the next blanking period, this signal compressing operation will be made again. The level of the compression is determined by the voltage V.sub.OF. Then, in the same manner, the signal will be compressed every horizontal blanking period. After one vertical scanning period φ.sub.G1 will become V.sub.RD again and thereby the compressed signal will be read out. Here, if the voltage of V.sub.OF is varied according to the formula (1) as shown by φ.sub.A in FIG. 38, a logarithmically compressed signal output will be obtained.
A signal φ.sub.G delayed by the timing of reading out the picture element 183 by the operation of the vertical scanning circuit 191 is applied to the picture element 183 connected to the other line 189-i (i≠1). (This delay is given by the vertical shift register 194 on the read-out voltage V.sub.RD and by the analogue shift register 195 on the voltage V.sub.OF.) Therefore, the operation of the respective picture elements 183 will be exactly the same as in the line 189-1 and the logarithmically compressed signals will be obtained from all the picture elements.
The degree of the signal compression can be freely set by varying the pulse φ.sub.A as a logarithmic compression controlling signal input into the analogue shift register 195. If this pulse φ.sub.A is normally made 0 volt, an uncompressed linear type output characteristic will be obtained. Also, if this pulse φ.sub.A is switched to a high voltage and low voltage, a characteristic represented by two curved lines Will be obtained. Also, in the case of conforming to the function of the formula (1), by adjusting the amplitude, gradient and the like, the dynamic range of the logarithmic compression can be varied. Therefore, the above described ACC and ADC can be controlled by the pulse φ.sub.A.
By the way, for example, a BBD (Bucket Brigade Device) can be used for the analogue shift register 195 to be used in the vertical scanning circuit 191. This BBD is of MOS transistors Q.sub.1 and capacitors C.sub.1 connected in many steps as shown in FIG. 39(a) and has such structure as is shown in FIG. 39(b). If the BBD is used, the analogue shift register 195 can be formed of a simple circuit.
FIG. 40 shows a formation of one picture element of a CMD, FIG. 40(a) shows a structure and FIG. 40(b) shows an equivalent circuit. Normally, a negative voltage is applied to a gate 201. When a light is incident, holes will be accumulated below the gate 201 and the potential will rise. When a voltage (negative voltage) higher than at the time of the light accumulation is applied to the gate 201 to read out a signal, a current between a source 202 and drain will flow in response to the light amount and the signal of the picture element will be read out. If a positive voltage is applied to the gate 201, the holes below the gate 201 will vanish and the gate 201 will be reset. The formation of the entire imaging device is to replace the picture element 183 in FIG. 36 with the CMD picture element shown in FIG. 40. The resetting circuit is unnecessary. The signal waveforms showing the operation timing are the same as in FIG. 37. The voltage of the gate pulses φ.sub.G1, φ.sub.G2, . . . , φ.sub.Gn may be only varied so as to be adapted to the CMD.
The voltage V.sub.OF applied to the resetting line 210 is set at 0 V at the time of reading out a signal. After the signal is read out, when a high voltage is applied, in each picture element, the photodiode 205 will be reset through the diode 208. Thereafter, if V.sub.OF is reduced, the light signal will be retained as it is for the picture element of a small light amount but the voltage will be clipped and therefore the signal will be compressed in the picture element of a large light amount. By varying V.sub.OF according to the formula (1), a logarithmically compressed signal can be obtained.
A logarithmically compressed color imaging apparatus can be realized as in FIG. 25 by using such devices realizing the logarithmically compressed characteristic. On the other hand, when an electric automatic gain controlling circuit and automatic dynamic range controlling circuit are combined in series with a log Y signal for making a device interior automatic gain controlling signal S.sub.4 and automatic dynamic range controlling signal S.sub.5 by using the devices of these embodiment and the output is used as a displaying log Y signal, the dynamic range can be extended, on the contrary, for an imaged object of a narrow dynamic range.
FIG. 45(a) is a diagram showing the sectioned structures of the photodiode, vertical shift register and overflow drain and FIG. 45(b) shows a potential distribution. FIG. 46 shows a pulse φ.sub.TG applied to the transfer gate. The pulse φ.sub.TG is a pulse reducing with an upward convex curve from a positive level Va on which the photodiode charge is all transferred to the vertical shift registers. If this curve is represented by V(t), in order to obtain an output of a perfect exponential characteristic, V(t) will be given to satisfy the following formula for the time t:
By applying the pulse φ.sub.TG of the curve V(t) shown in FIG. 46 and satisfying the above mentioned formula (8) to the transfer gate 226 during the light accumulating period, the output of the exponential characteristic can be obtained.
When a photoelectric charge is accumulated while applying the pulse φ.sub.TG of the curve shown in the above mentioned FIG. 46, the potential barrier between the photodiode and vertical shift register will be so low at the beginning of the accumulation that the electric charge will accumulated as divided to both (FIG. 47 (a)) but the barrier will become higher with the lapse of time and the electric charge will be accumulated only in the photodiode (FIG. 47 (b)). In this case, the weaker the incident light amount, the earlier the time when the electric charge becomes unable to pass over the barrier. Therefore, with the electric charge accumulated in the vertical shift register, the weaker the incident light amount, the shorter the accumulating time and the stronger the incident light amount, the longer the accumulating time. As a result, an exponential functional incident light strength versus output characteristic shown in FIG. 48 is obtained. In this case, if the saturated charge amounts of the photodiode and vertical shift register are equal to each other, the gradient of the tangent near the saturation of the output signal will be twice as large and the logarithmically converted signal will have a gain twice as large. In order to further increase this magnification, it is necessary to increase the saturated charge amount of the photodiode. That is to say, in order to makes the magnification N times as high, the saturated charge amount of the photodiode must be made (N-1) times as large. Therefore, the dimension of the photodiode part must be increased or the applied voltage must be increased. However, there are difficulties that, in the former, the device dimension increased and, in the latter, there is a restriction from the voltage resistance.
FIG. 49 shows a pulse φ.sub.TG to be applied to a transfer gate and a pulse φ.sub.OFDG to be applied to an OFD gate. The pulse φ.sub.TG reduces according to the formula (8) from Va. When it reaches OV, the voltage will be made high by Va. The pulse φ.sub.TG continues to continuously vary according to the formula (8). On the other hand, just before φ.sub.TG reaches OV, the positive pulse φ.sub.OFDG is added. This variation is repeated a proper number of times.
In case this pulse φ.sub.OFDG is applied, the operation from the beginning of the light accumulation is the same as in the above mentioned embodiment. When the pulse of φ.sub.OFDG is applied at the moment when the electric charge of the photodiode reaches the saturation, the electric charge of the photodiode will be discharged into the overflow drain as shown in FIG. 50(a). Just after this, the potential barrier between the photodiode and vertical shift register will become lower and the light accumulation will be resumed as shown in FIG. 50(b). When the potential barrier becomes higher with the time, only the electric charge of the picture element of a strong light amount will be accumulated in the vertical shift register as shown in FIG. 50(c). When this operation is repeated, the input versus output characteristic shown in FIG. 51 will be obtained. In case the electric charge is discharged n times in the course of the accumulation, the gradient near the saturation will become (n+2) times as large. As shown in FIG. 49, in case the charge is discharged twice in the course, the gain will become four times as large.
The above embodiments have been of the case that the photodiode is formed of a diffusing layer. The fourteenth embodiment of the present invention wherein the photodiode is formed of an MOS photodiode using an MOS gate is shown in the following. FIG. 53 is a view showing the sectioned structure of the vicinity of a photodiode and the potential distribution. The reference numeral 244 represents a gate (PD gate) on the photodiode, 245 represents a vertical shift register gate and 246 represents an overflow drain. FIG. 54 shows a pulse φ.sub.PDG to be applied to the PD gate. φ.sub.PDG represents a pulse increasing from the 0 level according to the formula (8).
On the other hand, the fifteenth embodiment of the present invention in the case of such field sequential imaging system (as RGB) for a monochromatic imaging device provided with no color filter array shall be explained. In the case of the field sequential imaging system, the illuminating light is varied successively so that the exposure amount (or the radiated light amount, that is, (light intensity) example, of 1:300 (when the dynamic range of the device unit is 50 dB) for the respective illuminating lights.
Therefore, a logarithmic compression controlling signal S.sub.3 is applied, for example, to the overflow drain gate of this CCD 450 from a control signal generating circuit 466 (shown, for example, in FIG. 23) at the time of receiving each field sequential light and a logarithmically compressed signal is output from this CCD 450.
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