Source: http://www.google.com/patents/US6104753?dq=4316055
Timestamp: 2013-12-12 15:48:50
Document Index: 351233755

Matched Legal Cases: ['art. 33', 'art 30', 'art 31', 'art 30', 'art 32', 'art 35', 'art 34', 'art 33', 'art 32', 'art 35', 'art 33', 'art 33', 'art 38', 'art 39', 'art 38', 'art 34', 'art 30', 'art 31', 'art 30', 'art 31', 'art 32', 'art 32', 'art 32', 'art 32', 'art 31', 'art 32', 'art 31', 'art 30', 'art 32', 'art 34', 'art 35', 'art 34', 'art 35', 'art 33', 'art 33', 'art 32', 'art 35', 'art 33', 'art 33', 'art 39', 'art 38', 'art 38', 'art 39', 'art 38', 'art 55', 'art 56', 'art 55', 'art 57', 'art 60', 'art 61', 'art 60', 'art 58', 'art 57', 'art 61', 'art 58', 'art 58', 'art 60', 'art 55', 'art 55', 'art 56', 'art 55', 'art 56', 'art 57', 'art 57', 'art 57', 'art 60', 'art 61', 'art 58', 'art 58', 'art 57', 'art 61', 'art 58', 'art 18', 'art 12', 'art 12', 'art 14', 'art 13', 'art 18', 'art 14', 'art 14', 'art 18', 'art 14', 'art 21', 'art 22', 'art 21', 'art 27', 'art 21', 'art 21', 'art 22', 'art 21', 'art 21', 'art 22', 'art 22', 'art 27', 'art 22', 'art 23', 'art 27', 'art 23', 'art 23', 'art 27']

Patent US6104753 - Device and method for decoding HDTV video - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsHDTV video decoder circuit is disclosed, which has an 1/4 size frame memory for a progressive scanned or interlace scanned video and yet can conduct IDCT and motion compensation to fit to the reduced frame memory size, which, in comparison to a conventional MPEG-2 video decoder which uses a 4 scanned...http://www.google.com/patents/US6104753?utm_source=gb-gplus-sharePatent US6104753 - Device and method for decoding HDTV videoPublication numberUS6104753 APublication typeGrantApplication numberUS 08/792,806Publication dateAug 15, 2000Filing dateFeb 3, 1997Priority dateFeb 3, 1996Fee statusPaidPublication number08792806, 792806, US 6104753 A, US 6104753A, US-A-6104753, US6104753 A, US6104753AInventorsJin-Gyeong Kim, Hwa-Young LyuOriginal AssigneeLg Electronics Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (13), Referenced by (48), Classifications (45), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetDevice and method for decoding HDTV videoUS 6104753 AAbstract HDTV video decoder circuit is disclosed, which has an 1/4 size frame memory for a progressive scanned or interlace scanned video and yet can conduct IDCT and motion compensation to fit to the reduced frame memory size, which, in comparison to a conventional MPEG-2 video decoder which uses a 4 scanned image into frame picture only to lose field information of the image resulting in a significant damage to the picture quality, facilitates to maintain the field information as it was resulting in an improvement in the picture quality.
What is claimed is: 1. A device for decoding an HDTV video comprising:horizontal decimating means for analyzing a motion vector and a coded structure of an image from a received video signal and for decimating the video signal in a horizontal direction; decompression means for inverse quantizing the data received from the horizontal decimating means and for conducting 8 quantized data; vertical decimating means for receiving the analyzed coded structure of the image and for decimating the data processed by decompression means in a vertical direction according to the analyzed coded structure of the image; means for receiving the motion vector and correcting the received motion vector based on the analyzed coded structure of the image; and restoring means for conducting a motion compensation of the horizontally and vertically decimated image using the corrected motion vector to restore an original image. 2. An HDTV video decoder circuit comprising:a VLD/demultiplexer for conducting a variable length decoding of a received bit stream to separate motion vectors, quantizing values, and 8 DCT coefficients; an 8 from the quantizing values and the 8 from the VLD/demultiplexer; an inverse quantizing part for quantizing the 8 from the zonal filter according to the quantizing values; an IDCT part for conducting an 8 from the inverse quantizing part to restore a video signal; an adaptive vertical decimating part for decimating an odd field of an interlace scanned image signal with the odd field matched to a display line position to produce 4 decimation of the IDC transformed 8 according to a DCT type and a progressive.sub.-- frame value; a motion vector correcting part for correcting the motion vector from the VLD/demultiplexer according to the motion vector value and progressive.sub.-- frame value; a motion compensating part for conducting a motion compensation of 8 motion vector corrected in the motion vector correcting part; an adding part for adding the 8 from the adaptive vertical decimating part and the 8 macro blocks motion compensated in the motion compensating part to restore 8 a frame memory for converting the video signal decimated by 1/2 in horizontal and vertical directions respectively in the adding part into a frame unit video signal according to B, I, P picture types and storing therein; and, a multiplexer for selecting an output from the adding part if it is a B picture, and selecting the video signal from the frame memory if it is I or P picture. 3. An HDTV video decoder circuit as claimed in claim 2, wherein the adaptive vertical decimating part removes averages of even lines and odd lines adjoining each other in case the image is an interlace scanned image of odd fields.
4. An HDTV video decoder circuit as claimed in claim 2, wherein the adaptive vertical decimating part averages even lines and odd lines adjoining each other in the decimation if the picture.sub.-- structure is of frame, the image is an interlace scanned image, the DCT type is of field, the picture is of a luminance signal, and the field is odd fields.
5. An HDTV video decoder circuit as claimed in claim 2, wherein, if the picture.sub.-- structure is of frame, the image is an interlace scanned image, and the DCT type is of frame, the adaptive vertical decimating part removes every other lines for even lines in the decimation and averages every adjacent two odd lines for odd lines in the decimation.
6. An HDTV video decoder circuit as claimed in claim 2, wherein, if the picture.sub.-- structure is of frame, the image is an interlace scanned image, and the DCT type is of field, and the picture is of a color difference signal, the adaptive vertical decimating part removes every other lines for even lines in the decimation and averages every adjacent two odd lines for odd lines in the decimation.
7. An HDTV video decoder circuit as claimed in claim 2, wherein, if the picture.sub.-- structure is of frame and the image is a progressive scanned image, the adaptive vertical decimating part removes data on even lines in the decimation.
8. An HDTV video decoder circuit as claimed in claim 2, wherein, if the picture.sub.-- structure is of frame, the image is an interlace scanned image, and the DCT type is of field, the picture is of a luminance signal, and the field is even field, the adaptive vertical decimating part removes data on even lines in the decimation.
15. An HDTV video decoder circuit as claimed in claim 2, wherein the motion vector correcting part and the motion compensating part conduct a 1/4 pel resolution motion compensation employing a vertical motion vector corrected by vertical scaling down if an interlace.sub.-- frame is a field based mode.
16. An HDTV video decoder circuit as claimed in claim 2, wherein the motion vector correcting part and the motion compensating part conduct a 1/4 pel resolution motion compensation employing a vertical motion vector corrected by vertical scaling down if an interface.sub.-- frame is a frame based mode and half pel.
17. An HDTV video decoder circuit as claimed in claim 2, wherein the motion vector correcting part and the motion compensating part conduct motion vector correction by dividing a vertical motion vector by 2 and adding/subtracting 0.5 thereto/therefrom for even field and odd field respectively in the motion compensation between fields of the same parity if an interlace.sub.-- frame is in a frame based mode.
18. An HDTV video decoder circuit as claimed in claim 2, wherein the motion vector correcting part and the motion compensating part correct a frame motion vector into a field motion vector in the motion compensation between fields of different parities if an interlace.sub.-- frame is in a frame based mode.
22. A method for decoding an HDTV video comprising:(1) analyzing a motion vector and a coded structure of a received video signal, and decimating the video signal in a horizontal direction with reference to the analysis to restore the video signal; (2) inverse quantizing the data decimated in horizontal direction and conducting 8 (3) receiving the analyzed coded structure of the image and decimating the processed 8 the analyzed coded structure; (4) correcting a received motion vector value with reference to the motion vector and the analyzed coded structure of a video; and (5) conducting a motion compensation using the horizontally/vertically decimated video and a respective motion vector value to restore an original image. 23. A method as claimed in claim 22, wherein step (2) includes:determining the received image of being the progressive scanned image or the interlace scanned image; determining a picture-structure of the received image if the received image is determined of being the interlace scanned image; and determining a DCT type of the image in case the determined picture.sub.-- structure is a frame picture, and, if the DCT type is a frame DCT type, classifying even fields and odd fields and removing data on even line positions for each of the classified fields. 24. A method as claimed in claim 23, where, if the DCT type is determined of being a field DCT type, the method further comprises:determining the picture of being of a luminance signal or a color difference signal, removing data on even line positions if the picture is of the luminance signal, to decimate the image in the vertical direction by 1/2, and classifying even fields and odd fields and removing data on even line position for each of the classified fields if the picture is of the color difference signal, to decimate the image in the vertical direction by 1/2. 25. A method as claimed in claim 23, further including removing data on even line positions in case the received image is a progressive scanned image and the picture.sub.-- structure is a field picture, to decimate the image in the vertical direction by 1/2.
28. A method as claimed in claim 22, wherein correcting the received motion vector value includes:determining a picture.sub.-- structure of the received image of being of frame or of field, directly scaling down the motion vector if the picture.sub.-- structure is of the field to make a motion compensation in field units, an determining the image of being a progressive scanned image or an interlace scanned image if the picture.sub.-- structure is of the frame, directly scaling down the motion vector of the image is the progressive scanned image to make a motion compensation in frame units, an determining a format of the motion vector of being formatted in frame units or field units if the image is the interlace scanned image, and conducting a field motion compression in field units if the format of the motion vector is of frame, and conducting the field motion compensation by directly scaling down the motion vector if the format of the motion vector is of field. 29. The device recited by claim 1, wherein the horizontal decimating means decimate the video signal in the horizontal direction before the vertical decimating means decimate in the vertical direction.
31. A method for decimating an HDTV video comprising:analyzing a coded structure of a video signal, and decimating the video signal in a horizontal direction with reference to the analysis to restore the video signal; and receiving the analyzed coded structure of the video signal, and decimating the restored video signal in a vertical direction with reference to the analyzed coded structure. 32. The device recited by claim 1, wherein the decompression means includes:an inverse quantizing part for quantizing 8 data received from the horizontal decimating means; and an IDCT part for conducting an 8 from the inverse quantizing part. 33. A method for decoding an HDTV video image comprising:analyzing, a coded structure of an input bit stream; decimating the input bit stream corresponding to the HDTV video image in the horizontal direction to generate horizontally decimated data; decompressing the horizontally decimated data to generate decompressed data; decimating the decompressed data in the vertical direction according to the analyzed coded structure of the video image and generating vertically decimated data; and decoding a resolution signal from the vertically decimated data. Description
An object of the present invention involves on decoding a video bit stream encoded to the MPEG-2 even after reducing a required memory size to 1/4. Accordingly, unlike the conventional technique, the horizontal 1/2 decimation is conducted by a motion compensation of 1/4 half-pel resolution using a horizontal 1/2 zonal filtering, 8 scaled down motion vector. However, the vertical decimation is processed differently depending on whether in a bit stream an encoded progressive scanned picture or encoded interlace scanned picture. To reduce a frame memory, a decoded image is decimated by 1/2 in horizontal and vertical directions respectively. Since the video data stored in the frame memory is used for restoring the next image, the video data should be stored to suit to the nature of the image. Accordingly, as shown in FIG. 6, a progressive scanned image is decimated in a vertical direction, in which positions of decimated lines correspond to even line positions. And, for decoding an interlace scanned image, the even field and the odd field should be decimated independently. As shown in FIG. 7, decimated positions in this case correspond to even line positions for each of the even field and the odd field. In the meantime, a macro block(MB) for a general MPEG-2 decoder has 16 cosine transformed either with a frame DCT method, as shown in FIG. 8a or with a field DCT method, as shown in FIG. 8b. As shown in FIG. 8a, the frame DCT method includes the steps of slicing the macro block into four blocks and conducting a DCT for each of the 8 shown in FIG. 8b, the field DCT method includes the steps of separating the macro block by fields, slicing each of the fields into two, and conducting a DCT of each of the sliced fields.
Referring to FIG. 9, the HDTV video decoder circuit in accordance with a first embodiment of the present invention includes a VLD/demultiplexer 28 for conducting a variable length decoding of a received bit stream to separate the bit stream into motion vectors, quantizing values, and 8 horizontal high frequency regions from the quantizing values and the 8 inverse quantizing part 30 for quantizing the 8 from the zonal filter 29 according to the quantizing values, an IDCT part 31 for conducting an 8 inverse quantizing part 30 to restore a video signal, an adaptive vertical decimating part 32 for vertical 1/2 decimation of the IDCT transformed 8 4 correcting the motion vector from the VLD/demultiplexer 28 according to a motion type, a motion compensating part 35 for conducting a motion compensation to match to the blocks reduced by the motion vector corrected in the motion vector correcting part 34 to produce 8 macro blocks, an adding part 33 for adding the 8 composed of 4 blocks from the adaptive vertical decimating part 32 and the 8 compensating part 35 to restore to 8 36 for converting the video signal from the adding part 33 into a frame unit video signal according to B, I, P picture types and storing therein, a multiplexer 37 for selecting one from the video signals from the adding part 33 and the frame memory 36 depending on the B, I, P picture types, a line position correcting part 38 for correcting a line position as an odd field of the video signal from the multiplexer 37, and a switching part 39 for selecting an output from the multiplexer 37 if the decoding picture is a progressive scanned image and selecting an output from the line position correcting part 38 if the decoding picture is an interlace scanned image, and presenting to a VDP.
A received HDTV bit stream is variable length decoded in the VLD/demultiplexer 28, of which resultant motion vectors are applied to the motion vector correcting part 34 and quantizing values and 8 coefficients are removed from horizontal high frequency regions in the zonal filter 29 and selected of quantizing values and coefficients corresponding to an 8 is composed of a macro block buffer of 8 filter 29 removes the horizontal high frequency regions, but not vertical high frequency regions, in order to restore the even, and odd fields, exactly. Therefore, of the 8 VLD/demultiplexer 28, the zonal filter 29 only selects coefficients for a 8 Accordingly, a quantizing rate of the inverse quantizing part 30 is reduced to 1/2, and an IDCT unit of the IDCT part 31 changes to 8 That is, the coefficients from the zonal filter 29 are quantized in the inverse quantizing part 30 according to the quantizing values, and 8 being restored into a video signal. The 8 in the IDCT part 31 is vertically decimated by 1/2 in the adaptive vertical decimating part 32 according to a DCT type to produce 4 pixels per block. That is, upon reception of a horizontally 1/2 decimated block, the adaptive vertical decimating part 32 vertically decimates differently depending on DCT types, picture structures, progressive.sub.-- frames and component indices. As shown in FIGS. 8a and 8b, there are frame DCTs and field DCTs in the DCT types, and there are field pictures in which even or odd fields compose a picture and frame pictures in which even, and odd fields together compose a picture in the picture structure. Therefore, in a decimation, the adaptive vertical decimating part 32 removes data on even line positions, as shown in FIG. 10, or data on pairs of even and odd fields after dividing a picture into even and odd fields as shown in FIG. 11 depending on DCT types, picture structures, progressive frames and component indices. The decimation shown in FIG. 10 is used when no division into even and odd fields is required, and the decimation shown in FIG. 11 is used when the DCT coefficients is a mix of even and odd coefficients to require a classification. The method of decimation whether to decimate by removing the data on the even lines, as shown in FIG. 10, or to decimate by removing pairs of even and odd fields after division into even and odd fields in advance, is determined based on different decoded parameters as shown in FIG. 12.
Referring to FIG. 12, in the S40 step, a progressive.sub.-- frame is determined of being `1` or `0`. If the progressive.sub.-- frame is `1`, the image is a progressive scanned image, if the progressive.sub.-- frame is `0`, the image is an interlace scanned image. If the progressive.sub.-- frame is `1`, there is no separate even fields and odd fields because it is a progressive scanned image. Therefore, as the image will have a frame structure as shown in FIG. 6, the adaptive vertical decimating part 32 removes data on even line positions from the data received from the IDCT part 31 to decimate the image by 1/2 in a vertical direction(S45).
In the meantime, if the progressive.sub.-- frame is determined to be `0` in the S40 step, as it indicates that the image is an interlace scanned image, which has a frame structure as shown in FIG. 7, the image should be decimated with the even fields and odd fields classified, without confusing the fields. Therefore, if the image is determined to be an interlace scanned image in the S40 step, a picture structure of the image should be determined. That is, since a picture structure of an interlace scanned image is either a frame picture in which an odd line is an odd field and an even line is an even field, or a field picture in which an even filed and an odd field are formed separate, in case of a bit stream composed of a field picture in which even fields and odd fields should not be mixed, if the picture structure is determined to be a field picture in the step S41, the adaptive vertical decimating part 32 removes data on even line positions from the data from the IDCT part 31 to decimate by 1/2 in a vertical direction as shown in FIG. 10(S45).
In the meantime, a reference unit of the motion compensation in an MPEG-2 video decoder is, 16 and 8 the received bit stream was decimated by 1/2 in horizontal and vertical direction respectively through the VLD/demultiplexer 28, zonal filter 29, inverse quantizing part 30, IDCT 31, and adaptive vertical decimating part 32, the reference unit of the motion compensation will be reduced to 8 color difference signal. Accordingly, a correction in the motion compensation method, such as correction of the motion vector is required. Particularly, in case an interlace scanned image is coded into a frame picture as shown in FIG. 11, in which the image is decimated in the vertical direction by 1/2 in field units lest the information between fields is lost, in case of a frame motion compensation, a vertical frame motion vector should be converted into a field motion vector and the motion compensation should be conducted in field units. Accordingly, the motion compensation of the motion vector compensating part 34 for each case and the subsequent operation of the motion compensating part 35 will be explained with reference to FIGS. 13�16, in detail. First, the vertical motion compensation will be explained.
On the other hand, if the image is determined of being a progressive scanned image encoded into a frame picture in the step S47 in which the image is vertically decimated by 1/2 in frame units, the vertical motion vector is directly scaled down by 1/2 as in the case of iii) and frame compensation is always conducted in a step S51. And, if the picture structure is determined of field in the step S46 in which an interlace scanned image is encoded into a field picture conserving field information as it was, the vertical motion vector is directly scaled down as in the case of the iiii) in a step S52 to compensated a field motion. The picture.sub.-- structure used in the step S46 in FIG. 17 in determining a picture structure, the progressive.sub.-- frame used in the step S47 in determining the image of being an interlace, or progressive scanned image, and the mv.sub.-- format used in the step S48 in detenmining a motion vector format, are signals cited in the MPEG-2 video standard. That is, if the picture structure is of field, the vertical motion vector is directly scaled down by 1/2 to compensate the field motion, and if the picture structure is of frame while being a progressive scanned image, the vertical motion vector is directly scaled down by 1/2 and the frame compensation is always conducted. And, if the picture structure is of frame and an interlace scanned image while the motion vector format is of field, the vertical motion vector is directly scaled down by 1/2 to make a field motion compensation. And, if the picture structure is of frame and an interlace scanned image while the motion vector format is of frame, the vertical frame motion vector is converted into a field motion vector, the frame motion is divided into field unit motions, and a field motion compensation for each of the divided motions is conducted.
Once the motion vector correction is thus done according to each of the cases in the motion vector correcting part 34, the motion compensating part 35 conducts a motion compensation as shown in FIG. 17 to fit to the blocks decimated by 1/2 in vertical and horizontal directions respectively using such a corrected motion vector and applies 8 blocks to the adding part 33. The adding part 33 adds the 8 composed of four blocks from the adaptive vertical decimating part 32 and the 8 compensating part 35 to restore 8 if the macro block data decoded into 8 part 33 is a B picture, the macro block data is, not stored in the frame memory 36, but applied to the multiplexer 37, and if the macro block data is I or P picture, the macro block data is, stored in the frame memory 36 and a prior I or P picture is read-in from the frame memory 36 and applied to the multiplexer 37. The multiplexer 37 selects an output from the adding part 33 if the picture type is B and an output from the frame memory 36 if the picture type is I or P, to apply directly to the VDP through the switching part 39, if the decoded picture is a progressive scanned image, and to the line position correcting part 38, if the image is an interlace scanned image, to correct odd field line positions. That is, the line position correcting part 38, which is provided for correcting line positions of an interlace scanned image into even lines and odd lines fit to a display, arranges output data employing a vertical filter. In this instant, even if intervals between even and odd fields are not regular, the irregular intervals between the even and odd fields are made regular as shown in FIG. 18, That is, in an even field, in case of a luminance signal, a decoded signal is directly produced as it was, and in case of a color signal, an weighted average of decoded adjacent color signals is produced, and in an odd field, in case of a luminance signal, an weighted average of decoded adjacent luminance signals is produced, and in case of a color signal, an weighted average of decoded adjacent color signals is produced. Accordingly, the switching part 39 presents the data from the multiplexer 37 in case the decoded picture is a progressive scanned image, and presents the data corrected in the line position correcting part 38 in case the image is an interlace scanned image. In this case, however, the HDTV video decoder of the present invention requires the line position correcting part for matching line positions of the decimated odd fields to display line positions because the line positions from the adaptive vertical decimating part does not match to the display line positions in case of an interlace scanned image, that causes an increase of hardware.
Referring to FIG. 19, the HDTV video decoder circuit in accordance with a second embodiment of the present invention includes a VLD/demultiplexer 53 for conducting a variable length decoding of a received bit stream to separate the bit stream into motion vectors, quantizing values and 8 horizontal high frequency regions from the quantizing values and the 8 inverse quantizing part 55 for quantizing the 8 from the zonal filter 54 according to the quantizing values, an IDCT part 56 for conducting an 8 inverse quantizing part 55 to restore a video signal, an adaptive vertical decimating part 57 for vertical 1/2 decimation of the IDC transformed 8 progressive.sub.-- frame value to produce 4 motion vector correcting part 60 for correcting the motion vector from the VLD/demultiplexer 53 according to a motion type and progressive.sub.-- frame value, a motion compensating part 61 for conducting a motion compensation to match to the blocks reduced by the motion vector corrected in the motion vector correcting part 60 to produce 8 macro blocks, an adding part 58 for adding the 8 composed of 4 blocks from the adaptive vertical decimating part 57 and the 8 compensating part 61 to restore to 8 59 for converting the video signal from the adding part 58 into a frame unit video signal according to picture types and storing therein, and a multiplexer 62 for selecting one from the video signals from the adding part 58 and the frame memory 59 depending on the picture types.
A received HDTV bit stream is variable length decoded in the VLD/demultiplexer 53, of which resultant motion vectors are applied to the motion vector correcting part 60, and quantizing values and 8 coefficients are removed of horizontal high frequency regions in the zonal filter 54 and selected of quantizing values and coefficients corresponding to an 8 a macro block buffer of 8 the horizontal high frequency regions, but not vertical high frequency regions, in order to restore the even, and odd fields, exactly. Therefore, of the 8 filter 54 only selects coefficients for a 8 the inverse quantizing part 55. Accordingly, a quantizing rate of the inverse quantizing part 55 is reduced to 1/2, and an IDCT unit of the IDCT part 56 becomes to change to 8 zonal filter 54 are quantized in the inverse quantizing part 55 according to the quantizing values, and 8 transformed in the IDCT part 56, for being restored into a video signal. The 8 decimated by 1/2 in the adaptive vertical decimating part 57 according to a DCT type and progressive frame value to produce 4 block. That is, in the vertical direction decimation in the adaptive vertical decimating part 57, the image is decimated in the vertical direction by 1/2 as shown in FIG. 20 if the image is a progressive scanned image, in which removed line positions corresponds to even line positions. And, if the image is an interlace scanned image, the decimation should be conducted for even fields and odd fields independently; in case of even lines, values on even line positions are removed as shown in FIG. 21, and in case of odd lines, averages of adjacent even lines and odd lines are removed. In case of an interlace scanned image, when the decimation is conducted for the even fields and odd fields differently, spatial phases of the fields in the decimated image become proper. That is, the adaptive vertical decimating part 57 vertically decimates horizontally 1/2 decimated blocks differently according to DCT types, picture structures, progressive.sub.-- frames and component indices. As shown in FIGS. 8a and 8b, there are frame DCTs and field DCTs in the DCT types, and there are field pictures in which even, or odd fields compose a picture and frame pictures in which even, and odd fields together compose a picture in the picture structure.
In the meantime, if the picture structure is determined of being of frame in the step S61, a progressive.sub.-- frame is determined of being `1` or `0` in the step S62, i.e., determined of being a progressive scanned image or interlace scanned image. If the progressive.sub.-- frame is `1`, the picture structure is a progressive scanned image and if the progressive.sub.-- frame is `0`, the picture structure is an interlace scanned image. Therefore, if the picture structure is determined of being the progressive scanned image in the step S62, which has no separate even and odd fields with the frame structure as shown in FIG. 6, the image is decimated by 1/2 in the step S62 selecting even lines only as shown in FIG. 25. And, if the picture structure is determined of being the interlace scanned image in the step S62, the DCT type of the image is determined of being of frame or field in the step S63. If the DCT type is determined of being of frame in the step S63, the image is decimated in field units in order not to lose its field information as shown in FIG. 21; every other lines of the even lines are removed and every adjacent odd lines are averaged in the decimation. If the DCT type is determined of being of field in the step S63, the picture is determined of being of a luminance signal or a color signal in the step S64. If the picture is determined of being of a color signal in the step S64, as shown in FIG. 24, every other lines of the even lines are removed and every adjacent odd lines are averaged in the decimation. If the picture is determined of being of a luminance signal in the step S64, the field is determined of being an even field or odd field in the step S65. If the field is determined of being an odd field in the step S65, as shown in FIG. 23, even lines and odd lines adjoining each other are averaged in the decimation. And, if the field is determined of being an odd field in the step S65, as shown in FIG. 25, only even lines are selected in the step S68 in decimating the image by 1/2.
Since the decoded lines in the progressive.sub.-- frame correspond to the even lines of an original picture, in which a distance between each of the decoded lines is 2 and the resolution of an original motion vector is half pel size, in a motion compensation of the progressive.sub.-- frame, the three interposed points between the decoded lines as shown in FIG. 26 can be reference frames. Therefore, as shown in FIG. 27, the two least significant bits of a motion vector represent a vertical interposed point, and the most significant bit represents a relative distance of lines.
On the other hand, as an interlace scanned image has even fields and odd fields and, as shown in FIG. 19, has its odd fields corrected to be matched to the display lines, when there are motion compensations between fields in a field picture, the interlace scanned image should be corrected of its motion vectors. If a reference field and an estimated field are on the same parity, though the motion vector correction is done if the motion vector is scaled down by 1/2, if the reference field and the estimated field are on fields of which parities are different from each other, the motion vector should be corrected as shown in FIG. 28. That is, a .+-5 should be added to an original motion vector, and [TABLE 5] shows respective corrected value.
Once the motion vector compensating part 60 thus conducts motion vector compensation according to each of the cases, the motion compensating part 61 makes motion compensation to fit to the blocks 1/2 decimated in the horizontal and vertical directions respectively using the motion vector corrected as above to produce and apply 8 adding part 58. The adding part 58 adds the 8 blocks from the adaptive vertical decimating part 57 and the 8 reference blocks motion compensated in the motion compensating part 61 to restore 8 8 stored in the frame memory 59, but applied to the multiplexer 62 directly, and if the data is of I or P picture, the data is stored in the frame memory 59 while a prior I or P picture is read in from the frame memory 59 and applied to the multiplexer 62. The multiplexer 62 selects an output from the adding part 58 if the picture type is B, and selects an output from the frame memory 59 and presents to the VDP if the picture type is I or P. Therefore, only with a 1/4 frame memory size, an MPEG-2 video bit stream can be decoded to allow obtaining an image decoded in horizontal and vertical directions by 1/2 for a progressive scanned picture or a interlace scanned picture.
As has been explained, in comparison to a conventional MPEG-2 video decoder which uses a 4 interlace scanned image into frame picture only to lose field information of the image resulting in a significant damage to the picture quality, the HDTV video decoder circuit of the present invention facilitates to maintain the field information as it was resulting in an improvement in the picture quality while requiring a 1/4 size frame memory. Accordingly, the present invention is cost competitive because it has applications to low cost MPEG-2 decoders, and, particularly, to substantially low cost video decoders, without use of conventional HDTV videos in reception of low resolution TV, such as SDTV, or NTSC TV for high definition images such as HDTV.
FIG. 26 illustrates the process of motion compensation of a progressive.sub.-- frame in view of pixels in the circuit shown in FIG. 19;
The GA(Grand Alliance) HDTV system, which is the U.S.A. HDTV standard, has video compression and multiplexing techniques following the MPEG-2(Moving Picture Experts Group-2) standards. It also has the capability for plural broadcasting video formats including with 24 Hz 30 Hz progressive scanning systems, and a 60 Hz interlaced scanning system for 1920 pixels, and 24 Hz, 30 Hz and 60 Hz progressive scanning systems for 1280
Referring to FIG. 1, upon reception of an HDTV bit stream, the VLD/demultiplexer 11 makes a variable length decoding of the bit stream and separates the bit stream into motion information, a quantizing value and at least one coefficient. The separated motion vector is applied to the motion compensating part 18, and the quantizing value and the coefficients are applied to the inverse quantizing part 12. The inverse quantizing part 12 inverse quantizes the coefficient from the VLD/demultiplexer 11 according to the quantizing value, and the inverse quantized coefficient is, restored into a video signal through an inverse DCT of 8 14. The adding part 14 adds the video signal from the IDCT part 13 to a signal predicted in the frame buffer 17 through the motion compensation in the motion compensating part 18 to restore a perfect image which is applies to the frame buffer 15. The frame buffer 15 converts the video signal from the adding part 14 into a frame unit video signal and which is applied to the slice buffer 16, and the slice buffer 16 converts the video signal from the frame buffer 15 into a line unit video signal which is thereafter presented as output. The video signal from the adding part 14 is converted into a frame unit video signal and stored in the frame buffer 17 of 6 M byte size, and the motion compensating part 18 makes a motion compensation of the video signal from the frame buffer 17 according to the motion vector from the VLD/demultiplexer 11 and applies the compensated video signal to the adding part 14.
A decimated image that is proportional to, for example, a selected region of an N discrete cosine transformation of the N region smaller than N and discarding the rest through a zonal filter, and conducting an inverse discrete cosine transformation suitable to the selected region. In this instant, an image decimated by 1/2 in vertical and horizontal directions can be obtained by using the zonal filter because the resolution of an NTSC image is 1/4 the resolution of an HDTV image.
Referring to FIG. 2a the feature of this system is the zonal filter 20 provided between the VLD/demultiplexer 19 and inverse quantizing part 21 of the system shown in FIG. 1, for selecting a quantizing value and a coefficient of a region corresponding to 1/4 of a macro block size among the quantizing values and coefficients from the VLD/demultiplexer 19. The IDCT part 22 in FIG. 2 conducts an inverse discrete cosine transformation of the quantized coefficient from the inverse quantizing part 21 in 4 received HDTV bit stream is finally presented as a video signal decimated by 1/2 in horizontal and vertical directions, i.e., a video signal decimated by 1/4 size.
A received HDTV bit stream is subjected to variable length decoding in the VLD/demultiplexer 19, from which motion vectors are applied to the motion compensating part 27, and quantizing values and coefficients are applied to the zonal filter 20. The received quantizing values and coefficients are filtered in the zonal filter 20; of the received quantizing values and coefficients, the quantizing values and coefficients in a region corresponding to a 4 Therefore, the zonal filter 20 has a macro block buffer corresponding to the 4 selects coefficients only from the 4 received from the VI.D/demultiplexer 19 and applies to the inverse quantizing part 21. Accordingly, a production rate of the inverse quantizing part 21 is reduced to 1/4 and an IDCT unit of the IDCT part 22 is also changed to 4 20 are inverse quantized in the inverse quantizing part 21 according to a quantizing value, and the quantized coefficients from the quantizing part 21 is inverse discrete cosine transformed in the IDCT part 22, to be restored as a perfect video signal.
In this time, since the IDCT unit is changed to 4 function of the IDCT part 22 should also be changed as follows, ##EQU1##
Therefore, the number of operations required the 4 implementation is reduced by a factor of approximately 1/16. And, a capacity of the frame memory required for the motion compensating part 27 and the frame buffer 26 is also reduced by a factor of 1/4. Accordingly, a volume of hardware required for implementation of such a video decoder is reduced to about below 1/4 in overall.
In the meantime, the video signal from the IDCT part 22 is added in the adding part 23 to the video signal motion compensated in the motion compensating part 27, and the video signal from the adding part 23 is, converted into a frame unit video signal in the frame buffer 24 and into a line unit video signal in the slice buffer 25, and finally presented. The video signal from the adding part 23 is stored in the frame buffer 26 in frame units for motion compensation; it is then applied to the motion compensating part 27. In this case, in the MPEG-2 video compression standard, a half-pet resolution level is applied to the interpolation in the motion compensation for improving correlation. That is, a motion vector transmitted through a channel is of the half-pel resolution. Accordingly, when of implementing a decoder in which the zonal filter 20 only selects a 4 decimated by 1/2 in horizontal and vertical directions respectively, a motion compensation of an interpolation to a quarter pel resolution in horizontal and vertical directions respectively are applied based on the received half-pel resolution motion vector for substantially reducing errors occurred in the motion compensation, which has been verified through a mock test. FIGS. 4 and 5 illustrate examples of such interpolation techniques for motion compensation. That is, of received horizontal and vertical 6 bit motion information, each of 2 least significant bits contains information which can interpolate up to 1/4 pel resolution, and specific interpolating methods using the information are shown in FIGS. 4 and 5.
However, though the conventional HDTV video decoder can effectively decode a bit stream of a progressive scanned image compressed according to the MPEG-2 standard, and having a frame that is composed of pixels formed at the same time, the conventional HDTV video decoder experiences severe errors when decoding an interlace scanned image having a frame that is composed of two fields of different time bases. That is, though there is no problem in decoding a progressive scanned image or interlace scanned image into a field picture if a vertical direction decimation is conducted applying a vertical direction 1/2 zonal filtering and a 4 case the picture quality suffers from vital damage because of loss of time information when decoding mixed images of two times bases within a frame, like the case of decoding an interlace scanned image into a frame picture. As this vertical decimation is not practicable, an 8 frame memory reduced by 1/2 in a horizontal direction are used, which results in increased costs.
In another aspect of the present invention, there is provided an HDTV video decoder circuit including a VLD/demultiplexer for conducting a variable length decoding of a received bit stream to separate motion vectors, quantizing values, and 8 filter for removing horizontal high frequency regions from the quantizing values and the 8 VLD/demultiplexer, an inverse quantizing part for quantizing the 8 DCT coefficients from the zonal filter according to the quantizing values, an IDCT part for conducting an 8 coefficients from the inverse quantizing part to restore a video signal, an adaptive vertical decimating part for decimating an odd field of an interlace scanned image signal with the odd field matched to a display line position to produce 4 decimation of the IDC transformed 8 according to a DCT type and a progressive.sub.-- frame value, a motion vector correcting part for correcting the motion vector from the VLD/demultiplexer according to the motion vector value and progressive.sub.-- frame value, a motion compensating part for conducting a motion compensation of 8 blocks reduced by the motion vector corrected in the motion vector correcting part, an adding part for adding the 8 composed of 4 blocks from the adaptive vertical decimating part and the 8 compensating part to restore 8 converting the video signal decimated by 1/2 in horizontal and vertical directions respectively in the adding part into a frame unit video signal according to B, I, P picture types and storing therein, and a multiplexer for selecting an output from the adding part if it is a B picture, and selecting the video signal from the frame memory if it is I or P picture.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5412428 *Dec 9, 1993May 2, 1995Sony CorporationEncoding method and decoding method of color signal component of picture signal having plurality resolutionsUS5485216 *Aug 11, 1994Jan 16, 1996Goldstar Co., Ltd.Video format conversion apparatus for high definition televisionUS5485279 *Jul 2, 1993Jan 16, 1996Sony CorporationMethods and systems for encoding and decoding picture signals and related picture-signal recordsUS5504530 *Jun 25, 1993Apr 2, 1996Sony CorporationApparatus and method for coding and decoding image signalsUS5519446 *Nov 14, 1994May 21, 1996Goldstar Co., Ltd.Apparatus and method for converting an HDTV signal to a non-HDTV signalUS5574565 *Oct 28, 1994Nov 12, 1996Samsung Electronics Co., Ltd.Data placement on tape for a digital video tape recorder suitable for high speed picture playbackUS5684539 *Aug 9, 1996Nov 4, 1997Hitachi America, Ltd.Method and apparatus for processing encoded video data to reduce the amount of data used to represent a video imageUS5708732 *Mar 6, 1996Jan 13, 1998Hewlett-Packard CompanyFast DCT domain downsampling and inverse motion compensationUS5737019 *Jan 29, 1996Apr 7, 1998Matsushita Electric Corporation Of AmericaMethod and apparatus for changing resolution by direct DCT mappingUS5742343 *Aug 19, 1996Apr 21, 1998Lucent Technologies Inc.Scalable encoding and decoding of high-resolution progressive videoUS5754238 *Mar 26, 1996May 19, 1998Sony CorporationPicture signal decoding method and apparatus thereofUS5832120 *Mar 26, 1996Nov 3, 1998Cirrus Logic, Inc.Universal MPEG decoder with scalable picture sizeUS5832124 *Mar 28, 1994Nov 3, 1998Sony CorporationPicture signal coding method and picture signal coding apparatus, and picture signal decoding method and picture signal decoding apparatus* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6424381 *Jun 26, 1998Jul 23, 2002Lsi Logic CorporationFiltering decimation technique in a digital video systemUS6539120 *Mar 11, 1998Mar 25, 2003Matsushita Electric Industrial Co., Ltd.MPEG decoder providing multiple standard output signalsUS6608867 *Mar 30, 2001Aug 19, 2003Koninklijke Philips Electronics N.V.Detection and proper scaling of interlaced moving areas in MPEG-2 compressed videoUS6658546Feb 23, 2001Dec 2, 2003International Business Machines CorporationStoring frame modification information in a bank in memoryUS6665346 *Apr 30, 1999Dec 16, 2003Samsung Electronics Co., Ltd.Loop-filtering method for image data and apparatus thereforUS6788347 *Mar 11, 1998Sep 7, 2004Matsushita Electric Industrial Co., Ltd.HDTV downconversion systemUS6839384 *Nov 13, 2001Jan 4, 2005Nec CorporationMethod and apparatus for decoding compressed video signalsUS6850571 *Apr 23, 2001Feb 1, 2005Webtv Networks, Inc.Systems and methods for MPEG subsample decodingUS6950469 *Sep 17, 2001Sep 27, 2005Nokia CorporationMethod for sub-pixel value interpolationUS7050494 *Jun 4, 1999May 23, 2006Nec CorporationFrame display method and apparatus using single field dataUS7079190 *Dec 27, 2001Jul 18, 2006Zoran CorporationTechnique for determining the slope of a field pixelUS7139315May 18, 2004Nov 21, 2006Sanyo Electric Co., Ltd.Apparatus and process for decoding motion picturesUS7471834 *Feb 10, 2003Dec 30, 2008Vmark, Inc.Rapid production of reduced-size images from compressed video streamsUS7483577 *Mar 2, 2004Jan 27, 2009Mitsubishi Electric Research Laboratories, Inc.System and method for joint de-interlacing and down-sampling using adaptive frame and field filteringUS7515210 *Jun 5, 2006Apr 7, 2009Zoran CorporationTechnique for determining the slope of a field pixelUS7564902 *Nov 19, 2003Jul 21, 2009Panasonic CorporationDevice, method and program for generating interpolation frameUS7612829Sep 13, 2005Nov 3, 2009Zoran Corporation2:2 and 3:2 pull-down detection techniquesUS7639742 *Nov 29, 2002Dec 29, 2009Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS7929612 *May 24, 2005Apr 19, 2011Samsung Electronics Co., Ltd.Image interpolation apparatus and methods that apply quarter pel interpolation to selected half pel interpolation resultsUS8155195Apr 7, 2006Apr 10, 2012Microsoft CorporationSwitching distortion metrics during motion estimationUS8189670Jun 11, 2009May 29, 2012Panasonic CorporationDevice, method and program for generating interpolation frameUS8213497 *Jun 27, 2007Jul 3, 2012Sony CorporationMoving image converting apparatus, moving image converting method, and computer programUS8213502 *Dec 31, 2007Jul 3, 2012Ceva D.S.P. Ltd.Method and system for real-time adaptive quantization controlUS8243806 *Apr 24, 2007Aug 14, 2012Hitachi, Ltd.Recording and reproducing apparatus, sending apparatus and transmission systemUS8243808 *Dec 19, 2008Aug 14, 2012Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS8243809 *Dec 19, 2008Aug 14, 2012Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS8275043 *Dec 19, 2008Sep 25, 2012Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS8437402 *Jun 5, 2012May 7, 2013Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS8457209 *Jun 5, 2012Jun 4, 2013Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS8494052Apr 7, 2006Jul 23, 2013Microsoft CorporationDynamic selection of motion estimation search ranges and extended motion vector rangesUS8542742 *Dec 12, 2012Sep 24, 2013Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS8548059 *Dec 12, 2012Oct 1, 2013Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS20060233258 *Apr 15, 2005Oct 19, 2006Microsoft CorporationScalable motion estimationUS20070248331 *Apr 24, 2007Oct 25, 2007Koichi HamadaRecording and Reproducing Apparatus, Sending Apparatus and Transmission SystemUS20090103623 *Dec 19, 2008Apr 23, 2009Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS20090129483 *Jan 22, 2009May 21, 2009Broadcom CorporationArtifact-Free Displaying of MPEG-2 Video in the Progressive-Refresh ModeUS20090135914 *Dec 19, 2008May 28, 2009Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS20090168869 *Dec 31, 2007Jul 2, 2009Eldad MelamedMethod and system for real-time adaptive quantization controlUS20090168888 *Dec 19, 2008Jul 2, 2009Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS20120243617 *Jun 5, 2012Sep 27, 2012Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS20120243800 *Jun 5, 2012Sep 27, 2012Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS20130093950 *Dec 12, 2012Apr 18, 2013Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS20130101020 *Dec 12, 2012Apr 25, 2013Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUS20130101044 *Dec 12, 2012Apr 25, 2013Sony CorporationImage information encoding method and encoder, and image information decoding method and decoderUSRE39455 *Oct 18, 2000Jan 2, 2007Matsushita Electric Industrial Co., Ltd.Video coding method and decoding method and devices thereofUSRE40080 *Oct 18, 2000Feb 19, 2008Matsushita Electric Industrial Co., Ltd.Video coding method and decoding method and devices thereofCN100467380CMay 28, 2002Mar 11, 2009昭和电工株式会社Spherical alumina particles and production process thereofEP1443771A2 *Feb 3, 2004Aug 4, 2004Samsung Electronics Co., Ltd.Video encoding/decoding method and apparatus based on interlaced frame motion compensation* Cited by examinerClassifications U.S. Classification375/240.16, 375/E07.171, 375/E07.211, 375/E07.212, 375/E07.15, 375/E07.094, 375/E07.181, 375/E07.229, 375/E07.176, 375/240.21, 375/E07.226, 375/E07.027, 375/E07.198International ClassificationH04N7/26, G06T9/00, H04N7/30, H04N7/50, H04N7/24Cooperative ClassificationH04N19/00127, H04N19/00278, H04N19/00296, H04N19/00533, H04N19/00309, H04N19/00266, H04N19/00224, H04N19/00084, H04N19/00684, H04N19/00484, H04N19/00757, H04N19/00781, H04N19/00012European ClassificationH04N7/26A8C, H04N7/26M6, H04N7/26A4Z, H04N7/46S, H04N7/26A4, H04N7/26A8T, H04N7/26A4T, H04N7/30S, H04N7/50, H04N7/26L2, H04N7/26A8P, H04N7/26A8B, H04N7/26A6S4, H04N7/26DLegal EventsDateCodeEventDescriptionSep 22, 2011FPAYFee paymentYear of fee payment: 12Jan 17, 2008FPAYFee paymentYear of fee payment: 8Jan 14, 2004FPAYFee paymentYear of fee payment: 4Jun 9, 1997ASAssignmentOwner name: LG ELECTRONICS INC., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, JIN-GYEONG;LYU, HWA-YOUNG;REEL/FRAME:008607/0307Effective date: 19970404RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google