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Patent US6918105 - Phase-shift lithography mapping method and apparatus - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsFor phase-shifting microlithography, a method of assigning phase to a set of shifter polygons in a mask layer separated by a set of target features includes assigning a first phase to a first shifter polygon, identifying a set of target features that touch the first shifter polygon, and assigning a second...http://www.google.com/patents/US6918105?utm_source=gb-gplus-sharePatent US6918105 - Phase-shift lithography mapping method and apparatusAdvanced Patent SearchPublication numberUS6918105 B2Publication typeGrantApplication numberUS 10/315,906Publication dateJul 12, 2005Filing dateDec 9, 2002Priority dateJun 30, 2000Fee statusPaidAlso published asUS6493866, US7415694, US20030159126, US20050257189, WO2002003139A2, WO2002003139A3, WO2002003139A9Publication number10315906, 315906, US 6918105 B2, US 6918105B2, US-B2-6918105, US6918105 B2, US6918105B2InventorsJeffrey P. MayhewOriginal AssigneeSynopsys, IncExport CitationBiBTeX, EndNote, RefManPatent Citations (17), Non-Patent Citations (22), Referenced by (4), Classifications (7), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetPhase-shift lithography mapping method and apparatus
US 6918105 B2Abstract
1. A computer-implemented method for assigning phases to a plurality of light shifter polygons of a photolithographic mask through which light is to be transmitted to photolithographically pattern an area on a substrate, wherein the mask has a plurality of locations corresponding to a plurality of target features which are located between the shifter polygons, the method comprising:
(A) selecting at least one shifter polygon from a pool P1 formed by said plurality of light shifter polygons and forming a set SP1 of all selected polygons; (B) removing from said pool P1 all selected polygons that are added to said set SP1; (C) adding at least one polygon from said set SP1 to a group of polygons to be associated with a phase; (D) identifying a set TF1 comprising at least one target feature of said plurality of target features that form a pool P2 such that each target feature in said set TF1 has a portion having an edge adjacent one of said at least one shifter polygon in said set SP1; (E) determining a set SP2 comprising at least one shifter polygon in said pool P1, such that for each shifter polygon in said set SP2 at least one predetermined condition is satisfied; (F) removing from said pool P1 all polygons that are determined to be in said set SP2; and (G) adding all polygons in said set SP2 to a group of polygons to be associated with a phase other than the phase used in a previous act of adding. 2. The computer-implemented method of claim 1 further comprising:
(H) removing all polygons currently in said set SP1; (I) removing all polygons currently in said set TF1; (J) adding to said set SP1 all polygons currently in said set SP2; (K) removing all polygons currently in said set SP2; and (L) repeating the acts (D), (E), (F) and (G). 3. The computer-implemented method of claim 2 further comprising repeating until said pool P1 is empty, said acts (H), (I), (J), (K) and (L).
4. The computer-implemented method of claim 1 wherein said at least one predetermined condition is satisfied when a shifter polygon in said set SP2 has an edge adjacent to a target feature in said set TF1.
This application is a continuation of U.S. patent application, Ser. No. 09/608,498 filed Jun. 30, 2000 now U.S. Pat. No. 6,493,866, entitled PHASE-SHIFT LITHOGRAPHY MAPPING METHOD AND APPARATUS by Jeffrey P. Mayhew, that is incorporated by reference herein hi its entirety.
Appendix A contains the following file in one CD-ROM in IBM-PC format and compatible with Microsoft Windows(of which two identical copies are attached hereto). Appendix A is a part of the present disclosure and is incorporated by reference herein hi its entirety.
Volume in drive D is 021209�1859 Volume Serial Number is 429C-56D7 Directory of D:\ Dec. 9, 2002 10:34a 20,895 Appendix.txt
1 File(s) 20,895 bytes 0 Dir(s) 0 bytes free The files of Appendix A form source code of computer programs (in the form of a Hercules runset) for implementing an illustrative embodiment of the present invention,
A portion of the disclosure of this patent document contains material which is subject to copyright protection The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears hi the patent and trademark office patent files or records, but otherwise reserves all copyright rights whatsoever.
In semiconductor manufacture, micro lithography is used in the formation of integrated circuits on a semiconductor wafer. During a lithographic process, a form of radiant energy, such as ultraviolet light, is passed through a photo mask or a reticle and onto the semiconductor wafer. �Light� is not limited to the visible spectrum. The photo mask contains opaque and transparent regions formed in a predetermined pattern. A grating pattern, for example, can be used to define parallel spaced conducting lines on a semiconductor wafer. The ultraviolet light exposes the mask pattern on a layer of resist formed on the wafer. The resist is then developed to remove either the exposed portions of resist for a positive resist or the unexposed portions of resist for a negative resist. The patterned resist can then be used for subsequent semiconductor fabrication processes such as ion implantation or etching.
Recently, different techniques have been developed in the art for fabricating different types of phase shifting photo masks. One type of phase shifting mask, named after a pioneer researcher in the field, M. D. Levenson, is known in the art as a �Levenson� or �strong� phase shifting mask. This type of mask is also referred to as an �alternating aperture� phase shifting mask because every other aperture contains a phase shifter. The term �strong� refers to the use of non-attenuated or full strength phase shifting illumination.
With phase shift lithography, the interference of light rays is used to improve the resolution and depth of focus of an image projected onto a target. In �strong� phase shift lithography, the phase of an exposure light at the object is controlled such that adjacent bright areas are formed preferably 180 degrees out of phase with one another. Dark regions are thus produced between the bright areas by destructive interference even when diffraction without phase shifting would otherwise cause these areas to be exposed away. This technique improves total resolution at the object and allows resolutions as fine as 0.1 μm or finer to occur.
In order to generate a phase shift lithography mask, target features in a given circuit design, or features that are small enough to require phase shift lithography, are identified. Next, shifter polygons meeting dimensional criteria dictated by mask-making constraints and optical performance are created on either side of each target feature. Then, the shifter polygons are �colored,� that is, assigned one of two color designations, so that each target feature is sandwiched between shifter polygons of opposing colors. The two colors correspond to the phase shifted and non phase shifted apertures.
The phase-shift mask is created in the DRC tool by applying several logical (such as not, and, or, and xor) and sizing operations to a representation of the circuit design to form output layers, such as a layer of target features, a layer of shifter polygons that pass light of phase 0�, and a layer of shifter polygons that pass light of phase 180�. The output layers correspond to features created on one or more masks. For simplicity, assigning shifter polygons to a particular output layer is referred to as assigning phase to a polygon or phase mapping a polygon.
Once the shifter polygons are created, one needs to assign phases to the shifter polygons. Assigning phase by hand is burdensome particularly for random logic. Typical computer methods require first sorting the shifter polygons into runs of shifter polygons oriented in the same direction. A �run� refers to a horizontal �run� of shifter polygons separated by target features, such that the run unambiguously alters between a shifter polygon and a target feature. Phase is then assigned by traversing the run in the direction of the run and assigning phase to the shifter polygons by alternating between phase 0 and phase 180. If two shifter polygons are not separated by a target feature, they are not interrelated. Such methods are limited. They work for a run in which the target features extend in the same predetermined direction such that traversing all of the shifter polygons in the run requires moving in only one direction. Such methods also require the data to first be sorted into runs. Sorting therefore adds an extra data processing step. Furthermore, in complex configurations where the target features contain branches or loops, it may not be possible to map the pattern by this technique alone. Therefore, it is desirable to develop more versatile computer methods for phase assignment of shifter polygons in a phase shift lithography mask.
FIG. 2 shows, in a flowchart, one embodiment in accordance with this disclosure of a method of decomposing a set of target features to form an unambiguous mesh of shifter polygons, shown as stage 12 in FIG. 1. FIGS. 3A-3D show pictorially a circuit design with the target features decomposed in accordance with the method of FIG. 2. The decomposition starts in stage 20 (FIG. 2). In stage 22, the target features in the circuit design are �leveled.� Leveling refers to preparing the circuit design data for the decomposition operation. Due to the large size of integrated circuit patterns, the patterns are often represented using a method that minimizes the redundant definition of multiple instances of the same polygons or sets of polygons. The circuit pattern is represented hierarchically, as a tree of multiple references in which each polygon is defined only once. The total pattern definition is created by referring to the placement of each polygon. The placement of each polygon specifies the item to be replicated, the location at which it is to be replicated, and any other transformations to be applied to that placement, such as rotation, change of scale, or reflection. The hierarchy is made of up cells, with the top cells containing the entire pattern and the bottom cells containing only polygon data. A common file format for storing this type of hierarchic data is called GDS. DRC tools distinguish between operations that are performed on the entire hierarchy and operations that are performed at the cell-level only. Cell-level operations can only operate on the polygons in a given cell. Thus, polygons in adjacent cells are ignored, even if the polygons in adjacent cells contact or overlap the polygons in the current cell. Thus, before performing a cell-level operation, the user can �level� the data by incorporating polygons that touch or overlap hierarchically into a common cell. In some embodiments, the data must be leveled because many of the DRC commands used for the decomposition are cell-level commands.
After the target features are leveled in stage 22 (FIG. 2), intersections between different sections of target features which may be problematic, that is, intersections at angles of 225�, 270�, and 315� are located in stage 24. FIG. 3A shows the three types of intersections 40, 41, and 42. In the data layers, these intersections are marked with small squares, or any other shape of marker, placed in the target features at the intersections in stage 26. FIG. 3B shows a target feature 45 after the problematic intersections are marked with squares 48-51 inside the target feature. The distance between the squares is checked in stage 28. If any of the marking squares are closer together than the maximum width of a target feature, that is, a feature small enough that it requires shifter polygons on either side, a polygon is added between the squares in stage 30. FIG. 3C shows a feature intersection with marking squares 48-51 closer together than the maximum width of a target feature. A polygon 52 has been added between squares 48-51.
FIG. 4 is a detailed flowchart of one embodiment of the method of assigning phase to a set of shifter polygons, shown in stage 13 of FIG. 1. FIGS. 5A-5D show pictorially a part of a circuit design with the phase assigned to the shifter polygons in accordance with the method of FIG. 4. Two derived layers, derived from the circuit design, are input into the DRC tool. Layer 101 is a group of shifter polygons without phase assignments. Layer 102 is a group of target features which the shifter polygons surround. The result of the process is a layer of shifter polygons of a first phase (191), a layer of shifter polygons of a second phase (192), and the layer of target features (not shown in the output, identical to layer 102). In stage 110, a first polygon is selected as the starter polygon. The starter polygon is added to the current layer of shifter polygons, called start_here in this embodiment. Shifter polygon 180 of FIG. 5A is selected as the starter polygon in stage 110 and moved to layer start_here. The process for selecting the starter polygon is described in more detail in connection with FIG. 7. In stage 115 (FIG. 4), the DRC tool determines if the start_here layer is empty or if it has unassigned shifter polygons in it. If start_here is not empty, in stage 120 any target features in the pool of unused target features that touch, i.e. that contact any edge of the polygon in the start_here layer, are added to a layer called touch_gates. Target features 181 and 182 in FIG. 5A are identified as the target features in the pool of unused target features that touch shifter polygon 180. Target features 181 and 182 are then added to the touch_gates layer. In stage 125 of FIG. 4, the polygon in the start_here layer is removed from the pool of unassigned polygons. In stage 130, any polygons in the pool of unassigned polygons that are between the target features in the touch_gates layer and the next set of target features selected are added to a layer called cumulate. Shifter polygons 183 and 184 of FIG. 5A are identified as the polygons in the pool of unassigned polygons that touch target features 181 and 182. Polygons 183 and 184 are then added to the cumulate layer.
FIG. 6 illustrates, in a flowchart, stage 130 of FIG. 4 in more detail. In stage 170, the shifter polygons in the pool of unassigned polygons that touch the target features in the touch_gates layer (hereinafter �first polygons�) are added to the cumulate layer. In stage 172, the tool checks to see if the first polygons touch or share any vertices with any other polygons in the pool of unassigned polygons (hereinafter �second polygons�). If the first polygons do not touch or share any vertices with any second polygons, the process returns to stage 135 in FIG. 4. If the first polygons do touch or share vertices with second polygons, the second polygons are added to the cumulate layer in stage 174. The tool then returns to stage 172 and checks to see if the second polygons touch or share any vertices with any other polygons in the pool of unassigned polygons. Stages 172 and 174 repeat until the tool cannot find any more polygons that touch or share vertices with the polygons in the cumulate layer.
The process then returns to stage 115 in FIG. 4. Stage 120 of FIG. 4 adds target features 189 and 190 (FIG. 5C) to the touch_gates layer. Stage 130 adds shifter polygons 193 and 194 (FIG. 5C) to the cumulate layer. Stage 140 adds polygons 193 and 194 (FIG. 5C) to. the phase0 layer. Stage 145 (FIG. 4) adds polygon 188 (FIG. 5B) to the phase1 layer. Stage 150 (FIG. 4) adds target feature 195 (FIG. 5D) to the next_gates layer. Stage 155 (FIG. 4) adds polygon 196 (FIG. 5D) to the start_here layer. The process again returns to stage 115. Since there are no target features in the pool of unused target features adjacent to polygon 196, stages 120, 130, 135, and 140 (FIG. 4) are skipped. In stage 145 (FIG. 4), polygon 196 is added to the phase1 layer. In this embodiment, the output layers, layers 191 and 192, represent actual mask layers. Layers such as start_here, cumulate, touch_gates, and next_gates are derived layers, that is, layers that are created by the computer program performing the shifter polygon phase assignment. The derived layers are created to facilitate manipulating the circuit design data to create the actual mask layers.
FIG. 7 shows selecting a starting polygon in stage 110 of FIG. 4 in more detail. FIG. 8A-8D show the selection of a starting polygon in accordance with the method of FIG. 7. In stage 210 (FIG. 7), a group of target features and shifter polygons connected by those target features are merged into a single polygon. Shifter polygons 271-276 and target features 277-280 of FIG. 8A are merged into a single polygon 282, shown in FIG. 8B. In stage 220 and 230, a vertex of the merged polygon is selected and marked with a seed polygon. The top left vertex of merged polygon 282 of FIG. 8B is marked with a seed polygon 283. In stage 250, the seed polygon is checked to make sure it touches only one shifter polygon. Seed polygon 283 of FIG. 8C is checked to make sure it only touches one shifter polygon. If the seed polygon is touching more than one shifter polygon, the process returns to stage 220 and selects a new vertex of the merged polygon. If the seed polygon is only touching one shifter polygon, that shifter is selected as the starting shifter polygon. Since seed polygon 283 touches only polygon 271 in FIG. 8C, polygon 271 is selected as the starting shifter polygon in stage 260 (FIG. 7). The process ends in stage 270.
9. A string parameter that is set to �yes� or �no� which determines whether decomposition is performed on the data before phases are assigned to the shifter polygons.
FIG. 10C illustrates decomposition module 302 in more detail. Problematic junction identifier 316 identifies target feature junctions with angles between 225� and 315�. Junction marker 317 marks the junctions identified as possibly problematic. Junction deleting element checks if any markers are closer than the maximum width of a target feature and subtracts the marks and the shape between the marks from the target feature if the markers are closer together than the maximum width of a target feature.
An improved implementation includes a module that converts the connectivity relationships established between the phase-shifting polygons and the target features into a special graph-based data structure. In this graph structure, the �nodes� represent one class of feature (i.e. phase shifters) and the connections between the nodes represents the other class (target features). The color mapping is then performed in the graph structure itself, and the resulting phase assignments are passed back to the corresponding phase shifter polygons. This method provides a significant improvement in mapping speed by eliminating the overhead of the geometric select operations on polygon data, and also provides a data structure that is more amenable to analysis for potential mapping conflicts (i.e. odd cycles).
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Pati et al., "Phase-Shifting Masks: Automated Design and Mask Requirements", SPIE-The International Society for Optical Engineering, vol. 2197, pp. 314-327.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7392168 *Jul 2, 2001Jun 24, 2008Yuri GranikMethod of compensating for etch effects in photolithographic processingUS7649612Jan 27, 2006Jan 19, 2010Chartered Semiconductor Manufacturing Ltd.Phase shifting photolithography systemUS8456474 *Feb 19, 2010Jun 4, 2013Alpine Electronics, Inc.Method for rendering outline of polygon and apparatus of rendering outline of polygonUS20100295857 *Feb 19, 2010Nov 25, 2010Hironori OnizawaMethod for Rendering Outline of Polygon and Apparatus of Rendering Outline of Polygon* Cited by examinerClassifications U.S. Classification716/55, 430/396, 430/5International ClassificationG06F17/50, G03F1/00Cooperative ClassificationG03F1/30European ClassificationG03F1/30Legal EventsDateCodeEventDescriptionDec 12, 2012FPAYFee paymentYear of fee payment: 8Apr 28, 2009SULPSurcharge for late paymentApr 28, 2009FPAYFee paymentYear of fee payment: 4Jan 19, 2009REMIMaintenance fee reminder mailedFeb 6, 2003ASAssignmentOwner name: SYNOPSYS, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVANT! 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