Source: http://www.google.com/patents/US8216951?ie=ISO-8859-1&dq=6,243,373
Timestamp: 2014-08-30 03:18:27
Document Index: 19530701

Matched Legal Cases: ['Application No. 06', 'Application No. 10003084', 'Application No. 10002884', 'Application No. 06800414', 'art 2', 'art 1', 'art 1', 'art 2']

Patent US8216951 - Quantum tunneling devices and circuits with lattice-mismatched semiconductor ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsStructures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials....http://www.google.com/patents/US8216951?utm_source=gb-gplus-sharePatent US8216951 - Quantum tunneling devices and circuits with lattice-mismatched semiconductor structuresAdvanced Patent SearchPublication numberUS8216951 B2Publication typeGrantApplication numberUS 12/973,616Publication dateJul 10, 2012Filing dateDec 20, 2010Priority dateSep 27, 2006Also published asUS7875958, US8629047, US20080073641, US20110086498, US20120309113, US20140167098, WO2008039534A2, WO2008039534A3Publication number12973616, 973616, US 8216951 B2, US 8216951B2, US-B2-8216951, US8216951 B2, US8216951B2InventorsZhiyuan Cheng, Calvin SheenOriginal AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (276), Referenced by (3), Classifications (29) External Links: USPTO, USPTO Assignment, EspacenetQuantum tunneling devices and circuits with lattice-mismatched semiconductor structuresUS 8216951 B2Abstract Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.
RELATED APPLICATIONS This application is a divisional of U.S. patent application Ser. No. 11/862,850, filed on Sep. 27, 2007, entitled �Quantum Tunneling Devices and Circuits with Lattice-Mismatched Semiconductor Structures,� which claims the benefit of and priority to U.S. Provisional Application Ser. No. 60/848,037 filed Sep. 27, 2006, and U.S. Provisional Application Ser. No. 60/923,838 filed Apr. 17, 2007; the disclosures of these applications are hereby incorporated by reference in their entireties.
Example 2 Referring to FIG. 21, two RTDs 400 and one MOSFET 1900 may be integrated to form an SRAM (TSRAM) 2100 with heteroepitaxial layers on Si. This circuit unit SRAM 2100 may be constructed with the structure illustrated in FIG. 22, where two RTD (or RITD) devices are integrated on a semiconductor substrate 405 with a conventional n-MOSFET 1900 to construct an SRAM memory cell unit. The RTD or RITD devices may be fabricated in a process flow using ART techniques. The two RTD devices may be connected in series by an underlying doped region 2205, e.g., a p+ Si region defined by implantation. Both RTD devices may be disposed over an n-well 2210 that is electrically isolated from an adjacent p-well 2215 underlying the n-FET. Interconnections (not shown) may be defined between the n-FET and the two RTD devices to form SRAM memory cell unit. The resulting structure illustrated in FIG. 22 show two tunneling structures (in the two RTDs) formed via ART and coupled to a MOSFET 1900, which as illustrated in FIGS. 23, 24 and 25 can be coupled to a terminal (gate, source, or drain) of the transistor.
III. Structures and Processes for Integrating Tunneling Devices and Conventional Devices into Circuit Units on Si or Common Substrates In various integrated circuit units described in II (Integrated Circuit Units with Tunneling Devices and Conventional Devices), the tunneling devices may be integrated with conventional devices by several different structures and processes, using ART techniques in accordance to one aspect of this invention.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4307510Mar 12, 1980Dec 29, 1981The United States Of America As Represented By The Administrator Of The National Aeronautics & Space AdministrationComputer circuit card pullerUS4322253Apr 30, 1980Mar 30, 1982Rca CorporationMethod of making selective crystalline silicon regions containing entrapped hydrogen by laser treatmentUS4370510Sep 26, 1980Jan 25, 1983California Institute Of TechnologySingle crystal interlayerUS4545109Jan 21, 1983Oct 8, 1985Rca CorporationForming ddoped layer on group 3-groups semi insulating material and etchingUS4551394Nov 26, 1984Nov 5, 1985Honeywell Inc.Gallium arsenide on siliconUS4651179Jun 26, 1985Mar 17, 1987Rca CorporationLow resistance gallium arsenide field effect transistorUS4727047Apr 6, 1981Feb 23, 1988Massachusetts Institute Of TechnologyMethod of producing sheets of crystalline materialUS4774205Jun 13, 1986Sep 27, 1988Massachusetts Institute Of TechnologyMonolithic integration of silicon and gallium arsenide devicesUS4789643Sep 16, 1987Dec 6, 1988Mitsubishi Denki Kabushiki KaishaMethod of manufacturing a heterojunction bipolar transistor involving etch and refillUS4826784Nov 13, 1987May 2, 1989Kopin CorporationSelective OMCVD growth of compound semiconductor materials on silicon substratesUS4860081Sep 19, 1985Aug 22, 1989Gte Laboratories IncorporatedSemiconductor integrated circuit structure with insulative partitionsUS4876210Mar 4, 1988Oct 24, 1989The University Of DelawareSolution growth of lattice mismatched and solubility mismatched heterostructuresUS4948456Jun 9, 1989Aug 14, 1990Delco Electronics CorporationConfined lateral selective epitaxial growthUS4963508Feb 22, 1990Oct 16, 1990Daido Tokushuko Kabushiki KaishaMethod of making an epitaxial gallium arsenide semiconductor wafer using a strained layer superlatticeUS5032893Jul 27, 1990Jul 16, 1991Cornell Research Foundation, Inc.Method for reducing or eliminating interface defects in mismatched semiconductor eiplayersUS5034337Aug 29, 1990Jul 23, 1991Texas Instruments IncorporatedMethod of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devicesUS5061644Sep 20, 1990Oct 29, 1991Honeywell Inc.Method for fabricating self-aligned semiconductor devicesUS5079616Feb 11, 1988Jan 7, 1992Gte Laboratories IncorporatedSemiconductor structureUS5091333Sep 7, 1988Feb 25, 1992Massachusetts Institute Of TechnologyMultilayer; interrupting growth temperature controlUS5091767Mar 18, 1991Feb 25, 1992At&T Bell LaboratoriesArticle comprising a lattice-mismatched semiconductor heterostructureUS5093699Mar 12, 1990Mar 3, 1992Texas A & M University SystemGate adjusted resonant tunnel diode device and method of manufactureUS5098850Jun 14, 1990Mar 24, 1992Canon Kabushiki KaishaProcess for producing substrate for selective crystal growth, selective crystal growth process and process for producing solar battery by use of themUS5105247Aug 3, 1990Apr 14, 1992Cavanaugh Marion EQuantum field effect device with source extension region formed under a gate and between the source and drain regionsUS5108947Jan 25, 1990Apr 28, 1992Agfa-Gevaert N.V.Controlling formation of microcracks using shaped mask for crystal depositionUS5156995Apr 12, 1991Oct 20, 1992Cornell Research Foundation, Inc.Method for reducing or eliminating interface defects in mismatched semiconductor epilayersUS5159413Dec 11, 1990Oct 27, 1992Eaton CorporationMonolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrateUS5164359Apr 20, 1990Nov 17, 1992Eaton CorporationMonolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrateUS5166767Jan 19, 1989Nov 24, 1992National Semiconductor CorporationSidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layerUS5223043May 11, 1992Jun 29, 1993The United States Of America As Represented By The United States Department Of EnergyCurrent-matched high-efficiency, multijunction monolithic solar cellsUS5236546Dec 12, 1991Aug 17, 1993Canon Kabushiki KaishaProcess for producing crystal articleUS5238869Jul 27, 1992Aug 24, 1993Texas Instruments IncorporatedMethod of forming an epitaxial layer on a heterointerfaceUS5256594Jun 16, 1989Oct 26, 1993Intel CorporationMasking technique for depositing gallium arsenide on siliconUS5269852May 26, 1992Dec 14, 1993Canon Kabushiki KaishaSemiconductor junctionsUS5269876Feb 25, 1993Dec 14, 1993Canon Kabushiki KaishaVapor deposition of silicon crystalUS5272105Dec 31, 1991Dec 21, 1993Gte Laboratories IncorporatedMethod of manufacturing an heteroepitaxial semiconductor structureUS5281283Dec 4, 1992Jan 25, 1994Canon Kabushiki KaishaGroup III-V compound crystal article using selective epitaxial growthUS5285086Jun 18, 1992Feb 8, 1994At&T Bell LaboratoriesSemiconductor devices with low dislocation defectsUS5295150Dec 11, 1992Mar 15, 1994Eastman Kodak CompanyDistributed feedback-channeled substrate planar semiconductor laserUS5356831Oct 28, 1992Oct 18, 1994Eaton CorporationMethod of making a monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrateUS5403751Jun 20, 1994Apr 4, 1995Canon Kabushiki KaishaProcess for producing a thin silicon solar cellUS5405453Nov 8, 1993Apr 11, 1995Applied Solar Energy CorporationHigh efficiency multi-junction solar cellUS5407491Apr 8, 1993Apr 18, 1995University Of HoustonHigh current density, low electrical resistanceUS5410167Jul 9, 1993Apr 25, 1995Fujitsu LimitedSemiconductor device with reduced side gate effectUS5417180Jul 29, 1993May 23, 1995Rohm Co., Ltd.Method for forming SOI structureUS5427976Mar 26, 1992Jun 27, 1995Nec CorporationMethod of producing a semiconductor on insulating substrate, and a method of forming a transistor thereonUS5432120Nov 19, 1993Jul 11, 1995Siemens AktiengesellschaftMethod for producing a laterally limited single-crystal region with selective epitaxy and the employment thereof for manufacturing a bipolar transistor as well as a MOS transistorUS5438018Dec 7, 1993Aug 1, 1995Fujitsu LimitedMethod of making semiconductor device by selective epitaxial growthUS5461243Oct 29, 1993Oct 24, 1995International Business Machines CorporationSubstrate for tensilely strained semiconductorUS5518953Mar 15, 1994May 21, 1996Rohm Co., Ltd.Method for manufacturing semiconductor device having grown layer on insulating layerUS5528209Apr 27, 1995Jun 18, 1996Hughes Aircraft CompanyMonolithic microwave integrated circuit and methodUS5545586May 13, 1994Aug 13, 1996Nec CorporationMethod of making a transistor having easily controllable impurity profileUS5548129Aug 1, 1995Aug 20, 1996Hughes Aircraft CompanyQuantum well structure with self-aligned gate and method of making the sameUS5589696Oct 14, 1992Dec 31, 1996Nec CorporationTunnel transistor comprising a semiconductor film between gate and source/drainUS5621227Jul 18, 1995Apr 15, 1997Discovery Semiconductors, Inc.Method and apparatus for monolithic optoelectronic integrated circuit using selective epitaxyUS5622891Dec 1, 1994Apr 22, 1997Fujitsu LimitedMethod of manufacturing semiconductor device with reduced side gate effectUS5640022Aug 25, 1994Jun 17, 1997Sanyo Electric Co., Inc.Quantum effect deviceUS5710436Sep 26, 1995Jan 20, 1998Kabushiki Kaisha ToshibaQuantum effect deviceUS5717709Jun 19, 1996Feb 10, 1998Sharp Kabushiki KaishaSemiconductor light-emitting device capable of having good stability in fundamental mode of oscillation, decreasing current leakage, and lowering oscillation threshold limit, and method of making the sameUS5792679Aug 30, 1993Aug 11, 1998Sharp Microelectronics Technology, Inc.Implanting mobility enhancing species into first region of low mobility semiconductor material, selectively oxidizingUS5825049Oct 9, 1996Oct 20, 1998Sandia CorporationResonant tunneling device with two-dimensional quantum well emitter and base layersUS5825240Aug 22, 1997Oct 20, 1998Massachusetts Institute Of TechnologyResonant-tunneling transmission line technologyUS5849077Jun 14, 1996Dec 15, 1998Texas Instruments IncorporatedProcess for growing epitaxial silicon in the windows of an oxide-patterned waferUS5853497Dec 12, 1996Dec 29, 1998Hughes Electronics CorporationHigh efficiency multi-junction solar cellsUS5869845Jun 26, 1997Feb 9, 1999Texas Instruments IncorporatedResonant tunneling memoryUS5883549Jun 20, 1997Mar 16, 1999Hughes Electronics CorporationBipolar junction transistor (BJT)--resonant tunneling diode (RTD) oscillator circuit and methodUS5886385Aug 20, 1997Mar 23, 1999Kabushiki Kaisha ToshibaSemiconductor device and manufacturing method thereofUS5903170Jun 3, 1997May 11, 1999The Regents Of The University Of MichiganDigital logic design using negative differential resistance diodes and field-effect transistorsUS5953361May 13, 1996Sep 14, 1999Siemens AktiengesellschaftDFB laser diode structure having complex optical grating couplingUS5959308Jan 29, 1993Sep 28, 1999Texas Instruments IncorporatedEpitaxial layer on a heterointerfaceUS5966620Nov 14, 1997Oct 12, 1999Canon Kabshiki KaishaProcess for producing semiconductor articleUS5998781Apr 30, 1997Dec 7, 1999Sandia CorporationApparatus for millimeter-wave signal generationUS6011271Jul 9, 1996Jan 4, 2000Fujitsu LimitedSemiconductor device and method of fabricating the sameUS6015979Aug 28, 1998Jan 18, 2000Kabushiki Kaisha ToshibaNitride-based semiconductor element and method for manufacturing the sameUS6049098Apr 26, 1996Apr 11, 2000Nec CorporationBipolar transistor having an emitter region formed of silicon carbideUS6083598Sep 16, 1998Jul 4, 2000Kabushiki Kaisha ToshibaInformation recording medium, method for manufacturing the medium, and apparatus for manufacturing the mediumUS6100106Nov 17, 1998Aug 8, 2000Nec CorporationFabrication of nitride semiconductor light-emitting deviceUS6110813Apr 3, 1998Aug 29, 2000Matsushita Electric Industrial Co., Ltd.Forming insulator film on surface of silicon carbide, the film having opening through which surface of substrate is exposed, depositing metal film in opening, forming ohmic electrode of metal film by heating by irradiation with laser lightUS6111288Mar 17, 1998Aug 29, 2000Kabushiki Kaisha ToshibaQuantum tunneling effect device and semiconductor composite substrateUS6121542May 16, 1997Sep 19, 2000Canon Kabushiki KaishaPhotovoltaic deviceUS6150242Mar 25, 1999Nov 21, 2000Texas Instruments IncorporatedMethod of growing crystalline silicon overlayers on thin amorphous silicon oxide layers and forming by method a resonant tunneling diodeUS6153010Apr 9, 1998Nov 28, 2000Nichia Chemical Industries Ltd.Nitriding; forming recesses; maskingUS6191432Sep 2, 1997Feb 20, 2001Kabushiki Kaisha ToshibaSemiconductor device and memory deviceUS6225650Mar 24, 1998May 1, 2001Mitsubishi Cable Industries, Ltd.Comprises a base substrate, a mask layer, and a gallium nitride group crystal layer grown to cover the mask layer; allows growth of a gallium nitride group crystal in the c axis orientationUS6228691Jun 30, 1999May 8, 2001Intel Corp.Silicon-on-insulator devices and method for producing the sameUS6229153Jun 19, 1997May 8, 2001Wisconsin Alumni Research CorporationHigh peak current density resonant tunneling diodeUS6235547Aug 4, 1999May 22, 2001Fujitsu LimitedSemiconductor device and method of fabricating the sameUS6252261Jun 28, 1999Jun 26, 2001Nec CorporationGaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process thereforUS6252287May 19, 1999Jun 26, 2001Sandia CorporationInGaAsN/GaAs heterojunction for multi-junction solar cellsUS6271551Dec 13, 1996Aug 7, 2001U.S. Philips CorporationSi-Ge CMOS semiconductor deviceUS6274889Sep 21, 1999Aug 14, 2001Matsushita Electric Industrial Co., Ltd.Method for forming ohmic electrode, and semiconductor deviceUS6300650Mar 5, 1999Oct 9, 2001Ricoh Company, Ltd.Photodetectors; refractive indexUS6320220Jul 14, 2000Nov 20, 2001Kabushiki Kaisha ToshibaQuantum tunneling effect device and semiconductor composite substrateUS6325850Oct 15, 1998Dec 4, 2001CENTRE NATIONAL DE LA RECHERCH� SCIENTIFIQUE (CNRS)Method for producing a gallium nitride epitaxial layerUS6339232Sep 20, 2000Jan 15, 2002Kabushika Kaisha ToshibaSemiconductor deviceUS6342404Mar 10, 2000Jan 29, 2002Toyoda Gosei Co., Ltd.Group III nitride compound semiconductor device and method for producingUS6348096Mar 11, 1998Feb 19, 2002Nec CorporationStrain and defects are minimized even during epitaxy using a hetero substrate which has a different lattice constant and thermal expansion coefficient, and which affords an epitaxial layer that resists cracking even where a thick film is grown.US6352942Jun 23, 2000Mar 5, 2002Massachusetts Institute Of TechnologyExposing silicon layer on germanium layer to dry oxygen gas at exposure temperature sufficient to induce oxidation of silicon layer substantially only by thermal energy, for time selected to oxidize only portion of silicon layerUS6362071Apr 5, 2000Mar 26, 2002Motorola, Inc.Method for forming a semiconductor device with an opening in a dielectric layerUS6380051Jun 21, 1999Apr 30, 2002Sharp Kabushiki KaishaLayered structure including a nitride compound semiconductor film and method for making the sameUS7777250 *Mar 23, 2007Aug 17, 2010Taiwan Semiconductor Manufacturing Company, Ltd.Lattice-mismatched semiconductor structures and related methods for device fabrication* Cited by examinerNon-Patent CitationsReference1"Communication pursuant to Article 94(3) EPC," Application No. 06 770 525.1-2203, Applicant: Taiwan Semiconductor Company, Ltd., Feb. 17, 2011, 4 pages.268 Applied Physics Letters 7, 1999, pp. 774-779 (trans. of relevant portions attached).3Ames, "Intel Says More Efficient Chips are Coming," PC World, available at: http://www.pcworld.com/printable/article/id,126044/printable.html (Jun. 12, 2006); 4 pages.4Asano et al., "AlGaInN laser diodes grown on an ELO-GaN substrate vs. on a sapphire substrate," Semiconductor Laser Conference (2000) Conference Digest, IEEE 17th International, 2000, pp. 109-110.5Asaoka, et al., "Observation of 1 f x/noise of GaInP/GaAs triple barrier resonant tunneling diodes, " AIP Conf. Proc., vol. 780, Issue 1, 2005, pp. 492-495.6Ashby, et al., "Low-dislocation-density GaN from a single growth on a textured substrate," Applied Physics Letters, vol. 77, No. 20, Nov. 13, 2000, pp. 3233-3235.7Ashley, et al., "Heternogeneous InSb Quantum Well Transistors on Silicon for Ultra-High Speed, Low Power Logic Applications," 43 Electronics Letters 14, Jul. 2007, 2 pages.8Bai et al., "Study of the Defect Elimination Mechanisms in Aspect Ratio Trapping Ge Growth," Applied Physics Letters, vol. 90, 2007, 3 pages.9Bakkers et al., "Epitaxial Growth on InP Nanowires on Germanium," Nature Materials, vol. 3, Nov. 2004, pp. 769-773.10Baron et al., "Chemical Vapor Deposition of Ge Nanocrystals on SiO2," Applied Physics Letters, vol. 83, No. 7, Aug. 18, 2003, pp. 1444-1446.11Bean et al., "GexSi1-x/Si strained-later Superlattice grown by molecular beam Epitaxy," Journal of Vacuum Science Technology A2 (2), Jun. 1984, pp. 436-440.12Beckett et al., "Towards a reconfigurable nanocomputer platform," ACM International Conference Proceeding Series, vol. 19, 2002, pp. 141-150.13Beltz et al., "A Theoretical Model for Threading Dislocation Reduction During Selective Area Growth," Materials Science and Engineering, A234-236, 1997, pp. 794-797.14Belyaev, et al., "Resonance and current instabilities in AIN/GaN resonant tunneling diodes," 21 Physica E 2-4, 2004, pp. 752-755.15Berg, J., "Electrical Characterization of Silicon Nanogaps," Doktorsavhandlingar vid Chalmers Tekniska Hagskola, 2005, No. 2355, 2 pages.16Bergman et al., "RTD/CMOS Nanoelectronic Circuits: Thin-Film InP-based Resonant Tunneling Diodes Integrated with CMOS circuits," 20 Electron Device Letters 3, 1999, pp. 119-122.17Blakeslee, "The Use of Superlattices to Block the Propagation of Dislocations in Semiconductors," Mat. Res. Soc. Symposium Proceedings 148, 1989, pp. 217-227.18Bogumilowicz et al., "Chemical Vapour Etching of Si, SiGe and Ge with HCL: Applications to the Formation of Thin Relaxed SiGe Buffers and to the Revelation of Threading Dislocations," 20 Semicond. Sci. Tech. 2005, pp. 127-134.19Borland, "Novel Device structures by selective epitaxial growth (SEG)," Electron Devices Meeting, vol. 33, 1987, pp. 12-15.20Bryskiewicz, "Dislocation filtering in SiGe and InGaAs buffer layers grown by selective lateral overgrowth method," Applied Physics Letters, vol. 66, No. 10, Mar. 6, 1995, pp. 1237-1239.21Burenkov et al., "Corner Effect in Double and Triple Gate FinFETs"European solid-state device research, 33rd Conference on Essderc '03 Sep. 16-18, 2003, Piscataway, NJ, USA, IEEE, vol. 16, pp. 135-138, XPo10676716.22Bushroa et al., "Lateral epitaxial overgrowth and reduction in defect density of 3C-SiC on patterned Si substrates," Journal of Crystal Growth, vol. 271, No. 1-2, Oct. 15, 2004, pp. 200-206.23Calado, et al., "Modeling of a resonant tunneling diode optical modulator," University of Algarve, Department of Electronics and Electrical Engineering, 2005, pp. 96-99.24Campo et al., "Comparison of Etching Processes of Silicon and Germanium in SF6-O2 Radio-Frequency Plasma," 13 Journal of Vac. Sci. Tech., B-2, 1995, pp. 235-241.25Cannon et al., "Monolithic Si-based Technology for Optical Receiver Circuits," Proceedings of SPIE, vol. 4999, 2003, pp. 145-155.26Chan et al., "Influence of Metalorganic Sources on the Composition Uniformity of Selectively Grown GaxIn1-xP," Japan. Journal of Applied Physics, vol. 33, 1994, pp. 4812-4819.27Chang et al. "3-D simulation of strained Si/SiGe heterojunction FinFETs" Semiconductor Device Research Symposium, Dec. 10-12, 2003, pp. 176-177.28Chang et al., "Effect of growth temperature on epitaxial lateral overgrowth of GaAs on Si substrate," Journal of Crystal Growth, vol. 174, No. 1-4, Apr. 1997, pp. 196-200.29Chang et al., "Epitaxial Lateral Overgrowth of Wide Dislocation-Free GaAs on Si Substrates," Electrochemical Society Proceedings, vol. 97-21, May 13, 1998, pp. 196-200.30Chau et al., Opportunities and Challenges of III-V Nanoelectronics for Future High-Speed, Low Power Logic Applications, IEEE CSIC Digest, 2005, pp. 17-20.31Chen et al., "Dislocation reduction in GaN thin films via lateral overgrowth from trenches," Applied Physics Letters, vol. 75, No. 14, Oct. 4, 1999, pp. 2062-2063.32Chengrong, et al., "DBRTD with a high PVCR and a peak current density at room temperature," Chinese Journal of Semiconductors vol. 26, No. 10, Oct. 2005, pp. 1871-1874.33Choi et al., "Monolithic Integration GaAs/AlGaAs LED and Si Driver Circuit," 9 Electron Device Letters 10, Oct. 1988, 3 pages.34Choi et al., "Monolithic Integration of GaAs/AlGaAs Double-Heterostructure LEDs and Si MOSFETs," Electron Device Letters, vol. EDL-7, No. 9, Sep. 1986, 3 pages.35Choi et al., "Monolithic Integration of Si MOSFETs and GaAs MESFETs," Electron Device Letters, vol. EDL-7, No. 4, Apr. 1986, 3 pages.36Choi, et al., "Low-voltage low-power K-band balanced RTD-based MMIC VCO," 2006 IEEE, Department of EECS, Korea Advanced Institute of Science and Technology, 2006, pp. 743-746.37Cloutier et al., "Optical gain and stimulated emission in periodic nanopatterned crystalline silicon," Nature Materials, Nov. 2005, 5 pages.38Currie et al., "Carrier Mobilities and Process Stability of Strained Si n- and p-MOSFETs on SiGe Virtual Substrates," J. Vacuum Science Technology, B, vol. 19, No. 6, 2001, pp. 2268-2279.39Dadgar et al., "MOVPE growth of GaN on Si (111) substrates," Journal of Crystal Growth, vol. 248, Feb. 1, 2003, pp. 556-562.40Datta et al., "Silicon and III-V Nanoelectronics," IEEE International Conference on Indium Phosphide & Related Materials, 2005, pp. 7-8.41Datta et al., "Ultrahigh-Speed 0.5 V Supply Voltage In0.7Ga0.3As Quantum-Well Transistors on Silicon Substrate," 28 Electron Device Letters 8, 2007, pp. 685-687.42Davis et al., "Lateral epitaxial overgrowth of and defect reduction in GaN thin films," Lasers and Electro-Optics Society Annual Meeting (1998) LEOS '98. IEEE, vol. 1, Dec. 1-4, 1998, pp. 360-361.43De Boeck et al., "The fabrication on a novel composite GaAs/SiO2 nucleation layer on silicon for heteroepitaxial overgrowth by molecular beam Epitaxy," Material Science and Engineering, B9, 1991, pp. 137-141.44Donaton et al., "Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure," 2006 IEDM, pp. 465-468.45Dong et al., "Selective area growth of InP through narrow openings by MOCVD and its application to inP HBT," Indium Phosphide and Related Materials, International Conference, May 12-16, 2003, pp. 389-392.46Dong, Y., et al, "Selective area growth of InP through narrow openings by MOCVD and its application to InP HBT," 2003 International Conference on Indium Phosphide and Related Materials, May 12-16, 2003, pp. 389-392.47European Patent Office, Extended European Search Report and Search Opinion dated Jan. 26, 2011 in EP Patent Application No. 10003084.0-2203 (9 pages).48European Search Report issued by the European Patent Office on Dec. 15, 2010 in European Patent Application No. 10002884.4 (10 pages).49Examination Report in European Patent Application No. 06800414.2, mailed Mar. 5, 2009, 3 pages.50Fang et al., "Electrically pumped hybrid AlGaInAs-silicon evanescent laser," 14 Optics Express 20, 2006, pp. 9203-9210.51Feltin et al., "Epitaxial lateral overgrowth of GaN on Si (111)," Journal of Applied Physics, vol. 93, No. 1, Jan. 1, 2003, pp. 182-185.52Feng et al., "Integration of Germanium-on Insulator and Silicon Substrate," 27 Electron Device Letters 11, 2006, pp. 911-913.53Fiorenza et al., "Film Thickness Constraints for Manufacturable Strained Silicon CMOS," 19 Semiconductor Science Technology, 2004, p. L4.54Fischer et al., "Elastic stress relaxation in SiGe epilayers on patterned Si substrates," 75 Journal of Applied Physics 1, 1994, pp. 657-659.55Fischer et al., "State of stress and critical thickness of Strained small-area SiGe layers,"Phys. Stat. Sol. (a) vol. 171, 1999, pp. 475-485.56Fitzgerald et al., "Elimination of Dislocations in Heteroepitaxial MBE and RTCVD GexSi1-x Grown on Patterned Si Substrates," Journal of Electronic Materials, vol. 19, No. 9, 1990, pp. 949-955.57Fitzgerald et al., "Epitaxial Necking in GaAs Growth on Pre-patterned Si Substrates," Journal of Electronic Materials, vol. 20, No. 10, 1991, pp. 839-853.58Fitzgerald et al., "Nucleation Mechanisms and the Elimination of Misfit Dislocations at Mismatched Interfaces by Reduction in Growth Areas," Journal of Applied Physics, vol. 65, No. 6, Mar. 15, 1989, pp. 2220-2237.59Fitzgerald et al., "Structure and recombination in InGaAs/GaAs heterostructures," 63 Journal of Applied Physics, vol. 3, 1988, pp. 693-703.60Fitzgerald et al., "Totally relaxed GexSi1-x layers with low threading dislocation densities grown on Si Substrates," vol. 59, Applied Physics Letters 7, 1991, pp. 811-813.61Fitzgerald, "The Effect of Substrate Growth Area on Misfit and Threading Dislocation Densities in Mismatched Heterostructures," Journal of Vacuum Science Technology, vol. 7, No. 4, Jul./Aug. 1989, pp. 782-788.62Gallagher et al., "Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip," 50 IBM J. Research & Dev. 1, Jan. 2006, pp. 5-23A.63Gallas et al., "Influence of Doping on Facet Formation at the SiO2/Si Interface," Surface Sci. 440, 1999, pp. 41-48.64Geppert, "Quantum transistors: toward nanoelectronics," IEEE Spectrum, Sep. 2000, pp. 46-51.65Gibbon et al., "Selective-area low-pressure MOCVD of GaInAsP and related materials on planar InP substrates," Semicond. Sci. Tech. vol. 8, 1993, pp. 998-1010.66Glew et al., "New DFB grating structure using dopant-induced refractive index step," J. Crystal Growth 261, 2004, pp. 349-354.67Golka, et al., "Negative differential resistance in dislocation-free GaN/AlGan double-barrier diodes grown on bulk GaN," 88 Applied Physics Letters 17, Apr. 2006, pp. 172106-1-172106-3.68Goodnick, S.M., "Radiation Physics and Reliability Issues in III-V Compound Semiconductor Nanoscale Heterostructure Devices," Final Technical Report, Arizona State Univ. Dept. Electrical & Computer Eng, 80 pages, 1996-1999.69Gould et al., "Magnetic resonant tunneling diodes as voltage-controlled spin selectors," 241 Phys. Stat. Sol. (B), vol. 3, 2004, pp. 700-703.70Groenert et al., "Monolithic integration of room-temperature cw GaAs/AlGaAs lasers on Si substrates via relaxed graded GeSi buffer layers," 93 Journal of Applied Physics, No. 362, Jan. 2003, pp. 362-367.71Gruber, et al., "Semimagnetic Resonant Tunneling Diodes for Electron Spin Manipulation," Nanostructures: Physics & Technology, 8th International Symposium, 2000, pp. 483-486.72Gustafsson et al., "Cathodoluminescence from relaxed GexSi1-x grown by heteroepitaxial lateral overgrowth," Journal of Crystal Growth 141, 1994, pp. 363-370.73Gustafsson et al., "Investigations of high quality GexSi1-x grown by heteroepitaxial lateral overgrowth using cathodoluminescence," Inst. Phys. Conf. Ser., No. 134, Section 11, Apr. 1993, pp. 675-678.74Hammerschmidt, "Intel to Use Trigate Transistors from 2009 on," EETIMES Online, available at: http://www.eetimes.com/showArticle.jhtml?articleID=189400035 (Jun. 12, 2006). 1 page.75Hasegawa, et al., "Sensing Terahertz Signals with III-V Quantum Nanostructures," Quantum Sensing: Evolution and Revolution from Past to Future, SPIE 2003, pp. 96-105.76Hayafuji et al., Japan, Journal of Applied Physics, vol. 29, 1990, pp. 2371.77Hersee et al., "The Controlled Growth of GaN Nanowires," Nano Letters, vol. 6, No. 8, 2006, pp. 1808-1811.78Hiramatsu et al., "Fabrication and characterization of low defect density GaN using facet-controlled epitaxial lateral overgrowth (FACELO)," Journal of Crystal Growth, vol. 221, Dec. 2000, pp. 316-326.79Hollander et al., "Strain and Misfit Dislocation Density in Finite Lateral Size Si1-xGex/Si Films Grown by Selective.Epitaxy," Thin Solid Films, vol. 292, 1997, pp. 213-217.80Hu et al., "Growth of Well-Aligned Carbon Nanotube arrays on Silicon Substrates Using Porous Alumina Film as a Nanotemplate," 79 Applied Physics Letters 19, 2001, 3 pages.81Huang et al., "Electron and Hole Mobility Enhancement in Strained SOI by Wafer Bonding," 49 IEEE Transactions on.Electron Devices 9, 2002, pp. 1566-1570.82Hydrick et al., "Chemical Mechanical Polishing of Epitaxial Germanium on Si02-patterned Si(001) Substrates," ECS Transactions, 16 (10), 2008, (pp. 237-248).83Intel Press Release, "Inters Tri-Gate Transistor to Enable Next Era in Energy-Efficient Performance," Intel Corporation (Jun. 12, 2006). 2 pages.84Intel to Develop Tri-Gate Transistors Based Processors, available at: http://news.techwhack.com/3822/tri-gate-transistors/ (Jun. 13, 2006) 6 pages.85International Preliminary Report on Patentability for International Application No. PCT/US2006/019152 mailed Nov. 29, 2007, 2 pages.86International Preliminary Report on Patentability for International Application No. PCT/US2006/029247 mailed Feb. 7, 2008, 12 pages.87International Preliminary Report on Patentability for International Application No. PCT/US2006/033859 mailed Mar. 20, 2008, 14 pages.88International Preliminary Report on Patentability for International Application No. PCT/US2007/019568 mailed Mar. 19, 2009, 10 pages.89International Preliminary Report on Patentability for International Application No. PCT/US2007/020181 mailed Apr. 2, 2009, 9 pages.90International Preliminary Report on Patentability for International Application No. PCT/US2007/020777 mailed Apr. 9, 2009, 12 pages.91International Preliminary Report on Patentability for International Application No. PCT/US2007/021023 mailed Apr. 9, 2009, 8 pages.92International Preliminary Report on Patentability for International Application No. PCT/US2007/022392 mailed Apr. 30, 2009, 14 pages.93International Search Report and Written Opinion for International Application No. PCT/US2006/019152 mailed Oct. 19, 2006, 11 pages.94International Search Report and Written Opinion for International Application No. PCT/US2006/029247 mailed May 7, 2007, 19 pages.95International Search Report and Written Opinion for International Application No. PCT/US2006/033859 mailed Sep. 12, 2007, 22 pages.96International Search Report and Written Opinion for International Application No. PCT/US2007/007373, dated Oct. 5, 2007, 13 pages.97International Search Report and Written Opinion for International Application No. PCT/US2007/019568 mailed Feb. 6, 2008, 13 pages.98International Search Report and Written Opinion for International Application No. PCT/US2007/020181 mailed Jan. 25, 2008, 15 pages.99International Search Report and Written Opinion for International Application No. PCT/US2007/020777 mailed Feb. 8, 2008, 18 pages.100International Search Report and Written Opinion for International Application No. PCT/US2007/021023 mailed Jun. 6, 2008, 10 pages.101International Search Report and Written Opinion for International Application No. PCT/US2007/022392 mailed Apr. 11, 2008, 20 pages.102International Search Report and Written Opinion for International Application No. PCT/US2008/068377, mailed Jul. 6, 2009, 19 pages.103International Search Report for International Application No. PCT/US2006/019152, mailed May 17, 2005. 11 pages.104International Technology Roadmap for Semiconductors- Front End Processes, pp. 1-62 (2005).105Ipri et al., "Mono/Poly technology for fabricating low-capacitance CMOS integrated circuits," Electron Devices, IEEE Transactions, vol. 35, No. 8, Aug. 1988 pp. 1382-1383.106Ishibashi, et al., "3rd Topical Workshop on Heterostructure Microelectronics for Information Systems Applications," Aug.-Sep. 1998, 115 pages.107Ishitani et al., "Facet Formation in Selective Silicon Epitaxial Growth," 24 Japan, Journal of Applied Physics, vol. 10, 1985, pp. 1267-1269.108Ismail et al., "High-quality GaAs on Sawtooth-patterned Si Substrates," 59 Applied Physics Letters 19, 1991, pp. 2418-2420.109Jain et al., "Stresses in strained GeSi stripes and quantum structures: calculation using the finite element method and determination using micro-Raman and other measurements," Thin Solid Films 292, 1997, pp. 218-226.110Jeong, et al., "Performance improvement of InP-based differential HBT VCO using the resonant tunneling diode," 2006 International Conf. on Indium Phosphide and Related Mat. Conf. Proc., pp. 42-45.111Ju et al., "Epitaxial lateral overgrowth of gallium nitride on silicon substrate," Journal of Crystal Growth, vol. 263, No. 1-4, Mar. 1, 2004, pp. 30-34.112Kamins et al., "Kinetics of Selective Epitaxial Depostion of Si1-xGex," Hewlett-Packard Company, Palo Alto, CA, Appl. Phys. Lett. 61 (6), Aug. 10, 1992 (pp. 669-671).113Kamiyama, et al., "UV laser diode with 350.9-nm-lasing wavelength grown by hetero-epitaxial-lateral overgrowth technology," Selected Topics in Quantum Electronics, IEEE Journal of Selected Topics in Quantum Electronics, vol. 11, No. 5, Sep.-Oct. 2005, pp. 1069-1073.114Kamiyama, et al., "UV light-emitting diode fabricated on hetero-ELO-grown AI0.22Ga0.78N with low dislocation density," Physica Status Solidi A, vol. 192, No. 2, Aug. 2002, pp. 296-300.115Kawai, et al., "Epitaxial Growth of InN Films and InN Nano-Columns by RF-MBE," The Institute of Electronics, Information and Communication Engineers, Gijutsu Kenkyu, vol. 13, No. 343 (CPM2003 102-116), 2003, pp. 33-37.116Kazi et al., "Realization of GaAs/AlGaAs Lasers on Si Substrates Using Epitaxial Lateral Overgrowth by Metalorganic Chemical Vapor Deposition," Japan, Journal of Applied Physics, vol. 40, 2001, pp. 4903-4906.117Kidoguchi et al., "Air-bridged lateral epitaxial overgrowth of GaN thin Films," Applied Physics Letters, vol. 76, No. 25, Jun. 19, 2000, pp. 3768-3770.118Kim et al., "GaN nano epitaxial lateral overgrowth on holographically patterned substrates," School of Physics and Inter-University Semiconductor Research Center, Seoul National University, Aug. 25-27, 2003, pp. 27-28.119Kim et al., "Silicon-Based Field-Induced Band-to-Band Tunneling Effect Transistor," IEEE Electron Device Letters, No. 25, No. 6, 2004, pp. 439-441.120Kimura et al., "Vibronic Fine Structure Found in the Blue Luminescence from Silicon Nanocolloids," Japan, Journal of Applied Physics, vol. 38, 1999, pp. 609-612.121Klapper, "Generation and Propagation of Dislocations During Crystal Growth," Mat. Chem. and Phys. vol. 66, 2000, pp. 101-109.122Knall et al., "Threading Dislocations in GaAs Grown with Free Sidewalls on Si mesas," Journal of Vac. Sci. Technol. B, vol. 12, No. 6, Nov./Dec. 1994, pp. 3069-3074.123Kollonitsch, et al., "Improved Structure and Performance of the GaAsSb/InP Interface in a Resonant Tunneling Diode," Journal of Crystal Growth, vol. 287, 2006, pp. 536-540.124Krishnamurthy, et al., "I-V characteristics in resonant tunneling devices: Difference Equation Method," Journal of Applied Physics, vol. 84, Issue 9, Condensed Matter: Electrical and Magnetic Properties (PACS 71-76), 1998, 9 pages.125Krost et al., "GaN-based Optoelectronics on Silicon Substrates," Materials Science & Engineering, B93, 2002, pp. 77-84.126Kusakabe, K. et al., Characterization of Overgrown GaN layers on Nano-Columns Grown by RF-Molecular Beam Epitaxy, Japan, Journal of Applied Physics, Part 2, vol. 40, No. 3A, 2001, pp. L192-L194.127Kushida et al., "Epitaxial growth of PbTiO3 films on SrTiO3 by RF magnetron sputtering," Ultrasonics, Ferroelectrics and Frequency Control, IEEE Transactions on Ultrasonics Ferroelectrics and Frequency Control, vol. 38, No. 6, Nov. 1991, pp. 656-662.128Kwok K. Ng, "Resonant-Tunneling Diode," Complete Guide to Semiconductor Devices, Chapter 10. Nov. 3, 2010, pp. 75-83.129Kwok, "Barrier-Injection Transit Time Diode, Complete Guide to Semiconductor Devices," 2nd ed., Chapter 18, 2002, pp. 137-144.130Lammers, "Trigate and High-k stack up vs. planar," EETIMES Online, available at: http://www.eetimes.com/showArticle.jhtml?articleID=188703323&pgno=2&printable=true (Jun. 12, 2006). 2 pages.131Langdo et al., "High Quality Ge on Si by Epitaxial Necking," Applied Physics Letters, vol. 76, No. 25, Jun. 19, 2000, pp. 3700-3702.132Langdo, "Selective SiGe Nanostructures," PhD Thesis, Massachusetts Institute of Technology, Jun. 2001, 215 pages.133Lee et al., "Growth of GaN on a nanoscale periodic faceted Si substrate by metal organic vapor phase epitaxy," Compound Semiconductors: Post-Conference Proceedings, Aug. 25-27, 2003, pp. 15-21.134Lee et al., "Strain-relieved, Dislocation-free InxGa1-xAs/GaAs(001) Heterostructure by Nanoscale-patterned Growth," Applied Physics Letters, vol. 85, No. 18, Nov. 1, 2004, pp. 4181-4183.135Li et al., "Defect Reduction of GasAs Epitaxy on Si (001) Using Selective Aspect Ratio Trapping," 91 Applied Physics Letters, 2007, pp. 021114-1-021114-3.136Li et al., "Heteroepitaxy of High-quality Ge on Si by Nanoscale Ge seeds Grown through a Thin Layer of SiO2," Applied Physics Letters, vol. 85, No. 11, Sep. 13, 2004, pp. 1928-1930.137Li et al., "Monolithic Integration of GaAs/InGaAs Lasers on Virtual Ge Substrates via Aspect-Ratio Trapping," Journal of the Electrochemical Society, vol. 156, No. 7, 2009, pp. H574-H578.138Li et al., "Morphological Evolution and Strain Relaxation of Ge Islands Grown on Chemically Oxidized Si (100) by Molecular-Beam Epitaxy," Journal of Applied Physics, vol. 98, 2005, pp. 073504-1-073504-8.139Li et al., "Selective Growth of Ge on Si (100) through Vias of Si02 Nanotemplate Using Solid Source Molecular Beam Epitaxy," Applied Physics Letters, vol. 83, No. 24, Dec. 15, 2003, pp. 5032-5034.140Liang et al., "Critical Thickness enhancement of Epitaxial SiGe films Grown on Small Structures," Journal of Applied Physics, vol. 97, 2005, pp. 043519-1-043519-7.141Lim et al., "Facet Evolution in Selective Epitaxial Growth of Si by cold-wall ultrahigh vacuum chemical vapor deposition," Journal of Vac. Sci. Tech., vol. B 22, No. 2, 2004, pp. 682.142Liu et al., "High Quality Single-crystal Ge on Insulator by Liquid-phase Epitaxy on Si Substrates," Applied Physics Letters, vol. 84, No. 14, Apr. 4, 2004, pp. 2563-2565.143Liu et al., "Rapid Melt Growth of Germanium Crystals with Self Aligned Microcrucibles on Si Substrates," Journal of the Electrochemical Society, vol. 152, No. 8, 2005, pp. G688-G693.144Loo et al., "Successful Selective Epitaxial Si1-xGex Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications," 150 Journal of Electrochemical Society 10, 2003, pp. G638-G647.145Lourdudoss et al., "Semi-insulating epitaxial layers for optoelectronic devices," Semiconducting and Insulating Materials Conference, SIMC-XI, 2000, pp. 171-178.146Luan et al., "High-quality Ge Epilayers on Si with Low Threading-dislocation Densities," Applied Physics Letters, vol. 75, No. 19, Nov. 8, 1999, pp. 2909-2911.147Luan, "Ge Photodetectors for Si Microphotonics," PhD Thesis, Massachusetts Institute of Technology, Department of Materials Science & Engineering, Jan. 12, 2001, 155 pages.148Lubnow et al., "Effect of III/V-Compound Epitaxy on Si Metal-Oxide-Semiconductor Circuits," Japan, Journal of Applied Physics, vol. 33, 1994, pp. 3628-3634.149Luo et al., Enhancement of (IN,Ga)N Light-Emitting Diode Performance by Laser Liftoff and Transfer From Sapphire to Silicon, IEEE Photonics Technology Letters, vol. 14, No. 10, 2002, pp. 1400-1402.150Luryi et al., "New Approach to the High Quality Epitaxial Growth of Latticed-Mismatched Materials," Applied Physics Letters, vol. 49, No. 3, Jul. 21, 1986, pp. 140-142.151Ma, et al., "A small signal equivalent circuit model for resonant tunneling diode," Chinese Physics Letters, vol. 23, No. 8, Aug. 2006, pp. 2292-2295.152Ma, et al., "Fabrication of an AlAs/In0.53/Ga0.47/As/InAs resonant tunneling diode on InP substrate for high-speed circuit applications," 27 Chinese J. Semiconductors 6, Jun. 2006, pp. 959-962.153Maekawa, et al., "High PVCR Si/Si1-x/Gex DW RTD formed with a new triple-layer buffer," Materials Science in Semiconductor Processing, vol. 8, 2005, pp. 417-421.154Maezawa, et al., "InP-based resonant tunneling diode/HEMT integrated circuits for ultrahigh-speed operation," IEEE Nagoya University, Institute for Advanced Research, 2006, pp. 252-257.155Maezawa, et al., "Metamorphic resonant tunneling diodes and its application to chaos generator ICs,"44 Jap. J. Applied Physics, Part 1, No. 7A, Jul. 2005, pp. 4790-4794.156Martinez et al., "Characterization of GaAs Conformal Layers Grown by Hydride Vapour Phase Epitaxy on Si Substrates by Microphotoluminescence Cathodoluminescence and MicroRaman," Journal of Crystal Growth, vol. 210, 2000, pp. 198-202.157Matsunaga et al., "A New Way to Achieve Dislocation-Free Heteroepitaxial Growth by Molecular Beam Epitaxy: Vertical Microchannel Epitaxy," Journal of Crystal Growth, vol. 237-239, 2002, pp. 1460-1465.158Matthews et al., "Defects in Epitaxial Multilayers�Misfit Dislocations," Journal of Crystal Growth, vol. 27, 1974, pp. 118-125.159Monroy, et al., "High UV/visible Contrast Photodiodes Based on Epitaxial Lateral Overgrown GaN layers," Electronics Letters, vol. 35, No. 17, Aug. 19, 1999, pp. 1488-1489.160Nakano et al., "Epitaxial Lateral Overgrowth of AIN Layers on Patterned Sapphire Substrates," Source: Physica Status Solidi A, vol. 203, No. 7, May 2006, pp. 1632-1635.161Nam et al., "Lateral Epitaxy of Low Defect Density GaN Layers via Organometallic Vapor Phase Epitaxy," Applied Physics Letters, vol. 71, No. 18, Nov. 3, 1997, pp. 2638-2640.162Naoi et al., "Epitaxial Lateral Overgrowth of GaN on Selected-area Si (111) Substrate with Nitrided Si Mask," Journal of Crystal Growth, vol. 248, 2003, pp. 573-577.163Naritsuka et al., "InP Layer Grown on (001) Silicon Substrate by Epitaxial Lateral Overgrowth," Japan, Journal of Applied Physics, vol. 34, 1995, pp. L1432-L1435.164Neudeck, et al., "Novel silicon Epitaxy for advanced MOSFET devices," Electron Devices Meeting, IEDM Technical Digest International, 2000, pp. 169-172.165Neumann et al., "Growth of III-V Resonant Tunneling Diode on Si Substrate with LP-MOVPE," Journal of Crystal Growth, vol. 248, 2003, pp. 380-383.166Noborisaka, J., et al., "Catalyst-free growth of GaAs nanowires by selective-area metalorganic vapor-phase epitaxy," Applied Physics Letters, vol. 86, May 16, 2005, pp. 213102-1-213102-3.167Noborisaka, J., et al., "Fabrication and characterization of freestanding GaAs/AlGaAs core-shell nanowires and AlGaAs nanotubes by suing selective-area metalorganic vapor phase epitaxy," Applied Physics Letters, vol. 87, Aug. 24, 2005, pp. 093109-1-093109-3.168Noda, et al., "Current-voltage characteristics in double-barrier resonant tunneling diodes with embedded GaAs quantum rings," Physica E 32, 2006, pp. 550-553.169Norman, et al., "Characterization of MOCVD Lateral Epitaxial Overgrown III-V Semiconductor Layers on GaAs Substrates," Compound Semiconductors, Aug. 25-27, 2003, pp. 45-46.170Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority for PCT/US2010/029552, Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., May 26, 2010, 14 pages.171Oehrlein et al., "Studies of the Reactive Ion Etching of SiGe Alloys," J. Vac. Sci. Tech, A9, No. 3, May/Jun. 1991, pp. 768-774.172Orihashi, et al., "Experimental and theoretical characteristics of sub-terahertz and terahertz oscillations of resonant tunneling diodes integrated with slot antennas," 44 Jap. J. Applied Physics, Part 1, No. 11, Nov. 2005, pp. 7809-7815.173Pae, et al., "Multiple Layers of Silicon-on-Insulator Islands Fabrication by Selective Epitaxial Growth," Electron Device Letters, IEEE, vol. 20, No. 5, May 1999, pp. 194-196.174Parillaud et al., "High Quality InP on Si by Conformal Growth," Applied Physics Letters, vol. 68, No. 19, May 6, 1996, pp. 2654-2656.175Park et al., "Defect Reduction and its Mechanism of Selective Ge Epitaxy in Trenches on Si(001) Substrates Using.Aspect Ratio Trapping," Mat. Res. Society Symp. Proc., vol. 994, 2007, 6 pages.176Park et al., "Defect Reduction of Selective Ge Epitaxy in Trenches on Si (001) Substrates Using Aspect Ratio Trapping," Applied Physics Letters 90, 052113, Feb. 2, 2007, 3 pages.177Park et al., "Fabrication of Low-Defectivity, Compressively Strained Geon Si0.2Ge0.8 Structures Using Aspect Ratio Trapping," Journal of the Electrochemical Society, vol. 156, No. 4, 2009, pp. H249-H254.178Park et al., "Growth of Ge Thick Layers on Si (001) Substrates Using Reduced Pressure Chemical Vapor Deposition," 45 Japan, Journal of Applied Physics, vol. 11, 2006, pp. 8581-8585.179Partial International Search for International Application No. PCT/US2006/033859 mailed Jun. 22, 2007, 7 pages.180Partial International Search Report for International Application No. PCT/US2008/004564 completed Jul. 22, 2009, mailed Oct. 16, 2009, 5 pages.181Partial International Search Report for International Application No. PCT/US2008/068377, completed Mar. 19, 2008, mailed Apr. 22, 2008, 3 pages.182PCT International Search Report of PCT/US2009/057493, from PCT/ISA/210, mailed Mar. 22, 2010, Applicant: Amberwave System Corporation et al., 2 pages.183Pidin et al., "MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer for 65-nm Technology Node," Symposium on VLSI Technology, Dig. Tech. Papers, 2004, pp. 54-55.184Piffault et al., "Assessment of the Strain of InP Films on Si Obtained by HVPE Conformal Growth," Indium Phosphide and Related Materials, Conference Proceedings, Sixth International Conference on Mar. 27-31, 1994, pp. 155-158.185Pribat et al., "High Quality GaAs on Si by Conformal Growth," Applied Physics Letters, vol. 60, No. 17, Apr. 27, 1992, pp. 2144-2146.186Prost, ed. "QUDOS Technical Report," 2002-2004, 77 pages.187Prost, et al., "High-speed InP-based resonant tunneling diode on silicon substrate, Proceedings of the 31st European Solid-State Device Research Conf.," 2005, pp. 257-260.188Radulovic, et al., "Transient Quantum Drift-Diffusion Modelling of Resonant Tunneling Heterostructure Nanodevices," Physics of Semiconductors: 27th International Conference on the Physics of Semiconductors�ICPS-27, Jun. 2005 AIP Conf. Proc., pp. 1485-1486.189Reed et al., "Realization of a Three-Terminal Resonant Tunneling Device: The Bipolar Quantum Resonant Tunneling Transistor," 54 Applied Physics Letters 11, 1989, p. 1034.190Ren et al., "Low-dislocation-density, Nonplanar GaN Templates for Buried Heterostructure Lasers Grown by Lateral Epitaxial Overgrowth," Applied Physics Letters, vol. 86, No. 11, Mar. 14, 2005, pp. 111901-1-3.191Rim et al., "Enhanced Hole Mobilities in Surface-Channel Strained-Si p-MOSFETs," 1995 IEDM, pp. 517-520.192Rim et al., "Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs," IEDM Tech. Dig., 2003, pp. 49-52.193Ringel et al., "Single-junction InGaP/GaAs Solar Cells Grown on Si Substrates with SiGe Buffer Layers," Prog. Photovolt., Res. & Applied, vol. 10, 2002, pp. 417-426.194Rosenblad et al., "A Plasma Process for Ultrafast Deposition of SiGe Graded Buffer Layers," 76 Applied Physics Letters 4, 2000, pp. 427-429.195Sakai, "Defect Structure in Selectively Grown GaN Films with Low Threading Dislocation Density," Applied Physics Letters 71, vol. 16, 1997, pp. 2259-2261.196Sakai, "Transmission Electron Microscopy of Defects in GaN Films Formed by Epitaxial Lateral Overgrowth," 73 Applied Physics Letters 4, 1998, pp. 481-483.197Sakawa et al., "Effect of Si Doping on Epitaxial Lateral Overgrowth of GaAs on GaAs-Coated Si Substrate," Japan, Journal of Applied Physics, vol. 31, 1992, pp. L359-L361.198Sass, et al., "Strain in GaP/GaAs and GaAs/GaP resonant tunneling heterostructures," Journal of Crystal Growth, vol. 248, Feb. 2003, pp. 375-379.199Schaub, et al., "Resonant-Cavity-Enhanced High-Speed Si photodiode Grown by Epitaxial Lateral Overgrowth," Photonics Technology Letters, IEEE, vol. 11, No. 12, Dec. 1999, pp. 1647-1649.200Seabaugh et al., "Promise of Tunnel Diode Integrated Circuits," Tunnel Diode and CMOS/HBT Integration Workshop, Naval Research Laboratory, Dec. 9, 1999, 13 pages.201Shahidi, et al., "Fabrication of CMOS on Ultrathin SOI Obtained by Epitaxial Lateral Overgrowth and Chemical-Mechanical Polishing," Electron Devices Meeting, Technical Digest, International, Dec. 9-12, 1990, pp. 587-590.202Shichijo et al., "Co-Integration of GaAs MESFET & Si CMOS Circuits," 9 Elec. Device Letters 9, Sep. 1988, pp. 444-446.203Shubert, E.F., "Resonant tunneling diode (RTD) structures," Rensselear Polytechnic Institute, 2003, pp. 1-14.204Siekkinen, et al., "Selective Epitaxial Growth Silicon Bipolar Transistors for Material Characterization," Electron Devices, IEEE Transactions on Electron Devices, vol. 35, No. 10, Oct. 1988, pp. 1640-1644.205Su et al., "Catalytic Growth of Group III-nitride Nanowires and Nanostructures by Metalorganic Chemical Vapor Deposition," Applied Physics Letters, vol. 86, 2005, pp. 013105-1-013105-3.206Su et al., "New Planar Self-Aligned Double-Gate Fully-depleted P-MOSFETs Using Epitaxial Lateral Overgrowth (ELO) and selectively grown source/drain (S/D)," 2000 IEEE Int'l SOI Conf., pp. 110-111.207Sudirgo et al., "Si-Based Resonant Interband Tunnel Diode/CMOS Integrated Memory Circuits," Rochester Institute of Technology, IEEE, 2006, pp. 109-112.208Suhara, et al, "Characterization of argon fast atom beam source and its application to the fabrication of resonant tunneling diodes," 2005 International Microprocesses and Nanotechnology Conf. Di. of Papers, 2005, pp. 132-133.209Sun et al., "InGaAsP Multi-Quantum Wells at 1.5 /splmu/m Wavelength Grown on Indium Phosphide Templates on Silicon," Indium Phosphide and Related Materials, May 12-16, 2003, pp. 277-280.210Sun et al., "Room-temperature observation of electron resonant tunneling through InAs/AlAs quantum dots," 9 Electrochemical and Solid-State Letters 5, May 2006, pp. G167-G170.211Sun et al., "Selective Area Growth of InP on InP Precoated Silicon Substrate by Hydride Vapor Phase epitaxy," Indium Phosphide and Related Materials Conference, IPRM. 14th, 2002, pp. 339-342.212Sun et al., "Sulfur Doped Indium Phosphide on Silicon Substrate Grown by Epitaxial Lateral Overgrowth," Indium Phosphide and Related Materials 16th IPRM, May 31-Jun. 4, 2004, pp. 334-337.213Sun et al., "Temporally Resolved Growth of InP in the Opening Off-Oriented from [110] Direction," Idium Phosphide and Related Materials, Conference Proceedings, 2000 International Conference, pp. 227-230.214Sun et al., "Thermal Strain in Indium Phosphide on Silicon Obtained by Epitaxial Lateral Overgrowth," 94 Journal of Applied Physics 4, 2003, pp. 2746-2748.215Sun et al., Electron resonant tunneling through InAs/GaAs quantum dots embedded in a Schottky diode with an AlAs insertion layer, 153 J. Electrochemical Society 153, 2006, pp. G703-G706.216Suryanarayanan et al., "Microstructure of Lateral Epitaxial Overgrown InAs on (100) GaAs Substrates," Applied Physics Letters, vol. 83, No. 10, Sep. 8, 2003, pp. 1977-1979.217Suzuki, et al., "Mutual injection locking between sub-THz oscillating resonant tunneling diodes," Japan Science and Technology Agency, IEEE, Joint 30th International Conference on Infrared and Millimeter Waves & 13th International Conference on Terahertz Electronics, 2005, pp. 150-151.218Takasuka et al., "AlGaAs/InGaAs DFB Laser by One-Time Selective MOCVD Growth on a Grating Substrate," 43 Japan, Journal of Applied Physics, 4B, 2004, pp. 2019-2022.219Takasuka et al., "InGaAs/AlGaAs Quantum Wire DFB Buried HeteroStructure Laser Diode by One-Time Selective MOCVD on Ridge Substrate," 44 Japan, Journal of Applied Physics, 4B, 2005, pp. 2546-2548.220Tamura et al., "Heteroepitaxy on High-Quality GaAs on Si for Optical Interconnections on Si Chip," Proceedings of the SPIE, vol. 2400, 1995, pp. 128-139.221Tamura et al., "Threading Dislocations in GaAs on Pre-patterned Si and in Post-patterned GaAs on Si," Journal of Crystal Growth, vol. 147, 1995, pp. 264-273.222Tanaka et al., "Structural Characterization of GaN Lateral Overgrown on a (111) Si Substrate," Applied Physics Letters, vol. 79, No. 7, Aug. 13, 2001, pp. 955-957.223Thean et al., "Uniaxial-Biaxial Hybridization for Super-Critical Strained-Si Directly on Insulator (SC-SSOI) PMOS with Different Channel Orientations," IEEE, 2005, pp. 1-4.224Thelander, et al., "Heterostructures incorporated in one-dimensional semiconductor materials and devices," Physics of Semiconductors, vol. 171, 2002, 1 page. Abstract Only.225Thompson et al., "A Logic Nanotechnology Featuring Strained-Silicon," 25 IEEE Electron Device Letters 4, 2004, pp. 191-193.226Ting, et al., "Modeling Spin-Dependent Transport in InAS/GaSb/AlSb Resonant Tunneling Structures," 1 J. Computational Electronics, 2002, pp. 147-151.227Tomiya et al., "Dislocation Related Issues in the Degradation of GaN-Based Laser Diodes," Selected Topics in Quantum Electronics, IEEE Journal of Selected Topics in Quantum Electronics, vol. 10, No. 6, Nov./Dec. 2004, pp. 1277-1286.228Tomiya, "Dependency of crystallographic tilt and defect distribution of mask material in epitaxial lateral overgrown GaN layers," Applied Physics Letters vol. 77, No. 5, pp. 636-638.229Tran et al., "Growth and Characterization of InP on Silicon by MOCVD," Journal of Crystal Growth, vol. 121, 1992, pp. 365-372.230Tsai, et al., "InP/InGaAs resonant tunneling diode with six-route negative differential resistances," 13th European Gallium Arsenide and other Compound Semiconductors Application Symp., 2006, pp. 421-423.231Tsang et al., "The heteroepitaxial Ridge-Overgrown Distributed Feedback Laser," Quantum Electronics, IEEE Journal of Quantum Electronics, vol. 21, No. 6, Jun. 1985, pp. 519-526.232Tsaur, et al., "Low-Dislocation-Density GaAs epilayers Grown on Ge-Coated Si substrates by Means of Lateral Epitaxial Overgrowth," Applied Physics Letters, vol. 41, No. 15, Aug. 1982, pp. 347-349.233Tseng et al., "Effects of Isolation Materials on Facet Formation for Silicon Selective Epitaxial Growth," 71 Applied Physics Letters 16, 1997, pp. 2328.234Tsuji et al., Selective Epitaxial Growth of GaAs on Si with Strained Sort-period Superlattices by Molecular Beam Epitaxy under Atomic Hydrogen Irradiation, J. Vac. Sci. Technol. B, vol. 22, No. 3, May/Jun. 2004, pp. 1428-1431.235Ujiie, et al., Epitaxial Lateral Overgrowth of GaAs on a Si Substrate, 28, Japan, Journal of Applied Physics, vol. 3, Mar. 1989, pp. L337-L339.236Usuda et al., "Strain Relaxation of Strained-Si Layers on SiGe-on-Insulator (SGOI) Structures After Mesa Isolation," Applied Surface Science, vol. 224, 2004, pp. 113-116.237Usui et al., "Thick GaN Epitaxial Growth with Low Dislocation Density by Hydride Vapor Phase Epitaxy," vol. 36, Japan, Journal of Applied Physics, 1997, pp. L899-L902.238Vanamu et al., "Epitaxial Growth of High-Quality Ge Films on Nanostructured Silicon Substrates," Applied Physics Letters, vol. 88, 2006, pp. 204104.1-204-104.3.239Vanamu et al., "Growth of High Quality Ge/Si1-xGex on Nano-scale Patterned Si Structures," J. Vac. Sci. Technology. B, vol. 23, No. 4, Jul./Aug. 2005, pp. 1622-1629.240Vanamu et al., "Heteroepitaxial Growth on Microscale Patterned Silicon Structures," Journal of Crystal Growth, vol. 280, 2005, pp. 66-74.241Vanamu et al., "Improving Ge Si5Ge1-x Film Quality through Growth onto Patterned Silicon Substrates," Advances in Electronics Manufacturing Technology, Nov. 8, 2004, pp. 1-4.242Vescan et al., "Lateral Confinement by Low Pressure Chemical Vapor Deposition-Based Selective Epitaxial Growth of Si1-xGex/Si Nanostructures," No. 81, Journal of Applied Physics 10, 1997, pp. 6709-6715.243Vetury et al., "First Demonstration of AlGaN/GaN Heterostructure Field Effect Transistor on GaN Grown by Lateral Epitaxial Overgrowth (ELO)," Inst. Phys. Conf. Ser. No. 162: Ch. 5, Oct. 1998, pp. 177-183.244Walker, et al., "Magnetotunneling spectroscopy of ring-shaped (InGa)As quantum dots: Evidence of excited states with 2pz character," 32 Physica E 1-2, May 2006, pp. 57-60.245Wang et al, "Fabrication of Patterned Sapphire Substrate by Wet Chemical Etching for Maskless Lateral Overgrowth of GaN," Journal of Electrochemical Society, vol. 153, No. 3, Mar. 2006, pp. C182-C185.246Watanabe, et al., "Fluoride resonant tunneling diodes on Si substrates," IEEE International Semiconductor Device Research Symp. Dec. 2005, pp. 177-178.247Wernersson et al., "InAs Epitaxial Lateral Growth of W Marks," Journal of Crystal Growth, vol. 280, 2005, pp. 81-86.248Williams et al., "Etch Rates for Micromachining Processing�Part II," Journal of Microelectromechanical Systems, vol. 4, 1996, pp. 761-778.249Williams et al., "Etch Rates for Micromachining Processing�Part II," Journal of Microelectromechnical Systems, vol. 5, No. 4, Dec. 1996, pp. 256-269.250Wu et al., "Enhancement-mode InP n-channel metal-oxide-semiconductor field-effect-transistors with atomic-layer-deposited Al2O3 dielectrics," Applied Physics Letters 91, 022108-022110 (2007).251Wu et al., "Inversion-type enhancement-mode InP MOSFETs with ALD Al2O3, HfAlO nanolaminates as high-k gate dielectrics," Proceedings of the 65th Device Research Conf., 2007, pp. 49-52.252Wu et al., Gross-Sectional Scanning/Tunneling Microscopy Investigations of Cleaned III-V Heterostructures, Technical report, Dec. 1996, 7 pages.253Wuu et al., "Defect Reduction and Efficiency Improvement of Near-Ultraviolet Emitters via Laterally Overgrown GaN on a GaN/Patterned Sapphire Template," Applied Physics Letters, vol. 89, No. 16, Oct. 16, 2006, pp. 161105-1-3.254Xie et al., "From Porous Si to Patterned Si Substrate: Can Misfit Strain Energy in a Continuous Heteropitaxial Film Be Reduced?" Journal of Vacuum Science Technology, B, vol. 8, No. 2, Mar./Apr. 1990, pp. 227-231.255Xu et al., "Spin-Filter Devices Based on Resonant Tunneling Antisymmetrical Magnetic Semiconductor Hybrid Structures," vol. 84, Applied Physics Letters 11, 2004, pp. 1955-1957.256Yamaguchi et al., "Analysis for Dislocation Density Reduction in Selective Area Growth GaAs Films on Si Substrates," Applied Physics Letters, vol. 56, No. 1, Jan. 1, 1990, pp. 27-29.257Yamaguchi et al., "Defect Reduction Effects in GaAs on Si Substrates by Thermal Annealing," Applied Physics Letters vol. 53, No. 23, 1998, pp. 2293.258Yamaguchi et al., "Super-High-Efficiency Multi-junction Solar Cells," Prog. Photovolt.: Res. Appl., vol. 13, 2005, pp. 125-132.259Yamaguchi et al., GaAs Solar Cells Grown on Si Substrates for Space Use: Prog. Photovolt.: Res. Appl., vol. 9, 2001; pp. 191-201.260Yamamoto et al., "Optimization of InP/Si Heteroepitaxial Growth Conditions Using Organometallic Vapor Phase Epitaxy," Journal of Crystal Growth, vol. 96, 1989, pp. 369-377.261Yang et al., "High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations," IEDM Tech. Dig., 2003, pp. 453-456.262Yang et al., "Selective Area Deposited Blue GaN-InGaN Multiple-quantum Well Light Emitting Diodes over Silicon Substrates," Applied Physics Letter, vol. 76, No. 3, Jan. 17, 2000, pp. 273-275.263Yanlong, et al., "Monolithically fabricated OEICs using RTD and MSM," Chinese Journal Semiconductors vol. 27, No. 4, Apr. 2006, pp. 641-645.264Yili, et al., "Physics-based hydrodynamic simulation of direct current characteristics in DBRTD," 29 Chinese J. Electron Devices 2, Jun. 2006, pp. 365-368.265Yin et al., "Ultrathin Strained-SOI by Stress Balance on Compliant Substrates and FET Performance," 52 IEEE Trans. on Electron Devices 10, 2005, pp. 2207-2214.266Ying-Long, et al., "Resonant tunneling diodes and high electron mobility transistors integrated on GaAs substrates," Chinese Physics Letters 23, vol. 3, Mar. 2006, pp. 697-700.267Yoon et al., "Selective Growth of Ge Islands on Nanometer-scale Patterned SiO2/Si Substrate by Molecular Beam Epitaxy," Applied Physics Letters, vol. 89, 2006, pp. 063107.1-063107.3.268Yoshizawa et al., "Growth of self-Organized GaN Nanostructures on Al 2O3 (0001) by RF-Radial Source Molecular Beam Epitaxy", Japan, Journal of Applied Physics, Part 2, vol. 36, No. 4B, 1997, pp. L459-L462.269Zamir et al., Thermal Microcrack Distribution Control in GaN Layers on Si Substrates by Lateral Confined Epitaxy, Applied Physics Letters, vol. 78, No. 3, Jan. 15, 2001, pp. 288-290.270Zang et al., "Nanoheteroepitaxial lateral overgrowth of GaN on nanoporous Si (111)," Applied Physics Letters, vol. 88, No. 14, Apr. 3, 2006, pp. 141925.271Zang et al., "Nanoscale lateral epitaxial overgrowth of GaN on Si (111)," Applied Physics Letters, vol. 87, No. 19 (Nov. 7, 2005) pp. 193106.1-193106.3.272Zela et al., "Single-crystalline Ge Grown Epitaxially on Oxidized and Reduced Ge/Si (100) Islands," Journal of Crystal Growth, vol. 263, 2004, pp. 90-93.273Zhang et al., "Removal of Threading Dislocations from Patterned Heteroepitaxial Semiconductors by Glide to Sidewalls," Journal of Electronic Materials, vol. 27, No. 11, 1998, pp. 1248-1253.274Zhang et al., "Strain Status of Self-Assembled InAs Quantum Dots," Applied Physics Letters, vol. 77, No. 9, Aug. 28, 2000, pp. 1295-1297.275Zheleva et al., "Lateral Epitaxy and Dislocation Density Reduction in Selectively Grown GaN Structures," Journal of Crystal Growth, vol. 222, No. 4, Feb. 4, 2001, pp. 706-718.276Zubia et al., "Initial Nanoheteroepitaxial Growth of GaAs on Si (100) by OMVPE," Journal of Electronic Materials, vol. 30, No. 7, 2001, pp. 812-816.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8541773 *May 2, 2011Sep 24, 2013Intel CorporationVertical tunneling negative differential resistance devicesUS8580659 *Jul 25, 2011Nov 12, 2013Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of SciencesMethod of fabricating high-mobility dual channel material based on SOI substrateUS20110210337 *Dec 3, 2010Sep 1, 2011International Rectifier CorporationMonolithic integration of silicon and group III-V devices* Cited by examinerClassifications U.S. Classification438/143, 438/979, 438/511, 438/797, 257/E21.353, 257/E21.404, 438/407, 257/E21.367International ClassificationH01L21/04Cooperative ClassificationY10S438/979, H01L21/02521, H01L21/02554, H01L21/0237, H01L21/0256, H01L21/02565, G11C11/16, B82Y10/00, H01L21/02636, H01L21/02568, H01L27/11, H01L27/24, H01L29/7376, H01L29/882European ClassificationH01L29/737B6, H01L27/11, H01L29/88R, G11C11/16, H01L27/24, B82Y10/00RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google