Source: http://www.google.com/patents/US6858898?dq=4740761
Timestamp: 2014-07-14 14:17:52
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Patent US6858898 - Semiconductor device and method for manufacturing the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges...http://www.google.com/patents/US6858898?utm_source=gb-gplus-sharePatent US6858898 - Semiconductor device and method for manufacturing the sameAdvanced Patent SearchPublication numberUS6858898 B1Publication typeGrantApplication numberUS 09/532,915Publication dateFeb 22, 2005Filing dateMar 22, 2000Priority dateMar 23, 1999Fee statusPaidAlso published asUS7064388, US7504343, US7821071, US8154059, US8610182, US20050116294, US20060267114, US20090224260, US20110034215, US20120187411, US20140139776Publication number09532915, 532915, US 6858898 B1, US 6858898B1, US-B1-6858898, US6858898 B1, US6858898B1InventorsMasahiko Hayakawa, Mitsunori Sakama, Satoshi ToriumiOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (40), Non-Patent Citations (14), Referenced by (19), Classifications (30), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and method for manufacturing the sameUS 6858898 B1Abstract An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.
1. A semiconductor device having a thin film transistor, the semiconductor device comprising:
a silicon oxide nitride film formed over a substrate; and a semiconductor film formed over the silicon oxide nitride film, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of nitrogen to the concentration of silicon, and wherein the silicon oxide nitride film has a refractive index of from 1.5 to 1.8 to a wavelength of 632.8 nm. 2. A device according to claim 1 wherein said semiconductor device is selected from the group consisting of a video camera, a digital camera, a projector, a head-mounted display, a car navigation, a car stereo, a personal computer, a mobile computer, a cellular phone, and a digital book.
3. A semiconductor device having a thin film transistor, the semiconductor device comprising:
a silicon oxide nitride film formed over a substrate; and a semiconductor film formed over the silicon oxide nitride film, wherein the silicon oxide nitride film ranges from 0.1 to 1.7 in a ratio of the concentration of oxygen to the concentration of silicon, and wherein the silicon oxide nitride film has a refractive index of from 1.5 to 1.8 to a wavelength of 632.8 nm. 4. A device according to claim 3 wherein said semiconductor device is selected from the group consisting of a video camera, a digital camera, a projector, a head-mounted display, a car navigation, a car stereo, a personal computer, a mobile computer, a cellular phone, and a digital book.
5. A semiconductor device having a thin film transistor, the semiconductor device comprising:
an insulating film formed over a substrate and having at least a silicon oxide nitride film and an insulating layer containing silicon and oxygen; and a semiconductor film formed over the insulating film; wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of nitrogen to the concentration of silicon, and wherein the silicon oxide nitride film has a refractive index of from 1.5 to 1.8 to a wavelength of 632.8 nm. 6. A device according to claim 5, wherein the silicon oxide nitride film is in contact with a surface of the substrate.
7. A device according to claim 5, wherein the semiconductor film is in contact with a surface of the insulating layer containing silicon and oxygen.
8. A device according to claim 5, wherein the insulating layer containing silicon and oxygen is made of silicon oxide nitride containing silicon, oxygen and nitrogen and wherein a ratio of the concentration of nitrogen to the concentration of silicon ranges from 0.1 to 0.8.
9. A device according to claim 5, wherein the insulating layer containing silicon and oxygen is made of silicon oxide.
10. A device according to claim 5 wherein said semiconductor device is selected from the group consisting of a video camera, a digital camera, a projector, a head-mounted display, a car navigation, a car stereo, a personal computer, a mobile computer, a cellular phone, and a digital book.
11. A semiconductor device having a thin film transistor, the semiconductor device comprising:
an insulating film formed over a substrate and having at least a silicon oxide nitride film and an insulating layer containing silicon and oxygen; and a non-single crystal semiconductor film formed over the insulating film, wherein the silicone oxide nitride film ranges from 0.1 to 1.7 in a ratio of the concentration of oxygen to the concentration of silicon, and wherein the silicon oxide nitride film has a refractive index of from 1.5 to 1.8 to a wavelength of 632.8 nm. 12. A device according to claim 11, wherein the silicon oxide nitride film is in contact with a surface of the substrate.
13. A device according to claim 11, wherein the semiconductor film is in contact with a surface of the insulating layer containing silicon and oxygen.
14. A device according to claim 11, wherein the insulating layer containing silicon and oxygen is made of silicon oxide.
15. A device according to claim 11 wherein said semiconductor device is selected from the group consisting of a video camera, a digital camera, a projector, a head-mounted display, a car navigation, a car stereo, a personal computer, a mobile computer, a cellular phone, and a digital book.
an insulating underlying film provided over a substrate and comprising at least a silicon oxide nitride film and an insulting layer containing silicon and oxygen; a semiconductor film comprising a channel forming region provided over the insulating underlying film; a gate insulating film provided over the channel forming region; and a gate electrode provided adjacent to the channel forming region and over the gate insulating film, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of nitrogen to the concentration of silicon, wherein the silicon oxide nitride film has a thickness of 50 to 200 nm, wherein the insulating layer containing silicon and oxygen has a thickness of 10 to 300 nm, and wherein the silicon oxide nitride film has a refractive index of from 1.5 to 1.8 to a wavelength of 632.8 nm. 17. A device according to claim 16 wherein said semiconductor device is incorporated into a personal computer.
18. A device according to claim 16 wherein said semiconductor device is incorporated into a video camera.
19. A device according to claim 16 wherein said semiconductor device is incorporated into a goggle type display.
20. A device according to claim 16 wherein said semiconductor device is incorporated into a player using a recording medium.
21. A device according to claim 16 wherein said semiconductor device is incorporated into a digital camera.
22. A device according to claim 16 wherein said semiconductor device is incorporated into a projector.
23. A device according to claim 16 wherein said semiconductor device is incorporated into a cellular phone.
24. A device according to claim 16 wherein said semiconductor device is incorporated into a portable book.
25. A device according to claim 16 wherein said semiconductor device is incorporated into a display.
an insulating underlying film provided over a substrate and comprising at least a silicon oxide nitride film and an insulting layer containing silicon and oxygen; a semiconductor film comprising a channel forming region provided over the insulating underlying film; a gate insulating film provided over the channel forming region; and a gate electrode provided adjacent to the channel forming region and over the gate insulating film, wherein the silicon oxide nitride film ranges from 0.1 to 1.7 in a ratio of the concentration of oxygen to the concentration of silicon, wherein the silicon oxide nitride film has a thickness of 50 to 200 nm, wherein the insulating layer containing silicon and oxygen has a thickness of 10 to 300 nm, and wherein the silicon oxide nitride film has a refractive index of from 1.5 to 1.8 to a wavelength of 632.8 nm. 27. A device according to claim 26 wherein said semiconductor device is incorporated into a personal computer.
28. A device according to claim 26 wherein said semiconductor device is incorporated into a video camera.
29. A device according to claim 26 wherein said semiconductor device is incorporated into a goggle type display.
30. A device according to claim 26 wherein said semiconductor device is incorporated into a player using a recording medium.
31. A device according to claim 26 wherein said semiconductor device is incorporated into a digital camera.
32. A device according to claim 26 wherein said semiconductor device is incorporated into a projector.
33. A device according to claim 26 wherein said semiconductor device is incorporated into a cellular phone.
34. A device according to claim 26 wherein said semiconductor device is incorporated into a portable book.
35. A device according to claim 26 wherein said semiconductor device is incorporated into a display.
a silicon oxide nitride film provided over a substrate; a first transistor provided in a pixel and over said silicon oxide nitride film; a first semiconductor film comprising a first channel forming region of said first transistor, a source region and a drain region provided in said first semiconductor film and sandwiching said first channel forming region; a first gate insulating film provided over said first channel forming region; a first gate electrode provided adjacent to said first channel forming region and over said first gate insulating film; a pixel electrode provided over said substrate and connected with one of said source region and said drain region; a second transistor provided in a driver and over said silicon oxide nitride film; a second semiconductor film comprising a second channel forming region of said second transistor; a second gate insulating film provided over said second channel forming region; a second gate, electrode provided adjacent to said second channel forming region and over said second gate insulating film, wherein said silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of nitrogen to the concentration of silicon, and wherein the silicon oxide nitride film has a refractive index of from 1.5 to 1.8 to wavelength of 632.8 nm. 37. A device according to claim 36 wherein said semiconductor device is incorporated into a personal computer.
38. A device according to claim 36 wherein said semiconductor device is incorporated into a video camera.
39. A device according to claim 36 wherein said semiconductor device is incorporated into a goggle type display.
40. A device according to claim 36 wherein said semiconductor device is incorporated into a player using a recording medium.
41. A device according to claim 36 wherein said semiconductor device is incorporated into a digital camera.
42. A device according to claim 36 wherein said semiconductor device is incorporated into a projector.
43. A device according to claim 36 wherein said semiconductor device is incorporated into a cellular phone.
44. A device according to claim 36 wherein said semiconductor device is incorporated into a portable book.
45. A device according to claim 36 wherein said semiconductor device is incorporated into a display.
a silicon oxide nitride film provided over a substrate; a first transistor provided in a pixel and over said silicon oxide nitride film; a first semiconductor film comprising a first channel forming region of said first transistor, a source region and a drain region provided in said first semiconductor film and sandwiching said first channel forming region; a first gate insulating film provided over said first channel forming region; a first gate electrode provided adjacent to said first channel forming region and over said first gate insulating film; a pixel electrode provided over said substrate and connected with one of said source region and said drain region; a second transistor provided in a driver and over said silicon oxide nitride film; a second semiconductor film comprising a second channel forming region of said second transistor; a second gate insulating film provided over said second channel forming region; a second gate electrode provided adjacent to said second channel forming region and over said second gate insulating film, wherein the silicon oxide nitride film ranges from 0.1 to 1.7 in a ratio of the concentration of oxygen to the concentration of silicon, and wherein the silicon oxide nitride film has a refractive index of from 1.5 to 1.8 to a wavelength of 632.8 nm. 47. A device according to claims 46 wherein said semiconductor device is incorporated into a personal computer.
48. A device according to claim 46 wherein said semiconductor device is incorporated into a video camera.
49. A device according to claim 46 wherein said semiconductor device is incorporated into a goggle type display.
50. A device according to claim 46 wherein said semiconductor device is incorporated into a player using a recording medium.
51. A device according to claim 46 wherein said semiconductor device is incorporated into a digital camera.
52. A device according to claim 46 wherein said semiconductor device is incorporated into a projector.
53. A device according to claim 46 wherein said semiconductor device is incorporated into a cellular phone.
54. A device according to claim 46 wherein said semiconductor device is incorporated into a table book.
55. A device according to claim 46 wherein said semiconductor device is incorporated into a display.
56. An electroluminescence device comprising:
a silicon oxide nitrate film formed over a substrate; a semiconductor film formed over the silicon oxide nitride film, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of nitrogen to the concentration of silicon, and wherein the silicon oxide nitride film has a refractive index of from 1.5 to 1.8 to a wavelength of 632.8 nm.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit including a thin film transistor and a method for manufacturing the same, and more particularly, to an insulating film for separating a substrate from the active layer of the thin film transistor.
In order to realize the further lower price of the liquid crystal display, it is required to use a glass substrate as a substrate. Accordingly, a research on a technology for manufacturing a TFT at a process temperature of from 600� C. to 700� C. or less has been carried out.
Since the glass substrate contains a lot of impurity ions such as Na− or the like, it is necessary to form an underlying film made of silicon oxide, silicon nitride, or the like on the surface of the glass substrate to prevent the impurity ions from entering a semiconductor film.
In a process for manufacturing a liquid crystal panel, a plasma CVD method is usually used for forming an underlying film or a gate insulating film. This is because the plasma CVD is performed at a low process temperature of from 300� C. to 400� C. and has a large throughput and can form a film in a large area.
SUMMARY OF THE INVENTION It is an object of the present invention to provide an insulating film capable of blocking impurities from a substrate and eliminating the problems caused by an internal stress and to improve the reliability of a TFT.
If a gas containing oxygen and nitrogen, for example, N2 0, is used as a source of oxygen, the insulating layer contains not only Si and O but also N, and it is recommended that a ratio of the concentration of N to the concentration of Si (a ratio of composition of N/Si) ranges from 0.1 to 0.8; specifically, the concentration of nitrogen is 2�1020 atoms/cm3 or less. The ratio of the composition of the insulating film containing Si and O can be controlled by adjusting the kinds of the raw material gases, the rate of flow of them, a substrate temperature, pressure, RF power, and a gap between electrodes.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a process for manufacturing a CMOS circuit;
DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments in accordance with the present invention will be described with reference to FIGS. 1 to 5.
A 5-inch 1737 glass substrate (made by Corning Corp.) was used as a glass substrate 100. An underlying film 101 was formed in contact with the whole surface of the glass substrate 100. The underlying film 101 was made of a laminated film of insulating layers 101 a and 101 b. In the present preferred embodiment, four different conditions were set to investigate variations in the characteristics of a TFT which were caused by the film forming conditions of the insulating layer 101 a and the presence or absence of a heat treatment process of the insulating layer 101 a. Here, substrates subjected to different conditions are distinguished from each other like a substrate-1, a substrate-2. FIG. 3 shows the raw material gas and its rate of flow of the insulating layers 101 a and 101 b, and the presence or absence of a heat treatment to the insulating layer 101 a. [Forming of an Insulating Layer 101 a] See FIG. 1(A).
On each of a substrate-1 and a substrate-2 was formed a silicon oxide nitride film using SiH4 and N2O as raw material gases, respectively. On each of a substrate-3 and a substrate-4 was formed a silicon oxide nitride film using SiH4, N2O, and NH3 as the raw material gases, respectively. The rate of flow of each raw material gas will be shown in Table 1. The other conditions were common to the substrates 1 to 4: that is, a substrate temperature was 400� C., pressure was 0.3 Torr, and RF power was 300 W. Also, the thickness of the insulating layer 101 a of each substrate was 200 nm.
[Heat Treatment of the Insulating Layer 101 a] Only the insulating layer 101 a of the substrate-1 was heated at 640� C. and then was cooled for four hours.
Following processes were common to the substrate-1 to the substrate-4.
(Sequential Forming of an Insulating Layer 101 b and an Amorphous Silicon Film) See FIG. 1(B).
An insulating layer 101 b made of a silicon oxide film was formed in contact with the surface of the insulating layer 101 a. An amorphous silicon film 102 was formed on the insulating layer 101 b without exposing the surface of the insulating layer 101 b to the atmosphere. A multi-chamber-type plasma CVD apparatus provided with a chamber for forming the insulating layer 101 b and a chamber for forming the amorphous silicon film 102 was used as a film forming apparatus.
The raw material gases of the insulating layer 101 b were TEOS (rate of flow: 10 sccm) and O2 (rate of flow: 50 sccm), and when the insulating layer 101 b was formed, a substrate temperature was 400� C., pressure was 0.3 Torr, and RF power was 300 W. Also, the silicon oxide film was formed in a thickness of 15 nm.
The raw material gases of the amorphous silicon film 102 were SiH4 (rate of flow: 100 sccm) and the amorphous silicon film 102 was formed in a thickness of 55 nm. When the amorphous silicon film 102 was formed, a substrate temperature was 300� C., pressure was 0.5 Torr, and RF power was 20 W.
(Crystallization of an Amorphous Silicon Film) See FIG. 1(C).
A KrF excimer laser (wavelength: 248 nm) was applied to the amorphous silicon film to polycrystallize it, whereby a polycrystalline silicon film 103 was formed. An application atmosphere was air and a substrate temperature was a room temperature. Excimer laser light was formed into a line on a surface to be irradiated by an optical system and the amorphous silicon film was scanned with a linear beam. Irradiation energy density was adjusted in a range of from 350 mj/cm2 to 400 mj/cm2.
When the amorphous silicon film 102 was irradiated with the linear excimer laser beam, it was instantly melted at the spot and was recrystallized while it was solidified. In this connection, the substrate 100 was heated at 500� C. for 60 minutes before the laser irradiation to release hydrogen from the amorphous silicon film 102 into a vapor phase.
(Forming of an Active Layer and a Gate Insulating Film) See FIG. 1(C).
A photoresist pattern was formed on the polycrystalline silicon film 103 and the polycrystalline silicon film 103 was patterned into a shape of an island by dry-etching to form active layers l04 and 105. The dry-etching was performed using etching gases of CF4 and O2 and the rate of flow of CF4 was 50 sccm and the rate of flow of O2 was 45 sccm.
A silicon oxide nitride film was formed as a gate insulating film 106 in a thickness of 50 nm with the plasma CVD apparatus. SiH4 and N2O were used as the raw material gases. The rate of flow of SiH4 was 4 sccm and the rate of flow of N2O was 400 sccm. When the film was formed, pressure was 0.3 a Torr, a substrate temperature was 400� C., and RF power was 200 W.
(Forming of a Gate Wiring) See FIG. 1(E).
An aluminum film was formed on the gate insulating film 106 in a thickness of 400 nm with a sputtering apparatus. A target was mixed with Sc and Sc was added about 0.18% by weight to the aluminum film.
(Anodic Oxidation Process) See FIG. 2(A).
Anodic oxidation was performed in a state in which the photoresist pattern used for patterning the gate wiring remained. The anodic oxidation was performed using a 3% by weight oxalic acid as an electrolytic solution with a voltage of 8 V applied across the anode and the cathode, whereby a porous anodic oxide film 108 was formed on the side of the gate wiring 107.
(Doping with Phosphorus) See FIG. 2(B).
The gate insulating film 106 was patterned using the gate wiring 107 and the anodic oxide film 108 as an etching mask. Then, the porous anodic oxide film 107 was removed. Then, in order to form the source region and the drain region of an n-channel-type TFT, the active layer 105 was doped with phosphorus (P).
Phosphorus was added by two doping processes with an ion doping apparatus using a PH3 gas diluted to 5% with H2 gas as a doping gas. A first doping was performed with a high acceleration voltage and a low dose under the following conditions: an acceleration voltage was 90 kV; RF power was 5 W: a set dose was 1.2�1013 ions/cm2. A second doping was performed with a low acceleration voltage and a high dose under the following conditions: an acceleration voltage was 10 kV; RF power was 20 W; a set dose was 5�1014 ions/cm2.
(Doping with Boron) See FIG. 2(C).
The active layer 105 of the n-channel-type TFT was covered with a photoresist pattern PR1 and boron was added to the semiconductor layer 105 with the doping apparatus to form p-type source and drain regions. A B2H6 gas diluted to 5% with H2 gas was used as a doping gas. Here, two doping processes were performed under different conditions. The first doping was performed under the following conditions: an acceleration voltage was 70 kV; RF power was 5 W; and set dose was 6�1014 ions/cm2. The second doping was performed under the following conditions: an acceleration voltage was 10 kV; RF power was 20 W; and set dose was 1.3�1015 ions/cm2.
(Forming of an Interlayer Insulating Film and a Wiring) See FIG. 2(D).
Two insulating films of a silicon nitride film and a silicon oxide film were formed as interlayer insulating films 128 with the plasma CVD apparatus. First, the silicon nitride film was formed in a thickness of 25 nm using SiH4, NH3, and N2 as the raw material gases under the following conditions: a substrate temperature was 325� C.; pressure was 0.7 Torr; and RF power was 300 W. Then, the silicon oxide film was formed in a thickness of 940 nm using TEOS (tetraethoxysilane) and O2 as the raw material gases under the following conditions: a substrate temperature was 300� C.; pressure was 1.0 Torr; and RF power was 200 W.
Finally, the substrate was subjected to a hydrogenation treatment in a hydrogen atmosphere at a substrate temperature of 300� C. for 120 minutes. The hydrogenation treatment electrically neutralizes defects and dangling bonds in the active layers 104 and 105.
The initial characteristics of the TFT formed by the above-mentioned processes were measured for each substrate and then a BT test was conducted to investigate the deterioration of the characteristics. The stress conditions of the BT test were as follows: substrate temperature was 150� C.; test duration was 1 hour: drain voltage VD was 0 V; source voltage VS=0 V; gate voltage VG=20 V (n-channel-type), and −20 V (p-channel-type). Also, the measurement values of channel length L and width W of the TFT to be measured were 5.6 μm for L and 7.5μm for W for both of the n-channel type and the p-channel type.
FIG. 4 shows a drain current ID vs. a gate voltage VG characteristic curve of each substrate. A vertical axis is on a log scale. A solid line designates data before the BT test and a dotted line designates data after the BT test. Also, the data of the n-channel-type TFT is the data obtained in the case where the drain voltage VD was 1 V, and the drain voltage VD was −1 V for the p-channel-type TFT.
FIG. 5 is a graph showing variations in the characteristics of the TFT obtained by the BT test. FIG. 5(A) shows variations in a gate voltage VGIDmin. The gate voltage VGIDmin. In means a value calculated from the ID-VG characteristic curve as is the case with a threshold voltage Vth. As is shown in FIG. 5(C), the gate voltage VGIDmin means a gate voltage at a point where, of tangents to the characteristic curve with a drain current ID on a log scale, a tangent having the maximum absolute value of gradient crosses a horizontal line passing the point of the minimum value of the drain current ID of the characteristic curve.
The data in FIG. 5(A) shows variations in the gate voltage VGIDmin before and after the BT test and a difference ΔVGIDmin between the gate voltage VGIDmin before the test and the gate voltage VGIDmin after the test=VGIDmin′−VGIDmin. In this connection, in the substrate-3, since the difference ΔVGIDmin for the case of the n-channel-type TFT (L/W=5.6/7.5 μm) is 0.007, very small, nothing is shown in the graph.
The data shown in FIG. 5(B) were calculated from log (Icut′-Icut), where the Icut was a value before the test and the Icut′ was a value after the test.
On the other hand, it is seen from the characteristic curves of the substrate-2 shown in FIGS. 4(C), (D), that the characteristic curves significantly vary in the subthreshold region and a heat treatment can decrease the deterioration (see FIGS. 4(A) and (B), which show the case of the substrate-1 corresponding to this).
On the other hand, the ΔVGIDmin and the ΔIcut of the p-channel-type TFT are slightly larger than those of the n-channel-type TFT, but as is evident from the ID-VG characteristic curves in FIG. 4(F), (H), the ID-VG characteristic curves are shifted to a normally-off side and hence it is thought that there is no problem in operations as compared with the case in which the ID-VG characteristic curves are shifted to a normally-on side.
The ID-VG characteristic curve being shifted to a normally-off side means that it is shifted to a side in which a cut-off current Icut decreases, and the ID-VG characteristic curve being shifted to a normally-on side means that it is shifted to a side in which a cut-off current Icut increases.
In the substrate-1 and the substrate-2, the ID-VG characteristic curves of the n-channel-type TFT and the p-channel-type TFT are shifted to the normally-on side and hence it is understood that the TFTs of the substrate-3 and the substrate-4 have high reliability.
In the insulating layer 101 a in the substrate-3, a ratio of the concentration of nitrogen to the concentration of silicon was 0.73 and a ratio of the concentration of oxygen to the concentration of silicon was 0.80. An internal stress was a tensile stress in asdepo and after the heat treatment.
In this connection, in the case where the rate of flow of NH3 was increased as compared with the substrate-4 when the insulating layer 101 a was formed, when the substrate was heated at a temperature of about 600� C. for several hours after the semiconductor film was formed, it was observed that the film was separated. Therefore, in the case where the substrate is heated at about 600� C. for several hours, it is preferable to adjust the upper limit of the ratio of the concentration of nitrogen to the concentration of silicon to 1.3 and to adjust the lower limit of the ratio of the concentration of oxygen to the concentration of silicon to 0.2.
Also, the concentrations of nitrogen in the insulating layer 101 a in the substrates measured with a SIMS were 2�1020 atoms/cm3 for the substrate-1 and the substrate-2, and 8�1021 atoms/cm3 for the substrate-3. Accordingly, the concentration of nitrogen in the insulating layer 101 a is adjusted to more than 2�1020 atoms/cm3, more preferably more than 1�1021 atoms/cm3, with the ratio of the composition of nitrogen to that of silicon in the above range.
In the driver circuit, the active layers of the n-channel-type TFT and the p-channel-type TFT cross a gate wiring 208 across the gate insulating film 205. In the active layer of the n-channel-type TFT, there are formed a channel forming region 230, n+-type high-concentration impurity regions 231 and 232, and n−-type low-concentration impurity regions 233 and 234. The n−-type low-concentration impurity regions 233 and 234 are lower in the concentration of phosphorus than the high-concentration impurity regions 231 and 232 and becomes high resistance regions. The n−-type low-concentration impurity regions 233 and 234 overlap the gate wiring 208 (electrode 208 a) and hence effectively prevent the deterioration caused by the hot carriers. Meanwhile, in the active layer of the p-channel-type TFT, there are formed channel forming regions 240 and p+-type high-concentration impurity regions 241 and 242.
(Forming of an underlying film, an active layer, and a gate insulating film) See FIG. 7(A).
The glass substrate 200 is cleaned and then an underlying film made of insulating layers 201 a and 201 b are formed in contact with the glass substrate 200.
First, a silicon oxide nitride film is formed as the insulating layer 201 a in a thickness of 100 nm by the use of gases of SiH4, NH3, N2O as the raw material gas under the following conditions: rate of flow of Si H4 is 10 sccm; rate of flow of NH3 is 100 sccm: rate of flow of N2O is 20 sccm: and when the film is formed, substrate temperature is 300� C., pressure is 0.3 Torr and RF power is 200 W.
On the insulating layer 201 a is formed a silicon oxide nitride film as the insulating layer 201 b in a thickness of 200 nm with the plasma CVD apparatus by the use of gases of SiH4 and N2O as the raw material gases under the following conditions: rate of flow of SiH4 is 4 sccm; rate of flow of N2O is 400 sccm; and when the film is formed, substrate temperature is 300� C., pressure is 0.3 Torr, and RF power is 200 W.
An acetic acid water solution containing nickel (Ni) is applied to the surface of the amorphous silicon film using a spin coater. In this process, Ni as an element facilitating crystallization is added to the amorphous silicon film. The substrate 200 is heated in an electric furnace at 500� C. for 1 hour to release hydrogen in the amorphous silicon film into a vapor phase and then the substrate is heated in the electric furnace in a nitrogen atmosphere at 550� C. for 4 hours to crystallize the amorphous silicon film to form a crystalline silicon film.
The crystalline silicon film is patterned in a shape of an island by dry-etching to form the active layer 202 of the pixel TFT, the active layers 203, 204 of the n-channel-type TFT and the p-channel-type TFT of the driver circuit. The gate insulating film 205 is formed over the active layers 202 to 204. A silicon oxide nitride film is formed as the gate insulating film 205 in a thickness of 150 nm with the plasma CVD apparatus using SiH4 and N2O as the raw material gases under the following conditions: rate of flow of SiH4 is 4 sccm; rate of flow of N2O is 400 sccm; and when the film is formed, pressure is 0.3 Torr, substrate temperature is 400� C. and RF power is 200 W.
(Doping Process of Phosphorus) See FIG. 7(B).
A photoresist pattern PR11 is formed on the gate insulating film 205. Regions where channels of the active layers 202 and 203 are formed are selectively covered with the photoresist pattern PR11 and the active layer 204 is wholly covered with it. Phosphorus is added thereto with an ion doping apparatus. A PH3 gas diluted with hydrogen is used as a doping gas. In order to add phosphorus to the active layers 202 and 203 through the gate insulating film 205, an acceleration voltage is set at a higher value of 80 keV. In the doping process, n−-type low concentration impurity regions 301 to 303 are formed in the active layer 202 and n−-type low concentration impurity regions 304 and 305 are formed in the active layer 203. It is preferable that the concentration of phosphorus in these low concentration impurity regions 301 to 305 ranges from 1�1016 atoms/cm3 to 1�1019 atoms/cm3, and it is set at 1�1018 atoms/cm3 this time.
(Forming of a Conductive Film) See FIG. 7(C).
The resist mask PR11 is removed and then a conductive film 306 constituting a gate wiring is formed on the surface of the gate insulating film 205. Here, a film including a tantalum film and a tantalum nitride film laminated thereon is formed as the conductive film 306 by a sputtering method.
The conductive film 306 is made of a single layer film or a laminated film made of a conductive material whose main component is an element selected from the group consisting of Ta, Ti, Mo, W, Cr, and Al, and silicon containing phosphorus or silicide. For example, such a composition as WMo, TaN, MoTa, WSix (2.4<x<2.7) can be used.
(Doping with Boron) See FIG. 8(A).
In order to pattern a conductive film 212, a photoresist pattern PR12 is formed on the conductive film 212. The conductive film 212 is patterned by wet-etching by the use of the photoresist pattern PR12. Masks 206 m, 208 m are formed on the active layers 202, 203 of the n-channel-type TFT so as to function as doping masks. A gate electrode 208 b having a final shape is formed on the active layer 204 of the p-channel-type TFT. After doping, doped phosphorus and boron is activated by a heat treatment at 450� C.
The substrate is doped with boron in the ion doping apparatus with the photoresist pattern PR12 left. A diborane (B2H6) gas diluted with hydrogen is used a doping gas and an acceleration voltage is 80 KeV. A channel forming region 240 and p+-type high-concentration impurity regions 241 and 242 are formed in the active layer 204 in a self-alignment manner. The concentration of boron of the p+-type high-concentration impurity regions 241 and 242 is 2�1020 atoms/cm3.
(Forming of a wiring) See FIG. 8(B).
The photoresist pattern PR12 is removed and then a new photoresist pattern PR13 is formed. The photoresist pattern 13 is used for patterning the masks 206 m and 208 m to form gate electrodes 206 a and 208 a, and the capacitance electrode 207 a and for protecting the active layer of the p-channel type TFT.
The masks 206 m and 208 m are patterned by a dry-etching method using the photoresist pattern PR13 to complete the gate wirings 206 and 208 and a capacitance wiring 207 as shown in the drawing. In then-type low concentration impurity regions 301 to 303, regions overlapping the gate electrodes 206 a and 206 b of the pixel TFT are defined as the n−-type low concentration impurity regions 219 to 222.
(Doping with Phosphorus) See FIG. 9(A).
The photoresist pattern PR13 is removed and then a photoresist pattern PR14 is formed and an n+-type region is formed by doping. In the pixel TFT, the electrode 206 and a part of the n−-type low-concentration impurity regions 301 to 303 are covered with the photoresist pattern PR14 to define the low-concentration impurity regions 219 to 222 not overlapping the gate electrodes 206 a and 206 b. In the n-channel type TFTs of a retention capacitance portion and a CMOS circuit, the photoresist pattern PR14 is formed only on the electrodes 207 a and 208 a, and the active layer of the p-channel-type TFT is wholly covered with the photoresist pattern PR14.
The substrate is doped with phosphorus in the ion doping apparatus using a PH3 gas diluted with hydrogen. An acceleration voltage is set at a higher value of 80 keV. In the active layers 203 and 204, there are formed n+-type high-concentration impurity regions 212 to 214, 231, 232. It is recommended that the concentration of phosphorus of these n+-type high-concentration impurity regions be 1�1019 atoms/cm3 to 1�1021 atoms/cm3 and in this case, it is 1�1020 atoms/cm3. In this doping process, the impurity region of the n-channel type TFT is completed.
(Forming of a Wiring and an Electrode) See FIG. 9(B).
A silicon nitride film 250 is formed by the plasma CVD method over the surface of the gate insulating film 205, gate wirings 206 and 208 and the retention capacitance wiring 207. The thickness of the silicon nitride film 250 is 50 nm. The substrate is heated at 600� C. to activate the doped phosphorus and boron.
(Forming of a Pixel Electrode) See FIG. 6.
Next, in order to cover the pixel TFT and the CMOS circuit, the silicon nitride film 257 is formed on the whole surface of the substrate by the plasma CVD method. Next, an acrylic film is formed as a planarization film 258 by the use of a spin coater. The planarization film 258 and the silicon nitride film 257 are etched to form a contact hole reaching the drain electrode 253. An ITO film is formed by the sputtering method and is patterned to form a pixel electrode 260. An oriented film made of polyimide is formed on the whole surface of the substrate 200. In this manner, an active matrix substrate is completed.
In the present embodiment, the TFT of a planar type as a top gate type was manufactured, but the TFT may be a bottom gate type such as an inverted stagger type. The use of the underlying film of the present embodiment can prevent the impurities contained in the glass substrate such as Na+ions or the like from entering the gate insulating film.
In FIG. 12(A), a reference numeral 3001 designates a substrate, a reference numeral 3002 designates a pixel part, a reference numeral 3003 designates a source side driver circuit, and a reference numeral 3004 designates a gate side driver circuit and each driver circuit leads to a FPC (flexible printed circuit) 3006 via a wiring 3005, and is connected to an external device.
Also, an ultraviolet-cured resin or a thermosetting resin can be used as the filling material 3103, and PVC (poly(vinyl chloride)), acrylic, polyimide, epoxy resin, a silicone resin, PVB (poly(vinyl butyl)), or EVA (ethylene vinyl acetate) can be used. A hygroscopic substance (preferably, barium oxide) put in the filling material 3103 can prevent the deterioration of the EL device. In this connection, in the present embodiment, a transparent material is used so that light from the EL device can pass the filling material 3103.
Also, FIG. 13(B) is an example having the current supply wiring 3408 in parallel to the gate wiring 3403. In this connection, while the example shown in FIG. 13(B) has a structure in which the current supply wiring 3408 does not overlap the gate wiring 3403, if both wirings are formed in different layers, they are arranged such that they overlap each other via an insulating film. In this case, since the current supply wiring 3408 and the gate wiring 3403 can share an area designed specifically therefor, the pixel part can be made in still higher definition.
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