Source: http://www.google.com/patents/US6475836?dq=6721967
Timestamp: 2018-01-18 10:26:27
Document Index: 176134126

Matched Legal Cases: ['application No. 11', 'application No. 10', 'application No. 10', 'application No. 11', 'application No. 11', 'application No. 11', 'application No. 11', 'application No. 7']

Patent US6475836 - Semiconductor device and manufacturing method thereof - Google Patents
It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film)...http://www.google.com/patents/US6475836?utm_source=gb-gplus-sharePatent US6475836 - Semiconductor device and manufacturing method thereof
Publication number US6475836 B1
Application number US 09/535,835
Also published as US6686228, US6900462, US7633085, US8093591, US20020197846, US20040140471, US20050200767, US20100155732
Publication number 09535835, 535835, US 6475836 B1, US 6475836B1, US-B1-6475836, US6475836 B1, US6475836B1
Inventors Hideomi Suzawa, Yoshihiro Kusuyama
Patent Citations (22), Non-Patent Citations (12), Referenced by (189), Classifications (26), Legal Events (5)
US 6475836 B1
It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.
forming a first conductive;
forming an inorganic insulating film over said first conductive film;
forming an organic resin film over said inorganic insulating film;
forming a contact hole in a laminated film formed of said inorganic insulating film and said organic resin film in one process by etching with a selective ratio of an etching rate of said inorganic insulating film to an etching rate of said organic resin film from 1.6 to 2.9; and
forming a second conductive film in said contact hole.
2. A method according to claim 1, wherein said process of forming said contact hole is performed by dry etching employing mixed gas containing fluorine-based etchant gas and oxygen gas.
forming a contact hole in a laminated film formed of said inorganic insulating film and said organic resin film in one process to form an edge portion of said inorganic insulating film that comes in contact with a bottom surface of said contact hole into a taper shape having an angle range of 30° to 80° from a horizontal surface; and
5. A method of manufacturing a semiconductor device, comprising the steps of;
forming a contact hole in a laminated film formed of said inorganic insulating film and said organic resin film in one process to form an edge portion of said organic resin film that comes in contact with said inorganic insulating film into a taper shape having an angle range of 50° to 90° from a horizontal surface; and
6. A method according to claim 1 wherein said semiconductor device is a video camera.
Still further, according to each structure of the above, an edge portion of an inorganic insulating film that comes in contact with a bottom surface of said contact hole is taper like having an angle range of 30° to 800° from a horizontal surface.
Further, according to each structure of the above, an edge portion of an organic resin film that comes in contact with said inorganic insulating film has an angle range of 50° to 90° from a horizontal surface.
Among the photographic views of FIGS. 3 and 4, a contact hole that is at its best shape is when the flow rate condition of CF4 is 45 sccm to 55 sccm, preferably 50 sccm (FIG. 3C). An edge portion of the inorganic insulating film that is in contact with the bottom surface of the contact hole in this state is taper like having an angle of 70° from the horizontal surface. And also from FIG. 2B, when the contact hole is most excellently-shaped, the selection ratio is 1.6 to 2.9, preferably 1.9.
An edge portion of the inorganic insulating film that comes in contact with the bottom surface of the contact hole (FIG. 5C, a) can be taper like with an angle range of 30° to 80° from a horizontal surface by utilizing the present invention. Additionally, an edge portion of the organic resin film that comes in contact with the inorganic insulating film (FIG. 5C, b) can be angled at a range of 50° to 90° from a horizontal surface.
In FIG. 8A, it is preferred that a quarts substrate or a silicon substrate be used as a substrate 101. A quartz substrate is used in the present embodiment. Others such as a metal substrate or a stainless substrate with an insulating film formed thereon can also be used as a substrate. Substrates having heat resistant properties that can stand a temperature of 800° C. are demanded in the present embodiment, therefore any of the substrates that meets this demand can be used.
Depending upon the amount of hydrogen contained in the amorphous silicon film, heat treatment is performed for a duration of 1 hour preferably at 400 to 550° C. It is desired that hydrogen be sufficiently eliminated before crystallization and the preferred amount of hydrogen contained be 5 atomic% or less.
In the crystallization process, first, heat treatment process is performed at 400 to 500° C. for a duration of 1 hour to eliminate hydrogen from the inside of the film, followed by performing heat treatment at 500 to 650° C. (preferably at 550 to 600° C.) for a duration of 6 to 16 hours (preferably for 8 to 14 hours).
In the present embodiment, nickel is used as the catalytic element, and heat treatment is performed for a duration of 14 hours at 570° C. As a result, crystallization progresses in a direction roughly parallel with the substrate (in the direction shown by the arrows) using the opening portions 104 a and 104 b as the starting point and semiconductor films (crystalline silicon films in the present embodiment) 105 a- 105 d having a crystal structure comprising crystals whose crystal growth directions are macroscopically aligned are formed. (FIG. 8B)
Gettering process is performed next to remove the nickel used in the crystallization process from the crystalline silicon film. In the present embodiment, using the mask film 13 that was previously formed just as the mask, the process of adding an element that belongs to group 15 (phosphorous in the present embodiment) is performed and then phosphorous doped regions containing phosphorous (hereinafter referred as gettering region) 106 a and 106 b are formed at 1 ×1019 to 1×1020 atoms/cm3 of concentration on the crystalline silicon film exposed from the opening portions 104 a and 104 b. (FIG. 8C)
Next, heat treatment process is performed at 450 to 650° C. (preferably at 500 to 550° C.) in a nitrogen atmosphere for a duration of 4 to 24 hours (preferably for 6 to 12 hours). Through this heat treatment process, the nickel in the crystalline silicon film moves toward the direction of the arrow and is captured in the gettering regions 106 a and 106 b by the gettering action of phosphorus. Namely, since nickel is removed from the crystalline silicon film, the concentration of nickel in crystalline silicon films 107 a through 107 d after gettering can be reduced to 1×1017 atoms/cm3 or below, preferably up to 1×1016 atms/cm3.
In this process, impurity regions 110 a and 110 b containing a P-type impurity element (boron in the present embodiment) are formed at a 1×1015 to 1×1018 atoms/cm3 (typically 5×1016 to 5×1017 atoms/cm3) concentration. The above concentration range of the impurity region (a region excluding phosphorus) containing P-type impurity element is defined as P-type impurity region (b) in the specifications of the present invention. (FIG. 8D)
After crystallization, nickel is removed or reduced by the gettering action of phosphorus, and the concentration of the catalytic element remaining in the active layers 111 through 114 is 1×1017 atoms/cm3 or less, preferably 1×1016 atoms/cm3. (FIG. 8E)
Next, heat treatment process is performed under an oxidizing atmosphere (thermal oxidation process) at a temperature of 800 to 1150° C. (preferably 900 to 1000° C.) for a duration of 15 minutes to 8 hours (preferably 30 minutes to 2 hours). In the present embodiment, heat treatment process is performed at 950° C. for 80 minutes under oxygen atmosphere doped with 3% by volume of hydrogen chloride. Furthermore, the boron doped in the process of FIG. 8D is activated during this thermal oxide process. (FIG. 9A)
The impurity regions 120 through 122 are impurity regions for functioning as an LDD region later for the N channel TFT of the CMOS circuit and the sampling circuit. The N-type impurity elements in the impurity regions formed here contain 2×1016 to 5×1019 atoms/cm3 of concentration (typically 5×1017 to 5×1018 atoms/cm3). The present invention defines the impurity regions containing N-type impurity elements in the above concentration range as N-type impurity region (b).
Here, mass separation is not performed on phosphine(PH3) and phosphorus is doped at 1×1018 atoms/cm3 by plasma excited ion dope means. Of course, the ion implantation method, which performs mass separation, can be employed. Phosphorus is doped in the crystalline silicon film via the gate film 115 in this process.
Next, heat treatment is performed at 600 to 1000° C. (preferably 700 to 800° C.) in an inactive atmosphere in order to activate the phosphorus that was doped in the process of FIG. 9B. In this embodiment, heat treatment is performed at 800° C. for 1 hour in a nitrogen atmosphere.
A conductive film that is to be a gate wiring is formed next. Although the gate wiring can be formed as a single layer conductive film, it is preferred that a lamination film of 2 or 3 layers be formed to meet the needs when required. In this embodiment, a first conductive film 123 and a second conductive film 124 are formed as the layered films. (FIG. 9D) Elements chosen from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si); conductive films from the above elements as the main component(typically a nitride tantalum film, a nitride tungsten film, a nitride titanium film) or alloy films from the combination of the above elements (typically an alloy of Mo—W, an alloy of Mo—Ta) can be used for the first conductive film 123 and the second conductive film 124.
Then a resist mask 129 is formed and a P-type impurity element (boron in this embodiment) is doped so that the impurity regions 130 and 131 containing boron is formed at high concentration. In this embodiment, boron is doped at 3×1020 to 3×1021 atoms/cm3 (typically 5×1020 to 1×1021 atoms/cm3) of concentration by the ion doping means employing diborane (of course ion implantation can be used). The present invention defines the impurity regions containing P-type impurity elements in the above concentration range as P-type impurity region (a). (FIG. 10A)
Subsequently, the resist mask 129 is removed and resist masks 132 through 134 are formed so as to cover the gate wirings and a region that is to be a P channel TFT. Then an Ntype impurity element (phosphorus in this embodiment) is doped and impurity regions 135 through 141 containing phosphorus are formed at high concentration. The ion doping means employing phosphine (PH3) is also conducted here (of course ion implantation can be used). The concentration of phosphorus in this region is 1×1020 to 1×1021 atoms/cm3 (typically, 2×1020 to 5×1021 atoms/cm3). (FIG. 10B) p The specifications of the present invention define the impurity regions containing N-type impurity elements in the above concentration range as N-type impurity region (a). Although the region in which the impurity regions 135 through 141 have been formed already contains phosphorus and boron that were doped in the previous process, there is no need to take into consideration the influences of phosphorus and boron that were doped in the previous process since it is considered that phosphorus was doped at a sufficient high concentration.
Using the gate wirings 125 through 128 as masks, an N-type impurity element (phosphorus in this embodiment) is doped in a self-aligning manner. Impurity regions 143 through 146 formed in this way are adjusted so that phosphorus can be doped at a concentration of ½to {fraction (1/10)} of the above N-type impurity regions (b) (typically ⅓ to ¼)(however, a concentration that is 5 to 10 times higher than the concentration of boron doped in the above-mentioned channel doping process, representatively 1×1016 to 5×1018 atoms/cm3, specification, the impurity regions containing N-type impurity elements (however, excluding P-type impurity region (a)) in the above concentration range are defined as N-type impurity region (c). (FIG. 10C)
As phosphorus is also doped at a concentration of 1×1016 to 5×1018 atoms/cm3 in all the impurity regions except the portion concealed by the gate wiring in this process, since concentration is extremely low, influences are not inflicted on the functions of each impurity region. Also, as boron is already doped in the N-type impurity regions (b) 143 through 146 at a concentration of 1×1015 to 1×1018 atoms/cm3 in the channel doping process, phosphorus is doped at a concentration that is 5 to 10 times higher than the concentration of boron in the P-type impurity regions (b). In this situation, it can also be considered that boron does not influence the functions of the N-type impurity regions (b).
However, strictly the phosphorus concentration of a portion of the N-type impurity regions (b) of either 147 or 148 that overlaps with the gate wiring is as it is, 2×1016 to 5×1019 atoms/cm3, though a 1×1016 to 5×1018 atoms/cm3 concentration of phosphorus is added to the portion that does not overlap on the gate wiring, which means that the N-type impurity region contains phosphorus at a little higher concentration.
Then heat treatment process is performed on the N-type or P-type impurity element, doped at its concentration respectively, for activation. In this process, heat treatment can be performed by furnace annealing, laser annealing, lamp annealing, or a combination of methods. If performing by furnace annealing, heat treatment is performed at 500 to 800° C., preferably at 550 to 600° C., in an inactive atmosphere. The impurity elements are activated at 600° C. for a duration of 4 hours in this embodiment. (FIG.10D)
Heat treatment is performed at 300 to 450° C. for a duration of 1 to 4 hours in an atmosphere containing 3 to 100% of hydrogen after the activation process. Then hydrogenation is carried out on the active layer. This process is to terminate dangling bonds in a semiconductor layer by thermally excited hydrogen. As other hydrogenation means, plasma hydrogenation (using hydrogen excited by plasma) can be performed.
Furthermore, the hydrogenation process can be performed after forming the passivation film 158. For example, performing heat treatment at 300 to 450° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen, or employing a plasma hydrogenation process in which similar effects can be obtained.
Then, a third interlayer insulating film 159 formed of organic resin is formed at about 1 μm in thickness. Polyimide, acrylic, polyamide, polyimide-amide, BCB (benzocyclobutene), etc. can be used as inorganic resin. The advantages of using organic resin are the simplification of forming a film, the reduction of a parasitic capacity due to a low dielectric constant, and having excellent flatness. Other organic resin or organic-based SiO compounds besides the ones mentioned above can be employed as well. Here, after coating the substrate, the interlayer insulating film 159 is formed by baking at 300° C. using a type of acrylic that is thermal polymeric.
In a region that is to be a pixel circuit, a shielding film 160 is formed on top of the third interlayer insulating film 159. In the context of the present invention, the term “shielding film” means the shielding of light and electromagnetic wave. The shielding film 160 is formed of an element selected from aluminum (Al), titanium (Ti), and tantalum (Ta) or has one of these elements as a main component at a thickness of 100 to 300 nm. According to the present embodiment, an aluminum film containing 1 wt% of titanium is formed at 125 nm in thickness.
In the P channel TFT 301 of the driving circuit, a channel forming region 201, a source region 202, and a drain region 203 are respectively formed in the P-type impurity regions (a). However, strictly the source region 202 and the drain region 203 contain phosphorus at a concentration of 1×1016 to 5×1018 atoms/cm3.
Further, in the N channel TFT 302, a channel forming region 204, a source region 205 and a drain region 206 are formed. Also, a region 207, which overlaps a gate wiring via a gate insulating film, is formed between the channel forming region and the drain region (the present invention calls this region “Lov” region, where “ov” refers to overlap). The Lov region 207 at this time contains phosphorus at a concentration of 2×1016 to 5×1019 atoms/cm3 and is formed as to overlap the gate wiring completely.
The LDD region 211 can further be classified as an Lov region and an Loff region. The above Lov region contains phosphorus at a concentration of 2×1016 to 5×1019 atoms/cm3 while the Loff region contains phosphorus at a concentration that is 1 to 2 times higher that the Lov region (typically, 1.2 to 1.5 times).
Due to the continuity of the crystal lattices in the crystal grain boundary, the crystal grain boundary is called “plane-like grain boundary”. In the present invention, the definition of the plane-like grain boundary is “planar boundary disclosed in ” Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol.27, No.5, pp.751-758, 1988
It is known that the grain boundary formed between two crystal grains becomes the corresponding grain boundary of Σ3 when the plane direction of the two crystals is {110} and the angle θ formed by a lattice stripe which corresponds to a {111} plane is θ=70.5°. Each lattice stripe of the crystal grains lined next to each other in the crystal grain boundary of the crystalline silicon film according the present embodiment is surely linked together at an angle about 70.5°. From this fact, it can be said that the crystal grain boundary is the corresponding grain boundary of Σ3.
Moreover, the crystal grain boundary becomes the corresponding grain boundary of Σ9 when θ=38.9° meaning that other corresponding grain boundaries do exist. However, in any case, all are inactive.
Furthermore, it has been confirmed from a TEM observation that almost all the defects existing inside a crystal grain are extinguished through a heat treatment process at a very high temperature of 800 to 1150° C. (corresponding to the thermal oxidation in embodiment 1). This is obvious since the number of defects has been largely lessened after thermal oxidation.
The difference in the number of defects will appear as the difference in spin density through an electron spin resonance analysis (ESR). The spin density of the crystalline silicon film according to the present embodiment in the present state has been identified as at least 5×1017 spins/cm3 or less (preferably 3×1017 spins/cm3 or less). However, this measured value is near the value that the present existing measurement device can limitedly detect. The actual spin density is expected to be lower.
For example, materials disclosed in “H. Furue et al.; Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability, SID, 1988”, “T. Yoshida et al.; A Full-Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time, 841, SID97DIGEST, 1997”, “S. Inui et al.; Thresholdless Antiferroelectricity in Liquid Crystals and its Application to Displays, 671-673, J.Mater.Chem.6(4),1996”, or U.S. Pat. No. 5,594,569 can be used.
Specifically, with respect to an electric field, as Thresholdless Antiferroelectric LCD (abbreviated as TL-AFLC) that indicates electro-optical response characteristic of continuously changing transmission rate, there is a type that indicates a V-shaped type (or U-shaped type) of electro-optical response characteristic. It has been proved that the drive voltage is approximately ±2.5 V (cell thickness is about 1 μm to 2 μm). Due to this fact, there are cases where the power voltage for pixel circuits is sufficient from 5 to 8 V and the possibility of operating the driving circuit and the pixel circuit at the same power source voltage has been suggested. That is, attempts can be made on the low consumption of electric power of the whole liquid display device.
US5477359 * Jan 21, 1994 Dec 19, 1995 Sharp Kabushiki Kaisha Liquid crystal projector having a vertical orientating polyimide film
US6204081 * May 20, 1999 Mar 20, 2001 Lg Lcd, Inc. Method for manufacturing a substrate of a liquid crystal display device
US6218206 * Sep 15, 1998 Apr 17, 2001 Mitsubishi Denki Kabushiki Kaisha Method for producing thin film transistor and thin film transistor using the same
JPH1197702A Title not available
1 English abstract re Japanese application No. 11-345767, published Dec. 14, 1999.
2 English abstract re Japanese patent application No. 10-247735, published Sep. 14, 1998.
3 English abstract re Japanese patent application No. 10-294280, published Nov. 4, 1998.
4 English abstract re Japanese patent application No. 11-097702, published Apr. 9, 1999.
5 English abstract re Japanese patent application No. 11-133463, published May 21, 1999.
6 English abstract re Japanese patent application No. 11-191628, published Jul. 13, 1999.
7 English abstract re Japanese patent application No. 11-354442, published Dec. 24, 1999.
8 English abstract re Japanese patent application No. 7-130652, published May 19, 1995.
9 Furue, H. et al, "Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability," SID 98 Digest, pp. 782-785, 1998.
10 Inui, S. et al, "Thresholdless Antiferroelectricity in Liquid Crystals and its Application to Displays," J. Mater. Chem., vol. 6, No. 4, pp. 671-673, 1996.
11 Shimokawa, R. et al, "Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement, " Japanese Journal of Applied Physics, vol. 27, No. 5, pp. 751-758, May, 1988.
12 Yoshida, T. et al, "A Full-Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time," SID 97 Digest, pp. 841-844, 1997.
US6737294 * Jun 18, 2003 May 18, 2004 Au Optronics Corp. Method of reducing surface leakage currents of a thin-film transistor substrate
US6773944 Nov 5, 2002 Aug 10, 2004 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US6838298 * Nov 8, 2002 Jan 4, 2005 Hynix Semiconductor Inc. Method of manufacturing image sensor for reducing dark current
US6862008 * Aug 5, 2002 Mar 1, 2005 Semiconductor Energy Laboratory Co., Ltd. Display device
US6900460 Nov 14, 2001 May 31, 2005 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US6909124 Jun 25, 2003 Jun 21, 2005 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US6927175 * Dec 26, 2001 Aug 9, 2005 Lg. Philips Lcd Co., Ltd. Method of fabricating X-ray detecting device
US6953705 Jul 22, 2003 Oct 11, 2005 E. I. Du Pont De Nemours And Company Process for removing an organic layer during fabrication of an organic electronic device
US7002292 Jul 22, 2003 Feb 21, 2006 E. I. Du Pont De Nemours And Company Organic electronic device
US7169710 Mar 19, 2002 Jan 30, 2007 Semiconductor Energy Laboratory Co., Ltd. Wiring and method of manufacturing the same, and wiring board and method of manufacturing the same
US7235420 Jul 13, 2004 Jun 26, 2007 E. I. Du Pont De Nemours And Company Process for removing an organic layer during fabrication of an organic electronic device and the organic electronic device formed by the process
US7268366 Dec 6, 2004 Sep 11, 2007 Lg.Philips Lcd Co., Ltd. Method of fabricating X-ray detecting device
US7285863 * Oct 12, 2004 Oct 23, 2007 Seiko Epson Corporation Pad structures including insulating layers having a tapered surface
US7335989 Aug 17, 2004 Feb 26, 2008 Rohm Co., Ltd. Semiconductor device and production method therefor
US7422984 Jun 28, 2004 Sep 9, 2008 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US7537972 May 20, 2005 May 26, 2009 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US7554113 * Feb 16, 2006 Jun 30, 2009 Semiconductor Energy Laboratory Co., Ltd. Organic semiconductor device
US7573469 * Jan 25, 2005 Aug 11, 2009 Semiconductor Energy Laboratory Co., Ltd. Display device
US7648910 * May 15, 2007 Jan 19, 2010 Winbond Electronics Corp. Method of manufacturing opening and via opening
US7662713 Dec 27, 2007 Feb 16, 2010 Rohm Co., Ltd. Semiconductor device production method that includes forming a gold interconnection layer
US8357571 * Sep 10, 2010 Jan 22, 2013 Cree, Inc. Methods of forming semiconductor contacts
US8597427 Aug 29, 2008 Dec 3, 2013 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US8673428 * Dec 27, 2007 Mar 18, 2014 Hitachi Chemical Company, Ltd. Engraved plate and substrate with conductor layer pattern using the same
US8901554 May 31, 2012 Dec 2, 2014 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including channel formation region including oxide semiconductor
US8969927 Mar 13, 2013 Mar 3, 2015 Cree, Inc. Gate contact for a semiconductor device and methods of fabrication thereof
US9087726 Nov 7, 2013 Jul 21, 2015 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9219165 Jun 8, 2015 Dec 22, 2015 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9343543 Jan 23, 2015 May 17, 2016 Cree, Inc. Gate contact for a semiconductor device and methods of fabrication thereof
US9343561 Mar 4, 2014 May 17, 2016 Cree, Inc. Semiconductor device with self-aligned ohmic contacts
US9449819 Oct 8, 2015 Sep 20, 2016 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9812583 Jun 20, 2016 Nov 7, 2017 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9818849 Oct 29, 2014 Nov 14, 2017 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device with conductive film in opening through multiple insulating films
US20020084475 * Dec 26, 2001 Jul 4, 2002 Kyo Ho Moon Method of fabricating X-ray detecting device
US20030030144 * Jul 26, 2002 Feb 13, 2003 Semiconductor Energy Laboratory Co., Ltd. Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US20030100151 * Nov 5, 2002 May 29, 2003 Satoru Okamoto Method of manufacturing a semiconductor device
US20040000673 * Jun 25, 2003 Jan 1, 2004 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US20040140471 * Oct 10, 2003 Jul 22, 2004 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20050017628 * Jul 22, 2003 Jan 27, 2005 Shiva Prakash Organic electronic device
US20050042785 * Jun 28, 2004 Feb 24, 2005 Semiconductor Energy Laboratory Co., Ltd., A Japan Corporation Method of manufacturing a semiconductor device
US20050046025 * Oct 12, 2004 Mar 3, 2005 Atsushi Kanda Semiconductor devices and methods of fabricating the same
US20050051899 * Aug 17, 2004 Mar 10, 2005 Goro Nakatani Semiconductor device and production method therefor
US20050098837 * Dec 6, 2004 May 12, 2005 Moon Kyo H. Method of fabricating X-ray detecting device
US20050112881 * Jul 13, 2004 May 26, 2005 Shiva Prakash Process for removing an organic layer during fabrication of an organic electronic device and the organic electronic device formed by the process
US20050140578 * Jan 25, 2005 Jun 30, 2005 Semiconductor Energy Laboratory Co., Ltd., A Japan Corporation Display device
US20050212046 * May 20, 2005 Sep 29, 2005 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US20060131573 * Feb 16, 2006 Jun 22, 2006 Semiconductor Energy Laboratory Co., Ltd. Organic semiconductor device and process of manufacturing the same
US20080054268 * Aug 31, 2007 Mar 6, 2008 Mitsubishi Electric Corporation Display device and method of manufacturing the display device
US20080116577 * Dec 27, 2007 May 22, 2008 Goro Nakatani Semiconductor device and production method therefor
US20080160756 * May 15, 2007 Jul 3, 2008 Winbond Electronics Corp. Method of manufacturing opening and via opening
US20090004872 * Aug 29, 2008 Jan 1, 2009 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US20100021695 * Dec 27, 2007 Jan 28, 2010 Susumu Naoyuki Engraved plate and substrate with conductor layer pattern using the same
US20120119260 * Sep 10, 2010 May 17, 2012 Fabian Radulescu Methods of Forming Semiconductor Contacts and Related Semiconductor Devices
CN100483632C Oct 25, 2004 Apr 29, 2009 株式会社半导体能源研究所 Method of manufacturing semiconductor device
WO2005041280A1 * Oct 25, 2004 May 6, 2005 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
U.S. Classification 438/149, 438/30, 257/E21.576, 257/E27.111, 257/E21.252, 257/E21.256, 257/E21.578
International Classification H01L21/84, H01L21/311, H01L21/768, H01L27/12, H01L21/77
Cooperative Classification H01L27/1244, H01L27/1248, H01L21/31116, H01L21/76804, H01L21/31138, H01L2924/0002, H01L27/12, H01L21/76801
European Classification H01L27/12T, H01L27/12, H01L21/311B2B, H01L21/311C2B, H01L21/768B2B, H01L21/768B
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUZAWA, HIDEOMI;KUSUYAMA, YOSHIHIRO;REEL/FRAME:011000/0874