Source: https://patents.google.com/patent/EP0133968A1/en
Timestamp: 2018-12-10 00:58:08
Document Index: 272497481

Matched Legal Cases: ['art 61', 'art 62', 'art 63', 'art 61', 'art 62', 'art 63', 'art 61', 'art 62', 'art 63', 'art 110']

EP0133968A1 - Solid state overcurrent detector - Google Patents
Solid state overcurrent detector Download PDF
EP0133968A1
EP0133968A1 EP19840108937 EP84108937A EP0133968A1 EP 0133968 A1 EP0133968 A1 EP 0133968A1 EP 19840108937 EP19840108937 EP 19840108937 EP 84108937 A EP84108937 A EP 84108937A EP 0133968 A1 EP0133968 A1 EP 0133968A1
EP19840108937
EP0133968B1 (en )
Ichirou C/O Fukuyama Seisakusho Arinobu
Solid state overcurrent detector is provided with a current sensor means (200) having an OR circuit (130) connected by its input terminals to output terminals of burden circuits (41, 42, 43) and a mean/effective value circuit (91, 92, 93) connected by their input terminals to said output terminals of the burden circuits, the output terminals of the mean/effective value circuit (91, 92, 93) are connected through an A/D convertor (100) to a microcomputer (110) having a first level discrimination means (1001) and a first time-current operation means (1002) with inverse time-current characteristics for various time interruptions responding to amount of overcurrent, and the output terminals of the OR circuit (130) is connected through a second level discrimination circuit (140) to a second time-current operating circuit (150) for instant interruption.
The present invention relates generally to a solid state overcurrent detector for detecting overcurrent, for instance, of power line or load, thereby to monitor, and further, be applied to protection of AC power lines, and more particularly concerns an overcurrent detector and a circuit interrupter suitable for most appropriate protection of AC power lines.
Hitherto, there has been, as an apparatus of a kind of the present invention such prior art apparatus as shown in FIG. 1 wherein a highest peak value of respective current of respective phase is detected, or another apparatus as shown in FIG. 2 wherein effective values or mean values of currents of respective phases of a set of power line are detected.
In the conventional apparatus of highest peak detection type of FIG. 1, on a set of AC lines R, S and T connected between power source side terminals 101, 102, 103 and load side terminals 101, 102 and 103, respectively, of three phases power lines 10, current transformers 21, 22 and 23 of a current sensor means 200 are provided, respectively. When an overcurrent flows in one or any lines of the power lines 10, transformed secondary currents flow through. secondary coils of the current transformers 21, 22 and 23, respectively, and therefrom to full-wave rectifier circuits 31, 32 and 33, which are connected across the secondary coils. Accordingly, a burden circuit 40, which is connected across series-connected rectified-output-terminals of the full-wave rectifiers 31, 32 and 33, detects a signal for the largest one of the rectified DC current which corresponds to the largest overcurrent among the currents of the three lines R, S and T. FIG. 3 shows a waveform of a full-wave rectifier. The burden circuit 40 comprises a resistance for transforming the current output of the peak value detection circuit 30 to a voltage output and a potentiometer for adjusting the output DC voltage to an appropriate voltage. FIG. 4 shows waveform of the output voltage of the burden circuit 40. The output of the burden circuit 40 is given to a level discrimination circuit 50 which discriminates the output voltage of the burden circuit 40 being below a predetermined voltage level, to issue an output signal. The output signal of the level discrimination circuit 50 is given to a time-current tripping circuit 60 which gives a operating signal responding to input signal levels. The time-current operating circuit 60 operates to issue an operating signal for tripping responding to time of continuation and level of output signal of the ievel discrimination circuit 50. Generally, the relation between the input signal level from the level discrimination circuit 50 and the tripping time is determined by considering heat resisting capacity of the power lines as shown in FIG. 5, wherein the tripping characteristic is of an inverse curve with regard to time and current on a graph when both the abscissa (current) and ordinate (time) are graduated in logarithmic scales. After a lapse of a predetermined time from starting of the above-mentioned time-current operating circuit 60, the time-current operating circuit 60 issues an output signal to an output circuit 70, which responding to its input circuit actuates an output device 80, for instance, a tripping means of a circuit interrupter, to resultantly actuate releasing contacts 201, 202 and 203 of the lines R, S and T, respectively, of the power lines.
As has been described with reference to FIG. 1, in the highest peak value detection type apparatus of FIG. 1, the voltage induced across both ends of the burden circuit 40 is, as shown in FIG. 4. The voltage waves for respective phase currents are different responding to the difference of overcurrents on the lines. That is, the apparatus of FIG. 1 works responding to a peak value of an overcurrent, and therefore a sharp peak in one phase only in a very short instance makes the apparatus work. In other words, the apparatus of FIG. 1 is substantially of the peak detection type, and therefore, this type apparatus can not detect the overcurrent being based on mean values or effective values for each phases for accurate detection of the overcurrent.
The time-current operating circuit 60 comprises a long time characteristic part 61, a short time characteristic part 62 and an instant time characteristic part 63, which are receiving output signal from the burden circuit 40. The long time characteristic part 61 produces a long time characteristic of curve A of FIG. 5(b), and the shorr time characteristic part 62 produces the short time characteristic as shown by curve B, and the instant time characteristic part 63 produces the instant time characteristic as shown by horizontal part C, respectively of FIG. 5(b). In FIG. 5(b) wherein both the abscissa (current) and the ordinates (time) are graduatedin logarithmic scales, a curve D shows time-current characteristic of heat resistant capacity of power lines and a curve E shows a time-current characteristic of heat resistance - capacity of loads. Since the curves D and E are of inverse shape as a whole, the curves A, B and C are of inverse type with respect to the current and time as a general view. The long time characteristic part 61, the short time characteristic part 62 and the instant time characteristic part 63 respectively produce output signal to be given to the output circuit 70 when level of the input signal becomes above respective predetermined levels. The output circuit 70 comprises, for instance, a thyristor 120 to be turned on by the output signal of the time-current operating circuit 60, thereby to actuate, for instance, a tripping device as the output device, thereby to release the interruption connectors 201, 202 and 203 to open the circuit connection in the power line.
FIG. 2 shows a representative conventional example of the mean effective value detection type apparatus. Operation characteristic of the apparatus of this kind is used for the operation of relatively long operation time such as for an overload protection relay of an electric motor, but not for instantaneous operation. In FIG. 2, the same numerals designate the corresponding parts and components to the first conventional example. The difference from the conventional apparatus of the first example is that the output tenninals of the rectifier circuits 31, 32 and 33 are respectively connected to both ends of the burden circuits 41, 42 and 43, respectively, and each one end of the burden circuit 41, 42 and 43 are connected in common to the ground. And, output terminals of the burden circuits 41, 42 and 43 are connected to three input terminals of a mean/effective value circuit 90, wherein input signals from the burden circuits 41, 42 and 43 are rectified thereby to produce DC output signals representing mean value or effective value of the input signals. Respective three output signals of the mean/effective value circuit 90 are given to the level discrimination circuit, and respective three output signals of the level discrimination circuit 50 are given to a time-current operating circuit 60. The time-current operating circuit 60 is constituted, generally to have the operation curve F shown in FIG. 1, which has a relatively long operation time characteristic. The output signals of the time-current operating circuit 60 are further given to an output circuit 70 which further gives output signals to an output apparatus 80, which is fed with power from an auxiliary source supply 801.
In the mean value type or effective value type conventional solid state overcurrent detector of FIG. 2, overcurrents in respective phases are accurately detected by producing mean value or effective value of the overcurrent by the mean/effective value circuit 90. On the other hand, this type apparatus has a shortcoming that its detection response is not sufficiently high since the mean/effective value circuit, which substantially have to contain integration circuits therein and having relatively long time constant. Accordingly, the conventional apparatus of mean/ effective value detection type of FIG. 2 is not suitable for detection of short-circuit currents or the like instantaneously increasing overcurrent.
Primary purpose of the present invention is to provide a solid state overcurrent detector and an improved circuit interrupter which comprises the solid state overcurrent detector.
The solid state overcurrent detector in accordance with the present invention comprises:
current sensor means provided for respective phases of AC power lines for issuing a first output signal corresponding to effective values or mean values of currents of respective phases and a second output signal corresponding to a highest peak value of the currents of respective phases,
first level discrimination means for discriminating levels of the first output signal of the current sensor means,
first time-current operating means for issuing a first time-current operating signal responding to output signal of the first level discrimination means,
first output means for issuing overcurrent detection signal responding to output signal of the first time-current operating means,
second level discrimination means for discriminating level of the second output signal from the current sensor means,
second time-current operating means for issuing a second time-current operating signal responding to output signal of the second discrimination means, and
second output means for issuing overcurrent detection signal responding to output signal of the second time-current operating means.
A circuit interrupter in accordance with the present invention comprises:
disconnectable contacts provided in respective lines of a set of AC power lines,
control means for controlling operations of the actuation means responding to an overcurrent under a predetermined condition,
current sensor means provided for respective phases of the AC power lines for issuing a first output signal corresponding to effective values or mean values of currents of respective phases and a second output signal corresponding to a highest peak value of the currents of respective phases,
first time-current tripping means for issuing a first time-current tripping signal responding output signal of the first level discrimination means,
first output means for issuing overcurrent detection signal responding to output signal of the first time-current tripping means,
second level discrimination for discriminating level of the second output signal from the current sensor means,
second time-current tripping means for issuing a second time-current tripping signal responding output signal of the second discrimination means, and
second output means for issuing overcurrent detection signal, responding to output signal of the second time-current tripping means.
The solid state overcurrent detector and the circuit interrupter in accordance with the present invention can carry out three kinds of operations responding to amount of overcurrent. That is, when the overcurrent is within a predetermined range, the overcurrent is detected taking account of heat resistance capacity of power lines and load connected thereto by basing on a maximum value among effective values or mean values of currents in respective phases. On the other hand, when the overcurrent is larger than the above-mentioned range, for instance, in acse of short-circuit current, an instantaneous peak value of any phase of the current as such is detected. In general, a large current of this kind can be considered as that of sinusoidal wave, and in this case, it is possible to carry out reduction from peak value to values corresponding to effective value or mean value. And, the circuit interrupter is actuated by means of such detected peak value. As a result of the above-mentioned general arrangement, the electric power lines and load are most preferably protected from accident, and as well, undesirable interruption of power service at an overcurrent of a negligibly short instance can be avoided. Furthermore, taking account of charging and discharging of heat in the electric power lines and loadmost appropriate monitoring and protection thereof can be carried out by the apparatus of the present invention. BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is the circuit block diagram of the representative conventional solid state overcurrent detector or a circuit interrupter.
FIG. 2 is the circuit block diagram of another type representative conventional example of a solid state overcurrent detector or a circuit interrupter.
FIG. 3 is a graph showing waveform in the circuit of FIG. 1 or FIG. 2.
FIG. 4 is a graph showing waveform in another circuit in FIG. 1 or FIG. 2.
FIG. 5(a) is the current vs. time characteristic graph of heat resistance capacity of general electric power lines and the required overcurrent detection characteristic for such electric power lines.
FIG. 5(b) is the current vs. time characteristic graph of the conventional solid state overcurrent detector or the conventional circuit interrupter of FIG. 1.
FIG. 6 is a circuit block diagram of a first embodiment in accordance with the present invention.
FIG. 7 is a detailed circuit diagram of a microcomputer 110 of the circuit of FIG. 6.
FIG. 8 is a flow chart showing operation of the microcomputer shown in FIG. 7.
FIG. 9 is a circuit block diagram of a second embodiment in accordance with the present invention.
FIG. 10 is a circuit block diagram of still another embodiment.
Hereinafter, details of the invention is described with reference to the drawings FIG. 6 and thereafter.
In a first embodiment shown in FIG. 6, on a set of power lines R, S and T of three phase power lines 10, current transformers 21, 22 and 23 of a current sensor means 200 are provided, respectively. Full-wave rectifiers 31, 32 and 33 are connected with its two input lines across both output lines of the current transformers 21, 22 and 23, respectively. Burden circuits 41, 42 and 43 are connected with their input lines to output lines of the full-wave rectifiers 31, 32 and 33, respectively, and each one of the input lines of the burden circuits 41, 42 and 43 are connected in common to the ground. The other input terminals of the burden circuits 41, 42 and 43 are connected to input terminals of an OR circuit 130, which consists of three diodes 131, 132 and 133 and output terminal of which are connected in common as an output terminals of the OR circuit 130. Adjustable output terminals of the burden circuits 41, 42 and 43, wherefrom output signals can be obtainable in desirably adjusted levels, are connected to input terminals of mean/effective value circuits 91, 92 and 93 of mean/effective value means 90, which are for producing mean values or effective values of the signals from the burden circuits 41, 42 and 43. The output terminals of the mean/effective value circuits 91, 92 and 93 are connected to input terminals of an A/D convertor 100. A microcomputer 110 is connected to the output terminal of the A/D converter 100. The output terminal of the OR circuit 130,as a second output terminal of the sensor means 200,is connected to the A/D convertor 100 and the microcomputer 110 through a power source circuit 300,which is generally a constant voltage circuit. Furthermore, the second output terminal of the current sensor means 200 is connected to a second level discrimination circuit 140 which, for instance, comprises at least one zener diode. The second level discrimination circuit 140 is connected to a second time-current tripping circuit 150. Output terminals of the microcomputer 110 and the second time-current operating circuit 150 are connected to a first and a second output circuit 120 and 120', respectively, for instance, comprising each one thyristor, for actuating a common device, for instance, a releasing device 80 for carrying out disconnection of line switches 201, 202 and 203. A first indicator 180 and a second indicator 180' are for indicating which circuit has operated. The microcomputer 110 comprises a first level discrimination means and a first time-current operating means as is described later herein.
The current sensor means 200 issues from the mean/effective value circuit 90 signals corresponding to mean values or effective values of the current in the power lines R, S and T 7and also issues from the OR circuit 130 the second output signals corresponding to peak value of the current in the power lines R, S and T. The second output signal of the current sensor means 200 is given through the second level discrimination circuit 140 to the second time-current operating circuit 150. The A/D convertor 100 has an analog-multiplexer part for time-sharingly select input signals of the mean/effective value. circuits 91, 92 and 93 in turn, to carry out A/D conversion. The outputs of the A/D convertor 100 is given to the microcomputer 110. The A/D convertor 100 and the microcomputer 110 are fed with a constant voltage D/C current from the power source circuit 300. The output signal of the microcomputer 110 is given to a first output circuit 120. The first output device is the first operation indicator 180 plus a releasing device 80 of an interrupter by which moving contacts 201, 202 and 203 are drived. The second output device is the second indicator 180' and the same releasing device 80. Thus, by means of the operation of the first or the second indicator, reason of disconnecting operation of the interrupter is shown.
FIG. 7 is a circuit block diagram of the microcomputer 110. As shown in FIG. 7, the microcomputer 110 comprises a central processor unit 111, a read-only memory 114, a random-access memory 115, an I/O port 116,a data bus 112 and an address bus 113. Parts of the data bus 112 and the address bas 113 are also connected to the A/D convertor 100. The read-only memory 114 contains a program for executing necessary signal processingand also data for a long time characteristic, a short time characteristic and an instant time characteristic of the first time-current operating means. The central processor unit 111 contains clock signal means necessary therefor. The random-access memory 115 functions as a register which is necessary for the signal processing.
Signal processing flow of the above-mentioned microcomputer 110 is described with reference to a flow chart shown in FIG. 8. As shown in FIG. 8, the microcomputer contains as fundamental functions,at least the first level discrimination means 1001 for discriminating level of input signal from the A/D convertor 100 and the first time-current operation means 1002 for producing necessary time-current characteristic responding to input signal from the A/D convertor._ Furthermore, the microcomputer contains a resetting means 1003, which is constituted in a manner to carry out a resetting, with a predetermined resetting time-schedule, when at least one of said first time-current operating means 1002 and said second time-current operating means 150 falls below respective predetermined levels. The time schedule is designated to correspond to decrease rate of heat discharging characteristics of the electric power lines and the loads.
The operation of the embodiment configurated as above-mentioned is as follows: when overcurrent(s) flows in the AC power lines 10, output currents of the current transformers 21, 22 and 23, coupled to the AC power lines R, S and T of the AC power lines 10, correspondingly produces output currents at predetermined transforming ratios. The output currents are rectified by the full-wave rectifiers 31, 32 and 33, respectively. The rectified output currents of the full-wave rectifiers 31, 32 and 33 are fed to respective burden circuits 41, 42 and 43. The wave forms of the signal voltages induced across the burden circuits 41, 42 and 43 becomes as shown in FIG. 3. The output signals of the burden circuits 41, 42 and 43 are transformed into mean values or effective values thereof by mean/effective value means 91, 92 and 93 of the mean/effective value circuit 90. Then the output signals of the mean/effective value circuit 90 are given to A/D converter 100, wherein the analog multiplexer part time-sharingly selects and A/D converts the input signal into digital signals. These digital signals are fed to the microcomputer 110, The microcomputer 110 carries out level discrimination of digital input signal thereto in accordance with a predetermined program stored in the read-only memory 114. Furthermore, basing on the results of the level discrimination, a predetermined time-current operation is carried out, thereby to issue output signal from the output port 116. That is, the microcomputer 110 functions as the first level discrimination means and the first time-current operating means. The above-mentioned time-current operation is carried out, for instance, along the inverse long time-current characteristic of part A of FIG. 5(b). The output signal issues from the output port 116 of the microcomputer 110 is fed to the gate of the thyristor 120, which is then turned on to drive the output device 80. Accordingly, the overcurrent indicator 180 indicates the occurrence of the overcurrent and at the - same time the releasing device 80 actuate the interrupting connectors 201, 202 and 203. The above-mentioned time-curremt characteristic of the curves A, B and C are designed by taking account of the capacity of fuses in the upper stream part of the power line 10.
On the other hand, the output of the full-wave rectifier 31, 32 and 33 are given to the OR circuit 130 consisting of diodes 131, 132 and 133. Since the output terminal of the OR circuit 130 is connected to the second level discrimination circuit 140 which, for instance, comprises at least one zener diode. When one input signal to the OR circuit 130 exceeds the second level, the discrimination circuit 140 gives output signal to the second time-current operating circuit 150, which accordingly ca-ries out necessary time-current operation, and thereby triggers the gate of the thyristor 120'. The time-current operation in this case is, for instance, as shown by the part B of the short time current inverse characteristic or the part C of instantaneous time-current characteristic. By the above-mentioned turn-on of the thyristor 120', the output device 80 is actuated, thereby its indicator 180' indicates the kind of the overcurrent and also drives the interruption connectors 201, 202 and 203. As the output device 80, use of a low power consumption type release device is recommendable. Since simple OR circuit 130 is combined with simply configurated second level discrimination circuit 140, the second time current operation circuit 150 can respond very quick to a large overcurrent without any delay.
Instead of the above-mentioned OR circuit 130 consisting of three diodes 131, 132 and 133, an OR circuit may be constituted with utilizing known highest value selection function of the microcomputer 110 by utilizing a part thereof. In such case, in the flow chart of FIG. 8, between the A/D conversion step F3 and the first level detection step 1001, a known sub-routine for the function of the highest value selection, which is substantially the same as the OR circuit 130, may be inserted.
Nextly, detailed signal processing in the microcomputer 110 is described with reference to the main flow chart of FIG. 8: Firstly, when the microcomputer 110 is started into an operable state, the program starts at Fl and the system is initiallized in F2. Namely, I/O port is set, flags are set and necessary resets are made, and the flow comes to main processing flow. Nextly, operation of the A/D convertor l10 containing the analog multiplexer part is executed. In this controlling operation, effective values or mean values of currents corresponding to the currents in the power lines R, S and T are time-sharingly selected, A/D converted and stored in the random access memory 115 in the microcomputer 110. Then, discrimination operation is executed such that, with respect to input signal data stored in the random access memory 115, the discrimination whether the input data are overcurrent or not is executed, in the step 1001. When the input data are not an overcurrent, the flow goes back to the step F3 through F5. Nextly, when an overcurrent comes, firstly flag H for representing heat charging is set in the step F4, and bits for heat charging is added for every predetermined unit times by utilizing random access memory 115 or a register in the central processor unit 114, so as to count time responding to amount of input signal level. The heat charging bits are selected in order to realize time-current operation along the characteristic curves of FIG. 8. Then, the added bits number is discriminated to examine whether the time is up for the selected time-current operation of the predetermined characteristic. And as a result, when the added bit number does not yet reach the predetermined number, the flow goes back from the step F6 to the step F3. When the added bits number reaches the predetermined number, In other words, the time is up, output is issued through the I/O port 116 to drive the thyristor 120, thereby to actuate the first indicator 180 and the output device 80. The steps F3 through F7 work as starting means.
Nextly, operation of heat discharging routine, namely, the routine for resetting the time-current operation is described. As above-mentioned, when the heat charging flag H is set and time is being count to some extent, and A/D converted digital data become below the predetermined level, the flow gets out of the level discrimination routine of 1001? And setting of heat charging flag H for representing the state immediately before itself is discriminated by the step F5. As a result, when the heat charging flag H is not set, the flow goes back to the A/D conversion step of F3. On the contrary when the heat charging flag H is set, from the bit number accumulated during the heat charging routine, discharge bit number is subtracted at the step 1003 at every predetermined unit times. When balance of counted number of the bit becomes 0 as a result of the subtractions in the step 1003, the heat charging flag H is reset in the step F9. And the heat discharging routine goes back from the step F9 to the A/D conversion step F3. When the counted number of the bit is not entirely reset, the heat charging flag H is not reset and the heat discharging routine goes back from the step F8 to the A/D conversion step F3. The steps F3 through F9 works as resetting means.
As above-mentioned, the microcomputer gives most - appropriate time-current operating characteristic taking account of heat charging and heat discharging in the electric power lines and loads. Incidentally, addition or subtraction of the heat charging and heat discharging can be executed in the inverse order to the above-mentioned embodiment.
FIG. 9 shows another embodiment in accordance with the present invention, wherein an OR circuit 160 consisting of three diodes 161, 162 and 163 which receives output signals of the mean/effective value circuits 91, 92 and 93, respectively and issues output signal to the A/D convertor 100. And the output signals of the microcomputer 110 and the second time-current operating circ uit 150 are given through an OR circuit 121 to a single indicator 180 and a single output device 80. Other parts and components are substantially the same as the first embodiment of FIG. 6. As a result of the above-mentioned configuration, the A/D convertor 100 receives the largest signal among the output signals of the mean/effective value circuits 91, 92 and 93. By comprising the OR circuit 160 for selectively issuing highest value of the output signals of the mean/ effective value circuits 91, 92 and 93, this embodiment does not need any analog multiplexer in the A/D convertor 100. Accordingly, the operation of the microcomputer and A/D convertor becomes simpler than the example of FIG. 6. Since the OR circuit 160 is used, the highest output signal of the mean/effective value circuits 91, 92 and 93 corresponding to the highest overcurrent in all phases, is given as the input signal to the A/D convertor 100 without delay, even at an overcurrent only in one phase, the circuit can detect the overcurrent in a very short time.
Apart from the above-mentioned embodiments utilizing the microcomputer 110, the function of the computation can be made by an analog computer, too. Such embodiment is shown in FIG. 10, wherein an analog processing circuit 111 is provided instead of the A/D converter 100 and the microcomputer 110 of the previous embodiments. The analog processing circuit 111 comprises a level detector 1113 having a level detection circuit 1111 and a switching circuit 1112, a charge control circuit 1116 having a long-time characteristic circuit 1114 and a short-time characteristic circuit 1115, a discharge control circuit 1117, a charge discharge circuit 1118 and a level detection circuit 1119. When the level detection circuit 1111 detects an overcurrent through the intensity of the signal from the OR circuit 160, it makes the switching circuit 1112 to issue an output to the charge control circuit 1116. Then, either of the long-time characteristic circuit 1114 or the short-time characteristic circuit 1115 of the charge control circuit 1116 issues output to the charge-discharge circuit 1118, which comprises a capacitor and several resistors. The charge control circuit 1116 functions for the heat charging routine of the flow chart of FIG. 8, and the discharge control circuit 1117 functions for the heat discharging routine of the flow chart of FIG. 8. Then the level detection circuit 1119 issues a first time-current operating signal.
In the above-mentioned embodiments of the present invention, as the current sensor means 200, any current sensor means such as Hall, magnetic resistance device or the like combined with suitable amplifier can be utilized instead of the circuit shown in the embodiments. Furthermore, as a means to obtain absolute value of the detected current, known means using operational amplifiers may be used. Moreover, by individually connecting indicators to the first time-current operating output and the second time-current operating output, finding of overcurrent or trouble on the individual phase is possible. Furthermore, by providing the heat discharging routine in the microcomputer 110 or the computing part 110', most appropriate protection in view of heat charging and discharging is obtainable, thereby enabling attainment of improved power supply service, as well as, higher protection of the power lines and loads.
1. A solid state overcurrent detector comprising:
a current sensor means provided for respective phases of AC power lines for issuing a first output signal corresponding to effective values or mean values of currents of respective phase and a second output signal corresponding to a highest peak value of said currents of respective phases,
first level discrimination means for discriminating levels of said first output signal of said current sensor means,
first time-current operating means for issuing a first time-current operating signal responding to output signal of said first level discrimination means,
first output means for issuing overcurrent detection signal responding to output signal of said first time-current operating means,
second level discrimination means for discriminating level of said second output signal from said current sensor means,
second time-current operating means for issuing a second time-current operating signal responding to output signal of said second discrimination means, and
second output means for issuing overcurrent detection signal responding to output signal of said second time-current operating means.
2. A solid state overcurrent detector in accordance with claim 1, which further comprises:
peak value detection means provided as a stage between said current sensor means and said first level discrimination means for detecting a peak value among said output signals of said current sensor means and issuing an output signal to said first time-current operating means.
3. A solid state overcurrent detector in accordance with claim 2, wherein
said first peak detection means is a diode OR circuit.
4. A solid state overcurrent detector in accordance with claim 1, 2 or 3, wherein
said current sensor means comprises burden circuits connected with its one end to a common potential point, and a diode OR circuit for obtaining said second output signal from the output signals of said burden circuits.
5. A solid state overcurrent detector in accordance with claim 1, 2 or 3, wherein
at least one of said first time-current operating means or said second time-current operating means comprises starting means for starting time-current operation when input signal becomes above a predetermined level and a resetting means for resetting said time-current operation when said input signal becomes below a predetermined level.
6. A solid state overcurrent detector in accordance with claim 5, wherein
when input signal to at least one of said first and second time-current operating means becomes below a predetermined level, said resetting means carries out a resetting along a predetermined heat discharging rate characteristic.
7. A solid state overcurrent detector in accordance . with claim 1, 2, 3 or 6, wherein
at least one of said first discrimination means and said first time-current operating means comprises a microcomputer.
8. A solid state overcurrent detector in accordance with claim 7, wherein
said second level discrimination means and said second time-current operating means are connected in a substantially direct way without data processing with each other.
9.- A solid state overcurrent detector in accordance with claim 7, wherein
said first time-current operating means has an inverse time-current characteristic.
10. A solid state overcurrent detector in accordance with claim 8, wherein
said second time-current operating means has an instant-responsive characteristic.
11. A solid state overcurrent detector in accordance with claim 1, 2 or 3, wherein
said current sensor means has a means for rectifying detection current into DC current, thereby feeding it as operation power for whole circuit of the solid state overcurrent detector.
12. A solid state overcurrent detector in accordance with claim 1, 2 or 3, wherein
said first and second output means is a single means which receives both output signals of said first and second time-current operating means through an OR circuit.
a releasing device for actuation of disconnection of said disconnectable contacts, and
control means for controlling operations of said releasing means responding to an overcurrent under a predetermined condition,
current sensor means provided for respective phases of said AC power lines for issuing a first output signal corresponding to effective values or mean values of currents of respective phases and a second output signal corresponding to a highest peak value of said currents of respective phases,
first time-current tripping means for issuing a first time-current tripping signal responding output signal of said first level discrimination means,
first output means for issuing overcurrent detection signal responding to output signal of said first time-current tripping means,
second time-current tripping means for issuing a second time-current tripping signal responding output signal of said second discrimination means, and
second output means for issuing overcurrent detection signal responding to output signal of said second time-current tripping means.
14. A circuit interrupter in accordance with claim 13, which further comprises:
peak value detection means provided as a stage between said current sensor means and said first level discrimination means for detecting a peak value among said output signals of said current sensor means and issuing an output signal to said first time-current tripping means.
15. A circuit interrupter in accordance with claim 14, wherein
16. A circuit interrupter in accordance with claim 13, 14 or 15, wherein
17. A circuit interrupter in accordance with claim 13, 14 or 15, wherein
at least one of said first time-current tripping means or said second time-current tripping means comprises starting means for starting time-current operation when input signal becomes above a predetermined level and a resetting means for resetting said time-current operation when said input signal becomes below a predetermined level.
18. A circuit interruptor in accordance with claim 17, wherein
19. A circuit interruptor in accordance with claim 13, 14, 15 or 18, wherein
at least one of said first discrimination means and said first time-current tripping means comprises a microcomputer.
20. A circuit interruptor in accordance with claim 19, wherein
said second level discrimination means and said second time-current tripping means are connected in a substantially direct way without data processing with each other.
21. A circuit interruptor in accordance with claim 19, wherein
said first time-current tripping means has an inverse time-current characteristic.
22. A circuit interruptor in accordance with claim 20, wherein
said second time-current tripping means has an instant-responsive characteristic.
23. A circuit interruptor in accordance with claim 13, 14 or 15, wherein
said current sensor means has a means for rectifying detection current into DC current, thereby feeding it as operation power for said control means.
24. A circuit interruptor in accordance with claim 13, 14 or 15, wherein
EP19840108937 1983-07-29 1984-07-27 Solid state overcurrent detector Expired EP0133968B1 (en)
JP14028383A JPS6030016A (en) 1983-07-29 1983-07-29 Circuit breaker
JP140285/83 1983-07-29
JP14028483A JPH0359656B2 (en) 1983-07-29 1983-07-29
JP140284/83 1983-07-29
JP14028283A JPH0359655B2 (en) 1983-07-29 1983-07-29
JP14028583A JPS6032211A (en) 1983-07-29 1983-07-29 Circuit breaker
JP140282/83 1983-07-29
JP140283/83 1983-07-29
EP0133968A1 true true EP0133968A1 (en) 1985-03-13
EP0133968B1 EP0133968B1 (en) 1989-06-07
ID=27472291
EP19840108937 Expired EP0133968B1 (en) 1983-07-29 1984-07-27 Solid state overcurrent detector
EP (1) EP0133968B1 (en)
DE (1) DE3478642D1 (en)
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EP0133968B1 (en) 1989-06-07 grant
DE3478642D1 (en) 1989-07-13 grant
Ref document number: 3478642
1989-09-06 ITF It: translation for a ep patent filed
1989-09-22 ET Fr: translation filed
1995-11-10 ITPR It: changes in ownership of a european patent