Source: https://patents.google.com/patent/US5361364A/en
Timestamp: 2019-09-21 16:51:42
Document Index: 211492457

Matched Legal Cases: ['art 603', 'art 603', 'art 603', 'art 603', 'art 603', 'art 603', 'art 603', 'art 603', 'art 603', 'art 603', 'art 603', 'art 603', 'art 825', 'art 825', 'art 603', 'art 825', 'art 825', 'art 825', 'art 825', 'art 825', 'art 825', 'art 825', 'art 826', 'art 825', 'art 825']

US5361364A - Peripheral equipment control device - Google Patents
Peripheral equipment control device Download PDF
US5361364A
US5361364A US07/795,697 US79569791A US5361364A US 5361364 A US5361364 A US 5361364A US 79569791 A US79569791 A US 79569791A US 5361364 A US5361364 A US 5361364A
US07/795,697
Yukari Nagashige
Shoichi Miyazawa
Kouji Shida
1990-11-22 Priority to JP31845090 priority Critical
1990-11-22 Priority to JP2-318450 priority
1990-11-30 Priority to JP32890390 priority
1990-11-30 Priority to JP2-328903 priority
1994-05-11 Assigned to HITACHI, LTD. reassignment HITACHI, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KOJIMA, SHINICHI, MIYAZAWA, SHOICHI, NAGASHIGE, YUKARI, SHIDA, KOUJI, WATANABE, KUNIO
1994-11-01 Publication of US5361364A publication Critical patent/US5361364A/en
2007-08-30 Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HITACHI, LTD.
A peripheral equipment control LSI interposed between an SCSI bus connected to a main CPU and peripheral equipment such as a file device. The LSI is divided into two major blocks. One block recognizes an SCSI protocol ID signal sent over the SCSI bus. The other block generates a signal that causes the other block to leave a sleep state (low power dissipation mode). In a state in which a command is awaited from the main CPU, the peripheral equipment control LSI allows the block containing the ID recognition part to remain active while the other block is kept in the sleep state. On receiving an ID-based selected (access) signal from the main CPU, the LSI detects the start of an access operation and causes the other block to leave its sleep state and to become active.
The present invention relates to structural improvements for lower power dissipation of peripheral equipment for use with workstations and personal computers. More particularly, the invention relates to structural improvements for lower power dissipation of semiconductor integrated circuits within peripheral equipment control devices.
For a first prior art example, take some peripheral control LSI's having an input terminal dedicated to specify low power dissipation mode. Receiving signals from an external microprocessor or a power dissipation controller through such dedicated terminal, this type of LSI maintains low power dissipation mode during designated periods. That is, part or all of the clock pulses are stopped during designated periods for those digital circuits in a peripheral control LSI which operate on a reference clock signal. The result is a reduced lever of power dissipation. In another arrangement, the power from a current source circuit is also cut off to part or all of the analog circuits in the peripheral control LSI during designated periods. This further lowers the power dissipation involved.
FIG. 18 schematically shows the DRR040C as typical prior art peripheral equipment. The DRR040C comprises disks 1801 which are magnetic media; head 1802 that read magnetically recorded information from the disks 1801; a head actuator 1803 that moves the heads 1802 to a target position on the disks 1801; a spindle motor 1804 that rotates the disks 1801; an actuator control circuit 1805 that controls the operation of the head actuator 1803; a CPU (control processing unit) 1806 that controls the whole operation of the DRR040C; a spindle motor control circuit 1807 that controls the spindle motor 1804 in accordance with control signals from the CPU 1806; a digital-to-analog converter 1808 that converts to analog format the digital information coming from the CPU 1806 and forwards the converted information to the actuator control circuit 1805; a read/write circuit 18109 that shapes into a waveform the signal read from the heads 1802 for conversion to a pulse train; a hard disk controller 1811 that converts to parallel data the pulse train generated by the read/write circuit 1810; an analog-to-digital converter 1809 that converts to digital format the head position and other analog information detected by the read/write circuit 1810 and sends the converted information to the CPU 1806; a buffer 1813 that temporarily accommodates signals from the disks 1801 or from an AT bus 1812 in order to adjust the difference in read rate between the AT bus 1812 and the disks 1801; and an AT bus control circuit 1814 that controls the AT bus 1812 under direction of the CPU 1806. It is to be noted that the AT bus is a bus having the PT/AT (a registered trademark of International Business Machines Corp.) Interface.
When not receiving or executing a command from the AT bus, the DRR040C operates as follows so as to reduce power dissipation:
4. Upon receipt of a sleep command from the AT bus, the DRR040C enters sleep mode, which is a fully low power dissipation mode. On entering sleep mode, DRR040C causes the AT bus control circuit 1814 to leave standby mode and to enter sleeping state. In sleep mode, the DRR040C accepts no commands from the AT bus; only a reset cam activate the drive.
Operating in the manner described, the DRR040C reduces power dissipation when not receiving or executing commands from its host computer.
In the second prior art example, there is no consideration for the current consumed by the AT bus control circuit 1814 in standby mode. This leaves room for an increase in power dissipation. In sleep mode, which is a fully low power dissipation mode, no commands are accepted; only a reset from the host computer or its equivalent activates the drive. This neglect for the responsive characteristic of the drive is liable to increase the overhead of the host computer.
It is therefore an object of the present invention to provide structural improvements for low power dissipation not only in peripheral equipment but also in the control device that controls such equipment.
In carrying out the invention and according to one aspect thereof, there is provided a peripheral equipment control device connected to a bus which is connected such external processing means as a processor, the peripheral equipment control device comprising access start detecting means for detecting the start of an access operation from the external processing means; access end detecting means for detecting the end of the access operation; and power dissipation controlling means for causing low power dissipation mode to be left in response to an output from the access start detecting means and causing that mode to be entered in response to an output from the access end detecting means.
The access start detecting means, access end detecting means and power dissipation controlling means are located inside the peripheral equipment control device or peripheral equipment control LSI. The peripheral equipment control device is a control device for peripheral equipment associated with a main CPU. Illustratively, this type of control device includes a file controller, a display controller, a keyboard controller, a printer controller and a communication controller. The peripheral equipment control LSI is a semiconductor integrated circuit acting in the same manner as the peripheral equipment control device.
The power dissipation controlling means according to the invention cuts off power, in low power dissipation mode, to the clock source of digital circuits or to analog circuits in major parts of the control device or LSI. This causes the major parts of the control device or LSI to stop operating and keeps them in low power dissipation state. When the host computer or main CPU initiates access such as setting of a command or detection of status to the control device or LSI, the access start detecting means, which is in constant operation, detects the start of such access. In response to the detection, the power dissipation controlling means causes the control device or LSI to leave low power dissipation mode. When the end of such access is detected by the access end detecting means, the power dissipation controlling means again causes low power dissipation mode to be entered accordingly.
According to the invention, furthermore, in an SCSI system wherein the host computer or main CPU is connected to peripheral equipment via an SCSI bus, the access start detecting means acts as ID recognizing means. This recognizing means detects that the peripheral equipment control device or LSI is selected by the host computer or main CPU.
FIG. 1 is a circuit block diagram of a peripheral equipment control device practiced as a first embodiment of the invention;
FIG. 3 shows a typical data processor incorporating a peripheral equipment control device or peripheral equipment control LSI embodying the invention. This type of data processor, used illustratively in a workstation or a personal computer, has a main CPU 14, a ROM 15 and a RAM 16 connected to a bus 50. The bus 50 is connected with a file controller 17, a display controller 18, a keyboard controller 19, a printer controller 20 and a communication controller 21. The controllers 17, 18, 19, 20 and 21 are in turn connected respectively to a file device 22, an LCD or CRT display 23, a keyboard 24, a printer 25, and a communication line, now shown.
FIG. 1 is a circuit block diagram of a peripheral equipment control device or a single-chip peripheral equipment control LSI practiced as the first embodiment of the invention. In FIG. 1, a power dissipation control circuit 2 stops internal clock pulse generation when the control device or LSI is not receiving any command from or otherwise accessed by the main CPU 14 over the bust 50. That is, the power dissipation control circuit 2 stops the operation of registers 8 through 10 and I/O control circuits 11 through 13 and places them in sleep mode to lower power dissipation. In that sense, the power dissipation control circuit 2 acts as power dissipation controlling means which also comprises the function of access start detecting means. At this point, the power dissipation control circuit 2, an address latch 3, a latch 6 an address decoder 4 and gate 5 are in constant operation.
Later, upon receipt of a command from main CPU 14, the power dissipation control circuit 2 detects the start of that command (i.e., access) on the basis of a chip select or write strobe signal from the main CPU or of an output from an address decoder 4 or from a gate 5. Then the power dissipation circuit 2 resumes supply of the internal clock signal to the registers 8 through 10 and the I/O control circuits 11 through 13.
Given the internal clock signal, the registers 8 through 10 and the I/O control circuits 11 through 13 are activated. The command retained by the latch 6 is moved to command registers included among the registers 8 through 10. This allows the command from the main CPU 14 to be executed. After the command has been processed, the I/O control circuits 11 through 13 send a command end signal to a NOR gate 1 that acts as access end detecting means. In turn, an output of the NOR gate 1 is input to the power dissipation control circuit 2. Thus the control circuit 2 again stops the internal clock pulse output and returns to low power dissipation mode.
If the peripheral equipment control device or LSI is accessed by the main CPU 14 for something other than command setting, the power dissipation control circuit 2 detects the start of an access operation, renders the control LSI or the control device operable and leaves low power dissipation mode, all based on a chip select signal, a write strobe signal or a read strobe signal. It is to be noted that the address latch 3, a latch 6, an address decoder 4 and gate 5 are in constant operation. Write data is introduced internally through the latch 6 while read data is output to the outside via the gate 7. Because this intermittent kind of access is noted for its short duration per cycle, the end such access is detected by the access end detecting means and low power dissipation mode is again entered accordingly.
Below is a description of how the power dissipation control circuit 2 is constructed and operated with reference to the block diagram of FIG. 2 as well as to the timing charts of FIGS. 4 and 5. The main CPU 14 sends address or command data along with such control signals as chip select and write strobe to the power dissipation control circuit 2. In turn, the power dissipation control circuit 2 sets an RS flip-flop 29 via gates 26 and 28 at a time t1 in accordance with the chip select and write strobe signals, as shown in FIG. 4.
Then an internal write strobe signal is output by the flip-flop 34. A command write strobe signal is input to a flip-flop 41 via the address decoder 4 at a time t3. At this point, the command write strobe signal moves the command retained by the latch 6 to the command registers among the registers 8 and 10. This starts the processing of the I/O control circuits 11 through 13. The output of the flip-flop 41 brings about a state in which a command end signal may be accepted via the gate 1 of the I/O control circuits 11 through 13.
At the end of the command processing by each of the I/O control circuits 11 through 13, the command end signal passes through the gate 1 and enters a gate 38 of the power dissipation control circuit 2 at a time t4. This causes the RS flip-flop 29 to be reset at time t5 via a gate 39 and a flip-flop 40. The output of the gate 29 controls the gate 33 via the flip-flops 31 and 32, stops the internal clock signal, and causes low power dissipation mode to be entered again at a time t6.
The ID recognition part 603 has a function of detecting whether or not the SCSI system is selected by another SCSI system via the SCSI bus. That is, the ID recognition part 603 acts as the access start detecting means. When the part 603 detects that the SCSI system is selected by another SCSI system, the part 603 supplies the function block 604 with a sleep leave signal for activating part or all of the minimally required circuits. That is, clock pulses are input to these minimally required circuits for their activation. With the ID recognition part 603 and the function block 604 using a separate power supply each, the function block 604 has its power supply cut off when entering sleep mode. The function block 604 is again connected to its power supply upon receipt of the sleep leave signal 605 from the ID recognition part 603. In this manner, the power consumption in sleep mode is minimized.
The SCSI control LSI in the second embodiment contains a sleep mode entry register or receives an input signal for entry into sleep mode. When the LSI has a sleep mode set value set to its sleep mode entry register or has the sleep mode entry signal asserted, the entire circuit except for the ID recognition part 603 enters sleep mode. In receiving a sleep leave signal from the ID recognition part 603, the SCSI control LSI causes each circuit block to leave sleep mode in accordance with the value set to the register. The register value is used to manage sleep leave information for each circuit block. This scheme minimizes current dissipation depending on the selection status of the ID recognition part 603 and on the system configuration. As described, the SCSI control LSI has the sleep leave signal 605 output by the ID recognition part 603 toward an external circuit in addition to ordinary interrupt signals. When the ID recognition part 603 detects that the SCSI control LSI is selected by another SCSI system, the part 603 asserts the external circuit sleep leave signal 605. This causes the other function block 604, disconnected from power in a state awaiting command input from another SCSI system, to be connected again to its power supply circuit so that the block immediately leaves sleep state with ease.
FIG. 8 is a circuit block digram of an SCSI bus control circuit 701 contained in the second embodiment. For illustration expediency, the right-hand side of the figure is connected to the SCSI bus 601 and the left-hand side thereof to an internal bus 1815. That is, the construction of FIG. 7 is mirrored crosswise in FIG. 8. The SCSI bus control circuit 701 is roughly divided into function blocks 841, 842 and 843 indicated by broken lines.
In FIG. 8, an internal CPU data bus 801 is used by the CPU 1806 to gain access to the SCSI bus control circuit 701. Part of an internal bus 15 is connected to the data bus 801. A read/write controller 802 uses such signals as RD/, WR/, CS/, DACK/ and DREQ output by the CP 1806 and the hard disk controller 1811 in order to access internal registers 803 through 811, 815 through 818 and an FIFO 819 inside the SCSI bus control circuit 701. In this specification, the symbol "/" following a signal name means an inverted signal. Of the internal registers provided, 803 is a transfer count register, 804 is a destination ID register, 805 is a transfer count register, 806 a configuration-1 register, 807 a configuration-2 register, 808 a synchronous offset register, 809 a synchronous transfer period register, 810 a time-out register, and 811 a clock conversion register. By setting values to these registers, the CPU 1806 controls the SCSI protocol.
FIFO's 819 and 820 are capable of temporarily storing the data transferred from the CPU 1806 or buffer 1813 to the SCSI bus, or from the SCSI bus or buffer 1813 to the CPU 1906. A parity generator and checker 821 deals with the data transferred from the CPU 1806 or buffer 1813 to the SCSI bus, or from the SCSI bus to the CPU 1806 or buffer 1813. A sequencer 823 controls the SCSI protocol in accordance with the settings in the registers 803 through 811 and with the SCSI bus control signal value given by the receiver 814. Thereafter, the sequencer 823 outputs the result of the processing to the status register 816 and interrupt register 817.
An ID recognition part 825 is a key block in the second embodiment. This part 825, contained in the function block 841, corresponds to the ID recognition part 603 acting as the access start detecting means shown in FIG. 6. The ID recognition part 825 monitors the values of SCSI bus control signals BSY/ and SEL/. When the BSY/ is brought High and SEL/ Low, the part 825 compares an own-ID, which is the ID of the second embodiment, with the value of an SCSI data bus SDB0/-SDB7/. If there is a match between the two values, a sleep leave signal 833 is output.
A sleep control circuit 826 asserts sleep control signals 828 and 829 as well as a sleep signal 827 upon receipt of a sleeper set signal 830 given by the sequencer 823. On receiving a sleep leave signal 833 from the ID recognition part 825, the sleep control circuit 826 negates the sleep control signals 828 and 829 along with the sleep signal 827. A clock signal 834 is AND'ed with the sleep control signal 828 for use by the function block 842, and AND'ed with the sleep control signal 829 for use by the function block 843.
A current control circuit 835 acts as power dissipation controlling means. The circuit 835 comprises a switch 836 and a power supply Vcc. The switch 836 is controlled by the sleep signal 837 given by the CPU 1806. The current control circuit 835 supplies current independently to the ID recognition part 825, to the sleep control circuit 826, to a power supply Vcc2 that furnishes currents to the function block 841 made of receivers 812 and 814, and to a power supply Vcc1 that feeds currents to the function blocks 842 and 843. Specifically, the current control circuit 835 controls the switch 830 in such a way that the power supply Vcc1 is activated upon receipt of the sleep signal 837 from the CPU 1806, and is deactivated given the sleep signal 833 by the ID recognition part 825.
FIGS. 11 and 12 schematically show the constructions of the receivers 812 and 814, respectively. As depicted in FIG. 11, the receiver 812 is made of receivers with hysteresis 1102, 1107, 1111, 1115, 1119, 1123, 1127, 1131 and 1135 which respectively receive signals SDB0/ through SDB7/ (1101, 1106, 1110, 1114, 1118, 1122, 1126, 1130) and SDBP/ (1134), and of three-stage synchronizers 1104, 1108, 1112, 1116, 1120, 1124, 1128, 1132 and 1136 which respectively synchronize the signals output by these receivers according to a clock signal 1103 (equivalent to the clock signals 834 in FIG. 8). The three-stage synchronizers 1104 through 1136 output internal signals SDB0 through SDBP (1105 through 1137).
The receiver 814 is basically constituted, as shown in FIG. 12, by receivers with hysteresis 1202, 1206, 1210, 1214, 1218, 1222, 1226, 1230 and 1234 which respectively receive SCSI control bus signals BSY/ (1201), SEL/ (1205), REQ/ (1209), ACK/ (1213), I/O/ (1217), C/D/ (1221), MSG/ (1225), ATN/ (1229) and RST/ (1233), and by three-stage synchronizers 1203, 1207, 1211, 1215, 1219, 1223, 1227, 1231 and 1235 which respectively synchronize the output signals from these receivers according to the clock signal 1103. (For the functions of the above input signals, reference should be made to the SCSI Protocol Specification mentioned earlier.) The three-stage synchronizers 1203 through 1235 respectively output internal signals BSY (1204), SEL (1208), REQ (1212), ACK (1216), I/O (1220), C/D (1224), MSG (1228), ATN (1232) and RST (1236).
As shown in FIG. 8, the receiver 814 of the second embodiment receives the sleep signal 827 from the sleep control circuit 826. In order to address the sleep signal 827, the receiver 814 has the receiver circuit construction of FIG. 10 which accepts the signals REQ/ (1209), ACK/ (1213), I/U/ (1217), C/D/ (1221), MSG/ (1225), ATN/ (1229) and RST/ (1233). While FIG. 10 indicates only the receiver circuit part corresponding to the signal MSG/ (1225), the same structure applies to the other signals REQ/ (1209), ACK/ (1213), I/O/ (1217), C/D (1221), ATN/ (1229) and RST/ (1233) as well.
As described, the sleep signal 827 is a signal that places the function blocks 843 and 842 in sleep mode. When the sleep signal 827 is activated, the circuit of FIG. 10 keeps the internal signals REQ (1212) through RST (1236) deactivated regardless of the values of the signals REQ/ (1209), ACK/ (1213), I/O/ (1217), C/D/ (1221), MSG/ (1225), ATN/ (1229) and RST/ (1233). The operations of an inverter circuit 1001, a two-input NOR circuit 1002 and a two-input OR circuit 1003 contained in FIG. 10 will be described later.
The receiver circuit parts corresponding to the signals BSY/ (1201) and SEL/ (1205) keep their arrangements as shown in FIG. 12 throughout. The reason for this is that these signals are needed for ID recognition of the SCSI protocol and must be functional at all times. Because the other signals are not needed for ID recognition of the SCSI protocol, the parts corresponding to these signals are constructed as shown in FIG. 10, i.e., controlled by the sleep signal 827.
Referring to FIG. 9, how the ID recognition block 825 in FIG. 8 is constructed will now be described. The ID recognition part 825 receives the internal signals BSY (1204) and SEL (1208) from the receiver 814 and SDB0 through SDB6 (1105-1133) from the receiver 812. The sleep leave signal 833 is output by the ID recognition part 825. In FIG. 9, reference numeral 901 is an OWN-ID register for retaining the ID of the SCSI system that is the second embodiment; 902 is an inverter; 903 through 912 are two-input AND circuits; and 913 is an eight-input OR circuit. How the ID recognition part 826 works will be described later in more detail.
In FIG. 13, reference numeral 1301 is a sleep leave select register; 1302 and 1303 are two-input AND gates; 1304 and 1305 are set/reset latch circuits that retain the sleep control signals 828 and 829, respectively; and 1306 is a two-input OR gate.
As depicted in FIG. 17A, the SCSI system enters a bus free phase after being reset by the initiator. The bus free phase is a state in which the SCSI bus is used by none of the SCSI systems configured. As shown in FIG. 17B, the SCSI system in the bus free phase negates the signals BSY/ (1201), SEL/ (1205), SDB0/ through SDB7/ (1104-1130) and SDBP/ (1134), i.e., holds these signals at the high level. The initiator then starts an arbitration phase in order to acquire the right to use the bus. That is, the initiator assets the signal BSY/ (1201) and outputs its own ID (i.e., initiators's device number) to SDB0/ through SDB7/ (1101-1130) and SDBP (1134). Checking the ID's on the SCSI bus in the arbitration phase, the initiator acquires the right to use the bus if its own ID is found to be the highest priority ID on the bus. With the bus right acquired, the initiator asserts the signal SEL/ (1205).
The initiator then starts a selection phase in order to select the target equipment to which to issue a command. That is, the initiator negates the signal BSY/ (1201) and outputs a partner ID (i.e., target equipment's number) to SDB0/ through SDB7/ (1101-1130) and SDBP/ (1134) in addition to the own-ID. When the target equipment finds that the signal BSY/ (1201) is negated and the signal SEL/ (1205) asserted, the target equipment compares the ID on the SCSI bus with the target's own ID.
If the ID on the SCSI bus is formed to match the target equipment's own ID, the target equipment responds to the initiator by asserting the signal BSY/ (1201). After verifying that the signal BSY/ (1201) is asserted, the initiator negates the signal SEL/ (1205) and terminates the selection phase. With the selection phase ended, the SCSI system enters an information transfer phase. In the information transfer phase, the initiator connected to the target equipment exchanges commands, data, messages and status therewith.
When all commands, data, messages and status have been exchanged, the target equipment negates the signal BSY/ (1201) and enters a bus free phase. Even if the exchanges of all commands, data, messages or status is not complete, the target equipment may negate the signal BSY/ (1201) and enter the bus free phase past a certain time limit. In that case, with the internal processing ended, the target equipment may start an arbitration phase and select the initiator in a re-selection phase to resume the interrupted exchange of the commands, data, messages and status. Where initiators add a queue tag message to each of the commands to be transferred to the target equipment, the target equipment may accept commands simultaneously from a plurality of initiators.
In a conventional arrangement, NCR's SCSI Control LSI 53C90A or 53C90B in an access wait state has all signals on the SCSI bus kept monitored by receivers and checked by a sequencer. The arrangement allows the LSI to check that the signal BSY/ is negated and the SEL/ asserted, thereby taking the ID on the SCSI bus into an FIFO for comparison with the own ID by the sequencer. This constitutes the operation of the selection phase mentioned above. Thus even in a state in which commands are awaited from an initiator, the whole SCSI bus control circuit including the sequencer and other internal circuits remains active. This necessarily promotes power dissipation.
The description of the operation of the second embodiment is continued. When the CPU 1806 of FIG. 7 has executed all commands given by the SCSI bus 601, exhausting the command queue defined by the SCSI protocol, the CPU outputs the sleep signal 837 to the power control circuit 835. In turn, the power control circuit 835 deactivates the power supply Vcc1 and enters sleep mode, cutting off power to all circuits in the function blocks 842 and 843 of the SCSI bus control circuit 701 but not to those in the function block 841 thereof, the block 841 comprising the ID recognition part 825, sleep control circuit 826, receivers 812 and 814, and two two-input AND circuits.
As shown in FIGS. 10 and 12, the receiver 814 of the second embodiment has all its input circuits except for the BSY/ (1201) and SEL/ (1205) circuits receive the sleep signal 827. When the sleep signal 827 is at the high level in sleep mode, the output of the two-input NOR circuit 1002 (FIG. 10) remains fixed at the low level. The outputs of the two-input OR circuit 1003 is held fixed at the high level. Thus the internal signal 1228 remains unchanged (i.e., fixed at the low level) even when the signal MSG/ (1225) varies on the SCSI bus. Generally, these circuits are made of CMOS's, which means that they dissipate no currents if the signals associated therewith stay unchanged. Thus in sleep mode, the receiver 814 does not dissipate currents except in the BSY/ (1201) and SEL/ (1207) input circuits thereof.
When the SCSI bus goes into an arbitration phase and on to a selection phase, the signal BSY/ (1201) is brought High and the SEL/ (1205) brought Low. Since the ID recognition part 825 is structured as shown in FIG. 9, the output of the inverter 902 and that of the two-input AND gate 903 are brought High each. If the ID retained in the own-ID register 901 is found to match the value in SDB0/ through SDB7/ (1105-1133), the sleep leave signal 833 is brought High.
If the own-ID is set to "3," and the signal SDB3/ (1114) is at the low lever, then the internal signal SDB3 (1117) is brought High and the output of the two-input AND circuit 908 is also brought High. It follows that the output of the eight-input OR circuit 913 is brought High. Thus the output of the two-input AND circuit 912 is brought High, which renders High the sleep leave signal acting as the access start signal. As a result, the current control circuit 835 activates the power supply Vcc1 to power the function blocks 843 and 842.
Meanwhile, the sleep control circuit 826, constructed as shown in FIG. 13, resets the sleep mode latches 1304 and 1305 as per the value in the sleep leave select register 1301 when the sleep leave signal 833 is brought High. This causes the sleep control signals 828 and 829 to be negated. The sleep control signal 828 places only the sequencer 823, the parity generator and checker 821 and the FIFO 819 in sleep mode. The sleep control signal 829 places into sleep mode the circuits within the SCSI bus control circuit 701 other than those controlled by the sleep control signal 828. For example, with the sleep leave select register 1301 containing a value of 10, the output of the two-input AND circuit 1302 is brought High and the output of the two-input AND circuit 1303 brought Low when the sleep leave signal 833 goes High.
In this manner, the sleep mode latch 1304 is reset while the sleep mode latch 1305 remains set. Consequently, the sleep control signal 828 is brought Low and the sleep control signal 829 brought High. Thus only the sequencer 823, the parity generator and checker 821 and the FIFO 819 leave their sleep mode. The sequencer 823 has the parity generator and checker 821 check to see if no parity error has occurred. With no ID error detected, the sequencer 823 allows the other circuits to leave their sleep mode. In case a parity error or an ID error is found, the sequencer 823, the parity generator and checker 821 and the FIFO 819 again enter sleep mode. This is the reason why the function blocks 842 and 843 of the second embodiment are controlled by the separate control signals 829 and 828.
The CPU 1806 waits for an interrupt signal from the SCSI bus control circuit 701 for a predetermined period of time. If not interrupt signal comes in during that period, the CPU 1806 again outputs the sleep signal 837 to the power control circuit 835, cutting off power to all circuits of the SCSI bus control circuit 701 except for the function block 841 thereof.
As described, the first and the second embodiments of the invention permit the peripheral equipment control device or LSI to minimize its current dissipation in command wait state without hampering its response characteristic.
Described below is the third embodiment of the invention with reference to FIGS. 14 through 16. Generally, the SCSI bus uses a 48 mA sink open collector arrangement or open drain driver arrangement. This makes it necessary, as shown in FIG. 14, to provide each signal line of the SCSI bus with terminators of 220 Ω and 330 Ω even in systems whose scope makes the effect of the reflection involved virtually negligible. The terminators always carry a current of 164 mA (=5 V/550 Ω×18).
Referring to FIG. 15, the user connects the switch 1501 and disconnects the switch 1505. This provides an SCSI bus driver configuration that complies with the SCSI protocol, accommodating up to eight SCSI systems over a maximum bus length of six meters. When all terminals are asserted, however, currents of 864 mA (=48 mA×18) are dissipated; when all terminals are negated, the current dissipation is 164 mA.
Next, assume a relatively small system such as a A4-size lap-top computer in which the effect of the reflection involved is negligible. In that case, the 48 mA sink drivers are not needed. Thus the external CPU 1806 causes the selector 1602 and 1603 to select the 24 mA sink drivers in accordance with the bit switch changed over to these drivers. The use connects the switch 1505 of FIG. 15 and disconnects the switch 1501. The settings permit the SCSI bus driver arrangement to be configured using the 24 mA sink drivers. With all terminals asserted, the current dissipation is 432 mA (=24 mA×18); with all terminals negated, the current dissipation is 82 mA. This means that the current dissipation is about half of what it is when the 48 mA sink drivers are employed.
1. A peripheral equipment control device connected to an interface bus which is connected to a plurality of processing means including a processor and a plurality of other peripheral equipment control devices, said peripheral equipment control device comprising:
access start detecting means for detecting a start of any access operation from said plurality of other peripheral equipment control devices independently of said processor;
access end detecting means for detecting an end of said access operation;
power dissipation controlling means, in data communication with the access start detecting means and the access end detecting means, for controlling power dissipation of said peripheral equipment control device in response to an output from at least one of said access start detecting means and said access end detecting means; and
means for controlling an associated peripheral device, said means being supplied power from said power dissipation controlling means.
2. A peripheral equipment control device according to claim 1, wherein said power dissipation controlling means causes said peripheral equipment control device to leave a low power dissipation mode in response to the output from said access start detecting means.
3. A peripheral equipment control device according to claim 1, wherein said power dissipation controlling means causes said peripheral equipment control device to enter a low power dissipation mode in response to the output from said access end detecting means.
4. A peripheral equipment control device according to claim 2, wherein only said access start detecting means is powered while in said low power dissipation mode, said peripheral equipment control device being powered as a whole when said low power dissipation mode is left.
5. A peripheral equipment control device according to claim 4, wherein said bus is a Small Computer System Interface bus generally known as SCSI bus, said access start detecting means comprising an ID recognition part for recognizing an ID signal transmitted over said SCSI bus.
6. A peripheral equipment control device according to claim 3, wherein said peripheral equipment control device is formed as a single semiconductor integrated circuit, said power dissipation controlling means cutting off power to a driving clock source within said semiconductor integrated circuit when in said low power dissipation mode.
7. A peripheral equipment control device according to claim 3, wherein said peripheral equipment control device is formed as a single semiconductor integrated circuit, said power dissipation controlling means cutting off power to said semiconductor integrated circuit in said low power dissipation mode.
8. A peripheral equipment control devices according to claim 1, wherein said access start detecting means regards as the start of said access operation a setting of a command by said processing means to said peripheral equipment control device, said access end detecting means regarding the end of the processing of said command as the end of said access operation.
9. A peripheral equipment control device according to claim 1, wherein the access start detecting means, access end detecting means, power dissipation controlling means and means for controlling the associated peripheral device are constructed as part of the associated peripheral device.
10. A Small Computer System Interface bus control device, generally known as an SCSI bus control device, in data communication with an SCSI bus and one of a plurality of peripheral equipment associated with a plurality of host computers connected to said SCSI bus, said SCSI bus control device comprising:
a central processing unit, generally known as CPU, connected to an internal bus, said CPU controlling said peripheral equipment in accordance with data transmitted over said SCSI bus by said host computers;
bus controlling means located between said SCSI bus and said internal bus, said bus controlling means controlling an exchange of said data and including,
a first block having at least means for generating a control signal to control power dissipation of said bus controlling means depending on whether an SCSI ID signal defined by an SCSI protocol is recognized in any of said data coming from said SCSI bus, and
a second block having at least sequencing means for executing the exchange of said data; and
power controlling means for continuously supplying power to said first block contained in said bus controlling means and selectively furnishing power to said second block depending on said control signal.
11. An SCSI bus control device according to claim 10, wherein said bus controlling means is made of a single semiconductor integrated circuit.
12. An SCSI bus control device according to claim 10, wherein said first block is connected to said SCSI bus and comprises:
receiving means connected to said SCSI bus to receive said data; and
recognizing means for recognizing said SCSI ID signal contained in said data received by said receiving means and supplying said power controlling means with a sleep leave signal acting as said control signal to furnish power to said second block.
13. An SCSI bus control device according to claim 12, wherein said first block further comprises sleep controlling means for receiving said sleep leave signal and transmitting a driving clock signal to said second block.
14. An SCSI bus control device according to claim 13, wherein said sequencing means transmits a sleep mode set signal to said sleep controlling means when the operation associated with said sleep leave signal has been completed, said sleep controlling means terminating concurrently the transmission of said driving clock signal to said second block.
15. An SCSI bus control device according to claim 14, wherein said second block is divided into a plurality of circuit blocks, said sleep controlling means having register means for managing the sleep leave information corresponding to said plurality of circuit blocks.
16. A peripheral equipment control device connected to a Small Computer System Interface bus which is connected to a plurality of processing means including a processor and a plurality of other peripheral equipment control devices, said peripheral equipment control device comprising:
an ID recognition unit for recognizing the device's own ID signal which is transmitted over said Small Computer System Interface bus upon a selection phase;
a power controller for setting the device on a sleep mode for power dissipation when the device is not accessed, and waking the device up from the sleep mode in response to an output from the ID recognition unit; and
means for controlling an associated peripheral device, said means being supplied power under control of the power controller.
17. A peripheral equipment control device according to claim 16, wherein only said ID recognition unit is provided while said sleep mode is being in effect, the device being powered as a whole when said sleep mode is left.
18. A peripheral equipment control device according to claim 16, wherein the device is formed as a single semiconductor integrated circuit, said power controller cutting off power to a driving clock source within said semiconductor integrated circuit in said sleep.
19. A peripheral equipment control device according to claim 16, wherein the device is formed as a single semiconductor integrated circuit, said power controller cutting off power to the semiconductor integrated circuit in said sleep mode.
20. A peripheral equipment device which is operated by external processing means via an interface bus and processes data, the device comprising:
processing circuits for processing data in response to data processing commands by said external processing means via said interface bus; and
a power dissipation control circuit, comprising,
access start detecting means for detecting issue of data processing commands by said external processing means via an interface bus,
access end detecting means for detecting an end of data processing by said processing circuits, and
activation controlling means for controlling activation of said processing circuits, said activation controlling means activating said processing circuits in response to an output from said access start detecting means and inactivating said processing circuits in response to an output from said access end detecting means.
21. A peripheral equipment device according to claim 20, wherein said means for controlling activation causes said peripheral equipment device to leave low power dissipation mode in response to the output from said access start detecting means.
22. A peripheral equipment control device according to claim 21, wherein only said access start detecting means is powered while in said low power dissipation mode, said peripheral equipment device being powered as a whole when said low power dissipation mode is exited.
23. A peripheral equipment device according to claim 20, wherein said means for controlling activation causes said peripheral equipment device to enter low power dissipation mode in response to the output from said access end detecting means.
24. A bus control device in data communication with a bus and one of a plurality of peripheral equipment associated with a plurality of host computers connected to said bus, said bus control device comprising:
a CPU connected to an internal bus, said CPU controlling said peripheral equipment in accordance with data transmitted over said bus by said host computers;
bus controlling means located between said bus and said internal bus, said bus controlling means controlling an exchange of said data and including
a first block having at least means for generating a control signal to control power dissipation of said bus controlling means depending on whether an ID signal defined by an upper protocol is recognized in any of said data coming from said bus, and
25. A bus control device according to claim 24, wherein said bus controlling means is made of a single semiconductor integrated circuit.
26. A bus control device according to claim 24, wherein said first block is connected to said bus and comprises:
receiving means connected to said bus to receive said data; and
recognizing means for recognizing said ID signal contained in said data received by said receiving means and supplying said power controlling means with a sleep leave signal acting as said control signal to furnish power to said second block.
27. A bus control device according to claim 26, wherein said first block further comprises sleep controlling means for receiving said sleep leave signal and transmitting a driving clock signal to said second block.
28. A bus control device according to claim 27, wherein said sequencing means transmits a sleep mode set signal to said sleep controlling means when the operation associated with said sleep leave signal has been completed, said sleep controlling means terminating concurrently the transmission of said driving clock signal to said second block.
29. A bus control device according to claim 28, wherein said second block is divided into a plurality of circuit blocks, said sleep controlling means having register means for managing the sleep leave information corresponding to said plurality of circuit blocks.
30. A peripheral equipment control device connected to a bus which is connected to a plurality of processing means including a processor and a plurality of other peripheral equipment control devices, said peripheral equipment control device comprising:
an ID recognition unit for recognizing the device's own ID signal which is transmitted over said bus upon a selection phase;
31. A peripheral equipment control device according to claim 30, wherein only said ID recognition unit is provided while said sleep mode is being in effect, the device powered as a whole when said sleep mode is left.
32. A peripheral equipment control device according to claim 30, wherein the device is formed as a single semiconductor integrated circuit, said power controller cutting off power to a driving clock source within said semiconductor integrated circuit in said sleep mode.
33. A peripheral equipment control device according to claim 30, wherein the device is formed as a single semiconductor integrated circuit, said power controller cutting off power to the semiconductor integrated circuit in said sleep mode.
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JP31845090 1990-11-22
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US08/757,318 Division US5892958A (en) 1990-11-22 1996-11-27 Peripheral equipment control device
US5361364A true US5361364A (en) 1994-11-01
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US07/795,697 Expired - Lifetime US5361364A (en) 1990-11-22 1991-11-21 Peripheral equipment control device
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