Source: http://www.google.com/patents/US7479677?dq=7,682,496
Timestamp: 2015-03-05 16:47:17
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Matched Legal Cases: ['Application No. 02826596', 'Application No. 02826596', 'Application No. 02826596', 'Application No. 02', 'Application No. 07002287', 'Application No. 07002289', 'Application No. 07002288', 'Application No. 07002289', 'Application No. 204', 'Application No. 91132182', 'Application No. 02826596', 'Application No. 02826596']

Patent US7479677 - Multi-state non-volatile integrated circuit memory systems that employ ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsNon-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one...http://www.google.com/patents/US7479677?utm_source=gb-gplus-sharePatent US7479677 - Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elementsAdvanced Patent SearchPublication numberUS7479677 B2Publication typeGrantApplication numberUS 12/020,266Publication dateJan 20, 2009Filing dateJan 25, 2008Priority dateOct 31, 2001Fee statusPaidAlso published asCN1610976A, CN100539195C, DE60219666D1, DE60219666T2, EP1446840A1, EP1446840A4, EP1446840B1, EP1777750A2, EP1777750A3, EP1777751A2, EP1777751A3, EP1777751B1, EP1777752A2, EP1777752A3, EP1777752B1, US6925007, US7341918, US7342279, US7579247, US7834392, US20030109093, US20050157551, US20050180210, US20080116509, US20080119026, US20090286370, WO2003038907A1Publication number020266, 12020266, US 7479677 B2, US 7479677B2, US-B2-7479677, US7479677 B2, US7479677B2InventorsEliyahou Harari, George Samachisa, Jack H. Yuan, Daniel C. GutermanOriginal AssigneeSandisk CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (98), Non-Patent Citations (46), Referenced by (9), Classifications (36), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMulti-state non-volatile integrated circuit memory systems that employ dielectric storage elements
In addition, different designs of memory cells have been implemented in order to further increase data storage density. An example is a dual floating gate memory cell connected in a NOR configuration, which can also be operated with the storage of multiple states on each floating gate. In this type of cell, two floating gates are included over its channel between source and drain diffusions with a select transistor in between them. A steering gate is included along each column of floating gates and a word line is provided thereover along each row of floating gates. When accessing a given floating gate for reading or programming, the steering gate over the other floating gate of the cell containing the floating gate of interest is raised sufficiently high to turn on the channel under the other floating gate no matter what charge level exists on it. This effectively eliminates the other floating gate as a factor in reading or programming the floating gate of interest in the same memory cell. For example, the amount of current flowing through the cell, which can be used to read its state, is then a function of the amount of charge on the floating gate of interest but not of the other floating gate in the same cell. An example of this cell array architecture, its manufacture and operating techniques are described in U.S. Pat. No. 5,712,180 (FIG. 9+), which patent is incorporated herein by this reference (hereinafter referred to as the �Dual Storage Element Cell�).
Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. Such a cell is described in an article by Chan et al., �A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,� IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (�ONO�) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. See also Nozaki et al., �A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,� IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar cell in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor. The foregoing two articles are incorporated herein by this reference. The programming techniques mentioned above, by reference to section 1.2 of the book edited by Brown and Brewer, are also described in that section to be applicable to dielectric charge-trapping devices.
In a particular example, the Dual Storage Element Cell described above in the Background has charge-storing dielectric substituted for each of the two floating gates of the memory cells. This dielectric is sandwiched between conductive steering gates and the substrate to form two functionally separate charge storage elements over channels of the memory cells between their sources and drains. One region of charge is preferably stored in each of these two storage elements, which lie along the length of the cell channels on opposite sides of the select transistors, although two such regions may alternatively be used to obtain a further increase in charge storage density. The level of charge in a region affects the threshold level of the portion of the length of the cell channel beneath that region. Two or more such charge levels, and thus two or more different threshold levels, are defined for programming into each of the two charge storage regions of each memory cell. Programming and reading of a selected one of the two charge storage regions of an addressed cell is accomplished in the same manner as in the dual floating gate systems, by turning on the select transistor and driving the other channel portion strongly conductive. This renders the selected charge storage region of the addressed cell responsive to voltages placed on its source, drain and gates. Specific examples of Dual Storage Element Cell arrays in which the charge storage dielectric may be substituted for floating gates are given in U.S. Pat. Nos. 6,091,633, 6,103,573 and 6,151,248, and in application Ser. No. 09/667,344, filed Sep. 22, 2000, by Yuan et al., entitled �Non-volatile Memory Cell Array having Discontinuous Source and Drain Diffusions Contacted by Continuous Bit Line Conductors and Methods of Forming,� now U.S. Pat. No. 6,512,263; Ser. No. 09/925,134, filed Aug. 8, 2001, by Harari et al., entitled �Non-Volatile Memory Cells Utilizing Substrate Trenches,� now U.S. Pat. No. 6,936,887; and Ser. No. 09/925,102, filed Aug. 8, 2001, by Yuan et al., entitled �Scalable Self-Aligned Dual Floating Gate Memory Cell Array and Methods of Forming the Array,� now U.S. Pat. No. 6,762,092, which patents and patent applications are incorporated herein in their entirety by this reference.
The second structure, shown in FIG. 6B, uses a tailored layer 141 of silicon rich silicon dioxide to trap and store electrons. Such material is described in the following two articles, which articles are incorporated herein in their entirety by this reference: DiMaria et al., �Electrically-alterable read-only-memory using Si-rich SI02 injectors and a floating polycrystalline silicon storage layer,� J. Appl. Phys. 52(7), July 1981, pp. 4825-4842; Hori et al., �A MOSFET with Si-implanted Gate-Si02 Insulator for Nonvolatile Memory Applications,� IEDM 92, April 1992, pp. 469-472. As an example, the thickness of the layer 141 can be about 500 Angstroms.
A large number of individually addressable memory cells 11 are arranged in a regular array of rows and columns, although other physical arrangements of cells are certainly possible. Bit lines, designated herein to extend along columns of the array 11 of cells, are electrically connected with a bit line decoder and driver circuit 13 through lines 15. Word lines, which are designated in this description to extend along rows of the array 11 of cells, are electrically connected through lines 17 to a word line decoder and driver circuit 19. Steering gates, which extend along columns of memory cells in the array 11, are electrically connected to a steering gate decoder and driver circuit 21 through lines 23. The steering gates and/or bit lines may be connected to their respective decoders by techniques described in a co-pending patent application by Harari et al. entitled �Steering Gate and Bit Line Segmentation in Non-Volatile Memories,� Ser. No. 09/871,333, filed May 31, 2001, now U.S. Pat. No. 6,532,172, which application is incorporated herein by this reference. Each of the decoders 13, 19 and 21 receives memory cell addresses over a bus 25 from a memory controller 27. The decoder and driving circuits are also connected to the controller 27 over respective control and status signal lines 29, 31 and 33. Voltages applied to the steering gates and bit lines are coordinated through a bus 22 that interconnects the steering gates and bit line decoder and driver circuits 13 and 21.
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SC-7, No. 5, Oct. 1972, pp. 369-375.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7834392Jul 27, 2009Nov 16, 2010Sandisk CorporationMulti-state non-volatile integrated circuit memory systems that employ dielectric storage elementsUS8134203 *Nov 13, 2009Mar 13, 2012Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS8547743 *Jun 28, 2011Oct 1, 2013Seagate Technology LlcRead error recovery for solid-state memory based on cumulative background chargesUS8575684 *Feb 2, 2012Nov 5, 2013Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS8614477 *Feb 2, 2012Dec 24, 2013Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS20100123184 *Nov 13, 2009May 20, 2010Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS20120139031 *Feb 2, 2012Jun 7, 2012Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS20120146128 *Feb 2, 2012Jun 14, 2012Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS20130003459 *Jun 28, 2011Jan 3, 2013Seagate Technology LlcRead Error Recovery for Solid-State Memory Based on Cumulative Background Charges* Cited by examinerClassifications U.S. Classification257/324, 257/E29.309, 257/E27.103, 257/E21.679, 257/326International ClassificationG11C11/56, H01L27/115, H01L29/788, G11C16/04, H01L21/8247, H01L21/8246, H01L29/792Cooperative ClassificationH01L27/11521, G11C2216/06, H01L27/11524, H01L27/115, G11C16/0491, B82Y10/00, H01L29/7923, H01L29/4234, G11C16/0475, G11C11/5671, G11C16/0483, G11C16/0466, Y10S438/947, H01L27/11568European ClassificationG11C16/04M, G11C16/04N, G11C11/56M, H01L29/423D2B3, H01L27/115F4, B82Y10/00, H01L27/115F4N, H01L29/792B, H01L27/115, H01L27/115G4Legal EventsDateCodeEventDescriptionJun 20, 2012FPAYFee paymentYear of fee payment: 4May 20, 2011ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:026317/0702Owner name: SANDISK TECHNOLOGIES INC., TEXASEffective date: 20110404RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services