Source: http://www.google.com/patents/US8156400?dq=3723653
Timestamp: 2016-07-01 10:28:51
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Patent US8156400 - Embedded parity coding for data storage - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA decoder memory system comprises a first memory comprising at least a portion of a parity check matrix H. A second memory receives the portion from the first memory and that is associated with a previous decoding iteration. A third memory communicates with the first memory, receives the parity check...http://www.google.com/patents/US8156400?utm_source=gb-gplus-sharePatent US8156400 - Embedded parity coding for data storageAdvanced Patent SearchPublication numberUS8156400 B1Publication typeGrantApplication numberUS 11/827,339Publication dateApr 10, 2012Filing dateJul 11, 2007Priority dateJun 2, 2006Fee statusPaidAlso published asUS8028216, US8255764, US8255765Publication number11827339, 827339, US 8156400 B1, US 8156400B1, US-B1-8156400, US8156400 B1, US8156400B1InventorsEngling Yeo, Eugene Pan, Henri Sutioso, Jun Xu, Shaohua Yang, Panu Chaichanavong, Gregory Burd, Zining WuOriginal AssigneeMarvell International Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (18), Non-Patent Citations (23), Referenced by (28), Classifications (18), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetEmbedded parity coding for data storage
US 8156400 B1Abstract
A decoder memory system comprises a first memory comprising at least a portion of a parity check matrix H. A second memory receives the portion from the first memory and that is associated with a previous decoding iteration. A third memory communicates with the first memory, receives the parity check matrix H and is associated with a current decoding iteration. A fourth memory comprises likelihood ratios. A control module generates a LDPC decoded signal based on the parity check matrix H, the previous decoded iteration and the likelihood ratios.
1. A decoder memory system comprising:
a first memory configured to store a parity check matrix H;
a second memory associated with a first decoding iteration of a tensor product code, the second memory configured to receive a first portion of the parity check matrix H from the first memory;
a third memory associated with a second decoding iteration of the tensor product code, the third memory configured to receive a second portion of the parity check matrix H from the first memory, wherein the second decoding iteration is performed subsequent to and based on the first decoding iteration, and wherein the second portion is same as the first portion;
a fourth memory configured to store likelihood ratios; and
a control module configured to generate a low-density parity check decoded signal based on (i) the parity check matrix H, (ii) the first decoded iteration, and (iii) the likelihood ratios.
2. The decoder memory system of claim 1, wherein:
the second memory is configured to store a plurality of segregated portions; and
each of the plurality of segregated portions is associated with a group of rows in the parity check matrix H.
3. The decoder memory system of claim 1, wherein:
the third memory is configured to store a plurality of segregated portions; and
4. The decoder memory system of claim 1, wherein the fourth memory is configured to store a plurality of segregated portions.
5. The decoder memory system of claim 1, wherein:
the second memory comprises a plurality of rows; and
each of the plurality of rows comprising a word.
6. The decoder memory system of claim 5, wherein the word comprises a plurality of sequential multi-bit entries.
7. The decoder memory system of claim 6, wherein the plurality of sequential multi-bit entries comprises a first minimum bit log-likelihood ratio.
8. The decoder memory system of claim 7, wherein the plurality of sequential multi-bit entries comprises a second minimum bit log-likelihood ratio.
9. The decoder memory system of claim 6, wherein the plurality of sequential multi-bit entries comprises a parity check sign bit.
10. The decoder memory system of claim 6, wherein the plurality of sequential multi-bit entries comprises an index.
11. The decoder memory system of claim 6, wherein the plurality of sequential multi-bit entries comprises a parity checksum of hard decision bits.
12. The decoder memory system of claim 11, wherein the hard decision bits indicate a valid codeword is detected.
13. The decoder memory system of claim 11, wherein the hard decision bits indicate decoding complete for an iteration.
14. The decoder memory system of claim 1, wherein:
the parity check matrix H is stored in the first memory as a series of offset values; and
the offset values indicate at least one row index.
15. The decoder memory system of claim 14, wherein the at least one row index comprises a non-zero entry along a leftmost column of a circulant of the parity check matrix H.
16. The decoder memory system of claim 1, wherein submatrices along a diagonal of the parity check matrix H share a common offset value.
17. The decoder memory system of claim 1, wherein the first memory is configured to store only one row and one column of the parity check matrix H.
18. The decoder memory system of claim 1, wherein at least one of the second memory or the third memory are configured to store a plurality of words in a single row.
19. The decoder memory system of claim 18, wherein a last word of the plurality of words comprises empty memory cells when the last word is indivisible by 4.
20. A method of operating a decoder memory system, the method comprising:
receiving a first portion of a parity check matrix H from a first memory via a second memory, wherein the second memory is associated with a first decoding iteration of a tensor product code;
receiving a second portion from the first memory via a third memory, wherein the third memory is associated with a second decoding iteration of the tensor product code, wherein the second portion is same as the first portion, and wherein the second decoding iteration is performed subsequent to and based on the first decoding iteration; and
generating a low-density parity check decoded signal via a control module and based on (i) the parity check matrix H, (ii) the first decoding iteration, and (iii) likelihood ratios.
the second memory comprises a plurality of rows;
each of the plurality of rows comprising a word;
the word comprises a plurality of sequential multi-bit entries;
the plurality of sequential multi-bit entries comprises a parity checksum of hard decision bits; and
the method further comprises indicating a valid codeword is detected via the hard decision bits.
the method further comprises indicating decoding complete for an iteration via the hard decision bits.
23. The method of claim 20, further comprising storing the parity check matrix H as a series of offset values, wherein the offset values indicate at least one row index.
24. The method of claim 23, wherein the at least one row index comprises a non-zero entry along a leftmost column of a circulant of the parity check matrix H.
25. The method of claim 20, wherein submatrices along a diagonal of the parity check matrix H share a common offset value.
26. The method of claim 20, further comprising generating a decoded signal based on the decoder memory system.
27. A decoder memory system comprising:
first storing means for storing a parity check matrix H;
second storing means for receiving a first portion of the parity check matrix H from the first storing means, wherein the second storing means is associated with a first decoding iteration of a tensor product code;
third storing means for receiving a second portion of the parity check matrix H from the first storing means, wherein the third storing means is associated with a second decoding iteration of the tensor product code, wherein the second decoding iteration is performed subsequent to and based on the first decoding iteration, and wherein the second portion is same as the first portion;
fourth storing means for storing likelihood ratios; and
a control means for generating a low-density parity check decoded signal based on (i) the parity check matrix H, (ii) the first decoding iteration, and (iii) the likelihood ratios.
28. The decoder memory system of claim 27, wherein:
the second storing means stores a plurality of segregated portions; and
29. The decoder memory system of claim 27, wherein:
the third storing means stores a plurality of segregated portions; and
30. The decoder memory system of claim 27, wherein the fourth storing means stores a plurality of segregated portions.
31. The decoder memory system of claim 27, wherein:
the second storing means comprises a plurality of rows; and
32. The decoder memory system of claim 31, wherein the word comprises a plurality of sequential multi-bit entries.
33. The decoder memory system of claim 32, wherein the plurality of sequential multi-bit entries comprises a first minimum bit log-likelihood ratio.
34. The decoder memory system of claim 33, wherein the plurality of sequential multi-bit entries comprises a second minimum bit log-likelihood ratio.
35. The decoder memory system of claim 32, wherein the plurality of sequential multi-bit entries comprises a parity check sign bit.
36. The decoder memory system of claim 32, wherein the plurality of sequential multi-bit entries comprises an index.
37. The decoder memory system of claim 32, wherein the plurality of sequential multi-bit entries comprises a parity checksum of hard decision bits.
38. The decoder memory system of claim 37, wherein the hard decision bits indicate a valid codeword is detected.
39. The decoder memory system of claim 37, wherein the hard decision bits indicate decoding complete for an iteration.
40. The decoder memory system of claim 27, wherein:
the parity check matrix H is stored in the first storing means as a series of offset values; and
41. The decoder memory system of claim 40, wherein the at least one row index comprises a non-zero entry along a leftmost column of a circulant of the parity check matrix H.
42. The decoder memory system of claim 27, wherein submatrices along a diagonal of the parity check matrix H share a common offset value.
43. The decoder memory system of claim 27, wherein the first storing means comprises only one row and one column of the parity check matrix H.
44. The decoder memory system of claim 27, wherein the second storing means and the third storing means stores a plurality of words in a single row.
45. The decoder memory system of claim 44, wherein a last word of the plurality of words comprises empty memory cells when the word is indivisible by 4. Description
This application is a continuation of U.S. patent application Ser. No. 11/809,670, filed on Jun. 1, 2007, which application claims the benefit of U.S. Provisional Application No. 60/810,495, filed Jun. 2, 2006. This application is related to U.S. patent application Ser. No. 11/518,020, filed on Sep. 8, 2006. The disclosures of the above applications are incorporated herein by reference in their entirety.
p k = ⊕ 9 i = 0 s k ( i ) ( 1 ) A collection of user bits form a tensor product codeword if and only if SPC parity bits form an LDPC codeword, i.e. Hp={right arrow over (0)}.
With the flexibility of LDPCs, codes can be constructed to match a particular block size or code rate. After the block size and code rate are established, an M-by-N parity check matrix H is constructed and contains a sparse number of ones. The number of rows M is greater than or equal to the number of parity bits N-K, where K is the number of information (user) bits. A binary string c, of length N is said to be a codeword in C if and only if Hc={right arrow over (0)}. An example parity check matrix H where N=7 and K=5 is provided as equation 2.
G = [ I G p 0 G ^ ′ ] , wherein matrix Gp is a non-low density matrix and matrix Ĝ′ is a non-cyclical matrix. In other features, the matrix Gp comprises circulant matrices.
In other features, the encoder system includes an LDPC parity bit generator that generates a parity vector based on an interleave output of the interleave module and the matrix Gp. In other features, the LDPC parity bit generator generates a binary vector based on the interleave output and the matrix Gp and that generates the parity vector based on the binary vector.
G = [ I G p 0 G ^ ′ ] . The matrix Gp is a non-low density matrix and the matrix Ĝ′ is a non-cyclical matrix. In other features, the matrix Gp includes circulant matrices. In other features, the method includes storing a selected row of each circulant of the matrix Gp. LDPC parity bits are generated based on the selected row. In other features, the method includes deriving remaining rows of the matrix Gp based on the selected row.
G = [ I G p 0 G ^ ′ ] . The matrix Gp is a non-low density matrix and the matrix Ĝ is a non-cyclical matrix. In other features, the matrix Gp includes circulant matrices. In other features, the encoder system includes storing means for storing a selected row of each circulant of the matrix Gp. Encoding means for generating LDPC parity bits based on the selected row is included. In other features, the encoder system wherein the encoding means derives remaining rows of the matrix Gp based on the selected row.
In other features, the matrix Gp includes circulant matrices. In other features, the encoder system further includes storing means for storing a selected row of each circulant of matrix Gp. The TPC encoder means generates LDPC parity bits based on the selected row. In other features, the encoding means derives remaining rows of matrix Gp based on the selected row.
In other features, a method of operating a decoder memory system is provided and includes receiving at least a portion of a parity check matrix H from a first memory via a second memory that is associated with a previous decoding iteration. The parity check matrix H is received via a third memory that is associated with a current decoding iteration. A control module generates a LDPC decoded signal based on the parity check matrix H, the previous decoded iteration, and likelihood ratios
The embodiments disclosed below describe efficient very large scale integrator (VLSI) implementation architectures for tensor-product code (TPC) applications. For a further example description of a tensor-product code and a further example application for the use of a tensor-product code within a system see U.S. patent application Ser. No. 11/449,066 entitled, “Tensor Product Codes Containing an Iterative Code”, filed Jun. 7th, 2006, which is incorporated herein by reference in its entirety. Referring now to FIGS. 3-5, a functional block diagram illustrating a tensor-product coded channel system 30 that performs LDPC coding, an encoder associated sector diagram and a TPC encoder process diagram are shown. The system 30 includes an encoder write/transmit path 32, a channel 34 and a decoder read/receive path 36, which may be referred to as tensor-product encoder and decoder paths. Data is encoded via the encoder path 32, stored on or transmitted through the channel 34, and read or received and decoded via the decoder path 36.
The fourth stage 44 includes a TPC encoder 61 that has a parity forming module 63, which may be based on a LDPC inner code, and an iterative LDPC encoder 62. The TPC encoder 61 replaces the inserted zeros with LDPC parity bits py, such as p1 and p2 shown in FIG. 4. The TPC encoder 61 generates a fourth stage output v(t). In FIG. 5, the third stage output 60 is shown followed by the fourth stage output v(t). The bits associated with each symbol in data, of the third stage output 60 are XOR with each other to generate q-bits. The bits associated with each symbol in data2 of the third stage output 60 are XOR with each other to generate a first set of LDPC parity bits, designated as pw. The LDPC parity bits pw are received by a LDPC encoder 62, which provides the LDPC parity bits px, respectively, to XOR gates 70. The bits (q) are XOR with the respective LDPC parity bits px, as shown to generate a second set of parity bits or the parity bits py. The parity bits py replace the zeros that are in the data, series. The LDPC encoder 62 provides the fourth stage output v(t), which is referred to as the LDPC encoded bits, to the channel 34.
When H is quasi-cyclic, then an efficient hardware based encoder may be designed. Again when Hp is of full rank then Hp −1 exists and is also quasi-cyclic. This simplifies storage requirements for an encoder. Similarly, when an encoder is implemented via the generator matrix G, the parity bit generator matrix Gp is also quasi-cyclic. The parity bit generator matrix Gp is a k-by-(n-k) matrix.
By letting length of c be equal to a circulant size, the parity bit generator matrix Gp has k/c rows of circulants and (n-k)/c columns of circulants. Each row of circulants is fully represented by the first row of bits in each circulant. Example circulants and first rows are shown in FIG. 8 and designated 183, 185, respectively. An example implementation of uGp is provided below with respect to FIG. 9, where initially the parity bits are 0s.
G = [ G ~ G ^ ] = [ I G p 0 G ^ ′ ] ( 6 ) The matrix G can also be expressed relative to user bits or a user vector ũ and associated LDPC parity bits or a parity vector {tilde over (p)}, as provided in expression 7. It is further noted that the matrix G satisfies expression 8.
[{tilde over (u)}{tilde over (p)}]={tilde over (u)} G (7)
The first row of each circulant of the matrix Gp is stored in the encoder memory 194, such as a read only memory (ROM) 200 and/or a circular buffer 202 having shift registers 204, as a single binary word. An example circular Gp buffer architecture 206 is shown in FIG. 9. The memory 194 is read when the LDPC encoding process proceeds into a new or subsequent circulant of the matrix Gp. The circular Gp buffer architecture 206 shows matrix Gp divided along the circulant boundaries. Rows within each cell of the circular Gp buffer architecture 206 are cyclically shifted. Hence, the architecture loads the first row of each circulant (for the embodiment described three circulants total each time) into the shift registers 204. The shift registers 204 are used to shift and obtain subsequent rows. After the first C rows, a new row corresponding to the first row of the next trio of circulants is loaded into the 3 shift register chains, and the process is repeated.
In use, the TPC encoder 190 performs a bitwise logical AND, designated 210, with each entering user bit uk and a vector of binary bits 212 from the corresponding row in the matrix Gp. The bits in one of the four registers SR1-SR4 are multiplexed, via a multiplexer 213 to provide the vector of binary bits 212. The vector result 214 out of the logical AND 210 is bitwise XOR, with an accumulating parity bit vector 216. The XOR is denoted as 217. A final parity vector result 218 is obtained after the last user bit is used in replacing the zeros inserted into the data1/data2 series generated in the first stage I.
The matrix Ĝ′ has Ĝr′ rows and Ĝc′ columns, where Ĝr′ is equal to [M-(N-K)] and Ĝc′ is equal to 3C or the number of rows of the parity check matrix H multiplied by the circulant size C. Thus, the matrix Ĝ′ is a [M-(N-K)]�3C matrix. Of course, the matrix Ĝ′ may have any number of columns. M is the number of circulant rows of the parity check matrix H. N is the number of columns of the parity check matrix H. K is the number of information bits within a row of the parity check matrix H.
The largest sub-code {tilde over (C)} of the LDPC code C that has a generator matrix upper portion {tilde over (G)} that is quasi-cyclic is determined. Once the generator matrix upper portion {tilde over (G)} is determined, then the generator matrix G may be written as provided in equation (6), wherein the generator matrix lower portion G contains bases of
HĜ T=0 (10)
{tilde over (g)}=[{tilde over (g)}u,{tilde over (g)}p] (12)
H p {tilde over (g)} p T =h u {tilde over (g)}p T={tilde over (H)}p −1 h u (13)
When m=n−k+1 then l*m bits in the generator matrix lower portion Ĝ are stored. I is the number of non-systematic information bits. For example, for a parity check matrix H that is 336-by-1008, when n−k=334, then 2*336 bits are stored.
Once LLRs for LDPC codewords are computed, the five decoder stages I′-V′ are performed and correspond to the five encoder stages I-V. The resultant output signals of stages I′-V′ are generated in reverse order than that of the stages I-V. The fifth stage V′ of the decoder path 156 includes the TPC decoder 226. The fifth stage V′ decodes the TPC and provides the output series {circumflex over (v)}/(t)′. The fourth stage IV′ includes a mark 0s module 230, which replaces the LDPC encoder parity bits of the LDPC decoder output series {circumflex over (v)}(t)′ with 0s prior to RS ECC decoder 234. The fourth stage IV′ provides a reset 0s output signal or fourth decoder stage output 182′ that is similar to or the same as the fourth stage encoder output 182.
In one embodiment, the preprocessor 274 may include parallel processors to determine the maximum likelihood (ML) decoding odd-parity error events or the closest codeword c to receive a vector v for each of the possible framing phases/boundaries of a received symbol. When a received symbol has ten (10) bits it has ten possible framing phases/boundaries. A buffer size associated with the ML decoding may be determined by the length of a data1 series. Once the framing signal is available based on the second sync mark, the information corresponding to one of ten possible phases is selected and used by the TPC decoder 220. This minimizes or eliminates performance loss due to a missed first sync mark.
Referring to FIG. 17, a sample of a memory entry configuration for an iteration of LDPC decoder processing is shown. Each word row in MEMMIN holds four MEMMIN entries 366. When a 64-bit wide memory is used, each row may have four 16-bit MEMMIN entries 366. Each MEMMIN entry 366 has a first minimum value Min1, a second minimum value Min2, a parity bit sgn, an index value indx and a 2nd parity bit. For the same example, the entries include five bits for each of the minimum values Min1, Min2, one bit for each of the 1st and 2nd parity bits sgn, HD, and four bits for the index value indx. This use of the MEMIN memory takes advantage of the sequential nature of memory access and allows the LDPC decoder 226 to be clocked at � the effective throughput rate. The � rate is due to the simultaneous processing of four data points associated with each of the four MEMMIN entries.
The minimum values Min1, Min2 refer to minimum LLR values associated with bit-to-check messaging. The 1st parity bit sgn refers to the result of the accumulated XOR of sign of the bit messages that are passed to a check node. The 2nd parity but HD refers to the accumulated XOR of the hard decisions associated with each adjacent bit node. The hard decision of each bit as is given by the sign of the sum of the messages passed to the bit node and the input LLR. A 2nd bit HD with zero (0) value indicates that a parity check constraint has been satisfied. For a further description of a bipartite graph see description with respect to bit-to-check messaging below and provided references.
Referring to FIG. 22, a timing diagram illustrating a read before write (RBW) implementation based on the parity check matrix H or Horig is shown. The embodiment of FIG. 22 is based on the processing pipeline of three cycles. The RBW problem occurs when one is attempting to read from a memory location in a MEMMIN memory prior to data entry being written in that location. In the example embodiment, where a parity check matrix Horig is a 3C�8C matrix. The RBW problem is possible when −3≦X≦0 where the circulant difference value X is the difference in shift values between adjacent circulants of a single row of the parity check matrix Horig. The circulant numbers in the parity check matrix H indicate the shift in that associated circulant. For example, the top left corner circulant of the parity check matrix Horig or the circulant associated with the 1st row and the 1st column, has a 3. The 3 indicates that there is a 1 in the third column of the 1st row of that circulant.
Referring to FIGS. 24 and 25, a decoding iteration diagram illustrating early termination and a parity check matrix diagram illustrating a last circulant block column is shown. A series of decoder iterations 440 and a sample parity check matrix H′″ are shown. The parity check matrix H′″ has a last column block 442. At the end of each decoding iteration the HD bits are read, as shown by timing blocks 444. The LDPC decoder 226 determines whether to stop iterative decoding based on the HD bits. The code design ensures that each row in the parity check matrix H′″ has one non-zero entry in each circulant. In one embodiment, each row in the parity check matrix H′″ has only one non-zero entry. As processing enters the last and final circulant block 442, the HD bit for the check nodes adjacent to a processed bit node becomes valid. There is no overhead in the memory access associated with early termination.
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