Source: http://www.google.com/patents/US6747888?ie=ISO-8859-1&dq=5958006
Timestamp: 2014-07-28 17:09:54
Document Index: 577831413

Matched Legal Cases: ['application No. 09', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 09', 'application No. 09']

Patent US6747888 - High speed data bus - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsThe invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller...http://www.google.com/patents/US6747888?utm_source=gb-gplus-sharePatent US6747888 - High speed data busAdvanced Patent SearchPublication numberUS6747888 B2Publication typeGrantApplication numberUS 10/017,257Publication dateJun 8, 2004Filing dateDec 6, 2001Priority dateJan 29, 1998Fee statusPaidAlso published asUS6349051, US6587363, US6781859, US6888734, US6903954, US7038927, US7184292, US7187574, US7274582, US7450410, US20020041522, US20020041523, US20020048183, US20020048194, US20020048195, US20030198072, US20050018464, US20050228935, US20050268066, US20060193193, US20070127282Publication number017257, 10017257, US 6747888 B2, US 6747888B2, US-B2-6747888, US6747888 B2, US6747888B2InventorsDean A. KleinOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (25), Referenced by (5), Classifications (26), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetHigh speed data busUS 6747888 B2Abstract The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.
a printed circuit board; a first plurality of electrical contacts arranged on said printed circuit board to connect to a data bus; a second plurality of electrical contacts arranged on said printed circuit board to connect to memory control signals for performing memory access cycles, said memory control signals including a row address strobe signal and a column address strobe signal; at least one memory integrated circuit attached to said printed circuit board and receiving one or more memory control signals from said second plurality of electrical contacts; a state decoder circuit separate from said memory integrated circuit having an input coupled to at least some of said memory control signals and an output, wherein said state decoder circuit is configured to have an output signal having a first state during a memory access and a second state in the absence of a memory access; and at least one switch having a plurality of inputs connected to corresponding ones of said first plurality of electrical contacts, and a plurality of outputs connected to said at least one memory integrated circuit so as to couple said data bus from said first plurality of electrical contacts to said memory integrated circuit, said at least one switch having an additional input coupled to said state decoder circuit output, and responsive to said state decoder circuit output to decouple said memory circuit from said data bus when no memory access cycle is being performed. 2. The memory module of claim 1, wherein the memory integrated circuit includes synchronous-DRAM memory.
a first plurality of electrical contacts arranged on said printed circuit board to connect to a data bus; a second plurality of electrical contacts arranged on said printed circuit board to connect to memory control signals for performing memory access cycles, said memory control signals including a row address strobe signal and a column address strobe signal; at least one memory integrated circuit attached to said printed circuit board and receiving one or more memory control signals from said second plurality of electrical contacts; a state decoder circuit separate from said memory integrated circuit having an input coupled to at least some of said memory control signals and an output, wherein said state decoder circuit is configured to have an output signal having a first state during a memory access and a second state in the absence of a memory access; and at least one switch having a plurality of inputs connected to corresponding ones of said first plurality of electrical contacts, and a plurality of outputs connected to said at least one memory integrated circuit so as to couple said data bus from said first plurality of electrical contacts to said memory integrated circuit, said at least one switch having an additional input coupled to said state decoder circuit output, and responsive to said state decoder circuit output to decouple said memory circuit from said data bus when no memory access cycle is being performed. 5. The printed circuit board of claim 4, wherein the memory integrated circuit includes synchronous-DRAM memory.
a state decoder for receiving a chip select signal targeted for a memory circuit and having an input coupled to memory control signals and an output, wherein said state decoder is configured to have an output signal having a first state during a memory access and a second state in the absence of a memory access, and wherein the state decoder is configured to activate a switch to decouple a memory circuit from a data bus when no memory access cycle is being performed. 8. The state decoder circuit of claim 7, wherein the state decoder is integrated with a printed circuited circuit board.
a plurality of inputs connected to corresponding ones of first plurality of electrical contacts, and a plurality of outputs connected to at least one memory integrated circuit so as to couple a data bus from said first plurality of electrical contacts to said memory integrated circuit, said at least one switch having an additional input coupled to a state decoder circuit output that is responsive to a chip select signal, and responsive to said state decoder circuit output to decouple said memory circuit from said data bus when no memory access cycle is being performed. 12. The switch of claim 11, wherein the switch is integrated with a printed circuit board.
RELATED APPLICATIONS This application is a divisional of, and incorporates by reference in its entirety U.S. application No. 09/015,845, titled �HIGH SPEED DATA BUS.� This Application is related to and incorporates by reference, in each of their entirety, the following patent applications that each have been filed on even date: U.S. application No. 10/021,388, U.S. application No. 10/017,255, U.S. application No. 10/017,826, and U.S. application No. 10/017,256. This application is also related to U.S. patent application No. 10/439,593, titled �HIGH SPEED DATA BUS,� filed May 16, 2003; U.S. patent application No. 10/615,325, titled �METHOD FOR BUS CAPACITANCE REDUCTION,� filed Jul. 7, 2003; U.S. patent application No. 10/615,326, titled METHOD FOR BUS CAPACITANCE REDUCTION,� filed Jul. 7, 2003; U.S. application No. 09/782,476, titled �METHOD FOR BUS CAPACITANCE REDUCTION,� filed Feb. 13, 2001; and U.S. patent application No. 09/015,376, titled �METHOD FOR BUS CAPACITANCE REDUCTION,� filed Jan. 29, 1998.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4757215Jun 29, 1987Jul 12, 1988Samsung Semiconductor & Telecommunications Co., Ltd.Data transmission circuit having decreased parasitic capacitanceUS4855902May 24, 1988Aug 8, 1989Honeywell, Inc.Microprocessor assisted data block transfer apparatusUS5014242Dec 8, 1988May 7, 1991Hitachi, Ltd.Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuitUS5046050Apr 10, 1990Sep 3, 1991National Semiconductor CorporationShared BiCMOS sense amplifierUS5115413Mar 20, 1990May 19, 1992Hitachi, Ltd.Semiconductor memory deviceUS5148047Feb 14, 1992Sep 15, 1992Motorola, Inc.CMOS bus driver circuit with improved speedUS5260892Nov 21, 1991Nov 9, 1993Sun Microsystems, Inc.Computer memory moduleUS5303192Feb 6, 1992Apr 12, 1994Fujitsu LimitedSemiconductor memory device having information indicative of presence of defective memory cellUS5319595Oct 9, 1992Jun 7, 1994Nec CorporationSemiconductor memory device with split read data bus systemUS5357478Sep 30, 1991Oct 18, 1994Mitsubishi Denki Kabushiki KaishaSemiconductor integrated circuit device including a plurality of cell array blocksUS5465229Nov 28, 1994Nov 7, 1995Sun Microsystems, Inc.Single in-line memory moduleUS5499215Oct 11, 1994Mar 12, 1996Matsushita Electronics CorporationSemiconductor memoryUS5537584Jan 4, 1995Jul 16, 1996Hitachi Maxell, Ltd.Power instability control of a memory card and a data processing device thereforUS5561622 *Sep 13, 1993Oct 1, 1996International Business Machines CorporationIntegrated memory cube structureUS5586076Sep 13, 1994Dec 17, 1996Mitsubishi Denki Kabushiki KaishaSemiconductor memory device permitting high speed data transfer and high density integrationUS5732042Oct 29, 1996Mar 24, 1998International Business MachinesDram array with local latchesUS5732245Apr 12, 1996Mar 24, 1998Pitney Bowes Inc.Multi-memory access limiting circuit for a multi-memory deviceUS5764590Oct 22, 1996Jun 9, 1998Mitsubishi Denki Kabushiki KaishaSynchronous semiconductor memory device which allows switching of bit configurationUS5802395Jul 8, 1996Sep 1, 1998International Business Machines CorporationHigh density memory modules with improved data bus performanceUS5877975Aug 13, 1996Mar 2, 1999Nexcom Technology, Inc.Insertable/removable digital memory apparatus and methods of operation thereofUS5930187Oct 31, 1997Jul 27, 1999Kabushiki Kaisha ToshibaOne-chip LSI including a general memory and a logicUS5953215Jun 26, 1998Sep 14, 1999Karabatsos; ChrisFor enhancing the performance of an electronic systemUS5987623Mar 26, 1997Nov 16, 1999Oki Electric Industry Co., Ltd.Terminal mapping apparatusUS6002632Sep 17, 1998Dec 14, 1999Texas Instruments IncorporatedCircuits, systems, and methods with a memory interface for augmenting precharge controlUS6011710 *Oct 30, 1997Jan 4, 2000Hewlett-Packard CompanyCapacitance reducing memory system, device and method* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7075808 *Mar 24, 2005Jul 11, 2006Micron Technology Inc.Method for bus capacitance reductionUS8352080 *Oct 21, 2009Jan 8, 2013Lennox Industries Inc.Communication protocol system and method for a distributed-architecture heating, ventilation and air conditioning networkUS8527096Oct 24, 2008Sep 3, 2013Lennox Industries Inc.Programmable controller and a user interface for sameUS8713697Jul 9, 2008Apr 29, 2014Lennox Manufacturing, Inc.Apparatus and method for storing event information for an HVAC systemUS20100106320 *Oct 21, 2009Apr 29, 2010Lennox Industries Inc.Communication protocol system and method for a distributed-architecture heating, ventilation and air conditioning network* Cited by examinerClassifications U.S. Classification365/63, 365/189.05, 365/51, 365/230.06International ClassificationG06F13/16, G06F12/00, G06F13/40, G06F13/42, G11C11/4096, G11C7/10Cooperative ClassificationG11C7/1072, G06F13/1684, G06F13/4234, G11C7/1048, G11C7/1006, G11C11/4096, G06F13/4068, G06F13/4022European ClassificationG06F13/42C3, G06F13/40E2, G06F13/16D6, G06F13/40D2, G11C7/10P, G11C11/4096, G11C7/10S, G11C7/10LLegal EventsDateCodeEventDescriptionNov 9, 2011FPAYFee paymentYear of fee payment: 8Jan 4, 2010ASAssignmentOwner name: ROUND ROCK RESEARCH, LLC,NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;US-ASSIGNMENT DATABASE UPDATED:20100204;REEL/FRAME:23786/416Effective date: 20091223Owner name: ROUND ROCK RESEARCH, LLC,NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;US-ASSIGNMENT DATABASE UPDATED:20100203;REEL/FRAME:23786/416Effective date: 20091223Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;US-ASSIGNMENT DATABASE UPDATED:20100211;REEL/FRAME:23786/416Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;US-ASSIGNMENT DATABASE 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