Source: http://www.google.fr/patents/US8019975
Timestamp: 2013-05-21 16:36:56
Document Index: 276250955

Matched Legal Cases: ['Application No. 1994', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 1994', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000']

Brevet US8019975 - System and method for handling load and/or store operations in a superscalar ... - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Historique Web | Connexion Recherche avanc�e dans les brevets BrevetsThe present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order...http://www.google.fr/patents/US8019975?utm_source=gb-gplus-shareBrevet US8019975 - System and method for handling load and/or store operations in a superscalar microprocessor Num�ro de publicationUS8019975 B2Type de publicationOctroi Num�ro de demande11/113,135 Date de publication13 sept. 2011 Date de d�p�t25 avr. 2005 Date de priorit�29 sept. 1992Autre r�f�rence de publicationUS20050283591 InventeursCheryl Senter BrashearsSanjiv GargYasuaki HagiwaraTe-Li LauDerek J. LentzYoshiyuki MiyayamaLe Trong NguyenQuang H. TrangSze-Shun WangJohannes Wang Cessionnaire d'origineSeiko-Epson Corporation Classification aux �tats-Unis712/225712/23712/220 Classification internationaleG06F7/38G06F9/44G06F9/00G06F15/00G06F9/38G06F15/76G06F9/312G06F9/318 Classification coop�rativeG06F9/3017G06F9/3826G06F9/3853G06F9/3004G06F9/3824G06F9/30087G06F9/3836G06F9/3885G06F9/3834G06F9/30043G06F9/30174 Classification europ�enneG06F 9/38EG06F 9/38D4G06F 9/30A2LG06F 9/30A2G06F 9/30A8SG06F 9/38D1G06F 9/38TG06F 9/38E6G06F 9/30U2G06F 9/30UG06F 9/38DR�f�rencesCitations de brevets (100)Citations hors brevets (99) R�f�renc� par (1)Liens externesUSPTO Cession USPTO EspacenetSystem and method for handling load and/or store operations in a superscalar microprocessorUS 8019975 B2 R�sum� The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
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