Source: http://www.google.com/patents/US7301748?dq=patent:+7360079
Timestamp: 2016-07-01 14:15:22
Document Index: 11647714

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'application No. 10', 'Application No. 2002320289']

Patent US7301748 - Universal energy conditioning interposer with circuit architecture - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThe present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a...http://www.google.com/patents/US7301748?utm_source=gb-gplus-sharePatent US7301748 - Universal energy conditioning interposer with circuit architectureAdvanced Patent SearchPublication numberUS7301748 B2Publication typeGrantApplication numberUS 11/169,926Publication dateNov 27, 2007Filing dateJun 30, 2005Priority dateApr 8, 1997Fee statusLapsedAlso published asUS7609500, US7609501, US7733621, US8004812, US20050286198, US20080158746, US20080160681, US20100078199, US20100307810Publication number11169926, 169926, US 7301748 B2, US 7301748B2, US-B2-7301748, US7301748 B2, US7301748B2InventorsAnthony A. Anthony, William M. AnthonyOriginal AssigneeAnthony Anthony A, Anthony William MExport CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (85), Referenced by (41), Classifications (41), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetUniversal energy conditioning interposer with circuit architecture
US 7301748 B2Abstract
1. An energy conditioning, comprising a G conductive structure, said G conductive structure comprising:
a first conductive layer, said first conductive layer having top and bottom major surfaces, a first conductive layer first side edge surface, and a first conductive layer second side edge surface;
a second conductive layer above said first conductive layer, said second conductive layer having a second conductive layer first side edge surface and a second conductive layer second side edge surface;
a third conductive layer above said second conductive layer, said third conductive layer having a third conductive layer first side edge surface and a third conductive layer second side edge surface;
a first conductive connection structure physically and conductively contacting to said first conductive layer first side edge surface, said second conductive layer first side edge surface, and said third conductive layer first side edge surface; and
a second conductive connection structure physically and conductively contacting to said first conductive layer second side edge surface, said second conductive layer second side edge surface, and said third conductive layer second side edge surface.
2. The conditioner of claim 1 wherein said first conductive layer first side edge surface, said second conductive layer first side edge surface, and said third conductive layer first side edge surface are aligned with one another.
3. The conditioner of claim 1 wherein said first conductive layer first side edge surface and said first conductive layer second side edge surface are on opposite ends of said first conductive layer from one another.
4. The conditioner of claim 1 further comprising:
additional conductive layers above said third conductive layer each of which having a first side edge and a second side edge, and wherein said first conductive connection structure physically and conductively contacts to the first side edges of all of said additional conductive layers, and wherein said second conductive connection structure physically and conductively contacts to the second side edges of all of said additional conductive layers.
5. The conditioner of claim 1 wherein said G conductive structure consists of an odd total number of conductive layers in a stack of layers including said first conductive layer.
6. The conditioner of claim 1 wherein:
(1) said first conductive layer, said second conductive layer, and the portions of said first conductive connection structure and said second conductive connection structure connecting said first conductive layer to said second conductive layer define a first cage structure;
(2) said second conductive layer, said third conductive layer, and the portions of said first conductive connection structure and said second conductive connection structure connecting said second conductive layer to said third conductive layer define a second cage structure;
a first layer of an A differential electrode contained in said first cage structure; and
a first layer of a B differential electrode contained in said second cage structure.
7. The conditioner of claim 6 wherein said A conductive structure consists of an odd total number of conductive layers in a stack of layers including said first layer of said A differential electrode.
8. The conditioner of claim 6 wherein said B conductive structure consists of an odd total number of conductive layers in a stack of layers including said first layer of said B differential electrode.
9. The conditioner of claim 6 further comprising additional cage structures having the same shape as said first cage structure, wherein adjacent cage structures have an adjoining wall formed from a single conductive layer.
10. The conditioner of claim 9 wherein a total number of the cage structures is an even number.
11. The conditioner of claim 9 wherein no more than a single conductive layer a differential electrode resides inside of any one of the cage structures.
12. The conditioner of claim 9 wherein at least one of the cage structures contains no conductive layer of any differential electrode.
13. The conditioner of claim 9 wherein a pair of adjacent cage structures both contain conductive layers of the same differential electrode.
14. A method of making an energy conditioning, said method comprising providing a G conductive structure, said G conductive structure comprising:
15. The method of claim 14 wherein said first conductive layer first side edge surface, said second conductive layer first side edge surface, and said third conductive layer first side edge surface are aligned with one another.
16. The method of claim 14 wherein said first conductive layer first side edge surface and said first conductive layer second side edge surface are on opposite ends of said first conductive layer from one another.
providing additional conductive layers above said third conductive layer each of which having a first side edge and a second side edge, and wherein said first conductive connection structure physically and conductively contacts to the first side edges of all of said additional conductive layers, and wherein said second conductive connection structure physically and conductively contacts to the second side edges of all of said additional conductive layers.
18. The method of claim 14 wherein said G conductive structure consists of an odd total number of conductive layers in a stack of layers including said first conductive layer.
20. A method of using an energy conditioning comprising a G conductive structure, said G conductive structure comprising:
a second conductive connection structure physically and conductively contacting to said first conductive layer second side edge surface, said second conductive layer second side edge surface, and said third conductive layer second side edge surface; and
said method comprising connecting terminals of said conditioner in a circuit across a source and a load.
This application is a continuation of application Ser. No. 10/237,079, filed Sep. 9, 2002, now U.S. Pat. No. 7,110,227 which is a continuation-in-part of Ser. No. 09/632,048, filed Aug. 3, 2000, now U.S. Pat. No. 6,738,249 which is a continuation-of-part of application Ser. No. 09/600,530, filed Jul. 18, 2000, now U.S. Pat. No. 6,498,710 which is a continuation-in-part of application Ser. No. 09/594,447 filed Jun. 15, 2000, now U.S. Pat. No. 6,636,406 which is a continuation-in-part of application Ser. No. 09/579,606 filed May 26, 2000, now U.S. Pat. No. 6,373,673 which is a continuation-in-part of application Ser. No. 09/460,218 filed Dec. 13, 1999, now U.S. Pat. No. 6,331,926 which is a continuation of application Ser. No. 09/056,379 filed Apr. 7, 1998, now issued as U.S. Pat. No. 6,018,448, which is a continuation-in-part of application Ser. No. 09/008,769 filed Jan. 19, 1998, now issued as U.S. Pat. No. 6,097,581, which is a continuation-in-part of application Ser. No. 08/841,940 filed Apr. 8, 1997, now issued as U.S. Pat. No. 5,909,350. This application also claims the benefit of U.S. Provisional Application No. 60/146,987 filed Aug. 3, 1999, U.S. Provisional Application No. 60/165,035 filed Nov. 12, 1999, U.S. Provisional Application No. 60/180,101 filed Feb. 3, 2000, U.S. Provisional Application No. 60/185,320 filed Feb. 28, 2000, U.S. Provisional Application No. 60/191,196 filed Mar. 22, 2000, U.S. Provisional Application No. 60/200,327 filed Apr. 28, 2000, U.S. Provisional Application No. 60/203,863 filed May 12, 2000, and U.S. Provisional Application No. 60/215,314 filed Jun. 30, 2000.
This application incorporates by reference all of the disclosure, including the specification, claims, and figures in application No. 10/237,079, filed Sep. 09, 2002.
Existing prior art discrete decoupling capacitors lose their effectiveness at about 500 MHz. For example, mounting inductance for 0603 size capacitors has been reduced to approximately 300 pH. Assuming 200 pH for the internal capacitance of the capacitors, this equates to a total of 500 pH, which corresponds to 1.57-Ohms at 500 MHz. Accordingly, current discrete capacitors are not effective. While it is possible to use multiple components that have various values of series resonant frequencies and low ESR capacitors to drive towards low impedance at 500 MHz, the capacitance required to obtain 500 MHz with 500 pH ESL is about 200 pF. Current board materials (FR4, 4 mils dielectric)—get 225 pF for every square inch of energy planes, which would require more than one discrete capacitor every square inch. Normally, various interposers that contain multiple discrete passive component structures offer into the circuitry a lack of electrical balance that in turn creates additional discontinuities with their presence in the energized circuit system.
There are two kinds of grounds normally found in today's electronics: earth-ground and circuit ground. The earth is not an equipotential surface, so earth ground potential can vary. Additionally, the earth has other electrical properties that are not conducive to its use as a return conductor in a circuit. However, circuits are often connected to earth ground for protection against shock hazards. The other kind of ground or common conductive pathway, circuit common conductive pathway, is an arbitrarily selected reference node in a circuit—the node with respect to which other node voltages in the circuit are measured. All common conductive pathway points in the circuit do not have to go to an external grounded trace on a PCB, Carrier or IC Package, but can be taken directly to the internal common conductive pathways. This leaves each current loop in the circuit free to complete itself in whatever configuration yields minimum path of least impedance for portions of energy effected in the AOC of the new invention. It can work for frequencies wherein the path of least impedance is primarily inductive.
Use of the invention will allow placement into a differentially operated circuitry and will provide a virtually electrically balanced and essentially, equal capacitance, inductive and resistance tolerances of one invention unit, that is shared and located between each paired energy pathway within the device, equally, and in a balanced electrical manner. Invention manufacturing tolerances or pathway balances between a commonly shared central conductive pathway found internally within the invention is maintained at levels that originated at the factory during manufacturing of the invention, even with the use of common non-conductive materials, dielectrics or conductive materials, which are widely and commonly specified among discrete units. Thus, an invention that is manufactured at 5% tolerance, when manufactured as described in the disclosure will also have a correlated 5% electrical tolerance between single or multiple, paired energy pathways in the invention when placed into an energized system. This means that the invention allows the use of relatively inexpensive materials; due to the nature of the architecture's minimal structure such that variation is reduced and the proper balance between energized paired pathways or differential energy pathways is obtained.
Attachment to an external conductive area includes an industry attachment methodology that includes industry accepted materials and processes used to accomplish connections that can be applied in most cases openly without additional constraints imposed when using a different device architecture. Through other functions such as cancellation or minimization of mutually opposing conductors, the invention allows a low impedance pathway to develop within a Faraday cage-like unit with respect to the enveloping conductive common shields pathways that can subsequently continue to move energy out onto an externally located conductive area that can include, but is not limited to, a “floating”, non-potential conductive area, circuit or system ground, circuit system return, chassis or PCB ground, or even an earth ground.
The various attachment schemes described herein will normally allow a “0” voltage reference to develop with respect to each pair or plurality of paired differential conductors located on opposite sides of the shared central and common conductive pathway, and be equal yet opposite for each unit of a separated paired energy pathway, or structure, between the centrally positioned interposing, common conductive shield pathway used. Use of the invention allows voltage to be maintained and balanced even with multiple SSO (Simultaneous Switching Operations) states among transistor gates located within an active integrated circuit all without contributing disruptive energy parasitics back into the energized system as the invention is passively operated, within its attached circuit.
Principals of a Faraday cage-like conductive shield structure are used when the common pathways are joined to one another as described above and the grouping of common conductive pathways together coact with the larger external conductive area or surface to suppress radiated electromagnetic emissions and provide a greater, conductive surface area in which to dissipate over voltages and surges and initiate Faraday cage-like conductive shield structure electrostatic functions of suppression or minimization of parasitics and other transients, simultaneously. This is particularly true when plurality of common conductive pathways 14 are electrically coupled to earth ground but are relied upon to provide an inherent common conductive pathway for a circuit in which the invention is placed into and energized with. As mentioned earlier, inserted and maintained between common conductive pathways 14 and both electrode pathways 16A and 16B is material 28 which can be one or more of a plurality of materials having different electrical characteristics.
FIG. 1A shows an alternative embodiment of multifunctional energy conditioner 10, which includes additional means of coupling electrical conductors or circuit board connections to multi-functional energy conditioner 10. Essentially, the plurality of common conductive pathways 14 are electrically connected together by the sharing of a separately located outer edge conductive band or bands 14A and/or 14B (not shown) at each conductive electrode exit and which in turn, are then joined and/or connected to the same external conductive surface (not shown) that can possess a voltage potential when the invention is placed into a portion of a larger circuit and energized. This voltage potential coacts with the external conductive surface area or areas through conductive bands 14A and/or 14B (not shown) and the internal common conductive electrodes 14 of the embodiment, as well as any of the conductive elements (shown or not shown) that are needed to utilize a connection that allows energy to propagate.
The following sections that reference to common conductive pathway 804/804-IM, also apply to common conductive pathways 808 and 810. Common conductive pathway 804/804-IM is offset a distance 814 from the edge of the invention. One or more portions 811A and 811B of the common conductive pathway electrode 804/804-1M extends through material 801 and is attached to common conductive band or conductive material structures 802A and 802B. Although not shown, common 802A and 802B electrically connects common conductive pathways 804/804-IM, 808 and 810 to each other and to all other common conductive pathways (860/860-IM, 840, 830, and 860/860-IM) if used.
As has described in FIG. 3, the dielectric material 801, conductively separates the individual common conductive pathway electrodes 830, 810, 804/804-IM, 808, 840, from the conductive pathway electrodes (not shown) sandwiched therein. In addition, as described in relation to FIG. 3, a minimum of two cages, for example 800B and 800C, which make up larger cage 900A, are required to make-up a multi-functional line-conditioning structure for use in all of the layered embodiments of the present invention. Accordingly, there are a minimum of two required common conductive cage like structures 800X, as represented in FIG. 4 per each 900A, 900B, and 900C, respectively. No matter the amount of shield layers used or the processes that derive the final form are arrived at, the very basic common conductive pathway manufacturing result of any sequence (excluding dielectric materials, etc.) should appear as an embodiment structure that is as follows: a first common conductive pathway, then a conductive pathway (not shown), then a second common conductive pathway, second conductive pathway (not shown) and a third common conductive pathway. The second common conductive pathway in the preceding results becomes the centrally positioned element of the result. For additional layering of pathways desired, additional results of a manufacturing sequence would yield as follows for example, a third conductive pathway (not shown), than a fourth common conductive pathway, a fourth conductive pathway (not shown); than a fifth common conductive pathway. If an image shield configuration is desired to be used as is shown in FIG. 4 as pathways 850/850-IM and 860/860-IM there is no difference in the first layer result other than a last set of sandwiching common conductive pathways 850/850-IM and 860/860-IM are added. Again as a result of almost any manufacturing sequence as follows: (excluding dielectric material, etc.) 860/860-IM common conductive pathway is placed, than a first common conductive pathway, then a conductive pathway (not shown), then a second common conductive pathway, second conductive pathway (not shown) and a third common conductive pathway a third conductive pathway (not shown), than a fourth common conductive pathway, a fourth conductive pathway (not shown); than a fifth common conductive pathway, finally a 850/850-IM common conductive pathway will be the resulting structure for this example in FIG. 4. In summary, most chip, non-hole thru embodiments of the applicants discreet, non-interposer energy conditioners will have a minimum of two electrodes 809 and 809′ (not shown) sandwiched between three common conductive electrodes 808 (not shown) and 804/804-IM and 810 (not shown), respectively, and a minimum of two electrodes 809 and 809′ (not shown) connect to external structures 809A and 809A′ (not shown). Three common conductive electrodes 808 (not shown) and 804/804-IM and 810 (not shown), respectively and connected external structures 802A and 802B are connected such that they are conductively considered as one to form a single, larger Faraday-cage-like structure 900A. Thus when a single, larger Faraday-cage-like structure 900A is attached to a larger external conductive area (not shown), the combination helps perform simultaneously, energized line conditioning and filtering functions upon the energy propagating along the conductors 809 and 809′ (not shown), sandwiched within the cage-like structure 900A, in an oppositely phased or charged manner. Connection of the joined common conductive and enveloping, multiple common shield pathways 808 (not shown) and 810 (not shown), respectively with a common centrally located common conductive pathway 804/804-IM will become like the extension of external conductive element 6803, as shown in FIG. 5B and will be interposed in such a multiple parallel manner that said common conductive elements will have microns of distance separation or ‘loop area’ with respect to the complimentary, phased differential electrodes that are sandwiched themselves and yet are separated from the extension of external conductive element like 6803, shown in FIG. 5B by a distance containing a dielectric medium.
Referring specifically to FIG. 5A, the by-pass shield structure 6800 is shown in cross section extending longitudinally and comprises a seven layer common conductive pathway stacking of two common conductive shield structures 1000A and 100B, which form the present embodiment of the by-pass shield structure 6800. In FIG. 5B, the by-pass shield structure 6800 is shown in cross section perpendicular to the cross section shown in FIG. 5A.
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27, 2010Jan 6, 2011Greatbatch Ltd.Shielded three-terminal flat-through emi/energy dissipating filterUS20140159200 *Dec 28, 2012Jun 12, 2014Alvin Leng Sun LokeHigh-density stacked planar metal-insulator-metal capacitor structure and method for manufacturing same* Cited by examinerClassifications U.S. Classification361/118, 257/E23.079, 257/E23.114, 257/E23.062, 257/E23.07International ClassificationH02H9/00, H01L23/50, H02H9/06, H05K1/02, H01L23/498, H03H1/00, H01L23/552, H01L23/66Cooperative ClassificationY10T29/49124, Y10T29/4913, Y10T29/49204, H01L2224/16235, H01L2924/01019, H01L2224/16265, H01L2224/16225, H01L23/66, H01L23/49838, H01L2924/3011, H01L2924/01322, H05K1/0237, H01L23/50, H05K2201/09236, H01L2924/15311, H01L23/552, H01L2924/01087, H01L2924/3025, H01L23/49822, H05K1/023, H05K2201/10378, H01L2924/10253European ClassificationH01L23/498G, H01L23/50, H05K1/02C2E, H01L23/66, H01L23/552, H01L23/498DLegal EventsDateCodeEventDescriptionJul 19, 2007ASAssignmentOwner name: X2Y ATTENUATORS, LLC, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ANTHONY, WILLIAM M.;ANTHONY, ANTHONY A.;REEL/FRAME:019575/0292Effective date: 20020909Mar 11, 2008CCCertificate of correctionJul 4, 2011REMIMaintenance fee reminder mailedSep 25, 2011SULPSurcharge for late paymentSep 25, 2011FPAYFee paymentYear of fee payment: 4Jul 10, 2015REMIMaintenance fee reminder mailedNov 27, 2015LAPSLapse for failure to pay maintenance feesJan 19, 2016FPExpired due to failure to pay maintenance feeEffective date: 20151127RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services