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Timestamp: 2018-06-20 02:06:10
Document Index: 308507371

Matched Legal Cases: ['Application No. 200610004027', 'Application No. 200610004027', 'Application No. 06250089', 'Application No. 06250089', 'Application No. 10183511', 'Application No. 10183511', 'Application No. 2006', 'Application No. 10', 'Application No. 95100745', 'Application No. 2006', 'Application No. 2010', 'Application No. 200910135462', 'Application No. 10183511', 'Application No. 06250089', 'Application No. 06250089', 'Application No. 10183511']

Translating a guest virtual address to a host physical address as guest software executes on a virtual machine - Intel Corporation
Translating a guest virtual address to a host physical address as guest software executes on a virtual machine
United States Patent 8533428
12/971911
711/2, 711/6, 711/203, 711/220, 718/1, 718/107
711/206, 711/203, 711/2, 711/6, 711/220, 718/1, 718/107
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Office Action received for European Patent Application No. 06250089.7, mailed on Apr. 23, 2009, 3 pages of Office Action.
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This application is a continuation of U.S. patent application Ser. No. 11/036,736, entitled “VIRTUALIZING PHYSICAL MEMORY IN A VIRTUAL MACHINE SYSTEM,” filed Jan. 14, 2005 now U.S. Pat. No. 7,886,126.
1. A processor to execute a virtual machine monitor on a host machine, the virtual machine monitor to control operation of guest software executing on a virtual machine, the processor comprising: execution logic to execute an instruction to transfer control of the processor from the virtual machine monitor to the guest software; and a control register to store a first pointer to a base of a page directory table in guest physical memory, the first pointer to be combined with a first plurality of bits of a guest virtual address to form a first guest physical address of a page directory entry in the page directory table during execution of the guest software on the virtual machine, the first guest physical address to be translated through a plurality of extended page tables to form a first host physical address of the page directory entry during execution of the guest software on the virtual machine.
2. The processor of claim 1 wherein the virtual machine monitor is to control operation of the guest software according to data stored in a virtual machine control structure.
3. The processor of claim 2, including logic to determine, based on an indicator stored in the virtual machine control structure, whether the processor is to translate the first guest physical address to the first host physical address using the extended page tables.
4. The processor of claim 2 wherein the virtual machine control structure is to store a second pointer to the extended page tables.
5. The processor of claim 1 wherein the page directory entry includes a base address of a guest page table in guest physical memory, the base address to be combined with a second plurality of bits of the guest virtual address to form a second guest physical address of a page table entry in the guest page table, the second guest physical address to be translated through the plurality of extended page tables to form a second host physical address of the page table entry.
6. The processor of claim 5 wherein the extended page tables include permission information.
7. The processor of claim 6 wherein the permission information indicates whether a page pointed to by the page table entry is present.
8. The processor of claim 6 wherein the permission information indicates whether a page pointed to by the page table entry is writeable.
9. The processor of claim 6 wherein the permission information indicates whether a page pointed to by the page table entry is executable.
10. The processor of claim 6, further comprising control logic to transition control of the processor to the virtual machine monitor in response to a violation of the permission information.
11. A method comprising: transferring control of a processor from a virtual machine monitor to guest software executing on a virtual machine; during execution of the guest software on the virtual machine, combining a base address of a page directory table in guest physical memory with a plurality of bits of a guest virtual address to form a guest physical address of a page directory entry in the page directory table, during execution of the guest software on the virtual machine, translating the guest physical address through a plurality of extended page tables to form a host physical address of the page directory entry.
12. The method of claim 11, wherein the virtual machine monitor is to control operation of the guest software.
13. The method of claim 12 wherein the virtual machine monitor is to control operation of the guest software according to data stored in a virtual machine control structure.
14. The method of claim 13 wherein the virtual machine control structure is to store a pointer to the extended page tables.
15. A system comprising: a memory; and a processor to execute a virtual machine monitor, the virtual machine monitor to control operation of guest software executing on a virtual machine, the processor including: execution logic to execute an instruction to transfer control of the processor from a virtual machine monitor to the guest software; and a control register to store a pointer to a base of a page directory table in guest physical memory, the pointer to be combined with a plurality of bits of a guest virtual address to form a guest physical address of a page directory entry in the page directory table during execution of the guest software on the virtual machine, the guest physical address to be translated through a plurality of extended page tables to form a host physical address of the page directory entry during execution of the guest software on the virtual machine.
16. The system of claim 15 wherein the processor is to execute the virtual machine monitor to control operation of the guest software according to data stored in a virtual machine control structure in the memory.
FIG. 3 illustrates one embodiment of a virtual-machine environment 300. In this embodiment, a processor-based platform 316 may execute a VMM 312. The VMM, though typically implemented in software, may emulate and export a virtual bare machine interface to higher level software. Such higher level software may comprise a standard OS, a real time OS, or may be a stripped-down environment with limited operating system functionality and may not include OS facilities typically available in a standard OS in some embodiments. Alternatively, for example, the VMM 312 may be run within, or using the services of, another VMM. VMMs may be implemented, for example, in hardware, software, firmware or by a combination of various techniques in some embodiments.
Operation of a virtual machine environment in an embodiment such as that previously described and depicted in FIG. 3 is depicted by processing shown in FIGS. 4a and 4b. FIG. 4a depicts the operation of a VM environment in an embodiment to process a privileged event occurring in guest software; and the operation of the embodiment to process a non-privileged event by guest software. FIG. 4b depicts operations of a VM environment in an embodiment specifically related to extended paging tables, specifically relating to guest software access to guest-physical memory and to the management of the EPT mechanism in hardware by the VMM in the embodiment. FIGS. 4a and 4b do not depict all components or all operations that may occur in an environment such as that depicted in FIG. 3. This is solely for clarity of presentation. While a small set of components and a few specific operations are represented in FIGS. 4a and 4b, a VM environment in an embodiment may comprise many other components, and many other operations may take place in such an embodiment.
FIG. 5 shows one example of processing using the extended page tables introduced above to ultimately compute a host-physical address when guest software in a virtual machine references a guest virtual address. The example depicted shows guest software running in an IA-32 platform using simple 32-bit virtual addressing and simple page table formats. One skilled in the art will easily be able to extend this example to understand, for example, other paging modes (e.g., 64-bit addressing in the guest software), other instruction set architectures (e.g., The Intel Itanium® Architecture, as specified, for example, in the Intel Itanium Architecture Software Developer's Manual, available from Intel Corporation) or other configurations.
FIG. 6 depicts another example of processing using the extended page tables introduced above to ultimately translate a guest-physical address to a host-physical address using a multi-leveled EPT table. In the exemplary embodiment shown in FIG. 6, the appropriate bits 602 in the in an EPT base pointer (EPTP) 620 indicate the host-physical address of the base of the first-level EPT table 650, which in this embodiment is stored in host-physical memory. The EPTP will be discussed in more detail below with regard to FIG. 7. In this example, the entries in the EPT tables are 8 bytes each. Bits 38:30 from the guest-physical address 610 (601) are appropriately adjusted by multiplying by 8 (for example, by shifting the value left by 3 bits) to obtain an adjusted upper guest-physical address 603. The EPT table base address value 602 is combined with (added to) the adjusted upper guest-physical address bits 603, forming the host-physical address 604 of an EPT table entry 651 in a first level EPT table 650. An exemplary format of an entry such as 651 in the first level EPT table 650 as well as entries in the other EPT tables 660 and 670 will be discussed below with regard to FIG. 8.
As shown in an exemplary embodiment depicted in FIG. 7, the EPT base address pointer (EPTP) includes bits used to form the base address (in host-physical memory) of the base of the first level EPT table such as that described above in FIG. 6. In the example depicted in FIG. 7, bits 59:12 form the base address. Bits 11:0 and 63:60 are assumed to be 0. Of course, the widths of the various bit fields may vary in other embodiments, for example the base address field will change depending on the number of address bits in a particular architecture or implementation. The remaining bits in the EPTP register may be used for other purposes in other embodiments. In one embodiment, the EPTP register is accessible only through a virtual machine entry or virtual machine exit. In such an embodiment, the EPTP register in the processor is loaded from an EPTP field in the VMCS at the time of a virtual machine entry, activating the EPT mechanism while the guest software operates. As indicated above, this activation (and loading of the EPTP field) may be controlled by other control bits within the VMCS or elsewhere.
This figure depicts an exemplary embodiment of the format of an entry in an EPT table. In this example, each entry in an EPT table is 8 bytes in size. In one embodiment, each EPT table is 4 KB in size, meaning that there are 512 EPT table entries per EPT table page. As shown in the example in FIG. 8, each EPT table entry contain the base host-physical address of the next level EPT table or page in memory (ADDR) and permission and other configuration information. As before, the widths of the various bit fields may vary in other embodiments, for example the ADDR width may change depending on the number of address bits in a particular architecture or implementation. FIG. 8 depicts only 2 permission bits, Present and Writable. In other embodiments, other permission and configuration information may be present in each EPT table entry. For example, in one embodiment, a permission bit indicates if a page of memory may be executed (i.e., if the contents of the page may be fetched and interpreted as instructions by the processor)
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