Source: http://www.google.com/patents/US8041294?dq=5,870,513
Timestamp: 2015-05-05 19:44:45
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Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US8041294 - Adaptive radio transceiver - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including...http://www.google.com/patents/US8041294?utm_source=gb-gplus-sharePatent US8041294 - Adaptive radio transceiverAdvanced Patent SearchPublication numberUS8041294 B2Publication typeGrantApplication numberUS 12/492,921Publication dateOct 18, 2011Filing dateJun 26, 2009Priority dateOct 21, 1999Also published asUS6404293, US6417737, US6608527, US7031668, US7555263, US7720444, US7970358, US20030042984, US20030067359, US20060205374, US20090286487, US20100295598Publication number12492921, 492921, US 8041294 B2, US 8041294B2, US-B2-8041294, US8041294 B2, US8041294B2InventorsAhmadreza Rofougaran, Maryam Rofougaran, Brima Ibrahim, Jacob Rael, Shahla Khorram, Shervin Moloudi, Stephen Wu, Hooman Darabi, William T. Colleran, Ed Chien, Meng-An PanOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (71), Non-Patent Citations (2), Referenced by (5), Classifications (29) External Links: USPTO, USPTO Assignment, EspacenetAdaptive radio transceiver
US 8041294 B2Abstract
a voltage comparator configured to compare a first voltage and second voltage;
a digitally tunable resistor array comprising a plurality of resistors arranged in series and a plurality of first switches, each respective first switch being coupled across a different corresponding resistor;
a digitally tunable capacitor array comprising a plurality of capacitors arranged in parallel and a plurality of second switches, each respective second switch being coupled in series with a corresponding different capacitor; and
control circuitry configured to generate a plurality of digital bits, each respective digital bit controlling a different one of the corresponding first switches and second switches,
wherein the digital bits are generated by the control circuitry as a function of the comparing of the first voltage and the second voltage.
2. The calibration circuit according to claim 1, wherein the control circuitry comprises a control logic block that has an input that receives an output signal from the voltage comparator.
3. The calibration circuit according to claim 1, wherein the calibration circuit uses CMOS circuitry.
4. The calibration circuit according to claim 1, wherein the calibration circuit is part of a wireless communications device that supports wireless communications using one or more of the following: orthogonal frequency division multiplexing, spread spectrum modulation, and direct sequence modulation.
5. The calibration circuit according to claim 1, wherein the calibration circuit is part of a wireless communications device that supports wireless communications using orthogonal frequency division multiplexing and wireless communications using spread spectrum modulation.
6. The calibration circuit according to claim 1, wherein the calibration circuit is part of a wireless communications device that supports wireless communications using orthogonal frequency division multiplexing and wireless communications using direct sequence spread spectrum modulation.
7. The calibration circuit according to claim 1, wherein the calibration circuit is part of a wireless communications device that supports wireless communications using orthogonal frequency division multiplexing and wireless communications using frequency hopping.
8. The calibration circuit according to claim 1, wherein the voltage comparator, the digitally tunable resistor array, the digitally tunable capacitor array, the first switches and the second switches are part of a single integrated circuit chip.
9. The calibration circuit according to claim 1, wherein the calibration circuit is configured to compensate for one or more of the following: process variation, temperature variation, and power supply variation.
10. The calibration circuit according to claim 1, wherein the calibration circuit is configured to provide dynamic calibration for resistor-capacitor circuits in a transmitter circuit, a receiver circuit, or a local oscillator generator circuit of a wireless communications device.
11. The calibration circuit according to claim 1, wherein the calibration circuit is configured to provide dynamic calibration for resistor-capacitor circuits in a transmitter and a receiver of a wireless communications device.
12. The calibration circuit according to claim 1, wherein the transmitter circuit, a receiver circuit, and a local oscillator generator circuit are integrated into a single integrated circuit chip.
13. The calibration circuit according to claim 1, wherein the plurality of capacitors comprise metal-insulator-metal capacitors.
14. The calibration circuit according to claim 1, wherein each respective first switch is configured to provide a path that bypasses the corresponding resistor.
15. The calibration circuit according to claim 1, wherein each respective first switch is configured to switch the corresponding resistor in and out of the digitally tunable resistor array.
16. The calibration circuit according to claim 1, wherein each respective second switch is configured to switch the corresponding capacitor in and out of the digitally tunable capacitor array.
17. The calibration circuit according to claim 1, wherein the first voltage is a resistor voltage, and wherein the second voltage is a capacitor voltage.
18. The calibration circuit according to claim 1, wherein the first voltage or the second voltage comprises a voltage across the digitally tunable resistor array or a voltage across a digitally tunable capacitor array.
19. The calibration circuit according to claim 1, wherein the first voltage is a voltage across a reference resistor.
20. The calibration circuit according to claim 1, wherein the first voltage or the second voltage comprises a resistor voltage or a capacitor voltage.
The present application is a CONTINUATION OF U.S. application Ser. No. 09/634,552, filed Aug. 8, 2000.
Said U.S. application Ser. No. 09/634,552 also claims benefit from and priority to the following U.S. provisional applications: U.S. Application No. 60/160,806, filed Oct. 21, 1999; U.S. Application No. 60/163,487, filed Nov. 4, 1999; U.S. Application No. 60/163,398, filed Nov. 4, 1999; U.S. Application No. 60/164,442, filed Nov. 9, 1999; U.S. Application No. 60/164,194, filed Nov. 9, 1999; U.S. Application No. 60/164,314, filed Nov. 9, 1999; U.S. Application No. 60/165,234, filed Nov. 11, 1999; U.S. Application No. 60/165,239, filed Nov. 11, 1999; U.S. Application No. 60/165,356, filed Nov. 12, 1999; U.S. Application No. 60/165,355, filed Nov. 12, 1999; U.S. Application No. 60/172,348, filed Dec. 16, 1999; U.S. Application No. 60/201,335, filed May 2, 2000; U.S. Application No. 60/201,157, filed May 2, 2000; U.S. Application No. 60/201,179, filed May 2, 2000; U.S. Application No. 60/201,330, filed May 2, 2000; and U.S. Application No. 60/202,997, filed on May 10, 2000.
In one aspect of the present invention, a method of wireless communications using a transceiver having a receiver and transmitter includes programming one of the receiver and the transmitter, receiving a first signal at the receiver from a wireless source, and transmitting a second signal from the transmitter into space.
In another aspect of the present invention, a method of wireless communications using a transceiver having a receiver, transmitter and local oscillator includes programming a frequency of a clock in the local oscillator, receiving a first signal at the receiver from a wireless source, downconverting the received first signal with the clock, upconverting a second signal with the clock, and transmitting the upconverted second signal from a transmitter into space.
In yet another aspect of the present invention, an adaptive transceiver includes a receiver having programmable component, a transmitter coupled to the receiver and having a programmable component, and a controller to program one of the receiver and transmitter components.
In a further aspect of the present invention, an adaptive transceiver includes means for receiving a first signal from an external wireless source, means for transmitting a second signal into space, and means for programming one of the receiving means and transmitting means.
In yet a further aspect of the present invention, an adaptive transceiver includes means for receiving a first signal from a wireless source, means for downconverting the received first signal with a clock, means for upconverting a second signal with the clock, means for transmitting the upconverted second signal into space, and means for programming a frequency of the clock.
In still yet a further aspect of the present invention, an integrated circuit includes a receiver having programmable component, a transmitter having a programmable component, and a controller to program one of the receiver and transmitter components.
FIG. 21 is a system block diagram of a signal processing system operating in a real time fax relay mode in accordance with an exemplary embodiment of the present invention;
FIG. 22 is a diagram of the message flow for a fax relay in non error control mode in accordance with an exemplary embodiment of the present invention;
FIG. 23 is a flow diagram of a method for fax mode spoofing in accordance with an exemplary embodiment of the present invention;
FIG. 24 is a block diagram of several signal processing systems in the modem relay mode for interfacing between a switched circuit network and a packet based network in accordance with an exemplary embodiment of the present invention;
The LO generator 14 provides the infrastructure for frequency planning. The LO generator 14 includes an IF clock generator 44 and an RF clock generator 47. The IF clock generator includes an oscillator 38 operating at a ratio of the RF signal (fOCS) High stability and accuracy can be achieved in a number of ways including the use of a crystal oscillator.
jω → j ( ω - ω 0 ) BW ( 5 ) where ω0 is the bandpass (BP) center frequency, and BW is the lowpass (LP) equivalent bandwidth, equal to half of the bandpass filter bandwidth. For instance, for a second-order biquad stage (as shown in FIG. 6), ω0=2Q/RC, and BW=1/RC. The biquad stage is designed by finding its LP equivalent frequency response using equation (5). Once the LP poles are known, the BP poles are calculated based on equation (5). Assume that the LP equivalent has n poles, and pi,LP=αi+jβi is the ith pole. From equation (5), the BP pole will be:
Y i = 1 R z + jω C z ( 11 ) which is not desirable, since the zero will be in the left-half plane, rather than the jω axis.
ωz/,2=ω0�ωz,LP �BW (15)
The center frequency of the complex filter can be adjusted by setting 1/RuCu equal to a reference frequency generated, by way of example, the crystal oscillator in the controller. The filter is automatically tuned by monotonic successive approximation as described in detail in Section 4.0 herein. Once the value of RuCu is set, the complex filter characteristics depends only on four-bit code for the capacitors and the four-bit code for the resistors. For example, assume that the value of the resistors in the biquad stage of FIG. 6 is as following: Ri=nARu, Rf=nQRu, and Rc=nQRu. Likewise, assume that C=nCCu where nC is a constant, and that 1/RuCu=ωu. The value of ωu is set to a reference crystal by a successive approximation feedback loop. The filter frequency response for the received signal will be:
A 2β2νin 2 +A 4β4νin 4 + . . . +A 2(n-m)β2(n-m)νin 2(n-m) +mβ 2 S 2 =RSSI (25)
The factor ⅓ appears in the above equations because the third harmonic of a square-wave has an amplitude which is one third of the main harmonic. Comparing equation (46) with equation (48), the two products are added in equation (46), while they are subtracted in equation (47). The reason is that for the main harmonic of the VCO, quadrature outputs have phases of 0 and 90�, whereas for the third harmonic, the phases are 0 and 270�. The same holds true for equation (45) and equation (47). The two cosines in equation (45) and equation (47), when added, give a cosine at 2ω1 with an amplitude of 2/3, yet the two sinewaves in equation (46) and equation (48) when added, give a component at 2ω1 with an amplitude of 4/3. Therefore, a significant amplitude imbalance exists at the I and Q outputs of the mixers. When these signals pass through the nonlinear buffer at the mixers output, the amplitude imbalance will be reduced. However, because of the AM to PM conversion, some phase inaccuracy will be introduced. The accuracy can be improved with a quadrature generator, such as a polyphase filter, after the mixers. A polyphase filter, however, is lossy, especially at high frequency, and it can load its previous stage considerably. This increases the LO generator power consumption significantly, and renders the choice of N=1 unattractive for embodiments of the present invention employing a low-IF receiver architecture with quadrature LO signals.
The following discussion changes based on the Q value. Considering a Q of about 5 for the inductor, with f0=1.5f1, the spur located at 2.5f1 is rejected by about 15 dB by each LC circuit. This spur is produced at the LO generator output due to the mixing of the VCO third harmonic (at 3f1) with the divider output (at 0.5f1). This signal is attenuated by 10 dB since the third harmonic of a square-wave is one third of the main harmonic, 15 dB at the LC resonator at the mixers output tuned to 1.5f1, and another 15 dB at the output of the buffers (900, 902 in FIG. 33). This gives a total rejection of 40 dB. When applied to the mixers in the transmitter, this LO generator output will upconvert the baseband data to 2.5f1. With LC filters (not shown) positioned at the upconversion mixers and PA output in the transmitter, another 15+15=30 dB rejection is obtained (FIG. 33).
The spur located at 0.5f1 is produced because of the third harmonic of the divider output (at 1.5f1) is mixed with the VCO output (at f1). Because of the hard switching action at the divider output, the third harmonic is about 10 dB lower than the main harmonic at 0.5f1. The buffer at the divider output tuned to 0.5f1(892, 8943 in FIG. 33), rejects this signal by about 22 dB (equation (24)). This spur can be further attenuated by LC circuits at the mixer and its buffer output by (2)(22)=44 dB. The total rejection is 76 dB.
FIG. 33( a) shows a signal passing through a limiting buffer 910 (such as the buffers implemented in the LO generator). When a large signal at a frequency of f accompanied with a small interferer at a frequency of Δf 902 away pass through a limiting buffer, at the limiter output the interferer produces two tones�Δf 914, 916 away from the main signal, each with 6 dB lower amplitude. Therefore, the spur at 2.5f1 will actually be 10+15+15+6=46 dB attenuated when it passes through the buffer, instead of the 40 dB calculated above. It will also produce an image at 0.5f1 which is 10+15+22+6=53 dB lower than the main signal. This will dominate the spur at 0.5f1 because of the third harmonic of the divider mixed with the VCO signal, which is more than 75 dB lower than the main signal.
The above equations show that regardless of the value of θ, the outputs are always in quadrature. However, other effects should be evaluated. First, a spur at ω1−ω2=0.5ω1 is produced at the output. This spur can be attenuated by 2�22=44 dB by the LC filters at the mixer and its buffer outputs. Thus, for 60 dB rejection, the single sideband mixers need to provide an additional 16 dB of rejection(about 0.158). Based on equation (53), tan(θ/2)=0.158, or θ�18�, phase accuracy of better than 18� can generally be achieved. Second, phase error at the VCO output lowers the mixer gain (term Cos(θ/2) in equation (52) or (53)). For a phase error of 18�, the gain reduction is, however, only 0.1 dB, which is negligible. For θ=90� (a single-phase VCO), both sidebands are equally upconverted at the mixer output. However, the LC filters reject the lower sideband by about 44 dB. The mixer gain will also be 3 dB lower. This will slightly increase the power consumption of the LO generator. If θ=180� (the VCO I and Q outputs are switched), the lower sideband is selected, and the desired sideband is completely rejected.
Transistors 818 and 820 form a cross-coupled pair that injects a current into tank #1 that is exactly 180 degrees out of phase with V1. Likewise, transistors 822 and 824 form a cross-coupled pair that injects a current into tank #2 that is exactly 180 degrees out of phase with V2. The first set of coupling devices 834, 836 injects a current into tank #2 that is in-phase with V1. The second set of coupling devices 838, 840 injects a current into tank #1 that is in phase with V2. The tank impedances causes a frequency dependent phase shift. By varying the amplitude of the coupled signals, the frequency of oscillation changes until the phase shift through the tanks results in a steady-state solution. Varying the bias of the current source controls the gm of the coupling devices. Current sources 812, 816 provide control of VCO tuning. Current sources 810, 814 provide segmentation of the VCO tuning range.
The programming data from the addressable registers 900-908 and the calibration data from the RC calibration circuit 907 and the bandgap calibration circuit 908 are coupled to an output register 909. The output register 909 formats the programmability and calibration data into a data packets. Each data packet includes a header or preamble which addresses the appropriate transceiver component. The data packets are then transmitted serially over a controller bus 910 to their final destination. Byway of example, the output register 909 packages the programming data from the power amplifier register 900 with the header or preamble for the power amplifier and outputs the packaged data as the first data packet to the controller bus 910.
With an input dynamic range of 50 dB, the RSSI circuit is designed to detect the levels of rejection provided by the polyphase filtering. The outputs of RSSI block 284 and RSSI block 285 are coupled to a comparator 280 where the level of signal rejection of each polyphase filter is compared by comparator 280. The outputs of the RSSI blocks are also coupled to the control logic 286. The control logic 286 determines from the RSSI outputs which polyphase filter has a lower amount of signal suppression. Then, the control logic 286 adjusts the frequency tuning of that filter in an incremental step via the control logic 286. This is done by either increasing the tuned frequency of the first filter (polyphase A) filter 280, or by decreasing the tuned frequency of the second filter (polyphase B) 282 by changing the appropriate 4-bit control word. This process continues in successive steps until the 4-bit control word in each branch are identical, at which point, the RC values of the two polyphase filters are equal. This results in a change of state of the comparator 288 output. The change in state of the comparator output disables the control logic 286 locking up the 4-bit control word for optimum calibration of the RC circuits in the transmitter, receiver and LO generator. The 4-bit control word provides a maximum deviation of only �5%.
The switches can be binary-weighted in size and the switch sizes can be chosen according to tradeoffs regarding parasitic capacitances and frequency limitations based on the on-resistance of the CMOS switches. The capacitive error resulting from the parasitic capacitance in each capacitive array does not result in frequency error between the three polyphase stages of the RC calibration circuit in the controller. This is because by using same capacitor array in each filter, and by scaling the resistance accordingly in each case. Scaling resistances, relative to those in the fundamental polyphase filter, by factors of ⅓ and ⅕ in the 3rd and 5th harmonic filters respectively, are achieved with a high degree of accuracy with proper layout. Similarly, RC tuning in all other blocks utilizing the calibrated code is optimized when an identical capacitive array is used, scaling only the resistance value in tuning to the desired frequency. The capacitors in the capacitive arrays are laid out in 100fF increments to improve the matching and parasitic fringing effects.
FIG. 42 shows an exemplary embodiment of the bandgap calibration circuit. The bandgap calibration circuit uses the reference clock provided from the LO generator and a reference resistor RREF 236 to adjust a tunable resistance value RPOLY 238 in a compare-and-increment loop until an optimum value is obtained. In embodiments of the present invention which are integrated into a single IC, the reference resistor RREF 236 can be off-chip to provide improved calibration accuracy. A 4-bit control word is output to accurately calibrate the resistors in the transmitter, receiver and LO generator within �2%. Transistors 227, 226, 228, 230, 232, 234 form a cascode current with a reference current IREF. The transistors 224, 230 each have their gates tied to their respective sources to set up the reference current IRFF. By tying the gates of the transistors 224, 230, respectively to the gates of the transistors 226, 232, the reference current IREF is mirrored to the reference resistor RREF 236. Similarly, by tying the gates of the transistors 228, 234, respectively to the gates of the transistors, the reference current IREF is also mirrored to the tunable resistor RPOLY 238. The voltage generated across the tunable resistor RPOLY 238 is compared, using a latched comparator 240, to the voltage generated across the reference resistor RREF 236. The value of the tunable resistor RPOLY 236 is incremented in successive steps, preferably, every 0.5 μs, through the utilization of control logic 242 that is clocked, byway of example, at 2 MHz. This process continues until the voltage VPOLY across the tunable resistor RPOLY 238 matches the voltage VREF across the off-chip reference resistor RREF 236 causing the output of the comparator to change states and disable the control logic 242. Once the control logic is disabled, the 4-bit control word can be used to accurately calibrate the resistors in the transmitter, receiver and LO generator.
The bandgap calibration circuit can be used for numerous applications. By way of example, FIG. 43 shows a bandgap calibration circuit 244 used in an application for calibrating a bandgap reference current that is independent of temperature. The 4-bit control word from the bandgap calibration circuit is coupled, by way of illustration, to the receiver. The 4-bit control word is used to calibrate resistances in a proportional-to-absolute-temperature (PTAT) bias circuit 246, and also in a VBE (negative temperature coefficient) bias circuit 248. The outputs of these block(s are two bias voltages, VP 250 and VN, 252 that generate currents exhibiting a positive temperature coefficient, and a negative temperature coefficient, respectively. When these currents are summed together using the cascode current mirror formed by transistors 254, 256, 258, 260, the result is a current IOUT displays a (ideally) zero temperature coefficient.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3932814 *May 20, 1974Jan 13, 1976Takeda Riken Kogyo KabushikikaishaHeterodyne receiver systemUS4129832 *Jun 20, 1977Dec 12, 1978Harris CorporationMethod and means for linearizing a voltage controlled oscillator sweep generatorUS4429418 *Jul 11, 1980Jan 31, 1984Microdyne CorporationFrequency agile satellite receiverUS4460872 *Dec 3, 1981Jul 17, 1984Inventab Audio KbLow noise differential amplifierUS4499435 *Sep 30, 1982Feb 12, 1985Harris CorporationSystem for linearizing sweep of voltage controlled oscillatorUS4580289 *Jun 21, 1984Apr 1, 1986Motorola, Inc.Fully integratable superheterodyne radio receiver utilizing tunable filtersUS4581593 *May 3, 1984Apr 8, 1986Sony CorporationVariable frequency oscillating circuitUS4723318 *Dec 16, 1985Feb 2, 1988U.S. Philips CorporationActive polyphase filtersUS4893316 *Jul 24, 1986Jan 9, 1990Motorola, Inc.Digital radio frequency receiverUS4914408 *Apr 24, 1989Apr 3, 1990U.S. Philips CorporationAsymmetric polyphase filterUS5014021 *Feb 8, 1990May 7, 1991Hughes Aircraft CompanyFrequency linearization circuit for a microwave VCO in ridged waveguideUS5108334 *Jun 1, 1989Apr 28, 1992Trimble Navigation, Ltd.Dual down conversion GPS receiver with single local oscillatorUS5146186 *May 13, 1991Sep 8, 1992Microsource, Inc.Programmable-step, high-resolution frequency synthesizer which substantially eliminates spurious frequencies without adversely affecting phase noiseUS5155452 *Nov 12, 1991Oct 13, 1992Silicon Systems, Inc.Linearized and delay compensated all CMOS VCOUS5177450 *Oct 4, 1991Jan 5, 1993Samsung Electronics Co., Ltd.Cmos power amplifierUS5179725 *Mar 29, 1991Jan 12, 1993International Business MachinesVoltage controlled oscillator with correction of tuning curve non-linearitiesUS5212459 *Oct 13, 1992May 18, 1993Silicon Systems, Inc.Linearized and delay compensated all CMOS VCOUS5235335 *Jun 2, 1992Aug 10, 1993Texas Instruments IncorporatedCircuit and method for tuning capacitor arraysUS5243302 *Sep 8, 1992Sep 7, 1993International Business Machines CorporationVoltage controlled oscillator with correction of tuning curve non-linearitiesUS5281924 *Nov 1, 1990Jan 25, 1994Italtel Societa Italiana Telecomunicazione S.P.A.Fully differential CMOS power amplifierUS5283484Oct 13, 1992Feb 1, 1994Motorola, Inc.Voltage limiter and single-ended to differential converter using sameUS5374903 *Apr 22, 1988Dec 20, 1994Hughes Aircraft CompanyGeneration of wideband linear frequency modulation signalsUS5434569 *Sep 1, 1993Jul 18, 1995Texas Instruments IncorporatedMethods for adjusting the coupling capacitor of a multi-stage weighted capacitor A/D converterUS5451910 *Aug 12, 1993Sep 19, 1995Northrop Grumman CorporationFrequency synthesizer with comb spectrum mixer and fractional comb frequency offsetUS5465414 *Jun 27, 1994Nov 7, 1995Hewlett-Packard CompanyAutomatic determination of the presence of a microwave signal and whether the signal is CW or pulsedUS5537459 *Jun 17, 1994Jul 16, 1996Price; Evelyn C.Multilevel cellular communication system for hospitalsUS5559473 *Jun 23, 1994Sep 24, 1996At&T Global Information Solutions CompanyMulti-range voltage controlled oscillatorUS5600283 *Sep 13, 1995Feb 4, 1997National Semiconductor CorporationDC isolated differential oscillator having floating capacitorUS5614864 *Sep 29, 1995Mar 25, 1997Rockwell Science Center, Inc.Single-ended to differential converter with relaxed common-mode input requirementsUS5631606 *Aug 1, 1995May 20, 1997Information Storage Devices, Inc.Fully differential output CMOS power amplifierUS5636213 *Dec 28, 1994Jun 3, 1997MotorolaMethod, transceiver, and system for providing wireless communication compatible with 10BASE-T EthernetUS5654708 *Apr 13, 1994Aug 5, 1997Robert Bosch GmbhProcess for compensating component tolerances in analog-digital convertersUS5703525 *Oct 9, 1996Dec 30, 1997Texas Instruments IncorporatedLow cost system for FSK demodulationUS5715529 *May 18, 1993Feb 3, 1998U.S. Philips CorporationFM receiver including a phase-quadrature polyphase if filterUS5724001 *Dec 2, 1996Mar 3, 1998Motorola, Inc.Method and apparatus for demodulating a frequency shift keyed signalUS5787123Oct 25, 1996Jul 28, 1998Sony CorporationReceiver for orthogonal frequency division multiplexed signalsUS5793359Aug 5, 1996Aug 11, 1998Mitsumi Electric Co., Ltd.System for RF communication between a computer and a remote wireless data input deviceUS5805017Nov 13, 1996Sep 8, 1998U.S. Philips CorporationBaseband demodulation of M-ary frequency shift keyed signals and a receiver thereforUS5808509May 7, 1997Sep 15, 1998U.S. Philips CorporationReceiver and demodulator for phase or frequency modulated signalsUS5818830Dec 29, 1995Oct 6, 1998Lsi Logic CorporationMethod and apparatus for increasing the effective bandwidth of a digital wireless networkUS5872810Jan 26, 1996Feb 16, 1999Imec Co.Programmable modem apparatus for transmitting and receiving digital data, design method and use method for said modemUS5881376Dec 15, 1995Mar 9, 1999Telefonaktiebolaget Lm EricssonDigital calibration of a transceiverUS5892409Jul 28, 1997Apr 6, 1999International Business Machines CorporationCMOS process compensation circuitUS5896063Apr 30, 1997Apr 20, 1999Maxim Integrated Products, Inc.Variable gain amplifier with improved linearity and bandwidthUS5905398Apr 8, 1997May 18, 1999Burr-Brown CorporationCapacitor array having user-adjustable, manufacturer-trimmable capacitance and methodUS5909463Nov 4, 1996Jun 1, 1999Motorola, Inc.Single-chip software configurable transceiver for asymmetric communication systemUS5930686Feb 19, 1997Jul 27, 1999Marconi Electronic Systems LimitedIntegrated transceiver circuit packaged componentUS5940456Jun 20, 1996Aug 17, 1999Ut Starcom, Inc.Synchronous plesiochronous digital hierarchy transmission systemsUS5949285Jun 5, 1997Sep 7, 1999Nec CorporationGain-variable amplifier having small DC output deviation and small distortionUS5949286Sep 26, 1997Sep 7, 1999Ericsson Inc.Linear high frequency variable gain amplifierUS5953640Apr 30, 1997Sep 14, 1999Motorola, Inc.Configuration single chip receiver integrated circuit architectureUS6049251Mar 30, 1998Apr 11, 2000Maxim Integrated Products, Inc.Wide-dynamic-range variable-gain amplifierUS6049702Dec 4, 1997Apr 11, 2000Rockwell Science Center, LlcIntegrated passive transceiver sectionUS6072994Aug 31, 1995Jun 6, 2000Northrop Grumman CorporationDigitally programmable multifunction radio system architectureUS6100759Feb 22, 1999Aug 8, 2000Stmicroelectronics S.R.L.Low noise, integrated AC differential amplifierUS6118811Jul 31, 1997Sep 12, 2000Raytheon CompanySelf-calibrating, self-correcting transceivers and methodsUS6118984Apr 8, 1997Sep 12, 2000Acer Peripherals, Inc.Dual conversion radio frequency transceiverUS6134453Sep 9, 1998Oct 17, 2000Charles M. Leedom, Jr.Adaptive omni-modal radio apparatus and methodsUS6175279Mar 4, 1998Jan 16, 2001Qualcomm IncorporatedAmplifier with adjustable bias currentUS6185418Nov 7, 1997Feb 6, 2001Lucent Technologies Inc.Adaptive digital radio communication systemUS6218909Oct 23, 1998Apr 17, 2001Texas Insturments Israel Ltd.Multiple frequency band voltage controlled oscillatorUS6327463 *May 29, 1998Dec 4, 2001Silicon Laboratories, Inc.Method and apparatus for generating a variable capacitance for synthesizing high-frequency signals for wireless communicationsUS6343207Nov 3, 1998Jan 29, 2002Harris CorporationField programmable radio frequency communications equipment including a configurable if circuit, and method thereforUS6366622May 4, 1999Apr 2, 2002Silicon Wave, Inc.Apparatus and method for wireless communicationsUS6377608Sep 30, 1998Apr 23, 2002Intersil Americas Inc.Pulsed beacon-based interference reduction mechanism for wireless communication networksUS6526034Sep 21, 1999Feb 25, 2003Tantivy Communications, Inc.Dual mode subscriber unit for short range, high rate and long range, lower rate data communicationsUS6714776Sep 28, 1999Mar 30, 2004Microtune (Texas), L.P.System and method for an image rejecting single conversion tuner with phase error correctionUS6738601Oct 18, 2000May 18, 2004Broadcom CorporationAdaptive radio transceiver with floating MOSFET capacitorsUS6968167 *Oct 19, 2000Nov 22, 2005Broadcom CorporationAdaptive radio transceiver with calibrationUS7139540 *Apr 15, 2005Nov 21, 2006Broadcom CorporationAdaptive radio transceiver with calibrationEP0803997A2Apr 22, 1997Oct 29, 1997Nokia Mobile Phones Ltd.A method and arrangement for producing a clock frequency in a radio device* Cited by examinerNon-Patent CitationsReference1Durham, A.M., "Circuit Architectures for High Linearity Monolithic Continuous-Time Filtering," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal-Processing, vol. 39, No. 9, pp. 651-657, Sep. 1992.2Rofougaran, Ahmadreza, "A Single-Chip Spread-Spectrum Wireless Transceiver in CMOS," Final Report, Integrated Circuits & Systems Laboratory Electrical Engineering Department, University of California, Los Angeles, CA, 1999, 339 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8248176 *Dec 8, 2010Aug 21, 2012Mitsumi Electric Co., Ltd.Current source circuit and delay circuit and oscillating circuit using the sameUS8384485 *Apr 29, 2011Feb 26, 2013Smsc Holdings S.A.R.L.Reducing spurs in injection-locked oscillatorsUS8729907Apr 5, 2012May 20, 2014Novatek Microelectronics Corp.Resistance-capacitance calibration circuit without current mismatch and method thereofUS20110156822 *Dec 8, 2010Jun 30, 2011Mitsumi Electric Co., Ltd.Current source circuit and delay circuit and oscillating circuit using the sameUS20120274370 *Apr 29, 2011Nov 1, 2012Smsc Holdings S.A.R.L.Reducing Spurs in Injection-Locked Oscillators* Cited by examinerClassifications U.S. Classification455/20, 327/111, 455/323, 327/337, 327/101, 455/333International ClassificationH04B7/14, H03H21/00, H03H11/12Cooperative ClassificationH03H2011/0494, H03H21/0012, H04B17/104, H04B17/19, H03H11/1291, H04B1/40, H03H21/0001, H04B17/14, H04B1/30, H03J2200/10, H03B21/01European ClassificationH04B1/40, H04B17/00A1T, H03B21/01, H04B17/00A2S, H03H11/12F, H04B17/00A3S, H03H21/00A, H03H21/00B, H04B1/30RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services