Source: http://www.patentsencyclopedia.com/app/20120120739
Timestamp: 2018-03-17 07:23:52
Document Index: 161755438

Matched Legal Cases: ['art 90', 'arts 90', 'arts 90', 'art 90', 'art 90', 'art 90', 'art 90', 'art 90', 'art 112', 'art 112', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 94', 'arts 94', 'arts 94', 'art 94', 'art 94', 'art 94', 'art 94', 'art 94', 'art 94', 'arts 94', 'arts 94', 'art 94', 'art 94', 'art 94', 'art 94', 'art 94', 'arts 94', 'art 90', 'art 90', 'arts 94', 'art 90', 'arts 94']

Inventors: Shinya Fujioka (Yokohama-Shi, JP) Shinya Fujioka (Yokohama-Shi, JP) Tomohiro Kawakubo (Yokohama-Shi, JP) Tomohiro Kawakubo (Yokohama-Shi, JP) Koichi Nishimura (Yokohama-Shi, JP) Koichi Nishimura (Yokohama-Shi, JP) Kotoku Sato (Yokohama-Shi, JP) Kotoku Sato (Yokohama-Shi, JP)
Patent application number: 20120120739
7. A semiconductor device comprising: a memory core with a plurality of memory cells: an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line; and a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein the internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and wherein the internal voltage generator includes a detector and a booster circuit.
8. The semiconductor device according to claim 7, wherein the detector compares the boosted internal voltage with a reference voltage and outputs a comparison signal, and the booster circuit, coupled to the detector, does pumping operation in response to the comparison signal to generate the boosted internal voltage.
9. The semiconductor device according to claim 8, further comprising: a divider circuit that divides the boosted internal voltage to generate a divided voltage, wherein the divided voltage is supplied to the detector.
10. The semiconductor device according to claim 7, wherein the detector includes a circuit, coupled to the low power entry circuit, whose operation is stopped in response to the low power signal.
11. The semiconductor device according to claim 7, wherein the booster circuit includes a plurality of booster units that are inactivated in response to the low power signal.
12. The semiconductor device according to claim 7, wherein the external voltage is supplied to the internal power supply line in the low power consumption mode.
13. A semiconductor device comprising: a memory core with a plurality of memory cells; an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line; and a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein the internal voltage generator includes a plurality of booster circuits coupled to the low power entry circuit, and a detector, and wherein at least one of the plurality of booster circuits is inactivated in response to the low power signal.
14. The semiconductor device according to claim 13, wherein the detector compares the boosted internal voltage with a reference voltage and outputs a comparison signal, and the plurality of booster circuits, coupled to the detector, do pumping operations in response to the comparison signal to generate the boosted internal voltage.
15. The semiconductor device according to claim 14, further comprising: a divider circuit that divides the boosted internal voltage to generate a divided voltage, wherein the divided voltage is supplied to the detector.
16. A semiconductor device comprising: a memory core with a plurality of memory cells; an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line; and a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein a voltage, which is lower than the boosted internal voltage, is supplied to the internal power supply line in the low power consumption mode, and wherein the internal voltage generator includes a detector and a booster circuit.
17. The semiconductor device according to claim 16, wherein the external voltage is supplied to the internal supply line as the voltage.
18. A semiconductor device comprising: a memory core including a plurality of memory cells; an internal voltage generator, coupled to the memory core via an internal power supply line, that generates an internal voltage based on an external voltage and supplies the internal voltage to the memory core via the internal power supply line; and a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and wherein the internal voltage generator includes a comparator, a divider circuit and a regulator.
19. The semiconductor device according to claim 18, wherein the divider circuit generates a divided voltage, the comparator compares the divided voltage with a reference voltage and supplies a comparison voltage to the regulator, and the regulator outputs the internal voltage in response to the comparison voltage and wherein the divider circuit divides the comparison voltage to generate the divided voltage.
20. The semiconductor device according to claim 18, wherein the internal power supply line is disconnected from the regulator based on the low power signal.
21. The semiconductor device according to claim 18, wherein the external voltage is supplied to the internal power supply line in the low power consumption mode.
22. A semiconductor device provided on a substrate comprising: an internal voltage generator that generates an internal voltage based on an external voltage and supplies the internal voltage to the substrate via an internal power supply line; and a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and wherein the internal voltage generator includes an oscillator and a pumping circuit.
23. The semiconductor device according to claim 22, further comprising: a detector that detects a level of the internal voltage and outputs a detected signal; and wherein the oscillator, coupled to the detector, generates a clock signal in response to the detected signal, and the pumping circuit, coupled to the oscillator, does pumping operation in response to the clock signal.
24. The semiconductor device according to claim 23, wherein the detector includes a circuit, coupled to the low power entry circuit, whose operation is stopped in response to the low power signal.
25. The semiconductor device according to claim 23, wherein the internal voltage generator comprises at least one of a plurality of units which are inactivated in response to the low power signal.
26. The semiconductor device according to claim 22, wherein the external voltage is supplied to the internal power supply line in the low power consumption mode.
27. A semiconductor device comprising: a bit line coupled to a memory cell; an internal voltage generator that generates a precharge voltage based on an external voltage and supplies the precharge voltage to the bit line; and a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein the internal voltage generator, stops supplying the precharge voltage to the bit line in response to the low power signal while the external voltage is supplied to the semiconductor device, and wherein the internal voltage generator includes a comparator.
28. The semiconductor device according to claim 27, wherein the comparator, compares the precharge voltage with a reference voltage to output the precharge voltage.
29. The semiconductor device according to claim 27, wherein the external voltage is supplied to the bit line in the low power consumption mode.
30. The semiconductor device according to claim 27, wherein the comparator includes a first comparator unit and a second comparator unit, the first comparator unit compares the precharge voltage with a first reference voltage, the second comparator unit compares the precharge voltage with a second reference voltage, and the first and second comparator units generate the precharge voltage supplied to the bit line.
31. A semiconductor device comprising: a bit line coupled to a memory cell; an internal voltage generator that generates a precharge voltage based on an external voltage and supplies the precharge voltage to the bit line; and a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein the internal voltage generator, coupled to the low power entry circuit, stops supplying the precharge voltage to the bit line in response to the low power signal while the external voltage is supplied to the semiconductor device, and wherein the internal voltage generator includes a first comparator unit comparing the precharge voltage with a first reference voltage to output a first comparison signal, a second comparator unit comparing the precharge voltage with a second reference voltage to output a second comparison signal, and a driver circuit, and wherein the driver circuit includes a first driver unit operating responsive to the first comparison signal, and a second driver unit operating responsive to the second comparison signal, and wherein the precharge voltage is supplied from a common output node of the first and second driver units to the bit line.
[0037] According to another aspect of the semiconductor memory device in the present invention, after the low power consumption mode is exited, a reset signal for nitializing an internal circuit is activated during a period where a boost voltage internally generated is lower than a predetermined voltage. For example, the reset signal is activated during a period where the boost voltage is lower than the power supply voltage. In addition, the reset signal can be activated during a period where the boost voltage is lower than a reference voltage generated by stepping down the power supply voltage.
[0102] The DRAM is supplied with a power supply voltage VDD (e.g., 2.5 V) from the exterior, a ground voltage VSS, chip enable signals /CE1 and CE2 as the control signals, a plurality of address signal AD, a plurality of data input/output signals DQ, and another control signal CN. This DRAM does not adopt the address multiplex method. Therefore, the address signals AD is supplied once at each read operation and at each write operation. The power supply voltage VDD and the ground voltage VSS are supplied to almost all the circuits excepting a partial circuit of the memory core 38. Here, the signals headed by the letter "/" are those of negative logic. The "address signals AD" may be abbreviated into the "AD signals" in the following description by omitting its signal name.
[0113] The substrate voltage generator 34 receives the reference voltage VRFV and generates a substrate voltage VBB (e.g., -1.0 V) to be fed to the substrate and the p-wells of the memory cells.
[0116] The booster 28 is composed of resistors R1 and R2 connected in series, a differential amplifier 28a, a pumping circuit 28b, an nMOS 28c, and a switching circuit 28d for controlling the gate of the nMOS 28c. The resistor R1 is supplied at its one end with the boost voltage VPP, and the resistor R2 is supplied at its one end with the ground voltage VSS through the nMOS 28c. A divided voltage V1 is generated from the connection node of the resistors R1 and R2. The nMOS 28c receives the power supply voltage VDD from the switching circuit 28d during the low power consumption mode. The differential amplifier 28a is formed of a MOS differential amplifier using a current mirror circuit, for example, as the current source. The differential amplifier 28a outputs a high level when the voltage V1 is lower than the reference voltage VPREF. The pumping circuit 28b receives the high level from the differential amplifier 28a and starts a pumping operation. By this pumping operation, the voltage VPP is raised, and the voltage V1 is raised. When this voltage V1 coincides with the reference voltage VPREF (i.e., 1.5 V), the output of the differential amplifier 28a reaches the low level so that the pumping operation stops. By repeating these operations, the boost voltage VPP is retained at a constant voltage.
[0117] The precharging voltage generator 30 is composed of two differential amplifiers 30a and 30b connected at their outputs with each other. The differential amplifier 30a is supplied with the reference potential VPRREFL and the precharging voltage VPR. The differential amplifier 30b is supplied with the reference potential VPRREFL and the precharging voltage VPR. Moreover, these differential amplifiers 30a and 30b generate the precharging voltage VPR at an intermediate value between the reference voltages VPRREFL and VPRREFH.
[0118] FIG. 5 shows the details of the internal supply voltage generator 32 and the substrate voltage generator 34. The internal supply voltage generator 32 is composed of a negative feedback type differential amplifier 32a, a compensating circuit 32b, a regulator 32c made of an nMOS, an nMOS 32d, and a switching circuit 32e for controlling the gate of the nMOS. The differential amplifier 32a receives the reference voltage VRFV and a voltage V2 generated by the compensating circuit 32b, and supplies a predetermined voltage to a node VG. In the compensating circuit 32b, an nMOS and resistors R3 and R4 in a diode connection are arranged in series between the node VG and the ground line VSS. The voltage V2 is generated at the connection node between the resistors R3 and R4. The regulator 32c is connected at its gate with the node VG, receives the power supply voltage VDD at its drain and generates the internal supply voltage VII at its source.
[0119] The nMOS 32d is grounded at its source and connected at its drain with the node VG. The switching circuit 32e supplies the power supply voltage VDD to a gate of the nMOS 32d during the lower power consumption mode. The nMOS 32d receives the power supply voltage VDD from the switching circuit 32e during the low power consumption mode, and fixes the node VG at the ground level.
[0120] In this internal supply voltage generator 32, when the threshold voltage of the regulator 32c is lowered due to the rise in the ambient temperature, for example, the threshold voltage of the nMOS of the compensating circuit 32b also drops, so that the voltage V2 rises. In response to the rise in the voltage V2, the differential amplifier 32a lowers the voltage of the node VG. Moreover, the source-to-drain current of the nMOS 32c is made constant so that the internal supply voltage VII is made constant.
[0121] The substrate voltage generator 34 is composed of an oscillator 34a and a pumping circuit 34b. In response to the high level of a control signal VBBEN, the oscillator 34a starts the oscillating operation to output an oscillating signal OSC. The pumping circuit 34b has a capacitor for repeating charge and discharge in response to the oscillating signal OSC from the oscillator 34a, and a diode-connected nMOS transistor connected with one end of the capacitor. The charges of a p-type substrate connected with the anode are discharged by the pumping operation, which lowers the substrate voltage VBB. Making the substrate voltage VBB negative leads to gaining some effects such as reducing the influences of a shift in the threshold voltage of the memory cells due to the substrate effect so that the characteristics of the memory cells may be improved.
[0123] The memory core 38 has a memory cell MC, nMOS switches 42a and 42b, a precharging circuit 44 and a sense amplifier 46.
[0125] The nMOS switches 42a and 42b control the connection between a bit line BL (or /BL) on the side of the memory cell MC and a bit line BL (or /BL) on the side of a sense amplifier SA. The nMOS switches 42a and 42b receive a control signal BT at their gates.
[0126] The precharging circuit 44 is composed of three nMOSes 44a, 44b and 44c. The nMOS 44a is connected at its source and drain, respectively, with the bit lines BL and /BL. The nMOSes 44b and 44c are connected at one of their sources and drains, respectively, with the bit lines BL and /BL, and are supplied at their others with the precharging voltage VPR. The nMOSes 44a and 44b and 44c receive a bit line control signal BRS at their gates.
[0129] First of all, when the power supply is switched on, the power supply voltage VDD rises gradually (FIG. 7(a)). The VDD starter 12 shown in FIG. 3 inactivates the start signal STTCRX (to the low level) till the power supply voltage VDD reaches a predetermined voltage (FIG. 7(b)). By this control, it is possible to prevent the ULP signal from being activated due to the malfunctioning of the low power entry circuit 14 when the power supply is switched on. An exterior controller (e.g., a CPU or a memory controller) for controlling the DRAM turns the CE2 signal at the high level a predetermined time TO after the power supply voltage VDD reaches the minimum operable voltage VDDmin (FIG. 7(c)).
[0130] After this, the DRAM becomes the standby state or executes an ordinary operation. The exterior controller turns the CE2 signal to the low level when the DRAM enters the low power consumption mode (FIG. 7(d)). The low power entry circuit 14 activates the ULP signal (to the high level) in response to the fall of the CE2 signal when the STTCRX signal is at the high level (FIG. 7(e)).
[0131] In response to the high level of the ULP signal, the low-pass filter 22 of the internal voltage generator 18 stops the supply of the power supply voltage to the reference voltage generator 24 and instead supplies the ground voltage VSS from the VSS supplying circuit 36. In response to the ground voltage VSS, the reference voltage generator 24 turns the reference voltages VPREF, VPRREFL, VPRREFH and VRFV to the ground level. The nMOS 28b of the booster 28 shown in FIG. 4 and the nMOS 32d of the internal supply voltage generator 32 shown in FIG. 5 are switched off. As a result, the booster 28, the precharging voltage generator 30, the internal supply voltage generator 32 and the substrate voltage generator 34 are inactivated to stop their operations. Thus, all the conventional circuits remaining operative during the low power consumption mode are stopped. Therefore, the power consumption in the low power consumption mode is drastically reduced as compared with the conventional.
[0132] When these circuits are inactivated, the generations of the boost voltage VPP, the precharging voltage VPR, the internal supply voltage VII and the substrate voltage VBB are stopped. However, the boost voltage VPP and the internal supply voltage VII are changed into the power supply voltage VDD by the VSS supplying circuit 36, and the substrate voltage VBB and the precharging circuit VPR are changed into the ground voltage VSS by the VSS supplying circuit 36. Therefore, the internal circuit of the main circuit unit 20 is prevented from having a leak path.
[0133] The exterior controller turns the CE2 signal to the high level when the low power consumption mode is released (FIG. 7(f)). In response to the high level of the CE2 signal, the low power entry circuit 14 inactivates the ULP signal (to the low level) (FIG. 7(g)). In response to the inactivation of the ULP signal, the low-pass filter 22 supplies the power supply voltage VDD to the reference voltage generator 24. In response to the inactivation of the ULP signal, the VDD supplying circuit 26 and the VSS supplying circuit 36 stop the supplies of the power supply voltage VDD and the ground voltage VSS. Then, the booster 28, the precharging voltage generator 30, the internal supply voltage generator 32 and the substrate voltage generator 34 are activated again to start their operations.
[0140] When the cellular phone then enters the service state from the waiting state, the CPU raises the CE2 signal shown in FIG. 8 to the high level. After the DRAM entered the idle mode, the data retained in the flash memory are transferred to the DRAM (FIG. 9(a)). During the service state, the DRAM is used as the work memory. Here, the service state includes not only the state of exchanging vocal communications but also the state of transferring data.
[0141] When the service state shifts to the waiting state, those, of the data of the DRAM, necessary to be retained are saved in the flash memory (FIG. 9(b)). After this, the CPU lowers the CE2 signal to the low level and enters the DRAM to the low power consumption mode. The DRAM does not perform refresh operation in the low power consumption mode so that the unnecessary data is lost.
[0159] When the power supply is switched on, the CE2 signal is raised to the high level the predetermined time TO after the power supply voltage VDD reaches the minimum operating voltage VDDmin. This makes it possible to prevent the erroneous entry into the low power consumption mode when the power supply is switched on.
[0164] The low powder entry circuit 50 has timing adjusting circuits 54a and 54b, a level shifter 56, an RS flip-flop 58 and a combinational circuit 60.
[0165] The timing adjusting circuit 54a is formed by connecting a two-input NOR gate connected at its one input with a delay circuit 54c and a two-input NAND gate connected at its one input with the delay circuit 54c, in plurality in cascade. Each delay circuit 54c has an MOS capacity arranged between a plurality of inverters connected in cascade. The timing adjusting circuit 54a delays the falling edge of a chip enable signal CE2Z by about 100 ns and outputs it to a node ND1. The CE2Z signal is the CE2 signal which is supplied from the exterior and received at the input buffer (not shown).
[0166] The timing adjusting circuit 54b is identical to the timing adjusting circuit 54a. The timing adjusting circuit 54b delays the falling edge of the signal transmitted to a node ND3, by about 100 ns.
[0170] The timing adjusting circuit 54b activates the ULP signal (to the high level) through the inverter about 100 ns after receiving the low level of the node ND3.
[0173] A predetermined time after the power supply was switched on, the STTCRX signal turns to the high level (FIG. 13(a)). After this, the exterior controller for controlling the DRAM raises the CE2 signal to the high level (FIG. 13(b)). The timings above are identical to those of the first embodiment. In response to the high level of the CE2Z signal, the node ND1 shown in FIG. 12 turns to the high level (FIG. 13(c)).
[0174] The initial cycle is executed to turn the RASX signal to the low level (FIG. 13(d)). In response to the low level of the RASX signal, the RS flip-flop 58 raises the node ND2 to the is high level (FIG. 13(e)). After this, there are started the operations of the internal voltage generator 18 shown in FIG. 11.
[0176] The timing adjusting circuit 54a turns the node ND1 to the low level about 100 ns after receiving the low level of the CE2Z signal (FIG. 13(f)). 100 ns or more after the falling edge of the CE2Z signal, the CE1X signal is turned to the low level (FIG. 13(g)). In response to the low level of the CE1Z signal and the low level of the node ND1, the combinational circuit 60 shown in FIG. 12 turns the node ND3 to the low level (FIG. 13(h)). The timing adjusting circuit 54b raises the ULP signal to the high level (FIG. 13(i)) about 100 ns after receiving the low level of the node ND3. The DRAM enters the low power consumption mode.
[0179] When the low power consumption mode is released, the CE1X signal is first turned to the high level (FIG. 13(j)). The combinational circuit 60 receives the high level of the CE1X signal to turn the node ND3 to the high level (FIG. 13(k)) and the ULP signal to the low level (FIG. 13(l)). 200 μs after the rising edge of the CE1X signal, the CE2Z signal is turned to the high level (FIG. 13(m)). In response to the high level of the CE2Z signal, a level of the node ND1 turns to the high level. During this period of 200 μs, the internal voltage generator 18 is activated to stabilize the individual internal voltages VPP, VPR, VII and VBB at predetermined levels.
[0188] The VII starter 70 comprises a release detecting circuit 72 shown in FIG. 15 , a level detecting circuit 74, and a power-on circuit 76 shown in FIG. 16. In FIGS. 15 and 16, a logic circuit is supplied with a power supply voltage VDD except the circuit with a power supply voltage indicated.
[0189] A release detecting circuit 72 comprises a detecting circuit 72a, a level shifter 72b, and a flip-flop 72c. The detecting circuit 72a receives a low power signal ULP shown in FIG. 3 and outputs the low level of a pulse LPLS in synchronization with the falling edge of the ULP signal. The level shifter 72b converts the high level voltage (internal power supply voltage VII) of a row address strobe signal RASZ to the external power supply voltage VDD and outputs a row address strobe signal RASX1 having inverted logic. The level shifter 72b is identical to the level shifter 56 shown in FIG. 12. Receiving a low pulse from the detecting circuit 72a, the flip-flop 72c turns a release signal REL to high level, and receiving a low level (RASZ=high level) from the level shifter 72b, it turns the release signal REL to low level.
[0190] In FIG. 16, a level detecting circuit 74 comprises a differential amplifier 74a including a current mirror circuit and an inverter row 74b which includes an odd number of inverters and receives the output of the differential amplifier 74a. The differential amplifier 74a is activated during the high level of the release signal REL, compares an internal power supply voltage VII with a reference voltage VREF, and outputs the comparison result to an inverter row 74b. A generator for the internal power supply voltage VII generates a constant value of the internal power supply voltage VII independent of the fluctuation of the power supply voltage VDD supplied from the exterior. On the other hand, the reference voltage VREF varies depending on the fluctuation of the power supply voltage VDD.
[0191] The output voltage of the differential amplifier 74a goes low when the internal power supply voltage VII is lower than the reference voltage VREF. The differential amplifier 74a comprises a MOS capacitor 74c for receiving the reference voltage VREF in order to prevent its response to insignificant fluctuation of the reference voltage VREF. In addition, an nMOS 74d for receiving the reference voltage VREF is disposed on a path to a ground line VSS in order to limit the amount of current flow to the ground line VSS and reduce the power consumption during the operation of the differential amplifier 74a. The nMOS 74d operates as high-resistance. An inverter 74e in the initial stage of the inverter row 74b has an nMOS connected in serial so as to have the logic threshold of an input signal in conformity with the output of the differential amplifier 74a.
[0192] A power-on circuit 76 turns a start signal STT to high level during a predetermined period since the power supply voltage is supplied to the DRAM. An OR circuit 78, upon receiving the high level of a start signal STTPZ or the high level of the start signal STT, outputs the high level of a start signal STTVII (reset signal). The start signal STTVII, similarly to that of FIG. 3, is supplied to the main circuit unit 20 and initializes a predetermined internal circuit.
[0194] Firstly, when the CE2 signal (not shown) is turned to low level, the DRAM enters the low power consumption mode by a low power entry circuit 14 shown in FIG. 3 and a generator for the internal power supply voltage VII terminates its operation. The internal power supply voltage VII (for example, 2.0V in a normal operation) becomes equal to the power supply voltage VDD (for example, 2.5V) (FIG. 17(a)) and an ULP signal turns to high level (FIG. 17(b)).
[0195] Subsequently, the CE2 signal being turned to high level, the DRAM is released from the low power consumption mode and the ULP signal turns to low level (FIG. 17(c)). In other words, the DRAM is released from the low power consumption mode in accordance with the level of the CE2 signal received during the low power consumption mode. The exit from the low power consumption mode is controlled by the low power entry circuit 14 shown in FIG. 3.
[0196] Receiving the falling edge of the ULP signal, the detecting circuit 72a in FIG. 15 turns an LPLS signal to low level (pulse) (FIG. 17(d)). Receiving the low level of the LPLS signal, the flip-flop 72c in FIG. 15 turns the REL signal to high level (FIG. 17 (e)).
[0197] Due to the exit from the low power consumption mode, a power supply line of the internal power supply voltage VII and that of the power supply voltage VDD are disconnected and simultaneously the generator for the internal power supply voltage VII initiates its operation. The internal power supply voltage VII goes low for some time from the initiation of the generator (FIG. 17(f)). The differential amplifier 74a in FIG. 16 outputs low level to the inverter row 74b when the internal power supply voltage VII is lower than the reference voltage VREF (for example, 1.25V). The inverter row 74b, upon receiving the low level of the differential amplifier 74a, outputs the high level of the STTPZ signal (FIG. 17(g)). The OR circuit 78, upon receiving the high level of the STTPZ signal, turns a start signal STTVII to high level. The start signal STTVII functions as a reset signal and a predetermined internal circuit of the main circuit unit 20 shown in FIG. 3 is initialized.
[0198] After the exit from the low power consumption mode, by issuing an operation command to the DRAM, the RASZ signal is turned to high level (FIG. 17(h)) and the REL signal to low level (FIG. 17(i)). The differential amplifier 74a is inactivated due to the low level of the REL signal.
[0202] One control signal (CE2 signal)enables the entry of a chip to the low power consumption mode and the exit of a chip from the low power consumption mode.
[0205] The level detecting circuit 80 comprises: a differential amplifier 80 for comparing the internal power supply voltage VII with the reference voltage VREF; an inverter row 80b including an even number of inverters; a differential amplifier 80c for comparing a boost voltage VPP of a word line (not shown) with the power supply voltage VDD from the exterior; an inverter row 80d including an even number of inverters; and an NAND gate 80e. The boost voltage VPP generated by a booster is formed inside of the chip. The differential amplifiers 80a and 80c are identical to the differential amplifier 74a in FIG. 16 and are activated upon receipt of the high level of the REL signal. The inverter rows 80b and 80d are constructed of the inverter in the initial stage and the inverter in the second stage of the inverter row 74b in FIG. 16. The inverter row 80b receives the output of the differential amplifier 80a and outputs the received logic level to a NAND gate 80e as a start signal STT1X. The inverter row 80d receives the output of the differential amplifier 80c and outputs the received logic level to the NAND gate 80e as a start signal STT2X. The NAND gate 80e operates as an OR circuit of negative logic and outputs a start signal STTPZ.
[0207] Firstly, when the CE2 signal(not shown) is turned to low level, the DRAM enters the low power consumption mode and a generator for the internal power supply voltage VII and a generator for the boost voltage VPP terminate their operation. The internal power supply voltage VII (for example, 2.0V in the normal operation) and the boost voltage VPP (for example, 3.7V in the normal operation) become equal to the power supply voltage VDD (for example, 2.5V) (FIG. 19(a)) and an ULP signal turns to high level (FIG. 18(b)).
[0208] Subsequently, the CE2 signal being turned to high level, the DRAM is released from the low power consumption mode and the ULP signal turns to low level (FIG. 19(c)). The LPLS signal is turned to low level (pulse) as well as in FIG. 17 (FIG. 19(d)) and the REL signal is turned to high level (FIG. 19(e)).
[0209] Due to the exit from the low power consumption mode, the power supply line of the internal power supply voltage VII and the power supply line of the power supply voltage VDD are disconnected and the generator for the internal power supply voltage VII initiates its operation. The internal power supply voltage VII goes low for some time from the initiation of the generator (FIG. 19(f)). The low level of the STT1X signal is output during a period where the internal power supply voltage VII is lower than the reference voltage VREF (for example, 1.25V) (FIG. 19(g)). Similarly, the connection between the power supply line of the boost voltage VPP and that of the power supply voltage VDD is disconnected and the generator for the boost voltage VPP initiates its operation. The boost voltage VPP goes low for some time from the initiation of the generator (FIG. 19(h)). The low level of the STT2X signal is output during a period where the boost voltage VPP is lower than the power supply voltage VDD (FIG. 19(i)).
[0210] The NAND gate 80e in FIG. 18 outputs the high level of the STTPZ signal during a period where the STT1X signal or the STT2X signal is at low level (FIG. 19(j)). During the high level of the STTPZ signal, the start signal STTVII (FIG. 16) is turned to high level. The start signal STTVII functions as a reset signal and initializes a predetermined internal circuit of the main circuit unit 20 shown in FIG. 3.
[0211] After the exit from the low power consumption mode, the DRAM initiates its operation, thereby the RASZ signal being turned to high level (FIG. 19(k)) and the REL signal to low level (FIG. 19(l)) as well as in FIG. 17. The differential amplifier 80a and 80c are inactivated due to the low level of the REL signal.
[0215] The start signal generator 82 are constructed of a CMOS inverter 82a for receiving a CE2X signal (internal signal) which is an inverted CE2 signal, a MOS capacitor 82b connected with the output of the CMOS inverter 82a, and a differential amplifier 82c for receiving the input of the CMOS inverter 82a and the reference voltage VREF. The differential amplifier 82c comprising a current mirror circuit, turns a start signal STTPZ to high level when the voltage of a node ND4 is lower than the reference voltage VREF.
[0216] The pMOS of the CMOS inverter 82a has a long channel length to have high on-resistance. A CR time constant circuit is constructed of the pMOS of the CMOS inverter 82a and the MOS capacitor 82b. Utilizing the on-resistance of a transistor to construct the CR time constant circuit allows the layout to be reduced in size than the case of utilizing diffused resistance.
[0218] Firstly, when the CE2 signal (not shown) is turned to low level, the CE2X signal is turned to high level and the DRAM enters the low power consumption mode. A generator for the internal power supply voltage VII and a generator for the boost voltage VPP terminate their operation. The CMOS inverter 82a in FIG. 20 upon receiving the high level of the CE2X signal, turns the nMOS on and a node ND4 to low level (FIG. 21(a)). The differential amplifier 82c turns a STTPZ signal to high level when the voltage of the node ND4 is lower than the reference voltage VREF (FIG. 21(b)).
[0219] Subsequently, the CE2 signal being turned to high level and the CE2X signal to low level, the DRAM is released from the low power consumption mode (FIG. 21(c)). The CMOS inverter 82 in FIG. 20 upon receiving the low level of the CE2X signal, turns the pMOS on and the node ND4 to high level (FIG. 21 (d)). At this time the voltage of the node ND4 gradually rises in accordance with the time constant determined by the on-resistance of the pMOS and the CMOS capacitor. The differential amplifier 82c turns the STTPZ signal to low level when the voltage of the node ND4 is higher than the reference voltage VREF (FIG. 21(e)).
[0220] Consequently, the STTPZ signal(reset signal) is activated (high level) and the internal circuit is initialized during a period T2 from the exit from the low power consumption mode. The period T2 is set after the exit from the low power consumption mode in correspondence with a period where the internal power supply voltage VII is lower than a predetermined voltage so that the operation of the internal circuit supplied with the internal power supply voltage VII can not be ensured. In other words, the start signal generator 82 operates as a timer for determining the length of the period T2.
[0227] The reference voltage generator 24 is provided with a reference voltage generator 24a for generating a reference voltage VREF, a starter 24b consisting of pMOS, a differential amplifier 24c, and a regulator 24d.
[0228] The reference voltage generator 24a has a current mirror circuit made of a pMOS, two nMOSes connected individually in series with the current mirror circuit, and a register connected between the source of one of the nMOSes and the ground line VSS. The output of the reference voltage generator 24a is connected with the gate of one nMOS and the drain of the other nMOS, from which the reference voltage VREF is generated. The gate of the other nMOS is connected with the source of the one nMOS.
[0229] The starter 24b raises the reference voltage VREF to the high level while the start signal STTCRX is activated after the power-on.
[0230] The differential amplifier 24c has a current mirror part made of pMOSes, a differential input part made of nMOSes and an nMOS supplying the gate with reference voltage and connecting the differential input part with the ground line VSS. The one nMOS of the differential input part is supplied at its gate with the reference voltage VREF, and the other nMOS is supplied at its gate with the reference voltage VRFV.
[0231] The regulator 24d is constructed by connecting a pMOS and five resistors in series between the power supply line VDD and the ground line VSS. From the connection nodes of the individual elements, there are individually outputted reference voltages VRFV, VPREF, VPRREFL and VPRREFH. With the two terminals of the resistor connected with the ground line VSS, there are connected the source and drain of the nMOS which is controlled by a low power signal NAPX. The resistor, as connected with the ground line VSS, is bypassed when the low power signal NAPX is activated (to a low level). During the low power consumption mode, therefore, the levels (absolute values) of the reference voltages VRFV, VPREF, VPRREFL, and VPRREFH vary, thereby lowering the voltages, compared with the normal operation mode.
[0233] This internal supply voltage generator 96 is constructed by eliminating the switch circuit 32e and the nMOS 32d from the VII internal supply voltage generator 32 of the first embodiment shown in FIG. 5 and by adding a stabilized capacitor 96a, a switch 96b, and an nMOS 96c. The stabilized capacitor 96a stores a portion of the electric charge supplied to the internal power supply line VII to reduce the shift of the power supply voltage VII, as might otherwise be caused by the power supply noise. The switch 96b is formed of a CMOS transmission gate, for example. The nMOS 96c, as arranged between the internal power supply line VII and the ground line VSS, is supplied at its gate with the inverted logic of the low power signal NAPX through an inverter.
[0234] The switch 96b is turned off, when the low power signal NAPX is activated, to disconnect the regulator 32c and the internal circuit. At this time, the nMOS 96c is turned off so that the internal power supply line VII drops to the ground voltage (0 V). The power supply voltage VII is not supplied to the internal circuit so that the leakage current of the transistor or the like in the internal circuit does not occur during the power consumption mode. Specifically, the power consumption of the internal circuit can be lowered to zero. At this time, the connection between the regulator 32c and the stabilized capacitor 96a is kept so that the stabilized capacitor 96a stores the electric charge as in the normal operation.
[0235] After the low consumption mode is released, the switch 96b is turned on when the low power signal NAPX is inactivated. Simultaneously with this, the nMOS 96c is turned off to connect the regulator 32c and the internal circuit. At this time, not only the electric charge supplied from the regulator 32c but also the electric charge stored in the stabilized capacitor 96a is supplied to the internal power supply line VII so that this internal power supply voltage VII is raised and supplied to the internal circuit. As a result, this internal circuit can be operated immediately after the low power consumption mode is released.
[0240] This unit 108 has four capacitors 108a, 108b, 108c and 108d each made of an nMOS, and pMOSes 108e and 108f to operate as switches. The capacitors 108a, 108b, 108c and 108d receive the inverted logics of pulse signals PLS1, PLS2, PLS3 and PLS4, respectively, at their one-side terminals when the low power signal NAPX is inactivated. The other terminals of the capacitors 108a-108d are connected with the power supply line VDD through a plurality of diode-connected nMOSes. The gates of the pMOSes 108e and 108f receive pulse signals PLS5 and PLS6, respectively, at their gates through the logic gates when the low power signal NAPPX is inactivated.
[0241] The pulse signals PLS1, PLS2 and PLS5 and the pulse signals PLS3, PLS4 and PLS6 are in opposite phases to each other. The high-level voltages of the low power signal NAPX and the pulse signals PLS5 and PLS6 are so equalized to the boost voltage VPP as to turn off the pMOSes 108e and 108f reliably.
[0242] The capacitors 108a and 108b, and 108c and 108d are alternately charged and discharged in response to the pulse signals PLS1, PLS2, PLS3 and PLS4 inputted. The pMOSes 108e and 108f are alternately turned on in synchronization with the pumping operations of the capacitors 108a and 108b, and the capacitors 108c and 108d. By these pumping operations, moreover, the power supply voltage VDD is boosted to the boost voltage VPP. The unit 108 stops its operation when the low power signal NAPX is activated.
[0246] This VPP detector 90 is provided with a differential amplifier 90a and a voltage generator 90b for supplying its voltage to one input of the differential amplifier 90a.
[0247] This differential amplifier 90a has a current mirror part 90c composed of pMOSes, and a pair of differential input parts 90d and 90e composed of nMOSes. Both the inputs of the differential input parts 90d and 90e receive the reference voltage VPREF and a control voltage VPP2 which is generated by shifting the level of the boost voltage VPP from the voltage generator 90b. The differential input part 90d is connected with the ground line VSS through the nMOS which is always on, and the differential input part 90e is connected with the ground line VSS through the nMOS which is turned on when the low power signal NAPX is inactivated.
[0248] In short, the differential input part 90d operates at all times, and the differential input part 90e operates only when the low power signal NAPX is inactivated. During the low power consumption mode, the differential input part 90e stops its operation so that the power consumption is reduced. The differential amplifier 90a activates the boost enable signal (to the high level) when the control voltage VPP2 is lower than the reference voltage VPREF.
[0249] The voltage generator 90b is constructed by connecting three resistors in series between the node for generating the boost voltage VPP and the ground line VSS. The control voltage VPP2 is outputted from the other terminal of the resistor on the side of the node for supplying the boost voltage VPP. With the two terminals of the resistor connected with the ground line VSS, there are individually connected the source and the drain of the nMOS which is controlled with the low power signal NAPX. The resistor connected with the ground line VSS is bypassed when the low power signal NAPX is activated. During the low power consumption mode, therefore, the level of the control voltage VPP2 drops.
[0251] This unit 112 is provided with an oscillator 112a and a pumping circuit 112b.
[0252] The oscillator 112a is constructed as a ring oscillator composed of odd stages of logic gates. The oscillator 112a operates when the substrate voltage detection signal VBBDET is activated but when the low power signal NAPX is inactivated.
[0253] The pumping circuit 112b includes a voltage supplying part 112c having three pMOSes and one nMOS connected in series between the power supply line VDD and the pumping node PND, a capacitor 112d composed of a pMOS connected at its gate with the pumping node PND, an nMOS 112e for connecting the pumping node PND and the ground line VSS when the pumping node PND is at the high level, and a diode-connected nMOS 112f for connecting the pumping node PND and the substrate node VBB.
[0254] In the pumping circuit 112b, the pumping node PND interchangeably has the ground voltage and a negative voltage when the pMOSes and nMOS of the voltage supplying part 112c and the capacitor 112d receive the clock signal from the oscillator 112a. When the pumping node PND has a negative voltage, moreover, the electric charge of the substrate node VBB is pumped out to set the substrate node VBB to a negative voltage. The unit 112 stops its operation during the power consumption mode (while the low power signal NAPX is active).
[0256] This unit 114 is provided with an oscillator 114a and a pumping circuit 114b.
[0257] The oscillator 114a is a circuit which is made by eliminating the logic of the low power signal NAPX from the oscillator 112a of the unit 112. In short, the oscillator 114a operates in response to the substrate voltage detection signal VBBDET even during the power consumption mode to generate the substrate voltage VBB. The pumping circuit 114b is a circuit identical to the pumping circuit 112b of the unit 112.
[0259] This VBB detector 98 is provided with two detection units 98a and 98b, and an OR circuit 98c for outputting the OR logic of the detection results of those units 98a and 98b as the substrate voltage detection signal VBBDET.
[0260] The detection unit 98a includes: a reference voltage generating part 98d having a resistor; a pMOS and a resistor connected in series between the internal power supply line VII and the ground line VSS; a level detecting part 98e having two nMOSes connected in series; a CMOS inverter 98f having a pMOS connected with the power supply line VII through a pMOS load circuit; and an nMOS 98g for connecting the output node NOUT1 of the level detecting part 98f with the ground line VSS. The gate of the pMOS of the reference voltage generating part 98d and the gate of the nMOS 98g receive the low power signal NAPX. Therefore, the detection unit 98a is inactivated in the normal operation mode but is activated during the power consumption mode. The voltage of the output node NOUT1 of the level detecting part 98e rises, when activated, with the rise of the substrate voltage VBB. In this embodiment, the CMOS inverter 98f outputs the low level in response to the detection result (i.e., the voltage of the output node NOUT1) at the level detecting part 98d when the substrate voltage VBB is boosted to -0.5 V. The OR circuit 98c activates the substrate voltage detection signal VBBDET when it receives the low level from the CMOS inverter 98f.
[0261] In the detection unit 98b, the gate of the pMOS of the reference voltage generating part 98d and the gate of the nMOS 98g are supplied with the inverted logic of the low power signal NAPX. The remaining constructions are identical to those of the detection unit 98a. In this embodiment, the CMOS inverter 98f outputs the low level in response to the detection result at the level detecting part 98e (i.e., the voltage of the output node NOUT1) when the substrate voltage VBB rises to -1.0 V in the normal operation mode. The output of the reference voltage generating part 98d of the detection unit 98b has the ground voltage VSS (at 0 V) when the low power signal NAPX is at the low level (during the power consumption mode). Therefore, the output node NOUT2 of the level detecting part 98e has the low level at all times. In short, the detection unit 98b is inactivated during the power consumption mode.
[0262] Therefore, the VBB detector 98 uses only the detection unit 98b in the normal operation mode and activates the substrate voltage detection signal VBBDET when the substrate voltage VBB rises to -1.0 V. When the substrate voltage detection signal VBBDET is activated, the units 112 and 114 of the substrate voltage generating circuit 100, as shown in FIGS. 29 and 30, operate so that the substrate voltage VBB drops.
[0263] During the low power consumption mode, on the other hand, the VBB detector 98 activates the detection unit 98a but inactivates the detection unit 98b when the low power signal NAPX is activated. As a result, the power consumption of the VBB detector 98 is reduced. The level of the substrate voltage VBB is detected during the power consumption mode only by the detection unit 98a so that the substrate voltage detection signal VBBDET is activated when the substrate voltage VBB rises to -0.5 V. The detection level (in an absolute value) of the substrate voltage VBB becomes low so that the absolute value of the substrate voltage VBB to be generated by the substrate voltage generator 100 is reduced. In other words, the operation of the substrate voltage generator 100 is further suppressed during the power consumption mode than during the normal operation mode. As a result, the power consumption can be reduced. The difference between the substrate voltage VBB and the ground voltage VSS is decreased, thereby reducing the substrate leakage. Therefore, the occurrence frequency of the substrate voltage detection signal VBBDET is lowered to decrease the operation frequency of the substrate voltage generator 100. As a result, the power consumption can be further reduced.
[0265] This precharging voltage generator 94 is provided with differential amplifiers 94a and 94b and a VPR generator 94c.
[0266] The differential amplifier 94a has a current mirror part 94d composed of pMOSes, and a pair of differential input parts 94e and 94f composed of nMOSes. Both the inputs of the differential input parts 94e and 94f receive the reference voltage VPRREFL and the precharging voltage VPR. The differential input part 94e is connected with the ground line VSS through the always on nMOS, and the differential input part 94f is connected with the ground line VSS through the nMOS which is turned on when the low power signal NAPX is inactivated.
[0267] In short, the differential input part 94e operates at all times, but the differential input part 94f operates only when the low power signal NAPX is inactivated. The differential input part 94f stops its operation during the power consumption mode so that the power consumption is reduced. The differential amplifier 94a sets the output node NOUT3 to the low level when the reference voltage VPRREFL is higher than the precharging voltage VPR.
[0268] The differential amplifier 94b has a current mirror part 94g composed of nMOSes, and a pair of differential input parts 94h and 94i composed of pMOSes. Both the inputs of the differential input parts 94h and 94i receive the reference voltage VPRREFH and the precharging voltage VPR. The differential input part 94g is connected with the power supply line VDD through the always on pMOS, and the differential input part 94i is connected with the power supply line VDD through the pMOS which is turned on when the low power signal NAPX is inactivated.
[0269] The differential input part 94h operates at all times, but the differential input part 94i operates only when the low power signal NAPX is inactivated. During the low power consumption mode, the differential input part 94i stops its operation so that the power consumption is reduced. The differential amplifier 94b sets the output node NOUT4 to the low level when the reference voltage VPRREFH is lower than the precharging voltage VPR.
[0270] The VPR generator 94c has a pMOS and an nMOS connected in series between the power supply line VDD and the ground line VSS. The gate of the pMOS connects the output node NOUT3. The gate of the nMOS connects the output node NOUT4. From the drains of the pMOS and the nMOS, there is outputted the precharging voltage VPR. This precharging voltage VPR is used as the equalizing voltage of the paired bit lines and the plate voltage of the memory cells in the memory core 38.
[0271] The inactivation of the differential input parts 94f and 94i during the power consumption mode deteriorates the response of the precharging voltage generator 94 to a shift in the precharging voltage. As will be described hereinafter, however, the reading operation and the refreshing operation are not executed during the power consumption mode so that no problem arises even if the response of the precharging voltage generator 94 is lowered.
[0273] This oscillator 104 is provided with a ring oscillator 104a having odd stages of CMOS inverters connected in cascade, and a buffer 104b for extracting an oscillating signal OSCZ from the ring oscillator 104a. Frames of broken lines in FIG. 33 are switches for adjusting the stage number (corresponding to the self-refreshing period) of the ring oscillator 104a. The on/off of these switches are set by the blow of the polysilicon fuse or by the layout pattern of the photomask of the wiring layer. In this example, the stage number of the ring oscillator 104a is set to "7". The sources of the pMOSes and the nMOSes of the CMOS inverters are io connected with the internal power supply line VII and the ground line VSS, respectively, through the pMOS loads and the nMOS loads. The gates of the pMOS loads and the nMOS loads are controlled with the control voltages PCNTL and NCNTL, respectively. The oscillator 104 has pMOSes and nMOSes for receiving the control of the low power signal NAPX. When the low power signal NAPX is activated, those pMOSes are turned on to fix the predetermined node of the ring oscillator 104a to the high level, but the connections between the nMOSes of the CMOS inverters and the ground line VSS are broken when those nMOSes are turned off. As a result, the oscillator 104 stops its operation during the power consumption mode.
[0276] The control voltage PCNTL is generated from the connection node between the pMOS diode and the resistor, and varies with the shift of the internal power supply voltage VII. The control voltage NCNTL is generated from the connection node between the nMOS diode and the resistor, and varies with the shift of the ground voltage VSS. Therefore, the gate-to-source voltage of the pMOS and the nMOS of the CMOS inverter shown in FIG. 33 is always constant so that the oscillation period of the ring oscillator 104a is constant irrespective of the shift of the internal power supply voltage VII. The MOS capacitor prevents the high-frequency noises to occur on the internal power supply line VII and the ground line VSS from influencing the control voltage PCNTL and the control voltage NCNTL. As a result, the shifts of the internal power supply voltage VII and the ground voltage VSS are canceled so that the oscillating signal OSCZ is generated always for a predetermined period while the oscillating circuit 104 is active (in the self-refreshing mode).
[0279] When the low power signal NAPX is activated, the reference voltage generator 24 shown in FIG. 23 lowers the levels of the reference voltages VRFV, VPREF, VPREFL and VPREFH. The VPP detector 90 shown in FIG. 28 inactivates the differential input part 90e and simultaneously lowers the level of the control voltage VPP2 to be supplied to the differential input part 90d. The unit 108 of the booster 92, as shown in FIG. 25, and the unit 112 of the substrate voltage generator 100 stop their operations. The VBB detector 98 shown in FIG. 31 inactivates the detection unit 98b but activates the detection unit 98a to raise the detection level of the substrate voltage VBB. Specifically, the substrate voltage detection signal VBBDET is activated when the substrate voltage VBB rises to -0.5 V. The differential amplifiers 94a and 94b of the precharging voltage generator 94 shown in FIG. 32 inactivate the differential input parts 94f and 94i, respectively. The oscillator 104 shown in FIG. 33 stops its operation. The generator 116 shown in FIG. 34 is inactivated.
[0287] During the low power consumption mode, the connection between the internal power supply line VII and the stabilized capacitor 96a is kept, and the connection between the internal power supply line VII and the internal circuit (the peripheral circuit 40 and the memory core 38) is broken. The power supply to the peripheral circuit 40 is stopped so that the leakage current to the peripheral circuit 40 can disappear to reduce the power consumption to zero. When the internal power supply line VII and the internal circuit are connected after the release from the low power consumption mode, the voltage corresponding to the electric charge stored in the stabilized capacitor 96a is supplied to the internal circuit through the internal power supply line VII. Before the internal supply voltage generator 96 generates a predetermined internal power supply voltage VII after the release from the low power consumption mode, therefore, the voltage corresponding to the electric charge stored in the stabilized capacitor 96a can be applied to the internal circuit. As a result, the internal circuit can operate immediately after the release from the low power consumption mode.
[0288] During the low power consumption mode, the differential input part 90e in the differential amplifier 90a of the VPP detector 90 and the differential input parts 94f and 94i in the differential amplifiers 94a and 94b of the precharging voltage generator 94 are inactivated so that the power consumption of the differential amplifiers 90a, 94a, and 94b can be reduced.
[0293] The foregoing second embodiment has been described on an example in which the low power entry circuit 50 is formed by connecting the plurality of delay circuits 54c in series. However, the present invention should not be limited thereto but may form the low power entry circuit by using a latch circuit to be controlled by the Si iCRX signal, for example. In this modification, the circuit scale is reduced.
[0296] The foregoing sixth embodiment has been described on an example of operating the start signal generator 82 as a timer for determining the length of the period T2 at the exit from the low power consumption mode and activating a SII PZ signal(reset signal) for initializing an internal circuit during the period T2. The present invention is not limited to this embodiment. For example, at the time of the exit from the low power consumption mode, a counter operating in normal operation is operated as a timer so as to count a predetermined number. The reset signal for initializing an internal circuit may well be activated during a period where the counter counts the number. A refresh counter indicating the refresh address of memory cells or the like can be used as the counter.
Patent applications by Koichi Nishimura, Yokohama-Shi JP
Patent applications by Kotoku Sato, Yokohama-Shi JP
Patent applications by Shinya Fujioka, Yokohama-Shi JP
Patent applications by Tomohiro Kawakubo, Yokohama-Shi JP
2013-12-12 Semiconductor memory device, and method of controlling the same