Source: http://www.google.com/patents/US20030054653?ie=ISO-8859-1&dq=7350717
Timestamp: 2014-10-22 14:26:09
Document Index: 6957504

Matched Legal Cases: ['art 3002', 'art 3003', 'art 3003', 'art 3003', 'art 3402', 'art 3403', 'art 3402', 'art 3402', 'art 4103', 'art 4103']

Patent US20030054653 - Wiring and method of manufacturing the same, and wiring board and method of ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe wiring of the present invention has a layered structure that includes a first conductive layer (first layer) having a first width and made of one or a plurality of kinds of elements selected from W and Mo, or an alloy or compound mainly containing the element, a low-resistant second conductive layer...http://www.google.com/patents/US20030054653?utm_source=gb-gplus-sharePatent US20030054653 - Wiring and method of manufacturing the same, and wiring board and method of manufacturing the sameAdvanced Patent SearchPublication numberUS20030054653 A1Publication typeApplicationApplication numberUS 10/099,972Publication dateMar 20, 2003Filing dateMar 19, 2002Priority dateMar 27, 2001Also published asCN1311549C, CN1378276A, CN100573884C, CN101009241A, CN101009241B, CN101009292A, US7169710, US7884369, US20070013859Publication number099972, 10099972, US 2003/0054653 A1, US 2003/054653 A1, US 20030054653 A1, US 20030054653A1, US 2003054653 A1, US 2003054653A1, US-A1-20030054653, US-A1-2003054653, US2003/0054653A1, US2003/054653A1, US20030054653 A1, US20030054653A1, US2003054653 A1, US2003054653A1InventorsShunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro KusuyamaOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManReferenced by (53), Classifications (34), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetWiring and method of manufacturing the same, and wiring board and method of manufacturing the sameUS 20030054653 A1Abstract The wiring of the present invention has a layered structure that includes a first conductive layer (first layer) having a first width and made of one or a plurality of kinds of elements selected from W and Mo, or an alloy or compound mainly containing the element, a low-resistant second conductive layer (second layer) having a second width smaller than the first width, and made of an alloy or a compound mainly containing Al, and a third conductive layer (third layer) having a third width smaller than the second width, and made of an alloy or compound mainly containing Ti. With this constitution, the present invention is fully ready for enlargement of a pixel portion. At least edges of the second conductive layer have a taper-shaped cross-section. Because of this shape, satisfactory coverage can be obtained. Images(23) Claims(46)
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to wiring formed by using a thin film technique and a method of manufacturing the same. The present invention also relates to a wiring board and a method of manufacturing the same. In the present specification, a wiring board refers to an insulating substrate made of glass, etc. or various substrates having wiring formed by using a thin film technique. [0003] 2. Description of the Related Art [0004] In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (thickness of about several to hundreds of nm) formed on a substrate with an insulating surface has been paid attention to. A TFT is widely applied to an electronic device such as an integrated circuit (IC) and an electrooptic apparatus. In particular, a TFT is being rapidly developed as a switching element of an image display apparatus. [0005] Conventionally, a liquid crystal display device as an image display apparatus is known. Since an image of higher precision can be obtained compared with a passive type liquid crystal display device, an active matrix type liquid crystal display device is being used more. In an active matrix type liquid crystal display device, pixel electrodes arranged in matrix are driven, whereby a display pattern is formed on a screen. More specifically, a voltage is applied between a selected pixel electrode and a counter electrode corresponding to the pixel electrode, whereby a liquid crystal layer disposed between the pixel electrode and the counter electrode is subjected to optical modulation, and this optical modulation is recognized by an observer as a display pattern. [0006] Such an active matrix type liquid crystal display device finds a wider range of uses, and there is an increasing demand for high precision, a high aperture ratio, and high reliability, as well as enlargement of a screen size. There is also a demand for enhancement of productivity and a decrease in cost. [0007] In the case where aluminum (Al) is used as wiring of the above-mentioned TFT in order to manufacture TFT, projections such as hillock and whisker are formed due to a heat treatment, and an Al atom diffuses to an insulating film and an active region (in particular, a channel-formation region), which may cause operation defects of the TFT or a decrease in electrical characteristics of the TFT. [0008] Under such a circumstance, the use of a metal material withstanding a heat treatment (typically, a metal element having a high melting point, such as tungsten (W) and molybdenum (Mo)) is considered. However, the resistance of these elements is very high compared with that of Al (see Table 1). TABLE 1 wiring material resistivity [μΩcm] Al 2 W 10�20 Mo 15�25 [0009] Therefore, when a screen size is enlarged, a wiring delay becomes a problem. In view of this, a method for decreasing a resistance by making wiring thicker is considered. However, when the width of wiring is enlarged, a degree of design freedom and an aperture ratio in a pixel portion may be lowered. Furthermore, when the film thickness of wiring is made larger, a short-circuit is likely to be caused at a portion where wiring crosses to each other three-dimensionally, and coverage is degraded at the step difference portion of the wiring. SUMMARY OF THE INVENTION [0010] Therefore, with the foregoing in mind, it is an object of the present invention to provide wiring that is ready for enlargement of a screen and a method of manufacturing the same, and a wiring board and a method of manufacturing the same. [0011] According to the present invention, wiring has a layered structure that includes: as a first layer, a conductive film mainly containing one or a plurality of kinds of elements selected from W and Mo, or one or a plurality of kinds of elements selected from W and Mo; as a second layer, a low-resistant conductive film mainly containing Al; and as a third layer, a conductive film mainly containing Ti, whereby it is attempted to lower a resistance of wiring. According to the present invention, the low-resistant conductive film mainly containing Al is sandwiched with other conductive films, whereby formation of projections such as hillock and whisker due to a heat treatment can be prevented. Furthermore, since the first and third layers are made of conductive films with a high melting point, they function as barrier metal, which can prevent an Al atom from diffusing to an insulating film and an active region (Table 2). Furthermore, when an insulating film is formed on wiring of the present invention, and contact with the wiring is formed, the third layer functions as a stopper for etching of the insulating film, so that contact can be easily formed. When Al comes into contact with an ITO film (typical transparent conductive film), Al causes electric corrosion to increase a contact resistance. However, the third layer is made of a conductive film mainly containing Ti, so that a contact resistance becomes satisfactory. TABLE 2 wiring material melting point [� C.] Al 660.4 W 3387 Mo 2610 Ti 1675 [0012] Furthermore, according to the present invention, at least edges of the second layer made of a low-resistant conductive film mainly containing Al have a taper shape. Because of the taper shape, coverage at the step difference portion is enhanced. In the present specification, a taper angle refers to an angle formed by a horizontal surface and a side surface of a material layer. Furthermore, in the present specification, for convenience sake, the side surface with a taper angle is referred to as a taper shape, and a portion with a taper shape is referred to as a taper portion. [0013] A constitution of the present invention disclosed in the present specification relates to wiring having a layered structure that includes a first conductive layer with a first width as a first layer, a second conductive layer with a second width smaller than the first width as a second layer, and a third conductive layer with a third width smaller than the second width as a third layer, characterized in that a cross-section of edges of the first conductive layer, the second conductive layer, or the third conductive layer has a taper shape. [0014] In the above-mentioned constitution, the wiring is characterized by having a layered structure that includes a conductive layer (first layer) made of an alloy or a compound mainly containing W, a conductive layer (second layer) made of an alloy or a compound mainly containing Al, and a conductive layer ( third layer) made of an alloy or a compound mainly containing Ti. Alternatively, the wiring is characterized by having a layered structure that includes a conductive layer (first layer) made of an alloy or a compound mainly containing Mo, a conductive layer (second layer) made of an alloy or a compound mainly containing Al, and a conductive layer (third layer) made of an alloy or a compound mainly containing Ti. For example, as the first layer, W, WN, Mo, or the like can be used. As the second layer, Al, Al�Si (2 wt %), Al�Ti (1 wt %), Al�Nd (1 wt %), Al�Sc (0.18 wt %), or the like can be used. As the third layer, Ti, TiN, or the like can be used. These layers can be formed by sputtering, plasma CVD, or the like. Furthermore, when Al�Si or the like is formed in the second layer, there is a limit (solid solubility limit) to the ratio at which an element such as Si can dissolve in Al. As the solution degree is higher, a resistance is increased, and heat resistance is also changed. Therefore, those skilled in the art may appropriately determine the ratio of Si or the like to Al, depending upon the resistance and heat resistance suitable for wiring, and the solid solubility limit of an element such as Si. [0015] Table 3 shows examples of a resistance in each conductive layer that constitutes wiring. It is understood from Table 3 that a conductive layer made of an alloy or a compound mainly containing Al has a very low resistance, compared with the other conductive layers. TABLE 3 wiring material resistivity [μΩcm] material mainly containing W W 10�20 WN 150�220 material mainly containing Al Al 2 Al�Si (2 wt %) 3.5�4.5 Ai�Ti (1 wt %) 8�10 Al�Nd (1 wt %) 7�10 Al�Sc (0.18 wt %) 3.5�4.0 material mainly containing Ti Ti 50�60 TiN 130�200 [0016] Any etching method can be applied, as long as the first, second, and third conductive films having heat resistance and conductivity can be etched at a high speed with good precision, and end portions of the films can be tapered. Among them, a dry etching method using high-density plasma is desirably used. An etching apparatus using a microwave, helicon wave plasma (HWP), or inductively coupled plasma (ICP) is suitable for a procedure of obtaining high-density plasma. For example, an electron cyclotron resonance (ECR) etching apparatus, a surface wave plasma (SWP) etching apparatus, an ICP etching apparatus, a two-frequency parallel-plate excitation-type etching apparatus, or the like may be used. In particular, the ICP etching apparatus controls plasma easily, and is ready for enlargement of a substrate to be treated. [0017] For example, in order to conduct a plasma treatment with high precision, a method of forming plasma by applying a high-frequency electric power to a multi-spiral coil (in which a plurality of spiral coil portions are connected in parallel via an impedance matching circuit) is used. Furthermore, a high-frequency electric power is also applied to a lower electrode holding a substance to be treated, thereby supplying a bias voltage thereto. [0018] When the ICP etching apparatus adopting such a multi-spiral coil is used, a taper angle is substantially varied depending upon a bias electric power applied to a substrate side. Therefore, by further increasing a bias electric power and changing a pressure, a taper angle can be changed in a range of 5� to 85�. [0019] As gas used for etching the second and third layers, a chlorine gas is desirable. For example, SiCl4, HCl, CCl4, BCl3, Cl2, or the like can be used. [0020] As gas used for etching the first layer, fluorine gas is desirable. For example, NF3, CF4, C2F6, SF6, or the like can be used. When a chlorine gas is introduced simultaneously with a fluorine gas, an etching rate in the first layer is enhanced, which is desirable. [0021] Furthermore, by allowing the wiring to have a layered structure including the above-mentioned conductive layers, the edges of the wiring are tapered by using an ICP etching method or the like. By tapering the edges of the wiring, coverage of films to be formed in the later processes can be made satisfactory. [0022] In the above-mentioned constitution, the edges of the first conductive layer are desirably tapered. A portion having a taper shape (i.e., a taper portion) is a region that is not overlapped with the second conductive layer, and the width of the region corresponds to that obtained by subtracting the second width from the first width. It is also desirable that the second conductive layer is tapered, and the taper angle thereof is made larger than that of the taper portion of the first conductive layer. Furthermore, it is desirable that the third conductive layer is tapered, and the taper angle thereof is made substantially the same as that of the taper portion of the second conductive layer. [0023] The constitution for realizing the present invention relates to a method of a manufacturing wiring comprising the steps of: forming a first-shaped conductive layer comprising a lamination of a first conductive layer, a second conductive layer, and a third conductive layer on an insulating surface; etching the first conductive layer, the second conductive layer and the third conductive layer to form a second-shaped conductive layer comprising a lamination of the first conductive layer with a first width, a second conductive layer with a second width, and a third conductive layer with a third width; and etching the second conductive layer with the second width and the third conductive layer with the third width to form a third-shaped conductive layer comprising a lamination of a first conductive layer with a fourth width, a second conductive layer with a fifth width, and a third conductive layer with sixth width, wherein a cross-section of edges of the first conductive layer, the second conductive layer, or the third conductive layer has a taper shape. [0024] In the above-mentioned constitution, the wiring is characterized by having a layered structure including a conductive layer (first layer) made of an alloy or a compound mainly containing W, a conductive layer (second layer) made of an alloy or a compound mainly containing Al, and a conductive layer (third layer) made of an alloy or a compound mainly containing Ti. Alternatively, the wiring is characterized by having a layered structure including a conductive layer (first layer) made of an alloy or a compound mainly containing Mo, a conductive layer (second layer) made of an alloy or a compound mainly containing Al, and a conductive layer (third layer) made of an alloy or a compound mainly containing Ti. [0025] Furthermore, by allowing the wiring to have a layered structure including the above-mentioned conductive layers, the edges of the wiring are tapered by using an ICP etching method or the like. By tapering the edges of the wiring, coverage of films to be formed in the later processes can be made satisfactory. [0026] In the above-mentioned constitution, the edges of the first conductive layer are desirably tapered. A portion having a taper shape (i.e., a taper portion) is a region that is not overlapped with the second conductive layer, and the width of the region corresponds to that obtained by subtracting the second width from the first width. It is also desirable that the second conductive layer is tapered, and the taper angle thereof is made larger than that of the taper portion of the first conductive layer. Furthermore, it is desirable that the third conductive layer is tapered and the taper angle thereof is made substantially the same as that of the taper portion of the second conductive layer. [0027] The constitution of the present invention relates to a wiring board including an insulating substrate and wiring, characterized in that the wiring has a layered structure including: as a first layer, a first conductive layer with a first width; as a second layer, a second conductive layer with a second width smaller than the first width; and as a third layer, a third conductive layer with a third width smaller than the second width, and characterized in that a cross-section of edges of the first conductive layer, the second conductive layer, or the third conductive layer has a taper shape. [0028] In the above-mentioned constitution, the process of forming the wiring is characterized in that a conductive film mainly containing W, a conductive film mainly containing Al, and a conductive film mainly containing Ti are stacked on top of each other, followed by etching with a mask. Furthermore, in the above-mentioned constitution, the process of forming the wiring is characterized in that a conductive film mainly containing Mo, a conductive film mainly containing Al, and a conductive film mainly containing Ti are stacked on top of each other, followed by etching with a mask. [0029] In the above-mentioned constitution, the edges of the first conductive layer are desirably tapered. A portion having a taper shape (i.e., a taper portion) is a region that is not overlapped with the second conductive layer, and the width of the region corresponds to that obtained by subtracting the second width from the first width. It is also desirable that the second conductive layer is tapered, and the taper angle thereof is made larger than that of the taper portion of the first conductive layer. Furthermore, it is desirable that the third conductive layer is tapered, and the taper angle thereof is made substantially the same as that of the taper portion of the second conductive layer. [0030] Furthermore, the constitution for realizing the present invention relates to a method of manufacturing a wiring board, characterized by including the steps of: forming a first conductive layer on an insulating surface; forming a second conductive layer on the first conductive layer; forming a third conductive layer on the second conductive layer, and etching the first to third conductive layers to form a conductive layer with a taper portion. [0031] In the above-mentioned constitution, the process of forming the wiring is characterized in that a conductive film mainly containing W, a conductive film mainly containing Al, and a conductive film mainly containing Ti are stacked on top of each other, followed by etching with a mask. Furthermore, in the above-mentioned constitution, the process of forming the wiring is characterized in that a conductive film mainly containing Mo, a conductive film mainly containing Al, and a conductive film mainly containing Ti are stacked on top of each other, followed by etching with a mask. [0032] Furthermore, by allowing the wiring to have a layered structure including the above-mentioned conductive layers, the edges of the wiring are tapered by using an ICP etching method or the like. By tapering the edges of the wiring, coverage of films to be formed in the later processes can be made satisfactory. [0033] In the above-mentioned constitution, the edges of the first conductive layer are desirably tapered. A portion having a taper shape (i.e., a taper portion) is a region that is not overlapped with the second conductive layer, and the width of the region corresponds to that obtained by subtracting the second width from the first width. It is also desirable that the second conductive layer is tapered, and the taper angle thereof is made larger than that of the taper portion of the first conductive layer. Furthermore, it is desirable that the third conductive layer is tapered, and the taper angle thereof is made substantially the same as that of the taper portion of the second conductive layer. [0034] According to the present invention, a low resistance can be realized in wiring by a simple method suitable for processes of manufacturing conventional wiring or wiring board. Therefore, a degree of design freedom and an aperture ratio in a pixel portion can be enhanced. Since wiring includes conductive layers with a taper shape, satisfactory coverage is obtained. Because of such advantages, in a semiconductor device represented by an active matrix type liquid crystal display device, the present invention is fully ready for enlargement of a screen caused by an increased area of a pixel portion, which allows the operation characteristics and reliability of the semiconductor device to be enhanced.
[0073] An exemplary structure of a wiring board provided with a gate electrode using the present invention will be described below. [0074] First, a base insulating film 11 is formed on a substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a silicon substrate, or a metal substrate or a flexible substrate with an insulating film formed thereon may be used. Furthermore, a plastic substrate having heat resistance withstanding a treatment temperature may be used. In the present embodiment, a glass substrate (1737 produced by Corning Co.) was used. [0075] As the base insulating film 11, a base film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Herein, the base film 11 with a double-layered structure (11 a, 11 b) is exemplified; however, the base film 11 may be a single-layer film of the insulating film or may have a multi-layered structure of two or more layers. Note that the base insulating film may not be formed. In the present embodiment, a silicon oxynitride film 11 a with a thickness of 50 nm (composition ratio: Si=32%, O=27%, N=24%, H=17%) was formed. Then, a silicon oxynitride film 11 b with a thickness of 100 nm (composition ratio: Si=32%, O=59%. N=7%, H=2%) was formed. [0076] Then, a semiconductor layer 12 is formed on the base insulating film 11. The semiconductor layer 12 is obtained by forming a semiconductor film with an amorphous structure by a known method (sputtering, LPCVD, plasma CVD, etc.), crystallizing the semiconductor film by known crystallization (laser crystallization, thermal crystallization, thermal crystallization using a catalyst such as nickel, etc.), and patterning the crystalline semiconductor film to a desired shape using a first photomask. The semiconductor layer 12 is formed to have a thickness of 25 to 80 nm (preferably, 30 to 60 nm). There is no particular limit to a material for the crystalline semiconductor film; however, the crystalline semiconductor film may be preferably formed of silicon, a silicon-germanium (SiGe) alloy, or the like. In the present embodiment, an amorphous silicon film was formed to have a thickness of 55 nm by plasma CVD, and a solution containing nickel was held on the amorphous silicon film. The amorphous silicon film was dehydrogenated at 500� C. for one hour, and subjected to thermal crystallization at 550� C. for 4 hours. A laser annealing process for improving crystallization was conducted to form a crystalline silicon film. The crystalline silicon film was patterned by photolithography to form a semiconductor layer 12. [0077] Then, an insulating film 13 is formed so as to cover the semiconductor layer 12. The insulating film 13 is formed to have a thickness of 40 to 150 nm by plasma CVD or sputtering so as to have a single-layered structure or a multi-layered structure of an insulating film containing silicon. The insulating film 13 is to be a gate insulating film. In the present embodiment, a silicon oxynitride film (composition ratio: Si=32%, O=59%, N=7%, H=2%) was formed to have a thickness of 110 nm by plasma CVD. [0078] Next, a first conductive film 14 (thickness: 20 to 100 nm), a second conductive film 15 (thickness: 100 to 800 nm), and a third conductive film 16 (thickness: 20 to 100 nm) are layered on the insulating film 13. Herein, these conductive films may be formed by sputtering or the like, and as the first conductive film 14 contacting the insulating film 13, a conductive film (W, WMo, Mo, etc.) mainly containing W or Mo may be used so as to prevent diffusion of impurities from the substrate 10 to a channel formation region. Furthermore, as the second conductive film 15, a low-resistant conductive film (Al, Al�Ti, Al�Sc, Al�Si, etc.) mainly containing Al may be used. As the third conductive film 16, a conductive film mainly containing Ti (Ti, TiN, etc.) with a low contact resistance may be used. In the present embodiment, a first conductive film 14 made of a W film (thickness: 30 nm), a second conductive film 15 made of an Al�Ti film (thickness: 500 nm), and a third conductive film 16 made of a Ti film (thickness: 50 nm) were layered by sputtering. The ratio of Ti of the second conductive film 15 was 1%, and the second conductive film 15 was formed using Al�Ti as a target. [0079] Then, a first etching process is conducted. The first etching process is conducted under first etching condition and second etching condition. In the present embodiment, under the first etching condition, an ICP etching method was used. More specifically, etching was conducted for 147 seconds by generating plasma, using BCl2, Cl2, and O2 as an etching gas in a gas flow rate of 65:10:5 (sccm) with an RF (13.56 MHz) power of 450 W supplied to a coil-shaped electrode under a pressure of 1.2 Pa. Herein, a dry etching apparatus (Model E645-ICP) using ICP produced by Matsushita Electric Industrial Co., Ltd. was used. An RF (13.56 MHz) power of 300 W is also supplied to a substrate side (sample stage), whereby a substantially negative self-bias voltage is applied thereto. Under the first etching condition, an etching speed with respect to the resist is 235.5 nm/min, an etching speed with respect to Al�Ti is 233.4 nm/min, and an etching speed with respect to W is 133.8 nm/min. The etching speed with respect to Ti is almost the same as that of Al�Ti. As shown in FIG. 22, the Al�Ti film and the Ti film are etched by the first etching condition to obtain a second conductive film 29 and a third conductive film 28. Under the first etching condition, the Al�Ti film and the Ti film are etched to taper the edges of second and third conductive layers. Furthermore, under the first etching condition, the taper angle of the Al�Ti film and the Ti film becomes about 45�. Because the etching speed with respect to W is much smaller than that of resist, T, and Al�Ti, a surface of the first conductive film 14 is mainly etched to form a shape denoted by a reference numeral 30. [0080] Thereafter, the etching condition is changed to the second etching condition without removing the resist mask 17 a. Under the second etching condition, etching was conducted for 30 seconds by generating plasma, using CF4, Cl2, and O2 as an etching gas in a gas flow rate of 25:25:10 (sccm) with an RF (13.56 MHz) power of 500 W supplied to a coil-shaped electrode under a pressure of 1 Pa. An RF (13.56 MHz) power of 20 W is also supplied to a substrate side (sample stage), whereby a substantially negative self-bias voltage is applied thereto. Under the second etching condition in which CF4, Cl2, and O2 are mixed, only the W film is etched. The etching speed with respect to W under the second etching condition is 124.6 nm/min. In order to conduct etching without leaving a residue on a gate insulating film, an etching time may be increased by about 10 to 20%. [0081] In the first etching process, by making the shape of a resist mask appropriate, the edges of the first and second conductive layers are tapered due to the effect of a bias voltage applied to the substrate side. The taper angle may be set to be 15� to 45�. Accordingly, a first-shaped conductive layer composed of the first conductive layer 20 a, the second conductive layer 19 a, and the third conductive layer 18 a is formed by the first etching process. The width of the first conductive layer 20 a in a channel length direction corresponds to W1 shown in the above-mentioned embodiment mode. Reference numeral 21 a denotes a gate insulating film, and regions of the gate insulating film 21 a not covered with the first-shaped conductive layer are slightly etched by about 20 to 50 nm. The first etching process herein corresponds to the first etching process (FIG. 1B) described in the above-mentioned embodiment mode. FIG. 2A shows an SEM photograph of the first-shaped conductive layer thus formed. [0082] Then, a second etching process is conducted without removing a resist mask. Herein, etching was conducted by generating plasma, using BCl3 and Cl2 as an etching gas in a gas flow rate of 20:60 (sccm) with an RF (13.56 MHz) power of 600 W supplied to a coil-shaped electrode under a pressure of 1.2 Pa. An RF (13.56 MHz) power of 100 W is also supplied to the substrate side (sample stage), whereby a substantially negative self-bias voltage is applied thereto. In the second etching process, the Al�Ti film and the Ti film are selectively etched. Due to the second etching process, the taper angle of the Al�Ti film and the Ti film became 80�. During the second etching process, a second conductive layer 19 b and a third conductive layer 18 b are formed. On the other hand, the first conductive layer 20 a is hardly etched compared to the second conductive layer 19 b and the third conductive layer 18 b to form a first conductive layer 20 b. The second etching process herein corresponds to the second etching process (FIG. 1C) described in the above-mentioned embodiment mode. Accordingly, a second-shaped conductive layer was formed, which is composed of the first conductive layer with a width of W1 in a channel length direction, the second conductive layer with a width of W2 therein, and the third conductive layer with a width of W3 therein. FIG. 2B shows an SEM photograph of the second-shaped conductive layer. [0083] Table 4 shows the results obtained by calculating a thickness (nm) of an underlying film to be etched, in the case where an etching rate of a film formed under the Al�Ti film with respect to the Al�Ti film is 2 to 10, considering an in-plane variation of the etching rate of the Al�Ti film. At this time, the thickness was calculated assuming that that the thickness of the Al�Ti film is 500 nm, and there is �5% variation in a plane. TABLE 4 variation in an etching rate with respect to the selection ratio with respect to the underlying film Al�Ti film (� %) 2 3 4 5 6 7 8 9 10 1 300.0 200.0 150.0 120.0 100.0 85.7 75.0 66.7 60.0 2 350.1 233.4 175.1 140.1 116.7 100.0 87.5 77.8 70.0 3 400.4 266.9 200.2 160.1 133.5 114.4 100.1 89.0 80.1 4 450.7 300.5 225.4 180.3 150.2 128.8 112.7 100.2 90.1 5 501.3 334.2 250.6 200.5 167.1 143.2 125.3 111.4 100.3 6 552.0 368.0 276.0 220.8 184.0 157.7 138.0 122.7 110.4 7 603.0 402.0 301.5 241.2 201.0 172.3 150.7 134.0 120.6 8 654.2 436.1 327.1 261.7 218.1 186.9 163.5 145.4 130.8 9 705.7 470.5 352.9 282.3 235.2 201.6 176.4 156.8 141.1 10 757.6 505.1 378.8 303.0 252.5 216.5 189.4 168.4 151.5 11 809.8 539.9 404.9 323.9 269.9 231.4 202.4 180.0 162.0 12 862.4 574.9 431.2 345.0 287.5 246.4 215.6 191.6 172.5 13 915.5 610.3 457.7 366.2 305.2 261.6 228.9 203.4 183.1 14 969.0 646.0 484.5 387.6 323.0 276.9 242.2 215.3 193.8 15 1023.0 682.0 511.5 409.2 341.0 292.3 255.8 227.3 204.6 [0084] As shown in Table 4, as the variation in an etching rate with respect to the Al�Ti film is increased, the thickness to be etched becomes larger. Furthermore, as a selection ratio with respect to the underlying film is increased, the thickness to be etched becomes thinner. If these characteristics are utilized, wiring with a desired shape can be formed. [0085] As described above, according to the present invention, since a gate line is formed of low-resistant conductive layers, even if the area of a pixel portion is enlarged, the pixel can be sufficiently driven. Furthermore, operation characteristics and reliability of a semiconductor device with such wiring formed thereon can be enhanced. [0086] [Embodiment 2]
[0087] In the present embodiment, the case where the first etching condition in the first etching process in Embodiment 1 is changed will be described with reference to FIGS. 3A-3B to 6A-6C. Herein, since the first etching condition is changed, only two layers (second and third conductive layers) in Embodiment 1 constitute a gate line. However, the present invention is also applicable to the case where a gate line is composed of three layers using the first conductive layer in Embodiment 1 as a lower layer. [0088] First, an oxynitride film 33 is formed to have a thickness of 200 nm on a 1737 glass substrate 10 by sputtering. Then, a first conductive film 34 made of an Al�Ti film (thickness: 500 nm) and a second conductive film 35 made of a Ti film (thickness: 100 nm) were layered by sputtering (FIG. 3A). [0089] Then, an etching process is conducted after forming a resist on the second conductive film 35. This etching process is conducted under the first etching condition in Embodiment 1. In the present embodiment, an ICP etching method was used, and BCl2 and Cl2 were used as an etching gas under a pressure of 1.2 Pa. Etching was conducted by varying a gas flow rate and an electric power supplied to a coil-shaped electrode and a substrate side (sample stage) as shown in Table 5 (FIG. 3B). Due to this etching process, a resist, the second conductive film 35, and the first conductive film was etched to form a second conductive layer 37, a first conductive layer 38, and further an oxynitride film 40. A reference numeral 36 denotes a resist after the etching process. TABLE 5 ICP Bias flow rate etching time condition (W) (W) gas (sccm) (sec.) 1 100 300 BCl3:Cl2 60:20 268 2 300 300 BCl3:Cl2 60:20 168 3 700 300 BCl3:Cl2 60:20 159 4 500 100 BCl3:Cl2 60:20 175 5 500 200 BCl3:Cl2 60:20 147 6 500 400 BCl3:Cl2 60:20 147 7 500 300 BCl3:Cl2 20:60 60 8 500 300 BCl3:Cl2 40:40 81 9 500 300 BCl3:Cl2 70:10 350 [0090] FIGS. 4A-4C to 6A-6C show configurations of conductive layers obtained under the conditions shown in Table 5, observed by a factor of 15000 with an SEM. FIG. 4A shows a conductive layer formed under Condition 1. FIG. 4B shows a conductive layer formed under Condition 2. FIG. 4C shows a conductive layer formed under Condition 3. FIG. 5A shows a conductive layer formed under Condition 4. FIG. 5B shows a conductive layer formed under Condition 5. FIG. 5C shows a conductive layer formed under Condition 6. FIG. 6A shows a conductive layer formed under Condition 7. FIG. 6B shows a conductive layer formed under Condition 8. FIG. 6C shows a conductive layer formed under Condition 9. It is understood from FIGS. 4A to 4C that as an electric power supplied to a coil-shaped electrode is increased, a taper angle becomes larger. It is understood from FIGS. 5A to 5C that as an electric power supplied to a substrate side is increased, a taper angle becomes larger. It is understood from FIGS. 6A to 6C that as a gas flow rate of BCl2 is increased, a taper angle becomes larger. Thus, a taper angle is varied depending upon the condition. Furthermore, Table 6 shows etching rates obtained under the conditions shown in Table 5. Table 7 shows a selection ratio with respect to each film. Anisotropic etching is made possible under the condition that a selection ratio between Al�Ti and W is large, whereby a conductive layer with a desired shape can be formed. TABLE 6 flow Al�Si resist SiON ICP Bias rate (nm/min) (nm/min) W (nm/min) (nm/min) condition (W) (W) (sccm) (Ave) (3σ) (Ave) (3σ) (Ave) (3σ) (Ave) (3σ) 1 100 300 60:20 168.8 39.3 122.4 33.1 37.1 6.4 38.4 8.1 2 300 300 60:20 236.9 51.4 197.9 36.7 59.4 16.2 66.4 8.9 3 700 300 60:20 262.1 63.2 263.1 33.2 110.7 23.1 107.6 12.0 4 500 100 60:20 236.7 40.6 133.7 26.3 41.4 17.0 56.0 8.2 5 500 200 60:20 246.8 46.1 199.6 23.7 69.1 22.3 81.8 8.8 6 500 400 60:20 251.0 55.2 255.3 24.4 102.6 21.3 104.0 13.4 7 500 300 20:60 750.7 111.0 395.2 70.7 127.8 49.9 104.0 17.6 8 500 300 40:40 495.6 116.5 351.1 62.2 112.4 39.4 101.0 16.8 9 500 300 70:10 142.3 24.2 148.6 17.7 61.0 10.8 99.3 9.7 [0091] TABLE 7 selection ratio with selection ratio with selection ratio with selection ratio with respect to Al�Si respect to resist respect to W respect to SiON condition resist W SiON Al�Si W SiON Al�Si resist SiON Al�Si resist W 1 1.38 4.55 4.40 0.73 3.30 3.19 0.22 0.30 0.97 0.23 0.31 1.03 2 1.20 3.99 3.57 0.84 3.33 2.98 0.25 0.30 0.89 0.28 0.34 1.12 3 1.00 2.37 2.44 1.00 2.38 2.45 0.42 0.42 1.03 0.41 0.41 0.97 4 1.77 5.72 4.23 0.56 3.23 2.39 0.17 0.31 0.74 0.24 0.42 1.35 5 1.24 3.57 3.02 0.81 2.89 2.44 0.28 0.35 0.85 0.33 0.41 1.18 6 0.98 2.45 2.41 1.02 2.49 2.46 0.41 0.40 0.99 0.41 0.41 1.01 7 1.90 5.88 7.22 0.53 3.09 3.80 0.17 0.32 1.23 0.14 0.26 0.81 8 1.41 4.41 4.91 0.71 3.12 3.47 0.23 0.32 1.11 0.20 0.29 0.90 9 0.96 2.33 1.43 1.04 2.44 1.50 0.43 0.41 0.61 0.70 0.67 1.63 [0092] As described above, by varying the condition, a conductive layer with a desired shape can be obtained. Furthermore, even if the area of a pixel portion is enlarged, a pixel can be sufficiently driven. Operation characteristics and reliability of a semiconductor device with such wiring formed thereon can be enhanced. [0093] [Embodiment 3]
[0238] A wiring board formed according to the present invention can be used for various electrooptic apparatuses (active matrix type liquid crystal display device, active matrix type EC display apparatus, and active matrix type light-emitting device). Specifically, the present invention can be carried out in all the electronic equipment in which these electrooptic apparatuses are incorporated into a display portion. [0239] Examples of such electronic equipment include a personal computer and a display. FIGS. 20A to 20C shows examples thereof. [0240]FIG. 20A shows a personal computer, which includes a body 3001, an image input part 3002, a display part 3003, a keyboard 3004, and the like. The present invention is applicable to the display part 3003. The present invention is ready for enlargement of the display part 3003. [0241]FIG. 20B shows a player using a recording medium storing a program (hereinafter, merely referred to as a recording medium), which includes a body 3401, a display part 3402, a speaker part 3403, a recording medium 3404, an operation switch 3405, and the like. This player uses a digital versatile disk (DVD), a compact disk (CD), and the like as a recording medium, and can be used for listening to music, seeing movies, playing games, and performing the Internet. The present invention is applicable to the display part 3402. The present invention is ready for enlargement of the display part 3402. [0242]FIG. 20C shows a display, which includes a body 4101, a support 4102, a display part 4103, and the like. The present invention is applicable to the display part 4103. The display of the present invention is fully ready for enlargement of a screen. In particular, the present invention is advantageous for a display of 10 inches or more in the opposite angle (particularly, 30 inches or more). [0243] As described above, the range of application of the present invention is extremely large and the present invention is applicable to various fields of electronic equipment. Further, electronic equipment of the present embodiment can be realized by adopting the constitution using any combination of embodiments 1 to 11. [0244] By adopting the constitution of the present invention, the following basic significance can be obtained. [0245] (a) A simple method suitable for processes of manufacturing conventional wiring or wiring board. [0246] (b) Low-resistance can be realized in wiring. Therefore, a degree of design freedom and an aperture ratio in a pixel portion are enhanced. [0247] (c) Satisfactory coverage is obtained. [0248] (d) In a semiconductor device such as an active matrix type liquid crystal display device, while the above-mentioned advantages are satisfied, the area of a pixel portion is enlarged, and the present invention is fully ready for enlargement of a screen, which enhances operational characteristics and reliability of the semiconductor device. [0249] Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be broadly construed. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6891195Jul 31, 2002May 10, 2005Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating the sameUS7064020Dec 23, 2002Jun 20, 2006Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing a semiconductor device having a gate electrode with a three layer structureUS7176069Feb 4, 2004Feb 13, 2007Semiconductor Energy Laboratory Co., Ltd.Manufacture method of display deviceUS7183146Jan 13, 2004Feb 27, 2007Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing semiconductor deviceUS7189654Feb 3, 2004Mar 13, 2007Semiconductor Energy Laboratory Co., Ltd.Manufacturing method for wiringUS7192859May 13, 2004Mar 20, 2007Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing semiconductor device and display deviceUS7202155Aug 5, 2004Apr 10, 2007Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing wiring and method for manufacturing semiconductor deviceUS7232773Apr 20, 2004Jun 19, 2007Semiconductor Energy Laboratory Co., Ltd.Liquid drop jetting apparatus using charged beam and method for manufacturing a pattern using the apparatusUS7358183Apr 2, 2007Apr 15, 2008Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing wiring and method for manufacturing semiconductor deviceUS7399704Oct 1, 2004Jul 15, 2008Semiconductor Energy Laboratory Co., Ltd.Fabrication method of a semiconductor device using liquid repellent filmUS7405033Jan 14, 2004Jul 29, 2008Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing resist pattern and method for manufacturing semiconductor deviceUS7416977Apr 20, 2005Aug 26, 2008Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing display device, liquid crystal television, and EL televisionUS7439086Nov 5, 2004Oct 21, 2008Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing liquid crystal display deviceUS7446054Oct 25, 2004Nov 4, 2008Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing semiconductor deviceUS7482274Apr 14, 2005Jan 27, 2009Semiconductor Energy Laboratory Co., Ltd.Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the sameUS7485579Dec 10, 2003Feb 3, 2009Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing a semiconductor deviceUS7494923Jun 13, 2005Feb 24, 2009Semiconductor Energy Laboratory Co., Ltd.Manufacturing method of wiring substrate and semiconductor deviceUS7510893Feb 4, 2004Mar 31, 2009Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing a display device using droplet emitting meansUS7510905Jan 27, 2005Mar 31, 2009Semiconductor Energy Laboratory Co., Ltd.Forming method of contact hole, and manufacturing method of semiconductor device, liquid crystal display device and EL display deviceUS7538039Apr 25, 2005May 26, 2009Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing a wiring over a substrateUS7554117Mar 25, 2004Jun 30, 2009Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and manufacturing method thereofUS7564059Sep 26, 2005Jul 21, 2009Semiconductor Energy Laboratory Co., Ltd.Semiconductor device with tapered gatesUS7575993Mar 16, 2007Aug 18, 2009Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing semiconductor device and display deviceUS7625493Feb 6, 2004Dec 1, 2009Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing display deviceUS7648897Jan 8, 2007Jan 19, 2010Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing conductive layer and semiconductor deviceUS7655499Feb 10, 2009Feb 2, 2010Semiconductor Energy Laboratory Co., Ltd.Forming method of contact hole and manufacturing method of semiconductor device, liquid crystal display device and EL display deviceUS7709843Oct 25, 2004May 4, 2010Semiconductor Energy Laboratory Co., Ltd.Display device and method for manufacturing the same, and television receiverUS7736955Jan 8, 2007Jun 15, 2010Semiconductor Energy Laboratory Co., Ltd.Manufacture method of display device by using droplet discharge methodUS7847873Jun 12, 2006Dec 7, 2010Semiconductor Energy Laboratory Co., Ltd.Display device and manufacturing method thereofUS7858453Feb 6, 2004Dec 28, 2010Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing semiconductor device and display device utilizing solution ejectorUS7859606Sep 13, 2005Dec 28, 2010Semiconductor Energy Laboratory Co. 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