Source: https://patents.google.com/patent/WO2001073846A1/en
Timestamp: 2020-01-21 07:13:53
Document Index: 431929775

Matched Legal Cases: ['art 2', 'art 3', 'art 3', 'art 4', 'art 5', 'art 4', 'art 4', 'art 2', 'art 4', 'art 5']

WO2001073846A1 - Semiconductor device - Google Patents
WO2001073846A1
WO2001073846A1 PCT/JP2000/001953 JP0001953W WO0173846A1 WO 2001073846 A1 WO2001073846 A1 WO 2001073846A1 JP 0001953 W JP0001953 W JP 0001953W WO 0173846 A1 WO0173846 A1 WO 0173846A1
PCT/JP2000/001953
2000-03-29 Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
2000-03-29 Priority to PCT/JP2000/001953 priority Critical patent/WO2001073846A1/en
2001-10-04 Publication of WO2001073846A1 publication Critical patent/WO2001073846A1/en
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210000000350 MC(T) Anatomy 0 abstract description 9
101700021520 MCC1 family Proteins 0 description 3
201000008550 xeroderma pigmentosum group D Diseases 0 description 3
101700060280 SWD3 family Proteins 0 description 2
102100007604 WDR5 Human genes 0 description 2
101700084234 WDR5 family Proteins 0 description 2
241000907788 Cordia gerascanthus Species 0 description 1
102100019373 MCCC2 Human genes 0 description 1
101700079231 SAC8 family Proteins 0 description 1
In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by using gain cells, a memory cell block constituted as follows is used. A memory block (MCT) comprises a plurality of memory cells (MC0-MC3). Each memory cell includes a PMO transistor (MO) for writing and an NMOS transistor (M1) for reading, and information is stored by holding electric charge in a storage node. The write transistors (MO) are arranged in parallel in a plurality of cells, each source-drain path is connected to a data line (DL). The read transistors (M1) are connected in series in a plurality of cells, and are connected to the data line (DL) via a block selection transistor (MB).
Akira fine manual semi-conductors equipment technology field
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device including a high current multiplication memory using the memory cell having an amplifying effect. BACKGROUND
Dynamic random access' memories (DRAM) is a fast memory in high integration, that is widely used, such as the main memory of a personal computer. One transistor and a transistor 1 Capacity data (1 T 1 C) type cell comprising a single capacitor is used as a memory cell. However, in recent semiconductor equipment, and the breakdown voltage decreases due to miniaturization of the MOS transistor, the operating voltage for low power consumption and summer low. Accordingly, 1, DRAM using a transistor cell, since there is no amplifying effect in the memory cell itself small read signal amount from the memory cell, the operation is likely to become unstable by receiving various noise.
Therefore, as a memory cell which can obtain a large read signal amount by amplifying function, 1 transistor cell commercialized by lifting one so-called gain cell amplification effect has been used previously, it is attracting attention again.
Gain cell is, for example, the eye. I scratch. I over. I over, International sled Tsu Doe State Saki'tsu Conference, Digest 'O Breakfast' Tech two force Norre 'Papers, the first one page from the first 0 pages (1 9 1972) (IEEE International
Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp. 10-11,
1972) (hereinafter referred to as Document 1) and, Ai 'I over' I one 'I scratch, interface one nationalist Nanore sled head -. State'.. Saki'tsu conference, Daijiesu capital 'O blanking Technical Papers, the first丄 from page 2, 1 page 3 (1 9 7 2 years) (IEEE
International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp. 12-13, 1972) (hereinafter, stated in reference 2 hereinafter). These three memory cells arranged transistors on silicon surface has a (hereinafter, 3 is referred to as a transistor cell Le).
As a gain cell of the new structure, two transistors and memory cells that have configured in one of the capacitor, Ai 'I scratch. I over-elect opening Knicks' Letters (1 9 9 9 years May 1 3 days), third 5 Certificates, 1 0 No. (IEE ELECTRONICS LETTERS 13th May 1999 Vol. 35 No. 10) has been proposed (hereinafter, referred to as Document 3). Memory cell shown in Figure 4 of the document 3, the low leakage transistor of the vertical structure, there is a possibility of realizing a very good data retention characteristics. Also, since that is the two transistors comprising the integrated one capacitor structure, it can be highly integrated compared to three-transistor cell of Document 1 and Document 2.
The memory cell of document 3, in addition to the body of the M_〇_S transistor, Wa one word line, bit line, sense line has four terminals of a ground voltage, it is necessary to connect these with the wiring connection contactors door for is required. Therefore, when considering the mask alignment accuracy, there is a possibility that the cell area increases, a means to avoid this is not shown in the literature 3.
Why DR AM is widely used, due to its highly integrated 1 T 1 C-type cell, a small chip area, because bit unit price is lower than the static random access' memories. Memory using memory cells as shown in the literature 3 also, for widespread acceptance in the marketplace, equal to or more highly integrated and DR AM is desired.
An object of the present invention, a memory cell having an amplifying effect achieved with high integration, is to provide a semiconductor device having a memory of a small area of ​​high-speed operation at a low voltage. Disclosure of the Invention
To describe the typical ones of the inventions disclosed by the present application is as follows.
That is, in order to achieve the above object, a semiconductor device according to the present invention, (in terms of the FIG. 1 embodiment to be described later, the data line DL) data line and a first word line crossing the data lines ( and WL 0), a second Wado line crossing the de one data line (WL 1) and a first memory cell provided at an intersection between the data line and the first Wado line (MC 0) When, in a semiconductor device having a second memory cell provided at an intersection between the data line and the second word line (MC 1),
The first memory cell,
A first transistor having a signal path at the time of writing (M0),
A second transistor as a signal path at the time of reading the (Ml),
And a first storage node for holding data by accumulating charges (N), said second memory cell,
Third transistor as a signal path upon a write (MO),
Fourth transistor as a signal path at the time of reading the (Ml),
And a second storage node for holding data by accumulating charges (N), the path of the read signal to the data line from said fourth transistor, configured to include the second transistor it is characterized in.
In this case, the gate of the first transistor is connected to the first Wado line, the gate of the third transistor, Ru preferred Der be connected to the second Wado line. Furthermore, one of the source Z drain terminal of the first transistor is connected to the de one data line, and the other is connected to the first storage node, the one of the source / drain terminal of said third transistor , connected to the data line and the other it is preferred to connect to said second 蓄 Sekinoichido.
The semiconductor device according to the present invention, (in terms of the 3 7 embodiments described later, the data line D LW) write data line and a read data line and (D LR), data write-out the specification first word lines crossing the line and read data lines and (WL 0), a second word line that intersects the data lines and the read data line for the write and (WL 1), and for the write data line first memory cells (MC 0), a second memory cell provided at an intersection between the write data line and the second Wa word line above provided et been at the intersection of the first word line Oite to a semiconductor device having a (MC 1) and,
Said first memory cell,
A first transistor having a signal path upon a write (MO),
A second transistor as a signal path at the time of reading the (M l),
Third transistor as a signal path upon a write (M 0),
Fourth transistor as a signal path at the time of reading the (M l),
Second storage node and a (N), configured to include a path force the second transistor of the read signal from the fourth transistor to the read data lines which holds data by accumulating charges it is also possible to.
In this case, the write data line and the read data lines, it is preferred to configure in different wiring layers. BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 illustrates an example of a memory cell structure of Example 1,
Figure 2 is a timing diagram illustrating the operation of the memory cells of Embodiment 1,
Figure 3 is a block diagram showing a configuration example of a synchronous memory,
Figure 4 is proc diagram showing a configuration example of a memory array portion of FIG. 3,
Figure 5 is a diagram showing a configuration example of a Sabuare shown in FIG. 4,
Figure 6 is a circuit diagram showing a configuration example of a sub Wa de driver shown in FIG. 5,
Figure 7 is a timing diagram illustrating the operation of the sub Wa de driver shown in FIG. 6,
Figure 8 is a circuit diagram showing a configuration example of the sense amplifier shown in FIG. 5,
Figure 9 is a timing diagram illustrating the operation of the sense amplifier shown in FIG. 8,
Figure 1 0 is a diagram showing an example of a memory cell structure of Example 2,
Figure 1 1 is a timing diagram illustrating the write operation of the proc selected cell shown in FIG. 1 0, FIG 1 2 showing the Reiauto of a memory cell of Example 2,
Figure 1 3 is a sectional view showing a memory cell structure of the section along the line A-A 'shown in Reiau preparative view of FIG. 1 2,
Figure 1 4 is a sectional view showing a memory cell structure of the portion along the line B-B 'shown in Reiau preparative view of FIG. 1 2,
Figure 1 5 is a sectional view showing a memory cell structure of the section along the line C-C 'shown in Reiau preparative view of FIG. 1 2,
Figure 1 6 is a manufacturing process (B-B 'sectional view, FIG. 1 7 is a manufacturing process (C-C shows the first memory cell of Example 2' indicating the first memory cell of Example 2 cross-sectional view, Figure 1 8 is a manufacturing process (B-B 'sectional view, C-C 1 9 shows a manufacturing step (Part 2 of the memory cell of example 2' indicating the second memory cell of example 2 cross-sectional view, 2 0 B shows a fabrication process (Part 3 of the memory cells of embodiment 2 - B 'sectional view, FIG. 2. 1 C-C showing a manufacturing process (part 3 of the memory cells of embodiment 2' sectional view, 2 2 manufacturing process (B showing the fourth memory cell of example 2 - B 'sectional view, C-C 2 3 is illustrating a manufacturing process (part 4 of the memory cells of embodiment 2' sectional view, Figure 2 4 is a manufacturing process (indicating the 5 B- B "cross section, C-C 2 5 shows a manufacturing process (part 5 of the memory cells of embodiment 2 'of memory cells of embodiment 2 cross section, Figure 2 6 shows a memory cell structure of example 3 Sectional view of along the portion located Figure 1 2 line B-B 'in FIG,
2 7 is a sectional view of a section along the line C-C 'Yes Figure 1 2-a view showing a memory cell structure of Example 3,
Figure 2 8 shows a manufacturing step (Part 4 of the memory cell of Example 3 B- B 'sectional view, C-C 2 9 shows a manufacturing step (Part 4 of the memory cells of Embodiment 3' sectional view, 3 0 the manufacturing process (B-B 'sectional view, FIG. 3 1 manufacturing process (C-C showing the fifth memory cell of example 3' indicating the 5 memory cells of embodiment 3 cross section, Figure 3 2 shows an example of a memory cell structure of example 4 FIG,
3 3 Thailand grayed diagram illustrating the operation of the memory cell shown in FIG. 3 2,
Figure 3 4 showing the Reiauto memory cell of Example 4,
3 5 is a sectional view showing a memory cell structure of the portion along the line B-B 'shown in Reiau preparative view of FIG. 3 4, 3 6 shown in the Reiauto diagram of FIG 4 C- sectional view showing a memory cell structure of the section along the C 'line,
3 7 is a diagram showing an example of a memory cell structure of Example 5,
Figure 3 8 is a timing diagram illustrating the operation of the memory cell shown in FIG. 3 7,
3 9 is a diagram showing a Reiau bets of the memory cell in Example 5,
4 0 A shown in the Reiauto view of FIG. 3 9 - sectional view showing the A 'memory cell structure of a portion along the line,
Figure 4. 1 is a sectional view showing a memory cell structure of the portion along the line B-B 'shown in Reiau preparative view of FIG 9,
4 2 is a sectional view showing a memory cell structure of C-C 'portion along the line shown in Reiauto diagram of FIG 9,
4 3 manufacturing process (1 shows B- B 'sectional view, FIG. 4 4 manufacturing process (C shows the first memory cell of Example 5 - C' thereof of the memory cells of Embodiment 5 cross-sectional view, 4 5 manufacturing process (B-B 'sectional view, FIG. 4 6 C-C showing a manufacturing process (part 2 of the memory cell of example 5' indicating the second memory cell of example 5 cross-sectional view, 4 7 manufacturing process (B-B 'sectional view, FIG. 4 8 manufacturing process (C-C shows the third memory cell of example 5' indicating the third memory cell of example 5 cross-sectional view, 4 9 manufacturing process (part 4 shown B- B 'sectional view, FIG. 5 0 manufacturing process (C-C showing the fourth memory cell of example 5' of the memory cell of embodiment 5 cross-sectional view, 5 1 manufacturing process (B-B 'sectional view, C-C 5 2 illustrates a manufacturing process (part 5 of the memory cell of example 5' indicating the 5 memory cells of embodiment 5 cross-sectional view, 5 3 the process of manufacturing the memory cell of example 5 (B-B 'sectional view, FIG. 5 4 C-C Note manufacturing process (showing the sixth embodiment 5' indicating the 6 cross-sectional view, FIG. 5 5 another out-of memory cells of Embodiment 5 is a diagram showing: bEST mODE fOR CARRYING OUT tHE iNVENTION
In the following, per specific examples of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings - Note that the "MOS transistor" in the present specification, the insulating gate Ichito type field effect Bok transistor It will be used as a shorthand expression that means. Ku Example 1>
An example of a memory cell arrangement according to the invention shown in FIG. Four of Les the memory cell MC0~MC3 as a memory cell block MCT one ^ 3, Ru. Each memory cell is, PMOS transistor M0 write, read NMOS transistors Ml, the transistor Ml and Ri Contact provided consists of a non-selected NMOS transistor M2 to maintain a non-selected state parallel, the charge storage node N by holding, storing information. Here, the writing and reading means exchanges of signals between the memory cell and the data line, the write operation and read operation of the entire memory is different meanings.
The gate of the writing transistor M0 and the non-select transistor M2 are respectively connected to Wa lead wires WL0 to WL3, 4 pieces of the source / drain path of the write preparative transistor M0 which is arranged in parallel with the memory cell data It is connected to the line DL. Each source / drain path of the reading transistor Ml and the unselected transistor M2 are connected in series with four memory cells, are connected to the data line via a block selecting bets transistor MB which is controlled by the block select line BWL there.
Such a memory cell configuration, as described with reference to specific examples below, it is possible to realize a highly integrated in capable stable operation memory. In this figure, for simplicity of explanation, it shows a case constituting a memory cell block of four memory cells, but is not limited to four, eight or 1 six memory cells in may be configured Memoriserubu-locking MCT, who were or 增 the number of memory cells, the proportion of area occupied by the memory Serupu lock MCT per block selection Tran register MB is reduced. Ie, the total area of ​​the plurality of memory Serupu lock to realize a certain memory capacity is reduced. However, increasing the number of memory cells, the number of the number of transistors connected in series to be read during the current path, the read current is small. Therefore, Shi desirable to configure the memory cell blocks 1 6 or so of the memory cells of four les. This is similar in all the following examples.
The operation of the memory cell structure shown in FIG. 1, will now be described with reference to FIG. In the figure, VB, VR, VW, respectively, waits for the word line voltage, the read word line voltage, a word line voltage for writing. Also, VDL, VSS are respectively, high (high-level) writing voltage and low (low level) writing voltage. In the configuration shown in FIG. 1, the threshold voltage of each transistor data is set so as to realize the following operation. Incidentally, in FIG. 2 shows the threshold voltage Vtn of the NMOS transistor.
In the standby state, Proc select line BWL is a read Wa one word line voltage VR, there block selection transistor MB is the non-conductive state (off state), the non-selection and read transistor Ml of the memory cell MC0 use transistor M2 is separated from the data line D Mr. On the other hand, none of the word lines WL0~WL3 is in a standby word line voltage VB of the high level. Thus, in a state where the non-selected transistor M2 in each memory cell is conducting (on-state), the internal node of the memory cell MC0 to MC3 S, D Hythe also, the same low level of VSS and the source line SL It has become. Incidentally, the read transistor data Ml, according to the voltage held in the storage node N, in the off state or the on state. In operation first, either the word line voltage VR for reading a word line, to select a menu Moriseru. The following describes by the word line WL1 as also was selected memory cell MC1.
In the selected memory cell within MC1, non-select transistor M2 is turned off, depending on whether the transistor Ml for and read out is whether the ON state is turned off, non-conducting or conduction between the internal node S and D or it is determined. In other memory cell MC 0, MC2, MC3, word line is kept waiting for the word line voltage VB, since non-select transistor M2 is in ON state, and conduction between the internal node S and D. Here, by setting the block selection lines BWL in standby Wado line voltage VB, if Tiger for the read memory cell MC 1 Njisuta Ml is in an on state, through the memory cell block MCT data line DL Karaso over scan line current flows to the SL. On the other hand, if the read transistor Ml Gao off state of the memory cell MC1, no current flows from the data line DL to the source line S Mr. That is, the information stored in the storage node N of the main Moriseru MC1 depending on whether it is a '1' power '0', whether or not a current from the data line DL to the source line SL flows is determined. Incidentally, in FIG. 2, in the information '1' (1), provides information '0' is (0), is the same Oite the other timing diagrams. By a two-detecting this current, can determine the information memory cell selected is stored.
In Figure 2, as shown the potential of the data line DL by the solid line, as furo one coating state of the first high level VD Mr. discharged via the memory cell block MCT, amplified by later sense amplifier the voltage It shows the case.
After completion of the sensing operation, returned to Wado line voltage VR for reading the block selection lines BWL, blocking the current path. Then, the Wado line voltage VW for writing selection Wado line WL1. Accordingly, in the memory cell MC1, the writing transistor M0 is turned on, the voltage of the data line DL is applied to the storage Roh one de N, information is written to the memory cell MC 1. Incidentally, the threshold voltage of the PMOS transistor for writing, turned on the write word line voltage VW, is set to so that such an OFF state in the read voltage VR and the standby voltage VB.
At this time, the block select transistor MB, since the current path from the data line DL through the memory cell block MCT to the source line SL is blocked, without Rukoto through current flows, stable write operation can be realized . In the other memory cells MC 0, MC2, C3, the word line is kept waiting for the word line voltage VB, the writing transistor M0 is because in the OFF state, the voltage of the internal node N will not change. By returning the selected word line WL1 to the standby Wado line voltage VB, the writing transistor M0 is turned off in the memory cell MC1, the write operation is completed.
As described above, in the memory cell structure of this embodiment, by providing the non-select transistors in parallel with the read transistor can be formed reliably current path during the non-selected memory cells. Moreover, PMOS Trang the writing transistor M0 register, because has a non-select transistor M2 complementary configuration with NMOS transistors, the standby word line voltage VB with a sufficiently high voltage, a write transistor M0 is sufficiently leak current small off-state, the non-select transistor M2 may be a small on-state sufficiently Chiyane Le resistance.
Also, by the non-selected transistor of the unselected memory cell are turned on, as in the time of reading, the source of the read transistor of the selected memory cell is low-level VSS. Even if the force Ppuringu from the channel of the read transistor, since the voltage of the storage node becomes substantially writing and reading are the same, there is no possibility of effective accumulated voltage is reduced.
Incidentally, NMOS transistor writing transistor M0, read Trang register Ml, non-select transistors M2, the block selection transistors MB and PMOS Bok transistors, it is also possible to operate controlled by a voltage inversely related. In some cases, the person manufacturing process can be simplified. However, since towards the PMOS transistor is a characteristic surface generally conductance is less than NMOS transistors, a write transistor M0 should reduce the leakage current and PMOS transistors, the on-resistance and smaller want read transistor Ml, Trang for unselected register M2, configuration of Figure 1 in which the block select transistors MB and NMOS transistors are preferred.
In JP-A 4 3 4 6 3 JP or Hei 4 1 4 7 4 9 0 JP, memory cell structure in which a memory Serupu lock connected in cascade 1 T 1 C-type DR AM cells is disclosed. The memory cell structure disclosed in these publications, in block units, which is a serial operation, such as read from the beginning to the written memory cell in the end. In contrast, the memory cell structure of the present invention, without destroying the information of the non-selected note Riseru in the memory cell block, is accessible to arbitrary memory cell. Therefore, the memory cell structure of the present invention, similar control can der a normal DR AM is, can achieve the same access time.
Above has described the write operation to the read operation and the memory cell from the memory cell, a read or write operation as a memory, after completion of the sensing operation is performed by transmitting and receiving signals with the outside. Furthermore, by re-writing the information read from the memory cell, the refresh operation is performed.
Incidentally, a result of the above read operation and rewrite operation, reverses the state of the storage node of the selected memory cell. In this case, the as described in Reference 2, the information is positive logic and negative logic les stores the flag indicating whether the turned displaced, and the logical sum of the flags of their connexion , it can be carried out by performing the transmission and reception of signals with the outside, the correct readings out or write operation. Alternatively, it performs an operation two cycles as a unit, the accumulation Bruno once in the memory cell is inverted twice can take operation scheme undone. In this case, the force cycle time as memory increases; a small influence on the access time, area penalty small les.
Next, the overall configuration of the memory using the memory cell structure. Figure 3 is a schematic block diagram showing a configuration example of a synchronous type memory. Clock buffer CLKB, command buffer CB, command Dodekoda CD, address buffer AB, has Karamua dress counter YCT, input buffer DIB, the output buffer DOB, further it contains do the memory array MAR sector SCTO, SCT1, ... is provided It is. Sector is correspond to the bank, it may be used as a plurality of sectors per bank. Sector further comprises a row predecoder XPD, column predecoder YPD, write buffer WB, and main amplifier MA. Each circuit block serves as follows. Clock buffer CLKB is an external click-locking CLK as 內部 click-locking CLKI, distributes the like to the command decoder CD. Command decoder CD, in response to a control signal CMD from the outside, § address buffer AB, a column § address counter YCT, input buffer DIB, it generates a control signal for controlling the output buffer DOB. Address buffer AB is the desired data I timing in accordance with the external clock CLK, it captures § address ADR from the outside, and sends a mouth Wadoresu BX to mouth Wadoresu predecoder XPD. Row address predecoder XPD is a row address BX and up Ridekodo, the row pre-decode address CX and mat selection signal the MS, and outputs the Memoriare one MAR.
§ dress buffer AB also, Ru send a Karamuadoresu to the column § address counter YCT. Column § address counter YCT is the Adoresu as an initial value, it generates a Karamuadoresu BY Burst operation, and Purideko once by column § address predecoder YPD, and outputs a column pre-decode address CY to the memory array MAR. Input cover Ffa DIB takes in data input and output data DQ with the outside at a desired timing, and outputs the line Todeta GI to write buffer WB.
Write buffer WB, and outputs the line Todeta GI to the main input and output line MI0. On the other hand, the main amplifier MA amplifies the signal of the main input and output lines MI0, and outputs it to cover Ffa DOB out the read data GO. The output buffer DOB is a desired Timing to input and output data DQ, and outputs the read data GO.
Thus, by using the memory cell structure according to the present invention, a synchronous memory having the same block structure as the sink port eggplant DRAM (SDRAM) can be realized. By synchronously with an external clock-locking CLK and synchronous memory for inputting and outputting uptake and data command Ya Adoresu is capable of operating at high frequencies, high data rate can be achieved. Memory cell arrangement according to the invention is not limited to SDRAM, leave in applications to various high-speed memory system which has been developed for DRAM using 1 T 1 C-type note Riseru.
Figure 4 shows a configuration example of a memory array MAR in FIG. The Sabuwadodorainoku portion WDG00~WDG74 and the sense amplifier section SAG00～SAG83, is divided into a plurality pieces of sub-arrays MCA00~MCA73 (3 2 of 8 X 4 in this view). Sub-word driver unit WDG00~WDG74 operate is selected by the row decoder XDEC0～XDEC7. On the other hand, the sense amplifier unit SAG00~SAG83 is controlled by sense amplifier control circuit SAC0～SAC8, it is selected by the column decoder YDEC.
Figure 5 is a subarray MCA22 in Figure 4, the sub-word driver portion adjacent thereto
WDG22, taken out WDG23 and a sense amplifier unit SAG22, SAG32, shows these internal configuration. Sabuare MCA22 the memory cell blocks MCT having the structure shown in FIG. 1 is formed by arranging in a matrix. Each memory cell block, as in FIG. 1, four word lines (e.g., WL00～WL03) and block select line (e.g., BWL0) is controlled by the data lines (e.g., DL0) and performs transmission and reception of signals . Word lines WL00~WL03, WL 10~WL 13, WL20~WL23, ... and a block selection / line BWLO, BWL 1, BW 2, ..., the sub-word driver unit WDG22, Sabuwa in WDG23 one de driver block SWDB, SWDA It is driven by either. Here, the sub-Wa de driver block STOA is a circuit for driving a two word lines, sub-word driver block SWDB is a circuit which performs also drives the block select lines in addition to the two Wado lines. Data line DL0, DL 1, DL2, DL3, ... is connected to one of the sense amplifiers SA in the sense amplifier unit SAG22, SAG3.
Configuration, as used herein, for the mouth © system is configured that called hierarchical Wado line configuration, Ri configuration der which are called multi-divided data lines configured for the column system, both in DRAM 2 Thus is an application of the structure that are generally used, by dividing the memory cell array into a plurality of subarrays, to shorten the line length of the word lines and data lines, thereby enabling high-speed operation there. Both sub-word Dora I bar portion WDG00~WDG74 and the sense amplifier unit SAG00~SAG83, except those located at the end, which is shared by the two subarrays, that have an area increase is suppressed.
Figure 6 shows a configuration example of a sub-Wa Dodo Rai bus blocks SWDB. In the figure, SWD0, SWD3 is a sub-word driver drives the word line WL0, WL3, respectively an NMOS transistor MW0 and PMOS transistors MW1, MW2. BSWD is the blanking-locking select line BWL driver, and a NMOS transistor MW3, MW5 a PMOS Trang register MW4, MW6. The sub-word driver block SWDB is selected by Meinwado line MWL and decodes the selectively drive Rowadoresu by mouth Udekoda. The main word line 丽 Mr. over subarrays are wired in metal layer of the upper layer is not used in Memorise Le. Further, Sabuwadodorainoku SWD0, SWD3 selection signal line FX0, FX3, FXOB, control signal lines BFX and power VB of FX3B block selection signal driver BSWD, VW, VR is provided on the sub-word driver unit.
Incidentally, the sub-word driver block SWDA in Figure 5, the sub-word driver block removes the block select line driver BSWD from the configuration of SWDB, be a configuration in which only two Sabuwadodo driver.
According 7, the operation of the sub-word driver of Figure 6: In FIG. 7 shows the case where Wa one word line WL0 is driven by the sub Buwadodoraiba SWD0.
During standby, the select signal line FX0 and Meinwado line MWL Wado line voltage VW for writing selection signal line FXOB has a standby Wa one word line voltage VB. Subword transistor MW0 is off state in the driver SWD0, Ri Contact transistors MW1 and MW2 are turned on, Wado line WL0 has a standby Wa one word line voltage VB. Further, in the block selection line driver BSWD, transistor MW3 and MW6 is turned off, the transistors Akira 4 and MW5 Gao down state, Proc selection line BWL has a read Wado line voltage VR: during operation first, the selection signal line FX0 rise in standby Wado line voltage VB, the transistor MW2 is turned off in the sub-word dry carbonochloridate SWD0. Further, the selection signal line FX0B, source read Wa word line voltage VR of the transistor MW0 is applied in Sabuwa within one de driver SWD0. Here, by Meinwado line MWL is standby Wa one word line voltage VB, the transistor MW1 is off in the sub-word driver SWD0, tiger Njisuta MW0 is turned on, Sabuwado lines SWL0 within read Wado line voltage VR It is driven.
Also within the block select line driver BSWD, transistor MW3 and MW6 ON APPLICATION transistors MW4 and MW5 is turned off. Here, the control signal BFX is by becoming a standby Wado line voltage VB, the block selection line BWL is driven in the standby Wado line voltage VB. When the control signal BFX returns to the read Wado line voltage VR, Plock select line BWL also return to the read word line voltage VR. Furthermore, by the selection signal line FX0B becomes the write word line voltage VW, Sabuwa one word line SWL0 is driven to write Wado line voltage VW. Thereafter, when the Meinwado line MWL back to the write Wado line voltage VW, the transistor MW1 is turned in the Sabuwado dry carbonochloridate SWD0, transistor hide 0 is turned off, the driving support Buwado lines SWL0 within standby Wado line voltage VB It is. Wa one word line voltage VW for writing selection signal line FX0, by the standby Wado line voltage VB of the select signal line FX0B, returns to the standby state.
As described above, in the configuration of FIG. 6, the driving of the word lines and block select lines to realize a memory cell operation shown in FIG. 2 can be realized. In this configuration, the selection of the sub-word driver of a selected block selection line driver, than performing the same Meinwado line Application Mr. requires less number of main word lines, increasing the pitch of the main word line for wiring on subarrays it can. By relaxing the wiring pitch, the yield is improved. Alternatively, it is possible to place such power lines between the main word lines, achieve high SZN and higher speeds.
Figure 8 shows a configuration example of the sense amplifier SA in FIG. To share a sense amplifier in the data line of the two sub-arrays, sense amplifier SA isolation transistor MSL, MSR is provided, consisting of three and the pre-charge circuit PC includes a PMOS transistor, two NMOS transistors reference a signal generator RG, two NMOS transistors and the latch type differential amplifier SAL consisting of two PMOS transistors, output line pair consists of two NMOS transistors controlled by a column selection line YS I0T, and I0B the is composed of a column gate YG for connection. Transistors of the reference signal generator RG is in so that approximately half of the current flows in the signal current of the memory cell blocks, defining the gate width and gate length.
According 9, the operation of the sense amplifier SA illustrated in FIG. First, Purichiya - by di control signal PCB becomes high level VDL, PM_〇 S transistor of the precharge circuit PC is turned off, the node in the sense amplifier DLT, DLB is floating. Also, share one de control signal SHR is by the mouth Ureberu VSS, transistor MSR is turned off, the sense amplifier from the data line of the adjacent non-selected Sabuare are separated. Here, the signal current is read from the memory cell blocks as shown in FIG. 2, the data line DL and the node DLT is discharged. Accordingly, the reference signal control signal RBG is by a high level, transistors in the reference signal generator RG discharges the node DLB.
After the voltage difference required to sense appeared to node DLT, DLB, shared control signal SHL as the low level VSS, and turns off transistor MSL, it separates the data lines DL from the node DLT, the reference signal control signal RBG the in the low level, to turn off the reference signal onset raw unit RG. Then, the common source CSN to the low level, by the differential amplifier SAL, node DLT, to positive feedback amplification of the high level VDL and mouth Ureberu VSS respectively DLB. This sense operation is completed.
Although not shown in FIG. 8, Ri by to the column select line YS to the high level at this two, to turn on the column gate YG, node DLT, DLB and output line pairs I0T, signals between I0B carry out the exchange. Also, return the shared control signal SHL high enough voltage VPP than the high level VDL, turn on the transistor MSL, to write-out re-written from the node DLT to the data line DL. The voltage VPP can be the same as the standby Wado line voltage VB. At the time of reset, first to return the common source CSN to the high level VDL, stop the operation of the differential amplifier SAL. Then, to return the pre-charge control signal PCB to the low level, the node DLT, are precharged to a high level VDL and DLB. Also, return the shared control signal SHR to the high voltage VPP, reconnecting the data lines of the adjacent non-selected Sabuare to the sense amplifier.
In the above operation, the reference signal that has to generate a current flowing from the transistor. Therefore, node DLT, the voltage difference between DLB spreads with time, a large tie Mindamajin. At the start of operation of the latch type differential amplifier SAL, by separating the data line DL from the sense amplifier SA, thereby preventing the difference in the load capacitance is generated by the data line capacitance, high-speed amplifying operation by reducing the load capacitance It is to allow. State The memory cell block MCT shown in FIG. 1, because having an amplifying function in a memory cell, it can operate without providing a sense amplifier for each data line, that latch the data in this way sense amplifier by the, synchronous memory can be implemented as shown in FIG. 3 to operate the column system at high speed.
Figure 1 0 shows an example of another memory cell arrangement according to the invention. As described in the literature 3, it is feature of using a low leakage transistors conformation. Similar to the memory cell configuration shown in FIG. 1, and four memory cells MC0~MC3 one of the memory cell blocks MCB. Each memory cell includes a PMOS transistor M0 for writing, and the NMOS transistor Ml for reading consists non-select transistor motor M2 Prefecture, the PMOS transistor M0 for the write, are made of a low leakage transistors conformation.
Further, instead of the block selection transistors MB in FIG. 1, is provided a block selection cell BMC, like the memory cell MC0 to MC3, block select cell BMC is writing PMOS transistor BM0, read NMOS transistors BM1, unselected is constituted by use NMOS transistor BM2, it is controlled by the block select line BWL. This is, in the manufacturing process of the memory cell structure shown below, is because the easy to make towards the same configuration as relatives also memory cell block selection transistor.
Normal operation, ie read and write crowded operation, like the memory cell configuration shown in FIG. 1 is performed as shown in FIG. However, keep in so that the read transistor BM 1 Gao off the block select cell BMC in Wado line voltage VR for to read out the block select line BWL. Therefore, in this memory cell configuration, it is necessary operation for addition to deciding the storage Roh one de BN in the block selected cell BMC normal operation is carried out as shown in FIG 1.
First, the data lines DL from the normal precharge voltage VDL, and the low level VSS. Next, the word line voltage VR for reading the block selection line BWL, and the write word line voltage VW. Thus, the storage node BN in the block selected cell belly C, even have become a voltage AV of raised from the low level VSS due leak, it is returned to the mouth © level VSS. Then, after returning to the word line voltage VR for reading the block selection lines BWL, return data line DL in the precharge voltage VDL. By controlling the data line DL and the block selection line BWL in the order described above, it is possible to prevent useless charging and discharging of the storage node Betanyu.
In the configuration example of the sub Wa de driver block SWDB shown in FIG. 6, by temporarily Wado line voltage VW and to Rukoto write the voltage of the power supply line read Wa word line voltage VR is applied, the block select line Doraiba BSWD drives the word line voltage VW for writing block selection lines B WL regardless of Meinwado line MWL. In the sense amplifier SA shown in FIG. 8, the pre-charge control line PCB as a high level VDL, turn off the precharge circuit PC, the reference signal control line RBG, even high level VDL RBT, 2 pieces of the reference signal generator RG if the transistors in both oN, thus c possible data lines DL in the mouth Ureberu VSS, without the structure of the sub-word driver block SWDB and the sense amplifier SA to the complex, can be realized operation shown in FIG. 1 1. Moreover, since the make this operation collectively in a number of memory cell blocks in the memory array, over one heads can not perform a normal operation of the memory array is small.
Next, an example of the structure of the memory cell blocks MCB shown in FIG. 1 0. Figure 1 2 shows the layout. In this figure, FL is the active region pattern, FG is polysilicon con working pattern, SG data line pattern, TG word line pattern for determining the area of ​​the node N in FIG. 1 in 0, BLCT data line contactor preparative pattern it is. The patterning of these patterns, known light Li c Figure 1 3 which lithography can be used are A-A shown in FIG. 1 2 'cross section of the portion along the line (hereinafter, A-A' referred to as a cross section). Similarly, FIG. 1. 4 'portion of the cross section (hereinafter along the line, B-B' B-B is referred to as a cross section), Fig. 1 5 is part of a section along the line C-C '( hereinafter, C - shows the C 'is referred to as a cross section). In these figures, a semiconductor substrate 100, 101 is p-type Ueru, 102 field isolation oxide, reads out and transistor Ml gate oxide film 103, 104 is p-type as the node N of FIG. 1 in 0 policy silicon, 105 a lower nitride film transistor M0 of FIG. 1 in 0, the intrinsic polysilicon con which no impurity is doped 106, 107 the upper nitride layer of the transistor M0, the source of the transistor M0 of FIG. 1 in 0 108 p-type polysilicon to be a Z drain terminal, 110 is an n-type diffusion layer, 111 is an interlayer oxide film, 112 is a data line contactor DOO, 113 data lines, 114 a layer between oxide film, 115 a gate of the writing transistor M0 oxide film, 116 is that Do a word line n-type polysilicon Con, 118 an interlayer oxide film.
As shown in FIG. 1 4, the three transistors of the memory cell, by constituting an integral in conformation can be a small area. Writing transistor M0 is vertical p-type polysilicon Con 104, 108 serving as a source / drain terminal, which sandwiched between intrinsic polysilicon con 106 serving as a channel region, a source Z drain path semiconductor substrate perpendicular direction is formed a structure, a gate oxide film 115, and the n-type polysilicon configuration 116 or Ranaru gate is formed on the side wall. During the p-type polysilicon Con 104, 108 and intrinsic polysilicon 106, Ri by the fact that across the nitride film serving as each diffusion Baria film, diffusion of Akuseputa to intrinsic polysilicon 106 is prevented, intrinsic polysilicon the impurity concentration in sufficiently low. Thus, the entire channel region during off can be realized fully depleted transistor to be depleted, it is possible to reduce the leakage current.
Reading transistor Ml and the unselected transistor M2 are connected in parallel, the source and drain can be made common. These transistors Ml, M2, by separately forming the gate, can be formed without the isolation region, the planar area decreases. The transistor M2 is 1 4 and consists on both sides of the transistor Ml as shown in, etc. mask misalignment, even offset gate portion of the transistor Ml is the position relative to the active region, the transistor M2 the gate width of the total small amount of change. Therefore, it is not necessary take a large alignment margin: The read for Tiger static Ml and the unselected transistor M2, since together adjacent, the electric field from both the channel forming gate contributes.
Although not shown in the equivalent circuit of FIG. 1 0, between the polysilicon 104 and 1 16 is only the gate oxidation film 1 15, the force Ppuringu capacitance is formed between the Wado line and the storage node N. The coupling capacitance when the word line driving, the voltage of the storage node N fluctuate, no this problem if determined the threshold voltage of each transistor in the memory cell considered. Rather, it raised voltage of the storage node N during non-selection, since the direction in which reading out and transistor is turned on, lowers the resistance of the non-selected memory cell to be the path of the read signal currents, the effect of increasing the signal current.
The semiconductor substrate 100 may be n-type in p-type, may be a so-called triple Ueru structure in which a deep © El of n-type under the p-type Ueru 101. And Uyuru outgoing Shi transistor Ml and the unselected transistor M2 reading memory cells, in Ueru of MOS Trang register of the peripheral circuit, depending on whether separate the voltage, is likely various Ueru configuration. For example, in the configuration of a memory array portion as shown in FIG. 4, the case of using the sub-word driver shown in FIG. 6, p-type Ueru as a Bode I of the NMOS transistor MW0 in the sub-word driver the following write Wado line voltage VW must be in, n-type Uweru as the body of the PMOS transistors MW1, MW2 must to wait for the word line voltage VB than on. Therefore, as their voltage is not applied to the body of the transistor of the peripheral circuit, the use of triple Ueru is effective in terms of speed. According 2 5 1 6, explaining the higher manufacturing E of the memory cell structure shown in FIGS. 1-4 and FIG 5. To create a peripheral circuit simultaneously, steps not shown, formation or n-type Ueru as a PMOS body For example, any time the line also including the formation of p-type diffusion layer.
First, as shown in FIG. 1 6 and 1 7, a p-type Uyuru 101 formed on the semiconductor substrate 100, an element isolation oxide film 102. In this state, B-B 'cross section and the C-C' cross-section have the same structure. To reduce the element isolation region in a known trench isolation method, it is effective to allow vertical oxide film surface to the base plate 100. Specifically, digging a trench by etching the p-type Uniru 1 01 in the active region pattern FL, which backfilled with oxide film is planarized by chemical mechanical 'poly Sshumento (CMP). Next, as shown in FIG. 1 8, to remove such contamination of the surface due to ion implantation, to form a gate oxide film 103. Then, p-type polysilicon Con 104, nitride layer 105, an intrinsic port Rishiri Con 106, nitride layer 107, p-type polysilicon con 108, the nitride film 109, are sequentially deposited by a known vapor phase length method (CVD). These are etched in polysilicon con working pattern FG. B- B 'cross section, is covered with the pattern FG, remain the layers were sedimentary. On the other hand, as shown in FIG. 1 9, no pattern FG C - C 'cross-section these are removed. Thereafter, using a well-known ion implantation method, to form formed an n-type diffusion layer 110. At this time, it is also possible to Shirisai de the n-type diffusion layer. Thus, although the number of steps is increased, it reduce the resistance of the diffusion layer. By Shirisai de reduction, since lowered the resistance of the source line SL in Fig. 1 in 0 can be increased signal current, to suppress the change in signal current due to pattern-dependent memory cell to be selected in the same Wa lead wire effective it is.
Next, as shown in FIGS. 2 0 and 2 1, buried interlayer oxide film 11 1, to flattening by CMP. Subsequently, by etching open connection holes with data line contactor DOO pattern BLCT, formed lump padded with metal such as barrier metal and tungsten such Chitan'nai stride, the data line contactor DOO 112. The data line contactor DOO, also be formed in the policy silicon, by using a metal, resistance can be reduced, thereby increasing the out signal current read. Incidentally, when CMP, a serve as a nitride film 109 gas Totsupa shown in FIG. 1 8, the remaining nitride film 109 is removed.
Next, as shown in FIG. 2 2 and 2 3, to deposit a metal wiring layer 113 and the interlayer oxide film 114 serving as a data line in CVD. Then, the data line pattern SG, etched until the gate oxide film 103. Thus, by polysilicon con 104 in data line pattern SG, 106, 108 is also etched, the storage node N which is the source Z is the drain terminal of the read transistors Ml gate of the write transistor M0, a self-aligned manner It can be formed.
Furthermore, as shown in FIG. 2 4, to form a write transistor M0 and. 5 to 1 0 nm about a thin oxide film 115 serving as a gate one gate oxide film of the non-select transistors M2 in CVD, the word line the polysilicon Con layer 116 is deposited by CVD. At this time, it is also possible to deposit the metal on the polysilicon con layer 116. Thus, although the number of processes increases, and reduce the resistance of the word line, it can achieve high-speed operation. Then, etching the word line pattern TG. B- B 'cross section, is covered with the pattern TG, remain polysilicon down layer 116 is deposited, as shown in FIG. 2 5, C-C no pattern TG' in cross-section is removed. Thereafter, an interlayer insulating film is deposited 118, the structure shown in FIGS. 1-4 and FIG. 1 5 is realized.
Memory cell arrangement according to the invention is not limited to the structure shown in Example 2, is another memory cell structure possible. In this embodiment, the memory cell structure of the same Fig. 1 0 Example 2, A shows the layout and FIG 3 as shown in FIG. 1 2 - and A 'cross section. It was but connexion, B - explained B for 'cross section and the C-C' cross section.
2 6 B- B 'cross section, FIG. 2 7 C - C' shows a cross-section. As in Example 2, 100 denotes a semiconductor substrate, 101 denotes a p-type © Le, 102 field isolation oxide, 103 is a gate oxide film of the read Tiger Njisuta Ml, 104 and nodes N in FIG. 1 in 0 p-type polysilicon Con, 105 lower nitride film transistor M0 of FIG. 1 in 0, 106 intrinsic polysilicon Con, 107 upper nitride layer of bets transistor M0, 108 has a source Bruno drain terminal of the transistor M0 of FIG. 1 in 0 p-type polysilicon Con made, 110 n-type diffusion layer, 112 is a data line contactor DOO, 113 data lines, 1 14 interlayer oxide film, 115 is gate one gate oxide film of the write transistor M0, 116 is a word line n-type polysilicon Con made, 118 denotes an interlayer oxide film.
In the structure of this embodiment, by etching so that the semiconductor substrate convexly, the non-select transistor M2 is that characteristic that is configured on the side wall. Thus, without increasing the planar area, the gate width of the non-select transistor M2 can be sufficiently large. Structure of this embodiment can be realized by the following production process. First, as in Example 2 coaxial, as illustrated in FIG. 2 1 figures 1-6, form up data line contactor sheet 1 12. Then, as shown in FIG. 2 8 and 2 9, after the metal wiring layer 1 13 and the interlayer oxide film 114 serving as a data line is deposited by CVD, the data line pattern SG, deep element isolation oxide than the gate oxide film 103 etched to the middle of the film 102. At this time, n-type diffusion layer 1 10 not covered with the data line pattern SG is removed.
Next, as shown in FIG. 3 0 and 3 1, a gate oxide film 1 15 is formed by CVD, is deposited by CVD a polysilicon con layer 1 16 serving as Wa lead wire, Wado line pattern Ichin TG in the E Tsu quenching. Further, the n-type diffusion layer 1 17 by ion implantation, so as to continuous with the portion of the n-type diffusion layer 1 10 formed in FIG. 9, again formed. Thus, the area of ​​the source line which is not covered with the data lines butter over emissions SG may ensure continuity. Thereafter, an interlayer insulating film is deposited 118, the structure shown in FIG. 2 6 and 2 7 is achieved.
3 2 illustrates another configuration example of a memory cell block according to the present invention. This embodiment is not provided with a non-select transistor M2 is used in the memory cell structure shown in FIG. 1 0, a method of performing an operation by the force Ppuringu capacitance between the storage Roh one de and Wado line. Also in this embodiment, similarly to the memory cell configuration shown in FIG. 1 0, and four memory cells MCC0～ MCC3, in a block selected cell BMCC the same structure as the memory cells constitute one memory cell block MCCB ing. Each memory cell includes a write PM_〇 S transistor motor M0, constitute a memory cell in the NMOS transistor Ml for reading, and a coupling capacitor C2. Here, the PMOS transistor M0 is for writing, are made of a low leakage transistors steric structure. Again What using the block selection cell thigh CC, similarly to Embodiment 2, because the easy to make towards the same configuration as Memorise Le than only the block select transistor.
Next, the operation of the memory cell structure of the present embodiment. Incidentally, it described as selecting the memory cells connected to the word line WL1.
Normal operation is carried out as shown in FIG 3. Wado line WL1, the block control of the selection line BWL and the data line DL is similar to FIG. 2, that is the voltage is applied from the word line WL1 to the storage node NC by force Ppuringu capacitor C2 is different from FIG. 2 .
In the standby state, the block selection line BWL is a read Wa one word line voltage VR, the transistor BM1 in the block selected cell BMCC is off, the read transistor Ml of the memory cell MCC0 data lines DL It is separated from. On the other hand, neither Wa word line WL0~WL3 is a standby word line voltage VB of the high level, the storage node NC is lifted by the force Ppuringu capacitor C2 in each main Moriseru, depending on the information stored not, read transistor Ml is in the oN state.
In operation first, one of the word lines, in this case the word line voltage VR for reading the WL 1, selects the memory cell MCC 1. In the selected memory cell, the voltage of the storage node NC is lowered by coupling-ring capacity C2, the information stored or read out by transistor Ml is in either the on state is in the OFF state is determined. In other memory cell, the word line is kept waiting for the word line voltage VB, the read transistor Ml is kept in the ON state. Here, by setting the block selection lines BWL in standby Wa one word line voltage VB, in a block selected cell BMCC, voltage Roh one de BNC is lifted by the force Ppuringu capacity BC2, transistor BM1 is turned on. As a result, information stored in the memory cell MCC1 is '1' at a force '0' at a force Koyori, whether or not a current to the data line DL Karaso over source line SL flows is determined. By detecting this current, it can determine the information memory cell selected is stored.
After completion of the sensing operation, returned to the word line voltage VR for reading the block selection lines BWL, lowering the voltage of the node BNC by the force Ppuringu capacity BC2, it turns off the transistor thigh 1, to cut off the current path. Then, you and Wado line voltage VW for writing selection Wado line WL1. Thereby, in the selected memory cell MCC1, transistor M0 is turned on for writing, the voltage of the data line DL is Shirushika 卩 accumulation Roh one de N, information is written into the memory cell. By returning the selected word line WL1 to the standby Wado line voltage VB, selected Memorise in the Le MCC1 with the writing transistor M0 is turned off by the coupling capacitance C2 storage node NC is lifted, the write operation is completed.
However, in the same manner as in Example 2, the read transistor BM1 in the block selected cell BMCC block select line BWL is in read Wado line voltage VR is kept set to be off. Therefore, in the control shown in FIG. 1 1, previously set the node BNC block selected cell BMCC.
The use of force Ppuringu capacity as in this embodiment, it is possible similar operation without using the non-select transistor such as that used in Example 3 from Example 1. Control is similar to Example 2, the structure of a memory Example 1 can urchin configuration.
Next, an example of the structure of the memory cell block in this embodiment. Figure 3 4 shows a layout. Similar to FIG. 1 2, FL active region pattern, FG is polysilicon con working pattern, SG data line pattern, TG denotes a word line pattern, BLCT are data lines co Ntaku preparative pattern.
A In this layout - A 'cross-section is the same as the structure shown in FIG 3. 3 5 B B 'cross section, FIG. 3-6 C - C' shows a cross-section. Reference numeral these figures also the same as that of FIG. 1 three et Figure 1 5, 100 denotes a semiconductor substrate, 101 denotes a p-type Ueru, 102 the element isolation oxidation film, 103 a gate oxide film of the reading transistor Ml , 104 p-type polysilicon configuration as the node NC in FIG 2, 105 3 2 in the lower nitride film transistor M0, the intrinsic polysilicon Con 106, 107 the upper nitride layer of the transistor M0, 108 FIG. 3 p-type polysilicon to be a source Z drain terminal of the tiger Njisuta M0 in 2, 1 10 n-type diffusion layer, the interlayer oxide film 111, 112 is a data line contactor DOO, 1 13 data lines, 114 denotes an interlayer oxide film , the gate one gate oxide film of the write transistor M0 115, 116 are n-type poly silicon as a Wado line, 118 denotes an interlayer oxide film.
Structure of this embodiment can be realized in the manufacturing process as described with reference to FIG. 2 to 5. FIG 1 6. A coupling capacitor C2, automatically configured on the sidewall of the polysilicon 104 serving as a storage node NC. Capacitance value of the capacitance C2 can be adjusted by may varying thickness during deposition of polysilicon 104. In Reiauto shown in FIG. 3 4, unlike FIG. 1 2, the common areas of Wa lead wire patterns TG and the active region pattern FL, and One covered by the data line pattern SG. Therefore, as shown in cross section B-B 'in FIG. 35, the polysilicon 104 which is the gate of the read transistor motor Ml it is, extends to the isolation oxide film 102 on. This is to reduce the gate capacitance of the read transistor Ml, to increase the influence of the coupling capacitance C2. The position of the gate in the misalignment between the mask is also offset with respect to Chiyane Le portion, variation of the gate capacitance is suppressed.
Ku Example 5>
3 7 illustrates yet another example of a memory cell arrangement according to the invention. The data lines, it is a feature that separates at a writing and reading. Memoriserubu lock MCB is similar to FIG. 1 0, but is composed of four memory cells MC0~MC3 and block select cells BMC, is connected to the write data line DLW and the read data lines DLR the point is different.
Normal operation is carried out as shown in FIG 8. Incidentally, it described as selecting the memory cells connected to the word line WL 1. Wado lines WL 1, control of proc selection line BWL is the same as that of FIG. Similar to Example 2, when the block selection line BWL is Wado line voltage VR for out readings are read transistor data BM1 in the block selected cell kept as turned off. Therefore, in the control shown in FIG. 1 1, previously to confirm the potential of the node BNC of the probe-locking the selected cell BMC.
In the standby state, Proc select line BWL is a read Wado line voltage VR, the transistor BM 1 and BM2 is off in a block selected cell BMC. On the other hand, none of the Wado lines WL0 to WL3, and the standby word line voltage VB of the high level, regardless of the information stored, the non-select transistor M2 is in the ON state.
In operation first, one of the word lines, in this case the word line voltage VR for reading the WL 1, to select a memory cell MC 1. In the selected memory cell, the non-select tiger Njisuta M2 is turned off, conduction and non-conduction of the read path is determined by the read transistor Ml. In other memory cell, the word line is kept waiting for the word line voltage VB, non-select transistor M2 maintains an on state.
Here, by the proc selection line BWL in standby Wado line voltage VB, at block selected cell BMC, transistor BM2 is on. As a result, selected according to the information of the memory cell MC1, whether from the readout data lines DLR through the memory cell blocks MCB current flows to the source line SL is determined. By detecting this current, it can determine the information selected memory cell stores.
After completion of the sensing operation, it returned to the word line voltage VR for reading the block selection lines BWL, turn off the door transistor BM2, to cut off the current path. Further, according to the detection result of the read data lines DLR, drives the write data line DLW. Then, the word line voltage VW for writing the selected word line WL1. Thus, the selected memory cell MC within 1, transistor M0 is turned on for writing, the voltage of the write data line DLW is Shirushiryoku D to storage node N, the information is written into the memory cell MCI. By returning the selected word line WL1 to the standby Wa one word line voltage VB, the write transistors M0 is turned off in the selected memory cell MC1, the write operation is completed.
In this operation, unlike the operation shown in FIG. 2, since the read-rewrite operation is not inverted information notes Riseru, it is easy to control. Also, small capacity because the transistor Ml is not connected for writing to the read data lines DLR, operation can be realized out fast read. Furthermore, by keeping the precharge voltage of the write data line DLW low level VSS, it is possible to prevent the voltage of the storage node N in Sabusure Sshorudo current of the writing transistor M0 during standby increases.
Note that although the same voltage amplitude of 3 for 8 reads the data lines DLR and the write data line DLW, it is also possible to separate voltage amplitude. Thus, the degree of freedom of the threshold setting of the transistor in a note Riseru increases.
Next, an example of the structure of the memory cell blocks. 3 9 shows the layout. In FIG. 3 9, FL active region pattern, FG polysilicon machining patterns, SG data line pattern for forming the write data line DLW, TG is Wado line pattern, LCNT the contactor DOO pattern, MIL is a metal interconnection pattern when you forming a read data line DLR. The contactor DOO pattern LCNT and metal wiring patterns MIL may be made of the same layer as the layer to be used in the form of a peripheral circuit, not increased as prepared E.
4 0 indicates 'cross section (Alpha-Alpha in section along the line' section) A-A of FIG. 3 in 9, as FIG. 4. 1 beta B 'cross section, FIG. 4 2 C-C' cross section the shows. Similar to FIG. 1 through FIG. 5 1 3, 100 denotes a semiconductor substrate, 101 is ρ type Ueru, 102 field isolation oxide, 103 a gate oxide film of the read transistor Ml, 104 a node N in FIG. 3 7 become p-type polysilicon down, 105 3 7 in the lower nitride film transistor M0, the intrinsic polysilicon Con 106, 107 the upper nitride layer of the transistor M0, 108 is the source Z drain of transistor M0 in Fig 7 p-type polysilicon configuration as the terminal, 110 is an n-type diffusion layer, 1 1 1 interlayer oxide film, 113 is a metal interconnection serving as a data line for write-out write, 1 14 interlayer oxide film, 115 is writing Trang register M0 a gate oxide film of 1 16 n-type polysilicon configuration of the word line, 118 in the interlayer oxidation film, 119 contactors DOO, 120 is a metal interconnection serving as read data lines. The memory cell structure of the present embodiment, since there is a contactor bets 119 pulled to Metall wiring 120 of the read data lines DLR from the diffusion layer 110, peak Tutsi data lines than in Example 2 are greatly summer. Utilizing this, expand the width of the active region pattern FL, since by increasing the gate width of the non-select transistors M2, can increase the signal current by reducing the on-resistance. Further, the contactor bets 119 provided on the diffusion layer 110 of the source line SL, and are connected to metal interconnect 120. By lining the metal wiring 120 where an additional layer of Metall wiring not shown, it can be increased signal current to reduce the resistance of the source line SL. For example, it can be wired in the same metal wiring layer as Meinwado line MWL Ru used for control of the sub-word driver shown in FIG.
The manufacturing process of the memory Serupu locking structure of this embodiment will be described with reference to FIG. 5 4 4 3. First, as shown in FIG. 4. 3 and 4 4, the p-type Uyuru 101 formed on the semiconductor substrate 100, an element isolation oxide film 102.
Next, as shown in FIG. 4 5 and 4 6, to form a gate oxide film 103, p-type policy silicon 104, nitride layer 105, an intrinsic polysilicon 106, nitride layer 107, p-type polysilicon 108, nitride film 109, are sequentially deposited. These are Etsu quenching with polysilicon con working pattern FG. Then, by using a well-known ion implantation method, form an n-type diffusion layer 1 10.
Next, as shown in FIG. 4 7 and 4 8, buried interlayer oxide film 111 and flattening by CMP. Incidentally, when CMP, a nitride film 109 serves as a stop, the remaining nitride film 109 is removed. Unlike Example 2, where a need to form a data line contactor preparative les. However, when used as a wiring metal wiring layer 1 13 in the peripheral circuit performs the contactor bets formation step in the peripheral circuit region.
Next, as shown in FIG. 4. 9 and FIG. 5 0, the metal wiring layer 113 and the interlayer oxide film 114 serving as a write data line is deposited with CVD, the data line pattern SG, to Etsuchingu until the gate oxide film 103. Then, as shown in FIG. 5 1 and 5 2, the write preparative transistor M0 gate oxide film 115 of a non-selected transistor M2 is formed by CVD, deposition by CVD a polysilicon layer 116 serving as Wa lead wire and, further Etchi in Wado line pattern Ichin TG, as shown in FIG. 3 and FIG. 5 4, an interlayer insulating film is deposited 1 18 opens the connection hole by etching with contactors preparative pattern LCNT, Chitan'nai tri Donado embedded in the metal, such as the barrier metal and tungsten, to form a contactor door 1 19. The data line contactor DOO, also be formed of polysilicon can be reduced more resistance to the use of metal.
Then, depositing a metal wiring layer 120, by etching a metal wiring pattern Ml Mr, the structure of FIG. 3 7 and 3 8 is realized.
5 5 illustrates another layout for realizing the memory cell configuration shown in FIG 7. Layout is only different structure and manufacturing process is similar to the example described above. This figure shows a magnification of a memory cell block of FIG 9. 3 9 the same way, FL active region pattern, FG is polysilicon con working pattern, SG data line pattern for forming the write data line DLW, TG in Wado line pattern, LCNT the contactor DOO pattern , MIL is a metal interconnection pattern for forming the read data lines DLR.
In Reiauto in FIG 9, the contactor bets pattern LCNT of the read data lines DLR, it is provided (right side in the figure) the same side of the pattern SG write data line. Therefore, the large summer pitch of the data lines is constrained. In order to alleviate this, the layout shown in FIG. 5 5, a contactor bets pattern LCNT, (right and left in the drawing) alternately to pattern SG write data line arranged, the data line pitch It is made smaller. Contactors DOO pattern LCNT is a staggered so as not to face. Therefore, when contactor preparative pattern LCNT the space larger force S of the word line pattern TG adjacent areas, the number of memory cells per memory cell block is large, in the case of 8 or more for example, such Reiau Bok it is the area of ​​the memory cell blocks becomes small. Also in the layout shown in FIG. 5 5, 1 or so to about four data lines read, it can to bring can pull the metal wire takes the contactor preparative diffusion layer 1 10 of the source line, the resistance of the source line It can be reduced. Industrial Applicability
The present invention can be realized a memory cell having an amplifying effect with high integration, it is useful to realize a semiconductor device having a memory of a small area that operates at a high speed at a low voltage c
1. And the data lines,
A first Wado lines crossing the data lines,
A second Wado lines crossing the data lines,
A first memory cell provided at an intersection between the data line and the first Wado line,
In a semiconductor device having a second memory cell provided at an intersection between the data line and the second word line,
A first transistor comprising a signal path at the time of writing,
A second transistor as a signal path during reading,
And a first storage node for holding data by accumulating charges, the second memory cell,
A third transistor as a signal path at the time of writing,
A fourth transistor comprising a signal path during reading,
And a second storage node for holding data by accumulating charges, path of the read signal to the data line from said fourth transistor, a semiconductor device which comprises the second transistor .
The gate of the first transistor being connected to said first Wado line, the gate of the third transistor is a semiconductor device which is characterized that you are connected to the second Wado line.
One of the source / drain terminal of the first transistor being connected to the data line, the other is connected to the first storage node,
The third one of the source / drain terminal of the transistor of the connection to the data line, and the other semiconductors apparatus characterized by being connected to the second storage node.
The first transistor and the second transistor are of opposite conductivity type to each other,
Wherein a said third transistor and said fourth transistor of opposite conductivity type to each other.
The first memory cell, the source and the drain of the second transistor, further comprising a fifth transistor having a source and drain connected respectively, said second memory cell, the fourth transistor the source and the drain, and wherein a and this further comprising a sixth transistor whose source and drain are respectively connected.
Said second transistor and the fifth transistor of the same conductivity type, the semiconductor device above the fourth transistor and the sixth transistor, which is a same conductivity type.
Gate one bets the fifth transistor being connected to said first Wa one word line, the gate of the sixth transistor semiconductor device which is characterized that you are connected to the second Wado line.
Transistor of the fifth period of the first transistor is conducting is rendered non-conductive,
The said first transistor in the fifth period the transistor is conducting in becomes non-conductive,
Transistor of the sixth period of the second transistor is in conduction becomes nonconductive,
The said second transistor is a sixth time period the transistor is conducting semiconductor device characterized by comprising a non-conductive.
The fifth transistor is provided on the side wall of said second transistor, a semiconductor device in which the sixth transistor, characterized in that provided on the side wall of the fourth transistor.
The semiconductor device according to 1 0. Claim 1, wherein,
It said first memory cell further comprises a first capacitance between the first Wado line and the first storage node,
It said second memory cell further, a semiconductor device and having a second capacitance between said second Wado line and the second storage node.
The semiconductor device according to 1 1. Claim 1, wherein,
A block select line crossing the de one data line,
Further organic and a seventh transistor having a gate connected to the proc selection line,
Path of the read signal from said second transistor to the data line includes the seventh transistor,
The path of the fourth read signal from the transistor to the data line, the semiconductor device characterized by including the seventh transistor.
1 2. And the write data line,
And the read data line,
A first Wado lines crossing the data lines and the read data lines for the write,
A second Wado lines crossing the data lines and the read data lines for the write,
A first Memorisenore provided at intersections between the write data line and the first Wado line,
In a semiconductor device having a second memory cell provided at an intersection between the write data line and the second Wado lines, the memory cells of the first l,
And a second storage node for holding data by accumulating charges, ROUTE of the read signal from the fourth transistor to the read data line, and characterized by including the second transistor semiconductor device.
The semiconductor device according to 1 3. The first two terms claims,
The write data line and the read data lines, wherein a are formed in different wiring layers.
The semiconductor device according to 1 4. The first three terms claims,
The read data lines to a semiconductor device characterized in that it is formed of a wiring layer above the wiring layer of the write data line.
1 5. Te semiconductor device odor according to any one of Claims first term - the first four terms,
The first transistor and the third transistor, a semiconductor device characterized by each of the source / drain path is formed in a direction perpendicular to the semiconductor substrate surface.
The semiconductor device according to 1 6. First 5 wherein the claims,
The first Wado line passes through the top of the source terminal and the drain terminal element of said first transistor,
The second Wado line semiconductor device characterized by being arranged to pass through the upper portion of the source terminal and the drain terminal terminal of the third transistor.
1 7. Each claims range semiconductor device smell the first transistor and the third transistor according to any one of the items 1 to 1 4 of the, first between the source pin and channel region the first diffusion barrier layer, a semiconductor device and having a second diffusion barrier layer between the drain terminal and the channel area.
1 8. Te semiconductor device odor according to any one of Claims first term - the first four terms,
The channel region of the first transistor and the third transistor, a semiconductor device characterized by being formed by port Rishirikon.
The semiconductor device according to 1 9. The first 7 wherein the claims,
The polysilicon, and wherein a is intrinsic polysilicon.
2 0. Te semiconductor device odor according to any one of Claims first term - first item 9,
In synchronization with an external clock, it captures the address and command, wherein a transmitting and receiving data.
PCT/JP2000/001953 2000-03-29 2000-03-29 Semiconductor device WO2001073846A1 (en)
PCT/JP2000/001953 WO2001073846A1 (en) 2000-03-29 2000-03-29 Semiconductor device
US10/239,417 US6570206B1 (en) 2000-03-29 2000-03-29 Semiconductor device
US10/239,417 A-371-Of-International US6570206B1 (en) 2000-03-29 2000-03-29 Semiconductor device
US10/408,221 Continuation US6677633B2 (en) 2000-03-29 2003-04-08 Semiconductor device
WO2001073846A1 true WO2001073846A1 (en) 2001-10-04
ID=11735846
US (1) US6570206B1 (en)
WO (1) WO2001073846A1 (en)
JPH03224265A (en) * 1990-01-30 1991-10-03 Toshiba Corp Nonvolatile semiconductor memory device and manufacture thereof
EP0224213A3 (en) * 1985-11-22 1987-10-28 Nec Corporation Semiconductor memory device
JP3350045B2 (en) 1990-10-11 2002-11-25 株式会社日立製作所 A semiconductor memory device
2000-03-29 US US10/239,417 patent/US6570206B1/en not_active Expired - Fee Related
2000-03-29 WO PCT/JP2000/001953 patent/WO2001073846A1/en active Application Filing
NAKAZATO,K. ET AL: "Silicon stacked tunnel transistor for high-speed and high-density random access memory gain cells", ELECTRONICS LETTERS, vol. 35, no. 10, 13 May 1999 (1999-05-13), pages 848 - 850, XP002929060 *
SHUKURI,S.ET AL: "A Semi-Static Complementary Gain Cell Technology For Sub-1 V Supply DRAMS's", IEEE TRANSACTIONS ON ELECTRON DEVICES,, vol. 41, no. 6, June 1994 (1994-06-01), pages 926 - 931, XP002929059 *
JP2013048007A (en) * 2009-10-30 2013-03-07 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2013021345A (en) * 2009-11-06 2013-01-31 Semiconductor Energy Lab Co Ltd Semiconductor device
TWI556236B (en) * 2009-11-27 2016-11-01 半導體能源研究所股份有限公司 Semiconductor device
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