Source: https://patents.google.com/patent/US9983659B2/en
Timestamp: 2019-07-22 09:03:06
Document Index: 669672605

Matched Legal Cases: ['Application No. 201180055923', 'Application No. 201180055923', 'application No. 11', 'Application No. 112011103193', 'Application No. 2013', 'Application No. 2013', 'Application No. 10', 'Application No. 201180055923', 'Application No. 201610029935', 'Application No. 104144235', 'Application No. 104144234', 'Application No. 100134148', 'Application No. 1306874', 'Application No. 1601963', 'Application No. 1602733', 'Application No. 1602734']

US9983659B2 - Providing per core voltage and frequency control - Google Patents
US9983659B2
US9983659B2 US14/966,273 US201514966273A US9983659B2 US 9983659 B2 US9983659 B2 US 9983659B2 US 201514966273 A US201514966273 A US 201514966273A US 9983659 B2 US9983659 B2 US 9983659B2
US14/966,273
US20160098078A1 (en
2014-12-15 Priority to US14/570,100 priority patent/US9348387B2/en
2015-12-11 Priority to US14/966,273 priority patent/US9983659B2/en
2016-04-07 Publication of US20160098078A1 publication Critical patent/US20160098078A1/en
2018-05-29 Publication of US9983659B2 publication Critical patent/US9983659B2/en
This application is a continuation of U.S. patent application Ser. No. 14/570,100, filed Dec. 15, 2014, which is a continuation of U.S. patent application Ser. No. 13/785,108, filed Mar. 5, 2013, now U.S. Pat. No. 9,032,226, issued May 12, 2015, which is a continuation of U.S. patent application Ser. No. 12/889,121, filed Sep. 23, 2010, now U.S. Pat. No. 8,943,334, issued Jan. 27, 2015, the content of which is hereby incorporated by reference.
a plurality of cores, at least one of the plurality of cores including a decoder to decode instructions, at least one execution unit to execute the decoded instructions, and at least one core-included cache memory, wherein the at least one of the plurality of cores comprises an out-of-order pipeline;
a power control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores, wherein the first core and the second core are to execute asymmetric workloads, the power control logic to determine whether to update the voltage/frequency of the first core based at least in part on a workload, a thermal design power (TDP) budget and a temperature of the processor, and responsive to the determination to update the voltage/frequency provided to the first core, wherein the power control logic is to send a control signal to a voltage regulator to cause the voltage regulator to provide the updated voltage to the first core.
2. The processor of claim 1, wherein the power control logic is to control the voltage/frequency of the first core while remaining within a thermal budget.
3. The processor of claim 2, wherein the temperature comprises a temperature of the first core.
4. The processor of claim 1, wherein the plurality of cores and the shared cache memory are formed on a single semiconductor die.
5. The processor of claim 4, wherein the voltage regulator comprises a fully integrated voltage regulator formed on the single semiconductor die.
6. The processor of claim 4, further comprising a plurality of fully integrated voltage regulators formed on the single semiconductor die.
7. The processor of claim 6, wherein the plurality of fully integrated voltage regulators are associated with at least one of the plurality of cores.
8. The processor of claim 6, wherein the plurality of fully integrated voltage regulators are to provide an independent voltage to at least one of the plurality of cores.
9. The processor of claim 1, wherein the power control logic is to receive a performance state change request from an operating system (OS) for dynamic update of a voltage/frequency of one or more cores of the plurality of cores during OS operation.
10. The processor of claim 1, wherein the power control logic is to control provision of the voltage/frequency to the first core independently of provision of a voltage/frequency to at least a second core of the plurality of cores.
11. The processor of claim 1, wherein the first core is to receive control information and a first voltage, and adjust the first voltage to a second voltage responsive to the control information.
12. The processor of claim 1, further comprising an uncore circuit comprising the power control logic.
13. The processor of claim 12, wherein the uncore circuit is to operate at a first voltage and a first frequency for a first workload and operate at a second voltage and a second frequency for a second workload.
14. The processor of claim 1, wherein the power control logic includes an activity monitor to monitor micro-architectural activity, including instruction execution information, of the plurality of cores.
15. The processor of claim 14, wherein the power control logic is to predict a usage of the first core in a future time period based on information from the activity monitor.
16. The processor of claim 1, wherein the voltage regulator comprises an external voltage regulator.
17. The processor of claim 16, wherein the processor further comprises a plurality of fully integrated voltage regulators coupled to the external voltage regulator to provide an independent voltage to at least one of the plurality of cores.
18. The processor of claim 1, wherein the power control logic is to adjust a first set of cores to execute at an increased voltage/frequency independently of a second set of cores, so that the thermal design power (TDP) budget for the processor is maintained.
19. The processor of claim 1, wherein the at least one execution unit comprises a single instruction multiple data logic unit.
20. The processor of claim 1, wherein at least one of the plurality of cores comprises a reduced instruction set computing processor.
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