Source: http://www.google.es/patents/US5869843?dq=flatulence
Timestamp: 2013-12-10 18:30:01
Document Index: 695764641

Matched Legal Cases: ['art 2', 'art 2', 'art 2', 'art 2', 'art 1', 'art 1']

Patente US5869843 - Memory array having a multi-state element and method for forming such array ... - Google PatentesB�squeda Im�genes Maps Play YouTube Noticias Gmail Drive M�s » B�squeda avanzada de patentes | Iniciar sesi�n B�squeda avanzada de patentesPatentesA memory device having a plurality of memory arrays. Each array has a plurality of memory cells, each memory cell including an electrode defining a respective contact area. Each memory array is formed by depositing a continuous chalcogenide layer. This chalcogenide layer, even when continuous, will have...http://www.google.es/patents/US5869843?utm_source=gb-gplus-sharePatente US5869843 - Memory array having a multi-state element and method for forming such array or cells thereof N�mero de publicaci�nUS5869843 ATipo de publicaci�nConcesi�n N�mero de solicitudUS 08/486,639 Fecha de publicaci�n9 Feb 1999 Fecha de presentaci�n7 Jun 1995 Fecha de prioridad7 Jun 1995TarifaPagadasTambi�n publicado comoUS6077729, WO1996041380A1 N�mero de publicaci�n08486639, 486639, US 5869843 A, US 5869843A, US-A-5869843, US5869843 A, US5869843A InventoresSteven T. Harshfield Cesionario originalMicron Technology, Inc.Exportar citaBiBTeX, EndNote, RefManCitas de patentes (36), Otras citas (22), Citada por (354), Clasificaciones (14), Eventos legales (6) Enlaces externos: USPTO, Cesi�n de USPTO, EspacenetMemory array having a multi-state element and method for forming such array or cells thereofUS 5869843 A Resumen A memory device having a plurality of memory arrays. Each array has a plurality of memory cells, each memory cell including an electrode defining a respective contact area. Each memory array is formed by depositing a continuous chalcogenide layer. This chalcogenide layer, even when continuous, will have active areas formed above the electrodes, and a conductive layer electrically coupling at least a portion of the active areas. The memory array can also include a dielectric volume surrounding at least a portion of the plurality of electrodes. The electrodes can be contacts, plugs or pillars deposited in etched openings in the dielectric volume.
What is claimed is: 1. A memory array having a plurality of memory cells, at least a portion of said memory array comprising:a substrate; a dielectric layer disposed on said substrate; a plurality of individual conductive members being formed in said dielectric layer and being coupled to said substrate, said plurality of individual conductive members being arranged in rows; a plurality of strips of multi-state material, one respective strip of multi-state material disposed on each of the respective rows of said plurality of individual conductive members; and a plurality of strips of conductive material, one respective strip of conductive material disposed on each respective strip of multi-state material. 2. The memory array, as set forth in claim 1, wherein said substrate comprises a plurality of access devices, each of said plurality of access devices being coupled to a respective one of said plurality of individual conductive members.
Many chalcogenide alloys may be contemplated for use with the present invention. For example, alloys of tellurium, antimony and germanium may be particularly desirable, and alloys having from approximately to 55-85 percent tellurium and on the order of 15-25 percent germanium, are contemplated for use in accordance with the present invention. Preferably, the chalcogenide element will be generally homogeneous (although gradiented alloys may be utilized), and will be alloys formed from tellurium, selenium, germanium, antimony, bismuth, lead, strontium, arsenic, sulfur, silicon, phosphorus, oxygen and mixtures or alloys of such elements. The alloys will be selected so as to establish a material capable of assuming multiple, generally stable, states in response to a stimulus. It is contemplated that in most cases, the stimulus will represent an electrical signal, and that the multiple states will be states of differing electrical resistance. U.S. Pat. No. 5,335,219 is believed to be generally illustrative of the existing state of the art relative to chalcogenide materials, and is believed to provide explanations regarding the current theory of function and operation of chalcogenide elements and their use in memory cells. The specification of U.S. Pat. No. 5,335,219 to Ovshinski et al., issued Aug. 2, 1994, is incorporated herein by reference, for all purposes. An exemplary specific chalcogenide alloy suitable for use in the present invention is one consisting of Te.sub.56 Ge.sub.22 Sb.sub.22.
Chalcogenide materials are very susceptible to damage by most present silicon semiconductor processing techniques. Silicon processing can require temperatures that liquify chalcogenides, thus destroying them as process-worthy materials. However, chalcogenides are compatible with metalization and passivation processes. In part, this is due to the fact that these processes are performed at lower temperatures; typically below 350 contaminated. Direct contact between silicon and chalcogenide can "poison" both materials, rendering each inoperable. For this reason, isolation barriers, or diffusion barriers, must often be included to prevent undesirable contamination of the chalcogenide material.
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technology and phase change memory array manufactured thereby* Citada por examinadorClasificaciones Clasificaci�n de EE.UU.257/5, 257/3, 257/E27.4, 257/2, 257/4 Clasificaci�n internacionalH01L27/115, H01L27/24, H01L29/792, H01L21/8247, H01L29/788, H01L27/105, G11C11/56 Clasificaci�n cooperativaH01L27/24 Clasificaci�n europeaH01L27/24Eventos legales FechaC�digoEventoDescripci�n8 Jul 2010FPAYFee paymentYear of fee payment: 124 Ene 2010ASAssignmentOwner name: ROUND ROCK RESEARCH, LLC,NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;US-ASSIGNMENT DATABASE UPDATED:20100525;REEL/FRAME:23786/416Effective date: 20091223Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:23786/416Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK14 Jul 2006FPAYFee paymentYear of fee payment: 818 Jul 2002FPAYFee paymentYear of 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