Source: https://patents.google.com/patent/US9299684B2/en
Timestamp: 2019-04-19 11:25:56
Document Index: 225316866

Matched Legal Cases: ['§119', '§1', 'Application No. 200505523', 'Application No. 2008', 'Application No. 2008', 'Application No. 10', 'Application No. 2008']

US9299684B2 - Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices - Google Patents
US9299684B2
US9299684B2 US14/011,138 US201314011138A US9299684B2 US 9299684 B2 US9299684 B2 US 9299684B2 US 201314011138 A US201314011138 A US 201314011138A US 9299684 B2 US9299684 B2 US 9299684B2
US14/011,138
US20130341805A1 (en
2005-08-26 Priority to SG200505523-1 priority
2005-08-26 Priority to SG200505523 priority
2013-12-26 Publication of US20130341805A1 publication Critical patent/US20130341805A1/en
2016-03-29 Publication of US9299684B2 publication Critical patent/US9299684B2/en
This application is a divisional of U.S. application Ser. No. 13/251,980 filed Oct. 3, 2011, now U.S. Pat. No. 8,519,523, which is a continuation of U.S. application Ser. No. 12/352,283 filed Jan. 12, 2009, now U.S. Pat. No. 8,030,748, which is a continuation of U.S. application Ser. No. 11/218,028 filed Aug. 31, 2005, now U.S. Pat. No. 7,504,284, which claims foreign priority benefits under 35 U.S.C. §119(a)-(d) and 37 C.F.R. §1.55 of Republic of Singapore Application No. 200505523-1 filed Aug. 26, 2005, now Republic of Singapore Patent No. 130066, each of which is incorporated herein by reference in its entirety.
wherein the first and second microelectronic dies each have an active side including a plurality of active terminals, and a back side, and wherein the back side of the first microelectronic die is attached to the back side of the second microelectronic die;
a first wire connecting the first surface of the first substrate to the first microelectronic die; and
2. The microelectronic package of claim 1, further comprising a second wire connecting the first wire bond contact and the second wire bond contact.
3. The microelectronic package of claim 1, further comprising a mold compound encapsulating the first and second wires.
4. The microelectronic package of claim 1 wherein the first substrate is larger than the second substrate.
6. The microelectronic package of claim 1 wherein the second microelectronic die comprises a flip-chip package construction.
7. The microelectronic package of claim 1, further comprising:
a first substrate having a first external contact at a first surface and a first wire bond contact at a second surface opposite the first surface, wherein the first substrate has a through opening;
a second substrate having a second external contact and a second wire bond contact at a third surface facing away from the first substrate and a fourth surface opposite the third surface;
a second microelectronic die between the first and second substrates, the second microelectronic die being attached to the first microelectronic die and adjoining the fourth surface;
a wire connecting the first wire bond contact and the second wire bond contact;
wires extending from a plurality of contacts on the first die to the first surface of the first substrate via the through opening; and
a molding compound at least partially encapsulating the first and second substrates, the first and second microelectronic dies and the wire without covering the first external contact or the second external contact.
9. The microelectronic package of claim 8 with the second substrate having an exposed grid array of electrical contacts to allow for a stacking assembly of two or more package assemblies.
10. The microelectronic package of claim 8 with the first and second microelectronic dies each having an active side including a plurality of active terminals, and a back side, and with the back side of the first microelectronic die attached to the back side of the second microelectronic die.
US14/011,138 2005-08-26 2013-08-27 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices Active 2025-11-18 US9299684B2 (en)
SG200505523 2005-08-26
US13/251,980 Division US8519523B2 (en) 2005-08-26 2011-10-03 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
US20130341805A1 US20130341805A1 (en) 2013-12-26
US9299684B2 true US9299684B2 (en) 2016-03-29
WO2004088727B1 (en) 2003-04-02 2005-03-10 United Test & Assembly Ct Ltd Multi-chip ball grid array package and method of manufacture
Office Action issued Apr. 3, 2012 in Japan Application No. 2008-528182, 6 pages.
Office Action issued Apr. 9, 2013 in Japan Application No. 2008-528182, 7 pages.
Office Action issued Feb. 24, 2010 in Korean Application No. 10-2008-7005294.
Office Action issued Feb. 8, 2011 in Japan Application No. 2008-528182, 7 pages.
Search Report and Written Opinion for International Application No. PCT/US20061033219, 11 pages, Mar. 26, 2007.
US20100200966A1 (en) 2010-08-12 Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages