Source: https://patents.google.com/patent/US8365040B2/en
Timestamp: 2019-05-20 22:48:24
Document Index: 722181040

Matched Legal Cases: ['Application No. 61', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61']

US8365040B2 - Systems and methods for handling immediate data errors in flash memory - Google Patents
Systems and methods for handling immediate data errors in flash memory Download PDF
US8365040B2
US8365040B2 US12/596,439 US59643908A US8365040B2 US 8365040 B2 US8365040 B2 US 8365040B2 US 59643908 A US59643908 A US 59643908A US 8365040 B2 US8365040 B2 US 8365040B2
US12/596,439
US20100122113A1 (en
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2008-09-17 Application filed by Densbits Tech Ltd filed Critical Densbits Tech Ltd
2008-09-17 Priority to PCT/IL2008/001237 priority patent/WO2009095902A2/en
2010-05-13 Publication of US20100122113A1 publication Critical patent/US20100122113A1/en
2011-01-19 Assigned to DENSBITS TECHNOLOGIES LTD. reassignment DENSBITS TECHNOLOGIES LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEVY, SHMUEL, WEINGARTEN, HANAN
2013-01-29 Publication of US8365040B2 publication Critical patent/US8365040B2/en
A flash memory system comprising temporary memory, writing apparatus for writing first logical data from the temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors, reading apparatus for reading the physical representation from the cells, thereby to generate, and store in the temporary memory, second logical data which if read immediately is identical to the first logical data other than the known errors; and controlling apparatus controlling the writing apparatus and the reading apparatus and including known error ID apparatus operative to identify the known errors by comparing the first logical data to second logical data read immediately after the physical representation is generated, to store information characterizing the known errors and to use the information, when the second logical data is next read, to correct the known errors.
This application is a National Phase Application of PCT International Application No. PCT/IL2008/001237, entitled “SYSTEMS AND METHODS FOR HANDLING IMMEDIATE DATA ERRORS IN FLASH MEMORY” International Filing Date Sep. 17, 2008, published on Aug. 6, 2009 as International Publication No. WO 2009/095902 A2, which in turn claims priority from U.S. Provisional Application No. 61/006,806, filed Jan. 31, 2008 a, U.S. Provisional Application No. 61/071,486, filed May 1, 2008, all of which are incorporated herein by reference in their entirety.
Other co-pending applications include: U.S. Provisional Application No. 60/960,207, filed Sep. 20, 2007 and entitled “Systems and Methods for Coupling Detection in Flash Memory”, U.S. Provisional Application No. 61/071,467, filed Apr. 30, 2008 and entitled “Improved Systems and Methods for Determining Logical Values of Coupled Flash Memory Cells”, U.S. Provisional Application No. 60/960,943, filed Oct. 22, 2007 and entitled “Systems and methods to reduce errors in Solid State Disks and Large Flash Devices” and U.S. Provisional Application No. 61/071,469, filed Apr. 30, 2008 and entitled “Systems and Methods for Averaging Error Rates in Non-Volatile Devices and Storage Systems”, U.S. Provisional Application No. 60/996,027, filed Oct. 25, 2007 and entitled “Systems and Methods for Coping with Variable Bit Error Rates in Flash Devices”, U.S. Provisional Application No. 61/071,466, filed Apr. 30, 2008 and entitled “Systems and Methods for Multiple Coding Rates in Flash Devices”, U.S. Provisional Application No. 61/006,120, filed Dec. 19, 2007 and entitled “Systems and Methods for Coping with Multi Stage Decoding in Flash Devices”, U.S. Provisional Application No. 61/071,464, filed Apr. 30, 2008 and entitled “A Decoder Operative to Effect A Plurality of Decoding Stages Upon Flash Memory Data and Methods Useful in Conjunction Therewith”, U.S. Provisional Application No. 61/006,385, filed Jan. 10, 2008 and entitled “A System for Error Correction Encoder and Decoder Using the Lee Metric and Adapted to Work on Multi-Level Physical Media”, U.S. Provisional Application No. 61/064,995, filed Apr. 8, 2008 and entitled “Systems and Methods for Error Correction and Decoding on Multi-Level Physical Media”, U.S. Provisional Application No. 60/996,948, filed Dec. 12, 2007 and entitled “Low Power BCH/RS Decoding: a Low Power Chien-Search Implementation”, U.S. Provisional Application No. 61/071,487, filed May 1, 2008 and entitled “Chien-Search System Employing a Clock-Gating Scheme to Save Power for Error Correction Decoder and other Applications”, U.S. Provisional Application No. 61/071,468, filed Apr. 30, 2008 and entitled “A Low Power Chien-Search Based BCH/RS Recoding System for Flash Memory, Mobile Communications Devices and Other Applications”, U.S. Provisional Application No. 60/996,782, filed Dec. 5, 2007 and entitled “Systems and Methods for Using a Training Sequence in Flash Memory”, U.S. Provisional Application No. 61/064,853, filed Mar. 31, 2008 and entitled “Flash Memory Device with Physical Cell Value Deterioration Accommodation and Methods Useful in Conjunction Therewith”, U.S. Provisional Application No. 61/129,608, filed Jul. 8, 2008 and entitled “A Method for Acquiring and Tracking Detection Thresholds in Flash Devices”, U.S. Provisional Application No. 61/006,078, filed Dec. 18, 2007 and entitled “Systems and Methods for Multi Rate Coding in Multi Level Flash Devices”, U.S. Provisional Application No. 61/064,923, filed Apr. 30, 2008 and entitled “Apparatus For Coding At A Plurality Of Rates In Multi-Level Flash Memory Systems, And Methods Useful In Conjunction Therewith”, U.S. Provisional Application No. 61/006,805, filed Jan. 31, 2008 and entitled “A Method for Extending the Life of Flash Devices”, U.S. Provisional Application No. 61/071,465, filed Apr. 30, 2008 and entitled “Systems and Methods for Temporarily Retiring Memory Portions”, U.S. Provisional Application No. 61/064,760, filed Mar. 25, 2008 and entitled “Hardware efficient implementation of rounding in fixed-point arithmetic”, U.S. Provisional Application No. 61/071,404, filed Apr. 28, 2008 and entitled “Apparatus and Methods for Hardware-Efficient Unbiased Rounding”, U.S. Provisional Application No. 61/136,234, filed Aug. 20, 2008 and entitled “A Method Of Reprogramming A Non-Volatile Memory Device Without Performing An Erase Operation”, U.S. Provisional Application No. 61/129,414, filed Jun. 25, 2008 and entitled “Improved Programming Speed in Flash Devices Using Adaptive Programming”, and several other co-pending patent applications being filed concurrently (same day).
The present invention relates generally to methods and systems for managing computer memory and more particularly to methods and systems for managing flash memory.
Conventional flash memory technology is described in the following publications inter alia:
[1] Paulo Cappelletti, Clara Golla, Piero Olivo, Enrico Zanoni, “Flash Memories”, Kluwer Academic Publishers, 1999
[2] G. Campardo, R. Micheloni, D. Novosel, “CLSI-Design of Non-Volatile Memories”, Springer Berlin Heidelberg N.Y., 2005
U.S. Pat. Nos. 5,771,346; 7,203,874; and Published United States Patent Application Nos. 2003231532; 2004243909; and 2007101184.
Today's Flash memory devices store information with high density on Flash cells with ever smaller dimensions. In addition, Multi-Level Cells (MLCs) store several bits per cell by differentially setting the amount of charge in the cell. The amount of charge is then measured by a detector, e.g. in the form of a threshold voltage of the transistor gate. Due to inaccuracies during the programming procedure and charge loss due to retention in memory and temperature, the measured levels during a Read operation suffer from detection errors. The small dimensions of the Flash cells result in cells that can store very small amounts of charge, enhancing the effects of inaccuracies due to randomness of programming, retention and previous erase/write cycles. Thus, new single level cells (SLC) and multi-level cell devices have significantly increased bit error rate (BER), decreasing the reliability of the device.
Flash devices are typically organized into physical pages. Each page contains a section allocated for data (typically 512 bytes-4 Kbytes) and a small number of bytes (typically 16-32 bytes for every 512 data bytes) containing redundancy and management information. The redundancy bytes are used to store error correcting information, for correcting errors which may have occurred during the page program or page read. Each Read and Program operation is typically performed on an entire page. A number of pages are grouped together to form an Erase Block (EB). A page typically cannot be erased unless the entire EB which contains it is erased.
An important factor of flash memory cost is the proportion of space allocated to “spare bits”, especially redundant information used to correct read errors e.g. due to retention. The ratio between the number of redundancy bits to the number of data bits is called the code rate.
The code rate is chosen according to the flash memory bit error rate or the number of error bits per page. The code rate is always less than the capacity bound that can be computed for each error probability. As shown in FIG. 2, the erasure channel capacity is always greater than the binary channel, so using erasure coding to correct the program errors is much more powerful than using conventional error correction code. Conventional error correction code, such as BCH or Reed-Solomon, corrects random errors during a read operation and lacks knowledge of the errors' locations.
Erasure coding use verifies procedure information to detect exactly the error bits' locations and to encode them. An example described below illustrates use of 15 bits of redundancy for 2 Kbyte page to correct up to 7 errors by using erasures whereas conventional error correction code allows correction of only a single error. The term “erasure” refers to a dummy logical value assigned to a symbol to indicate that it is unclear which logical value is best to assign, e.g. because the physical level read from the cell which the symbol represents is intermediate to adjacent logical values such as 110 and 111. The term “erasure coding” refers to the addition of redundancy (“erasure code”) to a codeword to enable the codeword to be properly decoded even though it includes at least one erasure.
Certain embodiments of the present invention seek to provide a flash memory system in which a page being programmed is read immediately after programming to detect immediate errors and construct parity bits according to error location. The term “immediate errors” is intended to include data errors which occur, hence can be identified and taken into account, as the data is being written from a still existing temporary memory, as opposed to errors which occur only after the temporary memory from which the data has been copied, no longer exists.
Bit error rate (BER)=a parameter that a flash memory device manufacturer commits to vis a vis its customers, expressing the maximum proportion of wrongly read bits (wrongly read bits/total number of bits) that users of the flash memory device may expect at any time during the stipulated lifetime of the flash memory device e.g. 10 years.
Cycling: Repeatedly writing new data into flash memory cells and repeatedly erasing the cells between each, two writing operations.
Physical Page=A portion, typically 512 or 2048 or 4096 bytes in size, of a flash memory e.g. a NAND or NOR flash memory device. Writing and reading is typically performed physical page by physical page, as opposed to erasing which can be performed only erase sector by erase sector. A few bytes, typically 16-32 for every 512 data bytes are associated with each page (typically 16, 64 or 128 per page), for storage of error correction information. A typical block may include 32 512-byte pages or 64 2048-byte pages.
Precise read, soft read: Cell threshold voltages are read at a precision (number of bits) greater than the number of Mapping levels (2^n). The terms precise read or soft read are interchangeable. In contrast, in “hard read”, cell threshold voltages are read at a precision (number of bits) smaller than the number of Mapping levels (2^ n where n=number of bits per cell).
Retention: of original physical levels induced in the flash memory cells despite time which has elapsed and despite previous erase/write cycles; retention is typically below 100% resulting in deterioration of original physical levels into present levels.
Dummy charge level: a charge level which does not represent an n-tuple of logical data
Retention noise: read errors generated by degradation of data due to length of retention in flash memory and/or previous write-erase cycles, as opposed to known errors.
Known errors: Immediate errors, such as but not limited to read errors generated by erratic over-programming also termed “erratic over-programming noise”, as opposed to retention noise.
Code rate: ratio of data bits to data and redundancy bits in flash memory.
Data cells: cells storing data provided by host as opposed to “non-data cells” which do not store host-provided data, and may, for example, store instead error correction information, management information, redundancy information, spare bits or parity bits.
Spare bits: Redundancy information, or all non-data information including management information.
In this specification, the terms “decision levels” and “threshold levels” are used interchangeably. “Reliably storing” and “reliable” are used to indicate that certain information is stored with high reliability in the sense that the information can be expected to be read without error throughout the guaranteed lifetime of the flash memory device.
There is thus provided, in accordance with at least one embodiment of the present invention, a flash memory system comprising temporary memory, writing apparatus for writing first logical data from the temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors, reading apparatus for reading the physical representation from the cells, thereby to generate, and store in the temporary memory, second logical data which, if read immediately, is identical to the first logical data other than the known errors; and controlling apparatus controlling the writing apparatus and the reading apparatus and including known error ID apparatus operative to identify the known errors by comparing the first logical data to second logical data read immediately after the physical representation is generated, to store information characterizing the known errors and to use the information, when the second logical data is next read, to correct the known errors.
Also in accordance with at least one embodiment of the present invention, the information enables addresses of the known errors to be reconstructed when the second logical data is next read and wherein the controlling apparatus is operative to reconstruct the addresses, using the information, when the second logical data is next read.
Further in accordance with at least one embodiment of the present invention, the information comprises addresses of the known errors.
Still further in accordance with at least one embodiment of the present invention, the information comprises an earmark on each, cell containing at least one known error and correct logical data for each cell bearing an earmark.
Further in accordance with at least one embodiment of the present invention, the earmark comprises a dummy physical level assigned to the cell.
Still further in accordance with at least one embodiment of the present invention, the information comprises the total number of known errors identified by the known error ID apparatus and a serial number of a set comprising the addresses of the known errors, within a sequence, having a predetermined order, of all possible sets of the addresses of the known errors given the total number of known errors.
Further in accordance with at least one embodiment of the present invention, at least a portion of the controlling apparatus resides in a microcontroller within a flash memory device within which the cells reside.
Still further in accordance with at least one embodiment of the present invention, at least a portion of the controlling apparatus resides in a controller external to a flash memory device within which the cells reside.
Additionally in accordance with at least one embodiment of the present invention, the cells comprise NAND cells or NOR cells.
Further in accordance with at least one embodiment of the present invention, the addresses comprise bit addresses or symbol addresses.
Also provided, in accordance with at least one embodiment of the present invention, is a flash memory system comprising a multiplicity of flash memory cells; reading apparatus; writing apparatus for writing logical data from temporary memory into individual flash memory cells from among the multiplicity of flash memory cells, thereby to generate a physical representation of the logical data including a plurality of physical levels at least some of which represent, to the reading apparatus, at least one bit-worth of the logical data; and special cell marking apparatus operative to earmark at least an individual one of the multiplicity of flash memory cells for subsequent special treatment.
Further in accordance with at least one embodiment of the present invention, the special cell marking apparatus is operative to earmark the individual one of the multiplicity of cells by assigning a dummy physical level assigned to the cell wherein the dummy physical level is characterized in that it does not represent logical data to the reading apparatus.
Additionally provided, in accordance with at least one embodiment of the present invention, is a method for storing a set of at least one consecutive integers in memory, the method comprising computing and storing at least one serial number identifying at least one respective position of at least one consecutive integer in the set respectively in a predetermined sequence of all possible addresses; and computing the at least one consecutive integer from the at least one serial number.
Further in accordance with at least one embodiment of the present invention, the set of at least one consecutive integers comprises at least one address.
Still further in accordance with at least one embodiment of the present invention, the address comprises a flash memory cell address.
Also provided, in accordance with yet a further embodiment of the present invention, is a flash memory utilization method comprising writing first logical data from temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors; reading the physical representation from the cells, thereby to generate, and store in the temporary memory, second logical data which, if read immediately, is identical to the first logical data other than the known errors; and controlling the writing apparatus and the reading apparatus including identifying the known errors by comparing the first logical data to second logical data read immediately after the physical representation is generated, storing information characterizing the known errors and using the information, when the second logical data is next read, to correct the known errors.
Additionally provided, in accordance with at least one embodiment of the present invention, is a flash memory utilization method comprising writing logical data from temporary memory into individual flash memory cells from among a multiplicity of flash memory cells, thereby to generate a physical representation of the logical data including a plurality of physical levels at least some of which represent, to reading apparatus, at least one bit-worth of the logical data; and special cell marking apparatus operative to earmark at least an individual one of the multiplicity of flash memory cells for subsequent special treatment.
According to one embodiment of the present invention, a program, verify and erasure coding method is provided in which some or all of the following steps are performed in any suitable order such as but not limited to the following: programming data only (page without parity bits), verifying including detecting the error bits and erratic over-programming, storing at least one error address in temporary memory such as SRAM, generating erasure data e.g. as described herein with reference to FIG. 5 or 6, encoding the data and erasure bits using error correction code and obtaining the parity bits, and programming of the erasure and parity bits. In contrast, conventionally, a page of data and parity bits is programmed, followed by verification.
According to one embodiment of the present invention, a method for erasure coding which utilizes an additional level is provided, in which some or all of the following steps are performed in any suitable order such as but not limited to the following: encoding the page, such that result=data+parity, programming the page, verifying that the cell level is between the lower and upper values, and if not (e.g. due to erratic over-programming), increase the cell voltage to an erasure level.
The embodiments referred to above, and other embodiments, are described in detail in the following sections.
FIG. 1A is a logarithmic-scale graph of distributions of voltage levels within flash memory cells suffering from erratic over-programming (EOP);
FIG. 1B is a simplified block diagram illustration of a flash memory system constructed and operative in accordance with a first embodiment of the present invention;
FIG. 1C is a simplified block diagram illustration of a flash memory system constructed and operative in accordance with a second embodiment of the present invention;
FIG. 1D is a simplified block diagram illustration of a flash memory system constructed and operative in accordance with a third embodiment of the present invention;
FIG. 2 is a code rate vs. bit flip error probability graph showing a rate of erasure in a top graph and a binary channel in a bottom graph;
FIG. 3 is a logarithmic-scale graph of distributions of voltage levels within theoretical flash memory cells which do not suffer from erratic overprogramming;
FIGS. 4A and 4B are prior art subsequence-symbol tables;
FIG. 5 is a simplified flowchart illustration of a recursive method for compact encoding of erratic over-programming error locations constructed and operative in accordance with certain embodiments of the present invention which is suitable for performing the corresponding encoding step of FIG. 7;
FIG. 6 is a simplified flowchart illustration of a recursive method, constructed and operative in accordance with certain embodiments of the present invention, for decoding erratic over-programming error locations encoded as per the method of FIG. 5, the method being suitable for performing the corresponding decoding step of FIG. 8;
FIG. 7 is a simplified flowchart illustration of a first method for erratic over-programming coding, constructed and operative in accordance with certain embodiments of the present invention, which uses a verify-read operation to generate known error characterizing information re cells which suffered from erratic over-programming;
FIG. 8 is a simplified flowchart illustration of a method, constructed and operative in accordance with certain embodiments of the present invention, for reading a page programmed as per the method of FIG. 7;
FIG. 9 is a simplified flowchart illustration of a second method for erratic over-programming coding, constructed and operative in accordance with certain embodiments of the present invention;
FIG. 10 is a simplified flowchart illustration of a decoding method, constructed and operative in accordance with certain embodiments of the present invention, which corresponds to the coding method of FIG. 9; and
FIG. 11 is a redundancy vs. bit error rate graph useful in implementing some of the embodiments shown and described herein.
According to certain embodiments of the present invention, the code rate is selected in the flash design stage. Experiments are performed in the course of which the bit error rate may be measured and the code rate computed e.g. as shown in FIG. 11. FIG. 11 illustrates a redundancy allocation per any bit error rate for a given page size. Conventional programming may include several steps e.g. as shown and described below including incremental injection of charge into the flash. The charge monotonically increases until the cell voltage reaches the pre-defined target value.
In technologies in which the charge can only increase, some cell voltages may overshoot their intended targets due to a random process known as erratic over-programming (EOP). It is appreciated however that certain embodiments of the present invention are described below in terms of erratic over-programming merely for simplicity, their applicability now being limited to applications in which erratic over-programming is actually occurring.
Erratic over-programming causes errors in the stored data. These errors are an example, but not the only example, of errors which, fortunately, may be detected immediately after the programming procedure ends in accordance with certain embodiments of the present invention. In FIG. 1A, erratic over-programming manifests itself as a long tail, indicated in dashed lines, on the right of the cell voltage distribution. FIG. 3, in contrast, is a theoretical illustration of how the distribution might appear in the absence of erratic over-programming. FIG. 1A too is not necessarily accurate in its parameters and is merely intended to illustrate the concept of erratic over-programming.
The errors during program operation can be detected immediately if a verify-read operation 230 is instituted following the page program operation 220, as shown in FIG. 7. The verify-read operation 230 is typically executed between successive repetitions of program steps 220 in order to learn the exact voltage value of the cell during the programming procedure. During the programming operation a cell voltage typically cannot be restored to a lower value, however, the verify-read information may be employed to construct code that corrects program errors.
Certain embodiments of the present invention employ program/verify and error correction to improve the flash programming quality. During normal programming operation some cells experience erratic over-programming. Both erratic over-programming noise and retention noise degrade the flash quality and generate read errors. Conventional error correction does not distinguish between the erratic over-programming and retention noise which are treated as a single read noise source. The flash suffers from aging as a result of program/erase cycles and retention time. The aging process results in loss of window size and increase in noise variance of each program level e.g. each of the four programming levels V1, . . . , V4 in FIG. 1A. The consequence may be loss in the signal to noise ratio and increase in number of error bits.
In order to encode information and to protect it against errors, redundancy information is typically appended to the original data. A bit (or symbol) sequence representing data (typically a pageful of data) and redundancy is termed herein a “codeword”. A “code rate” of a codeword may be the ratio between the number of bits (or symbols) in the codeword which serve to store data, and the total number of bits (or symbols) in the codeword which may for example be 1024 Bytes to 4096 Bytes. A bit may flip to the wrong value with probability p.
The bottom curve in FIG. 2 shows the maximum code rate achievable assuming there is no prior information on which bit flips and how many such bits there are. The top curve in FIG. 2 shows the maximum rate achievable if it is known which bits are suspicious and if such bits are marked as erasures so as to indicate that they may be either 0 or 1, with equal probability. As is apparent from FIG. 2, more density can be obtained from the flash if locations of erratic over-programming errors are recorded and erratic over-programming noise removed, using coding in accordance with any embodiment of the present invention. Advantages of these embodiments may include one or both of the following:
a. Narrowing of the program symbol regions (voltage distributions), e.g. removal of the erratic over-programming tail. (A “symbol” is an n-tuple of bits in a logical page, represented by a discrete charge level on a physical page. For example: ‘00’=V0, ‘01’=V1, ‘10’=V2 and ‘11’=V3 are 4 symbol/charge level relationships); and
b. Use of erasure coding to encode erratic over-programming cells.
According to one embodiment of the present invention, e.g. as shown in FIG. 1A, erratic over-programming is detected following a programming procedure and a sequence of bits (or symbols) may be allocated which represents the locations where erratic over-programming occurred. The sequence is then typically appended or stored separately (e.g. in redundancy symbols).
A second embodiment, as shown in FIG. 3, is to allocate an additional program level which will be denoted as an erasure level at each program symbol. The erasure symbols may be denoted by the top program level. The locations of erratic over-programming are then marked by doing a second programming procedure which raises the program levels of the erratic over-programming locations to the top level. FIG. 3 is an example of a case of a multi-level cell with 4 program levels and one erasure level marked as V5. More generally, a region between any two program levels may be deemed an erasure region. The program window may be divided into multiple erasure regions interspersed with multiple symbol regions figures shown in FIG. 3. In FIG. 3, by way of example, there are four erasure regions marked E1, E2, E3 and E4. The levels are tuned according to the erasure coding capability. If a specific cell's programmed level lies in the erasure region above it, or in any of the regions above that, the cell may be marked as erasure.
In the verify operation the erratic over-programming may be detected. By using the lower and upper verify level for each symbol, a cell which has moved beyond the lower or upper limits can be detected. If so the program erasure may be moved in the next step. If an erratic over-programming bit is detected, its physical value may be increased to the dummy value (V5 in the illustrated embodiment) which indicates that the cell suffers from erratic over-programming error.
Once marked by either erasures or in a separate sequence as described in detail below, a second code may be applied to both parts of the data (i.e. the data part and the erasure part), thereby protecting the information against additional errors due to retention. As a result, the programming errors are eliminated and more errors may be corrected compared with conventional error correction methods.
FIG. 1B is a simplified functional block diagram of a flash memory system constructed and operative, in accordance with a first embodiment of the present invention, to identify and rectify data errors which occur while the temporary memory from which the data was read, still exists. As shown, the system of FIG. 1C includes a host 100 interfacing with a flash memory device 105 including a microcontroller 110 (some or all of whose functions may alternatively be performed by an external microcontroller connected between the flash memory and the host), and one or more erase sectors 120 each having one or more physical pages 130 each of which comprises a plurality of data cells 140 as well as non-data cells 121. Also included is erasing circuitry 150, writing circuitry 160 and reading circuitry 170. The microcontroller 110 finds known errors by reading back data from cells 140 while original host-supplied data is still available for comparison. The non-data cells 121 are operative to store management info, redundancy info and information re known errors. It is appreciated that some or all of the functionality of the microcontroller 110 can be provided in fact by an external controller instead.
FIG. 1C is a simplified functional block diagram of a flash memory system constructed and operative, in accordance with a second embodiment of the present invention, to identify and rectify data errors which occur while the temporary memory from which the data was read, still exists. In the embodiment of FIG. 1D, the microcontroller 110, or an external controller, finds known errors by reading back data from cells 140 while original host-supplied data is still available for comparison. The controller also typically re-writes data, appending addresses of known errors thereto; and, during reading, flips bits at these addresses, all as described in detail below with reference to FIGS. 7-8. In this embodiment, non-data cells 121 typically store management information, redundancy information and known error bit addresses.
FIG. 1D is a simplified functional block diagram of a flash memory system constructed and operative, in accordance with a third embodiment of the present invention, to identify and rectify data errors which occur while the temporary memory, from which the data was read, still exists. In the embodiment of FIG. 1D, the microcontroller 110, or an external controller, finds known errors by reading back data from cells 140 while original host-supplied data is still available for comparison, re-writes data replacing known errors with dummy values and appending correct values, and, during reading, replaces dummy values with appended correct values. Non-data cells 121 typically store management info, redundancy info and content for cells found to be in dummy state, all as described in detail below with reference to FIGS. 9-10. In this embodiment, the data cells 140 have n data states plus one additional dummy state earmarking cell as suffering from known error.
A first embodiment of erratic over-programming coding, as illustrated in FIG. 7, uses a verify-read operation 230 to generate known error characterizing information re cells which suffered from erratic over-programming. Locations of these cells may be encoded, preferably as compactly as possible, and stored in the redundancy area of the page along with additional typically conventional error correction information. The error correction information may be generated from the erroneous page and the encoded erratic over-programming cell locations. A second programming procedure 270, may be then performed to program the redundancy cells. In this embodiment, no erasure regions are provided between programming levels.
The method of FIG. 7 typically includes some or all of the following steps in a suitable order e.g. as shown:
Step 210: Receive original data bits from host, store in temporary memory, and map the original data bits into levels. The mapping process converts n bits into 2^n levels, e.g. 2 bits per cell are converted to 4 levels to be program. This process may be done by applying Grey coding e.g. as shown in FIG. 4A for the case of 8 levels.
Step 220: Program the levels into cells reserved for data in a flash memory cell array
Step 230: while the original data still exists in temporary memory, read back a pageful of cell values from the array and decode them e.g. by mapping them back into bits.
Step 240: Compare the read result with the corresponding pageful of original data still residing in temporary memory. Record the locations of the erroneous bits in temporary memory, optionally in a compact form. It may be possible to store the locations, or to store the first locations followed by the intervals between each two adjacent locations, or to use any other suitable method for compactly storing the location information such as the method of FIG. 5.
Step 250: generate non-data bits for correcting retention errors using an error correction code to decode the data read from the device (which may include erratic over-programming errors)
Step 255: generate non-data bits for correcting known errors using an error correction code to encode the info re known error locations recorded in step 240
Step 260: Map the non-data bits generated in steps 250, 255 into levels
Step 270: Program the levels mapped in step 260, into non-data cells
Typically, according to the method of FIG. 7, the page is programmed in two sections (steps 220 and 270), first the data without parity then the erasure index and parity. If additional level coding is used, programming may occur in a single step (data and parity), since the erasure index may be programmed with the additional level.
A suitable method for reading a page programmed as per the method of FIG. 7 is illustrated in FIG. 8. As shown, the method of FIG. 8 may include some or all of the following steps, suitably ordered e.g. as shown:
Step 810: Read a physical page-full of cell values (data+non-data bits) into temporary memory and de-map them into bits.
Step 820: correct retention errors by error correction-decoding of the non-data cells storing the info encoded in step 250 (typically also correcting thereby, errors that occurred due to erratic over-programming in the programming of the redundancy. Since parity may be programmed in the second step it might be corrupted with erratic over-programming. So in the decoding step the entire page is typically corrected including the erratic over-programming errors in the parity bits.
Step 830: Access error location info encoded in step 255 & decode (e.g. using the method of FIG. 6 if locations were encoded using the method of FIG. 6) correct known errors by flipping the values of the data bits corresponding to the decoded error locations.
Reference is now made to FIG. 5 which illustrates a recursive method, including a recursive step 625, for compact encoding of erratic over-programming error locations suitable for performing step 240 of FIG. 7. FIG. 6 illustrates a recursive method, including a recursive step 685, for decoding erratic over-programming error locations encoded as per the method of FIG. 5 and is suitable for performing step 830 of FIG. 8.
These methods achieve near optimum encoding. Let k denote the number of locations and let n be the number of bits (or symbols) in the original data sequence. There are exactly
( n k ) = n ! k ! ⁢ ( n - k ) !
possible sequences of k out of n error locations. Therefore, at least
⌈ log 2 ⁡ ( n k ) ⌉
bits are employed to encode a sequence. First, k bits are encoded. If k<K, ┌log2 K┐ bits may be reserved for this, where K may be any integer greater than k. Next, encode the sequence of k out of n locations, typically in a compact form employing
In order to encode the sequence of k out of n locations, a serial number may be assigned to each ordered set of k possible locations between 0 and
( n k ) - 1.
This serial number may be then presented as a binary number; since the correspondence between serial number and ordered set of locations is known, the ordered set of locations can be retrieved. This may be done in a recursive manner. Assume the location of the first error is 1. There are then
( n - 1 k - 1 )
ways to define all possible k−1 locations of the remaining possible n−1 locations. Therefore, to encode a sequence of k out of n locations in which the first location is 1, these sequences may be numbered between 0 and
( n - 1 k - 1 ) - 1.
If the first location was not 1 but 2, there are
( n - 2 k - 1 )
ways to define all possible k−1 locations of the possible (left) n−2 locations. Therefore, to encode a sequence of k out of n locations in which the first location is 2, these sequences are numbered between
( n - 1 k - 1 ) ⁢ ⁢ and ⁢ ⁢ ( n - 1 k - 1 ) + ( n - 2 k - 1 ) - 1. ⁢ ⁢ ( n - 1 k - 1 )
may be added to the numbers to distinguish these cases from the case in which the first error was found in the first location. This procedure may be repeated iteratively until the first location is found and recursively to give the precise number of k−1 numbers out of n−v numbers where v is the location of the first error.
In summary, a compact and perhaps the most compact way to store a subset of cell locations, from among an original data sequence stored in n cell locations, which are special in some sense (e.g. in the sense that the cell locations in the subset suffer from known errors) comprises the following procedure as shown in FIG. 5: storing the number (k) of such cell locations in the redundancy bits, converting each possible set of cell locations into a cell location sequence having a predetermined order, typically increasing order of address, and arranging all possible cell location sequences in a known order, thereby to define a sequence of all possible selections of k cell locations from among the total number, n, of cell locations. If this is done, it may be sufficient to store the serial number of the particular set of known error locations within the sequence; from this and from the known number k of cell locations, the known error locations can be derived e.g. as per the method of FIG. 6.
For example, there may be k=5 cells with known errors in a flash memory physical page containing a total of n=1024 cells. The addresses of these cells may be 1, 6, 100, 457 and 900. There are 1024!/5!(1024−5)!=9291,185,992,704 different ordered sets of 5 addresses in total which may be selected from 1024 cells, of which (1, 6, 100, 457 and 900) is but one example. These 1024!/5!(1024−5)! ordered sets of addresses may be arranged in the following known order: (1, 2, 3, 4, 5); (1, 2, 3, 4, 6); . . . (1, 2, 3, 4, 1024); (1, 2, 3, 5, 6); (1, 2, 3, 5, 7); . . . (1, 2, 3, 5, 1024); . . . (1, 2, 3, 1022, 1023); (1, 2, 3, 1022, 1024); (1, 2, 3, 1023, 1024); (1, 2, 4, 5, 6) . . . , . . . , (1, 2, 4, 1023, 1024); . . . (1, 2, 1022, 1023, 1024); (1, 3, 4, 5, 6) . . . (1, 3, 1022, 1023, 1024); . . . ; . . . ; (1, 1021, 1022, 1023, 1024); (2, 3, 4, 5, 6) . . . (2, 3, 4, 5, 1024); . . . ; . . . ; (2, 3, 1022; 1023, 1024); (2, 1021; 1022; 1023; 1024); . . . (1020; 1021; 1022; 1023; 1024), thereby to form a sequence of all possible selections of 5 ordered cell addresses from among 1024 addresses total. Using the method of FIG. 5, it may be determined that the serial number (“number”) of (1, 6, 100, 457 and 900) in the above sequence of selected sets of 5 addresses, is 575,218,469. To retrieve (1, 6, 100, 457 and 900), plug n=1024, k=5, number=575,218,469 into the method of FIG. 6.
The erratic over-programming encoding method of FIG. 7 may be modified by encoding only the symbols in which erratic over-programming errors occurred instead of the bits in which they occurred. Thus, only k out of n′ symbol locations may be encoded, where n′ is defined by n/log 2L and where L is the number of levels programmed per cell. Thus, fewer bits may be employed to encode the error locations.
In the erratic over-programming correction process it can typically be assumed that errors occur only in one direction. That is, typically, one may mistakenly program a higher level than is appropriate (e.g. V4 instead of V3) whereas one never programs a lower level than the appropriate level (e.g. V3 instead of V4), since a too-low level is raised one level higher. Thus, once it is known that a certain location contains an error, the output read level may be decreased by 1 with respect to the level actually read.
The following example explains how the method of FIG. 6 enhances compactness of flash memory. Consider an example where 16384 bits of data are programmed on an multi-level cell flash containing 3 bits per cell (i.e. 8 levels per cell). Correct n1=50 erratic over-programming errors+n2=5 errors which occur due to retention. Using the method of FIG. 7, encode at least the 16384th bit over 5462 cells. To encode n1=50 locations out of 5462 possible locations using, e.g., the method of FIG. 6,
⌈ log 2 ⁢ 50 ⌉ + ⌈ log 2 ⁡ ( 5462 50 ) ⌉ = ⁢ 413
bits are employed.
A binary BCH code, say, may be used to protect against the retention errors. This code encodes both the data read from the device (with the erratic over-programming errors) and the 413 bits encoding up to 50 erratic over-programming error locations. Such a BCH code would employ 16×5=80 redundancy bits. Therefore, a total of 493 bits may be used. This outcome may be compared with a conventional code that does not distinguish between erratic over-programming errors and retention errors hence may be operative to correct 55 errors. If BCH code is used, this would employ 55*16=880 bits of redundancy. This is almost twice the redundancy provided in the above example of usage of the method of FIG. 7.
A second method for erratic over-programming coding is now described with reference to FIG. 9. The corresponding decoding method is shown in FIG. 10. In FIG. 9, instead of encoding the erratic over-programming error locations, the cells that suffered from erratic over-programming are marked within the cells themselves e.g. by programming the cells to the highest programming level which may be especially reserved for this purpose and is referred to as the erasure level. For example, FIG. 3 illustrates 5 bell curve distributions of 5 charge levels respectively, in a 2-bit-per-cell flash memory device. The fifth level may be reserved for erasure.
In step 910, the original data is programmed with redundancy which contains parity bits. The parity bits are generated by an error correction encoder which is designed to address erasures. An example of such an encoder is a Low Density Parity Check (LDPC) encoder which is known in the art (e.g. in Modern Coding Theory, T. Richardson and R. Urbanke, Cambridge University Press, Chapter 3, page 77) as especially suitable for erasure. Thus low redundancy may be provided to facilitate erasure correction, as shown in FIG. 2. The encoder may also be used to correct a small number of errors which are not marked as erasures and which are due to retention.
Step 940 identifies which of the cells were over-programmed. Step 950 marks the over-programmed cells by raising their programming level to the highest one (e.g. V5 in FIG. 3). It is appreciated that once a level is over-programmed it cannot be lowered to the correct value. Lowering levels can only be effected in the course of an erase operation and only on multiple pages simultaneously.
In summary, the encoding process of FIG. 9 typically comprises some or all of the following steps, suitably ordered e.g. as shown:
Step 910: Get original data bits from a host and append redundancy bits using an error correction code capable of coping with erasure coding e.g. LDPC codes
Step 920: Map the data and redundancy bits into levels (e.g. using the table of FIG. 4A or the table of FIG. 4B). Program the levels into the data cells+redundancy cells, respectively, in flash memory
Step 930: while the original data bits are still available (e.g. in temporary memory), read the symbols from the flash memory and compare to the original data bits to identify known error locations.
Step 940: for each known error location identified in step 930, store its contents, e.g. store error bits as part of the redundancy data (non-data) in the temporary memory
Step 950: Program the page again, raising the program levels of those cells found in step 930 to suffer from known errors, to erasure level and programming the additional error bits as part of the redundancy data stored in the temporary memory.
The decoding process of FIG. 10 typically comprises some or all of the following steps, suitably ordered e.g. as shown:
Step 1010: Read a pageful of cells (data+redundancy) from flash memory into SRAM and de-map into bits.
Step 1020: for each Bit mapped to a cell programmed to the erasure level, store bit's addresses in another SRAM
Step 1030: Decode the data bits+erasure addresses stored in step 1020+correct contents stored in FIG. 9 using the error correction code.
Step 1040: Output correct codeword and finish, including putting correct contents sequentially into addresses decoded in step 1030
It is appreciated that the teachings of the present invention can, for example, be implemented by suitably modifying, or interfacing externally with, flash controlling apparatus. The flash controlling apparatus controls a flash memory array and may comprise either a controller external to the flash array or a microcontroller on-board the flash array or otherwise incorporated therewithin. Examples of flash memory arrays include Samsung's K9XXG08UXM series, Hynix' HY27UK08BGFM Series, Micron's MT29F64G08TAAWP or other arrays such as but not limited to NOR or phase change memory. Examples of controllers which are external to the flash array they control include STMicroelectrocincs's ST7265x microcontroller family, STMicroelectrocincs's ST72681 microcontroller, and SMSC's USB97C242, Traspan Technologies' TS-4811, Chipsbank CBM2090/CBM1190. Example of commercial IP software for Flash file systems are: Denali's Spectra™ NAND Flash File System, Aarsan's NAND Flash Controller IP Core and Arasan's NAND Flash File System. It is appreciated that the flash controller apparatus need not be NAND-type and can alternatively, for example, be NOR-type or phase change memory-type.
The present invention may for example interface with or modify, as per any of the embodiments described herein, one, some or all of the above components and particularly the error correction code and NAND interface components.
Features of the present invention which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, features of the invention, including method steps, which are described for brevity in the context of a single embodiment or in a certain order may be provided separately or in any suitable subcombination or in a different order.
a writing apparatus for writing first logical data from said temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors;
a reading apparatus for reading said physical representation from the cells, thereby to generate, and store in said temporary memory, second logical data which if read immediately is identical to said first logical data other than said known errors; and
a controlling apparatus controlling said writing apparatus and said reading apparatus, wherein the controlling apparatus is operative to identify said known errors by comparing said first logical data to second logical data read immediately after said physical representation is generated, to store information characterizing said known errors and to use said information, when said second logical data is next read, to correct said known errors; wherein said information comprises (a) multiple earmarks, each earmark is stored in a cell containing at least one known error, and (b) correct logical data for each cell storing an earmark.
2. The system according to claim 1 wherein said information enables addresses of said known errors to be reconstructed when said second logical data is next read and wherein said controlling apparatus is operative to reconstruct said addresses, using said information, when said second logical data is next read.
3. The system according to claim 1 wherein said information does not comprise an address field.
4. The system according to claim 1 wherein said earmark comprises a dummy physical level assigned to the cell.
5. The system according to claim 1 wherein at least a portion of said controlling apparatus resides in a microcontroller within a flash memory device within which said cells reside.
6. The system according to claim 1 wherein at least a portion of said controlling apparatus resides in a controller external to a flash memory device within which said cells reside.
7. The system according to claim 1 wherein the system is arranged to program the multiple earmark into a cell that contained a known error after detecting all the known errors in the flash memory cells.
8. The system according to claim 1 wherein at least two different earmarks have values that belong to different erasure regions, the erasure regions differ from symbol regions.
temporary memory;
writing apparatus for writing first logical data from said temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors;
reading apparatus for reading said physical representation from the cells, thereby to generate, and store in said temporary memory, second logical data which if read immediately is identical to said first logical data other than said known errors; and
controlling apparatus controlling said writing apparatus and said reading apparatus, the controlling apparatus is operative to identify said known errors by comparing said first logical data to second logical data read immediately after said physical representation is generated, to store information characterizing said known errors and to use said information, when said second logical data is next read, to correct said known errors;
wherein said information enables addresses of said known errors to be reconstructed when said second logical data is next read and wherein said controlling apparatus is operative to reconstruct said addresses, using said information, when said second logical data is next read;
wherein said information comprises a total number of known errors to be identified by the controlling apparatus and a serial number of a set comprising the addresses of the known errors, within a sequence, having a predetermined order, of all possible sets of the addresses of the known errors given the total number of known errors.
10. The system according to claim 9 wherein said information comprises addresses of said known errors.
11. The system according to claim 9 wherein said addresses comprise bit addresses.
12. The system according to claim 9 wherein said addresses comprise symbol addresses.
13. A method for storing a set of integers that comprises a certain number of integers in memory, the method comprising:
computing and storing at least one serial number identifying at least one respective position of the set of integers in a predetermined sequence of all possible sets of integers that comprise the certain number of integers, wherein each integer of each set has a value within a predetermined range; and
computing at least one integer from the set of integers from said at least one serial number.
14. The method according to claim 13 wherein said set of integers comprises at least one address; and wherein the predetermined range is a predetermined range of addresses.
15. The method according to claim 14 wherein said at least one address comprises at least one flash memory cell address.
16. A flash memory utilization method comprising:
writing first logical data from temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors;
reading said physical representation from the cells, thereby to generate, and store in said temporary memory, second logical data which if read immediately is identical to said first logical data other than said known errors; and
controlling said writing apparatus and said reading apparatus, wherein the controlling comprises:
identifying said known errors by comparing said first logical data to second logical data read immediately after said physical representation is generated,
storing information characterizing said known errors; wherein said information comprises (a) multiple earmarks, each earmark is stored in a cell containing at least one known error, and (b) correct logical data for each cell storing an earmark; and
using said information, when said second logical data is next read, to correct said known errors.
US12/596,439 2007-09-20 2008-09-17 Systems and methods for handling immediate data errors in flash memory Active 2030-06-05 US8365040B2 (en)
US96020707P true 2007-09-20 2007-09-20
US96094307P true 2007-10-22 2007-10-22
US99602707P true 2007-10-25 2007-10-25
US99678207P true 2007-12-05 2007-12-05
US99694807P true 2007-12-12 2007-12-12
US607807P true 2007-12-18 2007-12-18
US612007P true 2007-12-19 2007-12-19
US638508P true 2008-01-10 2008-01-10
US680608P true 2008-01-31 2008-01-31
US680508P true 2008-01-31 2008-01-31
US61006806 2008-01-31
US6476008P true 2008-03-25 2008-03-25
US6485308P true 2008-03-31 2008-03-31
US6499508P true 2008-04-08 2008-04-08
US7140408P true 2008-04-28 2008-04-28
US7146908P true 2008-04-30 2008-04-30
US7146708P true 2008-04-30 2008-04-30
US7146508P true 2008-04-30 2008-04-30
US7146408P true 2008-04-30 2008-04-30
US7146608P true 2008-04-30 2008-04-30
US7146808P true 2008-04-30 2008-04-30
US7148708P true 2008-05-01 2008-05-01
US7148608P true 2008-05-01 2008-05-01
US61071486 2008-05-01
US12941408P true 2008-06-25 2008-06-25
US12960808P true 2008-07-08 2008-07-08
US13623408P true 2008-08-20 2008-08-20
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