Source: http://www.google.com/patents/US8238853?dq=7,339,580
Timestamp: 2016-07-30 14:08:01
Document Index: 162234413

Matched Legal Cases: ['Application No. 60', 'art 401', 'art 403', 'art 401', 'art 1101', 'art 1102', 'art 1221', 'art 1231', 'art 1231', 'art 1221', 'art 1231', 'art 1211', 'art 1211', 'art 1211', 'art 1201', 'art 1211', 'art 1221', 'Application No. 200780008485', 'Application No. 07710447', 'Application No. 07763206', 'Application No. 07763471', 'Application No. 07763471', 'Application No. 10195502', 'Application No. 2008', 'Application No. 2008', 'Application No. 2008', 'Application No. 10', 'art 4', 'art 4', 'art 3', 'art 3']

Patent US8238853 - Amplitude error de-glitching circuit and method of operating - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control...http://www.google.com/patents/US8238853?utm_source=gb-gplus-sharePatent US8238853 - Amplitude error de-glitching circuit and method of operatingAdvanced Patent SearchPublication numberUS8238853 B2Publication typeGrantApplication numberUS 13/216,871Publication dateAug 7, 2012Priority dateFeb 3, 2006Fee statusPaidAlso published asUS8032097, US20070184795, US20120019319Publication number13216871, 216871, US 8238853 B2, US 8238853B2, US-B2-8238853, US8238853 B2, US8238853B2InventorsSerge F. Drogi, Vikas Vinayak, Martin A. TomaszOriginal AssigneeQuantance, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (146), Non-Patent Citations (58), Referenced by (6), Classifications (30), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetAmplitude error de-glitching circuit and method of operating
US 8238853 B2Abstract
A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The RF power amplifier system may reduce the corrective action of the amplitude loop during periods of relatively rapid changes in amplitude, and thus distortion can be further reduced.
1. An RF power amplifier system, comprising:
an RF power amplifier configured to receive and amplify an input signal to generate an output signal;
an amplitude control loop configured to determine an amplitude correction signal indicative of an amplitude difference between an amplitude of the input signal and an attenuated amplitude of the output signal; and
an amplitude limiting circuit configured to limit an amplitude swing of the amplitude correction signal to a threshold if the amplitude swing of the amplitude correction signal exceeds the threshold to generate an adjusted amplitude correction signal;
where the amplitude control loop is configured to adjust a supply voltage or bias to the RF power amplifier based upon the adjusted amplitude correction signal.
2. The RF power amplifier system of claim 1, where:
the RF power amplifier has a gain responsive to the adjusted amplitude correction signal.
3. The RF power amplifier system of claim 1, further comprising:
a variable gain amplifier configured to adjust the amplitude of the input signal in response to the adjusted amplitude correction signal.
4. A method of controlling an RF power amplifier coupled to receive and amplify an input signal to generate an output signal, the method comprising:
generating an amplitude correction signal indicative of an amplitude difference between an amplitude of the input signal and an attenuated amplitude of the output signal in an amplitude control loop;
limiting an amplitude swing of the amplitude correction signal to a threshold if the amplitude swing of the amplitude correction signal exceeds the threshold to generate an adjusted amplitude correction signal; and
adjusting a supply voltage or bias to the RF amplifier based upon the adjusted amplitude correction signal.
5. A power amplifier controller circuit for controlling a RF power amplifier, the RF power amplifier coupled to receive and amplify an input signal to generate an output signal, the power amplifier controller circuit comprising:
means for generating an amplitude correction signal indicative of an amplitude difference between an amplitude of the input signal and an attenuated amplitude of the output signal in an amplitude control loop;
means for limiting an amplitude swing of the amplitude correction signal to a threshold if the amplitude swing of the amplitude correction signal exceeds the threshold to generate an adjusted amplitude correction signal; and
means for adjusting a supply voltage or bias to the RF power amplifier based upon the adjusted amplitude correction signal.
6. The method of claim 4, further comprising adjusting a gain of the RF power amplifier based on the adjusted amplitude correction signal.
7. The method of claim 4, further comprising adjusting the amplitude of the input signal based on the adjusted amplitude correction signal.
8. The controller circuit of claim 5, further comprising means for adjusting a gain of the RF power amplifier based on the adjusted amplitude correction signal.
9. The controller circuit of claim 5, further comprising means for adjusting the amplitude of the input signal based on the adjusted amplitude correction signal.
This application is a continuation application of, and claims priority under 35 U.S.C. �120 from, U.S. patent application Ser. No. 11/670,402, entitled “Amplitude Error De-Glitching Circuit and Method of Operating,” filed on Feb. 1, 2007, now U.S. Pat. No. 8,032,097 which application claims priority wider 35 U.S.C. �119(e) from U.S. Provisional Patent Application No. 60/764,947, entitled “RF Power Amplifier with Efficiency Improvement for High Peak to Average Modulation Types,” filed on Feb. 3, 2006; and which application is a continuation-in-part application of, and claims the benefit under 35 U.S.C. �120 from U.S. patent application Ser. No. 11/429,119 entitled “Power Amplifier Controller Circuit,” filed on May 4, 2006, now U.S. Pat. No. 7,933,570 the subject matters of all of which are incorporated by reference herein in their entirety.
The RF power amplifier 104 in general includes an output transistor (not shown) for its last amplification stage. When an RF modulated signal 106 is amplified by the RF PA 104, the output transistor tends to distort the RF modulated signal 106, resulting in a wider spectral occupancy at the output signal 110 than at the input signal 106. Since the RF spectrum is shared amongst, users of the cellular telephone, a wide spectral occupancy is undesirable. Therefore, cellular telephone standards typically regulate the amount of acceptable distortion, thereby requiring that the output transistor fulfill high linearity requirements. In this regard, when the RF input signal 106 is amplitude-modulated, the output transistor of the PA 104 needs to be biased in such a way that it remains linear at the peak power transmitted. This typically results in power being wasted during the off-peak of the amplitude of the RF input signal 106, as the biasing remains fixed for the acceptable distortion at the peak power level.
Certain conventional techniques exist to provide efficiency gains in the RF PA 104. One conventional technique is EER (Envelope Elimination and Restoration). The EER technique applies the amplitude signal (not shown in FIG. 1) and the phase signal (not shown in FIG. 1) of the RF input signal 106 separately to 2 ports of the power amplifier 104, its supply voltage port (Vcc) 108 and its RF input port 107, respectively. However, the EER technique often fails to provide significant efficiency gains, because the supply voltage 108 cannot be varied in an energy-efficient way to accommodate the large variations in the amplitude signal of the RF input signal 106 and thus it fails to provide a substantial energy efficiency gain while maintaining the required linear amplification of the RF signal in the RF PA 104. This is mainly due to the difficulty in realizing a fast, accurate, wide range, and energy efficient voltage converter to drive the supply voltage of the RF PA 104.
Finally, PAs are typically used in conjunction with band pass filters that have a high electric coefficient of quality. These filters are typically of the SAW (surface acoustic wave) type. Due to their high coefficient of quality, the filters exhibit a relatively high group delay. The group delay makes it very difficult, for a correction loop to work around the arrangement of the SAW filter and the PA while still meeting the high bandwidth requirements needed for the correction of the AM-to-PM.
One embodiment of the present invention disclosed is a power amplifier controller circuit for controlling a power amplifier based upon an amplitude correction signal or amplitude error signal. The power amplifier receives and amplifies an input, signal to the power amplifier and generates an output signal, and the power amplifier controller circuit controls the power amplifier so that it operates in an efficient manner.
In a first embodiment of the present invention, the amplitude control loop comprises an amplitude comparator comparing the amplitude of the input signal with an attenuated amplitude of the output signal to generate an amplitude correction signal, and a power supply coupled to receive the amplitude correction signal and generating the adjusted supply voltage provided to the power amplifier based upon the amplitude correction signal. The power supply can be a switched mode power supply. By using the amplitude correction signal to control the supply voltage to the power amplifier, a high efficiency yet low-bandwidth power supply such as the switched mode power supply may be used to provide the adjusted supply voltage to the power amplifier.
In a second embodiment of the present invention, the amplitude correction signal is split into two or more signals with different frequency ranges and provided respectively to different types of power supplies with different levels of efficiency to generate the adjusted supply voltage provided to the power amplifier. For example, in the second embodiment, the power supplies include a first power supply with a first efficiency and a second power supply with a second efficiency higher than the first efficiency. The first power supply receives a first portion of the amplitude correction signal in a first frequency range and generates a first adjusted supply output based upon the first portion of the amplitude correction signal, and the second power supply receives a second portion of the amplitude correction signal in a second frequency range lower than the first frequency range and generates a second adjusted supply output based upon the second portion of the amplitude correction signal. The first and second adjusted supply outputs are combined to form the adjusted supply voltage provided to the power amplifier. The first power supply can be a linear regulator, and the second power supply can be a switched mode power supply. By dividing the amplitude correction signal into two or more signals with different frequency ranges, the second embodiment of the present invention has the additional advantage that the switched mode power supply may be implemented with even, narrower bandwidth as compared to the first embodiment without significantly sacrificing efficiency. A narrower bandwidth power supply or a variable power supply with a smaller range of voltage variation is easier to implement.
In a fourth embodiment of the present invention, the amplitude loop operates in a manner which reduces the loop corrective action during periods of relatively rapid amplitude change in the signal amplified by the PA. These periods of relatively rapid amplitude change may be associated with certain types of transitions in the modulation, in which the signal modulation passes through or near the constellation origin. A relative decrease in amplitude of the signal can indicate this type of transition in the modulation.
The PA output amplitude lags the input amplitude due to the inherent delay through the PA. During the period when the signal amplitude is changing very rapidly, a temporary peaking of the difference in amplitude between input and output may result due to this lag. Since the amplitude loop described in prior embodiments generates an amplitude correction signal based on the difference between the amplitudes of the input and output, the amplitude correction signal may erroneously adjust the supply voltage to the PA or the gain of the VGA (if present) during these periods, adding distortion to the output signal.
Thus, in this embodiment, by reducing the corrective action of the loop during periods associated with periods of relatively rapid changes in amplitude, the distortion just described can be reduced.
FIG. 10A is a block diagram of an example of an RF power amplifier system according to the fourth embodiment.
FIG. 10B is a block diagram of an example of an RF power amplifier system according to the fourth embodiment.
FIG. 10C is a block diagram of an example of an RF power amplifier system according to the fourth embodiment.
FIG. 10D is a block diagram of an example of an RF power amplifier system according to the fourth embodiment.
FIG. 11 is a series of charts illustrating an example of signal modulation.
FIG. 12 is a series of charts illustrating an example of the effect of a loop gain adjust block in an RF power amplifier system according to the fourth embodiment.
FIG. 13 is a timing diagram illustrating an example of a modulation state transition signal according to the fourth embodiment.
FIG. 14 illustrates an example of a method of operating an RF power amplifier system according to the fourth embodiment.
FIG. 15 illustrates an example of a method of operating an RF power amplifier system according to the fourth embodiment.
FIG. 16 illustrates examples of a method of operating an RF power amplifier system according to the fourth embodiment.
FIG. 17 illustrates an example of a method of operating an RF power amplifier system according to the fourth embodiment.
The PA controller circuit 202 may also adjust the phase and amplitude of the signal 204 to allow for power control and PA ramping, in accordance with information received through the configuration signals 209. Since the PA controller circuit 202 is aware of the voltage at the output and the current in the power amplifier 104, it can also adjust for load variations at an antenna (not shown herein) that may be used with the PA. If a directional coupler (not shown) is used to teed the attenuated amplitude of the signal 204, the PA controller 202 can adjust the forward power while controlling the PA operation point as it is aware of the voltage and current at node 208.
The phase control loop includes two limiters 312, 314, a phase comparator 316, a loop filter (PLF (Phase Loop Lifter)) 318, and a phase shifter 320. To achieve stability over all conditions, the phase comparator 316 is of an adequate type with a capture range greater than 2*PI. To achieve this, a combination of adjustable delay elements and frequency dividers may be used. Also a phase sub-ranging system can be used since the dynamic phase variations that the phase correction loop processes are limited in amplitude. A sub-ranging phase control block (not shown) could be one of the constituents of the phase comparator 316 used with this system. Advantages of using sub-ranging in the phase comparator 316 are stability and good noise.
Referring to FIG. 3A, the phase control loop monitors the RF input signal 204 from the transmitter IC 102 (not shown in FIG. 3A) and compares the phase of the RF input signal 204 with the phase of the output signal 110 of the PA 104 attenuated 326 by the adjusted variable attenuator (RFFA) 306, resulting in a control signal 319 that varies the phase of the RF signal 206 coming out of the phase shifter 320. More specifically, the limiter 312 receives the RF input signal 204 from the TXIC 102 and outputs to the comparator 316 an amplitude limited signal 324 mathematically representative of the phase of its input signal. The limiter 314 also receives the output signal 110 of the PA 104 as attenuated 326 by the adjusted variable attenuator (RFFA) 306, and outputs its phase signal 325 to the comparator 316. The comparator 316 compares the phases of the output signals 324, 325 of the two limiters 312, 314, and generates a phase error signal 317. Note that the term “phase error signal” is used herein synonymously with the term “phase correction signal.” The phase error signal 317 is filtered by the loop filter (PLF) 318 to generate the phase control signal 319. The loop filter 318 completes the phase loop and provides the necessary gain, bandwidth limitation, and loop stability required for the phase loop to function properly. The particular loop filter used here can be of any type, and can include multiple integration and derivation stages so as to satisfy the best loop performance. The types of the loop filter may include classical types I, II, and the like. A particularity of this phase loop design is that the group delay through the PA 104 must be taken into account for stability reasons. This is achieved by choosing the proper pole-zero placement in the loop filter and may include delay compensation. The phase control signal 319 is input to the phase shifter 320 to control the shifting, of the phase of the input RF signal 206 so that the phase of the output signal 110 dynamically matches the phase of the transmitter signal 204.
FIG. 3B illustrates a method of controlling the amplitude control loop of a RF PA 104 in an RF PA system, according to the first embodiment of the present invention. Referring to both FIGS. 3A and 3B, as the process begins 352, the comparator 308 compares 354 the amplitude 323 of the RF input signal 204 with the attenuated amplitude 322 of the RF output signal 110 from the PA 104 to generate an amplitude correction signal 309. The SMPS 310 generates 358 an adjusted supply voltage 208 provided to the PA 104 based upon the amplitude correction signal 309, and the process ends, 360.
FIG. 4A illustrates an RF PA system, according to a second embodiment of the present invention. The RF PA system illustrated in FIG. 4A is substantially the same as the RF transmitter circuit illustrated in FIG. 3A, except that (i) the amplitude correction signal 309 is split into two signals, a high frequency amplitude correction signal 401 that is fed into a high frequency path including a linear regulator 402 and a low frequency amplitude correction signal 403 that is fed into a low frequency path including an SMPS 404 and that (ii) the outputs of the linear regulator 402 and the SMPS 404 are combined in the adder block 406 to generate the adjusted supply voltage 208 to the PA 104. For example, a simple current adding node, a small, high frequency transformer or other types of active electronic solutions can be used as the adder block 406. Any other types of power combiner circuits may be used as the adder block 406.
P bat=Effs*I pa *V pa with Effs=1.1,
If the average input voltage Vpa to the PA 104 is significantly lower than supply voltage Vcc of the battery, the SMPS 404 achieves much lower power consumption. While the linear regulator 402 is generally less efficient than the SMPS 404, the linear regulator 402 processing the high frequency part 401 of the amplitude correction signal 309 does not make the overall RP PA system inefficient in any significant way, because most of the energy of the amplitude correction signal 309 is contained in the low frequency part 403 rather than the high frequency part 401. This is explained below with reference to FIGS. 8 and 9.
4 QAM Signal
100 KHz (up to 40
Adjusted supply
(Through SMPS MHz)
voltage 208 to 404)
PA = 60% of Vbat Regulator 402)
energy in adjusted
supply voltage 208
to PA 104 in
conversion at 60%
of Vbat
using high and low
bandwidth paths
FIG. 5A illustrates an RF PA system, according to a third embodiment of the present invention. The RF transmitter system illustrated in FIG. 5A is substantially the same as the RP transmitter system illustrated in FIG. 4A, except that the gain control block 506 and the variable gain amplifier 502 are added to provide an additional means to control the efficiency of the PA 104 and the overall RF transmitter system. Although the third embodiment of FIG. 5A is illustrated herein as an improvement to the second embodiment of FIG. 4A, note that the same concepts of the third embodiment of FIG. 5A can also be used to improve the first embodiment of FIG. 3A.
FIG. 5B illustrates a method of controlling the amplitude control loop of a RF PA in an RF transmitter system, in accordance with the third embodiment of the present invention. The method illustrated in FIG. 5B is substantially the same as the method illustrated in FIG. 5A, except that step 502 is added. In step 502, the input signal 508 to the PA 104 is adjusted, by use of a variable gain amplifier 502, based upon the amplitude correction signal 309. Therefore, the method of FIG. 5B is provided with an additional means for controlling the efficiency of the PA 104 and the overall RF PA system.
FIG. 6 illustrates a method of controlling the phase control loop of a RF PA in an RF PA system in accordance with the present invention. The phase control method of FIG. 6 can be used with any one of the methods of controlling the amplitude correction loops described in FIGS. 3B, 4B, and 5B, as shown in FIGS. 3A, 4A, and 5A. The method of FIG. 6 will be explained in conjunction with FIGS. 3A, 4A, and 5A.
As the process begins 602, the comparator 316 compares 604 the phase of the RF input signal 204 with the phase of the attenuated RF output signal 326 from the PA 104 to generate the phase error signal 317. The phase error signal 316 is filtered 606 by the loop filter (PLF) 318 to generate the phase control signal 319. The phase of the input RF signal 204 is shifted 608 based upon the phase control signal 319 so that the difference between the phase of the input signal 204 and the phase of the output RF signal 110 is held constant, and the process ends 610.
FIG. 8 illustrates the simulation results of an example of a time domain waveform present at node 509 (which voltage would be the same as the voltage at node 309) of FIG. 5A, and FIG. 9 illustrates the simulation results of an example of a time domain waveform present at nodes 401 and 403 of FIG. 5A, both for a typical commercial WCDMA PA with 3.4 V nominal supply voltage and WCDMA modulation using 3.84 Mchips per second. The loop voltage versus time on FIG. 8 shows that the loops maintain a voltage much lower than 2.5 V most of the time, except for some short instants. This is due to the signals amplitude characteristics which require high peaks but a much lower average. In FIG. 9, the voltages 401 and 403 are shown. They correspond to the voltage 309 (or 509) after filtering by a 100 kHz high pass filter 410 and a 100 kHz low pass filter 411, respectively. It can be seen that the low pass filtered signal 403 is almost a DC signal of value 1.9 V, while the high pass filtered signal 401 is a band limited waveform having a low DC value and an rms value of only 0.2V. If the 1.9V is generated with an efficiency of 90% by an easy-to-realize low output bandwidth SMPS 404, and the 0.2V is generated with an efficiency of 60% using a linear amplifier 402, the signal 309 can be generated with a combined efficiency of (1.9+0.2)/(1.9/0.9+0.2/0.6)=87.5%. This is much better than generating the signal 309 using a linear regulator with an average efficiency of (1.9/3.4)/1.05=53%. While it should be understood that the calculations presented herein are engineering approximations, the potential benefit in battery life is clearly apparent through this example.
FIG. 10A includes elements of an RF PA system according to the fourth embodiment. The RF PA system illustrated in FIG. 10A is similar to the RF PA system illustrated in FIG. 5A. In FIG. 10A, the amplitude control loop section includes additional elements shown within detail 1002. Although the embodiments described with reference to FIG. 10A are illustrated herein as improvements to the third embodiment of FIG. 5A, note that the same concepts of the embodiments of FIG. 10A can also be used to improve the first and second embodiments described with reference to FIGS. 3A and 4A, respectively.
It is instructive to describe an example of signals which may be present in the RF PA system illustrated in FIG. 10A. FIG. 11 is a chart illustrating an example of signal modulation that may be applied as the input signal 204. For example, the input signal 204 may be modulated with a quadrature phase shift keying (QPSK) modulation. Chart 1101 is a constellation diagram illustrating QPSK modulation. Transition 1105 shows the trajectory from point 1 to point 2. Transition 1106 shows the trajectory from point 2 to point 3. Point Y marks a location on the transition 1106 where the transition 1106 passes through or near the origin. As indicated by the arrows on trajectories 1105 and 1106, in this example, as time passes the trajectory goes from point 1 to point 2, and from point 2 through point Y to point 3.
Chart 1102 shows the amplitude 1107 of the modulated signal versus time. Points 1, 2, Y, and 3 are indicated to show the position of the trajectory with respect to these points. When the trajectory 1106 passes through or near point Y, the amplitude 1107 passes through a minimum. Note that in this example shown, the time spent at point 2 is longer that the time transitioning between points 1 and 2, and points 2 and 3. Thus, a relatively rapid amplitude reduction results when the modulated signal passes through or near the constellation origin in the modulation.
FIG. 12 is a series of charts illustrating the modulation shown in FIG. 11 applied as the RF input signal 204 of FIG. 10A, and shows a detail 1002 of the amplitude loop to show the signals present in the circuit. Chart 1221 depicts the amplitudes seen by amplitude comparator 308, corresponding to the amplitude of input signal 204, and the amplitude of output signal 110 after passing through attenuator 306.
Amplitude comparator input signal 323 is equivalent to amplitude signal 1107 in FIG. 11. Thus, in this example, the signal passes through modulation points 1, 2, and 3, transitioning through or near constellation origin point Y during the transition 1106 from point 2 to point 3. The time spent at the various modulation points are as shown in chart 1231. The attenuated output signal 322, however, lags due to the delay through the RF PA by time 1205. Thus, chart 1231 shows a delayed set of modulation points 1′, 2′, and 3′, corresponding to the modulation points in the PA output 110 and, consequently, in the attenuated output signal 322.
By inspection of chart 1221, it can be seen that the inputs 323 and 322 to comparator 308 diverge for a period around the time shown in chart 1231 as points Y and Y′, due to the relatively rapid amplitude change of the input signal 204 as the modulated signal moves through or near the constellation origin point Y in the modulation. The amplitude correction signal 309 from comparator 308 is shown in chart 1211. The amplitude correction signal 309 represents the difference of signals 322 and 323, and thus exhibits the rapid glitch-shaped signal depicted in chart 1211.
Referring back to FIG. 10A, passing signal 309 as depicted in chart 1211 directly to gain control block 506 (by omitting loop gain adjust block 1008) may cause any or all of the elements SMPS 404, linear regulator 402, and VGA 502 to respond to the glitch-shaped amplitude correction signal 309, resulting in some distortion at PA output 110. Therefore, it is advantageous to reduce the action of the loop and thus limit the degree to which the SMPS 404 and linear regulator 402 may adjust the voltage to the PA, and the degree to which the VGA 502 would adjust its gain, during the periods of rapid amplitude change of the input signal. While periods of rapid amplitude change of the input signal are shown here as associated with the signal transition passing through or near the constellation origin in the modulation, rapid amplitude changes at the input signal may occur at other times, depending, for example, on the type of modulation used. In these cases, as well, it is advantageous to reduce the action of the loop
One example of reducing the action of the loop is to reduce the gain of the loop. In one example, the gain of the loop can be reduced by reducing the level of the signals in the correction path of the loop. One convenient means of controlling the correction path of the loop is to adjust the amplitude correction signal 309 before it is passed on to gain control block 506. Additional methods include reducing the degree to which the power supply 104 (comprised in this example of linear regulator 402 or SMPS 404) adjusts supply voltage 208 to PA. The degree to which VGA 502 adjusts its gain based on gain adjust signal 504 may also be reduced. Any method which reduces the gain of the loop may be used.
Referring to FIG. 10A, in an example of the fourth embodiment, the loop gain adjust block 1008 is configured to pass a reduced level of amplitude correction signal 309 as the adjusted amplitude correction signal 1010 when a rapid change in the amplitude of input signal 204 is indicated.
One example of detecting a rapid change in amplitude of the input signal is shown in circuitry 1090. Differentiator 1080 is employed to measure the rate of change of input amplitude 323. Differentiator output 1081 is provided to the magnitude block 1082. Since a differentiator may indicate a negative output for a decreasing signal and a positive output for an increasing signal, the magnitude of the output 1081 can be obtained using the magnitude block 1082. Thus, the output magnitude 1083 is the magnitude of the differentiator output 1081.
Output magnitude 1083 of differentiator 1080 increases in value with an increase in the rate of change in input amplitude 323. Inverter 1084 inverts output magnitude 1083 of differentiator 1080, so that inverter output signal 1085 fed to loop gain adjust block 1008 decreases in value with an increase in the rate of change of amplitude of input amplitude 323. In this example, loop gain adjust block 1008 is configured to reduce the level of amplitude correction signal 309 to generate the adjusted amplitude correction signal 1010, in response to a decrease in the inverter output signal 1085. Thus, when input signal 204 experiences a rapid change in amplitude, the signal level at inverter output 1085 decreases, and the level of adjusted amplitude correction signal 1010 is decreased relative to amplitude correction signal 309. This in turn reduces the gain of the loop during periods when the amplitude correction signal 309 may be generating a glitch-shaped signal, as previously described, and so reduces distortion caused by the response of SMPS 404 and linear regulator 402.
While circuitry 1090 describes one example of detecting a rapid change in amplitude of the input signal 204, any other method may be used. A rapid change of amplitude may be detected in the output signal 110, or the attenuated output signal 326, either as an alternative to detecting a rapid change in amplitude of the input signal 204, or in addition to detecting a rapid change in amplitude of the input signal 204. There are some benefits to detecting a rapid change in amplitude at both the input signal 204 and output signal 110, as will be described later.
As described previously, periods of rapid amplitude change of the input signal 204 are often associated with signal transitions passing through or near the constellation origin in the modulation. Since these signal transitions are also associated with a relative decrease in signal amplitude, a relative decrease in the detected input amplitude may be associated, with a period of rapid input amplitude change. Thus, loop gain adjust block 1008 may alternatively use the amplitude 323 of the input signal 204 to reduce the level of amplitude correction signal 309. As the detected input amplitude 323 is reduced, an adjusted amplitude correction signal 1010 is reduced by the loop gain adjust block 1008. The adjusted amplitude correction signal 1010 is then passed on to the gain control block 506. FIG. 12 shows an example of the adjusted amplitude correction signal 1010, shown in chart 1201. Thus, as in the previous example, the gain of the loop is reduced during periods when the amplitude correction signal 309 may be generating a glitch-shaped signal, and so the distortion caused by the response of SMPS 404 and linear regulator 402 is reduced.
One example of the loop gain adjust block 1008 is a multiplier. Using this example of loop gain adjust block 1008 and the example described which uses input amplitude 323 to adjust adjusted amplitude correction signal 1010, the loop gain adjust block 1008 operates as follows. The input amplitude signal 323 is multiplied with the amplitude correction signal 309 in the loop gain adjust block 1008. When the amplitude of input signal 204 is relatively high, the amplitude correction signal 309 is multiplied with a signal that is relatively high. Similarly, when the amplitude of the input signal 204 is relatively low, the amplitude correction signal 309 is multiplied by a signal that is relatively low. Since the periods of rapid amplitude change of the input signal 204 are associated with a relative reduction in amplitude (as the input signal 204 passes through a transition through or near the constellation origin in the modulation), multiplying the signal in this manner accomplishes the goal of reducing the action of the loop during these periods and reduces distortion at the output 110.
As another example, the loop gain adjust block 1008 may be a variable gain amplifier. In this example, the input amplitude signal 323 is used as the control for the gain of the variable gain, amplifier. When the input signal 204 is relatively low, the gain of the variable gain amplifier may be reduced to reduce the level of amplitude correction signal 304, and generate the adjusted amplitude correction signal 1010. Although a multiplier and a variable gain amplifier have been described as part of a loop gain adjust block 1008 to reduce the level of the amplitude correction signal 304, any circuit that can scale a first signal with a second signal can be used to reduce the level of the amplitude correction signal 304.
An additional benefit of reducing the level of a glitch in the amplitude correction signal 309 is as follows. Circuitry controlled by adjusted amplitude correction signal 1010 may be optimized to handle a modest degree of amplitude adjustment. For example, if the amplitude correction signal 309 of chart 1211 as shown in FIG. 12 were applied to control the gain adjustment input 504 of VGA 502, it is possible that signal level would exceed the normal operating range of gain control signal 504. In response, VGA 502 could generate additional distortion as it abruptly reaches its maximum or minimum gain setting.
Note also that, while the action of the amplitude correction loop is periodically reduced as described, the overall effect on the normal corrective action of the amplitude loop is minimal. Referring back to FIG. 11, the time around point Y, in which the adjusted amplitude correction signal 1010 is reduced as described above, is relatively small as compared with the time spent at modulation points 1, 2, or 3. Although, during such a time, the operation of the amplitude control loop approaches an open-loop condition and a small amount of residual distortion may be introduced, most of the time the amplitude loop operates in a closed loop manner. Note that even while in the open-loop condition, the PA output 110 still tracks the input 204, but with less accuracy than in the closed-loop condition. Additionally, note that the output signal amplitude 110 is relatively low during the time when the loop approaches an open-loop condition. As a result, the power of the residual distortion in the output signal 110 during this time is relatively small.
As mentioned before, FIGS. 10A, 10B, 10C, and 10D are shown as improvements to the third embodiment of FIG. 5A, and therefore show the adjusted amplitude correction signal 1010, 1020, 1030, and 1040 as coupled to gain control block 506 in FIGS. 10A, 10B, 10C, and 10D, respectively. However, the same concepts of the embodiment of FIG. 10A can also be used to improve the first and second embodiments of FIGS. 3A and 4A, respectively, and as applied to these embodiments, the adjusted amplitude correction signal would be coupled to the appropriate blocks as shown in FIGS. 3A and 4A.
Also, while gain control block 506 is shown as adjusting the gain of VGA 502, gain control block 506 may alternatively adjust the gain of PA 104, if PA 104 is of a type which allows such a gain adjustment. Thus, in any of the examples described, an adjustment of a gain of VGA 502 may be considered equivalent to an adjustment of a gain of PA 104.
Referring back to FIG. 10A, in another example of the fourth embodiment, the attenuated amplitude 322 of the output signal 110 is input to the loop gain adjust block 1008. As shown in FIG. 12, chart 1221, a relative reduction in amplitude of the output signal 110 is correlated with a transition through or near the constellation origin in the modulation, which results in a relatively rapid amplitude change. If the attenuated amplitude 322 of the output signal 110 is multiplied with the amplitude correction signal 309 to generate the adjusted amplitude correction signal 1010, the action of the loop during these periods is reduced, and results in reduced distortion at the output 110.
FIG. 10A includes elements of a block diagram of an RF power amplifier system according to another example of the fourth embodiment. In this example, the input amplitude 323 and the attenuated amplitude 322 of the output signal 110 are both input to the correction block 1008. Using a multiplier as an example of the correction block 1008 in this example, the amplitude correction signal 309 is multiplied by both the input amplitude signal 323 and the attenuated output amplitude signal 322. Thus, if either the input amplitude signal 323 or the attenuated output amplitude signal 322 is relatively low, the contribution of a large amplitude error on the amplitude correction signal 309 to the adjusted amplitude error signal 1010 is reduced. If there is substantial delay between input 204 and output 110, there is a benefit to this example, since both leading and failing edges of the large amplitude error may be reduced.
FIG. 10A includes elements of a block diagram of an RF power amplifier system according to yet another example. Amplitude adjust blocks 1004 and 1006 can provide a lower limit to the input amplitude 323 and attenuated output amplitude 322, respectively, before they are input to the amplitude comparator 308. Thus, as the input amplitude signal 323 and the attenuated output amplitude signal 322 reduce in amplitude during a transition through or near the constellation origin in the modulation, the inputs 1012 and 1014 to the amplitude comparator reduce to a modest and relatively equal value, reducing the gain of the amplitude loop, and reducing the amplitude of the glitch at the adjusted amplitude correction signal 1010.
While FIG. 10A describes several techniques in which the gain of the loop may be reduced in response to a relative decrease in signal amplitude, there are other methods as well. For example, the response of VGA 502 to VGA control signal 504 may be reduced, as well as the response of linear regulator 402 and SMPS 404 to control signal 509. Any method of reducing gain of the loop may be used.
FIG. 10B is a block diagram of an RF power amplifier system which includes elements of another example. The RF power amplifier system includes a switching circuit 1022 coupled to the output of the amplitude comparator 309. A correction switch control block 1018 controls the switching circuit 1022 in response to the input amplitude 323. Although the correction switch control block 1018 and the switching circuit 1022 have been described as distinct, the correction switch control block 1018 and the switching circuit 1022 may be combined together into a single switching circuit.
in this example the correction switch control block 1018 compares the amplitude of the input amplitude 323 to a threshold. The threshold may be represented in a variety of ways. For example, the threshold may be a voltage or a current. The threshold may be generated from a value stored in a register or generated by a resistor network. Any technique appropriate for the comparison in the correction switch control block 1018 may be used.
In response to the comparison, the correction switch control block 1018 controls the switching circuit 1022 to selectively pass the amplitude correction signal 309. For example, if the level of the input amplitude 323 is below the threshold, the switching circuit 1018 may block the amplitude correction signal 309. Since the rapid amplitude changes during modulation state transitions through or near the constellation origin are correlated to a relative decrease in amplitude, the amplitude errors on the amplitude correction signal 309 would be blocked from being passed to adjusted amplitude correction signal 1020 during these times, thus blocking the glitch at the amplitude correction signal 309.
The switching, circuit 1022 may take many forms. For example, the switching circuit 1022 may be a single transistor. When the amplitude is greater than the threshold, the correction switch control block 1018 turns on the transistor to pass the amplitude correction signal 309. Alternatively, when the amplitude is less than the threshold, the correction switch control block 1018 turns off the transistor to block the amplitude correction signal 309. A capacitor or other charge storage device may be present within the switching circuit 1022 to hold the value of the amplitude correction signal 309 prior to turning off the transistor.
Alternatively, the switching circuit 1022 may be a multiplier as described above. For example, the correction switch control block 1018 may generate a two level signal from comparing the amplitude of input signal 323 to the threshold. Since two levels are generated from the correction switch control block 1018, even if the multiplier is an analog multiplier, it can be controlled such that the amplitude correction signal 309 is passed or blocked. For example, the two levels can be 1 and 0. Any circuit that can be used to selectively pass and block the amplitude correction signal 309 may be used as a switching circuit 1022.
In general, referring to FIG. 10A, the relationship of a signal used by the loop gain adjust block 1008 to adjust the amplitude correction signal 309 may, but need not have a linear relationship to the effect on the amplitude correction signal 309. For example, with multiplication using the amplitude as described before, the amplitude has a linear relationship to the scaling of the amplitude correction signal 309. In contrast, with the correction switch control block 1018 (FIG. 10B) and the multiplier described above, the relationship between the amplitude and the scaling of the amplitude correction signal 309 has a discrete step, thus it is non-linear. Any relationship of the amplitude to the scaling of the amplitude correction signal 309 may be used.
FIG. 10C is a block diagram of an RF PA system according to another example. The detail 1002 of the amplitude loop now includes a modulation state transition indicator circuit 1028. The modulation state transition indicator circuit 1028 generates a modulation state transition signal 1029, indicating a state transition of modulation of the input signal 204 in which the modulation state transitions through or near the constellation origin. The loop gain adjust block 1032 is responsive to the modulation state transition signal 1029. Although the modulation state transition signal 1029 indicates these transitions in the state of the modulation of the input signal 204, it may, but need not be directly generated from the input signal 204. As described below, various other signals may exist that include information on the modulation of the input signal 204 and may be used to generate the modulation state transition signal 1029.
For example, a digital signal processor may generate the modulation for an in-phase component I and a quadrature-phase component Q used to generate a QPSK modulated signal. In QPSK, a 180 degree phase shift occurs when both the in-phase component I and the quadrature-phase component Q change phase during the same transition. This phase transition occurs at a time synchronous with the modulation state transitioning through or near the constellation origin. Additionally, the digital signal processor may have timing information about the modulation that is synchronous with any rapid amplitude change. Thus, the digital signal processor may provide information to generate the modulation state transition signal 1029.
FIG. 13 is a timing diagram illustrating an example of a modulation state transition signal 1029 according to the fourth embodiment. The modulation state transition indicator circuit 1028 generates a modulation state transition signal 1029 from the modulation information of the in-phase component I and the quadrature-phase component Q. In this example, the points 1, 2, Y, and 3 correspond to the same points illustrated in FIG. 11. At point Y, both the in-phase component I and the quadrature-phase component Q are transitioning to the opposite state. During such a transition, the transition passes the origin of the constellation diagram, resulting in a 180 degree phase shift as well as a relative decrease in signal amplitude. Because the modulation state transition indicator circuit 1028 has this information, the modulation state transition signal 1029 may be generated. In this example the modulation state transition signal 1029 is in the block state for a period of time somewhat shorter than the transition time from points 2 to 3.
Although a particular width, shape, timing, and other characteristics of the modulation state transition signal 1029 has been described, the modulation state transition signal 1029 may have any width, shape, timing, or other characteristics as needed to reduce distortions due to amplitude errors. In addition, the modulation state signal 1029 may have a triangular, continuous, or other shape with more than two levels.
Although the use of a QPSK signal has been described above as illustration, any modulation format from which amplitude transition information is available or may be obtained may be used to generate the modulation state transition signal 1029. More complex modulation, including QAM and OFDM, may include various periods within the modulated signal which result in rapid amplitude changes, which in turn may cause glitches in the amplitude loop as described. Any information about the timing and nature of amplitude changes may be used by the modulation state transition indicator 1028 to determine the modulation state signal 1029, even if these amplitude changes occur during periods outside of a modulation transition period.
FIG. 10C includes elements of a block diagram of RF power amplifier system according to another example. Amplitude adjust blocks 1004 and 1006 may adjust the input amplitude 323 and attenuated output amplitude 322, respectively, before they are input to the amplitude comparator 308, in response to the modulation state transition signal 1029. For example, if the modulation state transition signal indicates a period in which the modulation state transitions through or near the constellation origin, the amplitude adjust blocks 1004 and 1006 may cause the inputs 1012 and 1014 to the amplitude comparator to be limited such that they are not reduced below a modest and relatively equal value. As a result, the gain of the amplitude loop is reduced, reducing the amplitude of the glitch at the adjusted amplitude correction signal 1010.
While FIG. 10C describes several methods in which the gain of the loop may be reduced in response to the modulation state transition signal 1029, there are other methods as well. For example, the response of VGA 502 to VGA control signal 504 may be reduced, as well as the response of linear regulator 402 and SMPS 404 to control signal 509. Any method of reducing gain of the loop may be used.
FIG. 10D is a block diagram of a RF PA system according to another example. The RF PA system includes a correction limiter circuit 1042. The correction limiter circuit 1042 is to limit an amplitude of the amplitude correction signal 309 to generate an adjusted amplitude correction signal 1040. The correction limiter circuit 1042 is to limit the amplitude of the amplitude correction signal if a magnitude of the amplitude correction signal 309 exceeds a threshold.
Any of a variety of circuits may be used for the correction limiter circuit 1042. For example a pair of diodes may limit the amplitude of the amplitude correction signal 309. Alternatively, an amplifier may include an output level control to limit the output swing. Any circuit that can limit, clip, or otherwise reduce the amplitude of a signal according to its amplitude may be used as a correction limiter circuit 1042.
FIG. 14 illustrates an example of a method of operating an RF power amplifier system according to the fourth embodiment. The RF power amplifier coupled to receive and amplify an input signal to generate an output signal. In this example, the method includes generating an amplitude correction signal indicative of an amplitude difference between an amplitude of the input signal and an attenuated amplitude of the output signal in an amplitude control loop in 1402, reducing an action of the amplitude control loop during rapid amplitude changes in the input signal in 1403, and adjusting a supply voltage to the RF amplifier based upon the adjusted amplitude correction signal in 1408. By reducing the action of the amplitude control loop distortion of the signal can be reduced, as described above.
FIG. 15 illustrates an example of a method of operating an RF power amplifier system according to the fourth embodiment. In this example, the method includes generating an amplitude correction signal indicative of an amplitude difference between an amplitude of the input signal and an attenuated amplitude of the output signal in an amplitude control loop in 1402, measuring a characteristic of at least one of the input signal and the output signal in 1404, adjusting the amplitude correction signal to generate an adjusted amplitude correction signal based upon the measured characteristic in 1406, and adjusting a supply voltage to the RF amplifier based upon the adjusted amplitude correction signal in 1408.
As described above, a variety of circuits are capable of generating the amplitude correction signal. Thus generating the amplitude correction signal in 1402 can include detecting the amplitude of the input and output signals in detectors, coupling power from the input or output signals, attenuating the input and output signals, or the like.
FIG. 16 illustrates examples of a method of operating an RF power amplifier system according to the fourth embodiment. Measuring the characteristic of at least one of the input signal and the output signal in 1404 includes a variety of techniques. In one example, the method includes measuring an amplitude of at least one of the input signal and the output signal in 1502, and scaling the amplitude correction signal based upon the measured amplitude in 1504 to generate an adjusted amplitude correction signal. Thus, the amplitude correction signal is adjusted in response to the input signal, the output signal, or both. As described above, such adjustment can include multiplying, scaling, adjusting gain of a VGA, controlling a switch, or the like.
In another example of a method of operating an RF power amplifier, the method includes limiting an amplitude of the amplitude correction signal in 1508 to generate an adjusted amplitude correction signal. As described above, by limiting the amplitude of the amplitude correction signal effectively reduces the gain of the amplitude loop. As a result, glitches introduced by rapid amplitude changes in the input signal are reduced.
In another example of a method of operating an RF power amplifier, the method includes determining a state of modulation on the input signal in 1510, and adjusting the amplitude correction signal based upon the state of the modulation in 1512 to generate an adjusted amplitude correction signal. As described above, the state of the modulation can have information about rapid amplitude changes and other transitions that can introduce distortion into the output signal. By adjusting the amplitude correction signal in 1512 in response to the modulation state, such distortions can be reduced.
FIG. 17 illustrates an example of measuring the characteristic and adjusting the amplitude correction signal in FIG. 14. In this example, the method includes limiting the measured amplitude to be greater than a minimum value in 1506. As described above, the measured amplitude can be limited to be greater than a minimum value with amplitude adjust blocks. As can be seen in this example, the measured amplitude is limited before being used to generate the amplitude correction signal. The amplitude correction signal so generated is adjusted relative to an amplitude correction signal if there were no limiting of the measured amplitude. As a result, the amplitude correction signal is the adjusted amplitude correction signal.
Once an adjusted amplitude correction signal is generated, a supply voltage to the RF amplifier can be adjusted based upon the adjusted amplitude correction signal in 1408 as described above.
Another example includes a power amplifier controller circuit for controlling a power amplifier. The power amplifier coupled to receive and amplify an input signal to generate an output signal. The power amplifier controller circuit includes means for generating an amplitude correction signal indicative of an amplitude difference between an amplitude of the input signal and an attenuated amplitude of the output signal in an amplitude control loop, means for reducing an action of the amplitude control loop during rapid amplitude changes in the input signal, and means for adjusting a supply voltage to the RF amplifier based upon the amplitude correction signal.
In another example, the power amplifier controller circuit includes means for measuring a characteristic of at least one of the input signal and the output signal, and means for adjusting the amplitude correction signal to generate an adjusted amplitude correction signal based upon the measured characteristic.
In another example, the power amplifier controller circuit includes means for measuring an amplitude of at least one of the input signal the output signal, and means for scaling the amplitude correction signal based upon the measured amplitude to generate an adjusted amplitude correction signal.
In another example, the power amplifier controller circuit includes means for limiting the measured amplitude to be greater than a minimum value.
In another example, the power amplifier controller circuit includes means for limiting an amplitude of the amplitude correction signal to generate an adjusted amplitude correction signal.
In another example, the power amplifier controller circuit includes means for determining a state of modulation on the input signal, and means for adjusting the amplitude correction signal based upon the state of the modulation to generate an adjusted amplitude correction signal.
As described above, various circuits, systems, configurations, and the like have been described as part of a power amplifier controller circuit or power amplifier system. Such circuitry describes examples of the means for performing the functions described above.
in general, any combination of the above described systems may be implemented in one or more circuits. Referring to FIG. 10A, in one example, the loop gain adjust block 1008 is configured to generate an adjusted amplitude correction signal 1010 on an output in response to a characteristic of a signal on at least one of the inputs to the amplitude comparator 308. In FIG. 10A an output of an amplitude detector 323 adjusts the amplitude correction signal 309 in the loop gain adjust block 1008. Thus, the characteristic of the input to the amplitude comparator 308 is the amplitude of one or both of the amplitude of the input signal 204 and the output signal 110.
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