Source: http://www.google.com/patents/US5106787?ie=ISO-8859-1
Timestamp: 2015-05-05 05:59:55
Document Index: 443373173

Matched Legal Cases: ['art 12', 'art 12', 'art 14', 'art 14', 'art 14', 'art 10', 'art 12', 'art 12', 'arts 10', 'art 14', 'art 16']

Patent US5106787 - Method for high vacuum controlled ramping curing furnace for SOG planarization - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn apparatus is described for vacuum degassing and curing a spin-on-glass layer on an article. The machine has a chamber into which an article, such as at least one or more semiconductor wafers are moved by appropriate means. Means are provided for causing the chamber to be evacuated and for continuing...http://www.google.com/patents/US5106787?utm_source=gb-gplus-sharePatent US5106787 - Method for high vacuum controlled ramping curing furnace for SOG planarizationAdvanced Patent SearchPublication numberUS5106787 APublication typeGrantApplication numberUS 07/618,199Publication dateApr 21, 1992Filing dateNov 19, 1990Priority dateNov 19, 1990Fee statusPaidPublication number07618199, 618199, US 5106787 A, US 5106787A, US-A-5106787, US5106787 A, US5106787AInventorsDaniel L. W. YenOriginal AssigneeTaiwan Semiconductor Manufacturing Co.Export CitationBiBTeX, EndNote, RefManPatent Citations (6), Non-Patent Citations (6), Referenced by (23), Classifications (14), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod for high vacuum controlled ramping curing furnace for SOG planarization
US 5106787 AAbstract
1. A method for vacuum degassing and curing at least one article comprising:providing a chamber; moving said at least one article to be subjected to vacuum degassing and curing into said chamber; providing a vacuum of less than about 100 mtorr. in said chamber for vacuum degassing said article; maintaining the temperature of said article at a substantially constant level within a first range of temperature during the said vacuum degassing; ramping the temperature at a controlled rate from the said first range of temperature up to the desired second range of temperature for said curing said article; maintaining the temperature of said article at a substantially constant level within said second range of temperature during the said curing of said article; providing a constant inert gas flow to fill said chamber under the vacuum conditions during operation; and cooling said chamber and said article. 2. The method of claim 1 wherein said first range of temperature in between about 250� to 350� C. and said second range of temperature is between about 350� to 500� C. and the maintenance of said temperature at said constant value is within about plus/minus 3� C.
3. The method of claim 1 wherein the said article is at least one semiconductor wafer having a spin-on-glass layer thereon and said moving the said article into said chamber includes using a cassette to carry said at least one wafer.
4. The method of claim 1 wherein said ramping the temperature at a controlled rate is at a rate of between about 1� to 10� C. per minute.
5. The method of claim 1 wherein the said providing a constant inert gas flow includes a flow rate of about 10 sccm per minute and the gas in nitrogen.
6. The method of claim 1 wherein the said cooling of said chamber and article include passing Helium gas through the chamber while using cooling water is passing through the heat exchanger.
7. A method for vacuum degassing and curing a spin-on-glass layer on a integrated circuit wafer comprising:providing a chamber; moving at least one said wafer to be subjected to vacuum degassing and curing into said chamber; providing a vacuum of less than about 100 mtorr. in said chamber; maintaining the temperature of said wafer at a substantially constant level within a first range of temperature between about 250� to 350� C. during the said vacuum degassing; ramping the temperature at a controlled rate from the said first range of temperature up to the desired second range of temperature for said curing; maintaining the temperature of said wafer at a substantially constant level within said second range of temperature between about 350� to 500� C. during the said curing; providing a constant inert gas flow to fill said chamber under the vacuum conditions during operation; and cooling said chamber and said wafer to room temperature. 8. The method of claim 7 wherein the said providing a constant inert gas flow includes a flow rate of about 10 sccm per minute and the gas in nitrogen.
(1) U.S. patent application Ser. No. 07/521,401 filed Apr.19, 1990, now U.S. Pat. No. 5,003,062 by the same inventor Daniel L. W. Yen. U.S.
(2) U.S. patent application Ser. No. 07/615377 filed by the same inventor Daniel L. W. Yen.
These problems have been recognized in the prior art and attempts have been made to overcome these topographical problems principally in the one micron and above feature dimensions. These techniques can be generally grouped in categories of planarization either involving etchback or nonetchback techniques. Examples of such processes are shown in the S. Morimoto U.S. Pat. No. 4,721,548; W. I. Lehrer U.S. Pat. No. 4,619,839; J. K. Chu et al U.S. Pat. No. 4,775,550; V. W. Ryan et al U.S. Pat. No. 4,826,709 and C. T. Ting et al U.S. Pat. No. 4,885,262.
The coupling patent applications Ser. No. 07/512,401 entilted "Semiconductor Planarization Process for Submicron Devices" and Ser. No. 07/615377 entitled "Planarization Process for IC Submicron Devices" by Daniel L. W. Yen the same author of the present invention describe methods to overcome the problems involving outgassing in the nonetchback type of planarization process for both silicate and siloxane type of spin-on-glass types of materials. These new inventions have made it necessary to design and develop a new machine and method for high vacuum, controlled ramping curing furnace which allows successful vacuum degassing and curing of a spin-on-glass layer within the same machine.
Further in accordance with the invention, a method for vacuum degassing and curing a spin-on-glass layer on a integrated circuit wafer is shown. A chamber is provided. At least one wafer is moved into ths chamber to be subjected to vacuum degassing and curing. A vacuum of less than about 100 mtorr. is provided in the chamber. The temperature of said wafer is maintained at a substantially constant level within a first range of temperature between about 250� to 350� C. during the vacuum degassing. The temperature is ramped at a controlled rate from the first range of the temperature up to the desired second range of temperature for the desired curing. The temperature of wafer is maintained at a substantially constant level within the second range of temperature between about 350� to 500� C. during the curing step. A constant inert gas flow is provided to fill the chamber under the vacuum conditions during operations. The chamber and the wafer are then cooled to room temperature.
The spin-on-glass materials and how they are processed are critical to the success of the process for planarization of integrated circuits as described in the above cited pending Patent Applications of Daniel L. W. Yen. The most useful materials are silicates-Si (OH)4 and siloxanes-(RO)nSi(OH)4-n. These types of materials are generally known and available. Examples of the silicate type is OCD Type 2 made by Tokyo Okha Corp. and siloxane type is OCD Type 6 made by Tokyo Okha Corp. Each spin-on-glass coating is less than about 0.3 micrometers and preferably between about 0.08 and 0.2 micrometers. The more coatings that are used, the better the planarity. The material to be applied is thoroughly mixed in a suitable solvent which is usally a combination of a high boiling point solvent and a low boiling point solvent.
The final step in the making of the spin-on-glass layer is curing. Curing is a high temperture heating step to cause the breakdown of the silicate or siloxane material to a silicon dioxide like cross linked material. Water in the form of steam is the major reaction product of this reaction. The silicate spin-on-glass is cured at about 390 degrees C. and siloxane spin-on-glass is cured at about 450 degrees C. in nitrogen.
Referring now more particularly to FIG. 1, there is shown the operation of the vacuum degassing and curing steps of the apparatus of the invention. FIG. 2 schematically shows the apparatus 24 itself. Articles, such as semiconductor wafers having a planarizing spin-on-glass layer thereon are carried to the apparatus in a cassette 20. One or many of these wafers may be carried in this cassette 20. Conventional mechanizisms unload these wafers within the apparatus and load them into the furnace quartz boat 28 as is seen loaded with wafers and located in the chamber 26 of the apparatus 24 in the FIG. 2. A vacuum pump 30, associated piping and other equipment are connected to the chamber 26 to provide a vacuum of less than about 100 mtorr. in the chamber. Means 32 are provided for heating the chamber. Other control means (not shown) are provide for maintaining the temperature of the wafer in the chamber at a substantially constant level within a first range of temperature during the vacuum degassing. This control means also allows ramping the temperature at a controlled rate from the first range of temperature up to the desired second range of temperature for the curing step. This control means then maintains the temperature of the wafer and chamber at a substantially constant level within the second range of temperature during this curing step. Means, including valves, piping and controls 34 provide a constant inert gas flow to fill the chamber 26 under the vacuum conditions during operation. Cooling means are provided to cool the chamber and wafers to room temperature. The cooling can be done by either use of cooling water through the heat exchange structure or by using a gas such as Helium passing through the gas heat exchanger.
The operation of the apparatus 24 may be better seen with reference to the FIG. 1 which shows the graphical representation in time versus temperature to which the apparatus operates. Also the FIG. 3 shows the graphical representation in time versus vacuum to which the apparatus operates. After the wafer(s) each with a spin-on-glass layer thereon and which have been baked are described above to remove the vehicle, are positioned in the chamber the process may begin.
The next part 12 of the operation curve involves ramping the temperature at a controlled rate from the first range of temperature up to the desired second range of temperature for curing. Control means are provided to raise the temperature at a steady ramping rate of about 1� C./minute or more. It is important that the ramping temperature is raised at the constant rate because the silicate glass tends to crack once the stress of it builds up at an unacceptable rate. During the rise in temperature, as indicated in the operation curve nitrogen. Na or Argon is started to flow into the chamber. It is flowed into the chamber starting at this time because a convection type of heat transfer is preferred for the curing of silicate SOG. It continues to flow into the chamber through the cooling cycle. The nitrogen or other inert gas such as argon is flowed into the chamber at a flow rate of at least 10 sccm per minute. The ramping part 12 of the operating curve can take one of many curves. For example, curves A, B, and C are alternative ramping curves. The particular curve to be used depends upon the type, whether siloxane or silicate of spin-on-glass used and the thickness of the spin-on-glass layer or layers. For example, the A curve increases at about 5� C. per minute and would be the curve used for siloxane type of spin-on-glass. For silicate spin-on-glass types, the curves B and C are used depending upon the silicate type and its thickness.
The next part 14 of the operating curve is the curing of the spin-on-glass layer on each wafer time period. The temperature of the wafer is maintained at a substantially constant level within the second range of temperature. The preferred temperature is between about 350� to 500� C. During this curing part 14 of the operating curve is when crosslinking of the silicate or siloxane type molecules and these molecules are stabilized. It is important that the vacuum continues during this part 14 of the operating curve, because it provides the efficient way of degassing to avoid the poison via problem in the subsequent process steps. Even higher curing temperature are useful if the metal layers in the integrated circuit is uneffected by the temperature. However, the useful metal used is aluminium integrated circuits and the temperature must be limited to below about 500� C.
In order to more fully understand FIG. 1, the times for the parts of the curve 10, 12, 14 and 16 must be generally understood. The minimum time needed for part 10 of the curve for degassing is at least 15 minutes. It is preferred that the time be even longer. The time, of course depends upon the of spin-on-glass used and the thickness of the layer or layers. The part 12 of the curve for ramping has its ramping rate chosen depending upon the type and thickness of the spin-on-glass and its thickness. The time needed for part 12 is decided by the temperature difference between the curve parts 10 and 14. The curving part 14 of the curve should be at least 15 minutes and preferably longer. The final part 16 of the curve for cooling is not critical and can take whatever time needed depending upon equipment needs.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4619839 *Dec 12, 1984Oct 28, 1986Fairchild Camera & Instrument Corp.Method of forming a dielectric layer on a semiconductor deviceUS4721548 *May 13, 1987Jan 26, 1988Intel CorporationSemiconductor planarization processUS4775550 *Jun 3, 1986Oct 4, 1988Intel CorporationSurface planarization method for VLSI technologyUS4826709 *Feb 29, 1988May 2, 1989American Telephone And Telegraph Company At&T Bell LaboratoriesDevices involving silicon glassesUS4885262 *Mar 8, 1989Dec 5, 1989Intel CorporationChemical modification of spin-on glass for improved performance in IC fabricationUS5003062 *Apr 19, 1990Mar 26, 1991Taiwan Semiconductor Manufacturing Co.Semiconductor planarization process for submicron devices* Cited by examinerNon-Patent CitationsReference1Forester et al., "SOG Planarization for Polysilicon and First Metal Interconnect in a One Micron CMOS Process", V-MIC Confer., Jun./88, pp. 72-79.2 *Forester et al., SOG Planarization for Polysilicon and First Metal Interconnect in a One Micron CMOS Process , V MIC Confer., Jun./88, pp. 72 79.3Grupta et al., "Interlevel Dielectric Planarization with Spin-On-Glass Films", V-MIC Conference; Jun. 1986, pp. 506-515.4 *Grupta et al., Interlevel Dielectric Planarization with Spin On Glass Films , V MIC Conference; Jun. 1986, pp. 506 515.5Yen et al., "Defect Integration with Spin-On-Glass Sandwich as an Intermetal Dielectric Layer for 1.2 Micrometer CMOS DLM Process", V-MIC Conference, Jun. 13-14, 1988, pp. 85-94.6 *Yen et al., Defect Integration with Spin On Glass Sandwich as an Intermetal Dielectric Layer for 1.2 Micrometer CMOS DLM Process , V MIC Conference, Jun. 13 14, 1988, pp. 85 94.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5250472 *Sep 3, 1992Oct 5, 1993Industrial Technology Research InstituteSpin-on-glass integration planarization having siloxane partial etchback and silicate processesUS5320982 *Jul 2, 1991Jun 14, 1994Hitachi, Ltd.Wafer cooling method and apparatusUS5328871 *Feb 11, 1992Jul 12, 1994Sharp Kabushiki KaishaManufacturing process for semiconductor deviceUS5371046 *Jul 22, 1993Dec 6, 1994Taiwan Semiconductor Manufacturing CompanyMethod to solve sog non-uniformity in the VLSI processUS5413940 *Oct 11, 1994May 9, 1995Taiwan Semiconductor Manufacturing CompanyProcess of treating SOG layer using end-point detector for outgassingUS5454871 *Dec 1, 1994Oct 3, 1995Taiwan Semiconductor Manufacturing Company, Ltd.SOG coated apparatus to solve SOG non-uniformity in the VLSI processUS5496776 *Apr 27, 1995Mar 5, 1996United Microelectronics CorporationSpin-on-glass planarization process with ion implantationUS5512513 *Aug 25, 1994Apr 30, 1996Nippon Telegraph And Telephone CorporationMethod of fabricating semiconductor device with water protective filmUS5673750 *Jun 2, 1995Oct 7, 1997Hitachi, Ltd.Vacuum processing method and apparatusUS5763329 *Feb 26, 1997Jun 9, 1998Nec CorporationMethod for making semiconductor device by coating an SOG film in amine gas atmosphereUS5858871 *Jun 13, 1996Jan 12, 1999Texas Instruments IncorporatedPorous insulator for line-to-line capacitance reductionUS6071807 *Dec 23, 1997Jun 6, 2000Sanyo Electric Company, Ltd.Fabrication method of semiconductor device including insulation film with decomposed organic contentUS6214749 *Oct 21, 1997Apr 10, 2001Sanyo Electric Co., Ltd.Process for producing semiconductor devicesUS6235648Sep 25, 1998May 22, 2001Sanyo Electric Co., Ltd.Semiconductor device including insulation film and fabrication method thereofUS6268657Jun 18, 1997Jul 31, 2001Sanyo Electric Co., Ltd.Semiconductor devices and an insulating layer with an impurityUS6288438Sep 4, 1997Sep 11, 2001Sanyo Electric Co., Ltd.Semiconductor device including insulation film and fabrication method thereofUS6465369 *Jan 21, 2000Oct 15, 2002Mosel Vitelic Inc.Method for stabilizing semiconductor degas temperatureUS6690084Nov 21, 2000Feb 10, 2004Sanyo Electric Co., Ltd.Semiconductor device including insulation film and fabrication method thereofUS6794283May 27, 1999Sep 21, 2004Sanyo Electric Co., Ltd.Semiconductor device and fabrication method thereofUS6825132Jan 11, 1999Nov 30, 2004Sanyo Electric Co., Ltd.Manufacturing method of semiconductor device including an insulation film on a conductive layerUS6831015Aug 29, 1997Dec 14, 2004Sanyo Electric Co., Ltd.Fabrication method of semiconductor device and abrasive liquid used thereinUS7439111 *Sep 9, 2005Oct 21, 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and manufacturing method thereofEP0971400A2 *Jul 1, 1999Jan 12, 2000Dow Corning CorporationMethod for producing low dielectric coatings from hydrogen silsesquioxane resin* Cited by examinerClassifications U.S. Classification438/800, 438/760, 438/781, 257/E21.242, 257/E21.241, 438/782International ClassificationH01L21/3105, H01L21/00Cooperative ClassificationH01L21/67115, H01L21/31058, H01L21/3105European ClassificationH01L21/67S2H6, H01L21/3105, H01L21/3105PLegal EventsDateCodeEventDescriptionSep 12, 2003FPAYFee paymentYear of fee payment: 12Jun 24, 1999FPAYFee paymentYear of fee payment: 8Sep 25, 1995FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services