Source: http://www.google.com/patents/US7577892?dq=7,328,163
Timestamp: 2015-06-30 17:36:13
Document Index: 95760362

Matched Legal Cases: ['Application No. 60', 'art 3', 'art 3', 'art 1', 'art 11', 'art 11', 'art 11', 'art 11', 'art 16']

Patent US7577892 - High speed iterative decoder - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA high-speed decoder includes a buffer that includes buffer space for Q encoded data frames, where Q is a rational number greater than or equal to two. An iterative decoder receives the data frames from the buffer, generates a confidence result with each decoding iteration, and completes decoding a data...http://www.google.com/patents/US7577892?utm_source=gb-gplus-sharePatent US7577892 - High speed iterative decoderAdvanced Patent SearchPublication numberUS7577892 B1Publication typeGrantApplication numberUS 11/372,821Publication dateAug 18, 2009Filing dateMar 10, 2006Priority dateAug 25, 2005Fee statusPaidAlso published asUS7853855Publication number11372821, 372821, US 7577892 B1, US 7577892B1, US-B1-7577892, US7577892 B1, US7577892B1InventorsRunsheng HeOriginal AssigneeMarvell International LtdExport CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (99), Referenced by (3), Classifications (9), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetHigh speed iterative decoder
US 7577892 B1Abstract
1. A high-speed decoder, comprising:
a first buffer that includes buffer space for Q encoded data frames, where Q is a rational number greater than or equal to two; and
an iterative decoder that receives the data frames from the first buffer, that generates a confidence result with each decoding iteration, and that completes decoding a data frame when at least one of the number of iterations reaches a predetermined maximum number of iterations and the confidence result is greater than or equal to a predetermined confidence level,
wherein the iterative decoder stops decoding the Q data frames after a predetermined total number of iterations that is less than Q times the predetermined maximum number of iterations.
2. The high-speed decoder of claim 1 wherein the predetermined total number of iterations corresponds with a maximum acceptable error rate in decoding the Q data frames.
3. The high-speed decoder of claim 1 further comprising a clock that drives the iterative decoder and operates at a clock frequency based on an average number of iterations needed for the confidence result to achieve the predetermined confidence level.
4. The high-speed decoder of claim 1 further comprising a second buffer that receives decoded data frames from the iterative decoder.
5. The high-speed decoder of claim 4 wherein the second buffer includes a buffer space having the same size as the buffer space of the first buffer.
6. A transceiver comprising the high-speed decoder of claim 1 and a forward error correction encoder that employs a concatenated code.
7. The high-speed decoder of claim 1 further comprising a physical layer module that communicates with an input of the first buffer and that is otherwise compatible with at least one of the Bluetooth standard, Institute of Electrical and Electronics Engineers (IEEE) standard 802.3, 802.3an, 802.11, 802.11a, 802.11b, 802.11g, 802.11h, 802.11n, 802.16, and 802.20.
8. A high-speed decoding method, comprising:
buffering Q data frames, where Q is a rational number greater than or equal to two; and
receiving the data frames from the buffering step;
iteratively decoding the data frames;
generating a confidence result with each decoding iteration; and
completing decoding a data frame when at least one of the number of iterations reaches a predetermined maximum number of iterations and the confidence result is greater than or equal to a predetermined confidence level,
wherein the iterative decoding step stops decoding the Q data frames after a predetermined total number of iterations that is less than Q times the predetermined maximum number of iterations.
9. The high-speed decoding method of claim 8 wherein the predetermined total number of iterations corresponds with a maximum acceptable error rate in decoding the Q data frames.
10. The high-speed decoding method of claim 8 further comprising clocking the iterative decoding step at a clock frequency based on an average number of iterations needed for the confidence result to achieve the predetermined confidence level.
11. The high-speed decoding method of claim 8 further comprising:
receiving the decoded data frames from the iterative decoding step; and
buffering the decoded data frames.
12. The high-speed decoding method of claim 11 wherein step of buffering the decoded data frames includes maintaining a buffer space having a same size as a buffer space used in the step of buffering Q data frames.
13. The high-speed decoding method of claim 8 further comprising;
receiving the Q data frames according to at least one of the Bluetooth standard, Institute of Electrical and Electronics Engineers (IEEE) standard 802.3, 802.3an, 802.11, 802.11a, 802.11b, 802.11g, 802.11h, 802.11n, 802.16, and 802.20; and
communicating the received Q data frames to the buffering step.
14. A high-speed decoder, comprising:
first buffer means for buffering Q encoded data frames, where Q is a rational number greater than or equal to two; and
iterative decoder means for receiving the data frames from the first buffer means, generating a confidence result with each decoding iteration, and completing decoding a data frame when at least one of the number of iterations reaches a predetermined maximum number of iterations and the confidence result is greater than or equal to a predetermined confidence level,
wherein the iterative decoder means stops decoding the Q data frames after a predetermined total number of iterations that is less than Q times the predetermined maximum number of iterations.
15. The high-speed decoder of claim 14 wherein the predetermined total number of iterations corresponds with a maximum acceptable error rate in decoding the Q data frames.
16. The high-speed decoder of claim 14 further comprising clock means for driving the iterative decoder means and at a clock frequency based on an average number of iterations needed for the confidence result to achieve the predetermined confidence level.
17. The high-speed decoder of claim 14 further comprising second buffer means for receiving decoded data frames from the iterative decoding means.
18. The high-speed decoder of claim 17 wherein the second buffer means includes a buffer space having the same size as the buffer space of the first buffer means.
19. The high-speed decoder of claim 14 further comprising physical layer means for communicating with an input of the first buffer means and that is otherwise compatible with at least one of the Bluetooth standard, Institute of Electrical and Electronics Engineers (IEEE) standard 802.3, 802.3an, 802.11, 802.11a, 802.11b, 802.11g, 802.11h, 802.11n, 802.16, and 802.20.
This application claims the benefit of U.S. Provisional Application No. 60/711,164, filed on Aug. 25, 2005. The disclosure of the above application is incorporated herein by reference in its entirety.
Encoders 18 may employ a FEC such as low-density parity check (LDPC) and/or concatenated codes such as turbo serial-concatenated convolutional codes. Encoders 18 include first, or outer, encoders 26 that encode the data from hosts 22 according to a first codeword. Interleavers 28 interleave encoded data from outer encoders 26 before communicating it to second, or inner, encoders 30. Inner encoders 30 encode the interleaved data according to a second codeword. Inner encoders 30 then communicate the encoded data to PHYs 16 to be transmitted.
Decoders 20 include first sub-systems 32 that receive the transmitted data from PHYs 16. First sub-systems 32 communicate decoded data to deinterleavers 34. First sub-systems 32 can also generate one or more signals 36 that indicate how certain first sub-systems 32 are of the accuracy of the data that was sent to deinterleavers 34. Second sub-systems 38 receive the deinterleaved data from deinterleavers 34 and decode it. Second subsystems 38 can provide feedback, or soft result, 40 to outer decoders 32 to improve decoding accuracy.
Encoders 108 employ concatenated codes. Decoder channels 110 include input first-in, first-out buffers (FIFOs) 120 and output FIFOs 121 that communicate with respective inputs and outputs of central processing units (CPU) 122. In some embodiments FIFOs 120, 121 include sufficient memory space to buffer 0 data frames received through the communication channel 104. Q is a real number greater than 2. If N represents a number of bits in each data frame then the buffer memory size is Q*N bits.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3297951Dec 20, 1963Jan 10, 1967IbmTransversal filter having a tapped and an untapped delay line of equal delay, concatenated to effectively provide sub-divided delays along both linesUS3500215Nov 15, 1966Mar 10, 1970Philips CorpFilter for bivalent pulse signalsUS3521170Feb 28, 1967Jul 21, 1970Philips CorpTransversal digital filters having analog to digital converter for analog signalsUS3543009Sep 5, 1967Nov 24, 1970Research CorpBinary transversal filter systemsUS3793589Jun 28, 1972Feb 19, 1974Gen ElectricData communication transmitter utilizing vector waveform generationUS3973089Jun 25, 1975Aug 3, 1976General Electric CompanyAdaptive hybrid circuitUS4071842Jan 3, 1977Jan 31, 1978Bell Telephone Laboratories, IncorporatedApparatus for analog to digital conversionUS4112253Jun 24, 1977Sep 5, 1978Siemens AktiengesellschaftDevice for the transmission of push-pull signals across a two-wire line in full duplex operationUS4131767Feb 22, 1978Dec 26, 1978Bell Telephone Laboratories, IncorporatedEcho cancellation in two-wire, two-way data transmission systemsUS4152541Feb 3, 1978May 1, 1979Burroughs CorporationFull duplex driver/receiverUS4295218Jun 25, 1979Oct 13, 1981Regents Of The University Of CaliforniaError-correcting coding systemUS4309673Mar 10, 1980Jan 5, 1982Control Data CorporationDelay lock loop modulator and demodulatorUS4362909Apr 21, 1980Dec 7, 1982U.S. Philips CorporationEcho canceler with high-pass filterUS4393370Apr 29, 1981Jul 12, 1983Nippon Electric Co., Ltd.Digital to analog converter using matrix of current sourcesUS4393494Oct 2, 1980Jul 12, 1983Cselt Centro Studi E Laboratori Telecomunicazioni S.P.A.Transceiver for full-duplex transmission of digital signals over a common lineUS4408190May 28, 1981Oct 4, 1983Tokyo Shibaura Denki Kabushiki KaishaResistorless digital-to-analog converter using cascaded current mirror circuitsUS4464545Jul 13, 1981Aug 7, 1984Bell Telephone Laboratories, IncorporatedEcho cancellerUS4503421May 26, 1982Mar 5, 1985Nippon Electric Co., Ltd.Digital to analog converterUS4527126Aug 26, 1983Jul 2, 1985Micro Component Technology, Inc.AC parametric circuit having adjustable delay lock loopUS4535206Jun 8, 1982Aug 13, 1985At&T Bell LaboratoriesEcho cancellation in two-wire full-duplex data transmission with estimation of far-end data componentsUS4591832Jul 18, 1984May 27, 1986Rca CorporationDigital-to-analog conversion system as for use in a digital TV receiverUS4601044Nov 4, 1983Jul 15, 1986Racal Data Communications Inc.Carrier-phase adjustment using absolute phase detectorUS4605826Jun 21, 1983Aug 12, 1986Nec CorporationEcho canceler with cascaded filter structureUS4621172Dec 19, 1983Nov 4, 1986Nec CorporationFast convergence method and system for echo cancellerUS4621356Jul 18, 1983Nov 4, 1986Scipione Fred JCommunications interface for duplex transmission and reception of data and other signals over telephone linesUS4626803Dec 30, 1985Dec 2, 1986General Electric CompanyApparatus for providing a carrier signal with two digital data streams I-Q modulated thereonUS4715064Jun 22, 1984Dec 22, 1987Ncr CorporationAdaptive hybrid circuitUS4727566Dec 19, 1984Feb 23, 1988Telefonaktiebolaget Lm EricssonMethod to test the function of an adaptive echo cancellerUS4816830Sep 14, 1987Mar 28, 1989Cooper James CWaveform shaping apparatus and methodUS4817081Mar 20, 1987Mar 28, 1989At&T And Philips Telecommunications B.V.Adaptive filter for producing an echo cancellation signal in a transceiver system for duplex digital communication through one single pair of conductorsUS4868571Oct 21, 1987Sep 19, 1989Nec CorporationDigital to analog converterUS4878244Sep 19, 1985Oct 31, 1989Northern Telecom LimitedElectronic hybrid circuitUS4888762Feb 17, 1988Dec 19, 1989Nec CorporationEcho canceller for bidirectional transmission on two-wire subscriber linesUS4894820Mar 21, 1988Jan 16, 1990Oki Electric Industry Co., Ltd.Double-talk detection in an echo cancellerUS4935919Sep 14, 1987Jun 19, 1990Nec CorporationFull duplex modem having two echo cancellers for a near end echo and a far end echoUS4947171Mar 10, 1989Aug 7, 1990Deutsche Itt Industries GmbhCircuit arrangement for averaging signals during pulse-density D/A or A/D conversionUS4970715Apr 3, 1989Nov 13, 1990Universal Data Systems, Inc.Modem with improved remote echo location and cancellationUS4972360Aug 21, 1989Nov 20, 1990International Business Machines Corp.Digital filter for a modem sigma-delta analog-to-digital converterUS4988960Dec 8, 1989Jan 29, 1991Yamaha CorporationFM demodulation device and FM modulation device employing a CMOS signal delay deviceUS4993045Oct 31, 1988Feb 12, 1991Racal Data Communications Inc.Modem diagnostic loopUS4999830Sep 25, 1989Mar 12, 1991At&T Bell LaboratoriesCommunication system analog-to-digital converter using echo information to improve resolutionUS5018134Dec 4, 1989May 21, 1991Hitachi, Ltd.Method for cancelling echo in a transmitter and an apparatus thereforUS5084865Feb 23, 1990Jan 28, 1992Nec CorporationEcho canceller having fir and iir filters for cancelling long tail echoesUS5119365Dec 14, 1990Jun 2, 1992Ag Communication Systems CorporationBi-directional buffer line amplifierUS5136260Mar 8, 1991Aug 4, 1992Western Digital CorporationPLL clock synthesizer using current controlled ring oscillatorUS5148427Apr 10, 1990Sep 15, 1992Level One Communications, Inc.Non-linear echo cancellerUS5153450Jul 16, 1991Oct 6, 1992Samsung Semiconductor, Inc.Programmable output drive circuitUS5164725Feb 5, 1992Nov 17, 1992Tritech Microelectronics International Pte Ltd.Digital to analog converter with current sources paired for canceling error sourcesUS5185538Jun 5, 1991Feb 9, 1993Mitsubishi Denki Kabushiki KaishaOutput circuit for semiconductor integrated circuits having controllable load drive capability and operating method thereofUS5202528Apr 10, 1991Apr 13, 1993Casio Computer Co., Ltd.Electronic musical instrument with a note detector capable of detecting a plurality of notes sounded simultaneouslyUS5204880Apr 23, 1991Apr 20, 1993Level One Communications, Inc.Differential line driver employing predistortionUS5212659Oct 8, 1991May 18, 1993Crystal SemiconductorLow precision finite impulse response filter for digital interpolationUS5222084Jun 25, 1991Jun 22, 1993Nec CorporationEcho canceler having adaptive digital filter unit associated with delta-sigma modulation circuitUS5243346Dec 19, 1991Sep 7, 1993Nec CorporationDigital-to-analog converting device using decoders and parallel-to-serial convertersUS5243347Sep 28, 1992Sep 7, 1993Motorola, Inc.Monotonic current/resistor digital-to-analog converter and method of operationUS5245231Dec 30, 1991Sep 14, 1993Dell Usa, L.P.Integrated delay lineUS5245654Oct 10, 1991Sep 14, 1993Cermetek Microelectronics, Inc.Solid state isolation device using opto-isolatorsUS5248956Apr 5, 1991Sep 28, 1993Center For Innovative TechnologyElectronically controllable resistorUS5253249Jun 29, 1989Oct 12, 1993Digital Equipment CorporationBidirectional transceiver for high speed data systemUS5253272Mar 1, 1991Oct 12, 1993Amp IncorporatedDigital data transmission system with adaptive predistortion of transmitted pulsesUS5254994Mar 4, 1992Oct 19, 1993Kabushiki Kaisha ToshibaCurrent source cell use in current segment type D and A converterUS5267269Sep 4, 1991Nov 30, 1993Level One Communications, Inc.System and method employing predetermined waveforms for transmit equalizationUS5269313Sep 9, 1991Dec 14, 1993Sherwood Medical CompanyFilter and method for filtering baseline wanderUS5272453Aug 3, 1992Dec 21, 1993Motorola Inc.Method and apparatus for switching between gain curves of a voltage controlled oscillatorUS5280526May 26, 1992Jan 18, 1994At&T Bell LaboratoriesTransformer-less hybrid circuitUS5282157Sep 13, 1990Jan 25, 1994Telecom Analysis Systems, Inc.Input impedance derived from a transfer networkUS5283582Dec 20, 1991Feb 1, 1994Texas Instruments IncorporatedCircuitry and method for current input analog to digital conversionUS5305379May 19, 1992Apr 19, 1994Hitachi, Ltd.Semiconductor integrated deviceUS5307064Sep 9, 1992Apr 26, 1994Tekuno Esu Kabushiki KaishaDigital-to-analog converter capable of reducing load of low-pass filterUS5307405Sep 25, 1992Apr 26, 1994Qualcomm IncorporatedNetwork echo cancellerUS5323157Jan 15, 1993Jun 21, 1994Motorola, Inc.Sigma-delta digital-to-analog converter with reduced noiseUS5325400Jun 4, 1992Jun 28, 1994The Lan Guys, Inc.Method and apparatus for predistortion of signals in digital transmission systemsUS5357145Dec 22, 1992Oct 18, 1994National Semiconductor CorporationIntegrated waveshaping circuit using weighted current summingUS5365935Jul 12, 1993Nov 22, 1994Ralin, Inc.Portable, multi-channel ECG data monitor/recorderUS5367540Jan 19, 1993Nov 22, 1994Fujitsu LimitedTransversal filter for use in a digital subscriber line transmission interfaceUS5373147Sep 15, 1993Dec 13, 1994International Business Machines CorporationApparatus and method for detecting line segment directionUS5375147Aug 20, 1992Dec 20, 1994Fujitsu LimitedJitter compensating deviceUS5388092Nov 9, 1993Feb 7, 1995Nec CorporationEcho canceller for two-wire full duplex digital data transmissionUS5388123Apr 21, 1992Feb 7, 1995Matsushita Electric Industrial Co., Ltd.Data receiving systemUS5392042Aug 5, 1993Feb 21, 1995Martin Marietta CorporationSigma-delta analog-to-digital converter with filtration having controlled pole-zero locations, and apparatus thereforUS5399996Aug 16, 1993Mar 21, 1995At&T Global Information Solutions CompanyCircuit and method for minimizing electromagnetic emissionsUS5440514Mar 8, 1994Aug 8, 1995Motorola Inc.Write control for a memory using a delay locked loopUS5440515Mar 8, 1994Aug 8, 1995Motorola Inc.Delay locked loop for detecting the phase difference of two signals having different frequenciesUS5444739Aug 31, 1992Aug 22, 1995Matsushita Electric Industrial Co., Ltd.Equalizer for data receiver apparatusUS5465272Apr 8, 1994Nov 7, 1995Synoptics Communications, Inc.Data transmitter baseline wander correction circuitUS5479124Aug 20, 1993Dec 26, 1995Nexgen MicrosystemsSlew rate controller for high speed busUS5507036Sep 30, 1994Apr 9, 1996Rockwell InternationalApparatus with distortion cancelling feed forward signalUS5517435Mar 11, 1994May 14, 1996Nec CorporationMethod of identifying an unknown system with a band-splitting adaptive filter and a device thereofUS5521540May 26, 1995May 28, 1996Bull, S.A.Method and apparatus for multi-range delay controlUS5537113Jun 15, 1993Jul 16, 1996Advantest Corp.A/D or D/A conversion using distribution of differential waveforms to interleaved convertersUS5537444Jan 14, 1993Jul 16, 1996At&T Corp.Extended list output and soft symbol output viterbi algorithmsUS5539403May 28, 1993Jul 23, 1996Matsushita Electric Industrial Co, LtdD/A conversion apparatus and A/D conversion apparatusUS5539773Feb 9, 1993Jul 23, 1996Thomson Consumer Electronics S.A.Method and apparatus for ghost cancelling and/or equalizingUS5557027Jan 13, 1995Sep 17, 1996Shell Oil CompanyOligomerization catalyst and processUS5559476May 31, 1995Sep 24, 1996Cirrus Logic, Inc.Voltage controlled oscillator including voltage controlled delay circuit with power supply noise isolationUS5568064May 8, 1995Oct 22, 1996International Business Machines CorporationBidirectional transmission line driver/receiverUS5568142Oct 20, 1994Oct 22, 1996Massachusetts Institute Of TechnologyHybrid filter bank analog/digital converterUS5572159Nov 14, 1994Nov 5, 1996Nexgen, Inc.Voltage-controlled delay element with programmable delayUS20020184595 *Mar 15, 2002Dec 5, 2002Yoshikuni MiyataError correction encoding method and apparatus, and error correction decoding method and apparatusUSRE30111Jul 28, 1978Oct 9, 1979Motorola, Inc.Digital single signal line full duplex method and apparatus* Cited by examinerNon-Patent CitationsReference119.6 A DSP Based Receiver for 1000Base-T PHY; Runsheng He et al; Marvell Semiconductor, Inc.; 2001 IEEE International Solid-State Circuits Conference; 3 pages.219.7 A CMOS Transceiver Analog Front-End for Gigabit Ethernet over CAT-5 Cables;Pierte Roo et al; Marvell Semiconductor, Inc.; 2001 IEEE International Solid-State Circuits Conference; 4 pages.3802.11n; IEEE P802.11-04/0889r6; Wireless LANs, TGn Sync Proposal Technical Specification; 131 pages.4802.3ab; IEEE Std 802.3-2002 (Revisiion of IEEE 802.3, 2000 Edition); IEEE Standard for Information technology-Telecommunications and information exchange between systems-local and metropolitan area networks-Specific requirements Part 3: Carrier sense multiple access with collison detection (CSMA/CD) access method and physical layer specifications; IEEE Computer Society; Sponsored by the LAN/MAN Standards Committee; Mar. 8, 2002; 104 pages.5802.3an; Information technology-Telecommunications and information exchange between systems-Local and Metropolitan area networks-specific requirements Part 3: Carrier Sense Multiple Access with Collison Detection (CSMA/CD) Access Method and Physical Layer Specifications-Amendment: Physical Layer and Management Parameters for 10 Gb/s Operation-Type 10GBASE-T; Sponsored by the LAN/MAN Standards Committee of the IEEE Computer Society; 2004; 145 pages.6A 1.2 GHz Programmable DLL-Based Frequency Multipler for Wireless Applications; Chua-Chin Wang et al; IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, No. 12, Dec. 2004; pp. 1377-1381.7A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM; Thomas H. Lee et al; IEEE Journal of Solid-State Circuits; vol. 29, No. 12, Dec. 1994; pp. 1491-1496.8A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-mum CMOS; Beomsup Kim et al; IEEE Journal of Solid-State Circuits; vol. 25, No. 6, Dec. 1990; pp. 1385-1394.9A 690-mW 1-Gb/s 1024-b, Rate-� Low-Density Parity-Check Code Decoder; Andrew J. Blanksby and Chris J. Howland; IEEE JOurnal of Solid-State Circuits, vol. 37, No. 3, Mar. 2002; pp. 404-412.10A CMOS MIxed-Signal 100Mb/s Receive Architecture for Fast Ethernet; Ayal Shoval et al; IEEE 1998 Custom Integrated Circuits Conference; pp. 253-256.11A CMOS Oversampling D/A Converter with a Current-Mode Semidigital Reconstruction Filter; David K. Su; IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993; pp. 1224-1233.12A CMOS Serial Link for Fully Duplexed Data Communication; Kyeongho Lee et al; IEEE Journal of Solid-State Circuits, vol. 30, No. 4, Apr. 1995; pp. 353-364.13A CMOS Transceiver for 10-Mb/s and 100-Mb/s Ethernet; James Everitt et al; IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998; pp. 2169-2177.14A Constant Slew Rate Ethernet Line Driver; David S. Nack and Kenneth C. Dyer; IEEE Journal of Solid-State Circuits, vol. 36, No. 5, May 2001; pp. 854-858.15A Dynamic Line-Termination Circuit for Multireceiver Nets; Michael Dolle; IEEE Journal on Solid-State Circuits, vol. 28, No. 12, Dec. 1993; pp. 1370-1373.16A Monlithic 480 Mb/s Parallel AGC/Decision/Clock-Recovery Circuit in 1.2-mum CMOS; Timothy H. Hu et al; IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993; pp. 1314-1320.17A Monolithic 2.3-Gb/s 100-mW Clock and Data Recovery Circuit in Silicon Bipolar Technology; Mehmet Soyner; IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993; pp. 1310-1313.18A New Approach for the Fabrication of Micromechanical Structures; M. Parameswaran et al; Sensors and Actuators, 19 (1989) pp. 289-307.19A Third Method of Generation and Detection of Single-Sideband Signals; Donald K. Weaver, Jr.; Cover page and pp. 1703-1705; Proceedings of the IRE, vol. 44, No. 12, Dec. 1956.20A Two-Chip 1.5-GBd Serial Link Interface; Richard C. Walker et al; IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992; pp. 1805-1811.21A Viterbi Algorithm with Soft-Decision Outputs and its Applications; Joachim Hagenauer and Peter Hoeher; German Aerospace Research Establishment (DLR); 1969 IEEE; pp. 1680-1686.22Active Output Impedance for ADSL Line Drivers; Randy Stephens; Texas Instruments; Application Report, SLOA100-Nov. 2002; 52 pages.23Adaptive Impedance Matching; Anees S. Munshi et al; Department of Electrical and Computer Engineering; University of Toronto; pp. 69-72.24ADSL Line Driver/Receiver Design Guide, Part 1; Tim Regan; Linear Technology Magazine; Feb. 2000; pp. 26-31.25An 8-bit 2-ns Monolithic DAC; Tsutomu Kamoto et al; IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988; pp. 142-146.26An ADSL Integrated Active Hybrid Circuit; James Hellums, et al; Texas Instruments Incorporated; 23 pages.27An Integratable 1-2.5Gbps Low Jitter CMOS Transceiver with Built in Self Test Capability; Ah-Lyan Yee et al; Texas Instruments, Inc.; 1999 Symposium on VLSI Circuits Digest of Technical Papers; pp. 45-46.28An Operational Amplifier Circulator Based on the Weighted Summer; Fuad Surial Atiya; IEEE Transactions on Circuits and Systems, vol. CAS-22, No. 6, Jun. 1975; pp. 516-523.29Analysis and Design of Analog Integrated Circuits; Fourth Edition; 7 pages.30Analysis and Design of Analog Integrated Circuits; Fourth Edition; Paul R. Gray et al; 2001; 7 pages.31Analysis of Timing Jitter in CMOS Ring Oscillators; Todd C. Welgandt et al; pp. 27-30.32ANSI INCI TS 263-1995 (R2000) (formerly ANSI X3 263-1995 (R2000); American National Standard for Information Technology-Fibre Distributed Data Interface (FDDI)-Token Ring Twisted Pair Physical Layer Medium Dependent (TP-PMD); Developed by incits; 80 pages.33ANSI/IEEE Std 802.11, 1999 Edition; Information technology-Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications; LAN/MAN Standards Committee of the IEEE Computer Society; 528 pages.34Charge-Pump Phase-Lock Loops; Floyd M. Gardner; IEEE Transactions on Communications; vol. Com-28, No. 11, Nov. 1980; pp. 1849-1858.35CODEC for Echo-Canceling, Full-Rate ADSL Modems; Richard K. Hester; IEEE Journal of Solid-State Circuits, vol. 34, No. 12, Dec. 1999; pp. 1973-1985.36Coding, Iterative Detection and Timing Recovery for Magnetic Recording Channels; A Dissertation by Zi-Ning Wu; Aug. 1999; 159 pages.37Combining Echo Cancellation and Decision Feedback Equalization; K. H. Mueller; The Bell System Technical Journal; Feb. 1979, vol. 58, No. 2; Cover page and pp. 491-500.38Delay-Based Monolithic CMOS Frequency Synthesizer for Portable Wireless Applications; George Chien, University of California, Berkeley, CA; Qualifying Exam; May 20, 1998; 28 pages.39Digital General of Low-Frequency Sine Waves; Anthony C. Davies; IEEE Transactions on Instrumentation and Measurement, vol. IM-18, No. 2; Jun. 1969; Cover page and pp. 97-105.40Digital Logic and Computer Design; M. Morris Mano; 1979; 627 pages.41Digital Systems Engineer; William J. Dally and John W. Poulton; Cover page and pp. 390-391.42Digital-to-analog Converter having Common-mode Isolation and Differential Output; G. A. Hellwarth and S. Boinodiris; Jul. 19, 1972; pp. 54-60.43Doppler Estimation Using a Coherent Ultrawide-Band Random Noise Radar; Ram M. Narayanan; IEEE Transactions on Antennas and Propagation; vol. 48, No. 6, Jun. 2000; pp. 868-878.44DP83220 CDL Twisted Pair FDDI Transceiver Device; National Semiconductor, Advance Information, Oct. 1992; 10 pages.45Dual Mode Transmitter with Adaptively Controlled Slew Rate and Impedance Supporting Wide Range Data Rates; Hongjiang Song; Intel Corporation; Chandler, Arizona; 2001 IEEE; pp. 321-324.46Expermental Results and Modeling Techniques for Substate Noise in Mixed-Signal Integrated Circuits; David K. Su et al, IEEE Journal of Solid-State Circuits, vol. 28, No. 4, Apr. 1993; pp. 420-430.47FA 10.7: An Adaptive Cable Equalizer for Serial Digital Video Rates to 400Mb/s; Alan J. Baker; ISSCC96/ Feb. 9, 1996; 3 pages.48FA 18.5: A Delay Line Loopfor Frequency Synthesis of De-Skewed Clock; Alex Waizman; ISSCC94/Session 18;High-Performance Logic and Circuit Techniques/Paper FA 18.5; 1994; pp. 298-299.49FP 12.1: NRZ Timing Recovery Technique for Band-Limited Channels; Bang-Sup Song and David Soo; ISSCC96 Session 12/ Serial Data Communications/Feb. 9, 1996; 3 pages.50FP 12.1: NRZ Timing Recovery Technique for Band-Limited Channels; Bang-Sup Song and David Soo; ISSCC96 Session 12/ Serial Data Communications/Feb. 9, 1996; Slides; 4 pages.51FP 13.5: A 100 Mb/s CMOS 100Base-T4 Fast Ethernet Transceiver for Category 3, 4 and 5 UTP; K. Chan et al; IEEE 1998; pp. 13.5-1-13.5-10.52FP 13.6: A 10/100Mb /s CMOS Ethernet Transceiver for 10BaseT, 100BaseTX, and 100BaseFX; J. Everitt et al; IEEE 1998; pp. 13.6-1 through 13.6-9.53Future Directions in Silicon ICs for RF Personal Communication; P.R. Gray et al; IEEE 1995 Custom Integrated Circuits Conference; pp. 83-90.54Gigabit Ethernet 1000Base-T; 1997; 15 pages.55Good Error-Correcting Codes Based on Very Sparse Matrices; David J. MacKay; IEEE Transactions on Information Theory; vol. 45, No. 2, Mar. 1999; pp. 399-431.56High Speed Modem Solutions InfoCard 20; Linear Techology; 6 pages.57High-Performance Electrical Signaling; William Dally et al; 6 pages.58IEEE 802.20-PD-06, IEEE P 802.20 V14, Jul. 16, 2004, Draft 802.20 Permanent Document, System Requirements for IEEE 802.20 Mobile Broadband Wireless Access Systems-Version 14, 23 pages.59IEEE Std 802.11a-1999 (Supplement to IEEE Std 802.11-1999) [Adopted by ISO/IEC and redesignated as ISO/IEC 8802-11: 1999/Amd 1:2000(E)]; Supplement to IEEE Standard for Information technology-Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications High-speed Physical Layer in the 5 GHz Band; LAN/MAN Standards Committee of the IEEE Computer Society; 91 pages.60IEEE Std 802.11b-1999 (Supplement to IEEE Std 802.11-1999 Edition); Supplement to IEEE Standard for Information technology-Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Higher-Speed Physical Layer Extension in the 2.4 GHz Band; LAN/MAN Standards Committee of the IEEE Computer Society; Sep. 16, 1999 IEEE-SA Standards Board; 96 pages.61IEEE Std 802.11g/D2.8, May 2002 (Supplement to ANSI/IEEE Std 802.11, 1999 Edition) Draft Supplement to Standard [for] Information Technology-Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Further Higher-Speed Physical Layer Extension in the 2.4 GHz Band; LAN/MAN Standards Committee of the IEEE Computer Society; 53 pages.62IEEE Std 802.16-2004 (revision of IEEE Std 802.16-2001) IEE Standard for Local and metropolitan area networks; Part 16: Air Interface for Fixed Broadband Wireless Access Systems; IEEE Computer Society and the IEEE Microwave Theory and Techniquest Society; Oct. 1, 2004; 893 pages.63Integrated Analog-to-Digital and Digital-to-Analog Converters; Rudy Van de Plassche; Philips Research Laboratories, The Kluwer International Series in Engineering and Computer Science; 1994; 33 pages.64Large Suspended Inductors on Silicon and Their Use in a 2-mum CMOS RF Amplifier; J.y.-C. Chang et al; IEEE Electron Device Letters, vol. 14, No. 5, May 1993; pp. 246-248.65Low-Density Parity-Check Codes; R. G. Gallager; IRE Transactions on Information Theory; 1962; pp. 21-28.66Low-Density Parity-Check Codes; Robert G. Gallager; 1963; 90 pages.67Low-Noise Local Oscillator Design Techniques using a DLL-based Frequency Multiplier for Wireless Applications; George Chien; 2000; 188 pages.68Low-Noise Local Oscillator Design Techniques using a DLL-based Frequency Multiplier for Wireless Applications; George Chien; A dissertation; Spring 2000; 178 pages.69Micro-Electronic Circuits; Adel S. Sedra; 1982; 2 cover pages, pp. 95-97, 243-244, 246-247.70Microelectronic Circuits; Third Edition; Adel S. Sedra and Kenneth C. Smith, University of Toronto; 1991; two cover pages and pp. 48-115.71Monolithic CMOS Frequency Synthesizer for Cellular Applications; George Chien and Paul R. Gray; University of California, Berkeley; http://www.eecs.berkeley.edu/-gchien; 9 pages.72MP 2.3 A Mixed-Signal 120MSample/s PRML Solution for DVD Systems; Rex Baird et al; Cirrus Logic; 10 pages.73Multifrequency Zero-Jitter Delay-Locked Loop; Avner Efendovich et al; IEEE Journal of Solid-State Circuits; vol. 29, No. 1, Jan. 1996; pp. 67-70.74On-chip Terminating Resistors for High Speed ECL-CMOS Interfaces; Thaddeus J. Gabara; AT&T Bell Laboratories; pp. 292-295.75Parity Check Codes for Partial Response Channels; Mats Oberg and Paul H. Siegel; Global Telecommunications Conference, 1999 IEEE; pp. 717-722.76PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design; Beomsup Kim et al; pp. 31-34.77Pulse, Digital, and Switching Waveforms, Jacob Millman and Herbert Taub; 1965; 3 pages.78Si IC-Compatible Inductors and LC Passive Filters; Nguyen, et al; IEEE Journal on Solid State Circuits, vol. 25, No. 4, Aug. 1990; pp. 1028-1031.79SP 21.2: A 1.9GHz Single-Chip IF Transceiver for Digital Cordless Phones; Hisayasu et al; 3 pages.80SP 24.6: A 900MHz CMOS LC-Oscillator with Quadrature Outputs; Ahmadreza Rotougraan et al; Electrical Engineering Dept., University of California, Los Angeles, CA; 2 pages.81Specifications for Obsolete Product ITU CO/Loop Carrier SLIC; HC-5509B, Aug. 2003; 9 pages.82The Capacity of Low-Density Parity-Check Codes Under Message-Passing Decoding; Thomas J. Richardson and R. L. Urbanke; IEEE Transactions on Information Theory; vol. 47, No. 2, Feb. 2001; pp. 599-618.83The HC-5502X/4X Telephone Subscriber LIne Interface Circuits (SLIC); Application Note; Jan. 1997; AN549.1; Geoff Phillips; 17 pages.84TP 12.4: A 900-MHz Local Oscillator using a DLL-based Frequency Multiplier Technique for PCS Applications; George Chien and Paul R. Gray; University of California, Berkeley, CA; 3 pages.85TP 13.5 A Single-Chip CMOS Direct-Conversion Transceiver for 900 MHz Spread-Spectrum Digital Cordless Phones; Thomas Cho et al; Level One Communications, Inc., San Francisco, CA; 10 pages.86TP 9.2: A 900 MHz-Transceiver Chip Set for Dual-Mode Cellular Radio Mobile Terminals; Iconomos A. Joullias et al; ISSCC 93/Session 9/Radio Communication Circuits/Paper TP 9.2; 1993 IEE International Solid-State Circuits Conference; pp. 140-141, 278.87U.S. Appl. No. 09/559,186, filed Aug. 8, 2001, Nersi Nazari et al.88U.S. Appl. No. 09/730,597, filed Aug. 8, 2001, Burd et al.89U.S. Appl. No. 09/730,598, filed Aug. 8, 2001, Wu et al.90U.S. Appl. No. 09/730,603, filed Dec. 7, 2000, Wu et al.91U.S. Appl. No. 09/730,752, filed Aug. 8, 2001, Burd et al.92U.S. Appl. No. 09/737,743, filed Dec. 18, 2000, Sutardja, Sehat.93U.S. Appl. No. 09/901,507, filed Jul. 9, 2001, Wu et al.94U.S. Appl. No. 09/920,241, filed Aug. 1, 2001, Roo, Pierte.95WA 18.3 A Gigabit Transceiver Chip Set for UTP CAT-6 Cables in Digital CMOS Technology; Kamran Azadet et al; DSP and VLSI Systems Research Dept., Bell Labs, Lucent Technologies, Holmdel, NJ; 2000 IEEE International Solid-State Circuits Conference; 9 pages.96WA 18.4 A 3V Low-Power 0.25 m CMOS 100Mb/s Receiver for Fast Ethernet; Omid Shoaei et al; 2000 IEEE International Solid-State Circuits Conference; 10 pages.97WA 18.5 A MIxed-Signal DFE/FFE Receiver for 100Base-TX Applications; N. Patrick Kelly et al; Level One Communications, Inc., Sacramento, CA; 2000 IEEE International Solid-State Circuits Conference; 9 pages.98WA 18.7 A Combined 10/125Mbaud Twisted-Pair Line Driver with Programmable Performance/Power Features; Ayal Shoval et al; Lucent Technologies, Allentown, PA; 2000 IEEE International Solid-State Circuits Conference; pp. 314-315.99WP 23.7 A 6.5GHz Monolithic CMOS Voltage-Controlled Oscillator; Tin-Ping Liu; 1999 IEEE International Solid-State Circuits Conference; pp. 404-405, 484.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8037388Jul 30, 2007Oct 11, 2011Stmicroelectronics SaMethod and device for layered decoding of a succession of blocks encoded with an LDPC codeUS8046658 *Aug 6, 2007Oct 25, 2011Stmicroelectronics SaMethod and device for decoding blocks encoded with an LDPC codeUS8966339Jan 15, 2013Feb 24, 2015Western Digital Technologies, Inc.Decoder supporting multiple code rates and code lengths for data storage systems* Cited by examinerClassifications U.S. Classification714/755, 714/786International ClassificationH03M13/00Cooperative ClassificationH03M13/6544, H03M13/2957, H03M13/2975European ClassificationH03M13/65K8, H03M13/29T3, H03M13/29TLegal EventsDateCodeEventDescriptionMar 10, 2006ASAssignmentOwner name: MARVELL INTERNATIONAL LTD., BERMUDAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL SEMICONDUCTOR, INC.;REEL/FRAME:017844/0066Effective date: 20060309Mar 18, 2006ASAssignmentOwner name: MARVELL SEMICONDUCTOR, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HE, RUNSHENG;REEL/FRAME:017657/0276Effective date: 20060309Feb 19, 2013FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services