Source: http://www.google.com/patents/US7834407?dq=5893120
Timestamp: 2015-03-29 21:01:47
Document Index: 306196701

Matched Legal Cases: ['application No. 2005', 'art 9', 'art 11', 'art 9', 'art 9', 'art 11', 'art 11', 'art 9', 'art 11', 'art 11', 'art 11', 'art 9', 'art 9', 'art 9', 'art 11', 'art 11', 'art 9', 'art 11', 'art 9', 'art 9', 'art 11', 'art 11', 'art 11', 'art 9', 'art 11', 'art 11', 'art 40', 'art 40', 'art 40', 'art 41', 'art 41', 'art 41']

Patent US7834407 - Semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsIn a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode,...http://www.google.com/patents/US7834407?utm_source=gb-gplus-sharePatent US7834407 - Semiconductor deviceAdvanced Patent SearchPublication numberUS7834407 B2Publication typeGrantApplication numberUS 12/471,680Publication dateNov 16, 2010Filing dateMay 26, 2009Priority dateMay 20, 2005Fee statusPaidAlso published asUS8232610, US8592920, US8604563, US20060261391, US20090230467, US20100327359, US20120241855, US20120241856, US20140193968Publication number12471680, 471680, US 7834407 B2, US 7834407B2, US-B2-7834407, US7834407 B2, US7834407B2InventorsYoshito Nakazawa, Yuji YatsudaOriginal AssigneeRenesas Electronics CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (46), Referenced by (2), Classifications (31), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device
US 7834407 B2Abstract
In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.
(a) a field-effect transistor having a trench gate structure with a dummy gate electrode,
the field-effect transistor comprising:
a drain region of the field effect transistor disposed over a semiconductor substrate;
a channel forming region of the field-effect transistor disposed over the drain region;
a source region of the field-effect transistor disposed over the channel forming region;
a trench reaching the drain region from an upper surface of the source region;
a first insulating film disposed in the trench and disposed at a lower part of the trench;
a first conductive film disposed over the first insulating film in the trench and disposed at the lower part of the trench, the first conductive film serving as the dummy gate electrode;
a gate insulating film of the field-effect transistor disposed over the first insulating film in the trench and disposed at a upper part of the trench;
a gate electrode of the field-effect transistor disposed over the gate insulating film in the trench and disposed at the upper part of the trench,
wherein the gate electrode and the first conductive film are separately disposed in the trench in which a second insulating film is disposed between the gate electrode and the first conductive film, and
wherein a thickness of the gate insulating film is less than a thickness of the first insulating film; and
(b) a protective diode including a second conductive film which is formed by same film layer as the first conductive film,
wherein the field-effect transistor and the protective diode are formed over the same semiconductor substrate.
2. The semiconductor device according to claim 1, wherein a cathode region of the protective diode is connected to the gate electrode of the field-effect transistor, and an anode region of the protective diode is connected to a source region of the field-effect transistor.
3. The semiconductor device according to claim 1, wherein an anode region of the protective diode is connected to the gate electrode of the field-effect transistor, and a cathode region of the protective diode is connected to the source region of the field-effect transistor.
4. The semiconductor device according to claim 1, wherein a plurality of protective diodes are connected between the gate electrode and the source region of the field-effect transistor.
5. The semiconductor device according to claim 1, wherein the second conductive film is formed by a polycrystalline silicon film and is formed in the same step as that of a polycrystalline silicon film for the dummy gate electrode.
6. The semiconductor device according to claim 1, wherein a cathode region of the protective diode is formed in the same step as that of the source region of the field-effect transistor.
7. The semiconductor device according to claim 1, wherein a concentration of impurities introduced in the dummy gate electrode is lower than that of impurities introduced in the gate electrode of the field-effect transistor.
8. The semiconductor device according to claim 1, wherein a resistance of the dummy gate electrode is larger than that of the gate electrode of the field-effect transistor.
9. The semiconductor device according to claim 1, wherein a thickness of a lead-out part for the dummy gate electrode is smaller than that of a lead-out part for the gate electrode of the field-effect transistor.
10. The semiconductor device according to claim 1, wherein the dummy gate electrode and the gate electrode of the field-effect transistor are set at a same potential.
11. The semiconductor device according to claim 1, wherein a first contact hole connected to the dummy gate electrode and a second contact hole connected to the gate electrode of the field-effect transistor are arranged linearly, and a gate interconnection is disposed linearly over the first contact hole and the second contact hole.
wherein the dummy gate electrode is connected to the source region of the field-effect transistor, and
wherein the first contact hole connected to the dummy gate electrode and the second contact hole connected to the gate electrode of the field-effect transistor are arranged linearly, and in a position where a source electrode over the first contact hole is formed in a recessed shape, the corresponding gate interconnection over the second contact hole is formed in a convex shape, while, in a position where the source electrode is formed in a convex shape, the corresponding gate interconnection is formed in a recessed shape.
wherein the protective diode is electrically coupled between the gate electrode and the source region of the field-effect transistor.
14. The semiconductor device according to claim 4, wherein one cathode region of the plurality of protective diodes whose anode regions are connected to each other is connected to the gate electrode of the field-effect transistor, and the other cathode region thereof is connected to the source region of the field-effect transistor. Description
CONTINUING AND PRIORITY DATA INFORMATION
This application is a Continuation Application of U.S. Ser. No. 11/432,491, filed May 12, 2006, now abandoned the content of which is hereby incorporated by reference into this application. The present application claims priority from Japanese patent application No. 2005-147914 filed on May 20, 2005, the content of which is hereby incorporated by reference into this application.
[Patent document 1] Japanese Patent Publication
[Patent document 5] Japanese Unexamined Patent Publication No. Hei 04 (1992)-229662
When a voltage is applied to the drain region with the gate and the source region being grounded, the electric field becomes strongest at the bottom of the trench. Thus, a withstand voltage (BVdss) is determined based on a voltage which causes avalanche breakdown in the vicinity of the bottom of the trench. In the power MISFET having the trench gate structure provided with the dummy gate electrode, an effect of releasing the electric field of the dummy gate electrode can weaken the electric field at the bottom of the trench, and thus reduce the frequency of occurrence of the avalanche breakdown in the vicinity of the trench. Thus, the power MISFET has an advantage of improving the withstand voltage (BVdss) For this reason, the power MISFET having the trench gate structure with the dummy gate electrode has been used. It should be noted that the withstand voltage (BVdss) is a breakdown voltage obtained when a voltage is applied between the source region and the drain region with the gate electrode and the source region short-circuited.
A plurality of n+-type semiconductor regions 15 and p−-type semiconductor regions 8 a are formed between the source electrode 24 and the gate pad GP. That is, a plurality of protective diodes (Zener diodes) each made of a pn junction are formed between the source electrode 24 and the gate pad GP. Referring to FIG. 2, two sets of pairs of protective diodes which are connected so as to be oriented in different directions from each other (back to back) are formed between the source electrode 24 and the gate pad GP in series. More specifically, two sets of pairs of protective diodes, each pair consisting of anode electrodes (p−-type semiconductor regions 8 a serving as an anode region) connected to each other, are connected in series. Cathode electrodes of one pair of protective diodes (n+-type semiconductor region 15 serving as a cathode region) are connected to the gate interconnection 25. And, cathode electrodes of the other pair of protective diodes (n+-type semiconductor region 15) are connected to the source electrode 24.
The n-channel-type power MISFET includes a source region 14 which is a semiconductor region provided in the n-type epitaxial layer 2, and a drain region consisting of the n-type epitaxial layer 2 and the semiconductor substrate 1. In the n-type expitaxial layer 2 between the source region 14 and the drain region, a semiconductor region 13 for formation of a channel (channel forming region) is formed. For example, elements, such as phosphorous (P) or arsenic (As), are introduced or implanted into the source region 14, and elements, such as boron (B), are introduced or implanted into the semiconductor region 13 for channel formation.
A plurality of trenches 6 extending in a direction perpendicular to the main surface of the semiconductor substrate 1 (in a thickness direction of the semiconductor substrate 1) are formed on the main surface side of the substrate 1. The trench 6 penetrates the semiconductor region 13 for channel formation from the main surface side of the semiconductor substrate 1, and ends at the lower part of the n-type epitaxial layer 2. That is, the trench 6 is formed so as to extend from the upper surface of the source region 14 to reach the drain region.
In FIG. 3, at the lower part of the inside of each of the two trenches 6 as illustrated on the right side of the figure, a dummy gate electrode 9 a is formed via an insulating film (first insulating film) 7. At the upper part of the inside of the trench 6, a gate electrode 11 a is formed via a gate insulating film 10. Although the insulating film 7 and the gate insulating film 10 are made of, for example, a silicon oxide film, the thickness of the insulating film 7 is greater than that of the gate insulating film 10. More specifically, the thickness of the insulating film 7 is, for example, about 200 nm, and the thickness of the gate insulating film 10 is, for example, about 50 nm.
The dummy gate electrode 9 a and the gate electrode 11 a are made of, for example, a polycrystalline silicon film having low resistance, and insulated from each other by an insulating film intervening between the dummy gate electrode 9 a and the gate electrode 11 a. The dummy gate electrode (made of a first conductive film) 9 a is electrically connected to the gate electrode 11 a. That is, in the first embodiment, the dummy gate electrode 9 a and the gate electrode 11 a are set at the same potential, whereby the withstand voltage of the gate electrode 11 a cannot be affected by an insulation resistance of the insulating film intervening between the dummy gate electrode 9 a and the gate electrode 11 a, resulting in improved withstand voltage of the gate electrode 11 a. That is, the withstand voltage of the gate electrode 11 a is apt to be affected by the insulation resistance of the insulating film intervening between the dummy gate electrode 9 a and the gate electrode 11 a. In the first embodiment, however, the dummy gate electrode 9 a and the gate electrode 11 a with the insulating film sandwiched therebetween are set at the same potential, so that a voltage load is not applied to the intervening insulating film, thereby improving the withstand voltage of the gate electrode 11 a. The gate electrode 11 a is a control electrode of the power MISFET, to which a voltage for control of the operation of the power MISFET is applied. The upper surface of the gate electrode 11 a is slightly lower than the top part on the main surface side of the semiconductor substrate 1 (namely, the upper surface of the source region 14). On the upper surface of the gate electrode 11 a recessed downward, sidewalls 12 made of, for example, a silicon oxide film, are embedded. A channel of the power MISFET is formed in the semiconductor region 13 for channel formation opposite to the side of the gate electrode 11 a. That is, a channel current of the power MISFET passes along the side of the trench 6 in the thickness direction of the semiconductor substrate 1 which is perpendicular to the substrate 1.
In FIG. 3, the trench 6 positioned on the outmost periphery (on the left side) does not act as the power MISFET, and a lead-out part 9 b for the dummy gate electrode is formed in the trench via the insulating film 7. A lead-out part 11 b for the gate electrode is formed over the lead-out part 9 b for the dummy gate electrode via the gate insulating film 10. The lead-out part 9 b for the dummy gate electrode is electrically connected to the dummy gate electrode 9 a, and the lead-out part 11 b for the gate electrode is electrically connected to the gate electrode 11 a. Over the main surface of the semiconductor substrate 1, is formed an interlayer dielectric 16, from which a contact hole (second contact hole) 17 reaching the lead-out part 11 b for the gate electrode is formed. Similarly, a contact hole 18 reaching the semiconductor region 13 for channel formation is formed from the interlayer dielectric 16. The contact hole 18 is in contact with the source region 14. Note that, although not shown in FIG. 3, another contact hole (first contact hole) reaching the lead-out part 9 b for the dummy gate electrode from the interlayer dielectric 16 is formed without being in contact with the lead-out part 11 b for the gate electrode.
The gate interconnection 25 is formed so as to embed the contact hole 17 reaching the lead-out part 11 b for the gate electrode from the interlayer dielectric 16. That is, the lead-out part 11 b for the gate electrode is electrically connected to the gate interconnection 25. Similarly, the source electrode 24 is formed so as to embed the contact hole 18 reaching the semiconductor region 13 for the channel formation from the interlayer dielectric 16. The source electrode 24 and the gate interconnection 25 are made of a laminate consisting of a barrier metal film and a metal film. The barrier metal film is made of, for example, a titanium tungsten (TiW) film 22. The metal film is made of, for example, an aluminum film 23, or an aluminum alloy film.
A polyimide resin film 27 is formed as the passivation film over the main surface of the semiconductor substrate 1 with the source electrode 24 and the gate interconnection 25 formed thereon. The polyimide resin film 27 positioned on the source pad which is a part of the source electrode 24 is removed, which causes the source pad to be exposed to the outside. A drain electrode 29 is formed on a back surface opposite to the main surface of the semiconductor substrate 1, and is a laminate consisting of, for example, a titanium (Ti) film 28 a, a nickel (Ni) film 28 b, and a gold (Au) film 28 c. The power MISFET of the embodiment is provided with the dummy gate electrode 9 a, the function of which will be described hereinafter in detail.
In the known power MISFET without the dummy gate electrode 9 a, when a voltage is applied to the drain region with the gate electrode and the source region being grounded, the electric field becomes strongest at the bottom of the trench in which the gate electrode is formed. Thus, a withstand voltage (BVdss) of the power MISFET is determined based on a voltage which causes avalanche breakdown in the vicinity of the bottom of the trench. Since there exists only a relatively thin gate insulating film at the bottom of the trench, the electric field intends to become strong between the gate and the drain.
In contrast, although in the power MISFET provided with the dummy gate electrode 9 a such as that shown in FIG. 3, the electric field intends to become strongest at the bottom of the trench 6 of the dummy gate electrode 9 a, the presence of the insulating film 7 which is thicker than the gate insulating film 10 is likely to release the electric filed between the dummy gate electrode 9 a and the drain region. This power MISFET can improve the withstand voltage (BVdss) as compared with the power MISFET not provided with the dummy gate electrode 9 a. Furthermore, the provision of the dummy gate electrode 9 a has the following advantages. Generally, in the power MISFET, the gate insulating film is thinned thereby to improve the performance thereof. However, the power MISFET without the dummy gate electrode 9 a has a disadvantage that the gate insulating film cannot be thinned so much. That is, although in the power MISFET not provided with the dummy gate electrode 9 a, the gate electrode is formed inside the trench via the gate insulating film, there exists a weak spot at the corner of the trench where the defective formation of the gate insulating film intends to occur. This makes it impossible to thin the gate insulating film.
In contrast, in the power MISFET provided with the dummy gate electrode 9 a, the dummy gate electrode 9 a is formed via the insulating film 7 in the lower part of the trench 6, while the gate electrode 11 a is formed via the gate insulating film 10 in the upper part of the trench 6. Thus, at the corner of the bottom part of the trench 6, not the gate insulating film 10, but the insulating film 7 is formed. This insulating film 7 is thicker than the gate insulating film 10 in order to improve the withstand voltage (BVdss). Thus, even if the gate insulating film 10 is thinned, the corner of the bottom of the trench does not become a weak spot. As mentioned above, the power MISFET provided with the dummy gate electrode 9 a has the advantage that the thinning of the gate insulating film can improve the performance of the MISFET.
The thinning of the gate insulating film 10 may lead to reduction in electrostatic breakdown resistance of the gate insulating film 10. However, in the embodiment, the power MISFET provided with the dummy gate electrode 9 a and the protective diode connected to this MISFET are formed on the same semiconductor substrate 1. This achieves the thinning of the gate insulating film 10, while ensuring the electrostatic breakdown resistance of the gate insulating film 10.
FIG. 4 is a section view taken along a line B-B of FIG. 2. As shown in FIG. 4, the power MISFET with the dummy gate electrode 9 a and the protective diode are formed over the main surface of the semiconductor substrate 1. The protective diode is made of the pn junction occurring between the p−-type semiconductor region 8 a and the n+-type semiconductor region 15. In FIG. 4, the p−-type semiconductor regions 8 a and the n+-type semiconductor regions 15 are formed alternately between the gate interconnection 25 (electrically connected to the gate electrode 11 a) and the source electrode 24, which forms the four protective diodes. These four protective diodes are arranged in two sets of pairs positioned in series, each pair of diodes being connected together so as to be oriented in different directions from each other.
The operation of the motor control circuit according to the embodiment will be described hereinafter in detail. First, the gate drive circuit 30 turns on the power MISFET 33 and the power MISFET 34, and turns off the power MISFET 32 and the power MISFET 35. Thus, the positive electrode of the direct current power supply 36 is connected to a terminal 31 a of the motor 31 via the power MISFET 34. On the other hand, the negative electrode of the direct current power supply 36 is connected to a terminal 31 b of the motor 31 via the power MISFET 33. This rotates the motor 31 in a predetermined direction. Next, the gate drive circuit 30 turns on the power MISFET 32 and the power MISFET 35, and turns off the power MISFET 33 and the power MISFET 34. Then, the positive electrode of the direct current power supply 36 is connected to a terminal 31 b of the motor 31 via the power MISFET 32. On the other hand, the negative electrode of the direct current power supply 36 is connected to a terminal 31 a of the motor 31 via the power MISFET 35. This rotates the motor 31 in a reverse direction from the above-mentioned direction because the motor is connected reversely with respect to the connecting condition mentioned above. According to the motor control circuit of the embodiment, the rotating direction of the motor 31 can be controlled.
Subsequently, the insulating film 5 made of, for example, a silicon oxide film, is formed over the main surface of the semiconductor substrate 1. Although in the embodiment, the silicon oxide film is used, other materials, such as a silicon nitride film (Si3N4), may be used. Thereafter, a resist pattern is formed on the insulating film 5, using a series of photolithography steps, which involves applying a photoresist film (hereinafter referred to as a simple �resist film�), exposing, and developing. By etching the insulating film 5 using the resist pattern as an etching mask, and removing the resist pattern, the insulating film 5 for formation of the trenches is subjected to patterning. The pattern of the insulating film 5 has a function of serving as a hard mask film for formation of the trenches. In the protective diode forming region, the element isolation region 4 is covered with the insulating film 5.
A polycrystalline silicon film (first polycrystalline silicon film) 8 is formed over the main surface of the semiconductor substrate 1. The polycrystalline silicon film 8 is an intrinsic polycrystalline silicon film into which conductive impurities are not introduced, which film is formed by, for example, a chemical vapor deposition (CVD) method. The polycrystalline silicon film 8 is formed in the power MISFET forming region as well as in the protective diode forming region. The polycrystalline silicon film 8 serves as a polycrystalline silicon film for the dummy gate electrode (first conductive film), and as a polycrystalline silicon film for the protective diode (second conductive film), as mentioned later That is, in the first embodiment, the polycrystalline silicon film for the dummy gate electrode and the polycrystalline silicon film for the protective diode are simultaneously formed as the polycrystalline silicon film 8. This method has an advantage that it can simplify the process as compared with a case where the polycrystalline silicon film for the dummy gate electrode and the polycrystalline silicon film for the protective diode are independently formed in the different steps.
Then, as shown in FIG. 10, p-type impurities, such as boron (B), are introduced into the polycrystalline silicon film 8 formed over the semiconductor substrate 1 using the ion implantation method to form a p−-type semiconductor region 8 a. Thereafter, as shown in FIG. 11, a high concentration of n-type impurities is introduced into the p−-type semiconductor region 8 a of the power MISFET using the photolithography technique and the ion implantation method to form an n+-type semiconductor region 8 b. The n-type impurities include, for example, phosphorus (P), arsenic (As) and antimony (Sb) Subsequently, heat treatment (annealing process) is applied to the semiconductor substrate 1 at a temperature of, for example, 1100 degrees (� C.) or more. This heat treatment is carried out so as to increase a grain size (crystal grain size) of the polycrystalline silicon film 8 constituting the p−-type semiconductor region 8 a and the n+-type semiconductor region 8 b, As mentioned later, because the grain size of the p−-type semiconductor region 8 a, which is apart of the protective diode, is increased, the p−-type semiconductor region 8 a can decrease a leakage current from the protective diode. This is because the grain size of the semiconductor region 8 a is increased by high-temperature heat treatment, which leads to reduction in grain boundary across the pn junction of the protective diode (a boundary of the crystal grain). That is, since the grain boundary which may be the path of the leakage current, is reduced, the leakage current of the protective diode can be decreased. This high-temperature heat treatment is desirably carried out before forming the semiconductor region for the channel formation, as mentioned later. If the high-temperature heat treatment were carried out after forming the semiconductor region for the channel formation, the semiconductor region for the channel formation would be diffused, thus failing to achieve shallow junction of the channel part, which might be at a disadvantage in enhancing the performance of the power MISFET.
Then, as shown in FIG. 12, the polycrystalline silicon film 8 including the n+-type semiconductor region 8 b is subjected to patterning using the photolithography technique and the etching technique. Thus, the polycrystalline silicon film 8 formed in the trench 6 is etched up to a mid-point of the depth thereof to form the dummy gate electrode 9 a in the trench 6. The lead-out part 9 b for the dummy gate electrode is formed on the semiconductor substrate 1 by patterning. The lead-out part 9 b for the dummy gate electrode 9 a is formed so as to be electrically connected to the dummy gate electrode 9 a. At this time, the grain size of the polycrystalline silicon film 8 including the n+-type semiconductor region 8 b is increased by the above-mentioned heat treatment. This can effectively prevent the defective formation of the dummy gate electrode 9 a. Then, as shown in FIG. 13, the insulating film 7 is subjected to patterning by the photolithography and etching techniques. FIG. 14 illustrates a plan view of the chip region CR subjected to the above-mentioned steps. In FIG. 14, in the protective diode forming region, the p−-type semiconductor region (anode region) 8 a is formed, while, in the outer periphery of the power MISFET forming region, the lead-out part 9 b for the dummy gate electrode is formed.
The polycrystalline silicon film (second polycrystalline silicon film) is formed over the semiconductor substrate 1 as well as on the gate insulating film 10. This polycrystalline silicon film is formed by, for example, the CVD method, with the n-type impurities added thereinto. That is, in forming the polycrystalline silicon film, for example, then-type impurities, such as phosphorus or arsenic, are introduced into the polycrystalline silicon film. Thereafter, using the photolithography and etching techniques, the polycrystalline silicon film is subjected to patterning to form the gate electrode 11 a in the trench 6. The gate electrode 11 a has a recessed structure lower than the top part on the main surface side of the semiconductor substrate 1. By the application of patterning to the polycrystalline silicon film, the lead-out part 11 b for the gate electrode is formed. The lead-out part 11 b for the gate electrode is electrically connected to the gate electrode 11 a. The concentration of the n-type impurities introduced into the gate electrode 11 a is higher than that of the n-type impurities introduced into the dummy gate electrode 9 a. In other words, the resistance of the gate electrode 11 a is low as compared with that of the dummy gate electrode 9 a. This is because the higher resistance of the gate electrode 11 a makes it difficult for the power MISFETs connected in parallel to act uniformly. That is, if the power MISFETs do not operate uniformly, the electrostatic breakdown resistance of the gate insulating film, and the avalanche resistance may be decreased, and the switching speed may become slow disadvantageously. Note that when the power MOS is turned off with the dielectric load being connected, a voltage consisting of the sum of a power supply voltage and an induced electromotive force is instantaneously applied between the source region and the drain region. When this voltage exceeds the withstand voltage, the device becomes the avalanche breakdown condition. The avalanche resistance means the product of the maximum value of the avalanche current passing through without causing the breakdown, and the time (that is, the avalanche energy) at this time. To prevent such inconveniences, it is necessary to decrease the resistance of the gate electrode 11 a. For this reason, in formation of the gate electrode 11 a, the polycrystalline silicon film into which impurities, such as phosphorous or arsenic, are previously added, is used. The polycrystalline silicon film into which the impurities are previously added can achieve reduction in resistance of the polycrystalline silicon film, as compared with the polycrystalline silicon film which is formed without addition of the impurities, and then has the impurities introduced by the ion implantation. For example, the polycrystalline silicon film of 500 nm in thickness to which the impurities are previously added can decrease the sheet resistance to about 10Ω/□. In contrast, the polycrystalline silicon film of 500 nm in thickness into which the impurities are introduced by the ion implantation method cannot decrease the sheet resistance only up to about 20Ω/□. Therefore, the polycrystalline silicon film into which the impurities are previously added is used to form the gate electrode 11 a. On the other hand, the dummy gate electrode 9 a, which is different from the gate electrode 11 a of the power MISFET, does not make it difficult for the power MISFETs connected in parallel to act uniformly even if it has a higher resistance than that of the gate electrode 11 a. Moreover, since the dummy gate electrode 9 a is covered with the insulating film 7 whose thickness is greater than that of the gate insulating film 10, the dummy gate electrode 9 a is likely to ensure the electrostatic breakdown resistance even if the resistance of the dummy gate electrode is higher than that of the gate electrode 11 a. Therefore, the dummy gate electrode 9 a can be the polycrystalline silicon film which is made by forming an intrinsic polycrystalline silicon film without addition of impurities, and introducing the impurities into the intrinsic polycrystalline silicon film using the ion implantation method. It should be noted that the dummy gate electrode 9 a can be made of the polycrystalline silicon film into which the impurities are previously added. In the present embodiment, however, since the polycrystalline silicon film for the protective diode and the polycrystalline silicon film for the dummy gate electrode 9 a are simultaneously formed, the polycrystalline silicon film into which the impurities are previously added cannot be used for the formation of the dummy gate electrode 9 a. That is, in the polycrystalline silicon film into which the impurities are previously added, the concentration of the impurities introduced is high, and thus the polycrystalline silicon film cannot be used to form the protective diode. Thus, the polycrystalline silicon film of the protective diode cannot be formed at the same time when the gate electrode 11 a is formed using the polycrystalline silicon film with the impurities previously added thereto. In contrast, since the intrinsic polycrystalline silicon film can be used in the formation of the dummy gate electrode 9 a, the polycrystalline silicon film of the protective diode can be formed at the same time as that of forming the polycrystalline silicon film of the dummy gate electrode. For this reason, in the embodiment, the polycrystalline silicon film for the dummy gate electrode 9 a and the polycrystalline silicon film for the protective diode are simultaneously formed.
FIG. 17 is a plan view of the chip region CR subjected to the foregoing steps. As shown in FIG. 17, in the protective diode forming region, the p−-type semiconductor region 8 a is formed, and in the outer periphery of the power MISFET forming region, the lead-out part 9 b for the dummy gate electrode is formed. The lead-out part 11 b for the gate electrode is formed over the lead-out part 9 b for the dummy gate electrode.
FIG. 20 is a plan view of the chip region CR subjected to the above-mentioned steps. As shown in FIG. 20, in the protective diode forming region, the p�type semiconductor region 8 a and the n+-type semiconductor region 15 are formed to create the protective diode having the pn junction. As shown in the figure, in the power MISFET forming region, the source region 14 is formed.
Another reason why the polycrystalline silicon film for the gate electrode 11 a and the polycrystalline silicon film for the protective diode are not formed simultaneously, and the polycrystalline silicon film for the dummy gate electrode 9 a and the polycrystalline silicon film for the protective diode are formed at the same time will be described below.
As shown in FIG. 19, the dummy gate electrode 9 a is filled in the narrow trench sandwiched between the thick insulating films 7, whereas the gate electrode 11 a of the power MISFET needs to be filled in the wide trench sandwiched between the thin gate insulating films 10. That is, although the dummy gate electrode 9 a and the gate electrode 11 a are formed in the same trench 6, the thick insulating film 7 is formed between the dummy gate electrode 9 a and the trench 6. This narrows a region in which the dummy gate electrode 9 a is filled, by a length of the thick insulating film 7 formed. In contrast, since the thin gate insulating film 10 is formed between the gate electrode 11 a and the trench 6, the region in which the gate electrode 11 a is filled is wider than that in which the dummy gate electrode 9 a is filled. Thus, even if the thickness of the polycrystalline silicon film forming the dummy gate electrode 9 a is smaller than that of the polycrystalline silicon film forming the gate electrode 11 a, the trench 6 can be filled with. That is, the thickness of the lead-out part 9 b for the dummy gate electrode is smaller than that of the lead-out part 11 b for the gate electrode.
More specifically, when the width of the trench 6 is 0.8 μm, the thickness of the insulating film 7 is 200 nm, and the thickness of the gate insulating film 10 is 50 nm, at least the polycrystalline silicon film for the dummy gate electrode 9 a may be deposited to a thickness of 200 nm or more so that the dummy gate electrode 9 a can be filled in the trench region having the width of 0.4 W. In contrast, the polycrystalline silicon film for the gate electrode 11 a needs to be deposited to a thickness of 350 nm or more so that the gate electrode 11 a is required to be filled in the trench region having a width of 0.7 μm.
In forming the protective diode having the n p−junction, the p−-type semiconductor region 8 a is formed by forming the intrinsic polycrystalline silicon film, and then implanting the boron ions into the entire surface of the intrinsic polycrystalline silicon film in a dose amount of about 1�1013/cm2 to 1�1014/cm2. In contrast, the n+-type semiconductor region 15 needs to be selectively formed. The n+-type semiconductor region 15 of the protective diode is formed at the same ion implantation step in which the source region of the power MISFET is selectively formed (at the step of introducing arsenic in an amount of about 1�1015/cm2 to 1�1016/cm2). This can form the protective diode without increasing the number of steps.
Then, as shown in FIG. 21, the interlayer dielectric 16 made of, for example, a silicon oxide film, is formed over the main surface of the semiconductor substrate 1. Thereafter, a resist pattern is formed on the interlayer dielectric 16 by the photolithography technique such that a contact hole forming region is exposed. Subsequently, the interlayer dielectric 16 is etched using the resist pattern formed as an etching mask, and the resist pattern is removed thereby to form the contact holes 17, 18, and 19 in the interlayer dielectric 16. The contact hole 17 reaches the lead-out part 11 b for the gate electrode, and the contact hole 18 reaches the semiconductor region 13 for the channel formation formed over the main surface of the semiconductor substrate 1. The contact hole 19 is formed in the protective diode forming region, and reaches the n+-type semiconductor region 15, which is a cathode region of the protective diode.
FIG. 22 is a plan view of the chip region CR subjected to the above-mentioned steps. As shown in FIG. 22, the contact hole 17 is formed in the lead-out part 11 b for the gate electrode, and the contact hole 18 is formed in the active region. The contact hole 19 is formed in the n+-type semiconductor region 15 of the protective diode, and the contact hole 21 is formed in the lead-out part 9 b for the dummy gate electrode.
The source electrode 24 is formed to fill the contact hole 18, and to be connected to the source region 14 and the p-type semiconductor region 20. The gate interconnection 25 is connected to the lead-out part 11 b for the gate electrode via the contact hole 17. This lead-out part 11 b for the gate electrode is connected to the gate electrode 11 a, and thus the gate interconnection 25 is electrically connected to the gate electrode 11 a. In the protective diode forming region is formed the electrode 26, which is connected to the n+-type semiconductor region 15 via the contact hole 19. One of the electrodes 26 is connected to the source electrode 24, and the other of the electrodes 26 is connected to the gate interconnection 25. This arrangement of the electrodes 26 connects the protective diode between the source electrode 24 and the gate interconnection 25.
After the back surface of the semiconductor substrate 1 is ground, a laminate consisting of a titanium film (not shown) a nickel film (not shown), and a gold film (not shown) is formed on the entire back surface of the substrate 1 using the spattering method, for example. Thus, the drain electrode made of the laminate, which consists of the titanium film, the nickel film, and the gold film, is formed.
Referring to FIG. 25, the contact holes 17 connected to the lead-out part for the gate electrode and the contact holes 21 connected to the lead-out part for the dummy gate electrode are arranged linearly. The contact hole 17 is connected to the gate interconnection 25, while the contact hole 21 is connected to the source electrode 24. A part of the gate interconnection 25 which is connected to the contact hole 17 is a convex part 40 a. A part of the source electrode 24 opposite to the convex part 40 a is a recessed part 40 b. That is, in a position where the source electrode 24 on the contact hole 21 is formed in a recessed shape, the gate interconnection 25 on the contact hole 17 is formed in a convex shape. In contrast, apart of the source electrode 24 which is connected to the contact hole 21 is a convex part 41 a. A part of the gate interconnection 25 opposite to the convex part 41 a is a recessed part 41 b. That is, in a position where the source electrode 24 is formed in a convex shape, the gate interconnection 25 is formed in a recessed shape. With this layout arrangement, the effective area of the semiconductor chip CP can be increased. Note that in FIG. 25, parts of the source electrode 24 and the gate interconnection 25 are omitted so that the contact holes 17 and the contact holes 21 positioned under the gate interconnection 25 can be viewed.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4737468Apr 13, 1987Apr 12, 1988Motorola Inc.SemiconductorsUS5126807Jun 12, 1991Jun 30, 1992Kabushiki Kaisha ToshibaVertical MOS transistor and its production methodUS5272371Nov 19, 1991Dec 21, 1993Sgs-Thomson Microelectronics, Inc.Electrostatic discharge protection structureUS5298781 *Jul 8, 1992Mar 29, 1994Siliconix IncorporatedVertical current flow field effect transistor with thick insulator over non-channel areasUS5998833Oct 26, 1998Dec 7, 1999North Carolina State UniversityPower semiconductor devices having improved high frequency switching and breakdown characteristicsUS6163052 *Dec 16, 1997Dec 19, 2000Advanced Micro Devices, Inc.Trench-gated vertical combination JFET and MOSFET devicesUS6218262Nov 27, 1998Apr 17, 2001Mitsubishi Denki Kabushiki KaishaSemiconductor device and method of manufacturing the sameUS6246092Mar 17, 1998Jun 12, 2001Fuji Electric Co., Ltd.High breakdown voltage MOS semiconductor apparatusUS6323518Sep 13, 1999Nov 27, 2001Hitachi, Ltd.Insulated gate type semiconductor device and method of manufacturing thereofUS6445037Sep 28, 2000Sep 3, 2002General Semiconductor, Inc.Trench DMOS transistor having lightly doped source structureUS6541826Aug 23, 2001Apr 1, 2003Mitsubishi Denki Kabushiki KaishaField effect semiconductor device and its production methodUS6573562 *Oct 31, 2001Jun 3, 2003Motorola, Inc.First conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having theUS6677641 *Oct 17, 2001Jan 13, 2004Fairchild Semiconductor CorporationSemiconductor structure with improved smaller forward voltage loss and higher blocking capabilityUS6700793Jan 16, 2002Mar 2, 2004Renesas Technology CorporationSemiconductor deviceUS6767800Jul 28, 2003Jul 27, 2004Nanya Technology CorporationProcess for integrating alignment mark and trench deviceUS6870220 *Aug 14, 2003Mar 22, 2005Fairchild Semiconductor CorporationMethod and apparatus for improved MOS gating to reduce miller capacitance and switching lossesUS6953976Nov 21, 2002Oct 11, 2005Nec Lcd Technologies, Ltd.Method of deforming a pattern and semiconductor device formed by utilizing deformed patternUS7074691Jun 10, 2005Jul 11, 2006Hitachi, Ltd.Method of manufacturing a semiconductor integrated circuit device that includes forming dummy patterns in an isolation region prior to filling with insulating materialUS7112828 *Sep 24, 2004Sep 26, 2006Rohm Co., Ltd.Semiconductor deviceUS7122860 *May 21, 2003Oct 17, 2006Koninklijke Philips Electronics N.V.Trench-gate semiconductor devicesUS7183610 *Apr 30, 2004Feb 27, 2007Siliconix IncorporatedSuper trench MOSFET including buried source electrode and method of fabricating the sameUS7186618 *Oct 29, 2004Mar 6, 2007Infineon Technologies AgPower transistor arrangement and method for fabricating itUS7187041Oct 13, 2004Mar 6, 2007Matsushita Electric Industrial Co., Ltd.Vertical gate semiconductor device and method for fabricating the sameUS7208391Jun 10, 2005Apr 24, 2007Renesas Technology Corp.Method of manufacturing a semiconductor integrated circuit device that includes forming an isolation trench around active regions and filling the trench with two insulating filmsUS7344932 *Aug 18, 2005Mar 18, 2008Hrl Laboratories, LlcUse of silicon block process step to camouflage a false transistorUS7385248 *Aug 9, 2005Jun 10, 2008Fairchild Semiconductor CorporationShielded gate field effect transistor with improved inter-poly dielectricUS7482661 *May 3, 2005Jan 27, 2009Kabushiki Kaisha ToshibaPattern forming method and semiconductor device manufactured by using said pattern forming methodUS7557409 *Jan 26, 2007Jul 7, 2009Siliconix IncorporatedSuper trench MOSFET including buried source electrodeUS7638841 *May 31, 2006Dec 29, 2009Fairchild Semiconductor CorporationPower semiconductor devices and methods of manufactureUS20020030237 *Jun 28, 2001Mar 14, 2002Ichiro OmuraPower semiconductor switching elementUS20020093094Jan 16, 2002Jul 18, 2002Hitachi, Ltd.Semiconductor deviceUS20030157767Jan 24, 2003Aug 21, 2003Seiko Epson CorporationMethod of manufacturing semiconductor deviceUS20030173618 *Feb 21, 2003Sep 18, 2003Markus ZundelMOS transistor deviceUS20030178676 *Mar 19, 2003Sep 25, 2003Ralf HenningerTransistor configuration with a shielding electrode outside an active cell array and a reduced gate-drain capacitanceUS20040026737 *May 28, 2003Feb 12, 2004Markus ZundelMOS transistor deviceUS20040031987 *Mar 19, 2003Feb 19, 2004Ralf HenningerMethod for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configurationUS20040089910 *Sep 18, 2003May 13, 2004Infineon Technologies AgPower transistorUS20050001268May 28, 2004Jan 6, 2005Baliga Bantval JayantPower semiconductor devices having linear transfer characteristics when regions therein are in velocity saturation modes and methods of forming and operating sameUS20060157779Jan 19, 2006Jul 20, 2006Tsuyoshi KachiSemiconductor device and manufacturing method of the sameUS20060208306 *Mar 16, 2005Sep 21, 2006Nai-Chen PengSingle-poly eepromUS20070114570Jan 23, 2007May 24, 2007Masakazu YamaguchiPower semiconductor deviceUS20090230467 *May 26, 2009Sep 17, 2009Yoshito NakazawaSemiconductor device and manufacturing method of the sameJP2000307109A Title not availableJPH04229662A Title not availableJPH10261713A Title not availableJPS63296282A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7994571 *Oct 22, 2009Aug 9, 2011Rohm Co., Ltd.Semiconductor deviceUS8247866Jul 20, 2011Aug 21, 2012Rohm Co., Ltd.Semiconductor device* Cited by examinerClassifications U.S. Classification257/401, 257/288, 257/E21.38, 257/500, 257/501, 257/E21.444, 257/E21.453, 257/287, 257/502, 257/368, 438/183, 438/270International ClassificationH01L27/088Cooperative ClassificationH01L29/7808, H01L21/28008, H01L27/0255, H01L29/66727, H01L29/407, H01L29/7813, H01L29/0696, H01L29/66734, H01L29/42368, H01L29/4238, H01L29/456, H01L29/7811European ClassificationH01L29/78B2T, H01L29/78B2E, H01L29/40P6, H01L29/78B2A6, H01L29/66M6T6F14V3, H01L29/66M6T6F14V4Legal EventsDateCodeEventDescriptionApr 16, 2014FPAYFee paymentYear of fee payment: 4Jul 23, 2010ASAssignmentOwner name: RENESAS ELECTRONICS CORPORATION,JAPANFree format text: MERGER;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:24736/381Effective date: 20100401Owner name: RENESAS ELECTRONICS CORPORATION, JAPANFree format text: MERGER;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:024736/0381RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services