Source: https://insight.rpxcorp.com/pat/US6496729B2
Timestamp: 2019-10-19 10:09:12
Document Index: 90753006

Matched Legal Cases: ['art 264', 'art 264', 'art 264', 'art 264', 'art 264', 'art 264', 'art 264', 'art 264']

Patent US 6,496,729 B2
1. An implantable medical device of the type having an energy source and providing a therapy to a patient's body and/or monitoring a physiologic condition of the body, comprising:
a clock source that draws energy from the energy source to develop a clock signal having a clock frequency defining a clock cycle between successive clock signals;
timing control means for sequentially defining a sequence of predetermined time periods during which a medical device function is performed including one of delivering a therapy or monitoring physiologic events representative of a physiologic condition and providing a physiologic signal, wherein each predetermined time period extends between a prior predetermined time period and a subsequent predetermined time period;
at least one circuit that performs a function related to the provision of a therapy or monitoring a physiologic condition during at least one of the defined predetermined time periods, the circuit requiring a predetermined number of clock signals to perform the function; and
means for operating the clock source during the predetermined time period to provide a clock signal at a clock frequency providing the predetermined number clock signals to operate the circuit over the predetermined time period;
such that substantially the entire predetermined time period is used to perform the function, wherein the function is completed just prior to the subsequent time period and the number of clock signals applied to the circuit is minimized to conserve energy drawn from the energy source.
US 7,868,779 B2
US 7,757,062 B2
US 20070214336A1
US 6,842,478 B1
SYSTEM AND METHOD OF CONTROLLING POWER CONSUMPTION IN AN ELECTRONIC SYSTEM
US 20050188230A1
US 8,086,814 B2
US 20140100634A1
US 8,762,923 B2
US 8,782,590 B2
US 8,855,780 B2
US 6,163,721 A
US 4,460,835 A
US 4,031,899 A
2. The device of claim 1, wherein the at least one circuit comprises at least a first logic circuit for performing a first function and a second logic circuit for performing a second function, wherein the first logic circuit is operable to perform the first function employing a first predetermined number of clock signals during a first predetermined time period and the second logic circuit is operable to perform the second function employing a second predetermined number of clock signals during a second predetermined time period, and the means for operating the clock source provides a first clock signal at a first clock frequency providing the first predetermined number of clock signals to the first circuit and provides a second clock signal at a second clock frequency providing the second predetermined number of clock signals to the second circuit, whereby each of the first and second logic circuits is operated at a different clock frequency such that substantially the entire respective first and second predetermined time periods are used by the respective first and second logic circuits to perform the respective first and second functions.
a plurality of supply voltage sources derived from the energy source that provide a respective plurality of supply voltages; and
means for applying a supply voltage from a supply voltage source to the circuit as a function of the clock frequency provided to the at least one circuit to minimize energy drawn from the energy source.
9. The device of claim 8, wherein the at least one circuit comprises at least a first logic circuit for performing a first function and a second logic circuit for performing a second function, wherein each of the first and second logic circuits is operated at a clock frequency provided by the means for operating the clock source, and further wherein each of the logic circuits has a supply voltage applied thereto from one of the plurality of supply voltage sources correlated with the clock frequency.
the at least one circuit comprises a processing device, the processing device operable to perform a plurality of functions, wherein each of at least two of the plurality of functions is performed at a predetermined clock frequency provided by the means for operating the clock source such that substantially the entire associated predetermined time period for each function is used to perform the function prior to the subsequent time period in which another of the plurality of functions is performed; and
a first supply voltage is applied to the processing device during performance of one of the at least two functions and a second supply voltage is applied to the processing device during performance of the other function, wherein the first and second supply voltages are applied based on the clock frequencies provided to the processing device.
11. The device of claim 1, wherein the at least one circuit is of a type selected from the group consisting of CMOS circuits, CML circuits, SOS circuits, SOI circuits, BICMOS circuits and NMOS circuits.
Power consumption of CMOS circuits consists generally of two power consumption factors, namely “dynamic” power consumption and static power consumption. Static power consumption is only due to current leakage as the quiescent current of such circuits is zero. Dynamic power consumption is the dominant factor of power consumption for CMOS technology. Dynamic power consumption is basically due to the current required to charge internal and load capacitances during switching, i.e., the charging and discharging of such capacitances. Dynamic power (P) is equal to: ½CV<HIL><SB>DD</SB></HIL><HIL><SP>2</SP></HIL>F, where C is nodal capacitance, F is the clock or switching frequency, and V<HIL><SB>DD </SB></HIL>is the supply voltage for the CMOS circuit. As can be seen from the formula for calculating dynamic power (P), such dynamic power consumption of CMOS circuits is proportional to the square of the supply voltage (V<HIL><SB>DD</SB></HIL>). In addition, dynamic power (P) is proportional to the switching or clock frequency (F).
In accordance with the formula for dynamic power consumption, it has been effective conventionally in CMOS integrated circuit designs to scale down the supply voltage for an entire device (e.g., hybrid) or integrated circuit (IC), i.e., operate the circuit at low supply voltages, to reduce power consumption for such designs. For example, in the MEDTRONIC SPECTRAX® product of circa 1979, IC circuitry was powered by one lithium iodine (as opposed to the two cells employed in the prior art). This reduced the supply voltage to 2.8 volts from 5.6 volts, thus reducing overhead current. Voltages required to be greater than 2.8 volts were generated by a voltage doubler, or alternatively by a charge pump (e.g., output pacing pulses). In the MEDTRONIC SYMBOLS® product of circa 1983, for example, logic circuitry was powered by a voltage regulator controlling the IC supply voltage to a “sum of thresholds” supply. This regulator provided a supply to the IC (i.e., V<HIL><SB>DD</SB></HIL>) of several hundred millivolts above the sum of the n-channel and p-channel thresholds of the CMOS transistors making up the IC. This regulator was self calibrating regarding manufacturing variations of the transistor thresholds.
Other devices reduced power consumption in other manners. For example, various device designs have shut-down analog blocks and/or shut-off clocks to logic blocks not being used at particular times, thereby reducing power. Microprocessor based devices have historically used a “burst clock” design to operate a microprocessor at a very high clock rate (e.g., generally 500-1000 Kilohertz (KHz)), for relatively short periods of time to gain the benefit of a “duty cycle” to reduce average current drain. A much lower frequency clock (e.g., generally 32 KHz) is used for other circuitry and/or the processor when not in the high clock rate mode, i.e., burst clock mode. Many known processor based implanted devices utilize the burst clock technique. For example, implanted devices available from Medtronic, Vitatron, Biotroniç, ELA, Intermedics, Pacesetters, InControl, Cordis, CPI, etc., utilize burst clock techniques. A few illustrative examples which describe the use of a burst clock are provided in U.S. Pat. No. 4,561,442 to Vollmann et al., entitled “Implantable Cardiac Pacer With Discontinuous Microprocessor Programmable Anti Tachycardia Mechanisms and Patient Data Telemetry,” issued Dec. 31, 1985; U.S. Pat. No. 5,022,395 to Russie, entitled “Implantable Cardiac Device With Dual Clock Control of Microprocessor,” issued Jun. 11, 1991; U.S. Pat. No. 5,388,578 to Yomtov et al., entitled “Improved Electrode System For Use With An Implantable Cardiac Patient Monitor,” issued Feb. 14, 1995; and U.S. Pat. No. 5,154,170 to Bennett et al., entitled “Optimization for Rate Responsive Cardiac Pacemaker,” issued Oct. 13, 1992.
<FGREF>FIG. 1</FGREF> illustrates graphically energy/delay versus supply voltage for CMOS circuits such as CMOS inverter 10 shown in <FGREF>FIG. 2</FGREF> for illustrative purposes. Inverter 10 is provided with a supply voltage, V<HIL><SB>DD</SB></HIL>, which is connected to the source of a PMOS field effect transistor (FET) 12. PMOS FET 12 has its drain connected to the drain of a NMOS FET 14 whose source is connected to ground. In this configuration, an input V<HIL><SB>i </SB></HIL>applied to both the gates of FETs 12, 14 is inverted to provide output V<HIL><SB>o</SB></HIL>. Simply stated, one clock cycle, or logic level change, is used to invert the input V<HIL><SB>i </SB></HIL>to V<HIL><SB>o</SB></HIL>.
As shown in <FGREF>FIG. 1</FGREF>, the circuit logic delay increases drastically as the supply voltage is reduced to near one volt, as represented by delay line 16 and energy/delay line 18. As such, reducing of the supply voltage (V<HIL><SB>DD</SB></HIL>) continuously to lower levels is impractical because of the need for higher supply voltages when higher frequency operation is required. For example, generally CMOS logic circuits must periodically provide functionality at a higher frequency, e.g., burst clock frequency. However, as the supply voltage (V<HIL><SB>DD</SB></HIL>) is decreased, such energy consumption is reduced by the square of the supply voltage (V<HIL><SB>DD</SB></HIL>) as is shown by energy consumption line 20. Therefore, speed requires a higher supply voltage (V<HIL><SB>DD</SB></HIL>) which is in direct conflict with low power consumption.
Other problems are also evident when lower supply voltages (V<HIL><SB>DD</SB></HIL>) are used for CMOS circuit designs. When a lower supply voltage is selected, static leakage current losses may arise, particularly at lower frequencies, due to increased static leakage current losses.
<TABLE-US><TABLE-CALS><table><tgroup><colspec></colspec><colspec></colspec><colspec></colspec><colspec></colspec><thead><row><entry></entry><entry>TABLE 1</entry></row><row><entry></entry><entry></entry></row><row><entry></entry><entry> Patent No.</entry><entry>Inventor</entry><entry>Issue Date</entry></row><row><entry></entry><entry></entry></row></thead><tbody><row><entry></entry><entry>4,031,899</entry><entry>Renirie</entry><entry>June 28, 1977</entry></row><row><entry></entry><entry>4,460,835</entry><entry>Masuoka</entry><entry>July 17, 1984</entry></row><row><entry></entry><entry>4,561,442</entry><entry>Vollmann et al.</entry><entry>December 31, 1985</entry></row><row><entry></entry><entry>4,791,318</entry><entry>Lewis et al.</entry><entry>December 13, 1988</entry></row><row><entry></entry><entry>5,022,395</entry><entry>Russie</entry><entry>June 11, 1991</entry></row><row><entry></entry><entry>5,154,170</entry><entry>Bennett et al.</entry><entry>October 13, 1992</entry></row><row><entry></entry><entry>5,185,535</entry><entry>Farb et al.</entry><entry>February 9, 1993</entry></row><row><entry></entry><entry>5,388,578</entry><entry>Yomtov et al.</entry><entry>February 14, 1995</entry></row><row><entry></entry><entry>5,610,083</entry><entry>Chan et al.</entry><entry>March 11, 1997</entry></row><row><entry></entry><entry></entry></row></tbody></tgroup></table></TABLE-CALS></TABLE-US>
In comparison to known techniques for reducing power consumption in circuit designs, various embodiments of the present invention may provide one or more of the following advantages: reduced power consumption through the use of a lower voltage supply (V<HIL><SB>DD</SB></HIL>); reduced power consumption by decreased clock frequency for circuit designs; increased longevity of circuits, particularly implantable device circuitry; provide a potential reduction in product size; minimize static leakage current losses, i.e., static power consumption; provide multi-processor designs, DSP designs, and high performance processing designs with additional features/function opportunities due to the ability to reduce power with respect to other “required” features and functions; and provide for substantial reduction in current drain.
<FGREF>FIG. 1</FGREF> is a graphical illustration showing energy/delay versus supply voltage for CMOS circuit operation.
<FGREF>FIG. 2</FGREF> shows a prior art CMOS inverter which is used as a building block in many CMOS circuit designs.
<FGREF>FIG. 3</FGREF> is block diagram of a just-in-time clocking system according to the present invention.
<FGREF>FIGS. 4A-4C</FGREF> show timing illustrations for use in describing the just-in-time clocking system of FIG. 3.
<FGREF>FIG. 5</FGREF> is a block diagram illustration of a multiple supply voltage system according to the present invention.
<FGREF>FIG. 6</FGREF> is a block diagram illustrating a variable supply voltage system according to the present invention.
<FGREF>FIG. 7</FGREF> is a block diagram of clock controlled processing circuitry according to the present invention.
<FGREF>FIG. 8</FGREF> is a diagram illustrating an implantable medical device in a body.
<FGREF>FIG. 9</FGREF> is a block diagram of the circuitry of a pacemaker for use in illustrating one or more embodiments of the present invention.
<FGREF>FIG. 10</FGREF> is a schematic block diagram of an implantable pacemaker/cardioverter/defibrillator (PCD) for use in illustrating one or more embodiments of the present invention.
<FGREF>FIG. 11</FGREF> is a schematic block diagram illustrating a variable clock/variable supply voltage digital signal processing system according to the present invention.
The present invention is first generally described with reference to <FGREF>FIGS. 3 through 7</FGREF>. Thereafter, the present invention is described with reference to illustrative configurations of implantable medical devices shown in <FGREF>FIGS. 8 through 11</FGREF>.
<FGREF>FIG. 3</FGREF> shows a general block diagram of just-in-time clock system 30. Just-in-time clock system 30 includes integrated circuit 32 and clock source 34. Integrated circuit 32 includes a plurality of circuits C1-Cn. Each circuit when operable is capable of performing one or more circuit functions. A function is defined as any operation perform on one or more inputs in a plurality of cycles resulting in an output. Generally, the functions performed by the various circuits C1-Cn are performed in a predetermined number of clock cycles. Clock source 34 is operable for providing clock signals at a plurality of clock frequencies generally shown as clock1-clockn.
Just-in time controllable clock operation of the just-in-time clocking system 30 of <FGREF>FIG. 3</FGREF> shall be described with reference to <FGREF>FIGS. 4A-4C</FGREF>. As shown in <FGREF>FIG. 4A</FGREF>, time period (x) represents the time period in which a circuit, e.g., one of circuits C1-Cn, is required to complete one or more functions. The same time period (x) is shown in FIG. 4B. The time period x may be equated to any number of different time periods. For example, the time period may be the amount of time a processing circuit has to perform a particular detection function due to the need for a detection output by a certain point in time, may be a time period required to complete a particular function by a certain logic circuit so as to provide a timely output to a digital signal processing circuit, may be a time period to complete a firmware (software) routine, etc. Further, for example, the time period x may correspond to a cardiac cycle or a part thereof.
As shown in <FGREF>FIG. 4B</FGREF>, according to conventional processing, circuit functions were typically performed at a burst cycle frequency and, as such, the function performed required a time period 60. Therefore, only a small amount of time (i.e., time period 60) of the entire time period x was used to perform the one or more functions requiring n cycles of time to complete. In such a case, conventionally, such burst clocks were at a substantially high clock rate, e.g., 500-1000 KHz, for such short periods of time to gain the benefit of a “duty cycle” to reduce average current drain. However, such high clock rates may not be required for carrying out such functions, or all functions.
With just-in-time clocking according to the present invention, as shown in <FGREF>FIG. 4A</FGREF>, substantially the entire time period x is used to perform the one or more functions which are completed in n cycles. In other words, the clock frequency, e.g., one of clock1-clockn, for the circuit performing the one or more functions during the time period x is set such that the one or more functions are completed in the maximum time available for performing such functions, i.e., the clock frequency is at its lowest possible value. In other words, a lower frequency clock is used such that the one or more functions are performed just-in-time for other circuit or routine functionality to be performed. In such a just-in-time manner, the clock frequency used to control the performance of such functions by the particular CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS type of circuitry is lowered resulting in reduced power consumption by the circuitry. That is, according to the calculations of dynamic power, the lower frequency results in proportional power reduction. With the lowering of the clock frequency, the integrated circuit 32 including the various circuits C1-Cn can be designed to operate at a lower frequency, e.g., as opposed to burst frequency, and also at various other frequencies depending upon need.
<FGREF>FIG. 4C</FGREF> shows an illustrative timing example for processing circuitry which performs multiple functions. For example, the cardiac cycle of a patient is represented in <FGREF>FIG. 4C</FGREF> as time period x. During time period 71, i.e., during a QRS complex of the cardiac cycle, high speed processing is performed at a high clock frequency relative to a lower clock frequency used to control operation of the processing circuitry during time period y. During the time period y, when the processing circuitry is operated at a lower clock frequency, such lower clock frequency may be set such that the functions performed during z cycles are performed in substantially the entire maximum time period available for such processing, i.e., time period y. Once again, a small remainder time period 75 of the cardiac cycle time period x may exist. Such time period may be, for example, in the range of about 1.0 millisecond to about 10.0 milliseconds when the cardiac cycle is in the range of about 400 milliseconds to about 1200 milliseconds.
<FGREF>FIG. 5</FGREF> shows a general block diagram of a multiple supply voltage system 100 wherein one or more supply voltages are available and tailored for application to various circuits in an IC. The multiple supply voltage system 100 includes integrated circuit 102 and supply voltage source 106. Integrated circuit 102 includes circuits C1-Cn. Supply voltage source 106 is operable for providing a plurality of supply voltages V1-Vn. Each supply voltage from supply voltage source 106 is tailored to be applied to one or more circuits of circuits C1-Cn. As illustrated, supply voltage V1 is applied to circuit C1, supply voltage V2 is applied to circuit C2 and C3, and so forth.
The tailoring of the supply voltages V1-Vn to the particular circuits C1-Cn depends on the frequency at which the circuits C1-Cn are required to be operated. For example, and as previously described, the logic delay of such CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS circuits C1-Cn increases drastically as the supply voltage is reduced to near 1 volt. If such logic delay is tolerable, the supply voltage provided to a particular circuit will drastically reduce the power consumption for that particular circuit as the energy is reduced in proportion to the square of the supply voltage (V<HIL><SB>DD</SB></HIL>). However, if such logic delay is not tolerable, for example, if the logic circuit performs a function that must be completed within a particular period of time, the reduction of the supply voltage (V<HIL><SB>DD</SB></HIL>) applied to such a circuit will be limited depending upon the acceptable logic delay. However, the supply voltage V<HIL><SB>DD </SB></HIL>for any particular circuit can be reduced as low as possible yet meet adequate speed requirements.
Conventionally, supply voltage (V<HIL><SB>DD</SB></HIL>) is generally in the range of about 3 volts to about 6 volts. Preferably, in accordance with the present invention, the supply voltages V1-Vn are in the range of about 1 volt to about 3 volts dependent upon the CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS type of technology used.
With reduction in supply voltage (V<HIL><SB>DD</SB></HIL>), threshold voltage (V<HIL><SB>T</SB></HIL>) for the circuits is also reduced. For example, with supply voltages in the range of about 3 to about 6 volts, the threshold voltage for CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS types of devices is generally in the range of about 0.8 volts to about 1.0 volt. Preferably, in implantable medical devices, lithium chemistries are utilized for implantable batteries. Such lithium chemistries are generally in the range of about 2.8 volts to about 3.3 volts and generally the CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS circuitry has an associated threshold voltage of about 0.75. By reducing the supply voltages below 2.8, the voltage thresholds for CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS devices may be decreased to as low as about 0.2 volts to about 0.3 volts.
Therefore, multiple supply voltage system 100 may further optionally include back gate bias source 130 for providing back gate bias voltages BV1-BVn to circuits C1-Cn of integrated circuit 102. Generally, the back gate bias voltages BV1-BVn are dependent upon the supply voltage V1-Vn applied to the circuits C1-Cn to adjust the threshold voltages for devices of circuits C1-Cn. For example, the threshold voltage (V<HIL><SB>T</SB></HIL>) for the CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS devices of the circuit may be at a lower value by providing a back gate bias voltage to the particular circuits supplied with the lower supply voltage. Further, for example, if circuit C1 is supplied with a lower supply voltage V1, then a back gate bias voltage BV1 may optionally be applied to circuit C1 to adjust the threshold voltage (V<HIL><SB>T</SB></HIL>) for the CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS devices to a higher threshold voltage (V<HIL><SB>T</SB></HIL>) value. In this manner, static leakage current losses can be minimized because the equivalent higher threshold voltage has been restored. Further, a broader range of supply voltages is possible because the back gate adjustment allows a tailoring of the threshold allowing high/low speed operation and eliminating the static current drain leakage.
<FGREF>FIG. 6</FGREF> shows a general block diagram of a variable supply voltage/variable clock system 150 according to the present invention. The system 150 includes integrated circuit 152, clock source 156, supply voltage source 154, and clock/supply voltage interface 155. Supply voltage source 154 is operable for providing a plurality of supply voltages V1-Vn to a plurality of circuits C1-Cn of integrated circuit 152. Further, the clock source 156 of system 150 is operable for providing clock signals at a plurality of frequencies, clock1-clockn. Circuits C1-Cn are of a similar nature to those described with reference to <FGREF>FIG. 3</FGREF>, the clock source 156 is similar to the clock source 34 as described with reference to <FGREF>FIG. 3</FGREF>, and the supply voltage source 154 is similar to the supply voltage source 106 as described with reference to FIG. 5. However, in the variable supply voltage/variable clock system 150, a clock/voltage interface 155 is used to adjust the supply voltages V1-Vn applied to the circuits C1-Cn “on the fly” as required by specific timing functions required by the circuits C1-Cn.
<FGREF>FIG. 7</FGREF> shows a general block diagram of a clock controlled processing system 200 according to the present invention. The clock controlled processing system 200 includes processor 202 (e.g., a CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS type of microprocessor or CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS type of digital signal processor), clock source 204, supply voltage source 206, voltage regulator 212, regulator interface 210, clock control 208, and optional back gate bias source 214. In a manner similar to that described with reference to <FGREF>FIG. 6</FGREF>, the supply voltage 206 applied to processor 202 is changed “on the fly” as required by specific circuit timing requirements.
<FGREF>FIG. 4C</FGREF> illustrates one embodiment of the clock control processing system 200. As shown therein, during the overall cardiac cycle of predetermined time period x, a high frequency is used for controlling operation of processor 202 during time period 71 of the cardiac cycle time period x, e.g., during processing of the QRS complex. Thereafter, a lower clock frequency is used during time period y for controlling operation of processor 202 to perform any of a number of other different functions, such as cardiac event/EMI differentiation functions. During operation of the processor 202 at the higher clock frequency during time period 71, a higher supply voltage from supply voltage source 206 is applied to the CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS devices of processor 202. Likewise, during operation of the processor 202 at the relatively lower clock frequency, a lower supply voltage from supply voltage source 206 is applied to the CMOS or other types of devices of processor 202 during time period y of the overall cardiac cycle time period x.
Further, as shown in <FGREF>FIG. 7</FGREF>, an optional back gate bias 214 may be used to dynamically adjust the threshold voltage (V<HIL><SB>T</SB></HIL>) of CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS devices of processor 202 as a function of the clock frequency applied to processor 202 by clock source 204. The regulator interface 210 detects the clock frequency used to control operation of processor 202 and controls the voltage level of back gate bias 214 to be applied to the CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS devices of processor 202. The dynamic adjustment of the threshold voltage may be implemented as an adjustable or selectable voltage source utilizing, for example, a charge pump and a regulator. The back gate voltage and the “normal” gate voltage provide a gate bias or voltage to the transistor. By adjusting the back gate voltage, the “apparent” voltage is increased with a resultant reduction in leakage current.
<FGREF>FIG. 8</FGREF> is a simplified diagram of implantable medical device 260 for which the present invention is useful. Implantable device 260 is implanted in a body 250 near a human heart 264. Implantable medical device 260 is connected to heart 264 by leads 262. In the case where device 260 is a pacemaker, leads 262 are pacing and sensing leads to sense electrical signals attendant to the depolarization and repolarization of the heart 264 and provide pacing pulses in the vicinity of the distal ends thereof. Implantable medical device 260 may be any implantable cardiac pacemaker such as those disclosed in U.S. Pat. No. 5,158,078 to Bennett et al., U.S. Pat. No. 5,312,453 to Shelton et al., or U.S. Pat. No. 5,144,949 to Olson, all hereby incorporated herein by reference in their respective entireties and which can all be modified according to the present invention.
<FGREF>FIG. 9</FGREF> shows a block diagram illustrating the components of a pacemaker 300 in accordance with one embodiment of the present invention. Pacemaker 300 has a microprocessor-based architecture. However, the illustrative pacemaker 300 of <FGREF>FIG. 9</FGREF> is only one exemplary embodiment of such devices and it will be understood that it could be implemented in any logic-based, custom integrated circuit architecture, if desired, as can any microprocessor-based system.
In the illustrative embodiment of <FGREF>FIG. 9</FGREF>, pacemaker 300 is most preferably programmable by means of an external programming unit (not shown in the figures). One such programmer suitable for the purposes of the present invention is the commercially available Medtronic Model 9790 programmer. The programmer is a microprocessor-based device which provides a series of encoded signals to pacemaker 300 by means of a programming head which transmits radio frequency (RF) encoded signals to antenna 334 of pacemaker 300 according to a telemetry system such as, for example, that described in U.S. Pat. No. 5,127,404 to Wyborny et al., the disclosure of which is hereby incorporated by reference herein in its entirety. It is to be understood, however, that any programming methodology may be employed so long as the desired information is transmitted to and from the pacemaker.
Pacemaker 300 illustratively shown in <FGREF>FIG. 9</FGREF> is electrically coupled to heart 264 by leads 302. Lead 302a including electrode 306 is coupled to a node 310 in the circuitry of pacemaker 300 through input capacitor 308. Lead 302b is coupled to pressure circuitry 354 of input/output circuit 312 to provide a pressure signal from sensor 309 to the circuit 354. The pressure signal is used to ascertain metabolic requirements and/or cardiac output of a patient. Further, activity sensor 351, such as a piezoceramic accelerometer, provides a sensor output to activity circuit 352 of input/output circuit 312. The sensor output varies as a function of a measured parameter that relates to metabolic requirements of a patient. Input/output circuit 312 contains circuits for interfacing to heart 264, to activity sensor 351, to antenna 334, to pressure sensor 309 and circuits for application of stimulating pulses to heart 264 to control its rate as a function thereof under control of software-implemented algorithms in microcomputer unit 314.
According to the present invention, the circuits shown in <FGREF>FIG. 9</FGREF> are powered by an appropriate implantable battery supply voltage source 301 (e.g., a voltage source generally shown in FIGS. 1-7). For the sake of clarity, the coupling of supply voltage source 301 to various circuits of pacemaker 300 is not shown in the figures. Further, the circuits operable under control of a clock signal shown in <FGREF>FIG. 9</FGREF> are operated according to the present invention under clock source 338. For the sake of clarity, the coupling of such clock signals from the clock source 338 (e.g., a clock source generally shown in <FGREF>FIGS. 1-7</FGREF>) to such CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS circuits of pacemaker 300 is not shown in the Figures.
V<HIL><SB>REF </SB></HIL>and bias circuit 340 generates a stable voltage reference and bias currents for circuits of input/output circuit 312. Analog-to-digital converter (ADC) and multiplexer unit 342 digitize analog signals and voltages to provide “real-time” telemetry intracardiac signals and battery end-of-life (EOL) replacement function. A power on reset circuit 341 functions as a means to reset circuitry.
Digital controller/timer circuit 332 is preferably coupled to sense circuitry 345 and to electrogram (EGM) amplifier 348 for receiving amplified and processed signals sensed by electrode 306 disposed on lead 302a. Such signals are representative of the electrical activity of the patient's heart 264. Sense amplifier 346 of circuitry 345 amplifies sensed electrocardiac signals and provides an amplified signal to peak sense and threshold measurement circuitry 347. Circuit 347 in turn provides an indication of peak sensed voltages and measured sense amplifier threshold voltages on path 357 to digital controller/timer circuit 332. An amplified sense amplifier signal is also provided to comparator/threshold detector 40. Sense amplifier 332 may correspond to that disclosed in U.S. Pat. No. 4,379,459 to Stein, which is hereby incorporated by reference herein in its entirety.
Output pulse generator and amplifier 350 provides pacing stimuli to heart 264 through coupling capacitor 305 and electrode 306 in response to a pacing trigger signal provided by digital controller/timer circuit 332. Output amplifier 350 may correspond generally to the output amplifier disclosed in U.S. Pat. No. 4,476,868 to Thompson, also incorporated by reference herein in its entirety. The circuits of <FGREF>FIG. 9</FGREF> may be CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS circuitry capable of operating according to the present invention, and include processor 320, digital controller timer circuit 332, RAM 324, ROM 326, RAM/ROM unit 328 and ADC/Mux 342.
<FGREF>FIG. 10</FGREF> is a functional schematic diagram from U.S. Pat. No. 5,447,519 to Peterson, which shows an implantable PCD 400 in which the present invention may usefully be practiced. This diagram is an illustration to be taken only as an exemplary type of device in which the invention may be embodied, and not as limiting to the scope of the present invention. Other implantable medical devices as previously described having functional organizations wherein the present invention may be useful may also be modified in accordance with the present invention. For example, the present invention is also believed to be useful in conjunction with implantable PCDs as disclosed in prior U.S. Pat. No. 4,548,209 to Wielders et al.; U.S. Pat. No. 4,693,253 to Adams et al.; U.S. Pat. No. 4,830,006 to Haluska et al.; and U.S. Pat. No. 4,949,730 to Pless et al.; all of which are incorporated herein by reference in their entireties.
According to the present invention, the circuits shown in <FGREF>FIG. 10</FGREF> are powered by appropriate implantable battery supply voltage source 490 (e.g., a voltage source generally shown in FIGS. 1-7). For the sake of clarity, the coupling of supply voltage source 490 to various circuits of PCD 400 is not shown in the figures. Further, the circuits operable under control of a clock signal shown in <FGREF>FIG. 10</FGREF> are operated according to the present invention under clock source 491. For the sake of clarity, the coupling of such clock signals from the clock source 491 (e.g., a clock source generally shown in <FGREF>FIGS. 1-7</FGREF>) to such CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS circuits of PCD 400 is not shown in the Figures.
Other portions of PCD 400 of <FGREF>FIG. 10</FGREF> are dedicated to the provision of cardiac pacing, cardioversion, and defibrillation therapies. With regard to cardiac pacing, the pacer timing/control circuit 420 includes programmable digital counters which control the basic timing intervals associated with cardiac pacing, including the pacing escape intervals, the refractory periods during which sensed R-waves are ineffective to restart timing of escape intervals, etc. The durations of such intervals are typically determined by processor 424 and communicated to pacer timer/control circuit 420 via address/data bus 440. Further, under control of processor 424, pacer timing/control circuit also determines the amplitude of such cardiac pacing pulses and pace out circuit 421 provides such pulses to the heart.
The components of PCD 400 of <FGREF>FIG. 10</FGREF> may be CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS circuitry capable of operation according to the present invention include processor 424, control circuits 420 and 454, RAM 426, DMA 428, ADC 430, and multiplexer 432.
According to the present invention, pacemaker 300 illustrated in FIG. 9 and PCD 400 illustrated in <FGREF>FIG. 10</FGREF> may both be implemented in accordance with the generalized embodiments previously described herein with reference to <FGREF>FIGS. 1-7</FGREF>. First, for example, with respect to pacemaker 300 of <FGREF>FIG. 9</FGREF>, the voltage supply source 301 of pacemaker 300 may be implemented in a manner previously described with reference to <FGREF>FIGS. 1-7</FGREF> and, likewise, clock source 338 of pacemaker 300 may be implemented in such a manner as described with reference to <FGREF>FIGS. 1-7</FGREF>. Likewise, clock source 491 of PCD 400 of FIG. 10 and the voltage supply source 490 of PCD 400 of <FGREF>FIG. 10</FGREF> may be implemented in accordance with the generalized embodiments previously described herein with reference to <FGREF>FIGS. 1-7</FGREF>.
Additionally, and in respect of <FGREF>FIG. 10</FGREF>, A/D converter circuit 430, cardioverter/defibrillator control circuit 454, and various other circuits such as RAM 426, DMA 428, and multiplexer 432 may also be operated at different clock frequencies available from clock source 491 and at different corresponding supply voltages available from supply voltage source 490. Further, a telemetry circuit (not shown) may be used with PCD 400 of FIG. 10 and may also be operated at different clock frequencies available from clock source 491 and at different corresponding supply voltages available from supply voltage source 490. In addition, processor 424 may be operated at different clock speeds depending upon the function being performed by the processor 424, such as described with reference to <FGREF>FIG. 7</FGREF> herein. For example, morphology detection sensing at typical physiologic rates (i.e., 50 to 150 BPM) may be performed at a first clock frequency and corresponding supply voltage while arrahythmia detection may be performed at a different clock frequency and corresponding supply voltage.
<FGREF>FIG. 11</FGREF> shows a variable clock/variable supply voltage digital signal processing system 500 which may be used in conjunction with and/or in the alternative to certain circuits shown in <FGREF>FIGS. 9 and 10</FGREF>. For example, the digital signal processing system 500 according to <FGREF>FIG. 11</FGREF> may be used in place of activity circuit 352, pressure circuit 354, sense amplifier circuit 346 (for P-wave, R-wave- and/or T-wave sense amplifiers), and further may be provided with additional functionality with use of a pseudo EKG signal 502. Generally, any number of analog signals 499, for example, such as pseudo EKG signals 502, activity sensor signal 503 and pressure and onset sensor signal 504, are provided through respective amplifiers 505-507. The amplified signals are presented to multiplexer 510 which provides them to analog to digital converter (ADC) 516 in a cycled fashion. The signals 502-504 can be cycled at different rates by cycling through the outputs of the several amplifiers/preamplifiers 505-507 such as described in pending U.S. patent application Ser. No. 08/801,335, entitled “Method for Compressing Digitized Cardiac Signals Combining Lossless Compression and Non-linear Sampling,” which describes variable compression via ADC sampling and which is incorporated herein by reference in its entirety. The ADC may also have variable conversion rates as described in U.S. Pat. No. 5,263,486 and U.S. Pat. No. 5,312,446 which are also incorporated herein by reference in their entireties.
For example, only during a QRS complex will the waveform analysis processor 520 be in a high speeds processing mode at a relatively high frequency, while during the remainder of the cardiac cycle the processor 520 may be “idling along” at a much lower clock frequency. Such a processing cycle has been previously described with reference to FIG. 4C. In addition to the lower clock speed utilized for different portions of the cardiac cycle, one skilled in the art will recognize that in accordance with the other aspects of the present invention, as the speed is reduced, the supply voltage level (V<HIL><SB>DD</SB></HIL>) may also be reduced accordingly. Thus, reduced power consumption is attained as previously described.
US 20020173825A1
607/1, 607/2, 607/4, 607/5, 607/9, 607/16
US 6,023,641 A
Power Consumption Reduction In Medical Devices Employing Just In Time Clock
Power Consumption Reduction In Medical Devices Employing Just In Time Voltage Control