Source: http://www.google.com/patents/US8037474?dq=Xerox+%2B+%22centroid
Timestamp: 2014-09-02 09:54:03
Document Index: 177439727

Matched Legal Cases: ['application No. 06254919', 'Application No. 2008', 'Application No. 2008', 'application No. 2006', 'application No. 2006', 'application No. 200610142304', 'application No. 200610142305']

Patent US8037474 - Task manager with stored task definition having pointer to a memory address ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsCell processor task management in a cell processor having a main memory, one or more power processor units (PPU) and one or more synergistic processing units (SPU), each SPU having a processor and a local memory is described. An SPU task manager (STM) running on one or more of the SPUs reads one or more...http://www.google.com/patents/US8037474?utm_source=gb-gplus-sharePatent US8037474 - Task manager with stored task definition having pointer to a memory address containing required code data related to the task for executionAdvanced Patent SearchPublication numberUS8037474 B2Publication typeGrantApplication numberUS 11/238,087Publication dateOct 11, 2011Filing dateSep 27, 2005Priority dateSep 27, 2005Also published asEP1934739A1, EP2290543A2, EP2290543A3, US20070074207, WO2007038457A1Publication number11238087, 238087, US 8037474 B2, US 8037474B2, US-B2-8037474, US8037474 B2, US8037474B2InventorsJohn P. Bates, Payton R. White, Richard B. Stenson, Howard Berkey, Atilla Vass, Mark Cerny, John MorganOriginal AssigneeSony Computer Entertainment Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (75), Non-Patent Citations (62), Referenced by (1), Classifications (10), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetTask manager with stored task definition having pointer to a memory address containing required code data related to the task for executionUS 8037474 B2Abstract Cell processor task management in a cell processor having a main memory, one or more power processor units (PPU) and one or more synergistic processing units (SPU), each SPU having a processor and a local memory is described. An SPU task manager (STM) running on one or more of the SPUs reads one or more task definitions stored in the main memory into the local memory of a selected SPU. Based on information contained in the task definitions the SPU loads code and/or data related to the task definitions from the main memory into the local memory associated with the selected SPU. The selected SPU then performs one or more tasks using the code and/or data.
This application is also related to commonly-assigned U.S. patent application Ser. No. 11/238,085 entitled �METHOD AND SYSTEM FOR PERFORMING MEMORY COPY FUNCTION ON A CELL PROCESSOR� to Antoine Labour, John P. Bates and Richard B. Stenson, which is filed the same day as the present application, the entire disclosures of which are incorporated herein by reference.
Each SPU 104 includes a local memory 110. Code and data obtained from the main memory 106 can be loaded into the local memory 110 so that the SPU 104 can process tasks. As shown in the inset, a software manager referred to herein as an SPU Task Manager (STM) 112 resides in the local memory 110 of each SPU 104. Preferably, the STM 112 takes up only a small fraction of the total memory space available in each local memory 110. The heart of SPMM 112 is referred to as an �STM Kernel�, which typically takes up about 16 KB resident on each SPU. For a 256K local storage, this represents about 6% SPU Local Store usage.
By way of example, policy modules and work queues may be associated as follows. As shown in the lower inset in FIG. 1, the main memory 106 may contain a task set 114 having a set of task queues 116. Each task queue 116 includes one or more task queue elements, which include pointers to one or more task definitions 118. The PPU 102 can add new task queues to the task set 114 but has little other involvement with the management of the task set 114. Tasks may be added to the task queue 116 from the application running on the PPU 102. An operating system mutex, such as a Lv2OS mutex may be used for PPU thread contention. In addition the SPU 104 can also schedule new tasks. Each time a task is added to a task queue, it will execute once without interruption. The PPU 102 typically does not interrupt a task while it is being processed. The PPU application may poll the task queue 116 for completion of tasks. For example, when a �checked� task completes, the STM kernel 112 set a bit in an atomic. The bit can be polled from the PPU 102 using the API.
When the task queues 116 are empty, the SPU kernel on each SPU 104 waits on an atomic reservation lost event. The SPUs 104 notify the atomic mutex 117 of completion of �checked� tasks. By way of example, the atomic mutex may include 4 bytes of atomic used for a lock state, 2 bytes used for a completed task count and 122 bytes containing states for up to 488 tasks. The 122 bytes may include two bits per task: 1 for reservation, 1 for the state (e.g., waiting, processing or completed). Notification should be used sparingly. STM tasks can optionally notify a waiting PPU thread using the SPU Threads event queue. The latency for this technique (the time it takes from when the SPU sends the event to when the PPU thread is notified) however, can be significantly longer, e.g., about 100 times longer, than atomic notification.
When the STM Kernel 112 needs more tasks, it DMAs a number of Task Definitions from the front of the task queue. The task queues 116 may be circular, and can dynamically grow when tasks are added from the PPU 102 or SPU 104. In a circular queue, tasks are added to the end of the queue and taken from the beginning The tasks fill up the space available and then �wrap around� to occupy memory space that becomes available as tasks are removed from the end of the queue. The task queue may use an atomic mutex 117 to synchronize access to each queue. By way of example the atomic mutex may be a 128-byte atomic mutex. Pointers and indices for the task queue 116 can be stored in this atomic. The atomic mutex 117 generally includes one or more bits that indicate whether access to the task queue 116 is locked or not. The mutex 117 may also include one or more bytes of data that provide information about what other tasks in the task queue are in progress and/or the location of those tasks. The mutex 117 may also include one or more bytes for a counter that can be incremented or decremented to notify other SPU 104 or the PPU 102 which tasks in the task queue 116 have been taken.
Type-1 programs are higher performance use programs, though they tend to have more restrictions. An example of a Type-1 program 324 that can be cached is a MEM COPY program. This program takes advantage of the fact that memory transfers can be handled much faster by DMA using the SPU 104 than by the PPU 102. The MEM COPY takes advantage of this by using an available SPU to transfer data from one location in the main memory 106 to another location. Such SPU-based main memory management is particularly advantageous, e.g., where data needs to be aligned before DMA transfer from the main memory to an SPU or elsewhere. Examples of MEM COPY programs are described in commonly-assigned U.S. patent application Ser. No. 11/238,085 entitled �METHOD AND SYSTEM FOR PERFORMING MEMORY COPY FUNCTION ON A CELL PROCESSOR� to Antoine Labour, John P. Bates and Richard B. Stenson, which is filed the same day as the present application, the entire disclosures of which have been incorporated herein by reference.
Type-2 programs are characterized by the fact that they may use non-position independent code (non-PIC) and may dynamically allocate local store space at SPU runtime. Typically, only one Type-2 program is loaded on one SPU at a time, although exceptions to this feature are within the scope of embodiments of the present invention. As shown in FIG. 4D for a Type-2 program, the local store 310 includes an area of memory that is dynamically allocated by the program at runtime. As shown in FIG. 4E, this area may include Type-2 SPU program code 325 and context data 326. Furthermore, as shown in FIG. 4F the dynamically allocated area of the local store 310 may also contain malloc data 327. The malloc function is used to dynamically allocate memory space in the programming language known as C. The malloc function accesses this block of memory via a pointer. When the memory is no longer needed, the pointer is passed to �free� and the memory can be reused by the system. Type-2 programs determine how the leftover local store space is allocated among globals, stack, and/or malloc. Furthermore, unlike the Type-1 program the size of the stack 311 for a Type-2 program is variable. Type-2 programs are particularly suitable for situations where it is desired to load the program code on the SPU and then select tasks that match the program code. The STM kernel 312 can load another program if it looks far ahead in the task queue and finds nothing that matches.
FIG. 4G depicts a memory map of local storage 310 for an SPU in which the STM kernel 312 is implemented as a policy under SPMM 313. The STM kernel 312 manages an SPU program 324 and data 326 for one or more tasks. Running the STM kernel as a policy under SPMM allows flexibility where other policies, such as SPURS or SPU threads or developer-designed custom policies are also to be implemented. SPMM is described in detail in commonly assigned U.S. patent application Ser. No. 11/238,077 entitled �CELL PROCESSOR METHODS AND APPARATUS� to John P. Bates, Payton R. White and Attila Vass, which is filed the same day as the present application, the entire disclosures of which are incorporated herein by reference.
High performance processing can be achieved with embodiments that take advantage of code and/or data affinity. As used herein, �code affinity� refers to a situation where an SPU already has loaded in its associated local store the program code associated with a particular task. Where an SPU has code affinity with a particular task, it only has to DMA transfer the requisite data for the task. Similarly, �data affinity�refers to a situation where an SPU already has loaded in its associated local store the data associated with a particular task. Where an SPU has data affinity with a particular task it need only DMA transfer the requisite code. Since it is more efficient to process a task where SPU Kernels choose tasks that match their current SPU code. This reduces the occurrence of code switching. Please note that it is possible to cache several Type-1 programs in local store associated with an SPU and access them as needed. In such a case, code affinity is less important.
As used herein, the term I/O generally refers to any program, operation or device that transfers data to or from the system 1100 and to or from a peripheral device. Every transfer is an output from one device and an input into another. Peripheral devices include input-only devices, such as keyboards and mouses, output-only devices, such as printers as well as devices such as a writable CD-ROM that can act as both an input and an output device. The term �peripheral device� includes external devices, such as a mouse, keyboard, printer, monitor, external Zip drive or scanner as well as internal devices, such as a CD-ROM drive, CD-R drive or internal modem or other peripheral such as a flash memory reader/writer, hard drive.
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