Source: https://patents.google.com/patent/US20030098505?oq=5636223
Timestamp: 2018-03-21 00:00:04
Document Index: 303069000

Matched Legal Cases: ['art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 39', 'art 43', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 61', 'art 81', 'art 81', 'art 81']

US20030098505A1 - Semiconductor module - Google Patents
US20030098505A1
US20030098505A1 US10156975 US15697502A US20030098505A1 US 20030098505 A1 US20030098505 A1 US 20030098505A1 US 10156975 US10156975 US 10156975 US 15697502 A US15697502 A US 15697502A US 20030098505 A1 US20030098505 A1 US 20030098505A1
US10156975
US6870260B2 (en )
[0006]FIG. 1 illustrates a structure of a semiconductor module in accordance with a first exemplary embodiment of the present invention.
[0007]FIG. 2 shows an example of wiring patterns on a wiring part of the semiconductor module in accordance with the present invention.
[0008]FIG. 3(a) shows laser trimming of a capacitor made of wiring patterns.
[0009]FIG. 3(b) shows laser trimming of an inductor made of a wiring pattern.
[0010]FIG. 4 is a sectional view of the wiring part of the semiconductor module of the present invention.
[0011]FIG. 5 is a partially enlarged sectional view of the wiring part of the semiconductor module of the present invention.
[0012]FIG. 6 illustrates a structure of a semiconductor module in accordance with a second exemplary embodiment of the present invention.
[0013]FIG. 7 illustrates a structure of a semiconductor module in accordance with a third exemplary embodiment of the present invention.
[0014]FIG. 8 is a sectional view of a conventional electronic device.
[0017]FIG. 1 illustrates a structure of a semiconductor module in accordance with the first embodiment of the present invention. Semiconductor device 11 has terminals 16, 17, 18, 21, 22 and 23 led out on one side 11 a thereof. Provided on side 11 a of the semiconductor device is wiring part 12 substantially identical with semiconductor device 11 in size. Wiring part 12 has input/output terminals 19, 20, 24 and 25 for connection to external circuits (not shown). Provided on wiring part 12 are circuits 13, 14, and 15. Circuit 13 connects terminals 16 and 17 on the semiconductor device. Circuit 14 connects terminal 18 on semiconductor device 11 and input/output terminal 19. Circuit 15 connects terminal 21 on semiconductor device 11 and input/output terminal 20. Terminals 22 and 23 connect directly to input/output terminals 24 and 25, respectively. Input/output terminals 19, 20, 24, and 25 are solder bumps.
1) applying cream solder to the circuit board;
2) mounting the semiconductor module in a predetermined position on the circuit board; and
3) heating the semiconductor module and the circuit board in a reflow oven to melt the solder bumps and join the semiconductor module to the circuit board.
Because wiring part 12 has circuits 13, 14, and 15 as an interface circuit between the terminals on the semiconductor device and as interface circuits for connection to external circuits, the area for mounting the interface circuits on the circuit board are eliminated, and the electronic device are downsized accordingly. The semiconductor module in accordance with the present invention is easy to handle because the semiconductor device and the wiring part thereof are formed integrally. Moreover, even the same semiconductor device can be connected to various kinds of external circuits by changing circuit 14 or 15.
[0023]FIG. 2 shows an example of wiring patterns on wiring part 12. Conductors 28 a and 28 b connected to terminals 26 and 27 on semiconductor device 11, respectively, form a capacitor. The broken line shows a conductor formed on another layer when wiring part 12 is formed of a plurality of layers. Chip component 29 is mounted on wiring part 12. Inductor 30 is also provided on wiring part 12. Because distance 33 between the terminals on semiconductor device 11 is typically so narrow as 0.15 mm or smaller, the terminals cannot be soldered directly onto the circuit board without any appropriate measures. On the other hand, distance 34 between input/output terminals 31 and 32 is 0.2 mm or larger so that the input/output terminals can be reflow soldered onto the circuit board. Then the terminals on semiconductor device 11 are soldered onto the circuit board via input/output terminals 31 and 32.
[0025]FIG. 3(a) shows an example of capacitance adjustment of a capacitor formed of wiring patterns. The capacitance between patterns 37 and 38 is adjusted by laser trimming part 39 of pattern 38 opposite to pattern 37. FIG. 3(b) shows an example of inductance adjustment of inductor 42 formed of a wiring pattern. The inductance of inductor 42 is adjusted by laser trimming part 43 of the wiring pattern. By adjusting the wiring patterns in this manner, the differences in the characteristic of semiconductor device 11 can be accommodated.
[0026]FIG. 4 is a sectional view of the semiconductor module of the present invention. Chip component 30 and semiconductor amplifier 45 are mounted on wiring part 12 provided on one side of semiconductor device 11, and are embedded in insulator 47. Top face 45 a of semiconductor amplifier 45 is exposed from wiring part 12 for heat release. The heat release effect can be further improved by providing copper foil in a position in contact with top face 45 a on the circuit board on which this semiconductor module is mounted. Wiring part 12 is composed of a plurality of layers. Ground layer 46 is provided between semiconductor device 11 and wiring part 12. Ground layer 46 reduces mutual interference between the circuits in wiring part 12 and the circuits in semiconductor device 11.
[0027]FIG. 5 is a sectional partial view of the semiconductor module of the present invention. Wiring layers 51 and 52 are formed in two layers. Pad 50 formed on semiconductor device 11 joins directly to conductor 53 in the first layer. Conductor 53 in the first layer, in turn, joins directly to conductor 54 in the second layer, which is located at a distance from pad 50. Provided on conductor 54 is solder bump 55 as an input/output terminal of the semiconductor module. Solder bump 55 and circuit board 57 are soldered with each other. Conductor 53 in the first layer, conductor 54 in the second layer, and connection between these conductors are made by pressing and heating of conductor paste, using such a method as intaglio transfer printing. Each of wiring layers 51 and 52 is made of a material having a different coefficient of linear expansion, and the coefficient of linear expansion sequentially increases from semiconductor device 11 to circuit board 57.
[0033]FIG. 6 illustrates a structure of a semiconductor module in accordance with the second embodiment of the present invention. Semiconductor device 60 forms a chip tuner. Semiconductor device 60 has wiring part 61 on one side 60 a thereof. Input/output terminal 62 is connected to the input of high-frequency amplifying circuit 63 in semiconductor device 60. The output of high-frequency amplifying circuit 63 is connected to one input of mixer 65. The output of oscillator 64 is connected to the other input of mixer 65.
[0039]FIG. 7 illustrates a structure of a semiconductor module in accordance with the third embodiment of the present invention. On one side 80 a of semiconductor device 80, wiring part 81 substantially identical with side 80 a in size is provided. Input/output terminal 82 formed of a bump that is provided on wiring part 81 is connected to the input of electronic circuit 84 in semiconductor device 80, via low-pass filter 83 in wiring part 81. Low-pass filter 83 eliminates noise. When low-pass filter 83 is formed of an inductor and a capacitor that are made of wiring patterns, frequencies at which the filter is passed can be set to an optimal value by adjusting these patterns by laser trimming.
a semiconductor device having a plurality of terminals; and
a wiring part provided on one side of said semiconductor device and substantially identical with said semiconductor device in size, wherein said wiring part includes an input/output terminal for connection to an external circuit, and said wiring part further includes at least one of a circuit connected between the terminals on said semiconductor device and a circuit connected between the terminals on said semiconductor device and the input/output terminal.
2. The semiconductor module as set forth in claim 1, wherein the circuit in said wiring part includes one of an inductor and a capacitor made of a wiring pattern.
3. The semiconductor module as set forth in claim 2, wherein one of said inductor and said capacitor is structured so as to be adjustable by laser trimming.
7. The semiconductor module as set forth in claim 1, wherein a coefficient of linear expansion of an insulator in said wiring part is larger than a coefficient of linear expansion of said semiconductor device, and smaller than a coefficient of linear expansion of a circuit board on which said semiconductor device is mounted.
US10156975 2001-11-26 2002-05-29 Semiconductor module Active 2023-03-10 US6870260B2 (en)
JP2001358788A JP2003158214A (en) 2001-11-26 2001-11-26 Semiconductor module
JP2001-358788 2001-11-26
US20030098505A1 true true US20030098505A1 (en) 2003-05-29
US6870260B2 US6870260B2 (en) 2005-03-22
ID=19169907
US10156975 Active 2023-03-10 US6870260B2 (en) 2001-11-26 2002-05-29 Semiconductor module
US (1) US6870260B2 (en)
EP (1) EP1315207A3 (en)
JP (1) JP2003158214A (en)
CN (1) CN1280866C (en)
JP3287310B2 (en) * 1998-06-30 2002-06-04 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
JP2000349205A (en) * 1999-06-08 2000-12-15 Matsushita Electric Ind Co Ltd Laminated carrier board and package integrate circuit using the same
EP1315207A2 (en) 2003-05-28 application
US6870260B2 (en) 2005-03-22 grant
EP1315207A3 (en) 2006-09-20 application
JP2003158214A (en) 2003-05-30 application
CN1421925A (en) 2003-06-04 application
CN1280866C (en) 2006-10-18 grant
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIMURA, JUNICHI;TANAKA, KAZUTOSHI;REEL/FRAME:013175/0823