Source: http://www.google.com/patents/US4107556?dq=7565338
Timestamp: 2016-05-03 10:39:20
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Patent US4107556 - Sense circuit employing complementary field effect transistors - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA sense circuit suitable for use with semiconductor memory arrays which, in contrast to sense circuits of similar type, exhibits no voltage offset in the latched condition between the input-output (I/O) nodes and the supply lines. The sense circuit includes first and second complementary inverters with...http://www.google.com/patents/US4107556?utm_source=gb-gplus-sharePatent US4107556 - Sense circuit employing complementary field effect transistorsAdvanced Patent SearchPublication numberUS4107556 APublication typeGrantApplication numberUS 05/796,334Publication dateAug 15, 1978Filing dateMay 12, 1977Priority dateMay 12, 1977Publication number05796334, 796334, US 4107556 A, US 4107556A, US-A-4107556, US4107556 A, US4107556AInventorsRoger Green Stewart, Sargent Sheffield Eaton, Jr.Original AssigneeRca CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (6), Non-Patent Citations (1), Referenced by (21), Classifications (20) External Links: USPTO, USPTO Assignment, EspacenetSense circuit employing complementary field effect transistors
US 4107556 AAbstract
A sense circuit suitable for use with semiconductor memory arrays which, in contrast to sense circuits of similar type, exhibits no voltage offset in the latched condition between the input-output (I/O) nodes and the supply lines. The sense circuit includes first and second complementary inverters with inputs connected to first and second I/O nodes, respectively, and with outputs capable of being clamped to one or the other of the two supply lines powering the inverters. Selectively and sequentially enabled cross-coupling transmission gates are connected between the output of each inverter and the input to the other inverter, and selectively enabled biasing transmission gates are connected between the input and output of each inverter. In the operation of the circuit, the two input nodes are first precharged to a predetermined value by enabling the biasing gates. A signal is then applied to one I/O node causing its potential to vary from its quiescent value. Then, the cross-coupling gate connected to the output of the inverter whose input is connected to the one I/O node is first enabled and, subsequently, the other cross-coupling gate is enabled. When the two cross-coupling gates are enabled, the inverters are latched and form a flip flop with the first I/O node clamped to the supply line having the same binary signal and the second I/O node clamped to the other power supply line.
1. A sense amplifier comprising:first and second nodes; means for applying signals to said first and second nodes; first and second inverters, each inverter having an input, an output, and first and second power terminals for the application thereto of first and second operating voltages, respectively; each inverter comprising respective first and second transistors of complementary conductivity type and being responsive to a first level at its input for clamping its output to the voltage at said first power terminal via its first transistor conducting in the common source mode, and being responsive to a second level at its input for clamping its output to the voltage at said second power terminal via its second transistor conducting in the common source mode; means connecting the input of said first inverter to said first node, and means connecting the input of said second inverter to said second node; a first biasing means connecting between the input and the output of said first inverter, and a second biasing means connected between the input and the output of said second inverter, said first and second biasing means for selectively providing a direct current connection between the input and output of each one of said first and second inverters and biasing them at first and second quiescent points, respectively; and first and second selectively enabled cross coupling means; said first cross coupling means, when enabled, for coupling the output of said first inverter to said second node via a low impedance path which includes first transistor means conducting in the common source mode under all signal conditions, and said second cross coupling means, when enabled, for coupling the output of said second inverter to said first node via a low impedance path which includes second transistor means conducting in the common source mode under all signal conditions,. 2. The sense amplifier claimed in claim 1 wherein said first transistor means is a first complementary transistor transmission gate connected between the output of said first inverter and said second node; andwherein said second transistor means is a second complementary transistor transmission gate connected between the output of said second inverter and said first node. 3. The combination comprising:first and second nodes; means for applying signals to said first and second nodes; first and second inverters, each inverter having an input, an output; means connecting the input of said first inverter to said first node, and means connecting the input of said second inverter to said second node; a first biasing means connected between the input and the output of said first inverter, and a second biasing means connected between the input and the output of said second inverter, said first and second biasing means for selectively providing a direct current connection between the input and output of each one of said first and second inverters and biasing them at first and second quiescent points, respectively; and first and second selectively enabled cross coupling means, said first cross coupling means for coupling the output of said first inverter to said second node via a low impedance path, when enabled, and said second cross coupling means for coupling the output of said second inverter to said first node via a low impedance path, when enabled; said first and second selectively enabled cross coupling means including means for sequencing the enabling of said cross coupling means. 4. The combination as claimed in claim 3 wherein said means for applying signals to said first and second nodes, includes means for applying a signal to one of said first and second nodes at a time, andwherein said means for sequencing the turn on of said cross coupling include means responsive to the application of a signal to said one of said first and second nodes for first enabling the cross coupling means connected between the output of the inverter whose input is connected to said one node and for subsequently enabling the other cross coupling means. 5. The combination as claimed in claim 4 wherein each one of said cross-coupling means includes two transistors of complementary conductivity having their conduction paths connected in parallel.
This invention relates to sense circuits, suitable for use with semiconductor memory arrays and, in particular, to a sense circuit capable of sensing a small input signal on one of its input-output (I/O) lines and which, in response thereto, is capable of clamping that one of its I/O lines via a low impedance path to that one of the two power supply lines powering the sense circuit having the same binary significance as the input signal.
In the accompanying drawings, like reference characters denote like components and;
The memory cells of high density semiconductor memory arrays produce relatively small signals when read out. For example, a high density dynamic memory may include a storage capacitor (CS) and a series connected switching transistor at each bit location. When a bit is read out, CS is coupled via the switching transistor to a bit line connected to the input of a sense amplifier. CS is then placed in parallel with the capacitance (CA) associated with the bit line and the amplifier input, and the charge originally across CS is redistributed between CS and CA. Since CA is normally two or three orders of magnitude greater than CS, the signal voltage originally present across CS is greatly attenuated. Assume, for example, that CS and CA have values of C, and 10C, respectively, and that prior to read out, CS was either at zero volts or at +V volts and CA was at V/2 volts. After read out the voltage across CS and CA will be approximately [V/2 � ΔV] volts where ΔV is approximately equal to V/20. Therefore, the voltage across CS is altered from +V volts to [V/2 + ΔV] volts or from zero volts to V/2 - ΔV. The alteration of the signal originally present across CS amounts to destructive read out and is unacceptable in typical random access memories (RAMs). A sense circuit is, therefore, needed which can read the small signal (ΔV) produced when a memory cell is read out and then write back into the cell its original contents.
Sense circuits embodying the invention include first and second inverters connected at their inputs to first and second nodes, respectively. Each inverter is connected at its output via a selectively enabled cross-coupling transmission gate to the input of the other inverter. A selectively enabled biasing transmission gate is connected between the input and the output of each inverter for selectively biasing the inverter input to the voltage at its output. The inverters include devices of complementary conductivity type to clamp the output to the power supply lines.
DETAILED DESCRIPTION OF THE DRAWING OF THE INVENTION
The circuit of FIG. 2 includes a sense circuit 10 which senses the information contained in a memory array 20 whose data bits are divided into two parts 20a, 20b. The bits in part 20a are selectively coupled to bit line La (node "a") and the bits in part 20b are selectively coupled to bit line Lb (node "b"). When part 20a of memory 20 is coupled to La, part 20b functions as a dummy load and, vice versa, when part 20b is read out onto Lb, part 20a functions as a dummy load. For ease of illustration, only one cell or bit (1a and 1b) from each part of memory 20 is shown. Each cell includes a switching transistor (Ma, Mb) and a storage capacitor (CSa, CSb). The gate of each switching transistor is connected to a word line (Wa, Wb) having a like alphabetic subscript and its source-to-drain path is connected between one side of data storage capacitor (CSa, CSb) and a bit line (La, Lb) having a like subscript. Transistors Ma, Mb, which are P-type IGFETs, are turned on when their gates are driven to ground. They then transfer the charge (data) stored on their associated storage capacitors to the corresponding nodes "a" or "b".
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3868656 *Dec 19, 1973Feb 25, 1975Siemens AgRegenerating circuit for binary signals in the form of a keyed flip-flopUS3879621 *Apr 18, 1973Apr 22, 1975IbmSense amplifierUS3983543 *Jun 30, 1975Sep 28, 1976International Business Machines CorporationRandom access memory read/write buffer circuits incorporating complementary field effect transistorsUS3983544 *Aug 25, 1975Sep 28, 1976International Business Machines CorporationSplit memory array sharing same sensing and bit decode circuitryUS3983545 *Jun 30, 1975Sep 28, 1976International Business Machines CorporationRandom access memory employing single ended sense latch for one device cellUS3992704 *Sep 5, 1975Nov 16, 1976Siemens AgArrangement for writing-in binary signals into selected storage elements of an MOS-store* Cited by examinerNon-Patent CitationsReference1 *Lohman, "Applications of MOSFETs in Microelectronics", SCP & Solid-State Technology (pub.); pp. 23-29; Mar. 1966.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS4239994 *Aug 7, 1978Dec 16, 1980Rca CorporationAsymmetrically precharged sense amplifierUS4321492 *Oct 15, 1979Mar 23, 1982Rca CorporationTwo input sense circuitUS4506167 *May 26, 1982Mar 19, 1985Motorola, Inc.High speed logic flip-flop latching arrangements including input and feedback pairs of transmission gatesUS4638183 *Sep 20, 1984Jan 20, 1987International Business Machines CorporationDynamically selectable polarity latchUS4823031 *Feb 1, 1988Apr 18, 1989Texas Instruments IncorporatedSingle-ended sense amplifier with positive feedbackUS5226014 *Dec 24, 1990Jul 6, 1993Ncr CorporationLow power pseudo-static ROMUS5332929 *Apr 8, 1993Jul 26, 1994Xilinx, Inc.Power management for programmable logic devicesUS5352937 *Nov 16, 1992Oct 4, 1994Rca Thomson Licensing CorporationDifferential comparator circuitUS5361229 *Apr 8, 1993Nov 1, 1994Xilinx, Inc.Precharging bitlines for robust reading of latch dataUS5384504 *Oct 22, 1992Jan 24, 1995Dickinson; Alexander G.Sense amplifier powered from bit lines and having regeneratively cross-coupling meansUS5508649 *Jul 21, 1994Apr 16, 1996National Semiconductor CorporationVoltage level triggered ESD protection circuitUS7068556 *Mar 9, 2004Jun 27, 2006Lattice Semiconductor CorporationSense amplifier systems and methodsUS7102934May 17, 2006Sep 5, 2006Lattice Semiconductor CorporationSense amplifier systems and methodsUS8125840 *Aug 31, 2009Feb 28, 2012International Business Machines CorporationReference level generation with offset compensation for sense amplifierUS20050201172 *Mar 9, 2004Sep 15, 2005Cruz Louis D.L.Sense amplifier systems and methodsUS20060209608 *May 17, 2006Sep 21, 2006Cruz Louis D LSense amplifier systems and methodsUS20110051532 *Aug 31, 2009Mar 3, 2011International Business Machines CorporationReference level generation with offset compensation for sense amplifierEP0054022A1 *Jun 2, 1980Jun 23, 1982Mostek CorporationDynamic random access memoryEP0306519A1 *Mar 8, 1988Mar 15, 1989Inmos CorpCurrent sensing differential amplifier.WO2005091934A2 *Mar 2, 2005Oct 6, 2005Lattice Semiconductor CorporationSense amplifier systems and methodsWO2005091934A3 *Mar 2, 2005Sep 14, 2006Lattice Semiconductor CorpSense amplifier systems and methods* Cited by examinerClassifications U.S. Classification327/57, 327/63, 327/399, 365/205, 327/318, 365/202, 326/99, 365/196International ClassificationH03K3/356, G11C11/4091, H03K5/02, G11C11/404Cooperative ClassificationH03K5/023, G11C11/404, H03K3/356147, G11C11/4091European ClassificationG11C11/404, H03K5/02B, H03K3/356G2F, G11C11/4091RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services