Source: http://www.google.com/patents/US7486313?dq=6175559
Timestamp: 2015-01-27 01:16:19
Document Index: 432454992

Matched Legal Cases: ['art 800', 'art 800', 'art 805', 'art 805', 'art 805', 'art 900', 'art 900']

Patent US7486313 - System and method for automatic exposure control and white balancing for ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA system and method for averaging incident light on plural pixels using a CMOS sensor is provided. The process includes resetting all pixels in a given region during a reset phase; and reading a voltage of a floating reset node as a function of time during a measurement phase. During the reset phase,...http://www.google.com/patents/US7486313?utm_source=gb-gplus-sharePatent US7486313 - System and method for automatic exposure control and white balancing for CMOS sensorsAdvanced Patent SearchPublication numberUS7486313 B2Publication typeGrantApplication numberUS 10/346,235Publication dateFeb 3, 2009Filing dateJan 17, 2003Priority dateJan 17, 2003Fee statusPaidAlso published asUS7728897, US20040141074, US20060192888, WO2004068846A1Publication number10346235, 346235, US 7486313 B2, US 7486313B2, US-B2-7486313, US7486313 B2, US7486313B2InventorsMihail M. Milkov, David Standley, Amit MittraOriginal AssigneeBiomorphic Vlsi, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (14), Non-Patent Citations (1), Referenced by (2), Classifications (16), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSystem and method for automatic exposure control and white balancing for CMOS sensorsUS 7486313 B2Abstract A system and method for averaging incident light on plural pixels using a CMOS sensor is provided. The process includes resetting all pixels in a given region during a reset phase; and reading a voltage of a floating reset node as a function of time during a measurement phase. During the reset phase, an access select signal and a reset voltage are both high. The measurement phase begins when the access select signal is low and the reset voltage is still high. The system and method may be used to perform automatic exposure control and automatic white balancing operations.
1. An analog circuit for performing white balancing using a CMOS sensor, comprising:
a first access node that provides a first access voltage to at least a first pixel of a pixel array;
at least a second access node that provides a second access voltage to at least a second pixel of the pixel array;
a first access switch that operationally couples the first access node to a reset voltage source for making the first access node to receive a reset voltage provided by the reset voltage source directly;
a second access switch that operationally couples the second access node to the reset voltage source for making the second access node to receive the reset voltage directly;
a first reset switch that controls the pixels in even rows of the pixel array; and
a second reset switch that controls the pixels in odd rows of the pixel array, wherein during a measurement phase a change in one of the first access node voltage and the second access voltage provides an average response for a plurality of pixels coupled to the first access node and the second access node; and a pixel averaging operation is performed by pixel charge sharing in a single step instead of processing pixel data sequentially.
2. The analog circuit of claim 1, further comprising a first parasitic capacitor operationally coupled to the first access node.
3. The analog circuit of claim 1, further comprising a second parasitic capacitor operationally coupled to the second access node
4. The analog circuit of claim 1, wherein a signal external to the pixel array controls the first and the second access switches.
5. The analog circuit of claim 1, wherein a first reset signal controls the first reset switch and a second reset signal controls the second reset switch.
6. The analog circuit of claim 5, wherein during a reset phase if the first reset signal is high and the second reset signal is low then a pixel in an even row of the pixel array is coupled to one of the first access node and the second access node such that the first access voltage and the second access voltage is equal to the reset voltage.
7. The analog circuit of claim 5, wherein during the reset phase if the first reset signal is low and the second reset signal is high then a pixel in an odd row of the pixel array is coupled to one of the first access node and the second access node such that the first access voltage and the second access voltage is equal to the reset voltage.
8. An analog circuit for performing white balancing using a CMOS sensor, comprising:
a first access switch that operationally couples the first access node to a reset voltage source for making the first access node to receive a reset voltage provided by the reset voltage source directly; and
a second access switch that operationally couples the second access node to the reset voltage source for making the second access node to receive the reset voltage directly, wherein during a measurement phase a change in the first access node voltage or the second access voltage provides an average response for a plurality of pixels coupled to one of the first access node and the second access node; and a pixel averaging operation is performed by pixel charge sharing instead of processing pixel data sequentially.
9. The analog circuit of claim 8, further comprising:
second reset switch tat controls the pixels in odd rows of the pixel array.
10. The analog circuit of claim 9, wherein a first reset signal controls the first reset switch and a second reset signal controls the second reset switch.
11. The analog circuit of claim 10, wherein during a reset phase if the first reset signal is high and the second reset signal is low then a pixel in an even row of the pixel array is coupled to one of the first access node and the second access node such that the first access voltage and the second access voltage is similar to the reset voltage.
12. The analog circuit of claim 10, wherein during the reset phase if the first reset signal is low and the second reset signal is high then a pixel in an odd row of the pixel array is coupled to one of the first access node and the second access node such that the first access voltage and the second access voltage is similar to the reset voltage.
13. The analog circuit of claim 8, further comprising a first parasitic capacitor operationally coupled to the first access node.
14. The analog circuit of claim 8, further comprising a second parasitic capacitor operationally coupled to the second access node.
15. The analog circuit of claim 8, wherein a signal external to the pixel array controls the first access switch and the second access switch. Description
The present invention relates to image sensors, and more particularly, to automatic exposure control and white balancing using active pixel CMOS sensors.
Solid State or electronic image sensors consist of array(s) of photodiodes that produce an electrical signal in response to light illumination. Such image sensors can be divided into two broad categories, CCD (charge-coupled devices) and CMOS (Complementary Metal Oxide Semiconductor), depending on how the signal is read out from the photodiodes.
Typically, CCD sensors use repeated lateral transfer of charge in an analog shift register. Photo-generated electrons or holes are read out after they are shifted in appropriate positions. CCD sensors have disadvantages, for example, to perform charge shifting with high fidelity, and low loss requires specialized semiconductor fabrication processes, which are not compatible with the fabrication process used to make most solid-state integrated circuits. This increases the overall cost of the CCD sensors.
In CMOS sensors, signals from the photodiodes are read out as column readout lines, one row at a time. During readout, there is no shifting of charge from one pixel to another. Because CMOS sensors are compatible with typical CMOS fabrication processes, they allow integration of additional signal processing logic on the same substrate as the sensor array. This leads to reduction in the size and cost of a digital camera.
A highly integrated CMOS sensor chip can perform many image processing functions that are otherwise carried out by a controller, external to the sensor. Two such functions are automatic exposure (AE) control and automatic white balancing (AWB) that are described below.
Automatic exposure (AE) control: Similar to conventional film, sensors in digital cameras are exposed to light for certain duration, known as the �exposure time�. For given light conditions and lens aperture, there is an optimum exposure time that produces desirable pictures. An exposure time longer than optimum results in an image that is overly bright, and it will look �washed out.� An exposure time shorter than the optimum time results in an image that is �too dark and difficult to view.� AE control is the ability of the sensor chip to select optimum exposure time for a given scene lighting condition, without user intervention.
Currently, AE control processes used in electronic digital cameras calculate the optimum exposure value after performing a histogram analysis on a signal strength measured at all the locations in a picture using multiple preliminary frames. One way of analyzing the signal strength distribution is to determine the actual frame mean and then to compare it with a desired frame mean. If the actual frame mean is less than the desired mean, then the exposure time is increased; otherwise, the exposure time is decreased.
Another conventional solution is to sort all pixels within an image frame into different brackets depending on their brightness. The goal is to count the number of pixels that are unacceptably bright and those that are unacceptably dark and then make an incremental adjustment to the exposure setting that tries to balance the number of pixels that are too dark with those that are too bright.
The foregoing conventional techniques have disadvantages. To determine the optimum exposure time, both the foregoing techniques require a starting point to acquire an image that is not fully saturated or completely dark for the histogram analysis. An additional photometer is required as a part of the digital camera to choose a suitable exposure starting point that is close to the optimum exposure for arbitrary light conditions. If no additional photometer is used, the first frame used by the foregoing techniques is either saturated or too dark. Consequently, conventional techniques require acquisition of several frames until the optimum exposure time is determined. If the camera is used in a snapshot mode, then there will be a noticeable delay from the time the camera trigger is pressed until the final picture is taken
Conventional techniques also have to process sequentially a large number of pixels to build representative histogram data or find the mean. Since these techniques work directly on sensor output as the sensor is being scanned out, all data processing circuitry for pixel tallying must operate at pixel readout rate and thus consumes a significant amount of power during multiple frames. The power penalty may be even higher if digital pixel data is processed. In this case, all blocks in the signal processing chain from the pixel to the analog-to-digital (A/D) converter need to be powered while the AE control block is running.
Automatic white balancing (AWB): Typical solid state imaging arrays can be described as combination of multiple sub-arrays of individual color detectors. One such pattern 100 (known as the Bayer pattern) that is commonly used is shown in FIG. 1. This arrangement consists of interspersed red, green and blue (also referred to herein as R, G, B) detectors (103-101). R 103, G 102 and B 101 pixels have different light sensitivity and thus produce different signal levels even if incident light is white with equal components of red, green and blue. As a result, a white object in a scene will not appear white in an unprocessed picture. This problem is corrected by �white balancing� which adjusts signal levels for R, G and B pixels so that the image of a white object appears white in a picture. White balancing involves multiplying R, G and B pixels in an image array (e.g. 100 of FIG. 1) by certain coefficients, known as white balance (WB) coefficients. If R, G and B are raw signal levels before white balancing, then the signal levels after white balancing, RWB, GWB and BWB may be expressed as
R WB =W R *R (1a) G WB =W G *G (1b) B WB =W B *B (1c)
WR, WB and WG are white balance coefficients for red, green and blue, respectively for a given lighting.
Manual white balancing requires the user to point a camera at a white background and manually adjust the WB coefficients until the background appears white, for which RWB=GWB=BWB. Also the WB coefficient for the color having the strongest raw signal is usually set to 1. For example, if G>B>R, then;
W R =G white /R white (2a)WG=1 (2b) W B =G white /B white (2c)
Rwhite, Gwhite and Bwhite are raw signals from red, green and blue pixels comprising a white object and it is assumed that Gwhite is the strongest signal.
WB coefficients may be automatically determined by using equations (2a), (2b) and (2c). However, the user still needs to point the camera at a white object.
This restriction is overcome by making the assumption that real-world scenes contain equal amounts of red, green and blue colors. In other words, a typical white-balanced picture has equal means for R, G and B pixels when the means are calculated over the entire image. Under this assumption, equations (2a), (2b) and (2c) may be rewritten in terms of pixel means:
W R = G/ R (3a)WG=1 (3b) W R = G/ B, (3c)
where R, G and B are raw red, green and blue pixel means before white balancing and it is assumed (for illustration purposes) that the green mean is the highest.
Based on equations (3a), (3b) and (3c), real-life scene-based automatic white balancing requires three operations: 1) finding the mean values for R, G and B pixels; 2) finding the highest of the three means; 3) setting the WB coefficient of the color with the highest mean to 1, and finding the other two WB coefficients as ratios of the frame means. The three color means are representative only for a picture with intermediate frame brightness. A saturated picture or a picture that is too dark will not carry useful color information. Therefore white balancing will be accurate only after AE control is complete, which, as discussed earlier, takes several frames in conventional implementations.
Conventional AWB techniques have disadvantages. One such disadvantage is that conventional processes require several frames. Typically the user has to hold the camera still during this entire period since it is not clear when this process is completed by a digital camera and the actual picture is �saved.� Additional problems with conventional digital signal processing (DSP) or ASIC based implementations of the foregoing processes require additional chip area and power consumption. These limitations make the conventional processes impractical for single-chip digital camera applications.
Therefore what is required is a system and process for efficiently performing auto-exposure control and white balancing for the modern, single-chip digital cameras.
SUMMARY OF THE INVENTION In one aspect of the present invention, a method for averaging incident light on plural pixels (or pixel array) in a CMOS sensor is provided. The method includes resetting all pixels in a given region during a reset phase; and reading a voltage of a floating access node as a function of time during a measurement phase. During the reset phase, a signal external to the pixel array and a reset signal are similar. The measurement phase begins when the signal is low and the reset signal is still high.
In one aspect of the present invention, a system for averaging incident light on plural pixels (pixel array) using a CMOS sensor is provided. The system includes a voltage node common to plural pixels in a pixel array that provides a floating access voltage; a reset voltage source that provides a reset voltage to plural photodiodes; a reset signal that controls plural reset transistors; and a switch between the common voltage node and reset voltage source, wherein the operation of the switch is controlled by a signal external to the pixel array.
During a reset phase the signal external to the pixel array and the reset signal are similar for all pixels and the access voltage and reset voltage are substantially similar in value. A measurement phase begins when the external signal is low, while the reset signal is high. During the measurement phase a photodiode and a junction capacitor are in parallel to each other and a change in the access voltage over time indicates an average response of pixels to any incident illumination.
In another aspect of the present invention, an analog circuit for performing automatic exposure control for a CMOS sensor using pixel charge sharing is provided. The analog circuit includes the voltage node common to plural pixels in a pixel array that provides a floating access voltage; the reset voltage source that provides a reset voltage to plural transistors in the analog circuit; and the switch between the common voltage node and reset voltage source, wherein the operation of the switch is controlled by the signal external to the pixel array.
In another aspect, a method used in the analog circuit for performing automatic exposure control for a CMOS sensor using pixel charge sharing is provided. The method includes, resetting all pixels in a given region during a reset phase; and reading a voltage of a floating access node as a function of time during a measurement phase.
In yet another aspect of the present invention, an analog circuit for performing white balancing using a CMOS sensor by selectively applying pixel charge sharing to a pixel array is provided. The circuit includes, a first access node that provides a first access voltage to at least one pixel; at least a second access node that provides a second access voltage to at least a second pixel; a first access switch that operationally couples the first access node to a reset voltage source; a second access switch that operationally couples the second access node to the reset voltage source; a first reset switch that controls the pixels in even rows of the pixel array; and a second reset switch that controls the pixels in odd rows of the pixel array.
The circuit includes a first parasitic capacitor operationally coupled to the first access node and a second parasitic capacitor operationally coupled to the second access node. A signal external to the pixel array controls the first and second access switches and a first reset signal controls the first reset switch and a second reset signal controls the second reset switch.
During a reset phase if the first reset signal is high and the second reset signal is low then a pixel in an even row is coupled to the first access or second access node such that the first access node and second access node voltage is equal to a reset voltage. During a measurement phase the change in the first access node voltage or the second access node voltage provides a pixel response of the pixel coupled to the first access node or second access node.
During the reset phase if the first reset signal is low and the second reset signal is high then a pixel in an odd row is coupled to the first access or second access node such that the first access node and second access node voltage is equal to a reset voltage. Also, during the measurement phase the change in the first access node voltage or the second access node voltage provides a pixel response of the pixel coupled to the first access node or second access node.
In yet another aspect of the present invention, a method for performing white balancing using a CMOS sensor by selectively applying pixel charge sharing to a pixel array is provided. The method includes, coupling at least a first pixel to a first common node voltage during a reset phase; and coupling at least a second pixel to a second common node voltage during the reset phase.
In one aspect, the present invention overcomes the aforementioned problems associated with conventional AE control and AWB techniques. Pixel averaging in the present invention is implemented in the analog domain and it is designed such that the analog circuit does not process pixel data sequentially. Instead, the averaging operation is accomplished in one step by pixel charge sharing and this computation is performed in the imaging array itself. Due to the parallel nature of this computation the duration of the averaging process is independent of the number of pixels to be averaged and takes only a fraction of the time used by conventional techniques. Moreover, the obtained pixel average is always proportional to the average illumination; i.e., there is no saturation effect. As a result, both AE control and AWB can be completed in less than a frame, as opposed to several frames when the conventional techniques are used.
In another aspect of the present invention, since pixels are not read out sequentially, the entire readout and signal processing chain can be powered down during AE control and AWB operation. The present invention thus offers substantially decreased running time for performing AE control and AWB as well as significant reduction in the power dissipation.
In yet another aspect of the present invention, the pixel averages for each color are available as analog quantities to determine the WB coefficients given by equations (3a) and (3c), which saves chip area in the digital domain.
In yet another aspect of the present invention, no modification is required to the three-transistor active pixel sensor, commonly used in CMOS imagers. Only a single switch may be added between the access node and the reset voltage source, which is external to the imaging array.
BRIEF DESCRIPTION OF THE DRAWINGS The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate but not to limit the invention. The drawings include the following Figures:
FIG. 1 shows a pixel arrangement in a Bayer GR color pattern used in one aspect of the present invention;
FIG. 2 shows a schematic of a three-transistor active pixel sensor (APS) in an imaging array;
FIG. 3 shows a schematic of a column of APS pixels with an added access switch for pixel charge sharing, according to one aspect of the present invention;
FIG. 4 shows a timing diagram of signals for pixel charge sharing when all pixels in an imaging array are averaged, according to one aspect of the present invention;
FIGS. 5A and 5B show an equivalent circuit during pixel charge sharing when all pixels in an imaging array are averaged, according to one aspect of the present invention;
FIG. 6 shows an implementation of pixel charge sharing when red, green and blue pixels are averaged separately, according to one aspect of the present invention;
FIG. 7 shows a timing diagram of signals for pixel charge sharing when red, green and blue pixels are averaged separately, according to one aspect of the present invention;
FIGS. 8A-8D show a signal slope diagram and associated slope measurement system for automatic exposure control, according to one aspect of the present invention;
FIGS. 9A-9C show a pair of signals slope diagrams and an associated slope ratio measurement system for white balancing, according to yet another aspect of the present invention; and
FIGS. 10A-10D show block diagrams for implementing automatic exposure control and white balancing, according to yet another aspect of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS APS Imaging Array Operation
To facilitate an understanding of the preferred embodiment, the general architecture and operation of an active pixel sensor (APS) imaging array will first be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general operation of a modified APS array according to one aspect of the present invention.
FIG. 2 shows a schematic of a three-transistor APS 200, commonly used as a pixel element in CMOS sensors. APS pixel 200 includes a photodiode Dpix 201 with junction capacitor Cpix 202, reset transistor Mres 205, source follower transistor Mfol 206 and select transistor Msel 207. Node Vaccess 208 is common to all APS pixels and is connected to a reset voltage Vreset 213.
When a reset signal 205A to APS pixel 200 is high, Vpix node 204 is connected to node Vaccess 208 through reset transistor Mres 205, which is on at that instance. This charges capacitor Cpix 202 to a voltage Vreset 213 and photodiode Dpix 201 is reverse biased.
When Vpix 204=Vreset 213, reset transistor Mres 205 may be turned off, which leaves node Vpix 204 floating and photodiode current Iph 203 (the photo generated current), begins to discharge capacitor Cpix 202. As a result, pixel voltage Vpix 204 decreases at a rate proportional to Ip h 203. The exposure time for APS pixel array 200 is the period between the end of the reset phase (when Mres 205 is turned off) and when the pixel voltage Vpix 204 is read out. For illustration purposes, if the value of Vpix 204 at the time when it is read out is Vpix,RO, then Vpix,RO is converted to a digital value, proportional to the light intensity incident on the pixel. Therefore, to produce intermediate picture brightness, Vpix,RO, averaged over an entire frame should be in an appropriate range. This is achieved by choosing an appropriate exposure time for any given light intensity.
Pixel Charge Sharing: In one aspect of the present invention, a method and system is provided for averaging light incident on a group of pixels by charge sharing. The group of pixels may be an entire pixel array or a subset thereof, such as all red, or green, or all blue pixels.
FIG. 3 shows a system 200A for averaging pixels in a sensor (may also be referred to herein as �imager�) according to one aspect of the present invention. Vaccess 208 is common to all pixels and is coupled to a parasitic capacitor Cpar 216. In one aspect of the present invention, pixel charge sharing may be achieved by introducing a switch Sacc 214 between Vaccess node 208 and Vreset 213. Switch Sacc 214 may be controlled by an access select signal 215 that is external to pixel array 200A. In one aspect of the present invention, when access select signal 215 is high, Sacc 214 is closed and when access select signal 215 is low, Sacc 214 is open.
Averaging a chosen region of pixels by charge sharing can be accomplished by first resetting the pixels in the chosen region. This is followed by a node voltage read out phase (measurement phase), during which period the voltage of the floating reset network node is monitored as a function of time.
FIG. 4 illustrates a timing diagram, according to one aspect of the present invention, for finding the average intensity values of a group of pixels. The timing diagram shows the relationship between access select signal 215, reset signal 205A, row select signal 207A, Vaccess voltage 208, and Vreset voltage 213.
When row select signal 207A is low then transistors Mfol 206 and Msel 207 are off. For illustration purposes only, each pixel element may be simplified to include only photodiode Dpix 201 with capacitance Cpix 202 and reset transistor Mres 205. During reset phase 401, both access select signal 215 and reset signal 205A are high, and so for all pixels, transistor Mres 205 is on such that Vpix 204=Vaccess 208=Vreset 213. The measurement phase 403 begins when access select signal 215 becomes low at 405 and reset signal 205A is still high at 405A. All pixels still remain connected to Vaccess 208 and thus to each other, but Vaccess 208 now floats. During measurement phase 403, individual pixel photodiodes Dpix 201 and junction capacitors Cpix 202 are in parallel with each other.
This is also illustrated in FIGS. 5A-5B for a m�n pixel array. The charge on every pixel is shared among all pixels and the individual photodiode currents work in parallel to discharge this total charge. The total capacitance from Vaccess 208 to ground is:
C tot =NC pix +C par, (4)
where N=m�n is the total number of pixels. The total photodiode current,
I ph , tot = ∑ i = 0 m - 1 ∑ j = 0 n - 1 I ph , i , j = ∑ k = 1 N I ph , k , ( 5 ) discharges the total capacitance Ctot. Therefore, the rate of decrease of Vaccess 208 is
ⅆ V access ⅆ t = ∑ k = 1 N I ph , k N C pix + C par . ( 6 ) Since the average photodiode current over the total number of pixels N is
I _ ph = 1 N ∑ k = 1 N I ph , k , ( 7 ) equation (6) may be expressed as
ⅆ V access ⅆ t = I _ ph C pix + C par N . ( 8 ) The behavior of Vaccess 208 as a function of time is shown in FIG. 4. During the measurement phase 403, Vaccess 208 decreases (as shown by slope 402) with a rate proportional to the average photocurrent, or equivalently, to the average light intensity over the entire image array. In one aspect of the present invention, by measuring the temporal slope 402 of Vaccess 208 during measurement phase 403, the average response of all pixels to incident illumination can be determined, which provides automatic exposure control.
Finding RGB averages for AWB: In one aspect of the present invention, the system and method for determining pixel intensity average using pixel charge sharing may be utilized to average any group of pixels instead of the entire pixel array. The pixels to be averaged use common node Vaccess 208 that is connected to Vreset 213 through access switch Sacc 214. The pixels whose average is not required may have their access node directly connected to reset voltage 213. For AWB, the R, G and B averages are determined separately to calculate the WB coefficients as described above with respect to equations (3a), (3b) and (3c).
In one aspect of the present invention, FIG. 6 shows a circuit diagram for finding color averages for a pixel array (for example, pixel array 100 (FIG. 1)). For illustration purposes, green pixels on even rows may be designated as G1 602, and the green pixels on odd rows as G2 603. The pixels in even columns (G1 602 and B 601) share access node Vaccess1 208A while the pixels in odd columns (R 604 and G2 603) share access node Vaccess2 208B. Nodes Vaccess1 208A and Vaccess2 208B have corresponding parasitic capacitors 216A and 216B. Nodes Vaccess1 208A and Vaccess2 208B connect to reset voltage Vreset 213 through two switches Sacc1 214A and Sacc2 214B, both controlled by access select signal 215A. Reset switches 607 and 606 in all even row pixels are controlled by a reseteven rows signal (607A and 606A). Reset switches 608 and 605 in all odd row pixels are controlled by resetodd rows signal (608A and 605A).
FIG. 7 shows a timing diagram for signals access select 215A, reseteven rows (607A and 606A) and resetodd rows (608A and 605A) with two stages (700A and 700B) each including (1) a reset phase and (2) a measurement phase. (The row select signal, not shown in the diagram, is common to the entire pixel array and is low in both stages).
During the reset phase 700 of stage I 700A, reseteven rows 607A/606A are high and resetodd rows 608A/605A are low and therefore G1 602 pixel is connected to Vaccess1 208A and R pixel 604 is connected to Vaccess2 208B. Both Vaccess1 208A and Vaccess2 208B are first reset to Vreset 213 when access select signal 215A is high (reset phase 700), and then float when access select signal 215A is low (measurement phase 701).
During the measurement phase 701 of stage I 700A, slopes of Vaccess1 702 and Vaccess2 703 provide an average of G1 pixel 602 response and R pixel 604 response, respectively.
During stage II 700B, reseteven rows signals 607A/606A are low and resetodd rows signals 608A/605A are high and nodes Vaecess1 208A and Vaccess2 208B are connected to blue pixel 601 and G2 pixel 603, respectively. A measurement of slopes 706 (for Vaccess1 208A) and 707 for Vaccess2 208B) during measurement phase 705 of stage II 700B provides the average of blue pixel 601 and G2 603 pixel response, respectively.
Hence, R, G and B pixel means for an array (101, FIG. 1) may be determined in two stages of pixel charge sharing. The first stage yields the average values of G1 602 and R 604 and the second stage yields the average values of B 601 and G2 603. Either G1 602 or G2 603 can be used to represent the green response.
WB coefficients are then determined using the average values of R, G and B stored as voltage quantities. In one aspect of the present invention, both Vaccess1 208A and Vaccess2 208B are sampled at a certain time, t, after access select signal 215A goes low in each stage (700A and 700B). For purposes of illustration, sampled voltages may be designated as VG1,s and VR,s (from stage I, 700A) and VB,s and VG2,s (from stage II, 700B). The voltage quantities proportional to R, G and B means are determined by Vreset−VR,s, Vreset−VG2,s and Vreset−VB,s.
The pixel color with the highest mean may then be determined. For example, if green pixels have the highest mean, then the WB coefficients can be calculated as
W R = V reset - V G2 , s V reset - V R , s ( 9 a ) W G = 1 ( 9 b ) W B = V reset - V G2 , s V reset - V B , s . ( 9 c ) Slope Measurement:
There are several methods for measuring slope(s) 402, 702, 703, 706 and/or 707 discussed above with respect to FIGS. 4 and 7, respectively. The following provides examples of measuring the change in voltage over time, according to various adaptive aspects of the present invention. It is noteworthy that the present invention is not limited to any particular slope measuring technique.
Voltage Measurement for AE Control:
For AE control, a voltage signal may decrease at a constant rate and have a large range of possible values. This would be the situation when a camera is being used outdoors, where illumination is constant but can have a wide range of values. AE control typically has a time limit imposed by the user. FIG. 8A provides a graphical illustration of the change in voltage signal 808 over time. In FIG. 8A, the slope 808A is relatively steep (compared to slope 807A in FIG. 8B), and voltage Vsignal 808 crosses a fixed voltage Vref 804 at a time tstop 801, which is before the maximum period for AE, tmax 802. Hence, the time measurement 803 in FIG. 8A provides slope 808A.
FIG. 8B shows another Vsignal 807, where the slope 807A is not steep relative to slope 808A. In this example, Vsignal 807 does not reach Vref 804. Hence, a voltage measurement 806 at time tmax 802 provides slope 807A.
FIG. 8C shows a block diagram of a system 813 to measure tstop 801, according to one aspect of the present invention. Vsignal 808 (Vaccess 208 ) and Vref 804 are compared by comparator 812. The result 813 is sent to a time measurement module 803. A tstart 800 clock signal is also sent to time measurement module 803 that generates the time difference 803A between tstop 801 and tstart 800. Signal 803A is then sent to a multiplier (not shown) for normalization.
FIG. 8D shows a block diagram of a system 813A, according to one aspect of the present invention, to measure the difference between Vstart 805 (similar to Vreset 213) and Vsignal 807 (similar to Vaccess 208). Vsignal 807 is sent to a sample/hold module 810 which also receives a clock signal for tmax 802. Signal Vstop 809 is sent to an A/D converter 811 that also receives Vstart 805 as input. The difference between Vstart 805 and Vstop 809 is generated as signal 812A.
Slope Measurement for AWB:
FIGS. 9A and 9B show two voltage signals (903 and 906) of varying slopes. Here Vsignal1 903 has a steeper slope 903A than Vsignal2 906 slope 906A. In this example, Vsignal1 903 may be Vaccess1 208A and Vsignal2 906 may be Vaccess2 208 B (FIG. 7) during the first interval (stage I 700A), to get the slope ratio between G1 602 and R pixel 604.
During the second interval (stage II 700B), the foregoing may also be chosen to get the slope ratio between G2 603 and B pixel 601.
FIG. 9C shows system 913 that measures the ratio of these slopes (903A and 906A), which may be used in an AWB system of the present invention, as discussed above.
When Vsignal1 903 crosses Vref 901, voltage Vsignal2 906 may be sampled and converted by analog/digital (A/D) converter 914. The difference 912 (Vstart 900−Vsample 908) indicates the ratio as normalized to (Vstart 900−Vref 901). If a time constraint is imposed, then Vsignal1 903 must have a steep enough slope, just like the system of FIG. 8B.
FIGS. 10A-10D provide block diagrams for implementing the method/systems discussed above with respect to FIGS. 3 and 6, in yet another aspect of the present invention. FIGS. 10A-10D are based on a two-channel, two-stage R, G and B pixel averaging process described earlier. AE control is completed in stage 1 while AWB is completed only after both stage 1 and stage 2 are complete. If the user decides to bypass AWB, then only AE control may be performed in stage 1, and stage 2 is skipped.
Vaccess1/2 Monitoring circuit (FIG. 10A). Vaccess monitoring circuit 1000 generates a timing signal if either Vaccess1 208A or Vaccess2 208B falls below a reference voltage. In order to account for mismatches, the actual reset levels Vreset1 1014 and Vreset2 1015 for even and odd columns are sampled at the beginning of stage 1 (on the rising edge of start_s1 1002 signal) and stage 2 (on the rising edge of start_s 2 1032 (FIG. 10C)). The reference voltages Vref1 1003 and Vref2 1004 for even and odd columns are then established by subtracting a common voltage Δ V 1011 from sampled reset levels Vreset1 1014 and Vreset2 1015 respectively. The reset level sampling and subtraction of Δ V 1011 may be implemented in a switched capacitor opamp circuit using offset-canceling, as is known in the prior art.
Δ V 1011 = V drop 1012 M 1013 ( 10 ) is generated using a resistor ladder-based reference circuit. Its value is dependent on user-supplied parameter M 1013=1, 2, 4, 8 or 16 and on Vdrop 1012, which is the drop in access voltage that corresponds to an image frame with intermediate brightness. Choosing a higher M 1013 and thus a smaller Δ V 1011 leads to time saving, because Vaccess1 208A or Vaccess2 208B will cross the reference sooner, yet a smaller value of ΔV 1011 is more difficult to resolve in the comparator (1005 or 1006). The actual value for M 1013 is a compromise between these two factors. The signal stop1 1007 will go high whenever Vaccess1 208A≦Vref1 1003. Similarly, the signal stop2 1008 will go high whenever Vaccess2 208B≦Vref2 1004. Therefore stopXvr 1010 will go high as soon as the channel with the higher slope (Vaccess1 208A or Vaccess2 208B) drops by Δ V 1011.
Automatic Exposure Control Counter (FIG. 10B). For AE control, exposure counter 1020B generates a digital word to be written to the exposure register (not shown) of the sensor. The exposure counter 1020B is reset to zero on the rising edge of start_s1 1002. After that it starts counting in a step of N 1022B≧1, which is a user adjustable parameter. Selecting a step N>1 forces the exposure time to be a multiple of a certain time period. This proves advantageous when image flicker (as may be caused by luminescent lighting, for example) needs to be suppressed. Each time exposure counter 1020B is incremented, its value Exp is compared against MaxExp−N, where MaxExp 1022A is a parameter provided by the user indicating the maximum exposure time not to be exceeded by the AE control. If Exp≧MaxExp−N, then the signal stopMax 1017 goes high and therefore stop_s1 1020 goes high. Signal stop_s1 1020 also goes high when Vaccess1 208A or Vaccess2 208B crosses the reference in stage 1 (i.e. when stopXvr 1010 goes high).
When stop_s1 1020 goes high, exposure counter 1020B stops and its value can be transferred to the exposure register (not shown). It follows that the exposure time is based either on pixel average of G1 602 or R pixels 604, whichever is higher, or is limited to MaxExp 1022 A in low light conditions.
The frequency fc 1023 at which exposure counter 1020B is run depends on user-supplied parameters M 1013 and N 1022B and voltage Δ V 1011. If M1013=N 1022B=1, then fc=fc0 and Δ V 1011=Vdrop 1012. Because Vdrop 1012 corresponds to intermediate frame brightness, then time Δ texp in which Vaccess1 208A or Vaccess2 208B drops by Vdrop 1012 is the desired exposure time for given light conditions. This means that in a time Δtexp, exposure counter 1020B reaches a setting that will correspond to an exposure time of Δ texp. In other words, for M1013=N1022B=1, the exposure counter 1020B runs at the same speed as in an actual image frame acquisition. For every 1/fc0 step exposure counter 1020B is incremented by N=1, and 1/fc0 is the time duration corresponding to one exposure unit in the exposure register. More generally, if exposure counter 1020B is incremented by a step of N 1022B, then the counting frequency is fc0/N 1022B in order to achieve the same exposure setting, regardless of N 1022B, in time Δ texp.
For a higher value of M1013, ΔV 1011 is smaller, and so Vaceess1 208A or Vaccess 2 208B cross the reference earlier, which stops exposure counter 1020B earlier. However the exposure time should not depend on the choice of Δ V 1011 but instead on the light intensity. Therefore, as Vdrop 1012 is decreased by a factor of M 1013, the counting frequency fc0 must be increased by the same factor of M 1013 in order to maintain correct reporting of the exposure time. In summary, the counting frequency fc 1023 of the exposure counter 1020B is:
f c = M f c0 N ( 11 ) The user-provided parameter M 1013 affects the time spent in stage 1 and stage 2. This time is equal to Δ texp/M 1013 in each stage, where Δ texp is the desired exposure time for the given light conditions. Therefore, selecting a higher value of M 1013 leads to faster operation of the AE control and AWB operation. The user-provided parameter N 1022B determines the flicker suppression frequency by forcing the exposure time to be a multiple of N 1022B.
The exposure counter 1020B also runs in stage 2, yet it no longer counts the exposure time. Instead, at the beginning of stage 2 it starts from the exposure time reached in stage 1 and then counts backwards. When it reaches zero, it issues the signal stop_s2 1033. Thus the time Δ t from the start of stage 1 until stop_s1 1020 goes high is the same as the time from the start of stage 2 until stop_s2 1033 goes high. Because stop_s1 1020 and stop_s2 1033 are used as sampling signals, therefore, keeping the same Δ t ensures a fair comparison between the sampled signals in stage 1 and stage 2 for the purposes of white balancing.
SH buffer array (FIGS. 10C-1 and 10C-2). Plural sample-and-hold (SH) buffers (for example, 1024, 1024A, 1025, 1026, 1027, 1028, 1029 and 1030) are used, in one aspect of the present invention as shown in FIGS. 10C-1 and 10C-2. In one aspect of the present invention, ten buffers may be used. Five buffers are used to sample Vaccess1 208A and five more are used to sample Vaccess2 208B, at different instances of time. Depending on when the voltage is sampled, the SH buffers can be categorized as follows:
Reset SH buffers: At the beginning of stage 1 (when start_s1 1002 goes high), Vaccess1 208A and Vaccess2 208B are sampled and the sampled voltages Vrest1,s1 1014A and Vreset2,s1 1015A are the corresponding reset voltages for the two channels. At the beginning of stage 2 (when start_s2 1032 goes high), the reset voltages Vreset1,s2 1014B and Vreset2,s2 1015B are sampled for two channels. Sampling the reset levels separately for each channel in each stage allows accurate prediction of gain and WB coefficients even in the presence of mismatches or variation in the reset levels from stage 1 to stage 2.
Crossover SH buffers: When Vaccess1 208A or Vaccess2 208B drops by Δ V 1011 and crosses the reference in stage 1 (stop_s1 1020 goes high), voltages Vwb1,s1 1034 and Vwb2,s1 1035A are sampled for channels 1 and 2, respectively. When the signal stop_s2 1033 goes high in stage 2, voltages Vwb1,s2 1034A and Vwb2,s2 1035B are sampled for channels 1 and 2, respectively. The four crossover voltages and the four reset voltages provide sufficient information to find the G1, R, B and G2 pixel responses.
Step SH Buffers: On every f step of exposure counter 1020B in stage 1, i.e. whenever the exposure counter 1020B is incremented, voltages Vaccess1 208A and Vaccess2 208B are sampled. The sampled voltage levels for channels 1 and 2 are called Vs1 1037 and Vs2, 1036 respectively, and are used to calculate the compensation gain. This gain is applied to all pixels in the analog domain when the exposure control alone cannot produce the desired frame brightness. This is the case when MaxExp 1022 has been reached and the frame is still too dark, or when the optimum exposure lies between kN and (k+1)N, where k is an integer. The method for finding the compensation gain is discussed later.
The voltage sampled by each SH buffer should lie within the output range of the buffer. This is guaranteed for all Reset SH Buffers, where the sampled voltage may be a reset level. The voltages sampled by the Crossover SH Buffers and the Step SH Buffers in stage 1 are not lower than ΔV 1011 below the reset level and also lie in the output range of the buffers. For a typical spectral distribution of the incident light, the sampled signals in stage 2 are not more that X times stronger than the sampled signals in stage 1 (for example, X may be equal to 2.5), and thus the foregoing system and method for AE and AWB is immune to saturation effects for incident light with typical spectral distribution.
4) Gain Calculator (FIG. 10D). The purpose of the gain calculator is to find the minimum gain G 1036A for which
GΔVsig≧ΔVdes, (12)
where ΔVsig 1047 and ΔVdes 1048 are two differential signals. As gain G 1036A is increased monotonically in a stepwise fashion, equation (12) will first become true when G 1036A is approximately equal to ΔVsig 1047/ΔVdes 1048. This provides the ratio of two analog signals for calculating the WB coefficients and the compensation gain setting.
To determine gain G 1036A, a clk signal 1046 provides the timing and synchronization for a counter 1043, a Programmable Gain Amplifier (PGA) 1040 and a comparator 1039. Counter 1043 is initially reset to 0 and is then incremented by 1 on every clk signal 1046 edge. Each value of the counter is transformed into a gain setting G 1036A by decoder 1042, which is then fed to PGA 1040.
PGA 1040 amplifies the input signal ΔVsig 1047 by G 1036A. The output 1049 of PGA 1040 goes to one of the two inputs of a differential offset-canceling comparator 1039. The other input to comparator 1039 is the desired signal ΔVdes 1048. Comparator 1039 output stop signal 1050 goes high whenever equation (12) is satisfied. If stop signal 1050 is low and counter 1043 has not overflowed, then counter 1043 is incremented to the next setting, which increases gain G 1036A. At some instance either stop signal 1050 will be high or counter 1043 will overflow. As a result the end signal 1051 will go high, clk signal 1046 will be blocked and counter 1043 will no longer be incremented. The final setting of counter 1043 corresponds to the gain that is closest to ΔVsig 1047/ΔVdes 1048 and can be transferred to a WB register (not shown) or to a compensation gain register. The same or different instance of an identical PGA 1040 and decoder 1042 can be used to apply the necessary gain during frame readout.
The gain calculator is used once at the end of stage 1 to find the compensation gain, and twice at the end of stage 2 to find the two WB coefficients (the third WB coefficient is equal to 1 by definition). During every call, each of the two differential signals ΔVsig 1047 and ΔVdes 1048 is physically connected through appropriate multiplexers (1038 and 1038A) to two single-ended SH buffer output voltages. After each call to the gain calculator the contents of the counter is transferred to the appropriate compensation gain or WB register.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5122881 *Aug 4, 1989Jun 16, 1992Hitachi, Ltd.Solid-state imaging device with an amplifying FET in each pixel and an output capacitor in each rowUS5216493Feb 19, 1992Jun 1, 1993Eastman Kodak CompanyMultipoint digital automatic white balance for a video systemUS5502299Dec 12, 1994Mar 26, 1996Rockwell International CorporationCurrent ratio circuit for multi-color imagingUS5572074Jun 6, 1995Nov 5, 1996Rockwell International CorporationCompact photosensor circuit having automatic intensity range controlUS5619262Nov 9, 1995Apr 8, 1997Olympus Optical Co., Ltd.Solid-state image pickup apparatus including a unit cell arrayUS5734426Nov 15, 1996Mar 31, 1998Omnivision Technologies, Inc.Method of automatic exposure control in a MOS imaging arrayUS5990471 *Jan 13, 1998Nov 23, 1999Sharp Kabushiki KaishaMotion detection solid-state imaging deviceUS6452633Feb 26, 1998Sep 17, 2002Foveon, Inc.Exposure control in electronic cameras by detecting overflow from active pixelsUS6493030Apr 8, 1998Dec 10, 2002Pictos Technologies, Inc.Low-noise active pixel sensor for imaging arrays with global resetUS6580455 *May 5, 1998Jun 17, 2003Pixart Technology, Inc.High definition image sensorUS6791606 *May 9, 2000Sep 14, 2004Eastman Kodak CompanyAuto white balancing apparatus and methodUS7133073 *Feb 2, 2000Nov 7, 2006Dialog Imaging Systems GmbhMethod and apparatus for color interpolationEP1162831A1Jan 10, 2001Dec 12, 2001Symagery Microsystems Inc.Ambient light detection technique for an imaging arrayWO1999057605A1Mar 5, 1999Nov 11, 1999Intel CorpMethod and apparatus for processing a photocurrent in both discrete and continuous time* Cited by examinerNon-Patent CitationsReference1"Instantaneous Automatic Light Control for CMOS Sensors" by Olsen et al, pp. 121-124; Presentation at 2005 IEEE Workshop on Charge-coupled Devices and Advanced Image Sensors, Jun. 9-11, 2005, at Nagano, Japan.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7750278 *Feb 6, 2007Jul 6, 2010Sony CorporationSolid-state imaging device, method for driving solid-state imaging device and cameraUS20080239125 *Mar 26, 2008Oct 2, 2008Commissariat A L'energie AtomiqueImage sensor suitable for operating in subresolution mode* Cited by examinerClassifications U.S. Classification348/223.1, 348/302, 348/308International ClassificationH04N5/374, H04N5/351, H04N5/235, H04N3/14, H04N9/73Cooperative ClassificationH04N5/374, H04N5/347, H04N5/2351, H04N5/37452European ClassificationH04N5/347, H04N5/3745A, H04N5/374, H04N5/235BLegal EventsDateCodeEventDescriptionJul 19, 2012FPAYFee paymentYear of fee payment: 4Jan 17, 2003ASAssignmentOwner name: BIOMORPHIC VLSI, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MILKOV, MIHAIL M.;STANDLEY, DAVID;MITTRA, AMIT;REEL/FRAME:013670/0452Effective date: 20030110RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services