Source: https://patents.google.com/patent/US20070057720A1/en
Timestamp: 2019-09-18 04:11:35
Document Index: 172828467

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

US20070057720A1 - Systems and methods for load detection and correction in a digital amplifier - Google Patents
Systems and methods for load detection and correction in a digital amplifier Download PDF
US20070057720A1
US20070057720A1 US11/211,765 US21176505A US2007057720A1 US 20070057720 A1 US20070057720 A1 US 20070057720A1 US 21176505 A US21176505 A US 21176505A US 2007057720 A1 US2007057720 A1 US 2007057720A1
US11/211,765
US7259618B2 (en
2005-08-25 Application filed by D2Audio LLC filed Critical D2Audio LLC
2005-08-25 Priority to US11/211,765 priority Critical patent/US7259618B2/en
2005-08-25 Assigned to D2AUDIO CORPORATION reassignment D2AUDIO CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HAND, LARRY E., TAYLOR, WILSON E.
2007-03-15 Publication of US20070057720A1 publication Critical patent/US20070057720A1/en
2007-08-21 Publication of US7259618B2 publication Critical patent/US7259618B2/en
2014-04-23 Assigned to Intersil Americas LLC reassignment Intersil Americas LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: D2AUDIO LLC
2014-04-23 Assigned to D2AUDIO LLC reassignment D2AUDIO LLC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: D2AUDIO CORPORATION
This application claims priority to U.S. patent application Ser. No. 10/805,741, entitled “Systems And Methods For Automatically Adjusting Channel Timing,” by Taylor, et al., filed Mar. 22, 2004, which claims priority to: U.S. Provisional Patent Application No. 60/456,421, entitled “Output Device Switch Timing Correction,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,414, entitled “Adaptive Anti-Clipping Protection,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,430, entitled “Frequency Response Correction,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,429, entitled “High-Efficiency, High-Performance Sample Rate Converter,” by Andersen, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,422, entitled “Output Filter, Phase/Timing Correction,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,428, entitled “Output Filter Speaker/Load Compensation,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,420, entitled “Output Stage Channel Timing Calibration,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,427, entitled “Intelligent Over-Current, Over-Load Protection,” by Hand, et al., filed Mar. 21, 2003; each of which is fully incorporated by reference as if set forth herein in its entirety.
Another problem with prior art systems and methods is that the performance and quality characteristics of the remainder of the signal processing system vary with the applications in which they are used. Because the exact implementation in each system and the end-user applications are not deterministic, each system requires a point solution. These point solutions are not flexible, scalable or transportable across applications.
One embodiment of the invention is implemented in a Class D pulse width modulated (PWM) amplifier. In this embodiment, a digital PCM test signal is generated. This test signal is processed by the amplifier to produce a corresponding analog audio output signal that is used to drive a speaker. A sense resistor placed in series with the speaker is used to generate a test voltage that is compared to a reference voltage. When the test voltage reaches the reference voltage, the current through the sense resistor (hence the speaker) is at a known level, so the value of the digital test signal is noted. The impedance of the speaker is then determined from the test signal value and the speaker current.
FIG. 1 is a functional block diagram illustrating a PWM amplification system in accordance with one embodiment of the invention.
FIG. 2 is a more detailed diagram illustrating a digital PWM amplifier in accordance with one embodiment.
FIG. 5 is a functional block diagram illustrating a digital PWM amplifier in accordance with one alternative embodiment.
As described herein, various embodiments of the invention comprise systems and methods for detecting the impedance of an output load coupled to a digital amplifier and compensating for changes in the frequency response of the amplifier. One embodiment is implemented in a Class D pulse width modulated (PWM) amplifier. A mechanism is provided for determining the impedance of a speaker that is coupled to the output of the amplifier. The processing of the digital audio signal is then adjusted if necessary to optimize the frequency response of the amplifier for the specific impedance of the speaker.
Referring to FIG. 1, a functional block diagram illustrating a PWM amplification system in accordance with one embodiment of the invention is shown. As depicted in the figure, PWM amplification system 100 comprises an internal processor 110, a delta-sigma converter 120, a PCM-to-PWM modulator 130, a Driver 150, an output stage 160, a speaker 170 and a feedback subsystem 180. Delta-sigma converter 120 and PCM-to-PWM modulator 130 form a Class D modulator 140.
The structure of the amplifier in FIG. 1, with the exception of feedback subsystem 180, is very similar to a more conventional digital PWM amplifier. As in conventional amplifiers, the processing of digital audio signals by the amplifier to produce analog output signals varies somewhat with frequency. Ideally, the frequency response of the amplifier would be flat across all audio frequencies. In practice, however, it may be difficult to achieve this ideal. Various types of processing (e.g., filtering) of the digital data are employed in an attempt to optimize (flatten) the frequency response of the amplifier. Typically, however, the processing performed by the amplifier is optimized for a point solution that incorporates a specific speaker impedance. If a speaker having a higher impedance is used, the frequency response tends to increase at higher frequencies. If a speaker having a lower impedance is used, the frequency response tends to droop at higher frequencies. The present embodiment therefore incorporates a mechanism to determine the impedance of the speaker and to adjust the frequency response if necessary to correspond to this impedance.
Referring to FIG. 2, a more detailed diagram illustrating a digital PWM amplifier in accordance with one embodiment is shown. As depicted in this figure, the processor of the amplifier is implemented using a digital signal processor (DSP) 210. DSP 210 includes a test signal generator 211. Test signal generator 211 is configured to generate pulse code modulated (PCM) test signals that are provided to PWM engine 240. PWM engine 240 converts the stream of PCM audio data that is received from DSP 210 into PWM audio data. The PWM data is provided to driver/level shifter 250, which produces a pair of signals to drive high-side and low-side switching transistors 261-264 in the output stage. Transistors 261-264 are switched on and off to allow current to flow through speaker 270, as well as through LC filters (consisting of inductors 265 and 267, and capacitors 266 and 268) on either side of the speaker. The feedback mechanism in this embodiment consists of a resistor 281 positioned in series with speaker 270, and a differential amplifier 282. Differential amplifier 282 receives the voltage across resistor 281 and a reference voltage as inputs, and provides an output signal indicating which of the voltages is higher to DSP 210.
The amplifier of FIG. 2 operates in essentially the following manner. Signal generator 211 generates a test signal that consists of a sine wave having a particular frequency and a particular amplitude. As noted above, the test signal consists of digital PCM data. The PCM test signal is converted by PWM engine 240 into a PWM signal, which is used by driver/level shifter 250 to generate high-side and low-side switching signals. These switching signals are essentially inverses of each other, aside from minor timing differences that need not be discussed here. When the high-side signal is asserted and the low-side signal is not, transistors 261 and 264 are switched on, and transistors 262 and 263 are switched off. Current therefore flows from the voltage source through transistor 261, inductor 265, speaker 270, inductor 267, transistor 264 and resistor 281. When the low-side signal is asserted and the high-side signal is not, transistors 262 and 263 are switched on, and transistors 261 and 264 are switched off. Current then flows from the voltage source through transistor 263, inductor 267, speaker 270, inductor 265, transistor 262 and resistor 281.
It is apparent that, whether the high-side or low-side signal is asserted (i.e., whether current is flowing in one direction or the other,) the current through speaker 270 also flows through resistor 281. The size of resistor 281 is chosen to be small (e.g., 50 mΩ) in order to minimize the effect of the resistor in the circuit. Since the voltage across resistor 281 is equal to the current through the resistor times the resistance of the resistor (i.e., V=IR,) the voltage across the resistor is proportional to the current through the resistor (and through speaker 270.) Thus, when the voltage across resistor 281 reaches a threshold level, the current through the resistor and speaker 270 is at a corresponding threshold current level. The threshold voltage level across resistor 281 is determined by the reference voltage that is input to differential amplifier 282. When the voltage across resistor 281 is less than the reference voltage, the signal at the output of differential amplifier 282 is not asserted. When the voltage across resistor 281 is greater than the reference voltage, the signal at the output of differential amplifier 282 is asserted. Consequently, when the voltage across resistor 281 is equal to the reference voltage, the output signal of differential amplifier 282 transitions from low to high (if the voltage across resistor 281 is increasing) or from high to low (if the voltage across resistor 281 is decreasing.)
The output signal from differential amplifier 282 is provided to DSP 210. When the output signal of differential amplifier 282 transitions from low to high (or from high to low,) DSP 210 determines the value of the test signal produced by signal generator 211. The value of the test signal at the transition corresponds to the known speaker current, so it can be used to determine the impedance of the speaker. More specifically, the impedance of the speaker is calculated by multiplying a proportionality constant times the ratio of the PCM test signal value and the voltage across resistor 281 (which is equal to the reference voltage.)
It should be noted that the impedance of the speaker is frequency-dependent. Consequently, the determination of the speaker impedance is performed with a test signal that has a constant frequency and a variable amplitude. It is preferred that the test signal be a sine wave having the selected frequency. The amplitude of the test signal is initially low and is increased until the voltage drop across resistor 281 matches the reference voltage, and the corresponding test signal value is determined. The PCM test signal value is then used to determine the impedance of the speaker at the frequency of the test signal.
The method implemented by the system of FIG. 2 is summarized in the flow diagram of FIG. 3. As shown in FIG. 3, a PCM test signal is first generated (block 310.) As noted above, the test signal is preferably a sine wave having a fixed frequency. The test begins with the test signal at an initial amplitude, but the amplitude will be varied as described below. The digital PCM test signal is processed by the PWM amplifier (block 320) to generate an analog signal suitable for driving a speaker. This processing includes converting the PCM signal to a PWM signal and driving an output stage with the PWM signal to produce the analog output signal. The PWM amplifier may also be configured to filter the audio signal at various stages within the amplifier.
The analog output signal is then used to drive the speaker (block 330,) and the current through the speaker is monitored to determine whether the current has reached/exceeded a threshold level (block 340.) In the embodiment of FIG. 2, this is achieved by comparing the voltage across a sense resistor that is placed in series with the speaker to a reference voltage. The difference between the sense resistor voltage and the reference voltage is amplified to produce a binary signal that is low when the sense resistor voltage is less than the reference voltage and high when the sense resistor voltage is greater than the reference voltage. The transition of this binary signal from low to high indicates that the sense resistor voltage is equal to the reference voltage. If the binary signal is low, the amplitude of the test signal is increased slightly (block 350.) The increased-amplitude signal is processed by the PWM amplifier (block 320) and used to drive the speaker (block 330.) This process continues until the sense resistor voltage is greater than the reference voltage.
When the sense resistor voltage is greater than the reference voltage, the speaker current is determined to be equal to (or just greater than) a threshold level (block 340.) This is indicated by the transition of the binary signal from low to high. The binary signal is provided to the DSP and, when the signal transitions from low to high, the DSP records the value of the PCM signal at the test signal generator that caused the transition (block 360.) This may be accomplished, for example, by generating an interrupt when the transition is detected. The corresponding value of the PCM signal corresponds to the known threshold current level through the speaker. The value of the PCM signal and the threshold current level through the speaker are then used to calculate the impedance of the speaker (block 370.) Based upon the calculated impedance of the speaker, the response of the amplifier can be adjusted (e.g., to compensate for high-frequency peaking or drooping.)
Referring to FIG. 5, a functional block diagram illustrating a digital PWM amplifier in accordance with one alternative embodiment is shown. In this figure, a DSP 510 includes a test signal generator 511 which is configured to generate pulse code modulated (PCM) test signals. Rather than being provided directly to PWM engine 540, the PCM signal is provided to a variable gain block 530. Variable gain block 530 adjusts the gain of the PCM signal according to a control signal received from integrator 520. the gain-adjusted PCM signal is then provided to PWM engine 540, which converts the stream of PCM audio data into PWM audio data. The PWM data is provided to driver/level shifter 550, which produces a pair of signals to drive output stage/speaker 560.
This embodiment forms a closed loop system that regulates the output signal level as a function of the output impedance. The lower the impedance, the lower the output signal level. With a continuous test signal, the control voltage becomes representative of the output impedance. The control loop provides real-time averaging over thousands of measurements, which greatly increases the accuracy and repeatability of the current (or impedance) measurement. This control loop also has the advantage of requiring minimal maintenance on the part of the DSP.
This embodiment makes use of several ideas to reduce the effects of variability in the system. One of the ideas makes use of the fact that the current through the sense resistor is trapezoidal. (“Trapezoidal” as used here refers to the fact that the speaker current passes through an inductive element that causes the current to increase or decrease linearly, as shown in FIG. 6.) The current therefore has a low frequency audio component and a high frequency ripple component due to the LC filter in the output. This at first appears to be problematic because, at very low levels of audio, the magnitude of the ripple voltage is much greater than the audio contribution. The amplifier, however, employs a debounce mechanism that causes the over-threshold signal to be passed to the DSP only if the signal is asserted by the comparator for a minimum interval (a selected amount of time or number of cycles.) As a result, the signal does not “bounce” between asserted and deasserted states. By carefully adjusting the debounce counters that process the over-threshold signal, audio components of the signal can be discriminated from the ripple voltage even when the reference voltage is set well below the level of the ripple voltage. It should be noted that the same debounce mechanism used for this purpose during testing used for other purposes during normal operation of the amplifier.
Only a few of the possible embodiments of the invention have been discussed in this disclosure. Many alternative embodiments are possible, and many will be apparent to persons of skill in the art of the invention upon reading this disclosure. It should also be noted that the various components of the systems described above should be construed broadly to include comparable components. For instance, while the foregoing description refers to speakers, this should be construed to include other types of output loads (e.g., subsequent amplifiers) as well. Similarly, references to the DSP should be construed to include other types of processors and/or control circuitry, references to the differential amplifier should be construed to include other types of comparators, and so on.
3. The method of claim 1, further comprising repeating (a)-(f) with multiple digital test signals having different frequencies and one or more threshold levels of current through the load, and calculating an impedance profile of the load based on the threshold levels of current through the load and the corresponding values of the digital test signals
4. The method of claim 3, further comprising comparing the calculated impedance profile of the load to a library of impedance profiles and selecting one of the impedance profiles in the library that matches the calculated impedance profile of the load
5. The method of claim 4, further comprising implementing a set of operating parameters in the digital amplifier that is associated with the selected one of the impedance profiles in the library
6. The method of claim 1, wherein the digital test signal comprises a pulse code modulated (PCM) signal and converting the digital test signal to the analog signal comprises converting the PCM signal to a pulse width modulated (PWM) signal and converting the PWM signal to the analog signal
7. The method of claim 6, wherein detecting the threshold level of current through the load comprises comparing a voltage across a sense resistor that is in series with the load to a reference voltage that is equal to a resistance of the sense resistor times the threshold level of current
8. The method of claim 7, further comprising asserting a binary signal when the voltage across the sense resistor exceeds the reference voltage
9. The method of claim 7, further comprising asserting an interrupt when the voltage across the sense resistor exceeds the reference voltage
comparing a voltage across the sense resistor to a first reference voltage,
wherein the first reference voltage is equal to a resistance of the sense resistor times a first threshold level of current,
a digital test signal generator;
the reference voltage generator is configured to generate a first reference voltage equal to a resistance of the sense resistor times a first threshold level of current below a maximum current level, and
the processor is configured to calculate the impedance of the load based on the threshold level of current and the value of the digital test signal corresponding to the transition in the binary signal; and
US11/211,765 2005-08-25 2005-08-25 Systems and methods for load detection and correction in a digital amplifier Active 2025-10-05 US7259618B2 (en)
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US20070057720A1 true US20070057720A1 (en) 2007-03-15
US7259618B2 US7259618B2 (en) 2007-08-21
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