Source: http://www.google.com/patents/US6337232?dq=4168396
Timestamp: 2016-06-26 21:29:42
Document Index: 559871419

Matched Legal Cases: ['arts 3', 'arts 6', 'art 6', 'art 13', 'art 17', 'art 16']

Patent US6337232 - Method of fabrication of a crystalline silicon thin film semiconductor with ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method for forming a semiconductor device is disclosed. A semiconductor film comprising silicon is formed on a substrate. The semiconductor film is crystallized. The crystallized semiconductor film is patterned into a marker part for aligning a mask and an insular semiconductor part at the same time....http://www.google.com/patents/US6337232?utm_source=gb-gplus-sharePatent US6337232 - Method of fabrication of a crystalline silicon thin film semiconductor with a thin channel regionAdvanced Patent SearchPublication numberUS6337232 B1Publication typeGrantApplication numberUS 09/325,572Publication dateJan 8, 2002Filing dateJun 4, 1999Priority dateJun 7, 1995Fee statusLapsedAlso published asUS6541795, US20020055209Publication number09325572, 325572, US 6337232 B1, US 6337232B1, US-B1-6337232, US6337232 B1, US6337232B1InventorsNaoto Kusumoto, Yasuhiko Takemura, Hisashi OhtaniOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (28), Non-Patent Citations (11), Referenced by (72), Classifications (26), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetMethod of fabrication of a crystalline silicon thin film semiconductor with a thin channel region
US 6337232 B1Abstract
A method for forming a semiconductor device is disclosed. A semiconductor film comprising silicon is formed on a substrate. The semiconductor film is crystallized. The crystallized semiconductor film is patterned into a marker part for aligning a mask and an insular semiconductor part at the same time. A part of the semiconductor film to become a channel formation region is thinned to a thickness 300 Å or less.
forming a semiconductor film comprising silicon on an insulating surface; crystallizing said semiconductor film; and thinning at least a portion of the crystallized semiconductor film to become a channel-forming region to a thickness of 300 Å or less; patterning the crystallized semiconductor film into a marker part for aligning a mask and an insular semiconductor part at the same time. 2. A method for forming a semiconductor device comprising the steps of:
forming a semiconductor film comprising silicon on an insulating surface; crystallizing said semiconductor film; thinning at least a portion of the crystallized semiconductor film to become a channel-forming region to a thickness of 300 Å or less; patterning the crystallized semiconductor film into a marker part for aligning a mask and an insular semiconductor part at the same time; and forming a transistor comprising a source region, a drain region and a channel-forming region formed in said insular semiconductor part, said channel-forming region being formed between said source region and said drain region. 3. A method for forming a semiconductor device comprising the steps of:
forming a semiconductor film comprising silicon on an insulating surface; crystallizing said semiconductor film; thinning at least a portion of the crystallized semiconductor film to become a channel-forming region to a thickness of 300 Å or less; patterning the crystallized semiconductor film into a marker part for aligning a mask and an insular semiconductor part at the same time; forming a gate insulating film over said marker part and said insular semiconductor part; forming a gate electrode on said gate insulating film; and forming a source region and a drain region by introducing a dopant into said insular semiconductor part using a mask comprising said gate electrode to thereby form a channel-forming region adjacent to said gate electrode and between said source region and said drain region. 4. A method for forming a semiconductor device comprising the steps of:
forming a semiconductor film comprising silicon on an insulating surface; crystallizing said semiconductor film by heat treatment; irradiating the crystallized semiconductor film with a laser light; thinning at least a portion of the crystallized semiconductor film to become a channel-forming region to a thickness of 300 Å or less after said irradiating step; patterning the crystallized semiconductor film into a marker part for aligning a mask and an insular semiconductor part at the same time after said irradiating step; forming a gate insulating film over said marker part and said insular semiconductor part; forming a gate electrode on said gate insulating film; and forming a source region and a drain region by introducing a dopant into said insular semiconductor part using a mask comprising said gate electrode to thereby form a channel-forming region adjacent to said gate electrode and between said source region and said drain region. 5. A method for forming a semiconductor device comprising the steps of:
forming a semiconductor film comprising silicon on an insulating surface; crystallizing said semiconductor film; thinning at least a portion of the crystallized semiconductor film to become a channel-forming region to a thickness of 300 Å or less; patterning the semiconductor film into a marker part for aligning a mask and an insular semiconductor part which includes said portion to become said channel-forming region, at the same time; forming a gate insulating film over said marker part and said insular semiconductor part; forming a gate electrode on said gate insulating film; and forming a source region and a drain region by introducing a dopant into said insular semiconductor part using a mask comprising said gate electrode to thereby form said channel-forming region adjacent to said gate electrode and between said source region and said drain region. 6. A method for forming a semiconductor device comprising the steps of:
forming a semiconductor film comprising silicon on an insulating surface; crystallizing said semiconductor film; thinning at least a portion of the crystallized semiconductor film to become a channel-forming region to a thickness of 300 Å or less; patterning the semiconductor film into a marker part for aligning a mask and an insular semiconductor part which includes said portion to become said channel-forming region, at the same time; forming a gate insulating film having a thickness of 500 Å or less over said marker part and said insular semiconductor part; forming a gate electrode on said gate insulating film; and forming a source region and a drain region by introducing a dopant into said insular semiconductor part using a mask comprising said gate electrode to thereby form said channel-forming region adjacent to said gate electrode and between said source region and said drain region. 7. The method of claim 1 further comprising the step of thinning the crystallized semiconductor film before said patterning step.
8. The method of claim 2 further comprising the step of the thinning of the crystallized semiconductor film before said patterning step.
9. The method of claim 4 further comprising the step of the thinning of the crystallized semiconductor film before said patterning step.
10. The method of the claim 1 wherein the crystallization is promoted by an element for promoting crystallization is promoted by an element for promoting crystallization of silicon.
11. The method of the claim 2 wherein the crystallization is promoted by an element for promoting crystallization is promoted by an element for promoting crystallization of silicon.
12. The method of the claim 3 wherein the crystallization is promoted by an element for promoting crystallization is promoted by an element for promoting crystallization of silicon.
13. The method of the claim 4 wherein the crystallization is promoted by an element for promoting crystallization is promoted by an element for promoting crystallization of silicon.
14. The method of the claim 5 wherein the crystallization is promoted by an element for promoting crystallization is promoted by an element for promoting crystallization of silicon.
15. The method of the claim 6 wherein the crystallization is promoted by an element for promoting crystallization is promoted by an element for promoting crystallization of silicon.
16. The method of claim 10 wherein said element is nickel, palladium, platinum, cobalt or iron.
17. The method of claim 11 wherein said element is nickel, palladium, platinum, cobalt or iron.
18. The method of claim 12 wherein said element is nickel, palladium, platinum, cobalt or iron.
19. The method of claim 13 wherein said element is nickel, palladium, platinum, cobalt or iron.
20. The method of claim 14 wherein said element is nickel, palladium, platinum, cobalt or iron.
21. The method of claim 15 wherein said element is nickel, palladium, platinum, cobalt or iron.
This application is a divisional application of application Ser. No. 08/844,856, filed Apr. 23, 1997, now U.S. Pat. No. 5,940,690, which is a divisional application of application Ser. No. 08/487,166, filed Jun. 7, 1995, now U.S. Pat. No. 5,656,825.
In the present invention, two methods can be employed for the etching process described above when silicon is used as a semiconductor. The first method is characterized in that a process in which a silicon film is slightly oxidized to form a silicon oxide film and this is etched and repeated as many times as necessary. This method is excellent in controllability of etching depth as compared with a method in which a silicon film is directly dissolved by etching.
After forming a thin silicon oxide film by the above method, the silicon oxide film formed on the surface is etched by exposing the silicon film to an etchant which does not etch silicon (for example a solution of a hydrogen fluoride such as 1% hydrofluoric acid or the like). This results in causing the silicon film to get thin only by the oxidized part. The problem with this method is that the necessity to repeat the process means that a longer time is taken as the depth to be etched becomes greater.
FIG. 5 shows a ID-VG characteristic example of a TFT according to the present invention (Preferred Embodiment 1);
According to researches by the present inventors, a concentration of nickel of 1 ppm or more in the acetate solution is sufficient for practical use. A nickel acetate layer having an average thickness of 20 Å could be formed on the surface of the amorphous silicon film after spin drying by carrying out this coating process of the nickel acetate solution once or more times. This layer does not necessarily form a complete film. The layer can be formed in the same manner using other nickel compounds. Thus, a nickel acetate film 104 was formed. (FIG. 1(A)).
Then, as shown in FIG. 1(B), the crystalline silicon film was etched to a film thickness of 150 to 300 Å. This etching process was carried out by first oxidizing the surface of the crystalline silicon film with a mixed solution of hydrogen peroxide and ammonia to form silicon oxide and then removing the silicon oxide film with hydrofluoric acid. Since about 50 to 120 Å is etched each time in this process, the same operation was repeated several times to achieve etching of the required thickness. A mixed solution prepared by mixing hydrogen peroxide, ammonia and water in the ratio 5:2:2 was used, but solutions having other mixing ratios can be used. Besides these, nitric acid may be used, and the surface of the crystalline silicon film may be etched with hydrofluoric acid after being thermally oxidized.
Next, the crystalline silicon film 105 thus obtained was etched by dry etching to form an insular region 106 (insular silicon film). This insular silicon film 106 constitutes an active layer in a TFT. Then, as a gate insulating film, a silicon oxide film 107 having a film thickness of 200 to 1500 Å, for example 500 A was formed by sputtering.
As shown in FIG. 1(C), an aluminum (containing Si 1 wt % or Sc 0.1 to 0.3 wt %) film having a thickness of 1000 Å to 3 mm, for example 5000 Å was formed by sputtering, and this was patterned to form a gate electrode 108. Next, the substrate was dipped in a 1 to 3% ethylene glycol solution of tartaric acid of pH about 7, and anodic oxidation was carried out with platinum as a cathode and the aluminum gate electrode 108 as an anode. Anodic oxidation was finished after initially raising the voltage up to 220 V at a fixed current and maintaining this voltage for one hour. Thus, an anodic oxide film 109 having a thickness of 1500 to 3500 Å, for example 2000 Å was formed.
As illustrated in FIG. 1(D), an impurity (phosphorus in the present preferred embodiment) was then injected into the insular silicon film 106 by ion doping with the gate electrode 108 and the anodic oxide film 109 as masks. Phosphine gas (PH3) was used as the doping gas. On this occasion, the dose amount was set at 1�1013 to 5�1015 atoms cm−2, and the accelerating voltage to 10 to 90 kV, for example, the dose amount to 5�1014 atoms cm−2 and the accelerating voltage to 80 kV. This resulted in an N type impurity region 110 (source/drain) being formed.
Next, as illustrated in FIG. 1(E), a silicon oxide film 111 was formed as an interlayer insulating film to a thickness of 3000 Å by plasma CVD.
The interlayer insulating film 111 and the gate insulating film 107 were then etched to form contact holes to the source and the drain. Then, as shown in FIG., 1(F), a titanium nitride film thickness 1000 Å and an aluminum film (thickness 5000 Å) were formed by sputtering and etched to form source and drain electrodes 112 and 113, whereby the TFT circuit was completed.
The leak current was measured in further detail and is shown in FIG. 7. In particular, it can be seen that the leak current at VD=10V is markedly reduced by thinning the active layer. This was desirable as a switching transistor for an active matrix circuit of which low leak current is required when a high voltage is applied across the source/drain.
To describe this problem in detail, conventionally, in a process for forming elements by superposing films on a transparent substrate, a pattern of some film has generally been made a marker at an initial stage and used, in a later process for aligning the mask. A silicon film was generally used as a film for forming the marker in the top gate type TFT. That is, because the pattern formation which is done at first is the formation of an insular region in the process for the top gate type TFT. In forming this insular region, the marker for adjusting the mask is formed at the same time. Thereafter, the marker which is formed on this occasion is used in all the processes for aligning the mask. This marker caused several problems as the silicon film got thinner. In particular, when patterns were formed on an aluminum film, it was necessary to distinguish a level difference between the marker part and the aluminum film to align the mask, but when the silicon film was thinned to 500 Å or less, it became impossible to confirm a sufficient level difference, and failure became liable to occur in the mask-adjusting process.
As illustrated in FIG. 2(A), in addition to improvement in the TFT characteristics, an improved method will be shown as well in the aspect of mask alignment. The present preferred embodiment is shown in FIG. 2. First, a silicon oxide film 202 was formed to 1000 to 5000 Å, for example 2000 Å on a transparent glass substrate 201 as a base oxide film by sputtering. This silicon oxide film is provided in order to prevent impurities from diffusing from the glass substrate. Then, an amorphous silicon film was formed to 500 to 1500 Å, for example 800 Å by plasma CVD. It is for securing a thickness which makes it possible to sufficiently confirm the marker during mask alignment that the thickness of the silicon film was set to 800 Å here.
Then, a photoresist 205 was formed on the silicon oxide film and patterning was carried out, whereby a mask was formed so that adjacency of the channel region formed could be etched. A cross-sectional drawing of this state is shown in FIG. 2(B), and a view seen from above in FIG. 4(A). In the present preferred embodiment, two patterns consisting of first pattern and a second pattern were formed and compared. The arrow shown in FIG. 4(A) shows the direction of the cross section in FIG. 2.
Thereafter, as illustrated in FIG. 2(C), the silicon film was etched in the same manner as that in Preferred Embodiment 1 to form a film to a thickness of 150 to 300 Å in the periphery of a channel-forming region. On this occasion, oxidation with a mixed solution of hydrogen peroxide and ammonia and etching with 1% hydrofluoric acid were alternately carried out to etch the silicon film to the required thickness.
Then, the photoresist 205 and the silicon oxide film 204 were removed. Next, the crystalline silicon film thus obtained was etched to form an insular region 206 (insular silicon film) for forming a TFT and the markers 207 and 208 for aligning a mask. A view seen from above at this time is shown in FIG. 4(B). In this drawing, the pattern of thinning of the above silicon film is shown as well in dotted lines. In the first pattern (FIG. 4(B), left side), this resulted in the shape of the region of the thin silicon film becoming almost an H form. In the second pattern, the shape of the region of the thin silicon film was rectangular. In the second pattern, the constricted part of the insular region was sometimes broken by abnormal etching when etching the insular region was etched, but such a phenomenon was not observed in the first pattern.
Thereafter, as shown in FIG. 2(D), a silicon oxide film 209 having a film thickness of 200 to 1500 Å, for example 1000 Å was formed as a gate insulating film by plasma CVD.
A polycrystalline silicon film of thickness 1000 Å to 3 μm, for example 5000 Å and doped with phosphorus was then formed by reduced pressure CVD, and this was patterned to form the pattern of a photoresist corresponding to a gate electrode interconnector. The marker 207 was used for this. Then, the polycrystalline silicon film was etched with the pattern of this photoresist to form a gate electrode 210. A view seen from above at this time is shown in FIG. 4(C).
Then, as shown in FIG. 2(E), an impurity (phosphorus in the present example) was injected in a self-aligned manner into the insular silicon film 206 with the gate electrode 210 as a mask by ion doping. PH3 was used as the doping gas. On this occasion, the dose amount was set to 1�1013 to 5�1015 atoms cm−2, and the accelerating voltage to 10 to 90 kV, for example the dose amount to 1�1015 atoms cm−2 and the accelerating voltage to 80 kV. This resulted in an N type impurity region 211 (source/drain) being formed.
A silicon oxide film 212 was then formed to a thickness of 3000 Å as aninterlayer insulating film by reduced pressure CVD.
The interlayer insulating film 212 and the gate insulating film 209 were etched to form contact holes to the source and the drain. On this occasion, the contact holes were easy to form unlike Preferred Embodiment 1, because the source and drain regions were thick, at 800 Å. Then, an aluminum film was formed by sputtering and patterned to form the pattern of a photoresist corresponding to a source/drain electrode interconnector. The marker 208 was used for this. As shown in FIG. 2(F), the aluminum film was then etched with the pattern of this photoresist to form source/drain electrode/interconnectors 213 and 214.
After forming the TFT, hydrogenated treatment at 200 to 400� C. may further be carried out.
Since the TFT thus obtained was thin in the periphery of the channel-forming region in the semiconductor layer as compared with conventional TFTS, a TFT having no big difference from Preferred Embodiment 1 in the characteristics such as electric field effect mobility, threshold voltage, leak current and the like could be obtained. On the other hand, since the silicon film of the marker had a sufficient thickness, failure in the mask alignment could be reduced. Also, since the source and the drain had a thickness of 800 Å, sheet resistance was sufficiently low. Since the source and the drain had a sufficient thickness, a defective contact did not occur at the source and the drain even though a titanium nitride film was not provided.
Thereafter, as shown in FIG. 3(A), a nickel-containing layer of several to several tens of Å was formed on the amorphous silicon film by spin coating in the same manner as that in Preferred Embodiment 1. After forming the nickel-containing layer, heat treatment was carried out at 550� C. for 4 hours in a heating furnace in a nitrogen atmosphere to crystallize the layer. Irradiation with a KrF excimer laser ray having an energy density of 200 to 350 mJ/cm2 was then carried out to improve crystallization.
Next, as shown in FIG. 3(B), a mask was formed on the crystalline silicon film 303 thus obtained in the same manner as that in Preferred Embodiment 2, and only the region of an active matrix circuit was thinned to form a thin silicon region 303′. The thickness of the silicon film in the region 303′ was set to 300 Å. Etching was carried out by the same method as that in Preferred Embodiment 2.
Then, as shown in FIG. 3(C), the crystalline silicon film thus obtained was patterned to form insular regions 304, 305 and 306 (insular silicon film) . These insular regions 304, 305 and 306 are the active layers in a TFT. The former two are used for a circuit of a shift register in a peripheral driving circuit, and the latter is used for a pixel TFT for the active matrix circuit. Further, a silicon oxide film 307 having a film thickness of 200 to 1500 Å, for example 1000 Å was formed as a gate insulating film 307 by plasma CVD.
Then, as shown in FIG. 3(D), impurities were self-alignedly injected into the insular silicon films 304, 305 and 306 by ion doping with the gate electrodes 308, 309 and 310 as a mask. On this occasion, phosphorus was injected into the front surface with phosphine gas (PH3) as the doping gas to form N type impurity regions 311, 312 and 313.
Then, as shown in FIG. 3(E), a part where an N channel type TFT was formed was covered with a photoresist 314, and boron was injected into a part where a P channel type TFT was formed with diborane (B2H6) as the doping gas, causing the N type impurity region 311 to be reversed, whereby a P type impurity region 315 was formed. Here, the dose amount of phosphorus was set to 2 to 8�1015 atoms cm2, the accelerating voltage to 80 kV, the dose amount of boron to 4 to 10�1015 atoms cm−2, and the accelerating voltage to 65 kV.
The interlayer insulating film 316 and the gate insulating film 307 were then etched to form contact holes to the source and the drain. Then, as shown in FIG. 3(F), an aluminum film was formed by sputtering, and patterned to form source and drain electrodes 317, 318 and 319.
Lastly, a silicon nitride film having a thickness of 2000 to 6000 Å, for example 3000 Å was formed as a passivation film 320 by plasma CVD, and this, the silicon oxide film 316 and the gate insulating film 307 were etched to form contact holes to the impurity region 313. Then, as shown in FIG. 3(G), an indium tin oxide film (ITO film) was formed and etched to form a pixel electrode 321.
Next, as shown in FIG. 8(A), a mask was formed on the crystalline silicon film 403 thus obtained in the same manner as that in Preferred Embodiment 2, and a channel-forming region in an active matrix circuit and the periphery of all the TFT-forming regions were thinned to form a thin silicon region 403′. The thickness of the silicon film in the thin silicon region was set to 300 Å. Etching was carried out by the same method as that in Preferred Embodiment 2. The peripheral region of the insular region was thinned here to prevent a periphery which forms a channel region from being excessively etched in forming an insular region in a later process.
The effects of the above will be briefly explained with reference to FIG. 10. It is shown in FIGS. 10(A) to (D) that the periphery of the insular region was formed without thinning it as was the case with Preferred Embodiment 2. FIGS. 10(A) and (B) show the state before the silicon film is etched. In the same drawings, a region 2 which has been thinned to a thickness of 300 Å is formed on a region 1 having a thickness of 600 Å by the same thinning process as that described above. The oblique line parts 3 in the drawings show the pattern of the insular region 2, and the parts excluding this are to be etched. Etching is promoted here.
First, the state after which the silicon film was etched by 300 Å is shown in FIG. 10(C). At this time, since the silicon films are not etched in the region of the parts 6 and 7 where the insular regions are formed, they have the same film thicknesses (each 300 Å and 600 Å) as before. Here, the region 6 is a region where a gate electrode will be formed later, and a small level difference in the insular region is desired. On the other hand, in the region 1 having a thickness of 600 Å in FIG. 10(B), the silicon film is etched to be thinned to a silicon region 4 having a thickness of about 300 Å.
On the other hand, the region 2 having a thickness of 300 Å in FIG. 10(B) has the whole silicon film etched, and a surface 5 of the base oxide film exposed, as shown in FIG. 10(C). However, the silicon region 4 and the regions 6 and 7 are still connected and require further etching.
Further, etching of the silicon film by 300 A provides the state shown in FIG. 10(D). In FIG. 10(C), the region 4 where the silicon film of 300 Å remained has the whole silicon film just etched, and a base oxide film surface 9 is exposed. However, the base oxide film surface, region 15 as illustrated in FIG. 10(C), is etched more deeply in the base oxide layer and is shown as region 10 in FIG. 10(D). Accordingly, a level difference between the part 6 where the thickness was 300 Å among the insular regions 8 and the base oxide film has at least about 400 Å even in the preferred condition that an etching ratio of silicon to silicon oxide is 3:1. This level difference varies according to the selection ratio of silicon to silicon oxide in etching. While the insular region was thinned, the level difference was hardly improved, and it was difficult to make, the gate insulating film thinner (for example, 500 Å or less).
According to the present-preferred embodiment, the above point can be improved by thinning an insular region periphery. The aspect of the present preferred embodiment is shown in FIGS. 10(E) to (G) . Similarly to FIG. 10(A), a silicon region 11 having a thickness of 600 Å is thinned to provide a silicon region 12 having a thickness of 300 Å. The stippled regions illustrating part 13 is the pattern of the insular region. As can be seen illustrated in FIG. 10(F), the whole periphery of the insular region 13 is turned to a thinned silicon film.
Promoting etching in this state causes a base silicon oxide surface 15 to be exposed at the time when etching is done by 300 Å. On that occasion, the thicknesses of part 17 which had a thickness of 600 Å and a part 16 which had a thickness of 300 Å in the insular region remained as they were. The peripheral region of the insular region is just in the state that the whole silicon film has been etched and in the state that it is separated from a circumferential silicon region 14. Thus, the insular region is completed. The silicon region 14 was a silicon region having a thickness of 600 Å in FIG. 10(F), and the etching thereof makes the thickness about 300 Å. To consider a level difference, the level difference between a region 16 on which a gate electrode is formed and the base oxide film surface has just a thickness corresponding to that of the region 16 (that is, 300 Å), and forming thereon a gate insulating film having a thickness of 600 Å provides no problems.
With respect to thinning of a silicon film in the preferred embodiment described above, the film thickness was reduced only to a half. If the film thickness is reduced to, for example, � or less, the effect provided by thinning the peripheral part of the insular region as is the case with the present preferred embodiment is marked. For example, to consider the case where a silicon film of 800 Å is thinned to 200 Å, in the case of Preferred Embodiment 2, a level difference is 350 Å obtained by adding the depth 150 Å of silicon oxide which was overetched to 200 Å even in a very preferred case that the etching selection ratio of silicon to silicon oxide is 4:1. In the case of the present preferred embodiment, the level difference is 200 Å, and the level difference is larger by 75% in Preferred Embodiment 2 than in the present preferred embodiment.
Then, as shown in FIG. 8(B), an aluminum film having a thickness of 1000 Å to 3 μm, for example, 5000 Å was formed by sputtering, and photoresist was formed by spin coating. Forming an aluminum oxide film having a thickness of 100 to 1000 Å by anodic oxidation before forming the photoresist improves the adhesion of the photoresist. The photoresist and the aluminum film were then patterned to form the gate electrodes 407, 408 and 409. The photoresist was not removed after finishing etching and was allowed to remain as the mask films 410, 411 and 412 on the respective gate electrodes.
Further, current was passed through it in an electrolyte to effect porous anodic oxidation to form the porous anodic oxides 413, 414 and 415 having a thickness of 3000 to 6000 Å, for example, 5000 Å. Porous anodic oxidation can be carried out using 3 to 20% acid aqueous solutions of citric acid or oxalic acid, phosphoric acid, chromic acid and sulfuric acid, and fixed voltage of 5 to 30 V can be applied to the gate electrode. In the present preferred embodiment, anodic oxidation was carried out in an oxalic acid solution (30� C.) at the voltage of 10 V for 20 to 40 minutes. The thickness of the porous anodic oxide was controlled by the time for carrying out the anodic oxidation.
Then, as shown in FIG. 8(D), the masks 410, 411 and 412 were removed, and anodic oxidation was carried out in the same manner as that in the preferred embodiment. That is, the substrate was dipped in a 1 to 3% ethylene glycol solution of tartaric acid of pH about 7, and anodic oxidation was promoted with platinum as a cathode and the aluminum gate electrodes 407, 408 and 409 as anodes while gradually raising the voltage. The anodic oxide coat thus formed is minute and has pressure resistance. In particular, it is called barrier type anodic oxide. In the present preferred embodiment, the barrier type anodic oxides 416, 417 and 418 having a thickness of 1500 to 3500 Å, for example 2000 Å were formed.
Next, as shown in FIG. 8(E), a region where an N channel type TET and a pixel TFT in a peripheral circuit were formed was covered with a mask 419, and the porous anodic oxide 413 of a P channel type TFT in the peripheral circuit was etched. On this occasion, a mixed acid of phosphoric acid, acetic acid and nitric acid was used as an etchant.
Then, the mask 419 was removed, and the gate oxide film 406 was etched by dry etching. On this occasion, by using CH4 as etching gas, the anodic oxides were not etched, and only the silicon oxide film 406 was etched. As a result, as shown in FIG. 8(F), the silicon oxide film under the porous anodic oxides 414 and 415 was etched, and 406 a, 406 b and 406 c were left.
Then, as shown in FIG. 9(A), the porous anodic oxides 414 and 415 of the N channel type TFT and the pixel in the peripheral circuit were etched.
Thereafter, as shown in FIG. 9(B), the region of the N channel type TFT in the peripheral circuit was covered with a mask 420, and impurities were injected into a silicon film in the region of the P channel type TFT and an insular region 405 in the peripheral circuit in a self-aligned manner with a gate electrode part (gate electrode, barrier anodic oxide and silicon oxide film) as a mask by ion doping. Here, boron was injected with diborane (B2H6) as the doping gas, whereby the P type impurity regions 421 and 422 were formed. On this occasion, the dose amount of boron was set to 1 to 4�105 atoms cm−2, and the accelerating voltage to 10 kV. Herein, since the accelerating voltage was low, the lower part of the gate oxide film 406 c was not doped, and boron was not introduced.
Then, as shown in FIG. 9(C), the mask 420 was removed, and phosphorus was injected into a front surface with phosphine gas (PH3) as the doping gas to form an N type impurity region 423 in the region of the N channel type TFT in the peripheral circuit. Here, the dose amount of phosphorus was set to 1 to 8�1014 atoms cm−2, and the accelerating voltage to 5 kV. Here, since the accelerating voltage was low, the lower part of the gate oxide film 406 b was not doped, and phosphorus was not introduced. Further, since the dose amount of phosphorus was low as compared with that of boron, the impurity regions 421 and 422 of the P channel type TFT and the pixel TFT in the peripheral circuit remained P-type impurity regions.
Then, as shown in FIG. 9(D), with the dose amount of phosphorus set to 1�1013 to 1�1014 atoms cm−2 and the accelerating voltage to 90 kV, phosphorus was introduced into the lower part of the gate oxide film 406 b which had not been doped in the region of the N channel type TFT in the peripheral circuit, whereby a low concentration drain 424 (LDD, N−type) was formed.
Further, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used to activate the impurity regions 421, 422, 423 and 424. The energy density of the laser was suitably 200 to 400 mJ/cm2, and preferably 250 to 300 mJ/cm2. On this occasion, a PI junction present under the gate oxide film 406 c in the pixel TFT was sufficiently activated by laser irradiation. However, sufficient laser irradiation cannot be expected to a PI junction and a N−junction of a TFT in the peripheral circuit.
Accordingly, annealing was further carried out at 350 to 550� C. after the laser irradiation process to promote the activation of the junctions described above. Here, since the thickness of the active layer of the TFT in the peripheral circuit was as thick as 500 Å, crystallization proceeded from a channel-forming region (I type) to a P type and a N− type in the periphery, and a good PI junction and N− junction were obtained.
Next a silicon oxide film 425 was formed as an interlayer insulating film to a thickness of 3000 Å by plasma CVD.
Lastly, as shown in FIG. 9(E), a silicon nitride film having a thickness of 2000 to 6000 Å, for example 3000 Å was formed as a passivation film 430 by plasma CVD, and this, the silicon oxide film 425 and the gate insulating film 406 were etched to form contact holes to the impurity region 422. Then, an indium tin oxide film (ITO film) was formed and etched to form a pixel electrode 431.
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C30B29/06European ClassificationC30B1/02B, H01L29/66M6T6F15A2, H01L29/786S, H01L29/06C, H01L27/12T4T, H01L21/20DLegal EventsDateCodeEventDescriptionJun 16, 2005FPAYFee paymentYear of fee payment: 4Jun 10, 2009FPAYFee paymentYear of fee payment: 8Aug 16, 2013REMIMaintenance fee reminder mailedJan 8, 2014LAPSLapse for failure to pay maintenance feesFeb 25, 2014FPExpired due to failure to pay maintenance feeEffective date: 20140108RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services