Source: http://www.google.com/patents/US8001417?dq=6,460,050
Timestamp: 2017-03-28 22:27:37
Document Index: 239575462

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US8001417 - Method and apparatus for repairing uncorrectable drive errors in an ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsIn one embodiment, the invention provides a method for repairing a defective storage device in a physical storage-device array having a plurality of storage devices. The method comprises the steps of identifying a disk error associated with the defective storage device; effecting an error recovery pause...http://www.google.com/patents/US8001417?utm_source=gb-gplus-sharePatent US8001417 - Method and apparatus for repairing uncorrectable drive errors in an integrated network attached storage deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8001417 B2Publication typeGrantApplication numberUS 11/967,248Publication dateAug 16, 2011Filing dateDec 30, 2007Priority dateDec 30, 2007Fee statusPaidAlso published asUS20090172464Publication number11967248, 967248, US 8001417 B2, US 8001417B2, US-B2-8001417, US8001417 B2, US8001417B2InventorsRichard J. Byrne, Thomas Klucsarits, Nevin C. Heintze, Ambalavanar Arulambalam, Michael J. Hunter, Xing Zhao, Zhi Ping He, Yun Peng, Qian Gao Xu, Eu Gene Goh, Silvester TjandraOriginal AssigneeAgere Systems Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (27), Referenced by (6), Classifications (8), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetMethod and apparatus for repairing uncorrectable drive errors in an integrated network attached storage device
US 8001417 B2Abstract
In one embodiment, the invention provides a method for repairing a defective storage device in a physical storage-device array having a plurality of storage devices. The method comprises the steps of identifying a disk error associated with the defective storage device; effecting an error recovery pause based on the disk error; processing one or more outstanding data storage or retrieval requests; and generating a new data storage request instructing the physical disk device array having the defective storage device to store valid data associated with the data storage or retrieval request corresponding to the disk device error, whereby the defective storage device is repaired.
(i) U.S. Provisional Patent Application No. 60/725,060 entitled “Method and Apparatus for Aligned Data Storage Addresses in a RAID System” filed Oct. 7, 2005;
(ii) U.S. Provisional Patent Application No. 60/724,464 entitled “Method and Apparatus for Disk Address and Transfer Size Management” filed Oct. 7, 2005;
(iii) U.S. Provisional Patent Application No. 60/724,722 entitled “Method and Apparatus for Secure Key Management and Protection” filed Oct. 7, 2005;
(iv) U.S. Provisional Patent Application No. 60/724,463 entitled “Method and Apparatus for RTP Egress Streaming Using Complementary Directing File” filed Oct. 7, 2005;
(v) U.S. Provisional Patent Application No. 60/724,462 entitled “Media Data Processing Using Distinct Elements for Streaming and Control Processes” filed Oct. 7, 2005;
(vi) U.S. Provisional Patent Application No. 60/724,692 entitled “Buffer Management Method and System” filed Oct. 7, 2005;
(vii) U.S. Provisional Patent Application No. 60/724,573 entitled “Storage Device Management” filed Oct. 7, 2005;
(viii) U.S. patent application Ser. No. 11/273,750 entitled “Method and System For Accessing A Single Port Memory” filed Nov. 15, 2005;
(ix) U.S. patent application Ser. No. 11/364,979 entitled “Method And Apparatus For Burst Transfer” filed Feb. 28, 2006;
(x) U.S. patent application Ser. No. 11/518,543 entitled “High-Speed Redundant Disk Controller Methods and Systems” filed Sep. 8, 2006;
(xi) U.S. patent application Ser. No. 11/518,544 entitled “High-Speed Redundant Disk Controller Methods and Systems” filed Sep. 8, 2006;
(xii) U.S. patent application Ser. No. 11/544,442 entitled “Virtual Profiles for Storage-Device Array Encoding” filed Oct. 6, 2006;
(xiii) U.S. patent application Ser. No. 11/544,445 entitled “Back-Annotation in Storage-Device Array” filed Oct. 6, 2006;
(xiv) U.S. patent application Ser. No. 11/544,456 entitled “Ping-Pong State Machine for Storage-Device Array” filed Oct. 6, 2006;
(xv) U.S. patent application Ser. No. 11/544,462 entitled “Parity Rotation in Storage-Device Array” filed Oct. 6, 2006;
(xvi) U.S. patent application Ser. No. 11/539,350 entitled “Method and Apparatus for Disk Address and Transfer Size Management” filed Oct. 6, 2005;
(xvii) U.S. patent application Ser. No. 11/857,024 entitled “Double Degraded Array Protection in an Integrated Network Attached Storage Device” filed Sep. 18, 2007.
In one embodiment, the present invention provides a method for repairing a defective storage device in a physical storage-device array having a plurality of storage devices. The method comprises the steps of identifying a disk error associated with the defective storage device; effecting an error recovery pause based on the disk error; processing one or more outstanding data storage or retrieval requests; and generating a new data storage request instructing the physical disk device array having the defective storage device to store valid data associated with the data storage or retrieval request corresponding to the disk device error, whereby the defective storage device is repaired.
Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements:
A “sector” is the basic unit of read and write operations and consists of a uniquely addressable set of predetermined size, usually 512 bytes. Sectors correspond to small arcs of tracks on disk-drive platters that move past read/write heads on a disk as the disk rotates.
A “Data-Sector Unit” (DSU) is a sector's worth of data.
A “Data-Sector Address” (DSA) is a 32-bit numerical address that is used to refer to a particular DSU in the array, as described below with reference to FIG. 9. In a DSA-addressing scheme, sectors are numbered sequentially from 0 to D−1, where D is the total number of DSUs in the whole RAID array.
A “Parity-Sector Unit” (PSU) is a sector's worth of parity information. In a disk array with N drives, a PSU is derived from the bit-wise XOR of the data in the N−1 DSUs of a Stripe-Sector Unit (SSU), as described in further detail below.
A “Logical-Block Address” (LBA) is a 48-bit numerical address that is used to refer to a sector on an individual disk drive. In an LBA-addressing scheme, sectors are numbered sequentially from 0 to S−1, where S is the total number of sectors on a disk drive.
A “Stripe-Sector Unit” (SSU) is a set of sectors that includes one sector collected from each drive in the array. The set of sectors in an SSU share the same LBA, and thus, a specific SSU is referenced by the common LBA of its member sectors. For a block-interleaved, distributed-parity disk array with N drives, an SSU holds N−1 data sectors, plus one sector of parity information. The term “sector level” will be used to refer collectively to the corresponding addresses of the drives at which an SSU is stored.
A “stripe” is a set of chunks that includes one chunk collected from each drive in the array. The term “stripe index” will be used to refer to a numerical address identifying a stripe within an array.
FIG. 8 illustrates a rotating parity-placement striping scheme employed by RDE 701 in an exemplary RAID-5 array in one embodiment of the present invention. Lowercase letters represent chunks of data stored on disk0 through disk4 as follows. The following five chunks are stored at the same time: Chunk a is stored on disk0, chunk b is stored on disk1, chunk c is stored on disk2, chunk d is stored on disk3, and parity chunk P0 (which was generated by XOR-combining chunks a, b, c, and d) is stored on disk4. Next, the following five chunks are stored at the same time: chunk e is stored on disk0, chunk f is stored on disk1, chunk g is stored on disk2, parity chunk P1 (which was generated by XOR-combining chunks e, f, g, and h) is stored on disk3, and chunk h is stored on disk4. Next, the following five chunks are stored at the same time: chunk i is stored on disk0, chunk j is stored on disk1, parity chunk P2 (which was generated by XOR-combining chunks i, j, k, and l) is stored on disk2, chunk k is stored on disk3, and chunk 1 is stored on disk4. Next, the following five chunks are stored at the same time: chunk m is stored on disk0, parity chunk P3 (which was generated by XOR-combining chunks m, n, o, and p) is stored on disk1, chunk n is stored on disk2, chunk o is stored on disk3, and chunk p is stored on disk4. Next, the following five chunks are stored at the same time: parity chunk P4 (which was generated by XOR-combining chunks q, r, s, and t) is stored on disk0, chunk q is stored on disk1, chunk r is stored on disk2, chunk s is stored on disk3, and chunk t is stored on disk4. Next, the following five chunks are stored at the same time: chunk u is stored on disk0, chunk v is stored on disk1, chunk w is stored on disk2, chunk x is stored on disk3, and then parity chunk P5 (which was generated by XOR-combining chunks u, v, w, and x) is stored on disk4, and so forth. In this scheme, parity rotation through data is by stripes of chunks. In other words, in this rotating-parity scheme, parity chunks are distributed in round-robin manner across the drives of the disk array and through the data chunks of the stripes, such that each stripe contains exactly one parity chunk, and each subsequent stripe contains a parity chunk in a position that is “left-rotated” from that of the parity chunk of the current stripe. It should be understood that alternative parity placements are possible in various embodiments of the present invention. For example, alternative embodiments could employ a right-symmetric parity scheme or a different parity scheme wherein one chunk of parity per stripe is written.
RAID4— DID=DSA mod(N−1).
FIG. 22 illustrates Traffic-Manager Interface (TMI) sub-block 2100 of RDE 701. As shown, TMI includes response FIFO 2200 (e.g., a 2 k×33-bit FIFO), Write-Information Buffer Registers (WIBR) 2201, Read-Interface State Machine (RISM) 2202, and Write-Interface State Machine (WISM) 2203. TMI 2100 interfaces to TMA 707, which controls access to shared memory 711 of AAP 702. In the read path, in response to demands from TMA 707, response FIFO 2200 receives data from BPR 2106 on 33-bit data signal bpr_data[32:0], and data is read out of response FIFO 2200 to TMA 707 on 32-bit data signal rde_tma_data[31:0], as controlled by RISM 2202. In the write path, in response to demands from TMA 707, WIBR 2201 receives data from TMA 707 on 32-bit data signal tma_rde_data[31:0], and data is read out of WIBR 2201 to PBP 2102 (for parity generation) on 32-bit data signal pbp_indata[31:0], as controlled by WISM 2203. WIBR 2201 also provides to PBP 2102 control signal psb_sel, which determines whether (i) an SSU arriving at PBP 2102 via pbp_indata[31:0] will pass through PBP 2102 and be provided to WIF 2103 normally (in non-degraded mode), or instead, (ii) PBP 2102 will generate and output accumulated parity information to WIF 2103 (in degraded mode), rather than the arriving SSU. Handshaking between RDE 701 and TMA 707 is implemented in TMI 2100 by RISM 2202 and WISM 2203, as described above, via signals (i) rde_tma_valid, provided by RISM 2202 to TMA 707, (ii) tma_rde_ready, provided by TMA 707 to RISM 2202, (iii) rde_tma_ready, provided by WISM 2203 to TMA 707, and (iv) tma_rde_valid, provided by TMA 707 to WISM 2203. Additionally, RISM 2202 provides SOH signal rde_tma_soh to TMA 707, and TMA 707 provides SOH signal tma_rde_soh to WISM 2203. WIBR 2201 also provides header information to WOS 2101 on 32-bit data signal wos_data[31:0] for storage in Write-Header Extraction Registers (WHER) 2301.
FIG. 25 illustrates Parity-Block Processor (PBP) sub-block 2102 of RDE 701. PBP 2102 performs block-parity generation on SSU sector data received from WIBR 2201 of TMI 2100, as directed by WOSM 2300 of WOS 2101. Instead of storing parity information for each SSU sector (as in traditional RAID array systems), which would require substantial overhead in terms of memory and time, PBP 2102 accumulates parity information in a single buffer, i.e., Parity-Sector Buffer (PSB) 2500 (e.g., a 128×32-bit RAM with separate read and write ports). As the first sector of an SSU flows to WIF 2103, this sector is also copied to PSB 2500. As subsequent sectors flow through to WIF 2103, the contents of PSB 2500 are replaced with the XOR of (i) its previous contents and (ii) the arriving SSU sector data, thereby accumulating parity information in PSB 2500. When N−1 sector units have been transferred, PSB 2500 is transferred and cleared. Signal psb_sel received from WIBR 2201 of TMI 2100 controls multiplexer 2501, thereby determining whether (i) an SSU arriving at PBP 2102 via pbp_indata[31:0] will pass through PBP 2102 and be provided as pbp_outdata[31:0] to WIF 2103 normally (in non-degraded mode), or instead, (ii) PBP 2102 will generate and output as pbp_outdata[31:0] accumulated parity information to WIF 2103 (in degraded mode), rather than the arriving SSU.
FIG. 26 illustrates Write-Interface (WIF) sub-block 2103 of RDE 701. WIF 2103 includes Write-Header Information-Buffer Register (WHIBR) 2600, PARROT DID Map 2601, PHYS DID Map 2602, Pending-Write Request FIFO (WPF) 2603, and state machine 2604. WIF 2103 buffers requests for storage and retrieval operations and communicates those requests to MDC 705. Write operations are executed as commanded by WOS 2101 and, as these requests are written to WPF 2603 (e.g., a 2 k×36-bit FIFO) and then sent to MDC 705, information is also written by WOS 2101 to IRF 2700 of ROS 2104 and the issued request occupancy count (irf_o_count) in the RDE status register rRSTAT in CSR 2108 is incremented. WHIBR 2600 holds header information to be multiplexed with storage request data. Accordingly, WHIBR 2600 receives from WHIR 2304 of WOS 2101 header information including LBA[47:0], XCNT[12:0], QID[6:0], and T. This header information (as shown in FIG. 16 and FIG. 17) is written for each drive in the RAID-Array Cluster once per storage or retrieval request.
FIG. 27 illustrates the Read-Operation Sequencer (ROS) sub-block 2104 of RDE 701. ROS 2104 includes Issued-Request FIFO (IRF) 2700, Read-Operation State Registers (ROSR) 2701, Read-Response Configuration Registers (RCFR) 2702, Request-Information Response Registers (RIRR) 2703, translator 2704, Response-Header Information Register (RHIR) 2705, Response-Header Error Register (RHER) 2706, and Read-Operation State Machine (ROSM) 2707. IRF 2700 (e.g., a 64×64-bit FIFO) receives header information (as shown in FIG. 28, described below) via data signal irf_data[64:0] from WHER 2301 of WOS 2101, which ROS 2104 uses to monitor and confirm responses to issued requests. It is noted that the information stored in many of these registers changes quickly, i.e., as each SSU is being read from disks 712.
With reference to the state diagram of FIG. 29, the operation of ROSM 2707 will now be described. The PING states unload, into response FIFO 2200 of TMI 2100, (i) the contents of the primary buffer of SSUB 3101 of BPR 2106 and (ii) the contents of the primary Response-Header Information_Buffer Register (RHIBR) 3103 of BPR 2106. Concurrently, the PONG states unload, into response FIFO 2200 of TMI 2100, (i) the contents of the alternate buffer of SSUB 3101 of BPR 2106 and (ii) the contents of the alternate RHIBR 3103 of BPR 2106. ROSM 2707 can be referred to as a “ping-pong state machine” because the PING states and PONG states execute at the same time, thereby permitting concurrent use of two different RAID-Array Clusters (e.g., rebuilding a degraded volume on one RAC while retrieving multimedia data from a different RAC). The PING portion of the state machine “ping-pongs” the buffers of SSUB 3101 and RHIBR 3103, i.e., flips the primary-alternate buffer designations, when unloading of headers and data into response FIFO 2200 of TMI 2100 is complete and the PONG portion of the state machine is ready.
The Update Double Degraded (UPDOUBDEG) State is entered from states UPDEGCKH, UPDEGDSU or UPDEGPSU when the E field in a response header (as discussed above in connection with MDC Error Marking) was set indicating an MDC response error (as shown in FIG. 20) and the operative rRAC profile was RAID0 or already marked as degraded. The appropriate double-degraded-error-status bit is set in the RAID Array Cluster register rRAC corresponding to the active VAP (see rRAC table, above), and the MDC-to-RDE interfaces are disabled by setting the rRCTL register's EMDCRDE and ERDEMDC bits to a “disabled” value (e.g., zero). Thus, Request and Retrieval operations between the MDC and RDE are thus halted automatically to permit correction of the double-degraded condition, e.g., by replacing one of the two degraded drives in the array with a new drive.
FIG. 31 illustrates Block-Parity Reconstructor (BPR) sub-block 2106 of RDE 701. BPR 2106 passes retrieved data to TMI 2100 and reconstructs data when operating in degraded mode. BPR 2106 includes Retrieval Parity-Sector Buffer (RPSB) 3100, Stripe Sector-Unit Buffer (SSUB) 3101, Sector Sequencer (SSEQ) 3102, and Response-Header Information-Buffer Register (RHIBR) 3103. BPR 2106 receives signal rpsb_sel, which indicates a degraded volume, from the degraded[6] bit of the operative VAP stored in one of RAC Profile Registers 0-15 (rRAC0-rRAC15, discussed in further detail with respect to Tables 21 and 22 below). BPR 2106 receives data signal rif_data[31:0] from RIF 2105. BPR 2106 receives header information from ROS 2104 via signals degraded_ddid[3:0], current_did[3:0], and dword[10:0]. BPR 2106 receives the T and QID fields from ROS 2104 via signals rhir_t and rhir_qid[6:0], respectively. BPR 2106 provides control signal bpr_parity_check to ROS 2104 and data signal bpr_data[32:0] to TMI 2100. The operation of BPR 2106 is directed by ROS 2104. SSUB 3101 (e.g., 2×1 k×32-bit single-port RAMs) is a dual ping-pong buffer (or “double buffer”). A ping-pong buffer contains a pair of storage arrays (a “primary buffer” and an “alternate buffer”). Data received into a ping-pong buffer from a first bus is written into a first array, while data is read out of the second array and supplied to a second bus. The read and write functions of the two storage arrays are interchanged back and forth (“ping-ponged”) from time to time, so that data is alternatingly written into the first array and then the second array, and data is alternatingly read out from the second array and then the first array, in an opposite manner from that used for the writing operation. Accordingly, SSUB 3101 contains a primary buffer and an alternate buffer, which are alternatingly used to build SSUs. Retrieved SSUs flow through RPSB 3100 (e.g., a 128×32-bit RAM with separate read and write ports) and become logically organized in SSUB 3101, to be stored into one of the two buffers of SSUB 3101, as selected through SSEQ 3102.
CSR 2108 (e.g., a 32×32-bit memory) includes four categories of registers: (i) Error-Status Registers (rRERR), (ii) RAC-Profile Registers (rRAC), (iii) an RDE-Control Register (rRCTL), and (iv) an RDE Status Register (rRSTAT).
The RAC-Profile Registers (rRAC) store information about each of the VAPs, including chunk size (K), number of DSUs per stripe (K*(N−1)), whether parity-checking is enabled, double-degraded status (DBLD), logical number of a degraded drive (RAID—5_DID_ideg), cluster degraded status, RAID level, cluster size, and physical-to-logical drive mappings. In the write path, the operative RAID-Array Cluster Profile is chosen as indexed by the request's RAC[3:0] field (as shown in FIG. 12). In the read path, the operative RAID-Array Cluster Profile is chosen as indexed by the response's RAC[3:0] field (as shown in FIG. 13). In the unlikely occurrence that an error-induced back-annotation event is recognized simultaneously with a processor-mandated update on an operative VAP, the software-mandated update directed by AAP 702 overrides the back-annotation, because the update is based on the “stale” profile. If, however, the newly-recognized event arrives at the profile register one or more clock cycles before or after the register is cleared, then there is no collision, and there is no obstructing refractory interval. Such collisions could be avoided by software restricting configuration updates to “spare” out-of-service profiles that will not be operative for outstanding requests, and then switching to the spare updated alternate profile. It is noted that, for each RAID-Array Cluster, a RAID level is stored in bits[5:4], which can be either RAID-5, RAID-4, RAID-0, or “Just a Bunch of Disks” (JBOD). Whereas a RAID system stores the same data redundantly on multiple physical disks that nevertheless appear to the operating system as a single disk, JBOD also makes the physical disks appear to be a single one, but accomplishes this by combining the drives into one larger logical drive. Accordingly, JBOD has no advantages over using separate disks independently and provides none of the fault tolerance or performance benefits of RAID. Nevertheless, JBOD may be useful for certain applications, and an RAC cluster can utilize a JBOD scheme instead of a RAID scheme, if a user so desires. The following register map Tables 21-24 show the RAC Profile registers.
The data storage system 700 may be further configured to attempt data recovery after receiving a uncorrectable disk device (“UNC”) error from a PDID in a VAP. A UNC error occurs when a disk device's controller is unable to correctly retrieve information from one or more “bad” disk sectors. The RAID array defined by the VAP may provide redundancy allowing the automatic reconstruction of data in the event of disk error or failure. As such, the system 700 may be able to repair an error by rebuilding the entire disk array, e.g., by rewriting duplicated or reconstructed data back to the affected array. Rewriting the duplicated or reconstructed data in certain instances effectively repairs the disk device, because some disk device controllers perform a read check after writing data and will re-map the failed region to a new region, if the read check is unsuccessful. Such disk devices facilitate repairs by logically re-mapping these failed sector addresses to spare physical sectors when these sector addresses are re-written. Because re-building an entire disk array may not be feasible due to the high data throughput requirements of the system 700, however, the system 700 is preferably configured, in the event of a disk error, to trace the outstanding issued requests, determine the information related to each request, and re-try the same request or requests after the errored sector has been remapped. During the recovery process, new requests should not be issued by the TMA 707 or processed by the RDE 701 and MDC 705.
Third, the ROSM 2707 enters the PAUSE state, described above, and remains in the pause state until the interface control bit ERDEMDC is re-enabled (e.g., set to a “1” value) or until the PAUSE bits in the rRCTL register are set to a value “00,” thus disabling the Pause-on-Error and Pause-for-Stepping modes.
Fourth, if the system 700 is configured to attempt repairs after disk device errors, during the first PAUSE state after identification of the error, the AAP 702 sets the Pause-for-Stepping mode bits in the RCTL register field to allow single stepping of outstanding requests. The AAP 702 further retrieves from the IRF 2700 (shown on FIG. 27) the pending outstanding requests—i.e., requests for which corresponding responses have not been completely processed—based on the value of the Issued Request Occupancy Counter field IRF_O_COUNT in the rRSTAT register. The AAP 702 also reads the information stored in the RDE Request Information Response register rRIRR.
Fifth, the system 700 sequentially processes the pending outstanding requests, in order to clear the storage/retrieval pipeline of outstanding requests and in order to identify the specific issued request that prompted the disk device error. In particular, (a) the AAP 702 conditionally re-enables the four RDE interfaces by re-setting the ETMARDE, ERDETMA, EMDCRDE and ERDEMDC bits (e.g., to a value of “1”. In a preferred embodiment, re-enabling the interface control bit ERDEMDC causes the ROSM 2707 to terminate the PAUSE state (described above with reference to FIG. 29) and to continue operation at the RIDLE state. The ROSM 2707 then continues operation on the current issued request that is pending in the IRF FIFO, in accordance with the ROS states described above with reference to FIG. 29. (b) The AAP 702 reads the rRIRR and rSTAT registers for the current request being processed and saves the request entry information corresponding to the current request into memory. (c) If the current request causes the rRERR register in the RDE 707 to become set, thus indicating that the MDC 705 has recognized an error marked Device to Host register FIS, the AAP 702 checks the link corresponding to the Ldeg field of the RDE's operative RAC profile and reads the MDC block's FeatErr shadow register for that link to see if the UNC bit was set on that Dev-Host Register FIS. The AAP 702 may also read the LBA from the shadow register. (d) After the completion of the response to the current request, the ROSM 2707 once again conditionally disables all four RDE interfaces (e.g., during the PINGPONG state), until the AAP 702 authorizes the RDE 701 to proceed to the next pending request by writing to the RDE control register rRCTL to re-enable the RDE interfaces. Steps (a) through (d) are repeated until the outstanding requests have been exhausted.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4864531Sep 28, 1987Sep 5, 1989La Telemecanique ElectriqueError control apparatus using restore memory for recovering from parity discordances in transmissions between controller and real-time I/O devicesUS5367669Mar 23, 1993Nov 22, 1994Eclipse Technologies, Inc.Fault tolerant hard disk array controllerUS5373512May 6, 1994Dec 13, 1994International Business Machines CorporationMemory controller with parity generator for an I/O control unitUS5491816Jan 17, 1995Feb 13, 1996Fujitsu LimitedInput/ouput controller providing preventive maintenance information regarding a spare I/O unitUS5568629Nov 4, 1993Oct 22, 1996At&T Global Information Solutions CompanyMethod for partitioning disk drives within a physical disk array and selectively assigning disk drive partitions into a logical disk arrayUS5805788May 20, 1996Sep 8, 1998Cray Research, Inc.Raid-5 parity generation and data reconstructionUS5826001Oct 13, 1995Oct 20, 1998Digital Equipment CorporationReconstructing data blocks in a raid array data storage system having storage device metadata and raid set metadataUS5844919 *Sep 16, 1996Dec 1, 1998Cirrus Logic, Inc.Sector and track level error correction system for disc storage systemsUS5960169Feb 27, 1997Sep 28, 1999International Business Machines CorporationTransformational raid for hierarchical storage management systemUS6269453Jun 29, 1993Jul 31, 2001Compaq Computer CorporationMethod for reorganizing the data on a RAID-4 or RAID-5 array in the absence of one diskUS6397347 *Feb 26, 1999May 28, 2002Nec CorporationDisk array apparatus capable of dealing with an abnormality occurring in one of disk units without delaying operation of the apparatusUS6457109Aug 18, 2000Sep 24, 2002Storage Technology CorporationMethod and apparatus for copying data from one storage system to another storage systemUS6571351Apr 7, 2000May 27, 2003Omneon Video NetworksTightly coupled secondary storage system and file systemUS6651154Jul 11, 2000Nov 18, 2003International Business Machines CorporationMethod, system, and program for expanding the storage space in an array of storage unitsUS6839827Jan 18, 2000Jan 4, 2005International Business Machines CorporationMethod, system, program, and data structures for mapping logical blocks to physical blocksUS6842422Jun 15, 1999Jan 11, 2005Marconi Communications, Inc.Data striping based switching systemUS7536584 *Oct 23, 2006May 19, 2009Dot Hill Systems CorporationFault-isolating SAS expanderUS20010002480Sep 30, 1997May 31, 2001Lsi Logic CorporationMethod and apparatus for providing centralized intelligent cache between multiple data controlling elementsUS20020083379 *Nov 1, 2001Jun 27, 2002Junji NishikawaOn-line reconstruction processing method and on-line reconstruction processing apparatusUS20020095532Jan 16, 2001Jul 18, 2002International Business Machines Corporation:System, method, and computer program for explicitly tunable I/O device controllerUS20030056142Sep 17, 2001Mar 20, 2003Ebrahim HashemiMethod and system for leveraging spares in a data storage system including a plurality of disk drivesUS20030088611 *May 7, 2002May 8, 2003Mti Technology CorporationSystems and methods for dynamic alignment of associated portions of a code word from a plurality of asynchronous sourcesUS20030131191Nov 25, 2002Jul 10, 2003Broadlogic Network Technologies, Inc.Multi-stream access scheme for high speed access and recording using a hard disk driveUS20040049632Sep 9, 2002Mar 11, 2004Chang Albert H.Memory controller interface with XOR operations on memory read to accelerate RAID operationsUS20040153717Nov 7, 2002Aug 5, 2004Duncan Kurt A.Apparatus and method for enhancing data availability by implementing inter-storage-unit communicationUS20060107002Nov 15, 2004May 18, 2006Benhase Michael TMethod, system, and program for an adaptor to read and write to system memoryUS20090172464 *Dec 30, 2007Jul 2, 2009Agere Systems Inc.Method and apparatus for repairing uncorrectable drive errors in an integrated network attached storage device* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8621267 *Dec 15, 2010Dec 31, 2013Microsoft CorporationExtended page patchingUS9182958 *Sep 3, 2013Nov 10, 2015Atmel CorporationSoftware code profilingUS9213611Aug 26, 2013Dec 15, 2015Western Digital Technologies, Inc.Automatic raid mirroring when adding a second boot driveUS20120159262 *Dec 15, 2010Jun 21, 2012Microsoft CorporationExtended page patchingUS20140331085 *Jul 15, 2014Nov 6, 2014Cleversafe, Inc.Method and apparatus for distributed storage integrity processingUS20150067661 *Sep 3, 2013Mar 5, 2015Atmel CorporationSoftware code profiling* Cited by examinerClassifications U.S. Classification714/6.13, 714/6.11, 714/5.1International ClassificationG06F11/00Cooperative ClassificationG06F11/1092, G06F11/1088European ClassificationG06F11/10R4, G06F11/10R3Legal EventsDateCodeEventDescriptionOct 13, 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