Source: http://www.google.com/patents/US7376318?dq=7350717
Timestamp: 2018-01-16 13:46:22
Document Index: 314783932

Matched Legal Cases: ['art.\n5', 'art 4', 'art 4', 'art 4', 'art 4', 'art 4', 'art 4', 'art 4', 'art 4', 'arts 4', 'arts 4', 'art 4', 'art 402', 'art 902', 'art 400', 'art 402', 'art 400', 'art 400', 'art 402', 'art 402', 'art 402']

Patent US7376318 - Circuit board and its manufacturing method - Google Patents
A circuit board comprises a base film that is a base layer, a first conductive circuit manufactured by hardening conductive paste material formed in a predetermined shape on the base film, a first insulating layer manufactured by hardening insulating paste material formed on the base film and the first...http://www.google.com/patents/US7376318?utm_source=gb-gplus-sharePatent US7376318 - Circuit board and its manufacturing method
Publication number US7376318 B2
Application number US 11/653,891
Also published as CN1320846C, CN1525804A, US7180749, US20040134681, US20070114058
Publication number 11653891, 653891, US 7376318 B2, US 7376318B2, US-B2-7376318, US7376318 B2, US7376318B2
Patent Citations (17), Classifications (49), Legal Events (3)
US 7376318 B2
a part arrangement layer with an electronic part disposed in such a manner that an electrode terminal of said electronic part is exposed on one surface of said electronic part; and
a second conductive circuit formed in a predetermined shape, said second conductive circuit being electrically connected to said electrode terminal;
wherein said part arrangement layer includes
(i) a first conductive circuit, formed by hardening a conductive paste material coated in a predetermined shape, and
(ii) an insulating layer, having an opening, formed by hardening an insulating paste material made of thermosetting resin coated onto said first conductive circuit, with said electronic part being fitted into said opening with said insulating layer being formed in such manner that said electrode terminal is exposed on a surface of said insulating layer.
a connection opening in said insulating layer on said first conductive circuit, and said first conductive circuit
wherein said first conductive circuit and said second conductive circuit are electrically connected with each other via said connection opening.
3. The circuit board of claim 1, wherein
said part arrangement layer further includes other electronic parts electrically connected to said first conductive circuit.
a base layer which supports said part arrangement layer, said base layer adhered via an adhesive to a surface of said electronic part that is opposite to said one surface of said electronic part.
5. The circuit board of claim 4, wherein
said part arrangement layer is only on a part of said base layer.
6. The circuit board of claim 4, wherein
said base layer comprise a film member.
7. The circuit board of claim 6, further comprising;
a plate member connected to a part of a surface of said part arrangement layer that is opposite to a surface of said part arrangement layer that is connected to said base layer.
8. The circuit board of claim 4, wherein
9. The circuit board of claim 8, further comprising:
wherein said part arrangement layer is sandwiched between said base layer and said another plate member.
10. The circuit board of claim 1, wherein
one of said first conductive circuit and said second conductive circuit is connected to metallic wiring formed by any one of depositing, plating and sputtering processes.
11. The circuit board of claim 10, wherein
said electronic part comprises a semiconductor integrated circuit element of bare chip configuration, and
said metallic wiring is formed so as to connect an electrode terminal of said semiconductor integrated circuit element to said second conductive circuit.
12. The circuit board of claim 1, wherein
said part arrangement layer is further provided with other electronic parts.
This application is divisional of application Ser. No. 10/727,650, filed Dec. 5, 2003 now U.S. Pat. No. 7,180,749.
FIG. 11 is a flow chart showing the main manufacturing process of the circuit board of the first exemplary embodiment.
When the circuit board 1 is to be manufactured, as shown in FIG. 1, a base film of about 100 gm thick is used as a base layer. In the present exemplary embodiment, the base layer is described as base film 11 in the following. As the base film 11, it is desirable to use polyethylene telephthalate (PET) resin, acrylonitrile-butadiene styrene (ABS) resin or polycarbonate resin, but it is also possible to use resin that is relatively high in heat resistance such as polyimide resin.
Next, as shown in FIG. 5, an insulating paste material is printed onto the first insulating layer 15 formed and the electronic part 4 by performing a screen printing process or the like, and this paste material is heated and hardened to form second insulating layer 17 (step 314). In this case, the paste material is not printed on the via 310 and the second opening 330 of the first insulating layer 15, and also nearly only surfaces of the electrode terminals 41 of the electronic part 4 are exposed from the second insulating layer 17. In this way, the electronic part 4 is buried in the second insulating layer 17 as a whole. In order to prevent the electronic part 4 from being damaged, the insulating paste materials used are desirable to harden at 120° C. or lower, and more preferably, at 110° C. or lower.
The second conductive circuit 19 is further provided with gap 22. As shown in FIG. 8, resistant paste material is applied to the gap 22. And, the resistant paste material is heated and hardened to form resistive layer 52. Each end of the resistive layer 52 in the gap 22 is electrically connected with the conductor of first conductive circuit 13, thereby configuring resistor 71 (step S17). It is preferable to execute heating and hardening of the resistance paste material simultaneously with heating and hardening of conductive paste material that is to form the second conductive circuit 19.
Next, as shown in FIG. 9, insulating paste material is printed on the second conductive circuit 19, resistor 71 and the second insulating layer 17 by screen printing or the like, followed by heating and hardening this insulating paste material to form third insulating layer 23 (step 318). The third insulating layer 23 is provided with via 340 as needed, which is a connection opening where the second conductive circuit 19 is exposed.
Further, in the circuit board 1 of the present exemplary embodiment, inductor 191 is disposed on the second conductive circuit 19, capacitor 61 is disposed by holding the dielectric layer 51 between the first conductive circuit 13 and the second conductive circuit 19, and resistor 71 is disposed by forming the resistive layer 52 in the gap 22 of the second conductive circuit 19. Accordingly, it is possible to obtain the circuit board 1 having complicated circuits with excellent function while realizing a reduction in thickness.
Further, it is possible to form a resistive layer by heating and hardening a resistance paste material applied to the second opening 330. In this case, a resistive layer is formed between first conductive circuit 13, which is a lower layer, and second conductive circuit 19, which is an upper layer, thereby forming a resistor in a vertical direction. Also, it is possible to heat and harden the dielectric paste material applied to the gap 22, to be formed into the second conductive circuit 19 so as to form a dielectric layer thereon. In this case, a capacitor is formed in a horizontal direction because second conductive circuits 19 connected to the dielectric layer serve as electrodes respectively at both sides by being flush with each other. Thus, in the flow chart shown in FIG. 11, it is possible to freely form a dielectric layer and resistive layer by properly changing the paste material in step S15 and step S17.
FIG. 12 and FIG. 13 are diagrams for describing a modified method of manufacturing a circuit board. The modified method additionally includes a step of applying adhesive to a bottom of the first opening 320 between step S12 and step 813 described in the first exemplary embodiment, thereby bonding the electronic part 4 beforehand, and this point differs from the first exemplary embodiment. FIG. 14 is a part of a flow chart additionally including a step of “applying adhesive to the first opening” that is step 21 between step 12 and step 13.
Thus, even when a shape of first opening 320 is poor in accuracy, electronic part 4 can be correctly secured in a predetermined position. In that case, even when the first opening 320 becomes larger than the electronic part 4, causing a gap to be created between the first opening 320 and the electronic part 4, the gap will be filled with the second insulating layer 17 to be formed later. Accordingly, even in case a plurality of electronic parts 4, including relatively many electrode terminals 41, are mounted, positional deflection of electronic parts 4 from each other can be lessened, and therefore, forming the second conductive circuit 19 by printing or the like will not cause shorting trouble or the like. This is effective especially in a case of using a bare chip IC as electronic part 4, and a large number of electrode terminals 41.
As shown in FIG. 21, another electronic part 402 is inserted into the third opening 324 (step S37). The electronic part 902, same as with the electronic part 400 initially mounted, is inserted in such manner that a surface at an opposite side of electrode terminals 412 formed on one surface thereof comes into contact with the base film 11. The another electronic part 402 is required to be larger in thickness than the electronic part 400. Therefore, when a bare chip IC is used, it should be thicker than the electronic part 400. Also, a package IC or the like is to be used.
After that, as shown in FIG. 22, fourth insulating layer 308 is formed on a surface of the electronic part 402, except for electrode terminals 412, and a surface of the third insulating layer 306. The fourth insulating layer 308 is also formed by screen printing or the like of an insulating paste material, followed by heating and hardening this material (step S38). In this case, the via 312 formed in the third insulating layer 306 is left intact, and the electrode terminals 912 of electronic part 402 are exposed on the fourth insulating layer 308. In this condition, layers including the second conductive circuit 204, the third insulating layer 306 and the fourth insulating layer 308, in addition to the first conductive circuit 202, the first insulating layer 302 and the second insulating layer 309 configuring the part arrangement layer 200 described above, configure part arrangement layer 250 in relation to the electronic part 402.
US20030221864 Feb 19, 2003 Dec 4, 2003 Leif Bergstedt Printed board assembly and method of its manufacture
US20040037061 Aug 21, 2002 Feb 26, 2004 David Liu Method and components for manufacturing multi-layer modular electrical circuits
JP2001053413A Title not available
JP2001093934A Title not available
JP2002164392A Title not available
JP2002261421A Title not available
JP2002344137A Title not available
JPS594195A Title not available
U.S. Classification 385/129, 385/130, 257/E25.011, 385/131, 257/E23.178
International Classification H01L23/538, H05K1/16, G02B6/10, H01L25/065, H05K1/09, H05K3/12, H05K3/46, H05K1/18, H01L23/12, H01L21/60
Cooperative Classification Y10T29/49126, Y10T29/49124, Y10T29/53874, H01L2924/07802, H01L2924/19042, H05K1/185, H05K3/4664, H05K1/162, H05K1/167, H01L2924/01033, H01L2924/19041, H01L2924/01006, H05K2203/0568, H01L2224/24226, H01L24/82, H01L2924/01029, H01L2924/14, H01L2924/01027, H01L2924/30107, H01L2224/16, H05K2201/0187, H01L2924/01004, H05K1/095, H01L25/0652, H01L2924/01013, H01L2924/01078, H01L24/24, H01L2924/014, H01L2924/01005, H01L2924/01047, H01L2924/19043, H05K1/165, H01L23/5389