Source: https://patents.google.com/patent/US9892766B2/en
Timestamp: 2018-10-20 16:30:06
Document Index: 178784834

Matched Legal Cases: ['Application No. 14760332', 'Application No. 10', 'Application No. 2016', 'Application No. 10', 'Application No. 201480011890', 'Application No. 2015', 'Application No. 103107275', 'Application No. 14760332']

US9892766B2 - Apparatuses and methods for performing logical operations using sensing circuitry - Google Patents
US9892766B2
US9892766B2 US15270761 US201615270761A US9892766B2 US 9892766 B2 US9892766 B2 US 9892766B2 US 15270761 US15270761 US 15270761 US 201615270761 A US201615270761 A US 201615270761A US 9892766 B2 US9892766 B2 US 9892766B2
US15270761
US20170011782A1 (en )
This application is a Continuation of U.S. application Ser. No. 14/878,452, filed Oct. 8, 2015, which is a Continuation of U.S. application Ser. No. 13/784,219, filed Mar. 4, 2013, which issued as U.S. Pat. No. 9,158,667 on Oct. 13, 2015, the contents of which are included herein by reference.
Furthermore, the circuitry of the processing resource(s) (e.g., compute engine) may not conform to pitch rules associated with a memory array. For example, the cells of a memory array may have a 4F2 or 6F2 cell size, where “F” is a feature size corresponding to the cells. As such, the devices (e.g., logic gates) associated with ALU circuitry of previous PIM systems may not be capable of being formed on pitch with the memory cells, which can affect chip size and/or memory density, for example.
FIG. 2 illustrates a schematic diagram of a portion of a memory array 230 coupled to sensing circuitry in accordance with a number of embodiments of the present disclosure. In this example, the memory array 230 is a DRAM array of 1T1C (one transistor one capacitor) memory cells each comprised of an access device 202 (e.g., transistor) and a storage element 203 (e.g., a capacitor). In a number of embodiments, the memory cells are destructive read memory cells (e.g., reading the data stored in the cell destroys the data such that the data originally stored in the cell is refreshed after being read). The cells of array 230 are arranged in rows coupled by word lines 204-0 (Row0), 204-1 (Row1), 204-2, (Row2) 204-3 (Row3), . . . , 204-N(RowN) and columns coupled by sense lines (e.g., digit lines) 205-1 (D) and 205-2 (D_). In this example, each column of cells is associated with a pair of complementary sense lines 205-1 (D) and 205-2 (D_). Although only a single column of memory cells is illustrated in FIG. 2A, embodiments are not so limited. For instance, a particular array may have a number of columns of memory cells and/or sense lines (e.g., 4,096, 8,192, 16,384, etc.). A gate of a particular memory cell transistor 202 is coupled to its corresponding word line 204-0, 204-1, 204-2, 204-3, . . . , 204-N, a first source/drain region is coupled to its corresponding sense line 205-1, and a second source/drain region of a particular memory cell transistor is coupled to its corresponding capacitor 203. Although not illustrated in FIG. 2A, the sense line 205-2 may also be coupled to a column of memory cells.
In a number of embodiments, a compute component (e.g., 231) can comprise a number of transistors formed on pitch with the transistors of the sense amp (e.g., 206) and/or the memory cells of the array (e.g., 230), which may conform to a particular feature size (e.g., 4F2, 6F2, etc.). As described further below, the compute component 231 can, in conjunction with the sense amp 206, operate to perform various logical operations using data from array 230 as input and store the result back to the array 230 without transferring the data via a sense line address access (e.g., without firing a column decode signal such that data is transferred to circuitry external from the array and sensing circuitry via local I/O lines). As such, a number of embodiments of the present disclosure can enable performing logical operations and computing functions associated therewith using less power than various previous approaches. Additionally, since a number of embodiments eliminate the need to transfer data across local I/O lines in order to perform compute functions, a number of embodiments can enable an increased parallel processing capability as compared to previous approaches.
A second source/drain region of transistor 208-1 and 208-2 is commonly coupled to a negative control signal 212-1 (Accumb). A second source/drain region of transistors 209-1 and 209-2 is commonly coupled to a positive control signal 212-2 (Accum). The Accum signal 212-2 can be a supply voltage (e.g., Vcc) and the Accumb signal can be a reference voltage (e.g., ground). Enabling signals 212-1 and 212-2 activates the cross coupled latch comprising transistors 208-1, 208-2, 209-1, and 209-2 corresponding to the secondary latch. The activated sense amp pair operates to amplify a differential voltage between common node 217-1 and common node 217-2 such that node 217-1 is driven to one of the Accum signal voltage and the Accumb signal voltage (e.g., to one of Vcc and ground), and node 217-2 is driven to the other of the Accum signal voltage and the Accumb signal voltage. As described further below, the signals 212-1 and 212-2 are labeled “Accum” and “Accumb” because the secondary latch can serve as an accumulator while being used to perform a logical operation. In a number of embodiments, an accumulator comprises the cross coupled transistors 208-1, 208-2, 209-1, and 209-2 forming the secondary latch as well as the pass transistors 207-1 and 208-2. As described further herein, in a number of embodiments, a compute component comprising an accumulator coupled to a sense amplifier can be configured to perform a logical operation that comprises performing an accumulate operation on a data value represented by a signal (e.g., voltage or current) on at least one of a pair of complementary sense lines.
At time t1, the equilibration signal 226 is deactivated, and then a row is activated (e.g., the row corresponding to a memory cell whose data value is to be sensed). Signal 204 represents the voltage signal applied to the selected row. When row signal 204 reaches the threshold voltage (Vt) of the access transistor (e.g., 202) corresponding to the selected cell, the access transistor turns on and couples the sense line D to the selected memory cell (e.g., to the capacitor 203 if the cell is a 1T1C DRAM cell), which creates a differential voltage signal between the sense lines D and D_ (e.g., as indicated by signals 205-1 and 205-2, respectively) between times t2 and t3. The voltage of the selected cell is represented by signal 203. Due to conservation of energy, creating the differential signal between D and D_ (e.g., by coupling the cell to D) does not consume energy, since the energy associated with activating/deactivating the row signal 204 can be amortized over the plurality of memory cells coupled to the row.
At time t3, the sense amp fires (e.g., the positive control signal 231 (e.g., PSA 331 shown in FIG. 3) goes high, and the negative control signal 228 (e.g., RNL_ 328) goes low), which amplifies the differential signal. The primary energy consumption occurs in charging the sense line D 205-1 from VDD/2 to VDD.
At time t4, the pass transistor 207-1 and/or 207-2 is activated, depending on the particular logic operation. Since timing diagram 285 is describing a first phase of a NAND operation, both pass transistors 207-1 and 207-2 are activated (as described above, in subsequent phases of a NAND operation only one of the pass transistors (e.g., 207-1) is activated during accumulate operations). At time t5, the accumulator control signals 212-1 (Accumb) and 212-2 (Accum) are activated. As described above, in subsequent phases of a NAND operation, the accumulator control signals 212-1 and 212-2 would already be activated. As such, in this example, activating the control signals 212-1 and 212-2 activates the accumulator. If the accumulator was previously activated, then activating passd 211 results in accumulating the data value corresponding to the voltage signal 205-1.
At time t6, the pass transistors 207-1 and 207-2 are deactivated; however, since the accumulator control signals 212-1 and 212-2 remain activated, an accumulated result is stored (e.g., latched) in the accumulator. At time t7, the row signal 204 is deactivated, and the array sense amps are deactivated at time t8 (e.g., sense amp control signals 228 and 231 are deactivated).
At time t9, the sense lines D and D_ are equilibrated (e.g., equilibration signal 226 is activated), as illustrated by sense line voltage signals 205-1 and 205-2 moving from their respective rail values to the equilibration voltage 225 (VDD/2). The equilibration consumes little energy due to the law of conservation of energy.
The example logic operation phase described in association with FIG. 2 involves accumulating a data value (e.g., a data value sensed from a memory cell and/or a data value corresponding to a voltage or current of a sense line). Due to conservation of energy, the energy consumed in performing the logic operation phase is approximately equal to the energy consumed during charging of the capacitance of the sense line D or D_ from VDD/2 to VDD, which begins at time t3 (e.g., when the sense amp is fired). As such, a logical operation is performed that consumes approximately the energy used to charge a sense line (e.g., digit line) from VDD/2 to VDD. In contrast, various previous processing approaches consume at least an amount of energy used to charge a sense line from rail to rail (e.g., from ground to VDD.
In operation, when a memory cell is being sensed (e.g., read), the voltage on one of the sense lines D, D_ will be slightly greater than the voltage on the other one of sense lines D, D_. The PSA signal is then driven high and the RNL_signal is driven low to enable the sense amplifier 306. The sense line D, D_ having the lower voltage will turn on one of the PMOS transistor 329-1, 329-2 to a greater extent than the other of PMOS transistor 329-1, 329-2, thereby driving high the sense line D, D_ having the higher voltage to a greater extent than the other sense line D, D_ is driven high. Similarly, the sense line D, D_ having the higher voltage will turn on one of the NMOS transistor 327-1, 327-2 to a greater extent than the other of the NMOS transistor 327-1, 327-2, thereby driving low the sense line D, D_ having the lower voltage to a greater extent than the other sense line D, D_ is driven low. As a result, after a short delay, the sense line D, D_ having the slightly greater voltage is driven to the voltage of the PSA signal (which can be the supply voltage Vcc), and the other sense line D, D_ is driven to the voltage of the RNL_signal (which can be a reference potential such as a ground potential). Therefore, the cross coupled NMOS transistors 327-1, 327-2 and PMOS transistors 329-1, 329-2 serve as a sense amp pair, which amplify the differential voltage on the sense lines D and D_ and serve to latch a data value sensed from the selected memory cell. As used herein, the cross coupled latch of sense amp 306 may be referred to as a primary latch. In contrast, and as described above in connection with FIG. 2, a cross coupled latch associated with a compute component (e.g., compute component 231 shown in FIG. 2) may be referred to as a secondary latch.
sensing circuitry comprising a sense amplifier and a compute component coupled to a column of an array of memory cells, the column comprising a sense line; and
a controller configured to use the sensing circuitry to perform a logical operation by using a first data value on the sense line at a first point in time as a first input and a second data value on the sense line at a second point in time as a second input.
2. The apparatus of claim 1, wherein the sense amplifier comprises a first latch and the compute component comprises a second latch.
3. The apparatus of claim 1, wherein the controller is configured to use the sensing circuitry to perform the logical operation without activating a column decode signal.
4. The apparatus of claim 1, wherein the controller is further configured to cause the sensing circuitry to store a result of the logical operation in a memory cell coupled to the sense line.
5. The apparatus of claim 1, wherein the controller is further configured to cause a result of the logical operation to be transferred from the sense amplifier and/or the compute component external to the sensing circuitry and the array.
6. The apparatus of claim 1, wherein the logical operation is a Boolean operation.
7. The apparatus of claim 1, wherein the logical operation is a non-Boolean operation.
8. The apparatus of claim 1, wherein the sensing circuitry is configured to sense the first data value from a first memory cell coupled to the sense line and is configured to sense the second data value from a different memory cell coupled to the sense line.
9. The apparatus of claim 1, wherein the sense line is a first sense line of a pair of complementary sense lines corresponding to the column, and wherein the compute component comprises:
a first pass transistor coupled to the first sense line and a second pass transistor coupled to a second sense line of the pair of complementary sense lines;
a first n-channel transistor of a pair of cross coupled n-channel transistors coupled to the first pass transistor and a second n-channel transistor of the pair of cross coupled n-channel transistors coupled to the second pass transistor; and
a first p-channel transistor of a pair of cross coupled p-channel transistors coupled to the first pass transistor and a second p-channel transistor of the pair of cross coupled p-channel transistors coupled to the second pass transistor.
10. The apparatus of claim 9, wherein the compute component further comprises:
a first pull down transistor coupled to the first sense line and a second pull down transistor coupled to the second sense line;
a third pull down transistor coupled the first pull down transistor and to a gate of the second n-channel transistor, which is coupled to a gate of the second p-channel transistor; and
a fourth pull down transistor coupled to the second pull down transistor and to a gate of the first n-channel transistor, which is coupled to a gate of the first p-channel transistor.
a sense amplifier coupled to a pair of complementary sense lines of an array of memory cells;
a compute component comprising a latch configured to serve as an accumulator and coupled to the sense amplifier via a pair of pass transistors; and
a controller configured to provide signals to the sense amplifier and the compute component in association with performing a compute function that comprises performing a logical operation on a data value represented by a signal on at least one of the pair of complementary sense lines.
12. The apparatus of claim 11, wherein the compute component comprises a plurality of transistors formed on pitch with memory cells corresponding to a column of the array.
a first source/drain region of a first pass transistor of the pair of pass transistors is coupled to a first sense line of the pair of complementary sense lines;
a first source/drain region of a second pass transistor of the pair of pass transistors is coupled to a second sense line of the pair of complementary sense lines;
the latch comprises a first pair of cross coupled transistors and a second pair of cross coupled transistors;
a second source/drain region of the second pass transistor is commonly coupled to a gate of a first transistor of the first pair of cross coupled transistors, a gate of a first transistor of the second pair of cross coupled transistors, and a first source/drain region of a second transistor of the first pair of cross coupled transistors; and
a second source/drain region of the first pass transistor is commonly coupled to a gate of the second transistor of the first pair of cross coupled transistors, a gate of a second transistor of the second pair of cross coupled transistors, and a first source/drain region of the first transistor of the first pair of cross coupled transistors.
14. The apparatus of claim 13, wherein the apparatus is configured to perform the accumulate operation by applying an active control signal to at least one of a gate of the first pass transistor and a gate of the second pass transistor while applying an active control signal to a second source/drain region of the first pair of cross coupled transistors and while applying an active control signal to a second source/drain region of the second pair of cross coupled transistors.
15. The apparatus of claim 11, wherein the apparatus is configured to:
drive a result of the logical operation from the latch to the pair of complementary sense lines through one of the first and the second pass transistor;
amplify the result via the sense amplifier; and
responsive to a read request, transfer the result from the sense amplifier via an input/output line without accessing data stored in the array.
determining data values stored in memory cells coupled to a first access line of an array of memory cells, the memory cells being coupled to respective columns of the array, with the columns having corresponding respective sensing circuitries each comprising a sense amplifier and corresponding compute component; and
performing, in parallel, logical operations using the determined data values as a plurality of first inputs and data values stored in memory cells coupled to a second access line of the array as respective second inputs, the memory cells coupled to the second access line are coupled to corresponding respective columns of the array; and
storing results of the logical operations in respective compute components of the corresponding respective columns.
17. The method of claim 16, wherein determining data values stored in memory cells coupled to the first access line of the array comprises sensing the memory cells coupled to the first access line by enabling the first access line and storing the data values in respective sense amplifiers of the corresponding columns.
18. The method of claim 17, wherein performing, in parallel, logical operations using the determined data values as the plurality of first inputs and data values stored in memory cells coupled to the second access line of the array as respective second inputs comprises, copying the determined data values from the respective sense amplifiers to respective corresponding compute components.
19. The method of claim 18, wherein the respective sense amplifiers comprise respective primary latches and the corresponding compute components comprise respective secondary latches, and wherein copying the determined data values from the respective sense amplifiers to respective corresponding compute components comprises enabling the respective secondary latches while enabling pairs of pass transistors corresponding to the respective columns.
20. The method of claim 19, wherein performing, in parallel, logical operations using the determined data values as the plurality of first inputs and data values stored in memory cells coupled to the second access line of the array as respective second inputs further comprises:
subsequent to copying the determined data values from the respective sense amplifiers to respective corresponding compute components, maintaining the respective secondary latches in an enabled condition while sensing the memory cells coupled to the second access line; and
subsequent to sensing the memory cells coupled to the second access line, enabling only one pass transistor of each of the respective pairs of pass transistors such that the results of the logical operations are stored in the respective compute components.
US15270761 2013-03-04 2016-09-20 Apparatuses and methods for performing logical operations using sensing circuitry Active 2033-03-20 US9892766B2 (en)
US13784219 US9158667B2 (en) 2013-03-04 2013-03-04 Apparatuses and methods for performing logical operations using sensing circuitry
US14878452 US9472265B2 (en) 2013-03-04 2015-10-08 Apparatuses and methods for performing logical operations using sensing circuitry
US15270761 US9892766B2 (en) 2013-03-04 2016-09-20 Apparatuses and methods for performing logical operations using sensing circuitry
US15688545 US9959913B2 (en) 2013-03-04 2017-08-28 Apparatuses and methods for performing logical operations using sensing circuitry
US15965733 US20180247679A1 (en) 2013-03-04 2018-04-27 Apparatuses and methods for performing logical operations using sensing circuitry
US14878452 Continuation US9472265B2 (en) 2013-03-04 2015-10-08 Apparatuses and methods for performing logical operations using sensing circuitry
US15688545 Continuation US9959913B2 (en) 2013-03-04 2017-08-28 Apparatuses and methods for performing logical operations using sensing circuitry
US20170011782A1 true US20170011782A1 (en) 2017-01-12
US9892766B2 true US9892766B2 (en) 2018-02-13
US13784219 Active 2033-08-24 US9158667B2 (en) 2013-03-04 2013-03-04 Apparatuses and methods for performing logical operations using sensing circuitry
US14878452 Active US9472265B2 (en) 2013-03-04 2015-10-08 Apparatuses and methods for performing logical operations using sensing circuitry
US15270761 Active 2033-03-20 US9892766B2 (en) 2013-03-04 2016-09-20 Apparatuses and methods for performing logical operations using sensing circuitry
US15688545 Active US9959913B2 (en) 2013-03-04 2017-08-28 Apparatuses and methods for performing logical operations using sensing circuitry
US15965733 Pending US20180247679A1 (en) 2013-03-04 2018-04-27 Apparatuses and methods for performing logical operations using sensing circuitry
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