Source: http://www.google.com/patents/US7880179?dq=oakley+5,387,949&ei=4yI4T8nkLYa80QG0xqnWAg
Timestamp: 2016-09-25 14:10:31
Document Index: 598385513

Matched Legal Cases: ['Application No. 02796172', 'Application No. 02816578', 'Application No. 7002747', 'Application No. 2003', 'Application No. 2003', 'Application No. 2003']

Patent US7880179 - Process for making contact with and housing integrated circuits - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished...http://www.google.com/patents/US7880179?utm_source=gb-gplus-sharePatent US7880179 - Process for making contact with and housing integrated circuitsAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7880179 B2Publication typeGrantApplication numberUS 12/623,323Publication dateFeb 1, 2011Filing dateNov 20, 2009Priority dateAug 24, 2001Fee statusPaidAlso published asCN1547778A, CN100578816C, CN101714516A, EP1419534A2, EP2287916A2, EP2287916A3, US6911392, US7700957, US7821106, US8349707, US20030113979, US20050042786, US20080150063, US20100065883, US20110021002, US20130137259, WO2003019653A2, WO2003019653A3Publication number12623323, 623323, US 7880179 B2, US 7880179B2, US-B2-7880179, US7880179 B2, US7880179B2InventorsDipl.-Ing. Florian Bieck, J�rgen LeibOriginal AssigneeWafer-Level Packaging Portfolio LlcExport CitationBiBTeX, EndNote, RefManPatent Citations (46), Non-Patent Citations (16), Referenced by (4), Classifications (81), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetProcess for making contact with and housing integrated circuits
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Gore & Associates, Inc.Wafer level contact sheet and method of assemblyUS5807783Oct 7, 1996Sep 15, 1998Harris CorporationSurface mount die by handle replacementUS5814889Jun 5, 1995Sep 29, 1998Harris CorporationIntergrated circuit with coaxial isolation and methodUS5965933May 28, 1996Oct 12, 1999Young; William R.Semiconductor packaging apparatusUS6114191Dec 3, 1998Sep 5, 2000Intersil CorporationSemiconductor packaging methodUS6171887May 4, 1999Jan 9, 2001Kabushiki Kaisha ToshibaSemiconductor device for a face down bonding to a mounting substrate and a method of manufacturing the sameUS6338284Feb 12, 1999Jan 15, 2002Integrated Sensing Systems (Issys) Inc.Electrical feedthrough structures for micromachined devices and methods of fabricating the sameUS6384353Feb 1, 2000May 7, 2002Motorola, Inc.Micro-electromechanical system deviceUS6393183Aug 17, 1999May 21, 2002Eugene Robert WorleyOpto-coupler device for packaging optically coupled integrated circuitsUS6448168Apr 14, 2000Sep 10, 2002Intel CorporationMethod for distributing a clock on the silicon backside of an integrated circuitUS6461888Jun 14, 2001Oct 8, 2002Institute Of MicroelectronicsLateral polysilicon beam processUS6489675Apr 13, 2000Dec 3, 2002Infineon Technologies AgOptical semiconductor component with an optically transparent protective layerUS6501182Jun 25, 2001Dec 31, 2002Murata Manufacturing Co., Ltd.Semiconductor device and method for making the sameUS6503793Aug 10, 2001Jan 7, 2003Agere Systems Inc.Method for concurrently forming an ESD protection device and a shallow trench isolation regionUS6515355Sep 2, 1998Feb 4, 2003Micron Technology, Inc.Passivation layer for packaged integrated circuitsUS6541987Aug 30, 1999Apr 1, 2003Advanced Micro Devices, Inc.Laser-excited detection of defective semiconductor deviceUS6580858Apr 30, 2001Jun 17, 2003Xerox CorporationMicro-opto-electro-mechanical system (MOEMS)US6703689Jul 10, 2001Mar 9, 2004Seiko Epson CorporationMiniature optical element for wireless bonding in an electronic instrumentUS6911392Aug 26, 2002Jun 28, 2005Schott GlasProcess for making contact with and housing integrated circuitsUS20020028537Aug 6, 2001Mar 7, 2002Farnworth Warren M.Hermetic chip and method of manufactureUS20020135069Mar 23, 2001Sep 26, 2002Wood Robert L.Electroplating methods for fabricating microelectronic interconnectsUS20030001240Jul 2, 2001Jan 2, 2003International Business Machiness CorporationSemiconductor devices containing a discontinuous cap layer and methods for forming sameUS20030092243May 4, 2001May 15, 2003New Mexico Tech Research FoundationMethod for anodically bonding glass and semiconducting material togetherDE4314907C1May 5, 1993Aug 25, 1994Siemens AgMethod for producing semiconductor components making electrically conducting contact with one another verticallyDE19746641A1Oct 22, 1997Apr 1, 1999Fraunhofer Ges ForschungVerdrahtungsverfahren f�r Halbleiter-Bauelemente zur Verhinderung von Produktpiraterie und Produktmanipulation, durch das Verfahren hergestelltes Halbleiter-Bauelement und Verwendung des Halbleiter-Bauelements in einer ChipkarteDE19846232A1Oct 7, 1998Mar 9, 2000Fraunhofer Ges ForschungBack face contacted semiconductor device, e.g. an ion-sensitive FET, is produced by metabolizing a back face contact hole for contacting a connection region or metallization level of a front face circuit structureDE19918671A1Apr 23, 1999Nov 2, 2000Giesecke & Devrient GmbhVertikal integrierbare Schaltung und Verfahren zu ihrer HerstellungDE19958486A1Dec 4, 1999Dec 7, 2000Fraunhofer Ges ForschungVerfahren zur vertikalen Integration von elektrischen Bauelementen mittels R�ckseitenkontaktEP0810659A2May 9, 1997Dec 3, 1997Harris CorporationSemiconductor packaging apparatus and methodJP2000195861A Title not availableJP2001177081A Title not availableJP2001351997A Title not availableJPH0321859A Title not availableJPH06113214A Title not availableJPH10335337A Title not availableWO1994017557A1Jan 10, 1994Aug 4, 1994Hughes Aircraft CompanyThermally matched readout/detector assembly and method for fabricating sameWO1998052225A1May 13, 1998Nov 19, 1998Chipscale, Inc.An electronic component package with posts on the active surfaceWO1999040624A1Feb 3, 1999Aug 12, 1999Shellcase Ltd.Integrated circuit deviceWO2001080285A2Apr 12, 2001Oct 25, 2001Honeywell International Inc.Top illuminated opto-electronic devices integrated with micro-optics and electronic integrated circuitsNon-Patent CitationsReference1"ShellCase Ultrathin Chip Size Package," 1999 International Symposium on Advanced Packaging Materials, Jerusalem, Israel, pp. 236-240.2A Plated Through Interconect Tecnology in Silicon. By Maha A. S. Jaafar and Denice D. Denton. Jul. 7, 1997.3Clearfield, et al., "Wafer-level Chip Scale Packaging: Benefits for Integrated passive Devices," May 2, 2000.4European Office Action dated Nov. 7, 2006.5European Search Report dated Feb. 23, 2010 for corresponding European Patent Application No. 02796172.1 (w/ translation).6Future Sytem-On-Silicon LDI Chips. By Mitsumasa Koyanangi et al. 1998.7Influence of the Grain Boundries and Intagrain Defects on the Performance of Poly-Si Thin Film Transistors. By Yoshihiro Morimoto et al. Jul. 7, 1997.8International Preliminary Exam Report dated Mar. 31, 2004 corresponding to International Patent Application No. PCT/EP02/09498.9Office Action dated Aug. 25, 2006 corresponding to Chinese Patent Application No. 02816578.0.10Office Action dated Feb. 23, 2006 corresponding to Korean Patent Application No. 7002747/2004.11Office Action dated Jul. 17, 2008 corresponding to Japanese Patent Application No. 2003-523003.12Office Action dated May 8, 2009 corresponding to Japanese Patent Application No. 2003-523003.13Office Action dated Sep. 26, 2007 corresponding to Japanese Patent Application No. 2003-523003.14Packaging of VCSEL Arrays for Cost-Effective Interconnects at <10 Meters; Hibbs et al., 1999.15Vertical Integration of Silicon Allows Packaging of Extremely Dense System Memory in Tiny Volumes Memory-Chip Stackes Send Destiny Skyward. By David Maliniak. Aug. 22, 1994.16Wafer-Level Processing Cuts Chip-Scale packaging Cost. By David Morrison. Oct. 18, 1999.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8188604 *Mar 2, 2009May 29, 2012Oki Semiconductor Co., Ltd.Semiconductor device incorporating preventative measures to reduce cracking in exposed electrode layerUS8564141 *Mar 2, 2011Oct 22, 2013SK Hynix Inc.Chip unit and stack package having the sameUS20090230563 *Mar 2, 2009Sep 17, 2009Shigeru YamadaSemiconductor device and method of manufacturing the sameUS20110272798 *Nov 10, 2011Hynix Semiconductor Inc.Chip unit and stack package having the same* Cited by examinerClassifications U.S. Classification257/82, 257/E31.058, 257/777, 257/723, 257/81, 257/432International ClassificationH01L21/00, H01L27/15, H01L, H01L23/00, H01L21/44, H01L31/02, H01L25/16, H01L21/76, H01L31/0203, H01L21/3205, H01L23/12, H01L21/768, H01L23/52, H01L27/146, H01L23/485, H01L23/31Cooperative ClassificationH01L2224/0401, H01L25/0657, H01L27/14683, H01L2225/06541, H01L2224/13025, H01L2221/68363, H01L2225/06572, H01L27/14636, H01L2924/01039, H01L2225/06582, H01L2924/01013, H01L2924/01019, H01L2924/14, H01L2924/01006, H01L2924/01082, H01L2924/3025, H01L21/76877, H01L2924/0102, H01L2924/01068, H01L21/76898, H01L2924/01015, H01L2924/0106, H01L27/14634, H01L2924/01032, H01L23/3114, H01L27/14618, H01L31/0203, H01L24/13, H01L27/1469, H01L2924/3511, H01L2924/01005, H01L2924/01004, H01L24/14, H01L2924/01074, H01L2224/16, H01L2225/06513, H01L2224/13099, H01L24/94, H01L2924/01023, H01L2924/014, H01L2924/01058, H01L2924/01029, H01L2924/01078, H01L2924/01033, H01L2924/10329, H01L2924/01075, H01L2924/01057, H01L2224/13024, H01L2224/02372European ClassificationH01L21/768T, H01L23/31H1, H01L24/10, H01L24/13, H01L27/146A6, H01L27/146V, H01L31/0203, H01L24/94, H01L25/065S, H01L24/14Legal EventsDateCodeEventDescriptionSep 30, 2010ASAssignmentOwner name: SCHOTT ELECTRONIC PACKAGING ASIA PTE. LTD., SINGAPFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SCHOTT AG;REEL/FRAME:025066/0719Effective date: 20070725Oct 1, 2010ASAssignmentOwner name: WAFER-LEVEL PACKAGING PORTFOLIO LLC, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SCHOTT ELECTRONIC PACKAGING ASIA PTE. LTD.;REEL/FRAME:025077/0418Effective date: 20080722Jul 2, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services