Source: http://www.google.com/patents/US7053594?dq=6,260,087
Timestamp: 2016-09-28 00:11:25
Document Index: 651301627

Matched Legal Cases: ['Application No. 04023251', 'Application No. 04023259', 'Application No. 04023192', 'Application No. 04023249', 'Application No. 04023234', 'Application No. 04023247']

Patent US7053594 - Adaptive duty cycle limiter and method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA duty cycle limiter for limiting a transfer of energy between an input source and a regulated output of an output regulator. The output regulator having a regulator characteristic and a computed duty cycle for controlling the transfer of energy between the input source and the regulated output. The...http://www.google.com/patents/US7053594?utm_source=gb-gplus-sharePatent US7053594 - Adaptive duty cycle limiter and methodAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7053594 B2Publication typeGrantApplication numberUS 10/827,645Publication dateMay 30, 2006Filing dateApr 19, 2004Priority dateJul 10, 2002Fee statusPaidAlso published asCN1603998A, CN1603999A, CN1604000A, CN1604001A, CN1604001B, CN1604002A, CN1604445A, CN1607716A, CN1607717A, CN1639659A, CN1664737A, CN100380798C, CN100392551C, CN100392552C, CN100392971C, CN100407086C, CN100416442C, CN100416998C, CN100440097C, CN100440098C, DE60323498D1, DE60323499D1, DE60323501D1, DE60324148D1, DE60334102D1, DE60336816D1, DE60336817D1, DE60336818D1, DE60337012D1, EP1532501A2, EP1532501B1, US6894465, US6933711, US6977492, US6979988, US7009372, US7023192, US7042202, US7358711, US7368898, US7411377, US7573249, US7609043, US7622904, US7863880, US20040008016, US20040155640, US20040178785, US20040183510, US20040196015, US20040196016, US20040196017, US20040196018, US20040239300, US20050156581, US20060022657, US20080030176, US20080030182, US20080186014, WO2004006037A2, WO2004006037A3Publication number10827645, 827645, US 7053594 B2, US 7053594B2, US-B2-7053594, US7053594 B2, US7053594B2InventorsSehat Sutardja, Runsheng He, Jiancheng ZhangOriginal AssigneeMarvell World Trade Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (49), Non-Patent Citations (26), Referenced by (16), Classifications (32), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetAdaptive duty cycle limiter and method
US 7053594 B2Abstract
A duty cycle limiter for limiting a transfer of energy between an input source and a regulated output of an output regulator. The output regulator having a regulator characteristic and a computed duty cycle for controlling the transfer of energy between the input source and the regulated output. The duty cycle limiter including a digital controller to generate a reference level and to compare the regulator characteristic of the output regulator to the reference level to determine a maximum duty cycle. The digital controller to control the reference level at a frequency at least equal to a switching frequency of the output regulator. The digital controller to limit the computed duty cycle to the maximum duty cycle.
1. A duty cycle limiter for limiting a transfer of energy between an input source and a regulated output of an output regulator, the output regulator having a regulator characteristic and a computed duty cycle for controlling the transfer of energy between the input source and the regulated output, comprising:
a digital controller to generate a reference level and to compare the regulator characteristic of the output regulator to the reference level to determine a maximum duty cycle, the digital controller to control the reference level at a frequency at least equal to a switching frequency of the output regulator; and
the digital controller to limit the computed duty cycle to the maximum duty cycle.
2. The duty cycle limiter of claim 1 wherein the regulator characteristic is selected from a group consisting of input power and output power.
3. The duty cycle limiter of claim 2 wherein the input power includes input current, input voltage, input ripple voltage, and input energy.
4. The duty cycle limiter of claim 1 wherein the computed duty cycle signal includes a multi-bit digital signal.
5. The duty cycle limiter of claim 1 wherein the computed duty cycle signal includes a variable pulse width signal.
6. The duty cycle limiter of claim 1 wherein the digital controller controls the reference level at a frequency approximately ranging between the switching frequency and a sampling frequency.
7. The duty cycle limiter of claim 1 further including a duty cycle estimator for determining a nominal duty cycle, the computed duty cycle determined based on the nominal duty cycle, the duty cycle estimator comprising;
a mode one estimator to determine the nominal duty cycle as a function of prior duty cycles.
8. The duty cycle limiter of claim 7 wherein the duty cycle estimator further includes a mode two estimator to determine the nominal duty cycle as a function of accumulated error; and
a mode selector to, based on a mode selection criteria, select a one of the at least two modes to generate the nominal duty cycle.
9. The duty cycle limiter of claim 7 further including an adjust determiner to determine an adjustment value to combine with the nominal duty cycle to generate the computed duty cycle.
10. A duty cycle limiter for limiting a transfer of energy between an input source and a regulated output of an output regulator, the output regulator having a regulator characteristic and a computed duty cycle for controlling the transfer of energy between the input source and the regulated output, comprising:
means for digital controlling to generate a reference level and to compare the regulator characteristic of the output regulator to the reference level to determine a maximum duty cycle, the means for digital controlling to control the reference level at a frequency at least equal to a switching frequency of the output regulator; and
the means for digital controlling to limit the computed duty cycle to the maximum duty cycle.
11. The duty cycle limiter of claim 10 wherein the regulator characteristic is selected from a group consisting of input power and output power.
12. The duty cycle limiter of claim 11 wherein the input power includes input current, input voltage, input ripple voltage, and input energy.
13. The duty cycle limiter of claim 10 wherein the computed duty cycle signal includes a multi-bit digital signal.
14. The duty cycle limiter of claim 10 wherein the computed duty cycle signal includes a variable pulse width signal.
15. The duty cycle limiter of claim 10 wherein the means for digital controlling controls the reference level at a frequency approximately ranging between the switching frequency and a sampling frequency.
16. The duty cycle limiter of claim 10 further including means for estimating duty cycle to determine a nominal duty cycle, the computed duty cycle determined based on the nominal duty cycle, the means for estimating duty cycle comprising;
means for mode one estimating to determine the nominal duty cycle as a function of prior duty cycles.
17. The duty cycle limiter of claim 16 wherein the means for estimating duty cycle further includes means for mode two estimating to determine the nominal duty cycle as a function of accumulated error; and
means for mode selecting to, based on a mode selection criteria, select a one of the first mode and the second mode to generate the nominal duty cycle.
18. The duty cycle limiter of claim 16 further including means for determining duty cycle adjustment to determine an adjustment value to combine with the nominal duty cycle to generate the computed duty cycle.
19. A method for limiting a transfer of energy between an input source and a regulated output of an output regulator, the output regulator having a regulator characteristic and a computed duty cycle for controlling the transfer of energy between the input source and the regulated output, comprising:
generating a reference level;
comparing the regulator characteristic of the output regulator to the reference level to determine a maximum duty cycle;
controlling the reference level at a frequency at least equal to a switching frequency of the output regulator; and
limiting the computed duty cycle to the maximum duty cycle.
20. The method of claim 19 wherein the regulator characteristic is selected from a group consisting of input power and output power.
21. The method of claim 20 wherein the input power includes input current, input voltage, input ripple voltage, and input energy.
22. The method of claim 19 wherein the computed duty cycle signal includes a multi-bit digital signal.
23. The method of claim 19 wherein the computed duty cycle signal includes a variable pulse width signal.
24. The method of claim 19 wherein the frequency is approximately between the switching frequency and a sampling frequency.
25. The method of claim 19 further including a mode one including determining a nominal duty cycle as a function of prior duty cycles; and
determining the computed duty cycle based on the nominal duty cycle.
26. The method of claim 25 further including a mode two including determining the nominal duty cycle as a function of accumulated error; and
selecting, based on a mode selection criteria, a one of the first mode and the second mode to generate the nominal duty cycle.
27. The method of claim 25 further including determining an adjustment value to combine with the nominal duty cycle to generate the computed duty cycle.
28. The duty cycle limiter of claim 1 included in the output regulator.
29. The duty cycle limiter of claim 10 included in the output regulator.
This application is a divisional of application Ser. No. 10/460,825, filed Jun. 12, 2003 which claims the benefit of the filing date of U.S. provisional applications Nos. 60/395,115 filed Jul. 10, 2002, and No. 60/395,697 filed Jul. 12, 2002, the entire contents of which are herein incorporated by reference.
A voltage sensor 118 may sense the voltage at VL. The voltage sensor 118 may generate a digital output based on the sensed voltage. The digital output of VL may be 2 or more bits. The VL information may be used for control and protection such as indirectly sensing current through the lower power array 114 b. A delay line 120 may fine tune the estimated duty cycle computed by the digital controller 102. The delay line 120 may generate a delay signal to lengthen the estimated duty cycle. For example, the estimated duty cycle may be computed as an integer multiple of a clock pulse width and the delay line 120 may vary the estimated duty cycle by increments that are less than the clock pulse width. The delay line 120 may receive a digital signal of one or more bits such as a multibit digital signal, and generate a pulse with a controlled pulse width. Any type of pulse stretching technique may be employed. In addition, the delay line 120 may include dithering to generate fractional increments. In an exemplary system, delay line 120 may generate a minimum increment resolution that is equal to “t1”, and by applying dithering, the average of the generated pulse may be pulse stretched by any fractional portion of “t1”. In one dithering method, a selected number of pulses within the continuing series of pulses may be stretched by an integer “N” number of increments, and the remaining pulses in the series of pulses may be stretched by an integer “N−1” or “N+1” number of increments to generate a pulse that is fractionally stretched.
FIG. 4 shows an aspect of a package configuration for the voltage converter 100. The package configuration advantageously reduces susceptibility to noise generated from the operation of the voltage converter 100. A package 200 includes a digital controller and power switches for controlling the flow of energy in the voltage converter 100. The pin configuration of the package 200 provides for improved routing of traces associated with the voltage converter 100. A return pin 202 may be located along a first side of the package 200. The return pin 202 provides a return current path for current flowing to Vout. A Vin pin 204 and a center-tap pin, CT, 206 may be located along a second side of the package 200. Pins 208–212 for control Input/Output (I/O) may be located along a third side of the package 200. Control I/O may include a functions such as frequency compensation, Cf, and output voltage selection, R1 and R2.
FIG. 12A shows an aspect of a power array 500 to generate a chopped voltage from an input voltage. The power array 500 may be included in a power regulator such as power regulator 10 described in this specification. The power array 500 may include one or more switch arrays 502 a and 502 b of power switches Q1–Q8 to control the flow of energy between two nodes. The power switches Q1–Q8 may each operate independently in two states, an on state and an off state. In the on state, the power switch has a low impedance and conducts energy between the two nodes. In the off state, the power switch has a high impedance and blocks the flow of energy between the two nodes. Any quantity and type of switching device may be used for the power switches such as MOSFETs, BJTs, MCTs, IGBTs, and Radio Frequency (RF) FETs. The power switches Q1–Q8 may include any mixture of sizes such as for MOSFETs, one device may have an Rds(on) of 0.1 ohm while other devices have an Rds (on) of 0.2 ohm and 0.4 ohm respectively.
ADJk =g(e k)+h(trendk)
Upk=Up*−ADJk*FACon
Downk=Down*+ADJk*FACoff
g ( e k ) = { 0 if  e k  < A1 sign ( e k ) * Δ 1 if A1 ≤  e k  < A2 sign ( e k ) * Δ 2 if A2 ≤  e k  < A3 h ( trend k ) = { 0 if  trend k  < 1 trend k if  trend k  ≥ 1 trend k = F slope * e k - e k - n _ where Fslope is a constant, {overscore (ek−ek-n)} is an average of the error from the “n” prior cycles where “n” is the number of samples in a switching period, and
where Up*1 is the up value generated by the mode 1 estimator 972, Up*2 is the up value generated by the mode 2 estimator 974, and Up*prior is the Up* value for the prior cycle, and T1 may be approximately 5 nsec for a switching frequency of 1 MHz.
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