Source: http://www.google.com/patents/US20050231515?dq=5,583,822
Timestamp: 2017-12-12 19:01:42
Document Index: 359661435

Matched Legal Cases: ['ART 420', 'ART 420', 'ART 420', 'ART 420', 'ART 420', 'ART 420']

Patent US20050231515 - Apparatus to map virtual pages to disparate-sized, non-contiguous real pages - Google Patents
A data processing system includes at least one system processor, chipset core logic, main memory to store computer software and data including operating system software, and a graphics address remapping table (GART). The chipset logic operates on first-sized real memory pages, while the operating system...http://www.google.com/patents/US20050231515?utm_source=gb-gplus-sharePatent US20050231515 - Apparatus to map virtual pages to disparate-sized, non-contiguous real pages
Publication number US20050231515 A1
Application number US 11/159,761
Also published as US6970992, US7117339, US20030200413
Publication number 11159761, 159761, US 2005/0231515 A1, US 2005/231515 A1, US 20050231515 A1, US 20050231515A1, US 2005231515 A1, US 2005231515A1, US-A1-20050231515, US-A1-2005231515, US2005/0231515A1, US2005/231515A1, US20050231515 A1, US20050231515A1, US2005231515 A1, US2005231515A1
Inventors Nagasubramanian Gurumoorthy, Shivaprasad Sadashivaiah
Apparatus to map virtual pages to disparate-sized, non-contiguous real pages
US 20050231515 A1
a memory coupled to the bus and capable of storing real pages of size X;
wherein the system processor and the graphics processor are capable of executing instructions of at least one application under an operating system organized in virtual pages of size Y, wherein Y is greater than X; and
a storage area capable of storing a page table comprising Z page table entries per virtual page, wherein Z=Y/X, and wherein each page table entry comprises a base address of a corresponding non-contiguous real page in the memory.
In an embodiment system processors 1 and 2 are Intel® Pentium® III processors commercially available from Intel Corporation. The AGP graphics processor 12 is an Intel® 740 graphics accelerator commercially available from Intel Corporation. Local graphics memory 14 is part of a graphics accelerator card commercially available from Intel Corporation.
Main memory can be implemented in any suitable commercially available memory system. In an embodiment main memory is implemented with synchronous dynamic random access memory (SDRAM) devices as, for example, in an Intel® 440BX motherboard commercially available from Intel Corporation.
In an embodiment the computer software for filling and maintaining the GART is implemented as a GART driver 38 (FIG. 1) which is integrated into the Windows® 64 operating system which is anticipated to be commercially available from Microsoft Corporation.
In an embodiment address translation logic is implemented by a suitable circuit component provided in the chipset core logic 10. Chipset core logic 10 comprises one or more logic devices and may take the form of an Intel® 82460GX chipset which is expected to be commercially available from Intel Corporation.
The 82460GX chipset is expected to include several integrated circuits. One chip is an Intel® 82460GX System Address and Control (SAC) integrated circuit which provides addressing functions. Other associated chips are a System Data Path (SDP) integrated circuit that provides data access functions, and a Graphics Expansion Bridge (GXB) integrated circuit providing AGP functions. Another chip is an Intel® I/O and Firmware Bridge (IFB) integrated circuit. This integrated circuit provides a PCI (Peripheral Component Interconnect)-to-ISA (Industry Standard Architecture) bridge function, a PCI-to-IDE (Integrated Device Electronics) function, a USB (Universal Serial Bus system bus) host/hub function, and an enhanced power management function.
In an embodiment, the system processors 401 and 402, chipset core logic 410, AGP graphics processor 412, local graphics memory 414, and main memory 430 may be similar to or identical to corresponding elements shown in FIG. 1. In other embodiments, these components may be different from the elements shown in FIG. 1
In an embodiment, the computer software for filling and maintaining the GART 420 is implemented as a GART driver 438, which may be integrated into an operating system, or alternatively it may be implemented as middleware.
A specific example of address translation involving disparate-sized pages will now be discussed with reference to FIG. 4. Assume that one of processors 401, 402, or 412 desires to access a memory location within a 16 KB-sized virtual page (e.g. an operating system page). Assume also that 4 KB is the size of real pages in main memory 430 that are supported by chipset core logic 410. In this example, main memory 430 is illustrated as comprising a plurality of 4 KB real pages, including pages Pi, P101-P104 (identified by reference numbers 451-454, respectively), and Pn.
As shown in FIG. 4, real pages 451-454 may be non-contiguous. As mapped, some or all of real pages 451-454 may be contiguous or non-contiguous within main memory 430.
The GART 420 entries provide a mapping of a single 16 KB virtual page Q2 to four 4 KB real pages 451-454, respectively, in main memory 430. As mentioned above, real pages 451-454 need not be contiguous, i.e. they need not be adjacent or arranged in sequence. In general, GART 420 is illustrated as comprising a plurality of entries, namely Mn entries. Let Mi represent the ith entry in GART 420. Each entry in GART 420 comprises an address that may represent, for example, a base address of a corresponding 4 KB real page in main memory 430.
If the memory access operation is to a virtual page Q2, one of the entries in GART 420 corresponding to page Q2 will be accessed, and that entry will comprise and/or identify the base address of corresponding 4 KB real page 451, 452, 453, or 454. Which GART entry 441-444 is accessed is determined by the memory controller in the memory access operation.
(1) // Each virtual page is mapped into Z
(2) //real pages.
(3) For (Index = 0; Index < Z; Index++)
(5) //GetRealPage() is an OS call available
(6) //for use by a GART driver in the OS.
(7) Pointer = GetRealPage()
(8) //Allocate one available real page that
(9) //may be located anywhere in memory.
(10) //Store the result in the Pointer variable.
(11) //The GART driver fills the Mi
(12) //entry in the GART table with the
(13) //starting address of the available real page.
(14) //Note that for a given virtual page, several
(15) //GART entries will be filled with the
(16) //addresses of smaller real pages
(17) //that can be anywhere (either contiguous
(18) //or non-contiguous) in the memory.
(19) FillUpGartEntry (Mi+Index, Pointer);
Lines (2-3), (5), and (12-13) together represent a loop that fills four entries in the GART for each virtual page, according to an embodiment wherein each virtual page is mapped to four real pages. Each entry contains the starting address of a real page in real memory. In an embodiment, the four GART entries for each virtual page are consecutive; in another embodiment, the four GART entries for each virtual page may not be consecutive.
In line (19), assume that Mi identifies the ith entry in the GART, and assume that we want to fill four GART entries beginning with the Mi entry. The function FillUpGartEntry performs this operation.
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U.S. Classification 345/520, 711/E12.059, 345/568
International Classification G06F12/10, G06F13/14
Cooperative Classification G06F12/1081, G06F12/1009, G06F2212/652
European Classification G06F12/10P, G06F12/10D