Source: https://patents.google.com/patent/DE69835807T2/en
Timestamp: 2020-05-25 13:17:14
Document Index: 634321356

Matched Legal Cases: ['art" 80', 'art 80', 'art 80', 'art 80', 'art 82', 'art 80', 'art 82', 'art 80', 'art 82', 'art 80', 'art" 100', 'art" 102', 'art 100', 'art 80', 'art 102', 'art 100', 'art 102', 'art 120', 'art 122', 'arts 120', 'art 122', 'art 120', 'art 120', 'art 140', 'art 100', 'art 140', 'art 150', 'art 122', 'art 122', 'art 141', 'art 151']

DE69835807T2 - Method and apparatus for clocking signal distribution to several bus nodes in a bus bridge - Google Patents
Method and apparatus for clocking signal distribution to several bus nodes in a bus bridge
DE69835807T2
DE69835807T2 DE1998635807 DE69835807T DE69835807T2 DE 69835807 T2 DE69835807 T2 DE 69835807T2 DE 1998635807 DE1998635807 DE 1998635807 DE 69835807 T DE69835807 T DE 69835807T DE 69835807 T2 DE69835807 T2 DE 69835807T2
DE1998635807
DE69835807D1 (en
N. Samir HULYALKAR
1997-12-30 Priority to US672 priority
2006-10-19 Publication of DE69835807D1 publication Critical patent/DE69835807D1/en
2007-04-12 Publication of DE69835807T2 publication Critical patent/DE69835807T2/en
The The present invention relates generally to bus bridges and in particular to a method and an apparatus for distributing of a clock signal via a number of serial bus nodes ("bridge portals") of an IEEE 1394 serial bus bridge, the a number of IEEE serial local Buses connects.
The IEEE 1394 standard (hereinafter sometimes simply referred to as "IEEE 1394") defines one serial bus technology for connecting consumer electronics and computer products, such as digital television receivers, personal computers, digital VCRs, digital ones Camcorders, printers, fax machines etc. IEEE 1394 (sometimes referred to as "firewire") currently the world's most accepted high-speed digital connection technology for connecting consumer electronics and computer products as it inexpensive, flexible and easy to use. The base IEEE 1394 standard defined serial data rates of 100 Mbps, 200 Mbps and 400 Mbps. A new IEEE 1394 subgroup (known as IEEEp l394.b ") is currently working on a backwards compatible one Extension to serial data rates up to 3.2 Gbps. IEEE 1394 can support asynchronous as well as synchronous data, thereby reducing it to this Way is ideally suited for Multimedia applications. In the April 1997 issue of "IEEE Spectrum" is mentioned that "if the" information superhighway "in the multimedia area get in, experts predict, that in 1394 the first and the last three meters of the highway run becomes"
IEEE 1394 currently defines a maximum wired distance or a length of 4.5 m. That way you can IEEE 1394 serial buses are actually just for connecting elements be used, which are close to each other. Such a system interconnected elements that are close to each other is mostly called "cluster". One Example of a cluster in a residential environment is a "multimedia island" that is a home entertainment cluster, a haum-computer cluster, a bedroom cluster, etc.
As in 1 As shown, it is possible to interconnect clusters via a wired or wireless connection. There are currently two main approaches to expanding the IEEE 1394 serial bus within a wired infrastructure.
A Approach, currently being considered by the IEEEp 1394.b subgroup is using of plastic optical fibers (POF) or unshielded Pairs (UTP category 5) of transmission lines to extend the IEEE 1394 serial bus with a wired IEEE 1394 serial bus extension for size distances to implement. This type of extension can be a distance from 50-100m to reach. Another approach, which is currently being considered by the IEEEp 1394.1 subgroup, is the IEEE 1394 serial bus to expand that a wired IEEE 1394 "bridge" between two different IEEE 1394 serial bus segments or clusters is created.
Recalling 1 Another approach to the IEEE 1394 serial bus extender is to create a wireless IEEE 1394 "bridge" between IEEE 1394 clusters. Such wireless IEEE 1394 bridges promise to capture usage and flexibility associated with an IEEE 1394 network. In general, wired IEEE 1394 bridges in new residential buildings can be expected to be the predominant approach, with IEEE 1394 "sockets" installed in each room. However, retrofitting such wired IEEE 1394 bridges in existing homes can be costly for many homes in terms of cost because of the extensive rewiring that will be required. In this way, wireless IEEE 1394 bridges, if reasonably priced, can provide a suitable alternative for such existing homes. Furthermore, it can be expected that wired and wireless solutions for expanding IEEE 1394 serial buses will coexist in the home environment in a complementary fashion.
It be noted that wireless bridges also have disadvantages. And indeed wireless bridges allow a lot lower data transfer rates as wired bridges, because of the inherent complexity of the implementation high-speed wireless connections. Furthermore, wireless bridges not cost-effectively scalable to higher data rates over wired ones Bridges. This is primary because the wireless frequency spectrum is a shared asset under FCC regulations with respect to the use. Such is for example the use of the 2.4 GHz band for spread spectrum communication limited, and hence the available Data rate to 2-4 Mbps limited (IEEE 802.11). transfers with a higher one Data rate (about 25-50 Mbps) are using a wireless asynchronous transfer mode (WATM) technology possible. transfers but with such a high data rate, using WATM technology is applied between 5.15-5.35 and 5.725 to 5.825 GHz use the NII band, which is much more expensive to implement, because the RF technology for this Frequencies currently not fully developed.
Out the above is likely It is clear that wireless IEEE 1394 bridges offer a variety of data rates which presupposes a requirement that wireless IEEE 1394 bridges should be able to support many data rates.
Anahand the 2 The general architecture of an IEEE 1394 bridge will now be described. In particular, the IEEE 1394 includes bridge 20 two or more bus nodes 22 , an implementation-specific switching system 24 and a cyclic clock 26 , Every bus node 22 is a single serial bus node which is for serial bus read out, bus write and bus lock requests from the related local IEEE 1394 serial bus connected thereto 30 reacts as described in document P 1394, draft 8.0v4, November 21, 1995. Every bus node 22 monitors all serial bus packets, asynchronous as well as isochronous, to determine which packets, if any, through the switching network 24 through to another bus node. The switching network 24 that is the bus node 22 connects to each other, is capable of serial bus packets from the one bus node 22 to another bus node 22 using wired and / or wireless transmission means. Within a local IEEE 1394 serial bus, it is necessary for a common clock signal to be distributed over all nodes on that bus. The main reason for this synchronization request is to allow time stamping of real-time data at the source, which can be used to significantly reduce the timing jitter caused by the fact that the network is not always available for transmission (because it is shared) ,
In a local one IEEE 1394 serial bus leads a cycle master (or "root node ") this function by. The cycle master is responsible for the synchronization of all Node with the local bus are connected, on a 125 microsecond clock signal. At the beginning each cycle, the cycle master sends a special one to each of the nodes asynchronous packet, referred to as "cycle_startup_package". Each Zyk lus_Startpaket contains the current bus_time and will be in a cycle time register (CTR) each Knotens enrolled. Because the communication channel at the time, where the cycle master wants to send the Cycle_Start packet can be "busy" (it can For example, a user / node may have some data about that It is possible that the transmission of the Cycle_Startpakets is delayed by the time that the cycle master wait until the blocking transmission ends and the communication channel becomes available. Because the cycle master across from all other nodes priority such inevitable delays are minimized. Every knot, which receives the cycle_start packet, must immediately the counter update so that all nodes synchronize to the same cycle become.
This Clock signal must now over transmit the IEEE 1394 bridge wired as described above using or wireless means that can be implemented with a variety potential Data rates transfers. to Time, the IEEE p1394.1 subgroup does not consider the transmission the clock signal as part of their work, and thus is currently no documentation available, how to propagate this clock signal.
As As described above, in an IEEE 1394 bridge all bus node nodes are on a relevant local IEEE 1394 serial bus. Of all IEEE 1394 serial buses, the with the serial bus bridge One is the "cycle monster" that is a knot is, from which the clock signal over all IEEE 1394 serial buses are propagated. It should be noted that it is not necessary for the cycle monster to be a bus node is. In general, the bus node that is serial over the IEEE 1394 Bus connected to the cycle monster, referred to as "cycle monster portal". It should also be noted that all bus nodes, except possibly the cycle monster portal, Cycle masters are.
All Bus nodes in the IEEE 1394 serial bus bridge must become a common clock signal be synchronized with that for the IEEE 1394 bridge an isynchronous route is supported by real-time data. That way is there is a method of distributing the clock signal a request so that this synchronization request is met while also the time jitter, originating from the use of various wired or wireless switching networks, is minimized (which are implementation specific and hence vary). The present invention fulfills these requirements.
The present invention, in one of the aspects, comprises a bus bridge for interconnecting a number of buses, each comprising a number of bus nodes each coupled to a respective bus of the buses, a number of switching subsystems each coupled to a respective bus node. The many switching subsystems collectively form a switching system that connects the many bus nodes. The bus bridge further includes a number of clock signal subsystems, each of which is operatively associated with a respective bus node and the respective switching subsystem coupled thereto. Each clock signal sub The system comprises a clock signal generator which generates a clock signal and a cycle counter which receives the clock signal at an input thereof and which generates a cyclic counter output signal which forms a common time reference value for the relevant switching subsystem and the respective bus node. The bus bridge is preferably an IEEE 1394 serial bus bridge. The switching system may be a wired or a wireless switching system using a frame synchronization protocol. Several specific implementations of the switching subsystems and bus nodes are described.
The The present invention in another aspect comprises a method for distributing a clock signal in a bus bridge comprising a number of bus nodes which is each coupled to a respective bus of the buses; a number of switching subsystems, each with a respective Bus nodes are coupled, with the many switching subsystems collectively include a switching system that interconnects the many bus nodes combines. The method comprises. in each bus node the following Steps: generating a clock signal; using a cycle counter for Generating a cyclic counter output signal; and the use of the cyclic counter output signal to generate a common time reference value for the bus node and the relevant one coupled with switching subsystem.
1 a block diagram with wired and wireless connections of IEEE 1394 clusters among each other,
2 a block diagram of the general architelture of an IEEE 1394 serial bus bridge,
3 a block diagram of a clock signal subsystem for generating a cycle_start packet at a root node of an IEEE 1394 serial local bus,
4 a block diagram of a subsystem for processing a cycle_start packet at a receiver node of an IEEE 1394 serial local bus,
5 12 is a block diagram of a cycle monster portal, a wireless switching subsystem, and a clock signal subsystem according to a first preferred embodiment of the present invention;
6 12 is a block diagram of a cycle monster portal, a wireless switching subsystem, and a clock signal system according to a second preferred embodiment of the present invention;
7 3 is a block diagram of another bus node, a wireless switching subsystem, and a clock signal subsystem according to the present invention;
8th 12 is a block diagram of a cycle monster portal, a wireless switching subsystem, and a clock signal subsystem according to an alternative embodiment of the present invention, and
9 a block diagram of another bus node, a wireless switching subsystem and a clock signal subsystem according to an alternative embodiment of the present invention.
In 3 is a clock signal subsystem 40 illustrated for generating the cycle_start packet at a root node of a local IEEE 1394 serial bus. The clock signal subsystem 40 includes a crystal 42 which runs at a master clock rate of 24.576 MHz and provides a clock signal of 24.576 MHz to a cycle counter used to time mark the IEEE 1394 data packets according to the IEC 1883 standard. The goal is that the clock signal be distributed over all nodes connected to the local IEEE 1394 serial bus, such that the cycle counters within all nodes connected to the local IEEE 1394 serial bus are synchronized.
The output signal of the cycle counter 44 is via a modulo 125 μs block 46 forwarded, every 125 μs of a state machine 48 sends a time signal.
Upon receipt of the output signal of the modulo 125 μs block 46 sends the state machine 48 a channel request signal to a 1394 physical layer (PHY) 50 , As soon as the channel becomes available, the 1394 PHY transmits 50 a signal to the state machine 48 back that the channel is available. Upon receipt of the channel available signal, the state machine prepares 48 the packet header for the cycle_start packet and also sends a register 52 an enable signal, this register containing the contents of the cycle counter 44 locks at that time to generate the bus_time. A certain delay in processing can easily be taken into account be aware that the delivery of the enable signal to the register 52 is delayed in a suitable manner.
At each node that receives the Cycle_Start packet (which consists of the packet header and the Bus_Parts that have been transmitted by the root node), the cycle counter within the receiver node must be set to the correct Bus_Time, according to the received Cycle_Start packet. Such a reset technique of bus_time is in 4 shown. As in 4 As can be seen, the 1394 PHY layer receives 60 of the receiver node, the cycle_start packet transmitted by the root node, and thereafter it is supplied to the coupling layer. The receiver node then decodes the packet header of the cycle_start packet (in block 62 ) to ensure that the received packet is indeed the Cycle_Start packet. At the same time, the bus_time value is entered in the register 64 of the recipient node. Depending on the processing delay (either for decoding or for loading the bus_time value into the register 64 ), an appropriate processing delay is determined (in the block 66 ). The determined processing delay is provided by the adder 68 to the output of the register 64 and the output of the decoded cycle_start block 62 is by a delay element 70 delayed by the determined processing delay. The output signal of the delay element 70 forms a charging signal, which is the cycle counter 72 the receiver node is supplied. The charging signal allows the summing output signal to be loaded by the adder 68 in the cycle counter 72 , The cycle counter 72 becomes the clock output of the 24.576 MHz crystal 75 Updated the recipient node. The update of the cycle counter 72 every 125 μs ensures that the clock signals received from the respective crystals in different nodes do not drift strongly over each other. This mechanism limits the time jitter of MPEG video to 3 bus clock cycles, or about 120 ns.
As already described all bus nodes in an IEEE 1394 serial bus bridge to one common clock signal to be synchronized to IEEE 1394 bridge Isynchronous route supported by real-time data. This way is a method for distributing the clock signal required by this synchronization request to fulfill, while also the time jitter is minimized, stemming from the use of different wired or wireless switching networks (the implementation-specific are variable and therefore variable).
When using a wireless switching network to interconnect IEEE 1394 bus nodes, the following problems are encountered:
(1) It may not be possible to send the Cycle_Start packet every 125 μs since the total cost of the Cycle_Start packet may be significant for low data rate transfers;
(2) The wireless communication channel may not be available at the time when the cycle_start_packet is to be sent. The time in which the communication channel can not be accessed can be very long compared to a wired switching network;
(3) It is possible that the cycle monster portal is not the root node; and
(4) Not all current wireless transmission standards may work on a frame basis, although most standards have a concept of frame timing that is synchronized between the respective wireless nodes.
As will be clear below, triggers the clock signal distribution method according to the present invention, any of the above problems. First It is assumed that all wireless standards are compatible IEEE 1394 support a frame synchronization mechanism. In this regard, IEEE 802.11 uses periods apart Beacons as a frame synchronization mechanism. A similar process, the time markers was used for Wireless ATM (WATM), which in Europe is referred to as "HIPERLAN 2". Wireless cellular standards, such as GSM, DECT, Information Signal 95, Information signal-54 and information signal-136 also use frame-based Timing. Maybe the only important wireless standard, that does not use frame-based timing, HIPERLAN 1. But given the small population of facilities based on this standard, is it possible, that HIPERLAN 1 is never widely accepted. To this Way, the assumption is that only those wireless standards, which support a frame synchronization mechanism, are compatible with IEEE 1394 is for the purpose of the present invention not overly restrictive.
Based on 5 A method for distributing the clock signal to the cycle monster portal in an IEEE 1394 serial bus bridge using a wireless switching network according to a first preferred embodiment of the present invention will now be described. The "wireless part" 80 in 5 refers to a wireless switching subsystem coupled to the cycle monster portal of the IEEE 1394 wireless serial bus bridge. The "1394 part" refers to a communication interface part of the cyclic monster pore of the wireless IEEE 1394 serial bus bridge. In the in 5 It is assumed that the cycle monster portal is not a cyclic master. It should be noted that, according to the present invention, each of the bus nodes in the IEEE 1394 serial bus bridge (including the cycle monster portal and all "other" bus nodes) will be coupled to a respective wireless (or wired) switching subsystem, as will become apparent below. Furthermore, it will be appreciated that the many switching subsystems coupled to the respective bus nodes collectively form the switching system (ie, the switching network) of the IEEE 1394 serial bus bridge.
It should be clear that the wireless part 80 the already described Taktsignalsubsystem 40 out 3 virtually equivalent, except that the modulo 125 μs block 46 through a modulo W μs block 46 ' has been replaced, where "W" is the cycle time of the wireless part 80 is, or more generally, the frame time of the wireless communication standard passing through the wireless part 80 is applied. The 1394 part 82 is virtually identical to the subsystem handling the recipient node 4 , According to the present invention, the wireless part 80 and the 1394 part 82 with a common clock subsystem 83 effectively coupled, which is a clock counter 90 and a 24.576 MHz crystal 92 having.
This is the wireless part 80 and the 1394 part 82 both essentially slaves of the same clock signal. In this way, any additional time jitter within the wireless part 80 by simply reducing the drift between the clock signals of the wireless switching network, which is a function of the parameter "W".
It might Those skilled in the art will appreciate that this clock signal distribution technique also be used in a wired IEEE 1394 serial bus bridge can, i. in an IEEE 1394 serial bus bridge, in which a wired Switching network, which wired the wireless subsystems Subsystems become.
Based on 6 A method for distributing the clock signal in the cycle monster portal in an IEEE 1394 serial bus bridge using a wireless switching network according to a second preferred embodiment of the present invention will be described. The "wireless part" 100 in 5 again refers to a wireless switching subsystem coupled to the clock monster portal of the IEEE 1394 wireless serial bus bridge. The "1394 part" 102 refers to a communications interface portion of the clock monster portal of the IEEE 1394 wireless serial bus bridge. In the in 6 It is assumed that the clock monster portal is a clock master. It should be clear that the wireless part 100 the in 5 illustrated wireless part 80 corresponds and the 1394 part 102 is essentially the same as in 3 illustrated clock subsystem 40 , The wireless part 100 and the 1394 part 102 Both are with a common clock subsystem 103 effectively connected to a crystal 110 and a clock counter 112 having.
Based on 7 For example, a method for distributing the clock signal over other bus nodes (ie, unlike the clock monster portal) in an IEEE 1394 serial bus bridge according to a preferred embodiment of the present invention will be described. The 1394 part 120 refers to the communication interface part of the respective "other" bus node in the IEEE 1394 serial bus bridge, and the wireless part 122 refers to the wireless subsystem that is effectively coupled to it. In general, the in 7 configuration shown the same as the out 5 except that the 1394 and the wireless parts 120 . 122 are opposite to correct 1394 / wireless physical layers. In this case, the wireless part updates 122 the clock counter 121 of the respective clock signal subsystem 123 when it receives a new cycle_start packet. As already described above, it is possible for the cycle_startup packet to be from the wireless part 122 received at a different rate than the 1394 part 120 , Since all the bus nodes in the IEEE 1394 serial bus bridge are clock masters (with the possible exception of the clock monster portal), the wired 1394 generates part 120 every "other" bus node always cycles_Startpaket in the appropriate 125 μs cycle. It will be appreciated that it is not essential to the present invention that each of the bus nodes be the clock master of the particular local serial bus.
It is also possible that the wireless / link standards do not support the complete clock count accuracy based on a 24.576 MHz clock signal. For example, IEEE 802.11 supports a clock accuracy of only 1 μs, ie it is not possible to send a bus_time that contains a sufficient number of bits to represent the 24,576 MHz clock signal with complete accuracy. According to another aspect of the present invention, however, it is possible to ensure the complete accuracy of the cycle counter of each respective clock subsystem, even if the wireless / link standards do not support the full accuracy of the clock counter based on the 24.576 MHz clock signal. More specifically, according to this aspect of the present invention, the clock counter continues its own update based on the 34.576 MHz clock signal, and the clock counter At least significant bits of this clock signal that can not be transmitted over the wireless channel are compared to a preset value, for example, all zero. The bus_time is sent over the wireless channel only when the least significant bits of the clock counter output signal are equal to the preset value. At the receiver, the preset value is loaded into the clock counter along with the given bus_time, ensuring the complete accuracy of the cycle counter.
8th Fig. 12 is a block diagram of a subsystem (an IEEE 1394 serial bus bridge) for generating a wireless cycle_start packet at a clock monster portal when the complete accuracy of the clock counter is not transmitted from the wireless part according to the aspect of the present invention described above; and 9 Figure 12 is a block diagram of one subsystem (an IEEE 1394 serial bus bridge) for receiving a wireless cycle_start packet in another bus node (the IEEE 1394 serial bus bridge) if complete accuracy of the clock counter is not communicated to the wireless part according to the aspect of the present invention described above.
The wireless part 140 of in 8th represented subsystem corresponds to the wireless part 100 out 6 , except that the wireless part 140 an additional processing block 142 to determine when the less significant bits of the clock counter output signal correspond to the preset value, and to generate a trigger signal to trigger the transmission of the cycle_start packet by the state machine when equality is detected. In the same way is the wireless part 150 of in 9 represented subsystem identical to the wireless part 122 out 7 , except that the wireless part 122 an additional processing block 152 for loading the preset value into the clock counter, along with the bus_time extracted from the received cycle_start packet. The 1394 part 141 of in 8th shown subsystem can those of the 5 or 6 depending on whether the clock monster portal is a clock master or not. The 1394 part 151 of in 9 shown subsystem can from the 7 correspond.
It will be apparent to those skilled in the art, based on the above and the foregoing, that the clock distribution methodology of the present invention is not limited to wireless IEEE 1394 serial bus bridges, but is generally applicable to all possible switch network implementations, the only limitation being that Switching network frame-based synchronization supported. Furthermore, it will be appreciated that the above-described clock signal distribution methodology of the present invention provides the numbered advantages over currently available technology:
(2) it can support wired or wireless switching networks;
(4) the implementation is simple and general; and
(5) it substantially minimizes time jitter.
Although the present invention has been described in detail hereinabove is, probably Make it easy for many modifications and / or modifications of the inventive basic concept are possible, those skilled in the art could come but which are within the scope of the present invention, such as in the appended claims Are defined.
Bus bridge ( 20 ) for connecting a number of buses ( 30 ), this bridge comprising: a number of bus nodes ( 22 ), each bus node ( 22 ) with a bus of the buses ( 30 ), - a number of switching subsystems ( 80 . 100 . 122 . 140 or 150 ) each of the switching subsystems being connected to a respective bus node ( 22 ), the number of switching subsystems collectively being a switching system ( 24 ) comprising the number of bus nodes ( 22 ) connects together; - wherein one of the buses comprises a cycle monster, which is a node from which the clock signal is distributed across all buses; wherein the bus node is coupled to the bus, the cycle monster being referred to as the cycle monster portal; A number of clock subsystems ( 83 . 103 or 123 ), each clock signal subsystem operating effectively with a respective bus node ( 22 ) and wherein the respective switching subsystem is coupled thereto, each clock subsystem comprising: - a clock signal generator ( 92 or 110 ) which generates a clock signal for the subsystem; and a clock counter ( 90 . 112 or 121 ) coupled to the clock signal generator and cyclically providing a clock counter output signal forming a time reference for the respective switching subsystem and bus node; - wherein the switching subsystem coupled to the clock monster portal is adapted to cyclically supply an output of the clock counter as a common time reference to each other switching subsystem; and each one switching subsystem, which is not coupled to the clock monster portal, is intended to load the common time reference value into the clock counter.
A bus bridge according to claim 1, wherein each of said switching subsystems ( 80 . 100 . 122 . 140 or 150 ) is a wireless switching subsystem and the switching system ( 24 ) is a wireless switching system.
A bus bridge according to claim 1, wherein each of said switching subsystems ( 80 . 100 . 122 . 140 or 150 ) is a wired subsystem and the switching system ( 24 ) is a wired switching system.
Bus bridge according to claim 1, wherein - the bus bridge ( 20 ) is a serial bus bridge, - each of the buses ( 30 ) is a serial local bus, and - each bus node ( 22 ) a node on the relevant serial local bus ( 30 ).
Bus bridge according to claim 1, wherein - the bus bridge ( 20 ) is an IEEE 1394 serial bus bridge, - each of the buses ( 30 ) an IEEE 1394 serial local bus, and - each bus node ( 22 ) is an IEEE 1394 serial bus node.
A bus bridge according to claim 1, wherein the clock monster portal ( 82 . 102 . 141 ) is a clock master.
A bus bridge according to claim 1, wherein the clock monster portal ( 82 . 102 . 141 ) is not a clock master.
A bus bridge according to claim 1, wherein the switching system ( 24 ) uses a frame synchronization protocol.
A bus bridge according to claim 8, wherein the switching subsystem ( 80 ) with the cyclic monster portal ( 82 ), comprising: - a modulo W μs counter ( 46 ' ) representing the clock counter output of the respective clock signal subsystem ( 83 ) and which generates a time signal in response to each W μs, where W is a frame time specified by the frame synchronization protocol; A state machine ( 48 ) which generates an enable signal in response to the timing signal; and - a register ( 52 ) having a first input which is the clock counter output of the respective clock signal subsystem ( 83 ) and a second input which receives the enable signal, whereby the register ( 52 ) provides a bus_time data block in response to the enable signal, wherein the bus_time data block is indicative of a current bus time.
A bus bridge according to claim 9, wherein the clock monster portal ( 82 ) Comprises: a physical layer ( 60 ) containing the clock_start packet from the relevant switching subsystem ( 80 ) receives; A decoding part ( 62 ) containing the clock_start packet from the relevant switching subsystem ( 80 ) receives; A decoding part ( 62 ) which decodes the packet header of the Clock_Start packet and which provides a decode signal indicative of receipt of the Clock_Start packet; A processing delay part ( 66 ), which determines a processing time required to decode the clock_start_packet, and which provides a processing delay time output indicative of the particular processing time, a delay element (FIG. 70 ) which delays the decode signal by the processing delay time and which provides a load signal; - a register ( 64 ) receiving the bus time data block and providing a register output indicative of the current bus_time; An adder ( 68 ), which adds together the processing delay time output signal and the register output signal, and which provides the sum, and - wherein the clock counter ( 90 ) of the respective clock signal subsystem ( 83 ) receives the load signal and the sum in response to the load signal in the clock counter ( 90 ) of the respective clock signal subsystem ( 83 ) is loaded.
Bus bridge na9, where the clock monster portal ( 102 ) Comprises: - a modulo N μs counter ( 46 ) representing the clock counter output of the respective clock signal subsystem ( 103 ) and which generates a second time signal in response to each N μs, where N is a value specified by a prescribed bus protocol; A second state machine ( 48 ' ) which generates a second enable signal in response to the second time signal; and - a second register ( 52 ' ) having a first input which is the clock counter output of the respective clock signal subsystem ( 103 ) and a second input receiving the second enable signal, whereby the second register ( 52 ' ) provides a second bus_time data block in response to the second enable signal, the second bus_time data block being indicative of a current bus time.
A bus bridge according to claim 9, wherein each bus node ( 120 or 151 ) unlike the clock monster portal ( 82 or 102 ) Includes: - a modulo N μs counter ( 46 '' ) representing the clock counter output of the respective clock signal subsystem ( 123 ) and which generates a time signal every N μs in response thereto, where N is a value specified by a prescribed bus protocol; A state machine ( 48 '' ) which generates a channel request signal in response to the time signal: - a physical layer ( 50 '' ) which receives the channel request signal and in response generates a channel available signal upon detection that a wireless communication channel available from the wireless switching system (FIG. 24 ), the state machine ( 48 '' ) receives the channel available signal and generates a packet header and an enable signal in response to the channel available signal; - a register ( 52 '' ) having a first input which is the clock counter output of the respective clock signal subsystem ( 123 ) and a second input receiving the enable signal, whereby the register ( 52 '' ) provides a bus_time data block in response to the enable signal. Where the bus_time_data_block is indicative of the current bus time; and - wherein the packet header and the bus_time data block together comprise a clock_start packet received from the respective wireless switching subsystem ( 122 ) is transmitted.
A bus bridge according to claim 9, wherein each of the wireless switching subsystems ( 122 or 150 ) connected to the bus nodes ( 120 or 151 ) unlike the clock monster portals ( 82 . 102 or 141 ), comprising: a wireless physical layer ( 60 '' ), which is a clock_start packet from the relevant bus node ( 120 or 150 ) receives; A decoding part ( 62 '' ) which decodes the packet header of the Clock_Start packet and which provides a decode signal indicative of receipt of the Clock_Start packet; A processing delay element ( 66 '' ), which determines a processing time required to decode the clock_start_packet, and which provides a processing delay time output indicative of the determined processing time, a delay element (FIG. 70 '' ) which delays the decode signal by the processing delay time and which provides a load signal; - a register ( 64 '' ) receiving the bus_time data block and generating a register output indicative of the current bus time; An adder ( 68 '' ) which sums the processing delay time output signal and the register output signal and which provides the sum; and - wherein the clock counter of the respective clock signal subsystem ( 123 ) receives the load signal and the sum in response to the load signal in the clock counter ( 121 ) of the respective clock signal subsystem ( 123 ) is loaded.
Bus bridge to spoke 8th where the switching subsystem ( 100 ), which with the Taktmonsterportal ( 102 ), comprising: - a modulo W μs counter ( 46 ' ) representing the clock counter output of the respective clock signal subsystem ( 103 ) and which generates a first time signal every W μs, where W is an image time specified by the image synchronization protocol; A state machine ( 48 ) which generates a channel request signal in response to the time signal; A physical layer ( 50 ) which receives the first channel request signal and in response generates a first channel available signal upon detection that a communication channel received from the switching system (Fig. 24 ) is available, the state machine ( 48 ) receives the channel available signal and generates a packet header and an enable signal in response to the channel available signal; - a register ( 52 ) having a first input which is the clock counter output of the respective clock signal subsystem ( 103 ) and a second input receiving the first enable signal, the register ( 52 ) provides a first bus_time data block in response to the first enable signal, the first bus_time data block being indicative of the current bus time; and - wherein the packet header and the bus_time data block together comprise a clock_start packet that is generated by the switching subsystem ( 100 ) is transmitted.
A bus bridge according to claim 8, wherein the wireless switching system ( 140 ), which with the Taktmonsterportal ( 141 ), comprising: - a modulo W μs counter ( 46 ' ) representing the clock counter output of the respective clock signal subsystem ( 83 ) and which generates a time signal every W μs, where W is an image time specified by the image synchronization protocol; A state machine ( 48 ) which generates a channel request signal in response to the time signal; A comparison circuit ( 142 ), the prescribed less significant bits of the clock counter output signal of the respective clock signal subsystem ( 83 ) compares with a preset value and provides a trigger signal upon detection of equality; A wireless physical layer ( 50 ) which receives the channel request signal and in response generates a channel available signal upon detection that a wireless communication channel received from the wireless switching system (Fig. 24 ) is used, is available - wherein the state machine ( 48 ) receives the channel available signal and generates a packet header and an enable signal in response to the receipt of the channel available signal and the trigger signal; - a register ( 52 ) having a first input which is the clock counter output of the respective clock signal subsystem ( 83 ) and a second input receiving the enable signal, - the register ( 52 ) provides a bus_time data block in response to the enable signal, wherein the bus_time data block is indicative of a current bus time; and wherein the packet header and the bus_time_data_block together comprise a clock_start packet issued by the respective wireless switching subsystem ( 140 ) is transmitted.
Method for distributing a clock signal in a bus bridge ( 20 ) containing a number of bus nodes ( 22 ), each with a bus of the buses ( 30 ) is coupled; a number of switching subsystems ( 80 . 100 . 122 . 140 or 150 ), each with a respective bus node ( 22 ), the number of switching subsystems ( 80 . 100 . 122 . 140 or 150 ) collectively a switching system ( 24 ), which determines the number of bus nodes ( 22 ) connects together; wherein one of the buses comprises a clock monster, which is a node from which the clock signal is propagated across all buses; wherein the bus node is coupled to the bus, the clock monster being referred to as the clock monster portal; the method comprising the following method steps: - at each bus node ( 22 ) generating a clock signal; - at each bus node ( 22 ), using a clock counter ( 90 . 112 . 121 ) coupled to the clock signal generator for cyclically generating a clock counter output signal, and using the clock counter output signal to generate a time reference value for the bus node (Fig. 20 ) and the relevant switching subsystem coupled thereto; In the switching subsystem coupled to the clock monster portal, cyclically transmitting an output of the clock counter as a common time reference to each other switching subsystem; and - for each switching subsystem that is not coupled to the clock monster portal, loading the common time reference value into the clock counter.
DE1998635807 1997-12-30 1998-10-08 Method and apparatus for clocking signal distribution to several bus nodes in a bus bridge Expired - Fee Related DE69835807T2 (en)
US672 1997-12-30
DE69835807D1 DE69835807D1 (en) 2006-10-19
DE69835807T2 true DE69835807T2 (en) 2007-04-12
DE1998635807 Expired - Fee Related DE69835807T2 (en) 1997-12-30 1998-10-08 Method and apparatus for clocking signal distribution to several bus nodes in a bus bridge
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1998-10-08 EP EP19980945471 patent/EP0961977B1/en not_active Expired - Lifetime