Source: http://www.google.com/patents/US7834398?dq=6,208,537
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Matched Legal Cases: ['Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 2007', 'Application No. 2009', 'Application No. 2009', 'Application No. 11', 'Application No. 2007']

Patent US7834398 - Method of manufacturing a semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThere is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal...http://www.google.com/patents/US7834398?utm_source=gb-gplus-sharePatent US7834398 - Method of manufacturing a semiconductor deviceAdvanced Patent SearchPublication numberUS7834398 B2Publication typeGrantApplication numberUS 11/978,586Publication dateNov 16, 2010Filing dateOct 30, 2007Priority dateJun 22, 1998Also published asUS6380046, US7199024, US7790570, US7816736, US8053837, US8187926, US8241997, US8288248, US8314010, US8575741, US20020109144, US20040147095, US20070173000, US20080061301, US20080067529, US20080067597, US20080083953, US20080213953, US20080286941, US20080286942, US20080286956, US20130143387Publication number11978586, 978586, US 7834398 B2, US 7834398B2, US-B2-7834398, US7834398 B2, US7834398B2InventorsShunpei YamazakiOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (101), Non-Patent Citations (52), Referenced by (8), Classifications (32) External Links: USPTO, USPTO Assignment, EspacenetMethod of manufacturing a semiconductor deviceUS 7834398 B2Abstract There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.
1. A microprocessor comprising an integrated circuit including an N-channel transistor and a P-channel transistor, at least one of the N-channel transistor and the P-channel transistor comprising:
an island-like single crystalline semiconductor layer over a silicon substrate with a bonded interface interposed between the island-like single crystalline semiconductor layer and the silicon substrate, the island-like single crystalline semiconductor layer comprising part of a single crystalline silicon substrate different from the silicon substrate and having at least a channel formation region and source and drain regions;
an insulating film formed on the island-like single crystalline semiconductor layer;
a gate electrode comprising poly silicon formed over the channel formation region with the insulating film interposed therebetween;
side walls formed adjacent to side surfaces of the gate electrode; and
an interlayer insulating film comprising silicon nitride formed over at least one of the N-channel transistor and the P-channel transistor,
wherein a top face of the island-like single crystalline semiconductor layer under the gate electrode is thermally oxidized to form the insulating film,
wherein a bottom face of the island-like single crystalline semiconductor layer is thermally oxidized to form a silicon oxide layer in contact with the bottom face,
wherein each of the source and drain regions includes at least a portion that extends through an entire thickness of the island-like single crystalline semiconductor layer such that the source and drain regions contact the silicon oxide layer, and
wherein an upper portion of the gate electrode and upper portions of the source and drain regions comprise a metal silicide.
2. The microprocessor according to claim 1 wherein the microprocessor is a RISC processor.
3. The microprocessor according to claim 1 wherein the microprocessor is an ASIC processor.
4. The microprocessor according to claim 1 further comprising a CPU core, a RAM, a clock controller, a cache memory, a cache controller, a serial interface and an I/O port.
5. The microprocessor according to claim 1 wherein the metal silicide is cobalt silicide.
6. The microprocessor according to claim 1 wherein the island-like single crystalline semiconductor layer is hydrogenated.
7. The microprocessor according to claim 1 wherein the source and drain regions are in contact with the silicon oxide layer.
8. The microprocessor according to claim 1 wherein the silicon oxide layer is 0.05 to 0.5 μm thick.
9. The microprocessor according to claim 1 wherein the side walls contact side surfaces of the gate electrode and the insulating film.
10. The microprocessor according to claim 1 wherein the silicon oxide layer contains a halogen.
11. The microprocessor according to claim 10 wherein the halogen is chlorine or fluorine.
12. The microprocessor device according to claim 1 wherein the maximum of the thickness of the island-like single crystalline semiconductor layer is 50 nm or lower.
13. A microprocessor comprising an integrated circuit including an N-channel transistor, the N-channel transistor comprising:
an island-like single crystalline semiconductor layer over a silicon substrate with a bonded interface interposed therebetween, the island-like single crystalline semiconductor layer comprising part of a single crystalline silicon substrate different from the silicon substrate and having at least a channel formation region, source and drain regions, and LDD regions;
side walls formed adjacent to side surfaces of the gate electrode wherein the LDD regions are located below the side walls with the insulating film interposed therebetween; and
an interlayer insulating film comprising silicon nitride formed over the N-channel transistor,
14. The microprocessor according to claim 13 wherein the microprocessor is a RISC processor.
15. The microprocessor according to claim 13 wherein the microprocessor is an ASIC processor.
16. The microprocessor according to claim 13 further comprising a CPU core, a RAM, a clock controller, a cache memory, a cache controller, a serial interface and an I/O port.
17. The microprocessor according to claim 13 wherein the metal silicide is cobalt silicide.
18. The microprocessor according to claim 13 wherein the island-like single crystalline semiconductor layer is hydrogenated.
19. The microprocessor according to claim 13 wherein the source and drain regions are in contact with the silicon oxide layer.
20. The microprocessor according to claim 13 wherein the silicon oxide layer is 0.05 to 0.5 μm thick.
21. The microprocessor according to claim 13 wherein the side walls contact side surfaces of the gate electrode and the insulating film.
22. The microprocessor according to claim 13 wherein the LDD regions are in contact with the silicon oxide layer.
23. The microprocessor according to claim 13 wherein the silicon oxide layer contains a halogen.
24. The microprocessor according to claim 23 wherein the halogen is chlorine or fluorine.
25. The microprocessor device according to claim 13 wherein the maximum of the thickness of the island-like single crystalline semiconductor layer is 50 nm or lower.
26. A microprocessor comprising an integrated circuit including an N-channel transistor and a P-channel transistor, at least one of the N-channel transistor and the P-channel transistor comprising:
an island-like single crystalline semiconductor layer formed on a silicon oxide layer on a silicon substrate with a bonded interface interposed therebetween, the island-like single crystalline semiconductor layer comprising part of a single crystalline silicon substrate different from the silicon substrate and having at least a channel formation region and source and drain regions;
a gate electrode formed over the channel formation region with the insulating film interposed therebetween;
side walls formed adjacent to side surfaces of the gate electrode wherein the side walls are in contact with an upper surface of the insulating film; and
wherein upper portions of the source and drain regions comprise a metal silicide.
27. The microprocessor according to claim 26 wherein the insulating film is formed by thermally oxidizing an upper surface and side surfaces of the island-like single crystalline semiconductor layer in an oxidizing atmosphere containing a halogen element.
28. The microprocessor according to claim 26 wherein the silicon oxide layer contains a halogen.
29. The microprocessor according to claim 28 wherein the halogen is chlorine or fluorine.
30. The microprocessor device according to claim 26 wherein the maximum of the thickness of the island-like single crystalline semiconductor layer is 50 nm or lower.
31. A semiconductor device comprising an integrated circuit including an N-channel transistor, the N-channel transistor comprising:
an island-like single crystalline semiconductor layer formed on a silicon oxide layer on a silicon substrate with a bonded interface interposed therebetween, the island-like single crystalline semiconductor layer comprising part of a single crystalline silicon substrate different from the silicon substrate and having at least a channel formation region and source and drain regions and LDD regions;
side walls formed adjacent to side surfaces of the gate electrode wherein the side walls are in contact with an upper surface of the insulating film and the LDD regions are located below the side walls with the insulating film interposed therebetween; and
wherein upper portions of the source and drain regions comprise a cobalt silicide.
32. The semiconductor device according to claim 31 wherein the silicon oxide layer contains a halogen.
33. The semiconductor device according to claim 32 wherein the halogen is chlorine or fluorine.
34. The semiconductor device according to claim 31 wherein the maximum of the thickness of the island-like single crystalline semiconductor layer is 50 nm or lower.
35. A semiconductor device comprising an integrated circuit including an N-channel transistor and a P-channel transistor, at least of the N-channel transistor and the P-channel transistor comprising:
wherein upper portions of the source and drain regions comprise a cobalt silicide, and the source and drain regions contact the silicon oxide layer.
36. The semiconductor device according to claim 35 wherein the silicon oxide layer contains a halogen.
37. The semiconductor device according to claim 36 wherein the halogen is chlorine or fluorine.
38. The semiconductor device according to claim 35 wherein the maximum of the thickness of the island-like single crystalline semiconductor layer is 50 nm or lower.
an island-like single crystalline semiconductor layer formed over a silicon substrate with a silicon oxide layer interposed therebetween, the island-like single crystalline semiconductor layer comprising part of a single crystalline silicon substrate different from the silicon substrate and having at least a channel formation region and source and drain regions;
a gate insulating film formed on the channel formation region;
a gate electrode comprising polysilicon formed over the channel formation region with the gate insulating film interposed therebetween; and
an interlayer insulating film comprising silicon nitride formed over the transistor,
wherein a top face of the island-like single crystalline semiconductor layer under the gate electrode is thermally oxidized to form the gate insulating film,
wherein each of the source and drain regions includes at least a portion that extends through an entire thickness of the island-like single crystalline semiconductor layer such that the source and drain regions contact the silicon oxide layer,
wherein an upper portion of the gate electrode and upper portions of the source and drain regions comprise a metal silicide, and
wherein the silicon oxide layer contains a halogen.
40. The semiconductor device according to claim 39 wherein the island-like single crystalline semiconductor layer is hydrogenated.
41. The semiconductor device according to claim 39 wherein the silicon oxide layer is 0.05 to 0.5 μm thick.
42. The semiconductor device according to claim 39 wherein the semiconductor device is a microprocessor.
43. The semiconductor device according to claim 39 wherein the semiconductor device is an information terminal.
44. The semiconductor device according to claim 39 wherein the halogen is chlorine or fluorine.
45. The semiconductor device according to claim 39 wherein the maximum of the thickness of the island-like single crystalline semiconductor layer is 50 nm or lower.
wherein an upper portion of the gate electrode and upper portions of the source and drain regions comprise cobalt silicide, and
47. The semiconductor device according to claim 46 wherein the island-like single crystalline semiconductor layer is hydrogenated.
48. The semiconductor device according to claim 46 wherein the silicon oxide layer is 0.05 to 0.5 μm thick.
49. The semiconductor device according to claim 46 wherein the semiconductor device is a microprocessor.
50. The semiconductor device according to claim 46 wherein the semiconductor device is an information terminal.
51. The semiconductor device according to claim 46 wherein the halogen is chlorine or fluorine.
52. The semiconductor device according to claim 46 wherein the maximum of the thickness of the island-like single crystalline semiconductor layer is 50 nm or lower.
a gate electrode formed over the channel formation region with the gate insulating film interposed therebetween; and
wherein upper portions of the source and drain regions comprise a metal silicide, and
54. The semiconductor device according to claim 53 wherein the island-like single crystalline semiconductor layer is hydrogenated.
55. The semiconductor device according to claim 53 wherein the silicon oxide layer is 0.05 to 0.5 μm thick.
56. The semiconductor device according to claim 53 wherein the semiconductor device is a microprocessor.
57. The semiconductor device according to claim 53 wherein the semiconductor device is an information terminal.
58. The semiconductor device according to claim 53 wherein the metal silicide is cobalt silicide.
59. The semiconductor device according to claim 53 wherein the halogen is chlorine or fluorine.
60. The semiconductor device according to claim 53 wherein the maximum of the thickness of the island-like single crystalline semiconductor layer is 50 nm or lower. Description
As another method, there is known a technique called ELTRAN (trademark of Canon K.K.). This technique is a method of manufacturing an SOI substrate using selective etching of a porous silicon layer. The particular technique of ELTRAN method is disclosed in �T. Yonehara, K. Sakaguchi and T. Hamaguchi: Appl. Phys. Lett. 43[3], 253 (1983)� in detail.
SUMMARY OF THE INVENTION The present invention has been made to solve the foregoing problem, and an object of the present invention is to provide a method of removing trap levels and defects due to stress, from a single crystal silicon thin film formed by Smart-Cut method or ELTRAN method.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are views showing forming steps of an island-like silicon layer of Embodiment 1;
FIGS. 10A to 10C are views showing structures of electronic apparatuses of Embodiment 10.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Detailed descriptions of preferred embodiments of the present invention will be made in conjunction with embodiments described below.
Embodiment 1 A structure of the present invention will be described with reference to FIGS. 1A to 1C and FIGS. 2A to 2D. First, a single crystal silicon substrate 101 is prepared. Next, a thermal oxidation treatment is carried out to form a silicon oxide film 102 on a major surface (component formation surface) of the substrate. Although the film thickness may be suitably determined by an operator, it is appropriate that the thickness is made 0.05 to 0.5 μm. This silicon oxide film 102 subsequently functions as a buried oxide film of an SOI substrate (FIG. 1A).
Embodiment 2 This embodiment is an example in which the sequence of the manufacturing steps of embodiment 1 is changed. Until the middle of the steps, steps are the same as in embodiment 1, so that their explanation will be omitted.
Embodiment 3 Embodiments 1 and 2 show examples in which trap levels and defects are reduced from the single crystal silicon thin films formed by Smart-Cut method. However, the present invention is also effective for a single crystal silicon thin film formed by other bonding SOI techniques.
Embodiment 4 This embodiment is an example in which the sequence of the manufacturing steps of embodiment 3 is changed. Until the middle of steps, steps are the same as in embodiment 3, their description will be omitted.
Embodiment 5 In this embodiment, a case where a TFT is manufactured by using an island-like silicon layer formed with the structure of embodiments 1 to 4 will be described with reference to FIGS. 5A to 5D.
When the state of FIG. 5B is obtained in this way, a side wall (side spacer) SOS made of a silicon oxide film is next formed. The side wall SOS can be formed by using a well-known anisotropic etching technique.
After the side wall SOS is formed, an adding step of phosphorus is again carried out, so that an impurity region with a concentration higher than the foregoing impurity region 504 is formed. Through the two impurity adding steps, a source region 506, a drain region 507, an LDD region 508, and a channel formation region 509 are defined (FIG. 5C).
Embodiment 6 FIG. 6 of this embodiment shows an example of a liquid crystal display device in which a semiconductor circuit is constructed by TFTs formed in accordance with the manufacturing steps of embodiment 5. Since well-known means can be used for a manufacturing method of a pixel TFT (pixel switching element) and/or a peripheral driver circuit and for a cell assembling step, the detailed description will be omitted.
Embodiment 7 The present invention can be applied to any conventional IC technique. That is, the present invention can be applied to any semiconductor circuit currently available on the market. For example, the present invention may be applied to a microprocessor such as a RISC processor or ASIC processor integrated on one chip, or may be applied to any circuit from a signal processing circuit such as a D/A convertor to a high frequency circuit for a portable equipment (cellular phone, PHS, mobile computer).
Embodiment 8 CMOS circuits and pixel active matrix circuits produced by the embodiments of the present invention can be applied to a plurality of electro-optical devices (e.g. an active matrix type liquid crystal display, an active matrix type EL display, and an active matrix type EC display). That is, the present invention can be carried out for all the electric apparatus including such the electro-optical devices as display media.
A structure of the light source optical system and display device, as shown in FIG. 10C is called as a color-filterless single-plate type. In this structure, a display device 2916 is equipped with a microlens array 2915, and a display image is colored by a dichroic mirror (Green) 2912, a dichroic mirror (Red) 2913 and a dichroic mirror (Blue). A projection optical system 2917 is constituted by a plurality of lenses including a projection lens. It is possible to apply the light source optical system and display device shown in FIG. 10C to the light source optical system and display device 2601 shown in FIG. 9A, or 2702 in FIG. 9B. Further, as the light source optical system 2911, an optical system having a coupling lens and a collimating lens other than a light source can be applied.
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