Source: http://www.google.fr/patents/US4447871
Timestamp: 2013-12-19 02:57:00
Document Index: 59365702

Matched Legal Cases: ['art 4', 'art 4', 'art 4', 'art 4', 'art 4', 'art 4']

Brevet US4447871 - Data communication system with a front-end-processor - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus »Connexion Recherche avanc�e dans les brevets BrevetsA data communication system which includes a data distributor, a communication station and a plurality of front-end-processors. These front-end-processors are connected with a computer through a common bus. The distributor distributes the data received by the station to one available front-end-processor,...http://www.google.fr/patents/US4447871?utm_source=gb-gplus-shareBrevet US4447871 - Data communication system with a front-end-processor Recherche avanc�e dans les brevets Num�ro de publicationUS4447871 AType de publicationOctroi Num�ro de demandeUS 06/230,805 Date de publication8 mai 1984 Date de d�p�t2 f�vr. 1981 Date de priorit�4 f�vr. 1980�tat de paiement des fraisCaducAutre r�f�rence de publicationDE3103786A1, DE3103786C2 Num�ro de publication06230805, 230805, US 4447871 A, US 4447871A, US-A-4447871, US4447871 A, US4447871A InventeursMatsuaki Terada, Koji Yokota Cessionnaire d'origineHitachi, Ltd.Exporter la citationBiBTeX, EndNote, RefManCitations de brevets (9), R�f�renc� par (22), Classifications (8), �v�nements juridiques (6) Liens externes: USPTO, Cession USPTO, EspacenetData communication system with a front-end-processorUS 4447871 A R�sum� A data communication system which includes a data distributor, a communication station and a plurality of front-end-processors. These front-end-processors are connected with a computer through a common bus. The distributor distributes the data received by the station to one available front-end-processor, which preprocesses the received data, and transfers the pre-processed data to the computer through the bus. By operating the front-end-processors in parallel with respect to successively received packets of data, the processing speed of the system is increased.
The program 7 generally requires 2000 to 8000 steps in order to perform the function described above. When the speed of the communication line 2 is improved so that the number of the packets 5 flowing through that line 2 is increased, difficulty in the program processing at the computer 1 takes place. If the time period for the program 7 to process one packet is assumed to be 4 ms (i.e., 2000 steps packet processing capability of the computer 1 has its upper limit at 250 packets/s. Thus, for this reason, the data communication system according to the prior art has a drawback in that the processing overhead is very time consuming, so that even if the speed of the communication line 2 is high, the computer 1 cannot receive the data at the sending speed of that communication line.
&lt;Bus Control Circuit and Station&gt; Receiving Operation The interruption signal provided by the station 4, as explained before, when it receives a packet from the communication line 2 is generated by a receive part 4-1 of the station 4 and comprises a device interruption signal and a receive-part identifying signal. These signals are sent to an AND gate 11-3-2 of the bus control circuit 11-3 respectively by way of lines 11-4-3-3 and 11-4-3-4 included in the control line 11-4-3. The interruption signal which the bus control circuit 11-3 provides on the line 11-15, as explained before, in response to the interruption signal from the station 4 at receiving a packet is generated by the AND gate 11-3-2 in response to the two signals. As explained before, the control 11-2-3 sends the reception command R onto the line 11-7 in response to the interruption signal on the line 11-15. The former and the latter are generated by merely transferring the reception command R to lines 11-4-3-1 and 11-4-3-2, respectively, within the bus control circuit 11-3. The line 11-4-3-1 is connected to both the receive part 4-1 and a send part 4-2 of the station 4. The line 11-4-3-2 is connected only to the receive part 4-1. In response to the both signals, the receive part 4-1 starts the transferring operation of the received packet by the DMA method as explained before, from the buffer therein (not shown) to the selected processor 10 by way of the buses 11-4-1, 11-4-2 and the bus 11-11. The bus 11-4-1 and 11-4-2 pass through the bus control circuit 11-3 and are connected to the bus 11-11. The reception terminating interruption which the station 4 generates, as explained before, after the transferring is over comprises an interruption signal and a device select signal respectively sent to the lines 11-4-3-3 and 11-4-3-4 by the receive part 4-1 of the station 4. The reception terminating interruption signal which the bus control circuit 11-3 generates on the line 11-15, as explained before, in response to the reception terminating interruption from the station 4 is generated again by the AND gate 11-3-2 in response to the both signals on the lines 11-4-3-3 and 11-4-3-4.
&lt;Control&gt; Receiving Operation The selection instructing signal explained before which the control 11-2-3 sends to the receive selector 11-2-4 by way of the line 11-18 in response to the interruption signal given by the bus control circuit 11-3 by way of the line 11-15 when receiving operation is to be begun is generated by an R-S flip-flop 11-2-3-5. The flip-flop 11-2-3-5 is in a reset state except during receiving operation, as will be explained later on. The inverted output of the flip-flop 11-2-3-5 enables an AND gate 11-2-3-4. Therefore, the interruption signal given on the line 11-15 is passed through the AND gate 11-2-3-4 and sets the flip-flop 11-2-3-5. The normal output of the flip-flop 11-2-3-5 is sent to the receive selector 11-2-4 by the line 11-18 as the selection instructing signal. The first delay (D1) interposed between the normal output terminal of the flip-flop 11-2-3-5 and an AND gate 11-2-3-7 has a delay time somewhat longer than the duration period of the interruption signal given on the line 11-15. Therefore, the interruption signal on the line 11-15 does not pass through the AND gate 11-2-3-7 because the gate is disabled at least during the duration period of the interruption signal. Therefore, the flip-flop 11-2-3-5 whose reset input is connected to the AND gate 11-2-3-7 keeps being in a set state and the first gate circuit 11-2-3-7 does not provide any output.
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