Source: https://patents.google.com/patent/JPH10262029A/en
Timestamp: 2020-07-10 01:12:01
Document Index: 537786301

Matched Legal Cases: ['art 2', 'Application No. 7', 'Application No. 8', 'Application No. 8', 'art, 23', 'art, 25', 'art, 25', 'art, 25']

JPH10262029A - Spectrum direct spread communication system coping with delay multiplex system and communication method using the system - Google Patents
Spectrum direct spread communication system coping with delay multiplex system and communication method using the system
JPH10262029A
JPH10262029A JP9065026A JP6502697A JPH10262029A JP H10262029 A JPH10262029 A JP H10262029A JP 9065026 A JP9065026 A JP 9065026A JP 6502697 A JP6502697 A JP 6502697A JP H10262029 A JPH10262029 A JP H10262029A
JP9065026A
1997-03-18 Application filed by Sharp Corp, シャープ株式会社 filed Critical Sharp Corp
1997-03-18 Priority to JP9065026A priority Critical patent/JPH10262029A/en
1998-09-29 Publication of JPH10262029A publication Critical patent/JPH10262029A/en
238000001228 spectrum Methods 0.000 title claims abstract description 32
PROBLEM TO BE SOLVED: To provide a system, capable of completely improving correlation and improving an error rate, regardless of a data length in a spectrum direct spread communication system by a delay multiplex system. SOLUTION: A data generation part 2 is provided with a means for adding an additional bit, so as to be the integral multiple of a multiplex number at the time of generating information for transmitting data received from a higher- order layer 1 called an MAC layer. Since the means recognizes the symbol length of a data part by the information obtained from the higher-order layer 1 and also recognizes the symbol length of a bit synchronization part, a frame synchronization part and the respective kinds of information parts to be originally added as a packet, the number of the additional bits so as to turn the entire symbol numbers to the integral multiple of the multiplex number is added in front of the frame synchronization part. A bit addition part may be inserted before the data are started or added to the last of the data, that is an omitted part.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to spread spectrum communication, and more particularly, to a communication system compatible with a delay multiplex system and a communication method using the communication system.
2. Description of the Related Art In recent years, a spread spectrum communication system has attracted attention as a new communication system. The modulation method used for general data communication is a narrow-band modulation method, which can be realized by a relatively small circuit. However, such as a room (office, factory, etc.), it is possible to reduce multipath and narrow-band colored noise. Has the disadvantage of being weak. On the other hand, the spread spectrum communication method has an advantage that these drawbacks can be eliminated because the spectrum of data is spread by a spread code and transmitted in a wide band. However, on the other hand, high-speed data transmission has been difficult because a wide band is required for the data transmission speed. For example, when transmitting by spreading with an 11-chip spreading code, QPSK (Quadrature Phase
Considering the case of transmission using (Shift Keying) modulation, a bandwidth of 22 MHz is required for 2 Mbps data transmission. If 10 Mbps data is transmitted, a 110 MHz band is required.
Moreover, since the band that can be transmitted wirelessly is limited, it is difficult to transmit high-speed data from this point of view.
Therefore, as a means for performing high-speed transmission in a limited band, a method of delaying and multiplexing a spread signal (hereinafter referred to as a "delay multiplexing method") has been proposed. (See Japanese Patent Application No. 7-206159). By using this method, high-speed transmission can be performed in a limited band.
In the previous example (2Mbps data, 22MHz band)
When the proposed method is used, 4 Mbps data is multiplexed in the same band, and 10 Mbps data communication is possible in 5 multiplexes.
FIG. 6 is a block diagram showing an example of a circuit used in a conventionally proposed delay multiplexing system. In FIG. 6, data generated by a data generation unit 10 is differentially encoded by a differential encoding unit 11, and thereafter, the S / P converter 1
It is parallel-converted into a number to be multiplexed by two. After that, the parallel data is spread by applying the PN code from the PN generator 14 in each of the multiplication units (13-1 to 13-5), and then, in the delay elements (15-1 to 15-5), respectively. Delay. Next, the delayed data is multiplexed by the multiplexer 16 to become a multi-valued digital signal, and the oscillation of the oscillator 18 is modulated by the modulator 17, and the frequency conversion unit 19, the power amplification unit 20, etc. Is transmitted. As a result, high-speed transmission in a limited band becomes possible.
However, as described above, when multiplexing and transmitting with delay, the phenomenon that the error rate deteriorates due to interference between multiplexed signals has occurred.
Therefore, as a method of improving this, the same inventor as in the present application has proposed a method of improving the correlation output at the time of multiplexing (see Japanese Patent Application No. 8-13963). FIG.
FIG. 3 is a diagram showing an example of a conventional circuit in which the error rate deterioration in the delay multiplexing method is improved. This example will be described with reference to FIG. Here, the transmission system is the same as before, and is therefore as shown in FIG. On the other hand, in the receiving system shown in FIG. 7, the received signal is frequency-converted by the frequency converter 21 and converted into a baseband signal, and then the correlation is obtained by the correlator 23. This correlation is latched by the latch unit 24 at the timing of the correlation spike, and then becomes a correlation output in which the correlation processing unit 25 cancels the deterioration due to the autocorrelation. The correlation output is distributed by the distributor 26, and the signal is controlled by the latch controller 29 and latched by the latch units 27 and 28. Here, according to the above-described specific example, latching is performed with two chips or three chips.
After that, the signal is differentiated by the differential section 30 and then discriminated by the discriminating section 31 and demodulated.
FIG. 8 is a block diagram showing an example of the configuration of the correlation processing section in FIG. This is an example in the case of five multiplexes. Although only one system is shown here, two systems are required for the configuration shown in FIG.
The input signal is input to the shift register 25S corresponding to the number of input bits, and four correlation spikes before and after the correlation spike at the desired data demodulation timing are held. These signals are output to the arithmetic unit 2 with the select function.
The calculation is performed by 5P, and the timing is performed by the timing generator 25T. In the timing generator 25T, the timing of the input signal and the output signal is
Are matched by signals of a correlation synchronization circuit not shown in FIG.
FIG. 9 is a block diagram showing an example of the internal configuration of the arithmetic unit with a select function in FIG. This figure 9
By using the means exemplified in (1), a change in signal amplitude due to the influence of the side lobe of the autocorrelation can be reduced, and the error rate can be drastically improved. that is,
According to the following operation. As shown in FIG. 9, the selector 25P
Signals A and F are input to 1, signals B and G are input to the selector 25P2, signals C and H are input to the selector 25P3, and signals D and I are input to the selector 25P4. Here, each selector 25P1-
25P4 selects signals A, B, C and D. Thereafter, the signals A, B, C and D are added by an adder 25P5, and thereafter, a 1/11 division is performed by a divider 25P6.
Is performed, and then the latch unit 25P8
Is latched and output. In this example, the correlation signal before and after is used to improve the correlation output. Here, for example, when the received signal is multiplexed by five, the blocks are divided into five blocks, so the improvement is made by using the five correlation outputs. However, depending on the length of data, the blocks are divided into five blocks. Things that cannot be done.
FIG. 10 is a conceptual diagram showing an example of a state in a configuration of five multiplexed data blocks. In the state illustrated in FIG. 10, in the signal before the multiplexing of the last part of the transmitted data (output of each delay element in FIG. 6), since the data is not a multiple of 5, the last two symbols There is no data and no transmission. For example, when the data is 128 symbols, 25 blocks each having 5 blocks are formed, and 3 blocks are enough. In this case, when the conventional correlation improvement circuit is used, the effect of the correlation improvement cannot be sufficiently exerted because a part of the blocked signal is missing, and the error rate of the last three symbols deteriorates. There was something. In packet communication and the like, if even one bit is incorrect, retransmission is performed, so that the error rate degradation in this portion has greatly affected the packet throughput. The present invention has been made in view of the above-described problems in the related art, and in a direct-sequence spread spectrum communication system using a delay multiplexing method, it is possible to completely improve the correlation regardless of the data length, and improve the error rate. It is an object of the present invention to provide a system and a communication method using the system.
According to the first aspect of the present invention, a signal directly spread by a spreading code is multiplexed using a multiplexing means capable of multiplexing a plurality of series of signals delayed by an arbitrary number of chips. In a delay multiplexing compatible direct spread spectrum communication system for transmitting and receiving signals, the multiplexing means includes means for detecting the number of bits of data to be multiplexed and transmitted. An additional bit is added to the data to be transmitted so as to be an integral multiple of the multiplexing number, and the data is input to the multiplexing means to perform a multiplexing operation.
According to a second aspect of the present invention, there is provided a direct-sequence spread spectrum communication system compatible with the delay multiplexing system according to the first aspect.
Further, there is provided a means adapted to transmit and receive a single signal directly spread by a spreading code.
According to a third aspect of the present invention, in the delay direct multiplexing system direct spread spectrum communication system according to the first or second aspect, the number of the additional bits is an integer multiple of (multiplex number) × (system processing unit, number of bits). It is characterized in that the means is configured in response to the above.
According to a fourth aspect of the present invention, there is provided a delay multiplexing system for transmitting and receiving a multiplexed signal using a multiplexing means capable of multiplexing a plurality of series of signals obtained by delaying a signal directly spread by a spreading code by an arbitrary number of chips. In a direct-sequence spread spectrum communication system, means for inserting additional bits other than the data to be originally transmitted is provided at the head of a multiplex part following a single part in a signal format for setting transmission and reception in a single mode and a multiplex mode. In addition, additional bits other than the data to be originally transmitted are inserted into the head portion of the multiplex portion following the single portion and transmitted.
According to a fifth aspect of the present invention, in the communication method using the spread spectrum direct-sequence communication system according to any one of the second to fourth aspects, the bit length to be inserted as the additional bit is changed from a single mode to a multiplex mode. Is set to a length corresponding to an unstable period that occurs transiently in the operation of the present system when moving to (1).
According to a sixth aspect of the present invention, in the communication method using the spread spectrum direct spread communication system supporting the delay multiplexing method, a multiplex following a single part in a signal format for setting transmission and reception in a single mode and a multiplex mode. This is characterized in that an additional bit other than the data to be transmitted is inserted at the head of the part and transmitted.
According to a seventh aspect of the present invention, in the communication method using the spread spectrum direct spread communication system supporting the delay multiplexing method according to the fifth or sixth aspect, the data format in the multiplex mode in the operation according to the format is convolved by the multiplexing unit. In order to use a method of performing error correction such as encoding, data according to the error correction method is applied to the additional bits, and training of processing is performed using the data.
According to an eighth aspect of the present invention, in the communication method using the delay multiplexing system direct spread spectrum communication system according to any one of the fifth to seventh aspects, the check is performed by preparing a data format for checking a CRC or the like. When the check is performed, the check is performed except for the data portion of the additional bit.
According to a ninth aspect of the present invention, in the communication method using the delay multiplexing system direct spread spectrum communication system according to any one of the fifth to eighth aspects, the number of the additional bits is (multiplex number) × (system processing). (Unit bit number).
In the present invention constituted by the means described above, by adding an additional bit, even in the last part of a packet, if it is five multiplexed, it can always be divided into five blocks, and the symbol loss Disappears. As a result, it is possible to eliminate the problem of the conventional example that the error rate decreases due to the last symbol loss during multiplexing, and it is possible to improve the packet error rate when using packets. The conventional problems can be solved.
In a configuration having a non-multiplexed part and a multiplexed part, the error rate can be improved by selectively adding bits to the multiplexed part, and the packet discarding rate can be improved when a packet is used. Can be performed.
Further, in the present invention, by inserting an additional bit between the single part and the multiplex part, the unstable part of the digital and analog systems when switching from the single part to the multiplex part can be avoided. As a result, the influence of the characteristic degradation portion can be removed from the transmitted data.
By doing so, the throughput of the communication can be increased.
The additional bits at this time are inserted between the single part and the multiplex part, and the number of additional symbols is (transient part +
Unstable section), the data format is defined so that the sum of the number of symbols converted into additional bit symbols and the number of symbols in the multiplexing section is an integral multiple of the multiplexing number, thereby avoiding unstable sections and missing blocks. Accordingly, it is possible to obtain an additional bit that is advantageous in both reducing the error rate.
When convolution error correction is performed, the contents of the additional bits are comment-rolled so that the additional bits can have the function of the pre-processing unit at the time of convolution. A format having an effect of error correction can be obtained from the head of data that becomes valid bits.
When a CRC or the like is checked, the CRC is applied by avoiding the added bits, so that C
Since the RC involves only valid data and does not delete unnecessary additional bits and does not calculate additional bits with a low error rate, effective error detection can be performed and the overall throughput can be increased. .
Also, by setting the number of bits to be added to the number of multiplexes and the number of bits in the processing unit of the system, for example, a common multiple of 8, the transmission length can be expressed in bytes, and the fractional number of bits can be obtained. Is eliminated, and complication of communication processing can be prevented.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described with reference to FIG. FIG. 1 is a diagram for explaining an embodiment in which a data block used in a communication system according to the present invention is configured. In general digital communication such as packet communication, as shown in FIG. 1, the transmission method is generally controlled by an upper layer 1 called a MAC layer. Therefore, when data received from the upper layer 1 is generated as information to be transmitted, a means for adding an additional bit so as to be an integral multiple of the multiplexing number is required, and the data generation unit 2 can perform the processing. It is. Generally, a packet for packet communication includes a bit synchronization section, a frame synchronization section, and various information sections as data necessary for wireless communication, followed by a data section to be transmitted. This data portion contains data transmitted from the upper layer 1. On the other hand, the bit synchronizing unit, the frame synchronizing unit, and the various information units are assumed to be added here by the data generating unit 2. The various information sections generally indicate the type of error correction, the packet length, the scrambling method, and the like.
In wireless communication, the bit synchronization unit is used for detection, carrier recovery, clock recovery, and the like. On the receiver side, the bit synchronization unit determines that the signal is being transmitted, and performs the above processing. Get ready to receive.
For example, a length of 256 bits or the like is used. The frame synchronization unit contains, for example, an m-sequence of 31 bits, and the start timing of data is known from the specific pattern. Therefore, what bit is what information is counted from this timing.
An embodiment of a data block according to the present invention will be described with reference to three examples shown in FIG. First, (B1) of FIG. 1 inserts an additional bit between the bit synchronization unit and the frame synchronization unit. In this embodiment, the symbol length of the data portion is known from information obtained from the upper layer 1. Also, the bit synchronization section that should be attached to it,
Since the symbol lengths of the frame synchronization section and various information sections are also known, the number of additional bits such that the total number of symbols becomes an integral multiple of the multiplexing number is added before the frame synchronization section. As a result, the total number of symbols after addition is, for example, 5 for 5 multiplexing.
The number is divisible by. As a result, even in the last part of the packet, five blocks can always be formed, and no symbols are lost. As a result, it is possible to eliminate the deterioration of the error rate due to the loss of the last symbol at the time of multiplexing, which is a problem of the conventional example, and it is possible to improve the error rate of the packet. Solvable. In this case, the total number of symbols of the entire packet becomes longer due to the addition of bits. However, since demodulation is performed based on the frame synchronization unit as described above, even if bits are added before the frame synchronization unit, there is no demodulation data. No need to change.
Next, (B2) of FIG. 1 will be described. In this example, the bit addition unit is inserted before the start of data. In this case, the start timing of the data is shorter than when no data is inserted. But it will change. However, since the bit addition section is next to the various information sections, by inserting information about the number of bits added to this information section, the head of the data can be found correctly, so that the bit addition can be performed. As in the previous case, it is possible to prevent the error rate from deteriorating due to the last symbol missing part at the time of multiplexing.
Next, (B3) in FIG. 1 will be described. In this example, the bit addition unit is added to the end of the data, that is, the missing part. Length) is determined, and the packet length is included in the various information sections as data. Therefore, even if a bit is added after the original data, that part is not demodulated and has no effect. However, in some systems, the mode is switched to the transmission mode after reception is completed.However, the added bit is at most a part where the multiplexed part is missing and negligible with respect to the switching time. .
Also in this case, it is possible to eliminate the deterioration of the error rate due to the last symbol missing part at the time of multiplexing, as in the case described above.
As described above, when bits are added, (B1), (B2) or (B3) in FIG. 1 may be selected according to the purpose of use. Note that, here, an example is shown in which bits are added to data from the upper layer by the data generation unit 2. However, depending on the system, all data may be created in the upper layer. Figure 1 of
Any of (B1), (B2) and (B3) can be adopted.
The same inventor as in the present application has proposed a configuration of the system having a non-multiplexed part and a multiplexed part (see Japanese Patent Application No. 8-47118). This system configuration having a single part and a multiplex part is used to maintain system compatibility, and the number of multiplexes can be changed for each system. If you do not know, you cannot receive. Therefore, a single portion is set in common, data indicating the number of multiplexes is inserted therein, and the number of multiplexes is switched according to the result. In this way, the number of multiplexes determined on the transmitting side, and on the receiving side,
The receiver settings can be adjusted to allow normal communication. As a result, communication can be performed with the optimal multiplex number according to the line state.
FIG. 2 is a diagram for explaining a data configuration in an embodiment using the present invention for a system having a single part and a multiplex part. FIG. 2A shows a preceding example, in which a non-multiplexed portion (single portion) is followed by a multiplex portion, which is required before switching to a non-multiplex portion as described above. And a bit synchronizing section, a frame synchronizing section, a multiplex information section, and the like similar to those shown in FIG. Therefore, in the present invention, places where the bit addition is effective are shown in FIGS. 2B and 2C.
In FIG. 2B, bits are added between the single part and the multiplex part such that the number of symbols in the multiplex part becomes an integral multiple of the multiplex number. In this case, information indicating which bit is valid is included in multiplexed information or the like, which is one of the information contained in the various information sections of the single part,
By using this information, data excluding the bit addition part is transmitted to the upper layer as data. As a result, the problem that the error rate is high in the last part of the packet can be solved as in the first embodiment.
In FIG. 2C, such a bit is added after the data of the multiplexing unit. In this case, unlike the above example, the data of the last added portion is unnecessary. However, here, since the number of data originally contained in the information data is known, the same information as the conventional information is used. Data. As described above, the present invention can be applied to a configuration having a non-multiplexed part and a multiplexed part. As a result, the error rate can be improved and the packet discard rate can be improved.
Next, a third embodiment of the present invention will be described. The configuration having a non-multiplexed portion (single portion) and a multiplexed portion has been described above. However, in an actual system, an unstable time portion occurs in a digital system and an analog system when moving from a non-multiplexed portion to a multiplexed portion. I do. This is because the clock needs to be changed to a multiple of the multiplex number from here, and the instability due to the switching operation and the stabilization time of the analog system due to the change in the signal amplitude are required.
FIG. 3 is a conceptual diagram for explaining a transmission / reception state at the time of switching from single to multiplex, and a change in the state will be described below with reference to FIG. In the single part, the spread signals are sent one by one sequentially. On the other hand, in the multiplex portion, five spread signals are generated in parallel, and the spread signals are delayed and multiplexed and transmitted. In FIG.
This state is shown. In the single part, [1] and [2] spread with a spreading code are transmitted, but when switching to multiplexing, [3], [4], [5], [ 6],
The five blocks of [7] are multiplexed and transmitted. Next, [8],
[9], [10], [11], [1
2] is the next block.
In this case, [3], [4], [5],
[6] and [7] are transient portions in which a non-multiplexed portion and a multiplexed portion coexist. However, as explained earlier, even if all the signals themselves are changed to multiplex signals,
Unstable parts occur for a while due to instability of digital and analog systems. In digital systems, this time can be determined based on a few bits and the number of bits regardless of the data rate, but in analog systems, in general, the stabilization time is determined by several microseconds and the time constant of the element used. Many. Therefore, it cannot be determined as several bits, but is determined by the time constant divided by the transmission rate. Therefore, the number of symbols in this unstable part depends on the system at that time,
It depends on the data rate.
In the present invention, since the unstable portion and the transient portion have a low error rate due to instability, bits irrelevant to data are added to this portion. The number of bits is set by the minimum number of bits determined by analog or the like, but since there is a part (S part) that can be formed in the middle of the bit, the bit is rounded up in such a case. Of course, the guard period of the unstable portion can be set longer in consideration of variations in the elements of the analog system. As a result,
The necessary transmission data can always be sent with a good error rate, so that a stable packet throughput can always be obtained. The number of bits can be determined from the characteristics of the transceiver, the data rate, and the like. However, it is also possible to embed the number of additional bits as information in single-part multiplexed information. As described above, in the present invention, the effect of the characteristic degraded portion when switching from the single portion to the multiplex portion is obtained by additionally inserting a bit irrelevant to the data to be originally transmitted between the single portion and the multiplex portion. Be able to remove from the data to be transmitted. By doing so, the packet throughput can be increased.
In the above invention, the number of bits to be added is set based on the stabilization time. However, as described above, when bits are added as in the invention showing the embodiment, it is desirable that the number be an integral multiple of the multiplex number. Therefore, in the embodiment of the present invention, the lower limit of the number of bits to be added is based on the time during which the stabilization time is reached, and the number is an integer multiple of the multiplex number. By doing this,
The added bit can perform two roles at the same time.
FIG. 4 is a diagram showing a data format having an additional bit portion of a predetermined number of bits used in the present invention. In FIG. 4, the additional bit part is inserted between the single part and the multiplex part, and the number of additional symbols inserted therein is the time until the operation shown in FIG. + Unstable part), and the sum of the number of symbols converted into additional bit symbols and the number of symbols in the multiplexing part is an integral multiple of the multiplexing number. By defining the data format in this way, it is possible to satisfy the two conditions and provide an additional bit that provides both advantages.
Although the configuration having the multiplexed part and the non-multiplexed part has been described above, in this case, the transmission rate of the multiplexed part relative to the non-multiplexed part is multiplied by the number of multiplexes, so that the error rate deteriorates accordingly. . For example, in the case of five multiplexes,
There is a 7 dB C / N (Carrier to Noise) degradation. Therefore, error correction or the like may be performed to improve the error rate of the multiplex part. Among error corrections, convolutional codes are said to have a great effect. However, in the case of a convolutional code, in order to store data in a shift register and construct data to be transmitted from the data, when convolution is started, data is indefinite until data is stored in the shift register. In general, first, the shift register is initially set to all 1, and data to be transmitted is sequentially input thereto.
In the case of convolution with a constraint length of 7, since there are seven shift registers, seven ones are stored first. When demodulating such convolved data,
In the first seven bits, 1 comes out, and data unrelated to the original data comes out. To avoid this, there is a method to keep the last shift register value sent in the previous packet.However, in packet communication, data is completed for each packet, which makes it difficult to correct errors. Remains.
Therefore, in the present invention, the additional bits inserted between the non-multiplexed part and the multiplexed part in the above embodiment have this function. FIG. 5 is a block diagram illustrating an example of a configuration of the convolutional encoding circuit. In FIG. 5, a clock controller 7 controls a data generator 4, a data generator 5, and a convolutional encoder 6. In the convolution operation, the convolution is １ ／ or 、, so that the rate of the data generation unit 4 becomes half the transmission rate to be transmitted after the convolution coding. Since a bit addition unit is added between the single unit and the multiplex unit, the clock controller 7 applies
A control is made so that a clock of about twice is added and additional bit insertion timing is added. The additional bits are provided with preprocessing data suitable for convolution. That is, for example, all the seven bits stored in the shift register are set to 1 in the additional bits, and the convolution is transmitted from the first bit of the additional bits. On the demodulation side,
Among the received data, the convolution including the additional bit portion is decoded, and from the decoded data, the start position indicated by the information bit is used as valid data.
By doing so, it becomes possible to give the additional bits the function of the pre-processing part at the time of convolution. Also, by adding a few bits (for example, 7 bits) to the last part of the data, error-corrected data can be obtained up to the last data bit. As described above, the function of both the multiplexing and the additional bit inserted between the multiplexing parts is provided, so that efficient transmission can be performed. In addition, since the start of valid data can be known from the information in the single part, the data is transferred to the upper layer from there.
In packet communication, FEC (Forward
Error Correction) and AR to retransmit
The Q (Automatic Repeat Request) method is generally used in many cases. In that case, CRC (Cyclic Redundancy chec
A check method such as k) is used. In the case of having one multiplex and a multiplex part, there are a case where CRC is applied to only the multiplex part and a case where CRC is applied to both the single part and the multiplex part.
In this case, the third and fourth embodiments are characterized in that the added bit has a poor error rate, and therefore CRC is applied avoiding this. The CRC checks from the specified start portion and calculates the entire data length, so that the start bit starts from the valid data portion that is known from the information in the single part. As a result, the CRC affects only valid data, and does not delete unnecessary additional bits and does not calculate additional bits with a low error rate, so that effective error detection can be performed and the overall throughput can be increased. Become like
In the above embodiments, the number of bits to be added is such that the sum of the numbers of symbols is an integral multiple of the number of multiplexes. However, in an actual communication system, processing is often performed in units of 8 bits or 16 bits, and data follows the processing. The packet length and valid data length incorporated in the single part are often indicated in byte units (8 bits) and word units (16 bits). In this case, if the number of additional bits is added by considering only the multiplex number, the transmission length is not a multiple of 8 or 16 as a whole, and the processing becomes complicated.
Therefore, the number of bits to be added is
A common multiple of By doing so, the transmission length does not break down a multiple of 8, 16 and the processing does not become complicated while acting as an additional bit. The minimum value is the least common multiple, but in an actual system, if the length is a multiple of a common multiple, the effect is the same for any number. By doing as described above, the transmission length can be expressed in units of bytes, no fractional bits appear, and the communication processing can be prevented from becoming complicated.
According to the first aspect of the invention, by adding the additional bit, even if the number of multiplexes is 5, for example, even in the last part of the packet, it is possible to always make five blocks, and symbols are not lost. As a result, it is possible to eliminate the deterioration of the packet error rate due to the lack of the last symbol at the time of multiplexing, which is a problem of the related art, and to improve the communication performance in the communication system.
Effect of Claim 2 In addition to the effect of Claim 1, it is possible to further adapt to a system having a non-multiplexed part (single part), thereby improving the transmission error rate as a whole system, The packet loss rate can be improved.
Effect of Claim 3 In addition to the effects of Claims 1 and 2, the transmission length can be increased by setting the number of bits to be added to a multiplex number and a common multiple of the processing unit of the system (for example, 8 or 16 bits). It can be expressed in byte units, and no fractional bit number is output, so that complication of communication processing can be prevented.
According to the fourth aspect of the present invention, an additional bit is inserted at the head of the multiplex part following the single part, and by using this additional bit, it is possible to cope with a failure occurring in the system, and the data to be transmitted is lost. Communication can be prevented and communication performance can be improved.
Effect of Claim 5: In addition to the effects of Claims 2 to 4, the length of the additional bit according to this claim is not affected by unstable operation in the transition period from single to multiplex, and furthermore, By defining the data format so as to be an integral multiple of the number, both the advantages of lowering the error rate due to block loss are brought.
Effect of Claim 6 In addition to the effect of Claim 2, by inserting an additional bit between the single part and the multiplex part, the characteristic deterioration does not affect the data to be transmitted. Packet throughput can be increased.
Effect of Claim 7 In addition to the effects of Claims 5 and 6, in performing error correction of convolution, an additional bit is provided so that the additional bit can have a function of a pre-processing part at the time of convolution. By controlling the contents of the bits, even at the time of convolution, it is possible to set a format having an effect of error correction from the head of the data that becomes valid bits.
Effect of Claim 8 In addition to the effects of Claims 5 to 7, in addition to the effect of CRC, the CRC is applied only to valid data by applying CRC while avoiding added bits when checking CRC or the like. ## EQU2 ## Since unnecessary additional bits are not deleted and additional bits with a low error rate are not calculated, effective error detection can be performed and the overall throughput can be increased.
Effect of Claim 9 In addition to the effect of Claims 5 to 8, the number of bits to be added is set to a common multiple of the number of multiplexes and the number of bits of the processing unit of the system, for example, 8 bits, so that the transmission length is increased. Can be expressed in byte units, no fractional bit number appears, and communication processing can be prevented from becoming complicated.
FIG. 1 is a diagram for explaining an embodiment in the case of configuring a data block used in a communication system according to the present invention.
FIG. 2 is a diagram for explaining a data configuration in an embodiment using the present invention in a system having a single part and a multiplex part.
FIG. 3 is a conceptual diagram for explaining a transmission signal and a reception state when switching from single to multiplex (five multiplex).
FIG. 4 is a diagram showing a data format having an additional bit portion of a predetermined number of bits used in the present invention.
FIG. 5 is a block diagram illustrating an example of a configuration of a convolution encoding circuit used in the embodiment of the present invention.
FIG. 6 is a block diagram showing an example of a circuit used in a delay multiplexing method conventionally proposed in direct spread spectrum communication.
FIG. 7 is a diagram illustrating an example of a conventional receiving circuit in which the error rate degradation in the delay multiplexing method is improved.
8 is a block diagram illustrating an example of a configuration of a correlation processing unit in the conventional receiving circuit illustrated in FIG.
9 is a block diagram illustrating an example of an internal configuration of an arithmetic unit with a select function in the correlation processing unit illustrated in FIG. 8;
FIG. 10 is a conceptual diagram showing an example of a transmission state in a conventional configuration of five multiplexed data blocks.
1 upper layer, 2 data generator, 3 modulator, 4 data generator, 5 data generator, 6 convolutional encoder,
7 clock controller, 10 data generator, 11
... Differential encoder, 12 ... S / P converter, 13-1 to 13
-5: Multiplying unit, 14: PN generator, 15-1 to 15-5
... delay element, 16 ... multiplexer, 17 ... modulator, 18, 22
... oscillator, 19 ... frequency converter, 20 ... power amplifier, 2
DESCRIPTION OF SYMBOLS 1 ... Frequency conversion part, 23 ... Correlator, 24 ... Latch part, 25 ... Correlation processing part, 25S ... Shift register, 25
P ... Calculator with select function, 25P1 ... Selector, 25
P2 ... selector, 25P3 ... selector, 25P4 ... selector, 25P5 ... adder, 25P6 ... divider, 25P7
... Timing control, 25P8 ... Latch part, 25
P9: adder / subtractor, 25T: timing generator, 26: distributor, 27, 28: latch unit, 29: latch controller, 30: differential unit, 31: discriminator.
1. A delay direct multiplexing-compatible spectrum direct spreading method for transmitting and receiving a multiplexed signal using a multiplexing means capable of multiplexing a plurality of series of signals obtained by delaying a signal directly spread by a spreading code by an arbitrary number of chips. In communication systems,
Means for detecting the number of bits of data to be multiplexed and transmitted using the multiplexing means, wherein the number of symbols at the time of modulation is an integer multiple of the number of multiplexes in the multiplexing means; A direct-sequence spread spectrum communication system for a delay multiplexing method, wherein an additional bit is added and input to the multiplexing means to perform a multiplexing operation.
2. A delay spread multiplexing system direct spread spectrum communication system according to claim 1, further comprising means adapted to transmit and receive a single signal directly spread by a spreading code. A multiplexing compatible direct spread spectrum communication system.
3. The delay spread multiplexing system direct spread spectrum communication system according to claim 1, wherein the number of additional bits is an integer multiple of (multiplex number) × (system processing unit, number of bits). A direct-sequence spread-spectrum communication system supporting a delay multiplexing method.
4. A delay multiplexing system compatible spectrum direct spread transmitting / receiving a multiplexed signal using a multiplexing means capable of multiplexing a plurality of series signals obtained by delaying a signal directly spread by a spreading code by an arbitrary number of chips. In communication systems,
In the signal format for setting transmission and reception in the single and multiplex modes, means for inserting additional bits other than the data to be transmitted at the beginning of the multiplex part following the single part are provided. A spread spectrum direct spread communication system compatible with a delay multiplexing method, wherein an additional bit other than the data to be originally transmitted is inserted into a portion and transmitted.
5. The communication method according to claim 2, wherein the bit length to be inserted as the additional bit is changed from a single mode to a multiplex mode. A communication method using a direct-sequence spread-spectrum communication system compatible with a delay multiplexing method, wherein the length is set to a length corresponding to an unstable period that occurs transiently in the operation of (1).
6. A communication method using a direct-sequence spread spectrum communication system supporting a delay multiplexing method according to claim 2,
Delay multiplexing characterized in that additional bits other than the data to be originally transmitted are inserted and transmitted at the beginning of a multiplex part following a single part in a signal format for setting transmission and reception in single and multiplex modes. A communication method using a system-directed spread spectrum direct communication system.
7. A communication method using a spread-spectrum direct-sequence communication system supporting a delay multiplexing method according to claim 5 or 6, wherein an error such as convolutional encoding in a multiplexing unit is used as a data format in a multiplex mode in an operation according to the format. A communication method using a spectrum direct communication system compatible with a delay multiplexing method, wherein data according to the error correction method is assigned to the additional bits so as to use a method of performing correction, and training of processing is performed using the data.
8. The communication method according to claim 5, wherein the check is performed by preparing a data format for checking a CRC or the like. A communication method using a direct-sequence spread spectrum communication system compatible with a delay multiplexing method, wherein the check is performed excluding a data portion of an additional bit.
9. The communication method according to claim 5, wherein the number of the additional bits is (multiplex number) ×
A communication method using a direct-sequence spread spectrum communication system compatible with a delay multiplexing method, wherein the communication number is an integer multiple of (the number of processing unit bits of the system).
JP9065026A 1997-03-18 1997-03-18 Spectrum direct spread communication system coping with delay multiplex system and communication method using the system Granted JPH10262029A (en)
JP9065026A JPH10262029A (en) 1997-03-18 1997-03-18 Spectrum direct spread communication system coping with delay multiplex system and communication method using the system
US09/367,384 US6501786B1 (en) 1997-03-18 1998-02-25 Direct spread spectrum communication system corresponding to delayed multiplex mode, and method of communication using the system
EP98905638A EP0987849A4 (en) 1997-03-18 1998-02-25 Direct spread spectrum communication system corresponding to delayed multiplex mode, and method of communication using the system
AU61156/98A AU6115698A (en) 1997-03-18 1998-02-25 Direct spread spectrum communication system corresponding to delayed multiplex mode, and method of communication using the system
PCT/JP1998/000757 WO1998042094A1 (en) 1997-03-18 1998-02-25 Direct spread spectrum communication system corresponding to delayed multiplex mode, and method of communication using the system
JPH10262029A true JPH10262029A (en) 1998-09-29
ID=13275062
JP9065026A Granted JPH10262029A (en) 1997-03-18 1997-03-18 Spectrum direct spread communication system coping with delay multiplex system and communication method using the system
US (1) US6501786B1 (en)
EP (1) EP0987849A4 (en)
JP (1) JPH10262029A (en)
AU (1) AU6115698A (en)
WO (1) WO1998042094A1 (en)
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CN107864032B (en) * 2017-11-21 2020-05-12 西安空间无线电技术研究所 Method for fusion processing of bit synchronization and frame synchronization of spread spectrum signal
JPH0955714A (en) * 1995-08-11 1997-02-25 Sharp Corp Spread spectrum communication system
JP3244434B2 (en) * 1996-01-30 2002-01-07 シャープ株式会社 Spread spectrum communication reception method
JP3337613B2 (en) 1996-03-05 2002-10-21 シャープ株式会社 Spread spectrum communication system
JP3244421B2 (en) * 1996-03-11 2002-01-07 シャープ株式会社 Spread spectrum signal receiver
1997-03-18 JP JP9065026A patent/JPH10262029A/en active Granted
1998-02-25 AU AU61156/98A patent/AU6115698A/en not_active Abandoned
1998-02-25 WO PCT/JP1998/000757 patent/WO1998042094A1/en not_active Application Discontinuation
1998-02-25 US US09/367,384 patent/US6501786B1/en not_active Expired - Fee Related
1998-02-25 EP EP98905638A patent/EP0987849A4/en not_active Withdrawn
EP0987849A4 (en) 2007-04-25
AU6115698A (en) 1998-10-12
WO1998042094A1 (en) 1998-09-24
US6501786B1 (en) 2002-12-31
EP0987849A1 (en) 2000-03-22
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