Source: http://www.google.com/patents/US7349513?dq=U.S.+Patent+No.+4,528,643)
Timestamp: 2014-10-25 03:12:00
Document Index: 575673185

Matched Legal Cases: ['in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine']

Patent US7349513 - Process, voltage, temperature independent switched delay compensation scheme - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable...http://www.google.com/patents/US7349513?utm_source=gb-gplus-sharePatent US7349513 - Process, voltage, temperature independent switched delay compensation schemeAdvanced Patent SearchPublication numberUS7349513 B2Publication typeGrantApplication numberUS 10/702,502Publication dateMar 25, 2008Filing dateNov 7, 2003Priority dateJun 30, 1998Fee statusPaidAlso published asUS6327318, US6683928, US7889826, US8379786, US20020015460, US20040091075, US20080143405, US20110095796, US20130135019Publication number10702502, 702502, US 7349513 B2, US 7349513B2, US-B2-7349513, US7349513 B2, US7349513B2InventorsGurpreet Bhullar, Graham AllanOriginal AssigneeMosaid Technologies IncorporatedExport CitationBiBTeX, EndNote, RefManPatent Citations (10), Referenced by (7), Classifications (13), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetProcess, voltage, temperature independent switched delay compensation schemeUS 7349513 B2Abstract A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.
1. A circuit for modeling a coarse delay element with a plurality of fine delay elements for a delay locked loop, the circuit comprising:
first and second parallel delay paths receiving a clock signal, the first path including a first plurality of delay elements and the second path including a second plurality of delay elements;
a phase detector for receiving the first and second clock delay signals from the first and second delay paths respectively, for detecting a phase difference between said first and second clock delay signals, the phase detector providing the phase difference to a counter; and
a decoder for receiving a signal from the counter, the decoder being connected to the first plurality of delay elements within the first delay path for adjusting the delay provided by the first delay path until the first and second clock delay signals are in a locked state, the delay lock loop including
a coarse delay line for receiving a system clock,
a fine delay line coupled to an output of the coarse delay line for providing a delay clock signal, and
a main phase detector for receiving the system clock and the delay clock signal, the main phase detector coupled to a main fine counter, the main fine counter being adjusted by the signal from the counter for adjusting the fine delay line.
2. The circuit according to claim 1 wherein the first plurality of delay elements comprise programmable delay elements.
3. The circuit according to claim 1 wherein the first plurality of delay elements comprise programmable digital delay elements.
4. The circuit according to claim 1 wherein the second plurality of delay elements comprise the same delay elements of the first plurality of delay elements in addition to a course delay element.
5. The circuit according to claim 1 wherein the second delay path comprises at least one coarse delay element.
6. The circuit according to claim 1 wherein the second delay path comprises at least one coarse delay element in addition to the first delay path.
7. The circuit according to claim 1 wherein the first delay path consists of fine delay elements.
8. The circuit according to claim 1 wherein the phase detector comprises a flip-flop circuit.
9. The circuit according to claim 1 wherein the counter is a count-up count-down type counter.
10. The circuit according to claim 1 wherein the counter is coupled to the main fine counter.
11. The circuit according to claim 10 wherein the signal provided by the counter to the main fine counter is substantially equal to a number of delays provided by the fine delay elements within the fine delay line that correspond to a delay provided by a course delay element within the coarse delay line.
12. A circuit for modeling a coarse delay element with a plurality of fine delay elements for a delay locked loop, the circuit comprising:
first and second parallel delay paths receiving a clock signal, the first path comprising a first plurality of delay elements and the second path including a second plurality of delay elements;
a phase detector for receiving the first and second clock delay signals from the first and second delay paths respectively, and for detecting a phase difference between said first and second clock delay signals, the phase detector providing the phase difference;
a counter for receiving the phase difference from the phase detector and for generating a signal for controlling a plurality of delay elements within the first delay path for adjusting a delay provided by the first delay path until the delay provided by the first and second paths are substantially equal, the delay lock loop including
a main phase detector for receiving the system clock and the delay clock signal, the phase detector coupled to a main fine counter, the main fine counter being adjusted by the signal from the counter for adjusting the fine delay line.
13. The circuit according to claim 12 wherein the first plurality of delay elements comprise programmable delay elements.
14. The circuit according to claim 12 wherein the first plurality of delay elements comprise programmable digital delay elements.
15. The circuit according to claim 12 wherein the second plurality of delay elements comprise the same delay elements of the first plurality of delay elements in addition to a course delay element.
16. The circuit according to claim 12 wherein the second delay path comprise at least one coarse delay element.
17. The circuit according to claim 12 wherein the second delay path comprise at least one coarse delay element in addition to the first delay path.
18. The circuit according to claim 12 wherein the first delay path consists of fine delay elements.
19. The circuit according to claim 12 wherein the phase detector comprises a flip-flop circuit.
20. The circuit according to claim 12 wherein the counter is a count-up count-down type counter.
21. The circuit according to claim 12 wherein the counter is coupled to the main fine counter.
22. The circuit according to claim 21 wherein the signal provided by the counter to the main fine counter is substantially equal to a number of delays provided by the fine delay elements within the fine delay line that correspond to a delay provided by a course-delay element within the coarse delay line.
This application is a continuation of U.S. application Ser. No. 09/968,897 filed Oct. 3, 2001 now U.S. Pat. No. 6,683,928, which is a continuation application of U.S. Ser. No. 09/106,755 filed Jun. 30, 1998, and issued on Dec. 4, 2001 as U.S. Pat. No. 6,327,318.
In accordance with an emobodiment of the inveniton, a circuit for modeling a course delay element with a plurality of fine delay elements, the circuit comprising first and second parallel delay paths receiving a clock signal, the first path including a first plurality of delay elements and the second path including a second plurality of delay elements, a phase detector receiving first and second clock delay signals from the first and second delay paths respectively for detecting a phase difference between said first and second clock delay signals, the phase detector providing the phase difference to a counter and a decoder receiving a signal from the counter, the decoder being connected to the first plurality of delay elements within the first delay path for adjusting the delay provided by the first delay path until the first and second clock delay signals are in a locked state.
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