Source: http://www.google.com/patents/US4755986?dq=5787449
Timestamp: 2016-07-24 01:55:25
Document Index: 358617575

Matched Legal Cases: ['art 210', 'art 211', 'art 211', 'art 221', 'art 221', 'art 210']

Patent US4755986 - Packet switching system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA packet switching system mainly consists of a packet transmission controller, connected to a line group, for performing transmission control of a data packet, and a packet switching unit for receiving the data packet from the packet transmission controller to perform switching processing. The packet...http://www.google.com/patents/US4755986?utm_source=gb-gplus-sharePatent US4755986 - Packet switching systemAdvanced Patent SearchPublication numberUS4755986 APublication typeGrantApplication numberUS 06/906,282Publication dateJul 5, 1988Filing dateSep 11, 1986Priority dateSep 13, 1985Fee statusPaidPublication number06906282, 906282, US 4755986 A, US 4755986A, US-A-4755986, US4755986 A, US4755986AInventorsHideyuki HirataOriginal AssigneeNec CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (3), Referenced by (77), Classifications (8), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetPacket switching system
US 4755986 AAbstract
A packet switching system mainly consists of a packet transmission controller, connected to a line group, for performing transmission control of a data packet, and a packet switching unit for receiving the data packet from the packet transmission controller to perform switching processing. The packet switching unit includes a packet separator for separating the data packet into a header part and a data part, a packet header processor for updating the separated header part, a packet data buffer for storing the separated data part, and a packet combiner for combining the output from the packet data buffer and the output from the packet header processor and supplying a combined packet to the packet transmission controller.
1. A packet switching system including packet transmission control means, connected to a line group, for performing transmission control of a data packet, and packet switching means for receiving the data packet from said packet transmission control means to perform switching, whereinsaid packet switching means comprises: packet separating means for separating the data packet into a header part and a data part; packet header processing means for updating the separated header part; packet data buffer means for storing the separated data part; and packet combining means for combining the output from said packet data buffer means and the output from said packet header processing means and supplying a combined packet to said packet transmission control means. 2. A system according to claim 1 wherein said packet separating means supplies the separated header part to said packet header processing means after adding to the separated header part an input line identifier which distinguishes a line terminal control number.
3. A system according to claim 2 wherein said packet header processing means comprises an input controller for receiving the output from said packet separating means to geneate a first reference address including said header part and said input line identifier; a processing routine controller which is referred to by the first reference address to generate a second reference address; active template reference means which is referred to by the second reference address to generate active template reference data; an active template memory which incorporates a plurality of active templates and receives the active template reference data to write in the active template; active template reading means for reading out an active template satisfying a fire condition from said active template memory; an operation circuit group which receives the active template read out from said active template memory to perform operation processing and generates a third reference address to supply it to an input terminal of said processing routine controller; and an output controller for receiving the active template storing all the necessary data from said active template memory to supply the undated header part to said packet combining means.
4. A system according to claim 3 wherein said processing routine controller comprises a status reference table memory for generating a status number in accordance with said first reference address which is the output from said input controller; a processing routine table memory for generating the second reference address upon reception of the outputs from said input controller and said status reference table memory; and an arbitrator for controlling the input to said status reference table memory.
5. A system according to claim 3, wherein said operation circuit group consists of a plurality of operation circuits including processors each of which is parallel-connected between the output of said template reading means and the input of said processing routine controller, and said operation circuits are selected by said active template reading means.
6. A system according to claim 3, wherein said active template reference means includes a memory storing addresses of said active template memory.
The present invention relates to a packet switching system.
In a packet switching system having a packet transmission controller, connected to a line group, for controlling packet transmission, and a packet switching unit for switching a data packet input through the packet transmission controller, the conventional packet switching unit comprises a general-purpose processor. The packet switching unit stores a received data packet in a common packet storage area in a main memory under the control of the processor, and performs switching and flow control. Input and output ports for the packet transmission controller are connected to a system bus together with the main memory and a direct memory access channel. Such a packet switching system is disclosed in U.S. Pat. No. 4,494,230 (Jan. 15, 1985). The data packet consists of a header part and a data part. In particular, during switching and flow control of the data packet, the header part must be directly processed by the processor. In the conventional packet switching unit, the main memory of the processor also serves as a packet path and a switch. For this reason, although the length of the header part to be processed by the processor is sufficiently shorter than the total length of the data packet, all the received packet data must be stored in the main memory. Therefore, it is difficult to obtain a storage area enough to achieve large-capacity, high-speed packet switching.
It is an object of the present invention to provide a packet switching system free from the above drawbacks and capable of large-capacity, high-speed packet processing by a simple arrangement without being influenced by the length of a data part.
According to the present invention, there is provided a packet switching system including packet transmission control means, connected to a line group, for performing transmission control of a data packet, and packet switching means for receiving the data packet from the packet transmission control means to perform switching, wherein the packet switching means comprises: packet separating means for separating the data packet into a header part and a data part; packet header processing means for updating the separated header part; packet data buffer means for storing the separated data part; and packet combining means for combining the output from the packet data buffer means and the output from the packet header processing means and supplying a combined packet to the packet transmission control means.
FIG. 1 is a block diagram showing the entire arrangement of a packet switching system according to an embodiment of the present invention;
FIG. 2 is a block diagram of a packet header processor shown in FIG. 1;
FIG. 3 is a sequence diagram for explaining the operation of the packet header processor shown in FIG. 2; and
FIG. 4 is a flowchart showing the operation of an active memory shown in FIG. 2.
A packet switching system according to an embodiment of the present invention will now be described with reference to the accompanying drawings.
FIG. 1 is a block diagram showing the entire arrangement of the packet switching system according to an embodiment of the present invention. Referring to FIG. 1, the packet switching system consists mainly of a packet transmission controller 10 and a packet switching unit 20. The packet transmission controller 10 has line terminal controls 111 to 11n respectively connected to lines 11 to 1n, a microprocessor 12 for performing control, maintenance, and management of a bus, and a main memory 13, an output port 14, and an input port 15 which are connected to system bus 16 of the microprocessor 12. The main memory 13 has a RAM (random access memory) and a ROM (read-only memory).
The packet switching unit 20 as the main feature of the present invention comprises a packet separator 21, which has an input terminal 21A connected to the output port 14 of the packet transmission controller 10, and separates a data packet input from the output port 14 into a header part and a data part; a packet data buffer 22, the input terminal of which is connected to an output terminal 21B of the packet separator 21 for outputting the separated data part, and which temporarily stores input data; a packet combiner 23, one input terminal 23A of which is connected to the output terminal of the packet data buffer 22, and which combines an input from its other input terminal 23B (to be described later) and an input from the input terminal 23A; and a packet header processor 30, the input terminal of which is connected to an output terminal 21C of the packet separator 21 for outputting the separated header part, and which modifies the input at its input terminal to supply it to the input terminal 23B of the packet combiner 23.
The operation of the packet switching system shown in FIG. 1 will now be described. The lines 11 to 1n and the packet transmission controller 10 communicate logical multiplexed data packets with each other through the corresponding line terminal controls 111 to 11n upon instruction from the microprocessor 12. For example, a data packet received by the line terminal control 111 is transferred to the packet separator 21 through the system bus 16 and the output port 14 under the control of the microprocessor 12. The packet separator 21 identifies a call by the line number and the logic channel of the received packet, and discriminates the type of the packet. If the received packet is a data packet, the separator 21 separates the header part necessary for control from the data packet, and adds an input line identifier to the header part to form an input token. The separator 21 then transfers the input token to the packet header processor 30 and transfers the data part to the packet data buffer 22. At this time, the packet data buffer 22 stores the data part received in accordance with an instruction from the packet separator 21.
The token input to the packet header processor 30 is subjected to predetermined processing to be updated, and is then output to the packet combiner 23. The packet combiner 23 combines the updated header part supplied from the packet header processor 30 and the data part read out from the packet data buffer 22 to form the updated packet and supplies it to the input port 15. The packet supplied to the input port 15 is sent onto the line 1n via the system bus 16 and, e.g., the line terminal control 11n upon instruction from the microprocessor 12.
FIG. 2 is a block diagram of an embodiment of the packet header processor 30 shown in FIG. 1. Referring to FIG. 2, the packet header processor 30 comprises an input controller 31 for receiving the output from the packet separator 21; a processing routine controller 32 for receiving the output from the controller 31; an active template reference circuit 33 for receiving the output from the controller 32; an active template memory 34 for receiving the output from the circuit 33; an active template reading circuit 35 for reading out the content of the memory 34; an operation circuit group 40 for performing a predetermined operation upon reception of the output from the reading circuit 35 and supplying the operation result to the controller 32; and an output controller 36 for supplying an output token to the packet combiner 23 upon reception of the output from the reading circuit 35.
The processing routine controller 32 comprises an arbitrator 321, connected to the output terminal of the input controller 31, for controlling an input token; a status reference table memory 322, connected to the output terminal of the input controller 31, for storing the status of the input token for every line; and a processing routine table memory 323 for receiving the outputs from the memory 322 and the controller 31 to determine the flow of following processing based on the input data.
The active template reference circuit 33 comprises a memory storing reference addresses of active templates 216 which does not satisfy a fire condition or of new templates in the active template memory 34. The active template memory 34 comprises a memory storing active templates.
The active template reading circuit 35 comprises a FIFO (first-in first-out) register 351 and a scheduler 352 for controlling the FIFO register 351.
The operation circuit group 40 comprises a plurality of operation circuits connected in parallel with the output terminal of the reading circuit 35. Each operation circuit consists of a FIFO register 411 commonly connected to the output terminal of the FIFO register 351 of the reading circuit 35, a processor 412 comprising a general-purpose processor, and a FIFO register 413, the input terminal of which is connected to the output terminal of the processor 412, and the output terminal of which is connected to the input terminal of the table memory 322 of the controller 32.
The operation of the packet header processor 30 shown in FIG. 2 will be described with reference to the sequence diagram in FIG. 3 and the flowchart shown in FIG. 4.
Referring to FIG. 3, in the packet separator 21, a data part 210 and a header part 211 are separated, and an input token consisting of the header part 211 and an input line identifier 212 is supplied to the input controller 31, as described previously. A status number of a corresponding logic line is read out from the status reference table memory 322 with reference to control data f(211,212) included in the input token from the controller 31. The processing routine table memory 323 is referred to by a new reference address 213 generated by the status number and the control data f(211,212) of the input token directly supplied thereto, and a reference address 214 of the reference circuit 33 is then added to the input token. Active template reference data 215 is added to the token (211,212,213,214) referring to the reference circuit 33, and the token is then transferred to the active template memory 34. The token is written in an active template 216 together with the data of its own. An active template 217 which satisfies a "fire" condition is read out by the reading circuit 35, and is transferred to the operation circuit group 40 or the output controller 36 in accordance with an instruction written in the active template 217.
FIG. 4 is a flowchart showing a embodiment of processing of the active template memory 34. Referring to FIG. 4, the left branch of flow shows processing when input data is a temporary token, and the right branch of flow shows the processing when input data is a release instruction token necessary for interrupting the processing.
The active template 217 input to one operation circuit of the operation circuit group 40 selected by the active template reading circuit 35 is subjected to operation processing, and an operation result 218 is supplied to the processing routine controller 32 as an input token having a new reference address 219. The above operation is repeated a required number of times.
If the active template of the memory 34 stores all data necessary for final output, the template is fired and is supplied to the output controller 36. The output controller 36 supplies the output token consisting of an updated packet header part 221, an output line identifier 222, and output control data 223 to the packet combiner 23. The combiner 23 combines the updated header part 221 and the data part 210 supplied from the packet data buffer 22 to form a new packet, and supplies it to the input port 15.
According to the present invention as described above, a data packet constituting a major traffic of packet communication in packet switching processing is separated into a data part and a header part, and only the header part is processed at high speed by a packet header processor having a pipeline structure on the basis of a data flow principle. For this reason, large-capacity, high-speed processing is allowed without being influenced by the length of the data part of the packet.
Since only the data part is subjected to buffering, the capacity of the buffer memory can be freely selected regardless of the processor, and a switching means for the packet length can be achieved by a simple circuit arrangement.
Since the packet header processor is a data flow type processor, the parallel flow property of the packet switching processing, such as development of a facility field, checking of facilities, and the like can be easily realized, thereby greatly improving processing speed and throughput.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4494230 *Jun 25, 1982Jan 15, 1985At&T Bell LaboratoriesFast packet switching systemUS4603416 *Dec 12, 1983Jul 29, 1986Michel Servel(Time division multiplex) switching system for routing trains of constant length data packetsUS4665514 *Aug 2, 1985May 12, 1987American Telephone And Telegraph Company, At&T Bell LaboratoriesIntegrated voice/data network* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS4837761 *May 24, 1988Jun 6, 1989Fujitsu LimitedHeader driven type packet switching systemUS4872157 *Mar 31, 1988Oct 3, 1989American Telephone And Telegraph Company, At&T Bell LaboratoriesArchitecture and organization of a high performance metropolitan area telecommunications packet networkUS4890280 *Nov 14, 1988Dec 26, 1989Nec CorporationFrame relay type data switching apparatusUS4920531 *Feb 19, 1988Apr 24, 1990Fujitsu LimitedHeader driven packet switching system and methodUS4930122 *Jan 29, 1988May 29, 1990Hitachi, Ltd.Message transfer system and methodUS4947388 *Apr 5, 1989Aug 7, 1990Hitachi, Ltd.Cell switching system of asynchronous transfer modeUS4977556 *Jul 10, 1989Dec 11, 1990Nec CorporationPacket switching system for a distributed processing ISDN switchUS5016159 *Feb 18, 1987May 14, 1991Fuji Xerox Co., Ltd.Stellate store and broadcast network with collision avoidanceUS5022046 *Apr 14, 1989Jun 4, 1991The United States Of America As Represented By The Secretary Of The Air ForceNarrowband/wideband packet data communication systemUS5091905 *Nov 16, 1990Feb 25, 1992Hitachi, Ltd.High-speed packet switching using a space division optical switchUS5175765 *May 9, 1989Dec 29, 1992Digital Equipment CorporationRobust data broadcast over a distributed network with malicious failuresUS5235592 *Aug 13, 1991Aug 10, 1993International Business Machines CorporationDynamic switch protocols on a shared medium networkUS5249185 *Aug 5, 1991Sep 28, 1993Nippon Telephone And Telegraph CorporationVoice packet assembling/disassembling apparatusUS5341369 *Feb 11, 1992Aug 23, 1994Vitesse Semiconductor Corp.Multichannel self-routing packet switching network architectureUS5379293 *Mar 29, 1993Jan 3, 1995Kanno; ShinVoice packet assembling/disassembling apparatusUS5386415 *Nov 7, 1991Jan 31, 1995Hitachi, Ltd.Packet communiction method and packet communication apparatusUS5396490 *Mar 23, 1992Mar 7, 1995Motorola, Inc.Packet reassembly method and apparatusUS5440545 *Aug 2, 1993Aug 8, 1995Motorola, Inc.Packet delivery systemUS5455701 *Mar 28, 1994Oct 3, 1995At&T Corp.Packet switching apparatus using pipeline controllerUS5455865 *Dec 20, 1993Oct 3, 1995Digital Equipment CorporationRobust packet routing over a distributed network containing malicious failuresUS5467346 *Jun 28, 1994Nov 14, 1995Hitachi, Ltd.Packet communication method and packet communication apparatusUS5475681 *Jan 31, 1994Dec 12, 1995White; Richard E.Wireless in-building telecommunications system for voice and data communicationsUS5477541 *Dec 13, 1993Dec 19, 1995White; Richard E.Addressing technique for storing and referencing packet dataUS5495482 *Jun 21, 1991Feb 27, 1996Motorola Inc.Packet transmission system and method utilizing both a data bus and dedicated control linesUS5517500 *Jun 21, 1993May 14, 1996Motorola, Inc.Packet handling methodUS5517505 *Dec 13, 1993May 14, 1996Motorola, Inc.Synchronization method and apparatus for a wireless packet networkUS5524007 *Dec 13, 1993Jun 4, 1996Motorola, Inc.Network interface architecture for a packet switch communication systemUS5951654 *Oct 17, 1995Sep 14, 1999Telefonaktiebolaget Lm EricssonSystem for processing cooperation signals by storing and executing the control part of the signal separately from the data part using pointer to link the two partsUS6671286Apr 22, 1999Dec 30, 2003Nokia Mobile Phones, Ltd.Method and apparatus for indicating variable data processing in telecommunication connectionsUS6741597 *Apr 5, 2000May 25, 2004Lg Information & Communications, Ltd.Apparatus and method for managing traffic of an asynchronous transfer mode (ATM) switching systemUS7304999 *Aug 24, 2002Dec 4, 2007Cisco Technology Inc.Methods and apparatus for processing packets including distributing packets across multiple packet processing engines and gathering the processed packets from the processing enginesUS7404015Aug 24, 2002Jul 22, 2008Cisco Technology, Inc.Methods and apparatus for processing packets including accessing one or more resources shared among processing enginesUS7539750 *Mar 30, 2004May 26, 2009Extreme Networks, Inc.System and method for packet processor status monitoringUS7561589Jul 14, 2009Cisco Technology, IncVirtual address storage which may be of particular use in generating fragmented packetsUS7606250Oct 20, 2009Cisco Technology, Inc.Assigning resources to items such as processing contexts for processing packetsUS7664897Feb 16, 2010Cisco Technology Inc.Method and apparatus for communicating over a resource interconnectUS7739426Oct 31, 2006Jun 15, 2010Cisco Technology, Inc.Descriptor transfer logicUS7801140Sep 21, 2010Juniper Networks, Inc.In-line packet processingUS7804833 *Sep 28, 2010Juniper Networks, Inc.In-line packet processingUS7813264 *Oct 12, 2010Juniper Networks, Inc.High capacity router having redundant componentsUS7856543 *Dec 21, 2010Rambus Inc.Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction streamUS7917727 *Mar 29, 2011Rambus, Inc.Data processing architectures for packet handling using a SIMD arrayUS8077724Dec 13, 2011Juniper Networks, Inc.In-line packet processingUS8127112 *Dec 10, 2010Feb 28, 2012Rambus Inc.SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction streamUS8200686Jun 14, 2005Jun 12, 2012Rambus Inc.Lookup engineUS8514890 *Apr 23, 2012Aug 20, 2013International Business Machines CorporationMethod for switching traffic between virtual machinesUS8537860 *Nov 3, 2009Sep 17, 2013International Business Machines CorporationApparatus for switching traffic between virtual machinesUS8605732Feb 15, 2011Dec 10, 2013Extreme Networks, Inc.Method of providing virtual router functionalityUS8625427Sep 3, 2009Jan 7, 2014Brocade Communications Systems, Inc.Multi-path switching with edge-to-edge flow controlUS8649256Sep 3, 2010Feb 11, 2014Juniper Networks, Inc.High capacity router having redundant componentsUS8743882 *Apr 16, 2013Jun 3, 2014Marvell Israel (M.I.S.L) Ltd.Packet header altering deviceUS8867543Nov 11, 2011Oct 21, 2014Juniper Networks, Inc.In-line packet processingUS8913617Apr 14, 2014Dec 16, 2014Marvell Israel (M.I.S.L.) Ltd.Packet processor for altering a header portion of a data packetUS20030041163 *Feb 14, 2002Feb 27, 2003John RhoadesData processing architecturesUS20040037322 *Aug 24, 2002Feb 26, 2004Vitaly SukonikMethods and apparatus for processing packets including distributing packets across multiple packet processing engines and gathering the processed packets from the processing enginesUS20040039787 *Aug 24, 2002Feb 26, 2004Rami ZemachMethods and apparatus for processing packets including accessing one or more resources shared among processing enginesUS20050163044 *Mar 21, 2005Jul 28, 2005Anis HaqHigh capacity router having redundant componentsUS20050232303 *Apr 25, 2003Oct 20, 2005Koen DeforcheEfficient packet processing pipeline device and methodUS20050243827 *Jun 14, 2005Nov 3, 2005John RhoadesLookup engineUS20060209862 *Feb 23, 2005Sep 21, 2006Cisco Technology, Inc., A California CorporationVirtual address storage which may be of partcular use in generating fragmented packetsUS20070147257 *Mar 5, 2007Jun 28, 2007Juniper Networks, Inc.In-line packet processingUS20070217453 *May 23, 2007Sep 20, 2007John RhoadesData Processing ArchitecturesUS20080031252 *Aug 20, 2007Feb 7, 2008Oskouy Rasoul MIn-line packet processingUS20100309916 *Aug 13, 2010Dec 9, 2010Juniper Networks, Inc.In-line packet processingUS20110083000 *Dec 10, 2010Apr 7, 2011John RhoadesData processing architectures for packet handlingUS20110103220 *May 5, 2011Juniper Networks, Inc.High capacity router having redundant componentsUS20110103389 *Nov 3, 2009May 5, 2011Blade Network Technologies, Inc.Method and apparatus for switching traffic between virtual machinesCN1300714C *Mar 10, 2003Feb 14, 2007华为技术有限公司Externally hung memory optimizing managing method for data communication exchanging chipCN100450050CApr 25, 2003Jan 7, 2009美商传威股份有限公司Efficient packet processing pipeline device and methodEP1523829A2 *Apr 25, 2003Apr 20, 2005Transwitch CorporationEfficient packet processing pipeline device and methodEP2541851A1 *Jun 30, 2011Jan 2, 2013Astrium LimitedApparatus and method for use in a spacewire-based networkWO1993019544A1 *Mar 22, 1993Sep 30, 1993Motorola Inc.Packet reassembly method and apparatusWO1999056437A1 *Apr 27, 1999Nov 4, 1999Nokia Mobile Phones LimitedMethod and apparatus for indicating variable data processing in telecommunication connectionsWO2003091857A2 *Apr 25, 2003Nov 6, 2003Transwitch CorporationEfficient packet processing pipeline device and methodWO2003091857A3 *Apr 25, 2003Dec 11, 2003Transwitch CorpEfficient packet processing pipeline device and methodWO2013000851A2 *Jun 25, 2012Jan 3, 2013Astrium LimitedApparatus and method for use in a spacewire-based networkWO2013000851A3 *Jun 25, 2012Apr 4, 2013Astrium LimitedApparatus and method for use in a spacewire-based network* Cited by examinerClassifications U.S. Classification370/392International ClassificationH04L12/56Cooperative ClassificationH04L12/56, H04L49/9042, H04L49/90European ClassificationH04L49/90K, H04L49/90, H04L12/56Legal EventsDateCodeEventDescriptionSep 11, 1986ASAssignmentOwner name: NEC CORPORATION, 33-1, SHIBA 5-CHOME, MINATO-KU, TFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:HIRATA, HIDEYUKI;REEL/FRAME:004603/0350Effective date: 19860829Owner name: NEC CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HIRATA, HIDEYUKI;REEL/FRAME:004603/0350Effective date: 19860829Oct 31, 1991FPAYFee paymentYear of fee payment: 4Sep 27, 1995FPAYFee paymentYear of fee payment: 8Dec 29, 1999FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services