Source: http://www.google.com/patents/US8214575?dq=inventor:%22Arthur+R.+Hair%22&ei=VAy0Tsa4NYTl0QGQiqWiBA
Timestamp: 2015-03-31 03:56:12
Document Index: 673377308

Matched Legal Cases: ['Application No. 07114348', 'Application No. 07114627', 'Application No. 07114628', 'Application No. 07114348', 'Application No. 07114627', 'Application No. 07114628', 'Application No. 07114348', 'Application No. 07114627', 'Application No. 07114628', 'Application No. 98948454', 'Application No. 07114348', 'Application No. 07114627', 'Application No. 07114348', 'Application No. 07114348', 'Application No. 07114627', 'Application No. 07114348', 'Application No. 07114627', 'Application No. 07114348', 'Application No. 07114627']

Patent US8214575 - Memory module having signal lines configured for sequential arrival of ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger....http://www.google.com/patents/US8214575?utm_source=gb-gplus-sharePatent US8214575 - Memory module having signal lines configured for sequential arrival of signals at synchronous memory devicesAdvanced Patent SearchPublication numberUS8214575 B2Publication typeGrantApplication numberUS 12/975,313Publication dateJul 3, 2012Filing dateDec 21, 2010Priority dateSep 26, 1997Also published asEP1064699A1, EP1064699A4, EP1863130A2, EP1863130A3, EP1863131A2, EP1863131A3, EP1884953A2, EP1884953A3, US6067594, US6266730, US7085872, US7519757, US7523244, US7523246, US7523247, US7870322, US8364878, US20040221083, US20050246471, US20060277345, US20070150635, US20070150636, US20070156943, US20070216800, US20090210604, US20110090727, US20120144085, WO1999017404A1Publication number12975313, 975313, US 8214575 B2, US 8214575B2, US-B2-8214575, US8214575 B2, US8214575B2InventorsHaw-Jyh Liaw, David NguyenOriginal AssigneeRambus Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (99), Non-Patent Citations (41), Classifications (35) External Links: USPTO, USPTO Assignment, EspacenetMemory module having signal lines configured for sequential arrival of signals at synchronous memory devices
US 8214575 B2Abstract
A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.
a signal line that includes a first segment connected to a second segment via a first turn portion such that the first segment of the signal line and the second segment of the signal line are oriented in different directions, and wherein a data signal traverses the signal line starting at a first edge finger disposed on the substrate, then traverses the first segment of the signal line, then traverses the first turn portion, then traverses the second segment of the signal line, all before terminating at a first termination element;
a clock line that includes a first segment connected to a second segment via a second turn portion such that the first and second segments of the clock line are oriented in different directions the clock line to provide a clock signal that traverses the clock line starting at a second edge finger, then traverses the first segment of the clock line, then traverses the second turn portion, then traverses the second segment of the clock line, all before terminating at a second termination element; and
a plurality of memory devices disposed on the substrate, wherein each memory device of the plurality of memory devices is connected to the second segment of the signal line and second segment of the clock line such that the signal and clock signal traversing along the signal line and clock line, respectively, arrive at the plurality of memory devices in sequence.
2. The module of claim 1, further including a plurality of signal lines routed alongside the signal line such that each signal line of the plurality of signal lines includes, respectively, a first segment, turn portion, and second segment that are routed alongside the respective first segment, first turn portion, and second segment of the signal line.
3. The module of claim 1, wherein the first turn portion is a right angle turn portion, such that the first segment of the signal line is oriented perpendicular to the second segment of the signal line.
4. The module of claim 1, wherein the first turn portion comprises a via that is routed through a feedthrough hole in the substrate of the module.
5. The module of claim 1, wherein the substrate includes a first side and a second side, wherein the first side is positioned opposite to the second side, and wherein a first memory device of the plurality of memory devices is disposed on the first side of the substrate and a second memory device of the plurality of memory devices is disposed on the second side of the substrate.
6. The module of claim 1, wherein the module includes at least three signal layers, and wherein:
the first segment of the signal line is routed on the first side of the substrate, the first turn portion comprises a via that is routed through a first feedthrough hole in the substrate, and the second segment of the signal line is routed in an internal layer of the substrate; and
the first segment of the clock line is routed on the second side of the substrate, the second turn portion of the clock line comprises a via that is routed through a second feedthrough hole in the substrate, and the second segment of the clock line is routed in the internal layer of the substrate.
7. The module of claim 1, wherein the first segment of the signal line is disposed along a width of the substrate and the second segment of the signal line is disposed along a length of the substrate such that the length is oriented perpendicular to the width.
8. The module of claim 1, wherein a length of the signal line between the first edge finger and the first termination element is substantially equal to a length of the clock line between the second edge finger and the second termination element.
9. The module of claim 1, wherein the first segment of the signal line is routed substantially parallel to a first edge of the module and the second segment of the signal line is routed substantially parallel to a second edge of the module, wherein the second edge is longer than the first edge.
first and second edge fingers disposed at a first edge of the substrate;
a signal line that includes a first segment, first turn portion, second segment, second turn portion, and third segment such that a data signal traverses the signal line starting at the first edge finger, then traverses the first segment of the signal line, then traverses the first turn portion, then traverses the second segment of the signal line, then traverses the second turn portion, then traverses the third segment of the signal line;
a clock line to provide a clock signal that traverses the clock line starting at the second edge finger, then traverses a first segment of the clock line, then traverses a third turn portion, then traverses a second segment of the clock line, then traverses a fourth turn portion, and then traverses a third segment of the clock line; and
a plurality of memory devices disposed on the module, wherein each memory device of the plurality of memory devices is connected to the second segment of the signal line and second segment of the clock line such that the data signal and clock signal traversing along the signal line and clock line, respectively, arrive at each memory device of the plurality of memory devices in sequence.
12. The module of claim 10, wherein the first turn portion is a right angle turn portion, such that the first segment of the signal line is oriented perpendicular to the second segment of the signal line.
13. The module of claim 10, wherein each of the first and second turn portions are right angle turn portions, such that the first segment of the signal line is oriented perpendicular to the second segment of the signal line and the second segment is oriented perpendicular to the third segment of the signal line.
14. The module of claim 10, wherein each of the first and second turn portions comprise a respective via that is routed through a respective feed-through hole in the substrate of the module.
the first segment of the signal line is routed on a first side of the substrate, the first turn portion comprises a via that is routed through a first feed-through hole in the substrate, and the second segment of the first signal line is routed in an internal layer of the substrate, and
the first segment of the clock line is routed on the second side of the substrate, the second turn portion of the clock line comprises a via that is routed through a second feed-through hole in the substrate of the module, and the second segment of the clock line is routed on the internal layer of the substrate.
19. A method of operating a module, the method comprising:
traversing a signal starting at a first edge finger disposed on the substrate, then through a first segment of a signal line, then through a first turn portion, then through a second segment of the signal line before terminating at a first termination element;
traversing a clock signal alongside the signal starting at a second edge finger, then through a first segment of a clock line that is routed alongside the first segment of the signal line, then through a second turn portion, then through a second segment of the clock line that is routed alongside the second segment of the signal line before terminating at a second termination element; and
wherein each of the signal and clock signal traversing along the signal line and clock line, respectively, arrive at each memory device, of a plurality of memory devices, in sequence.
20. A method of operating a module, the method comprising:
traversing a signal starting at a first edge finger disposed on a substrate of the module, then through a first segment of a signal line, then through a first turn portion of the signal line, then through a second segment of the signal line, then through a second turn portion of the signal line, then through a third segment of the signal line; and
traversing a clock signal alongside the signal line starting at a second edge finger disposed on the substrate of the module, then through a first segment of a clock line that is routed alongside the first segment of the signal line, then through a first turn portion of the clock line, then through a second segment of the clock line that is routed alongside the second segment of the signal line, then through a second turn portion of the clock line, then through a third segment of the clock line that is routed alongside the third segment of the signal line;
a signal line that includes a first segment connected to a second segment via a first turn portion, such that the first segment and the second segment are oriented in different directions, and wherein a data signal traverses the signal line starting at the controller device, then traverses the first segment of the signal line, then traverses the first turn portion, then traverses the second segment of the signal line, all before terminating at a first termination element;
a clock line that includes a first segment connected to a second segment via a second turn portion such that the first and second segments of the clock line are oriented in different directions, and wherein a clock signal traverses the clock line starting at the controller device, then traverses a first segment of the clock line, then traverses a second turn portion, then traverses a second segment of the clock line, all before terminating at a second termination element; and
a plurality of memory devices, wherein each memory device of the plurality of memory devices is connected to the second segment of the signal line and second segment of the clock line such that the data signal and clock signal traversing along the signal line and clock line, respectively, arrive at each memory device of the plurality of memory devices in sequence.
22. The apparatus of claim 21, wherein the substrate is a motherboard comprising a socket, and wherein the plurality of memory devices are disposed on a module having a connector interface that is capable of being inserted into the socket.
23. The apparatus of claim 22, wherein the first segment of the signal line, turn portion, and second segment of the signal line are routed on the memory module.
24. The apparatus of claim 21, wherein the first turn portion is a right angle turn portion, such that the first segment of the signal line is oriented perpendicular to the second segment of the signal line.
25. The apparatus of claim 21, further including a plurality of signal lines routed alongside the signal line such that each signal line of the plurality of signal lines includes, respectively, a first segment, a turn portion, and a second segment that are routed alongside the respective first segment of the signal line, first turn portion, and second segment of the signal line.
This application is a continuation of U.S. application Ser. No. 12/426,083, filed Apr. 17, 2009, now U.S. Pat. No. 7,870,322 which is a continuation of U.S. patent application Ser. No. 11/459,858, filed Jul. 25, 2006, now U.S. Pat. No. 7,523,244, which is a continuation of U.S. patent application Ser. No. 09/839,768, filed Apr. 19, 2001, now U.S. Pat. No. 7,085,872, which is a continuation of U.S. patent application Ser. No. 09/507,303, filed Feb. 18, 2000, now U.S. Pat. No. 6,266,730, which is a continuation of U.S. patent application Ser. No. 08/938,084, filed Sep. 26, 1997, which is now U.S. Pat. No. 6,067,594, which applications are incorporated by reference herein in their entirety.
Z1′=Z1sqrt(C1/CT)whereCT=C1+CDL, where CDL is the device load.
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No. 12/426,083, includes Terminal Disclaimer, 10 pgs.41Websters II New Riverside University Dictionary, 1988, definition of "alongside."Classifications U.S. Classification710/305International ClassificationG06F13/00, H05K1/02, H05K1/14, G06F13/42, G06F13/40, H05K7/14, G11C5/00, G11C5/06Cooperative ClassificationH05K2201/10159, H05K1/023, H05K7/1459, G06F13/1684, H05K2201/10022, G06F13/4086, H05K1/0248, G06F13/409, H05K1/14, H05K2201/10689, G06F13/4247, H05K2201/044, G11C5/04, G11C7/1048, H05K1/0246, G11C5/063, H05K2201/09263European ClassificationG06F13/40E2T, G11C5/04, G06F13/42D, H05K1/02C4T, H05K7/14G7, H05K1/02C4R, G06F13/40E4, G06F13/16D6, G11C5/06HRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services