Source: http://www.google.com/patents/US20020022300?dq=6317900
Timestamp: 2016-02-07 18:29:44
Document Index: 417861478

Matched Legal Cases: ['art 70', 'art 70', 'art 70', 'art 110', 'art 70', 'art 70', 'art 70', 'art 40', 'art 110', 'art 70']

Patent US20020022300 - Method for fabricating a stacked semiconductor chip package - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA stacked semiconductor chip package includes: a substrate including a plurality of conductive pads; a first semiconductor chip mounted on the substrate; and electrically connected to the conductive pads; a plurality of electrical leads provided about the substrate; a first molding part for sealing the...http://www.google.com/patents/US20020022300?utm_source=gb-gplus-sharePatent US20020022300 - Method for fabricating a stacked semiconductor chip packageAdvanced Patent SearchPublication numberUS20020022300 A1Publication typeApplicationApplication numberUS 09/977,313Publication dateFeb 21, 2002Filing dateOct 16, 2001Priority dateOct 24, 1998Also published asUS6339255, US6500698Publication number09977313, 977313, US 2002/0022300 A1, US 2002/022300 A1, US 20020022300 A1, US 20020022300A1, US 2002022300 A1, US 2002022300A1, US-A1-20020022300, US-A1-2002022300, US2002/0022300A1, US2002/022300A1, US20020022300 A1, US20020022300A1, US2002022300 A1, US2002022300A1InventorsMyoung-Jin ShinOriginal AssigneeHyundai Electronics Industries Co., Ltd.Export CitationBiBTeX, EndNote, RefManReferenced by (10), Classifications (40), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod for fabricating a stacked semiconductor chip package
BRIEF DESCRIPTION OF THE DRAWINGS [0013] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. [0014] In the drawings: [0015] [0015]FIG. 1 a vertical cross-sectional diagram of a conventional small outline J-leaded (SOJ) semiconductor chip package; [0016] [0016]FIG. 2 is a vertical cross-sectional diagram of a semiconductor chip package according to a first embodiment of the present invention; [0017] FIGS. 3A-3G are vertical cross-sectional diagrams sequentially illustrating a method for fabricating the semiconductor chip package according the first embodiment of the present invention; [0018] [0018]FIG. 4 is a vertical cross-sectional diagram of a semiconductor chip package according to a second embodiment of the present invention; [0019] [0019]FIG. 5 is a vertical cross-sectional diagram of a semiconductor chip package according to a third embodiment of the present invention; and [0020] [0020]FIG. 6 is a vertical cross-sectional diagram of a semiconductor chip package according to a fourth embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION [0021] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. FIG. 2 illustrates a semiconductor chip package according to a first embodiment of the present invention. As shown therein, a substrate 10 is provided having circuit patterns (not shown) laid therein. A plurality of first conductive pads 20 are provided at both end sides on an upper surface of the substrate 10. A plurality of second conductive pads 30 which respectively correspond to the first conductive pads 20 are provided on a lower surface of the substrate 10. The first conductive pads 20 and the corresponding second conductive pads 30 are electrically interconnected to each other via the circuit patterns provided in the substrate 10. Further, a first semiconductor chip 40 which has a plurality of chip pads (not shown) is attached on the substrate 10 between the first conductive pads 20 provided on the both sides of the upper surface of the substrate 10. The chip pads of the first semiconductor chip 40 and the first conductive pads 20 are electrically connected by corresponding first conductive wires 50. In addition, leads 60 are attached at both end portions of the substrate 10. A first molding part 70 is formed in which the substrate 10, the first conductive pad 20, the second conductive pad 30, the first semiconductor chip 40 and the first conductive wires 50—except for the leads 60—are sealed by a molding epoxy resin 71. Here, surfaces of the first molding part 70 and each of the leads 60 have the same upper and lower surface levels. [0022] A second semiconductor chip 80 which has a plurality of chip pads (not shown) and is attached onto a center portion of an upper surface of the first molding part 70 by an adhesive 90. The chip pads of the second semiconductor chip 80 are electrically connected with end portions of corresponding chip connection leads 61 of the leads 60 by second conductive wires 100. Further, there is formed a second molding part 110 in which a predetermined portion of the first molding part 70, including the second semiconductor chip 80 and the second conductive wires 100, is sealed by a molding expoxy resin 111. [0023] In addition, each of the leads 60 includes a substrate connection lead 62 and the chip connection lead 61 which is upwardly bent therefrom, wherein each lead 60 is higher than a height from a bottom surface of the substrate 10 to the first conductive wires 50. [0024] FIGS. 3A-3G sequentially illustrate a method for fabricating the semiconductor chip package according the first embodiment of the present invention. [0025] First, as shown in FIG. 3A, the plurality of first conductive pads 20 are provided on the upper surface of the substrate 10. Corresponding to the first conductive pads 20, the plurality of second conductive pads 30 are provided on the bottom of the substrate 10. Conductive circuit patterns (not shown) are laid in the substrate 10. The first conductive pads 20 are connected with the corresponding second conductive pads 30 by the circuit patterns. [0026] As shown in FIG. 3B, first semiconductor chip 40 having a plurality of chip pads (not shown) is mounted among the first conductive pads 20 onto the substrate 10. The first conductive wires 50 electrically connect the chip pads of the first conductive chip 40 to the corresponding conductive pads 20. [0027] As can be seen in FIG. 3C, the plurality of leads 60 are attached to the both end portions of the semiconductor substrate 10, each lead 60 including substrate connection lead 62 and chip connection lead 61 which is upwardly bent therefrom. [0028] In FIG. 3D, the first molding part 70 is formed, in which predetermined portions, including the substrate 10, the substrate pads 20, 30, the first semiconductor chip 40 and the first conductive wires 50 (except for the leads 60), are sealed by the molding resin 71. Here, it is noted that an epoxy resin is generally used for the molding resin 71. After the molding process, bottoms of second conductive pads 30 are exposed, while upper and lower surfaces of the first molding part 70 and each lead 60 have the same surface level. [0029] As shown in FIG. 3E, the second semiconductor chip 80 having a plurality of chip pads (not shown) is attached onto the center portion of the upper surface of the first molding part 40 by a adhesive 90. [0030] In FIG. 3F, the chip pads of the second semiconductor chip 80 are electrically connected to the corresponding chip connection leads 61 of the leads 60 by corresponding second conductive wires 100. [0031] Lastly, as shown in FIG. 3G, second molding part 110 is formed in which the predetermined portions of the first molding part 70, including the second semiconductor chip 80, a portion of the upper surface of each chip connection lead 61 and the second conductive wires 100, are sealed by the molding resin 111. Here, the epoxy resin material is also used for the molding resin 111. [0032] The semiconductor chip package of the present invention may have other structures. [0033] More specifically, FIG. 4 illustrates a semiconductor chip package according to a second embodiment of the present invention. As shown therein, the only difference with FIG. 2 is the shape of the leads 60, and thus a detailed description of this embodiment will be omitted. [0034] Meanwhile, FIG. 5 illustrates a semiconductor chip package according to a third embodiment of the present invention. In this embodiment, a substrate 10 has an opening in a center thereof in the vertical direction. Side pads 11 are attached to inner walls of the opening whereby corresponding substrate pads 20, 30 are electrically connected (instead of laying circuit patterns in the substrate 10). Since the other aspects of the structure thereof are identical to that of FIG. 2, a more detailed description of this embodiment will be omitted as well (Refer to FIG. 2). [0035] In general, the semiconductor chip package according to the present invention and discussed hereinabove relates to two (or more) stacked semiconductor chips which are electrically independent from each other. For example, in FIG. 2, semiconductor chip 40 is electrically connected with an exterior of the package through conductive pads 20, 30 provided on substrate 10. In contrast, semiconductor chip 80 is electrically connected with an exterior of the package by being electrically connected to leads 60. This arrangement is suitable when each semiconductor chip receives different electrical signals. [0036] However, it is within the scope of the present invention to provide a stacked semiconductor chip package in which respective semiconductor chips are interconnected, such that each semiconductor chip receives the same electrical signal simultaneously. This may be accomplished in several ways in accordance with the present invention. For example, FIG. 6 is a cross-sectional view of a semiconductor chip package similar to that illustrated in FIG. 2. However, leads 60 are also electrically connected to conductive pads 20 by wires 51, in addition to being electrically connected to semiconductor chip 80. Other arrangements are possible to electrically interconnect semiconductor chips 40 and 80, including without limitation, electrically connecting semiconductor chip 40 to leads 60 directly with wires (i.e., without intervening conductive pads 20). [0037] As described above, the semiconductor chip package according to the present invention has an effect of maximizing memory capacity within a limited area by providing a plurality of semiconductor chips in the single stacked chip package. [0038] It will be apparent to those skilled in the art that various modifications and variations can be made in the semiconductor chip package and the fabrication method thereof of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7501696 *Jul 25, 2005Mar 10, 2009Shinko Electric Industries Co., Ltd.Semiconductor chip-embedded substrate and method of manufacturing sameUS7816769Oct 19, 2010Atmel CorporationStackable packages for three-dimensional packaging of semiconductor diceUS8102040 *Jan 24, 2012Stats Chippac Ltd.Integrated circuit package system with die and package combinationUS8278150Oct 2, 2012Atmel CorporationStackable packages for three-dimensional packaging of semiconductor diceUS20060022332 *Jul 25, 2005Feb 2, 2006Tetsuya KoyamaSemiconductor chip-embedded substrate and method of manufacturing sameUS20080048308 *Aug 28, 2006Feb 28, 2008Atmel CorporationStackable packages for three-dimensional packaging of semiconductor diceUS20090309207 *Aug 20, 2009Dec 17, 2009Seng Guan ChowIntegrated circuit package system with die and package combinationUS20110014747 *Sep 27, 2010Jan 20, 2011Atmel CorporationStackable packages for three-dimensional packaging of semiconductor diceUS20110089551 *Apr 21, 2011Oki Electric Industry Co., Ltd.Semiconductor device with double-sided electrode structure and its manufacturing methodEP1556895A2 *Oct 8, 2003Jul 27, 2005Chippac, Inc.Semiconductor stacked multi-package module having inverted second package* Cited by examinerClassifications U.S. Classification438/109, 257/E23.125, 257/E23.068, 257/E25.023International ClassificationH01L25/07, H01L25/18, H01L25/065, H01L23/00, H01L23/498, H01L25/10, H01L23/31Cooperative ClassificationH01L2924/00014, H01L2924/181, Y10T29/49172, Y10T29/49146, Y10T29/49121, H01L2924/07802, H01L24/48, H01L25/0657, H01L2225/0651, H01L2225/06551, H01L2924/19107, H01L2224/48247, H01L2924/01082, H01L2924/01004, H01L2224/4911, H01L2924/01006, H01L24/49, H01L23/3121, H01L2924/01033, H01L2224/48091, H01L2224/73265, H01L23/49811, H01L2224/48227, H01L2924/01005, H01L25/03European ClassificationH01L24/49, H01L25/10J, H01L23/31H2, H01L23/498CLegal EventsDateCodeEventDescriptionOct 16, 2001ASAssignmentJun 5, 2006FPAYFee paymentYear of fee payment: 4May 25, 2010FPAYFee paymentYear of fee payment: 8May 20, 2014FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services