Source: http://www.google.com/patents/US7576394?dq=6,108,703
Timestamp: 2016-10-22 16:28:32
Document Index: 551961017

Matched Legal Cases: ['Application No. 2006', 'arts 7', 'art 7', 'arts 7', 'arts 7', 'arts 18', 'arts 18', 'arts 18', 'arts 18']

Patent US7576394 - Thin film transistor including low resistance conductive thin films and ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain...http://www.google.com/patents/US7576394?utm_source=gb-gplus-sharePatent US7576394 - Thin film transistor including low resistance conductive thin films and manufacturing method thereofAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7576394 B2Publication typeGrantApplication numberUS 11/701,343Publication dateAug 18, 2009Filing dateFeb 1, 2007Priority dateFeb 2, 2006Fee statusPaidAlso published asCN101326644A, CN101326644B, EP1979948A2, EP1979948B1, US7981734, US20070187760, US20090269881, WO2007089048A2, WO2007089048A3Publication number11701343, 701343, US 7576394 B2, US 7576394B2, US-B2-7576394, US7576394 B2, US7576394B2InventorsMamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko YoshidaOriginal AssigneeKochi Industrial Promotion Center, Casio Computer Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (112), Classifications (18), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetThin film transistor including low resistance conductive thin films and manufacturing method thereof
US 7576394 B2Abstract
wherein a pair of side surfaces of the oxide semiconductor thin film layer and a corresponding pair of side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel, and a pair of outer ends of the oxide semiconductor thin film layer and a corresponding pair of outer ends of the low resistance conductive thin films coincide with each other along a channel length direction of the panel.
2. The thin film transistor according to claim 1, wherein a length of the oxide semiconductor thin film layer in the channel width direction is equal to or larger than a length of the source/drain electrodes in the channel width direction.
3. The thin film transistor according to claim 1, wherein the oxide semiconductor thin film layer primarily comprises zinc oxide.
4. The thin film transistor according to claim 3, wherein the low resistance conductive thin films are made of intrinsic zinc oxide, and the zinc oxide forming the low resistance conductive thin films has a crystal grain size that is larger than a crystal grain size of the zinc oxide forming the oxide semiconductor thin film layer.
5. The thin film transistor according to claim 1, wherein the source/drain electrodes are made of metal.
6. The thin film transistor according to claim 1, wherein each of the low resistance conductive thin films primarily comprises any one selected from a group consisting of indium tin oxide (ITO), zinc oxide doped with gallium (Ga), and zinc oxide doped with aluminum (Al)
7. The thin film transistor according to claim 1, further comprising:
a gate insulating film disposed over the oxide semiconductor thin film layer, the gate insulating film having a dual-layer structure comprising a lamination of a first gate insulating film that covers only an upper surface of the oxide semiconductor thin film layer and a second gate insulating film that covers an upper surface and side surfaces of the first gate insulating film and side surfaces of the oxide semiconductor thin film layer; and a gate electrode disposed over the gate insulating film.
8. The thin film transistor according to claim 1, further comprising:
a gate electrode disposed below the oxide semiconductor thin film layer; and
an overcoat insulating film disposed over the oxide semiconductor thin film layer, the overcoat insulating film having a dual-layer structure comprising a lamination of a first overcoat insulating film that covers only an upper surface of the oxide semiconductor thin film layer and a second overcoat insulating film that covers an upper surface and side surfaces of the first overcoat insulating film and side surfaces of the oxide semiconductor thin film layer.
9. The thin film transistor according to claim 1, further comprising a gate insulating film and a gate electrode provided on the oxide semiconductor thin film layer, the gate insulating film being formed of a compound containing silicon and oxygen.
10. The thin film transistor according to claim 1, further comprising an overcoat insulating film provided on the oxide semiconductor thin film layer, the overcoat insulating film being formed of a compound containing silicon and oxygen.
an oxide semiconductor thin film layer having a pair of side surfaces and a pair of outer ends;
a pair of low resistance conductive thin films defining a gap therebetween along an area corresponding to a channel of the thin film transistor, each of the low resistance conductive thin films having a pair of side surfaces and an outer end, each of the side surfaces being positioned so as to coincide with a corresponding one of the side surfaces of the oxide semiconductor thin film layer, and the outer end being positioned so as to coincide with a corresponding one of the outer ends of the oxide semiconductor thin film layer; and
a pair of source/drain electrodes, each having a pair of side surfaces, each of the side surfaces being one of positioned so as to coincide with and positioned inside of a corresponding one of the side surfaces of the low resistance conductive thin films.
12. The thin film transistor according to claim 11, further comprising a gate insulating film and a gate electrode provided on the oxide semiconductor thin film layer, the gate insulating film being formed of a compound containing silicon and oxygen.
13. The thin film transistor according to claim 11, further comprising an overcoat insulating film provided on the oxide semiconductor thin film layer, the overcoat insulating film being formed of a compound containing silicon and oxygen.
a pair of low resistance conductive thin films made of intrinsic zinc oxide, each coating at least a part of one of the source/drain electrodes, the low resistance conductive thin films defining a gap therebetween; and
an oxide semiconductor thin film layer primarily comprising zinc oxide, which is continuously formed on upper surfaces of the pair of low resistance conductive thin films, and which extends along the gap defined between the low resistance conductive thin films so as to function as a channel;
wherein side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel; and
wherein the zinc oxide forming the oxide semiconductor thin film layer has a crystal grain size that is smaller than a crystal grain size of the zinc oxide forming the low resistance conductive thin films.
an oxide semiconductor thin film layer primarily comprising zinc oxide having a pair of side surfaces;
a pair of low resistance conductive thin films defining a gap therebetween along an area corresponding to a channel of the thin film transistor, each of the low resistance conductive thin films having a pair of side surfaces, each of the side surfaces being positioned so as to coincide with a corresponding one of the side surfaces of the oxide semiconductor thin film layer, each of the low resistance conductive thin films being made of intrinsic zinc oxide, and the zinc oxide forming the low resistance conductive thin films having a crystal grain size that is larger than a crystal grain size of the zinc oxide forming the oxide semiconductor thin film layer; and
a pair of source/drain electrodes, each having a pair of side surfaces, each of the side surfaces being positioned so as to coincide with, and positioned inside of, a corresponding one of the side surfaces of the low resistance conductive thin films. Description
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-26320, filed on Feb. 2, 2006, the entire contents of which are incorporated herein by reference.
The present invention relates to a thin film transistor including low resistance conductive thin films and a manufacturing method thereof.
An oxide TFT including a semiconductor thin film layer made of zinc oxide or magnesium zinc oxide has greater electron mobility and better TFT characteristics than an amorphous silicon TFT including a semiconductor thin film layer of amorphous silicon (a-Si:H), which has been mainly used for liquid crystal displays. Another advantage of the oxide TFTs is that high electron mobility can be expected because a crystalline thin film is formed even at a temperature as low as a room temperature. These advantages have been encouraging the development of the oxide TFTs.
FIG. 9A shows a TFT 500 as one example of the TFTs provided according to the conventional method. The TFT 500 has a pair of low resistance conductive thin films 110 sandwiched between the oxide semiconductor thin film layer 103 and a pair of source/drain electrodes 102 placed on a substrate 101. Since the low resistance conductive thin films 110 have a lower resistance than the oxide semiconductor thin film layer 103, they improve the contact between each of the source/drain electrodes 102 and the oxide semiconductor thin film layer 103. The oxide semiconductor thin film layer 103 is disposed on the low resistance conductive thin films 110 and on an area of the substrate 101 exposed between the pair of low resistance conductive thin films 110, while the outer periphery 110 a (See FIG. 9B described below for a plan view) of the low resistance conductive thin films 110 remains uncovered. All the exposed surfaces of the oxide semiconductor thin film layer 103 are covered with a gate insulating film 104. A gate electrode 106 is disposed over the gate insulating film 104. FIG. 9B is a plan view of an array of the TFTs 500 shown in FIG. 9A. In FIG. 9B, two of the TFTs 500 are aligned in parallel. FIG. 9A is a cross sectional view along line IXA-IXA of FIG. 9B. For clarity, FIG. 9B omits gate insulating film 104 shown in FIG. 9A In manufacturing the TFT 500, first a pair of source/drain electrodes 102 is patterned and then the low resistance conductive thin film 110 is formed. The low resistance conductive thin film 110 is separated into a plurality of low resistance conductive thin films 110 that are spaced apart from each other, using a photo-lithography technique. Accordingly, an outer periphery 110 a (cross-hatched in FIG. 9B) of the low resistance conductive thin films 110 protrudes from the outer profile of the oxide semiconductor thin film layer 103. As shown in FIG. 9B, at least a distance D (distance D=width A+gap B+width A) is needed between the oxide semiconductor thin film layers of the TFTs. A narrower distance D is preferable in order to achieve higher integration of TFTs. The width A is defined by the mask-alignment accuracy of an aligner, in other words, by the alignment accuracy in the photo-lithography of the low resistance conductive thin film 110 and the oxide semiconductor thin film layer 103. The higher the alignment accuracy is, the smaller the width A becomes. On the other hand, the gap B is defined by the minimum resolution during the patterning of the low resistance conductive thin film 110. The higher the minimum resolution is, the smaller the gap B becomes. When a conventional aligner for an LCD is used, the width A determined by the alignment accuracy, is about 1.5 μm, and the gap B determined by the minimum resolution is about 4.0 μm. Therefore, in the conventional TFT 500, the distance D between the oxide semiconductor thin film layers 103 is approximately 7.0 μm (1.5 μm+4.0 μm+1.5 μm) (see FIG. 9B).
According to one aspect of the present invention, a thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.
The manufacturing method of the thin film transistor according to one aspect of the present invention includes forming a pair of source/drain electrodes on a substrate; forming low resistance conductive thin films, which are made of an oxide, on the source/drain electrodes; and forming an oxide semiconductor thin film layer, which functions as a channel, along the gap defined between the low resistance conductive thin films and on the upper surfaces of the low resistance conductive thin films. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.
FIGS. 1A to 1C show the thin film transistor of the first embodiment of the present invention. FIG. 1A is a cross-sectional view of the thin film transistor along line IA-IA in FIG. 1C; FIG. 1B is a plan view of the layout of the thin film transistor according to the first embodiment after forming source/drain electrodes and low resistance conductive thin films; and FIG. 1C is a plan view of the layout of the thin film transistor according to the first embodiment;
FIGS. 2A to 2D are cross-sectional views showing steps of the manufacturing method of the thin film transistor according to the first embodiment of the present invention. FIG. 2A is a cross-sectional view of the thin film transistor according to the first embodiment after forming the source/drain electrodes and the low resistance conductive thin films on the substrate; FIG. 2B is a cross-sectional view of the thin film transistor according to the first embodiment after coating the oxide semiconductor thin film layer; FIG. 2C is a cross-sectional view of the thin film transistor according to the first embodiment after performing etching; FIG. 2D is a cross-sectional view of the thin film transistor according to the first embodiment after laminating the gate insulating film and a gate electrode; and FIG. 2E is a cross-sectional view after laminating contact parts, external source/drain electrodes, and a display electrode;
FIG. 3 is a cross-sectional view of the thin film transistor according to the second embodiment of the present invention;
FIG. 5 is a cross-sectional view of the thin film transistor according to the third embodiment of the present invention;
FIG. 7 is a cross-sectional view of the thin film transistor according to the fourth embodiment of the present invention;
FIGS. 1A-1C are views of the TFT 100 according to the first embodiment of the present invention. FIG. 1A is a cross-sectional view along line IA-IA of FIG. 1C. FIG. 1B shows the TFTs 100 at a stage of manufacturing after formation of the source/drain electrodes and low resistance conductive thin films and before coating the TFTs 100 with an oxide semiconductor thin film layer. In FIG. 1B a plurality (two in the figure) of the TFTs 100 are aligned in parallel for integration. FIG. 1C is a plan view for describing the subsequent processes. Hereinafter, the first embodiment of the present invention will be described referring mainly to FIG. 1A, as well as FIG. 1B and FIG. 1C.
A thin film transistor 100 according to the first embodiment of the present invention includes a substrate 1, a pair of source/drain electrodes 2, a pair of low resistance conductive thin films 10, an oxide semiconductor thin film layer 3, a gate insulating film 4, a gate electrode 6, contact parts 7 a, a pair of external source/drain electrodes 2 a, and a display electrode 8, which are laminated in the order shown in FIG. 1A.
The oxide semiconductor thin film layer 3 covers the entire upper surfaces of each of the low resistance conductive thin films 10. At least side surfaces 10 a (see FIG. 1C) of the low resistance conductive thin films 10, extending in the channel length direction, are positioned coincident with the side surfaces of the oxide semiconductor thin film layer 3.
A specific comparison between the conventional TFT 500 (see FIG. 9) and the TFT 100 according to the first embodiment of the present invention is set forth below.
As mentioned above, the TFT 500 is fabricated by patterning the low resistance conductive thin films 110 on each TFT and then forming the oxide semiconductor thin film layers 103. Consequently, the distance (spacing) between the oxide semiconductor thin film layers 103 is defined as gap B+2�width A (here the gap B is the width of an area determined by the minimum resolution, and the width A is the width of an area determined by the alignment accuracy of the photolithography of the low resistance conductive thin film 110 and the oxide semiconductor thin film layer 103). As explained above with respect to FIG. 9B, when a conventional aligner for an LCD is used, the width A determined by the alignment accuracy, is about 1.5 μm, and the gap B determined by the minimum resolution is about 4.0 μm. Therefore, in the conventional TFT 500, the distance D between the oxide semiconductor thin film layers 103 is approximately 7.0 μm (1.5 μm+4.0 μm+1.5 μm) (see FIG. 9B).
On the other hand, in manufacturing the TFT 100 according to the present invention, the low resistance conductive thin films 10 are formed on multiple pairs of the source/drain electrodes 2 (two pairs in the example shown in FIG. 1B) of the TFTs 100 as shown in FIG. 1B. Then the oxide semiconductor thin film layer 3 is coated on the low resistance conductive thin films 10. The oxide semiconductor thin film layer 3 and the low resistance conductive thin films 10 are subsequently etched together in a self-aligning manner so that the side surfaces 10 a of the low resistance conductive thin films 10 have an identical shape to the side surfaces of the oxide semiconductor thin film layer 3, so that the side surfaces of the low resistance conductive thin films 10 and the oxide semiconductor thin film layer 3 are positioned coincident with each other. Therefore, although the width A, which is determined by the alignment accuracy, is necessary in the conventional TFT 500, the width A is not necessary in the TFT 100 of the present invention. The distance between the adjacent oxide semiconductor thin film layers 3 of the TFT 100 may be reduced to be equal to the gap B 4.0 μm, which is determined by the minimum resolution. Consequently, the TFT 100 according to the present invention enables nearly twice as high integration as the conventional TFT 500.
The gate insulating film 4 may be a silicon oxide (SiOx) film, a silicon oxide nitride (SiON) film, a silicon nitride (SiNx) film, or a silicon nitride (SiNx) film that is doped with oxygen using oxygen or a compound containing oxygen. Preferably, the gate insulating film 4 is formed by a silicon nitride (SiNx) film that is doped with oxygen using oxygen or compound (e.g. N2O) containing oxygen. Such a doped silicon nitride film has a higher dielectric constant than silicon oxide compounds (SiOx) or silicon oxide nitride (SiON). Therefore, if the TFT 100 has a gate insulating film 4 made of a SiNx film doped with oxygen, the gate insulating film has a high dielectric constant and an excellent protecting effect on the oxide semiconductor thin film layer 3.
Along the channel length direction, the outer ends 6 b of the gate electrode 6 are positioned outside the inner ends 10 c of the low resistance conductive thin films 10.
Each of the external source/drain electrodes 2 a is connected to the corresponding source/drain electrodes 2 via the contact part 7 a. The display electrode 8 is configured to apply a voltage to a liquid crystal in a liquid crystal display via the thin film transistor. The display electrode 8 is formed by a conductive oxide thin film such as an indium tin oxide (ITO) thin film and the like because it must have high transmittance with respect to visible light.
If the low resistance conductive thin film 10 is made of zinc oxide doped with gallium (Ga) or aluminum (Al) or intrinsic zinc oxide (ZnO) with no impurity introduced, gases such as CH4, CF4, CHF3, Cl2, or gas containing one of these gases and oxygen may be used in the dry etching. On the other hand, if the low resistance conductive thin film 10 is made of indium tin oxide (ITO), gases such as CH4 or mixture of CH4 and oxygen may be used.
For example, conventional reactive ion etching (RIE method) or inductively coupled plasma (ICP) etching may be used in the dry etching process of the present invention. The low resistance conductive thin films 10 and the oxide semiconductor thin film layer 3 are etched together. As a result, the outer ends 10 b of each of the low resistance conductive thin films 10 and the outer ends 3 b of the oxide semiconductor thin film layer 3 are positioned coincident with each other along the channel length direction, as shown in FIG. 2C. Also, the low resistance conductive thin films 10 and the oxide semiconductor thin film layer 3 are formed to have an identical shape in the channel width direction. The low resistance conductive thin films 10 and the oxide semiconductor thin film layer 3 are slightly longer than the source/drain electrodes 2, as shown in FIG. 1C.
FIG. 2C is a sectional view illustrating the lamination of the substrate 1, the source/drain electrodes 2, the low resistance conductive thin films 10, and the oxide semiconductor thin film layer 3 after performing dry etching as described above. In the manufacturing stage shown in FIG. 2C, etched surfaces (3 b and 10 b in FIG. 2C) must be formed outside the respective inner ends 2 c of the source/drain electrodes 2, along the channel length direction. The source/drain electrodes 2 subsequently serve as etching stoppers (since the source/drain electrodes 2 are made of metal, as described above) so that only the low resistance conductive thin films 10 and the oxide semiconductor thin film layers 3 are etched.
The gate insulating film 4 may be a 100 to 300 nm thick SiNx film created by means of a plasma-enhanced chemical vapor deposition (PCVD) under a condition, for example, where a substrate temperature is 250� C. and mixed gas containing NH3 and SiH4 is used at a flow rate ratio of 4 to 1.
As shown in FIG. 2D, a gate electrode 6 is disposed over the gate insulating film 4 so that both of the outer ends 6 b of the gate electrode 6 are positioned outside the respective inner ends 10 c of the low resistance conductive thin films 10.
As shown in FIG. 2E, contact holes are opened in the gate insulating film 4 to expose portions of the source/drain electrodes 2 by means of photolithography. The external source/drain electrodes 2 a are respectively connected to the source/drain electrodes 2 through the contact holes via contact parts 7 a. In the final step to form a TFT array, a display electrode 8 made of indium tin oxide (ITO) and the like is formed.
FIG. 3 is a cross-sectional view showing the structure of the thin film transistor 200 according to the second embodiment of the present invention. The TFT 200 according to the second embodiment has some similar structures to the TFT 100 according to the first embodiment. These structures are denoted by the same reference numerals. However, in place of the gate insulating film 4 of the TFT 100 according to the first embodiment, the TFT 200 according to the second embodiment includes a first gate insulating film and a second gate insulating film, which are denoted as the first gate insulating film 41 and the second gate insulating film 5.
The first gate insulating film 41 and the second gate insulating film 5 may be a silicon oxide (SiOx) film; a silicon oxide nitride (SiON) film; a silicon nitride (SiNx) film; or a silicon nitride (SiNx) film doped with oxygen using oxygen or a compound containing oxygen as a constituent element. Preferably, the first gate insulating film 41 and the second gate insulating film 5 are formed by a SiNx film doped with oxygen using oxygen or a compound (e.g. N2O) containing oxygen. Such a doped SiNx film has a higher dielectric constant than silicon oxide compounds (SiOx) or silicon oxide nitride (SiON).
The first gate insulating film 41 and the second gate insulating film 5 are formed by means of a plasma-enhanced chemical vapor deposition (PCVD) process. It is desirable to perform the film formation by the plasma-enhanced chemical vapor deposition (PCVD) process at a substrate temperature of 250� C. or below. In this temperature range, the reduction of the oxide semiconductor thin film layer or removal of oxygen and zinc does not occur.
FIG. 4C shows a cross-section of a lamination comprising the oxide semiconductor thin film layer 3, the low resistance conductive thin films 10, and the first gate insulating film 41 after etching and removing the photo-resist. Etched surfaces 3 b, etched surfaces 10 b, and etched surfaces 41 b of the layers are positioned coincident with each other. Consequently, sufficient step coverage is maintained and leakage current is suppressed, after a second gate insulating film 5 is formed.
The etched surfaces must be formed outside the respective inner ends 2 c of the source/drain electrodes 2 in the channel length direction. Thus, only the first gate insulating film 41, the low resistance conductive thin films 10 and the oxide semiconductor thin film layer 3 are etched.
A gate electrode 6 made of a metal film is formed on the second gate insulating film 5. After that, external source/drain electrodes 2 a are formed with the same material as the gate electrode 6. The external source/drain electrodes 2 a are connected to the source/drain electrodes 2 via contact parts 7 a. A display electrode 8 is formed in the final step to form a TFT array of the second embodiment of the present invention (see the TFT shown in FIG. 3).
Hereinafter, the thin film transistor according to the third embodiment of the present invention will be described with reference to FIG. 5.
FIG. 5 is a cross-sectional view showing the structure of a thin film transistor 300 according to the third embodiment of the present invention. The thin film transistor 300 includes a substrate 11, a gate electrode 12, a gate insulating film 13, source/drain electrodes 14, low resistance conductive thin films 20, an oxide semiconductor thin film layer 15, an overcoat insulating film 16, external source/drain electrodes 14 a, contact parts 18 a, and a display electrode 19. The TFT 300 is a bottom gate type TFT in which these layers are laminated in the order shown in FIG. 5.
The overcoat insulating film 16 is formed so as to cover the upper surface and side surfaces of the oxide semiconductor thin film layer 15. The external source/drain electrodes 14 a are formed so as to be connected to the source/drain electrodes 14 via the contact parts 18 a in the contact holes opened in the overcoat insulating film 16.
FIG. 6C is a cross-sectional view of the TFT 300 after performing dry etching. At this stage, etched surfaces 15 b of the oxide semiconductor thin film layer 15 and etched surfaces 20 b of the low resistance conductive thin films 20 must be located outside respective inner ends 14 c of the source/drain electrodes 14 in the channel length direction. The source/drain electrodes 14 subsequently serve as etching stoppers so that only the low resistance conductive thin films 20 and the oxide semiconductor thin film layer 15 are etched.
After forming the overcoat insulating film 16, external source/drain electrodes 14 a are formed. The external source/drain electrodes 14 a are connected to the source/drain electrodes 14 via contact parts 18 a. A display electrode 19 is formed in the final step to form a TFT array of the third embodiment of the present invention (see the TFT shown in FIG. 5).
FIG. 7 is a cross-sectional view showing the structure of the thin film transistor 400 according to the fourth embodiment of the present invention. The TFT 400 according to the fourth embodiment has some similar structures to the TFT 300 according to the third embodiment. These structures are denoted by the same reference numerals. However, in place of the overcoat insulating film 16 of the TFT 300 according to the third embodiment, TFT 400 according to the fourth embodiment includes a first overcoat insulating film and a second overcoat insulating film, which are denoted as the first overcoat insulating film 161 and the second overcoat insulating film 17.
FIG. 8C shows a cross-section of a lamination comprising the oxide semiconductor thin film layer 15, the low resistance conductive thin films 20, and the first overcoat insulating film 161 after etching and removing the photo-resist. Etched surfaces 15 b, etched surfaces 20 b, and etched surfaces 161 b of the above-mentioned layers are positioned coincident with each other. Consequently, sufficient step coverage is maintained after a second overcoat insulating film 17 is formed.
Then contact holes are opened in the first overcoat layer 17 to expose portions of the source/drain electrodes 14. External source/drain electrodes 14 a, which are connected to the source/drain electrodes 14 via contact parts 18 a, are formed. Then a display electrode 19 is formed in the final step to form a TFT array of the fourth embodiment of the present invention (See the TFT shown in FIG. 7).
As described above, the thin film transistor according to the present invention has excellent performance so that it is preferably used as an active element of a liquid crystal display device and the like.
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