Source: http://www.google.com/patents/US6181184?dq=7143430
Timestamp: 2016-12-08 02:37:38
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Patent US6181184 - Variable delay circuit and semiconductor intergrated circuit device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA variable delay circuit includes a load on a signal transfer line, at least one transistor connected to the signal transfer line. Each transistor is controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected...http://www.google.com/patents/US6181184?utm_source=gb-gplus-sharePatent US6181184 - Variable delay circuit and semiconductor intergrated circuit deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6181184 B1Publication typeGrantApplication numberUS 09/089,397Publication dateJan 30, 2001Filing dateJun 3, 1998Priority dateJul 29, 1997Fee statusPaidAlso published asDE69840007D1, DE69840468D1, EP0895355A2, EP0895355A3, EP0895355B1, EP1555755A2, EP1555755A3, EP1555755B1, US6304117, US6549047, US20020008560Publication number089397, 09089397, US 6181184 B1, US 6181184B1, US-B1-6181184, US6181184 B1, US6181184B1InventorsMasafumi Yamazaki, Hiroyoshi TomitaOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (10), Non-Patent Citations (1), Referenced by (29), Classifications (28), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetVariable delay circuit and semiconductor intergrated circuit device
US 6181184 B1Abstract
A variable delay circuit includes a load on a signal transfer line, at least one transistor connected to the signal transfer line. Each transistor is controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected thereto.
Referring to FIG. 2, a conventional DLL circuit 210 includes a variable delay circuit 212, a phase comparator circuit 215, and a delay control circuit 216. The variable delay circuit 212 delays an external clock signal received by an input circuit 211 by a given delay time, and outputs the delayed external clock signal to an output circuit 213. The phase comparator circuit 215 compares the phase of a reference signal “ref” supplied from the input circuit 211 with the phase of a signal “in” output by a dummy circuit 214. The signal output by the dummy circuit 214 has a delay time equal to the sum of the delay times of the input circuit 211, the variable delay circuit 212 and the output circuit 213 and the delay times of wiring lines provided between the input circuit 211 and the output circuit 213. The conventional DLL circuit 210 thus configured functions to delay the clock signal from the input circuit 211 with a precision of approximately 200 ps so that the output clock signal having a predetermined phase relationship with the clock signal from the input circuit 211.
A description will now be given, with reference to FIG. 3, of a phase setting process of the DLL circuit 210. In FIG. 3, a symbol “ref” denotes the reference signal output by the input circuit 211, and a symbol “in” denotes the signal output by the dummy circuit 214. The DLL circuit 210 delays the external clock received via the input circuit 211 by a given delay time through the variable delay circuit 212. The output circuit 213 receives the delayed clock signal from the variable delay circuit 212 and supplies a circuit of the following stage with the clock signal which has been pulled in phase with the external clock signal.
The dummy circuit 214 supplies the phase comparator circuit 215 with the signal “in” having the same delay time as that equal to the sum of the delay times of the input circuit 211, the variable delay circuit 212 and the output circuit 213 and the delay times of the wiring lines provided therebetween (step S101). The input circuit 211 outputs, as the reference signal “ref”, the external clock signal to the phase comparator circuit 215 (step S101). The phase comparator circuit 215 determines whether the signals “ref” and “in” are in phase (step S102). If the signals “ref” and “in” are out of phase, the relative phase relationship therebetween is determined (step S102).
If the signals “ref” and “in” are in phase (“just” at step S102), the delay control circuit 216 holds the current delay time of the variable delay circuit 212, and the phase comparator circuit 215 periodically performs the phase comparing operation.
If it is discerned, at step S102, that the signal “ref” from the input circuit 211 lags behind the signal “in” (“−1” at step S102), the phase comparator circuit 215 detects the phase difference therebetween. The delay control circuit 216 controls, based on the detected phase difference, the variable delay circuit 212 to reduce the delay time one stage by one stage (step S103). Then, the process returns to step S101 so that the steps S101 and S102 via step S103 are repeatedly carried out at predetermined intervals.
If it is discerned, at step S102, that the signal “in” from the dummy circuit 214 lags behind the signal “ref” (“+1” of step S102), the phase comparator circuit 215 detects the phase difference therebetween. The delay control circuit 216 controls, based on the detected phase difference, the variable delay circuit 212 to increase the delay time one stage by one stage (step S104). Then, the process returns to step S101 so that the steps S101 and S102 via step S104 are repeatedly carried out at predetermined intervals.
It is a general object of the present invention to provide a variable delay circuit in which the above disadvantage is eliminated.
Other objects, features and advantages of the present invention are achieved by the following detailed description when read in conjunction with the accompanying drawings, in which:
FIG. 4 is a circuit diagram of a variable delay circuit according to an embodiment of the present invention. The variable delay circuit shown in FIG. 4 is connected to a transfer path extending from an input terminal P1 to an output terminal P2, and includes a plurality of delay circuits connected in parallel with the transfer path. The circuit configuration shown in FIG. 4 includes five delay circuits 41, 42, 43, 44 and 45. The delay time of the variable delay circuit can be controlled by controlling the variable delay circuits 41-45. The number of stages of the variable delay circuit is not limited to five as shown in FIG. 4 but may be equal to an arbitrary number.
The second variable delay circuit 2 can be configured according to the present invention and may have the same configuration as that shown in FIG. 4. The second variable delay circuit 2 is capable of controlling the delay time with a comparatively high precision. The term “comparatively high precision” means that the second variable delay circuit 2 has a higher precision than that of the first variable delay circuit 1. The delay time of the second variable delay circuit 2 can be varied by changing the gate capacitance of the built-in transistor or transistors by controlling the gate voltage or voltages. The second variable delay circuit 2 may be replaced by any of the circuits shown in FIGS. 5, 6 and 7.
The first phase comparator circuit 5 compares, with a comparatively low precision, the phase of a reference signal “ref” obtained by dividing the frequency of the input clock signal with a given frequency dividing ratio in the frequency dividing circuit 10 with the phase of an output signal “in” from a dummy circuit 13, and detects a phase difference therebetween. The output signal “in” has a delay time equal to the sum of the delay times of the input circuit 15, the DLL circuit 16 and the output circuit 14.
The second phase comparator circuit 6 compares, with a comparatively high precision, the phase of the reference signal “ref” with the output signal “in”, and detects a phase difference therebetween.
The following operation is carried out at step S1 shown in FIG. 10. The frequency dividing circuit 10 outputs a clock signal 10 b obtained by dividing the frequency of the input clock signal to the first variable delay circuit 1 at the same time as the clock signal 10 a is output to the first variable delay circuit 1. Further, the frequency dividing circuit 10 supplies the first phase comparator circuit 5, the second phase comparator circuit 6 and the timing generating circuit 7 with a signal 10 c obtained by dividing the frequency of the input clock signal. The above signal 10 c serves as the reference signal “ref”. At the time of power on, the frequency dividing circuit 10 has a comparatively low frequency dividing ratio so that an increased number of times that the phase comparing operations are repeatedly carried out. Hence, it is possible to rapidly determine the initial delay times of the first and second variable delay circuits 1 and 2 at the time of power on.
Further, at step S1, the first variable delay circuit 1 delays the received clock signal 10 b by the sum of t1 and T as in the case of the clock signal 10 a, and outputs a resultant clock signal 1 b to the second variable delay circuit 2. The second variable delay circuit 2 delays the clock signal 1 b by the circuit delay time t2 as in the case of the clock signal 1 a, and outputs a resultant clock signal 2 b to the dummy circuit 13. The dummy circuit 13 delays the clock signal 2 b by the sum of the circuit delay times tin and tout of the input circuit 15 and output circuit 14, and outputs a resultant clock signal 13 a, which serves as the output signal “in”.
At step S2, the first phase comparator circuit 5 performs a comparatively “rough” phase comparing operation. More particularly, the first phase comparing circuit 5 compares the phase of the signal 10 c with the phase of the signal 13 a at the timing of the rising edge of the input clock signal. While the first phase comparator circuit 5 is performing the phase comparing operation and the number of stages in the first variable delay circuit 1 is being determined, the second phase comparing circuit 6 is in the disabled state in order to reduce power consumed therein.
The result of the phase comparing operation at step S2 shows that there is no phase difference between the signals 10 c and 13 a (“just” at step S2), the first phase comparing circuit 5 completes the phase comparing operation. Then, the second phase comparing circuit 6 starts a phase comparing operation on the signals 10 c and 13 a at step S7.
If the first phase comparing circuit 5 determines at step S2 that the signal 10 c leads to the signal 13 a (“+1” at step S2), it notifies, at the timing generated by the timing generating circuit 7, the first shift signal generating circuit 8 that the signal 10 c leads to the signal 13 a. Then, the first shift signal generating circuit 8 supplies the first delay control circuit 3 with an instruction which is based on the phase difference detected by the first phase comparing circuit 5 and causes the number of stages in the first variable delay circuit 1 to be increased by 1 at a given timing. At this given timing, the second variable delay circuit 2 outputs the rising edge of the input clock signal that is next the rising edge thereof at which the phase comparing operation was carried out at step S2. Hence, it is possible to prevent the number of stages in the first variable delay circuit 1 from being increased or decreased while the input clock signal is passing through the first and second variable delay circuits 1 and 2.
If the result of step S2 shows that the signal 13 a leads to the signal 10 c (“−1” at step S2), the first phase comparing circuit 5 notifies, at the timing generated by the timing generating circuit 7, the first shift signal generating circuit 8 that the signal 13 a leads to the signal 10 c. Then, the first shift signal generating circuit 8 supplies the first delay control circuit 3 with an instruction which is based on the phase difference detected by the first phase comparing circuit 5 and causes the number of stages in the first variable delay circuit 1 to be decreased by 1 at the given timing.
At the phase comparing operation of the first phase comparing circuit 5 at step S2 shown in FIG. 10, the first phase comparing circuit 5 makes a decision that the two signals are in phase (“just”) and there is no need to increase or decrease the delay time, if the timing (edge) of the signal 13 a with respect to that of the signal 10 c is located within the range from time T(r1) to time T(r2), as shown in FIG. 12B. If the timing of the signal 13 a with respect to that of the signal 10 c is delayed over the time T(r1), the first phase comparing circuit 5 makes a decision that the delay time should be increased (“+1”). If the timing of the signal 13 a with respect to that of the signal 10 c is advanced over the time T(r2), the first phase comparing circuit 5 makes a decision that the delay time should be decreased (“−1”).
In the above situation, if the signal 13 a has a phase difference with respect to the signal 10 c as shown in FIG. 12(A) in the case where the first phase comparing circuit 5 has a precision such that the in-phase decision period (T(r2)-T(r1)) is shorter than the delay time of one stage of the first variable delay circuit 1, the first delay control circuit 3 controls the first variable delay circuit 1 to increase the delay time by the time equal to one stage on the basis of the decision result “+1” provided by the first phase comparing circuit 5. However, at the next phase setting timing, the first delay control circuit 3 controls the first variable delay circuit 1 to decrease the delay time by the time equal to one stage on the basis of the decision result “−1” provided by the first phase comparing circuit 5. That is, if the first phase comparing circuit 5 has a precision so that the in-phase decision period is longer than the delay time of one stage of the first variable delay circuit 1, the delay time increasing and decreasing operations are alternatively executed indefinitely, so that the number of stages in the first variable delay circuit cannot be determined for ever.
If the result of step S7 shows that there is no phase difference between the signals 10 c and 13 a (“just” at step S7), the DLL circuit 16 ends the phase setting process, and the delay times thus obtained are set in the first and second variable delay circuits 1 and 2. Then, the first and second phase comparing circuits 5 and 6 wait for the next timing (step S1) for phase comparison. It should be noted that the DLL circuit 16 outputs the output clock signal having the given phase relationship with the input clock signal when it is determined that there is no phase difference on the signals 10 c and 13 a. If it is determined, at step S7, that the signal 10 c leads to the signal 13 a (“+1” at step S7), the timing generating circuit 7 determines, at step S8, whether the step-up process with a carry in the first variable delay circuit 1 occurs before increasing the number of stages in the second variable delay circuit 2 by one on the basis of the detection result output by the number-of-stages detection circuit 12. The number-of-stages detection circuit detects the current number of stages in the second variable delay circuit 2, and notifies the timing generating circuit 7 of the detected number of stages. In the decision made by the timing generating circuit 7, the step-up process occurs when the second phase comparing circuit 6 determines that the signal 10 c leads to the signal 13 a and the second variable delay circuit 2 is set so as to have a predetermined number of stages, for example, the maximum number thereof. In other cases, the step-up process does not occur.
The DLL circuit 16 sequentially executes steps S1, S2, S7-S9 so that the number of stages in the second variable delay circuit 2 is increased one by one until it is determined at step S2 that there is no phase difference between the signals 10 c and 13 a (“just”) and it is determined at step S7 that there is no phase difference between the signals 10 c and 13 a (“just”).
The DLL circuit 16 sequentially executes steps S1, S2, S7-S9 so that the number of stages in the second variable delay circuit 2 is reduced one by one until it is determined at step S2 that there is no phase difference between the signals 10 c and 13 a (“just”) and it is determined at step S7 that there is no phase difference between the signals 10 c and 13 a (“just”).
It will now be assumed that the delay time equal to one stage of the first variable delay circuit 1 and the delay time equal to one stage of the second variable delay circuit 2 are set therein, as shown in FIG. 13A. Further, it will be assumed that the first variable delay circuit 1 is set at the kth stage of the delay circuit, and the second variable delay circuit 2 is set at the zeroth stage (minimum stage) of the delay circuit. In this case, the external clock signal and the output clock signal are in phase. In the following description, the numbers of stages of the first and second variable delay circuits 1 and 2 are indicated by coordinates (a, b) where “a” denotes the number of stages in the first variable delay circuit 1, and “b” denotes the number of stages in the second variable delay circuit 2.
In the phase comparing operations at steps S2 and S7 shown in FIG. 10, the first and second phase comparator circuits 5 and 6 detect the phase differences between the signals 10 c and 13 a. As shown in FIG. 13B, the first and second phase comparator circuits 5 and 6 judge that the signals 10 c and 13 a are in phase (“just”) if the phase differences respectively detected fall within the range between T(f1) and T(f2). In this case, there is no need to increase or decrease the numbers of stages of the first and second phase comparator circuits 5 and 6.
If the phase difference detected by the first phase comparator circuit 5 falls within the range between T(r1) and T(r2) and the phase difference detected by the second phase comparator circuit 6 falls within T(f2) and T(r2), the second phase comparator circuit 6 judges the phase difference as “−1” so that the number of stages in the second variable delay circuit 2 is decreased by one.
If the phase difference detected by the first phase comparator circuit 5 falls within the range between T(r1) and T(r2) and the phase difference detected by the second phase comparator circuit 6 falls within the range between T(r1) and T(f1), the second phase comparator circuit 6 judges the phase difference as “+1”, so that the number of stages in the second variable delay circuit 2 is increased by one.
If the phase difference detected by the first phase comparator circuit 5 exceeds T(r2), the first phase comparator circuit 5 judges the phase difference as “−1”, so that the number of stages in the first variable delay circuit 1 is decreased by one.
If the phase difference detected by the first phase comparator circuit 5 is less than T(r1), the first phase comparator circuit 5 judges the phase difference as “+1”, so that the number of stages in the first variable delay circuit 1 is increased by one.
If the signal 13 a has a phase difference {circle around (1)} (FIG. 13A) with respect to the signal 10 c, the result of step S2 executed by the first phase comparator circuit 5 is “just”, and the result of step S7 executed by the second phase comparator circuit 6 is “+1”. Then, the DLL circuit 16 repeatedly performs the phase setting process shown in FIG. 10 three times. The first and second delay control circuits 3 and 4 controls the first and second variable delay circuits 1 and 2 to change the respective numbers of stages from (k, 0) to (k, 3). Hence, the numbers of stages of the first and second variable delay circuits 1 and 2 are changed as (k, 0)→(k, 1)→(k, 2)→(k, 3).
If the signal 13 a has a phase difference {circle around (2)} (FIG. 13A) with respect to the signal 10 c, the result of step S2 is “+1”, the first delay control circuit 3 controls the first variable delay circuit 1 to change the number of stages from (k, 0) to (k+1, 0). The next result of step S2 will show “just”, while the result of step S7 executed by the second phase comparator circuit 6 is “−1”. Since the judgment of the phase comparing process by the second phase comparator circuit 6 is “−1” and the number of stages in the second variable delay circuit 3 is zero (minimum number), the step-down process occurs, so that the first and second delay control circuits 3 and 4 control the first and second variable delay circuits 1 and 2 to change the respective numbers of stages from (k+1, 0) to (k, 6). Further, the DLL circuit 16 repeatedly carries out the phase setting process shown in FIG. 10 twice. Thus, the first and second delay control circuits 3 and 4 control the first and second variable delay circuits 1 and 2 to change the respective numbers of stages from (k, 6) to (k, 4). Hence, the numbers of stages in the first and second variable delay circuits 1 and 2 are changed as (k, 0)→(k+1, 0)→(k, 6)→(k, 5)→(k, 4).
At step S21, the frequency dividing circuit 18 supplies, at the same time as the clock signal 10 a is output, the first variable delay circuit 1 with the clock signal 10 b obtained by dividing the frequency of the input clock signal according to instructions from the frequency dividing control circuit 17. Further, the frequency dividing circuit 18 supplies the first phase comparator circuit 5, the second phase comparator circuit 6, the timing generating circuit 7 and the frequency dividing control circuit 17 with the signal 10 c generated by dividing the frequency of the input clock signal in accordance with instructions from the frequency dividing control circuit 17. At the time of power on, the frequency dividing circuit 18 is set, in accordance with the instructions from the frequency dividing control circuit 17, to a comparatively low frequency dividing ratio so as to increase the number of times that the phase comparing operation are repeatedly carried out (“short period” at step S21). With the comparatively low frequency dividing ratio, the phases can be set at a high speed at step S22 (hereinafter the above setting will be referred to as a short-period mode).
If the frequency dividing control circuit 17 judges that there is no need to increase or decrease the delay times of the first and second variable delay circuits 1 and 2, the circuit 17 instructs the frequency dividing circuit 18 to increase the frequency dividing ratio so that the number of times for phase comparison can be reduced (“long period” at step S21). With the comparatively high frequency dividing ratio, the number of times that the phase comparing operations are repeatedly carried out is reduced and a reduced amount of power is consumed in a reduced power mode (hereinafter the above setting will be referred to as a long-period mode).
At step S14, the first variable delay circuit 1 delays the received clock signal 10 b by the sum of t1 and T as in the case of the clock signal 10 a, and outputs the resultant clock signal 1 b to the second variable delay circuit 2. The second variable delay circuit 2 delays the clock signal 1 b by the circuit delay time t2 as in the case of the clock signal 1 a, and outputs the resultant clock signal 2 b to the dummy circuit 13. The dummy circuit 13 delays the clock signal 2 b by the sum of the circuit delay times tin and tout of the input circuit 15 and output circuit 14, and outputs the resultant clock signal 13 a, which serves as the output signal “in”.
The result of the phase comparing operation at step S25 shows that there is no phase difference between the signals 10 c and 13 a (“just” at step S25), the first phase comparing circuit 5 completes the phase comparing operation. Then, the second phase comparing circuit 6 executes the phase comparing operation on the signals 10 c and 13 a at step S32.
If the first phase comparing circuit 5 determines at step S25 that the signal 10 c leads to the signal 13 a (“+1”), it notifies, at the timing generated by the timing generating circuit 7, the first shift signal generating circuit 8 that the signal 10 c leads to the signal 13 a. Then, the first shift signal generating circuit 8 supplies the first delay control circuit 3 with the instruction which is based on the phase difference detected by the first phase comparing circuit 5 and causes the number of stages in the first variable delay circuit 1 to be increased by 1 at a given timing. At this given timing, the second variable delay circuit 2 outputs the rising edge of the input clock signal that is next the rising edge thereof at which the phase comparing operation was carried out at step S25. Hence, it is possible to prevent the number of stages in the first variable delay circuit 1 from being increased or decreased while the input clock signal is passing through the first and second variable delay circuits 1 and 2.
If the result of step S25 shows that the signal 13 a leads to the signal 10 c (“−1”), the first phase comparing circuit 5 notifies, at the timing generated by the timing generating circuit 7, the first shift signal generating circuit 8 that the signal 13 a leads to the signal 10 c. Then, the first shift signal generating circuit 8 supplies the first delay control circuit 3 with the instruction which is based on the phase difference detected by the first phase comparing circuit 5 and causes the number of stages in the first variable delay circuit 1 to be decreased by 1 at the given timing.
If the result of step S32 shows that there is no phase difference between the signals 10 c and 13 a (“just”), the DLL circuit 19 ends the phase setting process, and the delay times thus obtained are set in the first and second variable delay circuits 1 and 2. Then, the frequency dividing circuit 17 sets the frequency dividing circuit 18 to the long-period mode at step S33. Then, the first and second phase comparing circuits 5 and 6 wait for the next timing for phase comparison. It should be noted that the DLL circuit 19 outputs the output clock signal having the given phase relationship with the input clock signal when it is determined that there is no phase difference on the signals 10 c and 13 a. If it is determined, at step S32, that the signal 10 c leads to the signal 13 a (“+1”), the timing generating circuit 7 determines, at step S34, whether the step-up process with a carry in the first variable delay circuit 1 occurs before increasing the number of stages in the second variable delay circuit 2 by one on the basis of the detection result output by the number-of-stages detection circuit 12. The number-of-stages detection circuit 12 detects the current number of stages in the second variable delay circuit 2, and notifies the timing generating circuit 7 of the detected number of stages. In the decision made by the timing generating circuit 7, the step-up process occurs when the second phase comparing circuit 6 determines that the signal 10 c leads to the signal 13 a and the second variable delay circuit 2 is set so as to have a predetermined number of stages, for example, the maximum number thereof. In other cases, the step-up process does not occur.
The DLL circuit 19 sequentially executes steps S21-S25 and S32-S35 so that the number of stages in the second variable delay circuit 2 is increased one by one until it is determined at step S25 that there is no phase difference between the signals 10 c and 13 a (“just”) and it is determined at step S32 that there is no phase difference between the signals 10 c and 13 a (“just”).
The DLL circuit 19 sequentially executes steps S21-S25, S32, S34 and S35 so that the number of stages in the second variable delay circuit 2 is reduced one by one until it is determined at step S25 that there is no phase difference between the signals 10 c and 13 a (“just”) and it is determined at step S32 that there is no phase difference between the signals 10 c and 13 a (“just”).
The DLL circuit 19 sequentially executes steps S21-S25, S32, S38 and S39 so that the number of stages in the second variable delay circuit 2 is increased one by one until it is determined at step S2 that there is no phase difference between the signals 10 c and 13 a (“just”) and it is determined at step S7 that there is no phase difference between the signals 10 c and 13 a (“just”).
The DLL circuit 19 sequentially executes steps S21-S25, S32, S38 and S39 so that the number of stages in the second variable delay circuit 2 is reduced one by one until it is determined at step S25 that there is no phase difference between the signals 10 c and 13 a (“just”) and it is determined at step S32 that there is no phase difference between the signals 10 c and 13 a (“just”).
The external clock signal is delayed by tin in the input buffer 33 and is applied to the frequency divider 34. Then, the frequency divider 34 outputs the signal 34 b to the first delay part 21 and outputs, as the reference signal “ref”, the clock signal 34 a to the first phase comparator part 25, the second comparator part 26 and the timing generating part 27 (step S1 shown in FIG. 10). At the time of power on, the frequency divider 34 is set so as to have a comparatively small frequency dividing ratio in order to increase the number of times for phase comparison. Hence, the first and second delay parts 21 and 22 can be set to the initial values at a high speed.
The first delay part 21 delays the signal 34 b by the sum of t1 and T and thus outputs a resultant signal 21 b. The second delay part 22 receives the signal 21 b, which is delayed by t2 therein. Then, a resultant signal 22 b is output to the dummy delay part 36, which delays the signal 22 b by the sum of tin, tout and p, and outputs the signal 36 a (“in”) to be compared with the reference signal 34 a (step S1).
A description will be given, with reference to FIGS. 16 and 17, of a case where the first phase comparator part 25 judges that there is no phase difference between the signals 36 a and 34 a (“just” at step S2).
A description will be given, with reference to FIGS. 16 and 18, of a case where the first phase comparator part 25 judges that the signal 34 a leads to the signal 36 a (“+1” at step S2).
The first phase comparator part 25 receives the signals 34 a and 36 a at step S1 and performs the phase comparing operation thereon at step S2 at the next timing for comparison defined by the frequency divider 34. The first phase comparator part 25 repeatedly executes the process of the steps S1 to S4 until it is judged that there is no phase difference between the signals 34 a and 36 a. When it is judged that there is no phase different (“just” at step S2), the phase comparing process is ended, and instead the second phase comparator part 26 initiates the phase comparing operation on the signals 34 a and 36 a (step S7).
A description will be given, with reference to FIGS. 16 and 19 of a case where it is judged that the signal 36 a leads to the signal 34 a by the first phase comparator circuit 25 (“−1” at step S2).
The first phase comparator part 25 receives the signals 34 a and 36 a at step S1 and performs the phase comparing operation thereon at step S2 at the next timing for comparison defined by the frequency divider 34. The first phase comparator part 25 repeatedly executes the process of the steps S1, S2, S5 and S6 until it is judged that there is no phase difference between the signals 34 a and 36 a. When it is judged that there is no phase different (“just” at step S2), the phase comparing process is ended, and instead the second phase comparator part 26 executes the phase comparing operation on the signals 34 a and 36 a (step S7).
A description will be given, with reference to FIGS. 16 and 20, of a case where the second phase comparator part 26 judges that there is no phase difference between the signals 34 a and 36 a (“just” at step S7).
If the second phase comparing part 26 judges that the signal 34 a leads to the signal 36 a (“+1” at step S7), the second phase comparator part 26 supplies, at the timing of the signal 27 c, the second shift signal generating circuit 30 with the signals 26 a-26 d indicating that the signal 34 a leads to signal 36 a. Further, the second shift signal generating part 30 sets the signal 26 f to the low level, which is applied to the timing generating circuit 27, and sets the signal 26 e to the high level (the delay time is too short), which is applied to the phase control part 28. Then, the phase control part 28 determines whether the step-up process occurs (step S8). The step-up process occurs when the signal 31 a indicates the maximum number n of stages in the second delay part 22 and the signal 26 e shows that the delay time is too short.
The first and second phase comparator parts 25 and 26 receive the signals 34 a and 36 a at step S1. Then, the first phase comparator part 25 perform the phase comparing operation on the received signals at step S2 at the next timing for comparison defined by the frequency divider 34. The steps S1, S2 and S7-S9 are repeatedly executed. The number of stages in the second delay part 22 is increased one by one until it is judged that there is no phase difference between the signals 34 a and 36 a by the first and second phase comparator parts 25 and 26 (“just” at step S7).
The first and second phase comparator parts 25 and 26 receive the signals 34 a and 36 a at step S1. Then, the first phase comparator part 25 performs the phase comparing operation on the received signals at step S2 at the next timing for comparison defined by the frequency divider 34. The steps S1, S2 and S7-S9 are repeatedly executed. The number of stages in the second delay part 22 is increased one by one until it is judged that there is no phase difference between the signals 34 a and 36 a by the first and second phase comparator parts 25 and 26 (“just” at step S7).
If the second phase comparing part 26 judges that the signal 36 a leads to the signal 34 a (“−1” at step S7), the second phase comparator part 26 supplies, at the timing of the signal 27 c, the second shift signal generating part 30 with the signals 26 a-26 d indicating that the signal 36 a leads to signal 34 a. Further, the second shift signal generating part 30 sets the signal 26 f to the low level, which is applied to the timing generating circuit 27, and sets the signal 26 e to the high level (the delay time is too long), which is applied to the phase control part 28. Then, the phase control part 28 determines whether the step-down process occurs (step S12). The step-down process occurs when the signal 31 a indicates the minimum number (zero) of stages in the second delay part 22 and the signal 26 e shows that the delay time is too long. In this case, the step-down process does not occur because the signal 31 a does not indicate the minimum number of stages although the signal 26 e indicates that the delay time is too long.
The first and second phase comparator parts 25 and 26 receive the signals 34 a and 36 a at step S1. Then, the first phase comparator part 25 performs the phase comparing operation on the received signals at step S2 at the next timing for comparison defined by the frequency divider 34. The sequence of the steps S1, S2, S7, S12 and S13 is repeatedly executed. The number of stages in the second delay part 22 is decreased one by one until it is judged that there is no phase difference between the signals 34 a and 36 a by the first and second phase comparator parts 25 and 26 (“just” at step S7).
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