Source: https://patents.google.com/patent/US6072945A/en
Timestamp: 2020-07-04 04:54:04
Document Index: 666784284

Matched Legal Cases: ['Application No. 5', 'Application No. 5', 'Application No. 6', 'Application No. 5', 'Application No. 5', 'Application No. 6']

US6072945A - System for automated electromigration verification - Google Patents
System for automated electromigration verification Download PDF
US6072945A
US6072945A US08/883,547 US88354797A US6072945A US 6072945 A US6072945 A US 6072945A US 88354797 A US88354797 A US 88354797A US 6072945 A US6072945 A US 6072945A
US08/883,547
Sandeep A. Aji
1997-06-26 Priority to US08/883,547 priority Critical patent/US6072945A/en
1998-03-10 Assigned to SUN MICROSYSTEMS, INC. reassignment SUN MICROSYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AJI, SANDEEP, DORESWAMY, MANJUNATH, KONSTADINIDIS, GEORGIOS
2000-06-06 Publication of US6072945A publication Critical patent/US6072945A/en
1. An apparatus for automatically detecting electromigration violations in an integrated circuit design, the integrated circuit design having a functional hierarchy including a plurality of top-most level functional blocks each containing a plurality of functional cells, a plurality of external networks each interconnecting two or more of the top-most level functional blocks and together with the interconnected top-most level functional blocks forming a plurality of top-level nets, and further including a plurality of internal networks each contained within a respective one of the top-most level functional blocks and each interconnecting two or more functional cells within the respective one top-most level functional block, each of the external and internal networks including conductive signal traces and each of the functional cells having a drive strength associated therewith, said apparatus comprising:
a layout file containing layout information for the integrated circuit design;
a rules table containing electromigration process rules for conductive signal traces of the integrated circuit design; and,
processing means for propagating upward within the functional hierarchy parasitic resistance and capacitance values of conductive signal traces of the integrated circuit design; for determining a lumped resistance a lumped capacitance and a lumped drive strength of each of the top-most level functional blocks; for determining a lumped resistance and lumped capacitance of each external network; for calculating at least one current value for each top-level net from the lumped resistance, the lumped capacitance and the lumped drive strength of the external networks and the top-most level functional blocks; for determining minimum electromigration dimensions for the conductive signal traces of the integrated circuit design based on the at least one current value for each of the top-most level nets, indexed to said rules table; for determining design dimensions of the conductive signal traces of the integrated circuit design; for comparing the design dimensions with the minimum electromigration dimensions; and for identifying violations of the fabrication process rules for the conductive signal traces of the integrated circuit design when the design dimensions are less than the minimum electromigration dimensions.
2. A apparatus as claimed in claim 1, wherein the at least one current value indicates a peak current, and average current and an rms current of each top-level net.
US08/883,547 1997-06-26 1997-06-26 System for automated electromigration verification Expired - Fee Related US6072945A (en)
US08/883,547 US6072945A (en) 1997-06-26 1997-06-26 System for automated electromigration verification
US6072945A true US6072945A (en) 2000-06-06
ID=25382805
US08/883,547 Expired - Fee Related US6072945A (en) 1997-06-26 1997-06-26 System for automated electromigration verification
US (1) US6072945A (en)
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US6954914B2 (en) * 2003-03-24 2005-10-11 Sun Microsystems, Inc. Method and apparatus for signal electromigration analysis
US8042080B2 (en) 2006-08-01 2011-10-18 Panasonic Corporation Electro-migration verifying apparatus, electro-migration verifying method, data structure and netlist used in the same
US10312189B2 (en) 2015-11-16 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Enhancing integrated circuit density with active atomic reservoir
US7971171B2 (en) 2011-06-28 Method and system for electromigration analysis on signal wiring
US6857113B2 (en) 2005-02-15 Process and system for identifying wires at risk of electromigration
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AJI, SANDEEP;DORESWAMY, MANJUNATH;KONSTADINIDIS, GEORGIOS;REEL/FRAME:009034/0916