Source: http://www.google.com/patents/US8094510?dq=5166694
Timestamp: 2014-09-19 02:00:02
Document Index: 316439751

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US8094510 - Memory array incorporating noise detection line - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates...http://www.google.com/patents/US8094510?utm_source=gb-gplus-sharePatent US8094510 - Memory array incorporating noise detection lineAdvanced Patent SearchPublication numberUS8094510 B2Publication typeGrantApplication numberUS 12/847,378Publication dateJan 10, 2012Filing dateJul 30, 2010Priority dateMar 21, 2001Also published asUS6937495, US7177181, US7505344, US7773443, US20030021148, US20030026120, US20090175094, US20100290301Publication number12847378, 847378, US 8094510 B2, US 8094510B2, US-B2-8094510, US8094510 B2, US8094510B2InventorsRoy E. ScheuerleinOriginal AssigneeSandisk 3D LlcExport CitationBiBTeX, EndNote, RefManPatent Citations (51), Non-Patent Citations (23), Classifications (25) External Links: USPTO, USPTO Assignment, EspacenetMemory array incorporating noise detection lineUS 8094510 B2Abstract A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.
a multi-level memory array of memory cells having at least one layer of word lines and more than one layer of bit lines, each layer of bit lines includes a bit line group;
at least one noise detection line associated with each layer of bit lines;
a selection circuit that selects a selected bit line associated with a particular bit line group, and a selected noise detection line associated with said particular bit line group; and
a bit line sensing circuit, said bit line sensing circuit senses a signal on said selected bit line and a signal on said selected noise detection line, said bit line sensing circuit includes a voltage sensing circuit;
said voltage sensing circuit includes a first precharge circuit for precharging said selected noise detection line to an unselected word line bias voltage; and
a second precharge circuit for precharging said selected bit line to a voltage other than the unselected word line bias voltage.
a bit line sensing circuit, said bit line sensing circuit senses a signal on said selected bit line and a signal on said selected noise detection line;
wherein alternating bit lines on a bit line layer form a first group and are associated with a selection circuit and sensing circuit disposed to one side of the array, and remaining bit lines on the layer form a second group and are associated with a selection circuit and sensing circuit disposed to a side of the array opposite the one side.
3. The integrated circuit according to claim 2, wherein said selected noise detection line associated with said particular bit line group is arranged on the same layer of bit lines as said particular bit line group.
4. The integrated circuit according to claim 2, wherein said selected noise detection line is arranged so that memory cells coupled respectively thereto are substantially non-conductive.
5. The integrated circuit according to claim 2, wherein said bit line sensing circuit includes a voltage sensing circuit.
6. The integrated circuit according to claim 2, wherein a second noise detection line is associated with said particular bit line group, said second noise detection line is arranged so that a subset of the memory cells coupled respectively thereto are substantially conductive.
7. The integrated circuit of claim 2, wherein memory cells coupled to each noise detection line remain unprogrammed.
8. The integrated circuit of claim 2, wherein said selection circuit is arranged so that a particular selected bit line on a bit line layer is never adjacent to a particular selected noise detection line on the same bit line layer.
9. The integrated circuit of claim 2, wherein said selection circuit is arranged so that a particular selected bit line on a bit line layer is never adjacent to another selected bit line on the same bit line layer at the same time.
10. The integrated circuit of claim 2, wherein each respective bit line group on a bit line layer is associated with a respective noise detection line.
11. The integrated circuit of claim 2, further comprising more than one selection circuit associated with each bit line group.
12. The integrated circuit of claim 2, wherein said multi-level memory array is arranged with a word line layer as the bottom-most layer of the memory array.
13. The integrated circuit of claim 2, wherein more than one noise detection line is associated with each selection circuit and sensing circuit.
14. The integrated circuit according to claim 1, wherein said selected noise detection line is arranged so that memory cells coupled respectively thereto are substantially non-conductive.
15. The integrated circuit according to claim 1, wherein a second noise detection line is associated with said particular bit line group, said second noise detection line is arranged so that a subset of the memory cells coupled respectively thereto are substantially conductive.
16. The integrated circuit of claim 1, wherein memory cells coupled to each noise detection line remain unprogrammed.
17. The integrated circuit of claim 1, wherein said selection circuit is arranged so that a particular selected bit line on a bit line layer is never adjacent to a particular selected noise detection line on the same bit line layer.
18. The integrated circuit of claim 1, wherein said selection circuit is arranged so that a particular selected bit line on a bit line layer is never adjacent to another selected bit line on the same bit line layer at the same time.
19. The integrated circuit of claim 1, wherein alternating bit lines on a bit line layer form a first group and are associated with a selection circuit and sensing circuit disposed to one side of the array, and remaining bit lines on the layer form a second group and are associated with a selection circuit and sensing circuit disposed to a side of the array opposite the one side.
20. The integrated circuit of claim 1, wherein each respective bit line group on a bit line layer is associated with a respective noise detection line.
21. The integrated circuit of claim 1, wherein said multi-level memory array is arranged with a word line layer as the bottom-most layer of the memory array.
22. The integrated circuit of claim 1, wherein more than one noise detection line is associated with each selection circuit and sensing circuit.
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation application of co-pending U.S. application Ser. No. 12/405,160 filed Mar. 16, 2009, which application is a continuation application of U.S. application Ser. No. 10/253,024 filed Sep. 24, 2002, now U.S. Pat. No. 7,505,344, which application is a divisional application of U.S. application Ser. No. 09/896,468 filed Jun. 29, 2001, now U.S. Pat. No. 7,177,181, which application claims the benefit of the following U.S. Provisional Applications, each of which was filed on Mar. 21, 2001: U.S. Provisional Application No. 60/277,794; U.S. Provisional Application No. 60/277,815; and U.S. Provisional Application No. 60/277,738. Each of the above-referenced applications is hereby incorporated by reference in its entirety.
SUMMARY OF THE INVENTION In one aspect, the invention provides an integrated circuit which includes: a memory array, said memory array includes a plurality of memory cells, a layer of word lines, and more than one layer of bit lines, each layer of bit lines includes a bit line group; at least one noise detection line associated with each layer of bit lines; a selection circuit, said selection circuit selects a particular bit line group and selects a particular noise detection line associated with said particular bit line group; and a bit line sensing circuit, said bit line sensing circuit senses a signal on a selected bit line associated with said particular bit line group and a signal on said particular noise detection line associated with said particular bit line group.
In another aspect, the invention provides an integrated circuit which includes: a multi-level memory array of memory cells having at least one layer of word lines and more than one layer of bit lines, each layer of bit lines includes a bit line group; at least one noise detection line associated with each layer of bit lines; a selection circuit that selects a selected bit line associated with a particular bit line group, and a selected noise detection line associated with said particular bit line group; and a bit line sensing circuit, said bit line sensing circuit senses a signal on said selected bit line and a signal on said selected noise detection line.
In yet another aspect the invention provides an integrated circuit which includes: a multi-level memory array having at least one layer of word lines and more than one layer of bit lines; at least one noise detection line associated with each layer of bit lines; a selection circuit for selecting a bit line on a bit line layer and for selecting a noise detection line associated with the selected bit line; and a bit line sensing circuit for comparing the selected noise detection line to the selected bit line.
Different aspects of the invention may be advantageously used alone or in combination.
In a resting mode (i.e., an array inactive mode), all bit lines are preferably biased at a voltage at or near ground and all word lines are preferably biased at a voltage at or near ground. In a read standby mode, the unselected bit lines are precharged to a standby bias of +V, and the unselected word lines are biased to a reference voltage VREF (preferably about ⅓ VDD). The +V voltage is then applied through a selection device 110 to the selected word line 102. Such a selection device 110 may take a variety of suitable forms, and may include a word line driver circuit configured to drive its associated word line to unselected and selected bias voltages during a read operation, and may also be configured to drive its word line to other voltages during other times. Useful word line circuits and configurations are described in �Three-Dimensional Memory Array Incorporating Serial Chain Diode Stack,� application Ser. No. 09/897,705, which was filed on Jun. 29, 2001, and which is hereby incorporated by reference in its entirety, and further described in �Memory Device with Row and Column Decoder Circuits Arranged in a Checkerboard Pattern under a Plurality of Memory Arrays,� application Ser. No. 09/896,814, which was filed on Jun. 29, 2001, and which is hereby incorporated by reference in its entirety.
An implementation of a clamped bit line sense circuit 120 is also shown in FIG. 2. The selected bit line 106 is connected through the selection switch 111 to the common node 124 which forms an input node of the sense circuit 120. The bit line 106 is coupled to the drain of a PMOS clamp device 126 whose gate is coupled to a reference voltage VREF2 equal to about a PMOS threshold below the unselected word line voltage (e.g., VREF). The source of the clamp device 126 (node 128) is connected to an input of an amplifier circuit 130. Node 128 is pulled down below the unselected word line voltage VREF by a precharge control device 132. Since the gate of the clamp device 126 is a threshold voltage below VREF, the selected bit line 106 falls to VREF by conduction through the clamp device 126, at which point the clamp device 126 turns off. This causes the selected memory cell to conduct a current that is determined by its data (programmed) state. Preferably a high conductance (corresponding to an programmed antifuse) is called a zero state, and a low conductance (corresponding to an unprogrammed antifuse) is called a one state. The precharge device 132 is then turned off and a current mirror device 134 is turned on which sinks a reference current from node 128 that is less than the current through a cell in a zero state. The current through the memory cell (if any) and the reference current are summed at node 128. If the cell current is greater than the reference current, node 128 rises quickly to the VREF voltage of the bit line 106. Alternatively, if the cell current is less than the reference current, the node 128 stays at or near its precharged level and well below the selected bit line 106 voltage. Node 128 thus rises to or falls well below the VREF voltage depending on the memory cell state, and does so without any substantial voltage change on the selected bit line 106. The amplifier 130 compares the voltage of node 128 (also labeled �IN�) to a reference level VREF−VMARGIN and produces an output signal on an output node 136. The magnitude of VMARGIN is preferably 200-400 mV.
Referring now to FIG. 3, a timing diagram is shown illustrating the operation just described. Initially, the word lines and bit lines are driven to VREF and +V, respectively, to place the array in a read stand-by state. Then, the selected word line 102 is driven from a VREF voltage to a +V voltage by the driver 110. At about the same time (for certain embodiments), the bit line selection switch 111 is turned on to couple the selected bit line 106 to the current sense circuit 120, and the precharge device 132 is also turned on. As a result, node 128 (the IN node) is pulled toward ground to a voltage below the VREF voltage, and the selected bit line 106 is driven from its earlier bias voltage of +V to the VREF voltage. Since the bit line is driven to the VREF voltage through a device that gradually turns off as the bit line approaches its final voltage (i.e., clamp device 126), the bit line transition is shown asymptotically approaching its final voltage of VREF. The IN voltage is initially pulled below the VREF voltage by the precharge device 132, and then either rises to the VREF voltage or falls below the VREF−VMARGIN voltage, depending upon the magnitude of the current through the selected memory cell (which, of course, depends upon the data state of the memory cell).
Any leakage current flowing through path 152 causes a current to flow through the selected bit line 106. Such a current would add to the current being summed at node 128, and potentially change the voltage of node 128 and seriously affect the sensing operation. The preferred bias voltage across the half-selected memory cells 105 is zero because the selected bit line is clamped to VREF and the unselected word lines are biased at VREF. However, a small bias voltage across the half-selected memory cells that is close enough to zero may still result in leakage current that is insignificant (e.g., less than about 5-10%) relative to a selected memory cell current.
In a preferred embodiment incorporating antifuse memory elements, the memory cells on the noise detection line are not written (programmed) to the conductive state, so that when sensing, any current flowing into the noise detection line is only displacement current arising from capacitive coupling. The routing path of each noise detection line from the memory array through selection circuitry to the sense amplifier is preferably implemented similarly to the path for its associated bit lines, to again achieve close matching of any capacitance and coupling. A selection circuit 220 and sensing circuit 222 may be provided for each bit line layer, or may serve bit lines and noise detection lines on more than one bit line layer. Moreover, more than one selection circuit 220 and sensing circuit 222 may be provided for a single bit line layer.
Referring now to FIG. 8, a clamped bit line sensing circuit 172 utilizes a noise detection line to provide a reference for sensing and to achieve a greater tolerance for array noise. The selected bit line 106 is connected through the selection switch 111 to the drain of the PMOS clamp device 126, whose gate terminal is connected to the VREF2 voltage which is equal to about a PMOS threshold below the unselected word line voltage VREF, and whose source is connected to a non-inverting input (node 128) of a voltage sensing circuit 130, as before. A noise detection line 161 is parallel to, but not adjacent to, the selected bit line 106. All the word lines which traverse over the regular bit lines also traverse over the noise detection line 161, but no memory cells coupled between any of the word lines and the noise detection line 161 are programmed to source any current into the noise detection line 161. The noise detection line 161 is coupled through a selection device 162 to the drain of a matching PMOS clamp device 163, whose gate is also connected to the VREF2 voltage (i.e., VREF−VT,P), and whose source terminal (node 171) is connected to an inverting input of the voltage sensing circuit 130 (i.e., the �reference� side of the voltage sensing circuit 130).
Referring now to FIG. 11, a clamped bit line sense amplifier 300 is shown which uses an amplified feedback network to maintain the selected bit line voltage. By using a noise detection line in the configuration shown, no reference current is needed to distinguish between the one and zero state of the memory cell. Such a reference current is frequently difficult to provide because the current through a programmed memory cell varies greatly with normal manufacturing tolerances. In the embodiment shown, the selected bit line 106 and noise detection line 161 are driven to the unselected word line voltage VREF during a precharge time and then released. A time delay is provide after turning off the precharge transistors 302 and 304 before enabling the amplifier 310, to provide sufficient time for voltage amplification of amplifier 306 to produce a valid output signal on the OUT node. The effect of coupled noise on the selected bit line is balanced by the effect of coupled noise on the noise detection line. Both lines will move by the same voltage since the capacitance of both lines is matched. The amplifier 306 produces a current through the feedback resistor 308 which is substantially equal to the selected cell signal current and is substantially insensitive to the noise coupled to the selected bit line. This current through resistor 308 produces a large voltage change on the OUT node (assuming a suitably large valued resistor) which can be sensed by a voltage sensing circuit 310 activated at a detection time (i.e., after the time delay). This voltage change on the OUT node can be more rapid and much larger than the current to be sensed could have produced on the bit line. The voltage excursions of node OUT may be large enough to satisfactorily use a single-ended amplifier for the voltage sensing circuit 310.
OTHER FEATURES AND EMBODIMENTS While several different sensing circuits have been described herein, the use of noise detection lines is contemplated with other sensing circuits as well. Moreover, the invention is also advantageously employed in a memory array having a single memory plane, and does not require a three-dimensional or multi-level memory array. In certain embodiments, more than two noise detection lines may be employed on each bit line layer for better tracking, allowing a noise detection line which is close to the selected bit line to be selected by the selection circuit. A noise detection line may be connected to more than one sense amplifier to save space, or may be provided for each sense amplifier per bit line group. If a noise detection line is shared among more than one sense circuit, its total capacitance is preferably matched to the total capacitance for the path from a bit line to just one sense amplifier. In another embodiment, a noise detection line is associated with just one bit line on just one level. In a preferred embodiment, a three-dimensional array may be implemented with a �word line first� arrangement (a layer of word lines on the bottom closest to circuitry within the substrate) rather than a �bit line first� arrangement to help reduce coupling onto the bottom-most layer of bit lines.
The instant invention can be applied to any memory array, whether three-dimensional or otherwise, having memory cells exhibiting diode-like characteristic conduction. Preferably, the memory cells are comprised of semiconductor materials, as described in U.S. Pat. No. 6,034,882 to Johnson et al., U.S. Pat. No. 6,185,122 to Johnson, et al., U.S. Pat. No. 5,835,396 to Zhang, U.S. patent application Ser. No. 09/560,626 to Knall, and U.S. patent application Ser. No. 09/638,428 to Johnson, each of which is hereby incorporated by reference in its entirety. Fuse memory cells and antifuse memory cells are also contemplated. For some embodiments, such memory cells may program at a voltage in the range of about 5-20 volts. Specifically an antifuse memory cell is preferred. Other passive element memory cells incorporate layers of organic materials including at least one layer that has a diode-like characteristic conduction and at least one organic material that changes conductivity with the application of an electric field. U.S. Pat. No. 6,055,180 to Gudensen et al. describes organic passive element arrays and is also hereby incorporated by reference in its entirety. Memory cells comprising materials such as phase-change materials and amorphous solids can also be used. See U.S. Pat. No. 5,751,012 to Wolstenholme et al. and U.S. Pat. No. 4,646,266 to Ovshinsky et al., each of which is hereby incorporated by reference in its entirety.
The embodiments described may show a selected word line being driven to a voltage and a selected bit line being sensed, and memory cell anode terminals connected to word lines and cathode terminals connected to bit lines, but other embodiments are specifically contemplated. For example, in a multi-level memory array, an adjacent memory plane may be connected similarly (e.g., a back-to-back diode stack memory array), or may reverse the directionality of memory cells in the adjacent plane (e.g., a serial chain diode stack memory array) so that the anode terminals are connected to bit lines and the cathode terminals to word lines. In other words, the X-lines of a given X-line layer may be connected to respective anode terminals of some associated memory cells (e.g., in a memory plane below the given layer), and to respective cathode terminals of other associated memory cells (e.g., in a memory plane above the given layer). In such a case, a selected X-line may be either driven or sensed depending upon whether it connects to a respective anode terminal of a selected memory cell (e.g., a selected memory cell in a memory plane below the given layer) or a respective cathode terminal of a selected memory cell (e.g., a selected memory cell in a memory plane above the given layer). Consequently, the designations herein of X-lines, word lines, and row lines, and of Y-lines, bit lines, and column lines are illustrative of the various embodiments but should not be viewed in a restrictive sense, but rather a more general sense. For example, the sensing circuits described herein may be coupled to word lines rather than bit lines, or may be used for both word lines and bit lines, when sensing a current in a word line rather than in a bit line. Such organizations (and others) are described in the aforementioned �Three-Dimensional Memory Array Incorporating Serial Chain Diode Stack� by Kleveland, et al, U.S. patent application Ser. No. 09/897,705.
The foregoing detailed description has described only a few of the many possible implementations of the present invention. For this reason, this detailed description is intended by way of illustration, and not by way of limitations. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope and spirit of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of this invention.
On Mar. 21, 2001, the following U.S. patent applications were filed, each of which is hereby incorporated by reference in its entirety: �Memory Device with Row and Column Decoder Circuits Arranged in a Checkerboard Pattern under a Plurality of Memory Arrays,� U.S. Provisional Application No. 60/277,794; �Passive Element Memory Array and Related Circuits Useful Therefor,� U.S. Provisional Application No. 60/277,815; �Three-Dimensional Memory Array,� U.S. Provisional Application No. 60/277,738; and �Three-Dimensional Memory Array and Method of Fabrication,� U.S. application Ser. No. 09/814,727.
On Jun. 29, 2001, the following U.S. patent applications were filed, each of which is hereby incorporated by reference in its entirety: �Method and Apparatus for Writing Memory Arrays Using External Source of High Programming Voltage,� U.S. patent application Ser. No. 09/897,785; �Three-Dimensional Memory Array Incorporating Serial Chain Diode Stack,� U.S. patent application Ser. No. 09/897,705; �Method and Apparatus for Biasing Selected and Unselected Array Lines when Writing a Memory Array,� U.S. patent application Ser. No. 09/897,771; �Memory Device with Row and Column Decoder Circuits Arranged in a Checkerboard Pattern under a Plurality of Memory Arrays,� U.S. patent application Ser. No. 09/896,814; �Method and System for Increasing Programming Bandwidth in a Non-Volatile Memory Device,� U.S. patent application Ser. No. 09/895,960; �Method and Apparatus for Discharging Memory Array Lines,� U.S. patent application Ser. No. 09/897,784; �Current Sensing Method and Apparatus Particularly Useful for a Memory Array of Cells Having Diode-Like Characteristics,� U.S. patent application Ser. No. 09/896,468; �Memory Array Incorporating Noise Detection Line,� U.S. patent application Ser. No. 09/897,704; and �Memory Device and Method for Sensing while Programming a Non-Volatile Memory Cell,� U.S. patent application Ser. No. 09/896,815.
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(now abandoned).Classifications U.S. Classification365/206, 365/63, 365/51International ClassificationG11C17/18, G11C7/02, G11C8/08, G11C7/06, G11C5/02, G11C7/18, G11C8/10Cooperative ClassificationG11C2207/063, G11C8/08, G11C7/062, G11C5/025, G11C7/067, G11C7/18, G11C8/10, G11C17/18European ClassificationG11C7/06C, G11C8/08, G11C17/18, G11C5/02S, G11C7/18, G11C7/06S, G11C8/10RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google