Source: http://www.google.com/patents/US20030097246?ie=ISO-8859-1&dq=5,758,352
Timestamp: 2014-11-28 18:28:14
Document Index: 309695186

Matched Legal Cases: ['arty 1120', 'arty 1221', 'arty 1221', 'arty 1221', 'arty 1121', 'arty 1221', 'arty 2120']

Patent US20030097246 - Circuit simulation method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsIn a circuit simulation system, a simulator and part of device models and circuit models are stored in a server on the Internet, a user sends arbitrary circuit data to the server, the server carries out calculation using the circuit data received from the user and the device and circuit models stored...http://www.google.com/patents/US20030097246?utm_source=gb-gplus-sharePatent US20030097246 - Circuit simulation methodAdvanced Patent SearchPublication numberUS20030097246 A1Publication typeApplicationApplication numberUS 09/987,841Publication dateMay 22, 2003Filing dateNov 16, 2001Priority dateNov 16, 2001Publication number09987841, 987841, US 2003/0097246 A1, US 2003/097246 A1, US 20030097246 A1, US 20030097246A1, US 2003097246 A1, US 2003097246A1, US-A1-20030097246, US-A1-2003097246, US2003/0097246A1, US2003/097246A1, US20030097246 A1, US20030097246A1, US2003097246 A1, US2003097246A1InventorsTsutomu Hara, Hideki Osaka, Toyohiko Komatsu, Hitoshi Yokota, Atsushi Nakamura, Koichi KimuraOriginal AssigneeTsutomu Hara, Hideki Osaka, Toyohiko Komatsu, Hitoshi Yokota, Atsushi Nakamura, Koichi KimuraExport CitationBiBTeX, EndNote, RefManReferenced by (7), Classifications (4), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetCircuit simulation methodUS 20030097246 A1Abstract In a circuit simulation system, a simulator and part of device models and circuit models are stored in a server on the Internet, a user sends arbitrary circuit data to the server, the server carries out calculation using the circuit data received from the user and the device and circuit models stored therein, and then the server returns the results of calculation to the user. Images(15) Claims(12)
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0027] The present invention will now be described in detail by way of example with reference to the accompanying drawings. [0028] The following describes a first preferred embodiment of the present invention. Referring to FIG. 1, there is shown a configuration of a circuit simulation system in the first preferred embodiment. The circuit simulation system of the first preferred embodiment mainly comprises a terminal apparatus 1120 of a circuit design engineering party (chip-set manufacturer), a terminal or server 1130 of a device manufacturer, and a server 1111 in which circuit simulation is carried out. The server 1111 is connected to the terminal apparatus 1120 of the circuit design engineering party (chip-set manufacturer) over the Internet 1140. [0029] The server 1111 is also connected to the Internet 1140 and to the terminal 1130 of the device manufacturer through an Internet interface 1112. Note that the server 1111 may be connected to the terminal 1130 of the device manufacturer via the Internet 1140, a local area network, or a part of the server 1111 itself. On the server 1111, there is provided a data region 1115 in which data necessary for circuit simulation is stored. [0030] The data region 1115 comprises a region 1116 for holding design rules such as noise budgets, a region 1117 for holding simulation circuit connection models, and a region 1118 for holding device transistor models. These regions can be accessed by the device manufacturer. [0031] With reference to FIGS. 2 to 9, a data processing flow in the first preferred embodiment is described below. [0032]FIG. 2 shows a flow of data processing in the circuit simulation system. In processing 1291 on the server 1111 shown in FIG. 2, a Web page (home page) having an entry screen 1300 such as shown in FIG. 3 is set up on the Internet. The circuit design engineering party 1120 (chip-set manufacturer using the terminal apparatus 1120) can enter the environment of the circuit simulation system by accessing the Web page 1130 on the Internet. [0033] When the circuit design engineering party (chip-set manufacturer) 1120 selects a desired circuit model, the circuit design engineering party inputs a user account (user name) and a password as shown in FIG. 4. Thus, information on circuit model selection (destination-of-link information) is sent to the server 1111 (processing 1291 on the server) together with the user account and password. The user account and password are used for billing and checking an attempt to access simulation result data or calculation graph data. Upon receiving the circuit model selection information (destination-of-link information), user account and password, the server 1111 performs a user registration/checkup and then presents a Web page 1500 shown in FIG. 5 according to the circuit model selection information (destination-of-link information). On the Web page 1500, the circuit design engineering party can specify such parameters as circuit configuration values, electric constants and driver elements. [0034] As shown in FIG. 5, the circuit design engineering party enters electric constants with reference to a circuit model scheme 1501. A first input box 1502 is used for specifying an operation frequency. A second input box 1503 has a pull-down menu, which provides a list of selectable device names. The following three input boxes 1504 to 1506 are used for specifying a damping resistance, a terminator resistance, and a load capacity of a receiver. [0035] On the lower part of the Web page 1500, there are provided input boxes for defining a cross-sectional configuration of a circuit board. These input boxes are used to specify a line width 1511, a line thickness 1512, a dielectric layer thickness 1513, a dielectric constant 1514, a permeability value 1515, and a line length 1516. Calculation is performed to determine a constant according to the printed circuit board configuration and signal wiring arrangement concerned. After entering all the conditions, the circuit design engineering party presses a calculation run button 1510 to issue a calculation execution command. When the calculation execution command is issued, an impedance and a propagation velocity are calculated and data reshaping for transmission thereof is carried out at the terminal apparatus of the circuit design engineering party (data processing and calculation 1224 in FIG. 2). [0036] Thereafter, data thus prepared at the terminal apparatus of the circuit design engineering party is sent to the server (1225 in FIG. 2). The server receives the data over the Internet (1205 in FIG. 2), and then carries out data processing and calculation for circuit simulation (1206 in FIG. 2). After these steps, a SPICE simulation start command is issued to the server to carry out SPICE circuit simulation (1207 in FIG. 2). [0037] In execution of the SPICE circuit simulation, calculation is performed using the above-noted data including the electric constants, device name and circuit configuration values which have been input through the Internet, with reference to mounting rule data, circuit connection model data and transistor model data stored in the data region 1115 of the server. Simultaneously with execution of the circuit simulation, a status display screen is prepared to indicate the progress of calculation (1208 in FIG. 2). [0038]FIGS. 6 and 7 show examples of status display screens. In the first preferred embodiment of the present invention, when the calculation run button (1510 in FIG. 3) is pressed, the status display screen shown in FIG. 6 is presented to indicate whether or not calculation has been performed normally. When a calculation result display button 1601 is pressed in the course of calculation, the status display screen shown in FIG. 7 is presented. A judgment is formed on whether or not the circuit simulation has been completed. If not, a wait is provided until completion of the circuit simulation (1209 in FIG. 2). At the end of execution of the circuit simulation, a graph is generated using the results of the circuit simulation (1210 in FIG. 2). [0039] Then, the graph thus generated and numeric data resultant from the circuit simulation are processed for placement in a Web page (1211 in FIG. 2). At this step, the status display screen shown in FIG. 7 (Web page 1701) is changed into a graph display page. Thus, the calculation result display button 1601 can be used for checking the current status of calculation and the results of calculation. In this arrangement, since the circuit design engineering party (chip-set manufacturer) can disconnect the terminal apparatus thereof from the circuit simulation system during a calculation time, the circuit design engineering party can perform another task on the terminal apparatus without applying unnecessary load thereto. [0040] Further, by making access to the Internet at a convenient time, the circuit design engineering party can acquire a calculation result graph such as shown in FIG. 8 and numeric data through the status display screen shown in FIG. 6. When the circuit design engineering party attempts to access calculation result data, a message prompting for input of a user account (name) and a password appears as shown in FIG. 4. This makes it possible for the circuit design engineering party to attain calculation result data concerned promptly while preventing a third party from reading the calculation result data. [0041] The advantageous effects of the first preferred embodiment of the present invention are described below with reference to FIGS. 1, 2, and 9 to 11. [0042] Using FIGS. 9, 10 and 1, the advantageous effects of the first preferred embodiment from the standpoint of the circuit design engineering party are discussed first. FIG. 9 shows a conventional design method using circuit simulation. In the conventional design method, there is provided a simulator 1920 on the part of a circuit design engineering party (chip-set manufacturer) 1221 as shown in FIG. 9. Mounting rules 1916 and circuit connection models 1917 are also formed on the part of the circuit design engineering party 1221. That is to say, it is required for the circuit design engineering party to prepare a simulator, mounting rules, circuit connection models, and device simulation models. Therefore, a mounting design flow such as shown in FIG. 10(a) is taken on the part of the circuit design engineering party. In the conventional design method, product specifications are determined first, and then digital circuit logic design is performed. Thereafter, mounting design for layout and wiring arrangements is carried out. In the phase of mounting design, circuit simulation is performed to check for reflection due to circuit impedance mismatching, transmission line propagation delay, crosstalk, radiation noise, etc. [0043] Based on the results of model optimization examination and circuit simulation, the designing of layout and wiring arrangements is repeated to attain a proper mounting formation. Then, an actual circuit board is produced and evaluated. If any specified requirement is not satisfied, mounting design and circuit simulation are repeated until the specified requirement is satisfied. For shortening a design time, it is required to optimize simulation models. Further, it is also required to reduce the number of repetitions of layout/wiring design based on the results of circuit simulation and mounting design based on the results of actual product evaluation. Therefore, in mounting design of high-speed circuits, accumulation of know-how and verification through experiments are needed for preparing proper mounting rules 1916 and circuit connection models 1917. [0044] Moreover, in the conventional design method, the circuit design engineering party 1221 is required to prepare device transistor models 1918. In cases where high-accuracy simulation calculation is carried out using the device transistor models 1918, actual LSI process data and transistor characteristics must be expressed with high fidelity. Through model analysis on the part of the circuit design engineering party 1221, there is a possibility that confidential technical information and know-how possessed by the device manufacturer concerned 1130 may leak to the circuit design engineering party 1121. [0045] To prevent leakage of confidential technical information out of the device transistor models 1918, a confidentiality agreement is made between the circuit design engineering party 1221 and the device manufacturer 1130 at much expense in time and effort. As a means of preventing leakage of confidential technical information, IBIS models 1919 (input/output buffer information specification models) for approximately expressing LSI behavior in terms of voltage-current relationship are used in some cases. The IBIS models 1919 are however disadvantageous in that satisfactory calculation accuracy is not attainable. [0046] By way of contrast, in the first preferred embodiment of the present invention, the transistor models 1118 are managed in the server. Therefore, the circuit design engineering party (chip-set manufacturer) cannot make direct access to the transistor models 1118. [0047] With reference FIG. 2, a flow of data to be used by the circuit design engineering party is described below. In FIG. 2, each broken line indicates a path through which information is disclosed. From the server, the circuit design engineering party receives the following data; table-of-contents screen data 1201 (FIG. 3), user registration screen data 1202 (FIG. 4), circuit model screen data 1203 (FIG. 5), calculation status screen data 1208 (FIG. 6), and calculation result screen data 1211 (FIG. 8). In the circuit simulation system of the present invention, since transistor model data is not directly disclosed to the circuit design engineering party but calculation result data only is disclosed thereto, it is possible to prevent the circuit design engineering party from attempting unauthorized analysis of device transistor models. [0048] The following describes advantageous effects of the first preferred embodiment from the standpoint of the supply side of device models, with reference to FIGS. 11 and 1. FIG. 11(a) shows how device models are produced by a device model supplier in the conventional design method. Using semiconductor chip process data, transistor models are prepared. At the same time, IBIS modeling is made through analysis of electrical characteristics such as resistance, capacity and inductance of each LSI package. In this modeling step, for reproducing actual operation with high fidelity, highly accurate process data is incorporated in simulation models. As a result, there occurs a possibility that confidential technical information regarding fabrication process, circuit design and manufacture may leak out of the simulation models. Therefore, in a situation where simulation models at this step are supplied from the device model supplier to each customer, a confidentiality agreement concerning information release is made therebetween. To prevent leakage of confidential technical information out of simulation models, transistor models are converted into IBIS models in which device output is approximately expressed in terms of voltage-current relationship. [0049] For preparing each of these IBIS models, it is required to take a burdensome step of determining a voltage-current relational condition through experiments. A circuit scheme in which an impedance varies during operation is adopted for a certain type of high-speed circuit. In such a case, it is necessary to prepare each model corresponding to each condition. Thus, time-consuming tasks for experiments and conditioning are needed to produce simplified models. [0050] Further, as shown in FIG. 9, each circuit design engineering party (chip-set manufacturer) uses a simulator of its own. In some cases, simulation models may not be applicable to a type/version of simulator different from that assumed by the device manufacturer. To circumvent this problem, the device manufacturer must prepare models applicable to each type/version of simulator at much expense in time and effort. Further, a substantial amount of time and additional costs are required in cases where models thus prepared are delivered to many customers. [0051] In the first preferred embodiment of the present invention, since there is no need to disclose device transistor model data to each customer as mentioned in the foregoing, the device manufacturer has only to register, in the server, combination models containing device transistor models and electric constant models of LSI packages as shown in FIG. 11(b). It is therefore not required to prepare approximate models and carry out experiments using these models. Further, since models are registered only in the server regardless of the number of customers, the time and costs required for delivering models to each customer can be eliminated. [0052] Moreover, the server may also be provided with a model access counting function and a device usage recording function. Through the use of these functions, the device manufacturer can attain information on technical trends in circuit modeling among the customers. [0053] Still further, as shown in FIG. 14, a screen for displaying the results of calculation in circuit simulation may be so arranged as to indicate such items as selected device data, device configuration data, a request for data sheets/circuit diagrams used for calculation, and a purchase order for devices. This makes it easy for each customer to place an order for devices, which could lead to an increase in sales of the devices. [0054] The following describes a circuit simulation system according to a second preferred embodiment of the present invention, with reference to FIGS. 12 and 13. As in the first preferred embodiment, the circuit simulation system of the second preferred embodiment mainly comprises a terminal apparatus 2120 of a circuit design engineering party (chip-set manufacturer), a terminal or server 2130 of a device manufacturer, and server 2111 in which circuit simulation is carried out. The server 2111 is connected to the terminal apparatus 2120 of the circuit design engineering party (chip-set manufacturer) over the Internet 2120. Through an Internet interface 2112, the server 2111 is also connected to the Internet 2140 and to the terminal 2130 of the device manufacturer. [0055] On the server 2111, there is provided a data region 2115 in which data necessary for circuit simulation is stored. The data region 2115 comprises a region 2116 for holding mounting rules such as noise budgets, a region 2117 for holding simulation circuit connection models, and region 2118 for holding device transistor models and device models received from the circuit design engineering party. A manager of the server is authorized to alter the contents of the region 2116 for holding mounting rules such as noise budgets and the region 2117 for holding simulation circuit connection models. The authority to alter the contents of these regions may be granted to either the server manager or a program which carries out data processing in the server. As to device models, a device supplier is authorized to alter device model data. The authority to alter device model data may be granted to either the device supplier or an apparatus (program) managed by the device supplier. [0056] The authority to alter the contents of the region 2118 for holding device models received from the circuit design engineering party is granted to the circuit design engineering party. As mentioned above, the data storage regions in the server are classified into regions accessible only with particular authority and regions accessible without any authority. A simulator used for carrying out circuit simulation can make access to any data in the server. [0057] With reference to FIG. 13, a data processing flow in the second preferred embodiment is described below. FIG. 13 shows a flow of data processing in the circuit simulation system. In processing 1291 on the server shown in FIG. 13, a Web page (home page) having an entry screen 2300 is set up on the Internet. When the circuit design engineering party 2120 (chip-set manufacturer using the terminal apparatus 2120) selects a desired circuit model, the circuit design engineering party inputs a user account (user name) and a password as shown in FIG. 4. Then, information on circuit model selection (destination-of-link information) is sent to the server 2111 (processing 2291 on the server) together with the user account and password. The user account and password are used for billing, checking an attempt to access simulation result data or calculation graph data, and identifying each data region in which user's simulation models are registered. Upon receiving the circuit model selection information (destination-of-link information), user account and password, the server 2111 performs a user registration/checkup and then presents a Web page 2500 according to the circuit model selection information (destination-of-link information). On the Web page 2500, the circuit design engineering party can specify such parameters as circuit configuration values, electric constants and driver elements. [0058] As in the first preferred embodiment, the circuit design engineering party enters electric constants and other parameters with reference to a circuit model scheme. If a unique simulation model is required, the circuit design engineering party specifies a data file therefor. After entering all the conditions, the circuit design engineering party presses a calculation run button 2510 to issue a calculation execution command. When the calculation execution command is issued, an impedance and a propagation velocity are calculated and data reshaping for transmission thereof is carried out at the terminal apparatus of the circuit design engineering party. Thereafter, data regarding electric constants and other parameters for device model selection and data specific to user simulation modeling are sent to the server (1225 in FIG. 13). The server receives these data over the Internet (2205 in FIG. 13), and then carries out data processing and calculation for circuit simulation (2206 in FIG. 13). [0059] According to the user account (user name) and password registered by the circuit design engineering party, simulation model data is stored in the data region of the server. The data region is so arranged as to be accessible by the user (circuit design engineering party), simulator, and server manager. In a modified arrangement, only the server manager may be authorized to access the data region. After these steps, a SPICE simulation start command is issued to the server to carry out SPICE circuit simulation (2207 in FIG. 13). In execution of the SPICE circuit simulation, calculation is performed using the above-noted data including the electric constants, device name and circuit configuration values which have been input through the Internet, with reference to mounting rule data, circuit connection model data, circuit connection model data and user-specific simulation model data stored in the data region 2115 of the server. Simultaneously with execution of the circuit simulation, a status display screen is prepared to indicate the progress of calculation (2208 in FIG. 13). [0060] Then, a judgment is formed on whether or not the circuit simulation has been completed. If not, a wait is provided until completion of the circuit simulation (2209 in FIG. 13). At the end of execution of the circuit simulation, a graph is generated using the results of the circuit simulation (2210 in FIG. 13). Then, the graph thus generated and numeric data resultant from the circuit simulation are processed for placement in a Web page, and the contents of the Web page are registered in a file (2211 in FIG. 13). Thus, the circuit design engineering party can acquire a calculation result graph and numeric data by making access to the Internet at a convenient time. [0061] As mentioned above, in the second preferred embodiment of the present invention, since user-specific simulation model data is temporarily stored in the server, it is possible to perform simulation calculation on other than existent model data pre-registered in the server. Further, a user account (user name) and password are attached to user-specific simulation model data in the server for limiting accessibility thereto. Thus, the user-specific simulation model data can be protected against unauthorized access from a third party. [0062] As set forth hereinabove and according to the present invention, a simulator, device model data and circuit connection model data are registered in a server on the Internet, and a circuit design engineering party (chip-set manufacturer) acquires the results of simulation calculation through the Internet. Thus, only the results of simulation calculation can be disclosed to the circuit design engineering party without directly disclosing device transistor model data thereto. It is therefore possible to prevent the circuit design engineering party from attempting unauthorized analysis of device transistor models. Furthermore, since device models registered in the server are available to the circuit design engineering party through the Internet, there is no need to deliver device models to the circuit design engineering party each time they are updated. In a modification of the present invention, there may be provided such an arrangement that the results of simulation calculation can be accessed only by the circuit design engineering party concerned or from an information processing apparatus used by the circuit design engineering party concerned. [0063] The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6978435 *Aug 29, 2002Dec 20, 2005Anadigm, Inc.Apparatus for programming a programmable device, and methodUS7093205 *Apr 10, 2003Aug 15, 2006Barcelona Design, Inc.Method and apparatus for efficient semiconductor process evaluationUS7240309 *Jan 20, 2004Jul 3, 2007Matsushita Electric Industrial Co., Ltd.Design check system, design check method and design check programUS7483820 *Apr 17, 2007Jan 27, 2009Gemini Design Technology, Inc.Method for ranking webpages via circuit simulationUS7783465Dec 18, 2006Aug 24, 2010Synopsys, Inc.Parallel multi-rate circuit simulationUS20100114553 *Oct 28, 2009May 6, 2010Kyung Rok KimSystems and Methods for Executing Unified Process-Device-Circuit SimulationWO2007123919A2 *Apr 17, 2007Nov 1, 2007Gemini Design Technology IncMethod for ranking webpages via circuit simulation* Cited by examinerClassifications U.S. Classification703/14International ClassificationG06F17/50Cooperative ClassificationG06F17/5036European ClassificationG06F17/50C4Legal EventsDateCodeEventDescriptionOct 11, 2002ASAssignmentOwner name: HITACHI, LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HARA, TSUTOMU;OSAKA, HIDEKI;KOMATSU, TOYOHIKO;AND OTHERS;REEL/FRAME:013379/0128;SIGNING DATES FROM 20011010 TO 20011015May 21, 2002ASAssignmentOwner name: HITACHI, LTD., JAPANFree format text: CORRECTIVE ASSIGNMENT TO ADD FOURTH ASSIGNOR TO RECORD, PREVIOUSLY RECORDED AT REEL 012668, FRAME 0530;ASSIGNORS:HARA, TSUTOMU;OSAKA, HIDEAKI;KOMATSU, TOYOHIKO;AND OTHERS;REEL/FRAME:012932/0211;SIGNING DATES FROM 20011010 TO 20011015Mar 12, 2002ASAssignmentOwner name: HITACHI, LTD., JAPANFree format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE SECOND ASSIGNOR PREVIOUSLY RECORDED ON REEL 012313FRAME 0438;ASSIGNORS:HARA, TSUTOMU;OSAKA, HIDEKI;KOMATSU, TOYOHIKO;AND OTHERS;REEL/FRAME:012668/0530;SIGNING DATES FROM 20011010 TO 20011015Nov 16, 2001ASAssignmentOwner name: HITACHI, LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HARA, TSUTOMU;OSAKA, HIDEAKI;KOMATSU, TOYOHIKO;AND OTHERS;REEL/FRAME:012313/0438;SIGNING DATES FROM 20011010 TO 20011015RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google