Source: https://patents.google.com/patent/US8836023B2/en
Timestamp: 2019-09-22 07:26:01
Document Index: 519971462

Matched Legal Cases: ['Application No. 06785207', 'Application No. 06785207', 'Application No. 06785207', 'Application No. 10', 'Application No. 200718836', 'Application No. 200718836', 'Application No. 200680022726', 'Application No. 2008', 'Application No. 2008', 'Application No. 10', 'Application No. 10', 'Application No. 095122787', 'Application No. 095122787']

US8836023B2 - Memory device with recessed construction between memory constructions - Google Patents
US8836023B2
US8836023B2 US13/025,047 US201113025047A US8836023B2 US 8836023 B2 US8836023 B2 US 8836023B2 US 201113025047 A US201113025047 A US 201113025047A US 8836023 B2 US8836023 B2 US 8836023B2
US13/025,047
US20110133270A1 (en
2005-06-24 Priority to US11/166,721 priority Critical patent/US7902598B2/en
2011-02-10 Application filed by Micron Technology Inc filed Critical Micron Technology Inc
2011-02-10 Priority to US13/025,047 priority patent/US8836023B2/en
2011-02-15 Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JUENGLING, WERNER
2011-06-09 Publication of US20110133270A1 publication Critical patent/US20110133270A1/en
2014-09-16 Publication of US8836023B2 publication Critical patent/US8836023B2/en
a substrate having a first surface and a doping concentration;
a plurality of memory cells arranged in a pattern on the substrate, wherein the plurality of memory cells each include a charge storage device and a recessed access device formed so as to extend into the substrate, wherein the recessed access device is configured to induce a first depletion region in the substrate and define a current flow path about the recessed perimeter of the recessed access device within the substrate; and
a plurality of isolation structures each recessed in the substrate so as to isolate adjacent memory cells of the plurality of memory cells from each other, wherein each of the plurality of isolation structures receives a bias voltage during operation of the memory device that together with the doping concentration of the substrate induces a second depletion region in the substrate that merges with the corresponding first depletion region to thereby inhibit leakage between adjacent memory cells.
5. The device of claim 4, wherein the second depletion region merges with the corresponding first depletion region such that the doping level of the substrate can be reduced without increasing the leakage current between memory cells.
6. The device of claim 3, wherein each of the plurality of memory cells comprise a first and a second plurality of recessed gates and a first and a second charge storage device and wherein each of the plurality of memory cells include a common source/drain region that is common between the first and second gates and is electrically coupled to a single digit line.
8. The device of claim 1, wherein the substrate comprises a p-doped substrate and wherein the plurality of recessed gates comprises recessed access devices.
9. The device of claim 1, further comprising a word line that is used to activate the gate of a plurality of cells and wherein the bit line also electrically connects to a plurality of cells and wherein the gate of each memory cell defines an active area.
10. The device of claim 9, wherein the active area of each of the plurality of cells is oriented at an angle of about 45 degrees with respect to the bit line and word line.
a grounded recessed transistor gate construction interposed between the first and second memory constructions, wherein during operation of the memory device the grounded recessed gate construction receives a bias that together with the doping concentration of the substrate forms a depletion region that merges with a depletion region of the first transistor construction and a depletion region of the second transistor construction such that leakage current between the first transistor construction and the second transistor construction is substantially reduced.
12. The memory device of claim 11, wherein the first and second transistor constructions are two-sided access transistors.
13. The memory device of claim 11, wherein the memory device is a 4.5F2 DRAM cell.
14. The memory device of claim 11, wherein the first digit line and the second digit line are the same.
15. The device of claim 11, wherein substrate is a semiconductor substrate, and wherein the depletion region of the grounded recessed transistor gate construction merges with the depletion region of the first transistor construction and the depletion region of the second transistor construction such that the doping level of the semiconductor substrate can be reduced without substantially increasing leakage current between the first transistor construction and the second transistor construction.
a first memory construction comprising: a first transistor construction having a first recessed gate that extends into the substrate from the first surface; a first source; and a first drain, the first recessed gate interposed between the first source and the first drain;
a second memory construction comprising: a second transistor construction having a second recessed gate that extends into the substrate from the first surface; a second source; and a second drain, the second recessed gate interposed between the second source and the second drain; and
a recessed transistor gate construction interposed between the first and second memory constructions, wherein during operation of the memory device the recessed transistor gate construction receives a bias that together with the doping concentration of the substrate forms a depletion region that merges with a depletion region of the first transistor construction and a depletion region of the second transistor construction to provide isolation between the first memory construction and the second memory construction.
17. The device of claim 16, wherein the recessed transistor gate construction is biased such that the recessed transistor gate construction is in the depletion mode.
18. The device of claim 16, wherein the recessed transistor gate construction is biased such that the recessed transistor gate construction is in the accumulation mode.
19. The device of claim 16, wherein the recessed transistor gate construction is grounded.
20. The device of claim 16, further comprising a first memory storage device electrically coupled to the first source and a first digit line electrically coupled to the first drain.
21. The device of claim 16, further comprising a second memory storage device electrically coupled to the second source and a second digit line electrically coupled to the second drain.
22. The device of claim 16, wherein substrate is a semiconductor substrate, and wherein the depletion region of the recessed transistor gate construction merges with the depletion region of the first transistor construction and the depletion region of the second transistor construction such that the doping level of the semiconductor substrate can be reduced without substantially increasing leakage current between the first transistor construction and the second transistor construction.
US13/025,047 2005-06-24 2011-02-10 Memory device with recessed construction between memory constructions Active US8836023B2 (en)
US11/166,721 US7902598B2 (en) 2005-06-24 2005-06-24 Two-sided surround access transistor for a 4.5F2 DRAM cell
US13/025,047 US8836023B2 (en) 2005-06-24 2011-02-10 Memory device with recessed construction between memory constructions
US13/799,084 US8933508B2 (en) 2005-06-24 2013-03-13 Memory with isolation structure
US11/166,721 Division US7902598B2 (en) 2005-06-24 2005-06-24 Two-sided surround access transistor for a 4.5F2 DRAM cell
US13/799,084 Continuation US8933508B2 (en) 2005-06-24 2013-03-13 Memory with isolation structure
US20110133270A1 US20110133270A1 (en) 2011-06-09
US8836023B2 true US8836023B2 (en) 2014-09-16
US11/166,721 Active 2027-10-25 US7902598B2 (en) 2005-06-24 2005-06-24 Two-sided surround access transistor for a 4.5F2 DRAM cell
US13/025,047 Active US8836023B2 (en) 2005-06-24 2011-02-10 Memory device with recessed construction between memory constructions
US13/799,084 Active 2025-06-27 US8933508B2 (en) 2005-06-24 2013-03-13 Memory with isolation structure
TW (1) TWI360202B (en)
WO (1) WO2007002117A2 (en)
KR101920626B1 (en) * 2011-08-16 2018-11-22 삼성전자주식회사 Data storage device and method of fabricating the same
KR20150091944A (en) * 2014-02-04 2015-08-12 삼성전자주식회사 Magnetic memory device
US20160104782A1 (en) * 2014-10-08 2016-04-14 Inotera Memories, Inc. Transistor structure and method of manufacturing the same
US10312321B2 (en) 2015-08-28 2019-06-04 International Business Machines Corporation Trigate device with full silicided epi-less source/drain for high density access transistor applications
WO2018182726A1 (en) * 2017-03-31 2018-10-04 Intel Corporation Transistors with oxygen exchange layers in the source and drain
JPH05198773A (en) 1991-08-16 1993-08-06 Gold Star Electron Co Ltd Semiconductor memory cell and its manufacturing method
JPH06326273A (en) 1993-05-16 1994-11-25 Nec Corp Semiconductor memory
JPH07297297A (en) 1994-04-22 1995-11-10 Nec Corp Semiconductor memory device and method of manufacturing
JP2001148418A (en) 1999-11-19 2001-05-29 Mitsubishi Electric Corp Semiconductor device
2005-06-24 US US11/166,721 patent/US7902598B2/en active Active
2006-06-21 JP JP2008518327A patent/JP2008547228A/en active Pending
2006-06-21 EP EP20060785207 patent/EP1897134B1/en active Active
2006-06-21 KR KR20087001926A patent/KR101331748B1/en active IP Right Grant
2006-06-21 CN CN 200680022726 patent/CN101208795B/en active IP Right Grant
2006-06-21 WO PCT/US2006/024025 patent/WO2007002117A2/en active Application Filing
2006-06-23 TW TW95122787A patent/TWI360202B/en active
2011-02-10 US US13/025,047 patent/US8836023B2/en active Active
2013-03-13 US US13/799,084 patent/US8933508B2/en active Active
US6396113B1 (en) 1999-11-19 2002-05-28 Mitsubishi Denki Kabushiki Kaisha Active trench isolation structure to prevent punch-through and junction leakage
Communication under Rule 71(3) EPC of Oct. 2, 2013 for European Patent Application No. 06785207.9 filed Jun. 21, 2006. 5 pages.
Eiji Takeda et al. "A New SOI Device-Delta-Structure and Characteristics" IEICE Transactions, Institute of Electronics Information and Comm. Eng. Tokyo, JP, vol. E74, No. 2, Feb. 1, 1991, pp. 360-368, XP000230407 ISSN: 0917-1673, p. 361, paragraph 7-8.
European Office Action of Aug. 1, 2008, for corresponding European Patent Application No. 06785207.9, filed Jun. 21, 2006. 3 pages.
European Office Action of Aug. 13, 2010, for corresponding European Patent Application No. 06785207.9, filed Jun. 21, 2006. 4 pages.
Notice of Allowance of Oct. 29, 2013 for Korean Patent Application No. 10-2008-7001926 filed Jun. 21, 2006. 2 pages.
Singaporean Office Action of Jun. 21, 2010, for corresponding Singaporean Patent Application No. 200718836-0, filed Jun. 21, 2006. 6 pages.
Singaporean Office Action of Mar. 23, 2009, for corresponding Singaporean Patent Application No. 200718836-0, filed Jun. 21, 2006. 8 pages.
Translation of Chinese Office Action of Feb. 6, 2009, for corresponding Chinese Patent Application No. 200680022726.9, filed Jun. 21, 2006. 5 Pages.
Translation of Japanese Office Action of Feb. 19, 2013, for corresponding Japanese Patent Application No. 2008-518327, filed Jun. 21, 2006. 6 pages.
Translation of Japanese Office Action of Feb. 21, 2012, for corresponding Japanese Patent Application No. 2008-518327, filed Jun. 21, 2006. 5 pages.
Translation of Korean Office Action of Apr. 9, 2013 for Korean Patent Application No. 10-2008-7001926 filed Jun. 21, 2006. 4 Pages.
Translation of Korean Office Action of Oct. 10, 2012, for corresponding Korean Patent Application No. 10-2008-7001926, filed Jun. 21, 2006. 5 Pages.
Translation of Taiwanese Office Action of May 27, 2009, for corresponding Taiwanese Patent Application No. 095122787, filed Jun. 23, 2006. 8 pages.
Translation of Taiwanese Office Action of Oct. 28, 2008, for corresponding Taiwanese Patent Application No. 095122787, filed Jun. 23, 2006. 7 pages.
Yan et al., Scaling the Si MOSFET: From Bulk to SOI to Bulk, IEEE Transactions of Electron Devices, vol. 39, No. 7, Jul. 1992, pp. 1704-1710.
US8933508B2 (en) 2015-01-13
WO2007002117A3 (en) 2007-03-15
JP2008547228A (en) 2008-12-25
EP1897134B1 (en) 2014-08-27
EP1897134A2 (en) 2008-03-12
TW200707653A (en) 2007-02-16
US7902598B2 (en) 2011-03-08
TWI360202B (en) 2012-03-11
CN101208795B (en) 2010-05-19
US20110133270A1 (en) 2011-06-09
CN101208795A (en) 2008-06-25
KR101331748B1 (en) 2013-11-20
WO2007002117A2 (en) 2007-01-04
US20130248958A1 (en) 2013-09-26
KR20080026631A (en) 2008-03-25
US20060289919A1 (en) 2006-12-28
US7408218B2 (en) 2008-08-05 Semiconductor device having plural dram memory cells and a logic circuit