Source: https://patents.justia.com/patent/10211182
Timestamp: 2019-10-20 08:23:38
Document Index: 675530660

Matched Legal Cases: ['§ 371', 'Application No. 2016', 'Application No. 104118154', 'Application No. 201480003741', 'Application No. 2016', 'Application No. 2016', 'Application No. 2016', 'Application No. 14870668', 'Application No. 201480003741', 'Application No. 10', 'Application No. 2016', 'Application No. 104118154', 'Application No. 2015', 'Application No. 2016']

US Patent for Package-on-package stacked microelectronic structures Patent (Patent # 10,211,182 issued February 19, 2019) - Justia Patents Search
Justia Patents Passive Components In IcsUS Patent for Package-on-package stacked microelectronic structures Patent (Patent # 10,211,182)
Jul 7, 2014 - Intel
A package-on-package stacked microelectronic structure comprising a pair of microelectronic packages attached to one another in a flipped configuration. In one embodiment, the package-on-package stacked microelectronic structure may comprise a first and a second microelectronic package, each comprising a substrate having at least one package connection bond pad formed on a first surface of each microelectronic package substrate, and each having at least one microelectronic device electrically connected to the each microelectronic package substrate first surface, wherein the first and the second microelectronic package are connected to one another with at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.
This application is a U.S. National Phase application under 35 U.S.C. § 371 of International Application No. PCT/US2014/045560, filed on Jul. 7, 2014, the entire contents of which are hereby incorporated by reference herein.
Embodiments of the present description generally relate to the field of microelectronic package fabrication, and, more particularly, to a microelectronic structure including two microelectronic packages stacked in a flipped configuration.
The microelectronic industry is continually striving to produce ever faster and smaller microelectronic packages for use in various electronic products, including, but not limited to, computer server products and portable products, such as portable computers, electronic tablets, cellular phones, digital cameras, and the like. One route to achieve these goals is the fabrication of stacked packages. On type of package stacking, called Package-on-Package (PoP) stacking, is becoming an important solution for mobile and wireless applications that require small lateral dimensions, low package heights, and high bandwidth between the microelectronic devices within the Package-on-Package stacked structure.
FIGS. 1-7 illustrates cross-sectional views of processes of fabricating a package-on-package stacked microelectronic structure, according to an embodiment of the present description.
FIG. 8 illustrates a cross-sectional view of a package-on-package stacked microelectronic structure, according to another embodiment of the present description.
FIG. 9 illustrates a cross-sectional view of a package-on-package stacked microelectronic structure, according to still another embodiment of the present description.
FIG. 10 illustrates a cross-sectional view of a package-on-package stacked microelectronic structure, according to yet another embodiment of the present description.
FIG. 11 illustrates a top plan view along line A-A of FIG. 3, according to one embodiment of the present description.
FIG. 12 illustrates a top plan view along line A-A of FIG. 3, according to another embodiment of the present description
FIG. 13 is a flow chart of a process of fabricating a package-on-package stacked microelectronic structure, according to an embodiment of the present description.
FIG. 14 illustrates a computing device in accordance with one implementation of the present description.
Embodiments of the present description include a package-on-package stacked microelectronic structure comprising a pair of microelectronic packages attached to one another in a flipped configuration. In one embodiment, the package-on-package stacked microelectronic structure may comprise a first and a second microelectronic package, each comprising a substrate having at least one package connection bond pad formed on a first surface of each microelectronic package substrate, and each having at least one microelectronic device electrically connected to the each microelectronic package substrate first surface, wherein the first and the second microelectronic package are connected to one another with at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.
FIGS. 1-7 illustrate embodiments of the present description wherein a pair of microelectronic packages are attached to one another in a flipped configuration to form a package-on-package stacked microelectronic structure. As shown in FIG. 1, a package substrate 110 may be formed. The package substrate 110 may be any appropriate substrate, such as an interposer or the like, having a first surface 112 and an opposing second surface 114. The package substrate 110 may have a plurality of bond pads, comprising at least one microelectronic device attachment bond pad 122 and at least one package-to-package bond pads 124, formed in or on the package substrate first surface 112, and a plurality of external connection bond pads 126 formed in or on the package substrate second surface 114. The package substrate 110 may comprise a plurality of dielectric layers (not illustrated) having a plurality of conductive routes 116 formed therethrough, wherein the conductive routes 116 may form connections between appropriate bond pads, such as the microelectronic device attachment bond pads 122, the package-to-package bond pads 124, and/or the external connection bond pads 126.
The package substrate 110 may comprise any appropriate dielectric material, including, by not limited to, liquid crystal polymer, epoxy resin, bismaleimide triazine resin, FR4, polyimide materials, and the like. The conductive routes 116 may be formed of any appropriate conductive material, including, but not limited to, copper, silver, gold, nickel, and alloys thereof. It is understood that the package substrate 110 may be formed from any number of dielectric layers, may contain a rigid core (not shown), and may contain active and/or passive microelectronic devices (not shown) formed therein. It is further understood that the conductive routes 116 could form any desired electrical route within the package substrate 110 and/or with additional external components (not shown). It is also understood that solder resist layers (not shown) could be utilized on the package substrate first surface 112 and/or the package substrate second surface 114, as will be understood to those skilled in the art. The processes used for forming the package substrate 110 are well known to those skilled in the art, and for the sake of brevity and conciseness will not be described or illustrated herein.
As shown in FIG. 2, a package interconnection material bump 134 may be formed on each of the package-to-package bond pads 124. The package interconnection material bumps 134 may be formed from any appropriate material, including, but not limited to, reflowable solder.
As shown in FIG. 3, a microelectronic device 142 having an active surface 144 and an opposing back surface 148 may be attached to corresponding microelectronic device attachment bond pads 122 with a plurality of device-to-substrate interconnects 132, in a configuration generally known as a flip-chip or controlled collapse chip connection (“C4”) configuration, to form a microelectronic package 100. The device-to-substrate interconnects 132 may extend between the microelectronic device attachment bond pads 122 and mirror-image bond pads 146 on an active surface 144 of the microelectronic device 142 to form an electrical connection therebetween. It is understood that the microelectronic device bond pads 146 may be in electrical communication with integrated circuitry (not shown) within the microelectronic device 142. The microelectronic device 142 may be any appropriate microelectronic device, including, but not limited to a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit device, and the like.
The device-to-substrate interconnects 132 can be made any appropriate material, including, but not limited to, solders and conductive filled epoxies. Solder materials may include may be any appropriate material, including but not limited to, lead/tin alloys, such as 63% tin/37% lead solder, or lead-free solders, such a pure tin or high tin content alloys (e.g. 90% or more tin), such as tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, and similar alloys. When the microelectronic device 142 is attached to the microelectronic substrate 110 with device-to-substrate interconnects 132 made of solder, the solder is reflowed, either by heat, pressure, and/or sonic energy to secure the solder between the microelectronic device bond pads 146 and the microelectronic device attachment bond pads 122. Additionally, the microelectronic device 142 may be copper pillar based flip chip component which is attached to the substrate 110, as will be understood to those skilled in the art.
As shown in FIG. 4, an electrically-insulating flowable material, such as an underfill material 152 may be disposed between the microelectronic device 142 and the package substrate 110, which substantially encapsulates the device-to-substrate interconnects 132. The underfill material 152 may be used to reduce mechanical stress issues that can arise from thermal expansion mismatch between the microelectronic device 142 and the microelectronic substrate 110. The underfill material 152 may be an epoxy material, including, but not limited to epoxy, cyanoester, silicone, siloxane and phenolic based resins, that has sufficiently low viscosity to be wicked between the microelectronic device 142 and the microelectronic substrate 110 by capillary action when introduced by an underfill material dispenser (not shown), which will be understood to those skilled in the art. The underfill material 152 may be subsequently cured (hardened), such as by heat or radiation. The underfill material 152 may also be a molded material (molded underfill) or similar encapsulation material, which is underfilling and covering the microelectronic device 142 at the same time and is applied in a molding step, as will be discussed.
As shown in FIG. 5, a pair of microelectronic packages, illustrated as first microelectronic package 1001 and second microelectronic package 1002, may be placed in a substantially mirrored position, wherein the first microelectronic package substrate first surface 1121 faces the second microelectronic package substrate first surface 1122, and the package interconnection material bumps (see elements 134 of FIG. 4) of each of the first microelectronic package 1001 and the second microelectronic package 1002 attach to one another to form package-to-package interconnection structures 154. The package-to-package interconnection structures 154 may provide electrical communication routes between the first microelectronic package 1001 and the second microelectronic package 1002. It is noted the like components for the first microelectronic package 1001 and the second microelectronic package 1002 with regard to the components of FIGS. 1-4 are denoted with subscript “1” and subscript “2”, respectively.
The package interconnection material bumps (see elements 134 of FIG. 4) can be made any appropriate material, including, but not limited to, solders and conductive filled epoxies. Solder materials may include may be any appropriate material, including but not limited to, lead/tin alloys, such as 63% tin/37% lead solder, or lead-free solders, such a pure tin or high tin content alloys (e.g. 90% or more tin), such as tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, and similar alloys. When the first microelectronic package 1001 and the second microelectronic package 1002 attach to one another with package interconnection material bumps 134 that are made of solder, the solder is reflowed, either by heat, pressure, and/or sonic energy such that corresponding interconnection material bumps of the first microelectronic package 1001 and the second microelectronic package 1002 combine to form package-to-package interconnection structures 154.
As shown in FIG. 6, an encapsulation material 156 may be disposed between the first microelectronic package 1001 and the second microelectronic package 1042 to form a package-on-package stacked microelectronic structure 180. The encapsulation material 156 may be any appropriate material, such as an epoxy resin, and may provide structural rigidity to the package-on-package stacked microelectronic structure 180, wherein the encapsulation material 156 substantially surrounds the package-to-package interconnection structures 154, the first microelectronic device 1421, and the second microelectronic device 1422.
As shown in FIG. 7, a variety of additional components may be a part of the package-on-package stacked microelectronic structure 180. As illustrated, external interconnects 158 may be attached to the first microelectronic package external connection bond pads 1261 for connecting the package-on-package stacked microelectronic structure 180 to external structures (not shown), such as a motherboard. Furthermore, additional microelectronic devices may be a part of the package-on-package stacked microelectronic structure 180, such as additional microelectronic device 162 attached by additional device interconnects 166 extending between bond pads 164 of the additional microelectronic devices 162 and the second microelectronic package external connection bond pads 1262.
It is understood that the subject matter of the present description is not limited to the structures illustrated in FIGS. 1-7. For example, as shown in FIG. 8, the microelectronic devices need not be attached by flip-chip attachment; rather, for example, the first microelectronic device back surface 1481 may be attached to the first microelectronic package substrate first surface 1121 and bond wires 172 may be formed between the first microelectronic package microelectronic device bond pads 1461 and the first microelectronic package substrate microelectronic device attachment bond pads 1221. Further, the underfill material (illustrated as first underfill material 1521 and/or second underfill material 1522 of FIG. 7) may not be necessary when the encapsulation material 156 is of sufficiently low viscosity to flow between the microelectronic device and the substrate, such as shown in FIG. 7 between the second microelectronic package microelectronic device 1422 and the second microelectronic package substrate 1102 (e.g. a molded underfill material). Moreover, one of the substrates (e.g. elements 1101 and 1102) may be single sided substrate (e.g. bond pads only on one surface), such as a flex tape (e.g. polyimide), a mold body with a redistribution layer, a ceramic material, a laminate, or any other appropriate single side substrate, such as illustrated for second microelectronic package substrate 1102 in FIG. 9. In another embodiment, the first microelectronic package microelectronic device back surface 1481 may be attached to the second microelectronic package microelectronic device back surface 1482 with an adhesive material 174 prior to disposing the encapsulation material 156, as illustrated in FIG. 10.
As shown in FIG. 11, which is a top plan view along line A-A of FIG. 3, the arrangement of the package interconnection material bumps 134 may be such that they substantially surround the microelectronic device 142. In other embodiment shown in FIG. 12, the package interconnection material bumps 134 may be arranged on opposing sides of the microelectronic device 142. It is understood that the arrangements of the package interconnection material bumps 134 in FIGS. 11 and 12 are merely exemplary and any appropriate arrangement may be employed.
FIG. 13 is a flow chart of a process 200 of fabricating a microelectronic structure according to an embodiment of the present description. As set forth in block 202, a first microelectronic package may be formed, comprising a substrate having a first surface and at least one package connection bond pad formed on the each microelectronic package substrate first surface. At least one first microelectronic device may be electrically connected to the microelectronic package substrate first surface, as set forth in block 204. As set forth in block 206, a second microelectronic package may be formed, comprising a substrate having a first surface and at least one package connection bond pad formed on the each microelectronic package substrate first surface. At least one second microelectronic device may be electrically connected to the microelectronic package substrate first surface, as set in block 208. As set forth in block 210, the second microelectronic package first surface may be oriented to face the first microelectronic package first surface. At least one package-to-package interconnection structure may be formed between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad, as set forth in block 212.
FIG. 14 illustrates a computing device 300 in accordance with one implementation of the present description. The computing device 300 houses a board 302. The board 302 may include a number of components, including but not limited to a processor 304 and at least one communication chip 306A, 306B. The processor 304 is physically and electrically coupled to the board 302. In some implementations the at least one communication chip 306A, 306B is also physically and electrically coupled to the board 302. In further implementations, the communication chip 306A, 306B is part of the processor 304.
The communication chip 306A, 306B enables wireless communications for the transfer of data to and from the computing device 300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 306 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 300 may include a plurality of communication chips 306A, 306B. For instance, a first communication chip 306A may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 306B may be dedicated to longer range wireless communications such as GPS EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 304 of the computing device 300 may be included in a package-on-package stacked microelectronic structure, as described above. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Furthermore, the communication chip 306A, 306B may be included in a package-on-package stacked microelectronic structure, as described above.
It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in FIGS. 1-14. The subject matter may be applied to other microelectronic devices and assembly applications, as well as any appropriate electronic application, as will be understood to those skilled in the art.
In Example 1, a package-on-package stacked microelectronic structure may comprise a first microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on the microelectronic package substrate first surface, and having at least one microelectronic device electrically connected to the microelectronic package substrate first surface; a second microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on the each microelectronic package substrate first surface, and having at least one microelectronic device electrically connected to the microelectronic package substrate first surface; and at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.
In Example 2, the subject matter of Example 1 can optionally include an encapsulation material disposed between the first microelectronic package substrate first surface and the second microelectronic package substrate first surface.
In Example 3, the subject matter of Example 1 or 2 can optionally include at least one of the first microelectronic package microelectronic device and the second microelectronic package microelectronic device being attached to its respective substrate with a plurality of interconnects in a flip-chip configuration.
In Example 4, the subject matter of Example 3 can optionally include at least one of a first underfill material disposed between the first microelectronic package microelectronic device and the first microelectronic package substrate, and a second underfill material disposed between the second microelectronic package microelectronic device and the second microelectronic package substrate.
In Example 5, the subject matter of Examples 1 to 2 can optionally include at least one of the first microelectronic package microelectronic device and the second microelectronic package microelectronic device is attached to its respective substrate with a plurality of wirebonds.
In Example 6, the subject matter any of Examples 1 to 4 can optionally include a back surface of the first microelectronic package microelectronic device being attached to a back surface of the second microelectronic package microelectronic device with an adhesive material.
In Example 7, the subject matter of any of Examples 1 to 6 can optionally include the first microelectronic package substrate including a second surface and the second microelectronic package substrate including a second surface, and further including a plurality of external bond pads in or on at least one of the first microelectronic package substrate second surface and the second microelectronic package substrate second surface.
In Example 8, a method of forming a package-on-package stacked microelectronic structure may comprise forming a first microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on the each microelectronic package substrate first surface; electrically connecting at least one first microelectronic device to the microelectronic package substrate first surface; forming a second microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on the each microelectronic package substrate first surface; electrically connecting at least one second microelectronic device to the microelectronic package substrate first surface; orienting the second microelectronic package first surface to face the first microelectronic package first surface; and forming at least one package-to-package interconnection structure between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.
In Example 9, the subject matter of Example 8 can optionally include forming at least one package-to-package interconnection structure between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad comprising forming a package interconnection material bump on its respective first microelectronic package connection bond pad, forming a package interconnection material bump on the second microelectronic package connection bond pad, and attaching the first microelectronic package interconnection material bump with the second microelectronic package interconnection material bump.
In Example 10, the subject matter of Example 9 can optionally include forming the package interconnection material bump on its respective first microelectronic package connection bond pad, forming the package interconnection material bump on the second microelectronic package connection bond pad, and attaching the first microelectronic package interconnection material bump with the second microelectronic package interconnection material bump comprising forming a package interconnection solder bump on its respective first microelectronic package connection bond pad, forming the package interconnection solder bump on the second microelectronic package connection bond pad, and reflowing the first microelectronic package interconnection solder bump with the second microelectronic package interconnection solder bump.
In Example 11, the subject matter of any of Examples 8 to 10 can optionally include disposing an encapsulation material between the first microelectronic package substrate first surface and the second microelectronic package substrate first surface.
In Example 12, the subject matter of any of Examples 8 to 11 can optionally include electrically connecting the first microelectronic device to the microelectronic package substrate first surface comprising electrically connecting the first microelectronic device to the first microelectronic package substrate first surface with a plurality of interconnects in a flip-chip configuration.
In Example 13, the subject matter of Example 12 can optionally include disposing a first underfill material between the first microelectronic package microelectronic device and the first microelectronic package substrate.
In Example 14, the subject matter of any of Example 8 to 13 can optionally include electrically connecting the second microelectronic device to the microelectronic package substrate first surface comprising electrically connecting the second microelectronic device to the second microelectronic package substrate first surface with a plurality of interconnects in a flip-chip configuration.
In Example 15, the subject matter of Example 14 can optionally include disposing a second underfill material between the second microelectronic package microelectronic device and the second microelectronic package substrate.
In Example 16, the subject matter of Example 8 can optionally include at least one of electrically connecting the first microelectronic device to the microelectronic package substrate first surface and electrically connecting the second microelectronic device to the microelectronic package substrate comprises at least one of electrically connecting the first microelectronic device to the first microelectronic package substrate first surface with a plurality of wirebonds and electrically connecting the second microelectronic device to the second microelectronic package substrate first surface with a plurality of wirebonds.
In Example 17, the subject matter of Example 8 can optionally include attaching a back surface of the first microelectronic package microelectronic device to attached to a back surface of the second microelectronic package microelectronic device with an adhesive material.
In Example 18, the subject matter of any of Examples 8 to 17 can optionally include the first microelectronic package substrate including a second surface and the second microelectronic package substrate including a second surface, and further including forming a plurality of external bond pads in or on at least one of the first microelectronic package substrate second surface and the second microelectronic package substrate second surface.
In Example 19, a computing device may comprise a board; and a package-on-package stacked microelectronic structure attached to the board, wherein the package-on-package stacked microelectronic structure comprising a first microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on the microelectronic package substrate first surface, and having at least one microelectronic device electrically connected to the microelectronic package substrate first surface; a second microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on the each microelectronic package substrate first surface, and having at least one microelectronic device electrically connected to the microelectronic package substrate first surface; and at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.
In Example 20, the subject matter of Example 19 can optionally include an encapsulation material disposed between the first microelectronic package substrate first surface and the second microelectronic package substrate first surface.
In Example 21, the subject matter of Examples 19 or 20 can optionally include at least one of the first microelectronic package microelectronic device and the second microelectronic package microelectronic device being attached to its respective substrate with a plurality of interconnects in a flip-chip configuration.
In Example 22, the subject matter of Example 21 can optionally include at least one of a first underfill material disposed between the first microelectronic package microelectronic device and the first microelectronic package substrate, and a second underfill material disposed between the second microelectronic package microelectronic device and the first microelectronic package substrate.
In Example 23, the subject matter of Example 19 or 20 can optionally include at least one of the first microelectronic package microelectronic device and the second microelectronic package microelectronic device being attached to its respective substrate with a plurality of wirebonds.
In Example 24, the subject matter of Example 19 can optionally include a back surface of the first microelectronic package microelectronic device attached to a back surface of the second microelectronic package microelectronic device with an adhesive material.
In Example 25, the subject matter of any of Examples 19 to 24 can optionally include the first microelectronic package substrate including a second surface and the second microelectronic package substrate including a second surface, and further including a plurality of external bond pads in or on at least one of the first microelectronic package substrate second surface and the second microelectronic package substrate second surface.
1. A package-on-package stacked microelectronic structure, comprising:
a first microelectronic package, comprising a substrate having a first surface and a second surface opposite the first surface, and at least one package connection bond pad formed on the microelectronic package substrate first surface, and having at least one microelectronic device electrically connected to the first microelectronic package substrate first surface;
a second microelectronic package, comprising a substrate having a first surface and a second surface opposite the first surface, and at least one package connection bond pad formed on each second microelectronic package substrate first surface, and having at least one microelectronic device electrically connected to the second microelectronic package substrate first surface, and having at least two microelectronic devices electrically connected to the second microelectronic package substrate second surface, the at least two microelectronic devices co-planar with one another on the second microelectronic package substrate second surface, and the at least two microelectronic devices electrically coupled to the at least one microelectronic device of the second microelectronic package by conductive routes through the second microelectronic package substrate, wherein a first of the conductive routes couples a first microelectronic device of the at least two microelectronic devices to a microelectronic device of the at least one microelectronic device, and a second of the conductive routes couples a second microelectronic device of the at least two microelectronic devices to the microelectronic device of the at least one microelectronic device; and
at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.
2. The package-on-package stacked microelectronic structure of claim 1, further including an encapsulation material disposed between the first microelectronic package substrate first surface and the second microelectronic package substrate first surface.
3. The package-on-package stacked microelectronic structure of claim 1, wherein at least one of the first microelectronic package microelectronic device and the second microelectronic package microelectronic device is attached to its respective substrate with a plurality of interconnects in a flip-chip configuration.
4. The package-on-package stacked microelectronic structure of claim 3, further including at least one of a first underfill material disposed between the first microelectronic package microelectronic device and the first microelectronic package substrate, and a second underfill material disposed between the second microelectronic package microelectronic device and the second microelectronic package substrate.
5. The package-on-package stacked microelectronic structure of claim 1, wherein at least one of the first microelectronic package microelectronic device and the second microelectronic package microelectronic device is attached to its respective substrate with a plurality of wirebonds.
6. The package-on-package stacked microelectronic structure of claim 1, wherein a back surface of the first microelectronic package microelectronic device is attached to a back surface of the second microelectronic package microelectronic device with an adhesive material.
7. The package-on-package stacked microelectronic structure of claim 1, wherein the first microelectronic package substrate includes a second surface and the second microelectronic package substrate includes a second surface, and further including a plurality of external bond pads in or on at least one of the first microelectronic package substrate second surface and the second microelectronic package substrate second surface.
8. A method of forming a package-on-package stacked microelectronic structure, comprising:
forming a first microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on each microelectronic package substrate first surface; electrically connecting at least one first microelectronic device to the microelectronic package substrate first surface;
forming a second microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on each microelectronic package substrate first surface;
electrically connecting at least one second microelectronic device to the second microelectronic package substrate first surface;
electrically connecting at least one third microelectronic device and one fourth microelectronic device to the second microelectronic package substrate second surface, the at least one third and one fourth microelectronic devices co-planar with one another on the second microelectronic package substrate second surface, and the at least one third and one fourth microelectronic devices electrically coupled to the at least one second microelectronic device of the second microelectronic package by conductive routes through the second microelectronic package substrate, wherein a first of the conductive routes couples a first microelectronic device of the at least one third and one fourth microelectronic devices to a microelectronic device of the at least one second microelectronic device, and a second of the conductive routes couples a second microelectronic device of the at least one third and one fourth microelectronic devices to the microelectronic device of the at least one second microelectronic device;
orienting the second microelectronic package first surface to face the first microelectronic package first surface; and
forming at least one package-to-package interconnection structure between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.
9. The method of claim 8, wherein forming at least one package-to-package interconnection structure between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad comprises forming a package interconnection material bump on its respective first microelectronic package connection bond pad, forming a package interconnection material bump on the second microelectronic package connection bond pad, and attaching the first microelectronic package interconnection material bump with the second microelectronic package interconnection material bump.
10. The method of claim 9, wherein forming the package interconnection material bump on its respective first microelectronic package connection bond pad, forming the package interconnection material bump on the second microelectronic package connection bond pad, and attaching the first microelectronic package interconnection material bump with the second microelectronic package interconnection material bump comprises forming a package interconnection solder bump on its respective first microelectronic package connection bond pad, forming the package interconnection solder bump on the second microelectronic package connection bond pad, and reflowing the first microelectronic package interconnection solder bump with the second microelectronic package interconnection solder bump.
11. The method of claim 8, further including disposing an encapsulation material between the first microelectronic package substrate first surface and the second microelectronic package substrate first surface.
12. The method of claim 8, wherein electrically connecting the first microelectronic device to the microelectronic package substrate first surface comprises electrically connecting the first microelectronic device to the first microelectronic package substrate first surface with a plurality of interconnects in a flip-chip configuration.
13. The method of claim 12, further including disposing a first underfill material between the first microelectronic package microelectronic device and the first microelectronic package substrate.
14. The method of claim 8, wherein electrically connecting the second microelectronic device to the microelectronic package substrate first surface comprises electrically connecting the second microelectronic device to the second microelectronic package substrate first surface with a plurality of interconnects in a flip-chip configuration.
15. The method of claim 14, further including disposing a second underfill material between the second microelectronic package microelectronic device and the second microelectronic package substrate.
16. The method of claim 8, wherein at least one of electrically connecting the first microelectronic device to the microelectronic package substrate first surface and electrically connecting the second microelectronic device to the microelectronic package substrate comprises at least one of electrically connecting the first microelectronic device to the first microelectronic package substrate first surface with a plurality of wirebonds and electrically connecting the second microelectronic device to the second microelectronic package substrate first surface with a plurality of wirebonds.
17. The method of claim 8, further comprising attaching a back surface of the first microelectronic package microelectronic device to a back surface of the second microelectronic package microelectronic device with an adhesive material.
18. The method of claim 8, wherein the first microelectronic package substrate includes a second surface and the second microelectronic package substrate includes a second surface, and further including forming a plurality of external bond pads in or on at least one of the first microelectronic package substrate second surface and the second microelectronic package substrate second surface.
19. A computing device, comprising: a board; and
a package-on-package stacked microelectronic structure attached to the board, wherein the package-on-package stacked microelectronic structure comprises:
a first microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on the microelectronic package substrate first surface, and having at least one microelectronic device electrically connected to the microelectronic package substrate first surface;
a second microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on the second microelectronic package substrate first surface, and having at least one microelectronic device electrically connected to the second microelectronic package substrate first surface, and having at least two microelectronic devices electrically connected to the second microelectronic package substrate second surface, the at least two microelectronic devices co-planar with one another on the second microelectronic package substrate second surface, and the at least two microelectronic devices electrically coupled to the at least one microelectronic device of the second microelectronic package by conductive routes through the second microelectronic package substrate, wherein a first of the conductive routes couples a first microelectronic device of the at least two microelectronic devices to a microelectronic device of the at least one microelectronic device, and a second of the conductive routes couples a second microelectronic device of the at least two microelectronic devices to the microelectronic device of the at least one microelectronic device; and
20. The computing device of claim 19, further including an encapsulation material disposed between the first microelectronic package substrate first surface and the second microelectronic package substrate first surface.
21. The computing device of claim 19, wherein at least one of the first microelectronic package microelectronic device and the second microelectronic package microelectronic device is attached to its respective substrate with a plurality of interconnects in a flip-chip configuration.
22. The computing device of claim 21, further including at least one of a first underfill material disposed between the first microelectronic package microelectronic device and the first microelectronic package substrate, and a second underfill material disposed between the second microelectronic package microelectronic device and the first microelectronic package substrate.
23. The computing device of claim 19, wherein at least one of the first microelectronic package microelectronic device and the second microelectronic package microelectronic device is attached to it respective substrate with a plurality of wirebonds.
24. The computing device of claim 19, wherein a back surface of the first microelectronic package microelectronic device is attached to a back surface of the second microelectronic package microelectronic device with an adhesive material.
25. The computing device of claim 19, wherein the first microelectronic package substrate includes a second surface and the second microelectronic package substrate includes a second surface, and further including a plurality of external bond pads in or on at least one of the first microelectronic package substrate second surface and the second microelectronic package substrate second surface.
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Patent Publication Number: 20160260689
Inventors: Thorsten Meyer (Regensburg), Gerald Ofner (Regensburg)
Assistant Examiner: Tsz Chu
Application Number: 14/649,104
Current U.S. Class: Passive Components In Ics (257/528)
International Classification: H01L 23/48 (20060101); H01L 21/60 (20060101); H01L 25/065 (20060101); H01L 25/10 (20060101); H01L 21/54 (20060101); H01L 25/00 (20060101); H05K 1/11 (20060101); H01L 23/00 (20060101); H01L 23/538 (20060101); H01L 23/31 (20060101); H01L 23/498 (20060101);