Source: http://www.google.com/patents/US5861642?ie=ISO-8859-1&dq=ininventor:oliver+ininventor:steele
Timestamp: 2015-05-04 14:45:03
Document Index: 344381870

Matched Legal Cases: ['art 203', 'art 204', 'art 204', 'art 203', 'art 203', 'art 204', 'art 203', 'art 204', 'art 203', 'art 204', 'art 204', 'art 204', 'art 204', 'art 203']

Patent US5861642 - Semiconductor device having charge transfer device equipped with three ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe semiconductor device of the present invention is equipped with a plurality of photodiodes, a horizontal transfer part and a vertical transfer part, and in particular, the horizontal transfer part or the vertical transfer part has a configuration described as in the following. Namely, the device has...http://www.google.com/patents/US5861642?utm_source=gb-gplus-sharePatent US5861642 - Semiconductor device having charge transfer device equipped with three semiconductor layers of same conductivity type with mutually different concentrationsAdvanced Patent SearchPublication numberUS5861642 APublication typeGrantApplication numberUS 08/691,393Publication dateJan 19, 1999Filing dateAug 2, 1996Priority dateAug 9, 1995Fee statusLapsedAlso published asEP0762508A2, EP0762508A3Publication number08691393, 691393, US 5861642 A, US 5861642A, US-A-5861642, US5861642 A, US5861642AInventorsYasutaka NakashibaOriginal AssigneeNec CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (2), Classifications (13), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device having charge transfer device equipped with three semiconductor layers of same conductivity type with mutually different concentrations
US 5861642 AAbstract
The semiconductor device of the present invention is equipped with a plurality of photodiodes, a horizontal transfer part and a vertical transfer part, and in particular, the horizontal transfer part or the vertical transfer part has a configuration described as in the following. Namely, the device has a semiconductor region which is formed by regularly and consecutively arranging a plurality of blocks of the same conductivity type, where each of the plurality of the blocks is equipped with three regions of mutually different impurity concentrations, clock pulses are applied to two regions out of the three regions and the voltage of the high level or low level of the clock pulse is applied to the remaining region out of the three regions as a constant potential.
1. A charge transfer device comprising a charge transfer region, having a plurality of sets of regions, each of said sets of regions including:at least three regions, each of said three regions being of a same depth and having impurity concentrations different from one another; a first electrode covering two adjacent regions of said at least three regions; and a second electrode covering a third region of said at least three regions, wherein said first electrode of each of alternate ones of said sets are supplied with a first clock pulse and said first electrode of each of remaining ones of said sets are supplied with a second clock pulse having a phase different than that of said first clock pulse, said first pulse and second clock pulse alternating between a first voltage and a second voltage, wherein said second electrode is supplied with one of said first voltage and said second voltage as a constant power source. 2. A charge transfer device as claimed in claim 1, wherein said three regions comprise:a first semiconductor region having a first impurity concentration; a second semiconductor region having a second impurity concentration lower than said first impurity concentration; and a third semiconductor region having a third impurity concentration lower than said second impurity concentration, said second electrode being positioned on said first semiconductor region and said first electrode being positioned on said second semiconductor region and said third semiconductor region. 3. A charge transfer device as claimed in claim 2, wherein said charge transfer region comprises N-type regions formed by implanting ions into a P-type semiconductor substrate.
4. A charge transfer device as claimed in claim 1, wherein said three regions comprise:a first semiconductor region having a first impurity concentration; a second semiconductor region having a second impurity concentration lower than said first impurity concentration; and a third semiconductor region having a third impurity concentration lower than said second impurity concentration, said second electrode being positioned on said third semiconductor region and said first electrode being positioned on said first semiconductor region and said second semiconductor region. 5. A charge transfer device as claimed in claim 4, wherein said charge transfer region comprises a plurality of N-type regions formed by implanting ions into a P-type semiconductor substrate.
6. A charge transfer device comprising:a plurality of blocks formed consecutively in a semiconductor substrate and comprising a charge transfer path, each of said blocks comprising three regions being of a same depth and having mutually different impurity concentrations; a plurality of first electrodes, each covering two adjacent regions of said three regions, wherein complementary clock signals are supplied to adjacent ones of said plurality of said first electrodes, said complimentary clock signals alternating between a first voltage and a second voltage; and a plurality of second electrodes, each covering a third region of said three regions and being supplied with one of said first voltage and said second voltage as a constant potential. 7. A charge transfer device as claimed in claim 6, wherein said three regions comprise:a first semiconductor region having a first impurity concentration; a second semiconductor region having a second impurity concentration lower than said first impurity concentration; and a third semiconductor region having a third impurity concentration lower than said second impurity concentration; wherein each of said second electrodes are positioned on said first semiconductor region, and wherein each of said first electrodes are positioned on said second semiconductor region and said third semiconductor region. 8. A charge transfer device as claimed in claim 6, wherein said three regions comprise:a first semiconductor region having a first impurity concentration; a second semiconductor region having a second impurity concentration lower than said first impurity concentration; a third semiconductor region having a third impurity concentration lower than said second impurity concentration; wherein each of said second electrodes are positioned on said third semiconductor region, and wherein each of said first electrodes are positioned on said first semiconductor region and said second semiconductor region. 9. A semiconductor device comprising:a plurality of photo-diodes; a vertical transfer part for receiving a plurality of signals from said plurality of photo-diodes and for transferring said signals sequentially; and a horizontal transfer part for receiving said signals transferred from said vertical transfer part and for transferring said signals sequentially to an output terminal, at least one of said horizontal transfer part and said vertical transfer part having a plurality of consecutively arranged blocks, each of said blocks including three semiconductor regions being of a same depth and having a same conductivity type of mutually different impurity concentrations, wherein complementary clock pulses, alternating between a first voltage and a second voltage, are supplied in to even-numbered blocks and odd-numbered blocks of said plurality of blocks, said semiconductor device further comprising a first electrode covering two adjacent semiconductor regions of said three semiconductor regions and being supplied with a clock pulse of said complementary clock pulses; and a second electrode covering a third semiconductor region of said three semiconductor regions and being supplied with one of said first voltage and said second voltage as a constant potential. Description
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a charge transfer device controlled by two driving pulses.
In a solid-state image pickup device such as a charge coupled device (CCD), the electrons produced by a photodiode are utilized as means of conveying image information. In order to transfer the image information to a signal processor such as a display which actually restores the information, a charge transfer device is called for. The charge transfer device is controlled by a control device placed outside of the transfer device. As is well known, the charge transfer device may be referred either to a vertical transfer part or to a horizontal transfer part of a CCD.
For example, the two-phase drive charge transfer device disclosed in Japanese Laid-Open Patent Publication Hei 6-314706 (1994) has the following a structure.
FIG. 1(a) shows the structure of the charge transfer device. The device has an N-type semiconductor layer 2 formed on a P-type semiconductor substrate 1. In the N-type semiconductor layer 2, there are formed N- -type semiconductor regions 6 by a selective ion implantation of, for example, boron. As a result, there are formed alternating regions of N-type and N- -type. A silicon oxide film, that is, an insulating film 3 is formed by thermal oxidation on the N-type semiconductor regions 2 and the N- -type semiconductor regions 6. First electrodes 4 are formed on the insulating film 3 so as to cover each of a part of the N-type semiconductor regions 2. An insulating film 5 is formed on the first electrode. Further, second electrodes 8 are formed so as to cover each of the remaining part of the N-type semiconductor region 2 and a part of each of the N- -type semiconductor regions 6. As shown in FIG. 1(a), the second electrodes 8 are formed consecutively, grouped into two types of even-numbered electrodes 8a and odd-numbered electrodes 8b. The electrodes 8a receive a clock pulse φ1 from a control device while the electrodes 8b receive a clock pulse φ2 from the control device. The first electrodes 4 receive a constant voltage VM.
Next, referring to FIGS. 1(b), 1(c) and 1(d), the operation of the charge transfer device as shown in FIG. 1(a) will be described. The clock pulses φ1 and φ2 are signals that vary complementary with each other as shown in FIG. 2. The constant voltage VM is an inter-mediate potential between the high level and the low level of the clock pulses φ1 and φ2. FIG. 1(b) shows an electric potential diagram of the device at the time tb in FIG. 2. Similarly, FIGS. 1(c) and 1(d) are electrical potential diagrams at the times tc and td, respectively, in FIG. 2. In the description that follows it will be assumed that the charge transfer device illustrated by FIG. 1(a) represents a horizontal transfer part of a CCD.
At the time tb, a high level voltage VH is applied to the electrodes 8a and a low level voltage VL is applied to the electrodes 8b. In this situation, the transfer of a signal charge 110 transferred from a vertical transfer part of the CCD will now be described.
In this case, signal charges 110 are accumulated in the N-type semiconductor regions 2 covered with the electrodes 8a. This is because the electrodes 8a are receiving the high level voltage VH, and hence their electric potential is the deepest.
At the time tc, the electric potential of the semiconductor regions covered with the electrodes 8a becomes shallow and the electric potential of the semiconductor regions covered with the electrodes 8b becomes deep, due to variations in the potentials of the clock pulses φ1 and φ2. The situation is as illustrated in FIG. 1(c).
At the time td, the low level voltage VL is applied to the electrodes 8a and the high level voltage VH is applied to the electrodes 8b. In comparison to the situation at the time tc, the electric potential of the semiconductor regions covered with the electrodes 8a becomes shallower and the electric potential of the semiconductor regions covered with the electrodes 8b becomes deeper. Accordingly, the signal charges 110 accumulated at the time tb in the N-type semiconductor regions 2 covered with the electrodes 8a make transitions at the time td as indicated by the arrow in FIG. 1(d). That is, the charges, are accumulated in the N-type semiconductor regions 2 covered with the electrodes 8b.
Thereafter, the signal charges 110 are transferred sequentially by the repetition of the above operation.
However, a CCD chip with the conventional charge transfer device built in requires a constant voltage VM which is different from the voltages VH and VL that can be taken by the clock pulses φ1 and φ2. Hence, it is necessary to install a constant voltage generator which generates the constant voltage VM by processing a power supply voltage, on the outside or inside of the chip. When the constant voltage generator is installed within the chip, the CCD chip will necessarily become large sized. On the contrary, when the constant voltage generator is installed outside the chip, it becomes necessary to furnish terminals to receive the constant voltage on the CCD chip, which will also hamper the miniaturization of the chip.
It is the object of the present invention to provide a semiconductor device equipped with a charge transfer device which makes it possible to miniaturize the chip.
The semiconductor device according to this invention includes a plurality of photodiodes, a horizontal transfer part and a vertical transfer part, and in particular, the horizontal transfer part and the vertical transfer part have the following configuration. Namely, the device has a semiconductor region which is formed by regularly and consecutively arranging a plurality of blocks of the same conductivity type, where each of the plurality of blocks is equipped with three regions having mutually different impurity concentrations. Clock pulses are applied to two of the three regions, and the voltage of the high level or the low level of the clock pulses is applied to the remaining one of the three regions as a constant potential.
Consequently, according to the configuration of this invention two voltage levels suffice for the charge transfer operation in contrast to the requirement of three voltage levels in the conventional charge transfer. Hence, the semiconductor device having the charge transfer device according to this invention will make it possible to reduce the number of terminals compared with the conventional semiconductor device.
FIGS. 1(a)-1(d) shows a structure and potential diagrams of a charge transfer device of the prior art;
FIG. 2 is a waveform diagram of the clock pulses used in the prior art;
FIG. 3 is an example of semiconductor device in which the charge transfer device according to this invention is employed;
FIG. 4 is a plan view of the charge transfer device showing a first embodiment of this invention;
FIGS. 5(a)-5(d) shows a structure and potential diagrams of the charge transfer device of the first embodiment of this invention;
FIG. 6 is a waveform diagram of the clock pulses used in this invention;
FIGS. 7(a)-7(e) shows diagrams for manufacturing the charge transfer device of the first embodiment according to this invention;
FIGS. 8(a)-8(d) shows a structure and potential diagrams of the charge transfer device of a second embodiment according to this invention; and
FIGS. 9(a)-9(e) shows diagrams for manufacturing the charge transfer device of the second embodiment according to this invention.
FIG. 3 is a diagram showing an embodiment of the semiconductor device of this invention. This semiconductor device is constituted of a single chip 201. Signal charge from a plurality of photodiodes 202 is transferred by a vertical transfer part 203 to a horizontal transfer part 204. The horizontal transfer part 204 sequentially transfers signal charges transferred from the vertical transfer part 203 to an output circuit 205. The output circuit 205 outputs the received signal charges as a serial signal from an output terminal 206. The vertical transfer part 203 and the horizontal transfer part 204 are two-phase drive type charge transfer device. Consequently, the vertical transfer part 203 is driven by receiving mutually complementary clock pulses φV1 and φV2 from clock input terminals 208. The horizontal transfer device 204 is driven by receiving mutually complementary clock pulses φH1 and φH2 from clock input terminals 207. The clock pulses φV1, φV2, 100 H1, and φH2 are generated by a control circuit installed outside the chip 201. Such a control device controls not only the drive of the chip 201, but also other devices such as a display which displays the signal output from the output terminal 206 as an image signal.
A plan view of a specific configuration of the horizontal transfer device 204 is shown in FIG. 4. Besides, a sectional view along a line I-I' in FIG. 4 is shown in FIG. 5(a). On a P-type semiconductor substrate 1 there is formed an N-type semiconductor layer 2 by ion implantation. N- -type semiconductor regions 6 and N-- -type semiconductor regions 7 are formed by further selective ion implantations. In other words, differing from the conventional example, this embodiment includes three kinds of N-type semiconductor layers with mutually different impurity concentrations.
A silicon oxide film, namely, an insulating film 3, is formed by thermal oxidation on the N-type semiconductor regions 2, N- -type semiconductor regions 6 and N-- -type semiconductor regions 7. On the insulating film 3 there are formed first electrodes 4 so as to cover a part of each of the N-type semiconductor regions 2. Further, second electrodes 8 are formed so as to cover a part of each of the N- -type regions 6 and a part of each of the N-- -type regions 7. As shown in FIG. 4 and FIG. 5(a), the second electrodes 8 are formed consecutively, with two types of even-numbered electrodes 8a and odd-numbered electrodes 8b. The electrodes 8a receive a clock pulse φH1 and the electrodes 8b receive a clock pulse φH2. A constant voltage VL which is equal to the low level voltage of the clock pulses φH1 and φH2 is applied to the first electrodes 4.
Referring to FIGS. 5(b), 5(c) and 5(d), the operation of the horizontal transfer part 204 shown in FIG. 5(a) will be described. The clock pulses φH1 and φH2 are signals that vary in complementary fashion which take on respectively a high level voltage VH and a low level voltage VL alternately. FIG. 5(b), 5(c) and 5(d) are electric potential diagrams at the times tb, tc and td, respectively, in FIG. 6.
At the time tb, the high level voltage VH is applied to the electrodes 8a, and the low level voltage VL is applied to the electrodes 8b. How a signal charge 110 transferred from the vertical transfer part 203 is further transferred in this situation will be described next.
In this case, signal charges are accumulated in the N- -type semiconductor regions 6 covered with the electrodes 8a. This is because the electrodes 8a receive the high level voltage VH, and hence their electric potential is the deepest.
At the time tc, the electric potential of the semiconductor regions covered with the electrodes 8a becomes shallow, and the electric potential of the semiconductor regions covered with the electrodes 8b become deep due to variations in the potential of the clock pulses φH1 and φH2. The situation is as illustrated in FIG. 5(c).
At the time td, the low level voltage VL is applied to the electrodes 8a and the high level voltage VH is applied to the electrodes 8b. As a result, the electric potential of the semiconductor regions covered with the electrodes 8a becomes shallower and the electric potential of the semiconductor regions covered with the electrodes 8b becomes deeper, compared with the situation at the time tc. Consequently, the signal charges 110 accumulated in the N- -type semiconductor regions 6 covered with the electrodes 8a at the time tb make transitions at the time td as shown by an arrow in FIG. 5(d). In other words, the signal charges 110 are all moved to the N- -type semiconductor regions 6 covered with the electrodes 8b, and accumulated there.
Thereafter, the signal charges 110 are transferred sequentially by repeating the above operation.
Next, referring to FIGS. 7(a)-7(e), a method of manufacturing the horizontal transfer part 204 will be described.
An N-type semiconductor layer 2 is formed by implanting ions of an N-type impurity such as phosphorus to a concentration of about 1017 cm-3 into a P-type semiconductor substrate 1 with impurity concentration of about 1015 cm-3. Next, an insulating film 3 is formed by thermally oxidizing the N-type semiconductor layer 2. Then, first electrodes 4 are formed selectively by photolithography (FIG. 7(a)).
Next, ions of a P-type impurity such as boron are implanted using the first electrodes 4 as masks. As a result, N- -type semiconductor layers 6 with impurity concentration of about 0.8�1017 cm-3 are formed in self-aligned fashion (FIG. 7(b)).
Ions of a P-type impurity such as boron are further implanted using photoresists 10 and one end of each of the first electrodes 4 as masks. As a result, N-- -type semiconductor layers 7 with impurity concentration of about 0.6�1017 cm-3 are formed self-aligned with one end of each of the first electrodes 4 (FIG. 7(c)).
Next, following removal of the insulating film 3 once, an insulating film 5 is formed again by thermal oxidation. Subsequently, second electrodes 8 are formed and respective electrodes are connected with wirings, completing the horizontal transfer part 204 (FIGS. 7(d) and 7(e)).
The present embodiment includes three kinds of N-type semiconductor layers, namely, an N-type semiconductor layer 2, an N- -type semiconductor layer 6 and an N-- -type semiconductor layer 7. Consequently, electric potentials similar to those of the prior art can be obtained even without the use of a voltage intermediate between the high level voltage VH and the low level voltage VL required by the prior art. What needs be pointed out here is the fact that the electric potential ψM1 formed in the N-type semiconductor layers 2 directly below the first electrodes 4 is shallower than the electric potential ψH, formed in the N-- -type semiconductor layers 7 by the high level voltage VH applied to the electrodes 8a, and that the electric potential ψM1 is deeper than the electric potential ψL formed in the N- -type semiconductor layer 6 by the low level voltage VL applied to the electrodes 8b. In other words, the intended charge transfer operation becomes feasible by virtue of the validity of such a relation among the electric potentials.
According to the configuration of this embodiment, the constitution of the device can be made simpler and the number of terminals can be reduced if, for example, the ground potential is taken as the low level voltage VL. Besides, the horizontal transfer part 204 is described in this embodiment, but the configuration of the horizontal transfer part 204 can also be applied to the vertical transfer part 203. In other words, it can be applied to all types of devices having the function of transferring the signal charges.
Next, referring to FIGS. 8(a)-8(d), a second embodiment of this invention will be described. In the first embodiment of the charge transfer part, three kinds of semiconductor layers, namely, an N-type semiconductor layer, an N- -type semiconductor layer and an N-- -type semiconductor layer are formed. In this embodiment, however, three kinds of semiconductor layers, namely, an N-type semiconductor layer, an N++ -type semiconductor layer and an N+ -type semiconductor layer will be formed. A specific configuration is shown in FIG. 8(a) in which component parts identical to those of FIG. 5(a) are given identical numbers. Accordingly, the difference in the configurations of FIG. 8(a) and FIG. 5(a) resides in the fact that an N++ -type semiconductor layer 12 and an N- -type semiconductor layer 11 are formed in FIG. 8(a) in place of the N- -type semiconductor layer 6 and the N-- -type semiconductor layer 7 in FIG. 5(a). In the configuration shown in FIG. 8(a), a constant voltage VH which is the voltage equal to the high level voltage of the clock pulses φH1 and φH2 is applied to the first electrodes 4.
A method of manufacturing the second embodiment is shown in FIGS. 9(a)-9(e) where the component parts identical to those in FIGS. 7(a)-7(e) are given identical numbers.
An N-type semiconductor layer 2 is formed by implantating ions of an N-type impurity such as phosphorus to a concentration of about 1017 cm-3 into a P-type semiconductor substrate with impurity concentration of about 1015 cm-3. Next, an insulating film 3 is formed by thermally oxidizing the surface of the N-type semiconductor layer 2. Following that, first electrodes 4 are formed selectively by photolithography (FIG. 9(a)).
Next, N+ -type semiconductor layers 11 with impurity concentration of about 1.2�1017 cm-3 are formed in self-aligned fashion by implanting ions of an N-type impurity such as phosphorus by using the first electrodes 4 as masks (FIG. 9(b)).
By a further implantation of an N-type impurity such as phosphorus using photoresists 10 and one end of each of the first electrodes 4 as masks, N++ -type semiconductor layers 12 with impurity concentration of about 1.4�1017 cm-3 are formed in self-alignment with one end of each of the first electrodes 4 (FIG. 9(c)).
Next, after removal of the insulating film 3 once, an insulating film 5 is formed again by thermal oxidation. Following that second electrodes 8 are formed and respective electrodes are connected to wirings, completing the horizontal transfer part (FIGS. 9(d) and 9(e)).
In this embodiment, electric potentials suitable for charge transfer can be obtained as shown in FIGS. 8(b), 8(c) and 8(d). Besides, the description about the operation shown in FIGS. 8(b), 8(c) and 8(d) will be omitted since it is similar to that of FIGS. 7(a)-7(e).
In the first and the second embodiment of this invention, an embedded charge transfer device formed within a P-type semiconductor substrate has been disclosed, but an N-type semiconductor substrate may be used instead. Namely, the conductivity types indicated in FIG. 5(a) and FIG. 8(a) may respectively be changed to corresponding opposite conductivity types. Moreover, the N-type semiconductor layer 2 in FIG. 7(a) and FIG. 9(a) is assumed to be formed by ion implantation, but it may be grown epitaxially on the P-type semiconductor substrate. Furthermore, the present invention may be applied to a surface type charge transfer device without being limited to the embedded type charge transfer device provided that a configuration similar to the scope of this invention is obtainable. In other words, a surface type charge transfer device can be obtained if three semiconductor layers with mutually different concentrations can be secured by implantations of impurities having the conductivity type same as that of the substrate, and electric potentials complying with the scope of this invention can be obtained.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4621369 *Oct 20, 1983Nov 4, 1986Sony CorporationInput circuit for charge transfer deviceUS5286987 *Nov 26, 1991Feb 15, 1994Sharp Kabushiki KaishaCharge transfer deviceUS5289022 *May 13, 1992Feb 22, 1994Sony CorporationCCD shift register having a plurality of storage regions and transfer regions thereinUS5315137 *Nov 12, 1991May 24, 1994Matsushita Electronics CorporationCharge transfer device, process for its manufacture, and method of driving the device* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5986296 *Nov 13, 1998Nov 16, 1999Thomson-CsfCCD type semiconductor deviceUS6380005 *Apr 7, 2000Apr 30, 2002Nec CorporationCharge transfer device and method for manufacturing the same* Cited by examinerClassifications U.S. Classification257/221, 257/227, 257/219, 438/60, 257/E27.154, 257/246, 257/236, 438/75International ClassificationH01L27/148, H01L21/339, H01L29/762Cooperative ClassificationH01L27/14831European ClassificationH01L27/148CLegal EventsDateCodeEventDescriptionMar 20, 2007FPExpired due to failure to pay maintenance feeEffective date: 20070119Jan 19, 2007LAPSLapse for failure to pay maintenance feesAug 9, 2006REMIMaintenance fee reminder mailedJun 27, 2002FPAYFee paymentYear of fee payment: 4Aug 2, 1996ASAssignmentOwner name: NEC CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NAKASHIBA, YASUTAKA;REEL/FRAME:008413/0127Effective date: 19960731RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services