Source: http://www.google.com/patents/US5528238?dq=6480844
Timestamp: 2014-03-14 21:48:57
Document Index: 519981079

Matched Legal Cases: ['art1', 'art2', 'art3', 'art4', 'art4', 'art3', 'art2', 'art1', 'art1', 'art2', 'art3', 'art4']

Patent US5528238 - Process, apparatus and system for decoding variable-length encoded signals - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA fixed-length signal is retrieved from a bitstream comprising one or more variable-length encoded signals. A variable-length encoded signal of the bitstream is decoded to generate a decoded signal corresponding to the fixed-length signal by accessing one or more tables in accordance with the fixed-length...http://www.google.com/patents/US5528238?utm_source=gb-gplus-sharePatent US5528238 - Process, apparatus and system for decoding variable-length encoded signalsAdvanced Patent SearchPublication numberUS5528238 APublication typeGrantApplication numberUS 08/234,785Publication dateJun 18, 1996Filing dateApr 28, 1994Priority dateNov 24, 1993Fee statusPaidPublication number08234785, 234785, US 5528238 A, US 5528238A, US-A-5528238, US5528238 A, US5528238AInventorsBrian NickersonOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (1), Referenced by (15), Classifications (104), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetProcess, apparatus and system for decoding variable-length encoded signalsUS 5528238 AAbstract A fixed-length signal is retrieved from a bitstream comprising one or more variable-length encoded signals. A variable-length encoded signal of the bitstream is decoded to generate a decoded signal corresponding to the fixed-length signal by accessing one or more tables in accordance with the fixed-length signal to retrieve a contribution, an input pointer flag, an output pointer flag, and a next state.
What is claimed is: 1. A computer-implemented process for decoding variable-length encoded signals, comprising the steps of:(a) retrieving a fixed-length signal from a bitstream comprising one or more variable-length encoded signals; and (b) decoding a variable-length encoded signal of the bitstream to generate a decoded signal corresponding to the fixed-length signal by accessing one or more tables in accordance with the fixed-length signal to retrieve a contribution, an input pointer flag, an output pointer flag, and a next state, wherein:step (a) comprises the steps of: (1) initializing an input pointer, an output pointer, a current state, and an accumulator; and (2) retrieving the fixed-length signal from the bitstream in accordance with the input pointer; andstep (b) comprises the steps of: (1) masking the fixed-length signal in accordance with the current state to generate a masked signal; (2) retrieving the contribution from the one or more tables in accordance with the masked signal and the current state; (3) updating the accumulator in accordance with the contribution to generate the decoded signal; (4) transmitting the decoded signal to an output stream in accordance with the output pointer; (5) retrieving the input pointer flag from the one or more tables in accordance with the masked signal and the current state; (6) incrementing the input pointer if indicated by the input pointer flag; (7) retrieving the output pointer flag from the one or more tables in accordance with the masked signal and the current state; (8) incrementing the output pointer if indicated by the output pointer flag; (9) initializing the accumulator if indicated by the output pointer flag; (10) retrieving the next state from the one or more tables in accordance with the masked signal and the current state; and (11) updating the current state in accordance with the next state; and further comprising the step of repeating steps (a)(2) and (b)(1) through (b)(11) to decode the bitstream. 2. The process of claim 1, wherein the bitstream comprises Huffman-encoded macroblock signals and Huffman-encoded block signals, wherein the macroblock signals and blocks signals correspond to a plurality of video frames.
3. The process of claim 2, wherein the decoded signal corresponds to a decoded macroblock signal.
4. The process of claim 2, wherein the decoded signal corresponds to a decoded block signal.
5. The process of claim 2, wherein the one or more tables correspond to eleven macroblock states and twenty block states.
6. The process of claim 5, wherein: the eleven macroblock states comprise:(1) an MPrefixAt0 state; (2) an MPrefixAt2 state; (3) an MPrefixAt4 state; (4) an MPrefixAt6 state; (5) an MGot2Prefix state; (6) an MNeed2Code state; (7) an MNeed4Code state; (8) an MNeed2Non0 state; (9) an MNeed2Non1 state; (10) an MNeed4Non0 state; and (11) an MNeed4Non1 state; andthe twenty block states comprise: (1) a BPrefixAt0 state; (2) a BPrefixAt2 state; (3) a BPrefixAt4 state; (4) a BPrefixAt6 state; (5) a BGot2Prefix state; (6) a BGot4Prefix state; (7) a BGot8PAt4 state; (8) a BGot6Prefix state; (9) a BGot8Prefix state; (10) a BNeed2Code state; (11) a BNeed4Code state; (12) a BNeed6Code state; (13) a BNeed2At4 state; (14) a BNeed4At4 state; (15) a BNeed6At4 state; (16) a BEnd state; (17) a BlkDataAt0 state; (18) a BlkDataAt2 state; (19) a BlkDataAt4 state; and (20) a BlkDataAt6 state. 7. An apparatus for decoding variable-length encoded signals, comprising:(a) means for retrieving a fixed-length signal from a bitstream comprising one or more variable-length encoded signals; and (b) means for decoding a variable-length encoded signal of the bitstream to generate a decoded signal corresponding to the fixed-length signal by accessing one or more tables in accordance with the fixed-length signal to retrieve a contribution, an input pointer flag, an output pointer flag, and a next state, wherein:means (a) comprises: (1) means for initializing an input pointer, an output pointer, a current state, and an accumulator; and (2) means for retrieving the fixed-length signal from the bitstream in accordance with the input pointer; andmeans (b) comprises: (1) means for masking the fixed-length signal in accordance with the current state to generate a masked signal; (2) means for retrieving the contribution from the one or more tables in accordance with the masked signal and the current state; (3) means for updating the accumulator in accordance with the contribution to generate the decoded signal; (4) means for transmitting the decoded signal to an output stream in accordance with the output pointer; (5) means for retrieving the input pointer flag from the one or more tables in accordance with the masked signal and the current state; (6) means for incrementing the input pointer if indicated by the input pointer flag; (7) means for retrieving the output pointer flag from the one or more tables in accordance with the masked signal and the current state; (8) means for incrementing the output pointer if indicated by the output pointer flag; (9) means for initializing the accumulator if indicated by the output pointer flag; (10) means for retrieving the next state from the one or more tables in accordance with the masked signal and the current state; and (11) means for updating the current state in accordance with the next state; and further comprising means for repeating the operation of means (a)(2) and (b)(1) through (b)(1) to decode the bitstream. 8. The apparatus of claim 7, wherein the bitstream comprises Huffman-encoded macroblock signals and Huffman-encoded block signals, wherein the macroblock signals and blocks signals correspond to a plurality of video frames.
9. The apparatus of claim 8, wherein the decoded signal corresponds to a decoded macroblock signal.
10. The apparatus of claim 8, wherein the decoded signal corresponds to a decoded block signal.
11. The apparatus of claim 8, wherein the one or more tables correspond to eleven macroblock states and twenty block states.
12. The apparatus of claim 11, wherein: the eleven macroblock states comprise:(1) an MPrefixAt0 state; (2) an MPrefixAt2 state; (3) an MPrefixAt4 state; (4) an MPrefixAt6 state; (5) an MGot2Prefix state; (6) an MNeed2Code state; (7) an MNeed4Code state; (8) an MNeed2Non0 state; (9) an MNeed2Non1 state; (10) an MNeed4Non0 state; and (11) an MNeed4Non1 state; andthe twenty block states comprise: (1) a BPrefixAt0 state; (2) a BPrefixAt2 state; (3) a BPrefixAt4 state; (4) a BPrefixAt6 state; (5) a BGot2Prefix state; (6) a BGot4Prefix state; (7) a BGot8PAt4 state; (8) a BGot6Prefix state; (9) a BGot8Prefix state; (10) a BNeed2Code state; (11) a BNeed4Code state; (12) a BNeed6Code state; (13) a BNeed2At4 state; (14) a BNeed4At4 state; (15) a BNeed6At4 state; (16) a BEnd state; (17) a BlkDataAt0 state; (18) a BlkDataAt2 state; (19) a BlkDataAt4 state; and (20) a BlkDataAt6 state. 13. The apparatus of claim 7, wherein the apparatus comprises a host processor.
14. A system for decoding variable-length encoded signals, comprising:(a) a monitor; and (b) a conferencing system for:(1) retrieving a fixed-length signal from a bitstream comprising one or more variable-length encoded signals, wherein:the bitstream comprises Huffman-encoded macroblock signals and Huffman-encoded block signals; and the macroblock signals and blocks signals correspond to a plurality of video frames; (2) decoding a variable-length encoded signal of the bitstream to generate a decoded signal corresponding to the fixed-length signal by accessing one or more tables in accordance with the fixed-length signal to retrieve a contribution, an input pointer flag, an output pointer flag, and a next state; and (3) transmitting the decoded signal to the monitor for display. 15. The system of claim 14, wherein:the conferencing system:initializes an input pointer, an output pointer, a current state, and an accumulator; retrieves the fixed-length signal from the bitstream in accordance with the input pointer; masks the fixed-length signal in accordance with the current state to generate a masked signal; retrieves the contribution from the one or more tables in accordance with the masked signal and the current state; updates the accumulator in accordance with the contribution to generate the decoded signal; transmits the decoded signal to an output stream in accordance with the output pointer; retrieves the input pointer flag from the one or more tables in accordance with the masked signal and the current state; increments the input pointer if indicated by the input pointer flag; retrieves the output pointer flag from the one or more tables in accordance with the masked signal and the current state; increments the output pointer if indicated by the output pointer flag; initializes the accumulator if indicated by the output pointer flag; retrieves the next state from the one or more tables in accordance with the masked signal and the current state; and updates the current state in accordance with the next state. 16. The system of claim 14, wherein the decoded signal corresponds to a decoded macroblock signal.
17. The system of claim 14, wherein the decoded signal corresponds to a decoded block signal.
18. The system of claim 14, wherein the one or more tables correspond to eleven macroblock states and twenty block states.
19. The system of claim 18, wherein:the eleven macroblock states comprise: (1) an MPrefixAt0 state; (2) an MPrefixAt2 state; (3) an MPrefixAt4 state; (4) an MPrefixAt6 state; (5) an MGot2Prefix state; (6) an MNeed2Code state: (7) an MNeed4Code state; (8) an MNeed2Non0 state; (9) an MNeed2Non1 state; (10) an MNeed4Non0 state; and (11) an MNeed4Non1 state; andthe twenty block states comprise: (1) a BPrefixAt0 state; (2) a BPrefixAt2 state; (3) a BPrefixAt4 state; (4) a BPrefixAt6 state; (5) a BGot2Prefix state; (6) a BGot4Prefix state; (7) a BGot8PAt4 state; (8) a BGot6Prefix state; (9) a BGot8Prefix state; (10) a BNeed2Code state; (11) a BNeed4Code state; (12) a BNeed6Code state; (13) a BNeed2At4 state; (14) a BNeed4At4 state; (15) a BNeed6At4 state; (16) a BEnd state; (17) a BlkDataAt0 state; (18) a BlkDataAt2 state; (19) a BlkDataAt4 state; and (20) a BlkDataAt6 state. 20. The system of claim 14, wherein the conferencing system comprises a host processor for decoding the variable-length encoded signal to generate the decoded signal.
21. A storage medium encoded with machine-readable computer program code for decoding variable-length encoded signals, comprising:(a) means for causing a computer to retrieve a fixed-length signal from a bitstream comprising one or more variable-length encoded signals; and (b) means for causing the computer to decode a variable-length encoded signal of the bitstream to generate a decoded signal corresponding to the fixed-length signal by accessing one or more tables in accordance with the fixed-length signal to retrieve a contribution, an input pointer flag, an output pointer flag, and a next state, wherein:means (a) comprises means for causing the computer to: (1) initialize an input pointer, an output pointer, a current state, and an accumulator; and (2) retrieve the fixed-length signal from the bitstream in accordance with the input pointer; andmeans (b) comprises means for causing the computer to: (1) mask the fixed-length signal in accordance with the current state to generate a masked signal; (2) retrieve the contribution from the one or more tables in accordance with the masked signal and the current state; (3) update the accumulator in accordance with the contribution to generate the decoded signal; (4) transmit the decoded signal to an output stream in accordance with the output pointer; (5) retrieve the input pointer flag from the one or more tables in accordance with the masked signal and the current state; (6) increment the input pointer if indicated by the input pointer flag; (7) retrieve the output pointer flag from the one or more tables in accordance with the masked signal and the current state; (8) increment the output pointer if indicated by the output pointer flag; (9) initialize the accumulator if indicated by the output pointer flag; (10) retrieve the next state from the one or more tables in accordance with the masked signal and the current state; and (11) update the current state in accordance with the next state; and further comprising means for repeating the operations of means (a)(2) and (b)(1) through (b)(11) to decode the bitstream. 22. A computer-implemented process for decoding variable-length encoded signals, comprising the steps of:(a) retrieving a fixed-length signal from a bitstream comprising one or more variable-length encoded signals, wherein the fixed-length signal comprises at least two bits; (b) generating a multi-bit index from the fixed-length signal, wherein the multi-bit index comprises at least two bits; and (c) decoding a variable-length encoded signal of the bitstream to generate a decoded signal corresponding to the fixed-length signal by accessing one or more tables using the multi-bit index to retrieve a contribution, an input pointer flag, an output pointer flag, and a next state. 23. The process of claim 22, wherein step (b) comprises the step of masking the fixed-length signal in accordance with a current state to generate the multi-bit index.
24. The process of claim 23, wherein:step (a) comprises the steps of: (1) initializing an input pointer, an output pointer, the current state, and an accumulator; and (2) retrieving the fixed-length signal from the bitstream in accordance with the input pointer; andstep (c) comprises the steps of: (1) retrieving the contribution from the one or more tables in accordance with the multi-bit index and the current state; (2) updating the accumulator in accordance with the contribution to generate the decoded signal; (3) transmitting the decoded signal to an output stream in accordance with the output pointer; (4) retrieving the input pointer flag from the one or more tables in accordance with the masked signal and the current state; (5) incrementing the input pointer if indicated by the input pointer flag; (6) retrieving the output pointer flag from the one or more tables in accordance with the masked signal and the current state; (7) incrementing the output pointer if indicated by the output pointer flag; (8) initializing the accumulator if indicated by the output pointer flag; (9) retrieving the next state from the one or more tables in accordance with the masked signal and the current state; and (10) updating the current state in accordance with the next state. 25. The process of claim 22, wherein the variable-length encoded signals are encoded video signals.
26. An apparatus for decoding variable-length encoded signals, comprising:(a) means for retrieving a fixed-length signal from a bitstream comprising one or more variable-length encoded signals, wherein the fixed-length signal comprises at least two bits; (b) means for generating a multi-bit index from the fixed-length signal, wherein the multi-bit index comprises at least two bits; and (c) means for decoding a variable-length encoded signal of the bitstream to generate a decoded signal corresponding to the fixed-length signal by accessing one or more tables using the multi-bit index to retrieve a contribution, an input pointer flag, an output pointer flag, and a next state. 27. The apparatus of claim 26, wherein means (b) masks the fixed-length signal in accordance with a current state to generate the multi-bit index.
28. The apparatus of claim 27, wherein:means (a): (1) initializes an input pointer, an output pointer, the current state, and an accumulator; and (2) retrieves the fixed-length signal from the bitstream in accordance with the input pointer; andmeans (c): (1) retrieves the contribution from the one or more tables in accordance with the multi-bit index and the current state; (2) updates the accumulator in accordance with the contribution to generate the decoded signal; (3) transmits the decoded signal to an output stream in accordance with the output pointer; (4) retrieves the input pointer flag from the one or more tables in accordance with the masked signal and the current state; (5) increments the input pointer if indicated by the input pointer flag; (6) retrieves the output pointer flag from the one or more tables in accordance with the masked signal and the current state; (7) increments the output pointer if indicated by the output pointer flag; (8) initializes the accumulator if indicated by the output pointer flag; (9) retrieves the next state from the one or more tables in accordance with the masked signal and the current state; and (10) updates the current state in accordance with the next state. 29. The apparatus of claim 26, wherein the variable-length encoded signals are encoded video signals.
30. A storage medium encoded with machine-readable computer program code for decoding variable-length encoded signals, comprising:(a) means for causing a computer to retrieve a fixed-length signal from a bitstream comprising one or more variable-length encoded signals, wherein the fixed-length signal comprises at least two bits; (b) means for causing the computer to generate a multi-bit index from the fixed-length signal, wherein the multi-bit index comprises at least two bits; and (c) means for causing the computer to decode a variable-length encoded signal of the bitstream to generate a decoded signal corresponding to the fixed-length signal by accessing one or more tables using the multi-bit index to retrieve a contribution, an input pointer flag, an output pointer flag, and a next state. 31. The storage medium of claim 30, wherein means (b) causes the computer to mask the fixed-length signal in accordance with a current state to generate the multi-bit index.
32. The storage medium of claim 31, wherein:means (a) causes the computer to: (1) initialize an input pointer, an output pointer, the current state, and an accumulator; and (2) retrieve the fixed-length signal from the bitstream in accordance with the input pointer; andmeans (c) causes the computer to: (1) retrieve the contribution from the one or more tables in accordance with the multi-bit index and the current state; (2) update the accumulator in accordance with the contribution to generate the decoded signal; (3) transmit the decoded signal to an output stream in accordance with the output pointer; (4) retrieve the input pointer flag from the one or more tables in accordance with the masked signal and the current state; (5) increment the input pointer if indicated by the input pointer flag; (6) retrieve the output pointer flag from the one or more tables in accordance with the masked signal and the current state; (7) increment the output pointer if indicated by the output pointer flag; (8) initialize the accumulator if indicated by the output pointer flag; (9) retrieve the next state from the one or more tables in accordance with the masked signal and the current state; and (10) update the current state in accordance with the next state. 33. The storage medium of claim 30, wherein the variable-length encoded signals are encoded video signals.
Motion estimation preferably is based on the stun of absolute differences (SAD(i,j)) between the component signals of the target macroblock and the component signals of the macroblock in the reference frame corresponding to the motion vector (i,j). In a preferred embodiment, only 64 of the possible 256 component differences are used to compute the SAD. These 64 differences preferably correspond to every other row and every other column starting at one corner of the (16
ME Rule (B) For each of the other image regions k (having the same number of rows of macroblocks as image region i), the target macroblocks of image region k(1) may not have motion vectors that correspond to image regions above image region k of the reference frame j-1 and (2) may not have motion vectors that correspond to image region i of the reference frame j-1.
(1) Calculate InterSAD=sum of c(i,j)-p(i,j)
(2) Calculate IntraSAD=sum of c(i,j)-C
(5) Otherwise classify target macroblock as an intra macroblock. Step (4) forces a macroblock with a relatively small InterSAD to be inter encoded. Those skilled in the art will understand that this helps prevent artifacts that may occur when macroblocks in non-moving parts of the image are intra encoded.
If the magnitude of the difference between the scaled quantization level Q(i) for the current macroblock i and the scaled quantization level Q(i-1) for the previous macroblock i-1 is greater than a specified threshold D, then the scaled quantization level Q(i) is adjusted (in step 812) according to Equation (5) as follows: ##EQU3## Step 812 limits the magnitude of the change in quantization level from macroblock to macroblock. Those skilled in the art will understand that step 812 is a filter designed to reduce oscillations in quantization levels. Step 812 also hard limits the quantization level Q(i) to between 0 and 15, inclusive.
B.sub.f.sup.t is the specified target number of bits per frame. The target number of bits per frame B.sub.f.sup.t may be generated by dividing the target bit rate (in bits per second) by the video frame rate (in frames per second). The number of available bits B.sub.a (n-1) from the previous frame n-1 is preferably initialized to the target number of bits per frame B.sub.f.sup.t at the start of the video sequence. The number of bits actually used B.sub.f (n-1) to encode the previous frame n-1 is preferably initialized to 0 at the start of the video sequence.
if(v.sub.u &gt;=0)v.sub.q =v.sub.u /q;
else v.sub.q =-(-v.sub.u /q); where v.sub.u is the unquantized DST coefficient, q is the quantizer, "/" represents division with truncation, and v.sub.q is quantized DST coefficient. The different treatment of DST coefficients with negative values ensures truncation toward zero. Those skilled in the art will understand that a purpose of this is to improve compression by always truncating toward the smaller of the two nearest integer values.
Macroblock Codebook {1,2,3,4*}
Block Codebook {1,2,3,4,5,6,5,6*}
TABLE II______________________________________Code Words and Corresponding Values for theMacroblock Codebook.     Code Words              Values______________________________________         1x       0-1        01xx      2-5        001xxx     6-13       00000000   hole00000001 to 00011110   14-43       00011111   separator______________________________________
TABLE III______________________________________Code Words and Corresponding Values for theBlock Codebook.        Code Words                  Values______________________________________              1x      0-1             01xx     2-5             001xxx    6-13            0001xxxx  14-29            00001xxxxx                      30-61           000001xxxxxx                       62-127           0000001xxxxx                      128-159          00000000 00xxxx                      hole00000000 010000 to          00000001 101111                      160-255______________________________________
where c is a Y component of an inter macroblock of the current frame, p is the corresponding non-motion-compensated Y component of the reference frame, and s is the temporal filter strength. The temporal filter strength s may be either 1, 2, or 3, where s-1 corresponds to taking 1/4 of the reference image, s=2 corresponds to taking 1/8 of the reference image, and s=3 corresponds to taking 1/16 of the reference image. The "(1&lt;&lt;2)" term is included to avoid drift due to integer math.
Temporal post-filtering is preferably not applied to empty macroblocks, or to empty blocks that have a motion vector of zero. In these cases, each current Y component (curr[ ][ ]) is identical to the corresponding non-motion-compensated Y component (prev[ ][ ]) from the reference frame. Temporal post-filtering is, however, preferably applied to empty blocks with non-zero motion vectors.
TABLE IV______________________________________Image Sizes Indicated by the ImageSize Signal.ImageSizeValue         Image Size______________________________________0             (1601             (2402             (3203             defined______________________________________
TABLE VI______________________________________Base Matrices, Quantization Parameters, and PowersOf2Flag Values Indicated by the QuantMatrices Signal.QuantMatrices      Base       QuantizationValue      Matrices   Parameters  PowersOf2______________________________________0          Default    Default     01          Default    Default     12          Default    In QuantData                             In QuantData3          In QuantData                 In QuantData                             In QuantData4          From Past  From Past   From Past5-7        . . . Reserved . . .______________________________________
The 2-bit Reserved 1 signal is reserved and preferably has a value of 0.
TABLE VII______________________________________Semantic Table for Information Stored in TypeSignal.                           4-bit HuffmanIntra  NewQ      MV     CBP     Value Value______________________________________0      0         0      1       1     00      0         1      1       3     11      0         0      0       8     20      1         1      1       7     30      1         0      1       5     41      1         0      0       12    50      0         1      0       2     6______________________________________
where QV represents the Huffman-decoded value corresponding to the Huffman-encoded QValue signal and tosigned() is a function which converts from an unsigned signal to a signed signal and is defined the following C computer language code: ##EQU6##
where MVx and MVy represent the Huffman-decoded values corresponding to the first and second Huffman-encoded signals in the MV signal, respectively, and tosigned0 is the same function as defined above. A positive X component means that the reference block in the previous frame is to the right of the block in the current frame. A positive Y component means that the reference block is below the block in the current frame. At the start of each row of macroblocks, the motion vector of the previous macroblock (prevMVx, prevMVy) is preferably set to be the zero vector (0,0).
The block signals of the slice signal format of FIG. 17 encode information for each of the non-empty blocks in the slice. The block signals are a series of Huffman-encoded run-val pairs terminated by a block separator signal comprising a string of 14 zero bits. Each run-val pair corresponds to a run of DST coefficients having value 0 followed by a non-zero DST coefficient value. Common run-val pairs are encoded with a single RVcode which is used as an index to a run table (runtb1) and a value table (valtb1).
______________________________________empty = 0   `` initialize number of empty macroblockswhile (1)code = gethuff( );           `` retrieve and decode next signalif (code &amp;lt; 42){empty += code;  `` increment empty by codebreak;}else if (code == 42)empty += 41;    `` increment empty by 41else if (code == 43)all macroblocks to end of slice are empty}______________________________________
As described earlier in this specification in the section entitled "Block Signals," the block signals comprise a series of Huffman-encoded run-val pairs terminated by a block separator signal comprising a string of 14 zero bits. Each run-val pair corresponds to a run of DST coefficients having value 0 followed by a non-zero DST coefficient value. Common run-val pairs are encoded with a single RVcode which is used as an index to a run table (runtbl) and a value table (valtb1). Those run-val pairs that are not contained in the lookup tables are encoded as four Huffman-encoded signals per run-val pair--one for the escape code, one for the run, and two for the value.
______________________________________for (i=0; i&amp;lt;8; i++)for (j=0; j&amp;lt;8; j++)coeff[i] [j] = 0;start at position "-1' on the zig-zag path (one step "before" 0)for (each run/val pair)step forward by `run  positions on the zig-zag pathdeposit  val  at the new position}______________________________________
______________________________________for (i=0; i&amp;lt;8; i++)for (j=0; j&amp;lt;8; j++)q = Qmatrix[Intra] [thisQ] [i] [j];c = coeff[i] [j];if (c &amp;gt; 0)coeff[i] [j] = (q * c) + (q &amp;gt;&amp;gt; 1) - (q &amp; 1);else if (c &amp;lt; 0)coeff[i] [j] = (q * c) - (q &amp;gt;&amp;gt; 1) + (q &amp; 1);else if (c == 0)coeff[i] [j] = 0;}______________________________________
coeff[0][0]+=prevDC
prevDC=coeff[0][0]
for (i=0; i&amp;lt;8; i++)
for (j=0; j&amp;lt;8; j++)
image[i][j]=clamp (MCprev[i][j])+array[i][j],8,120);
where array[ ][ ] contains the results of the IDST calculation, MCprev[ ][ ] is the corresponding motion-compensated (8 signals from the previous image, and the function clamp(n,min,max) limits a value n to the range (min,max).
image[i][j]=clamp(array[i][j],8,120);
______________________________________k = 0;while (1)v = gethuff( );if (v == EOB)break;else if (v == ESC) // get explicit run, val from bitstream{run[k] = gethuff ( ) + 1;lo = gethuff( );hi = gethuff( );val[k] = tosigned((lo   (hi&amp;lt;&amp;lt;6))+1);}else // lookup run, val in tables{run[k] = runtbl[v];val[k] = valtbl[v];}k++;}______________________________________
______________________________________runtbl [ ] = {    0      1      1    2    2    1    1    3    1      3      1    0    4    4    1    2    1      2      5    5    1    6    1    6    1      7      7    1    1    9    8    8    2      9      1    2    3    10   1    10    3      1      11   1    1    2    1    13    1      4      4    1    1    11   12   2    13     1      2    15   1    1    12   14    3      14     1    2    15   5    6    5    1      1      1    1    1    3    1    1    6      16     2    1    1    7    1    21    1      2      2    4    7    18   1    16    1      1      17   2    8    4    1    8    18     19     7    22   3    17   9    2    4      20     10   19   10   1    1    2    21     20     29   28   23   25   3    3    3      24     26   26   2    12   9    2    1      2      2    27   13   22   5    5    28     30     23   32   27   2    3    6    9      4      32   12   11   31   11   14    3      3      3    3    2    6    8    7    5      29     14   9    25   24   2    3    2      6      6    8    7    4    4    4    13     31     10   18   6    7    5    4    5      5      4    10   21   30   19   18    19     22     20   21   22   20   16   15    15     17     17   16   3    3    4    4    3      3      4    6    6    7    7    5    4      4      5    6    5    5valtbl[ ] = {    0      -1     1    1    -1   -2   2    -1    -3     1      3    0    1    -1   -4   -2    4      2      -1   1    -5   1    5    -1    -6     -1     1    6    7    -1   -1   1    -3     1      -7   3    -2   -1   -8   1    2      8      -1   9    -9   4    -11  1    -10    -2     2    10   11   1    -1   -4    -1     -13    -5   -1   -12  13   1    1    3      -1     12   5    1    2    2    -2    -15    14     16   -14  15   -3   -17  18    -2     -1     6    17   -16  2    19   -1    -19    7      -6   -3   -2   1    -22  1    -20    -18    -1   -7   2    4    20   -2    -1     -1     -3   -1   -4   1    -2   -8    3      1      -2   1    2    -21  22   9    1      -1     -1   -1   -1   -1   5    -5    4      -1     -1   1    8    -2   2    11    21     10     -11  1    -2   1    3    -3    1      -1     1    1    -1   12   6    3    -3     -4     -1   2    -2   -1   2    2    -7     -9     -8   7    -12  5    -3   3    -4     1      -2   3    1    1    -10  8    -9     -4     -3   3    -4   6    5    -5    2      1      -3   -2   4    -5   7    -6    5      -5     7    3    2    1    2    2    -2     -2     2    -2   2    -2   -2   2    -2     2      -2   2    -6   -10  -8   -9    10     9      -7   6    -5   5    4    -7    9      8      6    -6   -6   4}______________________________________
Note that runtb1[0]=valtb1[0]=0 and that runtb1[11]=valtb1[11]=0, because the values 0 and 11 are reserved for the EOB and ESC signals, respectively.
The forward discrete slant transform (FDST) transforms pixel components in the spatial domain to DST components in the spatial frequency domain. The inverse DST (IDST) transforms DST components back into pixel components. The discrete slant transform applies an (8 eight rows and eight columns of an (8 in this specification in conjunction with FIG. 4, pixel processor 302 of FIG. 3 applies the FDST when generating encoded video signals (step 412 of FIG. 4). Pixel processor 302 also applies the IDST when generating the reference frame signals from the encoded video signals (step 426). Similarly, as described earlier in this specification in conjunction with FIG. 21, host processor 202 of FIG. 2 applies the IDST when decoding the encoded video signals (step 2112 of FIG. 21).
______________________________________slant8          s = pointer to input column or row          d = pointer to output column or rowint s[ ],d[ ],fwd;          fwd = 1 for forward DST, 0 for inverse       DSTint r1,r2,r3,r4,r5,r6,r7,r8;int t,t1,*p;if (fwd)       apply forward DST}p = s;r1 = *p++;       store value pointed to by p to r1 and            then increment pr2 = *p++;r3 = *p++;r4 = *p++;r5 = *p++;r6 = *p++;r7 = *p++;r8 = *p++;SlantPart1;SlantPart2;SlantPart3;SlantPart4;p = d;*p++ = r1;*p++ = r4;*p++ = r8;*p++ = r5;*p++ = r2;*p++ = r6;*p++ = r3;*p++  = r7;}else             apply inverse DST{p = s;r1 = *p++;r4 = *p++;r8 = *p++;r5 = *p++;r2 = *p++;r6 = *p++;r3 = *p++;r7 = *p++;SlantPart4;SlantPart3;SlantPart2;SlantPart1;p = d;*p++ = r1;*p++ = r2;*p++ = r3;*p++ = r4;*p++ = r5;*p++ = r6;*p++ = r7;*p++ = r8;}}______________________________________
______________________________________#define SlantPart1bfly(r1,r4);bfly(r2,r3);bfly(r5,r8);bfly(r6,r7);#define SlantPart2bfly(r1,r2);reflect(r4,r3);bfly(r5,r6);reflect(r8,r7);#define SlantPart3bfly(r1,r5);bfly(r2,r6);bfly(r7,r3);bfly(r4,r8);#define SlantPart4t = r5 - (r5&amp;gt;&amp;gt;3) + (r4&amp;gt;&amp;gt;1);    t = 7/8 r5 + 1/2 r4r5 = r4 - (r4&amp;gt;&amp;gt;3) - (r5&amp;gt;&amp;gt;1);    r5 = 7/8 r4 - 1/2 r5r4 = t;______________________________________
______________________________________bfly(x,y):t = x+y;y = x-y;x = t;#define reflect(s1,s2)            for forward transform   t = 11/8 s1 + 9/16 s2t = s1 + (s1&amp;gt;&amp;gt;2) + (s1&amp;gt;&amp;gt;3) + (s2&amp;gt;&amp;gt;1) + (s2&amp;gt;&amp;gt;4);   s2 = -11/8 s2 + 9/16 s1s2 = -s2 - (s2&amp;gt;&amp;gt;2) - (s2&amp;gt;&amp;gt;3) + (s1&amp;gt;&amp;gt;1) + (s1&amp;gt;&amp;gt;4);s1 = t;#define reflect(s1,s2)            for inverse transform   t = 5/4 s1 + 1/2 s2t = s1 + (s1&amp;gt;&amp;gt;2) + (s2&amp;gt;&amp;gt;1);   s2 = -5/4 s2 + 1/2 s1s2 = -s2 - (s2&amp;gt;&amp;gt;2) + (s1&amp;gt;&amp;gt;1);s1 = t;______________________________________
array[i][j]=(array[i][j]+4)&amp;gt;&amp;gt;3
array[i][j]=array[i][j]&amp;gt;&amp;gt;3
Pseudo-SIMD Dual Slant Transform For intra blocks, the forward DST converts 7-bit unsigned component signals in the spatial domain into 11-bit DST coefficients in the spatial frequency domain. For inter blocks, the FDST converts 8-bit signed component difference signals in the spatial domain into 11-bit DST coefficients in the spatial frequency domain. The inverse DST does the reverse. To allow for error introduced by the quantization and dequantization of the DST coefficients, 12-bit precision in the DST coefficients is preferably provided.
Bit 0 (i.e., the LSB) corresponds to row 0:
Bit 3 is 1 because at least one of DST coefficients (4,0), (5,0), (6,0), and (7,0) is non-zero. And, analogously, for column complexity masks 1-7. Note that the 4-bit column complexity masks for columns 4-7 each contain the value (0000).
TABLE IX______________________________________Initial Assignment of Column DST Operations andFinal Assigment of Row DST Operations.4-bitComplexity  Mask            DSTMask        Values          Operation______________________________________(1xxx)       8-15           slant8x1(01xx)      4-7             slant4x1(001x)      2-3             slant2x1(0001)      1               slant1x1(0000)      0               null______________________________________
The only case where a column is not processed according to its original complexity, is when the mask is 0000 for the column, but the slant1 subsequent row operations.
we need to perform slant1 comments above.
q.sub.1 ≧T and if Block 1 is not {empty and inter and MV=0}
______________________________________  add code length to bit pointer  loop while (bit pointer &amp;gt; = 8) {   increment byte pointer by 1;   decrement bit pointer by 8;   }______________________________________
______________________________________Table[bit pointer] = 0            for bit pointer = 0, . . . , 7Table[bit pointer] = 1            for bit pointer = 8, . . . , 15Table[bit pointer] = 2            for bit pointer = 16, . . . , 23            etc.______________________________________
where B is the masked byte, *pIn retrieves the byte specified by the pIn pointer, MASK is a lookup table of the possible masks, and STATE is a value assigned to the current state. The possible masks may be represented as (11111111), (0111111), (00001111), (00000011), (00000000), (11000000), (11110000), and (11111100).
Contrib[ ][ ] Specifies the contribution to the 8-bit accumulator.
NextState[ ][ ] Specifies a 6-bit value corresponding to the next state.
Incin[ ][ ] Specifies a 1-bit flag indicating whether the input pointer (pIn) is to be incremented.
IncOut[ ][ ] Specifies a 1-bit flag indicating whether the accumulator is to be initialized and whether the output pointer (pOut) is to be incremented.
TABLE X______________________________________Possible States for Parsing Huffman-Encoded Macroblock Signals.STATE       MEANING______________________________________MPrefixAt0  Prefix starts at bit 0 of current byte.MPrefixAt2  Prefix starts at bit 2 of current byte.MPrefixAt4  Prefix starts at bit 4 of current byte.MPrefixAt6  Prefix starts at bit 6 of current byte.MGot2Prefix Bit 0 of current byte is the third bit (bit       2) of prefix started in previous byte.MNeed2Code  Bits 0-1 of current byte complete free bits.MNeed4Code  Bits 0-3 of current byte complete free bits.MNeed2Non0  Bits 0-1 of current byte complete free bits,       but they are not both 0.MNeed2Non1  Bits 0-1 of current byte complete free bits,       but they are not both 1.MNeed4Non0  Bits 0-3 of current byte complete free bits,       but they are not all 0.MNeed4Non1  Bits 0-3 of current byte complete free bits,       but they are not all 1.______________________________________
TABLE XI______________________________________Possible States for Parsing Huffman-Encoded Block Signals.STATE       MEANING______________________________________BPrefixAt0  Prefix starts at bit 0 of current byte.BPrefixAt2  Prefix starts at bit 2 of current byte.BPrefixAt4  Prefix starts at bit 4 of current byte.BPrefixAt6  Prefix starts at bit 6 of current byte.BGot2Prefix Bit 0 of current byte is bit 2 of prefix.BGot4Prefix Bit 0 of current byte is bit 4 of prefix.BGot8PAt4   Bit 4 of current byte is bit 8 of prefix.BGot6Prefix Bit 0 of current byte is bit 6 of prefix.BGot8Prefix Bit 0 of current byte is bit 8 of prefix.BNeed2Code  Bits 0-1 of current byte complete free bits.BNeed4Code  Bits 0-3 of current byte complete free bits.BNeed6Code  Bits 0-5 of current byte complete free bits.BNeed2At4   Bits 4-5 of current byte complete free bits.BNeed4At4   Bits 4-7 of current byte complete free bits.BNeed6At4   Bits 4-7 of current byte and bits 0-1 of next       byte complete free bits.IllegalCode Code not allowed.BEnd        End of block signals (end of slice).BlkDataAt0  Block signals begin at bit 0 of current byte.BlkDataAt2  Block signals begin at bit 2 of current byte.BlkDataAt4  Block signals begin at bit 4 of current byte.BlkDataAt6  Block signals begin at bit 6 of current byte.______________________________________
Tables XII-XV present the information encoded in the four lookup tables Contrib[ ][ ], NextState[ ][ ], IncIn[ ][ ], and IncOut[ ][ ] which define the allowable state transitions used by decoder 3300. Each line of Tables XII-XV represents a macro (or abstract rule) that defines a set of rules for the allowable state transitions. The number of rules defined by each macro is the number of possible combinations of the masked byte for that macro as defined below.
Column (1) in Tables II-XV is a representation of the masked bytes (B) corresponding to the possible current byte values. Column (2) is the current state (STATE) of decoder 3300. The masked byte and the current state are the indices for the lookup tables that map to Columns 4-6. Column 4 is the next state. Column 3 is a base value for the contribution that gets added to the accumulator. Column 5 is the bitstream pointer flag, where 1 means increment the bitstream pointer. Column 6 is the output pointer flag, where 0 means increment the output pointer and initialize the accumulator.
TABLE XII__________________________________________________________________________Abstract Rules for Variable-Length Decoding.                      Increment                            SignalByte   Current         Next   Base  Bitstream                            NotValue  State  State  Contrib                      Pointer                            Complete__________________________________________________________________________XXXXXXF1  MPrefixAt0         MPrefixAt2                0     0     0XXXXFE10  MPrefixAt0         MPrefixAt4                2     0     0X1FED100  MPrefixAt0         MPrefixAt6                6     0     010FED100  MPrefixAt0         MNeed2Code                6     1     000FED100  MPrefixAt0         MGot2Prefix                6     1     0fedcb000  MPrefixAt0         MPrefixAt0                14-1  1     000000000  MPrefixAt0         IllegalCode                255   1     011111000  MPrefixAt0         BlkDataAt0                255   1     0XXXXF1ZZ  MPrefixAt2         MPrefixAt4                0     0     0X1FE10ZZ  MPrefixAt2         MPrefixAt6                2     0     010FE10ZZ  MPrefixAt2         MNeed2Code                2     1     000FE10ZZ  MPrefixAt2         MGot2Prefix                2     1     0FED100ZZ  MPrefixAt2         MPrefixAt0                6     1     0dcb000ZZ  MPrefixAt2         MNeed2Code                14-3  1     1000000ZZ  MPrefixAt2         MNeed2Non0                0     1     1111000ZZ  MPrefixAt2         MNeed2Non1                28    1     1X1F1ZZZZ  MPrefixAt4         MPrefixAt6                0     0     010F1ZZZZ  MPrefixAt4         MNeed2Code                0     1     000F1ZZZZ  MPrefixAt4         MGot2Prefix                0     1     0FE10ZZZZ  MPrefixAt4         MPrefixAt0                2     1     0D100ZZZZ  MPrefixAt4         MNeed2Code                6-2   1     10000ZZZZ  MPrefixAt4         MNeed4Non0                0     1     11000ZZZZ  MPrefixAt4         MNeed4Non1                16    1     1F1ZZZZZZ  MPrefixAt6         MPrefixAt0                0     1     010ZZZZZZ  MPrefixAt6         MNeed2Code                0     1     100ZZZZZZ  MPrefixAt6         MGot2Prefix                0     1     1ZZXXFED1  MGot2Prefix         MPrefixAt4                6     0     0ZZfedcb0  MGot2Prefix         MPrefixAt6                14-1  0     0ZZ000000  MGot2Prefix         IllegalCode                255   1     0ZZ111110  MGot2Prefix         BlkDataAt6                255   0     0ZZZZZZFE  MNeed2Code         MPrefixAt2                2     0     0ZZZZFEDC  MNeed4Code         MPrefixAt4                2     0     0__________________________________________________________________________
TABLE XIII__________________________________________________________________________Abstract Rules for Variable-Length Decoding.                      Increment                            SignalByte   Current         Next   Base  Bitstream                            NotValue  State  State  Contrib                      Pointer                            Complete__________________________________________________________________________ZZZZZZfe  MNeed2Non0         MPrefixAt2                14-1  0     0ZZZZZZ00  MNeed2Non0         IllegalCode                255   0     0ZZZZZZfe  MNeed2Non1         MPrefixAt2                14-1  0     0ZZZZZZ11  MNeed2Non1         BlkDataAt2                255-28                      0     0ZZZZfedc  MNeed4Non0         MPrefixAt4                14-1  0     0ZZZZ0000  MNeed4Non0         IllegalCode                255   0     0ZZZZfedc  MNeed4Non1         MPrefixAt4                14-1  0     0ZZZZ1111  MNeed4Non1         BlkDataAt4                255-16                      0     0XYYYYYF1  BPrefixAt0         BPrefixAt2                0     0     0000000F1  BPrefixAt0         BGot6Prefix                0     1     0100000F1  BPrefixAt0         BNeed6Code                0     1     0XYYYFE10  BPrefixAt0         BPrefixAt4                2     0     00000FE10  BPrefixAt0         BGot4Prefix                2     1     01000FE10  BPrefixAt0         BNeed4Code                2     1     0X1FED100  BPrefixAt0         BPrefixAt6                6     0     000FED100  BPrefixAt0         BGot2Prefix                6     1     010FED100  BPrefixAt0         BNeed2Code                6     1     0FEDC1000  BPrefixAt0         BPrefixAt0                14    1     0DCB10000  BPrefixAt0         BNeed2Code                30-2  1     1BA100000  BPrefixAt0         BNeed4Code                62-14 1     1B1000000  BPrefixAt0         BNeed4Code                126-14                      1     110000000  BPrefixAt0         BNeed6Code                206-62                      1     100000000  BPrefixAt0         BGot8Prefix                0     1     1XYYYF1ZZ  BPrefixAt2         BPrefixAt4                0     0     00000F1ZZ  BPrefixAt2         BGot4Prefix                0     1     01000F1ZZ  BPrefixAt2         BNeed4Code                0     1     0X1FE10ZZ  BPrefixAt2         BPrefixAt6                2     0     000FE10ZZ  BPrefixAt2         BGot2Prefix                2     1     010FE10ZZ  BPrefixAt2         BNeed2Code                2     1     0FED100ZZ  BPrefixAt2         BPrefixAt0                6     1     0DC1000ZZ  BPrefixAt2         BNeed2Code                14-2  1     1B10000ZZ  BPrefixAt2         BNeed4Code                30-14 1     1100000ZZ  BPrefixAt2         BNeed6Code                0     1     1000000ZZ  BPrefixAt2         BGot6Prefix                0     1     1__________________________________________________________________________
TABLE XIV__________________________________________________________________________Abstract Rules for Variable-Length Decoding.                      Increment                            SignalByte   Current         Next   Base  Bitstream                            NotValue  State  State  Contrib                      Pointer                            Complete__________________________________________________________________________X1F1ZZZZ  BPrefixAt4         BPrefixAt6                0     0     000F1ZZZZ  BPrefixAt4         BGot2Prefix                0     1     010F1ZZZZ  BPrefixAt4         BNeed2Code                0     1     0FE10ZZZZ  BPrefixAt4         BPrefixAt0                2     1     0D100ZZZZ  BPrefixAt4         BNeed2Code                6-2   1     11000ZZZZ  BPrefixAt4         BNeed4Code                0     1     10000ZZZZ  BPrefixAt4         BGot4Prefix                0     1     1F1ZZZZZZ  BPrefixAt6         BPrefixAt0                0     1     010ZZZZZZ  BPrefixAt6         BNeed2Code                0     1     100ZZZZZZ  BPrefixAt6         BGot2Prefix                0     1     1XYYYFED1  BGot2Prefix         BPrefixAt4                6     0     00000FED1  BGot2Prefix         BGot4Prefix                6     1     01000FED1  BGot2Prefix         BNeed4Code                6     1     0X1FEDC10  BGot2Prefix         BPrefixAt6                14    0     000FEDC10  BGot2Prefix         BGot2Prefix                14    1     010FEDC10  BGot2Prefix         BNeed2Code                14    1     0FEDCB100  BGot2Prefix         BPrefixAt0                30    1     0DCBA1000  BGot2Prefix         BNeed2Code                62-2  1     1DCB10000  BGot2Prefix         BNeed2Code                126-2 1     1BA100000  BGot2Prefix         BNeed4Code                206-14                      1     1ba000000  BGot2Prefix         BNeed4Code                158-30                      1     100000000  BGot2Prefix         BEnd   255   0     1ZZZZDCB1  BGot4Prefix         BNeed2At4                30    0     1ZZZZBA10  BGot4Prefix         BNeed4At4                62    0     1ZZZZB100  BGot4Prefix         BNeed4At4                126   0     1ZZZZ1000  BGot4Prefix         BNeed6At4                206   0     1ZZZZ0000  BGot4Prefix         BGot8PAt4                0     0     1DCbaZZZZ  BGot8PAt4         BNeed2Code                158-18                      1     10000ZZZZ  BGot8PAt4         BEnd   255   0     1ZZZZDCB1  BGot6Prefix         BNeed2At4                126   0     1ZZZZBA10  BGot6Prefix         BNeed4At4                206   0     1ZZZZba00  BGot6Prefix         BNeed4At4                158-16                      0     1ZZZZ0000  BGot6Prefix         BEnd   255   0     1__________________________________________________________________________
TABLE XV__________________________________________________________________________Abstract Rules for Variable-Length Decoding.                      Increment                            SignalByte   Current         Next   Base  Bitstream                            NotValue  State  State  Contrib                      Pointer                            Complete__________________________________________________________________________ZZZZZZYY  BGot8Prefix         BNeed6Code                158-78                      0     1ZZZZZZ00  BGot8Prefix         BEnd   255   0     1ZZZZZZFE  BNeed2Code         BPrefixAt2                2     0     0ZZZZFEDC  BNeed4Code         BPrefixAt4                14    0     0ZZFEDCBA  BNeed6Code         BPrefixAt6                62    0     0X1FEZZZZ  BNeed2At4         BPrefixAt6                0     0     000FEZZZZ  BNeed2At4         BGot2Prefix                0     1     010FEZZZZ  BNeed2At4         BNeed2Code                0     1     0FEDCZZZZ  BNeed4At4         BPrefixAt0                0     1     0DCBAZZZZ  BNeed6At4         BNeed2Code                0xFE  1     1ZZZZZZZZ  BlkDataAt0         BPrefixAt0                0     0     1ZZZZZZZZ  BlkDataAt2         BPrefixAt2                0     0     1ZZZZZZZZ  BlkDataAt4         BPrefixAt4                0     0     1ZZZZZZZZ  BlkDataAt6         BPrefixAt6                0     0     1__________________________________________________________________________
______________________________________for (k=0; k&amp;lt;2; k++)  // for each of inter, intra base matrices// Apply tilt to base matrixfor (j=0; j&amp;lt;8; j++)for (i=0; i&amp;lt;8; i++)Base [k][j][i] = (Base [k][j][i]     (32 + (i+j) * (Tilt[k]-32)/32))/32;// Generate the 16 quantization matrices of this typefor (m=0; m&amp;lt;16; m++){for (j=0; j&amp;lt;8; j++){for (i=0; i&amp;lt;8; i++){if (i==0 &amp;&amp; j==0 &amp;&amp; k==1)s = DCstep;elses = QuantStep;q = (Base[k][j][i]*(QuantStart + ((s*m)&amp;gt;&amp;gt;2))) &amp;gt;&amp;gt; 6;if (q&amp;lt;2) q=2;if (q&amp;gt;127) q=127;if (PowersOf2)q = Round2[q];elseq =  q &amp;gt;&amp;gt; 1;Qmatrix[k][m][j][i] = q;}}}}______________________________________
where Round2[ ] is a lookup table that divides by two and rounds to the nearest power of two, as follows:
______________________________________Round2[] = 0,        0,     1,      2,   2,    2,   4,    4, 4,        4,     4,      4,   8,    8,   8,    8, 8,        8,     8,      8,   8,    8,   8,   16,16,       16,    16,     16,  16,   16,  16,   16,16,       16,    16,     16,  16,   16,  16,   16,16,       16,    16,     16,  16,   16,  32,   32,32,       32,    32,     32,  32,   32,  32,   32,32,       32,    32,     32,  32,   32,  32,   32,32,       32,    32,     32,  32,   32,  32,   32,32,       32,    32,     32,  32,   32,  32,   32,32,       32,    32,     32,  32,   32,  32,   32,32,       32,    32,     64,  64,   64,  64,   64,64,       64,    64,     64,  64,   64,  64,   64,64,       64,    64,     64,  64,   64,  64,   64,64,       64,    64,     64,  64,   64,  64,   64,64,       64,    64,     64,  64,   64,  64,   64};______________________________________
The Tilt[ ] parameters tilt the main diagonal of the base matrices, thus changing how heavily or lightly high-frequency coefficients are quantized, relative to low-frequency coefficients. A tilt value of 32 applies no tilt, and leaves the base matrix unchanged. Tilt values less than 32 decrease high-frequency quantization, and tilt values greater than 32 increase high-frequency quantization.
______________________________________QuantStart       = 30QuantStep        = 36DCstep           =  8Tilt[0] = Tilt[1]            = 32PowersOf2        =  1______________________________________
______________________________________Inter: 8     8       8       8     9     9    10    10 8     8       8       9     9    10    10    11 8     8       8       9    10    11    11    12 8     9       9      10    10    11    12    13 9     9      10      10    11    12    12    14 9    10      11      11    11    12    13    1510    10      11      12    13    13    14    1510    11      12      13    14    15    15    16Intra: 6     8       9      11    13    13    14    17 8     8      11      12    13    14    17    18 9    11      13      13    14    17    17    1911    11      13      13    14    17    18    2011    13      13      14    16    17    20    2413    13      14      16    17    20    24    2913    13      14      17    19    23    28    3413    14      17      19    23    28    34    41______________________________________
SUMMARY OF THE INVENTION The present invention is a computer-implemented process, apparatus, and system for decoding variable-length encoded signals. A fixed-length signal is retrieved from a bitstream comprising one or more variable-length encoded signals. A variable-length encoded signal of the bitstream is decoded to generate a decoded signal corresponding to the fixed-length signal by accessing one or more tables in accordance with the fixed-length signal to retrieve a contribution, an input pointer flag, an output pointer flag, and a next state.
CROSS-REFERENCES TO RELATED APPLICATIONS This is a continuation-in-part of co-pending application Ser. No. 08/158,855, filed on Nov. 24, 1993, entitled "Computer-Implemented Process and System for Decompressing a Compressed Image."
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