Source: http://www.google.com/patents/US20050060675?dq=5,666,293
Timestamp: 2017-04-30 02:02:10
Document Index: 581317664

Matched Legal Cases: ['art 600', 'art 600', 'art 600', 'art 700', 'art 700', 'art 700', 'art 800', 'art 800', 'art 900', 'art 900', 'art 900']

Patent US20050060675 - Method of noise analysis and correction of noise violations for an ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method of noise analysis and correction of noise violations for an integrated circuit design includes steps of (a) receiving as input a standard parasitic exchange file for an integrated circuit design; (b) parsing the standard parasitic exchange file to generate a resistance graph; (c) generating...http://www.google.com/patents/US20050060675?utm_source=gb-gplus-sharePatent US20050060675 - Method of noise analysis and correction of noise violations for an integrated circuit designAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20050060675 A1Publication typeApplicationApplication numberUS 10/665,927Publication dateMar 17, 2005Filing dateSep 17, 2003Priority dateSep 17, 2003Also published asUS7062731Publication number10665927, 665927, US 2005/0060675 A1, US 2005/060675 A1, US 20050060675 A1, US 20050060675A1, US 2005060675 A1, US 2005060675A1, US-A1-20050060675, US-A1-2005060675, US2005/0060675A1, US2005/060675A1, US20050060675 A1, US20050060675A1, US2005060675 A1, US2005060675A1InventorsAlexander TetelbaumOriginal AssigneeAlexander TetelbaumExport CitationBiBTeX, EndNote, RefManPatent Citations (15), Referenced by (18), Classifications (5), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetMethod of noise analysis and correction of noise violations for an integrated circuit design
US 20050060675 A1Abstract
A method of noise analysis and correction of noise violations for an integrated circuit design includes steps of (a) receiving as input a standard parasitic exchange file for an integrated circuit design; (b) parsing the standard parasitic exchange file to generate a resistance graph; (c) generating a representation of the resistance graph to determine noise critical nets; (d) generating a list of only noise critical nets from the representation of the resistance graph; (e) selecting a net from the list of only noise critical nets; (f) calculating a value of total crosstalk noise in the selected net from all aggressor nets relative to the selected net; and (g) generating as output the value of total crosstalk noise in the selected net for correcting a noise violation. Images(11) Claims(27)
1. A method of noise analysis and correction of noise violations for an integrated circuit design comprising steps of: (a) receiving as input a standard parasitic exchange file for an integrated circuit design; (b) parsing the standard parasitic exchange file to generate a resistance graph; (c) generating a representation of the resistance graph to determine noise critical nets; (d) generating a list of only noise critical nets from the representation of the resistance graph; (e) selecting a victim net from the list of only noise critical nets; (f) calculating a value of total crosstalk noise in the selected victim net from all aggressor nets relative to the selected victim net; and (g) generating as output the value of total crosstalk noise in the selected victim net for correcting a noise violation. 2. The method of claim 1 wherein step (c) comprises generating one of a resistance tree and a resistance star tree as the representation of the resistance graph. 3. The method of claim 1 wherein step (d) comprises filtering the nets in the representation of the resistance graph to exclude nets that are not subject to false switching from crosstalk noise. 4. The method of claim 1 wherein step (d) comprises filtering the nets in the representation of the resistance graph to include nets that drive logical stages that drive noise critical nets. 5. The method of claim 1 wherein step (f) comprises calculating a peak noise and a drop noise for the selected net. 6. The method of claim 5 wherein step (f) comprises comparing the peak noise and the drop noise to a peak noise threshold and a drop noise threshold for the selected victim net to determine whether a noise violation may occur in the selected net. 7. The method of claim 6 wherein step (g) comprises generating a report of a noise violation if the peak noise threshold or the drop noise threshold is exceeded. 8. The method of claim 7 wherein step (g) comprises reporting a name of the selected victim net, the peak noise, the drop noise, and names of significant aggressor nets and their respective contributions to the total noise. 9. The method of claim 1 wherein step (f) comprises calculating a crosstalk noise VXm coupled into the selected victim net by an aggressor by the following formulas: VX
10. The method of claim 9 wherein step (f) comprises calculating a ratio rm of a coupling capacitance Ccm to a total net capacitance CvT so that the crosstalk noise VXm is given by: VX
11. The method of claim 1 further comprising a step of selecting an equivalent transient resistance of an aggressor net as an aggressor driver resistance for worst case, best case, and nominal case operating conditions from a cell library. 12. The method of claim 1 further comprising a step of determining values of a peak noise threshold and a drop noise threshold for the selected net and storing the values in a cell library. 13. The method of claim 1 wherein step (g) further comprises correcting a noise violation in the integrated circuit design by modifying a floorplan of the integrated circuit design wherein modifying the floorplan comprises at least one of increasing driver power of the selected victim net, decreasing driver power of an aggressor net, inserting a buffer in the victim net to reduce net delay, inserting a buffer in at least one of the aggressor nets to reduce net delay, and re-routing the victim net and its aggressors. 14. A computer program product for analyzing noise and correcting noise violations for an integrated circuit design comprising: a medium for embodying a computer program for input to a computer; and a computer program embodied in the medium for causing the computer to perform steps of: (a) receiving as input a standard parasitic exchange file for an integrated circuit design; (b) parsing the standard parasitic exchange file to generate a resistance graph; (c) generating a representation of the resistance graph to determine noise critical nets; (d) generating a list of only noise critical nets from the representation of the resistance graph; (e) selecting a net from the list of only noise critical nets; (f) calculating a value of total crosstalk noise in the selected net from all aggressor nets relative to the selected net; and (g) generating as output the value of total crosstalk noise in the selected net for correcting a noise violation. 15. The computer program product of claim 14 wherein step (c) comprises generating one of a resistance tree and a resistance star tree as the representation of the resistance graph. 16. The computer program product of claim 14 wherein step (d) comprises filtering the nets in the representation of the resistance graph to exclude nets that are not subject to false switching from crosstalk noise. 17. The computer program product of claim 14 wherein step (d) comprises filtering the nets in the representation of the resistance graph to include nets that drive logical stages that drive noise critical nets. 18. The computer program product of claim 14 wherein step (f) comprises calculating a peak noise and a drop noise for the selected net. 19. The computer program product of claim 18 wherein step (f) comprises comparing the peak noise and the drop noise to a peak noise threshold and a drop noise threshold for the selected net to determine whether a noise violation may occur in the selected net. 20. The computer program product of claim 19 wherein step (g) comprises generating a report of a noise violation if the peak noise threshold or the drop noise threshold is exceeded. 21. The computer program product of claim 20 wherein step (g) comprises reporting a name of the selected net, the peak noise, the drop noise, and names of significant aggressor nets and their respective contributions to the total noise. 22. The computer program product of claim 14 wherein step (f) comprises calculating a crosstalk noise VXm coupled into the selected net by an aggressor by the following formulas: VX
23. The computer program product of claim 22 wherein step (f) comprises calculating a ratio rm of a coupling capacitance Ccm to a total net capacitance CvT so that the crosstalk noise VXm is given by: VX
24. The computer program product of claim 14 further comprising a step of selecting an equivalent transient resistance of an aggressor net as an aggressor driver resistance for worst case, best case, and nominal case operating conditions from a cell library. 25. The computer program product of claim 14 further comprising a step of determining values of a peak noise threshold and a drop noise threshold for the selected net and storing the values in a cell library. 26. The computer program product of claim 14 wherein step (g) further comprises correcting a noise violation in the integrated circuit design by modifying a floorplan of the integrated circuit design wherein modifying the floorplan comprises at least one of: increasing driver power of the selected victim net; decreasing driver power of an aggressor net; inserting a buffer in the victim net to reduce net delay; inserting a buffer in at least one of the aggressor nets to reduce net delay; and re-routing the victim net and its aggressors. 27. A method of noise analysis and correction of noise violations for an integrated circuit design comprising steps of: (a) receiving as input a standard parasitic exchange file for an integrated circuit design; (b) parsing the standard parasitic exchange file to generate a resistance graph; (d) generating a list of only noise critical nets from the representation of the resistance graph; (c) calculating a value of total crosstalk noise in a selected victim net in the list of noise critical nets from all aggressor nets relative to the selected victim net; and (d) generating as output the value of total crosstalk noise in the selected victim net for correcting a noise violation. Description
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates generally to the design of integrated circuits. More specifically, but without limitation thereto, the present invention relates to methods of estimating and avoiding crosstalk in an integrated circuit design. [0003] 2. Description of Related Art [0004] With the dramatic increase in very large scale integrated circuit (VLSI) chip gate counts and circuit density, circuit noise resulting from crosstalk interference is becoming increasingly significant. Noise analysis is an important step in the design flow of integrated circuits, because crosstalk interference may result in false switching and failure of the design to meet performance specifications. Computer software tools have been developed for analyzing crosstalk noise, however, these tools may not be suitable for a variety of applications. Such tools generally require preparation of several special input files that require other software tools, which increases the turnaround time (TAT). The accuracy of the noise calculations is also limited by the accuracy of the software tools used to prepare the special input files. SUMMARY OF THE INVENTION [0005] In one aspect of the present invention, a method of noise analysis and correction of noise violations for an integrated circuit design includes steps of: (a) receiving as input a standard parasitic exchange file for an integrated circuit design; (b) parsing the standard parasitic exchange file to generate a resistance graph; (c) generating a representation of the resistance graph to determine noise critical nets; (d) generating a list of only noise critical nets from the representation of the resistance graph; (e) selecting a net from the list of only noise critical nets; (f) calculating a value of total crosstalk noise in the selected net from all aggressor nets relative to the selected net; and (g) generating as output the value of total crosstalk noise in the selected net for correcting a noise violation. [0013] In another aspect of the present invention, a computer program product for analyzing noise and correcting noise violations for an integrated circuit design includes: a medium for embodying a computer program for input to a computer; and a computer program embodied in the medium for causing the computer to perform steps of: (a) receiving as input a standard parasitic exchange file for an integrated circuit design; (b) parsing the standard parasitic exchange file to generate a resistance graph; (c) generating a representation of the resistance graph to determine noise critical nets; (d) generating a list of only noise critical nets from the representation of the resistance graph; (e) selecting a net from the list of only noise critical nets; (f) calculating a value of total crosstalk noise in the selected net from all aggressor nets relative to the selected net; and (g) generating as output the value of total crosstalk noise in the selected net for correcting a noise violation. BRIEF DESCRIPTION OF THE DRAWINGS [0023] The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements throughout the several views of the drawings, and in which: [0024] FIG. 1 illustrates a circuit model for a noise calculation according to an embodiment of the present invention; [0025] FIG. 2 illustrates a simplified circuit model of FIG. 1 in which a separate aggressor is associated with each crosstalk coupling point; [0026] FIG. 3 illustrates a chain structure for calculating noise from each aggressor net in the simplified circuit model of FIG. 2; [0027] FIG. 4 illustrates the circuit model of FIG. 3 further simplified to illustrate a noise calculation according to an embodiment of the present invention; [0028] FIGS. 5A, 5B, and 5C illustrate examples of net resistance graphs according to an embodiment of the present invention; [0029] FIG. 5D illustrates an example of a resistance tree constructed from the resistance net graph of FIG. 5C; [0030] FIG. 5E illustrates an example of a resistance star tree constructed from SPEF coordinates according to an embodiment of the present invention; [0031] FIG. 6 illustrates a flow chart of a method of analyzing crosstalk noise according to an embodiment of the present invention; [0032] FIG. 7 illustrates a flow chart for calculating noise in the selected net in the method of FIG. 6; and [0033] FIG. 8 illustrates a flow chart for performing an additional check to consider noise propagated into the selected net from the previous logical stage in the method of FIG. 6; and [0034] FIGS. 9A, 9B and 9C illustrate a flow chart for correcting a noise violation according to an embodiment of the present invention.
[0035] Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to point out distinctive features in the illustrated embodiments of the present invention. DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS [0036] Crosstalk noise is generally capacitively coupled between traces in an integrated circuit and is most significant when the sources of the crosstalk, commonly referred to as aggressor nets or aggressors, have a fast switching waveform. The switching waveforms of one or more aggressor nets are coupled by parasitic capacitances to a “victim” net, that is, a net that is in a non-switching state when the crosstalk is generated. The crosstalk noise may cause false switching in the victim net and consequent failure of the integrated circuit design to meet performance specifications. To avoid the possibility of false switching, it is advantageous to estimate the crosstalk noise to determine whether a modification to the floorplan is needed to reduce the crosstalk noise below the input threshold of the victim net. [0037] While commercial software tools have been developed for estimating crosstalk noise, these tools generally may not be tuned or refined to suit specific applications. The inflexibility of such noise analysis tools may include assumptions and limitations that are disadvantageous to resolving noise problems. For example, noise thresholds are assumed to be identical for all cells, which may not reflect the actual noise thresholds in the integrated circuit design. Noise violations are typically reported in all nets, even nets that do not drive state cells (flip-flops or other storage cells). Noise does not propagate from one stage to the next in a logical path, and the noise model may be inaccurate, resulting in false reporting. Additional input files may have to be generated, increasing turnaround time and incurring license fees. Also, the accuracy of the noise calculation depends on the accuracy of the additional input files, such as the ramptime data after a delay estimation. Disadvantageously, previous tools for noise analysis do not have the capability of generating the appropriate modifications to the floor plan needed to correct the noise violations that are reported. [0038] To simplify the design flow, to decrease turnaround time, and to maintain control over the noise analysis procedure, the disadvantages of the previous noise analysis tools described above may be avoided by calculating the crosstalk noise from coupling information in the SPEF (Standard Parasitic Exchange Format, IEEE 1481-1999 clause 9) file that is included in the floorplan of an integrated circuit design. The method of crosstalk noise analysis and correction of noise violations of the present invention may be incorporated into a delay estimator that reads the SPEF file with coupling capacitance and wire resistance information. In an alternative embodiment, the method of crosstalk noise analysis and correction of noise violations of the present invention may be implemented as a separate tool for use with an SPEF file. [0039] In one aspect of the present invention, a method of noise analysis for an integrated circuit design includes steps of: (a) receiving as input a standard parasitic exchange file for an integrated circuit design; (b) parsing the standard parasitic exchange file to generate a resistance graph; (c) generating a representation of the resistance graph to determine noise critical nets; (d) generating a list of only noise critical nets from the representation of the resistance graph; (e) selecting a net from the list of only noise critical nets; (f) calculating a value of total crosstalk noise in the selected net from all aggressor nets relative to the selected net; and (g) generating as output the value of total crosstalk noise in the selected net for correcting a possible noise violation. [0047] FIG. 1 illustrates a circuit model for a noise calculation according to an embodiment of the present invention. Shown in FIG. 1 are a victim net 102, a victim driver cell 104, receiver cells 106, and aggressors 108. [0048] The victim driver cell 104 and the receiver cells 106 constitute the victim net 102 that is representative of a fragment of a typical tree structure used, for example, in distributing a clock signal in an integrated circuit design. Each aggressor 108 generates a crosstalk noise VX coupled by a coupling capacitance Ccto the receiver cells 106. As shown in FIG. 1, one aggressor 108 may couple crosstalk into the victim net 102 at multiple receiver cells 106. To simplify the representation, each point into which crosstalk is coupled into the victim net 102 may be associated with a separate aggressor. [0049] FIG. 2 illustrates a simplified circuit model of FIG. 1 in which a separate aggressor is associated with each crosstalk coupling point. Shown in FIG. 2 are a victim net 102, a victim driver cell 104, receiver cells 106, and N aggressors 202. [0050] The crosstalk noise coupled into the victim net 102 may be estimated according to the formula: VX = ∑ m = 1 N VX m ( 1 ) To find the crosstalk noise VXm generated by the aggressor m, the circuit of FIG. 2 may be transformed with acceptable accuracy to the chain structure of FIG. 3. [0052] FIG. 3 illustrates a chain structure for calculating noise from each aggressor net in the simplified circuit model of FIG. 2. Shown in FIG. 3 are a victim net 302, a victim driver 304, an aggressor m net 306, an aggressor driver 308, a coupling capacitance 310, and a crosstalk noise VXm 312. [0053] In FIG. 3, the equivalent resistance of each of the receiver cells along the path from the victim driver 304 to the N coupling points in FIG. 2 from the aggressor m net 306 may be mapped as follows: R1=Rv5 (2) R2=Rs=Rv2 C1=Cv5 C2=Cv6 C3=Cs=Cv2 C cRest =C c1 +C c2 + . . . +C cm−1 +C cm+1 + . . . +C cN C vRest=(C v1 +C v2 + . . . +C vn)−(C 1 +C 2 + . . . +C N) [0054] FIG. 4 illustrates the circuit model of FIG. 3 further simplified to illustrate a noise calculation according to an embodiment of the present invention. Shown in FIG. 4 are a victim net 302, a victim driver 304, an aggressor m net 306, an aggressor driver 308, a coupling capacitance 310, and a crosstalk noise VXm 312. [0055] The values for Cv and Rvm may be calculated as follows: C v = C 1 + C 2 + … + C s + C vRest + C cRest = C v1 + C v2 + … + C vn + C cRest R vm = R v + R 1 + R 2 + … + R s = R v + R v_m ( 3 ) [0056] The crosstalk noise VXm 312 coupled into the victim net 302 by the aggressor m net 306 may be derived analytically from the model of FIG. 4 by the following formulas: VX m = V dd τ cm τ T · ( τ T τ m ) τ m τ m - τ T if τ m - τ T ≠ 0 VX m = V dd τ cm τ T · ⅇ - 1 if τ m - τ T = 0 ( 4 ) where: τm=(R m +R am)C m τcm=Rvm Ccm τT=Rvm CvT Vdd is the voltage of power supply in the design. e is natural log base; it comes from the solution of differential equations describing signal transition for this timing condition (τm−τT=0). In general, a timing transition is described as an exponential function of time V=EXP(−at). [0059] The resistance Rm is the equivalent transient resistance of the aggressor m net 306 that may be read from a cell library as the driver resistance of the aggressor driver 308 for selected operating conditions WC (worst case), BC (best case), and NC (nominal case). [0060] The resistance Ram is the wire resistance of the aggressor m net 306 from the aggressor driver 308 up to the coupling point to the victim net 302. Ram may be calculated as the sum of the wire segment resistances of the aggressor m net 306 retrieved from the SPEF (standard parasitic exchange format) file. Specifically, Ram is the sum of all wire resistances from the aggressor driver 308 to the coupling point of the parasitic capacitance Ccm to the victim net 302. The wire resistance Ram is a function of the nominal aggressor wire resistance Ram′, temperature, and a temperature coefficient tcoeff: R am =R am′(1+(temperature−25)*tcoeff) (5) where: temperature=115 in WC mode, −40 in BC mode, and 25 in NC mode; and tcoeff is a technology constant obtained by test chip measurements. [0064] The resistance Rvm is the effective resistance Rv of the victim driver 304 plus the nominal victim wire resistance Rv — m as shown in the formulas (3) above. The effective resistance Rv may be read from the cell library as the DC driver resistance of the victim driver 304 for the selected operating conditions WC (worst case), BC (best case), and NC (nominal case). The wire resistance Rv — m is a function of the nominal wire resistance Rv − m′, temperature, and a temperature coefficient tcoeff: R v — m′(1+(temperature−25)*tcoeff) (6) where: temperature=115 in WC mode, −40 in BC mode, and 25 in NC mode; and tcoeff is a technology constant obtained by test chip measurements. [0068] The wire resistance Rv — m may be calculated as the sum of the wire segment resistances from the victim driver 304 to the coupling point of the aggressor m net 306 as shown in the formulas (3) above, where the wire segment resistances R1, R2, . . . may be estimated from the SPEF file as discussed below in further detail. [0069] The capacitance Ccm is the coupling capacitance between the aggressor net m 306 and the victim net 302. The total net capacitance CvT is given by: C vT =C v +C cm (7) where Cv is given by the formula (3) above, so that: C v=(C v1 +C v2 + . . . +C vn)+(C c1 +C c2 + . . . +C cN) (8) All the capacitances on the right side of the formula (8) may be found in the SPEF file. [0072] The ratio rm of the coupling capacitance Ccm to the total net capacitance CvT may be expressed as: r m =C cm /C vT (9) The formulas (4) may then be simplified so that the individual noise VXm coupled from the aggressor net m 306 into the victim net 302 is given by: VX m = r m · V dd · ( τ T τ m ) τ m τ m - τ T if τ m - τ T ≠ 0 VX m = r m · V dd · ⅇ - 1 if τ m - τ T = 0 ( 10 ) [0074] In noise analysis, it is important to consider two types of possible noise. If the victim net is at a zero or low voltage state, and if the aggressor nets switch from zero to one, that is, the low-to-high transition, then peak noise is observed at the victim net. If the victim net is at a one or high voltage state, and if the aggressor nets switch from one to zero, that is, the high-to-low transition, then a noise drop is observed at the victim net. The model and formulas given above may be used to find both values of noise coupled into the victim net. For peak noise VXp, the victim driver resistance at low voltage and the aggressor driver resistance for the transition from low-to-high voltage are used. For the noise drop VXd, the victim driver resistance at high voltage and the aggressor driver resistance for the transition from high-to-low voltage are used. [0075] The nominal wire resistance Rv — m′ and the nominal aggressor wire resistance Ram′ may be estimated using the resistance available from the SPEF file as follows. Real net structure is a tree-like structure, and the same is true for a resistance graph of the net as shown in FIG. 1. However, the resistance structure in the SPEF file may not be a tree in the general case as illustrated in FIGS. 5A, 5B and 5C. [0076] FIGS. 5A, 5B, and 5C illustrate examples of net resistance graphs according to an embodiment of the present invention. Shown in FIGS. 5A, 5B and 5C are a victim driver 502, a victim net 504, receivers 506 and 508, aggressor net coupling capacitance Ccm 510, a noise coupling node 512, an additional resistance node 514, and wire resistances 516. [0077] FIG. 5A illustrates the victim net 504 with noise coupling from the aggressor net coupling capacitance Ccm 510. [0078] FIG. 5B illustrates a resistance graph of the victim net 504 that includes the wire resistances 516 R1, R2, R3, and R4 and the additional resistance node 514. [0079] FIG. 5C illustrates a resistance graph of the victim net 504 obtained from the SPEF file with no resistance nodes. [0080] FIG. 5D illustrates an example of a resistance tree constructed from the resistance net graph of FIG. 5C. In this representation of the resistance net graph, the number of resistances is minimized. [0081] FIG. 5E illustrates an example of a resistance star tree constructed from SPEF coordinates according to an embodiment of the present invention. [0082] The problem of finding the resistance tree from the SPEF resistance graph is a complex one, because it is not known how many additional resistance nodes 514 should be introduced or what is the structure of the resistance tree. Also, it is time consuming to calculate the appropriate wire resistances. [0083] One method of finding a resistance tree from the SPEF resistance graph is to build the minimum resistance tree illustrated in FIG. 5D, in which a resistance path from the victim driver 502 to each resistance node has a minimum resistance. The resistance tree may be found by the well-known technique of equal costs in graph theory, however, a disadvantage of this technique is that the values of some resistances may be overestimated. In the example of FIG. 5C, the actual resistance of the path from the victim driver 502 to the receiver 508 is (R1+(R5+R6)R7/(R5+R6+R7)). The resistance path found from the resistance tree in FIG. 5D is (R1+R7). [0084] Another method of finding a resistance tree from the SPEF resistance graph is to build the star tree illustrated in FIG. 5E using the coordinates of all resistance nodes that may be obtained from the SPEF file, where each wire resistance connects the victim driver 502 to a resistance node and has a value given by: R(driver, node)=R unit(|X driver −X node |+|Y driver −Y node|) (11) where Runit is the resistance of a unit length of the victim net wire, (Xdriver, Ydriver) are the driver coordinates, and (Xnode, Ynode) are the node coordinates. This formula may also be used to calculate the resistance of each path from the driver to each node. A disadvantage of this method is that some heuristics should be used to define the value of Runit for each net, because the value of Runit depends on the metal layer in which the net is implemented. [0086] To conserve computation time, a set of screening criteria may be used to identify those nets that are most likely to have a crosstalk violation and should be analyzed because noise may lead to false switching of a state cell, such as flip-flops, latches, and memories. A pin is identified herein to be noise critical if it is a pin of a state cell and if a signal transition on the pin can cause the cell to change state. A net (signal) is identified herein to be noise critical if the net contains a noise critical pin. [0087] There are several methods that may reduce the computation time for noise analysis by filtering out nets that do not require noise analysis because they are not subject to noise interference. On the other hand, other filtering techniques may be used to find nets that should be subjected to noise analysis. For example, the following filters may be used to determine which nets may be excluded from noise analysis: F1: nets that do not drive noise critical pins or cells that generate noise critical signals; F2: victim nets having small total capacitance, for example, less than 5 pf. F3: victim nets having a small coupling ratio: r=r1+r2+ . . . +rm+ . . . +rN<const, where const may be, for example, less than 0.5, and rm is a coupling ratio to aggressor m as described above with respect to formula (9); and [0092] F6: aggressor nets that have a small coupling to the victim net, for example, 0.05. [0093] The following filters may be used to determine which nets should be included in the noise analysis: F4: nets that drive noise critical pins; and F5: nets that drive cells that generate noise critical signals. [0096] Noise is not generally propagated through cells, however, a noise level that exceeds a usually high noise threshold value VP(cell) may propagate some propagated noise fraction F(cell) of the noise VX through the cell. A method of accounting for noise propagation through cells in estimating crosstalk noise according to an embodiment of the present invention is described as follows. [0097] Each cell is pre-characterized by determining values for the noise threshold value VP(cell) and the propagated noise fraction F(cell) and storing the values in a cell library according to well-known techniques. [0098] The filter F4 is applied during noise analysis to find the nets NETS(F4) that drive noise critical pins. In some cases, the filter F5 is applied to find the nets NETS(F5,C) that drive a cell C which generates a noise critical signal from the list in NETS(F4). The following rules describe the noise propagation through the cell C driven by a net N in the list NETS(F5,C): [0099] R1: If the net N has a noise level VX that is less than VP(C), then an additional noise VXa(N) equal to zero will be propagated through the cell C from the net N. [0100] R2: If the net N has a noise level VX that is greter than or equal to VP(C), then an additional noise VXa(N) at least equal to VX*F(C) will be propagated through the cell C from the net N. [0101] R3: If the cell C is driven by multiple nets from NETS(F5,C), then an additional noise VXa equal to the maximum value of VXa(N) will be propagated through the cell C from the multiple nets and should be added to the output net driven by the cell C. [0102] Two values of additional propagated noise may be calculated as described above for the peak noise VXap and the drop noise VXad. [0103] Each critical pin is pre-characterized by determining values for peak noise threshold VTp(pin) and drop noise threshold VTd(pin) and storing the values in the cell library according to well-known techniques. The following criteria may be used to determine whether a net failure will occur in the integrated circuit design: If the noise in a net N is greater than or equal to the noise threshold for a critical pin P: Failure criterion (1): VX p(N) ≧VT p(P) or (11) Failure criterion (2): VX d(N) ≧VT d(P) [0105] If a critical net N has several critical pins, then the following criteria may be used to determine whether a net failure will occur in the integrated circuit design: Failure criterion (1): VX p(N) ≧VT p(N) or (12) Failure criterion (2): VX d(N) ≧VT d(N) where VTp(N) and VTd(N) are noise thresholds for the net N: VT p(N)=min{VT p(P)} for all critical pins P in the net N (13) VT d(N)=min{VT d(P)} for all critical pins P in the net N [0107] FIG. 6 illustrates a flow chart 600 of a method of analyzing crosstalk noise according to an embodiment of the present invention. [0108] Step 602 is the entry point of the flow chart 600. [0109] In step 604, an SPEF file for an integrated circuit floorplan design is received as input. [0110] In step 606, the SPEF file is parsed to generate a resistance graph. The resistance graph contains all the information from the SPEF file to facilitate future processing and access. For example, the resistance graph may be a data structure that provides the cell type for each cell instance, the driver for each net in the integrated circuit design, and so on. [0111] In step 608, a representation of the resistance graph is constructed from the resistance graph. The representation of the resistance graph may be, for example, a resistance tree or a resistance star tree as described above with reference to FIGS. 5D and 5E. [0112] In step 610, the nets in the representation of the resistance graph are filtered using the filters F2 and F3 described above to exclude nets that are not subject to false switching from crosstalk noise. [0113] In step 612, the nets in the representation of the resistance graph are filtered using the filter F4 described above to include nets that drive logical stages that drive noise critical nets. [0114] In step 614, a list of the nets that were not excluded in step 610 and the nets that were included in step 612 are generated as output in a list of nets NETS(F4). The list of nets NETS(F4) includes only noise critical nets that may be subject to false switching from crosstalk noise and nets that drive logical stages that drive noise critical nets. [0115] In step 616, a net from the list NETS(F4) is selected. [0116] In step 618, a noise VX from all aggressor nets relative to the selected net in the representation of the resistance graph is calculated as described in further detail below from the pre-characterized information stored in the cell library as described above. [0117] In step 620, after calculating the noise propagated into the selected net from all aggressor nets, an additional check is performed to consider the maximum possible noise that may be propagated into the selected net from the previous logical stage. [0118] In step 622, noise violations are reported so that they may be corrected by modifying the floorplan of the integrated circuit design as described in further detail below. For example, the report may include the name of the victim net in which the noise violation occurred along with the noise peak/drop and the names of the victim net's top ten aggressors. [0119] In step 624, if all nets in the list NETS(F4) have been selected, then control is transferred to step 626. Otherwise, control is transferred to step 616. [0120] Step 626 is the exit point of the flow chart 600. [0121] FIG. 7 illustrates a flow chart 700 for calculating noise in the selected net in the method of FIG. 6. [0122] Step 702 is the entry point of the flow chart 700. [0123] In step 704, a graph model of the selected net is constructed as described above with respect to FIGS. 5B and 5C. The graph model may contain resistive loops, as illustrated in FIG. 5C. [0124] In step 706, a tree model is constructed from the graph model as described above with respect to FIGS. 5D and 5E. [0125] In step 708, the values for the peak noise VXp(N) and the drop noise VXd(N) from all aggressors relative to the selected net are calculated as described above with respect to the formulas (10). The values of the aggressor noise are then compared in steps 710 and 712 to determine whether propagated noise contributes to the noise in the selected net. [0126] In step 710, if the peak noise VXp(N) is less than the peak noise threshold minus the peak propagation noise threshold (VTp(N)−VPp), then control is transferred to step 712. Otherwise, control is transferred to step 714. [0127] In step 712, if the drop noise VXd(N) is greater than or equal to the drop noise threshold minus the drop propagation noise threshold (VTd(N)−VPd), then control is transferred to step 714. Otherwise, control is transferred to step 718. [0128] In step 714, the values of the peak propagated noise VXap and the drop propagated noise VXad are calculated using the rules R1, R2, R3 and the filter F5 as described above for the selected net. [0129] In step 716, the values calculated for the propagated noise are added to the values calculated for the peak noise VXp(N) and the drop noise VXd(N) in step 708. [0130] Step 718 is the exit point of the flow chart 700. [0131] FIG. 8 illustrates a flow chart for performing an additional check to consider noise propagated into the selected net from the previous logical stage in the method of FIG. 6. [0132] Step 802 is the entry point of the flow chart 800. [0133] In step 804, the calculated peak noise VXp(N) is compared to the pre-characterized peak noise threshold VTp(N) stored in the cell library. If VXp(N) is less than VTp(N), then control is transferred to step 806. Otherwise, control is transferred to step 808. [0134] In step 806, the calculated drop noise VXd(N) is compared to the pre-characterized drop noise threshold VTd(N) stored in the cell library. If VXd(N) is less than VTd(N), then control is transferred to step 810. Otherwise, control is transferred to step 808. [0135] In step 808, a noise report is constructed for the selected net including the name of the selected victim net, the peak noise VXp(N), the drop noise VXd(N), the names of the ten most significant aggressor nets and their respective contribution to the noise propagated into the selected victim net. [0136] Step 810 is the exit point of the flow chart 800. [0137] The noise violations in the integrated circuit design found may be corrected using the calculations described above to perform appropriate modifications to the floorplan of the integrated circuit design. Specifically, the driver power of a victim net may be increased, the driver power of an aggressor net may be decreased, a buffer may be inserted in the victim net to reduce net delay, and a buffer may be inserted in the aggressor net to reduce net delay as described in further detail below. If the crosstalk still exceeds the crosstalk peak or drop noise thresholds of the victim net, the victim net and its aggressors may be re-routed according to well-known techniques. Advantageously, the correction of a noise violation in accordance with the method of the present invention may be performed in a single pass, in contrast to previous methods of correcting noise violations that typically require multiple lengthy calculations. [0138] FIGS. 9A, 9B and 9C illustrate a flow chart 900 for correcting a noise violation according to an embodiment of the present invention. [0139] Step 902 is the entry point of the flow chart 900. [0140] In step 904, a victim net for which a noise violation is reported as described above is selected. [0141] In step 906, if the selected victim net is also an aggressor net to another noise critical net, then control is transferred to step 912. Otherwise, control is transferred to step 908. [0142] In step 908, the driver of the selected victim net is “up-sized”, that is, replaced with a driver having higher drive power, and the crosstalk into the victim net is recalculated for the new victim driver. [0143] In step 910, if the selected victim net still has a noise violation, then control is transferred to step 912. Otherwise, control is transferred to step 944. [0144] In step 912, if the selected victim net is timing critical, then control is transferred to step 918. Otherwise control is transferred to step 914. The selected victim net is timing critical if it belongs to a timing critical path. A path is timing critical if its delay is close to the clock period, for example, within ten percent. [0145] In step 914, a buffer is inserted in the selected victim net to reduce net delay according to well-known techniques, and the crosstalk into the selected victim net is recalculated with the new buffer. [0146] In step 916, if the selected victim net still has a noise violation, then control is transferred to step 918. Otherwise, control is transferred to step 944. [0147] In step 918, the most significant aggressor net relative to the victim net is selected, that is, the aggressor net coupling the greatest amount of crosstalk noise into the selected victim net that has not been previously selected. [0148] In step 920, if the selected aggressor net is timing critical, then control is transferred to step 930. Otherwise, control is transferred to step 922. [0149] In step 922, if the selected aggressor net is noise critical, then control is transferred to step 924. Otherwise, control is transferred to step 926. [0150] In step 924, if the selected aggressor net has a noise violation, then control is transferred to step 930. Otherwise, control is transferred to step 926. [0151] In step 926, the driver of the selected aggressor net is “down-sized”, that is, replaced with a driver having a lower drive power, preferably the lowest possible drive power, and the crosstalk into the selected victim net is recalculated with the new driver. [0152] In step 928, if the selected victim net has a noise violation, then control is transferred to step 930. Otherwise, control is transferred to step 944. [0153] In step 930, if a buffer may be inserted in the selected aggressor net to reduce net delay, then control is transferred to step 932. Otherwise, control is transferred to step 936. [0154] In step 932, a buffer is inserted in the selected aggressor net, and the crosstalk into the selected victim net is recalculated with the new buffer. [0155] In step 934, if the selected victim net has a noise violation, then control is transferred to step 936. Otherwise, control is transferred to step 944. [0156] In step 936, if there is another aggressor net relative to the victim net that has not been selected, then control is transferred back to step 918. Otherwise, control is transferred to step 938. [0157] In step 938, the routing of the selected victim net and its aggressors is modified to minimize crosstalk coupling into the victim net according to well-known techniques. [0158] In step 940, if the noise violation(s) were successfully corrected by the modifications in step 938, then control is transferred to 944. Otherwise, control is passed to step 942. [0159] In step 942, a noise violation is reported in the selected victim net, and control is transferred to step 944. [0160] Step 944 is the exit point of the flow chart 900. [0161] As may be appreciated from the method of noise analysis and correction of noise violations according to the present invention described above, the effect of crosstalk noise on the performance of an integrated circuit design may be estimated more quickly and more simply compared to previous methods. Advantageously, the only input required is the SPEF file that is already available from the design flow. The SPEF file includes all the values of the capacitances, coupling capacitances, resistances, cell types, and cell coordinates. The models developed according to the method of the present invention produce results comparable to SPICE modeling at a much lower cost and turnaround time. [0162] Unique features of the noise analysis and correction of noise violations according to the method of the present invention include selecting only noise critical nets and nets that propagate noise into noise critical nets for noise analysis, incorporating different noise threshold values for different cells and pins, the calculation of both peak and drop noise for each selected noise critical net, and the modification of the floorplan to correct possible noise violations. [0163] Although the method of the present invention illustrated by the flowchart descriptions above are described and shown with reference to specific steps performed in a specific order, these steps may be combined, sub-divided, or reordered without departing from the scope of the claims. Unless specifically indicated herein, the order and grouping of steps is not a limitation of the present invention. [0164] The steps described above with regard to the flow charts described above may also be implemented by instructions performed on a computer according to well-known computer programming techniques. [0165] In another aspect of the present invention, a computer program product for analyzing noise for an integrated circuit design includes: a medium for embodying a computer program for input to a computer; and a computer program embodied in the medium for causing the computer to perform steps of: (a) receiving as input a standard parasitic exchange file for an integrated circuit design; (b) parsing the standard parasitic exchange file to generate a resistance graph; (c) generating a representation of the resistance graph to determine noise critical nets; (d) generating a list of only noise critical nets from the representation of the resistance graph; (e) selecting a net from the list of only noise critical nets; (f) calculating a value of total crosstalk noise in the selected net from all aggressor nets relative to the selected net; and (g) generating as output the value of total crosstalk noise in the selected net for correcting a possible noise violation. [0175] While the invention herein disclosed has been described by means of specific embodiments and applications thereof, numerous modifications and variations could be made thereto by those skilled in the art without departing from the scope of the invention set forth in the following claims. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5535133 *Feb 9, 1995Jul 9, 1996Unisys CorporationMethod of fabricating IC chips with table look-up estimated crosstalk voltages being less than noise marginUS5555506 *Feb 9, 1995Sep 10, 1996Unisys CorporationMethod of fabricating IC chips with equation estimated statistical crosstalk voltages being less than noise marginUS5568395 *Jun 29, 1994Oct 22, 1996Lsi Logic CorporationModeling and estimating crosstalk noise and detecting false logicUS5596506 *Feb 9, 1995Jan 21, 1997Unisys CorporationMethod of fabricating IC chips with equation estimated peak crosstalk voltages being less than noise marginUS6327542 *Jul 21, 1999Dec 4, 2001Hewlett-Packard CompanySystem and method for approximating the coupling voltage noise on a nodeUS6363516 *Nov 12, 1999Mar 26, 2002Texas Instruments IncorporatedMethod for hierarchical parasitic extraction of a CMOS designUS6378109 *Jun 30, 2000Apr 23, 2002Texas Instruments IncorporatedMethod of simulation for gate oxide integrity check on an entire ICUS6493853 *Jul 17, 2000Dec 10, 2002Texas Instruments IncorporatedCell-based noise characterization and evaluationUS6499131 *Jun 30, 2000Dec 24, 2002Texas Instruments IncorporatedMethod for verification of crosstalk noise in a CMOS designUS6523149 *Sep 21, 2000Feb 18, 2003International Business Machines CorporationMethod and system to improve noise analysis performance of electrical circuitsUS6601222 *Oct 13, 2000Jul 29, 2003International Business Machines CorporationCoupled noise estimation and avoidance of noise-failure using global routing informationUS6615395 *Dec 20, 1999Sep 2, 2003International Business Machines CorporationMethod for handling coupling effects in static timing analysisUS6732339 *Nov 20, 2002May 4, 2004Texas Instruments IncorporatedCell-based noise characterization and evaluationUS6853967 *Dec 30, 1999Feb 8, 2005Intel CorporationMethod and apparatus for calculating interconnect noise due to cross capacitance in the presence of line resistanceUS6990420 *May 10, 2004Jan 24, 2006Lsi Logic CorporationMethod of estimating a local average crosstalk voltage for a variable voltage output resistance model* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6990420 *May 10, 2004Jan 24, 2006Lsi Logic CorporationMethod of estimating a local average crosstalk voltage for a variable voltage output resistance modelUS7017130 *Jul 12, 2004Mar 21, 2006Chang Gung UniversityMethod of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuitsUS7124381 *May 25, 2004Oct 17, 2006Chang Gung UniversityMethod of estimating crosstalk noise in lumped RLC coupled interconnectsUS7131084 *Dec 9, 2003Oct 31, 2006International Business Machines CorporationMethod, apparatus and computer program product for implementing automated detection excess aggressor shape capacitance coupling in printed circuit board layoutsUS7181711Apr 27, 2005Feb 20, 2007International Business Machines CorporationPrioritizing of nets for coupled noise analysisUS7409659 *Nov 12, 2004Aug 5, 2008Agere Systems Inc.System and method for suppressing crosstalk glitch in digital circuitsUS7506276 *May 26, 2005Mar 17, 2009International Business Machines CorporationMethod for isolating problem networks within an integrated circuit designUS7596099 *Aug 22, 2005Sep 29, 2009Motorola, Inc.Method and apparatus for managing a communication linkUS20050125752 *Dec 9, 2003Jun 9, 2005International Business Machines CorporationMethod, apparatus and computer program product for implementing automated detection excess aggressor shape capacitance coupling in printed circuit board layoutsUS20050251354 *May 10, 2004Nov 10, 2005Weiqing GuoMethod of estimating a local average crosstalk voltage for a variable voltage output resistance modelUS20050278668 *May 25, 2004Dec 15, 2005Chang Gung UniversityMethod of estimating crosstalk noise in lumped RLC coupled interconnectsUS20060010406 *Jul 12, 2004Jan 12, 2006Chang Gung UniversityMethod of verification of estimating crosstalk noise in coupled rlc interconnects with distributed line in nanometer integrated circuitsUS20060069537 *Sep 29, 2004Mar 30, 2006Lihui CaoMethod for simulating noise in an integrated circuit systemUS20060100830 *Nov 5, 2004May 11, 2006Chang Gung UniversityMoment computations of nonuniform distributed coupled RLC trees with applications to estimating crosstalk noiseUS20060107245 *Nov 12, 2004May 18, 2006Kanad ChakrabortySystem and method for suppressing crosstalk glitch in digital circuitsUS20060248485 *Apr 27, 2005Nov 2, 2006International Business Machines CorporationPriortizing of nets for coupled noise analysisUS20060271893 *May 26, 2005Nov 30, 2006International Business Machines CorporationMethod for isolating problem networks within an integrated circuit designUS20070060186 *Aug 22, 2005Mar 15, 2007Ganesan Eshwar PMethod and apparatus for managing a communication link* Cited by examinerClassifications U.S. Classification716/115International ClassificationG06F17/50, G06F9/45Cooperative ClassificationG06F17/5036European ClassificationG06F17/50C4Legal EventsDateCodeEventDescriptionSep 17, 2003ASAssignmentOwner name: LSI LOGIC CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TETELBAUM, ALEXANDER;REEL/FRAME:014554/0128Effective date: 20030909Dec 4, 2009FPAYFee paymentYear of fee payment: 4Nov 13, 2013FPAYFee paymentYear of fee payment: 8May 8, 2014ASAssignmentOwner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGFree format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031Effective date: 20140506Jun 6, 2014ASAssignmentOwner name: LSI CORPORATION, CALIFORNIAFree format text: CHANGE OF NAME;ASSIGNOR:LSI LOGIC CORPORATION;REEL/FRAME:033102/0270Effective date: 20070406Apr 3, 2015ASAssignmentOwner name: AVAGO TECHNOLOGIES GENERAL IP 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