Source: http://www.google.com/patents/US8180951?ie=ISO-8859-1
Timestamp: 2015-03-31 23:59:08
Document Index: 247708198

Matched Legal Cases: ['art 12', 'art 12', 'art 211', 'art 12', 'art 13', 'art 12', 'art 13', 'art 122', 'art 213', 'art 213', 'art 213', 'art 211', 'art 211', 'art 12']

Patent US8180951 - Memory system and method of controlling the memory system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA memory system for transmitting data to and receiving data from a host apparatus includes a semiconductor memory and an access-controlling part. The semiconductor memory has storage areas identified by physical addresses, stores data in each of the storage areas, performs data write in accordance with...http://www.google.com/patents/US8180951?utm_source=gb-gplus-sharePatent US8180951 - Memory system and method of controlling the memory systemAdvanced Patent SearchPublication numberUS8180951 B2Publication typeGrantApplication numberUS 11/687,087Publication dateMay 15, 2012Filing dateMar 16, 2007Priority dateMar 16, 2006Also published asUS20070220216Publication number11687087, 687087, US 8180951 B2, US 8180951B2, US-B2-8180951, US8180951 B2, US8180951B2InventorsTakashi OshimaOriginal AssigneeKabushiki Kaisha ToshibaExport CitationBiBTeX, EndNote, RefManPatent Citations (12), Non-Patent Citations (2), Classifications (9), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMemory system and method of controlling the memory system
A semiconductor memory such as a NAND-type flash memory, from and into which some data items of a predetermined size can be read and written, may be incorporated in a memory card that is to be connected to a host apparatus (See, for example, Jpn. Pat. Appln. KOKAI Publication No. 7-122088.). In such a semiconductor memory, the process time in response to an access may vary in accordance with the address of the memory to which the host apparatus accesses. The �process time� in response to an access is the time required to write or read data into or from the semiconductor memory.
As shown in FIG. 1, the memory card according to the first embodiment of this invention is a memory card 10 that can transmit data to and receive from a host apparatus 20. The memory card 10 comprises a semiconductor memory 11 and an access control part 12. The semiconductor memory 11 can be accessed from the host apparatus 20. The access control part 12 determines a recommended address to be accessed, from the operation information about the memory card 10. The recommended address thus determined is output to the host apparatus 20. Data to which the recommended address is allocated is read from, or written into, the semiconductor memory 11. Data to which the recommended address is allocated can be written faster than data with any other addresses at the time certain data writing is completed. The �operation information� represents a factor that influences the process time in response to an access to the semiconductor memory 11, such as the data-storage state or the functions of the semiconductor memory 11.
A specific logic block-address (LBA) is assigned to a block (hereinafter referred to as �small block�) that is composed of a plurality of data items of a predetermined size. In the memory card 10, data is read and written from and into the semiconductor memory 11 in the LBA order in units of small blocks. The small blocks are stored in a block (hereinafter referred to as �large block�) of a predetermined size in the semiconductor memory 11. In the scheme where the small blocks should be stored in the large block in the LBA order, storing small blocks with non-sequential LBAs involves moving small blocks stored in the large block in order to store small blocks in a large block in the LBA order. FIG. 2 shows exemplar small blocks and large blocks. As FIG. 2 shows, a small block is comprised of data for 4�8 pages, each being 528 bytes. As FIG. 2 shows, too, a large block is comprised of 2112 bytes�128 pages and can therefore store 16 small blocks, each being 2112 bytes (4 pages)�8 pages.
The process of rearranging small blocks in a large block so that the small blocks may be stored in the LBA order will be called �re-storing� hereinafter. When the re-storing is performed, the time required to write data will increase. In other words, the process speed (access speed) of the memory will decrease when the memory operates in response to an access the host apparatus 20 has made.
Writing Small blocks having sequential LBAs into a large block does not require re-stored. Such small blocks are only needed to be �sequentially added (incrementally written)� in a vacant area in a large block. Hence, the access speed for writing small blocks with sequential LBAs is higher than that for writing small blocks with non-sequential LBAs. To �sequentially add (incrementally write) the small blocks� represents writing small blocks in a large block without performing the re-storing of small blocks.
The size of a block, which corresponds to the erase unit in the semiconductor memory 11 and hereinafter referred to as �erase-block size�, is equal to the size of the large block. The semiconductor memory 11 can be, for example, a NAND-type flash memory
A method of writing data into the semiconductor memory 11 shown in FIG. 1 will be explained with reference to FIGS. 3 to 6. In FIGS. 3 to 6, the small block LBA00 h, for example, is a small block allocated with LBA�00 h�. As shown in FIG. 3, small blocks LBA00 h to LBA0Fh are stored in the large block B1. Small blocks LBA10 h to LBA1Fh are stored in the large block B2. The small blocks LBA07 h and LBA08 h and the small blocks LBA14 h to LBA18 h are hatched in FIG. 3. This means small blocks identical in LBA to hatched small blocks have been written elsewhere in the semiconductor memory 11. More precisely, small blocks LBA07 h to LBA08 h are stored in the large block B3, and small blocks LBA14 h to LBA18 h are stored in the large block B4. The small blocks LBA07 h and LBA08 h stored in the large block B1 and the small blocks LBA14 h to LBA18 h stored in the large block B2 can be erased because they are not used. Nevertheless, the small blocks LBA07 h and LBA08 h and the small blocks LBA14 h to LBA18 h stored in the large blocks B1 and B2, respectively, are not erased to remain in the semiconductor memory 11 because the data is erased in units of large blocks in the semiconductor memory 11. Hereinafter, any large blocks that cannot hold new small blocks written, such as block B1 and block B2, will be referred to as �old assign blocks�. On the other hand, any large blocks that can hold new small blocks written, such as block B3 and block B4, will be referred to as �new assign blocks�.
How the memory card system comprising the memory card 10 and the host apparatus 20, both shown in FIG. 1, operates will be explained with reference to the timing chart of FIG. 7. The timing chart of FIG. 7 explains how the system operates if the memory card 10 has an interface identical to that of an NAND-type flash memory. The signals shown in the timing chart of FIG. 7 are control signals and the like for controlling the NAND-type flash memory shown in FIG. 8. Signal �DATA� shown in FIG. 8 represents the commands, addresses and data that are transferred between the memory card 10 and the host apparatus 20. Signal �DATA� is combined with signal �CLE�, �−WE�, �ALE� and �−RE�, to distinguish a command, an address and data from one another. Signal �−CE� indicates an access to the memory card 10. Signal �R/−B� indicates the internal state of the memory card 10. Signal �−WP� inhibits data-writing into the memory card 10. Any signal with the sign �−� is valid at low level. Any signal with no sign �−� is valid at high level.
At time t0 shown in the timing chart of FIG. 7, a data-input command �80 h� is input as signal �DATA� to the memory card 10. Next, one-page data is transferred from the buffer part 211 to the memory card 10. The data transferred is stored into the memory card 10. Then, at time t1, a write command �10 h� is input, as signal �DATA�, to the memory card 10. In the memory card 10, the data is written in a large block contained in the semiconductor memory 11. The access control part 12 monitors the data-storage state of the semiconductor memory 11 and writes a recommended address into the recommended-address storage part 13. Assume that the semiconductor memory 11 has the data-storage state of FIG. 3 at time t2. In this case, the access control part 12 selects LBA�09 h� and LBA�19 h�, which can be sequentially added, as recommended addresses.
At time t2, a status-read command �70 h� is input, as signal �DATA�, to the memory card 10. Status-reading is therefore performed to determine whether data was successfully written or not in the memory card 10. The memory card 10 that has received the status-read command outputs a status signal ST at time t3. The status signal ST indicates whether the write process has been successfully performed.
At time t4 or thereafter, a recommended address is output, as signal �DATA�, from the memory card 10 to the host apparatus 20. The recommended-address storage part 13 may store LBA�09 h� and LBA�19 h�. If so, the address-outputting part 122 outputs LBA�09 h� at time t4, and LBA�19 h� at time t5, to the output control part 213.
The output control part 213 selects LBA�09 h� or LBA�19 h� as the LBA of the small block that is to be transferred to the memory card 10. Then, the output control part 213 transfers a small block which is allocated with LBA�09 h� or LBA�19 h�, if any in the buffer part 211, to the memory card 10. In the memory card 10, the small block allocated with LBA�09 h� or the small block allocated with LBA�19 h� are written into the semiconductor memory 11. As a result, no re-storing is performed in the semiconductor memory 11. This suppresses an increase in the write time, due to re-storing. However, re-storing may be necessary to be performed in the next data-writing process if the buffer part 211 stores no small blocks allocated with recommended addresses.
In the aforementioned instance, the recommended addresses are LBAs that can be sequentially added to the large blocks contained in the semiconductor memory 11. That is, the access control part 12, in order to determine the recommended addresses, uses LBAs that can be sequentially added in the semiconductor memory 11 and are selected depending on the data-storage state of the memory 11 as operation information. Alternatively, the physical address (PBA) of the semiconductor memory 11, which suppresses the decrease in the speed with which new data is written immediately into the memory 11, can be used as a recommended address. Still alternatively, a PBA that allows a write process at high reliability can be used as a recommended address. Note that �PBA� is an address actually allocated to the memory, the output/input port, or the like. PBAs that can be used as recommended addresses will be exemplified.
FIG. 9 shows an example of the semiconductor memory 11, which comprise a plurality of NAND-type flash memory chips. Hereinafter, the page buffer included in a memory chip and a memory cell whose pages share the page buffer will be called �district�. That is, FIG. 9 illustrates a semiconductor memory that has two districts D1 and D2. The district D1 comprises a memory-cell unit D11 and a page buffer D12. The page buffer D12 stores one-page data. In the write process, data is transferred at a time from the page buffer D12 to the memory-cell unit D11. In the read process, the one-page data stored in the memory-cell unit D11 is stored at a time into the page buffer D12. Like the district D1, the district D2 comprises a memory-cell unit D21 and a page buffer D22. Pages P1 and P2 that are shaded in FIG. 9 and have been stored in the memory-cell units D11 and D21, respectively, are pages that have been read or written.
Assume that, as shown in FIG. 11, a lower page A and an upper page B share the memory-cell unit having pages 0 to 127. With One memory cell capable of storing two bits, a �lower page� consists of the lower bits of a page identified by one address, and an �upper page� consists of the upper bits of that page. For example, the lower page identified by the uppermost address in the left column of FIG. 11 is handled as page 0, while the upper page identified by the uppermost address in the left column is handled as page 4.
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