Source: https://patents.google.com/patent/US8214570?oq=6721967
Timestamp: 2018-04-24 17:41:58
Document Index: 543801167

Matched Legal Cases: ['Application No. 10179814', 'Application No. 07121085', 'Application No. 05025388', 'Application No. 07121085', 'Application No. 0502538', 'Application No. 00975263']

US8214570B2 - Memory controller and method utilizing equalization co-efficient setting - Google Patents
Memory controller and method utilizing equalization co-efficient setting Download PDF
US8214570B2
US8214570B2 US13196840 US201113196840A US8214570B2 US 8214570 B2 US8214570 B2 US 8214570B2 US 13196840 US13196840 US 13196840 US 201113196840 A US201113196840 A US 201113196840A US 8214570 B2 US8214570 B2 US 8214570B2
US13196840
US20110289245A1 (en )
A chip includes a transmitter circuit and a register provided to store a value representative of an equalization co-efficient setting. The transmitter circuit includes an output driver configured to adjust an output data signal based at least in part on the equalization co-efficient setting.
This application is a continuation of U.S. patent application Ser. No. 12/479,679, filed Jun. 5, 2009, entitled “System and Dynamic Random Access Memory Device Having a Receiver,” now U.S. Pat. No. 8,001,305, which is a continuation of U.S. patent application Ser. No. 11/929,974, filed Oct. 30, 2007, now U.S. Pat. No. 7,565,468, which is a continuation of U.S. application Ser. No. 11/672,018, filed Feb. 6, 2007, now abandoned which is a continuation of U.S. patent application Ser. No. 11/181,411, filed Jul. 13, 2005, now U.S. Pat. No. 7,174,400, which is continuation of U.S. patent application Ser. No. 11/073,403, filed on Mar. 4, 2005, now U.S. Pat. No. 7,032,058, which was a continuation of U.S. patent application Ser. No. 10/742,247, filed Dec. 19, 2003, now U.S. Pat. No. 7,032,057, which is a continuation of U.S. patent application Ser. No. 10/359,061, filed Feb. 4, 2003, now U.S. Pat. No. 6,684,263, which was a continuation of U.S. patent application Ser. No. 09/910,217, filed Jul. 19, 2001, now U.S. Pat. No. 6,516,365, which was a continuation of U.S. patent application Ser. No. 09/420,949 filed Oct. 19, 1999, now U.S. Pat. No. 6,321,282, the contents of which are incorporated by reference herein in their entirety.
A bus system is a chip-to-chip electronic communications system in which one or more slave devices are connected to, and communicate with, a master device through shared bus signal lines. FIG. 1 illustrates in block diagram form a bus system. The bus system includes a Master control device (M) that communicates with one or more Slave devices (D) via a bi-directional data bus. Typically, the bi-directional data bus comprises a plurality of bus signal lines, but for simplicity, FIG. 1 illustrates only one bus signal line. The terms bus signal line and channel are used synonymously herein. Thus, it will be understood that the data bus includes many channels, one for each bit of data. Each bus signal line terminates on one side at an I/O pin of the master device and terminates on its other side at one end of a resistive terminator (T). The resistance of the terminator is closely matched to the loaded impedance, ZL, of the bus signal line to minimize reflections and absorb signals sent down the bus signal line toward the terminator. The opposite end of the terminator is connected to a voltage supply that provides an AC ground and sets the DC termination voltage of the bus signal line. The positions along the bus signal line tapped by the Master terminator, and Slaves are labeled pM, pT, and p1- - - pN, respectively.
Z 0 ⁢ ⁢ L = R S + j ⁢ ⁢ wL 0 G P + j ⁢ ⁢ wC I
Z L = L o · d ( C o · d ) + C I
FIG. 11 illustrates the effect of position-dependent channel characteristics on binary signaling between the master device and various slave devices in a system. FIG. 11A shows what a . . . 101010 . . . binary data pattern might look like when it is transmitted at the Master. The signal at the Master has a fairly large amplitude given by the equation Vswing,M=(VOH,M-VOL,M)=(VTerm-VOL,M)=(VL+VH),M and has sharp rise and fall times indicated in FIG. 11A as tr and tf, respectively. Additionally, the transmitted signal is asymmetric relative to the reference voltage, vref. The amount of asymmetry is measured by the equation:
Asym = V L - V H V L + V H
In some embodiments described below, an integrated circuit device includes an output driver, a first register to store a value representative of a drive strength setting of the output driver, wherein the value is determined based on information stored in a supplemental memory device external to the integrated circuit memory device, and a transmitter circuit configurable to receive the value representative of a drive strength setting of the output driver. The output driver is configurable to output data synchronously with respect to an external clock signal.
In some other embodiments described below, an integrated circuit memory device includes an output driver; a first register to store a value representative of a drive strength setting of the output driver, wherein the value is determined based on information stored in a supplemental memory device external to the integrated circuit memory device; a transmitter circuit configurable to receive the value representative of a drive strength setting of the output driver; a locked loop circuit to generate an internal transmit signal, wherein the transmitter circuit outputs the data in response to the internal transmit signal; and a second register to store a value representative of a transmit timing offset to apply to the internal transmit signal.
In some embodiments described below, a method of operation in a system including a first integrated circuit device coupled to a second integrated circuit device, the method includes initializing the system; deriving a value, representative of a drive strength setting of an output driver disposed on the first integrated circuit device, based on information pertaining to the second integrated circuit device stored in a supplemental memory device external to the first integrated circuit device; programming the value into a register disposed on the first integrated circuit device; and outputting data using the output driver utilizing the derived value.
In some embodiments described below, a method of operation in an integrated circuit memory device includes determining a value, representative of a drive strength setting of an output driver disposed on the integrated circuit memory device based on information pertaining to a second integrated circuit device, wherein the information is stored in a supplemental memory device external to the integrated circuit memory device; storing the determined value in a first register disposed on the integrated circuit memory device; providing data to an output driver, wherein the output driver utilizes a value representative of a drive strength setting of the output driver; and outputting the data synchronously with respect to an external clock signal.
In some embodiments described below, a memory module includes a serial presence detect memory device; and a plurality of memory devices including a first memory device. The first memory device includes an output driver; a first register to store a value representative of a drive strength setting of the output driver, wherein the value is determined based on information stored in a supplemental memory device external to the integrated circuit memory device; and a transmitter circuit configurable to receive the value representative of a drive strength setting of the output driver. The output driver is configurable to output data synchronously with respect to an external clock signal.
In the illustrated embodiment, four Slew Rate Adjustments Blocks 442 a-d are connected in parallel with Base Block 440, although any arbitrary number may be used consistent with the present invention. Slew Rate Adjustment Blocks 442 a and 442 b are responsive to slew rate control signals from Slew Rate Estimator 410. Slew Rate Control Blocks 442 c and 442 d are responsive to slew rate control signals from Slew Rate Control Register 394. The slew rate of the signal on line 421 increases with the number of enabled Slew Rate Adjustment Blocks 442. In one embodiment each Slew Rate Adjustment Block 442 includes a Control Block 448 connected in series with a Stacked Transistor Pair 450. When enabled by their associated slew rate control signals Control Blocks 448 enable their associated Stacked Transistor Pairs 450 to be responsive to the data signal on line 419. Each Control Block 448 includes a NAND gate 449 and a NOR gate 451. NAND gate 449 enables the p-channel transistor T5 of Transistor Stack 450 and NOR gate 451 enables re-channel transistor T6. The output 452 of each Stacked Transistor Pair 450 connects to q-node 421.
FIG. 19 illustrates schematically Output Current Driver 422, which controls both the voltage swing at the output pins of the transmitting device and the average level of that swing in response to Current/Symmetry control bits cc. (In the interests of simplicity, FIG. 19 omits circuitry for equalizing the output signal from Output Current Driver 422.) Output Current Driver 422 includes multiple Transistor Stacks 460-472 connected in parallel between Bus 330 and ground. Each Transistor Stack 460-472 includes two re-channel transistors, an upper transistor and a lower transistor that are connected in series. The q-node signal on line 421 is input to the gate of the upper transistors T10, T12, T14, T16, T18, T20 and T22. Current/symmetry control signals on a set of current/symmetry control bits, cc through cc, are input to the gate of the lower transistors T11, T13, T15, T17, T21 and T23. When each of the current/symmetry control signals is at or exceeds the threshold voltage (Vth) of the lower transistor, the corresponding lower transistor T11, T13, T15, T17, T21 and T23 is enabled or “on.” When a lower transistor T11, T13, T15, T17, T21 or T23 is enabled and when the q-node signal transitions high (i.e., to its logic high voltage), a predetermined amount of current flows through the selected Transistor Stack to the circuit ground. Therefore, the output drive current is adjusted by setting a subset of the current/symmetry control signals to a high voltage level.
FIG. 26A illustrates, in block diagram form, an embodiment 700A of Output Current Driver 422 that dynamically adjusts its drive strength to compensate for voltage margins caused by residual signals on the same channel. Output Current Drive 700A adjusts its drive current in response to the topography dependent parameter stored in Equalization Control Register 401. In other words, Output Current Driver 700A performs temporal equalization in response to a topography dependent parameter. In the interests of simplicity, FIG. 26A omits circuitry related to Current/Symmetry control. To accommodate Output Current Driver 700A, Equalization Control Register 401 is preferably realized as a multiplicity of Equalization Control Registers (ECRs), ECRL 401-1 through ECRk 401-k, each storing a topography dependent equalization coefficient, ceq. Output Current Driver 700A includes Weighted Driver 701, a multiplicity of Equalization Drivers 702-1 to 702-K, and Data History Generator 705. Weighted Driver 701, which may be implemented using the same circuitry as shown in FIG. 19, receives a data signal, Dataj, from q-node 421 and weights that signal by an amount determined by the current control CC parameter, as explained above. When turned on by the data signal, Dataj, a current iSIG to flow through Weighted Driver 701. In other words, the magnitude of iSIG is a function of Data and CC. Data History Generator 705 provides input signals to the Equalization Drivers 702 that represent prior data signals, Dataj−1 through Dataj-k. Data History Generator 705 may be realized as a shift register. Like Weighted Driver 701, Equalization Drivers 702 weight their respective prior data signals by an amount determined by an associated ECR, which stores a topography dependent equalization coefficient, ceq. Thus the Equalization Drivers 702 respectively sink equalization currents iEQ1 through iEQK, each of which is a function of the prior data signal input to the individual Equalization Driver 702 and the associated topography dependent equalization coefficient. The total current, iOL, output by Output Current Driver 700A may be expressed as follows:
i OL =i SIG +i EQ1 +i EQ2 . . . +i EQK
Data History Generator 705 receives the signal Dataj and a transmit clock signal, tCLK, and generates K delayed data signals, Dataj−1 through Dataj-k. In one embodiment, a new data value is transmitted at each rising edge and each falling edge of the tCLK signal, while in an alternative embodiment data is transmitted on only one clock edge per cycle of the transmit clock.
FIG. 26B illustrates in greater detail one of the Equalization Drivers 702-y of FIG. 26A. Equalization Driver 702-y includes a multiplexer (MUX) 709, a set of additive logic gates, ADD Gates 712A-712R, a set of associated binary weighted Transistors 710A-710R, a set of subtractive logic gates, SUB Gates 711A-711R, and a set of associated binary weighted Transistors 713A-713R. In the illustrated embodiment, each ECR 401A-401K+1 represents it equalization coefficient via a sign bit (S bit) and multiple magnitude bits. In the illustrated embodiment, the equalization coefficient is represented by three magnitude bits; however, other embodiments including fewer or more magnitude bits are consistent with the present invention. Referring specifically to the illustrated embodiment of Equalization Driver 702-y in FIG. 26B, the S bit selects from MUX 709 either the inverted or non-inverted version of the Dataj-y signal, while each bit of the coefficient magnitude is input to an “ADD” AND Gate 712 and to a “SUB” AND Gate 711. The paired ADD Gate 712 and SUB Gate 711 associated with a particular magnitude bit each are associated with a similarly weighted binary weighted Transistor. In particular, bit 1 of the coefficient magnitude is input to ADD Gate 712A and SUB Gate 711A, which, depending on the state of the Dataj-y signal, activates Transistor 710A (1×) and Transistor 713A (−1×), respectively. Note that the binary weighting of Transistors 710A and 713A is equal in magnitude, but of opposite sign. Similarly, bit 2 of the coefficient magnitude in input to ADD Gate 712B and SUB Gate 711B, which may active Transistor 710B and Transistor 713B, respectively.
Consider the operation of Equalization Driver 702-y when the coefficient magnitude bits stored in ECRy 401-y represent zero. In this situation, every SUB Gate 711A-711R activates its associated binary weighted Transistor 713A-713R, while no ADD Gate 712A-712R activates its associated binary weighted Transistor 710A-710R. This is true regardless of the state of the Dataj-y signal or the state of the S bit from ECR2 401B. Thus, the current sunk by Equalization Driver 702-y iEQy, is approximately (2R−1)×IUNIT, where IUNIT is the current through 1× transistor 710A when it is activated.
i EQ1=2R ×I UNIT+(c EQ1×2R)×Polarity(Dataj−1)×I UNIT; where
Equalizer Drivers 702-1 to 702-k operate in a similar fashion in response to their associated data signals and equalizer coefficients, allowing their output current to be increased or decreased relative to 2R×IUNIT. Thus, the total current iOL output by Output Current Driver 700A is given by the following expression:
i OL = i SIG + i EQ ; ⁢ where i EQ = 2 R × K × I UNIT + ( c EQ ⁢ ⁢ 1 × 2 R ) × Polarity ⁡ ( Data j - 1 ) × I UNIT + ( c EQ ⁢ ⁢ 2 × 2 R ) × Polarity ⁡ ( Data j - 2 ) × I UNIT + ⋮ ( c EQK × 2 R ) × Polarity ⁡ ( Data j - K ) × I UNIT .
By setting the term (2R×K×IUNIT) equal to the desired high voltage level, VHI, on the channel, the equalization coefficients, cEQ1-cEQK, stored in ECRs 401A-401K can be used to effect a current swing above and below the nominal current used to produce VHI and above and below the nominal current used to produce the desired low voltage level, VLO. These current swings can be used in turn to overdrive or underdrive the channel, compensating the output voltage for past output levels. Note that the current IUNIT drawn by the 1× Transistor (T23, FIG. 19) associated with Weighted Driver 701 may be different from the current IUNIT drawn by the 1× Transistor 712A associated with Equalization Driver 702-y.
FIG. 27 illustrates a bus receiver 800 with equalization circuitry according to one embodiment. Incoming data, Dataj, is summed with an equalization offset 816 by analog adder 817, generating an equalized data value DEQ, for comparison with Vref by a comparator 830. The equalization offset 816 is generated by adding and subtracting equalization coefficients C1 EQ to CKEQ according to the state of previously received data values, Dataj−1 to Dataj-k, respectively.
A data history generator 705, preferably implemented as a shift register, receives the output of the comparator 830 and generates the data history values, Dataj−1 to Dataj-k. The data history values are used to select, via multiplexers 811-1 to 811-k, between positive and negative versions of respective equalization coefficients C1 EQ to CKEQ stored in equalization registers 804-1 to 804-k. As with the equalization coefficients discussed above with reference to FIG. 26B, equalization coefficients C1 EQ to CKEQ may be positive or negative values. As shown in FIG. 27, a negative version of the content of each equalization register 804 is generated by a respective two's complement generator 809. Any number of circuits for generating negative versions of equalization coefficients may be used in alternate embodiments. Also, one's complement circuitry may be used in alternate embodiments instead of two's complement circuitry.
In yet another alternate embodiment of a bus receiver, analog rather than digital circuitry is used to perform equalization. Sample and hold circuitry is used to capture past data signals, Dataj−1 to Dataj-k. The amplitude of the captured signals are weighted by equalization coefficients C1 EQ to CKEQ from registers 804-1 to 804-k, and then input to analog adder 817. Cross-talk equalization is also accomplished in this manner, except that neighboring signals are weighted by the equalization coefficients instead of prior data signals on the same signal path.
a first register to store a value representative of an equalization co-efficient setting; and
a transmitter circuit including an output driver to output data at least in part in accordance with the equalization co-efficient setting.
2. The chip of claim 1, wherein the chip is a memory controller device.
3. The chip of claim 1, wherein the chip is a memory device.
4. The chip of claim 1, wherein the value is determined based on information stored in a supplemental memory device.
5. The chip of claim 4, wherein the output driver is configured to output the data to a memory device disposed on a memory module, wherein the information stored in the supplemental memory device includes information corresponding to the memory device.
6. The chip of claim 1, wherein the value is based on information associated with a transmission path onto which the output driver outputs data.
7. The chip of claim 1, wherein the output driver is connectable to a signal line onto which data is output, wherein the equalization co-efficient setting compensates for a parasitic signal present on the signal line, wherein the parasitic signal includes at least one of a reflection of one or more previously transmitted signals and a cross-coupled signal.
8. The chip of claim 1, further comprising a data history generator circuit coupled to the transmitter circuit, to adjust the transmitter circuit based on previous data output by the output driver.
9. The chip of claim 1, further comprising a locked loop circuit to generate a clock signal, wherein:
the output driver outputs a first data value of the data at a rising edge transition of the clock signal; and
the output driver outputs a second data value of the data at a falling edge transition of the clock signal.
a locked loop circuit to generate a transmit signal, wherein the transmitter circuit is configured to output the data in response to the transmit signal;
a second register to store a value representative of a transmit timing offset applicable to the transmit signal; and
a third register to store a value representative of a slew rate adjustment applicable to the transmitter circuit.
11. The chip of claim 1, further comprising a second register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs the data using the drive strength setting.
12. The chip of claim 11, further comprising a data history generator circuit, coupled to the transmitter circuit, to provide an adjustment to the drive strength of data output based on the equalization co-efficient setting and data that was previously output by the output driver.
13. The chip of claim 12, wherein the data history generator includes a shift register to store the data that was previously output by the output driver.
14. The chip of claim 11, further comprising a counter, coupled to the output driver, the counter configured to maintain a count value that is used to adjust the voltage swing of the output driver in accordance with a signal that indicates a direction to adjust the count value.
15. A method of operation of a chip including an output driver and a first register, the method comprising:
storing a value representative of an equalization co-efficient setting in the first register; and
transmitting a data signal from the output driver, wherein a voltage swing of the data signal transmitted is varied in accordance with the equalization co-efficient setting.
generating a transmit signal using a locked loop circuit;
outputting a first data value of data at a rising edge transition of the transmit signal; and
outputting a second data value of the data at a falling edge transition of the transmit signal.
17. The method of claim 15, further comprising storing in a second register, a value representative of the voltage swing.
18. The method of claim 15, wherein the voltage swing of the data signal transmitted is varied in accordance with the equalization co-efficient setting and data previously transmitted by the output driver.
means for storing a value representative of an equalization co-efficient setting; and
means for transmitting data, wherein the transmission means is configured to adjust an output signal carrying the data at least in part in accordance with the equalization co-efficient setting.
20. A chip comprising:
a first register to store a value representative of an equalization setting; and
an output driver to output a data signal corresponding to a data bit, wherein a magnitude of the data signal is conditionally weighted by the equalization setting, wherein the magnitude of the data signal is further conditionally weighted depending upon a logic state of a historical bit of output data relative to a logic state of the data bit.
21. The chip of claim 20, wherein the value is based on information associated with a transmission path onto which the output driver outputs the data signal.
22. The chip of claim 20, wherein the output driver is connectable to a signal line onto which the data signal is output, wherein the equalization setting compensates for a parasitic signal present on the signal line, wherein the parasitic signal includes at least one of a reflection of one or more previously transmitted signals and a cross-coupled signal.
23. The chip of claim 20, further comprising a locked loop circuit to generate a clock signal, wherein:
the output driver outputs a first data signal at a rising edge transition of the clock signal; and
the output driver outputs a second data signal at a falling edge transition of the clock signal.
24. The chip of claim 20, further comprising:
a locked loop circuit to generate a transmit signal, wherein the output driver is configured to output the data signal in response to the transmit signal;
a third register to store a value representative of a slew rate adjustment applicable to the output driver.
25. The chip of claim 20, further comprising a second register to store a value representative of a drive strength setting associated with the output driver such that the output driver outputs the data signal based at least in part on the drive strength setting.
26. The chip of claim 25, further comprising a data history generator circuit, coupled to the output driver, to provide an adjustment to the drive strength setting based at least in part on the equalization setting and the data signal that was previously output by the output driver.
27. The chip of claim 26, wherein the data history generator includes a shift register to store the data bit corresponding to the data signal that was previously output by the output driver, wherein a voltage swing setting of the output driver is modified based at least in part on the data bit corresponding to the data signal that was previously output by the output driver.
28. A method of operation of a chip, the method comprising:
storing a first value representative of an equalization setting; and
outputting a data signal corresponding to a data bit having a magnitude that is conditionally weighted by the equalization setting, wherein the magnitude of the data signal is further conditionally weighted depending upon a logic state of a historical bit of output data relative to a logic state of the data bit.
wherein outputting the data signal includes outputting a first data signal at a rising edge transition of the clock signal, and outputting a second data signal at a falling edge transition of the clock signal.
generating a transmit signal, wherein outputting the data signal includes outputting the data signal in response to the transmit signal;
storing a second value representative of a transmit timing offset applicable to the transmit signal; and
storing a third value representative of a slew rate adjustment applicable to the data signal.
US13196840 1999-10-19 2011-08-02 Memory controller and method utilizing equalization co-efficient setting Active US8214570B2 (en)
US09910217 US6516365B2 (en) 1999-10-19 2001-07-19 Apparatus and method for topography dependent signaling
US10359061 US6684263B2 (en) 1999-10-19 2003-02-04 Apparatus and method for topography dependent signaling
US10742247 US7032057B2 (en) 1999-10-19 2003-12-19 Integrated circuit with transmit phase adjustment
US11073403 US7032058B2 (en) 1999-10-19 2005-03-04 Apparatus and method for topography dependent signaling
US11181411 US7174400B2 (en) 1999-10-19 2005-07-13 Integrated circuit device that stores a value representative of an equalization co-efficient setting
US11672018 US20070239914A1 (en) 1999-10-19 2007-02-06 Integrated Circuit Device that Stores a Value Representative of an Equalization Co-Efficient Setting
US11929974 US7565468B2 (en) 1999-10-19 2007-10-30 Integrated circuit memory device and signaling method for adjusting drive strength based on topography of integrated circuit devices
US12479679 US8001305B2 (en) 1999-10-19 2009-06-05 System and dynamic random access memory device having a receiver
US13196840 US8214570B2 (en) 1999-10-19 2011-08-02 Memory controller and method utilizing equalization co-efficient setting
US13535228 US8458385B2 (en) 1999-10-19 2012-06-27 Chip having register to store value that represents adjustment to reference voltage
US13853978 US8775705B2 (en) 1999-10-19 2013-03-29 Chip having register to store value that represents adjustment to reference voltage
US14321718 US9110828B2 (en) 1999-10-19 2014-07-01 Chip having register to store value that represents adjustment to reference voltage
US14682926 US9323711B2 (en) 1999-10-19 2015-04-09 Chip having port to receive value that represents adjustment to transmission parameter
US14683324 US9135967B2 (en) 1999-10-19 2015-04-10 Chip having register to store value that represents adjustment to output drive strength
US14683290 US9135186B2 (en) 1999-10-19 2015-04-10 Chip having port to receive value that represents adjustment to output driver parameter
US14686522 US9152581B2 (en) 1999-10-19 2015-04-14 Chip storing a value that represents adjustment to output drive strength
US14875433 US9411767B2 (en) 1999-10-19 2015-10-05 Flash controller to provide a value that represents a parameter to a flash memory
US15228614 US9852105B2 (en) 1999-10-19 2016-08-04 Flash controller to provide a value that represents a parameter to a flash memory
US12479679 Continuation US8001305B2 (en) 1999-10-19 2009-06-05 System and dynamic random access memory device having a receiver
US13535228 Continuation US8458385B2 (en) 1999-10-19 2012-06-27 Chip having register to store value that represents adjustment to reference voltage
US20110289245A1 true US20110289245A1 (en) 2011-11-24
US8214570B2 true US8214570B2 (en) 2012-07-03
US09420949 Active US6321282B1 (en) 1999-10-19 1999-10-19 Apparatus and method for topography dependent signaling
US09910217 Active US6516365B2 (en) 1999-10-19 2001-07-19 Apparatus and method for topography dependent signaling
US10359061 Active US6684263B2 (en) 1999-10-19 2003-02-04 Apparatus and method for topography dependent signaling
US10742247 Active 2019-11-09 US7032057B2 (en) 1999-10-19 2003-12-19 Integrated circuit with transmit phase adjustment
US10763849 Expired - Fee Related US7024502B2 (en) 1999-10-19 2004-01-22 Apparatus and method for topography dependent signaling
US10881433 Active 2019-11-05 US7051129B2 (en) 1999-10-19 2004-06-30 Memory device having programmable drive strength setting
US11073403 Active US7032058B2 (en) 1999-10-19 2005-03-04 Apparatus and method for topography dependent signaling
US11181411 Active US7174400B2 (en) 1999-10-19 2005-07-13 Integrated circuit device that stores a value representative of an equalization co-efficient setting
US11672018 Abandoned US20070239914A1 (en) 1999-10-19 2007-02-06 Integrated Circuit Device that Stores a Value Representative of an Equalization Co-Efficient Setting
US11929985 Active US7539802B2 (en) 1999-10-19 2007-10-30 Integrated circuit device and signaling method with phase control based on information in external memory device
US11929980 Active US7546390B2 (en) 1999-10-19 2007-10-30 Integrated circuit device and signaling method with topographic dependent equalization coefficient
US11929974 Active US7565468B2 (en) 1999-10-19 2007-10-30 Integrated circuit memory device and signaling method for adjusting drive strength based on topography of integrated circuit devices
US12479679 Active 2020-03-26 US8001305B2 (en) 1999-10-19 2009-06-05 System and dynamic random access memory device having a receiver
US13196840 Active US8214570B2 (en) 1999-10-19 2011-08-02 Memory controller and method utilizing equalization co-efficient setting
US13535228 Active US8458385B2 (en) 1999-10-19 2012-06-27 Chip having register to store value that represents adjustment to reference voltage
US13853978 Active US8775705B2 (en) 1999-10-19 2013-03-29 Chip having register to store value that represents adjustment to reference voltage
US14321718 Active US9110828B2 (en) 1999-10-19 2014-07-01 Chip having register to store value that represents adjustment to reference voltage
US14682926 Active US9323711B2 (en) 1999-10-19 2015-04-09 Chip having port to receive value that represents adjustment to transmission parameter
US14683290 Active US9135186B2 (en) 1999-10-19 2015-04-10 Chip having port to receive value that represents adjustment to output driver parameter
US14683324 Active US9135967B2 (en) 1999-10-19 2015-04-10 Chip having register to store value that represents adjustment to output drive strength
US14686522 Active US9152581B2 (en) 1999-10-19 2015-04-14 Chip storing a value that represents adjustment to output drive strength
US14875433 Active US9411767B2 (en) 1999-10-19 2015-10-05 Flash controller to provide a value that represents a parameter to a flash memory
US15228614 Active US9852105B2 (en) 1999-10-19 2016-08-04 Flash controller to provide a value that represents a parameter to a flash memory
US (23) US6321282B1 (en)
US20130227214A1 (en) * 1999-10-19 2013-08-29 Mark A. Horowitz Chip Having Register to Store Value that Represents Adjustment to Reference Voltage
US20160335204A1 (en) * 2015-05-14 2016-11-17 Micron Technology, Inc. Apparatuses and methods for asymmetric input/output interface for a memory
US3646329A (en) 1968-11-20 1972-02-29 Matsushita Electric Ind Co Ltd Adaptive logic circuit
US4549124A (en) 1982-02-26 1985-10-22 Kaltenbach & Voigt Gmbh & Co. Circuit arrangement for controlling the action of an adjusting device, in particular for a patient chair
US4627080A (en) 1984-11-23 1986-12-02 At&T Bell Laboratories Adaptive timing circuit
US4670666A (en) 1984-07-26 1987-06-02 Mitsubishi Denki Kabushiki Kaisha MOS transistor circuit for shared precharging of bus lines
US4680487A (en) 1985-08-19 1987-07-14 Ricoh Company, Ltd. Input/output port including auxiliary low-power transistors
US4691127A (en) 1984-12-05 1987-09-01 U.S. Philips Corporation Adaptive electronic buffer system having consistent operating characteristics
US4715003A (en) 1984-07-27 1987-12-22 Keller Ag Fur Druckmesstechnik Method for temperature compensation and measuring circuit therefor
US4728881A (en) 1986-02-19 1988-03-01 Haven Automation Limited Circuit for providing a controlled resistance
US4779013A (en) 1985-08-14 1988-10-18 Kabushiki Kaisha Toshiba Slew-rate limited output driver having reduced switching noise
US4894562A (en) 1988-10-03 1990-01-16 International Business Machines Corporation Current switch logic circuit with controlled output signal levels
US4967105A (en) 1988-05-30 1990-10-30 Sharp Kabushiki Kaisha Load current control-type logic circuit
US4977333A (en) 1988-04-13 1990-12-11 Hitachi, Ltd. Power semiconductor device including an arrangement for controlling load current by independent control of a plurality of semiconductor elements
US5024101A (en) 1989-02-10 1991-06-18 Nippondenso Co., Ltd. Power source circuit and bridge type measuring device with output compensating circuit utilizing the same
US5029272A (en) 1989-11-03 1991-07-02 Motorola, Inc. Input/output circuit with programmable input sensing time
US5045832A (en) 1988-12-28 1991-09-03 Astec International Limited Digitally controlled variable resistor
US5055715A (en) 1989-04-03 1991-10-08 Nec Corporation Semiconductor integrated circuit provided with monitor-elements for checking affection of process deviation on other elements
EP0463316A1 (en) 1990-06-07 1992-01-02 International Business Machines Corporation Self-adjusting impedance matching driver
US5081379A (en) 1985-12-10 1992-01-14 U.S. Philips Corporation Current-sensing circuit for an ic power semiconductor device
EP0482392A2 (en) 1990-10-26 1992-04-29 Alcatel SEL Aktiengesellschaft Circuit arrangement for providing an output current for a data driver
US5228064A (en) 1989-12-22 1993-07-13 Universal Data Systems, Inc. Data timing recovery apparatus and method
US5565796A (en) 1995-05-24 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Bus drive circuit, receiver circuit, and bus system
US5568068A (en) 1995-06-08 1996-10-22 Mitsubishi Denki Kabushiki Kaisha Buffer circuit for regulating driving current
US5578960A (en) 1992-09-30 1996-11-26 Sharp Kabushiki Kaisha Direct-current stabilizer
US5628027A (en) 1993-10-29 1997-05-06 Compaq Computer Corporation Method of determining the configuration of devices installed on a computer bus
US5668468A (en) 1996-01-11 1997-09-16 Harris Corporation Common mode stabilizing circuit and method
US5862094A (en) 1996-12-17 1999-01-19 Fujitsu Limited Semiconductor device and a semiconductor memory device
WO1999003106A1 (en) 1997-07-09 1999-01-21 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
US5872347A (en) 1997-06-24 1999-02-16 Industrial Technology Research Institute Method and device for controlling discharging current slope of wire cut electrical discharge machine
EP0897154A2 (en) 1997-08-13 1999-02-17 Compaq Computer Corporation Memory controller supporting dram circuits with different operating speeds
US5887150A (en) 1997-06-25 1999-03-23 Adaptec, Inc. SCSI controller having output driver with slew rate control
US5926651A (en) 1995-07-28 1999-07-20 Intel Corporation Output buffer with current paths having different current carrying characteristics for providing programmable slew rate and signal strength
US5945819A (en) 1996-05-31 1999-08-31 Sgs-Thomson Microelectronics S.R.L. Voltage regulator with fast response
US5963502A (en) 1998-01-14 1999-10-05 Mitsubishi Denki Kabushiki Kaisha Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing
US6026051A (en) 1997-02-11 2000-02-15 Micron Technology, Inc. Low skew differential receiver with disable feature
US6028451A (en) 1997-12-31 2000-02-22 Intel Corporation Method and apparatus for topology dependent slew rate control
US6031787A (en) 1997-11-17 2000-02-29 Micron Electronics Apparatus for providing additional latency for synchronously accessed memory
WO2000028596A1 (en) 1998-11-10 2000-05-18 Infineon Technologies Ag Memory cell arrangement
US6072747A (en) 1997-11-07 2000-06-06 Samsung Electronics Co., Ltd. High-speed current setting systems and methods for integrated circuit output drivers
US6087893A (en) 1996-10-24 2000-07-11 Toshiba Corporation Semiconductor integrated circuit having suppressed leakage currents
US6094075A (en) 1997-08-29 2000-07-25 Rambus Incorporated Current control technique
WO2001028596A2 (en) 1999-10-21 2001-04-26 Ivo Edward Ruzek Superabsorbent plexifibrils, fibrous sheets made out of them and process for their manufacturing
US6661268B2 (en) 1998-12-28 2003-12-09 Rambus Inc. Charge compensation control circuit and method for use with output driver
US6782438B1 (en) 2000-08-31 2004-08-24 Hewlett-Packard Development Company, L.P. IO speed and length programmable with bus population
US6975160B2 (en) 1997-08-29 2005-12-13 Rambus Inc. System including an integrated circuit memory device having an adjustable output voltage setting
US6995627B2 (en) 2002-12-20 2006-02-07 Intel Corporation Transmitter equalization method and apparatus
US7580474B2 (en) 1997-06-20 2009-08-25 Massachusetts Institute Of Technology Digital transmitter
US7715494B2 (en) 1997-06-20 2010-05-11 Massachusetts Institute Of Technology Digital transmitter
US7602857B2 (en) 1997-06-20 2009-10-13 Massachusetts Institute Of Technology Digital transmitter
US7602858B2 (en) 1997-06-20 2009-10-13 Massachusetts Institute Of Technology Digital transmitter
US7032058B2 (en) 1999-10-19 2006-04-18 Rambus Inc. Apparatus and method for topography dependent signaling
US8001305B2 (en) * 1999-10-19 2011-08-16 Rambus Inc. System and dynamic random access memory device having a receiver
US7546390B2 (en) * 1999-10-19 2009-06-09 Rambus, Inc. Integrated circuit device and signaling method with topographic dependent equalization coefficient
"400 Mb/s/pin SLDRAM" Draft/Advance, "4M x 18 SLDRAM, Pipelined, Eight Bank, 2.5V Operation." Rev. Jul. 9, 1998, pp. 1-69, Copyright 1998, SLDRAM Inc.
"Intel 430 TX PCISET:82439TX System Controller (MTXC)". Preliminary. Order No. 290559-001. Copyright Feb. 1997, Intel Corporation. 84 pages.
Allan, G., "DDR SDRAM/SGRAM: An Interpretation of the JEDEC Standard," MOSAID Technologies Inc., Sep. 25, 1998, 48 pages.
Armstrong, D. H., "Pitfalls in Testing Digital Devices," IEEE 1987 Custom Integrated Circuits Conference, pp. 573-578.
Biber, A. I. "The Design of an Application Specific Interface Driver for a High Capactive Load," Masters Thesis at the Massachusetts Inst. Of Technology, Dec. 1989, 67 pages.
Cox, D. T., et al., "VLSI Performance Compensation for Off-Chip Drivers and Clock Generation," IEEE 1989 Custom Integrated Circuits Conference, pp. 14.3.1-14.3.4.
Dally, W. J. et al., "Digital Systems Engineering", pp. 361-366 (1998).
Douseki, T., et al., "BiCMOS Circuit Technology for a High-Speed SRAM," IEEE Journal of Solid State Circuits, vol. 23, No. 1, Feb 1988, pp. 68-73.
EP Response dated Jul. 5, 2011 to the European Search Opinion dated Feb. 8, 2011 and to the Official Communication dated Mar. 14, 2011 re EP Application No. 10179814.8. 6 Pages.
European Patent Office Action for EP 00975263.5 dated Mar. 19, 2010, 1 pgs.
European Patent Office Brief Communication with Preliminary Opinion Examining Division dated Sep. 21, 2010 for European Application No. 07121085.0-2212, 2 pgs.
European Patent Office Communication dated Dec. 1, 2010 EP Application No. 05025388.9 in the Decision to refuse an EP Application, 9 pgs.
European Patent Office Communication dated May 17, 2010 for EP 00975263.5 regarding statement of grounds of Appeal filed by Micron on May 10, 2010, Appeal No. 70555/10-3501, 15 pgs.
European Patent Office Communication for EP 07121085.0-2212 mailed Sep. 24, 2010, 1 pg.
European Patent Office Communication for EP 10180625.5 extended European Search Report dated Dec. 14, 2010, 5 pgs.
European Patent Office Extended Search Report for EP 10179814.8 dated Feb. 8, 2011, 5 pgs.
European Patent Office Response to Official Action for EP 10180625.5 dated Jun. 15, 2011, 17 pgs.
European Patent Office Summons to Attend Oral Proceedings for EP 05025388.9-2212 dated Mar. 9, 2010, 4 pgs.
European Patent Office Summons to Attend Oral Proceedings for EP 07121085.0 dated Mar. 8, 2010, 4 pgs.
European Provision of the Minutes of the Oral Proceedings before the Opposition Division with mail date of Dec. 30, 2009, EP Application 00975263.5 with opponent Micron Europe Ltd. includes The Interlocutory Decision in Opposition Proceedings and Documents for the Maintenance of the Patents as Ameneded, listed under Annex to the Minutes, 59 pgs.
Gabara, T. J., et al., "Digitally Adjustable Resistors in CMOS for High-Performance Applications", IEEE Journal of Solid State Circuits, IEEE Inc. New York, US, vol. 27, No. 8, Aug. 1, 1992, pp. 1176-1185, XP000309397 ISSN: 0018-9200.
Gillingham, P. et al, "SLDRAM: High Performance Open-Standard Memory," IEEE Micro, Nov./Dec. 1997, pp. 29-39, vol. 17, No. 6, Institute of Electrical and Electronics Engineers, Inc., Los Alamitos, California.
Gillingham, P., "SLDRAM Architectural and Functional Overview," SLDRAM Consortium, SLDRAM Inc., pp. 1-14 (Aug. 29, 1997).
Horowitz, Mark, U.S. Appl. No. 12/479,679, filed Jun. 5, 2009, Notice of Allowance and Fee(s) Due with mail date of Apr. 11, 2011. 10 Pages.
Horowitz, Mark, U.S. Appl. No. 12/479,679, filed Jun. 5, 2009, Notice of Allowance and Fee(s) Due with mail date of Jan. 20, 2011. 13 Pages.
IBM Application Note, "DDR SDRAM Module Serial Presence Detect Definitions," Oct. 1999, 34 pages.
IBM Corporation, "Driver with Noise-Dependent Switching Speed Control," IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1986, pp. 1243-1244.
IBM Corporation, 2000, 184 Pin DIMM Updates/Ramifications for Unbuffered and Registered DDR DEVIMs, 13 pages.
IBM, ApplicationNote, "DDR SDRAM Module Serial Presence Detect Definitions," Oct. 1999, 1-34 pgs.
IBM, Micron Technology and Reliance Computer Corporation, (Prepared by) DDR SDRAM Registered DIMM Design Specification Revision 0.6 Nov. 1999, 58 pages.
Intel, (1998), "Intel.RTM. 440BX AGPset: 82443BX Host Bridge/Controller:Datasheet," TOC: pp. 1-1 to 5-9.; pp. 2-4, 3-25 to 3-27, 4-19 to 4-20.
Johnson, C. D. et al., "Highly Accurate Resistance Deviation to Frequency Converter with Programmable Sensitivity and Resolution," IEEE vol. IM-35, No. 2, Jun 1986, 4 pages.
Knight, T. F. Jr., "A Self-Terminating Low-Voltage Swimming CMOS Output Driver." IEEE Journal of Solid-State Circuits, vol. 23, No. 2, Apr. 1988. pgs. 457-464.
Leung, K., "Controlled Slew Rate output Buffer," IEEE 1988 Custom Integrated Circuits Conference, 1988, pp. 5.5.1-5.5.4.
Mathews, J. W. et al., "Power Supply Voltages for Future VLSI," IEEE 1986 Custom Integrated Circuits Conference, pp. 149-152.
Minutes of Meeting No. 33 JC-16 Committee on Voltage Level and Interface, Mar. 2, 1999, Las Vegas, Nevada, 11 pages.
Nakase, Y., et al., "Source-Synchronization and Timing Vernier Techniques for 1.2-GB/s SLDRAM Interface," IEEE Journal of Solid-State Circuits, vol. 34, No. 4, pp. 494-501. Apr. 1999.
Notice of Opposition to European Patent No. 1151387, Filed by Micron Europe Ltd., on Jun. 19, 2008.
Oshima, Y., et al., "High-Speed Memory Architecture for multimedia Applications," IEEE, Circuits & Devices, Jan. 1997, pp. 8-13.
Paris L., et al., "WP 24.3: A 800 MB/s 72 Mb SLDRAM with Digitally-Calibrated DLL", ISSCC, 0-7803-5129-0/99, 10 pages. Slide Supplement, IEEE, 1999.
Poulton, J., "Signaling in High Performance Memory Systems", IEEE Solid State Circuits Conference, slides 1-59 on 30 pages (Feb. 1999).
Preliminary publication of JEDEC Semiconductor Memory Standards, JEDEC 64 MEG: x4, x8, x16 DDR SDRAM, JEDEC, Aug. 1999, 73 pages.
Rambus Inc., "RDRAM Annotated Specification 4.1.2," 1997.
Rambus Inc.,"16/18Mbit (2Mx8/9) & 64/72 Mbit (8Mx8/9) Concurrent RDRAM-Advance Information," Data Sheet, Jul. 1996, 61 pages.
Rambus Inc.,"16/18Mbit (2Mx8/9) & 64/72 Mbit (8Mx8/9) Concurrent RDRAM—Advance Information," Data Sheet, Jul. 1996, 61 pages.
Rambus, Inc., "8/9-Mbit (1Mx8/9) & 16/18Mbit (2Mx8/9) RDRAM-Preliminary Information," Rambus Inc. Data Sheet, Mar. 1, 1996, 30 pages.
Rambus, Inc., "8/9-Mbit (1Mx8/9) & 16/18Mbit (2Mx8/9) RDRAM—Preliminary Information," Rambus Inc. Data Sheet, Mar. 1, 1996, 30 pages.
Raver, N., "Open-Loop Gain Limitations for Push-Pull Off-chip Drivers,"IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 145-150.
Response to the Official Communication of Mar. 8, 2010 (summons to attend oral proceedings), dated Aug. 27, 2010, includes Summons to Attend Oral Proceedings, New claims 1-18 (with highlighted amendments), and New claims 1-18 (clear copy), in EP Application 07121085.0-2212, 12 pgs.
Response to the Official Communication of Sep. 21, 2010, dated Sep. 22, 2010 in EP Application No. 07121085.0-2212 (includes Amendments), 12 pgs.
Response to the Summons to Attend Oral Proceedings, Official Communication of Mar. 9, 2010, dated Aug. 27, 2010, includes Summons to Attend Oral Proceedings, New Claims 1-10, in EP Application No. 0502538 8.9-2212, 19 pgs.
Reynolds, C.B., "Analysis and Guidelines for High-Speed VLSI System Interconnections," IEEE 1988 Custom Integrated Circuits Conference, pp. 23.5.1-23.5.4.
Rhoden, "Platform 99 Standard DRAM Futures and DDR Infrastructures," Advanced Memory International, Inc., Jul. 21 & 22, 1999, 49 pgs.
Rhoden, Desi, Advanced Memory International, Inc., "Platform99, Standard DRAM Futures and DDR Infrastructures," Jul. 21 & 22, 1999. 48 pages.
Sasaki, et al., "Automated Measurement System for 1-Omega Standard Resistors Using a Modified Wheatstone Bridge," IEEE Transactions on Instrumentation and Measurement, vol. 4, No. 2, Apr. 1991, p. 274=277.
Sasaki, et al., "Automated Measurement System for 1-Ω Standard Resistors Using a Modified Wheatstone Bridge," IEEE Transactions on Instrumentation and Measurement, vol. 4, No. 2, Apr. 1991, p. 274=277.
Sasaki, H. et al, "High-Precision Automated Resistance Measurement Using a Modified Wheatstone Bridge," CPEM '88 Digest, Japan, 1988, 1 page.
Sasaki, H. et al., "Measurement of the Pressure Dependence of Standard Resistors Using a Modified Wheatstone Bridge," Trans. IEE of Japan, vol. 109, No. 1/2, Jan./Feb. 1989, 6 pages.
Sasaki, H., et al., "A Modified Wheatstone Bridge for High-Precision Automated Resistance Measurement," IEEE Trans. On Instr. And Measurement, vol. 26, No. 2, Dec. 1987, pp. 947-949.
Senbon, T. et al., Instrumentation Systems: Fundamentals and Applications, Chapter 3: Detection and Covnersion of Industrial Variables: 1991, 11 pages.
Song, B., et al., "NRZ Timing Recovery Technique for Band-Limited Channels," IEEE Journal of Solid-State Circuits, vol. 32, No. 4, pp. 514-520 (Apr. 1997).
Submission to European Patent Office dated Aug. 26, 2010 in Patent Application No. 00975263.2-2212 (includes the Main Request as well as Auxiliary Requests I-IV, Annexes 1-3, and Excerpts from Betty Prince's "High Performance Memories," John Wiley & Sons, 1996, pg. 11), 82 pgs.
Ware, F. A., Rambus, Inc., "Direct RDRAM 256/288-Mbit (512Kx16/18x32s) Data Sheet", Preliminary Information, Document DL0060 Version 0.90, 1999, pp. 1-66.
US8775705B2 (en) * 1999-10-19 2014-07-08 Rambus Inc. Chip having register to store value that represents adjustment to reference voltage
EP1630681A3 (en) 2006-08-16 application
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOROWITZ, MARK A.;BARTH, RICHARD M.;HAMPEL, CRAIG E.;ANDOTHERS;SIGNING DATES FROM 19991119 TO 19991203;REEL/FRAME:035424/0548