Source: https://patents.google.com/patent/US6839603B2/en
Timestamp: 2019-12-15 10:47:20
Document Index: 438421950

Matched Legal Cases: ['arts 11', 'arts 11', 'art 7', 'arts 11', 'art 3', 'art 3', 'art 3', 'art 3', 'art 7', 'art 3', 'art 7', 'art 3', 'art 7', 'art 3', 'art 7']

US6839603B2 - Semiconductor manufacturing system and control method thereof - Google Patents
Semiconductor manufacturing system and control method thereof Download PDF
US6839603B2
US6839603B2 US10/275,647 US27564702A US6839603B2 US 6839603 B2 US6839603 B2 US 6839603B2 US 27564702 A US27564702 A US 27564702A US 6839603 B2 US6839603 B2 US 6839603B2
US10/275,647
US20030153995A1 (en
2000-05-09 Priority to JP2000-135985 priority Critical
2000-05-09 Priority to JP2000135985 priority
2001-05-08 Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
2001-05-08 Priority to PCT/JP2001/003846 priority patent/WO2001086704A1/en
2002-11-08 Assigned to TOKYO ELECTRON LIMITED reassignment TOKYO ELECTRON LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KARASAWA, WATARU
2003-08-14 Publication of US20030153995A1 publication Critical patent/US20030153995A1/en
2005-01-04 Publication of US6839603B2 publication Critical patent/US6839603B2/en
239000004065 semiconductor Substances 0 abstract claims description title 274
G05B2219/32349—Simulate effect of stoppages of production facilities, operate as function of simulation
TABLE 1 Kind Priority A 3 B 3 C 3 D 2 E 3
TABLE 2 kind Priority A 3 B 3 C 3 D 2 E 3 Z 1 (2, 3)
TABLE 3 Proc. Status Re- Time Time to Failure part of maining after next pro- No. process time repair check bability First In process 30 sec 100 hrs 30 hrs 20% Second In process 60 sec 250 hrs 20 hrs 50% Third Failure 2 hrs 501 hrs 20 hrs 100% Fourth Periodic 2 hrs 100 hrs 0 hr 20% check Fifth In process 50 sec 400 hrs 10 hrs 80% Sixth In process 30 sec 250 hrs 5 hrs 50%
Additionally, the “failure probability” is calculated by the formula of (“time after repair”/MTBF)×100(%). Here, “MTBF” means the mean time between failure of the processing parts 11-17. For example, supposing this value is 500 hours, as shown in table 3, failure probability with respect to each of the first through sixth processing parts 11-16 is set to 20%, 50%, 100% (when computed or more with 100, referred to as 100), 20%, 80% and 50%, respectively. Therefore, the higher the failure probability is, the more the failure occurs easily.
Next, the first control part judges, in step S4, whether the time to the next scheduled inspection with respect to the selected processing part is longer than mean processing time. The “mean processing time” is a value which is obtained by dividing an accumulated processing time of the processing part by a number of wafers processed within the accumulated process time. That is, the “mean processing time” means the mean time of the processing time needed for processing a single wafer. Additionally, the “mean processing time” is calculated by the second control part 7 for each processing parts 11-17 whenever the wafer 25 is processed by the processing parts, and is retained in relation to the information of the table 3. If the control part 3 judges that the time to the next scheduled inspection of the selected processing part is longer than the mean processing time, the routine proceeds to step S5 a. On the other hand, when the time to the next scheduled inspection is judged to be shorter than the mean processing time, the routine proceeds to step S5 b.
Next, the first control part 3 judges, in step S5 a, whether the failure probability of the selected processing part is within an allowable range based on the information shown in the above-mentioned table 3. If the value of, for example, 90% is set up beforehand as a degree of permission, of the failure probability and if the failure probability calculated with respect to each of the processing parts exceeds 90%, the routine proceeds to step S5 b. In step S5 a, the selected processing part is removed from a selection candidate, and the routine returns to Step S3. On the other hand when the failure probability does not exceed 90%, the routine proceeds to step S6. It should be noted that a warning may be issued, in step S6, based on a warning threshold value which is set together with the above-mentioned allowable range. That is, when a value of, for example, 70% is set to the warning threshold value, a warning may be issued so as to notify a user of a high probability of failure in a processing part having a failure probability of more than 70%. This may be effective with respect to a prediction of failure. Additionally, the processing parts having the failure, probability exceeding the warning threshold value may be excluded from the candidates of selection.
TABLE 4 Failure No. Cause of failure Repair time 1 Conveyance system 10 minutes failure (parameter abnormality) 2 Lamp failure 30 minutes 3 Conveyance system 2 hours failure 4 Vacuum failure 5 hours . . . . . . . . .
More specifically, supposing the mean failure interval time of the selected processing part is 200 hours and the reliance minimum coefficient corresponding to a reliance level of 90% is 0.6, 120 hours obtained by calculating 200×0.6 correspond to a reliance minimum of 90% with respect to the mean failure interval time (200 hours). If it is judged by the first control part 3 that the thus-obtained reliance minimum is below a minimum value, the processing part may be excluded from the candidates of selection.
Then, with respect to the processing part of which “time to the next scheduled inspection” is judged to reach the allowable value, the routine proceeds to step S62 b. On the other hand, the routine proceeds to step S62 a with respect to the processing part of which “time to the next scheduled inspection” is judged not to reach the allowable value. In step S62 b, a flag contained in the first control part 3 or the second control part 7 is raised so as to exclude the processing part from the candidates for selection, and the routine returns to step S61 a.
On the other hand, in step S62 a, the first control part 3 accesses the second control part 7 and refers to the “failure probability” for the processing part, and judges whether or not the “failure probability” will reach a predetermined allowable value when the new wafer is supplied. It should be noted that the judgment whether or not the “failure probability” will reach the allowable value may be made at a time when the process applied to the newly supplied wafer is ended.
Then, with respect to the processing part of which “failure probability” is judged to reach the allowable value, the routine proceeds to step S63 b. On the other hand, the routine proceeds to step S63 a with respect to the processing part of which “failure probability” is judged not to reach the allowable value. In step S63 b, a flag contained in the first control part 3 or the second control part 7 is raised so as to exclude the processing part from the candidates for selection, and the routine returns to step S61 a.
In step S63 a, the first control part 3 selects one of the processing parts having a shortest conveyance time, and sends an instruction to the driver 21 and the second control part 7 to convey the wafer to the selected one of the processing parts and process the wafer in the selected one of the processing parts.
a memory part that stores priority-level data which indicates a priority level of a process to be applied to each of said plurality of semiconductor substrates on an individual semiconductor substrate basis; and
a control part which controls said processing apparatus to process a newly supplied semiconductor substrate by determining an order of processing said plurality of semiconductor substrates being supplied to said processing apparatus based on a comparison of new priority-level data given to said newly supplied semiconductor substrate with said priority-level data stored in said memory part with respect to said plurality of semiconductor substrates so as to change a previously determined order of processing said plurality of semiconductor substrates in accordance with said new priority-level data.
2. The semiconductor manufacturing system as claimed in claim 1,
wherein said control part calculates a time of ending a process being applied to said newly supplied semiconductor substrate to which said new priority-level data is given or a process for all of said plurality of semiconductor substrates.
3. The semiconductor manufacturing system as claimed in claim 1,
wherein said control part calculates, based on a simulation of an operation of said processing apparatus, a time of supplying said newly supplied semiconductor substrate to which said new priority-level data is given to said processing apparatus in response to a time of ending a process designated by a user so as to end a process applied to said newly supplied semiconductor substrate to which said new priority-level data is given or all of said plurality of semiconductor substrates.
4. The semiconductor manufacturing system as claimed in claim 1,
wherein a plurality of processing apparatuses including said processing apparatus are provided and are controlled by said control part;
wherein a monitoring part monitors a condition of a process being performed by each of said plurality of processing apparatuses; and
wherein said control part selects one of said plurality of processing apparatuses which applies a process to said newly supplied semiconductor substrate to which said new priority-level data is given in response to said condition of this process being performed by each of said plurality of processing apparatuses.
5. The semiconductor manufacturing system as claimed in claim 4,
wherein said control part calculates a time of ending the process being applied to said newly supplied semiconductor substrate to which said new priority-level data is given or the process for all of the semiconductor substrates.
6. The semiconductor manufacturing system as claimed in claim 4,
wherein said control part calculates, based on a simulation of an operation of one of said plurality of processing apparatuses, a time of supplying said newly supplied semiconductor substrate to which said new priority-level data is given to said processing apparatus in response to a time of ending a process designated by a user so as to end the process applied to said newly supplied semiconductor substrate to which said new priority-level data is given or all of said plurality of semiconductor substrates.
7. The semiconductor manufacturing system as claimed in claim 4,
wherein said monitoring part monitors a remaining time for each of said plurality of processing apparatuses, said remaining time being a time until a process currently being applied is ended; and
wherein said control part selects one of said plurality of processing apparatuses which applies the process to said newly supplied semiconductor substrate to which said new priority-level data is given in accordance with said remaining time.
8. The semiconductor manufacturing system as claimed in claim 4,
wherein said monitoring part monitors a time remaining for performing a next periodic inspection for each of said plurality of processing apparatuses; and
wherein said control part selects one of said plurality of processing apparatuses which applies the process to said newly supplied semiconductor substrate to which said new priority-level data is given in accordance with said time remaining for performing said next periodic inspection.
9. The semiconductor manufacturing system as claimed in claim 1, wherein said newly supplied semiconductor substrate is one of said plurality of semiconductor substrates of which order of processing has been scheduled so that a previously scheduled order of processing is changed in accordance with said new priority-level data.
storing priority-level data in a memory part which indicates a priority level of the process to be applied to each of said plurality of semiconductor substrates on an individual semiconductor substrate basis;
determining an order of processing a newly supplied semiconductor substrate being supplied to said processing apparatus based on a comparison of new priority-level data given to said newly supplied semiconductor substrate with said priority-level data stored in said memory part with respect to said plurality of semiconductor substrates so as to change a previously determined order of processing said plurality of semiconductor substrates in accordance with said new priority-level data; and
causing said processing apparatus to apply the process to said newly supplied semiconductor substrate.
12. A control method of a semiconductor manufacturing system having a plurality of processing apparatuses which apply a plurality of processes to semiconductor substrates, comprising:
storing priority-level data in a memory part, which indicates a priority level of a process to be applied to each of said semiconductor substrates on an individual semiconductor substrate basis;
monitoring a condition of a process in each of said processing apparatuses;
determining an order of processing a newly supplied semiconductor substrate being supplied to one of said processing apparatuses based on a comparison of new priority-level data given to said newly supplied semiconductor substrate with said priority-level data stored in said memory part with respect to said semiconductor substrates so as to change a previously determined order of processing said semiconductor substrates in accordance with said new priority-level data;
selecting one of said processing apparatuses which applies the process to said newly supplied semiconductor substrate in accordance with said condition of the process and said order of processing; and
13. A computer-readable recording medium storing program code for causing a computer to control a process applied to a plurality of semiconductor substrates, comprising:
first program code means for storing priority-level data which indicates a priority level of a process to be applied to each of said plurality of semiconductor substrates on an individual semiconductor substrate basis;
second program code means for comparing new priority-level data with said stored priority-level data with respect to said plurality of semiconductor substrates of which process has been scheduled, said new priority-level data being supplied in response to a newly supplied semiconductor substrate being supplied to a processing apparatus;
third program code means for determining an order of processing said newly supplied semiconductor substrate being supplied to said processing apparatus while changing a previously determined order of processing said plurality of semiconductor substrates; and
fourth program code means for causing said processing apparatus to apply the process to said newly supplied semiconductor substrate.
14. The computer-readable recording medium as claimed in claim 13, further comprising:
fifth program code means for calculating a time of ending the process being applied to said newly supplied semiconductor substrate or a process for all of said plurality of semiconductor substrates.
15. The computer-readable recording medium as claimed in claim 13, further comprising:
fifth program code means for calculating, based on a simulation of an operation of said processing apparatus, a time of supplying said newly supplied semiconductor substrate to said processing apparatus in response to a time of ending a process designated by a user so as to end the process applied to said newly supplied semiconductor substrate or all of said plurality of semiconductor substrates.
16. A computer-readable recording medium storing program code for causing a computer to control a process applied to a plurality of semiconductor substrates by a plurality of processing apparatuses, comprising:
second program code means for monitoring a condition of a process in each of said plurality of processing apparatuses;
third program code means for comparing new priority-level data with said stored priority-level data with respect to said plurality of semiconductor substrates of which process has been scheduled, new priority-level data being supplied in response to a newly supplied semiconductor substrate to which a process is applied;
fourth program code means for determining an order of processing said newly supplied semiconductor substrate being supplied to one of said plurality of processing apparatuses;
filth program code means for selecting said one of said plurality of processing apparatuses which applies a process to said newly supplied semiconductor substrate in accordance with said condition of the process; and
sixth program code means for causing said selected one of said processing apparatuses to apply the process to said newly supplied semiconductor substrate;
wherein the program code changes a previously determined order of processing semiconductor substrates in accordance with said new priority level data.
17. The computer-readable recording medium as claimed in claim 16, further comprising:
seventh program code means for calculating a time of ending the process being applied to said newly supplied semiconductor substrate or a process for all of said plurality of semiconductor substrates.
18. The computer-readable recording medium as claimed in claim 16, further comprising:
seventh program code means for calculating, based on a simulation of an operation of one of said plurality of processing apparatuses, a time of supplying said newly supplied semiconductor substrate to said one of said plurality of processing apparatuses in response to a time of ending a process designated by a user so as to end the process applied to said newly supplied semiconductor substrate or all of said plurality of semiconductor substrates.
19. The computer-readable recording medium as claimed in claim 16, further comprising:
seventh program code means for monitoring a remaining time for each of said plurality of processing apparatuses, said remaining time being a time until the process currently being applied is ended; and
eighth program code means for selecting one of said plurality of processing apparatuses which applies the process to said newly supplied semiconductor substrate in accordance with said remaining time.
20. The computer-readable recording medium as claimed in claim 16, further comprising:
seventh program code means for causing monitoring a time remaining for performing a next periodic inspection for each of said plurality of processing apparatuses; and
eighth program code means for selecting said one of said plurality of processing apparatuses which applies the process to said newly supplied semiconductor substrate in accordance with said time remaining for performing said next periodic inspection.
21. A semiconductor manufacturing system having a processing apparatus for applying a process to semiconductor substrates;
wherein a memory part stores priority-level data which indicates a priority level of a process to be applied to each of said semiconductor substrates on an individual semiconductor substrate basis;
wherein a control part controls said processing apparatus to apply a process to a newly supplied one of said semiconductor substrates by determining an order of processing said newly supplied one of said semiconductor substrates being supplied to said processing apparatus based on a comparison of new priority-level data with said priority-level data stored in said memory part with respect to said semiconductor substrates of which process has been scheduled, said new priority-level data being supplied in response to said newly supplied one of said semiconductor substrates being supplied to said processing apparatus;
wherein said control part calculates a time of ending a process being applied to said newly supplied one of said semiconductor substrates or a time of ending a process for all of said semiconductor substrates; and
wherein said memory part stores information regarding kinds of failure possibly occurring in said processing apparatus and a repair time needed for repairing said processing apparatus in response to each kind of failure; and when a failure occurs in processing apparatuses, said control part calculates a time of ending a process in accordance with said repair time read from said memory part in response to a kind of failure designated by a user.
22. A semiconductor manufacturing system having a processing apparatus for applying a process to semiconductor substrates;
wherein a plurality of processing apparatuses are controlled by said control part;
wherein a monitoring part monitors a condition of a process being performed by each of said plurality of processing apparatuses;
wherein said control part selects one of said plurality of processing apparatuses which applies the process to said newly supplied one of said semiconductor substrates in response to a condition of the process being performed by each of said plurality of processing apparatuses;
wherein said control part calculates a time of ending the process being applied to said newly supplied one of said semiconductor substrates or a time of ending a process for all of said semiconductor substrates; and
wherein said memory part stores information regarding kinds of failure possibly occurring in said processing apparatus and a repair time needed for repairing said processing apparatus in response to each of said kinds of failure; and when a failure occurs in said processing apparatus, said control part calculates a time of ending a process in accordance with said repair time read from said memory part in response to a kind of failure designated by a user.
23. A semiconductor manufacturing system having at least one processing apparatus for applying a process to semiconductor substrates;
wherein a control part controls a processing apparatus to apply a process to a newly supplied one of said semiconductor substrates by determining an order of processing said newly supplied one of said semiconductor substrates being supplied to said processing apparatus based on a comparison of new priority-level data with said priority-level data stored in said memory part with respect to said semiconductor substrates of which process has been scheduled, said new priority-level data being supplied in response to said newly supplied one of said semiconductor substrates being supplied to said processing apparatus;
wherein said control part selects one of said plurality of processing apparatuses which applies the process to said newly supplied one of said semiconductor substrates in response to said condition of the process being performed by each of said plurality of processing apparatuses; and
wherein said monitoring part monitors a continuous operating time for each of said plurality of processing apparatuses; and
wherein said control part selects one of said plurality of processing apparatuses which applies the process to said newly supplied one of said semiconductor substrates by referring to a failure occurring rate calculated for each of said plurality of processing apparatuses in accordance with said continuous operating time.
24. A computer-readable recording medium storing program code for causing a computer to control a process applied to semiconductor substrates, comprising:
first program code means for storing priority-level data which indicates a priority level of a process to be applied to each of said semiconductor substrates on an individual semiconductor substrate basis;
second program code means for comparing new priority-level data with previous stored priority-level data with respect to said semiconductor substrates of which process has been scheduled, said new priority-level data being supplied in response to a newly supplied one of said semiconductor substrates being supplied to a processing apparatus;
third program code means for determining an order of processing said newly supplied one of said semiconductor substrates being supplied to said processing apparatus;
fourth program code means for causing said processing apparatus to apply a process to said newly supplied one of said semiconductor substrates;
fifth program code means for calculating a time of ending the process being applied to said newly supplied one of said semiconductor substrates or a time of ending a process for all of said semiconductor substrates; and
sixth program code means for storing information regarding kinds of failure possibly occurring in said processing apparatus and a repair time needed for repairing said processing apparatus in response to each of said kinds of failure; and seventh program code means, when a failure occurs in said processing apparatus, for calculating a time of ending a process in accordance with said repair time which is read in response to a kind of failure designated by a user.
25. A computer-readable recording medium storing program code for causing a computer to control a process applied to semiconductor substrates by a plurality of processing apparatuses, comprising:
third program code means for comparing new priority-level data with a previously stored priority-level data with respect to said semiconductor substrates of which process has been scheduled, said new priority-level data being supplied in response to a newly supplied one of said semiconductor substrates to which a process is applied;
fourth program code means for determining an order of processing said newly supplied one of said semiconductor substrates being supplied to said plurality of processing apparatuses;
fifth program code means for selecting one of said plurality of processing apparatuses which applies a process to said newly supplied one of said semiconductor substrates in accordance with said condition of the process;
sixth program code means for causing said selected one of said plurality of processing apparatuses to apply the process to said newly supplied one of said semiconductor substrates;
seventh program code means for calculating a time of ending the process being applied to said newly supplied one of said semiconductor substrates or a time of ending a process for all of said semiconductor substrates;
eighth program code means for storing information regarding kinds of failure possibly occurring in a processing apparatus and a repair time needed for repairing said processing apparatus in response to each of said kinds of failure; and
ninth program code means, when a failure occurs in said processing apparatus, for calculating a time of ending a process in accordance with said repair time which is read in response to a kind of failure designated by a user.
26. A computer-readable recording medium storing program code for causing a computer to control a process applied to semiconductor substrates by a plurality of processing apparatuses, comprising:
seventh program code means for monitoring a continuous operating time for each of said plurality of processing apparatuses; and
eighth program code means for selecting one of said plurality of processing apparatuses which applies the process to said newly supplied one of said semiconductor substrates by referring to a failure occurring rate calculated for each of said plurality of processing apparatuses in accordance with said continuous operating time.
US10/275,647 2000-05-09 2001-05-08 Semiconductor manufacturing system and control method thereof Expired - Fee Related US6839603B2 (en)
JP2000-135985 2000-05-09
JP2000135985 2000-05-09
PCT/JP2001/003846 WO2001086704A1 (en) 2000-05-09 2001-05-08 Semiconductor manufacturing system and control method thereof
US20030153995A1 US20030153995A1 (en) 2003-08-14
US6839603B2 true US6839603B2 (en) 2005-01-04
ID=18643995
US10/275,647 Expired - Fee Related US6839603B2 (en) 2000-05-09 2001-05-08 Semiconductor manufacturing system and control method thereof
US (1) US6839603B2 (en)
EP (1) EP1281195A4 (en)
JP (1) JP4906216B2 (en)
CN (1) CN1194381C (en)
AU (1) AU5269401A (en)
TW (1) TW487956B (en)
WO (1) WO2001086704A1 (en)
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2001-05-08 JP JP2001582826A patent/JP4906216B2/en not_active Expired - Fee Related
2001-05-08 AU AU52694/01A patent/AU5269401A/en not_active Abandoned
2001-05-08 CN CNB018088546A patent/CN1194381C/en not_active IP Right Cessation
2001-05-08 WO PCT/JP2001/003846 patent/WO2001086704A1/en active Application Filing
2001-05-08 TW TW090110889A patent/TW487956B/en not_active IP Right Cessation
2001-05-08 US US10/275,647 patent/US6839603B2/en not_active Expired - Fee Related
2001-05-08 EP EP01926154A patent/EP1281195A4/en not_active Withdrawn
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WO2001086704A1 (en) 2001-11-15
CN1428004A (en) 2003-07-02
EP1281195A4 (en) 2005-04-13
JP2003533044A (en) 2003-11-05
US20030153995A1 (en) 2003-08-14
JP4906216B2 (en) 2012-03-28
CN1194381C (en) 2005-03-23
AU5269401A (en) 2001-11-20
EP1281195A1 (en) 2003-02-05
TW487956B (en) 2002-05-21
KR100275639B1 (en) 2000-12-15 Production controller capable of controlling work start in each facility of a facility group taking buffer capacity of the facility group into consideration
JP4503634B2 (en) 2010-07-14 Preparing or distributing components in a maintenance, repair, or demolition inspection environment
JP4860907B2 (en) 2012-01-25 System and method for transferring small lot size substrate carriers between processing tools
JP2006060226A (en) 2006-03-02 Method of controlling manufacturing system
JP2000280145A (en) 2000-10-10 Production planning preparation method and device thereof
JP2005524165A (en) 2005-08-11 Agent-responsive scheduling in an automated manufacturing environment
US7610111B2 (en) 2009-10-27 Method and system for wafer lot order
JP2005528787A (en) 2005-09-22 Specialization of active software agents in automated manufacturing environments
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KARASAWA, WATARU;REEL/FRAME:013923/0584