Source: http://www.google.com/patents/US4413337?dq=7,328,163
Timestamp: 2014-03-11 16:18:10
Document Index: 558967733

Matched Legal Cases: ['arts 11', 'art 10', 'art 10', 'art 14', 'art 10', 'art 14', 'art 10', 'art 11']

Patent US4413337 - Time division switching system for circuit mode and packet mode lines - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe system switches first lines, each having a circuit mode channel and a packet mode channel, second circuit mode lines and third and fourth packet mode lines. The first lines are connected to subscriber equipments, each of which convoys both multiplexed channels which have a rate equal to that of the...http://www.google.com/patents/US4413337?utm_source=gb-gplus-sharePatent US4413337 - Time division switching system for circuit mode and packet mode linesAdvanced Patent SearchPublication numberUS4413337 APublication typeGrantApplication numberUS 06/231,936Publication dateNov 1, 1983Filing dateFeb 4, 1981Priority dateFeb 13, 1980Fee statusLapsedAlso published asCA1150429A1, DE3160102D1, EP0034514A1, EP0034514B1Publication number06231936, 231936, US 4413337 A, US 4413337A, US-A-4413337, US4413337 A, US4413337AInventorsJean-Louis Dauphin, Olivier F. Louvet, Jean-Marc PitieOriginal AssigneeDauphin Jean Louis, Louvet Olivier F, Pitie Jean MarcExport CitationBiBTeX, EndNote, RefManPatent Citations (1), Non-Patent Citations (3), Referenced by (29), Classifications (12), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetTime division switching system for circuit mode and packet mode linesUS 4413337 AAbstract The system switches first lines, each having a circuit mode channel and a packet mode channel, second circuit mode lines and third and fourth packet mode lines. The first lines are connected to subscriber equipments, each of which convoys both multiplexed channels which have a rate equal to that of the other lines. The second and third lines are connected to outside switching networks while the fourth lines are connected to a packet switching network. The number of the fourth lines is less than the sum of numbers of first and third lines. The fourth lines convey packets for all the connections established between two first lines or between a first line and a third line, or between a first line and the packet transmission medium served by the switching network. The system distinguishes the circuit mode channel and the packet mode channel in a first line. Switching is controlled either in response to the detection of the absence of flags in the incoming packet mode channel of a first line or in an incoming third line, or from switching network for a link from this network from a first or third line.
What we claim is: 1. A time division digital switching system for switching, on the one hand, between first PCM circuit mode digital channels and second PCM bidirectional circuit mode digital lines, each of the first channels being multiplexed with a second packet mode digital channel into a first bidirectional line having a first predetermined rate, as well as fourth bidirectional packet mode digital lines, said first and second channels and said second, third and fourth lines having a second rate half said first rate, each of the first, second, third and fourth channels including incoming and outgoing channels, the first bidirectional line including first incoming digital and first second, third and fourth outgoing digital lines, said system comprising:first means for demultiplexing the incoming first digital lines into the incoming first and second digital channels; first means for multiplexing the outgoing first and second channels into the outgoing first digital lines; second means for multiplexing said incoming first and second channels and the incoming second, third and fourth lines into an incoming digital multiplex having a third predetermined rate; means receiving said incoming multiplex for bidirectionally switching said first channel of each first line with the first channel of a first line or with a second line and for bidirectionally switching the second channel of each first line with a fourth line to derive an outgoing digital multiplex; and second means for demultiplexing the outgoing digital multiplex having said third rate which results from the switching operations in said means for switching, into said outgoing first and second channels and the outgoing second, third and fourth lines. 2. A time division digital switching system according to claim 1 wherein said first demultiplexing means comprises means for detecting flags interposed between two packets convoyed in said second channel of each incoming first line in said second multiplexing means and means for addressing said switching means so as to bidirectionally switch said second channel with a free fourth packet mode line in response to a flag absence signal delivered from said flag detecting means.
OBJECTS OF THE INVENTION The principal object of this invention is to provide a digital switching system wherein the circuit mode switching, i.e. of the digital voice channels, as well as the packet switching, i.e. of the packet mode channels, is performed via a subscriber-related conventional digital switching network, providing a few internal modifications thereto are made.
SUMMARY OF THE INVENTION According to this object, a time division digital system, while in a first state, switches first PCM circuit mode digital channels, each of which is multiplexed with a second packet mode digital channel, into (1) an incoming line having a first predetermined rate, and (2) second PCM bidirectional circuit mode digital lines. In a second state, the system switches said second channels and third and fourth bidirectional packet mode digital lines. The channels and second, third and fourth lines have a rate that is half of the first rate. The system comprises:
BRIEF DESCRIPTION OF THE DRAWING Other objects and features of the invention will be apparent from the following more particular description of preferred embodiments of the invention as illustrated in the accompanying drawings, in which:
DESCRIPTION OF THE PREFERRED EMBODIMENTS The nature of time-division switching system 1 embodying the invention is depicted in FIG. 1. The bidirectional digital connections to the system 1 are conventional and comprise for example lines including pairs of two types of symmetrical coaxial cables which operate in the duplex mode. The first type of cable includes first bidirectional digital lines 2.sub.1 to 2.sub.M having a first predetermined binary rate equal to 128 kbit/s. The second type concerns second, third and fourth bidirectional digital lines 3.sub.1 to 3.sub.N, 4.sub.1 to 4.sub.P and 5.sub.1 to 5.sub.Q having a second binary rate equal to 64 kbit/s, i.e. half the first binary rate. The first lines 2.sub.1 to 2.sub.M are subscriber's lines. They each convey a first digital channel in circuit mode TI.sub.c and a single digital channel in packet mode TI.sub.P, each having a binary rate of 64 kbit/s. At the subscriber end, each first line 2.sub.1 to 2.sub.M is connected, via interfaces 20.sub.1 to 20.sub.M each of which comprises a multiplexer-demultiplexer, on the one hand, to the subscriber's telephone set 21.sub.1 to 21.sub.M, each of which is fitted with a single-channel PCM encoder/decoder and which is associated with the 64 kbit/s circuit mode TI.sub.c channel and, on the other hand, to subscriber data terminal equipments (D.T.E.) 22.sub.1 to 22.sub.M, each of which is ascribed to the 64 kbit/s packet mode TI.sub.p channel. The first circuit mode channel is of the PCM type and is suited for conventionally transmitting sampled speech in TI.sub.c octets. The second packet mode channel transmits packets in time intervals or octets TI.sub.p. As known, each subscriber D.T.E. is linked to a plurality of terminals of the teletypewriter, telecopier, print-out, videophone or similar type, and transmits and receives messages ascribed to each terminal in split time. The messages transmitted by subscriber D.T.E. 22 are in the form of one or several informative packets which are routed via the switching system 1 to a packet switching network 6. After each packet heading has been analyzed, the switching network 6 reemits the latter packet to the second TI.sub.p channel of a first subscriber line 2, if the packet is intended for a subscriber D.T.E., or to a third line 4, if the packet is intended to be emitted over an outside network to distant subscribers, or lastly, to the packetized data transmission medium.
Consequently, propagating along each of a subscriber telephone lines 2.sub.1 to 2.sub.M is, on the one hand, a conventional telephone digital channel in the so-called circuit mode at 64 kbit/s and, on the other hand, a digital channel in the packet mode at 64 kbit/s. The prime function of the switching system 1 is to distinguish between these two types of channel. The first channel TI.sub.c is switched to one of conventional 64 kbit/s voice PCM digital second lines 3.sub.1 to 3.sub.N of the switched telephone network, thence to a distant subscriber's telephone set, or directly to the first circuit mode channel TI.sub.c of a local subscriber's line 2.sub.1 to 2.sub.M. The second channel TI.sub.p is switched via fourth 64 kbit/s digital lines 5.sub.1 to 5.sub.Q, operating in the packet mode, over to the packet switching network 6 which determines the various virtual circuits to be established for each of the messages propagating along the channel TI.sub.p. These virtual circuits can be established via the digital switching system 1 and the packet switching network 6 either between two local subscribers or between a local subscriber and an outside network matching device 7. The device 7 is illustrated in FIG. 1 by a single block which is linked at 64 kbit/s to the second lines 3.sub.1 to 3.sub.N and third lines 4.sub.1 to 4.sub.p on the switching system side.
(3) The physical level is related to the transmission features of the link between subscriber D.T.E. 22 and packet switching network 6, namely primarily those of the corresponding lines 2.sub.1 to 2.sub.M and 5.sub.1 to 5.sub.Q and of the digital switching system 1.
The present invention looks only at the latter two levels: the packet level is, indeed, only dealt with by the packet switching network 6. The system 1 does not take packet routing into consideration but concentrates solely on transmitting packets received from the channels TI.sub.p of the lines 2.sub.1 to 2.sub.M or received from the lines 4.sub.1 to 4.sub.p to the packet switching network 6, and conversely.
The frame level is monitered at each end of a link by the D.T.E. which is for instance one of a D.T.E.'s 22.sub.1 to 22.sub.M for one of lines 2.sub.1 to 2.sub.M, a D.T.E. (not shown) of the matching device 7 for one of lines 4.sub.1 to 4.sub.p or a D.T.E. of the packet switching network 6 for one of lines 5.sub.1 to 5.sub.Q.
The units making up system 1 that are specific to the invention are primarily the emitting and receiving parts of subscriber individual equipments (S.I.E.) 10.sub.1 to 10.sub.M and 11.sub.1 to 11.sub.M which are connected to subscriber lines 2.sub.1 to 2.sub.M, the emitting and receiving parts of circuit-switching individual equipment (C.I.E.) 12.sub.1 to 12.sub.N and 13.sub.1 to 13.sub.N which are connected to the outside network matching device 7, the emitting and receiving parts of the packet-switching individual equipments (P.I.E.) 14.sub.1 to 14.sub.p and 15.sub.1 to 15.sub.p, both of which are connected to 64 kbit/s third packet mode lines 4.sub.1 to 4.sub.p conveying the frames between the system 1 and the outside network matching device 7, the emitting and receiving parts of the packet-switching individual equipments (P.N.I.E.) 16.sub.1 to 16.sub.Q and 17.sub.1 to 17.sub.Q both of which are connected to 64 kbit/s fourth packet mode lines 5.sub.1 to 5.sub.Q conveying the frames between the system 1 and the packet switching network 6, a multiplexer 180 and a demultiplexer 181. Moreover, time-division switching system 1 comprises a known switching network 19 for the switching of 64 kbit/s simple lines or channels. The switching network 19 comprises a multiplexer 191 which multiplexes digital channels 1800.sub.1 to 1800.sub.R outgoing from the multiplexer 180, a demultiplexer 192 performing the inverse operation and transmitting digital channels 1810.sub.1 to 1810.sub.R to the multiplexer 181, a buffer memory (BM) 193 and a control memory (CM) 194. The control memory 194 receives the connection establishing or freeing orders delivered by a marking unit 183 via a bidirectional link 182.
Incoming lines 2, 3, 4 and 5 at 128 kbit/s and 64 kbit/s rate are multiplexed in the multiplexer 180 into a certain number of higher bit-rate digital channels 1800.sub.1 to 1800.sub.R. The digital channels 1810.sub.1 to 1810.sub.R which are derived from the switching network 19 and have the same bit-rate as that of digital channels 1800.sub.1 to 1800.sub.R, are demultiplexed in the demultiplexer 181 into the outgoing lines 2, 3, 4 and 5.
The system is, for instance, coupled up to (M=110) 128 kbit/s subscriber lines 2.sub.1 to 2.sub.110, (N=22) 64 kbit/s lines 3.sub.1 to 3.sub.22, (P=6) 64 kbit/s lines 4.sub.1 to 4.sub.6 and (Q=8) 64 kbit/s lines 5.sub.1 to 5.sub.8. The multiplexer 180 thus multiplexes 2M+N+P=256 digital channels of 64 kbit/s transmitted by the receiving parts of individual equipment items 10, 12, 14 and 16. Multiplexer comprises R=8 multiplexing modules, each of which multiplexes 32 64 kbit/s channels into one digital channel 1800 of 2048 kbit/s. Multiplexing takes place in each module of the multiplexer 180 in groups of 8 consecutive bits delivered by each incoming 64 kbit/s channel. The octet thus formed is series transmitted in a time interval of 3.9 μs along the 2048 kbit/s digital channel. R=8 digital channels 1800.sub.1 to 1800.sub. 8 derived from the multiplexer 180 are therefore connected to the switching network 19.
A conventional, but less optimized, embodiment is illustrated in FIG. 1. A series-to-parallel converter and a multiplexer 191 supplies octets delivered in series along digital channels 1800.sub.1 to 1800.sub.R in parallel to 8 wires and multiplexes these parallel octets into a supermultiplex 195 having 8 wires, on each of which is derived a digital binary rate equal to 2048 kbit/s. The buffer memory 193 comprises, according to the chosen example, 32 control memory 194 also comprises 256 8-bit words. In FIG. 1, demultiplexer 192 is a parallel-series converter for conducting octets derived from the supermultiplex 196, which has 8 wires leaving buffer memory 193, into a series data stream; demultiplexer 192 also includes a demultiplexer which demultiplexes the derived octets in R=8 digital channels 1810.sub.1 to 1810.sub.R.
Outgoing digital channels 1810.sub.1 to 1810.sub.R of digital switching network 19 are connected to demultiplexer 181. The latter comprises R=8 demultiplexing modules, each of which demultiplexes an outgoing digital channel 1810 to derive 32 64 kbit/s channels connected to the emitting parts 11, 13, 15 and 17 of the individual equipments.
The control memory 194 of the switching network 19 is reset by the marking unit 183 of the system 1. The unit 183 receives from each receiving part 10, 12, 14, 16 the transmitted data and the corresponding line address via a particular bus 184. Bus 182 supplies via the link 182 to the control memory 194, write-in control signals which enable data corresponding to an address of an incoming line 3, 4, 5 or an incoming channel (TI.sub.p or TI.sub.c) of an incoming line 2 to be written-in at an address of the control memory 194 identifying an outgoing line 3, 4, 5 or an outgoing channel (TI.sub.p or TI.sub.c) of an outgoing line 2.
According to a known feature of the prior art, the 8-wire supermultiplexers 195 and 196 have 256 time intervals which correspond to the 256 lines and are split, in the afore-mentioned example, into 220 channels along lines 2 (i.e. 110 mode circuit channels TI.sub.c and 110 mode packet channels TI.sub.p), N=22 lines 3.sub.1 to 3.sub.22, P=6 lines 4.sub.1 to 4.sub.6 and Q=8 lines 5.sub.1 to 5.sub.8.
In this way, according to the invention, the same switching network 19 makes it possible, depending on requirements, to establish (1) connections between channels TI.sub.c of the lines 2, (2) connections between a channel TI.sub.c of a line 2 and a line 3 as regards the voice-routing connections, (3) connections between a channel TI.sub.p of a line 2 and a line 5 and (4) connections between a line 4 and a line 5 as regards the data (or packet) frame-routing connections.
The marking unit 183 detects whether or not lines 5.sub.1 to 5.sub.Q are occupied, either by means of a special internal memory that it resets when connections are established or freed, or by reading the control memory 194 by means of the bidirectional link 182. Thus when the beginning of a frame (indicated by an absence of flags) is detected along the channel TI.sub.p of a line 2 by the receiving part 10 of an S.I.E. or along a line 4 by receiving part 14 of a P.I.E., marking unit 183 is advised thereof by the bus 184 over which the S.I.E. receiving part 10 or the P.I.E. receiving part 14 indicates the line in question. The marking unit 183 searches for a free line 5. If a line 5 is available, the unit 183 orders the marking in the control memory 194 thereby establishing a connection between line 2 or 4, over which a frame emission has started, and the selected available line 5 selected.
The marking unit 183 can also receive, via a link 81, connection requests delivered by a system control unit 8, when connections have to be established between two channels TI.sub.c of lines 2 or between a channel TI.sub.c of a line 2 and a line 3. Finally, the marking unit 183 can receive connection requests via the link 60 from the packet switching network 6 when connections have to be established between a line 5 and a line 4 or a channel TI.sub.p of a line 2. Each of these connections requests, controlled by the packet switching network 6, precedes the emission by the latter of a frame along a line 5.
A circuit diagram of subscriber individual equipment S.I.E. is illustrated in FIG. 2. Emitting part 10 of equipment S.I.E. comprises a binary synchronizing and shaping circuit 100 for the digits of the TI.sub.p and TI.sub.c channels delivered by the corresponding line 2, first demultiplexing means in the form of a demultiplexer 102 which demultiplexes the two TI.sub.p and TI.sub.c channels, a flag detector 103 and a call register 104. The reception part 11 of equipment S.I.E. comprises first multiplexing means in the form of a multiplexer 111 and a reshaping circuit 112.
The multiplexer 102 comprises a shift register 1020 having 16 binary stages into which data are written at the 128 kHz frequency. This register 1020 acts as a series-to-parallel converter that is read out at the 8 kHz frequency. The contents of the last eight stages represent an octet transmitted from the circuit mode channel TI.sub.c to a buffer register 1021.
In conjunction with the preceding transfer, the contents of the first eight stages of the register 1020 are written in a second buffer register 1022 and delivered to the flag detector 103. This detector compares each received binary word with a previously stored word F=0 1 1 1 1 1 1 0. Following a sequence of contiguous flags, once the detector 103 detects the absence of a flag, i.e. the start of a control frame CF, it delivers a transmit authorization signal to the call register 104. The latter is synchronized by time base 9 and supplies along the bus 184 a switching request intended for the marking unit 183, whilst indicating the address of the line 2. The marking unit 183 searches for a free line amongst the Q lines 5.sub.1 to 5.sub.Q. To this end, it examines either the contents of a "free" or "occupied" status internal memory for lines 5.sub.1 to 5.sub.Q, or the contents of the control memory 194 by reading along the link 182. If there is no free line 5, the unit 183 does not connect the line 2 to a line 5, which is no way troublesome for the reason that since the D.T.E. 22 in question has emitted a frame, it can repeat the re-emission ten or so times until it receives a response frame RF delivered by the packet switching network 6. In the opposite case, the unit 183 sends a double marking order to the control memory 194 so as to establish a bidirectional connection in switching network 19 between the line 2 and the selected line 5 (2 to 5 and 5 to 2).
Once the frame exchange or exchanges have finished, the packet switching network 6 gives the marking unit 183 the order to disconnect the lines 2 and 5, via the bus 60. This order follows the detection of an RF emitted from the D.T.E. 22 or the emission from the switching network 6 of an RF. The unit 183 supplies an order to control memory 194 to cancel the addresses corresponding to the previously established link. This cancellation order consists, in fact, of making unidirectional connections in switching network 19 between the previously connected outgoing channels of lines 2 (TI.sub.p) and 5, and a particular line 3 which continually supplies to system 1 a particular code identical to the flag code 0 1 1 1 1 1 1 0. In this way, after each disconnection or, more generally, for channels TI.sub.p and unconnected lines 4 and 5, the switching network 19 continually transmits flags from a particular incoming line 3 to outgoing lines 4, 5 and the outgoing channels TI.sub.p of outgoing lines 2 of the system 1.
As can be seen on FIG. 2, the multiplexer 111 comprises two buffer registers 1111 and 1112 which receive the 64 kbit/s channels TI.sub.p and TI.sub.c in parallel from the demultiplexer 181, and a shift register 1110 for retransmitting the multiplexed and channels TI.sub.p and TI.sub.c to the line 2 via the reshaping circuit 112. The multiplexer 111 performs the inverse function of demultiplexer 102.
Indeed, as already pointed out, the packet switching network 6, prior to any frame being transmitted along a line 5, requests the marking unit 183, via the bus 60, to carry out a connection performed by switching network 19 between said line 5 and a destination line 4 or a destination channel TI.sub.p on a line 2. A P.N.I.E. connected to the packet switching network 6 does not need to detect a flag absence since the connection is established beforehand. After frame exchange has occured, the switching network 6 asks the marking unit 183 for a disconnection, along the bus 60. The unit 183 delivers the disconnection order to the switching network 19 which therefore connects outgoing lines with a line 3 continually emitting the flag code 0 1 1 1 1 1 1 0, as previously described.
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