Source: http://www.google.co.uk/patents/US7159041?hl=en&output=html_text
Timestamp: 2018-01-20 19:22:59
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Matched Legal Cases: ['art/9612', 'art4', 'art/9606', 'art4', 'art/9606', 'art7', 'art/9606', 'art5', 'art/9606', 'art6', 'art/9606', 'art8', 'art 2']

Patent US7159041 - Method and system for defining and controlling algorithmic elements in a ... - Google Patents
An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are...http://www.google.co.uk/patents/US7159041?utm_source=gb-gplus-sharePatent US7159041 - Method and system for defining and controlling algorithmic elements in a graphics display system
Publication number US7159041 B2
Application number US 09/796,577
Also published as US7782316, US7800606, US7800607, US7884817, US7965288, US20020033817, US20050027682, US20050052456, US20050086317, US20050086669, US20100039430
Publication number 09796577, 796577, US 7159041 B2, US 7159041B2, US-B2-7159041, US7159041 B2, US7159041B2
Patent Citations (24), Non-Patent Citations (75), Referenced by (12), Classifications (8), Legal Events (4)
US 7159041 B2
In an exemplary embodiment, a developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip. Further background, hereby incorporated by reference in its entirety, may be found in U.S. patent Appln. 09/801,079 entitled “API Communications For Vertex And Pixel Shaders” having inventors Boyd and Toelle.
Stream Data Definition (single DWORD token) Vertex Input Register Load
D3DVSD—TOKEN_NOP=0, //NOP or extension
D3DVSD—TOKEN_STREAM, //stream selector
D3DVSD—TOKEN_STREAMDATA, //stream data definition (map to vertex input memory)
D3DVSD_TOKEN_TESSELLEATOR, //vertex input memory from tessellator
D3DVSD_TOKEN_CONSTMEM, //constant memory from shader
D3DVSD_TOKEN_EXT, //extension
D3DVSD_TOKEN_END=7, //end-of-array (requires all DWORD bits to be 1)
D3DVSD_FORCE_DWORD=0x7fffffff,//force 32-bit size enum
#define D3DVSD13DATALOADTYPESHIFT 28
#define D3DVSD13DATALOADTYPEMASK (0x1<<
#D3DVSD_DATALOADTYPESHIFT)
#define D3DVSD_VERTEXREGINSHIFT20
#define D3DVSD_CONSTADDRESSMASK (0xF<<
#define D3DVSD_CONTRSSHIFT 16
#define D3DVSD_(0x1F<<D3DVSD_EXTCOUNTSHIFT)
#define D3DVSD_MAKETOKENTYPE(tokenType) ((tokenType<<
//macros for generation of Create VertexShader Declaration token array
//Set current stream
//_StreamNumber [0..(MaxStreams-1)]stream to get data from
//Set tessellator stream
(D3DVSD_MAKETOKENTYPE(D3DVSD_TOKEN—STREAM)|
//bind single vertex register to vertex element from vertex stream
//_VertexRegister [0..15] address of the vertex register
//_Type [D3DVSDT_*] dimensionality and arithmetic data type
(D3DVSD_MAKETOKENTYPE(D3DVSD_TOKEN_STREAMDATA)\
((_Type)<<D3DVSD_DATATYPESHIFT)|(_VertexRegister))\
//Skip_DWORDCount DWORDs in vertex
#define D3DVSD_SKIP(_DWORDCount)| \
//load data into vertex shader constant memory
//_ConstantAddress [0..95]-address of constant array to begin filling data
//_Count [0..15]-number of constant vectors to load (4 DWORDs each)
//followed by 4*_Count DWORDS of data
#define D3DVSD_CONST(_ConstantAddress,_Count)\
//enable tessellator generated normals
//_VertexRegisterIn [0..15] address of vertex register whose input stream
//will be used in normal computation
//_VertexRegisterOut [0..15] address of vertex register to output the normal to
#define D3DVSD_TESSNORMAL(_VertexRegisterIn,_VertexRegisterOut)\
//enable tessellator generated surface parameters
//Generates END token
//Generates NOP token
//bit declarations for _Type fields
#define D3DVSD_FLOAT1 0x00 //1D float expanded to (value, 0., 0.,1.)
#define D3DVSD_FLOAT2 0x01 //2D float expanded to (value, value, 0., 1.)
#define D3DVSD_FLOAT3 0x02 //3D float expanded to (value, value, value, 1.)
#define D3DVSDT_FLOAT4 0x03 //4D float
#define D3DVSDT_D3DCOLOR 0x04 //4D packed unsigned bytes mapped to 0. to 1. range
#define D3DVSDT_UBYTE4 0x05 //4D unsigned byte
#define D3DVSDT_SHORT2 0x06 //2D signed short expanded to (value, value, 0., 1.)
#define D3DVSDT_SHORT4 0x07 //4D signed short
//assignments of vertex input registers for fixed function vertex shader
//Maximum supported number of texture coordinate sets
#define D3DDP_MAXTEXCOORD8
//Pixel Shader (PS) & Vertex Shader (VS) Instruction Token Definition
//**** Version Token ****
//[015:08] major version number
//**** End Token ****
//[31:00] 0x0000FFFF
//[15:00] 0xFFFE
//[30:16] DWORD Length (up to 2{circle around ( )}15 DWORDS =128 KB)
// ****Instruction Token ****
//[15:00] Opcode (D3DSIO_*)
//[23:16] Opcode-Specific Controls
//[29:24] Reserved 0x0
//[30] Co-Issue—if set then execute this instruction with the previous instruction(s)
//**** Destination Parameter Token ****
//[07:00] Register Number (offset in register file)
//[15;08] Reserved 0x0
//[23:30]
//[27:24]
//[30:28]VS Reserved Type
// VS Reserved Type
//**** Source Parameter Token ****
//[12:00] Register Number (offset in register file)
//[14:15]
//[23:16] Source Component Swizzle
//[27:24] Source Modifier
The exception for source parameter tokens is with the instruction:
//D3DSIO_DEF c#,f0,f1,f2,f2
//Here, the source parameter tokens (f#) are each taken as 32 bit floats.
//Instruction Token Bit Definitions
D3DSIO_NOP=0, //PS/VS
D3DSIO_MOV, //PS/VS
D3DSIO_ADD, //PS/VS
D3DSIO_SUB, //PS
D3DSIO_MAD, //PS/VS
D3DSIO_MUL, //PS/VS
D3DSIO_DP3, //PS/VS
D3DSIO_DP4, //PS/VS
D3DSIO_MIN, //VS
D3DSIO_MAX, //VS
D3DSIO_SLT, //VS
D3DSIO_SGE, //VS
D3DSIO_EXP, //VS
D3DSIO_LOG, //VS
D3DSIO_LIT, //VS
D3DSIO_DST, //VS
D3DSIO_LRP, //PS
D3DSIO_FRC, //VS
D3DSIO_M4x4, //VS
D3DSIO_M4x3, //VS
D3DSIO_M3x4, //VS
D3DSIO_M3x3, //VS
D3DSIO_TEXCOORD=64, //PS
D3DSIO_TEXKILL, //PS
D3DSIO_TEX, //PS
D3DSIO_TEXBEM, //PS
D3DSIO_TEXBEML, //PS
D3DSIO_TEXREG2AR, //PS
D3DSIO_TEXREG2GB, //PS
D3DSIO_TEXM3x2PAD, //PS
D3DSIO_TEXM3x3VSPEC, //PS
D3DSIO_EXPP, //VS
D3DSIO_LOGP, //VS
D3DSIO_CND, //PS
D3DSIO_DEF, //PS
D3DSIO_RESERVED0=96, //PS
D3DSIO_RESERVED1, //PS
D3DSIO_RESERVED2, //PS
D3DSIO_RESERVED3, //PS
;end _internal
D3DSIO_FORCE_DWORD=0x7fffffff, //force 32-bit size enum.
}D3DSHADER_INSTRUCTION_OPCODE_TYPE;
//Co-Issue Instruction Modifier-if set then this instruction is to be
//issued in parallel with the previous instruction(s) for which this bit
Parameter Token Bit Definitions
//destination parameter write mask
#define D3DSP_WRITEMASK—0 0x00010000//Component 0(X;Red)
#define D3DSP_WRITEMASK—1 0x00020000//Component 1(Y;Green)
#define D3DSP_WRITEMASK—0 0x00040000//Component 2(Z;Blue)
#define D3DSP_WRITEMASK—0 0x00080000//Component 3(W;Alpha)
#define D3DSP_WRITEMASK_ALL 0x000F0000//All Components
//destination parameter modifiers
D3DSPDM_NONE=0<<D3DSP_DSTMOD_SHIFT, //nop
D3DSPDM_SATURATE=1<<D3DSP_DSTMOD_SHIFT, //clamp to 0. to 1. range
D3DSPDM_FORCE_DWORD=0x7ffffff, //force 32-bit size enum
//destination parameter shift
//destination/source parameter register type
D3DSPR_TEMP=0<<D3DSP_REGTYPE_SHIFT, //Temporary Register File
D3DSPR_INPUT=1<<D3DSP_REGTYPE_SHIFT, //Input Register File
D3DSPR_CONST=2<<D3DSP_REGTYPE_SHIFT, //Constant Register File
D3DSPR_ADDR=3<<D3DSP_REGTYPE_SHIFT, //Address Register (VS)
D3DSPR_TEXTURE=3<<D3DSP_REGTYPE_SHIFT, //Texture Register File (PS)
D3DSPR_RASTOUT=4<<D3DSP_REGTYPE_SHIFT, //Rasterizer Register File
D3DSPR_ATTROUT=5<<D3DSP_REGTYPE_SHIFT, //Attribut Output Register File
D3DSPR_TEXCRDOUT=6<<D3DSP_REGTYPE_SHIFT, //Texture Coordinate Output Register File
D3DSPR_FORCE_DWORD=0x7fffffff, //force 32-bit size enum
}D3SHADER_PARAM_REGISTER_TYPE;
//Register offsets in the Rasterizer Register File
D3DSRO_FORCE_DWORD=0x7fffffff, //force 32-size enum
}D3DVS_RASTOUT_OFFSETS;
//Source operand addressing modes
D3DVS_ADDRMODE_FORCE_DWORD=0x7fffffff, //force 32-bit size enum
//Source operand swizzle definitions
//The following bits define where to take component X:
//The following bits define where to take component Y:
//The following bits define where to take component Z:
//The following bits define where to take component W:
//Value when there is no swizzle (X is taken from X, Y is taken from Y,
//Z is taken from Z, W is taken from W
//source parameter swizzle
#define D3DSP_NO SWIZZLE\
//pixel-shader swizzle ops
//source parameter modifiers
typedef enum_D3SHADER_PARAM_SRCMOD_TYPE
D3DSPSM_NONE=0<<D3DSP_SRCMOD_SHIFT, //nop
D3DSPSM_NEG=1<<D3DSP_SRCMOD_SHIFT, //negate
D3DSPSM_BIAS=2<<D3DSP_SRCMOD_SHIFT, //bias
D3DSPSM_BIASNEG=3<<D3DSP_SRCMOD_SHIFT, //bias and negate
D3DSPSM_SIGN=4<<D3DSP_SRCMOD_SHIFT, //sign
D3DSPSM_SIGNNEG=5<<D3DSP_SRCMOD_SHIFT, //sign and negate
D3DSPSM_COMP=6<<D3DSP_SRCMOD_SHIFT, //complement
D3DSPSM_FORCE_DWORD=0x7fffffff, //force 32-bit size enum
}D3SHADER_PARAM_SRCMOD_TYPE;
//pixel shader version token
#define D3DPS_VERSION(_Major,_Minor) (0xFFFF0000|((_Major)<<8|(—Minor))
//vertex shader version token
#define D3DVS_VERSION(_Major,_Minor) (0xFFFE0000|((_Major)<<8|(—Minor))
//extract major/minor from version cap
#define D3SHADER_VERSION_MAJOR(_Version) (((_Version)8)&0xFF)
#define D3SHADER_VERSION_MINOR(_Version) (((_Version)0)&0xFF)
#define D3SHADER_COMMENT(_DWordSize)\
//pixel/vertex shader end token
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U.S. Classification 709/246, 345/419, 345/418
International Classification G06T15/00, G06F15/16, G06F17/00
Free format text: CORRECTED RECORDATION FORM COVER SHEET TO CORRECT ERROR IN THE SERIAL NUMBER PREVIOUSLY RECORDED ATREEL/FRAME 011743/0859 (ASSIGNMENT OF ASSIGNOR S INTEREST);ASSIGNORS:BOYD, CHARLES N.;TOELLE, MICHAEL A.;REEL/FRAME:012051/0644