Source: http://www.google.com/patents/US5594762?dq=6233682
Timestamp: 2016-05-26 19:19:43
Document Index: 183414431

Matched Legal Cases: ['art 1', 'art 12', 'art 11', 'art 12', 'art 11', 'art 14', 'art 15', 'art 13', 'art 14', 'art 14', 'art 13', 'art 12', 'art 15', 'art 15', 'art 12', 'art 14', 'art 17', 'art 16', 'art 17', 'art 15', 'art 17', 'art 15', 'art 16', 'art 12', 'art 12', 'art 11', 'art 14', 'art 15', 'art 12', 'art 13', 'art 14', 'art 14', 'art 15', 'art 16', 'art 17', 'art 14', 'art 12', 'art 13', 'art 14', 'art 15', 'art 15', 'art 17', 'art 12', 'art 14', 'art 12', 'art 14', 'art 12', 'art 15', 'art 16', 'art 15', 'art 17', 'art 17', 'art 16', 'art 15', 'art 11', 'art 12', 'art 16', 'art 16']

Patent US5594762 - Apparatus for retiming digital data transmitted at a high speed - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThis invention relates to an apparatus for retiming digital data transmitted at a high speed even though the phase of a binary data bit is not related to the phase of the static offset of a retiming clock pulse, the apparatus comprising: local clock pulse generation means 11 for generating and outputting...http://www.google.com/patents/US5594762?utm_source=gb-gplus-sharePatent US5594762 - Apparatus for retiming digital data transmitted at a high speedAdvanced Patent SearchPublication numberUS5594762 APublication typeGrantApplication numberUS 08/354,417Publication dateJan 14, 1997Filing dateDec 12, 1994Priority dateDec 11, 1993Fee statusLapsedPublication number08354417, 354417, US 5594762 A, US 5594762A, US-A-5594762, US5594762 A, US5594762AInventorsBheom S. Joo, Bhum C. Lee, Jung S. Kim, Seok Y. KangOriginal AssigneeElectronics And Telecommunications Research InstituteExport CitationBiBTeX, EndNote, RefManPatent Citations (13), Non-Patent Citations (2), Referenced by (30), Classifications (18), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetApparatus for retiming digital data transmitted at a high speed
US 5594762 AAbstract
This invention relates to an apparatus for retiming digital data transmitted at a high speed even though the phase of a binary data bit is not related to the phase of the static offset of a retiming clock pulse, the apparatus comprising: local clock pulse generation means 11 for generating and outputting local clock pulse FT; delayed clock pulse parallel generation means 12 for outputting, in parallel, n delayed clock pulses delayed sequentially by one cycle of local clock pulse FT; input data transition detection means 13 for outputting pulse DT each time the rising and falling carrier waves intersect in input data D; sequential logic parallel phase detection means 14 for providing clock pulse selection data by outputting sequential logic phases of the upper location of the pulse generated during input data transition and transition location of n delayed clock pulses; retiming clock pulse selection means 15 for outputting a retiming clock pulse according to the clock pulse selection data of the input delayed clock pulses; time delay compensation means 16 for outputting delayed input data; and data retiming means 17 for outputting the data retimed DR according to the retiming clock pulse.
1. An apparatus for retiming digital data transmitted at a high speed, the apparatus comprising:local clock pulse generation means for generating and outputting a local clock pulse; delayed clock pulse parallel generation means for delaying an external clock pulse CP by a period independent of the local clock pulse from said local clock pulse generation means and outputting n delayed clock pulses in parallel, n being a natural number greater than or equal to 4, said delayed clock pulse parallel generation means including a plurality of flip-flops, each of said flip-flops having a minimum allowable clock pulse width; input data transition detection means for receiving an external input data signal D having a unit bit interval with rising and falling portions and for outputting a pulse DT whenever the rising and falling portions are sensed in the external input data signal D, the pulse DT being shorter than the unit bit interval of the external data signal D and longer than the minimum allowable clock pulse width of the flip-flops; sequential logic parallel phase detection means for providing (n-1) clock pulse selection data signals with a logic phase relation between a first transition point of input data signal DT from said input data transition detection means and a second transition point of n delayed clock pulses input from said delayed clock pulse parallel generation means; retiming clock pulse selection means for outputting a retiming clock pulse by getting input of n-1 delayed clock pulses from said delayed clock pulse generation means and by selecting the delayed clock pulse having a nearest falling portion relative to the first transition point of input data signal DT according to the clock pulse selection data signals from said sequential logic parallel phase detection means; time delay compensation means for outputting a compensated signal after compensating the input data signal D by a time delay due to retiming clock pulse selection in said retiming clock pulse selection means; data retiming means for outputting retimed data signals after performing retiming for time compensated signals from said time delay compensation means according to retiming clock pulse input from said retiming clock pulse selection means. 2. An apparatus according to claim 1, wherein said local clock pulse generation means generates a first frequency more than four times a second frequency of input data signal D, and outputs the local clock pulse having period longer than the total sum of setup time and hold time of one of said flip-flops.
3. An apparatus according to claim 1 wherein said delayed clock pulse parallel generation means comprises n D-type flipflops, so as to meet the requirement of n times one period of the local clock pulse being greater than one period of the clock pulse CP, and outputs clock pulses CP1, CP2, CP3, . . . , CP(n-1), CPn to said sequential logic parallel phase detection means and n-1 clock pulses CP1, CP2, . . . , CP(n-1) to said retiming clock pulse selection means.
4. An apparatus according to claim 1 wherein said retiming clock pulse selection means compares the phase of a clock pulse CPi, which is CP delayed by i periods of the local clock pulse output, i being an arbitrary number between 1 and n-1, from said delayed clock pulse parallel generation means with that of clock pulse selection data signals from said sequential logic parallel phase detection means, and then, after selecting at least one clock pulse having a falling portion nearest the first transition point, performs the logic function AND on the selected at least one clock pulse and outputs a resulting signal to said data retiming means.
The present invention relates to an apparatus for retiming digital data transmitted at a high speed, and more particularly, to an apparatus for retiming it stably, even though the phase of binary data bits is not related to that of static offset of the retiming clock pulses and there are wander and alignment jitter in the input binary data.
Conventional data retiming devices were designed to provide retiming clock pulses, which have a rising edge in the center of the eye pattern or in the interval of data bits transmitted to retiming parts of the transmission side and the receiving side from the source clock generation part, as shown in FIGS. 1A and 1B. The timing of data transmitted in parallel or in serial is predictable at the retiming part of the receiving side due to the relatively slow speed of the data bits. However, it is more difficult to predict phases between receiving data and clock pulse at the retiming part of the receiving side when the interval of data bits is reduced due to the increased speed of data bits. Accordingly, a conventional device for retiming data transmitted at a high speed can not meet the hold time and the setup time of a D-type flip-flop, and metastability occurs. Metastability is also generated due to environmental factors, even though the transmission distance is relatively short and the size of alignment jitter is small. These matters make stable retiming impossible.
To solve the above problems, a variety of methods using the concept of bit synchronization of transmission have been provided, in which the transmission side transmits only data and the receiving side generates retiming clock pulses from the received data through a non-linear process or performs data retiming by generating retiming clock pulses with a voltage control oscillator. Representative references are C. P. Summers (U.S. Pat. No. 4,422,176), M. Belkin (U.S. Pat. No. 4,400,667), and C. R. Hogge (U.S. Pat. No. 4,535,459). In addition, an application retiming device (AMCC 20P025, retiming chip Applied by Micro Corp.) was invented. However, these methods have a bit synchronization device with a complicated structure. While the devises perform stable data retiming for transmitting data at a high speed, they are too complex and non-economical to use for a data link which is transmitted in parallel because integration is difficult due to use of analog parts, such as a voltage control oscillator and a low pass filter.
Additionally, digital bit synchronization devices perform received data retiming by using a clock pulse with a cycle of 1/16 times data unit bit interval transmitted, such as M. Tanaka (U.S. Pat. No. 4,385,395). Tanaka has the advantage of not using an analog low-pass filter, but has the disadvantage of not being suitable for performing data retiming at a high speed, since that requires a more stable clock pulse than the data bits at the high speed.
On the other hand, Kwan (U.S. Pat. No. 5,036,529) discloses a retiming device which adapts received data to the retiming clock pulse by delaying the data with active delay elements. This device has the advantage of performing a relatively stable retiming function by using a clock pulse with the same period as the data unit bit interval, but the device can not perform stable retiming functions when the static offset phase between the data and the clock pulse reaches the limitation of the delay element alignment jitter.
An object of the present invention is to solve the above-mentioned problems encountered in the prior art and, thus, provide an apparatus for retiming digital data in a high speed transmission, capable of achieving suitable retiming clock pulses. The apparatus eliminates generation of metastability by transmission or by environmental factors, and also eliminates alignment jitter generated in the transmitted data using a digital logic element when the transmission distance is relatively short and an exterior retiming clock pulse has the same period as the unit bit interval of the transmission data and has an arbitrary static offset phase with the data.
In accordance with the present invention, the above and other objects can be accomplished by provision of an apparatus for retiming digital data comprising local clock pulse generation means for generating and outputting local clock pulse; delayed clock pulse parallel generation means for delaying an external clock pulse by a period of the local clock pulse from the local clock pulse generation means and outputting the n (n is natural number greater than or equal to 4) delayed clock pulses in parallel; input data transition detection means for outputting a pulse DT that is shorter than the unit interval of input data and longer than the minimum allowable clock pulse width of a D-type flip-flop belonging to each component whenever the alternating rising and falling edges of the data carrier pulse intersect the external input data D; sequential logic parallel phase detection means for providing n-1 clock pulse selection data signals by logically outputting the phase relation between the transition point of an input data signal from the input data transition detection means and the transition point of n delayed clock pulses input from the delayed clock pulse parallel generation means; retiming clock pulse selection means for outputting a retiming clock pulse by getting the input of the n-1 delayed clock pulses from the delayed clock pulse parallel generation means and by selecting the delayed clock pulses which have the nearest falling portion relative to the transition timing edge of input data signal D according to the clock pulse selection data signals from the sequential logic parallel phase detection means; time delay compensation means for outputting a time compensated signal after compensating the input data signal D by a time delay due to the selecting process of the retiming clock pulse in the retiming clock pulse selection means; and data retiming means for outputting retimed data signals after performing the retiming for the time compensated signals from the time delay compensation means according to the retiming clock pulse input from the retiming clock pulse selection means.
FIG., 1A is a block diagram of a conventional data retiming device;
FIG. 1B is a timing diagram of signals in the principal parts of the conventional data retiming device;
FIG. 2 is a block diagram of a digital data retiming device in accordance with the present invention;
FIG. 3A is a detailed circuit diagram of the delayed clock pulse parallel generation part in accordance with the present invention;
FIG. 3B is a timing diagram of signals in the principal parts of the delayed clock pulse parallel generation part in accordance with the present invention;
FIG. 4A is a detailed block diagram of the input data transition detection part in accordance with the present invention;
FIG. 5B is a timing diagram of signals in the principal parts of the input data transition detection part in accordance with the present invention;
FIG. 5 is a detailed circuit diagram of the sequential logic parallel phase detection part, the retiming clock pulse selection part, the time delay compensation part, and the data retiming part; and
FIG. 6 is a timing diagram of signals in the principal part in accordance with the present invention.
FIG. 2 is a block diagram of a data retiming device in accordance with the present invention. As shown in FIG. 2, a local clock pulse generation part 1t generates a clock pulse whose frequency is more than four times the speed of binary data bit input from outside and whose period is longer than the total sum of the setup time and hold time of any of the flip-flops 31, 32, 33, . . . , 3(n-1), 3n (see FIG. 3) and sends it to a delayed clock pulse parallel generation part 12 described below. Such a local clock pulse generation part 11 may be formed by a ring oscillator (not shown) or other suitable means.
The delayed clock pulse parallel generation part 12 delays the clock pulse input CP from outside by one period of the local clock pulse generated in the local clock pulse generation part 11, and outputs n delayed clock pulses (n being a natural number greater than or equal to 4) where the total delay time becomes longer than one period of the clock pulse input CP from outside, to a sequential logic parallel phase detection part 14 and a retiming clock pulse selection part 15 described below.
An input data transition detection part 13 generates a pulse whenever alternating rising and falling portions of external binary input data signal D are sensed, which pulse being shorter than the input data unit bit interval but longer than or equal to the minimum allowable clock pulse width of a flip-flop 31, 32, 33, . . . , 3(n-1), 3n and is synchronized with the input data transition and outputted to a sequential logic parallel phase detection part 14 described below.
The sequential logic parallel phase detection part 14 outputs clock pulse selection data signals with a logic phase relation between the rising portion of the pulse generated during the transition of input data received from the input data transition detection part 13 and the transition point of n delayed clock pulses received from the delayed clock pulse parallel generation part 12, and outputs the clock pulse selection data signals to a retiming clock pulse selection part 15, described below.
The retiming clock pulse selection part 15 receives n-1 delayed clock pulses from the delayed clock pulse parallel generation part 12 and selection data about the n-1 delayed clock pulses from the sequential logic parallel phase detection part 14. Thereafter, it selects the delayed clock pulse whose difference of input data transition point and delayed clock pulse transition point is within one period of the local clock pulse and whose falling portion is generated at the closest point to a transition timing point of the input data among the n-1 delayed clock pulses, and outputs it to a data retiming part 17, described below.
The time delay compensation part 16 receives external binary data input and it outputs delayed data to data retiming part 17. This output delayed data has been compensated by the time delay in the process of the retiming clock pulse selection in the retiming clock pulse selection part 15.
The data retiming part 17 receives the retiming clock pulse from the retiming clock pulse selection part 15 and performs retiming of the time compensated data received from the time delay compensation part 16 and then outputs the retimed data.
FIG. 3A shows a circuit diagram of the delayed clock pulse parallel generation part 12 in accordance with the present invention. As shown in FIG. 3A, in the delayed clock pulse parallel generation part 12, D-type flip-flops 31, 32, and 33, 3(n-1), 3n generate n clock pulses CP1, CP2, CP3, . . . , CP(n-1) CPn which are clock pulse CP delayed sequentially by 1 period, 2 periods, 3 periods, . . . , (n-1) periods, n periods of FT by the local clock pulse FT generated in the local clock pulse generation part 11 in FIG. 2. This occurs if the external clock pulse CP period is the same as the unit bit interval of the binary data transmitted from outside and the external clock pulse CP has an arbitrary static offset phase with the data. Here, n refers to a natural number greater than or equal to 4 which meets the requirement of n x one period of FT (TFT)>one period of CP (TCP). The n clock pulses CP1, CP2, CP3, . . . , CP(n-1), CPn and the n-1 clock pulses CP1, CP2, CP3, . . . , CP(n-1) are output to the sequential logic parallel phase detection part 14 and the retiming clock pulse selection part 15 of FIG. 2, respectively.
FIG. 3B shows the timing diagram of signals for the principal parts of the delayed clock pulse parallel generation part 12. It indicates that n clock pulses are generated whose phase difference is one period interval of the local clock pulse FT during the minimum period longer than the TCP (one period of cp).
FIG. 4A shows a detailed block diagram of the input data transition detection part 13 in accordance with the present invention.
As shown in FIG. 4A, the delay part d consists of logic element gates, which delays binary data D input from outside and then outputs them to an input terminal of exclusive OR gate 41.
After this process, exclusive OR gate 41 performs exclusive OR of the delayed data D' through the delay part D2 with external binary input data D. It then outputs the pulse DT longer than or equal to the minimum allowable clock pulse width to the sequential logic parallel phase detection part 14, as shown in FIG. 2, when rising and falling edges are generated in the binary data D input from the outside.
FIG. 4B shows a timing diagram of signals in the principal parts of the input data transition detection part in accordance with the present invention. It includes binary data D which is input from the outside, delayed data D', and the signal between the pulses DT generated during data transition. Phase difference between the data transition point and the rising edge of DT shall be designed to the minimum.
FIG. 5 shows a detailed circuit diagram of the sequential logic parallel phase detection part 14, the retiming clock pulse selection part 15, the time delay compensation part 16, and the data retiming part 17.
In sequential logic parallel phase detection part 14, n D-type flip-flops 511, 512, 513, . . . , 51(n-1), 51n each receives input of n delayed clock pulses CP1, CP2, CP3, . . . , CP(n-1), CPn which are output from the delayed clock pulse parallel generation part 12 through corresponding data input terminal, and pulse DT which is output from the input data transition detection part 13 through the corresponding clock pulse input terminal. Then, the sequential logic parallel phase detection part 14 outputs the phase value of n clock pulses CP1, CP2, CP3, . . . , CP(n-1), CPn at DT's rising edge in the form of logic level. The n-1 inverters 521, 522, . . . , 52(n-1) invert each output of the n-1 D-type flip-flops 512, 513, . . . , 51(n-1), 551n.
The `i`th (i is a number from 1 to n-1) OR gate 53i of n-1 OR gates 531, 532, 533, . . . , 53(n-1) performs OR of the output of the inverter 52i, which inverted D-type flip-flop 51(i+1) showing the phase of the CP(i+1) (clock pulse delayed by the (i+1) period by the local clock pulse FT) with logic value, and the output of the D-type flip-flop 51i showing the phase of CPi (clock pulse delayed by i by the local clock pulse FT) in logic value at the timing point of transition generation in the input data (rising edge of DT). Then the OR gate outputs the result to the retiming clock pulse selection part 15.
Since the output of `i`th OR gate 53i is the resulting OR of the output of the `i`th D-type flip-flop 51i and the inverted ouput of the `(i+1)`th D-type flip-flop 51(i+1), then the output of the `i`th OR gate 53i becomes logic level "0" when the output of the `i`th D-type flip-flop 51i is logic level "0" and the output of the `(i+1)`th D-type flip-flop 51(i+1) is logic level "1" at the same time. This indicates that the falling edge took place for CPi right before the. rising edge (input data transition point intersection generation) in DT pulse and the falling edge took place for CP(i+1) right after the rising edge occurring in DT pulse.
That is, CPi or CP(i+1) is a clock pulse having the largest timing margin in retiming the input data D which generates the falling edge closest to the transition point in the input data.
The retiming clock pulse selection part 15 performs AND of the selected clock pulses in AND gate 62, which has an n-1 input terminal, after selecting more than or as many as 1 among the n-1 delayed clock pulses and outputs them to the data retiming part 17. In other words, it performs OR of n-1 delayed clock pulse CP1, CP2, CP3, . . . , CP(n-1) outputs from the delayed clock pulse parallel generation part 12 and clock pulse selection data output from n-1 OR gates 531, 532, 533, . . . , 53(n-1) of the sequential logic parallel phase detection part 14 through n-1 OR gates 611, 612, 613, . . . , 61(n-1). That is, the `i`th OR gate 61i outputs the clock pulse CPi output from the delayed clock pulse parallel generation part 12 when the output of the `i`th OR gate 53i of the sequential logic parallel phase detection part 14 is logic level "0", or in other words, only when the falling edge of the CPi (clock pulse delayed by i period by the local clock pulse FT) is right before the data transition point and the falling edge of CP(i+1) is right after the data transition point.
Since `n` in the delayed clock pulse generation part 12 was selected from natural numbers greater than or equal to 4, which meets the requirement of n�TFT (one period of local clock pulse) > TCP (one period of input clock pulse from outside), at least one out of the n-1 OR gates 611, 612, 613, . . . , 61(n-1) of the retiming clock pulse selection part 15 shall output the clock pulse which rises in the center of the input data eye pattern, as shown in FIG. 6.
Time delay compensation part 16 delays the external binary data D input by a transmission delay time DS in OR gate 61i of the retiming clock pulse selection part 15 and AND gate 62 which has an n-1 input terminal through the delay part D3 consisting of logic element gates, and outputs the time delay compensated data DD to the data retiming part 17.
Data retiming part 17 receives input of the time delay compensated data DD from the time delay compensation part 16 through the data input terminal and the retiming clock pulse ouput from the retiming clock pulse selection part 15 through the clock pulse input terminal, and then outputs the data after retiming them.
FIG. 6 shows a timing diagram of signals in the principal part of a preferred embodiment in accordance with the present invention. As shown in FIG. 6, the local clock pulse FT generated from the local clock pulse generation part 11 has a frequency which is 6 times the bit speed of binary data input. The delayed clock pulse parallel generation part 12 delays the external clock pulse CP, which is input from outside sequentially by the interval of one period of the local clock pulse FT, to generate 7 delayed clock pulses CP1, CP2, CP3, CP4, CP5, CP6, CP7. It shows that the retiming clock pulse in the data retiming part 16 retimes data in the center of the data eye pattern if the delay time of the retiming clock pulse in the retiming clock pulse selection process is equal to that of the data DD time delay compensated in the time delay compensation part 16.
First, the present invention can be integrated into a semiconductor since only the local clock pulse, whose frequency is greater than or equal to four times the retiming clock pulse, is required.
Second, the present invention can apply to a data retiming device with a wide range of bit speed by making the total delay time of n delayed clock pulses sufficiently long.
Third, the present invention can eliminate jitter and wander.
Fourth, the present invention provides stable operation against environmental change and can be applied to implementation of high speed bit synchronization of more advanced semiconductor integration in the future.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4385395 *Apr 15, 1981May 24, 1983Sony CorporationBit clock reproducing circuitUS4400667 *Jan 12, 1981Aug 23, 1983Sangamo Weston, Inc.Phase tolerant bit synchronizer for digital signalsUS4422176 *Nov 27, 1981Dec 20, 1983U.S. Philips CorporationPhase sensitive detectorUS4535459 *May 26, 1983Aug 13, 1985Rockwell International CorporationSignal detection apparatusUS4672639 *May 21, 1985Jun 9, 1987Kabushiki Kaisha ToshibaSampling clock pulse generatorUS4814879 *Aug 7, 1987Mar 21, 1989Rca Licensing CorporationSignal phase alignment circuitryUS5036529 *Apr 20, 1990Jul 30, 1991Electronics And Telecommunications Research InstituteDigital auto-phase-controlled retiming circuitUS5101419 *Apr 18, 1990Mar 31, 1992Advanced Micro Devices, Inc.Fixed duty cycle clock generatorUS5280539 *May 29, 1992Jan 18, 1994Samsung Electronics Co., Ltd.Synchronous circuit for serial input signalUS5359630 *Aug 13, 1992Oct 25, 1994Digital Equipment CorporationMethod and apparatus for realignment of synchronous dataDE4142825A1 *Dec 23, 1991Jul 2, 1992Mitsubishi Electric CorpSynchronised clock pulse generator with delay elements - which are series-connected for generating delayed clock pulse signals w.r.t. input delay cycle circuitJPH0568025A * Title not availableJPS60143017A * Title not available* Cited by examinerNon-Patent CitationsReference1"An ECL gate array with integrated PLL-based clock recovery and synthesis for high speed data and telecom applications", by David S. Rosky, Bruce H. Coy, and Marc Friedman, SPIE, vol. 1577, 1991, pp. 182-191.2 *An ECL gate array with integrated PLL based clock recovery and synthesis for high speed data and telecom applications , by David S. Rosky, Bruce H. Coy, and Marc Friedman, SPIE, vol. 1577, 1991, pp. 182 191.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5963606 *Jun 27, 1997Oct 5, 1999Sun Microsystems, Inc.Phase error cancellation method and apparatus for high performance data recoveryUS6154509 *Jan 16, 1998Nov 28, 2000Natural Microsystems Corp.Data phase recovery systemUS6285722Nov 25, 1998Sep 4, 2001Telcordia Technologies, Inc.Method and apparatus for variable bit rate clock recoveryUS6538475Mar 15, 2000Mar 25, 2003Intel CorporationPhase detectorUS6690217May 7, 2002Feb 10, 2004Matsushita Electric Industrial Co., Ltd.Data width correctorUS6970521Dec 21, 2000Nov 29, 2005Matsushita Electric Industrial Co., Ltd.Circuit and system for extracting dataUS7088796 *Mar 27, 2002Aug 8, 2006Pmc-Sierra Ltd.Phase detector customized for clock synthesis unitUS7268602 *Oct 15, 2004Sep 11, 2007Rambus Inc.Method and apparatus for accommodating delay variations among multiple signalsUS7782682Aug 24, 2010Fujitsu Semiconductor LimitedSemiconductor device with circuitry for efficient information exchangeUS8009763 *Aug 30, 2011Oracle America, Inc.Method and apparatus for equalizing a high speed serial data linkUS8120442 *Nov 7, 2008Feb 21, 2012Hynix Semiconductor Inc.Semiconductor deviceUS8582706Oct 29, 2009Nov 12, 2013National Instruments CorporationTraining a data path for parallel data transferUS20010005156 *Dec 21, 2000Jun 28, 2001Matsushita Electric Industrial Co., Ltd.Circuit and system for extracting dataUS20020125499 *Dec 10, 2001Sep 12, 2002Fujitsu LimitedSemiconductor device with circuitry for efficient information exchangeUS20020154722 *Mar 27, 2002Oct 24, 2002Hormoz DjahanshahiPhase detector customized for clock synthesis unitUS20050068082 *Oct 15, 2004Mar 31, 2005Rambus Inc.Method and apparatus for accommodating delay variations among multiple signalsUS20090252212 *Apr 2, 2008Oct 8, 2009Sun Microsystems, Inc.Method and apparatus for equalizing a high speed serial data linkUS20090302965 *Dec 10, 2009Hynix Semiconductor, Inc.Semiconductor deviceUS20110103533 *Oct 29, 2009May 5, 2011Conway Craig MTraining a Data Path for Parallel Data TransferUS20150162918 *Dec 5, 2013Jun 11, 2015Arm LimitedDigital output clock generationCN101803194BSep 24, 2007Mar 27, 2013高通股份有限公司Signal generator with signal trackingEP1111836A2 *Dec 22, 2000Jun 27, 2001Matsushita Electronics CorporationCircuit and system for extracting dataEP1148646A1 *Apr 19, 2000Oct 24, 2001TOSHIBA Electronics Europe GmbHMethod of optimising digital signal samplingEP1239594A2 *Dec 10, 2001Sep 11, 2002Fujitsu LimitedSemiconductor device with circuitry for efficient information exchangeEP1336270A1 *Sep 24, 2001Aug 20, 2003Telefonaktiebolaget Lm EricssonAn arrangement for capturing dataEP1643652A2 *Dec 10, 2001Apr 5, 2006Fujitsu Ltd.Semiconductor device with circuitry for efficient information exchangeEP1643652A3 *Dec 10, 2001Jul 8, 2009Fujitsu Microelectronics LimitedSemiconductor device with circuitry for efficient information exchangeEP2221969A2 *Mar 23, 2001Aug 25, 2010NEC Electronics CorporationClock control circuit and clock control methodWO2001069786A2 *Mar 15, 2001Sep 20, 2001Giga ApsA phase detectorWO2001069786A3 *Mar 15, 2001Feb 7, 2002Giga ApsA phase detector* Cited by examinerClassifications U.S. Classification375/371, 327/161International ClassificationH03K5/1534, H04L7/00, H03K5/135, H04L25/40, H03K5/15, H04L7/033, H04L7/02, H04L7/04Cooperative ClassificationH03K5/1534, H03K5/135, H03K5/15066, H04L7/0338European ClassificationH03K5/1534, H04L7/033E2, H03K5/135, H03K5/15D6BLegal EventsDateCodeEventDescriptionJul 14, 1995ASAssignmentOwner name: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JOO, BHEOM SOON;LEE, BHUM CHEOL;KIM, JUNG SIK;AND OTHERS;REEL/FRAME:007555/0253Effective date: 19950331Owner name: KOREA TELECOMMUNICATION AUTHORITY, KOREA, REPUBLICFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JOO, BHEOM SOON;LEE, BHUM CHEOL;KIM, JUNG SIK;AND OTHERS;REEL/FRAME:007555/0253Effective date: 19950331Oct 7, 1997CCCertificate of correctionApr 7, 1998CCCertificate of correctionJul 3, 2000FPAYFee paymentYear of fee payment: 4Jun 10, 2004FPAYFee paymentYear of fee payment: 8Jul 21, 2008REMIMaintenance fee reminder mailedJan 14, 2009LAPSLapse for failure to pay maintenance feesMar 3, 2009FPExpired due to failure to pay maintenance feeEffective date: 20090114RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services