Source: http://www.google.com/patents/US5553002?dq=%22frederick+douglis%22
Timestamp: 2015-09-01 21:25:24
Document Index: 531179196

Matched Legal Cases: ['application No. 08', 'application No. 08', 'application No. 07', 'application No. 08', 'application No. 07', 'application No. 07']

Patent US5553002 - Method and system for creating and validating low level description of ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications using a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially...http://www.google.com/patents/US5553002?utm_source=gb-gplus-sharePatent US5553002 - Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interfaceAdvanced Patent SearchPublication numberUS5553002 APublication typeGrantApplication numberUS 08/077,403Publication dateSep 3, 1996Filing dateJun 14, 1993Priority dateApr 6, 1990Fee statusPaidAlso published asUS6324678Publication number077403, 08077403, US 5553002 A, US 5553002A, US-A-5553002, US5553002 A, US5553002AInventorsCarlos Dangelo, Richard Deeley, Vijay Nagasamy, Manoucher VafaiOriginal AssigneeLsi Logic CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (30), Non-Patent Citations (76), Referenced by (104), Classifications (25), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface
US 5553002 AAbstract
A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications using a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized. A top-down design methodology is described, wherein a matrix of milestones (goals in the design activity) is defined by degree of complexity (level of abstraction) of a design and for progressive stages (levels) of design activity (from concept through implementation). The milestones are defined in a monotonic, unidirectional manner using continuous refinement, and the design activity proceeds towards subsequent milestones. As milestones are achieved, previous design activity becomes fixed and unalterable. A feasibility stage is key to convergence of the process. Single level or multi-level estimators (predictors) determine the direction of the process.
1. A method of synthesizing an electronic design, comprising:creating a matrix of milestones, the matrix having columns representing levels of design abstraction and rows representing stages of design development; providing at least one activity associated with each milestone, wherein completion of the at least one activity associated with a corresponding milestone indicates completion of the corresponding milestone; upon completion of a milestone, enabling activities associated with subsequent milestones and disabling all activity associated with previous milestones. 2. A method, according to claim 1, wherein:the stages comprise, in progression: a concept stage, a specification stage; a feasibility stage; a design stage; an implementation stage; and a verification stage. 3. A method, according to claim 1, further comprising:estimating, at a high level of abstraction, low level constraints of a device to be implemented by the electronic design. 4. A method, according to claim 3, wherein:one of the constraints is power dissipated by the device. 5. A method, according to claim 3, wherein:one of the constraints is area occupied by the device. 6. A method, according to claim 3, wherein:one of the constraints is low-level timing parameters of the device. 7. An ECAD system for synthesizing an electronic design, comprising:a user-interface operating on a computer; a milestone matrix incorporated into the user-interface, the milestone matrix having a plurality of matrix elements representing a plurality of milestones to be completed by a user during the synthesis of the electronic design; at least one activity associated with each milestone; transition conditions, incorporated in the computer and associated with the milestone matrix and operable to enable the user to perform the at least one activity for each milestone and to progress to performing the at least one activity associated with the next of the at least one milestones; wherein: completion of the at least one activity associated with a particular milestone indicates completion of the associated milestone; and the transition conditions are established to ensure that the milestones are completed by the user in a progressive order, and that activity for a previous milestone is disabled once a milestone is completed. 8. An ECAD system, according to claim 7, wherein:the milestone matrix is organized in rows and columns; the rows represent different stages of design activity; and the columns represent different levels of design abstraction. 9. An ECAD system, according to claim 8, wherein:the stages of design activity comprise, in progression: a concept stage, a specification stage; a feasibility stage; a design stage; an implementation stage; and a verification stage; and the levels of design abstraction include at least one high-level of abstraction. 10. An ECAD system, according to claim 9, wherein:the levels of design abstraction comprise in progression: a system level; a behavioral level; a micro-architectural level; and a logic level. 11. An ECAD system, according to claim 7, further comprising:a system-level partitioner in the computer for partitioning the electronic design into sub-modules such that a resulting partitioning of the electronic design meets user-defined constraints. 12. An ECAD system, according to claim 11, wherein:the constraints include the parameters of power dissipated by a device and timing of the device implemented by the electronic design. 13. An ECAD system, according to claim 7, further comprising:a multi-level estimator for estimating at least one parameter of a physical implementation of the electronic design. 14. An ECAD system, according to claim 13, wherein:the multi-level estimator provides estimates low-level manifestations of high-level changes to the electronic design. 15. An ECAD system, according to claim 14, wherein:the estimates are provided in response to parameters available at a given level of design abstraction. 16. An ECAD system, according to claim 13, wherein:the parameter is power dissipated by a device representing a physical implementation of the electronic design. 17. An ECAD system, according to claim 13, wherein:the parameter is low-level timing of a device representing a physical implementation of the electronic design. 18. In an ECAD system, a method of creating and validating a low level description of an electronic design from a higher level, behavior-oriented description thereof, comprising:entering on an ECAD system a specification of a desired behavior of an electronic design, including high-level timing goals, in a high-level, behavior-oriented language; on the ECAD system, iteratively simulating and changing the electronic design at the behavioral-level until the desired behavior is obtained; on the ECAD system, partitioning the electronic design into a number of architectural blocks and constraining the architectural choices to those which meet the high-level timing goals; on the ECAD system, directing the various architectural blocks to logic synthesis programs, said logic synthesis programs also running in the ECAD system, thereby providing a low level description of the electronic design; for each change of the behavioral-level description of the electronic design, estimating low-level timing parameters for a physical implementation of the electronic design. creating a matrix of milestones, the matrix having columns representing levels of design abstraction and rows representing stages of design development; providing at least one activity associated with each milestone, wherein completion of the at least one activity associated with a corresponding milestone indicates completion of the corresponding milestone; and upon completion of a milestone, enabling activities associated with subsequent milestones and disabling all activity associated with previous milestones. 19. In an ECAD system, a method of deriving a structural description of a system from a behavioral description thereof, comprising:(a) specifying a behavioral design for a system in a high-level, behavior-oriented language; (b) describing, in the high-level language, a functional description of the design of the system, and inputting the functional description to the ECAD system; (c) verifying in the high-level language, correctness of intended functionality and, if necessary, iteratively simulating and changing the functional description of the system until the desired functionality is obtained; (d) on the ECAD system, partitioning the functional description into a number of architectural blocks, taking into account low level timing parameters of a physical implementation of the device; (e) on the ECAD system, constraining the architectural choices for the design to those which meet the desired behavior; (f) on the ECAD system, mapping the architecturally constrained design into a structural description of the system; (g) on the ECAD system, creating a matrix of milestones, the matrix having columns representing levels of design abstraction and rows representing stages of design development; (h) providing at least one activity associated with each milestone, wherein completion of the at least one activity associated with a corresponding milestone indicates completion of the corresponding milestone; and (i) upon completion of a milestone, enabling activities associated with subsequent milestones and disabling all activity associated with previous milestones. 20. In an ECAD system, a method of creating and validating a structural description of a device from a behavior-oriented description, comprising:specifying a behavioral description for a desired behavior of a device in a high-level, behavior-oriented language, and inputting the behavioral description to an ECAD system; on the ECAD system, iteratively simulating and changing the behavioral description until the desired behavior is obtained; on the ECAD system, partitioning the behavioral description into architectural blocks, taking into account low level timing parameters of a physical implementation of the device; on the ECAD system, synthesizing a structural description of the architectural blocks in a lower-level language; on the ECAD system, simulating the functionality of the structural description; creating a matrix of milestones, the matrix having columns representing levels of design abstraction and rows representing stages of design development; providing at least one activity associated with each milestone, wherein completion of the at least one activity associated with a corresponding milestone indicates completion of the corresponding milestone; and upon completion of a milestone, enabling activities associated with subsequent milestones and disabling all activity associated with previous milestones. 21. In an ECAD system, a method of partitioning the design of a digital device, comprising:inputting a design to an ECAD system, and on the ECAD system performing the following steps: partitioning a design into functional blocks; generally laying out the partitioned design; selecting existing designs for a portion of the functional blocks; generating another portion of the functional blocks; partitioning yet another portion of the functional blocks into smaller functional units; synthesizing the remaining portion of the functional blocks; generating a structural description of the functional blocks and units; predicting delays between functional blocks and units; estimating low level timing parameters of a physical implementation of the device; creating a matrix of milestones, the matrix having columns representing levels of design abstraction and rows representing stages of design development; providing at least one activity associated with each milestone, wherein completion of the at least one activity associated with a corresponding milestone indicates completion of the corresponding milestone; and upon completion of a milestone, enabling activities associated with subsequent milestones and disabling all activity associated with previous milestones. 22. In an ECAD system, a method of creating and validating a structural description of a circuit or device from a higher level, behavior-oriented description thereof, comprising:(1) creating a matrix of milestones, the matrix having columns representing levels of design abstraction and rows representing stages of design development; (2) providing at least one activity associated with each milestone, wherein completion of the at least one activity associated with a corresponding milestone indicates completion of the corresponding milestone; (3) upon completion of a milestone, enabling activities associated with subsequent milestones and disabling all activity associated with previous milestones; (4) entering on an ECAD system a specification for an entire design of desired behavior of a device, including high-level timing goals, in a high-level, behavior-oriented language; (5) on the ECAD system, deriving a functional description from the specification, including intended functionality; (6) on the ECAD system, verifying the correctness of the intended functionality of the functional description; (7) on the ECAD system, partitioning the functional description into a partitioned design having separate modules, taking into account low-level timing parameters of a physical implementation of the device; (8) on the ECAD system, describing the modules, and imposing on each module a set of timing and area constraints; (9) on the ECAD system, reconstructing the partitioned design, and examining and verifying the partitioned design, to provide an RTL description of the entire design; (10) on the ECAD system, verifying architectural decisions that were made during partitioning, and examining their impact on the functionality and performance of the entire design; (11) on the ECAD system, providing a target technology library for the modules; (12) on the ECAD system, mapping the design is mapped into the target technology; (13) on the ECAD system, providing a gate-level, technology-dependent structural descriptions of the modules; (14) on the ECAD system, verify the correctness of the structural descriptions of the modules against their intended functionality; (15) on the ECAD system, associating specified timing and area constraints on the structural description of the modules; (16) on the ECAD system, modifying the structural descriptions of the modules so that their area and timing characteristics comply with the specified constraints; (17) on the ECAD system, deriving optimized structural description of the modules from the modified structural descriptions; (18) on the ECAD system, examining the impact of the optimized structural descriptions of the modules on the entire design; (19) on the ECAD system, deriving a high level module, from the optimized structural descriptions of the modules, wherein the high level module describes the interaction and connectivity between the modules, and creating higher level modules hierarchically from high level modules until the entire design is described in a highest level module; (20) on the ECAD system, composing the optimized structural descriptions of the modules are composed (see step 5) together to implement the intended functionality of the highest level module; (21) in the ECAD system, performing floor-planning for the modules, and determining more accurate intra-block and inter-block delays; (22) in the ECAD system, back-annotating the delays into the structural descriptions of the modules; and (23) in the ECAD system, further modifying the structural descriptions of the modules so that their area and timing characteristics comply with global constraints. 23. An ECAD system for creating and validating a structural description of a circuit or device from a higher level, behavior-oriented description thereof, comprising:means for entering on an ECAD system a specification for a design of desired behavior of a device, including high-level timing goals, in a high-level, behavior-oriented language; means, in the ECAD system, for iteratively simulating and changing the design of the device at the behavioral-level until the desired behavior is obtained; means, in the ECAD system, for partitioning the design of the device into a number of architectural blocks and for constraining the architectural choices to those which meet the high-level timing goals, taking into account low level timing parameters of a physical implementation of the device; means, in the ECAD system, for directing the various architectural blocks to logic synthesis programs, said logic synthesis programs also running in the ECAD system, thereby providing a netlist or gate-level description of the design; a user-interface operating on the ECAD system; a milestone matrix incorporated into the user-interface, the milestone matrix having a plurality of matrix elements representing a plurality of milestones to be completed by a user during the synthesis of the electronic design; at least one activity associated with each milestone; transition conditions, incorporated in the ECAD system and associated with the milestone matrix and operable to enable the user to perform the at least one activity for each milestone and to progress to performing the at least one activity associated with the next of the at least one milestones; wherein: completion of the at least one activity associated with a particular milestone indicates completion of the associated milestone; and the transition conditions are established to ensure that the milestones are completed by the user in a progressive order, and that activity for a previous milestone is disabled once a milestone is completed. Description
This is a continuation-in-part of U.S. patent application No. 08/077,294, filed Jun. 14, 1993, which is a continuation-in-part of the U.S. patent application No. 08/054,053, filed Apr. 26, 1993, which is a continuation of U.S. patent application No. 07/507,201, filed Apr. 6, 1990, by DANGELO, NAGASAMY et al. (now U.S. Pat. No. 5,222,030, issued Jun. 22, 1993).
The aforementioned U.S. patent application No. 08/077,294 is also a continuation-in-part of U.S. patent application No. 07/917,801, filed Jul. 20, 1992 (now U.S. Pat. No. 5,220,512, issued Jun. 15, 1993), which is a continuation of U.S. patent application No. 07/512,129, filed Apr. 19, 1990 (now abandoned).
The present invention provides a method and system for generating structural descriptions of complex digital devices from high-level descriptions and specifications using a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions.
Important features of the invention include capturing the users concepts, intent, specification, descriptions, constraints and trade-offs