Source: http://www.google.com/patents/US7507994?ie=ISO-8859-1
Timestamp: 2014-12-19 17:57:22
Document Index: 657836288

Matched Legal Cases: ['arts 62', 'arts 62', 'arts 62', 'arts 62', 'arts 62', 'arts 62', 'arts 22', 'arts 62', 'arts 62']

Patent US7507994 - Thin film transistor array panels for a liquid crystal display and a method ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this...http://www.google.com/patents/US7507994?utm_source=gb-gplus-sharePatent US7507994 - Thin film transistor array panels for a liquid crystal display and a method for manufacturing the sameAdvanced Patent SearchPublication numberUS7507994 B2Publication typeGrantApplication numberUS 11/625,694Publication dateMar 24, 2009Filing dateJan 22, 2007Priority dateApr 8, 1999Fee statusPaidAlso published asUS6524876, US6849873, US6887742, US7176496, US20030073267, US20030197177, US20050170592, US20070126005Publication number11625694, 625694, US 7507994 B2, US 7507994B2, US-B2-7507994, US7507994 B2, US7507994B2InventorsBum-Ki Baek, Mun-pyo Hong, Jang-Soo Kim, Sung-Wook Hao, Jong-Soo Yoon, Doug-Gyu KimOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (2), Classifications (39), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetThin film transistor array panels for a liquid crystal display and a method for manufacturing the sameUS 7507994 B2Abstract A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.
a gate line formed on a substrate including a first conductive layer and a second conductive layer on the first conductive layer;
a conductor formed on the first insulating layer, overlapping the storage electrode, and separated from the drain-electrode;
a second insulating layer formed on the data line, the drain electrode and the conductor and having a contact hole exposing the conductor; and
2. A thin film transistor array panel of claim 1, wherein the conductor is made of the same material as the data line.
3. A thin film transistor array panel of claim 1, wherein the semiconductor layer has the same layout as the corresponding data line, the drain electrode and the conductor except for a channel part of a thin film transistor.
4. A thin film transistor array panel of claim 1, wherein the data line is overlapped the pixel electrode.
5. A thin film transistor array panel of claim 1, wherein the gate line comprises a gate pad that is connected to and receives scanning signals from an external circuit.
6. A thin film transistor array panel of claim 5, wherein the gate pad comprises a single-layered structure.
7. A thin film transistor array panel of claim 5, wherein the first insulating layer has a first contact hole exposing the gate pad and the second insulating layer has a second contact hole exposing the gate pad, the first contact hole and the second contact hole have the same form in a plan view. Description
CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 11/083,612 filed on Mar. 16, 2005, now U.S. Pat. No. 7,176,496 which is a continuation of U.S. application Ser. No. 10/302,927 filed on Nov. 25, 2002 and issued as U.S. Pat. No. 6,887,742, which is a continuation of U.S. application Ser. No. 09/545,891 filed on Apr. 7, 2000 and issued as U.S. Pat. No. 6,524,876, which claims priority to Korean Patent Application Nos. 1999-12287 filed on Apr. 8, 1999, 1999-33091 filed on Aug. 12, 1999, and 1999-27550 filed on Jul. 8, 1999, the disclosures of which are incorporated herein by reference in their entirety.
A liquid crystal display (LCD) is one of the most popular flat panel displays (FPD), The liquid crystal display has two panels having electrodes for generating electric fields and a liquid crystal layer interposed therebetween.
In order to prevent the delay or distortion of signals applied to wires, materials having a low resistivity, such as aluminum or aluminum alloy, are generally used. However, because of the poor contact properties between aluminum or aluminum alloy and indium tin oxide (ITO), which is used as a transparent electrode in a pad portion of a liquid crystal display, the aluminum or aluminum alloy is removed to prevent the corrosion of aluminum and aluminum alloy and a different material is then inserted therebetween. Accordingly, the manufacturing process is complicated and production costs are increased,
FIGS. 3B, 3C, 4, and 5 are cross-sectional views taken along the line IIIB-IIIB′ of FIG. 3A.
FIGS. 23B, 24B and 25A, 26B, and 27B are the cross-sectional views taken along the lines XXIIIB-XXIIIB′, XXIVB-XXIVB′, XXVIB-XXVIB′, and XXVIIB-XXIIB′ of FIGS. 23A, 24A, 26A, and 27A, respectively.
A data wire made of conductive materials such as Mo or Mo alloy and Cr is formed or the ohmic contact layer patterns 55 and 56 and the gate insulating layer 30. The data wire has a data line 62 extending in the vertical direction in FIG. 1 and defining a pixel along with the gate line 22, a data pad 68 that is connected to an end of data line 62 and transmits image signals from an external circuit to the data line 62, a source electrode 6.5 of a thin film transistor that is connected to the data line 62 and is extended on the ohmic contact layer 55, and a drain electrode 66 of the thin film transistor that is formed on the ohmic contact layer 56 opposite the source electrode 65 with respect to the gate electrode 26 and is separated from the source electrode 65.
A passivation layer 70 is formed on the data wire parts 62, 65, 66, and 68, and the semiconductor layer 40 which is not covered by the data wire parts 62, 65, 66, and 68. The passivation layer 70 has contact holes 76 and 78 respectively exposing the drain electrode 66 and the data pad 68, and also has (along with the gate insulating layer 30) another contact hole 74 exposing the lower layer 201 of the gate pad 24 The passivation layer 70 can be made of an insulating material such as SiNx, acrylic organic material, other transparent photo-definable material, or other organic material.
At first, as shown in FIGS. 3A and 3B, a lower layer 201 of a conductive layer having good contact properties with ITO such as chromium, molybdenum, molybdenum alloy and titanium, and an upper layer 202 of a conductive layer having a low resistivity such as aluminum or aluminum alloy are deposited on a substrate 10 by such methods as sputtering to a thickness of 500 Å to 2,500 Å. Then, gate wire parts including as gate line 22 and a gate electrode 26, which have the lower layer 201 and the upper layer 202, and a gate pad 24 made only of the lower layer 201 are formed by dry or wet etching through a photolithography process using a mask.
At this time, it is desirable that the widths and the intervals of the slit and the lattice are smaller than the resolution of the exposure device. When using a partly-transparent lawyer, the mask including a plurality of thin films having different transmittance values, or a thin film having different thickness depending on positions may be used to control the amount of incident light.
The remaining photoresist layer 114 on the upper layer 202 is then removed, by ashing, the upper layer 202 is etched using the photoresist layer 112 as an etch mask to form the gate electrode 24 of only the lower layer 201, and the remaining photoresist layer is removed. Here, it is preferable that the thickness of the photoresist layer 112 is about 2,000 Å after ashing. At this time, the edge of the upper layer 202 is tapered to have a sloping angle.
Then, as shown in FIGS. 7A and 7B, a conductor layer such as chromium, aluminum, or aluminum alloy is deposited by such methods as sputtering and patterned through a photolithography process using a mask to form a data wire including a data line 62 intersecting the gate line 22, a source electrode 65 connected to the data line 62 and extended over the gate electrode 26, a drain electrode 66 separated from the source electrode 65 and opposite the source electrode 65 with respect to the gate electrode 22 and a data pad 68 connected to the end of the data line 62.
The ohmic contact layer patterns 55, 56, and 53 reduce the contact resistance between the semiconductor patterns 42 and 43 and the corresponding data wire parts 62, 63, 65, 56, and 68, and have the same layout as the data wire parts 62, 63, 65, 66, and 68. In other words, a first ohmic contact layer portion 55 under the data line part has the same shape as the data line parts 62, 68, and 65, a second ohmic contact layer portion 56 under the drain electrode part has the same shape as the drain electrode 66, and a third ohmic contact layer portion 53 under the conductor pattern 63 has the same shape as the conductor pattern 63 for the storage capacitor.
Next, as shown in FIGS. 13A and 13B, a gate insulating layer 30, a semiconductor layer 40, and an ohmic contact layer 50 are sequentially deposited to thicknesses of 1,500 Å to 5,000 Å, 500 Å to 2,000 Å, and 300 Å to 600 Å, respectively, by such methods as chemical vapor deposition (CVD). Then, a conductor layer 60, such as a metal, is deposited to a thickness of 1,500 Å to 3,000 Å by such methods as sputtering, and a photoresist layer 110 having a thickness of 1 μm to 2 μm is coated on the conductive layer 60.
Thereafter, the photoresist layer 110 is exposed to light through a second mask and developed to form photoresist patterns 112 and 114 as shown in FIGS. 14B and 14C. At this time, the first portion 114 of the photoresist pattern located between a source electrode 65 and a drain electrode 66, i.e., a thin film transistor channel part C as shown in FIG. 14C, is thinner than the second portion 112 of photoresist pattern located over the data wire portion A where a data wires 62, 63, 65, 66, and 68 will be formed, and the third portion, the remaining portion of the photoresist pattern located at portion B, is thinner than the first portion. The third portion may have a thickness determined according to an etching method. For example, the third portion has substantially zero thickness when using a wet etch, but the third portion may have a non-zero thickness when using a dry etch. At this time, the thickness ratio between the first portion 114 and the second portion 112 depends on the etch conditions that will be described liter. However, it is preferable that the thickness of the first portion 114 is equal to or less than half of that of the second portion 112, or for example, less than 4,000 Å.
As shown in FIGS. 15A and 15B, the ohmic contact layer 50 of the part B is exposed by removing the conductor layer 60 thereon. At this time, both wet and dry etch can be used, and it is preferable that the etch is performed under a condition that the conductor layer 60 is etched but the photoresist layers 112 and 114 are not etched. However, due to its etch selectivity, the dry etch method may also etch the photoresist patterns 112 and 114 In this case, the first portion 114 may be made thicker than in the wet etch case so that the conductor layer 60 is not exposed.
If the conductor layer 60 is made of Mo or MoW alloy, Al or Al alloy, or Ta, both dry or wet etch methods can be used, However, if the conductor layer 60 is made of Cr, wet etch is better because Cr is not easily removed by dry etching. CeNHO3 can be used as a wet etchant for etching a Cr conductor layer 60. The gas mixture of CF4 and HCl or the mixture of CF4 and O2 can be used for dry etching a Mo or MoW conductor layer 60. The mixture of CF4 and O2 shows similar etch rate on the photoresist layer and on the conductor layer 60.
Then, as shown in FIGS. 16A and 16B, the conductor pattern 67 is exposed by removing the first portion 114 of the channel part C, and the gate insulating layer 30 is exposed by removing the ohmic contact layer 50 and the semiconductor layer 40 of the part B shown in FIG. 11B. At the same time, the thickness of the second portion 112 over the data wire part A is reduced by etching. This step completes the semiconductor pattern 42 and 43 The reference numerals 57 and 53 respectively represent the ohmic contact layer pattern under the conductor patterns 67 and 63 for the source/drain electrodes and the storage capacitor.
After forming data wire parts 62, 63, 65, 66, and 68 by the above steps, a passivation layer 70 having the thickness of over 2,000 Å is formed by CVD of SiNx or by spin coating of organic insulator, as shown in FIG. 18A to FIG. 18C. Then, contact holes 76, 74, 78, and 72 respectively exposing the drain electrode 66, the gate pad 24., the data pad 68, and the conductor pattern 63 for the storage capacitor are formed by etching the passivation layer 70 and the gate insulating layer 30 at the same time by using a third mask.
As described above, the second embodiment is forming the data wires 62, 63, 65, 66, and 68, the ohmic contact patterns 55, 56, and 53, and the semiconductor patterns 42 and 43, by using one mask. Furthermore, by separating the source electrode 65 and the drain electrode 66 in this process, the second embodiment can achieve the structure of the first embodiment in a much simpler process.
A gate insulating layer pattern 30 of silicon-nitride (SiNx) is formed on the gate wise parts 22, 24, 26, and the redundant data line 25. The gate insulating layer pattern 30 has contact holes 34 and 32 exposing the gate pad 24 and the redundant data line 25.
A passivation layer 70 is formed on the data wire parts 62, 65, 66, 68, the semiconductor layer 40 not covered by the data wire parts 62, 65, 66, and 68, and the first redundent gate pad 64. The passivation layer 70 has contact holes 76, 74, and 78 respectively exposing the drain electrode 66, the first redundant gate pad 64, and the data pad 68.
FIGS. 23A, 24A, 26A, and 27A are layout views of a thin film transistor array panel according to the third embodiment of the present invention showing the manufacturing steps. FIGS. 23B, 24B and 25A, 26B, and 27B are cross-sectional views taken along lines XXIIIB-XXIIIB′, XXIVB-XXIVB′, XXVIB-XXVIB′, and XXVIIB-XXVIIB′ of FIGS. 23A, 24A, 26A, and 27A, respectively. Furthermore, FIGS. 23C, 24C and 25B, 26C, and 27C are cross-sectional views taken along lines XXIIIC-XXIIIC′, XXIVC-XXIVC′, XXVIC-XXVIC′, and XXVIIC-XXVIIC′ of FIGS. 23A, 24A, 26A, and 27A, respectively. Additionally FIGS. 23D, 24D and 25C, 26D, and 27D are cross-sectional viewes taken along lines XXIIID-XXIIID′, XXIVD-XXIVD′, XXVID-XXVID′, and XXVIID-XXVIID′ of FIGS. 23A, 24A, 26A, and 27A, respectively.
Next, as shown in FIGS. 24A, and 25A to 25C, a gate insulating layer 30, a semiconductor layer 40, and an ohmic contact layer 50 are respectively deposited sequentially by such methods as chemical vapor deposition (CVD), and are sequentially patterned through a photolithography step using a second mask to form a gale insulating layer pattern having contact holes 34 and 32 exposing the gate pad 24 and the redundant data line 25. The semiconductor layer pattern 40 and an ohmic contact layer pattern 50, which both have an island-like shape, are located over the gate electrode 26. At this time, the gate insulating layer 30, the semiconductor layer 40 and the ohmic contact layer 50 must be all removed to form contact holes 32 and 34, and the semiconductor layer 40 and the ohmic contact layer 50 on the portions excluding the gate electrode 26 must be removed to form the semiconductor layer and the ohmic contact layer patterrns 40 and 50 having an island-like shape. To obtain this object, as in the above embodiment, a photoresist pattern including at least three portions having different thickness must be used as etch mask, and a mask including at least three regions having these different transmittance values must be used to form such a photoresist pattern.
First, as shown in FIGS. 24B, 24C, and 24D, a positive photoresist layer 110 having a thickness of 1 μm to 2 μm is coated on the ohmic contact layer 50, exposed to light through a second mask, and developed to form photoresist patterns 112 and 114, which have different thicknesses indicated as t1 and t2, respectively. At this time, it is preferable that the transmittances of the regions of the mask 100 corresponding to portions A, C, and B are in the ranges of 0-3%, 20-60% (more preferably 25-40%), and more than 90%. A thick reference line D represents the thickness of the photoresist patterns 112 and 114. Here, the portion B may be of substantially zero thickness, but may also have a non-zero thickness. It is preferable that the thickness of the first portion 114 and the second portion 112 are respectively in the range of 2,000-4,000 Å (more preferably 3,000-4,000 Å) and more than 1 μm. At this time, the thickness between the first portion 114 and the second portion 112 depends on the etch condition and on the etch method, which will be described later, as well as the thicknesses of the triple layers 30, 40, and 50. The transmittances of the portions A, B, and C may be different when a negative photoresist layer is used. Next, the underlying layers including the gate insulating layer 30, the ohmic contact layer 50, and the semiconductor layer 40 are etched by using the phctoresist pattern 112 and 114. Then, the gate insulating pattern 30, the semiconductor layer 40, and the ohmic contact layer 50 can be formed.
Thus, in the third embodiment, the semiconductor pattern 40 and the ohmic contact layer pattern 50 are formed along with the gate insulating layer pattern 30 in one photolithography step using a photoresist pattern including at least three portions, having different thickness. This simplifies the manufacturing steps.
However, a pixel electrode 82 of transparent conductive material such as ITO is formed on a gate insulating layer 30 of the pixel enclosed by a gate line 22 and a data line 62, and is connected to the drain electrode 66. A supporting data line 85 is formed on the data line 62 intersecting the gate line 22, and a second redundant gate pad 84 and a redundant data pad 88 are formed on the first redundant gate pad 24 and the data pad 68. The supporting data line 85 prevents the data line 62 from disconnecting due to the steps of the gate line 22 A passivation layer 70 of silicon nitride or silicon oxide is formed on the entire insulating substrate 10. The passivation layer 70 has an opening 72 exposing the greater part of the pixel electrode 82, and has openings 74 and 78 respectively exposing the second redundant gate pad 84 and the data pad 68.
Next, as shown in FIGS. 35A to 35D, an ITO layer is deposited and etched through a photolithography step using a mask to form a pixel electrode 82 connected to the drain electrode 66, and to form a second redundant gate pad 84 and a redundant date pad 88 covering the first redundant gate pad 64 and the data pad 68.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6195140 *Jul 27, 1998Feb 27, 2001Sharp Kabushiki KaishaLiquid crystal display in which at least one pixel includes both a transmissive region and a reflective regionUS6259119 *May 15, 1998Jul 10, 2001Lg. Philips Lcd Co, Ltd.Liquid crystal display and method of manufacturing the same* Cited by examinerClassifications U.S. Classification257/59, 257/40, 257/E21.414, 257/72, 257/149International ClassificationH01L27/12, H01L29/49, G02F1/1362, H01L21/336, H01L29/417, H01L21/84, H01L29/423, H01L21/77, H01L29/45, H01L29/04Cooperative ClassificationY10S438/949, G02F1/13458, H01L29/41733, G02F1/136286, G02F1/136227, H01L27/1214, H01L29/458, H01L29/66765, G02F2001/136272, H01L29/4908, H01L27/12, G02F2001/13629, G02F2001/136236, H01L29/42384, H01L27/1288European ClassificationH01L27/12T, G02F1/1345T, H01L29/49B, H01L29/417D2, H01L29/423D2B8, G02F1/1362W, H01L29/45S2, H01L29/66M6T6F15A3, H01L27/12Legal EventsDateCodeEventDescriptionSep 17, 2012ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SAMSUNG ELECTRONICS CO., LTD.;REEL/FRAME:029045/0860Owner name: SAMSUNG DISPLAY CO., LTD., KOREA, REPUBLIC OFEffective date: 20120904Aug 27, 2012FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google