Source: http://www.google.com/patents/US6861670?dq=5166694
Timestamp: 2016-02-06 16:14:59
Document Index: 19869022

Matched Legal Cases: ['application No. 10', 'application No. 10', 'application No. 11', 'application No. 11', 'application No. 11', 'application No. 7', 'application No. 7', 'application No. 9']

Patent US6861670 - Semiconductor device having multi-layer wiring - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThe object is to pattern extremely fine integrated circuits by forming fine contact holes. The dry etching method is employed to form contact holes to pattern a wiring (114), using a mask made of metallic film (112) and an organic material as an inter-layer insulating film (111) for covering switching...http://www.google.com/patents/US6861670?utm_source=gb-gplus-sharePatent US6861670 - Semiconductor device having multi-layer wiringAdvanced Patent SearchPublication numberUS6861670 B1Publication typeGrantApplication numberUS 09/535,836Publication dateMar 1, 2005Filing dateMar 28, 2000Priority dateApr 1, 1999Fee statusPaidAlso published asEP1041622A1, US20050098894, US20110254009Publication number09535836, 535836, US 6861670 B1, US 6861670B1, US-B1-6861670, US6861670 B1, US6861670B1InventorsHisashi Ohtani, Misako Nakazawa, Satoshi Murakami, Etsuko FujimotoOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (25), Non-Patent Citations (13), Referenced by (108), Classifications (32), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device having multi-layer wiring
US 6861670 B1Abstract
a first insulating film comprising an organic material formed over a conductive layer; a first metallic layer formed on said first insulating film; a second metallic layer formed on said first metallic layer; a second insulating film formed in contact with said second metallic layer, said first metallic layer and said first insulating film; and a pixel electrode formed on said second insulating film, said pixel electrode being connected to said second metallic layer at the bottom of a contact hole provided in said second insulating film, wherein said conductive layer and said second metallic layer are directly connected to each other through a contact hole provided in said first metallic layer and said first insulating film. 2. The semiconductor device according to claim 1, wherein said first metallic layer is selected from the group consisting of aluminum and a material predominantly composed of aluminum.
a first insulating film comprising an organic material formed over a thin film transistor; a first metallic layer formed on said first insulating film; a second metallic layer formed on said first metallic layer; a second insulating film formed in contact with said second metallic layer, said first metallic layer and said first insulating film; and a pixel electrode formed on said second insulating film, said pixel electrode being connected to said second metallic layer at the bottom of a contact hole provided in said second insulating film, wherein a source region or a drain region of said thin film transistor and said second metallic layer are directly connected to each other through a contact hole provided in said first metallic layer and said first insulating film. 8. The semiconductor device according to claim 7, wherein said first metallic layer is selected from the group consisting of aluminum and a material predominantly composed of aluminum.
a first insulating film comprising an organic material formed over a thin film transistor; a first conductive layer formed on said first insulating film; a second conductive layer formed on said first conductive layer; a second insulating film formed in contact with said second conductive layer, said first conductive layer and said first insulating film; and a pixel electrode formed on said second insulating film, said pixel electrode being connected to said second conductive layer at the bottom of a contact hole provided in said second insulating film, wherein a source region or a drain region and said second conductive layer are directly connected to each other through a contact hole provided in said first conductive layer and said first insulating film, wherein said second conductive layer is contact with said first insulating film inside of said contact hole. 14. The semiconductor device according to claim 13, wherein said first conductive layer is selected from the group consisting of aluminum and a material predominantly composed of aluminum.
a thin film transistor formed over a substrate, said thin film transistor having a semiconductor layer and a gate electrode adjacent to said semiconductor layer with a gate insulating film interposed therebetween; a first insulating film comprising an organic material formed over said thin film transistor; a first conductive layer formed on said first insulating film; a second conductive layer formed on said first conductive layer; a second insulating film formed in contact with said second conductive layer, said first conductive layer and said first insulating film; and a pixel electrode formed on said second insulating film, said pixel electrode being connected to said second conductive layer at the bottom of a contact hole provided in said second insulating film, wherein said second conductive layer is directly connected to said semiconductor layer through a contact hole provided in said first conductive layer and said first insulating film. 20. The semiconductor device according to claim 19, wherein said first conductive layer is selected from the group consisting of aluminum and a material predominantly composed of aluminum.
a thin film transistor formed over a substrate, said thin film transistor having a semiconductor layer and a gate electrode adjacent to said semiconductor layer with a gate insulating film interposed therebetween; a first insulating film comprising an organic material formed over said thin film transistor; a first conductive layer formed on said first insulating film; a second conductive layer formed on said first conductive layer; a second insulating film formed in contact with said second conductive layer, said first conductive layer and said first insulating film; and a pixel electrode formed on said second insulating film, said pixel electrode being connected to said second conductive layer at the bottom of a contact hole provided in said second insulating film, wherein said second conductive layer is directly connected to said semiconductor layer through a contact hole provided in said first conductive layer and said first insulating film. 26. The semiconductor device according to claim 25, wherein said first conductive layer is selected from the group consisting of aluminum and a material predominantly composed of aluminum.
a thin film transistor formed over a substrate, said thin film transistor having a semiconductor layer and a gate electrode adjacent to said semiconductor layer with a gate insulating film interposed therebetween; a first insulating film comprising an organic material formed over said thin film transistor; a first wiring formed on said first insulating film; a second wiring formed on said first wiring; a second insulating film formed in contact with said second wiring, said first wiring and said first insulating film; and a pixel electrode formed on said second insulating film, said pixel electrode being connected to said second wiring at the bottom of a contact hole provided in said second insulating film, wherein said second wiring is directly connected to said semiconductor layer through a contact hole provided in said first wiring and said first insulating film. 32. The semiconductor device according to claim 31, wherein said first wiring is selected from the group consisting of aluminum and a material predominantly composed of aluminum.
an inter-layer insulating film composed of an organic material on a conductive material layer, a first metallic layer on said inter-layer insulating film, and a second metallic layer on said first metallic film, wherein said conductive material layer and said second metallic layer are connected to each other at the bottom of a contact hole provided in said inter-layer insulating film. Furthermore, another configuration of the present invention is a semiconductor device comprising:
an inter-layer insulating film composed of an organic material on a thin film transistor, a first metallic layer on said inter-layer insulating film, and a second metallic layer on said first metallic layer, wherein the source region or the drain region of said thin film transistor and the said second metallic layer are connected to each other at the bottom of a contact hole provided in said inter-layer insulating film. It is possible to use a conductive material as the first metallic layer or the second metallic layer in the aforementioned configurations. For example, a material layer predominantly is composed of Al, Ta, Ti, Cr, W, Mo or silicon provided with conductivity, or multi-layer film comprised thereof can be used. Furthermore, the first metallic layer is preferably composed of aluminum, which has low resistance, and a material predominantly composed of aluminum.
forming a thin film transistor on an insulating surface, depositing an inter-layer insulating film composed of an inorganic material to cover said thin film transistor, depositing a first metallic film to cover said inter-layer insulating film, patterning said first metallic film to form a first metallic layer, with said first metallic layer employed as a mask, etching said inter-layer insulating film to form contact holes, depositing a second metallic film to cover said first metallic layer and said contact holes, and patterning said first metallic layer and said second metallic film to form wirings, part of the wirings having a multi-layer structure. Furthermore, another configuration of the present invention is comprised of a method for fabricating a semiconductor device which is characterized by comprising the steps of:
forming a first conductive material layer on an insulating surface, depositing an inter-layer insulating film composed of an organic material to cover said first material layer, depositing a first metallic film to cover said inter-layer insulating film, patterning said first metallic film to form a first metallic layer, with said first metallic layer employed as a mask, etching said inter-layer insulating film to form contact holes, depositing a second metallic film to cover said first metallic layer and said contact holes, depositing an inorganic film to cover said second metallic film, patterning said first metallic layer, said second metallic film, and said inorganic film to form wirings having an inorganic layer on the upper surface thereof, and forming a second conductive material layer in contact with said wirings to form a capacitor between said wirings and said second material layer with said inorganic layer as a dielectric substance. In the aforementioned configuration, said inorganic film is characterized by being deposited by a CVD method.
Next, the impurity element doped to the active layer (the X III group or the XV group element) was thermally annealed or activated by laser beam radiation. In this embodiment, the excimer laser was used for the activation of the element and thereafter the element was further thermally annealed for two hours at a temperature of 450� C.
Furthermore, an organic material film 0.5 to 3 μm in thickness was formed as the first inter-layer insulating film 111 to cover the entire surface of the substrate. As deposited method, the spin coating method using a spinner was used, and a coating with a flat surface was readily obtained. Subsequently, the film was baked by heating for one hour at a temperature of 250� C. In this embodiment, acrylic was used for depositing 1 μm in thickness. On the other hand, as a first inter-layer insulating film, it is possible to use polyimide, BCB (benzocyclobutane), or other organic material other than acrylic.
In FIG. 6(A), a substrate 601 desirably employs a quartz substrate or a silicon substrate. This embodiment employed a quartz substrate. Alternatively, such a substrate may be used as is provided with an insulating film on the surface of a metallic substrate or a stainless steel substrate. This embodiment requires the heat resistance to resist a temperature of 800� C. or more, and thus any substrate that satisfies the heat resistance may be used.
Furthermore, the amorphous silicon film, depending on the content of hydrogen, is preferably heated for about one hour at a temperature ranging from 400 through 550� C. to allow hydrogen to escape thoroughly so as to be desirably crystallized. In this case, the content of hydrogen is preferably 5 atomic % or less.
In the crystallization process, first, heat treatment is performed for about one hour at temperatures ranging from 400 through 500� C., then hydrogen is allowed to escape from inside the film, thereafter heat treatment is performed at temperatures ranging from 500 through 650� C. (preferably, from 550 through 600� C.) for 6 through 16 hours (preferably, for 8 through 14 hours).
In this embodiment, nickel is used as the catalytic element and undergoes heat treatment for 14 hours at a temperature of 570� C. This allows crystallization to proceed from the openings 604 a and 604 b in the directions (indicated by the arrows) substantially parallel to the substrate, so that semiconductor films 605 a-605 d (crystalline silicon films in this embodiment) are formed which contain crystalline structures with aligned macroscopic crystal growth directions. (FIG. 6(B)).
Next, a gettering process is performed to remove the nickel used in the crystallization process from the crystalline silicon film. In this embodiment, a process for doping an element of group XV (phosphorus in this embodiment) is performed using the mask film 603, which is previously formed, as a mask as it is in order to form phosphorus doping regions 606 a and 606 b (hereinafter referred to as gettering regions) containing phosphorus of a concentration of 1�1019-1�1020 atoms/cm3 on the crystalline silicon film exposed at the openings 604 a and 604 b. (FIG. 6(C)).
Next, a heat treatment process is performed in an atmosphere of nitrogen at temperatures ranging from 450 through 650� C. (preferably, 500 through 550� C.) for 4 through 24 hours (preferably, 6 through 12 hours). This heat treatment process causes the nickel in the crystalline silicon film to move in the directions indicated by the arrows and thus nickel is eliminated from inside the crystalline silicon film due to this gettering action. Accordingly, the concentration of nickel contained in crystalline silicon films 607 a-607 d after the gettering is reduced to 1�1017 atoms/cm3 or less, or preferably down to 1�1016 atoms/cm3.
This process forms impurity regions 610 a and 610 b containing a p-type impurity element (boron in this embodiment) of a concentration of 1�1015-1�1018 atoms/cm3 (typically, 5�1016-5�1017 atoms/cm3. Furthermore, in this specification, an impurity region containing a p-type impurity element (the region not containing phosphorus) within the aforementioned range of concentration is defined as a p-type impurity region (b). (FIG. 6(D)).
Next, the resist mask 609 is removed and then the crystalline silicon film is patterned to form island-shaped semiconductor layers (active layers) 611-614. Furthermore, the active layers 611-614, crystallized by selective doping of nickel, are made of a crystalline silicon film with very good crystallinity. More specifically, the layers have a crystalline structure in which bar-shaped or pillar-shaped crystals are arranged with a specific directivity. In addition, after crystallization, nickel has been removed or reduced due to the gettering action of phosphorus, the concentration of the catalytic element remaining in the active layers 611-614 being 1�1017 atoms/cm3 or less, or preferably 1�1016 atoms/cm3. (FIG. 6(E)).
Next, a heat treatment process is performed at temperatures within the range of 800 through 1150� C. (preferably, from 900 through 1000� C.) for 15 minutes to 8 hours (preferably, for 30 minutes through 2 hours) under an oxidizing atmosphere (the thermal oxidation process). In this embodiment, a heat treatment process is performed for 80 minutes at a temperature of 950� C. in an oxygen atmosphere mixed with 3 vol % hydrogen chloride. Furthermore, the boron doped in the process shown in FIG. 6(D) is activated during this thermal oxidation process. (FIG. 7(A)).
The impurity regions 620-622 will function as an LDD region in an n-channel type TFT of a CMOS circuit or sampling circuit later. Furthermore, the impurity regions formed here include an n-type impurity element in a concentration of 2�106-5�1019 atoms/cm3 (typically, 5�107-5�1018 atoms/cm3). In this specification, an impurity region containing an n-type impurity element within the aforementioned range of concentration is defined as an n-type impurity region (b).
Furthermore, here, the ion doping method is employed to dope phosphorus of a concentration of 1�1018 atoms/cm3, where phosphine (PH3) is excited in the state of plasma without mass separation. As a matter of course, the ion implantation method may also be employed in which mass separation is carried out. In this process, phosphorus is doped into the crystalline silicon film via the gate film 615.
Next, a heat treatment process is performed in an inactive atmosphere at temperatures within the range of 600 through 1000� C. (preferably, 700 through 800� C.) to activate the phosphorus doped in the process shown in FIG. 7(B). In this embodiment, the heat treatment is carried out in a nitrogen atmosphere at a temperature of 800� C. for one hour. (FIG. 7(C)).
Next, a resist mask 629 is formed and a p-type impurity element (boron in this embodiment) is doped to form impurity regions 630 and 631 containing boron in a high concentration. In this embodiment, boron is doped in a concentration of 3�1020-3�1021 atoms/cm3 (typically, 5�1020-1�1021 atoms/cm3) by means of the ion doping method (as a matter of course, the ion implantation may be used) using diborane (B2H6). Furthermore, in this specification, an impurity region containing a p-type impurity element within the range of the aforementioned concentration is defined as a p-type impurity region (a). (FIG. 8 (A)).
Next, the resist mask 629 is removed and then resist masks 632-634 are formed to cover the regions that are to be gate wirings and p-channel type TFTs. Then, an n-type impurity element (phosphorus in this embodiment) is doped to form impurity regions 635-641, which contain a high concentration of phosphorus. Here, the ion doping method (as a matter of course, the ion implantation method may be employed) is also employed using phosphine (PH3), with the concentration of phosphorus in this region being 1�1020-1�1021 atoms/cm3 (typically, 2�1020-5�1021 atoms/cm3). (FIG. 8(B)).
Next, an n-type impurity element (phosphorus in this embodiment) is doped in a self-aligning manner with the gate wirings 625-628 employed as a mask. An adjustment is made so that the resulting impurity regions 643-646 are doped with the concentration (5 through 10 times the concentration of the boron doped in the aforementioned channel doping process, generally 1�1016-5�1018 atoms/cm3, typically 3�1017-3�1018 atoms/cm3) of phosphorus � through {fraction (1/10)} (typically, ⅓ through �) that of said n-type impurity regions (b). Furthermore, in this specification, an impurity region containing an n-type impurity element within the range of the aforementioned concentration (however, excluding a p-type impurity region (a)) is defined as an n-type impurity region (c). (FIG. 8(C)).
Furthermore, in this process, phosphorus is doped into all impurity regions except the portions covered with the gate wirings in the concentration of 1�1016-5�1018 atoms/cm3. However, since the concentration is very low, the function of each impurity region will not be given an adverse effect. In addition, the n-type impurity regions (b) 643-646 have already been doped with boron in the concentration of 1�1015-1�1018 atoms/cm3 in the channel doping process. However, in this process, since phosphorus is doped in a concentration 5 through 10 times that of the boron contained in the p-type impurity regions (b), it may be safely considered that boron will give no adverse effect on the function of the n-type impurity regions (b) in this case as well.
Thereafter, a heat treatment process was carried out to activate the n-type or p-type impurity element doped in respective concentrations. This process can be performed using the furnace annealing method, the laser annealing method, or the lamp annealing method, or by a combination. In the case of the furnace annealing method, it may be carried out in an inactive atmosphere at temperatures ranging from 500 through 800� C., preferably, at temperatures ranging from 550 through 600� C. In this embodiment, the impurity element was activated by heat treatment at a temperature of 600� C. for four hours. (FIG. 8 (D)).
Next, after the activation process, heat treatment is carried out at temperatures ranging from 300 through 450� C. for 1 through 4 hours in an atmosphere containing 3 through 100% hydrogen in order to hydrogenate the active layers. This process is to terminate dangling bonds of semiconductor layers by means of hydrogen thermally excited. As an alternative means for hydrogenation, plasma hydrogenation may be carried out (using hydrogen excited by plasma).
In addition, the hydrogenation process may be further carried out thereafter. For example, heat treatment may be carried out in an atmosphere containing 3-100% hydrogen at temperatures within the range of 300 through 450� C. for 1 through 12 hours. Alternatively, the same effect can be obtained using the plasma hydrogenation method.
Thereafter, a second inter-layer insulating film 659 composed of an organic resin is formed in a thickness of about 1 μm. It is also possible to use an organic resin film such as polyimide, acrylics, polyamide, polyimide-amide, or BCB (benzocyclobutane) as the organic resin. The advantages of using an organic resin film are that the deposition method is simple, the specific dielectric constant is low, whereby the parasitic capacitance can be reduced, and the organic resin film provides outstanding flatness. Furthermore, organic resin films other than those mentioned above or an organic-based SiO compound can be used. Here, a thermally polymerized polyimide was formed by being applied on a substrate and baked at a temperature of 300� C.
FIG. 12 is a circuit diagram of an active matrix EL display device. Reference number 81 denotes a pixel circuit around which there are provided an X-direction drive circuit 82 and a Y-direction drive circuit 83. Each pixel of the pixel circuit 81 has a switching TFT 84, a condenser 85, a current control TFT 86, and an organic EL element 87. An X-direction signal line 88 a (or 88 b) and Y-direction signal line 89 a (or 89 b or 89 c) are connected to the switching TFT 84. In addition, the current control TFT 86 is connected with supply lines 90 a and 90 b. In the active matrix EL display device of the present embodiment, the TFT that is used for the X-direction drive circuit 82, Y-direction drive circuit 83, and current control TFT 86 is formed by the combination of the p-channel type TFT 301 and the n-channel type TFT 302 or 303, shown in FIG. 9(B). Moreover, the TFT for the switching TFT 84 is formed by the n-channel type TFT 804 of FIG. 9(B).
In particular, some of threshold-less anti-ferroelectric LC (abbreviated as TL-AFLC) having an opto-electric response characteristic in that the transmittance varies successively to an electric field were found to show a V-shaped (or a U-shaped) opto-electric response characteristic with the drive voltage being about �2.5V (1 through 2 μm in thickness of a cell). Accordingly, in some cases, the source voltage for the pixel circuit may be only 5 through 8V, indicating the possibility of operating the drive circuit and pixel circuit with the same source voltage. That is, the power consumption of the entire liquid-crystal display device can be reduced.
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H01L29/458European ClassificationH01L21/768C, H01L27/12T, H01L21/768C6, H01L21/768B2, G02F1/1362H, H01L29/786B6Legal EventsDateCodeEventDescriptionJul 31, 2000ASAssignmentOwner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OHTANI, HISASHI;NAKAZAWA, MISAKO;MURAKAMI, SATOSHI;AND OTHERS;REEL/FRAME:010963/0239;SIGNING DATES FROM 20000704 TO 20000717Aug 27, 2008FPAYFee paymentYear of fee payment: 4Aug 1, 2012FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services