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Patente US6239459 - Capacitors, methods of forming capacitors and integrated circuitry - Google PatentesB�squeda Im�genes Maps Play YouTube Noticias Gmail Drive M�s »Iniciar sesi�n B�squeda avanzada de patentesPatentesIn accordance with one implementation the invention, a capacitor comprises two conductive capacitor electrodes separated by a capacitor dielectric layer, with at least one of the capacitor electrodes comprising at least one of Pt and Pd, and also comprising another metal which is capable of forming a...http://www.google.es/patents/US6239459?utm_source=gb-gplus-sharePatente US6239459 - Capacitors, methods of forming capacitors and integrated circuitry B�squeda avanzada de patentes N�mero de publicaci�nUS6239459 B1Tipo de publicaci�nConcesi�n N�mero de solicitudUS 09/393,078 Fecha de publicaci�n29 May 2001 Fecha de presentaci�n7 Sep 1999 Fecha de prioridad21 May 1998TarifaPagadasTambi�n publicado comoUS6255186 N�mero de publicaci�n09393078, 393078, US 6239459 B1, US 6239459B1, US-B1-6239459, US6239459 B1, US6239459B1 InventoresHusam N. Al-Shareef, Scott Jeffery DeBoer, Randhir P. S. Thakur Cesionario originalMicron Technology, Inc.Exportar citaBiBTeX, EndNote, RefManCitas de patentes (60), Otras citas (27), Citada por (4), Clasificaciones (12), Eventos legales (3) Enlaces externos: USPTO, Cesi�n de USPTO, EspacenetCapacitors, methods of forming capacitors and integrated circuitry
US 6239459 B1 Resumen
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Inc.Capacitor, and methods for forming a capacitorUS584477115 Ago 19971 Dic 1998Micron Technology, Inc.Capacitor constructionUS58997404 Sep 19974 May 1999Samsung Electronics Co., Ltd.Methods of fabricating copper interconnects for integrated circuitsUS591021812 Sep 19968 Jun 1999Samsung Electronics Co., Ltd.Systems for forming films having high dielectric constantsUS59166341 Oct 199629 Jun 1999Sandia CorporationChemical vapor deposition of W-Si-N and W-B-NUS593058430 Abr 199627 Jul 1999United Microelectronics Corp.Process for fabricating low leakage current electrode for LPCVD titanium oxide filmsUS5990507 *9 Jul 199723 Nov 1999Kabushiki Kaisha ToshibaSemiconductor device having ferroelectric capacitor structuresUS601074423 Dic 19974 Ene 2000Advanced Technology Materials, Inc.Method for nucleation controlled chemical vapor deposition of metal oxide ferroelectric thin filmsUS6015989 *20 Dic 199618 Ene 2000Mitsubishi Denki Kabushiki KaishaSemiconductor device having a capacitor electrode formed of iridum or ruthenium and a quantity of oxygenUS6027969 *4 Jun 199822 Feb 2000Taiwan Semiconductor Manufacturing CompanyCapacitor structure for a dynamic random access memory cellUS6028360 *29 Jun 199822 Feb 2000Hitachi, Ltd.Semiconductor integrated circuit device in which a conductive film is formed over a trap film which in turn is formed over a titanium filmUS6051859 *16 Ene 199818 Abr 2000Kabushiki Kaisha ToshibaDRAM having a cup-shaped storage node electrode recessed within an insulating layerJP40534364A T�tulo no disponibleJPH0621333A T�tulo no disponibleJPH01222469A T�tulo no disponibleJPH05221644A T�tulo no disponible* Citada por examinadorOtras citasReferencia1Eimori, T., et al. "Newly Designed Planar Stacked Capacitor Cell with High Dielectric Constant Film for 256Mbit DRAM" I.E.E.E., IEDM 93-631-4, pp. 631-4 (1993).2Farooq, M.A., et al., "Tantalum Nitride as a Diffusion Barrier Between Pd2Si, CoSi2 and Aluminum", 1989 American Institute of Physics, pp. 3017-3022.3Fazan, P.C., et al., "A High-C Capacitor (20.4fF/mum2) with Ultrathin CVD-Ta2O5 Films Deposited on Rugged Poly-Si for High Density DRAMs", I.E.E.E., pp. 263-266 (1992).4Fazan, P.C., et al., "A High-C Capacitor (20.4fF/μm2) with Ultrathin CVD-Ta2O5 Films Deposited on Rugged Poly-Si for High Density DRAMs", I.E.E.E., pp. 263-266 (1992).5Kamiyama, S., et. al., "Highly Reliable 2.5nm Ta2O5 Capacitor Process Technology for 256Mbit DRAMs", I.E.E.E., pp. 827-830 (1991).6Kamiyama, S., et. al., "Ultrathin Tantalum Oxide Capacitor Dielectric Layers Fabricated Using Rapid Thermal Nitridation Prior to Low Pressure Chemical Vapor Deposition", J. Electrochem. Soc., vol. 140, No. 6, pp. 1617-1625 (Jun. 1993).7Lesaicherre, P-Y, et. al., "A Gbit-Scale DRAM Stacked Capacitor Technology with ECR MOCVD SrTiO3 and RIE Patterned RuO2/TiN Storage Nodes", I.E.E.E., pp. 831-834 (1994).8McIntyre, Paul C. et al., "Kinetics And Mechanisms Of TiN Oxidation Beneath Pt/TiN Films", J. Appl. Phys., vol. 82, No. 9, pp. 4577-4585 (Nov. 1997).9Onishi, Shigeo et al., "A Half-Micron Ferroelectric Memory Cell Technology With Stacked Capacitor Structure", I.E.E.E., IDEM 94-843, pp. 843-6 (1994).10U.S. application No. 08/738,789, Sandhu et al., filed Oct. 29, 1996.11U.S. application No. 08/858,027, Sandhu et al., filed May 16, 1997.12U.S. application No. 08/881,561, Sandhu et al., filed Jun. 24, 1997.13U.S. application No. 08/916,771, DeBoer et al., filed Aug. 20, 1997.14U.S. application No. 08/994,054, Parekh et al., filed Dec. 19, 1997.15U.S. application No. 09/033,063, Al-Shareef et al., filed Feb. 28, 1998.16U.S. application No. 09/033,064, Al-Shareef et al., filed Feb. 28,1998.17U.S. application No. 09/058,612, Agarwal et al., filed Apr. 10, 1998.18U.S. application No. 09/059,057, Agarwal et al., filed Apr. 10, 1998.19U.S. application No. 09/074,638, Agarwal et al., filed May 7, 1998.20U.S. application No. 09/086,389, Sandhu et al., filed May 28, 1998.21U.S. application No. 09/098,035, DeBoer et al., filed Jun. 15, 1998.22U.S. application No. 09/122,473, Schuegraf, filed Jul. 23, 1998.23U.S. application No. 09/137,780, Al-Shareef et al., filed Aug. 20, 1998.24U.S. application No. 09/185,412, Graettinger et al., filed Nov. 3, 1998.25U.S. application No. 09/229,518, DeBoer et al., filed Jan. 13, 1999.26Wolf, S., and Tauber, R.N., Silicon Processing for the VLSI Era, vol. 2, Lattice press, pp. 589-591.27Yamaguchi, H., et al., "Structural and Electrical Characterization of SrTiO3 Thin Films Prepared by Metal Organic Chemical Vapor Deposition", Jpn. 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Citada por Patente citante Fecha de presentaci�n Fecha de publicaci�n Solicitante T�tuloUS6518670 *6 Mar 200211 Feb 2003International Business Machines CorporationElectrically porous on-chip decoupling/shielding layerUS6535413 *31 Ago 200018 Mar 2003Micron Technology, Inc.Method of selectively forming local interconnects using design rulesUS693090117 Sep 200216 Ago 2005Micron Technology, Inc.Method of selectively forming local interconnects using design rulesUS7525140 *14 Dic 200528 Abr 2009Intel CorporationIntegrated thin film capacitors with adhesion holes for the improvement of adhesion strength* Citada por examinadorClasificaciones Clasificaci�n de EE.UU.257/296, 257/306, 257/295, 257/E21.011, 257/E21.009, 257/E21.648 Clasificaci�n internacionalH01L21/8242, H01L21/02 Clasificaci�n cooperativaH01L28/55, H01L28/60, H01L27/10852 Clasificaci�n europeaH01L28/60Eventos legales FechaC�digoEventoDescripci�n22 Sep 2004FPAYFee paymentYear of fee payment: 430 Oct 2008FPAYFee paymentYear of fee payment: 828 Sep 2012FPAYFee paymentYear of fee payment: 12GirarImagen originalP�gina principal de Google - Sitemap - Descargas masivas de USPTO - Pol�tica de privacidad - Condiciones de servicio - Acerca de Google Patentes - Enviar sugerenciasDatos proporcionados por IFI CLAIMS Patent Services