Source: http://www.google.com/patents/US7642598?dq=7,194,691
Timestamp: 2015-01-31 00:24:04
Document Index: 622726995

Matched Legal Cases: ['Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 2007', 'Application No. 2009', 'Application No. 2009']

Patent US7642598 - Method of fabricating a semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate,...http://www.google.com/patents/US7642598?utm_source=gb-gplus-sharePatent US7642598 - Method of fabricating a semiconductor deviceAdvanced Patent SearchPublication numberUS7642598 B2Publication typeGrantApplication numberUS 11/926,552Publication dateJan 5, 2010Filing dateOct 29, 2007Priority dateSep 4, 1998Fee statusPaidAlso published asUS6335231, US6803264, US7473592, US7473971, US7476576, US7638805, US8405090, US20020137265, US20050009252, US20070184632, US20080054269, US20080067596, US20080070335, US20080113487, US20080113488, US20090236698, USRE42097, USRE42139, USRE42241Publication number11926552, 926552, US 7642598 B2, US 7642598B2, US-B2-7642598, US7642598 B2, US7642598B2InventorsShunpei Yamazaki, Hisashi OhtaniOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (31), Referenced by (8), Classifications (28), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod of fabricating a semiconductor deviceUS 7642598 B2Abstract A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
an island-like single crystalline semiconductor layer comprising silicon formed by removing portions of a single crystal silicon layer on an insulating layer comprising silicon oxide over a silicon substrate, the island-like single crystalline semiconductor layer having at least a channel formation region and source and drain regions;
a gate wiring line formed over the channel formation region with the gate insulating film interposed therebetween, wherein the gate wiring line includes a metal layer which contacts the gate insulating film;
etching stoppers formed on side surfaces of the gate wiring line;
side walls comprising silicon nitride formed adjacent to the side surfaces of the gate wiring line with the etching stoppers interposed therebetween, wherein silicon oxide is interposed between the island-like single crystalline semiconductor layer and the side walls; and
an insulating film comprising silicon nitride formed over the island-like single crystalline semiconductor layer and the gate wiring line,
wherein the island-like single crystalline semiconductor layer is 20 to 100 nm thick.
2. The electronic equipment according to claim 1 wherein the source and drain regions are in contact with the insulating layer.
3. The electronic equipment according to claim 1 further comprising a first LDD region between the channel formation region and the drain region and a second LDD region between the channel formation region and the source region, wherein the first and second LDD regions are in contact with the insulating layer.
a gate wiring line comprising polysilicon formed over the channel formation region with the gate insulating film interposed therebetween;
silicon oxide films formed on side surfaces of the gate wiring line;
side walls comprising silicon nitride formed adjacent to the side surfaces of the gate wiring line with the silicon oxide films interposed therebetween, wherein silicon oxide is interposed between the island-like single crystalline semiconductor layer and the side walls; and
wherein an upper surface of the gate wiring line and at least a part of the source and drain regions comprise a metal silicide, and
5. The electronic equipment according to claim 4 wherein the electronic equipment is a portable information terminal.
6. The electronic equipment according to claim 4 wherein the electronic equipment is a portable computer.
7. The electronic equipment according to claim 4 wherein the electronic equipment is a cellular phone.
8. The electronic equipment according to claim 4 wherein the metal silicide is cobalt silicide.
9. The electronic equipment according to claim 4 wherein the island-like single crystalline semiconductor layer is hydrogenated.
10. The electronic equipment according to claim 4 wherein the source and drain regions are in contact with the insulating layer.
an insulating film comprising silicon nitride oxide formed over the island-like single crystalline semiconductor layer and the gate wiring line,
a gate wiring line comprising poly silicon formed over the channel formation region with the gate insulating film interposed therebetween;
a gate wiring line formed over the channel formation region with the gate insulating film interposed therebetween;
side walls comprising silicon nitride formed adjacent to the side surfaces of the gate wiring line with the silicon oxide films interposed therebetween;
a first insulating film comprising silicon nitride formed over the island-like single crystalline semiconductor layer and the gate wiring line;
a second insulating film formed over the first insulating film wherein the second insulating film is a flattening film;
a wiring line formed over the second insulating film and electrically connected to one of the source and drain regions; and
a third insulating film formed over the second wiring line and the second insulating film wherein the third insulating film is a flattening film,
14. The electronic equipment according to claim 13 wherein the gate wiring line includes a metal layer which contacts the gate insulating film.
15. The electronic equipment according to claim 14 wherein the gate wiring line comprises tantalum or a tantalum nitride.
16. The electronic equipment according to claim 13 wherein the first insulating film comprises silicon nitride.
17. The electronic equipment according to claim 13 wherein the second and third flattening insulating films comprise a resin.
18. The electronic equipment according to claim 13 wherein an upper surface of the gate wiring line and at least a part of the source and drain regions comprise a metal silicide.
19. The electronic equipment according to claim 18 wherein the metal silicide is cobalt silicide.
20. The electronic equipment according to claim 13 wherein the electronic equipment is a portable computer.
21. The electronic equipment according to claim 13 wherein the electronic equipment is a cellular phone.
22. An electronic equipment comprising:
a CMOS circuit including an N-channel transistor and a P-channel transistor, each of the N-channel transistor and the P-channel transistor comprising:
an island-like single crystalline semiconductor layer comprising silicon formed by removing portions of a single crystal silicon layer on an insulating layer comprising silicon oxide over a silicon substrate, the island-like single crystalline semiconductor layer including at least a channel formation region, a source region and a drain region,
a gate insulating film formed on the channel formation region,
a gate wiring line formed over the channel formation region with the gate insulating film interposed therebetween,
silicon oxide films formed on side surfaces of the gate wiring line, and
an interlayer insulating film comprising silicon nitride formed over the island-like single crystalline semiconductor layer and the gate wiring line,
wherein the island-like single crystalline semiconductor layer of the N-channel transistor and the island-like single crystalline semiconductor layer of the P-channel transistor are separately located, and
wherein the island-like single crystalline semiconductor layer of the N-channel transistor and the island-like single crystalline semiconductor layer of the P-channel transistor are 20 to 100 nm thick.
an island-like single crystalline semiconductor layer comprising silicon formed by removing portions of a single crystal silicon layer on an insulating layer comprising silicon oxide over a silicon substrate, the island-like single crystalline semiconductor layer including at least two channel formation regions, a source region and a drain region,
a gate insulating film formed on the two channel formation regions,
at least two gate wiring lines formed over the two channel formation regions with the gate insulating film interposed therebetween,
silicon oxide films formed on side surfaces of the two gate wiring lines, and
side walls comprising silicon nitride formed adjacent to the side surfaces of the two gate wiring lines with the silicon oxide films therebetween, wherein silicon oxide is interposed between the island-like single crystalline semiconductor layer and the side walls; and
an interlayer insulating film comprising silicon nitride formed over the island-like single crystalline semiconductor layer and the two gate wiring lines,
24. An electronic equipment comprising:
an island-like single crystalline semiconductor layer comprising silicon formed by removing portions of a single crystal silicon layer on an insulating layer comprising silicon oxide over a silicon substrate, the island-like single crystalline semiconductor layer including at least a channel formation region, a source region and a drain region, wherein upper surfaces of the source region and the drain region comprise a metal silicide,
a gate wiring line formed over the channel formation region with the gate insulating film interposed therebetween, wherein the gate wiring line comprises polysilicon and an upper surface of the gate wiring line comprises a metal silicide,
an interlayer insulating film comprising silicon nitride in contact with at least the metal silicide of the gate wiring line and the side walls,
an island-like single crystalline semiconductor layer comprising silicon formed by removing portions of a single crystal silicon layer on an insulating layer comprising silicon oxide over a silicon substrate, the island-like single crystalline semiconductor layer including at least two channel formation regions, a source region and a drain region wherein upper surfaces of the source region and the drain region comprise a metal silicide,
at least two gate wiring lines formed over the two channel formation regions with the gate insulating film interposed therebetween, wherein each of the two gate wiring lines comprises polysilicon and upper surfaces of the two gate wiring lines comprise a metal silicide,
side walls comprising silicon nitride formed adjacent to the side surfaces of the two gate wiring lines with the silicon oxide films therebetween wherein silicon oxide is interposed between the island-like single crystalline semiconductor layer and the side walls; and
an interlayer insulating film comprising silicon nitride in contact with at least the metal suicide of the two gate wiring lines and the side walls,
26. An electronic equipment comprising:
side walls comprising silicon nitride formed adjacent to the side surfaces of the gate wiring line with the silicon oxide films interposed therebetween, wherein silicon oxide is interposed between the island-like single crystalline semiconductor layer and the side walls;
an interlayer insulating film comprising silicon nitride formed over the N-channel transistor and the P-channel transistor;
a first wiring line formed over the interlayer insulating film, wherein the first wiring line is in contact with one of the source region and the drain region of the N-channel transistor through a contact hole of the interlayer insulating film; and
a second wiring line formed over the interlayer insulating film wherein the second wiring line is in contact with one of the source region and the drain region of the P-channel transistor through a contact hole of the interlayer insulating film,
an island-like single crystalline semiconductor layer comprising silicon formed on an insulating layer comprising silicon oxide over a silicon substrate, the island-like single crystalline semiconductor layer including at least two channel formation regions, a source region and a drain region wherein upper surfaces of the source region and the drain region comprise a metal silicide,
a gate insulating film formed on the island-like single crystalline semiconductor layer,
side walls comprising silicon nitride formed adjacent to the side surfaces of the two gate wiring lines with the silicon oxide films therebetween wherein silicon oxide is interposed between the island-like single crystalline semiconductor layer and the side walls;
an interlayer insulating film comprising silicon nitride formed over the transistor; and
a wiring line formed over the interlayer insulating film and being in contact with one of the source region and the drain region through a contact hole of the interlayer insulating film,
28. The electronic equipment according to any one of claims 1, 4, 11, 12, 13 and 22-27 wherein the island-like single crystalline semiconductor layer has a main surface of a {110} plane.
29. The electronic equipment according to any one of claims 1, 11, 12, 13 and 22-27 wherein the island-like single crystalline semiconductor layer is hydrogenated.
30. The electronic equipment according to any one of claims 1, 4, 11, 12, 13 and 22-27 wherein the electronic equipment is an information terminal.
31. The electronic equipment according to any one of claims 1, 4, 11, 12, 13 and 22-27 wherein the electronic equipment is a TV.
32. The electronic equipment according to any one of claims 1, 4, 11, 12, 13 and 22-27 wherein the island-like single crystalline semiconductor layer contains oxygen and a concentration of the oxygen is less than 2�1018 atoms/cm3.
33. The electronic equipment according to any one of claims 1, 4, 11, 12, 13, 22-27 wherein the insulating layer comprising silicon oxide includes a first silicon oxide layer and a second silicon oxide layer, the first silicon oxide layer being in contact with the silicon substrate and the second silicon oxide layer being in contact with the island-like single crystalline semiconductor layer.
34. The electronic equipment according to any one of claims 1, 4, 11, 12, 13 and 22-27 wherein the single crystalline semiconductor layer comprises part of a single crystalline silicon substrate different from the silicon substrate.
This application is a continuation of copending U.S. application Ser. No. 11/731,415, filed on Mar. 30, 2007 which is a continuation of U.S. application Ser. No. 10/9 14,357, filed on Aug. 9, 2004 which is a continuation of U.S. application Ser. No. 09/808,162, filed on Mar. 13, 2001 (now U.S. Pat. No. 6,803,264 issued Oct. 12, 2004) which is a divisional of U.S. application Ser. No. 09/386,782, filed on Aug. 31, 1999 (now U.S. Pat. No. 6,335,231 issued Jan. 1, 2002).
Further, as a great merit of using the single crystal silicon layer having the main surface of the {110} plane, it is possible to mention that a silicon surface is very flat. In the case where the main surface is the {110} plane, a cleavage plane appears lamellary, and it is possible to form a surface with very few asperities.
This technique is a well-known silicide technique. Thus, it does not matter if titanium or tungsten is used instead of cobalt, and a heat treatment condition and the like may be referred to the well-known technique. In this embodiment, the heat treatment step is carried out by using lamp annealing.
Further, although the description in this embodiment has been made on the liquid crystal display device as an example, it is needless to say that the present invention can be applied to an EL (electroluminescence) display device or an EC (electrochromic) display device as long as the display device is an active matrix type display device. Here, an example of a circuit constituting the driver circuits 13 and 14 of FIG. 5A is shown in FIG. 5B. Since a TFT portion has been described in embodiment 1, only necessary portions will be described here.
Embodiment 5 The present invention can be applied to all conventional IC techniques. That is, the present invention can be applied to all semiconductor circuits presently available on the market. For example, the present invention may be applied to a microprocessor such as a RISC processor integrated on one chip or an ASIC processor, and may be applied to circuits from a signal processing circuit such as a D/A converter to a high frequency circuit for a portable equipment (portable telephone, PHS, mobile computer).
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3964941May 7, 1973Jun 22, 1976Motorola, Inc.Method of making isolated complementary monolithic insulated gate field effect transistorsUS4217153Mar 31, 1978Aug 12, 1980Mitsubishi Denki Kabushiki KaishaMethod of manufacturing semiconductor deviceUS4583122May 25, 1983Apr 15, 1986Hitachi, Ltd.Imaging display deviceUS4665419Apr 1, 1986May 12, 1987Fujitsu LimitedSemiconductor deviceUS4733947Oct 23, 1985Mar 29, 1988Ngk Insulators, Ltd.Multicolor liquid crystal display panelUS4753896Nov 21, 1986Jun 28, 1988Texas Instruments IncorporatedSidewall channel stop processUS4768076Sep 11, 1985Aug 30, 1988Hitachi, Ltd.Recrystallized CMOS with different crystal planesUS4786955Feb 24, 1987Nov 22, 1988General Electric CompanySemiconductor device with source and drain depth extenders and a method of making the sameUS4822752Mar 6, 1987Apr 18, 1989Agency Of Industrial Science And TechnologyProcess for producing single crystal semiconductor layer and semiconductor device produced by said processUS4857986Jul 14, 1986Aug 15, 1989Kabushiki Kaisha ToshibaShort channel CMOS on 110 crystal planeUS4899202Jul 8, 1988Feb 6, 1990Texas Instruments IncorporatedHigh performance silicon-on-insulator transistor with body node to source node connectionUS4933298Dec 19, 1988Jun 12, 1990Fujitsu LimitedMethod of making high speed semiconductor device having a silicon-on-insulator structureUS4943837Mar 10, 1988Jul 24, 1990Hitachi, Ltd.Thin film semiconductor device and method of fabricating the sameUS5002630Jun 6, 1989Mar 26, 1991Rapro TechnologyMethod for high temperature thermal processing with reduced convective heat lossUS5059304Nov 30, 1988Oct 22, 1991Chevron Research CompanyCactalytic hydrogenation to form hydrogen sulfide, adsorption for removalUS5130770Jun 14, 1991Jul 14, 1992BrevatomeIntegrated circuit in silicon on insulator technology comprising a field effect transistorUS5215931Jul 27, 1992Jun 1, 1993Texas Instruments IncorporatedLightly doped drain profile; low resistance contact region lies along entire width of body region; vertical contactUS5243213Jul 8, 1991Sep 7, 1993Sony CorporationMis semiconductor device formed by utilizing soi substrate having a semiconductor thin film formed on a substrate through an insulating layerUS5258323Dec 29, 1992Nov 2, 1993Honeywell Inc.Single crystal silicon on quartzUS5261999May 8, 1991Nov 16, 1993North American Philips CorporationSemiconductors of silicon doped with boron and germanium for p-type laminated structure and etchingUS5317236Dec 31, 1991May 31, 1994Kopin CorporationSingle crystal silicon arrayed devices for display panelsUS5341028Oct 3, 1991Aug 23, 1994Mitsubishi Denki Kabushiki KaishaSemiconductor device and a method of manufacturing thereofUS5371037Aug 5, 1991Dec 6, 1994Canon Kabushiki KaishaSemiconductor member and process for preparing semiconductor memberUS5374564Sep 15, 1992Dec 20, 1994Commissariat A L'energie AtomiqueProcess for the production of thin semiconductor material filmsUS5387555Sep 3, 1992Feb 7, 1995Harris CorporationBonded wafer processing with metal silicidationUS5403759Oct 2, 1992Apr 4, 1995Texas Instruments IncorporatedMethod of making thin film transistor and a silicide local interconnectUS5424230Jul 29, 1994Jun 13, 1995Casio Computer Co., Ltd.Method of manufacturing a polysilicon thin film transistorUS5426062Jun 29, 1994Jun 20, 1995Texas Instruments IncorporatedMethod for forming a silicon on insulator deviceUS5444282Jun 30, 1994Aug 22, 1995Mitsubishi Denki Kabushiki KaishaSemiconductor device and a method of manufacturing thereofUS5508209Sep 27, 1994Apr 16, 1996Semiconductor Energy Laboratory Co., Ltd.Mask and porous oxide formed on gate electrodeUS5550070 *Dec 16, 1994Aug 27, 1996Sharp Kabushiki KaishaMethod for producing crystalline semiconductor film having reduced concentration of catalyst elements for crystallization and semiconductor device having the sameUS5569620Dec 8, 1994Oct 29, 1996Harris CorporationBonded wafer processing with metal silicidationUS5573961Nov 9, 1995Nov 12, 1996Taiwan Semiconductor Manufacturing Company Ltd.Method of making a body contact for a MOSFET device fabricated in an SOI layerUS5574292May 5, 1993Nov 12, 1996Seiko Instruments Inc.Semiconductor device with monosilicon layerUS5576556Aug 16, 1994Nov 19, 1996Semiconductor Energy Laboratory Co., Ltd.Thin film semiconductor device with gate metal oxide and sidewall spacerUS5581092Sep 6, 1994Dec 3, 1996Semiconductor Energy Laboratory Co., Ltd.Gate insulated semiconductor deviceUS5612230Apr 6, 1995Mar 18, 1997Canon Kabushiki KaishaProcess for manufacturing a semiconductor device by applying a non-single-crystalline material on a sidewall inside of an opening portion for growing a single-crystalline semiconductor bodyUS5640033Apr 3, 1996Jun 17, 1997Kabushiki Kaisha ToshibaMOSFET having fine gate electrode structureUS5643826Oct 25, 1994Jul 1, 1997Semiconductor Energy Laboratory Co., Ltd.Disposing crystallization promoting solution containing specified element in contact with amorphous silicon film on substrate, crystallizing by heatingUS5648277Nov 2, 1994Jul 15, 1997Semiconductor Energy Laboratory Co., Ltd.Performing ion introduction for forming impurity regions using the gate electrode and extensions of gate insulating film as mask; varying conditions of introduction in order to control concentrationUS5693959Apr 10, 1996Dec 2, 1997Canon Kabushiki KaishaThin film transistor and liquid crystal display using the sameUS5698869Sep 13, 1995Dec 16, 1997Kabushiki Kaisha ToshibaInsulated-gate transistor having narrow-bandgap-sourceUS5710057Jul 12, 1996Jan 20, 1998Kenney; Donald M.SOI fabrication methodUS5714395Sep 12, 1996Feb 3, 1998Commissariat A L'energie AtomiqueDoping surface of wafer, creating cleavage layer, heat treating to cause separation of surface layerUS5719065Sep 28, 1994Feb 17, 1998Semiconductor Energy Laboratory Co., Ltd.High resistivity region formed between channel region and each of the sources and drain regions; film capable of trapping positive charges on high resistivity regionUS5750000Nov 25, 1996May 12, 1998Canon Kabushiki KaishaSemiconductor member, and process for preparing same and semiconductor device formed by use of sameUS5778237Dec 14, 1995Jul 7, 1998Hitachi, Ltd.Data processor and single-chip microcomputer with changing clock frequency and operating voltageUS5784132Jun 16, 1997Jul 21, 1998Sony CorporationDisplay deviceUS5793073Mar 1, 1996Aug 11, 1998Ricoh Co., Ltd.Semiconductor thin film sensor device with (110) planeUS5818076Jan 30, 1996Oct 6, 1998Semiconductor Energy Laboratory Co., Ltd.Transistor and semiconductor deviceUS5821138Feb 16, 1996Oct 13, 1998Semiconductor Energy Laboratory Co., Ltd.Forming multilayer of first and second insulating films, an amorophous silicon films, holding a metal element that enhance the crystallization of silicon, crystallization by heat treatment, forming thin film transistor and sealing filmUS5837569Dec 30, 1996Nov 17, 1998Sharp Kabushiki KaishaAnnealing to crystallize patterned region of amorphous silicon substrate surface selectively seeded with crystallization promoter, further processing to form thin film transistorUS5840616Sep 8, 1995Nov 24, 1998Canon Kabushiki KaishaMethod for preparing semiconductor memberUS5841173Jun 13, 1996Nov 24, 1998Matsushita Electric Industrial Co., Ltd.MOS semiconductor device with excellent drain currentUS5849627Apr 28, 1995Dec 15, 1998Harris CorporationBonded wafer processing with oxidative bondingUS5854123Oct 7, 1996Dec 29, 1998Canon Kabushiki KaishaMethod for producing semiconductor substrateUS5854509May 2, 1996Dec 29, 1998Mitsubishi Denki Kabushiki KaishaMethod of fabricating semiconductor device and semiconductor deviceUS5877070May 31, 1997Mar 2, 1999Max-Planck SocietyMethod for the transfer of thin layers of monocrystalline material to a desirable substrateUS5882987Aug 26, 1997Mar 16, 1999International Business Machines CorporationSmart-cut process for the production of thin semiconductor material filmsUS5886385Aug 20, 1997Mar 23, 1999Kabushiki Kaisha ToshibaSemiconductor device and manufacturing method thereofUS5893730Feb 19, 1997Apr 13, 1999Semiconductor Energy Laboratory Co., Ltd.Using metal catalyst to crystallize a silicon oxide film by chemical vapor depostion and irradiating film to form a monodomain region; transistor having an active layer constituted by a crystalline silicon filmUS5899711Oct 11, 1996May 4, 1999Xerox CorporationMethod for enhancing hydrogenation of thin film transistors using a metal capping layer and method for batch hydrogenationUS5904528Jan 17, 1997May 18, 1999Advanced Micro Devices, Inc.Method of forming asymmetrically doped source/drain regionsUS5913111Jan 17, 1996Jun 15, 1999Canon Kabushiki KaishaMethod of manufacturing an insulaed gate transistorUS5923962Apr 28, 1995Jul 13, 1999Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing a semiconductor deviceUS5926430Dec 5, 1997Jul 20, 1999Hitachi, Ltd.Semiconductor integrated circuit device and method of activating the sameUS5943105Jun 25, 1997Aug 24, 1999Sharp Kabushiki KaishaLiquid crystal display device having specified structure for contact hole connecting pixel electrode with source/drain electrodes via a connecting electrodeUS5949107Nov 5, 1996Sep 7, 1999Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating sameUS5953622Sep 15, 1997Sep 14, 1999Hyundai Electronics Industries Co., Ltd.Method for fabricating semiconductor wafersUS5962897Jun 30, 1997Oct 5, 1999Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the sameUS5965918Mar 18, 1999Oct 12, 1999Kabushiki Kaisha ToshibaSemiconductor device including field effect transistorUS5966594Dec 18, 1996Oct 12, 1999Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the sameUS5966620Nov 14, 1997Oct 12, 1999Canon Kabshiki KaishaProcess for producing semiconductor articleUS5982002Jan 27, 1993Nov 9, 1999Seiko Instruments Inc.Light valve having a semiconductor film and a fabrication process thereofUS5985681Sep 24, 1997Nov 16, 1999Nec CorporationMethod of producing bonded substrate with silicon-on-insulator structureUS5985740Jan 16, 1997Nov 16, 1999Semiconductor Energy Laboratory Co., Ltd.Crystallizing amorphous semiconductor film by first heat treatment and reducing catalyst existing in film by a second heat treatment within an oxidizing atmosphere containing a halogenUS6020252May 14, 1997Feb 1, 2000Commissariat A L'energie AtomiqueDoping by bombardmentUS6027988Aug 20, 1997Feb 22, 2000The Regents Of The University Of CaliforniaMethod of separating films from bulk substrates by plasma immersion ion implantationUS6031249Jul 8, 1997Feb 29, 2000Semiconductor Energy Laboratory Co., Ltd.CMOS semiconductor device having boron doped channelUS6044474Apr 8, 1997Mar 28, 2000Klein; Dean A.Memory controller with buffered CAS/RAS external synchronization capability for reducing the effects of clock-to-signal skewUS6049092Apr 10, 1997Apr 11, 2000Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the sameUS6051453Sep 5, 1996Apr 18, 2000Semiconductor Energy Laboratory Co., Ltd.Forming a non-single crystal semiconductor film comprising silicon and hydrogen on an insulating surface, ejecting hydrogen from non-single crystal semiconductor film, crystallizing the semiconductor film by irradiating a lightUS6054363Nov 12, 1997Apr 25, 2000Canon Kabushiki KaishaMethod of manufacturing semiconductor articleUS6063706Jan 28, 1998May 16, 2000Texas Instruments--Acer IncorporatedMethod to simulataneously fabricate the self-aligned silicided devices and ESD protective devicesUS6077731Jan 17, 1997Jun 20, 2000Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for fabricating the sameUS6093937Feb 19, 1997Jul 25, 2000Semiconductor Energy Laboratory Co. Ltd.Semiconductor thin film, semiconductor device and manufacturing method thereofUS6096582Jul 23, 1997Aug 1, 2000Canon Kabushiki KaishaMethod of making a semiconductor deviceUS6107639Aug 25, 1998Aug 22, 2000Semiconductor Energy Laboratory Co., Ltd.Semiconductor device with rod like crystals and a recessed insulation layerUS6107654Feb 8, 1999Aug 22, 2000Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS6118148Nov 4, 1997Sep 12, 2000Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and manufacturing method thereofUS6124613May 4, 1998Sep 26, 2000Nec CorporationSOI-MOS field effect transistor that withdraws excess carrier through a carrier path silicon layerUS6127702Sep 16, 1997Oct 3, 2000Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having an SOI structure and manufacturing method thereforUS6133073Apr 23, 1998Oct 17, 2000Semiconductor Energy Laboratory Co., Ltd.Thin film semiconductor and method for manufacturing the same, semiconductor device and method for manufacturing the sameUS6140667Feb 20, 1998Oct 31, 2000Semiconductor Energy Laboratory Co., Ltd.Semiconductor thin film in semiconductor device having grain boundariesUS6157421Dec 8, 1995Dec 5, 2000Canon Kabushiki KaishaLiquid crystal display and method of manufacturing the sameUS6165880Jun 15, 1998Dec 26, 2000Taiwan Semiconductor Manufacturing CompanyDouble spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuitsUS6171982Dec 22, 1998Jan 9, 2001Canon Kabushiki KaishaMethod and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the sameUS6184556Jul 2, 1998Feb 6, 2001Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS6191007Apr 28, 1998Feb 20, 2001Denso CorporationMethod for manufacturing a semiconductor substrateUS6191476May 20, 1997Feb 20, 2001Seiko Instruments Inc.Semiconductor device* Cited by examinerNon-Patent CitationsReference1Assaderaghi et al., "A 7.9/5.5 psec Room/Low Temperature SOI CMOS", IEDM: Technical Digest of International Electron Devices Meeting, Dec. 7, 1997, pp. 415-418.2Auberton-Herve, A.J. et al, "Industrial Research Society (Kogyo Chosa Kai)," Electronic Material, Aug. 1997, pp. 83-87.3Auberton-Herve, A.J. et al, "Unibond SOI Wafer by Smart Cut," Industrial Research Society (Kogyo Chosa Kai), Electronic Material, Aug. 1997, full English translation, pp. 1-12.4Bell, T.E. et al, "A Dissolved Wafer Process Using a Porous Silicon Sacrificial Layer and a Lightly-Doped Bulk Silicon Etch-Stop," IEEE, 1998, pp. 251-256.5Bruel, M., "Silicon on Insulator Material Technology," Electronics Letters, vol. 31, No. 14, Jul. 6, 1995, pp. 1201-1202.6Chau et al., "Scalability of Partially Depleted SOI Technology for Sub-0.25muM Logic Applications", IEDM: Technical Digest of International Electron Devices Meeting, Dec. 7, 1997, pp. 591-594.7Ishiyama et al., "Application of Reversed Silicon Wafer Direct Bonding to Thin-Film SOI Power ICs", Extended Abstracts of the 1997 International Conference on Solid State Devices and Materials, Sep. 16, 1997, pp. 162-163.8Izumi, K. et al, "C.M.O.S. Devices Fabricated on Buried SiO2 Layers Formed by Oxygen Implantation into Silicon," Electronics Letters, vol. 14, No. 18, Aug. 31, 1978, pp. 593-594.9Nandakuma, "Shallow Trench Isolation for advanced ULSI CMOS Technologies", IEDM: Technical Digest of International Electron Devices Meeting, Dec. 6, 1998, pp. 133-136.10Office Action (Japanese Patent Application No. 10-174482) dated Feb. 5, 2009, with full English Translation, 2 pages.11Office Action (Japanese Patent Application No. 10-174482) dated Jul. 15, 2008, with full English Translation, 6 pages.12Office Action (Japanese Patent Application No. 10-174482) dated Oct. 7, 2008, with full English Translation, 7 pages.13Office Action (Japanese Patent Application No. 2007-024310) dated Jan. 20, 2009, with full English Translation, 7 pages.14Office Action (Japanese Patent Application No. 2009-190690) dated Oct. 6, 2009, with full English Translation, 8 pages.15Office Action (Japanese Patent Application No. 2009-190694) dated Oct. 6, 2009, with full English Translation, 10 pages.16Office Action (U.S. Appl. No. 11/670,462) dated May 8, 2009.17Office Action (U.S. Appl. No. 11/716,583) dated Sep. 5, 2008, 18 pages.18Office Action (U.S. Appl. No. 11/926,520) dated Feb. 26, 2009, 29 pages.19Office Action (U.S. Appl. No. 11/926,598) dated May 22, 2009, 26 pages.20Office Action (U.S. Appl. No. 11/926,623) dated Dec. 12, 2008, 21 pages.21Office Action (U.S. Appl. No. 11/926,623) dated Jun. 25, 2008, 16 pages.22Office Action (U.S. Appl. No. 11/978,586) dated May 29, 2009, 31 pages.23Office Action (U.S. Appl. No. 11/978,605) dated Dec. 31, 2008, 23 pages.24Office Action (U.S. Appl. No. 11/978,609) dated May 29, 2009, 23 pages.25Office Action (U.S. Appl. No. 11/978,610) dated Oct. 7, 2009, 32 pages.26Office Action (U.S. Appl. No. 111926,623) dated Jun. 26, 2009, 24 pages.27Office Action (U.S. Appl. No. 12/216,754) dated Apr. 9, 2009, 23 pages.28Sakaguchi, K. et al, "Current Progress in Epitaxial Layer Transfer (ELTRAN)," IEICE Trans. Electron, vol. E80 C, No. 3, Mar. 1997, pp. 378-387.29U.S. Appl. No. 11/978,610, filed Oct. 30, 2007, including specification, claims, abstract and drawings.30U.S. Patent Office Action (U.S. Appl. No. 11,978,605), dated Jun. 9, 2008, 20 pages.31Wolf, S., Silicon Processing for the VLSI Era, vol. 2: Process Integration, Lattice Press, 1990, pp. 238-239.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8314012Sep 15, 2010Nov 20, 2012Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing semiconductor substrate and method for manufacturing semiconductor deviceUS8324086Jan 14, 2009Dec 4, 2012Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing a semiconductor substrate by laser irradiationUS8394703Dec 9, 2009Mar 12, 2013Semiconductor Energy Laboratory Co., Ltd.Manufacturing method of SOI substrate and manufacturing method of semiconductor deviceUS8471272Sep 8, 2010Jun 25, 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having a display portionUS8513678May 12, 2008Aug 20, 2013Semiconductor Energy Laboratory Co., Ltd.Light-emitting deviceUS8674368Mar 28, 2012Mar 18, 2014Semiconductor Energy Laboratory Co., Ltd.Display device and method for manufacturing thereofUS8759842Jun 7, 2011Jun 24, 2014Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the sameUS8772128Oct 7, 2008Jul 8, 2014Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing semiconductor deviceClassifications U.S. Classification257/347, 257/E21.563International ClassificationH01L29/786, H01L21/762, H01L27/12, H01L21/336, H01L21/02, H01L21/30Cooperative ClassificationY10S438/973, Y10S438/977, H01L21/76243, H01L27/1203, H01L29/045, H01L27/1266, H01L21/76256, H01L27/1214, H01L29/78603, H01L29/66772, H01L21/76254European ClassificationH01L21/762D2, H01L29/66M6T6F15C, H01L21/762D8D, H01L27/12T, H01L27/12T30A2, H01L21/762D8B, H01L27/12B, H01L29/04B, H01L29/786ALegal EventsDateCodeEventDescriptionMar 11, 2013FPAYFee paymentYear of fee payment: 4Jun 1, 2010CCCertificate of correctionFeb 16, 2010CCCertificate of correctionRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services