Source: http://www.google.com/patents/US7312511?dq=7,468,661
Timestamp: 2015-04-27 22:33:36
Document Index: 709866670

Matched Legal Cases: ['art 35', 'art 35', 'art 35', 'art 35', 'art 35', 'arts 11', 'arts 11', 'art 11']

Patent US7312511 - Semiconductor device with electrically isolated ground structures - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThis invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which...http://www.google.com/patents/US7312511?utm_source=gb-gplus-sharePatent US7312511 - Semiconductor device with electrically isolated ground structuresAdvanced Patent SearchPublication numberUS7312511 B2Publication typeGrantApplication numberUS 11/455,157Publication dateDec 25, 2007Filing dateJun 19, 2006Priority dateApr 30, 2002Fee statusPaidAlso published asUS20060237830Publication number11455157, 455157, US 7312511 B2, US 7312511B2, US-B2-7312511, US7312511 B2, US7312511B2InventorsTadatoshi Danno, Tsutomu TsuchiyaOriginal AssigneeRenesas Technology Corp.Export CitationBiBTeX, EndNote, RefManPatent Citations (12), Referenced by (5), Classifications (71), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device with electrically isolated ground structures
US 7312511 B2Abstract
the first electrode is electrically connected with one of the leads via a first conductive wire;
2. The semiconductor device according to claim 1, wherein the semiconductor device has a Quad Flat Non-leaded Package (QFN) structure.
3. The semiconductor device according to claim 1, wherein the low noise amplifier processes a radio signal received by an antenna.
4. The semiconductor device according to claim 1, wherein the semiconductor device further comprises a modulator, a demodulator, and terminals for coupling with a base band circuit of the radio communication device,
5. A semiconductor device for use in a radio communication device, comprising:
6. A semiconductor device for use in a radio communication device, comprising:
7. A semiconductor device for use in a radio communication device, comprising:
the first ground is electrically connected with the chip mounting portion by at least one downbonded wire; and
the second ground is electrically connected to one or more of the leads by at least one additional wire and has no downbonded wire connection to the chip mounting portion.
This application is a division of application Ser. No. 10/512,459 filed Oct. 26, 2004, which is a 371 of International Application No. PCT/JP03/05475 filed Apr. 28, 2003.
Further, in Japanese Unexamined Patent Publication No. Hei 11(1999)-186921 (laid open to public inspection on Jul. 9, 1999), a multiple band mobile body communication device which is applicable to mobile phone systems such as a PCN (Personal Communication Network: DCS-1800), PCS (Personal Communications Service: DCS-1900), GSM and the like is disclosed.
The dual band method processes signals of two communication systems such as the GSM method and the DCS 1800 method, while the triple band method processes signals of three communication systems such as the dual band method, the DCS (Digital Cellular System) 1800 and the PCS1900 method. As the GSM, a GSM900 or a GSM 850 is incorporated.
Accordingly, as shown in FIG. 34B, by adopting the two-input method in which a differential low noise amplifier (differential amplifier: LNA) is used as the LNA100 and signals which have phases thereof inverted from each other (complementary signals) are inputted, a DC offset is set to a small value. That is, the differential amplifier (differential amplifying circuit) 10Q is comprised of two unit amplifiers having the same constitution and performs the differential amplification when two high frequency signals (complementary signals) (which have phases thereof inverted from each other) are inputted. Accordingly, the components having the same phase are cancelled and hence, it is possible to suppress the DC offset value to a small value.
For example, the lead-portion which is formed of a plate member made of metal such as copper has relatively large thickness and width and hence, the difference in inductance due to the minute difference in lead length of several mm is small. However, with respect to the wire portion where the diameter is approximately 20 to 30 μm, the large difference in inductance is liable to be generated due to the difference in length of the wire portion. This difference in wire inductance can be expressed as the difference in inputting time of two complementary input signals and hence, the pair characteristics of the input signals is impaired. As a result, in the high-speed communication system, the above-mentioned circuit part is not favorable with respect to a point that the gain is lowered.
The tab 4 has four corners thereof supported by narrow tab supporting leads 6. These tab supporting leads 6 are positioned on diagonal lines of the quadrangular sealing body 2 and have outer ends thereof face respective corner portions of the quadrangular sealing body 2. The sealing body 2 has a flattened quadrangular shape and corner portions thereof are chamfered to form oblique faces 2 a (see FIG. 1). Outer ends of the tab supporting leads 6 slightly project onto the chamfered portions by 0.1 mm or less. The projection length is determined by a cutting mold of a press machine at the time of cutting the tab supporting leads 6 in a lead frame state. For example, the projection length of 0.1 mm or less is selected.
Further, side surfaces of the sealing body 2 a reformed into inclined surfaces 2 b (see FIG. 2). The inclined surfaces 2 b are formed as a result of designing the sealing body 2 such that the sealing body 2 is formed over one surface of the lead frame by one-face molding and, thereafter, at the time of removing the sealing body 2 from a cavity of a forming mold, the side surfaces of the cavity are formed into inclined surfaces to facilitate the removal of the forming mold. Here, FIG. 1 is a schematic view in which an upper portion of the sealing body 2 is cut away to allow the watching of the tab 4, the tab supporting leads 6, the lead 7, the semiconductor chip 3 and the like.
Here, the manufacturing method of the semiconductor device 1 of this embodiment 1 is explained in conjunction with FIG. 6 to FIG. 11. As shown in the flow chart described in FIG. 6, the semiconductor device 1 is manufactured through respective steps comprising of the preparation of the lead frame (S101), the chip bonding (S102), the wire bonding (S103) sealing (molding: S104), plating processing (S105), and cutting and removing of the dispensable lead frame (S106).
Further, as shown in FIG. 8, on the main surface of the tab 4, the quadrangular region at the center thereof is a semiconductor element mounting portion 4 a (region surrounded by a chain double-dashed line) and a region outside the semiconductor element mounting portion 4 a is a wire connecting region 4 b. After preparing such a lead frame 13, as shown in FIG. 8 and FIG. 9, the semiconductor chip 3 is fixed to the semiconductor element mounting portion 4 a of the tab 4 of each unit lead frame patterns 14 by way of the adhesive agent 5 (chip bonding)(S102).
A thickness of the lead frame 13 (tab 4, tab supporting leads 6, leads 7) is 0.2 mm, a thickness of the chip 3 is 0.28 mm, a thickness of the semiconductor device 1 is 1.0 mm, a width of the leads 7 is 0.2 mm, a length of the leads 7 is 0.5 mm, a distance between a wire connection portion (point) of the tab 4 and the end of the chip 3 mounted on the tab 4 is 0.1 mm, and a distance between the tab 4 and the lead 7 is 0.2 mm.
On the main surface of the mounting board (printed circuit board) 80 of the mobile phone, for mounting the semiconductor device 1, a land 81 and a tab fixing portion 82 which are contiguously formed with the wires corresponding to the leads 7 and the tab 4 of the semiconductor device 1 are formed. Here, the semiconductor device 1 is positioned and placed on the mounting board 80 such that the leads 7 and the tab 4 of the semiconductor device 1 correspond-to and are overlapped to the land 81 and the fixing portion 82. Then, in such a state, a solder plating film which is preliminarily formed over a back surface of the leads 7 and the tab 4 of the semiconductor device 1 is temporarily made to reflow so as to connect (mount) the leads 7 and the tab 4 with a solder 83.
The semiconductor chip 3 is provided with a synthesizer which is comprised of an RF synthesizer 41 and an IF (intermediate) synthesizer 42 as signal processing ICs. The RF synthesizer 41 is connected with a RFVCO 44 through a buffer 43 and performs a control such that the RFVCO 44 outputs an RF local signal. Two frequency dividers 37, 38 for local signals are connected to the buffer 43 in series and switches 48, 49 are connected to respective output ends of the frequency dividers 37, 38. The RF local signal transmitted from the RFVCO 44 is inputted to the 90-degree phase converter 40 by the change over of the switch 48. In response to the RF local signal, the 90-degree phase converter 40 controls the mixer 26.
The transmission system includes two mixers 61 which uses the I/Q signals outputted from the base band chip 22 as input signals, a 90-degree phase shifter 62 which controls phases of these two mixers 61, an adder 63 which adds outputs of these two mixers 61, a mixer 64 and DPD (digital phase detector) 65 which receive an output of the adder 63 as inputs thereof, a loop filter 66 which receives outputs of the mixer 64 and the DPD65 as an input thereof, two TXVCO (transmission wave voltage control oscillators) 67 which receive an output of the loop filter 66 as inputs thereof, a power module 68 which receives outputs of two TXVCO 67 as an input thereof, and the antenna switch 21. The loop filter 66 is an exteriorly mounted part.
FIG. 4 is a schematic layout chart showing the arrangement of respective circuit parts in the semiconductor chip 3. On the main surface of the semiconductor chip 3, electrode terminals (pads) 9 are arranged along the sides. Further, in the inside of these electrode terminals 9, the respective circuit parts are arranged by dividing the region. As shown in FIG. 4, at the center of the semiconductor chip 3, the control logic circuit part 35 for ADC/DAC&DC offset is arranged. On the other hand, the mixers 26, 64 and three LNA24 are arranged in parallel at the left side of the control logic circuit part 35, the RFVCO 44 is positioned at the upper side of the control logic circuit part 35, the RF synthesizer 41, the VCXO 50, the IF synthesizer 42 and the IFVCO 45 are arranged at the right side of the control logic circuit part 35 from an upper portion to a lower portion, and the TXVCO 67 is positioned at the lower side of the control logic circuit part 35.
To focus on three LNA 24 which are the specified circuit parts 11 (the first circuit parts), the leads 7 which are expected to be connected with the band pass filter 23 which is an exteriorly mounted part, that is, the leads 7 on which �Signal� is described on the left side thereof and the signal electrode terminals 9 of the LNA 24 are connected through the wires 10. Two signal lines which reach the lead 7 from the electrode terminals 9 through the wires 10 are provided. At both sides of these signal lines, the ground electrode terminals 9 of the LNA 24 which is the specified circuit parts 11 are connected to the grounding lead 7 (the lead 7 which is described as GND at the left side in the drawing) through the wires 10 thus forming the ground lines.
(6) In the high frequency power modulel, the electrode terminals 9 of the semiconductor chip 3 and the leads (pins) 7 are connected with each other using the wires 10 and at the same time, the tab 4 which assumes the ground potential and the electrode terminals (grounding electrode terminals) of the semiconductor chip 3 are connected with each other using down-bond wires 10 a thus providing the down-bonding structure. Accordingly, the number of grounding leads which become the external electrode terminals 7 can be reduced, and hence, the miniaturization of the sealing body 2 attributed to the reduction of the number of pins can be realized whereby the miniaturization of the high frequency power module 1 can be achieved.
This embodiment 4 is characterized in that the tab 4 which serves as the common ground terminal and the leads 7 which are made to assume the ground potential are electrically connected with each other using the conductive wires lob, and the leads 7 also serve as ground external electrode terminals. In the semiconductor device 1 of this embodiment 4, since the back surface of the tab 4 is exposed from the back surface (mounting surface) of the sealing body 2, the tab 4 can be used as the ground external electrode terminal and, at the same time, the leads 7 which are connected to the tab 4 through the wires 10 b are also used as the ground external electrode terminal.
A plurality of circuit-parts of the semiconductor chip 3 include differential amplifiers (differential amplifying circuit parts) having a pair of inputs. In this differential amplifying circuit parts, as shown in FIG. 25, the low noise amplifier (LNA) 24 is formed. As shown in FIG. 25, with respect to a specified circuit part 11 which surrounds three LNA, in a region which is insulated and separated from other circuit parts in the semiconductor chip, respective LNA are formed. Then, the respective LNA use the common ground level. The constitution of this part is substantially equal to the constitution described in the embodiment 1.
Further, as described above, the second portion 7 d of the lead 7 is positioned in the inside of the sealing body 2 and is not exposed from the back surface of the resin sealing body 2 and hence, the second portion 7 d of the lead 7 can extend in the free direction. That is, as shown in 24A, the extending direction of the second portion 7 d can be aligned with the extending direction of the wire 10 and hence, the wire 10 can be positioned within the width of the distal end of the lead 7 whereby the length of the connection portion of the wire 10 can be made long as �f�.
As described in conjunction with the embodiment 5, as shown in FIG. 24A, by making the extending direction of the second portion 7 d aligned with the stretch direction of the wire 10, the connection length between the lead 7 and the wire 10 can be elongated as �f�. Accordingly, the connection strength of the wire can be increased and the reliability of the connection of the wire (wire bonding) can be enhanced.
Further, the pair characteristics of the input signals is similarly important also in the RFVC044 which processes a high frequency signal. In the embodiment 5, as shown in FIG. 25, two wires 10 which are two signal lines which extend in the RFVC044 are also configured to have the same wire length. Further, the electromagnetic shielding is applied to two signal lines by ground lines arranged at both sides of the two signals and hence, the generation of crosstalk can be prevented.
In the embodiment 5, as shown in the schematic enlarged cross-sectional view of FIG. 27, the semiconductor chip 3 is mounted on the chip mounting portion 4 by way of an adhesive agent 5. The semiconductor chip 3 includes a first semiconductor substrate 85, an insulation layer 86 formed over the surface of the first semiconductor substrate 85, a second semiconductor substrate 87 formed over the insulation layer 86 and, the plurality of electrode terminals 9 a reformed over the main surface of the second semiconductor substrate 87, the plurality of circuit parts are formed over the second semiconductor substrate 87 and the back surface of the first semiconductor substrate 85 of the semiconductor chip 3 is electrically connected to the chip mounting portion 4 by way of a conductive adhesive agent 5.
In the high frequency power module 1 according to the embodiment 5, the low noise amplifier (LNA) 24 which processes high frequency signals and the RFVC044 adopt two input-two output constitution and, at the same time, to ensure the pair characteristics of two input signals, the lengths of the wires 10 of two inputs are set to the equal length. Further, with respect to the length of the wires 10 forming the signal line, by connecting the wire 10 to the electrode terminal 9 of the semiconductor chip 3 and to the end portion of the second portion 7 d of the lead 7, the length of the wire is made short so as to reduce the wire inductance. Accordingly, the enhancement of the high frequency characteristics (DC offset being small) can be achieved.
The inventions made by inventors of the present invention have been specifically explained here to fore based on the embodiments, however, the present invention is not limited to the above-mentioned embodiments and various modifications can be made without departing from the gist of the present invention.
(7) As has been described heretofore, the semiconductor device according to the present invention is used for a radio communication device such as a mobile telephone or the like. Specifically, in a mobile telephone having a plurality of communication systems, ground electrode terminals of a circuit part which processes an extremely weak input signal such as a low noise amplifier are not connected to the tab serving as a common ground potential and but connected to the leads all of which are independent from each other and hence, when a communication system is used, cross talk between the communication system and the other communication systems is not generated and a high frequency power module which enables a favorable telephone call can be provided.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6104078Sep 30, 1997Aug 15, 2000Denso CorporationDesign for a semiconductor device having elements isolated by insulating regionsUS6628170 *Jun 4, 1998Sep 30, 2003Analog Devices, Inc.Low noise amplifierUS6686652 *Jul 14, 2000Feb 3, 2004National SemiconductorLocking lead tips and die attach pad for a leadless package apparatus and methodUS7013123 *Feb 20, 2001Mar 14, 2006Hitachi, Ltd.Wireless communication systemEP1187208A2Aug 3, 2001Mar 13, 2002Hitachi ULSI Systems Co.,Ltd.Semiconductor deviceJP2000091489A Title not availableJP2001189402A Title not availableJP2001313363A Title not availableJP2002026222A Title not availableJP2002076235A Title not availableJPH11186921A Title not availableJPH11251494A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7777309 *Feb 19, 2008Aug 17, 2010Renesas Technology Corp.Amplifier chip mounted on a lead frameUS7937105 *Feb 17, 2008May 3, 2011Renesas Electronics CorporationSemiconductor device and electronic deviceUS8126501 *Apr 26, 2011Feb 28, 2012Renesas Electronics CorporationSemiconductor device and electronic deviceUS8558363 *Mar 10, 2011Oct 15, 2013Toppan Printing Co., Ltd.Lead frame substrate and method of manufacturing the same, and semiconductor deviceUS20110163435 *Mar 10, 2011Jul 7, 2011Toppan Printing Co., Ltd.Lead frame substrate and method of manufacturing the same, and semiconductor device* Cited by examinerClassifications U.S. Classification257/503, 257/E23.124, 257/E23.046, 257/E23.037, 257/E23.079, 257/E21.514, 257/E23.153International ClassificationH01L29/00Cooperative ClassificationH01L2924/1306, H01L24/32, H01L24/48, H01L2924/01078, H01L23/3107, H01L2224/45144, H01L24/85, H01L2924/19107, H01L2924/19041, H01L2924/01079, H01L2924/01023, H01L24/97, H01L2224/85, H01L2924/01015, H01L2924/01029, H01L2924/3011, H01L2924/30105, H01L23/49503, H01L2224/32245, H01L23/49548, H01L2924/01047, H01L23/50, H01L2924/20752, H01L2924/13091, H01L2224/97, H01L2924/014, H01L2224/45015, H01L2924/3025, H01L2224/48257, H01L2924/01014, H01L2924/01046, H01L2924/01019, H01L2224/29007, H01L2924/01013, H01L2924/14, H01L2224/49171, H01L2224/92, H01L2924/00014, H01L2924/01033, H01L23/66, H01L24/45, H01L2224/48091, H01L24/49, H01L2224/48247, H01L2924/01082, H01L21/561, H01L2924/01005, H01L2224/73265, H01L2924/01006, H01L2224/4911, H01L2224/92247, H01L2924/30107, H01L2224/32013European ClassificationH01L24/85, H01L24/31, H01L24/49, H01L24/97, H01L23/495G4, H01L23/50, H01L23/31H, H01L21/56B, H01L23/495A, H01L23/66Legal EventsDateCodeEventDescriptionMay 25, 2011FPAYFee paymentYear of fee payment: 4Aug 13, 2010ASAssignmentEffective date: 20100401Owner name: NEC ELECTRONICS CORPORATION, JAPANFree format text: MERGER;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:024879/0190Owner name: RENESAS ELECTRONICS CORPORATION, JAPANFree format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:024864/0635Effective date: 20100401RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services