Source: http://www.google.com/patents/US8239580?dq=6,921,985
Timestamp: 2016-05-03 12:10:57
Document Index: 62947156

Matched Legal Cases: ['Application No. 6', 'Application No. 93918401', 'Application No. 93110478', 'Application No. 157562', 'Application No. 157562', 'Application No. 47881', 'Application No. 93918428', 'Application No. 93918424', 'Application No. 93918401', 'Application No. 93110478', 'Application No. 93918428', 'Application No. 2', 'Application No. 93918401', 'Application No. 59873', 'Application No. 157562', 'Application No. 47881', 'Application No. 93110478', 'Application No. 93918401', 'Application No. 47881', 'Application No. 93918424', 'Application No. 93918401', 'Application No. 2', 'Application No. 93918401', 'Application No. 59873', 'Application No. 93918428', 'Application No. 93918428', 'Application No. 47881', 'Application No. 93918424', 'Application No. 93918401', 'Application No. 93921684', 'Application No. 6', 'Application No. 6', 'Application No. 6', 'Application No. 6', 'Application No. 2005', 'Application No. 157562']

Patent US8239580 - Programmed I/O ethernet adapter with early interrupts for accelerating data ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsIn a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed...http://www.google.com/patents/US8239580?utm_source=gb-gplus-sharePatent US8239580 - Programmed I/O ethernet adapter with early interrupts for accelerating data transferAdvanced Patent SearchPublication numberUS8239580 B2Publication typeGrantApplication numberUS 12/939,604Publication dateAug 7, 2012Priority dateJul 2, 1992Also published asDE69329607D1, DE69329607T2, EP0577115A2, EP0577115A3, EP0577115B1, US5412782, US5485584, US5872920, US6112252, US20110047302Publication number12939604, 939604, US 8239580 B2, US 8239580B2, US-B2-8239580, US8239580 B2, US8239580B2InventorsRichard Hausman, Paul William Sherer, James P. Rivers, Cynthia Zikmund, Glenn W. Connery, Niles E. Strohl, Richard S. ReidOriginal AssigneeU.S. Ethernet Innovations, LlcExport CitationBiBTeX, EndNote, RefManPatent Citations (124), Non-Patent Citations (220), Classifications (29), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetProgrammed I/O ethernet adapter with early interrupts for accelerating data transfer
US 8239580 B2Abstract
a host computer comprising a system bus; and
a data communications adapter comprising:
a host interface coupled to said system bus and configured to exchange data with said host computer via said system bus;
a transceiver coupled to receive and transmit data over communications media;
data transmit control circuitry responsive to said Ethernet control circuitry and coupled to said transceiver, to a transmit data buffer, and to said host interface, for generating a packet transmit signal causing said transceiver to begin transmitting data from said transmit data buffer over said communications media;
data receive control circuitry responsive to said Ethernet control circuitry and coupled to said transceiver, to said receive data buffer, and to said host interface, for storing data received by said transceiver in said receive data buffer, and for generating a receive interrupt signaling to said host computer that data has been received by said transceiver, wherein said data receive control circuitry is operative to generate said receive interrupt once said transceiver has received over said communications media a predetermined number of bytes of a data packet that is less than all of said data packet, wherein said Ethernet control circuitry, said host interface, said data receive control circuitry, said data transmit control circuitry, said receive data buffer, and said transmit data buffer are all contained in a single Application Specific Integrated Circuit (ASIC).
2. The apparatus of claim 1, wherein said data receive control circuitry is programmable.
3. The apparatus of claim 1, wherein said data transmit control circuitry is programmable to generate said packet transmit signal when said transmit data buffer contains the predetermined number of bytes of the data packet that is less than all of said data packet.
4. The apparatus of claim 1 wherein the receive data buffer is a ring buffer connected to the host interface via a DMA channel.
5. The apparatus of claim 1 wherein said host interface is coupled to said host computer.
6. A method performed on a host computer of transferring a packet of data from a computer network communications media through an adapter to a system bus coupled to a central processing unit (CPU) of the host computer, said method comprising the steps of:
receiving from said computer network communications media through a transceiver and storing in an adapter receive buffer a predetermined first receive threshold number of bytes of said packet of data;
generating a first early receive interrupt from said adapter to said CPU via the system bus;
adjusting said first receive threshold number of bytes according to a length of said packet of data;
continuing to receive from said computer network communications media through said transceiver and store in the adapter receive buffer bytes of said packet of data;
thereafter generating a second early receive interrupt from said adapter to said CPU via the system bus, prior to complete reception of said packet of data; and
storing from said communications media through said transceiver and storing in said adapter receive buffer a remainder of said packet of data;
wherein said host computer employs a driver allowing for early indications and having an early lookahead size associated with the predetermined first receive threshold number of bytes.
7. The method of claim 6, further comprising, after the step of generating said first early receive interrupt, the steps of:
b) adjusting said first receive threshold number of bytes if said evaluating step does not indicate substantial equality. Description
This application is a continuation of U.S. patent application Ser. No. 09/488,942, filed Jan. 21, 2000, which is a continuation of U.S. patent application Ser. No. 09/028,088 filed Feb. 23, 1998, now U.S. Pat. No. 6,112,252, which is a continuation of U.S. patent application Ser. No. 08/503,797 filed Jul. 18, 1995, now U.S. Pat. No. 5,872,920, which is a continuation of U.S. patent application Ser. No. 08/374,491, filed Jan. 17, 1995, now U.S. Pat. No. 5,485,584, which is a divisional of U.S. patent application Ser. No. 07/907,946, filed Jul. 2, 1992, now U.S. Pat. No. 5,412,782, the disclosures of which are incorporated herein by reference in their entireties.
This invention-relates to the field of local computer networks, more particularly to an Ethernet adapter providing high throughput for hosts of a network.
The minimal latency of the adapter allows the adapter to employ relatively smaller receive and transmit FIFO buffers which can be contained within RAM internal to an Application Specific Integrated Circuit (ASIC). Specifically, the
ASIC may contain the transceiver, ethernet control circuitry, FIFO control circuitry, FIFO RAM buffers and the host interface in one unit. A further understanding of the nature and advantage of this invention may be realized by reference to the remaining portions of the specification and drawings.
Referring to FIG. 1, a block diagram is shown of an adapter 10 according to the present invention for communications between a client host computer and an ethernet computer network twisted pair wires. Adapter 10 comprises a number of components coupled between a host computer system bus 20 and communications network twisted pair physical media 30. A twisted pair transceiver 100 is coupled in parallel with an Attachment Unit Interface (ADI) 110 between physical media 30 and both decoder circuitry 115 and encoder circuitry 120. Decoder circuitry 115 is coupled to receive control circuitry 130, and encoder circuitry 120 is coupled to transmit control circuitry 140. Receive control circuitry 130 and transmit control circuitry 140 are coupled to each other and are both coupled to and share ethernet control circuitry 150. Ethernet control circuitry 150 may also include an interrupt timer, explained in more detail below. Receive control circuitry 130 is coupled to receive First In First Out (FIFO) circuitry 160, which is in turn coupled to a receive (RX) RAM FIFO 170. Similarly, transmit control circuitry 140 is coupled to transmit FIFO circuitry 180, which is in turn coupled to a transmit (TX) RAM FIFO 190. Receive FIFO circuitry 160 and transmit FIFO circuitry 180 are both coupled to a host interface 200 coupled to host system bus 20. Host interface 200 also includes DMA control circuitry.
The transceiver, control circuitry, and RAM discussed thus far are shown in FIG. 1 enclosed by a dotted line to indicate that this circuitry may all be contained within a single Application Specific Integrated Circuit (ASIC) 210. ASIC 210 also employs an EEPROM 220 coupled to host interface 200 to provide configuration data such as station address, and it may also optionally employ a boot PROM 230 for automatic configuration. Also contained within and employed throughout ASIC 210 are clocks 240 and network management circuitry 250 to manage various network status signals. An external voltage controlled oscillator (VCO) 270 is also coupled to decoder 115 and encoder 120 An alternative configuration for an adapter 10′ for networks carried by coaxial cable physical media 30′ rather than twisted pair physical media 30 is illustrated in FIG. 2. Adapter 10′ employs an ASIC 210′ that is substantially identical to ASIC 210, except that it uses an external coaxial transceiver 260 rather than internal twisted pair transceiver 100 Overview of Operation
All data transfer operations between adapter 10 and the host are performed preferably through programmed I/O (PIO), except that a direct memory access (DMA) mode is available as a backup for receive operations. Data is stored by the adapter as double words (4 bytes). As a data packet is received, it is copied into receive FIFO 170, An early receive threshold size is established so that any packet larger than a preselected size triggers the early receive interrupt. If adapter 10 is not provided with or programmed for early receive interrupts, or if the packet is smaller than the early receive threshold size, adapter 10 will wait until the entire packet has been received and then generate an interrupt indicating that a complet packet has been received, that is, a receive complete interrupt, to signal a driver that a complete packet is available for reading. If adapter 10 is provided with or programmed for early interrupts at a particular early receive threshold, an early receive interrupt will be generated once that number of bytes have been received. The driver may then begin reading the data, or for long packets may reprogram the early receive threshold to generate another early receive interrupt once more of the packet has been received.
The TX status register, illustrated in FIG. 35 and indicated generally by reference numeral 370, is treated as if stacked in a similar manner to the RX status register. However, it is actually implemented as a pseudo-stack comprising a register of status flags 371 and a five bit counter 372, as opposed to a true stack of status flag registers. The use of such a pseudo-stack is possible because transmission stops upon any transmission error, and does not resume until the error status is popped from the status register. Any sequence of N transmissions would therefore be a string of N−1 successful transmissions followed by the Nth transmission which may or may not have been successful. Status flags 371 store the status of the Nth transmission, and counter 372 stores N, the number of transmissions in the stack. At a new packet transmission the adapter increments counter 372 and updates flags 371 as necessary. Popping TX status register 370 results in counter 372 being automatically decremented. When the contents of TX status register 370 are accessed, if the count is greater than one, then the regular successful status bits are forced on the bus. If the count is equal to one, then the contents of status flags 371 are applied to the bus, indicating the status of the most recent transmission. If the count is equal to zero, then TX status register 370 is indicated as being empty by applying zeros to the bus.
The flags 371 are a transmission complete flag, a flag specifying whether an interrupt should be generated on successful completion of transmission, and several error flags. Whenever the driver reads TX status register 370 and the TX completed bit is set, the stack is popped, and the next TX status may be read, if any. Popping everything off this stack turns off the TX Complete interrupt bit in adapter status register 350, described above. When the completion of a packet is signalled to the host, the packet has already been discarded from TX FIFO 190. If an error occurred and the packet needs to be retransmitted, it must be copied to TX FIFO 190 again. If the error occurred while the packet was still being copied to the adapter, the host should continue copying the packet to the 720 adapter. When completely copied to the adapter, the packet will be discarded.
FIG. 4B illustrates the process by which packets are transmitted from TX FIFO 190 to the physical medium. In step 420 it is determined if the number of bytes in TX FIFO 190 is at least equal to a TX start threshold. The TX start threshold may be varied by the driver to reduce the likliehood of transmit underruns. Control remains at this step until the TX start threshold is met, at which time control passes to step 425. At step 425 the adapter begins to transmit a packet from TX FIFO 190 and continues until the entire packet has been transmitted or an error has occurred, at which point control passes to step 430. At step 430 it is determined if an error was detected during transmission. If so, control passes to step 435 at which it is determined if the error was an underrun error. If the error was an underrun error, then a “bad” CRC is intentionally generated at step 440. If the error was not an underrun, or after a bad CRC is generated, control passes to step 445 where the error status is updated, and next to step 450 where the transmitter is disabled. If at step 430 no error was detected, control passes from there to step 460, at which the transmit status is updated. Next, at step 465, the software protocol (driver) is checked to determine if whether an acknowledgement that packet transmission is complete is required. If not, control returns to start again at the loop of step 420 to await transmission of the next packet. If an acknowledgement is required, at step 470 the driver requests from the adapter an interrupt on successful completion of the next packet transmission, after which control passes to the loop of step 420.
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