Source: https://patents.google.com/patent/US9665478B2/en
Timestamp: 2019-06-18 14:14:34
Document Index: 284502801

Matched Legal Cases: ['Application No. 200380109302', 'Application No. 03790271', 'Application No. 03790271', 'Application No. 03', 'Application No. 2004', 'Application No. 2005', 'Application No. 92134378', 'Application No. 92134378']

US9665478B2 - Zone boundary adjustments for defects in non-volatile memories - Google Patents
Zone boundary adjustments for defects in non-volatile memories Download PDF
US9665478B2
US9665478B2 US11/552,227 US55222706A US9665478B2 US 9665478 B2 US9665478 B2 US 9665478B2 US 55222706 A US55222706 A US 55222706A US 9665478 B2 US9665478 B2 US 9665478B2
US11/552,227
US20070047305A1 (en
INNOVATIVE MEMORY SYSTEMS, INC.
2006-10-24 Application filed by INNOVATIVE MEMORY SYSTEMS, INC. filed Critical INNOVATIVE MEMORY SYSTEMS, INC.
2006-10-24 Priority to US11/552,227 priority patent/US9665478B2/en
2007-03-01 Publication of US20070047305A1 publication Critical patent/US20070047305A1/en
2015-12-14 First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=32468705&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US9665478(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
2017-05-30 Publication of US9665478B2 publication Critical patent/US9665478B2/en
This application is a continuation of application Ser. No. 11/114,996, filed on Apr. 26, 2005, which is a continuation of application Ser. No. 10/315,451, filed on Dec. 9, 2002. These applications are all incorporated herein by reference in their entirety for all purposes.
Such non-volatile memory systems include one or more arrays of floating-gate memory cells and a system controller. The controller manages communication with the host system and operation of the memory cell array to store and retrieve user data. The memory cells are grouped together into blocks of cells, a block of cells being the smallest grouping of cells that are simultaneously erasable. Prior to writing data into one or more blocks of cells, those blocks of cells are erased. User data are typically transferred between the host and memory array in sectors. A sector of user data can be any amount that is convenient to handle, preferably less than the capacity of the memory block, often being equal to the standard disk drive sector size, 512 bytes. In one commercial architecture, the memory system block is sized to store one sector of user data plus overhead data, the overhead data including information such as an error correction code (ECC) for the user data stored in the block, a history of use of the block, defects and other physical information of the memory cell block. Various implementations of this type of non-volatile memory system are described in the following United States patents and pending applications assigned to SanDisk Corporation, each of which is incorporated herein in its entirety by this reference: U.S. Pat. Nos. 5,172,338, 5,602,987, 5,315,541, 5,200,959, 5,270,979, 5,428,621, 5,663,901, 5,532,962, 5,430,859 and 5,712,180, and application Ser. No. 08/910,947, filed Aug. 7, 1997, and application Ser. No. 09/343,328, filed Jun. 30, 1999. Another type of non-volatile memory system utilizes a larger memory cell block size that stores multiple sectors of user data.
Since the programming of data into floating-gate memory cells can take significant amounts of time, a large number of memory cells in a row are typically programmed at the same time. But increases in this parallelism cause increased power requirements and potential disturbances of charges of adjacent cells or interaction between them. U.S. Pat. No. 5,890,192 of SanDisk Corporation, which is incorporated above, describes a system that minimizes these effects by simultaneously programming multiple pages (referred to as chunks in that patent) of data into different blocks of cells located in different operational memory cell units (sub-arrays). Memory systems capable of programming multiple pages in parallel into multiple sub-array units are described in co-pending patent application Ser. No. 09/505,555, filed Feb. 17, 2000 by Kevin Conley et al., which is incorporated by reference above, and Ser. No. 09/759,835, filed Jan. 10, 2001, by John Mangan et al., which application is expressly incorporated herein by this reference.
A number of architectures are used for non-volatile memories arrays, such as 400 (FIG. 1) or 51-58 (FIG. 3). A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference or which have been previously incorporated above: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, and 6,151,248, and Ser. No. 09/505,555, filed Feb. 17, 2000, and Ser. No. 09/667,344, filed Sep. 22, 2000.
The use of planes is discussed above in the Background. In order to improve performance by reducing programming time, a goal is to program as many cells in parallel as can reasonably be done without incurring other penalties. One implementation is the use of planes that divide the memory array into largely independent sub-arrays or units, each unit in turn being divided into a large number of blocks, as described in U.S. patent application Ser. No. 09/505,555, filed Feb. 17, 2000, by Kevin Conley et al. and Ser. No. 09/759,835, filed Jan. 10, 2001, by John Mangan et al., which are incorporated by reference above. Pages of data are then programmed at the same time into more than one of the units. Another configuration further combines one or more of these units from multiple memory chips. These multiple chips may be connected to a single bus (as shown in FIG. 2) or multiple independent busses for higher data throughput.
Although the invention has been described with respect to various exemplary embodiments, it will be understood that the invention is entitled to protection within the full the appended claims.
one or more physical memory arrays, each of said one or more physical memory arrays having a plurality of non-volatile storage elements;
programming circuitry selectable connectable to the storage elements to write data content thereto;
read circuitry connectable to the storage elements to read data content stored therein; and
erase circuitry connectable to the storage elements to erase data content stored therein, the one or more physical memory arrays each being formed of a plurality of physical blocks, wherein the storage elements within individual ones of the physical blocks are simultaneously erasable; and
a memory controller circuit that controls writing of data into addressed blocks, reading data from addressed blocks and erasing data from one or more of addressed blocks at a time, wherein the one or more physical memory arrays are subdivided by the controller into logical zones each comprised of a plurality of physical blocks by introducing logical boundaries of the one or more physical memory arrays for address translation within which logical to physical block translations are performed for the plurality of physical blocks thereof, and where the logical zones correspond to contiguous physical spaces by introducing beginning and end physical block addresses for the logical zones, wherein the memory controller circuit can adjust said logical boundaries and update said correspondence in response to identifying one or more of said physical blocks as defective based on the distribution of the identified defective physical blocks while maintaining a correspondence of physical blocks to logical zones corresponding to contiguous physical spaces.
2. The memory system of claim 1, wherein the identifying of physical blocks as defective is based on testing data.
3. The memory system of claim 2, wherein the memory controller circuit performs testing of the physical blocks in response to a signal external to said memory system.
4. The memory system of claim 2, wherein said memory controller circuit further comprises error correction code (ECC) logic and performs testing of the physical blocks in response to an error correction code result.
5. The memory system of claim 1, wherein the memory controller circuit identifies a physical block as defective based on a program verification result.
6. The memory system of claim 1, wherein the memory controller circuit identifies a physical block as defective based on an erase verification result.
7. The memory system of claim 1, wherein the memory controller circuit updates said correspondence based on minimizing the variation in the number of non-defective physical blocks in said logical zones.
8. The memory system of claim 1, wherein the memory controller circuit further includes a volatile memory in which said correspondence is maintained.
9. The memory system of claim 8, wherein the memory controller circuit additionally maintains a copy of said correspondence in non-volatile memory.
10. The memory system of claim 1, wherein in response to updating said correspondence, the memory system rewrites user data stored in a first physical block into a second physical block, wherein said first physical block is part of a first logical zone prior to said updating and is part of second logical zone subsequent to said updating, and wherein said second physical block is part of said first zone subsequent to said updating.
11. The memory system of claim 10, wherein subsequent to rewriting user data stored in a first physical block into a second physical block, the memory controller circuit further updates said correspondence on the distribution of the identified defective blocks.
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:026325/0238