Source: https://patents.google.com/patent/US6407452?oq=6%2C049%2C612
Timestamp: 2018-03-24 11:04:09
Document Index: 734714879

Matched Legal Cases: ['application No. 08', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09']

US6407452B1 - Integrated circuitry and method of restricting diffusion from one material to another - Google Patents
Integrated circuitry and method of restricting diffusion from one material to another Download PDF
US6407452B1
US6407452B1 US09611586 US61158600A US6407452B1 US 6407452 B1 US6407452 B1 US 6407452B1 US 09611586 US09611586 US 09611586 US 61158600 A US61158600 A US 61158600A US 6407452 B1 US6407452 B1 US 6407452B1
US09611586
This application is a division of Ser. No. 09/058,612, filed Apr. 10, 1998.
A semiconductor wafer in process in accordance with one aspect of the invention is indicated in FIG. 1 with reference numeral 30. Such comprises a bulk monocrystalline silicon substrate 32 having a conductive diffusion region 34 formed therein. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
An insulative dielectric layer 36 is formed over substrate 32. Exemplary materials are Si3N4, SiO2 and doped SiO2 such as borophosphosilicate glass. A contact opening 37 is formed therein to diffusion region 34. A first layer of material 45 is formed within opening 37. Example materials include electrically conductive TiN, WN, TaN, Ta, WxSiyNz, TixSiyNz, TaxSiyNz, TixAlyNz, TaxAlyNz, and mixtures thereof where “x” preferably ranges from 0.3 to 0.7, “y” ranges from 0.5 to 2.0, and “z” is equal to 1−x−y. Layer 45 is preferably deposited by chemical vapor deposition (CVD). The illustrated construction can be produced by CVD followed by a planarization process such as chemical-mechanical polishing. Some of the material of layer 45 might also adhere to the walls of contact opening 37 (not shown). Layer 45 as initially formed can be either crystalline or amorphous, with an initial amorphous structure being preferred and shown. Regardless, layer 45 is preferably subsequently annealed at a temperature of at least 300° C. for a time period sufficient to achieve a selected crystalline structure intended to densify and improve conductivity of the material (FIG. 2). Exemplary anneal conditions include a temperature range of from about 300° C. to about 1200° C. at a pressure of from about 2 mTorr to about 5 atm for a treatment time of anywhere from about 1 minute to 2 hours. Unfortunately as described above with respect to the prior art, such annealing can cause sufficient crystallization to form singular grains at various locations throughout layer 45 having grain boundaries which extend from one surface of the layer to the other, as shown.
Accordingly, the finished construction includes a contact 38 formed within opening 37 in electrical connection with diffusion region 34 through a conductive barrier layer 40. Accordingly, materials 42 and 34 constitute different first and second materials separated by a barrier layer 40 which is capable of restricting diffusion of material therebetween. Diffusion barrier layer 40 can be considered as a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same material.
a semiconductive substrate having an insulative material received thereover;
a conductive contact formed through the insulative material to the semiconductive substrate, the conductive contact comprising:
a crystalline conductive diffusion barrier layer material within the contact opening received over the semiconductive substrate;
an amorphous layer of the same conductive diffusion barrier layer material over and contacting the crystalline conductive diffusion barrier layer material; and
a conductive plugging material different from the conductive diffusion barrier layer material within the contact opening.
2. The integrated circuitry of claim 1 wherein the same material is selected from the group consisting of TiN, WN, TaN, Ta, WxSiyNz, TixSiyNz, TaxSiyNz, TixAlyNz, TaxAlyNz, and mixtures thereof.
3. The integrated circuitry of claim 1 wherein the conductive diffusion barrier layer material comprises TiN.
4. The integrated circuitry of claim 1 wherein the conductive diffusion barrier layer material comprises WN.
5. The integrated circuitry of claim 1 wherein the conductive diffusion barrier layer material comprises TaN.
6. The integrated circuitry of claim 1 wherein the conductive diffusion barrier layer material comprises Ta.
7. The integrated circuitry of claim 1 wherein the conductive diffusion barrier layer material comprises WxSiyNz.
8. The integrated circuitry of claim 1 wherein the conductive diffusion barrier layer material comprises TixSiyNz.
9. The integrated circuitry of claim 1 wherein the conductive diffusion barrier layer material comprises TaxSiyNz.
10. The integrated circuitry of claim 1 wherein the conductive diffusion barrier layer material comprises TixAlyNz.
11. The integrated circuitry of claim 1 wherein the conductive diffusion barrier layer material comprises TaxAlyNz.
12. The integrated circuitry of claim 1 wherein the semiconductive material comprises a conductive diffusion region formed within the semiconductive substrate.
13. The integrated circuitry of claim 1 wherein the semiconductive material comprises a conductive diffusion region within the semiconductive substrate to which the conductive contact electrically connects.
US09611586 1998-04-10 2000-07-07 Integrated circuitry and method of restricting diffusion from one material to another Active US6407452B1 (en)
US09058612 US6156638A (en) 1998-04-10 1998-04-10 Integrated circuitry and method of restricting diffusion from one material to another
US09611586 US6407452B1 (en) 1998-04-10 2000-07-07 Integrated circuitry and method of restricting diffusion from one material to another
US09058612 Division US6156638A (en) 1998-04-10 1998-04-10 Integrated circuitry and method of restricting diffusion from one material to another
US6407452B1 true US6407452B1 (en) 2002-06-18
ID=22017890
US09058612 Active US6156638A (en) 1998-04-10 1998-04-10 Integrated circuitry and method of restricting diffusion from one material to another
US09611586 Active US6407452B1 (en) 1998-04-10 2000-07-07 Integrated circuitry and method of restricting diffusion from one material to another
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