Source: http://www.google.com/patents/US7958312?dq=6,272,646
Timestamp: 2014-07-10 07:47:44
Document Index: 61449035

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 200680050850', 'Application No. 095142014', 'Application No. 2006800507749', 'Application No. 2006800507749', 'Application No. 200680050850', 'Application No. 095142016']

Patent US7958312 - Small and power-efficient cache that can provide data for background DMA ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsSmall and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping....http://www.google.com/patents/US7958312?utm_source=gb-gplus-sharePatent US7958312 - Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power stateAdvanced Patent SearchPublication numberUS7958312 B2Publication typeGrantApplication numberUS 11/559,069Publication dateJun 7, 2011Filing dateNov 13, 2006Priority dateNov 15, 2005Also published asEP1958070A2, US20070186057, WO2007059085A2, WO2007059085A3Publication number11559069, 559069, US 7958312 B2, US 7958312B2, US-B2-7958312, US7958312 B2, US7958312B2InventorsLaurent R. Moll, Yu Qing Cheng, Peter N. Glaskowsky, Seungyoon Peter SongOriginal AssigneeOracle America, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (82), Non-Patent Citations (51), Classifications (8), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSmall and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power stateUS 7958312 B2Abstract Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).
pre-filling a buffer/mini-cache with data;
entering a snooping-disabled mode after pre-filling; and
responding to a request from a peripheral device when in the snooping disabled mode,
wherein responding to the request comprises providing a first portion of data from the buffer/mini-cache to the peripheral device in response to a read request from the peripheral device, and
wherein the responding to the request further comprises modifying a second portion of the data in the buffer/mini-cache in response to a write request from the peripheral device, wherein the second portion is flushed in response to the write request.
2. The method of claim 1, wherein the buffer/mini-cache identifies requests that originate from the peripheral device.
3. The method of claim 1, wherein the buffer/mini-cache is on a single chip with a controller for the peripheral device.
4. The method of claim 1, wherein the buffer/mini-cache is on a single chip with a processor.
5. The method of claim 1, wherein the data that is utilized to pre-fill the buffer is provided by a processor.
6. The method of claim 1, wherein the data that is utilized to pre-fill the buffer is provided by a controller of the peripheral device.
7. The method of claim 1, wherein the data that is utilized to pre-fill the buffer is provided by the peripheral device.
one or more peripheral devices coupled to the processor; and
a buffer/mini-cache coupled to the processor and at least one of the peripheral devices;
wherein the buffer/mini-cache is configured to be pre-filled with data, and to respond, when the system is in a snooping-disabled mode after the pre-filling to a request from at least one of the peripheral devices,
wherein the buffer/mini-cache is further configured to respond to the request, by providing a first portion of data from the buffer/mini-cache to the peripheral device in response to a read request from the peripheral device, and
wherein the buffer/mini-cache is further configured to respond to the request by modifying a second portion of the data in the buffer/mini-cache in response to a write request from the peripheral device wherein the second portion is flushed after the write request.
9. The system of claim 8, wherein the buffer/mini-cache identifies requests that originate from the peripheral device.
10. The system of claim 8, wherein the buffer/mini-cache is on a single chip with a controller for the peripheral device.
11. The system of claim 8, wherein the buffer/mini-cache is on a single chip with the processor.
12. The system of claim 8, wherein the data that is utilized to pre-fill the buffer is provided by the processor.
13. The system of claim 10, wherein the data that is utilized to pre-fill the buffer is provided by the controller of the peripheral device.
14. The system of claim 8, wherein the data that is utilized to pre-fill the buffer is provided by the peripheral device. Description
CROSS REFERENCE TO RELATED APPLICATIONS Under 35 U.S.C. �120, this is a continuation Ser. No. 11/351,058, now US patent application claiming the benefit of priority to U.S. Pat. No. 7,412,570, filed Feb. 9, 2006, which claims priority to U.S. Provisional Patent Application No. 60/736,632, filed Nov. 15, 2005, U.S. Provisional Patent Application No. 60/736,736, filed Nov. 15, 2005, U.S. Provisional Patent Application 60/761,220, filed Jan. 23, 2006, U.S. Provisional Patent Application No. 60/761,925, filed Jan. 25, 2006, U.S. Pat. No. 7,516,274, filed Feb. 9, 2006, co-pending U.S. patent application Ser. No. 11/559,133, filed on even-date herewith, co-pending U.S. patent application Ser. No. 11/559,192, filed on even-date herewith, all of which are incorporated herein by reference.
FIGS. 7 a-7 f illustrate various embodiment contexts of a processor-included buffer/mini-cache.
Advanced Config.Uration And Power Interface
A first illustrative combination of a method including the steps of responding to a DMA access by referencing a data structure that is distinct from a coherency domain; when the coherency domain transitions between coherency modes, synchronizing the data structure with the coherency domain; and wherein the coherency modes include an incoherent mode and a coherent mode.
The first illustrative combination wherein the synchronizing includes at least one of flushing modified data from the data structure to the coherency domain, marking unneeded data in the data structure as available for pre-filling from the coherency domain, and pre-filling data from the coherency domain to the data structure. The first illustrative combination wherein the data structure includes at least one of a buffer and a cache. The first illustrative combination wherein the DMA access is a cacheable access. The first illustrative combination wherein the DMA access is a non-cacheable access.
The first illustrative combination wherein the DMA access is a first DMA access and further including responding to a second DMA access by referencing the coherency domain. The foregoing illustrative combination wherein the first DMA access is to a first physical address that is greater than or equal to a lower limit physical address. The foregoing illustrative combination wherein the first physical address is less than or equal to an upper limit physical address. The foregoing illustrative combination wherein the second DMA access is to a second physical address that is less than the lower limit physical address. The foregoing illustrative combination further including responding to a third DMA access by referencing the coherency domain and wherein the third DMA access is to a third physical address that is greater than the upper limit physical address.
The first illustrative combination wherein the data structure is operated according to a predetermined replacement policy. The first illustrative combination wherein the data structure is operated according to a dynamic replacement policy. The first illustrative combination wherein the data structure is operated according to an LRU replacement policy. The first illustrative combination wherein the data structure is operated according to an mru replacement policy.
The first illustrative combination wherein the data structure is operated according to a replacement policy that references replacement policy state. The foregoing illustrative combination wherein the replacement policy state advances independent of a current coherency mode of the coherency domain. The first illustrative combination wherein the data structure is operated according to a replacement policy that references replacement policy state and the replacement policy state advances dependent upon a current coherency mode of the coherency domain.
The first illustrative combination wherein the data structure is managed according to a direct map caching management technique. The first illustrative combination wherein the data structure is managed according to a set associative caching management technique. The first illustrative combination wherein the data structure is managed according to a fully associative caching management technique.
A second illustrative combination of a method including the steps of in response to a request for a coherency domain to transition from a coherent mode to an incoherent mode, enabling a memory structure to be responsive to memory accesses from a device; and after the enabling, allowing the coherency domain to transition to the incoherent mode.
The second illustrative combination wherein the device is a DMA device. The foregoing illustrative combination wherein the enabling includes determining a physical address value that is to be compared to respective physical addresses associated with each of the memory accesses. The foregoing illustrative combination wherein if one of the physical addresses is greater than or equal to the physical address value, then the respective memory access is processed by the memory structure. The foregoing illustrative combination wherein if one of the physical addresses is less than the physical address value then the respective memory access is processed by the coherency domain.
The second illustrative combination wherein each of the memory accesses having a respective physical address that is greater than or equal to a physical address value are processed by the memory structure. The foregoing illustrative combination wherein the physical address value is held in a register that is programmable by a processor implemented in the coherency domain. The foregoing illustrative combination wherein each of the memory accesses having a respective physical address that is less than the physical address value are processed by the processor.
The second illustrative combination wherein each of the memory accesses having a respective physical address that is between a lower physical address value and an upper physical address value are processed by the memory structure. The foregoing illustrative combination wherein the physical address values are held in registers that are programmable by a processor implemented in the coherency domain. The foregoing illustrative combination wherein each of the memory accesses having a respective physical address that is outside of the range between the lower and upper physical address values are processed by the processor.
The second illustrative combination wherein the enabling includes pre-filling at least a portion of the memory structure with data. The foregoing illustrative combination wherein at least one of the memory accesses is a read access; and further including providing some of the data in response to the read access.
The second illustrative combination wherein the enabling includes pre-filling at least a part of the memory structure with data; wherein at least one of the memory accesses is a write access; and further including modifying some of the data in response to the write access.
The second illustrative combination wherein the enabling includes pre-filling at least a portion of the memory structure with data; and further including in response to a request for the coherency domain to transition from the incoherent mode to the coherent mode, marking at least a sub-portion of the portion of the memory structure as available for pre-filling. The foregoing illustrative combination further including after the marking, allowing the coherency domain to transition to the coherent mode.
The second illustrative combination wherein the enabling includes pre-filling at least a sub-region of the memory structure with data, the sub-region being determined at least in part based on a programmable register value. The second illustrative combination wherein the enabling includes pre-filling at least a sub-region of the memory structure with data, the sub-region being determined at least in part based on a dynamic range determined by observation of previous memory accesses.
The second illustrative combination wherein the coherency domain is responsive to the memory accesses when the coherency domain is in the coherent mode, and the coherency domain is unresponsive to the memory accesses when the coherency domain is in the incoherent mode.
The second illustrative combination wherein the coherency domain is responsive to the memory accesses when the coherency domain is in the coherent mode, and the memory structure is responsive to the memory accesses when the coherency domain is in the incoherent mode.
Any of the first and the second illustrative combinations, wherein the coherency domain includes at least one of a processor, a cache, and a link coupled to a cache sub-system. Any of the first and the second illustrative combinations, wherein the coherent mode includes at least one of a high-power mode, a high-performance mode, and a snooping-enabled mode. Any of the first and the second illustrative combinations, wherein the incoherent mode includes at least one of a low-power mode, a low-performance mode, and a snooping-disabled mode.
A third illustrative combination of the second ic further including responding to at least one of the memory accesses by accessing the memory structure.
The third illustrative combination wherein the at least one of the memory accesses is a read. The foregoing illustrative combination wherein the accessing includes determining if read data for the read is present in the memory structure. The foregoing illustrative combination wherein if the read data is not present in the memory structure, then requesting the read data from the coherency domain.
The third illustrative combination wherein the at least one of the memory accesses is a write. The foregoing illustrative combination wherein the accessing includes determining if the memory structure has a location allocated for write data for the write. The foregoing illustrative combination further including if the memory structure lacks the location allocated for the write data, then allocating a new location for the write data in the memory structure. The foregoing illustrative combination further including storing the write data into the new location.
The third illustrative combination wherein in response to a request for the coherency domain to transition from the incoherent mode to the coherent mode, disabling the memory structure from responding to the memory accesses. The foregoing illustrative combination further including after the disabling, allowing the coherency domain to transition to the coherent mode.
The third illustrative combination wherein in response to a request for the coherency domain to transition from the incoherent mode to the coherent mode, flushing the memory structure of modified data stored since the memory structure was enabled. The foregoing illustrative combination further including after the flushing, allowing the coherency domain to transition to the coherent mode.
A fourth illustrative combination of a system including a microprocessor; and a storage structure coupled to the microprocessor; and wherein in response to a request for the microprocessor to enter a snoop-enabled state, modified data in the storage structure is flushed to the microprocessor and then the microprocessor is allowed to enter the snoop-enabled state.
A fifth illustrative combination of the foregoing illustrative combination wherein after the request and before the modified data is flushed, the storage structure is disabled from responding to accesses from a device.
A sixth illustrative combination of a system including a microprocessor; and a storage structure coupled to the microprocessor; and wherein in response to a request for the microprocessor to enter a snoop-enabled state, unmodified data in the storage structure is marked as unneeded and then the microprocessor is allowed to enter the snoop-enabled state.
A seventh illustrative combination of the foregoing illustrative combination wherein after the request and before the unmodified data is marked, the storage structure is disabled from responding to accesses from a device. The foregoing illustrative combination wherein in response to a request for the microprocessor to enter a snoop-disabled state, a portion of the data marked as unneeded is replaced with pre-fill data. The foregoing illustrative combination wherein after the portion is replaced the microprocessor is allowed to enter the snoop-disabled state. The foregoing illustrative combination wherein after the portion is replaced the storage structure is enabled to respond to accesses from a device. The foregoing illustrative combination wherein at least one of the accesses is a read access satisfied by some of the pre-fill data. The foregoing illustrative combination wherein at least another one of the accesses is a write access that modifies a part of the pre-fill data.
An eighth illustrative combination of a system including a microprocessor; a storage structure coupled to the microprocessor; and wherein in response to a request for the microprocessor to enter a snoop-disabled state, the storage structure is pre-filled with data and then the microprocessor is allowed to enter the snoop-disabled state.
A ninth illustrative combination of the eighth ic wherein after the data is pre-filled the storage structure is enabled to respond to accesses from a device. The foregoing illustrative combination wherein the accesses include a read access and a write access. The foregoing illustrative combination wherein processing the read access includes providing a portion of the data. The foregoing illustrative combination wherein processing the write access includes modifying a portion of the data.
A tenth illustrative combination of a system including a microprocessor; a storage structure coupled to the microprocessor; and wherein in response to a request for the microprocessor to enter a snoop-disabled state, the storage structure is enabled to respond to accesses from a device and then the microprocessor is allowed to enter the snoop-disabled state.
Any of the fifth, seventh, ninth, and tenth illustrative combinations further including the device. The foregoing illustrative combination wherein the device is a DMA device.
The system includes several solid-line box elements partitioned, according to various scenarios, into a variety of distinct integrated circuits (or chips), as shown by several dashed-line box elements. Three variations are illustrated by the figure. A first variation has a processor-included buffer/mini-cache (such as buffer/mini-cache 112 a) to satisfy selected non-cacheable accesses. The first variation further has a processor-external buffer/mini-cache (such as such as buffer/mini-cache 112 b) to satisfy some background DMA device accesses. A second variation has the processor-included buffer/mini-cache and lacks the processor-external buffer/mini-cache. A third variation has the processor-external buffer/mini-cache and lacks the processor-included buffer/mini-cache. In some usage scenarios buffer/mini-cache 112 a may also satisfy some background DMA device accesses. In some usage scenarios buffer/mini-cache 112 b may also satisfy selected non-cacheable accesses.
CPUs and cache(s) element 110, having one or more CPUs and associated caches and/or cache sub-systems, is coupled to (processor) control unit 130 a having buffer/mini-cache 112 a according to the first and second variations. The processor control unit is coupled via link 120 to (chipset) control unit 130 b having buffer/mini-cache 112 b according to the first and the third variations. The chipset control unit is coupled to GPU/DMA device(s) 115, (internal) DMA device(s) 132, and (external) DMA device(s) 133. Two techniques for interfacing to dram are illustrated. In the first technique, processor-centric dram controller 113 a is coupled to (processor) control unit 130 a and drams 114 a. In the second technique chipset-centric dram controller 113 b is coupled to (chipset) control unit 130 b and drams 114 b. Various embodiments may implement any combination of the dram interfacing techniques.
The partitioning scenarios include processor chip 102 implemented as a single integrated circuit having CPUs and cache(s) element 110, control unit 130 a (optionally including buffer/mini-cache 112 a according to variation), and optionally dram controller 113 a. The partitioning scenarios further include chipset 103 having control unit 130 b (optionally including buffer/mini-cache 112 b according to variation), (internal) DMA device(s) 132, and optionally dram controller 113 b implemented as another single integrated circuit. The partitioning scenarios further include integrated graphics chipset 104 having chipset 103 and GPU/DMA device(s) 115 implemented as a single chip.
The partitioning scenarios further include processor system 101 including all of the elements of processor 102 and chipset 103 implemented as a single chip. In some usage scenarios (single-chip) processor system 101 is operated in conjunction with GPU/DMA device(s) 115, (external) DMA device(s) 133, and drams 114 a or 114 b as separate chips. The partitioning scenarios further include processor and dram chip 100 including all of the elements of processor chip 102 and all or any portion of drams 114 a implemented in a single chip, multi-die, or multi-chip module. The partitioning scenarios further include integrated graphics and dram chipset 105 including all of the elements of integrated graphics chipset 104 and all or any portion of drams 114 b implemented in a single chip, multi-die, or multi-chip module. The aforementioned partitioning scenarios are illustrative only, and not limiting, as other partitioning scenarios are possible and contemplated. For example, any elements described as being implemented in a single chip may be implemented as a single integrated circuit die included in a single-module package or a multi-module package.
In some embodiments the buffer/mini-cache (whether internal to or external to the processor) is synchronized (or made coherent with) any caching structure(s) implemented in the processor (such as first- and second-level caches I1s and I2s, respectively. In some embodiments the buffer/mini-cache is kept coherent incrementally, i.e. Snooped as needed when the processor is performing accesses. In some embodiments the buffer/mini-cache is kept coherent by explicit flushes as the processor transitions from a non-snooping power state to a snooping power state. In some embodiments no explicit operations are performed to synchronize the buffer/mini-cache, i.e. It is operated incoherently with respect to any processor implemented caches. In some of the embodiments where the buffer/mini-cache is operated incoherently, system software guarantees no stale data remains in the buffer/mini-cache.
FIG. 2 illustrates selected aspects of an embodiment of either of buffer/mini-caches 112 a-b of FIG. 1 as buffer/mini-cache 112. The buffer/mini-cache includes memory structure 201 operated under the control of and accessed by state machine 202 and associated control logic in accordance with information from mode register 221. The memory structure is organized into a plurality of identical entries (or groups of identical entries, according to embodiment) as shown by lines 201.0 . . . 201.n. Each line includes one or more fields of one or more bits, as exemplified by line 201.0 having optional tag field 211, data field 212, valid bit 213, dirty bit 214, and optional cacheable bit 215. In some embodiments any combination of the dirty and cacheable bits are implemented in a single field referred to hereinafter as a status field. The status field is not limited to two bits in width, and may including three or more bits to encode a variety of line status conditions.
In some embodiments the memory structure is identical to a conventional cache (i.e. Cacheable bit 215 is not present). In some embodiments the memory structure is adapted from a conventional cache. In some embodiments allocation and replacement functions of a conventional cache are used in part to manage the memory structure. In some embodiments the memory structure is combined with a portion of CPU caches, or integrated with an outer-level cache, such as an I2 or I3 cache (see the processor-included buffer/mini-cache embodiments section elsewhere herein for more information).
After transitioning to the normal mode, the state machine begins operation in �normal operation� state 312 where non-cacheable transactions are not processed by buffer/mini-cache 112. The normal operation state is not exited until detection of one of the normal-to-buffer-mode events. Then the state machine transitions to �(normal) flush buffer/mini-cache� state 313 via �buffer mode entry event� 311, where all dirty lines (if any) are flushed from the buffer/mini-cache to memory (such as either of drams 114 a or 114 b of FIG. 1).
Operation to reduce dram accesses by processing selected non-cacheable accesses by a buffer/mini-cache (such as according to the foregoing first and third variations having a processor-external buffer/mini-cache) is as follows. After a system reset, a CPU included in CPUs and cache(s) element 110 executes software to program memory range and operational mode information in mode register 221 (of FIG. 2) to specify non-cacheable accesses to optimize. The buffer/mini-cache (such as buffer/mini-cache 112 b of FIG. 1) begins processing according to �normal operation� state 312 (of FIG. 3), and non-cacheable accesses, such as generated by GPU/DMA device(s) 115 of FIG. 1, are not processed by the buffer/mini-cache. After a programmable event has occurred (such as time spent in a low power/performance state) state machine 202 (of FIG. 2) begins to enable caching of matching non-cacheable transactions in the buffer/mini-cache by flushing all dirty lines (if any) in the buffer/mini-cache and marking all lines in the buffer/mini-cache as invalid (such as by a deasserted valid bit 213). After the buffer/mini-cache is completely flushed the buffer/mini-cache is operated in the buffer mode, and matching non-cacheable transactions are processed by the buffer/mini-cache.
A non-cacheable transaction generated by the GPU/DMA device is compared to the ranges (such as described by programmable memory range 402 of FIG. 4), and if the address of the non-cacheable transaction matches one of the ranges, then it is processed with the buffer/mini-cache (non-matching transactions are processed elsewhere, such as with either of drams 114 a or 114 b of FIG. 1). The matching non-cacheable (and in some embodiments optionally matching cacheable) transactions are processed by the buffer/mini-cache akin to processing by a conventional cache having allocation, replacement, and snooping policies. In some embodiments the allocation policy is generally set to allocate on read so that after a line has been read once from the dram the line resides in the buffer/mini-cache. In some embodiments the allocation policy includes allocating on a write or writing through.
Operation of embodiments where the buffer/mini-cache is external to the processor or included in the chipset (such as processor-external buffer/mini-cache 112 b of FIG. 1) enable the link coupling the processor and chipset to remain powered down as long as the buffer/mini-cache is servicing DMA requests, and bus and snoop logic in the processor may remain in low-power states even while the DMA requests are serviced, leading to high power savings. In usage scenarios where the buffer/mini-cache is flushed, the processor is temporarily �popped up� to a higher-power state (such as transitioning from c3, c4, c5, and so forth to c2, c1, or c0) to service write backs associated with the flush. The chipset, operating in conjunction with the processor, postpones processing memory traffic until all buffer/mini-cache modified state (dirty lines, for example) is flushed to the processor and associated coherency domain. In some embodiments the chipset is enabled to fully participate in the coherency domain (such as so-called �front-side� bus systems implemented by some x86-compatible systems). In some embodiments where the chipset fully participates in the coherency domain the buffer/mini-cache may be operated as a coherent cache and is snooped, avoiding explicit flushing.
Operation of embodiments where the buffer/mini-cache is included in the processor (such as processor-internal buffer/mini-cache 112 a of FIG. 1) power up the link coupling the processor and the chipset whenever DMA activity is to be processed in order to communicate the DMA activity from the chipset to the processor where the buffer/mini-cache resides. Thus the processor keeps at least a portion of the processor control unit powered up to respond to the DMA activity. In embodiments where the buffer/mini-cache is operated in the incoherent fashion, the buffer/mini-cache is explicitly flushed when cache systems associated with the processor become operational (such as when the processor exits a low-power or non-snooping state to a fully-operational and/or snooping state). In embodiments where the buffer/mini-cache is operated in the coherent fashion, explicit flushes are not used, although incrementally maintaining coherence results in additional power consumption.
FIG. 5 illustrates selected operations performed by an embodiment implementing a coherent buffer/mini-cache (either processor-internal such as buffer/mini-cache 112 a of FIG. 1 or processor-external such as buffer/mini-cache 112 b of FIG. 1) for satisfying background DMA device accesses. Processing is according to two major flows, one for each of a DMA read access and a DMA write access. Processing for either flow begins (�idle� 501) with a DMA access from a DMA device (�DMA received� 502), and processing continues according to the type of access (i.e. Read or write).
Processing of a DMA read (�read� 502 r) begins by determining whether the read may be satisfied by data already present in the buffer/mini-cache, such as either of buffer/mini-caches 112 a-b of FIG. 1 (�hit?� 503 r). If not (�no� 503 rn), then processing continues to determine if the buffer/mini-cache has any remaining lines available for allocation (�space available?� 504 r). If not (�no� 504 rn), then a line is selected for eviction from the buffer/mini-cache (�choose victim� 505 r). If the selected line has any modified data (�dirty� 505 rd), then the line is stored in the coherency domain (�write-back to processor� 506 r). The line then is allocated for the DMA read being processed (�reserve line� 507 r). If the line was previously not dirty (�clean� 505 rc), then no write-back is performed and the line is immediately allocated (�reserve line� 507 r). If there is a remaining line available (�yes� 504 ry), then no victim is chosen (and hence there is also no write-back) and a selected line is immediately allocated (�reserve line� 507 r).
After the line is allocated for the DMA read data, the DMA access is passed to the coherency domain for further processing (�DMA request to processor� 508 r). Data is provided by the coherency domain (such as after popping-up to a snoop-enabled state), stored in the allocated buffer/mini-cache line, and marked as �clean� and �valid� (�write; mark �clean� & �valid�� 509 r). The data is also provided to the DMA device (�data to device� 510 r), processing of the DMA access is complete, and waiting begins for a new DMA access (�idle� 501). If the buffer/mini-cache already has the data necessary to satisfy the DMA read access (�yes� 503 ry), then no miss processing is required, and data is immediately delivered to the DMA device (�data to device� 510 r), omitting line allocation and filling operations.
Processing of a DMA write (�write� 502 w) begins by determining whether a line for the write may already be allocated in the buffer/mini-cache (�hit?� 503 w). If not (�no� 503 wn), then processing continues to determine if the buffer/mini-cache has any remaining lines available for allocation (�space available?� 504 w). If not (�no� 504 wn), then a line is selected for eviction from the buffer/mini-cache (�choose victim� 505 w). If the selected line has any modified data (�dirty� 505 wd), then the line is stored in the coherency domain (�write-back to processor� 506 w). The line is then allocated for the DMA write being processed (�reserve line� 507 w). If the line was previously not dirty (�clean� 505 wc), then no write-back is performed and the line is immediately allocated (�reserve line� 507 w). If there was a remaining line available (�yes� 504 wy), then no victim is chosen (and hence there is also no write-back) and a selected line is immediately allocated (�reserve line� 507 w).
After the line is allocated for the DMA write data, the DMA write data is stored therein and marked as not clean (�write; mark �dirty�� 508 w). Processing of the DMA access is then complete, and waiting begins for a new DMA access (�idle� 501). If the buffer/mini-cache already has a line allocated for the DMA write (�yes� 503 wy), then no miss processing is required, and the DMA write data is immediately stored into the buffer/mini-cache (�write; mark �dirty�� 508 w), omitting line allocation operations.
FIG. 6 illustrates selected operations performed by an embodiment implementing an incoherent buffer/mini-cache (either processor-internal such as buffer/mini-cache 112 a of FIG. 1 or processor-external such as buffer/mini-cache 112 b of FIG. 1) for satisfying background DMA device accesses. Processing is according to two major flows, one for each of an entry to a lower-power state (�lower c-state� 600 l) and an entry to a higher-power state (�higher c-state� 600 h).
The lower-power state entry processing begins (�idle� 601) with a notification of a desired transition to a lower-power c-state (�enter lower c-state� 601 l), such as when entering a deep c-state (e.g. C3, c4, or so forth). A determination is made as to whether there are any remaining lines in the buffer/mini-cache that are available to receive system data, i.e. That have a �valid� tag and have a �free� status (�more lines?� 602 l). If so (�yes� 602 ly), then processing continues to select one of the �valid� and �free� lines (�choose line� 603 l). Data is then obtained from the coherent domain for storage into the selected line (�data from system� 604 l). The data is stored into the line and marked as clean (�write; mark �clean�� 605 l), leaving the line unavailable for additional system data, as the line is no longer �free�.
Flow then loops back to determine if there are any additional lines available in the buffer/mini-cache to receive system data (�more lines?� 602 l). If there are no additional lines available (�no� 602 ln), then the buffer/mini-cache filling in preparation for the entry into the lower-power state is complete, the buffer/mini-cache is ready to enter the lower-power state, and flow loops back to await another c-state transition (�idle� 601).
In some embodiments the processing relating to entering a reduced-power state (�lower c-state� 600 l) is omitted, i.e. There is no �pre-filling� of the buffer/mini-cache.
Processing for the entry to the higher-power state begins (�idle� 601) with a notification of a desired transition to a higher-power c-state (�enter higher c-state� 601 h), such as when entering a snoop-enabled c-state (e.g. C2, c1, or c0). A determination is made as to whether there are any remaining lines in the buffer/mini-cache that may have new data to be written back to the coherency domain, i.e. That have a status other than �free�, such as �clean� or �dirty� (�more lines?� 602 h). If so (�yes� 602 hy), then processing continues to select one of the not �free� lines (�choose line� 603 h). If the selected line has any modified data, such as indicated by a status of �dirty� (�dirty� 603 hd), then the line is stored in the coherency domain (�write-back to coherency domain� 604 h) and the line status is then changed to �free� (�mark �free�� 605 h). If the selected line has no modified data, such as indicated by a status of �clean� (�clean� 603 hc), then the write-back is omitted and the line state is immediately changed to free (�mark �free�� 605 h).
Flow then loops back to determine if there are additional lines to examine for possible new data (�more lines?� 602 h). If there are no additional lines to process (�no� 602 hn), then the buffer/mini-cache is synchronized with the coherency domain and accesses to the coherency domain may resume, the buffer/mini-cache is ready to enter the higher-power state, and flow loops back to await another c-state transition (�idle� 601).
FIGS. 7 a-7 f illustrate various embodiments of and contexts associated with a processor-included buffer/mini-cache, as relating to all or portions of processor chip 102 of FIG. 1. The Figures illustrate various arrangements of CPUs and associated cache sub-systems, including several combinations of I1, I2, and I3 cache structures. The Figures further illustrate embodiments where the processor-included buffer/mini-cache is distinct from or combined with the cache sub-system.
FIG. 7 a illustrates a variation of processor chip 102 as processor chip 102 a having four CPU and I1 units 700.0-3 coupled to control unit 130 a having processor-included buffer/mini-cache 112 a. Other elements may be included in the processor chip (such as a dram controller) but are omitted from the figure for clarity. The CPU and I1 units may individually include one or more CPUs and one or more I1 caches (such as instruction and data caches), according to various implementations. Although four CPU and I1 units are illustrated, those of ordinary skill in the art will recognize that more or fewer units may be used. In some embodiments each of the CPU and I1 units are identical, while in some embodiments one or more of the CPU and I1 units may be distinct (i.e. Have a CPU or cache with greater or lesser power or performance characteristics). In some embodiments all or portions of the buffer/mini-cache are implemented in one or more of the CPU and I1 units.
FIG. 7 b illustrates a variation of processor chip 102 as processor chip 102 b having a pair of processors 701.0-1 coupled to control unit 130 a having processor-included buffer/mini-cache 112 a. Other elements may be included in the processor chip (such as a dram controller) but are omitted from the Figure for clarity. As illustrated, each of the processors includes a pair of CPU and I1 units coupled to a shared I2 cache (such as processor 701.0 having CPU and I1 units 710.0-1 and I2 711.0). The I2 caches are in turn coupled to the control unit to exchange data with the buffer/mini-cache. Although a pair of processors each having a pair of CPUs is illustrated, those of ordinary skill in the art will recognize that more or fewer CPUs may be used in each processor, and more or fewer processors may be used. In some embodiments each of the processors are identical, while in some embodiments one or more of the processors may be distinct (such as having more or fewer CPUs). In some embodiments each of the CPU and I1 units are identical, while in some embodiments one or more of the CPU and I1 units may be distinct (i.e. Have a CPU or cache with greater or lesser power or performance characteristics).
FIG. 7 c illustrates a variation of processor chip 102 as processor chip 102 c that is similar to processor chip 102 b (of FIG. 7 b), except the I2 cache resource is a single unit (I2 711) in single processor 701. Other elements may be included in the processor chip (such as a dram controller) but are omitted from the Figure for clarity. As in embodiments illustrated in FIGS. 7 a and 7 b, the number, arrangement, and characteristics of CPUs and I1s may vary according to embodiment.
FIG. 7 d illustrates a variation of processor chip 102 as processor chip 102 d that is similar to processor chip 102 c (of FIG. 7 c), except that the I2 and the buffer/mini-cache have been combined. Control unit 130 d is similar to control unit 130 a except that it is adapted to manage buffer/mini-cache 112 d as implemented by inclusion in I2 711 d, that is in turn similar to I2 711 except for inclusion of the buffer/mini-cache. In some embodiments the inclusion of the buffer/mini-cache is implemented by reserving a portion of the I2 for use as a buffer/mini-cache. The reserving may be according to a number or identification of ways in the I2, or any other similar mechanism (see the reduction of dram accesses by non-cacheable accesses section elsewhere herein for more information). As in embodiments illustrated in FIGS. 7 a-7 c, other elements may be included in the processor chip, and the number, arrangement, and characteristics of CPUs and I1s may vary according to embodiment.
FIG. 7 e illustrates a variation of processor chip 102 as processor chip 102 e that is similar to processor chip 102 b (of FIG. 7 b), except that an additional layer of cache is inserted between the CPUs and the buffer/mini-cache as I3 720. As in embodiments illustrated in FIGS. 7 a-7 d, other elements may be included in the processor chip, and the number, arrangement, and characteristics of CPUs, I1s, and I2s may vary according to embodiment.
FIG. 7 f illustrates a variation of processor chip 102 as processor chip 102 f that is similar to processor chip 102 e (of FIG. 7 e), except that the I3 and the buffer/mini-cache have been combined. Control unit 130 f is similar to control unit 130 a except that it is adapted to manage buffer/mini-cache 112 f as implemented by inclusion in I3 720 f, that is in turn similar to I3 720 except for inclusion of the buffer/mini-cache. Similar to embodiments illustrated by FIG. 7 d, the inclusion of the buffer/mini-cache may be implemented by reserving a portion of the I3 for use as a buffer/mini-cache. The reserving may be according to a number or identification of ways in the I3, or any other similar mechanism (see the reduction of dram accesses by non-cacheable accesses section elsewhere herein for more information).
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No. 11/751,973, mailed on Oct. 6, 2010 (11 pages).Classifications U.S. Classification711/135, 711/146, 710/56International ClassificationG06F12/00Cooperative ClassificationG06F1/3225, G06F12/0835European ClassificationG06F12/08B4P4P, G06F1/32P1C6Legal EventsDateCodeEventDescriptionAug 23, 2011ASAssignmentFree format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 020957 FRAME 0434. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT ASSIGNEES ARE SUN MICROSYSTEMS, INC. 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