Source: http://www.google.com/patents/US5616942?dq=%235,519,867
Timestamp: 2017-03-25 09:07:45
Document Index: 687761929

Matched Legal Cases: ['art(11', 'art(12', 'art(11', 'art(12', 'art(11', 'art(11', 'art(12', 'art(12']

Patent US5616942 - Flash EEPROM cell and manufacturing methods thereof - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThis invention relates to a flash EEPROM(Electrically Erasable Programmable Read-Only Memory) cell, more particularly to the cell having an inverter structure with an n-channel part and a p-channel part which hold a floating gate in common, in which the floating gate is charged with hot electrons produced...http://www.google.com/patents/US5616942?utm_source=gb-gplus-sharePatent US5616942 - Flash EEPROM cell and manufacturing methods thereofAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS5616942 APublication typeGrantApplication numberUS 08/622,757Publication dateApr 1, 1997Filing dateMar 27, 1996Priority dateMar 28, 1995Fee statusPaidPublication number08622757, 622757, US 5616942 A, US 5616942A, US-A-5616942, US5616942 A, US5616942AInventorsBok N. SongOriginal AssigneeHyundai Electronics Industries Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (47), Classifications (9), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetFlash EEPROM cell and manufacturing methods thereof
US 5616942 AAbstract
This invention relates to a flash EEPROM(Electrically Erasable Programmable Read-Only Memory) cell, more particularly to the cell having an inverter structure with an n-channel part and a p-channel part which hold a floating gate in common, in which the floating gate is charged with hot electrons produced in the n-channel part in programming and the floating gate is neutralized or inverted with hot holes produced in the p-channel part in erasing.
1. A flash EEPROM cell, comprising:a first source and a first drain formed in a p-type silicon substrate: a second source and a second drain formed in an n-well of said p-type silicon substrate, with said second source connecting to said first drain; a first tunnel oxide and a second tunnel oxide formed on said p-type silicon substrate between said first source and said first drain, and said p-type silicon substrate between said second source and said second drain respectively; a first floating gate and a second floating gate formed on said first and second tunnel oxides, respectively, wherein said first floating gate is connected to said second floating gate; a first insulating film and a second insulating film formed on said first and second floating gates, respectively; and a first control gate and a second control gate formed on said first and second insulating films, respectively, with said first control gate connecting to said second control gate. Description
This invention relates to a flash EEPROM(Electrically Erasable Programmable Read-Only Memory) cell, and manufacturing methods thereof, more particularly to the cell having an inverter structure with an n-channel part and a p-channel part which hold a floating gate in common.
In a non-volatile memory cell like a flash EEPROM(referred to as the cell below), one of the most severe disadvantages is that the time to be taken to erase the cell is much longer than the time to be taken to program same cell for example, about 1,000 times. In programming the cell, as a physical phenomenon so called "hot carrier injection" that has a high efficiency for the program is used it takes only several tens of micro(μ) seconds. However, due to the use of tunneling mechanism with very low efficiency, several tens of milli(m) seconds are required in an erasing stage. So the difference of the required time between program and erasure is at least 1000 times so that it results in severe asymmetry in time to be required to program and erase information. And also a thin insulating film of thickness of about 100Åthat is required for tunneling becomes another barrier in view of reliability.
It is an object of the present invention to provide a flash EEPROM cell and method of manufacturing the same which can solve the above shortcomings. Another object of the invention is that it provides a flash EEPROM cell having an inverter with an n-channel part and a p-channel part holding a floating gate in common, in which the floating gate is charged with hot electrons produced in the n-channel part in programming and the floating gate is neutralized or inverted with hot holes produced in the p-channel part in erasing.
FIGS. 1A through 1C are cross-sectional views for explaining the method of manufacturing an EEPROM cell in accordance with the present invention.
Vfg=K ×Vcg+Qn/Ct                                     (equation 1)
Vtn=K ×Vtxn+Qn/Ct                                    (equation 2)
where, Vfg is a potential that is induced to the floating gate by charge coupling, Vcg is a voltage applied to the control gate, Qn is total charges stored the floating gate by programming(Qn<0), Vtn is a threshold voltage of the n-channel part in the floating gate, Vtp is a threshold voltage of the p-channel part in the floating gate, Vtxn is a threshold voltage of the n-channel part in the control gate, Vtxp is a threshold voltage of the p-channel part in the control gate, Ct is a parallel capacitance of Cp(capacitance between the control gate and the floating gate) and Cox(capacitance between the floating gate and the silicon substrate), and K is a coupling ratio(Cp/Ct).
Referring FIG. 3C, as bias conditions for a read operation of the cell, when ground potential(Vss) is applied to the source(9A) of the n-channel part(11), about 2.5 Volt is applied to the control gate(7A), the control gate(7B) of the p-channel part(12) is set to about 2.5 Volt, and the source(9B) and the pickup region(13) are set to 5 Volt, then data stored in the cell can be read. That is, as shown in FIGS. 4A and 4B, in case that the n-channel part(11) and the p-channel part(12) compose an inverter in the cell, a read operation is as below. Assuming that the n-channel part(11) was programmed, the n-channel part(11) is turned off and the the p-channel part(12) is strongly turned on in a read operation, whereby a capacitor(CLoad) is charged with p-channel cell current(Ip) so that an output(Vout) becomes a high level of 5 Volt. On the contrary, assuming that the p-channel part(12) in FIG. 4B was programmed, the output(Vout) becomes a low level of 0 Volt with n-channel cell current(In). As a result, a very high driving capability of the inverter makes it possible to read out data at high speed.
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