Source: http://www.google.com/patents/US7457994?dq=U.S.+Patent+No.+4,528,643)
Timestamp: 2016-02-12 21:49:13
Document Index: 387810133

Matched Legal Cases: ['art 1', 'Application No. 06023616', 'Application No. 06023617', 'Application No. 06023620', 'Application No. 06023621', 'Application No. 06023629', 'Application No. 06023630', 'Application No. 06023631', 'Application No. 06023632', 'Application No. 06023633', 'Application No. 06023634', 'Application No. 8']

Patent US7457994 - Coding apparatus and decoding apparatus for transmission/storage of ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality...http://www.google.com/patents/US7457994?utm_source=gb-gplus-sharePatent US7457994 - Coding apparatus and decoding apparatus for transmission/storage of information using synchronization codeAdvanced Patent SearchPublication numberUS7457994 B2Publication typeGrantApplication numberUS 11/418,105Publication dateNov 25, 2008Filing dateMay 5, 2006Priority dateSep 29, 1995Fee statusLapsedAlso published asUS6493838, US7051248, US7093170, US7441161, US7441162, US7469364, US7506221, US20030046634, US20030066007, US20030066008, US20060195763, US20060195764, US20060200725, US20060206785, US20060206786, US20060206787, US20060206788, US20060218462, US20060218463, US20060218473Publication number11418105, 418105, US 7457994 B2, US 7457994B2, US-B2-7457994, US7457994 B2, US7457994B2InventorsYoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi NagaiOriginal AssigneeKabushiki Kaisha ToshibaExport CitationBiBTeX, EndNote, RefManPatent Citations (47), Non-Patent Citations (16), Classifications (54), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetCoding apparatus and decoding apparatus for transmission/storage of information using synchronization code
US 7457994 B2Abstract
With these problems in mind, therefore, it is the first object of the present invention to provide a coding and/or decoding apparatus, which can solve such a problem, as pseudo-synchronization or synchronization-loss, due to erroneous detection of the synchronization code, when combined with the resynchronization method which uses both the error correction and/or detection code and the synchronization code.
After the synchronization code 301 has been outputted to the output bitstream 205, the picture header 302, the prediction mode information 303, the motion vector information 304, and the residual DCT coefficients 305 are coded as follows: First, bits are inserted into the bitstream 201 outputted by the multiplexer 111 by the bit inserter 211 in order to prevent the generation of the pseudo-synchronization. In other words, when a bit pattern the same as that of the code word of the synchronization code 301 exists in the output bitstream 205, since the synchronization code 301 cannot be decoded unequivocally, bits are inserted according to the necessity. For instance, if the synchronization code 301 is a code word in which the sync_0_len bits of “0” are arranged continuously as shown in FIG. 6, it is possible to prevent the pseudo-synchronization by inserting “1” in such a way, that “0” will not be continued beyond the sync_0_len bits in the bitstream, except at the synchronization code 301.
For instance, when the synchronization code word is that as shown in FIG. 6 and further when the bits are inserted by the bit inserter 211 at “0000 . . . ” portion of the first sync_len bits in such a way that the Hamming distance from the synchronization code is more than (2*n+1), the number (−n0) of “1” in {sync_0_len−(2*n+1)} bits beginning from the synchronization code insertion position is counted, when n0 is less than 2*n+1, bits of (2*n+1−n0) are removed. Here, however, since the insertion bits are determined as “1”, when the bit decided by the insertion bit remover 905 as the insertion bit is “0”, this is regarded as that an error is mixed in the synchronization code insertion block. In this case, therefore, the error detection signal 804 is outputted.
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