Source: https://patents.google.com/patent/CN101013724A/en
Timestamp: 2020-08-03 15:01:47+00:00
Document Index: 35488694

Matched Legal Cases: ['art 213', 'art 213', 'art 213', 'arts 213', 'art 213', 'art 213', 'art 213', 'art 213', 'art 213', 'art 213', 'art 213', 'art 213', 'art 213', 'art 213', 'art 213', 'art 100', 'art 213', 'art 213', 'art 213', 'arts 213', 'art 213', 'art 213', 'art 213', 'art 213', 'art 213', 'art 213', 'art 213', 'arts 213', 'art 213', 'art 213', 'art 213', 'arts 213', 'art 213', 'art 213']

CN101013724A - Semiconductor device having super junction structure and method for manufacturing the same - Google Patents
Semiconductor device having super junction structure and method for manufacturing the same Download PDF
CN101013724A
CN101013724A CNA2007100073746A CN200710007374A CN101013724A CN 101013724 A CN101013724 A CN 101013724A CN A2007100073746 A CNA2007100073746 A CN A2007100073746A CN 200710007374 A CN200710007374 A CN 200710007374A CN 101013724 A CN101013724 A CN 101013724A
CNA2007100073746A
CN101013724B (en
宫岛健
2006-01-31 Priority to JP2006023145 priority Critical
2006-01-31 Priority to JP023145/2006 priority
2006-03-09 Priority to JP063833/2006 priority
2006-03-09 Priority to JP2006063833A priority patent/JP5076335B2/en
2006-12-05 Priority to JP2006328397A priority patent/JP5217158B2/en
2006-12-05 Priority to JP328397/2006 priority
2007-01-31 Application filed by 株式会社电装 filed Critical 株式会社电装
2007-08-08 Publication of CN101013724A publication Critical patent/CN101013724A/en
2013-07-17 Publication of CN101013724B publication Critical patent/CN101013724B/en
238000005755 formation Methods 0.000 claims description 34
XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound 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[Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 62
Semiconductor device and manufacture method thereof with super-junction structure
The present invention relates to a kind of method with semiconductor device and semiconductor device that manufacturing has super-junction structure of super-junction structure.
The substrate of super node MOSFET is by a kind of PN post repeatedly is set to constituting in transistor formation region, and is for example disclosed in JP-A-2004-146689.As its result, compare with conventional MOSFET, can reduce conducting resistance and can carry out high-speed transitions by reducing drift resistance.
Although can carry out high-speed transitions, from conducting state when cut-off state is changed, the electric current between drain electrode and the source electrode can interrupt suddenly.Therefore, the voltage sharp increase between drain electrode and the source electrode, thereby take place as puncture robustness (breakdown robustness amount) to degenerate, produce problems such as radio noise.
In addition, the MOSFET with super-junction structure for example discloses in US patent application publication No.2005-0035401.This super-junction structure is to constitute by right N type impurity range and the p type impurity district of formation PN post alternately is set.Compare with conventional MOSFET, reduced conducting resistance and can carry out high-speed transitions by reducing drift resistance.
Yet in this super node MOSFET, the PN post is to depleted immediately.Therefore, compare with conventional MOSFET, although under high voltage operation, can carry out high-speed transitions, from conducting state when cut-off state is changed, the electric current between drain electrode and the source electrode can interrupt suddenly.Therefore, the voltage between drain electrode and the source electrode increases greatly, thus take place as produce radio noise, puncture that robustness is degenerated, degradation problem under the recovery characteristics.
Therefore, need a kind of semiconductor device, in rapid rising that can deboost when cut-off state is changed from conducting state.
In view of the above problems, the purpose of this invention is to provide a kind of semiconductor device with super-junction structure.Another object of the present invention provides the method that a kind of manufacturing has the semiconductor device of super-junction structure.
According to first scheme of present disclosure, the semiconductor device with super-junction structure comprises: a plurality of first posts that have first conduction type and extend in direction of current flow; With a plurality of second posts that have second conduction type and extend in direction of current flow.First post and second post alternately are provided with on alternately (alternating) direction perpendicular to direction of current flow, thereby super-junction structure is provided.Each first post provides drift layer, is used to make electric current to flow through under the situation of conducting state.First post and second post have the border between first post and second post, depletion layer extends from this border under the situation of cut-off state.In first post and second post at least one has impurity dose, and this impurity dose is different but uneven along with the position on alternating direction.
When this device from conducting state when cut-off state is changed, the time that exhausts first and second posts fully at alternating direction along with the position is different but devious.Therefore, when device was transformed into cut-off state, voltage was beated and has been reduced.
According to the alternative plan of present disclosure, the semiconductor device with super-junction structure comprises: a plurality of first posts that have first conduction type and extend in direction of current flow; With a plurality of second posts that have second conduction type and extend in direction of current flow.First post and second post alternately are provided with on perpendicular to the alternating direction of direction of current flow, thereby super-junction structure is provided.Each first post provides drift layer, is used to make electric current to flow through under the situation of conducting state.First post and second post have the border between first post and second post, depletion layer extends from this border under the situation of cut-off state.In first post and second post at least one has impurity dose, and this impurity dose is different but uneven along with the position on direction of current flow.
When this device from conducting state when cut-off state is changed, the time that exhausts first and second posts fully in direction of current flow along with the position is different but devious.Therefore, when device was transformed into cut-off state, voltage was beated and has been reduced.
According to third party's case of present disclosure, the method that is used to make the semiconductor device with super-junction structure comprises: preparation has the Semiconductor substrate of first conduction type; Form a plurality of grooves in this substrate, wherein each groove has the constant width along first direction, and wherein comprises first distance and second distance at least along the distance between two adjacent grooves of first direction; Formation has the epitaxial film of second conduction type on substrate, thereby fills these grooves with this epitaxial film; And a side of the substrate that forms epitaxial film on it carried out planarization.
Said method provides semiconductor device, has wherein reduced voltage when this device is transformed into cut-off state and has beated.
According to the cubic case of present disclosure, the semiconductor device with super-junction structure comprises: a plurality of first posts that have first conduction type and extend in direction of current flow; With a plurality of second posts that have second conduction type and extend in direction of current flow.First post and second post alternately are provided with on perpendicular to the alternating direction of direction of current flow, thereby super-junction structure is provided.Each first post provides drift layer, is used to make electric current to flow through under the situation of conducting state.First post and second post have the border between first post and second post, depletion layer extends from this border under the situation of cut-off state.In first post and second post each has the stripe-shape plane figure on the plane perpendicular to direction of current flow.In first post and second post at least one has bridging part, and this bridging part connects one first or second post and the first or second adjacent post.
When this device from conducting state when cut-off state is changed, the time that exhausts first and second posts fully is along with the position is different but devious.Therefore, when device was transformed into cut-off state, voltage was beated and has been reduced.
According to the 5th scheme of present disclosure, the method that is used to make the semiconductor device with super-junction structure comprises: preparation has the Semiconductor substrate of first conduction type; In this substrate, form a plurality of grooves, wherein each groove has the constant width along first direction, wherein these grooves have constant distance between two grooves adjacent along first direction, and wherein each groove extends discontinuously in the second direction perpendicular to first direction; Formation has the epitaxial film of second conduction type on substrate, thereby fills these grooves with this epitaxial film.
Said method provides semiconductor device, has wherein reduced voltage when this device is transformed into cut-off state and has beated.In addition, because these grooves have constant distance between adjacent two grooves, and each groove extends discontinuously in second direction, can prevent that therefore trench wall from tilting.
To make above-mentioned and other purposes, feature and advantage of the present invention become more apparent from reference to the accompanying drawings detailed description.In the accompanying drawing:
Fig. 1 is the profile that illustrates according to the semiconductor device of first execution mode;
Fig. 2 illustrates the profile that the part of the super-junction structure of device shown in Fig. 1 is amplified;
Fig. 3 is the curve that is illustrated in the voltage waveform in the device shown in Figure 1 and current waveform under the change over condition;
Fig. 4 is the profile that illustrates according to the semiconductor device of second execution mode;
Fig. 5 is the profile that the part amplification of the super-junction structure in the device shown in Figure 4 is shown;
Fig. 6 is the profile that illustrates according to the semiconductor device of the 3rd execution mode;
Fig. 7 is the profile that the part amplification of the super-junction structure in the device shown in Fig. 6 is shown;
Fig. 8-the 11st, the profile of the manufacture method of explanation semiconductor device shown in Figure 6;
Figure 12 is a profile of explaining another manufacture method of semiconductor device shown in Figure 6;
Figure 13 illustrates the profile that amplifies according to the part of the super-junction structure in the semiconductor device of the 4th execution mode;
Figure 14 illustrates the profile that the part of the depletion layer of the super-junction structure among Figure 13 is amplified;
Figure 15 illustrates the profile that amplifies according to the part of the super-junction structure in the semiconductor device of the remodeling of the 4th execution mode;
Figure 16 is the profile that illustrates according to first second half conductor device of retrofiting of the 3rd execution mode;
Figure 17 is the perspective view that illustrates according to second second half conductor device of retrofiting of the 3rd execution mode;
Figure 18 is the curve that the deviation and the relation between the puncture voltage of impurity surface concentration are shown;
Figure 19 is the profile that illustrates as the semiconductor device of the Comparative Examples of first execution mode;
Figure 20-the 22nd illustrates the profile that the part of the depletion layer in the device shown in Figure 19 is amplified;
Figure 23 is illustrated in the voltage waveform of device shown in Figure 19 under the change over condition and the curve of current waveform;
Figure 24 is the profile that illustrates according to the semiconductor device of the 5th execution mode;
Figure 25 is the profile that the device of the line XXV-XXV intercepting in Figure 24 is shown;
Figure 26 A and 26B are the profiles that the depletion layer in the device shown in Figure 25 is shown;
Figure 27 A and 27B are the profiles that illustrates as the depletion layer in the semiconductor device that does not have bridging part of the Comparative Examples of the 5th execution mode;
Figure 28-29 and 31-32 are the profiles that the method for device shown in Figure 25 is made in explanation;
Figure 30 is the perspective view of the manufacture method of explanation device shown in Figure 25;
Figure 33 is the profile that illustrates according to the semiconductor device of the 6th execution mode; And
Figure 34 is the perspective view that illustrates as the semiconductor device that does not have bridging part of the Comparative Examples of the 5th execution mode.
To introduce with reference to the accompanying drawings below and embody first execution mode of the present invention.
Fig. 1 is the longitudinal sectional drawing of the semiconductor device in the present embodiment.This semiconductor device is vertical MOS FET, and electric current is vertically flowing.That is, vertically be the flow direction of electric current, and laterally be perpendicular to the direction of the flow direction of electric current.
Silicon layer 2 is formed on N +On the silicon substrate 1, and N type silicon layer 3 is formed on the silicon layer 2.Constitute Semiconductor substrate by this laminated structure.In the silicon layer 2 of Semiconductor substrate, be adjacent in the horizontal and the N type impurity range (N post) 4 that alternately is arranged on longitudinal extension and same in the p type impurity district of longitudinal extension (P post) 5.Post is made of N type impurity range 4 and p type impurity district 5 (PN post to).Therefore, form super-junction structure.When conducting state, the N type impurity range 4 of PN post centering becomes drift layer, and has electric current to flow.When cut-off state, depletion layer is from the interface expansion in N type impurity range 4 and p type impurity district 5.
In above-mentioned N type silicon layer 3, form the channel formation region 6 of P type, so that reach p type impurity district 5.N type source region 7 is formed in the surface layer part in the P type channel formation region 6.In the part that is used for exposing the P type channel formation region 6 on the upper surface of N type silicon layer 3, the gate oxide film 8 that passes as gate insulating film forms grids 9.With silicon oxide film 10 cover gate 9.On the upper surface of N type silicon layer 3, form source electrode 11.This source electrode 11 is electrically connected to source region 7 and channel formation region 6.Drain electrode 12 is formed on N +On the lower surface of silicon substrate 1 (rear surface).
Be set to earth potential and apply under the state of positive potential for drain electrode 12 at source electrode 11, make transistor turns by applying positive potential for grid 9.When the transistor turns state, as shown in Figure 1, electric current 12 passes N from draining +Part (inversion layer) and source region 7 relative with grid 9 in silicon substrate 1, N type impurity range 4, N type district (3), the channel formation region 6 flow to source electrode 11.
On the other hand, when when grid 9 was set to earth potential, this transistor ended from transistor turns state (wherein source electrode 11 is set to earth potential, and drain electrode 12 is set to positive potential, and grid 9 is set to the state of positive potential).As shown in Figure 2, depletion layer is from the expansion at the interface in N type impurity range 4 and p type impurity district 5.
Here, in the present embodiment, the PN post in the transistorized active area (transistor formation region) in the Semiconductor substrate right laterally in impurity dose be uneven on diverse location.That is, the total amount (dosage) of the impurity in two zones 4,5 transversely is according to the different differences that are set in position.Particularly, in Fig. 1, the width W 4 of each N type impurity range 4 is set to constant, and the width W 5 in each p type impurity district 5 also is set to constant.The impurity concentration of N type impurity range 4 is set to three classes: N1, N2, N3, and the impurity concentration in p type impurity district 5 is set to three classes: P1, P2, P3.
Like this, the width W 4 of each N type impurity range 4 equally is provided with, and the width W 5 in each p type impurity district 5 also equally is provided with.In addition, the impurity concentration in the impurity concentration of N type impurity range 4 and p type impurity district 5 differently is provided with according to transversely position.The right impurity dose of PN post like this, transversely is uneven according to the position.
Therefore, as shown in Figure 2, the expansion rate of the depletion layer shown in the with dashed lines is according to the difference of impurity concentration and difference (concentration is low more, and expansion rate is fast more) in the figure, and the balance of the P type and the impurity dose of N type is different and different according to the position.Therefore, being used for exhausting fully the right time of PN post is different in surface (laterally), and prevents that all PN posts from ending simultaneously.The result is, as shown in Figure 3, reduced in the change rate (dI/dt) when conducting state is converted to cut-off state with respect to the electric current I ds between drain electrode and the source electrode, and can stop from conducting state when cut-off state is changed, drain and source electrode between the jumping of voltage Vds increase (jumping-up).
Figure 19 is the longitudinal sectional drawing of the super node MOSFET that is used for contrasting.In Figure 19, only a kind of PN post that is made of the p type impurity district (P post) 5 of N type impurity range (the N post) 4 of impurity concentration N1 and impurity concentration P1 is to being arranged in the active area (transistor formation region).Super-junction structure by the PN post of same structure (N1 and P1) to constituting, and and location independent.From transistorized conducting state when cut-off state (turn-off time) is changed, as shown in figure 20, after beginning to exhaust shaping, advance similarly each post centering to exhaust shaping.As shown in figure 21, further exhaust shaping similarly each post centering.As shown in figure 22, finish simultaneously each post centering and exhaust shaping.In this operation, as shown in figure 23, from conducting state when cut-off state is changed, very big with respect to the change rate (dI/dt) of electric current between drain electrode and the source electrode, and the jumping that has produced the voltage Vds between drain electrode and the source electrode increases.
In contrast to this, in the present embodiment, super-junction structure is that N type impurity range (the N post) 4 of N1, N2, N3 and p type impurity district (P post) that impurity concentration is P1, P2, P3 5 constitute by impurity concentration.Therefore, super-junction structure by two kinds or above PN post to constituting.Like this, can form the right multiple combination of adjacent PN post, and the balance of the P type and the impurity dose of N type is according to the position in the active area (transistor formation region) and different.Like this, from transistor turns state (deadline) when cut-off state is changed, be used for exhausting fully the right time of PN post in transistor forms face (laterally), can be offset.Therefore, prevented that all crystals pipe unit from being ended simultaneously.Like this, as shown in Figure 3, can when switching, cut-off state stop the voltage Vds jumping between drain electrode and the source electrode to increase from conducting state.That is, by using impurity dose different two kinds or above PN post that the time that exhausts shaping fully is offset in active area.Therefore, reduced with respect to the change rate (dI/dt) of electric current I ds between drain electrode and the source electrode, and can prevent to drain and source electrode between voltage Vds jump and increase.
According to above-mentioned execution mode, can obtain following effect.
In having the semiconductor device of super-junction structure (vertical MOS FET), the right impurity dose of the horizontal post in the active area of semiconductor device is according to the position but uneven.Correspondingly, being used for exhausting fully the post that is made of N type impurity range 4 and p type impurity district 5 was offset from conducting state (during shutoff) when cut-off state is changed in the horizontal to time of (PN post to).Therefore, may be limited to from the jumping of conducting state voltage when cut-off state is changed and increase.
In addition, in general power MOSFET, increase resistance, the radio noise that produces when changing to be limited in, thereby make grid input waveform to handling this insensitive for noise.Yet, increased the heat that produces, and limited the compactness of product.In addition, in super node MOSFET, the voltage when exhausting formation fully jumps to increase becomes problem.Therefore, only can not take any measure to radio noise by gate waveform control.In contrast to this, by making the right impurity dose of post according to the position and difference, can reduce the radio noise in the super knot element.In addition, under the situation of the heat that does not increase generation, can realize this minimizing.
Introduce second execution mode with the difference that is different from first execution mode as emphasis below.
Fig. 4 is the longitudinal sectional drawing of semiconductor device that replaces the present embodiment of Fig. 1.This semiconductor device also is vertical MOS FET, and has super-junction structure.
The width W 4 of each N type impurity range 4 is set consistently, and the width W 5 in each p type impurity district 5 also is set consistently.The impurity concentration of N type impurity range 4 is set to three kinds: N1, N2, N3, and the impurity concentration in p type impurity district 5 is set to a kind of P1.That is, Fig. 4 is different from Fig. 1 part and is: the concentration of N type impurity range (N post) 4 is three kinds: N1, N2, N3, and the concentration of p type impurity district (P post) 5 is a kind of P1.
Like this, the width W 4 of each N type impurity range 4 is set equally, and the width W 5 in each p type impurity district 5 equally is set.In addition, the impurity concentration in each p type impurity district 5 is set equally, the impurity concentration of N type impurity range 4 differently is provided with according to transversely position.Like this, the right impurity surface concentration transversely of post is different on diverse location.
Thus, as shown in Figure 5, from transistorized conducting state (during shutoff) when cut-off state is changed, for expansion by the depletion layer shown in the dotted line among this figure, exhaust fully the PN post right the time be engraved in transistor and form that face (laterally) is interior can be offset.Therefore, may be limited to from the jumping of conducting state voltage when cut-off state is changed and increase.
Like this, can also only change the impurity concentration of N type impurity range (N post) 4, perhaps can also only change the impurity concentration in p type impurity district (P post) 5.
To introduce the 3rd execution mode as emphasis with the distinctive points that is different from first execution mode below.
Fig. 6 is the longitudinal sectional drawing that replaces the semiconductor device of 1 present embodiment.This semiconductor device also is vertical MOS FET, and has super-junction structure.
The impurity concentration of N type impurity range 4 is set to a kind of N1, and the impurity concentration in p type impurity district 5 is set to a kind of P1.The width W 5 in each p type impurity district 5 is set consistently, and the width W 4 of N type impurity range 4 is set to three kinds.
Like this, the impurity concentration of each N type impurity range 4 is set equally, and the impurity concentration in each p type impurity district 5 also equally is set.In addition, the width W 5 in each p type impurity district 5 is set equally, and the width W 4 of N type impurity range 4 is provided with differently according to transversely position.Therefore, the right impurity surface concentration transversely of post is according to the position but uneven.
Thus, as shown in Figure 7,,, exhaust the right moment of PN post fully can in transistor forms face (laterally), be offset for expansion by the depletion layer shown in the dotted line among this figure from transistorized conducting state (during shutoff) when cut-off state is changed.Therefore, may be limited to from the jumping of conducting state voltage when cut-off state is changed and increase.
Next, the manufacture method that explanation is had the Semiconductor substrate of this super-junction structure.
As shown in Figure 8, preparation is as the N type silicon wafer 20 of N type semiconductor substrate.As shown in Figure 9, carry out ion etching with respect to wafer 20, form groove 22 by in wafer surface, using mask 21.When forming this groove, (consistently) is provided with the recess width Wt of groove 22 equably, and all the other width Ws be set to two kinds or more than.
Afterwards, as shown in figure 10, on N type silicon wafer 20, form P type epitaxial film 23, and bury groove 22 with epitaxial film 23.Then, to first type surface one side (a top side) of N type silicon wafer 20, promptly upper surface one side of epitaxial film 23 is polished and planarization.Carry out this polishing, till exposing silicon wafer 20.In addition, as shown in figure 11, on the upper surface of N type silicon wafer 20, form N type epitaxial film 24.By can also forming N type surface silicon layer in the upper surface that ion is injected into N type silicon wafer 20, rather than on the upper surface of N type silicon wafer 20, form N type epitaxial film 24.
In addition, the rear surface (lower surface) of N type silicon wafer 20 is polished, till near groove 22, and with N +Silicon substrate bonds on this burnishing surface.Can also be by injecting ion with N from the rear surface (lower surface) of N type silicon wafer 20 +Silicon layer is formed on the rear surface of N type silicon wafer 20, and need not polish the rear surface and the bonding silicon substrate of N type silicon wafer 20.
Vertical MOS FET shown in Figure 6 is by utilizing the Semiconductor substrate (Semiconductor substrate with super-junction structure) that forms by this way to make.That is, form P type channel formation region 6, N type source region 7, gate oxide film 8, grid 9, silicon oxide film 10, source electrode 11 and drain 12.Like this, finished the super node MOSFET of Fig. 6.
As another kind of manufacture method, as shown in figure 12, can also repeat to form N type epitaxial film 4a, 4b, 4c, 4d, 4e and p type impurity district 5 to form the PN post right by using ion to inject (and diffusion).That is, N type epitaxial film 4a is formed on N +On the silicon substrate 1, and in the presumptive area of this N type epitaxial film 4a, form p type impurity district 5.Subsequently, on N type epitaxial film 4a, form N type epitaxial film 4b, and in this N type epitaxial film 4b, form p type impurity district 5.Afterwards, repeat this technology and extend in the vertical and N type impurity range 4 and p type impurity district 5 be set.
In addition, can also change recess width Wt rather than change all the other width Ws among Fig. 9.That is, all the other width Ws also can be set to uniformly (consistently be provided with), and recess width Wt that can groove 22 is set to two or more.
Then, will attach most importance to the difference that is different from first execution mode and introduce the 4th execution mode.
The PN post that Figure 13 illustrates in the present embodiment is right.Identical among other structures and Fig. 1, and omit its explanation.
In first to the 3rd execution mode, in pole unit (impurity range unit), change dosage.Yet in the present embodiment, it is poor to form impurity dose in post in the vertical.That is, the right impurity dose of the post among vertical (flow direction of the electric current) Z in the active area of semiconductor device is according to position (being the degree of depth) but uneven.
Specifically, the impurity concentration of N type impurity range 4 is set to a kind of N1, and the impurity concentration in p type impurity district 5 is set to a kind of P1.The wideest with respect to the width W 4 (Z) on vertical Z of N type impurity range 4 in the bottom, and narrow down linearly towards upside.The narrowest with respect to the width W 5 (Z) on vertical Z in p type impurity district 5 in the bottom, and broaden linearly towards upside.
Like this, the impurity concentration of each N type impurity range 4 is set equally, and the impurity concentration in each p type impurity district 5 equally is set.In addition, with respect to N type impurity range 4 vertically on width W 4 and with respect to p type impurity district 5 vertically on width W 5 differently be provided with according to the position (degree of depth) on vertically.Like this, post right vertically on impurity dose according to the position but uneven.
Like this, as shown in figure 14,,, exhaust the right moment of PN post fully can be offset according to direction of current flow with respect to expansion by the depletion layer shown in the dotted line among this figure from transistorized conducting state (during shutoff) when cut-off state is changed.Therefore, reduced, and jumping that can deboost increases in change rate from the electric current of conducting state when cut-off state is changed.
As Figure 15 rather than shown in Figure 13, N type impurity range 4 vertically on width and p type impurity district 5 vertically on width also can differently be provided with according to the position vertically.In addition, the width transversely (width transversely in the p type impurity district 5 among Figure 15) with respect to zone 4,5 also can differently be provided with in each zone 4,5 (each the p type impurity district 5 among Figure 15).In Figure 15, the width transversely in p type impurity district 5 differently is provided with in each zone 5.Yet the width transversely of N type impurity range 4 also can differently be provided with in each zone 4, and perhaps the width transversely with respect to N type impurity range 4 and p type impurity district 5 also can differently be provided with in the zone 4,5 separately at two.
Above-mentioned execution mode can also following the setting.
The epitaxial wafer that can also use the silicon layer 2 by stacked low impurity concentration in high impurity concentration silicon substrate 1 to form, and can be with the body substrate as the silicon wafer among Fig. 1, or the like.
In addition, as the manufacture method in PN post (N type impurity range 4 and p type impurity district 5), can also after forming, groove bury groove by injecting ion from trenched side-wall.In addition, after forming, groove in groove, buries the material (for example oxide) of impurity, and also can be as the manufacture method of PN post to the method for trenched side-wall one side diffusion impurity from the material of impurity by heat treatment.In addition, as the manufacture method of PN post, can also only inject and diffusion and do not form groove and form post by ion.
As in the method that makes right non-homogeneousization of impurity dose of post perpendicular to the flow direction of electric current with respect to the position, just in the broadest sense, at least one in the impurity concentration of the width W 4 of N type impurity range 4, the width W 5 in p type impurity district 5, N type impurity range 4 and the impurity concentration in p type impurity district 5 can be according to differently being provided with perpendicular to the position on the direction of the flow direction of electric current.
The front is illustrated plane MOSFET as an example, but matrix and groove-shaped in also can obtain similar effects.Figure 16 shows an example under the situation of groove gate type MOSFET.In Figure 16, N type source region 31 is formed in the surface layer part of P type silicon layer 30.In P type silicon layer 30, form groove 32, so that pass source region 31 and P type silicon layer 30.Grid 34 passes gate oxide film 33 and is formed in the groove 32.With silicon oxide film 35 cover gate 34, and form source electrode 36 thereon.In addition, on the rear surface of substrate 1, form drain electrode 37.
In addition, the foregoing description can also be applicable to (Silicon-on-insulator) MOSFET lateral.Figure 17 is illustrated in an example under the situation of (Silicon-on-insulator) MOSFET lateral.In Figure 17, P type channel formation region 41 is formed in the surface layer part on the upper surface of N type silicon substrate 40.N type source region 42 is formed in the surface layer part in this channel formation region 41.Grid 44 passes in the exposed portions serve of the channel formation region 41 on the upper surface that gate oxide film 43 is formed on substrate 40.In addition, form N in the locational surface layer part of on the upper surface of N type silicon substrate 40, separating with P type channel formation region 41 +Drain region 45.P type channel formation region 41 and N +Drain region 45 forms band shape respectively, and forms with constant interval abreast.
The N type impurity range 46 that extends at laterally (flow direction of electric current) and equally in the p type impurity district 47 of laterally (flow direction of electric current) extension at P type channel formation region 41 and N +Be adjacent between the drain region 45 alternately to be arranged in the surface layer part on the upper surface of N type silicon substrate 40.
Here, for example, the impurity concentration of each N type impurity range 46 is set equally, and the impurity concentration in each p type impurity district 47 equally is set.The width W 46 of each N type impurity range 46 equally is set, and the width W 47 in p type impurity district 47 is provided with differently according to the position on horizontal (more especially, the Y direction among Figure 17).Like this, the impurity dose on right horizontal (particularly, the Y direction among Figure 17) of post is according to the position but uneven.
In addition, except MOSFET, the foregoing description can also be applied to IGBT and diode.
In the explanation in front, first conduction type is the N type, and second conduction type is the P type.Yet on the contrary, first conduction type also can be the P type, and second conduction type also can be the N type.
Then, with discuss impurity dose according to the position different and optimization impurity dose when inhomogeneous.
Figure 18 illustrates the relation between impurity dose and the component pressure.
In Figure 18, use the different structure 1,2 of component structure, and carry out withstand voltage measurement by the impurity dose that differently is provided with in the structure 1,2 (for example, the structure of the structure of Fig. 4 and Fig. 6 is set to structure 1,2).More particularly, for example, carry out withstand voltage measurement in a kind of semiconductor device, in this semiconductor device, all parts that are set to three kinds of concentration N1, N2, N3 in the structure of Fig. 4 all are set to concentration N1.All these parts all are set to carry out withstand voltage measurement in the semiconductor device of concentration N2 therein.All these parts all are set to carry out withstand voltage measurement in the semiconductor device of concentration N3 therein.In addition, for example, in the structure of Fig. 6, all parts that are set to three kinds of width W 4 (little), W4 (medium), W4 (greatly) therein in the structure of Fig. 6 all are set to carry out withstand voltage measurement in the semiconductor device of width W 4 (little).All these parts all are set to carry out withstand voltage measurement in the semiconductor device of width W 4 (medium) therein.In being set to the semiconductor device of width W 4 (greatly), all these parts carry out withstand voltage measurement.
In Figure 18,, that is, when any lateral deviation of impurity dose to high impurity dose and low impurity dose that reaches maximum component pressure moved, also can reduce component pressure even when the skew of component pressure forward ground and negative sense ground.Correspondingly, also show roughly symmetrical characteristic.Even when component structure changes, this trend also is identical.
Therefore, when impurity dose is set to two kinds of values, reaches withstand voltage peaked impurity dose and be set to reference value, and optionally determine the skew of forward ground and negative sense ground equivalent and roughly have two withstand voltage points of equating.Particularly, for example, in Figure 18, two kinds of impurity dose α 1, α 2 carry out the equivalent skew from reaching maximum withstand voltage impurity dose forward ground and negative sense ground, and are set up.Like this, the voltage in the time of just can reducing to turn-off under the situation that need not reduce component pressure is partly jumped and is increased.That is, when component pressure only reduces according to the position, exist in the possibility that causes current concentration when puncturing and cause component breakdown.Yet,, avoided current concentration, and under the situation that does not make current concentration, can prevent component breakdown in breakdown time by optionally determining roughly have two withstand voltage points of equating.
When impurity dose is set to three kinds or more kinds of value, optionally determine impurity dose from two points of forward and negative offset equally and by these two some clamping zones.Specifically, for example, in Figure 18, for three kinds of impurity dose α 1, α 2, α 3, impurity dose α 1, α 2 carry out the equivalent skew from reaching maximum withstand voltage impurity dose forward ground and negative sense ground, and are set up.Impurity dose α 3 is arranged in the zone by impurity dose α 1, α 2 clampings.Impurity dose α 3 preferably medially is arranged in the zone by impurity dose α 1, α 2 clampings.Similarly, in Figure 18, for four kinds of impurity dose β 1, β 2, β 3, β 4, impurity dose β 1, β 2 are offset from reaching maximum withstand voltage impurity dose forward ground and negative sense ground equivalent, and are set up.Impurity dose β 3, β 4 are arranged in the zone by impurity dose β 1, β 2 clampings.Impurity dose β 3, β 4 preferably are set in by the zone of impurity dose β 1, β 2 clampings by the impurity dose of trisection.Similarly, in Figure 18, for five kinds of impurity dose α 1, α 2, α 3, α 4, α 5, impurity dose α 1, α 2 are from reaching maximum withstand voltage impurity dose forward ground and the skew of negative sense ground equivalent and being set up.Impurity dose α 3, α 4, α 5 are arranged in the zone by impurity dose α 1, α 2 clampings.Impurity dose α 3, α 4, α 5 preferably are set in by the zone of impurity dose α 1, α 2 clampings by the impurity dose of the quartering.
Described three kinds or multiplely comprise that also continually varying is a kind of.
As mentioned above, in each above-mentioned execution mode, be set to two values so that impurity dose is different and different according to the position at impurity dose, and when the impurity dose with equal side-play amount is set at high impurity dose one side and low impurity dose one side about reaching maximum withstand voltage impurity dose, can prevent that component pressure from reducing partly.In addition, in above-mentioned each execution mode, when impurity dose is set to three kinds or multiple value so that impurity dose is different and different along with the position, and the impurity dose with equal side-play amount is set at high impurity dose one side and low impurity dose one side about reaching maximum withstand voltage impurity dose, and all the other impurity doses can prevent that component pressure from reducing partly when being set in the zone of clamping therebetween.
Introduce below with reference to accompanying drawings and be used to embody the 5th execution mode of the present invention.
Figure 24 is the longitudinal sectional drawing of the semiconductor device in the present embodiment.This semiconductor device is vertical MOS FET, and electric current is vertically flowing.That is, vertically be the flow direction of electric current, and laterally be perpendicular to the direction of direction of current flow.
Figure 25 is the transverse cross-sectional view along the line XXV-XXV intercepting of Figure 24, and the structure of the section in the super-junction structure part is shown.
In Figure 24, silicon layer 2 is formed on N +On the silicon substrate 1, and N type silicon layer 3 is formed on the silicon layer 2.Semiconductor substrate is made of this laminated structure.In the silicon layer 2 of Semiconductor substrate, the N of longitudinal extension type impurity range (N post) 4 and same being adjacent in the horizontal in the p type impurity district of longitudinal extension (P post) 5 and alternately setting.Post is made of N type impurity range 4 and p type impurity district 5 (PN post to).Like this, formed super-junction structure.When conducting state, the N type impurity range 4 of PN post centering becomes drift layer, and has electric current to flow.When ending, depletion layer is from the interface expansion in N type impurity range 4 and p type impurity district 5.
In above-mentioned N type silicon layer 3, form P type channel formation region 6, so that arrive p type impurity district 5.Form N type source region 7 in the surface layer part in P type channel formation region 6.In the part that is used for exposing the P type channel formation region 6 on the upper surface of N type silicon layer 3, the gate oxide film 8 that passes as gate insulating film forms grids 9.With silicon oxide film 10 cover gate 9.Source electrode 11 is formed on the upper surface of N type silicon layer 3.This source electrode 11 is electrically connected to source region 7 and channel formation region 6.Drain electrode 12 is formed on N +On the lower surface of silicon substrate 1 (rear surface).
Be set to earth potential and 12 apply under the state of positive potential at source electrode 11, make transistor turns by applying positive potential to grid 9 to drain electrode.When the transistor turns state, as shown in figure 24, electric current 12 passes N from draining +Silicon substrate 1, N type impurity range 4, N type district (3), part (inversion layer) and source region 7 relative with grid 9 in channel formation region 6 flow to source electrode 11.
On the other hand, when grid 9 was set to earth potential, transistor became and ends from transistor turns state (wherein source electrode 11 is set to earth potential and is set to positive potential with drain electrode 12, and grid 9 is set to positive potential).Depletion layer is from the interface expansion in N type impurity range 4 and p type impurity district 5.
Here, in the present embodiment, as shown in figure 25, N type impurity range (N post) 4 that the post in the active area of transistor formed is right and p type impurity district (P post) 5 form its section shape for banded, and alternately are set in parallel on the same direction (Y direction).In addition, N type impurity range (N post) 4 bridge joints adjacent one another are get up.That is,, form the bridging part 213 of constant width with predetermined space for adjacent N type impurity range (N post) 4.More particularly, bridging part 213 is arranged in the chip regularly, promptly in plane X-Y of Figure 25.In addition, the width W b of bridging part 213 is set to be clamped in the width W a or the littler (Wb≤Wa) of the impurity range 5 between the impurity range 4 that is bridged.In addition, for adjacent impurity range 4, on the bearing of trend (Y direction) of impurity range 4, a plurality of bridging parts 213 are set, and the length L between the bridging part 213 is set to different value according to the position.That is, in Figure 25, being provided with of bridging part 213 is set at interval length L 1, L2, L3 (L1＜L2＜L3).Like this, the right impurity dose transversely (total impurities in zone 4,5) of periodic variation PN post.
When bridging part 213 not being set (when adjacent N type impurity range 4 is not bridged), shown in Figure 27 A, exhausting shaping in the propelling of post centering from transistorized conducting state (during shutoff) when cut-off state is changed.Shown in Figure 27 B, finish simultaneously post centering and to exhaust shaping (exhausting shaping immediately).In this operation, as shown in figure 23, from conducting state when cut-off state is changed, very big with respect to the change rate (dI/dt) of electric current I ds between drain electrode and the source electrode, and the jumping that has produced the voltage Vds between drain electrode and the source electrode increases.
In contrast to this, in the present embodiment, be provided with bridging part 213 (adjacent N type impurity range 4 bridge joints), and, exhaust shaping in the propelling of the post centering shown in Figure 26 A from transistorized conducting state (during shutoff) when cut-off state is changed.Shown in Figure 26 B, do not finish simultaneously this post centering and to exhaust shaping.In by the region S shown in the shade in the bridging part 213, exhaust when being shaped when in other zones, finishing, it is not finished and exhausts shapings (being offset the timing that exhausts shaping fully in chip wittingly).Like this, from transistorized conducting state (during shutoff) when cut-off state is changed, can exhaust the right timing of PN post fully in transistor face inner control.Therefore, as shown in Figure 3, reduced about the change rate (dI/dt) of electric current I ds between drain electrode and the source electrode, and can stop drain when cut-off state is changed from conducting state and source electrode between the jumping of voltage Vds increase.
That is, make the right impurity dose of PN post at bridging part 213 and uneven on every side, and it is also different to exhaust the timing of shaping by forming bridging part 213.Prevented from instantaneously in component side to exhaust shaping fully.In addition, can stop when conversion to produce noise, and can improve the anti-puncture amount of recovery characteristics and diode-built-in.
The manufacture method that below introduction is had the Semiconductor substrate of this super-junction structure.
As shown in figure 28, preparation is as the N type silicon wafer 20 of N type semiconductor substrate.As shown in figure 29, in wafer face, carry out etching (dry etching or wet etching), go up the groove 22 that forms constant recess width Wa with constant residue width Ws in same direction (the Y direction of Figure 25) with respect to wafer 20 by using mask 21.When forming this groove, this channel shaped becomes the length that has transistor area on depth direction (the Y direction of Figure 25) or longer.
In the present embodiment, as shown in figure 30, in forming the technology of groove 22, groove 22 is provided with and extension discontinuously abreast, and bridging part 213, promptly be used for not excavating groove area part be arranged in the transistor area.The width W b of bridging part 213 is arranged to following relation: Wb≤Wa with respect to the width W a of groove, thereby can not reduce device withstand voltage greatly.That is, when forming the groove 22 that extends discontinuously, the width W b of the part (bridging part 213) of interrupting with respect to this groove is set to the width W a of groove 22 or littler.
In addition, when forming the groove 22 that extends discontinuously, promptly, when the groove 22 that forms as the p type impurity district 5 among Figure 25, in the middle of the continuous part, differently set the length L of the part continuous in the part (bridging part 213) of interrupting with respect to groove according to the position with respect to groove with respect to groove.
Afterwards, as shown in figure 31, on N type silicon wafer 20, form P type epitaxial film 23, and bury groove 22 by epitaxial film 23.Afterwards, to first type surface one side (upper surface side) of N type silicon wafer 20, promptly upper surface one side of epitaxial film 23 is polished and planarization.Carry out this polishing, till exposing silicon wafer 20.Upper surface one side of epitaxial film 23 also can replace polishing to carry out planarization by returning to carve.In addition, if the control epitaxial growth is so that make the upper surface planarization of epitaxial film 23, then the planarization after the extension can be set to be unnecessary.
In addition, shown in figure 32, on the upper surface of N type silicon wafer 20, form N type epitaxial film 24.Can also form N type surface silicon layer by on the upper surface of N type silicon wafer 20, injecting ion, rather than on the upper surface of N type silicon wafer 20, form N type epitaxial film 24.
In addition, the rear surface (lower surface) of N type silicon wafer 20 is polished, till near groove 22, and with N +Silicon substrate bonds on this burnishing surface.Can also replace the rear surface of N type silicon wafer 20 is polished and N +Silicon substrate bonding, but by from the rear surface of N type silicon wafer 20 (lower surface) inject ion, with N +Silicon layer is formed on the rear surface of N type silicon wafer 20.
Make vertical MOS FET shown in Figure 24 by using the Semiconductor substrate (Semiconductor substrate) that forms in this way with super-junction structure.That is, form P type channel formation region 6, N type source region 7, gate oxide film 8, grid 9, silicon oxide film 10, source electrode 11 and drain 12.Like this, finished the super node MOSFET of Figure 24.
Here, the groove of discussing the extension of utilizing groove in above-mentioned manufacturing process is formed technology and buries technology.
In Figure 34, in the device of medium and high withstand voltage (for example 200 arriving 300V or bigger), it is big that the aspect ratio of wall part 100 (H/W) becomes.For example, aspect ratio is that " 5 " arrive " 10 " when 600V withstand voltage, and aspect ratio is that " 5 " arrive " 10 " or bigger when surpassing 1000V withstand voltage.About the length (L) of groove, groove forms longlyer than transistor area.Therefore, under the situation of the power device that is used to handle big electric current, this length at about 1mm in the scope of ten mm and several mm.Therefore, exist trench wall 100 to tilt and the possibility of before groove is buried, fall down suddenly when wafer transport and during cleaning (fall).And, owing to increased, therefore can not form the long groove that reaches wafer diameter to the inclination of trench wall and the worry of falling down suddenly.Therefore, force formation to meet the groove of chip size.
In this embodiment, after forming strip groove 22, bury groove 22 by epitaxial growth.Yet, when forming strip groove 22, as shown in figure 30,, can avoid that trench wall 223 tilts and falls down suddenly before raceway groove is buried in transistor area by bridging part (being used for not excavating the zone of groove) 213 partly is set.Like this, the PN post that forms same design in can the whole zone in wafer face is right, and the substrate trenches that has nothing to do of formation and chip size.
(1) in having the semiconductor device of super-junction structure (vertical MOS FET), formed on right N type impurity range (N post) 4 and p type impurity district (the P post) 5 of post for the active area of banded formation semiconductor device perpendicular to the face of direction of current flow, as shown in figure 25, and they alternately be arranged in parallel in the same direction.Adjacent N type impurity range (N post) 4 bridge joints are got up.Correspondingly, shown in Figure 26 A and 26B, from conducting state (during shutoff) when cut-off state is changed, exhaust fully the post that constitutes by N type impurity range (N post) 4 and p type impurity district (P post) 5 to the timing of (PN post to) on face, at the bridging part 213 of N type impurity range (N post) 4 and be offset on every side perpendicular to direction of current flow.Like this, can limit from the jumping of conducting state voltage when cut-off state is changed and increase.
(2) as manufacture method, comprise first technology and second technology with Semiconductor substrate of super-junction structure.Shown in Figure 29 and 30, in first technology, by in N type silicon wafer 20, carrying out the groove 22 that etching is provided with constant recess width Wa abreast, so that it is extended discontinuously with constant residue width Ws on same direction.As shown in figure 31, in second technology, on N type silicon wafer 20, form P type epitaxial film 23, and bury groove 22 by this epitaxial film 23.Correspondingly, can obtain to be used for the substrate of the semiconductor device of above-mentioned (1) at an easy rate.In addition, in the mill, the aspect ratio of the wall part after groove forms becomes big, and before the use epitaxial growth was buried, wall tilted easily and falls down suddenly easily.Yet, in the present embodiment, the groove 22 of constant recess width Wa is set abreast, so that on same direction, extend discontinuously with constant residue width Ws.Therefore, can prevent that trench wall from tilting and falling down suddenly.Thereby the PN post that forms same design in can the whole zone in wafer face is right, and can form and substrate trenches that chip size is irrelevant.
(3) particularly, in (1), as shown in figure 25, the width W b of bridging part 213 is set to the width W a in the p type impurity district 5 of clamping between the N type impurity range 4 that is bridged or littler.Thereby the zone of being represented by the Reference numeral S among Figure 26 B has reduced, and can prevent that the withstand voltage of device from too reducing.Therefore, when forming the groove 22 that extends discontinuously in above-mentioned first technology, the width W b of the part (bridging part 213) of interrupting with respect to groove is set to the width W a of groove 22 or littler just enough.
In addition, as shown in figure 25,, a plurality of bridging parts 213 are set on the bearing of trend of N type impurity range 4, and the length L between the bridging part 213 is provided with differently according to the position difference with respect to adjacent N type impurity range 4.Correspondingly, bridging part 213 can be set by the length between the periodic variation bridging part, and can on perpendicular to the face of direction of current flow, bridging part 213 be set brokenly.Like this, can in active area, be offset and exhaust and be shaped regularly the optimization of (exhausting be shaped regularly by skew gradually etc.), and obtain bigger effect.Therefore, when in above-mentioned first technology, forming the groove 22 that extends discontinuously, the part (bridging part 213) that will interrupt with respect to groove and differently be provided with just enough according to the position with respect to the length L of the part continuous in the middle of the continuous part of groove with respect to groove.
Attach most importance to the difference that is different from the 5th execution mode below and introduce the 6th execution mode.
Present embodiment is configured to as Figure 33 but not structure shown in Figure 25.
In Figure 33, bridging part 213 is as the formation position of bridging part 213 and periodically be provided with, and the width W b of bridging part 213 is arranged to (order of Wb1＜Wb2＜Wb3) increases successively according to Wb1, Wb2, Wb3.
That is,, on the bearing of trend (Y direction) of N type impurity range 4, a plurality of bridging parts 213 are set, and the width W b of bridging part 213 is provided with differently according to the position with respect to adjacent N type impurity range 4.Therefore, when in above-mentioned first technology, forming the groove 22 that extends discontinuously, in the part (bridging part 213) of interrupting with respect to groove with respect to groove in the middle of the continuous part, the width W b of the part (bridging part 213) of interrupting with respect to groove differently is provided with according to the position.Like this, can be used in each bridging part the timing slip that on cross section (perpendicular to the face of the flow direction of electric current), exhausts shaping fully.Like this, can be offset the optimization (timing that exhausts adjacent bridging part is offset gradually, etc.) of the timing that exhausts adjacent bridging part, and obtain bigger effect.
About the N type impurity range 4 that is bridged, as described in the 5th execution mode, can be with respect to adjacent impurity range 4, at the bearing of trend of impurity range 4 a plurality of bridging parts 213 are set, and the length L between the bridging part 213 can also differently be provided with according to the position.In addition, as explaining in the 6th execution mode, the width W b of bridging part 213 also can differently be provided with according to the position.Therefore, can carry out more detailed design.
Above-mentioned execution mode can also carry out following setting.
In Figure 25 etc., adjacent N type impurity range (N post) 4 is bridged, but adjacent p type impurity district (N post) 5 also can be bridged.
In the explanation in front, first conduction type is the N type, and second conduction type is the P type.Yet on the contrary, first conduction type also can be the P type, and second conduction type also can be the N type.That is, in Figure 24, the P post of post centering also can be set to the drift region as the P channel mosfet.
In addition, the front has been explained plane MOSFET as an example, but matrix with groove-shaped in also can obtain identical effect.
Above-mentioned disclosure has following aspect.
According to first scheme of present disclosure, the semiconductor device with super-junction structure comprises: a plurality of first posts that have first conduction type and extend on direction of current flow; With a plurality of second posts that have second conduction type and on direction of current flow, extend.First post and second post alternately are provided with on perpendicular to the alternating direction of direction of current flow, thereby this super-junction structure is provided.Each first post provides drift layer, is used to make electric current to flow through under the situation of conducting state.First post and second post have the border between first post and second post, depletion layer extends from this border under the situation of cut-off state.In first post and second post at least one has impurity dose, and this impurity dose is different but uneven along with the position on alternating direction.
When this device from conducting state when cut-off state is changed, the timing that exhausts first and second posts fully at alternating direction along with the position is different but devious.Therefore, when device was transformed into cut-off state, voltage was beated and has been reduced.
Perhaps, each first post can have first impurity concentration, and each second post can have second impurity concentration.In first impurity concentration and second impurity concentration at least one changes along with the position on the alternating direction.
Perhaps, each first post can have first width on alternating direction, and each second post can have second width on alternating direction.In first width and second width at least one changes along with the position on the alternating direction.
Perhaps, each first post can have first width on alternating direction, and first width on alternating direction along with change in location but constant.Each second post can have second width on alternating direction, second width on alternating direction along with change in location but constant.Each first post can have first impurity concentration, and each second post can have second impurity concentration.First impurity concentration and second impurity concentration change along with change in location on alternating direction.
Perhaps, each first post can have first width on alternating direction, and first width on alternating direction with change in location but constant.Each second post can have second width on alternating direction, and second width on alternating direction with change in location but constant.Each first post can have first impurity concentration, and each second post can have second impurity concentration.First impurity concentration changes along with change in location on alternating direction, and second impurity concentration on alternating direction along with change in location but constant.
Perhaps, each first post can have first impurity concentration, and first impurity concentration on alternating direction with change in location but constant.Each second post can have second impurity concentration, and second impurity concentration on alternating direction along with change in location is constant.Each first post can have first width on alternating direction, and each second post can have second width on alternating direction.First width changes along with change in location on alternating direction, second width on alternating direction with change in location but constant.
Perhaps, at least one in the impurity dose of first post and second post can comprise first dosage and second dosage.When one of described in impurity dose was predetermined best impurity dose, this device had maximum breakdown voltage.First dosage is than the high predetermined value of this best impurity dose.Second dosage is than the low predetermined value of this best impurity dose.In this case, the puncture voltage of device has improved, and, prevents that the puncture voltage of device from reducing partly that is.
Perhaps, at least one in the impurity dose of first post and second post can comprise first dosage, at least one middle dosage and second dosage.When one of described in the impurity dose was predetermined best impurity dose, this device had maximum breakdown voltage.First dosage is than the high predetermined value of this best impurity dose.Second dosage is than the low predetermined value of this best impurity dose.Middle dosage is set in the zone between first dosage and second dosage.
Perhaps, this device can be vertical MOS FET or lateral type MOSFET.
According to the alternative plan of present disclosure, the semiconductor device with super-junction structure comprises: a plurality of first posts that have first conduction type and extend on direction of current flow; With a plurality of second posts that have second conduction type and on direction of current flow, extend.First post and second post alternately are provided with on perpendicular to the alternating direction of direction of current flow, thereby super-junction structure is provided.Each first post provides drift layer, is used to make electric current to flow through under the situation of conducting state.First post and second post have the border between first post and second post, depletion layer extends from this border under the situation of cut-off state.In first post and second post at least one has impurity dose, and this impurity dose is different but uneven along with the position on direction of current flow.
When this device from conducting state when cut-off state is changed, the timing that exhausts first and second posts fully in direction of current flow along with the position is different but devious.Therefore, when device was transformed into cut-off state, voltage was beated and has been reduced.
Perhaps, each first post can have first impurity concentration, and first impurity concentration is along with the position on the alternating direction is different but constant.Each second post can have second impurity concentration, and second impurity concentration is along with the position on the alternating direction is different but constant.Each first post can have first width on alternating direction, and each second post can have second width on alternating direction.First width and second width change with the position on direction of current flow.
According to third party's case of present disclosure, the method that is used to make the semiconductor device with super-junction structure comprises: preparation has the Semiconductor substrate of first conduction type; Form a plurality of grooves in this substrate, wherein each groove has the constant width along first direction, and wherein comprises first distance and second distance at least along the distance between two adjacent grooves of first direction; Formation has the epitaxial film of second conduction type on substrate, thereby fills these grooves with this epitaxial film; And substrate one side that forms epitaxial film on it carried out planarization.
Said method provides this semiconductor device, wherein when this device is transformed into cut-off state, has reduced voltage and has beated.
According to the cubic case of present disclosure, the semiconductor device with super-junction structure comprises: a plurality of first posts that have first conduction type and extend on direction of current flow; With a plurality of second posts that have second conduction type and on direction of current flow, extend.First post and second post alternately are provided with on perpendicular to the alternating direction of direction of current flow, thereby super-junction structure is provided.Each first post provides drift layer, is used to make electric current to flow through under the situation of conducting state.First post and second post have the border between first post and second post, depletion layer extends from this border under the situation of cut-off state.In first post and second post each has the stripe-shape plane pattern on the plane perpendicular to direction of current flow.At least a in first post and second post has bridging part, and this bridging part connects one first or second post and the first or second adjacent post.
When this device from conducting state when cut-off state is changed, the timing that exhausts first and second posts fully at alternating direction along with the position is different but devious.Therefore, when device is transformed into cut-off state, has reduced voltage and beated.
Perhaps, the another kind in first post and second post can have the width along alternating direction.Bridging part has along the width of the bearing of trend of stripe-shape plane pattern, and described bearing of trend is perpendicular to alternating direction, and the width of bridging part is less than alternative width described in first post and second post.In this case, improved the puncture voltage of device.
Perhaps, bridging part can comprise a plurality of bridging elements.Bridging element has along the distance of bearing of trend between a bridging element and adjacent bridging element perpendicular to the stripe-shape plane pattern of alternating direction, and this distance of bridging element changes along with the position.In this case, bridging element can periodically be provided with or be provided with at random, thereby optimization is carried out in the timing that exhausts first and second posts fully.Like this, when device when cut-off state is changed, reduced voltage effectively and beated.
Perhaps, bridging part can comprise a plurality of bridging elements.Each bridging element has along the width perpendicular to the bearing of trend of the stripe-shape plane pattern of alternating direction, and the width of bridging element changes with the position.
According to the 5th scheme of present disclosure, the method that is used to make the semiconductor device with super-junction structure comprises: preparation has the Semiconductor substrate of first conduction type; In this substrate, form a plurality of grooves, wherein each groove has the constant width along first direction, wherein these grooves have constant distance between two grooves adjacent along first direction, and wherein each groove extends on perpendicular to the second direction of first direction discontinuously; Formation has the epitaxial film of second conduction type on substrate, thereby fills these grooves with this epitaxial film.
Said method provides semiconductor device, has wherein reduced voltage when this device is transformed into cut-off state and has beated.In addition, because these grooves have constant distance between adjacent two grooves, and the extension discontinuously on second direction of each groove, can prevent that therefore trench wall from tilting.
Perhaps, groove can have breaking part, and groove stops to extend at this breaking part.Breaking part has the width along second direction, and the width of breaking part is less than the constant width of groove.
Perhaps, groove can have a plurality of breaking parts, and groove stops to extend at this breaking part.Breaking part has along second direction, distance between a breaking part and adjacent breaking part, and this distance of breaking part changes with the position.
Perhaps, these grooves can have a plurality of breaking parts, and groove stops to extend at breaking part.Each breaking part has the width along second direction, and the width of breaking part changes with the position.
Although introduced the present invention, it should be understood that to the invention is not restricted to these preferred embodiments and structure with reference to the preferred embodiments of the present invention.This invention is intended to cover various modifications and equivalence setting.In addition, although preferred described various combinations and structure, comprise more, still less or only other combinations and the structure of discrete component also all comprise within the spirit and scope of the present invention.
1, a kind of semiconductor device with super-junction structure comprises:
Have first conduction type, and a plurality of first posts (4) that on direction of current flow, extend; With
Have second conduction type, and a plurality of second posts (5) that on this direction of current flow, extend, wherein
Described first post (4) and described second post (5) alternately are provided with on perpendicular to the alternating direction of this direction of current flow, thereby this super-junction structure is provided,
Each first post (4) provides drift layer, is used to make electric current to flow through under the situation of conducting state,
Described first post (4) and described second post (5) have the border between first post (4) and second post (5), depletion layer extends from this border under the situation of cut-off state, and
In described first post (4) and described second post (5) at least one has impurity dose, this impurity dose on this alternating direction along with change in location but uneven.
2, device according to claim 1, wherein
Each first post (4) has first impurity concentration,
Each second post (5) has second impurity concentration, and
In this first impurity concentration and this second impurity concentration at least one changes with the position on this alternating direction.
3, device according to claim 1, wherein
Each first post (4) has first width on this alternating direction,
Each second post (5) has second width on this alternating direction, and
In described first width and described second width at least one changes along with the position on this alternating direction.
4, device according to claim 1, wherein
This first width on this alternating direction along with change in location but constant,
Each second post (5) has second width on this alternating direction,
This second width on this alternating direction along with change in location but constant,
This first impurity concentration and this second impurity concentration change along with the position on this alternating direction.
5, device according to claim 1, wherein
This first width on this alternating direction with change in location but constant,
This second width on this alternating direction with change in location but constant,
Each second post (5) has second impurity concentration,
This first impurity concentration changes along with the position on this alternating direction, and
This second impurity concentration on this alternating direction along with change in location but constant.
6, device according to claim 1, wherein
This first impurity concentration on this alternating direction with change in location but constant,
This second impurity concentration on this alternating direction along with change in location is constant,
This first width changes along with the position on this alternating direction, and
This second width on this alternating direction with change in location but constant.
7, according to each described device among the claim 1-6, wherein
In the impurity dose of described first post (4) and described second post (5) at least one comprises first dosage and second dosage,
When one of described in impurity dose was predetermined best impurity dose, this device had maximum breakdown voltage,
This first dosage is than the high predetermined value of this best impurity dose, and
This second dosage is than the low described predetermined value of this best impurity dose.
8, according to each described device among the claim 1-6, wherein
In the impurity dose of described first post (4) and described second post (5) at least one comprises first dosage, at least one middle dosage and second dosage,
When one of described in the impurity dose was predetermined best impurity dose, this device had maximum breakdown voltage,
This first dosage is than the high predetermined value of this best impurity dose,
This second dosage is than the low described predetermined value of this best impurity dose, and
This centre dosage is set in the zone between this first dosage and this second dosage.
9, according to each described device among the claim 1-6, wherein
This device is vertical MOS FET or lateral type MOSFET.
10, a kind of semiconductor device with super-junction structure comprises:
This first post (4) and this second post (5) alternately are provided with on perpendicular to the alternating direction of this direction of current flow, thereby this super-junction structure is provided,
In described first post (4) and described second post (5) at least one has impurity dose, and this impurity dose is different but uneven along with the position on this direction of current flow.
11, device according to claim 10, wherein
This first impurity concentration is different but constant along with the position on this alternating direction,
This second impurity concentration is different but constant along with the position on this alternating direction,
This first width and this second width change with the position on this direction of current flow.
12, according to claim 10 or 11 described devices, wherein
13, according to claim 10 or 11 described devices, wherein
This centre dosage is set in the zone between described first dosage and described second dosage.
14, according to claim 10 or 11 described devices, wherein
15, a kind of method that is used to make semiconductor device with super-junction structure, this method comprises:
Preparation has the Semiconductor substrate (20) of first conduction type;
Form a plurality of grooves (22) in this substrate (20), wherein each groove (22) has the constant width along first direction, and wherein comprises first distance and second distance at least along the distance between adjacent two grooves (22) of this first direction;
Go up formation at this substrate (20) and have the epitaxial film (23) of second conduction type, thereby fill described groove (22) with this epitaxial film (23); And
These substrate (20) one sides that form described epitaxial film (23) on it are carried out planarization.
16, a kind of semiconductor device with super-junction structure comprises:
Described first post (4) and described second post (5) have the border between first post (4) and second post (5), depletion layer extends from this border under the situation of cut-off state,
In described first post (4) and described second post (5) each has the stripe-shape plane pattern on the plane perpendicular to this direction of current flow, and
In described first post (4) and described second post (5) at least one has bridging part (213), and this bridging part (213) connects one first or second post (4,5) and adjacent first or second post (4,5).
17, device according to claim 16, wherein
In described first post (4) and described second post (5) another has the width along this alternating direction,
Described bridging part (213) has along the width of the bearing of trend of this stripe-shape plane pattern, and described bearing of trend is perpendicular to this alternating direction, and
This width of described bridging part (213) is less than another width described in described first post (4) and described second post (5).
18, according to claim 16 or 17 described devices, wherein
Described bridging part (213) comprises a plurality of bridging elements (213),
Described bridging element (213) has along the distance of bearing of trend between a bridging element (213) and adjacent bridging element (213) perpendicular to this stripe-shape plane pattern of this alternating direction, and
This distance of described bridging element (213) changes along with the position.
19, according to claim 16 or 17 described devices, wherein
Each bridging element (213) has along the width perpendicular to the bearing of trend of this stripe-shape plane pattern of this alternating direction, and
This width of described bridging element (213) changes with the position.
20, according to claim 16 or 17 described devices, wherein
21, a kind of method that is used to make semiconductor device with super-junction structure, this method comprises:
In this substrate (20), form a plurality of grooves (22), wherein each groove (22) has the constant width along first direction, wherein said groove (22) has constant distance between two grooves (22) adjacent along this first direction, and wherein each groove (22) extends on perpendicular to the second direction of this first direction discontinuously;
Go up formation at this substrate (20) and have the epitaxial film (23) of second conduction type, thereby fill described groove (22) with this epitaxial film (23).
22, method according to claim 21, wherein
Described groove (22) has breaking part (213), and groove (22) stops to extend at this breaking part (213),
Described breaking part (213) has a width in this second direction, and
This width of described breaking part (213) is less than the constant width of described groove (22).
23, according to claim 21 or 22 described methods, wherein
Described groove (22) has a plurality of breaking parts (213), and groove (22) stops to extend at this breaking part (213),
Described breaking part (213) has distance between a breaking part (213) and adjacent breaking part (213) along this second direction, and
This distance of described breaking part (213) changes with the position.
24, according to claim 21 or 22 described methods, wherein
Each breaking part (213) has a width along this second direction, and
This width of described breaking part (213) changes with the position.
CN2007100073746A 2006-01-31 2007-01-31 Semiconductor device having super junction structure and method for manufacturing the same CN101013724B (en)
JP2006023145 2006-01-31
JP023145/2006 2006-01-31
JP063833/2006 2006-03-09
JP2006063833A JP5076335B2 (en) 2006-03-09 2006-03-09 Semiconductor device and method for manufacturing semiconductor substrate having super junction structure
JP2006328397A JP5217158B2 (en) 2006-01-31 2006-12-05 Semiconductor device
JP328397/2006 2006-12-05
CN201210100028.3A Division CN102623349B (en) 2006-01-31 2007-01-31 Semiconductor device having super junction structure and method for manufacturing the same
CN2013100986196A Division CN103258853A (en) 2006-01-31 2007-01-31 Semiconductor device having super junction structure and method for manufacturing the same
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CN101013724B CN101013724B (en) 2013-07-17
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CN2013100986196A CN103258853A (en) 2006-01-31 2007-01-31 Semiconductor device having super junction structure and method for manufacturing the same
CN201210100028.3A CN102623349B (en) 2006-01-31 2007-01-31 Semiconductor device having super junction structure and method for manufacturing the same
CN2007100073746A CN101013724B (en) 2006-01-31 2007-01-31 Semiconductor device having super junction structure and method for manufacturing the same
US (4) US8106453B2 (en)
CN (3) CN103258853A (en)
DE (2) DE102007063840B3 (en)
CN102299073A (en) * 2010-06-25 2011-12-28 无锡华润上华半导体有限公司 Vertical double-diffusion metal oxide semiconductor (VDMOS) device and manufacturing method thereof
CN102738212A (en) * 2011-03-29 2012-10-17 万国半导体股份有限公司 Configuration and method to generate saddle junction electric field in edge termination
CN102891088A (en) * 2012-09-17 2013-01-23 电子科技大学 Method for manufacturing vertical double diffusion metal oxide semiconductor field effect transistor device
CN101877307B (en) * 2009-04-29 2013-02-13 上海华虹Nec电子有限公司 Method for obtaining alternative P-type and N-type semiconductor device structure and device structure thereof
CN104103524A (en) * 2014-08-11 2014-10-15 肖胜安 Super-junction device manufacturing method
CN104425602A (en) * 2013-08-30 2015-03-18 上海华虹宏力半导体制造有限公司 Super-junction appliance and manufacturing method
CN104425600A (en) * 2013-08-28 2015-03-18 上海华虹宏力半导体制造有限公司 Super-junction device and method for manufacturing same
CN104659086A (en) * 2013-11-21 2015-05-27 上海华虹宏力半导体制造有限公司 Power semiconductor device and manufacturing method thereof
CN105428397A (en) * 2015-11-17 2016-03-23 深圳尚阳通科技有限公司 Super-junction device and manufacturing method therefor
CN103199104B (en) * 2013-03-05 2016-04-27 矽力杰半导体技术(杭州)有限公司 A kind of crystal circle structure and apply its power device
CN107516678A (en) * 2017-08-07 2017-12-26 电子科技大学 A kind of super junction power device
JP4530036B2 (en) * 2007-12-17 2010-08-25 株式会社デンソー Semiconductor device
CN104576730B (en) * 2013-10-16 2017-03-29 上海华虹宏力半导体制造有限公司 Super-junction device and its manufacture method
CN103594504A (en) * 2013-11-19 2014-02-19 西安永电电气有限责任公司 IGBT with semi-super junction structure
CN104319284A (en) * 2014-10-24 2015-01-28 矽力杰半导体技术(杭州)有限公司 Semiconductor device structure and manufacturing method thereof
US9768284B2 (en) 2015-03-05 2017-09-19 Infineon Technologies Americas Corp. Bipolar semiconductor device having a charge-balanced inter-trench structure
CN106158626A (en) * 2015-03-30 2016-11-23 中芯国际集成电路制造(上海)有限公司 Power device and forming method thereof
KR101962834B1 (en) * 2015-04-30 2019-03-27 수 조우 오리엔탈 세미컨덕터 콤퍼니 리미티드 Semiconductor super-junction power device and manufacturing method therefor and manufacturing method therefor
CN105428412A (en) * 2015-12-22 2016-03-23 工业和信息化部电子第五研究所 Algan/gan heterojunction field effect transistor and preparation method thereof
CN107331702A (en) * 2016-04-29 2017-11-07 株洲中车时代电气股份有限公司 Carrier injection type IGBT with super-junction structure
CN106206734B (en) * 2016-07-11 2019-10-29 中国科学院微电子研究所 A kind of superjunction MOS transistor
US10580884B2 (en) * 2017-03-08 2020-03-03 D3 Semiconductor LLC Super junction MOS bipolar transistor having drain gaps
KR20190127324A (en) * 2018-05-04 2019-11-13 현대자동차주식회사 Semiconductor device and method manufacturing the same
DE10061310A1 (en) * 2000-12-08 2002-06-27 Infineon Technologies Ag Semiconducting component with increased breakdown voltage has active structure and edge structure, compensation field strength in edge structure lower than that in active area
JP4265201B2 (en) 2002-10-25 2009-05-20 富士電機デバイステクノロジー株式会社 Super junction semiconductor device
JP4773716B2 (en) * 2004-03-31 2011-09-14 株式会社Ｓｕｍｃｏ Manufacturing method of semiconductor substrate
2007-01-30 DE DE102007063840.1A patent/DE102007063840B3/en active Active
2007-01-30 US US11/699,579 patent/US8106453B2/en active Active
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CN102738212B (en) * 2011-03-29 2014-11-26 万国半导体股份有限公司 Configuration and method to generate saddle junction electric field in edge termination
CN104659086B (en) * 2013-11-21 2018-02-06 上海华虹宏力半导体制造有限公司 Power semiconductor and its manufacture method
CN104103524B (en) * 2014-08-11 2019-03-12 肖胜安 A kind of super-junction device production method
CN105428397B (en) * 2015-11-17 2019-07-02 深圳尚阳通科技有限公司 Superjunction devices and its manufacturing method
US8421154B2 (en) 2013-04-16
DE102007004616B4 (en) 2014-01-23
US9368575B2 (en) 2016-06-14
US20130157444A1 (en) 2013-06-20
US8106453B2 (en) 2012-01-31
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CN102623349A (en) 2012-08-01
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US8659082B2 (en) 2014-02-25
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US20070177444A1 (en) 2007-08-02
US20120068298A1 (en) 2012-03-22
US20140077289A1 (en) 2014-03-20
KR101630734B1 (en) 2016-06-16 Power device
JP3804375B2 (en) 2006-08-02 Semiconductor device and power switching drive system using the same
DE102004051348B4 (en) 2017-07-27 Superjunction device with improved robustness
CN101366105B (en) 2012-05-09 Semiconductor device and method for manufacturing same
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