Source: http://www.google.com/patents/US6249827?dq=7143430
Timestamp: 2016-12-04 06:16:10
Document Index: 392848718

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 08', 'Application No. 08']

Patent US6249827 - Method for transferring data associated with a read/write command between a ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks and communicatively...http://www.google.com/patents/US6249827?utm_source=gb-gplus-sharePatent US6249827 - Method for transferring data associated with a read/write command between a processor and a reader circuit using a plurality of clock linesAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6249827 B1Publication typeGrantApplication numberUS 08/987,328Publication dateJun 19, 2001Filing dateDec 9, 1997Priority dateAug 11, 1997Fee statusLapsedPublication number08987328, 987328, US 6249827 B1, US 6249827B1, US-B1-6249827, US6249827 B1, US6249827B1InventorsDavid V. James, Bruce Millar, Cormac M. O'Connell, Peter B. Gillingham, Brent KeethOriginal AssigneeAdvanced Memory International, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (3), Classifications (41), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod for transferring data associated with a read/write command between a processor and a reader circuit using a plurality of clock lines
This application claims priority from U.S. Provisional Patent Application No. 60/055,349, entitled, “SLDRAM Architecture,” filed Aug. 11, 1997, naming as inventors Kevin Ryan et al., with Attorney Docket No. 017938-000900, and under an obligation of assignment to the Assignee of the instant invention. U.S. Provisional Patent Application No. 60/055,349 is incorporated herein by reference for all purposes.
This application also claims priority from U.S. Provisional Patent Application No. 60/057,092, entitled, “SLDRAM Architecture,” filed Aug. 27, 1997, naming as inventors David B. Gustavson et al., and under an obligation of assignment to the Assignee of the instant invention. U.S. Provisional Patent Application No. 60/057,092 is incorporated herein by reference for all purposes.
This application also claims priority from U.S. Provisional Patent Application No. 60/055,368, entitled, “A High-Speed Memory Interface (SyncLink),” filed Aug. 11, 1997, naming as inventors David B. Gustavson et al., and under an obligation of assignment to the Assignee of the instant invention. U.S. Provisional Patent Application No. 60/055,368 is incorporated herein by reference for all purposes.
This application also claims priority from U.S. Patent Application No. 08/909,299, entitled, “Bifurcated Data and Command/Address Communication Bus Architecture for Random Access Memories Employing Synchronous Communication Protocols,” filed Aug. 11, 1997, naming as inventors David B. Gustavson et al., and under an obligation of assignment to the Assignee of the instant invention. U.S. Patent Application No. 08/909,299 is incorporated herein by reference for all purposes.
A differential clock #_5A2 accompanies read and write data packets. (In one embodiment, such clocked packets have a minimum burst length of 4 clock phases (“4N”)). The two sets of DCLKs #_5A2 allow one circuit component #_510, #_520 to pass control of the data link #_5A0 to another component #_510, #_520 with minimum gap.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3735277 *May 27, 1971May 22, 1973North American RockwellMultiple phase clock generator circuitUS3883853 *Aug 2, 1973May 13, 1975Burroughs CorpAddress generator for rotating data storage devicesUS4366538 *Oct 31, 1980Dec 28, 1982Honeywell Information Systems Inc.Memory controller with queue control apparatusUS4371928 *Apr 15, 1980Feb 1, 1983Honeywell Information Systems Inc.Interface for controlling information transfers between main data processing systems units and a central subsystemUS4503494 *Jun 26, 1980Mar 5, 1985Texas Instruments IncorporatedNon-volatile memory systemUS5058051 *Jul 29, 1988Oct 15, 1991Texas Medical Instruments, Inc.Address register processor systemUS5394541 *Dec 20, 1991Feb 28, 1995Sun Microsystems, Inc.Programmable memory timing method and apparatus for programmably generating generic and then type specific memory timing signalsUS5428804 *Dec 18, 1992Jun 27, 1995Xerox CorporationEdge crossing circuitry for SIMD architectureUS5696730 *Jun 13, 1996Dec 9, 1997Waferscale Integration Inc.First read cycle circuit for semiconductor memory* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7142605 *Sep 5, 2001Nov 28, 2006Texas Instruments IncorporatedMethod to transfer data without a clock or strobe signalUS20030091117 *Sep 5, 2001May 15, 2003Keith KrasnanskyMethod to transfer data without a clock or strobe signalUS20070283104 *May 31, 2006Dec 6, 2007International Business Machines CorporationConcurrent Hardware Selftest for Central Storage* Cited by examinerClassifications U.S. Classification710/58, 710/33, 711/167, 710/52, 710/61, 711/217, 710/60, 711/157, 711/220, 711/169, 711/4, 711/170, 711/168International ClassificationG11C7/22, G11C7/10, G06F13/42Cooperative ClassificationG06F13/4243, G11C7/1057, G11C7/1087, G11C7/1051, G11C7/1066, G11C7/22, G11C7/109, G11C2207/2254, G11C7/10, G11C7/1072, G11C7/106, G11C7/1012, G11C7/1078European ClassificationG11C7/10L3, G11C7/10W3, G11C7/10W5, G11C7/10R2, G11C7/10R7, G11C7/10R3, G11C7/22, G11C7/10R, G06F13/42C3S, G11C7/10, G11C7/10S, G11C7/10WLegal EventsDateCodeEventDescriptionDec 18, 2000ASAssignmentOwner name: SLDRAM, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MILLAR, BRUCE;O CONNELL, CORMAC;GILLINGHAM, PETER;REEL/FRAME:011397/0952Effective date: 19980527Jan 5, 2005REMIMaintenance fee reminder mailedJun 20, 2005LAPSLapse for failure to pay maintenance feesAug 16, 2005FPExpired due to failure to pay maintenance feeEffective date: 20050619RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services