Source: http://www.google.com/patents/US6717179?dq=6106459
Timestamp: 2017-07-26 09:45:57
Document Index: 764521355

Matched Legal Cases: ['application No. 09', 'application No. 09', 'application No. 10', 'application No. 11', 'application No. 11', 'application No. 7', 'application No. 7', 'application No. 7', 'application No. 8', 'application No. 09', 'application No. 09', 'application No. 09']

Patent US6717179 - Semiconductor device and semiconductor display device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor device includes a control circuit for carrying out gamma correction of a supplied signal, and a memory for storing data used in the gamma correction. The control circuit and the memory are constituted by TFTs, and are integrally formed on the same insulating substrate. A semiconductor...http://www.google.com/patents/US6717179?utm_source=gb-gplus-sharePatent US6717179 - Semiconductor device and semiconductor display deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6717179 B1Publication typeGrantApplication numberUS 09/540,639Publication dateApr 6, 2004Filing dateMar 31, 2000Priority dateAug 19, 1997Fee statusPaidPublication number09540639, 540639, US 6717179 B1, US 6717179B1, US-B1-6717179, US6717179 B1, US6717179B1InventorsShunpei Yamazaki, Jun KoyamaOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (65), Non-Patent Citations (15), Referenced by (33), Classifications (26), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and semiconductor display device
3. A device according to claim 1 wherein an active layer of each of the TFTs contains an element selected from the group consisting of carbon, nitrogen, oxygen and sulphur, and concentration of the element therein is less than 5×1018 atoms/cm3.
7. A device according to claim 5 wherein an active layer of each of the TFTs contains an element selected from the group consisting of carbon, nitrogen, oxygen and sulphur, and concentration of the element therein is less than 5×1018 atoms/cm3.
13. A device according to claim 11 wherein the first and second semiconductor layers contain an element selected from the group consisting of carbon, nitrogen, oxygen and sulphur, and concentration of the element therein is less than 5×1018 atoms/cm3.
18. A device according to claim 16 wherein the first and second semiconductor layers contain an element selected from the group consisting of carbon, nitrogen, oxygen and sulphur, and concentration of the element therein in less than 5×1018 atoms/cm3.
23. A device according to claim 21 wherein the first and second semiconductor layers contain an element selected from the group consisting of carbon, nitrogen, oxygen and sulphur, and concentration of the element therein is less than 5×1018 atmos/cm3.
28. A device according to claim 26 wherein the first and second semiconductor layers contain an element selected from the group consisting of carbon, nitrogen, oxygen and sulphur, and concentration of the element therein is less than 5×1018 atoms/cm3.
33. A device according to claim 31 wherein the first and second semiconductor layers contain an element selected from the group consisting of carbon, nitrogen, oxygen and sulphur, and concentration of the element therein is less than 5×1018 atoms/cm3.
38. A device according to claim 36 wherein the first and second semiconductor layers contain an element selected from the group consisting of carbon, nitrogen, oxygen and sulphur, and concentration of the element therein is less than 5×1018 atoms/cm3.
45. A device according to claim 43 wherein the first and second semiconductor layers contain an element selected from the group consisting of carbon, nitrogen, oxygen and sulphur, and concentration of the element therein is less than 5×1018 atoms/cm3.
a memory for storing data; and a logic circuit for controlling the data, wherein the memory and the logic circuit are constituted by TFTs, and are integrally disposed over a same insulating substrate, and wherein an active layer of each of the TFTs contains an element selected from the group consisting of carbon, nitrogen, oxygen and sulphur, and concentration of the element therein is less than 5×1018 atoms/cm3.
Reference numeral 108 denotes a pixel region which is constituted by a plurality of thin film transistors (TFTs) arranged in matrix. The pixel region 108 is also called a pixel matrix circuit. In this embodiment, the number of pixels was made 1024×768 in length and breadth. Although explanation will be made with respect to a liquid crystal display device having the foregoing number of the pixels in this embodiment, the present invention is not limited to the liquid crystal display device having the foregoing number of the pixels.
Next, the operation of the liquid crystal display device of this embodiment will be described. Reference will be made to FIG. 2. FIG. 2 is a schematic structural view showing the memory 105 of this embodiment. The memory 105 of this embodiment is constituted by a plurality of memory elements, and X- and Y-address decoders 201 and 202. As shown in FIG. 2, a storage element (memory element) for recording each bit information is constituted by two TFTs. One is a P-channel FAMOS (Floating gate Avalanche injection MOS) type nonvolatile memory element Tr1 having a floating gate and the other is an N-channel switching element Tr2. In the two TFTs Tr1 and Tr2, the drain electrodes are connected in series with each other, and this series connection circuit constitutes a one-bit memory element. Memory elements of 64×64 in length and breadth, each of which is made of the foregoing one-bit memory element, are arranged in matrix. Since each memory element can store one-bit information, the memory 105 in this embodiment has a storage capacity of 4096 bits (=about 4K bits).
In this embodiment, management is made so that the concentration of each of C (carbon), N (nitrogen), O (oxygen), and S (sulfur), which are typical impurities in the amorphous silicon film 402, becomes less than 5×1018 atoms/cm3 (preferably not larger than 1×1018 atoms/cm3). It is because if the concentration of any one of the impurities exceeds the above value, the impurity may have a bad influence on the film at crystallization and may cause the film quality to be degraded after the crystallization.
Next, after the adding step of the catalytic element is ended, dehydrogenating is carried out at about 450° C. for 1 hour, and then a heat treatment is carried out in an inert gas atmosphere, a hydrogen atmosphere, or an oxygen atmosphere at a temperature of 500 to 700° C. (typically 550 to 650° C.) for 4 to 24 hours to crystallize the amorphous silicon film 402. In this embodiment, a heat treatment is carried out in a nitrogen atmosphere, at 570° C., and for 14 hours.
Thus, in this embodiment, the heat treatment is carried out at a temperature exceeding 700° C., preferably 800 to 1000° C. (typically 950° C.), and a processing time is made 0.1 to 6 hours, typically 0.5 to 1 hour.
In this embodiment, an example is shown in which a heat treatment is carried out in an oxygen atmosphere containing hydrogen chlorine (HCl) of 0.5 to 10 vol % (in this embodiment, 3 vol %) at 950° C. for 30 minutes. If the concentration of HCl is higher than the above-mentioned concentration, roughness comparable to a film thickness is produced on the surfaces of the active layers 409, 410 and 411. Thus, such a high concentration is not preferable.
In this step, it is conceivable that nickel is removed in such a manner that nickel in the active layers 409, 410 and 411 is gettered by the action of chlorine and is transformed into volatile nickel chloride which is released into the air. By this step, the concentration of nickel in the active layers 409, 410 and 411 is lowered down to 5×1017 atoms/cm3 or less.
Incidentally, the value of 5×1017 atoms/cm3 is the lower limit of detection in the SIMS (Secondary Ion Mass Spectroscopy). As a result of analysis of TFTs experimentally produced by the present inventors, when the concentration is not higher than 1×1018 atoms/cm3 (preferably 5×1017 atoms/cm3 or less), the influence of nickel upon TFT characteristics can not be seen. However, it should be noted that the concentration of an impurity in the present specification is defined as a minimum value in measurement results of the SIMS analysis.
As a result of the SIMS analysis for other elements, it was confirmed that the concentration of any of C (carbon), N (nitrogen), O (oxygen), and S (sulfur) as typical impurities was less than 5×1018 atoms/cm3 (typically 1×1018 atoms/cm3 or less).
In this embodiment, the addition of impurity is divided and is carried out two times. The first impurity addition (P (phosphorus) is used in this embodiment) is carried out at a high acceleration voltage of about 80 KeV to form an n− region. Adjustment is made so that the concentration of p ion impurity in the n− region becomes 1×1018 to 1×1019 atoms/cm3.
Here, a semiconductor thin film manufactured by a manufacturing method of this embodiment will be described. According to the manufacturing method of this embodiment, it is possible to obtain a crystalline silicon film called by the present applicant “continuous grain boundary crystalline silicon (so-called Continuous Grain Silicon: CGS)” by crystallizing an amorphous silicon film.
The difference in the number of defects appears as the difference in spin density by the analysis of ESR (Electron Spin Resonance). In the present circumstances, it is ascertained that the spin density of the crystalline silicon film by the manufacturing method of this embodiment is at most 5×1017 spins/cm3 (preferably 3×1017 spins/cm3 or less). However, since this measurement value is near the detection limit of an existing measuring device, it is expected that the actual spin density is lower than the value.
Incidentally, in the formation of the CGS, the foregoing annealing step at a temperature above crystallizing temperature (700 to 1100°) plays an important role with respect to lowering of defects in the crystal grain. This will be described below.
The present inventors consider also a model in which the crystalline silicon film is bonded to its under layer by a heat treatment at a temperature (700 to 1100° C.) above the crystallizing temperature and adhesiveness is increased, so that the defects disappear.
The continuity of crystal lattices in the crystal grain boundary is caused from the fact that the crystal grain boundary is a grain boundary called “plane grain boundary”. The definition of the plane grain boundary in the present specification is given as “Planar boundary” set forth in “Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol. 27, No. 5, pp. 751-758, 1988”.
Reference will be made to FIG. 10. Reference numeral 1001 denotes an analog signal supply source for supplying an analog picture signal such as a video signal or a television signal. Reference numeral 1002 denotes a gamma correction control circuit for gamma correcting the analog signal supplied from the analog picture signal supply source 1001. Reference numeral 1003 denotes a D/A conversion circuit, and 1004 denotes a memory. The memory 1004 is similar to that in the Embodiment 1. Reference numeral 1005 denotes a source signal line side driver, and 1006 denotes a gate signal line side driver. Reference numeral 1007 denotes a pixel region which is constituted by a plurality of thin film transistors (TFTs) arranged in matrix. The pixel region 1007 is also called a pixel matrix circuit. In this embodiment, the number of pixels is made 1024×768 in length and breadth. In this embodiment, although the liquid crystal display device having the foregoing number of pixels will be described, the present invention is not limited to the liquid crystal display device having the foregoing number of pixels.
If Ta or Ta alloy is used for the gate electrode, it is possible to carry out thermal oxidation at about 450° C. to about 600° C., so that an oxide film having excellent film quality, such as a Ta2O3 film, is formed on the gate electrode. It is known that this oxide film has a film quality better than that of the oxide film formed when Al (aluminum) is used for the gate electrode as described in the above embodiment 1.
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