Source: http://www.google.com/patents/US5918043?dq=oakley+D523,461&ei=qiI4T-CjGqXf0QHz_PSUCA
Timestamp: 2017-11-19 15:50:54
Document Index: 327985037

Matched Legal Cases: ['Application No. 297630', 'Application No. 297630', 'Application No. 1', 'Application No. 1', 'Application No. 1', 'Application No. 1', 'Application No. 3', 'Application No. 3', 'Application No. 4', 'Application No. 4']

Patent US5918043 - Method and apparatus for asynchronously stopping the clock in a processor - Google Patents
An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes...http://www.google.com/patents/US5918043?utm_source=gb-gplus-sharePatent US5918043 - Method and apparatus for asynchronously stopping the clock in a processor
Publication number US5918043 A
Application number US 08/874,559
Also published as US5473767, US5560001, US5560002, US5657483
Publication number 08874559, 874559, US 5918043 A, US 5918043A, US-A-5918043, US5918043 A, US5918043A
Patent Citations (90), Non-Patent Citations (24), Referenced by (10), Classifications (16), Legal Events (3)
Method and apparatus for asynchronously stopping the clock in a processor
US 5918043 A
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EP0451661A2 * Mar 30, 1991 Oct 16, 1991 Matsushita Electric Industrial Co., Ltd. Low power consumption microprocessor
JPH01131934A * Title not available
JPH03161815A * Title not available
JPH04148403A * Title not available
1 * (Translation of) Japanese Office Action for Patent Application No. 297630/ 93, dated Nov. 18, 1997.
2 (Translation of) Japanese Office Action for Patent Application No. 297630/'93, dated Nov. 18, 1997.
3 Case, Brian, "R4000 Extends R3000 Architecture with 64-bit Capabilities", Microprocessor Report, vol. V5 No. N19, p. 10(4), Oct. 16, 1991.
4 * Case, Brian, R4000 Extends R3000 Architecture with 64 bit Capabilities , Microprocessor Report, vol. V5 No. N19, p. 10(4), Oct. 16, 1991.
5 * Complete English Translation of Japanese Patent Application No. 1 131934.
6 Complete English Translation of Japanese Patent Application No. 1-131934.
7 IBM Technical Disclosure Bulletin, "Multiple Phase Clock Generation From a Single Oscillator", vol. 33, No. 6B, p. 322-325, Nov. 1990, Armonk, New York.
8 * IBM Technical Disclosure Bulletin, Multiple Phase Clock Generation From a Single Oscillator , vol. 33, No. 6B, p. 322 325, Nov. 1990, Armonk, New York.
9 Intel Automotive Components Handbook "Power-On Reset", 1988, p. 10-24 and 10-25.
10 * Intel Automotive Components Handbook Power On Reset , 1988, p. 10 24 and 10 25.
11 * Motorola MC6802032 Bit Microprocessor User s Manual, 3rd Edition, 1990, p. 1.
12 Motorola MC6802032--Bit Microprocessor User's Manual, 3rd Edition, 1990, p. 1.
13 Slater, Michael, "MIPS Previews 64-bit R4000 Architecture", Microprocessor Report, vol. V5 , No. N2, p. 1(6), Feb. 6, 1991.
14 * Slater, Michael, MIPS Previews 64 bit R4000 Architecture , Microprocessor Report, vol. V5 , No. N2, p. 1(6), Feb. 6, 1991.
15 * Translation of Abstract Japanese Patent Application No. 1 131934.
16 Translation of Abstract Japanese Patent Application No. 1-131934.
17 * Translation of Abstract of Japanese Patent Application No. 3 161815.
18 Translation of Abstract of Japanese Patent Application No. 3-161815.
19 * Translation of Abstract of Japanese Patent Application No. 4 148403.
20 Translation of Abstract of Japanese Patent Application No. 4-148403.
21 Wescon/89 Conference Record, Nov. 14, 1989, San Francisco, CA, "The VL86C020 RISC with On-Board Cache", pp. 251-254.
22 * Wescon/89 Conference Record, Nov. 14, 1989, San Francisco, CA, The VL86C020 RISC with On Board Cache , pp. 251 254.
23 Wilson, Ron, "MIPS Rethinks RISC with Superpipelining", Computer Design, vol. V30 No. N3, p. 28(3), Feb. 1, 1991.
24 * Wilson, Ron, MIPS Rethinks RISC with Superpipelining , Computer Design, vol. V30 No. N3, p. 28(3), Feb. 1, 1991.
US6754814 * Dec 16, 1999 Jun 22, 2004 Fujitsu Limited Instruction processing apparatus using a microprogram that implements a re-reading operation by controlling early loading of instructions
US6914459 * Jun 1, 2004 Jul 5, 2005 Broadcom Corporation Clock multiplier using masked control of clock pulses
US20040217791 * Jun 1, 2004 Nov 4, 2004 Haluk Konuk Programmable frequency multiplier
US20050218957 * Jun 7, 2005 Oct 6, 2005 Haluk Konuk Programmable frequency multiplier
International Classification G06F11/00, G06F11/267, G06F1/10, G06F1/26, G06F1/04
Cooperative Classification G06F1/26, G06F11/2236, G06F1/04, G06F11/004, G06F1/10
European Classification G06F1/26, G06F11/00H, G06F11/22A12, G06F1/10, G06F1/04