Source: http://www.google.com/patents/US7934023?dq=4200770
Timestamp: 2014-07-24 15:56:03
Document Index: 695082030

Matched Legal Cases: ['Application No. 2002361837', 'Application No. 2004311001', 'Application No. 2003238219', 'Application No. 2', 'Application No. 200480033685', 'Application No. 200480033685', 'Application No. 200480033685', 'Application No. 02797469', 'Application No. 02828446', 'Application No. 2003', 'Application No. 10']

Patent US7934023 - Apparatus and method for performing fast fibre channel write operations over ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA method and apparatus to improve the performance of a SCSI write over a high latency network. The apparatus includes a first Switch close to the initiator in a first SAN and a second Switch close to the target in a second SAN. In various embodiments, the two Switches are border switches connecting their...http://www.google.com/patents/US7934023?utm_source=gb-gplus-sharePatent US7934023 - Apparatus and method for performing fast fibre channel write operations over relatively high latency networksAdvanced Patent SearchPublication numberUS7934023 B2Publication typeGrantApplication numberUS 10/726,269Publication dateApr 26, 2011Filing dateDec 1, 2003Priority dateDec 1, 2003Also published asCA2546783A1, CA2546783C, CN1918925A, CN1918925B, EP1690359A2, EP1690359A4, US20050117522, WO2005055497A2, WO2005055497A3Publication number10726269, 726269, US 7934023 B2, US 7934023B2, US-B2-7934023, US7934023 B2, US7934023B2InventorsMurali Basavaiah, Satish Ambati, Magesh Iyengar, Thomas Edsall, Dinesh G. Dutt, Silvano Gai, Varagur V. ChandrasekaranOriginal AssigneeCisco Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (88), Non-Patent Citations (60), Referenced by (2), Classifications (18), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetApparatus and method for performing fast fibre channel write operations over relatively high latency networksUS 7934023 B2Abstract A method and apparatus to improve the performance of a SCSI write over a high latency network. The apparatus includes a first Switch close to the initiator in a first SAN and a second Switch close to the target in a second SAN. In various embodiments, the two Switches are border switches connecting their respective SANs to a relatively high latency network between the two SANs. In addition, the initiator can be either directly connected or indirectly connected to the first Switch in the first SAN. The target can also be either directly or indirectly connected to the second Switch in the second SAN. During operation, the method includes the first Switch sending Transfer Ready (Xfr_rdy) frame(s) based on buffer availability to the initiating Host in response to a SCSI Write command from the Host directed to the target. The first and second Switches then coordinate with one another by sending Transfer Ready commands to each other independent of the target's knowledge. The second switch buffers the data received from the Host until the target indicates it is ready to receive the data. Since the Switches send frames to the initiating Host independent of the target, the Switches manipulate the OX_ID and RX_ID fields in the Fiber Channel header of the various commands associated with the SCSI Write. The OX_ID and RX_ID fields are manipulated so as to trap the commands and so that the Switches can keep track of the various commands associated with the SCSI write.
FIELD OF THE INVENTION The present invention relates generally to network communications, and more particularly, to an apparatus and method for performing fast Fibre Channel write operations over relatively high latency networks.
BACKGROUND OF THE INVENTION With the increasing popularity of Internet commerce and network centric computing, businesses and other organizations are becoming more and more reliant on information. To handle all of this data, storage area networks or SANs have become very popular. A SAN typically includes a number of storage devices, a plurality of Hosts, and a number of Switches arranged in a Switching Fabric that connects the storage devices and the Hosts.
SUMMARY OF THE INVENTION To achieve the foregoing and other objectives and in accordance with the purpose of the present invention, an apparatus and method to improve the performance of a SCSI write over a high latency network is provided. The apparatus includes a first Switch close to the initiator in a first SAN and a second Switch close to the target in a second SAN. In various embodiments, the two Switches are border switches connecting their respective SANs to a relatively high latency network between the two SANs. In addition, the initiator can be either directly connected or indirectly connected to the first Switch in the first SAN. The target can also be either directly or indirectly connected to the second Switch in the second SAN. During operation, the method includes the first Switch sending Transfer Ready (Xfr_rdy) frame(s) based on buffer availability to the initiating Host in response to a SCSI Write command from the Host directed to the target. The first and second Switches then coordinate with one another by sending Transfer Ready commands to each other independent of the target's knowledge. The second switch buffers the data received from the Host until the target indicates it is ready to receive the data. Since the Switches send frames to the initiating Host independent of the target, the Switches manipulate the OX_ID and RX_ID fields in the Fibre Channel header of the various commands associated with the SCSI Write. The OX_ID and RX_ID fields are manipulated so as to trap the commands and so that the Switches can keep track of the various commands associated with the SCSI write.
BRIEF DESCRIPTION OF THE DRAWINGS The features of the present invention may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings.
DETAILED DESCRIPTION OF THE INVENTION Referring to FIG. 1, a diagram of a high latency inter-SAN network 10 connecting a Host H1 in a first SAN 12 and a target storage device T1 in a second SAN 14 is shown. The Host H1 is coupled to the high latency network 10 through a first switch SW1 in SAN 12. The target storage device T1 is coupled to the network 10 through a second switch SW2. The switches SW1 and SW2 are considered �border� switches since they are positioned at the interface of the network 10 and the SANs 12 and 14 respectively. According to various embodiments, the Host H1 and target T1 may be either directly connected to switches SW1 and SW2 or connected indirectly through any number of intermediate switches respectively. The network 10 may use the Internet Protocol (IP) for example over an inter-SAN link such as Gigabit Ethernet, SONET, ATM, wave division multiplexing, etc. to connect the SANs 12 and 14. Again, the network 10 may have a high latency relative to the SANs 12 and 14 for a variety of reasons, such as the speed of the link, congestion on the link, or distance.
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ISBN: 0-7803-5794-9; pp. 642-648.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8694691 *Sep 27, 2012Apr 8, 2014Marvell World Trade Ltd.Systems and methods for creating bidirectional communication channels using block devicesUS20130080664 *Sep 27, 2012Mar 28, 2013Marvell International Ltd.Systems and methods for creating bidirectional communication channels using block devices* Cited by examinerClassifications U.S. Classification710/5, 370/252, 370/230, 711/114International ClassificationH04L12/26, G06F3/06, G06F3/00, H04L, H04L29/08Cooperative ClassificationH04L67/1097, G06F3/067, G06F3/0659, G06F3/0635, G06F3/0613European ClassificationG06F3/06A4C6, G06F3/06A4T6, G06F3/06A2P4, G06F3/06A6DLegal EventsDateCodeEventDescriptionJun 27, 2005ASAssignmentOwner name: CISCO TECHNOLOGY, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CISCO SYSTEMS, INC.;REEL/FRAME:016741/0616Effective date: 20040219Owner name: CISCO TECHNOLOGY, INC.,CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CISCO SYSTEMS, INC.;US-ASSIGNMENT DATABASE UPDATED:20100203;REEL/FRAME:16741/616Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CISCO SYSTEMS, INC.;REEL/FRAME:16741/616Jul 6, 2004ASAssignmentOwner name: CISCO SYSTEMS, INC., CALIFORNIAFree format text: MERGER;ASSIGNOR:ANDIAMO SYSTEMS, INC.;REEL/FRAME:014849/0935Effective date: 20040219Owner name: CISCO SYSTEMS, INC.,CALIFORNIAFree format text: MERGER;ASSIGNOR:ANDIAMO SYSTEMS, INC.;US-ASSIGNMENT DATABASE UPDATED:20100203;REEL/FRAME:14849/935Free format text: MERGER;ASSIGNOR:ANDIAMO SYSTEMS, INC.;REEL/FRAME:14849/935Jun 1, 2004ASAssignmentOwner name: CISCO TECHNOLOGY, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BASAVAIAH, MURALI;AMBATI, SATISH;IYENGAR, MAGESH;AND OTHERS;REEL/FRAME:014681/0422;SIGNING DATES FROM 20040506 TO 20040517Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BASAVAIAH, MURALI;AMBATI, SATISH;IYENGAR, MAGESH;AND OTHERS;SIGNING DATES FROM 20040506 TO 20040517;REEL/FRAME:014681/0422RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google