Source: http://www.google.com/patents/US4953224?ie=ISO-8859-1&dq=6078894
Timestamp: 2014-07-12 12:15:21
Document Index: 187922993

Matched Legal Cases: ['art 14', 'art 4', 'art 6', 'art 14', 'art 4', 'art 6', 'art 14', 'art 4', 'art 6', 'art 4', 'art 6', 'art 6', 'art 1', 'art 4', 'art 14', 'art 1', 'art 4', 'art 6', 'art 14', 'art 1', 'art 4', 'art 6', 'art 14', 'art 14', 'art 4', 'art 6', 'art 4', 'art 6', 'art 14', 'art 4', 'art 6', 'art 14', 'art 14', 'art 6', 'art 14', 'art 6', 'art 1', 'art 4', 'art 6', 'art 14', 'in fine']

Patent US4953224 - Pattern defects detection method and apparatus - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA pattern defect detecting method and apparatus are disclosed on a connectivity processor to input a binary picture signal pattern and a pad position coordinate and outputting connectivity data between pads. Here, the connectivity processing refers to a processing for giving the identical number to one...http://www.google.com/patents/US4953224?utm_source=gb-gplus-sharePatent US4953224 - Pattern defects detection method and apparatusAdvanced Patent SearchPublication numberUS4953224 APublication typeGrantApplication numberUS 07/158,125Publication dateAug 28, 1990Filing dateFeb 16, 1988Priority dateSep 27, 1984Fee statusPaidPublication number07158125, 158125, US 4953224 A, US 4953224A, US-A-4953224, US4953224 A, US4953224AInventorsToshiaki Ichinose, Takanori Ninomiya, Yasuo NakagawaOriginal AssigneeHitachi, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (14), Referenced by (47), Classifications (6), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetPattern defects detection method and apparatusUS 4953224 AAbstract A pattern defect detecting method and apparatus are disclosed on a connectivity processor to input a binary picture signal pattern and a pad position coordinate and outputting connectivity data between pads. Here, the connectivity processing refers to a processing for giving the identical number to one aggregation of connected or linked pads for the pads given to a serial pattern. In the connectivity processor wherein a plane on which the drawn pattern to be inspected is scanned by a linear sensor, the connectivity processing can be releazed almost concurrently with the scanning by driving a temporary memory.
What is claimed is: 1. An apparatus for detecting a defect of a pattern comprising:image pickup means for sensing an optical image of a pattern on an XY plane by scanning individual lines along the X-direction and line-by-line along a subscanning Y-direction for providing an electrical image signal; a binary digitizing circuit which transforms said electrical image signal into corresponding binary signals representing picture elements; a connection data generator including:a pad position table memory for storing pad position coordinates (Xi, Yi) with representative pad numbers Ni, line segment generation means for generating a start position u and an end position v, in the X coordinate, of a line segment of the pattern detected along a main scanning line, pad number assigning means for assigning said pad number Ni as labels to a line segment when said pad position coordinates (Xi, Yi) satisfy a condition u≦Xi≦v, labelling means for determining that a label representation M corresponds to the minimum label value representation of a first label value M0 and a second label value M1 when a corresponding first line segment is determined as being connected along the subscanning direction Y to a corresponding second line segment, said first label M0 and second label M1 correspond to the detection of line segments, as represented by pad numbers Ni, detected along respective adjacent scanning lines, and wherein said label representation M corresponds to a label value M2 when said first line segment is connected to said second line segment and one of said two line segments has the label value representation M2 and the other one of said line segments has no representative label value assigned, and assigning M to said first and second line segments, and a connectivity table memory for storing the connection data signals representative of a connectivity relationship expressed by said minimum label signal M as a data D(I) corresponding to address A(I) of said first and second label signals M0 and M1, respectively, showing said pad positions; and comparison means for comparing said connection data signals read out from said connectivity table memory of said connection data generator with design data signals expressed in the form of a cyclic list of symbols assigned to pads in the connectivity relationship, whereby a determination of a defect of the pattern is made based on the output of said comparison means. 2. An apparatus according to claim 1, wherein said pattern comprises a wiring pattern.
7. An apparatus for detecting a defect of a pattern comprising:image pickup means for sensing optical images of both a reference circuit pattern, being provided prior to effecting a defect detection process, and a corresponding circuit pattern for inspection on an XY plane by scanning individual lines along the X-direction and line-by-line along a subscanning Y-direction direction for providing electrical image signals representative of both said reference circuit pattern and said circuit pattern for inspection; a binary digitizing circuit which transforms said electrical image signals representative of both said reference circuit pattern and said circuit pattern for inspection into corresponding binary signals representing picture elements of both; a connection data generator including:a pad position table memory for storing pad position coordinates (Xi, Yi) with representative pad numbers Ni, line segment generation means for generating a start position u and an end position v, in the X coordinate, of a line segment detected along a main scanning line of both circuit patterns,pad number assigning means for assigning said pad number Ni as labels to a line segment of each of said circuit patterns when said pad position coordinates (Xi, Yi) satisfy a condition u≦Xi≦v and Yi=Y coordinate of said main scanning line, labeling means for determining that a label representation M corresponds to the minimum label value representation of a first label value M0 and a second label value M1 when a corresponding first line segment of each of said circuit patterns is determined as being connected along the subscanning direction Y to a corresponding second line segment of each of said circuit patterns, said first label M0 and second label M1 correspond to the detection of line segments as represented by pad numbers Ni, detected along respective adjacent scanning lines, and wherein said label representation M corresponds to a label value M2 when said first line segment is connected to said second line segment and one of said two line segments has the label value representation M2 and the other one of said line segments has no representative label value assigned, and assigning M to said first and second line segments of each of said circuit patterns, and a connectivity table memory for storing the connection data signals representative of a connectivity relationship expressed by said minimum label signal M as a data D(1) corresponding to address A(1) of said first and second label signals M0 and M1, respectively, showing said pad positions of each of said circuit patterns; design data generating means for converting said connection data signals read out from said connectivity table memory of said connection data generator and produced with respect to said reference circuit pattern, prior to said defect detection process, into corresponding design data expressed in the form of a circulation list of pad numbers Ni assigned to pads in the connectivity relationship representative of said reference circuit pattern; design data storing means for storing said design data; and comparison means for comparing said connection data signals read out from said connectivity table memory of said connection data generator and being produced with respect to said circuit pattern for inspection with said corresponding design data signals read out from said design data storing means which are representative of said reference circuit pattern, whereby a determination of the defect of the inspecting circuit pattern is made based on the output of said comparison means. Description
BACKGROUND OF THE INVENTION 1. Field Application of the Invention
SUMMARY OF THE INVENTION One object of the invention is to provide a connectivity detecting method and apparatus capable of detecting whether a plurality of points specified externally on the pattern of a detected binary picture image are concatenated through the pattern without increasing memory capacity. To attain the object, a different number (a pad number subsequently given) is assigned to each of the points to be detected for connectivity and coordinated with the address in memory, and when some point is found on any pattern, the number of the point is given as a label or pad numbers for the pattern, which is written as data at the address correspond to corresponding to the point, and when different labels are given to any same patterns, these are rewritten to one of them in the memory according to a predetermined method, so that the arbitrary two points are judged to be connected only when the labels loaded in the coordinated address are the same.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a general block diagram of a connectivity processor in a pattern defect detecting apparatus given in one embodiment of this invention;
DETAILED DESCRIPTION OF THE INVENTION This invention refines the prior U.S. patent application Ser. No. 600957, now U.S. Pat. No. 4,654,583 which is descriptive of a connectivity detecting art in the former half and a pattern defect detecting art for which the art commands a main part in the latter half.
<LABELING> As described above, a label is assigned to a detected pattern, and the label is further rewritten to a normal processing, which is represented on the drawings, and a specific method for labeling the pattern will now be described.
vjt &#8807;uit-1 and vit-1 &#8807;ujt(1)
<EPTIOME OF CONSTRUCTION AND OPERATION OF THE APPARATUS> Now, the connectivity detecting apparatus according to this invention will be described specifically. FIG. 1 represents a general construction given in one example. Detailed descriptions of the preferred embodiments and the operation thereof will now be described.
<INITIALIZATION> Prior to starting a process, specific point position coordinates (xi, yi) and a pad number Ni corresponding thereto are input to the pad position table memory 10 through the interface circuit 11. FIG. 24 shows the storing format of the specific point position coordinates (xi, yi) on the pad position table memory 10 and the grid number Ni. In this case, the order in which data is written into the pad position table memory 10 is y1 ≦y2 ≦. . .≦yi ≦yi+1. . . , and . . .<xi <xi+ <. . . for the same yi. That is, the data of the specific point position is sorted in the order of picture detection. Next, the line buffer memories 3A, 3B (FIG. 1), the connectivity table memory 12, the flag memory 15, the switching circuits 2, 7 and the line table memories 8A to 8C are initialized, and further the number of lines according to the size of a processing area is set to the labeling part 14 externally through the interface circuit 11. A processing is started after the above initialization.
<PARALLEL PROCESSING> In accordance with a process start, a binary picture signal is input alternately to the two line buffer memories 3A, 3B as shown in TABLE 1, and the code conversion part 4 operates to detect a segment and addresses its start and end with the content of the line buffer memory to which a picture image is not input currently as an input. Then, in parallel with the above processings, the start point and end point addresses of the segment and the label are input cyclically to one of the three line table memories 8A to 8C from the pad number assigner part 6 as shown in TABLE 2, and the labeling part 14 operates for labeling with a content of the remaining two line buffer memories as an input. Accordingly, if the code conversion part 4 and the pad number assigner part 6 operate for the t-th line processing, then the picture input operates to the t+1-th line and the labeling part 14 operates to the t-2-th line. Thus, the above-mentioned three operations can be realized in parallel perfectly without being subjected to interference by changing the switching circuits 2, 7 at every boundary line of the input picture image, thereby ensuring high-speed processing. Then, since FIFO is provided between the code conversion part 4 and the pad number assigner part 6, code conversion and grid number assignment can be realized nonsynchronously and parallel in part, so that these portions can be processed at high speed. It is evident that, buffer memories 17A, 17B and a switching circuit 16 can be provided instead of FIFO as shown in FIG. 25, and from effecting input and output operations alternately as in the case of line buffer memories 3A, 3B, a perfect parallel processing of the code conversion part 4 and the pad number assigner part 6 can be realized. In this case, if the pad number assigner part 6 is in processing of the t-th line, then the picture input part 1, the code conversion part 4 and the labeling part 14 will be in processing of the t+2-th, t+1-th, t-1-th and t-2-th lines respectively.
<RATE DETERMINING PROCESS> A processing rate of the apparatus according to this invention is determined on the portion for which processing time is most required of those which operate in parallel with each other like the picture input part 1, the code conversion part 4, the pad number assigner part 6, the labeling part 14. Then, the picture input part 1 of those which are mentioned above is operable for real-time input at a specific rate determined only on a speed of the line buffer memories 3A, 3B and a speed of a peripheral circuit such as switching circuit 2 or the like. In the case of code conversion part 4, pad number assigner part 6, and lableing part 14, the processing time varies according to a complexity of the input binary picture pattern. As will be described later, processing is particularly complicated for labeling part 14 as compared with the code conversion part 4 and the pad number assigner part 6, therefore from interposing FIFO between the code conversion part 4 and the pad number assigner part 6 instead of buffer memories, the processing time per line at the portions will never be longer than the processing time per line at the labeling part 14 even if this processing is not carried out exactly in parallel. The matter on interposing FIFO of buffer memories selectively between the code conversion part 4 and the pad number assigner part 6 may depend on how to accelerate processing on the labeling part 14, which must be determined by simulation after specific circuit design.
≦COLLISION AVOIDANCE> As will be described hereinlater, the labeling part 14 and the pad number assigner part 6 are capable of writing or reading concurrently to the same connectivity table memory 12. Consequently, collisions will be avoided by the access control circuit 13. The controlling process is shown in FIG. 26. That is, periods of accessible time from the labeling part 14 and the pad number assigner part 6 are provided alternately. In this case, it is necessary to design τ in FIG. 26 or a circuit so that the sum of access time of the connection table memory 12 and delay time of the peripheral circuit will be shorter than τ. This method is one of known memory access methods, however, a comparatively simple circuit configuration is effective enough to realize access control according to the method. Needless to say, and other methods known hitherto can be used otherwise.
<CONSTRUCTION OF EACH PART> Next, construction and operation of the picture input part 1, the code conversion part 4, the pad number assigner part 6, and the lableing part 14 will be described in detail.
ui t-1 &#8806;vj t-2 and uj t-2 &#8806;vi t-1                                   (2).
&#8594;Normal
&#8594;Disconnected
&#8594;Short-circuited
<FIRST EMBODIMENT> The most basic embodiment of the pattern defect inspecting art relating to this invention will be described according to FIG. 38.
<SECOND EMBODIMENT> A second embodiment according to the invention will be described next. A construction of the system for putting the embodiment into practice is shown in FIG. 41. What is different from the foregoing embodiment (FIG. 38) is that a contraction processor 29 is inserted between the binary-coding device 22 and the connectivity processor 23, and other construction remains exactly the same.
One example of the contraction processor 29 is shown in FIG. 42. The processor comprises n-bit shift register 31 in (m2 -1) pieces and m1 -bit shift register 32 in m2 pieces. These shift registers are driven by the identical sampling clock. The n is made to coincide with a horizontal sampling number of the pickup device 21. Then, m1, m2 are determined by sampling time interval, vertical resolution of the pickup device and size of a defect to be detected. If, for example, the sampling time interval and the vertical resolution correspond to 10 μm each and the size of a defect is 30 μm square, then m1 =m2 =3 (FIG. 43). Then, an output of the m1 �m2 shift register 32 (FIG. 42) is led to AND circuit 33 and output to the connectivity processor 23 (FIG. 41). In FIG. 42, outputs of all the shift registers are extracted, however, they can be extracted selectively according to a shape of the defect to be detected. A result obtained through subjecting the binary pattern shown in FIG. 43 to a contraction processing on the system of FIG. 42 is shown in FIG. 44. A square with the shortest segment as one side represents one picture element.
<THIRD EMBODIMENT> A third embodiment will be described next. A construction of the system for putting the embodiment into practice is shown in FIG. 47. As will be apparent from the drawing, this embodiment combines the first embodiment (FIG. 38) and the second embodiment (FIG. 41). An attribute data detected from the pattern to be inspected shown in FIG. 45, and a defect decision result are shown in TABLE 9 together with the design data.
<FOURTH EMBODIMENT> Next, a fourth embodiment according to the invention will be described. A construction of the system for putting this embodiment into practice is shown in FIG. 48. What is different from the first embodiment (FIG. 38) is that the expansion processor 30 is inserted between the binary-coding device 22 and the connectivity processor 23, and other construction remains exactly the same. One example of the expansion processor 30 is shown in FIG. 49. This processor comprises the n-bit shift register 31 in (m2 -1) pieces and the m1 -bit shift register 32 in 32 m2 pieces. These shift registers are driven by the identical sampling clock. The n is made to coincide with a horizontal sampling number of the pickup device. Then, m1, m2 are determined by sampling time interval, vertical resolution of the pickup device 21 and size of a defect to be detected. If, for example, the sampling time interval and the vertical resolution correspond to 10 μm each and the size of a defect is 30 μm square, then m1 =m2 =3 (FIG. 49). Then, an output of the m1 �m2 shift register 32 is led to OR circuit 34 and output to the connectivity processor 23 (FIG. 48). In FIG. 49, outputs of all the shift registers 32 are led to OR circuit 34, however, they can be extracted selectively according to a shape of the defect to be detected. A result obtained through expanding the binary pattern shown in FIG. 43 on the device of FIG. 49 is shown in FIG. 50. Further, a pattern obtained through expanding the pattern to be inspected which is shown in FIG. 45 is shown in FIG. 51, and a connectivity data created through connectivity processing is shown in TABLE 10. In addition, an attribute data created similarly to the first embodiment and a defect decision result are shown in TABLE 11 together with the design data. As will be apparent from the result, a small pattern interval at a specified value (30 μm in the example) or below will be shortened and so detected. However, small short-circuited pattern intervals cannot be detected, and a fine disconnection may be overlooked. As described, according to this embodiment, a pattern defect detecting apparatus can be realized through a relatively simple construction only for detecting a short circuit and a small pattern interval without distinction.
<FIFTH EMBODIMENT> Next, a fifth embodiment will be described. A construction of the system for putting this embodiment into practice is shown in FIG. 52. As will be apparent from the drawing, the embodiment combines the first embodiment (FIG. 38) and the fourth embodiment (FIG. 48). An attribute data detected from the pattern to be inspected which is shown in FIG. 45 and a defect decision result are shown in TABLE 12. The system shown in FIG. 52 is that for which the system of FIG. 38 and that of FIG. 48 are combined, like parts in each of the figures are identified by the common reference numeral, and "a" attached to the reference numeral indicates belonging to a sequence for processing a source pattern as in the case of FIG. 47, and "c" indicates belonging to a sequence for processing an expanded pattern. The processing in each sequence is exactly the same as the processing in the first and fourth embodiments, however, as in the case of third embodiment, a processing for judging synthetically a decision result obtained from the source pattern and a decision result obtained from the expanded pattern is added finally.
<SIXTH EMBODIMENT> Next, a sixth embodiment according to the invention will be described. A construction of the system for putting the embodiment into practice is shown in FIG. 53. As will be apparent from the drawing, this embodiment combines the second embodiment (FIG. 41) and the fourth embodiment (FIG. 48). An attribute data detected from the pattern to be inspected shown in FIG. 45, and a defect decision result are shown in TABLE 13 together with the design data. The processing in the embodiment is exactly the same as the second and fourth embodiments. However, a processing for deciding synthetically a decision result obtained from the contracted pattern and a decision result obtained from the expanded pattern is added finally. That is, as shown in TABLE 14, a small pattern interval and a fine short circuit, a small pattern width and a fine disconnection cannot be distinguished from the two decision results, however, others can perfectly be detected distinctively and also not overlooked. Thus, according to the embodiment, perfect short circuit, perfect disconnection, small pattern interval or fine short circuit, small pattern width or fine disconnection can be detected distinctively.
<SEVENTH EMBODIMENT> A seventh embodiment according to this invention will be described next. A construction of the system for putting the embodiment into practice is shown in FIG. 54. As will be apparent from the drawing, this embodiment combines the first (FIG. 38), second (FIG. 41) and fourth (FIG. 48) embodiments. An attribute data detected from the pattern to be inspected, shown in FIG. 45, and a defect decision result are shown in TABLE 15 together with the design data.
<CONSIDERATION> Next, a memory capacity and a processing time necessary for the above-described seven embodiments will be taken up for consideration.
Assuming the pad is present at 256�256 points in one substrate, the memory capacity is calculated, first. In this case, the pad number can be represented in 16 bits (2 bytes). If all the pads are detected on connectivity processing, a created connectivity data is: ##EQU1## Then, design data is: ##EQU2##
Then, with reference to the processing time, a conversion from the connectivity data into a cyclic list structure will be performed one time only before inspection, therefore it can be excluded from the processing time, and thus it will be appreciated according to a reference frequency of the design data. If an average pad number on one connected pattern is n, then, assuming that all patterns are free from defect, an average reference frequency necessary for finding the root pad at the time of attribute data creation will be: ##EQU4## Accordingly, ##EQU5## at the time of 256�256 pads. Now, if there is a defect wherein the root pad cannot be found, the reference frequency is n+1 from ##EQU6## therefore: ##EQU7## If n=4, then a reference must be made to the design data 165,478.4 times. Further, since the reference will be made to all design data one time only, the reference is necessary at:
Particularly, a list structure is employed for the design data indicating a connectivity, therefore as compared with a representation in a connection matrix, data compression from 2562 �2562 ≈2.56�109 bits to 1.05�106 bits can be realized in the case, for example, for a 256�256 pad, and processing time can also sharply be decreased.
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