Source: http://www.patentsencyclopedia.com/app/20090128465
Timestamp: 2017-12-12 18:39:47
Document Index: 191935112

Matched Legal Cases: ['art 220', 'art 220', 'art 220', 'art 220', 'art 201', 'art 201', 'art 220', 'art 220']

Inventors: Naoya Sugimoto (Tokyo, JP) Fusao Ishii (Menlo Park, CA, US) Kazuma Arai (Tokyo, JP) Akira Shirai (Tokyo, JP) Yoshihiro Maeda (Tokyo, JP)
Patent application number: 20090128465
The present invention provides a spatial light modulator, comprising: a plurality of pixel units configured as a two dimensional array extending in a vertical direction and a horizontal direction; a plurality of row lines each comprises a word line and a plate line connected to a plurality of the pixel units along a row in the horizontal direction; a first address decoder for selecting the word line; a second address decoder for selecting the plate line; and a level retention circuit interconnected between the plate line and second address decoder to retain a voltage level of the plate line.
1. A spatial light modulator, comprising:a plurality of pixel units arranged as a pixel array along a vertical and a horizontal directions;a plurality of row lines each comprises a word line and a plate line and each connected to a plurality of the pixel units;a first address decoder connected to said word lines for selecting and activating selected word lines;a second address decoder connected to said plate lines for selecting and activating selected plate lines; anda level retention circuit interconnected between the plate line and the second address decoder to retain the voltage level of the plate line.
2. The spatial light modulator according to claim 1, wherein:said plate lines are divide into a plurality of groups and the second address decoder controls said plate lines in each of said group independently.
3. A spatial light modulator, comprising:a plurality of pixel units arranged as a two-dimensional pixel array extending along a vertical and a horizontal directions;a plurality of row lines each includes a word line and a plate line and each connected to a plurality of the pixel units;a first address decoder connected to the word lines for selecting and activating selected word lines; anda second address decoder and a third address decoder share and select the plate lines.
4. The spatial light modulator according to claim 3, further comprising:level retention circuits interconnected between the plate lines and the second address decoder, and between the plate lines and the third address decoder to retain voltage levels of the plate lines.
5. The spatial light modulator according to claim 3, wherein:each of the row lines is alternately addressed by the second and third address decoders.
6. The spatial light modulator according to claim 3, wherein:the second and third address decoders alternately address different row lines.
7. A spatial light modulator, comprising:a plurality of pixel units configured as a two-dimensional pixel array extended along a vertical direction and a horizontal direction;a plurality of row lines each comprises a word line and a plate line connected to a plurality of the pixel units disposed along a row in said two-dimensional pixel array;a first address decoder connected to the word lines for selecting and activating the selected word line; anda second address decoder connected to said plate lines for selecting and activating the selected plate line.
8. The spatial light modulator according to claim 7, wherein:the second address decoder selects the plate line continuously for at least twice in a display frame period.
9. A mirror array device, comprising:a video image controller for transmitting a digital image data according to a video image signal;a plurality of mirror elements arranged as a pixel array for modulating an illumination light in accordance with the digital image data corresponding to the video image signal;each of the mirror elements further comprises a memory circuit;a bit line for transmitting a first data signal to the memory circuit;a word line for selecting a plurality of memory circuits disposed on a selected row;a plate line for transmitting a second data signal to the memory circuits disposed on a selected row;a first address decoder for selecting the word line in accordance with the digital image data; anda second address decoder for selecting the plate line when a predetermined delay time elapses after the word line is selected.
10. The mirror array device according to claim 9, wherein:the first address decoder selects all of the word lines at least once in one frame period, while the second address decoder selects all of the plate lines at least twice in the one frame period.
11. The mirror array device according to claim 9, wherein:the second address decoder selects and independently controls the plate lines in at least two separate regions, whereinthe plate lines in the at least two separate regions are selected at least once in the one frame period.
12. The mirror array device according to claim 9, wherein:the predetermined delay time is maintained as a constant delay within one frame period.
13. The mirror array device according to claim 9, wherein:the predetermined delay time is determined by a quantity of the illumination light projected from a light source or a quantity of a reflection light from the mirror element.
14. The mirror array device according to claim 9, wherein:each of the mirror elements has an ON state, an OFF state and an oscillation state, whereineach of the plate lines is selected for shifting one of the mirror elements from the ON or OFF state to the oscillation state.
15. The mirror array device according to claim 9, wherein:said pixel array comprises approximately 900 thousand mirror elements or more, whereineach mirror has a mirror surface area ranging between 25 square micrometers and 100 square micrometers.
16. The mirror array device according to claim 9, wherein:the pixel array has at least 720 row lines extending along a horizontal direction.
17. The mirror array device according to claim 9, wherein:the mirror elements are arranged as a two-dimensional array extending along a vertical direction and a horizontal direction wherein:the first data signal from the bit line is transmitted to the memory circuits connected to one line in the horizontal direction at a rate of 23 nanoseconds or less.
18. The mirror array device according to claim 9, wherein:the plate lines have a data transmission speed for transmitting the second data signal to the memory circuit higher than a data transmission speed of the first data signal on the bit lines for writing data to the memory circuits.
19. A spatial light modulator, comprising:a plurality of pixel units arranged as a two-dimensional pixel array extending in a vertical and a horizontal directions;a plurality of row lines, each of row lines comprise a plurality of the pixel units along the horizontal direction wherein said row lines are divided into an upper region and a lower region in the vertical direction;each of the row lines further comprises a word line and plate line;a first address decoder for controlling the word line;a second address decoder for controlling the plate lines of the upper region; anda third address decoder for controlling the plate lines of the lower region.
20. The spatial light modulator according to claim 19, wherein:the second and third address decoders control each of the plate lines in substantially a simultaneously manner.
[0001]This application is a Non-provisional application claiming a Priority date of Nov. 16, 2007 based on a previously filed Provisional Application 61/003,375 and a Non-provisional patent application Ser. No. 11/121,543 filed on May 3, 2005 issued into U.S. Pat. No. 7,268,932. The application Ser. No. 11/121,543 is a Continuation In Part (CIP) Application of three previously filed Applications. These three applications are Ser. No. 10/698,620 filed on Nov. 1, 2003, Ser. No. 10/699,140 filed on Nov. 1, 2003 now issued into U.S. Pat. No. 6,862,127, and Ser. No. 10/699,143 filed on Nov. 1, 2003 now issued into U.S. Pat. No. 6,903,860 by the Applicant of this patent applications. The disclosures made in these patent applications are hereby incorporated by reference in this patent application.
[0018]A first exemplary embodiment of the present invention provides a spatial light modulator, comprising, a plurality of pixel units arranged as a pixel array along a vertical and a horizontal direction, a plurality of row lines each comprises a word line and a plate line and each connected to a plurality of the pixel units, a first address decoder connected to the word lines for selecting and activating selected word lines, a second address decoder connected to said plate lines for selecting and activating selected plate lines, and a level retention circuit interconnected between the plate line and the second address decoder to retain the voltage level of the plate line.
[0019]A second exemplary embodiment of the present invention provides the spatial light modulator according to the first exemplary embodiment, wherein said plate lines are divide into a plurality of groups and the second address decoder controls said plate lines in each of said group independently.
[0020]A third exemplary embodiment of the present invention provides a spatial light modulator, comprising, a plurality of pixel units arranged as a two-dimensional pixel array extending along a vertical and a horizontal directions, a plurality of row lines each includes a word line and a plate line and each connected to a plurality of the pixel units, a first address decoder connected to the word lines for selecting and activating selected word lines, and a second address decoder and a third address decoder share and select the plate lines.
[0021]A fourth exemplary embodiment of the present invention provides the spatial light modulator according to the third exemplary embodiment, further comprising level retention circuits interconnected between the plate lines and the second address decoder, and between the plate lines and the third address decoder to retain voltage levels of the plate lines.
[0022]A fifth exemplary embodiment of the present invention provides the spatial light modulator according to the third exemplary embodiment, wherein each of the row lines is alternately addressed by the second and third address decoders.
[0023]A sixth exemplary embodiment of the present invention provides the spatial light modulator according to the third exemplary embodiment, wherein the second and third address decoders alternately address different row lines.
[0024]A seventh exemplary embodiment of the present invention provides a spatial light modulator, comprising, a plurality of pixel units configured as a two-dimensional pixel array extended along a vertical direction and a horizontal direction, a plurality of row lines each comprises a word line and a plate line connected to a plurality of the pixel units disposed along a row in said two-dimensional pixel array, a first address decoder connected to the word lines for selecting and activating the selected word line, and a second address decoder connected to the plate lines for selecting and activating the selected plate line.
[0025]An eighth exemplary embodiment of the present invention provides the spatial light modulator according to the seventh exemplary embodiment, wherein the second address decoder selects the plate line continuously for at least twice in a display frame period.
[0026]A ninth exemplary embodiment of the present invention provides a mirror array device, comprising a video image controller for transmitting a digital image data according to a video image signal, a plurality of mirror elements arranged as a pixel array for modulating an illumination light in accordance with the digital image data corresponding to the video image signal, each of the mirror elements further comprises a memory circuit, a bit line for transmitting a first data signal to the memory circuit, a word line for selecting a plurality of memory circuits disposed on a selected row, a plate line for transmitting a second data signal to the memory circuits disposed on a selected row, a first address decoder for selecting the word line in accordance with the digital image data, and a second address decoder for selecting the plate line when a predetermined delay time elapses after the word line is selected.
[0027]A tenth exemplary embodiment of the present invention provides the mirror array device according to the ninth exemplary embodiment, wherein the first address decoder selects all of the word lines at least once in one frame period, while the second address decoder selects all of the plate lines at least twice in the one frame period.
[0028]An eleventh exemplary embodiment of the present invention provides the mirror array device according to the ninth exemplary embodiment, wherein the second address decoder selects and independently controls the plate lines in at least two separate regions, wherein the plate lines in the at least two separate regions are selected at least once in the one frame period.
[0029]A twelfth exemplary embodiment of the present invention provides the mirror array device according to the ninth exemplary embodiment, wherein the predetermined delay time is maintained as a constant delay within one frame period.
[0030]A thirteenth exemplary embodiment of the present invention provides the mirror array device according to the ninth exemplary embodiment, wherein the predetermined delay time is determined by a quantity of the illumination light projected from a light source or a quantity of a reflection light from the mirror element.
[0031]A fourteenth exemplary embodiment of the present invention provides the mirror array device according to the ninth exemplary embodiment, wherein each of the mirror elements has an ON state, an OFF state and an oscillation state, wherein each of the plate lines is selected for shifting one of the mirror elements from the ON or OFF state to the oscillation state.
[0032]A fifteenth exemplary embodiment of the present invention provides the mirror array device according to the ninth exemplary embodiment, comprising said pixel array comprises approximately 900 thousand mirror elements or more, wherein each mirror has a mirror surface area ranging between 25 square micrometers and 100 square micrometers.
[0033]A sixteenth exemplary embodiment of the present invention provides the mirror array device according to the ninth exemplary embodiment, wherein the pixel array has at least 720 row lines extending along a horizontal direction.
[0034]A seventeenth exemplary embodiment of the present invention provides the mirror array device according to the ninth exemplary embodiment, wherein the mirror elements are arrayed vertically and horizontally in the pixel array, wherein the mirror elements are arranged as a two-dimensional array extending along a vertical direction and a horizontal direction wherein, the first data signal from the bit line is transmitted to the memory circuits connected to one line in the horizontal direction at a rate of 23 nanoseconds or less.
[0035]An eighteenth exemplary embodiment of the present invention provides the mirror array device according to the ninth exemplary embodiment, wherein the plate lines have a data transmission speed for transmitting the second data signal to the memory circuit higher than a data transmission speed of the first data signal on the bit lines for writing data to the memory circuits.
[0036]A nineteenth exemplary embodiment of the present invention provides a spatial light modulator, comprising a plurality of pixel units arranged as a two-dimensional pixel array extending in a vertical and a horizontal directions, a plurality of row lines connected to a plurality of the pixel units along the horizontal direction wherein said row lines are divided into an upper region and a lower region in the vertical direction, each of the row lines further comprises a word line and plate line, a first address decoder for controlling the word line, a second address decoder for controlling the plate lines of the upper region, and a third address decoder for controlling the plate lines of the lower region.
[0037]A twentieth exemplary embodiment of the present invention provides the spatial light modulator according to the nineteenth exemplary embodiment, wherein the second and third address decoders control each of the plate lines in substantially a simultaneously manner.
[0171]First Vias 907a, 907b, 907c, 907d, 907d, and 907e and second Vias 915a, 915b, and 915c are preferably made of a metallic material containing tungsten and/or cupper.
[0231]In contrast, in of FIG. 9D, the distance d1' of the edge of electrode B from elastic hinge 911 is set at a value smaller than the above described distance d1, and the distance d2' of the edge of electrode B' from elastic hinge 911 is set at a value larger than the above described distance d2 so that the edge of electrode B' functions as a stopper for mirror 913.
[0259]Furthermore, in each of the multiple pixel units 211 belonging to the same ROW line (ROW-n), the second ON capacitor 233 is connected to plate line 232 or second plate line 232-2, respectively. For example, in pixel unit 1-1, the second ON capacitor 233 is connected to plate line 232, while in next pixel unit 1-2, the second ON capacitor 233 is connected to second plate line 232-2.
[0261]Referring to FIG. 11A, plate line 232 (PL-1) is at L level (0 volts), and "0" volts of bit line 221-2 (Bitline) is applied to ON electrode 216 by means of the H level (5 volts) of word line 231 (WL-1).
[0266]The above description has illustrated one case of Cap 2=15 femto farad (fF) and Cap 3=ff; if Cap 2 is only the floating capacitance Cf of gate transistor 216c, a voltage close to the potential of plate line 232 (PL-1) will be applied to ON electrode 216.
1/60 [sec]/4[divisions]/256 [bit gray scale]/720 [lines]=22.6 nsec.
[0301]Second stage: 640 latches (at the second stage latch 220b)
[0303]Voltage conversion (level shift) (at the level shift circuit 220c)
[0307]In this case, the respective display states of the two pixel units 211 arena gray display for the <pixel 1-1> and a black display for the <pixel 1-2>.
[0313]Until control time t1, the mirror 212 of the <pixel 1-1> is stationary deflected to the side of ON electrode 216 if the Latch OUT (i.e., the output of the third stage latch 220d) is "1" and to the side of OFF electrode 215 if the Latch OUT is "0". That is, until control time t1, the operation of mirror 212 is controlled by means of a pulse width modulation (PWM) in accordance with a PWM control profile 451.
[0314]Immediately prior to control time t1, mirror 212 is stationary deflected to the side of ON electrode 216; then, at control time t1, the mode changeover signal 221-3 (Intermediate) is turned to be "H", and (although the latch OUT is "1") OFF electrode 215 and ON electrode 216 are turned to be "0" volts, prompting mirror 212 to start a free oscillation.
[0326]On ROW 1, at control time t1, word line 231 (WL-1) carries out data loading and then first address decoder 230a (WL_ADDR1) selects ROW 2, 3, 4 through 1080 sequentially to carry out data loading.
[0383]The configuration illustrated in FIG. 22A divides multiple ROW lines (ROW-1 through ROW-1080) into upper and lower groups (i.e., an upper row line area 210a and a lower row line area 210b, each comprising an upper bit line driver part 220-1 and a lower bit line driver part 220-2 (bit line Driver), a first address decoder 230a, a word line driver 230b (WL Address Decoder_up and WL Driver_up, WL Driver_down and WL Driver_down), a plate line driver 251-1, a plate line address decoder 252-1, and a plate line address decoder 252-2 (PL Address Decoder-a up and PL Driver_up, PL Address Decoder-a_down, b_down and PL Driver_up, down)).
[0386]FIG. 22B shows an example configuration in which plate line driver 251-1 (PL Driver_up) and plate line driver 251-2 (PL Driver_down) that are equipped for the upper and lower ROW line groups, each equipped with one plate line address decoder 252 (PL Address Decoder_up) and one plate line address decoder 252 (PL Address Decoder_down) in the comprisal of pixel array 210 as shown in the above described FIG. 22A.
[0393]FIG. 23A is a cross-sectional diagram showing an example modification of the configuration of a pixel unit 211 (i.e., a mirror element 4011) according to the present embodiment.
[0394]FIG. 23B is a conceptual diagram showing an example configuration of the drive circuit for the pixel unit.
[0395]Mirror element 4011 (i.e., pixel unit 211) according to the present embodiment comprises a hinge electrode 4009 and an address electrode 4013, both of which are placed on a device substrate 4004 and covered with an insulation layer 4006.
[0396]A mirror 4003 is supported on insulation layer 4006 of hinge electrode 4009 by way of an elastic hinge 4007. In this case, mirror 4003 is supported as a cantilever against elastic hinge 4007, with the entirety of the mirror 4003 protruding over an address electrode 4013.
[0397]Furthermore, a stopper 4002 is placed on the other side of the address electrode 4013 across from the elastic hinge 4007, with the lower edge of the stopper 4002 fixed onto the device substrate 4004.
[0398]Furthermore, mirror 4003 is tilted to close to address electrode 4013 by a Coulomb force resulting from an application of a voltage V1 to address electrode 4013. Mirror 4003 is stopped at a position abutting on insulation layer 4006 covering address electrode 4013 (which is called an ON state).
[0399]Furthermore, when the application of voltage V1 to address electrode 4013 is cut off, mirror 4003 is restored by the elasticity of elastic hinge 4007 to its horizontal position, abutted by the stopper 4002 so that it does not move beyond this state (which is called an OFF state).
[0400]The following is a description of a control circuit for mirror element 4011, as illustrated in FIG. 23B. In this case, mirror element 4011 is supported by elastic hinge 4007 in a cantilever and therefore is a configuration equipped with bit line 221-2, gate transistor 216c, ON capacitor 216b, and word line 231, which are the circuit elements of memory cell M2 on the ON side, included in the circuit configuration shown in the above described FIG. 10A.
[0401]Furthermore, as shown in FIG. 10A, the present embodiment is equipped with plate line 232, in addition to word line 231, and connects plate line 232 to address electrode 4013 by way of the second ON capacitor 233.
[0402]Further, with the control using word line 231, plate line 232 and bit line 221-2, the OFF state, ON state, and the intermediate oscillation state that is between the ON state and OFF state, are achieved as described below.
[0403]The following is a description of an example method for controlling pixel array 210 comprising the cantilever-structured mirror 4003 as shown in the above described FIGS. 23A and 23B.
[0404]Note that the control system can use the configuration, as is, as shown in FIG. 12A.
[0405]FIG. 24 is a circuit diagram illustrating in detail a part of the layout of pixel array 210 comprising a mirror 4003 (shown in the above described FIG. 23B) that is structured as a cantilever.
[0406]FIG. 25 is a timing chart depicting the operation of the mirror and the operation timings of the <pixel 1-1> and <pixel 1-2> belonging to the same ROW line as that of FIG. 24.
[0407]The example shown in FIGS. 24 and 25 presupposes that the <pixel 1-1> displays gray, while the <pixel 1-2> displays black.
[0408]In this case, since the <pixel 1-1> and <pixel 1-2> belong to the same ROW line, the mode changeover signal 221-3 (Intermediate), word line 231 (WL-1), and plate line 232 (PL-1) are common signals to the two of them.
[0409]Until control time t1, mirror 4003 of the <pixel 1-1> is in PWM operation and a voltage V1 in accordance with bit line 221 (bitline) is applied to the electrode.
[0410]Specifically, if the voltage at bit line 221 (bitline) is at the H level, mirror 4003 is drawn to address electrode 4013 so as to abut onto insulation layer 4006 of address electrode 4013 and is stationary. This is an ON state.
[0411]If the potential at bit line 221 (bitline) is L level, mirror 4003 separates from address electrode 4013, abuts on stopper 4002 and stops thereat. This is an OFF state.
[0412]Just prior to control time t1, mirror 4003 is stationary in the ON state, that is, abutting on address electrode 4013. At control time t1, address electrode 4013 is changed by bit line 221 (bitline) to be "0" volts (i.e., discharged), and mirror 4003 starts to separate from address electrode 4013 by means of the elasticity of elastic hinge 4007.
[0413]At control time t2, that is, before mirror 4003 is far from address electrode 4013, plate line address decoder 252-1 (PL Address Decoder-a) selects plate line 232 (PL-1), and plate line 232 (PL-1) is changed to H level (i.e., a potential 232b, which is lower than the H level of bit line 221). A voltage is generated at the electrode by the potential 232b so that mirror 4003 is attracted by address electrode 4013 and is stationary thereat.
[0414]At control time t3, the plate line address decoder 252-2 (PL Address Decoder-b) selects plate line 232 (PL-1) and, if it is L level, mirror 4003 starts to separate from address electrode 4013 again.
[0415]At control time t4, that is before mirror 4003 is far from address electrode 4013, as at t2, the plate line address decoder 252-2 (PL Address Decoder-a) selects plate line 232 (PL-1) and is changed to H level (i.e., the potential 232b) and mirror 4003 is re-attracted to address electrode 4013 and is stationary thereat.
[0416]At control time t5, the plate line address decoder 252-2 (PL Address Decoder-b) selects plate line 232 (PL-1), and the PL-1 is changed to L level so that mirror 4003 is re-attracted by address electrode 4013 to be stationary thereat. Simultaneously, or a little thereafter, a memory cell is selected by word line 231, and "0" volts is set by bit line 221.
[0417]With this series of operation, mirror 4003 able 1) to generate a smaller quantity of light than the quantity during the minimum data-loading period in accordance with a PWM control with word line 231 (WL) and 2) to express an intermediate gray scale.
[0418]In this case, the mirror of the <pixel 1-2> adjacent to the <pixel 1-1> displays black and therefore the mirror needs to be continuously stationary on the side of stopper 4002 (i.e., the OFF side).
[0419]Plate line 232 (PL-1) is common to the <pixel 1-1> and <pixel 1-2> and therefore, between control times t2 and t5, a voltage is generated at address electrode 4013. However, mirror 4003 is stationary on the OFF side and the distance between address electrode 4013 and mirror 4003 is far, and, therefore, a Coulomb force applied to mirror 4003 is small, causing no change to the position of mirror 4003.
[0420]That is, the control is such as to maintain the following relationship in order not to change the position of mirror 4003:
[0421]As such, spatial light modulator 200 comprising mirror element 4011, configured as shown in FIGS. 23A and 23B, is configured to control mirror element 4011 with one memory cell M2, thereby making it possible to make the size of the mirror element 4011 more compact and express various gray scale by means of the intermediate oscillation of mirror 4003, in addition to the ON and OFF states, using plate line 232.
[0422]In a projection technique using spatial light modulator 200, a reduction in the size of mirror element 4011 makes it possible to obtain both a higher level of definition of the projection image by arraying a larger number of mirror elements 4011 and a higher grade of gray scale with the intermediate oscillation of mirror 4003 using plate line 232.
[0423]FIG. 26A is a plain view diagram illustrating the packaging structure of a package accommodating the spatial light modulator shown in the above described FIGS. 22A through 22D, et cetera. FIG. 26B is its cross-sectional diagram.
[0424]The spatial light modulator 200 according to the present embodiment places the upper bit line driver part 220-1 and lower bit line driver part 220-2 along the upper and lower sides, respectively, which are parallel to the ROW line in the surrounding area of pixel array 210, and places word line driver unit 230 and plate line driver unit 250 along the left and right sides, respectively, which cross the aforementioned upper and lower sides.
[0425]The spatial light modulator 200 is accommodated in the concave part 201a of package 201.
[0426]Multiple bonding pads 202 are placed in the surrounding area of the concave part 201a of package 201.
[0427]Bit lines and address lines placed in the upper bit line driver part 220-1, lower bit line driver part 220-2, word line driver unit 230, and plate line driver unit 250 are connected, by way of bonding wires, to bonding pads 202 provided in the surrounding area, and are further connected electrically, by way of external connection electrodes (which are not shown in a drawing here) that are placed on the bottom part of the package 201, to the wiring board or the like of a projection apparatus (which is described below) incorporating package 201.
[0428]The following is a description of an example configuration of a projection apparatus comprising spatial light modulator 200 equipped with the above described plate line 232. Note that the constituent component corresponding to the previously described constituent component is noted in the drawing with a corresponding sign in parenthesis as appropriate.
[0429]FIG. 27 is a conceptual diagram showing the configuration of a projection apparatus according to a preferred embodiment of the present invention.
[0430]As shown in FIG. 27, a projection apparatus 5010 according to the present embodiment comprises a single spatial light modulator (SLM) 5100 (i.e., the spatial light modulator 200), a control unit 5500 (i.e., the control apparatus 300), a Total Internal Reflection (TIR) prism 5300, a projection optical system 5400, and a light source optical system 5200.
[0431]The spatial light modulator 5100 is implemented according to the above-described spatial light modulator 200 comprising plate line 232.
[0432]The projection apparatus 5010 is generally referred to as a single-panel projection apparatus 5010 implemented with a single spatial light modulator 5100.
[0433]The projection optical system 5400 is equipped with spatial light modulator 5100 and TIR prism 5300 in the optical axis of projection optical system 5400, and the light source optical system 5200 is equipped in such a manner that the optical axis thereof matches that of projection optical system 5400.
[0434]The TIR prism 5300 causes 1) an illumination light 5600 from light source optical system 5200, which is placed onto the side, to enter spatial light modulator 5100 at a prescribed inclination angle relative thereto as incident light 5601 and 2) a reflection light 5602 reflected by spatial light modulator 5100 so as to reach projection optical system 5400.
[0435]The projection optical system 5400 projects reflection light 5602, as projection light 5603, by way of spatial light modulator 5100 and TIR prism 5300 to a screen 5900 or the like.
[0436]The light source optical system 5200 comprises an adjustable light source 5210 for generating illumination light 5600, a condenser lens 5220 for focusing illumination light 5600, a rod type condenser body 5230, and a condenser lens 5240.
[0437]The adjustable light source 5210, condenser lens 5220, rod type condenser body 5230, and condenser lens 5240 are sequentially placed in the aforementioned order on the optical axis of illumination light 5600 emitted from adjustable light source 5210 and incident to the side face of TIR prism 5300.
[0438]The projection apparatus 5010 employs a single spatial light modulator 5100 for implementing a color display on the screen 5900 by means of a sequential color display method.
[0439]That is, adjustable light source 5210, comprising a red laser light source 5211, a green laser light source 5212, and a blue laser light source 5213 (which are not shown in a drawing here), which allows independent controls for the light emission states, performs the operation of dividing one frame of display data into multiple sub-fields (i.e., three sub-fields, that is, red (R), green (G) and blue (B) in the present case) and causes the red laser light source 5211, green laser light source 5212, and blue laser light source 5213 to emit each respective light in at the time frame corresponding to the sub-field of each color as described below.
[0440]FIG. 28 is a block diagram showing an example configuration of control unit 5500 comprised in the above described single-panel projection apparatus 5010. Control unit 5500 comprises a frame memory 5520, an SLM controller 5530, a sequencer 5540, a video image analysis unit 5550, a light source control unit 5560, and a light source drive circuit 5570.
[0441]The sequencer 5540 implements a microprocessor and the like, controls the operation timing and the like of the entirety of control unit 5500 and spatial light modulator 5100.
[0442]The frame memory 5520 retains, for example, the equivalent to one frame, input digital video data 5700 (i.e., a binary video image signal 400) from an external device (not shown in a drawing herein) that is connected to a video signal input unit 5510. The input digital video data 5700 is updated, moment-by-moment, every time the display of one frame is completed.
[0443]The SLM controller 5530 processes the input digital video data 5700 read from the frame memory 5520 as described below, separating the read data into multiple sub-fields, and outputs them to the spatial light modulators 5100 as control data used for implementing the ON/OFF control and oscillation control (which are described below) of a mirror 5112 of spatial light modulator 5100.
[0444]The sequencer 5540 outputs a timing signal to the spatial light modulators 5100 synchronously with the generation of data at the SLM controller 5530.
[0445]The video image analysis unit 5550 outputs a video image analysis signal 6800 used for generating various light source pulse patterns on the basis of the input digital video data 5700 inputted from the video signal input unit 5510.
[0446]The light source control unit 5560 controls, by way of the light source drive circuit 5570, the operation of adjustable light source 5210 emitting illumination light 5600 on the basis of the video image analysis signal 6800 obtained from the video image analysis unit 5550 by way of the sequencer 5540.
[0447]The light source drive circuit 5570 drives the red laser light source 5211, green laser light source 5212, and blue laser light source 5213 of adjustable light source 5210 to emit light on the basis of an instruction from the light source control unit 5560.
[0448]FIG. 29 is a conceptual diagram showing another exemplary modification of a multi-panel projection apparatus according to the present embodiment.
[0449]The projection apparatus 5040 is configured so that multiple to place spatial light modulators 5100 (i.e., the spatial light modulator 200) corresponding to the three respective colors R, G and B, so as to be adjacent to one another in the same plane on one side of a light separation/synthesis optical system 5330.
[0450]This configuration makes it possible consolidate spatial light modulators 5100 into the same packaging unit, for example, a package 201 or the like, and thereby save space.
[0451]The light separation/synthesis optical system 5330 comprises a TIR prism 5331, a TIR prism 5332, and a TIR prism 5333.
[0452]TIR prism 5331 has guides to spatial light modulators 5100 illumination light 5600, incident in the lateral direction of the optical axis of projection optical system 5400, as incident light 5601.
[0453]TIR prism 5332 separates a red color light from the incident light 5601 and guides it to the red color-use spatial light modulator 5100, and also captures reflection light 5602 of the separated incident light and guides it to projection optical system 5400.
[0454]Likewise, TIR prism 5333 separates the incident lights of green and blue colors from incident light 5601, makes them incident to the individual spatial light modulators 5100, equipped correspondently to their respective colors, and captures reflection lights 5602 of the respective colors and guides them to projection optical system 5400.
[0455]FIG. 30 is a block diagram showing an example configuration of the control unit of a multi-panel projection apparatus according to the present embodiment.
[0456]Control unit 5502 comprises SLM controllers 5531, 5532, and 5533, which are used for controlling each of the spatial light modulators 5100 equipped for the colors R, G and B. The comprisal of the controllers is different from the above described control unit 5500, which is otherwise similar.
[0457]That is, SLM controller 5531, SLM controller 5532, and SLM controller 5533 correspond to their respective color-use spatial light modulators 5100, which are formed on the same substrates as those of their respective spatial light modulators 5100 (i.e., the spatial light modulators 200). This configuration makes it possible to place the individual spatial light modulators 5100 and the respectively corresponding SLM controller 5531, SLM controller 5532, and SLM controller 5533 close to each other, thereby enabling a high speed data transfer rate.
[0458]Furthermore, a system bus 5580 is formed to connect to the frame memory 5520, light source control unit 5560, sequencer 5540, and SLM controllers 5531 through 5533, in order to speed up and simplify the connection path of each connecting element.
[0459]FIG. 31 is a functional block diagram for showing an exemplary modification of a multi-panel projection apparatus according to another preferred embodiment of the present invention.
[0460]The projection apparatus 5020 shown in FIG. 31 is implemented with two spatial light modulators 5100 (i.e., the spatial light modulators 200), each of which comprises the above described plate line 232, wherein one spatial light modulator 200 modulates the green light while the other spatial light modulator 200 modulates the red and blue lights.
[0461]Specifically, projection apparatus 5020 comprises a dichroic mirror 5320 as a light separation/synthesis optical system.
[0462]Dichroic mirror 5320 separates the wavelength component of a green light and the wavelength components of red and blue lights from incidence light 5601, which is incident from light source optical system 5200, causing them to branch into two spatial light modulators 200, respectively, synthesizing reflection light 5602 of the green light reflected (i.e., modulated) by the corresponding spatial light modulator 200 with the reflection light of the red and blue light reflected (i.e., modulated) by the corresponding spatial light modulator 200 to guide the synthesized light to the optical axis of projection optical system 5400, and projecting the synthesized light onto a screen 5900 as projection light 5603.
[0463]FIG. 32 is a block diagram for showing an example configuration of a control unit 5506 provided in projection apparatus 5020 comprising the above-described two spatial light modulators 200. In this case, SLM controller 5530 controls two spatial light modulators 5100 (i.e., the spatial light modulators 200), which is the only difference from the configuration shown in FIG. 28.
[0464]FIG. 33 is a timing diagram for showing the waveform of a control signal of the projection apparatus according to the present embodiment.
[0465]A drive signal (i.e., a mirror control profile 450 shown in FIG. 33) generated by SLM controller 5530 drives multiple spatial light modulators 5100.
[0466]The light source control unit 5560 generates a light source profile control signal 5800 corresponding to mirror control profile 450, which is a signal for driving individual spatial light modulators 5100 for inputting the signal generated to light source drive circuit 5570, which then adjusts the intensity of the laser light (i.e., the illumination light 5600) emitted from the red laser light source 5211, the green laser light source 5212, and the blue laser light source 5213.
[0467]The control unit 5506 comprised in the projection apparatus 5020 is configured such that a single SLM controller 5530 drives the spatial light modulators 5100, thereby enabling the irradiation of illumination light 5600 on the respective spatial light modulators 5100 with the optimal quantity of light, without a requirement to configure the light source control unit 5560 or light source drive circuit 5570 for each spatial light modulator 5100. This configuration simplifies the circuit configuration of the control unit 5506.
[0468]As shown in FIG. 33, the light source control unit 5560 and light source drive circuit 5570 drives the red laser light source 5211, green laser light source 5212, and blue laser light source 5213 so as to adjust the intensities of individual lasers (i.e., illumination light 5600) of the colors R, Q and B synchronously with the irrespective SLM drive signals (i.e., the mirror control profile 450) generated by the SLM controller 5530.
[0469]In this case, two colors, R and B, share one spatial light modulator 5100, and therefore the control is a color sequential method.
[0470]That is, one frame includes multiple subfields, that include subfields 6701, 6702, and 6703, and the same light source pulse pattern 6815 is repeated in each subfield in one spatial light modulator 5100 corresponding to green (G).
[0471]Meanwhile, the pulse emission of the red laser light source 5211 and blue laser light source 5213 for the red (R) and blue (B) lights that share one spatial light modulator 5100 are separately controlled. Therefore, the subfields that include subfields 6701 through 6703 are alternately applied in a time series as the light source pulse pattern 6816 and light source pulse pattern 6817.
[0472]Furthermore, with the light source as described, the emission pulse intervals t1 and emission pulse widths tp can be changed in the light source pulse pattern 6815 of the green laser, the light source pulse pattern 6816 of the red laser, and the light source pulse pattern 6817 of the blue laser.
[0473]Therefore, the present embodiment can improve the levels of the gray scale for each of the R, G, and B colors.
[0474]According to above descriptions, the present invention discloses a system configuration and method for increasing the definition of the projection image while improving the levels of the gray scale for an image projection system implemented with a spatial light modulator.
[0475]Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.
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