Source: https://patents.google.com/patent/US9106399B2/en
Timestamp: 2018-08-19 18:35:56
Document Index: 15805506

Matched Legal Cases: ['§371', 'Application No. 60', 'art.\n1', 'Application No. 07853389', 'Application No. 07853389', 'Application No. 07853389']

US9106399B2 - Phase control block for managing multiple clock domains in systems with frequency offsets - Google Patents
US9106399B2
US9106399B2 US14321723 US201414321723A US9106399B2 US 9106399 B2 US9106399 B2 US 9106399B2 US 14321723 US14321723 US 14321723 US 201414321723 A US201414321723 A US 201414321723A US 9106399 B2 US9106399 B2 US 9106399B2
US14321723
US20150030113A1 (en )
This application is a continuation of U.S. application Ser. No. 13/710,404, filed Dec. 10, 2012, which is a continuation of U.S. patent application Ser. No. 12/225,999, filed Jan. 12, 2009, now U.S. Pat. No. 8,331,512, which is a United States National stage application filed under 35 U.S.C. §371 of PCT Patent Application Ser. No. PCT/US2007/008493, filed Apr. 4, 2007, which claimed the benefit of the filing date of U.S. Provisional Patent Application No. 60/789,406 filed Apr. 4, 2006, all of which are incorporated herein by reference in their entireties.
The phase adjustment signal is supplied to three accumulating registers 80, 85, and 90 (“Phase ACC Edge,” “Phase ACC DFE,” and “Phase ACC TX”). Each register maintains a phase shift value and increments or decrements the phase shift value in response to the phase adjustment signal.
One register (“Phase ACC Edge”) is connected directly to a control input 92 of an edge clock phase shifter 95 (“Interpolator Edge”) which in this embodiment is a phase interpolator. Other types of phase shifters may be used in place of each interpolator referred to herein as, for example, adjustable delay lines or combinations of delay lines and phase interpolators. The edge clock phase shifter is arranged to receive a clock signal 100 referred to herein as the “Receiver clock signal.” The Receiver clock signal may be generated by a phase locked loop (not shown) or other conventional circuit and in many embodiments will be multiple clock signals of the same frequency but equally spaced within a period of the Receiver clock signal. The edge clock phase shifter shifts the phase of the Receiver clock signal by an amount directly related to the output of Phase ACC Edge. The phase-shifted replica of the Receiver clock signal constitutes the edge clock signal. The edge clock signal is applied to the clock input of a latch or other sampling device 105 (“Edge Sampler”). This sampling device receives a digital signal 110 (“equalized signal”), captures successive samples of the digital signal at times set by the edge clock signal and compares these samples to a threshold to convert each sample to “edge samples” 115, which are in the form of a digital “1” or “0.” These “edge samples” are supplied to a deserializer and phase detector 120.
An adaptive clock phase shifter 160 (“Interpolator Adapt”) is connected to an adder 165 which receives the phase shift value from the same register (“Phase ACC Edge”) and also receives a selectively variable adaptive clock offset value 170 (“A_os”). The adaptive clock phase shifter provides another replica (“adaptive clock”) 22 of the Receiver clock, phase shifted by an amount directly related to the sum of the phase shift value stored in register Phase ACC Edge and A_os, to a further sampler 175 which also samples the equalized signal. The selectively variable offset between the adaptive clock and the data and edge clocks allows control of the adaptive sampler to take samples at any desired point on the digital signal waveform. This capability can be used to measure the size of the data eye of the digital signal while the system continues to collect the data using the data clock and edge clock as discussed above. Furthermore, the values provided by the adaptive sampler are provided to a circuit 180 (“adaptation”) which may also receive the values from the data sampler. The “adaptation” block can use these sampler outputs to optimize the equalizers “DFE” to obtain a better BER performance through the link. That the process of adapting an equalizer requires these samples is obvious to those skilled in the art.
1. A circuit for receiving a digital signal comprising:
at least three samplers for sampling the digital signal, each sampler having a clock input, wherein the samplers include an edge sampler and a data sampler and an adaptive sampler;
edge clock circuitry to generate an edge clock signal, coupled to the edge sampler to sample the digital signal in accordance with the edge clock signal;
data clock circuitry to generate a data clock signal, coupled to the data sampler to sample the digital signal in accordance with the data clock signal; and
adaptive clock circuitry to generate an adaptive clock signal, coupled to the adaptive sampler to sample the digital signal in accordance with the adaptive clock signal, and to phase shift the adaptive clock signal so as to sample the digital signal at selected phases in a data eye of the digital signal.
a decision feedback equalizer to generate a compensation signal;
adaptation circuitry to receive a signal generated by the adaptive sampler, generate an adaptation output and provide the adaptation output to the decision feedback equalizer; and
circuitry to combine the compensation signal and the digital signal to generate a compensated digital signal.
a phase accumulator that generates an output;
DFE clock circuitry to generate a phase shifted clock signal, comprising a first replica of a receiver clock signal, phase shifted by an amount controlled by the output generated by the phase accumulator; and
a decision feedback equalizer (DFE) to generate a compensation signal, the DFE having timing controlled by the phase shifted clock.
4. The circuit of claim 3, further comprising a phase detector configured to receive a plurality of signals, including the data signal, received from a source external to the circuit, and a sampled data signal from the data sampler or edge sampler, and further configured to generate a phase error signal corresponding to a phase relationship between the plurality of signals received by the phase detector;
wherein the phase accumulator is configured to accumulate a phase error in accordance with the phase error signal generated by the phase detector.
5. The circuit of claim 3, wherein the DFE clock circuitry is configured to generate the phase shifted clock signal by phase shifting the receiver clock signal by an amount corresponding to a sum of a selectively variable offset and the output generated by the phase accumulator.
6. The circuit of claim 3, further comprising phase adjusting circuitry to adjust a phase offset between the edge clock signal and data clock signal.
7. The circuit of claim 6, wherein the phase adjusting circuitry to adjust the phase offset between the edge clock signal and data clock signal includes circuitry for combining a data clock offset value with an accumulated phase adjustment signal to generate a control value.
8. The circuit of claim 7, wherein the data clock circuitry includes circuitry to generate the data clock signal as a second replica of the receiver clock signal, phase shifted by an amount controlled by the control value.
9. A method of receiving a digital signal, comprising:
sampling the digital signal with three samplers, each sampler having a clock input, wherein the samplers include an edge sampler and a data sampler and an adaptive sampler; and
generating an edge clock signal, coupled to the edge sampler to sample the digital signal in accordance with the edge clock signal;
generating a data clock signal, coupled to the data sampler to sample the digital signal in accordance with the data clock signal; and
generating an adaptive clock signal, coupled to the adaptive sampler to sample the digital signal in accordance with the adaptive clock signal, and phase shifting the adaptive clock signal so as to sample the digital signal at selected phases in a data eye of the digital signal.
10. The method of claim 9, wherein phase shifting the adaptive clock signal includes phase shifting the adaptive clock signal so as to sample the digital signal at phases selected in accordance with a selectively variable offset so as to measure the data eye of the digital signal.
generating an adaptation output in accordance with an output generated by the adaptive sampler,
providing the adaptation output to a decision feedback equalizer;
generating a compensation signal using the decision feedback equalizer; and
combining the compensation signal and the digital signal to generate a compensated digital signal.
generating a phase accumulation value;
generating a phase shifted clock signal, comprising a first replica of a receiver clock signal, phase shifted by an amount controlled by the phase accumulation value; and
generating a compensation signal with a decision feedback equalizer (DFE), the DFE having timing controlled by the phase shifted clock.
13. A circuit for receiving a digital signal comprising:
edge clock means for generating an edge clock signal, coupled to the edge sampler to sample the digital signal in accordance with the edge clock signal;
data clock means for generating a data clock signal, coupled to the data sampler to sample the digital signal in accordance with the data clock signal; and
adaptive clock means for generating an adaptive clock signal, coupled to the adaptive sampler to sample the digital signal in accordance with the adaptive clock signal, and for phase shifting the adaptive clock signal so as to sample the digital signal at phases between phases of the edge clock signal and data clock signal so as to measure a data eye of the digital signal.
adaptation means for receiving a signal generated by the adaptive sampler, generating an adaptation output and providing the adaptation output to the decision feedback equalizer; and
means for combining the compensation signal and the digital signal to generate a compensated digital signal.
DFE clock means for generating a phase shifted clock signal, comprising a first replica of a receiver clock signal, phase shifted by an amount controlled by the output generated by the phase accumulator; and
16. The circuit of claim 15, further comprising a phase detector configured to receive a plurality of signals, including the data signal, received from a source external to the circuit, and a sampled data signal from the data sampler or edge sampler, and further configured to generate a phase error signal corresponding to a phase relationship between the plurality of signals received by the phase detector;
17. The circuit of claim 15, wherein the DFE clock means is configured to generate the phase shifted clock signal by phase shifting the receiver clock signal by an amount corresponding to a sum of a selectively variable offset and the output generated by the phase accumulator.
18. The circuit of claim 15, further comprising means for adjusting a phase offset between the edge clock signal and data clock signal.
19. The circuit of claim 18, wherein the means for adjusting the phase offset between the edge clock signal and data clock signal includes means for combining a data clock offset value with an accumulated phase adjustment signal to generate a control value.
20. The circuit of claim 19, wherein the data clock means includes means for generating the data clock signal as a second replica of the receiver clock signal, phase shifted by an amount controlled by the control value.
US14321723 2006-04-04 2014-07-01 Phase control block for managing multiple clock domains in systems with frequency offsets Active US9106399B2 (en)
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