Source: http://www.google.com/patents/US7629256?dq=6076065
Timestamp: 2017-03-26 22:26:40
Document Index: 406014917

Matched Legal Cases: ['arts 541', 'art 541', 'art 542', 'arts 541', 'art 541', 'arts 541', 'arts 541', 'art 541', 'arts 541', 'arts 541', 'Application No. 05011705']

Patent US7629256 - In situ silicon and titanium nitride deposition - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method of processing semiconductor wafers is provided, comprising loading a batch of semiconductor wafers into a processing chamber; depositing titanium nitride (TiN) onto the wafers in the processing chamber; and depositing silicon onto the wafers in the processing chamber, without removing the wafers...http://www.google.com/patents/US7629256?utm_source=gb-gplus-sharePatent US7629256 - In situ silicon and titanium nitride depositionAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7629256 B2Publication typeGrantApplication numberUS 11/748,364Publication dateDec 8, 2009Filing dateMay 14, 2007Priority dateMay 14, 2007Fee statusPaidAlso published asUS20080286981Publication number11748364, 748364, US 7629256 B2, US 7629256B2, US-B2-7629256, US7629256 B2, US7629256B2InventorsAlbert HasperOriginal AssigneeAsm International N.V.Export CitationBiBTeX, EndNote, RefManPatent Citations (101), Non-Patent Citations (12), Referenced by (7), Classifications (9), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetIn situ silicon and titanium nitride deposition
US 7629256 B2Abstract
A method of processing semiconductor wafers is provided, comprising loading a batch of semiconductor wafers into a processing chamber; depositing titanium nitride (TiN) onto the wafers in the processing chamber; and depositing silicon onto the wafers in the processing chamber, without removing the wafers from the processing chamber between said depositing steps. In preferred embodiments, the TiN and silicon depositing steps are both conducted at temperatures within about 400-550° C., and at temperatures within 100° C. of one another.
1. A method of processing semiconductor wafers, comprising:
loading a batch of semiconductor wafers into a processing chamber;
depositing titanium nitride (TiN) onto the wafers in the processing chamber; and
depositing silicon onto the wafers in the processing chamber by performing a thermal chemical vapor deposition at a silicon deposition temperature within about 20° C. of a temperature for depositing titanium nitride, without removing the wafers from the processing chamber between said depositing steps, wherein the silicon precursor is trisilane.
2. The method of claim 1, wherein said step of depositing silicon occurs after said step of depositing TiN.
3. The method of claim 1, wherein said step of depositing TiN occurs after said step of depositing silicon.
4. The method of claim 1, wherein the TiN and silicon depositing steps are both conducted at temperatures within about 400-550° C.
5. The method of claim 1, wherein loading the batch of wafers comprises providing an arrangement of generally parallel wafers spaced from one another, and wherein depositing TiN and silicon comprises flowing precursor gases through gas injector tubes each positioned within the processing chamber and oriented substantially perpendicular to the wafers, each injector tube extending along a majority of a length of the arrangement of wafers, each tube having a plurality of gas injector holes along its length.
6. The method of claim 4, wherein the TiN and silicon depositing steps are both conducted at temperatures within about 450-500° C.
7. The method of claim 5, wherein loading the batch of wafers comprises providing an arrangement of generally horizontal wafers spaced vertically from one another, each injector tube being oriented substantially vertically and extending along a majority of a height of the arrangement of wafers.
8. The method of claim 5, wherein depositing TiN comprises:
flowing a plurality of separate pulses of a titanium precursor gas through a first of the injector tubes; and
flowing a plurality of separate pulses of a nitrogen precursor gas through a second of the injector tubes, each of the nitrogen precursor gas pulses occurring temporally between two successive ones of the titanium precursor gas pulses.
9. The method of claim 5, wherein depositing TiN comprises:
flowing a nitrogen precursor gas through a first of the injector tubes; and
while flowing the nitrogen precursor gas, flowing a plurality of separate pulses of a titanium precursor gas through a second of the injector tubes.
10. The method of claim 5, wherein depositing TiN comprises flowing nitrogen and titanium precursor gases in accordance with a cycle comprising the following steps:
flowing a pulse of the nitrogen precursor gas through a first of the injector tubes during a first time interval;
flowing a pulse of the titanium precursor gas through a second of the injector tubes during the first time interval; and
flowing a pulse of the nitrogen precursor gas through the first injector tube during a second time interval after the first time interval, wherein the titanium precursor gas is not delivered to the processing chamber during the second time interval.
11. The method of claim 8, wherein depositing TiN further comprises, during each of a plurality of separate time intervals, one of (1) flowing a purge gas into the processing chamber and (2) evacuating the processing chamber, each said time interval being after a pulse of one of the precursor gases and before an immediately following pulse of the other of the precursor gases.
12. The method of claim 8, wherein depositing TiN further comprises flowing an additional pulse of the nitrogen precursor gas through the second injector tube after a last of the titanium precursor gas pulses, said additional nitrogen precursor gas pulse not being followed by another titanium precursor gas pulse.
13. The method of claim 10, wherein the cycle further includes the following steps:
temporally between the first and second time intervals, one of (1) purging the processing chamber with a purge gas and (2) evacuating the processing chamber; and
temporally after the second time interval, one of (1) purging the processing chamber with the purge gas and (2) evacuating the processing chamber.
14. The method of claim 10, wherein the titanium precursor gas comprises titanium tetrachloride (TiCl4), and the nitrogen precursor gas comprises ammonia (NH3).
The present application relates generally to semiconductor processing, and more particularly to silicon and titanium nitride deposition.
The present application incorporates by reference the full disclosures of the following: U.S. Pat. No. 6,746,240; U.S. Pat. No. 6,962,859; U.S. Patent Application Publication No. 2003/0111013 A1; U.S. Patent Application Publication No. 2004/0250853 A1; U.S. Patent Application Publication No. 2005/0118837 A1; U.S. Patent Application Publication No. 2006/0060137 A1; U.S. Patent Application Publication No. 2006/0088985 A1; and Sze, VLSI TECHNOLOGY, pp. 240-41 (1988).
High-temperature ovens, called reactors, are used to create structures of very fine dimensions, such as integrated circuits on semiconductor substrates. One or more substrates, such as silicon wafers, are placed on a substrate support inside the reaction chamber. Both the substrate and support are heated to a desired temperature. In a typical substrate treatment step, reactant gases (also referred to as precursors) are passed over the heated substrate, causing the deposition (e.g., chemical vapor deposition, or CVD) of a thin layer on the substrate. CVD is typically conducted at high temperatures, such as 250-900° C.
Deposition equipment normally includes a system for delivering gas to the reaction chamber. The gas delivery system typically comprises a plurality of precursor sources, optionally one carrier gas and/or purge gas source, a network of pipes for delivering the precursor gases to the reaction chamber, eventually an injection manifold or showerhead for injecting the gas evenly into the chamber, and a number of valves for controlling the gas flow. Also, some precursor sources may be in powder or liquid form, and means for vaporizing such precursors can be provided (e.g., bubblers).
Another type of deposition process is atomic layer deposition (ALD). In ALD, two complementary precursors are alternatively introduced into the reaction chamber. Typically, a first precursor will adsorb onto the substrate surface, but it cannot completely decompose without the second precursor. The first precursor adsorbs until it saturates the substrate surface; further growth cannot occur until the second precursor is introduced. Thus, the film thickness is controlled by the number of precursor injection cycles rather than the deposition time, as is the case for conventional CVD processes. Accordingly, ALD allows for extremely precise control of film thickness and uniformity. ALD is typically conducted at temperatures in a range 250-500° C.
In ALD, the reaction chamber is typically pulsed with a non-reactive protective gas between injections of the two precursor gases, in an attempt to rid the chamber of any excess of the preceding precursor gas. Otherwise, the excess preceding precursor would intermix and react with the subsequently pulsed precursor to form unwanted CVD-type growth on the substrate surface and/or on surfaces of the chamber.
For various reasons, including low electrical resistivity, good thermal stability, and good diffusion barrier properties, there are numerous applications for titanium nitride (TiN) in the fabrication of integrated circuits. Exemplary applications include use as a contact or barrier layer and as an electrode in electrical devices, such as transistors.
For example, the Low Pressure Chemical Vapor Deposition (LPCVD) of TiN films in a hot wall furnace has been described by N. Ramanuja et al. in Materials Letters, Vol. 57 (2002), pp. 261-269. The reach of Ramanuja et al. is limited, however, as Ramanuja et al. investigated 100 mm wafers, rather than industry standard 200 mm and 300 mm wafers.
In addition to being able to form acceptable TiN films, it is desirable for the deposition temperature of the TiN deposition process to be relatively low, thereby increasing flexibility for integrating the deposition process with other processes and structures. For example, reducing deposition temperatures to the 400-500° C. range allows the films to be used in conjunction with multi-level aluminum or copper metallization.
It is an object and advantage of the present application to provide viable methods for in situ deposition of TiN and silicon onto substrates in a batch reactor.
In one aspect, a method of processing semiconductor wafers is provided. A batch of semiconductor wafers is loaded into a processing chamber. Titanium nitride (TiN) is deposited onto the wafers in the processing chamber. Silicon is deposited onto the wafers in the processing chamber, without removing the wafers from the processing chamber between said depositing steps.
In another aspect, an apparatus comprises a processing chamber, titanium precursor source, nitrogen precursor source, silicon precursor source, and valve system. The processing chamber is configured to contain a plurality of semiconductor wafers. The titanium, nitrogen, and silicon precursor sources are each connected to the chamber to deliver a vapor of the titanium, nitrogen, and silicon precursor, respectively, into the chamber. The valve system is configured to allow selective control of delivery of the vapors into the chamber.
For purposes of summarizing the present application and the advantages achieved over the prior art, certain objects and advantages have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
All of these embodiments are intended to be within the scope of the invention. These and other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description of the preferred embodiments having reference to the attached figures, the invention not being limited to any particular preferred embodiment(s) disclosed.
FIG. 1 is a flow chart illustrating a method of in situ deposition of TiN and silicon onto substrates within a batch reactor.
FIG. 2 illustrates an exemplary furnace for use with embodiments of the invention.
FIG. 3 illustrates an exemplary liquid delivery system for use with embodiments of the invention.
FIG. 4 illustrates another exemplary furnace for use with embodiments of the invention.
FIG. 5 illustrates an additional exemplary furnace for use with embodiments of the invention.
FIG. 6 is a schematic cross-sectional side view of an elongated batch process tube with a gas injector, constructed in accordance with one embodiment of the invention.
FIG. 7 is a front view of a gas injector for use with the batch process tube of FIG. 6.
FIG. 8 is a horizontal cross-sectional view of the gas injector of FIG. 7.
FIG. 9 is a reactant flow rate graph illustrating one method for depositing TiN.
FIG. 10 is a reactant flow rate graph illustrating another method for depositing TiN.
FIG. 11 is a reactant flow rate graph illustrating yet another method for depositing TiN.
It has recently been found that uniform and low resistivity TiN films can be economically deposited onto substrates in a batch reactor by periodically introducing, or pulsing, one or more precursors into the reaction chamber of the reactor. For example, U.S. Patent Application Publication No. 2006/0060137 A1 to Hasper et al. discloses forming TiN films using stable titanium and nitrogen precursors, i.e., precursors that are not radicals or a plasma. Hasper et al. disclose two general methods: (1) alternately pulsing a titanium precursor (such as titanium tetrachloride, TiCl4) and a nitrogen precursor (such as ammonia, NH3) into the reaction chamber; and (2) continuously flowing one of the precursors (such as NH3) into the reaction chamber while pulsing the other precursor (such as TiCl4). Hasper et al. found that these methods allow for the deposition of TiN films with good uniformity and low resistivity on industry size wafers, such as 200 mm or 300 mm wafers. Furthermore, Hasper et al. found that such methods allow for TiN deposition at lower temperatures (e.g., between 450-600° C.), such that the deposition is compatible with other processes such as multi-level aluminum or copper metallization.
A TiN film is susceptible to oxidation. Typically, a protective polysilicon capping film is deposited onto the TiN film shortly after the TiN film is deposited, to protect the TiN film from oxidation. Current methods involve depositing the TiN and the silicon capping film in two different reactors, because silicon deposition is normally conducted at temperatures that are significantly higher than the preferred temperature range for depositing TiN (e.g., 450-500° C., as taught by U.S. Patent Application Publication No. 2006/0060137 A1 to Hasper et al.). A primary reason why TiN and silicon have been deposited in separate reactors, as opposed to depositing both layers at different temperatures within the same reactor, is because changes in temperature of a process tube used for depositing silicon (e.g., polysilicon) lead to unacceptable amounts of particle generation in the reaction chamber, which adversely affects the quality of deposited films. As well understood, the deposition of silicon onto substrates in a reaction chamber also results in silicon deposition onto the reaction chamber walls. It is usually the case that the deposited silicon and the chamber walls have different coefficients of thermal expansion. For example, radiantly heated reaction chambers are typically formed of quartz walls, and the coefficients of thermal expansion of quartz and silicon are 0.59 ppm/K and 2.3 ppm/K, respectively. If the temperature is varied significantly, the chamber walls and the silicon deposited thereon will expand and contract at different rates. This causes silicon particles to flake off of the walls, thereby contaminating the chamber. For this reason, it is generally not desirable to change the temperature in a reaction chamber used for silicon deposition.
This problem also arises when TiN and silicon are deposited at different temperatures as adjacent layers on substrates. TiN has a coefficient of thermal expansion of 9.3 ppm/K. Thus, if TiN is deposited at one temperature (e.g., 450-500° C.) and silicon is deposited onto the TiN at a significantly higher temperature, there would be an unacceptable risk of flaking and particle generation caused by the differential in thermal expansion and contraction of the silicon and the TiN.
Another reason why TiN and silicon have been deposited in separate reactors, as opposed to depositing both layers at different temperatures within the same reactor, is that it takes longer to wait for the temperature to change and stabilize throughout the chamber (particularly for a batch reactor) than it takes to transfer the one or more substrates to another chamber maintained at a different temperature. At the relatively low temperature used for TiN deposition, heat transport through radiation is limited. Heat transport by conduction is also not very efficient for a stack of substrates in a batch furnace at low pressure. Consequently, temperature stabilization is slow, and it is often less time consuming to transfer the substrates to another chamber.
The practice of depositing TiN and silicon in different reactors involves several problems and drawbacks. The need to transfer substrates between two separate reactors involves greater equipment costs and more complicated processing, and results in lower throughput. Further, while transferring the substrate with the TiN film from the TiN deposition reactor to a silicon deposition reactor, the TiN becomes exposed to air, which leads to an undesirable interface between the TiN and the silicon capping film.
Embodiments of the present application involve depositing a TiN film and an amorphous silicon capping film onto a plurality of substrates in a single batch reactor in situ, without removing the substrates from the processing chamber between these deposition steps. By depositing both films in the same reactor, it is possible to avoid the formation of an undesired interface between the TiN and the polysilicon capping film. The elimination of one reactor reduces costs. Also, the elimination of the intermediate substrate transfer step simplifies the processing logistics and increases substrate throughput.
FIG. 1 illustrates the process. First, a plurality of substrates, such as semiconductor wafers, is loaded 1 into a processing chamber of a batch reactor. TiN is deposited 2 onto the wafers in the processing chamber. Silicon is deposited 3 onto the wafers in the processing chamber, without removing the wafers from the processing chamber between said depositing steps 2 and 3.
“Substrate” is used herein in its usual sense to include any underlying surface onto which a material is deposited or applied. Preferred substrates include semiconductor wafers, such as silicon wafers. However, substrates can be made of virtually any material, including without limitation metal, silicon, germanium, plastic, and/or glass, preferably silicon compounds (including Si—O—C—H low dielectric constant films) and silicon alloys. Substrates can also have in them physical structures such as trenches or steps, as in a partially fabricated integrated circuit.
In some embodiments, the TiN deposition is conducted in accordance with the aforementioned methods taught by U.S. Patent Application Publication No. 2006/0060137 A1 to Hasper et al.: (1) alternately pulsing a titanium precursor (such as TiCl4) and a nitrogen precursor (such as NH3) into the reaction chamber, preferably with purge or evacuation steps therebetween; and (2) continuously flowing one of the precursors (such as NH3) into the reaction chamber while pulsing the other precursor (such as TiCl4). In other embodiments, the TiN deposition involves the following cyclical sequence: substantially simultaneous pulses of the titanium and nitrogen precursors, a purge or evacuation step, another nitrogen precursor pulse (referred to elsewhere herein as a “flush”), and then another purge or evacuation step. In some embodiments, both the TiN deposition and the polysilicon deposition are conducted at a relatively low temperature (e.g., 300-600° C., more preferably 400-500° C.). In preferred embodiments, trisilane (Si3H8) is used as a silicon precursor.
While the above discussion contemplates the in situ deposition of silicon capping films onto TiN films, in some embodiments the deposition sequence of the films is reversed, such that TiN films are deposited in situ onto previously deposited silicon films. For example, in FIG. 1, the silicon deposition 3 can occur before the TiN deposition 2.
As mentioned above, the in situ deposition of TiN and silicon films is preferably conducted on a plurality of substrates, such as semiconductor wafers, in a batch reactor. Several exemplary batch reactors are now described.
Preferably, the batch reactor is configured or programmed to deliver one or more precursors in temporally separated pulses. The batch reactor preferably has a vertically extending reaction chamber that accommodates substrates vertically separated from each other, with major faces of the substrates oriented horizontally. Preferably, the reaction chamber accommodates at least 25 substrates, and more preferably at least 50 substrates.
FIG. 2 schematically shows a vertical furnace reactor 10 that accommodates substrates 40 vertically separated from one another, and which has benefits for efficient heating and loading sequences. The furnace 10 is preferably adapted to support 100-125 substrates. Examples of suitable vertical furnaces are the A400™ and A412™ vertical furnaces, commercially available from ASM International, N.V. of Bilthoven, the Netherlands. A vertical furnace type of reactor has benefits for efficient heating and loading sequences. It will be understood, however, that while preferred embodiments are presented in the context of a vertical batch furnace, the principles and advantages disclosed herein will have application to other types of reactors. For example, while the illustrated reactors are shown holding substrates in a vertically-separated manner, the methods described herein can be applied to a batch reactor that holds substrates in a horizontally separated manner.
With continued reference to FIG. 2, a tube 12 defines a reaction chamber 20 in the interior of the vertical furnace or reactor 10. The lower end of the tube 12 terminates in a flange 90, which mechanically seals the chamber 20 by contact with a lower support surface 14. Process gases can be fed into the reaction chamber 20 through a gas inlet 22 at the top of the chamber 20 and evacuated out of the chamber 20 through a gas outlet 24 at the bottom of the chamber 20. The reaction chamber 20 accommodates a wafer boat 30 holding a stack of vertically spaced substrates or wafers 40.
The process tube flange 90 can be maintained at an elevated temperature to avoid condensation of process gases on it. It will be appreciated that the elevated temperature can vary from process to process and is preferably chosen based upon the identities of the process gases (which, in some embodiments, are TiCl4, NH3, Si3H8, and N2). For example, the elevated temperature of the flange 90 is preferably above 120° C., preferably about 180-200° C. Regulation of the temperature of the flange 90 can be achieved by providing it with electrical heaters and a water-cooling system. The water-cooling is desired primarily to avoid overheating of the flange 90 during unloading of a batch of hot wafers 40.
Various systems can be used to supply reactants or precursors to the reaction chamber 20 (FIG. 2). For example, where the precursor is a gas, it can be flowed directly from a gas source to the chamber 20. The timing and rate of the flow of the gas can be controlled by, e.g., mass flow controllers, as known in the art.
FIG. 3 schematically shows an exemplary system for controlling the flow of liquid precursors, such as TiCl4. The liquid precursor is stored in a container 50. Liquid flow control is used to regulate the amount of the liquid precursor flowing into the reactor 10 by regulating the flow of the liquid into an evaporator or vaporizer 60. After being vaporized, well-separated pulses of a precursor can be generated and flowed into the reaction chamber 20 using a valve system 70 comprising valves 80, shown in the upper section of FIG. 3. Preferably, the valves 80 of the valve system 70 are operated at elevated temperatures and have no or minimal dead volume, to provide good separation between the flow of different reactants. Such a valve system is described in further detail in U.S. Patent Application Publication No. 2004/0250853 A1.
As noted above, process gases can be introduced into the chamber 20 in various ways. For example, in the reactor illustrated in FIG. 2, all gases are introduced into the interior 20 of the reactor 10 at the top, via the top inlet 22, and exhausted at the bottom of the reactor 10, via the exhaust 24. In other embodiments, a more even distribution of the process gases can be achieved over the length of the tube by using multiple-hole injectors for introduction of process gases into the reactor. Suitable multiple-hole injectors are disclosed in U.S. Pat. No. 6,746,240, and U.S. Patent Application Publication No. 2003/0111013 A1. Alternatively, less spacious and cylindrical multiple-hole injectors can be used. Such injectors can have, e.g., a diameter of about 25 mm and holes of about 1 mm diameter. In some preferred embodiments, multiple-hole injectors are preferably mounted on or beneath the flange 90 at the lower end of the reaction chamber 20 and point upwardly.
A multiple-hole injector is preferably not used to introduce a purge gas, however, because the top part of the reaction chamber 20 may be not effectively purged by an injector that only extends part way up the height of the chamber 20. Preferably, a purge gas is introduced into the chamber 20 at the chamber end that is opposite to the exhaust end, so that the purge gas flows through all regions of the reaction chamber 20 after entry and before being exhausted.
FIG. 4 shows another exemplary batch reactor. In this design, the process tube 100 is closed at the top. An advantage of this design is that the process tube 100 is simpler in construction and eventual problems with the gas-tightness and the thermal isolation of the top inlet 22 (FIG. 2) can be prevented. All gases in this set-up are introduced through gas injectors 110, of which two are shown. Preferably, separate injectors 110 are used for each gas. In the case of TiN deposition, one injector 110 can be used for each of the titanium precursor gas (such as TiCl4) and the nitrogen precursor gas (such as NH3). An additional injector 110 can be provided for the silicon precursor gas (such as Si3H8). These injectors 110 are preferably multiple-hole gas injectors having holes distributed over the height of the tube 100. The injectors 110 may be each oriented substantially perpendicular to the substrates. Each injector 110 may extend along a majority of a length of the arrangement of substrates. An exhaust 24 is provided, preferably at the bottom of the tube 100, for process gases exiting the tube 100.
An additional injector 110 can be used for a purge gas, preferably an inert gas such as nitrogen gas. The injector 110 for the purge gas is preferably a tube with an open end at the top and without gas discharge holes in its sidewall, so that all the purge gas is discharged at the top of the reaction chamber 120. FIG. 5 illustrates a reactor 10 having three vertically extending injectors, 110 a, 110 b and 110 c. The injectors 110 a, 110 b and 110 c each have an inlet 140 a, 140 b, and 140 c, respectively, for connecting to one or more gas feeds. The injector 110 b opens at its top end 112 to allow purge gas to flow downward through the reactor 10 and to exit out the exhaust 24 at the bottom of the reactor 10. In other embodiments, the exhaust 24 can be at the top of the reaction chamber 120 and the purge gas can be discharged at the bottom of the reaction chamber 120. Advantageously, using such multiple-hole gas injectors, the evenness of gas distribution into the reaction chamber can be improved, thereby improving the uniformity of deposition results.
FIGS. 6-8 illustrate another version of an exemplary batch reactor, also commercially available under the trade name Advance 412™ or A412™ from ASM International N.V. of Bilthoven, The Netherlands. FIG. 6 is a schematic cross-sectional side-view of the elongated furnace with a gas injector. The process tube or chamber 526 is preferably surrounded by a heating element (not shown). A liner 528, delimiting the outer perimeter of the reaction space 529, is preferably provided inside the process chamber 526. Preferably, at the bottom of the process chamber 526, a wafer load 550 may enter and exit the process chamber 526 by a door 530. Precursor source gas is injected through a gas injector 540, preferably via a gas feed conduit 544. The gas injector 540 is provided with a pattern of holes 548, preferably extending substantially over the height of the wafer load 550. Note that, because gases are first introduced into the reaction space 529 from the holes 548 of the gas injector 540, the interior of gas delivery devices through which gases travel, such as the gas injector 540, is not part of the reaction space 529 and is, in a sense, outside of the reaction space 529. Consequently, the reaction space 529 comprises the interior volume of the process chamber 526, excluding the volume occupied by gas delivery devices such as the gas injector 540. Further details of the chamber 526 are provided in U.S. Patent Application Publication No. 2003/0111013 A1.
In a preferred embodiment, inside the process chamber 526, gas is flowed in a generally upward direction 552 and then removed from the reaction space 529 via an exhaust space 554 between the process chamber 526 and the liner 528, where gas flows in a downward direction 556 to the exhaust 558, which may be connected to a pump (not shown). The gas injector 540 preferably distributes process gases inside the process chamber 526 over the entire height of the reaction space 529. The gas injector 540 itself acts as a restriction on the flow of gas, such that the holes 548 that are closer to the conduit 544 tend to inject more gas into the reaction space than those holes 548 that are farther from the conduit 544. Preferably, this tendency for differences in gas flows through the holes 548 can be compensated to an extent by reducing the distance between the holes 548 (i.e., increasing the density of the holes 548) as they are located farther away from the conduit 544. In other embodiments, the size of individual holes making up the holes 548 can increase with increasing distance from the conduit 544, or both the size of the holes 548 can increase and also the distance between the holes 548 can decrease with increasing distance from the conduit 544. Advantageously, however, the preferred embodiments are illustrated with holes 548 of constant size so as to minimize the surface area of the sides of the gas injector 540 containing the holes 548.
The injector 540 is advantageously designed to reduce the pressure inside the gas injector, resulting in a reduction of the gas phase reactions within the injector, since reaction rates typically increase with increasing pressure. While such reduced pressure can also lead to a poor distribution of gas over the height of the gas injector 540, the distribution of holes 548 across the height of the injector 540 is selected to improve uniformity of gas distribution.
FIG. 7 shows one illustrative embodiment of the gas injector 540. The gas injector 540 preferably comprises two gas injector parts 541 and 542, each preferably provided with separate gas feed conduit connections 545 and 546, respectively. The first part 541 injects gas into the lower volume of the reaction space 529 (FIG. 6) and the second part 542 injects gas into the upper volume of the reaction space 529. The parts 541 and 542 are connected by linkages 549 and 551. At its top end, the gas injector 540 can be provided with a hook 553, to secure the top end of the gas injector 540 to a hook support inside the chamber 526 (FIG. 6).
The gas injector 540 is provided with a pattern of holes 548 substantially extending over the height 560 (FIG. 6) of the wafer load 550. The total cross section of the holes is preferably at least about 30 mm2. The diameter of each of holes 548 is preferably about 1 mm or more, more preferably between about 2.5 mm and 3.5 mm, and in one embodiment about 3 mm. In the illustrative embodiment shown in FIG. 7, the gas injector 540 has a total of 40 holes 548 for a total hole cross-sectional area of about 282 mm2. More generally, the total cross-sectional area of the holes 548 is preferably about 30 mm2 or more, and more preferably between about 196 mm2 and 385 mm2.
With reference to FIG. 8, each part 541 and 542 of the gas injector 540 has an inner cross-sectional area 564 and 562, respectively, available for the conduction of source gases through the gas injector 540. Preferably, each of inner cross-sectional areas 564 and 562 are at least about 100 mm2. In the illustrated embodiment, the cross-sectional area of each of the parts 541, 542 of the gas injector 540 is about 330 mm2. More generally, the cross-sectional area of each of the parts 541, 542 is preferably between about 140 mm2 and 600 mm2, more preferably between about 225 mm2 and 455 mm2.
The cross-section shown in FIG. 8 is taken through the lower end of the gas injector 540 and straight through a pair of injection holes 548 provided in gas injector part 541, for injecting the gas into the lower end of the process chamber 526. Preferably, in each gas injector part, the holes 548 are provided in pairs, at the same height. In addition, the two holes 548 preferably inject the precursor gas in two directions 566 and 568 forming an angle 570 of between about 60 and 120 degrees, illustrated at about 90 degrees, to improve the radial uniformity. Moreover, as shown, the tubes comprising the gas injector 540 preferably have an oblong shape, as viewed in horizontal cross-section. Preferably, the longer dimension of the oblong shape faces the center of the process chamber 526, i.e., the side of the oblong shape with the longer dimension is perpendicular to an imaginary line extending radially from the center of the process chamber 526.
In a preferred embodiment, in a CVD mode, two precursor source gases, providing the two constituting elements of a binary film, are mixed in the gas supply system (not shown) prior to entering the gas injector 540 via feed conduit connections 545 and 546 (FIG. 7). Pre-mixing the precursor gases in the gas supply system is one way to ensure a homogeneous composition of injected gas over the height of the boat. However, the gases can be flowed into the process chamber 526 (FIG. 6) without pre-mixing. In another embodiment, the two precursor source gases can each be injected via their own separate gas injectors 540 (not shown), so that they are first mixed after being injected into the reaction space 529. Consequently, it will be appreciated that more than one gas injector 540 may be located inside the process chamber 526.
Advantageously, the use of two gas injector parts 541 and 542 allows for further tuning possibilities. The flows supplied to the different gas injector parts 541, 542 can be chosen differently to fine-tune the gas flow into the reaction space 529. This will improve uniformity in the deposition rates of precursors over the height 560 of the wafer load 550 (FIG. 6).
One skilled in the art will appreciate that further modifications to the batch reactor, or to the way of operating the batch reactor, known in the art, can be applied to improve the performance of this process. For example, it is possible to use a holder boat or ring boat (i.e., a wafer boat in which each wafer is individually supported by a separate wafer holder or ring-shaped holder inserted into the boat).
It will be appreciated that while the aforementioned hardware configurations are described in the context of pulsed CVD and ALD, they are equally suitable for use in the context of low pressure chemical vapor deposition (LPCVD).
It has been found that uniform and low resistivity TiN films can be deposited on wafers in a batch reactor by periodically introducing, or pulsing, one or more precursors into the reaction chamber of the reactor. Preferably, the TiN films are formed using stable titanium and nitrogen precursors, i.e., precursors which are not radicals or a plasma. More preferably, titanium tetrachloride (TiCl4) and ammonia (NH3) are used as the titanium and nitrogen precursors, respectively.
In one method, both precursors (e.g., TiCl4 and NH3) are alternately pulsed into the reaction chamber, preferably with intermediate purge gas injections or chamber evacuation steps. In this method (described below with reference to FIG. 9), each pair of pulses comprises one cycle, and any number of cycles can be conducted. In another method (described below with reference to FIG. 10), only one precursor is pulsed while the other precursor flows continuously into the reaction chamber. In some preferred embodiments, the titanium precursor, e.g., TiCl4, is pulsed into the reaction chamber while the nitrogen precursor, e.g., NH3, is flowed continuously into the chamber. In still another method (described below with reference to FIG. 11), each cycle includes, in the following sequence, substantially simultaneous pulses of the titanium and nitrogen precursors, a purge or evacuation step, another nitrogen precursor pulse (also referred to as a “flush”), and then another purge or evacuation step. The second nitrogen precursor pulse or flush is provided to more fully react nitrogen with any remaining titanium from the prior titanium pulse.
The TiN deposition advantageously can be performed at a temperature of less than about 600° C. and, more preferably, at less than about 500° C., e.g., about 450-500° C. Thus, the deposition is compatible with other processes such as multi-level aluminum or copper metallization. In addition, the deposition can advantageously be used to deposit films on industry standard 200 mm and 300 mm wafers.
In some preferred embodiments, a stack of vertically-spaced substrates, e.g., semiconductors wafers, is accommodated in a batch reaction chamber and temporally separated pulses of the titanium and nitrogen precursors, such as TiCl4 and NH3, are supplied to the reaction chamber alternatingly and sequentially in an ALD of TiN. FIG. 9 is a reactant flow rate graph illustrating an embodiment of this method for alternate pulses of TiCl4 and NH3. While not shown, it will be understood that chamber purge or evacuation steps can be conducted during time intervals between the alternate pulses of the reactants. In FIG. 9, the TiCl4 and NH3 flows are shown separately for clarity. The cycling sequence preferably ends with a nitrogen precursor gas (e.g., NH3) pulse. In other words, after the last TiCl4 pulse, an additional NH3 pulse is preferably injected, which is not followed by another TiCl4 pulse.
The deposition rate of the TiN has been found to be particularly sensitive to variations in the gas partial pressure of NH3. As a result, NH3 is preferably flowed into the chamber using a gas injector having vertically distributed holes to allow an even distribution of the NH3. Preferably, each reactant is removed, e.g., by purging with an inert gas or evacuating the reaction chamber, before introduction of the other reactant. The duration of each of the pulses is preferably about 60 seconds or less, more preferably about 30 seconds or less, and even more preferably about 15 seconds or less.
When TiN films are formed by continuous CVD, by continuously flowing TiCl4 and NH3 into a reaction, the deposition rate of the TiN films has been found to not vary significantly with the partial pressure of the TiCl4. On the other hand, the deposition rate has been found to be approximately proportional to the partial pressure of the NH3. For depositing uniform films, these findings indicate that the mode of introduction and distribution of NH3 inside the reaction chamber is more important than that for TiCl4, whether or not NH3 is pulsed into the chamber, e.g., whether or not NH3 is used in an ALD or pulsed CVD process. As a result, as noted above, NH3 is preferably discharged into the reaction chamber in a manner that maximizes the evenness of the distribution of the gas into the chamber. In particular, NH3 is preferably discharged into the vertical furnace reaction chamber in a vertically distributed manner, e.g., through a multiple-hole injector having a plurality of vertically spaced apart holes, such as those discussed above. The injector preferably extends substantially over a height of the chamber, such that the holes of the injector span most or all of the vertical height occupied by the substrates. TiCl4 can also be discharged using the multiple-hole injector, or it can be discharged at a feed end of the reaction chamber (FIG. 2).
In other preferred embodiments, the nitrogen precursor, e.g., NH3, is continuously supplied to the reaction chamber and only the titanium precursor, e.g., TiCl4, is supplied pulse-wise, resulting in CVD of TiN. FIG. 10 is a reactant flow rate graph illustrating an embodiment of this method for pulsed flow of TiCl4 and continuous flow of NH3. In FIG. 10, the TiCl4 and NH3 flows are superimposed for a better understanding of relative flow rate value. Advantageously, such a deposition scheme allows an increased deposition rate per reactant pulse without losing film quality, in comparison to a scheme in which both TiCl4 and NH3 are alternately pulsed. By continuously flowing one precursor, more than one monolayer of TiN is typically deposited per TiCl4 pulse. In addition, where the titanium precursor pulses are relatively short, the deposited titanium-containing films are effectively nitrided by the nitrogen precursor flow between the titanium precursor pulses. Thus, high quality, low resistivity and uniform TiN films can be obtained at relatively low deposition temperatures of preferably less than about 600° C., and, more preferably, less than about 500° C., e.g., about 450° C. Preferably, the pulse duration is about 60 seconds or less, more preferably, about 30 seconds or less and, most preferably, about 15 seconds or less.
In still other preferred embodiments, each deposition cycle includes, in the following sequence, substantially simultaneous pulses of the titanium and nitrogen precursors, a purge or evacuation step, another nitrogen precursor pulse, and then another purge or evacuation step. FIG. 11 is a reactant flow rate graph illustrating an embodiment of this method for pulses of TiCl4 and NH3. FIG. 11 shows the TiCl4 and NH3 flows separately for clarity. In this embodiment, TiCl4 pulses 200 occur substantially simultaneously with NH3 pulses 210. However, an additional NH3 pulse 220 (also referred to as an “ammonia flush”) occurs temporally between the combined or simultaneous pulses 200, 210. While not shown, it will be understood that a chamber purge or evacuation step can be conducted after the combined pulse 200, 210 and before the ammonia flush 220. In addition, another chamber purge or evacuation step can be conducted after the ammonia flush 220 and before the next combined pulse 200, 210. In other words, if the pulses 200 and 210 occur during a first time interval of the deposition cycle, and if the pulse 220 occurs during a second time interval of the cycle, then the purge or evacuation steps can be conducted between the first and second time intervals and again after the second time interval.
Advantageously, high quality titanium nitride films can be formed in accordance with the preferred embodiments. For example, the thicknesses of deposited titanium nitride films can vary by less than about 3 nm between substrates in a batch of substrates, and the resistivity can vary by less than about 5 μOhm·cm. Moreover, the films can be formed having a low resisitivity of about 220 μOhm·cm or less.
Advantageously, at lower deposition temperatures (e.g., 450° C.), the average film thickness across a wafer has been found to be exceptionally uniform from wafer to wafer, varying less than about 3 nm among the various wafers of a batch of wafers. At this temperature, the average resistivity of the films has been found to be advantageously uniform, varying less than about 5 μOhm·cm among the various wafers in the batch.
It is understood that precursor pulse time affects film thickness and resistivity. While longer pulse times would be expected to increase or possibly not affect the thickness of the deposited film in cases where the total TiCl4 exposure time was unchanged, it has been unexpectedly found that pulse times longer than about 30 seconds actually cause a decrease in average film thickness (in some experiments, from about 23.5 nm to about 23 nm). Even more unexpectedly, the average resistivity of the deposited film has been found to be strongly dependent on pulse times. In particular, in some experiments, film resistivity has been found to increase from about 220 μOhm·cm for TiCl4 pulse durations of about 15 seconds to about 520 μOhm·cm for TiCl4 pulse durations of about 60 seconds. Thus, shorter pulse times advantageously allow deposition of TiN films with reduced resistivity, e.g., about 220 μOhm·cm or less.
In addition, the cycle duration can be selected to give a desired TiN film resistivity. For example, resistivities of about 520 μOhm·cm to about 220 μOhm·cm can be achieved by appropriately adjusting the TiCl4 pulse time (e.g., between about 15-60 seconds), or the duration of each cycle of process gases can be adjusted (e.g., between about 1-10 minutes).
Silicon Deposition
As discussed above, a silicon layer can be deposited onto the wafers in the batch reactor either before or after the TiN layer is deposited. The silicon layer may comprise amorphous silicon, and may be deposited by CVD, preferably at a low temperature or a temperature that is the same as or relatively close to the temperature at which the TiN layer is deposited. The deposited silicon and TiN layers can be deposited in direct contact with one another (e.g., immediately adjacent). The silicon layer may be deposited over the TiN layer so as to be a protective capping film. Alternatively, the TiN layer can be deposited over the silicon layer.
Between the steps of TiN deposition and silicon deposition, any excess precursor of associated with the earlier-deposited layer can be removed from the chamber by the injection of a purge gas, by a chamber evacuation process, by displacement of the earlier precursor gas by a gas carrying a reactive species, or any combination thereof. Where the earlier precursor gas is removed by purging, the process chamber is preferably purged for a duration long enough to replace the atmosphere in the chamber at least once.
A silane is preferably used as the silicon precursor. The silane can be selected from the group consisting of monosilane (SiH4), a polysilane and a chlorosilane (SiH4-nCln, where n=1 to 4). More preferably, a polysilane is used as the silicon precursor to form the silicon layer, discussed below. As used herein, a “polysilane” has the chemical formula SinH2n+2, where n=2 to 4. Preferably, the polysilane is disilane or trisilane. Most preferably, the polysilane is trisilane. Consequently, while embodiments of the invention are described in the context of employing CVD cycles with trisilane, the skilled artisan will appreciate, in view of the present disclosure, that certain advantages of the described processes can be obtained with other precursors and/or other deposition techniques.
Trisilane (H3SiSiH2SiH3 or Si3H8) offers substantial benefits when used as a silicon precursor, as disclosed in U.S. Patent Application Publication No. 2005/0118837 A1 and U.S. Pat. No. 6,962,859. For example, films can be deposited with trisilane at substantially lower temperatures than with other silicon precursors, such as silane (SiH4), which advantageously makes possible in situ deposition of both TiN and silicon in a low temperature range (e.g., 400-500° C.). Moreover, deposition rates with trisilane are relatively insensitive to substrate material and thickness. Also, trisilane has an extremely short film nucleation time, which reduces the size of localized crystalline deposits of silicon. As a result, deposited silicon films can be made thinner, while still being uniform. Moreover, the films will show reduced surface roughness due to the reduced size of the localized silicon deposits. In addition, with regards to process throughput, trisilane exhibits higher deposition rates relative to silane. Trisilane also reduces thermal budgets, since it allows use of lower process temperatures than does silane.
Thus, employing trisilane in the deposition methods described herein provides numerous advantages. For example, these deposition methods enable in situ deposition of TiN and silicon layers in a single reaction chamber. These methods also enable the production of silicon-containing compound films that are uniformly thin and continuous. These advantages, in turn, enable devices to be produced in higher yields, and also enable the production of new devices having smaller circuit dimensions and/or higher reliability.
The silicon precursor is preferably introduced into the process chamber in the form of a feed gas or as a component of a feed gas. The feed gas can include gases other than the silicon precursor, such as inert carrier gases. The carrier gas can comprise carrier gases known in the art, such as nitrogen, hydrogen, helium, argon, or various combinations thereof. Where the silicon precursor is trisilane, the trisilane is preferably introduced into the chamber by way of a bubbler used with a carrier gas to entrain trisilane vapor. More preferably, a temperature controlled bubbler is utilized.
In forming the silicon layer, deposition from a silicon precursor can be conducted according to various deposition methods known to those skilled in the art, but the greatest benefits are obtained when deposition is conducted according to the CVD methods taught herein. The disclosed methods can be practiced by employing CVD, including plasma-enhanced chemical vapor deposition (PECVD) or, more preferably, thermal CVD.
Deposition conditions are preferably tailored to processing in the particular type of reactor in which substrates are loaded. In general, deposition conditions are established to supply sufficient energy to pyrollize or decompose the silicon precursor on a hot substrate surface.
In addition, deposition conditions are preferably established so that the reaction rate of the silicon precursor is the limiting variable for the silicon deposition rate. Thus, the ability of hot wall reactors to achieve highly uniform temperature distributions can advantageously be applied to form uniform layers. While depositions conducted under reaction kinetics limited conditions have deposition rates that are sensitive to temperature changes, the ability to establish high temperature uniformity minimizes the effect of this sensitivity. Moreover, reaction kinetics limited conditions advantageously have deposition rates that are relatively insensitive to supplied reactant concentrations.
It will be appreciated that a reaction kinetics limited regime is primarily achieved by use of a relatively low temperature. This results in a reduced film deposition rate that is preferable in a batch furnace. Because of the large batch size, an adequate throughput can still be achieved at a deposition rate that results from temperatures shifted down into the reaction rate limited regime. Advantageously, trisilane enables acceptable deposition rates at very low temperatures, allowing a considerably reduced consumption of thermal budgets. As the skilled artisan will readily appreciate, thermal budgets are constantly reduced as critical dimensions are scaled down, tolerances for diffusion are reduced, and new materials with lower resistance to thermal processing are introduced. The silicon deposition process is preferably operated at a temperature below about 600° C., more preferably below about 525° C., more preferably below about 500° C., more preferably below about 475° C. The silicon can be deposited at a temperature between about 300° C. and about 500° C.
In addition to temperature, the skilled artisan will appreciate that the kinetic regime is partially dependent upon the reactant supply or partial pressure of the silicon precursor. Preferably, the reaction rate is slower than the rate at which reactant is supplied.
The thickness of the deposited silicon film can be varied according to the intended application, as known in the art, by varying the deposition time and/or gas flow rates for a given set of deposition parameters (e.g., total pressure and temperature).
A silicon layer is first deposited by flowing a silicon precursor, preferably trisilane. As noted, process conditions are preferably arranged for deposition in the kinetic regime. The process is preferably operated at a temperature below about 600° C. and, more preferably, at a temperature below about 500° C., and, even more preferably, at a temperature between about 400-450° C. In addition, the reactant supply or partial pressure of trisilane is preferably set at a sufficiently low level to maintain the deposition in the kinetic regime. As long as the reaction rate is slower than the rate at which reactant is supplied, uniformity in a properly tuned batch furnace (in which uniform temperatures can be maintained) is excellent. Reference is made to Sze, VLSI TECHNOLOGY, pp. 240-41 (1988). In the illustrated batch reactors, process pressure is maintained at about 10 Torr or below and more preferably about 1 Torr or below. In order to maintain reaction rate limited deposition, trisilane preferably is supplied at less than about 100 sccm trisilane, and, more preferably, at less than about 20 sccm. The trisilane is typically diluted with a flow of a non-reactive or inert gas such as N2, H2, Ar or He. The trisilane partial pressure is thus preferably below about 10 mTorr, more preferably, about 3-4 mTorr. Preferably, a trisilane deposition step has a duration of about 30-120 seconds.
In addition, the silicon deposition and the TiN deposition (described above) are preferably conducted under generally isothermal conditions. In other words, if the TiN deposition is conducted at a first average temperature and the silicon deposition is conducted at a second average temperature, then the first and second temperatures differ, if at all, by preferably less than 100° C., more preferably less than 50° C., and even more preferably less than 20° C. An “average temperature” refers to a time-averaged temperature, reflecting the possibility that temperature may fluctuate during a deposition process. Conducting the silicon deposition and TiN deposition at the same or similar average temperatures simplifies processing because there is no need to significantly adjust temperature between deposition steps, or to transfer the substrates to a different reactor. In one embodiment, the TiN and silicon depositing steps are both conducted at temperatures within about 400-550° C., and more preferably within about 450-500° C.
Advantageously, the above-described in situ deposition of TiN and silicon within a relatively narrow temperature range can be conducted without producing an undesirable amount of particle generation. As described above, a chamber used for in situ processes at significantly different temperatures results in unacceptable particle generation when one of the processes is silicon deposition, due in large part to the differential in thermal expansion and contraction between the silicon and the other parts of the reaction chamber, such as the chamber walls. Silicon and TiN also have significantly different rates of thermal expansion and contraction, exacerbating the problem for adjacent TiN and silicon layers. However, the presently disclosed embodiments substantially overcome this problem, due to the relatively narrow temperature range within which the TiN and silicon layers are deposited.
The following represents process conditions in one example of in situ deposition of TiN and amorphous silicon layers onto a plurality of semiconductors in a batch reaction chamber. For pulsed CVD TiN deposition, temperature in the reaction chamber can be about 450° C., and pressure can be about 200 mTorr. The titanium precursor can be TiCl4, and the nitrogen precursor can be NH3. The TiCl4 can be delivered to the chamber via an N2 carrier gas. The flow rate of TiCl4 during the TiCl4 pulses can be about 1.5 g/min, and the flow rate of the N2 carrier gas can be about 200 sccm. The flow rate of the NH3 during deposition can be about 0.19 slm. The duration of the TiCl4 pulses can be 15 seconds, 30 seconds, or 60 seconds.
As discussed above, the TiN deposition can be conducted in three ways: (1) alternately pulsing the TiCl4 and NH3 precursors into the reaction chamber, preferably with purge or evacuation steps therebetween; (2) continuously flowing one of the precursors (such as NH3) into the reaction chamber while pulsing the other precursor (such as TiCl4); and (3) repeating the following cycle: substantially simultaneous pulses of TiCl4 and NH3, a purge or evacuation step, another NH3 pulse (also known as an “ammonia flush”), and then another purge or evacuation step. The NH3 flow during the ammonia flush can be about 1 slm.
A capping film of amorphous silicon can be deposited in situ onto the TiN layer. The temperature and pressure of the reaction chamber can be maintained at about 450° C. and about 200 mTorr, respectively. Trisilane can be continuously injected into the chamber at a flow rate of about 60 sccm, with an N2 carrier gas flow rate of about 1 slm.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS2865791Feb 28, 1955Dec 23, 1958Metallgesellschaft AgMetal nitride coating processUS4188444Feb 23, 1978Feb 12, 1980Pilkington Brothers LimitedMethod of coating glass and glass coated therebyUS4262631Oct 1, 1979Apr 21, 1981Kubacki Ronald MThin film deposition apparatus using an RF glow dischargeUS4277320Oct 1, 1979Jul 7, 1981Rockwell International CorporationProcess for direct thermal nitridation of silicon semiconductor devicesUS4279947Mar 26, 1979Jul 21, 1981Motorola, Inc.Deposition of silicon nitrideUS4298629Mar 7, 1980Nov 3, 1981Fujitsu LimitedMethod for forming a nitride insulating film on a silicon semiconductor substrate surface by direct nitridationUS4363828Dec 12, 1979Dec 14, 1982International Business Machines Corp.Method for depositing silicon films and related materials by a glow discharge in a disiland or higher order silane gasUS4389973Dec 11, 1981Jun 28, 1983Oy Lohja AbApparatus for performing growth of compound thin filmsUS4402997May 17, 1982Sep 6, 1983Motorola, Inc.Process for improving nitride deposition on a semiconductor wafer by purging deposition tube with oxygenUS4413022Jun 21, 1979Nov 1, 1983Canon Kabushiki KaishaMethod for performing growth of compound thin filmsUS4428975Jan 28, 1983Jan 31, 1984Motorola, Inc.Process for improving nitride deposition on a semiconductor waferUS4495218Sep 22, 1983Jan 22, 1985Hitachi, Ltd.Process for forming thin filmUS4535000Oct 28, 1983Aug 13, 1985Gordon Roy GChemical vapor deposition of titanium nitride and like filmsUS4570328Mar 7, 1983Feb 18, 1986Motorola, Inc.Method of producing titanium nitride MOS device gate electrodeUS4585671Nov 15, 1983Apr 29, 1986Mitsui Toatsu Chemicals, IncorporatedFormation process of amorphous silicon filmUS4684542Aug 11, 1986Aug 4, 1987International Business Machines CorporationLow pressure chemical vapor deposition of tungsten silicideUS4699805Jul 3, 1986Oct 13, 1987Motorola Inc.Process and apparatus for the low pressure chemical vapor deposition of thin filmsUS4715937May 5, 1986Dec 29, 1987The Board Of Trustees Of The Leland Stanford Junior UniversityLow-temperature direct nitridation of silicon in nitrogen plasma generated by microwave dischargeUS4803127Oct 22, 1987Feb 7, 1989Liburdi Engineering LimitedVapor deposition of metal compound coating utilizing metal sub-halides and coated metal articleUS4834020Dec 4, 1987May 30, 1989Watkins-Johnson CompanyAtmospheric pressure chemical vapor deposition apparatusUS4851095Feb 8, 1988Jul 25, 1989Optical Coating Laboratory, Inc.Magnetron sputtering apparatus and processUS4855254Dec 13, 1988Aug 8, 1989Fujitsu LimitedMethod of growing a single crystalline β-SiC layer on a silicon substrateUS4935661Jun 26, 1986Jun 19, 1990Stc PlcPulsed plasma apparatus and processUS4943581Jun 26, 1989Jul 24, 1990Hokuriku Pharmaceutical Co., Ltd.IsoquinolinesulfonamidesUS5015330Feb 28, 1990May 14, 1991Kabushiki Kaisha ToshibaFilm forming method and film forming deviceUS5111266Jun 12, 1991May 5, 1992Fujitsu LimitedSemiconductor device having a region doped to a level exceeding the solubility limitUS5214002Dec 3, 1991May 25, 1993Agency Of Industrial Science And TechnologyProcess for depositing a thermal CVD film of Si or Ge using a hydrogen post-treatment step and an optional hydrogen pre-treatment stepUS5227329Aug 30, 1991Jul 13, 1993Hitachi, Ltd.Method of manufacturing semiconductor deviceUS5246881Apr 14, 1993Sep 21, 1993Micron Semiconductor, Inc.Low-pressure chemical vapor deposition process for depositing high-density, highly-conformal, titanium nitride films of low bulk resistivityUS5279857Aug 16, 1991Jan 18, 1994Materials Research CorporationProcess for forming low resistivity titanium nitride filmsUS5287205Mar 25, 1992Feb 15, 1994Semiconductor Energy Laboratory Co., Ltd.Gradation method for driving liquid crystal device with ramp and select signalUS5308655Feb 10, 1992May 3, 1994Materials Research CorporationProcessing for forming low resistivity titanium nitride filmsUS5356673Mar 18, 1991Oct 18, 1994Jet Process CorporationEvaporation system and method for gas jet deposition of thin film materialsUS5356821Aug 12, 1993Oct 18, 1994Kabushiki Kaisha ToshibaMethod for manufacturing semiconductor integrated circuit deviceUS5389398Jan 14, 1994Feb 14, 1995Hoya CorporationMethod of manufacturing magnetic recording medium for contact recordingUS5389570Aug 18, 1992Feb 14, 1995Kabushiki Kaisha ToshibaMethod of forming boron doped silicon layer and semiconductorUS5453858Feb 3, 1995Sep 26, 1995Semiconductor Energy Laboratory Co., Ltd.Electro-optical device constructed with thin film transistorsUS5471330Jul 29, 1993Nov 28, 1995Honeywell Inc.Polysilicon pixel electrodeUS5607724Apr 28, 1995Mar 4, 1997Applied Materials, Inc.Low temperature high pressure silicon deposition methodUS5614257May 18, 1995Mar 25, 1997Applied Materials, IncLow temperature, high pressure silicon deposition methodUS5648293Jul 22, 1994Jul 15, 1997Nec CorporationMethod of growing an amorphous silicon filmUS5656531Dec 15, 1995Aug 12, 1997Micron Technology, Inc.Method to form hemi-spherical grain (HSG) silicon from amorphous siliconUS5672385Mar 6, 1996Sep 30, 1997Anelva CorporationTitanium nitride film-MOCVD method incorporating use of tetrakisdialkylaminotitanium as a source gasUS5695819May 2, 1996Dec 9, 1997Applied Materials, Inc.Method of enhancing step coverage of polysilicon depositsUS5698771Mar 30, 1995Dec 16, 1997The United States Of America As Represented By The United States National Aeronautics And Space AdministrationVarying potential silicon carbide gas sensorUS5700520Jun 19, 1996Dec 23, 1997Applied Materials, Inc.Low temperature, high pressure silicon deposition methodUS5723382Jul 31, 1995Mar 3, 1998Sandhu; Gurtej S.Method of making a low-resistance contact to silicon having a titanium silicide interface, an amorphous titanium nitride barrier layer and a conductive plugUS5741330Jun 7, 1995Apr 21, 1998Baxter International, Inc.Close vascularization implant materialUS5769950May 25, 1995Jun 23, 1998Canon Kabushiki KaishaDevice for forming deposited filmUS5786027Jul 7, 1997Jul 28, 1998Micron Technology, Inc.Method for depositing polysilicon with discontinuous grain boundariesUS5789030Mar 18, 1996Aug 4, 1998Micron Technology, Inc.Method for depositing doped amorphous or polycrystalline silicon on a substrateUS5837580Apr 23, 1997Nov 17, 1998Micron Technology, Inc.Method to form hemi-spherical grain (HSG) siliconUS5849601Apr 22, 1994Dec 15, 1998Semiconductor Energy Laboratory Co., Ltd.Electro-optical device and method for manufacturing the sameUS5874129Dec 10, 1996Feb 23, 1999Applied Materials, Inc.Low temperature, high pressure silicon deposition methodUS5876797Oct 8, 1997Mar 2, 1999Applied Materials, Inc.Low temperature high pressure silicon deposition methodUS5885869Sep 14, 1995Mar 23, 1999Micron Technology, Inc.Method for uniformly doping hemispherical grain polycrystalline siliconUS5907792Aug 25, 1997May 25, 1999Motorola,Inc.Method of forming a silicon nitride layerUS5916365Aug 16, 1996Jun 29, 1999Sherman; ArthurSequential chemical vapor depositionUS5925188Oct 29, 1996Jul 20, 1999Tokyo Electron LimitedFilm forming apparatusUS5959326May 7, 1997Sep 28, 1999Nec CorporationCapacitor incorporated in semiconductor device having a lower electrode composed of multi-layers or of graded impurity concentrationUS5959327Dec 14, 1995Sep 28, 1999Micron Technology, Inc.Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming sameUS6015590Nov 28, 1995Jan 18, 2000Neste OyMethod for growing thin filmsUS6027705Nov 30, 1998Feb 22, 2000Showa Denko K.K.Method for producing a higher silaneUS6056823Mar 31, 1998May 2, 2000Applied Materials, Inc.Temperature controlled gas feedthroughUS6083810Dec 5, 1996Jul 4, 2000Lucent TechnologiesIntegrated circuit fabrication processUS6087229Mar 9, 1998Jul 11, 2000Lsi Logic CorporationComposite semiconductor gate dielectricsUS6103600Sep 24, 1998Aug 15, 2000Sharp Kabushiki KaishaMethod for forming ultrafine particles and/or ultrafine wire, and semiconductor device using ultrafine particles and/or ultrafine wire formed by the forming methodUS6136654Dec 4, 1997Oct 24, 2000Texas Instruments IncorporatedMethod of forming thin silicon nitride or silicon oxynitride gate dielectricsUS6136690Feb 13, 1998Oct 24, 2000Micron Technology, Inc.In situ plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applicationsUS6159828Dec 8, 1998Dec 12, 2000Micron Technology, Inc.Semiconductor processing method of providing a doped polysilicon layerUS6161498Jun 30, 1997Dec 19, 2000Tokyo Electron LimitedPlasma processing device and a method of plasma processUS6171662Dec 10, 1998Jan 9, 2001Mitsubishi Denki Kabushiki KaishaMethod of surface processingUS6180462Jun 7, 1999Jan 30, 2001United Microelectronics Corp.Method of fabricating an analog integrated circuit with ESD protectionUS6197669Apr 15, 1999Mar 6, 2001Taiwan Semicondcutor Manufacturing CompanyReduction of surface defects on amorphous silicon grown by a low-temperature, high pressure LPCVD processUS6197694Jul 31, 1996Mar 6, 2001Applied Materials, Inc.In situ method for cleaning silicon surface and forming layer thereon in same chamberUS6200893Mar 11, 1999Mar 13, 2001Genus, IncRadical-assisted sequential CVDUS6203613Oct 19, 1999Mar 20, 2001International Business Machines CorporationAtomic layer deposition with nitrate containing precursorsUS6228181Sep 28, 1998May 8, 2001Shigeo YamamotoMaking epitaxial semiconductor deviceUS6252295Jun 19, 2000Jun 26, 2001International Business Machines CorporationAdhesion of silicon carbide filmsUS6271054Jun 2, 2000Aug 7, 2001International Business Machines CorporationMethod for reducing dark current effects in a charge couple deviceUS6294399Jan 27, 2000Sep 25, 2001Sharp Kabushiki KaishaQuantum thin line producing method and semiconductor deviceUS6326311Mar 29, 1999Dec 4, 2001Sharp Kabushiki KaishaMicrostructure producing method capable of controlling growth position of minute particle or thin and semiconductor device employing the microstructureUS6348420Dec 23, 1999Feb 19, 2002Asm America, Inc.Situ dielectric stacksUS6373112Dec 2, 1999Apr 16, 2002Intel CorporationPolysilicon-germanium MOSFET gate electrodesUS6385020Jan 19, 2000May 7, 2002Samsung Electronics Co., Ltd.Methods of forming HSG capacitors from nonuniformly doped amorphous silicon layers and HSG capacitors formed therebyUS6390753Feb 23, 1998May 21, 2002Asm International N.V.System for loading, processing and unloading substrates arranged on a carrierUS6391803Jun 20, 2001May 21, 2002Samsung Electronics Co., Ltd.Method of forming silicon containing thin films by atomic layer deposition utilizing trisdimethylaminosilaneUS6455892Sep 15, 2000Sep 24, 2002Denso CorporationSilicon carbide semiconductor device and method for manufacturing the sameUS6468924May 31, 2001Oct 22, 2002Samsung Electronics Co., Ltd.Methods of forming thin films by atomic layer depositionUS6503846Jun 20, 2001Jan 7, 2003Texas Instruments IncorporatedTemperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gatesUS6524650Sep 22, 2000Feb 25, 2003Kokusai Electric Co., Ltd.Substrate processing apparatus and methodUS6528530Sep 18, 2001Mar 4, 2003Celgene CorporationPhenidate drug formulations having diminished abuse potentialUS6537910Oct 27, 2000Mar 25, 2003Micron Technology, Inc.Forming metal silicide resistant to subsequent thermal processingUS6551893Nov 27, 2001Apr 22, 2003Micron Technology, Inc.Atomic layer deposition of capacitor dielectricUS6573184Mar 7, 2002Jun 3, 2003Ips, Ltd.Apparatus and method for depositing thin film on wafer using atomic layer depositionUS6585823Jul 7, 2000Jul 1, 2003Asm International, N.V.Atomic layer depositionUS6593219Jul 30, 2001Jul 15, 2003Matsushita Electric Industrial Co., Ltd.Method for fabricating electrode structure and method for fabricating semiconductor deviceUS6613695Aug 31, 2001Sep 2, 2003Asm America, Inc.Surface preparation prior to depositionUS6638879Dec 6, 2001Oct 28, 2003Macronix International Co., Ltd.Method for forming nitride spacer by using atomic layer depositionUS20020176939 *May 2, 2002Nov 28, 2002Applied Materials, Inc.Method of improving the adhesion of copperUS20050205942 *Mar 19, 2004Sep 22, 2005Shian-Jyh LinMetal gate with composite film stack* Cited by examinerNon-Patent CitationsReference1European Search Report for counterpart EP Application No. 05011705.2Hillman et al., "Properties of LPCVD TiN Barrier Layers," Microelectronic Engineering 19 (1992) 375-378.3Hiltunen et al., "Nitrides of Titanium, Niobium, Tantalum and Molybdenum Grown as Thin Films by the Atomic Layer Epitaxy Method," Thin Solid Films, 166 (1988) 149-154.4Hiramatsu et al., Formation of TiN Films with Low Cl Concentration by Pulsed Plasma Chemical Vapor Deposition, J. Vac. Sci. Technol. A, 14(3) May/Jun. 1996.5Ikoma et al., Growth of Si/3C-SiC/Si(100) hetrostructures by pulsed supersonic free jets, Applied Physics Letters, vol. 75, No. 25, pp. 3977-3979, Dec. 1999.6International Search Report dated May 8, 2007 for international patent application No. PCT/US2006/047805.7International Search Report dated Nov. 13, 2003 for international patent application No. PCT/US02/02921, filed on Feb. 1, 2002.8Office Action of Aug. 21, 2008 in U.S. Appl. No. 11/843,552, filed Aug. 22, 2007.9Pintchovski et al., "LPCVD titanium nitride-deposition, properties, and application to ULSI", Tungsten and Other Refractory Metal for ULSI Application, No. IV, pp. 275-282, (1989).10Ramanuja, et al., "Synthesis and characterization of low pressure chemically vapor deposited titanium nitride films using TiCl4 and NH3," Materials Letters 57 (2002) 261-269.11Sze, VLSI Technology, "Arrhenius plot for polysilicon deposition for different silane partial pressures," (1988) pp. 240-241.12Travis et al., "A scalable submicron contact technology using conformal LPCVD TiN", ilDEM Conference Proceedings, Dec. 1990.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8394201 *Jan 21, 2009Mar 12, 2013Samsung Electronics Co., Ltd.Atomic layer deposition apparatusUS8461062 *Dec 20, 2011Jun 11, 2013Hitachi Kokusai Electric Inc.Substrate processing apparatus and method for manufacturing semiconductor deviceUS8546270 *Feb 28, 2013Oct 1, 2013Samsung Electronics Co., Ltd.Atomic layer deposition apparatusUS8828141 *Feb 20, 2009Sep 9, 2014Hitachi Kokusai Electric Inc.Substrate processing apparatus and method for manufacturing semiconductor deviceUS20090191717 *Jan 21, 2009Jul 30, 2009Ki-Hyun KimAtomic layer deposition apparatusUS20090223448 *Feb 20, 2009Sep 10, 2009Hitachi Kokusai Electric Inc.Substrate processing apparatus and method for manufacturing semiconductor deviceUS20120122318 *Dec 20, 2011May 17, 2012Hitachi Kokusai Electric Inc.Substrate processing apparatus and method for manufacturing semiconductor device* Cited by examinerClassifications U.S. Classification438/680, 257/E21.101International ClassificationH01L21/44Cooperative ClassificationC23C16/34, C23C16/45525, C23C16/45578European ClassificationC23C16/34, C23C16/455F2, C23C16/455K14Legal EventsDateCodeEventDescriptionJun 19, 2007ASAssignmentOwner name: ASM INTERNATIONAL N.V., NETHERLANDSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HASPER, ALBERT;REEL/FRAME:019452/0750Effective date: 20070610Mar 8, 2013FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services