Source: https://patents.google.com/patent/US8631203
Timestamp: 2018-04-21 19:28:58
Document Index: 316351432

Matched Legal Cases: ['Application No. 2', 'Application No. 200680047384', 'Application No. 200510083792', 'Application No. 200510116208', 'Application No. 200980136912', 'Application No. 200980137190', 'Application No. 200980145878', 'Application No. 200980137190', 'Application No. 200680047384', 'Application No. 200510083792', 'Application No. 03022573', 'Application No. 03022573', 'Application No. 03022573', 'Application No. 05103690', 'Application No. 05103697', 'Application No. 05103697', 'Application No. 05103697', 'Application No. 05103697', 'Application No. 05109295', 'Application No. 09813565', 'Application No. 09814983', 'Application No. 09826570', 'Application No. 09826570', 'Application No. 05109295', 'Application No. 05109295', 'Application No. 05109295', 'Application No. 06839426', 'Application No. 09813565', 'Application No. 191502', 'Application No. 2008', 'Application No. 2008', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2005', 'Application No. 2011', 'Application No. 2012', 'Application No. 2003129662', 'Application No. 094114140']

US8631203B2 - Management of external memory functioning as virtual cache - Google Patents
Management of external memory functioning as virtual cache Download PDF
US8631203B2
US8631203B2 US11953312 US95331207A US8631203B2 US 8631203 B2 US8631203 B2 US 8631203B2 US 11953312 US11953312 US 11953312 US 95331207 A US95331207 A US 95331207A US 8631203 B2 US8631203 B2 US 8631203B2
US11953312
US20090150611A1 (en )
A method and apparatus for managing the caching of data on an auxiliary memory of a computer. Pages of data may be cached on an auxiliary memory, such as a flash memory, at a virtual level using an identifier that does not involve a physical address of the pages on a memory. Pages may be cached on auxiliary memory that may be removable from the computer, e.g., by unplugging the memory from the computer. Page data may be encrypted and/or compressed on the auxiliary memory. An authentication indicator may be used to verify the accuracy of cached data in the case of an interrupted connection to the auxiliary memory, e.g., as a result of computer power down, hibernation, removal of the memory from the computer, etc.
This invention relates to managing the use of auxiliary memory devices as cache memory.
Improvements to central processing unit (CPU) hardware have, in general, far outpaced advances made in disk drive memory in terms of speed of operation. As a result, a common bottleneck to improved computer performance has been the time needed to retrieve data from disk drive memory for use by the CPU. To help alleviate this problem, computer systems are commonly operated so as to store (or cache) data needed by the CPU in main system memory, e.g., RAM that is typically located on the computer motherboard and has relatively fast read/write times, especially as compared to magnetic disk memory. Thus, needed data can be moved from a disk drive to the main system memory (preferably before the data is needed by the CPU), helping to speed the computer's operation.
The inventors have appreciated that the use of auxiliary memory, e.g., memories that may or may not be located on the motherboard, in a computer system as cache memory can improve a computer system's performance, particularly if the auxiliary memory read/write time is faster than the memory(ies) on which most of the system's data is stored (often a disk drive or drives). With the more widespread use of flash memory (e.g., in the form of USB memory sticks or other similar devices), a computer system often has access to memory that operates at a faster rate than a disk drive typically employed to store the bulk of a computer's data. If such auxiliary memory has usable space, the memory can help to speed computer function by caching data from slower memories.
In accordance with an aspect of the invention, auxiliary memories that are removable from the computer system may be effectively used as cache memory. (As used herein, removable means that the memory can be ejected or otherwise disconnected from the computer without causing the computer to crash.) For example, the computer system may use a USB flash memory that a user has plugged into a USB port to cache data for use by the CPU. Management of the cached data may be performed so that even in the event that the auxiliary memory is disconnected or otherwise removed from the system, no loss of data will occur. In one embodiment, only so-called “clean” pages, e.g., blocks of data about 4 kB in size that are not subject to modification, are cached on removable and/or non-removable auxiliary memory. Thus, clean pages may have a backup on another memory, such as an internal disk drive, so that removal of the memory will not cause loss of data. Other pages that may be modified, so-called “dirty” pages, may be cached only on non-removable memory, or may also be stored on removable memory if the system is suitably equipped (e.g., has the ability to ask the user to reconnect a removable memory to the computer if the user wants the system/process to continue running or other ability to recover from the loss of the “dirty” page data).
In another aspect of the invention, the computer system may cache virtual pages on an auxiliary memory or memories. In typical caching techniques, the system caches data at a physical level, i.e., blocks of data identified by physical address in a memory (such as a disk drive) are stored on a second memory (such as a cache memory). The inventors have appreciated that this approach may have disadvantages, including inefficient use of cache memory space. For example, a particular process may only require a relatively small portion of a data block, but the memory manager will typically continue to cache the entire block despite the fact that most of the block will not be used. As another example, if a disk drive is defragmented (which essentially involves the physical rearrangement of data on a disk to free up disk space), a complicated scheme is required to relay to the cache management regarding where data to be cached has been moved on the disk so that appropriate data can be cached.
In one aspect of the invention, data may be cached on a virtual level, e.g., in a way that does not identify a cached page by its physical address on memory device, but rather by a virtual identifier that describes the identity of the cached page at a more abstract level. For example, pages may be virtually identified by a page key that includes a tuple of a process employing the page and a virtual address for the page, or a name or handle of a file that includes the page and a file offset. Other virtual page identifiers may be used as suitable. By identifying a page at a virtual level as opposed to a physical level, more efficient caching may be performed since only those pages expected to be used by the CPU need be cached, potentially avoiding the caching of data that is unlikely to be used. Also, since a process may clearly identify which page(s) are released, e.g., by file or process, the cache management system may rapidly release the corresponding data from the cache.
In another aspect of the invention, data may be cached in one or more auxiliary memories that are removable from the computer system. Such auxiliary memories may include any suitable memory type, such as flash memory, disk drive memory, etc., and may be removable from the computer system by physically disconnecting the memory from the computer system while the computer system continues to otherwise operate normally (e.g., by unplugging a flash memory stick from a computer) and/or by disabling a connection between the computer system and the auxiliary memory (e.g., by disabling a local area network connection via which the computer system communicates with an auxiliary memory). Data may be cached on the auxiliary memory in any suitable way, such as by virtual address as discussed above, and/or by physical address. In accordance with an aspect of the invention, the accuracy of data cached on a removable auxiliary memory may be verified if the auxiliary memory is disconnected from the computer system, and then reconnected.
In one aspect of the invention, a computer system includes a processor adapted to execute instructions to carry out one or more functions, and a main system memory adapted to store a plurality of pages of data that are used by the processor in performing the one or more functions. At least one auxiliary memory may be in communication with the processor and be adapted to store a plurality of pages of data for use by the processor, by the processor directly accessing the auxiliary memory and/or indirectly accessing the auxiliary memory by transferring data to be used by the processor from the auxiliary memory to main system memory. A cache manager (e.g., which may be part of a memory manager in the computer operating system) may control the caching of virtual pages of data for use by the processor on the auxiliary memory and may identify virtual pages using a virtual identifier that is not an address that defines a physical location of the virtual page on a memory. In one embodiment, virtual identifier includes a tuple of file and offset information, or a tuple of process and virtual address information. The auxiliary memory may be removable from the computer, and caching of pages may be managed so that loss of data due to removal of the memory is avoided.
In another aspect of the invention, a method of managing virtual pages cached in auxiliary memory of a computer system includes providing a computer system including a processor adapted to execute instructions to carry out one or more functions, a main system memory adapted to store a plurality of pages of data that are used by the processor in performing the one or more functions, and an auxiliary memory in (direct or indirect) communication with the processor. Virtual pages of data may be cached for use by the processor on the auxiliary memory, and the auxiliary memory may be disconnected from the computer system. In one embodiment, the auxiliary memory may be disconnected from the computer system without loss of the cached data.
In another aspect of the invention, a method of managing pages cached in memory of a computer system includes providing a computer system having a processor adapted to execute instructions to carry out one or more functions, main system memory adapted to store a plurality of pages of data that are used by the processor in performing the one or more functions, and an auxiliary memory in communication with the processor. The auxiliary memory may be adapted to store a plurality of pages of data for use by the processor and be removable from the computer system. Pages of data may be cached for use by the processor on the auxiliary memory, and the auxiliary memory disconnected from the computer system. The auxiliary memory may be reconnected to the computer system, and pages cached on the auxiliary memory may be verified to be consistent with corresponding page data stored in another memory of the computer system.
FIG. 1 shows a schematic block diagram of a computer arranged in accordance with aspects of the invention; and
FIG. 2 conceptually illustrates an example of managing virtual cache pages in one embodiment.
Aspects of the invention are described below with reference to illustrative embodiments. However, it should be appreciated that aspects of the invention are not limited to any of the particular embodiments. For example, embodiments are described below regarding a general purpose programmable computer with one or more auxiliary memories. However, it should be appreciated that aspects of the invention may be employed in any suitable environment, such as where auxiliary memory used as cache memory are linked by a network connection to the computer.
FIG. 1 shows a schematic block diagram of a computer 10 that is arranged in accordance with aspects of the invention. Although in this illustrative embodiment, only selected portions of the computer 10 are identified as being included in the computer 10, this is done for purposes of clarity and not to limit aspects of the invention in any way. For example, the computer 10 may include a display, a keyboard and/or other user input devices (such as a mouse, touch screen or other), communications devices (such as devices suitable for wireless and/or wired communications), as well as any suitable software or other instructions that may be executed by the computer 10 so as perform desired input/output or other functions.
In this illustrative embodiment, the computer 10 includes a central processing unit (CPU or processor) 1 and main system memory 2 that the processor 1 uses for performing its functions. The main system memory 2 may be located on a motherboard with the processor 1 and may have a relatively high read and/or write speed so that data exchanges with the processor 1 can be performed rapidly, e.g., may include RAM that the processor 1 uses to cache data for use in performing various operations. The computer 10 may also include one or more auxiliary memory devices 3, e.g., memories 3 that are not part of the main system memory and may or may not be located on a motherboard with the processor 1. Although the auxiliary memory devices 3 may function as cache memory in accordance with aspects of the invention, these devices 3 are not limited to functioning as a conventional cache memory. For example, the computer 10 may include as auxiliary memory 3 one or more disk drives 3 a where a majority of data used by the computer 10 is stored, an optical memory 3 b, and a flash memory device 3 c. Other auxiliary memory may be provided, such as volatile or non-volatile RAM of any suitable form. Some of the memories 3 may be located within an outer casing of the computer 10, such as the disk drive 3 a and the optical memory 3 b, whereas others, such as the flash memory 3 c may be located outside of the outer casing of the computer 10. Also, some of the memories, such as the disk drive 3 a and the optical memory 3 b, may not be removable from the computer 10, whereas other of the auxiliary memory, such as the flash memory device 3 c, may be removable (e.g., by unplugging the flash memory 3 c at a USB port, PCMCIA connection, a memory card reader or other connection to the computer 10). In some embodiments, auxiliary memory 3 may be provided via a network connection to the computer 10 (e.g., by a network server and/or client on the network), and in such cases the auxiliary memory 3 may be removable from the computer 10, i.e., can be physically disconnected from the computer and/or communication with the memory 3 can be disabled.
In accordance with one aspect of the invention, the computer 10 may store cache data on a removable auxiliary memory 3, such as the flash memory 3 c. For example, a memory manager 4, which may be part of the operating system for the computer 10, may direct data to be used by the processor 1 that is located on the disk drive 3 a to be cached on the flash memory 3 c. The faster read and/or write time of the flash memory 3 c as compared to the disk drive 3 a may help to speed operation of the computer 10 and/or applications executed by the computer 10 (e.g., by reducing operation time perceived by a user), particularly if the main system memory 2 is full or otherwise cannot be used in an efficient way. The memory manager 4 may operate so that pages that are “in use”, i.e., pages that can be modified by an application without operating system intervention, are cached only at the main system memory 2. However, other data may be cached on the auxiliary memory 3. The memory manager 4 may also operate so that only “clean” pages are cached on removable auxiliary memory 3. That is, only pages that are not modified or will not be modified whether by operating system intervention or not are stored on removable auxiliary memory 3. In this way, if the auxiliary memory 3 is removed, the memory manager 4 may resort to the copy of the page on the disk drive 3 a or other memory. As for “dirty” pages, i.e., pages that may be or are modified, the memory manager 4 may cache such pages only on non-removable auxiliary memory 3 (or, of course, main system memory 2). In this way, the computer 10 will not lose modified pages due to removal of the auxiliary memory 3.
In accordance with another aspect of the invention, cached pages stored on removable (or non-removable) auxiliary memory 3 may be encrypted. This approach may help to ensure privacy of cached information (such as credit card numbers, bank accounts, passwords, etc.) that is stored on removable auxiliary memory 3, e.g., in case that sensitive information is cached on a removable memory 3 and the memory 3 is removed, taking the sensitive data with it. By encrypting the cached data, it may be difficult or impossible to recover the information from the removable memory 3 without the necessary encryption key or other information needed to recover the encrypted data. One possible way to encrypt cached pages is to generate a random key and encrypt the page(s) using the key and a suitable encryption algorithm. In another example, the key may be salted based on the specific device offset the page is being written to.
In another aspect of the invention, cached pages on auxiliary memory 3 may be compressed. For example, compression ratios of approximately 2:1 or 3:1, depending on the type of data or other factors may be possible, thereby reducing the amount of space needed to cache data. Cached pages that originate from a file, termed “file pages” herein, may experience a compression ratio of 2:1. Cached pages that cannot be shared and that originate from the virtual address space of a process, termed “private pages” herein, may experience a 3:1 compression ratio. As with all other aspects of the invention which may be combined with other aspects in any suitable way, compression of cached pages may be combined with encryption. In fact, in some embodiments, encryption of the cached data may result in compression of the data as well as encryption.
In another aspect of the invention, bytes of data on auxiliary memory 3 may be shared by multiple cached pages. For example, multiple pages containing the same data can be stored in the same location on the auxiliary memory 3 to further optimize space usage.
In another aspect of the invention, a data authenticity indicator may be generated and used to verify that a cached page (or pages) on an auxiliary memory remains unchanged after communication between the computer system and the auxiliary memory is interrupted (e.g., the auxiliary memory has been “removed” from the computer system). Communication with the auxiliary memory 3 may be interrupted in a variety of ways, such as by the computer 10 powering down, crashing, experiencing a power failure, hibernating, etc., a network connection being cut and/or the auxiliary memory 3 being removed from the computer 10. In such cases, the memory manager 4 cannot be assured that the cached data on the auxiliary memory 3 (or data on the source memory from which the cached data was obtained) has not been maliciously changed or otherwise modified without making some kind of verification. In one embodiment, a hash of cached data (or other cryptographic authenticity indicator for the data) on the auxiliary memory 3 may be generated, e.g., after each write of cached data to the auxiliary memory 3, and used in the case of communication interruption to verify that the cached data on the auxiliary memory 3 after reconnection to the computer 10 remains unchanged from before the communication interruption and/or to verify that cached data at the source memory (such as a disk drive) has not changed. The hash may be determined for each page, for each region of the auxiliary memory 3 and/or the entire memory 3. Before entering a sleep state, each memory 3 and/or the memory manager 4 may mark all of the regions of the memory 3 having cached data so that those regions can be hash-verified after the sleep state is terminated. It may be important to ensure that the hash algorithm is cryptographically strong so that one can be reasonably certain that a hash match provides a suitable guarantee that there has been no alteration of data. In another embodiment, the memory manager 4 may maintain a list of changes to data on a source memory so that the memory manager 4 can determine whether there are any differences between the data on the source memory and corresponding cached data on the auxiliary memory 3, and if so, either discard the cached data or update the data so the cached data reflects changes that have occurred. Of course, it will be understood that another technique that may be used to determine differences between cached data on a removed auxiliary memory 3 and data on a source memory is a comparison of the relevant data to determine whether any differences exist. If differences exist, the cached data may be updated using data from the source memory, the source data may be restored (in the case that the cached data on the removed auxiliary memory 3 is determined to be an appropriate data set for use), or the cached data may be discarded.
In another aspect of the invention, data cached on an auxiliary memory may be cached at a virtual level. For example, the memory manager 4 may identify cached pages by a page key that does not include a physical address for the page on a memory and does not include a physical address for a larger block of data on a memory that includes the page. In one embodiment, pages may be identified by a tuple of the page's file identifier and file offset (e.g., for pages originating from a file) or a tuple of a process using the page and the page's virtual address within the process (e.g., for pages originating from a process). The memory manager 4, which may control the caching of data in a main system memory, may include a cache manager 41 that manages the caching of virtual pages on one or more auxiliary memories 3. (Alternately, the cache manager 41 may be a separate component from the memory manager 4 that interacts with the memory manager 4.) In this embodiment, communication between the memory manager 4 and the cache manager 41 uses page keys to identify pages, and pages may be organized in auxiliary memories 3 in respective stores (i.e., an organizational arrangement for pages and information regarding pages). A policy manager (which may or may not be part of the memory manager 4) may make the decisions regarding which pages are placed in stores 31 on auxiliary memories 3 and when. These decisions may be made based on various factors, including store location, store read/write speed, store size, store removability, page identity, page access history, page compressibility, and others. For example, if the memory manager 4 and/or policy manager determines that caching a set of pages on an auxiliary memory 3 having a read/write speed greater than a disk memory would improve performance of the system, the memory manager 4 may direct the pages expected to be used by the processor 1 be copied to the auxiliary memory 3. In one embodiment shown schematically in FIG. 2, when a page is added to a store 31, the memory manager 4 gives the cache manager 41 the page, its key and optionally a set of stores 31 to which the page is to be added. The cache manager 41 may organize stores 31 in an auxiliary memory 3 into regions, which may have a size of about 32 kB to 1 MB when using a 4 kB-8 kB page size. The cache manager 41 (or alternately a store 31) may maintain information regarding the location of each page in each store 31, e.g., expressed as the tuple of a region number and the region offset in the auxiliary memory 3. This information may be stored in a lookup data structure 32, called a PageMap, which may take the form of a B+tree or hash table. The PageMap 32 may include an entry for each page in the store 31, and be searchable by the associated Page key. As can be seen in FIG. 2, the entry for each page may include the Page key tuple (e.g., file/offset or process/virtual address) as well as the location information (e.g., store bitmap) and one or more flags (e.g., priority information, CRC information, etc.).
When retrieving a page from a store 31 (e.g., so that an application can use the page) or removing a page from a store 31, the memory manager 4 provides the page key to the cache manager 41. In response, the cache manager 41 may search the PageMap 32 for the corresponding Page keys, identify the store(s) 31 and location(s) for the page, and provide the page to the memory manager 4. A retrieved page may be placed in main system by the memory manager 4, e.g., so that an application can access the page. If the page is not present, e.g., because an auxiliary memory 3 having the cached page has been removed, the cache manager 41 may indicate a failed operation to the memory manager 4. The memory manager 4 may then resort to other copies of the page. Modified pages or pages that are to be modified generally are removed from stores 31 on auxiliary memory 3 because those copies on the stores 31 will become out of date. The cache manager 41 may remove pages from a store 31 without any input/output being required with the respective auxiliary memory 3, e.g., by updating the PageMap 32. With this arrangement, the memory manager 4 may maintain a relatively small amount of information regarding pages, e.g., the page key and a “present bit” which indicates whether a page is present in a store or not, since the cache manager 41 may maintain sufficient information regarding page location, etc.
Aspects, including embodiments described above, can be implemented in any of numerous ways. For example, the embodiments may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers. It should be appreciated that any component or collection of components that perform the functions described above can be generically considered as one or more controllers that control the above-discussed functions. The one or more controllers can be implemented in numerous ways, such as with dedicated hardware, or with general purpose hardware (e.g., one or more processors) that is programmed using microcode or software to perform the functions recited above.
a main system memory configured for storing a plurality of pages of data;
at least one auxiliary memory configured for storing the plurality of pages of data and for being removable from the computing device; and
a memory manager configured for controlling the caching of virtual pages of data on the at least one auxiliary memory, the memory manager further configured for identifying a virtual page of the virtual pages using a page key comprising a tuple, the page key configured for identifying the virtual page as cached in a file based on the tuple comprising the virtual page's file identifier and its file offset information, and further configured for identifying the virtual page as employed by a process based on the tuple comprising the virtual page's process identifier and its virtual address within the process, the memory manager further configured for verifying that virtual pages of data cached on the auxiliary memory are consistent with pages of data stored in the main system memory after the auxiliary memory is removed from the computing device and reconnected to the computing device, where the verifying is based on an analysis of non-time stamp virtual page data on the auxiliary memory.
2. The computing device computer system of claim 1, wherein the tuple of the page key comprises the virtual page's originating file identifier and its originating file offset information corresponding to the virtual page being cached in the file, and wherein the tuple of the page key comprises the virtual page's process identifier and its virtual address within the process corresponding to the virtual page being employed by the process.
3. The computing device of claim 1, wherein the at least one auxiliary memory is removable from the computer system without loss of data corresponding to the virtual pages stored on the at least one auxiliary memory.
4. The computing device of claim 3, wherein the at least one auxiliary memory includes a plurality of memories.
5. The computing device of claim 1, wherein virtual pages stored on the removable at least one auxiliary memory are encrypted.
6. The computing device of claim 1, wherein dirty virtual pages are stored on non-removable auxiliary memories, and clean virtual pages are stored on removable or non-removable auxiliary memories.
7. The computing device of claim 1, wherein the virtual pages are stored in compressed form on the at least one auxiliary memory.
8. The computing device of claim 1, wherein a virtual data authenticity indicator is used by the memory manager to verify that a virtual page on an auxiliary memory remains unchanged after communication between the computer system and the auxiliary memory is interrupted.
9. The computing device of claim 8, wherein the virtual data authenticity indicator includes a hash of the virtual page, and interruption of communication between the computing device and the auxiliary memory is caused by power down of the computing device or removal of the auxiliary memory from the computing device.
10. A method performed on a computing device for managing virtual pages cached in auxiliary memory, the method comprising:
providing a main system memory configured for storing a plurality of pages of data, and the auxiliary memory configured for storing the plurality of pages of data and for being removable from the computing device;
caching virtual pages of data on the auxiliary memory, a virtual page of the virtual pages being identified by a page key comprising a tuple, the page key configured for identifying the virtual page as cached in a file based on the tuple comprising the virtual page's file identifier and its file offset information, and further configured for identifying the virtual page as employed by a process based on the tuple comprising virtual page's process identifier and its virtual address within the process;
disconnecting the auxiliary memory from the computing device;
reconnecting the auxiliary memory to the computing device; and
verifying that virtual pages cached on the auxiliary memory are consistent with corresponding page data stored in the main system memory, the verifying performed after reconnecting the auxiliary memory to the computing device and based on an analysis of non-time stamp cached virtual page data on the auxiliary memory.
11. The method of claim 10, further comprising caching other virtual pages of data on the auxiliary memory, the virtual pages being identified by a page key that includes a tuple of process and virtual address information.
12. The method of claim 11, further comprising generating a virtual data authenticity indicator used to verify that a virtual page on an auxiliary memory remains unchanged after communication between the computing device and the auxiliary memory is interrupted.
13. The method of claim 10, wherein the disconnecting and the reconnecting are performed without loss of data corresponding to the virtual pages stored on the at least one auxiliary memory.
14. The method of claim 10, wherein virtual pages stored on the auxiliary memory are encrypted.
15. The method of claim 10, wherein the step of caching virtual pages includes:
caching dirty virtual pages on non-removable auxiliary memory, and
caching clean virtual pages on removable auxiliary memory.
16. The method of claim 10, wherein the virtual pages are stored in compressed form on the auxiliary memory.
first identifying, in response to the virtual page being cached in the file, the virtual page using the page key based on the tuple of the page key comprising the virtual page's originating file identifier and its originating file offset information; or
second identifying, in response to the virtual page being employed by the process, the virtual page using the page key based on the tuple of the page key comprising the virtual page's process identifier and its virtual address within the process.
18. A method performed on a computing device for managing pages cached in memory, the method comprising:
providing a main system memory configured for storing a plurality of pages of data, and an auxiliary memory configured for storing the plurality of pages of data and for being removable from the computer system;
caching virtual pages of data on the auxiliary memory, a virtual page of the virtual pages being identified by a page key comprising a tuple, the page key configured for identifying the virtual page as cached in a file based on the tuple comprising the virtual page's file identifier and file offset information, and further configured for identifying the virtual page as employed by a process based on the tuple comprising the virtual page's process identifier and its virtual address within the process.
reconnecting the auxiliary memory to computing device to speed computing device operations; and
verifying that pages cached on the auxiliary memory are consistent with corresponding page data stored in another memory of the computer system, the verifying performed after reconnecting the auxiliary memory to the computer system and based on an analysis of non-time stamp cached page data on the auxiliary memory, wherein the verifying includes:
comparing data cached on the auxiliary memory with the corresponding data stored on the source memory of the computer system from which the data was cached; or
assessing whether an authenticity indicator for the data cached on the auxiliary memory indicates a change in the data; or
determining whether changes to the data cached on the auxiliary memory have occurred based on a list of changes maintained for the auxiliary memory.
first identifying, in response to the virtual page being cached in the file, the virtual page using the page key based on the tuple of the page key comprising the virtual page's originating file identifier and its originating file offset information; and
US11953312 2007-12-10 2007-12-10 Management of external memory functioning as virtual cache Active 2028-09-25 US8631203B2 (en)
US11953312 US8631203B2 (en) 2007-12-10 2007-12-10 Management of external memory functioning as virtual cache
US14076576 US20140075126A1 (en) 2007-12-10 2013-11-11 Management of external memory functioning as virtual cache
US14076576 Continuation US20140075126A1 (en) 2007-12-10 2013-11-11 Management of external memory functioning as virtual cache
US20090150611A1 true US20090150611A1 (en) 2009-06-11
US8631203B2 true US8631203B2 (en) 2014-01-14
ID=40722856
US11953312 Active 2028-09-25 US8631203B2 (en) 2007-12-10 2007-12-10 Management of external memory functioning as virtual cache
US14076576 Abandoned US20140075126A1 (en) 2007-12-10 2013-11-11 Management of external memory functioning as virtual cache
US (2) US8631203B2 (en)
JP2012221333A (en) * 2011-04-12 2012-11-12 Sony Corp Memory management device, memory management method and control program
KR20150120557A (en) * 2014-04-17 2015-10-28 에스케이하이닉스 주식회사 Electronic device including semiconductor memory and operation method of the same
US20160283390A1 (en) * 2015-03-27 2016-09-29 Intel Corporation Storage cache performance by using compressibility of the data as a criteria for cache insertion
EP0547992A2 (en) 1991-12-17 1993-06-23 International Business Machines Corporation Method and system for enhanced efficiency of data recovery in balanced tree memory structures
EP0744697A1 (en) 1995-05-22 1996-11-27 Symbios Logic Inc. Method and apparatus for transferring data between computer devices
US5923838A (en) 1996-12-17 1999-07-13 Mitsubishi Denki Kabushiki Kaisha Microcomputer with built-in flash memory
US20010007123A1 (en) 2000-01-02 2001-07-05 Nobuyuki Seguchi Stored program controlled switching system
US6301635B2 (en) 1996-09-30 2001-10-09 Nokia Mobile Phones Limited Memory device
US20020083275A1 (en) 2000-12-25 2002-06-27 Shinichi Kawamoto Cache coherent control system
EP0712067B1 (en) 1994-11-09 2002-07-31 Mitsubishi Denki Kabushiki Kaisha Flash disk card
US20020108017A1 (en) 2001-02-05 2002-08-08 International Business Machines Corporation System and method for a log-based non-volatile write cache in a storage controller
US20030074550A1 (en) 2001-10-16 2003-04-17 Wilks Andrew W. Method for allowing CD removal when booting embedded OS from a CD-ROM device
US20030202377A1 (en) 1989-04-13 2003-10-30 Eliyahou Harari Flash EEprom system
US20040010639A1 (en) 1991-12-06 2004-01-15 Hitachi, Ltd. External storage subsystem
US20040019762A1 (en) * 2002-07-25 2004-01-29 Hitachi, Ltd. Semiconductor integrated circuit
US6721863B1 (en) 2000-02-29 2004-04-13 Kabushiki Kaisha Toshiba Disk control mechanism preferable for random disk write
US20040136259A1 (en) 2002-09-10 2004-07-15 Nokia Corporation Memory structure, a system, and an electronic device, as well as a method in connection with a memory circuit
US20050005188A1 (en) 2003-06-20 2005-01-06 International Business Machines Corporation Preserving cache data against cluster reboot
US20050138283A1 (en) 2003-12-18 2005-06-23 Garney John I. Writing cache lines on a disk drive
US6930919B2 (en) 2003-02-26 2005-08-16 Samsung Electronics Co., Ltd. NAND-type flash memory device having array of status cells for storing block erase/program information
US20060112195A1 (en) 2004-11-19 2006-05-25 Canon Kabushiki Kaisha Electronic device and control method therefor
US7082499B2 (en) 2001-10-03 2006-07-25 Sharp Kabushiki Kaisha External memory control device regularly reading ahead data from external memory for storage in cache memory, and data driven type information processing apparatus including the same
US20060177067A1 (en) 2005-02-03 2006-08-10 Samsung Electronics Co., Ltd. Hybrid broadcast encryption method
US20060236034A1 (en) 2005-04-19 2006-10-19 Pomaranski Ken G External state cache for computer processor
US20070005882A1 (en) 2005-06-15 2007-01-04 Gallagher William J System and method for scheduling disk writes in an application server or transactional environment
US20070011405A1 (en) 2005-07-11 2007-01-11 Adusumilli Vijay P High-speed interface for high-density flash with two levels of pipelined cache
US20070156954A1 (en) 2005-12-29 2007-07-05 Intel Corporation Method and apparatus to maintain data integrity in disk cache memory during and after periods of cache inaccessiblity
US20070162700A1 (en) 2005-12-16 2007-07-12 Microsoft Corporation Optimizing write and wear performance for a memory
US20080010415A1 (en) 2006-07-05 2008-01-10 International Business Machines Corporation A pseudo lru tree-based priority cache
US20080010401A1 (en) 2003-06-27 2008-01-10 Intel Corporation Cache write integrity logging
US7412562B2 (en) 2002-11-04 2008-08-12 Intel Corporation Using non-volatile memories for disk caching of partition table entries
US20090150611A1 (en) 2007-12-10 2009-06-11 Microsoft Corporation Management of external memory functioning as virtual cache
US20100070701A1 (en) 2008-09-15 2010-03-18 Microsoft Corporation Managing cache data and metadata
US20100070747A1 (en) 2008-09-15 2010-03-18 Microsoft Corporation Managing cache data and metadata
US20100082550A1 (en) 2008-09-19 2010-04-01 Microsoft Corporation Aggregation of write traffic to a data store
US20040230743A1 (en) 2001-09-10 2004-11-18 Rambus Inc. Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules
US20050228964A1 (en) 2002-10-04 2005-10-13 Microsoft Corporation Methods and mechanisms for proactive memory management
US20100199063A1 (en) 2002-10-04 2010-08-05 Microsoft Corporation Methods and mechanisms for proactive memory management
US20110276743A1 (en) 2004-10-21 2011-11-10 Microsoft Corporation Using external memory devices to improve system performance
US20120102265A1 (en) 2008-09-19 2012-04-26 Microsoft Corporation Aggregation of Write Traffic to a Data Store
US20110197016A1 (en) 2008-09-19 2011-08-11 Microsoft Corporation Aggregation of Write Traffic to a Data Store
"Computervision Launches Design Automation Development Platform for Windows, UNIX Desktop Applications", PR Newswire, Jan. 10, 1995.
"Developer's Guide to Apple Data Detectors-For Version 1.0.2", Apple Computer, Inc., Dec. 1, 1997.
"Developer's Guide to Apple Data Detectors—For Version 1.0.2", Apple Computer, Inc., Dec. 1, 1997.
"Improved Recovery from Partial Page Writes of Data Pages", IBM Technical Disclosure Bulletin, vol. 36, No. 5, May 1993.
"Mechanical Design Software", Computer-Aided Engineering, Dec. 1993.
"Non-Volatile Memory Host Controller Interface (NVMHCI) 1.0". Apr. 14, 2008. 65 Pages.
"Optimization of CF Host Operation," SanDisk® Corporation, Feb. 28, 2005.
"Optimizing Program/Erase Times", Spansion™, Sep. 2, 2004.
"Oracle9i SQL Reference", Release 2 (9.2), Oct. 2002.
"Referential Integrity Implementation Details and Advantages", IBM Technical Disclosure Bulletin, vol. 38, No. 3, Mar. 1995.
Anderson, "A Case for Buffer Servers". Proceedings of the Seventh Workshop on Hot Topics in Operating Systems, Mar. 28-30, 1999.
Andrews, "Combining Language and Database Advances in an Object-Oriented Development Environment", Conference on Object-Oriented Programming Systems, Languages, and Applications(OOPSLA'87), Oct. 4-8, 1987.
Archer, Tom and Ayers, Matt, "ReadyBoost Q&A," Jun. 2006, http://blogs.msdn.com/b/tomarcher/archive/2006/06/02/615199.aspx. *
Archer, Tom, "ReadyBoost-Using Your USB Key to Speed Up Windows Vista," Apr. 2006, http://blogs.msdn.com/b/tomarcher/archive/2006/04/14/576548.aspx. *
Archer, Tom, "ReadyBoost—Using Your USB Key to Speed Up Windows Vista," Apr. 2006, http://blogs.msdn.com/b/tomarcher/archive/2006/04/14/576548.aspx. *
Beard, "Multilevel and Graphical Views of Metadata", Fifth International Forum on Research and Technology Advances in Digital Libraries, Apr. 22-24, 1998.
Beitner, "Multimedia Support and Authoring in Microcosm: an extended model", 1994.
Berg, "How Do I Create Persistent Java Objects?", Dr. Dobb's Journal, Apr. 1997.
Bhattacharya, "Coordinating Backup/Recovery and Data Consistency Between Database and File Systems", Proceedings of the 2002 ACM SIGMOND International Conference on Management of Data, Jun. 3-6, 2002.
Billiris, "The Performance of Three Database Storage Structures for Managing Large Objects", Proceedings of the 1992 ACM SIGMOD International Conference on Management of Data, Jun. 2-5, 1992.
Bisson, "A Hybrid Disk-Aware Spin-Down Algorithm with 110 Subsystem Support", Performance, Computing, and Communications Conference, Apr. 11-13, 2007.
Booch, "Object-Oriented Analysis and Design with Applications", The Benjainin/Cummings Publishing Company, Inc., 1994.
Bracchi, "Binary Logical Associations in Data Modelling", Modelling in Data Base Management Systems, Proceedings of the IFIP Working Conference on Modelling in Data Base Management Systems, Jan. 5-8, 1976.
Budiu, "A Dual-Disk File System: ext4", Apr. 16, 1997.
Bullock, "Recovery of Data Pages After Partial Page Writes", IBM Technical Disclosure Bulletin, Aug. 1, 1991.
Bunernan, "Inheritance and Persistence in Database Programming Languages", Proceedings of the 1986 ACM SIGMOD international Conference on Management of Data, May 28-30, 1986.
CA Examiner's Report for Application No. 2,523,761, Feb. 26, 2013.
Cammarata, "Extending a Relational Database with Deferred Referential Integrity Checking and Intelligent Joins", Proceedings of the 1989 ACM SIGMOD International Conference on Management of Data, May 31-Jun. 2. 1989.
CDRinfo, "Microsoft Explains Vista ReadyBoost," Nov. 2006, http://cdr- info.com/Sections/News/Details.aspx?NewsId=19077. *
Chien, "Concurrent Aggregates (CA): Design and Experience with a Concurrent Object-Oriented Language Based on Aggregates". Journal of Parallel and Distributed Computing, Mar. 1995.
Chryssostornidis; "Geometric Modeling Issues in Computer Aided Design of Marine Structures", Marine Technology Society Journal, vol. 22, No. 2, Dec. 1988.
Ciccozz , "Microsoft Press Computer Dictionary", Third Edition, 1997.
CN Decision on Rejection for Application No. 200680047384.6, Nov. 11, 2010.
CN Notice on First Office Action for Application No. 200510083792.4, Feb. 1, 2008.
CN Notice on First Office Action for Application No. 200510116208.0, Jun. 6, 2008.
CN Notice on the First Office Action for Application No. 200980136912.9, Jan. 14, 2013.
CN Notice on the First Office Action for Application No. 200980137190.9, Oct. 24, 2012.
CN Notice on the First Office Action for Application No. 200980145878.1, Jan. 29, 2013.
CN Notice on the Second Office Action for Application No. 200980137190.9, Mar. 20, 2013.
CN The First Office Action for Application No. 200680047384.6, Jan. 22, 2010.
CN The Second Office Action for Application No. 200510083792.4, Jun. 27, 2008.
D'Andrea, "UniSQL's Next-Generation Object-Relational Database Management System", Proceedings of the 1996 ACM SIGMOD International Conference on Management of Data, vol. 25, No. 3, Sep. 1996.
Darby, "Object Serialization in Java 1.1: Making Objects Persistent", WEB Techniques, Sep. 1997.
Darden, "Data Integrity: The Dell|EMC Distinction", May 2002. 5 Pages.
Dietrich, Jr., "TGMS: An Object-Oriented System for Programming Geometry", Software-Practice and Experience, Oct. 1989.
Dobashi, "Skylight for Interior Lighting Design", Eurographics '94 Conference Proceedings, vol. 13, No. 3, 1994.
Dorsch, "Accel signs with IBM to buy Album PCB unit-Accel Technologies acquires the assets to Altium's P-CAD business unit", LookSmart's FindArticles, Electronic News, Jan. 16, 1995.
Dorsch, "Accel signs with IBM to buy Album PCB unit—Accel Technologies acquires the assets to Altium's P-CAD business unit", LookSmart's FindArticles, Electronic News, Jan. 16, 1995.
Dove, "Windows XP for embedded applications", Jul. 10, 2008.
Ekman et al., TLB and Snoop Energy-Reduction using Virtual Caches in Low-Power Chip-Multiprocessors, ISLPED, Aug. 2002, pp. 243-246.
EP Communication for Application No. 03022573.4-1229, Reference EP28554-/df, Aug. 2, 2007.
EP Communication for Application No. 03022573.4-1229, Reference EP28554-/df, Nov. 8, 2007.
EP Communication for Application No. 03022573.4-1229, Reference EP28554-/df, Oct. 6, 2008.
EP Communication for Application No. 05103690.3-2201, Reference EP34981TE900kap, Apr. 24, 2008.
EP Communication for Application No. 05103697.8-2201, Reference EP349791-E900dfi, Oct. 26, 2007.
EP Communication for Application No. 05103697.8-2201, Reference EP34979TE900dfi, Jun. 17, 2008.
EP Communication for Application No. 05103697.8-2201, Reference EP34979TE900dfi, May 21, 2007.
EP Communication for Application No. 05103697.8-2201, Reference EP34979TE900dfi, Nov. 7, 2008.
EP Communication for Application No. 05109295.5-2201, Reference EP3683ORK900dfi, Jun. 8, 2007.
EP Communication for Application No. 09813565.0-1229/2329360 PCT/US2009056419, Apr. 3, 2012.
EP Communication for Application No. 09814983.4-2224/2329361 PCT/US2009055198, Reference FB24231, Oct. 10, 2012.
EP Communication for Application No. 09826570.5 229/2353081 PCTIUS2009063127, Reference FB24586, May 29, 2012.
EP Communication for Application No. 09826570.5-1229 / 2353081 PCT/US2009063127, reference FB24586, May 29, 2012.
EP Decision to refuse a European Patent for Application No. 05109295.5-2201, Reference EP3683ORK900dfi, Aug. 7, 2012.
EP Provision of the minutes for Application No. 05109295.5-2201, Reference EP3683ORK900dfi, Aug. 7, 2012.
EP Summons to attend or proceedings for Application No. 05109295.5-2201/1650666, Reference EP36830RK900dfi, Mar. 8, 2012.
EP Supplementary Search Report for Application No. 06839426, May 4, 2009.
EP Supplementary Search Report, Reference FB24240, Application No. 09813565.0-1229 / 2329360 PCT/US2009056419, Apr. 3, 2012.
Fegaras, "Optimizing Object Queries Using an Effective Calculus", ACM Transactions on Database Systems, vol. 25, No. 4, Dec. 2000.
Findler, "Contract Soundness for Object-Oriented Languages", Proceedings of the 2001 ACM SIGPLAN Conference on Object-Oriented Programming Systems, Languages and Applications, Oct. 14-18, 2001.
Foley, "Computer Graphics: Principles and Practices", Second Edition, Addison-Wesley Publishing Company, Chapter 5, pp. 201-227, 1990.
Fox, "Invention: The phantom car", NewScientist.com, Aug. 17, 2005.
Friis-Christensen; "Requirements and Research Issues in Geographic Data Modeling", Proceedings of the 9th ACM International Symposium on Advances in Geographic Information Systems, Nov. 9-10, 2001.
Fuh, "Implementation of SQL3 Structured Types with Inheritance and Value Substitutability", Proceedings of 25th International Conference on Very Large Data Bases (VLDB '99), Sep. 7-10, 1999.
Garret, Jr., "An Object-Oriented Environment for Representing Building Design and Construction Data", Advanced Construction Technology Center, Mar. 15, 1989.
Gosciriski, "Distributed Operating Systems: The logical Design", Addison-Wesley Publishers Ltd., 1991.
Greenan, "CompulsiveFS: Making NVRAM Suitable for Extremely Reliable Storage". Feb. 13-16, 2007.
Harrison, "Structure Editors: User-Defined Type Values and Type Inference", International Conference on Software Methods and Tools (SMT 2000), Nov. 6-9, 2000.
Haverlock, "Object Serialization, Java, and C++", Dr. Dobb 's Journal, Aug. 1, 1998.
Hay, "Data Model Patterns: Convention of Thought", Dorset House Publishing, Chapter 4 (pp. 46-67), and Chapter 12 (pp. 235-259), 1996.
Hernandez, "The Merge/Purge Problem for Large Databases", Proceedings of the 1995 ACM SIGMOD International Conference on Management of Data, May 22-25, 1995.
Hsiao, "DLFM: A Transactional Resource Manager", Proceedings of the 2000 ACM SIGMOD International Conference on Management of Data, May 16-18, 2000.
IL Notification of Defects in Patent Application No. 191502, Feb. 17, 2013.
International Search Report from PCT/US2009/056419, reference 325076-03 WO, Mar. 12, 2010.
International Search Report from PCT/US2009/063127, reference 325668-02 WO, May 31, 2010.
iSCSI, "Performance evaluations of iSCSI implementation", printed Jan. 10, 2008.
JP Notice of Reasons for Rejection for Application No. 2008-545888, Apr. 19, 2012.
JP Notice of Reasons for Rejection for Application No. 2008-545888, Aug. 29, 2012.
JP Notice of Rejection for Application No. 2005-134492, Jan. 25, 2011.
JP Notice of Rejection for Application No. 2005-135274, Sep. 24, 2010.
JP Notice of Rejection for Application No. 2005-135274, Sep. 9, 2011.
JP Notice of Rejection for Application No. 2005-306948, Mar. 11, 2011.
JP Notice of Rejection for Application No. 2011-527865, Oct. 16, 2012.
JP Notice of Rejection for Application No. 2012-111004, May 14, 2013.
Kaneko, "Design of 3D CG Data Model of "Move" Animation Database System", Advanced Database Research and Development Series, Proceedings of the Second Far-East Workshop On Future Database Systems, Apr. 26-28, 1992.
Kaneko, "Towards Dynamics Animation on Object-Oriented Animation Database System 'MOVE'", Advanced Database Research and Development Series. Proceedings of the Third International Symposium on Database Systems for Advanced Applications, Apr. 6-8, 1993.
Katz, "Toward a Unified Framework for Version Modeling in Engineering Databases", ACM Computing Surveys, vol. 22, No. 4, Dec. 1990.
Kawabe, "A Framework for 3D Modeling: Constraint-Based Description and Non-Manifold Geometric Modeling", Organization of Engineering Knowledge for Product Modelling in Computer Integrated Manufacturing, A Collection of Contributions Based on Lectures Presented at the 2nd Toyota Conference, Oct. 2-5, 1988.
Kempfer, "CAD Jumps on Windows 3.1 Bandwagon", Computer Aided Engineering, Nov. 1993.
Khan, "A Performance Evaluation of Storing XML Data in Relational Database Management Systems", Third International Workshop on Web Information and Data Management (WIM 2001), Nov. 9, 2001.
Khoshafian, "Object Identity", Proceedings of the ACM Conference on Object-Oriented Programming Systems, Languages, and Applications (OOPSLA'86), Sep. 1986.
Kiesling, "ODBC in UNIX Environments", Dr. Dobb's Journal, Dec. 2002.
King, "TriStarp-An Investigation into the Implementation and Exploitation of Binary Relational Storage Structures", Proceedings of the 8th British National Conference On Data Bases (BNCOD-8), Jul. 9-11, 1990.
King, "TriStarp—An Investigation into the Implementation and Exploitation of Binary Relational Storage Structures", Proceedings of the 8th British National Conference On Data Bases (BNCOD-8), Jul. 9-11, 1990.
Krouse, "Geometric Models for CAD/CAM", Machine Design, Jul. 24, 1980.
Larsen, "Improve Programming Performance with Intel® Flash Memory Enhanced Factory Programming," Intel Corporation, printed May 9, 2006.
LeBlanc, "Design Data Storage and Extraction Using Objects", Concurrent Engineering: Research and Applications, Mar. 1993.
Leontiev, "On Type Systems for Object-Oriented Database Programming languages", ACM Computing Surveys, vol. 34, No. 4, Dec. 2002.
Levy, "Incremental Recovery in Main Memory Database Systems", IEEE Transactions on Knowledge and Data Engineering, vol. 4, No. 6, Dec. 1992.
Lim, "Transaction Processing in Mobile, Heterogeneous Database Systems", IEEE Transactions on Knowledge and Data Engineering, vol. 14, No. 6, Nov./Dec. 2002.
Mallet, "Myrtle: A set-oriented meta-interpreter driven by a "relational" trace for deductive databases debugging", Jan. 1999.
Mariani, "Oggetto: An Object Oriented Database Layered on a Triple Store", The Computer Journal, vol. 35, No. 2, Apr. 1992.
Matthews, "Improving File System Performance With Adpative Methods", Fall 1999.
McMahon, "SED—A Non-interactive Text Editor", Bell laboratories, Jan. 10, 1979.
Melton, "SQL and Management of External Data", ACM SIGMOD Record, vol. 30, No. 1, Mar. 2001.
Mitchell, "Managing Cache Coherence in Multiprocessor Computer Systems", printed Jul. 10, 2008.
Mitchell, "The logic of Architecture", Massachusetts Institute of Technology, pp. 139-143. Apr. 26, 1990.
Motoazabu, "IEEE1394: A Dream interface at the Turning Pont", PC User, Softbank Publishing Corporation, Oct. 24, 1999.
Navathe, "Evolution of Data Modeling for Databases", Communications of the ACM, vol. 35, No. 9, Sep. 1992.
Nelson, "Generic Support for Caching and Disconnected Operation", 4th Workshop on Workstation Operating Systems (WWOS-IV), Oct. 14-15, 1993.
Nieplocha, "ARMCI: A Portable Aggregate Remote Memory Copy Interface", Oct. 30, 2000.
Nijssen, "Conceptual Schema and Relational Database Design: A Fact Oriented Approach", Prentice Hall, pp. 9-33, 42-43, 48-51, and 156-171, Jun. 1989.
Novell Documentation: NetWare 6, "NSS Features and Benefits", printed Jul. 10, 2008.
Ohn, "Path conscious caching of B+ tree indexes in a shared disks cluster", ScienceDirect, Dec. 4, 2006.
Orenstein, "Query Processing in the ObjectStore Database System", Proceedings of the 1992 ACM SIGMOD International Conference on Management of Data, Jun. 2-5, 1992.
Ottogalli, "Visualisation of Distributed Applications for Performance Debugging", International Conference on Computational Science (ICCS 2001), May 28-30, 2001.
Pachet, "A Combinatorial Approach to Content-based Music Selection", Proceedings of the IEEE International Conference on Multimedia Computing and Systems (ICMCS 1999), vol. 1, Jun. 7-11, 1999.
Papiani, "A Distributed Scientific Data Archive Using the Web, XML and SQL/MED", SIGMOD Record, Vol. 28, No. 3, Sep. 1999.
PCT International Search Report and Written Opinion for Application No. PCT/US2006/048402, Reference 314396.02 WO, May 8, 2007.
PCT International Search Report and Written Opinion for Application No. PCT/US2009/055198, reference 324268-02 WO, Feb. 26, 2010.
Ponnekanti, "Online Index Rebuild", Proceedings of the 2000 ACM SIGMOD International Conference on Management of Data, May 16-18, 2000.
Powell, "Object, References, Identifiers and Equality White Paper", SunSoft, OMG TC Document No. 93.7.5, Jul. 2, 1993.
Prosise, "2-D Drafting: Why Pay More?", PC Magazine, Feb. 23, 1993.
Ramsey, "An Algebraic Approach to File Synchronization", Proceedings of the Joint 8th European Software Engineering Conference (ESEC), and the 9th ACM SIGSOFT Symposium on the Foundations of Software Engineering (FSE-9) , Sep. 10-14, 2001.
Read III, "Developing the Next Generation Cockpit Display System", Proceedings of the IEEE 1996 National Aerospace and Electronics Conference (NAECON), May 20-23, 1996.
Reiner, "Benefits of X-based Three-Tier Client/Server Model with ESRI Applications", Virtual Solutions, 1995.
Rosenblum, "The Design and Implementation of a Log-Structured File System", Proceedings of the 13th ACM Symposium on Operating Systems Principles, Jul. 24, 1991.
Rouse, "CAD Pioneers Are Still Trailblazing", Machine Design, vol. 59, No. 25, Oct. 22, 1987.
Roussopoulos, "Using Semantic Networks for Data Base Management", Proceedings of the First International Conference on Very Large Data Bases (VLDB'75), Sep. 22-24, 1975.
RU Official Action for Application No. 2003129662, Nov. 11, 2007.
Santos, "Computer Aided Mechanicai Engineering Design Environment for Concurrent Design Process", Proceedings of the 1993 ITEC Workshop on Concurrent Engineering, Simulation in Concurrent Engineering, May 4-6, 1993.
Seshadri, "Enhanced abstract data types in object-relational databases", The VLB Journal, The International Journal on Very Large Databases, vol. 7, No. 3, Aug. 1998.
Simon, "Strategic Database Technology. Management for the Year 2000", Morgan Kaufmann Publishers, Inc., pp. 3-33, 55-69, May 1995.
Singhal, "DDB: An Object Oriented Design Data Manager for VLSI CAD", Proceedings of the 1993 ACM SIGMOD International Conference on Management of Data, May 26-28, 1993.
Sirnoes, "A RISC-Microcontroller Based Photovoltaic System for Illumination Applications", Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (APEC 2000), Feb. 6-10, 2000.
Sreekanth, "A Specification EnvirOnMent for Configuring a Discrete-Part Manufacturing System Simulation Infrastructure", International Conference on Systems, Man and Cybernetics, Systems Engineering in the Service of Humans, Oct. 17-20, 1993.
Sreenath, "A hybrid computation environment for multibody simulation", Mathematics and Computers in Simulation, vol. 34, Issue 2, Aug. 1992.
Stevens, "Value in 3-D", Industry Week, Jan. 8, 1996.
Stonebraker, "The Case for Partial Indexes", SIGMO Record, vol. 18, No. 4, Dec. 1989.
Strickland, "Intersection of Relational and Object", Proceedings of the AM/FM International Conference XVII, Mar. 14-17, 1994.
Sutherland, "The Hybrid Object-Relational Architecture (HORA): An Integration of Object-Oriented and Relational Technology", Proceedings of the 1993 ACM/SIGAPP Symposium on Applied Computing, States of the Art and Practice, Feb. 14-16, 1993.
Suzuki, "Geometric Modeling for Modeling Products", Proceedings of the Third International Conference on Engineering Graphics and Descriptive Geometry, vol. 2, Jul. 11-16, 1988.
Taylor, "An Integrated Robot System Architecture", Proceedings of the IEEE, vol. 71, No. 7, Jul. 1983.
TW Search Report for Application No. 094114140, Nov. 22, 2011.
Varlarnis, "Bridging XML-Schema and relational databases. A system for generating and manipulating relational databases using valid XML documents", Proceedings of the 2001 ACM Symposium on Document Engineering, Nov. 9-10, 2001.
Vitter, External Memory Algorithms, PODS, 1998, pp. 119-128.
Watanabe, "Knowledge Integration for Architectural Design", Knowledge-Based Computer-Aided Architectural Design, Jul. 1994.
Waugh, "Specifying metadata standards for metadata tool configuration", Computer Networks and ISDN Systems, Proceedings of the Seventh International World Wide Web Conference, Apr. 14-18, 1998.
Wilcox, "Object Databases: Object methods in distributed computing" Dr. Dobbs Journal, Nov. 1994.
Wold, "Content-Based Classification, Search, and Retrieval of Audio", IEEE MultiMedia, vol. 3, Issue 3, Sep. 1996.
Yoshikawa, "XRel: A Path-Based Approach to Storage and Retrieval of XML Documents Using Relational Databases", ACM Transactions on Internet Technology, vol. 1, No. 1, Aug. 2001.
Zhu, "Power Aware Storage Cache Management", Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801. May 2005.
US20140075126A1 (en) 2014-03-13 application
US20090150611A1 (en) 2009-06-11 application
US20090323940A1 (en) 2009-12-31 Method and system for making information in a data set of a copy-on-write file system inaccessible
Pang et al. 2003 StegFS: A steganographic file system
US20060193470A1 (en) 2006-08-31 Data storage device with data transformation capability
US20060224639A1 (en) 2006-10-05 Backup system, program and backup method
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FORTIN, MICHEL;ERGAN, CENK;IYIGUN, MEHMET;AND OTHERS;REEL/FRAME:020453/0159;SIGNING DATES FROM 20071127 TO 20071203
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FORTIN, MICHEL;ERGAN, CENK;IYIGUN, MEHMET;AND OTHERS;SIGNING DATES FROM 20071127 TO 20071203;REEL/FRAME:020453/0159
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE THE SPELLING OF FIRST NAMED INVENTOR FROM "MICHEL FORTIN" TO "MICHAEL FORTIN" PREVIOUSLY RECORDED ON REEL 020453 FRAME 0159. ASSIGNOR(S) HEREBY CONFIRMS THE FIRST NAMED INVENTOR SHOULD BE SPELLED AS FOLLOWS ON THE RECORDED ASSIGNMENT: MICHAEL FORTIN;ASSIGNORS:FORTIN, MICHAEL;ERGAN, CENK;IYIGUN, MEHMET;AND OTHERS;SIGNING DATES FROM 20071127 TO 20071203;REEL/FRAME:031616/0882