Source: http://www.google.com/patents/US5760471?dq=5,241,671
Timestamp: 2014-07-22 20:56:12
Document Index: 486770105

Matched Legal Cases: ['Application No.63', 'Application No.63', 'arts 4', 'arts 4', 'arts 4', 'Application No.6', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'arts 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'arts 24', 'art 24', 'art 24', 'arts 24', 'art 24', 'art 24', 'art 85', 'art 85', 'arts 194', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'arts 240', 'art 240', 'art 240', 'art 240', 'arts 240', 'arts 240', 'arts 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'art 240', 'arts 240', 'art 710', 'art 710', 'arts 710', 'art 710', 'art 710', 'art 710', 'art 240', 'art 240', 'art 710', 'art 710', 'art 710', 'art 240', 'art 240', 'arts 240', 'arts 710']

Patent US5760471 - Semiconductor device having an inner lead extending over a central portion ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA semiconductor device including a semiconductor element, and leads connected with the semiconductor element. Each of the leads includes an outer lead part for being connected externally. The semiconductor device further includes a plastic package sealing the semiconductor element and the leads. In the...http://www.google.com/patents/US5760471?utm_source=gb-gplus-sharePatent US5760471 - Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic packageAdvanced Patent SearchPublication numberUS5760471 APublication typeGrantApplication numberUS 08/794,763Publication dateJun 2, 1998Filing dateFeb 3, 1997Priority dateApr 20, 1994Fee statusLapsedPublication number08794763, 794763, US 5760471 A, US 5760471A, US-A-5760471, US5760471 A, US5760471AInventorsTetsuya Fujisawa, Mitsutaka Sato, Junichi Kasai, Masataka Mizukoshi, Kousuke Otokita, Hiroshi Yoshimura, Katsuhiro Hayashida, Akira Takashima, Masahiko Ishiguri, Michio SonoOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (45), Classifications (32), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic packageUS 5760471 AAbstract A semiconductor device including a semiconductor element, and leads connected with the semiconductor element. Each of the leads includes an outer lead part for being connected externally. The semiconductor device further includes a plastic package sealing the semiconductor element and the leads. In the semiconductor device, the outer lead part is exposed to the outside of a side face of the plastic package, and the plastic package is mounted on any base in a standing form by the side face contacting the base.
What is claimed is: 1. A semiconductor device comprising:a semiconductor element; leads connected with said semiconductor element, each of said leads including an inner lead part extending over a central portion of a first side of said semiconductor element and an outer lead part for being connected externally, said outer lead part extending over at least a portion of a second side of said semiconductor element; and a plastic package sealing said semiconductor element and said leads, wherein said outer lead part is sealed within said plastic package, and a portion of said outer lead part is viewable to the outside of a side face of said plastic package, and the plastic package is adapted to be mounted on any base in a standing form by said side face contacting the base. 2. The semiconductor device as claimed in claim 1, wherein said outer lead part further comprises parts which are exposed to the outside of two faces of the plastic package.
3. The semiconductor device as claimed in claim 1, wherein said semiconductor element comprises a back face which is exposed to the outside of the plastic package.
4. The semiconductor device as claimed in claim 1, wherein said device further comprises a stage on which the semiconductor element is mounted.
5. The semiconductor device as claimed in claim 1, wherein said outer lead part further comprises a part which is exposed to the outside of an opposite side face of said side face of the plastic package.
6. A semiconductor device unit comprising a plurality of semiconductor devices, each of said semiconductor devices having:a semiconductor element; leads connected with said semiconductor element, each of said leads including an inner lead part extending over a central portion of a first side of said semiconductor element and an outer lead part for being connected externally, said outer lead part extending over at least a portion of a second side of said semiconductor element; and a plastic package sealing said semiconductor element and said leads; wherein said outer lead part is sealed within said plastic package and a portion of said outer lead part is viewable to the outside of a side face of said plastic package, and the plastic package is mounted on any base in a standing form by said side face contacting the base, wherein said plurality of semiconductor devices are adaptable to be stacked one upon the other. 7. The semiconductor device as claimed in claim 6, wherein said outer lead part of each of said semiconductor devices further comprises parts which are exposed to the outside of two faces of the plastic package, and wherein said plurality of semiconductor devices are adapted to be stacked in a horizontal direction such that the outer lead parts of the semiconductor devices are connected to each other.
8. The semiconductor device unit as claimed in claim 6, wherein said semiconductor element of each of said semiconductor devices comprises a back face which is exposed to the outside of the plastic package.
9. The semiconductor device unit as claimed in claim 6, wherein each of said semiconductor devices further comprises a stage on which the semiconductor element is mounted.
10. The semiconductor device unit as claimed in claim 6, wherein said outer lead part further comprises a part which is exposed to the outside of an opposite side face of said side face of the plastic package, and wherein said plurality of semiconductor devices are stacked in a vertical direction such that the outer lead parts of the semiconductor devices are connected to each other.
11. The semiconductor device as claimed in claim 1, wherein said plastic package forms a chip size package structure around said semiconductor element.
12. The semiconductor device unit as claimed in claim 6, wherein said plastic package forms a chip-size package structure around said semiconductor element.
CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of application Ser. No. 08/525,347, filed Sep. 7, 1995, now abandoned, which is a Continuation-In-Part Application of a U.S. patent application Ser.No. 401,682 filed Mar. 10, 1995.
It has been required recently that electronic devices be miniaturized, capable of a high-speed operation, and have a high-level function, and it has been desired that a semiconductor device used in these electronic devices meet the same requirements.
To meet these requirements, a surface-mounted-type semiconductor device, in which leads are connected to a surface of the mounting base, is used. Further, it is desired to develop the semiconductor device in which higher-efficiency mounting can be performed.
FIG. 1 shows a perspective view of a conventional semiconductor device 1, and FIG. 2 is a cross-sectional view along line 2--2 of the semiconductor device shown in FIG. 1. The semiconductor device 1 has been proposed by the inventors of the present invention , and is disclosed in Japanese Laid-Open Patent Application No.63-15453, and Japanese Laid-Open Patent Application No.63-15451.
However, this configuration of the semiconductor device also has the following problem. In the semiconductor device shown in FIG. 2, the inner-lead parts 4a of the leads 4 are located outside the semiconductor chip 2 to make it easy for the wire 5 to be connected to the inner lead parts 4a. Therefore, the package 3 requires a large area for covering the semiconductor chip 2 and the inner-lead parts 4a, thus preventing sufficient miniaturization of the semiconductor device 1. Ideally speaking, it is desired that the semiconductor device has a size as small as that of the semiconductor chip. In actuality, the plastic package 3 of the semiconductor device 1 has a size three times that of the semiconductor chip 2.
To solve this problem, the inventors of the present invention proposed another configuration of the semiconductor device, which is disclosed in Japanese Laid-Open Patent Application No.6-132453 entitled "SEMICONDUCTOR DEVICE AND ITS FABRICATION METHOD". FIGS. 3A and 3B show a configuration of the other semiconductor device.
According to the above-mentioned semiconductor device 10, planar dimensions of the semiconductor device 10 may be reduced. Thus, high-density mounting may be achieved when the semiconductor device 10 is mounted as part of a single layer (two-dimensional-direction mounting) on a mounting base.
However, the above-mentioned semiconductor device 10 is mounted on the mounting base such that a widest face of six outside faces of the plastic package 17 contacts the mounting base. Therefore, for two-dimensional-direction mounting of a plurality of the semiconductor devices 10, a wider mounting space is required. Accordingly, in the semiconductor device 10, it is difficult to carry out the high-density mounting along two-dimensional directions.
On the other hand, recently, to perform a higher-density mounting, a method for layering and mounting a plurality of semiconductor devices along three-dimensional directions is frequently used. However, in the conventional semiconductor device 10 shown in FIGS. 3A and 3B, it is impossible to layer and mount the semiconductor devices 10 in a vertical direction. Therefore, in such a conventional semiconductor device, it is difficult to perform the higher-density mounting along three-dimensional directions.
SUMMARY OF THE INVENTION It is an object of this invention to provide a semiconductor device and a semiconductor device unit which realize an increased high-density mounting, in which the disadvantages described above are eliminated.
A more specific object of the present invention is to improve an efficiency and design flexibility in mounting semiconductor devices along three-dimensional directions.
The object described above is achieved by a semiconductor device comprising: a semiconductor element; leads being connected with the semiconductor element, each of the leads including an outer lead part for being connected externally; and a plastic package sealing the semiconductor element and the leads; wherein the outer lead part is exposed to the outside of a side face of the plastic package, and the plastic package is mounted on any base in a standing form by the side face contacting the base.
According to the above semiconductor device, the outer lead part for being connected externally is exposed to the outside of the side face of the plastic package and the side face in which the outer lead part is formed is used for a mounting face. Therefore, the plastic package may be mounted on any base in the standing form. Accordingly, a space necessary for mounting the semiconductor device on the base may be reduced, and the increased high-density mounting is realized.
The object described above is also achieved by the semiconductor device mentioned above, wherein the outer lead part further comprises parts which are exposed to the outside of two opposite faces crossing the side face of the plastic package.
According to the above semiconductor device, the outer lead part is also exposed to the outside of the two opposite faces of the plastic package. Therefore, the outer lead part may be connected externally in three faces, namely the side face, and the two opposite faces crossing the side face of the plastic package. Accordingly, an electrical connection method may be flexibly selected. And, since neighboring semiconductor devices may be connected to each other by using the outer lead parts in the above opposite faces, a plurality of the semiconductor devices may be stacked.
The object described above is also achieved by the semiconductor device mentioned above, wherein the semiconductor element comprises a back face which is exposed to the outside of the plastic package.
According to the above semiconductor device, the back face of the semiconductor element is exposed to the outside of the plastic package. Therefore, a heat radiation efficiency of the semiconductor element may be improved, and the semiconductor device may be miniaturized.
The object described above is also achieved by the semiconductor device mentioned above, wherein the device further comprises a stage on which the semiconductor element is mounted.
According to the above semiconductor device, the semiconductor element is mounted on the stage. Therefore, when plastic molding is carried out, the semiconductor element may be surely supported.
The object described above is also achieved by the semiconductor device mentioned above, wherein the outer lead part further comprises a part which is exposed to the outside of an opposite side face of the side face of the plastic package.
According to the above semiconductor device, the outer lead part is also exposed to the outside of the opposite side face of the side face for contacting the base. Therefore, the outer lead part may be connected externally in two opposite side faces of the plastic package. Since the semiconductor devices may be connected to each other by using the outer lead parts in the above opposite side faces, a plurality of the semiconductor devices may be stacked in a vertical direction.
The object described above is also achieved by a semiconductor device unit comprising a plurality of the above-mentioned semiconductor devices.
According to the semiconductor device unit, the semiconductor devices are connected to each other by the outer lead parts being electrically connected to each other. Therefore, a plurality of the semiconductor devices may be stacked in the horizontal and vertical directions. Accordingly, a large number of semiconductor devices may be mounted on a small space, and, thus, the mounting density may be further improved.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a perspective view of a conventional semiconductor device, and FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line 2--2;
FIGS. 28A to 28C show, respectively, a bottom view, a perspective view, and an extended illustration of the connection leads of the thirteenth embodiment of the semiconductor-device unit according to the present invention;
FIGS. 29A to 29C show, respectively, a bottom view, a perspective view, and an extended illustration of the connection leads of a fourteenth embodiment of a semiconductor-device unit according to the present invention;
FIG. 41 shows a cross-sectional view of a sixth embodiment of the semiconductor device according to the present invention;
FIG. 42A to FIG. 46 show manufacturing processes of the sixth embodiment of the semiconductor device according to the present invention shown in FIG. 41;
FIG. 47 shows a modification of the sixth embodiment of the semiconductor device shown in FIG. 41;
FIG. 48 shows another modification of the sixth embodiment of the semiconductor device shown in FIG. 41;
FIG. 49 shows a cross-sectional view of a seventh embodiment of the semiconductor device according to the present invention;
FIG. 50 shows a configuration of a semiconductor device unit having a plurality of the semiconductor devices shown in FIG. 49 which are arranged in a horizontal direction;
FIG. 51 shows a modification of the seventh embodiment of the semiconductor device shown in FIG. 49;
FIG. 52 shows another modification of the seventh embodiment of the semiconductor device shown in FIG. 49;
FIG. 53 shows a cross-sectional view of an eighth embodiment of the semiconductor device according to the present invention;
FIG. 54 shows a configuration of a semiconductor device unit having a plurality of the semiconductor devices shown in FIG. 53 which are arranged in horizontal and vertical directions;
FIG. 55 shows a modification of the eighth embodiment of the semiconductor device shown in FIG. 53; and
FIG. 56 shows another modification of the eighth embodiment of the semiconductor device shown in FIG. 53.
DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a description will be given of a first embodiment of a semiconductor device according to the present invention, by referring to FIG. 4. FIG. 4 shows a cross-sectional view of the semiconductor device of the first embodiment according to the present invention. A semiconductor device 20 includes a semiconductor element (semiconductor chip) 21 which is fixed on a stage 22. The semiconductor chip 21 is, for example, a memory chip, and has a relatively large size. Electrode pads 23 are formed on a center region of the semiconductor chip 21 and in a direction of a longer side of the semiconductor chip 21 (as shown in FIG. 12)
The first-port part 24b-1 is formed to be exposed on the bottom surface 27a of the plastic package 27, the second-port part 24b-2 is formed over the top surface 27b of the plastic package 27, and the third-port part 24b-3 is formed to extend in a vertical direction near side walls 27c of the plastic package 27. Thus, the outer-lead part 24b of each of the leads 24 is extended from the bottom surface 27a of the plastic package 27 to the top surface 27b thereof along an outline of the plastic package 27.
In the first-port part 24b-1, a portion thereof is buried in the bottom surface 27a of the plastic package 27. Further, between the second-port part 24b-2 and the top surface 27bof the plastic package 27, a small gap 28 is formed, and also between the third-port part 24b-3 and the side wall 27cof the plastic package 27, a small gap 29 is formed.
Assuming that a length of each lead 24 in a horizontal direction (direction indicated by arrow "G") is L1, an overlap length L2 between the lead 24 and the semiconductor chip 21 may be represented by 2�L1. Further, the plastic package 27 is formed to have almost the same area as that of the semiconductor chip 21,therefore, assuming that a length of the semiconductor chip 21 is L3 as shown in FIG. 4, a length of the semiconductor device 20 in the horizontal direction may be almost L3.
On the contrary, in the conventional semiconductor device 1 shown in FIGS. 1 and 2, a length L4 (not shown )of the package 3 in the horizontal direction may be almost represented by a sum of the length L3 of the semiconductor chip 2 and the length 2�L1 of the lead 4 (L4=L3+2�L1). Namely, the semiconductor device 20 according to the present invention may be miniaturized as compared with the semiconductor chip 1 shown in FIGS. 1 and 2 by the overlap length L2.
FIG. 5A shows a condition of the semiconductor device 20 before forming the second- and the third-port parts 24b-2, 24b-3. In this condition, the outer-lead part 24b is extended straight from the side wall 27cof the plastic package 27 in the horizontal direction. In FIG. 5A, only the outer-lead part 24b in a right side of the plastic package 27 is illustrated, but a left side of the plastic package 27 has a configuration similar to that of the right side thereof.
When the connection between an upper and a lower semiconductor device 20 is performed by a heating process such as soldering, the second-port part 24b-2 and the third-port part 24b-3 may be bent by thermal-expansion. However, in the semiconductor device 20, there is the gap 28 between the second-port part 24b-2 and the top surface 27b of the plastic package 27, and there is the gap 29 between the third-port part 24b-3 and the side wall 27c of the plastic package 27. Therefore, these gaps 28, 29 are available for space for deviation generated due to the second-port part 24b-2 and the third-port part 24b-3 being bent.
Further, because the semiconductor devices 20 are piled one upon the other if an amount of stress is applied on the second-port part 24b-2 and the third-port part 24b-3, these gaps absorb the stress by the port parts 24b-2, 24b-3 being bent.
As shown in the embodiments of FIGS. 9A and 9B, the first-port part 24b-1 and the second-port part 24b-2 can be symmetrically formed along upper and lower sides of the plastic package 27, therefore the reversed semiconductor devices 20 can also be piled one upon the other as shown in the semiconductor-device unit 50B, which operates like the semiconductor-device unit 50A. Thus such a configuration makes it possible to improve design flexibility in mounting these devices on the mounting base.
Further, since in the semiconductor device 35 in the semiconductor-device units 55A, 55B, symmetrical port parts 24b-1, 24b-2 like those of the semiconductor device 20 can be formed, the reversed semiconductor devices 25 can also be piled one upon the other as shown in the semiconductor-device unit 55B, which operates like the semiconductor-device unit 55A. Thus such a configuration also makes it possible to improve design flexibility in mounting these devices on the mounting base.
In the semiconductor-device unit 60 shown in FIG. 11, the semiconductor device 35 shown in FIG. 7 and reversed ones are piled one upon the other in a vertical direction. In the example shown in FIG. 11, the lower-side semiconductor device 35 is turned upside down. Therefore, the first-port part 24b-1 of the upper-side semiconductor device 35 is connected with the first-port part 24b-1 of the lower-side semiconductor device 35.
In the semiconductor-device unit 70 shown in FIG. 13, the plurality of the semiconductor devices 20 shown in FIG. 4 and reversed ones are respectively piled up in parallel with no spaces between them.
In the semiconductor-device unit 80 shown in FIG. 15, semiconductor devices 81a, 81b, which are ultra thin small L-lead package (UTSOP) type devices, are piled one upon the other on a mounting base 87. In each of the UTSOP-type semiconductor devices 81a, 81b, a semiconductor chip 84 mounted on a stage 83 is sealed within a plastic package 82, the stage 83 being exposed from the plastic package 82. Since the stages 83 are exposed from inside the plastic packages 82, such a configuration makes it possible to reduce the thickness of the semiconductor devices 81a, 81b, and to improve a heat radiation of the semiconductor chip 84.
Next, a description will be given of a ninth embodiment of the semiconductor-device unit according to the present invention, by referring to FIG. 17. FIG. 17 shows a cross-sectional view of the ninth embodiment of the semiconductor-device unit 95 according to the present invention. Like elements to those of FIG. 15 carry the same reference numerals. Also in the semiconductor-device unit 95 shown in FIG. 17, the UTSOP-type semiconductor devices 81a, 81b are piled one upon the other on the mounting base 87.
In the semiconductor-device unit 100, when the semiconductor devices 81a, 81b are piled one upon the other, the outer-lead part 85b of the semiconductor device 81a at the upper side is electrically connected to the outer-lead part 85b of the semiconductor device 81b at the lower side. For this electrical connection, any connecting method described above with reference to FIGS. 15 to 17 is available. Further, in the semiconductor-device unit 100, the plastic package 82 of the semiconductor device 81a is piled and fixed on the plastic package 82 of the semiconductor device 81b by inserting adhesive 101 between both the plastic packages 82. When the adhesive 101 is set, the adhesive may surely support the upper-side semiconductor device 81a against the lower-side semiconductor device 81b.
As shown in FIG. 25, in the conventional mounting configuration, when a plurality of the first semiconductor devices 122 are mounted on the mounting base 121, the supporting leads 126a, 126b, 127a and 127b of each first semiconductor device 122 are arranged without interrupting with each other. Therefore, a given space formed by a length (2�a) is needed for an interval space between the first semiconductor devices 122. However, this space formed by the length (2�a) is used only for the supporting leads 126a, 126b, 127a and 127b, and this configuration makes the mounting efficiency of the semiconductor devices poor.
FIGS. 28A to 28C show configurations of the thirteenth embodiment of the semiconductor-device unit 120 according to the present invention. FIG. 28A shows a bottom view of the semiconductor-device unit 120, FIG. 28B shows a perspective view thereof, and FIG. 28C shows an extended illustration of the connection leads 128, 130.
In the semiconductor-device unit 180, when an interval between the propping parts 194 is set wider, each of spaces between the semiconductor devices 160, 170 also becomes larger Such a configuration may improves a heat-radiation of the semiconductor-device unit 180 compared to a configuration in which the semiconductor devices 160, 170 are piled in close contact face to face with each other.
Next, a description will be given of a sixth embodiment of the semiconductor device according to the present invention. FIG. 41 shows a cross-sectional view of the sixth embodiment of the semiconductor device according to the present invention. A semiconductor device 205 has a semiconductor chip 210, for example, a semiconductor element of a memory chip. On a central part of the semiconductor chip 210, a plurality of electrode pads are straightly arranged (since FIG. 41 shows the cross-sectional view in a side direction, only one electrode pad 220 is illustrated). And, on a side of the semiconductor chip 210 (the side is referred to as a surface 210a, hereinafter) where the electrode pads are arranged, a cover film 230 is also formed. The cover film 230 is a plastic tape having an insulating function, and adheres to the surface 210a.
The semiconductor device 205 includes a plurality of leads 240 (in the same was as the electrode pad 220, only one lead 240 is illustrated). An inner lead part 240a which is formed on an inner side of each lead 240 extends over the semiconductor chip 210, and is connected to the electrode pad 220 formed on the semiconductor chip 210 through a wire 250. In this way, the semiconductor device 205 forms a lead-on-chip (LOC) structure. By applying the LOC structure to the device, the semiconductor device 205 may be miniaturized. The electrical connection between the inner lead part 240a and the electrode pad 220 is not limited to the above manner using the wire 250, but a flip chip connection using bumps may also be applied for the above electrical connection.
Further, in the lead 240, an outer lead part 240b is formed to be connected to the inner lead part 240a in series. The outer lead part 240b consists of a first-port part 240b-1 and a second-port part 240b-2. The lead 240 is fixed to the semiconductor chip 210 by the inner lead part 240a being adhered onto the cover film 230.
A plastic package 270 shown as a hatched element is made of a epoxy resin, etc., and seals the semiconductor chip 210, the leads 240, and the wires 250 to protect them. The plastic package 270 has an approximately rectangular solid shape, and has almost the same dimensions as that of the semiconductor chip 210. In this way, the semiconductor device 205 has a chip-size package (CSP) structure, and, thereby, the semiconductor device 205 may be further miniaturized.
The outer lead part 240b of the lead 240 is extended along the inside of surfaces of the plastic package 270. In further detail, the plastic package 270 has six outside faces, the face opposite to the surface 210a of the semiconductor chip 210 being referred to as a surface 270b, and the face opposite to a side face of the semiconductor chip 210 being referred to as a side face 270a. The second-port part 240b-2 of the outer lead part 240b is extended along the inside of the surface 270b of the plastic package 270, and the first-port part 240b-1 of the outer lead part 240b is extended along the inside of the side face 270a of the plastic package 270.
In the side face 270a, the first-port part 240b-1 is exposed to the outside of the plastic package 270, and in the surface 270b, the second-port part 240b-2 is exposed to the outside of the plastic package 270. Therefore, the first-port part 240b-1 and the second-port part 240b-2 are available as externally connecting ports.
The inner lead part 240a and the outer lead part 240b in the lead 240 can be formed by properly bending the lead 240. Therefore, the lead 240 having such a construction may be easily formed. Since the lead 240 except the first-port part 240b-1 and the second-port part 240b-2 is sealed within the plastic package 270, the lead 240 is surely protected and a lead pitch between the neighboring leads 240 may be maintained at a constant pitch. Therefore, no short circuit between the neighboring leads 240 occurs, and, thus, a reliability of the semiconductor device 205 may be improved.
In the semiconductor device 205 shown in FIG. 41, a back surface 210b of the semiconductor chip 210 is exposed from a back surface 270c of the plastic package 270. Therefore, heat generated in the semiconductor chip 210 may be efficiently radiated externally, and the plastic package 270 may be small in size. Accordingly, an efficiency of heat radiation of the semiconductor device 205 may be improved, and the semiconductor device 205 may be further miniaturized.
As mentioned above, in the semiconductor device 205, the first-port part 240b-1 of the outer lead part 240 available as the externally connecting port is extended to be exposed to the outside of the side face 270a of the plastic package 270. Therefore, the side face 270a in which the first-port part 240b-1 is formed is available as a connecting face for mounting the plastic package 270 on a mounting base (not shown). As a result, the plastic package 27 may be mounted in a standing form, which is referred to as a standing-form mount, hereinafter. By using the standing-form mount, a mounting space on the mounting base necessary for mounting the semiconductor device 205 may be reduced, and, thus, the high-density mounting may be realized.
Next, a description will be given of a manufacturing process of the sixth embodiment of the semiconductor device 205 shown in FIG. 41, by referring to FIG. 42A to FIG. 46. FIG. 42A to FIG. 46 show the manufacturing processes of the sixth embodiment of the semiconductor device 205 according to the present invention shown in FIG. 41. Elements in FIG. 42A to FIG. 46 which are the same as those of FIG. 41 are given the same reference numerals.
For manufacturing the semiconductor device 205, a lead frame 300 is formed first. For forming the lead frame 300, a base plate made of a lead frame material such as a 42 alloy and an alloy of copper is prepared and is, for example, pressed and stamped out (other processing methods such as etching are available). In this way, the lead frame 300 comprising the leads 240, timbers 310, and a cradle 320 is provided.
FIG. 42B shows a cross-sectional view of the lead frame 300 along a 42-42 line shown in FIG. 42A. As shown in FIG. 42B, when the base plate is pressed and stamped out to provide the lead frame 300, a shaping process (bending process) of the leads 240 are simultaneously carried out. In this way, at the same time, the lead frame 300 is provided by the pressing and stamping out processes, and the inner lead part 240a, and the first- and second-port parts 240b-1, 240b-2 are formed by the shaping process. Therefore, the manufacturing process of the lead frame 300 may be simplified.
After the lead frame 300 is formed, as shown in FIG. 43, the lead frame 300 is installed on the semiconductor chip 210. On the surface 210a of the semiconductor chip 210 except for a space around where the electrode pad 220 is formed, the cover film 230 is previously adhered. And, the inner lead part 240a of the lead frame 300 is connected to the cover film 230 by using an insulating adhesive. In this way, the lead frame 300 and semiconductor chip 210 are connected to each other. At this time, the electrode pad 220 is also formed. A connected point of the inner lead part 240a is selected close to the space for forming the electrode pad 220.
After the lead frame 300 and the semiconductor chip 210 are connected to each other, as shown in FIG. 44, the wire 250 is connected between the inner lead part 240a and the electrode pad 220. The easy and rapid process of connecting the wire 250 is realized by using a wire bonding apparatus.
After the wire bonding process is finished, as shown in FIG. 45, the semiconductor chip 210 and the lead frame 300 are provided to a metal mold, and the plastic package 270 is formed by a molding process. In the molding process, the first- and second-port parts 240b-1, 240b-2 of the lead 240 directly contact a cavity of the metal mold without a gap. Thereby, the first- and second-port parts 240b-1, 240b-2 may be easily exposed to the outside of the plastic package 270. In the same way, since the back surface 210b of the semiconductor chip 210 directly contacts the cavity of the metal mold without a gap in the molding process, the back surface 210b may be easily exposed to the outside of the plastic package 270.
After the plastic package 270 is formed, the process proceeds to a process of removing burrs generated in the plastic package 270, a process of gilding the first- and second-port parts 240b-1, 240b-2 with a solder, and a process of removing unnecessary parts (the timbers 310, the cradle 320, etc.) in the lead frame 300. When the above successive processes are finished, the semiconductor device 205 shown in FIG. 41 is provided.
In the manufacturing process shown in FIG. 42A to FIG. 45, the lead frame 300 is used for forming the lead 240, and the wire 250 is used for electrically connecting the lead 240 and the semiconductor chip 210. However, the methods of forming the lead 240 and connecting the lead 240 and the semiconductor chip 210 are not limited to the above embodiment. For example, as shown in FIG. 46, for the forming of the lead 240, a tape lead 330 in which connection lines are printed on a plastic base film is available. And, for the electrical connection of the tape lead 330 and the semiconductor chip 210, a bump 340 is available.
FIG. 47 and FIG. 48 respectively show modifications of the semiconductor device 205 of the sixth embodiment shown in FIG. 41. Elements in FIG. 47 and FIG. 48 which are the same as those of FIG. 41 are given the same reference numerals.
In FIG. 47, a semiconductor device 400 has a feature that the semiconductor chip 210 with the back face 210b is fully sealed within the plastic package 270. The semiconductor device 400 is suitable for cases that an amount of heat evolution from the semiconductor chip 210 is relatively small, or the semiconductor chip 210 is easily damaged by humidity and the air.
In FIG. 48, a semiconductor device 450 has a feature that the semiconductor chip 210 is disposed on a stage 460 and the semiconductor chip 210 with the stage 460 is fully sealed within the plastic package 270. In the configuration shown in FIG. 44, since the semiconductor chip 210 and the lead frame 300 are connected to each other by only bonding the inner lead part 240a and the cover film 230, a reliable connection between the semiconductor chip 210 and the lead frame 300 may not be obtained. In this case, when the semiconductor chip 210 and the lead frame 300 are provided to the metal mold for the plastic molding process, the semiconductor 210 may be disconnected from the lead frame 300.
On the contrary, in the semiconductor device 450 shown in FIG. 48, the stage 460 is provided to the lead frame 300 and the semiconductor chip 210 is disposed on the stage 460. Therefore, the semiconductor chip 210 is surely prevented from being disconnected from the lead frame 300. The stage 460 with the lead 240 may be formed by being integrated in the lead frame 300. Or, a lead frame for the lead 240 and a lead frame for the stage 460 may be individually formed, and the lead frame 300 including the stage 460 may be formed by integrating these two lead frames by welding, etc.
Next, a description will be given of a seventh embodiment of the semiconductor device according to the present invention. FIG. 49 shows a cross-sectional view of the seventh embodiment of the semiconductor device according to the present invention. Elements in FIG. 49 which are the same as those of FIG. 41 are given the same reference numerals.
In the semiconductor device 205 of the sixth embodiment, the outer lead part 240b is extended to the side face 270a of the plastic package 270. However, in a semiconductor device 500 of the seventh embodiment, the outer lead part 240b is further extended to the back face 270c of the plastic package 270, and a third-port part 240b-3 is formed in the back face 270c. Namely, the semiconductor device 500 has a feature that the outer lead part 240b is exposed in the opposite faces, the surface 270b and the back face 270c, which are in a vertical direction perpendicular to the side face 270a, as well as in the side face 270a (mounting face) of the plastic package 270.
In this way, in the semiconductor device 500, the first-port part 240b-1 is formed in the side face 270a of the plastic package 270, the second-port part 240b-2 is formed in the surface 270b of the plastic package 270, and the third-port part 240b-3 is formed in the back face 270c of the plastic package 270.
Therefore, a plurality of the semiconductor devices 500 may be stacked in a horizontal direction.
FIG. 50 shows a configuration of a semiconductor device unit having a plurality of the semiconductor devices 500 which are arranged in the horizontal direction. In a semiconductor device unit 550 shown in FIG. 50, to electrically connect the neighboring semiconductor devices 500 to each other, the second-port part 240b-2 formed in the surface 270b of the semiconductor device 500 and the third-port part 240b-3 formed in the back face 270c of a neighboring semiconductor device 500 are connected to each other. And, each semiconductor device 500 is electrically connected to the mounting base (not shown) by the first-port part 240b-1 formed in the side face 270a of the plastic package 270.
In this way, in the semiconductor device 500 according to the present invention, since the first-, second- and third-port parts 240b-1, 240b-2 and 240b-3 are exposed to the outside of the faces 270a, 270b, 270c of the plastic package 270, a plurality of semiconductor devices 500 may be stacked one upon the other to provide the semiconductor device unit 550. Therefore, the semiconductor devices 500 may be arranged in a higher density as compared to the semiconductor device 200 shown in FIG. 41, and the mounting density may be further improved. As a result, an electronic apparatus having the semiconductor device unit 550 may be further miniaturized.
FIG. 51 and FIG. 52 respectively show modifications of the semiconductor device 500 of the seventh embodiment shown in FIG. 49. Elements in FIG. 51 and FIG. 52 which are the same as those of FIG. 49 are given the same reference numerals.
In FIG. 51, a semiconductor device 600 has a feature that the back face 210b of the semiconductor chip 210 is exposed to the outside of the back face 270c of the plastic package 270 as compared to the semiconductor device 500. According to the semiconductor device 600, in the same way as the semiconductor device 205 shown in FIG. 41, the heat radiation efficiency of the semiconductor chip 210 may be improved, and the plastic package 270 may be miniaturized.
In FIG. 52, a semiconductor device 650 has a feature that the semiconductor chip 210 is disposed on the stage 460, and the semiconductor chip 210 with the stage 460 is fully sealed within the plastic package 270. According to the semiconductor device 650, in the same way as the semiconductor device 450 shown in FIG. 48, the semiconductor chip 210 is surely prevented from being disconnected from the lead frame 300.
Next, a description will be given of an eighth embodiment of the semiconductor device according to the present invention. FIG. 53 shows a cross-sectional view of the eighth embodiment of the semiconductor device according to the present invention. Elements in FIG. 53 which are the same as those of FIG. 49 are given the same reference numerals.
In the semiconductor device 500 shown in FIG. 49, the lead 240 is extended to one side of the two sides of the plastic package 270, namely the side face 270a. On the contrary, in the semiconductor device 700, in addition to the lead 240, a lead 710 is extended to an opposite side of the side face 270a, namely a side face 270d of the plastic package 270. Shapes of the lead 710 extended to the side face 270d and the lead 240 extended to the side face 270a are symmetrical with each other.
In the semiconductor device 700, an electrode pad 730 is also formed on the semiconductor chip 210 in addition to the electrode pad 220. An inner lead part 710a of the lead 710 is electrically connected to the electrode pad 730 by a wire 720. And, in the same way as the lead 240, an outer lead part 710b of the lead 710 includes first-, second- and third-port parts 710b-1, 710b-2 and 710b-3. The first-port part 710b-1 is exposed to the outside of the side face 270d of the plastic package 270, the second-port part 710b-2 is exposed to the outside of the surface 270b of the plastic package 270, and the third-port part 710b-3 is exposed to the outside of the back face 270c of the plastic package 270.
In the semiconductor device 500 shown in FIG. 49, when the semiconductor device 500 is connected to another semiconductor device 500 or the mounting base, only ports in a lower part of the semiconductor device 500 are used. On the contrary, in the semiconductor device 700, in addition to the port in the lower part of the semiconductor device 700, ports in an upper part thereof can be also used for the electrical connection. Therefore, the semiconductor device 700 has a flexibility of the electrical connection. Namely, though the semiconductor device 500 of the seventh embodiment shown in FIG. 49 may be stacked in only the horizontal direction, the semiconductor device 700 of the eighth embodiment shown in FIG. 53 may be stacked in both the horizontal direction and the vertical direction.
FIG. 54 shows a configuration of a semiconductor device unit having a plurality of the semiconductor devices shown in FIG. 53 which are arranged in the horizontal and vertical directions. In a semiconductor device unit 750 shown in FIG. 54, to electrically connect the neighboring semiconductor devices 700 to each other in the horizontal direction, the second-port part 240b-2 formed in the surface 270b of the semiconductor device 700 and the third-port part 240b-3 formed in the back face 270c of the neighboring semiconductor device 700 are connected to each other. And also, the second-port part 710b-2 formed in the surface 270b of the semiconductor device 700 and the third-port part 710b-3 formed in the back face 270c of the neighboring semiconductor device 700 are connected to each other.
And, to electrically connect the neighboring semiconductor devices 700 in the vertical direction to each other, the first-port part 710b-1 formed in the side face 270d of a lower-side semiconductor device 700 and the first-port part 240b-1 formed in the side face 270a of an upper-side semiconductor device 700 are connected to each other.
Further, each lowest-side semiconductor device 500 is electrically connected to the mounting base (not shown) by the first-port part 240b-1 formed in the side face 270a of the plastic package 270.
In this way, in the semiconductor device 700 according to the present invention, since the first-, second- and third-port parts 240b-1, 240b-2 and 240b-3 formed in the lead 240 and the first-, second- and third-port parts 710b-1, 710b-2 and 710b-3 formed in the lead 710 are exposed to the outside of the faces 270a, 270b, 270c, 270d of the plastic package 270, a plurality of semiconductor devices 700 may be stacked in both horizontal and vertical directions to provide the semiconductor device unit 750. Therefore, the semiconductor devices 700 may be arranged in a higher density as compared to the semiconductor device 500 shown in FIG. 49, and the mounting density of the semiconductor devices 700 may be further improved. As a result, an electronic apparatus having the semiconductor device unit 750 may be further miniaturized.
FIG. 55 and FIG. 56 respectively show modifications of the semiconductor device 700 of the eighth embodiment shown in FIG. 53. Elements in FIG. 55 and FIG. 56 which are the same as those of FIG. 53 are given the same reference numerals.
In FIG. 55, a semiconductor device 800 has a feature that the back face 210b of the semiconductor chip 210 is exposed to the outside of the back face 270c of the plastic package 270 as compared to the semiconductor device 700. According to the semiconductor device 800, in the same way as the semiconductor devices 205, 600 shown in FIGS. 41, 51, as compared to the semiconductor device 700, the heat radiation efficiency of the semiconductor chip 210 may be improved, and the plastic package 270 may be miniaturized.
In FIG. 56, a semiconductor device 850 has a feature that the semiconductor chip 210 is disposed on the stage 460, and the semiconductor chip 210 with the stage 460 is fully sealed within the plastic package 270. According to the semiconductor device 850, in the same way as the semiconductor devices 450, 650 shown in FIGS. 48, 52, the semiconductor chip 210 is surely prevented from being disconnected from the lead frame 300.
According to the above semiconductor device, the outer lead part for being connected externally is exposed to the outside of the side face of the plastic package and the side face in which the outer lead part is formed is used for the mounting face. Therefore, the plastic package may be mounted on any base in the standing form. Accordingly, a space necessary for mounting the semiconductor device on the base may be reduced, and the increased high-density mounting is realized.
According to the above semiconductor device, the outer lead part is also exposed to the outside of the two opposite faces of the plastic package. Therefore, the outer lead part may be connected externally in three faces, namely the side face, and the two opposite faces crossing the side face of the plastic package. Accordingly, an electrical connection method may be flexibly selected. And, since neighboring semiconductor devices may be connected to each other by using the outer lead parts in the above opposite faces, a plurality of the semiconductor devices may be stacked in the horizontal direction.
According to the above semiconductor device, the back face of the semiconductor element may be exposed to the outside of the plastic package. Therefore, the heat radiation efficiency of the semiconductor element may be improved, and the semiconductor device may be miniaturized.
According to the above semiconductor device, the semiconductor element may be mounted on the stage. Therefore, when plastic molding is carried out, the semiconductor element may be surely supported.
According to the above semiconductor device, the outer lead part is also exposed to the outside of the opposite side face of the side face for being contacted with the base. Therefore, the outer lead part may be connected externally in the two opposite side faces of the plastic package. Since the semiconductor devices may be connected to each other by using the outer lead parts in the above opposite side faces, a plurality of the semiconductor devices may be stacked in the vertical direction.
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2013美光科技公司Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methodsDE19833713C1 *Jul 27, 1998May 4, 2000Siemens AgLaminate or stacked package arrangement based on at least two integrated circuitsEP2306516A1 *Sep 30, 2009Apr 6, 2011Tyco Electronics Nederland B.V.Semiconductor device, method for fabricating a semiconductor device and lead frame, comprising a bent contact sectionWO2009014989A1 *Jul 17, 2008Jan 29, 2009Micron Technology IncMicroelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods* Cited by examinerClassifications U.S. Classification257/692, 257/E23.039, 257/698, 257/723, 257/693, 257/686, 257/E25.023, 257/E23.047, 257/696, 257/666International ClassificationH01L23/495, H01L25/10Cooperative ClassificationH01L24/48, H01L2924/01013, H01L2224/48247, H01L25/105, H01L23/49551, H01L2224/48091, H01L2924/01029, H01L2924/01079, H01L2224/48465, H01L2224/4826, H01L23/4951, H01L2224/32245, H01L2224/73215, H01L2225/1041, H01L2225/1005, H01L2225/107, H01L2225/1029European ClassificationH01L23/495G4B, H01L23/495A4, H01L25/10JLegal EventsDateCodeEventDescriptionJul 30, 2002FPExpired due to failure to pay maintenance feeEffective date: 20020602Jun 3, 2002LAPSLapse for failure to pay maintenance feesDec 26, 2001REMIMaintenance fee reminder mailedRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google