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Patent US6368733 - Semiconductor substrate overcoated with masking layer - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor substrate comprising a single crystal substrate having thereon a mask and a Group III-V compound semiconductor epitaxially grown layer, said mask comprising an insulating material thin film or high melting point metal thin film having a plurality of slit-like exposed areas running at...http://www.google.com/patents/US6368733?utm_source=gb-gplus-sharePatent US6368733 - Semiconductor substrate overcoated with masking layerAdvanced Patent SearchPublication numberUS6368733 B1Publication typeGrantApplication numberUS 09/369,148Publication dateApr 9, 2002Filing dateAug 5, 1999Priority dateAug 6, 1998Fee statusPaidPublication number09369148, 369148, US 6368733 B1, US 6368733B1, US-B1-6368733, US6368733 B1, US6368733B1InventorsTatau NishinagaOriginal AssigneeShowa Denko K.K.Export CitationBiBTeX, EndNote, RefManPatent Citations (8), Non-Patent Citations (1), Referenced by (12), Classifications (21), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor substrate overcoated with masking layerUS 6368733 B1Abstract A semiconductor substrate comprising a single crystal substrate having thereon a mask and a Group III-V compound semiconductor epitaxially grown layer, said mask comprising an insulating material thin film or high melting point metal thin film having a plurality of slit-like exposed areas running at an angle in excess of 0�, and said Group III-V compound semiconductor epitaxially grown layer being formed by growing a Group III-V compound semiconductor starting from each of said plurality of exposed areas and conjunction-integrating the grown semiconductors on said mask.
What is claimed is: 1. A semiconductor substrate comprising a single crystal substrate having thereon a mask and a Group III-V compound semiconductor epitaxially grown layer, said mask comprising an insulating material thin film or high melting point metal thin film having a plurality of slit-like exposed areas running at an angle in excess of 0� with respect to an adjacent slit-like exposed area, and said Group III-V compound semiconductor epitaxially grown layer being formed by growing a Group III-V compound semiconductor starting from each of said plurality of exposed areas and conjunction-integrating the grown semiconductors on said mask.
2. A semiconductor substrate comprising a single crystal substrate having thereon a basal layer, a mask formed on said basal layer and a Group III-V compound semiconductor epitaxially grown layer, said basal layer comprising a Group III-V compound semiconductor grown layer, said mask comprising an insulating material thin film or high melting point metal thin film having a plurality of slit-like exposed areas running at an angle in excess of 0� with respect to an adjacent slit-like exposed area, and said Group III-V compound semiconductor epitaxially grown layer being formed by epitaxially growing a Group III-V compound semiconductor starting from each of said plurality of exposed areas and conjunction-integrating the grown semiconductors on said mask.
4. A semiconductor substrate comprising a single crystal substrate having thereon a mask and a Group III-V compound semiconductor epitaxially grown layer, said mask comprising an insulating material thin film or high melting point metal thin film having a plurality of exposed areas each in the shape of a single closed curve, and said Group III-V compound semiconductor epitaxially grown layer being grown on the mask between said exposed areas starting from said exposed areas adjacent to each other and conjunction-integrated on said mask, wherein two boundaries defined by the mask part between said adjacent exposed areas and respective exposed areas run at an angle in excess of 0�.
5. A semiconductor substrate comprising a single crystal substrate having thereon a basal layer, a mask formed on said basal layer and a Group III-V compound semiconductor epitaxially grown layer, said basal layer comprising a Group III-V compound semiconductor grown layer, said mask comprising an insulating material thin film or high melting point metal having a plurality of exposed areas each in the shape of a single closed curve, and said Group III-V compound epitaxially grown layer being grown on the mask between said exposed areas starting from said exposed areas adjacent to each other and conjunction-integrated on said mask, wherein two boundaries defined by the mask part between adjacent exposed areas and respective exposed areas run at an angle in excess of 0�.
6. A semiconductor substrate comprising a single crystal substrate having thereon a mask and a Group III-V compound semiconductor epitaxially grown layer, said mask comprising an insulating material thin film or high melting point metal thin film having an exposed area in the shape of a single closed straight line having at least one pair of two adjacent linear sides meeting at an angle of from 250 to 358�, and said Group III-V compound semiconductor epitaxially grown layer being conjunction-integrated on the mask part within a triangle including said two sides on said mask.
7. A semiconductor substrate comprising a single crystal substrate having thereon a basal layer, a mask formed on said basal layer and a Group III-V compound semiconductor epitaxially grown layer, said basal layer comprising a Group III-V compound semiconductor grown layer, said mask comprising an insulating material thin film or high melting point metal thin film having an exposed area in the shape of a single closed curve having at least one pair of two adjacent linear sides meeting at an internal angle of 250 to 358�, and said Group III-V compound semiconductor epitaxially grown layer being conjunction-integrated on the mask part within a triangle including said two sides on said mask.
8. A semiconductor substrate comprising a single crystal substrate having thereon a mask and a Group III-V compound semiconductor epitaxially grown layer, said mask comprising an insulating material thin film or high melting point metal thin film having an exposed area consisting of at least one pair of two right-angled triangles disposed in a line symmetric manner with each other such that two sides meeting at right angles of one right-angled triangle lie in a straight line with or run in parallel to two sides meeting at right angles of another right-angled triangle and the internal angle defined by two hypotenuses of said one pair of two right-angled triangles is from 250 to 358�, and said Group III-V compound semiconductor epitaxially grown layer being conjunction-integrated on the mask within a triangle including said two sides on said mask.
9. A semiconductor substrate comprising a single crystal substrate having thereon a basal layer, a mask formed on said basal layer and a Group III-V compound semiconductor epitaxially grown layer, said basal layer comprising a Group III-V compound semiconductor grown layer, said mask comprising an insulating material thin film or high melting point metal thin film having an exposed area consisting of at least one pair of two right-angled triangles disposed in a line symmetric manner with each other such that two sides meeting at right angles of one right-angled triangle lie in a straight line with or run in parallel to two sides meeting at right angles of another right-angled triangle and the internal angle defined by two hypotenuses of said one pair of two right-angled triangles is from 250 to 358�, and said Group III-V compound semiconductor epitaxially grown layer being conjunction-integrated on the mask within a triangle including said two sides on said mask.
CROSS REFERENCE TO RELATED APPLICATIONS This application is an application filed under 35 U.S.C. �111(a) claiming benefit pursuant to 35 U.S.C. �119(e)(i) of the filing date of the Provisional Application No. 60/116,584 filed Jan. 20, 1999 based on Japanese Applications 10-258868 filed Sep. 11, 1998 and 10-223281 filed Aug. 6, 1998 pursuant to 35 U.S.C. �111(b).
FIELD OF THE INVENTION The present invention relates to a low dislocation substrate useful for epitaxial growth mainly of a GaN system.
BACKGROUND OF THE INVENTION GaN has been already put into commercial products as a crystal for short wavelength light elements such as blue and ultraviolet light. Further, studies are being made thereon for developing higher performance elements or on application to electronic devices. However, a GaN-type crystal has no single crystal substrate for its epitaxial growth. Therefore, at the present time, a method of growing a low temperature buffer layer on a sapphire substrate and growing thereon a GaN single crystal layer at a high temperature is mainly used.
For example, JP-B-6-105797 (the term �JP-B� as used herein means an �examined Japanese patent publication�) discloses a technique of forming a mask comprising an insulating material thin film or high melting point metal thin film on a semiconductor substrate such that an exposed area in the shape of a fine line is provided on a part of the mask, and growing a low dislocation epitaxial layer in the direction parallel to the substrate surface by epitaxy over the entire surface of the substrate through the exposed area.
SUMMARY OF THE INVENTION An object of the present invention is to provide a technique of transverse growth, where the insulating material thin film or high melting point metal thin film formed on a single crystal surface is designed to have a specific shape to thereby reduce the crystal defects appearing in the junction area of epitaxial growth layers grown from adjacent exposed areas on the mask part and provide a crystal layer reduced in the defects as compared with that formed by conventional techniques.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing one example of the mask for use in the present invention and also showing the transverse growth process.
DETAILED DESCRIPTION OF THE INVENTION The present inventors have studied in detail the cause of generation of the linear crystal defects in the junction area on a mask in the transverse growth and reached the present invention.
In the transverse growth, the mask parts adjacent to exposed areas are usually formed like parallel lines and the front parts of the growth layers (hereinafter referred to as a �growth front�) grown from adjacent exposed areas grow in parallel. As a result, the two growth fronts come into contact nearly at the center portion of the mask part throughout the length of the growth front.
In the figure, the small width portions are exposed areas 1 formed after the thin film is removed by etching and the large width portions are mask parts 2. In the example of FIG. 1, the exposed area and the mask part both are bent every 200 μm and continued in the longitudinal direction. Such a mask pattern is repeatedly formed over the entire surface of the substrate having a size of 20 mm�20 mm. In the figure, the numerical value between arrows is a dimension in the unit of μm.
In the example of the figure, the angle defined by the two edges 2 a and 2 b of the mask is about 0.86�, namely, the adjacent exposed areas 1 are formed to lean at an angle of about 0.86�.
By forming the mask part 2 such that two edges 2 a and 2 b meet at an angle (hereinafter referred to as a �mask boundary angle�) in excess of 0�, preferably of 0.30 or more, the layers grown starting from adjacent exposed areas are allowed to come into contact at a portion of the mask part having the smallest width, thus, the contact can be made to occur at one portion.
In the case of a laser diode in which the present invention is considered to be mainly used, the size of the active area is a few μm�hundreds of μm square for an edge surface emission type and tens of μm square for a surface emission type. In order to form a low dislocation crystal layer of this size, the contact is not necessarily required to occur at one point throughout the length over the entire surface of the substrate. The requirement can be satisfied by allowing the contact to occur at one point in the length of from tens to hundreds of μm. Accordingly, most practically, the exposed area is formed to run zigzag in a length of from tens of μm to 1,000 μm and to have a width of about 1 μm.
The exposed area 1 is suitably formed to have two straight lines meeting at an angle of from 250 to 358�. In short, it is sufficient if the two straight lines do not run in parallel but run slightly at an angle with each other. If the angle is less than 250�, the apex angle of the mask part in a pseudo triangle shape is too large to bring out the effect of the present invention, whereas if the internal angle exceeds 358�, the good-quality growth film is excessively reduced in the width and the use range is limited.
EXAMPLES The present invention is described in greater detail below by referring to the Examples. Unless otherwise indicated, all parts, percents, ratios and the like are by weight.
Example 1 On the (0001) face of sapphire of a size of 20 mm�20 mm, a high temperature GaN epitaxial growth layer was laminated through a low temperature GaN buffer layer working out to a basal layer as follows.
In this case, the mask boundary angle was about 0.43�.
The cross section of this GaN grown layer was observed through transmission electron microscopy (TEM). Then, it was found that the GaN grown layer on the SiO2 film mask part 2 was greatly reduced in the dislocation density as compared with the layer grown on the exposed area and had a dislocation density of about 1.0�105/cm2. On the other hand, the dislocation density of the GaN grown layer on the exposed area 1 with no mask was about 108/cm2. The junction area 3 on the mask part 2 exclusive of the junction area on the broadest portion of the mask part 2, had substantially the same dislocation density as the grown layer on other portions of the mask part 2. The dislocation density of the junction area on the broadest portion of the mask part 2 was almost the same as that of the GaN grown layer on the exposed area 1.
Example 2 On the basal layer formed on the same type of substrate as described in Example 1, the same SiO2 film pattern as described in Example 1 was formed almost over the entire surface. Thereon, a GaN epitaxial growth film was grown by HVPE (hydride vapor phase epitaxial) growth method to have a thickness of 20 μm, as a result, the grown layers were joined on the mask part 2.
The cross section of this GaN grown layer was observed through TEM. Then, it was found that the GaN epitaxial layer grown on the SiO2 film mask part 2 was greatly reduced in the dislocation density as compared with the GaN layer grown on the exposed area 1 and had a dislocation density of about 1.5�105/cm2. On the other hand, the dislocation density of the GaN grown layer on the exposed area 1 with no mask was about 108/cm2. The junction area 3 on the mask part 2 exclusive of the junction area on the broadest portion of the mask part 2, had substantially the same dislocation density as the GaN grown layer on other portions of the mask part 2. The dislocation density of the junction area on the broadest portion of the mask part 2 was almost the same as that of the grown layer on the exposed area 1.
Example 3 On the basal layer formed on the same type of substrate as described in Example 1, a 0.02 μm-thick palladium film was formed by sputtering.
The cross section of this grown layer was observed through TEM. Then, it was found that the Al0.1Ga0.9N epitaxial growth layer grown on the SiO2 film mask part 2 was greatly reduced in the dislocation density as compared with the layer grown on the exposed area 1 and had a dislocation density of about 7.0�105/cm2. On the other hand, the dislocation density of the Al0.1Ga0.9N grown layer on the exposed area 1 with no mask was about 108/cm2. The junction area 3 on the mask part 2 exclusive of the junction area on the broadest portion of the mask part 2, had substantially the same dislocation density as the AlGaN grown layer on other portions of the mask part 2. The dislocation density of the junction area on the broadest portion of the mask part 2 was almost the same as that of the Al0.1Ga0.9N grown layer on the exposed area 1.
Example 4 On the basal layer formed on the same type of substrate as described in Example 1, a 0.2 μm-thick SiO2 film was formed by CVD.
Then, a pattern having linear exposed areas 1 and mask parts 2 shown in FIG. 4 was formed by conventional photolithography almost over the entire surface of a 20 mm-square substrate. At this time, the narrow portion 2 c of the mask part 2 had a width of 4 μm, the wide portion 2 d had a width of 8 μm, the distance between one bend point and the next bend point was 100 μm, and the exposed area 1 had a width of 1 μm. In this case, the mask boundary angle was about 2.29�. Thereon, GaN epitaxial growth films were grown by MOCVD to have a thickness of 12 μs, as a result, the GaN grown layers were joined on the mask part 2.
The cross section of this GaN grown layer was observed through TEM. Then, it was found that the GaN epitaxial growth layer on the SiO2 film mask part 2 was greatly reduced in the dislocation density as compared with the GaN layer grown on the exposed area 1 and had a dislocation density of about 1.3�105/cm2. On the other hand, the dislocation density of the GaN grown layer on the exposed area 1 with no mask was about 108/cm2. The junction area 3 on the mask part 2 exclusive of the junction area on the broadest portion of the mask part 2, had substantially the same dislocation density as the GaN grown layer on other portions of the mask part 2. The dislocation density of the junction area on the broadest portion of the mask part 2 was almost the same as that of the GaN grown layer on the exposed area 1.
Example 5 On the (0001) face of sapphire of a size of 20 mm�20 mm, a 0.2 μm-thick SiO2 film was formed by CVD. A pattern having linear exposed areas 1 and mask parts 2 shown in FIG. 3 was formed in the SiO2 film by conventional photolithography almost over the entire surface of the substrate. At this time, the narrow portion 2 c of the mask part 2 had a width of 3 μm, the wide portion 2 d had a width of 6 μm, the distance between one bend point and the next bend point was 400 μm, and the exposed area 1 had a width of 1 μm.
The cross section of this GaN grown layer was observed through TEM. Then, it was found that the GaN grown layer on the SiO2 film mask part 2 was greatly reduced in the dislocation density as compared with the layer grown on the exposed area and had a dislocation density of about 1.0�108/cm2. On the other hand, the dislocation density of the GaN grown layer on the exposed area 1 with no mask was about 1�1010/cm2. The junction area 3 on the mask part 2 exclusive of the junction area on the broadest portion of the mask part 2, had substantially the same dislocation density as the grown layer on other portions of the mask part 2. The dislocation density of the junction area on the broadest portion of the mask part 2 was almost the same as that of the GaN grown layer on the exposed area 1.
Example 6 On the (0001) face of sapphire of a size of 20 mm�20 mm, a high temperature GaN epitaxial growth layer was laminated through a low temperature GaN buffer layer working out to a basal layer as follows.
In this case, the mask boundary angle was about 11.3�.
The cross section of this GaN grown layer was observed through TEM. Then, it was found that the GaN grown layer on the SiO2 film mask part 2 was greatly reduced in dislocation density as compared with the layer grown on the exposed area and had a dislocation density of about 1.5�105/cm2. On the other hand, the dislocation density of the GaN grown layer on the exposed area 1 with no mask was about 2�108/cm2. The growth front 3 on the mask part 2 exclusive of the junction area on the broadest portion of the mask part 2, had substantially the same dislocation density as the grown layer on other portions of the mask part 2. The dislocation density of the junction area on the broadest portion of the mask part 2 was almost the same as that of the GaN grown layer on the exposed area 1.
Example 7 On the 20 mmφ Si (100) face, a 2 μm-thick GaAs buffer layer working out to a basal layer was laminated by a conventional MBE method.
On the thus-formed basal layer, a 0.2 μm-thick SiO2 film was formed by CVD. In this SiO2 film, a back wedge-shape exposed area 1 shown in FIG. 8 was formed by conventional photolithography almost over the entire surface of the substrate. At this time, the long side A of the exposed area 1 had a length of 140 μm, the short side B meeting the long side A at right angles had a length of 100 μm, the sides C1 and C2 of the back wedge had a length of 120 μm, the side C and the side A were connected through a 5 μm-length side b meeting the side A at right angles, and the internal angle defined by the sides C1 and C2 was about 315�. This back wedge-shape exposed area 1 was formed by conventional photolithography over the entire surface of the substrate.
Example 8 On the (0001) face of sapphire of a size of 20 mm�20 mm, a high temperature GaN epitaxial growth layer was laminated through a low temperature GaN buffer layer working out to a basal layer as follows.
On the above-described basal layer, a 0.2 μm-thick SiO2 film was formed by CVD. In this SiO2 film, a back wedge-shape exposed area 1 shown in FIG. 9 was formed by conventional photolithography almost over the entire surface of the substrate. At this time, the long side A of the exposed area had a length of 40 μm. the short side B meeting the long side A at right angles had a length of 30 μm, the sides C of the back wedge had a length of 20 μm, the side C and the side A were connected through a 2 μm-length side b meeting the side A at right angles, and the internal angle defined by the sides C1 and C2 was about 308�. This back wedge-shape exposed area 1 was formed by conventional photolithography over the entire surface of the substrate.
The cross section of this GaN grown layer was observed through TEM. Then, it was found that the GaN grown layer on the SiO2 film mask part 2 was greatly reduced in dislocation density as compared with the layer grown on the exposed area and had a dislocation density of about 1.0�105/cm2. On the other hand, the dislocation density of the GaN grown layer on the exposed area 1 with no mask was about 108/cm2. The growth front 3 on the mask part 2 had substantially the same dislocation density as the grown layer on other portions of the mask part 2. The dislocation density of the junction area on the broadest portion of the mask part 2 was almost the same as that of the GaN grown layer on the exposed area
Example 9 On the 20 mmφ Si (100) face, a 2 μm-thick GaAs buffer layer working out to a basal layer was laminated by a conventional MBE method.
On the thus-formed basal layer, a 0.2 μm-thick SiO2 film was formed by CVD. In this SiO2 film, an exposed area 1 consisting of a pair of two congruent right-angled triangles disposed in a line symmetric manner with each other shown in FIG. 10 was formed by conventional photolithography almost over the entire surface of the substrate. At this time, the long sides A1 and A2 of the right-angled triangles had a length of 120 μm, the short sides B1 and B2 meeting the long sides at right angles had a length of 60 μm, the hypotenuses C1 and C2 had a length of 134 μm, and the angle defined by the sides C1 and C2 was about 60�.
Example 10 On the (0001) face of sapphire of a size of 20 mm�20 mm, a high temperature GaN epitaxial growth layer was laminated through a low temperature GaN buffer layer working out to a basal layer as follows.
On the above-described basal layer, a 0.2 μm-thick SiO2 film was formed by CVD. In this SiO2 film, an exposed area consisting of a pair of two congruent right-angled triangles disposed in a line symmetric manner with each other shown in FIG. 10 was formed by conventional photolithography almost over the entire surface of the substrate. At this time, the long sides A1 and A2 of the right-angled triangles had a length of 40 μm, the short sides B1 and B2 meeting the long sides at right angles had a length of 10 μm, the hypotenuses C1 and C2 had a length of 41 μm, and the angle defined by the sides C1 and C2 was about 37�.
The cross section of this GaN grown layer was observed through TEM. Then, it was found that the GaN grown layer on the SiO2 film mask part 2 was greatly reduced in the dislocation density as compared with the layer grown on the exposed area and had a dislocation density of about 1.0�105/cm2. On the other hand, the dislocation density of the GaN grown layer on the exposed area 1 with no mask was about 108/cm2. The growth front 3 on the mask part 2 had substantially the same dislocation density as the grown layer on other portions of the mask part 2.
Comparison Example as to Mask Boundary Angle The same GaN laminated sapphire substrate as described in Example 1 was used.
On this substrate, a pattern shown in FIG. 6 was formed by conventional photolithography over the entire surface of the 20 mm-square substrate. In this case, the mask boundary angle was 0.17�. Thereon, GaN epitaxial growth layers were grown by MOCVD to have a thickness of 20 μm, as a result, the GaN grown layers were joined on the mask part 2.
The cross section of this GaN grown layer was observed through TEM. Then, the GaN epitaxial layer grown on the SiO2 film mask part 2 was greatly reduced in dislocation density as compared with the GaN layer grown on the exposed area 1 and had a dislocation density of about 1.2�105/cm2. On the other hand, the GaN grown layer on the exposed area 1 with no mask had a dislocation density of about 108/cm2. However, the junction area on the mask part 2 had a high dislocation density of the same level as the GaN grown layer on the exposed area 1.
Epitaxial layers were grown in the same manner as above by varying the mask pattern. As a result, it was found that when the mask boundary angle was less than 0.3�, the dislocation density of the junction area on the mask part 2 was partly higher than the dislocation density of portions other than the junction area, revealing that the effect of the present invention is limited.
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