Source: https://patents.google.com/patent/US10313107B2/en
Timestamp: 2019-09-18 02:20:09
Document Index: 167900961

Matched Legal Cases: ['application No. 2009', 'Application No. 2012', 'Application No. 18165550', 'Application No. 16191616', 'Application No. 08744319', 'Application No. 14169143', 'Application No. 14169143', 'Application No. 200880006495', 'Application No. 201310110523', 'Application No. 2017', 'Application No. 18165550', 'Application No. 200810096342', 'Application No. 200880006495', 'Application No. 200880006495', 'Application No. 200880006495', 'Application No. 201310110523', 'Application No. 201310110523', 'Application No. 201310110523', 'Application No. 201310110523', 'Application No. 10', 'Application No. 10', 'Application No. 2009', 'Application No. 2009', 'Application No. 2009', 'Application No. 2012', 'Application No. 2012', 'Application No. 2013', 'Application No. 2015', 'Application No. 2015', 'Application No. 2015', 'Application No. 2015', 'Application No. 10', 'Application No. 97111091', 'Application No. 08744319', 'Application No. 0804870', 'Application No. 0804870']

US10313107B2 - Flexible architecture and instruction for advanced encryption standard (AES) - Google Patents
US10313107B2
US10313107B2 US14/984,616 US201514984616A US10313107B2 US 10313107 B2 US10313107 B2 US 10313107B2 US 201514984616 A US201514984616 A US 201514984616A US 10313107 B2 US10313107 B2 US 10313107B2
US14/984,616
US20160248580A1 (en
2013-08-29 Priority to US14/014,091 priority patent/US20140003602A1/en
2014-12-16 Priority to US14/572,620 priority patent/US9634830B2/en
2015-12-30 Application filed by Intel Corp filed Critical Intel Corp
2015-12-30 Priority to US14/984,616 priority patent/US10313107B2/en
2016-08-25 Publication of US20160248580A1 publication Critical patent/US20160248580A1/en
2019-06-04 Publication of US10313107B2 publication Critical patent/US10313107B2/en
FIG. 8 illustrates an embodiment of an aes round instruction 830 with immediate byte that may be used to generate round keys and perform encryption and decryption. Instead of the aes instruction set shown in Table 1, a single aes round instruction is provided to perform the functions of the aes instruction set. The particular function to be performed by the single aes instruction is encoded in bits in the immediate byte (key13 select13 modifier) 832. The immediate byte allows the aes round instruction to be expanded to add new features instead of creating a plurality of new instructions with each instruction having a unique operation code.
dest :=aes13 key13 round (source2, source1), key13 select13 modifier.
The aes 13 key13 round instruction is issued to a particular execution unit 210 based on port number 833 in order to perform an AES encrypt or decrypt operation. In the embodiment shown, port number 4 is the designated execution port for the AES round instruction. The execution unit 210 is divided into many parallel ports (super-scalar). However, not all ports are equal. Some ports have specialized resources such as a large integer multiplier, or floating-point multiplier or divider. Simpler and more common instructions such as addition, subtraction and exclusive OR are supported on multiple ports for maximum performance. Thus for each instruction or micro-operation, issue control logic determines the port to which to issue the micro-operation/instruction. In this embodiment, the aes instruction is always issued to port number 4. However, in other embodiments other port numbers may be used.
Referring to FIG. 8, the dest stores 128 bits of expanded key for round N, source2 stores 128 bits of expanded key for round N−1, and source1 stores 128 bits of expanded key for round N−2. The key_select—modifier 832 is an 8-bit immediate value used to provide current round number (N), direction of operation (encrypt/decrypt) and AES key size. For AES-128, source1 is not needed and is ignored. The execution unit 210 is AES unit and no flags (integer 834 or floating point 836) are used.
a level 1 (L1) instruction cache to store a plurality of instructions, the plurality of instructions to include a plurality of Advanced Encryption Standard (AES) instructions of an instruction set of the processor, the instruction set of the processor including a Single Instruction Multiple Data (SIMD) instruction set, wherein the plurality of AES instructions include a first AES instruction for a round of an AES decryption operation, a second AES instruction for a final round of the AES decryption operation, a third AES instruction for a round of an AES encryption operation, and a fourth AES instruction for a final round of the AES encryption operation, and wherein the plurality of AES instructions each comprise a different opcode;
an L1data cache;
decode logic to decode instructions including the first AES instruction;
a first 128-bit source register to store a round key to be used for the round of the AES decryption operation;
a second 128-bit source register to store input data to be decrypted by the round of the AES decryption operation;
a plurality of ports, each associated with one or more corresponding execution resources, to support parallel execution of integer and floating point operations;
an execution unit including AES execution logic to execute the first AES instruction of the instruction set of the processor to perform the round of the AES decryption operation,
wherein the execution unit is to execute microcode, determined from the decode of the first AES instruction, to execute the first AES instruction, the AES decryption operation to use the round key from the first 128-bit source register to decrypt the input data from the second 128-bit source register and to store a result of the round of the AES decryption operation in a 128-bit destination register,
wherein the round of the AES decryption operation is to include:
a substitution operation to be performed on the input data, the substitution operation to use an inverse substitution box (S-box) lookup;
an inverse Shift Rows operation;
an inverse Mix Columns operation; and
an Add Round Key operation in which an exclusive OR function is to use data from the round key; and
a retirement unit;
a system memory comprising a multiple data rate dynamic random access memory coupled to the processor over one or more interconnects;
one or more storage devices coupled to the processor; and
an input/output (I/O) controller to couple the processor to one or more devices, the one or more devices to include the one or more storage devices, wherein at least one of the one or more storage devices is to be coupled to the processor over at least one Serial Attached Small Computer System Interface (SAS).
2. The system of claim 1, wherein the one or more storage devices are to be arranged as a Redundant Array of Independent Disks (RAID).
3. The system of claim 1, further comprising at least one network interface coupled to the processor to process data packets.
4. The system of claim 1, further comprising at least one network interface coupled to the processor to process data packets, and wherein the one or more storage devices are to be arranged as a Redundant Array of Independent Disks (RAID).
5. The system of claim 1, wherein the processor is a general-purpose processor, and wherein the plurality of AES instructions include more than four AES instructions that each comprise a different opcode.
a decode unit to decode instructions including the first AES instruction;
an execution unit to perform the first AES instruction of the instruction set of the processor to perform the round of the AES decryption operation, wherein the execution unit is to execute microcode, determined from the decode of the first AES instruction, to execute the first AES instruction, the AES decryption operation to use the round key from the first 128-bit source register to decrypt the input data from the second 128-bit source register and to store a result of the round of the AES decryption operation in a 128-bit destination register,
7. The system of claim 6, wherein the one or more storage devices are to be arranged as a Redundant Array of Independent Disks (RAID).
8. The system of claim 6, further comprising at least one network interface coupled to the processor to process data packets.
9. The system of claim 6, further comprising at least one network interface coupled to the processor to process data packets, and wherein the one or more storage devices are to be arranged as a Redundant Array of Independent Disks (RAID).
10. The system of claim 6, wherein the processor is a general-purpose processor, and wherein the plurality of AES instructions include more than four AES instructions that each comprise a different opcode.
11. The processor of claim 6, wherein the execution unit is to have a different execution port to perform the first AES instruction than one or more other execution ports that are to be used for AES key scheduling operations.
a level 1 (L1) instruction cache to store a plurality of instructions of an instruction set of the processor, the instruction set of the processor including a Single Instruction Multiple Data (SIMD) instruction set, the plurality of instructions to include a first Advanced Encryption Standard (AES) instruction, wherein the first AES instruction has a bit with a value of one to indicate that encryption is to be performed instead of a value of zero which would indicate that decryption is to be performed;
a first 128-bit source register to store a round key to be used for a round of an AES decryption operation;
US14/984,616 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (AES) Active US10313107B2 (en)
US14/014,091 US20140003602A1 (en) 2007-03-28 2013-08-29 Flexible Architecture and Instruction for Advanced Encryption Standard (AES)
US14/572,620 US9634830B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US14/984,616 US10313107B2 (en) 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (AES)
US14/572,620 Continuation US9634830B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US20160248580A1 US20160248580A1 (en) 2016-08-25
US10313107B2 true US10313107B2 (en) 2019-06-04
US11/729,199 Active 2030-04-30 US8538015B2 (en) 2007-03-28 2007-03-28 Flexible architecture and instruction for advanced encryption standard (AES)
US14/014,091 Pending US20140003602A1 (en) 2007-03-28 2013-08-29 Flexible Architecture and Instruction for Advanced Encryption Standard (AES)
US14/572,423 Active US9647831B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US14/572,565 Active US9634829B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US14/572,540 Active US9634828B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US14/572,593 Active US9654281B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US14/572,578 Active US9641319B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US14/572,545 Active US10181945B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US14/572,607 Active US10270589B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US14/572,602 Active US9654282B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US14/572,620 Active US9634830B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US14/572,584 Active US9641320B2 (en) 2007-03-28 2014-12-16 Flexible architecture and instruction for advanced encryption standard (AES)
US14/872,556 Pending US20160197720A1 (en) 2007-03-28 2015-10-01 Flexible architecture and instruction for advanced encryption standard (aes)
US14/872,584 Active US10291394B2 (en) 2007-03-28 2015-10-01 Flexible architecture and instruction for advanced encryption standard (AES)
US14/984,601 Active US10256971B2 (en) 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (AES)
US14/984,686 Active US10171232B2 (en) 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (AES)
US14/984,656 Active US10187201B2 (en) 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (AES)
US14/984,647 Active US10263769B2 (en) 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (AES)
US14/984,663 Active US10171231B2 (en) 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (AES)
US14/984,629 Active US10256972B2 (en) 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (AES)
US14/984,673 Active US10158478B2 (en) 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (AES)
US14/984,637 Pending US20160119126A1 (en) 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (aes)
US14/984,588 Active US10164769B2 (en) 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (AES)
US14/984,616 Active US10313107B2 (en) 2007-03-28 2015-12-30 Flexible architecture and instruction for advanced encryption standard (AES)
TWI407307B (en) * 2009-06-18 2013-09-01 Univ Ishou
TWI397300B (en) * 2009-09-25 2013-05-21 Univ Shu Te
US20040039896A1 (en) 2002-08-26 2004-02-26 Pechanek Gerald George Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors
US20040082632A1 (en) 2000-01-18 2004-04-29 Howarth Jonathan N. Methods for microbiological control in aqueous systems
US20060023875A1 (en) 2004-07-30 2006-02-02 Graunke Gary L Enhanced stream cipher combining function
TWI268449B (en) 2002-04-12 2006-12-11 Intel Corp Method, apparatus, system, and related machine-readable medium for microcode patch authentication
TWI269169B (en) 2001-12-04 2006-12-21 Microsoft Corp Methods and systems for cryptographically protecting secure content
2017-01-06 JP JP2017001149A patent/JP2017083879A/en active Granted
KR20050078271A (en) 2004-01-29 2005-08-05 삼성전자주식회사 Hardware cryptographic engine and method improving power consumption and operation speed
Advisory Action from U.S. Appl. No. 14/572,602, dated Dec. 1, 2016, 4 pages.
American National Standard Institute, "The Elliptic Curve Digital Signature Algorithm (ECDSA)", American National Standard for Financial Services, Accredited Standards Committee X9, Inc. Financial Services, X9.62/2005-Draft, Nov. 14, 2005, 163 pages.
Astarloa, et al., "Multi-architectural 128 bit AES-CBC Core based an Open-Source Hardware AES Implementations for Secure Industrial Communications", International Conference on Communication Technology, ICCT '06, 2006, 5 pages.
CERTICOM, "SEC 1: Elliptic Curve Cryptography", Standards for Efficient Cryptography, Version 1.0, Sep. 20, 2000, 97 pages.
Decision of rejection from foreign counterpart Japanese application No. 2009-552935, dated Sep. 16, 2014, 19 pages.
Decision of Rejection from foreign counterpart Japanese Patent Application No. 2012-226077, dated Sep. 30, 2014, 20 pages.
Extended European Search Report for Application No. 18165550.7, dated May 14, 2018, 9 pages.
Extended European Search Report received for European Patent Application No. 16191616.8, dated Feb. 8, 2017, 9 pages.
Extended European Search report received for the European Patent Application No. 08744319.8, dated Feb. 16, 2011, 9 pages.
Extended European Search Report received on European Patent Application No. 14169143.6, dated Feb. 23, 2015, 8 pages.
Final Office Action from U.S. Appl. No. 14/014,091, dated Mar. 22, 2018, 55 pages.
Final Office Action from U.S. Appl. No. 14/872,556, dated May 17, 2018, 42 pages.
Final Office Action from U.S. Appl. No. 14/872,584, dated May 2, 2018, 52 pages.
Final Office Action from U.S. Appl. No. 14/984,637, dated May 2, 2018, 43 pages.
Final Office Action Received for the U.S. Appl. No. 14/572,540, dated May 6, 2016, 11 pages.
Final Office Action Received for the U.S. Appl. No. 14/572,545, dated May 4, 2016, 17 pages.
Final Office Action Received for the U.S. Appl. No. 14/572,565, dated May 5, 2016, 14 pages.
Final Office Action Received for the U.S. Appl. No. 14/572,578, dated May 13, 2016, 14 pages.
Final Office Action Received for the U.S. Appl. No. 14/572,607, dated May 5, 2016, 13 pages.
Final Office Action Received for the U.S. Appl. No. 14/572,620, dated May 16, 2016, 14 pages.
Final Office Action received for U.S. Appl. No. 11/729,199, dated Oct. 26, 2010, 17 Pages.
Final Office Action received for U.S. Appl. No. 14/014,091, dated Dec. 30, 2016, 32 Pages.
Final Office Action received for U.S. Appl. No. 14/014,091, dated Jun. 26, 2015, 10 pages.
Final Office Action received for U.S. Appl. No. 14/572,423, dated May 19, 2016, 16 pages.
Final Office Action received for U.S. Appl. No. 14/572,545, dated May 11, 2017, 13 pages.
Final Office Action received for U.S. Appl. No. 14/572,584, dated May 31, 2016, 18 pages.
Final Office Action received for U.S. Appl. No. 14/572,602, dated Jun. 2, 2016, 13 pages.
Final Office Action received for U.S. Appl. No. 14/572,607, dated Aug. 30, 2017, 13 pages.
Final Office Action received for U.S. Appl. No. 14/872,556, dated Feb. 8, 2017, 15 pages.
Final Office Action received for U.S. Appl. No. 14/872,584, dated Feb. 8, 2017, 15 pages.
Final Office Action received for U.S. Appl. No. 14/984,588, dated Feb. 10, 2017, 14 pages.
Final Office Action received for U.S. Appl. No. 14/984,601, dated Feb. 9, 2017, 15 pages.
Final Office Action received for U.S. Appl. No. 14/984,629, dated Feb. 9, 2017, 15 pages.
Final Office Action received for U.S. Appl. No. 14/984,637, dated Feb. 9, 2017, 15 pages.
Final Office Action received for U.S. Appl. No. 14/984,647, dated Feb. 10, 2017, 15 pages.
Final Office Action received for U.S. Appl. No. 14/984,656, dated Mar. 6, 2017, 15 pages.
Final Office Action received for U.S. Appl. No. 14/984,663, dated Mar. 6, 2017, 15 pages.
Final Office Action received for U.S. Appl. No. 14/984,673, dated Mar. 6, 2017, 14 pages.
Final Office Action received for U.S. Appl. No. 14/984,686, dated Mar. 6, 2017, 15 pages.
Gonzalez, R, "XTENSA: A Configurable and extensible processor", IEEE Micro, vol. 20, Issue 2, Mar.-Apr. 2000, pp. 60-70.
Intention to Grant a Patent for Application No. 14169143.6, dated May 22, 2018, 39 pages.
International Preliminary Report on Patentability and Written Opinion received for PCT Patent Application No. PCT/US2008/058128, dated Sep. 29, 2009, 5 pages.
International Search Report and Written Opinion received for PCT Patent Application No. PCT/US2008/058128, dated Jul. 31, 2008, 10 pages.
NIST, "(Specification for the) Advanced Encryption Standard (AES)", Federal Information Processing Standards Publication 197, Nov. 26, 2001, 51 pages.
Non Final Office Action Received for the U.S. Appl. No. 14/572,545, dated Nov. 28, 2016, 15 Pages.
Non Final Office Action Received for the U.S. Appl. No. 14/572,607, dated Nov. 23, 2016, 13 Pages.
Non Final Office Action received for U.S. Appl. No. 14/014,091, dated Apr. 14, 2016, 42 pages.
Non Final Office Action received for U.S. Appl. No. 14/572,593, dated Apr. 28, 2016, 15 pages.
Non Final Office Action received for U.S. Appl. No. 14/572,620, dated Sep. 15, 2015, 11 pages.
Non Final Office Action received for U.S. Appl. No. 14/872,556, dated Jun. 30, 2016, 8 pages.
Non Final Office Action received for U.S. Appl. No. 14/872,584, dated Jun. 27, 2016, 8 pages.
Non Final Office Action received for U.S. Appl. No. 14/984,588, dated Jun. 27, 2016, 8 pages.
Non Final Office Action received for U.S. Appl. No. 14/984,601, dated Jun. 27, 2016, 8 pages.
Non Final Office Action received for U.S. Appl. No. 14/984,629, dated Jul. 6, 2016, 9 pages.
Non Final Office Action received for U.S. Appl. No. 14/984,637, dated Jul. 5, 2016, 9 pages.
Non Final Office Action received for U.S. Appl. No. 14/984,647, dated Jul. 5, 2016, 9 pages.
Non Final Office Action received for U.S. Appl. No. 14/984,656, dated Jul. 19, 2016, 12 pages.
Non Final Office Action received for U.S. Appl. No. 14/984,663, dated Jul. 29, 2016, 13 pages.
Non Final Office Action received for U.S. Appl. No. 14/984,673, dated Jul. 29, 2016, 13 pages.
Non Final Office Action received for U.S. Appl. No. 14/984,686, dated Jul. 29, 2016, 13 pages.
Non-Final Office Action from U.S. Appl. No. 14/572,545, dated Dec. 12, 2017, 38 pages.
Non-Final Office Action from U.S. Appl. No. 14/572,607, dated Mar. 22, 2018, 39 pages.
Non-Final Office Action from U.S. Appl. No. 14/984,601, dated Apr. 4, 2018, 37 pages.
Non-Final Office Action from U.S. Appl. No. 14/984,629, dated Apr. 16, 2018, 36 pages.
Non-Final Office Action from U.S. Appl. No. 14/984,637, dated Jan. 15, 2019, 38 pages.
Non-Final Office Action from U.S. Appl. No. 14/984,647, dated Apr. 5, 2018, 35 pages.
Non-Final Office Action received for U.S. Appl. No. 11/729,199, dated Apr. 13, 2010, 18 Pages.
Non-Final Office Action received for U.S. Appl. No. 11/729,199, dated Mar. 30, 2012, 21 Pages.
Non-Final Office Action received for U.S. Appl. No. 11/729,199, dated Nov. 9, 2012, 21 Pages.
Non-Final Office Action received for U.S. Appl. No. 14/014,091, dated Aug. 2, 2017, 28 pages.
Non-Final Office Action received for U.S. Appl. No. 14/014,091, dated Dec. 3, 2014, 10 pages.
Non-Final Office Action received for U.S. Appl. No. 14/572,423, dated Nov. 24, 2015, 14 pages.
Non-Final Office Action received for U.S. Appl. No. 14/572,540, dated Nov. 6, 2015, 17 pages.
Non-Final Office Action received for U.S. Appl. No. 14/572,545, dated Nov. 19, 2015, 18 pages.
Non-Final Office Action received for U.S. Appl. No. 14/572,565, dated Nov. 10, 2015, 15 pages.
Non-Final Office Action received for U.S. Appl. No. 14/572,578, dated Nov. 9, 2015, 16 pages.
Non-Final Office Action received for U.S. Appl. No. 14/572,584, dated Dec. 3, 2015, 16 pages.
Non-Final Office Action received for U.S. Appl. No. 14/572,602, dated Dec. 3, 2015, 15 pages.
Non-Final Office Action received for U.S. Appl. No. 14/572,607, dated Nov. 6, 2015, 15 pages.
Non-Final Office Action received for U.S. Appl. No. 14/872,556, dated Sep. 13, 2017, 16 pages.
Non-Final Office Action received for U.S. Appl. No. 14/872,584, dated Sep. 14, 2017, 17 pages.
Non-Final Office Action received for U.S. Appl. No. 14/984,588, dated Sep. 25, 2017, 15 pages.
Non-Final Office Action received for U.S. Appl. No. 14/984,637, dated Sep. 22, 2017, 16 pages.
Non-Final Office Action received for U.S. Appl. No. 14/984,656, dated Oct. 12, 2017, 24 pages.
Non-Final Office Action received for U.S. Appl. No. 14/984,663, dated Oct. 13, 2017, 25 pages.
Non-Final Office Action received for U.S. Appl. No. 14/984,673, dated Nov. 16, 2017, 24 pages.
Non-Final Office Action received for U.S. Appl. No. 14/984,686, dated Oct. 24, 2017, 24 pages.
Notice of Allowance from U.S. Appl. No. 14/014,091, dated Oct. 24, 2018, 21 pages.
Notice of Allowance from U.S. Appl. No. 14/572,545, dated Aug. 27, 2018, 17 pages.
Notice of Allowance from U.S. Appl. No. 14/572,607, dated Nov. 14, 2018, 14 pages.
Notice of Allowance from U.S. Appl. No. 14/984,588, dated Jul. 27, 2018, 12 pages.
Notice of Allowance from U.S. Appl. No. 14/984,656, dated Aug. 27, 2018, 12 pages.
Notice of Allowance from U.S. Appl. No. 14/984,663, dated Aug. 10, 2018, 12 pages.
Notice of Allowance from U.S. Appl. No. 14/984,673, dated Aug. 6, 2018, 12 pages.
Notice of Allowance from U.S. Appl. No. 14/984,686, dated Aug. 10, 2018, 12 pages.
Notice of Allowance received for Chinese Patent Application No. 200880006495.1, dated Jan. 15, 2013, 2 Pages of Notice and 2 Pages of English Translation.
Notice of Allowance received for Chinese Patent Application No. 201310110523.7, dated Aug. 18, 2017, 4 pages of Chinese Notice of Allowance including 2 pages of English Translation.
Notice of Allowance received for the U.S. Appl. No. 14/572,540, dated Dec. 19, 2016, 8 Pages.
Notice of Allowance received for the U.S. Appl. No. 14/572,565, dated Dec. 15, 2016, 9 Pages.
Notice of Allowance received for the U.S. Appl. No. 14/572,578, dated Dec. 23, 2016, 8 Pages.
Notice of Allowance received for the U.S. Appl. No. 14/572,620, dated Dec. 15, 2016, 10 Pages.
Notice of Allowance received for U.S. Appl. No. 11/729,199, dated May 28, 2013, 17 Pages.
Notice of Allowance received for U.S. Appl. No. 14/572,423, dated Dec. 30, 2016, 13 Pages.
Notice of Allowance received for U.S. Appl. No. 14/572,584, dated Dec. 21, 2016, 14 Pages.
Notice of Allowance received for U.S. Appl. No. 14/572,593, dated Dec. 9, 2016, 7 pages.
Notice of Allowance received for U.S. Appl. No. 14/572,602, dated Jan. 5, 2017, 11 Pages.
Notification of Reasons for Refusal from foreign counterpart Japanese patent Application No. 2017-001149, dated Apr. 9, 2018, 8 pages.
Office Action from foreign counterpart European Patent Application No. 18165550.7, dated Aug. 20, 2018, 6 pages.
Office Action Received for Chinese Patent Application No. 200810096342.2, dated Apr. 1, 2010, 4 pages of English Translation only.
Office Action received for Chinese Patent Application No. 200880006495.1, dated Apr. 25, 2011, 8 Pages of Office Action and 8 Pages of English Translation.
Office Action received for Chinese Patent Application No. 200880006495.1, dated Jun. 19, 2012, 4 Pages of Office Action including 1 page of English Translation.
Office Action received for Chinese Patent Application No. 200880006495.1, dated Nov. 22, 2011, 11 Pages of Office Action and 11 Pages of English Translation.
Office Action received for Chinese Patent Application No. 201310110523.7, dated Apr. 8, 2015, 9 pages of Chinese Office Action only.
Office Action received for Chinese Patent Application No. 201310110523.7, dated Jan. 14, 2016, 7 pages of English Translation and 5 pages of Chinese Office Action.
Office Action received for Chinese Patent Application No. 201310110523.7, dated May 17, 2017, 10 pages of Chinese Office Action including 5 pages of English Translation.
Office Action received for Chinese Patent Application No. 201310110523.7, dated Sep. 13, 2016, 8 Pages of Chinese Office Action including 4 Pages of English Translation.
Office Action received for German Patent Application No. 10 2008 014 359.6-31, dated Jul. 21, 2010, 2 pages of English Translation only.
Office Action received for German Patent Application No. 10 2008 014 359.6-31, dated May 15, 2009, 6 pages of English translation only.
Office Action received for Japanese Patent Application No. 2009-552935, dated Apr. 16, 2013, 8 pages of Office Action including 4 pages of English Translation.
Office Action received for Japanese patent Application No. 2009-552935, dated Jan. 10, 2012, 3 pages of Office Action including 4 pages of English Translation.
Office Action received for Japanese patent Application No. 2009-552935, dated Jun. 12, 2012, 8 Pages of office Action including 4 pages of English Translation.
Office Action received for Japanese Patent Application No. 2012-226077, dated Jun. 25, 2013, 4 Pages of Office Action and 3 pages of English Translation.
Office Action received for Japanese Patent Application No. 2012-226077, dated Mar. 12, 2013, 7 Pages of Office Action including 3 pages of English Translation.
Office Action received for Japanese Patent Application No. 2013-222466, dated Aug. 26, 2014, 4 Pages of Office Action and 4 Pages of English Translation.
Office Action received for Japanese Patent Application No. 2015-012125, dated Dec. 15, 2015, 3 pages of English Translation and 3 pages of Japanese Office Action.
Office Action received for Japanese Patent Application No. 2015-012125, dated Sep. 6, 2016, 7 pages of Japanese Office Action including 3 pages of English Translation.
Office Action received for Japanese Patent Application No. 2015-049638, dated Dec. 15, 2015, 4 pages of English Translation and 5 pages of Japanese Office Action.
Office Action received for Japanese Patent Application No. 2015-049638, dated Sep. 6, 2016, 7 pages of Japanese Office Action including 3 pages of English Translation.
Office Action received for Korean Patent Application No. 10-2008-24067, dated Feb. 18, 2010, 3 pages of English Translation and 5 pages of Korean Office Action.
Office Action received for Taiwan Patent Application No. 97111091, dated Jan. 2, 2012, 10 Pages.
Office Action received for the European Patent Application No. 08744319.8, dated Feb. 24, 2015, 7 pages.
Office Action received for United Kingdom Patent Application No. 0804870.4, dated Apr. 8, 2009, 2 pages.
Office Action received for United Kingdom Patent Application No. 0804870.4, dated Jun. 25, 2008, 7 pages.
Tillich, et aL, "An Instruction Set Extension for Fast and Memory-Efficient AES Implementation", International Federation for Information Processing 2005, Communications and Multimedia Security, CMS, Lecture Notes in computer Science (LNCS), vol. 3677, 2005, pp. 11-21.
Tomonari, H., "Examining a 'Nay to realize AES Encryption Circuit", Design Wave Magazine, CQ Publishing Co., Ltd., Dec. 1, 2003, pp. 154-160.
EP2132899A1 (en) 2009-12-16