Source: https://patents.google.com/patent/US6747888B2/en
Timestamp: 2018-09-21 04:47:30
Document Index: 214496781

Matched Legal Cases: ['application No. 09', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 10', 'application No. 09', 'application No. 09']

US6747888B2 - High speed data bus - Google Patents
US6747888B2
US6747888B2 US10017257 US1725701A US6747888B2 US 6747888 B2 US6747888 B2 US 6747888B2 US 10017257 US10017257 US 10017257 US 1725701 A US1725701 A US 1725701A US 6747888 B2 US6747888 B2 US 6747888B2
Expired - Lifetime, expires 2018-04-30
US10017257
US20020041522A1 (en )
This application is a divisional of, and incorporates by reference in its entirety U.S. application No. 09/015,845, titled “HIGH SPEED DATA BUS.” This Application is related to and incorporates by reference, in each of their entirety, the following patent applications that each have been filed on even date: U.S. application No. 10/021,388, U.S. application No. 10/017,255, U.S. application No. 10/017,826, and U.S. application No. 10/017,256. This application is also related to U.S. patent application No. 10/439,593, titled “HIGH SPEED DATA BUS,” filed May 16, 2003; U.S. patent application No. 10/615,325, titled “METHOD FOR BUS CAPACITANCE REDUCTION,” filed Jul. 7, 2003; U.S. patent application No. 10/615,326, titled METHOD FOR BUS CAPACITANCE REDUCTION,” filed Jul. 7, 2003; U.S. application No. 09/782,476, titled “METHOD FOR BUS CAPACITANCE REDUCTION,” filed Feb. 13, 2001; and U.S. patent application No. 09/015,376, titled “METHOD FOR BUS CAPACITANCE REDUCTION,” filed Jan. 29, 1998.
FIG. 3 illustrates one embodiment of a computing system incorporating the invention. As shown in this Figure, the system includes a host processor 20 which in one embodiment of the invention comprises a microprocessor such as the X86 or Pentium(TM) families from Intel Corporation. Any digital data processing circuitry may, however, comprise the host processor 20 of FIG. 3, including digital signal processors, microcontrollers, multi-processor systems, etc. The host processor 20 may interface with a memory controller 22. The memory controller interface circuitry includes a data bus 24 for the transfer of digital data between the memory controller 22 and the host processor 20.
Additional circuitry including control and address buses also connect between the host processor 20 and memory controller 22, but these are not illustrated in FIG. 3.
a first plurality of electrical contacts arranged on said printed circuit board to connect to a data bus;
a second plurality of electrical contacts arranged on said printed circuit board to connect to memory control signals for performing memory access cycles, said memory control signals including a row address strobe signal and a column address strobe signal;
at least one memory integrated circuit attached to said printed circuit board and receiving one or more memory control signals from said second plurality of electrical contacts;
a state decoder circuit separate from said memory integrated circuit having an input coupled to at least some of said memory control signals and an output, wherein said state decoder circuit is configured to have an output signal having a first state during a memory access and a second state in the absence of a memory access; and
at least one switch having a plurality of inputs connected to corresponding ones of said first plurality of electrical contacts, and a plurality of outputs connected to said at least one memory integrated circuit so as to couple said data bus from said first plurality of electrical contacts to said memory integrated circuit, said at least one switch having an additional input coupled to said state decoder circuit output, and responsive to said state decoder circuit output to decouple said memory circuit from said data bus when no memory access cycle is being performed.
2. The memory module of claim 1, wherein the memory integrated circuit includes synchronous-DRAM memory.
3. The memory module of claim 1, wherein the switch, the memory integrated circuit, and a memory controller each collectively reside within a single integrated circuit.
5. The printed circuit board of claim 4, wherein the memory integrated circuit includes synchronous-DRAM memory.
6. The printed circuit board of claim 4, wherein the switch, the memory integrated circuit, and a memory controller each collectively reside within a single integrated circuit.
7. A state decoder circuit, comprising:
a state decoder for receiving a chip select signal targeted for a memory circuit and having an input coupled to memory control signals and an output, wherein said state decoder is configured to have an output signal having a first state during a memory access and a second state in the absence of a memory access, and wherein the state decoder is configured to activate a switch to decouple a memory circuit from a data bus when no memory access cycle is being performed.
8. The state decoder circuit of claim 7, wherein the state decoder is integrated with a printed circuited circuit board.
9. The state decoder circuit of claim 8, wherein the printed circuit board is integrated with the memory circuit.
10. The state decoder circuit of claim 9, wherein the memory circuit comprises synchronous-DRAM memory.
a plurality of inputs connected to corresponding ones of first plurality of electrical contacts, and a plurality of outputs connected to at least one memory integrated circuit so as to couple a data bus from said first plurality of electrical contacts to said memory integrated circuit, said at least one switch having an additional input coupled to a state decoder circuit output that is responsive to a chip select signal, and responsive to said state decoder circuit output to decouple said memory circuit from said data bus when no memory access cycle is being performed.
12. The switch of claim 11, wherein the switch is integrated with a printed circuit board.
US10017257 1998-01-29 2001-12-06 High speed data bus Expired - Lifetime US6747888B2 (en)
US10017257 US6747888B2 (en) 1998-01-29 2001-12-06 High speed data bus
US10840198 US7038927B2 (en) 1998-01-29 2004-05-05 High speed data bus
US11103357 US7187574B2 (en) 1998-01-29 2005-04-11 High speed data bus
US11394997 US7184292B2 (en) 1998-01-29 2006-03-31 High speed data bus
US10840198 Continuation US7038927B2 (en) 1998-01-29 2004-05-05 High speed data bus
US20020041522A1 true US20020041522A1 (en) 2002-04-11
US6747888B2 true US6747888B2 (en) 2004-06-08
DE60210170D1 (en) * 2002-07-15 2006-05-18 Infineon Technologies Ag storage system
US7075808B2 (en) * 1998-01-29 2006-07-11 Micron Technology Inc. Method for bus capacitance reduction
US6888734B2 (en) 2005-05-03 grant