Source: http://www.google.com/patents/US6169529?ie=ISO-8859-1&dq=6,621,746
Timestamp: 2014-03-16 14:36:06
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Patent US6169529 - Circuit and method for controlling the color balance of a field emission display - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA circuit and method for time multiplexing a voltage signal for controlling the color balance of a flat panel display. Within an FED screen, a matrix of rows and columns is provided and emitters are situated within each row-column intersection. Rows are sequentially activated during �row on-time windows�...http://www.google.com/patents/US6169529?utm_source=gb-gplus-sharePatent US6169529 - Circuit and method for controlling the color balance of a field emission displayAdvanced Patent SearchPublication numberUS6169529 B1Publication typeGrantApplication numberUS 09/050,667Publication dateJan 2, 2001Filing dateMar 30, 1998Priority dateMar 30, 1998Fee statusPaidAlso published asDE69840936D1, EP1066618A1, EP1066618A4, EP1066618B1, WO1999050816A1Publication number050667, 09050667, US 6169529 B1, US 6169529B1, US-B1-6169529, US6169529 B1, US6169529B1InventorsRonald L. Hansen, Jay Friedman, Lee StoianOriginal AssigneeCandescent Technologies CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (20), Referenced by (14), Classifications (12), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetCircuit and method for controlling the color balance of a field emission displayUS 6169529 B1Abstract A circuit and method for time multiplexing a voltage signal for controlling the color balance of a flat panel display. Within an FED screen, a matrix of rows and columns is provided and emitters are situated within each row-column intersection. Rows are sequentially activated during �row on-time windows� by row drivers and corresponding individual gray scale information (voltages) are driven over the columns by column drivers. When the proper voltage is applied across the cathode and anode of the emitters, electrons are released toward a phosphor spot, e.g., red, green, blue, causing illumination. Within each column driver, the present invention provides selection circuitry for driving a first voltage signal during a first part of the row on-time window and a second voltage during a second part of the row on-time window. The lengths of the first part and second part of the row on-time window can be adjusted for a given color, to adjust the color balance with respect to that color, e.g., red, green or blue. In one embodiment, a shift register is used to divide a digital representation of the first voltage value in half for application during the second part of the row on-time window. In a second embodiment, a multiplexer is used to divide the first voltage value in half for application during the second part. In a third embodiment, the first and second parts of the row on-time window are swapped such that two first parts occur consecutively and two second parts occur consecutively over a period of two row on-time windows. The third embodiment reduces the frequency of voltage change and thereby saves power.
In the field of flat panel display devices, much like conventional cathode ray tube (CRT) displays, a white pixel is composed of a red, a green and a blue color point or �spot.� When each color point of the pixel is excited simultaneously, the pixel appears white. To produce different colors at the pixel, the intensity to which the red, green and blue points are driven is altered using well known techniques. The separate red, green and blue data that correspond to the color intensities of a particular pixel are called the pixel's color data. Color data is often called gray scale data. The degree to which different colors can be achieved within a pixel is referred to as gray scale resolution and is directly related to the amount of different intensities to which each red, green and blue point can be driven.
SUMMARY OF THE INVENTION A circuit and method are described for time multiplexing a voltage signal for controlling the color balance of a flat panel display. Adjustment of color balancing can be done in response to tube aging, viewer taste and/or manufacturing variations in the phosphor.
Within an FED screen, a matrix of rows and columns is provided and emitters are situated within each row-column intersection. Rows are sequentially activated during �row on-time windows� by row drivers and corresponding individual gray scale information (voltages) are driven over the columns by column drivers. When the proper voltage is applied across the cathode and anode of the emitters, electrons are released toward a phosphor spot, e.g., red, green, blue, causing illumination. Within each column driver, the present invention provides selection circuitry for driving a first voltage signal during a first (�full�) part of the row on-time window and a second voltage signal during a second (�half�) part of the row on-time window. The total or effective voltage applied to a given column is therefore a weighted average of the two voltages applied during the first part and the second part of the row on-time window. The weights of the weighted average is represented by the respective lengths of the first and second parts, respectively.
Phosphors 25 of FIG. 2 are part of a picture element (�pixel�) that contains other phosphors (not shown) which emit light of different color than that produced by phosphors 25. Typically a pixel contains three phosphor or �color� spots, a red spot, a green spot and a blue spot. Also, the pixel containing phosphors 25 adjoins one or more other pixels (not shown) in the FED flat panel display. If some of the electrons intended for phosphors 25 consistently strike other phosphors (in the same or another pixels), the image resolution and color purity can become degraded. As discussed in more detail below, the pixels of an FED flat panel screen are arranged in a matrix form including n columns and x rows. In one implementation, a pixel is composed of three phosphor spots aligned in the same row, but having three separate columns. Therefore, a single pixel is uniquely identified by one row and three separate columns (a red column, a green column and a blue column). As described more fully below, each column of the three columns that constitute a pixel is associated with its own column driver circuit.
Importantly, the intensity of the target phosphor portion 30 of FIG. 2 depends on the magnitude of the incident current which is itself dependent upon the voltage potential applied across the cathode 60/40 and the gate 50. Thus, the intensity of a color spot is related to the voltage differential applied between the row and column at whose intersection the color spot is located. The larger the voltage potential, the larger the intensity of the target phosphor portion 30. Secondly, the intensity of the target phosphor portion 30 depends on the amount of time a voltage is applied across the cathode 40/60 and the gate 50 (e.g., on-time window). The larger the on-time window, the larger the intensity of the target phosphor portion 30. Therefore, within the present invention, the intensity of FED flat panel structure 75 is dependent on the voltage and the amount of time (e.g., �on-time�) the voltage is applied across cathode 60/40 and the gate 50. The effective voltage (EV) is obtained by taking both voltage amplitude and voltage on-time into consideration.
As shown in FIG. 3, the FED flat panel display 200 is subdivided into an array of x horizontally aligned row lines 230 (�rows�) and n vertically aligned column lines 250 (�columns�). The pixels of the FED flat panel display 200 are also aligned vertically and horizontally. Color points (also called �phosphor spots�) are formed at each intersection of row and a column. Three adjacent color points of a same row, a red, a green and a blue, form a pixel. For n pixels horizontally, there are 3n columns. For x pixels vertically, there are x rows. The FED flat panel display 200 of FIG. 3 is described in more detail further below.
A portion 100 of this FED flat panel display 200 is shown in more detail in FIG. 4 and includes at least one full pixel. Specifically, FIG. 4 illustrates a respective pixel 125 (also called �white group�). The respective pixel 125 of FIG. 4 contains a red phosphor spot 125 a, a green phosphor spot 125 b and a blue phosphor spot 125 c of a same emitter line (also called �row electrode� or �row�) 230. In one embodiment, each phosphor spot of a pixel is controlled by a different column driver, but all phosphor spots of a pixel are controlled by the same row driver because all phosphor spots of a same pixel reside within the same row 230. The exemplary ith pixel 125 is therefore located at the ith red column line, ith green column line, the ith blue column line and the jth row line.
The boundaries of the respective pixel 125 of FIG. 4 are indicated by dashed lines. Three separate emitter lines 230 (row lines) are also shown. Each emitter line 230 is a row electrode for one of the rows of pixels in the array. The middle row electrode 230 is coupled to the emitter cathodes 60/40 (FIG. 2) of each emitter of the particular row associated with the electrode. A portion of one pixel row is indicated in FIG. 4 and is situated between a pair of adjacent spacer walls 135. A pixel row is comprised of all of the pixels along one row line 250. Two or more pixel rows (and as much as 24-100 pixel rows), are generally located between each pair of adjacent spacer walls 135. Each column of pixels has three gate lines (also called �columns�) 250: (1) one for red; (2) a second for green; and (3) a third for blue. Likewise, each pixel column includes one of each phosphor stripes (red, green, blue), three stripes total. Each of the gate lines 250 is coupled to the gate 50 (FIG. 2) of each emitter structure of the associated column. This structure 100 is described in more detail in U.S. Pat. No. 5,477,105 issued on Dec. 19, 1995 to Curtin, et al., which is incorporated herein by reference.
Row and Column Array. As discussed above, FIG. 3 illustrates an FED flat panel display screen 200 organized as an array of rows and columns in accordance with the present invention. Specifically, the screen contains x rows and n columns of �pixels�. Region 100, as described with respect to FIG. 4, is also shown in its relative position in FIG. 3. The FED flat panel display screen 200 consists of x number of row lines (horizontal) and 3n number of column lines (vertical) to achieve (xn) total pixels, e.g., three column lines per pixel are required. For clarity, a row line is called a �row� and a column line is called a �column.� Row lines are driven by x row driver circuits 220 a-220 c which in one embodiment are integrated circuits. Shown in FIG. 3 are exemplary row groups 230 a, 230 b and 230 c. Each row group contains an arbitrary number of rows (e.g., y) that are all associated with a particular row driver circuit; three respective row driver circuits are shown 220 a-220 c. In one embodiment of the present invention, there are over 400 rows (x=400) and therefore 400/y number of individual row groups 230 and associated row drivers 220. However, it is appreciated that the present invention is equally well suited to an FED flat panel display screen 200 having any number of rows.
A horizontal clock signal (�H SYNCH�) is also supplied to each row driver 220 a-220 c of FIG. 3 in parallel over clock line 214 of FIG. 3. The horizontal clock signal 214 (or synchronization signal) pulses each time a new row is to be energized and marks the start of a row on-time window. The horizontal clock signal 214 also synchronizes the loading of new column color data into the column driver circuits 240. Therefore, the x rows of a display frame are energized, one at a time, with the columns receiving the respective data. When all rows have been energized, a frame of data is displayed. Assuming an exemplary frame update rate of 60 Hz, all rows are updated once every 16.67 milliseconds. Assuming x rows per frame update, the horizontal clock signal 214 pulses once every 16.67/x milliseconds. In other words a new row is energized every 16.67/n milliseconds. If x is 400, the horizontal clock signal 214 pulses once every 41.67 microseconds.
All row drivers of FED 200 are configured to implement one large serial shift register having x bits of storage, one bit per row. Row data is shifted through these row drivers using a row data line 212 that is coupled to the row drivers 220 a-220 c in serial fashion. During sequential frame update mode, all but one of the bits of the n bits within the row drivers contain a �0� and the other one contains a �1�. Therefore, the �1� is shifted serially through all n rows, one at a time, from the upper most row to the bottom most row. Upon a given horizontal clock signal pulse, the row corresponding to the �1� is then driven for the on-time window. The bits of the shift registers are shifted through the row drivers 220 a-220 c once every pulse of the horizontal clock as provided by line 214. In interlace mode, the odd rows are updated in series followed by the even rows. A different bit pattern and clocking scheme is therefore used.
The row corresponding to the shifted �1� becomes driven responsive to the horizontal clock pulse over line 214. The row remains on during a particular �on-time� window. During this on-time window, the corresponding row is driven with the voltage value as seen over voltage supply line 212 provided the row drivers are also enabled. During the on-time window, the other rows are not driven with any voltage. In one embodiment, the rows are energized with a negative voltage, which could be a positive voltage in other embodiments.
The Column Driver Circuits 240. As shown by FIG. 4, there are three columns per pixel (or �white group�) within the FED flat panel display screen 200 of the present invention. Column lines 250 a of FIG. 3 control one column of pixels, column lines 250 b control another column of pixels, etc. FIG. 3 also illustrates the column drivers 240 that control the gray-scale information for each pixel. In an analogous fashion to the row driver circuits, the column drivers 240 can be broken into separate circuits that each drive groups of column lines. In accordance with the present invention, the column drivers 240 drive time multiplexed, amplitude modulated, voltage signals over the column lines 250. The amplitude modulated voltage signals driven over the column lines 250 a-250 e represent gray-scale data for a respective row of pixels. The larger the effective voltage (EV) of the column voltage, the larger the light intensity of the corresponding color point. The lower the effective voltage (EV) of the column voltage, the lower the light intensity for the corresponding color point.
In accordance with the present invention, the effective voltage applied is adjusted by time multiplexing two different column voltages over the row on-time window. In one embodiment, a full column voltage is applied during a first part of the row on-time window and a second or �half� column voltage is then applied over a second part of the row on-time window. The effective voltage then applied over the row-time window is the weighted average of the two voltages (full and half) weighted in accordance with the lengths of the first and second parts, respectively. The lengths of the first and second parts of the row on-time window are the same for a given color but can vary from color to color. In this way, color balancing is applied uniformly with respect to a given color.
FIG. 7 illustrates that the amplifier circuits 370 a(i), 370 b(i) and 370 c(i) are directly coupled to receive the outputs from lines 365 a(i), 365 b(i) and 365 c(i), respectively, and drive their respective column lines with these voltage levels. When row 230 j (e.g., the jth row) is active, column driver 240 a(i) drives a column voltage over ith red column line 250 f to illuminate the ith red spot 460 a; column driver 240 b(i) drives a column voltage over ith green column line 250 g to illuminate the ith green spot 460 b; and column driver 240 c(i) drives a column voltage over ith blue column line 250 h to illuminate the ith blue spot 460 c. It is appreciated that the red spot 460 a, the green spot 460 b and the blue spot 460 c comprise the ith pixel for a given row, e.g., row 230 j. Output Register Having Divide By Two Function For Time Multiplexing Column Voltages Over Row-On Time FIG. 8A, FIG. 8B and FIG. 8C illustrate the circuitry used by a first embodiment of the present invention for adjusting color balance within an FED screen 200 for three exemplary column drivers: the ith red column driver 240 a(i) of the n red column drivers 240 a, the ith green column driver 240 b(i) of the n green column drivers 240 b and the ith blue column driver 240 c(i) of the n blue column drivers 240 c. These three exemplary ith column drivers provide the column voltage signals for the ith pixel along a given row of pixels during a first part and a second part of the row on-time window. The first embodiment uses an output shift right register to perform a divide by two function, described below, to generate the voltages applied during the first and second parts.
Components with FIGS. 8A, 8B and 8C that have the �(i)� designation are replicated for each of the n column drivers of the same color as the exemplary column driver, (i), to which they are described. Components without the �(i)� designation are not replicated within each column driver but rather are shared by all column drivers, or all column drivers of a similar color, as described more particularly below.
FIG. 8A illustrates circuitry within the exemplary red column driver 240 a(i) that drives the ith red column (250 f of FIG. 7) within the ith pixel (of the n horizontal pixels) of the FED screen 200. Prior to the next pulse of the horizontal synchronization signal 214, the input shift register 310 a(i) serially receives (over bus 520) one seven bit color data value for the red intensity of the ith pixel of a row (e.g., row j). This data is clocked in based on signal 205. On the next pulse of horizontal synchronization signal 214, a new row on-time window starts. When a new row on-time window starts, the �first voltage� data from the input register 310 a(i) is then loaded in parallel to the output shift register 320 a(i) over the lines of bus 315 a(i). The first voltage data is held in shift register 320 a(i), and output over lines of bus 317 a(i), until a pulse is received from the shift right generator circuit 321 a. One circuit 321 a is coupled to and used by all of the n red column drivers 240 a. Circuit 321 a is coupled to receive the RSEL signal 345 a and according to the present invention generates a pulse to the output shift register 320 a(i) when the RSEL signal 345 a transitions.
When the pulse is received from circuit 321 a of FIG. 8A, the output shift register 320 a(i) of the present invention serially shifts its bit contents by one bit position to the right, effectively performing a divide by two operation on the first voltage data. During the right shift operation, a zero bit is inserted into the left most bit position (e.g., the MSB). The resulting digital value, a six bit �second voltage� data, represents half of the �first voltage� data and is held on lines 317 a(i) until the start of the next row on-time window (e.g., until the next pulse of line 214).
The data bits (either of the first or the second voltage data) are forwarded over bus 317 a(i) in parallel to decoder circuit 330 a(i) which in response generates a signal over a single output line of bus 319 a(i). If seven bits of color data are used, then decoder circuit 330 a(i) is a 0 to 127 decoder (as shown). Alternatively, if six bits of color data are used, then decoder circuit 330 a(i) is a 0 to 63 decoder. For a given input over bus 317 a(i), the decoder circuit 330 a(i) generates a single active signal over one of the lines of bus 319 a(i) to the digital to analog (�DA�) voltage converter circuit 340 a(i). Since the first and second voltage data are presented, time multiplexed, within a given row on-time window, decoder circuit 330 a(i) generates two separate time multiplexed outputs to the DA voltage circuit 340 a(i) during the row on-time window.
The DA voltage circuit 340 a(i) of FIG. 8A contains a function of switches that can provide any transformation function (e.g., linear or non-linear) depending on the programmed configuration of certain internal switches coupled to a resistor chain which is coupled to the previously described voltage taps. This is described in more detail in co-pending U.S. patent application entitled, �A Circuit and Method for Controlling the Color Balance of a Flat Panel Display Without Reducing Gray Scale Resolution,� filed Sep. 25, 1997, Ser. No. 08/938,194, by Hansen, et. al., and incorporated herein by reference. Using its transformation function, the DA voltage circuit 340 a(i) generates, over line 365 a(i), a first analog voltage corresponding to the first voltage data. Subsequently, DA voltage circuit 340 a(i) generates a second analog voltage corresponding to the second voltage data. The channel amplifier circuit 370 a(i) receives these time multiplexed analog voltage signals over line 365 a(i) and drives these values over the ith red column line 250 f as appropriate.
As discussed with reference to FIG. 8A, the output shift register 320 c(i) generates two different blue voltage data values, a first and a second, which are time multiplexed and fed to decoder 330 c(i). The channel amplifier 370 c(i) therefore generates two different time multiplexed blue analog voltage signals over column line 250 h. The time multiplexing for blue is controlled by the BSEL line 345 c. FIG. 9A, FIG. 9B and FIG. 9C illustrate the circuitry used by a second embodiment of the present invention for adjusting color balance within an FED screen 200 for three exemplary column drivers: the ith red column driver 240 a(i)′ of the n red column drivers 240 a, the ith green column driver 240 b(i)′ of the n green column drivers 240 b and the ith blue column driver 240 c(i)′ of the n blue column drivers 240 c. These three exemplary ith column drivers represent the ith pixel along a given row of pixels. The second embodiment uses a multiplexer configuration, rather than a shift register, to perform the divide by two function, described below. Components with FIGS. 9A, 9B and 9C that have the �(i)� designation are replicated for each column driver of the same color as the exemplary column driver to which they are described. Components without the �(i)� designation are not replicated within each column driver but rather are shared by all column drivers, or all column drivers of a similar color, as described more particularly below.
FIG. 9A illustrates circuitry within the exemplary red column driver 240 a(i)′ that drives the ith red column (250 f of FIG. 7) within the ith pixel (of the n horizontal pixels) of the FED screen 200. Prior to the next pulse of the horizontal synchronization signal 214, the input shift register 310 a(i) serially receives (over bus 520) one seven bit color data value for the red intensity of the ith pixel of a row (e.g., row j). This data is clocked in based on signal 205. On the next pulse of horizontal synchronization signal 214, a new row on-time window starts. When a new row on-time window starts, the �first voltage� data from the input register 310 a(i) is then loaded in parallel onto lines 0 to 6 of bus 315 a(i). Lines 0 to 6 of bus 315 a(i) are coupled to one input 542 a(i) of multiplexer 544 a(i). Lines 1 to 6 are coupled to a second input 540 a(i) of multiplexer 544 a(i) starting from the LSB(0) position. This digitally provides that the value represented by input 540 a(i) is half of the value represented by input 542 a(i).
The RSEL signal 345 a of FIG. 12A divides each row on-time window 580 into two parts, a first part which presents the first or �full� voltage data and a second part which presents the second or �half� voltage data. (In one alternate embodiment, the half voltage data is gauged such that half current is drawn.) Also shown in FIG. 12A is the analog voltage signal driven on the ith column line 250 f for producing light intensity at red color spot 460 a (FIG. 7). For example, during row on-time window 580 a of FIG. 12A, first voltage v1 is driven during the first part 585 a and second, or half, voltage (v1/2) is driven during the second part 585 b of row on-time window 580 a. The relative lengths of first part 585 a and second part 585 b can be adjusted by adjusting the resistor-capacitor network 572 a (FIG. 11). The effective voltage amplitude, VE, for window 580 a is therefore the weighted average of v1 and (v1/2) over their respective on-time parts 585 a-585 b according to:
FIG. 12B illustrates timing diagrams of the pertinent signals used by the first and second embodiments of the present invention for the exemplary green column driver 240 b(i) of FIG. 8B and for the exemplary column driver 240 b(i)′ of FIG. 9B. The horizontal synchronization clock 214 is shown divided into the four exemplary consecutive row on-time windows 580 a-580 d of FIG. 12A. The GSEL signal 345 b divides each row on-time window 580 into two parts, a first part which presents the first or �full� voltage data and a second part which presents the second or �half� voltage data. Also shown in FIG. 12B is the analog voltage signal driven on the ith column line 250 g for producing light intensity at green color spot 460 b (FIG. 7). For example, during row on-time window 580 a of FIG. 12B, voltage v1 is driven during the first part 585 c and half voltage (v1/2) is driven during the second part 585 d of row on-time window 580 a. The relative lengths of first part 585 c and second part 585 d can be adjusted by adjusting the resistor-capacitor network 572 b (FIG. 11). Likewise, for row on-time 580 b, voltages v2 and (v2/2) are driven as shown. For row ontime 580 c, voltages v3 and (v3/2) are driven as shown and for row on-time 580 d, voltages v4 and (v4/2) are driven as shown. It is appreciated that V1-V4 of FIG. 12A are not the same voltage values as V1-V4 of FIG. 12B.
According to the teachings above, the color balance of the first and second embodiments of the present invention can be adjusted by varying the RSEL signal 345 a, the GSEL signal 345 b and the BSEL signal 345 c according to the circuit 550 of FIG. 11. The red component of the current color balance can be increased by altering RSEL signal 345 a such that the first part of the row on-time window that corresponds to the red color is increased. This increases the period in which the first or �full� voltage is applied. Since the red timing pulse RSEL 345A is applied to all red column drivers 240 a, they will uniformly adjust up the respective effective column voltages which are used to generate the red color intensities. Although each red column driver receives different red color data, all red color intensities will be uniformly increased by the same amount. Likewise, the red component of the current color balance can be decreased by altering RSEL signal 345 a such that the second part of the row on-time window that corresponds to the red color is increased. This increases the period in which the second or �half� voltage is applied. The same is true with respect to the green and blue color components which can be altered by similarly altering the GSEL 345 b and the BSEL 345 c, respectively.
Power Savings Third Embodiment of the Present Invention As shown in FIG. 12A and FIG. 12B, the first and second parts of the row on-time windows 580 a-580 d occur in sequential and alternating order, e.g., the first or �full� part always following the second or �half� part which follows a first part, etc. Although effective to provide color balancing, this alternating scheme of the first and second embodiments of the present invention generates some frequency of voltage change with respect to the voltage signals driven on the columns (e.g., columns 250 f and 250 g). For instance, every full analog voltage level is followed by its half voltage level which is followed again by a full voltage of a next row-on time window, and so on.
The third embodiment of the present invention provides a mechanism for altering the order of the first and second parts of a row on-time window to decrease the overall frequency of voltage change on the columns while still providing for the same level of color balance functionality provided by the first and second embodiments of the present invention. Specifically, the third embodiment of the present invention provides a mechanisms whereby, for the period of two consecutive row on-time windows, two consecutive full parts are followed by two consecutive half parts. In other words, the order of the first (�FULL�) and second (�HALF�) parts of the row on-time window, compared to the first and second embodiments, are swapped for every other row on-time window. The result produces the following ordering within the third embodiment:
FIG. 13 illustrates a circuit 700 used by the third embodiment of the present invention for providing the proper color select signals to realize the above ordering of full and half parts. Specifically, circuit 700 can be used to generate either signal 345 a, 345 b or 345 c, any one of which is represented by the reference �345 x� and �XSEL.�
Circuit 700 includes a divide-by-two circuit 710 which receives the horizontal synchronization signal 214 and divides its frequency by two to produce a �HALF H SYNCH� signal at node 715. Any of a number of well known divide-by-two circuits can be used and the configured D flip-flop 710 shown in FIG. 13 is exemplary only. The HALF H SYNCH signal of node 715 controls a ramp generator circuit 720. Specifically, the signal at node 715 controls the enable line of a charging constant current source 722 and the inverse of the signal at node 715 (via inverter 726) controls the enable of a discharging constant current source 724. The charging constant current source 722 is coupled to a voltage source Vcc, and coupled to node 730. Node 730 is coupled to the discharging constant current source 724 which is coupled to ground or a negative voltage supply Vpp.
FIG. 15 illustrates timing diagrams of the pertinent signals used by the third embodiment of the present invention for the exemplary red column driver 240 a(i)′ of FIG. 9A. (In order for the exemplary red column driver 240 a(i) to operate with the third embodiment, the driver would need to be modified such the output shift register 320 a(i) was able to simultaneously supply both the first or �full� voltage data and the second or �half� voltage data.) The horizontal synchronization clock 214 is shown divided into four exemplary consecutive row on-time windows 580 a-580 d. The HALF H SYNCH signal 715 is also shown. During the first row-on time window 580 a, the ramp signal 730 is charging, during the second row-on time window 580 b, the ramp signal 730 is discharging. This sequence continues over windows 580 c and 580 d. Although shown as analog, the ramp generator circuit 750 could also be implemented using digital circuits. In this digital implementation, the charging of node 730 can be simulated by upcounting a counter circuit and the discharging of node 730 can be simulated by downcounting the counter circuit wherein signal 715 controls the count direction. In this implementation, a digital comparator is used for circuit 740 x and the threshold value VTX would be a digital number.
FIG. 15 also illustrates the constant threshold voltage VTR. As shown by the RSEL signal 345 a, for those periods when the ramp signal 730 exceeds the threshold voltage VTR, then RSEL signal 345 a is asserted and deasserted otherwise. These signals create the following ordering. During the first window 580 a, the first or �FULL� part is asserted followed by its second or �HALF� part. However, during the second window 580 b, the HALF part is asserted followed by its FULL part. During the third window 580 c, the FULL part is asserted followed by its HALF part and during the fourth window 580 d, the HALF part is asserted followed by its FULL part. Although the order of the FULL and HALF parts have been altered, compared to the ordering of the first and second embodiments, the lengths of each FULL part of FIG. 15 are the same and the lengths of each HALF part of FIG. 15 are the same. It is appreciated that by varying the level of the threshold voltage VTR, the relative lengths of the FULL and HALF parts can be adjusted.
FIG. 16 illustrates timing diagrams of the pertinent signals used by the third embodiment of the present invention for the exemplary green column driver 240 b(i)′ of FIG. 9B. (In order for the exemplary green column driver 240 b(i) to operate with the third embodiment, the driver would need to be modified such that the output shift register 320 b(i) was able to simultaneously supply both the first or �full� voltage data and the second or �half� voltage data.) The horizontal synchronization clock 214 is shown divided into the four exemplary consecutive row on-time windows 580 a-580 d. The HALF H SYNCH signal 715 is also shown. The same ramp generation signal 730 is shown in FIG. 16 as is shown in FIG. 15.
FIG. 16 also illustrates the constant threshold voltage VTG which is lower in value than VTR of FIG. 15. As a result, the HALF parts of FIG. 16 are larger in duration than the HALF parts of FIG. 15. As shown by the GSEL signal 345 b, for those periods when the ramp signal 730 exceeds the threshold voltage VTG, then GSEL signal 345 b is asserted and deasserted otherwise. These signals create the following ordering. During the first window 580 a, the first or �FULL� part is asserted followed by its second or �HALF� part. However, during the second window 580 b, the HALF part is asserted followed by its FULL part. During the third window 580 c, the FULL part is asserted followed by its HALF part and during the fourth window 580 d, the HALF part is asserted followed by its FULL part. It is appreciated that by varying the level of the threshold voltage VTG, the relative lengths of the FULL and HALF parts can be adjusted.
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