Source: http://www.google.com/patents/US6407452?dq=6011510
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Patent US6407452 - Integrated circuitry and method of restricting diffusion from one material ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe invention includes methods of restricting diffusion between materials. First and second different materials which are separated by a barrier layer capable of restricting diffusion of material between the first and second materials are provided. The barrier layer is formed by forming a first layer...http://www.google.com/patents/US6407452?utm_source=gb-gplus-sharePatent US6407452 - Integrated circuitry and method of restricting diffusion from one material to anotherAdvanced Patent SearchPublication numberUS6407452 B1Publication typeGrantApplication numberUS 09/611,586Publication dateJun 18, 2002Filing dateJul 7, 2000Priority dateApr 10, 1998Fee statusPaidAlso published asUS6156638Publication number09611586, 611586, US 6407452 B1, US 6407452B1, US-B1-6407452, US6407452 B1, US6407452B1InventorsVishnu K. Agarwal, Garo J. DerderianOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (91), Non-Patent Citations (19), Referenced by (5), Classifications (14), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetIntegrated circuitry and method of restricting diffusion from one material to another
An insulative dielectric layer 36 is formed over substrate 32. Exemplary materials are Si3N4, SiO2 and doped SiO2 such as borophosphosilicate glass. A contact opening 37 is formed therein to diffusion region 34. A first layer of material 45 is formed within opening 37. Example materials include electrically conductive TiN, WN, TaN, Ta, WxSiyNz, TixSiyNz, TaxSiyNz, TixAlyNz, TaxAlyNz, and mixtures thereof where “x” preferably ranges from 0.3 to 0.7, “y” ranges from 0.5 to 2.0, and “z” is equal to 1−x−y. Layer 45 is preferably deposited by chemical vapor deposition (CVD). The illustrated construction can be produced by CVD followed by a planarization process such as chemical-mechanical polishing. Some of the material of layer 45 might also adhere to the walls of contact opening 37 (not shown). Layer 45 as initially formed can be either crystalline or amorphous, with an initial amorphous structure being preferred and shown. Regardless, layer 45 is preferably subsequently annealed at a temperature of at least 300� C. for a time period sufficient to achieve a selected crystalline structure intended to densify and improve conductivity of the material (FIG. 2). Exemplary anneal conditions include a temperature range of from about 300� C. to about 1200� C. at a pressure of from about 2 mTorr to about 5 atm for a treatment time of anywhere from about 1 minute to 2 hours. Unfortunately as described above with respect to the prior art, such annealing can cause sufficient crystallization to form singular grains at various locations throughout layer 45 having grain boundaries which extend from one surface of the layer to the other, as shown.
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