Source: http://www.google.com.tw/patents/US7818490
Timestamp: 2013-05-20 13:20:15
Document Index: 519515125

Matched Legal Cases: ['application No. 02703078', 'Application No. 2002', 'Application No. 2002', 'Application No. 2008', 'Application No. 2003', 'Application No. 2008', 'Application No. 2008', 'Application No. 02703078', 'Application No. 2002', 'Application No. 200610142358', 'Application No. 200610142359', 'Application No. 02803882']

�M�Q US7818490 - Partial block data programming and reading operations in a non-volatile memory - Google �M�Q�j�M �Ϥ� �a�� Play YouTube �s�D Gmail ���ݵw�� ��h »�i���M�Q�j�M | �������� | �n�J�i���M�Q�j�M�M�QData in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of...http://www.google.com.tw/patents/US7818490?utm_source=gb-gplus-share�M�Q US7818490 - Partial block data programming and reading operations in a non-volatile memory���}��US7818490 B2�X���������v�ӽЮѽs��11/250,238�o�G���2010�~10��19���ӽФ��2005�~10��13�� �u���v���2001�~1��19����L���}�M�Q��CN1290021CCN1514971ACN1924830ACN1924831ACN100485641CCN100485642CEP1352394A2EP1352394B1EP1645964A2EP1645964A3EP1653323A2EP1653323A3US6763424US6968421US7657702US8316177US20020099904US20040210708US20060031627US20090150601WO2002058074A2WO2002058074A3WO2002058074A9�o��HKevin M. Conley��M�Q�v�HSandisk Corporation ���M�Q������711/103711/115711/113��ڱM�Q������G11C16/10G11C16/06G06F12/00G11C16/02G06F12/02G06F9/24 �X�@����G11C2216/16G06F2212/7208G11C16/105G06F2212/7209G06F12/0246G11C16/102 �ڬw������G11C16/10E2G11C16/10EG06F12/02D2E2�ѦҤ��m�M�Q�ޥ� (89)�D�M�Q�ޥ� (63)�~���s�����M�Q�ӼЧ� ���M�Q�ӼЧ��M�Q����T�� �ڬw�M�Q��Partial block data programming and reading operations in a non-volatile memoryUS 7818490 B2�K�n Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.
In one commercial form, each block contains enough cells to store one sector of user data plus some overhead data related to the user data and/or to the block in which it is stored. The amount of user data included in a sector is the standard 512 bytes in one class of such memory systems but can be of some other size. Because the isolation of individual blocks of cells from one another that is required to make them individually erasable takes space on the integrated circuit chip, another class of flash memories makes the blocks significantly larger so there is less space required for such isolation. But since it is also desired to handle user data in much smaller sectors, each large block is often further partitioned into individually addressable pages that are the basic unit for reading and programming user data (unit of programming and/or reading). Each page usually stores one sector of user data, but a page may store a partial sector or multiple sectors. A ��sector�� is used herein to refer to an amount of user data that is transferred to and from the host as a unit.
Another principal aspect of the present invention groups together two or more blocks positioned in separate units of the memory array (also termed ��sub-arrays��) for programming and reading together as part of a single operation. Such a multiple block group is referenced herein as a ��metablock.�� Its component blocks may be either all located on a single memory integrated circuit chip, or, in systems using more than one such chip, located on two or more different chips. When data in fewer than all of the pages of one of these blocks is updated, the use of another block in that same unit is normally required. Indeed, the techniques described above, or others, may be employed separately with each block of the metablock. Therefore, when data within pages of more than one block of the metablock are updated, pages within more than one additional block are required to be used. If there are four blocks of four different memory units that form the metablock, for example, there is some probability that up to an additional four blocks, one in each of the units, will be used to store updated pages of the original blocks. One update block is potentially required in each unit for each block of the original metablock. In addition, according to the present invention, updated data from pages of more than one of the blocks in the metablock can be stored in pages of a common block in only one of the units. This significantly reduces the number of unused erased blocks that are needed to store updated data, thereby making more efficient use of the available memory cell blocks to store data. This technique is particularly useful when the memory system frequently updates single pages from a metablock.
CS�XChip Select. Used to activate flash memory interface. RS�XRead Strobe. Used to indicate the I/O bus is being used to transfer data from the memory array. WS�XWrite Strobe. Used to indicate the I/O bus is being used to transfer data to the memory array. AS�XAddress Strobe. Indicates that the I/O bus is being used to transfer address information. AD[7:0]�XAddress/Data Bus This I/O bus is used to transfer data between controller and the flash memory command, address and data registers of the memory control 450. This interface is given only as an example as other signal configurations can be used to give the same functionality. FIG. 1 shows only one flash memory array 400 with its related components, but a multiplicity of such arrays can exist on a single flash memory chip that share a common interface and memory control circuitry but have separate XDEC, YDEC, SA/PROG and DATA REG circuitry in order to allow parallel read and program operations.
In some prior art systems having large capacity memory cell blocks that are divided into multiple pages, as discussed above, the data from a block that is not being updated needs to be copied from the original block to a new block that also contains the new, updated data being written by the host. This technique is illustrated in FIG. 4, wherein two of a large number of blocks of memory are included. One block 11 (PBN0) is illustrated to be divided into 8 pages for storing one sector of user data in each of its pages. Overhead data fields contained within each page include a field 13 containing the LBN of the block 11. The order of the logical pages within a logical block is fixed with respect to the corresponding physical pages within a physical block. A second similarly configured block 15 (PBN1) is selected from an inventory of unused, erased blocks. Data within pages 3�V5 of the original block 11 are being updated by three pages of new data 17. The new data is written into the corresponding pages 3�V5 of the new block 15, and user data from pages 0�V2, 6 and 7 of the block 11 are copied into corresponding pages of the new block 15. All pages of the new block 15 are preferably programmed in a single sequence of programming operations. After the block 15 is programmed, the original block 11 can be erased and placed in inventory for later use. The copying of data between the blocks 11 and 15, which involves reading the data from one or more pages in the original block and subsequently programming the same data to pages in a newly assigned block, greatly reduces the write performance and usable lifetime of the storage system.
With reference to FIGS. 5A and 5B, partial tables show mapping of the logical blocks into the original and new physical blocks 11 and 15 before (FIG. 5A) and after (FIG. 5B) the updating of data described with respect to FIG. 4. Before the data update, the original block 11, in this example, stores pages 0�V7 of LBN0 into corresponding pages 0�V7 of PBN0. After the data update, the new block 15 stores pages 0�V7 of LBN0 in corresponding pages 0�V7 of PBN1. Receipt of a request to read data from LBN0 is then directed to the physical block 15 instead of the physical block 11. In a typical controller operation, a table in the form of that shown in FIGS. 5A and 5B is built from the LBN field 13 read from a physical page and knowledge of the PBN that is addressed when reading the data field 13. The table is usually stored in a volatile memory of the controller for ease of access, although only a portion of a complete table for the entire system is typically stored at any one time. A portion of the table is usually formed immediately in advance of a read or programming operation that involves the blocks included in the table portion.
In other prior art systems, flags are recorded with the user data in pages and are used to indicate that pages of data in the original block that are being superceded by the newly written data are invalid. Only the new data is written to the newly assigned block. Thus the data in pages of the block not involved in the write operation but contained in the same physical block as the superceded data need not be copied into the new block. This operation is illustrated in FIG. 6, where pages 3�V5 of data within an original block 21 (PBN0) are again being updated. Updated pages 3�V5 of data 23 are written into corresponding pages of a new block 25. As part of the same operation, an old/new flag 27 is written in each of the pages 3�V5 to indicate the data of those pages is old, while the flag 27 for the remaining pages 0�V2, 6 and 7 remains set at ��new��. Similarly, the new PBN1 is written into another overhead data field of each of the pages 3�V5 in the block 21 to indicate where the updated data are located. The LBN and page are stored in a field 31 within each of the physical pages.
FIGS. 7A and 7B are tables of the correspondence between the data LBN/page and the PBN/page before (FIG. 7A) and after (FIG. 7B) the data update is complete. The unchanged pages 0�V2, 6 and 7 of the LBN remain mapped into PBN0 while the updated pages 3�V5 are shown to reside in PBN1. The table of FIG. 7B is built by the memory controller by reading the overhead data fields 27, 29 and 31 of the pages within the block PBN0 after the data update. Since the flag 27 is set to ��old�� in each of pages 3�V5 of the original block PBN0, that block will no longer appear in the table for those pages. Rather, the new block number PBN1 appears instead, having been read from the overhead fields 29�� of the updated pages. When data are being read from LBN0, the user data stored in the pages listed in the right column of FIG. 7B are read and then assembled in the order shown for transfer to the host.
A common feature of each of the existing memory management techniques described above with respect to FIGS. 4�V7B is that a logical block number (LBN) and page offset is mapped within the system to at most two physical block numbers (PBNs). One block is the original block and the other contains the updated page data. Data are written to the page location in the block corresponding to the low order bits of its logical address (LBA). This mapping is typical in various types of memory systems. In the techniques described below, pages containing updated data are also assigned the same LBN and page offsets as the pages whose data has been superceded. But rather than tagging the pages containing original data as being superceded, the memory controller distinguishes the pages containing the superceded data from those containing the new, updated version either (1) by keeping track of the order in which the pages having the same logical addresses were written, such as by use of a counter, and/or (2) from the physical page addresses wherein, when pages are written in order within blocks from the lowest page address to the highest, the higher physical address contains the most recent copy of the data. When the data is accessed for reading, therefore, those in the most current pages are used in cases where there are pages containing superceded data that have the same logical addresses, while the superceded data are ignored.
A first specific implementation of this technique is described with respect to FIGS. 8 and 9. The situation is the same in this example as that in the prior art techniques described with respect to FIGS. 4�V7B, namely the partial re-write of data within a block 35, although each block is now shown to contain 16 pages. New data 37 for each of the pages 3�V5 of the block 35 (PBN 35) is written into three pages of a new block 39 (PBN1) that has previously been erased, similar to that described previously. A LBN and page offset overhead data field 41 written into the pages of PBN1 that contain the updated data is the same as that in the pages of the superceded data in the initial block PBN0. The table of FIG. 9, formed from the data within the fields 41 and 41��, shows this. The logical LBN and page offsets, in the first column, are mapped into both the first physical block (PBN0), in the second column, and, for the pages that have been updated, also into the second physical block (PBN1) in the third column. The LBN and logical page offsets 41�� written into each of the three pages of updated data within the new block PBN1 are the same as those 41 written into each of a corresponding logical page of the original block PBN0.
There are several ways in which the field 43, which contains a form of time stamp, may be written. The most straight forward way is to record in that field, when the data of its associated page is programmed, the output of a real-time clock in the system. Later programmed pages with the same logical address then have a later time recorded in the field 43. But when such a real-time clock is not available in the system, other techniques can be used. One specific technique is to store the output of a modulo-N counter as the value of the field 43. The range of the counter should be one more than the number of pages that are contemplated to be stored with the same logical page number. When updating the data of a particular page in the original block PBN0, for example, the controller first reads the count stored in the field 43 of the page whose data are being updated, increments the count by some amount, such as one, and then writes that incremented count in the new block PBN1 as the field 43��. The counter, upon reaching a count of N+1, rolls over to 0. Since the number of blocks with the same LBN is less than N, there is always a point of discontinuity in the values of stored counts. It is easy then to handle the rollover with normalized to the point of discontinuity.
The controller, when called upon to read the data, easily distinguishes between the new and superceded pages' data by comparing the counts in the fields 43 and 43�� of pages having the same LBA and page offset. In response to a need to read the most recent version of a data file, data from the identified new pages are then assembled, along with original pages that have not been updated, into the most recent version of the data file.
It will be noted that, in the example of FIG. 8, the new data pages 37 are stored in the first three pages 0�V2 of the new block PBN1, rather than in the same pages 3�V5 which they replace in the original block PBN0. By keeping track of the individual logical page numbers, the updated data need not necessarily be stored in the same page offset of the new block as that of the old block where superceded data is contained. Page(s) of updated data can also be written to erased pages of the same block as the page of data being superceded.
As a result, there is no constraint presented by the techniques being described that limit which physical page new data can be written into. But the memory system in which these techniques are implemented may present some constraints. For example, one NAND system requires that the pages within the blocks be programmed in sequential order. That means that programming of the middle pages 3�V5, as done in the new block 25 (FIG. 6), wastes the pages 0�V2, which cannot later be programmed. By storing the new data 37 in the first available pages of the new block 39 (FIG. 8) in such a restrictive system, the remaining pages 3�V7 are available for later use to store other data. Indeed, if the block 39 had other data stored in its pages 0�V4 at the time the three pages of new data 37 were being stored, the new data could be stored in the remaining unused pages 5�V7. This makes maximum use of the available storage capacity for such a system.
FIG. 11 illustrates an extension of the example of FIG. 8 by including a second update to the data originally written in the block PBN0. New data 51 for logical pages 5, 6, 7 and 8 is written to the respective physical pages 3, 4, 5 and 6 of the new block PBN1, along with their LBN and page number. Note, in this example, that the data of logical page 5 is being updated for the second time. During a reading operation that begins from the last page of the new block PBN1, the most recently written logical pages 8, 7, 6 and 5 of the data of interest are first read in that order. Thereafter, it will be noted that the LBN/page overhead field in physical page 2 of PBN1 is the same as that read from the physical page 3, so the user data of page 2 is not read. The physical pages 1 and 0 are then read. Next, the pages of the original block PBN0 are read, beginning with physical page 15. After reading physical pages 15�V9, the controller will note that the LBN/page fields of each of pages 8�V3 match those of pages whose data has already been read, so the old data need not be read from those pages. The efficiency of the reading process is thus improved. Finally, the original data of physical pages 2�V0 are read since that data was not updated.
An efficient way to organize pages of data being read from a physical block, where one or more of the pages has been updated, is illustrated by FIG. 13. Enough space is provided in a volatile memory of the controller to buffer at least several pages of data at a time, and preferably a full block of data. That is what is shown in FIG. 13. Sixteen pages of data, equal to the amount stored in a non-volatile memory block, are stored in the controller memory. Since the pages are most commonly read out of order, each page of data is stored in its proper position with respect to the other pages. For example, in the reverse page read operation of FIG. 11, logical page 8 if the first to be read, so it is stored in position 8 of the controller memory, as indicated by the ��1�� in a circle. The next is logical page 7, and so forth, until all pages of data desired by the host are read and stored in the controller memory. The entire set of page data is then transferred to the host without having to manipulate the order of the data in the buffer memory. The pages of data have already be organized by writing them to the proper location in the controller memory.
In order to improve performance by reducing programming time, a goal is to program as many cells in parallel as can reasonably be done without incurring other penalties. One implementation divides the memory array into largely independent sub-arrays or units, such as multiple units 80�V83 of FIG. 15, each unit in turn being divided into a large number of blocks, as shown. Pages of data are then programmed at the same time into more than one of the units. Another configuration further combines one or more of these units. from multiple memory chips. These multiple chips may be connected to a single bus (as shown in FIG. 2) or multiple independent busses for higher data throughput. An extension of this is to link blocks from different units for programming, reading and erasing together, an example being shown in FIG. 15. Blocks 85�V88 from respective ones of the units 80�V83 can be operated together as a metablock, for example. As with the memory embodiments described above, each block, the smallest erasable group of the memory array, is typically divided into multiple pages, a page containing the smallest number of cells that are programmable together within the block. Therefore, a programming operation of the metablock shown in FIG. 15 will usually include the simultaneously programming of data into at least one page of each of the blocks 85�V88 forming the metablock, which is repeated until the metablock is full or the incoming data has all been programmed. Other metablocks are formed of different blocks from the array units, one block from each unit.
In the course of operating such a memory, as with others, pages of data less than an entire block often need to be updated. This can be done for individual blocks of a metablock in the same manner as described above with respect to either of FIG. 4 or 6, but preferably by use of the improved technique described with respect to FIG. 8. When any of these three techniques are used to update data of one block of the metablock, an additional block of memory within the same unit is also used. Further, a data update may require writing new data for one or more pages of two or more of the blocks of a metablock. This can then require use of up to four additional blocks 90�V93, one in each of the four units, to update a data file stored in the metablock, even though the data in only a few pages is being updated.
In order to reduce the number of blocks required for such partial block updates, according to another aspect of the present invention, updates to pages of data within any of the blocks of the illustrated metablock are made, as illustrated by FIG. 16, to a single additional block 90 in the memory unit 80, so long as unused pages in the block 80 remain. If, for example, data in three pages of the block 86 and two pages of the block 88 are being updated at one time, all five pages of the new data are written into the block 90. This can save the use of one block of memory, thereby to effectively increase the number of available erased blocks by one block. This helps avoid, or at least postpone, the time when an inventory of erased blocks becomes exhausted. If one or more pages from each of the four blocks 85�V88 are being updated, all of the new data pages are programmed in the single block 90, thereby avoiding tying up an additional three blocks of memory to make the update. If the number of pages of new data exceed the capacity of an unused block, pages that the block 90 cannot accept are written to another unused block which may be in the same unit 80 or one of the other units 81�V83.
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