Source: http://www.google.com/patents/US7834407?dq=7,403,220
Timestamp: 2017-11-23 21:25:38
Document Index: 64947924

Matched Legal Cases: ['art 9', 'art 11', 'art 9', 'art 9', 'art 11', 'art 11', 'art 9', 'art 11', 'art 9', 'art 9', 'art 9', 'art 11', 'art 11']

Patent US7834407 - Semiconductor device - Google Patents
In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode,...http://www.google.com/patents/US7834407?utm_source=gb-gplus-sharePatent US7834407 - Semiconductor device
Publication number US7834407 B2
Application number US 12/471,680
Also published as US8232610, US8592920, US8604563, US9013006, US9245973, US9478530, US20060261391, US20090230467, US20100327359, US20120241855, US20120241856, US20140193968, US20150228758, US20160148923, US20170040445
Publication number 12471680, 471680, US 7834407 B2, US 7834407B2, US-B2-7834407, US7834407 B2, US7834407B2
Inventors Yoshito Nakazawa, Yuji Yatsuda
Patent Citations (46), Referenced by (4), Classifications (36), Legal Events (2)
US 7834407 B2
14. The semiconductor device according to claim 4, wherein one cathode region of the plurality of protective diodes whose anode regions are connected to each other is connected to the gate electrode of the field-effect transistor, and the other cathode region thereof is connected to the source region of the field-effect transistor.
The dummy gate electrode 9 a and the gate electrode 11 a are made of, for example, a polycrystalline silicon film having low resistance, and insulated from each other by an insulating film intervening between the dummy gate electrode 9 a and the gate electrode 11 a. The dummy gate electrode (made of a first conductive film) 9 a is electrically connected to the gate electrode 11 a. That is, in the first embodiment, the dummy gate electrode 9 a and the gate electrode 11 a are set at the same potential, whereby the withstand voltage of the gate electrode 11 a cannot be affected by an insulation resistance of the insulating film intervening between the dummy gate electrode 9 a and the gate electrode 11 a, resulting in improved withstand voltage of the gate electrode 11 a. That is, the withstand voltage of the gate electrode 11 a is apt to be affected by the insulation resistance of the insulating film intervening between the dummy gate electrode 9 a and the gate electrode 11 a. In the first embodiment, however, the dummy gate electrode 9 a and the gate electrode 11 a with the insulating film sandwiched therebetween are set at the same potential, so that a voltage load is not applied to the intervening insulating film, thereby improving the withstand voltage of the gate electrode 11 a.
The gate electrode 11 a is a control electrode of the power MISFET, to which a voltage for control of the operation of the power MISFET is applied. The upper surface of the gate electrode 11 a is slightly lower than the top part on the main surface side of the semiconductor substrate 1 (namely, the upper surface of the source region 14). On the upper surface of the gate electrode 11 a recessed downward, sidewalls 12 made of, for example, a silicon oxide film, are embedded. A channel of the power MISFET is formed in the semiconductor region 13 for channel formation opposite to the side of the gate electrode 11 a. That is, a channel current of the power MISFET passes along the side of the trench 6 in the thickness direction of the semiconductor substrate 1 which is perpendicular to the substrate 1.
In FIG. 3, the trench 6 positioned on the outmost periphery (on the left side) does not act as the power MISFET, and a lead-out part 9 b for the dummy gate electrode is formed in the trench via the insulating film 7. A lead-out part 11 b for the gate electrode is formed over the lead-out part 9 b for the dummy gate electrode via the gate insulating film 10. The lead-out part 9 b for the dummy gate electrode is electrically connected to the dummy gate electrode 9 a, and the lead-out part 11 b for the gate electrode is electrically connected to the gate electrode 11 a.
Over the main surface of the semiconductor substrate 1, is formed an interlayer dielectric 16, from which a contact hole (second contact hole) 17 reaching the lead-out part 11 b for the gate electrode is formed. Similarly, a contact hole 18 reaching the semiconductor region 13 for channel formation is formed from the interlayer dielectric 16. The contact hole 18 is in contact with the source region 14. Note that, although not shown in FIG. 3, another contact hole (first contact hole) reaching the lead-out part 9 b for the dummy gate electrode from the interlayer dielectric 16 is formed without being in contact with the lead-out part 11 b for the gate electrode.
A polyimide resin film 27 is formed as the passivation film over the main surface of the semiconductor substrate 1 with the source electrode 24 and the gate interconnection 25 formed thereon. The polyimide resin film 27 positioned on the source pad which is a part of the source electrode 24 is removed, which causes the source pad to be exposed to the outside. A drain electrode 29 is formed on a back surface opposite to the main surface of the semiconductor substrate 1, and is a laminate consisting of, for example, a titanium (Ti) film 28 a, a nickel (Ni) film 28 b, and a gold (Au) film 28 c.
The power MISFET of the embodiment is provided with the dummy gate electrode 9 a, the function of which will be described hereinafter in detail.
In contrast, although in the power MISFET provided with the dummy gate electrode 9 a such as that shown in FIG. 3, the electric field intends to become strongest at the bottom of the trench 6 of the dummy gate electrode 9 a, the presence of the insulating film 7 which is thicker than the gate insulating film 10 is likely to release the electric filed between the dummy gate electrode 9 a and the drain region. This power MISFET can improve the withstand voltage (BVdss) as compared with the power MISFET not provided with the dummy gate electrode 9 a.
Furthermore, the provision of the dummy gate electrode 9 a has the following advantages. Generally, in the power MISFET, the gate insulating film is thinned thereby to improve the performance thereof. However, the power MISFET without the dummy gate electrode 9 a has a disadvantage that the gate insulating film cannot be thinned so much. That is, although in the power MISFET not provided with the dummy gate electrode 9 a, the gate electrode is formed inside the trench via the gate insulating film, there exists a weak spot at the corner of the trench where the defective formation of the gate insulating film intends to occur. This makes it impossible to thin the gate insulating film.
Then, as shown in FIG. 10, p-type impurities, such as boron (B), are introduced into the polycrystalline silicon film 8 formed over the semiconductor substrate 1 using the ion implantation method to form a p−-type semiconductor region 8 a. Thereafter, as shown in FIG. 11, a high concentration of n-type impurities is introduced into the p−-type semiconductor region 8 a of the power MISFET using the photolithography technique and the ion implantation method to form an n+-type semiconductor region 8 b. The n-type impurities include, for example, phosphorus (P), arsenic (As) and antimony (Sb) Subsequently, heat treatment (annealing process) is applied to the semiconductor substrate 1 at a temperature of, for example, 1100 degrees (° C.) or more. This heat treatment is carried out so as to increase a grain size (crystal grain size) of the polycrystalline silicon film 8 constituting the p−-type semiconductor region 8 a and the n+-type semiconductor region 8 b, As mentioned later, because the grain size of the p−-type semiconductor region 8 a, which is apart of the protective diode, is increased, the p−-type semiconductor region 8 a can decrease a leakage current from the protective diode. This is because the grain size of the semiconductor region 8 a is increased by high-temperature heat treatment, which leads to reduction in grain boundary across the pn junction of the protective diode (a boundary of the crystal grain). That is, since the grain boundary which may be the path of the leakage current, is reduced, the leakage current of the protective diode can be decreased. This high-temperature heat treatment is desirably carried out before forming the semiconductor region for the channel formation, as mentioned later. If the high-temperature heat treatment were carried out after forming the semiconductor region for the channel formation, the semiconductor region for the channel formation would be diffused, thus failing to achieve shallow junction of the channel part, which might be at a disadvantage in enhancing the performance of the power MISFET.
Then, as shown in FIG. 12, the polycrystalline silicon film 8 including the n+-type semiconductor region 8 b is subjected to patterning using the photolithography technique and the etching technique. Thus, the polycrystalline silicon film 8 formed in the trench 6 is etched up to a mid-point of the depth thereof to form the dummy gate electrode 9 a in the trench 6. The lead-out part 9 b for the dummy gate electrode is formed on the semiconductor substrate 1 by patterning. The lead-out part 9 b for the dummy gate electrode 9 a is formed so as to be electrically connected to the dummy gate electrode 9 a. At this time, the grain size of the polycrystalline silicon film 8 including the n+-type semiconductor region 8 b is increased by the above-mentioned heat treatment. This can effectively prevent the defective formation of the dummy gate electrode 9 a.
Then, as shown in FIG. 13, the insulating film 7 is subjected to patterning by the photolithography and etching techniques. FIG. 14 illustrates a plan view of the chip region CR subjected to the above-mentioned steps. In FIG. 14, in the protective diode forming region, the p−-type semiconductor region (anode region) 8 a is formed, while, in the outer periphery of the power MISFET forming region, the lead-out part 9 b for the dummy gate electrode is formed.
The polycrystalline silicon film (second polycrystalline silicon film) is formed over the semiconductor substrate 1 as well as on the gate insulating film 10. This polycrystalline silicon film is formed by, for example, the CVD method, with the n-type impurities added thereinto. That is, in forming the polycrystalline silicon film, for example, then-type impurities, such as phosphorus or arsenic, are introduced into the polycrystalline silicon film. Thereafter, using the photolithography and etching techniques, the polycrystalline silicon film is subjected to patterning to form the gate electrode 11 a in the trench 6. The gate electrode 11 a has a recessed structure lower than the top part on the main surface side of the semiconductor substrate 1. By the application of patterning to the polycrystalline silicon film, the lead-out part 11 b for the gate electrode is formed. The lead-out part 11 b for the gate electrode is electrically connected to the gate electrode 11 a.
The concentration of the n-type impurities introduced into the gate electrode 11 a is higher than that of the n-type impurities introduced into the dummy gate electrode 9 a. In other words, the resistance of the gate electrode 11 a is low as compared with that of the dummy gate electrode 9 a. This is because the higher resistance of the gate electrode 11 a makes it difficult for the power MISFETs connected in parallel to act uniformly. That is, if the power MISFETs do not operate uniformly, the electrostatic breakdown resistance of the gate insulating film, and the avalanche resistance may be decreased, and the switching speed may become slow disadvantageously. Note that when the power MOS is turned off with the dielectric load being connected, a voltage consisting of the sum of a power supply voltage and an induced electromotive force is instantaneously applied between the source region and the drain region. When this voltage exceeds the withstand voltage, the device becomes the avalanche breakdown condition. The avalanche resistance means the product of the maximum value of the avalanche current passing through without causing the breakdown, and the time (that is, the avalanche energy) at this time. To prevent such inconveniences, it is necessary to decrease the resistance of the gate electrode 11 a. For this reason, in formation of the gate electrode 11 a, the polycrystalline silicon film into which impurities, such as phosphorous or arsenic, are previously added, is used. The polycrystalline silicon film into which the impurities are previously added can achieve reduction in resistance of the polycrystalline silicon film, as compared with the polycrystalline silicon film which is formed without addition of the impurities, and then has the impurities introduced by the ion implantation. For example, the polycrystalline silicon film of 500 nm in thickness to which the impurities are previously added can decrease the sheet resistance to about 10Ω/□. In contrast, the polycrystalline silicon film of 500 nm in thickness into which the impurities are introduced by the ion implantation method cannot decrease the sheet resistance only up to about 20Ω/□. Therefore, the polycrystalline silicon film into which the impurities are previously added is used to form the gate electrode 11 a.
On the other hand, the dummy gate electrode 9 a, which is different from the gate electrode 11 a of the power MISFET, does not make it difficult for the power MISFETs connected in parallel to act uniformly even if it has a higher resistance than that of the gate electrode 11 a. Moreover, since the dummy gate electrode 9 a is covered with the insulating film 7 whose thickness is greater than that of the gate insulating film 10, the dummy gate electrode 9 a is likely to ensure the electrostatic breakdown resistance even if the resistance of the dummy gate electrode is higher than that of the gate electrode 11 a. Therefore, the dummy gate electrode 9 a can be the polycrystalline silicon film which is made by forming an intrinsic polycrystalline silicon film without addition of impurities, and introducing the impurities into the intrinsic polycrystalline silicon film using the ion implantation method. It should be noted that the dummy gate electrode 9 a can be made of the polycrystalline silicon film into which the impurities are previously added. In the present embodiment, however, since the polycrystalline silicon film for the protective diode and the polycrystalline silicon film for the dummy gate electrode 9 a are simultaneously formed, the polycrystalline silicon film into which the impurities are previously added cannot be used for the formation of the dummy gate electrode 9 a. That is, in the polycrystalline silicon film into which the impurities are previously added, the concentration of the impurities introduced is high, and thus the polycrystalline silicon film cannot be used to form the protective diode. Thus, the polycrystalline silicon film of the protective diode cannot be formed at the same time when the gate electrode 11 a is formed using the polycrystalline silicon film with the impurities previously added thereto. In contrast, since the intrinsic polycrystalline silicon film can be used in the formation of the dummy gate electrode 9 a, the polycrystalline silicon film of the protective diode can be formed at the same time as that of forming the polycrystalline silicon film of the dummy gate electrode. For this reason, in the embodiment, the polycrystalline silicon film for the dummy gate electrode 9 a and the polycrystalline silicon film for the protective diode are simultaneously formed.
FIG. 20 is a plan view of the chip region CR subjected to the above-mentioned steps. As shown in FIG. 20, in the protective diode forming region, the p—type semiconductor region 8 a and the n+-type semiconductor region 15 are formed to create the protective diode having the pn junction. As shown in the figure, in the power MISFET forming region, the source region 14 is formed.
In forming the protective diode having the n p−junction, the p−-type semiconductor region 8 a is formed by forming the intrinsic polycrystalline silicon film, and then implanting the boron ions into the entire surface of the intrinsic polycrystalline silicon film in a dose amount of about 1×1013/cm2 to 1×1014/cm2. In contrast, the n+-type semiconductor region 15 needs to be selectively formed. The n+-type semiconductor region 15 of the protective diode is formed at the same ion implantation step in which the source region of the power MISFET is selectively formed (at the step of introducing arsenic in an amount of about 1×1015/cm2 to 1×1016/cm2). This can form the protective diode without increasing the number of steps.
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U.S. Classification 257/401, 257/288, 257/E21.38, 257/500, 257/501, 257/E21.444, 257/E21.453, 257/287, 257/502, 257/368, 438/183, 438/270
Cooperative Classification H01L29/7808, H01L29/4238, H01L29/0696, H01L29/42368, H01L27/0255, H01L29/66545, H01L21/28556, H01L29/4916, H01L29/66484, H01L29/4236, H01L21/28008, H01L29/7811, H01L29/407, H01L29/7813, H01L29/66727, H01L29/66734, H01L29/456
European Classification H01L29/78B2T, H01L29/78B2E, H01L29/40P6, H01L29/78B2A6, H01L29/66M6T6F14V3, H01L29/66M6T6F14V4