Source: http://www.google.com/patents/US8069102?dq=7,446,777
Timestamp: 2016-02-14 02:42:11
Document Index: 173638194

Matched Legal Cases: ['Application No. 03729000', 'Application No. 03729000', 'Application No. 03729000', 'Application No. 03729000', 'Application No. 03729000', 'Application No. 03729000']

Patent US8069102 - Method and apparatus for processing financial information at hardware speeds ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method and apparatus use decision logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The decision logic can be configured to perform data reduction operations on the financial information stream. Examples of such data reductions operations...http://www.google.com/patents/US8069102?utm_source=gb-gplus-sharePatent US8069102 - Method and apparatus for processing financial information at hardware speeds using FPGA devicesAdvanced Patent SearchPublication numberUS8069102 B2Publication typeGrantApplication numberUS 11/561,615Publication dateNov 29, 2011Filing dateNov 20, 2006Priority dateMay 21, 2002Fee statusPaidAlso published asCA2486359A1, CA2486359C, EP1506501A2, US7139743, US20030018630, US20070078837, US20120116998, US20120130922, WO2003100662A2, WO2003100662A3Publication number11561615, 561615, US 8069102 B2, US 8069102B2, US-B2-8069102, US8069102 B2, US8069102B2InventorsRonald S. Indeck, Ron Kaplan Cytron, Mark Allen Franklin, Roger D. ChamberlainOriginal AssigneeWashington UniversityExport CitationBiBTeX, EndNote, RefManPatent Citations (315), Non-Patent Citations (178), Referenced by (31), Classifications (14), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod and apparatus for processing financial information at hardware speeds using FPGA devices
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