Source: http://www.google.de/patents/US8453022
Timestamp: 2017-09-19 11:51:24
Document Index: 800573275

Matched Legal Cases: ['Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 60', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61', 'Application No. 61']

Patent US8453022 - Apparatus and methods for generating row-specific reading thresholds in ... - Google Patentsuche
A method for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the method comprising predetermining at least one initial reading threshold; performing the following steps for at least one current...http://www.google.de/patents/US8453022?utm_source=gb-gplus-sharePatent US8453022 - Apparatus and methods for generating row-specific reading thresholds in flash memory
Veröffentlichungsnummer US8453022 B2
Anmeldenummer US 12/596,450
PCT-Nummer PCT/IL2008/001231
Auch veröffentlicht unter US8321625, US8341335, US8751726, US8843698, US9104550, US20100064096, US20100131809, US20100146191, US20100180073, US20130080691, US20130238839, WO2009072100A2, WO2009072100A3, WO2009072101A2, WO2009072101A3, WO2009072102A2, WO2009072102A3, WO2009072104A2, WO2009072104A3, WO2009072104A8
Veröffentlichungsnummer 12596450, 596450, PCT/2008/1231, PCT/IL/2008/001231, PCT/IL/2008/01231, PCT/IL/8/001231, PCT/IL/8/01231, PCT/IL2008/001231, PCT/IL2008/01231, PCT/IL2008001231, PCT/IL200801231, PCT/IL8/001231, PCT/IL8/01231, PCT/IL8001231, PCT/IL801231, US 8453022 B2, US 8453022B2, US-B2-8453022, US8453022 B2, US8453022B2
Erfinder Michael Katz
Patentzitate (228), Nichtpatentzitate (37), Referenziert von (56), Klassifizierungen (7), Juristische Ereignisse (6)
US 8453022 B2
1. A method for generating a set of at least one row-specific reading threshold, the method comprising:
predetermining at least one initial reading threshold;
performing the following steps for at least one current logical page:
generating bit, error characterizing information regarding at least one corresponding bit error within at least one flash memory cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and
computing each row-specific reading threshold out of at least one row-specific reading threshold based on said bit error characterizing information and on a previous threshold initially comprising an initial threshold out of the at least one initial reading threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and
reading at least a portion of said current logical page, wherein the reading comprises comparing gate voltages of flash memory cells representing the at least portion of said current logical page to said at least one row-specific reading threshold.
2. The method according to claim 1 wherein said bit error characterizing information comprises identification of a reading threshold associated with the bit error.
3. The method according to claim 1 wherein said bit error characterizing information comprises a direction of the bit error.
4. The method according to claim 1 wherein a first number of threshold errors whose direction, with respect to said previous threshold, is from left to right is compared to a second number of threshold errors whose direction, with respect to said previous threshold, is from right to left, wherein the row-specific reading threshold depends upon at least one of the sign and magnitude of the difference between said first and second numbers of threshold errors.
5. The method according to claim 1 and also comprising: selecting a subset of rows within said erase sector; and identifying a set of logical pages residing within said subset of rows; and performing said generating, computing and reading for said set of logical pages and for less than all pages in said erase sector.
6. The method according to claim 5 and wherein said generating, computing and reading are performed only for said set of logical pages.
7. The method according to claim 1 wherein said previous threshold is corrected only if a number of bit errors per page is in a process of change of at least a predetermined magnitude.
8. The method according to claim 7 wherein said previous threshold is corrected only if a difference between a number of bit errors encountered during reconstruction of said current page and a number of bit errors occurring during reconstruction of at least one previous page is larger than a predetermined number.
9. The method according to claim 1 wherein said generating is performed for at least one CSB page residing in a row corresponding to an MSB page also residing in said row, based at least partly on values read from said MSB page.
10. The method according to claim 9 wherein said generating performed for said CSB page is based at least partly on values read on-the-fly from said MSB page.
11. The method according to claim 9 wherein said generating performed for said CSB page is based at least partly on stored values previously read from said MSB page.
12. The method according to claim 1 wherein said generating is performed for an LSB page residing in a row corresponding to an MSB and at least one CSB page also residing in said row, based at least partly on values read from at least one of said MSB and CSB pages.
13. The method according to claim 12 wherein said generating performed for said LSB page is based at least partly on values read on-the-fly from at least one of said MSB and CSB pages.
14. The method according to claim 12 wherein said generating performed for said LSB page is based at least partly on stored values previously read from at least one of said MSB and CSB pages.
15. A method for using flash memory to store data, the method comprising:
writing at least one page of data to said flash memory;
reading said at least one page of data from said flash memory using a set of reading thresholds;
generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and
detecting portions of said flash memory which suffer from read-disturb phenomenon based on said bit error characterizing information.
16. The method according to claim 15 wherein said bit error characterizing information comprises identification of a reading threshold which is associated with the bit error.
17. The method according to claim 15 wherein said bit error characterizing information comprises a direction of the bit error.
18. The method according to claim 15 wherein said detecting comprises detecting an overly large number of bit errors whose source is a reading threshold which is closest, within said set of reading thresholds, to zero voltage, and whose direction is from left to right.
19. A system for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the system comprising:
apparatus for predetermining at least one initial reading threshold;
a bit error analyzer operative, for at least one current logical page, to generate bit error characterizing information regarding at least one corresponding bit error within at least one cell of the flash memory device representing at least a logical portion of at least one successfully reconstructed previous logical page;
a bit error-based threshold generator operative to compute each row-specific reading threshold out of at least one row-specific reading threshold based on said bit error characterizing information and on a previous threshold initially comprising an initial threshold out of the at least one initial thresholds and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and
a flash memory cell reader operative to read at least a portion of said current logical page by comparing gate voltages of flash memory cells representing the at least portion of said current logical page to said at least one row-specific reading threshold.
20. A system for using flash memory to store data, the system comprising:
apparatus for writing in flash memory operative to write at least one page of data to the flash memory;
a bit error characterizing reader operative to read said at least one page of data from said flash memory using a set of reading thresholds, and to generate bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and
a bit error-based controller operative to detect portions of said flash memory which suffer from read-disturb phenomenon based on said bit error characterizing information.
This application is a National Phase Application of PCT International Application No. PCT/IL2008/001231, entitled “APPARATUS AND METHODS FOR GENERATING ROW-SPECIFIC READING THRESHOLDS IN FLASH MEMORY” International Filing Date Sep. 17, 2008, published on Jun. 11, 2009 as International Publication No. WO 2009/072101, which in turn claim priority from Priority is claimed from U.S. Provisional Application No. 61/129,608, filed Jul. 8, 2008, U.S. Provisional Application No. 60/996,782, filed Dec. 5, 2007, U.S. Provisional Application No. 61/064,853, filed Mar. 31, 2008, U.S. Provisional Application No. 61/006,805, filed Jan. 31, 2008, U.S. Provisional Application No. 61/071,465, filed Apr. 30, 2008, all of which are incorporated herein by reference in their entirety.
Priority is claimed from the following co-pending applications: U.S. Provisional Application No. 61/129,608, filed Jul. 8, 2008 and entitled “A Method for Acquiring and Tracking Detection Thresholds in Flash Devices”, U.S. Provisional Application No. 60/996,782, filed Dec. 5, 2007 and entitled “Systems and Methods for Using a Training Sequence in Flash Memory”, U.S. Provisional Application No. 61/064,853, filed Mar. 31, 2008 and entitled “Flash Memory Device with Physical Cell Value Deterioration Accommodation and Methods Useful in Conjunction Therewith”, U.S. Provisional Application No. 61/006,805, filed Jan. 31, 2008 and entitled “A Method for Extending the Life of Flash Devices” and U.S. Provisional Application No. 61/071,465, filed Apr. 30, 2008 and entitled “Systems and Methods for Temporarily Retiring Memory Portions”.
Other co-pending applications include: U.S. Provisional Application No. 60/960,207, filed Sep. 20, 2007 and entitled “Systems and Methods for Coupling Detection in Flash Memory”, U.S. Provisional Application No. 61/071,467, filed Apr. 30, 2008 and entitled “Improved Systems and Methods for Determining Logical Values of Coupled Flash Memory Cells”, U.S. Provisional Application No. 60/960,943, filed Oct. 22, 2007 and entitled “Systems and methods to reduce errors in Solid State Disks and Large Flash Devices” and U.S. Provisional Application No. 61/071,469, filed Apr. 30, 2008 and entitled “Systems and Methods for Averaging Error Rates in Non-Volatile Devices and Storage Systems”, U.S. Provisional Application No. 60/996,027, filed Oct. 25, 2007 and entitled “Systems and Methods for Coping with Variable Bit Error Rates in Flash Devices”, U.S. Provisional Application No. 61/071,466, filed Apr. 30, 2008 and entitled “Systems and Methods for Multiple Coding Rates in Flash Devices”, U.S. Provisional Application No. 61/006,120, filed Dec. 19, 2007 and entitled “Systems and Methods for Coping with Multi Stage Decoding in Flash Devices”, U.S. Provisional Application No. 61/071,464, filed Apr. 30, 2008 and entitled “A Decoder Operative to Effect A Plurality of Decoding Stages Upon Flash Memory Data and Methods Useful in Conjunction Therewith”, U.S. Provisional Application No. 61/006,385, filed Jan. 10, 2008 and entitled “A System for Error Correction Encoder and Decoder Using the Lee Metric and Adapted to Work on Multi-Level Physical Media”, U.S. Provisional Application No. 61/064,995, filed Apr. 8, 2008 and entitled “Systems and Methods for Error Correction and Decoding on Multi-Level Physical Media”, U.S. Provisional Application No. 60/996,948, filed Dec. 12, 2007 and entitled “Low Power BCH/RS Decoding: a Low Power Chien-Search Implementation”, U.S. Provisional Application No. 61/071,487, filed May 1, 2008 and entitled “Chien-Search System Employing a Clock-Gating Scheme to Save Power for Error Correction Decoder and other Applications”, U.S. Provisional Application No. 61/071,468, filed Apr. 30, 2008 and entitled “A Low Power Chien-Search Based BCH/RS Recoding System for Flash Memory, Mobile Communications Devices and Other Applications”, U.S. Provisional Application No. 61/006,806, filed Jan. 31, 2008 and entitled “Systems and Methods for using a Erasure Coding in Flash memory”, U.S. Provisional Application No. 61/071,486, filed May 1, 2008 and entitled “Systems and Methods for Handling Immediate Data Errors in Flash Memory”, U.S. Provisional Application No. 61/006,078, filed Dec. 18, 2007 and entitled “Systems and Methods for Multi Rate Coding in Multi Level Flash Devices”, U.S. Provisional Application No. 61/064,923, filed Apr. 30, 2008 and entitled “Apparatus For Coding At A Plurality Of Rates In Multi-Level Flash Memory Systems, And Methods Useful In Conjunction Therewith”, U.S. Provisional Application No. 61/064,760, filed Mar. 25, 2008 and entitled “Hardware efficient implementation of rounding in fixed-point arithmetic”, U.S. Provisional Application No. 61/071,404, filed Apr. 28, 2008 and entitled “Apparatus and Methods for Hardware-Efficient Unbiased Rounding”, U.S. Provisional Application No. 61/136,234, filed Aug. 20, 2008 and entitled “A Method Of Reprogramming A Non-Volatile Memory Device Without Performing An Erase Operation”, U.S. Provisional Application No. 61/129,414, filed Jun. 25, 2008 and entitled “Improved Programming Speed in Flash Devices Using Adaptive Programming”, and several other co-pending patent applications being filed concurrently (same day).
[1] Paulo Cappelletti, Clara Golla, Piero Olivo, Enrico Zanoni, “Flash Memories”, Kluwer Academic Publishers, 1999.
[2] G. Campardo, R. Micheloni, D. Novosel, “VLSI-Design of Non-Volatile Memories”, Springer Berlin Heidelberg N.Y., 2005.
[3] G. Proakis, “Digital Communications,” 3rd ed., New York: McGraw-Hill, 1995.
[4] P. Cappelletti et al., “Flash Memories,” Kluwer, 1999.
“Read-disturb” is a known phenomenon whereby following a great many read operations performed on one or more particular physical pages within an erase sector, there is a deterioration in the quality of those physical pages or more typically in the quality of the entire erase sector. Typically, un-programmed cells tend to behave as though they were programmed, causing read errors.
Logical page: a portion of typically sequential data, whose amount is typically less than or equal to a predetermined amount of data defined to be a pageful of data, which has typically been defined by a host (data source/destination) or user thereof, as a page, and which is sent by the host to a flash memory device for storage and is subsequently read by the host from the flash memory device.
Physical Page=A portion, typically 512 or 2048 or 4096 bytes in size, of a flash memory e.g. a NAND or NOR flash memory device. Writing and reading is typically performed physical page by physical page, as opposed to erasing which can be performed only erase sector by erase sector. A few bytes, typically 16-32 for every 512 data bytes are associated with each page (typically 16, 64 or 128 per page), for storage of error correction information. A typical block may include 32 512-byte pages or 64 2048-byte pages. Alternatively, a physical page is an ordered set (e.g. sequence or array) of flash memory cells which are all written in simultaneously by each write operation, the set typically comprising a predetermined number of typically physically adjacent flash memory cells containing actual data written by and subsequently read by the host, as well as, typically error correction information and back pointers used for recognizing the true address of a page.
Precise read, soft read: Cell threshold voltages are read at a precision (number of bits) greater than the number of Mapping levels (2^n). The terms precise read or soft read are interchangeable. In contrast, in “hard read”, cell threshold voltages are read at a precision (number of bits) smaller than, or equal to, the number of mapping levels (2^n where n=number of bits per cell).
Resolution: Number of levels in each cell, which in turn determines the number of bits the cell can store; typically a cell with 2^An levels stores n bits. Low resolution (partitioning the window, W, of physical values a cell can assume into a small rather than large number of levels per cell) provides high reliability.
Retention: Retention of original physical levels induced in the flash memory cells despite time which has elapsed and despite previous erase/write cycles; retention is typically below 100% resulting in deterioration of original physical levels into present levels.
Threshold level or “decision level”: the voltage (e.g.) against which the charge level of a cell is measured. For example, a cell may be said to store a particular digital n-tuple D if the charge level or other physical level of the cell falls between two threshold values T.
In the present specification, the terms “row” and “column” refer to rows of cells and columns of cells, respectively and are not references to sub-divisions of a logical page.
The term “MSB” is used herein to denote the bit which is programmed into a multi-level cell, storing several bits, first. The term “LSB” is used herein to denote the bit which is programmed into the multi-level cell, last. The term “CSB” is used herein to denote the bit which is programmed into a 3-level cell, storing 3 bits, second, i.e. after the MSB and before the LSB. It is appreciated that more generally, e.g. if the multi-level cell stores 4 or more levels, there are more than one CSBs and use of the term “CSB” herein, which implies that the cell is a 3-level cell, is merely by way of example and is not intended to be limiting.
A logical page is a set of bytes which is meaningful to an application. The location of a logical page in memory is termed herein a physical page. This location may comprise certain cells in their entirety, or, more commonly, may comprise only one or some bits within certain cells. The locations of each of a sequence of logical pages (page 0, page 1, page 2, . . . ) within memory is pre-determined by a suitable mapping scheme mapping logical pages into the bits of the cells of a particular erase sector (block) in flash memory.
“Successfully reconstructed” means that using error correction code, the original logical page has been reconstructed generally satisfactorily, e.g., typically, that the logical page has been read, using reading thresholds, has undergone error correction as appropriate and has successfully passed its CRC (cyclic redundancy check) criterion.
“Bit errors” are those errors found in the physical page corresponding to a logical page, which typically are corrected using ECC (error correction code) such that the page is successfully reconstructed despite these errors.
The term “reading threshold” and “detection threshold” are used generally interchangeably.
The term “directed threshold errors” refers to events in which a cell which was programmed to one program level is erroneously interpreted, upon performing a read operation, as being programmed to another program level. A directed threshold error is described by stating the index of the threshold lying between the cell's program level and the erroneously read program level and which is closest to the cell's actual program level, as well as the direction of the error, i.e. “right to left” if the cell was misinterpreted as being programmed to a program level residing to the left of the cell's program level, and “left to right” if the cell was misinterpreted as being programmed to a program level residing to the right of the cell's program level.
Certain embodiments of the present invention seek to provide improved flash memory device.
Certain embodiments of the present invention seek to provide inference methods in Flash Memory Devices based on analysis of bit error patterns.
Certain embodiments of the present invention seek to provide a method for correcting at least one detection threshold for reading the data of at least one page within an erase sector of a flash memory device, the method comprising associating the bit errors of at least one previous successfully read page to corresponding directed threshold errors and choosing a corrected threshold based on the previous detection threshold and number of the directed threshold errors.
Certain embodiments of the present invention seek to provide a method for associating at least one bit error of at least one successfully decoded page within an erase sector of a flash device to a corresponding directed threshold error.
Certain embodiments of the present invention seek to provide a method for performing tracking of at least one detection threshold for reading the data of at least one page within an erase sector of a flash memory device wherein previously decoded pages are used.
There is thus provided, in accordance with certain embodiments of the present invention, a method for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the method comprising predetermining at least one initial reading threshold, performing the following steps for at least one current logical page: generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and computing at least one row-specific reading threshold based on the bit error characterizing information and on a previous threshold initially comprising the initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and reading at least a portion of the current logical page using the at least one row-specific reading threshold.
It is appreciated that the above row-specific method is performed locally, i.e. for local regions within a flash memory device being read, e.g. for each row in the flash memory, or for some individual rows, or for each of a number of sets each comprising a relatively small number of typically adjacent rows.
According to certain embodiments of the present invention the detection thresholds are corrected only for a subset of pages in the erase sector wherein the subset of pages is chosen such that the correction will be done on detection thresholds which were used on a subset of rows within an erase sector.
According to certain embodiments of the present invention thresholds are corrected only if the difference between the total error count associated with the decoding of the page and the total error count associated with the decoding of the previous page is larger than some number.
It is appreciated that a reading threshold is associated with each bit error in that a wrong logical value is assigned to a bit when a physical value induced in the cell in which the bit resides, falls so far along one of the two tail ends of the voltage (e.g.) distribution of the logical value as to exceed the upper threshold of the programmed value or so as to fall below the lower threshold of the programmed value. In the first instance, the upper threshold is associated with the bit error and the direction of the bit error is termed “left to right”. In the second instance, the lower threshold is associated with the bit error and the direction of the bit error is termed “right to left”.
The predetermined number is typically selected to be relatively large so that the reading threshold correction process is only initiated when a very significant rise in bit error frequency is detected. For example, if the page size is, say, 4 K bytes, an increase in the number of bit errors per page of the order of magnitude of dozens or hundreds of bit errors might trigger a reading threshold correction process such as those shown and described herein.
Additionally in accordance with certain embodiments of the present invention, the generating performed for the CSB page is based at least partly on stored values previously read from the MSB page.
Further in accordance with certain embodiments of the present invention, the generating performed for the LSB page is based at least partly on stored values previously read from at least one of the MSB and CSB pages.
It is appreciated that the values read from the MSB and/or CSB pages may be read from a buffer which stored these pages, perhaps when they were originally read, or may be a re-read of a page which has already been read at least once either only for reading its own data, or also in order to perform the teachings of this invention, say, for a CSB page preceding the current page which is an LSB page. The buffer is typically located within a controller external to a flash memory device although alternatively it may be located within an internal controller.
Also provided, in accordance with another embodiment of the present invention, is a method for using flash memory to store data, the method comprising writing at least one page of data to the flash memory, reading the at least one page of data from the flash memory using a set of reading thresholds, including generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and subsequently, using the flash memory so as to take into account the bit error characterizing information.
Further in accordance with certain embodiments of the present invention, the bit error characterizing information comprises identification of a reading threshold which is associated with the bit error.
Additionally in accordance with certain embodiments of the present invention, the using comprises reading at least one subsequent page of data so as to take into account the bit error characterizing information.
Further in accordance with certain embodiments of the present invention, the using comprises detecting portions of the flash memory which suffer from read-disturb phenomenon based on the bit error characterizing information.
FIG. 1 is a simplified block diagram of a flash memory system constructed and operative in accordance with certain embodiments of the present invention;
FIG. 2 is a simplified functional block diagram illustration of the bit-error analyzing controller 102 of FIG. 1, according to certain embodiments of the present invention;
FIG. 3 is a theoretical graph of voltage distributions conditional on program levels which is useful in understanding certain embodiments of the present invention;
FIG. 4A-4C, taken together, are a diagram depicting mapping from data bits to program levels and threshold crossover errors which is useful in understanding certain embodiments of the present invention;
FIGS. 5A-5B, taken together, form a simplified flowchart illustration of a method for correcting reading thresholds by tracking bit error patterns, which method may for example be performed by the system of FIGS. 1-2, the method being operative according to certain embodiments of the present invention;
FIG. 6 is a simplified flowchart illustration of a method for performing the “bit error to threshold error” step in FIGS. 5A-5B for an MSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof;
FIG. 7 is a simplified flowchart illustration of a method for performing the “bit error to threshold error” step in FIGS. 5A-5B for a CSB page, assuming, which of course need not be the case, that the cells in each page are 3-level cells (i.e. assuming for simplicity that there is only one CSB page), the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof;
FIGS. 8A-8B, taken together, form a simplified flowchart illustration of a method for performing the “bit error to threshold error” step in FIGS. 5A-5B for an LSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof;
FIG. 9 is a simplified flowchart illustration of a method for performing the threshold updating step in FIGS. 5A-5B for either an MSB, CSB, or an LSB page;
FIG. 11 is a simplified flowchart illustration of a modification of the method of FIGS. 5A-5B in which tracking activation is diluted;
FIG. 12 is a simplified flowchart illustration of a method for accessing the page-to-row lookup table corresponding to the mapping type;
FIG. 13 is a table comprising a mapping between logical pages and physical pages which is useful in understanding certain embodiments of the present invention;
FIG. 16 is a look-up-table based on the mapping in FIG. 14 which associates for each page index the corresponding row index where the logical page resides, and which is useful in understanding certain embodiments of the present invention;
FIG. 17 is a simplified flowchart illustration of a modification of the method of FIGS. 5A-5B in which tracking activation is conditional, the method being operative according to certain embodiments of the present invention;
FIG. 18 is a generalized flowchart illustration of a method of operation of the system of FIGS. 1-2, the method being operative according to certain embodiments of the present invention; and
FIG. 19 is a simplified flowchart illustration of a method for using flash memory to store data, the method being operative in accordance with certain embodiments of the present invention.
In the present specification, the terms “row” and “column” as used herein are intended to include rows of cells and columns of cells, respectively and are not references to sub-divisions of a logical page.
The term “MSB” as used herein is intended to include the bit which is programmed into a multi-level cell, storing several bits, first. The term “LSB” as used herein is intended to include the bit which is programmed into the multi-level cell, last. The term “CSB” as used herein is intended to include the bit which is programmed into a 3-level cell, storing 3 bits, second, i.e. after the MSB and before the LSB. It is appreciated that more generally, e.g. if the multi-level cell stores 4 or more levels, there are more than one CSBs and use of the term “CSB” herein, which implies that the cell is a 3-level cell, is merely by way of example and is not intended to be limiting.
A logical page as used herein is intended to include a set of bytes which is meaningful to an application. The location of a logical page in memory is termed herein a physical page. This location may comprise certain cells in their entirety, or, more commonly, may comprise only one or some bits within certain cells. The locations of each of a logical sequence of logical pages (page 0, page 1, page 2, . . . ) within memory is pre-determined by a suitable mapping scheme mapping logical pages into the bits of the cells of a particular erase sector (block) in flash memory.
“Successfully reconstructed” as used herein is intended to include situations in which, using error correction code, the original logical page has been reconstructed generally satisfactorily, e.g., typically, that the logical page has been read, using reading thresholds, has undergone error correction as appropriate and has successfully passed its CRC (cyclic redundancy check) criterion.
“Bit errors” as used herein is intended to include those errors found in the physical page corresponding to a logical page, which typically are corrected using ECC (error correction code) such that the page is successfully reconstructed despite these errors.
The terms “reading threshold” and “detection threshold” are used generally interchangeably.
Reference is now made to FIG. 1 which is a simplified block diagram of a flash memory system constructed and operative in accordance with certain embodiments of the present invention. As shown, the flash memory system of FIG. 1 includes a host or outside application 100 which interfaces, via an interface controller 102, with a flash memory device 105. An internal microcontroller 110 typically manages the functional units of the flash memory device 105. The storage portion of the flash memory device includes one or more typically many erase sectors 120 each storing one or more typically many physical pages 130 each including one or more typically many cells 140 having more than one possible state such that logical values may be stored therein. Erasing circuitry 150 is provided to erase data from cells, writing circuitry 160 writes data into cells, and reading circuitry 170 reads data from cells.
A particular feature of the system shown in FIG. 1 by way of example is the bit-error analyzing functionalities of the I/F controller 102 and/or of the internal micro-controller 110.
FIG. 2 is a simplified functional block diagram illustration of the bit-error analyzing controller 102 of FIG. 1, according to certain embodiments of the present invention. As shown, the controller 102 may include a bit error characterization block 200 which provides information regarding bit errors' characteristics, particularly joint characteristics, to application functionalities such as but not limited to a read threshold computation unit 210 and/or a read-disturb event finder 220. Optionally, a buffer 230 is provided which is useful for reading MSB and CSB pages as described in detail herein. The buffer 230 serves the characterizer of bit errors 200 which in turn serves read threshold computation unit 210 and/or read-disturb event finder 220.
The system of FIGS. 1-2 is particularly suitable for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device. This method may comprise some or all of the following steps, as shown in FIG. 18:
Step 3020: performing steps 3030 and 3040 for each of at least one current logical pages.
Step 3030: generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page.
Conventionally, flash memory devices store information as charge in “cells”, each made of either a floating gate transistor or an NROM transistor. In single-level cell (SLC) devices, each cell stores only one bit of information. Multi-level cell (MLC) devices can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of their cells. The amount of charge (also known as charge level) is then measured by a detector, by comparing the voltage of the transistor gate (also known as charge level and denoted VT) to a decision threshold voltage (also known as charge level boundary point and denoted VD). The amount of charge is then used to determine the programmed level (logical value) of the cell. Due to inaccuracies during the programming procedure and charge loss due to time and temperature (also known as retention), the measured levels suffer from a random distortion. Prior art FIG. 3 illustrates an example of the eight separate probability distributions of a cell which can be programmed with one of eight corresponding program levels (111, 110, 100, 101, 001, 000, 010, and 011, respectively). For each distribution curve, the Y-axis represents the probability that the cell is programmed to the corresponding level, given the value of the charge level VT (represented by the x-axis).
A particular feature of certain embodiments of the present invention, is that changes in the distributions of the programming lobes illustrated in FIG. 3 are tracked between pages, using a suitable indicator of such changes such as bit error characteristics including associated threshold and direction of each bit error, all as described in detail below.
The cell's programmed level may be determined using several methods. One method is to apply a voltage to the cell's gate and measure if the cell conducts current. The cell has a certain threshold voltage such that if voltage above that threshold is applied to the gate, the gate will conduct. Below that threshold voltage the gate will not conduct current (or will conduct a small amount of current, below a certain demarcation level). As the amount of charge in the cell changes this threshold voltage, the charge may be inferred by determining at which voltage the cell starts to conduct current. Thus, the programmed level is determined by iteratively applying different voltages to the gate and measuring whether the cells conduct or not. Another method is based on the fact that when applying a voltage above the threshold voltage, the cell conducts current and the amount of current depends on the difference between the applied voltage and the threshold voltage. As the threshold voltage changes as a function of the amount of charge in the cell, the programmed level may be inferred by measuring the current going through the cell.
In general, if there are L possible program levels, then L−1 decision threshold levels are employed. As the probability distributions extend beyond the decision threshold levels, there is a probability of detection error, i.e. detecting the wrong program level. In order to minimize the detection error, one wishes to set the decision threshold levels optimally. The optimal placement of the decision thresholds levels in terms of minimizing the detection error probability generally depends on the probability distribution associated with the VT level of the cells. The statistical behavior of the cells' VT level can be approximated by Gaussian distributions. The optimal placement of the detection threshold for the Gaussian case is a known function of the means and standard deviations (STDs) of the Gaussian distributions. In other words, knowledge of good decision thresholds (assuming the Gaussian assumption is correct) is possible if the means and STDs of the cells' VT distributions are known.
Since the means and STDs of the probability distributions change as a result of cycling and retention, it is not clear how to set the decision thresholds when attempting to read a given page storing information. Setting the decision thresholds to the optimal position corresponding to a fresh device might show acceptable performance only if the page was recently programmed and not retained for a significant amount of time. Similarly, setting the decision thresholds to fit a device which was cycled 1000 times and retained for 10 years might not work, i.e. cause too many detection errors, if the page in question was recently written to a non-cycled flash device.
In some applications, this situation calls for a training stage in which the flash device's controller learns the “state” of the page/block and determines a set of decision thresholds which will yield preferably as little detection errors as possible when used to read the page.
Since some variations exist in the statistics of the program levels between different blocks within one flash device, and between different pages within one erase sector, it is appreciated that one cannot hope to find a single choice of thresholds which will be appropriate, i.e. yield a sufficiently high uncoded bit error rate (UBER), for all the pages in the flash device. One solution is to use the training process for every page to be read, or for every page for which it is suspected that the detection thresholds previously obtained are not sufficiently accurate. Depending on the complexity of the training process, such a solution might be too costly, and might jeopardize the feasibility of certain flash applications.
Certain embodiments of this invention include a way for adapting the detection thresholds from one page to the next in such a way which considerably limits the number of training operations employed to read an entire population of blocks of a flash device. The adaptation is done either without or with very little additional reading operations from the flash device. In certain embodiments, the adaptation is done based on the bit error pattern obtained after successful decoding of the error correcting code (ECC).
The embodiment described above also has applications for coping with read disturb. Read disturb is a situation where the voltages applied to the row and column of a target memory floating gate cell in order to perform the read operation, cause unwanted programming to erased cells which lie on the same column as the target cell. This unwanted programming accumulates over time after successive read operations to the degree of causing cells in the erased state to be in programmed states.
Certain embodiments of this invention use the bit error patterns to identify a block which is suffering from a severe read disturb and if left unchanged might reach a state where the data stored in it becomes undetectable.
Also described herein are variations on the above embodiments which account for performance trade-offs.
According to certain embodiments of the present invention, tracking of the changes in the detection thresholds which occur between successive pages in a flash array is provided. The tracking is performed by analyzing the asymmetry between errors which occur due to cells' V1 levels crossing the detection thresholds from left to right and errors which occur due to cells' VT levels crossing the detection thresholds from right to left. The detection thresholds are modified according to the sign and magnitude of the difference between the two types of threshold errors. The tracking operation guarantees that detection thresholds adapt to the changes in the threshold voltage distributions without the need to perform multiple training procedures which may be costly in terms of flash read operations.
Certain embodiments of this invention seek to perform the above functionalities in a manner which saves processing time e.g. by performing the tracking procedure only for certain rows/pages within an erase sector, and/or by performing the tracking procedure only when the total number of errors increases drastically with respect to previous rows/pages. Certain embodiments of this invention seek to perform the above functionalities in a manner which saves memory requirements e.g. by performing read operations from the flash “on the fly” in order to associate bit errors to the threshold errors.
By way of example, consider a floating gate flash memory device where each cell has 8 possible charge levels (or program levels), thus storing 3 bits per cell. That said, certain embodiments of this invention are also applicable to NROM flash devices and/or flash devices with less or more charge levels. The page to be read has been written to a flash device after an unknown number of program/erase cycles, and the data in the page was retained for an unknown period of time. Denote the number of cells in the page by Nc. Denote the means of the cells' VT level distributions by μ1, μ2, . . . , μ8, where the index 1 corresponds to the erase level, index 2 corresponds to the program level closest to the erased state, and so on. Furthermore, denote by σ1, σ2, . . . , σ8 the standard deviations (STDs) of these distributions, respectively. Finally, denote by T1, T2, . . . , T7 the detection thresholds which are to be used for reading the page. An approximation to the optimal detection thresholds is given by the following formula:
T k = σ k + 1 μ k + σ k μ k + 1 σ k + σ k + 1 , k = 1 , 2 , … , 7.
In the example shown and described herein, the mapping between data bits and cell program levels is depicted in prior art FIG. 4. Each combination of bits corresponding to a specific selection of MSB, CSB, and LSB is mapped to one of eight program levels as shown in FIG. 4. The dashed vertical lines mark the reading thresholds. In order to read the MSB, a single threshold is used. Cells which conduct current when this threshold is applied to their gate are interpreted as having their MSB equal to 1, while the remaining cells are identified as having their MSB equal 0. The reading of the CSB employs two thresholds. Cells which conduct when the left threshold is applied to them and cells which do not conduct (even) if the right threshold is applied to them are identified as having their CSB equal 1, while the cells which do not conduct when the left threshold is applied to them but conduct current when the right threshold is applied to them are interpreted as having their CSB equal 0. For the LSB, four thresholds are employed. Cells whose VT lies between T1 and T2 or between T3 and T4 are interpreted as having their LSB equal 0, while for the remaining cells, the LSB is read as 1.
The curved arrows above each detection threshold designate errors resulting from threshold voltages of some cells appearing in the detection regions of their neighboring cells. For example, assume a cell was programmed to level 3, but due to programming error and/or retention effects, the actual threshold voltage at the time the cell is to be read is just to the left of T1 in the second graph of FIG. 4. When T1 is applied to this cell, it will conduct current and its CSB bit will be erroneously interpreted as a 1 even though its CSB was 0. Such an error event is marked by the bold solid curved arrow above T1 in the second graph of FIG. 4. Similarly, the remaining dashed curved arrows designate threshold errors from left to right, while the solid arrows mark errors from right to left. These threshold errors are termed herein “directed threshold errors”.
The tracking process may proceed as depicted in FIGS. 5A-5B. It is appreciated that T1-T4 in FIGS. 5A-5B are defined by FIG. 4. Once a page within a block of a flash device is successfully decoded, the corrected page bits are passed to the tracking block along with the location of the erroneous bits, the page bit type (MSB, CSB, or LSB), and the set of thresholds which was used to read the page. If the page is an MSB page, only one threshold is supplied. If the page is a CSB page, 2 thresholds are given, and finally, tracking of an LSB page uses knowledge of four detection thresholds.
Next, the process maps each bit error to a directed threshold error event and updates an appropriate counter. For each threshold, two counters are used, one counting threshold errors from left to right, and another which counts errors from right to left. Once all the errors in the page are processed, the corresponding thresholds are corrected in the appropriate direction as a function of the asymmetry in the number of threshold errors. In one embodiment, the difference between the threshold errors from left to right and from right to left is computed for every threshold, and according to the difference's sign and magnitude an appropriate quantity is either added to or subtracted from the original threshold. The procedure described in FIGS. 5A-5B is repeated for every page which is successfully decoded.
The way in which the bit errors are mapped to threshold error events depends on the type of page which is being tracked. For example, assuming here and throughout the present specification, that standard gray level coding is used, the mapping may be as shown in FIGS. 6-8. Specifically, FIG. 6 is a simplified flowchart illustration of a method for performing the “bit error to threshold error” step in FIGS. 5A-5B for an MSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof.
FIG. 7 is a simplified flowchart illustration of a method for performing the “bit error to threshold error” step in FIGS. 5A-5B for a CSB page, assuming that the cells in each page are 3-level cells (i.e. assuming for simplicity that there is only one CSB page), the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof.
FIGS. 8A-8B, taken together, form a simplified flowchart illustration of a method for performing the “bit error to threshold error” step in FIGS. 5A-5B for an LSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof.
It is appreciated that in the case of an MSB page, as shown in FIG. 6, each bit error of the form 0→1 corresponds to a threshold error from right to left, and each bit error of the form 1→0 is a result of a threshold error from left to right. As shown in FIG. 7, in the case of a CSB page in a certain physical row, the mapping depends on the corresponding bit in the MSB page residing in the same physical row. For instance, a bit error event of the form 0→1 can be interpreted as a right-to-left threshold error event of threshold T1, if the MSB bit equals 1, or as a left-to-right threshold error event of threshold T2, if the MSB bit equals 0. Similarly, as shown in FIGS. 8A-8B, the mapping of bit errors to threshold error events for an LSB page typically comprises using knowledge of the MSB and CSB bits in the corresponding cells residing in the same physical row. Depending on the order in which the pages are written to and read from the erase sector, and depending on the mapping between logical pages and physical pages (and rows), a buffer may be used in order to store the values of the MSB and CSB pages for future tracking of CSB and LSB pages.
For instance, if the LSB page of a certain row is always written d pages after the MSB page of the same row, a buffer of length at least d may be used to guarantee that upon decoding of the LSB page, the MSB page of the same row is available.
Identification of Read Disturbs according to certain embodiments of the present invention is now described in detail.
In flash memories, the read procedure involves the application of certain voltages to the word line corresponding to the row address of the read cell as well as the bit line corresponding to the column address of the cell. These voltages are of the same kind as those which are applied during programming, only lower in magnitude. The voltage applied to the bit line may induce a small charge transfer to the floating gate. While the charge transfer which occurs in any individual read operation is limited due to the relatively low voltage applied to the bit line, the cumulative effect of many (˜100,000) read operations might cause a significant charge increase in the floating gate. This phenomenon may cause cells which are in the erased state and which share the same bit line as the cell being read to become programmed. Furthermore, since all the cells along a bit line are affected by this disturb, the excessive reading of even a single page might have a deleterious effect on the entire block.
Any suitable action may be initiated if a read-disturb phenomenon has been detected. To give one possible example among many suitable remedial actions, the content of the block can be copied to another available block, and the block suffering from read disturb can be erased and used subsequently as an available block.
Performance trade-off considerations according to certain embodiments of the present invention are now described in detail.
Several methods by which memory consumption stemming from the buffer may be reduced, are described below. It is appreciated that the presentation of these in the context of the tracking application described above is merely by way of example and the applicability of these methods is not limited to the tracking application described above.
Dilution of Tracking Activation according to certain embodiments of the present invention is now described in detail. In some applications, the voltage variation across the rows of a block are such which employ only a few threshold corrections within the block. In the tracking method described above, the procedure for tracking the detection thresholds is activated for every page in the block. This implies that most of the times, the tracking is activated in vain.
In certain embodiments of the present invention, the tracking is employed only on pages which lie in rows which are multiples of a certain integer values (e.g. 2, 3). The advantages of this approach are twofold. First, the processing of the bit errors is circumvented in some of the rows in the block, leading to saving in processing times. Second, the MSB and CSB pages which belong to the untracked rows need not be saved in the buffer, leading to savings in the system's memory requirements. An example of this procedure is shown in FIG. 11.
In some applications, the mapping between logical pages and physical pages is such that in order to implement the tracking procedure a large number of pages is employed such as several dozen pages. It is therefore sometimes advantageous to trade-off memory resources with time resources.
In certain embodiments of this invention, the buffer is relinquished and replaced by occasional read operations from the flash. Based on the reasoning described above, it is expected that tracking will hardly be employed within the block. Tracking is typically employed when the distributions of the program levels have changed significantly with respect to the ones which were obtained last. Such a situation can be identified by checking if the total number of errors has significantly increased with respect to the previous row or page. Only if the number of errors has risen drastically, is the tracking procedure employed, and in case of tracking a CSB or a LSB page, appropriate read operations will be performed to enable association of bit errors to threshold errors. It is assumed that the scarcity of the tracking procedures employed within one block is sufficient to render the performance loss or increased time delay, due to the additional read operation, negligible.
Example implementations: Two specific implementations of the invention shown and described herein are now described, by way of example, which pertain respectively to different mappings of a sequence of logical pages numbered for convenience 0, 1, 2, . . . each including a multiplicity of data bytes such as 4 K data bytes, into an erase block including an array of physical cells arranged in physical rows numbered for convenience 0, 1, 2, . . . and physical columns. Implementation 1 pertains to a mapping scheme termed Mapping 1 and described below, and Implementation 2 pertains to a mapping scheme termed Mapping 2 and described below. It is appreciated that alternatively, any other suitable mappings may be used.
Mapping 1 comprises the following mapping scheme: A sequence of logical pages is mapped into an erase block including an array of physical multi-level e.g. 3-level cells as follows:
Logical page 1 is stored in the MSBs of cells 1, 3, 5 etc. in row 0.
Logical page 2 is stored in the MSBs of cells 0, 2, 4, etc. in row 1.
Logical page 6 is stored in the MSBs of cells 0, 2, 4, etc. in row 3.
Logical page 7 is stored in the MSBs of cells 1, 3, 5, etc. in row 3.
Logical page 11 is stored in the CSBs of cells 1, 3, 5, etc. in row 0.
Logical page 12 is stored in the MSBs of cells 0, 2, 4, etc. in row 5.
Logical pages 0, 2, etc. are termed herein “even pages” whereas pages 1, 3, etc. are termed herein “odd pages”. For the case of erase sectors comprising 192 logical pages mapped to 32 physical rows, the mapping of pages to cells is listed in its entirety in FIG. 14.
Example implementation 1 is now described. As for tracking an MSB page, the implementation is not dependent on the mapping and is depicted in FIG. 6. As for tracking a CSB page, e.g. as shown in FIG. 7, the step 705 comprises looking in the table appearing in FIG. 16, and finding the row in which the page resides. Then, the row number is used to access the table in FIG. 14 and obtain the page number of the corresponding MSB page residing in the same row. The page itself is located in the buffer appearing in FIG. 2.
As for tracking an LSB page e.g. as shown in FIGS. 8A-8B, the step 810 comprises looking in the table appearing in FIG. 16, and finding the row in which the page resides. Then, the row number is used to access the table in FIG. 14 and obtain the page numbers of the corresponding MSB and CSB pages residing in the same row. The pages themselves are located in the buffer appearing in FIG. 2.
Mapping 2 comprises the following mapping scheme:
Logical page 2 is stored in the CSBs of cells 0, 2, 4, etc. in row 0.
Logical page 6 is stored in the MSBs of cells 0, 2, 4, etc. in row 1.
Logical page 7 is stored in the MSBs of cells 1, 3, 5, etc. in row 1.
Logical pages 0, 2, etc. are termed herein “even pages” whereas pages 1, 3, etc. are termed herein “odd pages”. For the case of erase sectors comprising 192 logical pages mapped to 32 physical rows, the mapping of pages to cells is listed in its entirety in FIG. 13.
Example implementation 2 is now described. As for tracking an MSB page, the implementation is not dependent on the mapping and is depicted in FIG. 6. As for tracking a CSB page e.g. as shown in FIG. 7, step 705 comprises looking in the table appearing in FIG. 15, and finding the row in which the page resides. Then, the row number is used to access the table in FIG. 13 and obtain the page number of the corresponding MSB page residing in the same row. The page itself is located in the buffer appearing in FIG. 2. As for tracking an LSB page e.g. as shown in FIGS. 8A-8B, step 810 comprises looking in the table appearing in FIG. 15, and finding the row in which the page resides. Then, the row number is used to access the table in FIG. 13 and obtain the page numbers of the corresponding MSB and CSB pages residing in the same row. The pages themselves are located in the buffer appearing in FIG. 2.
FIG. 18 is a generalized flowchart illustration of a method of operation of the system of FIGS. 1-2, the method being operative according to certain embodiments of the present invention.
The method of FIG. 18 typically comprises some or all of the following steps, suitably ordered e.g. as shown:
Step 3010: predetermine at least one initial reading threshold.
Step 3040: compute at least one row-specific reading threshold based on the bit error characterizing information and on a previous threshold initially comprising the initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page.
FIG. 19 is a simplified flowchart illustration of a method for using flash memory to store data, the method being operative in accordance with certain embodiments of the present invention. The method of FIG. 19 typically comprises some or all of the following steps, suitably ordered e.g. as shown:
Step 3110: Write at least one page of data to flash memory
Step 3120: Read at least one page of data from flash memory using a set of reading thresholds, including generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page
Included in the scope of the present invention, inter alia, are electromagnetic signals carrying computer-readable instructions for performing any or all of the steps of any of the methods shown and described herein, in any suitable order; machine-readable instructions for performing any or all of the steps of any of the methods shown and described herein, in any suitable order; program storage devices readable by machine, tangibly embodying a program of instructions executable by the machine to perform any or all of the steps of any of the methods shown and described herein, in any suitable order; a computer program product comprising a computer useable medium having computer readable program code having embodied therein, and/or including computer readable program code for performing, any or all of the steps of any of the methods shown and described herein, in any suitable order; any technical effects brought about by any or all of the steps of any of the methods shown and described herein, when performed in any suitable order; any suitable apparatus or device or combination of such, programmed to perform, alone or in combination, any or all of the steps of any of the methods shown and described herein, in any suitable order; information storage devices or physical records, such as disks or hard drives, causing a computer or other device to be configured so as to carry out any or all of the steps of any of the methods shown and described herein, in any suitable order; a program pre-stored e.g. in memory or on an information network such as the Internet, before or after being downloaded, which embodies any or all of the steps of any of the methods shown and described herein, in any suitable order, and the method of uploading or downloading such, and a system including server/s and/or clients for using such; and hardware which performs any or all of the steps of any of the methods shown and described herein, in any suitable order, either alone or in conjunction with software.
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US-Klassifikation 714/719, 365/185.33
Internationale Klassifikation G11C29/00, G11C16/04
Unternehmensklassifikation G06F12/0246, G11C16/349, G06F2212/1032
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