Source: http://www.google.com/patents/US6696324?dq=6668407
Timestamp: 2016-12-06 06:26:58
Document Index: 221659811

Matched Legal Cases: ['art.\n35', 'art.\n37', 'arts 62', 'arts 62', 'arts 62', 'arts 62']

Patent US6696324 - Contact structures of wirings and methods for manufacturing the same, and ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsFirst, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer...http://www.google.com/patents/US6696324?utm_source=gb-gplus-sharePatent US6696324 - Contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the sameAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6696324 B2Publication typeGrantApplication numberUS 09/751,840Publication dateFeb 24, 2004Filing dateJan 2, 2001Priority dateDec 31, 1999Fee statusPaidAlso published asUS7507996, US20010019125, US20040140575, US20080293241Publication number09751840, 751840, US 6696324 B2, US 6696324B2, US-B2-6696324, US6696324 B2, US6696324B2InventorsMun-pyo Hong, Sang-Gab KimOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (21), Non-Patent Citations (3), Referenced by (35), Classifications (32), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetContact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same
US 6696324 B2Abstract
First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pad and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed. Next, IZO is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively and electrically connected to the drain electrode, the gate pad and the data pad via the inter-layer reaction layers.
What is claimed is: 1. A manufacturing method of a contact structure of a wire comprising steps of:
forming a wire on a substrate; forming an inter-layer reaction layer on the wire by annealing; and forming a conductive layer on the inter-layer reaction layer such that the conductive layer is electrically connected to the wire through the inter-layer reaction layer. 2. The method of claim 1, wherein the wire is made of a conductive material including aluminum-based material.
3. The method of claim 1, further comprising the step of forming an insulating layer having a contact hole between the wire and the conductive layer.
4. The method of claim 3, wherein the annealing process is executed before forming the insulating layer.
5. The method of claim 3, wherein the annealing process is executed after forming the insulating layer.
6. The method of claim 1, wherein the inter-layer reaction layer includes silicon or transition metal.
7. The method of claim 3, wherein the inter-layer reaction layer is inter-metallic compound layer.
8. The method of claim 1, wherein the conductive layer is made of a transparent conductive material of indium zinc oxide.
9. The method of claim 1, wherein the annealing process is executed in the range of 200-400° C.
10. A manufacturing method of a thin film transistor array panel comprising steps of:
forming a gate wire; forming a data wire; forming a semiconductor layer; forming an inter-layer reaction layer on the gate wire and the data wire through annealing process; and forming a conductive layer on the inter-layer reaction layer such that the conductive layer is electrically connected to the gate wire or the data wire through the inter-layer reaction layer. 11. The method of claim 10, further comprising the step of forming an insulating layer having a contact hole on the gate or the data wires between the gate or the data wires and the conductive layer.
12. The method of claim 10, wherein the gate wire and the data wire include a conductive material of aluminum-based material.
13. The method of claim 10, wherein the inter-layer reaction layer includes silicon or transition metal.
14. The method of claim 13, wherein the inter-layer reaction layer includes amorphous or doped amorphous silicon.
15. The method of claim 13, wherein the inter-layer reaction layer is an inter-metallic compound.
16. The method of claim 10, wherein the conductive layer is made of indium zinc oxide.
17. The method of claim 10, wherein the annealing process is executed before forming the insulating layer.
18. The method of claim 10, wherein the annealing process is executed after forming the insulating layer.
19. The method of claim 10, wherein the insulating layer is deposited in the range of 200-400° C.
20. The method of claim 10, further comprising the step of executing a wet cleaning process using etchant or a dry cleaning process using plasma before forming the inter-layer reaction layer.
21. A manufacturing method of a thin film transistor array panel for a liquid crystal display comprising steps of:
forming a gate wire including a gate line, and a gate electrode connected to the gate line by depositing and patterning a first conductive material on an insulating substrate; depositing a gate insulating layer; forming a semiconductor layer; forming a data wire including a data line intersecting the gate line, a source electrode connected to the data line and adjacent to the gate electrode and a drain electrode opposite of the source electrode with respect to the gate electrode by depositing and patterning a second conductive material; depositing a passivation layer; forming an inter-layer reaction layer on the gate wire and the data wire by executing annealing process; patterning the passivation layer to form a first contact hole exposing the drain electrode; and forming a pixel electrode electrically connected to the drain electrode through the first contact hole on the passivation layer. 22. The method of claim 21, wherein the first and the second conductive material include a metal of aluminum-based material.
23. The method of claim 21, wherein the annealing process is executed before forming the gate insulating layer or the passivation layer.
24. The method of claim 21, wherein the annealing process is executed after forming the first contact hole.
25. The method of claim 21, wherein the pixel electrode is made of a transparent conductive material.
26. The method of claim 25, wherein the pixel electrode is made of indium zinc oxide.
27. The method of claim 21, wherein the annealing process is executed in the range of 200-400° C.
28. The method of claim 21, wherein the inter-layer reaction layer includes silicon or transition metal.
29. The method of claim 28, wherein the inter-layer reaction layer includes amorphous or doped amorphous silicon.
30. The method of claim 28, wherein the inter-layer reaction layer is an inter-metallic compound.
31. The method of claim 21, wherein the gate wire further includes a gate pad which is connected to the gate line and receives a signal from an external circuit, and the data wire further includes a data pad which is connected to the data line and receives a signal from a external circuit, and the passivation layer and the gate insulating layer have a second contact hole and a third contact hole respectively exposing the inter-layer reaction layer on the gate pad and the data pad, and
further comprising the step of forming a redundant gate pad and a redundant data pad which are made of the same layer as the pixel electrode and respectively electrically connected to the gate pad and the data pad through the second and the third contact holes. 32. The method of claim 21, wherein the data wire and the semiconductor layer are together formed by photolithography process using a photoresist pattern having different thicknesses depending the positions.
33. The method of claim 32, wherein the photoresist pattern has a first portion having a first thickness, a second portion having a second thickness larger than the first portion, and a third portion having a third thickness smaller than the first thickness.
34. The method of claim 23, wherein a mask used for forming the photoresist pattern has a first, a second, and a third part, a transmittance of the third part is higher than the first and the second parts, a transmittance of the first part is higher than the second part.
35. The method of claim 34, wherein the first and the second portion of the photoresist pattern are respectively aligned on portion between the source electrode and the drain electrode, and the data wire.
36. The method of claim 35, wherein the first part of the mask includes a partially transparent layer, or a slit pattern smaller than the resolution of the exposure used in the exposing step, to regulate the transmittance of the first part.
37. The method of claim 21, further comprising step of depositing an ohmic contact layer between the data wire and the semiconductor layer.
38. The method of claim 37, wherein the data wire, the ohmic contact layer, and the semiconductor layer are formed in the same photolithography process.
In order to prevent delay or distortion of signals, materials having low resistivity such as aluminum or aluminum alloy are generally used. However, since the physical and the chemical properties of the aluminum or aluminum alloy is not good, that is, the aluminum or aluminum alloy is easily oxidized and corroded, when connecting other conductive material in a contact portions, accordingly the characteristics of semiconductor devices are deteriorated. To improve a contact properties of the wire made of aluminum and aluminum alloy, a different material is then inserted. However, to form the wire of multi-layered structure, several etchant to pattern the wire of multi-layered structure are needed, also many photolithography steps are needed. Accordingly, the manufacturing method is complicated and production costs are increased.
It is desirable that the wire is made of aluminum-based material, and the inter-layer reaction layer may include silicon or transition metal. Here, an insulating layer having a contact hole may be added between the wire and the conductive layer, the insulating layer may formed before forming the inter-layer reaction or after forming the inter-layer reaction.
It is desirable that the first part of the mask includes a partially transparent layer, or a slit pattern smaller than the resolution of the exposure used in the exposing step, to regulate the transmittance of the first part, and the thickness of the first portion is less than the half of the thickness of the second portion.
FIGS. 17A, 18A, and 19A are cross-sectional views in the next manufacturing step following that represented in FIGS. 16B taken along the line XVIB-XVIB′ of FIG. 16A.
Inter-layer reaction layers 94, 96 and 98, which include at least AlxSix made of aluminum and silicon, or inter-metallic compound, are at least formed on the portion of the gate pad 24, the drain electrode 66 and the data pad 68, which are exposed through contact holes 74, 76 and 78. Here, the inter-layer reaction layers 94, 96 and 98 have the function improving contact prosperities between the gate pad 24 and the upper layer 602 of the drain electrode 66 and the data pad 68, which is made of aluminum-based material, and a pixel wire 82, 86 and 88 of IZO, which will be formed later. It is preferable that the inter-metallic compound includes transition metal such as chromium, molybdenum, molybdenum alloy etc.
Next, as shown in FIGS. 9A and 9B, a silicon layer such as an amorphous silicon or a doped amorphous silicon, or a transition metal layer such as chromium, molybdenum, molybdenum alloy or titanium is deposited at thickness of about 500 Å or more than 200 Å on the substrate 10 to form a inter-layer reaction layer improving contact prosperities between IZO and metal layer of aluminum-based material. Then, anneal process is executed in the range of 200-400° C. to form a inter-layer reaction layer 94, 96 and 98 including AlxSix or a transition metal layer such as chromium, molybdenum, molybdenum alloy or titanium on aluminum-based layer of the gate pad 24, and the upper layer 602 of the drain electrode 66 and the data pad 68. Next, a whole etch process is executed to remove the silicon layer or the transition metal layer. At this time, the silicon layer or the transition metal layer is removed, but the inter-layer reaction layer 94, 96 and 98 are remained. In this embodiment, the transition layer is deposited at thickness of about 300 Å, the annealing process is executed during about 30 minute, and the inter-metallic compound layer 94, 96 and 98 as the inter-layer reaction layer is formed at thickness of less than 60 Å.
The ohmic contact layer patterns 55, 56, and 58 play a roll to reduce the contact resistance between the semiconductor patterns 42 and 48 and the corresponding data wire parts 62, 64, 65, 66, and 68, and have the same layout as the data wire parts 62, 64, 65, 66, and 68. In other word, a first ohmic contact layer portion 55 under the data line part has the same shape as the data line parts 62, 68, and 65, a second ohmic contact layer portion 56 under the drain electrode part has the same shape as the drain electrode 66, and a third ohmic contact layer portion 58 under the conductor pattern 64 has the same shape as the conductor pattern 64 for the storage capacitor.
Pixel electrodes 82 that receive an image signal and generate an electric field with a common electrode of an upper panel are formed on the passivation layer. The pixel electrode 82 is made of a transparent conductive material such as indium zinc oxide (IZO). The pixel electrode 82 is connected to the inter-layer reaction layer 91 on the drain electrode 66 both physically and electrically through the contact hole 71, and receives the image signal from the drain electrode 66. Even though the aperture ratio is increased when the pixel electrode 82 overlaps the gate lines 22 or the adjacent the data lines 62, these lines are not required to overlap the pixel electrode. The pixel electrode 82 is connected to the conductor pattern 64 for storage capacitance through the contact hole 74 and transmits an image signal to the conductor pattern 64.
Next, as shown in FIGS. 15A and 15B, a gate insulating layer 30, a semiconductor layer 40, and an ohmic contact layer 50 are sequentially deposited to thicknesses of 1,500 Å to 5,000 Å, 500 Å to 2,000 Å, and 300 Å to 600 Å, respectively, by such methods as chemical vapor deposition (CVD). Then, a conductor layer 60, such as a metal, is deposited to a thickness of 1,500 Å to 3,000 Å by such methods as sputtering and a photoresist layer 110 having a thickness of 1 ┤ to 2 ┤ is coated on the conductive layer 60.
Referring to FIGS. 17A and 17B, as a result, only the portions of the conductor 67 and 64 under the photoresist layers 112 and 114 at the channel part C and the data wire part B for source/drain electrodes and a storage capacitor are left, and the remaining portion of the conductor layer 60 at part B is wholly removed to expose the ohmic contact layer 50 thereunder. At this time, the conductor patterns 67 and 64 have the same layout as the data wire parts 62, 64, 65, 66, and 68 except that the source electrode 65 and the drain electrode 66 are connected to each other. When a dry etch is used, the photoresist layers 112 and 114 are also etched to a certain thickness.
Next, as shown in FIGS. 21A to 21C, the dry cleaning process using gas such as SF6/O2, CF4/O2, BCl3/Cl2 or BCl3/HBR2 is executed to clean the portions of the drain electrode 66, the gate pad 24, the data pad 68, and the conductor pattern 64, which are exposed through contact holes 71, 72, 73, and 74 respectively. Then, such as the first embodiment, a silicon layer or a transition metal layer is deposited on the substrate 10 and is annealed to form a inter-layer reaction layer 91, 92, 93 and 94 including AlxSix or a transition metal layer on aluminum-based layer of the gate pad 24, and the upper layer 602 of the drain electrode 66, the data pad 68, and the conductor pattern 64. Next, a whole etch process is executed to remove the silicon layer or the transition metal layer.
Next, as shown in FIGS. 8 to 10, a IZO layer is deposited having a thickness 400 Å to 500 Å at a temperature of about 150° C., and etched by using a fourth mask to form a pixel electrode 82 electrically connected to the drain electrode 66 and the conductor pattern 64, a redundant gate pad 84 electrically connected to the gate pad 24, and a redundant data pad 86 electrically connected to the data pad 68. Also, in this embodiment according the present invention, to minimize contact resistance of contact portion, it is preferable that the IZO layer is deposited in the range of less than 200° C., and the IZO thin film is formed through sputtering process by using the target including In2O3 and ZnO and comprising 15-20 at % (atomic percentage) of Zn.
In the embodiments according the present invention, by forming the inter-layer reaction layers including transition metal or silicon between the metal layer of aluminum-based material and the IZO layer, the contact resistance of the contact portions including IZO and the metal layer of aluminum-based material may be minimized and a reliable contact portion including the pad portions may be obtained. Furthermore, by forming the wire of aluminum and aluminum alloy, the characteristics of display device may be improved in large scale LCDs, and by simplifying the manufacturing process, manufacturing costs may also be minimized.
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