Source: https://patents.google.com/patent/US8538012B2/en
Timestamp: 2020-01-19 21:31:00
Document Index: 740756612

Matched Legal Cases: ['application No. 200810096342', 'application No. 2008', 'application No. 10', 'application No. 10', 'Application No. 200810096342', 'application No. 200810096342']

US8538012B2 - Performing AES encryption or decryption in multiple modes with a single instruction - Google Patents
Performing AES encryption or decryption in multiple modes with a single instruction Download PDF
US8538012B2
US8538012B2 US11/724,005 US72400507A US8538012B2 US 8538012 B2 US8538012 B2 US 8538012B2 US 72400507 A US72400507 A US 72400507A US 8538012 B2 US8538012 B2 US 8538012B2
US11/724,005
US20080229116A1 (en
2007-03-14 Application filed by Intel Corp filed Critical Intel Corp
2007-03-14 Priority to US11/724,005 priority Critical patent/US8538012B2/en
2008-09-18 Publication of US20080229116A1 publication Critical patent/US20080229116A1/en
2009-08-21 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GUERON, SHAY, CHENNUPATY, SRINIVAS, DIXON, MARTIN
2013-09-17 Publication of US8538012B2 publication Critical patent/US8538012B2/en
1. A machine-readable non-transitory storage medium having stored thereon an instruction, which when executed by a machine causes the machine to perform a method comprising:
determining from a first operand of the instruction an Advanced Encryption Standard (AES) encryption mode by which to encrypt data;
applying an exclusive OR operation to the first operand of the instruction and a second operand of the instruction to produce a combined result and encrypting the combined result using a key in accordance with the determined AES encryption mode to produce an encrypted result; and placing the encrypted result in a memory location of the first operand of the instruction.
2. The medium of claim 1, wherein the encrypting includes:
obtaining the key from one or more predetermined registers.
3. The medium of claim 2, wherein the key is 128 bits or 256 bits in length.
4. The medium of claim 1, wherein the second operand is plaintext to be encrypted that is 128 bits in length.
5. The medium of claim 1, wherein the first operand is zero in a first AES encryption mode by which the result is encrypted.
6. The medium of claim 1, wherein the first operand is a prior encrypted result from a prior encryption operation in a second AES encryption mode by which the result is encrypted.
7. A processor to perform encryption, comprising:
a first logic, responsive to execution of a single instruction that includes a first operand and a second operand and executable in a selected one of a plurality of Advanced Encryption Standard (AES) modes, to logically combine, via an exclusive OR operation (XOR), a plaintext value supplied by the second operand with a second value supplied by the first operand to produce a combined result, and to encrypt the combined result using an AES algorithm and a key to produce an encrypted result, wherein a particular mode of the plurality of the AES modes via which to produce the encrypted result is selected according to the first operand.
a first register to store the second value; and
a second register to store the key.
9. The processor of claim 8, wherein the first logic is arranged to store the encrypted result in the first register.
10. The processor of claim 7, wherein the second value of zero is distinctly associated with a first mode of encryption and the second value of a previously encrypted result is distinctly associated with a second mode of encryption.
11. The processor of claim 7, wherein the plaintext value and the encrypted result are each 128 bits in length.
12. A system to encrypt data, comprising:
a memory to store an Advanced Encryption Standard (AES) encryption instruction having two operands; and
a processor to execute the AES encryption instruction according to a particular mode of a plurality of modes of the AES encryption instruction, the particular mode determined based on a value of one of the two operands, wherein:
in a first mode and responsive to execution of the AES encryption instruction, the
processor is to execute a first loop to clear a first operand, logically combine a plaintext value supplied by a second operand obtained from a first corresponding memory location of a first memory, the first corresponding memory location indicated by a counter value, with a second value supplied by the first operand to produce a combined result, encrypt the combined result using an AES algorithm and a key to produce an encrypted result, store the encrypted result in a second corresponding memory location of a second memory, the second corresponding memory location indicated by the counter value, decrement the counter value, and re-execute the first loop until the counter value reaches a predetermined value; and
in a second mode and responsive to the execution of the AES encryption instruction, the processor is to clear the first operand, and thereafter execute a second loop to logically combine the plaintext value with the second value to produce the combined result, encrypt the combined result using the AES algorithm and the key to produce the encrypted result, store the encrypted result in the second corresponding memory location of the second memory indicated by the counter value, decrement the counter value, and re-execute the second loop until the counter value reaches the predetermined value.
13. The system of claim 12, wherein the AES encryption instruction has only two operands.
14. The system of claim 12, wherein the at least two modes includes two of electronic codebook mode, counter mode, and cipher block chaining mode.
15. The system of claim 12, wherein when a first operand has a value of zero, the selected mode is electronic codebook (EBC).
16. The system of claim 12, wherein the plaintext value is logically combined with the second value via an XOR operation.
US11/724,005 2007-03-14 2007-03-14 Performing AES encryption or decryption in multiple modes with a single instruction Active 2031-05-30 US8538012B2 (en)
US11/724,005 US8538012B2 (en) 2007-03-14 2007-03-14 Performing AES encryption or decryption in multiple modes with a single instruction
JP2008064272A JP4767985B2 (en) 2007-03-14 2008-03-13 Executing AES encryption or decryption in multiple modes with a single instruction
TW097108905A TWI390401B (en) 2007-03-14 2008-03-13 Performing aes encryption or decryption in multiple modes with a single instruction
CN201410197191.5A CN103957100B (en) 2007-03-14 2008-03-14 AES encryption or decryption are executed in various modes using single instrction
GB0804870A GB2447563B (en) 2007-03-14 2008-03-14 Performing AES encryption or decryption in multiple modes with a single instruction
CN200810096342.2A CN101272238B (en) 2007-03-14 2008-03-14 Performing AES encryption or decryption in multiple modes with a single instruction
DE102008014359A DE102008014359B4 (en) 2007-03-14 2008-03-14 Perform AES encryption or decryption in multiple modes with a single command
KR1020080024067A KR20080084752A (en) 2007-03-14 2008-03-14 Performing aes encryption or decryption in multiple modes with a single instruction
KR1020100059386A KR101302799B1 (en) 2007-03-14 2010-06-23 Performing aes encryption or decryption in multiple modes with a single instruction
US13/790,748 US9325498B2 (en) 2007-03-14 2013-03-08 Performing AES encryption or decryption in multiple modes with a single instruction
KR1020130056494A KR101394710B1 (en) 2007-03-14 2013-05-20 Performing aes encryption or decryption in multiple modes with a single instruction
US15/079,305 US20160261406A1 (en) 2007-03-14 2016-03-24 Performing AES Encryption Or Decryption In Multiple Modes With A Single Instruction
US13/790,748 Continuation US9325498B2 (en) 2007-03-14 2013-03-08 Performing AES encryption or decryption in multiple modes with a single instruction
US20080229116A1 US20080229116A1 (en) 2008-09-18
US8538012B2 true US8538012B2 (en) 2013-09-17
ID=39328229
US11/724,005 Active 2031-05-30 US8538012B2 (en) 2007-03-14 2007-03-14 Performing AES encryption or decryption in multiple modes with a single instruction
US13/790,748 Active US9325498B2 (en) 2007-03-14 2013-03-08 Performing AES encryption or decryption in multiple modes with a single instruction
US15/079,305 Abandoned US20160261406A1 (en) 2007-03-14 2016-03-24 Performing AES Encryption Or Decryption In Multiple Modes With A Single Instruction
US (3) US8538012B2 (en)
JP (1) JP4767985B2 (en)
KR (3) KR20080084752A (en)
CN (2) CN103957100B (en)
DE (1) DE102008014359B4 (en)
GB (1) GB2447563B (en)
TW (1) TWI390401B (en)
US10419210B2 (en) 2014-07-22 2019-09-17 Intel Corporation SM4 acceleration processors, methods, systems, and instructions
US8447796B2 (en) * 2008-11-25 2013-05-21 Intel Corporation Apparatus with a vector generation unit and encoder for receiving first and second inputs to generate at least significant zero (LSZ)
JPH07261662A (en) 1994-03-22 1995-10-13 Fujitsu Ltd Cipher operation circuit
JP2004233427A (en) 2003-01-28 2004-08-19 Nec Corp Aes encryption processing device, aes decryption processing device, and aes encryption/decryption processing device
US20040223610A1 (en) 2003-04-18 2004-11-11 Via Technologies Inc. Apparatus and method for performing transparent cipher block chaining mode cryptographic functions
CA2179971C (en) * 1995-06-30 2001-10-30 Takahisa Yamamoto An adaptable communication apparatus and an adaptable communication system
JP3851115B2 (en) * 2001-06-28 2006-11-29 富士通株式会社 Cryptographic circuit
DE10201449C1 (en) * 2002-01-16 2003-08-14 Infineon Technologies Ag Calculator, method for performing an operation with an encrypted operand, carry select adder and cryptography processor
ES2376818T3 (en) * 2005-11-08 2012-03-20 Irdeto Access B.V. Methods of randomization and dealeatorization of data units.
2007-03-14 US US11/724,005 patent/US8538012B2/en active Active
2008-03-13 TW TW097108905A patent/TWI390401B/en not_active IP Right Cessation
2008-03-13 JP JP2008064272A patent/JP4767985B2/en active Active
2008-03-14 CN CN201410197191.5A patent/CN103957100B/en active IP Right Grant
2008-03-14 KR KR1020080024067A patent/KR20080084752A/en active Application Filing
2008-03-14 CN CN200810096342.2A patent/CN101272238B/en active IP Right Grant
2008-03-14 DE DE102008014359A patent/DE102008014359B4/en active Active
2008-03-14 GB GB0804870A patent/GB2447563B/en active Active
2010-06-23 KR KR1020100059386A patent/KR101302799B1/en active IP Right Grant
2013-03-08 US US13/790,748 patent/US9325498B2/en active Active
2013-05-20 KR KR1020130056494A patent/KR101394710B1/en active IP Right Grant
2016-03-24 US US15/079,305 patent/US20160261406A1/en not_active Abandoned
"2004 IEEE Workshop on Signal processing Systems design and Implementation", published 2004, IEEE, pp. 152-157 Nadehara et al. "Extended Instructions for the AES cryptography and their efficient implementattion". See whole document.
Astarloa, A. et al., "Multi-architectural 128 bit AES-CBC Core based on Open-Source Hardware AES Implementations for secure industrial communications", International Conference on Communication Technology, Nov. 27-30, 2006, 6 pages.
Bos, J., et al, ‘Efficient Hashing using the AES Instruction Set’, 2010, Dept of CS, Univ. of Bristol, UK, entire document, http://eprint.iacr.org/2010/576.pdf. *
Bos, J., et al, 'Efficient Hashing using the AES Instruction Set', 2010, Dept of CS, Univ. of Bristol, UK, entire document, http://eprint.iacr.org/2010/576.pdf. *
Chinese Patent Office, Office Action mailed Dec. 9, 2011 in Chinese application No. 200810096342.2.
Combined Search and Examination Report received for United Kingdom Patent Application No. GB0804870.4, mailed on Jun. 25, 2008, 7 pages.
Japanese Patent Office, Office Action mailed Jan. 25, 2011 in Japanese patent application No. 2008-0064272.
Korean International Patent Office, Office Action mailed Sep. 24, 2012 in Korean application No. 10-2010-59386.
Korean Patent Application 10-2008-24067, office action dated Feb. 18, 2010, 6 pages.
Office action dated May 15, 2009 from German application No. 10 2008 014 359.6-31, 6 pages.
Office Action Received for Chinese Patent Application No. 200810096342.2 , mailed on Apr. 1, 2010, 4 Pages of Chinese Office Action, and 4 Pages of English Translation.
State Intellectual Property Office of the People's Republic of China, Office Action mailed Jun. 5, 2012 in Chinese application No. 200810096342.2.
Tillich, S. et al, ‘An Instruction Set Extension for Fast and Memory-Efficient AES Implementation’, International Federation for Information Processing 2005, CMS 2005, LNCS 3677, pp. 11-21, 2005, http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.83.55&rep=rep1&type=pdf. *
Tillich, S. et al, 'An Instruction Set Extension for Fast and Memory-Efficient AES Implementation', International Federation for Information Processing 2005, CMS 2005, LNCS 3677, pp. 11-21, 2005, http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.83.55&rep=rep1&type=pdf. *
VIA Technologies, VIA PadLock Programming Guide, May 3, 2005, pp. 1-55.
US10425222B2 (en) 2014-07-22 2019-09-24 Intel Corporation SM4 acceleration processors, methods, systems, and instructions
US10454669B2 (en) 2014-07-22 2019-10-22 Intel Corporation SM4 acceleration processors, methods, systems, and instructions
US10469249B2 (en) 2014-07-22 2019-11-05 Intel Corporation SM4 acceleration processors, methods, systems, and instructions
US10476667B2 (en) 2014-07-22 2019-11-12 Intel Corporation SM4 acceleration processors, methods, systems, and instructions
CN101272238A (en) 2008-09-24
DE102008014359B4 (en) 2011-08-25
US9325498B2 (en) 2016-04-26
TW200903254A (en) 2009-01-16
GB2447563A (en) 2008-09-17
KR101302799B1 (en) 2013-09-03
US20130202106A1 (en) 2013-08-08
JP2008283672A (en) 2008-11-20
CN103957100A (en) 2014-07-30
KR20100082748A (en) 2010-07-19
GB0804870D0 (en) 2008-04-16
JP4767985B2 (en) 2011-09-07
CN101272238B (en) 2014-06-04
KR20130076834A (en) 2013-07-08
TWI390401B (en) 2013-03-21
GB2447563B (en) 2009-09-30
US20160261406A1 (en) 2016-09-08
CN103957100B (en) 2018-10-16
US20080229116A1 (en) 2008-09-18
DE102008014359A1 (en) 2008-10-16
KR101394710B1 (en) 2014-05-15
KR20080084752A (en) 2008-09-19
Cook et al. 2005 CryptoGraphics: Secret key cryptography using graphics cards
JP4500306B2 (en) 2010-07-14 Apparatus and method for memory encryption with reduced decryption latency
EP1469371B1 (en) 2008-07-02 Microprocessor apparatus and method for performing block cipher cryptographic functions
EP0983541B1 (en) 2003-08-06 Method and apparatus for signing and sealing objects
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DIXON, MARTIN;CHENNUPATY, SRINIVAS;GUERON, SHAY;REEL/FRAME:023127/0988;SIGNING DATES FROM 20070308 TO 20070311
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DIXON, MARTIN;CHENNUPATY, SRINIVAS;GUERON, SHAY;SIGNING DATES FROM 20070308 TO 20070311;REEL/FRAME:023127/0988