Source: http://www.google.com/patents/US20040211997?ie=ISO-8859-1
Timestamp: 2014-03-11 02:57:58
Document Index: 372676243

Matched Legal Cases: ['Application No. 2001', 'Application No. 2001', 'art 45', 'art 45', 'art 45', 'art 45']

Patent US20040211997 - Ferroelectric memory device and method for manufacturing the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe present invention provides a ferroelectric memory device and a manufacturing method forming the same capable of preventing characteristic deterioration of a ferroelectric layer due to an plasma. The ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor...http://www.google.com/patents/US20040211997?utm_source=gb-gplus-sharePatent US20040211997 - Ferroelectric memory device and method for manufacturing the sameAdvanced Patent SearchPublication numberUS20040211997 A1Publication typeApplicationApplication numberUS 10/848,113Publication dateOct 28, 2004Filing dateMay 19, 2004Priority dateSep 14, 2001Also published asUS6773929, US6927437, US20030053351Publication number10848113, 848113, US 2004/0211997 A1, US 2004/211997 A1, US 20040211997 A1, US 20040211997A1, US 2004211997 A1, US 2004211997A1, US-A1-20040211997, US-A1-2004211997, US2004/0211997A1, US2004/211997A1, US20040211997 A1, US20040211997A1, US2004211997 A1, US2004211997A1InventorsSang-Hyun Oh, Jin-Yong Seong, Chung-Won SuhOriginal AssigneeHynix Semiconductor Inc.Export CitationBiBTeX, EndNote, RefManReferenced by (3), Classifications (18), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetFerroelectric memory device and method for manufacturing the sameUS 20040211997 A1Abstract The present invention provides a ferroelectric memory device and a manufacturing method forming the same capable of preventing characteristic deterioration of a ferroelectric layer due to an plasma. The ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, includes a semiconductor substrate; a first insulating layer formed on the semiconductor substrate; and a bottom electrode of the ferroelectric capacitor formed in the first insulating layer, wherein a top surface of the bottom electrode is planarized with the first insulating layer; a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and a top electrode of the ferroelectric capacitor formed on the ferroelectric layer and overlapped with the bottom electrode. Images(15) Claims(9)
What is claimed is: 1. A ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, comprising: a semiconductor substrate; a first insulating layer formed on the semiconductor substrate; a bottom electrode of the ferroelectric capacitor formed in the first insulating layer, wherein a top surface of the bottom electrode is planarized with the first insulating layer; a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and a top electrode of the ferroelectric capacitor formed on the ferroelectric layer and overlapped with the bottom electrode. 2. The ferroelectric memory device of claim 1, wherein the size of the top electrode is not smaller than the bottom electrode. 3. The ferroelectric memory device of claim 1 further comprising: a second insulating layer covering the ferroelectric capacitor; and a plate line coupling to the top electrode through a first contact hole in the second insulating layer. 4. The ferroelectric memory device of claim 3, wherein the top electrode is shared by adjacent ferroelectric capacitors, the second insulating layer further includes a second contact hole formed on an end of the top electrode, and the plate line is coupled to the top electrode through the first and second contact hole. 5. The ferroelectric memory device of claim 1, wherein the top electrode is shared by adjacent ferroelectric capacitors, and the ferroelectric memory device further comprises: a third insulating layer covering the top electrode of the ferroelectric capacitor; and a plate line coupling to the top electrode through a third contact hole in the third insulating layer. 6. The ferroelectric memory device of claim 1 further comprising a fourth insulating layer covering the ferroelectric layer and including a fourth contact hole therein, wherein the top electrode is formed in the fourth contact hole. 7. The ferroelectric memory device of claim 6 further comprising an adhesion layer formed on the fifth insulating layer. 8. The ferroelectric memory device of claim 6, wherein the adhesion layer is formed of TiO2 or Al2O3. 9. The ferroelectric memory device of claim 1, wherein the first area is a cell area and the second area is a peripheral circuit area.
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a Divisional of co-pending application Ser. No. 10/242,417, filed on Sep. 13, 2002, and for which priority is claimed under 35 U.S.C. � 120; and this application claims priority of Application No. 2001-56929 filed in Korea on Sep. 14, 2001 and Application No. 2001-88713 filed in Korea on Dec. 31, 2001 under 35 U.S.C. � 119; the entire contents of all are hereby incorporated by reference.
FIELD OF THE INVENTION [0002] The present invention relates to a ferroelectric memory device; and, more particularly, to a ferroelectric memory device including a ferroelectric layer covering all cell region and a method for manufacturing the same. DESCRIPTION OF RELATED ART [0003] Several studies on utility of a ferroelectric material as a capacitor dielectric, have been developed to overcome a limit of refresh in a conventional dynamic random access memory(DRAM) and to achieve a large capacitance. A ferroelectric random access memory (FeRAM) is one of e nonvolatile memory devices that can store information at turn-off state and has a rapid operating speed comparable to that of the DRAM.SrBi2Ta2O9 (SBT), Pb (Zrx, Ti1-x)O3 (PZT) or (Bi, La)4Ti3O12 (BLT) is mainly used as a storage material of FeRAM. The ferroelectric material has a dielectric constant being in the order of 102-103 at room temperature and has two stabilized remnant polarization states. Therefore, the ferroelectric material is suitable for applying to a nonvolatile memory device. [0004] A signal is inputted to the nonvolatile memory device adopting ferroelectric material by the change of polarization orientation according to an electric field applied thereto, and a digital signal �1� or �0� is stored therein by an orientation of remnant polarization when an electric field is removed. [0005] In a FeRAM device adopting SrxBiy(TaiNbj)2O9 (hereinafter, referred to as a SBTN), etc, which have perovskite structure, as a ferroelectric layer in a ferroelectric capacitor besides the above-mentioned PZT and SBT, a top/bottom electrode is formed of any one selected from the group consisting of Pt, Ir, Ru, IrO, RuO and Pt-alloy. [0006]FIG. 1 is a conventional equivalent circuit illustrating a FeRAM having one transistor and one capacitor(1T-1C) structure. In FIG. 1, �C� denotes a ferroelectric capacitor, �Q� denotes a MOS transistor, �WL1 and WL2� denote word lines connected to a gate of the MOS transistor Q, �BL� denotes a bit line connected to a source/drain region of the MOS transistor, and �PL� denotes a plate line connected to a top electrode of the ferroelectric capacitor C. [0007]FIG. 2 is a cross-sectional view of the FeRAM shown in FIG. 1. [0008] Referring to FIG. 2, adjacent two transistors are formed on a semiconductor substrate 11. A field oxide layer 12 is formed in a predetermined portion of the semiconductor substrate 11 in order to separate two transistors from another two transistors(not shown). [0009] The transistor is formed according to a usual complementary metal oxide semiconductor (CMOS) process. A gate electrode 13 is formed on the semiconductor substrate 11, and a common connection drain of adjacent two transistors (hereinafter, referred to as a �common drain�) 14A and source 14B of each transistor are formed in the semiconductor substrate at each side of the gate electrode 13. [0010] A first interlayer insulating layer 15 is formed and flattened on the semiconductor substrate 11. The first interlayer insulating layer 15 is formed of a first and a second insulating layer 15A and 15B successively deposited. A bit line 17 is connected to the common drain 14A through a fist contact plug 16 penetrating the first insulating layer 15A, and the bit line 17 is insulated by the second insulating layer 15B. [0011] A second contact plug 18 penetrates the first interlayer insulating layer 15 and is connected the source 14B of each transistor and a bottom electrode 19 of a ferroelectric capacitor. [0012] A bottom electrode 19 and a ferroelectric layer 20 are formed on the first interlayer insulating layer 15 to the same size, and a top electric 21 having smaller size than that of the bottom electrode 19 is formed on the ferroelectric layer 20. [0013] A second interlayer insulating layer 22 covers the ferroelectric capacitor and has opening which exposes the top electrode 21. A plate line 23 is formed to couple to the top electrode through the opening in the second interlayer insulating layer 22. [0014] The conventional ferroelectric capacitor of FeRAM cell shown in FIG. 2 is formed by stacking layers for the bottom electrode 19, the ferroelectric layer 20 and the top electrode 21, successively. Thereafter, the top electrode 21 is etched, and the ferroelectric layer 20 and the bottom electrode 19 are etched using other mask different from a mask for forming the top electrode 21. [0015] In the conventional method, it is difficult to form the top electrode and the bottom electrode to the same size, if the size of a bottom and top electrode is same, a bottom and top electrode can be shorten, so it is hard to obtain safety in a process. Also, it is difficult to form the ferroelectric capacitor with one step etch process because the layers of the ferroelectric capacitor is thick. Furthermore, the etch profile of the ferroelectric capacitor is not vertical but is slant, so there is some limit to reduce the size of the ferroelectric capacitor. [0016] Due to the above-mentioned reason, the size of a top electrode, which determines an electric charge storage capacity of a capacitor, is restricted to be smaller than that of a bottom electrode so that is difficult to obtain enough amount of an electric charge. [0017] In the conventional method, the ferroelectric layer is formed to cover the bottom electrode layer just after forming the bottom electrode layer, so the ferroelectric layer should be etched in an etch process for forming the bottom electrode pattern. In the etch process, the ferroelectric layer is exposed to plasma, and thereby the characteristics of the ferroelectric layer is deteriorated. Therefore, a thermal treatment to recover characteristic of the ferroelectric layer should be performed. [0018] That is, when an etch process for forming the bottom electrode is performed, the portion of ferroelectric layer not covered with the top electrode is inevitably exposed to plasma. At this circumstance of the ferroelectric layer being exposed to plasma, polarization has not have a value of (+) and (−), and according to a condition of the ferroelectric layer being exposed to plasma, a value is fixed into (+) or (−), namely pinning phenomenon is generated. Accordingly, a capacity of the ferroelectric capacitor is reduced extremely. [0019] To solve the above-mentioned problem of the ferroelectric layer being exposed to plasma, the ferroelectric layer is formed on the bottom electrode by a spin coating or liquid source misted chemical deposition (LSMCD) after patterning the bottom electrode. [0020] However, it is difficult to form the ferroelectric layer to a uniform thickness because of a bottom electrode and a topology of sub-layers, which are formed before the bottom electrode. Furthermore, cracks can be generated in a portion of the ferroelectric layer where the bottom electrode is not exist, so it is hard to adopt the spin coating and LSMCD to formed the ferroelectric layer. [0021] In addition, the height of the ferroelectric capacitor formed of the bottom electrode, the ferroelectric layer and the top electrode is over 5500 Å. Therefore, burden of etching is increased, and it becomes more difficult to fill an insulating layer between capacitors and to flat the insulating layers as the cell area is decreased. [0022] With decreasing a cell area, it is hard to form a contact hole between the plate line and the capacitor. There, there is proposed a method of connecting the top electrode directly to the plate line by removing an interlayer insulating layer, which covers the top electrode, with a blanket etching or a chemical mechanical polishing (CMP). However from the above-mentioned method, there may be brought out a problem that a plate line and a bottom electrode are being shorten when the interlayer insulating layer is very thin. SUMMARY OF THE INVENTION [0023] It is, therefore, an object of the present invention to provide a ferroelectric memory device and manufacturing method forming the same capable of preventing characteristic deterioration of a ferroelectric layer due to an plasma. [0024] It is, therefore, another object of the present invention to provide a ferroelectric memory device and manufacturing method forming the same capable of preventing decreasing of an electric charge storage capacity according to a limit of an electrode size. [0025] It is, therefore, further another object of the present invention to provide a manufacturing method of a ferroelectric memory device capable of preventing burden of a etching process cause by the height of a capacitor, difficulty in planarization and a shorten between top and bottom electrodes. [0026] In accordance with one aspect of the present invention, there is provided a ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, including: a semiconductor substrate; a first insulating layer formed on the semiconductor substrate; a bottom electrode of the ferroelectric capacitor formed in the first insulating layer, wherein a top surface of the bottom electrode is planarized with the first insulating layer; a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and a top electrode of the ferroelectric capacitor formed on the ferroelectric layer and overlapped with the bottom electrode. [0027] In accordance with another aspect of the present invention, there is provided a method of forming a ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, comprising steps of: forming a bottom electrode of the ferroelectric capacitor on a substrate; forming a first insulating layer on the bottom electrode and the substrate; removing the first insulating layer until a top surface of the bottom electrode is exposed, wherein the bottom electrode disposed in the first insulating layer and the top surface of the bottom electrode is planarized with the first insulating layer; forming a ferroelectric layer covering not only the bottom electrode but also all the first area; and forming a top electrode of the ferroelectric capacitor on the ferroelectric layer overlapped with the bottom electrode. [0028] In accordance with further another aspect of the present invention, there is provided a method of forming a ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, comprising steps of: forming a first insulating layer on a substrate; a forming an opening in the first insulating layer by selectively etching the first insulating layer; forming a bottom electrode of the ferroelectric capacitor in the opening, wherein a top surface of the bottom electrode is planarized with the first insulating layer; forming a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and forming a top electrode of the ferroelectric capacitor on the ferroelectric layer.
DETAILED DESCRIPTION OF THE INVENTION [0042]FIG. 3 is a cross-sectional view showing a FeRAM in accordance with a first embodiment of the present invention. The FeRAM shown in FIG. 3 has a structure that top electrodes of two capacitors are commonly connected to one plate line. [0043] Referring to FIG. 3, a FeRAM includes, two adjacent transistors, a first interlayer insulating layer 35, a bit line, a second interlayer insulating layer 42, a ferroelectric capacitor, a third interlayer insulating layer 45 and a plate line 47, on a semiconductor substrate 31. [0044] Each transistor includes a word line 33 formed on the semiconductor substrate 31, a common drain 34A to which the bit line 37 is coupled, and a source 34B. [0045] The first interlayer insulating layer is formed of a first and second insulating layer 35A, 35B. A tungsten plug 36 is connected to the common drain 34 a through a contact hole formed in the first insulating layer 35A, and a bit line 37 is formed on the first insulating layer 35A and the tungsten plug 36, so that the bit line 37 is coupled to the common drain 34A via the tungsten plug 36. A polysilicon plug 38, a titanium silicide layer 39 and a titanium nitride layer 40 are stacked in a contact hole formed in the first inter layer insulating layer 35 to expose the source 34B. The polysilicon plug or tungsten plug 38 is a contact plug for coupling a bottom electrode of the ferroelectric capacitor to the transistor, the titanium silicide layer 39 is an ohmic contact layer, and the titanium nitride layer 40 is a diffusion barrier. [0046] The ferroelectric capacitor includes a bottom electrode 41, a ferroelectric layer 43 and a top electrode 44. The bottom electrode 41 is formed in an opening defined in the second interlayer insulating layer 42. The ferroelectric layer 43 is formed on the second interlayer insulating layer 42 and the bottom electrode 41. Also, the ferroelectric layer covers all an area in which a plurality of ferroelectric capacitor is formed like cell area. The top electrode 44 is formed on the ferroelectric layer 43 to be overlapped with the bottom electrode 41 and to have the same size as the bottom electrode 41. The ferroelectric layer 43 is formed of SrBi2Ta2O9 (SBT), Bi4-xLaxTi3O12 (BLT), Pb (Zrx, Ti1-x)O3 (PZT), doped-SBT, doped-BLT, doped-PZT or other ferroelectric layer having perovskite or layered perovskite structure. The bottom and the top electrodes 41, 44 are formed of material selected from the group consisting of platinum, iridium, iridium oxide, ruthenium, ruthenium oxide, rhenium, rhodium and combinations thereof. [0047] The third interlayer insulating layer 45 covers the ferroelectric capacitor and has a contact hole exposing the top electrode 44 of the ferroelectric capacitor therein. The plate line 47 is coupled to the top electrode 44 through a diffusion barrier layer 46 formed in the contact hole and connected to the top electrode 44. [0048] In the preferred embodiment of the present invention, the first to third interlayer insulating layer are formed of material selected from a group consisting of oxide, nitride and combination thereof. Specially, the second interlayer insulating layer 42 is formed of material selected from a group consisting of tetraethyl orthosilicate(TEOS), phospho silicate glass(PSG), borophospho silicate glass{BPSG}, silicon nitride and combinations thereof. [0049] The manufacturing method of forming the FeRAM shown in FIG. 3 will be described with reference to FIGS. 4A to 4D. [0050] Referring to FIG. 4A, a device isolation 32 and a plurality of word line 33 are formed on the a semiconductor substrate 31, and source/drain 34A, 34B of a transistor are formed by implanting ions into the semiconductor substrate 31 at both sides of the word line 33. [0051] One of the source/drain becomes a common junction region, i.e. common drain, to which a bit line will be coupled. Therefore, the other of the source/drain becomes source of each transistor. [0052] A first interlayer insulating layer 35A is formed to cover the semiconductor substrate 31 and is flattened. Thereafter, the first insulating layer 35A is etched to form a first contact hole exposing the common drain 34A, and a tungsten plug 36 is formed in the first contact hole. [0053] A first conductive layer is formed on the first insulating layer 35A and is patterned to form the bit line 37 coupled to the common drain 34B through the tungsten plug 36. [0054] A second insulating layer 35B is formed on the first insulating layer 35A and the bit line 37, and the second and first insulating layer 35B, 35A are etched to form second contact hole exposing the source of the transistor, after flattening the second insulating layer 35B. [0055] Each the first and second interlayer insulating layer 35A, 35B forms the first interlayer insulating layer 35. [0056] A polysilicon layer is formed on a surface of the second insulating layer 35B and the second contact hole, and an etch back process is applied to the polysilicon layer to form a polysilicon plug 38 in the second contact hole. Thereafter, a titanium silicide layer 39 is formed on the polysilicon plug 38. At this time, a titanium layer is deposited and is undergone an annealing to form the titanium silicide layer 39, and remaining portions of titanium layer which are not changed to the titanium silicide are removed by an etch process. [0057] A barrier layer 40 is formed on the titanium silicide layer 39 in the second insulating layer 35B, by depositing a layer selected from a group consisting of TiN, TiAlN, TiSiN, RuTiN, CrTiN, and combination layers thereof, on the resulting structure including the titanium silicide 39, and by selectively removing the layer on the second insulating 35B with an etch back or a chemical mechanical polishing (CMP). The barrier layer 40 can be formed on the second insulating layer 35B in order that the barrier layer should have the same width with a bottom electrode of the capacitor to be formed thereon. [0058] The stacked layer of poly silicon plug 38, the titanium silicide 39 and the barrier layer 40 forms a storage node contact. [0059] A bottom electrode 41 is formed on the barrier layer 40 and the second insulating layer 35B by depositing and patterning a second conductive layer. The bottom electrode 41 is formed by depositing material selected from a group consisting of platinum, iridium, iridium oxide, ruthenium, rhenium, rhodium, and combinations thereof with chemical vapor deposition (CVD) or atomic layer deposition layer(ALD). Also, the bottom electrode 41 can be formed of a stack layer like Ir/IrOx/Pt. [0060] A third insulating layer 42 is formed on the bottom electrode 41 and the second insulating layer 35B with material selected from a group consisting of silicon oxide like tetra ethyl ortho silicate (TEOS), phospho silicate glass(PSG), and borophospho silicate glass {BPSG}, silicon nitride and combinations thereof. [0061] Referring to FIG. 4B, the third insulating layer 42 is selectively removed by an etch back or a CMP until the surface of the bottom electrode 41 is exposed. [0062] Referring to FIG. 4C, a ferroelectric layer 43 is formed on the third interlayer insulating layer 42 and the bottom electrode 41. On the ferroelectric layer 43, a top electrode, of which size is not smaller than that of the bottom electrode 41, is formed by depositing and patterning a third conductive layer. The ferroelectric layer 43 is formed of material selected from a group consisting of SrBi2Ta2O9 (SBT), Bi4.xLaxTi3O12 (BLT), Pb (Zrx, Ti1-x)O3 (PZT), doped-SBT, doped-BLT, doped-PZT or other ferroelectric layer having perovskite or layered perovskite structure with a CVD, a spin coating or liquid source misted chemical deposition(LSMCD). The top electrode 44 is formed by depositing material selected from a group consisting of platinum, iridium, iridium oxide, ruthenium, rhenium, rhodium, and combinations thereof with physical vapor deposition (PVD), chemical vapor deposition(CVD) or atomic layer deposition layer(ALD). [0063] As mentioned above and shown in FIG. 4C, the top electrode 44 is fully isolated from the bottom electrode 41 by the ferroelectric layer 43, the size of the top electrode 44 is not limited to smaller size of the bottom electrode 41. Also, the same mask can be used to form the top and bottom electrode because the bottom electrode can be formed to the same size with the top electrode. [0064] Referring to FIG. 4D, a fourth interlayer insulating part 45 is formed on the top electrode 44 and the ferroelectric layer 43, and the fourth interlayer insulating part 45 is selectively etched to form a capacitor contact hole exposing a portion of the top electrode 44. [0065] Thereafter, a diffusion barrier 46 is formed in the capacitor contact hole by deposing, and patterning a layer selected from a group consisting of TiN layer, Ti layer or a Ti/TiN layer. [0066] After forming the diffusion barrier 46, a metal layer is formed on the diffusion barrier 46 and the fourth interlayer insulating layer, and is patterned to form a plate line 47 coupling adjacent top electrodes 44. [0067] In the first embodiment of the present invention, the bottom electrode 41 is formed before forming the third interlayer insulating layer 42, however, the bottom electrode 41 can be formed in a bottom electrode region defined within the third interlayer insulating layer 42 after forming and selectively etching the third interlayer insulating layer 42 to form the bottom electrode region. [0068]FIG. 5A is an equivalent circuit showing a FeRAM in accordance with a second embodiment of the present invention, and FIG. 5B is a layout for embodying the FeRAM shown in FIG. 5A. In FIGS. 5A and 5B, WL1 and WL2 denote word line, BL1 and BL2 denote bit line, BLC1 and BLC3 denote bit line contact, PL1 and PL2 denote plate line, NM1 to NM4 denote NMOS transistor, and FC1 to FC4 denote ferroelectric capacitor. [0069] Referring to FIG. 5A, as shown in �A�, memory cells commonly coupled to the same bit line BL1 share the same plate line PL2. Each memory cell, in the same row, has a ferroelectric capacitor including one electrode coupled to the same plate line and a NMOS transistor including a gate coupled to the same word line, a drain coupled to bit line different from the adjacent memory cell in the same row and a source coupled to another electrode of the ferroelectric capacitor. [0070] Referring to FIG. 5B, the word lines WL1, WL2 and the bit lines BL1, BL2 are arranged to cross each other. For instance, the word lines WL1, WL2 are arranged to Y-axis and the bit lines BL1, BL2 are arranged to X-axis. Bit line contacts BLC1, BLC2 are arranged between the world lines WL1, WL2 for coupling the bit lines to a semiconductor substrate. A first and a second capacitor module CM1, CM2 are arranged parallel to world line WL1, WL2, respectively. The capacitor modules CM1, CM2 are arranged at one side of each word line WL1, WL2, and the bit line contacts BLC1 and BLC2 are arranged the other side of each word line WL1, WL2 in order that the bit line contact and the capacitor module should not be connected to each other. [0071] The first capacitor module CM1 includes storage nodes contact SNC1, SNC2, bottom electrodes BE1, BE2, contacted to the storage node contact SNC1, SNC2, a top electrode TE1, a plate line PL1 and a capacitor contact CAPC1 formed on one end of the plate line PL1 for coupling the top electrode TE1 and the plate line PL1. [0072] The second capacitor module CM2 includes storage nodes contact SNC3, SNC4, bottom electrodes BE3, BE4, contacted to the storage node contact SNC3, SNC4, a top electrode TE2, a plate line PL2 and a capacitor contact CAPC2 formed on one end of the plate line PL2 for coupling the top electrode TE2 and the plate line PL2. [0073] Also, each first and second capacitor module CM1, CM2 includes a ferroelectric layer F in common. Each top electrode TE1, TE2 can be plate line PL1, PL2 it self, that is, in case of this, the plate line PL1, PL2 can be omitted. [0074]FIGS. 6A to 6D are cross-sectional views showing a manufacturing method according to lines X-X′ and Y-Y′ of FIG. 5B. [0075] In FIGS. 6A to 6D, it should be understood that similar reference numerals corresponds to similar elements for FIGS. 4A to 4D. The differences between the first and second embodiment of the present invention are the same as follows. [0076] Two adjacent capacitors along the direction of the world line are isolated by a field oxide 22, as shown in parts of FIGS. 6A to 6D according to line X-X′ of FIG. 5B. Namely, the two adjacent capacitors are not formed on the same active region. [0077] Also, a capacitor contact hole exposing an end of the top electrode 44 is formed in the third insulating part 45 for the capacitor contact CAPC2 as shown in FIG. 6D. Therefore, it is possible to form a large capacitor contact even if cell area is reduced because the capacitor contact is not formed on each capacitor but is formed on an end of the top electrode. [0078] Furthermore, the process for forming a diffusion barrier 46 for preventing titanium elements from diffusing to a ferroelectric layer 43 can be omitted because the capacitor contact is formed on an end of the top electrode so that titanium elements diffused from the plate line do not affect on the characteristic of the ferroelectric layer 43. In case of forming the diffusion barrier layer 46, the surface of the third insulating part 45 is changed during an etch process for forming a pattern of the diffusion barrier layer 46, therefore, some problems are generated, and it is difficult to form a contact hole exposing a bit line in a peripheral region to a predetermined shape by a wet etch process. However, in case of omitting the process of forming the diffusion barrier, it is possible to form the contact hole to a wine glass shape by a wet etching. Accordingly, a conductive layer is filled well in the contact hole and contact resistance is reduced. [0079]FIG. 7 is a layout of a FeRAM according to a third embodiment of the present invention, and FIGS. 8A and 8B are cross-sectional views showing a manufacturing method according to a line Y-Y′ of FIG. 7. [0080] In FIG. 7, it should be understood that similar reference numerals corresponds to similar elements for FIG. 5B. The differences between the second and third embodiment of the present invention are the same as follow. [0081] Capacitor contact for coupling a top electrode and a plate line is arranged on each ferroelectric capacitor. In FIG. 7, CAPC11 and CAPCl2 denote capacitor contacts on each capacitor module, CM1 and CM2. [0082] The method of forming the FeRAM in accordance with the third embodiment is shown in FIGS. 8A and 8B. In FIGS. 8A and 8B, it should be understood that similar reference numerals corresponds to similar elements for FIGS. 4A to 4D. [0083] Referring to FIG. 8A, an interlayer insulating layer 65 and an adhesion layer 68 are formed on a ferroelectric layer 43. The adhesion layer 68 is formed of TiO2 or Al2O3. [0084] A contact hole 69 exposing the ferroelectric layer 43 is formed by selectively etching the adhesion layer 68 and the interlayer insulating layer 65. At this time, a wet etch is adopted to the adhesion layer 68 and the interlayer insulating layer in order that the ferroelectric layer 43 is not deteriorated due to plasma. [0085] Referring to FIG. 8B, conductive layers are formed on a resulting structure including the contact hole 69, and the conductive layer are patterned to form a top electrode 64 and a plate line 67 through one etch process. At this time, the top electrode is formed to a size not smaller than that of a bottom electrode 61, and the plate line 67 is formed of a TiN/Ti/Al/TiN stack layer. [0086]FIG. 9 is a layout of a FeRAM according to a fourth embodiment of the present invention, and FIGS. 10A and 10B are cross-sectional views showing a manufacturing method according to lines Y-Y′ and X-X′ of FIG. 9, respectively. [0087] In FIG. 9, it should be understood that similar reference numerals corresponds to similar elements for FIGS. 5B and 7. The third embodiment of the present invention is different from the third embodiment in that capacitor contacts CPAC11, CAPC12, CAPC1, CAPC2 are arranged not only on each ferroelectric capacitor but also on an end of each top electrode, as shown in FIG. 9, and plate lines are coupled to the top electrode through only the capacitor contact arranged on the ends of the top electrode as shown in FIG. 10B. [0088] The method of forming the FeRAM in accordance with the fourth embodiment is shown in FIGS. 10A and 10B. In FIGS. 10A and 10B, it should be understood that similar reference numerals corresponds to similar elements for FIGS. 8A and 8B. [0089] Referring to FIG. 10A, a top electrode 64 is formed in a contact hole within an adhesion layer 68 and an interlayer insulating layer 65 and on a ferroelectric layer 43 to a size not smaller than a bottom electrode 61. [0090] Referring to FIG. 10B, a conductive layer is formed on a resulting structure including the top electrode 64 and is patterned to form the plate line 67 on each end of the top electrode. [0091]FIG. 11 is a cross sectional view of FeRAM including a ferroelectric layer only in a cell area I in accordance with the present invention. As shown in FIG. 11, a ferroelectric layer 43 is not formed on a peripheral circuit area II. [0092] The ferroelectric layer in cell region FeRAM in accordance with the present invention, therefore, it is possible to prevent the ferroelectric layer being deteriorated from plasma, and to form the top electrode larger than the bottom electrode. Also, the burden of etch process adopted to form the ferroelectric capacitor is reduces owing to the step height of a target layer is reduced. Furthermore, in case of forming the capacitor contact only on an end of the top electrode, the possibility of the contact between the plate line and the bottom electrode, and the difficulty of forming the capacitor contact can be reduced even if the cell size is decreased. BRIEF DESCRIPTION OF THE DRAWINGS [0029] Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which: [0030]FIG. 1 is a conventional equivalent circuit illustrating a FeRAM having a 1T-1C structure; [0031]FIG. 2 is a cross-sectional view showing a conventional FeRAM; [0032]FIG. 3 is a cross-sectional view showing a FeRAM in accordance with a first embodiment of the present invention; [0033]FIGS. 4A to 4D are cross-sectional views showing manufacturing method of FeRAM shown in FIG. 3; [0034]FIG. 5A is an equivalent circuit showing a FeRAM in accordance with a second embodiment of the present invention; [0035]FIG. 5B is a layout for embodying the FeRAM shown in FIG. 5A; [0036]FIGS. 6A to 6D are cross-sectional views showing a manufacturing method of FeRAM shown in FIGS. 5A and 5B; [0037]FIG. 7 is a layout in accordance with a third embodiment of the present invention; [0038]FIGS. 8A and 8B are cross-sectional views showing a manufacturing method of FeRAM shown in FIG. 7; [0039]FIG. 9 is a layout diagram in accordance with a fourth embodiment of the present invention; [0040]FIGS. 10A and 10B are cross-sectional view according to a Y-Y′ line and X-X′ line in FIG. 9; and [0041]FIG. 11 is a cross sectional view of FeRAM including a ferroelectric layer only in a cell area in accordance with the present invention.
Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7179739 *Jun 8, 2004Feb 20, 2007Samsung Electronics Co., Ltd.Methods of forming a semiconductor device including a metal silicide layer between a conductive plug and a bottom electrode of a capacitorUS7629636 *Dec 7, 2007Dec 8, 2009Fujitsu Microelectronics LimitedSemiconductor device and manufacturing method thereofUS7820456Oct 29, 2009Oct 26, 2010Fujitsu Semiconductor LimitedSemiconductor device and manufacturing method thereof* Cited by examinerClassifications U.S. Classification257/295, 257/306, 257/E21.664, 257/310, 438/244, 438/3, 257/E27.099International ClassificationG11C11/22, H01L21/8246, H01L27/11Cooperative ClassificationH01L27/11502, H01L27/1104, H01L27/11507, G11C11/22European ClassificationG11C11/22, H01L27/11F, H01L27/115C, H01L27/115C4Legal EventsDateCodeEventDescriptionFeb 1, 2013FPAYFee paymentYear of fee payment: 8Jan 7, 2009FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google