Source: http://www.google.com/patents/US7583534?dq=5,675,808
Timestamp: 2014-03-17 19:21:04
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Patent US7583534 - Memory utilizing oxide-conductor nanolaminates - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsOne floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential...http://www.google.com/patents/US7583534?utm_source=gb-gplus-sharePatent US7583534 - Memory utilizing oxide-conductor nanolaminatesAdvanced Patent SearchPublication numberUS7583534 B2Publication typeGrantApplication numberUS 11/217,771Publication dateSep 1, 2009Filing dateAug 31, 2005Priority dateJul 8, 2002Fee statusPaidAlso published asUS7221017, US7687848, US20040004245, US20060008966, US20070178643, US20090218612Publication number11217771, 217771, US 7583534 B2, US 7583534B2, US-B2-7583534, US7583534 B2, US7583534B2InventorsLeonard Forbes, Kie Y. AhnOriginal AssigneeMicron Technolgy, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (102), Non-Patent Citations (77), Referenced by (5), Classifications (19), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMemory utilizing oxide-conductor nanolaminatesUS 7583534 B2Abstract One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers.
CROSS REFERENCE TO RELATED APPLICATIONS The present application is a divisional of U.S. application Ser. No. 10/191,336, filed Jul. 8, 2002, now issued as U.S. Pat. No. 7,221,017, which is incorporated herein by reference in its entirety.
This application is related to the following, commonly assigned U.S. patent applications: �Memory Utilizing Oxide Nanolaminates,� Ser. No. 10/190,717, filed Jul. 8, 2002, now issued as U.S. Pat. No. 7,221,586; and �Memory Utilizing Oxide-Nitride Nanolaminates,� Ser. No. 10/190,689, filed Jul. 8, 2002; each of which disclosure is herein incorporated by reference.
Eitan, B. et al., �Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM device,� IEEE Electron Device Lett., 22(11), 556-558 (November 2001);
Britton, J. et al., �Metal-Nitride-Oxide IC Memory Retains Data for Meter Reader,� Electronics, 45(22); 119-23(23 Oct. 1972);
A. Yagishita et al., �Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) with low threshold voltage, high drive current and uniform electrical characteristics,� Digest Technical Papers Int. Electron Devices Meeting, San Francisco, pp. 663-666 (December 2000);
A. Yagishita et al., �Dynamic Threshold Voltage Damascene Metal Gate MOSFET (DT-DMG-MOS) With Low Threshold Voltage, High Drive Current and Uniform Electrical Characteristics,� Digest Technical Papers Int. Electron Devices Meeting, San Francisco, Dec. 2000, pp. 663-666;
X in Resistivity, Donor concentration, Mobility, ZnO1�xSx Ω cm cm−3 cm2/V s 0 0.0048 4.8 � 1019 13.2 0.25 0.101 1.7 � 1018 36.1 0.56 0.042 1.66 � 1019 32.2 0.66 1.28 2.0 � 1017 24 0.82 8.27 2.4 � 1016 28 0.92 67.9 2.61 � 1015 94 Atomic Layer Deposition of Metal Films
W: The atomic layer deposition (ALD) of tungsten (W) films has been demonstrated using alternate exposure of tungsten hexafluoride (WF6) and disilane (Si2H6). The present investigation explored the kinetics of the WF6 and Si2H6 surface reactions during W ALD at 303-623 K using Auger electron spectroscopy technique. The reaction of WF6 with the Si2H6-saturated W surface proceeded to completion at 373-573 Kelvin (K). The WF6 reaction displayed a reactive sticking coefficient of S=0.4 and required an exposure of 30 L (1 L=1*10−6 Torr s) to achieve saturation at 573 K. The WF6 exposures necessary to reach saturation increased with decreasing temperature. At surface temperatures<373 K, the WF6 reaction did not consume all the silicon (Si) surface species remaining from the previous Si2H6 exposure. The reaction of Si2H6 with the WF6-saturated W surface displayed three kinetic regimes. In the first region at slow Si2H6 exposures< or =50 L, the Si2H6 reaction is independent of temperature and had a reactive striking coefficient of S�5*10−2. In the second kinetic region at intermediate Si2H6 exposure of 50-300 L, the Si2H6 reaction showed an apparent saturation behavior with Si thickness at saturation at increased at substrate temperature. At high Si2H6 exposures of 300-1*105/L, additional Si is deposited with an approximately logarithmic dependence on Si2H6 exposure. The Si2H6 reaction in this third kinetic region had an activation energy E=2.6 kcal/mol and the Si thickness deposited by a 1.6*105 L Si2H6 exposure increased with temperature from 3.0 Å at 303 K to 6.6 Å at 623 K. These kinetic results should help to explain W ALD growth rates observed at different exposures and substrate temperatures.
Further, in embodiments of the present invention, the gate structure embodiment of FIG. 5, having silicon oxide-metal oxide-silicon oxide-conductor nanolaminates, is used in place of the gate structure provided in the following: Eitan, B. et al., �NROM: A novel localized Trapping, 2-Bit Nonvolatile Memory Cell,� IEEE Electron Device Lett., 21(11), 543-545 (November 2000); Eitan, B. et al., �Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM device,� IEEE Electron Device Lett., 22(11), 556-558 (November 2001); Maayan, E. et al., �A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate,� Dig. IEEE Int. Solid-State Circuits Conf., 100-101 (2002). In these embodiments, the gate structure embodiment of FIG. 5, having silicon oxide-metal oxide-silicon oxide-conductor nanolaminates used in place of the gate structures in those references, can be programmed in the reverse direction and read in the forward direction to obtain more sensitivity in the device characteristics to the stored charge.
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IEDM, (Dec. 2000),663-666.76Yoder, M, "Wide Bandgap Semiconductor Materials and Devices", IEEE Transactions on Electron Devices, 43, (Oct. 1996),1633-1636.77Zhu, W J., et al., "Current transport in metal/hafnium oxide/silicon structure", IEEE Electron Device Letters, 23, (2002),97-99.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7872901 *Dec 17, 2007Jan 18, 2011International Business Machines CorporationProgrammable-resistance memory cellUS7973357 *Dec 18, 2008Jul 5, 2011Samsung Electronics Co., Ltd.Non-volatile memory devicesUS8264863 *Aug 27, 2010Sep 11, 2012Semiconductor Manufacturing International (Shanghai) CorporationGreen transistor for nano-Si ferro-electric RAM and method of operating the sameUS8314457Apr 27, 2011Nov 20, 2012Samsung Electronics Co., Ltd.Non-volatile memory devicesUS20110090731 *Aug 27, 2010Apr 21, 2011Semiconductor Manufacturing International (Shanghai) CorporationGreen transistor for nano-si ferro-electric ram and method of operating the same* Cited by examinerClassifications U.S. Classification365/185.18, 257/315, 365/185.05, 257/314International ClassificationG11C11/56, H01L29/788, H01L29/423, H01L27/115, G11C16/04, G11C16/06Cooperative ClassificationG11C16/0416, H01L29/42332, G11C11/5671, H01L27/115, H01L29/7885European ClassificationH01L29/423D2B2C, G11C11/56M, H01L29/788B6B, H01L27/115Legal EventsDateCodeEventDescriptionJan 30, 2013FPAYFee paymentYear of fee payment: 4Oct 13, 2009CCCertificate of correctionRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google