Source: http://www.google.com/patents/US6556484?dq=system+for+measuring+web+traffic&ei=Lg8FT__TIIr-sQKzxaGRCg
Timestamp: 2017-12-15 07:45:47
Document Index: 579355358

Matched Legal Cases: ['Art” 1', 'Art 1', 'art 112', 'Art 1', 'Art 1', 'Art 1', 'art 12', 'art 12']

Patent US6556484 - Plural line buffer type memory LSI - Google Patents
In a plural line buffer type memory LSI, a line selection register 16 (holding an address for designating a line buffer) is added. The value of the line selection register 16 is previously updated by a memory access instruction having a room in an address. Thus, it is possible to maintain compatibility...http://www.google.com/patents/US6556484?utm_source=gb-gplus-sharePatent US6556484 - Plural line buffer type memory LSI
Publication number US6556484 B2
Application number US 09/746,809
Also published as US20020021591
Publication number 09746809, 746809, US 6556484 B2, US 6556484B2, US-B2-6556484, US6556484 B2, US6556484B2
Inventors Yoshikazu Yabe, Masato Motomura
US 6556484 B2
In a plural line buffer type memory LSI, a line selection register 16 (holding an address for designating a line buffer) is added. The value of the line selection register 16 is previously updated by a memory access instruction having a room in an address. Thus, it is possible to maintain compatibility with input/output terminals of a general purpose memory LSI, or to prevent the increase in the number of input/output terminals, and also to prevent the increase of the memory access delay attributable to the restriction in connection with the issue of the commands. Accordingly, it is possible to maintain the compatibility with the general purpose memory LSI having no line buffer, or alternatively to prevent the increase of the memory access delay attributable to a restriction in an interval for issuing the commands.
1. A plural line buffer type memory LSI comprising:
a plural line buffer section including a plurality of line buffers connected to said memory section; and
a data buffer connected to said plural line buffer section,
so that a data transfer is carried out between said memory section and said plural line buffer section and between said plural line buffer section and said data buffer,
the plural line buffer type memory LSI further comprising a line selection register for designating at least one line buffer in said plural line buffer section.
2. A plural line buffer type memory LSI claimed in claim 1, wherein a data transfer is carried out between said memory section and the line buffer designated by said line selection register.
an operation instruction for writing a page or a portion of the page in said memory section designated and pre-activated by said bank address, to the line buffer designated by said line selection register; and then,
an operation instruction for outputting a word designated by said column address, in the data held in the line buffer designated by said line selection register, to said data input/output terminal group.
10. A plural line buffer type memory LSI claimed in claim 5, wherein through said command input terminal group and said address input terminal group, a bank address and a column address are inputted, and the following operation instructions are given:
an operation instruction for writing data inputted from said data input/output terminal group, to a word designated by said column address, in the data held in the line buffer designated by said line selection register.
11. A plural line buffer type memory LSI claimed in claim 10, wherein after completion of the operation of said instruction given, but prior to a next memory access operation, a pre-charging of said memory section is automatically executed.
The present invention relates to a plural line buffer type memory LSI, and more specifically to a plural line buffer type memory LSI including a plurality of line buffers added to a memory section so as to be able to effectively reduce a memory access delay.
As a typical example of the above mentioned plural line buffer type memory LSI, a Virtual Channel Memory (VCM) architecture reported by NEC Corporation is already known. This VCM architecture is actually incorporated in a commercially available 128M-bit DRAM, and is disclosed in a 128M-bit Virtual Channel SDRAM Data Sheet available from NEC Corporation. FIG. 19 briefly illustrates a circuit block of the 128M-bit VC-SDRAM. This 128M-bit VC-SDRAM will be called a “Prior Art” 1 in this specification. In this Prior Art 1, a line buffer is called a channel. As well known, a memory section 107 in the DRAM is activated in units of page, and the activated page is read out to a sense amplifier part 112 within the memory section 107. In the case of a conventional DRAM (called a “page type memory LSI” hereinafter), data is read out in units of word, from the activated page (read out to the sense amplifier part). (The page type memory LSI is exemplified by SDRAM, and its detail is disclosed in a 128M-bit SDRAM Data Sheet available from NEC Corporation.) Differently from this SDRAM, the VC-SDRAM of the Prior Art 1 is characterized in that data of a portion called a segment, in the activated page, is read and written at a time between the memory section and a plural line buffer section 108. In the Prior Art 1, here, the size of the page, the segment and the word are 8 kbits, 2 kbits and 16 bits, respectively, and the number of the line buffers is 16. FIG. 20 shows a truth table of commands used in the Prior Art 1. Here, a bank address, a row address, a segment address (indicating a segment within a page), a column address, and a line buffer number are 1 bit, 14 bits, 2 bits, 9 bits and 4 bits, respectively.
Accordingly, it is an object of the present invention to provide a plural line buffer type memory LSI capable of reducing the delay time in the memory access attributable to the restriction in connection with the issue of the commands.
FIG. 1 is a circuit block diagram illustrating the plural line buffer type memory LSI in accordance with the present invention;
As shown in the drawings, an embodiment of the plural line buffer type memory LSI in accordance with the present invention is provided with memory sections and a plural line buffer section. As shown in FIG. 1, the memory sections 7 are bidirectionally connected to the plural line buffer section 8. A control circuit 6 is connected to the memory sections 7 and the plural line buffer section 8. An address buffer 4 and a command decoder 5 are connected to the control circuit 6.
FIG. 3 and FIG. 4 show a timing chart illustrating an operation of the plural line buffer type memory LSI in accordance with the present invention and an address allocation in the address input terminal group 1, respectively. A data transfer for transferring the data from the memory section 7 to the plural line buffer section 8 is shown (in the following, a command for executing this operation will be called an “APFC”). Here, a bank address (an address for selecting data included in one of the memory sections 7) and a row address are composed of 1 bit and 13 bits, respectively, and the address input terminal group is composed of 14 bits.
FIG. 5 and FIG. 6 show a timing chart illustrating another mode of the operation of the plural line buffer type memory LSI in accordance with the present invention and another address allocation in the address input terminal group 1, respectively. A data transfer for transferring the data from the plural line buffer section 8 to the memory section 7 is shown (in the following, a command for executing this operation will be called an “ARST”). Here, the bank address and the row address are composed of 1 bit and 13 bits, respectively, and the address input terminal group 1 is composed of 14 bits. As shown in FIG. 5, at a time T1, the ARST instruction is inputted together with the bank address and the row address.
FIG. 7 and FIG. 8 show a timing chart illustrating still another mode of the operation of the plural line buffer type memory LSI in accordance with the present invention and still another address allocation in the address input terminal group 1, respectively. Here, a data transfer for transferring the data from the plural line buffer section 8 to the data input/output terminal group 3 is shown (in the following, a command for executing this operation will be called an “READ”). A column address is composed of 9 bits, and the address input terminal group 1 is composed of 14 bits.
FIG. 9 and FIG. 10 show a timing chart illustrating a further mode of the operation of the plural line buffer type memory LSI in accordance with the present invention and a further address allocation in the address input terminal group 1, respectively. Here, a data transfer for transferring the data from the data input/output terminal group 3 to the plural line buffer section 8 is shown (in the following, a command for executing this operation will be called an “WRITT”). A column address is composed of 9 bits, and the address input terminal group 1 is composed of 14 bits.
FIG. 11 and FIG. 12 show a timing chart illustrating a sixth mode of the operation of the plural line buffer type memory LSI in accordance with the present invention and an address allocation in the address input terminal group 1, respectively. An operation for transferring the data from the sense amplifier part 12 in the memory section 7 through the plural line buffer section 8 to the data input/output terminal group 3 is shown (in the following, a command for executing this operation will be called an “PER”). Here, a bank address, a row address and a column address are composed of 1 bit, 13 bits and 9 bits, respectively, and the address input terminal group is composed of 14 bits.
FIG. 13 and FIG. 14 show a timing chart illustrating a still further mode of the operation of the plural line buffer type memory LSI in accordance with the present invention and a still further address allocation in the address input terminal group 1, respectively. An operation for transferring the data from the sense amplifier part 12 in the memory section 7 to the plural line buffer section 8 and succeedingly writing the data inputted to the data input/output terminal group 3 to the plural line buffer section 8 is shown (in the following, a command for executing this operation will be called an “PFW”). Here, a bank address, a row address and a column address are composed of 1 bit, 13 bits and 9 bits, respectively, and the address input terminal group is composed of 14 bits.
FIG. 15 and FIG. 16 show a timing chart illustrating a still further mode of the operation of the plural line buffer type memory LSI in accordance with the present invention and a still further address allocation in the address input terminal group 1, respectively. Here, an operation for updating the value of the line selection register 16 is shown (in the following, a command for executing this operation will be called an “STCR”). A line selection register number (an address for selecting one of the plurality of line selection registers 16) and a line buffer number are composed of 2 bits and 4 bits, respectively, and the address input terminal group is composed of 14 bits.
JPH05274862A Title not available
JPH07134895A Title not available
JPS6214190A Title not available
US8151150 * Feb 15, 2010 Apr 3, 2012 Silicon Motion, Inc. Data storage device and method for writing test data to a memory
US20110035636 * Feb 15, 2010 Feb 10, 2011 Silicon Motion, Inc. Data storage device and method for writing test data to a memory
U.S. Classification 365/189.05, 365/230.08, 365/230.03
International Classification G11C11/409, G11C7/10, G11C11/401, G11C11/407, G11C11/40
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YABE, YOSHIKAZU;MOTOMURA, MASATO;REEL/FRAME:011415/0565