Source: http://www.google.com/patents/US8120312?dq=5359317
Timestamp: 2013-12-06 06:40:07
Document Index: 629711543

Matched Legal Cases: ['Application No. 2005510056', 'Application No. 2004034107', 'Application No. 2004087906', 'Application No. 2004194913', 'Application No. 2007240920', 'Application No. 2007240920', 'Application No. 2007100801777', 'Application No. 2004100039347', 'Application No. 200410062105', 'Application No. 3801413', 'Application No. 93102793', 'Application No. 93119744', 'Application No. 3814354', 'Application No. 4002904', 'Application No. 4002904', 'Application No. 4002904', 'Application No. 4006551', 'Application No. 4006551', 'Application No. 4014686', 'Application No. 4014686', 'Application No. 4014686', 'Application No. 4801781', 'Application No. 2007', 'Application No. 2003354266', 'Application No. 2004087906', 'Application No. 2005510056', 'Application No. 2005518382', 'Application No. 2005518382', 'Application No. 1020040019300', 'Application No. 1020040040629', 'Application No. 1020040040629', 'Application No. 1020040051380', 'Application No. 92130623', 'Application No. 2005510056']

Patent US8120312 - Power management topologies to control power between a DC power source and ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsA power supply topology according to one embodiment includes a first path coupled to a controllable DC power source, a second path coupled to a rechargeable battery, and a third path coupled to a system load, the three paths coupled to a common node. The topology may further include a unidirectional...http://www.google.com/patents/US8120312?utm_source=gb-gplus-sharePatent US8120312 - Power management topologies to control power between a DC power source and one or more batteries to a system loadPublication numberUS8120312 B2Publication typeGrantApplication numberUS 12/877,076Publication dateFeb 21, 2012Filing dateSep 7, 2010Priority dateSep 21, 2000Also published asCN1330070C, CN1578047A, EP1494332A2, EP1494332A3, US7348760, US7791314, US20040178766, US20080231117, US20100327813Publication number12877076, 877076, US 8120312 B2, US 8120312B2, US-B2-8120312, US8120312 B2, US8120312B2InventorsConstantin Bucur, Daryl Nees, Marian Niculae, Vlad Mihail Popescu-StanestiOriginal Assignee02Micro International LimitedPatent Citations (105), Non-Patent Citations (42), Classifications (29) External Links: USPTO, USPTO Assignment, EspacenetPower management topologies to control power between a DC power source and one or more batteries to a system loadUS 8120312 B2Abstract A power supply topology according to one embodiment includes a first path coupled to a controllable DC power source, a second path coupled to a rechargeable battery, and a third path coupled to a system load, the three paths coupled to a common node. The topology may further include a unidirectional switch coupled to the first path and a selectively unidirectional switch coupled to the second path. The topology may further include a power management control circuit including a wake up circuit having a comparison circuit and an output decision circuit. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
20. The apparatus of claim 17, wherein said selector signal comprises a digital signal, and wherein said second switch is in a full conduction state in response to said digital signal in a first state. Description
CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. Nonprovisional Application Ser. No. 12/054,743 filed Mar. 25, 2008, now U.S. Pat. No. 7,791,314, which itself is a continuation of U.S. Nonprovisional Application Ser. No. 10/812,802 filed Mar. 30, 2004, now U.S. Pat. No. 7,348,760, which itself is a continuation-in-part application of U.S. Nonprovisional Application Ser. No. 10/652,110 filed Aug. 29, 2003, which itself is a continuation-in-part application of U.S. Nonprovisional Application Ser. No. 10/364,228 filed Feb. 11, 2003, now U.S. Pat. No. 6,977,482, the teachings of which are incorporated herein by reference, and claims the benefit of the filing date of U.S. Provisional Application Ser. No. 60/484,635, filed Jul. 3, 2003, the teachings of which are also incorporated herein by reference. U.S. Nonprovisional Application Ser. No. 10/652,110 filed Aug. 29, 2003 is also a continuation-in-part of U.S. Nonprovisional Application Ser. No. 09/960,453 filed Sep. 21, 2001, now U.S. Pat. No. 6,741,006, the teachings of which are incorporated herein by reference, and claims the benefit of the filing date of U.S. Provisional Application Ser. No. 60/234,442, filed Sep. 21, 2000, the teachings of which are also incorporated herein by reference.
FIELD OF THE INVENTION The present invention relates to power management systems, and in particular to various power management topologies for electronic devices.
BACKGROUND OF THE INVENTION Various portable electronic devices have a power supply system that monitors, controls, and directs power from various power sources to supply power to the system load of the electronic device. These power sources generally include a fixed output ACDC adapter and one or more rechargeable batteries. The power supply system contains a power conversion block, e.g., a DC to DC converter to convert a fixed DC voltage supplied by the ACDC adapter to a finely controlled variable output DC voltage to charge the battery.
DETAILED DESCRIPTION FIG. 1 illustrates a simplified block diagram of an electronic device 100 having a system load 110 capable of being powered by a controllable DC power source 104, a battery 105, or by both in parallel as the need arises as further detailed herein. A table 180 showing the position of switches SW1 and SW2 in various power supply modes is also illustrated. In one embodiment, the controllable DC power source 104 may be a controllable adapter as further detailed herein, e.g., an ACDC adapter, that provides the only power conversion necessary to deliver power to the system load 110 and the battery 105. As such, the need for an additional power conversion step (e.g., a DC to DC converter to provide a finely controlled output to the battery for charging) typically utilized in other power supply systems is obviated in this instance.
The DC to DC converter 104 b may be any variety of converters controlled by any variety of control signals along path 303 from the power management control circuit 130. In one embodiment, the DC to DC converter 104 b may be a buck converter having a high side switch, a low side switch, and an LC filter as is known in the art. The control signal from the power management circuit 130 may be a pulse width modulated (PWM) signal. The width of the PWM signal controls the duration of the �switch ON� state (high side switch ON and low side switch OFF) and �switch OFF� state (high side switch OFF and low side switch ON) and hence the output voltage and current level of the DC to DC converter 104 b. Turning to FIGS. 4 through 8, various embodiments of power supply systems consistent with the invention are illustrated having a controllable adapter 104 a as the controllable DC power source 104 and two batteries (Battery A and B). As such, the embodiments of FIGS. 4 through 8 have one power conversion due to the controllable adapter 104 a to supply power to the system load 110 and the battery 105. The one step power conversion embodiments may be used independently of, or together with, the earlier detailed buffer battery power supply mode enabling both the battery and controllable DC power source to provide power to the system load 110.
In contrast, FIGS. 9 through 15 as further detailed herein are directed to additional embodiments having a controllable DC to DC converter 104 b as the controllable DC power source 104 and also having two batteries (Batteries A and B). The embodiments of FIGS. 9 through 15 therefore have at least two power conversions due to a fixed adapter 302 and the DC to DC converter 104 b. The embodiment of FIG. 4 may have all the functionality earlier detailed regarding FIG. 1 and FIG. 2. However, the embodiment of FIG. 4 may or may not have the earlier detailed buffer battery power supply mode enabling both the battery and controllable DC power source to provide power in parallel to the system load 110. For instance, a particular power supply system may only desire the one step power conversion and not be concerned with the buffer battery power supply mode.
Turning to the power management control circuit 130, it may include a host interface 13, a plurality of current sense amplifiers 14, 15, 17, 18, associated control and data paths, and a decision circuit 16. The decision circuit 16 may further include a selector circuit 409 to provide a first set of output signals via bus 20 to control the state of switches SW1, SW2A, and SW2B. The decision circuit 16 may also include a control circuit 411 to provide a second set of output signals via path 133 to control an output parameter of the controllable adapter 104 a. The host interface 13 is a generic interface configured to accept an input set of signals from the PMU 12 and to output a converted set of signals to the decision circuit 16 via internal signal bus 23. Such signals provided to the decision circuit 16 may contain voltage and current limits for Battery A, Battery B, the controllable adapter 104 a, and the system load 110. The host interface 13 may accept analog or digital signals from the PMU 12.
The plurality of current sense amplifier 14, 15, 17, 18 amplifies signals from the respective sense resistors 3, 4, 5, 7 since the sense resistor is typically quite small. For instance, sense amplifier 14 amplifies the voltage drop across the system sense resistor 3 and provides an ISYS signal representative of the current flow along path 121. Sense amplifier 15 amplifies the voltage drop across the adapter sense resistor 4 and provides an IAD signal representative of the current flow along path 114. Sense amplifier 17 amplifies the voltage drop across the Battery B sense resistor 5 and provides an ICDB signal representative of current flow along path 118 b. Finally, sense amplifier 18 amplifies the voltage drop across the Battery A sense resistor 7 and provides an ICDA signal representative of current flow along path 118 a. The ISYS, IAD, ICDB, and ICDA signals from the respective sense amplifiers 14, 15, 17, 18 may then be provided to the decision circuit 16, and in particular, to the control circuit 411 portion of the decision circuit 16. In addition, the VFB_SYS signal representative of the voltage level of the system load 110, the VFB_B signal representative of the voltage level of Battery B, and the VFB_A signal representative of the voltage level of Battery A may also be provided to the decision circuit 16, and in particular, to the control circuit 411 portion of the decision circuit 16.
providing all the necessary adapter current up to a maximum output current level of the adapter or up to the power supply limits of the system load 110, and if requested to provide charging current to charge the battery source 105; Limiting the total charging current delivered to the battery 105 during a charging mode to the difference between the maximum output current level of the adapter 104 a and the required current of the system load 110; providing the maximum charging current to each battery (Battery A and B) as long as the maximum charging voltage level has not been reached for any of the batteries; providing up to the maximum charging current to the lowest voltage battery as long as the maximum charging voltage has not been reached for any of the batteries; and providing a set maximum supply voltage to the system load 110 when no battery is present or no charge request is received. Those skilled in the art will recognize various ways that such functionality of the control circuit 411 portion of the decision circuit 16 may be accomplished through hardware only, software only, or some combination thereof. For instance, with hardware the control circuit 411 may include a plurality of error amplifiers to compare signals ISYS, IAD, ICDB, ICDA, VFB_SYS, VFB_B, and VFB_A with an associated maximum threshold level for each monitored parameter. The plurality of error amplifiers may be configured as an analog �wired-OR� topology such that the error amplifier that first detects a condition exceeding the associated maximum level controls the command signal to the controllable adapter 104 a. An appropriate output signal may then be sent to the controllable adapter 104 a, e.g., to lessen an output power parameter of the adapter 104 a if a maximum threshold limit is reached.
ensuring an uninterrupted power supply to the system load 110 as long as at least one power source (ACDC adapter 104 a, Battery A, Battery B) is present; connecting the appropriate battery or batteries to a charging path as requested by the PMU 12; connecting the appropriate battery or batteries to a discharging path to supply power to the system load 110 as requested by the PMU 12; avoiding cross conduction between batteries when a number of batteries are coupled in parallel and between the ACDC adapter and the batteries in parallel supply mode; independently solving any power crises event such as power source connection/disconnection, short circuits, and the like; and independently and safely managing the power supply system when the host PMU 12 fails to send the appropriate control signal. To accomplish such tasks, especially such tasks dependent on use of two or more batteries (e.g., to avoid cross conduction between batteries), reference should be made to U.S. patent application Ser. No. 10/364,228 filed Feb. 11, 2003, the teachings of which are incorporated herein by reference, which discloses a selector circuit that may be utilized as part of a power supply system consistent with the invention.
When the output decision circuit 1612 provides the comparison output signal from the comparison circuit 1718 to the switch SW2A1, the switch SW2A1 is responsive to this signal to limit the charging current level provided to Battery A to the wake up current level. In one embodiment, the switch SW2A1 may provide a constant current flow to Battery A equal to the wake up charging current level. The comparison output signal may be an analog signal and the switch SW2A1 may be responsive to this analog signal to enter an intermediate conduction state. As used herein, an �intermediate conduction state� means a state that at least somewhat limits current flowing from one terminal to another terminal of the switch. As such, the switch SW2A1 in an intermediate conduction state may limit current provided to battery A to a wake up current level when the battery A is deeply discharged. In one instance, the switch SW2A1 may behave like an error amplifier controlled resistor when it receives the comparison output signal from the comparison circuit 1718.
When the output decision circuit 1612 provides the selector output signal, the switch SW2A1 is responsive to this signal to be either ON or OFF. The signal provided by the selector circuit may be a digital signal such that if the digital signal is a digital one, switch SW2A1 may be ON and if the digital signal is a digital zero, switch SW2A1 may be OFF. When switch SW2A1 is ON in response to the selector output signal, the switch SW2A1 may be in a full conduction state. As used herein, a �full conduction state� means a state that does not appreciably limit current flowing from one terminal to another terminal of the switch. Therefore, if switch SW2A1 is ON in response to the selector output signal, normal charging current levels may then be provided to Battery A. Therefore, the comparison output signal, e.g., an analog signal in one embodiment, may be utilized to control switch SW2A1 when Battery A is deeply discharged and hence charging current may be limited to a wake up charging current level. In addition, the selector output signal, e.g., a digital signal in one embodiment, may be utilized to control switch SW2A1 and provide higher normal charging current levels to Battery A.
It will be appreciated that the functionality described for the embodiments of the power management control circuit and wake up circuit may also be implemented using software, or a combination of hardware and software. If implemented in software, a processor and machine-readable medium may be required. The processor can be any type of processor capable of providing the speed and functionality required by the embodiments of the invention. For example, the processor could be a process from the Pentium� family of processors made by Intel Corporation, or the family of processors made by Motorola. Machine-readable media include any media capable of storing instructions adapted to be executed by a processor. Some examples of such media include, but are not limited to, read-only memory (ROM), random-access memory (RAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), dynamic RAM (DRAM), magnetic disk (e.g. floppy disk and hard drive), optical disk (e.g. CD-ROM), and any other device that can store digital information. In one embodiment, the instructions may be stored on the medium in a compressed and/or encrypted format.
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No. 10/685,043, dated Mar. 4, 2005.40Office Action issued in U.S. Appl. No. 11/463,042, dated Dec. 14, 2007.41Office Action issued in U.S. Appl. No. 9960453, dated Dec. 20, 2002.42Official Inquiry issued in Japanese Application No. 2005510056, dated Nov. 18, 2008, with English translation.Classifications U.S. Classification320/106International ClassificationH02J7/02, H02J9/06, H02J7/00, H01M10/46, H02J3/00, H02J7/34, H02M3/00, H02J7/04Cooperative ClassificationH02J9/061, Y02T10/7055, H02J2007/0059, H02J7/0027, H02J7/34, H02J7/0013, H02M2001/0045, H02J7/0018, H02J7/0068, H02J7/02, H02J7/0057, H02J2007/0067European ClassificationH02J9/06B, H02J7/02, H02J7/00C1C, H02J7/00C6, H02J7/00L, H02J7/34, H02J7/00G3, H02J7/00CRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google