Source: http://www.google.com/patents/US5537601?dq=6011510
Timestamp: 2014-12-25 04:28:10
Document Index: 728199190

Matched Legal Cases: ['art) 14', 'art) 31', 'art 14', 'art 31', 'art 31', 'art 14']

Patent US5537601 - Programmable digital signal processor for performing a plurality of signal ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA digital signal processor for processing various types of signals, such as an image signal and an audio signal, a basic signal processing part, a programmable logic part, and a bus for connecting these parts together. Circuit configuration data is transferred to the programmable logic part from an external...http://www.google.com/patents/US5537601?utm_source=gb-gplus-sharePatent US5537601 - Programmable digital signal processor for performing a plurality of signal processingsAdvanced Patent SearchPublication numberUS5537601 APublication typeGrantApplication numberUS 08/272,749Publication dateJul 16, 1996Filing dateJul 11, 1994Priority dateJul 21, 1993Fee statusLapsedAlso published asEP0637173A2, EP0637173A3Publication number08272749, 272749, US 5537601 A, US 5537601A, US-A-5537601, US5537601 A, US5537601AInventorsJunichi Kimura, Yoshito Nejime, Kouji NoguchiOriginal AssigneeHitachi, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (6), Non-Patent Citations (26), Referenced by (180), Classifications (25), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetProgrammable digital signal processor for performing a plurality of signal processingsUS 5537601 AAbstract A digital signal processor for processing various types of signals, such as an image signal and an audio signal, a basic signal processing part, a programmable logic part, and a bus for connecting these parts together. Circuit configuration data is transferred to the programmable logic part from an external memory through a data input/output line and the bus under control of the basic signal processing part. The circuit configuration data corresponds to the types of signal processing that is to be performed, and several different types of signal processings can be performed successively.
We claim: 1. A digital signal processor chip for performing a plurality of signal processings of audio and video input signal data in a data processing system having memory means and providing processed output data, comprising:said chip being connected to said system; a first processor part and a second progammable logic part each connected for input and output of data with said system, said second part having programmable logic that is selectively programmed by configuring said programmable logic with circuit configuration data of at least one of a plurality of predetermined logic programs that correspond with a respective one of said signal processings; an internal processor bus for connecting the first and second parts; and said first part having control means receiving commands from said system for initiating said signal processings and in response for controlling transfer of said circuit configuration data of said plurality of predetermined logic programs from said memory means to the second part so that said circuit configuration data of said predetermined logic programs is successively transferred from said memory means to said second part each time a different one of said plurality of signal processings is commanded to be executed, and said control means controlling inputting of the audio and video input signal data to the second part for executing said respective signal processings following configuring of said programmable logic with said circuit configuration data of said respective logic programs, and further controlling outputting of said output data from said second part to said system. 2. The digital signal processor chip according to claim 1, wherein said programmable logic includes a plurality of arithmetic cells that perform signal processing including receiving said audio and video input signal data through input signal lines and outputting said output data through output signal lines, wherein said input and output lines are connected to buses arranged between the cells and to said processor bus, and wherein said buses are connected together through bus switches having switch connection states for setting the input/output state of each of said arithmetic cells.
FIELD OF THE INVENTION The present invention relates to a digital signal processor, and particularly to a digital signal processor for executing digital signal processing such as analyzing, coding, and synthesizing various types of video and audio signals in a multimedia terminal.
BACKGROUND OF THE INVENTION Since a digital signal processor (DSP) has a multiplier accumulator, filter processing, frequency conversion, and matrix operation can be easily performed by software. To process image signals, however, there are too many picture elements to be processed. For example, in the case of digital TV signal processing, it is necessary to process signals at a rate of 20M picture elements per second. Therefore, because the required high-speed processing rate cannot be achieved only by the software processing using the DSP, it is necessary to use an exclusive circuit in addition to the DSP. To reduce the circuit scale, as described in "A Video Digital Signal Processor with a Vector-Pipeline Architecture, 1992 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS, pp. 72-73 (1992.2) by TOYOKURA, et. al." exclusive circuits are built in the DSP. The configuration of the DSP disclosed in the above document will be briefly described below referring to FIG. 1.
SUMMARY OF THE INVENTION FIG. 1 shows a conventional video digital signal processor (VDSP) for video CODEC systems that includes exclusive circuits. The VDSP 1 includes a basic signal processing part (core part) 14 having an arithmetic and logic unit (ALU), registers (REG), an accumulator (ACC) and other exclusive circuits, such as a DCT, spatial filter, etc.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an illustration of a conventional digital signal processor;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is described below by reference to the embodiment shown in FIG. 3. The embodiment of FIG. 3 provides the same signal processing functions as those performed by the VDSP 1 of FIG. 1. The DSP 30 is connected to a host signal processing system such as a multi media terminal, computer, video conferencing system or similar machine, which requires various types of signal processing. In FIG. 3, a programmable logic part (PL part) 31 is provided that is not part of the VDSP of FIG. 1. In this embodiment, core part 14 controls the set up and configuration of PL part 31 in response to commands received from a host system, not shown. Circuit configuration data is transferred, for example, from the data input/output line 32, which is connected to an external storage device, to the PL part 31 through the bus 18. Exchange control of the data between the core part 14 and the PL part is performed through the bus 18. The PL part has a control line 22, a data line 33, and input and output lines 20, 19 for communication with an external unit. The bus 18 comprises a signal line for transmitting various types of data by means of time-sharing and a signal line dedicated to data, for example.
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EventsDateCodeEventDescriptionSep 14, 2004FPExpired due to failure to pay maintenance feeEffective date: 20040716Jul 16, 2004LAPSLapse for failure to pay maintenance feesFeb 4, 2004REMIMaintenance fee reminder mailedDec 30, 1999FPAYFee paymentYear of fee payment: 4Mar 11, 1996ASAssignmentOwner name: HITACHI, LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIMURA, JUNICHI;NEJIME, YOSHITO;NOGUCHI, KOUJI;REEL/FRAME:007856/0146Effective date: 19940629RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google