Source: http://www.google.com/patents/US8165427?dq=5636223
Timestamp: 2017-03-29 03:54:55
Document Index: 343000719

Matched Legal Cases: ['Application No. 2003', 'Application No. 2003', 'Application No. 2009', 'Application No. 2003', 'Application No. 2003', 'Application No. 2003']

Patent US8165427 - Data processing apparatus, image processing apparatus, and method therefor - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThere are provided a data processing apparatus which makes an I/F for data processing modules (processors) versatile to facilitate addition/modification on a data processing module basis in accordance with processing contents, an image processing apparatus, and a method for the apparatuses. A data processing...http://www.google.com/patents/US8165427?utm_source=gb-gplus-sharePatent US8165427 - Data processing apparatus, image processing apparatus, and method thereforAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8165427 B2Publication typeGrantApplication numberUS 13/019,122Publication dateApr 24, 2012Filing dateFeb 1, 2011Priority dateFeb 13, 2002Fee statusPaidAlso published asUS7266254, US7822296, US7889935, US7899275, US8867864, US9361664, US20030158608, US20070263945, US20090202161, US20090208139, US20110134443, US20120170871, US20140105521Publication number019122, 13019122, US 8165427 B2, US 8165427B2, US-B2-8165427, US8165427 B2, US8165427B2InventorsHisashi Ishikawa, Ryoko MiseOriginal AssigneeCanon Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (60), Non-Patent Citations (9), Classifications (11), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetData processing apparatus, image processing apparatus, and method therefor
US 8165427 B2Abstract
For example, as shown in FIG. 7, in two-dimensional addressing in which data are accessed on a data block basis, first of all, a start address As is loaded into the register 17. The sequencer 15 controls the selector 14 to select the address difference value D1. Since the selector 14 selects the address difference value D1, an output from the adder 16 becomes As+Al, thereby generating the next address. Upon reception of the acknowledgement signal ack, the register 17 outputs As+D1 as the next address. If the access count in the horizontal direction is represented by w, the address generator repeats the above operation (w−1) times. In the wth address generating operation, the sequencer 15 controls the selector 14 to select the address difference value D2. Therefore, the wth address becomes As+(w−1)·D1+D2, and first data P1,0 of the next line is accessed.
Furthermore, the present invention is characterized in that input image data is JPEG decoded data before rasterization, and a block used for image processing is a block (8×8 pixels or MCU) used when
JPEG decoding is performed. The present invention is characterized in that image data is MPEG decoded data before rasterization, and a block used for image processing is a block (8×8 pixels or MB) used when MPEG decoding is performed.
Resizing processing is performed for a block which is determined as valid in the clipping processing in step S82 (step S83). FIG. 32 is a flow chart for explaining in detail the resizing processing performed in step 583. First of all, in the resizing processor 321-2, it is checked whether resizing is to be done (step S101). If it is determined that no resizing is to be done (NO), the processing is terminated without performing resizing processing, and the input image data is transferred to the subsequent image processor without any change. If it is determined that resizing is to be done (YES), parameters are set for resizing (step S102). Resizing processing is performed in accordance with the set parameters, and sub-sampling processing, linear interpolation processing, and the like are performed to reduce the size of the image data to a desired size (step S103). Note that parameter setting step S102 may be omitted by performing resizing processing determination step S101 in accordance with the size after the resizing processing which is set in parameter setting step S81 in FIG. 30. If, for example, the horizontal size of a block of an input image is 8, and the horizontal size after resizing is less than 8, resizing is performed. In this case, if the horizontal size after resizing is a parameter for resizing, and is set to, for example, 4, an 8×8 pixel block is reduced to a 4×4 pixel block by resizing.
The intra-block rotating circuit 353 increments the internal write horizontal counter, vertical counter, and block counter in accordance with the input valid signal Resize_Valid. The intra-block rotating circuit 353 grasps a pixel position in a block through the vertical and horizontal counters, and grasps a block position through the block counter. In this embodiment, since the maximum block size is 8×8 pixels, both the horizontal and vertical counters are 3-bit counters. If the size is changed by the MCU reducing circuit 352, the horizontal and vertical counters become counters corresponding to the size. If the size after reduction is represented by W, a carry is generated when the counter is W-1, and the counter returns to 0 (base-W counter). Note that the vertical counter is incremented in accordance with a carry of the horizontal counter. Since the maximum number of Y blocks in an MCU is four, the block counter becomes a 2-bit counter and is incremented in accordance with the AND of a carry of the horizontal counter and a carry of the vertical counter.
In the case of the Y block buffer counters, in the 4:4:4 mode, both the horizontal and vertical counters operate as base-W up/down counters (three bits). In the 4:2:2 mode, the horizontal counter operates as a base-W up/down counter, and the vertical counter operates as a base-2 W up/down counter (0°, 180°) or a base-W up/down counter+1-bit block counter (90°, 270°). In the 4:2:0 mode, the horizontal counter operates as a base-W up/down counter, the vertical counter operates as a base-2 W up/down counter+1-bit block counter. The above counter configurations are switched by a carry (borrow) generating method. Note that the initial value in down count operation is W-1 (base-W) or 2 W-1 (base-2 W).
(1) In sampling mode=4:4:4 (common to Y, Cr, and Cb) for 0°: Yr, Xr
for 180°: !Yr, !Xr for 270°: Xr, !Yr
for 270°: Xcr′[3..1], !Ycr′
Assume that “,” indicates bit coupling, and “!”
for 180°: !Br, !Yr[2..1], !Yr[0], !Xr[1..0]
for 180°: !Xr<and !Yr<W
In this embodiment, since data can be identified on an 8×8 pixel basis in read operation, clipping can be done on an 8×8 pixel basis. In this case, clipping is performed in three stages, i.e., on an MCU basis, DCT block (8×8 pixel) basis, and pixel basis. Alternatively, clipping may be performed in two stages, i.e., on a DOT block (8×8 pixel) basis and pixel basis, by omitting clipping on an MCU basis.
z=My and m=Hm: 90° and 270° rotations In addition, letting As be the start address of the page buffer, each difference address and an initial value A(0) of an address are given as follows:
A(0)=As+(Wm−1)×Wx D1=−Wm×Wx×(Hm×Wy−1)−2Wx+1
A(0)=As+Wm×Wx×(Hm−1)×Wy+(Wm−1)×Wx D1=−Wm×Wx×(2Wy−1)+(Wm−2)×Wx+1
A(0)=As+Wm×Wx×(Hm−1)×Wy D1=Wm×Wx×((Hm−2)×Wy+1)+1
In the case shown in FIG. 34, for example, the original image is reduced to 101×151 MCU image by the MCU clipping circuit 351. The MCU reducing circuit 352 then reduces a 16×8 pixel MCU into a 6×3 pixel MCU. The intra-block rotating circuit 353 rotates the image through 90° and outputs the resultant image data. Therefore, the MCU size after MCU reduction/rotation becomes 3×6. That is, Wx=3, Wy=6, Wm=151, and Hm=101. If the start address of the page buffer is set to As=0, A(0)=450, D1=−274070, and Dm=Db=451. The horizontal counter x in an MCU is a base-3 counter, and the vertical counter y in the MCU counts up in accordance with a carry of this counter. The vertical counter y in the MCU is a base-6 counter, and an MCU counter My counts up in accordance with a carry of this counter. The MCU counter My is a base-101 counter, which counts up from 0 to 100 and returns to 0. Note that no horizontal MCD counter is required.
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