Source: https://patents.google.com/patent/US7900104
Timestamp: 2018-06-25 01:20:49
Document Index: 165435915

Matched Legal Cases: ['Application No. 04', 'Application No. 00', 'Application No. 00', 'Application No. 04', 'Application No. 04', 'Application No. 00', 'Application No. 04', 'Application No. 2001', 'Application No. 2001', 'Application No. 00']

US7900104B2 - Test pattern compression for an integrated circuit test environment - Google Patents
Test pattern compression for an integrated circuit test environment Download PDF
US7900104B2
US7900104B2 US12405409 US40540909A US7900104B2 US 7900104 B2 US7900104 B2 US 7900104B2 US 12405409 US12405409 US 12405409 US 40540909 A US40540909 A US 40540909A US 7900104 B2 US7900104 B2 US 7900104B2
US12405409
US20090259900A1 (en )
a1 ⊕ a2 ⊕ a4 ⊕ a6 ⊕ a2 ⊕ a4 ⊕ a6 ⊕ a1 ⊕ a2 ⊕ a2 ⊕ a8 ⊕ a6 ⊕ a4 ⊕ a5 ⊕ a2 ⊕ a3 ⊕
a10 a8 a13 a4 ⊕ a10 ⊕ a9 a7 a14 a12
a2 ⊕ a4 ⊕ a6 ⊕ a8 a2 ⊕ a4 ⊕ a8 ⊕ a11 a2 ⊕ a4 ⊕ a5 ⊕ a6 ⊕ a7 ⊕ a1 ⊕ a6 ⊕ a7 ⊕ a10
a8 ⊕ a9
a1 ⊕ a2 ⊕ a4 ⊕ a6 ⊕ a1 ⊕ a2 ⊕ a4 ⊕ a6 ⊕ a1 ⊕ a4 ⊕ a6 ⊕ a7 ⊕ a8 ⊕ a9 ⊕ a3 ⊕ a8 ⊕ a9 ⊕ a12
a8 ⊕ a10 a10 ⊕ a13 a10 ⊕ a11
a5 ⊕ a6 ⊕ a7 ⊕ a9 ⊕ a10 ⊕ a11 ⊕ a12 ⊕ a13 ⊕ a15 ⊕ a18 ⊕ a19 ⊕ a20 ⊕ a21 ⊕
a23 ⊕ a24 = 1
a0 ⊕ a1 ⊕ a3 ⊕ a4 ⊕ a5 ⊕ a6 ⊕ a7 ⊕ a9 ⊕ a12 ⊕ a13 ⊕ a14 ⊕ a15 ⊕ a17 ⊕
a18 = 0
It can be verified that the resulting input variables a2, a3, a6 and a12 are equal to the value of one while the remaining variables assume the value of zero. This seed will subsequently produce a fully specified test pattern in the following form (the initial specified position are now underlined) shown in Table 9:
21. The computer-readable medium of claim 12, wherein the method further includes generating symbolic expressions that are associated with scan cells in the integrated circuit, wherein generating symbolic expressions includes using a mathematical representation of a decompressor.
US12405409 1999-11-23 2009-03-17 Test pattern compression for an integrated circuit test environment Active 2020-07-28 US7900104B2 (en)
US20090259900A1 true US20090259900A1 (en) 2009-10-15
US7900104B2 true US7900104B2 (en) 2011-03-01
DE602006010031D1 (en) * 2006-05-04 2009-12-10 St Microelectronics Srl Adaptive scan compression architecture
WO2010124148A1 (en) * 2009-04-22 2010-10-28 Mentor Graphics Corporation At-speed scan testing with controlled switching activity
US7996741B2 (en) 2009-08-24 2011-08-09 Syntest Technologies, Inc. Method and apparatus for low-pin-count scan compression
US20180045781A1 (en) * 2016-04-28 2018-02-15 Innotio Inc. Apparatus, method, and system for testing ic chip
EP1475643A1 (en) 1999-11-23 2004-11-10 Mentor Graphics Corporation Test pattern compression for an integrated circuit test environment
US7610540B2 (en) * 2005-10-03 2009-10-27 Nec Laboratories America, Inc. Method for generating, from a test cube set, a generator configured to generate a test pattern
EP1236111B1 (en) 1999-11-23 2005-02-09 Mentor Graphics Corporation Test pattern compression for an integrated circuit test environment
JP3920640B2 (en) 1999-11-23 2007-05-30 メンター・グラフィクス・コーポレーション Test pattern compression method for an integrated circuit test environment
Bardell et al., "Pseudorandom arrays for built-in tests," IEEE Trans. on Computers, vol. C-35, No. 6, pp. 653-658 (1986).
European Communication dated Apr. 26, 2005, from European Application No. 04 01 7880.
European Communication dated Dec. 22, 2003, from European Application No. 00 97 8684.
European Communication under Rule 51(4) EPC dated Aug. 17, 2004, from European Application No. 00 97 8684.
European Communication under Rule 51(4) EPC dated Feb. 27, 2006, from European Application No. 04 01 7880.
European Decision to Grant dated Aug. 24, 2006, from European Application No. 04 01 7880.
European Decision to Grant dated Dec. 30, 2004, from European Application No. 00 97 8684.
European Search Report dated Sep. 8, 2004, from European Application No. 04 01 7880.
International Preliminary Examination Report from International Application No. PCT/US00/31377.
International Search Report from International Application No. PCT/US00/31377.
Japanese Office Action dated May 26, 2005, including an English-language translation, from Japanese Patent Application No. 2001-540467.
Japanese Office Action dated Sep. 20, 2006, including an English-language translation, from Japanese Patent Application No. 2001-540467.
Supplementary European Search Report dated Jul. 24, 2003, from European Application No. 00 97 8684.
US20030131298A1 (en) 2003-07-10 application
Barnhart et al. 2001 OPMISR: The foundation for compressed ATPG vectors
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RAJSKI, JANUSZ;KASSAB, MARK;MUKHERJEE, NILANJAN;AND OTHERS;REEL/FRAME:022942/0366;SIGNING DATES FROM 20000720 TO 20000928
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RAJSKI, JANUSZ;KASSAB, MARK;MUKHERJEE, NILANJAN;AND OTHERS;SIGNING DATES FROM 20000720 TO 20000928;REEL/FRAME:022942/0366