Source: http://www.google.com/patents/US7209997?dq=6,073,142
Timestamp: 2014-10-20 11:01:56
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Matched Legal Cases: ['Application No. 00108822', 'Application No. 91908374', 'Application No. 91908374', 'Application No. 91908374', 'Application No. 00', 'Application No. 00', 'Application No. 00', 'Application No. 89', 'Application No. 91', 'Application No. 00010832', 'Application No. 00010832', 'Application No. 0010822', 'Application No. 0010822']

Patent US7209997 - Controller device and method for operating same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA controller device and method for operating same is disclosed. In one particular exemplary embodiment, the controller device may comprise output driver circuitry and input receiver circuitry. The output driver circuitry may output a value, a first operation code, a block size value, and second operation...http://www.google.com/patents/US7209997?utm_source=gb-gplus-sharePatent US7209997 - Controller device and method for operating sameAdvanced Patent SearchPublication numberUS7209997 B2Publication typeGrantApplication numberUS 10/716,596Publication dateApr 24, 2007Filing dateNov 20, 2003Priority dateApr 18, 1990Fee statusPaidAlso published asUS6684285, US6715020, US6728819, US6751696, US6807598, US20010023466, US20020087777, US20020099896, US20020147877, US20030005208, US20060039213Publication number10716596, 716596, US 7209997 B2, US 7209997B2, US-B2-7209997, US7209997 B2, US7209997B2InventorsMichael Farmwald, Mark HorowitzOriginal AssigneeRambus Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (99), Non-Patent Citations (99), Referenced by (2), Classifications (80), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetController device and method for operating sameUS 7209997 B2Abstract A controller device and method for operating same is disclosed. In one particular exemplary embodiment, the controller device may comprise output driver circuitry and input receiver circuitry. The output driver circuitry may output a value, a first operation code, a block size value, and second operation code. The first operation code may represent an instruction to a memory device to store the value in a register in the memory device. The block size value may indicate an amount of read data to be output by the memory device in response to the second operation code. The second operation code may represent an instruction to the memory device to perform a read operation. The input receiver circuitry may sample a first portion of the read data output by the memory device after a read delay following the outputting of the second operation code.
CROSS-REFERENCE OF THE RELATED APPLICATIONS This patent application is a continuation of U.S. patent application Ser. No. 10/037,171, filed Dec. 21, 2001, now U.S. Pat. No. 6,715,020 which is a continuation of U.S. patent application Ser. No. 09/835,263, filed Apr. 13, 2001, now U.S. Pat. No. 6,751,696 which is a continuation of U.S. patent applicatuin Ser. No. 09/545,648, filed Apr. 10, 2000 (now U.S. Pat. No. 6,378,020); which is a continuation of U.S. patent application Ser. No. 09/161,090, filed Sep. 25, 1998 (now U.S. Pat. No. 6,049,846); which is a division of U.S. patent application Ser. No. 08/798,520, filed Feb. 10, 1997 (now U.S. Pat. No. 5,841,580); which is a division of U.S. patent application Ser. No. 08/448,657, filed May 24, 1995 (now U.S. Pat. No. 5,638,334); which is a division of U.S. patent application Ser. No. 08/822,646, filed Mar. 31, 1994 (now U.S. Pat. No. 5,513,327); which is a continuation of U.S. patent application Ser. No. 07/954,945, filed Sep. 30, 1992 (now U.S. Pat. No. 5,319,755); which is a continuation of U.S. patent application Ser. No. 07/510,898, filed Apr. 18, 1990 (now abandoned).
In U.S. Pat. No. 4,315,308 (Jackson), a bus connecting a single CPU to a bus interface unit is described The invention uses multiplexed address, data, and control information over a single 16-bit wide bus. Block-mode operations are defined, with the length of the block sent as part of the control sequence. In addition, variable access-time operations using a �stretch� cycle signal are provided. There are no multiple processing elements and no capability for multiple outstanding requests, and again, not all of the interface signals are bused
High bus bandwidth is achieved by running the bus at a very high clock rate (hundreds of MHz). This high clock rate is made possible by the constrained environment of the bus. The bus lines are controlled-impedance, doubly-terminated lines. For a data rate of 500 MHz, the maximum bus propagation time is less than 1 ns (the physical bus length is about 10 cm). In addition, because of the packaging used, the pitch of the pins can be very close to the pitch of the pads. The loading on the bus resulting from the individual devices is very small. In a preferred implementation, this generally allows stub capacitances of 1�2 pF and inductances of 0.5�2 nH. Each device 15, 16, 17, shown in FIG. 3, only has pins on one side and these pins connect directly to the bus 18. A transceiver device 19 can be included to interface multiple units to a higher order bus through pins 20.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram which illustrates the basic 2-D organization of memory devices:
DETAILED DESCRIPTION The present invention is designed to provide a high speed, multiplexed bus for communication between processing devices and memory devices and to provide devices adapted for use in the bus system. The invention can also be used to connect processing devices and other devices, such as I/O interfaces or disk controllers, with or without memory devices on the bus. The bus consists of a relatively small number of lines connected in parallel to each device on the bus. The bus carries substantially all address, data and control information needed by devices for communication with other devices on the bus. In many systems using the present invention, the bus carries almost every signal between every device in the entire system. There is no need for separate device-select lines since device-select information for each device on the bus is carried over the bus. There is no need for separate address and data lines because address and data information can be sent over the same lines Using the organization described herein, very large addresses (40 bits in the preferred implementation) and large data blocks (1024 bytes) can be sent over a small number of bus lines (8 plus one control line in the preferred implementation).
Another unique aspect of this invention is that each memory device is a complete, independent memory subsystem with all the functionality of a prior art memory board in a conventional backplane bus computer system. Individual memory devices may contain a single memory section or may be subdivided into more than one discrete memory section. Memory devices preferably include memory address registers for each discrete memory section. A failed memory device (or even a subsection of a device) can be �mapped out� with only the loss of a small fraction of the memory, maintaining essentially full system capability. Mapping out bad devices can be accomplished in two ways, both compatible with this invention.
The preferred method uses address registers in each memory device (or independent discrete portion thereof) to store information which defines the range of bus addresses to which this memory device will respond. This is similar to prior art schemes used in memory boards in conventional backplane bus systems. The address registers can include a single pointer, usually pointing to a block of known size, a pointer and a fixed or variable block size value or two pointers, one pointing to the beginning and one to the end (or to the �top� and �bottom�) of each memory block. By appropriate settings of the address registers, a series of functional memory devices or discrete memory sections can be made to respond to a contiguous range of addresses, giving the system access to a contiguous block of good memory, limited primarily by the number of good devices connected to the bus. A block of memory in a first memory device or memory section can be assigned a certain range of addresses, then a block of memory in a next memory device or memory section can be assigned addresses starting with an address one higher (or lower, depending on the memory structure) than the last address of the, previous block.
In a preferred implementation of this invention shown in FIG. 4, a request packet 22 contains 6 bytes of data�4.5 address bytes and 1.5 control bytes. Each request packet uses all nine bits of the multiplexed data/address lines (AddrValid 23+BusData[0:7] 24) for all six bytes of the request packet. setting 23 AddrValid=1 in an otherwise unused ven cycle indicates the start of an request packet (control information). In a valid request packet, AddrValid 27 must be 0 in the last byte. Asserting this signal in the last byte invalidates the request packet. This is used for the collision detection and arbitration logic (described below). Bytes 25�26 contain the first 35 address bits, Address[0:35]. The last byte contains AddrValid 27 (the invalidation switch) and 28, the remaining address bits, Address[36:39], and BlockSize[0:3] (control information).
In page mode, the data stored in the DRAM sense amplifiers may be accessed within much less time than it takes to read out data in normal mode (�10�20 nS vs. 40�100 nS). This data may be kept available for long periods. However, if these sense amps (and hence bit lines) are not precharged after an access, a subsequent-access to a different memory word (row) will suffer a precharge time penalty of about 40�100 nS because the sense amps must precharge before latching in a new value.
The contents of the sense amps thus may be held and used as a cache, allowing faster, repetitive access to small blocks of data. DRAM-based page-mode caches have been attempted in the prior art using conventional DRAM organizations but they are not very effective because several chips are required per computer word. Such a conventional page-mode cache contains many bits (for example, 32 chips�4 Kbits) but has very few independent storage entries. In other words, at any giv n point in time the s nse amps hold only a few different blocks or memory �locales� (a single block of 4K words, in the example above). Simulations have shown that upwards of 100 blocks are required to achieve high hit rates (>90% of requests find the requested data already in cache memory) regardless of the size of each block. See, for example, Anant Agarwal, et. al, �An Analytic Cache Model,� ACM Transactions on Computer Systems, Vol. 7(2), pp 184�215 (May 1989).
The organization of memory in the present invention allows each DRAM to hold one or more (4 for 4MBit DRAMS) separately-addressed and independent blocks of data. A personal computer or workstation with 100 such DRAMs (i.e. 400 blocks or locales) can achieve extremely high, very repeatable hit rates (98�99% on average) as compared to the lower (50�80%), widely varying hit rates using DRAMS organized in the conventional fashion. Further, because of the time penalty associated with the deferred precharge on a �miss� of the page-mode cache, the conventional DRAM-based page-mode cache generally has been found to work less well than no cache at all.
AccessType[1:3] Use AccessTime 0 Control Register Fixed, 8[AccessReg0] Access 1 Unused Fixed, 8[AccessReg0] 2�3 Unused AccessReg1 4�5 Page Mode DRAM AccessReg2 access 6�7 Normal DRAM access AccessReg3 Persons skilled in the art will recognize that a series of available bits could be designated as switches for controlling these access modes. For example:
BlockSize[0:3] specifies the size of the data block transfer. If BlockSize[0] is 0, the remaining bits are the binary representation of the block size (0�7). If BlockSize[0] is 1, then the remaining bits give the block size as a binary power of 2, from 8 to 1024. A zero-length block can be interpreted as a special command, for example, to refresh a DRAM without returning any data, or to change the DRAM from page mode to normal access mode or vice-versa.
BlockSize[0:2] Number of Byt s in Block 0�7 0�7 respectively 8 8 9 16 10 32 11 64 12 128 13 256 14 512 15 1024 Persons skilled in the art will recognize that other block size encoding schemes or values can be used.
With two or more masters on the bus, masters will occasionally transmit independent request packets during the same bus cycle. Those multiple requests will collide as each such master drives the bus simultaneously with different information, resulting in scrambled request information and-neither desired data block transfer. In a preferred form of the invention, each device on the bus seeking to write a logical 1 on a BusData or AddrValid line drives that line with a current sufficient to sustain a voltage greater than or equal to the high-logic value for the system. Devices do not drive lines that should have a logical 0; those lines are simply held at a voltage corresponding to a low-logic value. Each master t sts the voltage on at least some, preferably all, bus data and the AddrValid lines so the master can detect a logical �1� where the expected level is �0� on a line that it does not drive during a given bus cycle but another master does drive.
Another way to detect collisions is to select one or more bus lines for collision signaling. Each master sending a request drives that line or lines and monitors the selected lines for more than the normal drive current (or a logical value of �>1�), indicating requests by more than one master. Persons skilled in the art will recognize that this can be implemented with a protocol involving BusData and AddrValid lines or could be implemented using an additional bus line.
FIG. 6 illustrates one preferred way of implementing this arbitration. Each colliding master signals its intent to send a request packet by driving a single BusData line during a single bus cycle corresponding to its assigned master number (1�15 in the present example). During two-byte arbitration cycle 29, byte 0 is allocated to requests 1�7 from masters 1�7, respectively, (bit 0 is not used) and byte 1 is allocat d to requests 8�15 from masters 8�15, respectively. At least one device and preferably each colliding master reads the values on the bus during the arbitration cycles to determine and store which masters desire to use the bus. Persons skilled in the art will recognize that a single byte can be allocated for arbitration requests if the system includes more bus lines than masters. More than 15 masters can be accommodated by using additional bus cycles.
To reset all devices on a bus, a master sets the R setIn line of the first device to a �1� for long enough to ensure that all devices on the bus have been reset (4 cycles times the number of devices�note that the maximum number of devices on the preferred bus configuration is 256 (8 bits), so that 1024 cycles is always enough time to reset all devices.) Then ResetIn is dropped to �0� and the BusData lines are driven with the first followed by successive device ID numbers, changing after every 4 clock pulses. Successive devices set those device ID numbers into the corresponding device ID register as the falling edge of ResetIn propagates through the shift registers of the daisy-chained devices. FIG. 14 shows ResetIn at a first device going low while a master drives a first device ID onto the bus data lines BusData[0:3]. The first device then latches in that first device ID. After four clock cycles, the master changes BusData[0:3] to the next device ID number and ResetOut at the first device goes low, which pulls ResetIn for the next daisy-chained device low, allowing the next device to latch in the next device ID number from BusData[0:3]. In the preferred embodiment, one master is assigned device ID 0 and it is the r sponsibility of that master to control the ResetIn line and to drive successive device ID numbers onto the bus at the appropriate times. In the preferred embodiment, each device waits two clock cycles after ResetIn goes low before latching in a device ID number from BusData[0:3].
The configuration master should choose and set an access time in each access-time register 173 in each slave to a period sufficiently along to allow the slave to perform an actual, desired memory access. For example, for a normal DRAM access, this time must be longer than the row address strobe (RAS) success time. If this condition is not met, the slave may not deliver the correct data. The value stored in a slave access-time register 173 is preferably one-half the number of bus cycles for which the slave device should wait before using the bus in response to a request. Thus an access time value of �1� would indicate that the slave should not access the bus until at least two cycles after the last byte of the request packet has been received. The value of AccessReg0 is preferably fixed at 8 (cycles) to facilitate access to control registers.
Error detection and correction (�ECC�) methods well known in the art can be implemented in this system. ECC information typically is calculated for a block of data at the time that block of data is first written into memory. The data block usually has an integral binary size, e g. 256 bits, and the ECC information uses significantly fewer bits. A potential problem arises in that each binary data block in prior art schemes typically is stored with the ECC bits appended, resulting in a block size that is not an integral binary power.
Since this system is quite flexible, the system designer can choose the size of the data blocks and the number of ECC bits using the memory devices of this invention. Note that the data stream on the bus can be interpreted in various ways. For instance the sequence can be 2n data bytes followed by 2m ECC bytes (or vice versa), or the sequence can be 2k iterations of 8 data bytes plus 1 ECC byte. Other information, such as information used by a directory-based cache coherence scheme, can also be managed this way. See, for example, Anant Agarwal, et al., �Scaleable Directory Schemes for Cache Consistency,� 15th International Symposium on Computer Architecture, June 1988, pp. 280�289. Those skilled in the art will recognize alternative methods of implementing ECC schemes that are within the teachings of this invention.
The use of a low pin count and an edge-connected bus permits a simple 3-D package, whereby the devices are stacked and the bus is connected along a single edge of the stack. The fact that all of the signals are bused is important for the implementation of a simple 3-D structure. Without this, the complexity of the �backplane� would be too difficult to make cost effectively with current technology. The individual devices in a stack of the present invention can be packed quite tightly because of the low power dissipated by the entire memory system, permitting the devices to be stacked bumper-to-bumper or top to bottom. Conventional plastic-injection molded small outline (SO) packages can be used with a pitch of about 2.5 mm (100 mils), but the ultimate limit would be the device die thickn ss, which is about an order of magnitude smaller, 0.2�0.5 mm using current wafer technology.
Clock distribution problems can be further reduced by using a bus clock and device clock rate equal to the bus cycle data rate divided by two, that is, the bus clock period is twice the bus cycle period. Thus a 500 MHz bus preferably uses a 250 MHz clock rate. This reduction in frequency provides two benefits. First it makes all signals on the bus have the same worst case data rates�data on a 500 MHz bus can only change every 2 ns. Second, clocking at half the bus cycle data rate makes the labeling of the odd and even bus cycles trivial, for example, by defining even cycles to be those when the internal d vice clock is 0 and odd cycles when the internal device clock is 1.
Persons skilled in the art will recognize that a more sophisticated transceiver can control transmissions to and from primary bus units. An additional control line, TrncvrRW can be bused to all devices on the transceiver bus, using that line in conjunction with the AddrValid line to indicate to all devices on the transceiv r bus that the information on the data lines is: 1) a request packet, 2) valid data to a slave, 3) valid data from a slave, or 4) invalid data (or idle bus). Using this extra control line obviates the need for the transceivers to keep track of when data needs to be forwarded from its primary bus to the transceiver bus�all transceivers send all data from their primary bus to the transceiver bus whenever the control signal indicates condition 2) above. In a preferred implementation of this invention, if AddrValid and TrncvrRW are both low, there is no bus activity and the transceivers should remain in an idle state. A controller sending a request packet will drive AddrValid high, indicating to all devices on the transceiver bus that a request packet is being sent which each transceiver should forward to its primary bus unit. Each controller seeking to write to a slave should drive both AddrValid and TrncvrRW high, indicating valid data for a slave is present on the data lines. Each transceiver device will then transmit all data from the transceiver bus lines to each primary bus unit. Any controller expecting to receive information from a slave should also drive the TrncvrRW line high, but not drive AddrValid, thereby indicating to each transceiver to transmit any data coming from any slave on its primary local bus to the transceiver bus. A still more sophisticated transceiver would recognize signals addressed to or coming from its primary bus unit and transmit signals only at requested times.
The output drivers are quite simple, and consist of a single NMOS pulldown transistor 76. This transistor is sized so that under worst case conditions it can still sink the 50 mA required by the bus. For 0.8 micron CMOS t chnology, the transistor will need to be about 200 microns long. Overall bus performance can be improved by using feedback techniques to control output transistor current so that the current through the d vice is roughly 50 mA under all operating conditions, although this is not absolutely necessary for proper bus operation. An example of one of many methods known to persons skilled in the art for using feedback techniques to control current is described in Hans Schumacher, et. al., �CMOS Subnanosecond True-ECL Output Buffer,� J. Solid State Circuits, Vol. 25 (1), pp. 150�154 (February 1990). Controlling this current improves performance and reduces power dissipation. This output driver which can be operated at 500 MHz, can in turn be controlled by a suitable multiplexer with two or more (preferably four) inputs connected to other internal chip circuitry, all of which can be designed according to well known prior art.
In the preferred embodiment, two sets of these delay lines are used, one to generate the true value of the internal device clock 73, and the other to generate the complement 74 without adding any inverter delay. The dual circuit allows generation of truly complementary clocks, with extremely small skew. The complement internal device clock is used to clock the �even� input receivers to sample at time 127, while the true internal device clock is used to clock the �odd� input receivers to sample at time 125. The true and complement internal device clocks 73 and 74, respectively, are also used to select which data is driven to the output drivers. The gate delay between the internal device clock and output circuits driving the bus is slightly greatly than the output circuits driving the bus is slightly greater than the corresponding delay for the input circuits, which means that the new data always will be driven on the bus slightly after the old data has been sampled.
A block diagram of a conventional 4 MBit DRAM 130 is shown in FIG. 15. The DRAM memory array is divided into a number of subarrays 150�157, for example, 8. Each subarray is divided into arrays 148, 149 of memory cells. Row address selection is performed by decoders 146. A column decoder 147A, 147B, including column sense amps on either side of the decoder, runs through the core of each subarray. These column sense amps can be set to precharge or latch the most-recently stored value, as described in detail above. Internal I/O lines connect each set of sense-amps, as gated by corresponding column decoders, to input and output circuitry connected ultimately to the device pins. These internal I/O lines are used to drive the data from the selected bit lines to the data pins (some of pins 131�145), or to take the data from the pins and write the selected bit lines. Such a column access path organized by prior art constraints does not have sufficient bandwidth to interface with a high speed bus. The method of this invention does not require changing the overall method used for column access, but does change implementation details. Many of these details have been implemented selectively in certain fast memory devices, but n ver in conjunction with th bus architecture of this invention.
Running the internal I/O lines in the conventional way at high bus cycle rates is not possible. In the preferred method, several (preferably 4) bytes are read or written during each cycle and the column access path is modified to run at lower rate (the inverse of the number of bytes accessed per cycle, preferably � of the bus cycle rate). Three different techniques are used to provide the additional internal I/O lines required and to supply data to memory cells at this rate. First, the number of I/O bit lines in each subarray running through the column decoder 147A and 147B is increased, for example, to 16, eight for each of the two columns of column sense amps and the column decoder selects one set of columns from the �top� half 148 of subarray 150 and one set of columns from the �bottom� half 149 during each cycle, where the column decoder selects one column sense amp per I/O bit line. Second, each column I/O line is divided into two halves, carrying data independently over separate internal I/O lines from the left half 147A and right half 147B of each subarray (dividing each subarray into quadrants) and the column decoder selects sense amps from each right and left half of the subarray, doubling the number of bits available at each cycle. Thus each column decode selection turns on n column sense amps, where n equals four (top left and right, bottom left and right quadrants) times the number of I/O lines in the bus to each subarray quadrant (8 lines each�4=32 lines in the preferred implementation). Finally, during each RAS cycle, two different subarrays, e.g. 157 and 153, are accessed. This doubles again the available number of I/O lines containing data. Taken together, these changes increase the internal I/O bandwidth by at least a factor of 8. Four internal buses are used to route these internal I/O lines. Increasing the number of I/O lines and then splitting them in the middle greatly reduces the capacitance of each internal I/O line which in turn reduces the column access time, increasing the column access bandwidth even further.
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Amitai, "New System Archtitectures for DRAM Control and Error Correction", Monolithic Memories Inc., Electro/87 and Mini/Mico Northeast: Focusing on the OEM Conference Record, pp. 1132, 4/31-3, (Apr. 1987).Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8254205Jun 29, 2009Aug 28, 2012Hynix Semiconductor Inc.Circuit and method for shifting addressUS8461782Aug 27, 2009Jun 11, 2013Allegro Microsystems, LlcLinear or rotational motor driver identificationClassifications U.S. Classification710/305, 365/189.17, 365/194International ClassificationG11C11/4076, G11C11/4096, G11C5/06, G11C5/00, G11C8/00, G11C7/10, G06F12/06, G06F11/10, G06F13/16, G06F13/376, G11C29/00, G06F11/00, G11C7/22, G06F12/02, G06F13/00Cooperative ClassificationG06F13/1605, G11C8/00, G06F11/1048, G06F13/1678, G11C7/222, G06F13/1694, G11C5/04, G11C29/88, G06F11/006, G11C7/1069, G11C7/1066, G11C2207/105, G06F13/1689, G11C7/1045, G11C11/4096, G11C8/12, G11C7/1006, G11C7/1012, G11C7/1057, G11C7/109, G11C11/4076, G06F13/376, G11C7/1051, G06F12/0661, G11C7/1078, G11C7/22, G11C2207/108, G11C7/225, G06F12/0684, G11C5/066, G11C7/1072, G06F12/0215, G06F13/161European ClassificationG11C5/06M, G11C8/12, G06F12/06K2D, G11C8/00, G11C7/10L, G11C11/4096, G11C7/10M7, G06F12/02C, G06F12/06K6, G06F13/16A, G11C7/10R, G11C11/4076, G06F13/16D9, G06F13/16D8, G11C7/10S, G06F13/16A2, G06F13/376, G11C5/04, G06F13/16D4, G11C29/88, G11C7/10R7, G11C7/10L3, G11C7/10R2, G11C7/22A, G11C7/10W5, G11C7/10R9, G11C7/22B, G11C7/10W, G11C7/22Legal EventsDateCodeEventDescriptionMay 22, 2012B2Reexamination certificate second reexaminationFree format text: THE PATENTABILITY OF CLAIMS 1-38 IS CONFIRMED.Oct 25, 2010FPAYFee paymentYear of fee payment: 4Oct 12, 2010B1Reexamination certificate first reexaminationFree format text: THE PATENTABILITY OF CLAIMS 1-38 IS CONFIRMED.Jul 28, 2009RRRequest for reexamination filedEffective date: 20090515Jul 14, 2009RRRequest for reexamination filedEffective date: 20090515RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google