Source: https://patents.google.com/patent/JP3839323B2/en
Timestamp: 2020-02-22 20:23:00
Document Index: 758395836

Matched Legal Cases: ['art 8', 'art 12', 'art\n8', 'art\n8', 'art\n12', 'art)\n12', 'art)\n13']

JP3839323B2 - Manufacturing method of semiconductor device - Google Patents
JP3839323B2
JP3839323B2 JP2002012775A JP2002012775A JP3839323B2 JP 3839323 B2 JP3839323 B2 JP 3839323B2 JP 2002012775 A JP2002012775 A JP 2002012775A JP 2002012775 A JP2002012775 A JP 2002012775A JP 3839323 B2 JP3839323 B2 JP 3839323B2
JP2002012775A
JP2002368190A (en
JP2002368190A5 (en
2001-04-06 Priority to JP2001-108603 priority Critical
2001-04-06 Priority to JP2001108603 priority
2002-01-22 Application filed by 株式会社ルネサステクノロジ, 株式会社ルネサス北日本セミコンダクタ filed Critical 株式会社ルネサステクノロジ
2002-01-22 Priority to JP2002012775A priority patent/JP3839323B2/en
2002-12-20 Publication of JP2002368190A5 publication Critical patent/JP2002368190A5/ja
2002-12-20 Publication of JP2002368190A publication Critical patent/JP2002368190A/en
2006-11-01 Publication of JP3839323B2 publication Critical patent/JP3839323B2/en
239000004065 semiconductor Substances 0 abstract 15
A semiconductor device having a stack structure comprises: a single-piece substrate having a chip support surface serving as a main surface, a back surface, a plurality of connection terminals provided on the chip support surface and a plurality of solder balls provided on the back surface; a first semiconductor chip having a main surface, aback surface, a plurality of semiconductor devices on the main surface of the first semiconductor chip and a plurality of pads provided on the main surface of the first semiconductor chip; a second semiconductor chip having a main surface, a back surface, a plurality of semiconductor devices provided on the main surface of the second semiconductor chip and a plurality of pads provided on the main surface of the second semiconductor chip; and a resin sealing body formed on the chip support surface of the single-piece substrate and used for sealing the first semiconductor chip and the second semiconductor chip; and a plurality of wires for connecting the pads of the second semiconductor chip to the respective connection terminals provided on the single-piece substrate. In the stack structure, the second semiconductor chip is made thinner than the first semiconductor chip. As a result, the structure package of the semiconductor device can be made thin.
The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique effective when applied to miniaturization of a semiconductor device having a stack structure.
In a semiconductor device (semiconductor package) having a semiconductor chip on which a semiconductor element is formed, a stack structure is known as an example of a structure in which a plurality of semiconductor chips are contained in one package.
In a semiconductor device having a stack structure, for example, semiconductor chips are stacked in two stages, and this is resin molded to form a package.
For example, Japanese Patent Application Laid-Open Nos. 2000-188369, 2000-299431, and 11-219984 describe the semiconductor device having a stack structure and the manufacturing method thereof. As disclosed in Japanese Patent Laid-Open No. 2000-188369, in a structure in which another chip is stacked and mounted on a chip which is mounted face-up and connected by wire bonding, the upper chip is the lower chip. It is necessary to have a shape that does not cover the electrodes, and the chip size is greatly limited.
In comparison, as disclosed in JP 2000-299431 A and JP 11-219984 A, the lower semiconductor chip is flip-chip connected by face-down mounting, and the upper semiconductor chip is the face. In the structure in which wire bonding is connected by up-mounting, there is no restriction on the chip size as described above, and the structure is more flexible.
Among them, Japanese Patent Application Laid-Open No. 2000-299431 describes a technique for improving the wire bonding property of an upper semiconductor chip in a semiconductor device having a structure in which a part of the upper semiconductor chip protrudes.
Japanese Patent Laid-Open No. 11-219984 describes a semiconductor device package having a chip laminated structure and capable of being mounted on a thick film wiring substrate by SMT (Surface Mount Technology) and a method for manufacturing the same. Yes.
However, when a semiconductor device having a stack structure is mounted on a portable device such as a cellular phone, it is required to make the semiconductor device smaller and thinner. However, when pursuing further thinning of the semiconductor device, a new problem of lowering the chip strength has occurred.
In order to improve productivity, it is desirable to employ a transfer molding method as means for resin-sealing a semiconductor chip mounted on a wiring board. However, when adopting the transfer mold method for the chip laminated structure, another new problem of void generation has occurred.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a stack structure which is intended to be thin. Set It is to provide a manufacturing method.
Another object of the present invention is to provide a semiconductor device having a stack structure that reduces the restriction on the chip size. Set It is to provide a manufacturing method.
Furthermore, another object of the present invention is to provide a semiconductor device having a stack structure that prevents void generation and chip cracking during resin sealing. Set It is to provide a manufacturing method.
That is, the present invention includes a step of preparing a wiring board having a plurality of electrodes on the main surface, a main surface and a back surface, and a plurality of the plurality of electrodes on the main surface. Protrusion A step of preparing a first semiconductor chip having an electrode and a plurality of semiconductor elements; a main surface and a back surface; a plurality of electrodes and a plurality of semiconductor elements on the main surface; A step of preparing a second semiconductor chip thinner than one semiconductor chip, a main surface of the first semiconductor chip facing a main surface of the wiring substrate, and a plurality of the first semiconductor chips Protrusion The first semiconductor chip is placed on the main surface of the wiring board so that the electrodes face the plurality of electrodes of the wiring board. Through the first adhesive After the step of arranging and the step of arranging the first semiconductor chip, a pressure is applied to the back surface of the first semiconductor chip, and a plurality of the first semiconductor chips are arranged. Protrusion Electrical connection between electrodes and multiple electrodes on the wiring board And bonding the first semiconductor chip to the wiring board by the first adhesive material. And electrically connecting And bonding the first semiconductor chip After the step, the second semiconductor chip is placed on the back surface of the first semiconductor chip, and the back surface of the first semiconductor chip and the back surface of the second semiconductor chip are Second To face each other through adhesive Place and Apply a pressure smaller than the pressure applied during the electrical connection process Adhering the second semiconductor chip to the back surface of the first semiconductor chip by the second adhesive material A step of electrically connecting a plurality of electrodes of the second semiconductor chip and a plurality of electrodes of the wiring board via a plurality of wires, the first and second semiconductor chips, and the plurality of the plurality of electrodes. Forming a resin sealing body for sealing the wire.
Furthermore, the outline of other inventions of the present application is briefly shown in sections. That is,
1. A cavity having first and second side surfaces facing each other, a third and fourth side surfaces in contact with the first and second side surfaces and facing each other, and a resin injection formed on the first side surface A step of preparing a mold having an inlet; a wiring board having a main surface; a first semiconductor chip fixed on the main surface of the wiring board; a second fixed on the first semiconductor chip; A step of preparing a semiconductor chip, a step of disposing the wiring substrate and the first and second semiconductor chips inside the cavity, and after disposing the first and second semiconductor chips, from the resin injection port And a step of sealing the first and second semiconductor chips by injecting resin. In the step of arranging the first and second semiconductor chips, In the cross section parallel to the third side surface of the first and second semiconductor chips, the length of the first semiconductor chip is longer than the length of the second semiconductor chip. Is to arrange.
2. A first and second side surface facing each other, a cavity in contact with the first and second side surfaces and having third and fourth side surfaces facing each other, and a plurality of cavities formed on the first side surface A step of preparing a mold having a resin inlet, a wiring board having a main surface and having a plurality of device regions formed thereon, a first semiconductor chip fixed to each of the plurality of device regions of the wiring substrate, Preparing a second semiconductor chip fixed on the first semiconductor chip; and arranging the wiring board, the plurality of first and second semiconductor chips inside the cavity, and the plurality of device regions. A plurality of devices corresponding to the respective device regions after the step of collectively covering the device regions with the cavities and the step of collectively covering the plurality of device regions with the cavities. A method of manufacturing a semiconductor device including a step of injecting resin from a resin injection port and sealing the plurality of first and second semiconductor chips in a lump. In the covering step, in the cross section parallel to the third side surface of the cavity, the length of each of the first semiconductor chips is longer than the length of the second semiconductor chip stacked on the first semiconductor chip. The wiring board and the plurality of first and second semiconductor chips are arranged so as to be long.
Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other or all of the modifications, details, supplementary explanations, and the like are related.
1 is a cross-sectional view showing an example of the structure of a semiconductor device (stacked structure CSP) according to a first embodiment of the present invention, FIG. 2 is a partial cross-sectional view showing the structure of the CSP shown in FIG. 1, and FIG. FIG. 4 is a partial cross-sectional view showing an example of a state of attaching a die bond film to a wafer in the CSP assembly shown in FIG. 4, FIG. 4 is a partial cross-sectional view showing an example of wafer dicing in the CSP assembly shown in FIG. 1, and FIG. FIG. 6 is a partial cross-sectional view showing an example of the assembly of FIG. 1. (a) is a diagram showing the first chip mount, (b) is a diagram showing the first chip thermocompression bonding, and FIG. 6 is an example of the assembly of the CSP shown in FIG. It is a fragmentary sectional view shown, (a) is a figure showing the 2nd chip mount, and (b) is a figure showing the 2nd chip wire bonding.
The semiconductor device according to the first embodiment shown in FIGS. 1 and 2 has a stack structure in which two semiconductor chips are stacked on an individual substrate 3 (wiring substrate), and also supports the chip of the individual substrate 3. The first semiconductor chip 1 and the second semiconductor chip 2 laminated thereon are sealed with a resin mold on the surface 3a (main surface) side.
Further, the semiconductor device is a semiconductor package having a size equal to or slightly larger than the chip size. That is, the semiconductor device is a CSP 9 having a stack structure.
A plurality of solder balls 11 which are external terminals and projecting electrodes are provided in a matrix arrangement on the surface opposite to the chip support surface 3a of the individual substrate 3 (hereinafter referred to as the back surface 3b).
Note that the CSP 9 of the first embodiment is a large number of wiring boards on which a plurality of device regions 7a (for example, 3 × 13 = 39 matrix arrangement) as shown in FIG. 13 are formed. The substrate 7 is used for resin molding in a state of collectively covering a plurality of device regions 7a defined by the dicing lines 7b (hereinafter referred to as collective molding), and FIG. 27B formed thereby. The collective mold part 8 shown is diced after molding and separated into pieces.
The detailed structure of the CSP 9 will be described. It has a chip support surface 3a and a back surface 3b which are main surfaces, and has a plurality of connection terminals 3c (electrodes) as shown in FIG. 8 on the chip support surface 3a. An individual substrate 3 having a plurality of solder balls 11 on the back surface 3b, a main surface 1b and a back surface 1c, and a plurality of pads 1a (electrodes) and a plurality of semiconductor elements on the main surface 1b. The first semiconductor chip 1 has a main surface 2b and a back surface 2c, and has a plurality of pads 2a (electrodes) and a plurality of semiconductor elements on the main surface 2b. The second semiconductor chip 2 having a small thickness and the resin sealing body which is formed on the chip support surface 3a of the individual substrate 3 and seals the first semiconductor chip 1 and the second semiconductor chip 2 6 and the second semiconductor chip Consisting of the pad 2a and a plurality of wires 4 for connecting the connection terminals 3c of the individual substrate 3 corresponding thereto.
Further, the first semiconductor chip 1 is arranged such that the plurality of pads 1 a of the first semiconductor chip 1 are opposed to the connection terminals 3 c of the individual substrate 3 on the chip support surface 3 a of the individual substrate 3. The main surface 1b of the semiconductor chip 1 and the chip support surface 3a of the individual substrate 3 are arranged to face each other.
At this time, the main surface 1b of the first semiconductor chip 1 and the chip support surface 3a of the individual substrate 3 are fixed via an adhesive such as a thin-film NCF (Non-Conductive Film) 12 or the like. Has been.
However, as the adhesive, an ACF (Anisotropic Conductive Film) other than NCF 12 or the like may be used, or other adhesive may be used.
Here, NCF 12 or ACF is an adhesive mainly used for flip chip connection, and is a tape-like film formed of a thermosetting resin mainly composed of an epoxy resin.
The plurality of pads 1a of the first semiconductor chip 1 are in pressure contact with the plurality of connection terminals 3c of the individual substrate 3 corresponding thereto.
At that time, the gold bump 1d, which is a protruding electrode provided on the pad 1a of the first semiconductor chip 1, and the connection terminal 3c of the individual substrate 3 are pressed against each other.
The gold bump 1d is a protruding electrode provided on the electrode of the semiconductor chip using a wire bonding technique using a gold wire. In assembling the CSP 9, the pad 1a of the first semiconductor chip 1 is previously provided. Keep it.
On the other hand, the second semiconductor chip 2 is disposed on the chip support surface 3a of the individual substrate 3 via the first semiconductor chip 1, and the first semiconductor chip 1 and the second semiconductor chip 2 are The back surfaces 1c and 2c face each other through the die bond film material 5 (adhesive material) and are disposed on the chip support surface 3a of the individual substrate 3.
That is, the CSP 9 has a stack structure in which the first semiconductor chip 1 on the lower layer side is flip-chip connected to the individual substrate 3 by face-down mounting, while the second semiconductor chip 2 on the upper layer side is The semiconductor chip 1 is face-up mounted on the back surface 1c of the semiconductor chip 1 and connected by wire bonding. At this time, as shown in FIG. 2, the thickness (t 2 ) Is the thickness of the first semiconductor chip 1 on the lower layer side (t 1 ) Thinner (t 1 ≧ t 2 ).
For example, t 1 = 240 μm, t 2 = 180 μm, etc. However, it is not limited to these numerical values.
Here, description will be given of making the thickness of the second semiconductor chip 2, which is a feature of the CSP 9 of the first embodiment, thinner than the thickness of the first semiconductor chip 1.
For example, a semiconductor element used in a portable device such as a cellular phone is required to have a low mounting height. Therefore, it is necessary to use a semiconductor chip that has been processed thinly. Many semiconductor chips used in thin semiconductor elements in recent years have been processed to a thickness of 200 μm or less.
Generally, the ease of cracking with respect to the load of a semiconductor chip becomes more prominent as the thickness of the semiconductor chip is thinner. Therefore, in the CSP 9 of the first embodiment, the first semiconductor chip 1 to which a large load is applied is made thicker, and the second semiconductor chip 2 is made thinner than the first semiconductor chip 1.
For example, the load when thermocompression bonding the first semiconductor chip 1 is 10 to 20 kgf, and the load when thermocompression bonding the second semiconductor chip 2 is 1 kgf.
Thus, there are the following reasons for making the load for thermocompression bonding the first semiconductor chip 1 larger than the load for thermocompression bonding the second semiconductor chip 2.
In the mounting process of the first semiconductor chip 1, as shown in FIG. 5B, the gold bump 1 d is pressed against the connection terminal 3 c on the wiring substrate 3 (individual substrate) by pressure from the thermocompression bonding head 20. In this state, heat is applied to cure the thermosetting resin and secure the connection between the gold bump 1d and the connection terminal 3c. At this time, even when the height of the gold bump 1d varies, in order to ensure the connection between the gold bump 1d and the connection terminal 3c, the gold bump 1d and the connection by the pressure applied from the thermocompression bonding head 20 are ensured. It is effective to elastically or plastically deform the terminal board 3c or the wiring board 3 under the connection terminal 3c.
Thus, in order to ensure the connection reliability of the first semiconductor chip 1 connected to the connection terminal 3c on the wiring substrate 3 via the gold bump 1d, a large pressure bonding force is required, and the first semiconductor The chip 1 needs to have a strength sufficient to withstand such a pressing force, that is, a thickness of the chip.
In comparison with this, by reducing the pressure applied when the second semiconductor chip 2 mounted face up and connected to the connection terminal 3c via the wire 4 is disposed on the first semiconductor chip 1, Even if the semiconductor chip 2 is thinned, chip cracking can be prevented.
As a result, both the first semiconductor chip 1 and the second semiconductor chip 2 are not broken by the mounting load, and the connection reliability with the connection terminal 3c is not lowered, and the CSP 9 can be made thinner. As a result, a desired mounting height can be realized.
Further, the first semiconductor chip 1 on the lower layer side is flip-chip connected by face-down mounting, so that the size in the planar direction of the second semiconductor chip 2 stacked on the back surface 1c of the first semiconductor chip 1 is increased. It is possible to make the semiconductor chip 1 smaller or larger than one semiconductor chip 1, and the chip size restriction can be greatly reduced.
Thereby, in the stack structure, the degree of freedom of combination of chip sizes is widened, and a small multi-chip module can be realized.
In the CSP 9, the bus frequency of the first semiconductor chip 1 is higher than the bus frequency of the second semiconductor chip 2.
At this time, the first semiconductor chip 1 is a logic chip, and the second semiconductor chip 2 is a memory chip.
This is because the logic chip, which is the first semiconductor chip 1, is mounted face down on the lower layer side and connected to the connection terminal 3c of the individual substrate 3 via the gold bump 1d, thereby suppressing the inductance of the input / output unit. Because it can.
As a result, it is possible to increase the bus frequency while suppressing noise on the output signal, and to bring out the performance of the logic chip to a sufficient value required by the system.
Compared to the logic chip, the memory chip as the second semiconductor chip 2 can sufficiently exhibit the required performance even in a range in which the amount of time change of current is limited in order to suppress the generation of noise. In addition, the CSP 9 can be downsized by stacking the logic chip (first semiconductor chip 1) and the memory chip (second semiconductor chip 2).
As shown in FIG. 15, the first semiconductor chip 1 and the second semiconductor chip 2 are made of, for example, silicon, and a semiconductor integrated circuit is formed on each of the main surfaces 1b and 2b. A plurality of pads 1a and 2a, which are connection electrodes, are formed on the peripheral portions of the main surfaces 1b and 2b.
The resin for molding used for forming the resin sealing body 6 is, for example, a thermosetting epoxy resin.
Further, the individual substrate 3 is, for example, an epoxy substrate with glass.
The individual substrate 3 is formed with a plurality of connection terminals 3c for connecting the wires 4 and the gold bumps 1d on the chip support surface 3a, and a solder ball 11 is mounted on the back surface 3b. A plurality of bump lands 3d as shown in FIG. 14B are exposed.
Moreover, the wire 4 connected by wire bonding is a gold wire, for example.
Further, a plurality of solder balls 3 which are external terminals electrically connected to the connection terminals 3 c of the individual substrate 3 are provided in a matrix arrangement on the back surface 3 b of the individual substrate 3.
Next, an outline of a method for manufacturing the CSP 9 of the first embodiment will be described.
Here, in the CSP9 manufacturing process, the semiconductor chip forming process shown in FIGS. 3 and 4, the first semiconductor chip mounting process shown in FIG. 5A, and the first semiconductor shown in FIG. The chip thermocompression bonding process, the second semiconductor chip mounting process shown in FIG. 6A, and the wire bonding process shown in FIG. 6B will be described.
First, an individual substrate 3 (wiring substrate) having a plurality of connection terminals 3c on a chip support surface 3a is prepared.
Further, a first semiconductor chip 1 and a second semiconductor chip 2 are prepared.
That is, a first semiconductor chip having a main surface 1b and a back surface 1c and having a plurality of pads 1a and a plurality of semiconductor elements on the main surface 1b, and similarly having a main surface 2b and a back surface 2c, and A second semiconductor chip 2 having a plurality of pads 2 a and a plurality of semiconductor elements on the main surface 2 b and being thinner than the first semiconductor chip 1 is prepared.
At that time, for the second semiconductor chip 2 to be stacked on the first semiconductor chip 1, as shown in FIG. 3, the die bond film material 5 is pasted on the back surface 17b of the semiconductor wafer 17 in advance. Thereafter, the second semiconductor chip 2 is obtained by dividing into pieces by dicing.
First, after the back surface 17b opposite to the main surface (circuit surface) 17a of the semiconductor wafer 17 for forming the second semiconductor chip 2 is ground to a desired thickness by back grinding, a die bond film material made of epoxy resin or the like is used. 5 is attached to the entire back surface 17 b of the semiconductor wafer 17.
That is, the semiconductor wafer 17 with the main surface 17a facing down is placed on the stage 18 heated to 120 ° C. At that time, 120 ° C. is a temperature at which the die bond film material 5 does not cure and the die bond film material 5 easily adheres to the semiconductor wafer 17.
Thereafter, the die-bonding film material 5 is placed on the back surface 17b of the semiconductor wafer 17, and the roller 14 is rolled on the semiconductor wafer 17 from above the die-bonding film material 5 and stuck while extruding bubbles.
Subsequently, the die bond film material 5 protruding from the semiconductor wafer 17 is cut off, and the protective sheet 15 attached to the die bond film material 5 is peeled off.
Thereafter, as shown in FIG. 4, the semiconductor wafer 17 to which the die bond film material 5 is attached is attached to a dicing tape 16 that is a UV tape for dicing supported by a fixing ring 19.
Thereafter, dicing is performed using the dicing blade 10 to cut the semiconductor wafer 17 (divide into pieces), thereby obtaining the second semiconductor chip 2.
At that time, the dicing blade 10 is cut to a depth at which the dicing blade 10 completely cuts the die bond film material 5. This is because in the next die bonding step, if the die bond film material 5 is not cut, when the semiconductor chip is peeled from the dicing tape 16, only the semiconductor chip is pushed up and the die bond film material 5 is peeled off from the semiconductor chip. It is for preventing it.
As described above, the die bond film material 5 is applied to the entire back surface 17b of the semiconductor wafer 17 and then diced to obtain the individual second semiconductor chips 2, whereby the individual semiconductor chips are later formed. Compared with the case where the die-bonding film material 5 is stuck, workability | operativity improves and cost reduction can be aimed at.
Thereafter, the first semiconductor chip 1 shown in FIG. 5A is mounted.
Each of the plurality of pads 1a of the first semiconductor chip 1 includes a pad 1a formed on the main surface 1b of the first semiconductor chip 1 and a gold bump 1d that is a protruding electrode disposed on the pad 1a. It is comprised by.
First, the main surface 1b of the first semiconductor chip 1 faces the chip support surface 3a of the individual substrate 3, and the plurality of pads 1a of the first semiconductor chip 1 are opposed to the plurality of connection terminals 3c of the individual substrate 3. Thus, the first semiconductor chip 1 is arranged on the chip support surface 3 a of the individual substrate 3.
Thereafter, pressure is applied to the back surface 1 c of the first semiconductor chip 1 to electrically connect the plurality of pads 1 a of the first semiconductor chip 1 and the plurality of connection terminals 3 c of the piece substrate 3.
At this time, first, as shown in FIG. 5A, an NCF 12 (adhesive material) cut slightly larger than the first semiconductor chip 1 in the first semiconductor chip 1 mounting area of the chip support surface 3a of the individual substrate 3 is used. Next, the first semiconductor chip 1 is positioned so that the pad 1a of the first semiconductor chip 1 faces the connection terminal 3c of the individual substrate 3, and the pad 1a and the corresponding connection terminal 3c are positioned to the first. The semiconductor chip 1 is placed on the chip support surface 3 a of the individual substrate 3, and then a very slight load of about 1 to 5 kgf is applied to the back surface 1 c of the first semiconductor chip 1.
As a result, the gold bump 1 d is applied to the NCF 12, and the first semiconductor chip 1 is temporarily fixed on the individual substrate 3.
Thereafter, as shown in FIG. 5B, pressure is applied to the back surface 1 c of the first semiconductor chip 1 by the thermocompression bonding head 20. Also, heat is applied from the thermocompression bonding head 20 simultaneously with the pressure.
Thereby, the thermosetting resin of NCF 12 is cured between the main surface 1b of the first semiconductor chip 1 and the chip support surface 3a of the individual substrate 3, and the first semiconductor chip is interposed via the thermosetting resin. 1 is fixed on the chip support surface 3 a of the individual substrate 3.
The thermocompression bonding head 20 has a pressure surface that is approximately the same size as the individual substrate 3.
In the thermocompression bonding, the individual substrate 3 is placed on the die bond stage 21 heated to about 70 ° C., and the back surface 1 c of the first semiconductor chip 1 is pressed by the thermocompression bonding head 20 heated to about 300 ° C. The pressure load at this time is about 50 to 100 gf per bump of the first semiconductor chip 1. For example, if the CSP 9 has 200 bumps, a load of about 10 to 20 kgf is applied to the first semiconductor chip 1 by the thermocompression bonding head 20.
As a result, the NCF 12 reaches a temperature of around 200 ° C. and melts and hardens, whereby the gold bumps 1d on the pads 1a of the first semiconductor chip 1 and the connection terminals 3c of the individual substrate 3 come into contact with each other. Conducted to.
At this time, although not shown in detail in detail, the gold bump 1d, the connection terminal 3c, or the wiring board 3 under the connection terminal 3c is elastically or plastically deformed by a pressure load from the thermocompression bonding head 20. In order to cure the thermosetting resin, when the height of the gold bump 1d varies, or due to heat generated during the operation of the first semiconductor chip 1 or the second semiconductor chip 2, the thermosetting resin has thermally expanded. Even in this case, the connection reliability between the gold bump 1d and the connection terminal 3c can be sufficiently ensured.
Note that when the flip chip connection of the first semiconductor chip 1 is performed by, for example, gold-gold connection, that is, when the surface of the connection terminal 3c of the individual substrate 3 is plated with gold, the NCF 12 Without using a film-like adhesive such as ACF or ACF, the first semiconductor chip 1 and the individual substrate 3 are connected to each other by applying an ultrasonic wave to the first semiconductor chip 1 simultaneously with pressure and by ultrasonic gold-gold connection. It is also possible to connect.
In that case, in order to protect the main surface 1 b of the first semiconductor chip 1, to ensure connection reliability, and to prevent chip cracking during molding, between the individual substrate 3 and the first semiconductor chip 1 after chip connection. Underfill sealing is performed by pouring an insulating resin.
Next, the second semiconductor chip 2 shown in FIG. 6A is mounted.
At that time, the second semiconductor chip 2 formed to be thinner than the first semiconductor chip 1 on the back surface 1c of the first semiconductor chip 1 is replaced with the back surface 1c of the first semiconductor chip 1 and the second semiconductor chip 1. While arrange | positioning so that the back surface 2c of the semiconductor chip 2 may face through the die-bonding film material 5, the pressure (when CSP9 is 200 bumps) at the time of the die-bonding of the 1st semiconductor chip 1 with a crimping head (room temperature) (Load of about 10 to 20 kgf) is placed while applying a smaller pressure.
That is, since the die-bonding film material 5 is previously attached to the back surface 2c of the second semiconductor chip 2, the die-bonding is applied to the back surface 1c of the first semiconductor chip 1 that is flip-chip connected by heat and a small load. The second semiconductor chip 2 is fixed by using the film material 5 as an adhesive. At this time, heating for curing the die bond film material 5 is performed by the die bond stage 21, and the temperature of the pressure bonding head is lower than the temperature of the die bond stage 21.
The load (pressure) at that time is, for example, 50 mm when the size of the main surface 2b of the second semiconductor chip 2 of the CSP 9 is 50 mm. 2 In the case of the degree, it is about 1 kgf and the temperature is about 160 ° C.
Thereafter, as shown in FIG. 6B, a plurality of pads 2a of the second semiconductor chip 2 and a plurality of connection terminals 3c of the individual substrate 3 corresponding to each of the pads 2a are connected via wire 4 of gold wire by wire bonding. Connect them electrically.
Subsequently, the first semiconductor chip 1, the second semiconductor chip 2, and the plurality of wires 4 are sealed with resin.
That is, on the chip support surface 3 a side of the individual substrate 3, the first semiconductor chip 1, the second semiconductor chip 2, and the plurality of wires 4 are resin-sealed by transfer molding to form the resin sealing body 6.
After that, on the back surface 3 b of the individual substrate 3, the solder balls 11 that are a plurality of protruding electrodes that are electrically connected to the plurality of connection terminals 3 c of the individual substrate 3 are mounted.
That is, the solder balls 11 are mounted on each bump land 3d exposed on the back surface 3b opposite to the side where the resin sealing body 6 of the individual substrate 3 is formed by reflow or the like to form the external electrode of the CSP 9.
7 is a partial sectional view showing an example of the structure of the semiconductor device (CSP having a stack structure) according to the second embodiment of the present invention, and FIG. 8 is an enlarged plan view showing an example of a wiring state in the assembly of the CSP shown in FIG. 9 is a partial cross-sectional view showing an example of the assembly of the CSP shown in FIG. 7. FIG. 9A is a view showing the first chip mount, FIG. 9B is a view showing the first chip thermocompression bonding, and FIG. 2A is a partial cross-sectional view showing an example of assembly of the CSP shown in FIG. 2A, FIG. 2A is a view showing a second chip mount, and FIG. 2B is a view showing second chip wire bonding.
FIG. 11 is a manufacturing process flow chart showing an example of all the steps in the assembly procedure of the semiconductor device according to the second embodiment of the present invention. FIG. 12 shows the detailed steps in the assembly procedure of the semiconductor device according to the second embodiment of the present invention. FIG. 13 is a plan view showing an example of the structure of a multi-chip substrate in assembling the semiconductor device according to the second embodiment of the present invention. FIG. 14 is a plan view of the multi-chip substrate shown in FIG. FIG. 15 is an enlarged partial view showing the part in an enlarged manner, (a) is a plan view showing details of part A in FIG. 13, (b) is a bottom view on the back side of (a), and FIG. FIG. 6 is a plan view of first and second semiconductor chips used for assembling the semiconductor device of the second embodiment, (a) is a diagram of the first semiconductor chip, (b) is a diagram of the second semiconductor chip, FIG. 16 shows the first semiconductor chip shown in FIG. FIG. 17A is an enlarged partial side view, FIG. 17B is an enlarged partial plan view, and FIG. 17 is a first NCF pasting in the assembly of the semiconductor device according to the second embodiment of the present invention. 18 is a plan view showing an example of the process, FIG. 18 is a plan view showing the details of the first NCF attaching step shown in FIG. 17, (a) is a view before NCF placement, and (b) is a view after attaching NCF. FIGS. 19A and 19B are diagrams showing the arrangement state of the first semiconductor chip with respect to the first NCF pasting shown in FIG. 17, FIG. 19A is a diagram of the first semiconductor chip arrangement state, and FIG. FIG. 20 is a diagram showing an example of a die bonding method for a first semiconductor chip, FIG. 20A is a diagram showing a first semiconductor chip mounting state, and FIG. 20B is a diagram showing a first semiconductor chip thermocompression bonding. Later figure, Fig.21 shows the first NCF pasting shown in Fig.17 FIG. 22 is a plan view showing an example of the structure after die bonding of the first semiconductor chip, FIG. 22 is a plan view showing an example of the structure after the second NCF is attached to the first NCF attachment shown in FIG. FIG. 23 is a diagram showing a mounting completion structure of the first and third semiconductor chips with respect to the second NCF pasting shown in FIG. 22, (a) is a plan view, and (b) is a part B of FIG. 24 is an enlarged partial plan view showing details, FIG. 24 is a plan view showing an example of a structure after die bonding of the second and fourth semiconductor chips to the second NCF bonding shown in FIG. 22, and FIG. 25 is the second and fourth structures. It is a figure which shows the structure after wire bonding of the semiconductor chip of (a), (a) is a top view, (b) is an enlarged partial top view which shows the detail of the C section of (a), FIG. It is a plan view showing an example of the wire bonding state of the chip, (A) is a view before wire bonding, (b) is a view after wire bonding, FIG. 27 is a plan view showing an example of the structure of a multi-chip substrate on which batch molding is performed, and (a) is before batch molding. FIG. 28B is a view after batch molding, FIG. 28 is a plan view showing an example of the resin inflow direction in the batch molding method for assembling the semiconductor device according to the second embodiment of the present invention, and FIG. 29 is FIG. It is a figure which shows an example of a lump molding method, (a) is the fragmentary sectional view at the time of lump molding of the cross section along the DD line of FIG. 28, (b) is the cross section along the EE line of FIG. FIG. 30 is a plan view showing an example of the resin inflow direction in the batch molding method of the modified example of the batch molding method shown in FIG. 28, and FIG. 31 is the batch molding method of the modified example shown in FIG. Is a diagram showing 30A is a partial cross-sectional view of the cross section taken along the line FF in FIG. 30 at the time of batch molding, FIG. 30B is a partial cross-sectional view of the cross section taken along the line GG of FIG. FIG. 33 is a plan view showing an example of the structure of a multi-chip substrate after batch molding in the assembly of the semiconductor device according to the second embodiment of the present invention; FIG. 33 is a first NCF for assembling the semiconductor device according to the second embodiment of the present invention; FIG. 34 is a cross-sectional view showing the structure of a CSP of a modification to the CSP having the stack structure shown in FIG. 1.
In the second embodiment, characteristic parts in the assembly of the CSP 9 described in the first embodiment or the CSP 22 described in the second embodiment will be described.
The CSP 22 of the second embodiment has a stack structure, and, like the CSP 9 of the first embodiment, the first semiconductor chip 1 on the lower layer side is flip-chip connected by face-down mounting, and the first semiconductor The second semiconductor chip 2 stacked on the chip 1 is connected by wire bonding by face-up mounting, and the second semiconductor chip 2 is thinner than the first semiconductor chip 1, The difference from the first embodiment is that, as shown in FIG. 7, at least two opposite sides of the second semiconductor chip 2 protrude from the outer periphery of the first semiconductor chip 1 in a planar manner (over). Hang).
That is, the NCF 12 (ACF is the same) shown in FIG. 9A is once melted and becomes liquid when thermocompression bonding.
Thereafter, as shown in FIG. 9B, when a load of about 10 to 20 kgf is applied to the back surface 1c of the first semiconductor chip 1 by the thermocompression bonding head 20, the NCF 12 below the first semiconductor chip 1 is pushed out. Thus, it protrudes from the end of the first semiconductor chip 1.
Thereafter, the NCF 12 is cured to a desired thickness. At this time, the amount protruding from the end of the first semiconductor chip 1 is a remainder obtained by subtracting the thickness after pressure bonding from the initial thickness of the NCF 12. The protruding NCF 12 crawls up along the side surface of the first semiconductor chip 1 and reaches the back surface 1 c of the first semiconductor chip 1.
Therefore, by making the thermocompression bonding head 20 larger than the size of the first semiconductor chip 1, as shown in FIG. 9B, the NCF 12 has the same height as the back surface 1c of the first semiconductor chip 1. The flat part 12a can be formed in the protruding part.
The length of the flat portion 12a can be adjusted by changing the initial thickness of the NCF 12.
Thereafter, as shown in FIG. 10A, the second semiconductor chip 2 is mounted on the back surface 1 c of the first semiconductor chip 1 to mount the second semiconductor chip 2.
Further, after mounting the second semiconductor chip 2, wire bonding is performed to connect the pads 2 a of the second semiconductor chip 2 and the connection terminals 3 c of the individual substrate 3 with the wires 4 as shown in FIG. Connect electrically.
Note that the mounting method and wire bonding method of the second semiconductor chip 2 are the same as the mounting method and wire bonding method of the second semiconductor chip 2 described in the first embodiment.
The assembly of the CSP 22 will be described with reference to the manufacturing process flowchart shown in FIG.
Note that the manufacturing process flow chart shown in FIG. 12 shows the manufacturing process flow chart of FIG. 11 in more detail.
First, as shown in FIG. 14A, a plurality of first connection terminals 3e (first electrodes) and a plurality of second connection terminals 3f (second electrodes) formed on the chip support surface 3a and the chip support surface 3a. A multi-chip substrate 7 which is a wiring substrate shown in FIG. 13 having electrodes) is prepared.
Here, the electrode connected to the first semiconductor chip 1 in one device region 7a of the multi-chip substrate 7 and the device region 7a in the staggered arrangement is defined as a first connection terminal 3e, and the other adjacent to the device region 7a. An electrode connected to the third semiconductor chip in the device region 7a of the staggered arrangement is referred to as a second connection terminal 3f.
Note that the third semiconductor chip 26 shown in FIG. 23 in the second embodiment has the same structure as the first semiconductor chip 1 and is disposed on the lower layer side.
Further, bump lands 3d as shown in FIG. 14 (b) are exposed in a matrix arrangement on the back surface 3b side of the device region 7a to be the individual substrates 3 shown in FIG. 14 (a).
Subsequently, a plurality of first semiconductor chips 1 shown in FIG. 15A having a main surface 1b and a plurality of gold bumps 1d formed on the pad 1a on the main surface 1b and a plurality of semiconductor elements, and A plurality of second semiconductor chips 2 shown in FIG. 15B each having a main surface 2b and a plurality of pads 2a formed on the main surface 2b and a plurality of semiconductor elements are prepared.
As for the preparation of the first semiconductor chip 1 and the second semiconductor chip 2, as shown in FIG. 11, in the first semiconductor chip 1, back grinding in step S21, dicing in step S22, and curing in step S23. The preparation and the gold (Au) bump formation in step S24 are carried out by the method described in the first embodiment and prepared as shown in FIGS. 16 (a) and 16 (b). On the other hand, in the second semiconductor chip 2, The back grinding in step S31, the bonding of the die bond film in step S32, and the dicing in step S33 are performed by the method described in the first embodiment.
For the multi-chip substrate 7, first, after preparation, step NO. In the manufacturing process flow chart of FIG. The substrate baking shown in FIG.
Here, heat treatment is performed on the multi-piece substrate 7 at 100 ° C. or higher (for example, at 125 ° C. for a baking time of about 4 hours).
This is a process for removing moisture because an epoxy resin substrate easily absorbs moisture, so that when the first semiconductor chip 1 is thermocompression bonded, bubbles are formed in the multi-cavity substrate 7. While being able to prevent formation, the fall of the adhesiveness by moisture content can be prevented.
Therefore, after the baking process, the first semiconductor chip 1 is disposed on the chip support surface 3a of the multi-chip substrate 7 via an adhesive such as NCF 12, and then the adhesive is heat-treated and cured to be the first. This is a procedure for fixing a large number of semiconductor chips 1 on the substrate 7.
Next, the NCF is affixed as shown in step S1 of FIG.
Here, the first NCF 12b is used as the first adhesive, and the plurality of first connection terminals 3e shown in FIG. The first NCF 12b is disposed as shown in FIG.
The first NCF 12b has first and second portions that are separated from each other and are disposed on the device region 7a of the multi-chip substrate 7.
Here, as an example, as shown in FIG. 17, a plurality of first NCFs 12 b that are separated (the first and second portions) are arranged in a staggered arrangement.
Further, as shown in FIGS. 19A and 20A, on any one of the plurality of first NCFs 12b arranged in a staggered arrangement (for example, the first NCF 12b arranged at the corner). The first semiconductor chip 1 is disposed, and the first semiconductor chip 1 is fixed by thermocompression bonding. That is, the first semiconductor chip 1 is flip-chip mounted in step S2 shown in FIG. 11, and thermocompression bonding is further performed in step S3.
At the time of the thermocompression bonding, as shown in FIG. 19B, the first semiconductor chip 1 is formed on the die bonding stage 21 heated to about 70 ° C. by the thermocompression bonding head 20 heated to about 315 ° C. A heat is applied by applying a load from the back surface 1c.
As a result, as shown in FIGS. 19B and 20B, the first semiconductor chip 1 is fixed via the first NCF 12b, and a plurality of gold bumps 1d of the first semiconductor chip 1 are obtained. The first connection terminal 3 e in the device region 7 a of the substrate 7 is electrically connected, and the first NCF 12 b protrudes from the outer periphery of the first semiconductor chip 1.
Note that a range P surrounded by a dotted line shown in FIG. 19A indicates a range in which the substrate temperature rises to the extent that the thermosetting resin of the first NCF 12b is cured due to the influence of heat from the thermocompression bonding head 20. When arranging the plurality of first NCFs 12b in an arrangement such as a staggered arrangement, the adjacent first NCFs 12b must be arranged so as not to fall within the range P.
That is, the plurality of first NCFs 12b are arranged in an arrangement such as a staggered arrangement with intervals sufficient to avoid the influence of heat from the thermocompression bonding head 20.
As a result, due to the influence of heat from the thermocompression bonding head 20, it is possible to prevent thermosetting before the thermocompression bonding of the adjacent first NCF 12b, and to arrange a number of first NCFs 12b within a range that does not fall within the range P. After arranging the first semiconductor chip 1 on each of them, a plurality of first semiconductor chips 1 are continuously thermocompression bonded so that the mounting process of the first semiconductor chip 1 can be performed efficiently.
In this way, as shown in FIG. 21, the thermocompression bonding of the first semiconductor chip 1 is completed in a staggered arrangement.
Thereafter, among the device regions 7a of the multi-chip substrate 7, adjacent to the device region 7a in which the first semiconductor chips 1 are mounted and adjacent to the device region 7a in which the first semiconductor chips 1 are not mounted. The second NCF 12c (second adhesive) is disposed on the plurality of second connection terminals 3f in the region 7a.
That is, as shown in FIG. 22, a plurality of separated second NCFs 12c are arranged in a staggered arrangement next to each of the first semiconductor chips 1 in a staggered arrangement.
After that, as shown in FIG. 22, a plurality of third semiconductor chips 26 shown in FIG. 23 are mounted on the second NCFs 12c arranged in a staggered arrangement, and the third semiconductor chips 26 are thermocompression bonded by the same method as described above. Thermocompression bonding is performed by the head 20.
As a result, a plurality of third semiconductor chips 26 are fixed on the chip support surface 3a of the plurality of device regions 7a of the multi-piece substrate 7 via the second NCF 12c, and a plurality of third semiconductor chips 26 are provided. The gold bump 1d (see FIG. 16) is electrically connected to the plurality of second connection terminals 3f in the device region 7a of the multi-chip substrate 7 shown in FIG. 14 (a).
As a result, as shown in FIGS. 23A and 23B, mounting of the first semiconductor chip 1 and the third semiconductor chip 26, which are lower layer semiconductor chips mounted on the multi-chip substrate 7, is performed. Complete.
The first NCF 12b and the second NCF 12c are films formed of a thermosetting resin. Therefore, the thermosetting resin of the first NCF 12b and the second NCF 12c is thermoset by the load and heat applied by the thermocompression bonding head 20 and the die bond stage 21, thereby performing thermocompression bonding.
In the second embodiment, as shown in FIG. 17, first, a plurality of first NCFs 12b (in the case of the staggered arrangement described here, may be a plurality other than the staggered arrangement) are arranged. Furthermore, as shown in FIG. 21, after mounting the first semiconductor chip group including the plurality of first semiconductor chips 1 on the first NCF 12b, the remaining second NCF 12c is mounted as shown in FIG. As shown in FIG. 23, a second semiconductor chip group consisting of a plurality of third semiconductor chips 26 is mounted thereon, and a plurality of first semiconductor chips 1 and a plurality of third semiconductors are mounted thereon. The case where the mounting of the chip 26, that is, the lower semiconductor chip is completed has been described.
However, when the thermal influence on the adjacent device region 7a by the thermocompression bonding head 20 can be ignored, the arrangement of the NCFs 12 is first completed, and then the plurality of first semiconductor chips 1 and the plurality of first semiconductor chips 1 are collectively collected. In this case, it is not necessary to divide the NCF 12 into the first NCF 12b and the second NCF 12c, and the mounting of the first semiconductor chip 1 is also possible. Since it can be performed in one step, it is possible to efficiently mount the NCF 12 and the lower semiconductor chip.
Conversely, the thermal effect on the adjacent device region 7a by the thermocompression bonding head 20 is very large. For example, when even the thermal effect between the device regions 7a adjacent in the diagonal direction cannot be ignored, all the adjacent regions are adjacent. In order not to arrange the NCFs 12 in the device region 7a at the same time, the NCFs 12 may be arranged by a quarter of the total number, and the first semiconductor chip 1 may be mounted in four steps.
Next, the second semiconductor chip 2 shown in step S4 of FIG. 11 is mounted.
In the second embodiment, as shown in FIG. 24, the second semiconductor chip 2 is mounted after all the first semiconductor chips 1 are mounted.
However, the mounting method of each second semiconductor chip 2 is the same as the mounting method of the second semiconductor chip 2 described in the first embodiment.
That is, the second semiconductor chip 2 formed to be thinner than the first semiconductor chip 1 on the back surface 1c of the first semiconductor chip 1 is replaced with the back surface 1c of the first semiconductor chip 1 and the second semiconductor chip. The back surface 2c of the chip 2 is disposed so as to face the die bond film material 5 (see FIG. 6A), and the die bonding of the first semiconductor chip 1 is performed by the thermocompression bonding head 20 shown in FIG. It arrange | positions, applying the pressure smaller than the pressure applied in that case (when CSP22 is 200 bumps, a load of about 10-20 kgf).
As a result, the second semiconductor chip 2 is fixed to the back surface 1c of the first semiconductor chip 1 that is flip-chip connected by heat and load using the die bond film material 5 as an adhesive (see FIG. 26A).
With this method, the plurality of second semiconductor chips 2 and the plurality of fourth semiconductor chips 27 are sequentially thermocompression bonded, and the mounting of the second semiconductor chip 2 and the fourth semiconductor chip 27 is shown in FIG. Complete all as shown.
Here, the plurality of fourth semiconductor chips 27 have the same structure as the second semiconductor chip 2 and are respectively disposed on the plurality of third semiconductor chips 26.
Thereafter, the plurality of pads 2a of the second semiconductor chip 2 and the fourth semiconductor chip 27 shown in step S5 of FIG. 11 and the plurality of first connection terminals 3e of the individual substrate 3 which are the device regions 7a corresponding to the respective pads 2a. Alternatively, the second connection terminal 3f is electrically connected via a gold wire 4 by wire bonding (see FIGS. 25B and 26B).
As shown in FIG. 25A, the wire bonding is sequentially performed on the second semiconductor chip 2 to complete the wire bonding of the second semiconductor chip 2 including the fourth semiconductor chip 27. .
After that, resin sealing of the first semiconductor chip 1 (including the third semiconductor chip 26), the second semiconductor chip 2 (including the fourth semiconductor chip 27), and the plurality of wires 4 shown in Step S6 of FIG. Resin mold is performed.
Here, a case of a batch molding: MAP (Mold Array Package) method in which a plurality of device regions 7a on a multi-piece substrate 7 are covered with one cavity 13a and molded together, and then diced into individual pieces. explain.
First, in the molding step, as shown in FIGS. 29A and 29B, the first side surface 13b and the second side surface 13c facing each other, and the first side surface 13b and the second side surface 13c are in contact with each other. And a third side surface 13d and a fourth side surface 13e facing each other, and a cavity 13a having an upper surface 13j and a lower surface 13k adjacent to the first to fourth side surfaces 13e, and a first side surface 13b. A mold die 13 which is a die having a plurality of resin injection ports 13f is prepared.
That is, the mold 13 includes an upper mold 13h and a lower mold 13i, and has a cavity 13a having a first side surface 13b, a second side surface 13c, a third side surface 13d, a fourth side surface 13e, and an upper surface 13j. Is formed on the upper mold 13 h of the mold 13.
Further, an air hole 13g is formed in the upper mold 13h of the mold 13 as a vent hole on the second side surface 13c.
On the other hand, a multi-chip substrate 7 which is a wiring substrate on which a plurality of device regions 7a are formed, a first semiconductor chip 1 fixed to each of the plurality of device regions 7a of the multi-device substrate 7; A second semiconductor chip 2 fixed on the semiconductor chip 1 is prepared.
That is, as shown in FIG. 27A, a multi-chip substrate 7 after wire bonding is prepared.
A plurality of gold-plated portions 7c are formed at one end in the longitudinal direction of the multi-piece substrate 7 (the side corresponding to the resin injection port 13f of the mold 13). This is for facilitating peeling of the resin gate portion 8a formed by molding from the multi-piece substrate 7 shown in FIG.
After that, as shown in FIG. 29A, the multi-chip substrate 7, the plurality of first semiconductor chips 1 and the second semiconductor chips 2 are arranged in the lower mold 13i inside the cavity 13a, and FIG. ), The plurality of device regions 7a are collectively covered with the cavities 13a of the upper mold 13h.
In the cavity 13a, in the cross section parallel to the third side surface 13d of the cavity 13a (the cross section in FIG. 29A), the length of each first semiconductor chip 1 is the first semiconductor chip. A plurality of first semiconductor chips 1 and a plurality of second semiconductor chips 2 are arranged so as to be longer than the length of the second semiconductor chip 2 stacked in one.
On the other hand, in the cross section in which the 90 ° direction is changed, that is, in the cross section parallel to the first side surface 13b of the cavity 13a (refer to FIG. 29B), the length of the first semiconductor chip 1 is the second. The first semiconductor chip 1 and the second semiconductor chip 2 are arranged so as to be shorter than the length of the semiconductor chip 2.
That is, the relationship between the first semiconductor chip 1 and the second semiconductor chip 2 is that the length of the first semiconductor chip 1 is greater than the length of the second semiconductor chip 2 with respect to the resin inflow direction shown in FIG. The relationship should be long.
At this time, the length of the first semiconductor chip 1 is shorter than the length of the second semiconductor chip 2 in a direction perpendicular to the resin inflow direction.
In this state, the upper mold 13h and the lower mold 13i are clamped, and then a resin (resin) is injected from a plurality of resin injection ports 13f corresponding to the respective device regions 7a, thereby a plurality of first semiconductor chips. The first and second semiconductor chips 2 are collectively sealed with resin.
In this case, a step is generated between the back surface 1c of the first semiconductor chip 1 and the second semiconductor chip 2 with respect to the resin inflow direction shown in FIG. 28, and the second semiconductor chip 2 on the upper layer side is more Since it is retracted, a resin flow 23 as shown in FIG. 29A is obtained, and the resin (resin) easily wraps around the main surface 2b of the second semiconductor chip 2, and the air in the cavity 13a flows into the air hole 13g. Can be kicked out of.
Therefore, generation of voids on the main surface 2b of the second semiconductor chip 2 can be suppressed, and moldability can be improved.
As a modification of FIG. 29, the second semiconductor chip 2 is replaced with the first semiconductor chip as shown in FIGS. 30 and 31A with respect to the direction parallel to the resin inflow direction in the cavity 13a. Both of them may be arranged so as to have a portion projecting in a plane from the outer periphery of 1, and in that case, between the projecting portion of the second semiconductor chip 2 and the chip support surface 3 a of the multi-chip substrate 7. Is filled with NCF12 which is an adhesive.
If the space between the protruding portion of the second semiconductor chip 2 and the chip support surface 3a of the multi-chip substrate 7 is not filled with the NCF 12, the first side 13b of the cavity 13a far from the first side surface 13b is used. There is a high possibility that an unfilled portion (void) of the resin is generated below the portion where the semiconductor chip 2 protrudes. In the transfer molding method, it is possible to reduce the void volume by applying a very high pressure to the resin at the final stage of the molding process to eliminate or compress the void in the resin. If pressure is applied to the resin with a large void underneath, the chip may break.
However, in the second embodiment, the space between the protruding portion of the second semiconductor chip 2 and the chip support surface 3a of the multi-chip substrate 7 is filled with NCF 12 in advance before the molding process. Even if pressure is applied during the molding process, the problem of chip breaking can be avoided.
When the molding is completed, a batch mold portion 8 and a plurality of resin gate portions 8a as shown in FIGS. 27B and 32 are formed on the multi-piece substrate 7.
Thereafter, the solder balls are mounted in step S7 of FIG. 11 to temporarily fix the solder balls to the bump lands 3d in the device region 7a of the multi-chip substrate 7.
Subsequently, the solder ball is reflowed in step S8 to fix the solder ball to the bump land 3d.
Thereafter, the multi-chip substrate 7 in step S9 is diced into individual packages.
Further, the mark stamping in step S10 and the electrical test in step S11 are performed to complete the assembly of the CSP 22.
FIG. 35 is a plan view showing an example of the structure of the semiconductor device (stack structure CSP) according to the third embodiment of the present invention through a resin sealing body, and FIG. 36 is taken along the line JJ shown in FIG. FIG. 37 is a plan view showing an example of the structure of a first semiconductor chip incorporated in the CSP shown in FIG. 35, and FIG. 38 is a first assembly of the CSP shown in FIG. 39 is an enlarged partial cross-sectional view showing an example of the mounting state of the semiconductor chip, FIG. 39 is an enlarged partial cross-sectional view showing an example of the thermocompression bonding state of the first semiconductor chip in the assembly of the CSP shown in FIG. 35, and FIG. FIG. 41 is an enlarged partial sectional view showing an example of the shape of the adhesive material after thermocompression bonding in the thermocompression step shown, and FIG. 41 is an enlarged part showing an example of the mounting state of the second and third semiconductor chips in the assembly of the CSP shown in FIG. Sectional view, FIG. FIG. 43 is an enlarged partial cross-sectional view showing an example of the wire bonding state of the assembly of the CSP shown in FIG. 35, and FIG. 44 is an enlarged partial cross-sectional view, FIG. 44 is an enlarged partial cross-sectional view showing an example of a method of forming a protruding electrode on the first semiconductor chip in the assembly of the modified example of the CSP shown in FIG. 35, and FIG. 45 is a CSP shown in FIG. FIG. 46 is an enlarged partial cross-sectional view showing an example of a method for bonding the first semiconductor chip to the wiring board in the assembly of the modified example of FIG. 46, and FIG. 46 shows the first and second semiconductor chips in the modified example of the CSP shown in FIG. FIG. 47 is an enlarged partial sectional view showing an example of the third semiconductor chip assembled in the modified example of the CSP shown in FIG. 35.
The semiconductor device according to the third embodiment shown in FIG. 35 has a stack structure in which three semiconductor chips are stacked on an individual substrate 3 (wiring substrate), and the chip support surface 3a ( On the main surface side, the first semiconductor chip 1, the second semiconductor chip 2 stacked on the first semiconductor chip 1, and the third semiconductor chip 29 stacked on the second semiconductor chip 2, Is a resin-encapsulated type encapsulated by a resin mold, and is a CSP 30 having a stack structure of three chips.
As shown in FIGS. 35 and 36, the structure of the CSP 30 is characterized in that a plurality of pads 29a, which are electrodes formed on the main surface 29b of the third semiconductor chip 29, which is a third-stage semiconductor chip, The semiconductor chip 1 and the second semiconductor chip 2 are arranged at positions outside the respective end portions, and at this time, the portion of the second semiconductor chip 2 protruding from the first semiconductor chip 1 That is, the NCF 12 that is an adhesive is also disposed on the back surface 2 c and the back surface 29 c of the third semiconductor chip 29 that protrudes from the second semiconductor chip 2.
That is, the CSP 30 is a semiconductor package having a structure in which the NCF 12 is also disposed below each pad 29 a of the third semiconductor chip 29.
Accordingly, since the NCF 12 can support the region on the back surface 29c side corresponding to each pad 29a of the main surface 29b of the third semiconductor chip 29, wire bonding can also be performed on the third semiconductor chip 29. In addition, the pads 29 a of the third semiconductor chip 29 are also connected to the wires 4 in the same manner as the second semiconductor chip 2.
Therefore, the NCF 12 that is an adhesive is a first chip bonding portion 12d that is a first portion formed between the main surface 1b of the first semiconductor chip 1 and the chip support surface 3a of the individual substrate 3. A protruding portion 12e which is the second portion formed outside the region where the first semiconductor chip 1 is arranged and between the back surface 2c of the second semiconductor chip 2 and the chip support surface 3a of the individual substrate 3 And the outside of the area where the first semiconductor chip 1 and the area where the second semiconductor chip 2 are arranged, and the back surface 29c of the third semiconductor chip 29 and the chip support surface 3a of the individual substrate 3 And a protruding portion 12f which is a third portion formed therebetween.
Therefore, the protruding portion 12e of the NCF 12 is thicker than the first chip bonding portion 12d, and the protruding portion 12f is thicker than the protruding portion 12e.
The adhesive is preferably NCF12 or ACF, but may be other than NCF12 or ACF.
The second semiconductor chip 2 and the third semiconductor chip 29 are bonded to the back surface 1c of the first semiconductor chip 1 and the main surface 2b of the second semiconductor chip 2 by a die bond film material 5, respectively.
In addition, adhesive materials, such as NCF12 and the die-bonding film material 5, are thermosetting, and contain a thermosetting resin.
Here, as for each semiconductor chip in the CSP 30, for example, the first semiconductor chip 1 is a microcomputer, the second semiconductor chip 2 is an SRAM (Static Random Access Memory), and the third semiconductor chip 29 is a flash memory. However, the functions of the respective semiconductor chips are not limited to the functions described above, and may have other functions.
The other structure of the CSP 30 according to the third embodiment is the same as that of the CSP 9 according to the first embodiment, and a duplicate description thereof is omitted.
Next, the manufacturing method of CSP30 of this Embodiment 3 is demonstrated.
First, an individual substrate 3 (wiring substrate) having a chip support surface 3a and a back surface 3b opposite to the chip support surface 3a and having a plurality of connection terminals (electrodes) 3c on the chip support surface 3a is prepared.
Further, the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 29 are prepared.
That is, a first semiconductor chip having a main surface 1b and a back surface 1c and having a plurality of pads 1a and a plurality of semiconductor elements on the main surface 1b, and similarly having a main surface 2b and a back surface 2c, and Similarly to second semiconductor chip 2 having a plurality of pads 2a and a plurality of semiconductor elements on main surface 2b, it has main surface 29b and back surface 29c, and has a plurality of pads 29a and a plurality of pads on main surface 29b. A third semiconductor chip 29 having a semiconductor element is prepared.
At this time, gold bumps 1 d that are protruding electrodes are formed on the pads 1 a of the first semiconductor chip 1.
As shown in FIG. 37, the first semiconductor chip 1 mounted on the CSP 30 has a square shape and an outer peripheral pad array in which a plurality of pads 1a are arranged side by side on the outer peripheral portion of the main surface 1b. is there.
Thereafter, the first semiconductor chip 1 shown in FIGS. 38 to 40 is mounted.
First, as shown in FIG. 38, the main surface 1 b of the first semiconductor chip 1 faces the chip support surface 3 a of the individual substrate 3, and a plurality of pads 1 a of the first semiconductor chip 1 are formed on the individual substrate 3. The first semiconductor chip 1 is disposed on the chip support surface 3a of the individual substrate 3 so as to face the connection terminal 3c.
At that time, first, an NCF 12 (adhesive) cut larger than the first semiconductor chip 1 is arranged in the first semiconductor chip 1 mounting area of the chip support surface 3a of the individual substrate 3, and then the first semiconductor chip 1 is mounted. The pads 1a of the semiconductor chip 1 are opposed to the connection terminals 3c of the individual substrate 3, and the pads 1a and the corresponding connection terminals 3c are positioned so that the first semiconductor chip 1 is a chip of the individual substrate 3. It arrange | positions on the support surface 3a, and a load is applied to the back surface 1c of the 1st semiconductor chip 1 after that.
As a result, the gold bumps 1 d are pushed against the NCF 12, and the first semiconductor chip 1 is temporarily fixed on the individual substrate 3.
Thereafter, pressure is applied to the back surface 1c of the first semiconductor chip 1 by a thermocompression bonding head 28 which is a thermocompression bonding jig having a protrusion 28a at the tip as shown in FIG. Simultaneously with the pressure, heat is applied from the thermocompression head 28.
The protrusion 28 a at the tip of the thermocompression bonding head 28 has substantially the same shape and the same size as the second semiconductor chip 2 mounted on the first semiconductor chip 1. Specifically, the size of the projection 28a in the plane direction (direction perpendicular to the pressing direction) is slightly larger than that of the second semiconductor chip 2, and the height of the projection of the projection 28a is second. The thickness of the semiconductor chip 2 is slightly smaller.
Further, when the first semiconductor chip 1 is pressurized and heated, the NCF 12 protrudes to the outer periphery of the first semiconductor chip 1 by this pressure, and is also desired to form the protruding portion 12e and the protruding portion 12f. The thickness is as follows.
Therefore, when the back surface 1c of the first semiconductor chip 1 is pressed by the thermocompression bonding head 28, the NCF 12 protrudes to the outer periphery of the first semiconductor chip 1, and according to the protruding portion 28a of the thermocompression bonding head 28. A protruding portion (second portion) 12e and a protruding portion (third portion) 12f are formed.
As a result, in the NCF 12, as shown in FIG. 40, the first chip bonding portion 12d, the protruding portion 12e thicker than this, and the protruding portion 12f thicker than the protruding portion 12e are formed.
The difference in thickness between the protruding portion 12f and the protruding portion 12e is the second because the height of the protruding portion 28a of the thermocompression bonding head 28 is slightly smaller than the thickness of the second semiconductor chip 2. The thickness of the semiconductor chip 2 becomes smaller.
In thermocompression bonding, the individual substrate 3 is placed on the die bond stage 21 heated to about 70 ° C., and the back surface 1c of the first semiconductor chip 1 is applied by a thermocompression bonding head 28 heated to about 300 ° C. Press.
As a result, when the NCF 12 becomes high temperature and melts and hardens, the gold bumps 1d on the pads 1a of the first semiconductor chip 1 and the connection terminals 3c of the individual substrate 3 come into contact with each other and are electrically connected.
Thereafter, the second semiconductor chip 2 and the third semiconductor chip 29 shown in FIG. 41 are mounted.
The second semiconductor chip 2 and the third semiconductor chip 29 are bonded in advance.
In other words, the main surface 2 b of the second semiconductor chip 2 and the back surface 29 c of the third semiconductor chip 29 are bonded together by the die bond film material 5 that is bonded in advance to the back surface 29 c of the third semiconductor chip 29.
At that time, the first semiconductor chip 1 and the second semiconductor chip 2 are bonded so that the plurality of pads 29 a of the third semiconductor chip 29 are arranged outside the second semiconductor chip 2. A similar die bond film material 5 is also attached to the back surface 2 c of the second semiconductor chip 2.
Thus, in the state where the second semiconductor chip 2 and the third semiconductor chip 29 are bonded, the first back surface 2c of the second semiconductor chip 2 faces the back surface 1c of the first semiconductor chip 1. The second semiconductor chip 2 and the third semiconductor chip 29 are arranged on the semiconductor chip 1.
As a result, the plurality of pads 29 a of the third semiconductor chip 29 are located outside the first semiconductor chip 1 and arranged outside the second semiconductor chip 2.
Thereafter, a load and heat are applied to the main surface 29b from above the third semiconductor chip 29, and the second semiconductor chip 2 and the third semiconductor chip 29 are thermocompression bonded.
At that time, the die bond film material 5 attached to the back surface 2c of the second semiconductor chip 2 and the back surface 29c of the third semiconductor chip 29 serves as an adhesive, respectively, to form the second semiconductor chip 2 and the third semiconductor chip. 29 is thermocompression bonded.
Note that the difference in thickness between the protruding portion 12f and the protruding portion 12e in the NCF 12 is slightly smaller than the thickness of the second semiconductor chip 2, so that a part of the NCF 12, that is, the protruding portion 12f is located outside the first semiconductor chip 1. An interval (gap) between the plurality of pads 29a of the third semiconductor chip 29 arranged and the back surface 29c of the third semiconductor chip 29 and the protruding portion 12f between the chip support surface 3a of the individual substrate 3 is as follows. The third semiconductor chip 29 is arranged to be smaller than the thickness thereof.
That is, the gap formed between the protruding portion 12 f of the NCF 12 and the back surface 29 c of the third semiconductor chip 29 is much smaller than the thickness of the third semiconductor chip 29.
When the mounting of the second semiconductor chip 2 and the third semiconductor chip 29 is completed, the respective pads 29a of the third semiconductor chip 29 are arranged outside the first semiconductor chip 1 and the second semiconductor chip 2. It becomes.
Thereafter, wire bonding is performed.
That is, as shown in FIG. 42, the plurality of pads 2a of the second semiconductor chip 2 and the plurality of pads 29a of the third semiconductor chip 29 and the plurality of connection terminals 3c of the individual substrate 3 respectively corresponding to the wires are connected. Electrical connection is made through a gold wire 4 by bonding.
At that time, first, wire bonding is performed from the second semiconductor chip 2. In the wire bonding of the second semiconductor chip 2, the protruding portion 12e of the NCF 12 disposed on the back surface 2c side with respect to the pad 2a of the second semiconductor chip 2 disposed outside the first semiconductor chip 1 is provided. Since it becomes a load receiver at the time of wire bonding, the crack of the 2nd semiconductor chip 2 at the time of wire bonding can be prevented.
After the wire bonding to the second semiconductor chip 2 is finished, the wire bonding to the third semiconductor chip 29 is performed.
In the wire bonding of the third semiconductor chip 29, the protruding portion 12f of the NCF 12 arranged on the back surface 29c side with respect to each pad 29a of the third semiconductor chip 29 arranged outside the second semiconductor chip 2 Since it becomes a load receiver at the time of wire bonding, the crack of the 3rd semiconductor chip 29 at the time of wire bonding can be prevented.
Here, the gap formed between the protruding portion 12f and the back surface 29c of the third semiconductor chip 29 is much smaller than the thickness of the third semiconductor chip 29, and the protruding portion 12f takes the load during wire bonding. Since it can receive reliably, the crack of the 3rd semiconductor chip 29 can be prevented.
Thereafter, the first semiconductor chip 1, the second semiconductor chip 2, the third semiconductor chip 29, and the plurality of wires 4 are sealed with resin.
That is, on the chip support surface 3a side of the individual substrate 3, the first semiconductor chip 1, the second semiconductor chip 2, the third semiconductor chip 29, and the plurality of wires 4 are sealed with resin by transfer molding. A stop 6 is formed.
Note that the protruding portion 12f of the NCF 12 serves as a load receiver even when resin molding is applied or when a load is applied to the third semiconductor chip 29, such as during mold clamping. Can be prevented.
Thereafter, as shown in FIG. 36, solder balls 11 that are a plurality of protruding electrodes that are electrically connected to the plurality of connection terminals 3 c of the individual substrate 3 are mounted on the back surface 3 b of the individual substrate 3.
That is, the solder balls 11 are mounted on each bump land 3d (see FIG. 14) exposed on the back surface 3b of the individual substrate 3 by reflow or the like to form external electrodes of the CSP 30.
Next, a modified example of the manufacturing method of the CSP 30 according to the third embodiment will be described.
First, as shown in FIG. 43, the first semiconductor chip 1 and the second semiconductor chip 2 are bonded. Here, the back surface 1c of the first semiconductor chip 1 and the back surface 2c of the second semiconductor chip 2 are arranged facing each other and bonded. At that time, the die bond film material 5 is pasted on the back surface 1c of the first semiconductor chip 1 in advance, and the die bond film material 5 is bonded by thermocompression using a thermocompression head 33 which is a thermocompression bonding jig. Glue through.
Thereafter, as shown in FIG. 44, gold bumps 1d as protruding electrodes as shown in FIG. 45 are formed on the pads 1a of the first semiconductor chip 1.
At this time, a gold bump 1d is formed on the pad 1a of the first semiconductor chip 1 by using a wire bonding technique using a gold wire. That is, the wire 4 is guided by the capillary 32 which is a bonding tool, and the gold bump 1d is formed on the pad 1a of the first semiconductor chip 1 in the same manner as the wire bonding.
Thereafter, the NCF 12 cut larger than the first semiconductor chip 1 is disposed in the first semiconductor chip 1 mounting area of the chip support surface 3a of the individual substrate 3, and then the pads 1a of the first semiconductor chip 1 are arranged. The pads 1a and the corresponding connection terminals 3c are positioned so as to face the connection terminals 3c of the individual substrate 3, and the first semiconductor chip 1 and the second semiconductor chip 2 are arranged on the chip of the individual substrate 3. It arrange | positions on the support surface 3a.
That is, the first semiconductor chip 1 bonded to the second semiconductor chip 2 is placed on the chip support surface 3 a of the individual substrate 3 so that the main surface 1 b faces the chip support surface 3 a of the individual substrate 3. Deploy.
Thereafter, thermocompression bonding is performed using the thermocompression head 33 to electrically connect the first semiconductor chip 1 and the plurality of connection terminals 3c of the individual substrate 3 via the plurality of gold bumps 1d. The main surface 1b of the first semiconductor chip 1 and the chip support surface 3a of the individual substrate 3 are bonded with NCF 12.
At that time, as shown in FIG. 45, a load and heat are applied from the main surface 2 b side of the second semiconductor chip 2 through the second semiconductor chip 2 by the thermocompression bonding head 33.
Thereby, the thermosetting resin of NCF 12 is cured between the main surface 1b of the first semiconductor chip 1 and the chip support surface 3a of the individual substrate 3, and the first semiconductor chip is interposed via the thermosetting resin. 1 is fixed on the chip support surface 3a of the individual substrate 3, and further, the gold bumps 1d on the pads 1a of the first semiconductor chip 1 and the connection terminals 3c of the individual substrate 3 come into contact with each other and are electrically connected. To do.
The NCF 12 protrudes to the outer periphery of the first semiconductor chip 1 by this pressure when the first semiconductor chip 1 is pressurized and heated, and is desired to form the protruding portion 12e and the protruding portion 12f. The thickness is as follows.
Therefore, as shown in FIG. 46, when the first semiconductor chip 1 is pressurized via the second semiconductor chip 2 by the thermocompression bonding head 33, the NCF 12 protrudes around the outer periphery of the first semiconductor chip 1. A protruding portion (second portion) 12e is formed on the back surface 2c side of the second semiconductor chip 2 protruding from the first semiconductor chip 1, and an protruding portion (third portion) 12f is formed on the outer side. Is done.
At this time, due to the pressing surface of the thermocompression bonding head 33, the main surface 2b of the second semiconductor chip 2 and the protruding portion 12f are formed at substantially the same height or slightly slightly lower than the protruding portion 12f. .
Thereafter, the third semiconductor chip 29 is bonded onto the main surface 2 b of the second semiconductor chip 2 so that the back surface 29 c faces the main surface 2 b of the second semiconductor chip 2.
At this time, the third semiconductor chip 29 is placed in the second semiconductor so that the plurality of pads 29a of the third semiconductor chip 29 are arranged at positions outside the first semiconductor chip 1 and the second semiconductor chip 2. Place on chip 2.
That is, the plurality of pads 29a of the third semiconductor chip 29 are arranged outside the first semiconductor chip 1 and the second semiconductor chip 2, and the die bond film material 5 is previously attached to the back surface 29c. The third semiconductor chip 29 is arranged on the main surface 2b with its back surface 29c facing the main surface 2b of the second semiconductor chip 2, and then, as shown in FIG. The main surface 29 b of the third semiconductor chip 29 is pressed and heated by the thermocompression bonding head 33 to bond them together.
As a result, the second semiconductor chip 2 is bonded to the back surface 1c of the first semiconductor chip 1 via the die bond film material 5 including the thermosetting resin, and the third semiconductor chip 29 is bonded to the second semiconductor chip 29. Similarly, a plurality of pads 29a of the third semiconductor chip 29 are bonded to the main surface 2b of the semiconductor chip 2 via the die bond film material 5 containing a thermosetting resin. The semiconductor chip 1 and the second semiconductor chip 2 are disposed outside the semiconductor chip 1.
Thereafter, wire bonding is performed by the same method as the wire bonding shown in FIG.
At this time, the protruding portion 12e of the NCF 12 disposed on the back surface 2c side of the pad 2a of the second semiconductor chip 2 disposed outside the first semiconductor chip 1 serves as a load receiver during wire bonding. Therefore, it is possible to prevent the second semiconductor chip 2 from cracking during wire bonding.
Furthermore, for each pad 29a of the third semiconductor chip 29 disposed outside the second semiconductor chip 2, the protruding portion 12f of the NCF 12 disposed on the back surface 29c side serves as a load receiver during wire bonding. Therefore, cracking of the third semiconductor chip 29 at the time of wire bonding can be prevented.
Further, in the manufacturing method of the modified example, the shape of the tip (pressurized surface) of the thermocompression bonding head 33 can be a flat surface, and the thermocompression bonding head 28 of the example of the third embodiment described above. The shape can be made simpler than that.
Note that the manufacturing method after wire bonding and other effects obtained thereby are the same as those in the above-described example of the third embodiment, and therefore, redundant description thereof is omitted.
FIG. 48 is a plan view showing an example of the structure of the semiconductor device (stacked structure CSP) according to the fourth embodiment of the present invention through a resin sealing body, and FIG. 49 is a first view incorporated in the CSP shown in FIG. FIG. 50 is an enlarged partial cross-sectional view showing an example of the mounting state of the first semiconductor chip in the assembly of the CSP shown in FIG. 48 at a location cut along the line KK. 51 is an enlarged partial sectional view showing an example of the mounting state of the second semiconductor chip in the assembly of the CSP shown in FIG. 48. FIG. 52 is an example of the mounting state of the third semiconductor chip in the assembly of the CSP shown in FIG. 53 is an enlarged partial sectional view, FIG. 53 is an enlarged partial sectional view showing an example of the wire bonding state in the assembly of the CSP shown in FIG. 48, and FIG. 54 is a KK line of the CSP shown in FIG. Is an enlarged partial cross-sectional view showing the structure of a cross section taken along.
Similar to the CSP 30 of the third embodiment, the semiconductor device of the fourth embodiment is a CSP 31 (see FIG. 48) having a stack structure in which three semiconductor chips are stacked on the individual substrate 3. 3 is different from the CSP 30 in that the plurality of pads 29a of the third semiconductor chip 29, which is the third-stage semiconductor chip, are located in the region inside the end portion of the second-stage second semiconductor chip 2. And, it is arranged at a position outside the first semiconductor chip 1 in the first stage.
Therefore, the NCF 12 which is an adhesive is a first chip joint portion 12d which is a first portion formed between the main surface 1b of the first semiconductor chip 1 and the chip support surface 3a of the individual substrate 3. A protruding portion 12e which is the second portion formed outside the region where the first semiconductor chip 1 is arranged and between the back surface 2c of the second semiconductor chip 2 and the chip support surface 3a of the individual substrate 3 Since each pad 29a of the third semiconductor chip 29 is disposed on the second semiconductor chip 2, the protruding portion 12e is provided on the back surface of each pad 29a of the second semiconductor chip 2. 2c side and the back surface 29c side of each pad 29a of the third semiconductor chip 29 are arranged.
As a result, the protruding portion 12e of the NCF 12 in the CSP 31 supports the region where the plurality of pads 2a of the second semiconductor chip 2 are arranged, and further the third semiconductor chip 29 via the second semiconductor chip 2. The region where the plurality of pads 29a are arranged is also supported.
As shown in FIG. 49, the first semiconductor chip 1 mounted on the CSP 31 is rectangular, and a plurality of pads 1a are arranged in parallel in the longitudinal direction in the vicinity of the center in the width direction of the main surface 1b. The center pad array is arranged.
Each semiconductor chip in the CSP 31 includes, for example, a first semiconductor chip 1 that is a DRAM (Dynamic Random Access Memory), a second semiconductor chip 2 that is an SRAM (Static Random Access Memory), and a third semiconductor chip. The chip 29 is a flash memory or the like, but the function of each semiconductor chip is not limited to the above-described function, and may have other functions.
The other structure of the CSP 31 according to the fourth embodiment is the same as that of the CSP 30 according to the third embodiment, and a duplicate description thereof is omitted.
Next, the manufacturing method of CSP31 of this Embodiment 4 is demonstrated.
First, as in the third embodiment, an individual substrate 3, a first semiconductor chip 1, a second semiconductor chip 2, and a third semiconductor chip 29 having a plurality of connection terminals 3c are prepared.
Note that the first semiconductor chip 1 has a center pad arrangement as shown in FIG. 49, and gold bumps 1d, which are protruding electrodes, are formed on each pad 1a as in the third embodiment. .
Thereafter, the first semiconductor chip 1 shown in FIG. 50 is mounted.
At that time, first, the NCF 12 cut larger than the first semiconductor chip 1 is arranged in the first semiconductor chip 1 mounting area of the chip support surface 3 a of the individual substrate 3, and then the first semiconductor chip 1. The first semiconductor chip 1 is placed on the chip support surface 3 a of the individual substrate 3 by positioning the pad 1 a and the corresponding connection terminal 3 c so that the pad 1 a faces the connection terminal 3 c of the individual substrate 3. Then, a load is applied to the back surface 1 c of the first semiconductor chip 1.
Thereafter, pressure is applied to the back surface 1c of the first semiconductor chip 1 by the thermocompression bonding head 33 having a flat pressure surface, and heat is also applied from the thermocompression bonding head 33 at the same time.
Thereby, the thermosetting resin of NCF 12 is cured between the main surface 1b of the first semiconductor chip 1 and the chip support surface 3a of the individual substrate 3, and the first semiconductor chip is interposed via the thermosetting resin. 1 is fixed on the chip support surface 3 a of the individual substrate 3. As a result, the gold bump 1d on the pad 1a of the first semiconductor chip 1 and the connection terminal 3c of the individual substrate 3 come into contact and are electrically connected.
The NCF 12 protrudes from the outer periphery of the first semiconductor chip 1 by the pressure when the first semiconductor chip 1 is pressurized and heated, but is covered by the pressure surface of the thermocompression bonding head 33. Therefore, the protruding portion 12e is formed.
As a result, the back surface 1c of the first semiconductor chip 1 and the protruding portion 12e are formed at substantially the same height, or the protruding portion 12e is formed slightly lower.
Thereafter, the second semiconductor chip 2 shown in FIG. 51 is mounted.
Here, the second semiconductor chip 2 is bonded onto the back surface 1 c of the first semiconductor chip 1 so that the back surface 2 c faces the back surface 1 c of the first semiconductor chip 1.
At this time, as shown in FIG. 48, the second semiconductor chip 2 is placed in the first semiconductor so that the plurality of pads 2 a of the second semiconductor chip 2 are arranged at positions outside the first semiconductor chip 1. It is arranged on the chip 1.
That is, the plurality of pads 2a of the second semiconductor chip 2 are located outside the first semiconductor chip 1 and disposed on the protruding portion 12e of the NCF 12, and the die bond film material 5 is previously placed on the back surface 2c. The pasted second semiconductor chip 2 is placed on the back surface 1c with its back surface 2c facing the back surface 1c of the first semiconductor chip 1, and then the second semiconductor chip 2 is thermocompression bonded from above. The main surface 2b of the second semiconductor chip 2 is pressed and heated by the contact 33 to bond them together.
As a result, the second semiconductor chip 2 is bonded to the back surface 1c of the first semiconductor chip 1 via the die bond film material 5 containing a thermosetting resin. At this time, the second semiconductor chip 2 The plurality of pads 2 a are arranged at positions outside the first semiconductor chip 1.
Thereafter, the third semiconductor chip 29 shown in FIG. 52 is mounted.
Here, the third semiconductor chip 29 is bonded onto the main surface 2 b of the second semiconductor chip 2 so that the back surface 29 c faces the main surface 2 b of the second semiconductor chip 2. At that time, the plurality of pads 29 a of the third semiconductor chip 29 are arranged inside the region where the plurality of pads 2 a of the second semiconductor chip 2 are arranged and outside the first semiconductor chip 1. Thus, the third semiconductor chip 29 is arranged on the second semiconductor chip 2.
Thereafter, the main surface 29b of the third semiconductor chip 29 is pressed and heated by the thermocompression bonding head 33 from above the third semiconductor chip 29 to bond them together.
As a result, the third semiconductor chip 29 is bonded to the main surface 2b of the second semiconductor chip 2 via the die bond film material 5 containing a thermosetting resin. The plurality of pads 29 a of the chip 29 are in a state of being disposed inside the region where the plurality of pads 2 a of the second semiconductor chip 2 are disposed and outside the first semiconductor chip 1.
Therefore, the region of the second semiconductor chip 2 protruding from the first semiconductor chip 1 is supported by the protruding portion 12e of the NCF 12, and the region where the plurality of pads 29a of the third semiconductor chip 29 are arranged is the second. The semiconductor chip 2 is also supported by the protruding portion 12e.
Thereafter, wire bonding is performed as shown in FIG.
That is, the plurality of pads 2a of the second semiconductor chip 2 and the plurality of pads 29a of the third semiconductor chip 29 are electrically connected to the plurality of connection terminals 3c of the individual substrate 3 corresponding to each by wire bonding. .
At that time, first, wire bonding is performed from the second semiconductor chip 2.
A part of the NCF 12, that is, the protruding portion 12e, is a distance between the back surface 2c of the region where the plurality of pads 2a of the second semiconductor chip 2 arranged outside the first semiconductor chip 1 are arranged and the protruding portion 12e. In this state, the (gap) is arranged to be smaller than the thickness of the second semiconductor chip 2.
Therefore, in the wire bonding of the second semiconductor chip 2, the NCF 12 disposed on the back surface 2c side with respect to each of the plurality of pads 2a of the second semiconductor chip 2 disposed outside the first semiconductor chip 1. Since the protruding portion 12e serves as a load receiver during wire bonding, the second semiconductor chip 2 can be prevented from cracking during wire bonding.
After the wire bonding to the second semiconductor chip 2 is finished, the wire bonding to the third semiconductor chip 29 is performed. In the wire bonding of the third semiconductor chip 29, the second semiconductor chip 2 and the protruding portion 12e of the NCF 12 arranged on the back surface 2c side serve as a load receiver during wire bonding. The crack of the semiconductor chip 29 can be prevented.
Thereafter, the first semiconductor chip 1, the second semiconductor chip 2, the third semiconductor chip 29, and the plurality of wires 4 are resin-sealed by transfer molding, whereby a resin-sealed body 6 as shown in FIG. 54 is formed. Form.
Note that the protruding portion 12e of the NCF 12 serves as a load receiver even when resin molding is applied or when a load is applied to the third semiconductor chip 29, such as during mold clamping, so that the third semiconductor chip 29 cracks. Can be prevented.
That is, the solder ball 11 is mounted on each bump land 3d (see FIG. 14) exposed on the back surface 3b of the individual substrate 3 by reflow or the like to form an external electrode of the CSP 31.
In the manufacturing method of the fourth embodiment, the shape of the tip (pressurized surface) of the thermocompression bonding head 33 can be a flat surface, and the thermocompression bonding head of the third embodiment is an example. Compared to 28, the shape can be made simple.
In the first embodiment, in order to ensure the connection reliability between the gold bumps 1d and the connection terminals 3c, the plurality of first semiconductor chips 1 are individually thermocompression bonded, so there is a concern that work efficiency may be reduced. Is done. Therefore, as a measure to improve the work efficiency of thermocompression bonding, the temperature of heat treatment applied to the first adhesive material such as NCF12 at the time of thermocompression bonding is set higher than the temperature of heat treatment applied to the second adhesive material. The curing time of the first adhesive of the first semiconductor chip 1 on the lower layer side can be shortened, thereby improving the working efficiency of the entire thermocompression bonding.
However, when the temperature of the heat treatment of the first semiconductor chip 1 is increased, the warp of the first semiconductor chip 1 after thermosetting increases due to the difference in thermal expansion coefficient between the substrate and the chip, and the first semiconductor chip 1 The warp of the first semiconductor chip 1 after the mounting is increased.
That is, the flatness of the first semiconductor chip 1 after the mounting of the first semiconductor chip 1 is deteriorated. As described above, if the second semiconductor chip 2 mounted on the first semiconductor chip 1 is tilted due to the warp of the first semiconductor chip 1, wire bonding cannot be performed satisfactorily, and the second semiconductor chip As a result, the connection reliability between 2 and the connection terminal 3c is lowered.
Therefore, after the first semiconductor chip 1 is mounted by thermocompression bonding, the second semiconductor chip 2 is attached to the first semiconductor chip 1 via the second adhesive material such as the die bond film material 5 described in the first embodiment. In a state where the second semiconductor chip 2 is disposed on the back surface 1c of the substrate and the second semiconductor chip 2 is held by the crimping head, the second adhesive material is subjected to heat treatment to be cured, and the second semiconductor chip 2 is bonded to the second adhesive chip. It fixes on the 1st semiconductor chip 1 via a material.
Thereafter, a jig such as a crimping head is separated from the second semiconductor chip 2.
Thus, by fixing the second semiconductor chip 2 with the second semiconductor chip 2 held by the jig (crimping head), the flatness is lowered even on the warped first semiconductor chip 1. The second semiconductor chip 2 can be fixed without any problem.
At this time, since the chip is separated into pieces with the die-bonding film material 5 attached in advance to the back surface 2c of the second semiconductor chip 2, the pieces are separated into a plurality of device regions 7a. Compared with the mounting process of the first semiconductor chip 1 in which the converted NCF 12 needs to be arranged, the working efficiency can be increased.
Note that when this method is used to perform sequential die bonding of a plurality of device regions 7a as described in the second embodiment, first, as shown in FIG. 23, one device region 7a is used. The mounting of the first semiconductor chip 1 is thermocompression bonded by the above-described method, and then the third semiconductor chip 26 (the third semiconductor chip here is the same as described in the second embodiment). 1 is prepared in the same structure as that of the first semiconductor chip 1 and is arranged on the lower layer side), and the third semiconductor chip 26 is picked up to the other device region 7a of the substrate 7 to obtain the third adhesive. To place through.
Subsequently, the third adhesive material is cured by heat treatment, and the third semiconductor chip 26 is fixed on the other device region 7a of the multi-chip substrate 7 via the third adhesive material.
Further, a second semiconductor chip 2 is prepared, and then the second semiconductor chip 2 is disposed on the first semiconductor chip 1 via a second adhesive material such as a die bond film material 5.
Further, in a state where the second semiconductor chip 2 is held by a jig such as a crimping head, the second adhesive material is cured by heat treatment, and the second semiconductor chip 2 is interposed via the second adhesive material. To be fixed on the first semiconductor chip 1.
Thereafter, the jig is separated from the second semiconductor chip 2.
Thereafter, a fourth semiconductor chip 27 (here, the fourth semiconductor chip 27 has the same structure as the second semiconductor chip 2 described in the second embodiment and is disposed on the upper layer side). Then, the fourth semiconductor chip 27 is disposed on the third semiconductor chip 26 via the fourth adhesive material such as the die bond film material 5.
Further, in a state where the fourth semiconductor chip 27 is held by a jig such as a crimping head, the fourth adhesive material is subjected to heat treatment to be cured, and the fourth semiconductor chip 27 is interposed via the fourth adhesive material. And fixed on the third semiconductor chip 26.
Thereafter, the jig is separated from the fourth semiconductor chip 27.
In the second embodiment, the case where a plurality of first NCFs 12b are arranged as a first adhesive in a staggered arrangement as shown in FIG. 17 is described. However, the first adhesive is arranged in a staggered manner. It is not limited to arrays. For example, when the thermal influence on the adjacent device region 7a by the thermocompression bonding head 20 can be ignored due to the characteristics of the adhesive or the setting of the thermocompression bonding process, the first adhesive is previously applied to the plurality of adjacent device regions 7a. However, if the first adhesive is disposed on a large number of device regions 7a, the NCF 12 may be thermally cured by being exposed to the heat from the die bond stage 21 for a long time. . In such a case, as shown in the modified example of FIG. 33, for example, the first NCF 12b is arranged for each column, and the first semiconductor chip 1 on the first NCF 12b in one column (three) is arranged. After the mounting, the first NCF 12b and the first semiconductor chip 1 may be mounted one by one by moving to the adjacent column.
In the first and second embodiments, the semiconductor device has been described as having a stack structure in which two semiconductor chips are stacked. However, the number of stacked semiconductor chips may be three layers as shown in the modification of FIG. It may be more.
In this way, even when three or more semiconductor chips are stacked, the thickness of the semiconductor chip to be face-up mounted is smaller than that of the semiconductor chip to be face-down mounted, and the pressure applied in the face-down mounting process is increased. It is possible to reduce the thickness of the CSP 25 without reducing the reliability and preventing the occurrence of chip cracking.
In the CSP 25 having the three-layer stack structure shown in FIG. 34, the wire bonding performed on the third-stage semiconductor chip 24 is 1st bonding on the substrate side and 2nd bonding on the chip side. The height of the sealing body 6 is kept low so that the height of the CSP 25 does not become high.
In the first embodiment, the case where the first semiconductor chip 1 on the lower layer side is a logic chip and the second semiconductor chip 2 on the upper layer side is a memory chip in the stack structure has been described. The function of the upper semiconductor chip is not particularly limited.
In the second embodiment, the case where the multi-piece substrate 7 is used and the collective molding method is adopted as the assembly of the semiconductor device has been described. However, the individual substrate 3 divided in advance is used. Further, it may be assembled by using a multi-mold substrate 7 and by a single molding method in which one cavity 13a corresponds to one device region 7a.
In the first and second embodiments, the lower layer side flip chip connection is performed using a film-like material such as NCF 12 or ACF, and the upper layer side die bonding is performed using the die bond film material 5 as the adhesive. However, the adhesive may be in the form of a paste.
In the first and second embodiments, the case where the semiconductor device is the CSP 9, 22, 25 has been described. However, the semiconductor device has a stack structure, and stacked semiconductor chips are mounted on a wiring board. If the upper semiconductor chip is thinner than the lowermost semiconductor chip, other semiconductor devices such as BGA (Ball Grid Array) and LGA (Land Grid Array) may be used.
In a semiconductor device having a stack structure, the semiconductor device can be thinned by reducing the thickness of the upper semiconductor chip from the lower semiconductor chip.
1 is a cross-sectional view showing an example of the structure of a semiconductor device (a CSP having a stack structure) according to a first embodiment of the present invention;
FIG. 2 is a partial cross-sectional view showing the structure of the CSP shown in FIG.
3 is a partial cross-sectional view showing an example of a state in which a die bond film is attached to a wafer in the assembly of the CSP shown in FIG. 1;
4 is a partial cross-sectional view showing an example of wafer dicing in the assembly of the CSP shown in FIG. 1;
5A and 5B are partial cross-sectional views showing an example of assembly of the CSP shown in FIG. 1, FIG. 5A is a view showing a first chip mount, and FIG. 5B is a first chip thermocompression bonding. FIG.
6A and 6B are partial cross-sectional views showing an example of the assembly of the CSP shown in FIG. 1, FIG. 6A is a diagram showing a second chip mount, and FIG. 6B is a second chip wire bonding. FIG.
7 is a partial cross-sectional view showing an example of the structure of a semiconductor device (a CSP having a stack structure) according to a second embodiment of the present invention; FIG.
8 is an enlarged plan view showing an example of a wiring state in the assembly of the CSP shown in FIG. 7. FIG.
9A and 9B are partial cross-sectional views showing an example of assembly of the CSP shown in FIG. 7, FIG. 9A is a view showing a first chip mount, and FIG. 9B is a first chip thermocompression bonding. FIG.
10A and 10B are partial cross-sectional views showing an example of the assembly of the CSP shown in FIG. 7, FIG. 10A is a view showing a second chip mount, and FIG. 10B is a second chip wire bonding; FIG.
FIG. 11 is a manufacturing process flow chart showing an example of all the processes in an assembling procedure of the semiconductor device according to the second embodiment of the present invention;
FIG. 12 is a manufacturing process flowchart showing an example of detailed steps in the assembly procedure of the semiconductor device of the second embodiment of the present invention;
13 is a plan view showing an example of the structure of a multi-chip substrate in assembling the semiconductor device according to the second embodiment of the present invention; FIG.
14A and 14B are enlarged partial views showing an enlarged part of the multi-chip substrate shown in FIG. 13, and FIG. 14A is a plan view showing the details of part A in FIG. And (b) is a bottom view of the back side of (a).
15A and 15B are plan views of first and second semiconductor chips used for assembling the semiconductor device according to the second embodiment of the present invention, and FIG. 15A is a first semiconductor chip; FIG. 5B is a diagram of the second semiconductor chip.
16A and 16B are views showing an example of the structure of the first semiconductor chip shown in FIG. 15, FIG. 16A is an enlarged partial side view, and FIG. 16B is an enlarged partial plan view. .
FIG. 17 is a plan view showing an example of a first NCF adhering step in assembling the semiconductor device according to the second embodiment of the present invention;
FIGS. 18A and 18B are plan views showing details of the first NCF attaching step shown in FIG. 17; FIG. 18A is a view before placing the NCF, and FIG. 18B is after attaching the NCF; FIG.
19A and 19B are views showing the arrangement state of the first semiconductor chip with respect to the first NCF attachment shown in FIG. 17, and FIG. 19A is a view showing the arrangement state of the first semiconductor chip. (B) is a figure which shows the press state by a collet.
FIGS. 20A and 20B are diagrams showing an example of a die bonding method for a first semiconductor chip, FIG. 20A is a diagram showing a first semiconductor chip mounted state, and FIG. 20B is a diagram showing a first semiconductor chip; It is a figure after chip | tip thermocompression bonding.
21 is a plan view showing an example of a structure after die bonding of the first semiconductor chip with respect to the first NCF pasting shown in FIG. 17;
22 is a plan view showing an example of a structure after the second NCF is attached to the first NCF attachment shown in FIG.
23 (a) and 23 (b) are diagrams showing a completed mounting structure of the first and third semiconductor chips with respect to the second NCF attachment shown in FIG. 22, and FIG. 23 (a) is a plan view; (B) is an enlarged partial top view which shows the detail of the B section of (a).
24 is a plan view showing an example of a structure after die bonding of the second and fourth semiconductor chips with respect to the second NCF pasting shown in FIG. 22;
FIGS. 25A and 25B are views showing a structure after wire bonding of the second and fourth semiconductor chips, FIG. 25A is a plan view, and FIG. 25B is a diagram of C in FIG. It is an enlarged partial top view which shows the detail of a part.
FIGS. 26A and 26B are plan views showing an example of a wire bonding state of the second semiconductor chip, FIG. 26A is a diagram before wire bonding, and FIG. 26B is a diagram after wire bonding; is there.
FIGS. 27A and 27B are plan views showing an example of the structure of a multi-cavity substrate on which batch molding is performed. FIG. 27A is a diagram before batch molding, and FIG. 27B is a diagram after batch molding. FIG.
FIG. 28 is a plan view showing an example of a resin inflow direction in the batch molding method for assembling the semiconductor device according to the second embodiment of the present invention;
FIGS. 29A and 29B are diagrams showing an example of the batch molding method shown in FIG. 28, and FIG. 29A is a partial cross-sectional view of the section along the line DD in FIG. 28 at the time of batch molding. (B) is the fragmentary sectional view at the time of the collective molding of the cross section along the EE line of FIG.
30 is a plan view showing an example of a resin inflow direction in the collective molding method according to a modification of the collective molding method shown in FIG. 28. FIG.
FIGS. 31A and 31B are views showing a batch molding method of the modification shown in FIG. 30, and FIG. 31A is a partial cross section of the cross section taken along the line FF in FIG. FIG. 4B is a partial cross-sectional view of the cross section taken along the line GG in FIG.
32 is a plan view showing an example of the structure of a multi-chip substrate after batch molding in the assembly of the semiconductor device according to the second embodiment of the present invention; FIG.
FIG. 33 is a plan view showing a first NCF pasting step as a modification to the first NCF pasting step in assembling the semiconductor device according to the second embodiment of the present invention;
34 is a cross-sectional view showing the structure of a modified CSP with respect to the CSP having the stack structure shown in FIG. 1;
FIG. 35 is a plan view showing an example of the structure of a semiconductor device (a CSP having a stack structure) according to a third embodiment of the present invention through a resin sealing body;
36 is an enlarged partial cross-sectional view showing a cross-sectional structure cut along the line JJ shown in FIG. 35. FIG.
37 is a plan view showing an example of a structure of a first semiconductor chip incorporated in the CSP shown in FIG. 35. FIG.
38 is an enlarged partial cross-sectional view showing an example of a mounted state of the first semiconductor chip in the assembly of the CSP shown in FIG. 35;
FIG. 39 is an enlarged partial sectional view showing an example of a thermocompression bonding state of the first semiconductor chip in the assembly of the CSP shown in FIG. 35;
40 is an enlarged partial cross-sectional view showing an example of the shape of the adhesive after thermocompression bonding in the thermocompression bonding step shown in FIG. 39. FIG.
41 is an enlarged partial cross-sectional view showing an example of the mounted state of the second and third semiconductor chips in the assembly of the CSP shown in FIG. 35;
42 is an enlarged partial sectional view showing an example of a wire bonding state in the assembly of the CSP shown in FIG. 35. FIG.
43 is an enlarged partial cross-sectional view showing an example of a bonding method of the first semiconductor chip and the second semiconductor chip in the assembly of the modified example of the CSP shown in FIG. 35;
44 is an enlarged partial cross-sectional view showing an example of a method of forming a protruding electrode on the first semiconductor chip in the assembly of the modified example of the CSP shown in FIG. 35;
45 is an enlarged partial cross-sectional view showing an example of a method for adhering the first semiconductor chip to the wiring board in the assembly of the modified example of the CSP shown in FIG. 35;
46 is an enlarged partial cross-sectional view showing an example of a thermocompression bonding state of the first and second semiconductor chips in the assembly of the modified example of the CSP shown in FIG. 35. FIG.
47 is an enlarged partial sectional view showing an example of a thermocompression bonding state of a third semiconductor chip in the assembly of the modified example of the CSP shown in FIG. 35. FIG.
48 is a plan view showing an example of the structure of a semiconductor device (a CSP having a stack structure) according to a fourth embodiment of the present invention through a resin sealing body; FIG.
49 is a plan view showing an example of a structure of a first semiconductor chip incorporated in the CSP shown in FIG. 48. FIG.
50 is an enlarged partial cross-sectional view showing an example of the mounting state of the first semiconductor chip in the assembly of the CSP shown in FIG. 48, taken along the line KK. FIG.
51 is an enlarged partial cross-sectional view showing an example of a mounted state of a second semiconductor chip in the assembly of the CSP shown in FIG. 48. FIG.
52 is an enlarged partial cross-sectional view showing an example of a mounted state of a third semiconductor chip in the assembly of the CSP shown in FIG. 48. FIG.
53 is an enlarged partial sectional view showing an example of a wire bonding state in the assembly of the CSP shown in FIG. 48. FIG.
54 is an enlarged partial cross-sectional view showing a cross-sectional structure taken along the line KK of the CSP shown in FIG. 48. FIG.
1 First semiconductor chip
1a Pad (electrode)
1b Main surface
1c Back side
1d Gold bump (projection electrode)
2 Second semiconductor chip
2a Pad (electrode)
2b Main surface
2c Back side
3 piece board (wiring board)
3a Chip support surface (main surface)
3b Back side (opposite side)
3c Connection terminal (electrode)
3d bump land
3e First connection terminal (first electrode)
3f Second connection terminal (second electrode)
5 Die bond film material (adhesive)
6 Resin encapsulant
7 Large number of substrate (wiring board)
7a Device area
7b Dicing line
7c Gold plating part
8 Batch mold part
8a Resin gate
9 CSP (semiconductor device)
10 Dicing blade
11 Solder balls (external electrodes)
12 NCF (Adhesive)
12a Flat part
12b First NCF (first adhesive)
12c Second NCF (second adhesive)
12d First chip joint (first portion)
12e Protruding part (second part)
12f Protruding part (third part)
13 Mold (mold)
13a cavity
13b first side
13c Second side
13d Third side
13e 4th side
13f Resin inlet
13g air hole
13h Upper mold
13i Lower mold
13j upper surface
13k bottom
15 Protection sheet
16 Dicing tape
17 Semiconductor wafer
17a Main surface
17b reverse side
19 Fixing ring
20 Thermocompression bonding head
21 Die Bond Stage
22 CSP (semiconductor device)
23 Resin Flow
24 Third stage semiconductor chip
25 CSP (semiconductor device)
26 Third semiconductor chip
27 Fourth semiconductor chip
28 Thermocompression Head (Jig for Thermocompression)
28a Protrusion
29 Third semiconductor chip
29a Pad (electrode)
29b Main surface
29c reverse side
30 CSP (semiconductor device)
31 CSP (semiconductor device)
32 capillary
33 Thermocompression Head (Jig for Thermocompression)
(A) preparing a wiring board having a plurality of electrodes on the main surface;
(B) preparing a first semiconductor chip having a main surface and a back surface, and having a plurality of protruding electrodes and a plurality of semiconductor elements on the main surface;
(C) having a main surface and a back surface, having a plurality of electrodes and a plurality of semiconductor elements on the main surface, and preparing a second semiconductor chip thinner than the first semiconductor chip;
(D) The main surface of the first semiconductor chip faces the main surface of the wiring board, and the plurality of protruding electrodes of the first semiconductor chip are opposed to the plurality of electrodes of the wiring board.
Disposing the first semiconductor chip on the main surface of the wiring board via a first adhesive ;
(E) applying pressure to the back surface of the first semiconductor chip after the step (d) to electrically connect the plurality of protruding electrodes of the first semiconductor chip and the plurality of electrodes of the wiring board ; and Bonding the first semiconductor chip to the wiring board with the first adhesive ;
(F) After the step (e), the second semiconductor chip is bonded onto the back surface of the first semiconductor chip, and the back surface of the first semiconductor chip and the back surface of the second semiconductor chip are second bonded. wood arranged as facing through, and adhering the second semiconductor chip to the back surface of the first semiconductor chip the (e) with a small pressure from the pressure applied to the added during step by said second adhesive Process,
(G) electrically connecting the plurality of electrodes of the second semiconductor chip and the plurality of electrodes of the wiring board via a plurality of wires;
(H) forming a resin sealing body that seals the first and second semiconductor chips and the plurality of wires.
2. The method of manufacturing a semiconductor device according to claim 1, wherein heat is applied simultaneously to the first semiconductor chip at the time of the step (e).
2. The method of manufacturing a semiconductor device according to claim 1 , wherein the plurality of protruding electrodes are gold bumps, the first adhesive material is a film material, and the plurality of first semiconductor chips in the step (e). A method of manufacturing a semiconductor device , wherein electrical connection between the protruding electrode and the plurality of electrodes of the wiring board is performed by press- contacting the gold bumps .
JP2002012775A 2001-04-06 2002-01-22 Manufacturing method of semiconductor device Active JP3839323B2 (en)
JP2001-108603 2001-04-06
JP2001108603 2001-04-06
JP2002012775A JP3839323B2 (en) 2001-04-06 2002-01-22 Manufacturing method of semiconductor device
TW091103953A TWI286806B (en) 2001-04-06 2002-03-04 Semiconductor device and method for manufacturing the same
US10/086,717 US6951774B2 (en) 2001-04-06 2002-03-04 Semiconductor device and method of manufacturing the same
KR1020020012170A KR100818423B1 (en) 2001-04-06 2002-03-07 Semiconductor device and method of manufacturing the same
JP2002368190A5 JP2002368190A5 (en) 2002-12-20
JP2002368190A JP2002368190A (en) 2002-12-20
JP3839323B2 true JP3839323B2 (en) 2006-11-01
ID=26613215
JP2002012775A Active JP3839323B2 (en) 2001-04-06 2002-01-22 Manufacturing method of semiconductor device
US (1) US6951774B2 (en)
JP (1) JP3839323B2 (en)
KR (1) KR100818423B1 (en)
TW (1) TWI286806B (en)
FR2857157B1 (en) * 2003-07-01 2005-09-23 3D Plus Sa Method for interconnecting active and passive components and heterogeneous component with low thickness therefrom
JP2005340761A (en) * 2004-04-27 2005-12-08 Seiko Epson Corp Packaging method of semiconductor device, circuit board, electro-optical device, and electronic apparatus
JP2011258757A (en) * 2010-06-09 2011-12-22 Toshiba Corp Semiconductor device
KR101696638B1 (en) * 2015-06-25 2017-01-16 크루셜텍 (주) Sensor package and method of manufacturing same
JP6489965B2 (en) * 2015-07-14 2019-03-27 新光電気工業株式会社 Electronic component device and manufacturing method thereof
JPH03106622A (en) * 1989-09-20 1991-05-07 Matsushita Electric Ind Co Ltd Semiconductor molding process
JP3572833B2 (en) * 1996-12-19 2004-10-06 株式会社デンソー Method for manufacturing resin-encapsulated semiconductor device
2002-01-22 JP JP2002012775A patent/JP3839323B2/en active Active
2002-03-04 US US10/086,717 patent/US6951774B2/en not_active Expired - Fee Related
2002-03-04 TW TW091103953A patent/TWI286806B/en not_active IP Right Cessation
2002-03-07 KR KR1020020012170A patent/KR100818423B1/en not_active IP Right Cessation
KR100818423B1 (en) 2008-04-01
TWI286806B (en) 2007-09-11
KR20020077650A (en) 2002-10-12
US6951774B2 (en) 2005-10-04
JP2002368190A (en) 2002-12-20
US20020151103A1 (en) 2002-10-17
JP2004281921A (en) 2004-10-07 Semiconductor device, electronic device, electronic apparatus, process for producing semiconductor device, and process for producing electronic device
US20040256443A1 (en) 2004-12-23 Ball grid array package with stacked center pad chips and method for manufacturing the same
US20060079023A1 (en) 2006-04-13 Semiconductor device and manufacturing method for the same
JPWO2002103793A1 (en) 2004-10-07 Semiconductor device and manufacturing method thereof
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