Source: http://www.google.com/patents/USRE42139?dq=5319712
Timestamp: 2017-11-18 22:19:44
Document Index: 472690400

Matched Legal Cases: ['Application No. 11', 'Application No. 2007', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 2007', 'Application No. 2009', 'Application No. 2009']

Patent USRE42139 - Method of fabricating a semiconductor device - Google Patents
A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate,...http://www.google.com/patents/USRE42139?utm_source=gb-gplus-sharePatent USRE42139 - Method of fabricating a semiconductor device
Publication number USRE42139 E1
Application number US 12/418,280
Also published as US6335231, US6803264, US7473592, US7473971, US7476576, US7638805, US7642598, US8405090, US9070604, US20020137265, US20050009252, US20070184632, US20080054269, US20080067596, US20080070335, US20080113487, US20080113488, US20090236698, USRE42097, USRE42241
Publication number 12418280, 418280, US RE42139 E1, US RE42139E1, US-E1-RE42139, USRE42139 E1, USRE42139E1
Patent Citations (212), Non-Patent Citations (54), Referenced by (7), Classifications (28), Legal Events (3)
US RE42139 E1
a supporting substrate comprising single crystalline silicon;
an insulating layer comprising silicon oxide at a surface of the supporting substrate;
an island-like single crystalline semiconductor layer comprising silicon formed on an the insulating layercomprising silicon oxide over a supporting substrate , the single crystalline semiconductor layer having at least a channel formation region and source and drain regions;
etching stopperssilicon oxide films formed on side surfaces of the gate electrode;
side walls formed adjacent to the side surfaces of the gate electrode with the etching stoppers silicon oxide films interposed therebetween; and
wherein the island-like single crystalline semiconductor layer comprises part of a single crystalline semiconductor substrate different from the supporting substrate.
side walls comprising silicon nitride formed adjacent to the side surfaces of the gate electrode with the etching stoppers silicon oxide films interposed therebetween, respectively; and
wherein an upper surface of the gate electrode and at least a part of the source and drain regions comprise a metal silicide, and
an insulating layer at a surface of the supporting substrate;
a single crystalline semiconductor layer comprising silicon formed on an the insulating layerover a supporting substrate , the single crystalline semiconductor layer having at least a channel formation region and source and drain regions;
wherein the single crystalline semiconductor layer comprises part of a single crystalline semiconductor substrate different from the supporting substrate.
an insulating film comprising silicon nitride oxide formed over the single crystalline semiconductor layer and the gale electrode,
a single crystalline semiconductor layer comprising silicon formed on an the insulating layer, the single crystalline semiconductor layer having at least a channel formation region and source and drain regions;
side walls formed adjacent to the side surfaces of the gate electrode with the etching stoppers silicon oxide films interposed therebetween;
a second electrode formed on the second flattening insulating film; and a third flattening insulating film formed over the second electrode and the second flattening insulating film,
an island-like single crystalline semiconductor layer comprising silicon on the insulating layer, the island-like single crystalline semiconductor layer having at least a channel formation region and source and drain regions;
a gate electrode comprising poly silicon formed over the channel formation region;
silicon oxide films formed on side surfaces of the gate electrode;
side walls comprising silicon nitride formed adjacent to the side surfaces of the gate electrode with the silicon oxide films interposed therebetween, respectively; and
a single crystalline semiconductor layer comprising silicon formed on the insulating layer, the single crystalline semiconductor layer having at least a channel formation region and source and drain regions;
This application is a Reissue application of U.S. application Ser. No. 11/731,415 filed Mar. 30, 2007 (now U.S. Pat. No. 7,473,971 issued Jan. 6, 2009 ) which is a continuation of U.S. application Ser. No. 10/914,357, filed on Aug. 9, 2004, now U.S. Pat. No. 7,476,576, issued Jan. 13, 2009, which is a continuation of U.S. application Ser. No. 09/808,162, filed on Mar. 13, 2001 (now U.S. Pat. No. 6,803,264 issued Oct. 12, 2004) which is a divisional of U.S. application Ser. No. 09/386,782, filed on Aug. 31, 1999 (now U.S. Pat. No. 6,335,231 issued Jan. 1, 2002), and claims the benefit of a foreign priority application filed in Japan as Serial No. 10- 251635 on Sep. 4, 1998. This application claims priority to each of these prior applications.
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U.S. Classification 257/347, 257/E21.563
International Classification H01L21/30, H01L29/786, H01L27/12, H01L21/336, H01L21/762, H01L21/02
Cooperative Classification H01L29/045, H01L27/1214, H01L21/76254, H01L27/1266, H01L21/76256, H01L21/76243, Y10S438/973, Y10S438/977, H01L29/78603, H01L27/1203, H01L29/66772
European Classification H01L21/762D8B, H01L29/786A, H01L29/04B, H01L21/762D2, H01L29/66M6T6F15C, H01L27/12B, H01L21/762D8D, H01L27/12T, H01L27/12T30A2