Source: http://www.google.com/patents/US6455914?dq=2040248
Timestamp: 2015-05-29 20:19:28
Document Index: 22593155

Matched Legal Cases: ['art 200', 'art 200', 'art 200', 'art 200', 'art 400', 'art 400', 'art 400', 'art 400', 'art 400']

Patent US6455914 - Pedestal fuse - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the...http://www.google.com/patents/US6455914?utm_source=gb-gplus-sharePatent US6455914 - Pedestal fuseAdvanced Patent SearchPublication numberUS6455914 B2Publication typeGrantApplication numberUS 09/842,545Publication dateSep 24, 2002Filing dateApr 26, 2001Priority dateApr 29, 1999Fee statusLapsedAlso published asUS6261873, US6492207, US20010031516, US20010034084Publication number09842545, 842545, US 6455914 B2, US 6455914B2, US-B2-6455914, US6455914 B2, US6455914B2InventorsDennis P. Bouldin, Timothy H. Daubenspeck, William T. MotsiffOriginal AssigneeInternational Business Machines CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (9), Non-Patent Citations (2), Referenced by (1), Classifications (10), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetPedestal fuse
US 6455914 B2Abstract
What is claimed is: 1. A metallization structure formed on a semiconductor substrate, comprising:
an insulator structure formed on the substrate, said insulator structure having an upper layer and a lower layer, said upper layer being thinner than said lower layer, said insulator structure having a plurality of openings therein of varying depth; and a metal structure inlaid in said insulator structure, said metal structure having first and second portions and a third portion there between that is substantially more resistive than said first and second portions, said third portion having a thickness that is substantially similar to the thickness of said upper layer of said insulator structure. 2. The structure according to claim 1 wherein said upper layer comprises a nitride layer and said lower layer comprises an oxide layer.
Thickness of fuse
Thick LM
Thin LM
FIG. 1A illustrates a semiconductor structure including resist segments 102 a, 102 b and 102 c formed on a thin upper nitride layer 104 which overlays an inter layer dielectric (ILD) oxide layer 106 which in turn overlays last metal minus 1 (LM-1) layer segments 108 a and 108 b. From step 204, flowchart 200 can continue with step 206. In step 206, the nitride layer and oxide layer can be etched to create a “line” trench, and the resist layer can be stripped. The structure formed by step 206 is depicted in FIG. 1B.
FIG. 1B illustrates the semiconductor structure of FIG. 1A following etching of the nitride and oxide layers 104 and 106, yielding oxide layer 106 a including exemplary line trenches and pedestals. Nitride 104 is etched leaving nitride segments 104 a, 104 b and 104 c remaining capping the pedestals of oxide layer 106 a, formed by stripped resist segments 102 a, 102 b and 102 c. LM-1 segments 108 a and 108 b remain overlaid by the oxide ILD layer 106 a. From step 206, flowchart 200 can continue with step 208. In step 208, resist can be applied and an image can be opened using a mask or reticle over resist segments and interrupted center pedestal oxide segment, leaving uncovered the interrupted center pedestal oxide segment and covering the other oxide pedestal portions where the nitride layer will be retained. The resulting structure of the material is illustrated in FIG. 1C.
FIG. 1C illustrates the semiconductor structure of FIG. 1B following application of resist segments 110 a and 110 b and opening an image mask over interrupted center oxide segment of oxide 106 a having nitride segment cap 104 b, leaving resist segments 110 a and 110 b , protecting nitride segment caps 104 a and 104 c, respectively. LM-1 segments 108 a and 108 b remain overlaid by the oxide ILD layer 106 a. Photoresist can be dispensed with a wafer structure stationary or rotating. A uniform resist thickness is preferred.
FIG. 1D illustrates the semiconductor structure of FIG. 1C following etching of interrupted nitride cap segment 104 b of oxide 106 a, and stripping of resist segments 110 a and 110 b , leaving exposed the center pedestal portion of oxide 106 a and nitride caps 104 a and 104 c. LM-1 segments 108 a and 108 b remain overlaid by the oxide ILD layer 106 a. From step 210, flowchart 200 can continue with step 212. In step 212, resist can be applied and an image can be opened using a mask for defining vias to the LM-1 layer forming resist segments leaving uncovered the intended locations of the vias and covering the center pedestal portion of the oxide and the two nitride capped pedestals. The resulting structure formed by step 212 is illustrated in FIG. 1E.
FIG. 1E illustrates the semiconductor structure of FIG. 1D following application of resist segments 112 a, 112 b and 112 c over pedestals portions of oxide 106 b including nitride cap segments 104 a and 104 c and opening an image mask so as to leave uncovered by resist portions of oxide 106 a intended as locations of vias to LM-1 segments 108 a and 108 b. LM-1 segments 108 a and 108 b remain overlaid by the oxide ILD layer 106 a. From step 212, flowchart 200 can continue with step 214. In step 214, the oxide segments intended as locations of vias to LM-1 can be selectively etched away and the resist segments can then be stripped away, leaving a structure include vias and line trenches ready for a damascene metallization fill. Various etching techniques can be used including, e.g., wet etching and dry etching. Wet etching can use various mixtures of hydrofluoric acid and water (e.g., 10:1, 6:1, 100:1), and can include a buffering agent such as ammonium fluoride for a slower, more controlled etch rate. Although relatively inexpensive, wet etching can also lead to severe undercutting since it is an isotropic process, i.e. proceeding at nearly equal rates in all directions, which can make it impractical. To avoid encroachment, dry, or plasma etch technology, using, e.g., a glow discharge to ionize an inert gas (i.e. reactive ion etching (RIE)physical sputtering) can be used to set up very anisotropically (i.e. directional) etched features, providing for higher circuit densities. When multiple layers are involved in dry etching process, such as silicon nitride over silicon dioxide, it is important to know the relative etch rates of the two materials in the available etchants. This “selectivity” will determine if significant etching of underlying layers will occur. Plasma etch processes, since they are basically chemical by nature exhibit better selectivity as compared to RIE physical sputtering processes. To etch the oxide layer using plasma etch CF4, CHF3 and NF3 gases can be used, for example, with an etch rate of greater than 5000 angstrom per minute. The resulting structure formed by step 214 is illustrated in FIG. 1F.
FIG. 3A illustrates a semiconductor structure including resist segments 302 a, 302 b and 302 c formed on a thin upper nitride layer 304 which overlays an inter layer dielectric (ILD) oxide layer 306 which in turn overlays last metal minus 1 (LM-1) layer segments 308 a and 308 b. From step 404, flowchart 400 can continue with step 406. In step 406, the nitride layer and oxide layer can be etched to create a “line” trench, and the resist layer can be stripped. The structure formed by step 406 is depicted in FIG. 3B.
FIG. 3B illustrates the semiconductor structure of FIG. 3A following etching of the nitride and oxide layers 304 and 306, yielding oxide layer 306 a including exemplary line trenches and pedestals. Nitride 304 is etched leaving nitride segments 304 a, 304 b and 304 c remaining capping the pedestals of oxide layer 306 a, formed by stripped resist segments 302 a, 302 b and 302 c. LM-1 segments 308 a and 308 b remain overlaid by the oxide ILD layer 306 a. From step 406, flowchart 400 can continue with step 408. In step 408, resist can be applied and an image can be opened using a mask or reticle over resist segments and interrupted center pedestal oxide segment, leaving uncovered the interrupted It center pedestal oxide segment and covering the other oxide pedestal portions where the nitride layer will be retained. The resulting structure of the material is illustrated in FIG. 3C.
FIG. 3C illustrates the semiconductor structure of FIG. 3B following application of resist segments 310 a and 310 b and opening an image mask over interrupted center oxide segment of oxide 306 a having nitride segment cap 304 b, leaving resist segments 310 a and 310 b, protecting nitride segment caps 304 a and 304 c, respectively. LM-1 segments 308 a and 308 b remain overlaid by the oxide ILD layer 306 a. From step 408, flowchart 400 can continue with step 410. In step 410, the technique can selectively etch the exposed oxide layer forming vias to the LM-1 layer, leaving exposed the nitride cap segment protecting the center pedestal oxide segment, and leaving covered the two other pedestal portions of the oxide and their two nitride caps. The resulting structure formed by step 410 is illustrated in FIG. 3D.
FIG. 3D illustrates the semiconductor structure of FIG. 3C following selective etching of oxide 306 a forming vias to LM-1 segments 308 a and 308 b. Resist segments 310 a and 310 b protect pedestal portions of oxide 306 b and 306 d and nitride cap segments 304 a and 304 c, and LM-1 segments 308 a and 308 b are overlaid by the oxide ILD layer segments 306 b and 306 d. From step 410, flowchart 400 can continue with step 412. In step 412, the center nitride cap segment over the center interrupt oxide pedestal can be selectively etched away and the resist layer can then be stripped away. The center nitride cap segment, if sufficiently thin, can be etched without a selective etchant. It will be apparent to those skilled in the art that the oxide layer segments 306 b and 306 d could be etched if not covered by resist segments 310 a and 310 b, as shown in FIG. 3E. The resulting structure formed by step 412 is illustrated in FIG. 3E.
FIG. 3E illustrates the semiconductor structure of FIG. 3D following etching of interrupted nitride cap segment 304 b of center pedestal oxide 306 c. LM-1 segments 308 a and 308 b remain overlaid by the oxide ILD layer segments 306 b and 306 c. From step 412, flowchart 400 can continue with step 414. In step 414, the resist is stripped away, including resist segments 310 a and 310 b, leaving the structure ready for damascene fill. The resulting structure includes vias and line trenches ready for a damascene metallization fill. The resulting structure formed by step 414 after damascene filling is illustrated in FIG. 3F.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4329706Mar 1, 1979May 11, 1982International Business Machines CorporationDoped polysilicon silicide semiconductor integrated circuit interconnectionsUS4873506Mar 9, 1988Oct 10, 1989Cooper Industries, Inc.Metallo-organic film fractional ampere fuses and method of makingUS5169802Jun 17, 1991Dec 8, 1992Hewlett-Packard CompanyInternal bridging contactUS5360988Jun 23, 1992Nov 1, 1994Hitachi, Ltd.Semiconductor integrated circuit device and methods for production thereofUS5420455Mar 31, 1994May 30, 1995International Business Machines Corp.Array fuse damage protection devices and fabrication methodUS5523253Feb 16, 1995Jun 4, 1996International Business Machines Corp.Array protection devices and fabrication methodUS5663590Jul 31, 1996Sep 2, 1997Lsi Logic CorporationProduct of process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional stepsUS5780919 *May 21, 1996Jul 14, 1998Quicklogic CorporationElectrically programmable interconnect structure having a PECVD amorphous silicon elementUS5960254Apr 10, 1997Sep 28, 1999International Business Machines CorporationMethods for the preparation of a semiconductor structure having multiple levels of self-aligned interconnection metallization* Cited by examinerNon-Patent CitationsReference1IBM Technical Disclosure Bulletin, vol. 32, No. 3, Aug. 1989, pp. 438-439, "Fuse Structure for Wide Fuse Materials Choice".2IBM Technical Disclosure Bulletin, vol. 32, No. 8A, Jan. 1990, pp. 218-219, "Method To Incorporate Three Sets of Pattern Information In Two Photomasking Steps".Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6991971 *Sep 30, 2003Jan 31, 2006International Business Machines CorporationMethod for fabricating a triple damascene fuse* Cited by examinerClassifications U.S. Classification257/529, 257/536, 257/762, 257/E23.15, 257/752, 257/537International ClassificationH01L23/525Cooperative ClassificationH01L2924/0002, H01L23/5258European ClassificationH01L23/525F4Legal EventsDateCodeEventDescriptionNov 16, 2010FPExpired due to failure to pay maintenance feeEffective date: 20100924Sep 24, 2010LAPSLapse for failure to pay maintenance feesMay 3, 2010REMIMaintenance fee reminder mailedNov 18, 2005FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services