Source: http://www.google.com/patents/US6920145?dq=6,357,003
Timestamp: 2016-07-24 02:56:02
Document Index: 417019976

Matched Legal Cases: ['arts 1', 'art 4', 'art 1', 'arts 1', 'arts 3', 'art 4', 'art 3', 'art 3', 'art 4', 'art 1', 'art 4']

Patent US6920145 - Packet switch device and scheduling control method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA packet switch device having a plurality of input buffers; a packet switch; a plurality of schedulers, having a pipeline scheduling process module wherein a plurality of time units corresponding to the number of output lines is spent in scheduled sending process of the fixed length packets from the...http://www.google.com/patents/US6920145?utm_source=gb-gplus-sharePatent US6920145 - Packet switch device and scheduling control methodAdvanced Patent SearchPublication numberUS6920145 B2Publication typeGrantApplication numberUS 09/759,181Publication dateJul 19, 2005Filing dateJan 12, 2001Priority dateJan 12, 2000Fee statusPaidAlso published asDE60113312D1, EP1117213A2, EP1117213A3, EP1117213B1, US20010007562Publication number09759181, 759181, US 6920145 B2, US 6920145B2, US-B2-6920145, US6920145 B2, US6920145B2InventorsNaoki Matsuoka, Hiroshi Tomonaga, Kenichi KawaraiOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (4), Non-Patent Citations (4), Referenced by (33), Classifications (16), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetPacket switch device and scheduling control method
Referring to FIG. 2 which shows the overall configuration of a packet switch device as one embodiment of the present invention, an input buffer type packet switch device comprises: a plurality of (N) input buffer parts 1, a packet switch of input N�output M matrix (common switch) 2, a plurality of (M) schedulers 3, and a result switching part 4.
Here, an input buffer part 1 of the N number of input buffer parts 1 are provided to each of the N input interface parts (Input INF in FIG. 5), which correspond to the plurality of (N) input lines (input route). The M scheduler parts 3 and the result switching part 4 constitute the scheduler (scheduling control device) 5. The plurality of (M) output lines (output route) from the packet switch of N�M matrix 2 is received by the output interface part (Output INF in FIG. 5).
Each scheduler part 3 corresponding to an output line comprises input highway (HW) for scheduling requested information and extended output highway (HW). By outputting scheduling requested information as the way it is received, requested information is notified to each scheduler part 3. Further, by providing, corresponding to each output line, the result switching part 4 to notify the input buffer part 1 of scheduling results, the result switching part 4 is formed which has a 1�N configuration consisting of one input highway, N output highway, and N extended input highway.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5517495 *Dec 6, 1994May 14, 1996At&T Corp.Fair prioritized scheduling in an input-buffered switchUS6611527 *Feb 3, 2000Aug 26, 2003Hitachi, Ltd.Packet switching apparatus with a common bufferUS6704312 *May 11, 2000Mar 9, 2004Cheng-Shang ChangSwitching apparatus and method using bandwidth decompositionJPH05181817A Title not available* Cited by examinerNon-Patent CitationsReference1Kawaeai, et al., "Terabit Switch Architecture Using Input Queing Technique" Sep. 1999; Proceedings of ICCC 99 vol. 15, No. 4, pp. 124-128, XP009023676.2Marsan, et al., "Scheduling in Input Queued Cell Based Packet Switches" Globecom 99, Dec. 1999 pp. 1227-1235, XP002269673.3McKeown, et al., "Tiny Tera: A Packet Switch Core" IEEE Micro, vol. 17, No. 1, 1997, pp. 26-33; XP000642693, ISSN:0272-1732.4Mekkitikul, "Scheduling Non Uniform Traffic in High Speed Packet Switches and Routers" Nov. 1998 XP002269673.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7436898 *Oct 14, 2003Oct 14, 2008Matsushita Electric Industrial Co., Ltd.Integrated circuit (IC) card, data transmission apparatus, data transmission method and computer program of data transmission methodUS7756134May 2, 2006Jul 13, 2010Harris CorporationSystems and methods for close queuing to support quality of serviceUS7769028Jun 21, 2006Aug 3, 2010Harris CorporationSystems and methods for adaptive throughput management for event-driven message-based dataUS7856012Jun 16, 2006Dec 21, 2010Harris CorporationSystem and methods for generic data transparent rules to support quality of serviceUS7894509May 18, 2006Feb 22, 2011Harris CorporationMethod and system for functional redundancy based quality of serviceUS7916626Mar 29, 2011Harris CorporationMethod and system for fault-tolerant quality of serviceUS7929548Jan 7, 2008Apr 19, 2011International Business Machines CorporationWeighted fair queue serving plural output portsUS7990860Aug 2, 2011Harris CorporationMethod and system for rule-based sequencing for QoSUS8064464Nov 22, 2011Harris CorporationMethod and system for inbound content-based QoSUS8300653Oct 30, 2012Harris CorporationSystems and methods for assured communications with quality of serviceUS8325609 *Dec 4, 2012Renesas Electronics CorporationData processing deviceUS8516153Jun 16, 2006Aug 20, 2013Harris CorporationMethod and system for network-independent QoSUS8730981Jun 20, 2006May 20, 2014Harris CorporationMethod and system for compression based quality of serviceUS20030081624 *Oct 24, 2002May 1, 2003Vijay AggarwalMethods and apparatus for packet routing with improved traffic management and schedulingUS20050053095 *Oct 14, 2003Mar 10, 2005Isao KatoIc card, data transfer device, data transfer method, and data transfer method programUS20050163107 *Jan 27, 2004Jul 28, 2005Gunturi Ravi P.Packet processing pipelineUS20070002172 *Aug 31, 2006Jan 4, 2007Calvignac Jean LLinking frame data by inserting qualifiers in control blocksUS20070258486 *May 2, 2006Nov 8, 2007Harris CorporationSystems and methods for close queuing to support quality of serviceUS20070291647 *Jun 19, 2006Dec 20, 2007Harris CorporationMethod and System for Fault-Tolerant Quality of ServiceUS20070291653 *Jun 16, 2006Dec 20, 2007Harris CorporationMethod and system for network-independent qosUS20070291656 *Jun 16, 2006Dec 20, 2007Harris CorporationMethod and system for outbound content-based QoSUS20070291657 *Jun 16, 2006Dec 20, 2007Harris CorporationMethod and system for rule-based sequencing for QoSUS20070291751 *Jun 20, 2006Dec 20, 2007Harris CorporationMethod and system for compression based quality of serviceUS20070291766 *Jun 16, 2006Dec 20, 2007Harris CorporationMethod and system for inbound content-based QoSUS20070291768 *Jun 16, 2006Dec 20, 2007Harris CorporationMethod and system for content-based differentiation and sequencing as a mechanism of prioritization for QOSUS20070297416 *Jun 21, 2006Dec 27, 2007Harris CorporationSystems and methods for adaptive throughput management for event-driven message-based dataUS20080013559 *Jul 14, 2006Jan 17, 2008Smith Donald LSystems and methods for applying back-pressure for sequencing in quality of serviceUS20080025215 *Aug 13, 2007Jan 31, 2008IbmMETHOD AND APPARATUS FOR IMPROVING THE FAIRNESS OF NEW ATTACHES TO A WEIGHTED FAIR QUEUE IN A QUALITY OF SERVICE (QoS) SCHEDULERUS20080025318 *Jul 31, 2006Jan 31, 2008Harris CorporationSystems and methods for dynamically customizable quality of service on the edge of a networkUS20080036176 *Aug 9, 2006Feb 14, 2008Schuettenberg Donald WFront Tow Extended SaddleUS20080107118 *Jan 7, 2008May 8, 2008Goetzinger William JWeighted fair queue serving plural output portsUS20100241759 *Jul 31, 2006Sep 23, 2010Smith Donald LSystems and methods for sar-capable quality of serviceUS20110026396 *Jul 30, 2010Feb 3, 2011Renesas Electronics CorporationData processing device* Cited by examinerClassifications U.S. Classification370/412, 370/415, 370/414International ClassificationH04L12/937, H04L12/931Cooperative ClassificationH04L49/508, H04L49/205, H04L49/503, H04L49/608, H04L2012/5679, H04L49/254, H04L49/30, H04L49/3063European ClassificationH04L49/25E1, H04L49/30G, H04L49/60GLegal EventsDateCodeEventDescriptionNov 17, 1999ASAssignmentOwner name: NEOPOST B.V., NETHERLANDSFree format text: CHANGE OF NAME;ASSIGNOR:HADEWE B.V.;REEL/FRAME:010404/0693Effective date: 19990705Jan 12, 2001ASAssignmentOwner name: FUJITSU LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MATSUOKA, NAOKI;TOMONAGA, HIROSHI;KAWARAI, KENICHI;REEL/FRAME:011459/0770;SIGNING DATES FROM 20001222 TO 20001226Dec 18, 2008FPAYFee paymentYear of fee payment: 4Dec 19, 2012FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services