Source: https://patents.google.com/patent/JP4907659B2/en
Timestamp: 2020-01-24 09:01:18
Document Index: 241186686

Matched Legal Cases: ['art 40', 'art 53', 'art 54', 'art 55', 'arts 53', 'art 52', 'art 49', 'art 49', 'art 53', 'art 57', 'arts 63', 'art 62', 'art 59', 'art 59', 'art 49', 'art 49', 'art 53', 'art 49', 'art 49', 'art 53', 'art 49', 'art 49', 'art 49', 'art 49', 'arts 93', 'art 92']

JP4907659B2 - Active matrix substrate, liquid crystal panel, display device, television receiver - Google Patents
Active matrix substrate, liquid crystal panel, display device, television receiver Download PDF
JP4907659B2
JP4907659B2 JP2008525797A JP2008525797A JP4907659B2 JP 4907659 B2 JP4907659 B2 JP 4907659B2 JP 2008525797 A JP2008525797 A JP 2008525797A JP 2008525797 A JP2008525797 A JP 2008525797A JP 4907659 B2 JP4907659 B2 JP 4907659B2
JP2008525797A
JPWO2008010334A1 (en
2006-07-19 Priority to JP2006197319 priority Critical
2006-07-19 Priority to JP2006197319 priority
2006-12-08 Priority to JP2006332592 priority
2007-03-30 Application filed by シャープ株式会社 filed Critical シャープ株式会社
2007-03-30 Priority to JP2008525797A priority patent/JP4907659B2/en
2007-03-30 Priority to PCT/JP2007/057049 priority patent/WO2008010334A1/en
2009-12-17 Publication of JPWO2008010334A1 publication Critical patent/JPWO2008010334A1/en
2012-04-04 Publication of JP4907659B2 publication Critical patent/JP4907659B2/en
The present invention relates to a display device such as a liquid crystal display device and various EL display devices, and an active matrix substrate used for them.
Active matrix substrates are widely used in active matrix display devices such as liquid crystal display devices and EL (Electro Luminescence) display devices. A general active matrix substrate has a plurality of scanning signal lines, a plurality of data signal lines, and TFTs (Thin Film Transistors) provided at intersections thereof in the display area. Then, a potential signal is appropriately transmitted from the data signal line to the pixel electrode. Also, each pixel area (display area) is provided with a storage capacitor wiring in order to prevent image degradation due to self-discharge during the TFT off period, TFT off current, or to transmit various modulation signals in the liquid crystal drive. There are also active matrix substrates.
Incidentally, the plurality of storage capacitor lines formed in the display area are connected to a common line (trunk line) in a non-display area provided around the display area. For example, in the conventional technique shown in FIGS. 37A and 37B, each auxiliary capacitance line 811 is formed of a conductive film in the same layer as the data line 804 through the contact hole 808 in the non-display region. Connected to the auxiliary storage capacitor line 813 (common wiring) (see Patent Documents 1 and 2). In addition, the following patent documents 3 and 4 can be mentioned as a related well-known literature.
Japanese Patent Publication “Japanese Laid-Open Patent Publication No. 2002-6773 (Released on January 11, 2002)” Japanese Patent Publication “Japanese Patent Laid-Open No. 10-319433 (published on December 4, 1998)” Japanese Patent Publication “Japanese Laid-Open Patent Publication No. 7-114044 (published on May 2, 1995)” Japanese Patent Publication “JP 7-287252 A (published October 31, 1995)”
Here, in the prior art, each auxiliary capacitance line 811 and the gate line 802 are formed in the same layer, and the aggregate auxiliary capacitance line 813 (common wiring) is formed in an upper layer (the same layer as the data line 804). In the non-display region, the aggregate storage capacitor line 813 intersects the gate line 802 (scanning signal line). Therefore, at this intersection, the storage auxiliary capacitance line 813 is formed on the gate line 802 via the insulating film 803, and in order to reliably prevent a short circuit between the gate line 802 and the storage auxiliary capacitance line 813. Therefore, the insulating film 803 in the non-display area is required to have a corresponding thickness.
On the other hand, when the thickness of the insulating film 803 is increased, the etching depth at the time of forming the contact hole is increased, and formation failure of the contact hole 808 due to variations in the film thickness and film quality of the insulating film 803 is likely to occur. For example, if the film thickness at the contact hole formation position is large, the holes are not completely opened during the etching of the insulating film, and there is a possibility that each auxiliary capacitance line 811 and the collective auxiliary capacitance line 813 are poorly connected.
In addition, the same problem occurs in a portion where each scanning signal line is connected to a lead wiring for external connection through a contact hole in the non-display area. That is, in order to surely prevent a short circuit between the lead-out wiring and another wiring (for example, the auxiliary storage capacitor line), the insulating film in the non-display area needs to have a corresponding thickness. As the thickness of the contact hole increases, the etching depth at the time of contact hole formation increases, and contact hole formation defects are likely to occur due to variations in the film thickness and film quality of the insulating film.
The present invention has been made in view of the above-described problems, and an object of the present invention is to accurately connect two wirings (for example, a storage capacitor wiring and a trunk wiring thereof) in a non-display region, An object of the present invention is to provide an active matrix substrate in which a short circuit with other wirings (for example, scanning signal lines) hardly occurs.
The active matrix substrate according to the present invention is an active matrix substrate including a plurality of storage capacitor wires and an insulating film covering them, and each storage capacitor wire is a trunk wire that is located above the insulating film in a non-display region. The insulating film has a portion penetrated in the contact hole (under the opening of the contact hole), and a film thickness of a region adjacent to the penetrated portion is It is characterized by being smaller. In addition, the active matrix substrate is provided in the same layer as two wirings connected through a contact hole provided in a non-display area and one of these wirings, and in the other wiring and the non-display area. An active matrix substrate having intersecting interconnections, wherein the insulating layer between the two interconnections includes a through-hole portion for forming the contact hole and a first film thickness portion in contact with the through-hole portion. And a second film thickness portion that is located at least at the portion where the other wiring and the cross wiring intersect, and is thicker than the first film thickness portion. For example, the two wirings are a storage capacitor wiring and its trunk wiring, and the cross wiring is a scanning signal line.
In the non-display region, a portion having a locally reduced thickness is formed in the insulating film in the non-display region, and the contact hole (retention capacitor wiring and trunk wiring is formed through a part (for example, the central portion). This is obtained by forming a contact hole connecting the two.
In this way, the insulating film in the non-display area can be short-circuited between the main wiring and other wiring (for example, the scanning signal line) if the contact hole forming position and its vicinity are thin and the other portions are thick. Thus, the main wiring can be connected to the storage capacitor wiring with high accuracy.
The active matrix substrate according to the present invention includes first and second transistors, a first pixel electrode connected to the first transistor, and a second transistor connected to the second transistor in each pixel region of the display region. An active matrix substrate having a pixel electrode, comprising: first and second storage capacitor lines passing through each pixel region; and an insulating film covering the first and second storage capacitor lines, and a non-display region The first storage capacitor wiring is connected to the first trunk wiring in the upper layer of the insulating film through the first contact hole, and the second storage capacitor wiring is in the upper layer of the insulating film. 2 is connected to the trunk wiring via a second contact hole, and the insulating film has a portion penetrated in the first contact hole (under the opening of the first contact hole). This The thickness of the region adjacent to the penetrated portion is reduced, and the second contact hole has a penetrated portion (under the opening of the second contact hole). It is characterized in that the film thickness of the region adjacent to the portion is small.
According to the present active matrix substrate, it is possible to form a plurality of regions having different luminances in one pixel region (multi-pixel driving) by individually controlling the potentials of the first and second storage capacitor lines. Even in this case, the above effect can be expected. In this case, the potentials of the first and second trunk lines may be controlled so that the phases of the respective potential waveforms are shifted from each other by 180 degrees.
Further, the first and second trunk lines are configured so that the potential increases or decreases after the first and second transistors are turned off, and the state continues until the transistors are turned off in the next frame. The potential may be controlled. That is, the potential of the first storage capacitor wiring is controlled so that the potential rises after the transistors are turned off and the state continues until the transistors are turned off in the next frame. The potential of the storage capacitor wiring is controlled so that the potential drops after each of the transistors is turned off and the state continues until the transistors are turned off in the next frame, or the first storage capacitor The potential of the wiring is controlled so that the potential drops after each of the transistors is turned off, and the state continues until the transistors are turned off in the next frame. The potential is controlled after the transistor is turned off, and the potential is controlled so that the state continues until the transistor is turned off in the next frame.
In this case, the increase in the potential of the first storage capacitor line and the decrease in the potential of the second storage capacitor line are shifted by one horizontal period, or the potential of the first storage capacitor line May fall from the rise of the potential of the second storage capacitor wiring by one horizontal period.
In the present active matrix substrate, the insulating film is a gate insulating film, and is adjacent to the first film thickness portion adjacent to the pierced portion and the first film thickness portion. The wirings connected to each contact hole are formed in different layers, and the entire intersection of the wirings is located within the outer periphery of the first film thickness part. Also good. In this way, by setting a larger portion under each trunk wiring as the first film thickness portion (portion where the gate insulating film is thin), the distance between each trunk wiring and the counter electrode is widened, and the parasitic capacitance between the both is increased. Can be reduced. Thereby, the dullness of the signal transmitted through each trunk wiring can be suppressed. In this configuration, in the non-display region, the second storage capacitor line connected to the second trunk line also intersects with the first trunk line, and the second storage capacitor line and the first trunk line Although the portion where the second storage capacitor wiring and the first trunk wiring intersect with each other is located in the outer periphery of the first film thickness portion, It is desirable to be the same as the film thickness part (the part where the gate insulating film is thick). By doing so, it is possible to prevent a short circuit between the second storage capacitor wiring and the first trunk wiring while obtaining the above-described effect.
An active matrix substrate according to the present invention is an active matrix substrate having a plurality of scanning signal lines and an insulating film covering them, and each scanning signal line is a lead-out wiring located above the insulating film in a non-display region. The insulating film has a portion penetrated in the contact hole (under the opening of the contact hole), and the film thickness of a region adjacent to the penetrated portion is It is characterized by being smaller.
In the non-display region, the insulating film is formed with a portion having a thickness smaller than that of the periphery, and part of the insulating film (for example, the central portion) is penetrated to contact the contact hole (a contact hole for connecting the scanning signal line and the lead wiring). ) Is obtained.
As described above, in the insulating film in the non-display area, if the contact hole formation position is thin and the other portions are thick, the lead-out wiring and other wiring (for example, the storage capacitor wiring) are surely short-circuited. While avoiding this, the lead-out wiring and the scanning signal line can be connected with high accuracy.
In the active matrix substrate according to the present invention, the insulating film is adjacent to the first film thickness portion corresponding to the region and the second film thickness larger than the first film thickness portion. A part. In the above structure, the first film thickness portion having a smaller film thickness than the surrounding (second film thickness portion) is formed in the insulating film located in the non-display area, and a part of the first film thickness portion (for example, the center) And the contact hole is formed through the part). The first film thickness portion is preferably formed so as to surround the penetrating portion, and the second film thickness portion is formed at least at the intersection of the main wiring and the other wiring in the non-display area. It ’s fine.
In the present active matrix substrate, the insulating layer may be a gate insulating film, and the gate insulating film is composed of a plurality of gate insulating layers, and at least one gate insulating layer is formed thin in the thin film portion. It doesn't matter. The gate insulating film may be composed of a plurality of gate insulating layers, and may have one or more gate insulating layers in the thin film portion and more gate insulating layers in other portions.
In this case, at least one gate insulating layer may be a planarizing film. In this way, the level difference at the intersection of the scanning signal line and the data signal line is reduced, and the level difference between the data signal line and the scanning signal line is reduced. Therefore, disconnection of the data signal line at the signal line intersection is unlikely to occur. Become. For example, when a SiNx (silicon nitride) film is used as one of the gate insulating layers, the density at the taper portion of the gate electrode is lower than other regions (film quality is reduced), and the SiNx is destroyed due to static electricity. Cheap. Here, if a planarizing film is used for any of the plurality of gate insulating layers, the thickness of the insulating film can be secured even in the tapered portion, and the SiNx film can be prevented from being broken.
In the present active matrix substrate, the gate insulating film may include a gate insulating layer containing an organic substance. Examples of materials containing organic substances include SOG (spin-on glass) materials, acrylic resin materials, epoxy resins, polyimide resins, polyurethane resins, polysiloxane resins, and novolac resins. Since these materials can be formed by coating on a substrate, it is relatively easy to increase the thickness on the order of microns. For this reason, the distance between the conductive layer or the storage capacitor wiring connected to the scanning signal line and the other wiring can be increased, and a short circuit can be hardly generated.
In the other portions, the lowermost gate insulating layer is preferably a planarizing film. Furthermore, it is preferable that the thickness of the portion in contact with the substrate surface of the planarizing film is larger than the thickness of the gate electrode formed on the substrate surface. In this way, the planarization effect is improved, and the occurrence of a short circuit between the signal lines can be further suppressed. Further, disconnection of the data signal line is less likely to occur.
The lowermost gate insulating layer is preferably a planarizing film (SOG film) made of a spin-on glass (SOG) material. Thus, the second gate insulating layer, the high resistance semiconductor layer, and the low resistance semiconductor layer can be continuously formed on the SOG film as the first gate insulating layer by a CVD method or the like. As a result, the manufacturing process can be shortened. In this case, the SOG film may be removed from the thin film portion, and the SOG film may be formed in the lowermost layer of other portions. Further, if the vicinity of the edge of the thin film portion in the gate insulating film is formed in a forward tapered shape, each electrode formed in the upper layer is difficult to be disconnected.
In the present active matrix substrate, a plurality of the contact holes may be formed. Thus, by forming a plurality of contact holes, contact redundancy can be obtained, and the occurrence of contact failure can be further suppressed. In the contact hole, a connection electrode for connecting the storage capacitor line and the main line may be formed. By doing so, the area of the contact hole portion can be reduced, so that the area of the non-display region can be reduced. Thereby, the active matrix substrate can be reduced in size. In this case, the connection electrode may be formed of the same material as the pixel electrode in the display area. In this case, since the connection electrode can be formed simultaneously with the formation of the pixel electrode, the manufacturing process of the active matrix substrate can be simplified. The trunk wiring may be formed of the same material as the data signal line in the display area. In this way, the trunk wiring can be formed simultaneously with the formation of the data signal line, and the manufacturing process of the active matrix substrate can be simplified.
The active matrix substrate may include first and second interlayer insulating films above the gate insulating layer, and the contact hole may penetrate the gate insulating film and the first and second interlayer insulating films. In this case, an in-pixel contact hole that connects the transistor and the pixel electrode may be formed in each pixel region, and the gate insulating film under the in-pixel contact hole may have the same structure as the second film thickness portion. This makes it difficult for the transistor (its drain electrode) and the storage capacitor wiring to be short-circuited in the pixel region, thereby suppressing the occurrence of defective pixels.
In the above configuration, it is preferable that both wirings connected by the contact hole in the non-display area are formed in different layers, and the entire intersection of both wirings is located within the outer periphery of the first film thickness portion. In this way, the difference (thickness difference) between the thickness of the second interlayer insulating film in the contact hole portion of the non-display region and the thickness of the second interlayer insulating film in the contact hole portion in the pixel can be reduced, and the manufacturing process can be performed. Can be simplified (shortened). For example, at the intersection, the distance between the edge of the wiring located on the lower layer side of both wirings and the edge of the first film thickness portion is set to 60 μm or more. By doing so, the difference in film thickness can be made about 0.1 to 0.2 μm, so that both contact holes can be formed with the same exposure amount. As a result, the possibility that the second interlayer insulating film remains and contact failure occurs can be reduced.
In the present active matrix substrate, the gate insulating film may include a thin film portion having a small film thickness in a region overlapping with the storage capacitor wiring in each pixel region. In this way, the capacitance can be determined predominantly at the position where the storage capacitor wiring and the thin film portion overlap, and the influence of the finish of the storage capacitor wiring on the capacitance variation is reduced.
In this active matrix substrate, the gate insulating film has a thin film portion with a reduced thickness in a portion overlapping with the gate electrode of the transistor in each pixel region, and the thin film portion and the source electrode of the transistor The overlapping area may be smaller than the overlapping area between the thin film portion and the drain electrode of the transistor. In this way, it is possible to suppress the occurrence of a short circuit between signal lines (between the data signal line and the scanning signal line) that is not easily corrected while maintaining the characteristics of the transistor.
The liquid crystal panel of the present invention is a liquid crystal panel comprising the active matrix substrate and a counter substrate facing the active matrix substrate, and a spacer and a liquid crystal layer provided between the substrates, wherein the insulating film is a gate insulating film. The spacer includes a first spacer disposed in the display region and a second spacer disposed in the non-display region, and includes a gate insulating film structure below the first spacer and a second spacer. The gate insulating film structure is the same.
Thus, by setting the gate insulating film structure below the spacer between the non-display region and the display region, the height of the first and second spacers can be easily set, and the cell gap between the display region and the non-display region is facilitated. Can be reduced. Thereby, it is possible to suppress the occurrence of luminance unevenness in the vicinity of the boundary between the display area and the non-display area.
In the present liquid crystal panel, the gate insulating film has a first film thickness portion adjacent to the pierced portion and a film thickness from the first film thickness portion adjacent to the first film thickness portion. It is preferable that the portion below the second spacer is the second film thickness portion. This is because the second film thickness portion has a thick gate insulating film, and a planarization effect can be obtained by using an SOG material or the like for the gate insulating film. The gate insulating film has one or more gate insulating layers in the first film thickness portion and more gate insulating layers in the second film thickness portion than the first film thickness portion. In the film thickness portion, any one of the gate insulating layers may be a planarizing film.
In the present liquid crystal panel, each of the first and second spacers is provided so as to overlap only one metal wiring covered with the gate insulating film, and the one metal wiring is a scanning signal line or a storage capacitor wiring. May be.
Thus, by making the stacked structure under the spacer similar between the non-display area and the display area, it becomes easier to set the height of the first and second spacers, and the cell gap between the display area and the non-display area is reduced. The difference can be made smaller.
In the present liquid crystal panel, the first spacer is provided so as to overlap the intersection of the data signal line and the scanning signal line on the gate insulating film or the intersection of the data signal line and the storage capacitor line. The second spacer may be provided so as to overlap an intersection portion between the trunk wiring and the scanning signal line or an intersection portion between the trunk wiring and the storage capacitor wiring.
In the present liquid crystal panel, it is preferable that the relative dielectric constant of at least the second spacer is smaller than the average relative dielectric constant of the liquid crystal material in the liquid crystal layer. In this way, when the second spacer is installed on any of the trunk wirings, the parasitic capacitance between the trunk wiring and the counter substrate (electrode) is reduced, and the blunting of the signal transmitted through the trunk wiring is suppressed. it can.
In the present liquid crystal panel, an interlayer insulating film may be formed between the gate insulating film and the liquid crystal layer, and the interlayer insulating film may include a layer containing an organic substance. An interlayer insulating film containing an organic substance is more elastic than inorganic films such as SiNx and SiO2. Therefore, in the configuration in which the spacers in the display region and the non-display region are formed on the counter substrate side and the spacers are in contact with the active matrix substrate, if an interlayer insulating film containing an organic substance is disposed, the elastic deformation causes There is an effect that the thickness variation of the color filter layer and the black matrix on the counter substrate side, the variation of the spacer height, or the thickness variation of the active matrix substrate is absorbed. Note that an acrylic resin, an epoxy resin, a polyimide resin, a polyurethane resin, a polysiloxane resin, a novolac resin, or the like can be used for the interlayer insulating film containing an organic substance.
The present liquid crystal panel is a liquid crystal panel comprising the active matrix substrate and a counter substrate opposite to the active matrix substrate, and a spacer and a liquid crystal layer provided between the substrates, wherein the spacer is disposed in the display area. A second spacer is provided so as to overlap a portion where the second storage capacitor wiring and the first trunk wiring intersect with each other. The gate insulating film structure under the first spacer is the same as the gate insulating film structure under the second spacer, and the second spacer has a relative dielectric constant smaller than that of the liquid crystal material in the liquid crystal layer. To do.
Further, in order to prevent a short circuit between the first trunk wiring and the second storage capacitor wiring, if the intersecting portion thereof is a second film thickness portion (a portion where the gate insulating film is thick), the first trunk wiring and The distance between the opposing substrates is reduced, and the parasitic capacitance between the two is increased. Therefore, by arranging a spacer having a relative dielectric constant smaller than the average relative dielectric constant of the liquid crystal material on this intersecting portion, this parasitic capacitance can be reduced.
In the present liquid crystal panel, it is preferable that the first spacer is provided so as to overlap an intersection portion of the data signal line and the scanning signal line or any one of the storage capacitor lines in the upper layer of the gate insulating film.
The present liquid crystal panel is a liquid crystal panel comprising the active matrix substrate and a counter substrate facing the active matrix substrate, and a spacer and a liquid crystal layer provided between the substrates, wherein the insulating film is a gate insulating film. The spacer includes a first spacer disposed in the display region and a second spacer disposed in the non-display region, and includes a gate insulating film structure below the first spacer and a gate below the second spacer. The insulating film structure is the same.
In addition, a display device of the present invention includes the above active matrix substrate.
According to another aspect of the present invention, there is provided a television receiver including the display device and a tuner unit that receives a television broadcast.
As described above, with respect to the insulating film in the non-display region, the formation position of the contact capacitor connecting the storage capacitor wiring and the trunk wiring is made thin, and other portions are made thick so that the trunk wiring and the other wiring are The trunk wiring and the storage capacitor wiring can be accurately connected while reliably avoiding a short circuit. Also, by making the formation position of the contact hole connecting the scanning signal line and the lead-out wiring thin and making the other portions thick, the lead-out wiring and the other wiring can be reliably avoided while short-circuiting the lead-out wiring. And the scanning signal line can be connected with high accuracy.
It is a top view which shows the structure of the active matrix substrate which concerns on this Embodiment. It is sectional drawing which shows the cross section of A1-A2 of FIG. It is a top view which shows the other structure of this active matrix substrate. It is sectional drawing which shows the cross section of A3-A4 of FIG. It is a top view which shows the other structure of this active matrix substrate. It is a top view which shows the other structure of this active matrix substrate. It is sectional drawing which shows the cross section of B1-B2 of FIG. It is sectional drawing which shows the cross section of B3-B4 of FIG. It is a top view which shows the structure of the contact hole of this active matrix substrate. 9 is a graph showing the relationship between the distance d shown in FIGS. 7 and 8 and the difference (film thickness difference) between T1 and T2. It is sectional drawing which shows the structure of the liquid crystal panel which concerns on this Embodiment. It is a block diagram which shows the control structure of the liquid crystal panel which concerns on this Embodiment. It is a block diagram which shows the structure of the television receiver which concerns on this Embodiment. It is a perspective view which shows the structure of the television receiver which concerns on this Embodiment. 6 is a timing chart showing a method for driving the active matrix substrate shown in FIG. 5. 6 is a timing chart showing another driving method of the active matrix substrate shown in FIG. 5. It is a timing chart which shows the other drive method of this active matrix substrate. FIG. 6 is a plan view showing a modification of the active matrix substrate shown in FIG. 5. It is a top view which shows the structure of the liquid crystal panel using the active matrix substrate shown in FIG. FIG. 20 is a cross-sectional view of the display area of the liquid crystal panel shown in FIG. 19 and a cross-sectional view of the non-display area. FIG. 20 is a plan view illustrating a modification of the liquid crystal panel illustrated in FIG. 19. FIG. 22 is a cross-sectional view taken along the line arrow of the display area of the liquid crystal panel shown in FIG. 21 and a cross-sectional view taken along the line arrow of the non-display area. FIG. 20 is a plan view illustrating a modification of the liquid crystal panel illustrated in FIG. 19. FIG. 24 is a cross-sectional view taken along line arrow of the display area of the liquid crystal panel shown in FIG. 23 and a cross-sectional view taken along line arrow of the non-display area. FIG. 20 is a plan view illustrating a modification of the liquid crystal panel illustrated in FIG. 19. FIG. 26 is a cross-sectional view taken along line arrow of the display area of the liquid crystal panel shown in FIG. 25 and a cross-sectional view taken along line arrow of the non-display area. FIG. 20 is a plan view illustrating a modification of the liquid crystal panel illustrated in FIG. 19. FIG. 28 is a cross-sectional view taken along line arrow of the display area of the liquid crystal panel shown in FIG. 27 and a cross-sectional view taken along line arrow of the non-display area. FIG. 20 is a plan view illustrating a modification of the liquid crystal panel illustrated in FIG. 19. FIG. 30 is a cross-sectional view taken along line arrow of the display area of the liquid crystal panel shown in FIG. 29 and a cross-sectional view taken along line arrow of the non-display area. FIG. 20 is a plan view illustrating a modification of the liquid crystal panel illustrated in FIG. 19. FIG. 32 is a cross-sectional view of the display area of the liquid crystal panel shown in FIG. It is a top view which shows the structure of the liquid crystal panel using the active matrix substrate shown in FIG. FIG. 34 is a cross-sectional view taken along line arrow of the display area of the liquid crystal panel shown in FIG. 33 and a cross-sectional view taken along line arrow of the non-display area. It is a top view which shows the structure of the liquid crystal panel using the active matrix substrate shown in FIG. FIG. 36 is a cross-sectional view taken along line arrow of the display area of the liquid crystal panel shown in FIG. 35 and a cross-sectional view taken along line arrow of the non-display area. It is a top view which shows the structure of the conventional active matrix substrate. FIG. 38 is a cross-sectional view of the active matrix substrate shown in FIG.
7 Drain extraction electrode 8 Drain electrode 9 Source electrode 10 10x 10y 10z Active matrix substrate 11 48 68 Contact hole 12 TFT (transistor)
DESCRIPTION OF SYMBOLS 15 Data signal line 16 Scan signal line 17 Pixel electrode 18 Retention capacity wiring 21 1st gate insulating layer 22 2nd gate insulating layer 31 57 Thin film part 40 Gate insulating film 44 Display area 50 Cs trunk wiring 51 Photo spacer 52 62 92 Part 53 63 71 93 first film thickness part 54 64 94 second film thickness part 55 non-display area 59x gate lead-out wiring 61 photo spacer PA pixel area
The following describes Embodiment 1 of the present invention with reference to FIGS. FIG. 1 is a plan view showing a schematic configuration of an active matrix substrate (display area / non-display area) according to the present embodiment, and FIG. 2 is a cross-sectional view taken along line A1-A2 shown in FIG.
As shown in FIG. 1, the active matrix substrate 10 includes a scanning signal line 16 formed in the horizontal direction in the drawing and a data signal line 15 formed in the vertical direction in the drawing so as to be orthogonal to each other in the display region 44. A TFT (Thin Film Transistor) 12 formed in the vicinity of the intersection of each signal line (15, 16), a pixel electrode 17, and a storage capacitor wiring (Cs wiring) 18 formed in the horizontal direction in the figure. Is provided. Hereinafter, the horizontal direction in the figure means a direction along the scanning signal line or the storage capacitor line, and the vertical direction in the figure means a direction along the data signal line.
In the TFT 12, the source electrode 9 is connected to the data signal line 15, and the drain electrode 8 is connected to the pixel electrode 17 through the drain lead wiring 37, the drain lead electrode 7, and the contact hole 11. Note that the scanning signal line 16 also serves as the gate electrode of the TFT 12. The pixel electrode 17 is a transparent electrode such as ITO, and transmits light (backlight light) from below the active matrix substrate 10.
In the active matrix substrate 10, the TFT 12 is turned ON (the source electrode 9 and the drain electrode 8 are in a conductive state) by the scanning signal (gate ON voltage) sent to the scanning signal line 16, and in this state, the TFT 12 is sent to the data signal line 15. A data signal (signal voltage) is written to the pixel electrode 17 through the source electrode 9, the drain electrode 8, the drain lead wiring 37, the drain lead electrode 7, and the contact hole 11.
The storage capacitor line 18 crosses each pixel area PA in the horizontal direction in the figure. The storage capacitor line 18 serves as one electrode of the storage capacitor (storage capacitor lower electrode), and the drain lead electrode 7 serves as the other electrode (on the storage capacitor) Electrode). The storage capacitor functions as a capacitor C for holding the potential written in the pixel electrode 17 until the next data signal is input to the pixel electrode 17, for example.
On the other hand, as shown in FIG. 1, in the non-display area 55, the active matrix substrate 10 is formed with the end portion 16x of the scanning signal line and the end portion 18x of the storage capacitor wiring (Cs wiring) in the vertical direction in the figure. Cs trunk wiring (common wiring) 50 is provided. Here, the end portion 18 x of each storage capacitor wiring is connected to the Cs trunk wiring 50 through the contact hole 48, and a predetermined potential is applied to each storage capacitor wiring 18 through the Cs trunk wiring 50. Specifically, in the non-display area 55, the end 18x of each storage capacitor line and the Cs trunk line 50 are orthogonal to each other, and a contact hole 48 is formed in the intersection P.
Here, the cross-sectional structure of the intersection and the vicinity thereof is shown in FIG. As shown in the figure, in the non-display region, the end portion 18x of the storage capacitor line and the end portion 16x of the scanning signal line are formed on the substrate 20, and the gate insulating film 40 is provided so as to cover them. The gate insulating film 40 has a through hole 52 which is a part of the contact hole 48 (located below the opening of the contact hole 48) in the region overlapping with the end 18x of the storage capacitor wiring, and the through hole And a first film thickness portion 53 surrounding 52. Further, the gate insulating film 40 includes a second film thickness portion 54 so as to surround the first film thickness portion 53, and the second film thickness portion 54 overlaps, for example, the end portion 16x of the scanning signal line. ing. Here, the second film thickness portion 54 includes the first gate insulating layer 21 and the second gate insulating layer 22, while the first film thickness portion 53 includes only the second gate insulating layer 22. In the manufacturing process, after the first gate insulating layer 21 is formed so as to cover the storage capacitor wiring 18 and the scanning signal line 16, a part of the first gate insulating layer 21 (a portion corresponding to the first film thickness portion 53 and the punched-through portion 52) is formed. Etching is removed, and then the second gate insulating layer 22 is formed. Further, the portion corresponding to the through hole 52 of the second gate insulating layer 22 is removed by etching. Thereby, the 1st and 2nd film thickness parts 53 * 54 and the penetration part 52 are formed.
On the gate insulating film 40, the Cs trunk wiring 50 is formed in a portion other than the punched-out portion 52. In other words, the Cs trunk wiring 50 is provided with a metal extraction portion 49 that entirely overlaps the penetration portion 52 (of the gate insulating film).
Further, a first interlayer insulating film 25 is formed on the Cs trunk wiring 50. The first interlayer insulating film 25 is provided with a hole that is a part of the contact hole 48 so as to overlap the Cs trunk wiring 50, and a structure in which a part of the Cs trunk wiring 50 is exposed in the contact hole 48. It has become. A connection electrode 38 (ITO) is formed so as to fill the hole 52 in the gate insulating film 52, the metal extraction portion 49, and the first interlayer insulating film 25, and the connection electrode 38 forms the storage capacitor wiring. The end 18x and the Cs trunk wiring 50 are connected.
When the above configuration is viewed in plan, as shown in FIG. 1, the first film thickness portion 53 is entirely overlapped with the intersection portion P (intersection portion of the ends of the Cs trunk wiring and the storage capacitor wiring). The outer periphery (edge) has a rectangular shape with the vertical direction in the figure as the longitudinal direction. The metal extraction part 49 has a rectangular shape whose longitudinal direction is the left-right direction in the drawing so that the entire metal extraction part 49 fits within the edge of the first film thickness part 53. The contact hole 48 has a rectangular shape whose longitudinal direction is the vertical direction in the figure so that the contact hole 48 is entirely contained within the edge of the first film thickness portion 53 and intersects the metal extraction portion 49 at a right angle. In this way, by making the contact hole 48 and the metal extraction portion 49 orthogonal to each other, the deviation margin between them can be increased.
Note that the contact hole 48 for connecting the Cs trunk wiring 50 and the end portion 18x of the storage capacitor wiring does not have to be one as shown in FIG. 1, and a plurality of contact holes 48m can be used as shown in FIG. is there.
As described above, if the formation position of the contact hole 48 is made thin and the other portions are made thick in the gate insulating film in the non-display area 55, the Cs trunk wiring 50 and other wiring (for example, the end of the scanning signal line) The Cs trunk line 50 and the end 18x of the storage capacitor line can be accurately connected while reliably avoiding a short circuit with the line 16x).
The display area 44 of the active matrix substrate 10 is as follows. That is, on the gate insulating film covering the storage capacitor wiring 18, the drain lead electrode 7 drawn from the drain electrode 8 of the TFT 12 and the first interlayer insulating film are formed in this order, and the pixel is formed on the first interlayer insulating film. An electrode 17 is formed.
The drain lead electrode 7 entirely overlaps with the pixel electrode 17 and the storage capacitor wiring 18. Here, the gate insulating film provided in each pixel area PA has a thin film portion 31 having a thickness smaller than that of the surrounding area in a region overlapping with the drain extraction electrode 7. The thin film portion 31 has the same configuration as that of the first film thickness portion 53 of FIG. 2, and includes only the second gate insulating layer 22. Note that the gate insulating film around the thin film portion 31 has the same structure as the second film thickness portion (consisting of the first gate insulating layer 21 and the second gate insulating layer 22). When viewed in a plan view, the thin film portion 31 has a rectangular shape with the left-right direction as the longitudinal direction, and the entire thin film portion 31 overlaps the storage capacitor wiring 18 and the drain extraction electrode 7. As a result, the capacitance C can be determined predominantly at the overlapping portion of the storage capacitor line 18, the drain extraction electrode 7, and the thin film portion 31, so that the effect of the finish of the storage capacitor line 18 on the capacitance C variation is small. Become. Further, each pixel area PA is provided with a contact hole 11 that entirely overlaps the thin film portion 31 and the drain extraction electrode 7, and the drain extraction electrode 7 is connected to the pixel electrode 17 through the contact hole 11.
In addition, the gate insulating film in each pixel area PA is provided with a thin film portion 57 having a thickness smaller than that of the surroundings in a portion overlapping with the TFT 12. The thin film portion 57 has the same configuration as that of the first film thickness portion and includes only the second gate insulating layer. Here, the overlapping area of the source electrode 9 and the thin film portion 57 is configured to be smaller than the overlapping area of the drain electrode 8 and the thin film portion 57. In this way, it is possible to suppress the occurrence of a short circuit between the signal lines (between the data signal line 15 and the scanning signal line 16) that is not easily corrected while maintaining the characteristics of the TFT 12.
As the first gate insulating layer 21, an insulating material (for example, a material containing an organic substance) can be used. For example, a spin-on glass (SOG) material can be used. The SOG material is a material that can form a glass film (silica film) by a coating method such as spin coating. Among SOG materials, for example, a spin-on glass material containing an organic component (so-called organic SOG material) is preferable. As the organic SOG material, an SOG material having a Si—O—C bond as a skeleton or an SOG material having a Si—C bond as a skeleton can be preferably used. An organic SOG material has a low relative dielectric constant, and can easily form a thick film. That is, if an organic SOG material is used, it is easy to form a thick first gate insulating layer 21 by reducing the relative dielectric constant of the first gate insulating layer 21, and it is also possible to perform planarization. In the present embodiment, the thickness of the first gate insulating layer 21 is about 1.5 μm to 2.0 μm. In addition to the above SOG material, materials containing organic substances include acrylic resin materials, epoxy resins, polyimide resins, polyurethane resins, polysiloxane resins, and novolac resins.
Examples of the SOG material having the Si—O—C bond include the materials disclosed in Japanese Patent Laid-Open No. 2001-98224 and Japanese Patent Laid-Open No. 6-240455, and IDW'03 Proceedings, page 617. Examples include DD1100 manufactured by Toray Dow Corning Silicone Co., Ltd. Examples of the SOG material having a Si—C bond as a skeleton include materials disclosed in JP-A-10-102003.
In addition, an organic SOG material containing a silica filler can be used for the first gate insulating layer 21. In this case, it is preferable that the silica filler is dispersed in the base material formed from the organic SOG material. In this way, the first gate insulating layer 21 can be formed without generating cracks even when the substrate 20 is enlarged. In addition, the particle size of a silica filler is 10 nm-30 nm, for example, The mixing ratio is 20 volume%-80 volume%. As an organic SOG material containing a silica filler, for example, LNT-025 manufactured by Catalytic Chemical Co., Ltd. can be used.
The second gate insulating layer 22 is an insulating film formed on the first gate insulating layer 21. In the present embodiment, the second gate insulating layer 22 is a film made of silicon nitride (SiNx), and the thickness of the silicon nitride film is about 300 nm to 500 nm (3000 mm to 5000 mm).
The data signal line 15, the source electrode 9, the drain electrode 8, the Cs trunk wiring 50, and the like are, for example, a single layer film made of a metal such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, copper, or an alloy of these metals. Or it can be set as a laminated film. These film thicknesses may be about 100 nm to 300 nm (1000 to 3000 mm).
As the first interlayer insulating film 25 (channel protective film), an inorganic insulating film such as silicon nitride or silicon oxide, or a laminated film thereof is used. In this embodiment mode, silicon nitride having a thickness of about 200 nm to 500 nm (2000 to 5000 mm) is used.
Further, the pixel electrode 17 (display region) and the connection electrode 38 (non-display region) formed on the first interlayer insulating film 25 are transparent conductive materials such as ITO, IZO, zinc oxide, and tin oxide. It consists of a film, and the film thickness is about 100 nm to 200 nm (1000 to 2000 mm).
Below, an example of the manufacturing method of this active matrix substrate is demonstrated using FIG. 1, FIG.
First, a metal such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, copper, or an alloy of these metals is formed on the transparent insulating substrate 20 by a method such as sputtering. Then, the storage capacitor wiring 18 and the scanning signal line 16 (gate electrode of each TFT) are formed by patterning this metal film or alloy film into a necessary shape by a photoetching method or the like. Note that an end portion 18x of the storage capacitor wiring is formed in the non-display area.
Next, an SOG material or the like is applied so as to cover the storage capacitor wiring 18 and the scanning signal line 16 by using a spin coating method. Thereby, the first gate insulating layer 21 (planarization film) is formed. And after apply | coating a photoresist on the 1st gate insulating layer 21, it exposes using a photomask and develops after that. Next, the first gate insulating layer 21 is removed by dry etching. Dry etching can be performed, for example, using a mixed gas of hydrogen tetrafluoride (CF 4 ) and oxygen (O 2 ). At this time, by adjusting the mixing ratio of hydrogen tetrafluoride (CF 4 ) and oxygen (O 2 ), the vicinity of the edge of the removed portion of the first gate insulating layer can be formed into a forward tapered shape.
By patterning the first gate insulating layer 21 in this way, the first film thickness portion 53 in the non-display area and the thin film portions in the display area (the thin film portion 31 overlapping the storage capacitor wiring 18 and the thin film in the TFT portion). Part 57) can be formed.
Subsequently, the second gate insulating layer 22 and the semiconductor layer (high resistance semiconductor layer and low resistance semiconductor layer) are continuously formed by plasma CVD (chemical vapor deposition) or the like, and then patterned by a photoetching method or the like. Form.
Next, the data signal line 15, the source electrode 9, the drain electrode 8, the drain lead wiring 37, the drain lead electrode 7, and the Cs trunk wiring 50 are formed in the non-display region. These can all be formed by the same process. Specifically, a metal such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, copper, or an alloy of these metals is formed by a sputtering method or the like, and the metal film or alloy film is formed by a photoetching method or the like. And pattern to the required shape.
Then, the pattern of the data signal line 15, the source electrode 9, and the drain electrode 8 is formed on a high resistance semiconductor layer (i layer) such as an amorphous silicon film and a low resistance semiconductor layer (n + layer) such as an n + amorphous silicon film. Using the mask, channel etching is performed by dry etching. In this process, the film thickness of the i layer is optimized, and the TFT 12 is formed. That is, the semiconductor layer not covered with the data signal line 15, the source electrode 8, and the drain electrode 9 is removed by etching, and the i-layer film thickness necessary for the capability of the TFT 12 remains.
Next, a first interlayer insulating film 25 that protects the channel of the TFT 12 (covers the channel) is formed. In this embodiment, an inorganic insulating film such as silicon nitride or silicon oxide is formed by a plasma CVD method or the like.
Further, in the display region, the first interlayer insulating film 25 is etched based on the position of the contact hole 11 to form a hole, and in the non-display region, the first interlayer insulating film 25 and the hole are formed based on the position of the contact hole 48. The second gate insulating layer 22 is etched to form holes. Here, for example, the photosensitive resist is patterned by photolithography (exposure and development), and etching is performed.
Next, a transparent conductive film such as ITO, IZO, zinc oxide, tin oxide or the like is formed on the first interlayer insulating film and in the holes of the respective insulating layers (25, 22) by a method such as sputtering. Then, this is patterned into a necessary shape by a method such as a photoetching method. Thereby, the pixel electrode 17 is formed in the display region, and the pixel electrode 17 and the drain lead electrode 7 are connected in the contact hole 11. Further, the connection electrode 38 is formed in the non-display region, and the Cs trunk wiring 50 and the end portion 18x of the storage capacitor wiring are connected through the contact hole 48.
The present active matrix substrate can also be configured as shown in FIG. As shown in FIG. 3, in the non-display region 55, the active matrix substrate 10y includes scanning signal line end portions 16x formed in the left-right direction in the drawing, and gate lead wiring ends formed in the left-right direction in the drawing. A portion 59x, an end 18x of a storage capacitor wiring (Cs wiring) formed in the horizontal direction in the figure, and a Cs trunk wiring (common wiring) 50 formed in the vertical direction in the figure. The configuration of the display area 44 is the same as that shown in FIG. Here, the end portion 16x of the scanning signal line is connected to the end portion 59x of the gate lead-out wiring through the contact hole 68. Specifically, in the non-display area 55, the end portion 16x of the scanning signal line and the end portion 59x of the gate lead-out wiring overlap, and the contact hole 68 is formed in the overlapping portion P.
Here, FIG. 4 shows a cross-sectional structure of the overlapping portion P and its vicinity (A3-A4 cross-sectional view of FIG. 3). As shown in the figure, an end portion 16x of the scanning signal line is formed on the substrate 20, and a gate insulating film 40 is provided so as to cover the end portion 16x. The gate insulating film 40 has a through hole 62 which is a part of the contact hole 68 (located below the opening of the contact hole 68) and a through hole in a region overlapping with the end 16x of the scanning signal line. And a first film thickness portion 63 surrounding 62. Further, the gate insulating film 40 includes a second film thickness portion 64 so as to surround the first film thickness portion 63, and the second film thickness portion 64 overlaps the Cs trunk wiring 50, for example. Here, the second film thickness portion 64 includes the first gate insulating layer 21 and the second gate insulating layer 22, while the first film thickness portion 63 includes only the second gate insulating layer 22. In the manufacturing process, after the first gate insulating layer 21 is formed so as to cover the storage capacitor wiring 18 and the scanning signal line 16, a part thereof (a portion corresponding to the first film thickness portion 63 and the punched-out portion 62) is formed. Etching is removed, and then the second gate insulating layer 22 is formed. Further, a portion corresponding to the penetration portion 62 of the second gate insulating layer 22 is removed by etching. Thereby, the 1st and 2nd film thickness parts 63 * 64 and the penetration part 62 are formed.
On the gate insulating film 40, an end portion 59x of the gate lead-out wiring is formed in a portion other than the punched-out portion 62. That is, a metal extraction portion 69 that is entirely overlapped with the penetration portion 62 of the gate insulating film is provided at the end portion 59x of the gate lead-out wiring.
A first interlayer insulating film 25 is formed on the end portion 59x of the gate lead-out wiring. The first interlayer insulating film 25 is provided with a hole that is a part of the contact hole 68 so as to overlap the end part 59x of the gate lead-out wiring, and a part of the end part 59x of the gate lead-out wiring in the contact hole. Is exposed. A connection electrode 78 (ITO) is formed so as to fill the hole 62 in the gate insulating film, the metal extraction portion 69, and the first interlayer insulating film 25. The end 16x is connected to the end 59x of the gate lead-out wiring.
When the above configuration is viewed in plan, as shown in FIG. 3, the first film thickness portion 63 as a whole has an intersection P (an intersection between the end of the gate lead-out wiring and the end of the scanning line signal line). ) And its outer periphery (edge) has a rectangular shape with the vertical direction in the figure as the longitudinal direction. The metal punching portion 69 has a rectangular shape with the longitudinal direction in the horizontal direction in the figure such that the entire portion is within the edge of the first film thickness portion 63. The contact hole 68 has a rectangular shape whose longitudinal direction is the vertical direction in the drawing so that the entire contact hole 68 fits within the edge of the first film thickness portion 63 and intersects the metal extraction portion 69 at a right angle.
FIG. 35 shows a configuration of a liquid crystal panel including the active matrix substrate 10y and the color filter substrate (CF substrate) shown in FIG. Here, only the photo spacers are illustrated among the components of the color filter substrate. As shown in FIG. 35, in the liquid crystal panel 504j, photo spacers 51 (first spacers) are arranged so as to overlap the scanning signal lines 16 in the display area 44, and each scanning is performed in the non-display area 55. A photo spacer 61 (second spacer) is disposed so as to overlap with the end 16x of the signal line. Although not shown, the photo spacers 51 are arranged at intervals in the left-right direction in the drawing so as to overlap the scanning signal lines 16 in the display area 44.
The photo spacers 51 and 61 are columnar spacers provided on the CF substrate side, but may be provided on the active matrix substrate side.
FIG. 36 shows a cross-sectional view taken along line arrow including the photo spacer 51 in the display area of FIG. 35 and a cross-sectional view taken along line arrow including the photo spacer 61 in the non-display area. As shown in the figure, the scanning signal line 16, the first gate insulating layer 21, the second gate insulating layer 22, and the first interlayer are arranged in order from the transparent insulating substrate 20 side under the photo spacer 51 in the display region. An insulating film 25 is provided, and under the photo spacer 61 in the non-display area, in order from the transparent insulating substrate 20 side, an end portion 16x of the scanning signal line, the first gate insulating layer 21, the second gate insulating layer 22, and A first interlayer insulating film 25 is disposed.
35, since the structure under the photo spacer is the same between the non-display area and the display area, it is easy to set the height of each of the photo spacers 51 and 61, and between the display area 44 and the non-display area 55. The difference in cell gap can be reduced.
The present active matrix substrate can also be configured as shown in FIG. This active matrix substrate is used for multi-pixel driving in which a plurality of regions having different luminances are formed in one sub-pixel (corresponding to any one of R, G, and B).
As shown in FIG. 5, the active matrix substrate 10x includes a scanning signal line 16 formed in the horizontal direction in the drawing and a data signal line 15 formed in the vertical direction in the drawing so as to be orthogonal to each other in the display region 44. The first and second TFTs 12a and 12b formed in the vicinity of the intersections of the signal lines (15 and 16), the first and second pixel electrodes 17a and 17b, and the first TFT formed in the horizontal direction in the drawing. And second storage capacitor lines (Cs lines) 18a and 18b. One pixel area PA includes the first and second TFTs 12a and 12b and the first and second pixel electrodes 17a and 17b.
The first TFT 12a has its source electrode 9 connected to the data signal line 15, and its drain electrode 8a connected to the first pixel electrode 17a via the drain lead wiring 37a, the drain lead electrode 7a, and the contact hole 11a. The Similarly, in the second TFT 12b, the source electrode 9 is connected to the data signal line 15, and the drain electrode 8b is connected to the second pixel electrode 17b via the drain lead wiring 37b, the drain lead electrode 7b, and the contact hole 11b. Connected to. The scanning signal line 16 also serves as the gate electrodes of the first and second TFTs 12a and 12b.
In the present active matrix substrate, the first storage capacitor line 18a overlaps with the drain extraction electrode 7a, and the second storage capacitor line 18b overlaps with the drain extraction electrode 7b. The drain lead electrode 7a functions as one electrode of the capacitor C1, and the first storage capacitor line 18a functions as the other electrode of the capacitor C1. Similarly, the drain lead electrode 7b functions as one electrode of the capacitor C2, and the second storage capacitor line 18b functions as the other electrode of the capacitor C2. Each of these capacitors C1 and C2 functions as a control capacitor and a storage capacitor for each pixel electrode potential.
That is, in the present active matrix substrate, the data (signal potential) from the data signal line 15 passes through the common source electrode 9 of each TFT (12a and 12b), the drain electrodes 8a and 8b, etc. Although applied to the second pixel electrodes 17a and 17b, signal voltages having opposite phases to each other are applied to the first and second storage capacitor lines 18a and 18b, respectively, and the first and second pixel electrodes 17a and 17b are applied. Each of 17b is controlled to a different potential. Accordingly, a bright region and a dark region can be formed in one pixel region, and a halftone can be expressed by area gradation. As a result, it is possible to improve display quality, such as improving whitening at an oblique viewing angle.
On the other hand, in the non-display area 55, the active matrix substrate 10x has an end portion 16x of the scanning signal line, end portions 18A and 18B of the first and second storage capacitor lines (Cs lines), and the vertical direction in the figure. The first and second Cs trunk wires (common wires) 50a and 50b are formed.
Here, the end 18A of the first storage capacitor line is connected to the first Cs trunk line 50a via the contact hole 48a, and the first storage capacitor line is connected via the first Cs trunk line 50a. A signal potential is applied to 18a. Specifically, in the non-display area 55, the end 18A of the first storage capacitor line intersects the first Cs trunk line 50a, and a contact hole 48a is formed in the intersection P1. . Similarly, the end 18B of the second storage capacitor line is connected to the second Cs trunk line 50b via the contact hole 48b, and the second storage capacitor line is connected via the second Cs trunk line 50b. A signal potential (having a phase opposite to that of the first storage capacitor wiring 18a) is applied to 18b. Specifically, in the non-display area 55, the end 18B of the second storage capacitor line intersects with the second Cs trunk line 50b, and a contact hole 48b is formed in the intersection P2. .
The active matrix substrate 10x is provided with a first film thickness portion 53a, a metal removal portion 49a, a connection electrode 38a, and a contact hole 48a at a position overlapping the intersecting portion P1. The first film thickness portion 53a is a portion where the gate insulating film is thinner than the surroundings (consisting only of the first gate insulating layer). The gate insulating film has a second film thickness portion (not shown) having a large film thickness so as to surround the first film thickness portion 53a. The second film thickness portion is, for example, a scanning signal line. And the second Cs trunk wiring 50b. The metal extraction portion 49a is a portion that penetrates a part of the first Cs trunk wiring 50a, and overlaps the portion that the gate insulating film is penetrated.
Here, the entire first film thickness portion 53a overlaps the intersection portion P1 (intersection portion between the first Cs trunk wire 50a and the end portion 18A of the first storage capacitor wire), and the outer periphery ( The edge) has a rectangular shape with the vertical direction in the figure as the longitudinal direction. The metal extraction part 49a has a rectangular shape whose longitudinal direction is the left-right direction in the figure such that the entire metal extraction part 49a fits within the edge of the first film thickness part 53a. The contact hole 48a has a rectangular shape whose longitudinal direction is the vertical direction in the figure so that the entire contact hole 48a is within the edge of the first film thickness portion 53a and intersects the metal extraction portion 49a at a right angle. The connection electrode 38a (ITO) is formed so as to overlap the metal extraction portion 49a and the contact hole 48a, and connects the first Cs trunk wiring 50a and the end 18A of the first storage capacitor wiring. .
In the present active matrix substrate 10x, a first film thickness portion 53b, a metal removal portion 49b, a connection electrode 38b, and a contact hole 48b are provided at a position overlapping the intersecting portion P2. The first film thickness portion 53b is a portion where the gate insulating film is thinner than the surroundings (consisting only of the first gate insulating layer). The gate insulating film has a second film thickness portion (not shown) having a large film thickness so as to surround the first film thickness portion 53b. The second film thickness portion is, for example, a scanning signal line. And the second Cs trunk wiring 50a.
The metal extraction portion 49b is a portion that penetrates part of the second Cs trunk wiring 50b, and overlaps the portion where the gate insulating film is penetrated. Here, the entire first film thickness portion 53b overlaps the intersection P2 (intersection between the second Cs trunk wiring 50b and the end 18B of the second storage capacitor wiring), and the outer periphery ( The edge) has a rectangular shape with the vertical direction in the figure as the longitudinal direction. The metal extraction part 49b has a rectangular shape whose longitudinal direction is the left-right direction in the drawing so that the entire metal extraction part 49b fits within the edge of the first film thickness part 53b. The contact hole 48b has a rectangular shape whose longitudinal direction is the vertical direction in the drawing so that the contact hole 48b is entirely contained within the edge of the first film thickness portion 53b and intersects the metal extraction portion 49b at a right angle. The connection electrode 38b (ITO) is formed so as to overlap with the metal extraction portion 49b and the contact hole 48b, and connects the second Cs trunk wiring 50b and the end 18B of the second storage capacitor wiring. .
The configuration of the display area 44 is as follows. That is, the drain lead electrode 7a entirely overlaps with the first pixel electrode 17a and the first storage capacitor line 18a. Here, the gate insulating film provided in each pixel area PA has a thin film portion 31a having a thickness smaller than that of the surrounding area in a region overlapping with the drain extraction electrode 7a. The thin film portion 31 a has the same configuration as the first film thickness portions 53 a and 53 b (see FIG. 5), and includes only the second gate insulating layer 22. Note that the gate insulating film around the thin film portion 31a has the same structure as the second film thickness portion (consisting of the first gate insulating layer 21 and the second gate insulating layer 22).
When viewed in plan, the thin film portion 31a has a rectangular shape with the left-right direction as the longitudinal direction, and the entirety overlaps with the first storage capacitor wiring 18a and the drain extraction electrode 7a. As a result, the capacitance C1 can be determined predominantly at the overlapping portion of the first storage capacitor line 18a, the drain lead electrode 7a, and the thin film portion 31a. Further, each pixel area PA is provided with a contact hole 11a that entirely overlaps with the thin film portion 31a, and the drain extraction electrode 7a is connected to the first pixel electrode 17a through the contact hole 11a.
Further, the drain lead electrode 7b entirely overlaps with the second pixel electrode 17b and the second storage capacitor wiring 18b. Here, the gate insulating film provided in each pixel area PA has a thin film portion 31b having a thickness smaller than that of the surrounding area in a region overlapping with the drain extraction electrode 7b. The thin film portion 31b has the same configuration as the first film thickness portions 53a and 53b (see FIG. 5), and includes only the second gate insulating layer 22. The gate insulating film around the thin film portion 31b has the same structure as the second film thickness portion. When viewed in plan, the thin film portion 31b has a rectangular shape with the left-right direction as the longitudinal direction, and the entirety overlaps with the second storage capacitor wiring 18b and the drain extraction electrode 7b. As a result, the capacitance C2 can be determined predominantly at the overlapping portion of the second storage capacitor line 18b, the drain lead electrode 7b, and the thin film portion 31b. Further, each pixel region is provided with a contact hole 11b that overlaps the thin film portion 31b as a whole, and the drain extraction electrode 7b is connected to the second pixel electrode 17b through the contact hole 11b.
When the active matrix substrate 10x is applied to an MVA liquid crystal panel, a slit having, for example, a horizontal V shape (a shape obtained by rotating the V shape by 90 degrees) is provided in the first and second pixel electrodes 17a and 17b. Is formed.
FIG. 15 is a timing chart showing the operation of each part of FIG. Here, Vg is the voltage of the scanning signal line 16, Vs is the voltage (source voltage) of the data signal line 15, Vcs1 is the voltage of the first storage capacitor line 18a, Vcs2 is the voltage of the second storage capacitor line 18b, and Vlc1. Is the voltage of the first pixel electrode 17a, and Vlc2 is the voltage of the second pixel electrode 17b. In a liquid crystal display device, AC driving such as frame inversion, line inversion, and dot inversion is generally performed so that the liquid crystal is not polarized. That is, a positive polarity source voltage (Vsp) is given to the median source voltage Vsc in the nth frame, a negative polarity source voltage (Vsn) is given to Vsc in the next (n + 1) th frame, and Perform dot inversion for each frame. Further, the voltage of the first storage capacitor line 18a and the voltage of the second storage capacitor line 18b are each made to amplitude by the amplitude voltage Vad, and the phases of both are shifted by 180 degrees. That is, immediately after Vg becomes “L” at T2 (each TFT 12a and 12b is turned off), both are controlled so that Vcs1 becomes “H” and Vcs2 becomes “L”.
Also, as shown in FIG. 16, Vcs1 remains “High” (or remains “Low” at T3 immediately after Tg2 when Vg becomes “L” (TFTs 12a and 12b are turned off). ), And Vcs2 may be a waveform that remains “Low” (or remains “High”) at T4 after one horizontal period (1H) from T3. That is, after each transistor is turned off, Vcs1 is pushed up to maintain the state in which the frame is pushed up, and Vcs2 is pushed down by shifting by 1 H period from the pushing up of Vcs1 and the frame is kept pushed down. The potential control is performed so as to maintain the state, or after each transistor is turned off, Vcs1 is pushed down to maintain the pushed state in the frame, and is shifted by 1H period from the pushing down of Vcs1. Then, the potential control is performed such that Vcs2 is pushed up and the pushed-up state is maintained in the frame. In this way, the influence of the rounds of the Vcs1 and Vcs2 waveforms on the effective drain potential is reduced, which is effective in reducing luminance unevenness.
Note that the active matrix substrate shown in FIG. 5 has a configuration in which each storage capacitor wiring is shared by pixels adjacent vertically (in the direction along the data signal line). However, each storage capacitor wiring is shared by pixels adjacent vertically. In the configuration not sharing, as shown in FIG. 17, Vcs1 remains “High” at T3 immediately after Vg becomes “L” at T2 (TFTs 12a and 12b are turned off) (or “Low”). Similarly, Vcs2 is a waveform that remains “Low” (or remains “High”) at T3 immediately after Vg becomes “L” at T2. You can also. That is, after each transistor is turned off, Vcs1 is pushed up to maintain the state in which the frame is pushed up, and Vcs2 is pushed down in synchronization with the push-up of Vcs1 and the state in which the frame is pushed down. Is controlled, or after each transistor is turned off, Vcs1 is pushed down to keep this state pushed down in the frame, and Vcs2 is kept synchronized with the pushing down of Vcs1. It is also possible to perform potential control so that the frame is pushed up and the pushed-up state is maintained. Also in this case, the influence of the rounds of the Vcs1 and Vcs2 waveforms on the drain effective potential is reduced, which is effective in reducing luminance unevenness.
The present active matrix substrate 10x can be modified as shown in FIG. That is, the first film thickness portion (the portion where the gate insulating film is thin) is as large as possible in the portion between the two adjacent scanning signal lines in the first and second Cs trunk wires 50a and 50b. Form to include.
In the active matrix substrate shown in FIG. 18, the outer periphery of the first film thickness portion 71a has a rectangular shape with the left-right direction in the drawing including the intersecting portion P1 as the longitudinal direction. Here, one side extending in the left-right direction is close to one of the two scanning signal lines sandwiching the end portion 18A of the first storage capacitor line and crosses the first Cs trunk line 50a and the second Cs trunk line 50b. At the same time, the other side extending in the left-right direction is close to the other of the two scanning signal lines and crosses the first Cs trunk line 50a and the second Cs trunk line 50b. In addition, the metal extraction part 49a is a rectangular shape which makes the left-right direction in a figure the longitudinal direction so that the whole may settle in the cross | intersection part P1. The contact hole 48a has a rectangular shape whose longitudinal direction is the vertical direction in the figure so that the entire contact hole 48a fits in the intersection P1 and intersects the metal extraction part 49a at a right angle.
On the other hand, the outer periphery of the first film thickness portion 71b (portion where the gate insulating film is thick) shown in FIG. 18 is crossed portions P2 and P3 (end portions of the first Cs trunk wiring 50a and the second storage capacitor wiring). 18B includes a rectangular shape having a longitudinal direction in the horizontal direction in the drawing. Here, one side extending in the left-right direction is close to one of the two scanning signal lines sandwiching the end 18B of the first storage capacitor line, and crosses the first Cs trunk line 50a and the second Cs trunk line 50b. At the same time, the other side extending in the left-right direction is close to the other of the two scanning signal lines and crosses the first Cs trunk line 50a and the second Cs trunk line 50b. However, the portion corresponding to the intersection P3 is the second film thickness portion 36 (portion where the gate insulating film is thick). In addition, the metal extraction part 49b is a rectangular shape which makes the left-right direction in a figure the longitudinal direction so that the whole may be settled in the cross | intersection part P2. The contact hole 48b has a rectangular shape whose longitudinal direction is the vertical direction in the figure so that the entire contact hole 48b fits in the intersection P2 and intersects the metal extraction part 49b at a right angle.
In the active matrix substrate as shown in FIG. 18, the potential of the first Cs trunk wiring 50a is different from that of the common electrode formed on the counter substrate (CF substrate, not shown). Although the potential waveform of the Cs trunk wiring 50a (and hence the first storage capacitor wiring 18a) may become dull, the first film thickness portion 71a (the portion where the gate insulating film is thin) By forming the first and second Cs trunk lines 50a and 50b so as to include as many portions as possible in a region sandwiched between two adjacent scanning signal lines, the first Cs trunk lines 50a The parasitic capacitance can be reduced by lowering the position of many parts (toward the glass substrate) and increasing the distance from the counter substrate (CF). Thereby, the potential waveform of each Cs trunk line can be sharpened. The same can be said for the first film thickness portion 71b. Further, since the portion corresponding to the intersection P3 is the second film thickness portion 36 (the portion where the gate insulating film is thick), the first Cs trunk wiring The occurrence of a short circuit between 50a and the end 18B of the second storage capacitor wiring can also be prevented.
FIG. 19 shows a configuration of a liquid crystal panel including the present active matrix substrate and a color filter substrate (referred to as a CF substrate as appropriate) shown in FIG. Here, only the photo spacer is illustrated among the components of the CF substrate. As shown in FIG. 19, in the liquid crystal panel 504a, photo spacers 51 (first spacers) are arranged so as to overlap the scanning signal lines 16 in the display area 44, and each scanning is performed in the non-display area 55. A photo spacer 61 (second spacer) is disposed so as to overlap with the end 16x of the signal line. Although not shown, the photo spacers 51 are arranged at intervals in the left-right direction in the drawing so as to overlap the scanning signal lines 16 in the display area 44.
FIG. 20 shows a cross-sectional view taken along the line arrow of the display region and a cross-sectional view taken along the line arrow of the non-display region in FIG. As shown in the figure, the scanning signal line 16, the first gate insulating layer 21, the second gate insulating layer 22, and the first interlayer are arranged in order from the transparent insulating substrate 20 side under the photo spacer 51 in the display region. An insulating film 25 is provided, and under the photo spacer 61 in the non-display area, in order from the transparent insulating substrate 20 side, an end portion 16x of the scanning signal line, the first gate insulating layer 21, the second gate insulating layer 22, and A first interlayer insulating film 25 is disposed.
In this way, by setting the structure under the photo spacer (particularly the structure of the gate insulating film 40) between the non-display area and the display area, the height of each of the photo spacers 51 and 61 can be easily set. In addition, the difference in cell gap between the non-display areas 55 can be reduced. Thereby, it is possible to suppress the occurrence of luminance unevenness in the vicinity of the boundary between the display area 44 and the non-display area 55.
In a so-called VA mode liquid crystal display device in which the alignment of the liquid crystal layer is a vertical alignment, the cell gap in the non-display area is −0.4 μm to +0.2 μm, preferably −0.2 μm with respect to the cell gap in the display area. To +0.1 μm. In other words, even if there is a variation in the thickness of the color filter layer or black matrix on the CF substrate side, a variation in the height of the photo spacer, or a variation in the thickness of the active matrix substrate, the above-mentioned cell is divided between the display region and the non-display region. It is sufficient that the gap difference is within the above numerical range. Note that the negative range is wide because when the cell gap of the non-display area is smaller than the cell gap of the display area inside the non-display area, the luminance unevenness is visually recognized as compared with the case of being larger than the cell gap of the display area. It is difficult.
In the case where the non-display area can be designed to be sufficiently small, as shown in FIGS. 21 and 22 (a cross-sectional view of the display area and a cross-sectional view of the non-display area in FIG. 21), the seal of the liquid crystal panel 504b By including the bead-like spacer 76 in 67, the cell gap of the non-display area 55 can be maintained. In this case, the photo spacer 61 in the non-display area 55 can be formed lower than the photo spacer 51 (the photo spacer 61 has a constant cell gap in the non-display area when external pressure is applied to the liquid crystal panel. Function to prevent the value from falling below).
The liquid crystal panel according to this embodiment can also be configured as shown in FIG. As shown in FIG. 23, in the liquid crystal panel 504c, photo spacers 51 (first spacers) are arranged so as to overlap the scanning signal lines 16 in the display region 44, while each metal wiring ( Photo spacers 61 (second spacers) are arranged at positions that do not overlap the end portions 16x of the scanning signal lines and the end portions 18A and 18B of the storage capacitor lines. FIG. 24 shows a cross-sectional view taken along line arrow of the display area and a cross-sectional view taken along line arrow of the non-display area in FIG. As shown in the figure, the scanning signal line 16, the first gate insulating layer 21, the second gate insulating layer 22, and the first interlayer are arranged in order from the transparent insulating substrate 20 side under the photo spacer 51 in the display region. An insulating film 25 is disposed, and a first gate insulating layer 21, a second gate insulating layer 22, and a first interlayer insulating film 25 are arranged under the photo spacer 61 in the non-display area in order from the transparent insulating substrate 20 side. Arranged.
In this case, although the structure under the photo spacer does not match between the non-display area and the display area, the structures of the gate insulating film 40 (the first gate insulating layer 21 and the second gate insulating layer 22) match. Here, since the first gate insulating layer 21 is a planarizing film (SOG film or the like), the total film thickness of each film formed on the transparent insulating substrate 20 under the photo spacer 51 and under the photo spacer 61 The total film thickness of each film formed on the structural transparent insulating substrate 20 is almost the same. Therefore, also in the configuration shown in FIGS. 23 and 24, the height of each of the photo spacers 51 and 61 can be easily set, and the difference in cell gap between the display area 44 and the non-display area 55 can be reduced. Thereby, it is possible to suppress the occurrence of luminance unevenness in the vicinity of the boundary between the display area 44 and the non-display area 55.
Note that the photospacer 51 on the display area 44 side is not necessarily provided on the metal wiring (scanning signal line or the like), but is desirably arranged at a position that does not overlap with the pixel electrodes 17a and 17b. This is because if the photo spacers 51 are arranged at positions overlapping the pixel electrodes 17a and 17b, the photo spacers 51 may disturb the liquid crystal alignment.
The liquid crystal panel according to this embodiment can also be configured as shown in FIG. As shown in FIG. 29, in the liquid crystal panel 504f, a photo spacer 51 (first spacer) is disposed so as to overlap the first storage capacitor wiring 18a in the display area 44, and in the non-display area 55, A photo spacer 61 (second spacer) is disposed so as to overlap with the end portion 18A of the first storage capacitor wiring.
FIG. 30 shows a cross-sectional view taken along the line arrow of the display region and a cross-sectional view taken along the line arrow of the non-display region in FIG. As shown in the figure, below the photo spacer 51 in the display region, in order from the transparent insulating substrate 20 side, the first storage capacitor wiring 18a, the first gate insulating layer 21, the second gate insulating layer 22, and the first One interlayer insulating film 25 is disposed, and under the photo-spacer 61 in the non-display area, the end 18A of the first storage capacitor wiring, the first gate insulating layer 21, the second, in order from the transparent insulating substrate 20 side. A gate insulating layer 22 and a first interlayer insulating film 25 are disposed.
29, since the structure under the photo spacer is the same between the non-display area and the display area, it is easy to set the height of each of the photo spacers 51 and 61, and between the display area 44 and the non-display area 55. The difference in cell gap can be reduced.
The liquid crystal panel according to this embodiment can also be configured as shown in FIG. As shown in FIG. 31, in the liquid crystal panel 504g, a photo spacer 51 (first spacer) is arranged so as to overlap with the scanning signal line 16 in the display area 44, and in the non-display area 55, the first A photo spacer 61 (second spacer) is arranged so as to overlap with the end 18A of the storage capacitor wiring.
FIG. 32 shows a cross-sectional view taken along the line arrow of the display region and a cross-sectional view taken along the line arrow of the non-display region in FIG. As shown in the figure, the scanning signal line 16, the first gate insulating layer 21, the second gate insulating layer 22, and the first interlayer are arranged in order from the transparent insulating substrate 20 side under the photo spacer 51 in the display region. An insulating film 25 is disposed, and under the photo-spacer 61 in the non-display area, the end 18A of the first storage capacitor wiring, the first gate insulating layer 21, and the second gate insulating layer are sequentially formed from the transparent insulating substrate 20 side. 22 and the first interlayer insulating film 25 are disposed.
In the configuration of FIG. 31 as well, the structure under the photo spacers is the same between the non-display area and the display area, so that the height of each photo spacer 51 and 61 can be easily set, and the display area 44 and the non-display area 55 can be set. The difference in cell gap can be reduced.
The liquid crystal panel according to this embodiment can also be configured as shown in FIG. As shown in FIG. 25, in the liquid crystal panel 504d, photo spacers 51 (first spacers) are arranged in the display area 44 so as to overlap the intersections of the scanning signal lines 16 and the data signal lines 15, and the non-display area In 55, a photo spacer 61 (second spacer) is arranged so as to overlap the intersection of the first Cs trunk wiring 50a and the end 16x of each scanning signal line. FIG. 26 shows a cross-sectional view of the display area in FIG. 25 taken along a line and a cross-sectional view of a non-display area. As shown in FIG. 26, the scanning signal line 16, the first gate insulating layer 21, the second gate insulating layer 22, the data signal line 15, in order from the transparent insulating substrate 20 side, below the photo spacer 51 in the display area. The first interlayer insulating film 25 is disposed, and the scanning signal line end 16x, the first gate insulating layer 21, and the second gate are arranged under the photo spacer 61 in the non-display area in order from the transparent insulating substrate 20 side. The insulating layer 22, the first Cs trunk wiring 50a, and the first interlayer insulating film 25 are disposed.
Even in the configuration of FIG. 25, since the structure under the photo spacer is the same between the non-display area and the display area, it is easy to set the height of each of the photo spacers 51 and 61, and between the display area 44 and the non-display area 55. The difference in cell gap can be reduced. Thereby, it is possible to suppress the occurrence of luminance unevenness in the vicinity of the boundary between the display area 44 and the non-display area 55. Thereby, it is possible to suppress the occurrence of luminance unevenness in the vicinity of the boundary between the display area 44 and the non-display area 55.
In addition, the height of the photo spacer 61 can be reduced by the film thickness of the first Cs trunk wiring 50a in the non-display area 55, and the height of the photo spacer 61 can be increased by the film thickness of the data signal line 15 in the display area 44. Can be reduced. Therefore, it is possible to shorten the time for exposing and developing the photo spacer, leading to an improvement in throughput. Further, the material for forming the photo spacer can be reduced. The first Cs trunk wiring 50a and the data signal line 15 are formed in the same process and are arranged on the same layer (on the gate insulating film 40).
The liquid crystal panel according to this embodiment can also be configured as shown in FIG. As shown in FIG. 27, in the liquid crystal panel 504e, the photo spacer 51 (first spacer) is overlapped with the intersection of the scanning signal line 16 or the second storage capacitor line 18b and the data signal line 15 in the display area 44. ) Is arranged, and in the non-display area 55, the photo spacer 61 (so as to overlap the intersection of the end portion 16 x of the scanning signal line 16 or the end portion 18 B of the second storage capacitor line and the first Cs trunk line 50 a. A second spacer) is arranged. FIG. 28 shows a cross-sectional view of the display area in FIG. 27 taken along a line and a cross-sectional view of a non-display area. As shown in FIG. 28, below the photo spacer 51 in the display area, the scanning signal line 16, the first gate insulating layer 21, the second gate insulating layer 22, the data signal line 15, The first interlayer insulating film 25 is disposed, and the second storage capacitor wiring end 18B, the first gate insulating layer 21, The second gate insulating layer 22, the first Cs trunk wiring 50a, and the first interlayer insulating film 25 are disposed.
Even in the configuration of FIG. 27, since the structure under the photo spacer is the same between the non-display area and the display area, it is easy to set the height of each of the photo spacers 51 and 61, and between the display area 44 and the non-display area 55. The difference in cell gap can be reduced. Thereby, it is possible to suppress the occurrence of luminance unevenness in the vicinity of the boundary between the display area 44 and the non-display area 55. Thereby, it is possible to suppress the occurrence of luminance unevenness in the vicinity of the boundary between the display area 44 and the non-display area 55.
In addition, since the photospacer 61 is arranged at the intersection (P3) between the end 18B of the second storage capacitor line and the first Cs trunk line 50a, the relative dielectric constant of the photospacer 61 is set to (the liquid crystal layer). If it is lower than the average relative dielectric constant of the liquid crystal material, the parasitic capacitance between the first Cs trunk wiring 50a and the CF substrate at the intersection P3 can be suppressed.
As described above, in order to prevent a short circuit between the first Cs trunk wiring 50a and the end 18B of the second storage capacitor wiring, the intersecting portion P3 is set to the second film thickness portion 36 (portion where the gate insulating film is thick). Then, the distance between the first Cs trunk wiring 50a and the CF substrate is shortened, and the parasitic capacitance between both is increased. Therefore, the parasitic capacitance can be reduced by disposing a photo spacer 61 having a relative dielectric constant lower than the average relative dielectric constant of the liquid crystal material on the intersection P3. Since the average relative dielectric constant (average of ε || and ε⊥) of a general vertical alignment liquid crystal is about 6.0, for example, an acrylic photosensitive resin having a relative dielectric constant of about 4.3 on the photo spacer 61. If is used, an effect of reducing parasitic capacitance can be obtained. Note that, from the viewpoint of reducing the parasitic capacitance, the photo spacer 61 does not need to contact the active matrix substrate, and the photo spacer 61 preferably has a bottom area equivalent to the area of the intersection P3. The photo spacer 61 disposed on the intersection P3 includes a novolac resin having a relative dielectric constant of about 3.5 to 4.0, a urethane system having a relative dielectric constant of 3 to 5, and a polyester system having a relative dielectric constant of about 3. A resin, a polyolefin resin having a relative dielectric constant of about 2 to 3, and the like can be used.
The present active matrix substrate can also be configured as shown in FIG. FIG. 6 shows a schematic configuration of an active matrix substrate (display area / non-display area) according to the present embodiment. As shown in FIG. 6, the active matrix substrate 10 z is formed in the non-display area 55 in the vertical direction in the figure, with the end 16 x of the scanning signal line and the end 18 x of the storage capacitor wiring (Cs wiring). Cs trunk wiring (common wiring) 50. Here, the end portion 18 x of each storage capacitor line is connected to the Cs trunk line 50 through the contact hole 98, and a predetermined potential is applied to each storage capacitor line 18 through the Cs trunk line 50. Specifically, in the non-display area 55, the end 18x of each storage capacitor line and the Cs trunk line 50 intersect, and a contact hole 98 is formed in the intersection P.
Here, FIG. 7 shows the cross-section P and a cross-sectional structure in the vicinity thereof (B1-B2 cross-sectional view in FIG. 6). As shown in the figure, an end 18x of the storage capacitor wiring is formed on the substrate 20 and a gate insulating film 40 is provided so as to cover the end 18x. The gate insulating film 40 includes a through hole 92 that is a part of the contact hole 98 and a first film thickness portion 93 that surrounds the through hole 92 in a region overlapping with the end 18x of the storage capacitor wiring. Is provided. Further, the gate insulating film 40 includes a second film thickness portion 94 so as to surround the first film thickness portion 93. Here, the boundary K between the first and second film thickness portions 93 and 94 is positioned outside by a distance d from the edge of the end portion 18x of the storage capacitor wiring, and the second film thickness portion 94 is, for example, a scanning signal. It overlaps the line end 16x (see FIG. 6). Here, the second film thickness portion 94 includes the first gate insulating layer 21 and the second gate insulating layer 22, while the first film thickness portion 93 includes only the second gate insulating layer 22. In the manufacturing process, after the first gate insulating layer 21 is formed so as to cover the storage capacitor wiring 18 and the scanning signal line 16, a part of the first gate insulating layer 21 (a portion corresponding to the first film thickness portion 93 and the punched-out portion 92) is formed. Etching is removed, and then the second gate insulating layer 22 is formed. Further, the portion corresponding to the through hole 92 of the second gate insulating layer 22 is removed by etching. Thereby, the 1st and 2nd film thickness parts 93 * 94 and the penetration part 92 are formed.
On the gate insulating film 40, the Cs trunk wiring 50 is formed in a portion other than the punched-out portion 92. In other words, the Cs trunk wiring 50 is provided with a metal extraction portion 79 that overlaps with the penetration portion 92 (of the gate insulating film).
A first interlayer insulating film 25 and a second interlayer insulating film 26 are formed on the Cs trunk wiring 50. The first interlayer insulating film 25 and the second interlayer insulating film 26 are provided with a hole that is a part of the contact hole 98 so as to overlap the Cs trunk wiring 50, and the Cs trunk wiring 50 is formed in the contact hole. The structure is such that a part is exposed. Then, a connection electrode 95 (ITO) is formed so as to fill the punched through portion 92 of the gate insulating film, the metal extraction portion 79, the hole in the first interlayer insulating film 25, and the hole in the second interlayer insulating film 26. The connection electrode 95 connects the end 18x of the storage capacitor line to the Cs trunk line 50.
When the above configuration is viewed in plan, as shown in FIG. 6, the outer periphery (edge) of the first film thickness portion 93 has a rectangular shape whose longitudinal direction is the left-right direction in the drawing, and the intersection P The whole (intersection of the ends of the Cs trunk wiring and the storage capacitor wiring) is located within the outer periphery of the first film thickness portion 93. The metal punched portion 79 has a rectangular shape with the longitudinal direction in the horizontal direction in the figure such that the entire metal-extracted portion 79 fits within the edge of the first film thickness portion 93. The contact hole 98 has a rectangular shape whose longitudinal direction is the vertical direction in the figure so that the entire contact hole 98 fits within the edge of the first film thickness portion 93 and intersects the metal extraction portion 79 at a right angle.
The display area 44 of the active matrix substrate 10z will be described below with reference to FIGS. 6, 7, and 8 (cross-sectional view taken along line B3-B4 in FIG. 6). That is, the entire drain extraction electrode 7 connected to the drain electrode 8 of the TFT 12 overlaps with the pixel electrode 17 and the storage capacitor wiring 18, and the gate insulating film in each pixel region is in the region overlapping with the drain extraction electrode 7. A thick film portion 81 having a large film thickness, and a thin film portion 91 having a small film thickness surrounding the thick film portion 81. The thick film portion 81 has the same configuration as the second film thickness portion 94 of FIG. 7 and is composed of first and second gate insulating layers. The thin film portion 91 has the same configuration as that of the first film thickness portion 93 of FIG. 7 and is composed only of the second gate insulating layer. The periphery of the thin film portion 91 has the same structure as that of the second film thickness portion 94 (consisting of the first gate insulating layer 21 and the second gate insulating layer 22). When viewed in plan, the outer periphery of the thin film portion 91 has a rectangular shape with the left-right direction as the longitudinal direction, and the entire outer periphery overlaps with the storage capacitor wiring 18 and the drain extraction electrode 7. As a result, the capacitance can be determined predominantly at the overlapping portion of the storage capacitor wiring 18, the drain extraction electrode 7, and the thin film portion 91. Inside the thin film portion 91, a rectangular thick film portion 81 whose longitudinal direction is the left-right direction is formed. Further, in each pixel region, a contact hole 83 that entirely overlaps with the thick film portion 81 is formed, and the drain extraction electrode 7 is connected to the pixel electrode 17 through the contact hole 83.
In addition, the gate insulating film in each pixel region is provided with a thin film portion 96 having a small thickness at a portion overlapping with the TFT 12. The thin film portion 96 has the same configuration as that of the first film thickness portion 93 and includes only the second gate insulating layer. Here, the overlapping area between the source electrode 9 and the thin film portion 96 is configured to be smaller than the overlapping area between the drain electrode 8 and the thin film portion 96.
Here, when the distance d between the boundary K between the first and second film thickness portions 93 and 94 and the edge of the end portion 18x of the storage capacitor wiring is small, the second interlayer in the vicinity of the contact hole 98 (non-display region). The difference (film thickness difference) between the thickness T1 (see FIG. 7) of the insulating film 26 and the thickness T2 (see FIG. 8) of the second interlayer insulating film 26 in the vicinity of the contact hole 83 (display area) becomes large. This is shown in the graph of FIG. The graph of FIG. 10 shows that in FIGS. 7 and 8, the first gate insulating layer 21 (SOG film) is 1.5 μm, the second gate insulating layer 22 is 0.4 μm, and the storage capacitor wiring (18 / 18x) is a film. A thickness of 0.3 μm, a thickness of the first interlayer insulating film 25 is 0.3 μm, a thickness of the second interlayer insulating film 26 is 2.5 μm, and a second interlayer using an acrylic photosensitive resin is used. When the viscosity of the insulating film 26 is 7.5 cp (centipoise), the relationship between the distance d and the film thickness difference is examined. From the graph of FIG. 10, it can be seen that when the distance d is 60 μm (preferably 70 μm) or more, the film thickness difference falls within a range (0.1 to 0.2 μm) within which exposure can be adjusted.
FIG. 33 shows a configuration of a liquid crystal panel including the active matrix substrate 10z and the color filter substrate (CF substrate) shown in FIG. As shown in FIG. 33, in the liquid crystal panel 504h, photo spacers 51 (first spacers) are arranged so as to overlap the scanning signal lines 16 in the display area 44, and each scanning is performed in the non-display area 55. A photo spacer 61 (second spacer) is disposed so as to overlap with the end 16x of the signal line. Although not shown, the photo spacers 51 are arranged at intervals in the left-right direction in the drawing so as to overlap the scanning signal lines 16 in the display area 44.
FIG. 34 is a cross-sectional view taken along the line arrow of the display area of FIG. 33 and a cross-sectional view taken along the line arrow of the non-display area. As shown in the figure, below the photo spacer 51 in the display area, the scanning signal line 16, the first gate insulating layer 21, the second gate insulating layer 22, and the first interlayer insulation are sequentially formed from the transparent insulating substrate 20 side. The film 25 and the second interlayer insulating film 26 are disposed, and the scanning signal line end 16x, the first gate insulating layer 21, A second gate insulating layer 22, a first interlayer insulating film 25, and a second interlayer insulating film 26 are disposed.
Even in the configuration of FIG. 33, since the structure under the photo spacer is the same between the non-display area and the display area, it is easy to set the height of each of the photo spacers 51 and 61, and between the display area 44 and the non-display area 55. The difference in cell gap can be reduced.
In addition, the interlayer insulating film containing the organic substance (second interlayer insulating film 26) is more elastic than inorganic films such as SiNx and SiO2. Therefore, in the configuration in which the display region and the non-display region photo spacers 51 and 61 are formed on the CF substrate side and the photo spacer is in contact with the active matrix substrate, the interlayer insulating film containing the organic substance (second interlayer insulating film) 26), the elastic deformation absorbs the thickness variation of the color filter layer and the black matrix on the CF substrate side, the variation of the spacer height, or the variation of the thickness of the active matrix substrate. is there. Note that an acrylic resin, an epoxy resin, a polyimide resin, a polyurethane resin, a polysiloxane resin, a novolac resin, or the like can be used for the interlayer insulating film containing the organic substance (second interlayer insulating film 26). .
FIG. 11 is a cross-sectional view showing a specific configuration of a liquid crystal panel including the present active matrix substrate. As shown in the figure, the liquid crystal panel 504 includes a polarizing plate 41, the active matrix substrate 10 (10x to 10z), an alignment film 82, a liquid crystal layer 43, and a color filter substrate (CF substrate) in order from the backlight light source side. 84 and a polarizing plate 85. The color filter substrate 84 includes a photo spacer (not shown), an alignment film 85, a common (counter) electrode 86, a color filter layer 87 (including a black matrix 99), and a glass substrate 88 in this order from the liquid crystal layer 43 side.
In the MVA liquid crystal panel as shown in FIG. 11, the common (counter) electrode 86 is provided with a liquid crystal molecular alignment control protrusion (rib) 86x. The liquid crystal molecule alignment control protrusion 86x is formed of, for example, a photosensitive resin. Examples of the planar shape of the rib 86x (a shape when viewed from the direction perpendicular to the substrate surface) include a band shape that is bent in a zigzag manner (for example, a horizontal V shape obtained by rotating a V shape by 90 degrees). In correspondence with the rib 86x on the CF substrate 84 side, the pixel electrode on the active matrix substrate 10 side has a strip shape that is bent in a zigzag manner at a constant cycle (for example, a horizontal V shape obtained by rotating the V shape by 90 degrees). Slits are formed. That is, when an MVA liquid crystal panel is formed using this active matrix substrate, the slits as described above are formed in the pixel electrodes 17 (first and second pixel electrodes 17a and 17b) shown in FIGS. Will be formed.
Next, a method for manufacturing a color filter substrate (CF substrate) will be described. As described above, the color filter substrate is a color filter layer composed of three primary colors (red, green, blue) color filters (colored layers) and a black matrix (BM), a counter electrode (common electrode) on a glass substrate. , A vertical alignment film, a rib (alignment control protrusion), and a photo spacer.
First, on a transparent substrate, a negative acrylic photosensitive resin in which carbon fine particles are dispersed is applied by spin coating, followed by drying to form a black photosensitive resin layer. Then, after exposing a black photosensitive resin layer through a photomask, it develops and forms a black matrix (BM). At this time, in the regions where the first colored layer (for example, red layer), the second colored layer (for example, green layer), and the third colored layer (for example, blue layer) are formed, the first colored layer opening, The BM is formed so that an opening for the second colored layer and an opening for the third colored layer (each opening corresponds to each pixel electrode) are formed.
Next, after applying a negative acrylic photosensitive resin in which a pigment is dispersed by spin coating, drying is performed, and exposure and development are performed using a photomask to form a red layer. Thereafter, the second color layer (for example, the green layer) and the third color layer (for example, the blue layer) are similarly formed, and the color filter is completed.
Furthermore, a counter electrode made of a transparent electrode such as ITO is formed by sputtering, and then a positive type phenol novolak photosensitive resin is applied by spin coating, followed by drying, and exposure and development using a photomask. An alignment control protrusion is formed.
Then, after applying and drying a negative acrylic photosensitive resin, a photo spacer is formed by exposing and developing using a photo mask.
The color filter substrate is completed as described above.
Next, a method of enclosing liquid crystal between the active matrix substrate and the color filter substrate when forming a liquid crystal panel will be described. As for the liquid crystal sealing method, an injection port is provided around the substrate for injecting the liquid crystal, the injection port is immersed in liquid crystal in a vacuum, the liquid crystal is injected by opening to the atmosphere, and then the injection port is sealed with UV curable resin or the like Alternatively, a vacuum injection method or the like may be used. However, in the vertically aligned liquid crystal panel, since the injection time is much longer than that in the horizontal aligned panel, it is preferable to use the liquid crystal dropping bonding method described below. First, a UV curable seal resin is applied around the active matrix substrate, and liquid crystal is dropped onto the color filter substrate by a dropping method. An optimum amount of liquid crystal is regularly dropped on the inner part of the seal so as to obtain a desired cell gap by liquid crystal by a liquid crystal dropping method. Next, after the color filter substrate and the active matrix substrate on which the seal drawing and liquid crystal dropping as described above are introduced into the bonding apparatus, the atmosphere in the bonding apparatus is reduced to 1 Pa. Bond the substrates. Thereafter, the atmospheric pressure in the apparatus is changed to atmospheric pressure, whereby the top of the photo spacer contacts the active matrix substrate, and a desired cell gap is obtained. Next, after the sealing resin is temporarily cured by UV irradiation, baking is performed in order to finally cure the sealing resin. At this time, the liquid crystal spreads inside the sealing resin and the liquid crystal is filled in the cell. Then, after baking is completed, the panel is divided into units and a polarizing plate is attached. Thus, the liquid crystal panel as shown in FIG. 11 is completed.
Next, the liquid crystal display device according to the present embodiment will be described.
FIG. 12 is a block diagram showing a schematic configuration of the present liquid crystal display device 509. As shown in FIG. 12, a liquid crystal display device 509 includes a Y / C separation circuit 500, a video chroma circuit 501, an A / D converter 502, a liquid crystal controller 503, a liquid crystal panel 504 having this active matrix substrate, and a backlight driving circuit 505. , A backlight 506, a microcomputer 507, and a gradation circuit 508.
An image signal or a video signal displayed on the liquid crystal display device 509 is input to the Y / C separation circuit 500 and separated into a luminance signal and a color signal. These luminance signals and color signals are converted into analog RGB signals corresponding to R, G, and B which are the three primary colors of light by the video chroma circuit 501. Further, the analog RGB signal is converted into a digital RGB signal by the A / D converter 502 and input to the liquid crystal controller 503.
The digital RGB signal input to the liquid crystal controller 503 is input from the liquid crystal controller 503 to the liquid crystal panel 504. A digital RGB signal is input to the liquid crystal panel 504 at a predetermined timing from the liquid crystal controller 503, and RGB gradation voltages are supplied from the gradation circuit 508. Further, the backlight driving circuit 505 drives the backlight 506 to irradiate the liquid crystal panel 504 with light. Thereby, the liquid crystal panel 504 displays an image and a video. In addition, the microcomputer 507 controls the entire liquid crystal display device 509 including the above processes.
Examples of the video signal include various video signals such as a video signal based on television broadcasting, a video signal picked up by a camera, and a video signal supplied via an Internet line.
Further, as shown in FIG. 13, the liquid crystal display device 509 of the present invention is connected to a tuner unit 600 that receives a television broadcast and outputs a video signal, so that the liquid crystal display device 509 is based on the video signal output from the tuner unit 600. Video (image) display can be performed. In this case, the liquid crystal display device 509 and the tuner unit 600 constitute a television receiver 601.
When the liquid crystal display device is a television receiver 601, for example, as shown in FIG. 14, the liquid crystal display device 509 is sandwiched between a first housing 801 and a second housing 806. ing. The first housing 801 is formed with an opening 801a through which an image displayed on the liquid crystal display device 509 is transmitted. The second housing 806 covers the back side of the liquid crystal display device 509. The second housing 806 is provided with an operation circuit 805 for operating the liquid crystal display device 509, and a support member 808 is attached below. ing.
The active matrix substrate of the present invention is suitable for a liquid crystal television, for example.
A plurality of storage capacitor wirings, a gate insulating film covering them, a trunk wiring provided above the gate insulating film, and an interlayer insulating film provided above the trunk wiring ,
Each storage capacitor wiring is connected to the trunk wiring by a connection electrode formed so as to fill a contact hole penetrating the gate insulating film and the trunk wiring and the interlayer insulating film in the non-display region,
The active matrix substrate, wherein the gate insulating film has a first film thickness part adjacent to the contact hole and a second film thickness part having a film thickness larger than the first film thickness part.
An active matrix substrate having first and second transistors, a first pixel electrode connected to the first transistor, and a second pixel electrode connected to the second transistor in each pixel region of the display region Because
First and second storage capacitor lines passing through each pixel region, a gate insulating film covering the first and second storage capacitor lines, and first and second layers provided above the gate insulating film A trunk wiring and an interlayer insulating film provided in an upper layer than the first and second trunk wirings ;
In the non-display region, the first storage capacitor wiring is connected to the first main wiring by a connection electrode formed so as to fill the first contact hole penetrating the gate insulating film, the main wiring, and the interlayer insulating film. The second storage capacitor line is connected to the second trunk line by a connection electrode formed so as to fill the second contact hole penetrating the gate insulating film, the trunk line, and the interlayer insulating film. ,
In the gate insulating film, a portion adjacent to the first contact hole and a portion adjacent to the second contact hole are each a first film thickness portion, and the film thickness is larger than those of the first film thickness portion. An active matrix substrate having a second film thickness portion having a large thickness.
A plurality of scanning signal lines, a gate insulating film covering the plurality of scanning signal lines, a lead wiring provided above the gate insulating film, and an interlayer insulating film provided above the lead wiring Prepared ,
Each scanning signal line is connected to the extraction wiring by a connection electrode formed so as to fill a contact hole penetrating the gate insulating film and the extraction wiring and the interlayer insulation film in the non-display region,
The gate insulating film is composed of a plurality of gate insulating layers,
The active matrix substrate according to claim 1, wherein at least one gate insulating layer is formed thinner than the other layers in the first film thickness portion.
The gate insulating film includes a plurality of gate insulating layers, the first film thickness portion includes one or more gate insulating layers, and the second film thickness portion includes more gate insulating layers than the first film thickness portion. The active matrix substrate according to any one of claims 1 to 3, wherein
The active matrix substrate according to claim 5 , further comprising a gate insulating layer containing an organic substance.
6. The active matrix substrate according to claim 5 , wherein the at least one gate insulating layer is a planarizing film.
6. The active matrix substrate according to claim 5 , wherein in the second film thickness portion, the lowermost gate insulating layer is a planarizing film.
An SOG film made of a spin-on glass (SOG) material is formed as a lowermost gate insulating layer in the second film thickness portion, whereas the SOG film is not formed in the first film thickness portion. The active matrix substrate according to claim 5 .
9. The active matrix substrate according to claim 8 , wherein a thickness of a portion of the planarizing film in contact with the substrate surface is larger than a thickness of metal wiring formed on the substrate surface.
2. The active matrix substrate according to claim 1, wherein the contact hole is divided into a plurality of parts.
The active matrix substrate according to claim 1, wherein the connection electrode is formed of the same material as the pixel electrode in the display region.
2. The active matrix substrate according to claim 1, wherein the main wiring is formed of the same material as that of the data signal line provided in the display area.
The upper layer of the gate insulating film, according to claim 1 to 3 comprising a first and second interlayer insulating film, the contact hole is characterized in that through the gate insulating film and the first and second interlayer insulating film The active matrix substrate according to any one of the above.
The display area having a pixel contact hole for connecting the transistor and the pixel electrode, claim gate insulating film below the intra-pixel contact hole, characterized in that the same structure as the second film thickness portion 14 The active matrix substrate as described.
16. The wiring lines connected by the contact holes in the non-display area are formed in different layers, and the entire intersection of the wiring lines is located within the outer periphery of the first film thickness portion. Active matrix substrate.
17. The active matrix substrate according to claim 16 , wherein, in the intersection, an interval between the edge of the wiring located on the lower layer side of both wirings and the edge of the first film thickness portion is 60 μm or more.
The active matrix substrate according to any one of claims 1 to 3, wherein the vicinity of the edge of the first film thickness portion in the gate insulating film is a forward tapered shape.
4. The active device according to claim 1, wherein the gate insulating film includes a thin film portion having a reduced film thickness in a region overlapping with the storage capacitor wiring in each pixel region. Matrix substrate.
The gate insulating film has a thin film portion with a reduced thickness in a portion overlapping with the gate electrode of the transistor in each pixel region,
Overlapping area between the source electrode of the thin film portion and the transistor, the active matrix substrate according to claim 1, characterized in that less than overlapping area between the drain electrode of the thin film portion and the transistor.
3. The active matrix substrate according to claim 2, wherein the potential of the first and second trunk lines is controlled so that the phases of the respective potential waveforms are shifted from each other by 180 degrees.
The potential of the first storage capacitor line is controlled so that the potential rises after the transistors are turned off and the state continues until the transistors are turned off in the next frame. The potential of the capacitor wiring is controlled so that the potential drops after each transistor is turned off and the state continues until each transistor is turned off in the next frame, or
The potential of the first storage capacitor line is controlled so that the potential drops after each transistor is turned off and the state continues until the transistor is turned off in the next frame, and the second holding capacitor line is 3. The active wiring according to claim 2, wherein the potential of the capacitor wiring is controlled so that the potential rises after each of the transistors is turned off and the state continues until the transistors are turned off in the next frame. Matrix substrate.
The potential of the first storage capacitor line is increased from the decrease of the potential of the second storage capacitor line by one horizontal period or the potential of the first storage capacitor line is decreased. 23. The active matrix substrate according to claim 22 , wherein the potential of the second storage capacitor wiring is shifted by one horizontal period.
3. The active matrix according to claim 2, wherein both wirings connected by each contact hole are formed in different layers, and the entire intersection of both wirings is located within the outer periphery of the first film thickness portion. substrate.
In the non-display area, the second storage capacitor wiring connected to the second trunk wiring intersects with the first trunk wiring,
The portion where the second storage capacitor line and the first trunk line intersect is located within the outer periphery of the first film thickness portion, but the second storage capacitor line and the first trunk line intersect. 25. The active matrix substrate according to claim 24, wherein a portion of the gate insulating film structure is the same as that of the second film thickness portion.
Two wirings, provided in the same layer as one of the two wirings, and an intersection wiring that intersects the other of the two wirings in a non-display region,
The gate insulating film covers one of the two wirings, the other of the two wirings is provided above the gate insulating film, and an interlayer insulating film is provided above the other of the two wirings;
One and the other of the two wirings are connected by a connection electrode formed so as to fill a contact hole penetrating the gate insulating film and the other of the two wirings and the interlayer insulating film in the non-display region,
The gate insulating film is located at a portion where the first film thickness portion adjacent to the contact hole intersects at least the other of the two wirings and the cross wiring, and is a second film having a thickness larger than that of the first film thickness portion. An active matrix substrate comprising a thick portion.
In each pixel region of the display region, the first and second transistors, the first pixel electrode connected to the first transistor, the second pixel electrode connected to the second transistor, and the first pixel electrode A first storage capacitor line crossing the bottom and a second storage capacitor line crossing the second pixel electrode;
The first storage capacitor line is connected to the first trunk line via a contact hole provided in the non-display area, and the second storage capacitor line is connected to the second trunk hole via a contact hole provided in the non-display area. Connected to the trunk wiring,
The first and second storage capacitor lines are formed in the same layer, and the first and second trunk lines are formed in the same layer;
First and second storage capacitor wiring and the scanning signal lines formed on the same layer, according to claim 26, wherein the intersecting at first and second trunk wirings, respectively and a non-display region Active matrix substrate.
A liquid crystal panel comprising the active matrix substrate according to claim 1 and a counter substrate facing the active matrix substrate, wherein a spacer and a liquid crystal layer are provided between both substrates,
Upper Symbol spacer is composed of a second spacer that is disposed on the first spacer and a non-display region that is disposed in the display area,
A liquid crystal panel, wherein a gate insulating film structure under a first spacer and a gate insulating film structure under a second spacer are the same.
29. The liquid crystal panel according to claim 28 , wherein a portion of the gate insulating film under the second spacer is a second film thickness portion.
Each of the first and second spacers is provided so as to overlap only one metal wiring covered with a gate insulating film, and the one metal wiring is a scanning signal line or a storage capacitor wiring. Item 29. A liquid crystal panel according to item 28 .
The first spacer is provided so as to overlap the intersection of the data signal line and the scanning signal line on the gate insulating film or the intersection of the data signal line and the storage capacitor line, and the second spacer is 29. The liquid crystal panel according to claim 28 , wherein the liquid crystal panel is provided so as to overlap an intersection of the trunk wiring and the scanning signal line or an intersection of the trunk wiring and the storage capacitor wiring.
29. The liquid crystal panel according to claim 28 , wherein the relative dielectric constant of the second spacer is smaller than the average relative dielectric constant of the liquid crystal material in the liquid crystal layer.
The gate insulating film has one or more gate insulating layers in the first film thickness portion and more gate insulating layers in the second film thickness portion than the first film thickness portion,
30. The liquid crystal panel according to claim 29 , wherein any one of the gate insulating layers is a planarizing film in the second film thickness portion.
The liquid crystal panel according to claim 29, wherein it contains a layer containing an organic material in the interlayer insulating film.
35. The liquid crystal panel according to claim 34 , wherein the organic substance is one of an acrylic resin, an epoxy resin, a polyimide resin, a polyurethane resin, a polysiloxane resin, and a novolac resin.
A liquid crystal panel comprising the active matrix substrate according to claim 25 and a counter substrate facing the active matrix substrate, wherein a spacer and a liquid crystal layer are provided between the substrates.
The spacer includes a first spacer disposed in the display area and a second spacer disposed in the non-display area.
A second spacer is provided so as to overlap a portion where the second storage capacitor wiring and the first trunk wiring intersect, and the gate insulating film structure under the first spacer is a gate insulating film under the second spacer. Is identical to the structure,
The liquid crystal panel according to claim 1, wherein a relative dielectric constant of the second spacer is smaller than an average relative dielectric constant of the liquid crystal material in the liquid crystal layer.
37. The liquid crystal according to claim 36 , wherein the first spacer is provided so as to overlap an intersecting portion between the data signal line and the scanning signal line or any one of the storage capacitor lines on the gate insulating film. panel.
A liquid crystal panel comprising the active matrix substrate according to claim 3 and a counter substrate facing the active matrix substrate, wherein a spacer and a liquid crystal layer are provided between the substrates.
A liquid crystal panel comprising the active matrix substrate according to claim 1.
A display device comprising the active matrix substrate according to claim 1.
41. A television receiver comprising: the display device according to claim 40; and a tuner unit that receives a television broadcast.
JP2008525797A 2006-07-19 2007-03-30 Active matrix substrate, liquid crystal panel, display device, television receiver Active JP4907659B2 (en)
JP2006197319 2006-07-19
JP2006332592 2006-12-08
PCT/JP2007/057049 WO2008010334A1 (en) 2006-07-19 2007-03-30 Active matrix substrate, liquid crystal panel, display, television receiver
JP2008525797A JP4907659B2 (en) 2006-07-19 2007-03-30 Active matrix substrate, liquid crystal panel, display device, television receiver
JPWO2008010334A1 JPWO2008010334A1 (en) 2009-12-17
JP4907659B2 true JP4907659B2 (en) 2012-04-04
ID=38956669
JP2008525797A Active JP4907659B2 (en) 2006-07-19 2007-03-30 Active matrix substrate, liquid crystal panel, display device, television receiver
US (1) US8330883B2 (en)
EP (4) EP2383607A1 (en)
JP (1) JP4907659B2 (en)
CN (2) CN101421663B (en)
WO (1) WO2008010334A1 (en)
KR101490472B1 (en) * 2008-07-28 2015-02-05 삼성디스플레이 주식회사 ThinFilm Transistor Display Panel and Liquid Crystal Display Having the Same
US8520157B2 (en) * 2008-09-19 2013-08-27 Sharp Kabushiki Kaisha Display device
KR101359864B1 (en) * 2009-02-16 2014-02-06 샤프 가부시키가이샤 Tft array substrate, and liquid crystal display panel
CN102473368B (en) * 2009-07-16 2014-09-17 夏普株式会社 Active matrix substrate and active matrix display device
KR101359825B1 (en) 2009-12-04 2014-02-07 샤프 가부시키가이샤 Liquid crystal display device
JP5849489B2 (en) * 2011-07-21 2016-01-27 セイコーエプソン株式会社 Electro-optical device, projection display device, electronic apparatus, and method of manufacturing electro-optical device
CN103928453B (en) 2013-01-11 2016-09-28 北京京东方光电科技有限公司 A kind of array base palte and manufacture method thereof
JP2956380B2 (en) 1992-09-28 1999-10-04 日本電気株式会社 Thin film transistor array and a manufacturing method thereof
JP3229419B2 (en) 1993-02-10 2001-11-19 ダウ・コ−ニング・コ−ポレ−ション The method of forming the silicon oxide film
JPH07114044A (en) 1993-10-19 1995-05-02 Sanyo Electric Co Ltd Production of liquid crystal display device
JP2565148B2 (en) 1995-03-31 1996-12-18 セイコーエプソン株式会社 Method of manufacturing a matrix array
JP3234168B2 (en) 1997-05-20 2001-12-04 株式会社アドバンスト・ディスプレイ Method for producing Tft array substrate
2007-03-30 EP EP11005407A patent/EP2383607A1/en not_active Withdrawn
2007-03-30 CN CN 200780013043 patent/CN101421663B/en active IP Right Grant
2007-03-30 US US12/297,928 patent/US8330883B2/en active Active
2007-03-30 CN CN 201010622370 patent/CN102096259B/en active IP Right Grant
2007-03-30 EP EP11005409A patent/EP2385423A1/en not_active Withdrawn
2007-03-30 EP EP07740485A patent/EP2042916A4/en not_active Withdrawn
2007-03-30 EP EP11005408A patent/EP2385422A1/en not_active Withdrawn
2007-03-30 WO PCT/JP2007/057049 patent/WO2008010334A1/en active Application Filing
2007-03-30 JP JP2008525797A patent/JP4907659B2/en active Active
WO2008010334A1 (en) 2008-01-24
EP2385422A1 (en) 2011-11-09
JPWO2008010334A1 (en) 2009-12-17
EP2042916A4 (en) 2010-10-13
CN101421663A (en) 2009-04-29
EP2042916A1 (en) 2009-04-01
CN102096259A (en) 2011-06-15
CN101421663B (en) 2012-06-13
EP2385423A1 (en) 2011-11-09
CN102096259B (en) 2013-07-24
US20090091671A1 (en) 2009-04-09
EP2383607A1 (en) 2011-11-02
US8330883B2 (en) 2012-12-11
US8421982B2 (en) 2013-04-16 Display substrate, method of manufacturing the display substrate and display apparatus having the display substrate
KR20030079809A (en) 2003-10-10 In-plane switching mode active matrix type liquid crystal display device and method of fabricating the same
Ref document number: 4907659