Source: https://patents.google.com/patent/US7846777
Timestamp: 2018-02-24 10:32:54
Document Index: 713254972

Matched Legal Cases: ['art 150', 'art 150', 'art 150', 'art 150', 'art 150', 'art 150', 'art 150', 'art 150', 'art 150', 'art 150']

US7846777B2 - Semiconductor device package and fabricating method thereof - Google Patents
Semiconductor device package and fabricating method thereof
US7846777B2
US7846777B2 US12176110 US17611008A US7846777B2 US 7846777 B2 US7846777 B2 US 7846777B2 US 12176110 US12176110 US 12176110 US 17611008 A US17611008 A US 17611008A US 7846777 B2 US7846777 B2 US 7846777B2
US12176110
US20090020881A1 (en )
A loading part 150 a may be formed on a top surface of the base substrate 150. For example, the loading part 150 a may be formed by concavely etching the top surface of the base substrate 150. A bottom surface of the loading part 150 a may be formed flat to enable the first to third chips 110, 120, and 130 to be placed thereon. Edges 150 b of the base substrate 150 may be formed higher than the loading surface (i.e., bottom surface) of the loading part 150 a.
The base substrate 150 may include a substrate formed of a hard material. For instance, the base substrate 150 may include a silicon substrate.
Edges 150 b of the base substrate 150 can be formed higher than a loading surface (i.e., bottom surface) of the loading part 150 a.
Referring to FIG. 4, first to third chips 110, 120 and 130 may be arranged on the loading part 150 a of the base substrate 150.
The trenches 167T and 167T′ may be formed between via holes 167V for connecting the first and second chips 110 and 120 electrically or between via holes 167V′ for connecting the second and third chips 120 and 130 electrically. In particular, the trench 167T may be formed by partially etching a portion of the second preliminary insulating layer 163 a between the via holes 167V on the first and second chips 110 and 120 to be thinner than adjacent portions of the second preliminary insulating layer 163 a. Analogously, the other trench 167T′ may be formed by partially etching a portion of the second preliminary insulating layer 163 a between the via holes 167V′ on the second and third chips 120 and 130 to be thinner than adjacent portions of the second preliminary insulating layer 163 a.
Thus, a first hole pattern 167 a, including the via holes 167V on the first and second chips 110 and 120 and the trench 167 located between the via holes 167V, may be formed. In addition, a second hole pattern 167 b, including the via holes 167V′ on the second and third chips 120 and 130 and the trench 167T′ located between the via holes 167V′, may thus be formed.
Referring to FIG. 9, portions of the second and third chips 120 and 130 may be exposed by etching corresponding portions of the first preliminary insulating layer 161 a exposed via the first and second hole patterns 167 a and 167 b. Moreover, by etching portions of the first preliminary insulating layer 161 a exposed through the third hole patterns 165, corresponding portions of the base substrate 150 may be exposed. In this manner a first insulating layer 161 may be formed upon etching the first preliminary insulating layer 161 a.
Referring to FIG. 10, a metal layer 170 may be formed on the second insulating layer 163. The metal layer 170 may include, for example, a Cu metal layer.
Between the first and second chips 110 and 120, a first wire 271 may be formed. The first wire 271 may electrically connect the first and second chips 110 and 120 via the via metal patterns 283 formed within the holes in the first hole patterns 267 a.
Between the second and third chips 120 and 130, a second wire 272 may be formed. The second wire 272 may electrically connect the second and third chips 120 and 130 via the via metal patterns 283 formed within holes in the second hole patterns 267 b.
The first and second wires 271 and 272 may include at least one material selected from the group consisting of Cu, W, Al, Ti and Ta.
In FIG. 13, base substrate 150 may include a loading part 150 a for enabling chips to be mounted thereon. The loading part 150 may include a recess formed on a topside of the base substrate 150. Moreover, an edge 150 b of the base substrate 150 can be formed higher than a loading surface (i.e., bottom surface) of the loading part 150 a.
Referring further to FIG. 13, first to third chips 110, 120 and 130 may be mounted on the loading part 150 a of the base substrate 150.
A size or width of holes in the third hole pattern 265 may be smaller than that of holes in the first or second hole patterns 267 a or 267 b. The holes in third hole patterns 265 may also differ from the holes in first or second hole patterns 267 a or 267 b in depth. Yet, since the first insulating layer 161 is used as an etch-stop layer in etching the second insulating layer 263, it is able to protect the chips during formation of holes in the hole patterns 265, 267 a, and 267 b.
Referring to FIG. 15, a barrier layer 281 a may be formed over the base substrate 150 including the second insulating layer 263. A via metal layer 283 a may then be formed on the barrier layer 281 a.
The barrier layer 281 a and the via metal layer 283 are not deposited within holes in the third hole pattern 265. This is because the third hole pattern 265 is smaller in size than the first or second hole pattern 267 a or 267 b. For instance, a hole of the third hole pattern 265 is smaller than that of the first or second pattern 267 a or 267 b. Moreover, if the barrier layer 281 a is deposited by physical vapor deposition (PVD) with a thickness greater than the size of the third hole pattern 265, overhang of the barrier layer 281 a is generated at an opening of each hole in the third hole pattern 265. Therefore, a void may be formed within each hole in the third hole pattern 265.
Although the holes in the third hole pattern 265 are externally opened again, whereby an air layer can be formed within the holes, the barrier layer pattern 281 and the via metal pattern 283 each remain on inner surfaces of holes in the first and second hole patterns 267 a and 267 b.
Referring to FIG. 17, a metal layer 270 may be formed over the base substrate 150 including the second insulating layer 263. The metal layer 270 may include, for example, Al.
By patterning and selectively etching portions of the metal layer 270 corresponding to the topsides of the third hole patterns 265, holes can be opened to expose the voids in the third hole patterns 265. Portions of the metal layer 270 may also be etched to form the first wire 271 between the first and second chips 110 and 120 and to form the second wire 272 between the second and third chips 120 and 130. The first wire 271 may electrically connect the first and second chips 120 and 130 via the via metal pattern 283 formed within the holes in the first hole patterns 267 a. Analogously, the second wire 272 may electrically connect the second and third chips 120 and 130 via the via metal pattern 283 formed within holes in the second hole patterns 267 b.
Referring to FIG. 19, a third insulating layer 280 a may be formed over the substrate having the first and second wires 271 and 272 formed thereon to planarize or protect the semiconductor device package 200. The third insulating layer 280 a may include, for example, a silicon nitride layer.
forming a hole pattern at a position of the planarizing layer corresponding to the heat-dissipation hole pattern on the insulating layer by patterning the planarizing layer to open holes in the heat-dissipation hole pattern on the insulating layer.
US12176110 2007-07-19 2008-07-18 Semiconductor device package and fabricating method thereof Expired - Fee Related US7846777B2 (en)
KR10-2007-0072163 2007-07-19
KR20070072163A KR100871794B1 (en) 2007-07-19 2007-07-19 Semiconductor device package and method for fabricating the same
US20090020881A1 true US20090020881A1 (en) 2009-01-22
US7846777B2 true US7846777B2 (en) 2010-12-07
ID=40264178
US12176110 Expired - Fee Related US7846777B2 (en) 2007-07-19 2008-07-18 Semiconductor device package and fabricating method thereof
US (1) US7846777B2 (en)
KR (1) KR100871794B1 (en)
CN (1) CN101350344B (en)
KR101284220B1 (en) 2012-07-06 2013-07-09 (주) 이피웍스 An etching method for through silicon via of acute type semiconductor wafer
CN105789064A (en) * 2016-03-18 2016-07-20 深圳芯邦科技股份有限公司 Package method and package structure for fingerprint identification chip
US20050254215A1 (en) 2004-05-11 2005-11-17 Michael Khbeis Use of thermally conductive vias to extract heat from microelectronic chips and method of manufacturing
KR100244965B1 (en) 1997-08-12 2000-02-15 윤종용 Method for manufacturing printed circuit board(PCB) and ball grid array(BGA) package
KR100390453B1 (en) * 1999-12-30 2003-07-04 앰코 테크놀로지 코리아 주식회사 semiconductor package with such circuit board and method for fabricating the same
KR100806031B1 (en) 2006-11-27 2008-02-26 동부일렉트로닉스 주식회사 Semiconductor device and the fabrication method thereof
US20090020881A1 (en) 2009-01-22 application
CN101350344A (en) 2009-01-21 application
KR100871794B1 (en) 2008-12-02 grant
CN101350344B (en) 2012-07-04 grant
Owner name: DONGBU HITEK CO., LTD., KOREA, DEMOCRATIC PEOPLE S
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KIM, SANG CHUL;REEL/FRAME:021264/0241