Source: http://www.google.com/patents/US20070290376?dq=7,177,838
Timestamp: 2017-05-24 05:35:28
Document Index: 249802331

Matched Legal Cases: ['in fine', 'art 1000', 'art 1000', 'art 1000', 'art 1000', 'art 1000', 'art 1000', 'art 1000']

Patent US20070290376 - Integrated circuit (IC) package stacking and IC packages formed by same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsMethods, systems, and apparatuses for integrated circuit (IC) package vertical interconnection are described herein. In an aspect of the invention, an IC package includes an IC die with contact pads. The IC package also includes interconnect members which are coupled to the die at the contact pads. An...http://www.google.com/patents/US20070290376?utm_source=gb-gplus-sharePatent US20070290376 - Integrated circuit (IC) package stacking and IC packages formed by sameAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20070290376 A1Publication typeApplicationApplication numberUS 11/589,120Publication dateDec 20, 2007Filing dateOct 30, 2006Priority dateJun 20, 2006Also published asCN101127344A, CN101127344B, EP1870932A1, EP1870932B1, US8581381Publication number11589120, 589120, US 2007/0290376 A1, US 2007/290376 A1, US 20070290376 A1, US 20070290376A1, US 2007290376 A1, US 2007290376A1, US-A1-20070290376, US-A1-2007290376, US2007/0290376A1, US2007/290376A1, US20070290376 A1, US20070290376A1, US2007290376 A1, US2007290376A1InventorsSam Ziqun Zhao, Rezaur Rahman KhanOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (38), Referenced by (239), Classifications (57), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetIntegrated circuit (IC) package stacking and IC packages formed by same
US 20070290376 A1Abstract
an IC die having a plurality of contact pads; a plurality of interconnect members coupled to the plurality of contact pads; and an encapsulating material that encapsulates the IC die and the interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material. 2. The IC package of claim 1, wherein each interconnect member is a truncated solder ball.
a substrate having a first surface that mounts the IC die; and a second plurality of interconnect members; wherein the first surface of the substrate has a plurality of contact pads; wherein the second plurality of interconnect members are each coupled to a corresponding contact pad of the plurality of contact pads on the first surface of the substrate; wherein the second plurality of interconnect members are encapsulated by the encapsulating material such that a contact surface of each interconnect member of the second plurality of interconnect members is accessible at the surface of the encapsulating material. 5. The package of claim 1, wherein each interconnect member of the plurality of interconnect members comprises a metal.
a second IC package coupled to the first IC package through the plurality of interconnect members of the first IC package. 11. The stacked integrated circuit (IC) packaging device of claim 10,
wherein the surface of the encapsulating material has a cavity in which the contact surface of each of the interconnect members is accessible, wherein the second IC package is disposed at least partially in the cavity. 12. The stacked integrated circuit (IC) packaging device of claim 10, wherein each interconnect member is a truncated solder ball.
a substrate having a first surface that mounts the IC die; and a second plurality of interconnect members; wherein the first surface of the substrate has a plurality of contact pads; wherein the second plurality of interconnect members are each coupled to a corresponding contact pad of the plurality of contact pads on the first surface of the substrate; wherein the second plurality of interconnect members are encapsulated by the encapsulating material such that a contact surface of each interconnect member of the second plurality of interconnect members is accessible at the surface of the encapsulating material. wherein the second IC package is coupled to the first IC package through the second plurality of interconnect members. 14. The stacked integrated circuit (IC) packaging device of claim 10, wherein the second IC package further comprises a plurality of solder balls attached to a bottom surface of the second IC package;
wherein each solder ball of the plurality of solder balls is coupled to a corresponding contact surface of an interconnect member of the plurality of interconnect members. 15. The stacked integrated circuit (IC) packaging device of claim 10, wherein each interconnect member of the plurality of interconnect members comprises a metal.
(a) attaching an IC die to a first surface of a substrate, the die having a plurality of contact pads; (b) coupling a plurality of interconnect members to the plurality of contact pads; (c) coupling the die and the substrate with at least one wirebond; (d) encapsulating the die and the plurality of interconnect members in an encapsulating material; and (e) at least partially exposing the plurality of interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material. 21. The method of claim 20, further comprising the step of:
(f) mounting a plurality of solder balls to a second surface of the substrate. 22. The method of claim 20, wherein step (e) further comprising:
removing a layer of the encapsulating material. 23. The method of claim 20, wherein step (e) further comprising:
forming a cavity in the encapsulating material. 24. The method of claim 20, wherein step (c) is performed before step (b).
(b) coupling a second IC package to the first IC package at the plurality of interconnect members of the first IC package. 27. The method of claim 26, wherein step (a) further comprises:
(6) mounting a plurality of solder balls to a second surface of the substrate. 28. The method of claim 26, wherein step (a)(5) further comprises:
removing a layer of the encapsulating material. 29. The method of claim 26, wherein step (a)(5) further comprising:
forming a cavity in the encapsulating material. 30. The method of claim 28, wherein step (a)(3) is performed before step (a)(2).
coupling each solder ball of the plurality of solder balls to a corresponding contact surface of an interconnect member of the plurality of interconnect members. 33. An integrated circuit (IC) package, comprising:
a substrate having a plurality of contact pads on a first surface; an IC die mounted to the first surface of the substrate; a plurality of interconnect members coupled to the plurality of contact pads; and an encapsulating material that encapsulates the IC die and the interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material. 34. The IC package of claim 33, wherein each interconnect member is a truncated solder ball.
(a) attaching an IC die to a first surface of a substrate, the first surface of the substrate having a plurality of contact pads; (b) coupling a plurality of interconnect members to the plurality of contact pads; (c) coupling the die and the substrate with at least one wirebond; (d) encapsulating the die and the plurality of interconnect members in an encapsulating material; and (e) at least partially exposing the plurality of interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material. Description
[0001] This application claims the benefit of U.S. Provisional Appl. No. 60/814,875, filed Jun. 20, 2006, which is herein incorporated by reference in its entirety.
[0003] The invention relates generally to the field of integrated circuit (IC) device packaging technology, and more particularly to package to package interconnection of IC packages.
[0005] The die-up plastic ball grid array package (PBGA) was first introduced by Motorola and was called an overmolded plastic pad array carriers (OMPAC). See Freyman, and Pennisi, “Overmolded Plastic Pad Array Carriers (OMPAC): A Low Cost, High Interconnect Density IC Packaging Solution for Consumer and Industrial Electronics,” Electronic Components and Technology Conference, IEEE, pp. 176-182, (1991), which is incorporated by reference herein in its entirety.
[0006] A PBGA package features a plastic printed circuit board (substrate) typically made of BT (Bismaleimide Triazine) resins or FR4 materials. FIG. 1 shows a conventional PBGA package 100. An integrated circuit (IC) die 102 is attached directly to a top surface of a substrate 110 using a die attach material 106. Wirebonds 114 are used to electrically connect the integrated circuit of IC die 102 to the printed circuit of substrate 110. A matrix of solder balls 108 is mounted on the bottom side of substrate 110. Die 102 and wirebonds 114 are protected from the environment by a plastic molding compound 112. Mold compound 112 encapsulates both die 102 and the wirebond 114, and covers a center region of the top surface of the substrate 110. A periphery of the top surface of substrate 110 is left exposed. FIGS. 2A-2B show plan and side views of PBGA package 100.
[0007] A conventional PBGA package, such as package 100, has numerous drawbacks, including: (1) a thick top mold (e.g., mold compound 112) and a large overall package profile height; (2) a small ratio of die size to package size due to a mold cap which must be clamped to the package substrate 110 for molding; and (3) a large package body size.
[0008] The Joint Electron Device Engineering Council (JEDEC) has a standard for mold thickness standard for PBGA packages, which is 1.17 mm. With a mold thickness of 1.17 mm, the overall height of a typical PBGA package is in the range of 1.5 mm˜2.5 mm. However, a thinner package is more desirable for many applications, such as hand-held communication devices (cell phones, global positioning devices, watch-size communication devices, etc.), mobile multimedia (video/audio) players, wireless personal area networking devices such as Bluetooth headsets, and flash memory devices and memory cards.
[0009] A mold chase with multiple mold caps (mold cavities) is used for mold encapsulation of the JEDEC standard PBGA packages. PBGA package substrates are typically formed in a strip or panel of substrates. Each individual substrate unit in a substrate strip or panel has a corresponding mold cap of the mold chase for molding. Typically, a thermoset molding epoxy is applied in each mold cap, and the mold chase is applied to the substrate strip. In a finished package, the periphery of the top surface of each substrate is exposed as shown in FIGS. 1, 2A, and 2B (i.e., not covered by molding compound 112). Prior to application of the mold compound, both the IC die and the wirebonds must be placed within a mold cavity. Additionally, the IC die and the wirebonds must be kept far enough away from the inner walls of the mold cavity to allow for mold flow and to avoid wire sweeping. Therefore, the size of the IC die is limited by the size of the mold cap (i.e., the mold cavity). Therefore, for a PBGA package, the maximum size of the die must be substantially smaller than the substrate.
[0010] Thus, conventional PBGA packages are typically large in body size, ranging from 19 mm×19 mm and above. Large package sizes are undesirable for mobile applications where bulky electronic components make for bulky devices.
[0011] To reduce package size, chip scale packages have been developed where the size of the IC die is very close to the size of package. FIGS. 3A and 3B respectively show a perspective view and a cross-sectional view of a fine pitch ball grid array (FBGA) package 300. Similarly to PBGA package 100 described above, in FBGA package 300, a die 102 is mounted to a substrate 110 by a die attach material 106. IC die 102 is electrically connected by a plurality of wire bonds 114 to conductive features (e.g., traces, bond fingers, etc) such as a trace 210 on a top surface of a substrate 110. Mold compound 112 encapsulates die 102, wirebond 114, and the entire top surface of substrate 110. Solder balls 108 of FBGA package 300 may be smaller than solder balls 108 of PBGA package 100, and a smaller ball pitch may be used to space solder balls of FBGA package 300. In addition to the smaller solder balls 108 and smaller ball pitch, thickness of mold compound 112 is reduced to 0.25 mm˜0.7 mm. Molding compound 112 covers the entire top surface of FBGA package 300, enabling an increase in the ratio of the size of die 102 to the size of substrate 110 in FBGA package 300 versus PBGA package 100.
[0012] However, while providing some improvement, FBGA packages still suffer from the disadvantages described above with regard to PBGA packages. Thus, what are needed are IC packages that have small size and can accommodate large and complex ICs.
[0013] Methods, systems, and apparatuses for integrated circuit (IC) package to package vertical interconnection are described herein. The invention relates to numerous IC package types, including ball grid array (BGA) packages.
[0014] In an aspect of the invention, a first IC package is modified to expose a plurality of interconnect contact pads. A BGA package is stacked upon the first IC package. In an aspect, solder balls attached to a bottom surface of the BGA package are coupled to the interconnect members, which are accessible on the top surface of the first IC package.
[0015] In an aspect of the invention, an IC package includes an IC die with die contact pads. The IC die is encapsulated in an encapsulating material, such as a mold compound. The IC package also includes interconnect members which are electrically coupled to the die at the die contact pads, to form interconnect contact pads at the external surface of the IC package
[0016] In an alternative aspect, an IC package includes an IC die mounted to a first surface of a substrate. The IC package also includes interconnect members which are electrically coupled to the first surface of the substrate. The IC die and interconnect members are encapsulated in an encapsulating material. A top portion of the interconnect members is not covered by the encapsulating material to form interconnect contact pads at the external surface of the IC package.
[0017] In another aspect of the invention, a cavity is formed in the encapsulating material, in which the interconnect contact pads are exposed.
[0018] In an aspect of the invention, a first IC package includes a die, one or more interconnect members, a substrate, an encapsulating material encapsulating the die and interconnect members. The first IC package is electrically coupled to a second IC package through the interconnect members.
[0019] In an aspect of the invention, an IC package is manufactured by a method which includes attaching an IC die to a substrate, electrically coupling interconnect members to the die and/or the substrate, electrically connecting the die to the substrate by a wirebonding process, encapsulating the package, and at least partially exposing at least some of the interconnect members.
[0020] In one aspect of the invention, the interconnect members are exposed by removing an entire layer of an encapsulating material. In another aspect of the invention, the interconnect members are exposed by forming a cavity in the encapsulating material.
[0021] In an aspect of the invention, a package-on-package (PoP) stack is manufactured. An IC die is attached to a first surface of a substrate using a die attach material. Interconnect members are electrically coupled to the die and/or the first surface of the substrate. The die is electrically connected to the substrate using a wire bonding process. In this manner, a first IC package is formed. The first package is encapsulated in an encapsulating material. The interconnect members are at least partially exposed. A second IC package is mounted to the first IC package.
[0022] These and other objects, advantages and features will become readily apparent in view of the following detailed description of the invention. Note that the Summary and Abstract sections may set forth one or more, but not all exemplary embodiments of the present invention as contemplated by the inventor(s).
[0023] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.
[0024] FIG. 1 illustrates a conventional plastic ball grid array (PBGA) integrated circuit (IC) package.
[0025] FIGS. 2A-2B illustrate views of the PBGA IC package of FIG. 1.
[0026] FIGS. 3A-3B illustrate views of a conventional fine pitch ball grid array (FBGA) IC package.
[0027] FIGS. 4A-4B illustrate cross-sectional views of conventional package on package (PoP) stacked IC devices.
[0028] FIGS. 5A-5D illustrate views of example FBGA IC packages having interconnect members, according to exemplary embodiments of the invention.
[0029] FIGS. 6A-6D illustrate cross-sectional views of example FBGA IC packages having interconnect members, according to exemplary embodiments of the invention.
[0030] FIGS. 7A-7D illustrate cross-sectional views of example PoP stacked IC packages, according to exemplary embodiments of the invention.
[0031] FIGS. 8A-8B illustrate cross-sectional views of example PoP stacked IC packages, according to exemplary embodiments of the invention.
[0032] FIGS. 9A and 9B illustrates cross-sectional views of example PoP stacked IC packages, according to exemplary embodiments of the invention.
[0033] FIG. 10 illustrates an example flowchart for manufacturing IC packages, according to exemplary embodiments of the invention.
[0034] FIGS. 11A-11H illustrate cross-sectional views of example IC packages at various stages of manufacture, according to exemplary embodiments of the invention.
[0035] FIGS. 12A-12C illustrate cross-sectional views of example IC packages at various stages of manufacture, according to exemplary embodiments of the invention.
[0036] The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.
[0037] Methods, systems, and apparatuses for IC device packaging technology are described herein. In particular, methods, systems, and apparatuses for package to package interconnection of IC packages to form improved IC packages are described.
[0038] References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
[0039] The present specification discloses one or more embodiments that incorporate the features of the invention. The disclosed embodiment(s) merely exemplify the invention. The scope of the invention is not limited to the disclosed embodiment(s). The invention is defined by the claims appended hereto.
[0040] Furthermore, it should be understood that spatial descriptions (e.g., “above”, “below”, “left,” “right,” “up”, “down”, “top”, “bottom”, etc.) used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner.
[0041] In an embodiment, a package to package interconnect structure provides electrical coupling from a die (or dice) of a first package through an encapsulating material of the first IC package to a second IC package. The interconnect structure provides an interconnect contact pad for the attachment of a solder ball of the second IC package. In an embodiment, an array of interconnect members of the first IC package provide an array of interconnect contact pads for an array of solder balls on the bottom of the second IC package. The array of interconnect members of the first IC package provide a short interconnection path between an IC die (or dice) in the first IC package and electrical terminals of the second IC package. The combination of the first and second IC packages form a third IC package with compact size that accommodates at least two IC dies.
[0042] Conventional IC die encapsulation processes such as dam-and-fill (glob top), mold cap injection molding (transfer molding), and strip or panel over-molding (mold compound covers the edges of package substrate) can be used in embodiments of the first and second packages. Embodiments of the invention apply to many existing package technologies, including ball grid array (BGA) packages (e.g., fine pitch BGA (FBGA), plastic BGA (PBGA)), land grid array (LGA) packages, and leadframe packages. Furthermore, different package types may be stacked to form an improved IC package, including the stacking of leadframe packages on BGA packages, the stacking of BGA packages on leadframe packages, and other combinations. Although the detailed description provided herein typically describes first and second packages, persons of ordinary skill in the relevant art(s) would realize that the second package can be the “first package” for another “second package,” etc. Thus, in embodiments, a stack may include numbers of stacked IC packages of two or more IC packages.
[0043] PBGA and FBGA packages are examples of conventional IC packages. Package on package (PoP) stacked IC packages referred to “as package stackable very-thin fine-pitch Ball Grid Array” (PSvfBGA) packages exist. See Dreiza et al, “Implement Stacked Package-on-Package Designs,” at http://www.eetasia.com/ARTICLES/2005OCT/B/2005OCT17_EDA_MFG_A.pdf) (hereinafter “Dreiza”), which is incorporated by reference herein in its entirety. FIGS. 4A-4B show examples of stacked PSvfBGA packages. FIG. 4A shows a stacked IC package 400. As shown in FIG. 4A, stacked IC package 400 includes a package-to-package interconnection made by mounting a top BGA package 430 to a substrate 410 of a bottom BGA package 440. Top and bottom BGA packages 430 and 440 are very fine-pitch BGA packages.
[0044] Bottom package 440 has exposed land pads 420 on a top surface of substrate 410, that provide contact areas for solder balls 108 on a bottom surface of top BGA package 430. Exposed land pads 420 are located at a periphery of the top surface of substrate 110, surrounding a mold compound 112 formed on the top surface of bottom package 440. Top package 430 can be attached to bottom package 440 using a conventional reflow surface mount process.
[0045] FIG. 4B illustrates a stacked IC package 450, that includes a package-to-package interconnection made by mounting a top BGA package 480 to a substrate 410 of a bottom package 490. Top and bottom BGA packages 480 and 490 are very fine-pitch BGA packages. Stacked IC package 450 has reduced overall package stack height because IC die 406 of bottom package 490 is positioned within a window opening through substrate 410 of package 490.
[0046] However, a size of die 406 in bottom package 490 is limited in this configuration. As shown in FIG. 4A, the interconnection between top package 430 and bottom package 440 is made at the peripheral region of substrate 410 (outside mold compound 112) of bottom package 440. IC die 406 and wirebond 114 of bottom package 440 must be encapsulated with mold compound 112. Thus, a mold cap must be sized to prevent mold compound 112 from covering or contaminating exposed land pads 420. The mold cap cavity must be smaller than substrate 410. Thus, bottom IC package 440 must be similar to PBGA (as shown in FIGS. 2A-2B), and cannot be an overmold type (e.g., the FBGA package 300 shown in FIGS. 3A-3B) where the periphery of substrate 410 is covered by mold compound 112. Thus, the size of die 406 in bottom package 440 is limited such that both die 406 and wirebond 114 fit within mold compound 112, which must be sized to leave the periphery of substrate 410 exposed.
[0047] Moreover, under some circumstances it is advantageous to minimize mechanical stress between the top and bottom packages by using the same size and type of packages (i.e., with exactly the same structure, die or dice sizes, substrate and/or die carrier structure, etc.) for both the bottom and top packages. In such configurations, the top and bottom package is a PBGA package or similar type with a poor die size to substrate size ratio. Thus, what is lacking in conventional stacked IC packages is an interconnection structure that maximizes the die size for a given package body size for the bottom package. Embodiments of the present invention, described in the next section, enable larger die sizes for the bottom package in a stack.
[0048] FBGA packages, as described above (e.g., package 300 shown in FIGS. 3A-3B), have a better die to substrate ratio and a thinner mold chase. Thus, stacking FBGA packages may reduce the overall footprint and the overall stack height (or increase the number of packages in a stack for a given height). Therefore, a way to stack FBGA packages is desirable. Embodiments of the present invention, described in the next section, enable stacking of FBGA packages.
[0049] Additionally, many applications require high speed and broad bandwidth signaling between IC chips (e.g., 3rd generation wireless communication technologies (3G) integrated with high-speed voice, data, and video functions). A reduced interconnect electrical impedance between stacked packages is needed to support these applications. A more direct die to package interconnection within the PoP stacking structure is thus desirable. Embodiments of the present invention, described in the next section, enable more a direct connection of die-to-package in a stack.
[0050] Overmolded area array packages such as FBGA and land grid array (LGA) packages do not have electrical signal interconnect terminals on package top surface. The same problem exists for some types of leadframe packages, such as no-lead quad flat packages (QFN) (also known as micro leadframe packages (MLP, MLF), and plastic leadless chip carrier (PLCC) packages), and thin array plastic packages (TAPP). Consequently, these package types cannot have other packages stacked on their top. Therefore, what is needed is a way to stack overmolded package types. Embodiments of the present invention, described in the next section, enable such stacking. Example Interconnect Members
[0051] In an embodiment, a plurality of interconnect members enable a PoP interconnection, where a second IC package is stacked on a first IC package. An interconnect member may be an electrically conductive ball (e.g., solder ball), block, lump, or other regular or irregular object/material that makes an electrical connection through an encapsulation material of the first IC package.
[0052] Interconnect members are represented in the attached figures as spherical in shape, such as solder balls. However, interconnect members are shown in this manner for illustrative purposes, and are not intended to be limited to spheres. Any electrically conductive material in any shape may serve as an interconnect in different embodiments of the invention. For example, interconnect members may alternatively be electrically conductive posts/pins. The posts/pins may be formed before or after application of the encapsulation material. For example, if formed after application of the encapsulation material, holes may be drilled through the encapsulation material, the a metal or other electrically conductive material may be inserted into the holes (in liquid, gas, or solid form) to form the posts/pins. Furthermore, the interconnect members may be balls other than solder balls, such as balls made from a different metal, such as copper, aluminum, gold, nickel, tin, silver, or a combination of metals/alloy.
[0053] Furthermore, in an embodiment, the balls may have a core made of a first material that is covered by a shell made from a second material. For example, a core-shell ball may be a core ball made of copper covered by a shell of solder material. In an embodiment, an interconnect member is made of a core material that is coated with a bonding material such as solder, gold, silver, an epoxy, or other joining materials that mechanically bonds the thermal interconnect member with contact pads.
[0054] In embodiments, the interconnect members extend through the encapsulation material. In one embodiment, the interconnect members are truncated. For example, a top layer (or a portion of a top layer) of the encapsulation material may be removed from the bottom IC package, removing a top portion of the interconnect members in the process. In this manner, the interconnect members are thus exposed and provide a relatively uniform array of interconnect contact pads on an external surface of the package. These interconnect contact pads may be used for interconnection with a second IC package. In an embodiment, the plurality of interconnect members are mounted to a top surface of an IC die. In another embodiment, the plurality of interconnect members are mounted to a top surface of the package substrate.
[0055] Example embodiments of the present invention are described in detail below.
[0056] FIGS. 5A-5D illustrate views of example IC packages, according to embodiments of the present invention. FIG. 5A shows a perspective cutaway view of an FBGA package 500. In package 500, an IC die 102 is electrically connected by a plurality of wire bonds 114 to conductive features (e.g., traces, bond fingers, etc) on a top surface of a substrate 110. The conductive features on the top surface of substrate 110 are electrically coupled through substrate 110 (e.g., through one or more electrically and/or non-electrically conductive layers) to solder ball pads on a bottom surface of substrate 110. Furthermore the top and/or bottom surfaces of substrate 110 may be partially coated with non-electrically conductive material, such as a solder mask material, to insulate selected electrically conductive features on the top and bottom surfaces from short circuiting, etc. Conductive features on the top surface of substrate 114 to which wirebonds 114 connect are not covered with the non-electrically conductive material. Solder balls 108 are coupled to the solder ball pads, and are configured to be coupled to a circuit board, such as a printed circuit board (PCB) or printed wire board (not shown in FIGS. 5A-5D).
[0057] As shown in FIG. 5A, a top surface of die 102 has a plurality of contact pads 502. FIG. 5B shows a perspective cutaway view of an FBGA package 500, with interconnect members 508 visible. In FIG. 5B, interconnect members 508 are attached to corresponding contact pads 502. In embodiments, die 102 can have any number of contact pads 502, each for coupling with an interconnect member 508. Contact pads 502 are electrically coupled to electrical signals of die 102, including input/output signals, power signals, grounds signals, etc. Encapsulating material 512 encapsulates package 500. In the embodiments of FIGS. 5B-5D, interconnect members 508 are completely covered with encapsulating material 512. Encapsulating material 512 can be any type of encapsulating material used in IC packages that is described elsewhere herein, or is otherwise known, including an epoxy, a molding compound, etc.
[0058] FIGS. 5C and 5D respectively show a perspective cutaway view and a perspective view of an FBGA package 550. Package 550 is similar to package 500, except that encapsulating material 512 does not encapsulate top surfaces 504 of interconnect members 508. In an embodiment, a top layer of encapsulating material 512 is removed to expose surfaces 504 of interconnect members 508. In such an embodiment, interconnect members 508 are truncated to form the planar exposed surfaces 504 of interconnect members 508, and surfaces 504 are co-planar with a top surface of encapsulating material 512. Surfaces 504 can also be referred to as “electrical contact pads” or “interconnect contact pads.” Exposed surfaces 504 on package 550 can be used for electrical connections (e.g., signal, ground, or power) to die 102 for devices external to package 550. Various methods exist to truncate the spheres embedded in a package encapsulating material, including those further described below. FIG. 5D shows the external view of an example completed package 550. Interconnect contact pads 504 are visible on the external surface of encapsulating material 512.
[0059] In an embodiment, surfaces 504 exposed on package 550 may be used for a package-to-package electrical interconnection to form a stacked IC package. Many electronic components, including IC packages, inductors, capacitors, resistors, transistors, diodes, etc., can be electrically connected to package 550 at surfaces (contact pads) 504.
[0060] In an embodiment, interconnect members 508 are truncated. Various processes which may be used to truncate interconnect members 508 while removing a layer of encapsulating material 512, such as grinding, routing, other surface machining methods, and chemical etching processes.
[0061] FIGS. 6A-6C illustrate example IC packages, according to embodiments of the present invention. FIG. 6A shows a package 600 in which interconnect members 508 are attached to a top surface of die 102. Encapsulating material 512 encapsulates the top surface of substrate 110, die 102, and wirebonds 114. Furthermore, interconnect members 508 are fully encapsulated by encapsulating material 512. FIG. 6B illustrates an example package 650, where a top layer of encapsulating material 512 has been removed and interconnect members 508 have been thereby truncated. Surfaces (interconnect contact pads) 504 are formed on the top surface of encapsulating material 512.
[0062] FIG. 6C shows a package 660 in which only a portion of a layer 662 of encapsulating material 512 is removed, forming a cavity 664 in encapsulating material 512. In package 660, cavity 664 is formed centrally in the top surface of encapsulating material 512, in a volume of encapsulating material 512 in which a top portion of interconnect members 512 were present. Interconnect members 508 are truncated (the top portion removed) due to the formation of cavity 664. The truncation of interconnect members 508 results in the presence of surfaces (interconnect contact pads) 504 on the surface of encapsulating material 512, inside cavity 664.
[0063] In further embodiments, any number of one or more cavities 664 may be formed in encapsulating material 512 over interconnect members 512 to expose surfaces 504.
[0064] FIG. 6D shows a package 670, according to another example embodiment of the present invention. In package 670, a plurality of interconnect members 508 are mounted to electrically conductive features 604 (e.g., contact pads, bond fingers, traces, etc) on a top surface 602 of substrate 110. Interconnect members 508 are truncated (the top portion removed). The truncation of interconnect members 508 results in the presence of surfaces (interconnect contact pads) 504 on the surface of encapsulating material 512. Interconnect members 508 can be formed on top surface 602 of substrate 110 in an configuration, including a regular array, one or more rings of interconnect members 508 around die 102 on top surface 602, and any irregular configuration of interconnect members 508, where any number of interconnect members 508 are positioned as desired on top surface 602. For example, as shown in FIG. 6D, a single interconnect member 508 is shown to the left side of die 102 on top surface 602, while two interconnect members 508 are shown to the right side of die 102 on top surface 602.
[0065] FIGS. 7A-7D illustrate example embodiments of stacked FBGA packages. FIG. 7A illustrates a stacked IC package 700 that includes a second IC package 740 mounted on a first IC package 730. Second package 730 is configured similarly to package 300 shown in FIG. 3B. First package 740 is configured similarly to package 650 of FIG. 6B. Solder balls 108 on a bottom surface of substrate 110 of second package 730 are electrically coupled a plurality of interconnect members 508 accessible at a top surface 702 of encapsulating material 112 of first IC package 740. In particular, solder balls 108 are attached to surfaces 504 of interconnect members 508.
[0066] In the embodiment of FIG. 7A, each of solder balls 108 of second package 730 are coupled to a respective interconnect member 508 of first package 740. As illustrated in FIGS. 7B-7C, in embodiments, not all solder balls 108 of second package 730 are necessarily required to be electrically coupled to interconnect members 508. For example, in FIG. 7B, solder balls 708 are not electrically coupled to interconnect members 508, while solder balls 108 are coupled to interconnect members 508. In FIG. 7B, solder balls 708 are peripheral solder balls of an array of solder balls on a bottom surface 704 of second package 730. Solder balls 108 are inner solder balls of the array of solder balls on bottom surface 704 of second package 730. For example, solder balls 708 may form one or more rings of solder balls around solder balls 108. In FIG. 7C, ring shaped gap 706 that is depopulated of solder balls is present (i.e., one or more rings of solder balls are not present) between solder balls 708 and solder balls 108 on bottom surface 704 of second package 730.
[0067] In an embodiment, solder balls 708 may provide access to test signals of die 102 of second package 730 for testing of second package 730. In another embodiment, solder balls 708 may provide mechanical support for second package 730 on first package 740 at the peripheral areas of second package 730, by contacting top surface 702 of encapsulating material 512 of first package 740. In yet another embodiment, solder balls 708 serve no specific purpose or a combination of purposes.
[0068] As described above, in embodiments, first and second packages 740 and 730 may be identical in size and/or configuration, or may have different sizes and/or configurations. For example, FIG. 7D illustrates an example embodiment where second package 730 is physically smaller than the first package 740 (e.g., substrate 110 of second package 730 has a lesser area than a substrate of first package 740). In an embodiment, substrate 110 of second package 730 may have a width (and/or area) substantially the same or less than a width (and/or area) of die 102 of first package 740.
[0069] As described herein, in an embodiment, encapsulating material 512 may have a cavity 664. For example, FIGS. 8A-8B show exemplary embodiments of a stacked IC package 800 that includes a second FBGA package 830 mounted on a first FBGA package 840. In FIG. 8A, first package 840 has cavity 664 formed in encapsulating material 512. Interconnect members 508 have surfaces 504 accessible on a bottom surface 802 of cavity 664. Solder balls 108 on bottom surface 704 of second package 830 are electrically coupled to interconnect members 508 at surfaces 504.
[0070] In the embodiment of FIG. 8B, second package 830 resides entirely in cavity 664. In alternative embodiments, such as shown in FIG. 8A, only solder balls of second package 830 reside partially or entirely in cavity 664. Any portion of second package 830 may reside partially or entirely in cavity 664.
[0071] Furthermore, FIG. 8B illustrates an exemplary embodiment where die 102 of first package 840 is wider than cavity 664. Such an arrangement may enable second package 830 to be positioned very close to die 102 of first package 840, allowing for very short interconnect members 508, and therefore short signal paths, while keeping wirebonds 114 of first package 840 protected in encapsulating material 512. Another advantage is that a total height of stacked package 850 may be reduced.
[0072] Interconnect members 508 are not limited to electrically coupling a die in a first IC package to the bottom surface of the substrate of a second IC package. For example, FIG. 9A shows a stacked IC package 900 in which a second package 930 is mounted on a first package 940. First package 940 is similar to package 670 shown in FIG. 6D. In stacked IC package 900, a first plurality of interconnect members 508 are coupled between die 102 of first package 940 and solder balls 108 of second package 930, and a second plurality of interconnect members 508 are electrically coupled between a top surface 902 of substrate 110 in first package 940 and solder balls 108 of second package 930. Thus, as shown in FIG. 9A, interconnect members 508 may be mounted to electrically conductive features 904 (e.g., contact pads, bond fingers, traces, etc) on top surface 902 of substrate 110, to be coupled to solder balls 108 of second package 930 through encapsulating material 512.
[0073] FIG. 9B shows a stacked IC package 950, according to another example embodiment of the present invention. Package 950 includes a second package 960 mounted on a first package 970. First package 970 is similar to package 940 and second package 960 is similar to second package 930 shown in FIG. 9A, except that interconnect members are not present between die 102 of first package 970 and solder balls 108 of second package 960. In FIG. 9B, interconnect members 508 are mounted to electrically conductive features 904 (e.g., contact pads, bond fingers, traces, etc) on top surface 902 of substrate 110, to be coupled to solder balls 108 of second package 960 through encapsulating material 512.
[0074] The exemplary embodiments described above are not limited to FBGA or similar IC packages. Persons of ordinary skill in the relevant art(s) will understand that embodiments of the invention are applicable to many current and future IC package configurations or combinations of configurations.
[0075] FIGS. 10, 11A-11H, and 12A-12C illustrate example embodiments related to manufacturing of stacked IC packages. Although the IC packages illustrated in FIGS. 11A-11H and 12A-12C are BGA packages, the manufacturing embodiments described herein are applicable to other current and future IC package configurations and technologies.
[0076] FIG. 10 shows a flowchart 1000, which illustrates an example process for manufacturing a stacked IC package. Flowchart 1000 is described with reference to FIGS. 11A-11H, which show an example FBGA package a various phases of assembly. Steps 1002-1014 of flowchart 1000 form a first IC package with a plurality of interconnect contact pads. Step 1012 stacks a second IC package on the first IC package to form a stacked IC package. Note that the steps of flowchart 1000 do not necessarily have to be performed in the order shown. Flowchart 1000 is described in detail as follows.
[0077] In step 1002, a die is mounted to a substrate. For example, the die is die 102, which is attached to substrate 110 using die attach material 106, as shown in FIG. 11A. For example, die attach material 106 may be a conventional die attach material, such as an epoxy and/or a film adhesive.
[0078] In step 1004, one or more package interconnect members are mounted on the top surface of the IC die. For example, as shown in FIG. 11B, a plurality of interconnect members 508 are mounted on die 102. In an embodiment, interconnect members 508 are mounted onto die contact pads 502 on top surface of IC die 102, as shown in FIG. 5A. In another embodiment, interconnect members 508 may also be coupled to top surface 902 of substrate 110, as shown in FIG. 9.
[0079] In step 1006, wire bonds are coupled between the IC die and the substrate. For example, as shown in FIG. 11C, IC die 102 is connected to substrate 110 through a wire bonding process that applies wirebonds 114.
[0080] In step 1008, an encapsulating material is applied. For example, as shown in FIG. 11D, encapsulating material 512 is applied to top surface 902 of substrate 110 to encapsulate die 102, wirebonds 114, and interconnect members 508.
[0081] In step 1010, at least a portion of a top layer of encapsulating material 512 is removed. In an embodiment, interconnect members 508 are truncated, where a top portion of interconnect members 508 is removed along with some or all of a top layer of encapsulating material 512. Steps 1010 a and 1010 b illustrate two example optional ways of implementing step 1010. For example, in optional step 1010 a, an entire layer of encapsulating material 512 is removed. For instance, as shown in FIG. 11E, a grinding tool 1102 grinds away a top layer of encapsulating material 512 to truncates and expose interconnect members 508. In optional step 1010 b, a cavity is formed in encapsulating material 512. For example, as shown in FIG. 11F, a routing tool 1104 routes a cavity 664 into a top layer 662 of encapsulating material 512, to truncate and expose interconnect members 508. Other methods of material removal, such as chemical, mechanical, or laser machining may be used in step 1010 to remove a portion of encapsulating material 512 to expose and/or truncate interconnect members 508. Alternatively, cavity 664 can be formed in encapsulating material 512 using a mold, such as when encapsulating material 512 is applied to substrate 110.
[0082] In step 1012, solder balls are mounted to the bottom surface of the substrate. For example, as shown in FIG. 11G, solder balls 108 are formed on a bottom surface 1110 of substrate 110. The solder balls may be mounted using conventional ball mount methods. FIG. 11G illustrates a first package 1180, which is the product of steps 1002-1012.
[0083] In step 1014, a second IC package is mounted on the formed first package. For example, as shown in FIG. 11H, a second IC package 1130 is mounted on first IC package 1180. Solder balls 108 on bottom surface 704 of second IC package 1130 are attached to interconnect members 508, such as by reflow soldering, an electrically conductive adhesive, and/or other way.
[0084] In a further embodiment, second IC package 1130 may have interconnect members 508 mounted thereon, and another IC package may be mounted to second IC package 1130. This process may be repeated to stack as many packages as desired.
[0085] As described above, the steps of flowchart 1000 may be performed in various orders. For example, in another exemplary embodiment, wire bonding (e.g., step 1006) may be performed before interconnect members are attached to the die (e.g., step 1004). Furthermore, for example, application of solder balls to the first package (e.g., step 1012) may be performed after the second package is mounted to the first package (e.g., step 1014). The steps of flowchart 1000 may be varied in many ways, as would be apparent to persons skilled in the relevant art(s) from the teachings herein.
[0086] For these example embodiments, solder balls were used as the package interconnect structure as an example. Other electrically conductive materials and structures can also be used to form the package-to-package interconnect contact structure on mold top by extending the electrical contact on area array package (BGA, LGA, PGA, etc.) substrate top through mold encapsulation and expose electrical contact terminals on mold top surface. For example, metal posts can be attached to the substrate top contact pads and exposed on mold top surface.
[0087] While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6303997 *Apr 7, 1999Oct 16, 2001Anam Semiconductor, Inc.Thin, stackable semiconductor packagesUS6411396 *Feb 24, 1999Jun 25, 2002Adobe Systems IncorporatedImposition in a raster image processorUS6501184 *May 19, 2000Dec 31, 2002Amkor Technology, Inc.Semiconductor package and method for manufacturing the sameUS6548911 *Aug 3, 2001Apr 15, 2003Siliconware Precision Industries Co., Ltd.Multimedia chip packageUS6653723 *Mar 9, 2002Nov 25, 2003Fujitsu LimitedSystem for providing an open-cavity low profile encapsulated semiconductor packageUS6707140 *May 9, 2000Mar 16, 2004National Semiconductor CorporationArrayable, scaleable, and stackable molded package configurationUS6717245 *Jun 2, 2000Apr 6, 2004Micron Technology, Inc.Chip scale packages performed by wafer level processingUS6765287 *Nov 29, 2002Jul 20, 2004Charles W. C. LinThree-dimensional stacked semiconductor packageUS6933175 *Mar 13, 2003Aug 23, 2005Siliconware Precision Industries Co., Ltd.Method of fabricating a thin and fine ball-grid array package with embedded heat spreaderUS7026709 *Sep 25, 2004Apr 11, 2006Advanced Semiconductor Engineering Inc.Stacked chip-packaging structureUS7038315 *Apr 12, 2001May 2, 2006Micron Technology, Inc.Semiconductor chip packageUS7067911 *Oct 15, 2004Jun 27, 2006Bridge Semiconductor CorporationThree-dimensional stacked semiconductor package with metal pillar in encapsulant apertureUS7102225 *Jul 23, 2002Sep 5, 2006Broadcom CorporationDie-up ball grid array package with printed circuit board attachable heat spreaderUS7245008 *Jun 30, 2004Jul 17, 2007Samsung Electronics Co., Ltd.Ball grid array package, stacked semiconductor package and method for manufacturing the sameUS7262080 *May 21, 2004Aug 28, 2007Samsung Electronics Co., Ltd.BGA package with stacked semiconductor chips and method of manufacturing the sameUS7262082 *Aug 3, 2006Aug 28, 2007Bridge Semiconductor CorporationMethod of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant apertureUS7271024 *Oct 13, 2005Sep 18, 2007Siliconware Precision Industries Co., Ltd.Method for fabricating sensor semiconductor deviceUS7276802 *Apr 15, 2002Oct 2, 2007Micron Technology, Inc.Semiconductor integrated circuit package having electrically disconnected solder balls for mountingUS7288835 *Mar 17, 2006Oct 30, 2007Stats Chippac Ltd.Integrated circuit package-in-package systemUS7354800 *Apr 27, 2006Apr 8, 2008Stats Chippac Ltd.Method of fabricating a stacked integrated circuit package systemUS7372151 *Sep 12, 2003May 13, 2008Asat Ltd.Ball grid array package and process for manufacturing sameUS7385299 *Feb 25, 2006Jun 10, 2008Stats Chippac Ltd.Stackable integrated circuit package system with multiple interconnect interfaceUS7435619 *Feb 14, 2006Oct 14, 2008Stats Chippac Ltd.Method of fabricating a 3-D package stacking systemUS20010042913 *May 16, 2001Nov 22, 2001Kabushiki Kaisha ToshibaSemiconductor device, method of manufacturing semiconductor device, resin molding die, and semiconductor manufacturing systemUS20020100976 *Jan 30, 2001Aug 1, 2002Hui Chong ChinBOC semiconductor package including a semiconductor die and a substrate bonded circuit side down to the dieUS20020190396 *Aug 12, 2002Dec 19, 2002Brand Joseph M.Method and apparatus for removing encapsulating material from a packaged microelectronic deviceUS20040052060 *Jul 14, 2003Mar 18, 2004Staktek Group, L.P.Low profile chip scale stacking system and methodUS20040145039 *Sep 30, 2003Jul 29, 2004St Assembly Test Services Ltd.Stacked semiconductor packages and method for the fabrication thereofUS20040178499 *Mar 10, 2003Sep 16, 2004Mistry Addi B.Semiconductor package with multiple sides having package contactsUS20040183174 *Jan 29, 2004Sep 23, 2004Siliconware Precision Industries Co., Ltd.Semiconductor package with enhanced electrical and thermal performance and method for fabricating the sameUS20050023657 *Sep 25, 2004Feb 3, 2005Yu-Fang TsaiStacked chip-packaging structureUS20050046006 *Apr 29, 2004Mar 3, 2005Kun-Dae YeomUnit semiconductor chip and multi chip package with center bonding pads and methods for manufacturing the sameUS20060006534 *Jul 21, 2005Jan 12, 2006Yean Tay WMicroelectronic devices and methods for packaging microelectronic devicesUS20060012037 *Jun 30, 2005Jan 19, 2006Raedt Walter DMethods for bonding and devices according to such methodsUS20070158806 *Jan 12, 2006Jul 12, 2007Stats Chippac Ltd.Integrated circuit package system including honeycomb moldingUS20070158809 *Jan 4, 2006Jul 12, 2007Chow Seng GMulti-chip package systemUS20070210432 *Mar 10, 2006Sep 13, 2007Stats Chippac Ltd.Stacked integrated circuits package system with passive componentsUS20070273049 *Jan 11, 2007Nov 29, 2007Broadcom CorporationInterconnect structure and formation for package stacking of molded plastic area array package* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7632753Oct 4, 2007Dec 15, 2009Amkor Technology, Inc.Wafer level package utilizing laser-activated dielectric materialUS7642133Jul 26, 2007Jan 5, 2010Advanced Semiconductor Engineering, Inc.Method of making a semiconductor package and method of making a semiconductor deviceUS7656031 *Jun 6, 2007Feb 2, 2010Bridge Semiconductor CorporationStackable semiconductor package having metal pin within through hole of packageUS7670962Sep 19, 2007Mar 2, 2010Amkor Technology, Inc.Substrate having stiffener fabrication methodUS7671457Nov 9, 2006Mar 2, 2010Amkor Technology, Inc.Semiconductor package including top-surface terminals for mounting another semiconductor packageUS7692286Aug 5, 2008Apr 6, 2010Amkor Technology, Inc.Two-sided fan-out wafer escape packageUS7714431Nov 28, 2006May 11, 2010Amkor Technology, Inc.Electronic component package comprising fan-out and fan-in tracesUS7714453Jan 11, 2007May 11, 2010Broadcom CorporationInterconnect structure and formation for package stacking of molded plastic area array packageUS7719110Sep 18, 2007May 18, 2010Broadcom CorporationFlip chip package including a non-planar heat spreader and method of making the sameUS7723210Jun 6, 2007May 25, 2010Amkor Technology, Inc.Direct-write wafer level chip scale packageUS7750250Dec 22, 2006Jul 6, 2010Amkor Technology, Inc.Blind via capture pad structureUS7752752Jan 9, 2007Jul 13, 2010Amkor Technology, Inc.Method of fabricating an embedded circuit patternUS7755164Jun 21, 2006Jul 13, 2010Amkor Technology, Inc.Capacitor and resistor having anodic metal and anodic metal oxide structureUS7777351 *Oct 1, 2007Aug 17, 2010Amkor Technology, Inc.Thin stacked interposer packageUS7781266Aug 4, 2009Aug 24, 2010Broadcom CorporationMethods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packagesUS7808087Sep 27, 2006Oct 5, 2010Broadcom CorporationLeadframe IC packages having top and bottom integrated heat spreadersUS7825520May 5, 2009Nov 2, 2010Amkor Technology, Inc.Stacked redistribution layer (RDL) die assembly packageUS7832097Jan 23, 2008Nov 16, 2010Amkor Technology, Inc.Shielded trace structure and fabrication methodUS7842541Sep 24, 2008Nov 30, 2010Amkor Technology, Inc.Ultra thin package and fabrication methodUS7872335Nov 30, 2007Jan 18, 2011Broadcom CorporationLead frame-BGA package with enhanced thermal performance and I/O countsUS7898093Nov 2, 2006Mar 1, 2011Amkor Technology, Inc.Exposed die overmolded flip chip package and fabrication methodUS7901988 *Aug 8, 2008Mar 8, 2011Eems Asia Pte LtdMethod for forming a package-on-package structureUS7902660May 24, 2006Mar 8, 2011Amkor Technology, Inc.Substrate for semiconductor device and manufacturing method thereofUS7911037Aug 5, 2009Mar 22, 2011Amkor Technology, Inc.Method and structure for creating embedded metal featuresUS7923645Jun 20, 2007Apr 12, 2011Amkor Technology, Inc.Metal etch stop fabrication method and structureUS7932170Jun 23, 2008Apr 26, 2011Amkor Technology, Inc.Flip chip bump structure and fabrication methodUS7932595Mar 19, 2010Apr 26, 2011Amkor Technology, Inc.Electronic component package comprising fan-out tracesUS7932605 *Aug 8, 2007Apr 26, 2011Kabushiki Kaisha ToshibaSemiconductor device and manufacturing method thereforUS7951697Jun 20, 2007May 31, 2011Amkor Technology, Inc.Embedded die metal etch stop fabrication method and structureUS7958626Oct 25, 2007Jun 14, 2011Amkor Technology, Inc.Embedded passive component network substrate fabrication methodUS7960827Apr 9, 2009Jun 14, 2011Amkor Technology, Inc.Thermal via heat spreader package and methodUS7977163Jul 2, 2009Jul 12, 2011Amkor Technology, Inc.Embedded electronic component package fabrication methodUS7989950 *Aug 14, 2008Aug 2, 2011Stats Chippac Ltd.Integrated circuit packaging system having a cavityUS8012797Aug 25, 2009Sep 6, 2011Advanced Semiconductor Engineering, Inc.Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometriesUS8017436Dec 10, 2007Sep 13, 2011Amkor Technology, Inc.Thin substrate fabrication method and structureUS8018068Oct 28, 2009Sep 13, 2011Amkor Technology, Inc.Semiconductor package including a top-surface metal layer for implementing circuit featuresUS8022538 *Nov 17, 2008Sep 20, 2011Stats Chippac Ltd.Base package system for integrated circuit package stacking and method of manufacture thereofUS8026587Jun 10, 2010Sep 27, 2011Amkor Technology, Inc.Semiconductor package including top-surface terminals for mounting another semiconductor packageUS8035235 *Sep 15, 2009Oct 11, 2011Stats Chippac Ltd.Integrated circuit packaging system with package-on-package and method of manufacture thereofUS8076765Jul 22, 2009Dec 13, 2011Advanced Semiconductor Engineering, Inc.Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductorsUS8110909Jan 5, 2010Feb 7, 2012Amkor Technology, Inc.Semiconductor package including top-surface terminals for mounting another semiconductor packageUS8119455Mar 18, 2011Feb 21, 2012Amkor Technology, Inc.Wafer level package fabrication methodUS8143101Mar 21, 2008Mar 27, 2012Advanced Semiconductor Engineering, Inc.Semiconductor package and the method of making the sameUS8158888Jun 23, 2009Apr 17, 2012Advanced Semiconductor Engineering, Inc.Circuit substrate and method of fabricating the same and chip package structureUS8169058 *Aug 21, 2009May 1, 2012Stats Chippac, Ltd.Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillarsUS8169067Oct 20, 2006May 1, 2012Broadcom CorporationLow profile ball grid array (BGA) package with exposed die and method of making sameUS8176628Dec 23, 2008May 15, 2012Amkor Technology, Inc.Protruding post substrate package structure and methodUS8183680Jul 5, 2006May 22, 2012Broadcom CorporationNo-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancementUS8183687Feb 16, 2007May 22, 2012Broadcom CorporationInterposer for die stacking in semiconductor packages and the method of making the sameUS8188584Mar 19, 2010May 29, 2012Amkor Technology, Inc.Direct-write wafer level chip scale packageUS8198131Jul 29, 2010Jun 12, 2012Advanced Semiconductor Engineering, Inc.Stackable semiconductor device packagesUS8203203Sep 27, 2010Jun 19, 2012Amkor Technology, Inc.Stacked redistribution layer (RDL) die assembly packageUS8207022Jan 27, 2011Jun 26, 2012Amkor Technology, Inc.Exposed die overmolded flip chip package methodUS8222538Jun 12, 2009Jul 17, 2012Amkor Technology, Inc.Stackable via package and methodUS8222722 *Sep 11, 2009Jul 17, 2012St-Ericsson SaIntegrated circuit package and deviceUS8227338Aug 1, 2011Jul 24, 2012Amkor Technology, Inc.Semiconductor package including a top-surface metal layer for implementing circuit featuresUS8270176 *Aug 8, 2008Sep 18, 2012Stats Chippac Ltd.Exposed interconnect for a package on package systemUS8278746Apr 2, 2010Oct 2, 2012Advanced Semiconductor Engineering, Inc.Semiconductor device packages including connecting elementsUS8288852 *Oct 9, 2009Oct 16, 2012Elpida Memory, Inc.Semiconductor deviceUS8294276May 27, 2010Oct 23, 2012Amkor Technology, Inc.Semiconductor device and fabricating method thereofUS8298866Jan 26, 2012Oct 30, 2012Amkor Technology, Inc.Wafer level package and fabrication methodUS8300423May 25, 2010Oct 30, 2012Amkor Technology, Inc.Stackable treated via package and methodUS8316536May 9, 2008Nov 27, 2012Amkor Technology, Inc.Multi-level circuit substrate fabrication methodUS8319338Jul 8, 2010Nov 27, 2012Amkor Technology, Inc.Thin stacked interposer packageUS8322030Nov 1, 2007Dec 4, 2012Amkor Technology, Inc.Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patternsUS8323771Aug 15, 2007Dec 4, 2012Amkor Technology, Inc.Straight conductor blind via capture pad structure and fabrication methodUS8324511Apr 6, 2010Dec 4, 2012Amkor Technology, Inc.Through via nub reveal method and structureUS8337657Oct 27, 2010Dec 25, 2012Amkor Technology, Inc.Mechanical tape separation package and methodUS8338229Jul 30, 2010Dec 25, 2012Amkor Technology, Inc.Stackable plasma cleaned via package and methodUS8341835May 5, 2009Jan 1, 2013Amkor Technology, Inc.Buildup dielectric layer having metallization pattern semiconductor package fabrication methodUS8368194Jun 4, 2012Feb 5, 2013Amkor Technology, Inc.Exposed die overmolded flip chip packageUS8383950Apr 6, 2011Feb 26, 2013Amkor Technology, Inc.Metal etch stop fabrication method and structureUS8389329May 31, 2011Mar 5, 2013Stats Chippac Ltd.Integrated circuit packaging system with package stacking and method of manufacture thereofUS8390116Mar 18, 2011Mar 5, 2013Amkor Technology, Inc.Flip chip bump structure and fabrication methodUS8390130Jan 6, 2011Mar 5, 2013Amkor Technology, Inc.Through via recessed reveal structure and methodUS8405212Jun 18, 2010Mar 26, 2013Advanced Semiconductor Engineering, Inc.Semiconductor packageUS8426956Aug 12, 2010Apr 23, 2013Samsung Electronics Co., Ltd.Semiconductor package structure having plural packages in a stacked arrangementUS8440554Aug 2, 2010May 14, 2013Amkor Technology, Inc.Through via connected backside embedded circuit features structure and methodUS8471154Aug 6, 2009Jun 25, 2013Amkor Technology, Inc.Stackable variable height via package and methodUS8471394Oct 7, 2011Jun 25, 2013Stats Chippac Ltd.Integrated circuit packaging system with package-on-package and method of manufacture thereofUS8472199 *Feb 6, 2009Jun 25, 2013Mosaid Technologies IncorporatedSystem including a plurality of encapsulated semiconductor chipsUS8476748Oct 31, 2012Jul 2, 2013Amkor Technology, Inc.Exposed die overmolded flip chip package and fabrication methodUS8482134Nov 1, 2010Jul 9, 2013Amkor Technology, Inc.Stackable package and methodUS8486764Sep 26, 2012Jul 16, 2013Amkor Technology, Inc.Wafer level package and fabrication methodUS8487445Oct 5, 2010Jul 16, 2013Amkor Technology, Inc.Semiconductor device having through electrodes protruding from dielectric layerUS8501543May 16, 2012Aug 6, 2013Amkor Technology, Inc.Direct-write wafer level chip scale packageUS8502387 *Dec 9, 2010Aug 6, 2013Stats Chippac Ltd.Integrated circuit packaging system with vertical interconnection and method of manufacture thereofUS8508045Jun 30, 2011Aug 13, 2013Broadcom CorporationPackage 3D interconnection and method of making sameUS8508954Oct 22, 2010Aug 13, 2013Samsung Electronics Co., Ltd.Systems employing a stacked semiconductor packageUS8525318Nov 10, 2010Sep 3, 2013Amkor Technology, Inc.Semiconductor device and fabricating method thereofUS8530277Jun 16, 2011Sep 10, 2013Stats Chippac Ltd.Integrated circuit packaging system with package on package support and method of manufacture thereofUS8535961Dec 9, 2010Sep 17, 2013Amkor Technology, Inc.Light emitting diode (LED) package and methodUS8536462Jan 22, 2010Sep 17, 2013Amkor Technology, Inc.Flex circuit package and methodUS8541260Apr 17, 2013Sep 24, 2013Amkor Technology, Inc.Exposed die overmolded flip chip package and fabrication methodUS8552548Nov 29, 2011Oct 8, 2013Amkor Technology, Inc.Conductive pad on protruding through electrode semiconductor deviceUS8557629Dec 3, 2010Oct 15, 2013Amkor Technology, Inc.Semiconductor device having overlapped via aperturesUS8569885Sep 27, 2011Oct 29, 2013Advanced Semiconductor Engineering, Inc.Stacked semiconductor packages and related methodsUS8581381Oct 30, 2006Nov 12, 2013Broadcom CorporationIntegrated circuit (IC) package stacking and IC packages formed by sameUS8587132Oct 31, 2012Nov 19, 2013Broadcom CorporationSemiconductor package including an organic substrate and interposer having through-semiconductor viasUS8623753May 28, 2009Jan 7, 2014Amkor Technology, Inc.Stackable protruding via package and methodUS8624374Apr 2, 2010Jan 7, 2014Advanced Semiconductor Engineering, Inc.Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereofUS8629546Jun 4, 2012Jan 14, 2014Amkor Technology, Inc.Stacked redistribution layer (RDL) die assembly packageUS8633598Sep 20, 2011Jan 21, 2014Amkor Technology, Inc.Underfill contacting stacking balls package fabrication method and structureUS8643167Dec 5, 2011Feb 4, 2014Advanced Semiconductor Engineering, Inc.Semiconductor package with through silicon vias and method for making the sameUS8653674Sep 15, 2011Feb 18, 2014Amkor Technology, Inc.Electronic component package fabrication method and structureUS8664772Oct 11, 2013Mar 4, 2014Broadcom CorporationInterface substrate with interposerUS8671565May 21, 2010Mar 18, 2014Amkor Technology, Inc.Blind via capture pad structure fabrication methodUS8691632Jun 14, 2013Apr 8, 2014Amkor Technology, Inc.Wafer level package and fabrication methodUS8704365 *Jul 20, 2011Apr 22, 2014Stats Chippac Ltd.Integrated circuit packaging system having a cavityUS8704368Jun 20, 2012Apr 22, 2014Amkor Technology, Inc.Stackable via package and methodUS8704369Feb 12, 2013Apr 22, 2014Amkor Technology, Inc.Flip chip bump structure and fabrication methodUS8710649Sep 5, 2013Apr 29, 2014Amkor Technology, Inc.Wafer level package and fabrication methodUS8717775Aug 2, 2010May 6, 2014Amkor Technology, Inc.Fingerprint sensor package and methodUS8718550Sep 28, 2011May 6, 2014Broadcom CorporationInterposer package structure for wireless communication element, thermal enhancement, and EMI shieldingUS8748231 *Aug 23, 2011Jun 10, 2014Amphenol Thermometrics, Inc.Component assembly using a temporary attach materialUS8749040Sep 21, 2009Jun 10, 2014Stats Chippac Ltd.Integrated circuit packaging system with package-on-package and method of manufacture thereofUS8749072Feb 24, 2012Jun 10, 2014Broadcom CorporationSemiconductor package with integrated selectively conductive film interposerUS8753730Nov 19, 2012Jun 17, 2014Amkor Technology, Inc.Mechanical tape separation packageUS8791501Dec 3, 2010Jul 29, 2014Amkor Technology, Inc.Integrated passive device structure and methodUS8796561Oct 5, 2009Aug 5, 2014Amkor Technology, Inc.Fan out build up substrate stackable package and methodUS8823144Oct 11, 2013Sep 2, 2014Broadcom CorporationSemiconductor package with interface substrate having interposerUS8823156Feb 9, 2011Sep 2, 2014Advanced Semiconductor Engineering, Inc.Semiconductor device packages having stacking functionality and including interposerUS8823160Aug 22, 2008Sep 2, 2014Stats Chippac Ltd.Integrated circuit package system having cavityUS8826531Apr 5, 2005Sep 9, 2014Amkor Technology, Inc.Method for making an integrated circuit substrate having laminated laser-embedded circuit layersUS8829654Nov 13, 2013Sep 9, 2014Broadcom CorporationSemiconductor package with interposerUS8829655Nov 13, 2013Sep 9, 2014Broadcom CorporationSemiconductor package including a substrate and an interposerUS8829656Nov 13, 2013Sep 9, 2014Broadcom CorporationSemiconductor package including interposer with through-semiconductor viasUS8847372Aug 21, 2013Sep 30, 2014Amkor Technology, Inc.Exposed die overmolded flip chip package and fabrication methodUS8872321Feb 24, 2012Oct 28, 2014Broadcom CorporationSemiconductor packages with integrated heat spreadersUS8872329Jan 9, 2009Oct 28, 2014Amkor Technology, Inc.Extended landing pad substrate package structure and methodUS8889486 *Sep 5, 2012Nov 18, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Methods and apparatus for package on package structuresUS8890329Apr 25, 2012Nov 18, 2014Amkor Technology, Inc.Semiconductor deviceUS8890337Jan 10, 2014Nov 18, 2014Amkor Technology, Inc.Column and stacking balls package fabrication method and structureUS8900995Jun 26, 2013Dec 2, 2014Amkor Technology, Inc.Semiconductor device and manufacturing method thereofUS8908378Jun 14, 2013Dec 9, 2014Conversant Intellectual Property Management Inc.System including a plurality of encapsulated semiconductor chipsUS8922013 *Nov 8, 2011Dec 30, 2014Stmicroelectronics Pte Ltd.Through via packageUS8928128Feb 27, 2012Jan 6, 2015Broadcom CorporationSemiconductor package with integrated electromagnetic shieldingUS8937381Dec 3, 2009Jan 20, 2015Amkor Technology, Inc.Thin stackable package and methodUS8941250Feb 17, 2014Jan 27, 2015Amkor Technology, Inc.Electronic component package fabrication method and structureUS8952522Apr 29, 2014Feb 10, 2015Amkor Technology, Inc.Wafer level package and fabrication methodUS8957516Apr 7, 2014Feb 17, 2015Broadcom CorporationLow cost and high performance flip chip packageUS8963311 *Sep 26, 2012Feb 24, 2015Apple Inc.PoP structure with electrically insulating material between packagesUS8981572Sep 4, 2013Mar 17, 2015Amkor Technology, Inc.Conductive pad on protruding through electrode semiconductor deviceUS8994192 *Dec 15, 2011Mar 31, 2015Stats Chippac Ltd.Integrated circuit packaging system with perimeter antiwarpage structure and method of manufacture thereofUS9012789Apr 7, 2014Apr 21, 2015Amkor Technology, Inc.Stackable via package and methodUS9013011Mar 11, 2011Apr 21, 2015Amkor Technology, Inc.Stacked and staggered die MEMS package and methodUS9013035Sep 5, 2006Apr 21, 2015Broadcom CorporationThermal improvement for hotspots on dies in integrated circuit packagesUS9029962Oct 12, 2011May 12, 2015Amkor Technology, Inc.Molded cavity substrate MEMS package fabrication method and structureUS9040361 *Dec 2, 2010May 26, 2015Siliconware Precision Industries Co., Ltd.Chip scale package with electronic component received in encapsulant, and fabrication method thereofUS9042115Jul 3, 2013May 26, 2015Samsung Electronics Co., Ltd.Stacked semiconductor packagesUS9048298Mar 29, 2012Jun 2, 2015Amkor Technology, Inc.Backside warpage control structure and fabrication methodUS9054117Dec 30, 2014Jun 9, 2015Amkor Technology, Inc.Wafer level package and fabrication methodUS9059011Aug 17, 2012Jun 16, 2015Stats Chippac Ltd.Exposed interconnect for a package on package systemUS9059160 *Nov 3, 2011Jun 16, 2015Marvell International Ltd.Semiconductor package assemblyUS9060430Oct 8, 2010Jun 16, 2015Amkor Technology, Inc.Shielded trace structure and fabrication methodUS9064781Apr 26, 2012Jun 23, 2015Broadcom CorporationPackage 3D interconnection and method of making sameUS9082780 *Mar 23, 2012Jul 14, 2015Stats Chippac, Ltd.Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layerUS9082833Jan 31, 2013Jul 14, 2015Amkor Technology, Inc.Through via recessed reveal structure and methodUS9129943Mar 29, 2012Sep 8, 2015Amkor Technology, Inc.Embedded component package and fabrication methodUS9129980Jun 27, 2013Sep 8, 2015Broadcom CorporationPackage 3D interconnection and method of making sameUS9159672Apr 12, 2013Oct 13, 2015Amkor Technology, Inc.Through via connected backside embedded circuit features structure and methodUS9171792Feb 28, 2011Oct 27, 2015Advanced Semiconductor Engineering, Inc.Semiconductor device packages having a side-by-side device arrangement and stacking functionalityUS9177901Mar 26, 2012Nov 3, 2015Stats Chippac, Ltd.Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillarsUS9177932Sep 16, 2013Nov 3, 2015Amkor Technology, Inc.Semiconductor device having overlapped via aperturesUS9196590 *Mar 6, 2015Nov 24, 2015Stmicroelectronics (Grenoble 2) SasPerforated electronic package and method of fabricationUS9196597Aug 6, 2014Nov 24, 2015Advanced Semiconductor Engineering, Inc.Semiconductor package with single sided substrate design and manufacturing methods thereofUS9230875Apr 24, 2014Jan 5, 2016Broadcom CorporationInterposer package structure for wireless communication element, thermal enhancement, and EMI shieldingUS9240380Dec 14, 2012Jan 19, 2016Stats Chippac, Ltd.Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnectUS9263426Jan 9, 2015Feb 16, 2016Apple Inc.PoP structure with electrically insulating material between packagesUS9275976Feb 24, 2012Mar 1, 2016Broadcom CorporationSystem-in-package with integrated socketUS9293393Feb 7, 2014Mar 22, 2016Broadcom CorporationStacked packaging using reconstituted wafersUS9299634Sep 5, 2006Mar 29, 2016Broadcom CorporationMethod and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packagesUS9312243Sep 26, 2014Apr 12, 2016Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor packagesUS9318459 *Nov 19, 2014Apr 19, 2016Stmicroelectronics Pte Ltd.Through via packageUS9324614Oct 29, 2012Apr 26, 2016Amkor Technology, Inc.Through via nub reveal method and structureUS9349611Feb 25, 2013May 24, 2016Advanced Semiconductor Engineering, Inc.Stackable semiconductor package and manufacturing method thereofUS9355962 *Jun 12, 2009May 31, 2016Stats Chippac Ltd.Integrated circuit package stacking system with redistribution and method of manufacture thereofUS9391043May 22, 2015Jul 12, 2016Amkor Technology, Inc.Semiconductor device and manufacturing method thereofUS9397036Jun 15, 2015Jul 19, 2016Marvell International Ltd.Semiconductor package assemblyUS9406645Jun 9, 2015Aug 2, 2016Amkor Technology, Inc.Wafer level package and fabrication methodUS9431323Feb 5, 2015Aug 30, 2016Amkor Technology, Inc.Conductive pad on protruding through electrodeUS9462704Oct 17, 2014Oct 4, 2016Amkor Technology, Inc.Extended landing pad substrate package structure and methodUS9484279 *Jun 2, 2010Nov 1, 2016STATS ChipPAC Pte. Ltd.Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor dieUS9484282 *Oct 23, 2008Nov 1, 2016Rohm Co., Ltd.Resin-sealed semiconductor deviceUS9496210 *Jun 7, 2013Nov 15, 2016Amkor Technology, Inc.Stackable package and methodUS9543242Aug 11, 2015Jan 10, 2017Amkor Technology, Inc.Semiconductor package and fabricating method thereofUS9548251Jan 12, 2012Jan 17, 2017Broadcom CorporationSemiconductor interposer having a cavity for intra-interposer dieUS9576873 *Dec 14, 2011Feb 21, 2017STATS ChipPAC Pte. Ltd.Integrated circuit packaging system with routable trace and method of manufacture thereofUS20070241446 *Jun 6, 2007Oct 18, 2007Amkor Technology, Inc.Two-sided wafer escape packageUS20070267740 *Sep 5, 2006Nov 22, 2007Broadcom CorporationMethod and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packagesUS20070273023 *Oct 20, 2006Nov 29, 2007Broadcom CorporationIntegrated circuit package having exposed thermally conducting bodyUS20070290322 *Sep 5, 2006Dec 20, 2007Broadcom CorporationThermal improvement for hotspots on dies in integrated circuit packagesUS20080006934 *Sep 18, 2007Jan 10, 2008Broadcom CorporationFlip Chip Package Including a Non-Planar Heat Spreader and Method of Making the SameUS20080017973 *Aug 8, 2007Jan 24, 2008Kabushiki Kaisha ToshibaSemiconductor device and manufacturing method thereforUS20080020132 *Sep 19, 2007Jan 24, 2008Amkor Technology, Inc.Substrate having stiffener fabrication methodUS20080073769 *Jul 26, 2007Mar 27, 2008Yen-Yi WuSemiconductor package and semiconductor deviceUS20080076208 *Jul 26, 2007Mar 27, 2008Yen-Yi WuMethod of making a semiconductor package and method of making a semiconductor deviceUS20080096312 *Oct 20, 2006Apr 24, 2008Broadcom CorporationLow profile ball grid array (BGA) package with exposed die and method of making sameUS20080185708 *Jun 6, 2007Aug 7, 2008Bridge Semiconductor CorporationStackable semiconductor package having metal pin within through hole of packageUS20080230887 *Mar 21, 2008Sep 25, 2008Advanced Semiconductor Engineering, Inc.Semiconductor package and the method of making the sameUS20080303124 *Nov 30, 2007Dec 11, 2008Broadcom CorporationLead frame-BGA package with enhanced thermal performance and I/O countsUS20090184412 *Oct 23, 2008Jul 23, 2009Rohm Co., Ltd.Resin-seal type semiconductor deviceUS20090236726 *Dec 12, 2008Sep 24, 2009United Test And Assembly Center Ltd.Package-on-package semiconductor structureUS20100032847 *Aug 8, 2008Feb 11, 2010Yusof Asri BinMethod for forming a package-on-package structureUS20100033941 *Aug 8, 2008Feb 11, 2010Reza Argenty PagailaExposed interconnect for a package on package systemUS20100038781 *Aug 14, 2008Feb 18, 2010Dongsam ParkIntegrated circuit packaging system having a cavityUS20100044878 *Aug 22, 2008Feb 25, 2010Stats Chippac Ltd.Integrated circuit package system having cavityUS20100090325 *Oct 9, 2009Apr 15, 2010Elpida Memory, Inc.Semiconductor deviceUS20100118482 *Feb 6, 2009May 13, 2010Mosaid Technologies IncorporatedSystem including a plurality of encapsulated semiconductor chipsUS20100123247 *Nov 17, 2008May 20, 2010Ko WonjunBase package system for integrated circuit package stacking and method of manufacture thereofUS20100171205 *Jul 22, 2009Jul 8, 2010Kuang-Hsiung ChenStackable Semiconductor Device PackagesUS20100171206 *Aug 20, 2009Jul 8, 2010Chi-Chih ChuPackage-on-Package Device, Semiconductor Package, and Method for Manufacturing The SameUS20100171207 *Aug 25, 2009Jul 8, 2010Chi-Chih ShenStackable semiconductor device packagesUS20100314741 *Jun 12, 2009Dec 16, 2010Seongmin LeeIntegrated circuit package stacking system with redistribution and method of manufacture thereofUS20110042798 *Aug 21, 2009Feb 24, 2011Stats Chippac, Ltd.Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive PillarsUS20110062574 *Sep 15, 2009Mar 17, 2011Ki Youn JangIntegrated circuit packaging system with package-on-package and method of manufacture thereofUS20110062576 *Sep 11, 2009Mar 17, 2011St-Ericsson SaIntegrated circuit package and deviceUS20110068464 *Sep 21, 2009Mar 24, 2011Chi HeejoIntegrated circuit packaging system with package-on-package and method of manufacture thereofUS20110095424 *Aug 12, 2010Apr 28, 2011Samsung Electronics Co., Ltd.Semiconductor package structureUS20110149493 *Oct 22, 2010Jun 23, 2011Samsung Electronics Co., Ltd.Stacked semiconductor packages, methods of fabricating the same, and/or systems employing the sameUS20110272807 *Jul 20, 2011Nov 10, 2011Dongsam ParkIntegrated circuit packaging system having a cavityUS20110298101 *Jun 2, 2010Dec 8, 2011Stats Chippac, Ltd.Semiconductor Device and Method of Forming EMI Shielding Layer with Conductive Material Around Semiconductor DieUS20120038044 *Dec 2, 2010Feb 16, 2012Siliconware Precision Industries Co., Ltd.Chip scale package and fabrication method thereofUS20120146235 *Dec 9, 2010Jun 14, 2012Daesik ChoiIntegrated circuit packaging system with vertical interconnection and method of manufacture thereofUS20120326306 *Dec 29, 2010Dec 27, 2012Hyun Woo LeePop package and manufacturing method thereofUS20130049232 *Aug 23, 2011Feb 28, 2013General Electric CompanyComponent assembly using a temporary attach materialUS20130113098 *Nov 8, 2011May 9, 2013Stmicroelectronics Pte Ltd.Through via packageUS20130154105 *Dec 14, 2011Jun 20, 2013Byung Tai DoIntegrated circuit packaging system with routable trace and method of manufacture thereofUS20130154116 *Dec 15, 2011Jun 20, 2013Daesik ChoiIntegrated circuit packaging system with perimeter antiwarpage structure and method of manufacture thereofUS20130200509 *Oct 25, 2012Aug 8, 2013Samsung Electronics Co., Ltd.Semiconductor packageUS20130241044 *Nov 5, 2012Sep 19, 2013Samsung Electronics Co., Ltd.Semiconductor package having protective layer and method of forming the sameUS20140061932 *Sep 5, 2012Mar 6, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Methods and Apparatus for Package on Package StructuresUS20140084487 *Sep 26, 2012Mar 27, 2014Apple Inc.PoP STRUCTURE WITH ELECTRICALLY INSULATING MATERIAL BETWEEN PACKAGESUS20140124949 *Jan 29, 2013May 8, 2014Jong Sik PaekSemiconductor device and method of manufacturing semiconductor deviceUS20140367841 *Jun 12, 2014Dec 18, 2014Advanced Semiconductor Engineering, Inc.Semiconductor package structure and semiconductor processUS20150069607 *Nov 19, 2014Mar 12, 2015Stmicroelectronics Pte LtdThrough via packageUS20160093602 *Dec 7, 2015Mar 31, 2016Marvell World Trade Ltd.Package-on-package structuresUS20160240465 *Dec 17, 2015Aug 18, 2016Taiwan Semiconductor Manufacturing Co., Ltd.Reducing Cracking by Adjusting Opening Size in Pop PackagesWO2011081428A3 *Dec 29, 2010Nov 10, 2011Hana Micron Co.,Ltd.Pop package and manufacturing method thereof* Cited by examinerClassifications U.S. Classification257/787, 257/E21.502, 257/E25.023, 257/E23.021International ClassificationH01L23/28Cooperative ClassificationH01L2924/00014, H01L2224/48237, H01L2224/13, H01L2924/12042, H01L2924/181, H01L24/13, H01L24/48, H01L2224/92242, H01L2225/06568, H01L24/10, H01L2924/014, H01L24/91, H01L24/73, H01L2924/14, H01L2224/48091, H01L2924/19042, H01L2924/01005, H01L21/56, H01L2224/73207, H01L2924/01029, H01L2224/32225, H01L2924/01027, H01L2224/73265, H01L2924/15331, H01L2924/19043, H01L2924/3011, H01L2924/15311, H01L2924/01013, H01L2924/01047, H01L2924/01006, H01L2924/1815, H01L2924/01033, H01L25/105, H01L2224/48465, H01L2924/01079, H01L2924/19041, H01L2924/01082, H01L23/3128, H01L2224/48227, H01L2224/13099, H01L2224/32145, H01L2225/1088, H01L2924/15321, H01L2225/1058, H01L2225/1023, H01L2224/92127European ClassificationH01L24/91, H01L24/10, H01L24/73, H01L23/31H2B, H01L25/10J, H01L21/56Legal EventsDateCodeEventDescriptionOct 30, 2006ASAssignmentOwner name: BROADCOM CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHAO, SAM ZIQUN;KHAN, REZAUR RAHMAN;REEL/FRAME:018487/0850Effective date: 20060906Feb 11, 2016ASAssignmentOwner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTHFree format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001Effective date: 20160201Feb 1, 2017ASAssignmentOwner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTDFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:041706/0001Effective date: 20170120Feb 3, 2017ASAssignmentOwner name: BROADCOM CORPORATION, CALIFORNIAFree format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041712/0001Effective date: 20170119RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services