Source: http://www.google.com/patents/US7829971?ie=ISO-8859-1&dq=7,117,286
Timestamp: 2014-12-20 19:30:31
Document Index: 633906907

Matched Legal Cases: ['art.\n6', 'art.\n9', 'art.\n13', 'art.\n14', 'art.\n15', 'application No. 2008101843998', 'application No. 2007']

Patent US7829971 - Semiconductor apparatus - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor apparatus is disclosed. The semiconductor apparatus includes an SOI substrate including an active layer, a buried insulation film and a support substrate; a low potential reference circuit part located in the active layer and operable at a first reference potential; a high potential reference...http://www.google.com/patents/US7829971?utm_source=gb-gplus-sharePatent US7829971 - Semiconductor apparatusAdvanced Patent SearchPublication numberUS7829971 B2Publication typeGrantApplication numberUS 12/314,518Publication dateNov 9, 2010Filing dateDec 11, 2008Priority dateDec 14, 2007Fee statusPaidAlso published asDE102008054564A1, US20090152668Publication number12314518, 314518, US 7829971 B2, US 7829971B2, US-B2-7829971, US7829971 B2, US7829971B2InventorsHiroki Sone, Akira Yamada, Satoshi Shiraki, Nozomu AkagiOriginal AssigneeDenso CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (24), Non-Patent Citations (3), Classifications (18), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor apparatusUS 7829971 B2Abstract A semiconductor apparatus is disclosed. The semiconductor apparatus includes an SOI substrate including an active layer, a buried insulation film and a support substrate; a low potential reference circuit part located in the active layer and operable at a first reference potential; a high potential reference circuit part located in the active layer and operable at a second reference potential; a level-shifting element forming part located in the active layer and for providing a level-shift between the first and second reference potentials; and an insulation member insulating first and second portions of the support substrate from each other, wherein locations of the first and second portions respectively correspond to the low and high potential reference circuit parts.
an SOI substrate including an active layer, a support substrate and a buried insulation film, wherein the active layer and the support substrate are bonded to each other via the buried insulation film therebetween;
a low potential reference circuit part located in the active layer and operable at a first reference potential;
a high potential reference circuit part located in the active layer and operable at a second reference potential, which is greater than or equal to the first reference potential;
a level-shifting element forming part located in the active layer and having a level-shifting element providing a level-shift between the first reference potential and the second reference potential; and
an insulation member insulating a first portion and a second portion of the support substrate from each other, wherein the first portion corresponds in location to the low potential reference circuit part, wherein the second portion corresponds in location to the high potential reference circuit part, wherein:
the low potential reference circuit part has a first region to which the first reference potential is applied; and
the first portion of the support substrate is electrically connected with the first region of the low potential reference circuit part.
the insulation member is made of resin.
the insulation member is air.
the insulation member is vacuum.
5. The semiconductor apparatus according to claim 1, wherein:
the high potential reference circuit part has a second region to which the second reference potential is applied; and
the second portion of the support substrate is electrically connected with the second region of the high potential reference circuit part.
6. The semiconductor apparatus according to claim 5, wherein:
7. The semiconductor apparatus according to claim 1, wherein:
the second reference potential is variable.
8. The semiconductor apparatus according to claim 1, wherein:
the level-shifting element forming part is located between the low potential reference circuit part and the high potential reference circuit part; and
the active layer has a trench insulation member that surrounds the low potential reference circuit part, the high potential reference circuit part and the level-shifting element forming part;
the semiconductor apparatus according to claim 1 further comprising:
an element-outside part located in the active layer and located outward of the trench insulation member, wherein the support substrate further has a third portion, wherein the third portion corresponds in location to the element-outside part.
9. The semiconductor apparatus according to claim 8, wherein:
the first portion and the third portion of the support substrate are integrated.
10. The semiconductor apparatus according to claim 8, wherein:
the first portion and the third portion of the support substrate are electrically connected with each other.
an insulating member located on a first portion and a second portion of the back surface of the semiconductor layer, the first and second portions respectively correspond to the low and high potential reference circuit parts;
a first conductive member located opposite to the low potential reference circuit part with respect to the insulating member, and electrically connected with a first region of the low potential reference circuit part, wherein the first reference potential is applied to the first region; and
a second conductive member located opposite to the high potential reference circuit part with respect to the insulating member, and electrically connected with a second region of the high potential reference circuit part, wherein the second reference potential is applied to the second region.
12. The semiconductor apparatus according to claim 11, further comprising:
a bonding wire having a first bonding wire and a second bonding wire, wherein:
the first bonding wire electrically connects the first conductive member to the first region of the low potential reference circuit part; and
the second bonding wire electrically connects the second conductive member to the second region of the high potential reference circuit part.
13. The semiconductor apparatus according to claim 11, wherein:
the insulating member has a first trench and a first penetration electrode embedded in the first trench;
the first penetration electrode electrically connects the first conductive member to the first region of the low potential reference circuit part;
the insulating member further have a second trench and a second penetration electrode embedded in the second trench; and
the second penetration electrode electrically connects the second conductive member to the second region of the high potential reference circuit part.
14. The semiconductor apparatus according to claim 11, further comprising:
a lead frame having a first lead frame and a second lead frame, wherein
the first conductive member is a first lead frame for external electrical connection of the low potential reference circuit part; and
the second conductive member is a second lead frame for external electrical connection of the high potential reference circuit part.
15. The semiconductor apparatus according to claim 11, wherein
the insulating member is one of an insulation substrate and an insulating film.
16. The semiconductor apparatus according to claim 11, wherein
a substrate located opposite to the semiconductor layer with respect to the insulating member, and having a first conductive pattern and a second conductive pattern, wherein:
the first conductive member is the first conductive pattern; and,
the second conductive member is the second conductive pattern.
18. The semiconductor apparatus according to claim 17, wherein:
the insulating member is an encapsulation resin member encapsulating the semiconductor layer.
19. The semiconductor apparatus according to claim 18, further comprising:
first and second lead frames, wherein:
a first end of the first lead frame is located inside the encapsulation resin member and electrically connected with the first region of the low potential reference circuit part;
a second end of the first lead frame is electrically connected with the first conductive pattern of the substrate;
a first end of the second lead frame is located inside the encapsulation resin member and electrically connected with the second region of the high potential reference circuit part; and
a second end of the second lead frame is electrically connected with the second conductive pattern of the substrate.
20. The semiconductor apparatus according to claim 17, wherein:
the insulating member is a ceramic package onto which the semiconductor layer is mounted.
21. The semiconductor apparatus according to claim 20, further comprising:
first and lead frames, wherein:
the ceramic package has a concave portion into which the semiconductor layer is mounted;
one end of the first lead frame projects from the concave portion of the ceramic package and is electrically connected with the first region of the low potential reference circuit part;
another end of the first lead frame projects from the ceramic package and is electrically connected with the first conductive pattern;
one end of the second lead frame projects from the concave portion of the ceramic package and is electrically connected with the second region of the high potential reference circuit part; and
another end of the second lead frame projects from the ceramic package and is electrically connected with the second conductive pattern.
22. A semiconductor apparatus comprising:
an insulation member insulating a first portion and a second portion of the support substrate from each other, wherein
the first portion corresponds in location to the low potential reference circuit part,
the second portion corresponds in location to the high potential reference circuit part,
the low potential reference circuit part has a first region to which the first reference potential is applied,
the high potential reference circuit part has a second region to which the second reference potential is applied, and
the second portion of the support substrate is electrically connected with the second region of the high potential reference circuit part. Description
CROSS REFERENCE TO RELATED APPLICATION The present application is based on Japanese Patent Applications No. 2007-323064 filed on Dec. 14, 2007 and No. 2008-112483 filed on Apr. 23, 2008, the disclosures of which are incorporated herein by reference.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5442223Apr 11, 1994Aug 15, 1995Nippondenso Co., Ltd.Semiconductor device with stress reliefUS6013936Aug 6, 1998Jan 11, 2000International Business Machines CorporationDouble silicon-on-insulator device and method thereforUS6992363Jul 7, 2003Jan 31, 2006Mitsubishi Denki Kabushiki KaishaDielectric separation type semiconductor device and method of manufacturing the sameUS7205587Jul 28, 2005Apr 17, 2007Oki Electric Industry Co., Ltd.Semiconductor device and method of producing the sameUS7285455Dec 14, 2006Oct 23, 2007Oki Electric Industry Co., Ltd.Method of producing the sameUS7462913Oct 26, 2006Dec 9, 2008Denso CorporationSemiconductor device having first and second separation trenchesUS20030094654Aug 9, 2002May 22, 2003International Business Machines CorporationHigh energy deep oxygen implant creates a deep buried oxide layer and a first Si intermediate layer; lower energy oxygen implant creates a shallow buried oxide layer and a second Si intermediate layerUS20070090458 *Oct 26, 2006Apr 26, 2007Denso CorporationSemiconductor device having first and second separation trenchesUS20090004772Jan 24, 2008Jan 1, 2009Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing semiconductor deviceUS20090152668Dec 11, 2008Jun 18, 2009Denso DorporationSemiconductor apparatusJP23076504A Title not availableJP2006093229A Title not availableJP2006287009A Title not availableJP2007141958A Title not availableJPH0462847A Title not availableJPH01241168A Title not availableJPH02271567A Title not availableJPH02281753A Title not availableJPH10125925A Title not availableJPS5916341A Title not availableJPS5919350A Title not availableJPS6167253A Title not availableJPS6185853A Title not availableJPS61121466A Title not available* Cited by examinerNon-Patent CitationsReference1First Office Action issued from the Chinese Patent Office on Dec. 25, 2009 in the corresponding Chinese patent application No. 2008101843998 (with English translation).2Office Action mailed Oct. 6, 2009 in corresponding Japanese patent application No. 2007-323064 (and English translation).3U.S. Appl. No. 12/654,707, filed Dec. 29, 2009, Senda et al.Classifications U.S. Classification257/501, 257/E23.031, 257/E25.029International ClassificationH01L23/495, H01L25/16Cooperative ClassificationH01L24/48, H01L2924/13091, H01L23/585, H01L2924/19041, H01L2224/48247, H01L23/49589, H01L27/092, H01L2224/48095, H01L27/1203, H01L2924/13055European ClassificationH01L23/58B, H01L23/495Q, H01L27/12BLegal EventsDateCodeEventDescriptionMay 2, 2014FPAYFee paymentYear of fee payment: 4Jan 21, 2009ASAssignmentOwner name: DENSO CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SONE, HIROKI;YAMADA, AKIRA;SHIRAKI, SATOSHI;AND OTHERS;REEL/FRAME:022169/0260;SIGNING DATES FROM 20081212 TO 20081215RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google