Source: http://www.google.com/patents/US7193957?dq=6,460,050
Timestamp: 2015-08-01 18:41:00
Document Index: 115321365

Matched Legal Cases: ['application No. 10', 'art 2', 'art 4', 'art 3', 'art 7', 'art 118', 'art 118', 'art 111', 'art 104', 'art 116', 'art 115', 'art 104', 'art 104', 'art 115']

Patent US7193957 - Light source drive, optical information recording apparatus, and optical ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA light source drive which modulates a light source so as to cause the same to emit a light, includes: a superposition current generation part which generates a superposition current approximately corresponding to a charging/discharging current needed for a capacitance occurring in parallel to the light...http://www.google.com/patents/US7193957?utm_source=gb-gplus-sharePatent US7193957 - Light source drive, optical information recording apparatus, and optical information recording methodAdvanced Patent SearchPublication numberUS7193957 B2Publication typeGrantApplication numberUS 11/213,829Publication dateMar 20, 2007Filing dateAug 30, 2005Priority dateJul 3, 2002Fee statusPaidAlso published asEP1381036A2, EP1381036A3, US6954415, US7480230, US20040095853, US20060007841, US20070036059Publication number11213829, 213829, US 7193957 B2, US 7193957B2, US-B2-7193957, US7193957 B2, US7193957B2InventorsNaruhiro Masui, Hidetoshi EmaOriginal AssigneeRicoh Company, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (38), Referenced by (4), Classifications (18), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetLight source drive, optical information recording apparatus, and optical information recording method
US 7193957 B2Abstract
an output impedance control part which changes an output impedance value of a drive current output part which provides a drive current to said light source, for a predetermined time period near at least one of a rising-up part and a decaying-down part of a waveform of the drive current.
2. The light source drive as claimed in claim 1, further comprising:
a time control part which controls said predetermined time period.
3. The light source drive as claimed in claim 1, further comprising:
a resistance value control part which controls said output impedance value.
4. A light source drive which modulates a light source so as to cause the same to emit a light, comprising:
a MOS transistor connected in parallel with a drive current output part which outputs a drive current to said light source; and
a voltage control part which applies a voltage to a gate of said MOS transistor such that said MOS transistor enters a linear region for a predetermined time period near at least one of a rising-up part and a decaying-down part of a waveform of the drive current.
5. The light source drive as claimed in claim 4, further comprising:
This application is a divisional of U.S. patent application No. 10/606,780, filed on Jun. 27, 2003 now U.S. Pat. No. 6,954,415, the subject matter of which is incorporated in its entirety by reference herein.
‘CLD’ in this LD equivalent model 203 indicates the above-mentioned junction capacitance (the above-mentioned parasitic capacitance is also included therein), ‘r’ indicates an ON resistance, and ‘LDi’ indicates an ideal LD. Due to the occurrence of the junction capacitance, even when a predetermined drive current is provided with a sharp rising-up and a sharp decaying-down in its waveform, i.e., of a rectangular waveform, as shown in FIG. 2A, a part of the current is to flow through the junction capacitance as a charging/discharging current Ic therefor. Accordingly, the current then flowing through the ideal LD (LDi) has not sufficiently sharp rising-up and decaying-down, i.e., rounded, as shown in FIG. 2B. As a result, it becomes not possible to drive the LD with a desired signal waveform such as that shown in FIG. 2A.
The light source drive 1 includes a beam-application level setting part 2 which sets beam-application levels P0, P1, and P2 of an LD as shown in FIG. 3 (beam-application level control part). A modulation signal generation part 4 also included in the light source drive 1 generates modulation signals Mod1 and Mod2 for the LD from a record data signal Wdata and a record clock signal WCK. Further, a modulation part 3 also included in the light source derive 1 generates an LD modulation current Imod based on beam-application level data P0bata, P1Data, P2Data corresponding to the beam-application levels P0, P1, and P2 of the LD, respectively, and the modulation signals Mod1 and Mod2.
Moreover, according to the present embodiment, the superposition current value superposed to the drive current of the light source may be controlled according to the capacitance occurring in parallel with the light source. Thereby, according to the particular light source applied, a delay or rounding of the rising-up/decaying-down of the light waveform can be well cancelled, and light can be made to be emitted with a desired light waveform.
In this example, the gate voltage is controlled so that the transistor enters the linear region at a predetermined period at a time of rising-up/decaying-down of the drive current, while it enters the OFF state during all the other period.
Thus, according to the light source drive according to any one of the above-mentioned first through third embodiments of the present invention, the superposition current generation part generates the overshoot current Ios and undershoot current Ius at the rising-up and decaying-down timings of the modulation signals Mod1 and Mod2 from the modulation signal generation part. Since they are superposed and supplied to the drive-current of the light source LD, a delay (rounding) of the light waveform otherwise occurring due to the junction capacitance of the light source LD etc., can be well controlled, and a light can be made to be emitted with a desired light waveform.
That is, the current waveform is obtained superposed with the overshoot current Ios at the time of the rising-up of drive current, while superposed with the undershoot current Ius at the time of decaying-down of the same. The current levels I0 through I4 shown in the figure are current values generated in the current sources 8 and 13, respectively, and the current Ibias corresponds to a threshold current of the LD provided by the LD control part 7.
As shown in FIG. 11, the superposition signal generation unit 11 includes a delay element 57 which has the modulation signal Mod2 input thereto, and outputs the same signal with a delay time of Δ1 which is determined by a value of a current provided thereto, and a logical circuit 58 which perform a logical operation of {Mod2&!dMod2}, where ‘!dMod2’ means the inverted and delayed signal of Mod2, and outputs the operation result as the superposition signal ModO. Each signal is shown in FIG. 12, (a), (b) or (c). The superposition signal generation unit 11 also includes a delay element 59 which has the modulation signal Mod2 input thereto, and outputs a signal d2Mod2 delayed from the thus-input signal Mod2 with a delay time of Δ2, and a logical circuit 60 which performs a logical operation of {!Mod2&d2Mod2}, where ‘!Mod2’ means the inverted signal of Mod2, and outputs the operation result as the superposition signal ModU.
In addition, in order to reduce LD noise by a reflected light from a disk to the optical disk drive, usually, a method, called ‘high frequency superposition’, of superposing a high frequency signal on a drive current for the LD may be taken in some cases. In such a case, since it is a common way to use an oscillator (VCO), and, therefore, this oscillator may be used in common also as the above-mentioned oscillator 55.
The LD usually has a junction capacitance between the anode and cathode (in addition, parasitic capacitance also may occur there). The circuit shown in FIG. 19 includes a simple LD equivalent model 1202 in consideration of this junction capacitance. As shown, this equivalent model includes the junction capacitance CLD also including the parasitic capacitance, an turned-on resistance ‘r’ and an ideal LD ‘LDi’.
Next, a detailed internal configuration of the addition current generation part 118 will now be described. The addition current generation part 118 includes an addition signal generation part 111 which generates addition signals (respectively, ModO and ModU) which specify periods for which the overshoot current Ios and undershoot current Ius are superposed based on the modulation timings which the modulation signal generation part 104 generates. An addition power setting part 116 sets current values 13 and 14 of the overshoot current Ios and undershoot current Ius, and supplies setting data OSData and USData therefor.
Current sources OSDAC 113 a and USDAC 113 b supply the currents 13 and 14 based on the overshoot current setting data OSData and the undershoot current setting data USData, respectively. Switches 114 a and 114 b carry out on-off control of the currents I3 and I4 according to the addition signals ModO and ModU, respectively, and thus generate the overshoot current Ios and undershoot current Ius. An addition time setting part 115 sets addition time periods for the overshoot current Ios and undershoot current Ius.
Then, as shown in FIG. 22, (d), a front edge part ‘a’ of a record mark is formed with a top pulse TP, shown in FIG. 22, (c), and a cooling pulse subsequent thereto; a rear edge part ‘c’ of the record mark is formed with a last pulse LP and a cooling pulse subsequent thereto; and intermediate parts ‘b1’ and ‘b2’ of the record mark are formed with intermediate pulses MP and cooling pulses subsequent thereto, respectively. Thus, the one record mark corresponding to the record data Wdata shown in FIG. 22, (b) is formed.
The modulation signals Mod1 of (e-1) and Mod2 of (e-2) in FIG. 22 ate generated corresponding to the record data Wdata of (b) based on drive waveform information that indicates desired modulation timing of the light waveform beforehand set in the modulation signal generation part 104.
According to the first variant embodiment of the seventh embodiment, the modification signal generation part 104 shown in FIG. 22 measures the run length of the record data Wdata input, and supplies information concerning a mark length M1, an immediately preceding space length S0, and an immediately subsequent space-length S1, to the addition time setting part 115. Simultaneously, the modification signals Mod1 and Mod2 are also generated based on these lengths M1, S0, and S1.
Specifically, the addition times To1 and Tu1 may be determined for the top pulse TP-according to the immediately preceding space S0 and the mark length M1, while the addition times To3 and Tu3 may be determined for the last pulse LP according to the mark length M1 and the immediately subsequent space length S1. Furthermore, the addition times To2 and Tu2 may be determined for the intermediate pulses MP according to the mark length M1. Thereby, the effectively simplified control of beam-application energy is achieved.
In FIG. 24, (i), the waveform ‘a’ of the drive current ILD for the LD is one in a case where the above-mentioned overshoot current Ios is not added on a rising-up of the drive current. Waveforms ‘b’ through ‘d’ are those in case where the predetermined addition time of overshoot current Ios is added one by one gradually. In FIG. 24, (ii), a light waveform is shown as an example resulting from each of the above-mentioned drive currents ILD shown in FIG. 24, (i). As for the light waveform ‘a’, a rising-up is remarkably rounded due to the current consumed to charge the junction capacitance of the LD, and the light waveform ‘b’ results from a case where the added overshoot current Ios is exactly appropriated for the necessary charging current. The light waveforms ‘c’ and ‘d’ are those resulting from a case where the time added is further increased, and, thus, as in the above-mentioned seventh embodiment, the resolution of beam-application energy is increased accordingly.
Furthermore, it is further preferable to adjust the current values and/or the addition times of the overshoot current los and the undershoot current Ius according to various changes of beam-application levels.
The present application is based on Japanese priority applications Nos. 2002-194161 filed on Jul. 3, 2002, 2002-218559 filed on Jul. 26, 2002, and 2003-164054, filed on Jun. 9, 2003, the entire contents of which are hereby incorporated-by reference.
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