Source: https://patents.google.com/patent/JP4208840B2/en
Timestamp: 2020-07-09 09:30:16
Document Index: 426100686

Matched Legal Cases: ['art 109', 'art 105', 'art 2', 'art 2', 'art 1', 'art 1', 'art 2', 'art 2', 'art 3', 'art 3', 'art 1', 'art 2', 'art 2', 'arts 1', 'arts 4', 'art 4', 'art 4', 'art 4', 'art 4', 'art 1', 'art 4', 'art 5', 'art 5', 'art 2', 'art 6', 'arts 4', 'art 6', 'art 5', 'art 6', 'art 3', 'arts 1', 'art 9', 'arts 4', 'art 5', 'art 5', 'art 5', 'art 2', 'art 5', 'art 5', 'arts 5', 'art 5', 'art 5', 'art 5', 'art 2', 'art 5', 'art 4', 'art 2', 'arts 5', 'arts 5', 'arts 4']

JP4208840B2 - Semiconductor device - Google Patents
JP4208840B2
JP4208840B2 JP2004560577A JP2004560577A JP4208840B2 JP 4208840 B2 JP4208840 B2 JP 4208840B2 JP 2004560577 A JP2004560577 A JP 2004560577A JP 2004560577 A JP2004560577 A JP 2004560577A JP 4208840 B2 JP4208840 B2 JP 4208840B2
JP2004560577A
JPWO2004055891A1 (en
洋 三澤
貴雄 大野
2002-12-17 Application filed by 富士通マイクロエレクトロニクス株式会社 filed Critical 富士通マイクロエレクトロニクス株式会社
2002-12-17 Priority to PCT/JP2002/013198 priority Critical patent/WO2004055891A1/en
2006-04-20 Publication of JPWO2004055891A1 publication Critical patent/JPWO2004055891A1/en
2009-01-14 Publication of JP4208840B2 publication Critical patent/JP4208840B2/en
239000004065 semiconductor Substances 0.000 title claims description 238
230000001681 protective Effects 0.000 claims 3
The present invention relates to a semiconductor device, and more particularly to a stacked semiconductor device in which semiconductor elements are stacked.
In recent years, with the improvement in performance of semiconductor devices, stacked semiconductor devices in which a plurality of semiconductor elements are stacked have become widespread. In such a stacked semiconductor device, a wire bonding method is generally used as a wiring method for wiring between stacked semiconductor elements.
FIG. 1 shows a configuration example of a stacked semiconductor device 100 wired using a wire bonding method.
Referring to FIG. 1, a semiconductor element 101 is installed on an interposer 111 through an insulator 103, and a semiconductor element 102 is installed on the semiconductor element 101 through an insulator 104. The semiconductor element 101 is provided with active elements, passive elements, etc. (not shown), and the contact part 109 of the interposer by wire bonding using wires 107 from the wiring connection part 105 connected to these elements. Is wired.
Similarly, active elements and passive elements (not shown) are arranged in the semiconductor element 102, and the contact portion of the interposer is connected by wire bonding using wires 108 from the wiring connection portion 106 connected to these elements. 109 is wired. The semiconductor elements 101 and 102 and the wires 107 and 108 are fixed to the interposer 111 with a MOLD resin 110.
In the case of the stacked semiconductor device 100 using the wire bonding method as described above, problems caused by variations in wire bonding processing, such as a difference in the loop shape of the wire, or a variation in resistance value between the wiring connection portion and the wire connection portion. Is concerned.
In addition, since the wiring connection portion on the semiconductor element needs to be exposed in order to perform wiring with the wire, the upper semiconductor element must always be smaller than the lower semiconductor element when the semiconductor elements are stacked. There has been a problem in that the degree of freedom of design is limited when a stacked semiconductor device is formed due to size limitations.
Accordingly, an object of the present invention is to provide a new and useful semiconductor device that solves the above-described problems. A specific object of the present invention is to provide a wiring and a semiconductor device having a semiconductor element with high wiring accuracy and less variation in processing compared to conventional wire bonding which is wiring of a semiconductor element.
Another object of the present invention is to increase the degree of freedom in designing a stacked semiconductor device by eliminating the size limitation when stacking semiconductor elements.
In the present invention, the above-described problem is provided with a semiconductor element in which a plurality of electrodes are disposed on one main surface, and a wiring substrate in which a plurality of conductive layers are disposed on an insulating substrate, The semiconductor element is arranged in a substantially U shape along the outer edge of the semiconductor element, one end of the conductive layer in the wiring board is connected to the electrode of the semiconductor element, and the other end of the conductive layer is the other of the semiconductor element This is solved by using a semiconductor device characterized in that it is led out in a different direction from the semiconductor element on the main surface side.
According to the present invention, since the wiring using the conductive layer of the wiring board is formed along the outer edge portion of the semiconductor element, the wiring is compared with the conventional wire wiring formed in a loop shape. When the portion is formed, the wiring length can be minimized, and the variation in wiring length can be minimized.
According to the present invention, a conductive layer is disposed on an insulating substrate to form a wiring substrate, and the wiring substrate is disposed along the outer edge of the semiconductor element, thereby stacking another semiconductor element on the wiring substrate. Is possible. Therefore, a semiconductor element having the same size as the semiconductor element or a larger size than the semiconductor element can be stacked on the semiconductor element, and there is no limitation on the size of the semiconductor element when forming the stacked semiconductor element. This increases the degree of freedom in designing a stacked semiconductor device.
FIG. 1 is a diagram showing a configuration of a stacked semiconductor device using conventional wire bonding wiring.
FIG. 2 is a diagram showing a configuration example when the size of the semiconductor element is the same in the configuration of the stacked semiconductor device according to the present invention.
FIG. 3 is a diagram showing a configuration example when the sizes of the semiconductor elements are different in the configuration of the stacked semiconductor device according to the present invention.
FIG. 4 is a diagram showing a wiring method of the stacked semiconductor device shown in FIG.
FIG. 5 is a diagram showing details of the wiring method shown in FIG.
FIG. 6A is a perspective view showing an overview of the semiconductor element, and FIG. 6B is a perspective view showing an overview in which laminated parts are installed on the semiconductor element shown in FIG. 6A.
7A is a plan view (No. 1) showing a multilayer component according to the present invention, and FIG. 7B is a perspective view (No. 1) showing a shape when the multilayer component shown in FIG. 7A is bent and attached to a semiconductor element. It is.
FIG. 8A is a plan view (part 2) showing a laminated part according to the present invention, and FIG. 8B is a perspective view (part 2) in which the laminated part shown in FIG. 8A is bent and attached to a semiconductor element. It is.
9A is a cross-sectional view (part 1) showing a method for connecting wiring of a semiconductor element according to the present invention, and FIG. 9B is a perspective view (part 1) showing a method for connecting wiring of a semiconductor element shown in FIG. 9A. .
FIG. 10A is a cross-sectional view (part 2) showing a method for connecting wiring of a semiconductor element according to the present invention, and FIG. 10B is a perspective view (part 2) showing a method for connecting wiring shown in FIG. 10A.
FIG. 11A is a cross-sectional view (part 3) illustrating a wiring connection method of a semiconductor element according to the present invention, and FIG. 11B is a perspective view (part 3) illustrating a wiring connection method illustrated in FIG. 11A.
12A to 12C are cross-sectional views (part 1) showing steps of a method for connecting wiring of semiconductor elements according to the present invention.
13A and 13B are cross-sectional views (part 2) showing the steps of the method of connecting the wiring of the semiconductor element according to the present invention.
14A is a diagram showing a configuration in which the stacked semiconductor device shown in FIG. 2 is fixed by a MOLD resin, and FIG. 14B is a diagram showing a configuration in which the stacked semiconductor device shown in FIG. 3 is fixed by a MOLD resin. is there.
15A is a configuration diagram (No. 1) of a light receiving device using the stacked semiconductor device shown in FIG. 14B, and FIG. 15B is a configuration diagram of the light receiving device using the stacked semiconductor device shown in FIG. Part 2).
FIG. 16 shows a modification of the stacked semiconductor device shown in FIG.
FIG. 2 is a cross-sectional view showing the configuration of the stacked semiconductor device 10 according to the present invention. Referring to FIG. 2, the stacked semiconductor device 10 schematically has a configuration in which semiconductor elements 1 to 3 are disposed on an interposer 11. The semiconductor elements 1 to 3 are held by laminated components 4 to 6 installed along the outer edges of the semiconductor elements 1 to 3, respectively, from the lower surface to the side surface.
Each of the semiconductor elements 1 to 3 is formed with elements (not shown) such as active elements and passive elements, and wiring connection portions 1a to 3a connected to these elements are installed. The wiring contact portions 1b to 3b are installed on the portions 1a to 3a, respectively. The said wiring connection parts 1b-3b are connected with the wiring part mentioned later installed in the said laminated components 4-6.
The wiring of the stacked semiconductor device 10 is formed by the wiring portion described above and the stacked contact portions 1c to 3c installed below the stacked components 4 to 6 connected to the wiring portion. The formed wiring is connected to the contact portion 9 of the interposer through the laminated contact portion 1c. Details of the structure of such wiring will be described later.
As described above, since a laminated semiconductor device is formed by using a laminated part having a wiring part that replaces the conventional wire bonding, a semiconductor element can be placed in a space above the wiring connection part of the semiconductor element. Thus, as shown in FIG. 2, it is possible to form a stacked semiconductor device by stacking semiconductor elements having the same size.
Further, when forming a laminated semiconductor component using such a laminated component, a laminated semiconductor device is formed not only with the same size semiconductor element but also with different size semiconductor elements as shown in FIG. Therefore, there is no limitation on the size of the semiconductor element when forming the stacked semiconductor device.
FIG. 3 is a cross-sectional view of a configuration in which the stacked semiconductor device 20 is formed by the semiconductor element 1, the semiconductor element 2 ′, and the semiconductor element 3 ′ having different sizes using the above-described stacked components. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
Referring to FIG. 3, on the semiconductor element 1, a semiconductor element 2 ′ having a smaller size than the semiconductor element 1 is further larger than the semiconductor element 2 ′ and smaller than the semiconductor element 1. It is laminated on the interposer 11. The semiconductor elements 1 to 3 are held by laminated components 4 ′ to 6 ′ installed along the outer edges of the semiconductor elements 1 to 3, respectively, from the bottom surface to the side surface.
On one main surface (upper surface) of each of the semiconductor elements 1, 2 ′, 3 ′, an element such as an active element or a passive element (not shown) is formed, and a wiring connection is connected to these elements. Portions 1a, 2a ′ and 3a ′ are installed, and further, wiring contact portions 1b, 2b ′ and 3b ′ are respectively installed on the wiring connection portions 1a, 2a ′ and 3a ′. The wiring contact portions 1b, 2b ′, 3b ′ are connected to wiring portions, which will be described later, installed in the laminated parts 4 ′ to 6 ′.
The wiring of the stacked semiconductor device 10 is formed by the wiring components described above and the stacked contact portions 1c to 3c installed under the stacked components 4 ′ to 6 ′ connected to the wiring portion. The formed wiring is connected to the contact portion 9 of the interposer through the laminated contact portion 1c.
As shown in this figure, by using the above-described laminated component, it is possible to form a laminated semiconductor device in which a semiconductor element larger than the semiconductor element is laminated on the semiconductor element. In other words, since there is no restriction on the size of the semiconductor element when forming the stacked semiconductor device, there is an effect that the degree of freedom in designing the stacked semiconductor device is improved.
Next, the details of the wiring method using the above-described laminated component will be described with reference to FIG. FIG. 4 is an enlarged view of a part of the stacked semiconductor device shown in FIG. However, in the figure, the same reference numerals are given to the parts described above, and a part of the description will be omitted.
Referring to FIG. 4, first, taking the case of the laminated component 4 as an example, the outline of the laminated component 4 is as follows. A thin plate made of an insulator is bent into a substantially U-shape and the side surface of the semiconductor element 1 is viewed from the side. The wiring board 4a formed along the outer edge of the upper surface, the wiring part 4b formed on the surface of the wiring board 4a on the side inscribed in the semiconductor element 1, and the insulator formed on the inner side of the wiring component 4b A protective layer 4c.
The wiring portion 4b is led out to the outside of the wiring substrate 4a through the through hole of the wiring substrate 4a on the upper surface side (the side where the wiring connection portion is installed) of the semiconductor element 1 and is placed on the wiring portion 4b. A contact electrode 4g is formed. Similarly, the wiring part 4b is led out to the outside of the wiring board 4a through the through hole of the wiring board 4a on the lower surface side (the side facing the upper surface side) of the semiconductor element 1 to the wiring part 4b. A contact electrode 4f is formed.
The contact electrode 4g is connected to a contact electrode 5f that contacts a wiring portion 5b disposed on the multilayer component 5, and the contact electrode 4f is a wiring portion (not shown) formed on the interposer 11. And is electrically connected to a contact portion 9 installed on the lower surface thereof. The wiring part 4b and the wiring contact part 1b are connected via a contact electrode 4h.
As in the case of the wiring part 4b, the wiring part 5b arranged in the multilayer component 5 has a structure sandwiched between the target board 5a and the protective layer 5c. It is formed along the upper surface.
The wiring portion 5b is led out from the through hole of the wiring substrate 5a on the upper surface side (the side where the wiring connection portion is formed) of the semiconductor element 2, and a contact electrode 5g is formed on the wiring portion 5b. Yes. Further, the wiring part 5b and the wiring contact part 2b are connected via a contact electrode 5h.
Next, regarding the multilayer component 6, the wiring part 6b disposed in the multilayer component 6 has a structure sandwiched between the wiring substrate 6a and the protective layer 6c, as in the case of the wiring parts 4b and 5b. And is formed along the lower surface, outer edge, and upper surface of the semiconductor element 3.
The wiring portion 6b is led out from a through hole of the wiring substrate 6a on the lower surface side of the semiconductor element 3, and a contact electrode 6f is formed on the wiring portion 6b. The wiring part 6b is connected to the wiring part 5b through the contact electrodes 6f and 5g. The wiring part 6b and the wiring contact part 3b are connected via a contact electrode 6h.
Thus, the wiring connection parts 1a to 3a of the semiconductor elements 1 to 3 and the contact part 9 of the interposer 11 are electrically connected by the laminated parts 4 to 6, respectively. Further, the laminated components 4 to 6 also serve to hold the semiconductor elements 1 to 3, respectively. Further, the details of the structure using such a laminated part will be described in detail below with reference to FIG. 5, taking the laminated part 5 as an example.
FIG. 5 is a further enlarged view of the laminated component 5 and the semiconductor element 2. However, in the figure, the same reference numerals are given to the parts described above, and a part of the description will be omitted.
In such a configuration, the semiconductor element 2 has a thickness of, for example, 25 μm or more, and an active element and a passive element (not shown) are provided, and the wiring connection made of, for example, Al electrically connected to these elements. This is a Si semiconductor chip in which the portion 2a is arranged. Further, a wiring contact portion 2b is formed on the wiring connection portion 2a.
As described above, the wiring substrate 5a is disposed so as to extend along the outer surface of the semiconductor element 2 from the lower surface to the side surface, and is made of an insulating thin film, for example, polyimide having a thickness of about 20 to 75 μm.
The wiring portion 5b formed inside the wiring substrate 5a is made of copper (Cu) having a thickness of 2 to 10 μm.
The protective layer 5c formed so as to cover the wiring portion 5b is formed of a thin film made of an insulating material having tackiness, for example, a polyimide film having a thickness of 5 μm. If the protective layer 5c is made of, for example, a double-sided adhesive tape made of polyimide, the wiring part 5b and the wiring board 5a can be fixed to the semiconductor element 2 by the adhesive force of the double-sided tape. For this reason, it is not necessary to use a fixing coagulant such as a MOLD resin.
The wiring portion 5b is led out to the outside of the wiring board 5a through a through hole 5d formed in the wiring board 5a on the lower surface side of the semiconductor element 2, and is further Ni (2 μm) / Au (0.5 μm). ) A solder plating layer (10 μm) is formed on the plating layer to form the wiring electrode 5f.
Similarly, the wiring portion 5b is led out to the outside of the wiring substrate 5a through the through hole 5e formed in the wiring substrate 5a on the upper surface side of the semiconductor element 1, and further Ni (2 μm) / Au (0 .5 μm) A solder plating layer (10 μm) is formed on the plating layer to form a wiring electrode 5 g.
Further, the wiring part 5b and the wiring contact part 2b are electrically connected by the contact electrode 5h formed on the surface of the wiring part 5b. The contact electrode 5h has a structure in which a solder plating layer (10 μm) is formed on an Au stud bump or a Ni (2 μm) / Au (0.5 μm) plating layer.
Since the multilayer semiconductor device using the multilayer component according to the present invention has a wiring shape along the outer edge of the semiconductor element, the wiring space for wire bonding is unnecessary as compared with the conventional wire bonding type, so it is smaller. Can be realized.
Furthermore, it is easy to arrange another semiconductor element on the upper surface or the lower surface of the semiconductor element to form a laminated structure. That is, as described above, for example, a stacked structure in which another semiconductor element having the same size as that of the semiconductor element or a larger semiconductor element is placed on the semiconductor element can be provided, and the size of the stacked semiconductor element is eliminated, so that the stacked type The degree of freedom in designing semiconductor devices is expanded.
Further, the laminated component 5 has a structure in which the surface of the wiring portion 5b in contact with the semiconductor element 2 is covered with the protective layer 5c made of an insulator. For this reason, when the laminated component 5 is used, it is not necessary to form an insulating film on the surface of the semiconductor element 2 facing the wiring portion 5b.
Furthermore, when mounting using a plurality of stacked semiconductor devices according to the present invention, since the wiring portion 5b is covered with the wiring substrate 5a, the wiring portion 5b is adjacent to another stacked type. There is no problem of electrical shorting in contact with the wiring portion of the semiconductor device. Therefore, the stacked semiconductor device according to the present invention can be installed at a narrow pitch.
In addition, when wiring using the wiring part 5b is performed using the multilayer component 5, wiring length variation is smaller than that of the conventional wire method, and the wiring length is the same and the wiring length is very accurate. Is possible. This is advantageous in terms of, for example, electrical characteristics and speedup when considering SiP (system in packaging), which will have higher performance in the future.
Next, a method for mounting the above-described laminated component on a semiconductor element will be described with reference to FIGS. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
FIG. 6A is a perspective view of the semiconductor device 2. As described above, the semiconductor element is formed with an element such as an active element or a passive element (not shown), and a wiring connection portion 2a connected to these elements is installed. Further, the wiring connection portion A wiring contact portion 2b is installed on each 2a.
FIG. 6B is a perspective view in which the laminated component 5 is mounted on the semiconductor element 2. FIG. 3 is a perspective view in which four laminated parts 5 are mounted on the semiconductor element 1. When mounting the multilayer component 5 on the semiconductor element 2, it is necessary to bring the contact electrode 5h (not shown in this figure, but shown in FIG. 5) of the multilayer component 5 into contact with the wiring contact portion 2b. Yes. An alignment mark 5 i is provided on the laminated part 5 because accurate alignment is required.
In addition, it is also possible to perform individual performance tests in the state shown in FIG. 6B in which the semiconductor element 2 and the laminated part 5 are combined before the lamination part is mounted on the semiconductor element and laminated.
Next, the manufacturing method of the above-described laminated component will be described below with reference to FIGS.
FIG. 7A is a diagram in which the laminated component 5 that is bent substantially in a U shape as shown in FIG. 7B is developed on a plane. The laminated component 5 is manufactured as follows.
First, the wiring part 5b made of, for example, Cu corresponding to the thickness of the semiconductor element 2 and corresponding to the position of the wiring contact part 2b is formed on the surface of the wiring board 5a made of polyimide.
Further, the protective layer 5c made of polyimide, for example, is formed so as to cover a part of the wiring part 5b, and the laminated component 5 is formed.
The reason why polyimide is used for the wiring substrate 5a and the protective layer 5c is, for example, a MOLD process (175 ° C.), a solder reflow process (240 ° C.), and a heat process during substrate mounting (steps). This is because there is a process exposed to high temperature such as 260 ° C., and heat resistance is required. Other materials can be used as long as the insulator has heat resistance.
FIG. 7B is a perspective view in which the laminated component 5 is bent into a substantially U shape and attached to the semiconductor element 2.
The laminated component 5 is a laminated component used when the semiconductor element 2 and a semiconductor element having the same size as the semiconductor element 2 are laminated. An example of the manufacturing method in this case is shown in FIGS.
FIG. 8A is a plan view in which the laminated component 4 ′ shown in FIG. 3 in which the semiconductor elements having different sizes are laminated and bent in a substantially U-shape is developed in a plane.
Referring to FIG. 8A, the wiring board 4a ′ made of polyimide is a combination of a trapezoid and a rectangle as shown in the drawing in order to stack semiconductor elements having different sizes. Therefore, on the wiring substrate 4a ′, a wiring element 4b ′ made of Cu, for example, corresponding to the wiring contact part of the semiconductor element held by the multilayer component 4 ′ and another semiconductor element stacked on the semiconductor element is formed. To do.
Further, the protective layer 4c ′ made of, for example, polyimide is formed so as to cover a part of the wiring part 4b ′, and the laminated component 5 is formed.
FIG. 8B is a perspective view in which the laminated component 4 ′ is bent in a substantially U shape and attached to the semiconductor element 1. As shown in FIG. 3, the semiconductor element 1 is held by the multilayer component 4 ′, and the semiconductor element 2 ′ smaller than the semiconductor element 1 is further laminated on the multilayer component 4 ′.
Next, a method for installing the laminated component on the semiconductor element will be described below with reference to FIGS. 9A, B to 13A, B.
9A and 9B are views showing an installation method for installing the laminated component 5 on the semiconductor element 1, FIG. 9A is a sectional view thereof, and FIG. 9B is a perspective view thereof. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
Referring to FIG. 9A, the semiconductor element 2 is accommodated in a U-shaped space of the laminated component 5 bent in a substantially U-shape. The laminated component 5 is placed on a block 201 with temperature control. Here, the temperature of the multilayer component 5 and the semiconductor element 2 is controlled by the block with temperature control, and the contact electrode 5h (the book) of the wiring contact portion 2b and the multilayer component 5 is connected by the connecting jig 200. (Not shown in the figure, shown in FIG. 5) are electrically connected. The connection is performed by reflow processing of solder that is a part of the constituent material of the contact electrode 5h. At that time, the connection is made point by point according to the number of the wiring contact portions 2b and the contact electrodes 5h.
FIG. 9B is a perspective view of the installation method shown in FIG. 9A. As shown in the figure, the wiring contact portion 2b and the contact electrode 5h are connected one by one by the connection tool 200. Moreover, the installation method shown to FIG. 9A-B can be changed like FIG.
10A and 10B are modified examples of the installation method for installing the laminated component 5 shown in FIGS. 9A and 9B on the semiconductor element 1, FIG. 10A is a sectional view thereof, and FIG. 10B is a perspective view thereof. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
Referring to FIG. 10A, in this figure, the connection tool 200 used in FIG. 9A is changed to a connection tool 300. This is because the shape of the connection tool is changed to simultaneously connect the plurality of wiring contact portions 2b and the contact electrodes 5h.
Referring to FIG. 10B, a plurality of connection locations between the wiring contact portion 2 b and the contact electrode 5 h are simultaneously performed by the connection tool 300. For this reason, compared with the case of above-mentioned FIG. 9A-B, the efficiency of the connection operation | work of the said wiring contact part 2b and the said contact electrode 5h improves.
Furthermore, in order to further increase the efficiency of the connection work between the wiring contact portion 2b and the contact electrode 5h, the connection method may be changed to FIGS. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
Referring to FIG. 11A, the connection tool 400 is used in this figure, but the connection tool 400 is a larger connection tool than the connection tool 300. In the wiring connection method shown in this figure, the connection tool 400 is used to connect all the wiring contact portions 2b to be connected and the contact electrodes 5h at the same time.
FIG. 11B is a perspective view of the connection method shown in FIG. 11A, in which a plurality of the laminated parts 5 and all of the wiring contact portions 2b and the contact electrodes 5h of the laminated parts 5 are simultaneously connected. For this reason, it is possible to further improve work efficiency compared with the case shown in FIGS.
In addition, as an example of the process of attaching the multilayer component 5 to the semiconductor element 2 and then connecting the wiring contact portion 2b and the contact electrode 5h to install the multilayer component 5 on the semiconductor element 2, A procedure will be described with reference to FIGS.
12A to 12C show the installation process of installing the laminated component 5 on the semiconductor element 2 step by step. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
First, referring to FIG. 12A, first, the connection work of the contact electrode 5h (not shown in the figure and shown in FIG. 5) of the laminated component 5 on the plane to the wiring contact portion 2b is performed. Do.
Thereafter, as shown in FIG. 12B, the laminated component 5 is bent, and first, the laminated component 5 is bent along the side surface from the upper surface of the semiconductor element 2.
Next, as shown in FIG. 12C, the multilayer component 5 is bent along the lower surface of the semiconductor element 2 to complete the installation of the multilayer component 5 on the semiconductor element 2. Further, the steps shown in FIGS. 12A to 12C can be changed as shown in FIGS.
FIGS. 13A and 13B show the steps of installing the laminated component 5 on the semiconductor element 1 step by step. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
First, referring to FIG. 13A, the laminated component 5 bent in advance to the shape shown in the drawing is placed on the semiconductor element 2 along the lower surface and the outer edge of the side surface of the semiconductor element 2.
Thereafter, as shown in 13B, the laminated component 5 is bent. Then, as described above with reference to FIGS. 9A to 9B, the wiring contact portion 2b and the contact electrode 5h are connected. Further, the method of connecting the wiring contact portion 2b and the contact electrode 5h at this time may be the method shown in FIGS. 10A to 10B or may be performed by the method shown in FIGS.
As described above, the procedure of connecting the wiring contact portion 2b and the contact electrode 5h, bending the laminated component 5 and installing the laminated component 5 on the semiconductor element 2 can be arbitrarily changed. Even if the procedure is changed, it can be installed in the same manner.
Next, an example of an embodiment of a stacked semiconductor device formed using stacked components will be described with reference to FIGS. 14A and 14A to 15A and 15B.
14A and 14B are examples of a stacked semiconductor device formed using stacked components according to the present invention. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
First, referring to FIG. 14A, the stacked semiconductor device 10 </ b> A shown in this drawing is a modified example of the stacked semiconductor device 10 shown in FIG. 2.
In the present embodiment, the semiconductor elements 1 to 3 and the laminated parts 4 to 6 are fixed to the interposer 11 with a MOLD resin 500. In the case of the stacked semiconductor device 10 shown in FIG. 2, the semiconductor elements 1 to 3 are fixed to the interposer 11 by the stacked components 4 to 6. There is an effect that becomes unnecessary. However, as shown in FIG. 14A, when the semiconductor elements 1 to 3 and the stacking components 4 to 6 are fixed by the MOLD resin 500, the stability due to the fixing is increased, and the stacked semiconductor element 10A is fixed. When an impact is applied, the possibility of problems such as peeling of the semiconductor element is further reduced, and the reliability is further improved.
FIG. 14B shows a modified example of the stacked semiconductor device 20 shown in FIG.
In the present embodiment, the semiconductor elements 1, 2 ′, 3 ′ and the laminated components 4 ′, 5 ′, 6 ′ are fixed to the interposer 11 with a MOLD resin 500. Similarly in this case, when the semiconductor elements 1, 2 ′, 3 ′ and the laminating components 4 ′, 5 ′, 6 ′ are fixed by the MOLD resin 500, the stability due to the fixing is increased, and the stacking is performed. When an impact is applied to the type semiconductor element 20A, the possibility of problems such as peeling of the semiconductor element is further reduced, and the reliability is further improved.
Further, an embodiment in which a semiconductor element having a light receiving portion is stacked on the stacked semiconductor device 20A shown in FIG. 14B is shown in FIGS.
FIG. 15A is a cross-sectional view of a stacked semiconductor device 20B, which is an example in which a light receiving unit 600 is stacked on the semiconductor element 3 of the stacked semiconductor device 20A. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
In the stacked semiconductor device 20 </ b> B, an opening 501 is provided above the MOLD resin 500, and a light receiving unit 600 is mounted on the semiconductor element 3. For the light receiving unit 600, for example, a fingerprint sensor or a light receiving element can be used.
The semiconductor elements 1 and 2 are mounted with a drive circuit, an output circuit, a hydrochloric acid circuit, and the like. In such a stacked semiconductor device according to the present invention, the space for wire bonding is not required as compared with a conventional product, so that the entire package can be reduced in size. In addition, another semiconductor element can be stacked in a space on the wiring connection portion of the semiconductor element, and a semiconductor element having the same size or larger than the semiconductor element can be stacked. That is, in the stacked semiconductor device, there is no limitation on the size of the semiconductor elements to be stacked. In addition, since the wiring portion is structured to be covered with an insulator, when a plurality of stacked semiconductor devices are mounted, there is no problem that the wiring contacts in an adjacent semiconductor device, so that high-density mounting is possible. .
FIG. 15B shows a cross-sectional view of a stacked semiconductor device 20C, which is a modification of the stacked semiconductor device 20B shown in FIG. 15A.
In the case of the stacked semiconductor image 20C shown in the figure, a material that transmits light is used for the MOLD resin 500A. Therefore, it is not necessary to provide an opening in the MOD resin. Also in the stacked semiconductor device 20C, the entire package can be reduced in size as compared with the conventional product. Also in this case, the entire package can be reduced in size as compared with the conventional product, and the size of the semiconductor element stacked in the stacked semiconductor device is not limited. There is an advantage that the degree of freedom is large. Furthermore, since the wiring portion is structured to be covered with an insulator, when a plurality of stacked semiconductor devices are mounted, there is no problem that the wiring contacts in adjacent semiconductor devices, so that high-density mounting is possible. .
Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the specific embodiments described above, and various modifications and changes can be made within the scope described in the claims.
For example, FIG. 16 shows that in the stacked semiconductor device 10 shown in FIG. 2, only the semiconductor element 1 and the stacked component 4 are used without using the semiconductor elements 2 and 3, and further on the semiconductor element 1. An example of the semiconductor device 10B including the light receiving unit 600 will be described. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.
In the case of the semiconductor device 10B, a semiconductor element is used as a single layer without being stacked. In this case, it is possible to use the light receiving unit 600 as a fingerprint sensor, which has been difficult with conventional flip chip bonding. In this case, the pressure applied by the finger is effective in absorbing the stress by using the wiring board 4a as a buffer material.
In addition, the semiconductor device of the present invention can be modified and changed as necessary, and is not limited to the contents described above in the embodiment.
A semiconductor element having a plurality of electrodes disposed on one main surface, a wiring substrate having a plurality of conductive layers disposed on an insulating substrate, and an interposer,
Four wiring boards are arranged in a substantially U shape along the outer edge of the semiconductor element, corresponding to each of the four sides of the semiconductor element, and the conductive layers of the wiring board are arranged. One end is connected to the electrode of the semiconductor element, and the other end of the conductive layer is led out in the direction different from the semiconductor element on the other main surface side of the semiconductor element, and is electrically connected to the contact portion of the interposer. A semiconductor device connected to the semiconductor device.
2. The semiconductor device according to claim 1, wherein the wiring substrate includes the insulating substrate, the conductive layer disposed on one surface thereof, and a protective insulating layer that selectively covers the conductive layer.
The semiconductor device according to claim 1, wherein the conductive layer is electrically connected to an electrode disposed in another semiconductor element.
The semiconductor device according to claim 1, wherein the conductive layer passes through a through hole formed in the insulating substrate and is led out from the one surface of the insulating substrate to the other surface.
The semiconductor device according to claim 1, wherein the conductive layer is made of a metal material.
The semiconductor device according to claim 1, wherein the insulating substrate is made of polyimide.
The semiconductor device according to claim 2, wherein the protective insulating layer is made of polyimide.
3. The semiconductor device according to claim 2, wherein the protective insulating layer has adhesiveness, and the wiring board is fixed to the semiconductor element by the adhesiveness.
JP2004560577A 2002-12-17 2002-12-17 Semiconductor device Expired - Fee Related JP4208840B2 (en)
PCT/JP2002/013198 WO2004055891A1 (en) 2002-12-17 2002-12-17 Semiconductor device and stacked semiconductor device
JPWO2004055891A1 JPWO2004055891A1 (en) 2006-04-20
JP4208840B2 true JP4208840B2 (en) 2009-01-14
ID=32587958
JP2004560577A Expired - Fee Related JP4208840B2 (en) 2002-12-17 2002-12-17 Semiconductor device
US (1) US7196418B2 (en)
JP (1) JP4208840B2 (en)
CN (1) CN1650426A (en)
TW (1) TWI236759B (en)
WO (1) WO2004055891A1 (en)
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2002-12-17 WO PCT/JP2002/013198 patent/WO2004055891A1/en active Application Filing
2002-12-17 JP JP2004560577A patent/JP4208840B2/en not_active Expired - Fee Related
2002-12-25 TW TW091137350A patent/TWI236759B/en not_active IP Right Cessation
2005-01-26 US US11/042,347 patent/US7196418B2/en not_active Expired - Fee Related
US20050161793A1 (en) 2005-07-28
WO2004055891A9 (en) 2004-11-18
US7196418B2 (en) 2007-03-27
CN1650426A (en) 2005-08-03
JPWO2004055891A1 (en) 2006-04-20
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