Source: http://www.google.com/patents/US7483323?dq=oakley+5,387,949&ei=4yI4T8nkLYa80QG0xqnWAg
Timestamp: 2013-12-05 06:19:50
Document Index: 369805580

Matched Legal Cases: ['art 90', 'arts 90', 'arts 90', 'art 90', 'art 90', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 98', 'art 94', 'arts 94', 'arts 94', 'art 94', 'art 94']

Patent US7483323 - Semiconductor memory device, and method of controlling the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsAn internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage...http://www.google.com/patents/US7483323?utm_source=gb-gplus-sharePatent US7483323 - Semiconductor memory device, and method of controlling the samePublication numberUS7483323 B2Publication typeGrantApplication numberUS 11/515,853Publication dateJan 27, 2009Filing dateSep 6, 2006Priority dateNov 9, 1999Fee statusPaidAlso published asUS6563746, US6584032, US6868026, US6947347, US7495986, US7688661, US7869296, US7903487, US8130586, US20010043493, US20020009012, US20030161190, US20030227810, US20040057267, US20050262369, US20070002664, US20070014178, US20090010080, US20090016142, US20100302879, US20120120739Publication number11515853, 515853, US 7483323 B2, US 7483323B2, US-B2-7483323, US7483323 B2, US7483323B2InventorsShinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku SatoOriginal AssigneeFujitsu Microelectronics LimitedPatent Citations (38), Non-Patent Citations (1), Classifications (31), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor memory device, and method of controlling the sameUS 7483323 B2Abstract An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
1. A method of controlling a dynamic random access memory including dynamic memory cells, an internal voltage generator generating an internal voltage to be supplied to an internal voltage line, and a power supplying circuit supplying a power supply voltage as said internal voltage, the memory having a low power consumption mode, in which the dynamic memory cells do not retain data therein by prohibiting refresh operations, and an idle mode, comprising the steps of:
providing a first command to the memory for entering the idle mode which operates said internal voltage generator and stops operation of said power supplying circuit; and
providing a second command to the memory during the idle mode for entering the low power consumption mode which provides said power supply voltage as said internal voltage by operating said power supplying circuit and stopping operation of said internal voltage generator.
2. The method of controlling the dynamic random access memory according to claim 1,
wherein the memory enters the low power consumption mode in response to a voltage change of one control signal as the second command.
3. The method of controlling the dynamic random access memory according to claim 2, wherein the memory maintains the low power consumption mode while the control signal keeps a first level.
4. The method of controlling the dynamic random access memory according to claim 1 or 2, wherein the second command comprises a combination of control signals.
5. The method of controlling the dynamic random access memory according to claim 1, further comprising the step of:
providing a third command to the memory for exiting from the low power consumption mode.
6. The method of controlling the dynamic random access memory according to claim 5,
wherein the memory enters the low power consumption mode in response to a voltage change of one control signal as the second command, and the memory exits the low power consumption mode in response to a reverse voltage change of the control signal.
7. The method of controlling the dynamic random access memory according to claim 5, wherein the memory is initialized after the exit from the low power consumption mode.
8. The method of controlling the dynamic random access memory according to claim 7, wherein the memory enters the idle mode after an initialization period during which the memory is initialized.
9. The method of controlling the dynamic random access memory according to claim 1, wherein the dynamic random access memory is one of SDRAM, DDR SDRAM and FCRAM.
10. The method of controlling the dynamic random access memory according to claim 1, wherein the dynamic random access memory is equipped with a cellular phone.
11. The method of controlling a dynamic random access memory according to claim 1, wherein:
said internal voltage generator generates a voltage lower than an external power supply voltage as said internal voltage, and
said power supply voltage is the external power voltage.
12. The method of controlling a dynamic random access memory according to claim 1, wherein:
said internal voltage generator generates a booster voltage higher than an external power supply voltage as said internal voltage, and
13. The method of controlling a dynamic random access memory according to claim 1, wherein:
said internal voltage generator respectively generates a voltage lower than an external power supply voltage as said internal voltage and a booster voltage higher than the external power supply voltage as another internal voltage higher than the external power supply voltage as another internal voltage, and
said power supplying circuit supplies a power supply voltage common for both internal voltages during said low power consumption mode.
14. The method of controlling a dynamic random access memory according to claim 1, wherein:
said internal voltage generator generates a negative voltage as said internal voltage, and
said power supply voltage is a ground voltage.
15. The method of controlling a dynamic random access memory according to claim 1, wherein;
said internal voltage generator generates a precharge voltage for a bit line connected to said dynamic memory cells as said internal voltage, and
16. The method of controlling a dynamic random access memory according to claim 1, wherein:
said internal voltage generator generates a precharge voltage respectively for a bit line connected to said dynamic memory cells and a negative voltage as said internal voltage and another internal voltage, and
CROSS-REFERENCE TO RELATED APPLICATIONS This is a Division of application Ser. No. 11/189,858 filed Jul. 27, 2005, which is a Division of application Ser. No. 10/623,544 filed Jul. 22, 2003, now U.S. Pat. No. 6,947,347, which is a Division of application Ser. No. 10/365,456, filed Feb. 13, 2003, now U.S. Pat. No. 6,868,026, which is a Division of application Ser. No. 09/820,795, filed Mar. 30, 2001, now U.S. Pat. No. 6,563,746 B2, which is a Continuation-in-Part of application Ser. No. 09/675,198 filed Sep. 29, 2000, now abandoned. The disclosure of the prior applications is hereby incorporated by reference herein in its entirety.
SUMMARY OF THE INVENTION An object of the present invention is to enter the device into a low power consumption mode and exit the device from a low power consumption mode with reliability.
BRIEF DESCRIPTION OF THE DRAWINGS The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:
The DRAM is supplied with a power supply voltage VDD (e.g., 2.5 V) from the exterior, a ground voltage VSS, chip enable signals /CE1 and CE2 as the control signals, a plurality of address signal AD, a plurality of data input/output signals DQ, and another control signal CN. This DRAM does not adopt the address multiplex method. Therefore, the address signals AD is supplied once at each read operation and at each write operation. The power supply voltage VDD and the ground voltage VSS are supplied to almost all the circuits excepting a partial circuit of the memory core 38. Here, the signals headed by the letter �/� are those of negative logic. The �address signals AD� may be abbreviated into the �AD signals� in the following description by omitting its signal name.
First of all, when the power supply is switched on, the power supply voltage VDD rises gradually (FIG. 7( a)). The VDD starter 12 shown in FIG. 3 inactivates the start signal STTCRX (to the low level) till the power supply voltage VDD reaches a predetermined voltage (FIG. 7( b)). By this control, it is possible to prevent the ULP signal from being activated due to the malfunctioning of the low power entry circuit 14 when the power supply is switched on. An exterior controller (e.g., a CPU or a memory controller) for controlling the DRAM turns the CE2 signal at the high level a predetermined time T0 after the power supply voltage VDD reaches the minimum operable voltage VDDmin (FIG. 7( c)).
After this, the DRAM becomes the standby state or executes an ordinary operation. The exterior controller turns the CE2 signal to the low level when the DRAM enters the low power consumption mode (FIG. 7( d)). The low power entry circuit 14 activates the ULP signal (to the high level) in response to the fall of the CE2 signal when the STTCRX signal is at the high level (FIG. 7( e)).
When these circuits are inactivated, the generations of the boost voltage VPP, the precharging voltage VPR, the internal supply voltage VII and the substrate voltage VBB are stopped. However, the boost voltage VPP and the internal supply voltage VII are changed into the power supply voltage VDD by the VDD supplying circuit 26, and the substrate voltage VBB and the precharging circuit VPR are changed into the ground voltage VSS by the VSS supplying circuit 36. Therefore, the internal circuit of the main circuit unit 20 is prevented from having a leak path.
The exterior controller turns the CE2 signal to the high level when the low power consumption mode is released (FIG. 7( f)). In response to the high level of the CE2 signal, the low power entry circuit 14 inactivates the ULP signal (to the low level) (FIG. 7( g)). In response to the inactivation of the ULP signal, the low-pass filter 22 supplies the power supply voltage VDD to the reference voltage generator 24. In response to the inactivation of the ULP signal, the VDD supplying circuit 26 and the VSS supplying circuit 36 stop the supplies of the power supply voltage VDD and the ground voltage VSS. Then, the booster 28, the precharging voltage generator 30, the internal supply voltage generator 32 and the substrate voltage generator 34 are activated again to start their operations.
When the cellular phone then enters the service state from the waiting state, the CPU raises the CE2 signal shown in FIG. 8 to the high level. After the DRAM entered the idle mode, the data retained in the flash memory are transferred to the DRAM (FIG. 9( a)). During the service state, the DRAM is used as the work memory. Here, the service state includes not only the state of exchanging vocal communications but also the state of transferring data.
When the service state shifts to the waiting state, those, of the data of the DRAM, necessary to be retained are saved in the flash memory (FIG. 9( b)). After this, the CPU lowers the CE2 signal to the low level and enters the DRAM to the low power consumption mode. The DRAM does not perform refresh operation in the low power consumption mode so that the unnecessary data is lost.
A predetermined time after the power supply was switched on, the STTCRX signal turns to the high level (FIG. 13( a)). After this, the exterior controller for controlling the DRAM raises the CE2 signal to the high level (FIG. 13( b)). The timings above are identical to those of the first embodiment. In response to the high level of the CE2Z signal, the node ND1 shown in FIG. 12 turns to the high level (FIG. 13( c)).
The initial cycle is executed to turn the RASX signal to the low level (FIG. 13( d)). In response to the low level of the RASX signal, the RS flip-flop 58 raises the node ND2 to the high level (FIG. 13( e)). After this, there are started the operations of the internal voltage generator 18 shown in FIG. 11.
The timing adjusting circuit 54 a turns the node ND1 to the low level about 100 ns after receiving the low level of the CE2Z signal (FIG. 13( f)). 100 ns or more after the falling edge of the CE2Z signal, the CE1X signal is turned to the low level (FIG. 13( g)). In response to the low level of the CE1Z signal and the low level of the node ND1, the combinational circuit 60 shown in FIG. 12 turns the node ND3 to the low level (FIG. 13( h)). The timing adjusting circuit 54 b raises the ULP signal to the high level (FIG. 13( i)) about 100 ns after receiving the low level of the node ND3. The DRAM enters the low power consumption mode.
When the low power consumption mode is released, the CE1X signal is first turned to the high level (FIG. 13( j)). The combinational circuit 60 receives the high level of the CE1X lo signal to turn the node ND3 to the high level (FIG. 13( k)) and the ULP signal to the low level (FIG. 13( l)). 200 μs after the rising edge of the CE1X signal, the CE2Z signal is turned to the high level (FIG. 13( m)). In response to the high level of the CE2Z signal, a level of the node ND1 turns to the high level. During this period of 200 μs, the internal voltage generator 18 is activated to stabilize the individual internal voltages VPP, VPR, VII and VBB at predetermined levels.
The output voltage of the differential amplifier 74 a goes low when the internal power supply voltage VII is lower than the reference voltage VREF. The differential amplifier 74 a comprises a MOS capacitor 74 c for receiving the reference voltage VREF in order to prevent its response to insignificant fluctuation of the reference voltage VREF. In addition, an nMOS 74 d for receiving the reference voltage VREF is disposed on a path to a ground line VSS in order to limit the amount of current flow to the ground line VSS and reduce the power consumption during the operation of the differential amplifier 74 a. The nMOS 74 d operates as high-resistance. An inverter 74 e in the initial stage of the inverter row 74 b has an nMOS connected in serial so as to have the logic threshold of an input signal in conformity with the output of the differential amplifier 74 a. A power-on circuit 76 turns a start signal STT to high level during a predetermined period since the power supply voltage is supplied to the DRAM. An OR circuit 78, upon receiving the high level of a start signal STTPZ or the high level of the start signal STT, outputs the high level of a start signal STTVII (reset signal). The start signal STTVII, similarly to that of FIG. 3, is supplied to the main circuit unit 20 and initializes a predetermined internal circuit.
Firstly, when the CE2 signal (not shown) is turned to low level, the DRAM enters the low power consumption mode by a low power entry circuit 14 shown in FIG. 3 and a generator for the internal power supply voltage VII terminates its operation. The internal power supply voltage VII (for example, 2.0V in a normal operation) becomes equal to the power supply voltage VDD (for example, 2.5V)(FIG. 17( a)) and an ULP signal turns to high level(FIG. 17( b)).
Subsequently, the CE2 signal being turned to high level, the DRAM is released from the low power consumption mode and the ULP signal turns to low level(FIG. 17( c)). In other words, the DRAM is released from the low power consumption mode in accordance with the level of the CE2 signal received during the low power consumption mode. The exit from the low power consumption mode is controlled by the low power entry circuit 14 shown in FIG. 3.
Receiving the falling edge of the ULP signal, the detecting circuit 72 a in FIG. 15 turns an LPLS signal to low level (pulse)(FIG. 17( d)). Receiving the low level of the LPLS signal, the flip-flop 72 c in FIG. 15 turns the REL signal to high level (FIG. 17( e)).
Due to the exit from the low power consumption mode, a power supply line of the internal power supply voltage VII and that of the power supply voltage VDD are disconnected and simultaneously the generator for the internal power supply voltage VII initiates its operation. The internal power supply voltage VII goes low for some time from the initiation of the generator(FIG. 17( f)). The differential amplifier 74 a in FIG. 16 outputs low level to the inverter row 74 b when the internal power supply voltage VII is lower than the reference voltage VREF(for example, 1.25V). The inverter row 74 b, upon receiving the low level of the differential amplifier 74 a, outputs the high level of the STTPZ signal(FIG. 17( g)). The OR circuit 78, upon receiving the high level of the STTPZ signal, turns a start signal STTVII to high level. The start signal STTVII functions as a reset signal and a predetermined internal circuit of the main circuit unit 20 shown in FIG. 3 is initialized.
After the exit from the low power consumption mode, by issuing an operation command to the DRAM, the RASZ signal is turned to high level(FIG. 17( h)) and the REL signal to low level(FIG. 17( i)). The differential amplifier 74 a is inactivated due to the low level of the REL signal.
One control signal(CE2 signal)enables the entry of a chip to the low power consumption mode and the exit of a chip from the low power consumption mode.
Firstly, when the CE2 signal(not shown) is turned to low level, the DRAM enters the low power consumption mode and a generator for the internal power supply voltage VII and a generator for the boost voltage VPP terminate their operation. The internal power supply voltage VII (for example, 2.0V in the normal operation) and the boost voltage VPP (for example, 3.7V in the normal operation) become equal to the power supply voltage VDD (for example, 2.5V)(FIG. 19( a)) and an ULP signal turns to high level (FIG. 18( b)).
Subsequently, the CE2 signal being turned to high level, the DRAM is released from the low power consumption mode and the ULP signal turns to low level (FIG. 19( c)). The LPLS signal is turned to low level (pulse) as well as in FIG. 17 (FIG. 19( d)) and the REL signal is turned to high level (FIG. 19( e)).
Due to the exit from the low power consumption mode, the power supply line of the internal power supply voltage VII and the power supply line of the power supply voltage VDD are disconnected and the generator for the internal power supply voltage VII initiates its operation. The internal power supply voltage VII goes low for some time from the initiation of the generator(FIG. 19( f)). The low level of the STT1X signal is output during a period where the internal power supply voltage VII is lower than the reference voltage VREF (for example, 1.25V) (FIG. 19( g)). Similarly, the connection between the power supply line of the boost voltage VPP and that of the power supply voltage VDD is disconnected and the generator for the boost voltage VPP initiates its operation. The boost voltage VPP goes low for some time from the initiation of the generator (FIG. 19( h)). The low level of the STT2X signal is output during a period where the boost voltage VPP is lower than the power supply voltage VDD (FIG. 19( i)).
The NAND gate 80 e in FIG. 18 outputs the high level of the STTPZ signal during a period where the STT1X signal or the STT2X signal is at low level (FIG. 19( j)). During the high level of the STTPZ signal, the start signal STTVII (FIG. 16) is turned to high level. The start signal STTVII functions as a reset signal and initializes a predetermined internal circuit of the main circuit unit 20 shown in FIG. 3.
After the exit from the low power consumption mode, the DRAM initiates its operation, thereby the RASZ signal being turned to high level (FIG. 19( k)) and the REL signal to low level(FIG. 19( l)) as well as in FIG. 17. The differential amplifier 80 a and 80 c are inactivated due to the low level of the REL signal.
Firstly, when the CE2 signal (not shown) is turned to low level, the CE2X signal is turned to high level and the DRAM enters the low power consumption mode. A generator for the internal power supply voltage VII and a generator for the boost voltage VPP terminate their operation. The CMOS inverter 82 a in FIG. 20 upon receiving the high level of the CE2X signal, turns the nMOS on and a node ND4 to low level (FIG. 21( a)). The differential amplifier 82 c turns a STTPZ signal to high level when the voltage of the node ND4 is lower than the reference voltage VREF (FIG. 21( b)).
Subsequently, the CE2 signal being turned to high level and the CE2X signal to low level, the DRAM is released from the low power consumption mode (FIG. 21( c)). The CMOS inverter 82 in FIG. 20 upon receiving the low level of the CE2X signal, turns the pMOS on and the node ND4 to high level (FIG. 21( d)). At this time the voltage of the node ND4 gradually rises in accordance with the time constant determined by the on-resistance of the pMOS and the CMOS capacitor. The differential amplifier 82 c turns the STTPZ signal to low level when the voltage of the node ND4 is higher than the reference voltage VREF (FIG. 21( e)).
Consequently, the STTPZ signal(reset signal) is activated (high level) and the internal circuit is initialized during a period T2 from the exit from the low power consumption mode. The period T2 is set after the exit from the low power consumption mode in correspondence with a period where the internal power supply voltage VII is lower than a predetermined voltage so that the operation of the internal circuit supplied with the internal power supply voltage VII can not be ensured. In other words, the start signal generator 82 operates as a timer for determining the length of the period T2.
The reference voltage generator 24 is provided with a reference voltage generator 24 a for generating a reference voltage VREF, a starter 24 b consisting of pMOS, a differential amplifier 24 c, and a regulator 24 d. The reference voltage generator 24 a has a current mirror circuit made of a pMOS, two nMOSes connected individually in series with the current mirror circuit, and a register connected between the source of one of the nMOSes and the ground line VSS. The output of the reference voltage generator 24 a is connected with the gate of one nMOS and the drain of the other nMOS, from which the reference voltage VREF is generated. The gate of the other nMOS is connected with the source of the one nMOS.
This VPP detector 90 is provided with a differential amplifier 90 a and a voltage generator 90 b for supplying its voltage to one input of the differential amplifier 90 a. This differential amplifier 90 a has a current mirror part 90 c composed of pMOSes, and a pair of differential input parts 90 d and 90 e composed of nMOSes. Both the inputs of the differential input parts 90 d and 90 e receive the reference voltage VPREF and a control voltage VPP2 which is generated by shifting the level of the boost voltage VPP from the voltage generator 90 b. The differential input part 90 d is connected with the ground line VSS through the nMOS which is always on, and the differential input part 90 e is connected with the ground line VSS through the nMOS which is turned on when the low power signal NAPX is inactivated.
This unit 112 is provided with an oscillator 112 a and a pumping circuit 112 b. The oscillator 112 a is constructed as a ring oscillator composed of odd stages of logic gates. The oscillator 112 a operates when the substrate voltage detection signal VBBDET is activated but when the low power signal NAPX is inactivated.
This unit 114 is provided with an oscillator 114 a and a pumping circuit 114 b. The oscillator 114 a is a circuit which is made by eliminating the logic of the low power signal NAPX from the oscillator 112 a of the unit 112. In short, the oscillator 114 a operates in response to the substrate voltage detection signal VBBDET even during the power consumption mode to generate the substrate voltage VBB. The pumping circuit 114 b is a circuit identical to the pumping circuit 12 b of the unit 12.
The detection unit 98 a includes: a reference voltage generating part 98 d having a resistor; a PMOS and a resistor connected in series between the internal power supply line VII and the ground line VSS; a level detecting part 98 e having two nMOSes connected in series; a CMOS inverter 98 f having a pMOS connected with the power supply line VII through a pMOS load circuit; and an nMOS 98 g for connecting the output node NOUT1 of the level detecting part 98 f with the ground line VSS. The gate of the pMOS of the reference voltage generating part 98 d and the gate of the nMOS 98 g receive the low power signal NAPX. Therefore, the detection unit 98 a is inactivated in the normal operation mode but is activated during the power consumption mode. The voltage of the output node NOUT1 of the level detecting part 98 e rises, when activated, with the rise of the substrate voltage VBB. In this embodiment, the CMOS inverter 98 f outputs the low level in response to the detection result (i.e., the voltage of the output node NOUT1) at the level detecting part 98 d when the substrate voltage VBB is boosted to −0.5 V. The OR circuit 98 c activates the substrate voltage detection signal VBBDET when it receives the low level from the CMOS inverter 98 f. In the detection unit 98 b, the gate of the pMOS of the reference voltage generating part 98 d and the gate of the nMOS 98 g are supplied with the inverted logic of the low power signal NAPX. The remaining constructions are identical to those of the detection unit 98 a. In this embodiment, the CMOS inverter 98 f outputs the low level in response to the detection result at the level detecting part 98 e (i.e., the voltage of the output node NOUT1) when the substrate voltage VBB rises to −1.0 V in the normal operation mode. The output of the reference voltage generating part 98 d of the detection unit 98 b has the ground voltage VSS (at 0 V) when the low power signal NAPX is at the low level (during the power consumption mode). Therefore, the output node NOUT2 of the level detecting part 98 e has the low level at all times. In short, the detection unit 98 b is inactivated during the power consumption mode.
This precharging voltage generator 94 is provided with differential amplifiers 94 a and 94 b and a VPR generator 94 c. The differential amplifier 94 a has a current mirror part 94 d composed of pMOSes, and a pair of differential input parts 94 e and 94 f composed of nMOSes. Both the inputs of the differential input parts 94 e and 94 f receive the reference voltage VPRREFL and the precharging voltage VPR. The differential input part 94 e is connected with the ground line VSS through the always on nMOS, and the differential input part 94 f is connected with the ground line VSS through the nMOS which is turned on when the low power signal NAPX is inactivated.
This oscillator 104 is provided with a ring oscillator 104 a having odd stages of CMOS inverters connected in cascade, and a buffer 104 b for extracting an oscillating signal OSCZ from the ring oscillator 104 a. Frames of broken lines in FIG. 33 are switches for adjusting the stage number (corresponding to the self-refreshing period) of the ring oscillator 104 a. The on/off of these switches are set by the blow of the polysilicon fuse or by the layout pattern of the photomask of the wiring layer. In this example, the stage number of the ring oscillator 104 a is set to �7�. The sources of the pMOSes and the nMOSes of the CMOS inverters are connected with the internal power supply line VII and the ground line VSS, respectively, through the pMOS loads and the nMOS loads. The gates of the pMOS loads and the nMOS loads are controlled with the control voltages PCNTL and NCNTL, respectively. The oscillator 104 has pMOSes and nMOSes for receiving the control of the low power signal NAPX. When the low power signal NAPX is activated, those pMOSes are turned on to fix the predetermined node of the ring oscillator 104 a to the high level, but the connections between the nMOSes of the CMOS inverters and the ground line VSS are broken when those nMOSes are turned off. As a result, the oscillator 104 stops its operation during the power consumption mode.
During the low power consumption mode, the operations of the unit 108 of the booster 92 and the unit 112 of the substrate voltage generator 100 are stopped so that the power consumption during the power consumption mode can be further reduced.
The foregoing sixth embodiment has been described on an example of operating the start signal generator 82 as a timer for determining the length of the period T2 at the exit from the low power consumption mode and activating a STTPZ signal(reset signal) for initializing an internal circuit during the period T2. The present invention is not limited to this embodiment. For example, at the time of the exit from the low power consumption mode, a counter operating in normal operation is operated as a timer so as to count a predetermined number. The reset signal for initializing an internal circuit may well be activated during a period where the counter counts the number. A refresh counter indicating the refresh address of memory cells or the like can be used as the counter.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5197026Apr 13, 1989Mar 23, 1993Microchip Technology IncorporatedTransparent EEPROM backup of DRAM memoriesUS5241680Oct 9, 1992Aug 31, 1993Grid Systems CorporationLow-power, standby mode computerUS5262998Aug 14, 1991Nov 16, 1993Micron Technology, Inc.Dynamic random access memory with operational sleep modeUS5365487Mar 24, 1992Nov 15, 1994Texas Instruments IncorporatedDRAM power management with self-refreshUS5461338Apr 16, 1993Oct 24, 1995Nec CorporationSemiconductor integrated circuit incorporated with substrate bias control circuitUS5465367Jul 19, 1994Nov 7, 1995Intel CorporationSlow memory refresh in a computer with a limited supply of powerUS5500827Aug 11, 1995Mar 19, 1996Apple Computer, Inc.Method and apparatus for improved DRAM refresh operationUS5544096Jun 6, 1995Aug 6, 1996Oki Electric Industry Co., Ltd.Semiconductor memory device having volatile storage unit and non-volatile storage unitUS5561384Nov 8, 1995Oct 1, 1996Advanced Micro Devices, Inc.Input/output driver circuit for isolating with minimal power consumption a peripheral component from a core sectionUS5570005Jun 6, 1995Oct 29, 1996Nippon Steel Semiconductor Corp.Wide range power supply for integrated circuitsUS5799200Sep 28, 1995Aug 25, 1998Emc CorporationPower failure responsive apparatus and method having a shadow dram, a flash ROM, an auxiliary battery, and a controllerUS5835102Oct 19, 1995Nov 10, 1998Sparta, Inc.System for transmission and recovery of digital data using video graphics display processor and method of operation thereofUS5970009Dec 30, 1997Oct 19, 1999International Business Machines CorporationReduced stand by power consumption in a DRAMUS5986959Jul 24, 1997Nov 16, 1999Mitsubishi Denki Kabushiki KaishaSemiconductor memory device having internal voltage down-converting circuit reducing current consumption upon power ONUS5987589Oct 24, 1997Nov 16, 1999Hitachi Ltd.Microcomputer and microcomputer systemUS6025707Mar 25, 1999Feb 15, 2000Lg Semicon Co., Ltd.Internal voltage generatorUS6058061Jul 7, 1998May 2, 2000Mitsubishi Denki Kabushiki KaishaSemiconductor circuit device with reduced power consumption in slow operation mode.US6134167Jun 4, 1998Oct 17, 2000Compaq Computer CorporationReducing power consumption in computer memoryUS6136647May 14, 1997Oct 24, 2000Mosel Vitelic IncMethod of forming interpoly dielectric and gate oxide in a memory cellUS6150860Dec 2, 1999Nov 21, 2000Hyundai Electronics Industries Co., Ltd.Internal voltage generatorUS6198663Jul 27, 1999Mar 6, 2001Rohm Co., Ltd.Non-volatile semiconductor memory ICUS6330639 *Jun 29, 1999Dec 11, 2001Intel CorporationMethod and apparatus for dynamically changing the sizes of pools that control the power consumption levels of memory devicesUS6370073Jan 23, 2001Apr 9, 2002Monlithic System Technology, Inc.Single-port multi-bank memory system having read and write buffers and method of operating sameUS6407949Dec 17, 1999Jun 18, 2002Qualcomm, IncorporatedMobile communication device having integrated embedded flash and SRAM memoryUS6445932Feb 19, 1997Sep 3, 2002Nokia Mobile Phones Ltd.Multi-service mobile stationUS6515928Aug 28, 2001Feb 4, 2003Fujitsu LimitedSemiconductor memory device having a plurality of low power consumption modesUS6529433 *Apr 3, 2001Mar 4, 2003Hynix Semiconductor, Inc.Refresh mechanism in dynamic memoriesUS6556477May 21, 2001Apr 29, 2003Ibm CorporationIntegrated chip having SRAM, DRAM and flash memory and method for fabricating the sameUS6584032Sep 12, 2001Jun 24, 2003Fujitsu LimitedDynamic random access memory having a low power consumption mode, and method of operating the sameUS6614684Jan 28, 2000Sep 2, 2003Hitachi, Ltd.Semiconductor integrated circuit and nonvolatile memory elementUS6670234Jun 22, 2001Dec 30, 2003International Business Machines CorporationMethod of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereofUS6795362 *Aug 27, 2002Sep 21, 2004Elpida Memory, Inc.Power controlling method for semiconductor storage device and semiconductor storage device employing sameUS6826106Sep 4, 2003Nov 30, 2004Cypress Semiconductor Corp.Asynchronous hidden refresh of semiconductor memoryUS7020040 *Jul 8, 2003Mar 28, 2006Via Technologies Inc.Utilizing an ACPI to maintain data stored in a DRAMUS7088632 *May 26, 2004Aug 8, 2006Freescale Semiconductor, Inc.Automatic hidden refresh in a dram and method thereforUS7158434 *Apr 29, 2005Jan 2, 2007Infineon Technologies, AgSelf-refresh circuit with optimized power consumptionUS7184351 *Jun 17, 2005Feb 27, 2007Elpida Memory, Inc.Semiconductor memory deviceJPH05189961A Title not available* Cited by examinerNon-Patent CitationsReference1Patent Abstracts of Japan, vol. 17, No. 619 (P-1644) & JP 05 189961 A (Nov. 15, 1993).Classifications U.S. Classification365/222, 365/227, 365/228, 365/226, 365/229International ClassificationG06F1/26, H02M3/07, G06F1/32, G11C11/406, G11C5/14, G11C7/00Cooperative ClassificationY02B60/32, Y02B60/1225, G11C5/14, H02M3/07, G06F1/3275, G11C5/147, G06F1/3203, G11C2207/2227, G11C2211/4067, G11C11/406, G11C5/145, G11C14/00European ClassificationG06F1/32P5P8, G11C5/14P, G11C5/14R, H02M3/07, G06F1/32P, G11C5/14, G11C11/406, G11C14/00Legal EventsDateCodeEventDescriptionJun 27, 2012FPAYFee paymentYear of fee payment: 4Jul 22, 2010ASAssignmentEffective date: 20100401Owner name: FUJITSU SEMICONDUCTOR LIMITED, JAPANFree format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:024982/0245Dec 11, 2008ASAssignmentOwner name: FUJITSU MICROELECTRONICS LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021977/0219Effective date: 20081104Owner name: FUJITSU MICROELECTRONICS LIMITED,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100203;REEL/FRAME:21977/219Free format text: ASSIGNMENT OF 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