Source: http://www.google.com/patents/US6437767?dq=7222078
Timestamp: 2014-09-24 04:51:26
Document Index: 786341228

Matched Legal Cases: ['arts 33', 'arts 33', 'art 33', 'art 34', 'arts 33', 'Application No. 10', 'Application No. 98302556', 'Application No. 9706942']

Patent US6437767 - Active matrix devices - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn active matrix device includes a data line driver circuit for sampling the input signal to produce data signals for each of the rows of control elements in a corresponding line period, and a scan line driver circuit for addressing the scan lines sequentially by applying a scan signal to the scan inputs...http://www.google.com/patents/US6437767?utm_source=gb-gplus-sharePatent US6437767 - Active matrix devicesAdvanced Patent SearchPublication numberUS6437767 B1Publication typeGrantApplication numberUS 09/054,949Publication dateAug 20, 2002Filing dateApr 3, 1998Priority dateApr 4, 1997Fee statusPaidAlso published asEP0869471A1Publication number054949, 09054949, US 6437767 B1, US 6437767B1, US-B1-6437767, US6437767 B1, US6437767B1InventorsGraham Andrew Cairns, Michael James Brownlow, Andrew KayOriginal AssigneeSharp Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (15), Non-Patent Citations (9), Referenced by (25), Classifications (11), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetActive matrix devicesUS 6437767 B1Abstract An active matrix device includes a data line driver circuit for sampling the input signal to produce data signals for each of the rows of control elements in a corresponding line period, and a scan line driver circuit for addressing the scan lines sequentially by applying a scan signal to the scan inputs of the control elements along each of the rows so as to supply said data signals to the control elements along the row. Such circuits are controlled so that a data input signal is sampled and stored to produce data signals for a first group of the control elements along the row in a first line subperiod and the stored data signals are applied to the first group of control elements in a second line subperiod, and so that the data input signal is sampled and stored to produce data signals for a second group of control elements along the row in the second line subperiod and the stored data signals are applied to the second group of control elements in a subsequent line subperiod.
a plurality of data lines; a plurality of scan lines; an active matrix of control elements arranged in rows and disposed at intersections of the data lines and scan lines, the control elements having data inputs connected to the data lines and scan inputs connected to the scan lines such that each control element is addressable by a combination of data signals and a scan signal applied to a corresponding one of the data lines and a corresponding one of the scan lines; and an addressing element arranged so as to address the rows of control elements in successive line periods in response to an input signal, the addressing element including: a data line driver circuit arranged so as to sample the input signal to produce the data signals for each of the rows of control elements in a corresponding line period, the data line driver circuit being further arranged so as to apply said data signals to the data lines; and a scan line driver circuit arranged so as to address the scan lines sequentially by applying the scan signal to the scan inputs of the control elements along each of the rows so as to supply said data signals applied to the data lines to the control elements along said row on receipt of said scan signal by the control elements, wherein the data line driver circuit further includes: a first actuator arranged so as to sample and store the input signal to produce the data signals for a first group of the control elements along said row in a first subperiod of said one line period, the first actuator being further arranged so as to supply said data signals to the first group of control elements in a second subperiod of said one line period; and a second actuator arranged so as to sample and store the input signal to produce the data signals for a second group of control elements along said row in a subperiod which is at least partly coextensive with the second subperiod, the second actuator being further arranged so as to supply said data signals to the second group of control elements in a subsequent subperiod, and the data line driver circuit contains the same number of elements for sampling and storing the input signal in the data line driver circuit as there are control elements in a single row of the active matrix. 2. An active matrix device according to claim 1, wherein the second actuator is adapted to supply said data signals to the second group of control elements in a first subperiod of a further one of the line periods following said one line period.
TECHNICAL FIELD OF THE INVENTION This invention relates to active matrix devices and is concerned more particularly, but not exclusively, with driver circuits for active matrix liquid crystal displays (AMLCD's).
DESCRIPTION OF THE RELATED ART FIG. 1 shows a typical AMLCD 1 composed of N rows and M columns of pixels addressable by scan lines 2 connected to a scan line driver circuit 3 and data lines 4 connected to a data line driver circuit 5. Data voltages are applied to the data lines 4 by the data line driver circuit 5 and scan voltages are applied to the scan lines 2 by the scan line driver circuit 3 so that such voltages in combination serve to apply analogue data voltages to the pixel electrodes 6 in order to control the optical transmission states of the pixels along each row as the rows are scanned in a cyclically repeating sequence. This is achieved as follows for a single row of pixels. The data line driver circuit 5 reads a line of data to be displayed by the row of pixels and applies corresponding data voltages to the data lines 4 so as to charge up each data line 4 to the required data voltage. The scan line 2 corresponding to the row of pixels to be controlled is activated by the application of the scan voltage by the scan line driver circuit 3 so that a TFT 7 associated with each pixel is switched on to transfer charge from the corresponding data line 4 to a pixel storage capacitance 8 (as shown in broken lines in the figure) associated with the pixel. When the scan voltage is removed the TFT 7 isolates the pixel storage capacitance 8 from the data line 4 so that the optical transmission state of the pixel corresponds to the voltage across the pixel storage capacitance 8 until the pixel is refreshed during the next scanning frame. The rows of pixels are refreshed one at a time until all the rows have been refreshed to complete refreshing of a frame of display data. The process is then repeated for the next frame of data.
For analogue displays of small size or low pixel resolution, a point-at-a-time data line driver circuit 10 is commonly employed for the data line driver circuit, as shown in FIG. 2. In this circuit 10 a sampling shift register 11 composed of a chain of D-type flip-flops is connected so that the output of each flip-flop controls the gate of an associated sampling transistor 12 for applying the AVIDEO signal to the corresponding data line 4 with its associated parasitic capacitance shown in broken lines at 13 in the figure. The key feature of such a point-at-a-time driving scheme is that the sampling transistors 12 are directly connected to the data lines 4. In operation frame and line synchronisation pulses VSYNC (not shown) and HSYNC indicate the start of a frame period and a line period respectively, and a clock signal CK at the sampling frequency is applied to the clock inputs of the flip-flops so that a circulating �1� state within the shift register sequentially activates the sampling transistors 12 at the sampling frequency. The RC time constant formed by the resistance of the sampling transistor 12 and the data line 4 (which may have a resistance of several thousand Ohms). and the distributed capacitance of the data line (which may amount in total to tens of picofarads) must be sufficiently less than the available sampling period (1/fNM) for the sampling to be executed successfully.
In the case of digital displays, the data line driver circuits normally use a line-at-a-time driving scheme so that it is necessary to use line memories, usually based on latches. A typical digital data line driver circuit comprises an input register to which digital video data is supplied, for example in 6 or 8 bit RGB format, a storage register in the form of digital latches, and digital-to-analogue (D/A) converters connected to the outputs. of the storage register and supplied with reference voltages for applying data to up to 24 parallel digital data lines by way of output buffers. As the digital data bits are supplied to the input register, they are stored in the register and, when a whole line of data has been stored, the contents of the input register are transferred to the storage register in order to control the D/A converters. In the case of small screen displays, the D/A converters may be connected directly to the data lines so as to charge the data lines by simple charge sharing, although output buffers are required for higher performance displays. The D/A converters most commonly used are parallel converters (such as are referred to by Y. Matsueda, S. Inoue, S. Takenaka, T. Ozawa, S. Fujikawa, T. Nakazawa and H. Ohshima, �Low-temperature poly-Si TFT-LCD with integrated 6-bit digital data drivers�, Society for Information Display 96 Digest, pages 21-24) and ramp converters. However the digital line memory required for such a circuit is difficult to achieve with SOI digital driver integration.
It is known to use two scan line driver circuits to charge up the same scan line, as disclosed in C. Reita, �Integrated driver circuits for active matrix liquid crystal displays�, Displays 1993, Vol. 14(2), pages 104-114, and R. Martin, T. Chuang, H. Steemers, R. Fulks, S. Stuber, D. Lee, M. Young, J. Ho, M. Nguyen, W. Meuli, T. Fiske, R. Bruce, V. Da Costa, R. Kowalski, A. Lewis, W. Turner, M. Thompson, M. Tilton and L. Silverstein, �The electronic document display: A 6.3-million-pixel AMLCD�, Journal of the Society for Information Display 1996, Vol. 4(2), pages 65-73, for example. There are two advantages to such a driving scheme which are particularly relevant to circuits which are integrated on the same substrate as the display. The first advantage is that the circuit is rendered more tolerant to faults. The second advantage is that two scan line buffers can be used to charge up the significant capacitance of the scan line and connected TFT's more quickly and evenly. Furthermore it is known for the scan lines to be physically split down the centre of the display so that the display consists of two display parts which are scanned by separate scan line driver circuits connected to opposite edges of the display. Such an arrangement can be effected on a substrate which is common to the two display parts, or alternatively the display parts may be constituted by two display substrates which are bonded together edge to edge to make a larger area display. In both cases the scan lines of both display parts are controlled so that the same line is activated in the two parts at the same time.
SUMMARY OF THE INVENTION U.S. Pat. No. 4,830,466 discloses an AMLCD 32 in which the scan lines are split down the centre of the display into left and right hand scan line parts 33 and 34 as shown in FIG. 6. The scan line parts 33, 34 are activated in one line period of a point-at-a-time driving scheme, in which the left hand scan line part 33 is activated during the first half of the line period and the right hand scan line part 34 is activated during the second half of the line period. This allows more time for charging of the pixels by the data line driver circuit 37 towards the right hand side of the display as compared with a conventional point-at-a-time driving scheme as described above with reference to FIG. 3. It is to be noted that the two scan line parts 33 and 34 are scanned in a single scanning operation in which a line of data is read and applied to the data lines during application of the scan voltage, but in which the left and right hand scan lines are independently controlled.
BRIEF DESCRIPTION OF THE DRAWINGS In a further development of the invention the data lines corresponding to the first scan line are connected to first and second line drivers of the data line driver circuit means by first and second switching means, the data lines corresponding to the second scan line are connected to third and fourth line drivers of the data line driver circuit means by third and fourth switching means, and the data line driver circuit means is adapted to apply data signals to data lines of subgroups of the first and second groups of control elements while the input signal is being sampled for other subgroups of the first and second groups of control elements during each subperiod.
DETAILED DESCRIPTION OF THE INVENTION Preferred embodiments of the invention applied to an AMLCD will now be described with reference to FIGS. 7 to 18 of the drawings, although it should be understood that the invention is also applicable to other types of active matrix device. In each of the described embodiments the analogue or digital data line driver circuits operate with only a single line memory by utilising a part-line-at-a-time driving scheme in which the pixels along a row are addressed in two or more groups during the line period so that, during a first subperiod of the line period, the input data is sampled by the data line driver circuit to produce data signals for a first group of pixels along the row and, during a second subperiod of the line period, the data signals are applied to the first group of pixels whilst the data line driver circuit samples the input data to produce data signals for a second group of pixels along the row. Such part-line-at-a-time driving is achieved by a data line driver circuit composed of two or more banks which successively perform data sampling and data line driving at the line scanning frequency but out of phase with one another, for example by half a line period where the matrix is driven a half line at a time. It will be appreciated that, when a first bank of the data line driver circuit has completed sampling, its mode of operation changes to that of driving, and a second bank of the data line driver circuit effects sampling at the same time as the first bank effects driving.
By comparison with the line-at-a-time driving scheme which provides a single-line pipeline delay, the pipeline delay which is normally available for charging the data lines in the half-line-at-a-time driving scheme described above is reduced to half a line period, and this means that the line drivers must charge the data lines more quickly. For an XGA (extended graphics array) display of 1024�768 pixels operating at 70 Hz, the half line period is equal to 1/(2�70�768)=9.3 μs. If the loading effect is modelled using single R and C elements, then the values of these components for a 12.1 inch diagonal XGA display will be of the order of 10KΩ and 100pF respectively. Buffers constructed from low-mobility polysilicon transistors have been shown to be capable of charging such loads to potentials of �10 V well within 9.3 μs.
FIG. 12 shows a digital data line driver circuit 70 which can be used in either of the embodiments of the invention described above and which requires only a single storage register 71 in the form of digital latches, and line drivers 72 in the form of D/A converters and buffers connected to the outputs of the storage register 71 and supplied with reference voltages. Such a digital data line driver circuit 70 is described in more detail in British Patent Application No. (SLE 96055). It will be appreciated that such a data line driver circuit 70 requires less components than a conventional line-at-a-time data line driver circuit as described above since an additional input register is not required to store the RGB bits of input digital data. For an 8-bit colour XGA display, for example, adoption of such a driving scheme brings about a saving of 24�1024=24,576 one-bit latches. This is an important advantage since it improves both yield and power efficiency. The reduction in implementation area is even more important for monolithic drivers fabricated with low temperature polysilicon, for example, where the feature size of the transistors is quite large.
The scan line drivers for the above described embodiments must operate at different frequencies and/or must be phase shifted with respect to the line synchronisation pulse HSYNC. It is therefore necessary to generate SSYNC1 and SSYNC2 signals for both the switchable data line bank driving scheme of FIGS. 7 and 8 and the split scan line driving scheme of FIGS. 9 and 10, and a simple circuit arrangement for generating these signals will be described with reference to FIG. 13 which shows an enlarged centre portion of the sampling shift register 11 of a data line driver circuit 69 (which may correspond to the circuit 60 of FIG. 11, for example). The sampling shift register 11 is composed of a chain of D-type flip-flops 75, and the SSYNC1 signal is simply the output of the (M/2−1)th flip-flop since, when the circulating �1� reaches the centre of the shift register 74, a pulse having a falling edge coincident with the half line period is generated. Furthermore the line synchronisation pulse HSYNC is applied to one input of an OR gate 76 whilst the SSYNC1 signal is applied to the other input of the gate so as to generate the signal SSYNC2 at the output of the gate 76 which makes a rise and fall transition twice as frequently as the HSYNC pulse. In the switchable data line bank driving scheme of FIGS. 7 and 8, the signal SSYNC1 is supplied to the shift register of the scan line driver circuit, and the A and B switch signals can be generated from toggle flip-flops clocked with the signal SSYNC2. In the split scan line driving scheme of FIGS. 9 and 10, the signal SSYNC2 is supplied to the shift register or registers of the scan line driver circuit. Such a signalling technique is more practical for monolithic data and scan line driver circuits where it is relatively straightforward for signals to be transferred between the two types of driver circuit. The timing diagram at (b) in FIG. 13 shows the relative timing of the signals VSYNC, HSYNC, SSYNC1 and SSYNC2.
The scan line driver circuit for the switchable data line bank driving scheme is of generally standard construction except that a phase shift relative to the line synchronisation must be effected by use of the SSYNC1 signal. For the split scan line driving scheme, two options exist for the scan line driver circuit as will be described below. In a first option shown in FIG. 14, each of the left and right hand scan line driver circuits 53 and 54 comprises a shift register composed of a chain of D-type flip-flops 80 (although an alternative structure comprising latches and combinational logic may also be used) controlled by the frame synchronisation pulse VSYNC and the SSYNC2 signal which has two triggering pulses per line period. The output of every other flip-flop 80 in the shift register is connected to a scan line buffer 81 which can be formed from two appropriately scaled inverters, for example. Considering the left hand scan line driver circuit 53 first, it is initialised by the VSYNC pulse such that the contents of the shift register become �10000000 . . . � (reading the states of the flip-flops 80 from the top downwards). After two falling edges of the SSYNC2 signal (see FIG. 10), the contents of the shift register change to �00100000 . . . � and the scan voltage L1 goes high and remains high for one half of the line period. The scan voltage L2 does not go high until a full line period later when the contents of the shift register are changed to �00001000 . . . �. The right hand scan line driver circuit 54 operates in similar manner. However, for a given row of pixels, the right hand scan line buffer is connected to a flip-flop 80 one stage further down the shift register than the equivalent left hand scan line buffer. This ensures that the scan pulses are half a line period out of phase.
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