Source: https://www.iec.ch/dyn/www/f?p=103:20:33161594545360::::FSP_ORG_ID,FSP_LANG_ID:1372,25
Timestamp: 2019-10-15 11:26:27
Document Index: 731879296

Matched Legal Cases: ['art 8', 'art 1', 'art 1', 'art 2', 'in fine', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 3', 'art 3', 'art 3', 'art 3', 'art 4', 'art 4', 'art 4', 'art 4', 'art 4', 'art 5', 'art 5', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 6', 'art 1', 'art 1', 'art 1', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 2', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3']

IEC - SC 47D Dashboard > Projects / Publications: Work programme, Publications, Stability Dates, Project files
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Semiconductor devices packaging
SC 47D Project files (202)
Supplement to IEC 191-6 - Recommended values for dual-in-line packages of Form E
Supplement to IEC 191-6 - Recommended values for QFPs of form E
The individual standard for 48 pins plastic fine pitch ball grid array (P-FBGA), 0,75 & 0,65 mm terminal pitch (Intended for inclusion into IEC 191-2)
BGA (Ball Grid Array) package measuring method
Proposed new package outline, 3/4-land SMD
Proposed new package outline, DDRII SDRAM Family, 1,00 mm contact pitch
Proposed new package outline, Plastic, small outline family, 1,27 mm pitch, 7,5 mm body width and 14, 16, 18, 20, 24 and 28 lead counts
Proposed new package outline, Plastic small outline family, 1,27 mm pitch, 3,9 mm body width, 8, 14 and 16 leads
Proposed new package outline, Plastic small outline family, 25 mil pitch, 150 mil body width, 14, 16, 18, 20, 24 and 28 leads
Design guide for semiconductor packages - Ball Grid Array Package (BGA)
Proposed new package outline - 13 Pin reduced size MultiMediaCard (MMC) outline MMCmobile 18 x 24 x 1,4 mm
Proposed new package outline - 10 pin micro size Multimedia Card (MMC) outline MMCmicro 14 x 12 x 1,1 mm (Intended to become IEC 60191-2/F66, if approved)
Proposed new package outline - 13 Pin full size Multimedia Card (MMC) Outline MMCplus 32 x 24 x 1,4 mm (Intended to become IEC 60191-2/F67, if approved)
Standardization of semiconductor mechanical test methodology - Package warpage test sample preparation method by using BGA solder ball removal tool
Future IEC 60191-7 Ed.1: Package thermal characteristics guideline in semiconductor products
Future IEC 60191-8: Mechanical standardization of semiconductor devices – Part 8: Requirements to Semiconductor Devices Packaging Materials from the Environment point of View - Low Cl and Br Molding Compound
Future IEC 60191-X Ed.1: Requirement to semiconductor devices packaging materials from the environment point of view: Low Halogen Molding Compound
Mechanical standardization of semiconductor devices - Part 1: General rules for the preparation of outline drawings of discrete devices
Mechanical standardization of semiconductor devices. Part 1: Preparation of drawings of semiconductor devices
Restructuring of package outlines presently contained in IEC 191-2
Tape ball grid array package, 0,6 mm ball diameter family (intended for inclusion into IEC 60191-2)
48 pins P-FBGA (Plastic Fine pitch Ball Grid Array), 0.75 and 0.65 mm pitch , face down (intended for inclusion into IEC 191-2)
32 and 48 pins P-FBGA (Plastic Fine pitch Ball Grid Array), 0,8 mm pitch (Intended for inclusion into IEC 191-2)
Mechanical standardization of semiconductor devices. Part 2: Dimensions
Power semiconductor outline Form B, Types A and B, for inclusion into IEC 191-2
Inclusion of an additional drawing of integrated circuit in the family drawing A50 of IEC 191-2
General rules for HSOP (Heat sink small outline package) - Supplement to IEC 191-2
Tape ball grid array (TBGA) family (Intended for inclusion into 60191-2)
Drawing family of rectangular plastic leaded chip carrier (PLCCs) packages - Introduction of the outline family 124E in IEC 191-2
Mechanical standardization power devices. Proposal for tablet case outline drawings for two families to be introduced in IEC 191-2 for future use
Ceramic quadrature flat packages, square type, for surface mounting - Introduction of the outline families 130E and 131E in IEC 191-2
Recommended values for QFP, 0.30, 0.40, 0.50, 0.65, 0.80 and 1.00 mm lead spacing, for inclusion into IEC 191-2
Inclusion of a heat sink small outline (HSOP) family, similar to SOP family 075E contained in IEC 191-2
Plastic small outline family, J-Lead (P-SOJ), 10,16 mm body family (to be published as outline 141E-d)
Plastic thin small outline package P-TSOP II, 7,62 mm body family
P-TSOP II, 10,16 mm body family (if approved, to be included in outline 139 E)
HSOP reverse bend, heatslug up
Plastic thin small outline package J-Lead (P-TSOJ), 7,62 mm body family - (Supplement to IEC 191-2)
Proposal for a tape ball grid array, 0.75 mm ball diameter family (intended for inclusion into IEC 60191-2) as outline 146E
Ceramic thin LGA, 1,0 mm pitch outline family
4-leaded SMD (Body size DxE:2.00x1.25 mm) (for inclusion into IEC 191-2)
Surface Vertical Packages (SVP) - Outline family 155E
P-VSON (Plastic very small outline - Non-leaded packages) (will be published as Outline 164E-a)
Proposal for 0,8 mm pitch P-FBGA (plastic fine pitch ball grid array)
Proposal for a supplement of the rectangular type of QFN outline drawings to the outline family of 119E
Ceramic thin LGA, 0,8 mm pitch outline family
New package outline - Thin fine pitch ball grid array family (rectangular/square)
Small Outline J-Lead Package (SOJ), 0.80 mm Pitch (Outline 163E)
Proposal for 3-Leaded SMD (Body Size D x E : 2.9 x 1.5 mm) Outline Family 162E
Plastic enhanced, low profile quad flat pack (HLQFP) outline family, heat slug down, L-PQFP-G (Outline 151E-a)
Plastic enhanced, thin profile quad flat pack (HTQFP) outline family, heat slug up, T-PQFP-G (Outline 152E)
Plastic enhanced, thin profile quad flat pack (HTQFP) outline family, heat slug down, T-PQFP-G (Outline 153E)
Small Power Package with 17 Pins (published as Outline 168E)
Proposed new package outline for P-DHVQFN family. (Plastic Dual in-line compatible Heatsink Very thin Quad Flat Pack No Leads)
Amendment 17 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Proposed new package outline - Small outline package (SOT) 3-, 5- and 6-Lead SMD (to be published as 182E outline)
Proposed new package outline - large power package with 6 load terminals, P-UMP-A6. To be published as outline 185B, if approved.
Proposed new package outline - flange mounted package with through hole leads, P-SFM-T3 - To be published as outline 186F. if approved.
Proposed new package outline - flange mount package with flat leads, P-SFM-F8 - To be published as outline 187E, if approved.
Proposed new package outline - P-ZMP-P89
Proposed new package outline - P-UMP-Ax
EN 2020-03 N 47D/899/CDV
Amendment 1 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Inclusion of three drawings for power modules - Supplement to IEC 191-2
Additional outline drawing of power semiconductor device, to be included in IEC 191-2
Integrated circuits - Drawing family of leaded packages of Form E (Quad Flat packages), to be included in IEC 191-2
Amendment to Document 47(C.O.)1148: Inclusion of the outline drawings 121E and 122E in IEC 191-2
Surface mounted cylindrical diodes - Introduction of the outline family 100H in IEC 191-2
Surface mounted packages - Introduction of the outline family 129E in IEC 191-2
Dual in line packages for 0.07 inches pitch (1.778 mm) - Introduction of the outline family 101G in IEC 191-2
Amendment to IEC 191-2 - Single-ended package outline of Form A
Amendment 2 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Standard outlines for non-cylindrical surface-mount semiconductors, to be added to IEC 191-2
Inclusion in IEC 191-2 of a wire-ended diode package (small signal diode)
Flange-mounted header family (peripheral terminals) - 0.100 spacing for inclusion in IEC 191-2
Amendment 3 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 4 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 5 - Mechanical standardization of semiconductor devices. Part 2: Dimensions
Amendment 6 - Mechanical standardization of semiconductor devices. Part 2: Dimensions
Amendment 7 - Mechanical standardization of semiconductor devices. Part 2: Dimensions
Amendment 8 - Mechanical standardization of semiconductor devices. Part 2: Dimensions
Amendment 9 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 10 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 11 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 12 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 13 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 14 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 15 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 16 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 18 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 19 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Amendment 20 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits
Mold flash, interlead flash, gate burrs, and protrusion for plastic packages
Definition of mold flash, interlead flash, gate burrs and protrusions for plastic packages, to be introduced into IEC 191-2
Standardization of Pin #1 mark for identification in automatic handling systems
Definition of pin No. 1 orientation for TAB packages (intended for inclusion into IEC 191-3)
Mechanical standardization of semiconductor devices. Part 3: General rules for the preparation of outline drawings of integrated circuits
Amendment 1 - Mechanical standardization of semiconductor devices. Part 3: General rules for the preparation of outline drawings of integrated circuits
Amendment 2 - Mechanical standardization of semiconductor devices. Part 3: General rules for the preparation of outline drawings of integrated circuits
Amendment to Sub-clause 4.5 of IEC 191-3 - Devices with terminals disposed in three or more rows in each orthogonal direction
Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor device packages
Amendment 1 - Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor device packages
Proposed replacement of IEC 191-4: Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor devices
Amendment to IEC 191-4 to add a package style and a descriptive designator for high power semiconductor packages (100 ... 1700 V/10 ... 1000 A)
Definition and value of L, T
Amendment 2 - Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor device packages
Mechanical standardization of semiconductor devices. Part 4: Coding systems and classification into forms of package outlines for semiconductor devices
Mechanical standardization of semiconductor devices - Part 5: Recommendations applying to integrated circuit packages using tape automated bonding (TAB)
Mechanical standardization of semiconductor devices. Part 5: Recommendations applying to tape automated bonding (TAB) of integrated circuits.
Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
Mechanical standardization of semiconductor devices. Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
Amendment 1 - Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
Inclusion of an SVP outline family into IEC 191-6
O value of leaded packages with two parallel rows of terminals in IEC 191-6, Appendix B1
IEC 191-6 - General rules for TSOP (Thin small outline package) Type II
Amendment to IEC 60191-6 - Renaming 'terminal land area' to 'terminal position area'
IEC 60191-6-1 Ed.2: Part 6-1: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for gull-wing lead terminals
Mechanical standardization of semiconductor devices - Part 6-1: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for gull-wing lead terminals
Mechanical standardization of semiconductor devices - Part 6-2: General rules for the preparation of outline drawings of surface mounted semiconductor devices packages - Design guide for 1,50 mm, 1,27 mm and 1,00 mm pitch ball and column terminal packages
Corrigendum 1 - Mechanical standardization of semiconductor devices - Part 6-2: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for 1,50 mm, 1,27 mm and 1,00 mm pitch ball and column terminal packages
Mechanical standardization of semiconductor devices - Part 6-3: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of quad flat packs (QFP)
Mechanical standardization of semiconductor devices - Part 6-4: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of ball grid array (BGA)
Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)
Mechanical standardization of semiconductor devices - Part 6-6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine pitch land grid array (FLGA)
Mechanical standardization of semiconductor devices - part 6-7: General rules for the dimensions of P-VQFN
Mechanical standardization of semiconductor devices - Part 6-8: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for glass sealed ceramic quad flatpack (G-QFP)
Mechanical standardization of semiconductor devices - Part 6-9: General rules for the preparation of outline drawing of surface mounted semiconductor device packages - Design guideline of integrated circuits for Plastic Quad Flat Package (P-QFP)
Mechanical standardization of semiconductor devices - Part 6-10: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Dimensions of P-VSON
Mechanical standardization of semiconductor devices - Part 6-11: General design guidelines for rectangular Fine Pitch Ball Grid Array Packages (FBGA)
Mechanical standardization of semiconductor devices - Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guidelines for fine-pitch land grid array (FLGA)
Mechanical standardization of semiconductor devices - Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch land grid array (FLGA) - Rectangular type
Mechanical standardization of semiconductor devices - Part 6-13: Design guideline of open-top-type sockets for Fine-pitch Ball Grid Array (FBGA) and Fine-pitch Land Grid Array (FLGA)
Mechanical standardization of semiconductor devices - Part 6-13: Design guideline of open-top-type sockets for Fine-pitch Ball Grid Array and Fine-pitch Land Grid Array (FBGA/FLGA)
Mechanical standardization of semiconductor devices - Part 6-14: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ)
Mechanical standardization of semiconductor devices - Part 6-15: General rules for the preparation of outline drawings of surface mounted semiconductor device packages- Measuring methods for package dimensions of small outline packages (SOP)
Semiconductor Packaging - Part 6-16: Glossary of semiconductor tests and burn-in sockets for BGA, LGA, FBGA and FLGA
Mechanical standardization of semiconductor devices - Part 6-16: Glossary of semiconductor tests and burn-in sockets for BGA, LGA, FBGA and FLGA
Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)
Mechanical standardization of semiconductor devices - Part 6-18: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for ball grid array (BGA)
Corrigendum 1 - Mechanical stardardization of semiconductor devices - Part 6-18: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for ball grid array (BGA)
Corrigendum 2 - Mechanical standardization of semiconductor devices - Part 6-18: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for ball grid array (BGA)
Mechanical standardization of semiconductor devices - Part 6-19: Measurement methods of the package warpage at elevated temperature and the maximum permissible warpage
Mechanical standardization of semiconductor devices - Part 6-19: Measurement methods of package warpage at elevated temperature and the maximum permissible warpage
Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ)
Mechanical standardization of semiconductor devices - Part 6-21: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline packages (SOP)
Mechanical standardization of semiconductor devices - Part 6-22: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for semiconductor packages Silicon Fine-pitch Ball Grid Array and Silicon Fine-pitch Land Grid Array (S-FBGA and S-FLGA)
Mechanical standardization of semiconductor devices - Part 1: Preparation of drawings of semiconductor devices - First supplement
Mechanical standardization of semiconductor devices - Part 1: Preparation of drawings of semiconductor devices - Second supplement
Mechanical standardization of semiconductor devices - Part 1: Preparation of drawings of semiconductor devices - Third supplement
First supplement to Publication 191-2 (1966) Mechanical standardization of semiconductor devices - Part 2: Dimensions Part 2: Dimensions
Second supplement - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Third supplement
Fourth supplement
Fifth supplement
Sixth supplement
Seventh supplement
Eigth supplement
Ninth supplement - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Tenth supplement - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Eleventh supplement
Twelfth supplement
Thirteenth supplement - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Fourteenth supplement
fifteenth complement
Sixteenth supplement
Seventeenth supplement
Eighteenth supplement
Nineteenth supplement
Twentieth supplement
Twenty-first supplement
Proposal for a plastic thin shrink small outline package (TSSOP/HTSSOP), 1,00 mm lead length outline family, R-PDSO-G
Mechanical standardization of semiconductor devices - Part 2: Dimensions
Corrigendum 1 - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Twenty-third supplement - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Addition to the metric plastic quad flatpack family; 1.0 mm, 0,80 mm and 0,65 mm
Twenty-fourth supplement - Mechanical standardization of semiconductor devices - Part 2: Dimensions
Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - First supplement
Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - Second supplement
Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - Third supplement
Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - Fourth supplement
Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - Fifth supplement
Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - Sixth supplement
Dimensional check of surface mounted devices