Source: http://www.google.com/patents/US7898041?dq=5,832,511
Timestamp: 2015-03-01 11:19:10
Document Index: 663735150

Matched Legal Cases: ['Application No. 06815547', 'Application No. 11', 'Application No. 094136197', 'Application No. 10', 'Application No. 05711376', 'Application No. 112006001735', 'Application No. 95134963', 'Application No. 200680023301', 'Application No. 03817699', 'Application No. 200580007279', 'Application No. 95122087', 'Application No. 95122087', 'Application No. 95123858', 'Application No. 95123858', 'Application No. 95135820', 'Application No. 95135820', 'Application No. 95135820', 'Application No. 11', 'Application No. 200580032314', 'Application No. 2005070131', 'Application No. 200604766']

Patent US7898041 - Block contact architectures for nanoscale channel transistors - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic...http://www.google.com/patents/US7898041?utm_source=gb-gplus-sharePatent US7898041 - Block contact architectures for nanoscale channel transistorsAdvanced Patent SearchPublication numberUS7898041 B2Publication typeGrantApplication numberUS 11/855,823Publication dateMar 1, 2011Filing dateSep 14, 2007Priority dateJun 30, 2005Fee statusPaidAlso published asCN101208805A, CN101208805B, DE112006001735B4, DE112006001735T5, US7279375, US20070001219, US20080258207, WO2007005697A2, WO2007005697A3Publication number11855823, 855823, US 7898041 B2, US 7898041B2, US-B2-7898041, US7898041 B2, US7898041B2InventorsMarko Radosavljevic, Amlan Majumdar, Brian S. Doyle, Jack Kavalieros, Mark L. Doczy, Justin K. Brask, Uday Shah, Suman Datta, Robert S. ChauOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (162), Non-Patent Citations (119), Referenced by (40), Classifications (17), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetBlock contact architectures for nanoscale channel transistors
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4231149Oct 10, 1978Nov 4, 1980Texas Instruments IncorporatedNarrow band-gap semiconductor CCD imaging device and method of fabricationUS4487652Mar 30, 1984Dec 11, 1984Motorola, Inc.Semiconductor with insulating layerUS4711701Sep 16, 1986Dec 8, 1987Texas Instruments IncorporatedSelf-aligned transistor methodUS4818715Jul 9, 1987Apr 4, 1989Industrial Technology Research InstituteMethod of fabricating a LDDFET with self-aligned silicideUS4905063Jun 21, 1988Feb 27, 1990American Telephone And Telegraph Company, At&T Bell LaboratoriesFloating gate memoriesUS4906589Feb 6, 1989Mar 6, 1990Industrial Technology Research InstituteInverse-T LDDFET with self-aligned silicideUS4907048Nov 23, 1987Mar 6, 1990Xerox CorporationDouble implanted LDD transistor self-aligned with gateUS4994873Dec 26, 1989Feb 19, 1991Motorola, Inc.Local interconnect for stacked polysilicon deviceUS4996574Jun 30, 1989Feb 26, 1991Fujitsu LimitedMIS transistor structure for increasing conductance between source and drain regionsUS5023203Jun 23, 1989Jun 11, 1991Korea Electronics & Telecommunications Research Institute Et Al.Multilayer mask including intermediate spacerUS5120666May 2, 1990Jun 9, 1992Fujitsu LimitedManufacturing method for semiconductor deviceUS5124777Jan 3, 1991Jun 23, 1992Samsung Electronics Co., Ltd.Of strontium, barium, lanthanum and niobium oxides, crystal structureUS5179037Dec 24, 1991Jan 12, 1993Texas Instruments IncorporatedIntegration of lateral and vertical quantum well transistors in the same epitaxial stackUS5216271Sep 27, 1991Jun 1, 1993Kabushiki Kaisha ToshibaBiCMOS device with low bandgap CMOS contact regions and low bandgap bipolar base regionUS5278102Feb 12, 1993Jan 11, 1994Fujitsu LimitedSOI device and a fabrication process thereofUS5308999Feb 24, 1993May 3, 1994Fujitsu LimitedMOS FET having a thin film SOI structureUS5328810 *Nov 25, 1992Jul 12, 1994Micron Technology, Inc.Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic processUS5338959Mar 30, 1993Aug 16, 1994Samsung Electronics Co., Ltd.Thin film transistor with three dimensional multichannel structureUS5346836Aug 17, 1993Sep 13, 1994Micron Technology, Inc.Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnectsUS5346839Jan 8, 1993Sep 13, 1994Texas Instruments IncorporatedSidewall doping technique for SOI transistorsUS5357119Feb 19, 1993Oct 18, 1994Board Of Regents Of The University Of CaliforniaField effect devices having short period superlattice structures using Si and GeUS5391506 *Jan 27, 1993Feb 21, 1995Kawasaki Steel CorporationManufacturing method for semiconductor devices with source/drain formed in substrate projection.US5466621Oct 25, 1993Nov 14, 1995Hitachi, Ltd.Method of manufacturing a semiconductor device having silicon islandsUS5475869May 27, 1994Dec 12, 1995Nec CorporationRadio base station capable of distinguishing between interference due to collisions of outgoing call signals and an external interference noiseUS5479033May 27, 1994Dec 26, 1995Sandia CorporationComplementary junction heterostructure field-effect transistorUS5482877Feb 16, 1994Jan 9, 1996Samsung Electronics Co., Ltd.Method for making a semiconductor device having a silicon-on-insulator structureUS5514885Jan 13, 1995May 7, 1996Myrick; James J.Charge coupled deviceUS5521859Jan 17, 1995May 28, 1996Fujitsu LimitedSemiconductor memory device having thin film transistor and method of producing the sameUS5543351Oct 31, 1994Aug 6, 1996Matsushita Electric Industrial Co., Ltd.Method of producing electrically insulated silicon structureUS5545586May 13, 1994Aug 13, 1996Nec CorporationMethod of making a transistor having easily controllable impurity profileUS5563077Jun 20, 1995Oct 8, 1996Hyundai Electronics Industries Co., Ltd.Method of fabricating a thin film transistor having vertical channelUS5576227Nov 2, 1994Nov 19, 1996United Microelectronics Corp.Process for fabricating a recessed gate MOS deviceUS5578513Apr 20, 1995Nov 26, 1996Mitsubishi Denki Kabushiki KaishaMethod of making a semiconductor device having a gate all around type of thin film transistorUS5595919Feb 20, 1996Jan 21, 1997Chartered Semiconductor Manufacturing Pte Ltd.Method of making self-aligned halo process for reducing junction capacitanceUS5595941 *Feb 27, 1995Jan 21, 1997Mitsubishi Denki Kabushiki KaishaSemiconductorsUS5652454Jul 3, 1996Jul 29, 1997Iwamatsu; ToshiakiSemiconductor device on an SOI substrateUS5658806Oct 26, 1995Aug 19, 1997National Science CouncilMethod for fabricating thin-film transistor with bottom-gate or dual-gate configurationUS5665203Apr 28, 1995Sep 9, 1997International Business Machines CorporationSilicon etching methodUS5682048May 17, 1996Oct 28, 1997Nissan Motor Co., Ltd.Groove-type semiconductor deviceUS5698869Sep 13, 1995Dec 16, 1997Kabushiki Kaisha ToshibaInsulated-gate transistor having narrow-bandgap-sourceUS5701016Nov 24, 1995Dec 23, 1997Kabushiki Kaisha ToshibaSemiconductor device and method for its manufactureUS5716879Jan 13, 1997Feb 10, 1998Goldstar Electron Company, Ltd.Method of making a thin film transistorUS5739544Dec 12, 1995Apr 14, 1998Matsushita Electric Industrial Co., Ltd.Quantization functional device utilizing a resonance tunneling effect and method for producing the sameUS5760442Sep 29, 1995Jun 2, 1998Kabushiki Kaisha ToshibaSemiconductor device of a silicon on insulator metal-insulator type with a concave featureUS5770513May 2, 1995Jun 23, 1998Mitsubishi Denki Kabushiki KaishaMethod for producing semiconductor device with heat dissipation structureUS5773331Dec 17, 1996Jun 30, 1998International Business Machines CorporationMethod for making single and double gate field effect transistors with sidewall source-drain contactsUS5776821Aug 22, 1997Jul 7, 1998Vlsi Technology, Inc.Pre-gate side-walls exposed; removing oxide layer to reduce width while retaining a maskUS5793088Jun 18, 1996Aug 11, 1998Integrated Device Technology, Inc.Structure for controlling threshold voltage of MOSFETUS5804848Oct 31, 1997Sep 8, 1998Sony CorporationField effect transistor having multiple gate electrodes surrounding the channel regionUS5811324Feb 28, 1997Sep 22, 1998Lg Semicon Co., Ltd.Method for manufacturing thin film transistorUS5814895Dec 19, 1996Sep 29, 1998Sony CorporationStatic random access memory having transistor elements formed on side walls of a trench in a semiconductor substrateUS5821629Jul 12, 1995Oct 13, 1998United Microelectronics CorporationField isolation between active regions is not field oxide but doped silicon substrate; ultra-high density static random access memory cellUS5827769Nov 20, 1996Oct 27, 1998Intel CorporationMethod for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrodeUS5844278Sep 13, 1995Dec 1, 1998Kabushiki Kaisha ToshibaSemiconductor device having a projecting element regionUS5856225Nov 24, 1997Jan 5, 1999Chartered Semiconductor Manufacturing LtdCreation of a self-aligned, ion implanted channel region, after source and drain formationUS5859456 *Sep 9, 1996Jan 12, 1999Texas Instruments IncorporatedProgrammable integrated circuits utilizing lateral double diffused metal oxide semiconductor technologyUS5880015Oct 14, 1994Mar 9, 1999Sgs-Thomson Microelectronics, Inc.Method of producing stepped wall interconnects and gatesUS5888309Dec 29, 1997Mar 30, 1999Taiwan Semiconductor Manufacturing Company, Ltd.Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasmaUS5889304Jun 27, 1997Mar 30, 1999Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS5899710Feb 25, 1998May 4, 1999Sony CorporationMethod for forming field effect transistor having multiple gate electrodes surrounding the channel regionUS5905285Feb 26, 1998May 18, 1999Advanced Micro Devices, Inc.Ultra short trench transistors and process for making sameUS5908313Dec 31, 1996Jun 1, 1999Intel CorporationMethod of forming a transistorUS5952701Aug 18, 1997Sep 14, 1999National Semiconductor CorporationDesign and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor valueUS5965914Dec 23, 1997Oct 12, 1999Mitsubishi Denki Kabushiki KaishaThin film transistor having a branched gate and channelUS5976767Oct 9, 1997Nov 2, 1999Micron Technology, Inc.Ammonium hydroxide etch of photoresist masked siliconUS5985726Nov 6, 1998Nov 16, 1999Advanced Micro Devices, Inc.Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFETUS6013926Apr 18, 1997Jan 11, 2000Mitsubishi Denki Kabushiki KaishaSemiconductor device with refractory metal elementUS6018176Sep 8, 1997Jan 25, 2000Samsung Electronics Co., Ltd.Vertical transistor and memory cellUS6031249Jul 8, 1997Feb 29, 2000Semiconductor Energy Laboratory Co., Ltd.CMOS semiconductor device having boron doped channelUS6051452Jan 6, 1998Apr 18, 2000Kabushiki Kaisha ToshibaMethod for manufacturing a semiconductor device with ion implantationUS6054355Jun 29, 1998Apr 25, 2000Kabushiki Kaisha ToshibaMethod of manufacturing a semiconductor device which includes forming a dummy gateUS6063675Oct 24, 1997May 16, 2000Texas Instruments IncorporatedMethod of forming a MOSFET using a disposable gate with a sidewall dielectricUS6063677Oct 24, 1997May 16, 2000Texas Instruments IncorporatedMethod of forming a MOSFET using a disposable gate and raised source and drainUS6066869Oct 6, 1997May 23, 2000Micron Technology, Inc.Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitorUS6087208Mar 31, 1998Jul 11, 2000Advanced Micro Devices, Inc.Method for increasing gate capacitance by using both high and low dielectric gate materialUS6093621Apr 5, 1999Jul 25, 2000Vanguard International Semiconductor Corp.Method of forming shallow trench isolationUS6114201Jun 1, 1998Sep 5, 2000Texas Instruments-Acer IncorporatedMethod of manufacturing a multiple fin-shaped capacitor for high density DRAMsUS6114206Nov 6, 1998Sep 5, 2000Advanced Micro Devices, Inc.Multiple threshold voltage transistor implemented by a damascene processUS6117741Jan 5, 1999Sep 12, 2000Texas Instruments IncorporatedMethod of forming a transistor having an improved sidewall gate structureUS6120846Dec 23, 1997Sep 19, 2000Advanced Technology Materials, Inc.Simultaneously exposing insulating portion and electrically conductive portion of substrate to chemical vapor deposition process; during procedure selectively depositing bismuth based ferroelectric thin film on electrically conductive portionUS6144072Jan 15, 1999Nov 7, 2000Mitsubishi Denki Kabushiki KaishaSemiconductor device formed on insulating layer and method of manufacturing the sameUS6150222Jan 7, 1999Nov 21, 2000Advanced Micro Devices, Inc.Method of making a high performance transistor with elevated spacer formation and self-aligned channel regionsUS6153485Nov 9, 1998Nov 28, 2000Chartered Semiconductor Manufacturing Ltd.Forming transistorsUS6163053Nov 5, 1997Dec 19, 2000Ricoh Company, Ltd.Semiconductor device having opposite-polarity region under channelUS6165880Jun 15, 1998Dec 26, 2000Taiwan Semiconductor Manufacturing CompanyDouble spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuitsUS6174820Feb 16, 1999Jan 16, 2001Sandia CorporationUse of silicon oxynitride as a sacrificial material for microelectromechanical devicesUS6190975Dec 9, 1998Feb 20, 2001Matsushita Electric Industrial Co., Ltd.Method of forming HCMOS devices with a silicon-germanium-carbon compound semiconductor layerUS6200865Dec 4, 1998Mar 13, 2001Advanced Micro Devices, Inc.Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gateUS6218309Sep 30, 1999Apr 17, 2001Lam Research CorporationMethod of achieving top rounding and uniform etch depths while etching shallow trench isolation featuresUS6251729Dec 15, 1999Jun 26, 2001U.S. Philips CorporationMethod of manufacturing a nonvolatile memoryUS6251763Jun 29, 1998Jun 26, 2001Kabushiki Kaisha ToshibaSemiconductor device and method for manufacturing sameUS6252284Dec 9, 1999Jun 26, 2001International Business Machines CorporationPlanarized silicon fin deviceUS6259135Sep 24, 1999Jul 10, 2001International Business Machines CorporationMOS transistors structure for reducing the size of pitch limited circuitsUS6261921Sep 14, 1999Jul 17, 2001Taiwan Semiconductor Manufacturing Co., Ltd.Method of forming shallow trench isolation structureUS6262456Nov 6, 1998Jul 17, 2001Advanced Micro Devices, Inc.Integrated circuit having transistors with different threshold voltagesUS6274503Feb 1, 1999Aug 14, 2001United Microelectronics Corp.Etching method for doped polysilicon layerUS6287924Sep 28, 1999Sep 11, 2001Texas Instruments IncorporatedIntegrated circuit and methodUS6294416May 7, 1999Sep 25, 2001Texas Instruments-Acer IncorporatedMethod of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask countsUS6307235Mar 30, 1998Oct 23, 2001Micron Technology, Inc.Another technique for gated lateral bipolar transistorsUS6310367Feb 22, 2000Oct 30, 2001Kabushiki Kaisha ToshibaMOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layerUS6319807Feb 7, 2000Nov 20, 2001United Microelectronics Corp.Method for forming a semiconductor device by using reverse-offset spacer processUS6335251Apr 3, 2001Jan 1, 2002Kabushiki Kaisha ToshibaSemiconductor apparatus having elevated source and drain structure and manufacturing method thereforUS6358800Sep 18, 2000Mar 19, 2002Vanguard International Semiconductor CorporationMethod of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limitUS6413802 *Oct 23, 2000Jul 2, 2002The Regents Of The University Of CaliforniaFinfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufactureUS6716686 *Jul 8, 2003Apr 6, 2004Advanced Micro Devices, Inc.Method for forming channels in a finfet deviceUS6909151 *Jun 27, 2003Jun 21, 2005Intel CorporationNonplanar device with stress incorporation layer and method of fabricationUS6955961 *May 27, 2004Oct 18, 2005Macronix International Co., Ltd.Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolutionUS7013447 *Jul 22, 2003Mar 14, 2006Freescale Semiconductor, Inc.Method for converting a planar transistor design to a vertical double gate transistor designUS7060539 *Mar 1, 2004Jun 13, 2006International Business Machines CorporationMethod of manufacture of FinFET devices with T-shaped fins and devices manufactured therebyUS7105390 *Dec 30, 2003Sep 12, 2006Intel CorporationNonplanar transistors with metal gate electrodesUS7105894 *Feb 27, 2003Sep 12, 2006Taiwan Semiconductor Manufacturing Co., Ltd.Contacts to semiconductor fin devicesUS7105934 *Aug 30, 2004Sep 12, 2006International Business Machines CorporationFinFET with low gate capacitance and low extrinsic resistanceUS7163898 *Jul 30, 2003Jan 16, 2007Stmicroelectronics S.R.L.Method for manufacturing semiconductor integrated circuit structuresUS7214991 *Dec 6, 2002May 8, 2007Taiwan Semiconductor Manufacturing Co., Ltd.CMOS inverters configured using multiple-gate transistorsUS7339241 *Aug 31, 2005Mar 4, 2008Freescale Semiconductor, Inc.FinFET structure with contactsUS7348642 *Aug 3, 2005Mar 25, 2008International Business Machines CorporationFin-type field effect transistorUS7452778 *Apr 12, 2005Nov 18, 2008Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor nano-wire devices and methods of fabricationUS7456471 *Sep 15, 2006Nov 25, 2008International Business Machines CorporationField effect transistor with raised source/drain fin strapsUS7456476 *Jun 27, 2003Nov 25, 2008Intel CorporationNonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabricationUS7479421 *Sep 28, 2005Jan 20, 2009Intel CorporationProcess for integrating planar and non-planar CMOS transistors on a bulk substrate and article made therebyUS7585734 *Mar 5, 2008Sep 8, 2009Samsung Electronics Co., Ltd.Method of fabricating multi-gate transistor and multi-gate transistor fabricated therebyUS7612416 *Sep 29, 2004Nov 3, 2009Nec CorporationSemiconductor device having a conductive portion below an interlayer insulating film and method for producing the sameUS7655989 *Nov 30, 2006Feb 2, 2010International Business Machines CorporationTriple gate and double gate finFETs with different vertical dimension finsUS7701018 *Mar 22, 2005Apr 20, 2010Nec CorporationSemiconductor device and method for manufacturing sameUS20020011612 *Jul 30, 2001Jan 31, 2002Kabushiki Kaisha ToshibaSemiconductor device and method for manufacturing the sameUS20030203636 *Apr 29, 2002Oct 30, 2003Anthony Thomas C.Method of fabricating high density sub-lithographic features on a substrateUS20040036127 *Feb 14, 2003Feb 26, 2004Chau Robert S.Tri-gate devices and methods of fabricationUS20040108523 *Dec 6, 2002Jun 10, 2004Hao-Yu ChenMultiple-gate transistor structure and method for fabricatingUS20040113181 *Dec 13, 2002Jun 17, 2004Wicker Guy C.Lateral phase change memory and method thereforUS20040169269 *Feb 27, 2003Sep 2, 2004Yee-Chia YeoContacts to semiconductor fin devicesUS20040238887 *Jun 25, 2002Dec 2, 2004Fumiyuki NiheyField-effect transistor constituting channel by carbon nano tubesUS20050127362 *Dec 10, 2003Jun 16, 2005Ying ZhangSectional field effect devices and method of fabricationUS20050133829 *Nov 24, 2004Jun 23, 2005Mitsubishi Denki Kabushiki KaishaHigh-frequency semiconductor deviceUS20050162928 *Dec 21, 2004Jul 28, 2005Maarten RosmeulenNon-volatile multibit memory cell and method of manufacturing thereofUS20050202604 *Mar 23, 2005Sep 15, 2005Zhiyuan ChengIntegrated semiconductor device and method to make sameUS20060014338 *Jun 30, 2004Jan 19, 2006International Business Machines CorporationMethod and structure for strained finfet devicesUS20060043500 *Aug 24, 2004Mar 2, 2006Jian ChenTransistor structure with stress modification and capacitive reduction feature in a channel direction and method thereofUS20060170066 *Jan 31, 2005Aug 3, 2006Freescale Semiconductor Inc.Hybrid-fet and its application as sramUS20060172497 *Jun 27, 2003Aug 3, 2006Hareland Scott ANonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabricationUS20060180859 *Feb 16, 2005Aug 17, 2006Marko RadosavljevicMetal gate carbon nanotube transistorUS20060204898 *Feb 23, 2006Sep 14, 2006Martin GutscheProcess for producing sublithographic structuresUS20060220131 *Mar 21, 2006Oct 5, 2006Atsuhiro KinoshitaFin-type channel transistor and method of manufacturing the sameUS20060244066 *Jun 30, 2006Nov 2, 2006Taiwan Semiconductor Manufacturing Co., Ltd.Contacts to semiconductor fin devicesUS20060263699 *May 23, 2005Nov 23, 2006Mirzafer AbatchevMethods for forming arrays of a small, closely spaced featuresUS20060281266 *Jun 9, 2005Dec 14, 2006Wells David HMethod and apparatus for adjusting feature size and positionUS20070001219 *Jun 30, 2005Jan 4, 2007Marko RadosavljevicBlock contact architectures for nanoscale channel transistorsUS20070029624 *Aug 3, 2005Feb 8, 2007International Business Machines CorporationFin-type field effect transistorUS20070045735 *Aug 31, 2005Mar 1, 2007Orlowski Marius KFinFET structure with contactsUS20070052041 *May 31, 2004Mar 8, 2007Haruyuki SoradaSemiconductor device and method of fabricating the sameUS20070187682 *Aug 27, 2004Aug 16, 2007Nec CorporationSemiconductor device having fin-type effect transistorUS20070241414 *Jun 3, 2005Oct 18, 2007Mitsuru NarihiroSemiconductor Device and Manufacturing Process ThereforUS20080017890 *Jun 30, 2006Jan 24, 2008Sandisk 3D LlcHighly dense monolithic three dimensional memory array and method for formingUS20080017934 *Mar 16, 2007Jan 24, 2008Samsung Electronic Co., Ltd.Wire-type semiconductor devices and methods of fabricating the sameUS20080111163 *Nov 14, 2006May 15, 2008Infineon Technologies AgField effect transistor with a fin structureUS20080116515 *Nov 17, 2006May 22, 2008Infineon Technologies Agam CampeonMugfet with increased thermal massUS20080128797 *Nov 30, 2006Jun 5, 2008International Business Machines CorporationStructure and method for multiple height finfet devicesUS20080212392 *Mar 2, 2007Sep 4, 2008Infineon TechnologiesMultiple port mugfet sramUS20080237655 *Mar 24, 2008Oct 2, 2008Kabushiki Kaisha ToshibaSemiconductor apparatus and method for manufacturing sameUS20080258207 *Sep 14, 2007Oct 23, 2008Marko RadosavljevicBlock Contact Architectures for Nanoscale Channel TransistorsUS20090061572 *Oct 28, 2008Mar 5, 2009Intel CorporationNonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabricationUS20090099181 *Nov 16, 2007Apr 16, 2009Allergan, Inc.Sulfoximines as kinase inhibitorsUS20100200923 *Apr 13, 2010Aug 12, 2010Taiwan Semiconductor Manufacturing Co., Ltd.Multiple-gate transistor structure and method for fabricating* Cited by examinerNon-Patent CitationsReference1"International Preliminary Report on Patentability", PCT/US2004/032442, (Apr. 13, 2006), 13 pgs.2"International Preliminary Report on Patentability", PCT/US2005/010505, (Oct. 12, 2006), 16 pgs.3"International Search Report & Written Opinion", PCT/US2004/032442, (Jun. 16, 2005), 22 pgs.4"International Search Report & Written Opinion", PCT/US2004/032442, (Jun. 16, 2006), 12 pgs.5"International Search Report & Written Opinion", PCT/US2005/000947, (May 3, 2005), 7 pgs.6"International Search Report & Written Opinion", PCT/US2005/010505, (Aug. 26, 2005), 24 pgs.7"International Search Report & Written Opinion", PCT/US2005/033439, (Jan. 31, 2006), 7 pgs.8"International Search Report & Written Opinion", PCT/US2005/035380, (Feb. 13, 2006), 14 pgs.9"International Search Report & Written Opinion", PCT/US2005/037169, (Feb. 23, 2006), 11 pgs.10"International Search Report & Written Opinion", PCT/US2006/000378, (May 24, 2006), 11 pgs.11"International Search Report & Written Opinion", PCT/US2006/024516, (Jan. 17, 2007), 18 pgs.12"International Search Report & Written Opinion", PCT/US2006/025751, (Dec. 6, 2006), 14 pgs.13"International Search Report & Written Opinion", PCT/US2006/037634, (May 31, 2007), 21 pgs.14"International Search Report and Written Opinion", PCT/US2005/010505, (Aug. 26, 2005), 24 pgs.15"International Search Report and Written Opinion", PCT/US2005/020339, (Oct. 4, 2005), 11 pgs.16"International Search Report", PCT/US 03/26242, (Jan. 26, 2004), 8 pgs.17"International Search Report", PCT/US 03/39727, (Apr. 27, 2004), 6 pgs.18"International Search Report", PCT/US2003/40320, (Jun. 2, 2004), 6 pgs.19"Invitation to Pay Additional Fees", PCT/US2004/032442, (Apr. 12, 2005), 5 pgs.20"Office Action", European Patent Application No. 06815547.2 (P22156EP), Mailed Sep. 9, 2008, 3 pages.212nd OA KR 10-2007-7030988 mailed Mar. 12, 2010 3 pgs.22Auth, Christopher P., et al., "Vertical, Fully-Depleted, Surrounding Gate MOSFETs on sub-0.1nm Thick Silicon Pillars", 54th Annual Device Research Conference Digest, IEEE, (1996), 108-109.23Buchanan, D. A., et al., "Fabrication of Midgap Metal Gates Compatible With Ultrathin Dielectrics", Applied Physics Letters , 73(12), (Sep. 21, 1998), pp. 1676-1678.24Burenkov, A., "Corner effect in Double and Triple Gate FinFETs", European Solid-State Device Research 2003, 33rd Conference on. ESSDERC, (Sep. 16, 2003), pp. 135-138.25Chang, L., et al., "CMOS Circuit Performance Enhancement by Surface Orientation Optimization", IEEE Transactions on Electron Devices, 51(10), (Oct. 2004), pp. 1621-1627.26Chang, S. T., et al., "3-D Simulation of Strained S/SiGe heterojunction FinFets", Semiconductor Device Research Symposium, 2003 International Dec. 10-12, 2003, Piscataway, NJ, USA, (Dec. 2003), pp. 176-177.27Chau, Robert , Final Office Action mailed Feb. 17, 2010, 18 pages.28Chau, Robert, "Advanced Metal Gate/High-K Dielectric Stacks for High-Performance Cmos Transistors", Components Research, Intel Corporation, (2004), 1-3.29Chau, Robert, et al., Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate and Tri-Gate (invited paper), Components Research, Logic Technology Development, Hillsboro, OR, 2 pgs.30Choi, Yang-Kyu, et al., "A Spacer Patterning Technology for Nanoscale CMOS", IEEE, (49)3, XP-001102694, (Mar. 2002), pp. 436-441.31Choi, Yang-Kyu, et al., "Sub-20nm CMOS FinFET Technologies", IEEE, IEDM 01-421 to 1-424, (2001), pp. 421-424.32Claflin, B., et al., "Interface Studies of Tungsten Nitride and Titanium Nitride Composite Metal Gate Electrodes With Thin Dielectric Layers", Journal of Vacuum Science and Technology A 16.3, (May/Jun. 1998), pp. 1757-1761.33Collaert, N. , et al., "A Functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm Cmos node", IEEE Electron Device Letters, vol. 25, No. 8, Aug. 2004, 3 pgs.34Final Office Action from U.S. Appl. No. 11/080,765 mailed Nov. 13, 2007, 13 pgs.35Final Office Action from U.S. Appl. No. 11/158,661 mailed Jan. 15, 2008, 25 pgs.36Final Office Action from U.S. Appl. No. 11/240,487 mailed Sep. 21, 2009, 22 Pages.37Final Office Action from U.S. Appl. No. 12/025,665 mailed Jun. 10, 2009, 10 pgs.38Fried, David M., et al., "High-Performance P-Type Independent-Gate FinFETs", IEEE Electron Device Letters, 25(4), (Apr. 2004), pp. 199-201.39Fried, David M., et al., "Improved Independent Gate N-Type FinFET Fabrication and Characterization", IEEE Electron Device Letters, 24(9), (Sep. 2003), pp. 592-594.40German Office Action for German Patent Application No. 11 2006 003 576.2-33 mailed Dec. 12, 2008, 3 pgs.41Guo, Jing, et al., "Performance Projections for Ballistic Carbon Nanotube Field-Effect Transistors", Applied Physics Letters, 80(17), (Apr. 29, 2002), pp. 3192-3194.42Hisamoto, D., et al., "FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm", IEEE Transaction on Electron Devices, 47(12), (Dec. 2000), pp. 2320-2325.43Hisamoto, D., et al., "FinFET�A Self-Aligned Double-Gate MOSFET Scalable to 20 nm", IEEE Transaction on Electron Devices, 47(12), (Dec. 2000), pp. 2320-2325.44Hisamoto, Digh, et al, "A Folded-Channel MOSFET for Deepsub-tenth Micron Era", 1998 IEEE International Electron Device Meeting Technical Digest, (1998), pp. 1032-1034.45Hisamoto, Digh, et al., "A Fully Depleted Lean-Channel Transistor (DELTA)-A Novel Vertifcal Ultrathin SOI MOSFET", IEEE Electron Device Letters, IEEE, 11(1), 1990, pp. 36-3846Hisamoto, Digh, et al., "A Fully Depleted Lean-Channel Transistor (DELTA)�A Novel Vertifcal Ultrathin SOI MOSFET", IEEE Electron Device Letters, IEEE, 11(1), 1990, pp. 36-3847Huang, et al., "Sub 50 nm FinFET: PMOS", 1999 IEEE International Electron Device Meeting Technical Digest, (1999), pp. 67-70.48Hwang, Jeong-Mo, et al., "Novel Polysilicon/Tin Stacked-Gate Structure for Fully-Depleted SOI/CMOS", International Electronic Devices Meeting Technical Digest, (1992), pp. 345-348.49Ieong, et al., "Three Dimensional CMOS Devices and Integrated Circuits", IEEE CICC, San Jose, CA (Sep. 21-24, 2003), pp. 207-217.50International Preliminary Report on Patentability from Application No. PCT/US/2006/025751 mailed Jan. 9, 2008, 8 pgs.51International Preliminary Report on Patentability from Application No. PCT/US/2006/037634 mailed Apr. 10, 2008, 11 pgs.52International Preliminary Report on Patentability from Application No. PCT/US2006/024516 mailed Jan. 10, 2008, 11 pgs.53International Search Report & Written Opinion from PCT/US2006/037643 mailed on Jan. 24, 2007, 14 pgs.54International Search Report PCT/US2003/40320 mailed Jun. 2, 2004, 6 pgs.55IPO Search Report for Application No. 094136197, date mailed Sep. 19, 2008, 1 pg.56Javey, Ali , et al., "Ballistic Carbon Nanotube Field-Effect 424, Aug. 7, 2003, 4 pgs., Transistors", Nature, vol. 424, Aug. 7, 2003, 4 pgs.57Javey, Ali , et al., "High-k Dielectrics for Advanced Carbon-Nanotube Transistors and Logic Gates", www.nature.com/naturematerials.com, (Nov. 2002), pp. 1-8.58Jin, B. , "Mobility Enhancement in Compressively Strained Sige Surface Channel PMOS Transistors with HFO2/TIN Gate Stack", Componenets Research, Intel Corporation, pp. 1-12.59Jones, E. C., et al., "Doping Challenges in Exploratory Devices for High Performance Logic", 14th Int'l Conference, Piscataway, NJ, (Sep. 22-27, 2002), pp. 1-6.60Kim, Sung M., et al., "A Novel Multi-channel Field Effect Transistor (McFET) on Bulk Si for High Performance Sub 80-nm Application", IEEE, (2004), pp. 639-642.61Kuo, Charles , et al., "A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications", IEEE 50(12):, (2003), pp. 2408-2416.62Kuo, Charles , et al., "A Capacitorless Double-Gate DRAM Cell Design for High Density Applications", IEEE, (2002), pp. 843-846.63Ludwig, et al., "FinFET Technology for Future Microprocessors", 2003 IEEE Int'l . SOI Conference, New Port Beach, CA, (Sep. 29-Oct. 2, 2003), pp. 33-34.64Martel, Richard , et al., "Carbon Nanotube Field Effect Transistors for Logic Application", IEEE, pp. 7.5.1-7.5.4.65Mayer, T. M., et al., "Chemical Vapor Deposition of Flouroalkylsilane Monolayer Films for Adhesion Control in Microelectromechanical Systems", J. Vac. Sci. Technol. B. 18(5):, (2000), pp. 2433-2440.66Nackaerts, et al., "A 0.314um2 6T-SRAM Cell Build with Tall Triple-Gate Devices for 45nm node applications using 0.75NA 193 nm lithography", IEDM 2004, pp. 269-272.67Non-Final Office Action for U.S. Appl. No. 12/259,464, Mailed Oct. 20, 2009, 41.68Non-Final Office Action from U.S. Appl. No. 11/322,795 Mailed Jul. 28, 2009, 18 pgs.69Notice of Allowance from U.S. Appl. No. 11/173,866 mailed, May 31, 2007, 7 pgs.70Notice of Preliminary Rejection mailed Sep. 14, 2009 for Korean Application No. 10-2007-7030988 incl. translation, (Sep. 14, 2009), 4 pages.71Nowak E. J., et al., "A Functional FinFET-DGCMOS SRAM Cell", Int'l . Electron Devices Meeting, San Francisco, CA (Dec. 8-11, 2002), pp. 411-414.72Nowak, E. J., "Scaling Beyond the 65 nm Node with FinFET-DGCMOS", IEEE CIC, San Jose, CA (Sep. 21-24, 2003), pp. 339-342.73Nowark, Edward J., et al., "Turning Silicon On Its Edge.", IEEE Circuits & Devices Magazine vol. 1, (Jan./Feb. 2004), pp. 20-31.74Office Action for EP Application No. 05711376.3 mailed Jan. 11, 2010, 5 pages.75Office Action for German Application No. 112006001735.7 with translation mailed Oct. 20, 2009, 6 pages.76Office Action for Taiwan Application No. 95134963 (P22156TW) issued Jun. 1, 2009; incl. translation, Whole document.77Office Action from Chinese Patent Application No. 200680023301.X mailed Jun. 26, 2009, whole document.78Office Action from European Patent Application No. 03817699.6 mailed Aug. 29, 2007, 3 pgs.79Office Action from PRC Application No. 200580007279.5, PCT/US05/ 000947, mailed Apr. 4, 2008, 2 pgs.80Office Action from Taiwan Patent Application No. 95122087 mailed Dec. 16, 2008, 14 pgs.81Office Action from Taiwan Patent Application No. 95122087 mailed Jun. 10, 2008, 8 pgs.82Office Action from Taiwan Patent Application No. 95123858, dated Mar. 3, 2009, 4pgs.83Office Action from Taiwan Patent Application No. 95123858, dated Oct. 9, 2008, 10pgs.84Office Action from Taiwan Patent Application No. 95135820 mailed Jun. 4, 2009, 18 pgs.85Office Action from Taiwan Patent Application No. 95135820 mailed Oct. 22, 2009, 5 pgs.86Office Action from Taiwan Patent Application No. 95135820 mailed on Jan. 9, 2009, 14 pgs.87Office Action from U.S. Appl. No. 11/080,765 mailed May 2, 2007, 47 pgs.88Office Action from U.S. Appl. No. 11/173,866 mailed, Feb. 8, 2007, 21 pgs.89Office Action from U.S. Appl. No. 11/234,014 mailed Jan. 23, 2008, 9 pgs.90Office Action from U.S. Appl. No. 11/240,487 mailed Mar. 17, 2009, 13 pgs.91Office Action from U.S. Appl. No. 11/322,795 mailed Mar. 4, 2009, 12 pgs.92Office Action from U.S. Appl. No. 12/025,665 mailed on Nov. 12, 2008, 8 pgs.93Office Action from U.S. Patent Application No. 11/154,138 mailed Jun. 23, 2009, 14 pgs.94Ohsawa, Takashi , et al., "Memory Design Using a One-Transistor Gain Cell on SOI", IEEE 37 (11):, (Nov. 2002), pp. 1510-1522.95Park, Donggun, et al., "3-dimensional nano-CMOS Transistors to Overcome Scaling Limits", IEEE 2004, ISBN 0-7803-8511-X, pp. 35-40.96Park, et al., "PMOS Body-Tied FinFET (Omega MOSFET) Characteristics", Device Research Conference, Piscataway, NJ, Jun. 23-25, 2003, IEEE, pp. 33-34.97Park, J., "Pi-Gate SOI MOSFET", IEEE Electron Device Letters, vol. 22, No. 8, (Aug. 2001), pp. 405-406.98Park, Jae-Hyoun, et al., "Quantum-Wired MOSFET Photodetector Fabricated by Conventional Photolighography on SOI Substrate", Nanotechnology, 2004, 4th IEEE Conference on Munich, Germany, Aug. 16-19, 2004, Piscataway, NJ, pp. 425-427, XP010767302.99Park, T., et al., "Fabrication of Body-Tied FinFETs (Omega MOSFETs) Using Bulk Si Wafers", 2003 Symposium on VLSI Technology Digest of Technical Papers, (2003), pp. 1-2.100Second Office Action from Chinese Patent Application No. 200580032314.9 mailed May 8, 2009, 14 pgs.101Seevinck, Evert , et al., "Static-Noise Analysis of MOS SRAM Cells", IEEE, Journal of Solid-State Circuits, (SC-22)5, (Oct. 1987), pp. 748-754.102Stadele, M. , et al., "A Comprehensive Study of Corner Effects in Tri-gate Transistors", IEEE 2004, pp. 165-168.103Stolk, Peter A., et al., "Modeling Statistical Dopant Fluctuations in MOS Transistors", IEEE Transactions on Electron Devices, 45(9), (1997), pp. 153-156.104Subramanian V. , "A Bulk-Si-Compatible Ultrathin-body SOI Technology for Sub-100m MOSFETS", Proceeding of the 57th Annual Device Research Conference, (1999), pp. 28-29.105Sugizakai, T. , et al., "Novel Multi-bit SONOS Type Flash Memory Using a High-k Charge Trapping Layer", VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on Jun. 10-12, 2003., pp. 27-28.106Tanaka, T., et al., "Scalability Study on a Capacitorless IT-DRAM: From Single-gate PD-SOI to Double-gate FinDRAM", IEEE, (2004), pp. 1-4.107Tang, Stepehn H., et al., "FinFET-A Quasi-Planar Double-Gate MOSFET", 2001 IEEE International Solid-State Circuits Conference, Feb. 6, 2001, 3 pgs.108Tang, Stepehn H., et al., "FinFET�A Quasi-Planar Double-Gate MOSFET", 2001 IEEE International Solid-State Circuits Conference, Feb. 6, 2001, 3 pgs.109Tokoro, Kenji , et al., "Anisotropic Etching Properties of Silicon in KOH and TMAH Solutions", International Symposium on Micromechatronics and Human Service, IEEE, 1998, 6 pgs.110U.S. Office Action, "U.S. Appl. No. 10/227,068", (Dec. 18, 2006), pp. 1-25.111U.S. Office Action, "U.S. Appl. No. 10/703,316", (Dec. 15, 2006), pp. 1-22.112Wang, X. , et al., "Band alignments in sidewall strained Si/strained SiGe heterostructures", (May 28, 2002), 1-5.113Wolf, Stanley , et al., "Wet Etching Silicon", Silicon Processing for the VLSI Era, vol. 1: Process Technology, Sep. 1986, 3 pgs.114Written Opinion from Patent Application No. 2005070131 mailed Mar. 18, 2007, 4 pgs.115Written Opinion from Singapore Patent Application No. 200604766-6 mailed Apr. 4, 2008, 4 pgs.116Xiong, W., et al., "Corner Effect in Multiple-Gate SOI MOSFETs", IEEE, (2003), 111-113.117Xiong, Weize, et al., "Improvement of FinFET Electrical Characteristics by Hydrogen Annealing", 25(8):, (2004), pp. 541-543.118Yang, Fu-Liang, et al, "25nm CMOS Omega FET's," IEEE 2002, 10.3.1-10.3.4.119Yang, Fu-Liang, et al., "5nm-Gate Nanowire FinFET", IEEE, (2004), pp. 196-197.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8187928Sep 21, 2010May 29, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Methods of forming integrated circuitsUS8264021Apr 16, 2010Sep 11, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Finfets and methods for forming the sameUS8264032Apr 9, 2010Sep 11, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Accumulation type FinFET, circuits and fabrication method thereofUS8298881 *Jun 28, 2010Oct 30, 2012International Business Machines CorporationNanowire FET with trapezoid gate structureUS8298925Nov 8, 2010Oct 30, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Mechanisms for forming ultra shallow junctionUS8305790Mar 16, 2010Nov 6, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Electrical anti-fuse and related applicationsUS8305829Feb 18, 2010Nov 6, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the sameUS8399922 *Sep 14, 2012Mar 19, 2013Intel CorporationIndependently accessed double-gate and tri-gate transistorsUS8431453Mar 31, 2011Apr 30, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structureUS8440517Oct 13, 2010May 14, 2013Taiwan Semiconductor Manufacturing Company, Ltd.FinFET and method of fabricating the sameUS8461015Apr 9, 2010Jun 11, 2013Taiwan Semiconductor Manufacturing Company, Ltd.STI structure and method of forming bottom void in sameUS8472227Jan 27, 2010Jun 25, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Integrated circuits and methods for forming the sameUS8482073 *Mar 25, 2010Jul 9, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Integrated circuit including FINFETs and methods for forming the sameUS8497528May 6, 2010Jul 30, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Method for fabricating a strained structureUS8536658Oct 12, 2012Sep 17, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Mechanisms for forming ultra shallow junctionUS8592915Jan 25, 2011Nov 26, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Doped oxide for shallow trench isolation (STI)US8603924Jan 11, 2011Dec 10, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Methods of forming gate dielectric materialUS8623728Jul 7, 2010Jan 7, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Method for forming high germanium concentration SiGe stressorUS8629478Jun 10, 2010Jan 14, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Fin structure for high mobility multiple-gate transistorUS8652894 *Nov 9, 2012Feb 18, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Method for fabricating a FinFET deviceUS8693235 *Dec 6, 2011Apr 8, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Methods and apparatus for finFET SRAM arrays in integrated circuitsUS8735266Aug 20, 2013May 27, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Mechanisms for forming ultra shallow junctionUS8753964 *Jan 27, 2011Jun 17, 2014International Business Machines CorporationFinFET structure having fully silicided finUS8759943Oct 8, 2010Jun 24, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Transistor having notched fin structure and method of making the sameUS8769446Sep 8, 2011Jul 1, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Method and device for increasing fin device density for unaligned finsUS8806397Sep 4, 2013Aug 12, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Method and device for increasing fin device density for unaligned finsUS8809940Apr 9, 2013Aug 19, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Fin held effect transistorUS8829625Aug 10, 2012Sep 9, 2014International Business Machines CorporationNanowire FET with trapezoid gate structureUS8836046 *Sep 9, 2013Sep 16, 2014Samsung Electronics Co., Ltd.Semiconductor devices including protruding insulation portions between active finsUS8877602Jun 9, 2011Nov 4, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Mechanisms of doping oxide for forming shallow trench isolationUS8896055Aug 14, 2012Nov 25, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Accumulation type FinFET, circuits and fabrication method thereofUS8908421Feb 11, 2014Dec 9, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Methods and apparatus for FinFET SRAM arrays in integrated circuitsUS8912602Apr 12, 2010Dec 16, 2014Taiwan Semiconductor Manufacturing Company, Ltd.FinFETs and methods for forming the sameUS20110233679 *Mar 25, 2010Sep 29, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Integrated circuit including finfets and methods for forming the sameUS20110315950 *Jun 28, 2010Dec 29, 2011International Business Machines CorporationNanowire fet with trapezoid gate structureUS20120074472 *Sep 21, 2011Mar 29, 2012Renesas Electronics CorporationPower Semiconductor Device Having Gate Electrode Coupling Portions for Etchant ControlUS20120193712 *Jan 27, 2011Aug 2, 2012International Business Machines CorporationFinFET STRUCTURE HAVING FULLY SILICIDED FINUS20130071980 *Nov 9, 2012Mar 21, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Method for fabricating a finfet deviceUS20130141962 *Dec 6, 2011Jun 6, 2013Taiwan Semicondcutor Manufacturing Company, Ltd.Methods and Apparatus for finFET SRAM Arrays in Integrated CircuitsUS20140151810 *Sep 9, 2013Jun 5, 2014Shigenobu MaedaSemiconductor devices including protruding insulation portions between active fins* Cited by examinerClassifications U.S. Classification257/401, 257/E29.13, 257/288, 257/388, 257/213International ClassificationH01L27/01Cooperative ClassificationH01L2029/7858, H01L29/41791, H01L29/66795, H01L29/785, H01L29/78684, H01L29/66545, H01L29/7851, H01L29/78681European ClassificationH01L29/78S, H01L29/417D14, H01L29/66M6T6F16FLegal EventsDateCodeEventDescriptionAug 20, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services