Source: https://patents.google.com/patent/JP2008299611A/en
Timestamp: 2020-01-19 07:17:57
Document Index: 529843631

Matched Legal Cases: ['art, 3', 'art, 4', 'art, 5', 'art, 6', 'art, 7', 'art, 8', 'art, 9']

JP2008299611A - Memory security device - Google Patents
Memory security device Download PDF
JP2008299611A
JP2008299611A JP2007145265A JP2007145265A JP2008299611A JP 2008299611 A JP2008299611 A JP 2008299611A JP 2007145265 A JP2007145265 A JP 2007145265A JP 2007145265 A JP2007145265 A JP 2007145265A JP 2008299611 A JP2008299611 A JP 2008299611A
JP2007145265A
誠一郎 齋藤
2007-05-31 Priority to JP2007145265A priority Critical patent/JP2008299611A/en
2008-12-11 Publication of JP2008299611A publication Critical patent/JP2008299611A/en
<P>PROBLEM TO BE SOLVED: To prevent illegal data acquisition and alteration to a memory unit body. <P>SOLUTION: A memory security device 1 is provided with an address encryption means 4 which creates an encryption writing destination address by encrypting a writing destination address during data writing, and creates an encryption reading destination address by encrypting a reading destination address in the case of reading data; a data encryption means 5 which creates encryption writing data by encrypting writing data to the writing destination address; a writing means 6 which writes the encryption writing data in a memory 9 according to the encryption writing destination address; a reading means 7 for reading the encryption reading data from the memory 9 according to the encryption reading destination address; and a data decryption means 8 which creates the reading data to the reading destination address by decrypting the encryption reading data. <P>COPYRIGHT: (C)2009,JPO&INPIT
The present invention relates to a memory security device for protecting data stored in a memory.
In the secret information management apparatus 100 of Patent Document 1, when storing secret information during which secret information is not used, the random number generation unit 1021 generates a random number, and the encryption unit 1022 encrypts the secret information using the random number as an encryption key. (That is, concealment), the encrypted secret information is stored in the memory 101, and the transmission unit 105 transmits the encryption key to the outside and stores it in another information management apparatus. In the secret information management device 100 of Patent Document 1, when using secret information, the receiving unit 106 receives an encryption key from another information management device, and the encryption / decryption unit 1041 receives the received encryption key as an encryption / decryption key. The encrypted secret information stored in the memory 101 is decrypted (that is, recovered).
In Patent Document 2, encryption processing is performed on data stored in the external memory 4 in accordance with the storage position to be stored. Thus, for example, even if the encrypted data is copied from the external memory 4 to another storage medium, the encrypted data can be decrypted if it is not recognized in which storage location in the external memory 4 Can not.
In the system of Patent Document 3, the serial number of the recording medium and the user-specific data are encrypted and recorded on the recording medium, and when used, they are read out and decrypted to determine whether or not they are used illegally. Prevents unauthorized use by enabling an operation stop request.
In general, for example, when a chip (for example, a slave device) is connected to a certain device (for example, a host), and the memory of this chip is an external chip, the chip itself is removed from the device in normal use. Having a function that restricts access prevents unauthorized acquisition or falsification of code or data stored in the memory.
JP 2006-129340 A JP 2006-023957 A JP 2005-301339 A
However, when the power to the external memory is turned on due to the power saving function, etc., or when the power of the chip is turned off, or the reverse engineer intentionally turns off the power of the chip and supplies power only to the memory. When creating a situation, it may be possible to read the contents of this memory.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory security device that prevents illegal acquisition and alteration of data performed on a single memory.
The above-described problems are address encryption means for encrypting a write destination address to create an encrypted write destination address at the time of data writing, and creating an encrypted read destination address by encrypting the read destination address at the time of data reading, and a write destination Data encryption means for encrypting write data for an address to create encrypted write data, write means for writing encrypted write data to memory according to the encrypted write destination address, and memory according to the encrypted read destination address The memory security device includes a reading unit that reads out the encrypted read data and a data decryption unit that decrypts the encrypted read data and creates read data for the read destination address.
According to the present invention, it is possible to prevent illegal acquisition and falsification of data performed on a single memory.
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in the following each figure, the part which implement | achieves the same function attaches | subjects the same code | symbol, and abbreviate | omits description.
In the present embodiment, a memory security device having a function of converting the contents of data stored in a memory and further shuffling the storage position of the converted data will be described.
FIG. 1 is a block diagram showing an example of a memory security device according to the present embodiment.
The memory security device 1 according to the present embodiment includes a random number generation unit 2, a random number storage unit (register) 3, an address encryption unit 4, a data encryption unit 5, a write unit 6, a read unit 7, and a data decryption unit 8 It comprises.
In the present embodiment, it is assumed that the memory 9 and the device (for example, memory controller, memory interface, etc.) 10 are different chips. It is assumed that the memory security device 1 is provided in the device 10.
The memory 9 and the device 10 are connected by a bus RQ, a bus DQ, and a serial connection 11. The bus RQ is used to transfer a request between the device 10 and the memory 9. The bus DQ is used for data transfer between the device 10 and the memory 9. The serial connection 11 is used to transfer test data, initialization data, and debug data between the device 10 and the memory 9.
The host device 12 uses the device 10 to write data to the memory 9 and read data from the memory 9.
In the present embodiment, the random number generation unit 2 of the memory security device 1 generates a random number including an address random number and a data random number, and stores the random number in the random number storage unit 3. The memory security device 1 employs a structure in which the random number generated by the random number generation unit 2 and stored in the random number storage unit 3 cannot be read from the outside of the memory security device 1.
When writing data to the memory 9, the address encryption unit 4 XORs the write destination address with the address random number stored in the random number storage unit 3 to create an encrypted write destination address.
Further, when reading data from the memory 9, the address encryption unit 4 XORs the read destination address with the address random number stored in the random number storage unit 3, and sets the encrypted read destination address. create.
When data is written to the memory 9, the data encryption unit 5 XORs the write data with the data random number stored in the random number storage unit 3 to create encrypted write data.
The writing unit 6 writes the encrypted write data created by the data encryption unit 5 in the area indicated by the encrypted write destination address created by the address encryption unit 4 in the memory 9.
The reading unit 7 reads the encrypted read data from the area indicated by the encrypted read destination address created by the address encryption unit 4 to the memory 9.
The data decryption unit 8 XORs the encrypted read data read by the read unit 7 with the data random number stored in the random number storage unit 3 to create read data corresponding to the read data. .
In the memory security device 1 according to the present embodiment, a random number is generated and changed by the built-in random number generator 2 every time it is activated. The random number includes a random number for address and a random number for data, and is stored in the random number storage unit 3.
Thereafter, the address random number and the data random number stored in the random number storage device 3 are used until a reset is input to the device 10.
The random number for address is used for shuffling with respect to the address, and the random number for data is used for data scrambling.
Since the random number generator 2 changes the random number (seed) every time it is activated, it does not have the same value before and after the reset. The address random number and the data random number cannot be read from the outside. A value cannot be set in the random number storage unit 3 from another device that is not the random number generation unit 2.
The concept of data protection by the memory security device 1 according to this embodiment will be described below.
As shown in FIG. 2, when performing normal access restriction on the memory 9, the device 13 restricts access from the host device 12 to the memory 9, and content to be protected (for example, firmware, various programs, data, etc.) The 14 stored memories 9 cannot be directly accessed. In general, the access restriction can be turned on / off from the inside of the device 13.
However, even when the access restriction or the like is applied to the memory 9, direct writing into the memory 9 is possible by using the serial IO function etc. of the memory 9 itself.
Utilizing such a property, for example, as shown in FIG. 3, the crack code 16 including the code for releasing the access restriction using the illegal writing device 15 is directly stored in the memory using the buffer overflow, the buffer overrun or the like. 9, an attack method of releasing the access restriction inside the device 13 (the device 13 executes the crack code 16) is possible. When the crack code 16 is executed by the device 13, the host device 12 can access the content 14 whose access is restricted.
As a defense against such an attack, in this embodiment, the write data is shuffled, the storage location of the write data in the memory 9 is also shuffled, and the crack code 16 written in the memory 9 by the serial IO function is caused by the device 10. Adopt a mechanism to prevent execution.
FIG. 4 is a block diagram showing an example of a state in which data is protected by the memory security device 1 according to the present embodiment.
In FIG. 4, the device 10 performs writing to the memory 9 with the address and data shuffled. Furthermore, the device 10 reads data from the memory 9 in a state where the address and data are shuffled, and converts the data into a normal state.
For example, it is assumed that the crack code 16 is written in the memory 9 by the unauthorized writing device 15 using buffer overflow, buffer overrun, or the like.
In such a case, even if the crack code 16 is read by the device 10, the data decoding unit 8 performs an XOR operation using a random number on the read crack code 16. 16 will not function.
Therefore, it is possible to prevent the content 14 to be protected from being illegally acquired by the crack code 16.
Further, since the storage position and content of the content 14 are shuffled in the memory 9 due to the encryption of the address and data, the content 14 is protected even if the storage content of the memory 9 can be read. Can do.
FIG. 5 is a diagram showing an example of shuffling for addresses by the memory security device 1 according to the present embodiment. Although FIG. 5 shows shuffle processing for the write destination address, the same applies to the shuffle processing for the read destination address.
When a write destination address for the write data is issued, the random number generation unit 2 generates a random number, and the random number storage unit 3 stores the random number.
In the present embodiment, specific 21 bits among the generated random numbers of 36 bits are used as address random numbers and used for XOR of the write destination address. An encrypted write destination address is created by XORing an upper area including areas such as row, bank, and column among write destination addresses with a random number for addresses.
Writing to the memory 9 is executed according to the encrypted write destination address instead of the write destination address.
FIG. 6 is a diagram showing an example of shuffle processing for write data by the memory security device 1 according to the present embodiment.
The random number generator 2 generates a 32-bit random number, and this random number is used as a data random number for XOR of write data. The unit for XORing the write data is 32 bits. That is, the XOR operation is performed for every 32 bits of write data using the same random number for data.
Although FIG. 6 shows shuffle processing for write data, the same applies to processing for decoding read data. For example, the memory security device 1 takes out the encrypted read data from the external memory chip in 512-bit units, performs an XOR operation on the encrypted read data with a random number for data every 32 bits, and obtains 512-bit read data that has been descrambled. In this way, XOR is applied to the encrypted read data (32 bits × 16 pieces) with the same random number for data in units of 32 bits.
Since the memory security device 1 XORs both the address and the data in each case of writing and reading, the same value can be obtained on the system side.
As described above, in the present embodiment, the position where the instruction sequence included in the content 14 is stored in the memory 9 is different every time the memory security device 1 is activated. It is possible to prevent the position from being attacked. Further, even if the crack code 16 is written in the memory 9, since the device 1 performs data decryption on the read data, the crack code 16 is executed by the device 10 and the access restriction is released. Can be prevented.
In other words, in the present embodiment, even when data is written in the memory 9 using the serial IO function, the written content and the writing position can be made meaningless, and the memory 9 is modified. Act becomes difficult.
In the present embodiment, an encryption method and a decryption method that generate a random number and perform an XOR operation using the random number are employed, but other encryption methods and decryption methods may be used. . For example, various reversible transformations can be used. In addition, irreversible transformation can be used for encryption of write data and decryption of encrypted read data. Different methods may be used for data encryption and address encryption.
In the present embodiment, a case where the memory security device 1 according to the first embodiment is applied to a multiprocessor will be described.
FIG. 7 is a block diagram showing an example of a multiprocessor provided with the memory security device 1 according to the present embodiment.
The multiprocessor 17 performs processing by hardware since there are many fixed formats for decoding (decompressing) compressed video data, and encoding of video data can be converted into formats corresponding to various devices. Therefore, it is processed flexibly by software by a programmable processor element (for example, DSP: Digital Signal Processor).
The multiprocessor 17 includes a hardware decoding unit 18, a hardware decoding unit 19, a plurality of processor elements (SPE: Synergistic Processor Element) 20a to 20d, for example, a high-speed general-purpose bus interface (PCIe I / F) 21 such as PCI Express, A memory controller 22, a control processor (SCP) 23, and a data transfer unit (DMAC: Direct Memory Access Controller) 24 are connected via an internal bus (Interconnect Network) 25.
The general-purpose bus interface 21 exchanges data with the external device 26 via the bus 27.
The memory controller (memory interface) 22 is connected to a memory 28 used for the hardware decoding units 18 and 19 and the plurality of processor elements 20a to 20d.
The memory controller 22 corresponds to the device 10 of the first embodiment and includes the memory security device 1.
The memory 28 includes compressed video data 29a received by the multiprocessor 17, video data 29b obtained by decoding the compressed video data 29a, compressed video data 29c obtained by editing and compressing the video data 29b, and editing software. 29d and encoding software 29e are stored. This memory 28 corresponds to the memory 9 of the first embodiment.
The control processor 23 is a processor that controls the hardware decoding units 18 and 19, the plurality of processor elements 20a to 20d, the data transfer unit 24, and the like.
The data transfer unit 24 performs data transfer between the general-purpose bus interface 21 and the memory controller 22.
The hardware decoding unit 18 is configured by hardware, and decodes data (for example, mpeg2 / mpeg1) compressed in the first format.
The hardware decoding unit 19 is configured by hardware, and decodes data (for example, H.264 / VC1) compressed in the second format.
The plurality of processor elements 20 a to 20 d can operate in parallel under the control of the control processor 23. At least one of the plurality of processor elements 20a to 20d executes editing software 29d in the memory 28 in accordance with the control processor 23 to create editing data.
Further, at least one of the plurality of processor elements 20a to 20d executes the encoding software 29e of the memory 28 in accordance with the control processor 23, and encodes various data such as decoded video data 29b or editing data. To do.
In the present embodiment, the case where the four processor elements 20a to 20d are provided in the multiprocessor 17 is described as an example, but the number of processor elements provided in the multiprocessor 17 is two or more. If so, it can be changed freely.
That is, in the multiprocessor 17, the decoding is executed by the hardware decoding unit 18 or the hardware decoding unit 19 which is hardware, and the encoding is realized by the encoding software 29e operating on at least one of the processor elements 20a to 20d. Is done.
Since the resolution and the number of formats of the video data are fixedly determined by standards such as terrestrial digital broadcasting, BS high-definition broadcasting, HD-DVD, and Blue Ray, for example, in this embodiment, the compressed video data 29a is decoded. The hardware decoding unit 18 or the hardware decoding unit 19 which is hardware performs fixed processing. Generally, when a certain process is configured by hardware, the chip area is reduced.
There are various apparatuses for reproducing compressed video data, such as a mobile phone, a portable video player, a DVD recorder, a game machine, and a computer system. As described above, with regard to a wide variety of compressed video data playback apparatuses, the resolution and format are not uniformly defined, and the production company of each product often determines the resolution and format freely. Therefore, in the multiprocessor 17 according to the present embodiment, encoding of video data is performed by the processor elements 20a to 20d by the encoding software 29e in order to perform flexibly in a format corresponding to the playback apparatus for compressed video data.
Since the encoding software 29e can be updated, even if the playback device of the compressed video data and the encoding standard change after the multiprocessor 17 is shipped, the encoding software 29e can be handled.
The processing of the multiprocessor 17 having the above configuration will be described by dividing it from the first stage to the fourth stage.
In the first stage, the control processor 23 controls the data transfer unit 24. The data transfer unit 24 transfers compressed video data (compressed video stream) 29 a received by the general-purpose bus interface 21 from the external device 26 via the bus 27 to the memory controller 22 via the internal bus 25. The memory controller 22 stores the contents of the compressed video data 13a and the storage position thereof in the memory 28 in a state of being shuffled by the memory security device 1.
In the second stage, the control processor 7 controls the hardware decoding unit 18 or the hardware decoding unit 19. The hardware decoding unit 18 or the hardware decoding unit 19 acquires the compressed video data 29a stored in the memory 28 via the memory controller 22 and the internal bus 25. Here, when reading the compressed video data 29a from the memory 28, the memory controller 22 converts the read destination address by the memory security device 1 and decrypts the compressed video data 29a that is the read target and is encrypted. To do.
The hardware decoding unit 18 or the hardware decoding unit 19 decodes the compressed video data 29 a and stores the decoded video data 29 b in the memory 28 via the internal bus 25 and the memory controller 22. Here, the memory controller 22 stores the content of the decoded video data 29b and its storage position in the memory 28 in a state where the memory security device 1 has shuffled the content and the storage position thereof.
In the third stage, the control processor 23 controls at least one processor element (in this case, the processor elements 20a to 20d) among the plurality of processor elements 20a to 20d. The at least one processor element 20a to 20d accesses the editing software 29d stored in the memory 28 and the encoding software 29e stored in the memory 28 via the memory controller 22 and the internal bus 25, and the memory 28 The decoded video data 29b stored in is acquired. Here, when the memory controller 22 reads the editing software 29d, the encoding software 29e, and the decoded video data 29b from the memory 28, the memory controller 22 converts the read destination address by the memory security device 1 and encrypts the read destination address. The edited editing software 29d, encoding software 29e, and decoded video data 29b are decoded.
The processor elements 20a to 20d edit the video data 29b decoded by the operation based on the editing software 29d, encode the edited data by the operation based on the encoding software 29e, and the compressed video data 29c obtained by the encoding. The data is stored in the memory 28 via the internal bus 25 and the memory controller 22. Here, the memory controller 22 stores the contents of the compressed video data 29c and their storage positions in the memory 28 in a state of being shuffled by the memory security device 1. Note that the processor element that executes the editing software 29d and the processor element that executes the encoding software 29e may be overlapped or different.
In the fourth stage, the control processor 23 controls the data transfer unit 24. The data transfer unit 24 transfers the compressed video data 29 c stored in the memory 28 to the general-purpose bus interface 21 via the memory controller 22 and the internal bus 25. The general-purpose bus interface 21 transmits the compressed video data 29 c to the external device 26 via the bus 27. Here, when reading the compressed video data 29c from the memory 28, the memory controller 22 converts the read destination address by the memory security device 1, and decrypts the compressed video data 29c that is the read target and is encrypted. To do.
FIG. 8 is a block diagram showing an application example of the multiprocessor 17 according to the present embodiment. FIG. 8 illustrates a case where the multiprocessor 17 is provided in the computer system 30.
In the present embodiment, the computer system 30 includes a CPU 31, a memory 32, a GPU 33, a memory / processor control connection unit 34, an I / O control connection unit 35, a multiprocessor 17, and a memory 28.
The computer system 30 acquires data from the USB 36a, audio device 36b, network 36c, HDD or DVD 36d, and tuner 36e, and provides data to the USB 36a, audio device 36b, network 36c, HDD, or DVD 36d.
The memory / processor control connection unit 34 and the memory 32 are connected by a bus 37a having a bandwidth (transfer rate) of 8 GByte / sec, for example.
The memory / processor control connection unit 34 and the GPU 33 are connected by a bus 37b having a bandwidth of 4 GByte / sec, for example.
The memory / processor control connection unit 34 and the CPU 31 are connected by a bus 37c having a bandwidth of 8 GByte / sec, for example.
The memory / processor control connection unit 34 and the I / O control connection unit 35 are connected by a bus 37d having a bandwidth of 1 GByte / sec, for example.
The I / O control connection unit 35 and the multiprocessor 17 are connected by a bus 27 having a bandwidth of 1 GByte / sec, for example.
Data transfer is performed with a bandwidth of, for example, 100 MByte / sec between the I / O control connection unit 35 and the USB 36a, and between the I / O control connection unit 35 and the audio device 36b.
Between the I / O control connection unit 35 and the network 36c, between the I / O control connection unit 35 and the HDD or DVD 36d, and between the I / O control connection unit 35 and the tuner 36e, for example, a 250 MByte / sec band. Data transfer is performed in width.
The I / O control connection unit 35 is a chip that connects the various devices 36 a to 36 e and other components of the computer system 30.
The memory / processor control connection unit 34 connects the memory 32, the CPU 31, the GPU 33, and the I / O control connection unit 35.
The memory / processor control connection unit 34 includes the memory security device 1 according to the first embodiment, and uses the memory security device 1 for writing data into and reading data from the memory 32.
Hereinafter, the operation of the computer system 30 will be described.
The I / O control connection unit 35 receives the compressed video data 29a from any of the USB 36a, the audio device 36b, the network 36c, the HDD or DVD 36d, and the tuner 36e, and transfers the compressed video data 29a to the multiprocessor 17 via the bus 27. To do.
The multiprocessor 17 receives the compressed video data 29a, decodes it with internal hardware, executes necessary editing processing with the editing software 29d, encodes the editing data with the encoding software 29e, and handles it in the computer system 30. The compressed video data 29 c is created, and the compressed video data 29 c is transferred to the I / O control connection unit 35 via the bus 27. When the multiprocessor 17 uses the memory 28, the memory security device 1 provided in the multiprocessor 17 is used.
The I / O control connection unit 35 transfers the compressed video data 29c to the memory / processor control connection unit 34 via the bus 37d.
The memory / processor control connection unit 34 transfers the compressed video data 29c to any of the CPU 31, the memory 32, and the GPU 33 via any of the buses 37c, 37a, and 37b.
When receiving the compressed video data 29c, the CPU 31 decodes the compressed video data 29c using the decoding function 31a. Then, the CPU 31 stores the decoded video data 38 in the memory 32 via the bus 37c, the memory / processor control connection unit 34, and the bus 37a. When the memory / processor control connection unit 34 writes the decoded video data 38 to the memory 32, the memory security device 1 of the memory / processor control connection unit 34 is used.
When the GPU 33 receives the compressed video data 29c, the GPU 33 uses the decoding function 33a to decode the compressed video data 29c. Then, the GPU 33 performs a process for outputting the decoded video data 38.
Note that the GPU 33 may store the decoded video data 38 in the memory 32 via the bus 37b, the memory / processor control connection unit 34, and the bus 37a. In this case, the memory / processor control connection unit 34 stores the decoded video data 38 in the memory 32 using the memory security device 1. The GPU 33 may output the video data 38 decoded by the CPU 31.
The memory 38 stores the compressed video data 29c, the video data 38 obtained by decoding the compressed video data 29c, and other software used by the CPU 31, the GPU 33, and the like. The contents stored in the memory 38 are shuffled by the memory security device 1 of the memory / processor control connection unit 34.
Conversely, the I / O control connection unit 35 is connected to any one of the CPU 31, the memory 32, and the GPU 33.
The compressed video data is received via any of the buses 37c, 37a, and 37b, the memory / processor control connection unit 34, and the bus 37d. Then, the I / O control connection unit 35 transfers the received compressed video data to the multiprocessor 17 via the bus 27.
The multiprocessor 17 receives the compressed video data, internally decodes it, executes necessary editing processing, compresses the edited data again, and transfers the compressed video data to the I / O control connection unit 35 via the bus 27. . When the multiprocessor 17 uses the memory 28, the memory security device 1 provided in the multiprocessor 17 is used.
The I / O control connection unit 35 outputs the compressed video data to any one of the USB 36a, the audio device 36b, the network 36c, and the HDD / DVD 36d.
One of the data transfer from the CPU 31, the memory 32, or the GPU 33 to the multiprocessor 17 and the data transfer from the multiprocessor 17 to any of the CPU 31, the memory 32, or the GPU 33 are transferred. The data may not be compressed.
As described above, in the computer system 30, between the CPU 31 and the memory / processor control connection unit 34, between the memory 32 and the memory / processor control connection unit 34, and between the GPU 33 and the memory / processor control connection unit 34. The bandwidth of data transfer in is 8 GByte / sec or 4 GByte / sec.
In contrast, the bandwidth of data transfer between the memory / processor control connection unit 34 and the I / O control connection unit 35 and between the I / O control connection unit 35 and the multiprocessor 17 is 1 GByte / sec. .
That is, the bandwidth of data transfer between the CPU 31 and the memory / processor control connection unit 34, between the memory 32 and the memory / processor control connection unit 34, and between the GPU 33 and the memory / processor control connection unit 34 is It is wider than the data transfer bandwidth between the / processor control connection unit 34 and the I / O control connection unit 35, between the I / O control connection unit 35 and the multiprocessor 17, and the like.
For example, when transferring video data through the path of the I / O control connection unit 35, the bus 37d, the memory / processor control connection unit 34, the bus 37a, and the memory 32, the memory / processor control connection unit 34 and the I / O control connection unit The bus 37d to and from 35 has a bandwidth of 1 GByte / sec, and other data is transferred between the memory / processor control connection unit 34 and the I / O control connection unit 35 during the transfer of the video data. Since it is necessary to enable data transfer, the entire bandwidth of 1 GByte / sec cannot be used for transferring video data on the bus 37d. If the bandwidth is limited in the transfer of video data, it may be difficult to ensure the real-time property of the video data.
However, in this embodiment, since the compressed video data 29c is transferred between the memory / processor control connection unit 34 and the I / O control connection unit 35, the bandwidth of the bus 37d is efficiently used. In addition, data can be transferred in a state where the bandwidth of the bus in the computer system 30 has a margin, and real-time performance can be ensured even for video data having a large data size.
In other words, in the present embodiment, since the compressed video data is transferred on the bus 37d in the computer system 30, the data can be transferred in a state where real-time property is ensured even if the data transfer is duplicated on the bus 37d.
The above effect will be specifically described. For example, the bandwidth required for conventional NTSC data transfer is 320 (width) × 240 (height) × 3 (color) × 60 (frame / second) = about 15 MByte / sec. However, when handling high-definition broadcast video data, a bandwidth of 1920 (width) × 1080 (height) × 3 (color) × 60 (frame / second) = about 180 MByte / sec is required. In order to transfer high-definition broadcast video data in one direction on the bus and in the other direction, a bandwidth of about 360 MByte / sec is required. Actually, since it is necessary to transfer control information and the like, a wider bandwidth is required.
For example, a bus conforming to the first standard with a bandwidth of 133 MByte / sec in one slot (× 1) or a bus according to a second standard with a bandwidth of 250 MByte / sec in one slot (× 1) Then, there is not enough bandwidth to transfer the high-definition broadcast video data as described above as it is.
For example, a bus with 4 slots (× 4) in the second standard has a bandwidth of 1 GByte / sec, but the data transfer efficiency is normally 60% to 75%, overlapping with other data transfers. In some cases, video data cannot be transferred using the entire bandwidth of 1 GByte / sec.
However, in the computer system 30 including the multiprocessor 17 according to the present embodiment, as described above, the video data is compressed and transferred in a format corresponding to the computer system 30, so that the video data of the high-definition broadcast, etc. Even with such a large amount of data, output of video data can be executed while ensuring real-time performance.
In the multiprocessor 17 according to the present embodiment, at least one of the plurality of processor elements 20a to 20d decodes, edits, and encodes the compressed video data 29a to generate the compressed video data 29c. However, for example, the compressed video data of one format is converted to the compressed video data of another format, such as converting the data compressed with mpeg2 into the data compressed with H.264 (transformer). Codec) processing may be executed and editing processing may not be executed.
In the present embodiment, the editing process includes, for example, a process of extracting a sports highlight scene and a specific corner of a news program using an image processing technique and an audio processing technique. In this case, in the editing process, for example, data in which the number of repetitions in the video data exceeds a predetermined number, data of a portion where the volume increases, data having a certain characteristic, video data of a specific person by face recognition, etc. Extraction is performed based on a change or break in sound, a telop of video data, and the like.
The editing process may be a process of converting video data into data corresponding to the output device, such as changing the number of pixels and resolution.
Further, the editing process may be a process for realizing a user interface such as extracting feature points from video data and performing input control based on a user gesture included in the video data.
In the present embodiment, for example, decoding of compressed video data of terrestrial digital broadcasting, decoding of compressed video data of BS high-definition broadcasting, decoding of compressed video data stored in a recording medium such as a DVD or a hard disk, etc. Such a fixed process (a possibility of being changed, a process whose frequency is lower than a certain level) is executed by hardware.
On the contrary, in the present embodiment, for example, encoding itself is performed according to a certain processing content, but the main processing content is such as processing in which part of the processing content changes depending on the output destination. Even if the processing is fixed, processing that partially changes depending on the application is executed using software by one of the processor elements 20a to 20d. More specifically, for example, to encode to H.264 and save to HDD / HD or DVD, for example, to execute encoding to mpeg2 and save to DVD, for example, to reduce capacity The process of executing bit rate conversion to mpeg2, the process of executing encoding to mpeg4 and storing it in, for example, a portable game machine or a portable music player, are realized by the operation of a processor element based on software.
Similarly, editing processing such as face recognition processing, feature point extraction, sound recognition, and telop (character) recognition is executed using software by any processor element.
The multiprocessor 17 according to the present embodiment does not have a video output function but uses a chipset function. Since the multiprocessor 17 does not include a texture unit or rasterizer for processing computer graphics, the chip area can be made smaller than that of the GPU. By using the multiprocessor 17, it is not necessary to use a GPU for the transcodec, and the GPU can perform the original processing of the GPU, thereby increasing the cost-effectiveness of the chip.
In the present embodiment, a memory controller 22 that controls the external memory chip 28 and a memory / processor control connection unit 34 that controls the external memory chip 32 incorporate a device that performs encryption, and addresses and data are encrypted. The The memory controller 22 and the memory / processor control connection unit 34 shuffle the address and data required from within the chip, and send the shuffled address and the shuffled data between the external memory chips 28 and 32. Communicate with. As a result, even if illegal data acquisition or falsification is attempted for the external memory chips 28 and 32, the data obtained by the illegal data acquisition or falsification is meaningless information, and the contents of the data Can be protected.
In the present embodiment, a modification of the multiprocessor 17 according to the second embodiment will be described.
FIG. 9 is a block diagram showing an example of a multiprocessor provided with the memory security device according to the present embodiment.
The multiprocessor 39 is substantially the same as the multiprocessor 17 shown in FIG. 7 except that the multiprocessor 39 further includes a hardware encoder 40.
In the multiprocessor 39, the operation from when the general-purpose bus interface 21 receives the compressed video data 29a until the memory 28 stores the decoded video data 29b is the same as that of the multiprocessor 17 according to the second embodiment. It is.
In the multiprocessor 39, the control processor 23 controls at least one of the plurality of processor elements 20a to 20d. At least one of the plurality of processor elements 20a to 20d accesses the editing software 29d stored in the memory 28, acquires the decoded video data 29b stored in the memory 28, and edits the editing software 29d. The video data 29b decoded by the operation based on the above is edited, and the edited data is transferred to the hardware encoder 40.
Next, the control processor 23 controls the hardware encoding unit 40. The hardware encoder 40 encodes the edited data and stores the compressed video data 29c obtained by the encoding in the memory 28.
Then, the control processor 23 controls the data transfer unit 24. The data transfer unit 24 transmits the compressed video data 29c stored in the memory 28 from the general-purpose bus interface 21 to the outside.
In the multiprocessor 39 according to the present embodiment described above, encoding is also executed by hardware. By using the multiprocessor 39 according to the present embodiment, the same effects as those of the second embodiment can be obtained. The multiprocessor 39 is suitable for the case where the encoding is a fixed process as well as the decoding, and the processing speed can be improved.
In each of the above embodiments, the case where the data handled by the multiprocessors 17 and 39 and the computer system 30 is video data has been described as an example, but other data can be similarly applied.
The multiprocessors 17 and 39 are not only applied to the computer system 30 such as a personal computer, but may be provided in a device such as a DVD recorder.
The multiprocessors 17 and 39 according to each of the above embodiments may temporarily store the edit data in a memory and perform the encoding by accessing the edit data stored in the memory.
In the multiprocessors 17 and 39 according to the above embodiments, the operations of the control processor 23, the data transfer unit 24, and the memory security device 1 may also be realized by a processor element.
1 is a block diagram showing an example of a memory security device according to a first embodiment of the present invention. The block diagram which shows an example of the state which restrict | limits the access to a memory from a host with a device. The block diagram which shows an example of the state which cancels | releases access restrictions using a crack code. The block diagram which shows an example of the state by which data is protected by the memory security apparatus concerning 1st Embodiment. The figure which shows an example of the shuffle process with respect to the address by the memory security apparatus concerning 1st Embodiment. The figure which shows an example of the shuffle process with respect to the write data by the memory security apparatus concerning 1st Embodiment. The block diagram which shows an example of the multiprocessor provided with the memory security apparatus which concerns on the 2nd Embodiment of this invention. The block diagram which shows the example of application of the multiprocessor which concerns on 2nd Embodiment. The block diagram which shows an example of the multiprocessor provided with the memory security apparatus which concerns on the 3rd Embodiment of this invention.
DESCRIPTION OF SYMBOLS 1 ... Memory security apparatus, 2 ... Random number generation part, 3 ... Random number memory | storage part, 4 ... Address encryption part, 5 ... Data encryption part, 6 ... Write part, 7 ... Read part, 8 ... Data decryption part, 9 32, memory, 10, 13 ... device, 11 ... serial connection, 12 ... host device, 17, 39 ... multiprocessor, 18, 19 ... hardware decoding unit, 20a-20d ... processor element, 21 ... general purpose bus interface, 22 ... Memory controller, 23 ... Control processor, 24 ... Data transfer unit, 25 ... Internal bus, 26 ... External device, 27, 37a-37d ... Bus, 28 ... Memory, 29a ... Compressed video data, 29b, 38 ... Decoded Video data, 29c ... compressed video data, 29d ... editing software, 29e ... encoding software, 30 Computer system, 31 ... CPU, 31a, 33a ... decoding function, 33 ... GPU, 34 ... memory / processor control connector, 35 ... I / O control connector, 40 ... hardware encoding unit
An address encryption unit that encrypts a write destination address to create an encrypted write destination address when writing data, and encrypts a read destination address to create an encrypted read destination address when reading data;
A data encryption means for encrypting write data for a write destination address to create encrypted write data;
Writing means for writing the encrypted write data into a memory according to the encrypted write destination address;
Read means for reading encrypted read data from the memory according to the encrypted read destination address;
A memory security device comprising: data decrypting means for decrypting the encrypted read data to create read data for the read destination address.
The memory security device of claim 1, wherein
Random number generation means;
Random number storage means for storing a random number generated by the random number generation means,
The address encryption unit creates the encrypted write destination address based on the random number stored in the random number storage unit when writing data, and stores the random number stored in the random number storage unit when reading data Create the encrypted read destination address based on
The data encryption unit creates the encrypted read data based on the random number stored in the random number storage unit,
The memory security device, wherein the data decryption unit creates the read data based on the random number stored in the random number storage unit.
The memory security device of claim 2, wherein
The address encryption means creates an encrypted write destination address by performing an exclusive OR operation on the random number and the write destination address stored in the random number storage means when writing data. When the data is read, an exclusive OR operation is performed on the random number stored in the random number storage unit and the read destination address to create the encrypted read destination address,
The data encryption unit performs an exclusive OR operation on the random number and the write data stored in the random number storage unit to create the encrypted write data,
The data decryption unit performs an exclusive OR operation on the random number stored in the random number storage unit and the encrypted read data to create the read data. Memory security device.
The memory security device according to claim 2 or claim 3,
The random number generated by the random number generator includes an address random number and a data random number,
The address encryption means creates the encrypted write destination address based on the address random number when writing data, and creates the encrypted read destination address based on the address random number when reading data,
The data encryption means creates the encrypted read data based on the data random number,
The memory security device, wherein the data decryption means creates the read data based on the data random number.
JP2007145265A 2007-05-31 2007-05-31 Memory security device Withdrawn JP2008299611A (en)
JP2007145265A JP2008299611A (en) 2007-05-31 2007-05-31 Memory security device
US12/128,322 US20080301467A1 (en) 2007-05-31 2008-05-28 Memory Security Device
JP2008299611A true JP2008299611A (en) 2008-12-11
ID=40089624
JP2007145265A Withdrawn JP2008299611A (en) 2007-05-31 2007-05-31 Memory security device
US (1) US20080301467A1 (en)
JP (1) JP2008299611A (en)
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2007-05-31 JP JP2007145265A patent/JP2008299611A/en not_active Withdrawn
2008-05-28 US US12/128,322 patent/US20080301467A1/en not_active Abandoned
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2011-09-06 A761 Written withdrawal of application