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Patent US20040222749 - Light emitting device and electronic appliance - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThe present invention is to provide a light emitting device capable of obtaining a certain luminance without influence by the temperature change, and a driving method thereof. A current mirror circuit formed by using a transistor is provided for each pixel. The first transistor and the second transistor...http://www.google.com/patents/US20040222749?utm_source=gb-gplus-sharePatent US20040222749 - Light emitting device and electronic applianceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20040222749 A1Publication typeApplicationApplication numberUS 10/858,387Publication dateNov 11, 2004Filing dateJun 2, 2004Priority dateFeb 21, 2001Also published asUS6753654, US7336035, US7719498, US8120557, US8780018, US9040996, US9431466, US20020180369, US20080197777, US20100201721, US20120146887, US20150034922, US20150333113, US20160358542Publication number10858387, 858387, US 2004/0222749 A1, US 2004/222749 A1, US 20040222749 A1, US 20040222749A1, US 2004222749 A1, US 2004222749A1, US-A1-20040222749, US-A1-2004222749, US2004/0222749A1, US2004/222749A1, US20040222749 A1, US20040222749A1, US2004222749 A1, US2004222749A1InventorsJun KoyamaOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd. A Japan CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (18), Referenced by (25), Classifications (42), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetLight emitting device and electronic appliance
[0075] In the formula 1, all of μ, Co, W/L, and VTH are a fixed value determined by each transistor. Moreover, the drain current I1 of the transistor TR1 is maintained at constant Ic by the constant current source 107. Therefore, as it is apparent from the formula 1, the gate voltage VGS of the transistor Tr1 is determined by the current value Ic. [0076] The gate electrode of the transistor Tr2 is connected with the gate electrode of the transistor Tr1. Moreover, the source area of the transistor Tr2 is connected with the source area of the transistor Tr1. As a result, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2. Therefore, the drain current 12 of the transistor Tr2 is maintained in the same size as the drain current of the transistor Tr1. That is, I2=Ic. [0077] The drain current I2 of the transistor Tr2 flows into the OLED 104. Therefore, the OLED driving current has the same size as that of the constant current Ic determined in the constant current source 107. [0078] The OLED 104 emits a light by a luminance corresponding to the size of the OLED driving current. In the case the OLED driving current is extremely close to 0, or the OLED driving current flows in the counter bias direction, the OLED 104 does not emit a light. [0079] When selection of all the scanning lines G1 to Gy is finished, and the above-mentioned operation is executed for pixels in all the lines, the wiring period Ta is finished. When the writing period Ta is finished, the display period Td is started. [0080] [0080]FIG. 3B is a timing chart for a scanning line in the display period Td. In the display period Td, none of the scanning lines Gl to Gy is selected. [0081] [0081]FIG. 4B is a schematic diagram of a pixel in the display period Td. The transistor Tr3 and the transistor Tr4 are in the off state. Moreover, the source area of the transistor Tr3 and the transistor Tr4 are connected with the power source line Vi so as to be maintained at a constant potential (power source potential). [0082] In the display period Td, the drain area of the transistor Tr1 is in the so-called floating state without supply of a potential from another wiring, a power source, or the like. In contrast, in the transistor Tr2, VGS determined in the writing period Ta is maintained as it is. Therefore, the drain current I2 value of the transistor Tr2 is still maintained at Ic. Therefore, in the display period Td, the OLED 104 emits a light by a luminance corresponding to the size of the OLED driving current determined in the writing period Ta. [0083] In the case of a driving method using an analog video signal (analog driving method), the Ic size is determined according to the analog video signal so that the OLED 104 emits a light by a luminance corresponding to the size of the IC so as to display a gradient. In this case, the frame period comprising a writing period Ta and a display period Td so that an image is displayed in the frame period. [0084] [0084]FIG. 5 shows an example of a timing chart in the analog driving method. One period has y sets of line periods. In each line period, each scanning line is selected. In each line period, a constant current IC (Ic1 to Icx) flows in each signal line. [0085] In FIG. 5, the signal current value flowing in each signal line in the line period Lj (j=1 to y) is represented as Ic1 [Lj] to Icx [Lj]. [0086] The timing of starting the writing period Ta and the display period Td differs in each line so that the timings of appearance of the writing period of each line do not coincide. When the display period Td is finished in all the pixels, an image is displayed. [0087] In contrast, in the case of a time gradient driving method using a digital video signal (digital driving method), an image can be displayed by repeated appearance of the writing period Ta and the display period Td in one frame period. In the case of displaying an image by an n bit video signal, at least n sets of the writing periods and n sets of the display periods are provided in one frame period. N sets of the writing periods (Ta1 to Tan) and n sets of the display periods (Td1 to Tdn) correspond to each bit of the video signal. [0088] [0088]FIG. 6 shows the timing of appearance of n sets of the writing periods (Ta1 to Tan) and n sets of the display periods (Td1 to Tdn) in one frame period. The lateral axis represents the time and the vertical axis represents the position of the scanning line of the pixel. [0089] After the writing period Tam (m is an optional number from 1 to n), the display period corresponding to the same bit number, in this case, Tdm appears. Total of the writing period Ta and the display period Td is called a sub frame period SF. The sub frame period having the writing period Tam and the display period Tdm corresponding to the m-th bit is SFm. [0090] The length of the sub frame periods SF1 to SFn satisfies SF1: SF2: . . . : SFn=20: 21: . . . : 2n−1. [0091] For improvement of the image quality in display, a sub frame period with a long display period may be divided in some. Since a specific dividing method is disclosed in Japanese Patent Laid Open Application (JP-A) No. 2000-267164, it can be referred to. [0092] In the driving method shown in FIG. 6, the gradient is displayed by controlling the sum of the display period length with light emission in one frame period. [0093] In the present invention, according to the above-mentioned configuration, decline of the luminance of the OLED can be restrained even in the case the organic light emitting layer is deteriorated, and as a result, a sharp image can be displayed. Moreover, in the case of a color display light emitting device using an OLED corresponding to each color, a desired color can be displayed by preventing collapse of the luminance balance of each color even in the case the organic light emitting layers of the OLED are deteriorated by different rates per each corresponding color. [0094] Moreover, even in the case the temperature of the organic light emitting layer is influenced by the external atmosphere temperature, the heat generated by the OLED panel itself, or the like, the OLED driving current can be controlled at a desired value. Therefore, since the OLED driving current and the OLED luminance are proportional, change of the OLED luminance can be restrained as well as increase of the current consumption according to the temperature rise can be prevented. Moreover, in the case of the color display light emitting device, since the luminance change of the OLED of each color can be restrained without influence by the temperature change, collapse of the luminance balance of each color can be prevented, and thus a desired color can be displayed. [0095] Furthermore, since the OLED driving current change degree by the temperature in general differs depending on the kind of the organic light emitting material, the OLED luminance of each color in the color display may be changed independently by the temperature. However, according to the light emitting device of the present invention, since a desired luminance can be obtained without influence by the temperature change, collapse of the luminance balance of each color can be prevented so that a desired color can be displayed. [0096] Moreover, since the wiring for supplying a current to each pixel itself has a resistance in a common light emitting device, the potential thereof is slightly lowered depending on the wiring length. The potential decline differs largely also by the image to be displayed. In particular, in the case the ratio of pixels with a high gradient number is large in a plurality of the pixels having a current supplied from the same wiring, the current flowing in the wiring becomes large so that the potential decline appears significantly. Since the voltage on each OLED of each pixel becomes small in the case of the potential decline, the current supplied to each pixel becomes small. Therefore, even if a constant gradient is to be displayed in a predetermined pixel, if the gradient number of the other pixel having the current supplied from the same wiring is changed, the current supplied to the predetermined pixel is changed accordingly, and consequently, the gradient number is changed as well. However, according to the light emitting device of the present invention, since the OLED current can be corrected by obtaining the measured value and the reference value for each image to be displayed, a desired gradient number can be displayed by correction even in the case the image to be displayed is changed. [0097] Embodiment 2 [0098] In this embodiment, a configuration of the pixel 101 shown in FIG. 1 different from that of FIG. 2 will be explained. [0099] [0099]FIG. 7 shows the configuration of the pixel of this embodiment. The pixel 101 shown in FIG. 7 has a signal line Si (one from Sl to Sx), a scanning line Gj (one from G1 to Gy), and a power source line Vi (one from V1 to Vx). [0100] Moreover, the pixel 101 comprises at least a transistor Tr1 (first current driving transistor), a transistor Tr2 (second current driving transistor), a transistor Tr3 (first switching transistor), a transistor Tr4 (second switching transistor), an OLED 104 and a maintaining capacity 105. [0101] The gate electrodes of the transistor Tr3 and the transistor Tr4 are both connected with the scanning line Gj. [0102] One of the source area and the drain area of the transistor Tr3 is connected with the signal line Si, and the other one is connected with the drain area of the transistor Tr1. Moreover, one of the source area and the drain area of the transistor Tr4 is connected with the drain area of the transistor Tr1, and the other one is connected with the gate electrode of the transistor Tr1. [0103] The gate electrodes of the transistor Tr1 and the transistor Tr2 are connected with each other. Moreover, the source areas of the transistor Tr1 and the transistor Tr2 are both connected with the power source line Vi. [0104] The drain area of the transistor Tr2 is connected with a pixel electrode of the OLED 104. The potential of the power source line Vi (power source potential) is maintained at a constant level. Moreover, the potential of the counter electrode is maintained at a constant level as well. [0105] The transistor Tr3 and the transistor Tr4 may either be an n channel type TFT or a p channel type TFT. However, the polarity of the transistor Tr3 and the transistor Tr4 is same. [0106] Moreover, the transistor Tr1 and the transistor Tr2 may either be an n channel type TFT or a p channel type TFT. However, the polarity of the transistor Tr1 and the transistor Tr2 is same. In the case the anode is used as the pixel electrode and the cathode is used as the counter electrode, it is preferable that the transistor Tr1 and the transistor Tr2 are used as the p channel type TFT. In contrast, in the case the anode is used as the counter electrode and the cathode is used as the pixel electrode, it is preferable that the transistor Tr1 and the transistor Tr2 are used as the n channel type TFT. [0107] The maintaining capacity 105 is formed between the gate electrodes of the transistor Tr1 and the transistor Tr2 and the power source line Vi. Although the maintaining capacity 105 is provided for maintaining more securely the voltage (gate voltage) between the gate electrodes of the transistor Tr1 and the transistor Tr2 and the source area, it is not always necessarily provided. [0108] The operation of the light emitting device having the pixel shown in FIG. 7 can be explained for the writing period Ta and the display period Td as in the case of the pixel shown in FIG. 2. Furthermore, since the operation of the pixel in the writing period Ta and the display period Td is same as the case of the pixel shown in FIG. 2 so that the explanation for FIG. 3 and FIG. 4 in the first embodiment can be referred to, explanation is not given here. [0109] Embodiment 3 [0110] In this embodiment, a configuration of the pixel 101 shown in FIG. 1 different from that of FIG. 2 and FIG. 7 will be explained. [0111] [0111]FIG. 8 shows the configuration of the pixel of this embodiment. The pixel 101 shown in FIG. 8 has a signal line Si (one from S1 to Sx), a scanning line Gj (one from G1 to Gy), and a power source line Vi (one from V1 to Vx). [0112] Moreover, the pixel 101 comprises at least a transistor Tr1 (first current driving transistor), a transistor Tr2 (second current driving transistor), a transistor Tr3 (first switching transistor), a transistor Tr4 (second switching transistor), an OLED 104 and a maintaining capacity 105. [0113] The gate electrodes of the transistor Tr3 and the transistor Tr4 are both connected with the scanning line Gj. [0114] One of the source area and the drain area of the transistor Tr3 is connected with the signal line Si, and the other one is connected with the gate electrode of the transistor Tr1. Moreover, one of the source area and the drain area of the transistor Tr4 is connected with the drain area of the transistor Tr1, and the other one is connected with the gate electrode of the transistor Tr1. [0115] The gate electrodes of the transistor Tr1 and the transistor Tr2 are connected with each other. Moreover, the source areas of the transistor Tr1 and the transistor Tr2 are both connected with the power source line Vi. [0116] The drain area of the transistor Tr2 is connected with a pixel electrode of the OLED 104. The potential of the power source line Vi (power source potential) is maintained at a constant level. Moreover, the potential of the counter electrode is maintained at a constant level as well. [0117] The transistor Tr3 and the transistor Tr4 may either be an n channel type TFT or a p channel type TFT. However, the polarity of the transistor Tr3 and the transistor Tr4 is same. [0118] Moreover, the transistor Tr1 and the transistor Tr2 may either be an n channel type TFT or a p channel type TFT. However, the polarity of the transistor Tr1 and the transistor Tr2 is same. In the case the anode is used as the pixel electrode and the cathode is used as the counter electrode, it is preferable that the transistor Tr1 and the transistor Tr2 are used as the p channel type TFT. In contrast, in the case the anode is used as the counter electrode and the cathode is used as the pixel electrode, it is preferable that the transistor Tr1 and the transistor Tr2 are used as the n channel type TFT. [0119] The maintaining capacity 105 is formed between the gate electrodes of the transistor Tr1 and the transistor Tr2 and the power source line Vi. Although the maintaining capacity 105 is provided for maintaining more securely the voltage (gate voltage) between the gate electrodes of the transistor Tr1 and the transistor Tr2 and the source area, it is not always necessarily provided. [0120] The operation of the light emitting device having the pixel shown in FIG. 8 can be explained for the writing period Ta and the display period Td as in the case of the pixel shown in FIG. 2. Furthermore, since the operation of the pixel in the writing period Ta and the display period Td is same as the case of the pixel shown in FIG. 2 so that the explanation for FIG. 3 and FIG. 4 in the first embodiment can be referred to, explanation is not given here. EXAMPLES [0121] Hereinafter, examples of the present invention will be explained. Example 1 [0122] An example of a production method for a light emitting device according to the present invention will be explained with reference to FIGS. 9 to 13. Here, a method for simultaneously producing the transistor Tr2 and the transistor Tr4 shown in FIG. 2 and the TFT of the driving part provided in the periphery of the pixel part will be explained in detail in according to the steps as the representative. The transistor Tr1 and the transistor Tr3 can also be produced according to the production method for the transistor Tr2 and the transistor Tr4. Moreover, the pixel shown in FIGS. 7, 8 and 30 can also be produced by the production steps shown in this example. [0123] First, in this example, a substrate 900 made of a glass, such as a barium borosilicate glass, and an alumino borocilicate glass represented by #7059 glass and #1737 glass of Corning Incorporated, was used. As the substrate 900, any substrate having a light transmittivity can be used so that a quarts substrate may be used as well. Moreover, a plastic substrate having a heat resistance durable in a process temperature of this example can be used as well. [0124] Next, as shown in FIG. 9A, a base film 901 comprising an insulated film, such as a silicon oxide film, a silicon nitride film, and a silicon nitride oxide film was formed on the substrate 900. Although a two layer structure was employed as the base film 901 in this example, a single layer film of the above-mentioned insulated film, or a structure with two or more layers laminated can be used as well. As the first layer of the base film 901, a silicon nitride oxide film 901 a produced by a plasma CVD method using an SiH4, an NH3, and an N2O as the reaction gas, was formed by 10 to 200 nm (preferably 50 to 100 nm). In this example, the silicon nitride oxide film 901 a of a 50 nm film thickness (composition ratio Si=32%, 0=27%, N=24%, H=17%) was formed. Next, as the second layer of the base film 901, a silicon nitride oxide film 901 b produced by a plasma CVD method using an SiH4, and an N2O as the reaction gas, was formed by 50 to 200 nm (preferably 100 to 150 nm). In this example, the silicon nitride oxide film 901 b of a 100 nm film thickness (composition ratio Si=32%, O=59%, N=7%, H=2%) was formed. [0125] Next, semiconductor layers 902 to 905 were formed on the base film 901. The semiconductor layers 902 to 905 were formed by patterning into a desired shape a crystalline semiconductor film obtained by producing a semiconductor film having an amorphous structure by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like), and executing a known crystallization process (a laser crystallization method, a thermal crystallization method, a thermal crystallization method using a catalyst such as a nickel). The semiconductor layers 902 to 905 are formed by a 25 to 80 nm (preferably 30 to 60 nm) thickness. The material for the crystalline semiconductor films is not particularly limited, but it is formed preferably with a silicon or a silicon germanium (SixGe1-X (X=0.0001 to 0.02)) alloy. In this example, after forming a 55 nm amorphous silicon film using the plasma CVD method, a solution containing a nickel is maintained on the amorphous silicon film. After executing dehydration (500° C., 1 hour) to the amorphous silicon film, a thermal crystallization (550° C., 4 hours) was executed, and further, a laser annealing process was executed for improving the crystallization was executed for forming a crystalline silicon film. According to a patterning process of the crystalline silicon film using a photolithography method, the semiconductor layers 902 to 905 were formed. [0126] Moreover, it is also possible to dope a slight amount of an impurity element (boron or phosphorus) to the semiconductor layers 902 to 905 after formation of the semiconductor layers 902 to 905 for controlling the threshold value of the TFT. [0127] Moreover, in the case of producing a crystalline semiconductor film by the laser crystallization method, a pulse oscillation type or continuous light emitting type excimer laser, an YAG laser, or an YVO4 laser can be used. In the case of using these lasers, it is preferable to use a method of linearly collecting a laser beam outputted from a laser oscillator by an optical system and directing the same to the semiconductor films. The crystallization condition can be selected optionally by the operator, and in the case of using an excimer laser, the pulse oscillation frequency was set at 300 Hz, and the laser energy density was set at 100 to 400 mJ/cm2 (as the representative, 200 to 300 mJ/cm2). Furthermore, in the case of using an YAG laser, it is preferable to set the pulse oscillation frequency using the second harmonic at 30 to 300 kHz, and the laser energy density at 300 to 600 mJ/cm2 (as the representative, 350 to 500 mJ/cm2). Furthermore, it is preferable to direct a laser beam collected linearly in a 100 to 1,000 μm width, for example, 400 μm to the substrate entire surface, with an overlapping ratio of the linear laser beam at 50 to 90%. [0128] Next, a gate insulated film 906 for covering the semiconductor layers 902 to 905 was formed. The gate insulated film 906 was formed with an insulated film containing a silicon by a 40 to 150 nm thickness using the plasma CVD method or the sputtering method. In this example, a silicon nitride oxide film (composition ratio Si=32%, O=59%, N=7%, H=2%) was formed by a 110 nm thickness by the plasma CVD method. Of course the gate insulated film is not limited to the silicon nitride oxide film, and a single layer or a laminated structure of an insulated film containing another silicon can be adopted as well. [0129] Moreover, in the case a silicon oxide film is used, it can be used by mixing a TEOS (tetraethyl orthosilicate) and an O2 by the plasma CVD method, and executing electric discharge with a 40 Pa reaction pressure, a 300 to 400° C. substrate temperature, and a 0.5 to 0.8 W/cm2 high frequency (13.56 MHz) power density. According to the silicon oxide film accordingly produced, good characteristics as a gate insulated film can be obtained by thermal annealing at 400 to 500° C. thereafter. [0130] Then, a heat resistant conductive layer 907 for forming a gate electrode on the gate insulated film 906 was formed by a 200 to 400 nm (preferably 250 to 350 nm) thickness. The heat resistant conductive layer 907 can be formed in a single layer or as needed as a laminated structure comprising a plurality of layers such as two layers and three layers. The heat resistant conductive layer contains an element selected from the group consisting of a Ta, a Ti, and a W, an alloy containing the elements as a component, or an alloy film as a combination of the elements. The heat resistant conductive layer is formed by a sputtering method or a CVD method. In order to achieve a low resistance, it is preferable to reduce the concentration of a contained impurity. In particular, it is preferable to have the oxygen concentration of 30 ppm or less. In this example, the W film was formed by a 300 nm thickness. The W film can be formed by a sputtering method with a W used as a target, or it can be formed also by a method using a tungsten hexafluoride (WF6). In either case, in order to use as a gate electrode, a low resistance should be achieved, and it is preferable to have the W film resistivity at 20 μΩcm or less. Although a low resistivity can be achieved in the W film by enlarging the crystal grains, in the case a large amount of an impurity element such as an oxygen is contained in the W, the crystallization is prohibited so as to have a high resistivity. Thereby, in the case of the sputtering method, by forming the W film using a W target of a 99.9999% purity with sufficient attention paid for avoiding inclusion of impurities from the gas phase at the time of film formation, a 9 to 20 μΩcm resistivity can be realized. [0131] In contrast, in the case a Ta film is used for the heat resistant conductive layer 907, similarly, it can be formed by the sputtering method. For the Ta film, an Ar is used as the sputtering gas. Moreover, by adding an appropriate amount of a Xe or a Kr in the gas at the time of sputtering, peel off of the film can be prevented by alleviating the internal stress of the film to be formed. The resistivity of the Ta film of an a phase is about 20 μΩcm so that it can be used as the gate electrode, but the resistivity of the Ta film of a β phase is about 180μΩcm so that it cannot be suitable for the gate electrode. Since a TaN film has a crystal structure close to the a phase, by forming the TaN film as the base for the Ta film, the Ta film of the α phase can be obtained easily. Moreover, although it is not shown in the figure, it is effective to form a silicon film with a phosphorus (P) doped by about a 2 to 20 nm thickness below the heat resistant conductive layer 907. Thereby, improvement of the close contact property of the conductive film to be formed thereon and oxidation prevention can be achieved as well as diffusion of an alkaline metal element contained in the heat resistant conductive layer 907 by a slight amount to the gate insulated film 906 of the first shape can be prevented. In either case, it is preferable to have the resistivity of the heat resistant conductive layer 907 in a range of 10 to 50 μΩcm. [0132] Next, a mask 908 of a resist is formed using the photolithography technique. Then, the first etching process is executed. In this example, it is executed with a plasma formed by using an ICP etching device, a Cl2 and a CF4 as the etching gas, and introducing an RF (13.56 MHz) power of 3.2 W/cm2 by a 1 Pa pressure. By introducing the RF (13.56 MHz) power of 224 mW/cm2 also to the substrate side (specimen stage), a substantially negative self bias voltage is applied. In this condition, the W film etching rate is about 100 nm/min. For the first etching process, the time needed for just etching the W film was estimated based on the etching rate, and the etching time increased by 20% therefrom was set to be the etching time. [0133] By the first etching process, conductive layers 909 to 912 having the first tapered shape are formed. The conductive layers 909 to 912 were formed with the tapered part angle of 15 to 30°. In order to etch without leaving a residue, an over etching of increasing the etching time by a ratio of about 10 to 20% was applied. Since the selection ratio of the silicon nitride oxide film (gate insulated film 906) with respect to the W film is 2 to 4 (representatively 3), the surface with the silicon nitride oxide film exposed can be etched by about 20 to 50 nm by the over etching process (FIG. 9B). [0134] Then, by executing the first doping process, the one conductive type impurity element is added to the semiconductor layer. Here, an impurity element addition step for applying the n type was executed. With the mask 908 with the first shape conductive layer formed left as it is, impurity elements for providing the n type by self aligning were added using the conductive layers 909 to 912 having the first tapered shape by the ion doping method. In order to add the impurity elements for providing the n type reaching to the semiconductor layer through the tapered part at the end part of the gate electrode and the gate insulated film 906 disposed therebelow, the dose amount is set to be 1×1013 to 5×1014 atoms/cm2, and the acceleration voltage at 80 to 160 keV. As the impurity elements for providing the n type, elements belonging to the 15 group, typically a phosphorus (P) or an arsenic (As) can be used, but here a phosphorus was used. According to the ion doping method, in the first impurity areas 914 to 914, the impurity element for providing the n type was added in a concentration range of 1×1020 to 1×1021 atomic/cm3. (FIG. 9C) [0135] In this step, depending on the doping condition, the impurity may be placed below the first shape conductive layers 909 to 912 so that the first impurity areas 914 to 914 can be superimposed on the first shape conductive layers 909 to 912. [0136] Next, as shown in FIG. 9D, the second etching process is executed. Similarly, the etching process is executed with the ICP etching device using a gas mixture of a CF4 and a Cl2 as the etching gas, a 3.2 W/cm2 (13.56 MHz) RF power, a 45 mW/cm2 (13.56 MHz) bias power, and a 1.0 Pa pressure. Thereby, conductive layers 918 to 921 having the second shape formed by the condition can be provided. A tapered part is formed on the end part thereof, with a tapered shape with the thickness increased from the end part to inward. Compared with the first etching process, owing to a lower bias power applied to the substrate side, the ratio of the isotropic etching is increased so that the tapered part angle becomes 30 to 60°. The end part of the mask 908 is cut by etching so as to provide a mask 922. Moreover, in the step of FIG. 9D, the surface of the gate insulated film 906 is etched by about 40 nm. [0137] Then, the impurity element for providing the n type is doped with a dose amount smaller than that of the first doping process in a high acceleration voltage condition. For example, the operation is executed with a 70 to 120 KeV acceleration voltage and a 1×1013/cm2 dose amount so as to form the first impurity areas 924 to 927 having a larger impurity concentration and the second impurity areas 928 to 931 in contact with the first impurity areas 924 to 927. In this step, depending on the doping condition, the impurity may be placed below the second shape conductive layers 918 to 921 so that the second impurity areas 928 to 931 can be superimposed on the second shape conductive layers 918 to 921. The impurity concentration in the second impurity area is set to be 1×1016 to 1×1018 atoms/cm3. (FIG. 10A) [0138] Then, as shown in (FIG. 10B), impurity areas 933 (933 a, 933 b) and 934 (934 a, 934 b) of an opposite conductive type with respect to the one conductive type are formed in the semiconductor layers 902, 905 for forming the p channel type TFT. Also in this case, by adding an impurity element for providing the p type with the second shape conductive layers 918, 921 used as a mask, an impurity area is formed by self aligning. At the time, the semiconductor layers 903, 904 for forming the n channel type TFT has a resist mask 932 formed so as to cover the entire surface. The impurity areas 933, 934 formed here is formed by the ion doping method using a diborane (B2H6). The concentration of the impurity element for providing the p type of the impurity areas 933, 934 is set to be 2×1020 to 2×1021 atoms/cm3. [0139] However, the impurity areas 933, 934 can be regarded specifically as two areas containing the impurity element for providing the n type. The third impurity areas 933 a, 934 a contain the impurity element for providing the n type by a 1×1020 to 1×1021 atoms/cm3 concentration, and the fourth impurity areas 933 b, 934 b contain the impurity element for providing the n type by a 1×1017 to 1×1020 atoms/cm3 concentration. However, by having the concentration of the impurity element for providing the p type of the impurity areas 933 b, 934 b at 1×1019 atoms/cm3 or more, and having the concentration of the impurity element for providing the p type in the impurity areas 933 a, 934 a by 1.5 to 3 times as much as the concentration of the impurity element for providing the n type, any problem cannot be generated for the function as the source area and the drain area of the p channel type TFT in the third impurity area [0140] Thereafter, as shown in FIG. 10C, the first interlayer insulated film 937 is formed on the conductive layers 918 to 921 having the second shape and the gate insulated film 906. The first interlayer insulated film 937 can be formed with a silicon oxide film, a silicon nitride oxide film, a silicon nitride film, or a laminated film of a combination thereof. In either case, the first interlayer insulated film 937 is made of an inorganic insulated material. The film thickness of the first interlayer insulated film 937 is set to be 100 to 200 nm. In the case a silicon oxide film is used as the first interlayer insulated film 937, it can be formed by mixing a TEOS and an O2 are the plasma CVD method, and executing electric discharge with a 40 Pa reaction pressure, a 300 to 400° C. substrate temperature, and a 0.5 to 0.8 W/cm2 high frequency (13.56 MHz) power density. Moreover, in the case a silicon nitride oxide film is used as the first interlayer insulated film 937, a silicon nitride oxide film produced from an SiH4, an NH3, and an N2O, or a silicon nitride oxide film produced from an SiH4, and an N2O by the plasma CVD method can be used. As the production condition in this case, a 20 to 200 Pa reaction pressure, a 300 to 400° C. substrate temperature, and a 0.1 to 1.0 W/cm2 high frequency (60 MHz) power density can be provided. Moreover, as the first interlayer insulated film 937, a hydrogenated silicon nitride oxide film produced from an SiH4, an N2O, and an H2 can be adopted as well. Similarly, a silicon nitride film can be produced from an SiH4, and an NH3 as well. [0141] Then, a process for activating the impurity element for providing the n type or the p type added by each concentration is executed. This step is executed by the thermal annealing method using a furnace annealing furnace. In addition thereto, the laser annealing method, or a rapid thermal annealing method (RTA method) can be adopted as well. The thermal annealing method is executed in a nitrogen atmosphere of 1 ppm or less, preferably 0.1 ppm or less at 400 to 700° C., representatively 500 to 600° C. In this embodiment a heat treatment was executed at 550° C. for 4 hours. Moreover, in the case a plastic substrate having a low heat resistance temperature is used for the substrate 900, it is preferable to adopt the laser annealing method. [0142] Following the activation step, a step for hydrogenating the semiconductor layer by executing a heat treatment at 300 to 450° C. for 1 to 12 hours with the atmosphere gas changed to an atmosphere containing 3 to 100% of a hydrogen, is executed. This is a step for finishing the end of a dangling bond of 1016 to 1018/cm3 in the semiconductor layer by a thermally excited hydrogen. As another means for the hydrogenation, the plasma hydrogenation (using a hydrogen excited by a plasma) can be executed. In either case, it is preferable to have the defect density in the semiconductor layers 902 to 905 to 10 16/cm3 or less. Therefore, a hydrogen can be provided by about 0.01 to 0.1 atomic %. [0143] Then, the second interlayer insulated film 939 made of an organic insulated material is formed by a 1.0 to 2.0 μm average thickness. As the organic resin material, a polyimide, an acrylic, a polyamide, a polyimide amide, a BCB (benzocyclo butene), or the like can be used. For example, in the case a polyimide of a type thermally polymerizable after application on the substrate is used, it is formed by baking at 300° C. by a clean oven. Moreover, in the case an acrylic is used, it can be formed by using a two liquid type, mixing a main material and a hardener, applying the same on the substrate entire surface using a spinner, executing a preliminary heating operation at 80° C. for 60 seconds by a hot plate, and further baking at 250° C. for 60 minutes by a clean oven. [0144] By forming the second interlayer insulated film 939 accordingly with an organic insulated material, the surface can be preferably flat. Moreover, since the organic resin material in general has a low dielectric constant, the parasitic capacity can be reduced. However, since it has a moisture absorbing property and thus it is not suitable as a protection film, it can be used preferably in a combination with a silicon oxide film, a silicon nitride oxide film, a silicon nitride film, or the like formed as the first interlayer insulated film 937. [0145] Thereafter, a resist mask of a predetermined pattern is formed, and a contact hole reaching to the source area or the drain area formed in each semiconductor layer is formed. The contact hole is formed by the dry etching method. In this case, first the second interlayer insulated film 939 made of an organic resin material is etched using a gas mixture of a CF4, an O2, and an He as the etching gas, and then subsequently the first interlayer insulated film 937 is etched using a CF4, and O2 as the etching gas. Furthermore, in order to improve the selection ratio with respect to the semiconductor layer, a contact hole can be formed by etching the gate electrode 906 of the third shape with the etching gas changed to a CHF3. [0146] Then, source wirings 940 to 943 and drain wirings 944 to 946 are formed by forming a conductive metal film by the sputtering method or the vacuum deposition method, patterning with a mask, and etching. In this specification, both the source wirings and the drain wirings are referred to as connection wirings. Although it is not shown in the figure, in this specification, the connection wirings are formed as a laminated film of a Ti film of a 50 nm film thickness, and an alloy film (an alloy film of an Al and a Ti) of a 500 nm film thickness. [0147] Next, a pixel electrode 947 is formed by providing a transparent conductive film thereon by a 80 to 120 nm thickness, and patterning (FIG. A). In this example, an indium-tin oxide (ITO) film or a transparent conductive film having 2 to 20[%] of a zinc oxide (ZnO) added to an indium oxide is used as the transparent electrode. [0148] Moreover, the pixel electrode 947 can be connected electrically with the drain area of the transistor Tr2 by forming the same superimposed and connected with the drain wiring 946. [0149] [0149]FIG. 12 is a top view of the pixel at the time of finishing the step of FIG. 11A. In order to clarify the position of the wiring and the position of the semiconductor layer, the insulated films and the interlayer insulated films are omitted. The cross-sectional view taken on A-A′ in FIG. 12 corresponds with the part shown in A-A′ in FIG. 1A. [0150] [0150]FIG. 13 is a cross-sectional view taken on B-B′ in FIG. 12. The transistor Tr3 has a gate electrode 975 as a part of the scanning line 974, with the gate electrode 975 connected also with the gate electrode 920 of the transistor Tr4. Moreover, the impurity area 977 of the semiconductor layer of the transistor Tr3 is connected with a connection wiring 942 serving as the signal line on one side and with the connected with a connection wiring 971 on the other side. [0151] The transistor Tr1 has a gate electrode 976 as a part of the capacity wiring 973, with the gate electrode 976 connected also with the gate electrode 921 of the transistor Tr2. Moreover, the impurity area 978 of the semiconductor layer of the transistor Tr1 is connected with a connection wiring 971 on one side and with the connected with a connection wiring 943 serving as the power source line Vi on the other side. [0152] The connection wiring 943 is connected also with the impurity area 934 a of the transistor Tr2. Moreover, the numeral 970 is a maintaining capacity, having the semiconductor layer 972, the gate insulated film, 906 and the capacity wiring 973. The impurity area 979 of the semiconductor layer 972 is connected with the connection wiring 943. [0153] Next, as shown in FIG. 11B, the third interlayer insulated film 949 having an opening part at a position corresponding to the pixel electrode 947 is formed. The third interlayer insulated film 949 having the insulation property serves as a bank so as to play a roll of separating the organic light emitting layers of the adjacent pixels. In this example, the third interlayer insulated film 949 is formed using a resist. [0154] In this example, the thickness of the third interlayer insulated film 949 is provided by about 1 μm, with the opening part formed in the so-called reverse tapered shape, widened toward the pixel electrode 947. This can be formed by covering except the part for forming the opening part after film formation of the resist, exposing the same by directing the UV light, and eliminating the exposed part by a developer. [0155] Since the organic light emitting layers are divided for the adjacent pixels at the time of film formation of the organic light emitting layers in the following step by having the third insulated film 949 in the reverse tapered shape as in this example, even in the case the coefficients of thermal expansion of the organic light emitting layers and the third interlayer insulated film 949 are different, cracking or peel off of the organic light emitting layer can be restrained. [0156] Although a resist film is used as the third interlayer insulated film in this example, in some cases, a polyimide, a polyamide, an acrylic, a BCB (benzocyclo butene), a silicon oxide film, or the like can be used as well. As long as it has the insulation property, either organic or inorganic third interlayer insulated film 949 can be used. [0157] Next, an organic light emitting layer 950 is formed by the deposition method, and further, a cathode (MgAg electrode) 951 and a protection electrode 952 are formed by the deposition method. At the time, it is preferable to apply a heat treatment to the pixel electrode 947 for completely eliminating the moisture content prior to the formation of the organic light emitting layer 950 and the cathode 951. Although the MgAg electrode is used as the OLED cathode in this example, another known material can be used as well. [0158] As the organic light emitting layer 950, a known material can be used. Although a two layer structure comprising a hole transporting layer and a light emitting layer is provided as the organic light emitting layer in this example, in some cases any of a hole injecting layer, an electron injecting layer, or an electron transporting layer is provided. Accordingly, various examples of combinations have already been reported, and any configuration can be used. [0159] In this example, a polyphenylene vinylene is formed as the hole transporting layer by the deposition method. Moreover, as the light emitting layer, one having 30 to 40% of a 1,3,4-oxadiazol derivative molecularly dispersed in a polyvinyl carbazol is formed by the deposition method, with about 1% of a coumarin 6 added as a green light emission center. [0160] Moreover, it is also possible to protect the organic light emitting layer 950 from the moisture content or the oxygen by the protection electrode 952, but it is further preferable to provide a protection film 953. IN this example, a 300 nm thickness silicon nitride film is provided as the protection film 953. The protection film can be formed continuously after the protection electrode 952 without release to the atmosphere. [0161] Moreover, the protection electrode 952 is provided for preventing deterioration of the cathode 951, and a metal film having an aluminum as the main component is representative thereof. Of course, another material can be used as well. Moreover, since the light emitting layer 950 and the cathode 951 are extremely weak to the moisture content, it is preferable to form continuously to the protection electrode 952 without release to the atmosphere for protecting the organic light emitting layer from the outside air. [0162] The film thickness of the organic light emitting layer 950 can be provided by 10 to 400 [nm] (typically 60 to 150 [nm]), and the thickness of the cathode 951 can be provided by 80 to 200 [nm] (typically 100 to 150 [nm]). [0163] Accordingly, a light emitting device having the structure shown in FIG. 11B can be completed. The part 954 with the pixel electrode 947, the organic light emitting layer 950, and the cathode 951 superimposed corresponds to the OLED. [0164] The p channel type TFT 960 and the n channel type TFT 961 are a TFT of the driving circuit, which provides a CMOS. The transistor Tr2 and the transistor Tr4 are a TFT of the pixel part, and the TFT of the driving circuit and the TFT of the pixel part can be formed on the same substrate. [0165] In the case of a light emitting device using an OLED, since the voltage of the power source of the driving circuit is sufficiently about 5 to 6V, and about 10V at most, a problem of deterioration by the hot electron in the TFT is not involved. Moreover, since the driving circuit needs to be operated at a high speed, it is preferable that the TFT gate capacity is small. Therefore, as in this example, a configuration with the second impurity area 929 of the semiconductor layer of the TFT and the fourth impurity area 933 b not superimposed with the gate electrodes, 918, 919 is preferable. [0166] The production method for a light emitting device according to the present invention is not limited to the production method explained in this example, and a light emitting device of the present invention can be produced using a known method. Example 2 [0167] In this example, a production method for a light emitting device, different from that of the example 1 will be explained. [0168] The steps to the formation of the second interlayer insulated film 939 are same as those in the example 5. As shown in FIG. 14A, a passivation film 981 is formed in contact with the second interlayer film 939 after formation of the second interlayer insulated film 981. [0169] The passivation film 981 is effective for preventing entrance of the moisture content contained in the second interlayer insulated film 939 to the organic light emitting layer 950 via the pixel electrode 947 or the third interlayer insulated film 982. In the case the second interlayer insulated film 939 includes an organic resin material, since the organic resin material contains a large amount of the moisture content, it is particularly effective to provide the passivation film 981. [0170] In this example, as the passivation film 981, a silicon nitride film was used. [0171] Thereafter, a resist mask of a predetermined pattern is formed, and a contact hole etching to the source area or the drain area formed in each semiconductor layer is formed. The contact hole is formed by the dry etching method. In this case, first the passivation film 981 is etched using a gas mixture of a CF4 and O2 as the etching gas, next the second interlayer insulated film 939 made of an organic resin material is etched using a gas mixture of a CF4, an O2, and an He as the etching gas, and then subsequently the first interlayer insulated film 937 is etched using a CF4, and O2 as the etching gas. Furthermore, in order to improve the selection ratio with respect to the semiconductor layer, a contact hole can be formed by etching the gate electrode 906 of the third shape with the etching gas changed to a CHF3. [0172] Then, source wirings 940 to 943 and drain wirings 944 to 946 are formed by forming a conductive metal film by the sputtering method or the vacuum deposition method, patterning with a mask, and etching. Although it is not shown in the figure, in this specification, the connection wirings are formed as a laminated film of a Ti film of a 50 nm film thickness, and an alloy film (an alloy film of an Al and a Ti) of a 500 nm film thickness. [0173] Next, a pixel electrode 947 is formed by providing a transparent conductive film thereon by a 80 to 120 nm thickness, and patterning (FIG. 14A). In this example, an indium-tin oxide (ITO) film or a transparent conductive film having 2 to 20[%] of a zinc oxide (ZnO) added to an indium oxide is used as the transparent electrode. [0174] Moreover, the pixel electrode 947 can be connected electrically with the drain area of the transistor Tr2 by forming the same superimposed and connected with the drain wiring 946. [0175] Next, as shown in FIG. 14B, the third interlayer insulated film 982 having an opening part at a position corresponding to the pixel electrode 947 is formed. In this example, a side wall of a tapered shape was provided by using the wet etching method at the time of forming the opening part. Unlike the case of the example 1, since the organic light emitting layer formed on the third interlayer insulated film 982 is not divided, deterioration of the organic light emitting layer derived from a grade difference can involve a significant problem unless the side wall of the opening part is sufficiently smooth, attention should be paid thereto. [0176] In this example, as the third interlayer insulated film 982, in some cases, an organic resin film made of a polyimide, a polyamide, an acrylic, BCB (benzocyclo butene), or the like can be used as well. [0177] It is preferable to have the surface of the third interlayer insulated film 982 densed by applying a plasma process using an argon on the surface of the third interlayer insulated film 982 before forming the organic light emitting layer on the third interlayer insulated film 982. According to the above-mentioned configuration, entrance of the moisture content from the third interlayer insulated film 982 to the organic light emitting layer 950 can be prevented. [0178] Next, an organic light emitting layer 950 is formed by the deposition method, and further, a cathode (MgAg electrode) 951 and a protection electrode 952 are formed by the deposition method. At the time, it is preferable to apply a heat treatment to the pixel electrode 947 for completely eliminating the moisture content prior to the formation of the organic light emitting layer 950 and the cathode 951. Although the MgAg electrode is used as the OLED cathode in this example, another known material can be used as well. [0179] As the organic light emitting layer 950, a known material can be used. Although a two layer structure comprising a hole transporting layer and a light emitting layer is provided as the organic light emitting layer in this example, in some cases any of a hole injecting layer, an electron injecting layer, or an electron transporting layer is provided. Accordingly, various examples of combinations have already been reported, and any configuration can be used. [0180] In this example, a polyphenylene vinylene is formed as the hole transporting layer by the deposition method. Moreover, as the light emitting layer, one having 30 to 40% of a 1, 3, 4-oxadiazol derivative molecularly dispersed in a polyvinyl carbazol is formed by the deposition method, with about 1% of a coumarin 6 added as a green light emission center. [0181] Moreover, it is also possible to protect the organic light emitting layer 950 from the moisture content or the oxygen by the protection electrode 952, but it is further preferable to provide a protection film 953. IN this example, a 300 nm thickness silicon nitride film is provided as the protection film 953. The protection film can be formed continuously without release to the atmosphere after the protection electrode 952. [0182] Moreover, the protection electrode 952 is provided for preventing deterioration of the cathode 951, and a metal film having an aluminum as the main component is representative thereof. Of course, another material can be used as well. Moreover, since the light emitting layer 950 and the cathode 951 are extremely weak to the moisture content, it is preferable to form continuously to the protection electrode 952 without release to the atmosphere for protecting the organic light emitting layer from the outside air. [0183] The film thickness of the organic light emitting layer 950 can be provided by 10 to 400 [nm] (typically 60 to 150 [nm]), and the thickness of the cathode 951 can be provided by 80 to 200 [nm] (typically 100 to 150 [nm]). [0184] Accordingly, a light emitting device having the structure shown in FIG. 14B can be completed. The part 954 with the pixel electrode 947, the organic light emitting layer 950, and the cathode 951 superimposed corresponds to the OLED. [0185] The p channel type TFT 960 and the n channel type TFT 961 are a TFT of the driving circuit, which provides a CMOS. The transistor Tr2 and the transistor Tr4 are a TFT of the pixel part, and the TFT of the driving circuit and the TFT of the pixel part can be formed on the same substrate. [0186] The production method for a light emitting device according to the present invention is not limited to the production method explained in this example, and a light emitting device of the present invention can be produced using a known method. Example 3 [0187] In this example, a top view of the pixel shown in FIG. 7 will be explained. FIG. 15 is a top view of the pixel of this example. In order to clarify the position of the wiring and the position of the semiconductor layer, the insulated films such as the interlayer insulated films and the gate insulated films are omitted. Moreover, the wirings formed in the same layer are shown by the same hatching. Furthermore, FIG. 15 corresponds to a top view of the pixel after formation of the pixel electrode and before formation of the organic light emitting layer. [0188] The pixel shown in FIG. 15 has each one set of a scanning line 211, a signal line 210, and a power source line 217. Then, parts 212, 213 of the scanning line 211 each correspond to the gate electrodes of the transistor Tr3 and the transistor Tr4. [0189] One of the source area and the drain area of the transistor Tr3 is connected with the signal line 210, and the other one is connected with the drain area of the transistor Tr1 via the connection wiring 215. Moreover, one of the source area and the drain area of the transistor Tr4 is connected with the drain area of the transistor Tr1 via the connection wiring 215, and the other one is connected with the capacity wiring 216 via the connection wiring 214. [0190] Parts 218, 220 of the capacity wiring 216 correspond to the gate electrodes of the transistor Tr1 and the transistor Tr2. The source area of the transistor Tr1 is connected with the power source line 217. Moreover, the source area of the transistor Tr2 is connected with the power source line 217. Then, the drain area of the transistor Tr2 is connected with the pixel electrode 222 via the connection wiring 221. [0191] The numeral 219 denotes an active layer for forming a maintaining capacity. The capacity wiring 216 is formed on the active layer 219 for forming a maintaining capacity with the gate insulated film (not shown) interposed therebetween. The part with the active layer 219 for forming a maintaining capacity, the gate insulated film, and the capacity wiring 216 interposed corresponds to the maintaining capacity 205. The power source line 217 is formed on the capacity wiring 216 with the interlayer insulated film (not shown) interposed therebetween. The capacity formed in the part with the capacity wiring 216, the interlayer insulated film, and the power source line 217 superimposed may be used as the maintaining capacity 205. [0192] The top view of the pixel shown in this example is merely an example of the configuration of the present invention, and thus the top view of the pixel shown in FIG. 7 is not limited to the configuration shown in this example. This example can be executed freely as a combination with the example 1 or the example 2. Example 4 [0193] In this example, a top view of the pixel shown in FIG. 8 will be explained. FIG. 16 is a top view of the pixel of this example. In order to clarify the position of the wiring and the position of the semiconductor layer, the insulated films such as the interlayer insulated films and the gate insulated films are omitted. Moreover, the wirings formed in the same layer are shown by the same hatching. Furthermore, FIG. 16 corresponds to a top view of the pixel after formation of the pixel electrode and before formation of the organic light emitting layer. [0194] The pixel shown in FIG. 16 has each one set of a scanning line 311, a signal line 310, and a power source line 317. Then, parts 312, 313 of the scanning line 311 each correspond to the gate electrodes of the transistor Tr3 and the transistor Tr4. [0195] One of the source area and the drain area of the transistor Tr3 is connected with the signal line 310, and the other one is connected with the capacity wiring 316 via the connection wiring 330. Moreover, one of the source area and the drain area of the transistor Tr4 is connected with the capacity wiring 316 via the connection wiring 330, and the other one is connected with the drain area of the transistor Tr1 via the connection wiring 315. [0196] Parts 318, 320 of the capacity wiring 316 correspond to the gate electrodes of the transistor Tr1 and the transistor Tr2. The source area of the transistor Tr1 is connected with the power source line 317. Moreover, the source area of the transistor Tr2 is connected with the power source line 317. Then, the drain area of the transistor Tr2 is connected with the pixel electrode 322 via the connection wiring 321. [0197] The numeral 319 denotes an active layer for forming a maintaining capacity. The capacity wiring 316 is formed on the active layer 319 for forming a maintaining capacity with the gate insulated film (not shown) interposed therebetween. The part with the active layer 319 for forming a maintaining capacity, the gate insulated film, and the capacity wiring 316 interposed corresponds to the maintaining capacity 305. The power source line 317 is formed on the capacity wiring 316 with the interlayer insulated film (not shown) interposed therebetween. The capacity formed in the part with the capacity wiring 316, the interlayer insulated film, and the power source line 317 superimposed may be used as the maintaining capacity 305. [0198] The top view of the pixel shown in this example is merely an example of the configuration of the present invention, and thus the top view of the pixel shown in FIG. 8 is not limited to the configuration shown in this example. This example can be executed freely as a combination with the example 1 or the example 2. Example 5 [0199] In this example, a light emitting device with a configuration different from that of the example 1 will be explained. [0200] [0200]FIG. 27 is a cross-sectional view of a pixel part of the light emitting device according to this example. The light emitting device shown in FIG. 27 has a pixel for a red color (pixel for R) 800 r, a pixel for a green color (pixel for G) 800 g, and a pixel for a blue color (pixel for B) 800 b. The configuration of this example can be used not only for a color display light emitting device, but also for a light emitting device for displaying a monochrome image. [0201] For the pixel of each color, the transistor Tr2 is formed on a substrate 830. Although the transistors Tr1, Tr2, Tr3, Tr4 are formed for each pixel in the light emitting device of the present invention, only the transistor Tr2 is shown in FIG. [0202] The pixel electrodes 802 r, 802 g, 802 b (all together referred to as the pixel electrodes 802) are each connected with the drain areas 809 r, 809 g, 809 b of the transistor Tr2 via the contact hole formed in the gate insulated film 811, the first interlayer insulated film 810, and the second interlayer insulated film 807. [0203] In this example, the pixel electrodes are a cathode, and they to not allow the light transmission. Although an MgAg electrode is used as the cathode for the OLED in this example, another known material can be used as well. [0204] Then, the third interlayer insulated film 805 having an opening part at a position superimposed with the pixel electrodes 802 r, 802 g, 802 b is formed covering the pixel electrodes 802 r, 802 g, 802 b and the second interlayer insulated film 807. Although a silicon oxide film is used as the third interlayer insulated film 805 in this example, in some cases, an organic resin film made of a polyimide, a polyamide, an acrylic, a BCB (benzocyclo butene), a silicon oxide film, or the like can be used as well. [0205] Next, at the opening part of the third interlayer insulated film 805, the organic light emitting layers 803 r, 803 g, 803 b (all together referred to as the organic light emitting layers 803) are formed in contact with the pixel electrodes 802 r, 802 g, 802 b. At the time, the organic light emitting layers 803 r, 8903 g, 803 b are formed using a metal mask by the deposition method successively per each color. Although it is conceivable that the organic light emitting layers 803 r, 803 g, 803 b are formed to some extent in a part other than the opening part of the third interlayer insulated film 805 at the time of the deposition, they are formed only at the opening part of the third interlayer insulated film 805 as much as possible. [0206] Next, a conductive layer 806 having a metal is formed at the part other than the opening part in the third interlayer insulated film 805 using the deposition method. As the material for the conductive layer 806, a metal with a low resistance is preferable. Moreover, it is also possible to laminate conductive layers in a plurality of layers so as to be used as a conductive layer. Although a copper is used in this example, the conductive layer 806 material is not limited thereto, and a known metal material having a resistance lower than that of the counter electrode can be used. Since the resistance of the counter electrode to be formed later can be lowered by forming the conductive layer 806 in this example, it is suitable for enlargement of the substrate. [0207] Next, a counter electrode 804 comprising a transparent conductive film is formed covering the organic light emitting layers 803 r, 803 g, 803 b and the conductive layer 806. In this example, an ITO is used as the transparent conductive film. The ITO can be formed by the deposition method. In this example, the case of forming by the ion plating method will be explained. [0208] The ion plating method is one of the gas phase surface treatment techniques classified in the deposition method. It is a method for adhering a deposition substance evaporated by some means to a substrate by ionizing or exciting the same by a high frequency plasma or vacuum discharge, and accelerating the ion by providing a negative potential to the substrate to be deposited. [0209] As the specific condition for forming the counter electrode using the ion plating method, it is preferable to deposit with the substrate temperature maintained at 100 to 300° C. in a 0.01 to 1 Pa inert gas atmosphere. Furthermore, it is preferable to use the ITO as the evaporation source having a 70% or more sintering density. The optimum condition at the time of using the ion plating method can be selected optionally by the operator. [0210] Moreover, since the ionizing ratio or exciting ratio of the deposition substance can be improved by ionizing or exciting the deposition substance using the high frequency plasma as well as the ionized or excited deposition substance is in a high energy state, it can be bonded with the oxygen sufficiently with a high evaporation rate still maintained. Therefore, a good quality film can be formed at a high speed. [0211] In this example, the counter electrode 804 comprising a transparent conductive film was formed by a 80 to 120 nm thickness using the above-mentioned ion plating method. In this example, an indium-tin oxide (ITO) film or a transparent conductive film having 2 to 20[%] of a zinc oxide (ZnO) added to an indium oxide is used as the transparent electrode. [0212] The method for forming the counter electrode of this example is not limited to the above-mentioned ion plating method. However, since the film formed by the ion plating method has a high close contact property and it can form an ITO film with a high crystallization property even at a relatively low temperature, it can lower the resistance of the ITO as well as it can allow even film formation in a relatively wide area, and thus it is suitable for enlargement of the substrate. [0213] In each pixel, an OLED for R 801 r, an OLED for G 801 g, and an OLED for B 801 b are completed. Each OLED has the pixel electrodes 802 r, 802 g, 802 b, the organic light emitting layers 803 r, 803 g, 803 b, and the counter electrode 804. [0214] [0214]FIG. 28 is a top view of the substrate with the TFT formed (element substrate) of this example. It shows the state with the pixel part 831, the scanning line driving circuit 832, the signal line driving circuit 833, and the terminal 834 formed in the substrate 830. The terminal 834 and each driving circuit, and the power source line formed in the pixel part and the counter electrode are connected by a lead wiring 835. [0215] Moreover, as needed, an IC chip with a CPU, a memory, or the like formed, can be mounted on the element substrate by the COG (chip on glass)method, or the like. [0216] The OLED is formed between the conductive layers 806. The structure thereof is shown in FIG. 29. The pixel electrode 802 is an electrode corresponding to each pixel, formed between the conductive layers 806. In the upper layer thereof, an organic compound layer 803 is formed between the conductive layers 806, continuously in a stripe-like form across a plurality of the pixel electrodes 802. [0217] The counter electrode is formed in the upper layer of the organic compound layer 803 and the conductive layer 806 such that it is also in contact with the conductive layer 806. [0218] The lead line 835 is formed in the same layer as the scanning line (not shown) without direct contact with the conductive layer 806. Then, the lead line 835 and the counter electrode 804 has the contact in the superimposed part. [0219] The configuration of this example can be executed freely as a combination with the example 3 or 4. Example 6 [0220] In this example, the configuration of driving circuits (a signal driving circuit and a scanning line driving circuit) of a light emitting device driven by a digital driving method of the present invention. [0221] [0221]FIG. 17 is a block diagram showing the configuration of a signal line driving circuit 601. The numeral 602 is a shift resistor, the numeral 603 a memory circuit A, the numeral 604 a memory circuit B, and the numeral 605 a constant current circuit. [0222] To the shift resistor 602, a clock signal CLK and a start pulse signal SP are inputted. Moreover, to the memory circuit A 603, a digital video signal is inputted. And to the memory circuit B 604, a latch signal is inputted. A constant signal current Ic outputted from the constant current circuit 604 is inputted to the signal line. [0223] [0223]FIG. 18 shows a further detailed configuration of the signal line driving circuit 601. [0224] According to the input of the clock signal CLK and the start pulse signal SP from a predetermined wiring to the shift resistor 602, a timing signal is produced. The timing signal is inputted each to a plurality of latches A (LATA-1 to LATA-x) of the memory circuit A 603. At the time, it is also possible to input the timing signal produced by the shift resistor 602 each to a plurality of the latches A (LATA-1 to LATA-x) of the memory circuit A 603 after buffer amplification by a buffer, or the like. [0225] In the case the timing signal is inputted to the memory circuit A 603, a digital video signal for one bit to be inputted to the video signal line 610 is written successively to each of the plurality of the latches A (LATA-1 to LATA-x) synchronously with the timing signal so as to be stored. [0226] Although the digital video signal is inputted successively to the plurality of the latches A (LATA-1 to LATA-x) of the memory circuit A 603 at the time of taking the digital video signal to the memory circuit A 603 in this embodiment, the present invention is not limited to this configuration. It is also possible to execute the so-called divided drive of driving latches of a plurality of stages of the memory circuit A 603 into several stages, and inputting a digital video signal simultaneously for each group. The number of the groups at the time is called the division number. For example, in the case latches are divided into groups for 4 stages, it is called the four division divided drive. [0227] The time needed for finishing each writing operation of a digital video signal to the latches of all the stages of the memory circuit A 603 is called the line period. In the real situation, the period with the horizontal retrace line period added to the line period may be referred to as the line period. [0228] In the case one line period is finished, a latch signal is supplied to a plurality of latches B (LATB-1 to LATB-x) of the memory circuit B 604 via the latch signal line 609. At the moment, the digital video signals stored in the plurality of the latches A (LATA-1 to LATA-x) of the memory circuit A 603 are written and stored in the plurality of the latches B (LATB-1 to LATB-x) of the memory circuit B 604 all together. [0229] A digital video signal for the next one bit is written in the memory circuit A 603 after sending out the digital video signals to the memory circuit B 604, based on the timing signal from the shift registor 602 successively. [0230] In the second one line period, the digital video signals written and stored in the memory circuit B 604 are inputted to the constant current circuit 605. [0231] The constant current circuit 605 has a plurality of current setting circuits (C1 to Cx). In the case a digital video signal is inputted to each of the current setting circuits (C1 to Cx), based on the information of 1 or 0 of the digital video signal, either supply of a constant current Ic in the signal line, or application of a potential of the power source lines V1 to Vx to the signal line, is selected. [0232] [0232]FIG. 19 shows an example of a specific configuration of the current setting circuit C1. The current setting circuits C2 to Cx have the same configuration. [0233] The current setting circuit C1 has a constant current source 631, four transmission gates SW1 to SW4, and two inverters Inb1, Inb2. The polarity of the transistor 650 of the constant current source 631 is same as the polarity of the transistors Tr1 and Tr2 of the pixel. [0234] According to the digital video signal outputted from the LATB-1 of the memory circuit B 604, the switching operation of SW1 to SW4 is controlled. The digital video signals inputted to SW1 and SW3 and the digital video signals inputted to SW2 and SW4 are inverted by Inb1, Inb2. Therefore, in the case SW1 and SW3 are on, SW2 and SW4 are off, and in the case SW1 and SW3 are off, SW2 and SW4 are on. [0235] In the case SW1 and SW3 are on, a current Ic of a predetermined value except 0 is inputted from the constant current source 631 to the signal line S1 via SW1 and SW3. [0236] In contrast, in the case SW2 and SW4 are on, the current Ic from the constant current source 631 is provided to the ground via SW2. Moreover, the power source potential from the power source lines V1 to Vx is provided to the signal line S1 via SW4 so as to be Ic≈0. [0237] With reference to FIG. 18, the above-mentioned operation is executed simultaneously in a one line period for all the current setting circuits (C1 to Cx) of the constant current circuit 605. Therefore, the value of the signal current Ic inputted to all the signal lines is selected by the digital video signals. [0238] Next, the configuration of the scanning line driving circuit will be explained. [0239] [0239]FIG. 20 is a block diagram showing the configuration of the scanning line driving circuit 641. [0240] The scanning line driving circuit 641 each has a shift registor 642, and a buffer 643. In some cases, a level shifter may be provided as well. [0241] In the scanning line driving circuit 641, by inputting the clock CLK and the start pulse signal SP to the shift registor, a timing signal is produced. The produced timing signal is buffer-amplified by the buffer 643 so as to be supplied to a corresponding scanning line. [0242] The scanning line is connected with the gate electrodes of the first switching TFT and the second switching TFT for a pixel of one line. Since the first switching TFT and the second switching TFT for a pixel of one line should be switched on simultaneously, one capable of supplying a large amount of the current is used as the buffer 643. [0243] The driving circuit used in the present invention is not limited to the configuration shown in this example. The constant current circuit shown in this example is not limited to the configuration shown in FIG. 19. The constant current circuit used in the present invention can have any configuration as long as either one of the binary of the signal current Ic can be selected by the digital video signal, and the signal current of the selected value can be provided to the signal line. [0244] The configuration of this example can be executed freely as a combination with the examples 1 to 5. Example 7 [0245] In this example, the order of appearance of the sub frame periods SF1 to SFn in the driving method for a light emitting device according to the present invention corresponding to a digital video signal of n bits will be explained. [0246] [0246]FIG. 21 shows a timing n sets of writing periods (Ta1 to Tan) and n sets of display periods (Td1 to Tdn) appearing in one frame period. The lateral axis represents the time and the vertical axis represents the position of the scanning line of the pixel. As to the detailed operation of each pixel, the embodiments can be referred to, and thus it is omitted here. [0247] In the driving method of this example, the sub frame period (in this example, SFn) having the longest display period in the one frame period is not provided at the first and the last of the one frame period. In other words, another sub frame period contained in the same frame period appears before and after the sub frame period having the longest display period in the one frame period. [0248] According to the above-mentioned configuration, display irregularity derived from the successive arrangement of the display periods for emitting a light in the adjacent frame periods in the middle gradient display can hardly be recognized by human eyes. [0249] The configuration of this example is effective in the case of n≧3. Moreover, the configuration of this example can be executed freely as a combination with the examples 1 to 6. Example 8 [0250] In this example, an example of driving the light emitting device of the present invention using a digital video signal of 6 bits will be explained. [0251] [0251]FIG. 22 shows a timing of 6 sets of writing periods (Ta1 to Ta6) and 6 sets of display periods (Td1 to Td6) appearing in one frame period. The lateral axis represents the time and the vertical axis represents the position of the scanning line of the pixel. As to the detailed operation of each pixel, the embodiments can be referred to, and thus it is omitted here. [0252] In the case of the drive using a digital video signal of 6 bits, at least 6 sets of sub frame periods SF1 to SF6 are provided in the one frame period. [0253] The sub frame periods SF1 to SF6 correspond to each bit of the digital signal of 6 bits. The sub frame periods SF1 to SF6 have 6 sets of the writing periods (Ta1 to Ta6) and 6 sets of the display periods (Td1 to Td6). [0254] The sub frame period having the writing period Tam and the display period Tdm corresponding to the m-th bit (m is an optional number of 1 to 6) is SFm. After the writing period Tam, the display period corresponding to the same bit number, in this case, Tdm appears. [0255] By repeated appearance of the writing period Ta and the display period Td in the one frame period, an image can be displayed. [0256] The length of the display periods SF1 to SF6 satisfies SF1: SF2: . . . : SF6=20: 21: . . . : 25. [0257] According to the driving method of the present invention, the gradient is displayed by controlling the sum of the length of the display period with the light emission in the one frame period. [0258] The configuration of this example can be executed freely as a combination with the examples 1 to 7. Example 9 [0259] In this example, an example of the driving method using a digital video signal of n bits, which is different from that of FIG. 6 and FIG. 21. [0260] [0260]FIG. 23 shows a timing of n+1 sets of writing periods (Ta1 to Ta(n+1)) and n+1 sets of display periods (Td1 to Td(n+1)) appearing in one frame period. The lateral axis represents the time and the vertical axis represents the position of the scanning line of the pixel. As to the detailed operation of each pixel, the embodiments can be referred to, and thus it is omitted here. [0261] In this example, corresponding to the n bit digital video signal, n+1 sets of sub frame periods SF1 to SFn+1 are provided in the one frame period. Then, the sub frame periods SF1 to SFn+1 have n+1 sets of the writing periods (Ta1 to Ta(n+1)) and n+1 sets of the display periods (Td1 to Td(n+1) The sub frame period having the writing period Tam and the display period Tdm (m is an optional number of 1 to n+1) is SFm. After the writing period Tam, the display period corresponding to the same bit number, in this case, Tdm appears. [0262] The sub frame periods SF1 To SFn-1 correspond to each bit of the digital signal of 1 to (n−1) bits. The sub frame periods SFn and SF(n+1) correspond to the digital video signal of the n-th bit. [0263] Moreover, in this example, the sub frame periods SFn and SF(n+1) corresponding to the digital video signal of the same bit do not appear continuously. In other words, another sub frame period is provided between the sub frame periods SFn and SF(n+1) corresponding to the digital video signal of the same bit. [0264] By repeated appearance of the writing period Ta and the display period Td in the one frame period, an image can be displayed. [0265] The length of the display periods SF1 to SFn+1 satisfies SF1: SF2: . . . : (SFn+SF(n+1))=20: 21: . . . : 2(n−1). [0266] According to the driving method of the present invention, the gradient is displayed by controlling the sum of the length of the display period with the light emission in the one frame period. [0267] In this example, according to the above-mentioned configuration, display irregularity derived from the successive arrangement of the display periods for emitting a light in the adjacent frame periods in the middle gradient display can hardly be recognized by human eyes. [0268] Although the case with two sub frame periods corresponding to the same bit has been explained in this example, the present invention is not limited thereto. Sub frame periods corresponding to the same bit in one frame period can be provided three or more. [0269] Moreover, although a plurality of sub frame periods corresponding to the digital video signal of the uppermost position bit have been provided in this example, the present invention is not limited thereto. Sub frame periods corresponding to a digital video signal of a bit other than the bit of the uppermost position can be provided in a plurality. Furthermore, the bit provided with a plurality of the corresponding sub frame periods is not limited to one, and a configuration having a plurality of sub frame periods each to several bits can be adopted as well. [0270] The configuration of this example is effective in the case of n≧2. Moreover, the configuration of this example can be executed freely as a combination with the examples 1 to 8. Example 10 [0271] In this example, the configuration of a signal line driving circuit of a light emitting device according to the present invention driven by an analog driving method will be explained. As to the configuration of the scanning line driving circuit, one described in the example 6 can be adopted, explanation is omitted here. [0272] [0272]FIG. 31A is a block diagram of a signal line driving circuit 401 of this example. The numeral 402 is a shift resistor, the numeral 403 a buffer, the numeral 404 a sampling circuit, and the numeral 405 is a current converting circuit. [0273] To the shift register 402, a clock signal (CLK) and a start pulse signal (SP) are inputted. In the case the clock signal (CLK) and the start pulse signal (SP) are inputted to the shift resistor 402, a timing signal is produced. [0274] The produced timing signal is amplified or buffer-amplified by the buffer 403 so as to be inputted to the sampling circuit 404. Moreover, the timing signal can be amplified by providing a level shifter instead of the buffer. Furthermore, both the buffer and the level shifter can be provided. [0275] [0275]FIG. 31B shows a specific configuration of the sampling circuit 404 and the current converting circuit 405. The sampling circuit 404 is connected with the buffer 403 at the terminal 410. [0276] The sampling circuit 404 is provided with a plurality of switches 411. Furthermore, an analog video signal is inputted from the video signal line 406 to the sampling circuit 404. The switch 411 samples the analog video signal synchronously with the timing signal so as to input the same to the current converting circuit 405 in the later stage. Although FIG. 31B shows only the configuration of the current converting circuit 405 connected with one of the switches 411 of the sampling circuit 404, the current converting circuit 405 as shown in FIG. 31B is connected in the later stage of each switch 411. [0277] Although only one transistor is used for the switch 411 in this example, any switch capable of sampling the analog video signal synchronously with the timing signal can be adopted as the switch 411, and thus it is not limited to the configuration of this example. [0278] The sampled analog video signal is inputted to a current output circuit 412 of the current converting circuit 405. The current output circuit 412 outputs a current (signal current) of a value corresponding to the voltage of the inputted video signal. Although a current output circuit is provided using an amplifier and a TFT in FIG. 31, the present invention is not limited to the configuration, and any circuit capable of outputting the current of a value corresponding to the voltage of the inputted signal can be adopted. [0279] The signal current is inputted to a reset circuit 417 of the current converting circuit 405. The reset circuit has two analog switches 413, 414, an inverter 416, and a power source 415. [0280] A reset signal (Res) is inputted to the analog switch 414, and a reset signal (Res) inverted by the inverter 416 is inputted to the analog switch 413. Then, the analog switch 413 and the analog switch 414 are operated synchronously each with the inverted reset signal and the reset signal such that when one is on, the other is off. [0281] In the case the analog switch 413 is on, the signal current is inputted to the corresponding signal line. In contrast, in the case the analog switch 414 is on, the potential of the power source 415 is provided to the signal line so that the signal line is reset. It is preferable that the potential of the power source 415 is at substantially same height as the potential of the power source line provided to the pixel. And the current supplied to the signal line when the signal line is reset is preferably close to 0 as much as possible. [0282] It is preferable that the signal line is reset in the retrace line period. However, it is possible to reset in a period other than the retrace line period as needed as long as it is not a period showing an image. [0283] The configuration of the signal line driving circuit and the scanning line driving circuit for driving the light emitting device of the present invention is not limited to that shown in this example. The configuration of this example can be executed freely as a combination with the examples 1 to 9. Example 11 [0284] In this example, by using an organic light emitting material capable of utilizing the phosphorescence from a triplet exciton to the light emission, the external light emission quantum efficiency can dramatically be improved. Thereby, a low power consumption, a long life, and a light weight of the OLED can be achieved. [0285] Here, a report of improvement of the external light emission quantum efficiency utilizing the triplet exciton will be shown. (T. Tsutsui, C. Adachi, S. Saito, Photochemical Processes In organized Molecular Systems, ed. K. Honda, (Elsevier Sci. Pub., Tokyo, 1991) p. 437.) [0286] A molecular formula of the organic light emitting material (coumarin pigment) reported in the above-mentioned article is shown below. [0287] (M. A. Baldo, D., F. O'Brien, Y. You, A. Shoustikov, S. Sibley, M. E. Thompson, S. R. Forrest, Nature 395 (1998) p. 151.) [0288] A molecular formula of the organic light emitting material (Pt complex) reported in the above-mentioned article is shown below. [0289] (M. A. Baldo, S. Lamansky, P. E. Burrrows, M. E. Thompson, S. R. Forrest, Appl. Phys. Lett., 75 (1999) p. 4.) (T. Tsutsui, M. J.-Yang, M. Yahiro, K. Nakamura, T. Watanabe, T. Tsuji, Y. Fukuda, T. Wakimoto, S. Mayaguchi, Jpn. Appl. Phys., 38 (12B) (1999) L1502.) [0290] A molecular formula of the organic light emitting material (Ir complex) reported in the above-mentioned article is shown below. [0291] In the case the phosphorescence light emission from the triplet excitor can be utilized as mentioned above, in principle, a high external light emission quantum efficiency three to four times as much as the case of utilizing the fluorescence light emission from a singlet excitor can be realized. [0292] The configuration of this example can be executed freely as a combination with any of the examples 1 to 10. Example 12 [0293] An example of producing a light emitting device using the present invention will be explained in this example with reference to FIG. 24. [0294] [0294]FIG. 24 is a top view of a light emitting device formed by sealing the element substrate with the TFT formed by a sealing material. FIG. 24B is a cross-sectional view taken on the line A-A′ in FIG. 24A, and FIG. 24C is a cross-sectional view taken on the line B-B′ of FIG. 24A. [0295] A sealing material 4009 is provided surrounding a pixel part 4002 provided on a substrate 4001, a signal line driving circuit 4003, and first and second scanning line driving circuits 4004 a, b. Moreover, a sealing material 4008 is provided on the pixel part 4002, the signal line driving circuit 4003, and the first and second scanning line driving circuits 4004 a, b. Accordingly, the signal pixel part 4002, the signal line driving circuit 4003, and the first and second scanning line driving circuits 4004 a, b are sealed in a filling material 4210 by the substrate 4001, the sealing material 4009 and the sealing material 4008. [0296] Moreover, the pixel part 4002 provided on the substrate 4001, the signal line driving circuit 4003, and the first and second scanning line driving circuits 4004 a, b have a plurality of TFTs. FIG. 24B shows representatively a driving TFT included in the signal line driving circuit 4003, formed on the base film 4010 (here, the n channel type TFT and the p channel TFT) 4201, and a current controlling TFT (transistor Tr2) included in the pixel part 4002. [0297] In this example, the p channel type TFT or the n channel TFT produced by a known method is used for the driving TFT 4201, and a p channel type TFT produced by a known method is used for the current controlling TFT 4202. Moreover, the pixel part 4002 is provided with a maintaining capacity (not shown) connected with the gate of the current controlling TFT 4202. [0298] An interlayer insulated film (flattening film) 4301 is formed on the driving TFT 4201 and the current controlling TFT 4202, with a pixel electrode (anode) 4203 electrically connected with the drain of the current controlling TFT 4202 formed thereon. As the pixel electrode 4203, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of an indium oxide and a tin oxide, a compound of an indium oxide and a zinc oxide, a zinc oxide, or an indium oxide can be used. Moreover, the above-mentioned transparent conductive film with a gallium added can be used as well. [0299] Furthermore, the insulated film 4302 is formed on the pixel electrode 4203, and the insulated film 4302 has an opening part formed on the pixel electrode 4203. At the opening part, an organic light emitting layer 4204 is formed on the pixel electrode 4203. For the organic light emitting layer 4204, a known organic light emitting material or inorganic light emitting material can be used. Moreover, the organic light emitting material includes both a low molecular type (monomer type) and high molecular type (polymer type) materials, and either one can be used. [0300] As to the method for forming the organic light emitting layer 4204, a known deposition technique or application method technique can be used. Moreover, as to the organic light emitting layer structure, a laminated structure or a single layer structure provided by a free combination of a hole injecting layer, a positive hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer. [0301] A cathode 4205 made of a conductive film having the light blocking property (representatively a conductive film containing as the main component an aluminum, a copper, or a silver, or a laminated film of them and another conductive film) is formed on the organic light emitting layer 4204. Moreover, it is preferable to exclude the moisture content or the oxygen existing on the interface between the cathode 4205 and the organic light emitting layer 4204 as much as possible. Therefore, a scheme of forming the organic light emitting layer 4204 with a nitrogen or a rare gas atmosphere so that the cathode 4205 can be formed without contact with the oxygen or the moisture content, is necessary. In this example, the above-mentioned film formation is enabled by using a multi chamber method (cluster tool method) film forming device. A predetermined voltage is applied to the cathode 4205. [0302] As mentioned above, the OLED 4303 comprising the pixel electrode (anode) 4203, the organic light emitting layer 4204, and the cathode 4205 can be formed. Furthermore, a protection film 4303 is formed on the insulated film 4302 so as to cover the OLED 4303. The protection film 4303 is effective for preventing entrance of the oxygen, the moisture content, or the like to the OLED 4303. [0303] The numeral 4005 a is a lead wiring connected with the power source supply line, connected electrically with the source area of the current controlling TFT 4202. The lead line 4005 a disposed between the sealing material 4009 and the substrate 4001 is connected electrically with the FPC wiring 4301 of the FPC 4006 via the anisotropic conductive film 4300. [0304] For the sealing material 4008, a glass material, a metal material (representatively, a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. For the plastic material, an FRP (fiberglass-reinforced plastics) plate, a PVF (polyvinyl fluoride) film, a Mylar film, a polyester film, or an acrylic resin film can be used. Moreover, a sheet with a structure with an aluminum foil interposed by PVF films or Mylar films can be used as well. [0305] However, in the case the light radiation direction from the OLED is toward the cover material side, the cover material should be transparent. In this case, a transparent substance, such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used. [0306] Moreover, for the filling material 4210, in addition to an inert gas such as a nitrogen and an argon, an ultraviolet ray hardening resin or a thermosetting resin can be used. Examples thereof include a PVC (polyvinyl chloride), an acrylic, a polyimide, an epoxy resin, a silicon resin, a PVB (polyvinyl butylal), or an EVA (ethylene vinyl acetate). In this example, as the filling material, a nitrogen was used. [0307] Furthermore, in order to expose the filling material 4210 to a moisture absorbing substance (preferably a barium oxide) or a substance capable of adsorbing the oxygen, a recess part 4007 is provided in the sealing material 4008 on the substrate 4001 side for disposing a moisture absorbing substance or a substance capable of absorbing the oxygen 4207. Then, in order to prevent scattering of the moisture absorbing substance or the substance capable of absorbing the oxygen 4207, the moisture absorbing substance or the substance capable of absorbing the oxygen 4207 is kept in the recess part 4007 by a recess part cover material 4208. The recess part cover material 4208 has a fine mesh-like shape such that passage of the air or the moisture content is allowed but passage of the moisture absorbing substance or the substance capable of absorbing the oxygen 4207 is not allowed. By providing the moisture absorbing substance or the substance capable of absorbing the oxygen 4207, deterioration of the OLED 4303 can be restrained. [0308] As shown in FIG. 24C, simultaneously with the formation of the pixel electrode 4203, a conductive film 4203 a is formed in contact with the lead wiring 4005 a. [0309] Moreover, the anisotropic film 4300 has a conductive filler 4300 a. By thermally pressing the substrate 4001 and the FPC 4006, the conductive film 4203 a on the substrate 4001 and the wiring for the FPC 4301 on the FPC 4006 can be connected electrically by the conductive filler 4300 a. [0310] The configuration of this example can be executed freely as a combination with any of the examples 1 to 11. Example 13 [0311] In this example, an example of the configuration of the pixel of the light emitting device of the present invention different from that of FIGS. 2, 7, or 8 will be explained. [0312] [0312]FIG. 30A shows the configuration of the pixel of this example. The pixel 701 shown in FIG. 30A has a signal line Si (one of the S1 to Sx), the first scanning line Gaj (one of the Ga1 to Gay), the second scanning line Gbj (one of the Gb1 to Gby), and a power source line Vi (one of the V1 to Vx). The number of the first scanning lines and the second scanning lines provided in the pixel part need not to be always the same number. [0313] Moreover, the pixel 701 has at least a transistor Tr1 (the first current driving transistor or the first transistor), a transistor Tr2 (the second current driving transistor or the second transistor), a transistor Tr3 (first switching transistor or the third transistor), a transistor Tr4 (second switching transistor or the fourth transistor), a transistor Tr5 (transistor for erasure, or the fifth transistor), an OLED 704 and a maintaining capacity 705. [0314] The gate electrodes of the transistor Tr3 and the transistor Tr4 are both connected with the first scanning line Gaj. [0315] One of the source area and the drain area of the transistor Tr3 is connected with the signal line Si, and the other one is connected with the drain area of the transistor Tr1. Moreover, one of the source area and the drain area of the transistor Tr4 is connected with the signal line Si, and the other one is connected with the gate electrode of the transistor Tr1. [0316] The gate electrodes of the transistor Tr1 and the transistor Tr2 are connected with each other. Moreover, the source areas of the transistor Tr1 and the transistor Tr2 are both connected with the power source line Vi. [0317] The drain area of the transistor Tr2 is connected with a pixel electrode of the OLED 704. [0318] The gate electrode of the transistor Tr5 is connected with the second scanning line Gbj. Moreover, one of the source area and the drain area of the transistor Tr5 is connected with the power source line Vi, and the other one is connected with the gate electrodes of the transistor Tr1 and the transistor Tr2. [0319] The potential of the power source line Vi (power source potential) is maintained at a constant level. Moreover, the potential of the counter electrode is maintained at a constant level as well. [0320] The transistor Tr3 and the transistor Tr4 may either be an n channel type TFT or a p channel type TFT. However, the polarity of the transistor Tr3 and the transistor Tr4 is same. [0321] Moreover, the transistor Tr1 and the transistor Tr2 may either be an n channel type TFT or a p channel type TFT. However, the polarity of the transistor Tr1 and the transistor Tr2 is same. In the case the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistor Tr1 and the transistor Tr2 are used as the p channel type TFT. In contrast, in the case the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistor Tr1 and the transistor Tr2 are used as the n channel type TFT. [0322] Moreover, the transistor Tr5 may either be the n channel type TFT or the p channel type TFT. [0323] The maintaining capacity 705 is formed between the gate electrodes of the transistor Tr1 and the transistor Tr2 and the power source line Vi. Although the maintaining capacity 705 is provided for maintaining more securely the voltage (gate voltage) between the gate electrodes of the transistor Tr1 and the transistor Tr2 and the source area, it is not always necessarily provided. [0324] [0324]FIG. 30B shows another configuration of the pixel of this example. The pixel 711 shown in FIG. 30B has a signal line Si (one of the S1 to Sx), the first scanning line Gaj (one of the Ga1 to Gay) the second scanning line Gbj (one of the Gb1 to Gby) and a power source line Vi (one of the V1 to Vx) [0325] Moreover, the pixel 711 has at least a transistor Tr1 (the first current driving transistor), a transistor Tr2 (the second current driving transistor), a transistor Tr3 (first switching transistor), a transistor Tr4 (second switching transistor), a transistor Tr5 (transistor for erasure, or the fifth transistor), an OLED 714 and a maintaining capacity 715. [0326] The gate electrodes of the transistor Tr3 and the transistor Tr4 are both connected with the first scanning line Gaj. [0327] One of the source area and the drain area of the transistor Tr3 is connected with the signal line Si, and the other one is connected with the drain area of the transistor Tr1. Moreover, one of the source area and the drain area of the transistor Tr4 is connected with the drain area of the transistor Tr1, and the other one is connected with the gate electrode of the transistor Tr1. [0328] The gate electrodes of the transistor Tr1 and the transistor Tr2 are connected with each other. Moreover, the source areas of the transistor Tr1 and the transistor Tr2 are both connected with the power source line Vi. [0329] The drain area of the transistor Tr2 is connected with a pixel electrode of the OLED 714. The potential of the power source line Vi (power source potential) is maintained at a constant level. Moreover, the potential of the counter electrode is maintained at a constant level as well. [0330] The gate electrode of the transistor Tr5 is connected with the second scanning line Gbj. Moreover, one of the source area and the drain area of the transistor Tr5 is connected with the power source line Vi, and the other one is connected with the gate electrodes of the transistor Tr1 and the transistor Tr2. [0331] The transistor Tr3 and the transistor Tr4 may either be an n channel type TFT or a p channel type TFT. However, the polarity of the transistor Tr3 and the transistor Tr4 is same. [0332] Moreover, the transistor Tr1 and the transistor Tr2 may either be an n channel type TFT or a p channel type TFT. However, the polarity of the transistor Tr1 and the transistor Tr2 is same. In the case the anode is used as the pixel electrode and the cathode is used as the counter electrode, it is preferable that the transistor Tr1 and the transistor Tr2 are used as the p channel type TFT. In contrast, in the case the anode is used as the counter electrode and the cathode is used as the pixel electrode, it is preferable that the transistor Tr1 and the transistor Tr2 are used as the n channel type TFT. [0333] Moreover, the transistor Tr5 may either be the n channel type TFT or the p channel type TFT. [0334] The maintaining capacity 715 is formed between the gate electrodes of the transistor Tr1 and the transistor Tr2 and the power source line Vi. Although the maintaining capacity 715 is provided for maintaining more securely the voltage (gate voltage) between the gate electrodes of the transistor Tr1 and the transistor Tr2 and the source area, it is not always necessarily provided. [0335] [0335]FIG. 30C shows another configuration of the pixel of this example. The pixel 721 shown in FIG. 30C has a signal line Si (one of the S1 to Sx), the first scanning line Gaj (one of the Ga1 to Gay), the second scanning line Gbj (one of the Gb1 to Gby) and a power source line Vi (one of the V1 to Vx). [0336] Moreover, the pixel 721 has at least a transistor Tr1 (the first current driving transistor), a transistor Tr2 (the second current driving transistor), a transistor Tr3 (first switching transistor), a transistor Tr4 (second switching transistor), a transistor Tr5 (transistor for erasure, or the fifth transistor) an OLED 724 and a maintaining capacity 725. [0337] The gate electrodes of the transistor Tr3 and the transistor Tr4 are both connected with the first scanning line Gaj. [0338] One of the source area and the drain area of the transistor Tr3 is connected with the signal line Si, and the other one is connected with the gate electrode of the transistor Tr1. Moreover, one of the source area and the drain area of the transistor Tr4 is connected with the drain area of the transistor Tr1, and the other one is connected with the gate electrode of the transistor Tr1. [0339] The gate electrodes of the transistor Tr1 and the transistor Tr2 are connected with each other. Moreover, the source areas of the transistor Tr1 and the transistor Tr2 are both connected with the power source line Vi. [0340] The drain area of the transistor Tr2 is connected with a pixel electrode of the OLED 724. The potential of the power source line Vi (power source potential) is maintained at a constant level. Moreover, the potential of the counter electrode is maintained at a constant level as well. [0341] The gate electrode of the transistor Tr5 is connected with the second scanning line Gbj. Moreover, one of the source area and the drain area of the transistor Tr5 is connected with the power source line Vi, and the other one is connected with the gate electrodes of the transistor Tr1 and the transistor Tr2. [0342] The transistor Tr3 and the transistor Tr4 may either be an n channel type TFT or a p channel type TFT. However, the polarity of the transistor Tr3 and the transistor Tr4 is same. [0343] Moreover, the transistor Tr1 and the transistor Tr2 may either be an n channel type TFT or a p channel type TFT. However, the polarity of the transistor Tr1 and the transistor Tr2 is same. In the case the anode is used as the pixel electrode and the cathode is used as the counter electrode, it is preferable that the transistor Tr1 and the transistor Tr2 are used as the p channel type TFT. In contrast, in the case the anode is used as the counter electrode and the cathode is used as the pixel electrode, it is preferable that the transistor Tr1 and the transistor Tr2 are used as the n channel type TFT. [0344] Moreover, the transistor Tr5 may either be the n channel type TFT or the p channel type TFT. [0345] The maintaining capacity 725 is formed between the gate electrodes of the transistor Tr1 and the transistor Tr2 and the power source line Vi. Although the maintaining capacity 725 is provided for maintaining more securely the voltage (gate voltage) between the gate electrodes of the transistor Tr1 and the transistor Tr2 and the source area, it is not always necessarily provided. [0346] The driving method for a light emitting device having a pixel, shown in FIGS. 30A, 30B, 30C is limited only to the digital driving method. Furthermore, in the pixel shown in FIGS. 30A, 30B, 30C, by switching on the transistor Tr5 by controlling the potential of the second scanning line Gbj when the OLED 704, 714, 724 is emitting a light, the OLED 704, 714, 724 can be in a non-light emitting state. Therefore, since the display period of each pixel can be finished forcibly simultaneously with the input of the digital video signal to the pixel, the display period can be made shorter than the writing period so that it is suitable for driving with a digital video signal of a high bit number. [0347] The configuration of this example can be executed freely as a combination with the configuration shown in the examples 1, 2, 5, 6, 7, 8, 9, 11, 12. Example 14 [0348] Since the light emitting device using the OLED is a spontaneous light emitting type, compared with a liquid crystal display, it has a superior visibility in a bright place, and a wide view angle. Therefore, it can be used for the display part of various kinds of electronic appliances. [0349] As the electronic appliances using the light emitting device of the present invention, a video camera, a digital camera, a goggle type display (head mount display) a navigation system, a sound reproducing device (car audio, audio component, or the like), a lap top type personal computer, a game appliance, a portable information terminal (mobile computer, portable phone, portable type game machine, electronic book, or the like), an image reproducing device comprising a memory medium (specifically, a device for reproducing a memory medium such as a DVD: digital versatile disc, or the like, comprising a display for displaying the image), or the like, can be presented. In particular, since the width of the view angle is important for a portable information terminal with a lot of opportunities for viewing the screen from the oblique direction, it is preferable to use a light emitting device. A specific example of the electronic appliances is shown in FIG. 25. [0350] [0350]FIG. 25A shows an OLED display device, comprising a housing 2001, a supporting base 2002, a display part 2003, a speaker part 2004, a video input terminal 2005, or the like. The light emitting device of the present invention can be used for the display part 2003. Since the light emitting device is of a spontaneous light emitting type, backlighting is not necessary, and thus a display part thinner than a liquid crystal display can be provided. The OLED display device includes all the display devices for displaying information, such as a personal computer, a TV broadcast receipt, and an advertisement display. [0351] [0351]FIG. 25B shows a digital still camera, comprising a main body 2101, a display part 2102, an image receiving part 2103, an operation key 2104, an outside connection port 2105, a shutter 2106, or the like. The light emitting device of the present invention can be used for the display part 2102. [0352] [0352]FIG. 25C shows a lap top type personal computer, comprising a main body 2201, a housing 2202, a display part 2203, a key board 2204, an outside connection port 2205, a pointing mouse 2206, or the like. The light emitting device of the present invention can be used for the display part 2203. [0353] [0353]FIG. 25D shows a mobile computer, comprising a main body 2301, a display part 2302, a switch 2303, an operation key 2304, an infrared ray port 2305, or the like. The light emitting device of the present invention can be used for the display part 2302. [0354] [0354]FIG. 25E shows a portable type image reproducing device comprising a memory medium (specifically, a DVD reproducing device), comprising a main body 2401, a housing 2402, a display part A 2403, a display part B 2404, a memory medium (DVD, or the like), a reading part 2405, an operation key 2406, a speaker 2407, or the like. The display part A 2403 displays mainly the image information, and the display part B 2404 displays mainly the character information. The light emitting device of the present invention can be used for the display parts A, B 2403, 2404. The image reproducing device comprising the memory medium includes a domestic game appliance. [0355] [0355]FIG. 25F shows a goggle type display (head mount display), comprising a main body 2501, a display part 2502, and an arm part 2503. The light emitting device of the present invention can be used for the display part 2502. [0356] [0356]FIG. 25G shows a video camera, comprising a main body 2601, a display part 2602, a housing 2603, an outside connection port 2604, a remote control receiving part 2605, an image receiving part 2606, a battery 2607, a sound input part 2608, an operation key 2609, or the like. The light emitting device of the present invention can be used for the display part 2602. [0357] Here, FIG. 25H shows a portable phone, comprising a main body 2701, a housing 2702, a display part 2703, a sound input part 2704, a sound output part 2705, an operation key 2706, an outside connection port 2707, an antenna 2708, or the like. The light emitting device of the present invention can be used for the display part 2703. By displaying white characters on a black background in the display part 2703, the current consumption can be restrained for the portable phone. [0358] In the case the light emitting luminance of the organic light emitting material is made higher in the future, it can be used also in a front type or rear type projector by enlarging and projecting a light including the outputted image information by a lens, or the like. [0359] Moreover, in the above-mentioned electronic appliances, the information provided through an electronic communication network, such as the internet and a CATV (cable television) is displayed often, in particular, the opportunities for displaying video information are increased. Since the response speed of the organic light emitting material is extremely high, the light emitting device is preferable for the video display. [0360] Furthermore, since a part emitting a light in the light emitting device consumes the electric power, it is preferable to display the information with the light emitting part reduced to the minimum level. Therefore, in the case the light emitting device is used for the display part mainly having the character information, such as a portable information terminal, in particular, a portable phone, and a sound reproducing device, it is preferable to drive such that the character information is provided as a light emitting part with a non-light emitting part provided as the background. [0361] As heretofore explained, the present invention can be adopted in an extremely wide range, and thus it can be used for the electronic appliances in all the fields. Moreover, the electronic appliance of this example can employ the light emitting device of any configuration shown in the examples 1 to 13. [0362] According to the above-mentioned configuration, the light emitting device of the present invention can obtain a certain luminance without the influence by the temperature change. Moreover, in the color display, even in the case an OLED having different organic light emitting materials for each color is provided, inability of obtaining a desired color by individual change of the OLED luminance of each color due to the temperature can be prevented. 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Ltd.Organic light emitting display device and method for manufacturing the same* Cited by examinerClassifications U.S. Classification315/169.3International ClassificationG09G3/32, C09K11/06, H05B33/14, H01L27/32, G09G3/20Cooperative ClassificationH01L27/3248, H01L51/5259, G09G3/3208, H01L27/1285, H01L27/3279, H01L27/1222, H01L27/3262, H01L2251/301, G09G2300/0417, G09G3/2022, G09G3/3283, G09G2300/0809, G09G3/3266, G09G2320/0266, H05B33/14, G09G2310/027, G09G2320/041, G09G2320/0247, G09G2300/0842, G09G3/3241, G09G2300/0861, H01L27/3244, G09G2300/0426, C09K2211/185, C09K2211/1088, C09K11/06, H01L51/0096, H01L27/3272, H01L27/3246, H01L27/3258European ClassificationG09G3/32A14C, H05B33/14, C09K11/06, G09G3/32A12, G09G3/32A8C2, G09G3/20G6FLegal EventsDateCodeEventDescriptionJul 27, 2011FPAYFee paymentYear of fee payment: 4Aug 12, 2015FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services