Source: http://www.google.com/patents/US6900115?dq=5754119
Timestamp: 2016-05-28 10:01:24
Document Index: 241989432

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US6900115 - Deposition over mixed substrates - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsChemical vapor deposition methods are used to deposit silicon-containing films over mixed substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity....http://www.google.com/patents/US6900115?utm_source=gb-gplus-sharePatent US6900115 - Deposition over mixed substratesAdvanced Patent SearchPublication numberUS6900115 B2Publication typeGrantApplication numberUS 10/074,633Publication dateMay 31, 2005Filing dateFeb 11, 2002Priority dateFeb 12, 2001Fee statusPaidAlso published asDE60223662D1, DE60223662T2, DE60227350D1, EP1374290A2, EP1374290B1, EP1374291A2, EP1374291B1, EP1421607A2, US6716713, US6716751, US6743738, US6821825, US6958253, US6962859, US7186582, US7273799, US7285500, US7547615, US7585752, US7893433, US8067297, US8360001, US20020168868, US20020173113, US20020197831, US20030022528, US20030068851, US20030068869, US20030082300, US20050048745, US20050064684, US20050208740, US20050250302, US20070102790, US20080014725, US20080073645, US20100012030, WO2002064853A2, WO2002064853A3, WO2002065508A2, WO2002065508A3, WO2002065516A2, WO2002065516A3, WO2002065516A8, WO2002065517A2, WO2002065517A3, WO2002080244A2, WO2002080244A3, WO2002080244A9Publication number074633, 10074633, US 6900115 B2, US 6900115B2, US-B2-6900115, US6900115 B2, US6900115B2InventorsMichael A. ToddOriginal AssigneeAsm America, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (75), Non-Patent Citations (3), Referenced by (110), Classifications (126), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetDeposition over mixed substrates
US 6900115 B2Abstract
Chemical vapor deposition methods are used to deposit silicon-containing films over mixed substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. An example is in forming the base region of a heterojunction bipolar transistor, including simultaneous deposition over both single crystal semiconductor surfaces and amorphous insulating regions.
providing a substrate disposed within a chamber, wherein the substrate comprises a first surface having a first surface morphology and a second surface having a second surface morphology different from the first surface morphology, the first surface morphology being single crystalline and the second surface morphology being amorphous, polycrystalline or a mixture of amorphous and crystalline material; introducing trisilane to the chamber under chemical vapor deposition conditions; and depositing a Si-containing film onto the substrate over both of the first surface and the second surface. 2. The deposition method of claim 1, further comprising introducing a germanium source to the chamber simultaneously with the trisilane, thereby depositing a SiGe film as the Si-containing film.
3. The deposition method of claim 2, wherein the SiGe film comprises from about 0.1 atomic % to about 80 atomic % germanium.
4. The deposition method of claim 1, wherein the first surface comprises a semiconductor material and the second surface comprises a dielectric material.
5. The deposition method of claim 4, wherein the semiconductor material comprises silicon and a dopant selected from the group consisting of arsenic, boron, indium, phosphorous, and antimony.
6. The deposition method of claim 4, wherein the dielectric material comprises a material selected from the group consisting of silicon dioxide, silicon nitride, metal oxide and metal silicate.
7. The deposition method of claim 1, wherein the Si-containing film is a silicon buffer layer having a thickness of about 500 Å or less.
8. The deposition method of claim 7, further comprising introducing a germanium source a silicon source to the chamber to thereby deposit a SiGe film onto the buffer layer.
9. The deposition method of claim 8, wherein the silicon source comprises trisilane.
10. The deposition method of claim 1, wherein at least a portion of the first surface is non-coplanar with at least a portion of the second surface.
11. The deposition method of claim 10, wherein the Si-containing film has a first thickness T1 over the first surface and a second thickness T2 over the second surface such that T1:T2 is in the range of about 10:1 to about 1:10.
12. The deposition method of claim 11, wherein the chemical vapor deposition conditions comprise a temperature in the range of about 400� C. to about 750� C.
13. The deposition method of claim 11, wherein the Si-containing film has a first thickness T1 over the first surface and a second thickness T2 over the second surface such that T1:T2 is in the range of about 2:1 to about 1:2.
14. The deposition method of claim 13, wherein the Si-containing film has a first thickness T1 over the first surface and a second thickness T2 over the second surface such that T1:T2 is in the range of about 1.3:1 to about 1:1.3.
15. The deposition method of claim 1, further comprising introducing a dopant precursor to the chamber, thereby depositing an in situ doped Si-containing film as the Si-containing film.
16. The deposition method of claim 1, wherein the Si-containing film comprises a crystalline morphology over the first surface and a non-crystalline morphology over the second surface.
providing a substrate disposed within a chamber, wherein the substrate comprises a first surface having a single crystalline morphology and a second surface having a surface morphology different from the single crystalline morphology; introducing trisilane and a germanium source to the chamber under chemical vapor deposition conditions; and depositing a SiGe film onto the substrate over both of the first surface and the second surface. 18. The deposition method of claim 17, wherein the SiGe film comprises from abut 0.1 atomic % to about 80 atomic % germanium.
This application claims priority to U.S. Provisional Application No. 60/268,337, filed Feb. 12, 2001; U.S. Provisional Application No. 60/279,256, filed Mar. 27, 2001; U.S. Provisional Application No. 60/311,609, filed Aug. 9, 2001; U.S. Provisional Application No. 60/323,649, filed Sep. 19, 2001; U.S. Provisional Application No. 60/332,696, filed Nov. 13, 2001; U.S. Provisional Application No. 60/333,724, filed Nov. 28, 2001; and U.S. Provisional Application No. 60/340,454, filed Dec. 7, 2001; all of which are hereby incorporated by reference in their entireties. This application is also related to, and incorporates by reference in their entireties, co-owned and co-pending U.S. patent application Ser. Nos. 10/074,563; 10/074,149; 10/074,722; 10/074,564; and 10/074,534, all of which were filed on Feb. 11, 2002.
A variety of methods are used in the semiconductor manufacturing industry to deposit materials onto surfaces. For example, one of the most widely used methods is chemical vapor deposition (“CVD”), in which atoms or molecules contained in a vapor deposit on a surface and build up to form a film. Deposition of silicon-containing (“Si-containing”) materials using conventional silicon sources and deposition methods is believed to proceed in several distinct stages, see Peter Van Zant, “Microchip Fabrication,” 4th Ed., McGraw Hill, New York, (2000), pp. 364-365. Nucleation, the first stage, is very important and is greatly affected by the nature and quality of the substrate surface. Nucleation occurs as the first few atoms or molecules deposit onto the surface and form nuclei. During the second stage, the isolated nuclei form small islands that grow into larger islands. In the third stage, the growing islands begin coalescing into a continuous film. At this point, the film typically has a thickness of a few hundred angstroms and is known as a “transition” film. It generally has chemical and physical properties that are different from the thicker bulk film that begins to grow after the transition film is formed.
For example, silicon tetrachloride (SiCl4), silane (SiH4), and dichlorosilane SiH2Cl2) are the most widely used silicon sources in the semiconductor manufacturing industry for depositing Si-containing films, see Peter Van Zant, “Microchip Fabrication,” 4th Ed., McGraw Hill, New York, (2000), p 380-382. However, deposition using these conventional silicon sources is generally difficult to control over mixed substrates, such as surfaces containing both single crystal silicon and silicon dioxide. Control is difficult because the morphology and thickness of the resulting Si-containing film depend on both the deposition temperature and the morphology of the underlying substrate. Other deposition parameters, including total reactor pressure, reactant partial pressure and reactant flow rate can also strongly influence the quality of depositions over mixed substrates.
For example, FIG. 1A schematically illustrates a cross-section of a substrate 100 having an exposed silicon dioxide (“oxide”) surface 110 and an exposed single crystal silicon surface 120. FIGS. 1B and 1C schematically illustrate the results obtained by using silane in a chemical vapor deposition process to deposit a silicon film onto the substrate 100. For temperatures of about 625� C. and below, deposition conditions can be selected that result in a low defectivity, epitaxial silicon film 130 over the epitaxial surface 120, but under such conditions no film (FIG. 1B) or a film 140 having poor quality (FIG. 1C) is deposited over the oxide surface 110. The differences in film formation are believed to be a result of the differences in nucleation rates on the two surfaces when silane is used as the silicon source. Conventional silicon precursors demonstrate well-documented poor nucleation over dielectrics, such as silicon oxide. By the time spotty nucleation sites converge on the oxide, deposition over adjacent non-dielectric regions has progressed considerably. Furthermore, deposition tends to be rough over the dielectric since widely spread nucleation sites support deposition while regions between remain bare. Often, the illustrated “selective” epitaxial deposition is desired (FIG. 1B); in other cases, better deposition of silicon over the oxide surface 110 is desired, e.g., to facilitate later contact to the epitaxial region.
In the past, manufacturers have approached such problems through the use of selective deposition or additional masking and/or process steps. For example, U.S. Pat. No. 6,235,568 notes that one is presently unable to selectively deposit a silicon film onto p-type and n-type silicon surfaces at the same time. U.S. Pat. No. 6,235,568 purports to provide a solution to this problem by carrying out a pre-deposition low energy blanket ion implantation step. The stated purpose of this additional step is to make the surfaces appear the same to a subsequent deposition process.
Methods have now been discovered that utilize trisilane to deposit high quality Si-containing films over a variety of substrates. In accordance with one aspect of the invention, a deposition method is provided, comprising:
FIG. 1A to 1C are schematic cross sections illustrating problems encountered in prior art deposition methods onto a mixed substrate.
FIG. 3A to 3C of the invention illustrates deposition over a mixed substrate, including a window between field oxide regions, using trisilane in accordance with a preferred embodiment.
Deposition processes have now been discovered that are much less sensitive to nucleation phenomena. These processes employ trisilane (H3SiSiH2SiH3) to enable the deposition of high quality Si-containing films over mixed substrates. FIG. 2A schematically illustrates a preferred structure 200 resulting from such a deposition process. Compared to FIG. 1B, successful deposition of a Si-containing film 210 over both types of substrate surface (the single crystal, semiconductor surface 220 and the dielectric surface 230) while maintaining epitaxial crystal quality and a close match in total deposited thickness can be achieved using trisilane. FIGS. 2A and 2B are described in more detail below.
As used herein, a “mixed substrate” is a substrate that has two or more different types of surfaces. There are various ways that surfaces can be different from each other. For example, the surfaces can be made from different elements such as copper or silicon, or from different metals, such as copper or aluminum, or from different Si-containing materials, such as silicon or silicon dioxide. Even if the materials are made from the same element, the surfaces can be different if the morphologies of the surfaces are different. The electrical properties of surfaces can also make them different from each other. In the illustrated examples, silicon-containing layers are simultaneously formed over conductive semiconductive materials and dielectrics. Examples of dielectric materials include silicon dioxide, silicon nitride, metal oxide, and metal silicate.
The processes described herein are useful for depositing Si-containing films on a variety of mixed substrates, but are particularly useful for substrates having mixed surface morphologies. Such a mixed substrate comprises a first surface having a first surface morphology and a second surface having a second surface morphology. In this context, “surface morphology” refers to the crystalline structure of the substrate surface. Amorphous and crystalline are examples of different morphologies. Polycrystalline morphology is a crystalline structure that consists of a disorderly arrangement of orderly crystals and thus has an intermediate degree of order. The atoms in a polycrystalline material have long range order within each of the crystals, but the crystals themselves lack long range order with respect to one another. Single crystal morphology is a crystalline structure that has a high degree of order. Epitaxial films are characterized by a crystal structure and orientation that is identical to the substrate upon which they are grown. The atoms in these materials are arranged in a lattice-like structure that persists over relatively long distances (on an atomic scale). Amorphous morphology is a non-crystalline structure having a low degree of order because the atoms lack a definite periodic arrangement. Other morphologies include microcrystalline and mixtures of amorphous and crystalline material.
Specific examples of mixed substrates are shown in FIGS. 1A (discussed above) and 3A. FIG. 3A illustrates a substrate 300 having field isolation regions 310 over a semiconductor substrate 320. Preferably, the semiconductor substrate 320 is a single crystal wafer, (or an epitaxial silicon layer deposited over such a wafer) and the isolation regions 310 are silicon dioxide. In the illustrated embodiment, the substrate 300 comprises a first substrate surface having a semiconductor active area 340 having a single crystal surface morphology and a second substrate surface 330 having an amorphous surface morphology. The silicon active area 340 and the surface of the isolation regions 330 are morphologically different (crystalline vs. amorphous) and have different electrical conductivity (conductor vs. insulator). Those skilled in the art will appreciate a variety of methods for making such a structure 300, including local oxidation of silicon (LOCOS) and trench isolation processes, see Peter Van Zant, “Microchip Fabrication,” 4th Ed., McGraw Hill, New York, (2000), pp. 522-526.
A suitable manifold may be used to supply feed gas(es) to the CVD chamber. In the illustrated embodiments, the gas flow in the CVD chamber is horizontal, most preferably the chamber is a single-wafer, single pass, laminar horizontal gas flow reactor, preferably radiantly heated. Suitable reactors of this type are commercially available, and preferred models include the Epsilon™ series of single wafer reactors commercially available from ASM America, Inc. of Phoenix, Ariz. While the methods described herein can also be employed in alternative reactors, such as a showerhead arrangement, benefits in increased uniformity and deposition rates have been found particularly effective in the horizontal, single-pass laminar gas flow arrangement of the Epsilon™ chambers, employing a rotating substrate, particularly with low process gas residence times. CVD may be conducted by introducing plasma products (in situ or downstream of a remote plasma generator) to the chamber, but thermal CVD is preferred.
Incorporation of dopants into Si-containing films by CVD using trisilane is preferably accomplished by in situ doping using dopant precursors. Precursors for electrical dopants include diborane, deuterated diborane, phosphine, arsenic vapor, and arsine. Silylphosphines [(H3Si)3-xPRx] and silylarsines [(H3Si)3-xAsRx] where x=0-2 and Rx=H and/or D are preferred precursors for phosphorous and arsenic dopants. SbH3 and trimethylindium are preferred sources of antimony and indium, respectively. Such dopant precursors are useful for the preparation of preferred films as described below, preferably boron-, phosphorous-, antimony-, indium-, and arsenic-doped silicon, SiC, SiGe and SiGeC films and alloys. As used herein, “SiC”, “SiGe”, and “SiGeC” represent materials that contain the indicated elements in various proportions. For example, “SiGe” is a material that comprises silicon, germanium and, optionally, other elements, e.g., dopants. “SiC”, “SiGe”, and “SiGeC” are not chemical stoichiometric formulas per se and thus are not limited to materials that contain particular ratios of the indicated elements.
The amount of dopant precursor in the feed gas may be adjusted to provide the desired level of dopant in the Si-containing film. Typical concentrations in the feed gas can be in the range of about 1 part per billion (ppb) to about 1% by weight based on total feed gas weight, although higher or lower amounts are sometimes preferred in order to achieve the desired property in the resulting film. In the preferred Epsilon™ series of single wafer reactors, dilute mixtures of dopant precursor in a carrier gas can be delivered to the reactor via a mass flow controller with set points ranging from about 10 to about 200 standard cubic centimeters per minute (sccm), depending on desired dopant concentration and dopant gas concentration. The dilute mixture is preferably further diluted by mixing with trisilane and any suitable carrier gas. Since typical total flow rates for deposition in the preferred Epsilon™ series reactors often range from about 20 standard liters per minute (slm) to about 180 slm, the concentration of the dopant precursor used in such a method is small relative to total flow.
In a preferred embodiment, a mixed-morphology Si-containing film is deposited onto the mixed substrate. A “mixed-morphology,” as used herein, film is a film that comprises two or more different morphologies in different lateral regions of the substrate. FIG. 2A illustrates such a mixed morphology silicon film 210. The film 210 comprises a non-epitaxial region 240 deposited over the amorphous oxide surface 230 and an epitaxial region 260 deposited over the single crystal surface 220. In the illustrated embodiment, the film 210 also includes a boundary region 250 that is deposited over the boundary 270 between the oxide surface 230 and the single crystal surface 220.
The morphologies of the mixed-morphology film depend on the deposition temperature, pressure, reactant partial pressure(s) and reactant flow rates and the surface morphologies of the underlying substrate. Using trisilane, silicon-containing materials capable of forming single crystal films tend to form over properly prepared single crystal surfaces, whereas non-single crystal films tend to form over non-single crystalline surfaces. Epitaxial film formation is favored for silicon-containing materials capable of forming pseudomorphic structures when the underlying single crystal surface has been properly treated, e.g., by ex-situ wet etching of any oxide layers followed by in situ cleaning and/or hydrogen bake steps, and when the growth conditions support such film growth. Such treatment methods are known to those skilled in the art, see Peter Van Zant, “Microchip Fabrication,” 4th Ed., McGraw Hill, New York, (2000), pp. 385. Polycrystalline and amorphous film formation is favored over amorphous and polycrystalline surfaces and over single crystal surfaces that have not been treated to enable epitaxial film growth. Amorphous film formation is favored over amorphous and polycrystalline substrate surfaces at low temperatures, while polycrystalline films tend to form over amorphous and polycrystalline surfaces at relatively high deposition temperatures.
For a mixed substrate comprising a first surface having a first surface morphology and a second surface having a second surface morphology, the Si-containing film deposited onto this mixed substrate preferably has a thickness T1 over the first surface and a thickness T2 over the second surface such that T1:T2 is in the range of about 10:1 to about 1:10, more preferably about 5:1 to about 1:5, even more preferably about 2:1 to about 1:2, and most preferably about 1.3:1 to about 1:1.3. Surprisingly, trisilane deposition under the CVD conditions described herein tends to produce a Si-containing film having a thickness that is approximately proportional to deposition time and relatively independent of underlying surface morphology. More particularly, trisilane enables rapid nucleation and smooth film formation over dielectric surfaces, as compared to conventional silicon precursors. Compare FIGS. 6 and 7 to FIGS. 8 and 9, discussed below. Thus, under preferred deposition conditions, the nucleation time tends to be very short on a broad variety of surfaces, and T1:T2 is preferably about 1:1.
In a preferred embodiment, the Si-containing film is a buffer layer having a thickness of about 1,000 Å or less, preferably a thickness in the range of about 10 Å to about 500 Å, more preferably in the range of about 50 Å to about 300 Å. In this context, a “buffer layer” is a Si-containing film that is deposited onto a substrate for the purpose of facilitating the deposition of a subsequent layer or protecting an underlying layer. When the buffer layer is used for the purpose of facilitating nucleation, it may also be referred to as a nucleation layer. The thickness ranges described above refer to deposition over the entire mixed substrate, e.g., over both the crystalline and amorphous surfaces.
For example, the Si-containing film 210 in FIG. 2B is a buffer layer because it facilitates the subsequent deposition of an overlying film 280. In the illustrated embodiment, the film 280 is a silicon germanium-containing (“SiGe-containing”) material such as SiGe or SiGeC. Preferably, the overlying film 280 is a mixed morphology film having an epitaxial morphology over the epitaxial region 260 and a non-single crystal morphology over the non-single crystal region 240.
Preferably, the surface morphology and composition of at least one surface of the underlying mixed substrate is effective to allow strained heteroepitaxial growth of SiGe films thereon. A “heteroepitaxial” deposited layer is an epitaxial film that has a different composition than the single crystal substrate onto which it is deposited. A deposited epitaxial layer is “strained” when it is constrained to have a lattice structure in at least two dimensions that is the same as that of the underlying single crystal substrate, but different from its inherent lattice constant. Lattice strain is present because the atoms depart from the positions that they would normally occupy in the lattice structure of the free-standing, bulk material when the film deposits in such a way that its lattice structure matches that of the underlying single crystal substrate.
CVD using trisilane and a germanium source enables the formation of Si-containing films such as SiGe or SiGeC over mixed substrates. FIG. 3 illustrates the benefits obtained when using trisilane in the context of a preferred embodiment, but it will be recognized by those skilled in the art that variations of the preferred method in accordance with the teachings herein will provide similar benefits. FIG. 3A illustrates a preferred structure 300 having field isolation regions 310 over a semiconductor substrate 320. In the illustrated embodiment, the semiconductor substrate 320 comprises epitaxial silicon formed over a single-crystal wafer and the isolation regions 310 are silicon dioxide. Prior to deposition, the substrate 320 is prepared for epitaxial deposition by methods known to those skilled in the art to expose an active area 340 having an oxide-free crystalline surface (epitaxial silicon) and an amorphous surface 330.
Reference is now made to FIG. 4 to describe a preferred method for making a base structure for a SiGe heterojunction bipolar transistor (“SiGe HBT”), but it will be understood by those skilled in the art that the illustrated method is also applicable to other processes. Structure 400 in FIG. 4 is made by depositing a series of films onto a single-crystal silicon n+ substrate 402 having amorphous field isolation regions 404. The field isolation regions 404 are preferably silicon dioxide, but can be other dielectric materials, such as silicon nitride. Prior to deposition, the surface 408 of the substrate 402 is treated in a manner known to those skilled in the art to render it suitable for subsequent epitaxial deposition. Since the substrate 402 is n-doped, preferably with arsenic, the illustrated embodiment is suitable for npn transistors. However, those skilled in the art will recognize that the described methods are equally applicable to the fabrication of pnp devices.
A series of masking and etching steps are used to replace the undesired polycrystalline morphology in the region 550 with the desired epitaxial morphology. Using known photolithography techniques, a photoresist mask 560 is formed and patterned as illustrated in FIG. 5B. The exposed Si-containing layer in the region 550 is then etched away as illustrated in FIG. 5C using known etching techniques, opening a window to expose the underlying single-crystal surface 520. During the etching, the photoresist mask 560 protects the underlying polysilicon regions 540, which later serve to make contact with the base region being formed in the window 520. The photoresist mask 560 is then removed and a deposition process using a second (possibly the same) silicon source deposits an acceptable epitaxial film 570 onto the single-crystal surface 520 as illustrated in FIG. 5D. Such conventional deposition processes are known in the art, as discussed above with respect to FIG. 1B.
A substrate was provided consisting of a 1500 Å SiO2 (“oxide”) coating deposited onto a Si(100) wafer. The substrate was patterned to remove about 20% of the oxide coating to expose the underlying Si(100) wafer, thus creating a mixed substrate having a single-crystal surface and an amorphous oxide surface. The mixed substrate was then etched in a solution of dilute hydrofluoric acid, rinsed and dried. The mixed substrate was then loaded into an Epsilon E2500™ reactor system and subjected to a hydrogen bake at 900� C. at atmospheric pressure under a flow of 80 slm of ultra-pure hydrogen for 2 minutes. The mixed substrate was then allowed to reach thermal equilibrium at 600� C. at 40 Torr pressure under a flow of 20 slm of ultra-pure hydrogen gas. The steps of etching, drying, rinsing, and baking rendered the single crystal surface active for epitaxial film growth.
Pure hydrogen gas was then passed through liquid trisilane (maintained at room temperature using a water bath around the bubbler containing the trisilane) in order to deliver trisilane vapor to the heated substrate. The hydrogen/trisilane mixture, along with a flow of 90 sccm (inject) of trisilylarsine (100 ppm, 90 sccm mixed with 2 slm ultra-pure hydrogen) and 20 μm ultra-pure hydrogen, was then introduced into the reactor at a flow rate of 90 sccm for 15 seconds. A continuous, arsenic-doped, amorphous silicon film having a thickness of about 50 Å was deposited on the exposed oxide. A high crystal quality, arsenic-doped epitaxial silicon film having a thickness of about 45 Å was simultaneously deposited on the exposed Si<100> active areas. The trisilylarsine flow was then terminated. This deposition served as a buffer layer.
A Si-containing film was deposited onto a SiO2 substrate (without a nucleation layer) at a temperature of 600� C. using silane and germane as precursors. The surface roughness of the resulting SiGe film (as measured by atomic force microscopy) was 226 Å for a 10 micron�10 micron scan area Scanning electron microscopy (SEM) of the SiGe film revealed pyramidal, faceted grains indicative of an island-type deposition, as demonstrated in the SEM micrographs shown in FIGS. 6 and 7. This island-type deposition shows that deposition proceeded by a process in which isolated nuclei first formed on the surface, then grew together to form the islands shown. This illustrates the sensitivity of deposition to surface morphology when silane is used, i.e., poor nucleation of silane-deposited layers on oxide and consequent roughness.
A Si-containing film was deposited at 600� C. as described in Example 2, but trisilane and germane were used in place of silane and germane as precursors. The surface roughness of the resulting SiGe film (as measured by atomic force microscopy) was 18.4 Å for a 10 micron�10 micron scan area. SEM of the SiGe film revealed a much more uniform surface, as demonstrated in the SEM micrographs shown in FIGS. 8 and 9 (same magnifications and tilt angles as FIGS. 6 and 7, respectively). The relative lack of island-type deposition, as compared to silane, shows that deposition occurred evenly over the surface, and did not proceed by the nucleation and growth mechanism described above in Example 2. This illustrates the relative insensitivity of deposition to surface morphology when trisilane is used, i.e., excellent nucleation of trisilane-deposited layers and consequent smoothness.
A series of Si-containing films were deposited onto a SiO2 substrate (without a nucleation layer) at a pressure of 40 torr using trisilane and germane. The trisilane flow rate was constant at 77 sccm (hydrogen carrier, bubbler) for the examples of Table 1. Germane floe (10% germane, 90% H2) and deposition temperature were varied as shown in Table 1. Germanium concentration (atomic %) and thickness of the resulting SiGe films were determined by RBS, and surface roughness was determined by atomic force microscopy (AFM). The results shown in Table 1 demonstrate that highly uniform films can be prepared over a range of temperatures and flow rate conditions, particularly over a range of germane concentration, and further illustrate the relative insensitivity of deposition to surface morphology when trisilane is used.
*Thickness measured by optical technique nd: not determined It will be appreciated by those skilled in the art that various omissions, additions and variations may be made to the compositions and processes described above without departing from the scope of the invention, and all such modifications and changes are intended to fall within the scope of the invention, as defined by the appended claims.
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438/488, 257/E21.17, 257/E21.166, 257/E21.102, 257/E21.131, 438/482, 257/E21.101, 438/489, 257/E21.119, 257/E29.162, 257/E21.197International ClassificationH01L21/337, H01L21/28, H01L21/316, H01L21/469, H01L21/331, H01L21/8238, H01L29/737, C23C16/42, H01L27/092, H01L29/78, H01L21/425, C23C16/24, H01L21/205, H01L21/285, C23C16/02, C30B25/02, H01L29/51, H01L31/18, H01L21/20, H01L31/20Cooperative ClassificationY02P70/521, B82Y30/00, Y10S438/933, Y02E10/547, H01L21/0243, H01L21/32055, H01L31/182, H01L21/02598, H01L21/28556, C30B25/02, H01L31/202, H01L28/84, Y02E10/546, H01L29/517, H01L29/66181, C30B29/06, C23C16/22, C23C16/36, H01L29/127, C23C16/24, H01L21/0262, H01L29/518, H01L21/02592, C23C16/308, H01L29/66242, H01L29/51, H01L21/28194, H01L21/0245, H01L21/02422, H01L31/1804, C23C16/30, C23C16/56, H01L21/02667, H01L21/02595, C23C16/325, H01L21/3185, H01L21/02576, H01L21/28035, H01L21/0251, H01L21/28044, H01L21/2257, H01L21/28525, B82Y10/00, H01L21/02579, H01L21/02532, C23C16/345, H01L21/02529, C23C16/0272European ClassificationC23C16/30, H01L29/12W4, C23C16/56, C23C16/36, H01L21/225A4F, H01L21/318B, C23C16/24, C23C16/34C, C23C16/32B, C30B25/02, C23C16/30E, C23C16/22, H01L21/3205N, H01L21/28E2C2D, H01L29/51M, C30B29/06, H01L21/28E2B2P, H01L21/02K4C1A3, H01L21/02K4C3C1, H01L21/02K4C5M2, H01L21/02K4E3C, H01L21/02K4A1K, H01L21/02K4C3C2, H01L21/02K4B1A3, H01L21/02K4B5L7, H01L21/02K4C1A2, H01L21/02K4C5M1, H01L21/02K4C5M3, H01L21/02K4A5S, B82Y30/00, B82Y10/00, H01L28/84, H01L29/66M6D6, H01L29/66M6T2H, H01L31/18C, H01L21/205B, H01L29/51, H01L21/20C, H01L31/18C5, C23C16/02H, H01L21/20B, H01L21/28E2B2, H01L21/285B4H, H01L31/20B, H01L21/205, H01L21/285B4BLegal EventsDateCodeEventDescriptionMay 23, 2002ASAssignmentOwner name: ASM AMERICA, INC., ARIZONAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TODD, MICHAEL A.;REEL/FRAME:012909/0607Effective date: 20020422Dec 5, 2006CCCertificate of correctionDec 8, 2008REMIMaintenance fee reminder mailedMay 11, 2009FPAYFee paymentYear of fee payment: 4May 11, 2009SULPSurcharge for late paymentSep 28, 2012FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services