Source: http://www.google.com/patents/US20070049011?dq=5,579,517
Timestamp: 2017-03-24 12:30:58
Document Index: 343616059

Matched Legal Cases: ['Application No. 60', 'arts 200', 'arts 200', 'arts 200', 'arts 200', 'arts 200', 'arts 200', 'Application No. 60']

Patent US20070049011 - Method of forming isolated features using pitch multiplication - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsCrisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second...http://www.google.com/patents/US20070049011?utm_source=gb-gplus-sharePatent US20070049011 - Method of forming isolated features using pitch multiplicationAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20070049011 A1Publication typeApplicationApplication numberUS 11/219,067Publication dateMar 1, 2007Filing dateSep 1, 2005Priority dateSep 1, 2005Also published asUS7759197, US8043915, US8431971, US20100243161, US20120061807Publication number11219067, 219067, US 2007/0049011 A1, US 2007/049011 A1, US 20070049011 A1, US 20070049011A1, US 2007049011 A1, US 2007049011A1, US-A1-20070049011, US-A1-2007049011, US2007/0049011A1, US2007/049011A1, US20070049011 A1, US20070049011A1, US2007049011 A1, US2007049011A1InventorsLuan TranOriginal AssigneeMicron Technology, Inc., A CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (87), Referenced by (249), Classifications (28), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod of forming isolated features using pitch multiplication
US 20070049011 A1Abstract
Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross, e.g., are orthogonal to, the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with material, e.g., conductive material, to form conductive contacts. Images(39) Claims(40)
1. A method for semiconductor fabrication, comprising: forming a first set of spacers on a first level by pitch multiplication, the spacers of the first set of spacers elongated substantially in a first direction; forming a second set of spacers on a second level by pitch multiplication, the spacers of the second set of spacers elongated substantially in a second direction, wherein the first direction crosses the second direction; and selectively etching one or more layers underlying the first and the second set of spacers through a mask defined by the first and the second set of spacers. 2. The method of claim 1, wherein the spacers of the first set of spacers are substantially parallel to one another. 3. The method of claim 2, wherein the spacers of the second set of spacers are substantially parallel to one another. 4. The method of claim 1, wherein the first direction and the second direction cross at an angle of about 30-90° relative to one another. 5. The method of claim 4, wherein the angle is about 90°. 6. The method of claim 1, wherein selectively etching the one or more layers comprises forming a plurality of isolated voids. 7. The method of claim 6, wherein selectively etching the one or more layers comprises etching a dielectric layer. 8. The method of claim 7, wherein the dielectric layer comprises silicon oxide. 9. The method of claim 8, wherein the first set of spacers comprises amorphous silicon. 10. The method of claim 9, wherein the second set of spacers comprises silicon oxide. 11. The method of claim 6, further comprising depositing a material into the voids. 12. The method of claim 11, wherein depositing the material comprises a chemical vapor deposition. 13. The method of claim 11, wherein depositing the material comprises an electrochemical deposition. 14. The method of claim 11, wherein depositing the material comprises depositing a conductor into the voids to form a conductive plug. 15. The method of claim 14, wherein the conductor comprises one or more materials chosen from the group consisting of tungsten, doped polysilicon, titanium, tantalum, titanium compounds, tungsten compounds, tantalum compounds and nickel. 16. The method of claim 11, wherein depositing the material comprises depositing a phase change material into the voids to form a phase change memory. 17. The method of claim 16, wherein the phase change material is an alloy comprising germanium, antimony and tellurium. 18. The method of claim 11, wherein depositing the material comprises depositing a fusable material into the voids to form a programmable read only memory. 19. The method of claim 1, wherein forming a second set of spacers comprises forming a planarization layer around the first set of spacers. 20. The method of claim 19, wherein forming the planarization layer comprises depositing a planarization material around the first set of spacers. 21. The method of claim 20, wherein forming the planarization layer further comprises chemical mechanical polishing the planarization material. 22. The method of claim 20, wherein forming the planarization layer further comprises depositing a bottom anti-reflective coating (BARC) over the planarization. 23. The method of claim 22, wherein forming the planarization layer further comprises anisotropically etching the bottom anti-reflective coating (BARC) to form a planar surface. 24. The method of claim 20, wherein forming the planarization layer further comprises heating the planarization material, after depositing the planarization material, to form a level surface. 25. The method of claim 24, wherein the planarization material is one or more materials chosen from the groups consisting of borophosphosilicate glass and spin-on glass. 26-45. (canceled) 46. A method for semiconductor processing, comprising: forming a set of temporary placeholders; forming a first set of spacers immediately adjacent and contacting the placeholders, the first set of spacers having a sub-lithographic pitch; forming a second set of spacers above the first set of spacers, wherein spacers of the second set of spacers have a sub-lithographic pitch and are non-parallel to the first set of spacers; and exposing at least a portion of the temporary placeholders to a directional etch after forming the second set of spacers. 47. The method of claim 46, wherein the temporary placeholders each have a placeholder width of about 35-70 nm. 48. The method of claim 47, wherein the placeholder width is about 40-50 nm. 49. The method of claim 47, wherein spacers of the first set of spacers each have a spacer width of about 20-80 nm. 50. The method of claim 49, wherein the spacer width is about 50-75 nm. 51. The method of claim 49, wherein spacers of the second set of spacers each have a spacer width of about 20-80 nm. 52. The method of claim 46, wherein the first set of spacers have a pitch of about 100 nm or less. 53. The method of claim 52, wherein the second set of spacers have a pitch of about 100 nm or less. 54. The method of claim 46, further comprising selectively etching material underlying the first and the second set of spacers relative to the first and the second set of spacers. 55. The method of claim 54, wherein selectively etching the material defines features of a logic array. 56. The method of claim 46, wherein selectively etching the material defines features of a gate array. 57. The method of claim 46, wherein selectively etching the material defines features of a memory array. 58. The method of claim 46, wherein selectively etching the material defines features of a computer processor. 59-75. (canceled)
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is related to, and incorporates by reference in their entireties, the following: U.S. patent application Ser. No. 10/934,778 to Abatchev et al., filed Sep. 2, 2004; U.S. patent application Ser. No. 10/931,771 to Tran et al., filed Aug. 31, 2004; U.S. Provisional Patent Application No. 60/662,323 to Tran et al., filed Mar. 15, 2005; U.S. patent application Ser. No. 11/134,982 to Abatchev et al., filed May 23, 2005; and U.S. patent application Ser. No. ______ to Luan C. Tran, filed Sep. 1, 2005, entitled Reduced Pitch Contacts, Attorney Docket No. MICRON.313A (Micron Ref. No. 2004-1065.00/US).
BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates generally to integrated circuit fabrication and, more particularly, to masking techniques. [0004] 2. Description of the Related Art [0005] As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency, integrated circuits are continuously being made more dense. The sizes of the constituent features that form the integrated circuits, e.g., electrical devices and interconnect lines, are constantly being decreased to facilitate this scaling. [0006] The trend of decreasing feature size is evident, for example, in memory circuits or devices such as dynamic random access memories (DRAMs), flash memory, static random access memories (SRAMs), ferroelectric (FE) memories, etc. To take one example, DRAM typically comprises millions of identical circuit elements, known as memory cells. In general, a capacitor-based memory cell, such as in conventional DRAM, typically consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one bit (binary digit) of data. A bit can be written to a cell through the transistor and can be read by sensing charge in the capacitor. Some memory technologies employ elements that can act as both a storage device and a switch (e.g., dendritic memory employing silver-doped chalcogenide glass) and some nonvolatile memories do not require switches for each cell (e.g., magnetoresistive RAM). In addition, in some technologies, some elements can act as both charge storage and charge sensing devices. For example, this is the case with flash memory, thus, allowing this type of memory to have one of the smallest cell sizes (4F2) of all memory technologies. In general, by decreasing the sizes of the electrical devices that constitute a memory cell and the sizes of the conducting lines that access the memory cells, the memory devices can be made smaller. Additionally, storage capacities can be increased by fitting more memory cells on a given area in the memory devices. [0007] The continual reduction in feature sizes places ever greater demands on the techniques used to form the features. For example, photolithography is commonly used to pattern features, such as conductive lines. The concept of pitch can be used to describe the sizes of these features. Pitch is defined as the distance between an identical point in two neighboring features when the pattern includes repeating features, as in arrays. These features are typically defined by spaces between adjacent features, which spaces are typically filled by a material, such as an insulator. As a result, pitch can be viewed as the sum of the width of a feature and of the width of the space on one side of the feature separating that feature from a neighboring feature. However, due to factors such as optics and light or radiation wavelength, photolithography techniques each have a minimum pitch below which a particular photolithographic technique cannot reliably form features. Thus, the minimum pitch of a photolithographic technique is an obstacle to continued feature size reduction. [0008] “Pitch doubling” or “pitch multiplication” is one method for extending the capabilities of photolithographic techniques beyond their minimum pitch. A pitch multiplication method is illustrated in FIGS. 1A-1F and described in U.S. Pat. No. 5,328,810, issued to Lowrey et al., the entire disclosure of which is incorporated herein by reference. With reference to FIG. 1A, a pattern of lines 10 is photolithographically formed in a photoresist layer, which overlies a layer 20 of an expendable material, which in turn overlies a substrate 30. As shown in FIG. 1B, the pattern is then transferred using an etch (preferably an anisotropic etch) to the layer 20, thereby forming placeholders, or mandrels, 40. The photoresist lines 10 can be stripped and the mandrels 40 can be isotropically etched to increase the distance between neighboring mandrels 40, as shown in FIG. 1C. A layer 50 of spacer material is subsequently deposited over the mandrels 40, as shown in FIG. 1D. Spacers 60, i.e., the material extending or originally formed extending from sidewalls of another material, are then formed on the sides of the mandrels 40. The spacer formation is accomplished by preferentially etching the spacer material from the horizontal surfaces 70 and 80 in a directional spacer etch, as shown in FIG. 1E. The remaining mandrels 40 are then removed, leaving behind only the spacers 60, which together act as a mask for patterning, as shown in FIG. 1F. Thus, where a given pitch previously included a pattern defining one feature and one space, the same width now includes two features and two spaces, with the spaces defined by, e.g., the spacers 60. As a result, the smallest feature size possible with a photolithographic technique is effectively decreased. [0009] While the pitch is actually halved in the example above, this reduction in pitch is conventionally referred to as pitch “doubling,” or, more generally, pitch “multiplication.” Thus, conventionally, “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor. The conventional terminology is retained herein. [0010] Because a spacer pattern typically follows the outlines of mandrels, pitch multiplication is generally useful for forming regularly spaced linear features, such as conductive lines in a memory array. However, in addition to features which extend linearly over relatively large distances, e.g., conductive lines, integrated circuits contain more isolated features, e.g., conductive contacts. The continuing reduction in the sizes of integrated circuits has provided a continuing demand for reductions in the sizes of these isolated features and for increases in the densities of these features. Micromasking techniques, such as isotropically etching mask features, can reduce feature size but do not allow for a corresponding increase in feature density. [0011] Accordingly, there is a need for methods of reducing the sizes of isolated features, while also allowing increases in the density of these features. SUMMARY OF THE INVENTION [0012] According to one aspect of the invention, a method is provided for semiconductor fabrication. The method comprises forming a first set of spacers on a first level by pitch multiplication. Spacers of the first set of spacers are elongated substantially in a first direction. A second set of spacers is formed on a second level by pitch multiplication. Spacers of the second set of spacers are elongated substantially in a second direction, which crosses the first direction. The method also comprises selectively etching one or more layers underlying the first and the second set of spacers through a mask defined by the first and the second set of spacers. [0013] According to another aspect of the invention, a method is provided for forming an integrated circuit. The method comprises forming a first plurality of mandrels on a first level above a substrate. A first plurality of spacers is formed on sidewalls of the first plurality of mandrels. A second plurality of mandrels is formed on a second level above the first level. A second plurality of spacers is formed on sidewalls of the second plurality of mandrels. The first and the second plurality of mandrels are subsequently subjected to an anisotropic etch selective for materials forming the first and the second plurality of mandrels relative to materials forming the first and the second plurality of spacers. [0014] According to yet another aspect of the invention, a method is provided for semiconductor processing. The method comprises forming a set of temporary placeholders. A first set of spacers is formed immediately adjacent and contacting the placeholders. The first set of spacers have a sub-lithographic pitch. A second set of spacers is formed above the first set of spacers. The spacers of the second set of spacers have a sub-lithographic pitch and are non-parallel to the first set of spacers. At least a portion of the temporary placeholders are exposed to a directional etch after forming the second set of spacers. [0015] According to another aspect of the invention, a mask pattern overlying a partially fabricated integrated circuit is provided. The mask pattern comprises a first plurality of elongated spacers on a first level and a second plurality of elongated spacers on a second level. Spacers of the first plurality of spacers and spacers of the second plurality of spacers extend at an angle of about 30-90° relative to one another. BRIEF DESCRIPTION OF THE DRAWINGS [0016] The invention will be better understood from the Detailed Description of the Preferred Embodiments and from the appended drawings, which are meant to illustrate and not to limit certain embodiments of the invention, and wherein: [0017] FIGS. 1A-1F are schematic, cross-sectional side views of a sequence of masking patterns for forming conductive lines, in accordance with a prior art pitch doubling method; [0018] FIGS. 2A and 2B are schematic cross-sectional side and top plan views of a part of a partially formed integrated circuit, in accordance with preferred embodiments of the invention; [0019] FIGS. 3A and 3B are schematic cross-sectional side and top plan views of the partially formed integrated circuit of FIGS. 2A and 2B after forming lines in a photoresist layer, in accordance with preferred embodiments of the invention; [0020] FIGS. 4A and 4B are schematic cross-sectional side and top plan views of the partially formed integrated circuit of FIGS. 3A and 3B after widening spaces between lines in the photoresist layer, in accordance with preferred embodiments of the invention; [0021] FIG. 5 is a schematic, cross-sectional side view of the partially formed integrated circuit of FIGS. 4A and 4B after etching through a hard mask layer, in accordance with preferred embodiments of the invention; [0022] FIG. 6 is a schematic, cross-sectional side view of the partially formed integrated circuit of FIG. 5 after transferring a pattern from the hard mask layer to a temporary or mandrel layer to form mandrels on a first level, in accordance with preferred embodiments of the invention; [0023] FIG. 7 is a schematic, cross-sectional side view of the partially formed integrated circuit of FIG. 6 after a hard mask layer removal, in accordance with preferred embodiments of the invention; [0024] FIG. 8 is a schematic, cross-sectional side view of the partially formed integrated circuit of FIG. 7 after depositing a layer of a spacer material, in accordance with preferred embodiments of the invention; [0025] FIGS. 9A and 9B are schematic, cross-sectional side and top plan views of the partially formed integrated circuit of FIG. 8 after a spacer etch to define spacers on the first level, in accordance with preferred embodiments of the invention; [0026] FIGS. 10A and 10B are schematic, cross-sectional side and top plan views of the partially formed integrated circuit of FIGS. 9A and 9B after forming a planarization, or second mandrel, layer, in accordance with preferred embodiments of the invention; [0027] FIG. 11 is a schematic, cross-sectional side view of the partially formed integrated circuit of FIGS. 10A and 10B after depositing a hard mask layer and a photodefinable layer, respectively, in accordance with preferred embodiments of the invention; [0028] FIGS. 12A and 12B are schematic, cross-sectional side views of the partially formed integrated circuit of FIG. 11 after forming a pattern of mandrels in the planarization layer, on a second level, in accordance with preferred embodiments of the invention; [0029] FIG. 13 is a schematic, cross-sectional side view of the partially formed integrated circuit of FIG. 12 after depositing a spacer material around the mandrels, in accordance with preferred embodiments of the invention; [0030] FIGS. 14A and 14B are schematic, cross-sectional side views and FIG. 14C is a top plan view of the partially formed integrated circuit of FIG. 13 after performing a spacer etch to form spacers on a second level over the planarization layer, in accordance with preferred embodiments of the invention; [0031] FIGS. 15A and 15B are schematic, cross-sectional side views and FIG. 15C is a top plan view of the partially formed integrated circuit of FIGS. 14A-14C after directionally etching exposed mandrel material on the first and the second levels, in accordance with preferred embodiments of the invention; [0032] FIGS. 16A, 16B, 16C and 16D are schematic, cross-sectional side views and FIG. 16E is a top plan view of the partially formed integrated circuit of FIGS. 15A-15C after transferring a pattern formed by the combination of the spacers on the first and the second levels to an underlying layer, in accordance with preferred embodiments of the invention; [0033] FIGS. 17A and 17B are schematic, cross-sectional side and top plan views of the partially formed integrated circuit of FIGS. 16A-16E after removing the spacers on the first and the second levels, in accordance with preferred embodiments of the invention; and [0034] FIG. 18 is a top plan view of the partially formed integrated circuit of FIGS. 17A and 17B after filling voids masked by the spacers on the first and the second levels, in accordance with preferred embodiments of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0035] In preferred embodiments of the invention, in a process for reducing feature sizes, pitch-multiplied spacers are formed on multiple levels to define isolated features. The spacers on different levels extend or are elongated substantially in directions or axes that form an angle relative to spacers on other levels, so that the spacers on different levels appear to cross or intersect when viewed in a top down view. Preferably, the angle is about 30°-90°. More preferably, the spacers are formed on two levels and the spacers on a first level are orthogonal to the spacers on a second level. The spacers on each level are preferably formed by pitch multiplication in which mandrels are formed and the spacers are formed on the sides of each of the mandrels. Preferably, a plurality of mandrels is formed on each level, to form a plurality of spacers on each level. Exposed portions of the mandrels between the spacers are preferably removed after formation of the various sets of spacers, thereby forming voids bounded by the various spacers on the various levels. Preferably, the pattern formed by the spacers is transferred to one or more underlying materials, e.g., an oxide to form an array of vias which can later be filled to form individual circuit elements, e.g., contacts or memory storage devices, in an integrated circuit. In other embodiments, the spacers or the material underlying the spacers is removed to define a plurality of standalone, up-right, pillar-like structures for forming various electrical devices, e.g., vertical surround transistors formed by etching the substrate. [0036] Reference will now be made to the Figures, wherein like numerals refer to like parts throughout. It will be appreciated that these Figures are not necessarily drawn to scale. [0037] In a first phase of methods according to the preferred embodiments, spacers are formed on a first level. [0038] FIGS. 2A and 2B show cross-sectional side and top plan views of a portion of an integrated circuit 100. While the preferred embodiments can be used to form any integrated circuit, they are particularly advantageously applied to forming devices having arrays of electrical devices, including memory cell arrays for volatile and non-volatile memory devices such as DRAM, phase change memory (PCM), programmable conductor RAM (PCRAM), ROM or flash memory, including NAND flash memory, or integrated circuits having logic or gate arrays. For example, the logic array can be a field programmable gate array (FPGA) having a core array similar to a memory array and a periphery with supporting logics. Consequently, the integrated circuit 100 can be, e.g., a memory chip or a processor, which can include both a logic array and embedded memory, or any other integrated circuit having a logic or a gate array. [0039] With reference to FIG. 2A, various masking layers 120-140 are preferably provided above a dielectric or insulating layer 150, which is disposed above a substrate 160 in the illustrated embodiment. The layers 120-140 will be etched to form a mask for patterning the dielectric layer 150, as discussed below. In the illustrated embodiment, the dielectric layer 150 comprises silicon oxide. [0040] The materials for the layers 120-140 overlying the dielectric layer 150 are preferably chosen based upon consideration of the chemistry and process conditions for the various pattern forming and pattern transferring steps discussed herein. Because the layers between a topmost selectively definable layer 120 and the dielectric layer 150 preferably function to transfer a pattern derived from the selectively definable layer 120 to the dielectric layer 150, the layers 130-140 between the selectively definable layer 120 and the dielectric layer 150 are preferably chosen so that they can be selectively etched relative to other exposed materials. It will be appreciated that a material is considered selectively, or preferentially, etched when the etch rate for that material is at least about 2-3 times greater, preferably at least about 10 times greater, more preferably at least about 20 times greater and, most preferably, at least about 40 times greater than that for surrounding materials. It will be appreciated that one or more of the layers 120-140 can be omitted or substituted, or additional layers can be added, if suitable other materials, chemistries and/or process conditions are used. For example, the layer 130 can be omitted in some embodiments where the resolution enhancement properties of that layer, as discussed below, are not desired. [0041] In the illustrated embodiment, the selectively definable layer 120 overlies a first hard mask, or etch stop, layer 130, which overlies a temporary layer 140, which overlies the dielectric layer 150 to be processed (e.g., etched) through a mask. The temporary layer 140 can also be referred to as a mandrel layer. Preferably, the mask through which the dielectric layer 150 is processed is formed of spacers 175 and 275 (FIGS. 15A and 15B), as discussed below. [0042] With continued reference to FIG. 2B, the selectively definable layer 120 is preferably photodefinable, e.g., formed of a photoresist, including any photoresist known in the art. For example, the photoresist can be any photoresist compatible with 157 nm, 193 nm, 248 nm or 365 nm wavelength systems, 193 nm wavelength immersion systems, extreme ultraviolet systems (including 13.7 nm wavelength systems) or electron beam lithographic systems. In addition, maskless lithography, or maskless photolithography, can be used to define the selectively definable layer 120. Examples of preferred photoresist materials include argon fluoride (ArF) sensitive photoresist, i.e., photoresist suitable for use with an ArF light source, and krypton fluoride (KrF) sensitive photoresist, i.e., photoresist suitable for use with a KrF light source. ArF photoresists are preferably used with photolithography systems utilizing relatively short wavelength light, e.g., 193 nm. KrF photoresists are preferably used with longer wavelength photolithography systems, such as 248 nm systems. In other embodiments, the layer 120 and any subsequent resist layers can be formed of a resist that can be patterned by nano-imprint lithography, e.g., by using a mold or mechanical force to pattern the resist. [0043] The material for the hard mask layer 130 preferably comprises an inorganic material. Exemplary materials include silicon oxide (SiO2), silicon or a dielectric anti-reflective coating (DARC), such as a silicon-rich silicon oxynitride. Preferably, the hard mask layer 130 is a DARC. Using DARCs for the hard mask layer 130 can be particularly advantageous for forming patterns having pitches near the resolution limits of a photolithographic technique. The DARCs can enhance resolution by minimizing light reflections, thus increasing the precision with which photolithography can define the edges of a pattern. [0044] Due to its excellent etch selectivity relative to a variety of materials, including oxides, nitrides and silicon, the temporary layer 140 is preferably formed of amorphous carbon. More preferably, the amorphous carbon is a form of amorphous carbon that is highly transparent to light and that offers further improvements for photo alignment by being transparent to the wavelengths of light used for such alignment. Deposition techniques for forming such transparent carbon can be found in A. Helmbold and D. Meissner, Thin Solid Films, 283 (1996) 196-203, the entire disclosure of which is incorporated herein by reference. It will be appreciated that the oxide is preferably a form of silicon oxide and the nitride is preferably a form of silicon nitride. [0045] The material for the temporary layer 140 is preferably chosen based upon the materials used for the lower level spacers 175 (FIGS. 9A and 9B), the upper level spacers 275 (FIGS. 14 and 14B) and the underlying dielectric layer 150. As discussed herein, the layer 140 is preferably formed of amorphous carbon. An exemplary combination of materials is listed in the table below: Exemplary Spacer, Mandrel Layer, Hard Mask and Underlying Materials Underlying Lower Level Upper Level Hard Mandrel Dielectric Spacers Spacers Mask Layer Layer Amorphous Silicon Oxide DARC Amorphous Silicon Oxide Silicon Carbon [0046] In addition to selecting appropriate materials for the various layers, the thicknesses of the layers 120-140 are preferably chosen depending upon compatibility with the etch chemistries and process conditions described herein. As discussed above, when etching a material through a mask of another material, e.g., when transferring a pattern from an overlying layer to an underlying layer by selectively etching the underlying layer, materials from both layers are removed to some degree. Thus, the upper layer is preferably thick enough so that it is not worn away over the course of the pattern transfer. [0047] In the illustrated embodiment, the photodefinable layer 120 is preferably about 50-300 nm thick and, more preferably, about 200-250 nm thick. It will be appreciated that, in cases where the layer 120 is a photoresist, this thickness can vary depending upon the wavelength of light used to pattern the layer 120. A thickness of about 50-300 nm thick and, more preferably, about 200-250 nm thick is particularly advantageous for 248 nm wavelength systems. [0048] The hard mask layer 130 is preferably about 10-40 nm thick and, more preferably, about 15-30 nm thick. The temporary layer 140 is preferably about 50-200 nm thick and, more preferably, about 80-120 nm thick. Because spacers 175 are formed around mandrels 124 b (FIG. 9A), which are formed from the temporary layer 140, and because the spacers 175 are used as a mask in etching underlying material, the height of the spacers 175 is typically determined by the height of the mandrels 140. As a result, the height of the temporary layer 140 is preferably chosen to form spacers 175 with a height sufficient to account for removal of spacer material during etching of underlying material. It will be appreciated that the height of the spacers can be limited by the structural integrity and the aspect ratio of the spacers, since very tall spacers may collapse or otherwise deform. [0049] The various layers discussed herein can be formed by various methods known in the art. For example, spin-on-coating processes can be used to form photodefinable layers. Various deposition processes, such as sputtering, chemical vapor deposition or atomic layer deposition, can be used to form other layers, such as the hard mask layers. [0050] Preferably, a low temperature chemical vapor deposition (CVD) process is used to deposit the hard mask layer 130 or any other materials, e.g., a spacer material, over the temporary layer 140, especially in cases where the temporary layer 140 is formed of amorphous carbon. Preferably, materials are deposited on the temporary layer 140, or other layers formed of amorphous carbon, at temperatures of less than about 550° C. and, more preferably, less than about 450° C. and, most preferably, less than about 400° C. Such low temperature deposition processes advantageously prevent chemical or physical disruption of the amorphous carbon layer(s). [0051] The amorphous carbon layers described herein can be formed by chemical vapor deposition using a hydrocarbon compound, or mixtures of such compounds, as carbon precursors. Exemplary precursors include propylene, propyne, propane, butane, butylene, butadiene and acetelyne. A suitable method for forming amorphous carbon layers is described in U.S. Pat. No. 6,573,030 B1, issued to Fairbairn et al. on Jun. 3, 2003, the entire disclosure of which is incorporated herein by reference. In addition, the amorphous carbon may be doped. A suitable method for forming doped amorphous carbon is described in U.S. patent application Ser. No. 10/652,174 to Yin et al., filed Aug. 22, 2003, the entire disclosure of which is incorporated herein by reference. [0052] With reference to FIGS. 3A and 3B, a pattern comprising spaces or trenches 122, which are delimited by photodefinable material features 124, is formed in the photodefinable layer 120. The trenches 122 can be formed by, e.g., photolithography with 248 nm or 193 nm light, in which the layer 120 is exposed to radiation through a reticle and then developed. After being developed, the remaining photodefinable material, photoresist in the illustrated embodiment, forms mask features such as the illustrated lines 124 (shown in cross-section only). [0053] The pitch of the resulting lines 124 is equal to the sum of the width of a line 124 and the width of a neighboring space 122. To minimize the critical dimensions of features formed using this pattern of lines 124 and spaces 122, the pitch can be at or near the limits of the photolithographic technique used to pattern the photodefinable layer 120. For example, for photolithography utilizing 248 nm light, the pitch of the lines 124 can be about 100 nm. Thus, the pitch may be at the minimum pitch of the photolithographic technique and the spacer pattern discussed below can advantageously have a pitch below the minimum pitch of the photolithographic technique. Alternatively, because the margin of error for position and feature size typically increases as the limits of a photolithographic technique are approached, the lines 124 can be formed having larger feature sizes, e.g., 200 nm, to minimize errors in the positions and sizes of the lines 124. [0054] As shown in FIGS. 4A and 4B, the spaces 122 are preferably widened by etching the photoresist lines 124, to form modified spaces 122 a and lines 124 a. The photoresist lines 124 are preferably etched using an isotropic etch to “shrink” those features. Suitable etches include etches using an oxygen-containing plasma, e.g., a SO2/O2/N2/Ar, Cl2/O2/He or HBr/O2/N2 plasma. The extent of the etch is preferably selected so that the widths of the lines 124 a are substantially equal to the desired spacing between the later-formed spacers 175, as will be appreciated from the discussion below. For example, the width of the lines 124 can be reduced from about 80-120 nm to about 35-70 nm and, more preferably, about 40-50 nm. Advantageously, the width-reducing etch allows the lines 124 a to be narrower than would otherwise be possible using the photolithographic technique used to pattern the photodefinable layer 120. In addition, the etch can smooth the edges of the lines 124 a, thus improving the uniformity of those lines. While the critical dimensions of the lines 124 a can be etched below the resolution limits of the photolithographic technique, it will be appreciated that this etch does not alter the pitch of the spaces 122 a and lines 124 a, since the distance between identical points in these features remains the same. [0055] With reference to FIG. 5, the pattern in the (modified) photodefinable layer 120 a is transferred to the hard mask layer 130. This transfer is preferably accomplished using an anisotropic etch, such as an etch using a fluorocarbon plasma, although,a wet (isotropic) etch may also be suitable if the hard mask layer 130 is thin. Preferred fluorocarbon plasma etch chemistries include CFH3, CF2H2, CF3H and/or CF4/HBr for etching the illustrated DARC material. [0056] With reference to FIG. 6, the pattern in the photodefinable layer 120 a and the hard mask layer 130 is transferred to the temporary layer 140 to allow for deposition of a layer 170 of spacer material (FIG. 8). It has been found that the temperatures used for spacer material deposition are typically too high for photoresist to withstand. Thus, the pattern is preferably transferred from the photodefinable layer 120 a to the temporary layer 140, which is formed of a material that can withstand the process conditions for spacer material deposition and etch, discussed below. In addition to having higher heat resistance than photoresist, the material forming the temporary layer 140 is preferably selected such that it can be selectively removed relative to the material for the spacers 175 (FIGS. 9A and 9B), the spacers 275 (FIGS. 14A and 14B) and the underlying dielectric layer 150. As noted above, the layer 140 is preferably formed of amorphous carbon and, more preferably, transparent carbon. [0057] The pattern in the modified photodefinable layer 120 a is preferably transferred to the temporary layer 140 using a O2-containing plasma, e.g., a plasma containing SO2, O2 and Ar. Other suitable etch chemistries include a Cl2/O2/SiCl4 or SiCl4/O2/N2 or HBr/O2/N2/SiCl4-containing plasma. Advantageously, the SO2-containing plasma is used as it can etch carbon of the preferred temporary layer 140 at a rate greater than 20 times and, more preferably, greater than 40 times the rate that the hard mask layer 130 is etched. The etch chemistry is also preferably selective for the temporary layer 140 relative to the layer 150 or any intervening hard mask or etch stop layers (not shown) present between the layers 140 and 150. A suitable SO2-containing plasma is described in U.S. patent application Ser. No. 10/931,772 to Abatchev et al., filed Aug. 31, 2004, the entire disclosure of which is incorporate herein by reference. It will be appreciated that the SO2-containing plasma can simultaneously etch the temporary layer 140 and also remove the photodefinable layer 120 a. The resulting lines 124 b constitute the placeholders or mandrels along which a pattern of spacers 175 (FIGS. 9A and 9B) will be formed. [0058] With reference to FIG. 7, the hard mask layer 130 can be removed to facilitate later mask formation by leaving the mandrels 124 b exposed for subsequent etching (FIGS. 15A and 15B). The preferred hard mask layer 130 can be removed using a directional etch, or a wet etch with sufficient selectivity for the material of the layer 130, as known in the art. [0059] Next, as shown in FIG. 8, a layer 170 of spacer material is preferably blanket deposited conformally over exposed surfaces, including the dielectric layer layer 150 and the top and sidewalls of the temporary layer 140. The spacer material is preferably a material that can act as a mask for transferring a pattern to the underlying dielectric layer layer 150. The spacer material preferably: 1) can be deposited with good step coverage; 2) can be deposited at a temperature compatible with the temporary layer 140; and 3) can be selectively etched relative to the temporary layer 140 and the dielectric layer 150. Preferred materials include silicon, silicon oxides and silicon nitrides. In the illustrated embodiment, the spacer material is amorphous silicon, which provides particular advantages in combination with other selected materials of the masking stack. [0060] Preferred methods for spacer material deposition include chemical vapor deposition and atomic layer deposition. In one example, a plasma-enhanced CVD is used to deposit amorphous silicon by using SiH4 and He in an Applied Materials' Producer™ system. The thickness of the layer 170 is preferably determined based upon the desired width of the spacers 175 (FIGS. 9A-9B). For example, in the exemplary embodiment, the layer 170 is preferably deposited to a thickness of about 20-80 nm and, more preferably, about 50-75 nm. Preferably, the step coverage is about 80% or greater and, more preferably, about 90% or greater. [0061] With reference to FIGS. 9A and 9B, the amorphous silicon spacer layer 170 is then subjected to an anisotropic etch to remove spacer material from horizontal surfaces 180 of the partially formed integrated circuit 100. Such an etch, also known as a spacer etch, can be performed using, e.g., a HBr/Cl2-containing plasma. Thus, pitch multiplication has been accomplished to form spacers 175. In the illustrated embodiment, the pitch of the spacers 175 is roughly half that of the photoresist lines 124 and spaces 122 (FIGS. 3A-3B) originally formed by photolithography. Where the photoresist lines 124 had a pitch of about 200 nm, spacers 175 having a pitch of about 100 nm or less (for a width of about 50 nm) can be formed. It will be appreciated that because the spacers 175 are formed on the sidewalls of the features or lines 124 b, the spacers 175 generally follow the outline of the pattern of features or lines 124 a in the modified photodefinable layer 120 a and, so, typically form a closed loop in the spaces 122 a between the lines 124 a, as illustrated in FIG. 9B. [0062] Next, additional spacers are formed on a second level. The additional spacers are formed extending in a direction that is offset (non-parallel) from the direction in which the spacers 175 extend. Preferably, the mandrels 124 b on the first level remain in place during the formation of the additional spacers. [0063] To allow the additional spacers to be formed, a planar surface is formed by depositing a planarizing material which fills the spaces around (between and over) the spacers 175 to form a planarizing layer 200, as shown in FIGS. 10A-10B. The planarizing layer 200 is preferably at least as tall as the spacers 175 and, more preferably, is sufficiently tall to allow mandrels to be formed from the planarizing layer 200 and above the spacers 175, as discussed below. In addition, the planarizing layer 200 is preferably formed of a material selectively etchable relative to both the spacers 175, the spacers 275 (FIGS. 14A-14B) and the dielectric layer 150. More preferably, the planarization material is the same material as that used to form the mandrels 124 b. For example, the planarization material can be amorphous carbon and can be deposited as discussed above with respect to the layer 140 (FIG. 2A). In other embodiments, the planarization material and the mandrel material can be different materials or combinations of materials. [0064] It will be appreciated that, after forming the spacers 175, the mandrels 124 b are preferably retained between the spacers 175, thereby eliminating the need to deposit material into the spaces occupied by the mandrels 124 b. It will be appreciated that those spaces can be narrow and, given that substantially vertical spacer walls delimit the spaces occupied by the mandrels 124 b, the aspect ratio of the spaces can be large and deposition into those spaces can be difficult. Advantageously, retention of the mandrels 124 b eliminates the need for deposition into those spaces, thereby allowing the formation of a more conformal, uniform planarizing layer 200. [0065] Moreover, while the trenches 210 between the spacers 175 are of a similar width as the mandrels 124 b in the illustrated embodiment, deposition into the trenches 210 is less difficult than deposition into the space occupied by the mandrels 124 b, since the curved spacer surfaces 220 delimiting those trenches 210 advantageously facilitate deposition of the planarization material into those trenches 210. It will be appreciated that the curved spacer surfaces can effectively reduce the aspect ratio of the trenches 210 and/or aid in funneling deposition material or precursors into those trenches 210. [0066] After depositing the planarization material, which preferably acts as the mandrel material for a second set of mandrels, the planarizing or second mandrel layer 200 can optionally be subjected to a planarization process. Such a process can be desirable, e.g., if the planarizing layer 200 is not sufficiently flat to allow for high quality results in subsequent photolithography steps. For example, the planarizing layer 200 can be subjected to a chemical mechanical polishing (CMP). In other exemplary embodiments, one or more additional layers can be deposited and then etched and/or subjected to CMP to form a highly planar top surface. For example, a bottom anti-reflective coating (BARC) can be deposited and subjected to a dry etch to form a highly planar surface over the planarizing layer 200. In other embodiments, the planarization material can be a reflowable material such as borophosphosilicate glass or spin-on glass, which can be deposited and then subjected to an anneal to form a highly planar surface. Preferably, as discussed above, the planarization material is amorphous carbon, which is preferably deposited to a height sufficient to allow the formation of mandrels from the planarizing layer 200. [0067] With reference to FIG. 11, a sequence of layers 250-260 is deposited to allow patterning of mandrels in the planarizing layer 200. For example, a hard mask layer 250 comprising, e.g., a DARC, is deposited over the planarizing layer 200 and a photodefinable layer 260 comprising, e.g., a photoresist, is deposited over the hard mask layer 250. [0068] Preferably, applying again the steps discussed above with reference to FIGS. 2A-9B, the photoresist layer 260 can be etched, trimmed and the resulting pattern can be transferred to the hard mask layer 250 and then transferred to the planarizing layer 200 to form a pattern of mandrels 224, as shown in FIGS. 12A and 12B. [0069] With reference to FIG. 13, a spacer layer 270 is deposited around the mandrels 224. As noted above, the spacer layer 270 can be formed of any material having deposition and etch properties compatible with the other materials used herein. In the illustrated embodiment, the spacer material is silicon oxide which is preferably deposited at a temperature of less than about 550° C. and, more preferably, less than about 450° C. and, most preferably, less than about 400° C. The silicon oxide can be deposited by chemical vapor deposition, e.g., using O3 and TEOS in a deposition system such as Applied Materials' Producer® HARP™ system. Because a dimension of the contact vias 310 (FIGS. 17A-17B) to later be formed is dependent on the width of and the distance between the spacers 275 and because the thickness of the spacer layer 270 substantially corresponds to the width of the spacers 275 (FIGS. 14 a and 14B), the thickness of the spacer layer 270 is preferably chosen with reference to the distance between the mandrels 224 and with reference to the desired size of the contact vias to be formed using the spacers 275 as a mask. In the illustrated embodiment, the thickness of the spacer layer 270 is preferably about 50-75 nm to form contact vias having widths and lengths of about 50 nm. [0070] With reference to FIGS. 14A-14C, a spacer etch is performed to form the spacers 275, which are preferably orthogonal to the spacers 175. The spacer etch preferably comprises a fluorocarbon plasma, e.g., a CF4/CHF3, C4F8/CH2F2 or CHF3/Ar-containing plasma. FIG. 14A is a cross-sectional view, taken along a plane perpendicular to the length of the spacers 175, of the partially fabricated integrated circuit 100. FIG. 14B is a cross-sectional view, taken along a plane perpendicular to the length of the spacers 275, of the partially fabricated integrated circuit 100. FIG. 14C is a top view of the integrated circuit 100. [0071] With reference to FIGS. 15A-15C, the mandrels 224 and the planarizing layer 200 are preferably selectively anisotropically etched relative to the spacers 175 and 275. Examples of suitable etch chemistries are O2-containing plasmas, e.g., a SO2/O2/Ar, Cl2/O2/SiCl4, SiCl4O2/N2 or HBr/O2/N2/SiCl4-containing plasma. With ref 15A, it will be appreciated that the spacers 275 shield parts 200 a of the second planarizing or mandrel layer 200 from the etch. The unetched parts 200 a of the layer 200 support the spacers 275 above the level of the spacers 175. Thus, with reference to FIG. 15B, a pattern 300 comprising a matrix of orthogonal mask lines comprising the spacers 175 and 275 is formed above the dielectric layer 150. [0072] Next, the pattern 300 can be transferred to the underlying dielectric layer 150. [0073] With reference to FIGS. 16A-16E, the dielectric layer 150 is selectively etched relative to the spacers 175 and 275. In the illustrated embodiment, the lower or first spacers 175 act as a hard mask in a first lateral direction and the upper or second spacers 275 act as a hard mask in a second lateral direction orthogonal to the first direction. An example of a suitable etch for the dielectric layer 150 is an anisotropic etch comprising a fluorocarbon plasma, e.g., a CF4/CHF3, C4F8/CH2F2 or CHF3/Ar-containing plasma. It will be appreciated that if the spacers 275 and the dielectric layer 150 are formed of the same material, both materials will be etched when transferring the pattern 300 to the dielectric layer. Advantageously, if the spacers 275 are worn away, the parts 200 a of the planarizing, or second mandrel layer 200 that have the same pattern as the upper spacers 275 can function as another layer of hard mask material, thereby allowing the etch of the dielectric layer 150 to be completed. The dielectric layer 150 can be etched through, thereby forming voids 310 that extend to the substrate 160. With reference to FIG. 16B, the substrate 160 is visible in the top view and the lower spacers 175 and temporary layer parts 200 a overlie the unetched dielectric material 150 a (FIG. 16A) remaining from the dielectric layer 150. [0074] With reference to FIGS. 17A and 17B, the spacers 175 and parts 200 a can be removed. For example, the spacers 175 can be removed using an anisotropic etch comprising, e.g., a HBr/Cl2-containing plasma, and the parts 200 a can be removed using an anisotropic etch comprising an O2-containing plasma, e.g., a SO2/O2/Ar, Cl2/O2/SiCl4, SiCl4/O2/N2 or HBr/O2/N2/SiCl4-containing plasma. [0075] With reference to FIG. 18, the voids 310 can be filled with various materials, in various applications where voids, particularly arrays of voids, are desired. In some applications, contacts to various conductive features can be formed by filling the voids with a conductive material. For example, the substrate can comprise conductive interconnect lines, to which the voids 310 open to expose the conductive lines. Conductive plugs 320 can be formed by filling the voids 310 with a conductive material, e.g., a silicide, tungsten, doped polysilicon, titanium, tantalum, nickel and compounds thereof, including metal nitrides, such titanium nitride and titanium nitride tungsten compounds. The voids can be filled by various deposition processes, including, e.g., CVD. Advantageously, a self-directed, selective electrochemical deposition of metal into the voids 310 may also be accomplished by using the exposed conductive lines as a seed layer. [0076] In other non-limiting examples of applications, the voids 310 can be filled with phase change materials, which change conductivity with switchable changes in phase, in a process to form phase change memories or programmable conductor memories (PCRAM); filled with fusable materials (e.g., positively or negatively doped polysilicon or metals) in a process to form programmable read only memories (PROMs); etc. Phase change memories are memories having a material which can be switched between relatively conductive and insulating states by the application of heat. Examplary phase change materials include germanium, antimony and tellurium alloys (also referred to as GeSbT or GST). Programmable conductor RAM (PCRAM) are dendritic memories having a programmable conductor, e.g., chalcogenide glass doped with silver or other high mobility metal, which can be switched between a conductive and nonconductive state by the application of an electric field. For example, the conductors can cause shorts in the glass when an electric field is applied in one direction and can dissolve back into an insulating amorphous glass phase when an opposite electric field is applied. Fusable materials in PROMs can be used as fuses, which are retained or “blown” as desired to establish a desired conductive state in the memory. In other embodiments, electrical devices and/or parts thereof, such as capacitors, may be formed using the voids 310. [0077] It will be appreciated that the formation of patterns according to the preferred embodiments offers numerous advantages. For example, arrays of isolated features, e.g., voids, having widths and lengths of about 15-70 nm, more preferably, about 20-60 nm and, most preferably, about 30-55, can be formed using pitch multiplication. [0078] Moreover, the sizes of the voids can be substantially uniform, or the widths and lengths of the voids can be made to alternate between different sizes, e.g., two or three different sizes, by appropriately selecting the thickness of the spacers and the separation between the mandrels. It will be appreciated that the mandrels 140 (FIG. 9B) and 224 (FIG. 14B) and the separation between the spacers 175 (FIG. 9B) and 275 (FIG. 14B), respectively, determine the widths and/or lengths of columns and rows of voids 310 (FIG. 17B). Thus, by varying the sizes of the mandrels and/or the separation between the spacers 175 and 275, the sizes of the voids 310 can be made to alternate in a regular way. For example, by setting the separation between spacers 175 and 275 at one value and the width of the mandrels 130 and 224 at another value, a pattern of large squares (formed by the intersection of the separations between the spacers), relatively small rectangles (formed by the intersection of the separations between the spacers and the space occupied by the mandrels) and relatively smaller squares (formed by the intersection of the mandrels spaces), can be formed. [0079] In addition, the shape of the opening of the voids can advantageously be varied as desired. For example, squares can be formed by forming uniformly sized and spaced spacers on two levels. In other embodiments, rectangles can be formed by spacing spacers farther apart on one level than the other level. More generally, other parallelograms can be formed by forming the spacers 175 and 275 at an angle other than about 90° relative to one another (the angle as determined from a top down view of the spacers 175 and 275). Moreover, openings of other shapes can be formed by using more than two levels of spacers. For example, by forming two additional levels of spacers, each forming an angle of about 45° relative to existing spacers, octagon-shaped voids can be formed. [0080] It will also be appreciated that various modifications of the illustrated embodiments are possible. For example, while two levels of spacers are illustrated for ease of description, more than two levels of spacers can be formed, as noted above. Moreover, while the dielectric layer 150 is illustrated as a single layer of a single material for ease of illustration and description, the dielectric layer 150 can comprise multiple stratified materials and/or different materials embedded within one or more levels of material(s). In such cases, if necessary, multiple etches may be utilized to etch through the various layers. In some embodiments, to facilitate the etch of the layer 150, the pattern formed by the spacers 175 and 275 can be transferred to another hard mask layer which has a high etch selectivity relative to the material(s) of the layer 150. Such a hard mask layer can comprise, e.g., amorphous carbon, which as a high etch selectivity relative to many of the materials discussed herein. In addition, while formed of a dielectric in the illustrated embodiment, the layer 150 can comprise other materials, which may be insulating and/or conducting, or the mask may be formed directly on the substrate 160. [0081] The layer 150 can also be etched through the open spaces between the overlapping spacers 175 and 275 or the material exposed by the open spaces can be retained and the material underlying the spacers 175 and 275 can be selectively removed to form a pattern of pillars. For example, an inverse mask pattern to that of FIG. 15B can be formed by depositing a material into the open spaces and etching back (e.g., by CMP), and the spacers 175 and 275 and the temporary layer material 200 a can be removed to leave a pattern of mask pillars for etching the layer 150. In other embodiments, a material underlying the spacers 175 and 275 can be selectively converted to another material (e.g., by cross-linking or photo-developing) through the open spaces and the unconverted material can be removed to form a pattern of pillars. In some embodiments, the pillars can be the final structures and in other embodiments, these pillars can comprise a hard mask material for etching an underlying material, such as the layer 150. [0082] It will be appreciated that pitch multiplied patterns typically form closed loops, since the patterns are formed by spacers that are formed along the wall of a mandrel, e.g., around the exterior of a free-standing mandrel or in the interior of a cavity, along the walls of mandrels delimiting the cavity. Preferably, the dimensions and placement of the spacers on the various levels are chosen such that the ends of the closed loops overlap the peripheral spacers (e.g., the first or the last) of an overlying or underlying set of spacers, as shown in FIGS. 15C and 16E. Thus, a pattern of regularly spaced and dimensioned spacers can be formed. In other embodiments, the ends of the spacer loops may be formed protruding beyond the peripheral spacers. In such cases, additional processing steps can be used to cut off the ends of these loops, so that each loop forms two individual, non-connected lines. This can be accomplished, for example, by forming a protective mask around the parts of the lines to be maintained, while etching away the unprotected ends of the masks. A suitable method for cutting off the ends of the loops is disclosed in U.S. patent application Ser. No. 10/931,771 to Tran et al., filed Aug. 31, 2004, the entire disclosure of which is incorporated be reference herein. [0083] It will also be appreciated that the spacers 175 and 275 can be more than pitch doubled. For example, the spacers 175 can be further pitch multiplied by forming spacers around the spacers 175, then removing the spacers 175, then forming spacers around the spacers that were formerly around the spacers 175, and so on. In this case, the width of the spacers 175, rather than the width of the mandrels 124 b determine one of the dimensions of isolated features that may be formed using the spacer pattern. An exemplary method for further pitch multiplication is discussed in U.S. Pat. No. 5,328,810 to Lowrey et al. [0084] In addition, the preferred embodiments can be employed multiple times throughout an integrated circuit fabrication process to form pitch multiplied features in a plurality of layers or vertical levels, which may be vertically contiguous or non-contiguous and vertically separated. In such cases, each of the individual levels to be patterned would constitute a dielectric layer 150 and the various layers 120-260 can be formed over the individual level to be patterned. [0085] Also, while processing through the various mask layers preferably involves etching an underlying layer, processing through the mask layers can involve subjecting layers underlying the mask layers to any semiconductor fabrication process. For example, processing through the resultant mask can involve ion implantation, diffusion doping, depositing, or wet etching, etc. through the mask layers and onto underlying layers. In addition, the mask layers can be used as a stop or barrier for chemical mechanical polishing (CMP) or CMP can be performed on any of the layers to allow for both planarization and etching of the underlying layers, as discussed in U.S. Provisional Patent Application No. 60/666,031, filed Mar. 28, 2005, the entire disclosure of which is incorporated by reference herein. [0086] Accordingly, it will be appreciated by those skilled in the art that various other omissions, additions and modifications may be made to the methods and structures described above without departing from the scope of the invention. All such modifications and changes are intended to fall within the scope of the invention, as defined by the appended claims. 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ClassificationH01L21/4763Cooperative ClassificationH01L45/144, H01L21/0338, H01L21/76816, H01L21/0337, H01L45/1683, H01L21/31144, H01L45/085, H01L45/06European ClassificationH01L45/14B6, H01L45/16D2, H01L45/04, H01L27/24F4, H01L27/24F, H01L45/14, H01L45/08M, H01L45/16P4, H01L45/06, H01L21/311D, H01L21/033F4, H01L21/033F6, H01L21/768B2L, H01L27/24Legal EventsDateCodeEventDescriptionSep 1, 2005ASAssignmentOwner name: MICRON TECHNOLOGY, INC., IDAHOFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRAN, LUAN C.;REEL/FRAME:016961/0065Effective date: 20050901Dec 27, 2013FPAYFee paymentYear of fee payment: 4May 12, 2016ASAssignmentOwner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENFree format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001Effective date: 20160426Jun 2, 2016ASAssignmentOwner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERALFree format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, 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