Source: http://www.google.com/patents/US7962830?dq=6514640
Timestamp: 2017-03-28 18:12:26
Document Index: 495797232

Matched Legal Cases: ['Application No. 2457420', 'Application No. 2456485', 'Application No. 03132884', 'Application No. 03763216', 'Application No. 05789316', 'Application No. 03254214', 'Application No. 10001217', 'Application No. 03763495', 'Application No. 2004', 'Application No. 03763495', 'Application No. 05789316']

Patent US7962830 - Method and system for routing in low density parity check (LDPC) decoders - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to generate the LDPC coded signal are retrieved from memory. The edge values specify the relationship of bit nodes and check nodes, and are stored within...http://www.google.com/patents/US7962830?utm_source=gb-gplus-sharePatent US7962830 - Method and system for routing in low density parity check (LDPC) decodersAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7962830 B2Publication typeGrantApplication numberUS 11/710,761Publication dateJun 14, 2011Filing dateFeb 26, 2007Priority dateJul 3, 2002Fee statusPaidAlso published asUS7577207, US8102947, US8291293, US8615699, US20050271160, US20070168834, US20100107032, US20110239086, US20130091406Publication number11710761, 710761, US 7962830 B2, US 7962830B2, US-B2-7962830, US7962830 B2, US7962830B2InventorsMustafa Eroz, Lin-nan Lee, Feng-Wen Sun, Bob Cassagnol, Adam Von AnckenOriginal AssigneeDtvg Licensing, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (96), Non-Patent Citations (83), Referenced by (15), Classifications (33), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for routing in low density parity check (LDPC) decoders
US 7962830 B2Abstract
a 10 i 0 +a 11 i 1 + . . . +a 1,k−1 i k−1 +b 10 p 0 +p 1=0 Solve p1 and similarly for p2,p3, . . . ,pn−k−1. FIG. 7 is a graph showing performance between codes utilizing unrestricted parity check matrix (H matrix) versus restricted H matrix of FIG. 6. The graph shows the performance comparison between two LDPC codes: one with a general parity check matrix and the other with a parity check matrix restricted to be lower triangular to simplify encoding. The modulation scheme, for this simulation, is 8-PSK. The performance loss is within 0.1 dB. Therefore, the performance loss is negligible based on the restriction of the lower triangular H matrices, while the gain in simplicity of the encoding technique is significant. Accordingly, any parity check matrix that is equivalent to a lower triangular or upper triangular under row and/or column permutation can be utilized for the same purpose.
*p0=x0+x1+x2 p4=y0+x1+x2 p1=x0+x1+y2 p5=y0+x1+y2 p2=x0+y1+x2 p6=y0+y1+x2 p3=x0+y1+y2 p7=y0+y1+y2 Next, the bit metric generator 307 determines a priori log likelihood ratios of the coded bits as input to LDPC decoder 305, as follows:
u 0=ƒ(d 0 +p 0 ,d 1 +p 1 d 2 +p 2 ,d 3 +p 3)−ƒ(d 4 +p 4 ,d 5 +p 5 ,d 6 +p 6 ,d 7 +p 7)−e 0 u 1=ƒ(d 0 +p 0 ,d 1 +p 1 ,d 4 +p 4 ,d 5 +p 5)−ƒ(d 2 +p 2 ,d 3 +p 3 ,d 6 +p 6 ,d 7 +p 7)−e 1 u 2=ƒ(d 0 +p 0 ,d 2 +p 2 ,d 4 +p 4 ,d 6 +p 6)−ƒ(d 1 +p 1 ,d 3 +p 3 ,d 5 +p 5 ,d 7 +p 7)−e 2 It is noted that the function ƒ(.) with more than two variables can be evaluated recursively; e.g. ƒ(a,b,c)=ƒ(ƒ(a,b),c).
v n → k i = u n , n=0,1, . . . , N−1,i=1,2, . . . , deg(bit node n)
v n → k i denotes the message that goes from bit node n to its adjacent check node ki, un denotes the demodulator output for the bit n and N is the codeword size.
v n 1 → k , v n 2 → k , … , v n d c → k . The goal is to compute the outgoing messages from the check node k back to dc adjacent bit nodes. These messages are denoted by
w k → n 1 , w k → n 2 , … , w k → n d c , where w k → n i = g ( v n 1 → k , v n 2 → k , … , v n i - 1 → k , v n i + 1 → k , … , v n d c → k ) . The function g( ) is defined as follows:
w k 1 → n , w k 2 → n , … , w k d v → n The outgoing messages from the bit node n are computed back to dv adjacent check nodes; such messages are denoted by
v n → k 1 , v n → k 2 , … , v n → k d v , and computed as follows:
v n 1 → k , v n 2 → k , … , v n d c → k . It is desired that the outgoing messages are computed from the check node k back to dc adjacent bit nodes; these outgoing messages are denoted by
ƒ1=v1→k ƒ2 =g(ƒ1 ,v 2→k)
bdc=vdc→k b dc−1 =g(b dc ,v dc−1→k)
wk→1=b2 w k→i =g(ƒi−1 ,v i+1)=2,3, . . . ,d c−1
w k→dc=ƒdc−1 Under this approach, only the forward variables, ƒ2, ƒ3, . . . , ƒdc, are required to be stored. As the backward variables bi are computed, the outgoing messages, wk→i, are simultaneously computed, thereby negating the need for storage of the backward variables.
v n 1 → k , v n 2 → k , … , v n d c → k from dc adjacent bit nodes, the following parameter is computed, as in step 1311:
w k → n i can be solved in the following manner:
w k → n i for all ni can occur in parallel using the above equation, per step 1315.
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