Source: https://patents.google.com/patent/JP2013021102A/en
Timestamp: 2020-07-04 00:34:41
Document Index: 148236966

Matched Legal Cases: ['arts 16', 'arts 17', 'art.\n1', 'art 16', 'art 17', 'art, 17', 'art, 18']

JP2013021102A - Semiconductor storage device - Google Patents
JP2013021102A
JP2013021102A JP2011152672A JP2011152672A JP2013021102A JP 2013021102 A JP2013021102 A JP 2013021102A JP 2011152672 A JP2011152672 A JP 2011152672A JP 2011152672 A JP2011152672 A JP 2011152672A JP 2013021102 A JP2013021102 A JP 2013021102A
JP2011152672A
弘康 佐藤
清仁 西原
Hidefumi Nawata
秀文 縄田
正之 市毛
Ryuji Oba
2011-07-11 Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
2011-07-11 Priority to JP2011152672A priority Critical patent/JP2013021102A/en
2013-01-31 Publication of JP2013021102A publication Critical patent/JP2013021102A/en
PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can suppress interference between floating gate electrodes while ensuring coupling between a control gate electrode and the floating gate electrode.SOLUTION: The semiconductor storage device comprises: tunnel films 13 each provided on an active area 12; floating gate electrodes 14 each provided on the tunnel film; an interelectrode insulation film 18 provided on the floating gate electrodes and extending in a second direction intersecting a first direction; a control gate electrode 19; lower side insulation parts 16 provided between the active areas neighboring to each other in the second direction, between the tunnel films neighboring to each other in the second direction and between the floating gate electrodes neighboring to each other in the second direction; and upper side insulation parts 17 each provided between the lower side insulation part and the interelectrode insulation film and each having a top face located above a top face of the floating gate electrode. The lower side insulation part has a gas portion. Relative permittivity of the upper side insulation part is higher than that of the lower side insulation part. Relative permittivity of the interelectrode insulation film is higher than that of the upper side insulation part.
Conventionally, NAND flash memories have been developed as nonvolatile semiconductor memory devices. In the NAND flash memory, an STI (shallow trench isolation) extending in one direction is formed on an upper portion of a silicon substrate, and the upper portion of the silicon substrate is divided into a plurality of active areas by the STI. A tunnel film is provided on each active area, a floating gate electrode is provided on the tunnel film, and an interelectrode insulating film is provided so as to cover a plurality of floating gate electrodes provided on different active areas. A control gate electrode is provided on the intermediate insulating film. Then, by controlling the potential of the control gate electrode, charges are taken in and out of the floating gate electrode from the active area through the tunnel film, and information is stored. However, as the NAND flash memory is highly integrated, the distance between the floating gate electrodes is shortened, and it is difficult to suppress interference between the floating gate electrodes.
JP 2007-250565 A
An object of the present invention is to provide a semiconductor memory device capable of suppressing interference between floating gate electrodes while ensuring coupling between a control gate electrode and the floating gate electrode.
A semiconductor memory device according to an embodiment includes a semiconductor substrate having an upper portion divided into a plurality of active areas extending in a first direction, a tunnel film provided on the active area, and a floating film provided on the tunnel film. A gate electrode, an interelectrode insulating film provided on the floating gate electrode and extending in a second direction intersecting the first direction; and a control provided on the interelectrode insulating film and extending in the second direction A gate electrode, a lower insulating portion provided between the active areas adjacent in the second direction, between the tunnel films, and between the floating gate electrodes, and between the lower insulating portion and the inter-electrode insulating film And an upper insulating portion whose upper surface is located above the upper surface of the floating gate electrode. The lower insulating portion has a gas portion. The relative dielectric constant of the upper insulating part is higher than that of the lower insulating part, and the relative dielectric constant of the interelectrode insulating film is higher than that of the upper insulating part.
1 is a cross-sectional view illustrating a semiconductor memory device according to a first embodiment. (A) is sectional drawing which illustrates the semiconductor memory device which concerns on a 1st comparative example, (b) is a figure which illustrates the simulation result of an electric force line. It is sectional drawing which illustrates the semiconductor memory device which concerns on a 2nd comparative example. 6 is a cross-sectional view illustrating a semiconductor memory device according to a second embodiment; FIG. 6 is a cross-sectional view illustrating a semiconductor memory device according to a third embodiment; FIG. FIG. 6 is a cross-sectional view illustrating a semiconductor memory device according to a fourth embodiment. 10A to 10C are process cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the fifth embodiment. 10A to 10C are process cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the fifth embodiment. FIG. 9 is a cross-sectional view illustrating a semiconductor memory device according to a sixth embodiment.
The semiconductor memory device according to the present embodiment is a NAND flash memory.
FIG. 1 is a cross-sectional view illustrating a semiconductor memory device according to this embodiment.
As shown in FIG. 1, in the semiconductor memory device 1 according to the present embodiment, a silicon substrate 10 is provided. A trench 11 extending in one direction (hereinafter referred to as “AA direction”) is formed in the upper portion of the silicon substrate 10, and the upper portion of the silicon substrate 10 is divided into a plurality of active areas 12 by the trench 11. Yes. Each active area 12 extends along the AA direction.
A tunnel film 13 is provided on each active area 12. The lower surface of the tunnel film 13 is in contact with the upper surface of the active area 12. The tunnel film 13 is a film that allows a tunnel current to flow when a predetermined voltage within the drive voltage range of the semiconductor memory device 1 is applied, and is formed of an insulating material such as silicon oxide. The tunnel film 13 may be a multilayer film, for example, an ONO film.
A floating gate electrode 14 is provided on the tunnel film 13. The lower surface of the floating gate electrode 14 is in contact with the upper surface of the tunnel film 13. The floating gate electrode 14 is disposed immediately above the active area 12 and is divided in the AA direction. For this reason, in the semiconductor memory device 1, as viewed from above, the plurality of floating gate electrodes 14 are arranged in a matrix along the AA direction and a direction orthogonal to the AA direction (hereinafter referred to as “CG direction”). The floating gate electrode 14 is made of a conductive material, for example, polysilicon doped with impurities, a metal such as titanium or tungsten, or a metal nitride such as titanium nitride or tungsten nitride. The floating gate electrode 14 is surrounded by an insulating material and is in an electrically floating state.
Provided in the trench 11, that is, between the adjacent active areas 12, between the tunnel films 13 provided immediately above these active areas 12, and immediately above these active areas 12, respectively. A lower insulating portion 16 is provided between the floating gate electrodes 14. The lower insulating portion 16 is insulative as a whole, but is not necessarily constituted by a single member. A gas portion (not shown) is formed in at least a part of the lower insulating portion 16. The gas portion is a cavity in which a gas such as the atmosphere exists and is called an air gap.
An upper insulating portion 17 is provided immediately above the lower insulating portion 16. The upper insulating portion 17 is made of, for example, a single insulating material, and is made of, for example, silicon oxide, silicon nitride, or silicate. The interface 20 between the lower insulating portion 16 and the upper insulating portion 17 is located at the same height as the upper surface of the floating gate electrode 14. Therefore, the upper surface of the upper insulating portion 17 is located above the upper surface of the floating gate electrode 14.
An interelectrode insulating film 18 is provided above the floating gate electrode 14 and the upper insulating portion 17 so as to cover them. Each interelectrode insulating film 18 extends in the CG direction so as to connect a region directly above the floating gate electrode 14, and is in contact with the floating gate electrode 14 and the upper insulating portion 17. Therefore, the upper insulating portion 17 is provided between the lower insulating portion 16 and the interelectrode insulating film 18. The interelectrode insulating film 18 is formed of a high dielectric constant material, for example, a metal oxide such as lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium oxide, hafnium aluminum oxide, or aluminum oxide. Yes. In addition to these metal oxides, a silicate containing silicon, for example, lanthanum silicate, lanthanum aluminum silicate, lanthanum hafnium silicate, hafnium silicate, hafnium aluminum silicate, aluminum silicate, or the like may be used. However, when silicate is used for both the interelectrode insulating film 18 and the upper insulating portion 17, the concentration of the metal element in the interelectrode insulating film 18 is made higher than the concentration of the metal element in the upper insulating portion 17.
A control gate electrode 19 is provided immediately above each interelectrode insulating film 18. The shape of the control gate electrode 19 is a stripe shape and extends in the CG direction. The control gate electrode 19 is in contact with the interelectrode insulating film 18. The control gate electrode 19 is made of, for example, metal.
An interlayer insulating film (not shown) is provided on the control gate electrode 19. The interlayer insulating film covers a plurality of control gate electrodes 19 arranged along the AA direction. However, a gas portion (not shown) is disposed between the floating gate electrodes 14 adjacent in the AA direction. On the interlayer insulating film, a source line (not shown) extending in the CG direction and a bit line (not shown) extending in the AA direction are provided.
The relative dielectric constant ε2 of the upper insulating portion 17 is higher than the relative dielectric constant ε3 of the lower insulating portion 16, and the relative dielectric constant ε1 of the interelectrode insulating film 18 is higher than the relative dielectric constant ε2 of the upper insulating portion 17. high. That is, ε1> ε2> ε3. As described above, the interelectrode insulating film 18 is made of, for example, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium oxide, hafnium aluminum oxide, or aluminum oxide, and its relative dielectric constant ε1. Is for example 12-40, for example about 30. The upper insulating portion 17 is made of silicon oxide, silicon nitride, or silicate, and has a relative dielectric constant ε2 of 3 to 11, for example, 7. The lower insulating portion 16 includes a gas portion, and the relative dielectric constant ε3 of the entire lower insulating portion 16 is, for example, 1 to 3. When the entire lower insulating portion 16 is a gas portion, the relative dielectric constant ε3 is about 1.
In the semiconductor memory device 1 according to this embodiment, the lower insulating portion 16 is provided between the floating gate electrodes 14 adjacent in the CG direction. Since at least a part of the lower insulating portion 16 is provided with a gas portion, the lower insulating portion 16 as a whole has a low relative dielectric constant ε3. For this reason, interference between the floating gate electrodes 14 adjacent in the CG direction can be suppressed.
In the semiconductor memory device 1, an interelectrode insulating film 18 is provided between the floating gate electrode 14 and the control gate electrode 19. Since the interelectrode insulating film 18 is formed of a high dielectric constant material such as lanthanum oxide, the relative dielectric constant ε1 is high. Therefore, a high coupling ratio (CR) can be realized between the control gate electrode 19 and the floating gate electrode 14.
An upper insulating portion 17 is provided immediately above the floating gate electrode 14 adjacent in the CG direction and between the floating gate electrode 14 and the control gate electrode 19. The relative dielectric constant ε2 of the upper insulating portion 17 is higher than the relative dielectric constant ε3 of the lower insulating portion 16, and lower than the relative dielectric constant ε1 of the interelectrode insulating film 18. Thereby, interference between the floating gate electrodes 14 can be suppressed while ensuring a coupling rate between the control gate electrode 19 and the floating gate electrode 14. As a result, even when the semiconductor memory device 1 is highly integrated, charges can be efficiently injected and extracted from the floating gate electrode 14 by the control gate electrode 19, and the data writing operation and the erasing operation can be reliably performed. can do. In addition, since the charge injected into a certain floating gate electrode 14 can be prevented from leaking along with the operation of the adjacent floating gate electrode 14, the written data can be reliably held. Thereby, even if the semiconductor memory device 1 is highly integrated, operational reliability can be ensured.
That is, the greater the difference between the relative dielectric constants ε1, ε2, and ε3, the higher the effect. In the present embodiment, since the lower insulating portion 16 includes a gas portion, the relative dielectric constant ε3 can take a value close to 1, which is effective.
In the semiconductor memory device 1, since the gas portion is also disposed between the floating gate electrodes 14 adjacent in the AA direction, interference can be prevented between these floating gate electrodes 14.
Next, a first comparative example will be described.
FIG. 2A is a cross-sectional view illustrating a semiconductor memory device according to this comparative example, and FIG. 2B is a diagram illustrating a simulation result of lines of electric force.
As shown in FIG. 2A, in the semiconductor memory device 101 according to this comparative example, unlike the semiconductor memory device 1 according to the first embodiment described above (see FIG. 1), the lower insulating portion 116 is provided. The STI is made of silicon oxide. Further, the inter-electrode insulating film 18 made of a high dielectric constant material is also disposed at a position where the upper insulating portion 17 is not provided and the upper insulating portion 17 is provided in the first embodiment.
FIG. 2B shows a region A shown in FIG. 2A. The potential of the control gate electrode 19 is set to 0 V, the potential of a certain floating gate electrode 14a is set to 2 V, and viewed from the floating gate electrode 14a. The simulation results of the lines of electric force generated between these electrodes when the potential of the floating gate electrode 14b arranged adjacently in the CG direction is 0V are shown.
As shown in FIG. 2B, in the semiconductor memory device 101, many lines of electric force are generated between the control gate electrode 19 and the floating gate electrode 14a, and a good coupling rate is obtained. Yes. However, a large number of lines of electric force are generated between the floating gate electrode 14a and the floating gate electrode 14b via the lower insulating portion 116 and the interelectrode insulating film 18, and interference occurs. For this reason, in the semiconductor memory device 101 according to this comparative example, the charge retention characteristics of the floating gate electrode 14 are low. In particular, when the semiconductor memory device 101 is highly integrated, this problem becomes significant.
Next, a second comparative example will be described.
FIG. 3 is a cross-sectional view illustrating a semiconductor memory device according to this comparative example.
As shown in FIG. 3, in the semiconductor memory device 102 according to this comparative example, the upper insulating portion 17 (see FIG. 1) is different from the semiconductor memory device 1 (see FIG. 1) according to the first embodiment described above. Is not provided, and the lower insulating portion 16 is also disposed at a position where the upper insulating portion 17 is provided in the first embodiment.
In this comparative example, since the lower insulating portion 16 having a low relative dielectric constant is provided, interference between adjacent floating gate electrodes 14 in the CG direction can be suppressed. However, since the lower insulating portion 16 is also interposed in a part of the space between the control gate electrode 19 and the floating gate electrode 14, the coupling rate between the control gate electrode 19 and the floating gate electrode 14 is high. Low. For this reason, in the semiconductor memory device 102 according to this comparative example, the write / erase characteristics with respect to the floating gate electrode 14 are low. In particular, when the semiconductor memory device 102 is highly integrated, this problem becomes remarkable.
FIG. 4 is a cross-sectional view illustrating a semiconductor memory device according to this embodiment.
As shown in FIG. 4, in the semiconductor memory device 2 according to the present embodiment, the interface 20 between the lower insulating portion 16 and the upper insulating portion 17 is located above the upper surface of the floating gate electrode 14.
Thereby, interference between the floating gate electrodes 14 can be more effectively suppressed as compared with the semiconductor memory device 1 (see FIG. 1) according to the first embodiment described above. However, the coupling rate between the control gate electrode 19 and the floating gate electrode 14 is higher in the semiconductor memory device 1. That is, by selecting the position of the interface 20 between the lower insulating portion 16 and the upper insulating portion 17, the effect of suppressing the interference between the floating gate electrodes 14 and the cup between the control gate electrode 19 and the floating gate electrode 14. The balance with the effect of increasing the ring rate can be adjusted. Configurations and operational effects other than those described above in the present embodiment are the same as those in the first embodiment described above.
FIG. 5 is a cross-sectional view illustrating a semiconductor memory device according to this embodiment.
As shown in FIG. 5, in the semiconductor memory device 3 according to the present embodiment, the interface 20 between the lower insulating portion 16 and the upper insulating portion 17 is located below the upper surface of the floating gate electrode 14.
Thereby, the coupling rate between the control gate electrode 19 and the floating gate electrode 14 can be further increased as compared with the semiconductor memory device 1 (see FIG. 1) according to the first embodiment described above. However, the effect of suppressing interference between the floating gate electrodes 14 is higher in the semiconductor memory device 1. That is, as in the second embodiment described above, the balance of characteristics can be controlled by selecting the position of the interface 20. Configurations and operational effects other than those described above in the present embodiment are the same as those in the first embodiment described above.
FIG. 6 is a cross-sectional view illustrating a semiconductor memory device according to this embodiment.
As shown in FIG. 6, in the semiconductor memory device 4 according to the present embodiment, a part of the upper insulating portion 17 is compared with the semiconductor memory device 1 (see FIG. 1) according to the first embodiment described above. The difference is that the floating gate electrode 14 protrudes to the region immediately above both ends in the CG direction. Thereby, both ends of the floating gate electrode 14 in the CG direction are covered with the overhanging portions 17 a of the upper insulating portion 17. On the other hand, in the upper surface of the floating gate electrode 14, the central portion in the CG direction is not covered by the upper insulating portion 17 and is in contact with the interelectrode insulating film 18.
In the present embodiment, the corner portion between the upper surface of the floating gate electrode 14 and the side surface facing the CG direction is covered with the upper insulating portion 17. Since the overhanging portion 17a of the upper insulating portion 17 is disposed at a position where the lines of electric force concentrate in FIG. 2B, it is compared with the semiconductor memory device 1 according to the first embodiment (see FIG. 1). Thus, interference between adjacent floating gate electrodes 14 can be more effectively suppressed. Configurations and operational effects other than those described above in the present embodiment are the same as those in the first embodiment described above.
This embodiment is a specific example of the method for manufacturing the semiconductor memory device according to the fourth embodiment described above.
7A to 7C and 8A to 8C are process cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to this embodiment.
First, as shown in FIG. 7A, a silicon substrate 10 made of single crystal silicon is prepared. Next, a tunnel film 13 made of, for example, silicon oxide is formed on the entire surface of the silicon substrate 10. Next, for example, polysilicon doped with impurities is deposited on the entire surface of the tunnel film 13 to form the floating gate electrode 14. At this stage, the tunnel film 13 and the floating gate electrode 14 are not divided and are continuous films.
Next, a plurality of trenches 11 extending in the AA direction are formed in the structure in which the tunnel film 13 and the floating gate electrode 14 are stacked on the silicon substrate 10. Thereby, the floating gate electrode 14 and the tunnel film 13 are divided into a plurality of stripe-shaped portions extending in the AA direction, and the upper portion of the silicon substrate 10 is divided into a plurality of active areas 12 extending in the AA direction.
Next, a silicon oxide film 21 is formed on the entire surface. The silicon oxide film 21 is formed on the inner surface of the trench 11 and the upper surface of the floating gate electrode 14. Next, a silicon nitride film 22 is deposited on the entire surface. The silicon nitride film 22 is formed relatively thick on the upper surface of the floating gate electrode 14 and the side surface of the upper end portion of the trench 11, and is formed relatively thin on the inner surface of a portion other than the upper end portion of the trench 11. The As a result, at the upper end of the trench 11, the silicon nitride film 22 protrudes in a hook shape in a direction approaching each other. As a result, the opening width at the upper end portion of the trench 11 is narrower than the width of the portion other than the upper end portion of the trench 11.
Next, as shown in FIG. 7B, RIE (reactive ion etching) is performed to etch back the silicon nitride film 22. As a result, the portion of the silicon nitride film 22 deposited on the upper surface of the floating gate electrode 14 and the portion deposited on the bottom surface of the trench 11 are removed. As a result, the silicon oxide film 21 is exposed on the upper surface of the floating gate electrode 14 and the bottom surface of the trench 11. On the other hand, a portion of the silicon nitride film 22 deposited on the side surface of the trench 11 remains.
Next, for example, by performing wet etching using hydrofluoric acid, the exposed portion of the silicon oxide film 21, that is, the portion covering the upper portion of the floating gate electrode 14 and the portion deposited on the bottom surface of the trench 11 are removed. . As a result, the upper portion of the floating gate electrode 14 is exposed, and the silicon substrate 10 is exposed at the bottom surface of the trench 11. At this time, the upper end portion of the remaining silicon nitride film 22, that is, the portion protruding in a bowl shape in the region immediately above the trench 11 is located above the upper surface of the floating gate electrode 14.
Next, as shown in FIG. 7C, a silicon oxide film 23 is deposited by depositing silicon oxide on the entire surface by a method having a relatively high coverage, for example, an ALD (atomic layer deposition) method. Form. The silicon oxide film 23 is formed on the inner surface of the trench 11 and the upper surface of the floating gate electrode 14, and covers the silicon nitride film 22 protruding in a bowl shape at the upper end portion of the trench 11. Before the silicon oxide film 23 fills the inside of the trench 11, portions of the silicon oxide film 23 covering the silicon nitride films 22 facing each other in the region directly above the trench 11 are in contact with each other, and the upper end of the trench 11 is contacted. Block the part. As a result, a gas portion 29 is formed in the trench 11.
At this time, since the upper end portion of the silicon nitride film 22 is located above the upper surface of the floating gate electrode 14, the region located immediately above the trench 11 in the upper surface of the silicon oxide film 23 is floating. It is located above the region located immediately above the gate electrode 14. Thereby, irregularities are formed on the upper surface of the silicon oxide film 23.
Next, as shown in FIG. 8A, a silicon oxide film is deposited by depositing silicon oxide on the entire surface by a method with a relatively low coverage, for example, a CVD (chemical vapor deposition) method. 24 is formed. At this time, since the upper end portion of the trench 11 is blocked by the silicon oxide film 23, the silicon oxide film 24 does not enter the trench 11. Further, unevenness reflecting the shape of the silicon oxide film 23 is formed on the upper surface of the silicon oxide film 24. That is, in the upper surface of the silicon oxide film 24, a region corresponding to the region directly above the trench 11 is a convex portion, and a region corresponding to the region immediately above the floating gate electrode 14 is a concave portion.
Next, as shown in FIG. 8B, RIE is performed, and the silicon oxide films 24 and 23 are etched back. At this time, the upper surfaces of the silicon oxide films 24 and 23 recede while retaining the unevenness before starting RIE. As a result, the silicon oxide film 23 remains in the region immediately above the trench 11 that was a convex portion before the start of RIE and the region directly above both ends in the CG direction of the floating gate electrode 14, and the floating portion that was a concave portion before the start of RIE. In the region immediately above the central portion of the gate electrode 14 in the CG direction, the silicon oxide film 23 is removed and the floating gate electrode 14 is exposed. The silicon oxide film 24 is almost entirely removed.
Next, as shown in FIG. 8C, for example, lanthanum oxide is deposited to form the interelectrode insulating film 18. The interelectrode insulating film 18 covers the remaining portion of the silicon oxide film 23 and is in contact with the upper surface of the floating gate electrode 14 at the central portion in the CG direction. Next, for example, metal is deposited to form the control gate electrode 19. Next, a resist mask (not shown) is formed by lithography, and RIE is performed using the resist mask as a mask, thereby controlling gate electrode 19, interelectrode insulating film 18, silicon oxide film 23, silicon nitride film 22, and floating gate. The electrode 14 is selectively removed and divided into striped portions extending in the CG direction. Next, an interlayer insulating film (not shown) is formed on the entire surface, and a source line (not shown) and a bit line (not shown) are formed. Thereby, the semiconductor memory device 5 according to this embodiment is manufactured.
In the semiconductor memory device 5, the structure formed in the trench 11, that is, the silicon oxide film 21, the portion located in the trench 11 in the silicon nitride film 22, the portion located in the trench 11 in the silicon oxide film 23, and A structure including the gas portion 29 becomes the lower insulating portion 16. Further, the portion located on the floating gate electrode 14 in the silicon nitride film 22 and the portion located on the floating gate electrode 14 in the silicon oxide film 23 become the upper insulating portion 17. The upper insulating portion 17 is formed of silicon oxide and silicon nitride, and the lower insulating portion 16 includes a gas portion 29 in addition to silicon oxide and silicon nitride. The relative dielectric constant ε2 is higher than the relative dielectric constant ε3 of the entire lower insulating portion 16. Further, since the interelectrode insulating film 18 is made of lanthanum oxide, the relative dielectric constant ε1 of the interelectrode insulating film 18 is higher than the relative dielectric constant ε2 of the upper insulating portion 17. The effect in this embodiment is the same as that of the above-mentioned 4th Embodiment.
FIG. 9 is a cross-sectional view illustrating a semiconductor memory device according to this embodiment.
As shown in FIG. 9, in the present embodiment, in the step shown in FIG. 8C, the floating gate electrode 14, the interelectrode insulating film 18 and the control gate electrode 19 are selectively removed and extend in the CG direction. After dividing into stripe portions, wet etching is performed to remove the silicon nitride film 22 (see FIG. 8C). As a result, the portion where the silicon nitride film 22 is disposed becomes the gas portion 30. Thereafter, an interlayer insulating film (not shown), a source line (not shown), and a bit line (not shown) are formed. In this way, the semiconductor memory device 6 is manufactured.
In this embodiment, since the gas portion 30 is provided instead of the silicon nitride film 22 (see FIG. 8C), the semiconductor memory device 5 according to the fifth embodiment described above (FIG. 8C). The dielectric constant of the lower insulating part 16 and the upper insulating part 17 is lower than that of the reference). Thereby, interference between the floating gate electrodes 14 can be more effectively suppressed. The configuration, manufacturing method, and operational effects other than those described above in the present embodiment are the same as those in the fifth embodiment described above.
According to the embodiment described above, it is possible to realize a semiconductor memory device capable of suppressing interference between floating gate electrodes while ensuring coupling between the control gate electrode and the floating gate electrode.
1, 2, 3, 4, 5, 6: semiconductor memory device, 10: silicon substrate, 11: trench, 12: active area, 13: tunnel film, 14, 14a, 14b: floating gate electrode, 16: lower insulation 17: Upper insulating part, 17a: Overhanging part, 18: Interelectrode insulating film, 19: Control gate electrode, 20: Interface, 21: Silicon oxide film, 22: Silicon nitride film, 23, 24: Silicon oxide film 29, 30: Gas portion, 101, 102: Semiconductor memory device, 116: Lower insulating portion, A: Region
A semiconductor substrate having an upper portion divided into a plurality of active areas extending in the first direction;
A tunnel film provided on the active area;
A floating gate electrode provided on the tunnel film;
An inter-electrode insulating film provided on the floating gate electrode and extending in a second direction intersecting the first direction;
A control gate electrode provided on the interelectrode insulating film and extending in the second direction;
A lower insulating portion provided between the active areas adjacent in the second direction, between the tunnel films, and between the floating gate electrodes;
An upper insulating portion provided between the lower insulating portion and the inter-electrode insulating film and having an upper surface located above the upper surface of the floating gate electrode;
The lower insulating portion has a gas portion;
The relative dielectric constant of the upper insulating portion is higher than the relative dielectric constant of the lower insulating portion, and the relative dielectric constant of the interelectrode insulating film is higher than the relative dielectric constant of the upper insulating portion. apparatus.
2. The semiconductor memory device according to claim 1, wherein an interface between the lower insulating portion and the upper insulating portion is located above an upper surface of the floating gate electrode.
2. The semiconductor memory device according to claim 1, wherein an interface between the lower insulating portion and the upper insulating portion is located at the same height as an upper surface of the floating gate electrode.
2. The semiconductor memory device according to claim 1, wherein an interface between the lower insulating portion and the upper insulating portion is located below an upper surface of the floating gate electrode.
5. The semiconductor memory device according to claim 1, wherein a part of the upper insulating portion protrudes immediately above the floating gate electrode.
The upper insulating portion includes one or more materials selected from the group consisting of silicon oxide, silicon nitride, and silicate,
The interelectrode insulating film is made of lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium oxide, hafnium aluminum oxide, aluminum oxide, lanthanum silicate, lanthanum aluminum silicate, lanthanum hafnium silicate, hafnium silicate, hafnium aluminum The semiconductor memory device according to claim 1, comprising at least one oxide selected from the group consisting of silicate and aluminum silicate.
JP2011152672A 2011-07-11 2011-07-11 Semiconductor storage device Withdrawn JP2013021102A (en)
JP2011152672A JP2013021102A (en) 2011-07-11 2011-07-11 Semiconductor storage device
US13/353,818 US20130015518A1 (en) 2011-07-11 2012-01-19 Semiconductor memory device
JP2013021102A true JP2013021102A (en) 2013-01-31
ID=47518461
JP2011152672A Withdrawn JP2013021102A (en) 2011-07-11 2011-07-11 Semiconductor storage device
US (1) US20130015518A1 (en)
JP (1) JP2013021102A (en)
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