Source: http://www.google.com/patents/US7053485?dq=3657699
Timestamp: 2016-02-13 05:13:15
Document Index: 461800803

Matched Legal Cases: ['art 46', 'art 48', 'art 46', 'art 48', 'art 46', 'art 46', 'art 22', 'art 24', 'art 24', 'arts 22', 'art 24', 'art 22', 'arts 22', 'arts 22', 'art 24', 'art 22', 'art 122', 'art 124', 'art 122', 'art 124', 'arts 120']

Patent US7053485 - Microelectronic packages with self-aligning features - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA microelectronic package is made by a process which includes folding a substrate. Alignment elements on different parts of the substrate engage one another during the folding process to position the parts of the substrate precisely relative to one another. One or more of the alignment elements may be...http://www.google.com/patents/US7053485?utm_source=gb-gplus-sharePatent US7053485 - Microelectronic packages with self-aligning featuresAdvanced Patent SearchPublication numberUS7053485 B2Publication typeGrantApplication numberUS 10/640,177Publication dateMay 30, 2006Filing dateAug 13, 2003Priority dateAug 16, 2002Fee statusPaidAlso published asUS20040104470, WO2004017399A1Publication number10640177, 640177, US 7053485 B2, US 7053485B2, US-B2-7053485, US7053485 B2, US7053485B2InventorsKyong-Mo Bang, Teck-Gyu Kang, Jae M. ParkOriginal AssigneeTessera, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (8), Referenced by (6), Classifications (41), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMicroelectronic packages with self-aligning features
FIG. 2 is a diagrammatic sectional view taken along the line 2—2 in FIG. 1.
FIG. 3 is a diagrammatic sectional view taken along line 3—3 in FIG. 1.
FIG. 4 is a diagrammatic sectional view of a mold used in forming the article of FIGS. 1–3 during one stage in production of the article.
FIG. 5 is a diagrammatic perspective view of a package formed from the article of FIGS. 1–3.
FIG. 8 is a diagrammatic sectional view taken along line 8—8 in FIG. 7.
In a manufacturing process used to form the component of FIGS. 1–3, the substrate 20, with first microelectronic device or chip 40 thereon, is engaged in a mold 44 (FIG. 4). The mold may be a conventional transfer, injection, compression mold having a first part 46 and a second part 48. The first mold part 46 has a parting surface 49, which engages the interior surface 26 of the substrate. The second mold part 48 engages the exterior surface. A first element cavity 50 and a second element cavity 52 are provided in the first mold part 46. These cavities are open to the parting surface 49 of the first mold part. Cavity 50 is in the form of a generally rectangular block or mass 54 (FIG. 1) having a projecting ridge 56 at the top of the mass, remote from substrate 20. As best seen in FIG. 4, the chip or first microelectronic device 40 is disposed within the first element cavity 50 when the substrate is engaged with the mold. The portion 66 of cavity 50 (FIG. 4) which forms ridge 56 (FIG. 1) extends outwardly from the remainder of cavity 50 in a direction perpendicular to the direction of motion of the molded part during ejection from the mold and forms a “undercut” in the mold. To permit extraction of the molded article from the mold, mold part 46 may be provided with one or more elements 68 arranged to move in the directions parallel to the parting plane 49 of the mold (to the left or right in FIG. 4) when the mold opens. Such elements are commonly referred to in the mold making art as “side draws.” Numerous techniques for moving side draws in conjunction with the opening and closing motion of the mold are well known to those skilled in the mold making art.
With substrate 20 disposed in the mold, a moldable encapsulant such as a thermosetting or thermoplastic polymer composition is introduced into cavities 50 and 52 through channels 78 in the mold, until the encapsulant fills the cavities. The encapsulant is then brought to a solid condition by chemical reaction or by cooling. Preferably, the material in its solid condition is relatively rigid. Essentially any material commonly usable as a protective overmolding material in electronic packaging can be employed. Merely by way of example, thermal setting resins such as epoxies and phenolics may be employed. Some suitable resins include those sold under the designations EME-7730 and EME-7730L by the Sumitomo Bakelite Company Limited of Tokyo, Japan. These resins have a flexural modulus of about 2400 kg/mm2 at 25� C. and about 150–155 kg/mm2 at 240� C. Resins of this type adhere well to electronic components and to dielectric polymers such as polyimide. After the encapsulating material has been introduced into cavities 50 and 52 and brought to a solid condition, the part is ejected from the mold using conventional techniques. At this stage, the component has a first alignment element in the form of mass 54 (FIGS. 1 and 2) covering the first microelectronic device or chip 40, the first element 54 being disposed on the first part 22 of substrate 20. The component also has a U-shaped second alignment element 58 on the second part 24 of the substrate. Both of these alignment elements overlie the interior surface 26 of the substrate. A thin layer of an adhesive 80 is applied on the interior surface 26 of the second part 24 of the substrate, within the region encompassed by the U-shaped second alignment element 58. This layer of adhesive may be provided as a pre-formed film of the type commonly referred to as a “dry pad” adhesive.
Although the processing steps used to form the component of FIGS. 1–3 have been described with reference to a single component, it should be appreciated that these processing steps can be performed while substrate 20 is a part of a larger sheet or tape. For example, substrate 20 can be formed as part of a continuous or semi-continuous tape which is advanced through the mold in a step-wise fashion, so as to form one or more sets of alignment elements on individual portions of the tape, so as to produce a large number of components in sequence.
In the next stage of the process, substrate 20 is folded over upon itself by bending generally around an axis 82 (FIG. 1) between the first and second parts 22 and 24 of the substrate, so as to bring the substrate to the folded condition depicted in FIGS. 5 and 6. In this condition, the second part 24 of the substrate overlies the first part, with the interior surface 26 in the second part confronting the interior surface in the first part. The first alignment element or mass 54 enters into the opening defined by the second alignment element 58, so that mass 54 is disposed between the side walls 62 of the second element. The dimensions of the mass 54 and the dimensions of the second element 58 are arranged to provide a close fit between the first element or mass 54 and the second or U-shaped element 58. The first alignment element or mass 54 desirably also abuts the back wall 60 (FIGS. 1 and 5) of the second alignment element 58. The engaged first element 54 and second element 58 hold the second part of substrate 20 in precise position relative to the first part 22. Stated another way, the engaged elements limit relative movement of the two parts 22 and 24 in at least some directions parallel to the planes of these parts. These directions, to the left and right in FIG. 6 and into and out of the plane of the drawing in FIG. 6, are referred to herein as “horizontal directions.” As the parts are engaged with one another during the folding operation, the engagement of the first and second alignment elements 54 and 58 brings the two parts 22 and 24 of the substrate to the desired relative positions in the horizontal directions. This positioning action of the alignment elements assures that the connection terminals 34 on the second part 24, at the top of the assembly, will lie in the desired positions in the horizontal directions relative to the mounting terminals 30 on the first part 22 of the substrate. Consequently, if a further element is mounted on connecting terminals 34, that further element also can be precisely registered with the mounting terminals 30 in the horizontal directions.
A component according to a further embodiment of the invention (FIGS. 7 and 8) is similar to the component discussed above, in that it incorporates a substrate 120 having a first part 122 and a second part 124. Here again, a first microelectronic device or semiconductor element 140 (FIG. 8) is mounted to the first part 122 of the substrate and a first alignment element 154 is formed as a mass of an encapsulant covering the first microelectronic device. The component of FIGS. 7 and 8 also has a second microelectronic device 141 such as a second semiconductor chip (FIG. 8) mounted to the second part 124 of the substrate. The second alignment element 158 is in the form of a second mass of encapsulant covering the second microelectronic device 141. This second element or mass has an opening or recess 159 in its top surface sized to receive mass 154. In the folded condition (FIG. 9), the first element 154 is engaged in recess 159 of the second element 158. Here again, the engaged alignment elements constrain the first and second parts 120 and 124 of the substrate and guide these parts into the proper alignment during the folding operation. A component according to this embodiment of the invention may be formed by a process similar to that discussed above. A first chip or microelectronic device 140 is received in one cavity of the mold; whereas the second chip or microelectronic device 141 is received in another cavity in the same mold, so that once again the two alignment elements are formed in the same molding operation. The component and folded package of FIG. 9 may have the other features discussed above with reference to FIGS. 1–6, such as mounting terminals on one part of the substrate for mounting the folded package to a circuit panel and connecting terminals on the opposite part of the substrate for connecting additional elements or for testing the finished product. Here again, these two sets of terminals will be held in precise registration with one another. The mating alignment elements of FIGS. 7–9 do not include undercuts to hold the assembly in the folded condition. An adhesive (not shown) may be provided on one or both of the alignment elements for this purpose.
After the adhesive has set and formed a bond, the component may be severed, as by cutting along lines 202 so as to separate portions of the folded component from one another and form individual units, each including one or more of the microelectronic devices 240 and the associated portions of the folded substrate. At the same time, the substrate can be severed along further lines 204 so as to trim off portions of the substrate occupied by the second alignment element 258, which is no longer needed after the adhesive bond has been formed. Assemblies such as that discussed above with reference to FIGS. 7–9, where microelectronic devices are present on both parts of the substrate, may also include multiple devices. In such an arrangement, each of the masses or alignment elements 154 and 158 may be a relatively large mass including numerous microelectronic devices. These masses are severed along with the substrate when the individual units are separated from one another.
Numerous variations and combinations of the features discussed above can be utilized without departing from the present invention. In one such variant, the roles of the mounting terminals and connection terminals discussed above are reversed. For example, the package of FIGS. 5 and 6 can be mounted to the circuit board by connection terminals 34 and additional microelectronic devices or packages can be connected to mounting terminals 30. Similarly, the combined array of connection terminals 334 and 335 in the embodiment of FIGS. 13–16 can be used to mount the package to the circuit panel, so that the mounting terminals 330 face upwardly, away from the circuit panel. The mounting terminals can be used to connect an additional package or other device. Also, terminals other than the solder-bondable pads shown in the drawings, such as pins projecting from the substrate and adapted to be received in a socket, can be employed.
The inter-engagement of alignment elements can be used in more complex folded structures. For example, as disclosed in commonly-assigned, co-pending U.S. patent application Ser. No. 10/077,388, filed Feb. 15, 2002, a substrate in a generally cruciform shape having multiple arms extending from a central region can be folded so that the various arms all overlie the central region, and so that microelectronic devices positioned on all of the arms are stacked one above the other. Such a structure can be provided with alignment elements on two or more parts of the substrate as, for example, on one or more of the various arms, on the central portion, or both, so as to hold the parts of the substrate in a desired positional relationship when the substrate is in a folded condition. Also, the particular shapes of the alignment elements discussed above are illustrative only. Alignment elements having other shapes can be employed. For example, an alignment element on one part of a substrate may define a circular or cylindrical recess, or a plurality of such recesses, whereas an alignment element on the mating part of the substrate may define one or more pins adapted to fit within such recess or recesses. In a further variant, the alignment elements can be features of the substrate itself. Features of the substrate itself which constitute alignment elements should be considered as “attached” or “mounted” to the substrate. Also, the alignment elements can be formed from essentially any material. Merely by way of example, a pin-shaped metallic alignment element can be formed by processes similar to those used to form terminals and via liners, whereas a recess can be formed by processes used to form vias in the substrate. Here again, the alignment elements can be formed at essentially no additional cost. In yet another arrangement, the substrate may be formed with holes used for aligning and registering the substrate during processing operation, such as the sprocket holes commonly provided on tape-like substrates. An alignment element projecting from a part of the substrate remote from one set of socket holes may engage that set of socket holes when the substrate is folded.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3390308Mar 31, 1966Jun 25, 1968IttMultiple chip integrated circuit assemblyUS3923359Jul 10, 1972Dec 2, 1975Pressey Handel Und InvestmentsMulti-layer printed-circuit boardsUS4371912Oct 1, 1980Feb 1, 1983Motorola, Inc.Method of mounting interrelated componentsUS4489364Dec 31, 1981Dec 18, 1984International Business Machines CorporationChip carrier with embedded engineering change lines with severable periodically spaced bridging connectors on the chip supporting surfaceUS4540226Jan 3, 1983Sep 10, 1985Texas Instruments IncorporatedIntelligent electronic connection socketUS4638348Aug 8, 1983Jan 20, 1987Brown David FSemiconductor chip carrierUS4734825Sep 5, 1986Mar 29, 1988Motorola Inc.Integrated circuit stackable packageUS4754316Jun 3, 1982Jun 28, 1988Texas Instruments IncorporatedSolid state interconnection system for three dimensional integrated circuit structuresUS4841355Feb 10, 1988Jun 20, 1989Amdahl CorporationThree-dimensional microelectronic package for semiconductor chipsUS4868712Oct 27, 1987Sep 19, 1989Woodman John KThree dimensional integrated circuit packageUS4897918Mar 25, 1988Feb 6, 1990Nippon Telegraph And TelephoneMethod of manufacturing an interboard connection terminalUS4956694Nov 4, 1988Sep 11, 1990Dense-Pac Microsystems, Inc.Integrated circuit chip stackingUS4982265Jun 22, 1988Jan 1, 1991Hitachi, Ltd.Semiconductor integrated circuit device and method of manufacturing the sameUS4994902Nov 15, 1989Feb 19, 1991Hitachi, Ltd.Semiconductor devices and electronic system incorporating themUS4996583Feb 9, 1990Feb 26, 1991Matsushita Electric Industrial Co., Ltd.Stack type semiconductor packageUS4996587Mar 23, 1990Feb 26, 1991International Business Machines CorporationIntegrated semiconductor chip packageUS5028986Dec 23, 1988Jul 2, 1991Hitachi, Ltd.Semiconductor device and semiconductor module with a plurality of stacked semiconductor devicesUS5045921Dec 26, 1989Sep 3, 1991Motorola, Inc.Pad array carrier IC device using flexible tapeUS5117282Oct 29, 1990May 26, 1992Harris CorporationStacked configuration for integrated circuit devicesUS5128831Oct 31, 1991Jul 7, 1992Micron Technology, Inc.High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled viasUS5138438Nov 25, 1991Aug 11, 1992Akita Electronics Co. Ltd.Lead connections means for stacked tab packaged IC chipsUS5148265Mar 21, 1991Sep 15, 1992Ist Associates, Inc.Semiconductor chip assemblies with fan-in leadsUS5172303Nov 23, 1990Dec 15, 1992Motorola, Inc.Electronic component assemblyUS5198888Dec 20, 1990Mar 30, 1993Hitachi, Ltd.Semiconductor stacked deviceUS5222014Mar 2, 1992Jun 22, 1993Motorola, Inc.Three-dimensional multi-chip pad array carrierUS5247423May 26, 1992Sep 21, 1993Motorola, Inc.Stacking three dimensional leadless multi-chip module and method for making the sameUS5266912Aug 19, 1992Nov 30, 1993Micron Technology, Inc.Inherently impedance matched multiple integrated circuit moduleUS5281852Dec 10, 1991Jan 25, 1994Normington Peter J CSemiconductor device including stacked dieUS5311401Jul 9, 1991May 10, 1994Hughes Aircraft CompanyStacked chip assembly and manufacturing method thereforUS5313096Jul 29, 1992May 17, 1994Dense-Pac Microsystems, Inc.IC chip package having chip attached to and wire bonded within an overlying substrateUS5334875Mar 2, 1993Aug 2, 1994Hitachi, Ltd.Stacked semiconductor memory device and semiconductor memory module containing the sameUS5337077Mar 20, 1992Aug 9, 1994Mark Iv Industries LimitedElectromagnetic shutterUS5376825Nov 18, 1993Dec 27, 1994Seiko Epson CorporationIntegrated circuit package for flexible computer system alternative architecturesUS5384689Dec 20, 1993Jan 24, 1995Shen; Ming-TungIntegrated circuit chip including superimposed upper and lower printed circuit boardsUS5397916Jul 26, 1993Mar 14, 1995Normington; Peter J. C.Semiconductor device including stacked dieUS5412247Jan 25, 1991May 2, 1995The Charles Stark Draper Laboratory, Inc.Protection and packaging system for semiconductor devicesUS5455740Mar 7, 1994Oct 3, 1995Staktek CorporationBus communication system for stacked high density integrated circuit packagesUS5479318May 12, 1995Dec 26, 1995Staktek CorporationBus communication system for stacked high density integrated circuit packages with trifurcated distal lead endsUS5489749Jun 29, 1994Feb 6, 1996Tessera, Inc.Semiconductor connection components and method with releasable lead supportUS5543664Jan 20, 1995Aug 6, 1996Staktek CorporationUltra high density integrated circuit packageUS5548091Oct 26, 1993Aug 20, 1996Tessera, Inc.Semiconductor chip connection components with adhesives and methods for bonding to the chipUS5552631Dec 20, 1993Sep 3, 1996Lsi Logic CorporationSemiconductor device assembly including power or ground plane which is provided on opposite surface of insulating layer from signal traces, and is exposed to central opening in insulating layer for interconnection to semiconductor dieUS5552963Jul 24, 1995Sep 3, 1996Staktek CorporationBus communication system for stacked high density integrated circuit packagesUS5600541Aug 3, 1995Feb 4, 1997Hughes Aircraft CompanyVertical IC chip stack with discrete chip carriers formed from dielectric tapeUS5608265Mar 9, 1994Mar 4, 1997Hitachi, Ltd.Encapsulated semiconductor device package having holes for electrically conductive materialUS5616958Jan 25, 1995Apr 1, 1997International Business Machines CorporationElectronic packageUS5625221Jan 3, 1995Apr 29, 1997Samsung Electronics Co., Ltd.Semiconductor assembly for a three-dimensional integrated circuit packageUS5637536Aug 5, 1994Jun 10, 1997Thomson-CsfMethod for interconnecting semiconductor chips in three dimensions, and component resulting therefromUS5639695Nov 3, 1995Jun 17, 1997Motorola, Inc.Low-profile ball-grid array semiconductor package and methodUS5642261Jun 30, 1994Jun 24, 1997Sgs-Thomson Microelectronics, Inc.Ball-grid-array integrated circuit package with solder-connected thermal conductorUS5656856Jun 7, 1995Aug 12, 1997Samsung Electronics Co., Ltd.Reduced noise semiconductor package stackUS5659952Dec 29, 1994Aug 26, 1997Tessera, Inc.Method of fabricating compliant interface for semiconductor chipUS5668405Sep 14, 1995Sep 16, 1997Nec CorporationSemiconductor device with a film carrier tapeUS5677566May 8, 1995Oct 14, 1997Micron Technology, Inc.Semiconductor chip packageUS5681777Mar 29, 1996Oct 28, 1997Lsi Logic CorporationProcess for manufacturing a multi-layer tab tape semiconductor deviceUS5701031Jul 25, 1994Dec 23, 1997Hitachi, Ltd.Sealed stacked arrangement of semiconductor devicesUS5734555Mar 30, 1994Mar 31, 1998Intel CorporationShared socket multi-chip module and/or piggyback pin grid array packageUS5751063Sep 16, 1996May 12, 1998Nec CorporationMulti-chip moduleUS5783870Nov 14, 1995Jul 21, 1998National Semiconductor CorporationMethod for connecting packages of a stacked ball grid array structureUS5784264Nov 27, 1995Jul 21, 1998Nec CorporationMCM (Multi Chip Module) carrier with external connection teminals BGA (Ball Grid Array) type matrix array formUS5789815Apr 23, 1996Aug 4, 1998Motorola, Inc.Three dimensional semiconductor package having flexible appendagesUS5801439Feb 21, 1997Sep 1, 1998Fujitsu LimitedSemiconductor device and semiconductor device unit for a stack arrangementUS5804874Mar 4, 1997Sep 8, 1998Samsung Electronics Co., Ltd.Stacked chip package device employing a plurality of lead on chip type semiconductor chipsUS5805422 *Aug 15, 1997Sep 8, 1998Nec CorporationSemiconductor package with flexible board and method of fabricating the sameUS5834339Mar 7, 1996Nov 10, 1998Tessera, Inc.Methods for providing void-free layers for semiconductor assembliesUS5835988Oct 24, 1996Nov 10, 1998Mitsubishi Denki Kabushiki KaishaPacked semiconductor device with wrap around external leadsUS5844315Mar 26, 1996Dec 1, 1998Motorola CorporationLow-profile microelectronic packageUS5861666Aug 29, 1996Jan 19, 1999Tessera, Inc.Stacked chip assemblyUS5883426Apr 18, 1997Mar 16, 1999Nec CorporationStack moduleUS5956234Jan 20, 1998Sep 21, 1999Integrated Device Technology, Inc.Method and structure for a surface mountable rigid-flex printed circuit boardUS6030856Jun 10, 1997Feb 29, 2000Tessera, Inc.Bondable compliant pads for packaging of a semiconductor chip and method thereforUS6072233May 4, 1998Jun 6, 2000Micron Technology, Inc.Stackable ball grid array packageUS6093029Sep 8, 1998Jul 25, 2000S3 IncorporatedVertically stackable integrated circuitUS6121676Dec 11, 1997Sep 19, 2000Tessera, Inc.Stacked microelectronic assembly and method thereforUS6180881May 5, 1998Jan 30, 2001Harlan Ruben IsaakChip stack and method of making sameUS6195268Feb 26, 1998Feb 27, 2001Floyd K. EideStacking layers containing enclosed IC chipsUS6218848Oct 14, 1999Apr 17, 2001Micron Technology, Inc.Semiconductor probe card having resistance measuring circuitry and method of fabricationUS6225688Feb 4, 1999May 1, 2001Tessera, Inc.Stacked microelectronic assembly and method thereforUS6232152Apr 28, 1998May 15, 2001Tessera, Inc.Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structuresUS6268649Mar 29, 2000Jul 31, 2001Micron Technology, Inc.Stackable ball grid array packageUS6291259Jan 28, 1999Sep 18, 2001Hyundai Electronics Industries Co., Ltd.Stackable ball grid array semiconductor package and fabrication method thereofUS6303997Apr 7, 1999Oct 16, 2001Anam Semiconductor, Inc.Thin, stackable semiconductor packagesUS6313522Aug 28, 1998Nov 6, 2001Micron Technology, Inc.Semiconductor structure having stacked semiconductor devicesUS6335565Dec 4, 1996Jan 1, 2002Hitachi, Ltd.Semiconductor deviceUS6342728Jan 17, 2001Jan 29, 2002Hitachi, Ltd.Semiconductor device and manufacturing method thereofUS6369445Sep 26, 2000Apr 9, 2002Advantest CorporationMethod and apparatus for edge connection between elements of an integrated circuitUS6388264Aug 7, 2000May 14, 2002Benedict G PaceOptocoupler package being hermetically sealedUS6462421Apr 10, 2000Oct 8, 2002Advanced Semicondcutor Engineering, Inc.Multichip moduleUS6496026Feb 25, 2000Dec 17, 2002Microconnect, Inc.Method of manufacturing and testing an electronic device using a contact device having fingers and a mechanical groundUS6515870Nov 27, 2000Feb 4, 2003Intel CorporationPackage integrated faraday cage to reduce electromagnetic emissions from an integrated circuitUS20010006252Feb 2, 2001Jul 5, 2001Young KimStacked microelectronic assembly and method thereforJPS5275981A Title not availableJPS5661151A Title not availableJPS5731166A Title not availableJPS6129140A Title not availableJPS58178529A Title not availableJPS60194548A Title not availableJPS61101067A Title not availableJPS61120454A Title not availableJPS61137335A Title not available* Cited by examinerNon-Patent CitationsReference1"Megabyte Per Cubic Inch," Defense Science, May 1988, p. 56.2"Three-Dimensional Packaging," Defense Science, May 1988, p. 65.3Bang, U.S. Appl. No. 10/656,534, filed Sep. 5, 2003.4Fjelstad, U.S. Appl. No. 10/077,388, filed Feb. 15, 2002.5Forthun, U.S. Appl. No. 07/552,578, filed Jul. 13, 1990.6Mohammed, Serial No. PCT/US02/26805, filed Aug. 22, 2002.7Newsam, U.S. Appl. No. 60/314,042, filed Aug. 22, 2001.8U.S. Appl. No. 07/552,578, filed Jul. 13, 1990, Forthun.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7656678Oct 31, 2005Feb 2, 2010Entorian Technologies, LpStacked module systemsUS7719098Oct 16, 2007May 18, 2010Entorian Technologies LpStacked modules and methodUS7804985Aug 25, 2008Sep 28, 2010Entorian Technologies LpCircuit module having force resistant constructionUS7863737 *Apr 1, 2006Jan 4, 2011Stats Chippac Ltd.Integrated circuit package system with wire bond patternUS20070235869 *Apr 1, 2006Oct 11, 2007Stats Chippac Ltd.Integrated circuit package system with wire bond patternUS20080036068 *Oct 4, 2007Feb 14, 2008Staktek Group L.P.Stacked Module Systems and Methods* Cited by examinerClassifications U.S. Classification257/730, 257/727, 257/E23.065, 257/E23.125, 361/749, 257/E23.179, 257/797, 257/E25.023International ClassificationH01L23/544, H01L23/31, H01L23/34, H01L23/04, H01L23/498, H01L25/10, H05K1/00Cooperative ClassificationH01L2924/00014, H01L2924/181, H01L2224/45099, H01L24/45, H01L2224/85399, H01L2224/05599, H01L24/48, H01L2924/15311, H01L23/3121, H01L2924/3011, H01L23/4985, H01L2924/01079, H01L25/105, H01L23/544, H01L2224/4824, H01L2223/54473, H01L2924/01078, H01L2924/1815, H01L2224/48472, H01L2225/1023, H01L2225/1058, H01L2225/1041European ClassificationH01L25/10J, H01L23/544, H01L23/31H2, H01L23/498JLegal EventsDateCodeEventDescriptionJan 26, 2004ASAssignmentOwner name: TESSERA, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BANG, KYONG-MO;KANG, TECK-GYU;PARK, JAE M.;REEL/FRAME:014924/0954;SIGNING DATES FROM 20040114 TO 20040115Nov 5, 2009FPAYFee paymentYear of fee payment: 4Oct 30, 2013FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services