Source: https://patents.google.com/patent/US7390709B2/en
Timestamp: 2018-12-18 20:06:13
Document Index: 592574011

Matched Legal Cases: ['art 131', 'art 133', 'art 130', 'art 134', 'art 131', 'art 133', 'art 134', 'art 133', 'art 134', 'art 133', 'art 133', 'art 130']

US7390709B2 - Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode - Google Patents
Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode Download PDF
US7390709B2
US7390709B2 US10937195 US93719504A US7390709B2 US 7390709 B2 US7390709 B2 US 7390709B2 US 10937195 US10937195 US 10937195 US 93719504 A US93719504 A US 93719504A US 7390709 B2 US7390709 B2 US 7390709B2
US10937195
US20060051924A1 (en )
FIGS. 1 d-1 i illustrate an embodiment of the present invention in which part of first metal layer 116 is masked after first metal layer 116 is formed on high-k gate dielectric layer 115, and the exposed part of first metal layer 116 is then converted into a second metal layer with a second workfunction. To mask first metal layer 116, e.g., where formed on second part 131 of high-k gate dielectric layer 115, initially masking layer 132 may be formed on first metal layer 116, as shown in FIG. 1 d.
In a preferred embodiment, masking layer 132 comprises sacrificial light absorbing material (“SLAM”) 132, which may be spun onto first metal layer 116. First part 133 of SLAM 132 covers first part 130 of high-k gate dielectric layer 115, and second part 134 of SLAM 132 covers second part 131 of high-k gate dielectric layer 115. After depositing SLAM 132 on first metal layer 116, first part 133 of SLAM 132 is removed while second part 134 of SLAM 132 is retained. First part 133 of SLAM 132 may be removed in the following way. First, a layer of photoresist (not shown) is deposited on SLAM 132, then patterned such that it covers only second part 134 of SLAM 132. Exposed part 133 may then be removed, e.g., by applying an appropriate wet etch process. After removing part 133 of SLAM 132, the patterned photoresist layer may be removed. As a result, first metal layer 116 is exposed where formed on first part 130 of high-k gate dielectric layer 115, as FIG. 1 e illustrates.
In this embodiment, after converting part of first metal layer 116 into second metal layer 135 (and removing SLAM 132), the remainder of trenches 113 and 114 may be filled with a material that may be easily polished, e.g., tungsten, aluminum, titanium, or titanium nitride. Such a trench fill metal, e.g., metal 121, may be deposited over the entire device using a conventional metal deposition process, generating the FIG. 1 h structure. Fill metal 121, second metal layer 135, first metal layer 116, and high-k gate dielectric layer 115 may then be removed from the surface of first dielectric layer 112, e.g., via an appropriate CMP process, as shown in 1 i.
In the embodiment represented by FIGS. 3 a-3 e, if first metal layer 116 is n-type, then second metal layer 135 is p-type. If first metal layer 116 is p-type, then second metal layer 135 is n-type. In the resulting device, P/N junction 124 resides where first metal layer 116 meets second metal layer 135. In devices with the FIG. 3 e structure, an adjacent trench (e.g., trench 114 of FIGS. 1 a-1 i—not shown in FIG. 3 e) may have a P/N junction with the reverse orientation. Within such an adjacent trench, second metal layer 135 may contact high-k gate dielectric layer 115 where first metal layer 116 contacts that dielectric layer in FIG. 3 e, while first metal layer 116 may contact high-k gate dielectric layer 115 where second metal layer 135 contacts that dielectric layer in FIG. 3 e.
Although the embodiment of FIGS. 3 a-3 e illustrates a method for forming a structure with a P/N junction, other embodiments may form devices that do not include a P/N junction. For example, in other devices, first metal layer 116, shown in FIG. 1 i, may coat trench 114 along its entire width, while second metal layer 135, shown in FIG. 1 i, coats trench 113 along its entire width. The method of the present invention is thus not limited to forming devices with P/N junctions.
After converting part of first metal layer 416 into second metal layer 435, fill metal 421 may be deposited onto first metal layer 416 and second metal layer 435. Portions of fill metal 421, second metal layer 435, first metal layer 416, and high-k gate dielectric layer 415 are then removed, except where they fill the trench, generating the FIG. 4 e structure. Process steps for completing the device are omitted, as they are well known to those skilled in the art. Like the embodiment of FIGS. 1 a-1 i, first metal layer 416 of FIG. 4 e may coat trench 413 along its entire width, while second metal layer 435 of FIG. 4 e coats trench 414 along its entire width. Alternatively, the embodiment of FIGS. 4 a-4 e may be used to form a structure with a P/N junction, like the structure of FIG. 3 e.
As illustrated above, the method of the present invention enables production of CMOS devices that include a high-k gate dielectric layer and metal gate electrodes with appropriate workfunctions for both NMOS and PMOS transistors. This method may enable a replacement gate process to generate such a CMOS device without requiring removal of part of a metal gate layer from an underlying high-k gate dielectric layer. As a result, the process of the present invention may prevent such a removal step from damaging the high-k gate dielectric layer. Although the embodiments described above provide examples of processes for forming CMOS devices that may benefit from application of the present invention, the present invention is not limited to these particular embodiments.
15. The method of claim 14 wherein the first metal layer is between about 25 and about 300 angstroms thick, has a workfunction that is between about 3.9 eV and about 4.2 eV, and comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, and an aluminide, and the second metal layer has a workfunction that is between about 4.9 eV and about 5.2 eV.
US10937195 2004-09-08 2004-09-08 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode Active 2025-10-01 US7390709B2 (en)
US10937195 US7390709B2 (en) 2004-09-08 2004-09-08 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
CN 200580030142 CN101095223B (en) 2004-09-08 2005-08-22 A method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
DE200511002158 DE112005002158B4 (en) 2004-09-08 2005-08-22 A method for manufacturing a semiconductor device having a gate dielectric layer having a high K and a gate electrode made of metal
TW94128627A TWI282593B (en) 2004-09-08 2005-08-22 A method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
PCT/US2005/029813 WO2006028690A1 (en) 2004-09-08 2005-08-22 A method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US12157796 US7785958B2 (en) 2004-09-08 2008-06-12 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US12157796 Division US7785958B2 (en) 2004-09-08 2008-06-12 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US20060051924A1 true US20060051924A1 (en) 2006-03-09
US7390709B2 true US7390709B2 (en) 2008-06-24
ID=35448053
US10937195 Active 2025-10-01 US7390709B2 (en) 2004-09-08 2004-09-08 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US12157796 Active US7785958B2 (en) 2004-09-08 2008-06-12 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US (2) US7390709B2 (en)
CN (1) CN101095223B (en)
DE (1) DE112005002158B4 (en)
WO (1) WO2006028690A1 (en)
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US20060051924A1 (en) 2006-03-09 application
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US7785958B2 (en) 2010-08-31 grant
DE112005002158B4 (en) 2010-06-10 grant
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