Source: http://www.google.com/patents/US6835651?dq=5,266,072
Timestamp: 2014-03-09 20:13:18
Document Index: 450619560

Matched Legal Cases: ['arts 18', 'art 14', 'art 16', 'art 14', 'art 16', 'art 14', 'art 16', 'arts 16', 'arts 18', 'arts 14']

Patent US6835651 - Wiring forming method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAfter a wiring material layer (14) which is made of WSi2 or the like is formed on an insulation film covering a semiconductor substrate (10), a first antireflection coating film (16) which is made of TiON or TiN and a second antireflection coating film (18) which is made of an organic material are sequentially...http://www.google.com/patents/US6835651?utm_source=gb-gplus-sharePatent US6835651 - Wiring forming methodAdvanced Patent SearchPublication numberUS6835651 B2Publication typeGrantApplication numberUS 10/246,723Publication dateDec 28, 2004Filing dateSep 19, 2002Priority dateJul 2, 1997Fee statusPaidAlso published asUS6348404, US6509261, US20020052107, US20030029035Publication number10246723, 246723, US 6835651 B2, US 6835651B2, US-B2-6835651, US6835651 B2, US6835651B2InventorsSuguru Tabara, Hiroshi NakayaOriginal AssigneeYamaha CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (10), Non-Patent Citations (4), Classifications (23), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetWiring forming methodUS 6835651 B2Abstract After a wiring material layer (14) which is made of WSi2 or the like is formed on an insulation film covering a semiconductor substrate (10), a first antireflection coating film (16) which is made of TiON or TiN and a second antireflection coating film (18) which is made of an organic material are sequentially formed on the wiring material layer (14). Resist patterns (20 a to 20 c) are formed on the second antireflection coating film (18) by photolithography. The dry etching of the second antireflection coating film (18) is performed using the resist patterns (20 a to 20 c) as masks, after which the dry etching of the first antireflection coating film (16) is conducted using the resist patterns (20 a to 20 c) and patterns (18 a to 18 c) of the second antireflection coating film (18) as masks. The dry etching of the wiring material layer (14) is effected using the resist patterns (20 a to 20 c), the patterns (18 a to 18 c) of the second antireflection coating film (18) and patterns (16 a to 16 c) of the first antireflection coating film (16) as masks. The resist patterns (20 a to 20 c) and the patterns (18 a to 18 c) of the second antireflection coating film (18) are removed. Lamination layers, each including one of patterns of the wiring material layer (14) and one of the patterns of the first antireflection coating film (16), form wiring layers. The resist patterns (20 a to 20 c) and the patterns of the second antireflection coating film (18) may be removed after the etching of the first antireflection coating film (16), and the wring material layer (14) may be etched using the patterns of the first antireflection coating film (16) as masks.
What is claimed is: 1. A wiring forming method comprising:
forming a wiring material layer on an insulation film covering one of major surfaces of a substrate; forming a first antireflection coating film made of TiON on said wiring material layer; forming a second antireflection coating film made of an organic material directly on said first antireflection coating film; forming a resist layer on a lamination film which includes said first and second antireflection coating films, exposing said resist layer to light in accordance with predetermined wiring patterns and developing said exposed resist layer to from a resist pattern, wherein reflectance at said first and second antireflection coating films exhibits oscillating characteristics as a function of a thickness of said films, and wherein said first and second antireflection coating films have a thickness around one of a minimum of the oscillation characteristics of said reflectance. 2. A wiring forming method according to claim 1 wherein said wiring material layer is a polycide.
3. A wiring forming method according to claim 1, further comprising the steps of:
patterning the first and second antireflection coating films using the first and second antireflection coating films as a mask; and removing the resist pattern and the second antireflection coating film. 4. A wiring forming method according to claim 3, wherein said step of patterning the wiring material layer is done with an etching gas containing oxygen gas.
5. A wiring forming method comprising the steps of:
forming a wiring material layer made of polycide or polysilicon on an insulating film covering one of major surfaces of a substrate; forming a first antireflection coating film made of TiON on said wiring material layer; forming a second antireflection coating film made of an organic material directly on said first antireflection coating film; forming a resist layer on a lamination which includes said first and second antireflection coating films, and exposing and developing said resist layer to form resist pattern of wiring patterns; patterning the first and second antireflection coating films using the resist pattern as a mask; removing the resist pattern and the second antireflection coating film; and patterning the wiring material layer using the first antireflection coating film as a mask. 6. A wiring forming method according to claim 5, wherein said step of patterning the wiring material layer is done with an etching gas containing oxygen gas.
7. A wiring forming method comprising the steps of:
forming a wiring material layer made of polycide or polysilicon on an insulating film covering one of major surfaces of a substrate; forming a first antireflection coating film made of TiON or TiN on said wiring material layer; forming a second antireflection coating film made of an organic material directly on said first antireflection coating film; forming a resist layer on a lamination which includes said first and second antireflection coating films, and exposing and developing said resist layer to form resist pattern of wiring patterns; and patterning the wiring material layer using the resist pattern as a mask, wherein reflectance at said first and second antireflection coating films exhibits oscillating characteristics as a function of a thickness of said films, and wherein said first and second antireflection coating films have a thickness around one of a minimum of the oscillation characteristics of said reflectance. 8. A wiring forming method according to claim 7, wherein said step of patterning the wiring material layer is done with an etching gas containing oxygen gas.
9. A semiconductor device forming method comprising the steps of:
forming a gate oxide film on a substrate; forming a gate electrode layer over the gate oxide film; forming a first antireflection coating film made of TiON or TiN on said gate electrode layer; forming a second antireflection coating film made of an organic material on said first antireflection coating film; forming a resist layer on a lamination which includes said first and second antireflection coating films, exposing said resist layer to light in accordance with a predetermined pattern, and developing the resist layer to form an etching mask pattern consisting of said resist layer; and etching said gate electrode layer using said etching mask pattern to form a gate electrode, wherein reflectance at said first and second antireflection coating films exhibits oscillating characteristics as a function of a thickness of said films, and wherein said first and second antireflection coating films have a thickness around one of a minimum of the oscillation characteristics of said reflectance. 10. A wiring forming method according to claim 9, wherein said step of etching the gate electrode layer is done with an etching gas containing oxygen gas.
11. A wiring forming method according to claim 1, wherein said one of the major surfaces of the substrate has a silicon oxide insulating film formed by LOCOS (local oxidation of silicon).
12. A wiring forming method according to claim 1, wherein said light is a KrF excimer laser beam.
13. A wiring forming method according to claim 3, wherein said removing step is done by a chemical treatment using an amine-containing liquid or a mixture of H2SO4 and H2O2.
14. A wiring forming method according to claim 5, wherein said one of major surfaces of the substrate has a silicon oxide insulating film formed by LOCOS.
15. A wiring forming method according to claim 5, wherein said step of exposing uses a KrF excimer laser beam.
16. A wiring forming method according to claim 5, wherein said removing step is done by a chemical treatment using an amine-containing liquid or a mixture of H2SO4 and H2O2.
17. A wiring forming method according to claim 7, wherein said one of major surfaces of the substrate has a silicon oxide insulating film formed by LOCOS.
18. A wiring forming method according to claim 7, wherein said step of exposing uses a KrF excimer laser beam.
19. A wiring forming method according to claim 7, further comprising the step of removing the resist pattern by a chemical treatment using an amine-containing liquid or mixture of H2SO4 and H2O2.
20. A wiring forming method according to claim 9, wherein said substrate has a silicon oxide insulating film formed by LOCOS.
21. A wiring forming method according to claim 9, wherein said light is KrF excimer laser beam.
22. A wiring forming method according to claim 9, further comprising the step of removing said etching mask pattern by a chemical treatment using an amine-containing liquid or a mixture of H2SO4 and H2O2.
RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 09/969,270, filed Oct. 1, 2001 now U.S. Pat. No. 6,509,261, which is a division of application Ser. No. 09/109,443, filed Jul. 2, 1998 now U.S. Pat. No. 6,348,404, the disclosures of which are incorporated herein by reference.
A concave part of the surface of the wiring layer may form a concave mirror and the light reflected from the concave mirror may be converged at a region which is not to be exposed to light (this is known as �halation�). The halation causes the thinning and thickening of the wiring patterns, the breaking of the wiring and the formation of isolated spots.
On a substrate, m layers are stacked. The uppermost layer exposed to air (n0=1, k0=0) is called the first layer. The underlying layers are called the second, third, . . . , and m-th layers. The substrate is called the (m+1)-th layer. The real part and the imaginary part of the complex refractive index �j of the i-th layer are denoted nj and kj. Therefore, �j=nj−ikj. The complex reflectivity is denoted by r, and the complex transmissivity is denoted by t. Complex reflectivities at the uppermost surface, the first, second, third, . . . , interfaces are denoted by r0, r1, r2, r3, . . . . The complex reflectivity on the substrate surface is rm. Complex transmissivity at the first, second, third, . . . interfaces are denoted by t1, t2, t3, . . . . The complex transmissivity at the substrate surfaces is tm. These notations are shown in FIG. 14.
The intensity reflection on the substrate surface Rm is
R m =|r m|2=|(1−�m+1)/(1+�m+1)|2 The complex reflectivity of the j-th layer rj−1 is
r j−1=[{exp(−2i� j)}(F j −r j)−F j(1−F j r j)] /[F j{exp(−2i� j)}(F j −r j)−(1−F j r j)], where Fj=(n0−�j)/(n0+�j),
�j=2π�jd/γ,
γ: wavelength, and
d: thickness of the layer.
The simulation adopted obtains rm−1 by substituting rm, then rm−2 by substituting rm−1, . . . and r0 by substituting rj.
Ri=|ri|2. The simulation conditions in that case were as follows:
Refractive index �n� and
extinction coefficient �k� of TiON film:
extinction coefficient �k� of WSi2 layer:
extinction coefficient �k� of film Q:
SUMMARY OF THE INVENTION It is accordingly an object of the present invention to provide a wiring forming method which can improve the precision of the size of the wiring patterns.
According to one aspect of the present invention, there is provided a wiring forming method comprising the steps of: forming a wiring material layer on an insulation film covering one of major surfaces of a substrate; forming a first antireflection coating film made of one of TiON and TiN on the wiring material layer; stacking a second antireflection coating film made of an organic material directly on the first antireflection coating film; coating a resist layer on a lamination film which includes the first and second antireflection coating films, and exposing the resist layer to light in accordance with predetermined wiring patterns; forming resist patterns by developing the resist layer which has been exposed to light; and selectively removing the second antireflection coating film by anisotropic dry etching process which uses the resist patterns as masks, in order to leave patterns of the second antireflection coating film which correspond to the resist patterns.
Since the first antireflection coating film which is made of TiON or TiN is provided under the second antireflection coating film which is made of an organic material, the thickness of the second antireflection film can be reduced. A reduction in the thickness of the second antireflection film results in a reduction in the time required for performing the dry etching of the second antireflection coating films through utilization of the resist patterns as masks. Accordingly, the amount of shift in the size of the resist patterns is reduced such that the precision of the size of the wiring patterns is improved.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a substrate which shows the step of forming the wiring material layer according to the wiring forming method of the first embodiment of the present invention;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 8 illustrate the wiring forming method according to the first embodiment of the present invention. The steps (1) to (8), illustrated in FIGS. 1 to 8, respectively, will now be explained in sequence.
FIG. 12 shows the dependence R of the reflectance on the film thickness. This dependence was obtained by performing a computer simulation as regards a lamination film R provided on a WSi2 layer. The lamination film R in this case includes the TiON film corresponding to the antireflection coating film 16 and the organic antireflection coating film corresponding to the antireflection coating film 18 and stacked on the TiON film. Computer simulation was done under the conditions as described above. Since the TiON film has the same effect when it has a thickness of 40 nm or more, the thickness of the TiON film was fixed at 40 nm. The thickness of the organic film was varied in the range of 0-150 nm. The abscissa of FIG. 12 represents the thickness of the organic film 18. The computer simulation was conducted under the following conditions:
Refractive index �n� and extinction coefficient �k�
of TiON film corresponding to the film 16:
of the organic film corresponding to the film 18:
of the WSi2 layer 14 b: n−2.5
In the above-described embodiment, since the lamination film including the films 16 and 18 is formed within a film thickness range such as the range B, the reflectance variations are small and the accuracy of the pattern transfer is high even if the thickness of the lamination film varies due to the unevenness of the surface of the wiring material layer 14. In the case where a thinner lamination film is desired, the lamination film including the films 16 and 18 may be formed within a film thickness range such as the range A.
(5) By the anisotropic dry etching process which uses the resist patterns 20 a to 20 c as masks, the antireflection coating film 18 is selectively removed so that parts 18 a to 18 c of the antireflection coating film 18 are left in correspondence with the resist patterns 20 a to 20 c. The dry etching of the antireflection coating film 18 can be conducted using an oxygen and/or nitrogen plasma or using a chlorine plasma.
High frequency power: 60W
Coolant temperature at wafer stage: −20 to +20� C.
Coolant temperature at wafer stage: +5 to +20� C.
substrate stage temperature: 200-240� C., and
and rinses the substrate for ten minutes in the mixed liquid heated to 85-90� C. As a result, the lamination layer including the residual part 14 a of the wiring material layer 14 and the residual part 16 a of the antireflection coating film 16, the lamination layer including the residual part 14 b of the wiring material layer 14 and the residual part 16 b of the antireflection coating film 16, and the lamination layer including the residual part 14 c of the wiring material layer 14 and the residual part 16 c of the antireflection coating film 16 are left as wiring patterns 22 a to 22 c, respectively.
A chemical treatment using H2SO2/H2O2 may be employed as another removing method. With this chemical treatment, the residual parts 16 a to 16 c of the antireflection coating film 16 can also be removed in addition to the resist patterns 20 a to 20 c and the residual parts 18 a to 18 c of the antireflection coating film 18. In this case, the residual parts 14 a to 14 c of the wiring material layer 14 are left as the wiring patterns.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5980768 *Mar 7, 1997Nov 9, 1999Lam Research Corp.Methods and apparatus for removing photoresist mask defects in a plasma reactorUS6348404 *Jul 2, 1998Feb 19, 2002Yamaha CorporationWiring forming methodUS6509261 *Oct 1, 2001Jan 21, 2003Yamaha CorporationWiring forming methodJPH0653331A Title not availableJPH1092740A Title not availableJPH07201704A Title not availableJPH07201825A Title not availableJPH07211616A Title not availableJPH10125680A Title not availableJPS63233531A Title not available* Cited by examinerNon-Patent CitationsReference1 *Wolf et al., Silicon Processing for the VLSI Era-vol. 1:Process Technology, 1986, Lattice Press, pp. 384-386.2Wolf et al., Silicon Processing for the VLSI Era�vol. 1:Process Technology, 1986, Lattice Press, pp. 384-386.3 *Wolf et al., Silicon Processing for the VLSI Era-vol. I:Process Technology, 1986, Lattice Press, pp. 384-386.*4Wolf et al., Silicon Processing for the VLSI Era�vol. I:Process Technology, 1986, Lattice Press, pp. 384-386.** Cited by examinerClassifications U.S. Classification438/636International ClassificationH01L21/311, H01L21/31, H01L21/027, H01L21/3213, H01L21/469, G03F7/09, H01L21/4763, H05K3/02, H05K3/10Cooperative ClassificationY10S438/952, H01L21/32137, G03F7/091, H01L21/32139, H01L21/31133, H01L21/32136, H01L21/31138European ClassificationH01L21/3213C4B, H01L21/3213C4B2, G03F7/09A, H01L21/311C2B, H01L21/311C2, H01L21/3213DLegal EventsDateCodeEventDescriptionMay 30, 2012FPAYFee paymentYear of fee payment: 8Jun 13, 2008FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google