Source: http://www.google.com/patents/US7971130?dq=3798360
Timestamp: 2014-03-17 19:26:06
Document Index: 626769348

Matched Legal Cases: ['Application No. 60', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11']

Patent US7971130 - Multi-level signal memory with LDPC and interleaving - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsEmbodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals....http://www.google.com/patents/US7971130?utm_source=gb-gplus-sharePatent US7971130 - Multi-level signal memory with LDPC and interleavingAdvanced Patent SearchPublication numberUS7971130 B2Publication typeGrantApplication numberUS 11/627,250Publication dateJun 28, 2011Filing dateJan 25, 2007Priority dateMar 31, 2006Also published asEP2008363A1, US20070245214, US20110258509, WO2007116275A1Publication number11627250, 627250, US 7971130 B2, US 7971130B2, US-B2-7971130, US7971130 B2, US7971130B2InventorsAditya RamamoorthyOriginal AssigneeMarvell International Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (4), Non-Patent Citations (29), Referenced by (5), Classifications (11), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMulti-level signal memory with LDPC and interleavingUS 7971130 B2Abstract Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed.
a memory block comprising a plurality of memory cells, each memory cell configured to operate with multi-level signals;
a low density parity check (LDPC) coder configured to LDPC encode data values to provide LDPC encoded data values to be written into the memory cells;
an interleaver configured to interleave the LDPC encoded data values with bit interleaved code modulation to generate interleaved LDPC encoded data values; and
a mapper configured to map the interleaved LDPC encoded data values to modulation codes in accordance with a constellation map,
wherein a set of least significant bits is mapped to a modulation code corresponding to a lowest transmission voltage level, and a set of most significant bits is mapped to a modulation code corresponding to a highest transmission voltage level.
2. The memory apparatus of claim 1, further comprising a controller configured to control (i) encoding by the LDPC coder, (ii) interleaving by the interleaver, and (iii) receiving of the multi-level signals by the memory block.
3. The memory apparatus of claim 1, wherein the constellation map is based upon Gray code.
4. The memory apparatus of claim 3, wherein the constellation map comprises 8 modulation codes.
5. The memory apparatus of claim 1, further comprising a pulse amplitude modulator (PAM) operatively coupled to the interleaver and the memory block, the PAM configured to modulate the interleaved LDPC encoded data values for the memory block.
6. The memory apparatus of claim 5, further comprising a channel block that comprises (i) the interleaver and (ii) the PAM.
7. The memory apparatus of claim 1, further comprising a channel block that comprises (i) the interleaver and (ii) at least one of the LDPC coder or the mapper.
8. The memory apparatus of claim 1, wherein at least the memory block is configured as a flash memory device.
9. The memory apparatus of claim 1, wherein the memory block comprises one of a floating gate device, oxide-nitride-oxide (ONO) charge trapping device or a phase change memory device.
10. The memory apparatus of claim 1, further comprising a pulse amplitude modulator (PAM) and a digital bus interface operatively coupled to the PAM and the memory block, wherein the PAM is configured to output multi-level signals to the memory block serially.
11. The memory apparatus of claim 1, further comprising a de-interleaver operatively coupled to the memory block, the de-interleaver configured to deinterleave interleaved LDPC encoded data values from multi-level signals received from the memory block to provide de-interleaved LDPC encoded data values.
12. The memory apparatus of claim 11, further comprising a LDPC decoder operatively coupled to the de-interleaver, the LDPC decoder configured to decode data values from the de-interleaved LDPC encoded data values.
13. The memory apparatus of claim 12, further comprising a channel block that comprises (i) the de-interleaver and (ii) the LDPC decoder.
encoding a plurality of multi-level signal data values with corresponding low density parity (LDPC) codes to provide LDPC encoded multi-level signal data values;
interleaving the LDPC encoded multi-level signal data values with bit interleaved code modulation to provide interleaved LDPC encoded multi-level signal data values;
outputting, using multi-level signals, the interleaved LDPC encoded multi-level signal data values for storage in a memory block, wherein the memory block comprises a plurality of memory cells; and
mapping the interleaved LDPC encoded multi-level signal data values to modulation codes in accordance with a constellation map,
wherein mapping the interleaved LDPC encoded multi-level signal data values to a constellation map further comprises (i) mapping a set of least significant bits to a modulation code corresponding to a lowest transmission voltage level and (ii) mapping a set of most significant bits to a modulation code corresponding to a highest transmission voltage level.
15. The method of claim 14, wherein the constellation map is based upon Gray code.
16. The method of claim 14, wherein the constellation map comprising 8 constellation points.
17. The method of claim 14, further comprising modulating the interleaved LDPC encoded multi-level signal data values for storage.
18. The method of claim 17, wherein the modulating is performed with a pulse amplitude modulator (PAM).
receiving, from a memory block comprising a plurality of memory cells, an encoded multi-level signal data value, wherein the encoded multi-level signal data value has been encoded with a low density parity check code (LDPC) and interleaved with bit interleaved code modulation; and
decoding the encoded multi-level signal data value to recover a multi-level signal data value,
wherein the coded multi-level signal data value has also been mapped to a modulation code in accordance with a constellation map,
wherein a set of least significant bits have been mapped to a modulation code corresponding to a lowest transmission voltage level, and a set of most significant bits have been mapped to a modulation code corresponding to a highest transmission voltage level.
20. A memory apparatus comprising:
means for encoding data values with low density parity check (LDPC) code to create LDPC encoded data values;
means for generating bit interleaved code modulation (BICM) encoded data values from the LDPC encoded data values;
means for storing BICM encoded data values, the means for storing BICM encoded data values being configured to operate with multi-level signals; and
means for mapping the BICM encoded data values to modulation codes in accordance with a constellation map,
21. The memory apparatus of claim 20, further comprising means for controlling (i) the means for encoding, (ii) the means for generating, and (iii) the means for storing.
22. The memory apparatus of claim 20, further comprising means to modulate the multi-level signals.
23. The memory apparatus of claim 20, further comprising means for deinterleaving BICM encoded data values from multi-level signals received from the means for storing the BICM encoded data values to provide de-interleaved BICM encoded data values.
24. The memory apparatus of claim 23, further comprising means for decoding the data values from the de-interleaved BICM encoded data values.
25. A memory apparatus comprising:
a pulse amplitude modulator (PAM) operatively coupled to the interleaver and the memory block, the PAM configured to modulate the interleaved LDPC encoded data values for the memory block.
26. The memory apparatus of claim 25, further comprising a channel block that comprises (i) the interleaver and (ii) the PAM.
an interleaver configured to interleave the LDPC encoded data values with bit interleaved code modulation (BICM) to generate BICM encoded data values; and
a pulse amplitude modulator (PAM) and a digital bus interface operatively coupled to the PAM and the memory block, wherein the PAM is configured to serially output multi-level signals to the memory block. Description
CROSS REFERENCE TO RELATED APPLICATIONS The present application claims priority to U.S. Patent Application No. 60/788,291, filed Mar. 31, 2006, entitled �LDPC Codes for Multi-Level Flash Memory,� the entire disclosure of which is hereby incorporated by reference in its entirety.
TECHNICAL FIELD Embodiments of the present invention relate to the field of integrated circuits, and more particularly, to providing multi-level signal memory with LDPC and interleaving.
BACKGROUND In order to increase memory capacity, manufacturers have continually moved memory chip or on-chip memory (such as flash memory) production to smaller process geometries over the last few years. Recently, multi-level signal memory cells have been used to increase flash memory capacity. In such an arrangement, a cell is configured to produce distinct signal threshold levels, which results in distinct read-back levels. With four level signals available per cell, two bits may be included into each flash memory cell. One problem with writing with four signal levels into each cell is that the distinction between adjacent levels may become difficult to discern. This is often referred to in the art as reduced signal distance (often shown as reduced Dmin).
When writing a signal level to a given cell, there is generally an amount of uncertainty in the written-in signal level. When the probable distribution of each signal level overlaps the probable distribution of adjacent signal level, the signal level generally may not be determined by using a simple prior art slicer circuit. This results in a limit on the number of signal levels that may be employed to write into every cell. At present, the state of the art is four signal levels, or two bits per cell.
SUMMARY OF THE INVENTION In accordance with various embodiments of the present invention, a memory apparatus includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. The memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values.
In accordance with various embodiments, the memory apparatus further includes a controller adapted to control the coding by the LDPC coder, the interleaving by the interleaver, and the receiving of the of the multi-level signals by the memory block.
In accordance with various embodiments, the memory apparatus further includes a mapper to map the BICM coded data values to modulation codes in accordance with a constellation map.
In accordance with various embodiments, the constellation map is based upon Gray code.
In accordance with various embodiments, the constellation map comprises 8 modulation codes.
In accordance with various embodiments, a set of least significant bits is mapped to a modulation code corresponding to a lowest transmission voltage level, and a set of most significant bits is mapped to a modulation code corresponding to a highest transmission voltage level.
In accordance with various embodiments, the memory apparatus further includes a pulse amplitude modulator (PAM) operatively coupled to the interleaver and the memory block to modulate the multi-level signals for the memory block.
In accordance with various embodiments, the memory apparatus further includes a channel block that comprises the interleaver and the PAM.
In accordance with various embodiments, the memory apparatus further includes a channel block that comprises the interleaver and at least one of the LDPC coder or the mapper.
In accordance with various embodiments, at least the memory block is configured as a flash memory device.
In accordance with various embodiments, the memory apparatus further includes a pulse amplitude modulator (PAM) and a digital bus interface operatively coupled to the PAM and the memory block, wherein the PAM is adapted to output multi-level signals to the memory block serially.
In accordance with various embodiments, the memory apparatus further includes a de-interleaver operatively coupled to the memory block to deinterleave BICM coded data values from multi-level signals received from the memory block.
In accordance with various embodiments, the memory apparatus further includes a LDPC decoder operatively coupled to the de-interleaver to decode the data values from the de-interleaved LDPC coded data values.
In accordance with various embodiments, the memory apparatus further includes a channel block that comprises the de-interleaver and the LDPC decoder.
In accordance with various embodiments of the present invention, a method includes coding a plurality of multi-level signal data values with corresponding low density parity (LDPC) codes, interleaving the LDPC coded multi-level signal data values with bit interleaved code modulation (BICM), and outputting the interleaved LDPC coded data values for storage using multi-level signals.
In accordance with various embodiments of the present invention, a method includes receiving a coded multi-level signal data value, wherein the coded multi-level signal data value has been coded with a low density parity check code (LDPC) and interleaved with bit interleaved code modulation (BICM), and decoding the coded multi-level signal data value to recover a multi-level signal data value.
FIG. 2 schematically illustrates an exemplary transistor for a flash memory cell suitable for use to practice various embodiments of the present invention;
FIG. 5 is a graph illustrating the shift profile for the probability distribution for the threshold voltage of a system of four charge level flash memory cells;
FIG. 6 schematically illustrates a high gain coding scheme in accordance with various embodiments of the present invention; and
FIGS. 7 and 8 schematically illustrate exemplary channel block implementations in accordance with various embodiments of the present invention.
Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving.
In general, a block diagram of a memory arrangement 100, in accordance with various embodiments of the present invention, is illustrated in FIG. 1. Memory arrangement 100 includes one or more memory blocks 102 that each includes memory cell arrays, as well as read and write circuits. Memory arrangement 100 also includes a channel block 104 that performs signal processing used to decode signal levels received from memory blocks 102. In accordance with various embodiments, channel block 104 also performs signal processing to code various data values to write into memory blocks 102. A controller 108 is provided to interface to external system(s) to receive and send data signals through its external data interface, to and from channel block 104. Controller 106 performs various tasks including tasks that direct where data values need to be written into or read from memory blocks 102 depending upon command instructions received through its external interface. In various embodiments, memory blocks 102 may be flash memory blocks.
In accordance with various embodiments of the present invention, a high gain coding such as, for example, trellis coded modulation (TCM) is used by channel block 104 to code and/or decode multi-level signal data values to and/or from a memory block. The addition of TCM imposes a certain constraint as to what sample sets may be adjacent to a previous and a future sample sequence. Various codes may be used to allow multi-level signals data values with a spread distribution that reduces overlaps with one another, enabling the multi-level signals data values to be more likely detected correctly, using e.g. maximum likelihood detection and decoding with trellis coding. Pulse Amplitude Modulation code (PAM), Quadrature Amplitude Modulation code (QAM) and Low Density Parity Check code (LDPC) are examples of codes that may be used. By encoding the multi-level signal data values with high gain coding and/or one or more of PAM, QAM and LDPC, a higher reliability of reading and writing the multi-level signals may be achieved within each memory cell, which in turn may lead to increase in data density of a memory array (reduce usage of memory cells for auxiliary information).
Generally, an exemplary flash memory cell, in accordance with various embodiments of the present invention and depicted in FIG. 2, includes an insulated gate transistor 200 that includes a floating gate 202 between the channel 204 and the control gate 206. Charge trapped in floating gate 202 modifies the turn-on threshold voltage. The transistor characteristics are illustrated in FIG. 3, corresponding to different charge levels stored on floating gate 202. With devices that include a plurality of memory cells arranged in arrays, many parameters that naturally vary from one device to another due to imperfect process control may affect the programmed threshold of the device. Consequently, if one were to write to many devices targeting a certain threshold value, the end result is a distribution of target threshold values instead of the desired distinct target threshold values. FIG. 4 illustrates a typical probability density function (PDF) for the target threshold voltages of a system of flash memory cells, each cell having four target charge levels.
Over time, the charge trapped in floating gate 202 generally leaks slowly and the threshold voltage may shift back towards a lower value. While the leakage is generally slow, the specification for any commercially acceptable storage device requires the data to be readable even after a ten-year period. The rate of leakage of the floating gate charge is dependent upon the voltage on floating gate 202. FIG. 5 illustrates a typical shift profile for the threshold PDF over time. Furthermore, the physics of charge leakage in a memory cell is such that each signal level may leak at a different rate from the others. As such, over time, the signal levels generally will not drop at the same rate.
Thus, as an example, in accordance with various embodiments of the present invention, in a write mode, multi-level signals that are employed to write various data into memory cells within the memory block are encoded with the high gain coding. The high gain encoded data signals are output to the memory blocks to write data into the memory block cells.
During a read mode, in accordance with various embodiments of the present invention, memory blocks 102 responsive to the commands of controller 108 output data that is stored in at least one memory cell. In accordance with various embodiments, data stored in a whole row of memory cells may be outputted at different read-back signal levels. The multi-level read-back signals for each cell are transferred to channel block 104. If a small interface is desired, the signals may be transferred in a serial fashion. In one embodiment, analog to digital conversion or a digitizing function (not shown), may be performed by an analog to digital converter (ADC) that is included on memory block 102 if inclusion of such ADC is practical. Thus, the signal levels may be transferred as digitized data and sent back to channel block 104 serially. Otherwise, in accordance with various embodiments, analog signals may be transferred back to channel block 104 from memory block 102 as discrete time analog signals. Such transfers, in accordance with various embodiments, may be done serially if desired, or in parallel, in other embodiments. In a serial embodiment, the channel block may either digitize the signal or not based upon whether an analog or digital channel implementation is used. In accordance with various embodiments of the present invention a digital channel implementation is used and thus, the channel block includes an ADC, and memory block 102 and channel block 104 are operatively coupled to one another via a digital bus interface.
More particularly, with reference to FIG. 6, a coding scheme in accordance with various embodiments of the present invention includes multi-level signal data values being received at channel block 104 from controller 108. The received data values are encoded with LDPC via LDPC encoder/de-coder 600. The LDPC coded values are then passed through an interleaver 602. The interleaved values are mapped to constellation points by the constellation mapper at 604. Thus, the system implements bit-interleaved coded modulation (BICM). In accordance with various embodiments, Gray code mapping is used. In accordance with various embodiments, the constellation map includes 8 constellation points. Those skilled in the art will understand that fewer constellation points may be used if desired, e.g., 4 or 2 constellation points, or if possible, more constellation points, e.g., 16, 32, etc. The mapped values are transferred from channel block 104 to memory block 102 and written into a memory cell of memory block 102.
In accordance with various embodiments of the present invention, PAM is used to transmit signals between channel block 104 and memory block 102. Thus, in accordance with various embodiments, there are 8 channels for the PAM. As an example, the channels may include −7 v, −5 v, −3 v, −1 v, +1 v, +3 v, +5 v and +7 v transmission voltage levels. In accordance with various embodiments of the present invention, a least significant bit (e.g. bit 0) represents the lowest or �worst� channel, while a most significant bit (e.g. bit 100) represents the highest or �best� channel.
When data needs to be retrieved from memory block 102, coded multi-level signal data values are transferred from the memory block to channel block 104, where they are decoded. Thus, in accordance with various embodiments, the LDPC encoder/de-coder, interleaver and mapper are included with channel block 104.
Thus, with a coding scheme in accordance with various embodiments of the present invention, more levels may be realized on a multi-level memory device since the coding allows for more reliable retrieval of data values from the memory, even with the reduced distance between levels.
In accordance with various embodiments, an exemplary channel block 104 may be configured similar to generally known communication or magnetic hard disk drive (HDD) channels, as illustrated in FIG. 7. As may be seen in FIG. 7, such an exemplary channel block 104 may include an interface 700, a run length limited (RLL) encoder 702 and channel modulation 704 along a write path. The exemplary channel block 104 may further include a variable gain amplifier (VGA) 706, an offset setting 708, a continuous time filter (CTF) block 710, an ADC 712, a finite impulse response (FIR) block 714, a Viterbi detector 716, an RLL decoder 718, error generators 720, an offset control loop 722, a gain control loop 724, a clock recovery 726 and clock generator 728 along a read path, coupled to each other substantially as illustrated.
Some simplification may be made from a conventional channel block. For example, since data sampling and transfer, in accordance with various embodiments, are clocked synchronously, there is no need to include a timing recovery circuit (726, 728) in channel block 104. Such a timing recovery circuit may be included if desired such as, for example, for very high data-rate applications. However, generally the sampling clock frequency matches exactly to the incoming data signal frequency and thus, only the delay is potentially unknown. For such a system only a Type I timing recovery loop may be desired.
Additionally, the signal returning from memory block 102 may match well to the target response, i.e., the original signal, such that linear equalizers in the channel block (CTF 710 and FIR 714) may not be necessary. Other functional blocks typical of a communication/HDD channel may be included, in accordance with various embodiments of the present invention, for memory arrangement 100. In particular, as noted above, automatic gain control loop 724, Viterbi detector 716 (with trellis control) and channel encoder/decoder (702, 718) may also be included.
Often, standard deviation in the distribution of each target signal level is different from the others, and the mean distance between two adjacent ideal signal levels may not be constant relative to the design target. Thus, in accordance with various embodiments, Viterbi detector 716 may implement adaptive and non-linear branch metrics calculators (e.g., the Viterbi detector may use a subset non-linear detector algorithm used in magnetic HDD).
In accordance with various embodiments of the present invention, channel block 104 may also include a sample data buffer capable of storing a large section of data samples so iterative or over-a-block processing may be performed (e.g., block averaging for gain control so that signal levels may become normalized before other processing by the channel block). An example of such an arrangement for channel block 104 is schematically illustrated in FIG. 8. As may be seen, such an exemplary channel block 104 may include an interface 800, RLL encoder 802 and channel modulation 804 along a write path. The exemplary channel block 104 may further include a VGA 806, offset setting 808, ADC 810, sample buffer 812, offset setting 814, gain control 816, offset setting 818, feed forward offset control 820, offset setting 822, gain control 824, offset setting 826, offset control 828, error generator 830, Viterbi detector 832 and RLL decoder 834, coupled to each other substantially as illustrated.
In accordance with various embodiments of the present invention, at least the memory block, and even the entire memory arrangement, is a flash-type memory device. For clarity, the present invention has been substantially described as such, although those skilled in the art will understand that other types of memory may benefit from the present invention. Additionally, in accordance with various embodiments of the present invention, the present invention is useful for many types of memory devices such as, for example and not limited to, floating gate devices, oxide-nitride-oxide (ONO) charged trapping devices, and phase change memory devices.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6125050 *Jun 17, 1999Sep 26, 2000Siemens AktiengesellschaftConfiguration for driving parallel lines in a memory cell configurationUS7373581 *Nov 26, 2003May 13, 2008Nec CorporationDevice, program, and method for decoding LDPC codesUS7421041 *Mar 1, 2004Sep 2, 2008Qualcomm, IncorporatedIterative channel and interference estimation and decodingUS7516390 *Nov 2, 2005Apr 7, 2009Broadcom CorporationLDPC (Low Density Parity Check) coding and interleaving implemented in MIMO communication systems* Cited by examinerNon-Patent CitationsReference1802.11h, IEEE Standard for Information technology-Telectommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications, Amendment 6: Medium Access Control (MAC) Security Enhancements, IEEE Std 802.11i-2004, 190 pgs.2802.11h, IEEE Standard for Information technology�Telectommunications and information exchange between systems�Local and metropolitan area networks�Specific requirements, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications, Amendment 6: Medium Access Control (MAC) Security Enhancements, IEEE Std 802.11i�2004, 190 pgs.3802.11h, IEEE Standard for Information technology-Telectommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications, Amendment 5: Spectrum and Transmit Power Management Extensions in the 5 GHz band in Europe, IEEE Std 802.11h-2003, 75 pgs.4802.11h, IEEE Standard for Information technology�Telectommunications and information exchange between systems�Local and metropolitan area networks�Specific requirements�Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications, Amendment 5: Spectrum and Transmit Power Management Extensions in the 5 GHz band in Europe, IEEE Std 802.11h�2003, 75 pgs.5Draft Supplement to Standard [for] Information Technology-Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Further Higher-Speed Physical Layer Extension in the 2.4 GHz Band, IEEE Std 802.11g/D2.8, May 2002, 53 pgs.6Draft Supplement to Standard [for] Information Technology�Telecommunications and information exchange between systems�Local and metropolitan area networks�Specific requirements�Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Further Higher-Speed Physical Layer Extension in the 2.4 GHz Band, IEEE Std 802.11g/D2.8, May 2002, 53 pgs.7Draft Supplement to Standard for Information Technology-Telecommunications and Information Exchange Between Systems-LAN/MAN Specific Requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Specification for Enhanced Security, IEEE STD 802.11i/D3.0, Nov. 2002, 211 pgs.8Draft Supplement to Standard for Information Technology�Telecommunications and Information Exchange Between Systems�LAN/MAN Specific Requirements�Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Specification for Enhanced Security, IEEE STD 802.11i/D3.0, Nov. 2002, 211 pgs.9Gregori S et al: "Construction of polyvalent error control codes for multilevel memories", Proc. Intern. Conference on Electronics, Circuits and Systems, vol. 2, Dec. 17, 2000, pp. 751-754, XP010535817.10Hsi-Chia Chang et al: "Multi-level memory systems using error control codes", Proceedings of the 2004 International Symposium on Circuits and Systems, vol. 2, May 23, 2004, pp. 393-396, XP010720188.11IEEE P802.11, Wireless LANs, TGn Sync Proposal Technical Specification, May 18, 2005, IEEE 802.11-04/08898r6, 131 pgs.12IEEE P802.11g/D8.2, Draft Supplement to Standard [for] Information Technology-Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specification: Further Higher Data Rate Extension in the 2.4 GHz Band, Apr. 2003, 69 pgs.13IEEE P802.11g/D8.2, Draft Supplement to Standard [for] Information Technology�Telecommunications and information exchange between systems�Local and metropolitan area networks�Specific requirements�Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specification: Further Higher Data Rate Extension in the 2.4 GHz Band, Apr. 2003, 69 pgs.14IEEE P802.11g/D8.2, Draft Supplement to Standard [for] Information Technology-Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Further Higher Data Rate Extension in the 2.4 GHz Band, Apr. 2003, 69 pgs.15IEEE P802.11g/D8.2, Draft Supplement to Standard [for] Information Technology�Telecommunications and information exchange between systems�Local and metropolitan area networks�Specific requirements�Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Further Higher Data Rate Extension in the 2.4 GHz Band, Apr. 2003, 69 pgs.16IEEE Standard for Information technology-Telectommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Amendment 2: Higher-Speed Physical Layer (PHY) extension in the 2.4 [continued on p. 2] HGz Band-Corrigendum 1, IEEE Std 802.11b-1999/Cor Jan. 2001, 23 pgs.17IEEE Standard for Information technology�Telectommunications and information exchange between systems�Local and metropolitan area networks�Specific requirements�Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Amendment 2: Higher-Speed Physical Layer (PHY) extension in the 2.4 [continued on p. 2] HGz Band-Corrigendum 1, IEEE Std 802.11b-1999/Cor Jan. 2001, 23 pgs.18IEEE Standard for Information technology-Telectommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Amendment 7: Medium Access Control (MAC) Quality of Service (QoS) Enhancements, IEEE 802.11e/D11.0, Oct. 2004, 195 pgs.19IEEE Standard for Information technology�Telectommunications and information exchange between systems�Local and metropolitan area networks�Specific requirements�Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Amendment 7: Medium Access Control (MAC) Quality of Service (QoS) Enhancements, IEEE 802.11e/D11.0, Oct. 2004, 195 pgs.20International Standard, Information technology-Telectommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications, ISO/IEC 8802-11:1999(E), ANSI/IEEE, Std 802.11, 1999 edition, 531 pages.21International Standard, Information technology�Telectommunications and information exchange between systems�Local and metropolitan area networks�Specific requirements�Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications, ISO/IEC 8802-11:1999(E), ANSI/IEEE, Std 802.11, 1999 edition, 531 pages.22Lou H-L et al: "Coded Modulation to Increase Storage Capacity of Multilevel Memories", Proc. IEEE Globecom 1998, vol. vol 6, 1998, pp. 3379-3384, XP000805261.23Rossi D et al: "Fast and compact error correcting scheme for reliable multilevel flash memories", Proceedings of the Eighth IEEE International On-Line Testing Workshop, Jul. 8, 2002, pp. 221-225, XP010601444.24Supplemental to IEEE Standard for Information technology-Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Higher-Speed Physical Layer Extension in the 2.4 HGz Band, IEEE Std 802.11b-1999, 96 pgs.25Supplemental to IEEE Standard for Information technology�Telecommunications and information exchange between systems�Local and metropolitan area networks�Specific requirements�Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Higher-Speed Physical Layer Extension in the 2.4 HGz Band, IEEE Std 802.11b-1999, 96 pgs.26Supplemental to IEEE Standard for Information technology-Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer in the 5 GHZ Band, IEEE Std 802.11a-1999, 91 pgs.27Supplemental to IEEE Standard for Information technology�Telecommunications and information exchange between systems�Local and metropolitan area networks�Specific requirements�Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer in the 5 GHZ Band, IEEE Std 802.11a-1999, 91 pgs.28Winstead C: "Analog Soft Decoding for Multi-Level Memories", Proceedings 35th International Symposium on Multiple-Valued Logic, May 19, 2005, pp. 132-137, XP010798331.29Zhang Zhi et al: "Low-density parity-check codes and high spectral efficiency modulation", Proc. Personal, Indoor and Mobile Radio Communications Conference, Sep. 7, 2003, pp. 444-448, XP010681635.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8219886 *Dec 21, 2006Jul 10, 2012Marvell International Ltd.High density multi-level memoryUS8527849 *Jun 15, 2012Sep 3, 2013Stec, Inc.High speed hard LDPC decoderUS8560919 *Feb 21, 2011Oct 15, 2013Sandisk Technologies Inc.System and method of interleaving data according to an adjustable parameterUS8583991Jul 5, 2012Nov 12, 2013Marvell International Ltd.High density multi-level memoryUS20120102379 *Feb 21, 2011Apr 26, 2012Sandisk CorporationSystem and method of interleaving data according to an adjustable parameter* Cited by examinerClassifications U.S. Classification714/785, 714/774, 714/778International ClassificationH03M13/00Cooperative ClassificationH03M13/255, G06F11/1072, H03M13/11, G11C11/5621European ClassificationH03M13/25L, H03M13/11, G06F11/10M10Legal EventsDateCodeEventDescriptionMar 15, 2007ASAssignmentOwner name: MARVELL INTERNATIONAL LTD., BERMUDAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL SEMICONDUCTOR, INC.;REEL/FRAME:019020/0666Effective date: 20070307Owner name: MARVELL WORLD TRADE LTD., BARBADOSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL INTERNATIONAL LTD.;REEL/FRAME:019020/0694Effective date: 20070308Free format text: LICENSE;ASSIGNOR:MARVELL WORLD TRADE LTD.;REEL/FRAME:019020/0741Effective date: 20070312Jan 25, 2007ASAssignmentOwner name: MARVELL SEMICONDUCTOR, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RAMAMOORTHY, ADITYA;REEL/FRAME:018805/0950Effective date: 20070124RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google