Source: https://patents.google.com/patent/US9690314B2/en
Timestamp: 2018-12-11 04:48:16
Document Index: 653401293

Matched Legal Cases: ['Application No. 61', 'Application No. 200880120050', 'Application No. 200980110230', 'Application No. 200980110230', 'Application No. 200980137436', 'Application No. 200980110230', 'Application No. 2010', 'Application No. 201410214282', 'Application No. 098132132']

US9690314B2 - Inductive load power switching circuits - Google Patents
US9690314B2
US9690314B2 US14332967 US201414332967A US9690314B2 US 9690314 B2 US9690314 B2 US 9690314B2 US 14332967 US14332967 US 14332967 US 201414332967 A US201414332967 A US 201414332967A US 9690314 B2 US9690314 B2 US 9690314B2
US14332967
US20140327412A1 (en )
This application is a divisional of U.S. application Ser. No. 13/959,483, filed Aug. 5, 2013, which is a continuation of U.S. application Ser. No. 13/618,726, filed Sep. 14, 2012 (now U.S. Pat. No. 8,531,232), which is a continuation of U.S. application Ser. No. 12/556,438, filed Sep. 9, 2009 (now U.S. Pat. No. 8,289,065), which claims the benefit of U.S. Provisional Application No. 61/099,451, filed Sep. 23, 2008. The entire disclosure of each of the prior applications is hereby incorporated by reference.
A single-sided switch is a switching configuration where a switching device is used either to connect the load to a node at a lower potential—a “low-side” switch—or to a node at a higher potential—a “high-side” switch. The low-side configuration is shown in FIG. 1a , and the high-side configuration is shown in FIG. 2a , where the node at higher potential is represented by a high voltage (HV) source and the node at lower potential is represented by a ground terminal. In both cases, when the load 10 is an inductive load, a freewheeling diode 11 (sometimes referred to as a flyback diode) is required to provide a path for the freewheeling load current when the switching device is OFF. For example, as seen in FIG. 1b , when the switching device 12 is biased high by applying a gate-source voltage Vgs greater than the device threshold voltage Vth, current 13 flows through the load 10 and through switching device 12, and diode 11 is reverse biased such that no significant current passes through it. When switching device 12 is switched to low by applying a gate-source voltage Vgs<Vth, as shown in FIG. 1c , the current passing through the inductive load 10 cannot terminate abruptly, and so current 13 flows through the load 10 and through diode 11, while no significant current flows through switching device 12. Similar diagrams detailing current flow through the high-side switching configuration when the switch is biased high and when the switch is turned off (switched low) are shown in FIGS. 2b and 2c , respectively.
An alternative to the configurations illustrated in FIGS. 1 and 2 is to instead use synchronous rectification, as illustrated in FIGS. 3a-e . FIG. 3a is the same as FIG. 2a , except that a high-voltage metal-oxide-semiconductor (MOS) transistor 61 is included anti-parallel with diode 11. A standard MOS transistor inherently contains an anti-parallel parasitic diode and can therefore be represented as a transistor 62 anti-parallel to a diode 63, as illustrated in FIG. 3a . As seen in FIG. 3b , when switching device 12 is biased high and MOS transistor 61 is biased low, MOS transistor 61 and diode 11 both block a voltage equal to that across the load, so that the entire current 13 flows through the load 10 and through switching device 12. When switching device 12 is switched to low, as shown in FIG. 3c , diode 11 prevents transistor 62 and parasitic diode 63 from turning on by clamping the gate-drain voltage to a value less than Vth of the transistor and less than the turn-on voltage of the parasitic diode. Therefore, almost all of the freewheeling current flows through diode 11, while only a small, insignificant portion flows through the transistor channel and parasitic diode. As shown in FIG. 3d , MOS device 61 may then be biased high, which results in an increase in the channel conductivity of transistor 62 and thereby cause the majority of the freewheeling current to flow through the transistor channel. However, some dead time must be provided between turn-off of switching device 12 and turn-on of transistor 62 in order to avoid shoot-through currents from the high-voltage supply (HV) to ground. Therefore, diode 11 will be turned on for some time immediately after switching device 12 is switched from high to low and immediately before switching device 12 is switched back from low to high. While this reduces the conduction losses incurred by diode 11 in the absence of MOS transistor 61, the full switching loss for diode 11 is incurred, regardless of how long the diode remains on.
As shown in FIG. 3e , the circuit in FIGS. 3a-d can in principle operate without diode 11. In this case, parasitic diode 63 performs the same function that diode 11 performed in the circuit of FIGS. 3a-d . However, the parasitic diode 63 typically has much poorer switching characteristics and suffers from higher switching losses than a standard high-voltage diode, resulting in increased power loss, so the circuit of FIGS. 3a-d is usually preferred.
Many power switching circuits contain one or more high-side or low-side switches. One example is the boost-mode power-factor correction circuit shown in FIG. 4a , which contains a low-side switch. This circuit is used at the input end in AC-to-DC voltage conversion circuits. The configuration for the low-side switch in this circuit is slightly modified from that shown in FIG. 1a , since in FIG. 1a the freewheeling diode 11 is connected anti-parallel to the inductive load 10, whereas in this circuit the freewheeling diode 11 is between the inductive load 30 and the output capacitor 35. However, the fundamental operating principles of the two circuits are the same. As seen in FIG. 4b , when switching device 12 is biased high, current 13 passes through the load 30 and through the switching device 12. The voltage at the cathode end of the freewheeling diode 11 is kept sufficiently high by the output capacitor 35 so that the freewheeling diode 11 is reverse-biased, and thereby does not have any significant current passing through it. As seen in FIG. 4c , when switching device 12 is switched low, the inductor forces the voltage at the anode of the freewheeling diode 11 to be sufficiently high such that the freewheeling diode 11 is forward biased, and the current 13 then flows through the inductive load 30, the freewheeling diode 11, and the output capacitor 35. Because no significant current can flow in the reverse direction in a diode, diode 11 prevents discharge of the output capacitor 35 through switching device 12 during times where the load current is zero or negative, as can occur if the energy stored in the inductor 30 is completely transferred out before the commencement of the next switching cycle.
In some embodiments, the following features are present. The first mode of operation can comprise biasing the gate of the first switching device above a threshold voltage of the first switching device. The second mode of operation can comprise biasing the gate of the first switching device below a threshold voltage of the first switching device. The first switching device can have a first terminal and a second terminal on opposite sides of the gate, and the first terminal can be adjacent to the assembly and at a higher voltage than the second terminal of the first switching device during operation. The first switching device can have a first terminal and a second terminal on opposite sides of the gate, and the first terminal can be adjacent to the assembly and at a lower voltage than the second terminal of the first switching device during operation. A first node can be between the assembly and the first switching device, a second node can be at a high voltage side of the switch, and the second switching device can be capable of blocking a voltage when voltage at the first node is lower than voltage at the second node. A first node can be between the assembly and the first switching device, a second node can be at a low voltage or ground side of the switch, and the second switching device can be capable of blocking a voltage when voltage at the first node is higher than voltage at the second node. The second switching device can be capable of blocking a same voltage as the first switching device is capable of blocking. The second switching device can be capable of blocking voltage in two directions. When the gate of the first switching device is biased lower than a threshold voltage of the first switching device, the second switching device can be capable of conducting current. When the gate of the first switching device is biased lower than the threshold voltage of the first switching device, substantially all current can flow through a single primary channel of the second switching device. When the gate of the second switching device is biased higher than the threshold voltage of the second switching device, the voltage drop across the second switching device can be reduced as compared to when the gate of the second switching device is biased lower than the threshold voltage of the second switching device. The second switching device can have a positive threshold voltage. The first switching device can have a positive threshold voltage. The second switching device can be a HEMT. The second switching device can be a III-Nitride HEMT. The first switching device can be a HEMT. The first switching device can be a III-Nitride HEMT. The second switching device can be structurally the same as the first switching device. A voltage drop across the second switching device can be smaller in the third mode of operation as compared to in the second mode of operation. The load can be an inductive load. The first switching device or the second switching device can comprise a high-voltage depletion mode device and a low-voltage enhancement mode device, the second channel can be a channel of the high-voltage depletion mode device, and the threshold voltage of the second switching device can be a threshold voltage of the low-voltage enhancement mode device. The low-voltage enhancement mode device can at least block a voltage equal to an absolute value of a threshold voltage of the high-voltage depletion mode device. The high-voltage depletion mode device can be a III-Nitride HEMT. The low-voltage enhancement mode device can be a III-Nitride HEMT. The low-voltage enhancement mode device can be a Si MOS device. The device can include a diode connected antiparallel to the low-voltage enhancement mode device. The first switching device can comprise a high-voltage depletion mode device and a low-voltage enhancement mode device, the first channel can be a channel of the high-voltage depletion mode device, and a threshold voltage of the first switching device can be a threshold voltage of the low-voltage enhancement mode device.
FIGS. 1a-c show schematics of a low-side switch, and current paths for various bias conditions.
FIGS. 2a-c show schematics of a high-side switch, and current paths for various bias conditions.
FIGS. 3a-e show schematics of high-side switches with a MOSFET connected across the inductive load, and current paths for various bias conditions.
FIGS. 4a-c show schematics of a boost-mode power-factor correction circuit and current paths for various bias conditions.
FIGS. 5a-d show schematics of a low-side switch, along with current paths for various bias conditions.
FIG. 5e shows a biasing scheme for the switching devices in the circuits of FIGS. 5a -d.
FIGS. 6a-d show schematics of a high-side switch, along with current paths for various bias conditions.
FIG. 6e shows a biasing scheme for the switching devices in the circuits of FIGS. 6a -d.
FIGS. 8a-d show schematics of a boost-mode power-factor correction circuit, along with current paths for various bias conditions.
FIG. 8e shows a biasing scheme for the switching devices in the circuits of FIGS. 8a -d.
FIGS. 9a-c show the input current as a function of time for various operating conditions for the circuit in FIG. 8.
Low-side and high-side switches and the circuits which they comprise, wherein the freewheeling diode shown in FIGS. 1-3 is replaced by a switching device, such as a transistor, are described below. Embodiments are shown in FIGS. 5a and 6a , wherein FIG. 5a comprises a low-side switch, and FIG. 6a comprises a high-side switch. In FIGS. 5a and 6a , the freewheeling diode used in the circuits of FIGS. 1 and 2 has been replaced by switching device 41. In some embodiments, this device may be the same as the switching device 42 used to modulate the current path. FIGS. 5b and 6b illustrate the current path when switching device 42 is biased ON (high) and switching device 41 is biased OFF (low). FIGS. 5c and 6c illustrate the current path when switching device 42 is switched OFF. Switching device 41 can be an enhancement mode device, where the threshold voltage Vth>0, or a depletion mode device, where the threshold voltage Vth<0. In high power applications, it is desirable to use enhancement mode devices with threshold voltages as large as possible, such as Vth>2V or Vth>3V, a high internal barrier from source to drain at 0 bias (such as 0.5-2 eV), a high ON-to-OFF current ratio (such as >105), along with high breakdown voltage (600/1200 Volts) and low on resistance (<5 or <10 mohm-cm2 for 600/1200 V respectively).
Additionally, switching device 41 must have the following characteristics. It must be able to block significant voltage when the voltage at terminal 45/55 is lower than the voltage at terminal 46/56. This condition occurs when switching device 42 is biased high, as shown in FIGS. 5b and 6b . As used herein, “blocking a voltage” refers to the ability of a transistor to prevent a current that is greater than 0.0001 times the operating current during regular conduction from flowing through the transistor when a voltage is applied across the transistor. In other words, while a transistor is blocking a voltage which is applied across it, the total current passing through the transistor will not be greater than 0.0001 times the operating current during regular conduction. As used herein, “substantial current” includes any current which is at least ten percent of the operating current during regular conduction. The maximum voltage that switching device 41 must be able to block depends on the particular circuit application, but in general will be the same or very close to the maximum blocking voltage specified for switching device 42. In some embodiments, switching device 41 is able to block voltage in both directions. When switching device 42 is switched OFF, switching device 41 must be capable of conducting current 13 in the direction shown in FIGS. 5c and 6c . Furthermore, when the circuit is biased such as shown in FIG. 5c or 6 c, all substantial current through switching device 41 flows through a single, primary channel of the device, wherein the conductivity of this channel may be modulated by the gate electrode. This is different from the circuits in FIGS. 3a-3e , for which applying a voltage signal to the gate electrode of device 61 causes the current to shift from one channel (that of diode 11 or 63) to that of the transistor 62. The maximum current that switching device 41 must be able to conduct in this direction depends on the particular circuit application, but in general will be the same or very close to the maximum current specified for switching device 42. In some embodiments, the switching devices are able to conduct current in both directions.
The detailed operation of the circuit in FIG. 5 is as follows. When switching device 42 is biased ON, such as by setting the gate-source voltage VGS42 greater than the device threshold voltage Vth42, and switching device 41 is biased OFF, such as by setting VGS41<Vth41, current 13 flows through inductive load 10 and switching device 42, as seen in FIG. 5b . Here, switching device 41 is said to be in “blocking mode”, as it is supporting a voltage across it while at the same time blocking current from flowing through it, i.e., device 41 is blocking voltage. As shown in FIG. 5c , when switching device 42 is switched OFF, the current through the inductive load 10 cannot change abruptly, so the voltage at terminal 45 is forced sufficiently high to allow the freewheeling current 13 to be carried through switching device 41. Note that in this mode of operation, current is able to flow through switching device 41 even if VGS41 is not changed. This mode of operation for switching device 41 is known as “diode mode operation”. The circuit of FIG. 5 may be preferable to that of FIG. 1 because transistors suitable for use in this application typically have lower conduction and switching losses than diode 11.
Depending on the current level and the threshold voltage of switching device 41, the power dissipation through this device could be unacceptably high when operating in the diode mode. In this case, a lower power mode of operation may be achieved by applying a voltage VGS41>Vth41 to the gate of switching device 41, as shown in FIG. 5d . To prevent shoot-through currents from the high-voltage supply (HV) to ground, gate signals of the form shown in FIG. 5e are applied. The time during which switching device 42 is ON and switching device 41 is OFF is labeled “C” in FIG. 5e . This corresponds to the mode of operation shown in FIG. 5b . When switching device 42 is switched OFF, during the time switching device 41 conducts the freewheeling current, the gate of switching device 41 is driven high, allowing the drain-source voltage of switching device 41 to be simply the on-state resistance (Rdds-on) times the load current. To avoid shoot-through currents from the high-voltage supply (HV) to ground, some dead time must be provided between turn-off of switching device 42 and turn-on of switching device 41. These are the times labeled “A” in FIG. 5e . During these dead times, switching device 41 operates in the diode mode described above. Since this is a short time in comparison with the entire switching cycle, the relative amount of total power dissipation is low. Time “B” provides the dominant loss factor for switching device 41, and this corresponds to the low-power mode when switching device 41 is fully enhanced. The mode of operation illustrated in FIG. 5d allows for a further reduction in conduction loss, although switching losses remain unaffected.
In the circuit of FIG. 5, when switching device 42 is switched OFF, all substantial current flows through the primary channel of switching device 41 when the gate of switching device 41 remains low (FIG. 5c ) as well as when it is driven high (FIG. 5d ). This may be preferable to the operation of the circuit in FIG. 3, for which substantial current initially flows through a diode while transistor 61 remains low and only flows through the primary transistor channel once the gate of transistor 61 is driven high. Diode 11 and parasitic diode 63 in FIG. 3 typically exhibit higher switching losses than transistors 41 suitable for use in the circuit of FIG. 5. Additionally, switching devices 41 and 42 in FIG. 5 can be identical or similar devices, which simplifies the fabrication of this circuit.
The detailed operation of the circuit in FIG. 6 is similar to that of FIG. 5. When switching device 42 is biased ON, such as by setting VGS42>Vth42, and switching device 41 is biased OFF, such as by setting VGS41<Vth41, current 13 flows through inductive load 10 and switching device 42, as seen in FIG. 6b . As shown in FIG. 6c , when switching device 42 is switched OFF, the current through the inductive load 10 cannot change abruptly, so the voltage at terminal 56 is forced sufficiently negative to allow the freewheeling current 13 to be carried through switching device 41, and switching device 41 now operates in diode mode. Again, in this mode of operation, current is able to flow through switching device 41 even if VGS41 is not changed. As with the circuit of FIG. 5, power dissipation during diode mode operation of switching device 41 may be reduced by applying a voltage VGS41>Vth41 to the gate of switching device 41, as shown in FIG. 6d . Again, some dead time must be provided between turn-off of switching device 42 and turn-on of switching device 41 in order to avoid shoot-through currents from the high-voltage supply (HV) to ground, and so the bias scheme shown in FIG. 6e is used.
Preferably, switching device 41 is an enhancement mode device to prevent accidental turn on, in order to avoid damage to the device or other circuit components. III-Nitride (III-N) devices, such as III-Nitride HFETs, are especially desirable due to the large blocking voltages that can be achieved with these devices. The device preferably also exhibits a high access region conductivity (such as sheet resistance<750 ohms/square) along with high breakdown voltage (600/1200 Volts) and low on resistance (<5 or <10 mohm-cm2 for 600/1200 V respectively). The device can also include any of the following: a surface passivation layer, such as SiN, a field plate, such as a slant field plate, and an insulator underneath the gate. In other embodiments, switching device 41 is a SiC JFET.
A boost-mode power-factor correction circuit is shown in FIG. 8a . This circuit is similar to that shown in FIG. 4a , except that diode 11 has been replaced by a switching device 41 connected to a floating gate-drive circuit 72. Switching device 41 must meet the same specifications as switching device 41 in FIGS. 5 and 6. The details of operation of this circuit are as follows. When switching device 42 is biased ON and switching device 41 is biased OFF, as seen in FIG. 8b , current 13 passes through the load 30 and through the switching device 42. The voltage at node 77 is kept sufficiently high by the output capacitor 35 so that switching device 41 is in blocking mode, and thereby does not have any substantial current passing through it. As seen in FIG. 8c , when switching device 42 is switched OFF, the inductor forces the voltage at node 76 to be sufficiently high such that switching device 41 switches to diode mode, and the current 13 then flows through the inductive load 30, switching device 41, and the output capacitor 35.
As with the circuits in FIGS. 5 and 6, conduction losses in this circuit can be reduced by applying a voltage VGS41>Vth41 to the gate of switching device 41, as shown in FIG. 8d . However, for this circuit to operate properly, the timing of the signals applied by gate-drive circuit 72 to the gate of switching device 41 must be properly controlled. There are three cases which need to be considered independently. The first, illustrated in FIG. 9a , is the case where the load current is continuous (continuous mode). The second, illustrated is FIG. 9b , is the case where the load current is discontinuous (discontinuous mode), such that no current flows during some portion of the duty cycle. For this second case, it is also possible that the load current is negative (flows in the opposite direction through the load) during some portion of the duty cycle. This may occur if there are any inductive or capacitive components leading into the input of this circuit. The third, illustrated in FIG. 9c , is the case where the load current approaches zero but then immediately increases again. This mode is known as the “critical mode”.
If the load current is continuous, then the timing of the gate signals to switching devices 42 and 41 is similar to that of the circuits in FIGS. 5 and 6. To allow the load current to flow through switching device 42, switching device 42 is switched ON and switching device 41 is switched OFF, as in FIG. 8b . When switching device 42 is switched OFF, the inductor forces the load current through switching device 41 as shown in FIG. 8c , and switching device 41 is in diode mode. While current flows through switching device 41, conduction losses can be reduced by applying a voltage VGS41>Vth41 to the gate of switching device 41, as shown in FIG. 8d . Some dead time must be provided between turn-off of switching device 42 and turn-on of switching device 41 in order to prevent the capacitor 35 from discharging through switching devices 42 and 41, and so the bias scheme shown in FIG. 8e is used.
1. A power-factor correction circuit, comprising:
a second switching device, the second switching device comprising a depletion mode device and an enhancement mode device, the enhancement mode device including a gate, the depletion mode device including a channel;
wherein the first switching device is connected to a node between the inductive load and the second switching device, and the second switching device is between the inductive load and the capacitor, and
wherein the power-factor correction circuit is configured such that
in a first mode of operation current flows through the channel of the depletion mode device in a first direction when the gate of the enhancement mode device is biased below a threshold voltage of the enhancement mode device,
in a second mode of operation current flows through the channel of the depletion mode device in the first direction when the gate of the enhancement mode device is biased above the threshold voltage of the enhancement mode device, and
in a third mode of operation the depletion mode device blocks voltage applied in a second direction across the switching device and the enhancement mode device blocks a voltage at least equal to an absolute value of a threshold voltage of the depletion mode device.
2. The power-factor correction circuit of claim 1, wherein in the third mode of operation the gate of the enhancement mode device is biased below the threshold voltage of the enhancement mode device.
3. The power-factor correction circuit of claim 1, wherein the depletion mode device is a high-voltage device, the enhancement mode device is a low-voltage device, and the second switching device is configured to operate as a high-voltage enhancement mode device.
4. The power-factor correction circuit of claim 1, wherein the depletion mode device comprises a III-N HEMT.
5. The power-factor correction circuit of claim 4, wherein the enhancement mode device comprises a Si MOS device or a III-N HEMT.
6. The power-factor correction circuit of claim 4, wherein the enhancement mode device comprises a Si MOS device, the Si MOS device includes an inherent parasitic diode, and the switching device further comprises a Schottky diode connected antiparallel to the Si MOS device.
7. A power-factor correction circuit, comprising:
a first switching device comprising a first depletion mode transistor and a first enhancement mode transistor;
a second switching device comprising a second depletion mode transistor and a second enhancement mode transistor, wherein the first and second depletion mode transistors each comprise III-N HEMTs;
an inductive component; and
wherein the inductive component, the first switching device and the second switching device are connected to a first node, and the second switching device and the capacitor are connected to a second node, and
wherein the power-factor correction circuit is configured such that in a first mode of operation current flows through a channel of the second depletion mode transistor in a first direction when a gate of the second enhancement mode transistor is biased below a threshold voltage of the second enhancement mode transistor, and in a second mode of operation current flows through the channel of the second depletion mode transistor in the first direction when the gate of the second enhancement mode transistor is biased above the threshold voltage of the second enhancement mode transistor.
8. The power-factor correction circuit of claim 7, wherein the first and second enhancement mode transistors each comprise Si MOS devices.
9. The power-factor correction circuit of claim 7, wherein the power-factor correction circuit is configured such that in a third mode of operation the second depletion mode transistor blocks voltage applied in a second direction across the second switching device.
10. The power-factor correction circuit of claim 9, wherein in the third mode of operation the second enhancement mode transistor blocks a voltage at least equal to an absolute value of a threshold voltage of the second depletion mode transistor.
11. The power-factor correction circuit of claim 9, wherein in the third mode of operation the gate of the second enhancement mode transistor is biased below the threshold voltage of the second enhancement mode transistor.
12. A method of forming a power-factor correction circuit, comprising:
providing a first switching device, an inductive load, a capacitor, and a second switching device, the second switching device comprising a depletion mode device and an enhancement mode device, the enhancement mode device including a gate, the depletion mode device including a channel;
connecting the first switching device to a node between the inductive load and the second switching device, wherein the second switching device is between the inductive load and the capacitor; and
configuring the power-factor correction circuit such that
13. The method of claim 12, wherein in the third mode of operation the gate of the enhancement mode device is biased below the threshold voltage of the enhancement mode device.
14. The method of claim 12, wherein the depletion mode device is provided as a high-voltage device, the enhancement mode device is provided as a low-voltage device, and the second switching device is configured to operate as a high-voltage enhancement mode device.
15. The method of claim 12, wherein the depletion mode device comprises a III-N HEMT.
16. The method of claim 15, wherein the enhancement mode device comprises a Si MOS device or a III-N HEMT.
17. The method of claim 15, wherein the enhancement mode device comprises a Si MOS device, the Si MOS device includes an inherent parasitic diode, and the switching device further comprises a Schottky diode connected antiparallel to the Si MOS device.
18. A method of forming a power-factor correction circuit, comprising:
providing a first switching device comprising a first depletion mode transistor and a first enhancement mode transistor;
providing a second switching device comprising a second depletion mode transistor and a second enhancement mode transistor, wherein the first and second depletion mode transistors each comprise III-N HEMTs;
providing an inductive component;
connecting the inductive component, the first switching device and the second switching device to a first node, and connecting the second switching device and the capacitor to a second node; and
configuring the power-factor correction circuit such that in a first mode of operation current flows through a channel of the second depletion mode transistor in a first direction when a gate of the second enhancement mode transistor is biased below a threshold voltage of the second enhancement mode transistor, and in a second mode of operation current flows through the channel of the second depletion mode transistor in the first direction when the gate of the second enhancement mode transistor is biased above the threshold voltage of the second enhancement mode transistor.
19. The method of claim 18, wherein the first and second enhancement mode transistors each comprise Si MOS devices.
20. The method of claim 18, wherein the power-factor correction circuit is configured such that in a third mode of operation the second depletion mode transistor blocks voltage applied in a second direction across the second switching device.
21. The method of claim 20, wherein in the third mode of operation the second enhancement mode transistor blocks a voltage at least equal to an absolute value of a threshold voltage of the second depletion mode transistor.
22. The method of claim 20, wherein in the third mode of operation the gate of the second enhancement mode transistor is biased below the threshold voltage of the second enhancement mode transistor.
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