Source: https://patents.google.com/patent/US8644589B2/en
Timestamp: 2019-08-21 20:37:47
Document Index: 578940308

Matched Legal Cases: ['Application No. 60', 'Application No. 07', 'Application No. 07253652', 'Application No. 2002', 'Application No. 200708778', 'Application No. 096134260']

US8644589B2 - Method and apparatus for performing model-based OPC for pattern decomposed features - Google Patents
US8644589B2
US8644589B2 US13/786,249 US201313786249A US8644589B2 US 8644589 B2 US8644589 B2 US 8644589B2 US 201313786249 A US201313786249 A US 201313786249A US 8644589 B2 US8644589 B2 US 8644589B2
US13/786,249
US20130182940A1 (en
2007-09-13 Priority to US11/898,646 priority patent/US8111921B2/en
2012-01-25 Priority to US13/358,497 priority patent/US8391605B2/en
2013-03-05 Application filed by ASML MaskTools Netherlands BV filed Critical ASML MaskTools Netherlands BV
2013-03-05 Priority to US13/786,249 priority patent/US8644589B2/en
2013-03-18 Assigned to ASML MASKTOOLS B.V. reassignment ASML MASKTOOLS B.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, JANG FUNG, HSU, DUAN-FU STEPHEN, PARK, JUNG CHUL, VAN DEN BROEKE, DOUGLAS
2013-07-18 Publication of US20130182940A1 publication Critical patent/US20130182940A1/en
2014-02-04 Publication of US8644589B2 publication Critical patent/US8644589B2/en
This application is a continuation of U.S. application Ser. No. 13/358,497,filed Jan. 25, 2012, issued on Mar. 5, 2013 as U.S. Pat. No. 8,391,605, which is a continuation of U.S. application Ser. No. 11/898,646, filed Sep. 13, 2007, and issued on Feb. 7, 2012as U.S. Pat. No. 8,111,921, which claims priority from U.S. Provisional Application No. 60/844,074 , filed on Sep. 13, 2006, the contents of which are incorporated herein by reference in their entirety.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way, The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
However, while it possible to determine how to separate a target pattern into two separate masks, as explained further below, standard OPC treatments of the respective masks is often insufficient to obtain acceptable imaging performance. This is due, in part to the stronger proximity effects that occur when imaging features having increasingly smaller CDs, such as for example, in the 32 nm mode. Indeed, standard OPC treatments to the individual masks will often result in the final imaged pattern exhibiting broken contours or line breaks.
FIG. 12 is a block diagram that illustrates a computer system 100 which can assist in performing the process explained above. Computer system 100 includes a bus 102 or other communication mechanism for communicating infatuation, and a processor 104 coupled with bus 102 for processing information. Computer system 100 also includes a main memory 106, such as a random access memory (RAM) or other dynamic storage device, coupled to bus 102 for storing information and instructions to be executed by processor 104. Main memory 106 also may be used for storing temporary variables or other intermediate information during execution of instructions to be executed by processor 104. Computer system 100 further includes a read only memory (ROM) 108 or other static storage device coupled to bus 102 for storing static information and instructions for processor 104. A storage device 110, such as a magnetic disk or optical disk, is provided and coupled to bus 102 for storing information and instructions.
The term “computer-readable medium” as used herein refers to any medium that participates in providing instructions to processor 104 for execution. Such a medium may take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 110. Volatile media include dynamic memory, such as main memory 106, Transmission media include coaxial cables, copper wire and fiber optics, including the wires that comprise bus 102. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, DVD, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can read.
a projection system (“lens”) PL (e.g., a refractive, catoptric or catadioptric optical system) for imaging an irradiated portion of the mask MA onto a target portion C (e.g. comprising one or more dies) of the substrate W.
1. A computer-implemented method of performing optical proximity correction (OPC) of target circuit patterns that are decomposed into multiple sub-patterns, the multiple sub-patterns being configured to be imaged using a multiple patterning lithography process, the method comprising:
applying OPC parameters to each sub-pattern;
using feature geometries of the target circuit patterns and Boolean operations to extract overlap areas for each sub-pattern;
determining printing contour errors in the overlap areas with respect to intended target circuit patterns;
using Boolean operations to convert the determined printing contour errors into polygons that are added to the overlap areas, thereby generating modified sub-patterns; and
combining the modified sub-patterns to obtain an improved layout of the target circuit patterns.
2. The method of claim 1, wherein prior to combining the modified sub-patterns, applying a further round of OPC parameters to the modified sub-patterns.
verifying that the improved layout of the target circuit pattern produces an improved printing contour when imaged using a simulated model of the multiple patterning lithography process.
4. The method of claim 3, wherein the step of verifying comprises verifying that an average intensity modulation in the overlap areas is substantially flat.
5. The method of claim 1, wherein one or more steps of the method are repeated until the improved printing contour matches a desired printing contour.
6. The method of claim 5, wherein the OPC parameters and the further round of OPC parameters are dynamically updated.
7. The method of claim 1, wherein initial OPC parameters comprise reference OPC parameters associated with a baseline imaging performance.
8. The method of claim 7, wherein the OPC parameters include scatter bars as assist patterns that improve imaging performance.
9. The method of claim 1, wherein the target circuit patterns are decomposed using a coloring line (CLN) method.
10. The method of claim 1, wherein the target circuit patterns are decomposed using a coloring space (CSP) method.
11. The method of claim 1, wherein the target circuit patterns represent a full chip layout or a portion thereof.
12. A non-transitory computer-readable storage medium storing a computer program having computer-executable instructions for causing a computer to perform the steps of the method in claim 1.
US13/786,249 2006-09-13 2013-03-05 Method and apparatus for performing model-based OPC for pattern decomposed features Expired - Fee Related US8644589B2 (en)
US11/898,646 US8111921B2 (en) 2006-09-13 2007-09-13 Method and apparatus for performing model-based OPC for pattern decomposed features
US13/358,497 US8391605B2 (en) 2006-09-13 2012-01-25 Method and apparatus for performing model-based OPC for pattern decomposed features
US13/786,249 US8644589B2 (en) 2006-09-13 2013-03-05 Method and apparatus for performing model-based OPC for pattern decomposed features
US13/358,497 Continuation US8391605B2 (en) 2006-09-13 2012-01-25 Method and apparatus for performing model-based OPC for pattern decomposed features
US20130182940A1 US20130182940A1 (en) 2013-07-18
US8644589B2 true US8644589B2 (en) 2014-02-04
US11/898,646 Active 2030-12-07 US8111921B2 (en) 2006-09-13 2007-09-13 Method and apparatus for performing model-based OPC for pattern decomposed features
US13/358,497 Expired - Fee Related US8391605B2 (en) 2006-09-13 2012-01-25 Method and apparatus for performing model-based OPC for pattern decomposed features
US13/786,249 Expired - Fee Related US8644589B2 (en) 2006-09-13 2013-03-05 Method and apparatus for performing model-based OPC for pattern decomposed features
US20150131894A1 (en) * 2013-11-12 2015-05-14 Synopsys, Inc. Verification of circuit structures including sub-structure variants
JP2004079586A (en) 2002-08-09 2004-03-11 Toshiba Corp Aligner evaluation system, aligner evaluation method, aligner evaluation program, and manufacturing method of semiconductor device
US20050008952A1 (en) 2002-08-06 2005-01-13 Dulman H. Daniel Methods of forming patterned reticles
US20060008135A1 (en) 2004-07-09 2006-01-12 Shigeki Nojima Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method
JP2006106757A (en) 2004-10-05 2006-04-20 Samsung Electronics Co Ltd Mask for fabrication of semiconductor device and method of fabricating mask
US20060088772A1 (en) 2001-10-02 2006-04-27 Guobiao Zhang Pattern-Distributed Mask
JP2007279759A (en) 2000-07-10 2007-10-25 Mentor Graphics Corp Convergence technique for model-based optical proximity correction
Chang-Moon Lim et al., "Positive and Negative Tone Double Patterning Lithography for 50nm Flash Memory," Proc. of SPIE, vol. 6154, pp. 615410-1-615410-8 (2006).
European Office Action dated Oct. 16, 2012 in corresponding European Patent Application No. 07 253 652.7.
European Search Report dated Nov. 18, 2011 in corresponding European Patent Application No. 07253652.7.
Japanese Office Action dated Sep. 20, 2011 in corresponding Japanese Patent Application No. 2002-234053.
Jungchul Park et al., "Application Challenges with Double Patterning Technology (DPT) beyond 45 nm," Proc. of SPIE, vol. 6349, pp. 634922-1-634922-12 (2006).
JW Park et al., "Robust Double Exposure Flow for Memory," Proc. of SPIE, vol. 6154, pp. 61542E-1-61542E-10 (2006).
Martin Drapeau et al., "Double Patterning Design Split Implementation and Validation for the 32nm Node," Proc. of SPIE, vol. 6521, pp. 652109-1-652109-15 (2007).
Search Report issued May 15, 2008 in corresponding Singapore Patent Application No. 200708778-6.
Stephen Hsu et al., "65nm Full-chip Implementation Using Double Dipole Lithography," Proc. of SPIE, vol. 5040, pp. 215-231 (2003).
Taiwan Office Action dated Jan. 30, 2012 in corresponding Taiwan Patent Application No. 096134260.
US9886753B2 (en) * 2013-11-12 2018-02-06 Synopsys, Inc. Verification of circuit structures including sub-structure variants
KR100882260B1 (en) 2009-02-06
JP4383400B2 (en) 2009-12-16 Method of placing scattering bars based on the model in order to increase the focal depth of a quarter wavelength lithography, program product and apparatus
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSU, DUAN-FU STEPHEN;PARK, JUNG CHUL;VAN DEN BROEKE, DOUGLAS;AND OTHERS;REEL/FRAME:030027/0261