Source: http://www.google.com/patents/US7094060?ie=ISO-8859-1&dq=6233682
Timestamp: 2014-10-21 01:41:06
Document Index: 303564034

Matched Legal Cases: ['art 200', 'art 700', 'art 200', 'art 200', 'art 700', 'art 700', 'art 900', 'art 200', 'art 900', 'art 900']

Patent US7094060 - Via providing multiple electrically conductive paths - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit board formed by a plurality of substantially partially overlapping bores. An electrically conductive plating is formed on an inner surface of...http://www.google.com/patents/US7094060?utm_source=gb-gplus-sharePatent US7094060 - Via providing multiple electrically conductive pathsAdvanced Patent SearchPublication numberUS7094060 B2Publication typeGrantApplication numberUS 11/039,964Publication dateAug 22, 2006Filing dateJan 24, 2005Priority dateDec 12, 2002Fee statusPaidAlso published asUS6848912, US7168957, US7326061, US20040115992, US20050130480, US20060183354, US20070093082Publication number039964, 11039964, US 7094060 B2, US 7094060B2, US-B2-7094060, US7094060 B2, US7094060B2InventorsTonglong ZhangOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (6), Non-Patent Citations (2), Referenced by (10), Classifications (18), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetVia providing multiple electrically conductive pathsUS 7094060 B2Abstract A via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit board formed by a plurality of substantially partially overlapping bores. An electrically conductive plating is formed on an inner surface of the opening. The plating forms a plurality of distinct electrically conductive paths.
25. The via of claim 1, wherein each path of the electrically conductive paths corresponds to one of the substantially partially overlapping bores. Description
CROSS-REFERENCE TO RELATED APPLICATION(S) This application is a continuation of U.S. patent application Ser. No. 10/317,143, filed Dec. 12, 2002 now U.S. Pat. No. 6,848,912, which is incorporated herein by reference in its entirety.
SUMMARY OF THE INVENTION The present invention is directed to an apparatus and a method for providing a plurality of electrical connections between conductors on different layers of a circuit board.
BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES The accompanying drawings which are incorporated therein and form a part of the specification illustrate the present invention and together with the description further serves to explain the principles of the invention and to enable a person skilled in the art to make and use the invention.
FIGS. 4A�4D show views of example process steps for forming a via having two electrically conductive paths, according to an example embodiment of the present invention.
FIGS. 5A�5C show views of example process steps for forming a via having three electrically conductive paths, according to an example embodiment of the present invention.
Design and manufacturing techniques for circuit boards have progressed from one or two layered structures to multi-layer boards, where ten or more layers are not uncommon. Multi-layered circuit boards are formed from alternating layers of electrically conductive materials and electrically insulating materials. For example, the electrically insulating or dielectric materials may be organic, plastic, ceramic, and tape material, among other material. Such substrates may include materials such as polyimide, �BT�, which includes a resin called bis-maleimide triazine, �FR-4,� which is a fire-retardant epoxy resin-glass cloth laminate material, �FR-5,� and/or other similar materials.
�Through� vias and �blind� vias exist. �Through� vias extend through all layers of a circuit board. Blind vias extend through a portion of the layers of the circuit board, including extending between an external surface and an internal conductive layer, or between two internal conductive layers of the circuit board.
Note that as used herein, the term �substantially partially overlapping bores� refers to multiple types of bores. �Substantially partially overlapping bores� includes bores that (i) partially overlap each other, (ii) bores that are closely adjacent to each other, and (iii) combinations of partially overlapping and closely adjacent bores. Bores that are closely adjacent to each other include those that have openings that are close to each other, but are not overlapping. For example, in an embodiment, closely adjacent bores include bores that are formed more closely together than is normally practiced and/or allowable using typical via design techniques. In another embodiment, closely adjacent bores may include, but are not limited to, those bores formed so closely adjacent that their respective via pads and/or inner surface platings overlap or come into contact to form a �short circuit.� Thus, closely adjacent bores may include bores formed so closely adjacent such that conventional plating processes would tend to connect the bores with plating to cause the closely adjacent bores to become electrically coupled. Examples of some of partially overlapping and closely adjacent of bores are further described below. Furthermore, the vias of the present invention may be either �through� vias or �blind� vias, and may include bores formed according to standard and/or micro-via processes.
As stated above, the plurality of substantially partially overlapping bores formed in step 202 includes bores that partially overlap and/or bores that are closely adjacent. Examples of these types of bores are provided as follows. For example, FIG. 3A shows a first bore 302 a and a second bore 302 b that are partially overlapping. An overlapping portion is indicated in FIG. 3A as intersecting portion 380. First and second bores 302 a and 302 b each have a respective inner surfaces 304 a and 304 b. The combination of inner surfaces 304 a and 304 b create an inner surface for the opening through the circuit board formed by first and second bores 302 a and 302 b. FIG. 3B shows an example of first bore 302 a and second bore 302 b that are not overlapping, and are instead closely adjacent. As shown in FIG. 3B, first and second bores 302 a and 302 b have corresponding via pads 306 a and 306 b. As shown in FIG. 3B, corresponding via pads 306 a and 306 b are in contact, forming a �short circuit� or electrical connection. An intersecting portion of via pads 306 a and 306 b is indicated in FIG. 3B as intersecting portion 390.
FIG. 3C shows another example of first and second bores 302 a and 302 b that are closely adjacent. As shown in FIG. 3C, inner surfaces 304 a and 304 b of first and second bores 302 a and 302 b are plated with a first plating 308 a and a second plating 308 b, respectively. First and second bores 302 a and 302 b may be considered closely adjacent when they are close enough such that an excess plating material 310 a and/or 310 b extends sufficiently out of bores 302 a and 302 b onto the surface of the circuit board to come into contact to form a �short circuit� or electrical connection. Such contact between platings may be caused by the intentional application of excess plating material, or may occur due to inaccuracies inherent in the particular plating process used. The intersecting portion of plating material 310 a and/or 310 b is indicated in FIG. 3C as intersecting portion 370. Thus, as shown in FIGS. 3B and 3C, bores may be considered closely adjacent when their respective die pads and/or excess plating material come into contact.
As described above, a plurality of distinct electrically conductive paths are created in the via of the present invention. Furthermore, the electrical paths may be formed between conductors of any two or more layers of the circuit board. For example, FIG. 3D shows a cross-sectional view of a via 300 formed in a circuit board 350, according to an example embodiment of the present invention. Via 300 has multiple example conductive paths 320 created therein according to the present invention. As shown in the example of FIG. 3D, a first electrically conductive path 320 a and a second electrically conductive path 320 b are present in via 300. Circuit board 350 may have two or more layers 352 in which conductors 360 may be present, that are separated by dielectric or electrically insulating layers 354. In the example of FIG. 3D, circuit board 350 has a first conductive layer 352 a, a second conductive layer 352 b, a third conductive layer 352 c, and a fourth conductive layer 352 d. First, second, third, and fourth conductive layers 352 a�d are separated by dielectric or electrically insulating layers 354 a�c. As shown in FIG. 3D, first electrically conductive path 320 a electrically couples a conductor 360 a in second conductive layer 352 b to a conductor 360 b in fourth conductive layer 352 d. Second electrically conductive path 320 b electrically couples a conductor 360 c in second conductive layer 352 b to a conductor 360 d in third conductive layer 352 c. Note that although FIG. 3D shows pairs of conductors 360 that are electrically coupled by conductive paths 320, additional conductors may also coupled together, including three conductors, and greater numbers of conductors, by electrically conductive paths of the present invention.
Furthermore, flowchart 200 may include the step where the opening may be filled with a material or left unfilled. For example, the opening may be filled with an electrically conductive or non-conductive material. The opening may be filled prior to step 206, or after step 206. If the opening is filled prior to step 206, then the formation of an additional bore can be used to separate the electrically conductive, dielectric, or other material filling the opening into separate portions by removing a portion of the material. Hence, if the material is electrically conductive, the additional bore separates the material into electrically isolated portions. An electrically non-conductive material, such as a solder resist or solder mask material may alternatively be used, for example. After the opening is filled, the top and/or bottom surface of the filled opening may be plated (e.g., a �via-in-pad� as may be referred to in the art). For example, by filling the opening, and plating a surface of the opening, a solder ball or other object may be better attached to the resulting via. The plating formed on the top and/or bottom surface of the opening may be separated by the additional bore(s) or by another process, such as an etching process.
Partially Overlapping Bore Embodiments Via embodiments using partially overlapping bores are described in this section. For illustrative purposes, the present invention is described in terms of two, three, and four partially overlapping bores. However, it is to be understood that any number of two or more partially overlapping bores may be used to form a via of the present invention, including numbers of bores greater than four.
In step 204 described above, and shown in FIG. 2, an inner surface of the opening is plated with an electrically conductive material. FIG. 4A shows a top view of opening 330 after a plating 402 has been formed on inner surface 450 of opening 330. A first intersecting plating portion 404 a and a second intersecting plating portion 404 b of plating 402 are shown in FIG. 4A. First and second intersecting plating portions 404 a and 404 b are portions of plating 402 that are present at intersecting portions of first and second bores 302 a and 302 b. FIG. 4B shows a top view of opening 330, with an outline of an additional bore 410 that can be formed in the circuit board. As shown in FIG. 4B, the outline of additional bore 410 overlaps first and second intersecting portions 404 a and 404 b. In step 206 described above, and shown in FIG. 2, the plating is removed from intersecting portions of the plurality of substantially overlapping bores, to form a plurality of distinct electrically conductive paths. FIG. 4C shows a top view of a via 300, according to an example embodiment of the present invention. FIG. 4D shows a cross-sectional view of via 300. Via 300 has an opening 420, and distinct first and second electrically conductive paths 320 a and 320 b between conductive layers of the circuit board. First and second electrically conductive paths 320 a and 320 b are formed in plating 402 by additional bore 410, which removed portions of plating 402 from intersecting portions of the overlapping bores, including the removal of intersecting portions 404 a and 404 b. Note that additional bore(s) 410 may or may not remove lesser or additional portion(s) of the circuit board and plating 402 than shown in FIG. 4C. By removing intersecting portions of plating 402, first and second electrically conductive paths 320 a and 320 b are distinct within via 300.
FIG. 5B shows a single additional bore 410 positioned to remove plating from the three bore embodiment shown in FIG. 5A. FIG. 5C shows a top view of a via 300 resulting from application of the single additional bore 410 shown in FIG. 5B, according to an example embodiment of the present invention. FIG. 5C shows plating 402 having been removed from intersecting portions 404 a�c of first, second, and third bores 302 a, 302 b, 302 c to form first, second, and third distinct electrically conductive paths 320 a, 320 b, and 320 c, according to step 206 shown in FIG. 2. First, second, and third electrically conductive paths 320 a, 320 b, 320 c are formed in plating 402 by additional bore 410, which removed portions of plating 402, including intersecting portions 404 a�c. By removing intersecting portions of plating 402, first, second, and third electrically conductive paths 320 a, 320 b, 320 c are distinct within via 300.
FIG. 5D illustrates an alternative embodiment where multiple additional bores are used to separate plating 402 shown in FIG. 5A. For example, as shown in FIG. 5D, first, second, and third additional bores 410 a�c may be used to remove intersecting portions 404 a�c, respectively, instead of using a single additional bore, as shown in FIG. 5B. Other numbers of additional bores may also be used in alternative embodiments to remove plating 402.
FIG. 6A shows a top view of opening 330, formed according to step 202 shown in FIG. 2, having four substantially partially overlapping bores: first bore 302 a, second bore 302 b, third bore 302 c, and fourth bore 302 d. First, second, third, and fourth bores 302 a�d collectively form opening 330 in the circuit board. First, second, third, and fourth bores 302 a�d each have an inner surface that collectively form inner surface 450 of opening 330. As shown in FIG. 6A, inner surface 450 has been plated with plating 402, according to step 204 of FIG. 2.
FIG. 6B shows a single additional bore 410 positioned to remove plating from the four bore embodiment shown in FIG. 6A. FIG. 6E shows a top view of a via 300 resulting from application of the single additional bore 410 shown in FIG. 6B, according to an example embodiment of the present invention. FIG. 6E shows plating 402 having been removed from intersecting portions 404 a�d of first, second, third, and fourth bores 302 a�d to form first, second, third, and fourth distinct electrically conductive paths 320 a�d, according to step 206 shown in FIG. 2. First, second, third, and fourth electrically conductive paths 320 a�d are formed in plating 402 by additional bore 410, which removed portions of plating 402, including intersecting portions 404 a�d. By removing intersecting portions of plating 402, first, second, third, and fourth electrically conductive paths 320 a�d are distinct within via 300.
Note that alternative combinations of additional bores, and different sized additional bores, may be used to remove plating in embodiments of the present invention. For example, FIG. 6C shows a relatively larger first additional bore 410 a positioned to remove plating from intersecting portions 404 c and 404 d of plating 402. FIG. 6D. Thus, after application of first additional bore 410 a in FIG. 6C, plating 402 is separated into two portions, first and second plating portions 602 a and 602 b. First and second plating portions 602 a and 602 b may be used as electrically conductive paths in an embodiment, if desired. Furthermore, FIG. 6D shows second and third additional bores 410 b and 410 c positioned to remove plating from intersecting portions 404 a and 404 b. Hence, the combination of first, second, and third additional bores 410 a�c shown in FIG. 6D may be used to create first, second, third, and fourth electrically conductive paths 320 a�d, as shown in FIG. 6E. Alternatively, for example, two or four additional bores (not shown) may be used in step 206 to remove intersecting portions 404 a�d of plating 402 shown in FIG. 6A. Other numbers of additional bores may also be used in embodiments to remove plating 402.
FIG. 7 shows an example flowchart 700, similar to flowchart 200 shown in FIG. 2, according to an example embodiment of the present invention. Flowchart 200 is directed to forming a via using partially overlapping bores. Examples of such vias are shown in FIGS. 3A, 4A�4E, 5A�5D, and 6A�6E. Other operational and structural embodiments will be apparent to persons skilled in the relevant art(s) based on the following discussion. The steps of flowchart 700 are described in detail below.
Flowchart 700 begins with step 702. In step 702, a plurality of partially overlapping bores are formed through the circuit board to create an opening. For example, the plurality of closely adjacent bores are closely adjacent bores 302, which create opening 330, as described above with respect to FIGS. 3A, 4A�4E, 5A�5D, and 6A�6E.
In step 704, an inner surface of the opening is plated with an electrically conductive material. For example, inner surface 450 of opening 330 may be plated with a plating 402, as described above with respect to FIGS. 3A, 4A�4E, 5A�5D, and 6A�6E.
In step 706, the plating is removed from intersecting portions of the plurality of overlapping bores to form a plurality of distinct electrically conductive paths. For example, plating 402 may be removed from intersecting portions 404 by one or more additional bores 410 to form distinct electrically conductive paths 320, as described above with respect to FIGS. 3A, 4A�4E, 5A�5D, and 6A�6E.
FIG. 9 shows an example flowchart 900, similar to flowchart 200 shown in FIG. 2, according to an example embodiment of the present invention. Flowchart 900 is directed towards forming a via using closely adjacent bores, such as is shown in FIGS. 3B and 8A�8C. Other operational and structural embodiments will be apparent to persons skilled in the relevant art(s) based on the following discussion. The steps of flowchart 900 are described in detail below.
Note that the embodiments described herein may be combined in any manner. For example, FIG. 10 shows an embodiment of the present invention where partially overlapping and closely adjacent bores 302 are formed in the circuit board, according to step 202 shown in FIG. 2. As shown in FIG. 10, first, second, and third bores 302 a�c are formed in a circuit board, each having a respective via pad 306 a�c. First and second bores 302 a and 302 b are partially overlapping bores. Third bore 302 c is closely adjacent to first and second bores 302 a and 302 b. First and second bores 302 a and 302 b have a plating 402 a formed on their inner surface, and third bore 302 c has a plating 402 b formed on its inner surface.
FIG. 10 further shows example first and second additional bores 410 a and 410 b that may be applied during step 206 to removing intersecting portions of bores 302 a�c. For example, first additional bore 410 a removes intersecting portion 404 a, which includes portions of plating 402 a and via pads 302 a and 302 b. Second additional bore 410 b removes a portion of plating 402 and contacting portions of via pads 306 a�c (indicated generally as intersecting portion 404 b). Hence, three distinct electrically conductive paths may be formed by the configuration shown in FIG. 10. Note that other numbers of additional bores 410 may alternatively be used to remove plating.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6613986Sep 8, 1999Sep 2, 2003Ibiden Co., Ltd.Multilayer build-up wiring boardUS6651322Dec 28, 2000Nov 25, 2003Unisys CorporationMethod of reworking a multilayer printed circuit board assemblyUS6879234 *Jan 28, 2003Apr 12, 2005Nec Electronics CorporationSemiconductor integrated circuitUS20020076903 *Dec 10, 2001Jun 20, 2002Koji KondoManufacturing method of multilayer substrate and multilayer substrate produced by the manufacturing methodUS20030102151Dec 31, 2002Jun 5, 2003Naohiro HiroseMultilayer build-up wiring boardUS20030235115 *Jan 8, 2001Dec 25, 2003Raymond PorzioActive housing broadband tonpilz transducer* Cited by examinerNon-Patent CitationsReference1Geoff Smithson, "Practical RF Printed Circuit Board Design," presented at the Institution of Electrical Engineers (IEE) Training Event "How to Circuits," (location unknown) Apr. 5, 2000, 6 pages.2 *IBM, Test Probe Contact Grid Translator Board, Jan. 1979, IBM Technical Disclose Bulletin, vol. 21, All.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7326061 *Dec 14, 2006Feb 5, 2008Broadcom CorporationVia providing multiple electrically conductive pathsUS7566591Oct 31, 2005Jul 28, 2009Broadcom CorporationMethod and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface featuresUS7582951Oct 20, 2005Sep 1, 2009Broadcom CorporationMethods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packagesUS7714453Jan 11, 2007May 11, 2010Broadcom CorporationInterconnect structure and formation for package stacking of molded plastic area array packageUS7719110Sep 18, 2007May 18, 2010Broadcom CorporationFlip chip package including a non-planar heat spreader and method of making the sameUS7781266Aug 4, 2009Aug 24, 2010Broadcom CorporationMethods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packagesUS7808087Sep 27, 2006Oct 5, 2010Broadcom CorporationLeadframe IC packages having top and bottom integrated heat spreadersUS8169067Oct 20, 2006May 1, 2012Broadcom CorporationLow profile ball grid array (BGA) package with exposed die and method of making sameUS8183687Feb 16, 2007May 22, 2012Broadcom CorporationInterposer for die stacking in semiconductor packages and the method of making the sameUS8581381Oct 30, 2006Nov 12, 2013Broadcom CorporationIntegrated circuit (IC) package stacking and IC packages formed by same* Cited by examinerClassifications U.S. Classification439/55International ClassificationH05K3/00, H05K3/42, H01R12/00, H05K3/40Cooperative ClassificationH01R12/523, H05K3/42, H05K2201/09645, H05K2201/09181, H05K3/429, H05K1/115, H05K2203/1476, H05K3/0047, H05K2201/09854, H05K3/403European ClassificationH01R9/09F3, H05K1/11D, H05K3/40CLegal EventsDateCodeEventDescriptionFeb 24, 2014FPAYFee paymentYear of fee payment: 8Feb 19, 2010FPAYFee paymentYear of fee payment: 4Jan 24, 2005ASAssignmentOwner name: BROADCOM CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ZHANG, TONGLONG;REEL/FRAME:016212/0591Effective date: 20021209RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google