Source: http://www.google.de/patents/US7441162
Timestamp: 2013-05-22 21:53:17
Document Index: 309636290

Matched Legal Cases: ['art 1', 'Application No. 06023616', 'Application No. 06023617', 'Application No. 06023620', 'Application No. 06023621', 'Application No. 06023629', 'Application No. 06023630', 'Application No. 06023631', 'Application No. 06023632', 'Application No. 06023633', 'Application No. 06023634', 'Application No. 8']

Patent US7441162 - Coding apparatus and decoding apparatus for transmission/storage of ... - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr » Erweiterte Patentsuche | Webprotokoll | Anmelden Erweiterte Patentsuche PatenteAn output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality...http://www.google.de/patents/US7441162?utm_source=gb-gplus-sharePatent US7441162 - Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code Ver�ffentlichungsnummerUS7441162 B2PublikationstypErteilung Anmeldenummer11/418,106 Ver�ffentlichungsdatum21. Okt. 2008Eingetragen5. Mai 2006 Priorit�tsdatum29. Sept. 1995Auch ver�ffentlicht unterUS6493838US7051248US7093170US7441161US7457994US7469364US7506221US20030046634US20030066007US20030066008US20060195763US20060195764US20060200725US20060206785US20060206786US20060206787US20060206788US20060218462US20060218463US20060218473 ErfinderYoshihiro KikuchiToshiaki WatanabeKenshi DachikuTakeshi ChujohTakeshi NagaiUrspr�nglich Bevollm�chtigterKabushiki Kaisha Toshiba US-Klassifikation714/701Internationale KlassifikationH04N7/64G11B27/30H04J3/06H04N7/56H04L1/00H04L7/04H04N7/66H04N7/50G11B20/18H03M13/05 UnternehmensklassifikationH04J3/0602H04J3/07H04L7/048H04L2001/0098G11B20/1813H04L1/0072H03M13/27H04L1/0041H04L1/0046H04N7/66H04N7/56H04N21/4382H04N7/5073H04J3/0605H04N7/64H03M13/33G11B27/3027H03M13/356H04N21/2383H04L1/0083H04L1/004H04N7/50H04L7/041 Europ�ische KlassifikationG11B 27/30CH04L 1/00B3H04L 7/04BH04J 3/06A1H04N 7/56H04N 7/66H04N 7/50H04L 1/00F2H03M 13/27H04N 7/64H04L 1/00BH04L 1/00B5BH04J 3/06AH04J 3/07H04L 7/04CH04N 7/50MH04L 1/00B8H04N 21/2383H04N 21/438MH03M 13/33ReferenzenPatentzitate (47)Nichtpatentzitate (16)Externe LinksUSPTO USPTO-Zuordnung EspacenetCoding apparatus and decoding apparatus for transmission/storage of information using synchronization codeUS 7441162 B2 Zusammenfassung An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.
bitstream assembling means for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at desired positions of the bitstream, the check bits being arranged immediately before the synchronization code insertion positions and the stuffing code having a number of bits necessary to shift the position of the check bits.
2. The coding apparatus as set forth in claim 1, wherein the plurality of synchronization code insertion positions are arranged at a constant interval therebetween.
3. The coding apparatus as set forth in claim 1, wherein the plurality of synchronization code insertion positions are periodically arranged. Beschreibung
To realize the above-mentioned hierarchical coding, it is necessary to switch the error correction and/or detection codes of different error correction and/or detection capabilities midway in the outputted bitstream. As the method of switching the error correction and/or detection codings of different error correction and/or detection capabilities, there exists such a method that header information indicative of the sort of the error correction and/or detection code is added to the bitstream. FIG. 1 shows an example of a bitstream in which the error correction and/or detection codes are switched by adding header information. In more detail, in this example, two sorts of the error correction and/or detection codes FETC1 and FEC2 are switched. In each of the headers 1101 to 1104, header information indicative of the sort of the error correction and/or detection code and a number of code word is inserted. Therefore, the coding apparatus arranges the code word coded for error correction and/or detection after each header information, and the decoding apparatus decodes the header information; and the decoding apparatus decodes the header information and after that the error, correction and/or detection code in accordance with the decoded header information.
In the first aspect of the present invention, since the synchronization code is arranged at each of a plurality of predetermined synchronization code insertion positions in the output bitstream and further since the check bits of the error correction and/or detection code are arranged at positions other than the synchronization code, insertion positions, even if the bit pattern the same as that of the synchronization code is included in the check bits, there exists no possibility that the synchronization code is detected erroneously. Therefore, it is unnecessary to use a specific error correction and/or detection code to prevent a specific bit pattern form being formed or to insert bits to protect the synchronization pattern after having been coded to the error correction and/or detection code. As a result, it is possible to increase not only the degree of freedom of selection of the usable error correction and/or detection codes but also to improve the resistance against error, because there exists no possibility that the new erroneous synchronization detection occurs due to mixture of the erroneous insertion bit.
Further, the second aspect of the present invention provides a coding apparatus, comprising: bitstream converting means for converting an inputted bitstream other then a synchronization code arranged at each of a plurality of synchronization code insertion positions previously determined in an outputted bitstream, in such a way that a Hamming distance from the synchronization code exceeds a predetermined value; coding means for coding the bitstream converted by said bitstream converting means to an error correction and/or detection code composed of information bits and check bits; and bitstream assembling means for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of the synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream.
Further, the third aspect of the present invention provides a coding apparatus, comprising: coding means for coding an inputted bitstream to an error correction and/or detection code; synchronization code inserting means for inserting synchronization codes into the inputted bitstream; deciding means for deciding the number of information bits to be coded to the error correction an d/or detection code and arranged immediately before the synchronization code of the bitstream; and said coding means forming the error correction and/or detection code arranged immediately before the synchronization code as a degenerative code adaptively degenerated on the basis of the number of bits decided by said deciding means.
Further, the third aspect of the present invention provides a decoding apparatus, comprising: decoding means for decoding a bitstream coded to an error correction and/or detection code and further including inserted synchronization codes; synchronization code detecting means for detecting the synchronization codes arranged in the bitstream; deciding means for deciding the number of information bits coded to the error correction and/or detection code and arranged immediately before the synchronization code detected by said synchronization code detecting means; and said decoding means decoding the bitstream by deciding whether the error correction and/or, detection code arranged immediately before the synchronization code is a degenerative code or not on the basis of the number of the information bits decided by said deciding means.
In FIG. 2, moving picture signals 131 to be coded are inputted in unit of frame. The inputted moving picture signals 131 are processed for motion compensation adaptive prediction in unit of small region (e.g., macro block). In more detail, a motion vector between inputted moving picture signals 131 and video signals already coded and locally decoded and further stored in a frame memory is detected by a motion compensation adaptive predictor 101. Further, predicted signals 132 are formed by compensation prediction on the basis of the detected motion vector. In this motion compensation predictor 101, a preferable prediction mode to be used for coding is selected from both the motion compensation prediction coding and the intra-frame coding (the inputted moving picture signal 131 is coded as it is without forming any prediction signal) and the prediction signals corresponding to the selected mode, are outputted.
The outputted prediction signals are inputted to a subtracter 103, and prediction residual signals 133 obtained by subtracting the prediction signals 132 from the inputted moving picture signals 131 are outputted. The outputted prediction residual signals 133 are discrete-cosine transformed (DCTed) in unit of constant size block by a discrete cosine transform section 104, so that DCT coefficients can be formed. The formed DCT coefficients are quantized by a quantizer 105. The DCT coefficient signals quantized by the quantizer 105 are branched into two. One is variable-length coded by a first variable length coder 106. Further, the other is dequantized by a dequantizer 107, and further reversely discrete-cosine transformed by a inverse discrete cosine transform section 108. The output of the inverse discrete cosine transform section 108 is added to a prediction signal 132 by an adder 109 to form local decoded signals. The formed local, decoded signals are stored in a frame memory 102.
From the multiplexer 111, a bitstream 201 of the multiplexed variable length codes, an FEC, sort ID (identification) signal 202 indicative of a sort of the corresponding error correction and/or detection code, and a synchronization code insertion request signal 203 for requesting an insertion of a synchronization code is outputted.
FIG. 3 shows a flow of signals multiplexed by the multiplexer 111. Here, the multiplexing is executed in unit frame to be coded. First, the picture synchronization code 301 is multiplexed. When the picture synchronization code 301 is multiplexed, the synchronization code insertion request signal 203 is outputted from the multiplexer 111 to the coding apparatus 200, so that the coding apparatus 200 can know that the multiplexed code word is a synchronization code. Successively, a picture header 302 indicative of one of various coding modes of the coded frame is multiplexed upon the bitstream 201. Further, prediction mode information 303 indicative of the prediction mode of the motion compensation adaptive predictor MC at each region is multiplexed. Further, motion vector information 304 and the DCT coefficients (referred to as residual DCT coefficients) 305 of the prediction residual signals are multiplexed. Here; when the picture header 302, the prediction mode information 303, the motion vector information 304, and the residual DCT coefficients 305 are multiplexed, the FEC sort ID signal 202 indicative of the sort of the error correction and/or detection code is outputted in correspondence to each of the multiplexed signals.
FIG. 4 is a block diagram showing the output coding apparatus-200 shown in FIG. 2. The output coding apparatus 200 is composed of a bit inserter 211, an error correction and/or detection switching coder 212, and a bitstream assembler 213. Further, FIG. 5 shows an example of the output bitstream 205 formed by the output coding apparatus 200. The bitstream 205 is composed of a picture synchronization code PSC, a picture header PH, prediction mode information MODE, motion vectors MV, error correction and/or detection code check bits CHK, residual DCT coefficients COEF, and stuffing (insertion) bits STUFF. The output bitstream 205 has the following features:
(2) The error correction and/or detection code arranged at the last portion of one frame (i.e., at the last portion of one synchronization period sandwiched between the two synchronization codes PSC) is a punctured code such that only the finally remaining information bits are coded. Further, in order to shift the position of the check bit CHK (e.g., the check bit CHK6 in the example shown in FIG. 5) a necessary number of the stuffing bites STUFF are inserted.
Here, as shown in FIG. 5, since the synchronization code 301 (PSC) can be inserted at only the synchronization code insertion positions arranged at sync_period intervals of the output bitstream 205, when the last position of the output bitstream 205 already formed is not arranged at the synchronization code insertion position, the stuffing bits STUFF (as described later) are inserted in such a way that the synchronization code 301 can be arranged at the synchronization-code insertion position.
After the synchronization code 301 has been outputted to the output bitstream 205, the picture header 302, the prediction mode information 303, the motion vector information 304, and the residual DCT coefficients 305 are coded as follows: First, bits are inserted into the bitstream 201 outputted by the multiplexer 111 by the bit inserter 211 in order to prevent the generation of the pseudo-synchronization. In other words, when a bit pattern the same as that of the code word of the synchronization code 301 exists in the output bitstream 205, since, the synchronization code 301 cannot be decoded unequivocally, bits are inserted according to the necessity. For is instance, if the synchronization code 301 is a code word in which the sync_0_len bits of �0� are arranged continuously as shown in FIG. 6, it is possible to prevent the pseudo-synchronization by inserting �1� in such a way that �0� will not be continued beyond the sync_0_len bits in the bitstream, except at the synchronization code 301.
Here, if no is less than (2*N+1), {(2*n+1)−n0} bits of �1� are inserted into the bitstream 201.
The error correction and/or detection coder 604 codes the bitstream 222 supplied by the bit inserter 211 for error correction and/or detection in accordance with the latched signal 623; that is, forms and outputs the information bits 631 and check bits 632, respectively. Further, after the error correction and/or detection coding for one block has been completed, the error correction and/or detection coder 604 outputs a latch command signal 625 for commanding the latch circuit 603 to latch the succeeding FEC sort ID signal 202. Therefore, on the basis of this latch command signal 625, the latch circuit 603 latches the succeeding FEC sort ID signal 202 and supplies the latched signal to the error correction and/or detection coder 664 again.
By repeating the above-mentioned operation, the output coding apparatus 200 codes the bitstream 222 (to which bits have been already inserted by the bit inserter 211) for error correction and/or detection, by switching the error correction and/or detection codes by the error correction and/or detection switching coder 212 in accordance with the FEC sort ID signal 202 supplied by the multiplexer 111. Here, since the FEC sort ID signal 202 can be latched by the latch circuit 603 only when the error correction and/or detection coding of one block has been completed, the same error correction and/or detection code is kept applied until the FEC sort ID signal 202 is switched. For instance, in the case where the error correction and/or detection code of FEC1 is used for the picture header 302 and the code of FEC2 is used for the prediction mode information 303, if the number of bits of the picture header 302 is shorter than that of the one-blocs information of FEC1, the FEC1 code is kept used for the error correction and/or detection code of the succeeding prediction mode information 303 until reaching the bit number of FEC1 information.
As already explained, the check bits of the error correction and/or detection code are shifted in position so as to be formed between the information bits of the error correction and/or detection code arranged backward in the bitstream 205. Therefore, the controller 1001 controls the switch 1002 in such a way that these position-shifted check bits can be separated from the information bits. After the information bits of the one-block error correction and/or detection code have been inputted, the count value 1023 matches the information bit length 1024 in the comparator 1006. In response to this match signal, the controller 1001 receives the check bit length 1025 from the error correction end/or detection information output circuit 1007 to calculate the check bit position inserted between the information bits. Here, when the count value 911 indicative of the number of inputted bits of the bitstream 205′ (obtained when the comparator 1006 outputs the match signal) is denoted by bit_count; and the check bit length is denoted by check_len, the check bit start position check_start is
check_start=(bit_count/sync_period+1)*sync_period−check_len.
Further, since the error correction and/or detection coding is executed by the degenerative code at the last of one frame, a special processing is necessary. At the last of one frame, the synchronization detector 901 outputs a signal 803 indicative of that the synchronization code of the succeeding frame has been detected. In response to this signal, the controller 1001 calculates the position of the last error correction and/or detection check bit in the frame and the number of insufficient information bits. Here, the assumption is made that the count-value 911 of the number of bits of the bitstream 205′ inputted when the last error correction and/or detection code of one frame is started to be inputted is denoted by pre_last_count; the count value 911 at a time when the one-frame bitstream 205′ has been inputted is denoted by total_count; the count value 911 at the processing is denoted by bit_count; the check bit length of the last error correction and/or detection code of one frame is denoted by last_check_len; and the check bit length of the second-last error correction and/or detection code is denoted by pre_last_check_len. First, since the error correction code is a punctured code and further the bit is inserted, the overs and shorts of the information bits are calculated. Here, the number of information bits last_info_len of the last error correction and/or detection code of one frame included in the output bitstream 205 is
For instance, when the synchronization code word is that as shown in FIG. 6 and further when the bits are inserted by the bit inserter 211 at �0000.� portion of the first sync_len bits in such a way that the Hamming distance from the synchronization code is more than (2*n+1), the number (=n0) of �1� in {sync_0_len−(2*n+1)} bits beginning from the synchronization code insertion position is counted, when n0 is less than 2*n+1, bits of (2*n+1−n0) are removed. Here, however, since the insertion bits are determined as �1�, when the bit decided by the insertion bit remover 905 as the insertion bit is �0�, this is regarded as that an error is mixed in the synchronization code insertion block. In this case, therefore, the error detection signal 804 is outputted.
As described above, the bitstream 801 decoded, by the input decoding apparatus 800 is reverse multiplexed by the reverse multiplexer 811. In this operation, the code word multiplexed as shown, in FIG. 3 is separated and then outputted. Further, this reverse multiplexer 811 operates in linkage with the first and second variable length decoders 806 and 810, respectively.
When having decoded all the prediction mode information (the motion compensation adaptive prediction information code 842), the second variable length decoder 810 outputs an end signal to the reverse multiplexer 811. In response to this end signal, the reverse multiplexer 811 outputs the FEC sort ID signal indicative of the sort of the error correction and/or detection code corresponding to the motion vector information 304, and starts the reverse multiplex processing of the motion vector information 304. The reverse multiplexed motion vector information is outputted to the second variable length decoder 810 for decoding. After having decoded all the motion vector information, the second variable length decoder 810 outputs an end signal to the reverse multiplexer 811. In response to this end signal, the reverse-multiplexer 811 outputs the FEC sort ID signal indicative of the sort of the error correction and/or detection code corresponding to the residual DCT coefficient 305, reversely multiplexes the residual DCT coefficients 305, and outputs the reversely multiplexed results to the first variable length decoder 806. The first variable length decoder 806 decodes the residual DCT coefficients 305.
Further, when the bits are inserted into the bitstream arranged at the synchronization code insertion position in such a way as not to form the pseudo-sychronization, it is possible to eliminate such a prior art difficulty that the code word must be constructed in such a way that the bit pattern the same as that of the synchronization bits will not be formed.
In addition, in the present invention, since the bits are inserted under consideration of erroneous synchronization code; that is, since the bit train arranged at the synchronization code insertion position is converted in such a way that the Hamming distance from the synchronization code exceeds a predetermined value and further reversely converted by the decoding apparatus, the bit pattern the same as that of the synchronization code will not be included in the bit train, so that it is possible to secure that an erroneous detection of the synchronization code can be prevented as far as the number of bits is less than a predetermined value. As a result, the possibility of the erroneous detection of the synchronization code can be reduced. Further, when the above-mentioned conversion is executed, even if an error is mixed with the bitstream, since it is possible to discriminate the synchronization code from the bitstream other than the synchronization code, it is, possible to reduced the possibility that the synchronization code is detected erroneously.
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