Source: https://patents.google.com/patent/CN103928517B/en
Timestamp: 2019-12-06 08:46:29
Document Index: 655525641

Matched Legal Cases: ['art 720', 'art 720', 'art 720', 'art 720', 'art 720', 'art 720', 'art 720', 'art.\n13']

CN103928517B - FinFET and its manufacture method - Google Patents
FinFET and its manufacture method Download PDF
CN103928517B
CN103928517B CN201310428910.5A CN201310428910A CN103928517B CN 103928517 B CN103928517 B CN 103928517B CN 201310428910 A CN201310428910 A CN 201310428910A CN 103928517 B CN103928517 B CN 103928517B
CN201310428910.5A
CN103928517A (en
2013-03-15 Priority to US61/799,468 priority
2013-05-24 Priority to US13/902,322 priority
2013-09-18 Application filed by 台湾积体电路制造股份有限公司 filed Critical 台湾积体电路制造股份有限公司
2014-07-16 Publication of CN103928517A publication Critical patent/CN103928517A/en
2017-08-08 Publication of CN103928517B publication Critical patent/CN103928517B/en
The invention provides FinFET and its manufacture method.The semiconductor devices includes substrate, and the substrate has area of isolation, area of grid, by the separated source electrode of area of grid and drain region, the first fin structure in area of grid.First fin structure include the bottom as first fin structure the first semiconductor material layer, as first fin structure middle part exterior portion semiconductor oxide nitride layer, as first fin structure middle part core the first semiconductor material layer and second semiconductor material layer on top as first fin structure.Semiconductor devices also includes the source/drain part above the substrate in the regions and source/drain between two neighbouring area of isolation and the high k in area of grid（HK）/ metal gates（MG）Stack, the HK/MG stacks are covered in the top of a part for the first fin structure.
FinFET and its manufacture method
This patent is entitled " the Semiconductor Device And submitted on January 14th, 2013 The continuous case in part of Fabricating The Same " United States serial the 13/740th, 373, work is incorporated herein by the case For reference.This patent requires the rights and interests for the United States serial the 61/799th, 468 submitted on March 15th, 2013, by this application It is incorporated herein by reference.
The present invention relates to semiconductor applications, more particularly it relates to a kind of FinFET and its manufacture method.
Semiconductor integrated circuit（IC）Industry experienced Exponential growth.The technological progress of IC materials and design aspect is produced In IC generations, each of which generation, all has smaller than previous generation and more complicated circuit.During IC develops, functional density （The quantity of interconnection devices on i.e. per chip area）It is significantly increased and physical dimension（The minimum that can be created using manufacturing process Element（Or line））Reduce.This scaled technique is generally by improving production efficiency and reducing relevant cost and band Carry out benefit.
This scaled technique also increases processing and production IC complexity, thus in order to realize that these improve, Need to process the similar development with manufacture view in IC.For example, having had been introduced into such as fin formula field effect transistor（FinFET） Three-dimensional transistor replace planar transistor.Although the method for existing FinFET and manufacture FinFET is generally sufficient To realize their expected purpose, but it is not already what is be entirely satisfactory in every respect.Thus expect changing in this field Enter.
In order to solve the problems of in the prior art, according to an aspect of the invention, there is provided a kind of semiconductor Device, including：Substrate, with area of grid and source electrode and drain electrode（S/D）Region；First fin structure, positioned at the area of grid In, first fin structure includes：It is used as the first semiconductor material layer of the bottom of first fin structure；Conductor oxidate Layer, is used as the exterior portion at the middle part of first fin structure；It is used as the of the core at the middle part of first fin structure Semiconductor material layer；With the second semiconductor material layer, the top of first fin structure is used as；High k（HK）/ metal gates （MG）Stack, in the area of grid, the HK/MG stacks are covered in the top of part first fin structure； And S/D parts, in the S/D regions.
In the semiconductor devices, the first semiconductor material layer of the bottom as first fin structure and institute Stating the first semiconductor material layer of the core at the middle part as first fin structure includes the SiGe of epitaxial growth （SiGex）, wherein x is the Ge components represented with atomic percent.
In the semiconductor devices, in the area of grid, the Ge groups of the SiGe layer of the core at the middle part Divide x higher than the Ge components x of the SiGe layer of the bottom of first fin structure.
In the semiconductor devices, the Ge components x of the SiGe layer of the core at the middle part is about 0.2 to about 0.5 In the range of.
In the semiconductor devices, SiGexThe thickness of layer is in the range of about 5nm to about 40nm.
In the semiconductor devices, the exterior portion at the middle part of first fin structure is SiGeOy, wherein y is with original The oxygen component that sub- percentage is represented.
In the semiconductor devices, SiGeOyBy in the area of grid to the SiGe in first finxLayer is real Applying heat oxidation technology obtains volumetric expansion and formed.
In the semiconductor devices, second semi-conducting material includes silicon（Si）.
In the semiconductor devices, described Si layers thickness is in the range of about 20nm to about 50nm.
In the semiconductor devices, the S/D parts include the semi-conducting material of epitaxial growth.
In the semiconductor devices, there is single source feature, single drain electrode between two neighbouring area of isolation Part and multiple HK/MG stacks.
In the semiconductor devices, common source of the single S/D parts as the multiple HK/MG stacks/ Drain electrode.
According to another aspect of the present invention there is provided a kind of semiconductor devices, including：Substrate, with multiple area of isolation, Area of grid between neighbouring area of isolation and by the area of grid separated source region and drain region；First Fin structure, in area of grid, first fin structure includes：It is used as the SiGe of bottom（SiGex）Layer, wherein x is with original The Ge components that sub- percentage is represented；It is used as the silicon germanium oxide of middle part-exterior portion（SiGeOy）Layer, wherein y is with atom hundred Divide the oxygen component than representing；It is used as the SiGe of middle part-corezLayer, wherein z is the Ge components represented with atomic percent； With the Si layers as top；Source feature and drain feature, respectively in the source region and the drain region；And High k/ metal gates（HK/MG）, in the area of grid, the HK/MG is covered in above first fin structure of part.
In the semiconductor devices, z is substantially higher than x.
In the semiconductor devices, single source electrode and drain feature and multiple HK/MG stacks be located at two it is neighbouring Between area of isolation, and the single S/D parts are used as common source/drain electrode of multiple HK/MG stacks.
According to another aspect of the invention fin formula field effect transistor is manufactured there is provided one kind（FinFET）The side of device Method, methods described includes：Substrate is provided, the substrate includes：The first fin with area of grid；Separated by the area of grid Source electrode and drain region；Interior area of isolation between first fin；With the isolated area for including multiple interior area of isolation Domain；By first fin-shaped into recess；Foring first the first semiconductor material layer of fin Epitaxial growth of recess；Described The semi-conducting material of epitaxial growth on top second of first semiconductor material layer；By the interior area of isolation formation recess, with horizontal stroke To the top of second semi-conducting material is exposed, so as to form the second fin；It is square into dummy grid stack over the substrate, Including the top for the Part I of the second fin being covered in the area of grid；Remove the Part II of second fin, institute State Part II neighbouring dummy grid stack in the source electrode and drain region；It is outer on the second fin for form recess The semi-conducting material of epitaxial growth the 3rd, to form single source electrode/drain feature between two neighbouring area of isolation；Remove described Dummy grid stack is to form gate trench；By the interior area of isolation formation recess in the gate trench, laterally to expose institute State a part for the first semi-conducting material in the second fin；To the first semiconductor material of second fin in the gate trench The bed of material and the second semiconductor material layer implement thermal oxidation technology, and the exterior section of the first semi-conducting material exposed is changed into The outer layer of second semiconductor is simultaneously changed into the second conductor oxidate by the first conductor oxidate；Remove described the second half Conducting oxide, to expose the second semi-conducting material as the top of second fin in the gate trench；And Form high k/ metal gates（HK/MG）Stack, the HK/MG stacks are covered in the top of a part for second fin.
In the process, first semi-conducting material is SiGe（SiGex）, wherein x is represented with atomic percent Ge components, it is in the range of about 0.2 to about 0.5；Second semi-conducting material includes silicon（Si）.
In the process, in the combination of steam atmosphere and oxygen atmosphere in the pressure of about 1 atmospheric pressure and about 400 DEG C to about The thermal oxidation technology is carried out at a temperature in the range of 600 DEG C.
In the process, the single S/D parts are used as multiple HK/MG stacks between neighbouring area of isolation Common source/drain electrode.
When reading in conjunction with the accompanying drawings, the present invention may be better understood according to following detailed description.It should be emphasized that , the standard practices in industry, the purpose that various parts are not necessarily to scale and are merely to illustrate.It is actual On, for the sake of clear discussion, the size of various parts can be arbitrarily increased or decreased.
Fig. 1 is the flow chart for the exemplary method that FinFET is manufactured according to various aspects of the invention.
Fig. 2A is the diagram perspective drawing of the FinFET of each technique of experience according to an embodiment of the invention.
Fig. 2 B are the example FinFET devices along the line A-A in Fig. 2A in the fabrication stage built according to Fig. 1 method The sectional view of part.
Fig. 3 A are the diagram perspective drawings of the FinFET of each technique of experience according to an embodiment of the invention.
Fig. 3 B are the example FinFET devices along the line A-A in Fig. 3 A in the fabrication stage built according to Fig. 1 method The sectional view of part.
Fig. 4 to Fig. 6 is the example along the line A-A in Fig. 2A in the fabrication stage built according to Fig. 1 method The sectional view of FinFET.
Fig. 7 is the diagram perspective drawing of the FinFET of each technique of experience according to an embodiment of the invention.
Fig. 8, Figure 10, Figure 11, Figure 12 and Figure 13 be according to Fig. 1 method build in the fabrication stage along in Fig. 7 The sectional view of line B-B example FinFET.
Fig. 9 is the example FinFET along the line C-C in Fig. 7 in the fabrication stage built according to Fig. 1 method Sectional view.
In order to implement the different parts of the present invention, disclosure below provides many different embodiments or example. The particular instance of element and arrangement is described below to simplify the present invention.Certainly these are only that example is not intended to be used to limit.Example Such as, first component is on second component in the following description or the formation of top can include wherein first component and second Part may also be included in which and can be formed between first component and second component directly to contact the embodiment formed Extra part so that the embodiment that the first and second parts can be not directly contacted with.
No. 13/740,373 application of United States serial submitted on January 14th, 2013 is incorporated herein by reference.
The application is related to FinFET, but is not limited to FinFET otherwise.FinFET is for example Can include P-type mos（PMOS）FinFET and N-type metal-oxide semiconductor (MOS)（NMOS） The complementary metal oxide semiconductor of FinFET（CMOS）Device.Disclosure below will be gone on to say with FinFET examples Each embodiment of the present invention.However it will be appreciated that unless explicitly stated otherwise herein, the application is not limited to the device of particular type Part.
Fig. 1 is the flow chart for being used to manufacture the method 100 of FinFET according to each aspect of the present invention.It is appreciated that Can before the process per se, during and after extra step is provided, and for the other embodiment of this method, described one A little steps can be replaced or remove.The invention also describe that according to the manufacture of method 100 as shown in Fig. 2A to Figure 13 Several not be the same as Examples of FinFET 200.Repeat reference numerals and/or letter in various embodiments of the invention.It is this Repetition is that for purpose of brevity and clarity, and its own is not offered as between each embodiment and/or structure for being discussed Relation.
Fig. 2A is the diagram perspective of the first embodiment of the FinFET 200 of each technique of experience according to Fig. 1 method Figure.Fig. 2 B and Fig. 4 to Fig. 6 is the sectional view of the example of the FinFET 200 along the line A-A in Fig. 2A.
Fig. 3 A are the diagram perspectives of another embodiment of the FinFET 200 of each technique of experience according to Fig. 1 method Figure.Fig. 3 B are the sectional views of the example FinFET 200 along the line A-A in Fig. 3 A.
Fig. 7 is another embodiment of the FinFET 200 of each technique of experience of one embodiment of the method according to Fig. 1 Diagram perspective drawing.Fig. 8 and Figure 10 to Figure 13 is the sectional view along line B-B Fig. 7 FinFET 200；And Fig. 9 is Along the sectional view of line C-C FinFET.Line B-B is parallel to line C-C.
A to Fig. 2 B referring to Figures 1 and 2, method 100 starts from step 102, and there is provided substrate 210.In the present embodiment, serve as a contrast Bottom 210 is bulk silicon substrate.Alternatively, substrate 210 can include elemental semiconductor, the silicon or germanium of such as crystal structure form； Compound semiconductor, such as SiGe, carborundum, GaAs, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide；Or they Combination.Possible substrate 210 also includes silicon-on-insulator（SOI）Substrate.Isolated using note oxygen（SIMOX）, wafer engagement and/or Other suitable methods manufacture SOI substrate.
Some illustrative substrates 210 also include insulator layer.Insulator layer includes any suitable material, including oxidation Silicon, sapphire and/or combinations thereof.Exemplary insulated body layer can be oxygen buried layer（BOX）.By such as injecting（For example, SIMOX）, oxidation, any suitable technique of deposition and/or other suitable techniques formation insulators.It is exemplary at some In FinFET precursors, insulator layer is the part of silicon-on-insulator substrate（For example, layer）.
According to design requirement as known in the art, substrate 210 can include various doped regions.Doped region can be mixed It is miscellaneous to have p-type dopant, such as boron or BF2；N-type dopant, such as boron or arsenic；Or combinations thereof.Can be directly in substrate 210 Doped region is formed in upper, p-well structure, in N well structures, in Dual Well Structure or using raised structure.Substrate 210 can enter One step includes various active regions, and the region and configuration for being such as configured to N-type metal oxide semiconductor transistor device are used In the region of P-type mos transistor device.
The first fin 220 is formed in the top of substrate 210.In certain embodiments, substrate 210 includes the first more than one fin 220.Pass through any suitable technique the first fin 220 of formation including various depositions, photoetching and/or etch process.As example, Pass through the part to silicon substrate 210（Referred to as first groove 215）Patterned and etched to form the first fin 220.Another In one example, pass through the silicon layer to being deposited on insulator layer（The silicon-on-insulator of such as SOI substrate-silicon stack overlapping piece it is upper Layer silicon layer）Patterned and etched to form the first fin 220.In addition, before patterning and etch process, in substrate 210 The first hard mask layer of disposed thereon 212.First hard mask layer 212 includes silica, silicon nitride, silicon oxynitride or any other is suitable The dielectric material of conjunction.First hard mask layer 212 can be single or multiple lift.First hard mask layer 212 can pass through thermal oxide, change Learn oxidation, ald（ALD）Or any other appropriate method is formed.It is appreciated that to form multiple in a similar manner The first parallel fin 220.
Various area of isolation 230 are formed in substrate 210 or on substrate 210.Such as shallow trench isolation can be used （STI）Traditional isolation technology formation area of isolation 230 limit and be electrically isolated various regions.It is used as an example, STI shape Into including photoetching process；Second groove 225 is etched in substrate 210；Second groove is filled with one or more dielectric layers 235 225（For example by using chemical vapor deposition process）.Dielectric material includes silica, silicon nitride, silicon oxynitride or other are suitable The material or combinations thereof of conjunction.In the present embodiment, second groove 225 is significantly deeper than and is wider than first groove 215. There are one or more first grooves 215 between two second grooves.Dielectric layer while second groove 225 are filled 235 filling first grooves 215.In some instances, the groove 215 and 225 after filling can have sandwich construction, such as fill There is the thermal oxide lining of silicon nitride or silica.
Reference picture 3A and Fig. 3 B, it is another implement profit in, by using dielectric layer 235 fill first groove 215 come formed every From region 230.
In addition, implementing chemically mechanical polishing（CMP）Technique removes unnecessary dielectric layer 235 and makes area of isolation 230 The top planar of top surface and the first fin 220.In addition, CMP also removes the first hard mask 212.
Reference picture 1 and Fig. 4, method 100 proceed to step 104, and the first fin 220 is formed recess to form the 3rd groove 310.Dry etching process, wet etching process and/or combinations thereof can be included by forming recess technique.Recess technique is formed may be used also With including selective wet etching or selective dry ecthing.Wet etching solution includes TMAH（TMAH）、HF/HNO3/ CH3COOH solution or other suitable solution.Dry ecthing and wet etching process have adjustable etching parameter, such as use Etchant, etch temperature, etching solution concentration, etching pressure, source power, RF bias voltages, RF bias powers, etchant flow velocity Suitable parameter with other.For example, wet etching solution can include NH4OH、KOH（Potassium hydroxide）、HF（Hydrofluoric acid）、TMAH （TMAH）, other suitable wet etching solutions or combinations thereof.Dry etching process is including the use of based on chlorine The bias plasma etch process of chemical substance.Other dry ecthing agent gases include CF4、NF3、SF6And He.It can also use Such as DRIE（Deep reactive ion etch）Mechanism anisotropically implement dry ecthing.
Reference picture 1 and Fig. 5, method 100 proceed to step 106, deposit the first semiconductor material layer 410 to be partially filled with 3rd groove 310 and over top the second semiconductor material layer 420 of deposition in the first semi-conducting material 410.It can pass through Epitaxial growth technology deposits the first semiconductor material layer 410 and the second semiconductor material layer 420.Epitaxy technique includes chemical vapor Deposition（CVD）Deposition technique（Such as vapour phase epitaxy（VPE）And/or ultrahigh vacuum CVD（UHV-CVD））, molecular beam epitaxy and/or Other suitable techniques.First semiconductor material layer 410 and the second semiconductor material layer 420 can include germanium（Ge）, silicon（Si）、 GaAs（GaAs）, aluminum gallium arsenide（AlGaAs）, SiGe（SiGe）, gallium arsenide phosphide（GaAsP）Or other suitable materials.One In individual embodiment, the first semiconductor material layer 410 is SiGe, and the second semiconductor material layer 420 is Si.In addition it is possible to implement CMP Technique come remove unnecessary semiconductor material layer 410 and 420 and make semiconductor material layer 420 and area of isolation 230 top surface put down Smoothization.
Reference picture 1 and Fig. 6, method 100 proceed to step 108, will be around the second semiconductor material layer 420 and the second half and lead The formation recess of dielectric layer 235 of body material layer 410, laterally to expose the second semiconductor material layer 420 and the first semi-conducting material The top of layer 410, so as to form the second fin 510.In the present embodiment, the second fin 510 is made to be formed as layer 420, layer 410 and layer 210 stack（With order from top to bottom）.Formed recess technique can include dry etching process, wet etching process and/or Combinations thereof.
Reference picture 7, in the present embodiment, a part for the second fin 510 are defined as regions and source/drain 530, and another Part is defined as area of grid 540.Regions and source/drain 530 is separated by area of grid 540.
Reference picture 1 and Fig. 8, method 100 proceed to step 110, and being formed in area of grid 540 includes covering （wrapping）Between gate stack 610 in the top of a part for the second fin 510 and the side wall along gate stack 610 Spacing body 620.In first grid technology, gate stack 610 can be all or part of functional gate.On the contrary, in post tensioned unbonded prestressed concrete In technique, gate stack 610 can be dummy grid.In the present embodiment, gate stack 610 is dummy grid.Implementing high After hot temperature process, such as after the thermal process during source/drain formation, dummy grid stack 610 is later by high k （HK）And metal gates（MG）Replace.The puppet of the top for the part for including being covered in the second fin 510 is formed in the top of substrate 210 Gate stack 610.Dummy grid stack 610 can include dielectric layer 612, the hard mask 616 of polysilicon layer 614 and second.It is pseudo- Gate stack 610 can be formed by any suitable one or more techniques.For example, can be by including deposition, photoetching The process formation gate stack 610 of patterning and etch process.Depositing operation includes CVD, PVD（PVD）、 ALD, other suitable methods and/or combinations thereof.Lithographic patterning technique is coated with including photoresist（Such as rotary coating）、 Soft baking, mask registration, exposure, postexposure bake, lithographic glue, rinsing, drying（Such as hard baking）, other suitable works Skill and/or combinations thereof.Etch process includes dry ecthing, wet etching and/or other engraving methods（For example reactive ion loses Carve）.Dielectric layer 612 includes silica, silicon nitride or any other suitable material.Second hard mask 616 includes any be adapted to Material, such as silicon nitride, silicon oxynitride and carborundum.
Sidewall spacer 620 can include dielectric material, such as silica, silicon nitride, carborundum, silicon oxynitride or they Combination.Sidewall spacer 620 can include multilayer.The method that is typically formed of sidewall spacer 620 is included in gate stack 610 disposed thereon dielectric materials, then carry out anisotropically etch-back to dielectric material.Etch back process can include multistep Etching is controlled with increasing etching selectivity, flexibility and desired overetch.
Referring again to Fig. 1 and Fig. 9, method 100 proceeds to step 112, and source/drain is formed in regions and source/drain 530 Pole part 720.In one embodiment, each second fin 510 between two area of isolation 230, and two second are removed Dielectric layer 235 between fin 510, so as to form common source/drain groove 710 in the top of substrate 210.Form recess technique Dry etching process, wet etching process and/or combinations thereof can be included.Selective wet can also be included by forming recess technique Carve or selective dry ecthing.Multiple etch process can be included by forming recess technique.In another embodiment, instead of being formed altogether Source/drain groove 710 is formed in same source/drain groove 710, each type between two area of isolation 230, It is referred to as each source/drain groove 710.By the part formation recess by the second fin 510 between area of isolation 230 Form each source/drain groove 710.
The semi-conducting material of epitaxial growth the 3rd is to form source/drain part 720 in source/drain groove 710.3rd Semi-conducting material includes Ge, Si, GaAs, AlGaAs, SiGe, GaAsP or other suitable materials.Can be by one or more Epitaxial growth or extension（epi）Technique forms common source/drain part 720.Can be during epitaxy technique to source/drain Pole part 720 carries out doping in situ.For example, the SiGe source/drains part 720 of epitaxial growth can be doped with boron；And extension The Si epitaxial source/drain features 720 of growth can form Si doped with carbon：C-source/drain feature, doped with phosphorus with shape Into Si：P source/drain parts, or doped with carbon and phosphorus to form SiCP source/drain parts.In one embodiment, it is right Source/drain part 720 does not carry out doping in situ, implements injection technology（Tie injection technology）With to source/drain part 720 It is doped.
In one embodiment, by common source/drain groove 710 semi-conducting material of epitaxial growth the 3rd exist Single source electrode/drain feature 720 is formed between two area of isolation 230.In another embodiment, by each source electrode/ The semi-conducting material of epitaxial growth the 3rd forms multiple source/drain parts between two area of isolation 230 in drain trenches 710 720。
In addition, forming interlayer dielectric between dummy grid stack 610 in the top of substrate 210（ILD）Layer 730.ILD layer 730 include silica, nitrogen oxides or other suitable materials.ILD layer 730 includes single or multiple lift.Pass through such as CVD, ALD And spin coating（SOG）Suitable technology formation ILD layer 730.Chemically mechanical polishing can be implemented（CMP）It is unnecessary that technique is removed The top surface of ILD layer 730 and top surface and dummy grid stack 610 to ILD layer 730 is planarized.
Reference picture 1 and Figure 10, method 100 proceed to step 114, remove dummy grid stack 610 to form gate trench 810 and the dielectric layer 235 in gate trench 810 is formed recess laterally to expose the first semiconductor material layer of the second fin 510 410 at least a portion.Etch process can include selective wet etching or selective dry ecthing, to be led relative to the first half The semiconductor material layer 420 of body material layer 410 and second and sidewall spacer 620 have enough etching selectivities.Alternatively, may be used So that dummy grid stack 610 and dielectric layer 235 are formed into recess by the series of process including lithographic patterning and etch-back. After recess is formed, the first semiconductor material layer 410 has the first width w1.
Reference picture 1 and Figure 11, method 100 proceed to step 116, to exposing in the second fin 510 in gate trench 810 The first semiconductor material layer 410 and the second semiconductor material layer 420 implement thermal oxidation technology.In one embodiment, in oxygen Thermal oxidation technology is carried out in atmosphere.In another embodiment, thermal oxide work is carried out in the combination of steam atmosphere and oxygen atmosphere Skill.During thermal oxidation technology, a part for the first semiconductor material layer 410 exposed in the second fin 510, which is changed into, to be had Second width w2The first semiconductor oxide nitride layer 815, while at least one outer layer of the second semiconductor material layer 420 exposed Change into the second conductor oxidate 820.
During thermal oxidation technology, the first semiconductor material layer 410 obtains volumetric expansion.In the present embodiment, to first The semiconductor material layer 420 of semiconductor material layer 410 and second and thermal oxidation technology, which carry out configuration, makes the first semiconductor material layer 410 obtain w2With w1Ratio be more than 1.6 volumetric expansion, so as to realize the channel strain of expected degree, such as 1Gpa stretching Strain.As example, the first semiconductor material layer 410 is thickness in 5nm to the SiGex between 20nm1, wherein x1It is with atom The first Ge components in the range of 0.2 to 0.5 that percentage is represented.And the second semiconductor material layer 420 be thickness in 20nm extremely Si in the range of 40nm.Temperature in the combination of steam atmosphere and oxygen atmosphere, in the range of 1 atmospheric pressure and 400 DEG C to 600 DEG C Lower carry out thermal oxidation technology.During thermal oxidation technology, SiGex1The exterior portion of layer 410 changes into silicon germanium oxide（SiGeOy） Layer 815, wherein y is the oxygen component represented with atomic percent, and obtains w2With w1Ratio be 1.8 volumetric expansion.SiGex1 The core of layer 410 becomes the 2nd Ge components x2, it compares x1It is much higher.SiGex2Core size and dimension with The process conditions of such as oxidate temperature and time and change.The outer layer of Si layers 420 changes into silica simultaneously（SiOz）820, Wherein z is the oxygen component represented with atomic percent.By the volumetric expansion of SiGeOy layers 815, elongation strain can be induced The second fin 510 into area of grid 540, will form grid groove here.
Reference picture 1 and Figure 12, method 100 proceed to step 118, remove the second semiconductor oxide nitride layer 820 and the first half A part for the outer layer of conductive oxide layers 815 is with the 3rd fin 910 of display in area of grid 540.Removing technique includes dry corrosion Quarter, wet etching or combinations thereof.For example, having relative to the first semiconductor material layer 410 and the second semiconductor material layer 420 Implement selective wet etching or selective dry ecthing in the case of there are enough etching selectivities.3rd fin 910 is configured Under making it have the second semiconductor material layer 420 as top, the first semiconductor oxide nitride layer 815 as middle part and being used as First semiconductor material layer 410 in portion.
Reference picture 1 and Figure 13, method 100 proceed to step 120, and being formed in the top of substrate 210 includes being covered in gate regions The high k of the top of a part for the 3rd fin 910 in domain 540（HK）/ metal gates（MG）920, wherein the 3rd fin 910 is used as grid Pole channel region.Pass through such as ALD, CVD and ozone oxidation any suitable method deposited interfacial layer（IL）922.IL922 bags Include oxide, HfSiO and nitrogen oxides.Pass through such as ALD, CVD, metallorganic CVD（MOCVD）, PVD, thermal oxide, they The suitable technology or other suitable technologies of combination are in IL922 disposed thereon HK dielectric layers 924.HK dielectric layers 924 can be wrapped Include LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3 (BST), Al2O3, Si3N4, nitrogen oxides（SiON）Or other are adapted to Material.
Metal gates（MG）Layer 930 can include single or multiple lift, such as metal level, lining, wetting layer and adhesive layer.MG Layer 930 can include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W or appoint What suitable material.ALD, PVD, CVD or other suitable techniques formation MG layers 930 can be passed through.For N-FET and P-FFET It could be separately formed the MG layers 930 with different metal layer.CMP can be implemented to remove unnecessary MG layers 930.CMP is gold Belong to grid layer 930 and ILD layer 730 provides the top surface of substantially flat.
It is as known in the art each to be formed that FinFET 200 can carry out further CMOS or MOS technology processing Plant part and region.For example, following process can form various contact/through hole/lines and multilayer interconnection portion in the top of substrate 210 Part（Such as metal level and interlayer dielectric）, it is configured to connect the various parts or structure of FinFET 200.For example, multilayer Interconnection includes the perpendicular interconnection part of such as conventional through holes or contact and the horizontal cross tie part of such as metal wire.Various interconnecting members Various conductive materials, including copper, tungsten and/or silicide can be applied.In an example, using inlaying and/or dual damascene work Skill forms the related multilayer interconnection structure of copper.
Extra step can be provided before and after, during method 100, and for the other embodiment of method, Some described steps can be replaced or remove.
Based on the above, the invention provides with the strain grid by using volume expansion technique and serve many The semiconductor devices of single source electrode/drain feature of grid.Volume expansion technique cause grid groove occur enough strain with Device performance is improved, and single source electrode/drain feature is beneficial to source/drain resistance reduction.
The invention provides many different embodiments of semiconductor devices.Semiconductor devices include with area of isolation, Area of grid, by the separated source electrode of area of grid and drain electrode（S/D）Region, the lining of the first fin structure in area of grid Bottom.First fin structure includes the first semiconductor material layer of the bottom as first fin structure, is used as first fin structure The semiconductor oxide nitride layer of the exterior portion at middle part, as first fin structure middle part core the first semiconductor material The bed of material and second semiconductor material layer on top as first fin structure.Semiconductor devices is additionally included in neighbouring isolated area It is located at the regions and source/drain above the substrate in regions and source/drain between domain and includes being covered in above substrate The high k of the top of a part for the first fin structure in area of grid（HK）/ metal gates（MG）Stack.
In another embodiment, FinFET is included with area of isolation, area of grid, separated by area of grid Source electrode and drain region, the substrate of the first fin structure in area of grid.First fin structure includes the SiGe as bottom （SiGex）Layer, wherein x is the Ge components represented with atomic percent；It is used as the silicon germanium oxide of the exterior portion at middle part（SiGeOy） Layer, wherein y is the oxygen component represented with atomic percent；It is used as the SiGe of the core at middle partzLayer, wherein z is with atom The Ge components that percentage is represented；And it is used as the Si layers on top.FinFET also includes being located in source electrode and drain region The height of the top of a part for source/drain part and the first fin structure for including being covered in area of grid positioned at substrate top K/ metal gates（HK/MG）.
In yet another embodiment, a kind of method for manufacturing FinFET includes providing substrate.Substrate includes having grid First fin in polar region domain, by the separated source electrode of area of grid and drain region, interior area of isolation and bag between the first fin Area of isolation containing multiple interior area of isolation.This method also includes the first fin-shaped into recess；On the first fin of recess is formed The square semiconductor material layer of epitaxial growth first；In over top epitaxial growth the second semiconductor material of the first semiconductor material layer Material；Interior area of isolation is formed recess laterally to expose the top of the second semi-conducting material to form the second fin；Above substrate Form the dummy grid stack of the top of a part for the second fin for including being covered in area of grid；In source electrode and drain region Middle another part for removing the second fin beside dummy grid stack；It is being formed epitaxial growth the 3rd above the second fin of recess Semi-conducting material between two neighbouring area of isolation to form single source electrode/drain feature；Remove dummy grid stack with Form gate trench；Interior area of isolation in gate trench is formed recess laterally to expose the first semiconductor in the second fin A part for material；The first semiconductor material layer and the second semiconductor material layer in gate trench to the second fin implement hot oxygen Chemical industry skill is to change into the first conductor oxidate by the exterior portion of the expose first semi-conducting material and be led the second half The outer layer of body changes into the second conductor oxidate；Remove the second conductor oxidate and be used as to be exposed in gate trench Second semi-conducting material on the top of two fins；And form the high k/ metal gates of the top for the part for being covered in the second fin （HK/MG）Stack.
The part of some embodiments is discussed above so that each of the present invention may be better understood in those skilled in the art Individual aspect.It should be appreciated by those skilled in the art that easily can design using based on the present invention or change other Technique and structure for reaching with embodiments described herein identical purpose and/or realizing same advantage.This area skill Art personnel are it should also be appreciated that these equivalent constructions are without departing from the spirit and scope of the present invention, and without departing substantially from the present invention Spirit and scope in the case of, can carry out it is a variety of change, replace and change.
Substrate, with area of grid and source electrode and drain electrode (S/D) region；
First fin structure, in the area of grid, first fin structure includes：
It is used as the first semiconductor material layer of the bottom of first fin structure；
Semiconductor oxide nitride layer, is used as the exterior portion at the middle part of first fin structure；
It is used as the first semiconductor material layer of the core at the middle part of first fin structure；With
Second semiconductor material layer, as the top of first fin structure,
Wherein, as first fin structure middle part core the first semiconductor material layer and the semiconductor oxygen Compound layer, is formed by the first semiconductor material layer of the bottom as first fin structure by thermal oxidation technology；
High k (HK)/metal gates (MG) stack, in the area of grid, the high k/ metal gate stacks part covering In the top of part first fin structure, wherein, the high k/ metal gate stacks part includes：
Boundary layer, is consecutively provided in above the semiconductor oxide nitride layer and second semiconductor material layer, wherein, it is described The surface of the semiconductor oxide nitride layer is completely covered in boundary layer；And
Dielectric layer, and the boundary layer direct physical contact, wherein, the dielectric layer and described two relative sides of boundary layer Surface physics is contacted, and the top for the interface layer surfaces being arranged between described two relative sides；And
Source electrode and drain feature, in the source electrode and drain region.
2. semiconductor devices according to claim 1, wherein, the first the half of the bottom as first fin structure First semiconductor material layer of conductor material layer and the core at the middle part as first fin structure includes extension The SiGe of growthx, wherein x is the Ge components represented with atomic percent.
3. semiconductor devices according to claim 2, wherein, in the area of grid, the core at the middle part SiGe layer bottoms of the Ge components x than first fin structure SiGe layer Ge components x it is higher.
4. semiconductor devices according to claim 3, wherein, the Ge components x of the SiGe layer of the core at the middle part In the range of 0.2 to 0.5.
5. semiconductor devices according to claim 2, wherein, SiGexThe thickness of layer is in the range of 5nm to 40nm.
6. semiconductor devices according to claim 2, wherein, the exterior portion at the middle part of first fin structure is SiGeOy, wherein y is the oxygen component represented with atomic percent.
7. semiconductor devices according to claim 6, wherein, SiGeOyBy in the area of grid to described first SiGe in finxLayer implements thermal oxidation technology and obtains volumetric expansion and formed.
8. semiconductor devices according to claim 1, wherein, second semi-conducting material includes silicon (Si).
9. semiconductor devices according to claim 8, wherein, the thickness of the silicon layer is in the range of 20nm to 50nm.
10. semiconductor devices according to claim 1, wherein, the source electrode and drain feature include the half of epitaxial growth Conductor material.
11. semiconductor devices according to claim 1, wherein, there is single source between two neighbouring area of isolation Pole part, single drain feature and multiple high k/ metal gate stacks parts.
12. semiconductor devices according to claim 11, wherein, the single source electrode and drain feature are as the multiple Common source/drain electrode of high k/ metal gate stacks part.
13. a kind of semiconductor devices, including：
Substrate, with multiple area of isolation, the area of grid between neighbouring area of isolation and by the area of grid point The source region and drain region opened；
First fin structure, in area of grid, first fin structure includes：
It is used as the SiGe of bottomxLayer, wherein x is the Ge components represented with atomic percent；
It is used as the SiGeO of middle part-exterior portionyLayer, wherein y is the oxygen component represented with atomic percent；
It is used as the SiGe of middle part-corezLayer, wherein z is the Ge components represented with atomic percent；With
As the Si layers on top,
Wherein, as the SiGe of middle part-corezLayer and it is used as the SiGeO of middle part-exterior portionyLayer, by being used as bottom SiGexLayer is formed by thermal oxidation technology；
Source feature and drain feature, respectively in the source region and the drain region；And
High k/ metal gates (HK/MG), in the area of grid, the high k/ metal gates are covered in part described first Above fin structure, wherein, the high k/ metal gates include：
Dielectric layer, and the boundary layer direct physical contact, wherein, the dielectric layer and described two relative sides of boundary layer Surface physics is contacted, and the top for the interface layer surfaces being arranged between described two relative sides.
14. semiconductor devices according to claim 13, wherein, z is higher than x.
15. semiconductor devices according to claim 13, wherein, SiGeOyBy in the area of grid to described SiGe in one finxLayer implements thermal oxidation technology and obtains volumetric expansion and formed.
16. semiconductor devices according to claim 13, wherein, single source electrode and drain feature and multiple high k/ metal gates Pole stack is located between two neighbouring area of isolation, and the single source electrode and drain feature are used as multiple high k/ metals Common source/drain electrode of gate stack.
17. the method for one kind manufacture fin formula field effect transistor (FinFET) device, methods described includes：
Substrate is provided, the substrate includes：
The first fin with area of grid；
By the separated source electrode of the area of grid and drain region；
Interior area of isolation between first fin；With
Include the area of isolation of multiple interior area of isolation；
By first fin-shaped into recess；
Foring first the first semiconductor material layer of fin Epitaxial growth of recess；
In the semi-conducting material of epitaxial growth on top second of first semiconductor material layer；
By the interior area of isolation formation recess, laterally to expose the top of second semi-conducting material, so as to form second Fin；
It is square into dummy grid stack over the substrate, include the Part I for the second fin being covered in the area of grid Top；
Remove the Part II of second fin, the Part II neighbouring dummy grid in the source electrode and drain region Stack；
The semi-conducting material of the second fin Epitaxial growth the 3rd of recess is being formd, with the shape between two neighbouring area of isolation Into single source electrode/drain feature；
The dummy grid stack is removed to form gate trench；
By the interior area of isolation formation recess in the gate trench, laterally to expose the first semiconductor material in second fin A part for material；
Implement hot oxygen to the first semiconductor material layer of second fin and the second semiconductor material layer in the gate trench Chemical industry skill, the first conductor oxidate is changed into and by described the second half by the exterior section of the first semi-conducting material exposed The outer layer of conductor changes into the second conductor oxidate；
Second conductor oxidate is removed, to be exposed in the gate trench as the top of second fin Two semi-conducting materials；And
High k/ metal gates (HK/MG) stack is formed, the high k/ metal gate stacks part is covered in the one of second fin Partial top.
18. method according to claim 17, wherein, first semi-conducting material is SiGex, and wherein x is with atom The Ge components that percentage is represented, it is in the range of 0.2 to 0.5；Second semi-conducting material includes silicon (Si).
19. method according to claim 17, wherein, in the pressure of 1 atmospheric pressure in the combination of steam atmosphere and oxygen atmosphere The thermal oxidation technology is carried out at a temperature in the range of power and 400 DEG C to 600 DEG C.
20. method according to claim 17, wherein, the single source electrode/drain feature is used as neighbouring isolated area Common source/drain electrode of multiple high k/ metal gate stacks parts between domain.
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