Source: http://www.google.com/patents/US7821853?dq=patent:5881444
Timestamp: 2014-12-19 16:17:10
Document Index: 575123634

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US7821853 - Memory redundance circuit techniques - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsIn a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller,...http://www.google.com/patents/US7821853?utm_source=gb-gplus-sharePatent US7821853 - Memory redundance circuit techniquesAdvanced Patent SearchPublication numberUS7821853 B2Publication typeGrantApplication numberUS 12/190,394Publication dateOct 26, 2010Filing dateAug 12, 2008Priority dateFeb 2, 2000Fee statusPaidAlso published asUS7411846, US20040196721, US20070183230, US20080298146Publication number12190394, 190394, US 7821853 B2, US 7821853B2, US-B2-7821853, US7821853 B2, US7821853B2InventorsEsin TerziogluOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (35), Non-Patent Citations (1), Referenced by (1), Classifications (11), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMemory redundance circuit techniquesUS 7821853 B2Abstract In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a �FAILED� memory group condition. The redundancy controller also can includeselectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.
1. A memory redundancy circuit in a memory module having a designated group of memory cells assigned to represent a logical portion of a memory structure, the memory redundancy circuit comprising:
wherein the redundancy controller is configured to select at least one of a particular software mode and a particular hardware mode that provides an encoded address signal that represents a portion of the designated group that is to be replaced by a portion of the redundant group.
2. The memory redundancy circuit according to claim 1, wherein the encoded address signal that is stored in a programmable address capture circuit.
5. The memory redundancy circuit according to claim 2, wherein the encoded address signal is loaded through a first input port interface adapted to shift in an appropriate value indicating that at least one of the memory cell groups is flawed.
6. The memory redundancy circuit according to claim 5, comprising:
7. The memory redundancy circuit according to claim 1, wherein the memory redundancy circuit is employable at a wafer level and a device level using software and hardware programming elements.
8. The memory redundancy circuit according to claim 1, comprising:
fuse circuitry that is trimmed by at a wafer level.
9. The memory redundancy circuit according to claim 1, comprising:
latching circuitry,
wherein a particular address signal representing a valid portion of the designated memory is encoded within the latching circuitry.
10. The memory redundancy circuit according to claim 1, comprising:
fuse elements,
wherein values of the fuse elements are latched in parallel.
11. The memory redundancy circuit according to claim 1, comprising:
latching circuitry that comprises serially daisy chained set of latches that shift in the encoded address signal.
12. The memory redundancy circuit according to claim 1, comprising:
a shift clock that is used to serially load the encoded address signal.
13. The memory redundancy circuit according to claim 1, wherein the particular software mode comprises software programmable elements and the particular hardware mode comprises hardware programmable elements.
14. The memory redundancy circuit according to claim 13, wherein the software programmable elements are used to repair faults in the designated group detected at a device level.
15. The memory redundancy circuit according to claim 13, wherein the software programmable elements are used to revert the designated group to an original condition.
16. The memory redundancy circuit according to claim 13, wherein the software programmable elements can program anti-fuse elements.
17. The memory redundancy circuit according to claim 1, wherein the particular software mode uses a presence or an absence of electrical voltages to program anti-fuse elements.
18. The memory redundancy circuit according to claim 17, wherein the anti-fuse elements are programmed individually.
19. The memory redundancy circuit according to claim 10, comprising:
20. The memory redundancy circuit according to claim 16, wherein the circuitry that transfers data into and out of the redundant group of memory cells comprises a redundant read sense amplifier and one or more associated redundant group coupling devices.
21. The memory redundancy circuit according to claim 20, comprising:
an activation signal driven by the redundancy controller to switch in an associated redundant group of memory cells upon the redundancy controller encoding a group address signal representing a non nal group of memory cells that is to be replaced.
22. The memory redundancy circuit according to claim 20, comprising:
an activation signal driven by the redundancy controller to switch in an associated redundant group of memory cells upon the redundancy controller encoding a group address signal representing a particular group of memory cells that is to be switched out.
23. The memory redundancy circuit according to claim 20, wherein the redundant group coupling devices comprise switches that switch in a complimentary localized bit line associated with the redundant group of memory cells to the redundant read sense amplifier.
24. The memory redundancy circuit according to claim 23, wherein at least one of the switches of the redundant group coupling devices operatively couples a particular redundant column of memory cells.
25. The memory redundancy circuit according to claim 24, wherein at least one of the switches of the redundant group coupling devices operatively couples the redundant group of memory cells.
26. The memory redundancy circuit according to claim 1, wherein the redundancy controller comprises a redundancy decoder responsive to an encoded signal representative of the preselected memory group condition.
27. The memory redundancy circuit according to claim 1, wherein the redundancy controller comprises a plurality of selectable switches, the plurality of selectable switches encoding the preselected memory group condition.
28. The memory redundancy circuit according to claim 27, wherein the plurality of selectable switches are fuses.
29. The memory redundancy circuit according to claim 28, wherein the preselected memory group condition is a �FAILED� memory group condition, representative of a designated group malfunction.
30. The memory redundancy circuit according to claim 1, wherein each of the designated group of memory cells and the redundant group of memory cells comprises at least one of the following: a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, and a memory module.
CROSS-REFERENCE TO RELATED APPLICATION(S) The present application is a CONTINUATION of U.S. application Ser. No. 11/669,400, filed Jan. 31, 2007, which is a CONTINUATION of U.S. application Ser. No. 10/824,905, filed Apr. 15, 2004, now U.S. Pat. No. 7,173,867, which is a CONTINUATION of U.S. application Ser. No. 09/776,263, filed Feb. 2, 2001, now issued U.S. Pat. No. 6,745,354.
Said U.S. application Ser. No. 09/776,263 claims benefit from and priority to the following U.S. provisional applications: U.S. Application No. 60/215,741, filed Jun. 29, 2000; U.S. Application No. 60/193,607, filed Mar. 31, 2000; U.S. Application No. 60/193,606, filed Mar. 31, 2000; U.S. Application No. 60/179,777, filed Feb. 2, 2000; U.S. Application No. 60/193,605, filed Mar. 31, 2000; U.S. Application No. 60/179,766, filed Feb. 2, 2000; U.S. Application No. 60/220,567, filed Jul. 25, 2000; U.S. Application No. 60/179,866, filed Feb. 2, 2000; U.S. Application No. 60/179,718, filed Feb. 2, 2000; U.S. Application No. 60/179,765, filed Feb. 2, 2000; U.S. Application No. 60/179,768, filed Feb. 2, 2000; and U.S. Application No. 60/179,865, filed Feb. 2, 2000.
The following related patent applications, assigned to the same assignee hereof and filed on Feb. 2, 2001, disclose related subject matter, with the subject of each being incorporated by reference herein in its entirety:
Asynchronously Resettable Decoder for a Semiconductor Memory, U.S. application Ser. No. 09/775,477; High Precision Delay Measurement Circuit, U.S. application Ser. No. 09/776,262; Single-Ended Sense Amplifier with Sample-and-Hold Reference, U.S. application Ser. No. 09/776,220; Limited Swing Driver Circuit, U.S. application Ser. No. 09/775,478; Asynchronously-Resettable Decoder with Redundancy, U.S. application Ser. No. 09/775,476; Diffusion Replica Delay Circuit, U.S. application Ser. No. 09/776,029; Sense Amplifier with Offset Cancellation and Charge-Share Limited Swing Drivers, U.S. application Ser. No. 09/775,475; Memory Architecture with Single-Port Cell and Dual-Port (Read and Write) Functionality, U.S. application Ser. No. 09/775,701; Memory Redundance Circuit Techniques, U.S. application Ser. No. 09/776,263; and Circuit Technique for High Speed Low Power Data Transfer Bus, U.S. application Ser. No. 09/776,028.
SUMMARY OF THE INVENTION The present invention satisfies the above needs by providing in a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition. The redundancy controller can include a redundancy decoder responsive to an encoded signal representative of the preselected memory group condition, for example, a �FAILED� memory group condition which is representative of a designated group malfunction. The redundancy controller also can include a plurality of selectable switches, for example, fuses, which can encode the preselected memory group condition. In preferred embodiments of the invention herein, the designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof. Certain preferred embodiments of the foregoing memory redundancy implementation can include a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. The memory redundancy circuit can decode the first memory cell group, and is disposed to select and decode the second memory cell group responsive to an group-select signal. The selector responsive to the group-select signal can be a multiplexer.
In order to be able to independently reset word line WL 804, it is desirable that inputs 802, 803 be isolated from output 804, and the node 805 should be charged to Vdd, turning off the large PMOS driver MB 807 once word line WL 804 is set to logical HIGH. Charging of node 805 to Vdd can be accomplished by a feedback-resetting loop. Inputs 802, 803 can be isolated from output 804 setting NMOS device 808 to logic LOW. When output WL 804 goes high, monitor node 810 is discharged to ground, and device M0 812 is shut-off, thus isolating inputs 802, 803 from output WL 804. The feedback loop precharges the rest of the nodes in the buffers via monitor node 810, and PMOSFET M13 815 is turned on, connecting the input x2_n 802 to node 810. Decoder 800 will not fire again until x2_n 802 is reset to Vdd, which usually happens when the system clock signal changes to logic LOW. Once x2_n 802 is logic HIGH, node 810 charges to Vdd, with the assistance of PMOS device M14 818, and device M0 812 is turned on. This turns off PMOS device M13 815, thus isolating input x2_n 802 from the reset loop which employs node 810. Decoder 800 is now ready for the next input cycle.
FIG. 22B illustrates a bidirectional data bus transfer circuit (DBDT) 2250 which employs cross-linked inverters I1 2260 and I2 2270 to couple BUS 1 2252 with BUS 2 2254. It is desirable to incorporate a clocked charge/discharge circuit with DBDT 2250. Coupled with inverter I1 2260 is clocked charge transistor MPC1 2266 and clocked discharge transistor MNC1 2268. Similarly, inverter 12 2270 is coupled with clocked charge transistor MPC2 2276 and clocked discharge transistor MNC2 2278. Transistors MPC1 2266, MNC1 2268, MPC2 2276, and MNC2 2278 are preferred to be driven by clock signal 2280.
Beginning with clock signal 2280 going LOW, charge transistors MPC1 2266 and MPC2 2276 turn ON, allowing BUS 1 input node 2256 and BUS 2 input node 2258 to be precharged to HIGH. Additionally, discharge transistors MNC1 2268 and MNC2 2278 are turned OFF, so that no substantial discharge occurs. By taking input nodes 2256, 2258 to HIGH, respective signals propagate through, and are inverted by inverters I12260 and 12 2270 providing a LOW signal to BUS 1 pass transistor MP12 2262 and BUS 2 pass MP22 2272, respectively, allowing the signal on BUS 1 2252 to be admitted to input node 2256, and then to pass through to BUS 2 input node 2258 to BUS 2 2254, and vice versa. When clock signal 2280 rises to HIGH, both charge transistors MPC1 2266 and MPC2 2276 turn OFF, and discharge transistors MNC1 2268 and MNC2 2278 turn ON, latching the data onto BUS 1 2252 and BUS 2 2254. Upon the next LOW phase of clock signal 2280, a changed signal value on either BUS 1 2252 or BUS 2 2254 will propagate between the buses.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4885720 *Apr 1, 1988Dec 5, 1989International Business Machines CorporationMemory device and method implementing wordline redundancy without an access time penaltyUS5170375Sep 18, 1991Dec 8, 1992Siemens AktiengesellschaftHierarchically constructed memory having static memory cellsUS5307316Oct 16, 1991Apr 26, 1994Fujitsu LimitedSemiconductor memory unit having redundant structureUS5576999Jun 30, 1995Nov 19, 1996Samsung Electronics Co., Ltd.Redundancy circuit of a semiconductor memory deviceUS5596536Jul 24, 1995Jan 21, 1997Hyundai Electronics Industries Co., Ltd.Redundancy circuitUS5677917 *Apr 29, 1996Oct 14, 1997Motorola, Inc.Integrated circuit memory using fusible links in a scan chainUS5748543 *Aug 29, 1996May 5, 1998Samsung Electronics Co., Ltd.Self repairing integrated circuit memory devices and methodsUS5752264Aug 15, 1996May 12, 1998International Business Machines CorporationComputer architecture incorporating processor clusters and hierarchical cache memoriesUS5781498Dec 6, 1996Jul 14, 1998Hyundai Electronics Industries Co., Ltd.Sub word line driving circuit and a semiconductor memory device using the sameUS5848003Jun 27, 1997Dec 8, 1998Nec CorporationSemiconductor memoryUS5864497Oct 30, 1997Jan 26, 1999Hyundai Electronics Industries, Co., Ltd.Memory device having divided global bit linesUS5920515 *Sep 26, 1997Jul 6, 1999Advanced Micro Devices, Inc.Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory deviceUS5930183Nov 25, 1997Jul 27, 1999Fujitsu LimitedSemiconductor memory deviceUS5953258 *Jul 1, 1998Sep 14, 1999Micron Technology, Inc.Data transfer in a memory device having complete row redundancyUS5973978 *Aug 28, 1998Oct 26, 1999Micron Technology, Inc.Anti-fuse programming pathUS5995422Nov 17, 1995Nov 30, 1999Samsung Electronics Co., Ltd.Redundancy circuit and method of a semiconductor memory deviceUS6016265Dec 10, 1998Jan 18, 2000Kabushiki Kaisha ToshibaFuse-latch circuit having high integration densityUS6026036Dec 16, 1998Feb 15, 2000Mitsubishi Denki Kabushiki KaishaSynchronous semiconductor memory device having set up time of external address signal reducedUS6040999Oct 20, 1997Mar 21, 2000Sharp Kabushiki KaishaSemiconductor memory deviceUS6084807Nov 8, 1999Jul 4, 2000Choi; Jin H.Memory device with global redundancyUS6141286Aug 21, 1998Oct 31, 2000Micron Technology, Inc.Embedded DRAM architecture with local data drivers and programmable number of data read and data write linesUS6141287Sep 16, 1998Oct 31, 2000Infineon Technologies AgMemory architecture with multilevel hierarchyUS6141288May 19, 1999Oct 31, 2000Kabushiki Kaisha ToshibaSemiconductor memory device allowing change of refresh mode and address switching method therewithUS6144604Nov 12, 1999Nov 7, 2000Haller; Haggai HaimSimultaneous addressing using single-port RAMsUS6154413Apr 5, 1999Nov 28, 2000Longwell; Michael L.Method for designing a memory tile for use in a tiled memoryUS6157585Jun 30, 1999Dec 5, 2000Hyundai Electronics Industries Co., Ltd.Redundancy circuit and method of ferroelectric memory deviceUS6163495Sep 17, 1999Dec 19, 2000Cypress Semiconductor Corp.Architecture, method(s) and circuitry for low power memoriesUS6166942Jan 14, 2000Dec 26, 2000Micron Technology, Inc.Embedded DRAM architecture with local data drivers and programmable number of data read and data write linesUS6166986Jun 28, 1999Dec 26, 2000Hyundai Electronics Industries Co., Ltd.Semiconductor memory deviceUS6166989Mar 3, 1999Dec 26, 2000Mitsubishi Denki Kabushiki KaishaClock synchronous type semiconductor memory device that can switch word configurationUS6167540Jan 27, 1998Dec 26, 2000Nec CorporationSemiconductor memory device and redundant address selection method thereforUS6169701Oct 7, 1997Jan 2, 2001Fujitsu LimitedSemiconductor memory device using shared sense amplifier systemUS6172929Jun 25, 1999Jan 9, 2001Micron Technology, Inc.Integrated circuit having aligned fuses and methods for forming and programming the fusesUS6173379May 14, 1996Jan 9, 2001Intel CorporationMemory device for a microprocessor register file having a power management scheme and method for copying information between memory sub-cells in a single clock cycleUS6411557Feb 2, 2001Jun 25, 2002Broadcom CorporationMemory architecture with single-port cell and dual-port (read and write) functionality* Cited by examinerNon-Patent CitationsReference1Kiyoo Itoh et al., Trends in Low-Power RAM Circuit Technologies, Proceedings of the IEEE, vol. 83, No. 4, pp. 524-543, Apr. 1995.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8164362Mar 8, 2004Apr 24, 2012Broadcom CorporationSingle-ended sense amplifier with sample-and-hold referenceClassifications U.S. Classification365/200, 365/225.7, 365/189.05, 365/233.1International ClassificationG11C7/00, G11C7/06Cooperative ClassificationG11C7/06, G11C29/848, G11C5/04European ClassificationG11C29/848, G11C7/06Legal EventsDateCodeEventDescriptionApr 28, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google