Source: http://www.google.com/patents/US20080182526?dq=7,328,163
Timestamp: 2014-08-27 19:19:03
Document Index: 141797603

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No, 60']

Patent US20080182526 - Adaptive radio transceiver with an antenna matching circuit - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including...http://www.google.com/patents/US20080182526?utm_source=gb-gplus-sharePatent US20080182526 - Adaptive radio transceiver with an antenna matching circuitAdvanced Patent SearchPublication numberUS20080182526 A1Publication typeApplicationApplication numberUS 12/048,858Publication dateJul 31, 2008Filing dateMar 14, 2008Priority dateOct 21, 1999Also published asUS6738601, US6917789, US6920311, US6987966, US7116945, US7130579, US7233772, US7349673, US7356310, US7389087, US7697900, US7756472, US8023902, US8116690, US20040195917, US20050153664, US20050186925, US20070049205, US20070285154, US20080191313, US20080290966, US20100255792Publication number048858, 12048858, US 2008/0182526 A1, US 2008/182526 A1, US 20080182526 A1, US 20080182526A1, US 2008182526 A1, US 2008182526A1, US-A1-20080182526, US-A1-2008182526, US2008/0182526A1, US2008/182526A1, US20080182526 A1, US20080182526A1, US2008182526 A1, US2008182526A1InventorsShervin Moloudi, Ahmadreza Rofougaran, Maryam RofougaranOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManReferenced by (13), Classifications (54), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetAdaptive radio transceiver with an antenna matching circuitUS 20080182526 A1Abstract An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
CROSS-REFERENCE TO RELATED APPLICATION The present application is a continuation of co-pending patent application Ser. No. 09/634,552, filed Aug. 8, 2000, priority of which is hereby claimed under 35 U.S.C. � 120. The present application also claims priority under 35 U.S.C. � 119(e) to provisional Application Nos. 60/160,806, filed Oct. 21, 1999; Application No. 60/163,487, filed Nov. 4, 1999; Application No. 60/163,398, filed Nov. 4, 1999; Application No. 60/164,442, filed Nov. 9, 1999; Application No. 60/164,194, filed Nov. 9, 1999; Application No. 60/164,314, filed Nov. 9, 1999; Application No. 60/165,234, filed Nov. 11, 1999; Application No. 60/165,239, filed Nov. 11, 1999; Application No. 60/165,356; filed Nov. 12, 1999; Application No. 60/165,355, filed Nov. 12, 1999; Application No. 60/172,348, filed Dec. 16, 1999; Application No. 60/201,335, filed May 2, 2000; Application No. 60/201,157, filed May 2, 2000; Application No. 60/201,179, filed May 2, 2000; Application No. 60/202,997, filed May 2, 2000; Application No, 60/201,330, filed May 2, 2000. All these applications are expressly incorporated herein by referenced as though fully set forth in full.
V OI = A  ( 1 + j   RC   ω )  V II + 2  QV IQ ( 1 + j   RC   ω ) 2 + 4  Q 2   and ( 1 ) V OQ = A  - 2  QV II + ( 1 + j   RC   ω )  V IQ ( 1 + j   RC   ω ) 2 + 4  Q 2 ( 2 ) FIG. 7 shows the frequency response for the complex biquad filter.
H  ( jω ) = V o V I  ( j   ω ) = A 1 + j   RC   ω - j2   Q ( 3 ) This shows a passband gain of A 122 at a center frequency of 2Q/RC 124, with a 3-dB bandwidth of 2RC 126. Thus, the quality factor of the second-order stage will be Q. For the image signal however, the signal at the I branch leads, and as a result:
H  ( jω ) = A 1 + j   RC   ω + j2   Q ( 4 ) which shows that the image located at 2Q/RC is rejected by
jω - j  ( ω - ω 0 ) BW ( 5 ) where ω0 is the bandpass (BP) center frequency, and BW is the lowpass (LP) equivalent bandwidth, equal to half of the bandpass filter bandwidth. For instance, for a second-order biquad stage (as shown in FIG. 6), ω0=2Q/RC, and BW=1/RC. The biquad stage is designed by finding its LP equivalent frequency response using equation (5). Once the LP poles are known, the BP poles are calculated based on equation (5). Assume that the LP equivalent has n poles, and pi,Lp=αi+jβi is the ith pole. From equation (5), the BP pole will be:
α i � BW = - 1 RC   and ( 7 ) ω o + β i � BW = 2   Q RC ( 8 ) Since the LP equivalent poles are located in the left-half plane, ai is always negative. The above equations set the value of Q and RC in each stage. The gain of each biquad stage can be adjusted based on the desired gain in the complex filter, and noise-linearity trade-off: increasing the gain of one biquad stage lowers the noise contributed by the following biquad stages, but it also degrades the linearity of the complex filter.
jω - j  ( ω 2 - ω 0 2 ) BW � ω ( 9 ) This symmetric response in the biquad stage ensures a uniform group delay across the data band.
H   ( j   ω ) = R � Y i 1 + j   RC   ω - j2   Q ( 10 ) FIG. 8 shows Yi having resistor Rz 128 and capacitor Cz 130.
Y i = 1 R z + jω   C z ( 11 ) which is not desirable, since the zero will be in the left-half plane, rather than the j ω axis.
Y l = 1 V = 1 R z - C z  ω ( 13 ) which indicates that the filter will have a zero equal to 1/RzCz at the jω axis
H  ( jω ) = A   1 - RC z A  ω 1 + j   RC   ω - j2   Q ( 14 ) Equation (14) is analogous to equation (3), with the difference that now a zero at A/RCz is added to the biquad stage of the complex filter. By knowing the LP equivalent characteristics of the biquad stage, the poles are calculated based on equation (6). The value of Q and RC in each biquad stage is designed by using equation (7) and equation (8). If the normalized LP zeros are at �ωz,LP, then the biquad stage should be realized with two biquad stages cascoded, and the frequency of zeros in the biquad stages will be (equation (5)):
ωz1,2=ω0�ωz,LD �BW (15)
Referring to FIG. 12( b), each resistor can be implemented with a series of switchable resistors 158, 160, 162, 164, 166. Resistor 166 provides a resistance of Ru Resistor 164 provides a resistance of 2 Ru. Resistor 162 provides a resistance of 4 Ru. Resistor 160 provides a resistance of 8 Ru. Resistor 158 provides a resistance of 16 Ru. In the described exemplary embodiment, the resistance can be varied between Ru and 31�Ru in incremental steps equal to Ru by selectively bypassing the resistor based on a five-bit binary code.
H  ( j   ω ) = n F n A 1 + j   n c  n F  R u  C u  ω - j   n F n Q ( 16 ) Therefore, the biquad stage gain (A), center frequency (ω0), and bandwidth (BW) will be equal to:
A = n F n A ( 17 ) ω 0 = 1 n C  n Q � ω u ( 18 ) BW = 1 n C  n F � ω u ( 19 ) The above equations show that the characteristics of the biquad stage is independently programmed by varying nA, nF, and nQ. For instance, by setting nF, the gain of the biquad stage changes from nF/31 to nF by changing nA from 1 to 31
Ideal   Dynamic   Range = 20   log   S S A n  20   log   A n = 20  ( n )  log   A ( 22 ) However, in the case of a large amount of gain, the input level will be limited with the input noise and the dynamic range will also be limited to:
Dynamic   Range =  20   log   S σ n σ n =  total   noise   rms σ n =  ( BW ) � Noise   Factor ( 23 ) If each differential amplifier has the same input dynamic range VL and each full-wave rectifier has similar input dynamic range Vi, then the dynamic range of the logarithmic differential amplifier and the total RSSI circuitry are the same.
Max   RSSI - Min   RSSI = C   log   A 2   n ( 29 ) Δ   RSSI = C   log   A 2   n ( 30 ) C = Δ   RSSI 2  n   log   A ( 31 ) ( Ideal )  RSSI = Δ   RSSI 2  n   log   A  log   V in 2 ( 32 ) To find the relation between the gain of a differential amplifier, the gain of a rectifier, and the maximum input range of the combined differential amplifier and the rectifier, the RSSI will be calculated for the two consecutive differential amplifier and rectifier combinations (see equations (33) and (34)) for both ideal RSSI equations (32) and approximated RSSI equation (27):
V in   1 = S ( A ) n - m ( 33 ) V in   2 = S ( A ) n - m - 1 ( 34 ) ( Ideal )  RSSI 2 - RSSI 1 = log   ( A ) 2 ( 35 ) ( Approximated )  RSSI 2 - RSSI 1 = β 2  S 2 ( 36 ) Therefore,
RSSI = 1 ( A   β ) 2 - 1  ( A   β ) 2  ( n - m )  V in 2 + m   Δ   RSSI n ; S A n - m < V in < S A n - m - 1 ( 39 ) FIG. 16( a) shows a schematic diagram for an exemplary embodiment of the differential amplifier used in the type II core amplifier. The differential input signal is fed to the gates of transistor amplifiers 955, 957. The amplified differential output signal is provided at the drains of the transistor amplifiers 955, 957. The gain of the transistor amplifiers is set by load transistors 958, 860, each connected between the drain of one of the transistor amplifiers and a power source. More particularly, the gain of the differential amplifier is determined by the ratio of the square root of transistor amplifiers-to-load transistors.
Gain  ( A ) =  w in w in =  200 6 ≈ 5.8 ( 40 ) The sources of the transistor amplifiers 955, 957 are connected in common and coupled to a constant current source transistor 952. In the described exemplary embodiment, the controller provides the bias to the gate of the transistor 952 to set the current.
if    Δ   I SQM   1 =  ( I D   1 + I D   4 ) - ( I D   2 + I D   3 ) =  2  ( I DC + I SC ) =  2   k - 1 k + 1  I o - 4  k  ( k - 1 )  β N ( k + 1 ) 2  V I 2 ( 41 ) The input dynamic range of the full rectifier is then:
β 2  S 2 = 4  k  ( k - 1 )  β N ( k + 1 ) 2  V l 2  R L ( 43 ) By plugging the Vi from equation (42) and replacing β2S2 from equation (38), the following relation is obtained:
Because of the hard switching action of the buffers, the mixers will effectively be switched by a square-wave signal. Thus, the divider output will be upconverted by the main harmonic of VCO (f1), as well as its odd harmonics (n�f1), with a conversion gain of 1/n. In addition, at the input of the mixer, because of the nonlinearity of the mixers, and the buffers preceding the mixers, all the odd harmonics of the input signals to the mixers will exist. Even harmonics, both at the LO and the input of the mixers can be neglected if a fully balanced configuration is used. Therefore, all the harmonics of VCO (n�f1) will mix with all the harmonics of input (m�f2), where f2 is equal to f1/N. Because of the quadrature mixing, at each upconversion only one sideband appears at the mixer output. Upper or lower sideband rejection depends on the phase of the input and LO at each harmonic. For instance, for the main harmonics mixed with each other, the lower sideband is rejected, whereas when the main harmonic of the VCO mixes with the third harmonic of the divider output signal, the upper sideband is rejected. Table 1 gives a summary of the cross-modulation products up to the 5th hannonic of the VCO and input. In each product, only one sideband is considered, since the other one is attenuated due to quadrature mixing, and is negligible.
 H  ( f )  = f Q   f 0 [ 1 - ( f f 0 ) 2 ] 2 + ( f Q   f 0 ) 2 ( 49 ) The following discussion changes based on the Q value. Considering a Q of about 5 for the inductor, with f0=1.5f1, the spur located at 2.5f1 is rejected by about 15 dB by each LC circuit. This spur is produced at the LO generator output due to the mixing of the VCO third harmonic (at 3f1) with the divider output (at 0.5f1). This signal is attenuated by 10 dB since the third harmonic of a square-wave is one third of the main harmonic, 15 dB at the LC resonator at the mixers output tuned to 1.5f1, and another 15 dB at the output of the buffers (900, 902 in FIG. 33). This gives a total rejection of 40 dB. When applied to the mixers in the transmitter, this LO generator output will upconvert the baseband data to 2.5f1. With LC filters (not shown) positioned at the upconversion mixers and PA output in the transmitter, another 15+15=30 dB rejection is obtained (FIG. 33).
V out_  1 = - Sin  ( θ 2 ) � Sin  ( ( ω 1 - ω 2 )  t + θ 2 ) + Cos  ( θ 2 ) � Cos  ( ( ω 1 + ω 2 )  t + θ 2 )   and ( 52 ) V out_Q = - Sin  ( θ 2 ) � Cos  ( ( ω 1 - ω 2 )  t + θ 2 ) + Cos  ( θ 2 ) � Sin  ( ( ω 1 + ω 2 )  t + θ 2 ) ( 53 ) The above equations show that regardless of the value of θ, the outputs are always in quadrature. However, other effects should be evaluated. First, a spur at ω1-ω2=0.5 ω1 is produced at the output. This spur can be attenuated by 2�22=44 dB by the LC filters at the mixer and its buffer outputs. Thus, for 60 dB rejection, the single sideband mixers need to provide an additional 16 dB of rejection (about 0.158). Based on equation (53), tan(θ/2)=0.158, or θ≈18�, phase accuracy of better than 18� can generally be achieved. Second, phase error at the VCO output lowers the mixer gain (term Cos(θ/2) in equation (52) or (53)). For a phase error of 18�, the gain reduction is, however, only 0.1 dB, which is negligible. For θ=90� (a single-phase VCO), both sidebands are equally upconverted at the mixer output. However, the LC filters reject the lower sideband by about 44 dB. The mixer gain will also be 3 dB lower. This will slightly increase the power consumption of the LO generator. If θ=180� (the VCO I and Q outputs are switched), the lower sideband is selected, and the desired sideband is completely rejected.
V out_I = - Sin  ( θ 1 - θ 2 2 ) � Sin  ( ( ω 1 - ω 2 )  t + θ 1 - θ 2 2 ) + Cos  ( θ 1 + θ 2 2 ) � Cos  ( ( ω 1 + ω 2 )  t + θ 1 + θ 2 2 )   and  ( 54 ) V out_Q = - Sin  ( θ 1 + θ 2 2 ) � Cos  ( ( ω 1 - ω 2 )  t + θ 1 - θ 2 2 ) + Cos  ( θ 1 - θ 2 2 ) � Sin  ( ( ω 1 + ω 2 )  t + θ 1 + θ 2 2 ) ( 55 ) This shows that the outputs still have phases of 0 and 90�, but their amplitudes are not equal. The amplitude imbalance is equal to:
Δ   A A = 2  Cos  ( θ 1 + θ 2 2 ) - Cos  ( θ 1 - θ 2 2 ) Cos  ( θ 1 + θ 2 2 ) + Cos  ( θ 1 - θ 2 2 ) = 2   tan  ( θ 1 2 ) � tan  ( θ 2 2 ) ( 56 ) If θ1 and θ2 are small and have an equal standard deviation, that is, the phase errors in the VCO and divider are the same in nature, then the output amplitude standard deviation will be:
Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8019289Mar 27, 2009Sep 13, 2011Rfaxis, Inc.Radio frequency transceiver front end circuit with matching circuit voltage dividerUS8073400Apr 22, 2009Dec 6, 2011Rfaxis, Inc.Multi mode radio frequency transceiver front end circuitUS8073401Apr 22, 2009Dec 6, 2011Rfaxis, Inc.Multi mode radio frequency transceiver front end circuit with inter-stage matching circuitUS8078119Apr 22, 2009Dec 13, 2011Rfaxis, Inc.Multi mode radio frequency transceiver front end circuit with inter-stage power dividerUS8135355Mar 27, 2009Mar 13, 2012Rfaxis, Inc.Radio frequency transceiver front end circuit with parallel resonant circuitUS8140025Mar 27, 2009Mar 20, 2012Rfaxis, Inc.Single input/output port radio frequency transceiver front end circuit with low noise amplifier switching transistorUS8175541Mar 26, 2009May 8, 2012Rfaxis, Inc.Radio frequency transceiver front end circuitUS8265567Mar 27, 2009Sep 11, 2012Rfaxis Inc.Single input/output port radio frequency transceiver front end circuitUS8301084Mar 27, 2009Oct 30, 2012Rfaxis, Inc.Radio frequency transceiver front end circuit with direct current bias switchUS8325632Jul 7, 2009Dec 4, 2012Rfaxis, Inc.Multi-channel radio frequency front end circuit with full receive diversity for multi-path mitigationUS8467738May 3, 2010Jun 18, 2013Rfaxis, Inc.Multi-mode radio frequency front end moduleUS8483627May 5, 2009Jul 9, 2013Texas Instruments IncorporatedCircuits, processes, devices and systems for full integration of RF front end module including RF power amplifierWO2010096071A1 *Apr 27, 2009Aug 26, 2010Rfaxis, Inc.Multi mode radio frequency transceiver front end circuit* Cited by examinerClassifications U.S. Classification455/78International ClassificationH03H21/00, H04B1/38, H03H11/12Cooperative ClassificationH03F2203/45138, H03G3/001, H04B17/0012, H03G11/00, H03H2011/0494, H03L7/18, H03J2200/10, H03H21/0012, H03B21/01, H03F3/45475, H03H21/0001, H03F2200/336, H04B17/0027, H03L7/099, H03B27/00, H03F2203/45526, H03H11/344, H03F2200/451, H03F3/19, H03H11/22, H03H7/42, H03F1/56, H03F2203/45528, H03H11/1291, H03F3/245, H03F3/45179, H04B17/0037, H03F2200/318, H03F2203/45638, H03F2203/45386European ClassificationH04B17/00A2S, H04B17/00A3S, H04B17/00A1T, H03H7/42, H03F3/24B, H03L7/18, H03F3/45S1B, H03G3/00D, H03F3/45S1K, H03B21/01, H03L7/099, H03H11/34D, H03B27/00, H03F3/19, H03G11/00, H03H11/22, H03F1/56, H03H11/12F, H03H21/00B, H03H21/00ALegal EventsDateCodeEventDescriptionOct 15, 2013FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google