Source: https://patents.google.com/patent/US9123572
Timestamp: 2018-03-17 22:17:53
Document Index: 447876934

Matched Legal Cases: ['Application No. 60', 'Application No. 102136776', 'Application No. 05743122', 'Application No. 05743122', 'Application No. 08772785', 'Application No. 08772785', 'Application No. 2007', 'Application No. 2010', 'Application No. 2010', 'Application No. 10', 'Application No. 10', 'Application No. 097121479']

US9123572B2 - Anti-fuse memory cell - Google Patents
Anti-fuse memory cell
US9123572B2
US9123572B2 US14244499 US201414244499A US9123572B2 US 9123572 B2 US9123572 B2 US 9123572B2 US 14244499 US14244499 US 14244499 US 201414244499 A US201414244499 A US 201414244499A US 9123572 B2 US9123572 B2 US 9123572B2
US14244499
US20140209989A1 (en )
An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide is formed by depositing a first oxide over a channel region of the anti-fuse memory cell, removing the first oxide in a thin oxide area of the channel region, and then thermally growing a second oxide in the thin oxide area. The remaining first oxide defines a thick oxide area of the channel region. The second oxide growth occurs under the remaining first oxide, but at a rate less than thermal oxide growth in the thin oxide area. This results in a combined thickness of the first oxide and the second oxide in the thick oxide area being greater than second oxide in the thin oxide area.
This application is a continuation in part of U.S. application Ser. No. 13/662,842, filed on Oct. 29, 2012, which is a continuation in part of U.S. application Ser. No. 13/219,215, filed on Aug. 26, 2011, now issued as U.S. Pat. No. 8,313,987 on Nov. 20, 2012, which is a continuation of U.S. patent application Ser. No. 12/814,124, filed on Jun. 11, 2010, now issued as U.S. Pat. No. 8,026,574 on Sep. 27, 2011, which is a continuation of U.S. patent application Ser. No. 11/762,552 filed on Jun. 13, 2007 now issued as U.S. Pat. No. 7,755,162 on Jul. 13, 2010, which is a continuation in part of U.S. patent application Ser. No. 10/553,873 filed on Oct. 21, 2005, now U.S. Pat. No. 7,402,855 issued Jul. 22, 2008, which is a national stage entry of PCT Serial No. CA2005/000701 filed on May 6, 2005, which claims priority to U.S. Provisional Patent Application No. 60/568,315 filed on May 6, 2004, all of which are incorporated herein by reference.
U.S. Pat. No. proposed an nmos anti-fuse built in an isolated P-well using a standard Deep N-Well process. Another variant of Deep N-Well based anti-fuses is disclosed in U.S. Pat. No. 6,611,040.
U.S. Patent Publication No. 20040004269 disclosed an anti-fuse built from a MOS transistor having gate connected to the gate of a capacitor, degenerated by a thinner gate oxide and heavy doping under the channel through additional implantation (a diode). The rupture voltage is applied to a bottom plate of the capacitor.
U.S. Patent Application Publication No. 20060292755 (Parris) introduces a well-to-gate capacitor as an anti-fuse element having a tunable, variable gate oxide thickness formed through a thermal oxide process, in an attempt to increase reliability in programming of the anti-fuse element, by localizing the area of oxide breakdown (or rupture). The state of the Parris anti-fuse capacitor is detected by sensing a current in the well, that flows from its top plate through a programmed conductive link in the oxide breakdown region, and into the well which acts as the bottom plate. Hence the Parris anti-fuse capacitor does not function as a transistor since it does not have “channel” region. Because of the well sensing scheme, Parris teaches that each anti-fuse capacitor is formed in an isolated well, while the corresponding access transistors are formed outside of the well. Such a design would not be suited for high density applications since the access transistors must be spaced from the well according to minimum design rule requirements. Thus the Parris memory array has low area efficiency.
In a first aspect, there is provided a method of forming a variable thickness gate oxide for an anti-fuse transistor. The method includes growing a first oxide in a channel region of the anti-fuse transistor; removing the first oxide from a thin oxide area of the channel region; thermally growing a second oxide in the thin oxide area and in a thick gate oxide area of the channel region under the first oxide, and a combination of the first oxide and the second oxide in the thick gate oxide area has a thickness greater than the second oxide in the thin oxide area; and forming a diffusion region adjacent the thick oxide area for receiving current from the channel region. According to one embodiment of the first aspect, the second oxide under the first oxide is thinner than the second oxide in the thin oxide area. According to another embodiment of the first aspect, the method further includes forming a bitline contact in electrical contact with the diffusion region for sensing a current from the common gate when a conductive link is formed between the channel and the common gate.
In yet another embodiment of the first aspect, thermally growing includes growing the second oxide in the thin oxide area at a first rate and growing the second oxide in the thick gate oxide area at a second rate less than the first rate. In this embodiment, growing the second oxide in the thin oxide area at a first rate includes consuming a substrate surface of the thin oxide area to a first depth, and growing the second oxide in the thick gate oxide area includes consuming a substrate surface of the thick gate oxide area to a second depth less than the first depth. Thermally growing can further include forming an angled oxide area between the thick gate oxide area and the thin gate oxide area, where the angled oxide area has a thickness different from the combination of the first oxide and the second oxide in the thick gate oxide area, and from the second oxide in the thin oxide area. In this embodiment, the method further includes forming a common gate over the first oxide the second oxide, and the angled oxide area.
In a second aspect, there is provided an anti-fuse memory cell having a variable thickness gate oxide. The anti-fuse memory cell includes a channel region in a substrate, a first oxide, a second oxide, a diffusion region, isolation, and a gate over the first oxide and the second oxide. The first oxide is formed in a thick oxide area of the channel region. The second oxide is formed in a thin oxide area of the channel region and in the thick oxide area underneath the first oxide. The diffusion region is adjacent to the thick oxide area for receiving current from the channel region. The isolation is adjacent to the thin gate oxide area. The gate is formed over the first oxide and the second oxide.
According to an embodiment of the second aspect, the second oxide under the first oxide is thinner than the second oxide in the thin oxide area, and a combination of the first oxide and the second oxide in the thick oxide area has a thickness greater than the second oxide in the thin oxide area. In this embodiment, the second oxide in the thin oxide area extends into the substrate to a first depth, and the second oxide in the thick oxide area extends into the substrate to a second depth less than the first depth.
According to another embodiment of the second aspect, the anti-fuse memory cell further includes an angled oxide area between the thick gate oxide area and the thin gate oxide area, where the angled oxide area has a thickness different from the combination of the first oxide and the second oxide in the thick gate oxide area, and different from the second oxide in the thin oxide area.
In a further embodiment of the secont aspect, the gate is connected to a wordline and the diffusion region is connected to a bitline. Alternately, the anti-fuse memory cell includes an access transistor adjacent to the diffusion region, and another diffusion region adjacent to the access transistor, and the another diffusion region is connected to a bitline. In this particular embodiment, the access transistor has a gate oxide thickness corresponding to the combination of the first oxide and the second oxide in the thick gate oxide area.
FIG. 5A is a planar layout of the anti-fuse transistor of FIG. 4;
FIG. 5B is a planar layout of the anti-fuse transistor of FIG. 4 showing an alternate OD2 mask configuration;
FIG. 7A-7C illustrate the formation of the variable thickness gate oxide in accordance with steps of the flow chart of FIG. 6;
FIG. 8A-8C illustrate an alternate formation method of the variable thickness gate oxide;
FIG. 9 is a magnified illustration of the variable thickness gate oxide shown in FIG. 8C;
FIG. 10 is a cross sectional view of an anti-fuse transistor memory cell fabricated according to the alternate fabrication method shown in FIGS. 8A-8C;
FIG. 11A is a planar layout of an anti-fuse transistor according to an embodiment of the present invention;
FIG. 11B is a cross-sectional view of the anti-fuse transistor of FIG. 11A taken along line A-A;
FIG. 12 is an enlarged planar layout of the anti-fuse transistor of FIG. 11A;
FIG. 13 is a planar layout of a memory array using the anti-fuse transistor of FIG. 11A according to an embodiment of the present invention;
FIG. 14 is an enlarged planar layout of an anti-fuse transistor, according to another embodiment of the present invention;
FIG. 15 is a planar layout of a memory array using the anti-fuse transistor of FIG. 14 according to an embodiment of the present invention;
FIG. 16A is a planar layout of a two-transistor anti-fuse memory cell according to an embodiment of the present invention;
FIG. 16B is a cross-sectional view of the two-transistor anti-fuse memory cell of FIG. 16A taken along line B-B;
FIG. 16C is a cross-sectional view of an alternate two-transistor anti-fuse memory cell formed using a thermal oxide process;
FIG. 17 is a planar layout of a memory array using the two-transistor anti-fuse memory cell of FIGS. 16A and 16B, according to an embodiment of the present invention;
FIG. 18 is a planar layout of a memory array using the two-transistor anti-fuse memory cell according to an alternate embodiment of the present invention;
FIG. 19-23 are planar layouts of alternate anti-fuse memory cells, according to embodiments of the present invention; and
FIG. 24-27 are planar layouts of alternate two-transistor anti-fuse memory cells, according to embodiments of the present invention.
A method of creating a variable thick gate oxide from a standard CMOS process according to an embodiment of the present invention, is to utilize a well known two-step oxidation process. A flow chart outlining this process is shown in FIG. 6, while FIGS. 7A-7C show the various stages of the variable thickness gate oxide formation corresponding to specific steps in the process.
First, an intermediate gate oxide is grown in all active areas determined by the OD mask in step 200. In FIG. 7A, this is shown as the formation of intermediate gate oxide 300 on the substrate, over the channel region 302. In following step 202, the intermediate gate oxide 300 is removed from all the designated thin gate oxide areas using an OD2 mask. FIG. 7B shows the remaining portion of intermediate gate oxide 300 and the future thin oxide area 304. In the last gate oxide formation step 204, a thin oxide is grown again in all active areas as originally defined by the OD mask. In FIG. 7C, the thin gate oxide 306 is grown over the intermediate gate oxide 300 and the thin oxide area 304. In the present embodiment, the thick gate oxide is formed by a combination of removing intermediate gate oxide and growing thin gate oxide over the remaining intermediate gate oxide.
In the process of FIG. 6, a thin oxide is grown over the substrate and intermediate gate oxide 300 in step 204, as shown in FIG. 7C. In an alternate method for forming a dual thickness gate oxide, the thin oxide is thermally grown from the substrate surface. Thermal oxide growth is known in the art, as demonstrated by previously mentioned U.S. Patent Application Publication No. 20060292755, which uses a thermal oxide growth process to form the gate oxide. This alternate method is described with reference to the flow chart of FIG. 6 and FIGS. 8A-8C that show the various stages of the variable thickness gate oxide formation corresponding to specific steps in the process.
The first step is the same as previously described, where an intermediate gate oxide is grown in all active areas determined by the OD mask in step 200. In FIG. 8A, this is shown as the formation of intermediate gate oxide 310 on the substrate, over the channel region 312. In following step 202, the intermediate gate oxide 310 is removed from all the designated thin gate oxide areas using an OD2 mask. FIG. 8B shows the remaining portion of intermediate gate oxide 310 and the future thin oxide area 314. It is noted in FIG. 8B that the vertical edge on the right side of intermediate gate oxide 310 may be “undercut” during removal of the intermediate gate oxide 310 from thin oxide area 314 during a wet etching process. In the last gate oxide formation step 204, a thin oxide is thermally grown in the entire channel region 312 of the cell. Thermal oxide growing is a process known in the art, where oxygen atoms combine with silicon atoms of the substrate to form silicon dioxide. The silicon dioxide molecules grow on the surface of the substrate, and each successive layer of silicon dioxide molecules “pushes” previously grown layers upwards. Because this silicon dioxide growth mechanism requires oxygen to reach the silicon substrate surface, its growth rate will be affected by intervening structures which slow the oxygen atoms from reaching the substrate surface.
While anti-fuse transistors can have thin gate oxides formed using this process, any other transistors outside of the memory array can have their gate oxides formed at the same time, meaning that they would have the same gate oxide thickness as the thin oxide formed in step 204. These transistors can be core transistors, typically used in logic circuits or any other circuits where low voltages and high speed operation are desired.
FIG. 8C shows the result of thermally growing oxide in the channel region 312. In FIG. 8C, the thermally grown oxide is shown as thermal oxide 316, which has “pushed” or displaced the intermediate gate oxide 310 upwards and away from the substrate surface 318. Because of the presence of intermediate gate oxide 310 previously formed on substrate surface 318 in FIG. 8A, the growth rate of thermal oxide 316 under intermediate gate oxide 310 is slower than on the exposed portion of substrate surface 318 of FIG. 8B. For this reason, thermal oxide 316 has a thicker portion and a thinner portion. It is noted that the thermal oxide growing process consumes some of the substrate, thereby resulting in a substrate surface having different surface levels. This effect is also referred to as “silicon loss” during a thermal oxidation process. In other words, the substrate surface does not have a uniform surface level in the memory cell area. In the present embodiments, there are portions of thermal oxide 316 formed beneath the surrounding substrate surface 318.
FIG. 9 is a magnified illustration of the variable thickness gate oxide shown in FIG. 8C. In FIG. 9, three different regions of the variable thickness gate oxide are identified. Starting from the left side of the channel region is the thick gate oxide area 320, followed by an oxide angled area 322, which is followed by a thin gate oxide area 324. While oxide angled area 322 is shown to be distinct from thick gate oxide area 320, oxide angled area 322 can be considered as a part of thick gate oxide area 320. This is because both areas 320 and 322 are heterogeneous layers having thicknesses consisting of a combination of the intermediate gate oxide 310 and thermal oxide 316. In contrast, thin gate oxide area 324 is a homogeneous layer of thermal oxide 316. The thick gate oxide area 320 when combined with an overlying polysilicon gate or other conductive gate, forms an access transistor positioned in series with the anti-fuse device. The anti-fuse device is described in further detail below.
The thick gate oxide area 320 is the combined thicknesses of the thinner portion of the thermal oxide 316 and the intermediate gate oxide 310 shown in FIG. 8C. The thin gate oxide area 324 is the thicker portion of the thermal oxide 316 in thin oxide area 314 shown in FIG. 8C. The oxide angled area 322 is a transition area between the thick gate oxide area 320 and the thin gate oxide area 324 and may have a thickness different from both the thick gate oxide area 320 and the thin gate oxide area 324. In particular, the oxide angled area 322 is characterized as being thinner than the thick gate oxide area 320, but thicker than the thin gate oxide area 324. Furthermore, the thickness of oxide angled area 322 is variable along the entire oxide angled area 322, meaning that the thickness is not constant between the top sloping edge of oxide angled area 322 and the bottom edge of oxide angled area 322 that consists of substantially horizontal segments on either side of a sloping segment. During programming, a conductive link can be formed in the angled area 322 or the thin gate oxide area 324. Therefore, angled area 322 and thin gate oxide area 324 are considered the anti-fuse device of the anti-fuse memory cell. The thick gate oxide of the variable thickness gate oxide is characterized by having the substantially the same thickness 326, while the thin gate oxide of the variable thickness gate oxide is characterized by having the substantially the same thickness 328. The oxide angled area 322 is characterized by being angled relative to the thick gate oxide area 320 and the thin gate oxide area 324, and has a thickness 330 that differs from both thicknesses 326 and 328.
It is noted that transistors requiring thick gate oxides outside of the memory array can be formed at the same time the thick gate oxide area 320 is formed by thermal oxide growth. Such transistors can include input/output transistors that typically operate at voltages higher than core transistors. Therefore, core transistors and input/output transistors of the memory device can be formed during formation of the anti-fuse memory cell transistors in the memory array. Obvious cost advantages are realized since the same mask set used for forming the memory array anti-fuse memory cells is also used to form the core transistors and the input/output transistors, or vice versa.
The oxide angled area 322 is characterized by having a variable thickness that has a maximum thickness at the virtual interface between thick gate oxide area 320 and oxide angled area 322, which decreases to have a minimum thickness at the virtual interface between the oxide angled area 322 and the gate oxide area 324. The channel region 312 is therefore located at different depths relative to the substrate surface 318 due to the different thermal oxide growth rates and the consumption of the substrate surface 318. As shown in FIG. 9, the thick gate oxide area 320 has a bottom side formed at a depth “a” from substrate surface 318, while thin gate oxide area 324 has a bottom side formed at depth “b” from substrate surface 318. It is generally known that if a bare silicon surface is oxidized, less than half of the oxide thickness will lie below the original surface, and just more than half will be above it. For example, some empirical measurements have approximated that about 46% of the total oxide thickness lies below the original surface, while the remaining 54% lies above the original surface. Relative to the bottom side of thick gate oxide area 320, the bottom side of thin gate oxide area 324 extends to a further depth “c” into the substrate. Within the oxide angled area 322, the channel is angled at region 332. Therefore, the depth of “b” of the thin gate oxide area 324 is approximately “a”+“c”.
One advantage of using a thermal oxide process to fabricate the variable thickness gate oxide shown in FIG. 9 is the angled channel resulting from oxide angled area 322. The distribution of an electrical field resulting from a voltage applied to an overlying polysilicon gate (not shown) is more dense at curves and corners, which enhances oxide breakdown in those areas, when compared to a “flat” channel region.
It is noted that the relative thicknesses of the oxides shown in FIGS. 8A to 8C are not to scale, as the illustrations are meant to show the general fabrication principles at work. In experimental fabricated anti-fuse memory devices using the presently described method, the combined thinner portion of the thermal oxide 316 and the intermediate gate oxide 310 has been measured to be about 65 angstroms, while the oxide in the thin oxide area 314 has been measured to be about 25 angstroms.
FIG. 10 is a cross sectional view of a fully fabricated anti-fuse transistor memory cell fabricated according to the alternate fabrication method shown in FIGS. 8A-8C. The anti-fuse memory cell 350 has a variable thickness gate oxide 352 similar to the one shown in FIG. 9, a gate 354 formed over the variable thickness gate oxide 352, sidewall spacers 356, a diffusion region 358 and STI oxide 360. Diffusion region 358 can have an LDD 362 and a bitline contact 364 connected to a bitline (not shown).
FIG. 11A shows a planar view of an anti-fuse transistor having a minimized thin gate oxide area that can be manufactured with any standard CMOS process, according to an embodiment of the present invention. For example, the fabrication steps outlined in FIG. 6 can be used, including the embodiment employing the thermal oxide fabrication steps. FIG. 11B shows a cross-sectional view of the anti-fuse transistor of FIG. 11A, taken along line A-A. Anti-fuse 400 of FIG. 11A is very similar to anti-fuse 100 shown in FIG. 5 a, except that the area of the thin gate oxide of the variable thickness gate oxide beneath the polysilicon gate is minimized. This is in stark contrast to the anti-fuse cell described by Parris, in which the thin gate oxide portion is maximized such that it surrounds the thick oxide portion in order to elongate the transition line between the thin and the thick oxide portions.
Anti-fuse transistor 400 includes a variable thickness gate oxide 402, formed on the substrate channel region 404, a polysilicon gate 406, sidewall spacers 408, a diffusion region 410, and an LDD region 412 in the diffusion region 410. The variable thickness gate oxide 402 consists of a thick oxide and a thin gate oxide such that a majority area of the channel length is covered by the thick gate oxide and a small minority area of the channel length is covered by the thin gate oxide. As shown in FIG. 11A, the thick gate oxide area 414 covers most of the active area 416 under polysilicon gate 406, except for a small square thin gate oxide area 418. If anti-fuse 400 is fabricated with the previously described alternate thermal oxide fabrication steps, then thin gate oxide area 418 corresponds to thin gate oxide area 324 of FIG. 9. This means that the oxide angled area 322 and thick gate oxide area 320 of FIG. 9 are located within thick gate oxide area 414 of FIG. 11A. Anti-fuse transistor 400 can be a non-volatile memory cell, and hence will have a bitline contact 420 in electrical contact with diffusion region 410. The formation of the shape and size of thick gate oxide area 414 and thin gate oxide area 418 is discussed in further detail below.
FIG. 12 is an enlarged planar view of the anti-fuse transistor of FIG. 11A to highlight the planar geometry of the variable thickness gate oxide. Anti-fuse transistor 500 consists of an active area 502 with overlying polysilicon gate 504. In FIG. 12, shading from the polysilicon gate has been removed to clarify the features underneath it. The variable thickness gate oxide is formed between the active area 502 and polysilicon gate 504, and consists of a thick gate oxide area 506. According to the present embodiment, thick gate oxide area 506 can be considered as at least two rectangular segments. Those skilled in the art will understand that the delineation of the segments is a visual breakdown of the thick gate oxide shape into constituent rectangular shapes. The first thick gate oxide segment 508 extends from a first end of the channel region, coinciding with the left-most edge of the polysilicon gate 504, to a second end of the channel region. Segment 508 can be seen as a rectangular shaped area having a width less than the width of the channel region. The second thick gate oxide segment 510 is adjacent to the first segment 508, and extends from the same first end of the channel region to a predetermined distance of the channel length. The second thick gate oxide segment 510 has a width substantially equal to the difference between the channel width and the width of the first segment 508.
Because the second thick gate oxide segment 510 ends in the channel region, the remaining area is also rectangular in shape as it is bound on two sides by segments 508 and 510, and on the other two sides by the edges of the active area 502. This remaining area is the thin gate oxide area 512. While the OD2 mask 513 defines the areas within which thick oxide is to be formed, the OD2 mask 513 has a rectangular opening 514 in which no thick oxide is to be formed. Thin gate oxide will be grown within the area defined by opening 514. Expressed in the alternate, the areas outside of the rectangular outline 514 is where thick gate oxide is formed. With reference to the alternate fabrication method using thermal oxide fabrication steps, opening 514 is used to define where thermally grown thin oxide is to be formed. Then segments 508 and 510 are the areas within which thick oxide is a combined thickness of thermally grown oxide and previously formed intermediate oxide. Dashed outline 513 can represent an OD2 mask used during the fabrication process, which is positioned such that a corner of the opening 514 overlaps a corner of the active area 502 underneath the polysilicon gate 504. The dimensions of opening 514 can be selected to be any size, but has a preferred set of dimensions, as will be discussed with reference to FIG. 13. In the single transistor anti-fuse memory cell, a bitline contact 516 is formed for electrical connection to a bitline (not shown).
FIG. 13 is a planar layout of a memory array consisting of the anti-fuse memory cell of FIG. 12 according to an embodiment of the present invention. The memory array has anti-fuse memory cells arranged in rows and columns, where polysilicon gates 504, formed as continuous polysilicon lines, extend over the active areas 502 of each anti-fuse memory cell in a row. Each polysilicon line is associated with a logical wordline WL0, WL1, WL2 and WL3. In the presently shown embodiment, each active area 502 has two polysilicon gates 504, thereby forming two anti-fuse transistors that share the same bitline contact 516 and active area 502. It is noted that all the anti-fuse memory cells of the memory array are formed in a single common well that is formed before any of the anti-fuse memory cell structures are formed.
Therefore, the reliability of unprogrammed anti-fuse cells having this minimized feature size thin gate oxide area 512 is greatly improved. The shape of the thin gate oxide area 512 is rectangular, or square, resulting in a minimized area. According to alternate embodiments, instead of having a single rectangular shaped opening 514 overlap with four anti-fuse active areas 502 as shown in FIG. 13, multiple smaller openings can be used. For example, an opening can be shaped to overlap only two horizontally adjacent active areas 502. Or, an opening can be shaped to overlap only two vertically adjacent active areas 502. Furthermore, individual rectangles larger in size than the desired thin gate oxide area 512 can be used to overlap each active area 502. While any number of rectangles of any size are contemplated by the previously shown embodiment, the thin gate oxide can be triangular in shape.
FIG. 14 is an enlarged planar layout of an anti-fuse transistor according to another embodiment of the present invention. Anti-fuse transistor 600 is virtually identical to anti-fuse transistor 500, and therefore has the same active area 502, polysilicon gate 504, and bitline contact 516. Anti-fuse transistor 600 has a differently shaped variable thickness gate oxide. The thick gate oxide area 602 can be seen as being composed of at least two rectangular segments and a triangular segment. A first thick gate oxide segment 604 extends from a first end of the channel region, coinciding with the left-most edge of the polysilicon gate 504, to a second end of the channel region. Segment 604 can be seen as a rectangular shaped area having a width less than the width of the channel region. The second thick gate oxide segment 606 is adjacent to the first segment 604, and extends from the same first end of the channel region to a predetermined distance of the channel length. The second thick gate oxide segment 606 has a width substantially equal to the difference between the channel width and the width of the first segment 604. The third gate oxide segment 608 is triangular in shape and has its 90 degree sides adjacent to the first thick gate oxide segment 604 and the second thick gate oxide segment 606. Segment 606 can include segment 608, such that the predetermined distances is set by the diagonal edge of segment 608. The remaining triangular area having 90 degree sides formed by the edges of the active area 502 is the thin gate oxide area 610.
The dashed diamond-shaped area 612 defines openings in the OD2 mask 513 in which the thin gate oxide is to be grown. Expressed in the alternate, the areas outside of the diamond-shaped outline 612 and within OD2 mask 513 is where thick gate oxide is formed. Dashed outline 612 is the opening in the OD2 mask 513 that is used during the fabrication process, and positioned such that an edge of the opening 612 overlaps a corner of the active area 502 underneath the polysilicon gate 504. With reference to the alternate fabrication method using thermal oxide fabrication steps, opening 612 is used to define where thermally grown thin oxide is to be formed. Then segments 604, 606 and 608 are the areas within which thick oxide is a combined thickness of thermally grown oxide and previously formed intermediate oxide. In the presently shown embodiment, opening 612 is a 45 degree rotated version of opening 514 of FIG. 12. The dimensions of opening 612 can be selected to be any size, but has a preferred set of dimensions, as will be discussed with reference to FIG. 15.
FIG. 15 is a planar layout of a memory array consisting of the anti-fuse memory cell of FIG. 14 according to an embodiment of the present invention. The memory array has anti-fuse memory cells arranged in rows and columns, where polysilicon gates 504, formed as continuous polysilicon lines, extend over the active areas 502 of each anti-fuse memory cell in a row. The layout configuration of the polysilicon gates 504 with respect to the active areas 502 is identical to that shown in FIG. 13.
According to further embodiments of the present invention, an access transistor can be formed in series with the anti-fuse transistor to provide a two-transistor anti-fuse cell. FIGS. 16A and 16B are illustrations of a two-transistor anti-fuse memory cell according to an embodiment of the present invention.
FIG. 16A shows a planar view of a two-transistor anti-fuse memory cell 700 having a minimized thin gate oxide area that can be manufactured with any standard CMOS process, according to an embodiment of the present invention. FIG. 16B shows a cross-sectional view of the memory cell 700 of FIG. 16A, taken along line B-B. Two-transistor anti-fuse memory cell 700 consists of an access transistor in series with an anti-fuse transistor. The structure of the anti-fuse transistor can be identical to those shown in FIGS. 11A to 15. For the present example, it is assumed that the anti-fuse transistor is identical to the one shown in FIG. 11B, and hence the same reference numerals indicate the same previously described features. More specifically, the structure of the variable thickness gate oxide is the same as shown in FIG. 11B, except that the diffusion region 410 does not have a bitline contact formed on it.
As previously described, the variable thickness gate oxide 402 has a thick gate oxide area and a thin gate oxide area. The thickness of gate oxide 704 will be the same as the thickness of the thick gate oxide area of the variable thickness gate oxide 402. In one embodiment, the access transistor can be fabricated using a high voltage transistor process, or the same process used to form the thick gate oxide area of variable thickness gate oxide 402. The polysilicon gate 702 can be formed concurrently with polysilicon gate 406. The anti-fuse transistor can be fabricated using the previously described methods. More specifically, the variable thickness gate oxide 402 can be formed using the previously described thermal oxide process. Furthermore, the access transistor having gate oxide 704 can be formed at the same time that the thick portion of variable thickness gate oxide 402 is formed. Therefore, the thicknesses of gate oxide 704 and the thick portion of variable thickness gate oxide 402 have substantially the same composition and thickness. This is easily done by patterning the access transistor oxide with the same OD2 mask used for forming the variable thickness gate oxide 402.
FIG. 16C shows a cross-sectional view of a two transistor anti-fuse memory cell, similar to the memory cell 700 of FIG. 16A, manufactured according to the method steps of FIGS. 8A to 8C. The two-transistor anti-fuse memory cell 750 consists of an access transistor in series with an anti-fuse transistor. In this embodiment, the gate oxide of the access transistor is formed at the same time the variable thickness gate oxide is formed. The access transistor has a polysilicon gate 752 overlying a gate oxide 754. Formed to one side of the gate oxide 754 is the shared diffusion region 756. Another diffusion region 758 is formed on the other side of the gate oxide 754, which will have a bitline contact 760 formed on it to make electrical contact with a bitline (not shown). The anti-fuse transistor is identical to the one shown in FIG. 10, which includes a gate 354 formed over a variable thickness gate oxide 352.
As previously discussed and shown in FIG. 8C, the variable thickness gate oxide 352 of FIG. 16C has a thick gate oxide area (shown as area 320 in FIG. 9), which is a combination of intermediate oxide and thermal oxide grown underneath the intermediate oxide. The gate oxide 754 of the access transistor is formed using the same process by which the variable thickness gate oxide 352 is formed. With reference to FIGS. 8A and 8B, the intermediate oxide 310 is patterned for the desired dimensions of the access transistor of memory cell 700 at the same time the thick gate oxide area of the variable thickness gate oxide is patterned. Therefore, when the thermal oxide is grown to form the variable thickness gate oxide as shown in FIG. 8C, the thermal oxide will grow underneath the intermediate oxide of the access transistor. The rate of thermal oxide growth underneath the intermediate oxide of the access transistor will be substantially the same as the thermal oxide growth rate underneath intermediate oxide 310 for the variable thickness gate oxide, and thereby has substantially the same thickness. Because of the silicon loss in the substrate during the thermal oxide growth process, FIG. 16C shows how the gate oxide 754 and the variable thickness gate oxide 352 extend below the substrate surface, which is generally delineated by the top surface of diffusion regions 758 and 756.
FIG. 17 is a planar layout of a memory array consisting of the two-transistor anti-fuse memory cell of FIGS. 16A and 16B according to an embodiment of the present invention. The memory array has memory cells arranged in rows and columns, where the polysilicon gates 406, formed as continuous polysilicon lines, extend over the active areas 416 of each anti-fuse memory cell in a row. Each polysilicon line is associated with a logical cell plate VCP0, VCP1, VCP2 and VCP3. The polysilicon gates 702 are formed as continuous polysilicon lines which extend over the active areas 416 of each anti-fuse memory cell in a row. These polysilicon lines are associated with logical wordlines WL0, WL1, WL2 and WL3. In the presently shown embodiment, each active area 416 has two pairs of polysilicon gates 406/702, thereby forming two anti-fuse transistors that share the same bitline contact 708 and active area 416. It is noted that all the two transistor anti-fuse memory cells of the memory array are formed in a single common well.
The openings 710 in OD2 mask 513 for defining the areas where the thin gate oxide is to be grown is rectangular in shape and sized and positioned such that each of its four corners overlaps with the corner areas of four anti-fuse transistor active areas 416, thereby defining the thin gate oxide areas 418. The same relative mask overlap criteria described for the embodiment FIG. 13 applies to the present embodiment. The dimensions of rectangular shaped openings 710 is selected based on the spacing between horizontally adjacent active areas 416 and the spacing between vertically adjacent active areas 416, such that the overlap area between the corners of the openings 710 and the diffusion mask for defining the active areas 416 is smaller than or equal to the minimum feature size of the fabrication technology.
The embodiment of FIG. 17 is configured to having separately controlled cell plates VCP0, VCP1, VCP2 and VCP3, which allows for improved control to prevent unintentional programming of unselected cells. In an alternate embodiment, VCP0, VCP1, VCP2 and VCP3 can be connected to a common node. In such an embodiment, a specific programming sequence is used to prevent unintentional programming of unselected cells. The programming sequence for the alternate embodiment starts with a precharge of all wordlines and bitlines to a high voltage level, followed by driving the common cell plate to a programming voltage VPP. Using the embodiment of FIG. 16B for example, this would result in precharging the diffusion region 410 to a high voltage level. The wordline to be programmed is selected by deselecting all of the other wordlines, ie, by driving them to a low voltage level for example. Then, the bitline voltage connected to the selected memory cell is driven to a low voltage level, such as ground for example.
FIG. 18 is a planar layout of a memory array consisting of the two-transistor anti-fuse memory cell according to an alternate embodiment of the present invention. The memory array of FIG. 18 is identical to that of FIG. 17, except that a diamond-shaped opening 712 withing OD2 mask 513 is used for defining the thin gate oxide areas of the variable thickness gate oxides. The same relative mask overlap criteria described for the embodiment FIG. 15 applies to the present embodiment.
In the previously disclosed embodiments of the invention, one of the thick gate oxide segments has a length extending from one end of the channel region to the other end of the channel region. According to an alternate embodiment, the length of this thick gate oxide segment is slightly reduced such that it does not fully extend across the full length of the channel region. FIG. 19 is a planar layout of an anti-fuse transistor according to an alternate embodiment of the present invention. In FIG. 19, the anti-fuse transistor 800 includes an active area 802, a polysilicon gate 804 and a bitline contact 806. The active area 802 underneath the polysilicon gate 804 is the channel region of anti-fuse transistor 800. In the present embodiment, OD2 mask 808 defines the area within which thick oxide is to be formed, and includes an “L”-shaped opening 809 overlapping an active area 802, within which thin gate oxide will be grown. This embodiment is similar to that shown in FIG. 12, except that one thick gate oxide segment (ie. 508) extends to a first predetermined distance between the channel region top edge and a second predetermined distance for the adjacent thick gate oxide segment (ie. 510). Therefore, the thin gate oxide will be grown between the first predetermined distance and the channel region top edge, and the second predetermined distance and the channel region top edge.
The previously described embodiments of the anti-fuse transistor have channel regions of a constant width. According to further embodiments, the channel region can have a variable width across the length of the channel region. FIG. 20A is a planar layout of an anti-fuse transistor according to an alternate embodiment of the present invention. In FIG. 20A, the anti-fuse transistor 850 includes an active area 852, a polysilicon gate 854 and a bitline contact 856. The active area 852 underneath the polysilicon gate 854 is the channel region of anti-fuse transistor 850. In the present embodiment, OD2 mask 858 defines the area within which thick oxide is to be formed, and includes a rectangular-shaped opening 859 overlapping the active area 852, within which thin gate oxide will be grown. The active area underneath the polysilicon gate 854 is “L”-shaped, and the rectangular opening 859 has a bottom edge that ends at a predetermined distance the channel region top edge.
FIG. 20B shows the same anti-fuse transistor 850 without shading of the polysilicon gate 854 to illustrate the thick gate oxide segments of the channel region. In the present embodiment, a first thick gate oxide segment 860 extends from the diffusion edge of the channel region to a first predetermined distance defined by the bottom edge of rectangular opening 859. A second thick gate oxide segment is L-shaped, and includes two sub-segments 862 and 864. Those skilled in the art will understand that the delineation of the sub-segments is a visual breakdown of the thick gate oxide segment shape into constituent rectangular shapes. Sub-segment 862 extends from the diffusion edge of the channel region to the first predetermined distance, while sub-segment 864 extends from the diffusion edge of the channel region to a second predetermined distance. The second predetermined distance is between the first predetermined distance and the diffusion edge of the channel region. The thin gate oxide region extends from the first predetermined distance of the first thick gate oxide segment 860 and the sub-segment 862 to the channel region top edge.
FIG. 21A is a planar layout of an anti-fuse transistor according to an alternate embodiment of the present invention. In FIG. 21A, the anti-fuse transistor 880 includes the same features as those in FIG. 17. In the present embodiment, the active area underneath the polysilicon gate 854 is “T”-shaped, and the rectangular opening 859 has a bottom edge that ends at a predetermined distance from the channel region top edge. FIG. 21B shows the same anti-fuse transistor 880 without shading of the polysilicon gate 854 to illustrate the thick gate oxide segments of the channel region.
In the previously described embodiments of FIGS. 20A and 21A, the thin gate oxide area extends from a bottom edge of the rectangular opening 859 to the channel region top edge. Because the channel region has a variable width, in which a portion proximate to the diffusion edge is larger than the portion proximate to the channel region top edge, the overall the thin gate oxide area can be smaller than the anti-fuse embodiment shown in FIG. 5 a. According to further embodiments, the thin gate oxide of the anti-fuse transistor embodiments of FIGS. 20A and 21A are further minimized by applying an OD2 mask having the rectangular or diamond-shaped openings shown in FIGS. 12 and 14.
FIG. 22 is a planar layout of an anti-fuse transistor according to an alternate embodiment of the present invention. Anti-fuse transistor 900 is similar to anti-fuse transistor 850 of FIG. 20B, except that OD2 mask 902 includes rectangular opening 904 shaped and positioned for delineating the thin gate oxide area 906. In the presently shown embodiment, the thick gate oxide comprises a first thick gate oxide segment 908 and a second thick gate oxide segment having sub-segments 862 and 864. Sub-segments 862 and 864 are the same as in the embodiment of FIG. 20B. However, due to the overlapping corners of rectangular opening 904 and the channel region, the first thick gate oxide segment 908 only extends from the diffusion edge to a predetermined distance of the channel length. Hence, the thick gate oxide segment 908 is shorter in length than sub-segment 862. Accordingly, anti-fuse transistor 900 has a smaller thin gate oxide area than the embodiment of FIG. 20A. The application of the OD2 mask 902 with rectangular openings 904 can be applied to anti-fuse transistor 880 of FIG. 21B with the same result.
A further reduction in the thin gate oxide area of the anti-fuse transistors 850 and 880 is obtained by applying diamond-shaped openings in the OD2 mask, as illustrated earlier in FIG. 14. FIG. 23 is a planar layout of an anti-fuse transistor according to an alternate embodiment of the present invention. Anti-fuse transistor 950 is similar to anti-fuse transistor 880 of FIG. 21B, except that OD2 mask 952 includes rectangular opening 954 shaped and positioned for delineating the thin gate oxide area 956. In the presently shown embodiment, the thick gate oxide comprises first and second thick gate oxide segments. The first thick gate oxide segment includes sub-segments 888 and 890, which are the same as in the embodiment of FIG. 21B. The second thick gate oxide segment includes sub-segments 958 and 960.
Due to the overlap of diamond-shaped opening 954 and the channel region, the second thick gate oxide sub-segment 960 only extends from the diffusion edge to a predetermined distance of the channel length, the predetermined distance being defined by the diagonal edge of the diamond-shaped opening 954. Accordingly, anti-fuse transistor 950 can have a smaller thin gate oxide area than the embodiment of FIG. 22. The application of the OD2 mask 952 with diamond-shaped opening 954 can be applied to anti-fuse transistor 850 of FIG. 20B with the same result. It is noted that the dimensions of sub-segments 958 and 960 are selected such that the diagonal edge of opening 954 does not overlap with the channel region covered by sub-segment 958.
The previously described embodiments of FIGS. 19-23 are directed to single transistor anti-fuse memory cells. The embodiments of FIGS. 19-23 are applicable to two-transistor anti-fuse cells, in which an access transistor is formed in series with the anti-fuse transistor. FIGS. 24-27 illustrate various embodiments of a two-transistor anti-fuse memory cell having minimized thin gate oxide areas.
FIG. 24 is a planar layout of a two-transistor anti-fuse transistor according to an embodiment of the present invention.
According to further embodiments of the present invention, an access transistor can be formed in series with the anti-fuse transistor to provide a two-transistor anti-fuse cell. FIGS. 16A and 16B are illustrations of a two-transistor anti-fuse memory cell according to an embodiment of the present invention where the channel region has a variable width. Two-transistor anti-fuse memory cell 1000 is similar to the two-transistor cell 700 of FIG. 16A. The access transistor includes active area 1002, a polysilicon gate 1004 and a bitline contact 1006. The anti-fuse transistor includes active area 1002, a polysilicon gate 1008. A common source/drain diffusion region 1010 is shared between the access transistor and the anti-fuse transistor. Underneath the polysilicon gate 1008 and covering the channel region is the variable thickness gate oxide having a thick gate oxide area and a thin gate oxide area. OD2 mask 1012 illustrates the areas in which a thick gate oxide is to be formed, and includes a rectangular-shaped opening 1013 overlapping the active area 852, within which thin gate oxide will be grown. Thin gate oxide area 1014 covers the channel region between the bottom edge of the rectangular opening 1013 and the channel region top edge.
In FIG. 24 the channel region of the anti-fuse transistor has a variable width. In the embodiment of FIG. 25, the channel region of the anti-fuse transistor has a constant width, but is smaller in width than the remainder of the active area and the channel of the access transistor. More specifically, two-transistor anti-fuse memory cell 1050 is similar to memory cell 1000, except that active area 1052 is shaped such that the common source/drain diffusion region 1054 now has a variable width, leaving the channel region of the anti-fuse transistor constant, but smaller in width than the channel region of the access transistor.
FIG. 26 is yet another alternate embodiment of the two-transistor anti-fuse memory cell. Two-transistor anti-fuse memory cell 1100 is similar to two-transistor anti-fuse memory cell 1000 of FIG. 24, except that the active area 1102 is shaped such that the anti-fuse transistor has a “T”-shaped channel region instead of the “L”-shaped channel region. FIG. 27 is similar to the embodiment of FIG. 26, except that two-transistor anti-fuse memory cell 1150 has an active area 1152 shaped such that the anti-fuse transistor has a channel region of a constant width. The common source/drain diffusion region 1154 is “T”-shaped such that it has a portion of narrower width.
The two-transistor anti-fuse memory cell embodiments of FIGS. 24-27 can use OD2 masks having rectangular or diamond-shaped openings positioned to minimize the thin gate oxide areas of the anti-fuse transistors. The anti-fuse memory cell embodiments of FIGS. 19 to 27 can be fabricated with the alternate fabrication process where thermal oxide is grown to form the thick and thin portions of the variable thickness gate oxide.
It should be noted that design rules for certain features are set up to ensure that a specific area for that feature defined by a mask covers not only the specific area, but has some overlap onto adjacent features. In effect, the adjacent features truly control where the implantation occurs. For example, the OD2 shape will fully cover the 10 transistor area, which is defined by diffusion. Hence, it does not matter where the actual mask shape ends. This is one primary reason why the OD2 mask is a low grade, and consequently, a low cost mask, as there is an allowed margin of error. Furthermore, some aligner machines are capable of achieving 0.06 micron tolerance, but are only used at 0.1 micron as it is deemed sufficient for ion implant masks. For fabricating the anti-fuse transistors and memory arrays shown in FIGS. 4 to 18, the mask shape ends are important for defining the thin gate oxide area. The current grade OD2 mask used for typical CMOS processes can be used for defining the thin gate oxide areas of the described anti-fuse memory cells. However, the margin of error must be taken into account, thereby resulting in a memory cell having a particular minimum size.
According to an embodiment of the present invention, the anti-fuse memory cells of FIGS. 4-18 are fabricated using an OD2 mask having a grade corresponding to the mask grade used for source/drain implants (grade level 2) of the same process. The OD2 mask grade is preferably equivalent to the mask grade used for diffusion implants (grade level 5) of the same process to achieve smaller sized memory cells having high reliability. Therefore, higher density memory arrays, improved yield, improved performance and high reliability are obtained by using a high grade OD2 mask. The accuracy is further improved by ensuring that alignment of the mask is done at the highest possible accuracy level. High alignment accuracy is obtained by using superior lithography equipment, lithography methods and/or different light wavelengths and different mask types, any combination thereof being possible.
For the embodiment of FIG. 5A, more accurate overlap of the OD2 shape end/edge underneath the polysilicon gate 106 allows for a minimized thin oxide area under the polysilicon gate. In particular, the thin oxide area will be rectangular in shape, having two opposite sides defined by the width of the active area underneath the polysilicon gate, and another two opposite sides defined by the OD2 mask shape end underneath the polysilicon gate and an edge of the polysilicon gate. The addition of high precision alignment will further minimize the thin oxide area.
The drawings of the transistor devices presented in the figures are used to illustrate features of the transistor devices, and are intended to be drawn to scale. Actual fabricated transistor devices including the described features will have dimensions resulting from design choices or the application of design rules imposed by specific fabrication processes.
1. A method of forming a variable thickness gate oxide for an anti-fuse transistor, comprising the steps of:
growing a first oxide in a channel region of the anti-fuse transistor;
removing the first oxide from a thin oxide area of the channel region;
thermally growing a second oxide in the thin oxide area and in a thick gate oxide area of the channel region under the first oxide, and a combination of the first oxide and the second oxide in the thick gate oxide area has a thickness greater than the second oxide in the thin oxide area; and
forming a diffusion region adjacent the thick oxide area for receiving current from the channel region.
2. The method of claim 1, wherein thermally growing includes growing the second oxide in the thin oxide area at a first rate and growing the second oxide in the thick gate oxide area at a second rate less than the first rate.
3. The method of claim 2, wherein growing the second oxide in the thin oxide area at a first rate includes consuming a substrate surface of the thin oxide area to a first depth, and growing the second oxide in the thick gate oxide area includes consuming a substrate surface of the thick gate oxide area to a second depth less than the first depth.
4. The method of claim 3, wherein thermally growing includes forming an angled oxide area between the thick gate oxide area and the thin gate oxide area, the angled oxide area having a thickness different from the combination of the first oxide and the second oxide in the thick gate oxide area, and different from the second oxide in the thin oxide area.
5. The method of claim 4, further including forming a common gate over the first oxide the second oxide, and the angled oxide area.
6. The method of claim 1, wherein the second oxide under the first oxide is thinner than the second oxide in the thin oxide area.
7. The method of claim 1, further including forming a bitline contact in electrical contact with the diffusion region for sensing a current from the common gate when a conductive link is formed between the channel and the common gate.
8. An anti-fuse memory cell having a variable thickness gate oxide comprising:
a first oxide in a thick oxide area of the channel region; and,
a second oxide thermally grown in a thin oxide area of the channel region and in the thick oxide area underneath the first oxide;
a diffusion region adjacent to the thick oxide area for receiving current from the channel region;
isolation adjacent to the thin gate oxide area; and
a gate over the first oxide and the second oxide.
9. The anti-fuse memory cell of claim 8, wherein the second oxide under the first oxide is thinner than the second oxide in the thin oxide area.
10. The anti-fuse memory cell of claim 9, wherein a combination of the first oxide and the second oxide in the thick oxide area has a thickness greater than the second oxide in the thin oxide area.
11. The anti-fuse memory cell of claim 10, wherein the second oxide in the thin oxide area extends into the substrate to a first depth, and the second oxide in the thick oxide area extends into the substrate to a second depth less than the first depth.
12. The anti-fuse memory cell of claim 8, further including an angled oxide area between the thick gate oxide area and the thin gate oxide area, the angled oxide area having a thickness different from the combination of the first oxide and the second oxide in the thick gate oxide area, and different from the second oxide in the thin oxide area.
13. The anti-fuse memory cell of claim 8, wherein the gate is connected to a wordline.
14. The anti-fuse memory cell of claim 13, wherein the diffusion region is connected to a bitline.
15. The anti-fuse memory cell of claim 13, further including an access transistor adjacent to the diffusion region, and another diffusion region adjacent to the access transistor.
16. The anti-fuse memory cell of claim 15, wherein the another diffusion region is connected to a bitline.
17. The anti-fuse memory cell of claim 16, wherein the access transistor has a gate oxide thickness corresponding to the combination of the first oxide and the second oxide in the thick gate oxide area.
US14244499 2004-05-06 2014-04-03 Anti-fuse memory cell Active US9123572B2 (en)
US56831504 true 2004-05-06 2004-05-06
US10553873 US7402855B2 (en) 2004-05-06 2005-05-06 Split-channel antifuse array architecture
US11762552 US7755162B2 (en) 2004-05-06 2007-06-13 Anti-fuse memory cell
US12814124 US8026574B2 (en) 2004-05-06 2010-06-11 Anti-fuse memory cell
US13219215 US8313987B2 (en) 2004-05-06 2011-08-26 Anti-fuse memory cell
US13662842 US8735297B2 (en) 2004-05-06 2012-10-29 Reverse optical proximity correction method
US14244499 US9123572B2 (en) 2004-05-06 2014-04-03 Anti-fuse memory cell
EP20150773817 EP3108497A4 (en) 2014-04-03 2015-04-02 Anti-fuse memory cell
KR20167020381A KR20160127721A (en) 2014-04-03 2015-04-02 Anti-fuse memory cell
PCT/CA2015/050266 WO2015149182A1 (en) 2014-04-03 2015-04-02 Anti-fuse memory cell
CA 2887223 CA2887223C (en) 2014-04-03 2015-04-02 Anti-fuse memory cell
CN 201580002116 CN105849861A (en) 2014-04-03 2015-04-02 Anti-fuse memory cell
US13662842 Continuation-In-Part US8735297B2 (en) 2004-05-06 2012-10-29 Reverse optical proximity correction method
US20140209989A1 true US20140209989A1 (en) 2014-07-31
US9123572B2 true US9123572B2 (en) 2015-09-01
ID=51221983
US14244499 Active US9123572B2 (en) 2004-05-06 2014-04-03 Anti-fuse memory cell
US (1) US9123572B2 (en)
US3719866A (en) 1970-12-03 1973-03-06 Ncr Semiconductor memory device
US3781977A (en) 1970-09-19 1974-01-01 Ferrant Ltd Semiconductor devices
US3877055A (en) 1972-11-13 1975-04-08 Motorola Inc Semiconductor memory device
EP0089457A2 (en) 1982-03-23 1983-09-28 Texas Instruments Incorporated Avalanche fuse element as programmable memory
US4611308A (en) 1978-06-29 1986-09-09 Westinghouse Electric Corp. Drain triggered N-channel non-volatile memory
US4720818A (en) 1985-06-17 1988-01-19 Fujitsu Limited Semiconductor memory device adapted to carry out operation test
US5008721A (en) 1988-07-15 1991-04-16 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel
JPH03220767A (en) 1990-01-25 1991-09-27 Sharp Corp Nonvolatile semiconductor memory device
US5057451A (en) 1990-04-12 1991-10-15 Actel Corporation Method of forming an antifuse element with substantially reduced capacitance using the locos technique
US5138423A (en) 1990-02-06 1992-08-11 Matsushita Electronics Corporation Programmable device and a method of fabricating the same
EP0295935B1 (en) 1987-06-19 1992-12-23 Advanced Micro Devices, Inc. Electrically erasable programmable read only memory
US5258947A (en) 1989-12-07 1993-11-02 Sgs-Thomson Microelectronics, S.A. MOS fuse with programmable tunnel oxide breakdown
US5331181A (en) 1990-08-01 1994-07-19 Sharp Kabushiki Kaisha Non-volatile semiconductor memory
US5416343A (en) 1992-11-20 1995-05-16 U.S. Philips Corporation Semiconductor device provided with a number of programmable elements
US5422505A (en) 1990-10-17 1995-06-06 Kabushiki Kaisha Toshiba FET having gate insulating films whose thickness is different depending on portions
US5442589A (en) 1992-10-29 1995-08-15 Gemplus Card International Fuse circuitry having physical fuse and non-volatile memory cell coupled to a detector
US5502326A (en) 1992-11-20 1996-03-26 U.S. Philips Corporation Semiconductor device provided having a programmable element with a high-conductivity buried contact region
JPH08172138A (en) 1994-07-26 1996-07-02 Advanced Micro Devices Inc Method for forming first and second oxide layers and integrated circuit
JPH08213483A (en) 1994-11-12 1996-08-20 Deutsche Itt Ind Gmbh Programmable semiconductor storage device
US5550773A (en) 1994-01-31 1996-08-27 U.S. Philips Corporation Semiconductor memory having thin film field effect selection transistors
US5595922A (en) 1994-10-28 1997-01-21 Texas Instruments Process for thickening selective gate oxide regions
US5741737A (en) 1996-06-27 1998-04-21 Cypress Semiconductor Corporation MOS transistor with ramped gate oxide thickness and method for making same
US5786268A (en) 1991-04-26 1998-07-28 Quicklogic Corporation Method for forming programmable interconnect structures and programmable integrated circuits
US5798552A (en) 1996-03-29 1998-08-25 Intel Corporation Transistor suitable for high voltage circuit
US5821766A (en) 1996-02-20 1998-10-13 Hyundai Electronics Industries Co., Ltd. Method and apparatus for measuring the metallurgical channel length of a semiconductor device
US5825069A (en) 1997-01-27 1998-10-20 United Microeltronics Corp. High-density semiconductor read-only memory device
US5918133A (en) 1997-12-18 1999-06-29 Advanced Micro Devices Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof
US5925904A (en) 1996-04-03 1999-07-20 Altera Corporation Two-terminal electrically-reprogrammable programmable logic element
US5949712A (en) 1997-03-27 1999-09-07 Xilinx, Inc. Non-volatile memory array using gate breakdown structure
US5963799A (en) 1998-03-23 1999-10-05 Texas Instruments - Acer Incorporated Blanket well counter doping process for high speed/low power MOSFETs
JP2000077627A (en) 1998-06-17 2000-03-14 Mitsubishi Electric Corp Semiconductor element
US6037224A (en) 1997-05-02 2000-03-14 Advanced Micro Devices, Inc. Method for growing dual oxide thickness using nitrided oxides for oxidation suppression
US6121795A (en) 1998-02-26 2000-09-19 Xilinx, Inc. Low-voltage input/output circuit with high voltage tolerance
US6127235A (en) 1998-01-05 2000-10-03 Advanced Micro Devices Method for making asymmetrical gate oxide thickness in channel MOSFET region
US6136674A (en) 1999-02-08 2000-10-24 Advanced Micro Devices, Inc. Mosfet with gate plug using differential oxide growth
KR20010030493A (en) 1999-09-27 2001-04-16 가네꼬 히사시 Semiconductor device
US6221731B1 (en) 1998-01-12 2001-04-24 United Microelectronics Corp. Process of fabricating buried diffusion junction
US6303251B1 (en) 1998-07-29 2001-10-16 Matsushita Electric Industrial Co., Ltd. Mask pattern correction process, photomask and semiconductor integrated circuit device
US20020008279A1 (en) 1998-06-17 2002-01-24 Tsukasa Ooishi Semiconductor device
JP2002093745A (en) 2000-09-12 2002-03-29 Matsushita Electric Ind Co Ltd Manufacturing method of semiconductor device
US20020051399A1 (en) 2000-10-27 2002-05-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including a fuse circuit in which the electric current is cut off after blowing so as to prevent voltage fall
US20020086225A1 (en) 1999-11-18 2002-07-04 Jui-Tsen Huang Optical proximity correction of pattern on photoresist
US6429686B1 (en) 2000-06-16 2002-08-06 Xilinx, Inc. Output driver circuit using thin and thick gate oxides
JP2002319674A (en) 2001-02-27 2002-10-31 Internatl Business Mach Corp <Ibm> Semiconductor device with dielectric layer of two- dimensional thickness, and manufacturing method therefor
US20020192910A1 (en) 2000-11-28 2002-12-19 Ramsbey Mark T. Simultaneous formation of charge storage and bitline to wordline isolation
US20030094608A1 (en) 2001-11-20 2003-05-22 International Business Machines Corporation Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
US20030207526A1 (en) 2001-06-02 2003-11-06 Tito Gelsomini Anti-fuse structure and method of writing and reading in integrated circuits
US20030218234A1 (en) 2002-05-24 2003-11-27 Madurawe Raminda U. Programmable latch using antifuses
US6682980B2 (en) 2002-05-06 2004-01-27 Texas Instruments Incorporated Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant
US20040076070A1 (en) 2002-10-21 2004-04-22 Hyung-Dong Kim Semiconductor memory device for enhancing bitline precharge time
US6808985B1 (en) 2002-02-21 2004-10-26 Taiwan Semiconductor Manufacturing Company Products derived from embedded flash/EEPROM products
US6813406B2 (en) 2001-06-14 2004-11-02 Lightbay Networks Corporation Photonic switching apparatus for optical communication network
US6940122B2 (en) 2002-10-22 2005-09-06 Terra Semiconductor, Inc. Flash EEPROM unit cell and memory array architecture including the same
US6992365B2 (en) 2001-10-12 2006-01-31 Ovonyx, Inc. Reducing leakage currents in memories with phase-change material
CA2682092C (en) 2009-10-30 2010-11-02 Sidense Corp. And-type one time programmable memory cell
CA2646367C (en) 2008-04-04 2010-11-09 Sidense Corp. Low threshold voltage anti-fuse device
US20110042735A1 (en) 2009-05-11 2011-02-24 Renesas Electronics Corporation Semiconductor storage device and manufacturing method of semiconductor storage device
CA2815989C (en) 2012-05-16 2014-06-10 Sidense Corp. A power up detection system for a memory device
CA2816237C (en) 2012-05-18 2014-09-30 Sidense Corp. Circuit and method for reducing write disturb in a non-volatile memory device
JP2008544554T5 (en) 2009-07-09
US20010026494A1 (en) 1996-08-20 2001-10-04 Micron Technology, Inc. Method of anti-fuse repair
US6429495B2 (en) 1998-06-17 2002-08-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with address programming circuit
US20020185694A1 (en) 1998-06-17 2002-12-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with address programming circuit
KR20040015239A (en) 2001-05-01 2004-02-18 아트멜 코포레이숀 Eeprom cell with asymmetric thin window
JP2004527128A (en) 2001-05-01 2004-09-02 アトメル・コーポレイションＡｔｍｅｌ Ｃｏｒｐｏｒａｔｉｏｎ eeprom cell with a thin window of asymmetric
WO2004003966A3 (en) 2002-04-26 2006-10-26 Kilopass Technologies Inc High density semiconductor memory cell and memory array using a single transistor
JP2006504261A (en) 2002-10-22 2006-02-02 テラ セミコンダクター、インク． Flash eeprom unit cells and the memory array structure including the same
KR20070010077A (en) 2004-05-06 2007-01-19 싸이던스 코포레이션 Split-channel antifuse array architecture
Alam et al. "A Study of Soft and Hard Breakdown-Part I: Analysis of Statistical Percolation Conductance," IEEE Transactions on Electron Devices, vol. 49, pp. 232-238, Feb. 2002.
Alam et al. "A Study of Soft and Hard Breakdown-Part II: Principles of Area, Thickness, and Voltage Scaling," IEEE Transactions on Electron Devices, vol. 49, pp. 239-246, Feb. 2002.
Crupi et al. "A Novel Methodology for Sensing the Breakdown Location and Its Application to the Reliability Study of Ultrathin Hf-Silicate Gate Dielectrics," IEEE Transactions on Electron Devices, vol. 52, pp. 1759-1768, Aug. 2005.
Degraaf, C., et al. "A Novel High-Density Low-Cost Diode Programmable Read Only Memory", IEEE, pp. 189-192, 1996.
Degraeve et al. "A Consistent Model for the Thickness Dependence of Intrinsic Breakdown in Ultra-Thin Oxides," IEEE International Electron Devices Meeting, pp. 863-866, 1995.
Degraeve et al. "Relation Between Breakdown Mode and Location in Short-Channel nMOSFETs and Its Impact on Reliability Specifications," IEEE Transactions on Device and Materials Reliability, vol. 1, pp. 163-169, Sep. 2001.
English Translation of Taiwan Patent Application No. 102136776 Search Report dated Sep. 29, 2014.
Esquivel "High Density Contactless, Self Aligned EPROM Cell Array Technology," IEEE International Electron Devices Meeting, pp. 592-595, 1986.
European Patent Application No. 05743122.3, Office Action dated Jun. 23, 2010.
European Patent Application No. 05743122.3, Supplementary Search Report dated Jul. 2, 2009.
European Patent Application No. 08772785.5 Office Action dated Jul. 13, 2015.
European Patent Application No. 08772785.5, Search Report dated Dec. 7, 2010.
Ghani et al., 100nm Gate Length High Performance / Low Power CMOS Transistor Structure, IEEE International Electron Devices Meeting, pp. 415-418, 1999.
Gill et al. "A 5-Volt Contactless Array 256Kbit Flash EEPROM Technology," IEEE International Electron Devices Meeting, pp. 428-431, 1988.
International Patent Application No. PCT/CA2008/001122, Search Report dated Sep. 18, 2008.
International Patent Application No. PCT/CA2013/050772, Written Opinion and International Search Report dated Dec. 18, 2013.
International Patent Application No. PCT/CA2015/050266, International Search Report and Written Opinion dated Jul. 8, 2015.
Japanese Patent Application No. 2007-511808, English Translation of Office Action dated May 17, 2011.
Japanese Patent Application No. 2010-511457, English Translation of Notice of Reasons for Rejection dated Mar. 18, 2014.
Japanese Patent Application No. 2010-511457, Notice of Reasons for Rejection dated Apr. 16, 2013.
Kaczer et al. "Consistent Model for Short-Channel nMOSFET After Hard Gate Oxide Breakdown," IEEE Transactions on Electron Devices, vol. 49, pp. 507-513, Mar. 2002.
Kim et al., "3-Transistor Cell OTP ROM Array Using Standard CMOS Gate-Oxide Antifuse", Journal of Semiconductor Technology and Science, vol. 3, No. 4, Dec. 2003, 6 pages.
Ko et al. "The Effects of Weak Gate-to-Drain(Source) Overlap on MOSFET Characteristics," IEEE International Electron Devices Meeting, pp. 292-295, 1986.
Korean Patent Application No. 10-2006-7025621, English Translation of Office Action dated May 18, 2011.
Korean Patent Application No. 10-2010-7000718, Notice of Allowance dated Jan. 29, 2013.
Lee, Shiuh-Wuu, "A Capacitance-Based Method for Experimental Determination of Metallurgical Channel Length of Submicron LDD MOSFET's," IEEE Transactions on Electron Devices, vol. 41, pp. 403-412, Mar. 1994.
Lombardo et al. "Softening of Breakdown in Ultra-Thin Gate Oxide nMOSFET's at Low Inversion Layer Density", 39th Annual International Reliability Physics Symposium; Orlando, FL, pp. 163-167, 2001.
Miranda, E., et al. "Analytic Modeling of Leakage Current Through Multiple Breakdown Paths in SiO2 Films", 39th Annual International Reliability Physics Symposium; Orlando, FL, pp. 367-379, 2001.
Ogura et al. "A Half Micron MOSFET Using Double Implanted LDD," IEEE International Electron Devices Meeting pp. 718-721, 1982.
Rasras, Mahmoud et al. "Substrate Hole Current Origin After Oxide Breakdown"; IEEE, pp. 537-540, 2000.
Shur "Split-Gate Field Effect Transistor," Applied Physics Letters, vol. 54, pp. 162-164, Jan. 1989.
Sidense Corp., Motion for Leave to File Motion for Reconsideration of Claim Construction Order, USDC, filed Mar. 22, 2012, 179 pages.
Sune, Jordi et al. "Post Soft Breakdown Conduction in SiO2 Gate Oxides"; IEEE, pp. 533-536, 2000.
Taiwan Patent Application No. 097121479, English Translation of Office Action dated Jul. 24, 2013.
U.S. Appl. No. 10/553,873, Office Action dated May 14, 2008.
U.S. Appl. No. 11/762,552, Notice of Allowance dated Apr. 28, 2010.
U.S. Appl. No. 11/877,229, Notice of Allowance dated Oct. 14, 2009.
U.S. Appl. No. 12/139,992, Office Action dated Mar. 23, 2011.
U.S. Appl. No. 12/814,124, Notice of Allowance dated May 13, 2011.
U.S. Appl. No. 13/219,215, Notice of Allowance dated Jan. 19, 2012.
U.S. Appl. No. 13/662,842, Office Action dated Sep. 12, 2013.
Weir, B.E., et al., Ultra-Thin Gate Dielectrics: They Break Down, But Do They Fail?, IEEE International Electron Devices Meeting, pp. 73-76, 1997.
Wong, C., "Sidewall Oxidation of Polycrystalline-Silicon Gate," IEEE Electron Device Letters, vol. 10, pp. 420-422, Sep. 1989.
Wu et al. "Structural Dependence of Dielectric Breakdown in Ultra-Thin Oxides and Its Relationship to Soft Breakdown Modes and Device Failure;" IEEE International Electron Devices Meeting, pp. 187-190, 1998.
Wu, E.W. et al. "Voltage-Dependent Voltage-Acceleration of Oxide Breakdown for Ultra-Thin Oxides"; IEEE, pp. 541-544, 2000.
Yang et al. "Asymmetric Gate (AG) FET: Sub-micron MOS Device Structure With Excellent performance," Proceedings, 6th Intern. Conf. on Solid State and Integrated Circuits Technology pp. 543-546, 2001.
US20140209989A1 (en) 2014-07-31 application
US6327174B1 (en) 2001-12-04 Method of manufacturing mask read-only memory cell
Owner name: SIDENSE CORPORATION, CANADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KURJANOWICZ, WLODEK;REEL/FRAME:034378/0045
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPLICATION NUMBER: 14/111,079 PREVIOUSLY RECORDED ON REEL 034378 FRAME 0045. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT APPLICATION NUMBER IS: 14/244,499;ASSIGNOR:KURJANOWICZ, WLODEK;REEL/FRAME:035648/0412