Source: https://patents.google.com/patent/US5517664A/en
Timestamp: 2019-09-21 13:40:21
Document Index: 315662526

Matched Legal Cases: ['art 14', 'art 14', 'art 13', 'art 14', 'art 14', 'art 11', 'art 11', 'art 11', 'art 15', 'art 15', 'art 112', 'art 113', 'art 114', 'art 121', 'art 117', 'art 118', 'art 119', 'art 120', 'art 12', 'art 213', 'art 212', 'art 214', 'art 419', 'art 418', 'art 418', 'art 418', 'art 422', 'art 422', 'art 422', 'art.\n7']

US5517664A - RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing - Google Patents
RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing Download PDF
US5517664A
US5517664A US08/459,965 US45996595A US5517664A US 5517664 A US5517664 A US 5517664A US 45996595 A US45996595 A US 45996595A US 5517664 A US5517664 A US 5517664A
US08/459,965
Keiichi Kurakazu
1986-04-14 Priority to JP61-84552 priority Critical
1986-04-14 Priority to JP61085442A priority patent/JP2545789B2/en
1987-04-13 Priority to US07/037,843 priority patent/US5214786A/en
1992-09-17 Priority to US07/945,930 priority patent/US5307502A/en
1994-01-21 Priority to US08/183,830 priority patent/US5450610A/en
1995-06-02 Priority to US08/459,965 priority patent/US5517664A/en
1996-05-14 Publication of US5517664A publication Critical patent/US5517664A/en
In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing.
Besides, an address part for designating the main memory is provided in the same instruction.
This application is a Continuation of patent application Ser. No. 08/183,830, now U.S. Pat. No. 5,450,610 filed Jan. 21, 1994; which is a Continuation of patent application Ser. No. 07/945,930, filed Sep. 17, 1992 now U.S. Pat. No. 5,307,502, issued on Apr. 26, 1994; which is a Continuation of application Ser. No. 07/037,843, filed Apr. 13, 1987, now U.S. Pat. No. 5,214,786, issued May 25, 1993.
Heretofore, in a computer system furnished with a large number of registers, a method of assigning the individual registers has been discussed in, for example, D. A. Patterson and C. H. Sequin: A VLSI RISC, Computer September 1982, IEEE (pp. 8-21) and has generally been realized in the form of a RISC I-microprocessor (hereinbelow, abbreviated to "RISC I").
In the RISC I, there are bank of 32 logical registers which can be assigned by instructions, and a total of 138 physical registers exist. Letting L0, L1, . . . and L31 denote the logical registers to be assigned by the instructions, and letting R0, R1, . . . and R137 denote the physical registers, the registers L0, L1, . . . and L9 correspond respectively to registers R0, R1, . . . and R9 at all times. The registers L10, L11, . . . and L31 are respectively held in correspondence with registers R116, R117, . . . and R137 at the time of initialization. However, they are respectively brought into correspondence with the registers R100, R101, . . . and R121 after the call of the first subprogram, and with the registers R84, R85, . . . and R105 after the call of a subprogram directly below the level of the first subprogram. In this manner, the correspondence of the registers is shifted downwards or advanced by 16 registers in conformity with the nest level of the subprogram call. At the time of return from a subprogram, the correspondence is brought back upwards or retracted by 16 registers. The logical registers L26, L27, . . . and L31 before the subprogram call indicate the same physical registers as those corresponding to the registers L10, L11, . . . and L15 after the subprogram call, respectively.
With the prior art as stated above, the following problems are involved: (a) A register area to be used is shifted upwards or downwards in the fixed amount only when a subprogram is returned or called, and it is not considered at all to change a register position for use in adaptation to the property of a program or to a programming form, so that the efficient utilization of registers cannot be attained. (b) Large quantities of physical registers need to be saved and restored when a task is switched, and further increase in the number of physical registers does not lead to an increase in speed. (c) When physical registers have been used up, register saving, etc. operations are executed by an interrupt handling routine, and hence, a long time is expended for processing.
The information processing apparatus of the present invention for accomplishing the above-mentioned object is characterized in that means to simultaneously assign in one instruction the respective address space areas of a main memory and a register block is provided, and that the assignment of a register to be used by each instruction is expressed by the combination of the assignment of an area register having the register address of a register area as a value and the assignment of a displacement denoting a relative register address within the register area.
The value of an area register is set by software in conformity with the use of registers at each point of time as processing by a computer proceeds. In general, a plurality of area registers are provided, though a single area register may well be provided. The register field of each individual instruction is configured of an area register part which indicates the area register to be used, and a register displacement part which indicates a relative register address within the indicated area. The area register is realized by a special-purpose register in some cases, and by a register of specific area (hereinbelow, called "specific register") within a register block in which general registers are assembled, in the other cases. On the occasion of employing the special-purpose register, instructions for loading and storing the value of the register are provided. In contrast, on the occasion of employing the specific register, the assignment of the area register corresponding to the specific area is omitted, and the address of the area register to be used is assigned by only the register displacement.
Furthermore, in a case where one ring bank is provided in which banks each including l0 registers are grouped in m banks and where one set of global banks is configured of n banks, the respective global banks being constructed of l1, l2, . . . and ln registers, registers numbering l0 ×m+l1 +l2 + . . . +ln exist as a whole. In this case, the maximum number of registers l0, l1, l2, . . . ln can be assigned by the register displacement part of the instruction. Each bank of the ring bank is used in a form allocated to the corresponding one of the nest levels of the nested subprogram calls, while each global bank is used in a form allocated to the corresponding one of the tasks which are executed asynchronously. More specifically, as regards the ring bank, when the nest level of the subprogram call deepens by one, a bank at the next position in terms of the ring-shaped position is used as a current bank, and a bank having been used as a current bank till then is set as a previous bank. When the nest level shallows by one owing to the return from a subprogram, the ring-shaped position retracts by one to set a previous bank as a current bank, and a bank at the preceding position in terms of the ring-shaped position is set as a new previous bank. The global bank can have the allocation varied at the task switch, but in calling and returning a subprogram within an identical task, the allocation is held invariable and the content is not automatically saved and restored. One of the global banks is fixedly used by a system task for handling interruption etc., and that global bank shall be called the "system bank."
As a usage, information which is locally used within a single subprogram is put in the ring bank, while global information which is to be held beyond the partition of subprogram calls and temporal information which need not be saved and restored at the time of a subprogram call are put in the global bank. When information to be delivered to a subprogram of lower level is kept in the register of a current bank, the subprogram called can refer to it as the register of a previous bank. When information to be given as a function value or the like from a called subprogram back to a subprogram of higher level is kept in the register of a previous bank, it can be referred to as the register of a current bank after the time of a return.
For the purpose of making it possible to assign that register among the registers of a current bank which is to hold its content at the time of any later ring bank advance or retraction, an indication vector is provided in which the bit i thereof is set at 1 if a register corresponds thereto and at 0 if not, and the vector is held in the specific register of the current bank.
In a case where the position of a register is expressed as a register address of a binary number, where the number in registers of each register area is made the power of 2 and where the value of an area register is set to be an integral times the power of 2, the position of the register to be actually used can be generated by an OR circuit on the basis of the value of the area register therefore, its a value specified in a register displacement part, and processing can be increased in speed. In a case where register positions are expressed by binary numbers from 0 to 2p -1, the succeeding register and preceding register of a register of register address i can be readily calculated as registers having register addresses mod(i+1, 2p) and mod(i-1, 2p), respectively. When, in a ring bank prepared by grouping 2r register banks each of which consists of 2q registers, the value of a bank control pointer is set to be an integral times as large as 2q, the succeeding bank and preceding bank of a bank beginning with an address i×2q can be readily calculated as banks having head register addresses mod((i+1)×2q, 2p+q) and mod((i-1)×2q, 2p+q), respectively.
In the information processing apparatus of the present invention, the value of an area register is set in a part preceding the execution of an instruction using general registers, such as in the head part of one program or subprogram. In a case where a register area for use is changed according to the kind of information to be handled, different area registers may be used for the individual kinds of information. When an instruction having an area register part i and a register displacement part d comes under the condition that the value of an area register i is set at Ai, the address of a register which is actually used by the instruction becomes Ai +d. In case of synthesizing a register address by means of an OR circuit on the basis of the value of an area register and a register displacement value, a program is drawn up so that a register displacement value may be restricted to a numerical value which can be expressed by at most l' bits, l' denoting a number smaller than the bit length of a register displacement part, and that the value of the area register may be restricted to a numerical value the lower l' bits of which are O's. Then, a synthesized value in the OR circuit becomes equal to an added value in an adder, so that no malfunction occurs.
The value of the area register can be set at any desired point of time without being restricted to the head part of the subprogram, etc. Therefore, when the program is to be run, the assignment of registers to be used can be changed at programmer's will in conformity with the use the of registers in the past and the requested use of registers in the future.
FIGS. 2(a), 2(b), 2(c), 2(d), and 2(e) are format diagrams of the essential portions of instructions for the information processing apparatus of the present invention;
When utilizing the information items delivered as the arguments within the subprogram, an instruction for referring to the content of a register in the previous bank is given by the program. Information set in a current register of specified by register displacement part value of i on a calling side can be referred to as the content of the previous register of specified by register displacement part value of i on a called side. Information set in a global bank on the calling side can be utilized as it is on the called side.
In returning from the subprogram, information to be given back to the calling side, such as a function value, is first set in the previous register if necessary. Thereafter, a retract ring bank instruction is executed. This instruction functions to set the value of a previous bank pointer before the return, as the value of a new current bank pointer, and to set the preceding ring-shaped address (i-l if the address i of a new previous bank pointer is greater than 0, and l(m-1) if it is 0) as the new value of the previous bank pointer. On this occasion, when the new value of the current bank pointer becomes equal to that of the valid bank pointer, the content of a bank save area indicated by the previous bank pointer is transferred, thereby to restore the content, while the new value of the previous bank pointer is set as that of the valid bank pointer, and a bank stack pointer is retracted in conformity with the amount of the transfer. A save indicator vector indicating a register to which the content is to be transferred is contained in the head part of the data which is transferred from the bank save area.
In task switches caused by such software as an operating system or the like, the values of the current bank pointer, the previous bank pointer, the global bank pointer, the valid bank pointer and the bank stack pointer for the current task are saved according to a store bank status instruction, and thereafter, the values of the pointers are set for the next task by the a load bank status instruction. At that time, in a case where one ring bank is shared with another task, the content of the ring bank is also saved and restored by the a block transfer instruction.
It is also possible to run a program using only global banks without employing a ring bank. Therefore, when the program thus created is run as a task, the save and restore processes of the ring bank are unnecessary. If such a task has the global banks separately allotted thereto so as not to compete with another task, it does not require the saving and restoration of registers at all. If an interrupt processing program or the like is constructed in such a form, the speed of processing is rendered very high. A large number of such tasks can be processed by utilizing a global bank mode in which the ring bank can be treated equally to the global banks.
When the value of the area register 21 is expressed by bi and a binary number whose lower l bits are O's is set beforehand, the register address synthesized by the OR circuit 30 as stated above becomes equal to the arithmetical sum bi +d between the value bi and the value d of the register displacement part 14. The lower l bits of the content of the area register 21 need not always be set at O's. Let l' denote a number equal to or smaller than the bit length l of the register displacement part 14, the content of a certain area register is set at a number with its lower l' bits being O's. In an instruction wherein the address of the area register is used in the area register part 13, if the value of the register displacement part is limited to numbers expressible with l' bits, the register No. synthesized by the OR circuit 30 as described above becomes equal to a value obtained by taking the arithmetical sum between both the values of the area register and the register displacement part. What value is to be set as the number l' for limiting the value to be put in the register displacement part 14 can be selected by software. Therefore, the value l' can be varied for every use of the area register. Moreover, even for one area register, it can be varied depending upon the time of use.
Now, when the register No. bi +d is synthesized in the above way out of the value bi of the area register 21 selected by a certain instruction and the value d of the register displacement part 14 and is sent to the register selection circuit 31, the (Rb.sbsb.i+d) register 32 of register address bi +d is selected as a register for use in the instruction. If the content of the operation code part 11 of the instruction indicates an instruction whose operand is the content of the selected register, then the content of the register Rb.sbsb.i+d is sent to the ALU 4, and the operation is executed there. On the other hand, if the content of the operation code part 11 indicates an instruction the result register of which is the selected register, then a result from the ALU 4 is put in the register Rb.sbsb.i+d. If the content of the operation code part 11 is a load instruction, the content of a main memory address indicated by the main memory designator part 15 is put in the register Rb.sbsb.i+d, and if it indicates a store instruction, the content of the register Rb.sbsb.i+d is stored in a main memory of the address indicated by the main memory designator part 15. The transfer register 41 in the main memory access mechanism 6 is a register for temporarily holding information which is transferred between the main memory 2 and the instruction processor 1, while the main memory address register 42 is a register for temporarily holding the address of the main memory 2 which is selected at that time.
FIG. 2(b) shows an instruction the main memory designator part 112 of which includes a register designator part 113 for designating a base register, a register designator part 114 for designating an index register, and a main memory displacement part 121. In this instruction, a register Rb to be used as the base register is found in the foregoing way on the basis of an area register part 117 and a register displacement part 118 on one side, while a register Rx to be used as the index register is found in the foregoing form on the basis of an area register part 119 and a register displacement part 120 on the other side, and an address obtained by taking the arithmetical sum of the three, the content of the base register Rb, the content of the index register Rx and the value of the main memory displacement part 12 is set as the address of the main memory 2 for use in the instruction.
FIG. 3 is an arrangement diagram of the essential portions of an information processing apparatus showing the second embodiment of the present invention. In this embodiment, an area register block 207 which is a set of special-purpose area registers is disposed separately from a general register block 203 within an instruction processor 201. The general register block 203 is composed of general registers R0, R1, . . . and RN, while the area register block 207 is composed of area registers Q0, Q1, . . . and QK. When the content i of an area register part 213 included in the register designator part 212 of an instruction is sent to an area register selection circuit 220 in a register access mechanism 205, the content bi of the area register (Qi) 221 in the area register block 207 is sent to a register area pointer 222. This content bi of the area register Qi and the content d of the register displacement part 214 of the instruction are added by a register address calculator 230, and the sum value bi +d is sent to a register selection circuit 231. As a result, the (Rb.sbsb.i+d) register 232 is selected from within the general register block 203 as a register for use in this instruction. The other portions such as an ALU 204 and a main memory access mechanism 206 are the same as in the first embodiment described with reference to FIG. 1.
FIG. 4 is an arrangement diagram of the essential portions of an information processing apparatus showing the third embodiment of the present invention. The principal portions of the information processing apparatus in this embodiment are an instruction processor 301 and a main memory 302. The instruction processor 301 includes therein an operation register block 303, an ALU 306, an area register block 310, a register access mechanism 320, a main memory access mechanism 330, an instruction decoder 340, and a bank stack pointer (BSP) 324. The operation register block 303 includes therein a ring bank 304 and a global bank set 305. The area register block 310 includes therein four area registers, namely, a previous bank pointer (PBNR) 311, a current bank pointer (CBNR) 312, a valid bank pointer (VBNR) 313 and a global bank pointer (GBNR) 314. In order to realize the function of keeping the content of the ring bank 304, there are disposed the bank stack pointer (BSP) 324 and a bank stack 325 allocated in the main memory 302. Further, there is the bank mode register (BMR) 323 which indicates a bank use mode. Broken lines in FIG. 4 exemplify the pointers for the area registers and the bank stack pointer.
FIGS. 5(a) and 5(b) are diagrams showing the arrangements of register blocks in FIG. 4. As illustrated in FIG. 5(a), the ring bank 304 is configured of m banks RB0, RB1, RB2, . . . and RBm-1, each of which is composed of l registers R0, R1, R2, . . . Rl-1. Here, RBx at numeral 351 denotes any desired one of the banks, and numeral 352 denotes the register block in the bank.
As illustrated in FIG. 5(b), the global bank set 305 is configured of n global banks GB0, GB1, GB2, . . . and GBn-1, each of which is composed of k registers R0 ', R1 ', R2 ', . . . and Rk-1 '. Here GBy at numeral 353 denotes any desired one of the banks, and numeral 354 denotes the register block in the global bank.
With this information processing apparatus as the third embodiment, the number of banks m of the ring bank 304 and the number of banks n of the global bank set 305 can be altered during the running time of the information processing apparatus. That is, there are instructions for changing the number of banks m of the ring bank 304 to, e.g., 0, 4 and 8 and for changing the number of banks n of the global bank set 305 to, e.g., 2, 4, 8 and 16. A case where the number of banks of the ring bank 304 is greater than 1 is called the "ring bank mode," while a case where the number of banks of the ring bank 304 is 0 and where only the banks of the global bank set can be used is called the "global bank mode." The status of the apparatus concerning the number of banks of the ring bank 304 and the number of banks of the global bank set 305 is indicated by the bank mode register 323. As will be described later, there are instructions which set the contents of control registers and with which the bank mode can be altered, whereupon the bank mode register 323 changes so as to indicate the bank mode at the time of the alteration.
Regarding an instruction in which the content of the register displacement part 419 is an integer value i from 0 to (l-1), if the area register part 418 designates the global bank, a register i within a bank indicated by the global bank pointer 314 in FIG. 4 is used; if the area register part 418 designates the current bank, a register i within a bank indicated by the current register pointer 312 is used; and if the area register part 418 designates the previous bank, a register within a bank indicated by the previous bank pointer 311 is used.
FIG. 7 is a diagram showing one format of the bank status control instruction. As illustrated in FIG. 7, a bank status load instruction 421 has an operand designator part 422. In using this, five fields 423, 424, 425, 426 and 427 are provided in the memory. Bank No. to be put in the global bank pointer 314 is contained in the field 423 beforehand, bank No. to be put in the previous bank pointer 311 is contained in the field 424, bank No. to be put in the current bank pointer 312 is contained in the field 425, information to be put in the valid bank pointer 313 is contained in the field 426, and a location to be put in the bank stack pointer 324 is contained in the field 427. The head position of the series of fields is designated by the operand designator part 422. When the bank status load instruction 421 is executed under this state, the values of the fields 423 to 427 are set as the values of the bank control registers in accordance with the above correspondence. When a bank status store instruction is executed, the five pointers at the time of the execution are stored in memory positions indicated by the operand designator part 422 of the instruction as indicated at numerals 423, 424, 425, 426 and 427 in FIG. 7.
As instructions pertaining to the call of a subprogram, an advance ring bank instruction and a retrieve ring bank instruction exist besides a call instruction and a return instruction. At the subprogram call, information to be delivered as an argument is set in the register of a current bank, whereupon information called a save indicator vector as shown at numeral 429 in FIG. 8 is set in the 0th register 440 of the current bank 439, namely, a bank indicated by the current bank pointer 312. The save indicator vector 429 is information having a length of l bits where l denotes the number of registers in each bank. Letting i denote an integer value from 0 to (l-1), the value of the i-th bit bi at numeral 433 in the save indicator vector 429 is "1" if the content of the i-th register Ri at numeral 443 in the current bank 439 is to be saved, and the value is "0" if the content need not be saved. The 0th bit b0 at numeral 430 is always set to "1." When the call instruction is executed after setting the save indicator vector in the 0th register R0 440 of the current bank, an address next to the instruction is stacked in a stack for subprogram reference, and the execution of the instruction queue of the designated subprogram is started.
At the head of the instruction sequence of the subprogram, the advance ring bank instruction is executed. When the advance ring bank instruction is executed, the values of the current bank pointer (CBNR) 312 and the previous bank pointer (PBNR) 311 in FIG. 4 advance, and if necessary, also the values of the valid bank pointer (VBNR) 313 and the bank stack pointer (BSP) 324 change. Hereinbelow, the functions of the advance ring bank instruction will be elucidated using symbols CBNR1, PBNR1, VBNR1 and BSP1 which denote the values of the four pointers before the execution of the advance ring bank instruction, respectively, and symbols CBNR2, PBNR2, VBNR2 and BSP2 which denote the values of the four pointers after the execution of the advance ring bank instruction, respectively. In executing the advance ring bank instruction, first of all, the value CBNR1 which indicates the current bank before the execution of this instruction is set as the value PBNR2 of the previous bank pointer after the execution of the instruction, and the value of the current bank pointer is updated to a value mod(CBNR1 +1, m). Here, the mod(a, b) denotes a remainder obtained by dividing an integer a by an integer b, and m denotes the number of registers within one bank. On this occasion, if CBNR1 =VBNR1 holds, that is, if the value of the current bank pointer before the updating is equal to that of the valid bank pointer before the updating, then among the registers of a bank indicated by the value CBNR2 of each current bank pointer after the updating, the register indicated by the save indicator vector contained in the 0th register of the indicated bank has its content selectively saved in a place indicated by the bank stack pointer BSP1.
Further, the mechanism of this bank saving will be detailed with reference to FIG. 8. In the bank 439 indicated by the current bank pointer CBNR2 after the updating, there are l registers; the 0th register R0 440, the first register R1 441, the second register R2 442, . . . and the (l-1)-th register Rl-1 444. Also in the save indicator vector 429, there are l bits; the 0th bit b0 430, the first bit b1 431, the second bit b2 432, . . . and the (l-1)-th bit bl-1 434. If, for 0≦i≦l-1, the content of the i-th register 443 is to be saved, the i-th bit bi 433 of the save indicator vector is set at "1" beforehand, and if the content need not be saved, the bit bi is set at "0." This save indicator vector 429 is stored in the 0th register R0 440 of the bank 439. If the value CBNR1 of the current bank pointer before the updating, namely, the value PBNR2 of the previous bank pointer after the updating is equal to the value VBNR1 of the valid bank pointer before the updating, then the save indicator vector 429 which is stored in the 0th register R0 440 of the new current bank 439 indicated by the value CBNR2 of the current bank pointer after the updating is scanned in a direction from the bit bl-1 434 toward the bit b0 430. If the bit bi for 0≦i≦(l-1) is "1", the value of the bank stack pointer (BSP) 324 is advanced in the amount of one register, and the content of the register Ri is stored in a position indicated by the new value of the bank stack pointer in the bank stack 325. If the bit bi is "0" , the bank stack pointer 324 is not advanced, and the store of the register Ri is not executed, either. The value of the bank stack pointer 324 at the time at which the save indicator vector 429 has been scanned while changing i to l-1, l-2, . . . , 2, 1 and 0 and the necessary register store operations have been repeated, is the value BSP2 updated by the advance ring bank instruction. Since the 0th bit b0 of the save indicator vector is always set at "1", the value of the register R0 of the saved bank is stored in a position indicated by the bank stack pointer after the updating, namely, the uppermost part of the bank stack 325.
When this bank save operation has ended, the new value VBNR2 of the valid bank pointer 313 is set at VBNR2 =mod(CBNR1 +1, m) on the basis of the value VBNR1 thereof before the updating.
In returning from the subprogram, a function value or the like to be given back to a calling side is set in the register of the current bank if it is necessary, and thereafter the retract ring bank instruction is executed, followed by the execution of the return instruction. When the retrieve ring bank instruction is executed, the values of the current bank pointer CBNR 312 and the previous bank pointer PBNR 311 retract, and the values of the valid bank pointer VBNR 313 and the bank stack pointer BSP 324 change if it is necessary. Hereinbelow, the functions of the retract ring bank instruction will be elucidated using symbols CBNR3, PBNR3, VBNR3 and BSP3 which denote the values of the four pointers before the execution of this instruction, respectively, and symbols CBNR4, PBNR4, VBNR4 and BSP4 which denote the values of the four pointers after the execution of the instruction, respectively.
The mechanism of this bank restoration will be described with reference to FIG. 8. First, the content of the uppermost part of the bank stack 325 indicated by the value BSP3 of the bank stack pointer 324 before the updating is put in the 0th register R0 of a bank indicated by the value PBNR4 of the previous bank pointer 311 after the updating, and the value of the bank stack pointer 324 is retracted in the amount of one register. In the uppermost part of the bank stack 325, the save indicator vector has been faced at the time of the subprogram call. With the above operations, therefore, the save indicator vector 429 is put in the R0 register 440. Subsequently, the content of the save indicator vector 429 is scanned in a direction from the bi bit 431 toward the bl-1 bit 434. If the value of the bi bit 433 for 1≦i≦l-1 is "1," the data of a position indicated by the new value of the bank stack pointer 324 within the bank stack 325 is transferred to the Ri register 443, and the value of the bank stack pointer 324 is retracted in the amount of one register. If the value of the bi bit is "0," the transfer to the Ri register 443 is not performed, and the bank stack pointer 324 is not retracted, either. The value of the bank stack pointer 324 obtained as the result of repeating these operations (l-1) times while changing i to 1, 2, 3, . . . and l-1, is the value BSP4 thereof after the updating by the retract ring bank instruction. Thereafter, the value of the valid bank pointer 313 is retracted by one. That is, VBNR4 =mod(VBNR3 -1, m) is established. This value is the same as the value of the previous bank pointer after the updating.
As instructions for altering a bank status, there are a control register load instruction MTCR and a control register store instruction MFCR which alter control information indicating the status of the ring bank or the global bank, and which can also be used. With the two instructions, it is possible to individually set and individually refer to the respective values of the current bank pointer 312, previous bank pointer 311, valid bank pointer 313, global bank pointer 314, bank stack pointer 324 and bank mode register 323 in FIG. 4. When the content of the bank mode register 323 is changed, the number of banks of the ring bank and the number of banks of the global bank set can be changed. When the number of banks of the ring bank is set at 0, the global bank mode is established in which all the banks can be used as global banks. That is, in the global bank mode, banks having been used as the ring bank in another mode can also be utilized as the global banks. With an instruction which is executed in the global bank mode, the address mode part thereof cannot designate a previous bank or a current bank. Besides, in the global bank mode, the advance ring bank instruction and the retract ring bank instruction cannot be used.
FIG. 9 is an arrangement diagram of the essential portions of an information processing apparatus showing the fourth practicable example based on the construction as shown in FIG. 4. In this example, a register block 503 in an instruction processor 501 is configured of n global banks GB0 at numeral 510, GB1 at numeral 511, . . . and GBn-1 at numeral 513, and n ring banks R0 at numeral 520, R1 at numeral 521, . . . and Rn-1 at numeral 523 Each of the global banks GB0, GB1, . . . and GBn-1 is composed of k' registers as shown in FIG. 5(b). As shown in FIG. 5(a), each of the ring banks R0, R1, . . . and Rn-1 is composed of m banks, each of which is composed of l registers.
In this manner, in the present embodiment, the number of registers which can be assigned is determined by the number of bits of an area register which is larger than the number of bits of the register designator part of an instruction. Therefore, even when the register designator part of each individual instruction is short, a very large number of registers can be used. Moreover, by exploiting the fact that the large number of registers can be used, the register block can be utilized as one or several stacks. Therefore, even in a case where a register block of large capacity is included, the subprogram call or the task switch can be executed without saving and restoring registers or merely by saving and restoring a very small number of area registers, and high-speed processing which uses high-speed registers in large quantities can be realized without an overhead. Especially with the third embodiment, in the ring bank mode, the save and restore of registers attendant upon the call and return of the subprogram are unnecessary except when the current bank pointer advances beyond the valid bank pointer and when the previous bank pointer retracts beyond the valid bank pointer, and hence, the speed of the subprogram reference can be raised. Besides, it is possible to allot different global banks to the respective programs which are asynchronously executed and to draw up a program which uses a global bank allotted in dedicated fashion, as regards programs each of which uses only a small number of registers. In such a case, therefore, the replacement of registers attendant upon the change-over of programs can be avoided, and the speed of the program change-over such as the task switch can be raised. At the time of the subprogram reference, an argument and a function value can be delivered through registers without copying, under the condition that a current bank till then is regarded as the next previous bank, and hence, the speed of the subprogram reference can be raised. Even in a case where the ring bank needs to be saved and restored, a save indicator register is held in each bank of the ring bank, whereby the registers to be saved and restored can be limited to truly necessary ones only. Therefore, the processing can be raised in speed.
1. An information processing apparatus comprising main memory means having a main memory address space, main memory access means for accessing said main memory means, a register block having a register address space and furnished with general registers and an area register in combination, instruction decode means for decoding an instruction which has an area register part assigning the area register indicating a position of a register area included in said register block and a register displacement part for assigning a relative register position within the register area lying at the indicated position, register access means for accessing the register lying at the relative register position in accordance with an output of said instruction decode means, and arithmetic means for operating data from said main memory means and the accessed register.
2. An information processing apparatus according to claim 1, wherein a plurality of area registers to be assigned as stated above are provided, and an address in said main memory means and an address in the register lying at the relative register position are assigned by an identical instruction.
3. An information processing apparatus according to claim 1, wherein a value for assigning any desired register of said register block is set in said area register.
4. An information processing apparatus according to claim 1, wherein said area register is a special-purpose register which is provided separately from said register block and which indicates the position of the register area.
5. An information processing apparatus according to claim 1, wherein the area register is provided in a specific register area included in said register block, the area register for indicating a relative position within said specific register area is assigned by the area register part of the instruction which uses the general register, said specific register area is indicated by the area register part of each of the instruction which sets a desired value in said area register and an instruction which refers to the set value, and the relative position within said specific register is assigned by the register displacement part of said each instruction.
6. An information processing apparatus according to claim 1, wherein said register access means includes an OR circuit which adds a value possessed in the area register assigned by a register address as a numerical value stored in said area register part, and a value given by said register displacement part.
7. An information processing apparatus according to claim 1, wherein the plurality of registers included in said register block is put into one sequence in a relationship of next registers and previous registers, and the next register of a tail register in said sequence forms a head register, while the previous register of the head registers forms the tail register.
8. An information processing apparatus comprising main memory means having a main memory address space; a register block having a register address space and furnished with area registers; instruction decode means for decoding an instruction having an area register part which assigns any of the plurality of registers for indicating a position of a register bank to be used among a plurality of register banks that form register areas included in said register block and consisting of predetermined equal numbers of registers, a register displacement part which assigns a relative register position within the register bank lying at the indicated position, and a main memory designator part which assigns an address of said main memory means; register access means for accessing the register lying at the relative register position in accordance with an output of said instruction decode means; main memory access means for accessing said main memory means in accordance with another output of said instruction decode means; and arithmetic means for operating data from said main memory means and said register block.
9. An information processing apparatus according to claim 8, wherein the plurality of register banks each consisting of the predetermined number of registers are arranged in a bank row in which they are put into one sequence in a relationship of previous register banks and next register banks, and the next register bank to a tail register bank of the bank row is set as a head register bank, while the previous register bank to the head register bank is set as the tail register bank, whereby said register banks are connected as a ring-shaped ring bank.
10. An information processing apparatus according to claim 9, wherein said plurality of register banks consist of at least one ring bank in which the individual register banks composed of the predetermined number of registers are connected in a ring shape, and at least one global bank set which includes a register area provided separately from said ring bank.
11. An information processing apparatus according to claim 10, wherein among the plurality of register banks of said ring bank, the register bank which is chiefly used at one point of time is set as a current bank, the register bank which is used as a current bank at a point of time before change-over of used statuses of said ring bank is set as a previous bank, and the register bank which is used at one point of time in said global bank set is set as a global bank at that point of time, and as kinds of the area registers, said register banks are respectively assigned by a current bank pointer indicating a position of said current bank, a previous bank pointer indicating a position of said previous bank and a global bank pointer indicating a position of said global bank.
12. An information processing apparatus according to claim 11, wherein as instructions which update use positions of said current bank and said previous bank within said ring bank, there are set an advance ring bank instruction according to which a value of said current bank pointer before the updating is set as a value of said previous bank pointer after the updating, and a value of said current bank pointer after the updating is set as a position of a bank next to the current bank before the updating, and a retrieve ring bank instruction according to which a value of said previous bank pointer before the updating is set as a value of said current bank pointer before the updating, and a value of said previous bank pointer after the updating is set as a position of a bank immediately previous to the previous bank before the updating.
13. An information processing apparatus according to claim 12, wherein there are set a valid bank pointer which indicates a boundary of valid information items in said ring bank and a bank stack pointer which indicates a position of a bank stack being a bank save area within said main memory, and wherein in advancing the use position of said ring bank, necessity for bank save is decided from a relation between the value of said current bank pointer and the value of said valid bank pointer; when the bank save has been decided necessary, it is so performed that a content of the register bank indicated by said current bank pointer after the updating is stored in the bank stack indicated by said bank stack pointer; said bank stack pointer is advanced in conformity with an amount of the store; and the value of said valid bank pointer is updated so as to indicate the next bank in said ring bank; while in retrieving the use position of said ring bank, necessity for bank restore is decided from a relation between the value of said previous bank pointer and the value of said valid bank pointer; when the bank restore has been decided necessary, it is so performed that a content of the bank stack indicated by the value of said bank stack pointer before the updating is transferred to the register bank indicated by said previous bank pointer after the updating; said bank stack pointer is retrieved in conformity with an amount of the transfer; and the value of said valid bank pointer is updated so as to indicate the immediately previous bank in said ring bank.
14. An information processing apparatus according to claim 13, wherein save indicator information items which indicate the registers required to be saved and restored in the respective register areas or register banks are recorded in the corresponding register areas or register banks beforehand, and wherein when it has become necessary later to actually save one of said register areas or register banks, only the register indicated by the save indicator information corresponding thereto is selectively delay-saved, and when a content of the saved register area or register bank is to be restored, only the register indicated by the save indicator information extracted before is restored.
15. An information processing apparatus according to claim 11, for said current bank pointer, said previous bank pointer and said global bank pointer, and a valid bank pointer and a bank stack pointer, a bank status load instruction which sets values of the pointers and a bank status store instruction which stores values of the pointers are used.
16. An information processing apparatus according to claim 11, wherein as regards the current bank as well as the previous bank and the global bank, within one subprogram, information to be delivered as an argument from an upper subprogram having called said one subprogram and information to be given back to said upper subprogram are allotted to said previous bank, information to be delivered as an argument to a lower subprogram which said one subprogram calls and information to be received as a function value from said lower subprogram are allotted to said current bank, and an instruction queue for executing a retrieve ring bank at return from the subprogram is placed, whereby the arguments and the function values are transferred among the subprograms through the registers.
17. An information processing apparatus according to claim 8, wherein the register banks to be used in one program which is run asynchronously with another program are allotted as ones different from the register banks to be used in said other program.
18. An information processing apparatus according to claim 17, wherein one global bank and one ring bank are paired, and a plurality of such pairs are provided, whereby one pair consisting of said global bank and said ring bank is allotted to each of a plurality of programs which are asynchronously run.
19. An information processing apparatus according to claim 18, wherein the registers constituting said each register bank number a power of 2.
20. An information processing apparatus according to claim 19, wherein the position of said each register is expressed by an address being a numerical value, the bank next to any other bank than a tail bank in said ring bank denotes the register area of the address adjoining the register address of said any other bank, and the bank next to said tail bank denotes the register area of a head address.
21. An information processing apparatus according to claim 20, wherein a next bank pointer indicating the position of the next bank and a previous bank pointer indicating the position of the previous bank are used for said each register bank.
22. An information processing apparatus according to claim 21, wherein numbers of the registers which are included in the respective global banks of said global bank set are set to be identical, and as to said plurality of ring banks, numbers of the registers which are included in each of the banks constituting the ring bank are set to be equal to one another.
23. An information processing apparatus according to claim 22, wherein said main memory access means is situated within an instruction processor along with an instruction decoder, and using said access means, an instruction queue afforded from outside said information processing apparatus and stored in said main memory is executed in said instruction processor.
24. An information processing apparatus according to claim 23, wherein said register block, said register access means and said arithmetic means are implemented in an identical semiconductor chip.
US08/459,965 1986-04-14 1995-06-02 RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing Expired - Lifetime US5517664A (en)
JP61-84552 1986-04-14
JP61085442A JP2545789B2 (en) 1986-04-14 1986-04-14 The information processing apparatus
US07/037,843 US5214786A (en) 1986-04-14 1987-04-13 RISC system performing calls and returns without saving or restoring window pointers and delaying saving until multi-register areas are filled
US07/945,930 US5307502A (en) 1986-04-14 1992-09-17 Data processing system having multiple register management for call and return operations
US08/183,830 US5450610A (en) 1986-04-14 1994-01-21 RISC system capable of performing calls and returns without advancing or restoring window pointers
US08/459,965 US5517664A (en) 1986-04-14 1995-06-02 RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing
US08/183,830 Continuation US5450610A (en) 1986-04-14 1994-01-21 RISC system capable of performing calls and returns without advancing or restoring window pointers
US5517664A true US5517664A (en) 1996-05-14
ID=13858982
US07/037,843 Expired - Lifetime US5214786A (en) 1986-04-14 1987-04-13 RISC system performing calls and returns without saving or restoring window pointers and delaying saving until multi-register areas are filled
US07/945,930 Expired - Lifetime US5307502A (en) 1986-04-14 1992-09-17 Data processing system having multiple register management for call and return operations
US08/183,830 Expired - Lifetime US5450610A (en) 1986-04-14 1994-01-21 RISC system capable of performing calls and returns without advancing or restoring window pointers
US08/459,965 Expired - Lifetime US5517664A (en) 1986-04-14 1995-06-02 RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing
US (4) US5214786A (en)
EP (2) EP0517282B1 (en)
JP (1) JP2545789B2 (en)
KR (1) KR900005285B1 (en)
DE (4) DE3752287D1 (en)
JPH02143329A (en) * 1988-11-25 1990-06-01 Toshiba Corp Processor system
JPH02187825A (en) * 1989-01-13 1990-07-24 Mitsubishi Electric Corp Computer
JPH04242433A (en) * 1991-01-17 1992-08-31 Nec Corp Microprocessor
JP2668456B2 (en) * 1991-01-22 1997-10-27 三菱電機株式会社 Bit search circuit and a data processing apparatus provided therewith
US5438669A (en) * 1991-11-20 1995-08-01 Hitachi, Ltd. Data processor with improved loop handling utilizing improved register allocation
WO1995032466A1 (en) * 1994-05-19 1995-11-30 Vlsi Technology, Inc. Flexible register mapping scheme
JPH1011352A (en) * 1996-06-19 1998-01-16 Hitachi Ltd Data processor and its register address converting method
JP2002073330A (en) * 2000-08-28 2002-03-12 Mitsubishi Electric Corp Data processing device
JP3763518B2 (en) * 2001-05-29 2006-04-05 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｓｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ Compiler, the compilation method and program
US7103754B2 (en) * 2003-03-28 2006-09-05 International Business Machines Corporation Computer instructions for having extended signed displacement fields for finding instruction operands
GB1281167A (en) * 1969-01-02 1972-07-12 Plessey Telecomm Res Ltd Improvements relating to data processing systems
JPS53142841A (en) * 1977-05-19 1978-12-12 Toshiba Corp Data processor
JPS5931734B2 (en) * 1977-10-25 1984-08-03 Digital Equipment Corp
JPS5576448A (en) * 1978-12-05 1980-06-09 Fujitsu Ltd Multi-group register control system
JPS5616248A (en) * 1979-07-17 1981-02-17 Matsushita Electric Ind Co Ltd Processing system for interruption
JPS6017130B2 (en) * 1980-06-06 1985-05-01 Nippon Electric Co
JPS59105152A (en) * 1982-12-07 1984-06-18 Fujitsu Ltd Collectively storing method of plural registers
JPH0133854B2 (en) * 1983-09-02 1989-07-17 Hitachi Ltd
JPH0258649B2 (en) * 1984-08-20 1990-12-10 Tokyo Shibaura Electric Co
1986-04-14 JP JP61085442A patent/JP2545789B2/en not_active Expired - Lifetime
1987-04-09 KR KR8703382A patent/KR900005285B1/en not_active IP Right Cessation
1987-04-13 US US07/037,843 patent/US5214786A/en not_active Expired - Lifetime
1987-04-14 DE DE3752287A patent/DE3752287D1/en not_active Expired - Fee Related
1987-04-14 DE DE3752287T patent/DE3752287T2/en not_active Expired - Lifetime
1987-04-14 DE DE87105507A patent/DE3789122D1/en not_active Expired - Fee Related
1987-04-14 DE DE3789122T patent/DE3789122T2/en not_active Expired - Lifetime
1987-04-14 EP EP92110395A patent/EP0517282B1/en not_active Expired - Lifetime
1987-04-14 EP EP87105507A patent/EP0241909B1/en not_active Expired - Lifetime
1992-09-17 US US07/945,930 patent/US5307502A/en not_active Expired - Lifetime
1994-01-21 US US08/183,830 patent/US5450610A/en not_active Expired - Lifetime
1995-06-02 US US08/459,965 patent/US5517664A/en not_active Expired - Lifetime
"A VLSI RISC" by D. A. Patterson et al., Computer, Sep. 1989, IEEE, pp. 8-21.
A VLSI RISC by D. A. Patterson et al., Computer, Sep. 1989, IEEE, pp. 8 21. *
US7966474B2 (en) 2008-02-25 2011-06-21 International Business Machines Corporation System, method and computer program product for translating storage elements
JP2545789B2 (en) 1996-10-23
DE3789122D1 (en) 1994-03-31
EP0241909A2 (en) 1987-10-21
DE3752287D1 (en) 1999-09-02
EP0241909B1 (en) 1994-02-23
EP0517282A1 (en) 1992-12-09
DE3752287T2 (en) 2000-03-23
US5307502A (en) 1994-04-26
US5450610A (en) 1995-09-12
EP0241909A3 (en) 1990-03-28
DE3789122T2 (en) 1994-09-01
JPS62242243A (en) 1987-10-22
US5214786A (en) 1993-05-25
EP0517282B1 (en) 1999-07-28
KR900005285B1 (en) 1990-07-27
KR920003274B1 (en) 1992-04-27 Apparatus for stack control employing mixed handware registers and memory
CA1153470A (en) 1983-09-06 Vector to raster processor