Source: http://www.google.ca/patents/US9049125
Timestamp: 2017-09-21 01:39:23
Document Index: 342231515

Matched Legal Cases: ['application No. 60', 'Application No. 10', 'Application No. 10', 'Application No. 02816581', 'Application No. 02816581', 'Application No. 02816581', 'Application No. 10', 'Application No. 02816581', 'Application No. 02761480', 'Application No. 02761480', 'Application No. 02761480']

Patent US9049125 - General input/output architecture, protocol and related methods to implement ... - Google Patents
An enhanced general input/output communication architecture, protocol and related methods are presented....http://www.google.ca/patents/US9049125?utm_source=gb-gplus-sharePatent US9049125 - General input/output architecture, protocol and related methods to implement flow control
Publication number US9049125 B2
Application number US 13/729,953
Also published as CN1547704A, CN1547705A, CN1547823A, CN100357922C, CN100367254C, CN100409606C, DE60213616D1, DE60213616T2, DE60222782D1, DE60226627D1, EP1419446A1, EP1419446B1, EP1421501A1, EP1421501B1, EP1442548A2, EP1442548B1, US7152128, US7231486, US7353313, US7536473, US8566473, US8819306, US9071528, US9088495, US9565106, US9602408, US9736071, US20030115380, US20030145134, US20030158992, US20070038793, US20090193164, US20130117474, US20130254451, US20130254452, US20130268712, US20140129747, US20140185436, US20140189174, US20150178241, WO2003019391A2, WO2003019391A3, WO2003019393A1, WO2003019394A1
Publication number 13729953, 729953, US 9049125 B2, US 9049125B2, US-B2-9049125, US9049125 B2, US9049125B2
Patent Citations (172), Non-Patent Citations (49), Referenced by (4), Classifications (24)
US 9049125 B2
a device comprising logic to:
maintain flow control information for each of a plurality of virtual channels, wherein, the flow control information associated with a particular virtual channel of the plurality of virtual channels is to include an amount of consumed flow control credits and a flow control credit limit, wherein each flow control credit of the amount of consumed flow control credits is to be of a type from a set comprising posted request header flow control credits, posted request data payload flow control credits, non-posted request data payload flow control credits, non-posted request data payload flow control credits, completion header flow control credits, and completion data payload flow control credits, and wherein the amount of consumed flow control credits is to indicate an amount of flow control credits consumed by transaction layer packets since an initialization of the respective virtual channel;
identify initialization of flow control for the particular virtual channel, wherein initialization of the flow control is to include receipt of a value of the flow control credit limit associated with the particular virtual channel;
identify a second amount of flow control credits to be consumed by one or more transaction layer packets; and
determine whether to transmit the one or more transaction layer packets using the particular virtual channel based at least in part on the amount of consumed flow control credits and flow control credit limit for the particular virtual channel.
identifying initialization of a virtual channel of a general purpose I/O interconnect, wherein initialization of the virtual channel includes identification of a flow control credit limit for the virtual channel;
identifying an amount of flow control credits associated with one or more transaction layer packets; and
determining whether to transmit the one or more transaction layer packets based at least in part on the flow control credit limit.
3. The method of claim 2, further comprising transmitting the one or more transaction layer packets based on the determination.
4. The method of claim 2, further comprising delaying transmission of the one or more transaction layer packets based on the determination.
5. The method of claim 2, further comprising receiving, from a receiver, a flow control packet identifying the flow control credit limit.
6. The method of claim 2, further comprising receiving, from a receiver, a flow control packet identifying an updated flow control credit limit.
This application is a continuation of U.S. application Ser. No. 12/395,497, filed Feb. 27, 2009, which is a continuation of U.S. application Ser. No. 10/227,601 filed Aug. 23, 2002, now U.S. Pat. No. 7,536,473, issued on May 19, 2009, which claims the benefit of provisional application No. 60/314,708 filed on Aug. 24, 2001.
FIG. 1 is a block diagram of an electronic appliance incorporating one or more aspects of an embodiment of the invention to facilitate communication between one or more constituent elements of the appliance:
FIG. 4 is a graphical illustration of an example communication link comprising one or more virtual channels to facilitate communication between one or more elements of the electronic device, according to one aspect of the invention:
FIG. 5 is a flow chart of an example method to provide isochronous communication resources within the EGIO architecture, according to one embodiment of the invention:
Completer ID: A combination of one or more of a completer's bus identifier (e.g. number), device identifier, and a function identifier which uniquely identifies the completer of the request;
Host Bridge: Connects a host CPU complex to a Root Complex; Host bridge may provide Root Complex:
Message Space: One of the four address spaces of the EGIO architecture. Special cycles as defined in PCI are included as a subset of Message Space and, accordingly, provides an interface with legacy device(s):
Memory space (706) transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location. Memory space transactions may use two different address formats. e.g., a short address format (e.g., 32-bit address) or a long address format (e.g., 64-bits long). According to one example embodiment, the EGIO architecture provides for conventional read, modify, and write sequences using lock protocol semantics (i.e., where an agent may well lock access to modified memory space). More particularly, support for downstream locks are permitted, in accordance with particular device rules (bridge, switch, end-point, legacy bridge). As introduced above, such lock semantics are supported in the support of legacy devices.
With respect to traffic initiated by host processor 102, virtual channels may require ordering control based on default order mechanism rules, or the traffic may be handled completely out of order. According to one example implementation. VCs comprehend the following two types of traffic: general purpose IO traffic, and Isochronous traffic. That is, in accordance with this example implementation, two types of virtual channels are described: (1) general purpose IO virtual channels, and (2) isochronous virtual channels.
BWmax =Y/t. [3]
BWgranularity =Y/T. [4]
N link=BWlink/BWgranularity [5]
Transaction latency for an EGIO link 112 or the EGIO fabric is defined as the delay from the time a transaction is posted at the transmission end to the time it is available at the receiving end. This applies to both read and write transactions. In this regard. Lfabric depends on the topology, latency due to each link 112 and arbitration point in the path from requester to completer.
With reference to FIG. 9 a graphical illustration of an example transaction layer protocol is presented, in accordance with the teachings of the present invention. In accordance with the illustrated example implementation of FIG. 9. TLP header 900 is presented comprising a format field, a type field, an extended type/extended length (ET/EL) field, and a length field. Note that some TLPs include data following the header as determined by the format field specified in the header. No TLP should include more data than the limit set by MAX_PAYLOAD_SIZE. In accordance with one example implementation, TLP data is four-byte naturally aligned and in increments of a four-byte double word (DW).
⋮ •… •0000 0000 = 1 DW •0000 0001 = 2 DW •1111 1111 = 256 DW
In accordance with one aspect of the present invention, the concept of a flow control “credit” is introduced, wherein a receiver shares information about (a) the size of the buffer (in credits), and (b) the currently available buffer space with a transmitter for each of the virtual channel(s) established between the transmitter and the receiver (i.e. on a per-virtual channel basis). This enables the transaction layer 202 of the transmitter to maintain an estimate of the available buffer space (e.g., a count of available credits) allocated for transmission through an identified virtual channel, and proactively throttle its transmission through any of the virtual channels if it determines that transmission would cause an overflow condition in the receive buffer.
Switch devices—CPLD: FCU equal to the largest possible setting of the maximum payload size of the device, or the largest read request the device will ever generate, whichever is smaller,
To proactively inhibit the transmission of information if to do so would cause receive buffer overflow, a transmitter is permitted to transmit a type of information if the credits consumed count plus the number of credit units associated with the data to be transmitted is less than or equal to the credit limit value. i.e.,
When a transmitter receives flow control information for completions (CPLs) indicating non-infinite credits (i.e. <255 FCUs), the transmitter will throttle completions according to the credit available. When accounting for credit use and return, information from different transactions is not mixed within a credit. Similarly, when accounting for credit use and return, header and data information from one transaction is never mixed within one credit. Thus, when some packet is blocked from transmission by a lack of flow control credit(s), transmitters will follow the ordering rules (above) when determining what types of packets should be permitted to bypass the “stalled” packet.
LinkActDefer (LAD)—Normal operation disrupted. Physical Layer attempting to resume
As introduced above, the transaction layer 202 provides TLP boundary information to Data Link Layer 204, enabling the DLL 204 to apply a Sequence Number and cyclical redundancy check (CRC) error detection to the TLP. According to one example implementation, the Receive Data Link Layer validates received TLPs by checking the Sequence Number. CRC code and any error indications from the receive Physical Layer. In case of error in a TLP, Data Link Layer Retry is used for recovery.
When DLLR_IN_PROGRESS is clear. Received TLPs are checked as described below
not pass any TLPs to the Physical Layer for Transmission until an Acknowledgement DLLP has been received from the Component on the other side of the Link.
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49 USPTO Sep. 30, 2014 Notice of Allowance in Application U.S. Appl. No. 13/730,061.
International Classification H04L1/18, G06F13/12, H04L12/801, G06F13/38, G06F13/40, G06F13/00, G06F13/24, G06F13/42, G06F13/14, G06F3/00, G06F15/16
Cooperative Classification H04L47/30, H04L47/10, G06F13/4221, G06F5/06, G06F13/4059, G06F13/4269, G06F13/124, G06F13/4252, G06F13/385, G06F13/4282, G06F13/42, G06F13/4265