Source: http://www.google.es/patents/US5386518?hl=es&dq=flatulence
Timestamp: 2013-12-10 04:00:26
Document Index: 706235475

Matched Legal Cases: ['art=0', 'art=3', 'art=3', 'art=2', 'art=2', 'art=0', 'art=0', 'art=3', 'art=0']

Patente US5386518 - Reconfigurable computer interface and method - Google PatentesB�squeda Im�genes Maps Play YouTube Noticias Gmail Drive M�s » B�squeda avanzada de patentes | Iniciar sesi�n B�squeda avanzada de patentesPatentesA reconfigurable computer interface for use in interfacing a first subsystem to a second subsystem including a reconfigurable state machine mechanism for generating a plurality of interface control signals in accordance with a state table in response to a plurality of mode control signals. A first mechanism...http://www.google.es/patents/US5386518?utm_source=gb-gplus-sharePatente US5386518 - Reconfigurable computer interface and method N�mero de publicaci�nUS5386518 ATipo de publicaci�nConcesi�n N�mero de solicitudUS 08/017,222 Fecha de publicaci�n31 Ene 1995 Fecha de presentaci�n12 Feb 1993 Fecha de prioridad12 Feb 1993TarifaPagadasTambi�n publicado comoDE69416011D1, DE69416011T2, EP0610868A1, EP0610868B1 N�mero de publicaci�n017222, 08017222, US 5386518 A, US 5386518A, US-A-5386518, US5386518 A, US5386518A InventoresGregory D. Bolstad, Dennis J. Reagle Cesionario originalHughes Aircraft CompanyExportar citaBiBTeX, EndNote, RefManCitas de patentes (14), Citada por (35), Clasificaciones (4), Eventos legales (6) Enlaces externos: USPTO, Cesi�n de USPTO, EspacenetReconfigurable computer interface and methodUS 5386518 A Resumen A reconfigurable computer interface for use in interfacing a first subsystem to a second subsystem including a reconfigurable state machine mechanism for generating a plurality of interface control signals in accordance with a state table in response to a plurality of mode control signals. A first mechanism is included for generating the state table and a second mechanism is provided for generating the mode control signals with each transmitted to the reconfigurable state machine mechanism. In a preferred embodiment, an initiation logic device generates and downloads a state table and a plurality of mode control signals to a programmable state machine when the reconfigurable computer interface is utilized to connect a new external peripheral device to a signal processing system. The state table defines the characteristics of the state machine and the state machine controls the operation of the reconfigurable computer interface. The programmable state machine utilizes the present state, the state table and the mode control signals to determine the next machine state which provides rapid and convenient reconfigurability of the interface circuit to connect a variety of external devices to the signal processing system. A bus sizing register circuit is included to modify the word size of a plurality of data signals and temporary memory is also included.
12. A general purpose, reconfigurable parallel-to-parallel interface system for interfacing a first parallel data bus from an external peripheral device to a second parallel data bus from a signal processing system, the interface system comprising:buffer memory storage means for providing temporary storage of a plurality of data signals transmitted between said external peripheral device and said signal processing device, said buffer memory storage means operating in response to memory storage control signals; programmable bus sizing means for modifying the word size of a plurality of data signals transmitted between said external peripheral device and said signal processing device in response to bus sizing control signals; level translating means connected to said first data bus for translating the electrical levels of a plurality of data signals on said first data bus to electrical levels of said reconfigurable interface system; reconfigurable state machine means for generating a plurality of interface control signals in accordance with a state table in response to a plurality of external condition signals, said external condition signals including mode control signals, said interface control signals including said memory storage control signals and said bus sizing control signals; means for establishing a data path through said interface system for connecting said first data bus to said second data bus, said data path comprising said buffer memory storage means, said bus sizing means and said level translating means; control signal path means for establishing a control signal path between said state machine means and said external peripheral device, said control signal path being separate from said data path through the interface system and for carrying handshake control signals between said state machine means and external peripheral device, said handshake control signals comprising said external condition signals; host processor means for generating said state table and said mode control signals for said state machine means; and wherein said state machine means operates autonomously from said host processor means upon receiving said state table and said mode control signals until said host processor generates a fresh state table and mode control signals to reconfigure the interface system. Descripci�n
The buffer RAM 130 shown in FIG. 1 is located within the data path between the external peripheral device 104 and the signal processing system 102. Under the direction of control signals from the state machine 108, the buffer RAM 130 temporarily stores data transmitted from the external device 104 to the processing system 102. Likewise, the buffer RAM 130 provides temporary storage for data transmitted from the internal circuitry of the processing system 102 to the external device 104. In the specific implementation shown in FIG. 3, the buffer RAM 130 is shown as a (32K
Each state machine 108 and 162 is implemented with a registered static downloadable RAM 120 that is (4K channel. The RAM 120 has sixteen registered outputs which provide four bits of present state, four bits of pack/unpack register command, six I/O handshake lines, port direction control, memory access request and the transfer complete interrupt. The twelve address inputs to the RAM 120 receive four bits of the present state feedback, two bits of the microprocessor mode control bits, four I/O handshake lines, memory access granted from memory arbitration 146 and the address generator done interrupt from the memory control & address generator 148. The downloadable RAM 120 can be loaded with specific state table data from the host 106.
IDLE.sub.-- H
The state machine 108 has been loaded with the appropriate state table data and the microprocessor command word was set to zero (upstart=0) which means "Do Nothing". The state machine 108 will automatically transition to the IDLE.sub.-- L state at the beginning of the next clock cycle (time increment). During this state, the reconfigurable computer interface 100 outputs the sensor clock (SCLK) to a HIGH level and holds the ready signal (CRDY) to an inactive HIGH level.
IDLE.sub.-- L
The first path is back to IDLE.sub.-- H and this path is selected if the microprocessor command word is still set to zero. As long as the command word is set to zero, the states will cycle between IDLE.sub.-- H and IDLE.sub.-- L. The purpose for this cycle is to provide a sensor clock to the external device 104.
The second path is to the OUT.sub.-- GO state. The transition to this path occurs when the address generator signal INTAG.sub.-- L is HIGH and the microprocessor command signal has been set to three (upstart=3). The HIGH INTAG.sub.-- L signal is an indication that the address generator has been initialized for the impending transfer of data. This signal stays high until the required number of data words have been transferred. The command word "upstart=3" is a command by the microprocessor to transition to the data output mode.
The third path is to the CIO.sub.-- IN state. The transition to this path occurs when the INTAG.sub.-- L signal is HIGH and the microprocessor command word is set to two (upstart=2). The HIGH INTAG.sub.-- L signal is an indication that the address generator has been initialized for the impending transfer of data. The signal stays high until the required number of data words have been transferred. The command word "upstart=2" is a command by the microprocessor to transition to the data input mode.
During the period that the state machine is in the IDLE.sub.-- L state, the interface 100 outputs the sensor clock (SCLK) to a LOW level and holds the ready signal (CRDY) to an inactive HIGH level.
CIO.sub.-- IN
This state was entered from one of three states. During this state, the ready signal is set active (CRDY=LOW) and the read/write signal is set to write to memory (RDWRL=LOW). This state transitions to the REQ.sub.-- MEM.sub.-- IN state when the external device 104 is ready (RERDY=LOW) unless the microprocessor interrupts the transition by sending a "do nothing" command word (upstart=0).
The first possible path is from the IDLE.sub.-- L state. This would imply that the transfer is just beginning and the interface 100 has been initialized to input data from an external device 104.
REQ.sub.-- MEM.sub.-- IN
This state is entered from the CIO.sub.-- IN state. The function of this state is to request a memory location (MEMRQ=LOW) to store the input data. The next state to transition to is determined by the external ready and the memory location granted signals. The memory location request must be granted (MEMGNT=HIGH) to leave this state. With the memory grant present, the next state will be MEM.sub.-- IN if the external ready signal is inactive (RERDY=HIGH) and will be DELAY1 if the external ready signal is active (RERDY=LOW).
MEM.sub.-- IN
This state is entered from the REQ.sub.-- MEM.sub.-- IN state. During this state, the data is loaded into memory and the request for a memory location is deasserted (MEMRQ=HIGH). The state machine 108 remains in this state until the external ready becomes active (RERDY=LOW) or the address generator signals that the transfer is complete by setting the transfer complete interrupt (INTAG.sub.-- L=LOW). If the transfer is not complete and the external device 104 becomes ready, the state transitions back to REQ.sub.-- MEM.sub.-- IN. Under optimum conditions, the state machine would now cycle between REQ.sub.-- MEM.sub.-- IN and MEM.sub.-- IN until the address generator interrupt occurs signaling the end of the transfer.
DELAY1 is a state entered from the REQ.sub.-- MEM.sub.-- IN state when the external device 104 becomes temporarily disabled and cannot respond with an inactive signal (RERDY=HIGH). If the external device 104 recovers within one clock cycle, then the state will transition to CIO.sub.-- IN. If the recovery does not occur within one clock cycle, then the state will transition to DELAY2. During this state, the data is loaded into memory and the request for a memory location is deasserted (MEMRQ=HIGH).
DELAY2 is entered from DELAY1 as described above. Once in DELAY2, the state will not transition to CIO.sub.-- IN until the external device 104 goes inactive (RERDY=HIGH). DELAY2 is a hold condition.
This state is reached from the MEM.sub.-- IN state when the address generator has signaled that the correct number of words have been transferred. The only way to leave this state is by command of the microprocessor (upstart=0) and then the state transitions to IDLE.sub.-- H.
OUT.sub.-- GO
This state is entered from the IDLE.sub.-- L state when the microprocessor command word is set to three (upstart=3). This state always transitions to the REQ.sub.-- PIPE state on the following clock cycle unless interrupted by the microprocessor (upstart=0) and transitioned back to IDLE.sub.-- H. During this state, the sensor clock is set active (SCLK=HIGH).
REQ.sub.-- PIPE
This state is entered from the OUT.sub.-- GO state. During this state, the first memory location of the data transfer is requested (MEMRQ=LOW) and the sensor clock is set inactive (SCLK=LOW). Once it is granted (MEMGNT=HIGH), the state transitions to the FULL.sub.-- PIPE state.
FULL.sub.-- PIPE
This state is entered from the REQ.sub.-- PIPE state. During this state, the memory location request is set inactive (MEMRQ=HIGH) and the sensor clock is set active (SCLK=HIGH). The first word of the transfer is now ready to be sent to the external device 104. If the microprocessor does not interrupt the state machine 108, the next state is REQ.sub.-- MEM.sub.-- OUT.
REQ.sub.-- MEM.sub.-- OUT
This state is entered from the FULL.sub.-- PIPE state on the first word of the transfer and from MEM.sub.-- OUT thereafter. During this state, the next memory location of the data transfer is requested (MEMRQ=LOW) and the sensor clock is set inactive (SCLK=LOW). If the memory request is granted, (MEMGNT=HIGH), then the state transitions to MEM.sub.-- OUT.
MEM.sub.-- OUT
This state is entered from the REQ.sub.-- MEM.sub.-- OUT state. During this state, the data is read from memory and the request for a memory location is deasserted (MEMRQ=HIGH). The state machine 108 transitions to state REQ.sub.-- MEM.sub.-- OUT on the next clock cycle unless the address generator signals that the transfer is complete by setting the transfer complete interrupt (INTAG.sub.-- L=LOW). The state would then transition to the DONE state. If the transfer is not complete, the state transitions back to REQ.sub.-- MEM.sub.-- OUT. Under optimum conditions, the state machine 108 would now cycle between REQ.sub.-- MEM.sub.-- OUT and MEM.sub.-- OUT until the address generator interrupt occurs signaling the end of the transfer.
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DBA HUGHES ELECTRONICS;REEL/FRAME:016116/0506Effective date: 19971217Owner name: HE HOLDINGS, INC., A DELAWARE CORP. 7200 HUGHES TEFree format text: CHANGE OF NAME;ASSIGNOR:HUGHES AIRCRAFT COMPANY, A CORPORATION OF THE STATE OF DELAWARE /AR;REEL/FRAME:016087/05416 Jun 2002FPAYFee paymentYear of fee payment: 828 Jul 1998FPAYFee paymentYear of fee payment: 419 Abr 1993ASAssignmentOwner name: HUGHES AIRCRAFT COMPANYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:REAGLE, DENNIS J.;BOLSTAD, GREGORY D.;REEL/FRAME:006589/0083Effective date: 1993041519 Abr 1993AS02Assignment of assignor's interestOwner name: BOLSTAD, GREGORY D.Effective date: 19930415Owner name: HUGHES AIRCRAFT COMPANY 7200 HUGHES TERRACE LOS ANOwner name: REAGLE, DENNIS J.GirarImagen originalP�gina principal de Google - Sitemap - Descargas masivas de USPTO - Pol�tica de privacidad - Condiciones de servicio - Acerca de Google Patentes - Danos tu opini�nDatos proporcionados por IFI CLAIMS Patent Services©2012 Google