Source: https://patents.google.com/patent/GB2366012A/en
Timestamp: 2018-09-25 22:02:47
Document Index: 750088386

Matched Legal Cases: ['art 94', 'art 94', 'art 92', 'art 92', 'art 92', 'art 94']

GB2366012A - Fault Tolerant Computer System - Google Patents
GB2366012A
GB2366012A GB0019978A GB0019978A GB2366012A GB 2366012 A GB2366012 A GB 2366012A GB 0019978 A GB0019978 A GB 0019978A GB 0019978 A GB0019978 A GB 0019978A GB 2366012 A GB2366012 A GB 2366012A
GB0019978A
GB2366012B (en )
GB0019978D0 (en )
A computer system is arranged to provide protection against faults. The computer system comprises a plurality of processing sets, each having at least one processor (52) and a bridge coupled to each of the processing sets and operable to monitor a step locked operation of said processing sets. Each of the processors (52) has a processor identification register (64) which is read/writeable and is operable to store in the register data representative of a processor identification. The processors are arranged, consequent upon a masking condition, to load a predefined data value common to the processing sets jnto the processor identification register, which value has an effect of masking the processor identification. The erroneous detection by the bridge of a fault condition resulting from functionally the same processors having a different processor identification is thereby avoided, or at least the likelihood of a false detection reduced. The masking condition may be, for example, a boot or re-boot of a processing set, or a forced re-configuration or initialization of the processing system instigated by an operating system.
<Desc/Clms Page number 1> COMPUTER SYSTEM BACKGROUND OF THE INVENTION The invention relates to computer systems having first and second processing sets, each of which may comprise one or more processors, which communicate with an 1/0 device bus.
More particularly, the present invention relates to fault tolerant Computer systems in which the first and the second processing sets are arranged to communicate with the 1/0 device bus in a step locked manner, with provision for <RTI> identif,Vincy</RTI> lockstep errors in order to detect faulty operation of the computer <RTI> svstem.</RTI>
Generally it is desirable to provide fault tolerant computer systems with a facility for not only detecting faults, but also for automatically recovering from the detected faults. By detecting and recovering from the detect faults, tile computer system is provided with higher degree of system availability.
Automatic recovery from an error provides significant technical challenges. This is because a computer system has to be arranged to continue operating following fault detection to the effect of maintaining functional system performance of the system, whilst permitting, diagnostic operations to be performed to locate and remedy the fault.
The applicant has disclosed in a <RTI> co-pending</RTI> international patent application serial number <RTI> US99/124321,</RTI> corresponding to US patent application serial number 09/097,485, a fault tolerant computer system in which first and second <RTI> processincy</RTI> sets are connected via an 1/0 device bus to a bridge. The bridge operates to monitor the step locked operation of the processing sets, each processing set being arranged to operate in accordance with substantially identical software. The software includes for example an operating system of the computer system. If the bridge detects that one of the first or the second processing sets departs from the step locked operation with respect to the other processing set, then it is assumed that a fault or error condition has occurred. Interrogation and analysis is then performed by the operating system following error reports from the bridge. The operating system determines which of
the first or the second processing sets is in error, or whether another device was in <RTI> C></RTI> error, and takes corrective action. This fault detection and diagnosis is provided <RTI> fluough</RTI> the locked stepped operation of the processing sets as monitored by the <RTI> bridae.</RTI>
Although the step locked operation provides an effective <RTI> systern</RTI> for detecting faults. because the two processing sets are effectively <RTI> operatincy</RTI> <RTI> autonomouslv</RTI> some In conditions can occur in which the two processing, sets do not operate in lock step even though an error has not occurred.
SUMMARY OF THE <RTI> rNVENTION</RTI> Particular and preferred aspects of the invention are set out in the accompanying, independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.
In accordance with one aspect of the invention, there is provided a Computer system comprising a plurality of processing sets, each of the processing sets comprising at least one processor, and a bridge coupled to each of the processing sets and operable to monitor a step locked operation of the processing sets. wherein each of the processors has a processor identification register which is <RTI> read/writeable</RTI> and is operable to store in the register data representative of a processor identification, the processors being arranged, consequent upon a predetermined condition, to load a common predefined data value into the processor identification register.
Processors are typically provided with a processor identification which is for example a binary number loaded into a register, which may include manufacturer specific information, and/or other information relating to the status or configuration of the processor. The processor identification is provided to identify not only the processor, but also the version of the processor. The version number is provided because there may be no logical change in the structure and operation of the processor, however an update of the processor may occur to improve the manufacturing yield of the processor, or to increase the maximum speed of operation of the processor, although otherwise without a functional or logical change. The processor identification may therefore include, for example, data fields comprising the manufacturer's identification, an implementation identification, and a mask set version.
If the version number has changed between two processors which form part of different processing sets of a fault tolerant computer system the difference in the version numbers of the processors can cause errors to be wrongly detected as a result of the difference in processor numbers. For example, some processors include the processor identification as a field or fields of a word held in a register, which also
includes other configuration information, which is required by the operating system being executed by the processor. This configuration information may be, for example. the number of registers or the maximum number of supported trap levels beyond level 0 supported by the processor. As such. during execution, the information held <RTI> in</RTI> [lie v <RTI> i</RTI> identification <RTI> realster</RTI> will be read by the operating system, and stored In <RTI> ersion</RTI> 1 1 1 In memory. If this data is then read out of memory, sometime later, as a memory exchange as part of a virtual memory swap, then the version identification may be detected on the data bus by the bridge, and, therefore falsely diagnosed as a processing set error, because the version numbers of the processors in the processing sets differ.
Embodiments of the present invention address this technical problem by <RTI> provi</RTI> 1 , <RTI> the</RTI> <RTI> processor</RTI> <RTI> with</RTI> I a <RTI> processor</RTI> <RTI> register</RTI> - <RTI> which</RTI> I <RTI> is</RTI> <RTI> read/writeable,</RTI> and arranging, consequent upon a masking condition, for a predefined common data value, which is common to all processing sets, to be loaded into <RTI> the</RTI> version register.
The predetermined condition may be, for example, a boot or <RTI> re-boot</RTI> of a processing set. or a forced re -configuration or initialization of the <RTI> processina</RTI> set instigated by the operating system.
In a particular embodiment of the invention, each of the processing sets <RTI> ma,#</RTI> include a boot memory unit storing data which is representative of initialization code, which when read by the processor serves to initialize the processing set to operate within the computer system, the boot memory unit including the common predefined data value which is loaded by the processor into the processor identification register. In this embodiment, the boot memory may be a Boot PROM. or the like. The predefined value is loaded into the version register as part of instructions received from a Boot PROM, which are read and executed during a boot or <RTI> re-boot.</RTI> The boot or <RTI> re-boot</RTI> may be initiated following a "hot insertion" of a processing set, or following a forced <RTI> re-configuration</RTI> or initialization of the processing system by, for example the operating system.
According to an aspect of the invention there is provided a processor for use in a processing set forming, part of a fault tolerant computer system, the processor comprising an interface for communication with an 1/0 bus, and a process
identification register which is <RTI> read/writeable,</RTI> and has stored in the register data representative of a processor identification, wherein the processor is arranged, to write a common predefined data value received via the 1/0 bus into the processor identification register.
An aspect of the invention also provides a method of operating a fault tolerant computer system comprising a plurality of processing sets, each of which processing 0 sets is connected to a bridge, each of the processing sets having at least one processor, the method comprising the steps of, ID a) detecting a predetermined condition representative of a state in which the processor identification is present in a process identification register of the processor, and b) loading a common predefined data value into the processor identification register of each of the processors which predefined data value has an effect of masking the processor identification.
BRIEF DESCRIPTION OF THE DRAWINGS Exemplary embodiments of the present invention will be described hereinafter, by way of example only, with reference to the accompanying drawings in which like reference signs relate to like elements and in which: Figure I is a schematic overview of a fault tolerant computer system: Figure 2 is a schematic overview of a specific implementation of a system based on that of Figure 1; <RTI> Flaures</RTI> 3) and 4 are schematic <RTI> dia-rams</RTI> of examples of processing, sets.
Figure 5 is table providing an example illustration of data fields which may form part of a processor identification register; Figure 6 is an example block diagram of parts of a processor in accordance with an embodiment of the present invention; Figure 7 is an example block diagram of parts of a processor in accordance with a further embodiment of the present invention, and <RTI> Flaure</RTI> 8 is a flow <RTI> dia,,ram</RTI> illustrating a process for writing a common predefined value into the processor identification register of the processor shown in Figure 6.
DESCRIPTION OF THE PREFERRED EMBODIMENTS To facilitate understanding of the advantages provided by embodiments of the present invention, an example of a fault tolerant computer system will be presented ill the following paragraphs with reference to Figures I and 2. It will be appreciated however that the present invention finds application with any computer system which is arranged to operate with some duplication of processors.
Figure I is a schematic overview of a fault tolerant computing system 10 comprising a plurality of CPU sets (processing sets) 14, 16 and a bridge 12. As shown in Figure 1, there are two processing sets 14, 16, although in other embodiments there may be three or more processing sets. The bridge 12 forms an interface between the processing sets and 1/0 devices such as devices 28, 29, 30, 31, 32. In this document, the term "processing set" is used to denote a group of one or more processors, possibly including memory, which output and receive common outputs and inputs. It should be noted that the alternative term mentioned above, "CPU set", could be used instead. and that these <RTI> terrns</RTI> could be used interchangeably throughout this document. Also, it should be noted that the term <RTI> "brid(l)-e"</RTI> is used to denote any device, apparatus or arrangement suitable for <RTI> interconnectincy</RTI> two or more buses of the same or different types, The first processing set 14 is connected to the bridge 12 via a first processing set 1/0 bus (PA bus) 24, in the present instance a Peripheral Component Interconnect <RTI> (PCI)</RTI> bus. The second processing set 16 is connected to the bridge 12 via a second processing set 1/0 bus <RTI> (PB</RTI> bus) 26 of the same type as the PA bus 24 <RTI> (i.e.</RTI> here a <RTI> PCI</RTI> bus). The 1/0 devices are connected to the bridge 12 via a device 1/0 bus (D bus) 22, in the present instance also a <RTI> PCI</RTI> bus.
The processing sets 14, 16 and the bridge 12 are operable in synchronism under the control of a common clock 20, which is connected thereto by clock signal lines 2 1.
Some of the devices including an <RTI> Ethernet</RTI> <RTI> (E-NET)</RTI> interface 28 and a Small Computer System Interface <RTI> (SCSI)</RTI> interface 29 are permanently connected to the device bus 22, but other 1/0 devices such as 1/0 devices 30, 31, 32 can be hot <RTI> inser-table</RTI> into individual switched slots 33, 34 and 35. Dynamic field effect transistor
<RTI> (FET)</RTI> switching can be provided for the slots 3 <RTI> )3</RTI> <RTI> ),</RTI> 34 and 3 ) 5 to enable hot <RTI> insertability</RTI> of the devices such as devices 30, 31, 32. The provision of the <RTI> FETs</RTI> enables an increase in the length of the D bus 22 as only those devices which are active are switched on, reducing the effective total bus length. It will be appreciated that the number of 1/0 devices which may be connected to the D bus 22, and the number of slots provided for them, can be adjusted according to a particular implementation in accordance with specific design requirements.
Figure 2 is a schematic overview of a particular implementation of a fault <RTI> tolerant</RTI> <RTI> computer</RTI> <RTI> employing</RTI> a <RTI> bridge</RTI> I <RTI> structure</RTI> <RTI> of</RTI> <RTI> the</RTI> <RTI> type</RTI> <RTI> in</RTI> <RTI> Figure</RTI> <RTI> it#</RTI> <RTI> 1.</RTI> <RTI> In</RTI> <RTI> Fiaure</RTI> 2, the fault tolerant computer system includes a plurality (here four) of bridges 12 on first and second 1/0 motherboards (MB 40 and MB 42) in order to increase the number of 1/0 devices which may be connected and also to improve reliability and redundancy. Thus, in the embodiment shown in Figure 2, the two processing sets 14, 16 are each provided on a respective processing set board 44, 46, with the processing set boards 44, 46 <RTI> 'bridging'</RTI> the 1/0 motherboards MB 40 and MB 42. A first, master clock source 20A is mounted on the first motherboard 40, a second, slave clock source <RTI> 20B</RTI> is mounted on the second motherboard 42. Clock signals are supplied to the processing set boards 44, 46 via respective connections (not shown in Figure 2).
First and second bridges 12.1, 12.2 are mounted on the first <RTI> 1/10</RTI> motherboard 40. The first bridge 12.1 is connected to the processing sets 14, 16 by P buses 24.1, 26. 1, respectively. Similarly, the second bridge 12.2 is connected to the processing sets 14, 16 by P buses 24.2, 26.2, respectively. The bridge 12.1 is connected to an 1/0 <RTI> databus</RTI> (D bus) 22.1 and the bridge 12.2 is connected to an 1/0 <RTI> databus</RTI> (D bus) <RTI> -22-2.</RTI>
Third and fourth bridges 12.3, 12.4 are mounted on the second 1/0 motherboard 42. The bridge 123 is connected to the processing sets 14, 16 by P buses 24.3, 263, respectively. Similarly, the bridge 12.4 is connected to the processing sets 14, t6 by P buses 24.4, 26.4, respectively. The bridge 12.3 ) is connected to an 1/0 <RTI> databus</RTI> (D bus) 22.3 and the bridge 12.4 is connected to an 1/0 <RTI> databus</RTI> (D bus) 22.4.
It can be seen that the arrangement shown in Figure 2 can enable a large number of 1/0 devices to be connected to the two processing sets 14 and 16 via the D <RTI> Z:)</RTI>
buses 22.1, 22.2, 22.3 and 22.4 for either increasing the range of 1/0 devices available, or providing a higher degree of redundancy, or both.
Figure 3 is a schematic overview of one possible configuration of a processing set, such as the processing set 14 of Figure 1. The processing set 16 could <RTI> lia"-e</RTI> the same configuration, In Figure 3, a plurality of processors (here four) 52 are connected by one or more buses 54 to a processing, set bus controller 50. Also connected to the buses 54 is a boot programmable read only memory (Boot PROM) 55. The purpose and function of the Boot PROM 55 will be described shortly.
As shown in Figure <RTI> '),</RTI> one or more processing set output buses 24 are connected to the processing set bus controller 50, each processing Set Output <RTI> bus</RTI> 24 being connected to a respective bridge 12. For example, in the arrangement of Figure 1, only one processing set 1/0 bus (P bus) 24 would be provided, whereas in the arrangement of Figure 2, four such processing set 1/0 buses (P buses) 24 would be provided. In the processing set 14 shown in Figure 3, individual processors operate using the common memory 56, and receive inputs and provide outputs on the common P <RTI> bus(es)</RTI> 24.
Figure 4 illustrates an alternative configuration of a processing set, such as the processing set 14 of Figure 1. Here a simple <RTI> processin.-</RTI> set includes a single processor 72 and associated memory 76 connected via a common bus 74 to a processing set bus controller 70. The processing set shown in Figure 4 also includes a Boot PROM 73. The processing set bus controller 70 provides an interface between the internal bus 74 and the processing set 1/0 <RTI> bus(es)</RTI> (P <RTI> bus(es))</RTI> 24 for connection to CD the <RTI> bridge(s)</RTI> 12.
Accordingly, it will be appreciated from Figures 3 ) and 4 that the processing set may have many different forms and that the particular choice of a particular processing set structure can be made on the basis of the processing requirement of a particular application and the degree of redundancy required. In the following description, it is assumed that the processing sets 14, 16 referred to have a structure as shown in Figure 3, although it will be appreciated that another form of processing set could be provided.
The <RTI> bridge(s)</RTI> 12 are operable in a number of operating modes. These are described in detail in <RTI> co-pending</RTI> international patent application, serial number <RTI> US99/1243</RTI> <RTI> )2</RTI> 1. However to facilitate understanding and to illustrate the advantages of embodiments of the present invention a brief explanation of the operation of the bridge 12 is provided in the following paragraphs.
The bridge can be described as operating generally in one of two modes. In a first. combined mode, a bridge 12 is operable to route addresses and data between the processing sets 14 and 16 (via the PA and <RTI> PB</RTI> buses 24 and 26, respectively) and the devices (via the D bus 22). In this combined mode, 1/0 cycles generated by the processing sets 14, 16 are compared to ensure that both processing sets are operating correctly. Comparison failures force the bridge 12 into an error <RTI> limitina</RTI> mode C <RTI> (EState)</RTI> in which device 1/0 is prevented and diagnostic information is collected. In a second, split mode. the <RTI> bridcye</RTI> 12 routes and arbitrates addresses and data from one of the processing sets 14, 16 onto the D bus 22 and/or onto the other one of the processing sets 14. 16 respectively. In this mode of operation, the processing sets 14, 16 are not synchronized and no 1/0 comparisons are made. DMA operations are also permitted in both modes. Therefore, once an error condition has been detected by bridge 12 following a comparison failure, the bridge operates in the split mode to diagnose the error and to recover automatically from the error, by for example resetting the faulty processing set.
As already explained above, processors often contain a register in which version identification data of the processor is held. The version identification data may include one or more data fields, which contain <RTI> infonnation</RTI> inter <RTI> alia,</RTI> for identifying the processor revision. In the <RTI> followina</RTI> description this will be referred to as the version number, although as will be appreciated the version identification could by any <RTI> alpha-numeric</RTI> characters providing an identification of the processor version.
The presence of a different version identification number in a processor which forms part of a fault tolerant computing system described above provides a technical problem because processors within the fault tolerant computer system may have different version numbers although functionally and logically may operate substantially identically. An example of such a processor is the Sun Microelectronics
Ultra <RTI> Sparc</RTI> (Trademark) I and 2. As explained on page 241 of the Sun Ultra <RTI> Sparc</RTI> I and 2 Users Manual January 1997, the version register of the Ultra <RTI> Sparc</RTI> Processor includes two fields which <RTI> identifv</RTI> the processor and identify the <RTI> implernentation</RTI> of the processor as well as a mask set version. The fields of the version register are reproduced as an example of version identification data in the table shown in <RTI> FiOLire</RTI> 5. These fields will vary in accordance with a particular implementation of the processor. These fields form part of a 64 bit data word which include a field indicative of the maximum trap level supported <RTI> (MAXTL)</RTI> and a field indicative of the maximum number of windows of an integer register file <RTI> (MAXWEN).</RTI> As such, the version register will be interrogated by the operating system, and the contents may be stored in the memory units 56, 76 of the processing sets 14, 16. This is because the <RTI> MAXTL</RTI> and <RTI> MAXWTN</RTI> fields are required by the operating system in order to execute correctly. As a result there can exist in the memory units 56, 76 data values which will differ between the processing sets. As a result when the version identification data is loaded onto the 1/0 bus by the operating system, such as for example during a memory swap as part of a virtual memory access, a divergence will be caused between the data values which are put on to the <RTI> PA-bus</RTI> 24 and <RTI> PB-bus</RTI> 26. This may be detected by the bridge 12 as an error even though both processing sets 14, 16 of the computer system are operating correctly.
Embodiments of the present invention provide an arrangement in which the version register or at least the part of the version register which contains the processor identification is made to be <RTI> read/writeable,</RTI> and to write into the version register a predefined value which is common to all processors within the computer system. As a result the false detection of an error in the system is prevented or at least the likelihood of a false detection of an error reduced. An example of such a processor is shown in Figure 6.
In Figure 6 an example processor 52 is provided with an 1/0 port or ports 60 for connection to the <RTI> bus(es)</RTI> 54 of the processing sets shown in Figure <RTI> 3).</RTI> The bus 1/0 port 60 provides a means for communicating instructions, data and addresses to and from the processor 52. The <RTI> bus(es)</RTI> 54 therefore provide both data and address buses for the processor 52.
The processor 52 contains a read only register 62 and a <RTI> read/writeable</RTI> register 64. The <RTI> read/writeable</RTI> register 64 forms the version identification register. and is arranged to receive the contents of the read only register 62 under control of a control unit 66 via the internal bus 7 1. The control unit 66 is coupled to the read only register 62 and the version identification register 64 via control lines 68. In operation on <RTI> power-up,</RTI> the contents of the read only register 62 are written under control of the control unit 66 into a <RTI> writeable</RTI> part 94 of the version identification register 64. In this mode therefore the manufacturer's version identification data identifying the processor. the implementation identification and the mask set version, for example. are loaded into the corresponding field or fields of the version identification register 64. According to the example present in the table shown in Figure 5. the version identification register 64 may contain other configuration information such as <RTI> MAXTL</RTI> and <RTI> MAXWIN,</RTI> which may be loaded permanently in a read only section 92 of the register 64, as will be explained shortly.
On receipt of a command from the bus 54 as communicated to the control unit 66 via the 1/0 port 60, a common predefined <RTI> vaiue</RTI> received with the command is arranged to be latched into a <RTI> writeable</RTI> part 94 of the <RTI> readAvriteable</RTI> version register 64 via the internal bus 71. Alternatively, the common predefined value could not be communicated with the command but arranged to be an implicit value such as 0.
In this embodiment, the <RTI> read/writeable</RTI> version register 64 is divided into two parts, with the first part 92 containing information appertaining to the configuration of the processor 52. For example, as shown in the table of Figure 5, this information might include the maximum trap level supported and the maximum number of windows of integer register file <RTI> (MAXTL</RTI> and <RTI> MAXWfN).</RTI> As such these processor specific parameters may be held in a first part 92 of the version register 64. The first part 92 of the version register 64 is made to be a read only part and so is not overwritten by either the information from the read only register 62 or the common predefined value written into the second part 94 of version register 64 which is loaded from the bus 54 via the internal bus 71. In this way only the processor identification information is overwritten by the common predefined value or the true processor
<RTI> ication</RTI> value from the read only register 62. In Figure 6, which is represented <RTI> i</RTI> <RTI> 'dentif</RTI> schematically by an arrow 73.
Returning to Figure <RTI> 3),</RTI> the operation performed by the processor 52 to the effect of masking the processor identification number will now be explained in the context of the fault tolerant computer system.
Following system boot up or <RTI> re-boot,</RTI> the contents of the Boot PROM 55, which contains configuration and initialisation code are accessed by the processors 52 via the bus 54. The configuration and initialisation code contained in the Boot PROM 55 includes instructions to load a common predefined value which is received by the processor 52 via the bus 54. The instructions instructs the processor to load the common predefined value into the version register 64. In preferred embodiments, the common predefined value is supplied with the instructions from the Boot PROM 55. In this way the true processor identification which is initially loaded into the version register 64 from the read only register 62 is masked with the common predefined value. The common predefined value may be an all zeros value which can be easily identified and recognised as being a default processor identification and as such is recognised as not reflecting the true processor identification.
The steps and operation of the process through which the version identification number is replaced by the common predefined value is illustrated by the flow diagram shown in Figure 8. In Figure 8 following a <RTI> boot/re-boot</RTI> at step 80 the processor at step 82 operates to load the version register 64 with the processor identification held in the read only memory 62. At this point in the process the manufacturer's true processor identification data is present in the <RTI> read/writeable</RTI> version register 64 and so may be interrogated by a diagnostics system to determine the true version number of the processor. However at step 84, the processor is initialised with the configuration and initialisation code held in the Boot PROM 55.
The <RTI> re-boot</RTI> step 84 may be initiated for a number of reasons, referred to generally as a masking condition. It will be appreciated however that the following are just examples and other situations may occur in which the masking operation is effected. The term "masking condition" should therefore be interpreted as including any event or state for which the processor identification in the processor identification
register should be masked. For example if the fault tolerant computer system detects that a processing set is in error, the operating system running on the <RTI> processina</RTI> set 0 which is not in error <RTI> mav</RTI> initiate a <RTI> re-initialisation</RTI> and <RTI> re-boot</RTI> the <RTI> processin(-),</RTI> set at which point the code within the Boot PROM 53) is read by the processors. Alternatively, if it has been ascertained that a processing set is in error and is replaced. then after a "hot insertion" of a new processing set within a motherboard of the computer system, the new processing set is <RTI> re-booted</RTI> at which point again tile code within the Boot PROM 53 is read by the processors 52 in the processing set. A third alternative might be for example if the entire computer system is powered down at which point a <RTI> boot-up</RTI> follows and again the code within the Boot PROM <RTI> 53)</RTI> <RTI> Iis</RTI> read by the processors within each of the processing sets.
At processing step 86, the code within the Boot PROM is read by each of the processors within the processing set and an instruction to load the common predefined value received from the data bus 54 is executed by the processors 522 and the common predefined value is loaded into the version register 64. This is effected at processing step 88. At processing step 90 the process of masking the processor identification is completed.
As an alternative embodiment, the <RTI> read/writeable</RTI> version register 64 may not be divided into two parts, but the entire word length of the register may be <RTI> read/writeable.</RTI> For this embodiment the read only register 62 will contain the information appertaining to the configuration of the processor 52, as well as the manufacturer's processor identification. The same configuration information is therefore provided with the common predefined value and loaded from the buses 54.
As will be appreciated the example processing set shown in Figure 4 could also be implemented with the processor shown in Figure 6.
A further example of an implementation of a processor according to an alternative embodiment of the present invention is shown in Figure 7. The processor 52' shown in Figure 7 corresponds substantially to the processor shown in Figure 6 <RTI> Z:#</RTI> except that the processor in Figure 7 does not include a read only register 62. In this case, the version register 64 is again <RTI> read/writeable</RTI> however this register is loaded by I the manufacturer with the manufacturer's true processor identification fields.
Therefore, these processor identification fields remain with the other configuration fields within the version register 64 until and unless they are overwritten with the common predefined identification as described for the processor shown <RTI> in</RTI> Figure 6. Therefore for this embodiment of the invention the flow diagram <RTI> describin,,:,</RTI> the operation of the computer system which appears in <RTI> FiGUre</RTI> 7 is correspondingly executed with the exception that step 82 of the process is omitted. For this embodiment, the <RTI> read/writeable</RTI> version register 64 and the read only memory 62 are non-volatile <RTI> semi-conductor</RTI> memories such as flash or <RTI> EEPROM</RTI> <RTI> allowinu</RTI> the version registers to be permanently programmable.
According to a further embodiment of the invention, the common predefined value may be the processor identification of one of the processors of one of the processing sets in the computer system. In this way, all of the processors of the system may be arranged to be matched to the same processor identification. To this end, the operating system may interrogate the processor identification register of one of the processors to identify the processor identification. This processor identification is then used as the common predefined value, <RTI> whicn</RTI> is provided to the newly introduced processing set on <RTI> re-boot.</RTI> Alternatively, the operating system may <RTI> identift-</RTI> <RTI> the</RTI> processor identification of all of the processors and select one of these processor identifications as the common predefined value. The common predefined value may be redefined if the processor corresponding to the processor identification is contained in the processor set which has been replaced by a new processing set. In this case, the processor identification of one of the other processors is selected as the processing common predefined value.
As will be appreciated the embodiments of the invention herein before described are provided as illustrative examples and various modifications may be made without departing from the scope of the present invention. In particular, the processors embodying the present invention may be used in any computer system in which more than one of the processors are arranged to execute substantially identical software which is monitored by a bridge or the like.
CLAIMS A computer system comprising - a plurality of processing sets, each having at least one processor, and - a bridge coupled to each of said processing sets and operable to monitor a step locked operation of said processing sets, wherein - each of said processors has a processor identification register which is <RTI> read/writeable</RTI> and is operable to store in said register data representative of a processor identification, said processors being arranged. consequent upon a predetermined condition, to load a common predefined data value into said processor <RTI> i</RTI> <RTI> 'dent*f</RTI> 1 <RTI> ication</RTI> <RTI> register.</RTI> 0 A computer system as claimed in Claim 1, wherein said predetermined condition is a reset state of at least one of said plurality of processors. A computer system as claimed in Claim 2, wherein said reset state is a state I asserted in said fault tolerant computer system following boot or <RTI> re-boot.</RTI> 4. A computer system as claimed in any preceding Claim, wherein each of said processing sets includes a boot memory unit storing data which is representative of initialisation code arranged to initialise said processor to operate within said computer system, said boot memory unit including said common predefined data value which is loaded by said processor into said processor identification register. 5. A computer system as claimed in Claim 4, wherein said boot memory unit is a programmable read-only memory. 6. A computer system as claimed in any preceding Claim, wherein said common predefined value is an all zeros value.
7. A computer system as claimed in any preceding Claim, wherein each of said processors further includes - a read only register having stored therein said process identification data. ID 8. A computer system as claimed in Claim 7, wherein said process identification data stored in said read only register is loaded, upon initialisation into said processor identification register. 9. A computer system as claimed in any preceding Claim. wherein said common predefined value is a processor identification of one of the processors of said fault tolerant computer system, said processor identification of each of said processors being matched. 10. A processor for use in a processing set forming part of a fault tolerant computer system, said processor comprising - an interface for communication with an 1/0 bus, and - a <RTI> proces & -</RTI> identification register which is <RTI> read/writeable,</RTI> and has stored in said register data representative of a processor identification, wherein said processor is operable, to write a common predefined data value received via said 1/0 bus into said processor identification register. 11. A processor as claimed in Claim 10, comprising - a read only register having stored therein said process identification data, wherein said process identification data stored in said read only register is <RTI> loadable,</RTI> upon initialisation into said processor identification register. 12. A method of operating a fault tolerant computer system comprising a plurality of processing sets, each of which processing sets is connected to a bridge, each of said processing sets having at least one processor, said method comprising the steps of,
a) detecting a predetermined condition representative of a state in which s id processor identification is present in a process identification register of said al I I I I I I Z4 processor; and b) loading a common predefined data value into said processor identification register of each of said processors which predefined data value has an effect of masking said processor identification. I I A method of operating a fault tolerant computer system as claimed in Claim 12, wherein said predetermined condition is a reset state of at least one of said plurality of processing sets. 14. A method of operating a fault tolerant computer system as claimed in Claim I'), wherein said reset state is a state asserted in said fault tolerant computer system following boot or <RTI> re-boot.</RTI> 15, A method of operating a fault tolerant computer system as claimed in Claim <RTI> tn</RTI> 12, comprising detecting an error condition of at least one of said plurality of processing, sets, and if said error condition is detected performing the step of loading said common predefined value in said processor identification register of said at least one processor of the processing set which has said detected error. 16. A method of operating a fault tolerant computer system comprising a plurality of processing sets, each having at least one processor, and a bridge coupled to each of said processing sets and operable to monitor a step locked operation of said processing sets, said method comprising the step of - replacing a processor of one of said processing sets with a replacement processor according to Claim 10.
17. A method of operating a fault tolerant computer system as claimed in Claim 16, wherein said replacement processor is replaced by - replacing one of said processing sets with a processing set having the replacement processor according to Claim 10. 18. A computer system as herein before described with reference to the accompanying drawings. IM 19. A processor as herein before described with reference to the accompanying drawings. 20. A method of operating a fault tolerant computer system as herein before with 0 reference to the accompanying drawings.
GB0019978A 2000-08-14 2000-08-14 A computer system Active GB2366012B (en)
US09766246 US6862645B2 (en) 2000-08-14 2001-01-19 Computer system
GB0019978D0 GB0019978D0 (en) 2000-10-04
GB2366012A true true GB2366012A (en) 2002-02-27
GB2366012B GB2366012B (en) 2002-08-14
GB0019978A Active GB2366012B (en) 2000-08-14 2000-08-14 A computer system
US20040225792A1 (en) 2004-11-11 application