Source: http://www.google.com/patents/US7109516?dq=5572193
Timestamp: 2015-05-05 16:07:22
Document Index: 115649893

Matched Legal Cases: ['Application No. 01', 'Application No. 01', 'Application No. 01', 'Application No. 02', 'Application No. 02', 'Application No. 98', 'Application No. 98']

Patent US7109516 - Strained-semiconductor-on-insulator finFET device structures - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....http://www.google.com/patents/US7109516?utm_source=gb-gplus-sharePatent US7109516 - Strained-semiconductor-on-insulator finFET device structuresAdvanced Patent SearchPublication numberUS7109516 B2Publication typeGrantApplication numberUS 11/211,933Publication dateSep 19, 2006Filing dateAug 25, 2005Priority dateJun 7, 2002Fee statusPaidAlso published asUS7074623, US20040031979, US20050280103, US20060186510, US20060197123, US20060197124, US20060197125, US20060197126Publication number11211933, 211933, US 7109516 B2, US 7109516B2, US-B2-7109516, US7109516 B2, US7109516B2InventorsThomas A. Langdo, Matthew T. Currie, Glyn Braithwaite, Richard Hammond, Anthony J. Lochtefeld, Eugene A. FitzgeraldOriginal AssigneeAmberwave Systems CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (102), Non-Patent Citations (99), Referenced by (14), Classifications (67), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetStrained-semiconductor-on-insulator finFET device structures
1. Improved speed performance of highly integrated functionality of CMOS technology; 2. Lower power dissipation than bipolar technology; 3. Lower sensitivity to fan out and capacitive load; 4. Increased flexibility of input/output interface; 5. Reduced clock skew; 6. Improved internal gate delay; and 7. Reduced need for aggressive scaling because a 1�2 μm BiCMOS process offers circuit speed equivalent to that of sub-micron CMOS. SUMMARY
FIGS. 1A�6 are schematic cross-sectional views of substrates illustrating a method for fabricating an SSOI substrate;
An SSOI structure may be formed by wafer bonding followed by cleaving. FIGS. 1A�2B illustrate formation of a suitable strained layer on a wafer for bonding, as further described below.
Referring to FIG. 1A, an epitaxial wafer 8 has a plurality of layers 10 disposed over a substrate 12. Substrate 12 may be formed of a semiconductor, such as Si, Ge, or SiGe. The plurality of layers 10 includes a graded buffer layer 14, which may be formed of Si1−yGey, with a maximum Ge content of, e.g., 10�80% (i.e., y=0.1�0.8) and a thickness T1 of, for example, 1�8 micrometers (μm).
A relaxed layer 16 is disposed over graded buffer layer 14. Relaxed layer 16 may be formed of uniform Si1−xGex having a Ge content of, for example, 10�80% (i.e., x=0.1�0.8), and a thickness T2 of, for example, 0.2�2 μm. In some embodiments, Si1−xGex may include Si0.70Ge0.30 and T2 may be approximately 1.5 μm. Relaxed layer 16 may be fully relaxed, as determined by triple axis X-ray diffraction, and may have a threading dislocation density of <1�106 dislocations/cm2, as determined by etch pit density (EPD) analysis. Because threading dislocations are linear defects disposed within a volume of crystalline material, threading dislocation density may be measured as either the number of dislocations intersecting a unit area within a unit volume or the line length of dislocation per unit volume. Threading dislocation density, therefore, may be expressed in either units of dislocations/cm2 or cm/cm3. Relaxed layer 16 may have a surface particle density of, e.g., less than about 0.3 particles/cm2. Further, relaxed layer 16 produced in accordance with the present invention may have a localized light-scattering defect level of less than about 0.3 defects/cm2 for particle defects having a size (diameter) greater than 0.13 microns, a defect level of about 0.2 defects/cm2 for particle defects having a size greater than 0.16 microns, a defect level of about 0.1 defects/cm2 for particle defects having a size greater than 0.2 microns, and a defect level of about 0.03 defects/cm2 for defects having a size greater than 1 micron. Process optimization may enable reduction of the localized light-scattering defect levels to about 0.09 defects/cm2 for particle defects having a size greater than 0.09 microns and to 0.05 defects/cm2 for particle defects having a size greater than 0.12 microns.
A strained semiconductor layer 18 is disposed over relaxed layer 16. Strained layer 18 may include a semiconductor such as at least one of a group II, a group III, a group IV, a group V, and a group VI element. Strained semiconductor layer 18 may include, for example, Si, Ge, SiGe, GaAs, indium phosphide (InP), and/or zinc selenide (ZnSe). In some embodiments, strained semiconductor layer 18 may include approximately 100% Ge, and may be compressively strained. Strained semiconductor layer 18 comprising 100% Ge may be formed over, e.g., relaxed layer 16 containing uniform Si1−xGex having a Ge content of, for example, 50�80% (i.e., x=0.5�0.8), preferably 70% (x=0.7). Strained layer 18 has a thickness T3 of, for example, 50�1000 Å. In an embodiment, T3 may be approximately 200�500 Å.
Handle wafer 50 and epitaxial wafer 8 are cleaned by a wet chemical cleaning procedure to facilitate bonding, such as by a hydrophilic surface preparation process to assist the bonding of a semiconductor material, e.g., strained layer 18, to a dielectric material, e.g., dielectric layer 52. For example, a suitable prebonding surface preparation cleaning procedure could include a modified megasonic RCA SC 1 clean containing ammonium hydroxide, hydrogen peroxide, and water (NH4OH:H2O2:H2O) at a ratio of 1:4:20 at 60� C. for 10 minutes, followed by a deionized (DI) water rinse and spin dry. The wafer bonding energy should be strong enough to sustain the subsequent layer transfer (see FIG. 4). In some embodiments, top surfaces 60, 62 of handle wafer 50 and epitaxial wafer 8, including a top surface 63 of strained semiconductor layer 18, may be subjected to a plasma activation, either before, after, or instead of a wet clean, to increase the bond strength. The plasma environment may include at least one of the following species: oxygen, ammonia, argon, nitrogen, diborane, and phosphine. After an appropriate cleaning step, handle wafer 50 and epitaxial wafer 8 are bonded together by bringing top surfaces 60, 62 in contact with each other at room temperature. The bond strength may be greater than 1000 mJ/m2, achieved at a low temperature, such as less than 600� C.
Referring to FIG. 4 as well as to FIG. 3, a split is induced at cleave plane 20 by annealing handle wafer 50 and epitaxial wafer 8 after they are bonded together. This split may be induced by an anneal at 300�700� C., e.g., 550� C., inducing hydrogen exfoliation layer transfer (i.e., along cleave plane 20) and resulting in the formation of two separate wafers 70, 72. One of these wafers (70) has a first portion 80 of relaxed layer 16 (see FIG. 1A) disposed over strained layer 18. Strained layer 18 is in contact with dielectric layer 52 on semiconductor substrate 54. The other of these wafers (72) includes substrate 12, graded layer 14, and a remaining portion 82 of relaxed layer 16. In some embodiments, wafer splitting may be induced by mechanical force in addition to or instead of annealing. If necessary, wafer 70 with strained layer 18 may be annealed further at 600�900� C., e.g., at a temperature greater than 800� C., to strengthen the bond between the strained layer 18 and dielectric layer 52. In some embodiments, this anneal is limited to an upper temperature of about 900� C. to avoid the destruction of a strained Si/relaxed SiGe heterojunction by diffusion. Wafer 72 may be planarized, and used as starting substrate 8 for growth of another strained layer 18. In this manner, wafer 72 may be �recycled� and the process illustrated in FIGS. 1A�5 may be repeated. An alternative �recyling� method may include providing relaxed layer 16 that is several microns thick and repeating the process illustrated in FIGS. 1A�5, starting with the formation of strained layer 18. Because the formation of this thick relaxed layer 16 may lead to bowing of substrate 12, a layer including, e.g., oxide or nitride, may be formed on the backside of substrate 12 to counteract the bowing. Alternatively substrate 12 may be pre-bowed when cut and polished, in anticipation of the bow being removed by the formation of thick relaxed layer 16.
Referring to FIG. 6, a SSOI substrate 100 has strained layer 18 disposed over an insulator, such as dielectric layer 52 formed on semiconductor substrate 54. Strained layer 18 has a thickness T4 selected from a range of, for example, 50�1000 Å, with a thickness uniformity of better than approximately �5% and a surface roughness of less than approximately 20 Å. Dielectric layer 52 has a thickness T52 selected from a range of, for example, 500�3000 Å. In an embodiment, strained layer 18 includes approximately 100% Si or 100% Ge having one or more of the following material characteristics: misfit dislocation density of, e.g., 0�105 cm/cm2; a threading dislocation density of about 101�107 dislocations/cm2; a surface roughness of approximately 0.01�1 nm RMS; and a thickness uniformity across SSOI substrate 100 of better than approximately �10% of a mean desired thickness; and a thickness T4 of less than approximately 200 Å. In an embodiment, SSOI substrate 100 has a thickness uniformity of better than approximately �5% of a mean desired thickness.
In alternative embodiments, an SSOI structure may include, instead of a single strained layer, a plurality of semiconductor layers disposed on an insulator layer. For example, referring to FIG. 9, epitaxial wafer 300 includes strained layer 18, relaxed layer 16, graded layer 14, and substrate 12. In addition, a semiconductor layer 310 is disposed over strained layer 18. Strained layer 18 may be tensilely strained and semiconductor layer 310 may be compressively strained. In an alternative embodiment, strained layer 18 may be compressively strained and semiconductor layer 310 may be tensilely strained. Strain may be induced by lattice mismatch with respect to an adjacent layer, as described above, or mechanically. For example, strain may be induced by the deposition of overlayers, such as Si3N4. In another embodiment, semiconductor layer 310 is relaxed. Semiconductor layer 310 includes a semiconductor material, such as at least one of a group II, a group III, a group IV, a group V, and a group VI element. Epitaxial wafer 300 is processed in a manner analogous to the processing of epitaxial wafer 8, as described with reference to FIGS. 1�7.
Referring again to FIG. 7, in some embodiments, a small amount, e.g., approximately 20�100 Å, of strained layer 18 may be removed at an interface 105 between strained layer 18 and relaxed layer portion 80. This may be achieved by overetching after relaxed layer portion 80 is removed. Alternatively, this removal of strained layer 18 may be performed by a standard microelectronics clean step such as an RCA SCI, i.e., hydrogen peroxide, ammonium hydroxide, and water (H2O2+NH4OH+H2O), which at, e.g., 80� C. may remove silicon. This silicon removal may remove any misfit dislocations that formed at the original strained layer 18/relaxed layer 80 interface 105 if strained layer 18 was grown above the critical thickness. The critical thickness may be defined as the thickness of strained layer 18 beyond which it becomes energetically favorable for the strain in the layer to partially relax via the introduction of misfit dislocations at interface 105 between strained layer 18 and relaxed layer 16. Thus, the method illustrated in FIGS. 1�7 provides a technique for obtaining strained layers above a critical thickness without misfit dislocations that may compromise the performance of deeply scaled MOSFET devices.
Referring to FIG. 12, in some embodiments, handle wafer 50 may have a structure other than a dielectric layer 52 disposed over a semiconductor substrate 54. For example, a bulk relaxed substrate 400 may comprise a bulk material 410 such as a semiconductor material, e.g., bulk silicon. Alternatively, bulk material 410 may be a bulk dielectric material, such as Al2O3 (e.g., alumina or sapphire) or SiO2 (e.g., quartz). Epitaxial wafer 8 may then be bonded to handle wafer 400 (as described above with reference to FIGS. 1�6), with strained layer 18 being bonded to the bulk material 410 comprising handle wafer 400. In embodiments in which bulk material 410 is a semiconductor, to facilitate this semiconductor-semiconductor bond, a hydrophobic clean may be performed, such as an HF dip after an RCA SC1 clean.
Referring to FIG. 13, after bonding and further processing (as described above), a strained-semiconductor-on-semiconductor (SSOS) substrate 420 is formed, having strained layer 18 disposed in contact with relaxed substrate 400. The strain of strained layer 18 is not induced by underlying relaxed substrate 400, and is independent of any lattice mismatch between strained layer 18 and relaxed substrate 400. In an embodiment, strained layer 18 and relaxed substrate 400 include the same semiconductor material, e.g., silicon. Relaxed substrate 400 may have a lattice constant equal to a lattice constant of strained layer 18 in the absence of strain. Strained layer 18 may have a strain greater than approximately 1�10−3. Strained layer 18 may have been formed by epitaxy, and may have a thickness T5 of between approximately 20 Å�1000 Å, with a thickness uniformity of better than approximately �10%. In an embodiment, strained layer 18 may have a thickness uniformity of better than approximately �5%. Surface 92 of strained layer 18 may have a surface roughness of less than 20 Å.
Referring to FIGS. 21A and 21B, a self-aligned silicide (�salicide�) is formed over SSOI substrate 100 to provide low resistance contacts as follows. A conductive layer is formed over SSOI substrate 100. For example, a metal such as cobalt or nickel is deposited by, e.g., CVD or sputtering, with the conductive layer having a thickness of, e.g., 50�200 Å. An anneal is performed to react the conductive layer with the underlying semiconductor, e.g., exposed portions of gate 622 and gate contact area 624, to form salicide 650 including, e.g., cobalt silicide or nickel silicide. Anneal parameters may be, for example, 400�800� C. for 10�120 seconds. Unreacted portions of the conductive layer disposed directly over insulator material, such as exposed portions of dielectric layer 52 and sidewall spacers 642, are removed by a chemical strip. A suitable chemical strip may be a solution including H2SO4:H2O2 at a ratio of 3:1. A second anneal may be performed to further lower resistivity of salicide 650. The second anneal parameters may be, for example, 600�900� C. for 10�120 seconds A finFET 655 includes fins 600, gate insulator 610, source 630, drain 632, and gate 622. A finFET 655 having three fins 600 is illustrated in FIG. 21B. The three fins 600 share a common source 630 and a common drain 632. A single transistor may have multiple fins to increase current drive in comparison to a transistor with a single fin.
Referring to FIG. 22 as well as to FIG. 1A, epitaxial wafer 8 has layers 10 disposed over substrate 12. Substrate 12 may be formed of a semiconductor, such as Si, Ge, or SiGe. The plurality of layers 10 includes graded buffer layer 14, formed of Si1−yGey, with a maximum Ge content of, e.g., 10�80% (i.e., y=0.1�0.8). Relaxed layer 16 is disposed over graded buffer layer 14. Relaxed layer 16 may be formed of uniform Si1−xGex having a Ge content of, for example, 10�80% (i.e., x=0.1�0.8). Strained semiconductor layer 18 is disposed over relaxed layer 16. Strained layer 18 comprises at least one of a group II, a group III, a group IV, a group V, and a group VI element. Strained layer 18 may include, for example, Si and may be tensilely strained.
Referring to FIGS. 33�35, contact holes 770 are formed through thick insulator layer 760 to conductive sidewall spacers 742 and second gate electrode 730. Contact holes 770 may be defined by the use of photolithography and RIE. Contact holes 770 are filled with a conductive material such as, e.g., a metal such as titanium or tungsten. The conductive material is patterned by photolithography and etch to define contacts 780 to source 732, drain 734, first gate electrode 750 at a first gate electrode 793, and second gate electrode 730 at a second gate electrode 795. Double gate transistor 790 includes first gate electrode 750, second gate electrode 730, first gate insulator layer 700, second gate insulator layer 722, source 732, and drain 734.
Referring to FIG. 38, a base 1010 is formed over region 920 of collector 810. Base 1010 may be formed selectively by, e.g., selective deposition of a semiconductor material only over region 920 defined by mask 910. The selective deposition can be done by CVD methods, such as by APCVD, LPCVD, UHVCVD, or by MBE. In an embodiment, base 1010 may be deposited non-selectively. The non-selectively grown material will thus also form on a top surface 1012 of mask 910, and may be removed by further photolithography and etch steps. Base 1010 has a thickness T22 of, e.g., of 50�1000 Å. In an embodiment, T22 may be, for example 300�500 Å. Base 1010 includes a semiconductor material like Si or SiGe. In some embodiments, base 1010 is relaxed or compressively strained. The in-plane lattice constant of collector 810 (strained layer 18) was defined by relaxed layer 16 (see FIG. 1A). Therefore, in order that base 1010 be relaxed, the Ge content of base 1010 should be equal to the Ge content of relaxed layer 16 (see FIG. 1A). Similarly, in order that base 1010 be compressively strained, the Ge content of base 1010 should be greater than the Ge content of relaxed layer 16. This difference in Ge content also provides a base 1010 with a bandgap no larger than that of collector 810; which can be advantageous to device operation. In other embodiments, base 1010 is tensilely strained. In order that base 1010 be tensilely strained, the Ge content of base 1010 should be less than the Ge content of relaxed layer 16 (see FIG. 1A). Alternatively, base 1010 may be formed from the same material as collector 810, for example strained Si. Base 1010 is doped the opposite doping type as the collector, i.e., base 1010 is p-type doped for an n-type doped collector. Base 1010 may be doped during the deposition process, but may also be doped after deposition by ion implantation. Base 1010 may be doped to a level of 1�1018�1�1019 atoms/cm3.
Referring to FIG. 41B, in an alternative embodiment, after the formation of porous layer 1616 in a portion of relaxed layer 16, a second relaxed layer 1620 may be formed over relaxed layer 16 including porous layer 1616. Second relaxed layer 1620 may include the same material from which relaxed layer 16 is formed, e.g., uniform Si1−xGex having a Ge content of, for example, 10�80% (i.e., x=0.1�0.8) and having a thickness T17 of, e.g., 5�100 nm. In some embodiments, Si1−xGex may include Si0.70Ge0.30 and T17 may be approximately 50 nm. Second relaxed layer 1620 may be fully relaxed, as determined by triple axis X-ray diffraction, and may have a threading dislocation density of <1�106/cm2, as determined by etch pit density (EPD) analysis. Strained layer 18 may be formed over second relaxed layer 1620. Pores 1614 define cleave plane 20 in porous layer 1616.
Raman spectroscopy data enabled a comparison of the bonded and cleaved structure before and after SiGe layer 16 removal. Based on the peak positions the composition of the relaxed SiGe layer and strain in the Si layer may be calculated. See, for example, J. C. Tsang, et al., J. Appl. Phys. 75 (12) p. 8098 (1994), incorporated herein by reference. The fabricated SSOI structure 100 had a clear strained Si peak visible at �511/cm. Thus, the SSOI structure 100 maintained greater than 1% tensile strain in the absence of the relaxed SiGe layer 16. In addition, the absence of Ge�Ge, Si�Ge, and Si�Si relaxed SiGe Raman peaks in the SSOI structure confirmed the complete removal of SiGe layer 16.
In addition, the thermal stability of the strained Si layer was evaluated after a 3 minute 1000� C. rapid thermal anneal (RTA) to simulate an aggregate thermal budget of a CMOS process. A Raman spectroscopy comparision was made of SSOI structure 100 as processed and after the RTA step. A scan of the as-bonded and cleaved sample prior to SiGe layer removal was used for comparision. Throughout the SSOI structure 100 fabrication process and subsequent anneal, the strained Si peak was visible and the peak position did not shift. Thus, the strain in SSOI structure 100 was stable and was not diminished by thermal processing. Furthermore, bubbles or flaking of the strained Si surface 18 were not observed by Nomarski optical microscopy after the RTA, indicating good mechanical stability of the SSOI structure 100.
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