Source: http://www.google.ca/patents/US7904695
Timestamp: 2013-05-25 14:05:14
Document Index: 131010416

Matched Legal Cases: ['Application No. 200580008575', 'Application No. 200780000013', 'Application No. 200780000014', 'Application No. 200780000015', 'Application No. 05723250', 'Application No. 05723250', 'Application No. 07250614', 'Application No. 07250614', 'Application No. 07250614', 'Application No. 07250645', 'Application No. 07250645', 'Application No. 07250645', 'Application No. 07250646', 'Application No. 07250646', 'Application No. 07250646', 'Application No. 07250647', 'Application No. 07250647', 'Application No. 07250647', 'Application No. 07250648', 'Application No. 07250648', 'Application No. 07250648', 'Application No. 07250649', 'Application No. 07250649', 'Application No. 07250649', 'Application No. 07250649', 'Application No. 08251499', 'Application No. 08251499', 'Application No. 08251505', 'Application No. 08251505', 'Application No. 2007']

Patent US7904695 - Asynchronous power saving computer - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Web History | Sign inAdvanced Patent SearchPatentsA computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other...http://www.google.ca/patents/US7904695?utm_source=gb-gplus-sharePatent US7904695 - Asynchronous power saving computerPublication numberUS7904695 B2Publication typeGrantApplication number11/355,513Publication date8 Mar 2011Filing date16 Feb 2006Priority date16 Feb 2006Also published asCN101366003ACN101454755ACN101479714ACN101563679AUS20070192646InventorsCharles H. MooreOriginal AssigneeVns Portfolio LlcTechnology Properties Limited LlcTechnology Properties LimitedU.S. Classification712/16710/5712/11712/26710/31International ClassificationG06F13/14Cooperative ClassificationY02B60/1239G06F1/3209G06F1/3243European ClassificationG06F 1/32P1AG06F 1/32P5MReferencesPatent Citations (117)Non-Patent Citations (103)Referenced by (1)External LinksUSPTOUSPTO AssignmentEspacenetAsynchronous power saving computerUS 7904695 B2Abstract A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A slot sequencer (42) in each of the computers produces a timing pulse to cause the computer (12) to execute a next instruction. However, when the present instruction is a read or write type instruction, the slot sequencer does not produce the pulse until an acknowledge signal (86) starts it. The acknowledge signal (86) is produced when it is recognized that the communication has been completed by the other computer (12).
the bit is set when it is a �1�.
The present invention relates to the field of computers and computer processors, and more particularly to a method and means for allowing a computer to �go to sleep� while it is waiting to communicate with another computer or device, thereby saving power and reducing heat production. The predominant current usage of the present inventive asynchronous computer is in the combination of multiple computers on a single microchip, wherein computing power, power consumption, and heat production are important considerations.
Of course, efforts are being made to make the sharing of tasks among computer processors more efficient. The question of exactly how the tasks are to be allocated is being examined and processes improved. However, no one expects that there will not be at least some �wasted� processor power in such an arrangement, no matter how clever might be the implementation.
SUMMARY Accordingly, it is an object of the present invention to provide an apparatus and method for increasing computer processing speed while reducing power consumption.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagrammatic view of a computer array, according to one embodiment of the present invention;
A known mode for carrying out the invention is an array of individual computers. The array is depicted in a diagrammatic view in FIG. 1 and is designated therein by the general reference character 10. The computer array 10 has a plurality (twenty-four in the example shown) of computers 12 (sometimes also referred to as �cores� or �nodes� in the example of an array). In the example shown, all of the computers 12 are located on a single die 14. According to the present invention, each of the computers 12 is a generally independently functioning computer, as will be discussed in more detail hereinafter. The computers 12 are interconnected by a plurality (the quantities of which will be discussed in more detail hereinafter) of interconnecting data buses 16. In this example, the data buses 16 are bidirectional asynchronous high speed parallel data buses, although it is within the scope of the invention that other interconnecting means might be employed for the purpose. In the present embodiment of the array 10, not only is data communication between the computers 12 asynchronous, the individual computers 12 also operate in an internally asynchronous mode. This has been found by the inventor to provide important advantages. For example, since a clock signal does not have to be distributed throughout the computer array 10, a great deal of power is saved. Furthermore, not having to distribute a clock signal eliminates many timing problems that could limit the size of the array 10 or cause other known difficulties.
There may be several potential means and/or methods to cause the computers 12 to function as described above. However, in this present example, the computers 12 so behave simply because they are operating generally asynchronously internally (in addition to transferring data there-between in the asynchronous manner described). That is, instructions are completed sequentially. When either a write or read instruction occurs, there can be no further action until that instruction is completed (or, perhaps alternatively, until it is aborted, as by a �reset� or the like). There is no regular clock pulse, in the prior art sense. Rather, a pulse is generated to accomplish a next instruction only when the instruction being executed either is not a read or write type instruction (given that a read or write type instruction would require completion by another entity) or else when the read or write type operation is, in fact, completed.
FIG. 3 is a block diagram depicting the general layout of an example of one of the computers 12 of FIGS. 1 and 2. As can be seen in the view of FIG. 3, each of the computers 12 is a generally self contained computer having its own RAM 24 and ROM 26. As mentioned previously, the computers 12 are also sometimes referred to as individual �cores�, given that they are, in the present example, combined on a single chip.
Other basic components of the computer 12 are a return stack 28, an instruction area 30, an arithmetic logic unit (�ALU� or �processor�) 32, a data stack 34 and a decode logic section 36 for decoding instructions. One skilled in the art will be generally familiar with the operation of stack based computers such as the computers 12 of this present example. The computers 12 are dual stack computers having the data stack 34 and separate return stack 28.
Although the invention is not limited by this example, the present computer 12 is implemented to execute native Forth language instructions. As one familiar with the Forth computer language will appreciate, complicated Forth instructions, known as Forth �words� are constructed from the native processor instructions designed into the computer. The collection of Forth words is known as a �dictionary�. In other languages, this might be known as a �library�. As will be described in greater detail hereinafter, the computer 12 reads eighteen bits at a time from RAM 24, ROM 26 or directly from one of the data buses 16 (FIG. 2). However, since in Forth most instructions (known as operand-less instructions) obtain their operands directly from the stacks 28 and 34, they are generally only five bits in length such that up to four instructions can be included in a single eighteen-bit instruction word, with the condition that the last instruction in the group is selected from a limited set of instructions that require only three bits. Also depicted in block diagrammatic form in the view of FIG. 3 is a slot sequencer 42. In this embodiment of the invention, the top two registers in the data stack 34 are a T register 44 and an S register 46.
As discussed, above, the i4 bit 66 of each instruction 52 is set according to whether or not that instruction is a read or write type of instruction. The remaining bits 50 in the instruction 52 provide the remainder of the particular opcode for that instruction. In the case of a read or write type instruction, one or more of the bits may be used to indicate where data is to be read from or written to in that particular computer 12. In the present example of the invention, data to be written always comes from the T register 44 (the top of the data stack 34), however data can be selectively read into either the T register 44 or else the instruction area 30 from where it can be executed. That is because, in this particular embodiment of the invention, either data or instructions can be communicated in the manner described herein and instructions can, therefore, be executed directly from the data bus 16, although this is not a necessary aspect of this present invention. Furthermore, one or more of the bits 50 will be used to indicate which of the ports 38, if any, is to be set to read or write. This later operation is optionally accomplished by using one or more bits to designate a register 40, such as the A register 40 a, the B register, or the like. In such an example, the designated register 40 will be preloaded with data having a bit corresponding to each of the ports 38 (and, also, any other potential entity with which the computer 12 may be attempting to communicate, such as memory, an external communications port, or the like.) For example, each of four bits in the particular register 40 can correspond to each of the up port 38 a, the right port 38 b, the left port 38 c or the down port 38 d. In such case, where there is a �1� at any of those bit locations, communication will be set to proceed through the corresponding port 38. As previously discussed herein, in the present embodiment of the invention it is anticipated that a read opcode might set more than one port 38 for communication in a single instruction while, although it is possible, it is not anticipated that a write opcode will set more than one port 38 for communication in a single instruction.
The immediately following example will assume a communication wherein computer 12 e is attempting to write to computer 12 c, although the example is applicable to communication between any adjacent computers 12. When a write instruction is executed in a writing computer 12 e, the selected write line 20 (in this example, the write line 20 between computers 12 e and 12 c) is set high. If the corresponding read line 18 is already high, then data is immediately sent from the selected location through the selected communications port 38. Alternatively, if the corresponding read line 18 is not already high, then computer 12 e will simply stop operation until the corresponding read line 18 does go high. The mechanism for stopping (or, more accurately, not enabling further operations of) the computer 12 a when there is a read or write type instruction has been discussed previously herein. In short, the opcode of the instruction 52 will have a �0� at bit position i4 66, and so the first OR gate input 62 of the OR gate 60 is low, and so the slot sequencer 42 is not triggered to generate an enabling pulse.
In any case when the instruction 52 being executed is in the slot three position of the instruction word 48, the computer 12 will fetch the next awaiting eighteen-bit instruction word 48 unless, of course, bit i4 66 is a �0�. In actual practice, the present inventive mechanism includes a method and apparatus for �prefetching� instructions such that the fetch can begin before the end of the execution of all instructions 52 in the instruction word 48. However, this also is not a necessary aspect of the present inventive method and apparatus for asynchronous data communications.
The above example wherein computer 12 e is writing to computer 12 c has been described in detail. As can be appreciated in light of the above discussion, the operations are essentially the same whether computer 12 e attempts to write to computer 12 c first, or whether computer 12 c first attempts to read from computer 12 e. The operation cannot be completed until both computers 12 and 12 c are ready and, whichever computer 12 e or 12 c is ready first, that first computer 12 simply �goes to sleep� until the other computer 12 e or 12 c completes the transfer. Another way of looking at the above described process is that, actually, both the writing computer 12 e and the receiving computer 12 c go to sleep when they execute the write and read instructions, respectively, but the last one to enter into the transaction reawakens nearly instantaneously when both the read line 18 and the write line 20 are high, whereas the first computer 12 to initiate the transaction can stay asleep nearly indefinitely until the second computer 12 is ready to complete the process.
The inventor believes that a key feature for enabling efficient asynchronous communications between devices is some sort of acknowledge signal or condition. In the prior art, most communication between devices has been clocked and there is no direct way for a sending device to know that the receiving device has properly received the data. Methods such as checksum operations may have been used to attempt to insure that data is correctly received, but the sending device has no direct indication that the operation is completed. The present inventive method, as described herein, provides the necessary acknowledge condition that allows, or at least makes practical, asynchronous communications between the devices. Furthermore, the acknowledge condition also makes it possible for one or more of the devices to �go to sleep� until the acknowledge condition occurs. Of course, an acknowledge condition could be communicated between the computers 12 by a separate signal being sent between the computers 12 (either over the interconnecting data bus 16 or over a separate signal line), and such an acknowledge signal would be within the scope of this aspect of the present invention. However, according to the embodiment of the invention described herein, it can be appreciated that there is even more economy involved here, in that the method for acknowledgement does not require any additional signal, clock cycle, timing pulse, or any such resource beyond that described, to actually affect the communication.
In light of the above discussion of the procedures and means for accomplishing them, the following brief description of an example of the inventive method can now be understood. FIG. 6 is a flow diagram, designated by the reference character 74, depicting this method example. In an �initiate communication� operation 76 one computer 12 executes an instruction 53 that causes it to attempt to communicate with another computer 12. This can be either an attempt to write or an attempt to read. In a �set first line high� operation 78, which occurs generally simultaneously with the �initiate communication� operation 76, either a read line 18 or a write line 20 is set high (depending upon whether the first computer 12 is attempting to read or to write). As a part of the �set first line high� operation, the computer 12 doing so will, according the presently described embodiment of the operation, cease operation, as described in detail previously herein. In a �set second line high� operation 80 the second line (either the write line 20 or read line 18) is set high by the second computer 12. In a �communicate data operation� data (or instructions, or the like) is transmitted and received over the data lines 22. In a �pull lines low� operation 84, the read line 18 and the write line 20 are released and then pulled low. In a �continue� operation 86 the acknowledge condition causes the computers 12 to resume their operation. In the case of the present inventive example, the acknowledge condition causes an acknowledge signal 86 (FIG. 5) which, in this case, is simply the �high� condition of the acknowledge line 72.
Similarly, while the present invention has been described herein in relation to communications between computers 12 in an array 10 on a single die 14, the same principles and method can be used, or modified for use, to accomplish other inter-device communications, such as communications between a computer 12 and its dedicated memory or between a computer 12 in an array 10 and an external device (through an input/output port, or the like). Indeed, it is anticipated that some applications may require arrays of arrays�with the presently described inter device communication method being potentially applied to communication among the arrays of arrays.
INDUSTRIAL APPLICABILITY The inventive computer array 10, computers 12 and associated method 74 are intended to be widely used in a great variety of computer applications. It is expected that it they will be particularly useful in applications where significant computing power is required, and yet power consumption and heat production are important considerations.
As discussed previously herein, the applicability of the present invention is such that many types of inter-device computer communications can be improved thereby. It is anticipated that the inventive method, wherein some computers can be allowed to �go to sleep� when not in use, will be used to reduce power consumption, reduce heat production, and improve the efficiency of communication between computers and computerized devices in a great variety of applications and implementations.
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