Source: http://www.google.com/patents/US7822061?dq=U.S.+Patent+No.+4,528,643
Timestamp: 2016-08-30 03:29:38
Document Index: 538395363

Matched Legal Cases: ['Application No. 05798761', 'Application No. 05798761', 'Application No. 200580032948', 'Application No. 200580032948', 'Application No. 200580032948', 'Application No. 200580032888', 'Application No. 200580032947', 'Application No. 200580032947']

Patent US7822061 - Method and system for power control of fibre channel switches - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method and system for controlling power consumption in a fiber channel switch element having a plurality of ports and plural links to communicate over a network is provided. The switch element includes, a power control module that is used to provide power to only active ports after firmware of fiber...http://www.google.com/patents/US7822061?utm_source=gb-gplus-sharePatent US7822061 - Method and system for power control of fibre channel switchesAdvanced Patent SearchPublication numberUS7822061 B2Publication typeGrantApplication numberUS 12/267,188Publication dateOct 26, 2010Priority dateJul 21, 2003Fee statusPaidAlso published asUS7477655, US20050018663, US20090123150Publication number12267188, 267188, US 7822061 B2, US 7822061B2, US-B2-7822061, US7822061 B2, US7822061B2InventorsFrank R. Dropps, Charles M. CompOriginal AssigneeQlogic, CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (84), Non-Patent Citations (69), Classifications (17), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for power control of fibre channel switches
US 7822061 B2Abstract
A method and system for controlling power consumption in a fiber channel switch element having a plurality of ports and plural links to communicate over a network is provided. The switch element includes, a power control module that is used to provide power to only active ports after firmware of fiber channel switch element determines the active ports. The method includes, determining active ports of the fiber channel switch element, after all the ports are shut down in a known state; and providing power to only the active ports. All ports are powered up during fiber channel switch element reset and then powered down (except a common port) so that the ports are shut down in a known state.
1. A method for controlling power consumption in a switch element having a plurality of ports for transmitting and receiving network information, comprising:
(a) powering up the plurality of ports for a duration during the switch element initialization so that if the plurality of ports are shut down, they are shut down in a known state;
(b) shutting down all the ports in the known state, except a control port of the switch element;
(c) determining active ports of the switch element, after all the ports are shut down in the known state; and
(d) providing power to only the active ports to receive and transmit network information.
2. The method of claim 1, wherein the plurality of ports are powered up during a reset operation.
3. The method of claim 1, wherein firmware for the switch element determines the active ports.
4. The method of claim 3, wherein the firmware writes to a control register in a power control module to selectively turn on power to the active ports.
5. The method of claim 1, wherein a counter counts the duration for which the plurality of ports are powered up and when the counter reaches a certain value, clock signals to the plurality of ports are turned off to shut down all the ports, except the control port.
6. A switch element, comprising:
a plurality of ports for receiving and sending network information over a network; and
a power control module for controlling power consumption by the plurality of ports; wherein the power control module includes:
(a) a counter that starts a count when the plurality of ports are all powered up for a duration during a reset operation, causing the plurality of ports to be in a known state;
(b) logic for turning off power to the plurality of ports except a control port, after the counter reaches a maximum value; wherein the plurality of ports are shut down in a known state; and
(c) a control register which is written by firmware of the switch element to provide power only to active ports, after the plurality of ports are shut down.
8. The switch element of claim 6, wherein the clock signal is turned off after the counter reaches the maximum value and then turned on when the firmware writes to the control register.
a switch element coupled to at least another network device; wherein the switch elements includes:
(a) a counter that starts a count when the plurality of ports are powered up for a duration during a reset operation, which causes the plurality of ports to be in a known state;
10. The system of claim 9, wherein a clock generator generates a clock signal for powering up the plurality of ports during the reset operation.
11. The system of claim 10, wherein the clock signal is turned off after the counter reaches the maximum value and then turned on when the firmware writes to the control register.
This application is a continuation of a application Ser. No. 10/894,689 filed Jul. 20, 2004, now U.S. Pat. No. 7,477,655, which claims priority under 35 U.S.C. �119(e) (1) to the following provisional patent applications:
Fibre channel switches can have varying number of ports (for example, 8, 16 and/or 20 ports). However, all the ports may not be used at a given time depending upon fabric topology or network needs. Power consumption for these switches can also vary depending upon the number of ports.
In one aspect of the present invention, a method for controlling power consumption in a fibre channel switch element having a plurality of ports and plural links to communicate over a network is provided. The method includes, determining active ports of the fibre channel switch element, after all the ports are shut down in a known state; and providing power to only the active ports. All ports are powered up during fibre channel switch element reset and then powered down (except a common port) so that the ports are shut down in a known state.
In one aspect of the present inventions worst-case power requirements are reduced. Also, different size systems can be designed with the same switch element and optimize cooling and power requirements for reduced space and cost.
FIGS. 1E-1E-2 (jointly referred to as FIG. 1E) show another block diagram of a Fibre Channel switch element with sixteen GL_Ports and four 10G ports, according to one aspect of the present invention;
FIG. 3A/3B (jointly referred to as FIG. 3) show a block diagram of a GL_Port, according to one aspect of the present invention; and
FIG. 4A/4B (jointly referred to as FIG. 3) show a block diagram of XG_Port (10G) port, according to one aspect of the present invention.
“ASIC”: Application Specific Integrated Circuit
“Fibre channel ANSI Standard”: The standard (incorporated herein by reference in its entirety) describes the physical interface, transmission and signaling protocol of a high performance serial link for support of other high level protocols associated with IPI, SCSI, IF, ATM and others.
FIG. 1B is a block diagram of a 20-port ASIC fabric element according to one aspect of the present invention. FIG. 1B provides the general architecture of a 20-channel switch chassis using the 23-port fabric element. Fabric element includes ASIC 20 with non-blocking fibre channel class 2 (connectionless, acknowledged) and class 3 (connectionless, unacknowledged) service between any ports. It is noteworthy that ASIC 20 may also be designed for class 1 (connection-oriented) service, within the scope and operation of the present invention as described herein.
ASIC 20 has 20 ports numbered in FIG. 1B as GL0 through GL19. These ports are generic to common Fibre Channel port types, for example, F_Port, FL_Port and E_Port. In other words, depending upon what it is attached to, each GL port can function as any type of port. Also, the GL port may function as a special port useful in fabric element linking, as described below.
In the preferred embodiments of switch chassis described herein, the fabric controller is a firmware-programmed microprocessor, also referred to as the input/out processor (“IOP”) TOP 66 is shown in FIG. 1C as a part of a switch chassis utilizing one or more of ASIC 20. As seen in FIG. 1B, bi-directional connection to IOP 66 is routed through port 67, which connects internally to a control bus 60. Transmit buffer 56, receive buffer 58, control register 62 and Status register 64 connect to bus 60. Transmit buffer 56 and receive buffer 58 connect the internal connectionless switch crossbar 50 to IOP 66 so that it can source or sink frames.
FIG. 1C shows a 20-channel switch chassis S2 using ASIC 20 and IOP 66 S2 will also include other elements, for example, a power supply (not shown). The 20 GL ports correspond to channel C0-C19. Each GL port has a serial/deserlalizer (SERDES) designated as S0-S19. Ideally, the SERDES functions are implemented on ASIC 20 for efficiency, but may alternatively be external to each GL port.
Each GL port has an optical-electric converter, designated as OE0-OE19 connected with its SERDES through serial lines, for providing fibre optic input/output connections, as is well known in the high performance switch design. The converters connect to switch channels C0-C09. It is noteworthy that the ports can connect through copper paths or other means instead of optical-electric converters.
FIG. 1E-1/1E-2 (jointly referred to as FIG. 1E) show yet another block diagram of ASIC 20 with sixteen GL and four XG port control modules. Each GL port control module has a Receive port (RPORT) 69 with a receive buffer (RBUF) 69A and a transmit port 70 with a transmit buffer (TBUF) 70A, as described below in detail. CL and XG port control modules are coupled to physical media devices (“PMD”) 76 and 75 respectively.
XG_Port (for example 74B) includes RPORT 72 with RBUF 71 similar to SPORT 69 and RBUF 69A and a TBUF and TPORT similar to TBUF 70A and TPORT 70. Protocol module 73 interfaces with SERDES to handle protocol based functionality.
FIGS. 3A-3B (referred to as FIG. 3 show a detailed block diagram of a CL port as used in ASIC 20. GL port 300 is shown in three segments, namely, receive segment (RPORT) 310, transmit segment (TPORT) 312 and common segment 311.
Frames enter through link 301 and SERDES 302 converts data into 10-bit parallel data to fibre channel characters, which are then sent to receive pipe (“Rpipe” may also be referenced as Rpipe 1 or Rpipe 2) 303A via a de-multiplexer (DEMUX) 303. Rpipe 303A includes, parity module 305 and decoder 304. Decoder 304 decodes 10 B data to 8 B and parity module 305 adds a parity bit. Rpipe 303A also performs various Fibre Channel standard functions such as detecting a start of frame (SOF), end-of frame (EOF), Idles, R_RDYs (fibre channel standard primitive) and the like, which are not described since they are standard functions.
Reading from and writing to RBUF 69A are controlled by RBUF read control logic (“RRD”) 319 and RBUF write control logic (“RWT”, 307, respectively. RWT 307 specifies which empty RBUF 69A slot will be written into when a frame arrives through the data link via multiplexer (“Mux”) 313B, CRC generate module 313A and in EF (external proprietary format) module 314. EF module 314 encodes proprietary (i.e. non-standard) format frames to standard Fibre Channel 8B codes. Mux 313B receives input from Rx Spoof module 314A, which encodes frames to a proprietary format (if enabled). RWT 307 controls RBUF 69A write addresses and provides the slot number to tag writer (“TWT”) 317.
RTAG 318 also has frame content information that is passed to a requesting destination to precondition the destination for the frame transfer. These tags are transferred to the destination via a read multiplexer (RMUX) (not shown).
Transmit segment (“TPORT”) 312 performs various transmit functions. Transmit tag register (TTAG) 33Q provides a list of all frames that are to be transmitted. Tag Writer 317 or common segment 311 write TTAG 330 information. The frames are provided to arbitration module (“transmit arbiter” (“TARB”)) 331, which is then free to choose which source to process and which frame from that source to be processed next.
TARB 331 is activated anytime there are one or more valid frame tags in TTAG 330. TAR; 331 preconditions its controls for a frame and then waits for the frame to be written into TBUF 70A. After the transfer is complete, TARB 331 may request another frame from the same source or choose to service another source.
TMUX (may also be referred to as Tx Mux) 339 chooses which data path to connect to the transmitter. The sources are: primitive sequences specified by IOP 66 via control registers 326 (shown as primitive 339A), and signals as specified by Transmit state machine (“TSM”) 346, frames following the loop path, or steered frames exiting the fabric via TBUF 70A.
IOP buffer (“IBUF”) 345 provides TOP 66 the means for transmitting frames for special purposes.
A loop look up table (“LLUT” 322 and an address look up table (“ALUT”) 323 is used for private loop proxy addressing and hard zoning managed by firmware.
RPORT 310A uses a virtual lane (“VL”) cache 402 that stores plural vector values that are used for virtual lane assignment. In one aspect of the present invention, VL Cache 402 may have 32 entries and two vectors per entry. IOP 66 is able to read or write VL cache 402 entries during frame traffic State machine 401 controls credit that is received. On the transmit side, credit state machine 347 controls frame transmission based on credit availability. State machine 347 interfaces with credit counters 328A.
FIG. 2A shows a detailed schematic of power control module 326A that includes log 100 for controlling power consumption of every link port, according to one aspect of the present invention. The schematic allows ASIC 20 to minimize its power consumption for systems that do not need all the ports (for example, all 20 ports). It is noteworthy that the logic used in 326A, as shown In FIG. 2A, is not intended to limit the invention, but rather to illustrate the adaptive aspect of the present invention.
When the reset signal 108 is deactivated, logic 102 enables clock gates 106 (one clock gate for each port) using signal 105B so that ports 107 can have their resets active and are turned on for a short duration. This initial “turn on” of all the ports 107, resets ports 107 to a known state.
At this instance, counter 101 starts counting to its' maximum count. In one aspect, counter 101 is a 5 bit counter. It is noteworthy that the invention is not limited to any particular counter. Thereafter, signal 101A (the “done” signal) is activated and counter 101 stops counting. Done signal 101A removes the enable signal 102A for all ports 107 (via logic 104). This turns off all the clock signals to ports 107.
FIG. 2B shows a flow diagram of executable process steps, according to one aspect of the present invention for minimizing the maximum power consumption
In step S201, all the ports are powered up. This is done so that when the ports are shut down in a known state.
In step S204, only the active ports are powered up. This is achieved by using control register 103 as discussed above.
15 WATTS 16
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No. 10/956,501".69"Project-T11/1619-D/Rev. 0,50", Information technology Industry Council, Fibre Channel: Framing and Signaling-2, Dec. 2004, Rev. 0.50, (Dec. 2004),76, 81, 114, 115.Classifications U.S. Classification370/463International ClassificationH04L12/66, H04L12/10, H04L12/56Cooperative ClassificationH04L47/10, H04L49/3009, H04L12/10, H04L49/101, H04L49/254, H04L47/28, H04L47/32, H04L49/357European ClassificationH04L47/32, H04L47/28, H04L47/10, H04L49/35H2, H04L12/10Legal EventsDateCodeEventDescriptionAug 25, 2010ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DROPPS, FRANK R.;COMP, CHARLES M.;REEL/FRAME:024887/0578Effective date: 20040714Owner name: QLOGIC, CORPORATION, CALIFORNIAFeb 15, 2011CCCertificate of correctionMar 26, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services