Source: http://www.google.fr/patents/US6996009?hl=fr
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Brevet US6996009 - NOR flash memory cell with high storage density - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Historique Web | Connexion Recherche avanc�e dans les brevets BrevetsStructures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region...http://www.google.fr/patents/US6996009?utm_source=gb-gplus-shareBrevet US6996009 - NOR flash memory cell with high storage density Num�ro de publicationUS6996009 B2Type de publicationOctroi Num�ro de demande10/177,483 Date de publication7 f�vr. 2006 Date de d�p�t21 juin 2002 Date de priorit�21 juin 2002Autre r�f�rence de publicationUS7113429US7348237US7476586US20030235079US20050082599US20050085040US20070015331 InventeursLeonard Forbes Cessionnaire d'origineMicron Technology, Inc. Classification aux �tats-Unis365/185.17257/E27.103365/185.28257/E29.306257/E21.682365/185.33257/E21.693 Classification internationaleG11C16/04H01L27/115H01L21/8247H01L29/788 Classification coop�rativeH01L27/11521H01L29/7885H01L29/66825H01L27/115G11C2216/28H01L27/11556H01L29/7886G11C16/0416 Classification europ�enneH01L27/115F10C2H01L29/788B6CH01L29/66M6T6F17G11C16/04F1H01L29/788B6BH01L27/115H01L27/115F4R�f�rencesCitations de brevets (103)Citations hors brevets (79) R�f�renc� par (9)Liens externesUSPTO Cession USPTO EspacenetNOR flash memory cell with high storage densityUS 6996009 B2 R�sum� Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.
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