Source: http://www.google.com/patents/US6962863?ie=ISO-8859-1&dq=U.S.+Patent+No.+4,528,643
Timestamp: 2014-08-31 10:50:02
Document Index: 281414879

Matched Legal Cases: ['art 1', 'art 2', 'art 3', 'art 1', 'art 2', 'art 3', 'art 1', 'art 2', 'art 3']

Patent US6962863 - Semiconductor device having interconnection layer with multiply layered ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsThe semiconductor device comprises an interconnection layer 14 formed on a substrate 10, a cap insulation film 22 formed on the upper surface of the interconnection layer 14, and a sidewall insulation film which is formed on the side walls of the interconnection layer 14 and the cap insulation film 22...http://www.google.com/patents/US6962863?utm_source=gb-gplus-sharePatent US6962863 - Semiconductor device having interconnection layer with multiply layered sidewall insulation filmAdvanced Patent SearchPublication numberUS6962863 B2Publication typeGrantApplication numberUS 10/704,684Publication dateNov 8, 2005Filing dateNov 12, 2003Priority dateMar 30, 2001Fee statusPaidAlso published asUS6703715, US20020140100, US20040104485Publication number10704684, 704684, US 6962863 B2, US 6962863B2, US-B2-6962863, US6962863 B2, US6962863B2InventorsYuji YokoyamaOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (14), Referenced by (1), Classifications (21), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device having interconnection layer with multiply layered sidewall insulation filmUS 6962863 B2Abstract The semiconductor device comprises an interconnection layer 14 formed on a substrate 10, a cap insulation film 22 formed on the upper surface of the interconnection layer 14, and a sidewall insulation film which is formed on the side walls of the interconnection layer 14 and the cap insulation film 22 and which includes a larger layer number of insulation films 24, 26 28 covering the side wall of the interconnection layer 14 at the side wall of the cap insulation film 22 than a layer number of insulation films 24, 26 at the side wall of the cap insulation film 22. Accordingly, the sidewall insulation film can be thickened at the side wall of the interconnection layer 14, whereby a parasitic capacitance between the interconnection layer 14 and the electrodes 32 adjacent to the interconnection layer 14 through the sidewall insulation film can be low.
anisotropically etching the second insulation film and the first insulation film to leave the first insulation film selectively on side walls of the interconnection layer and the cap insulation film and leave the second insulation film selectively on a lower region of a side wall of the first insulation film;
forming a third insulation film on an upper region of the side wall of the first insulation film and a side wall of the second insulation film;
forming a fourth insulation film on the substrate with the interconnection layer and the first, second and third sidewall insulation films, the fourth insulation film contacting to the third sidewall insulation film; and
forming above a substrate an interconnection layer having a side surface;
forming a first sidewall insulation film to cover the side surface of the interconnection layer;
forming a second sidewall insulation film whose etching rate is different from that of the first sidewall insulation film and covering the side surface of the interconnection layer through the first sidewall insulation film;
forming a third sidewall insulation film whose etching rate is the same as that of the first sidewall insulation film and covering the side surface of the interconnection layer through the first and second sidewall insulation films;
anisotropically etching the fourth insulation film with the third sidewall insulation film as a stopper to form a contact hole down to the substrate in the fourth insulation film.
RELATED APPLICATION This application is a divisional of U.S. patent application Ser. No. 09/934,595 filed on Aug. 23, 2001, now U.S. Pat. No. 6,703,715, which is hereby incorporated by reference in its entirety. Priority under 35 U.S.C. ��120 and 121 is hereby claimed for benefit of the filing date of U.S. patent application Ser. No. 09/934,595.
BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically to a semiconductor device including sidewall insulation films for interconnection layers, which are suitable to open micronized contact holes between the interconnection layers.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device whose parasitic capacitance between interconnection layers is small and which includes a sidewall insulation film between the interconnection layers, which is easy for contact holes to be formed, and a method for fabricating the semiconductor device.
In the specification, a �substrate� means a semiconductor substrate itself, such as a silicon substrate or others, and also a semiconductor substrate with transistors, interconnection layers, insulation films or others, formed on.
FIGS. 2A�2C are sectional views of the semiconductor device according to the first embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which explain the method (Part 1).
FIGS. 3A�3C are sectional views of the semiconductor device according to the first embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which explain the method (Part 2).
FIGS. 4A�4C are sectional views of the semiconductor device according to the first embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which explain the method (Part 3).
FIGS. 7A�7C are sectional views of the semiconductor device according to the second embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 1).
FIGS. 8A�8C are sectional views of the semiconductor device according to the second embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 2).
FIGS. 9A�9C are sectional views of the semiconductor device according to the second embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 3).
FIGS. 12A�12C are sectional views of the conventional DRAM in the steps of a method for fabricating the DRAM up to forming a bit contact (Part 1).
FIGS. 13A�13C are sectional views of the conventional DRAM in the steps of a method for fabricating the DRAM up to forming a bit contact (Part 2).
FIGS. 14A�14C are sectional views of the conventional DRAM in the steps of a method for fabricating the DRAM up to forming a bit contact (Part 3).
The semiconductor device according to a first embodiment of the present invention and the method for fabricating the semiconductor device will be explained with reference t FIGS. 1, 2A�2C, 3A�3C, and 4A�4C. FIG. 1 is a diagrammatic sectional view of the semiconductor device according to the present embodiment, which show a configuration thereof. FIGS. 2A�2C, 3A�3C, and 4A�4C are sectional views of the semiconductor device in the steps of the method for fabricating the semiconductor device, which show the method.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 2A�2C, 3A�3C, and 4A�4C. FIGS. 2A�2C, 3A�3C, and 4A�4C are sectional views along a bit line of the DRAM.
The semiconductor device according to a second embodiment of the present invention and a method for fabricating the semiconductor device will be explained with reference to FIGS. 6, 7A�7C, 8A�8C, and 9A�9C. The same members of the present embodiment as those of the semiconductor device according to the first embodiment are represented by the same reference numbers not to repeat or to simplify their explanation.
Thus, in the present embodiment as well, the sidewall insulation film can be made thickened selectively near the gate electrode. The lower spacer insulation film 44 is formed of silicon oxide film, whose dielectric constant is lower than that of silicon nitride film, whereby a parasitic capacitance can be further low. An etching gas can be easily admitted inbetween the gate electrodes 14, which facilitates the etching for forming a contact hole 42. The upper surface of the plug can have a large area, which allows for a margin for the connection to upper interconnections, such as a bit line 36, etc.
Then, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 7A�7C, 8A�8C, and 9A�9C. The views of FIGS. 7A�7C, 8A�8C, and 9A�9C are sectional views of a DRAM along the bit line in the steps of the method for fabricating the DRAM.
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comprising MIS field-effect transistor, and method of fabricating the same* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7169677 *May 14, 2003Jan 30, 2007Infineon Technologies AgMethod for producing a spacer structure* Cited by examinerClassifications U.S. Classification438/595, 438/675, 257/E23.134, 438/618, 438/597, 257/E21.507International ClassificationH01L23/522, H01L27/108, H01L21/28, H01L21/8242, H01L21/768, H01L23/31, H01L21/60Cooperative ClassificationH01L2924/0002, H01L23/3192, H01L2924/19041, H01L21/76897, H01L29/6656European ClassificationH01L21/768S, H01L29/66M6T6F10, H01L23/31P12Legal EventsDateCodeEventDescriptionMar 7, 2013FPAYFee paymentYear of fee payment: 8Jul 9, 2010ASAssignmentOwner name: FUJITSU SEMICONDUCTOR LIMITED,JAPANFree format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:24651/744Effective date: 20100401Free format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS 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