Source: https://patents.google.com/patent/US20120142194A1/en
Timestamp: 2019-12-15 09:00:44
Document Index: 696192052

Matched Legal Cases: ['arts 121', 'art 121', 'arts 121', 'art 121', 'art 121', 'art 121', 'art 121']

US20120142194A1 - Method of forming semiconductor memory device - Google Patents
Method of forming semiconductor memory device Download PDF
US20120142194A1
US20120142194A1 US13/310,943 US201113310943A US2012142194A1 US 20120142194 A1 US20120142194 A1 US 20120142194A1 US 201113310943 A US201113310943 A US 201113310943A US 2012142194 A1 US2012142194 A1 US 2012142194A1
US13/310,943
US8518831B2 (en
Young Sun Hwang
2010-12-06 Priority to KR1020100123623A priority Critical patent/KR20120062385A/en
2010-12-06 Priority to KR10-2010-0123623 priority
2011-12-05 Application filed by SK Hynix Inc filed Critical SK Hynix Inc
2011-12-05 Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HWANG, YOUNG SUN
2012-06-07 Publication of US20120142194A1 publication Critical patent/US20120142194A1/en
2013-08-27 Publication of US8518831B2 publication Critical patent/US8518831B2/en
2032-04-01 Adjusted expiration legal-status Critical
238000009740 moulding (composite fabrication) Methods 0 abstract claims description title 47
239000004065 semiconductor Substances 0 abstract claims description title 44
239000010410 layers Substances 0 abstract claims description 250
230000000903 blocking Effects 0 abstract claims description 10
238000005192 partition Methods 0 claims description 216
239000000463 materials Substances 0 claims description 79
238000005530 etching Methods 0 claims description 16
229920002120 photoresistant polymers Polymers 0 description 121
238000000034 methods Methods 0 description 52
238000000206 photolithography Methods 0 description 10
238000000059 patterning Methods 0 description 5
238000005137 deposition process Methods 0 description 2
239000005368 silicate glasses Substances 0 description 2
A method of forming semiconductor memory device includes forming first to fourth spacers over a target layer including a first region and second regions adjacent to the first region so that a first spacer group including the first spacers spaced at a first interval is formed in the first region of the target layer, a second spacer group including the second spacers spaced at second intervals is formed in the second regions, a third spacer is formed between the first and the second spacer groups, and fourth spacers are formed between the third spacer and the first spacer group; forming an overlap pattern blocking the target layer; and forming first patterns, spaced at the first interval and each formed to have a first width, in the first region and second patterns, spaced at the second intervals and each formed to have a second width, in the second regions.
Priority is claimed to Korean patent application number 10-2010-0123623 filed on Dec. 6, 2010, the entire disclosure of which is incorporated herein by reference in its entirety.
Exemplary embodiments relate generally to a method of forming a semiconductor memory device and, more particularly, to a method of forming a semiconductor memory device, which forms patterns of different line widths at the same time.
Patterns forming a semiconductor device are formed using a photolithography process. The photolithography process includes a process of forming a photoresist layer on a target layer and a process of forming photoresist patterns by exposing and developing the photoresist layer. The exposed regions of the target layer are removed by using an etch process employing the photoresist patterns as an etch mask. The target layer is a material layer for the patterns of the semiconductor device or a hard mask layer formed on the material layer for the patterns of the semiconductor device.
If the target layer is the hard mask layer, a process of removing the exposed regions of the material layer for the patterns of the semiconductor device by using an etch process employing hard mask patterns, formed by etching the hard mask layer, as an etch mask is further performed.
When the patterns of the semiconductor device are formed by performing a series of the processes, an interval between the patterns and the width of each pattern are determined by an interval between the photoresist patterns and the width of each photoresist pattern. However, the exposure resolution limit may cause a limitation of the interval between the photoresist patterns and the width of each photoresist pattern. In order to overcome the exposure resolution limit, spacer patterning technology using spacers as an etch mask is being developed.
A process of forming the spacers includes a process of forming partition patterns on the target layer, a process of forming a spacer layer on a surface of the partition patterns, a process of etching a portion of the spacer layer to expose the partition patterns, and a process of removing the exposed partition patterns. In this case, since the width of each of the spacers formed by a series of the processes is determined by a deposition thickness of the spacer layer, the exposure resolution limit can be overcome and the photoresist patterns can be finely formed.
If the patterns of the semiconductor device are formed using the spacer patterning technology, the patterns can be formed finer than the exposure resolution limit because the width of each of the patterns is identical with the width of the spacer.
However, each of patterns formed in a specific region of the semiconductor device has a greater width than the spacer. For example, in case of the gate lines of a NAND flash memory device, the gate lines include word lines formed in a memory cell region and select lines formed in a select transistor region. In general, the word lines are formed to have finer line widths than the exposure resolution limit in order to improve the degree of high integration of semiconductor devices, and the select lines are formed to have wider widths than the word lines.
If the patterns of a semiconductor device are formed by using the spacers as an etch mask, however, the patterns of the semiconductor device have the same line width. Accordingly, there is a need for a method of forming patterns of different line widths (e.g., the word lines and the select lines) at the same time.
Exemplary embodiments relate to a method of forming semiconductor memory device which can form patterns of different line widths at the same time.
A method of forming semiconductor memory device according to an aspect of the present disclosure includes forming first to fourth spacers over a target layer including a first region and second regions adjacent to the first region so that a first spacer group including first spacers spaced apart from each other at a first interval is formed in the first region of the target layer, a second spacer group including second spacers spaced apart from one another at second intervals is formed in the second regions, a third spacer is formed between the first and the second spacer groups, and an odd number of fourth spacers are formed between the third spacer and the first spacer group; forming an overlap pattern blocking the target layer exposed between the third spacer and the first spacer group; and forming first patterns, spaced apart from each other at the first interval and each formed to have a first width, in the first region and second patterns, spaced apart from one another at the second intervals and each formed to have a second width, in the second regions by etching the target layer exposed between the first to fourth spacers and the overlap pattern.
FIG. 1 is a diagram illustrating the layout of the patterns of a semiconductor memory device according to an embodiment of the present invention;
FIGS. 2A to 2H are cross-sectional views illustrating a method of forming the patterns of a semiconductor memory device using spacer patterning technology;
FIGS. 3A to 3C are diagrams illustrating line patterns having relatively wide patterns when the method of forming the patterns of the semiconductor memory device shown in FIGS. 2A to 2H is used;
FIGS. 4A to 4H are cross-sectional views illustrating a method of forming the patterns of a semiconductor memory device according to an embodiment of present invention; and
FIGS. 5A to 5C are cross-sectional views illustrating a method of forming the patterns of a semiconductor memory device according to an embodiment of the present invention.
Hereinafter, some exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The figures are provided to allow those having ordinary skill in the art to understand the scope of the embodiments of the disclosure.
FIG. 1 is a diagram illustrating the layout of the patterns of a semiconductor memory device according to an embodiment of the present invention. In particular, FIG. 1 is a diagram illustrating the patterns of a semiconductor memory device which are formed by patterning the same material layer.
Referring to FIG. 1, first and second patterns L1 and L2 formed by patterning the same material layer may have different line widths. That is, each of the first patterns L1 may have a greater width than each of the second patterns L2. In particular, the second patterns L2 each having a relatively narrow width are repeatedly arranged at narrower intervals than the exposure resolution limit in order to improve the degree of high integration of semiconductor memory devices.
For example, in case of a NAND flash memory device, the first patterns L1 may be select lines formed in a select transistor region, and the second patterns L2 may be word lines formed in a memory cell region. A plurality of word lines L2 arranged between two adjacent select lines L1 may form a group, and a plurality of groups may be formed. The select lines L1 and the word lines L2 are, for example, parallel to each other. The word lines L2 are coupled to the gates of memory cells which form a cell string of the NAND flash memory device. The select lines L1 are coupled to the gate of a source select transistor for selecting a cell string or the gate of a drain select transistor.
An interval between the word lines L2 coupled to the memory cells may be set to be narrower than the exposure resolution limit in order to improve the degree of high integration of the devices. The drain select transistor and the source select transistor coupled to the select lines L1 have a different electrical characteristic from the memory cells. Furthermore, a contact plug is formed between adjacent select lines L1, e.g., at a boundary between the groups. Accordingly, an interval between the adjacent select lines L1 may be formed to be wider than the interval between the word lines L2 in order to secure a space where the contact plug is to be formed. Furthermore, in order to secure an electrical characteristic of the select lines L1, each select lines L1 may be formed to have a greater line width than the word line L2.
The word lines and the select lines of the NAND flash memory device have been described as the first and the second patterns L1 and L2, but the present invention is not limited thereto.
Referring to FIG. 2A, a target layer 109, including first regions R1 and second regions R2 spaced apart from each other, is formed over a semiconductor substrate 101. The first regions R1 arranged between each of the second regions R2. Here, the first region R1 has a wider width than each of the second patterns to be formed in the second regions R2. The first patterns are arranged at intervals wider than the second patterns and formed in the first region R1. The second region R2 is a region where the second patterns are formed to have narrow widths and narrow intervals in order to overcome the exposure resolution limit.
The target layer 109 may be a portion of the semiconductor substrate 101 or may be a stack layer including at least one layer formed over the semiconductor substrate 101. For example, the stack layer may be a single layer, such as a hard mask layer or a material layer for the semiconductor memory device, or a dual layer, including a material layer for the semiconductor memory device and a hard mask layer formed over the material layer. The material layer may be a single layer, such as an insulating layer or a conductive layer, or a multi-layer including an insulating layer and a conductive layer.
First to fourth auxiliary layers 113, 115, 117, and 119 are formed over the target layer 109. The first auxiliary layer 113 may be a material layer having a different etch selectivity from a material layer for spacers to be formed in a subsequent process. Also, the third auxiliary layer 117 may be a material layer having a different etch selectivity from a material layer for auxiliary spacers to be formed in a subsequent process. The second auxiliary layer 115 functions as an etch mask when the first auxiliary layer 113 is etched. Here, the second auxiliary layer 115 may be a material layer having a different etch selectivity from the first auxiliary layer 113. The fourth auxiliary layer 119 functions as an etch mask when the third auxiliary layer 117 is etched. Here, the fourth auxiliary layer 119 may be a material layer having a different etch selectivity from the third auxiliary layer 117.
For example, the material layer for the spacers and the material layer for the auxiliary spacers may be formed of an oxide layer. The first auxiliary layer 113 may be formed of amorphous carbon. The second auxiliary layer 115 may be formed of SiON. The third auxiliary layer 117 may be formed of amorphous carbon, and the fourth auxiliary layer 119 may be formed of Undoped Silicate Glass (USG).
Next, first and second photoresist patterns 121 a and 121 b are formed on the fourth auxiliary layer 119 by using a photolithography process employing an exposure mask. The first photoresist patterns 121 a are formed on the fourth auxiliary layer 119 corresponding to the first region R1. The second photoresist patterns 121 b are formed on the fourth auxiliary layer 119 corresponding to the second regions R2. An alignment error between the first and the second photoresist patterns 121 a and 121 b may not occur because an arrangement of the first and the second photoresist patterns 121 a and 121 b is determined according to blocked regions and exposed regions formed in the exposure mask. In order to improve the degree of high integration of the semiconductor memory devices, each of the first and the second photoresist patterns 121 a and 121 b is formed to have a minimum line width according to the exposure resolution limit.
According to an example, in order to form the alignment margin of an exposure mask when overlap patterns are subsequently formed, an interval between the first photoresist pattern 121 a and the second photoresist pattern 121 b is 4/3 of the width of the second photoresist pattern 121 b. Furthermore, in order to form the second patterns with a uniform interval, an interval between adjacent second photoresist patterns 121 b formed on the fourth auxiliary layer 119 corresponding to the second regions R2 is 5/3 of the width of the second photoresist pattern 121 b, although not shown.
In addition, the number of first photoresist patterns 121 a may vary according to the width of the first pattern to be formed. FIGS. 2A to 2H show an example where the width of the first pattern is four times the interval between the second patterns. In this case, the first photoresist pattern 121 a has the same width as the second photoresist pattern 121 b. The first photoresist patterns 121 a are formed on the fourth auxiliary layer 119 corresponding to edges of both sides of the first region R1 so that the first patterns are formed to be adjacent to each other in the first region R1. Here, in order for the interval between the first patterns to be wider than the interval between the second patterns, the interval between the first photoresist patterns 121 a is greater than the interval between the second photoresist patterns 121 b in the first region R1.
Referring to FIG. 2B, the exposed regions of the fourth auxiliary layer 119 are removed by using the first and the second photoresist patterns 121 a and 121 b of FIG. 2A as a mask. Next, the exposed regions of the third auxiliary layer 117 are removed. If the third auxiliary layer 117 is too thick and thus the third auxiliary layer 117 may not be used as a mask because the first and the second photoresist patterns 121 a and 121 b are removed when etching the exposed regions of the third auxiliary layer 117, the fourth auxiliary layer 119 may be used as a mask.
Consequently, first and second auxiliary partition patterns 123 a and 123 b, each having a stack structure of third and fourth auxiliary layers 119 a and 117 a remaining after the exposed regions of the third and the fourth auxiliary layers are etched, are formed. The first auxiliary partition patterns 123 a formed on the lower side of the first photoresist patterns may have the same widths and intervals as the first photoresist patterns. The second auxiliary partition patterns 123 b formed on the lower side of the second photoresist patterns may have the same widths and intervals as the second photoresist patterns. After the first and the second partition patterns 123 a and 123 b are formed, remaining first and second photoresist patterns are removed by a strip process.
Next, first auxiliary spacers 125 a are formed on the sidewalls of the first partition patterns 123 a, and second auxiliary spacers 125 b are formed on the sidewalls of the second partition patterns 123 b. The first and the second auxiliary spacers 125 a and 125 b are formed by depositing a material layer for the auxiliary spacers on a surface of the entire structure in which the first and the second auxiliary partition patterns 123 a and 123 b are formed and then etching the material layer by using a blanket etch process, such as etch-back, so that a top surface of the first and the second auxiliary partition patterns 123 a and 123 b is exposed.
According to an example, in order to form the second patterns with a uniform interval, the width of each of the first and the second auxiliary spacers 125 a and 125 b is formed to be ⅓ of the width of the second photoresist pattern or ⅓ of the width of the second auxiliary partition pattern 123 b. The width of each of the first and the second auxiliary spacers 125 a and 125 b may become ⅓ of the width of the second auxiliary partition pattern 123 b by controlling a deposition thickness of the material layer for the auxiliary spacers when the material layer for the auxiliary spacers is deposited. An interval between the first and the second auxiliary partition patterns 123 a and 123 b is 4/3 of the width of the second auxiliary partition pattern 123 b, and the width of each of the first and the second auxiliary spacers 125 a and 125 b is ⅓ of the width of the second auxiliary partition pattern 123 b. Thus, the width of an opening formed between the first and the second spacers 125 a and 125 b adjacent to each other is ⅔ of the width of the second auxiliary partition pattern 123 b. Although not shown, since an interval between the second auxiliary partition patterns 123 b is 5/3 of the width of the second auxiliary partition pattern 123 b, the width of an opening formed between the second auxiliary partition patterns 123 b is identical with the width of the second auxiliary partition pattern 123 b.
Referring to FIG. 2C, some regions of the second auxiliary layer 115, not overlapping with the first and the second auxiliary spacers 125 a and 125 b, are exposed by removing the first and the second auxiliary partition patterns 123 a and 123 b.
Referring to FIG. 2D, the exposed regions of the second auxiliary layer 115 are removed by using the first and the second auxiliary spacers 125 a and 125 b as an etch mask. Next, the exposed regions of the first auxiliary layer 113 are removed. If the first auxiliary layer 113 is too thick and thus the first and the second auxiliary spacers 125 a and 125 b may not be used as a mask because the first and the second auxiliary spacers 125 a and 125 b are removed when etching the exposed regions of the first auxiliary layer 113, the second auxiliary layer 115 may be used as a mask.
Consequently, first and second partition patterns 127 a and 127 b, each having a stack structure of the first and the second auxiliary layers 113 a and 115 a remaining after the exposed regions of the first and the second auxiliary layers are etched, are formed. The first partition patterns 127 a formed the lower sides of the first auxiliary spacers 125 a of FIG. 2C, respectively, have the same widths and intervals as the first auxiliary spacers 125 a. The second partition patterns 127 b formed under the second auxiliary spacers 125 b of FIG. 2C, respectively, have the same widths and intervals as the second auxiliary spacers 125 b. After the first and the second partition patterns 127 a and 127 b are formed, the first and the second auxiliary spacers are removed.
As a result of a series of the processes, an interval between the first partition pattern 127 a and the second partition pattern 127 b becomes twice the width of the first partition pattern 127 a or the width of the second partition pattern 127 b, and an interval between the second partition patterns 127 b becomes triple the width of the first partition pattern 127 a or the width of the second partition pattern 127 b. Furthermore, an interval between the two first partition patterns 127 a adjacent to the second partition pattern 127 b becomes triple the width of the first partition pattern 127 a or the width of the second partition pattern 127 b.
Referring to FIG. 2E, first spacers 129 a are formed on the side walls of the first partition patterns 127 a, and second spacers 129 b are formed on the side walls of the second partition patterns 127 b. The first and the second spacers 129 a and 129 b are formed by depositing a material layer for the spacers on a surface of the entire structure in which the first and the second partition patterns 127 a and 127 b are formed and then etching the material layer by using a blanket etch process, such as etch-back, so that a top surface of the first and the second partition patterns 127 and 127 b is exposed.
In order to form the second patterns with a uniform interval, the width of each of the first and the second spacers 129 a and 129 b is identical with the width of the first partition pattern 127 a or the second partition pattern 127 b. The width of each of the first and the second spacers 129 a and 129 b may become identical with the width of the first partition pattern 127 a or the second partition pattern 127 b by controlling a deposition thickness of the material layer for the spacers when the material layer for the spacers is deposited.
The first and the second spacers are coupled between a space between the first and the second partition patterns 127 a and 127 b, each having a width twice greater than the width of the first partition pattern 127 a or the second partition pattern, thus becoming third spacers 129 c.
Referring to FIG. 2F, some regions of target layer 109, not overlapping with the first to third spacers 129 a, 129 b, and 129 c, are exposed by removing the first and the second partition patterns 127 a and 127 b exposed in FIG. 2E.
Referring to FIG. 2G, in order to form the first patterns each having a greater width than the second pattern, an overlap pattern 131, blocking the space between the third spacer 129 c and the first spacer 129 a and the space between the three first spacers 129 a adjacent to the third spacer 129 c, is formed. The overlap pattern 131 is a photoresist pattern formed by a photolithography process using an exposure mask.
An interval between the first to third spacers 129 a, 129 b, and 129 c and the width of each of the first to third spacers 129 a, 129 b, and 129 c are determined by, for example, a photolithography process and a deposition thickness of the material layer for the auxiliary spacers and the material layer for the spacers. Accordingly, an edge of one side of the first pattern corresponds to the edge of the third spacer 129 c and an edge of the other side of the first pattern corresponds to the edge of the first spacer 129 a so that the interval between the first patterns and the width of each of the first patterns are not different from predetermined values.
Also, an edge of one side of the overlap pattern 131 is arranged on a top surface of the third spacer 129 c, and an edge of the other side of the overlap pattern 131, facing the edge of the top surface of the third spacer 129 c, is arranged on a top surface of the first spacer 129 a. In this case, since the edge of one side of the overlap pattern 131 is arranged on the top surface of the third spacer 129 c wider than each of the first and the second spacers 129 a and 129 b, the overlap pattern 131 can have a sufficient alignment margin. The edge of the other side of the overlap pattern 131 is positioned according to the width of the overlap pattern 131.
Referring to FIG. 2H, the exposed regions of the target layer 109 are removed by using the first to third spacers 129 a, 129 b, and 129 c and the overlap patterns 131 in FIG. 2G, thereby forming the first patterns L1 and the second patterns L2. Each of the first patterns L1 has a first width under the overlap patterns 131 and the first and the third spacers 129 a and 129 c overlapping with the overlap patterns 131. The second patterns L2 have the same widths and the same intervals as the second spacers 129 b, respectively, under the second spacers 129 b.
Furthermore, each of the second patterns L2 has a second width narrower than the first width. As a result of the processes described with reference to FIGS. 2A to 2H, the width of each first pattern L1 is four times the interval between the second patterns L2, and an interval between the first pattern L1 and the second pattern L2 is the same as an interval between the second patterns L2. Furthermore, the interval between the first patterns L1 adjacent to each other is automatically adjusted to the interval between the first spacers not blocked by the overlap pattern.
FIGS. 3A to 3C are diagrams illustrating line widths having relatively wide patterns when the method of forming the patterns of the semiconductor memory device shown in FIGS. 2A to 2H is used.
As described above with reference to FIG. 2A, one or more of first photoresist patterns may be formed on the fourth auxiliary layer, corresponding to the first region, according to the width of the first pattern to be formed. As shown in FIGS. 3A to 3C, however, in order to secure the alignment margin of overlap patterns 131 to be subsequently formed, an interval between a first photoresist pattern 121 a, 121 a 1, or 121 a 2 formed on the fourth auxiliary layer, corresponding to the first region, and a second photoresist pattern 121 b adjacent to the first photoresist pattern 121 a, 121 a 1, or 121 a 2 is, for example, 4/3 of the line width of the second photoresist pattern 121 b.
Furthermore, in order to form the first patterns with an interval greater than the interval between the second patterns, as shown in FIG. 3A, the first photoresist patterns 121 a are formed at the edges of the first region, and an interval between the first photoresist patterns 121 a formed on edges of both sides of the first region is formed to be greater than an interval between the second photoresist patterns 121 b. In some embodiments, as shown in FIG. 3B, the first photoresist pattern 121 a 1 may be formed at the center of the top of the first region, and the width of the first photoresist pattern 121 a 1 is formed to be greater than the width of the second photoresist pattern 121 b. In some embodiments, as shown in FIG. 3C, the first parts 121 a 1 of the first photoresist pattern may be formed on the edges of the first region, and the second part 121 a 2 of the first photoresist pattern is formed between the first parts 121 a 1. The second part 121 a 2 has a greater width than the second photoresist pattern 121 b. An interval between the first part 121 a 1 and the second part 121 a 2 may be 5/3 of the width of the second photoresist pattern 121 b. The width of the first photoresist pattern 121 a of FIG. 3A and the width of the first part 121 a 1 of FIG. 3C is identical with the width of the second photoresist pattern 121 b, having a minimum line width according to the exposure resolution limit, in order to finely control the width of the first pattern.
After the first and the second photoresist patterns 121 a, 121 a 1, 121 a 2, and 121 b are formed, in order to form the second patterns P1 with a uniform interval, first and second auxiliary spacers 125 a, 125 a 1, 125 a 2, and 125 b, each having a width that is ⅓ of the width of the second photoresist pattern 121 b are formed by using a deposition process and an etch process for a material layer for auxiliary spacers. Next, in order to form the second patterns P1 with a uniform interval, first and second spacers 129 a and 129 b, each having the same width as each of the first and the second auxiliary spacers 125 a, 125 a 1, 125 a 2, and 125 b, are formed by a deposition process and an etch process for a material layer for spacers.
According to the constraint conditions of the processes, the number of first spacers 129 a formed over the edge of one side of the first region may be increased or decreased every two as compared with FIG. 3A. Thus, the width of the first pattern may have only an even-numbered multiple of an interval between the second patterns P1. Accordingly, there is a need for a method of forming the patterns of a semiconductor memory device so that the width of the first pattern can have values of various ranges. In particular, there is a need for a method of forming the first pattern, having a width by one interval P1 smaller than the first pattern having the width four times the interval between the second patterns as shown in FIG. 3A.
According to an embodiment of the present invention, an interval between the second patterns can be finer than the exposure resolution limit and the width of the first pattern is greater than the interval P between the second patterns, but the width may have values of various ranges.
FIGS. 4A to 4H are cross-sectional views illustrating a method of forming the patterns of a semiconductor memory device according to an embodiment of the present invention. Furthermore, FIGS. 5A to 5C are cross-sectional views illustrating a method of forming the patterns of a semiconductor memory device according to an embodiment of the present invention. In particular, FIGS. 4A to 5C are cross-sectional views taken along line a direction crossing the first and the second patterns L1 and L2 shown in FIG. 1.
Referring to FIG. 4A, a target layer 209, including first regions R21 and second regions R22 spaced apart from each other, is formed over a semiconductor substrate 201. The first regions R21 arranged between each of the second regions R22. The first region R21 has a wider width than each of the second patterns to be formed in the second regions R22. The first patterns are arranged at intervals wider than the second patterns and formed in the first region R21. The second region R22 is a region where the second patterns are formed to have narrow widths and narrow intervals in order to overcome the exposure resolution limit.
The target layer 209 may be a portion of the semiconductor substrate 201 or may be a stack layer including at least one layer formed over the semiconductor substrate 201. For example, the stack layer may be a single layer, such as a hard mask layer or a material layer for the semiconductor memory device, or a dual layer, including a material layer for the semiconductor memory device and a hard mask layer formed over the material layer. The material layer may be a single layer, such as an insulating layer or a conductive layer, or a multi-layer including an insulating layer and a conductive layer.
First to fourth auxiliary layers 213, 215, 217, and 219 are formed over the target layer 209. The first auxiliary layer 213 may be a material layer having a different etch selectivity from a material layer for spacers to be formed in a subsequent process. The third auxiliary layer 217 may be a material layer having a different etch selectivity from a material layer for auxiliary spacers to be formed in a subsequent process. The second auxiliary layer 215 functions as an etch mask when the first auxiliary layer 213 is etched. Also, the second auxiliary layer 215 may be a material layer having a different etch selectivity from the first auxiliary layer 213. The fourth auxiliary layer 219 functions as an etch mask when the third auxiliary layer 217 is etched. Also, the fourth auxiliary layer 219 may be a material layer having a different etch selectivity from the third auxiliary layer 217.
For example, the material layer for the spacers and the material layer for the auxiliary spacers may be formed of an oxide layer. The first auxiliary layer 213 may be formed of amorphous carbon. The second auxiliary layer 215 may be formed of SiON. The third auxiliary layer 217 may be formed of amorphous carbon, and the fourth auxiliary layer 219 may be formed of Undoped Silicate Glass (USG).
Next, first to third photoresist patterns 221 a 1, 221 a 2, and 221 b are formed on the fourth auxiliary layer 219 by using a photolithography process employing an exposure mask. The first photoresist patterns 221 a 1 are formed on the fourth auxiliary layer 219 corresponding to the first region R21. The second photoresist patterns 221 a 2 are formed on the fourth auxiliary layer 219 corresponding to the second regions R22. In particular, the first photoresist pattern 221 a 1 is formed at the center of the top of the first region R21, and arranged between each of the second photoresist patterns 221 a 2. The number of second photoresist patterns 221 a 2 formed between the first photoresist pattern 221 a 1 and the third photoresist patterns 221 b is proportional to the width of each of first patterns to be formed subsequently.
An example where the width of the first pattern is triple the interval between second patterns to be formed subsequently is shown in FIGS. 4A to 4H. In this case, a second photoresist pattern 221 a 2 is formed between the first and the third photoresist patterns 221 a 1 and 221 b. An alignment error may not occur between the first to third photoresist patterns 221 a 1, 221 a 2, and 221 b because an arrangement of the first to third photoresist patterns 221 a 1, 221 a 2, and 221 b is determined according to blocked regions and exposed regions formed in the exposure mask.
In order to improve the degree of high integration of semiconductor memory devices, each of the second and the third photoresist patterns 221 a 2 and 221 b may have a minimum line width according to the exposure resolution limit. According to an example, the width of each of the second photoresist patterns 221 a 2 may be identical with the width of the third photoresist pattern 221 b so that the width of the first pattern is identical with an interval between the second patterns. Furthermore, the width of the third photoresist pattern 221 b may be greater than the exposure resolution limit. In this case, the width of the second photoresist pattern 221 a 2 may be ⅓ of the width of the third photoresist pattern 221 b. The width of the first photoresist pattern 221 a 1 is greater than the width of the third photoresist pattern 221 b so that an interval between the first patterns is wider than an interval between the second patterns.
In order to form the second patterns with a uniform interval, the third photoresist patterns 221 b have the same width, and an interval between the third photoresist patterns 221 b may be 5/3 of the width of the third photoresist pattern 221 b, although not shown. According to an example, in order to secure the alignment margin of an exposure mask and also form the first pattern having a width odd-numbered multiple of an interval between the second patterns when auxiliary overlap patterns for determining an interval between the first patterns are subsequently formed, an interval between the first photoresist pattern 221 a 1 and the second photoresist pattern 221 a 2 adjacent to each other is ⅔ of the width of the third photoresist pattern 221 b. Furthermore, in order to secure the alignment margin of an exposure mask when overlap patterns for determining the widths of the first patterns are subsequently formed, an interval between the second photoresist pattern 221 a 2 and the third photoresist pattern 221 b is 4/3 of the width of the third photoresist pattern 221 b.
If the plurality of second photoresist patterns 221 a 2 is formed between the first and the third photoresist patterns 221 a 1 and 221 b, an interval between the second photoresist patterns 221 a 2 adjacent to each other is identical with an interval between the third photoresist patterns 221 b so that the width of the first pattern is identical with the interval between the second patterns.
Referring to FIG. 5A, unlike FIG. 4A, first and second photoresist patterns 321 a and 321 b may be formed on a fourth auxiliary layer 219. The first photoresist patterns 321 a are formed on the fourth auxiliary layer 219 corresponding to edges of both sides of the first region R21. The second photoresist patterns 321 b are formed on the fourth auxiliary layer 219 corresponding to the second regions R22.
According to an example, an interval between the first photoresist pattern 321 a and the second photoresist pattern 321 b adjacent to each other is 4/3 of the width of the second photoresist pattern 321 b. Furthermore, in order to form second patterns with a uniform interval, an interval between the second photoresist patterns 321 b adjacent to each other is 5/3 of the width of the second photoresist pattern 321 b, although not shown.
If the width of each of the first photoresist pattern 321 a and the second photoresist pattern 321 b has a minimum line width according to the exposure resolution limit in order to improve the degree of high integration of the semiconductor memory devices, the first photoresist pattern 321 a and the second photoresist pattern 321 b are formed to have the same width. Furthermore, an interval between the first photoresist patterns 321 a is greater than an interval between the second photoresist patterns 321 b.
Referring to FIG. 4B, the exposed regions of the fourth auxiliary layer 219 are removed by using the first to third photoresist patterns 221 a 1, 221 a 2, and 221 b of FIG. 4A as a mask. Next, the exposed regions of a third auxiliary layer 217 are removed. If the third auxiliary layer 217 is too thick and thus the first to third photoresist patterns 221 a 1, 221 a 2, and 221 b may not be used as a mask because the first to third photoresist patterns 221 a 1, 221 a 2, 221 b are removed when etching the exposed regions of the third auxiliary layer 217, the fourth auxiliary layer 219 may be used as a mask.
Third and fourth auxiliary layers 219 a and 217 a remaining after the exposed regions of the third and the fourth auxiliary layers are etched become first to third auxiliary partition patterns 223 a 1, 223 a 2, and 223 b. The first auxiliary partition pattern 223 a 1 is formed to have the same width as the first photoresist pattern under the first photoresist pattern. The second auxiliary partition patterns 223 a 2 are formed to have the same widths and intervals as the second photoresist patterns under the second photoresist patterns, respectively. The third auxiliary partition patterns 223 b are formed to have the same widths and intervals as the third photoresist patterns under the third photoresist patterns, respectively. That is, the first and the second auxiliary partition patterns 223 a 1 and 223 a 2 are formed in the first region R21, and the first auxiliary partition pattern 223 a 1 is arranged between each of the second auxiliary partitions 223 a 2.
Furthermore, according to an example, the first and the second auxiliary partition patterns 223 a 1 and 223 a 2 are spaced apart from each other at an interval of ⅔ of the width of the third auxiliary partition pattern 223 b. The width of the second auxiliary partition pattern 223 a 2 is identical with the width of the third auxiliary partition pattern 223 b or is ⅓ of the width of the third auxiliary partition pattern 223 b. The width of the first auxiliary partition pattern 223 a 1 is greater than the interval between the third auxiliary partition patterns 223 b. The third auxiliary partition patterns 223 b have the same width. Although not shown, the third auxiliary partition patterns 223 b are spaced apart from each other at an interval of 5/3 of the width of the third auxiliary partition pattern 223 b. The second auxiliary partition pattern 223 a 2 and the third auxiliary partition pattern 223 b are spaced apart from each other at an interval of 4/3 of the width of the third auxiliary partition pattern 223 b.
The first to third photoresist patterns remaining after the first to third auxiliary partition patterns 223 a 1, 223 a 2, and 223 b are formed are removed by a strip process.
Next, after a material layer for auxiliary spacers is deposited on a surface of the entire structure in which the first to third auxiliary partition patterns 223 a 1, 223 a 2, and 223 b are formed, the material layer for the auxiliary spacers is etched using a blanket etch process, such as etch-back process, so that a top surface of the first to third auxiliary partition patterns 223 a 1, 223 a 2, and 223 b is exposed. Thus, first to third auxiliary spacers 225 a, 225 b, and 225 c are formed.
Each of the first auxiliary spacers 225 a is the material layer for the auxiliary spacers which is formed between the first auxiliary partition pattern 223 a 1 and the second auxiliary partition pattern 223 a 2. The second auxiliary spacers 225 b are the material layers for the auxiliary spacers which remain on the sidewalls of the third auxiliary partition patterns 223 b. Each of the third auxiliary spacers 225 c is the material layer for the auxiliary spacers which remains on a sidewall on one side of the second auxiliary partition pattern 223 a 2 adjacent to the third auxiliary partition pattern 221 b. The first auxiliary spacers 225 a are spaced apart from each other and the first auxiliary partition pattern 223 a 1 is arranged between each of the first auxiliary spacers 225 a. The second auxiliary spacers 225 b are spaced apart from each other at an interval narrower than the width of the first auxiliary spacer 225 a. Each of the second auxiliary spacers 225 b has a narrower width than the first auxiliary spacer 225 a. The third auxiliary spacer 225 c has the same width as the second auxiliary spacer 225 b between the first and the second auxiliary spacers 225 a and 225 b.
According to an example, in order to form the second patterns with a uniform interval, the width of the second auxiliary spacer 225 b is ⅓ of the width of the third auxiliary partition pattern 223 b. The width of the second auxiliary spacer 225 b may be adjusted by controlling a deposition thickness of the material layer for the auxiliary spacers when the material layer for the auxiliary spacers is deposited. Each of the third auxiliary spacers 225 c formed simultaneously with the second auxiliary spacers 225 b has the same width as the second auxiliary spacer 225 b.
Furthermore, the first and the second auxiliary partition patterns 223 a 1 and 223 a 2 are spaced apart from each other at an interval of ⅔ of the width of the third auxiliary partition pattern 223 b, and thus the material layer for the auxiliary spacers is formed between the first and the second auxiliary partition patterns 223 a 1 and 223 a 2. Furthermore, the first auxiliary spacer 225 a formed between the first and the second auxiliary partition patterns 223 a 1 and 223 a 2 fills the space between the first and the second auxiliary partition patterns 223 a 1 and 223 a 2 and has a width twice the width of the second or third auxiliary spacer 225 b or 223 c. In addition, an interval between the second and the third auxiliary partition patterns 223 a 2 and 223 b is 4/3 of the width of the third auxiliary partition pattern 223 b, and thus the width of an opening formed between the second and the third auxiliary spacers 225 b and 225 c is ⅔ of the width of the third auxiliary partition pattern 223 b. Although not shown, the third auxiliary partition patterns 223 b are spaced apart from one another at intervals of 5/3 of the width of the third auxiliary partition pattern 223 b, and the width of a region not blocked by the second auxiliary spacer 225 b between the third auxiliary partition patterns 223 b is identical with the width of the third auxiliary partition pattern 223 b.
Referring to FIG. 5B, unlike FIG. 4B, the exposed regions of the fourth auxiliary layer 219 are removed by using the first and the second photoresist patterns 221 a and 221 b of FIG. 5A as an etch mask. Next, the exposed regions of the third auxiliary layer 217 are removed. If the third auxiliary layer 217 is too thick and thus the first and the second photoresist patterns 221 a and 221 b may not be used as a mask because the first and the second photoresist patterns 221 a and 221 b are removed when etching the exposed regions of the third auxiliary layer 217, the fourth auxiliary layer 219 may be used as a mask.
Third and fourth auxiliary layers 219 a and 217 a remaining after the exposed regions of the third and the fourth auxiliary layers are etched become first and second auxiliary partition patterns 323 a and 323 b. The first and the second photoresist patterns remaining after the first and the second partition patterns 323 a and 323 b are removed by a strip process.
Next, first auxiliary spacers 325 a are formed on the sidewalls of the first partition patterns 323 a, and second auxiliary spacers 325 b are formed on the sidewalls of the second partition patterns 323 b. The first and the second auxiliary spacers 325 a and 325 b are formed by depositing a material layer for auxiliary spacers on a surface of the entire structure in which the first and the second auxiliary partition patterns 323 a and 323 b are formed and then etching the material layer for the spacers by using a blanket etch process, such as etch-back process, so that a top surface of the first and the second auxiliary partition patterns 323 a and 323 b is exposed.
The arrangement of the first and the second auxiliary partition patterns 323 a and 323 b and the width of each of the first and the second auxiliary partition patterns 323 a and 323 b are the same as the first and the second photoresist patterns of FIG. 5A.
Furthermore, according to an example, the first auxiliary spacers 325 a are the material layers for the auxiliary spacers which remain on the sidewalls of each of the first auxiliary partition patterns 323 a. The second auxiliary spacers 325 b are the material layers for the auxiliary spacers which remain on the sidewalls of each of the second auxiliary partition patterns 323 b. In order to form the second patterns with a uniform interval, the width of each of the first and the second auxiliary spacers 325 a and 325 b is ⅓ of the width of each of the first and the second auxiliary partition patterns 323 a and 323 b. The width of each of the first and the second auxiliary spacers 325 a and 325 b may be adjusted by controlling a deposition thickness of the material layer for the auxiliary spacers when the material layer for the auxiliary spacers is deposited.
Referring to FIG. 4C, some regions of the second auxiliary layer 215 not overlapping with the first to third auxiliary spacers 225 a, 225 b, and 225 c are exposed by removing the first to third auxiliary partition patterns 223 a 1, 223 a 2, and 223 b exposed in FIG. 4B. Next, an auxiliary overlap pattern 226 blocking the space between the first spacers 225 a is formed. The auxiliary overlap pattern 226 is a photoresist pattern formed by a photolithography process using an exposure mask. In particular, the auxiliary overlap pattern 226 may be formed simultaneously with a photoresist pattern for blocking a peripheral region where circuit elements for driving the semiconductor memory device are to be formed.
The edges of the auxiliary overlap pattern 226 are formed on the top surfaces of the first auxiliary spacers 225 a, each having a greater width than each of the second and the third auxiliary spacers 225 b and 225 c. Accordingly, the alignment margin of the auxiliary overlap pattern 226 can be secured.
Referring to FIG. 5C, unlike FIG. 4C, some regions of the second auxiliary layer 215 not overlapping with the first and the second auxiliary spacers 325 a and 325 b are exposed by removing the first and the second auxiliary partition patterns 323 a and 323 b exposed in FIG. 5B. Furthermore, an auxiliary overlap pattern 326 that blocks the second auxiliary layer 215 between the first auxiliary partition patterns in FIG. 5B is formed. The auxiliary overlap pattern 326 is a photoresist pattern formed by a photolithography process using an exposure mask. In particular, the auxiliary overlap pattern 326 may be formed simultaneously with a photoresist pattern for blocking a peripheral region where circuit elements for driving the semiconductor memory device are to be formed.
Edges on both sides of the auxiliary overlap pattern 326 are formed on the top surfaces of the first auxiliary spacers 325 a formed in the space between the first auxiliary partition patterns.
Referring to FIG. 4D, the exposed regions of the second auxiliary layer 215 are removed by using the first to third auxiliary spacers 225 a, 225 b, and 225 c of FIG. 4C and the auxiliary overlap pattern 226 as a mask. Next, the exposed regions of the first auxiliary layer 213 are removed. In addition, unlike FIG. 4D, the exposed regions of the second auxiliary layer 215 may be removed by using the first and the second auxiliary spacers 325 a and 325 b of FIG. 5C and the auxiliary overlap pattern 326 as an etch mask. Next, the exposed regions of the first auxiliary layer 213 are removed.
If the first auxiliary layer 213 is too thick and thus the first to third auxiliary spacers 225 a, 325 a, 225 b, 325 b, and 225 c and the auxiliary overlap patterns 226 and 326 may not be used as a mask because the first to third auxiliary spacers 225 a, 325 a, 225 b, 325 b, and 225 c and the auxiliary overlap patterns 226 and 326 are removed when etching the exposed regions of the first auxiliary layer 213, the second auxiliary layer 215 may be used as a mask.
First and second auxiliary layers 213 a and 215 a remaining after the exposed regions of the first and the second auxiliary layers are etched become first to third partition patterns 227 a 1, 227 a 2, and 227 b. The first partition pattern 227 a 1 is formed under the first auxiliary spacers 225 a and the auxiliary overlap pattern 226 of FIG. 4C. The second partition patterns 227 a 2 are formed under the third auxiliary spacers 225 c of FIG. 4C, respectively. The third partition patterns 227 b are formed under the second auxiliary spacers 225 b of FIG. 4C, respectively. An arrangement of the first to third partition patterns 227 a 1, 227 a 2, and 227 b is determined according to an arrangement of the first to third auxiliary spacers 225 a, 225 b, and 225 c and the auxiliary overlap pattern 226 of FIG. 4C.
In some embodiments, the first partition pattern 227 a 1 may be formed under the auxiliary overlap pattern 326 and the first auxiliary spacers 325 a overlapping with the auxiliary overlap pattern 326 of FIG. 5C. The second partition patterns 227 a 2 may be formed under the first auxiliary spacers 325 a, respectively, not overlapping with the auxiliary overlap pattern 326, from the first auxiliary spacers 325 a of FIG. 5C. The third partition patterns 227 b are formed under the second auxiliary spacers 325 b of FIG. 5C, respectively. An arrangement of the first to third partition patterns 227 a 1, 227 a 2, and 227 b is determined according to an arrangement of the first and the second auxiliary spacers 325 a and 325 b and the overlap pattern 326 of FIG. 5C.
According to the processes described with reference to FIGS. 4A to 4D or the processes described with reference to FIGS. 5A to 5C, the first partition pattern 227 a 1 is formed over the target layer 209 corresponding to the center of the first region R21. The first partition pattern 227 a 1 is arranged between the second partition patterns 227 a 2 over the target layer 209 corresponding to the first region R21. Furthermore, the third partition patterns 227 b are formed over the target layer 209 corresponding to the second regions R22. After the first to third partition patterns 227 a 1, 227 a 2, and 227 b are formed, the first to third auxiliary spacers and the auxiliary overlap pattern are removed. Thus, the first to third partition patterns 227 a 1, 227 a 2, and 227 b are spaced apart from one another.
As a result of a series of the processes, each of an interval between the first partition pattern 227 a 1 and the second partition pattern 227 a 2 adjacent to each other and an interval between the third partition patterns 227 b becomes triple the width of the second or third auxiliary spacer. That is, each of the interval between the first partition pattern 227 a 1 and the second partition pattern 227 a 2 adjacent to each other and the interval between the third partition patterns 227 b becomes triple the width of each of the second and third partition patterns 227 a 2 and 227 b. Furthermore, an interval between the second partition pattern 227 a 2 and the third partition pattern 227 b adjacent to each other becomes twice the width of the second or third auxiliary spacer or becomes identical with the width of the second or third auxiliary spacer. That is, the interval between the second partition pattern 227 a 2 and the third partition pattern 227 b adjacent to each other becomes twice the width of the second or third partition pattern 227 a 2 or 227 b or becomes identical with the width of the second or third partition pattern 227 a 2 or 227 b.
Referring to FIG. 4E, a material layer for spacers is deposited on a surface of the entire surface in which the first to third partition patterns 227 a 1, 227 a 2, and 227 b are formed and then etched by using a blanket etch process, such as etch-back process, so that a top surface of the first to third partition patterns 227 a 1, 227 a 2, and 227 b is exposed. Thus, first to fourth spacers 229 a 1, 229 b, 229 c, and 229 a 2 are formed.
The first spacers 229 a 1 are the material layers for the spacers which remain on both sides of the first partition pattern 227 a 1. The second spacers 229 b are the material layers for the spacers which remain on the sidewalls of the third partition patterns 227 b between the third partition patterns 227 b. The third spacers 229 c are the material layers for the spacers formed between the second partition patterns 227 a 2 and the third partition patterns 227 b. The fourth spacers 229 a 2 are the material layers for the spacers which remain on sidewalls on one side of the second partition pattern 227 a 2 adjacent to the first partition pattern 227 a 1. The first spacers 229 a 1 are spaced apart from each other and the first partition pattern 227 a 1 is arranged between each of the first spacers 229 a 1. The second spacers 229 b are spaced apart from one another at intervals each narrower than the width of the first spacer 229 a 1 on the target layer 209 corresponding to the second regions R22, respectively. Each of the third spacers 229 c has a greater width than each of the first and the second spacers 229 a 1 and 229 b between the first and the second spacers 229 a 1 and 229 b. An odd number of the fourth spacers 229 a 2 are formed between the first spacer 229 a 1 and the third spacer 229 c.
In order to form the second patterns with a uniform interval, each of the second spacers 229 b has the same with as the third partition pattern 227 b. The width of the second spacer 229 b may be adjusted by controlling a deposition thickness of the material layer for the spacers when the material layer for the spacers is deposited. Each of the first and the fourth spacers 229 a 1 and 229 a 2 formed simultaneously with the second spacers 229 b also has the same width as the second spacer 229 b.
As a result of a series of the processes, a space between the second partition pattern 227 a 2 and the third partition pattern 227 b has a width twice the width of the third partition pattern 227 b or has the same width as the third partition pattern 227 b. Accordingly, the space between the second partition pattern 227 a 2 and the third partition pattern 227 b is filled with the material layer for the spacers, which has been deposited in the same thickness as the second partition pattern 227 a 2 on the sidewall of each of the second partition pattern 227 a 2 and the third partition pattern 227 b. Furthermore, the third auxiliary spacer 229 c formed between the second partition pattern 227 a 2 and the third partition pattern 227 b adjacent to each other fills a space between the second partition pattern 227 a 2 and the third partition pattern 227 b adjacent to each other and may have a width twice the width of the first, second, or fourth spacer 229 a 1, 229 b, or 229 a 2 or have the same width as the first, second, or fourth spacer 229 a 1, 229 b, or 229 a 2. Furthermore, an interval between the third partition patterns 227 b is triple the width of the third partition pattern 227 b, and the second spacer 229 b has the same width as the third partition pattern 227 b. Accordingly, the width of an opening formed between the second spacers 229 b between the third partition patterns 227 b is identical with the width of the third partition pattern 227 b.
Furthermore, an interval between the first partition pattern 227 a 1 and the second partition pattern 227 a 2 adjacent to each other is triple the width of the third partition pattern 227 b, and each of the first and the fourth spacers 229 a 1 and 229 a 2 has the same width as the third partition pattern 227 b. Accordingly, the width of an opening formed between the first and the fourth spacers 229 a 1 and 229 a 2 is identical with the width of the third partition pattern 227 b.
If the thickness of the material layer for the spacers is thick enough to be able to secure the alignment margin of overlap patterns to be formed in a subsequent process, the third auxiliary spacer 229 c has the same width as the second spacer 229 b.
Referring to FIG. 4F, some regions of the target layer 209, not overlapping with the first to fourth spacers 229 a 1, 229 b, 229 c, and 229 a 2, are exposed by removing the first to third partition patterns 227 a 1, 227 a 2, and 227 b exposed in FIG. 4E. Thus, all the first to fourth spacers 229 a 1, 229 b, 229 c, and 229 a 2 are spaced apart from one another. Here, the second spacers 229 b are repeatedly arranged at uniform intervals. Furthermore, each of the first, second, and fourth spacers 229 a 1, 229 b, and 229 a 2 has the same width as and the same interval between the second spacers 229 b.
Referring to FIG. 4G, overlap patterns 231, each blocking some regions of the target layer 209 exposed between the first spacer 229 a 1 and the third spacer 229 c, are formed. The overlap patterns 231 are photoresist patterns formed by using a photolithography process using an exposure mask.
If the deposition thickness of the material layer for the spacers is thin, the third auxiliary spacer 229 c is formed to have a greater width than each of the first, second, and fourth spacers 229 a 1, 229 b, and 229 a 2 by using the above process so that a sufficient alignment can be secured when the edges of the overlap pattern 231 are arranged on the top surfaces of the third auxiliary spacers 229 c.
An interval between the first to fourth spacers 229 a 1, 229 b, 229 c, and 229 a 2 and the width of each of the first to fourth spacers 229 a 1, 229 b, 229 c, and 229 a 2 are determined by, for example, the photolithography process and the deposition thicknesses of the material layer for the auxiliary spacers and the material layer for the spacers. Accordingly, the edges of the first patterns are formed to correspond to the edges of the third spacers 229 c so that an interval between the first patterns to be formed subsequently and the width of each first pattern are not different from predetermined values. In an embodiment of the present invention, the edges of the overlap patterns 231 are formed on the top surfaces of the third spacers 229 c by securing the alignment margin of the overlap patterns 231. Accordingly, the edges of the first patterns are aligned to corresponding edges of the third spacers 229 c in a subsequent process.
As a result of the processes of an embodiment of the present invention, if the width of the third spacer 229 c is twice the width of the second spacer 229 b, the width of each of the some regions of the target layer 209, blocked by the first, third, and fourth spacers 229 a 1, 229 c, and 229 a 2 overlapping with the overlap patterns 231 and the overlap patterns 231, becomes triple the interval P1′ between the second spacers 229 b (that is, an odd-numbered multiple). Furthermore, if the third spacer 229 c has the same width as the second spacer 229 b, the width of each of the some regions of the target layer 209, blocked by the first, third, and fourth spacers 229 a 1, 229 c, and 229 a 2 overlapping with the overlap patterns 231 and the overlap patterns 231, becomes about 2.5 times the interval P1′ between the second spacers 229 b.
Referring to FIG. 4H, first patterns L1 and second patterns L2 are defined by removing the exposed regions of the target layer 209 by using the first to fourth spacers 229 a 1, 229 b, 229 c, and 229 a 2 and the overlap patterns 231 of FIG. 4G as a mask. The first patterns L1 are formed to have first widths, respectively, under the overlap patterns 231 and the first, third, and fourth spacers 229 a 1, 229 c, and 229 a 2 overlapping with the overlap patterns 231. The second patterns L2 are formed to have the same widths and intervals as the second spacers 229 b under the second spacers 229 b, respectively. An interval between the first patterns L1 is wider than an interval between the second patterns L2. Furthermore, each of the second patterns L2 has the second width narrower than the first width.
As a result of the processes described with reference to FIGS. 4A to 4H, an interval between the first pattern L1 and the second pattern L2 adjacent to each other and an interval between the second patterns L2 is identical with the width of each of the first, second, and the fourth spacers. Furthermore, an interval between the first patterns L1 adjacent to each other is automatically adjusted to an interval between the first spacers not blocked by the overlap pattern. Furthermore, the width of each of the first patterns L1 may be triple the interval between the second patterns L2 or may be 2.5 times the interval between the second patterns L2.
According to an embodiment of the present invention, since an odd number of fourth spacers are formed between the first spacer and the third spacer adjacent to each other as a result of the processes described with reference to FIGS. 4A to 4H, the width of the first pattern L1 can be controlled so that it becomes a value other than an even-numbered multiple of the interval between the second patterns L2.
As described above, the first spacers spaced apart from each other at a first interval are formed on a portion of the target layer. The second spacers spaced apart from one another at second intervals are formed on a portion of the target layer. The third spacer is formed between the first spacer and the second spacer. The fourth spacer is formed between the first spacer and the third spacer. Next, the overlap pattern is formed to block some regions of the target layer exposed between the first spacer and the second spacers. Next, the exposed regions of the target layer are removed by using the first to fourth spacers and the overlap patterns as a mask. Accordingly, the patterns of different line widths can be formed at the same time.
Furthermore, according to an embodiment of the present invention, an odd number of fourth spacers are formed between the first spacer and the third spacer, and an interval between the first to fourth spacers and the width of each of the first to fourth spacers are controlled. Accordingly, patterns having relatively wide line widths can be formed with various widths, each greater than an interval between relatively narrow patterns.
1. A method of forming semiconductor memory device, comprising:
forming first to fourth spacers over a target layer including a first region and second regions adjacent to the first region, wherein a first spacer group including the first spacers spaced apart from each other at a first interval is formed in the first region of the target layer, a second spacer group including the second spacers spaced apart from one another at second intervals is formed in the second regions, a third spacer is formed between the first and the second spacer groups, and an odd number of fourth spacers are formed between the third spacer and the first spacer group;
forming an overlap pattern blocking the target layer exposed between the third spacer and the first spacer group; and
forming first patterns and second patterns, wherein the first patterns are spaced apart from each other at the first interval and formed to have first widths in the first region, and the second patterns are spaced apart from one another at the second intervals and formed to have second widths in the second regions by etching the target layer exposed between the first to fourth spacers and the overlap pattern.
2. The method of claim 1, wherein each of the third spacers has an identical width with each of the first and second spacers or has a greater width than each of the first and second spacers.
3. The method of claim 1, wherein the first interval is wider than the second interval.
4. The method of claim 1, wherein the first width is greater than the second width.
5. The method of claim 1, wherein each of the first spacers, the second spacers, and the fourth spacers has the same width as the second interval.
6. The method of claim 1, wherein a width of each of the third spacers is twice a width of the second spacer.
7. The method of claim 1, wherein the second width and the second interval are identical with each other.
8. The method of claim 1, wherein an interval between the second spacer group and the third spacer is identical with the second interval.
9. The method of claim 1, wherein an interval between the first spacer group and the fourth spacer is identical with the second interval.
10. The method of claim 1, wherein an interval between the third spacer and the fourth spacer is identical with the second interval.
11. The method of claim 1, wherein an edge of the overlap pattern is formed on a top surface of the third spacer.
12. The method of claim 1, wherein forming the first to fourth spacers comprises:
forming first to third partition patterns over the target layer, wherein the first partition pattern is arranged between the second partition patterns in the first region and the third partition patterns are arranged in the second regions;
depositing a material layer for spacers on a surface of the first to third partition patterns;
etching the material layer for the spacers to expose a top surface of the first to third partition patterns; and
removing the first to third partition patterns.
the material layer for the spacers remaining on both sides of the first partition pattern becomes the first spacers,
the material layer for the spacers remaining on sidewalls of the third partition patterns become the second spacers,
the material layer for the spacers remaining between the second partition pattern and the third partition pattern become the third spacers, and
the material layer for the spacers remaining on a sidewall of the second partition pattern on one side, adjacent to the first partition pattern, becomes the fourth spacers.
14. The method of claim 12, wherein forming the first to third partition patterns comprises:
forming an auxiliary layer on the target layer;
forming first to third auxiliary spacers on the auxiliary layer, wherein a first auxiliary spacer group including the first auxiliary spacers is formed in the first region, a second auxiliary spacer group including the second auxiliary spacers each having a narrower width than the first auxiliary spacer is formed in the second regions, and the third auxiliary spacer having an identical width with the second auxiliary spacer is formed in the first region between the first auxiliary spacer group and the second auxiliary spacer group;
forming an auxiliary overlap pattern blocking the auxiliary layer exposed between the first auxiliary spacers;
etching the auxiliary layer exposed between the first to third auxiliary spacers and the auxiliary overlap pattern; and
removing the first to third auxiliary spacers and the auxiliary overlap pattern.
15. The method of claim 14, wherein edges of the auxiliary overlap pattern are formed on a top surface of the first auxiliary spacers.
the auxiliary layer remaining under the auxiliary overlap pattern and the first auxiliary spacers becomes the first partition pattern,
the auxiliary layer remaining under the third auxiliary spacers becomes the second partition patterns, and
the auxiliary layer remaining under the second auxiliary spacers become the third partition patterns.
17. The method of claim 14, wherein a width of each of the first auxiliary spacers is twice a width of each of the second and the third auxiliary spacers.
18. The method of claim 14, wherein a width of each of the second and the third auxiliary spacers is ⅓ of an interval between the second auxiliary spacers adjacent to each other.
19. The method of claim 14, wherein forming the first to third auxiliary spacers comprises:
forming first to third auxiliary partition patterns over the auxiliary layer, wherein the first auxiliary partition pattern is arranged between the second auxiliary partition patterns in the first region and the third auxiliary partition patterns are arranged in the second regions;
forming a material layer for the auxiliary spacers between the first and the second auxiliary partition patterns by depositing the material layer for the auxiliary spacers on a surface of the first to third auxiliary partition patterns;
etching the material layer for the auxiliary spacers to expose a top surface of the first to third auxiliary partition patterns; and
removing the first to third auxiliary partition patterns.
the material layer for the auxiliary spacers formed between the first auxiliary partition pattern and the second auxiliary partition pattern becomes the first auxiliary spacer,
the material layer for the auxiliary spacers remaining on sidewalls of the third auxiliary partition patterns become the second auxiliary spacers, and
the material layer for the auxiliary spacers remaining on a sidewall of the second auxiliary partition pattern on one side, adjacent to the third auxiliary partition pattern, becomes the third auxiliary spacers.
21. The method of claim 12, wherein forming the first to third partition patterns comprises:
forming first and second auxiliary partition patterns over the auxiliary layer, wherein the first auxiliary partition patterns are formed in the first region and the second auxiliary partition patterns, spaced apart from one another at intervals narrower than the first auxiliary partition patterns and each formed to have an identical width with the first auxiliary partition pattern, are formed in the second regions;
forming first and second auxiliary spacers over the auxiliary layer, wherein the first auxiliary spacers are formed on sidewalls of the first auxiliary partition patterns and the second auxiliary spacers each having an identical width with the first auxiliary spacer are formed on sidewalls of the second auxiliary partition patterns;
removing the first and the second auxiliary partition patterns;
etching the auxiliary layer exposed between the first and the second auxiliary spacers and the auxiliary overlap pattern; and
removing the first and the second auxiliary spacers and the auxiliary overlap pattern.
22. The method of claim 21, wherein edges on both sides of the auxiliary overlap pattern overlap with a top surface of the first auxiliary spacers formed in a space between the first auxiliary partition patterns.
the auxiliary layer remaining under the auxiliary overlap pattern and the first auxiliary spacers overlapping with the auxiliary overlap pattern becomes the first partition pattern,
the auxiliary layer remaining under the first spacers not overlapping with the auxiliary overlap pattern becomes the second partition patterns, and
the auxiliary layer remaining under the second auxiliary spacers becomes the third partition patterns.
24. The method of claim 21, wherein a width of each of the first and the second auxiliary spacers is ⅓ of a width of each of the first and the second auxiliary partition patterns.
25. The method of claim 21, wherein an interval between the first auxiliary partition pattern and the second auxiliary partition pattern adjacent to each other is 4/3 of a width of each of the second auxiliary partition patterns.
US13/310,943 2010-12-06 2011-12-05 Method of forming semiconductor memory device Active 2032-04-01 US8518831B2 (en)
KR1020100123623A KR20120062385A (en) 2010-12-06 2010-12-06 Method of manufacturing semiconductor memory device
KR10-2010-0123623 2010-12-06
US20120142194A1 true US20120142194A1 (en) 2012-06-07
US8518831B2 US8518831B2 (en) 2013-08-27
ID=46162639
US13/310,943 Active 2032-04-01 US8518831B2 (en) 2010-12-06 2011-12-05 Method of forming semiconductor memory device
US (1) US8518831B2 (en)
KR (1) KR20120062385A (en)
JP2014170912A (en) * 2013-03-01 2014-09-18 Huabang Electronic Co Ltd Patterning method and method of forming memory element
US20140273441A1 (en) * 2013-03-15 2014-09-18 Samsung Electronics Co., Ltd. Method for forming patterns of semiconductor device using sadp process
US8969215B2 (en) 2012-11-20 2015-03-03 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices using double patterning technology
US9378979B2 (en) 2012-11-20 2016-06-28 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices and devices fabricated thereby
US9502285B1 (en) * 2015-06-08 2016-11-22 United Microelectronics Corp. Method of forming trenches
US9536744B1 (en) * 2015-12-17 2017-01-03 International Business Machines Corporation Enabling large feature alignment marks with sidewall image transfer patterning
US20170125256A1 (en) * 2015-10-29 2017-05-04 Samsung Electronics Co., Ltd. Methods of Forming Patterns with Multiple Layers for Semiconductor Devices
US9865815B2 (en) 2015-09-24 2018-01-09 Lam Research Coporation Bromine containing silicon precursors for encapsulation layers
US9875891B2 (en) 2014-11-24 2018-01-23 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US10074543B2 (en) 2016-08-31 2018-09-11 Lam Research Corporation High dry etch rate materials for semiconductor patterning applications
US10134579B2 (en) 2016-11-14 2018-11-20 Lam Research Corporation Method for high modulus ALD SiO2 spacer
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
US10454029B2 (en) 2016-11-11 2019-10-22 Lam Research Corporation Method for reducing the wet etch rate of a sin film without damaging the underlying substrate
KR20160065332A (en) 2014-11-28 2016-06-09 삼성전자주식회사 Method for forming key patterns and method for manufacturing a semiconductor device using the same
US7115525B2 (en) * 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US20090317748A1 (en) * 2008-06-19 2009-12-24 Hynix Semiconductor Inc. Method for Forming Fine Patterns of Semiconductor Device
US7790531B2 (en) * 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US7943481B1 (en) * 2010-08-04 2011-05-17 Hynix Semiconductor Inc. Method of forming fine patterns
US8026179B2 (en) * 2009-04-09 2011-09-27 Macronix International Co., Ltd. Patterning method and integrated circuit structure
US8148247B2 (en) * 2005-08-30 2012-04-03 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
KR100914289B1 (en) 2007-10-26 2009-08-27 주식회사 하이닉스반도체 Method for forming patterns in semiconductor memory device using spacer
2010-12-06 KR KR1020100123623A patent/KR20120062385A/en active IP Right Grant
2011-12-05 US US13/310,943 patent/US8518831B2/en active Active
US9093378B2 (en) * 2013-03-15 2015-07-28 Samsung Electronics Co., Ltd. Method for forming patterns of semiconductor device using SADP process
US10141505B2 (en) 2015-09-24 2018-11-27 Lam Research Corporation Bromine containing silicon precursors for encapsulation layers
US10014181B2 (en) * 2015-10-29 2018-07-03 Samsung Electronics Co., Ltd. Methods of forming patterns with multiple layers for semiconductor devices
US9716184B2 (en) * 2015-12-17 2017-07-25 International Business Machines Corporation Enabling large feature alignment marks with sidewall image transfer patterning
KR20120062385A (en) 2012-06-14
US8518831B2 (en) 2013-08-27
US8213231B2 (en) 2012-07-03 NAND flash memory devices having wiring with integrally-formed contact pads and dummy lines and methods of manufacturing the same
KR101170289B1 (en) 2012-07-31 Semiconductor constructions, methods of forming multiple lines, and methods of forming high density structures and low density structures with a single photomask
US8110506B2 (en) 2012-02-07 Methods of forming fine patterns in semiconductor devices
JP2006351861A (en) 2006-12-28 Manufacturing method of semiconductor device
US8742529B2 (en) 2014-06-03 Semiconductor memory
US7615496B2 (en) 2009-11-10 Method of forming pad patterns using self-align double patterning method, pad pattern layout formed using the same, and method of forming contact holes using self-align double patterning method
JP5703339B2 (en) 2015-04-15 Patterning method and memory element forming method
US8822285B2 (en) 2014-09-02 Nonvolatile memory device and method of manufacturing the same
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US7604926B2 (en) 2009-10-20 Method of manufacturing a semiconductor device
US20080057666A1 (en) 2008-03-06 Method of manufacturing a semiconductor device
US8036036B2 (en) 2011-10-11 Semiconductor device and a manufacturing method thereof
US20060081914A1 (en) 2006-04-20 Semiconductor device and manufacturing method thereof
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JP5561485B2 (en) 2014-07-30 Method and related structure for isolating a portion of a pitch-multiplied material loop
KR101532012B1 (en) 2015-06-30 Semiconductor device and method of forming patterns for semiconductor device
JP2010153869A (en) 2010-07-08 Semiconductor device, and patterning method thereof
JP4271243B2 (en) 2009-06-03 Method for forming integrated circuit pattern
US7994056B2 (en) 2011-08-09 Method for forming pattern in semiconductor device
KR20060051663A (en) 2006-05-19 Semiconductor device
US9099470B2 (en) 2015-08-04 Method of forming patterns for semiconductor device
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