Source: http://www.google.com/patents/US7863657?dq=5,646,839
Timestamp: 2014-03-08 08:51:20
Document Index: 670952576

Matched Legal Cases: ['Application No. 050002849', 'Application No. 06011395', 'Application No. 06011396', 'Application No. 04', 'Application No. 05', 'Application No. 2007', 'Application No. 06', 'Application No. 06', 'Application No. 2004']

Patent US7863657 - Efficient transistor structure - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn integrated circuit comprises a first drain region having a symmetric shape across at least one of horizontal and vertical centerlines. A first gate region has a first shape that surrounds the first drain region. A second drain region has the symmetric shape. A second gate region has the first shape...http://www.google.com/patents/US7863657?utm_source=gb-gplus-sharePatent US7863657 - Efficient transistor structureAdvanced Patent SearchPublication numberUS7863657 B2Publication typeGrantApplication numberUS 11/586,470Publication dateJan 4, 2011Filing dateOct 25, 2006Priority dateOct 22, 2003Also published asUS7528444, US7652338, US7851872, US20070032063, US20070034903, US20070034904, US20070037353Publication number11586470, 586470, US 7863657 B2, US 7863657B2, US-B2-7863657, US7863657 B2, US7863657B2InventorsSehat SutardjaOriginal AssigneeMarvell World Trade Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (58), Non-Patent Citations (13), Classifications (36) External Links: USPTO, USPTO Assignment, EspacenetEfficient transistor structureUS 7863657 B2Abstract An integrated circuit comprises a first drain region having a symmetric shape across at least one of horizontal and vertical centerlines. A first gate region has a first shape that surrounds the first drain region. A second drain region has the symmetric shape. A second gate region has the first shape that surrounds the second drain region. A connecting gate region connects the first and second gate regions. A first source region is arranged adjacent to and on one side of the first gate region, the second gate region and the connecting gate region. A second source region is arranged adjacent to and on one side of side of the first gate region, the second gate region and the connecting gate region.
a first gate region having a first shape surrounding said first drain region;
a second drain region having said symmetric shape;
a second gate region having said first shape surrounding said second drain region;
a connecting gate region connecting said first and second gate regions;
a first source region arranged adjacent to and on one side of said first gate region, said second gate region and said connecting gate region;
a second source region arranged adjacent to and on another side of said first gate region, said second gate region and said connecting gate region opposite said one side; and
first and second substrate contacts arranged in said first and second source regions, respectively.
2. The integrated circuit of claim 1, wherein said symmetric shape tapers as a distance from a center of said symmetric shape increases.
3. The integrated circuit of claim 1, wherein said integrated circuit includes laterally-diffused MOSFET transistors.
4. The integrated circuit of claim 1, wherein said symmetric shape is a circular shape.
5. The integrated circuit of claim 1, wherein said symmetric shape is an elliptical shape.
6. The integrated circuit of claim 1, wherein said symmetric shape is a polygonal shape.
7. The integrated circuit of claim 1, wherein said symmetric shape is a hexagonal shape.
8. The integrated circuit of claim 1, wherein the first and second substrate contacts are aligned with the connecting gate region in a first direction.
9. The integrated circuit of claim 1, further comprising third and fourth substrate contacts arranged in the first and second drain regions, respectively.
a first drain region including a first substrate contact;
a first gate region surrounding the first drain region;
a second drain region including a second substrate contact;
a second gate region surrounding the second drain region;
a connecting gate region connecting the first and second gate regions;
a first source region arranged adjacent to and on a first side of the first gate region, the second gate region and the connecting gate region, the first source region including a third substrate contact; and
a second source region arranged adjacent to and on a second side of the first gate region, the second gate region and the connecting gate region, the second side including a fourth substrate contact and being opposite the first side.
11. The integrated circuit of claim 10, wherein the first and second drain regions surround the first and second substrate contacts, respectively.
12. The integrated circuit of claim 10, wherein the first and second source regions surround the third and fourth substrate contacts, respectively.
13. The integrated circuit of claim 10, wherein the first, second, third, and fourth substrate contacts have one of a rectangle, circle, cross, and diamond shape.
14. The integrated circuit of claim 10, wherein an area of the first substrate contact is greater than 2 nm, wherein n is a total number of substrate contacts located in the first source region, and wherein m is an area of one of the substrate contacts located in the first source region.
15. The integrated circuit of claim 10, wherein the third and fourth substrate contacts are aligned with the connecting gate region in a first direction. Description
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a Continuation of U.S. patent application Ser. No. 11/524,113 filed Sep. 20, 2006, which application claims the benefit of U.S. Provisional Application Nos. 60/825,517, filed Sep. 13, 2006, 60/824,357, filed Sep. 1, 2006, 60/823,332, filed on Aug. 23, 2006, 60/821,008, filed Aug. 1, 2006 and 60/798,568, filed on May 8, 2006 and is a continuation-in-part of U.S. patent application Ser. No. 11/252,010 filed on Oct. 17, 2005, which is a continuation of U.S. patent application Ser. No. 10/691,237 filed on Oct. 22, 2003. The disclosure of the above application is incorporated herein by reference in its entirety.
In other features of the integrated circuit and method, the first, second and third source regions have a length that is substantially equal to a length of the first drain region and wherein the fourth and fifth source regions have a length that is greater than or equal to a length of the first and second drain regions. The first, second and third source regions have a width that is less than a width of the first drain region. The width of the first, second and third source regions is approximately one-half the width of the first drain region. The fourth and fifth source regions are driven from sides thereof. The first and second drain contacts have a size that is greater than a minimum drain contact size. The drain contacts have one of a regular shape and an irregular shape. The drain contacts are one of square, rectangular, and cross-shaped. The first, second and third source regions include source contacts. The first and second drain regions and the first, second and third source regions are arranged in a first row and further comprising N additional rows, wherein drain regions of at least one of the N additional rows share one of the fourth and fifth source regions.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify the same elements. Additional transistors can be arranged on one or more sides of the illustrated transistors that are shown in the FIGs. as indicated by � . . . � in the FIGs.
Substantially all of the current flowing between the drain region 306-3 and the source contacts 311-1, 311-2, . . . and 311-B of the adjacent source region 304-2 flows between a facing portion 335 of the drain contact 334-3 and facing halves 337-1, 337-2, . . . and 337-S of source contacts 311-1, 311-2, . . . and 311-B in the source region 304-2. Current flows in a similar manner between other facing portions of the drain contact 334-3 and source contacts (not shown) in other adjacent source regions 304-5, 304-6 and 304-7.
In some implementations, the substrate contacts 347-11, 347-12, 347-21, 347-22, 347-23, . . . may be arranged in some, none or all of the second areas 345-B1, 345-B2, 345-B3 and 345-B4 of the source regions 344-1, 344-2, . . . and 344-R, for example as shown in FIG. 12D. The substrate contacts 347-11, 347-12, 347-21, 347-22, 347-23, . . . are shown arranged in the elongated substrate regions 344-1 and 344-2 and tend to lower RDS � ON. The substrate contacts 347-11, 347-12, 347-21, 347-22, 347-23, . . . may have a height that is less than or equal to a width �c� of the source regions 304 (as shown in FIG. 12A) and a width that is less than or equal to a width �d� of the source regions 304 (as shown in FIG. 12A).
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