Source: http://www.google.de/patents/US5034340
Timestamp: 2016-10-28 12:15:42
Document Index: 765883605

Matched Legal Cases: ['art 8', 'art 7', 'art 5', 'art 7', 'art 5', 'art 5', 'art 5', 'art 5']

Patent US5034340 - Amorphous silicon thin film transistor array substrate and method for ... - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr »Anmelden PatenteAn amorphous silicon thin film transistor array substrate is formed on an insulating substrate with a gate insulating layer, a gate wiring interconnecting gate electrodes and source wiring interconnecting source electrodes. The gate insulating layer is provided in a lower layer of a terminal part of...http://www.google.de/patents/US5034340?utm_source=gb-gplus-sharePatent US5034340 - Amorphous silicon thin film transistor array substrate and method for producing the same Erweiterte PatentsucheTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents. Ver�ffentlichungsnummerUS5034340 APublikationstypErteilung AnmeldenummerUS 07/371,478 Ver�ffentlichungsdatum23. Juli 1991Eingetragen26. Juni 1989 Priorit�tsdatum26. Febr. 1988Geb�hrenstatusBezahltAuch ver�ffentlicht unterUS5065202 Ver�ffentlichungsnummer07371478, 371478, US 5034340 A, US 5034340A, US-A-5034340, US5034340 A, US5034340A ErfinderSakae Tanaka, Yoshiaki WatanabeUrspr�nglich Bevollm�chtigterSeikosha Co., Ltd.Zitat exportierenBiBTeX, EndNote, RefManPatentzitate (23), Referenziert von (31), Klassifizierungen (18), Juristische Ereignisse (4) Externe Links: USPTO, USPTO-Zuordnung, EspacenetAmorphous silicon thin film transistor array substrate and method for producing the same
US 5034340 A Zusammenfassung
An amorphous silicon thin film transistor array substrate is formed on an insulating substrate with a gate insulating layer, a gate wiring interconnecting gate electrodes and source wiring interconnecting source electrodes. The gate insulating layer is provided in a lower layer of a terminal part of the source wiring. In the process for forming the array, the gate insulating layer is formed in a portion of the structure other than the terminal part of the gate, and the terminal part of the source wiring is formed on the gate insulating layer.
Bilder(7) Anspr�che(2)
1. A method for producing an amorphous silicon thin film transistor array substrate having a plurality of amorphous silicon thin film transistors formed on an insulating substrate, each of said amorphous silicon thin film transistors having a gate electrode formed on said insulating substrate, a gate insulating layer covering said gate electrode, an amorphous silicon layer formed on said gate insulating layer, and source and drain electrodes formed on said amorphous silicon layer, said method comprising:forming gate electrodes on an insulating substrate and simultaneously forming gate wiring on said insulating substrate for connecting said gate electrodes to one another, said gate wiring having a gate terminal adjacent an edge of said insulating substrate for connection to an external circuit, forming a gate insulating layer on substantially the entire surface of said insulating substrate to cover said gate electrodes and said gate wiring but not said gate terminal, forming an amorphous silicon layer on said gate insulating layer, for forming said amorphous silicon thin film transistors, forming source and drain electrodes on said amorphous silicon layer, and forming source wiring for connecting said source electrodes to one another, said source wiring having a source terminal adjacent an edge of said insulating substrate for connection to an external circuit, said source terminal being formed entirely on said gate insulating layer, whereby said source terminal is at substantially the same level as the portion of the source wiring adjacent thereto. 2. In a method for producing an amorphous silicon thin film transistor array substrate having a plurality of amorphous silicon thin film transistors formed on an insulating substrate, each of said amorphous silicon thin film transistors having a gate electrode formed on said insulating substrate, a gate insulating layer covering said gate electrode, an amorphous silicon layer formed on said gate insulating layer, and source and drain electrodes formed on said amorphous silicon layer, wherein said method comprises:forming gate electrodes on an insulating substrate and simultaneously forming gate wiring on said insulating substrate for connecting said gate electrodes to one another, said gate wiring having a gate terminal adjacent an edge of said insulating substrate for connection to an external circuit, forming a gate insulating layer on substantially the entire surface of said insulating substrate, forming an amorphous silicon layer on said gate insulating layer, for forming said amorphous silicon thin film transistors, forming source and drain electrodes on said amorphous silicon layer, and forming source wiring for connecting said source electrodes to one another, said source wiring having a source terminal adjacent an edge of said insulating substrate for connection to an external circuit, the improvement wherein said step of forming a gate insulating layer comprises forming said gate insulating layer except on said gate terminal, and said step of forming said source wiring comprises forming said source terminal entirely on said gate insulating layer, whereby said source terminal is at substantially the same level as the portion of the source wiring adjacent thereto. Beschreibung
This is a division of application Ser. No. 306,364, filed Feb. 3, 1989, now abandoned, and refiled as a file wrapper continuation application Ser. No. 534,003, filed June 4, 1990.
The present invention relates to an amorphous silicon thin film transistor array utilized in an active matrix type liquid crystal display device or the like, and a method for producing the same.
In recent years, a liquid crystal matrix display device, especially a liquid crystal display device of the so-called active matrix type provided with a switching element per each pixel has been under research and development in various places for a thin type picture image display device. An MIS type thin film transistor (hereinafter referred to as TFT) using amorphous silicon (hereinafter referred to as a-Si) has been primarily utilized for the above switching element.
FIG. 8 shows an example of the construction of an active matrix type liquid crystal display device using TFT. In this Figure, when Xi is selected, for example, in the gate wiring 8, the gates of respective TFT 21-a connected thereto are turned on all at once, and through the sources of these TFTs turned on, the signal voltage corresponding to the picture information is transmitted from respective signal lines 12 to the drains of the respective TFT 21-a. A pixel electrode (not shown in the Figure) is connected to the drain, and due to the voltage difference between this pixel electrode and the counter electrode 23 formed on the substrate, which is on the other side, putting the liquid crystal layer 22 therebetween, the optical transparency of the liquid crystal layer 22 is changed to effect picture image display.
When Xi is in a non-selective state, the gate of each TFT 21-a connected thereto is off, and successively, Xi+1 is selected, and the gate of each TFT 21-b connected thereto is turned on, and a process similar to that as described above is effected. Since the voltage difference between both the pixel electrode and the counter electrode 23 is preserved by the liquid crystal layer 22 until the same gate wiring 8 is selected in the next time, the liquid crystal corresponding to each pixel is statically driven, and a display of high contrast can be obtained even after the gate has been turned off.
FIG. 9 is a diagram showing an example of the a-Si TFT used in the above-described TFT 21-a and 21-b. Numeral 1 denotes an insulating substrate such as glass or the like, numeral 2 a gate insulating layer, numeral 3 an amorphous silicon layer, numeral 4 a protective insulating layer, numeral 9 a gate electrode, numeral 12 a source wiring, numeral 13 a pixel electrode, numeral 15 a source electrode, and numeral 16 a drain electrode. As shown in this Figure, a gate electrode 9, a source electrode 15 and a drain electrode 16 are formed putting the gate insulating layer 2 and the amorphous silicon layer 3 therebetween, and the gate electrode 9 is formed on the side nearer to the substrate than the source electrode 15 and drain electrode 16. A TFT having the structure explained above is called a reverse staggered type TFT.
In an active matrix type liquid crystal display device, since the terminal part of the gate wiring should effect the connection to the external circuit at the peripheral part of the substrate, the gate insulating layer 2 or the like must not be formed on the gate wiring terminal part in the peripheral part of the substrate. In usual cases, as shown in FIG. 10, when a gate insulating layer or the like is formed, a metal.. mask 14 is used to mask the peripheral part of the insulating substrate 1 such that a gate insulating layer or the like is not formed at this masked part.
FIG. 11 is a sectional diagram showing the terminal part of the source wiring when the gate insulating layer and the like were formed by the method as shown in FIG. 10. In this Figure, numeral 1 denotes an insulating substrate, numeral 2 a gate insulating layer, numeral 8a a source wiring terminal part, and numeral 8 a source wiring. When a gate insulating layer or the like is formed by using a metal mask as shown in FIG. 10, the gate insulating layer 2 is not formed also in the part of the source wiring terminal part 8a as shown in FIG. 11. Therefore, the source wiring 8 is formed across the interface of the gate insulating layer 2 and the insulating substrate 1, and due to the effect of such difference of the underlying layers or the level difference in the interface part, stress is generated in the neighborhood of the interface of the source wiring 8, and in this case film peeling or wire breaking results, which are serious problems for the yield of the products.
The present invention is therefore directed to a thin film transistor array and method for producing the same, reducing the above-described film peeling or the wire breaking in the neighborhood of the terminal part of the source wiring and improving the production yield.
FIGS. 1(a)-1(d), 2(a)-2(d) and 3(a)-3(d) are sectional diagrams of a process showing the views of the source wiring terminal part, gate wiring terminal part, and transistor part, respectively;
FIG. 4 is a perspective diagram showing the relationship between the metal mask and the insulating substrate used in the execution of the present invention;
FIGS. 5 to 7 are sectional diagrams of the source wiring terminal part used in another Example of the present invention;
FIG. 8 is a circuit diagram showing the construction of the active matrix type liquid crystal display device;
FIG. 9 is a sectional diagram showing an example of the reverse staggered type amorphous silicon thin film transistor;
FIG. 10 is a perspective diagram showing the relationship between the metal mask and the insulating substrate used in the conventional production method; and
FIG. 11 is a sectional diagram of a conventional source wiring terminal part.
In the following, an embodiment of the present invention will be explained by referring to FIGS. 1 to 4. FIGS. 1 to 3 show the source wiring terminal part, gate wiring terminal part, and TFT part formed by the same process respectively, and an explanation will be given of this production process.
FIGS. 1(a), 2(a) and 3 illustrate a gate insulating layer 2 made of silicon nitride, an amorphous silicon layer 3, and a protective insulating layer 4 made of silicon nitride deposited by the plasma CVD method on an insulating substrate 1 made of glass or the like on which a gate electrode 9 (FIG. 3(a)) and a gate wiring 8 (FIG. 2(a)) have been formed. The above-described respective layers are deposited by only masking the gate wiring terminal part by using the metal mask 14a as shown in FIG. 4. Therefore, the above-described respective layers are not deposited on the gate wiring terminal part 7 as shown in FIG. 2(a), but the above-described respective layers are deposited on the source wiring terminal part as shown in FIG. 1(d).
In FIGS. 1(b), 2(b) and 3, the protective insulating layer 4 is etched with a buffer fluoric acid solution leaving the TFT part except the other part.
In FIGS. 1(c), 2(c) and 3, with the object of forming ohmic contact with the amorphous silicon layer 3, a silicon layer 10 (FIG. 3(c)) containing n-type impurities (hereinafter referred to as n-type silicon layer) is deposited by the plasma CVD method, and then, a metal layer 11 (FIG. 3(c)) is deposited by the vacuum vapor deposition method. The metal layer 11 is patterned into the shapes of a source electrode and a drain electrode, and by making this patterned metal layer 11 and the protective insulating layer 4 as the mask, the amorphous silicon layer 3 and n-type silicon layer 10 are etched by using an organic alkaline solution.
In FIGS. 1(d), 2(d) and 3, a transparent electric conductive layer 6 (FIG. 3(d)) is deposited by the vacuum vapor deposition method, and this is selectively etched by using a ferric chloride solution to form the source wiring 12 (FIG. 3(d)) and the pixel electrode 13 (FIG. 3(d)). At this time, the source wiring terminal part 5 is formed on the gate insulating layer 2 as shown in FIG. 1(d).
In the a-Si TFT array substrate formed in such a manner as described above, since the gate insulating layer 2 and the like are formed by using a metal mask 14a as shown in FIG. 4, the gate wiring terminal part 7 has an exposed surface as shown in FIG. 2(d), and the source wiring terminal part 5 is formed flat on the gate insulating layer 2 as shown in FIG. 1(d).
FIGS. 5 to 7 are sectional diagrams showing the construction of a source terminal part in the other Example of the present invention. In these Figures, numeral 1 denotes an insulating substrate, numeral 2 a gate insulating layer, numeral 3 an a-Si layer, numeral 5 a source wiring terminal part, numeral 6 a transparent conductive layer, numeral 10 an n-type silicon layer, and numeral 11 a metal layer. The Example in FIG. 5 shows the source wiring terminal part 5 formed of a transparent conductive layer 6 and a metal layer 11.
The Example in FIG. 6 shows the source wiring terminal part 5 formed of a transparent conductive layer 6, a metal layer 11 and an n-type silicon layer 10.
The Example in FIG. 7 shows the source wiring terminal part formed of a transparent conductive layer 6, a metal layer 11, an n-type silicon layer 10, and an a-Si layer 3.
In each of the above-described Examples, since the metal mask 14a as shown in FIG. 4 is used in forming the gate insulating layer 2, the source wiring terminal part 5 is formed flat on the gate insulating layer 2.
As can be clearly apparent from the above explanation, in the present invention, since the gate wiring terminal part is masked and the source wiring part is not masked in forming the gate insulating layer, it is possible to form the source wiring part flat on the gate insulating layer with the gate wiring part left exposed in the same manner as in the conventional case. Also, the above-described production can be achieved by only changing the shape of the metal mask.
According to the present invention, since the source wiring terminal part is formed on the gate insulating layer, film peeling, wire breaking and the like near the source wiring part are reduced to a large extent, and an improvement of production yield to a large extent ca be expected.
Moreover, in forming the gate insulating layer, since the gate wiring terminal part only is masked and the source wiring part is not masked, the number of the production processes is not changed in any way from the conventional one, so that there is no increase in the number of processes.
Patentzitate Zitiertes PatentEingetragen Ver�ffentlichungsdatum Antragsteller TitelUS3885196 *28. Nov. 197320. Mai 1975Us ArmyPocketable direct current electroluminescent display device addressed by MOS or MNOS circuitryUS4368467 *20. Febr. 198111. Jan. 1983Fujitsu LimitedDisplay deviceUS4582395 *30. Juli 198115. Apr. 1986Kabushiki Kaisha Suwa SeikoshaActive matrix assembly for a liquid crystal display device including an insulated-gate-transistorUS4623908 *31. M�rz 198318. Nov. 1986Seiko Epson Kabushiki KaishaThin film transistorsUS4651185 *15. Apr. 198517. M�rz 1987Alphasil, Inc.Method of manufacturing thin film transistors and transistors made therebyUS4704002 *29. Dez. 19863. Nov. 1987Matsushita Electric Industrial Co., Ltd.Dot matrix display panel with a thin film transistor and method of manufacturing sameUS4720736 *22. Jan. 198619. Jan. 1988Sharp Kabushiki KaishaAmorphous silicon thin film transistorUS4723838 *4. Dez. 19859. Febr. 1988Hosiden Electronics Co., Ltd.Liquid crystal display deviceUS4778560 *3. Juni 198718. Okt. 1988Matsushita Electric Industrial Co., Ltd.Method for production of thin film transistor array substratesUS4779086 *29. Aug. 198618. Okt. 1988Canon Kabushiki KaishaLiquid crystal device and method of driving sameUS4786780 *26. Febr. 198822. Nov. 1988Alps Electric Co., Ltd.Method for trimming thin-film transistor arrayUS4803536 *24. Okt. 19867. Febr. 1989Xerox CorporationElectrostatic discharge protection network for large area transducer arraysUS4804953 *16. Sept. 198714. Febr. 1989General Electric CompanyRedundant conductor structures for thin film FET driven liquid crystal displaysUS4810061 *25. M�rz 19887. M�rz 1989Alps Electric Co., Ltd.Liquid crystal element having conductive wiring part extending from top of transistor light shield to edgeUS4823180 *28. Okt. 198218. Apr. 1989Siemens AktiengesellschaftPhoto-transistor in MOS thin-film technology and method for production and operation thereofUS4853755 *17. M�rz 19881. Aug. 1989Alps Electric Co., Ltd.Method for manufacturing a thin-film transistor array and a thin-film transistor array manufactured by the methodUS4890097 *21. Jan. 198826. Dez. 1989Matsushita Electric Industrial Co., Ltd.Active matrix circuit for liquid crystal displaysJPS631072A * Titel nicht verf�gbarJPS6092663A * Titel nicht verf�gbarJPS6151878A * Titel nicht verf�gbarJPS6347979A * Titel nicht verf�gbarJPS60105275A * Titel nicht verf�gbarJPS62122171A * Titel nicht verf�gbar* Vom Pr�fer zitiert Referenziert von Zitiert von PatentEingetragen Ver�ffentlichungsdatum Antragsteller TitelUS5236850 *18. Sept. 199117. Aug. 1993Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing a semiconductor film and a semiconductor device by sputtering in a hydrogen atmosphere and crystallizingUS5274602 *22. Okt. 199128. Dez. 1993Florida Atlantic UniversityLarge capacity solid-state memoryUS5332686 *29. Sept. 199326. Juli 1994Florida Atlantic UniversityMethod of manufacturing large capacity solid-state memoryUS5409851 *4. Mai 199325. Apr. 1995Goldstar Co., Ltd.Method of making a thin film transistorUS5436495 *1. M�rz 199425. Juli 1995Nec CorporationDevice isolation area structure in semiconductor deviceUS5573958 *14. Nov. 199412. Nov. 1996Frontec IncorporatedMethod of fabricating a thin film transistor wherein the gate terminal is formed after the gate insulatorUS5598011 *23. Jan. 199528. Jan. 1997Goldstar Co., Ltd.Thin film transistor and method of making the sameUS5672523 *26. Mai 199530. Sept. 1997Hitachi, Ltd.Thin film transistor substrate, manufacturing method thereof, liquid crystal display panel and liquid crystal display equipmentUS5889573 *12. Sept. 199730. M�rz 1999Hitachi, Ltd.Thin film transistor substrate, manufacturing method thereof, liquid crystal display panel and liquid crystal display equipmentUS617730222. Sept. 199423. Jan. 2001Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing a thin film transistor using multiple sputtering chambersUS62618772. Juli 199617. Juli 2001Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing gate insulated field effect transistorsUS656617511. Juni 200120. Mai 2003Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing gate insulated field effect transistorsUS687297420. Nov. 200229. M�rz 2005International Business Machines CorporationLow threshold voltage instability amorphous silicon field effect transistor structure and biasing for active matrix organic light-emitting diodesUS6876405 *25. Juli 20035. Apr. 2005Samsung Electronics Co., Ltd.Method for manufacturing a liquid crystal display with a novel structure of thin film transistor substrateUS69798406. Apr. 199427. Dez. 2005Semiconductor Energy Laboratory Co., Ltd.Thin film transistors having anodized metal film between the gate wiring and drain wiringUS713000311. Mai 200531. Okt. 2006Samsung Electronics Co., Ltd.Thin film transistor array substrate for a liquid crystal display and the method for fabricating the sameUS750761531. M�rz 200324. M�rz 2009Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing gate insulated field effect transistorsUS7511782 *29. M�rz 200531. M�rz 2009Lg Display Co., Ltd.Liquid crystal display device and fabrication method having open gate/data pads with transparent conductive layer thereon to an edge thereofUS764258418. Aug. 20055. Jan. 2010Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the sameUS802687321. Dez. 200727. Sept. 2011Global Oled Technology LlcElectroluminescent display compensated analog transistor drive signalUS81940634. M�rz 20095. Juni 2012Global Oled Technology LlcElectroluminescent display compensated drive signalUS82179283. M�rz 200910. Juli 2012Global Oled Technology LlcElectroluminescent subpixel compensated drive signalUS20030094616 *20. Nov. 200222. Mai 2003International Business Machines CorporationLow threshold voltage instability amorphous silicon field effect transistor structure and biasing for active matrix organic light-emitting diodesUS20030170939 *31. M�rz 200311. Sept. 2003Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing gate insulated field effects transistorsUS20050208711 *11. Mai 200522. Sept. 2005Woon-Yong ParkThin film transistor array substrate for a liquid crystal display and the method for fabricating the sameUS20050219433 *29. M�rz 20056. Okt. 2005Oh Kwang SLiquid crystal display device and method for fabricating the sameUS20060060852 *18. Aug. 200523. M�rz 2006Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the sameUS20090160740 *21. Dez. 200725. Juni 2009Leon Felipe AElectroluminescent display compensated analog transistor drive signalUS20100225630 *3. M�rz 20099. Sept. 2010Levey Charles IElectroluminescent subpixel compensated drive signalUS20100225634 *4. M�rz 20099. Sept. 2010Levey Charles IElectroluminescent display compensated drive signalWO2003050892A1 *20. Nov. 200219. Juni 2003International Business Machines CorporationActive matrix organic light-emitting-diodes with amorphous silicon transistors* Vom Pr�fer zitiertKlassifizierungen US-Klassifikation438/158, 257/57, 257/E29.291Internationale KlassifikationH01L21/84, H01L29/786, H01L29/78, H01L27/12, H01L21/336, H01L23/52, H01L21/31, H01L21/3205, G02F1/136, G02F1/1368, H01L21/77 UnternehmensklassifikationH01L29/78669, H01L27/1214 Europ�ische KlassifikationH01L27/12T, H01L29/786E4B4Juristische Ereignisse DatumCodeEreignisBeschreibung9. Jan. 1995FPAYFee paymentYear of fee payment: 46. M�rz 1997ASAssignmentOwner name: SEIKO PRECISION INC., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEIKOSHA CO., LTD.;REEL/FRAME:008447/0737Effective date: 1997021711. Jan. 1999FPAYFee paymentYear of fee payment: 818. Dez. 2002FPAYFee paymentYear of fee payment: 12DrehenOriginalbildGoogle-Startseite - Sitemap - USPTO-Bulk-Downloads - Datenschutzerkl�rung - Nutzungsbedingungen - �ber Google Patente - Feedback gebenDaten bereitgestellt von IFI CLAIMS Patent Services.