Source: http://www.google.com/patents/US4833542?ie=ISO-8859-1&dq=3140553
Timestamp: 2015-01-29 05:02:50
Document Index: 525553372

Matched Legal Cases: ['arts 2', 'arts 2', 'arts 2', 'arts 2', 'arts 2', 'arts 2', 'arts 2', 'arts 2']

Patent US4833542 - Large screen display apparatus having modular structure - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA large screen display apparatus comprising a display unit composed of a plurality of modules and a housing accommodating the display unit. Each of the modules includes a plurality of units arranged in a matrix form, a power source and a control unit. Further, each of the units includes a plurality of...http://www.google.com/patents/US4833542?utm_source=gb-gplus-sharePatent US4833542 - Large screen display apparatus having modular structureAdvanced Patent SearchPublication numberUS4833542 APublication typeGrantApplication numberUS 07/073,661Publication dateMay 23, 1989Filing dateJul 15, 1987Priority dateJul 15, 1986Fee statusPaidAlso published asCA1290800C, CA1298607C2, DE3785972D1, DE3785972T2, EP0253379A2, EP0253379A3, EP0253379B1, US4901155Publication number07073661, 073661, US 4833542 A, US 4833542A, US-A-4833542, US4833542 A, US4833542AInventorsZenichiro Hara, Toshiji TanakaOriginal AssigneeMitsubishi Denki Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Non-Patent Citations (6), Referenced by (69), Classifications (23), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetLarge screen display apparatus having modular structureUS 4833542 AAbstract A large screen display apparatus comprising a display unit composed of a plurality of modules and a housing accommodating the display unit. Each of the modules includes a plurality of units arranged in a matrix form, a power source and a control unit. Further, each of the units includes a plurality of light emitting elements arranged in a matrix form and a drive circuit for the light emitting elements. Due to this arrangement, it is possible to provide a large screen display apparatus being economical, small in weight and volume and high in usability.
What is claimed is: 1. A large screen display apparatus, comprising:a drive circuit (2) for providing drive signals; a display means (30) comprising a plurality of modules (4), each of said modules including a plurality of units (3) arranged in a matrix form of p columns�q lines (where p and q are positive integers), a power source (13) for providing power to each module and a control circuit (31) responsive to said drive signals for controlling said units, each of said units including a plurality of light emitting elements (1) with each of said light emitting elements having a plurality of light emitting parts (2) arranged in a matrix form of k column �1 lines (where k and 1 are positive integers), and said light emitting elements being arranged in a matrix form of m columns�n lines (where m and n are positive integers) to form said unit; and a housing means accomodating said display means and said drive circuit 2. A large screen display apparatus as claimed in claim 1, wherein:k=2r, and l=2s (where r and s are positive integers); and m=2t, and n=2u (where t and u are positive integers); and p=2v, and q=2w (where v and w are positive integers). 3. A large screen display apparatus as claimed in claim 2, wherein control electrodes of said light emitting elements for controlling said light emitting parts comprise first control electrode groups connected together in a vertical direction and second control electrode groups connected together in a horizontal direction, and said light emitting parts are arranged at the intersections of said first and second electrode groups.
4. A large screen display apparatus as claimed in claim 3, wherein said light emitting parts of each light emitting element are three kinds of light emitting parts which are adapted to emit red (R), green (G) and blue (B) light, respectively, and in each light emitting element said light emitting parts are provided in a ratio of R:G:B=1:2:1.
5. A large screen display apparatus as claimed in claim 2, wherein said modules are arranged to form module groups in which signal input sections of said modules are connected with a common signal line, and said module groups thus formed are arranged to form said display means.
6. A large screen display apparatus as claimed in claim 5, wherein said housing means incorporates signal supplying means which receives a signal, converts said signal into a predetermined digital signal, and supplies said digital signal to said common signal lines of said module groups.
7. A large screen display apparatus as claimed in claim 2, wherein said housing incorporates power distributing means for receiving electric power from said power source and distributing said electric power to said modules.
8. A large screen display apparatus as claimed in claim 1, wherein control electrodes of said light emitting elements for controlling said light emitting parts comprise first control electrode groups connected together in a vertical direction and second control electrode groups connected together in a horizontal direction, and said light emitting parts are arranged at the intersections of said first and second electrode groups.
9. A large screen display apparatus as claimed in claim 8, wherein said light emitting parts of each light emitting element are three kinds of light emitting parts which are adapted to emit red (R), green (G) and blue (B) light, respectively, and in each light emitting element said light emitting parts are provided in a ratio of R:G:B:=1:2:1.
10. A large screen display apparatus as claimed in claim 1, wherein said modules are arranged to form a module group in which signal input sections of said modules are connected with a common signal line, and said module groups thus formed are arranged to form said display means.
11. A large screen display apparatus as claimed in claim 18, wherein said housing means incorporates signal supplying means which receives a signal, converts said signal into a predetermined digital signal, and supplies said digital signal to said common signal lines of said module groups.
12. A large screen display apparatus as claimed in claim 1, wherein said housing means incorporates power distributing means (33) for receiving electric power from said power source and distributing said electric power to said modules.
13. A large screen display apparatus as claimed in claim 1, wherein said modules which are assigned by addresses, respectively, are arranged two-dimensionally, and wherein said modules are provided with signal input means, respectively, which are connected with common signal lines, said modules receiving respective display data transmitted through said common signal lines, according to address data transmitted through said common signal lines.
14. A large screen display apparatus as claimed in claim 13, wherein:each of said common signal lines comprises a data signal line and two kinds of timing signal lines, said display data and said address data being transmitted through said data signal line in a time-division multiplex mode, a timing signal for receiving said address data being transmitted through one of said two kinds of timing signal lines, and a timing signal for receiving said display data being transmitted through the other timing signal line; and each of said modules separates said display data and said address data from one another, according to said two timing signals. Description
In general, in a large screen display apparatus of this type, a display section is made up of a number of signal picture element light emitting elements which are CRTs or light bulbs. In a color display apparatus, three kinds of single picture element light emitting elements; i.e., red (R), green (G) and blue (B) single picture elements are arranged regularly, or a number or single picture element light emitting elements including three colors, red, green and blue, are arranged in matrix form. More specifically, the display apparatus comprises a number of units including a plurality of light emitting elements and an electronic circuit for driving them, and is provided with a control device for controlling the display operation and a power source.
FIG. 3 is a block diagram showing the entire arrangement of a display apparatus according to the invention. In FIG. 3, reference numeral 1 designates light emitting elements each comprising light emitting parts 2 arranged in a matrix form of k (vertically)�1 (horizontally) {k and 1 being positive integers (k=4 and 1=4 in FIG. 3)}. Further in FIG. 3, reference numeral 3 designates units each comprising the light emitting elements 1 arranged in a matrix form of m (vertically)�n (horizontally) {m and n being positive integers (m=4 and n=4 in FIG. 4)}. Reference numeral 4 designates a module comprising the units 3 arranged in a matrix form of p (vertically)�q (horizontally) p and q being positive integers (p=2 and q=2 in FIG. 3). Reference numeral 5 designates module groups each comprising the modules 4 arranged vertically; 6, a housing; and 30, a screen formed by arranging the module groups 5 horizontally in the housing 6. The light emitting elements 1 are dot matrix type display elements such as liquid crystal elements or fluorescent display tubes. The display is controlled by controlling two kinds of electrodes, namely, first and second electrodes which are crossed by one another.
FIG. 5 is a diagram for a description of the arrangement of the control electrodes adapted to control a display operation. The grids 8 are connected in four lines Y1 through Y4, and the anodes 7 are connected in four columns X1 through X4 ; that is, the grids 8 and the anodes 7 are arranged in matrix form so that the display operations of the light emitting parts at the intersections of the first and second control electrodes are controlled. When it is required to form a full-color display apparatus, the light emitting elements should be such that three kinds of fluorescent materials, i.e, red, green and blue fluorescent materials are applied, in a regular pattern, to the anodes. If the R, G and B light emitting parts 2 are arranged in the ratio of R:G:B=1:2:1 and the arrangement of picture elements as shown in FIG. 3 is employed, then a color display apparatus high in resolution can be obtained.
Each of the modules 4, as shown in FIG. 6, comprises: a plurality of units 3; a control circuit 31 for controlling the units 3; and a power source 13. Referring back to FIG. 1, in the conventional display apparatus, the display control section 29 and the power source 13 are provided outside of the screen 6, and are so designed as to be able to control a variety of screens different in size, and the circuitry is accordingly, intricate. On the other hand, in the display apparatus of the invention, the control circuits 31 are provided for the modules 4, respectively; that is, the control range of each control circuit 31 is limited to its own module, and therefore the control circuits 31 are simplified in circuitry as much. Especially when the number (k�1) of light emitting parts 2 in each light emitting element 1, the number (m�n) of light emitting elements in each unit 3. As the number (p�q) of units 3 in each module 4 are so determined as to meet k=2r, 1=2s, m=2t, n=2u, p=2v, and q=qw (where r and s are positive integers, and t, u, v and w are integers which are not negative); that is, these numbers are so selected as to be effective in processing digital signals, then control circuits 31 can be efficiently formed.
As shown in FIG. 7, the control circuits 31 together with the power sources 13 are positioned behind the units forming the modules 4, and are connected vertically with the signal lines 14. The signal supplying means 20 for supplying signals to the signal lines 14, and power distributing means 33 for supplying power to the power sources 13 are accommodated in the frame 6 of the screen 30, which makes the display apparatus compact in construction.
Now, the operation of the display apparatus thus constructed will be described. A video signal sampled at high speed is applied to the signal supplying means 20, in which it is converted into a digital signal by the A/D converter 26, which is stored in the buffer memories 21 provided respectively for the module groups 5. The signals written in the buffer memories 21 at high speed are read out, as display data, at low speed, and are delivered to the module groups 5 together with address data for specifying the modules 4 to which the display data should be transmitted, and timing signals for determining the timing of reception of the display data and the address data. In each module group 5, the display data multiplex with the address data in time sharing manner are received by the buffer 24 and transmitted through the signal line 14 to the modules 4. In this case, the display data received by the buffer 24 is made low in speed being subjected to speed conversion by the buffer memory 21 as was described above, and therefore a flat cable can be used as the common signal line 14. The common signal line 14 is made up of a data signal line and two kinds of timing signal lines. The upper part of FIG. 9 shows the address data and the display data which are transmitted in a time-division multiplex mode, the middle part shows a timing signal (hereinafter referred to as "an ALE signal", when applicable) for determining the timing of reception of the address data transmitted through one of the timing signal lines, and the lower part shows a timing signal (hereinafter referred to as "a DWT signal", when applicable) for determining the timing of reception of the display data transmitted through the other timing signal line.
In each of the modules 4, the data and the timing signals transmitted through the signal line 14 are received by the control circuit 31. In the control circuit 31, the address latch section 40 separates the address data according to the ALE signal, and the address data thus separated is supplied to the comparator 41. In the comparator 41, the address data is compared with the address set for the modulate 4 by the address setting switch 33. Only when the address data coincides with the address set by the switch 33, the gate 45 is opened. When the gate 45 is opened, the DWT signal is supplied through the gate 45 to the frame memory 15, so that a series of display data following the address data are written in the frame memory 15. In the address counter 42, the content there of is increased by the DWT signal, so that the display data writing address in the frame memory 15 is renewed and applied to the address selector 43.
The display data thus received and written in the frame memory 15 are read out a required number of times within a predetermined period of time and converted into on-off signals under the control of the address control section 18. The on-off signals thus formed are supplied through the unit selecting gate 19 to the units 3. In each unit 3, the display control is carried out in such a manner that the display data are arranged for the picture elements with the aid of the shift registers. Thus, in each light emitting element, the light emitting parts 2 emit light beams with predetermined luminances.
FIG. 12 is a time chart showing signals applied to the light emitting element 1, which is the fluorescent display tube in this case. Scanning signals different in timing are applied to four grids 8 as indicated by Y1 through Y4 in FIG. 12, and predetermined video signals are applied to the anodes 7 in synchronization with the scanning signals as indicated by X1 through X4, so that the light emitting parts 2 at the intersections are caused to emit light. In the matrix type light emitting element 1 as described above, it is impossible to control the light emitting parts 2 separately; that is, the light emitting parts 2 are controlled in time division manner separately according to the lines, i.e., separately according to the scanning lines, and therefore the display is made continuous by increasing the scanning speed. Half-tones are displayed by a method in which signals proportional in time width to the amplitudes of the video signals are applied to the anodes 7 thereby to vary the luminances of the light emitting parts 2.
FIG. 13 is a diagram showing the arrangement of the display section. In the display section, the picture elements are arranged in a matrix form of 2a (vertically)�2b (horizontally).
FIG. 14 is a diagram showing essential circuit elements for reading data out of the frame memory 15 in FIG. 1, i.e., FIG. 14 shows components required essentially for display control. In this case, it is assumed that a reading address has been selected for the frame memory 15, and therefore the address selector 43 is not shown in FIG. 14. In the frame memory 15, the addresses are specified by (a+b) signals lines arranged vertically and horizontally in correspondence to the number (2a �2b) of picture elements in the display section. In the embodiment, a=5, and b=5, and the address are specified with 10 bits; A0 through A9. In addition, the data are inputted with c bits, which means that a half-tone image having 2c gradations can be displayed. In the embodiment, c=6 is selected. In FIG. 14, reference numeral 16 designates an on-off decision section adapted to subject 6-bit data to comparison; 17, a timing control section for controlling the generation of clock signals; and 18, an address control section made up of a series of counters for frequency-dividing a clock signal to provide an output of (a+b+c) bits corresponding to the number of picture elements 2a �2b and the number of display gradations 2c. The output bits of an address counter 42 are represented by x0 through x4, y2 through y4, y0, y1, and c0 through c5 beginning with the least significant bit. These bits x0 through x4, and y0 through y4 represent the addresses in the frame memory 15, and correspond to the arrangement of the picture elements in the display section as shown in FIG. 13. The display section, as shown in FIG. 13, is made up of four units 3 each of which comprises sixteen (16) light emitting elements 1. In each unit 3, the light emitting elements 1 are controlled by a drive circuit provided on the same substrate.
FIG. 15 shows a part of the control circuit 31 for the units 3. The circuit shown in FIG. 15 is provided for each of the units 3. In the control circuit 31, it is necessary to send data to the units individually; however, data, a latch signal, and scanning signals are supplied to the units commonly, and clock signals CK1 through CK4 for arranging the data are applied to the units, respectively, so that each of the units receives the respective data with the aid of the clock signal applied thereto.
The operation of the control circuit 31 will be described in more detail. The output of the address control section 18 corresponds to an address in the frame memory 15. The data read is compared with the data (c0 -c5) of the on-off decision section 16 which is the output of the address control section 18. As a result of the comparison, 1-bit on-off data is provided which is "1" (corresponding to the "on" state of a picture element) when the data of the frame memory 15 is larger and "0" (corresponding to the "off" state) when the data is smaller. The data thus provided is applied to the respective picture element in the respective unit with the aid of the respective clock signal described above. On the other hand, as the clock signal is counted, the address control section 18 renews the address so that data are read out of the frame memory 15 successively. This operation is carried out repeatedly. In the circuit of FIG. 14, the data of the lines Y1 are converted into on-off data, which are applied to the shift registers. The on-off data thus applied are simultaneously latched and held for a predetermined period of time thereby to drive the corresponding X electrodes (second control electrodes). At the same time, the scanning electrodes (control electrodes) Y1 are driven for light emission (the Y electrodes being hereinafter referred to as "first control electrodes", when applicable). As the clock signals are further counted, the address control section 18 carries out the same operation for the line Y2, Y3 and Y4 repeatedly so that display of an on-off binary image forming one picture is accomplished. The timing in this operation is as shown in FIG. 12. In the case of FIG. 14, the on-off decision data, 6 bits (c0 -c5), are allotted to six high-order bits of the output of the address control section 18. This means that, during one cyclic operation of the address control section, the binary image display is repeated sixty-four times with the output (c0 -c5) changing form (0--0) over to (1--1) as shown in FIG. 16, a time chart. In FIG. 16, reference characters T1 through T64 designate the periods of time in which the output (c0 -c5) of the on-off decision section 16 is (0--0), (0--1), . . . and (1--1), respectively. More specifically, in the period of time T1, the data of the frame memory 15 is compared with the comparison data ((c0 -c5)-(0--0)) of the on-off decision section 16, as a result of which on-off data are provided and displaced as a binary image. In each of the remaining periods of time T2 through T64, the comparison data is increased by one "1", and with respect to the comparison data thus increased, the content of the frame memory 15 is converted into on-off data which are displayed as a binary image similarly as in the case of the period of time T1. As was described above, during one cyclical operation of the address control section 18, the data in the frame memory 15 are read sixty-four times and compared with the sixty-four different binary data ranged from (0--0) to (1--1), so that sixty-four binary images are displaced. Therefore, in the display during one cyclical operation of the address control section 18, the sum of the periods of time in which the picture elements are placed in "on" state is proportional to the contents of the memory, and half-tone images having sixty-four gradations can be displayed. On the other hand, in a television signal according to the NTSC system, one field of picture is switched every 1/60 sec. Accordingly, in displaying a television signal as an image, data corresponding to one field are rewritten in the frame memory every 1/60 sec. Therefore, selecting the clock frequency so as to allow the address control section 18 to achieve its one cyclical operation in 1/60 sec. permits the display of a television signal with sixty-four gradation. In the PAL system, one field corresponds to 1/50 sec., and therefore the clock frequency is 5/6 of that in the NTSC system.
The embodiment of the invention has been described with reference to the case where the display elements are operated on 1/4 duty dynamic drive for display control. However, the invention, being based on the relationships between the number of picture elements in the display section, the number of gradations of a half-tone image, and the number of outputs of the address control section 18, is effective irrespective of the display element drive system. The output of the address control section 18 may be allotted to the address or comparison data (c0 -c5) in various methods. FIGS. 17(a), (b) and (c) are examples of these methods. The part (a) of FIG. 17 is provided for FIG. 14, with the timing as indicated in FIG. 16. As the lines specified by y0 and y1 are scanned simultaneously, y0 and y1 are allotted to the high-order bits of the output of the counter. The part (b) of FIG. 17 shows the allotment in the case where the display is controlled on 1/8 duty dynamic drive. In this operation, the timing is as indicated in FIG. 18. In this case, half-tone images are obtained by overlapping sixty-four different binary images. In the case of the part (c) of FIG. 17, similarly as in the case of FIG. 14, the display is controlled on 1/4 duty dynamic drive and y0 and y1 are allotted to the most significant bits. In this case, the data are read sixty-four times for every scanning-line drive period, and the time width conversion is carried out for every scanning line, so that a display having sixty-four gradations is carried out with one scanning operation with the timing as shown in FIG. 19.
Further, each module 4 includes the control circuit 31 which is an essential signal processing element for a display operation, and the power source. If, under this condition, the signal supplying means 20 including the A/D converter 26 and the buffer memory 21, and the power distributing means 33 which receives electric power and distributes it to the modules are arranged inside the housing 6 of the screen 6, then all the necessary components are provided in the screen housing; that is, the resultant display apparatus is compact in construction. In the display apparatus of the invention, a plurality of light emitting elements each having a plurality of picture elements, in which a plurality of light emitting parts are arranged in matrix form are employed. The light emitting elements are arranged i a matrix form of m�n, to form a unit and a plurality of the units are arranged in a matrix form of p�q (where m, n, p and q are positive integers) to form a module. A plurality of the modules are arranged to form the screen. Therefore, the functions of the display apparatus can be distributed to the light emitting elements, units and modules effectively. Furthermore, the light emitting elements are much lower in cost than the single picture element light emitting elements, the number of which is equal to that of the light emitting parts thereof. Therefore, according to the invention, a large screen display apparatus high in resolution can be realized without increasing the manufacturing cost, the weight and the thickness thereof.
The modules with the frame memories may be two-dimensionally arranged to form the large screen. In such a display apparatus, the addresses are assigned to the modules, respectively, and the modules are connected with the common signal lines so that the display data and the address data are supplied to the modules through the common signal lines. According to the address data, the display data for the modules are selected and stored in the frame memories, and the display data thus stored are used for display control. That is, each module carries out its own display control. Thus, in the display apparatus of the invention, the display control is performed with high efficiency. Accordingly, the display apparatus of the invention can readily cope with an increase in the quantity of data which may be caused when the screen size is increased or the resolution is increased. Furthermore, in the display apparatus of the invention, the picture elements are arranged in a matrix form of 2a (vertically)� 2b (horizontally) (where a and b are positive integers) in the display section; i.e., the number of picture elements is so limited as to be convenient in processing digital signals. Therefore in the display apparatus, the output of the address control section comprising a series of binary counters can be used as the control signal, and the simple circuit can effectively achieve the half-tone control while the address control section performs its one cyclical operation. If the invention is practiced as module control circuit, then the module control circuit itself is simplified, and 1-bit data arrangement may be employed for the units. In addition, the units can be simplified in construction. Therefore, the large screen display apparatus can be reduced greatly in manufacturing cost and made compact in construction according to the invention.
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examinerClassifications U.S. Classification348/383, 345/75.1, 348/803, 348/E03.012, 345/903, 348/791International ClassificationG09G3/20, H04N3/12, G09G3/22, H04N9/31, G06F3/14Cooperative ClassificationG09F9/3026, Y10S345/903, G09G3/22, G09G2360/18, G09G2300/0452, H04N3/12, G09G3/2092, G09G3/20, G06F3/1446European ClassificationH04N3/12, G09G3/20T, G06F3/14C6Legal EventsDateCodeEventDescriptionOct 30, 2000FPAYFee paymentYear of fee payment: 12Sep 30, 1996FPAYFee paymentYear of fee payment: 8May 3, 1994DPNotification of acceptance of delayed payment of maintenance feeFeb 15, 1994FPAYFee paymentYear of fee payment: 4Feb 15, 1994SULPSurcharge for late paymentAug 10, 1993FPExpired due to failure to pay maintenance feeEffective date: 19930523May 23, 1993REINReinstatement after maintenance fee payment confirmedMay 18, 1988ASAssignmentOwner name: MITSUBISHI DENKI KABUSHIKI KAISHA,NO. 2-3, MARUNOUFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:HARA, ZENICHIRO;TANAKA, TOSHIJI;REEL/FRAME:004890/0699Effective date: 19870824Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HARA, ZENICHIRO;TANAKA, TOSHIJI;REEL/FRAME:004890/0699RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services