Source: http://www.google.com/patents/US8077511?dq=inventor:%22Arthur+R.+Hair%22
Timestamp: 2014-03-15 01:34:26
Document Index: 232251139

Matched Legal Cases: ['Application No. 03820492', 'Application No. 03763311', 'Application No. 03763311', 'Application No. 03763311', 'Application No. 2004', 'Application No. 092118353']

Patent US8077511 - Hybrid non-volatile memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to...http://www.google.com/patents/US8077511?utm_source=gb-gplus-sharePatent US8077511 - Hybrid non-volatile memoryAdvanced Patent SearchPublication numberUS8077511 B2Publication typeGrantApplication numberUS 11/829,370Publication dateDec 13, 2011Filing dateJul 27, 2007Priority dateApr 21, 2004Also published asUS7283390, US20060023550, US20080205150Publication number11829370, 829370, US 8077511 B2, US 8077511B2, US-B2-8077511, US8077511 B2, US8077511B2InventorsAlberto PesaventoOriginal AssigneeSynopsys, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (109), Non-Patent Citations (70), Classifications (19), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetHybrid non-volatile memoryUS 8077511 B2Abstract A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that provide an ON/OFF state output, and the like. Some of the outputs are used to calibrate circuits within a device following power-on. Other outputs are used to store information to be employed by various circuits.
1. A hybrid Non-Volatile Memory (NVM) device, comprising:
a first circuit of a first type NVM cell for storing data for a first operational component;
a second circuit of a second type NVM cell that is different from the first type NVM cell, wherein the second circuit is for storing data for a second operational component distinct from the first operational component, and wherein the second circuit is distinct from the first operational component; and
support circuitry, wherein a portion of the support circuitry is arranged to support the first circuit and the second circuit,
wherein one of the first circuit and the second circuit is arranged to provide an output responsive to transitioning from a first power state to a second power state, and
wherein another of the first circuit and the second circuit is arranged to provide an output responsive to being addressed.
2. The NVM device of claim 1, wherein
the first circuit is arranged to provide an output faster than an output of the second circuit.
3. The NVM device of claim 1, wherein
one of the first circuit and the second circuit is arranged in an array configuration; and wherein
another of the first circuit and the second circuit is arranged in a non-array configuration.
4. The NVM device of claim 1, further comprising:
at least one additional type NVM circuit, wherein the portion of the support circuitry is arranged to support also the at least one additional type NVM circuit.
5. The NVM device of claim 1, wherein
the first circuit is a programmable fuse circuit.
6. The NVM device of claim 5, wherein
the programmable fuse circuit includes at least one of: a one time programmable (OTP) fuse cell and a multiple time programmable (MTP) fuse cell.
7. The NVM device of claim 5, wherein
the programmable fuse circuit is programmable for storing its logic value.
8. The NVM device of claim 5, wherein
the programmable fuse circuit is adapted to output its stored logic value responsive to receiving a Power On Reset (POR) signal.
9. The NVM device of claim 1, wherein
the second circuit is an ordinary NVM circuit that is arranged to provide a logic value to the second operational component.
10. A hybrid NVM device, comprising:
a first circuit for storing data for a first operational component, wherein the first circuit includes a plurality of NVM array bits arranged in rows and columns of an NVM array, and wherein a first portion of the NVM array bits are arranged to output their stored logic value faster than a second portion of the NVM array bits during a power-on state;
a second circuit that includes at least one NVM cell arranged to provide an output responsive to transitioning from a first power state to a second power state, wherein the second circuit is for storing data for a second operational component distinct from the first operational component, and wherein the second circuit is distinct from the first operational component;
support circuitry, wherein a portion of the support circuitry is shared by the first circuit and the second circuit; and wherein the support circuitry include an addressing circuit that is arranged to cause the second portion of the NVM array bits to output their stored logic value in the power-on state.
11. The NVM device of claim 10, wherein
the first portion of the NVM array bits is arranged in the same manner as the second portion of the NVM array bits.
12. The NVM device of claim 10, wherein
the first portion of the NVM array bits includes at least one of a programmable bit and a fixed bit.
13. A hybrid NVM device, comprising:
support circuitry, wherein a portion of the support circuitry is shared by the first circuit and the second circuit; and wherein the support circuitry include an addressing circuit that is arranged to cause the second portion of the NVM array bits to output their stored logic value in the power-on state, wherein
the first portion of the NVM array bits includes at least one of a programmable bit and a fixed bit; and
the addressing circuit includes a by-passing circuit that is arranged to by-pass the fixed bit.
14. The NVM device of claim 13, wherein
the by-passing circuit includes at least one programmable bit.
15. A method for a hybrid NVM device, comprising:
storing a plurality of values in a plurality of NVM cells, wherein the NVM cells are adapted to store the values in a power-off state;
providing a first output from a first portion of NVM cells of a first type to a first operational component responsive to transitioning from a first power state to a second power state;
providing a second output from a second portion of NVM cells of a second type responsive to being addressed by support circuitry for a second operational component distinct from the first operational component, wherein a circuit for providing the second output is distinct from the first operational component and wherein the support circuitry is shared by the first portion of NVM cells and the second portion of NVM cells; and
providing a third output from a third portion of NVM cells for a third operational component; wherein the third output is distinct from the second output.
the outputs of the third portion of NVM cells include one of an ON state and an OFF state for the third operational component.
the outputs of the second portion of NVM cells include logic values for the second operational component.
calibrating the first operational component using the output of the first portion of NVM cells;
calibrating the second operational component using the output of the second portion of NVM cells; and
calibrating the third operational component using the output of the third portion of NVM cells.
latching the output of the third portion of NVM cells; and
providing the latched outputs of the third portion of NVM cells to the third operational component.
outputting the second portion of NVM cells as a result of a stored value in at least one of the first portion of NVM cells.
the first portion of NVM cells includes at least one of: a one time programmable (OTP) fuse cell and a multiple time programmable (MTP) fuse cell.
programming the first portion of NVM cells for storing their logic value.
evaluating a performance of at least one of the first, second, and third operational components; and
determining a value to be programmed in the first portion of NVM cells for improving the performance.
24. The method of claim 15, wherein
the second portion of the NVM cells are NVM bits of an NVM array, and the NVM bits are outputted as a result addressing of rows and columns of the NVM array by a control circuit.
the second portion of NVM bits includes at least one of a programmable bit and a fixed bit.
26. The NVM device of claim 1, wherein
the first power state is a power-off state and the second power state is a power-on state.
27. The NVM device of claim 15, wherein
RELATED APPLICATIONS This application is a Continuation Application of U.S. Pat. No. 7,283,390 filed on Sep. 28, 2005, which is a CIP of U.S. patent application Ser. No. 10/830,280 filed on Apr. 21, 2004; Ser. No. 11/839,985 filed on May 5, 2004; Ser. No. 11/016,546 filed on Dec. 17, 2004; and Ser. No. 11/015,293 filed on Dec. 17, 2004.
Furthermore, this application may be found to be related to U.S. Pat. No. 6,853,583 and U.S. patent application Ser. No. 10/813,907 filed on Mar. 30, 2004; Ser. No. 10/814,866 filed on Mar. 30, 2004; and Ser. No. 10/814,868 filed on Mar. 30, 2004.
This application may also be found related to U.S. Pat. No. 7,307,534.
The referenced Patent and Patent Applications, as well as the parent Patent Applications are incorporated herein by reference.
TECHNICAL FIELD The present invention relates to Non-Volatile Memory (NVM) circuits and devices; and more particularly, to hybrid NVM devices that include multiple types of NVM circuits supported by common support circuitry.
BACKGROUND Memory devices are electronic devices arranged to store electrical signals. For example, a basic memory element may be a fuse that can either be open or be closed. Open and closed states of the fuse may be used to designate one bit of information corresponding to a value of 1 or 0. A plurality of memory elements can be combined in various arrangements in order to store multiple bits arranged in words or other combinations. Various electronic circuits including semiconductor devices such as transistors are used as memory elements.
Memory elements may be classified in two main categories: volatile and nonvolatile. Volatile memory loses any data as soon as the system is turned off. Thus, it requires constant power to remain viable. Most types of random access memory (RAM) fall into this category. Non-volatile memory does not lose its data when the system or device is turned off. An NVM device may be implemented as a MOS transistor that has a source, a drain, an access or a control gate, and a floating gate. It is structurally different from a standard MOSFET in its floating gate, which is electrically isolated, or �floating�.
A range of considerations including a purpose of the device, power consumption, size, retention capacity and duration may influence design of non-volatile memory devices. For example, some NVM devices may be categorized as floating gate or charge-trapping from a programming perspective.
In floating gate memory circuits, electrons are typically transferred from the floating gate to the substrate or from the substrate to the floating gate by bi-directional tunneling through a thin silicon dioxide (SiO2) layer. Tunneling is the process by which an NVM device can be either erased or programmed and is usually dominant in thin oxides of thicknesses less than 12 nm. Storage of the charge on the floating gate allows the threshold voltage to be electrically altered between a low and a high value to represent logic 0 and 1, respectively. Other types of electron injection methods such as hot electron injection may also be employed in floating gate devices. In floating gate memory devices, charge or data is stored in the floating gate and is retained when the power is removed.
In charge-trapping memory devices, charge or data is stored in the discrete nitride traps and is also retained when the power is removed. Charge-trapping devices are typically used in MNOS (Metal Nitride Oxide Silicon), SNOS (Silicon Nitride Oxide Semiconductor), and SONOS (Silicon Oxide Nitride Oxide Semiconductor) technologies. The charges in MNOS memories may be injected from the channel region into the nitride by quantum mechanical tunneling through an ultra-thin oxide (UTO).
Non-volatile memory devices may also be implemented as NVM arrays that include a plurality of NVM cells arranged in rows and columns. In general, single-transistor n-channel NVM cells operate as follows. During an erase operation, electrons are removed from a floating gate of the NVM cell, thereby lowering the threshold voltage of the NVM cell. During a program operation, electrons are inserted into the floating gate of the NVM cell, thereby raising the threshold voltage of the NVM cell. Thus, during program and erase operations, the threshold voltages of selected NVM cells are changed. During a read operation, read voltages are applied to selected NVM cells. In response, read currents flow through these selected NVM cells.
SUMMARY Aspects of the invention are directed to a hybrid NVM circuit that includes a plurality of NVM sub-circuits of different types. The NVM sub-circuits, which can store data in a way that survives loss of power, may differ in their structure and/or function, but share common support circuitry.
According to one example aspect, one NVM sub-circuit is structured to provide its stored data during a transition period from a power-off state to a power-on state. Another NVM sub-circuit of the same NVM may provide its stored data upon being addressed in the power-on state.
According to another aspect, a first NVM sub-circuit may be adapted to provide a logic output to an operational component, while a second NVM sub-circuit provide an ON/OFF state output to another operational component.
In each aspect two or more NVM sub-circuits of the hybrid NVM circuit share at least a portion of the support circuitry.
It will be appreciated that a hybrid NVM circuit according to aspects may include any number of NVM sub-circuits of different types. The NVM sub-circuits may be of any type and share a portion or the whole support circuitry.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a block diagram of a device that includes a programmable fuse block for storing data such as calibration data to be used by an operational component;
FIG. 1B is a block diagram of another device that includes an ordinary NVM circuit for storing data such as calibration data to be used by another operational component;
FIG. 1C is a block diagram of a further device that includes a programmable fuse block such as that of FIG. 1A, and an ordinary NVM circuit such as that of FIG. 1B for storing data to be used by different operational components;
FIG. 2 is a block diagram of a device having a hybrid Non-Volatile Memory (NVM) circuit according to embodiments, for storing data to be used by other components of the device;
FIG. 3 is a block diagram of a device having a particular embodiment of the hybrid NVM circuit of FIG. 2 that accommodates two different types of NVM subcircuits, for storing data to be used by other components of the device;
FIG. 4 is a block diagram of a device having a particular embodiment of the hybrid NVM circuit of FIG. 2 that accommodates three different types of NVM subcircuits, for storing data to be used by other components of the device;
FIG. 5A is a block diagram illustrating an implementation of the hybrid NVM circuit of FIG. 4 according to an embodiment;
FIG. 5B is a block diagram illustrating an implementation of the hybrid NVM circuit of FIG. 4 according to another embodiment;
FIG. 6 schematically illustrates an embodiment of an ordinary type of NVM cell that may be part of the hybrid NVM circuit of FIG. 3 or FIG. 4;
FIG. 7 schematically illustrates an embodiment of another type of NVM cell that may be part of the hybrid NVM circuit of FIG. 3 or FIG. 4;
FIG. 8 schematically illustrates an embodiment of yet another type of an NVM cell that may be part of the hybrid NVM circuit of FIG. 3 or FIG. 4; and
FIG. 9 schematically illustrates an embodiment of one more type of an NVM cell that may be part of the hybrid NVM circuit of FIG. 3 or FIG. 4.
Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meanings identified below are not intended to limit the terms, but merely provide illustrative examples for the terms. The meaning of �a,� �an,� and �the� includes plural reference, the meaning of �in� includes �in� and �on.� The term �connected� means a direct electrical connection between the items connected, without any intermediate devices. The term �coupled� means either a direct electrical connection between the items connected or an indirect connection through one or more passive or active intermediary devices. The term �circuit� means either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term �signal� means at least one current, voltage, charge, temperature, data, or other measurable quantity. The term �ordinary NVM� refers to an NVM circuit or device that stores and outputs a logic value to be used by an operational component. As such, the �ordinary NVM� may or may not be arranged to provide the logic value for special purposes such as trimming an analog circuit.
FIG. 1A is a block diagram of device 102A that includes a programmable fuse block for storing data such as calibration data to be used by an operational component.
Device 102A includes programmable fuse block 112, operational component 108, and controller 122. Device 102A may be any electronic device that uses a memory circuit, in particular, a non-volatile memory circuit. Device 102A may use a variety of NVM circuits depending on available power, size, use of the stored information, and the like. For example, device 102A may be a Radio Frequency IDentification (RFID) tag with limitations on available power and size that uses an output of its NVM circuit to calibrate certain operational components, and the like.
A programmable fuse is essentially a non-volatile memory because it retains stored information in a power off state. A programmable fuse may be one time programmable (OTP) or multiple times programmable (MTP). Programmable fuse block 112 shown in the figure may include one or more programmable fuses. In case of multiple fuses, programmable fuse block 112 may include fuses that are arranged in an array.
Programmable fuse block 112 may provide an output to operational component 108 immediately following a transition to power-on state, while other types of NVM circuits may need to be addressed prior to providing their output. Accordingly, programmable fuse block 112 provides a fast NVM circuit that may be employed to calibrate operational components of a device during a power-on mode.
Device 102A also includes an operational component 108. As will be seen later in this description, operational component 108 is intended to be any one or more of a large possible number of components of device 102A, including programmable fuse block 112 itself, or even a component external to device 102A.
Operational component 108 may operate based on configuration/calibration data. A number of ways for accomplishing this are described later in this document. A distinction should be kept in mind, however, that programmable fuse block 112 may be employed to store other types of data in addition to the calibration data, such as a serial number of the RFID tag.
Programmable fuse block can store data 133 in cell 132. Data 133 encodes at least one value, or a series of values, for one or more operational components such as operational component 108. Data 133 may be the calibration data for operational component 108. Cell 132 may be a programmable fuse, a group of fuses, and the like. Data 133 encodes at least one value, or a series of values, for one or more operational components such as operational component 108. In some embodiments, data 133 is at least one logical bit, such as a 1 or a zero, stored in cell 132.
Data 133 may be input in operational component 108 via any number of paths. As data 133 is moved, it may change nature, or what it encodes.
Device 102A moreover includes controller 122. Controller 122 is adapted to program data 133 in cell 132. In addition, controller 122 may cooperate with other components, such as operational component 108.
As written above, operational component 108 may be any one or more of any of the tag circuit components. If more than one, then a plurality of calibration data may be stored. For each one of the possible operational components, one or more of their operation or performance characteristics may be controlled and/or changed by the calibration data. A number of examples and manners of controlling are described in this document.
FIG. 1B is a block diagram of device 102B that includes an ordinary NVM circuit for storing data such as calibration data to be used by another operational component.
Device 102B includes NVM circuit 114, operational component 109, and controller 124. Parts of device 102B perform actions that are similar to the actions performed by comparable parts in device 102A of FIG. 1A, while each part may or may not be formed and function similarly as described below.
NVM circuit 114 is an ordinary NVM circuit that is arranged to store data 135, a logic or non-logic value, such as an ON/OFF state, in individual cells (e.g. cell 134) and provide data 135 upon being addressed. In one embodiment, NVM circuit 114 may be an NVM array comprising cells that are addressable in terms of a row and a column.
In some embodiments, a value for data 135 may be encoded in an amount of charge stored in a device. In another embodiment, data 135 may be at least one logical bit, such as a 1 or a zero, stored in cell 134. Of course, data 135 may need more than one cell, and so on.
Controller 124 is adapted to program data 135 in cell 134. Controller 124 is also arranged to address cell 134 to provide data 135 to operational component 109. In addition, controller 124 may cooperate with other components, such as operational component 109.
Operational component 109 may be adapted to receive data 135 for processing, calibration, and the like. In FIG. 1B, data 135 is input in operational component 109 directly. In other embodiments, data 135 may be routed through any suitable component before being input in operational component 109. For example, data 135 may be first input from cell 134 into a binary output circuit. Then, from the binary output circuit, data 135 may be input in operational component 109.
Furthermore, controller 124 may be adapted to sense a performance of operational component 109. Controller 109 may then determine data 135 so as to adjust the performance. The performance may be optimized, if needed. In some instances, adjusting can be to diminish the performance if, for example, more privacy is required.
This feature of determining what data 135 to program may be invoked spontaneously, autonomously, in response to a received command, and so on. Adjusting may be desired if the performance has changed, for example either due to the passage of time, or due to changed environmental conditions, and so on. Adjusting may also take place while manufacturing or testing a device, or preparing it for field use. For example, the processor may step through a number of values to adjust an antenna reception of an RFID tag.
Device 102B may be implemented with fewer or additional components such as support circuitry for NVM circuit 114, communication circuitry for interaction with other devices, and the like.
FIG. 1C is a block diagram of device 102C that includes a programmable fuse block such as that of FIG. 1A, and an ordinary NVM circuit such as that of FIG. 1B for storing data to be used by different operational components.
Parts of device 102C that are similarly numbered in FIGS. 1A and 1B perform actions that are similar to the actions performed by comparable parts in devices 102A and 102B.
Accordingly, programmable fuse block 112 is adapted to provide a fast calibration data (e.g. data 133) to operational component 108, while NVM circuit 114 is adapted to provide data 135 to operational component 109 for programming purposes, and the like, upon being addressed.
Controller 126 may be a combination of controllers 122 and 124 of FIGS. 1A and 1B, and manage programmable fuse block 112 and NVM circuit 114. Consequently, controller 126 may include different blocks to address, program, monitor, and the like, programmable fuse block 112 and NVM circuit 114.
Some applications may need multiple NVM memory circuits. For example, RFID tags may include components that need calibration data at power-on and other components that need programming data after power-on. In such applications, having separate controller sub-circuits for different types of memory circuits is likely to increase power consumption and size of circuitry. On the other hand, in applications like RFID tags available power and size are at a premium.
FIG. 2 is a block diagram of device 202 having a hybrid Non-Volatile Memory (NVM) circuit according to embodiments, for storing data to be used by other components of the device.
Device 202 includes hybrid NVM circuit 210 that is adapted to interact with other circuits 204. Individual cells of hybrid NVM 210 are adapted to store information as a result of �write� operation 206 and provide the stored information as a result of �read� operation 208. The information is stored even during a power-off state of device 202.
�Read� operation 208, which provides the stored information to one or more of the other circuits 204, may occur during a transition from the power-off state to a power-on state for some parts of hybrid NVM circuit 210. For other parts of hybrid NVM circuit 210, �read� operation 208 may occur during the power-on state upon being addressed by another circuit (e.g. a controller).
As a result, different circuits of device 202 may receive data for their operation at different states of powering the device. For example, an oscillator circuit may be provided calibration data during the transition from the power-off state from one part of hybrid NVM circuit 210, while a digital signal processor circuit may be provided programming data after the transition.
The information stored in hybrid NVM circuit 210 may include analog, digital or other types of data. For example, different parts of hybrid NVM circuit 210 may provide logic bits, ON/OFF states, latched outputs for trimming analog circuits, and the like.
FIG. 3 is a block diagram of device 300 having a particular embodiment of the hybrid NVM circuit 210 of FIG. 2 that accommodates two different types of NVM sub-circuits, for storing data to be used by other components of the device.
Hybrid NVM circuit 310 includes first type NVM sub-circuit 312 and second type NVM sub-circuit 314. First type NVM sub-circuit 312 and second type NVM sub-circuit 314 operate as described previously and provide input to operational components 307 and 308, respectively. In one example embodiment, first type NVM sub-circuit 312 may provide a fast output for calibrating operational component 307 during a transition to the power-on state. In another example embodiment, second type NVM sub-circuit 314 may provide programming data to operational component 308 in the power-on state upon being addressed by controller 320.
Controller 320 is adapted to interact with both NVM sub-circuits. The interaction may include programming the NVM sub-circuits, addressing individual cells to output their data, and the like. In one embodiment, hybrid NVM circuit 310 may also include a sub-circuit that is adapted to store one or more fixed bits. In such an embodiment, controller 320 may include a by-passing circuit that arranged to by-pass the one or more fixed bits. Such a by-passing circuit may also include at least one programmable bit.
By integrating first type NVM sub-circuit 312 and second type NVM sub-circuit 314, and combining the control operations in a single controller (320), size and power consumption can be optimized.
FIG. 4 is a block diagram of device 400 having a particular embodiment of the hybrid NVM circuit 210 of FIG. 2 that accommodates three different types of NVM subcircuits, for storing data to be used by other components of the device.
Parts of device 400 that are similarly numbered in device 300 of FIG. 3 operate in a likewise manner. To illustrate the diversity of the hybrid NVM concept, hybrid NVM circuit 410 includes three NVM sub-circuits: first type NVM sub-circuit 312, second type NVM sub-circuit 314, third type NVM sub-circuit 416.
In addition to the first and second type NVM sub-circuits, third type NVM sub-circuit 416 provides input to operational component 409. In one embodiment, third type NVM sub-circuit 416 may provide a latched output for trimming an analog circuit. In a further embodiment, third type NVM sub-circuit 416 may provide an ON/OFF state output that may be employed to control at least one of a voltage, a frequency, or a current.
FIG. 5A is a block diagram illustrating an implementation of hybrid NVM circuit 510A according to an embodiment.
Hybrid NVM circuit 510A includes first type NVM sub-circuit 512, second type NVM sub-circuit 514, and third type NVM sub-circuit 516. These NVM sub-circuits are examples of NVM circuits as described in conjunction with previous figures.
NVM sub-circuits commonly comprise a number of cells (e.g. cells 532, 534, and 536), which store the data to be consumed by operational components. NVM sub-circuits may be implemented in form of an NVM array comprising cells that are addressable in terms of a row and a column. First type NVM sub-circuit 512 and second type NVM sub-circuit 514 are examples of NVM arrays, while third type NVM sub-circuit 516 illustrates a non-array NVM circuit.
In some embodiments, a non-volatile memory cell may be constructed using a floating-gate pFET readout transistor having its source tied to a power source and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor structure having its first terminal coupled to a first voltage source and its second terminal coupled to the floating gate and a tunneling capacitor structure having its first terminal coupled to a second voltage source and its second terminal coupled to the floating gate may be utilized in each embodiment.
The control capacitor structure is fabricated so that it has much more capacitance than does the tunneling capacitor structure (and assorted stray capacitance between the floating gate and various other nodes of the cell). Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the floating gate, thus controlling the charge on the floating gate and the information value stored thereon.
High voltage switches 541 and 542 are examples of a series of high voltage switches that are arranged to provide the first and the second voltages for programming and erasing of the NVM cells.
NVM controller 546 is arranged to program and address individual cells of the NVM sub-circuits to output their data by managing high voltage switches 541, 542, and the like.
NVM charge pump 545 is an electronic circuit that uses capacitors as energy storage elements to convert low voltages into higher voltage outputs. Charge pump circuits are typically capable of high efficiencies, sometimes as high as 90-95%.
NVM charge pump 545 may use switches to control a connection of voltages to the capacitor. For example, to generate a higher voltage, a first stage may involve the capacitor being connected across a voltage and charged up. In a second stage, the capacitor is disconnected from the original charging voltage and reconnected with its negative terminal to the original positive charging voltage. Because the capacitor retains the voltage across it (ignoring leakage effects) the positive terminal voltage is added to the original, effectively doubling the voltage. This higher voltage output may then be smoothed by the use of another capacitor.
FIG. 5B is a block diagram illustrating an implementation of hybrid NVM circuit 510B according to another embodiment. Parts of hybrid NVM circuit 510B that are similarly numbered in hybrid NVM circuit 510A of FIG. 5A operate in a likewise manner.
To emphasize that NVM sub-circuits may or may not include arrays, all three NVM sub-circuits in hybrid NVM circuit 510B are illustrated in array form. Differently from FIG. 5A, hybrid NVM circuit 510B includes CLOOP 548 in place of high voltage switch 542.
In some embodiments, a Control Loop for Overtunneling Current Prevention (CLOOP) device may be implemented instead of a series of high voltage switches that control rows and columns of NVM arrays within the hybrid NVM circuit. CLOOP 548 is such a device. Structure and operation of a CLOOP device is described in detail in U.S. Pat. No. 6,853,583.
The examples of FIGS. 5A and 5B are for illustration purposes, and do not constitute a limitation on the present invention. Other embodiments may be implemented using other circuits and other combinations of circuits for providing common support circuitry to a plurality of NVM sub-circuits of a hybrid NVM circuit, without departing from the scope and spirit of the invention. For example, the hybrid NVM circuit may further include an oscillator, an ESD protection device, and the like.
FIG. 6 schematically illustrates an embodiment of an ordinary type of NVM cell (634) that may be part of the hybrid NVM circuit of FIG. 3 or FIG. 4.
NVM cell 634 is adapted to store and provide a logic value such as a �1� or a �0� bit. While FIG. 6 shows an example implementation, an �ordinary� NVM cell may be implemented in any way known in the art.
Schematic diagram of NVM cell 634 shows the tunneling transistors as capacitors denoted CG1 and CG0 and the control transistors as capacitors denoted CG1′ and CG0′ for clarity but they may be implemented with pFETs, for example as described in U.S. patent application Ser. No. 11/839,935 (IMPJ-0057) filed on May 5, 2004.
In this embodiment, VDD may be provided at all times to bias the gates of transistors M1C and M0C. REN (row enable) and RSB (row select bar) are provided to address individual cells such as NVM cell 634 in the NVM array. TUN is tunneling signal provided to tunneling capacitors CG1 and CG0. The signals VDD, REN, TUN and RSB are the row control signals, although VDD need not be applied via a row and could instead be applied via a column. The column control signals comprise the data signals on lines D1 and D0.
Transistors M1C and M0C have their gates coupled together and to VDD and their sources, drains and well connections coupled to the corresponding sources, drains and well connections of respective readout transistors M1A and M0A. This is done in order to avoid disturbing the contents of the cell when it is not selected.
During a read operation, the REN (row enable) line is set to VDD and with the gates of M1C and M0C at VDD. Thus, M1C and M0C are not conducting and readout transistors M1A and M0A operate normally to provide an output current as a function of charge stored on corresponding floating gates FG1 and FG0.
During a write operation, REN is set to approximately half the tunneling voltage. With VDD on the gates of M1C and M0C, M1C and M0C conduct, effectively connecting the drain nodes of M1A and M0A to REN. Since the drain, source, and bulk nodes of both M1A and M0A are set to half the tunneling voltage, there can be no tunneling across M1A or M0A. Furthermore, TUN is also set to half the tunneling voltage during the write mode. Accordingly, there can be no tunneling across CG1 or CG0.
FIG. 7 schematically illustrates an embodiment of another type of NVM cell (732) that may be part of the hybrid NVM circuit of FIG. 3 or FIG. 4.
NVM cell 732 is one embodiment of a programmable fuse implemented using Metal Oxide Field Effect Transistors (MOSFETs). NVM cell 732 comprises cross-coupled transistor pair M1C and M0B, which form a half latch circuit. In the MOSFET embodiment, M1C and M0B may be nFETs. A gate terminal of M1C is coupled to a drain of M0B. Similarly, a gate terminal of M0B is coupled to a drain of M1C. Sources of both transistors are coupled together and are arranged to receive a ground signal.
The drain terminal of M0B is arranged to provide output signal OUT, which includes stored value 733. In one embodiment, stored value 733 may be a digital value �0� or �1�.
Drain terminals of pFET type transistors M1A and M0C are coupled to drain terminals of M1C and M0B, respectively. Source terminals of M1A and M0C are coupled to a supply voltage (VDD). The source terminals are also arranged to receive a reset signal or a power-on reset (POR) signal.
Gate terminals of M1A and M0C (FG1 and FG0) are arranged as floating gates that store a charge such that NVM cell 732 settles on a state determined by the charges of the floating gates upon receiving a power-up signal (VDD applied) or the reset signal.
Whereas MC1 and M0B form a half latch circuit, programmable fuses may be implemented using full latch circuits, multiple pairs of half latch circuits, and the like. Furthermore, the transistors are not restricted to MOSFET type transistors, and other types devices may also be employed.
The programmable fuse forming NVM cell 732 is termed �self-latching�, meaning that once power is applied to the fuse, the latch of the associated fuse will eventually settle to some state. Details of programmable fuses are described in more detail in U.S. patent application Ser. No. 10/813,907 (IMPJ-0027A) filed on Mar. 30, 2004; Ser. No. 10/814,866 (IMPJ-0027B) filed on Mar. 30, 2004; and Ser. No. 10/814,868 (IMPJ-0027C) filed on Mar. 30, 2004.
FIG. 8 schematically illustrates an embodiment of yet another type of an NVM cell (836) that may be part of the hybrid NVM circuit of FIG. 3 or FIG. 4.
Employing latch 852, NVM cell 836 provides a latched output to other operational components. This makes an output of NVM cell 836 suitable for trimming analog circuits. Parts of NVM cell 836 that are similarly numbered in NVM cell 634 of FIG. 6 operate in a likewise manner.
In addition to the components of NVM cell 634 of FIG. 6, NVM cell 836 includes latch 852, which is coupled to drains of M1B and M0B. Sources of M1B and M0B are coupled to drains of M1C-M1A and M0C-M0A transistor pairs. RSB signal controls gate terminals of M1B and M0B providing an output to latch 852.
Latch 852 is arranged to settle on a state upon receiving the output of NVM cell 634 such that the stored output can be used to trim an analog circuit, and the like.
FIG. 9 schematically illustrates an embodiment of one more type of an NVM cell (938) that may be part of the hybrid NVM circuit of FIG. 3 or FIG. 4.
NVM cell 938 includes transistors M1A and M1C, which are coupled together at their source and drain terminals. The source terminals are arranged to receive REN signal, while the drain terminals are arranged to provide an output.
A gate terminal of M1C is arranged to receive supply voltage VDD. A tunneling transistor as capacitor denoted CG1 and a control transistor as capacitor denoted CG1′ are coupled to a gate terminal of M1A, and function as described above in conjunction with FIG. 6.
An output of NVM cell 938 may be an ON state of an OFF state. The output may be used to control a current, a voltage, or a frequency of an operational component.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4090258Dec 29, 1976May 16, 1978Westinghouse Electric Corp.MNOS non-volatile memory with write cycle suppressionUS4132904Jul 28, 1977Jan 2, 1979Hughes Aircraft CompanyVolatile/non-volatile logic latch circuitUS4158239Dec 20, 1977Jun 12, 1979International Business Machines CorporationResistive gate FET flip-flop storage cellUS4384288Dec 31, 1980May 17, 1983Walton Charles APortable radio frequency emitting identifierUS4388524Sep 16, 1981Jun 14, 1983Walton Charles AElectronic identification and recognition system with code changeable reactanceUS4541073Sep 28, 1982Sep 10, 1985Societe Pour L'etude Et La Fabrication De Circuits Integres SpeciauxNon-volatile flip-flop with a static resettingUS4546241Dec 10, 1982Oct 8, 1985Walton Charles AElectronic proximity identification systemUS4571704Feb 17, 1984Feb 18, 1986Hughes Aircraft CompanyNonvolatile latchUS4575823Aug 17, 1982Mar 11, 1986Westinghouse Electric Corp.Electrically alterable non-volatile memoryUS4580041Dec 9, 1983Apr 1, 1986Walton Charles AElectronic proximity identification system with simplified low power identifierUS4758869Aug 29, 1986Jul 19, 1988Waferscale Integration, Inc.Nonvolatile floating gate transistor structureUS4935702Dec 9, 1988Jun 19, 1990Synaptics, Inc.Subthreshold CMOS amplifier with offset adaptationUS4953928Jun 9, 1989Sep 4, 1990Synaptics Inc.MOS device for long-term learningUS5018102Dec 20, 1988May 21, 1991Texas Instruments, IncorporatedMemory having selected state on power-upUS5068622Feb 28, 1990Nov 26, 1991Synaptics, IncorporatedCMOS amplifier with offset adaptationUS5086331Jan 18, 1991Feb 4, 1992U.S. Philips Corp.Integrated circuit comprising a programmable cellUS5124568Feb 14, 1991Jun 23, 1992Advanced Micro Devices, Inc.Edge-triggered flip-flopUS5146106Feb 5, 1991Sep 8, 1992Synaptics, IncorporatedCMOS winner-take all circuit with offset adaptationUS5168464Nov 29, 1989Dec 1, 1992Ncr CorporationNonvolatile differential memory device and methodUS5272368May 10, 1991Dec 21, 1993Altera CorporationComplementary low power non-volatile reconfigurable EEcellUS5301150Jun 22, 1992Apr 5, 1994Intel CorporationFlash erasable single poly EPROM deviceUS5323066Jun 1, 1992Jun 21, 1994Motorola, Inc.Method and apparatus for performing power on reset initialization in a data processing systemUS5361001Dec 3, 1993Nov 1, 1994Motorola, Inc.Circuit and method of previewing analog trimmingUS5384727Nov 8, 1993Jan 24, 1995Advanced Micro Devices, Inc.Fuse trimming in plastic package devicesUS5394367Mar 18, 1994Feb 28, 1995Ramtron International CorporationSystem and method for write-protecting predetermined portions of a memory arrayUS5412594Aug 8, 1994May 2, 1995Advanced Micro Devices, Inc.Fuse trimming in plastic package devicesUS5430670Nov 8, 1993Jul 4, 1995Elantec, Inc.Differential analog memory cell and method for adjusting sameUS5438542Oct 31, 1994Aug 1, 1995Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS5463348Jul 27, 1994Oct 31, 1995California Institute Of TechnologyCMOS low-power, wide-linear-range, well-input differential and transconductance amplifiersUS5504707 *Sep 16, 1994Apr 2, 1996Fujitsu LimitedSemiconductor deviceUS5517044Dec 20, 1994May 14, 1996Nec CorporationNon-volatile semiconductor memory device having thin film transistors equipped with floating gatesUS5541878Jun 27, 1994Jul 30, 1996Synaptics, IncorporatedWritable analog reference voltage storage deviceUS5596524Apr 21, 1995Jan 21, 1997Advanced Micro Devices, Inc.CMOS memory cell with gate oxide of both NMOS and PMOS transistors as tunneling window for program and eraseUS5616942Mar 27, 1996Apr 1, 1997Hyundai Electronics Industries Co., Ltd.Flash EEPROM cell and manufacturing methods thereofUS5617358Mar 10, 1995Apr 1, 1997Nec CorporationNonvolatile semiconductor memory device capable of converging threshold voltage with low power supply voltageUS5623442Jun 8, 1994Apr 22, 1997Nkk CorporationMemory cells and memory devices with a storage capacitor of parasitic capacitance and information storing method using the sameUS5627392Mar 7, 1995May 6, 1997California Institute Of TechnologySemiconductor structure for long term learningUS5633518Jul 28, 1995May 27, 1997Zycad CorporationNonvolatile reprogrammable interconnect cell with FN tunneling and programming method thereofUS5650966Nov 1, 1995Jul 22, 1997Advanced Micro Devices, Inc.Temperature compensated reference for overerase correction circuitry in a flash memoryUS5659498Jul 19, 1996Aug 19, 1997Sgs-Thomson Microelectronics S.R.L.Unbalanced latch and fuse circuit including the sameUS5666307Nov 14, 1995Sep 9, 1997Programmable Microelectronics CorporationPMOS flash memory cell capable of multi-level threshold voltage storageUS5677917Apr 29, 1996Oct 14, 1997Motorola, Inc.Integrated circuit memory using fusible links in a scan chainUS5687118Nov 14, 1995Nov 11, 1997Programmable Microelectronics CorporationPMOS memory cell with hot electron injection programming and tunnelling erasingUS5691939Dec 7, 1995Nov 25, 1997Programmable Microelectronics CorporationTriple poly PMOS flash memory cellUS5706227Dec 7, 1995Jan 6, 1998Programmable Microelectronics CorporationDouble poly split gate PMOS flash memory cellUS5717636May 3, 1996Feb 10, 1998Sgs-Thomson Microelectronics S.R.L.EEPROM memory with contactless memory cellsUS5729155Sep 21, 1995Mar 17, 1998Nec CorporationHigh voltage CMOS circuit which protects the gate oxides from excessive voltagesUS5731716Jan 26, 1996Mar 24, 1998Sgs-Thomson Microelectronics, S.R.L.Programmable multibit register for coincidence and jump operations and coincidence fuse cellUS5736764Nov 21, 1995Apr 7, 1998Programmable Microelectronics CorporationPMOS flash EEPROM cell with single polyUS5754471Jun 6, 1995May 19, 1998Advanced Micro Devices, Inc.Low power CMOS array for a PLD with program and erase using controlled avalanche injectionUS5761121Oct 31, 1996Jun 2, 1998Programmable Microelectronics CorporationPMOS single-poly non-volatile memory structureUS5763912Sep 25, 1995Jun 9, 1998Intel CorporationDepletion and enhancement MOSFETs with electrically trimmable threshold voltagesUS5777361Jun 3, 1996Jul 7, 1998Motorola, Inc.Single gate nonvolatile memory cell and method for accessing the sameUS5777926Oct 24, 1996Jul 7, 1998Programmable Microelectronics CorporationRow decoder circuit for PMOS non-volatile memory cell which uses channel hot electrons for programmingUS5786617Oct 5, 1995Jul 28, 1998National Semiconductor CorporationHigh voltage charge pump using low voltage type transistorsUS5790060Sep 11, 1996Aug 4, 1998Harris CorporationDigital-to-analog converter having enhanced current steering and associated methodUS5796656Feb 22, 1997Aug 18, 1998Programmable Microelectronics CorporationRow decoder circuit for PMOS non-volatile memory cell which uses electron tunneling for programming and erasingUS5798967Feb 22, 1997Aug 25, 1998Programmable Microelectronics CorporationSensing scheme for non-volatile memoriesUS5801994Aug 15, 1997Sep 1, 1998Programmable Microelectronics CorporationNon-volatile memory array architectureUS5822714Mar 5, 1997Oct 13, 1998International Business Machines CorporationData processing system and method for accessing a plurality of radio frequency identification tagsUS5825063Jul 26, 1996Oct 20, 1998California Institute Of TechnologyThree-terminal silicon synaptic deviceUS5835402Mar 27, 1997Nov 10, 1998Xilinx, Inc.Non-volatile storage for standard CMOS integrated circuitsUS5841165Dec 22, 1995Nov 24, 1998Programmable Microelectronics CorporationPMOS flash EEPROM cell with single polyUS5844300Sep 19, 1996Dec 1, 1998Intel CorporationSingle poly devices for monitoring the level and polarity of process induced charging in a MOS processUS5854762Oct 30, 1997Dec 29, 1998Sgs-Thomson Microelectronics, S.R.L.Protection circuit for redundancy register set-up cells of electrically programmable non-volatile memory devicesUS5875126Sep 26, 1996Feb 23, 1999California Institute Of TechnologyAutozeroing floating gate amplifierUS5886566Aug 21, 1997Mar 23, 1999Integrated Silicon Solution, Inc.High voltage charge transfer stageUS5890199Oct 21, 1996Mar 30, 1999Ramtron International CorporationData processor incorporating a ferroelectric memory array selectably configurable as read/write and read only memoryUS5892709May 9, 1997Apr 6, 1999Motorola, Inc.Single level gate nonvolatile memory device and method for accessing the sameUS5892712Apr 29, 1997Apr 6, 1999Nvx CorporationSemiconductor non-volatile latch device including embedded non-volatile elementsUS5898613Jun 25, 1997Apr 27, 1999California Institute Of TechnologypMOS analog EEPROM cellUS5901084Sep 23, 1997May 4, 1999Mitsubishi Denki Kabushiki KaishaNonvolatile semiconductor memory device having floating gate electrodeUS5912841Dec 23, 1997Jun 15, 1999Hyundai Electronics Industries Co., Ltd.Repair fuse circuit performing complete latch operation using flash memory cellUS5912842Oct 9, 1997Jun 15, 1999Programmable Microelectronics Corp.Nonvolatile PMOS two transistor memory cell and arrayUS5912937Mar 14, 1997Jun 15, 1999Xilinx, Inc.CMOS flip-flop having non-volatile storageUS5914894Jun 1, 1998Jun 22, 1999California Institute Of TechnologyMethod for implementing a learning functionUS5914895Sep 10, 1997Jun 22, 1999Cypress Semiconductor Corp.Non-volatile random access memory and methods for making and configuring sameUS5939945Jul 25, 1997Aug 17, 1999Siemens AktiengesellschaftAmplifier with neuron MOS transistorsUS5966329Oct 9, 1997Oct 12, 1999Programmable Microelectronics CorporationApparatus and method for programming PMOS memory cellsUS5969987Feb 3, 1999Oct 19, 1999Information Storage Devices, Inc.Non-volatile electrically alterable semiconductor memory for analog and digital storageUS5972804Nov 3, 1997Oct 26, 1999Motorola, Inc.Process for forming a semiconductor deviceUS5982669Nov 4, 1998Nov 9, 1999National Semiconductor CorporationEPROM and flash memory cells with source-side injectionUS5986927Nov 10, 1998Nov 16, 1999California Institute Of TechnologyAutozeroing floating-gate amplifierUS5990512Apr 22, 1997Nov 23, 1999California Institute Of TechnologyHole impact ionization mechanism of hot electron injection and four-terminal ρFET semiconductor structure for long-term learningUS6011425Jul 11, 1997Jan 4, 2000Electronics And Telecommunications Research InstituteCMOS offset trimming circuit and offset generation circuitUS6028789Jun 15, 1999Feb 22, 2000Vantis CorporationZero-power CMOS non-volatile memory cell having an avalanche injection elementUS6049229Jul 6, 1999Apr 11, 2000Pericom Semiconductor Corp.Self-biasing CMOS PECL receiver with wide common-mode range and multi-level-transmit to binary decoderUS6055185Apr 1, 1998Apr 25, 2000National Semiconductor CorporationSingle-poly EPROM cell with CMOS compatible programming voltagesUS6060919Dec 4, 1998May 9, 2000Ramtron International CorporationCMOS preferred state power-up latchUS6081451May 20, 1998Jun 27, 2000National Semiconductor CorporationMemory device that utilizes single-poly EPROM cells with CMOS compatible programming voltagesUS6111785Aug 23, 1999Aug 29, 2000Sharp Kabushiki KaishaNonvolatile semiconductor memory device capable of decreasing layout area for writing defective addressUS6125053Nov 30, 1998Sep 26, 2000California Institute Of TechnologySemiconductor structure for long-term learningUS6137721Apr 28, 1999Oct 24, 2000National Semiconductor CorporationMemory device having erasable frohmann-bentchkowsky EPROM cells that use a plate-to-floating gate coupled voltage during erasureUS6137722Apr 28, 1999Oct 24, 2000National Semiconductor CorporationMemory array having Frohmann-Bentchkowsky EPROM cells with a reduced number of access transistorsUS6137723Apr 28, 1999Oct 24, 2000National Semiconductor CorporationMemory device having erasable Frohmann-Bentchkowsky EPROM cells that use a well-to-floating gate coupled voltage during erasureUS6137724Oct 26, 1999Oct 24, 2000National Semiconductor CorporationMemory device that utilizes single-poly EPROM cells with CMOS compatible programming voltagesUS6141247Dec 21, 1998Oct 31, 2000Micron Technology, Inc.Non-volatile data storage unit and method of controlling sameUS6144581Nov 30, 1998Nov 7, 2000California Institute Of TechnologypMOS EEPROM non-volatile data storageUS6151238Feb 23, 1999Nov 21, 2000Microchip Technology, Inc.Calibrating functions of an integrated circuit and storing calibration parameters thereof in a programmable fuse arrayUS6166954Jul 14, 1999Dec 26, 2000Programmable Microelectronics CorporationSingle poly non-volatile memory having a PMOS write path and an NMOS read pathUS6400622 *Oct 23, 2001Jun 4, 2002Matsushita Electric Industrial Co., Ltd.Semiconductor memory deviceUS7106642 *Mar 9, 2005Sep 12, 2006Kabushiki Kaisha ToshibaSemiconductor integrated circuit device in which a measure to counter soft errors is takenUS7283390 *Sep 28, 2005Oct 16, 2007Impinj, Inc.Hybrid non-volatile memoryUS7307534 *Sep 28, 2005Dec 11, 2007Impinj, Inc.RFID tag using hybrid non-volatile memoryUS20040136245 *Oct 29, 2003Jul 15, 2004Hiroshi MakamuraSemiconductor memoryUS20060133175 *Dec 17, 2004Jun 22, 2006Vadim GutnikRFID tags with electronic fuses for storing component configuration dataUS20060221715 *Apr 15, 2005Oct 5, 2006Impinj, Inc.Redundant non-volatile memory cellUS20070263456 *May 15, 2007Nov 15, 2007Impinj, Inc.Inverter non-volatile memory cell and array systemUS20080112238 *Dec 20, 2006May 15, 2008Seon-Taek KimHybrid flash memory device and method for assigning reserved blocks thereof* Cited by examinerNon-Patent CitationsReference1Carley, L. Richard, "Trimming Analog Circuits Using Floating-Gate Analog MOS Memory", IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989, pp. 1569-1575.2Chang, L. et al., "Non-Volatile Memory Device With True CMOS Compatibility", Electronics Letters, vol. 35, No. 17, Aug. 19, 1999, pp. 1443-1445.3Chang, Leland et al., "A CMOS-Compatible Single-Poly Cell For Use As Non-Volatile Memory", International Semiconductor Device Research Symposium, Dec. 1-3, 1999, pp. 57-60.4Chinese First Office Action, Chinese Application No. 03820492.4, Jun. 21, 2008, 5 pages.5Chung, S.S. et al., "N-Channel Versus P-Channel Flash EEPROM-Which One Has Better Reliabilities", 39th Annual IEEE International Reliability Physics Symposium, 2001, pp. 67-72.6Declaration of Non-Establishment of International Search Report for International Application No. PCT/US03/21239, Nov. 5, 2003, 2 pages.7Declercq M. et al., "Design and Optimization of High-Voltage CMOS Devices Compatible with a Standard 5 V CMOS Technology", IEEE Custom Integrated Circuits Conference, 1993, pp. 24.6.1-24.6.4.8Dickson, John F., "On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique", IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, Jun. 1976, pp. 374-378.9Diorio, C. et al., "A Floating-Gate MOS Learning Array with Locally Computed Weight Updates" IEEE Transactions on Electron Devices, vol. 44, No. 12, Dec. 1997, pp. 1-10.10Diorio, C. et al., "A High-Resolution Non-Volatile Analog Memory Cell", IEEE International Symposium on Circuits and Systems, vol. 3, 1995, pp. 2233-2236.11Diorio,C., "A p-Channel MOS Synapse Transistor with Self-Convergent Memory Writes", IEEE Transaction On Electron Devices, vol. 47, No. 2, Feb. 2000, pp. 464-472.12European Examination Report, European Application No. 03763311.2, Feb. 7, 2006, 3 pages.13European Examination Report, European Application No. 03763311.2, Jun. 26, 2006, 4 pages.14European Examination Report, European Application No. 03763311.2, May 18, 2005, 4 pages.15Herdt, C. et al., "Analysis, Measurement, and Simulation of Dynamic Write Inhibit in an nvSRAM Cell", IEEE Transactions on Electron Devices, vol. 39, No. 5, May 1992, pp. 1191-1196.16IBM Technical Disclosure Bulletin, "Fuse Circuit With Zero DC Current", IBM Corporation, Jul. 1987, vol. 30, No. 2.17International Preliminary Examination Report for International Application No. PCT/US2005/010431, Aug. 3, 2006.18International Preliminary Report on Patentability for International Application No. PCT/US05/10432, date of mailing Jun. 19, 2006.19International Preliminary Report on Patentability for International Application No. PCT/US05/10434, Mar. 9, 2006.20International Preliminary Report on Patentability for International Application No. PCT/US2005/013644, Oct. 25, 2006.21International Report on Patentability for International Application No. PCT/US03/21239, May 24, 2010.22International Search Report and Written Opinion for International Application No. PCT/US05/10434, date of mailing Sep. 13, 2005.23International Search Report and Written Opinion for International Application No. PCT/US2005/010432, date of mailing Sep. 27, 2005.24International Search Report and Written Opinion for International Application No. PCT/US2005/013644, date of mailing Aug. 3, 2005.25International Search Report and Written Opinion for International Application No. PCT/US2005/015606, date of mailing Feb. 24, 2006.26International Search Report for International Application No. PCT/US03/23724, date of mailing Jan. 20, 2004.27International Search Report for International Application No. PCT/US03/31792, date of mailing Aug. 12, 2004.28International Search Report for International Application No. PCT/US2005/010431, date of mailing Sep. 27, 2005.29Invitation to Pay Additional Fees (Partial International Search), Application No. PCT/US 03/31792, date of mailing Apr. 22, 2004.30Invitation to Pay Additional Fees for Application No. PCT/US03/31792, date of mailing Apr. 2, 2004.31Invitation to Pay Additional Fees for Application No. PCT/US2005/015606, date of mailing Nov. 18, 2005.32Japanese Office Action, Japanese Application No. 2004-519985, Sep. 8, 2008, 9 pages.33Lanzoni M. et al., "A Novel Approach to Controlled Programming of Tunnel-Based Floating-Gate MOSFET's", 1994 IEEE Journal of Solid-State Circuits, vol. 29, No. 2, pp. 147-150.34Office Action for U.S. Appl. No. 11/015,293 mailed Apr. 4, 2007.35Ohsaki K., et al., "A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes", IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994, pp. 311-316.36Partial International Search for International Application No. PCT/US03/31792, date mailed Apr. 2, 2004.37Raszka, J. et al., "Embedded Flash Memory for Security Applications in a 0.13 mum CMOS Logic Process", 2004 IEEE International Solid-State Circuis Conference, ISSCC, Session 2, Non-Volatile Memory, 2.4, pp. 46-47, Feb. 2004.38Raszka, J. et al., "Embedded Flash Memory for Security Applications in a 0.13 μm CMOS Logic Process", 2004 IEEE International Solid-State Circuis Conference, ISSCC, Session 2, Non-Volatile Memory, 2.4, pp. 46-47, Feb. 2004.39Shi, Y. et al., "Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFET's", IEEE Transactions on Electron Devices, vol. 45, No. 11, Nov. 1998, pp. 2355-2360.40Taiwan Office Action, Taiwan Application No. 092118353, Jul. 30, 2008, 6 pages.41United States Office Action, U.S. Appl. No. 10/190,337, Jun. 17, 2003, 8 pages.42United States Office Action, U.S. Appl. No. 10/437,262, Jan. 11, 2005, 8 pages.43United States Office Action, U.S. Appl. No. 10/813,907, Aug. 22, 2006, 8 pages.44United States Office Action, U.S. Appl. No. 10/813,907, Dec. 21, 2005, 12 pages.45United States Office Action, U.S. Appl. No. 10/813,907, Nov. 15, 2006,3 pages.46United States Office Action, U.S. Appl. No. 10/814,866, Dec. 26, 2007, 12 pages.47United States Office Action, U.S. Appl. No. 10/814,866, Feb. 3, 2006, 26 pages.48United States Office Action, U.S. Appl. No. 10/814,866, Jul. 16, 2007, 18 pages.49United States Office Action, U.S. Appl. No. 10/814,866, Mar. 5, 2007, 19 pages.50United States Office Action, U.S. Appl. No. 10/814,866, Sep. 20, 2006, 19 pages.51United States Office Action, U.S. Appl. No. 10/814,868, May 3, 2006, 8 pages.52United States Office Action, U.S. Appl. No. 10/839,985, Aug. 25, 2006, 8 pages.53United States Office Action, U.S. Appl. No. 10/839,985, Nov. 29, 2005, 13 pages.54United States Office Action, U.S. Appl. No. 10/936,283, May 3, 2007, 18 pages.55United States Office Action, U.S. Appl. No. 10/936,283, Nov. 8, 2006, 20 pages.56United States Office Action, U.S. Appl. No. 11/016,546, Aug. 6, 2007, 14 pages.57United States Office Action, U.S. Appl. No. 11/016,546, Mar. 12, 2007, 15 pages.58United States Office Action, U.S. Appl. No. 11/237,012, Jun. 28, 2007, 20 pages.59United States Office Action, U.S. Appl. No. 11/237,099, Mar. 9, 2007, 15 pages.60United States Office Action, U.S. Appl. No. 11/237,099, Oct. 2, 2006, 14 pages.61United States Office Action, U.S. Appl. No. 11/731,228, Dec. 11, 2008, 8 pages.62United States Office Action, U.S. Appl. No. 11/731,228, Jul. 14, 2008, 7 pages.63United States Office Action, U.S. Appl. No. 11/865,777, Aug. 3, 2010, 9 pages.64United States Office Action, U.S. Appl. No. 11/865,777, Jan. 14, 2010, 9 pages.65United States Office Action, U.S. Appl. No. 11/865,777, Jun. 24, 2009, 9 pages.66United States Office Action, U.S. Appl. No. 11/865,777, Mar. 31, 2011, 11 pages.67Ususki, T. et al., "Direct Tunneling Memory: Trade-off Between Nonvolatility and High-Endurance with Low Voltage Operations", Nonvolatile Semiconductor Workshop Symposium, Aug. 12, 2001, pp. 80-81.68Vittoz, E., "Dynamic Analog Techniques", Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, Second Edition, Chapter 4, 1994, pp. 97-124.69Witters J.S., et al., "Analysis and Modeling of On-Chip High-Voltage Generator Circuits for Use in EEPROM Circuits", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1372-1380.70Written Opinion for International Application No. PCT/US2005/010431, date of mailing Sep. 2005.Classifications U.S. Classification365/185.01, 365/185.28, 711/103International ClassificationG11C11/34, G11C16/34Cooperative ClassificationG11C11/005, G11C16/0416, G11C2216/10, G11C16/3477, G11C16/0441, G11C2216/26, G11C16/3486, G11C16/3468European ClassificationG11C16/04F4, G11C16/04F1, G11C11/00C, G11C16/34V6Q, G11C16/34V6F, G11C16/34V6Legal EventsDateCodeEventDescriptionOct 8, 2010ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VIRAGE LOGIC CORPORATION;VL C.V.;ARC CORES LIMITED;AND OTHERS;REEL/FRAME:025105/0907Effective date: 20100902Owner name: SYNOPSYS, INC., CALIFORNIAOct 6, 2008ASAssignmentOwner name: VIRAGE LOGIC CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IMPINJ, INC.;REEL/FRAME:021637/0351Effective date: 20080625Owner name: VIRAGE LOGIC CORPORATION,CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IMPINJ, INC.;US-ASSIGNMENT DATABASE UPDATED:20100316;REEL/FRAME:21637/351Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IMPINJ, INC.;US-ASSIGNMENT DATABASE UPDATED:20100329;REEL/FRAME:21637/351Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IMPINJ, INC.;US-ASSIGNMENT DATABASE UPDATED:20100511;REEL/FRAME:21637/351Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IMPINJ, INC.;US-ASSIGNMENT DATABASE UPDATED:20100518;REEL/FRAME:21637/351Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IMPINJ, INC.;US-ASSIGNMENT DATABASE UPDATED:20100525;REEL/FRAME:21637/351Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IMPINJ, INC.;REEL/FRAME:21637/351Sep 4, 2007ASAssignmentOwner name: IMPINJ, INC., WASHINGTONFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PESAVENTO, ALBERTO;REEL/FRAME:019783/0440Effective date: 20070801Owner name: IMPINJ, INC.,WASHINGTONFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PESAVENTO, ALBERTO;US-ASSIGNMENT DATABASE UPDATED:20100329;REEL/FRAME:19783/440RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google