Source: http://www.google.com/patents/US7589660?ie=ISO-8859-1&dq=6233682
Timestamp: 2014-10-22 06:30:55
Document Index: 618063161

Matched Legal Cases: ['Application No. 60', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 11', 'art 16']

Patent US7589660 - Low power analog to digital converter - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA pipelined analog to digital converter comprises N stages, wherein N is an integer greater than one. A sample and integrate circuit communicates with at least two stages of the N stages. The sample and integrate circuit selectively samples a first voltage input to one of the at least two stages while...http://www.google.com/patents/US7589660?utm_source=gb-gplus-sharePatent US7589660 - Low power analog to digital converterAdvanced Patent SearchPublication numberUS7589660 B1Publication typeGrantApplication numberUS 12/217,766Publication dateSep 15, 2009Filing dateJul 8, 2008Priority dateFeb 3, 2006Fee statusPaidAlso published asUS7397412, US7768438Publication number12217766, 217766, US 7589660 B1, US 7589660B1, US-B1-7589660, US7589660 B1, US7589660B1InventorsThomas B. ChoOriginal AssigneeMarvell International Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (25), Non-Patent Citations (14), Referenced by (1), Classifications (6), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetLow power analog to digital converterUS 7589660 B1Abstract A pipelined analog to digital converter comprises N stages, wherein N is an integer greater than one. A sample and integrate circuit communicates with at least two stages of the N stages. The sample and integrate circuit selectively samples a first voltage input to one of the at least two stages while integrating a difference between a sampled second voltage input of another one of the at least two stages and a second reference voltage to generate a second residue. The sample and integrate circuit selectively integrates a difference between the sampled first voltage and a first reference voltage to generate a first residue while sampling a second voltage input.
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 11/486,906, filed Jul. 14, 2006, which claims the benefit of U.S. Provisional Application No. 60/764,985, filed Feb. 3, 2006. The disclosures of the above applications are incorporated herein by reference in their entirety.
FIELD The present disclosure relates to analog to digital converters.
BACKGROUND Reducing power consumption of electronic devices has become increasingly important, particularly for battery powered devices such as laptop computers, personal digital assistants, cellular phones, MP3 players and other devices. Analog-to-digital converters (ADCs) are commonly used in these electronic devices to transform analog signals to digital signals. Relative to other components, ADCs tend to consume a significant amount of power. Therefore, reducing the power consumption of the ADCs is important for reducing the overall power consumption of the system. The ADC may include a pipelined ADC that utilizes multiple stages. Each stage employs a sample and hold circuit that samples an analog input voltage Vin to the pipelined ADC or a residue voltage Vres from a prior stage.
SUMMARY A pipelined analog to digital converter comprises N stages, wherein N is an integer greater than one. A sample and integrate circuit communicates with at least two stages of the N stages and includes a first amplifier that integrates one of the N stages while the sample and integrate circuit samples for another one of the N stages and that integrates for the another one of the N stages while the sample and integrate circuit samples for the one of the N stages.
Referring now to FIG. 2B, the sample and integrate circuit 64-1 performs the functions of the sample circuit 14, the difference circuit 20 and the gain circuit 22, as will be described further below. The sample and integrate circuit 64 samples Vin � A during one cycle and then integrates a difference or residue between Vin � A and Vref � A, which is the output of the D/A module 68 of the first stage 60-1, and outputs the residue signal as Vout � A. In an alternate clock phase the sample and integrate circuit 64-1 samples VinB (in this case, Vin � B=Vout � A since the adjacent stages are used) and then integrates a difference or residue between Vin � B and Vref � B, which is the output of the D/A module 68 of the second stage 60-2, and outputs the residue signal as Vout � B.
A switch 134 selectively connects the capacitor C1 to a voltage Vin � A or to Vref � A. Vref � A is the output of the D/A converter 68 in the first stage. A switch 136 selectively connects the capacitors C3 to a voltage Vin � B or to Vref � B. Vref � B is the output of the D/A converter in the second stage. A switch 138 selectively connects an output of the amplifier 120 to Vout � B or Vout � A since the two stages are adjacent. In this circuit, Vin � B=Vout � A. Switches 140, 142, 144 and 146 selectively ground capacitors C3, C4, C1 and C2, respectively. A switch control module 148 may be used to control the switches in the circuit 100. The state of the switch depends upon phases ΦA and ΦB as indicated in FIG. 3A. Having two separate input stages improves the isolation between even and odd stages since the summing nodes are different.
Referring now to FIGS. 4 and 5, the circuit in FIG. 3A is shown operating in first and second phases. In FIG. 4, the switches are moved into the phase ΦB position. In this position, the upper portion 102 samples an input voltage Vin � A for one stage (such as the first stage 60-1). The lower portion 104 integrates a difference between Vin � B and Vref � B from another stage (such as the second stage 60-2).
In FIG. 5, the circuit of FIG. 3A is shown operating in a second phase. The switches are moved into the phase ΦA position. In this position, the upper portion 102 integrates a difference between Vin � A and Vref � A for the first stage 60-1. The lower portion 104 samples a voltage Vin � B from the second stage 60-2.
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No. 11/486,906, filed Jul. 14, 2006.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8643432 *Jul 27, 2012Feb 4, 2014Hong Kong Applied Science & Technology Research Institute Company Ltd.Op-Amp sharing by swapping trans-conductance cells* Cited by examinerClassifications U.S. Classification341/172International ClassificationH03M1/12Cooperative ClassificationH03M1/123, H03M1/164, H03M1/002European ClassificationH03M1/00PLegal EventsDateCodeEventDescriptionMar 15, 2013FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google