Source: http://www.google.com/patents/US8103858?ie=ISO-8859-1&dq=4316055
Timestamp: 2014-08-28 14:50:07
Document Index: 180420238

Matched Legal Cases: ['application No. 200910139647', 'application No. 102009030525', 'application No. 2009', 'application No. 10', 'application No. 10', 'application No. 2009124710']

Patent US8103858 - Efficient parallel floating point exception handling in a processor - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsMethods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two...http://www.google.com/patents/US8103858?utm_source=gb-gplus-sharePatent US8103858 - Efficient parallel floating point exception handling in a processorAdvanced Patent SearchPublication numberUS8103858 B2Publication typeGrantApplication numberUS 12/217,084Publication dateJan 24, 2012Filing dateJun 30, 2008Priority dateJun 30, 2008Also published asCN101620589A, CN101620589B, DE102009030525A1, US20090327665, US20120084533Publication number12217084, 217084, US 8103858 B2, US 8103858B2, US-B2-8103858, US8103858 B2, US8103858B2InventorsZeev Sperber, Shachar Finkelstein, Gregory Pribush, Arnit Gradstein, Guy Bale, Thierry PonsOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (21), Non-Patent Citations (8), Classifications (9), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetEfficient parallel floating point exception handling in a processorUS 8103858 B2Abstract Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
identifying a numerical exception for a SIMD floating point operation;
initiating a first SIMD micro-operation to generate a first packed partial result for the SIMD floating point operation;
initiating a second SIMD micro-operation to generate a second packed partial result for the SIMD floating point operation, wherein a set of one or more packed source operands used to produce the first and second packed partial results for the SIMD floating point operation are stored in their original representation widths;
initiating a SIMD denormalization micro-operation to combine the first and second packed partial results and to denormalize a first element of the combined first and second packed partial results to generate a third packed result having a denormal element;
storing the third packed result for the SIMD floating point operation; and
setting a flag identifying the denormal element of the third packed result in said first packed partial result.
initiating a SIMD normalization micro-operation on the first packed partial result for the SIMD floating point operation.
3. The method of claim 1, further comprising initiating the second SIMD micro-operation before initiating the first SIMD micro-operation.
4. The method of claim 1, further comprising initiating the third SIMD micro-operation if the SIMD floating point operation is executed at least in part in a SIMD floating point multiplier.
5. The method of claim 4, further comprising not initiating the third SIMD micro-operation if the SIMD floating point operation is executed at least in part in the SIMD floating point multiplier.
a non-transitory machine-accessible storage medium including data and instructions for handling a numerical exception for a single-instruction multiple-data (SIMD) floating point operation such that, when accessed by a machine, causes the machine to:
initiate a first SIMD micro-operation to generate a first packed partial result for the SIMD floating point operation;
initiate a second SIMD micro-operation to generate a second packed partial result for the SIMD floating point operation, wherein a set of one or more packed source operands used to produce the first and second sacked partial results for the SIMD floating point operation are stored in their original representation widths;
initiate a SIMD denormalization micro-operation to combine the first and second packed partial results and to denormalize a first element of the combined first and second packed partial results to generate a third packed result having a denormal element;
store the third packed result for the SIMD floating point operation; and
set a flag identifying the denormal element of the third packed result in said first packed partial result.
7. The article of manufacture of claim 6, the non-transitory machine-accessible storage medium including data and instructions that when accessed by a machine, causes the machine to:
initiate a SIMD normalization micro-operation on the first packed partial result for the SIMD floating point operation.
8. The article of manufacture of claim 6, the non-transitory machine-accessible storage medium including data and instructions that when accessed by a machine, causes the machine to:
initiate the second SIMD micro-operation before initiation of the first SIMD micro-operation.
9. The article of manufacture of claim 6, the non-transitory machine-accessible storage medium including data and instructions that when accessed by a machine, causes the machine to:
initiate the third SIMD micro-operation if the SIMD floating point operation is executed at least in part in a SIMD floating point multiplier.
10. The article of manufacture of claim 6, the non-transitory machine-accessible storage medium including data and instructions that when accessed by a machine, causes the machine to:
not initiate the third SIMD micro-operation if the SIMD floating point operation is not executed at least in part in the SIMD floating point multiplier.
a register file to store a plurality of packed floating point operands and a plurality of packed floating point results for single-instruction multiple-data (SIMD) floating point operations;
an exception generation circuit to identify a numerical exception for a first SIMD floating point operation;
a microcode exception handler, responsive to the numerical exception, to initiate a first SIMD micro-operation to generate a first packed result for the SIMD floating point operation;
the microcode exception handler, further responsive to the numerical exception, to initiate a second SIMD micro-operation to generate a second packed result for the SIMD floating point operation, wherein a set of one or more packed source operands used to produce the first and second packed partial results for the SIMD floating point operation are stored in their original representation widths;
the microcode exception handler, further responsive to the numerical exception, to initiate a SIMD denormalization micro-operation: to combine the first and second packed results, to denormalize an element of the combined first and second packed results, to generate a third packed result having the denormalized element, to store the third packed result for the SIMD floating point operation, and to set a flag identifying the denormalized element of the third packed result in said first packed result.
12. The processor of claim 11, wherein the processor comprises a floating point adder unit to perform single precision and double precision additions, and including exception circuitry to detect denormal elements of operands and results.
13. The processor of claim 11, wherein the processor comprises a floating point multiplication unit to perform single precision and double precision multiplications, and including exception circuitry to detect denormal elements of operands and results.
14. The processor of claim 11, wherein the processor comprises a floating point denormalization unit to perform single precision and double precision denormalization.
a processor including a single-instruction multiple-data (SIMD) floating point execution unit including:
a floating point adder unit to perform single precision and double precision additions, and including exception circuitry to detect denormal elements of operands and results;
a floating point multiplication unit to perform single precision and double precision multiplications, and including exception circuitry to detect denormal elements of operands and results;
a floating point denormalization unit to perform single precision and double precision denormalization; and
a microcode storage to store a plurality of SIMD micro-operations including a first SIMD micro-operation to generate a first packed partial result for a SIMD floating point operation, a second SIMD micro-operation to generate a second packed partial result for the first SIMD floating point operation, wherein the processor is to store a set of one or more packed source operands used to produce the first and second packed partial results for the first SIMD floating point operation in their original representation widths, and a SIMD denormalization micro-operation to combine the first and second packed partial results and to denormalize a first element of the combined first and second packed partial results to generate a third packed result having a denormal element, wherein a flag to identify the denormal element of the third packed result is to be stored with the first packed partial result.
FIELD OF THE DISCLOSURE This disclosure relates generally to the field of microprocessors. In particular, the disclosure relates to efficient techniques for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions.
BACKGROUND OF THE DISCLOSURE The IEEE (Institute of Electrical and Electronics Engineers) standard for floating point arithmetic (IEEE 754) specifies how floating point numbers of single precision (32 bit), double precision (64 bit)), single-extended precision (≧43-bit, not commonly used) and double-extended precision (≧79-bit, usually implemented with 80 bits) are to be represented (including negative zero, denormals, infinities and NaNs, which stands for �not a number�), as well as how arithmetic should be carried out on them. Only 32-bit values are required by the standard; the others are optional. It also specifies four rounding modes and five exceptions (including when the exceptions occur, and what happens when they do occur).
The exponents are biased by (2e−1)−1, where e is the number of bits used for the exponent field. For example, a single precision number has an 8-bit exponent and so its exponent is stored with 27−1=127 added to it, also called �biased with 127.� Normal single precision exponents range between −126 and 127. An exponent of 128 is reserved for plus or minus infinity. An exponent of −127 (all zeroes) is reserved for plus or minus zero (or for denormals, but in the case of denormals the bias used is (2e−1)−2, i.e. 126 not 127, since the most significant bit of the mantissa is presumed to be zero, not one). Some examples of single precision floating point representations are illustrated in Table 1.
DETAILED DESCRIPTION Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and a pair of SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A numerical exception in the context of the following disclosure may be understood to include at least an exception triggered by identifying a denormal input value, or by identifying an underflow condition which could potentially produce a denormal output value as a result, and consequently may require microcode assistance. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags may be set and stored with the packed partial results and/or the packed results to identify the denormal elements.
FIG. 3 illustrates one embodiment of a processor 300 that executes SIMD floating point instructions and uses efficient techniques for handling SIMD floating point exceptions. The in-order front end 301 is the part of the processor 300 that fetches the macro-instructions to be executed and prepares them to be used later in the processor pipeline. The front end 301 of this embodiment includes several units. The instruction prefetcher 326 fetches macro-instructions from memory 220 and/or from I-cache 327 and feeds them to an instruction decoder 328 which in turn decodes them into primitives called micro-instructions or micro-operations (also called micro-ops or uops) that the machine know how to execute. The micro-op cache 330 takes decoded micro-ops and stores them for future re-execution without decoding. Some embodiments of micro-op cache 330 may include a trace cache that assembles micro-ops into program ordered sequences or traces in the micro-op queue 334 for execution. For some embodiments, when decoder 328 or when a trace cache of micro-op cache 330 encounters a complex macro-instruction, the microcode ROM 344 may provide the micro-ops needed to complete the operation.
Thus a microcode assist mechanism as described above may utilize the microcode ROM 344 to transparently handle SIMD floating point exceptions.
FIG. 4 illustrates one alternative embodiment of an apparatus 460 for efficiently handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. The apparatus 460 includes the register file bypass network 308 operatively coupled with floating point execution unit 316. One embodiment of SIMD floating point execution unit 316 includes SIMD floating point adder unit (FAU) 400 and SIMD floating point multiplication unit (FMU) 420. Embodiments of includes SIMD FAU 400 and/or SIMD FMU 420 SIMD may also include floating point normalization unit (FNU) 410 and SIMD floating point denormalization unit (FDU) 430.
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