Source: http://www.google.com/patents/US7737042?dq=6985872
Timestamp: 2015-03-06 20:30:54
Document Index: 593787483

Matched Legal Cases: ['art 500', 'art 500', 'art 500', 'art 500', 'art 500', 'art 800', 'art 800', 'art 800']

Patent US7737042 - Pulsed-plasma system for etching semiconductor structures - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to...http://www.google.com/patents/US7737042?utm_source=gb-gplus-sharePatent US7737042 - Pulsed-plasma system for etching semiconductor structuresAdvanced Patent SearchPublication numberUS7737042 B2Publication typeGrantApplication numberUS 11/678,041Publication dateJun 15, 2010Filing dateFeb 22, 2007Priority dateFeb 22, 2007Fee statusPaidAlso published asUS20080206900Publication number11678041, 678041, US 7737042 B2, US 7737042B2, US-B2-7737042, US7737042 B2, US7737042B2InventorsTae Won Kim, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. DeshmukhOriginal AssigneeApplied Materials, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (21), Non-Patent Citations (12), Referenced by (1), Classifications (13), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetPulsed-plasma system for etching semiconductor structures
US 7737042 B2Abstract
A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
1. A method for etching a sample, comprising:
removing a first portion of said sample by applying a continuous plasma process, the first portion having a first composition;
removing a second portion of said sample by applying a pulsed plasma process, the second portion having a second composition different from the first composition, wherein said pulsed plasma process comprises a plurality of duty cycles, and wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma.
2. The method of claim 1 wherein the duration of each duty cycle is in the range of 5 micro-seconds-1 second.
3. The method of claim 1 wherein terminating said continuous etch process comprises terminating at a pre-determined time based on characteristics of said sample.
removing a third portion of said sample by applying a second continuous plasma process, the third portion having a composition different from the second composition;
removing a fourth portion of said sample, the fourth portion having a composition different from the composition of the third portion, by applying a second pulsed plasma process, wherein said second pulsed plasma process comprises a second plurality of duty cycles, and wherein each duty cycle represents the combination of a second ON state and a second OFF state of a second plasma.
5. The method of claim 1 wherein the portion of each duty cycle comprised of said ON state is in the range of 5-95%.
6. The method of claim 5 wherein the frequency of said plurality of duty cycles is in the range of 1 Hz-200 kHz.
7. The method of claim 1 wherein terminating said continuous etch process comprises detecting an end point.
8. The method of claim 7 wherein said end point is determined by the real-time composition of a set of chemical species generated during said continuous etch process.
9. The method of claim 7 wherein said end point is determined by the real-time film thickness measurement by interferometry. Description
FIGS. 4A-C illustrate cross-sectional views representing the effects of a significant reduction in micro-loading during a pulsed etch process conducted on a semiconductor stack, in accordance with an embodiment of the present invention.
FIG. 5A is a flowchart and FIG. 5B is a waveform, both representing a series of steps in a pulsed plasma process, in accordance with an embodiment of the present invention.
FIGS. 7A-C illustrate cross-sectional views representing a continuous/pulsed plasma etch process performed on a semiconductor stack, in accordance with an embodiment of the present invention.
FIG. 8 is a flowchart representing a series of steps in a pulsed plasma process, in accordance with an embodiment of the present invention.
FIGS. 9A-D illustrate cross-sectional views representing the steps of the flowchart from FIG. 8 performed on a more complex semiconductor stack, in accordance with an embodiment of the present invention.
FIG. 10 illustrates a system in which a pulsed plasma process is conducted, in accordance with an embodiment of the present invention.
FIGS. 12A-B illustrate the chamber from the system of FIG. 10 in a plasma ON/bias OFF state and a plasma ON/bias ON state, respectively, in accordance with an embodiment of the present invention.
Disclosed herein are a pulsed plasma method and a corresponding system for etching semiconductor structures. A portion of a sample may be removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. In accordance with an embodiment of the present invention, the ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In a specific embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
A semiconductor stack may be etched by a pulsed plasma etch process. FIGS. 4A-C illustrate cross-sectional views representing the effects of a significant reduction in micro-loading during a pulsed etch process conducted on a semiconductor stack, in accordance with an embodiment of the present invention.
Referring to FIG. 4B, the pattern of mask 406 is etched into etch layer 404 with a pulsed plasma etch process to form partially patterned etch layer 414. Under the appropriate conditions, and in accordance with an embodiment of the present invention, the etch rate of all density regions 408, 410 and 412 are substantially similar when a pulsed plasma process is employed, as depicted in FIG. 4B. The pulsed plasma process contains a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of the etching plasma. A duty cycle may be comprised of one ON state and one OFF state, wherein the durations of the ON state and OFF state are suitable to transfer the pattern of mask 406 into etch layer 404 at a substantially similar etch rate for density regions 408, 410 and 412. In accordance with an embodiment of the present invention, the portion of each duty cycle comprised of said ON state is in the range of 5-95% of the duty cycle. In a specific embodiment, the portion of each duty cycle comprised of said ON state is in the range of 65-75% of the duty cycle. In another embodiment, the frequency of a plurality of duty cycles is in the range of 1 Hz-200 kHz, i.e. each duty cycle has a duration in the range of 5 micro-seconds-1 second. In a specific embodiment, the frequency of a plurality of duty cycles is 50 kHz and the portion of each duty cycle comprised of said ON state is 70%.
The method of generating a plasma for use in the pulsed plasma process for etching etch layer 404 may comprise any method suitable to strike and maintain the plasma for a duration sufficient to satisfy the duration of the ON state in a duty cycle. For example, in accordance with an embodiment of the present invention, the method of generating the plasma comprises generating a plasma selected from the group consisting of an electron cyclotron resonance (ECS) plasma, a helicon wave plasma, an inductively coupled plasma (ICP) and a surface wave plasma. In a specific embodiment, the method of generating the plasma comprises generating an inductively coupled plasma in an Applied Materials� AdvantEdge G3 etcher.
The plasma generated for the pulsed plasma etch process may be comprised of any reaction gas suitable to generate ions and reactive radicals to remove portions of etch layer 404 without detrimentally impacting the pattern of mask 406. For example, in accordance with an embodiment of the present invention, the reaction gas is comprised of a halide species and is used to etch a silicon-based material. In a specific embodiment, the reaction gas is comprised of the species HBr, He and a 70%/30% He/O2 mixture in the approximate ratio of 300:50:12, respectively, and the pulsed plasma is used to etch amorphous silicon, poly-silicon or single-crystal silicon. In another embodiment, the reaction gas is comprised of a fluorocarbon species and is used to etch a dielectric layer. In a specific embodiment, the reaction gas is comprised of the species CF4 and the pulsed plasma is used to etch silicon dioxide or carbon-doped silicon oxide. The reaction gas may have a pressure suitable to provide a controlled etch rate. In an embodiment, the pressure is in the range of 1-100 mTorr. In another embodiment, the pressure is in the range of 3-100 mTorr. In a specific embodiment, the reaction gas is comprised of HBr, He and O2, the pressure of the reaction gas is in the range of 30-50 mTorr and the etch rate of poly-silicon is in the range of 500-6000 Angstroms/minute.
Referring to FIG. 4C, the pulsed plasma process described above is continued until partially patterned etch layer 414 becomes patterned etch layer 424. By using the pulsed plasma etch process described above through to completion of the etching of etch layer 404, the etch process is completed at density regions 408, 410 and 412 at substantially the same time. Thus, only a negligible amount of over-etching may be required in order to form patterned etch layer 424. As such, detrimental undercutting of the various structures of patterned etch layer 424 may be significantly mitigated, as depicted by the lack of undercut in FIG. 4C.
The duration of the ON state and the OFF state in a duty cycle of a pulsed plasma etch process may be targeted to correspond with the formation and removal of etch by-products. FIG. 5A is a flowchart and FIG. 5B is a waveform, both representing a series of such targeted steps in a pulsed plasma process, in accordance with an embodiment of the present invention. FIGS. 6A-D illustrate cross-sectional views representing the steps of the flowchart from FIG. 5A as performed on a semiconductor stack.
Referring to step 502 of flowchart 500 and corresponding FIG. 6A, a semiconductor stack 600 comprises a substrate 602, an etch layer 604 and a mask 606 at the start of a pulsed plasma etching process. Mask 606 is patterned with a low density region 608, a medium density region 610 and a high density region 612. Substrate 602, etch layer 604 and mask 606 may be comprised of any materials described in association with substrate 402, etch layer 404 and mask 406, respectively, from FIG. 4A. Semiconductor stack 600 may comprise a stack of greater complexity of material layers and/or pattern types, but is depicted in the manner shown herein for illustrative purposes.
Referring to step 504 of flowchart 500 and corresponding FIG. 6B, the pattern of mask 606 is partially etched into etch layer 604 during the ON state of a duty cycle in a pulsed plasma etch process to form partially patterned etch layer 614A. Unmasked portions of etch layer 604 are accessible by plasma etching species 620 while masked portions of etch layer 604, covered by mask 606, are protected from plasma etching species 620, as depicted in FIG. 6B. Etch by-products 616 are generated within reaction region 618 of semiconductor stack 600.
Etching species 620 may be comprised of any charged species and reactive neutrals ejected from the plasma used in a pulsed plasma etch process. For example, in accordance with an embodiment of the present invention, etching species 620 are comprised of positively charged ions and radicals. In one embodiment, the reaction gas is comprised of HBr, He and O2 and the etching species 620 are selected from the group consisting of H+, Br+, He+, O+, H, Br and O. In another embodiment, the reaction gas is comprised of a fluorocarbon and the etching species 620 are selected from the group consisting of F+, CF+, CF2 +, CF3 +, F, CF, CF2 and CF3. Etch by-products 616 may be comprised of any combination of atoms from etch layer 604 and etching species 620. In a specific embodiment, etching species 620 are comprised of a halide cation X+ and/or a halide radical X (X=F, Cl, Br), etch layer 604 is comprised of silicon atoms, and etch by-products 620 are comprised of by-products selected from the group consisting of the neutral species SiXn, where n is 1, 2, 3 or 4.
The duration of the ON state of a duty cycle may be selected to maximize etch efficiency while maintaining a substantially similar etch rate for all density regions 608, 610 and 612 of partially patterned etch layer 614A. As depicted in FIG. 6B, etch by-products 616 are formed and reside, at least for a time, among the partially etched features of partially patterned etch layer 614A, i.e. within reaction region 618. Reaction region 618 is a region adjacent semiconductor stack 600 within which etch by-products 616 that are formed may interfere with plasma etching species 620. That is, as the amount of etch by-products 616 increases within reaction region 618 throughout the lifetime of an ON cycle, plasma etching species 620 may be hindered from accessing unmasked portions of partially patterned etch layer 604. Such hindering of plasma etching species 620 may be more severe in high structure density regions as compared to low structure density regions, slowing the etch rate in the high density regions as compared with the etch rate of the low density regions. Thus, in accordance with an embodiment of the present invention, the ON state of a duty cycle in a pulsed plasma etch process is selected to be less than or, at most, correspond with the time at which a sufficient amount of etch by-products are generated to slow the etch rate of a high density region versus the etch rate of a low density region. In one embodiment, the duration of the ON state is selected to substantially match the time at which the etch rate of the partially patterned etch layer 614A becomes dependent on the density of the pattern of mask 606. In another embodiment, the ON state is of a sufficiently short duration to substantially inhibit micro-loading within reaction region 618. In an embodiment, the duration of the ON state is within any of the ranges described for the ON state of the duty cycle discussed in association with FIG. 4B.
Referring to step 506 of flowchart 500 and corresponding FIG. 6C, the plasma is in an OFF state and, thus, etching species 620 are no longer present in reaction region 618 of semiconductor stack 600. As depicted in FIG. 6C, etch by-products 616 are removed from reaction region 618.
At the initiation of the OFF state of the duty cycle, the concentration of by-products 618 may be substantially greater inside reaction region 618 than outside of reaction region 618. Thus, a natural diffusion gradient may form and etch by-products 616 may diffuse outside of reaction region 618. This process may be enhanced by an additional pressure gradient. That is, along with a build-up in etch by-products 616 during the ON state, the pressure within reaction region 618 may become greater than the pressure outside of reaction region 618, enhancing the extrusion of etch by-products 616. Thus, in accordance with an embodiment of the present invention, the OFF state of a duty cycle in a pulsed plasma etch process is selected to be of a sufficiently long duration to substantially enable removal of a set of etch by-products 616 from reaction region 618. In another embodiment, the quantity of etch by-products 616 removed is sufficient such that any etch by-products that remain with reaction region 618 do not substantially interfere with etching species during an ON state of a subsequent duty cycle. In one such embodiment, the duration of the OFF state is selected to substantially match the time at which more than 50% of the etch by-products 616 have been removed from reaction region 618. In another embodiment, the duration of the OFF state is selected to substantially match the time at which more than 75% of the etch by-products 616 have been removed from reaction region 618. In an alternative embodiment, the duration of the OFF state is within any of the ranges described for the OFF state of the duty cycle discussed in association with FIG. 4B. In an embodiment, an inert gas such as Ar or He is injected during the OFF state to enhance the by-product removal.
Referring to step 508 of flowchart 500 and corresponding FIGS. 6D-E, the pattern of mask 606 is continued to be etched into etch layer 604 during subsequent duty cycles of a pulsed plasma etch process, forming more extensively etched partially patterned etch layer 614B. The duty cycles (i.e. step 508) may be repeated until a desired amount of etch layer 604 has been etched. Thus, in accordance with an embodiment of the present invention, a portion of etch layer 604 is removed with a pulsed plasma etch process comprising a plurality of duty cycles. FIG. 5B illustrates the timeline of a duty cycle, as represented in a waveform.
Referring to step 510 of flowchart 500 and corresponding FIG. 6F, the pulsed plasma etch process is terminated following removal of a desired quantity of etch layer 604. By using the pulsed plasma etch process described above through to completion of the etching of etch layer 604, the etch process is completed at density regions 608, 610 and 612 at substantially the same time. Thus, only a negligible amount of over-etching may be required in order to form patterned etch layer 624. As such, detrimental undercutting of the various structures of patterned etch layer 624 may be significantly mitigated, as depicted by the lack of undercut in FIG. 6F. The determination of when to terminate the pulsed plasma process may be made by any suitable factor. For example, in accordance with an embodiment of the present invention, the termination of the pulsed plasma etch process is determined by ending the repetition of duty cycles at a predetermined time. In an alternative embodiment, the termination of the pulsed plasma etch process is determined by detecting a change in etch by-products 612 at the completion of the etching of etch layer 604 and the corresponding exposure of the top surface of substrate 602. In another embodiment, the termination of the pulsed plasma etch process is determined by measuring the depth of a trench using an interferometric technique.
A pulsed plasma etch process may be combined with a continuous plasma etch process. For example, it may be the case that a differential in etch rate for differing density regions of a semiconductor stack may not be significant until a portion of the semiconductor stack has already been etched, since the etch process may suffer from more severe micro-loading with increased aspect ratio of a pattern. As such, it may be more efficient to apply a continuous plasma for etching the first portion of a semiconductor stack, until a particular depth has been reached, and then to apply a pulsed plasma etch process to remove a second portion of the semiconductor stack. In accordance with an embodiment of the present invention, a semiconductor stack is etched with a continuous plasma etch process until a desired depth has been reached. The etching of the semiconductor stack is then completed by utilizing a pulsed plasma etch process. In one embodiment, a continuous/pulsed plasma etch process is utilized to increase the throughput of wafers in a single-wafer processing tool. This continuous/pulsed plasma etch process is illustrated in FIGS. 7A-C, in accordance with an embodiment of the present invention. Etch layer 704 patterned with mask 712 (FIG. 7A) is partially patterned with a continuous plasma etch process (FIG. 7B). A pulsed plasma etch process is subsequently employed to complete etching etch layer 704, i.e. until the etch stops on etch-stop layer 706, as depicted in FIG. 7C. In an embodiment, the depth at which the plasma etch process is changed from continuous to pulsed is selected as being in the range of 0.5-4 times the spacing width of the region of highest structure density. In one embodiment, the depth at which the plasma etch process is changed from continuous to pulsed is selected as being substantially equal to the spacing width of the region of highest structure density, i.e. when an aspect ratio of 1 has been achieved among the highest density structures.
FIG. 8 is a flowchart representing a series of steps combining a continuous plasma etch process with a subsequent pulsed plasma etch process, in accordance with an embodiment of the present invention. FIGS. 9A-D illustrate cross-sectional views representing the steps of the flowchart from FIG. 8 as performed on a more complex semiconductor stack.
Referring to step 802 of flowchart 800 and corresponding FIG. 9A, a semiconductor stack 900 comprises a substrate 902, two etch layers 904 and 908, two dielectric layers 906 and 810 and a mask 912 at the start of a continuous/pulsed plasma etching process. Substrate 902, etch layers 904 and 908 and mask 912 may be comprised of any materials described in association with substrate 402, etch layer 404 and mask 406, respectively, from FIG. 4A. Semiconductor stack 900 may comprise a stack of greater or lesser complexity of material layers, but is depicted in the manner shown herein for illustrative purposes. In one embodiment, semiconductor stack 900 is comprised of poly-silicon/SiON/poly-silicon/SiO2, as is found in a typical Flash memory stack.
Referring to steps 808, 810 and 812 of flowchart 800 and corresponding FIGS. 9C-D, the pattern of mask 912 is continued to be etched into semiconductor stack 900. At this point, because a first portion of semiconductor stack 900 has already been etched, a differential in etch rate for differing density regions of etch layer 908 may be significant, requiring the application of a pulsed plasma etch process. Thus, in accordance with an embodiment of the present invention, a pulsed plasma etch process is utilized to pattern semiconductor layer 908 to form patterned semiconductor layer 918. The duty cycles (i.e. step 812) may be repeated until a desired amount of etch layer 908 has been etched. Thus, in accordance with an embodiment of the present invention, a first portion of semiconductor stack 900 is patterned with a continuous etch plasma process and a second portion of semiconductor stack 900 is patterned with a pulsed plasma etch process comprising a plurality of duty cycles.
Referring to step 814 of flowchart 800 and corresponding FIG. 9D, the pulsed plasma etch process is terminated following removal of a desired quantity of etch layer 908. By using the pulsed plasma etch process described above through to completion of the etching of semiconductor layer 908, the etch process is completed at various density regions at substantially the same time. Thus, only a negligible amount of over-etching may be required in order to form patterned etch layer 918. As such, detrimental undercutting of the various structures of patterned etch layer 918 may be significantly mitigated, as depicted by the lack of undercut in FIG. 9D. The determination of when to terminate the pulsed plasma process may be made by any suitable factor. For example, in accordance with an embodiment of the present invention, the termination of the pulsed plasma etch process is determined by ending the repetition of duty cycles at a predetermined time. In an alternative embodiment, the termination of the pulsed plasma etch process is determined by detecting a change in etch by-products at the completion of the etching of etch layer 908 and the corresponding exposure of the top surface of dielectric layer 910.
The approach of combining continuous and pulsed plasma etch processes, as described above, may be extended by applying cyclic continuous/pulsed plasma etch processes. For example, in accordance with an embodiment of the present invention, a first portion of a semiconductor stack is patterned with a first continuous plasma etch process, a second portion of the semiconductor stack is patterned with a first pulsed plasma etch process, a third portion of the semiconductor stack is patterned with a second continuous etch process, and a fourth portion of the semiconductor stack is patterned with a second pulsed plasma etch process. In a specific embodiment, etch layer 904 of semiconductor stack 900 is also patterned with a first continuous plasma etch process followed by a first pulsed plasma etch process. Etch layer 908 is then patterned with a second continuous plasma etch process followed by a second pulsed plasma etch process.
A pulsed plasma etch process may be conducted in any processing equipment suitable to provide an etch plasma in proximity to a sample for etching. FIG. 10 illustrates a system in which a pulsed plasma etch process is conducted, in accordance with an embodiment of the present invention.
Referring to FIG. 10, a system 1000 for conducting a pulsed plasma etch process comprises a chamber 1002 equipped with a sample holder 1004. An evacuation device 1006, a gas inlet device 1008 and a plasma ignition device 1010 are coupled with chamber 1002. A computing device 1012 is coupled with plasma ignition device 1010. System 1000 may additionally include a voltage source 1014 coupled with sample holder 1004 and a detector 1016 coupled with chamber 1002. Computing device 1012 may also be coupled with evacuation device 1006, gas inlet device 1008, voltage source 1014 and detector 1016, as depicted in FIG. 10.
Computing device 1012 comprises a processor and a memory. In accordance with an embodiment of the present invention, the memory of computing device 1012 includes a set of instructions for controlling plasma ignition device 1010 to switch between an ON state and an OFF state of a plasma in a pulsed plasma etch process. In an embodiment, the set of instructions contains machine operable code capable of effecting a plurality of duty cycles, wherein each duty cycle represents the combination of one ON state and one OFF state of the plasma. In a specific embodiment, the set of instructions for controlling plasma ignition device 1010 includes timing instructions for each duty cycle to have an ON state in the range of 5-95% of the duration of the duty cycle. In an embodiment, the set of instructions for controlling plasma ignition device 1010 includes timing instructions for each duty cycle to have an ON state in the range of 65-75% of the duration of the duty cycle. In another embodiment, the set of instructions for controlling plasma ignition device 1010 includes timing instructions such that the frequency of a plurality of duty cycles is in the range of 1 Hz-200 kHz, i.e. each duty cycle has a duration in the range of 5 micro-seconds-1 second. In a specific embodiment, the set of instructions for controlling plasma ignition device 1010 includes timing instructions such that the frequency of a plurality of duty cycles is 50 kHz and the portion of each duty cycle comprised of said ON state is 70%.
During the ON state of a duty cycle in a pulsed plasma etch process, positive charge may be imparted to the sample being etched. In some instances, the positive charge of the sample may be substantial enough to partially deflect the positively charged etch species ejected from a plasma. Such deflection of the etching species may result in detrimental undercut of features being etched into a particular sample. By biasing the sample with a negative charge during the etching process, the deflection of positively charged particles may be mitigated.
FIGS. 12A-B illustrate chamber 1002 from system 1000 of FIG. 10 in a plasma ON/bias OFF state and a plasma ON/bias ON state, respectively, in accordance with an embodiment of the present invention. A voltage source 1014 is coupled with sample holder 1004 and may be used to bias sample holder 1004, and hence sample 1102, during an etch process. Referring to FIG. 12A, voltage source 1014 is in an OFF state and positively charged etch species ejected from plasma 1100 are partially deflected near the surface of sample 1102. However, referring to FIG. 12B, voltage source 1014 is in an ON state (i.e. negatively biasing sample holder 1004) and, thus, positively charged etch species ejected from plasma 1100 are held to an orthogonal trajectory (i.e. anisotropic trajectory) near the surface of sample 1102. In accordance with an embodiment of the present invention, voltage source 1014 is used to apply a negative bias to sample holder 1004 in the range of 100-200 Watts. A pulsed plasma etch process (as compared with a continuous plasma etch process) may reduce the extent of positive charge build-up on sample 1102 during an etch process. However, the additional step of biasing sample holder 1004 with voltage source 1014 may still be utilized as part of the pulsed plasma etch process in order to optimize the mitigation of undercutting of structures during the etch process. Therefore, in accordance with another embodiment of the present invention, the additional step of biasing sample holder 1004 with voltage source 1014 is used to extend the duration of the ON state of a duty cycle in a pulsed plasma etch process.
Thus, a pulsed plasma system for etching semiconductor structures has been disclosed. In one embodiment, a portion of a sample is removed by applying a pulsed plasma etch process, wherein the pulsed plasma etch process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process.
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