Source: https://patents.google.com/patent/US8913413B2/en
Timestamp: 2019-12-08 00:45:19
Document Index: 799813495

Matched Legal Cases: ['Application No. 61', 'Application No. 200980139725', 'Application No. 2011', 'Application No. 098126194', 'Application No. 09793151', 'Application No. 2011', 'Application No. 200980139725', 'Application No. 2011', 'Application No. 200980133212', 'Application No. 098126194', 'Application No. 2011', 'Application No. 200980139725', 'Application No. 200980133212', 'Application No. 2009801332124', 'Application No. 200980133212', 'Application No. 098126194', 'Application No. 09790573', 'Application No. 09737244']

US8913413B2 - Memory system with sectional data lines - Google Patents
US8913413B2
US8913413B2 US13/362,311 US201213362311A US8913413B2 US 8913413 B2 US8913413 B2 US 8913413B2 US 201213362311 A US201213362311 A US 201213362311A US 8913413 B2 US8913413 B2 US 8913413B2
US13/362,311
US20120170346A1 (en
2012-01-31 Application filed by SanDisk 3D LLC filed Critical SanDisk 3D LLC
2012-01-31 Priority to US13/362,311 priority patent/US8913413B2/en
2012-03-05 Assigned to SANDISK 3D LLC reassignment SANDISK 3D LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FASOLI, LUCA, YAN, TIANHONG
2012-07-05 Publication of US20120170346A1 publication Critical patent/US20120170346A1/en
2014-12-16 Publication of US8913413B2 publication Critical patent/US8913413B2/en
230000002441 reversible Effects 0 description 14
The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
This application is a divisional application of U.S. patent application Ser. No. 12/410,648, “Memory System with Sectional Data Lines,” by Yan, et al., filed on Mar. 25, 2009, which claims the benefit of U.S. Provisional Application No. 61/091,720, “Memory System With Sectional Data Line,” by Yan, et al., filed on Aug. 25, 2008, both of which are incorporated herein by reference in their entirety.
This application is related to U.S. patent application Ser. No. 13/362,320, “Memory System with Sectional Data Lines,” by Yan, et al., filed the same day as the present application, and U.S. patent application Ser. No. 13/079,613, “Memory System with Sectional Data Lines,” by Yan, et al., filed on Apr. 4, 2011, both of which are incorporated herein by reference in their entirety.
In one embodiment, all of the components depicted in FIG. 1 are arranged on a single integrated circuit. For example, system control logic 130, column control circuitry 110 and row control circuitry 120 are formed on the surface of a substrate and memory array 102 is a monolithic three-dimensional memory array formed above the substrate (and, therefore, above system control logic 130, column control circuitry 110 and row control circuitry 120). In some cases, a portion of the control circuitry can be formed on the same layers as some of the memory array. More information about suitable embodiments like that of FIG. 1 can be found in the following United States patents that are incorporated herein by reference in their entirety: U.S. Pat. No. 6,879,505; U.S. Pat. No. 7,286,439; U.S. Pat. No. 6,856,572; and U.S. Pat. No. 7,359,279.
In one embodiment, the memory cells 200 may be such that they can be programmed once and read many times. One example memory cell includes a pillar of layers formed at the intersection between the upper and lower conductors. In one embodiment, the pillar includes a steering element, such as a diode, that is connected in series with a state change element, such as an antifuse layer. When the antifuse layer is intact, the cell is electrically an open circuit. When the antifuse layer is breached, the cell is electrically a diode in series with the resistance of the breached antifuse layer. Examples of memory cells can be found in U.S. Pat. No. 6,034,882; U.S. Pat. No. 6,525,953; U.S. Pat. No. 6,952,043; U.S. Pat. No. 6,420,215; U.S. Pat. No. 6,951,780; and U.S. Pat. No. 7,081,377.
As mentioned above, FIG. 2 shows a portion of a monolithic three-dimensional memory array. As can be seen, the bit lines 206 and 210 are arranged in a first direction and the word lines 208 are arranged in a second direction perpendicular to the bit lines. In a memory array with additional layers of memory cells, there would be additional layers of bit lines and word lines. The supporting circuitry (e.g., column control circuitry 110, row control circuitry 120, and system control logic 130) are arranged on the surface of the substrate with the memory array fabricated above the supporting circuitry. FIG. 3, which depicts various layers of an integrated circuit, shows the Memory Array positioned above the Substrate. The Memory Array includes bit line layers BL0, BL1 and BL2, and word line layers WL0 and WL1. In other embodiments, additional bit line and word line layers can also be implemented. An integrated circuit implementing a semiconductor memory system also includes multiple metal layers used for routing signals between different components of the support circuitry, and between the supporting circuitry and the bit lines and word lines. These metal layers are arranged above the support circuitry that is implemented on the surface of the Substrate and below the Memory Array. FIG. 3 shows two metal layers R1 and R2 used for routing; however, other embodiments can include more or less than two metal layers. In one example, these metal layers R1 and R2 are formed of Tungsten (about 1.5 ohm/squre), which has both a relatively high resistance and high capacitance.
Positioned above the memory array can be one or more metal layers used for routing signals between different components of the memory system. FIG. 3 shows one such metal layer above the memory array, labeled as the Top Metal layer. In one example, the top metal layer is formed of aluminum or copper (about 0.05 ohm/squre), which has a smaller resistance and capacitance than layers R1 and R2. Metals layers R1 and R2 are not implemented using the same materials as used for the Top Metal because the metal used for R1 and R2 needs to withstand the processing steps for fabricating the memory array on top of R1 and R2.
In the embodiment of FIG. 6, each block has its own set of local data lines. For example, block 0 includes SELB0<31:0>, block 1 includes SELB1<31:0>, . . . block 15 includes SELB15<31:0>. The local data lines SELB0<31:0>, SELB1<31:0>, . . . SELB15<31:0> are implemented in metal layer R1 under their respective block, and only run the width of the respective block. Selection circuits 300 for a particular column are used to selectively connect the 32 bit lines for that same column to 32 respective local data lines (SELB0<31:0>, SELB1<31:0>, . . . or SELB15<31:0>). As can be seen from FIG. 6, each of the selection circuits 300 receives a selection signal CD from column decoders 112 and a bit line connection from one of the 32 bit lines associated with the column. Based on the selection input from column decoder 112, the selection circuit 300 will connect or disconnect the bit line to a respective one of the local data lines (e.g., SELB0<31:0>, SELB1<31:0>, SELB15<31:0>).
For some embodiments of two-terminal re-writable memories, the sense amplifier is sensing the selected memory cell during read operations by biasing the selected bit line to a higher voltage (e.g., 1.5v). The selected word line is biased to lower voltage (e.g., 0v). To avoid sensing leakage current from the selected bit line to many unselected word-lines, the unselected word lines are biased at the same voltage as the selected bit-lines (e.g., 1.5v). To avoid leakage current from the unselected bit lines to the selected word line, the unselected bit lines can be biased at the same voltage as selected bit-lines (e.g. 0v).
In program operations (SET/RESET/FORM), the memory array is also forward biased, which is similar to a read operation. The main difference is the voltage range. The selected bit line is required to be biased at the highest voltage: VWR (e.g., 8v in “FORM”). The selected word-line is at VSS. All unselected bit lines are biased at VUB (e.g., 0.7v). All un-selected word-line are biased at VUX (e.g., 7.5v in “FORM”). The voltage range for SET and RESET operations is 2-5 volts. In an embodiment that uses reversible resistance-switching material in a data storage element, the SET operation puts the reversible resistance-switching material in a low resistance state, the RESET operation puts the reversible resistance-switching material in a high resistance state, and the FORM operation is the first SET operation (which requires a higher voltage than subsequent SET operations). Other schemes can also be used.
In order to reduce the maximum voltage requirement for the on-chip charge pumps, the bit line driver circuits are designed to pass selected bit line voltages through a PMOS transistor, as depicted in FIG. 7 (see transistor 584). It is proposed that the voltage driven during a read operation be lower than in the past. This creates an issue because the PMOS transistor (e.g., transistor 584 of FIG. 7) at the selected bit line driver (e.g. selection circuit) cannot deliver enough READ current (e.g. 1 uA) with the gate biased at VSS (0v). Another disadvantage of connecting the local data lines to the selected bit-line is the noise of N-well biased voltage (VUX) coupling to the sense amplifier output node. There is more than 4K of unselected bit-line drivers, which may couple enough noise (from VUX) to the sense amplifier output to cause a sensing error during read operations. This coupling happens through the parasitic capacitance of the bit line driver.
An extra NMOS transistor 324 is added to the selection circuit 310 between the bit line and the unselected bit line voltage. The gate signal XCSEL of transistor 324 is the reverse logic of PMOS transistor 320 during a read operation. In the selection circuit 310 for the selected bit line, CSEL (gate of transistors 320 and 322) is high (e.g., 3.5 v) and the sense amplifier output (SELBN) is connected to the selected bit line through NMOS transistor 322. In a selection circuit 310 for an unselected bit line, CSEL is low (e.g., 0v) and XCEL is high; therefore, the unselected voltage power (VUB=0v) can be delivered to the unselected bit line though NMOS transistor 324.
During program operations, the maximum voltage (e.g., 2-8 v) should be able to be passed to the selected bit line. The sense amplifier output is connected to the source of the PMOS transistor 320 (labeled SELB). When the selection circuit 310 is selected (CSEL=VSS), the sense amplifier output voltage VWR (e.g., 6 volts) is applied on the selected bit line through the PMOS transistor 320. If the bit line is unselected (CSL=VWR) the bit line is pulled down (to approximately 0.7 volts) through NMOS transistor 322 with CSEL at 6v and XCSEL at 6v.
NAND gate 404 receives MAD[1], READ and XDIS and provides an output to transistor 428, transistor 430 and inverter 462. The output of inverter 462 is provided to transistor 434. Transistor 428 is also connected to GSELB[i] and SELBN[j]. Transistor 430 is also connected to SELBN[j] and transistor 432. Transistor 432 is also connected to VUB and XDIS. Transistor 434 is also connected to SELBN[j] and GSELB[i].
NAND gate 408 receives MAD[1], XREAD and XDIS and provides an output to transistor 444, transistor 446 and inverter 466. The output of inverter 466 is provided to transistor 450. Transistor 444 is also connected to GSELB[i] and SELB[j]. Transistor 446 is also connected to SELB[j] and transistor 448. Transistor 448 is also connected to VUB and XDIS. Transistor 450 is also connected to SELBN[i] and GSELB[i].
a plurality of non-volatile storage elements arranged in groups;
multiple sets of first local data lines, each group includes its own set of first local data lines;
multiple sets of second local data lines, each group includes its own set of second local data lines;
each set of first local data lines and each set of second local data lines being respectively outside the plurality of non-volatile storage elements for its respective group;
a set of global data lines outside the plurality of non-volatile storage elements arranged in groups;
first selection circuits, each group includes a different subset of the first selection circuits for selectively electrically connecting a subset of the bit lines to first local data lines for the respective group or second local data lines for the respective group;
second selection circuits, the second selection circuits selectively electrically connect a subset of the set of first local data lines for the respective group or a subset of the set of second local data lines for the respective group to the global data lines; and
control circuits in communication with the global data lines.
the plurality of non-volatile storage elements is a three-dimensional memory array that includes multiple layers of memory cells;
the control circuits comprise column control circuitry that includes sense amplifiers;
the first selection circuits include pmos transistors connected to nmos transistors;
the second selection circuits includes 2:1 multiplexers; and
the groups are blocks of memory cells that share a common set of sense amplifiers.
the second selection circuits are 4:1 multiplexers.
the first local data lines are positioned in at least one metal layer below the plurality of non-volatile storage elements; and
the global data lines are positioned in at least one metal layer above the plurality of non-volatile storage elements.
5. The non-volatile storage device of claim 1, further comprising:
a substrate, the control circuits in communication with the global data lines, being positioned on the substrate.
6. The non-volatile storage device of claim 5, further comprising:
the sets of first local data lines and the sets of second local data lines being positioned between the substrate and the non-volatile storage elements.
7. The non-volatile storage device of claim 1, further comprising:
the global data lines are positioned outside of the plurality of non-volatile storage elements arranged in groups.
8. The non-volatile storage device of claim 1 further comprising:
the non-volatile storage elements are arranged in three-dimensions.
9. The non-volatile storage device of claim 1 further comprising:
the non-volatile storage elements are arranged in a monolithic three-dimensional memory structure.
10. The non-volatile storage device of claim 1 further comprising:
the non-volatile storage device includes a three-dimensional memory array including the non-volatile storage elements.
11. A method for operating a data storage system, comprising:
selecting a first bay from a plurality of bays, the plurality of bays comprise an array of data storage elements, each bay includes a plurality of blocks of data storage elements and multiple sets of local data lines, each block includes a set of local data lines outside the data storage elements;
selecting a block within the first bay, the selected block includes multiple columns of first selection circuits for selective communication of bit lines with the set of local data lines for the respective block, each of the first selection circuits are connected to a different bit line for the selected block, the bit lines for the selected block are in communication with data storage elements, and the selected block includes second selection circuits providing selective communication of the set of local data lines with a set of global data lines, the set of global data lines being outside the plurality of blocks of data storage elements;
selecting a column of the selected block and using the first selection circuits of the selected column to provide selective communication between a subset of the set of local data lines for the respective block and a subset of bit lines connected to the first selection circuits of the selected column;
selecting the subset of the local data lines for the respective block to communicate with the set of global data lines using the second selection circuits, the set of global data lines also connect to local data lines for other blocks; and
performing a memory operation, using the global data lines, on data storage elements in communication with the selected subset of local data lines.
driving signals on global data lines;
selecting one or more word lines; and
driving signals on the selected one or more word lines for the memory operation.
the local data lines are in at least one metal layer below the data storage elements; and
the global data lines are in at least one metal layer above the data storage elements.
the array of data storage elements is a three-dimensional memory array.
15. A method for operating a data storage system, comprising:
selectively electrically connecting a subset of bit lines to a subset of a set of local data lines for selective communication of the subset of bit lines with the subset of the set of local data lines using a set of first selection circuits, the subset of bit lines are also in communication with a first subset of a plurality of data storage elements, the set of local data lines are positioned outside of the plurality of data storage elements;
selecting and electrically connecting the subset of the set of local data lines to a set of global data lines using a set of second selection circuits so that the subset of the set of local data lines are in communication with the set of global data lines, the global data lines are positioned outside of the plurality of data storage elements, the global data lines are connected to control circuitry, the global data lines are also connected to other sets of local data lines by the set of second selection circuits; and
performing a memory operation on at least a portion of the first subset of data storage elements using the control circuitry.
the plurality of data storage elements comprise a monolithic three-dimensional memory array;
the sets of local data lines are in at least one metal layer below the monolithic three-dimensional memory array; and
the global data lines are in at least one metal layer above the monolithic three-dimensional memory array.
the selectively electrically connecting the subset of bit lines to the subset of the set of local data lines comprises sending selection signals to the set of first selection circuits connected to the subset of bit lines and the set of local data lines; and
the selecting and electrically connecting the subset of the set of local data lines to the set of global data lines using a set of second selection circuits comprises sending selection signals to multiplexer circuits connected to the set of local data lines and the set of global data lines.
the data storage elements are arranged in three-dimensions.
the data storage elements are arranged in a three-dimensional memory structure.
the data storage system includes a three-dimensional memory array including the data storage elements.
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