Source: http://www.google.com/patents/US20010049303?dq=3798359
Timestamp: 2017-05-27 20:09:19
Document Index: 686928288

Matched Legal Cases: ['ART 100', 'ART 100', 'ART 100', 'ART 180', 'ART 100', 'ART 100', 'ART 100']

Patent US20010049303 - Multivenue jackpot system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsMultivenue jackpot system comprising a central control system (6), connecting via a communications network (4) to a jackpot controller (32) at multiple gaming venues (26). Each gaming venue (26) having multiple electronic gaming machines (28) (i.e. poker, slot, video machines which include hard meters...http://www.google.com/patents/US20010049303?utm_source=gb-gplus-sharePatent US20010049303 - Multivenue jackpot systemAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20010049303 A1Publication typeApplicationApplication numberUS 09/043,787PCT numberPCT/AU1996/000608Publication dateDec 6, 2001Filing dateSep 26, 1996Priority dateSep 26, 1995Also published asCA2233039A1, WO1997012338A1Publication number043787, 09043787, PCT/1996/608, PCT/AU/1996/000608, PCT/AU/1996/00608, PCT/AU/96/000608, PCT/AU/96/00608, PCT/AU1996/000608, PCT/AU1996/00608, PCT/AU1996000608, PCT/AU199600608, PCT/AU96/000608, PCT/AU96/00608, PCT/AU96000608, PCT/AU9600608, US 2001/0049303 A1, US 2001/049303 A1, US 20010049303 A1, US 20010049303A1, US 2001049303 A1, US 2001049303A1, US-A1-20010049303, US-A1-2001049303, US2001/0049303A1, US2001/049303A1, US20010049303 A1, US20010049303A1, US2001049303 A1, US2001049303A1InventorsStephen John Found, Alex Millar, Eddie ShellOriginal AssigneeStephen John Found, Alex Millar, Eddie ShellExport CitationBiBTeX, EndNote, RefManReferenced by (147), Classifications (10), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMultivenue jackpot system
[0015] These and other novel features of the system will become apparent from the following description of examples of the invention, in which: [0016] [0016]FIG. 1 is a block diagram of an electronic gaming system of the invention; [0017] [0017]FIG. 2 is a block diagram of the venue configuration; [0018] [0018]FIG. 3 is a diagrammatic representation showing data flows at the central control system; [0019] [0019]FIG. 4 is a block diagram of a jackpot interface board (JIB); [0020] [0020]FIG. 5 is a block diagram of the jackpot controller; [0021] FIGS. 6 to 9 are circuit diagrams for one implementation of an IP module; [0022] FIGS. 10 to 18 are block diagrams of glue logic in the IP module; [0023] [0023]FIG. 19 is a flow chart showing boot loading of the jackpot interface board; [0024] [0024]FIG. 20 is a diagrammatic representation of the major process steps carried out by the central controller (JCC); [0025] [0025]FIG. 21 diagrammatically illustrates messages in the win sequence of the system; and [0026] [0026]FIG. 22 is a flow chart illustrating the major functional steps of the jackpot controller. [0027] The illustrated gaming system of the invention includes a jackpot control centre (JCC) 6 which is coupled to a wide area network (WAN) 4. The wide area network may comprise a public telephone system. The JCC 6 may include a central computer 8 which includes a real time UNIX based operating system which, generally speaking, maintains overall control of the system. The central computer 8 is coupled by first and second local area networks (LAN) 10 and 19 to a standby central computer 12, which comes into operation should there be a fault in the central computer 8. Duplicate LANs are used for greater system redundancy. The LANs 10 and 19 are also connected to a command PC 14 which can be used for input and output of instructions at a high level in the system and monitor progress jackpot applications. The JCC 6 also includes a number of front end processing (FEP) devices 15 connected to the LANs 10 and 19. The front end processing devices 15 essentially comprise high speed modems for coupling the first and second LANs 10 and 19 to the wide area network 4. [0028] The system may also include a management information system 21 which provides management statistical and account data processing which may be carried out on an off-line basis. The management information system 21 also includes a management information system (MIS) computer 23 which operates a jackpot data base (JDB) which for instance can be implemented on INGRES data base. The computer 23 is coupled to the LANs 10 and 19 by means of a router 24. Alternatively, the computer 23 could be coupled directly to dual LANs 10 and 19. [0029] The system includes a number of venues 26, one of which is shown in FIG. 1. In practice there would be a number of venues 26 which are coupled to the JCC 6 by means of the wide area network 4. The venue 26 may comprise a casino, gambling hall or other site at which gambling is permitted by the relevant authorities. The venue includes a number of electronic gaming machines (EGMs) 28 which are coupled to a venue jackpot LAN 30. The EGMs 28 can be operated independently for gaming such as by playing poker or the like or may be connected to another network (not shown) for communications within the venue. The EGMs can also be coupled together within the venue or within a number of different venues for playing jackpot games subject to the control of the JCC 6. [0030] Each venue 26 includes a jackpot controller 32 which is coupled to the venue jackpot LAN 30 and to a network termination device (NTU) 34 via a bus 33. The network termination device 34 may comprise a modem and is coupled to the wide area network 4. Each of the EGMs 28 includes a jackpot interface board (JIB) 56 which provides coupling to the venue jackpot LAN 30 in a manner which permits the EGMs to participate in jackpots which are applicable to a selected number of EGMs at the venue, all EGMs at the venue, or selected EGMs at different venues, as will be described below. The venue 26 includes jackpot displays 38 and 40 which are controlled by the jackpot controller 32. The display 38 may comprise one or more LED displays which are located in prominent positions at the venue to display prize money and other information relating to jackpots. The display 40 may comprise video display monitors which display similar information. The displays 38 and 40 are of course different to the video displays (not shown) which form part of the EGMs 28. [0031] [0031]FIG. 2 shows in more detail an arrangement for the hardware configuration at a venue. In this arrangement, the video displays 40 are driven by a video display interface 46. Similarly, the LED displays 38 are driven by LED display interfaces 48. Interfaces 46 and/or 48 may be embodied in a PC. The arrangement includes a slip printer 50 and bar code reader 52 which are coupled by means of a peripheral interface 54 to the venue jackpot LAN 30. The slip printer 50 and bar code reader 52 can be used as part of a jackpot win procedure which will be described below. [0032] In the preferred implementation of the invention, the JIBs 56 are intelligent devices which greatly facilitate linking together of the EGMs 28 to participate in a jackpot game which is subject to the control of the jackpot controller 32 as well as the JCC 6. [0033] The main functions of the JCC 6 are: [0034] 1. To configure and reconfigure jackpot controllers 32 and peripherals. [0035] 2. To start, stop and restart jackpots. [0036] 3. To maintain software counters for counting contributions from EGMs. [0037] 4. To identify when a jackpot has been won and take appropriate action. [0038] 5. To check the integrity of the software and hardware in the jackpot system at any time. [0039] 6. To log information packets that are sent by the jackpot controllers 32. [0040] 7. To issue jackpot tickets. [0041] 8. To validate jackpot tickets. [0042] 9. To be able to provide any information about the status of any part of the jackpot system as required. [0043] The EGMs 28 can be of standard types apart from the inclusion of the JIB board 56. EGMs normally include logic means for playing the normal games on the EGM such as poker, black jack or the like. The logic generates hard meter input signals for hard meters which are provided in the EGM. The hard meters indicate such things as credit played (which is the amount of cash which has been wagered), cash out (which is the amount of cash which has been paid out by the EGM), cash in (which is the amount of cash inserted into the machine), and credit won (which is the amount of money which has been won on that machine). In the system of the invention, the JIBs 56 are responsive to the hard meter input signals and communicate relevant changes to the jackpot controller 32 at the venue via the venue jackpot LAN 30. The jackpot controller 32 communicates with the JCC 6 via the network 4 so that in accordance with the invention, a jackpot game can be carried out by effectively monitoring the hard meter input signals at a number of venues. A jackpot can be configured in the JCC 6 to have a random jackpot value and a jackpot pool is established and is incremented in accordance with hard meter input signals which have been generated by the various participating EGMs. When a hard meter input signal increments the jackpot pool so that it reaches or exceeds the random jackpot value, that constitutes a jackpot win and the system operates to identify the EGM which generated the hard meter input signal which generated the win. [0044] An even simpler jackpot game is to make the jackpot a fixed amount and to generate a random time within a specified time frame (1 hr, 24 hrs, etc . . . ). When that time arrives a venue is randomly selected and then the jackpot controller 32 at that venue makes the next EGM to make a contribution the winner. A slightly fairer model is to randomly select the venue from a list that is weighted according to each venue's average total contribution rates over a selected period. Again the jackpot controller is notified and the next EGM to make a contribution is the winner. [0045] [0045]FIG. 4 is a block diagram showing the main functional blocks of the JIB 56. Briefly, the JIB 56 carried out a variety of functions but its main function however is to enable the EGM 28 to which it is connected via hard meters to participate in a jackpot game involving a number of EGMs which are linked together at a venue 26 and at a number of venues 26. The JIB 56 monitors input signals to hard meters of the EGM via connector 120 and enables transfer of hard meter input signals to the jackpot controller 32. It also enables the jackpot controller to check the status of logic seal switches, audit keys and door seals and the like which are normally provided on the EGMs 28. It also superimposes messages on the EGM display relevant to the jackpot in which the EGM is participating. [0046] The JIB 56 comprises a microprocessor 16, a serial communications port 18, a memory 20 and a network interface 22. The JIB includes a system bus 78 coupled between the microprocessor 16 and the network interface 22. The network interface 22 may comprise known forms of interfaced device such as ethernet cards or the like. The network interface 22 is coupled to the venue jackpot LAN 30. Data flows between the EGM and venue jackpot LAN 30 through the interface device 22 and is formatted by the microprocessor 16 in accordance with information stored in the memory 20. The memory 20 also includes software for implementation of processing steps by the microprocessor relating to jackpot implementation, data communication and video displays. The JIB 56 also includes a communications bus 29 which can enable additional serial communications. [0047] The interface port also includes a video mixing device 42 which receives video in data from the EGM logic and provides video out data for the EGM display. The video mixing device 42 is coupled to the microprocessor 16 which provides a control mechanism for controlling video mixing of the video signals applied to the EGM display. The device 42 is arranged to superimpose jackpot information on the normal EGM display. Alternatively, it can be arranged to blank out the normal display when the jackpot information is displayed. [0048] Reference is made to a copending Australian patent application filed contemporaneously herewith in respect of an invention entitled “Jackpot Display System for an Electronic Gaming Machine”, the content of which is incorporated herein by reference. The copending application describes an example of circuitry for the JIB 56 in greater detail. [0049] [0049]FIG. 5 is a block diagram of the jackpot controller 32. The jackpot controller can be implemented on a PC platform. It comprises a processor 60 which preferably comprises a Motorola MVME 162-223A which is similar in some respects to a PC designed for specific applications. The processor 60 includes a CPU 62, flash memory 64 (e.g. 1 MB), DRAM memory 66 (e.g. 1-4 MB parity DRAM and 16-32 MB ECC DRAM) and SRAM memory 68 (e.g. 128K-2 MB SRAM with battery backup). The processor 60 includes a serial port controller 70 such as an 85230 serial I/O controller, coupled to a serial port connector 74. The processor 60 also includes an ethernet controller 76 (e.g. 182596CA) coupled to a DB-15 ethernet connector 78. The processor 60 also includes a coprocessor 80, such as a 53C710 SCSI coprocessor, coupled to a SCSI connector 82. The processor 60 also includes two IP ports 84 and 86. The IP ports are for receipt of “industry pack” modules which are particular circuit modules designed to assist the processor 60 in accordance with the required application. [0050] In the illustrated embodiment of the jackpot controller 32, an IP module 88 is coupled to the IP port 86. The IP module 88 is coupled to the network termination device 34 via the bus 33 for communication with the JCC 6. The processor 60 communicates with the JIBs 56 through the ethernet connector 78 which is connected to the venue jackpot LAN 30. The processor 60 also is coupled to a disk drive 90 via the connector 82. The operating system and the operational software of the jackpot controller 32 are stored on the disk drive in UNIX file system format. [0051] The IP module 88 can be implemented in a number of ways depending on the requirements for carrying out the jackpot system. In particular, the IP module can consist of two physically separate boards with different functions that are covered below. FIG. 6 is a more detailed block diagram of the IP module 88. [0052] The IP module 88 includes a connector 92 which is connected to the IP port 86 of the processor 60. The connector 92 is coupled to an IP module address bus 94, IP module data bus 96 and an IP module control bus 98. The buses 94, 96 and 98 are coupled to a DUART device 100 (e.g. AM85C30) which is arranged to control serial communications with the JCC 6. Serial communications can be made at an RS 232 connector 102 via a level converter 104. Alternatively, serial communications can be made through an RS 422 connector 106 via a level and protocol converter 108. The IP module 88 includes a memory 110 which is coupled to the buses 94, 96 and 98. Software and data is stored in the memory for enabling the jackpot controller to participate in multivenue jackpots as explained below. A memory supervisor circuit 112 is coupled to the memory 110 to provide for battery backup should the power supply fail. The IP module 88 includes an electronically programable logic device (EPLD) 114 (e.g. EPM7064LC84) which provides various “glue logic” functions for the module 88. The EPLD 114 is coupled to a battery monitor circuit 116, an over temperature circuit 118 and an alarm circuit 120. The EPLD 114 is also coupled to an LED indicating device 122. Control signals for controlling the LED are generated by the EPLD 114 from signals which could include MEMSEL and from the logic seal latch 139 and voltage comparators 147 and 148 (FIG. 9). [0053] The IP module 88 also includes logic seal detection circuitry 123 coupled to a logic seal switch (not shown) via connector 124. The jackpot controller 32 is located within a secure housing which, when opened, changes the state of the logic seal switch coupled to the connector 124 and this will be sensed by the logic seal circuit 123 and this causes the jackpot controller to stop the jackpot game by sending appropriate messages to the participating EGMs. To restart the jackpots at the venue, a special command will be sent from the JCC 6 and received by the jackpot controller 32. The IP module 88 also includes an optional EPROM 125 (e.g. 27519) which can be used for further enhancements. [0054] [0054]FIGS. 7, 8 and 9 show more details of the IP module 88. It will be seen that the logic bus 93 extends from the connector 92 to the DUART 100 and EPROM 125. The bus 93 is also coupled to the EPLD 114 which, as mentioned above, is arranged to provide glue logic for the circuit components for the IP module 88. The EPLD 114 provides six main functional blocks: [0055] acknowledge signal generation; I/O and memory read signal generation; interrupt acknowledge signal generation; I/O and memory write signal generation; memory decode, control signal generation; and status information storage. The acknowledge signal is generated from the trailing edges of the read and write signals. It is an open collector output. On reset the acknowledge output is tri-stated. An intermediate read signal is generated when either IOSEL or MEMSEL is active and the R/W signal is in read state. The INTSEL signal is delayed before generating the read output; this is to allow the interrupt source to clear its interrupt output before reading the interrupt vector. The intermediate read signal is combined with the reset line to produce the I/O read signal. This is required because the serial communications controller requires both its read and write lines to be held low to reset it. The I/O and memory write signals are generated when either a MEMSEL or IOSEL is active and the R/W line is in the write state. The I/O write line is combined with the reset line because the serial communications controller requires both its read and write lines to be held low during reset. [0056] The DUART provides serial communications with JCC6. It is selected when an I/O read or write occurs or an interrupt acknowledge occurs, provided IOSEL is active. [0057] The memory 110 comprises first and second SRAMs 126 and 127 and is selected by the lines MEMO and MEM1. MEM0 is generated from a combination of BS0, D13, D14 and MEMSEL. MEM1 is generated in a similar manner except BS1 is used instead of BS0. The memories 126 and 127 can store data representing hard meter input signals from the various EGMs which are coupled to the jackpot controller 32. Normally the hard meter input to the credit played hard meter will be stored and this information is vital to correct playing of the jackpot and accordingly the memories are duplicates of one another so as to provide security should one of them fail. Some gaming authorities require that certain information be maintained in two physical locations and three logical locations. The SRAMs 126 and 127 provide the physical locations. One of these SRAMs has two copies of the data, the other SRAM has a single copy of the data. Checksums are used to maintain the integrity of the data. If a single copy of the sensitive data becomes corrupted, then it is recovered by using one of the other good copies. If for some reason there are three good copies, but they are different, a majority vote is used to decide which copy to replace. The memories 126 and 127 are coupled to memory supervisor circuits 128 and 129 (e.g. DS1210) which operate with the associated backup to batteries to maintain high signal levels at the CE inputs of the memories should power fail so as to prevent data held in the memories being corrupted when power is disconnected. The DUART 100 is connected via the logic bus 93 to interface circuits 130 and 131 (e.g. SN75173) which convert RS 422 signals from the connector 106. The circuit also includes a converter 132 (e.g. SN75172) which converts TTL signals to RS 422 signals which are outputted to the connector 106. Inputs and outputs from the converters 130, 131 and 133 are coupled to the connector 106 via protection diodes 134, termination resistors 135 and current limiting resistors 136. [0058] In some applications it may be appropriate to communicate with the JCC 6 at RS 232 levels and in this case, the IP module 88 includes a converter 137 (e.g. MAX211) which is arranged to convert signals from TTL to RS 232 and vice versa for coupling to the RS 232 output connector 102. [0059] The logic seal circuit 123 is illustrated in more detail in FIG. 9. The input connector 124 is connected to a logic seal switch (not shown) which is coupled via line 138 to an eight bit latch 139. The latch 139 is coupled to the logic bus 93 so that an eight bit number can be written into and read from the latch by the CPU 62 of the processor 60. If the logic seal switch changes state, the latch 139 will be reset and this will be sensed by the CPU 62 thus indicating that the logic seal has been broken. This information will also be communicated to the JCC which will suspend participation of the EGMs in the jackpot game which are coupled to the jackpot controller having its logic seal switch open. The latch 139 is coupled to a memory supervisor chip 140 (e.g. DS1210) which operates to provide power to the latch 139 and also to connect a battery backup thereto if the normal power supply is low. The circuit 140 also operates to prevent corruption to the number stored in the latch 139 if power fails. The CPU 62 can be arranged to write the eight bit number on lines d0-d7 once but preferably it is arranged to write different numbers periodically so as to provide for additional security. [0060] [0060]FIG. 9 also illustrates in more detail the over temperature circuit 118. It includes a connector 141 which is connected to a temperature sensing device (not shown) which is located at a strategic location, say on a heat sink coupled to the CPU 64. The connector 141 is coupled to one input to a comparator 142 which has a reference level applied to its other input from a zener diode 143. The comparator 142 produces an output signal TEMPOV on line 144 when an over temperature is sensed. The comparator could be designed to trip at 65° C. and reset at about 60° C., for example. [0061] [0061]FIG. 9 also illustrates the battery monitor circuit 116. It comprises first and second comparators 145 and 146 which are coupled to receive inputs on lines 147 and 148 from the backup batteries for the memories 126 and 127. Other inputs to the comparators 145 and 146 comprise a reference level derived from a zener diode 149. When the comparators 145 or 146 detect a low battery condition, a LOWBAT signal is produced on output line 150. [0062] [0062]FIG. 9 also illustrates the alarm circuit 120. The alarm circuit 120 has inputs 151 and 152 from the EPLD 114. The input 151 can be selected for muting an audible alarm produced by alarm loudspeaker 153 whereas signals on the line 152 from the EPLD 114 can be used to change the frequency of the audible alarm in accordance with the type of alarm which is detected. The alarm circuit includes a timer 157 (such as an LM555) which is normally held in a reset state by a mute signal on input 151. When an over-temperature fault is detected or the logic area seal is broken, the alarm is set off. The alarm can only be reset under the control of software. The two tone feature is implemented by switching in or out different value capacitors, into the timer circuit, by means of transistor 159. [0063] FIGS. 10 to 18 diagrammatically illustrate some of the glue logic functions provided by the EPLD 114. It will be appreciated that these functions could be implemented by providing discrete logic components in the circuitry but it is preferred that they be implemented in an electronically programmable device for simplicity and flexibility should the circuit parameters need to be modified. [0064] The EPLD 114 is programmed so as to provide an address latch circuit 160 which stores the address information from the multiplexer address/data lines. FIG. 11 shows the memory latch 160 in greater detail. It will be seen that the memory latch 160 functionally includes two eight bit latches 164 and 165. [0065] The EPLD 114 includes status logic 167 (shown in greater detail in FIG. 12) which has an input 168 for receipt of LAREA signals from the logic seal circuitry 123. The logic 167 includes an input 169 for receipt of TEMPOV signals from the circuit 118. The logic 167 includes an input 170 for receipt of LOWBAT signals from the battery monitor circuit 116. The logic 167 produces an LED signal output on line 171 for coupling to the status indicating LED 122. It has an output on line 172 for producing MUTE signals on line 151 for muting the alarm circuit 120. It also produces FREQSEL for selecting the tone produced by the loudspeaker 153, as shown in FIGS. 9 and 12. [0066] The EPLD 114 also includes a memory select logic 173 which has inputs on lines 174 from the CPU 62 via control bus 98. The input signals on lines 174 determine how data is stored in the memories 126 and 127. The memory logic circuitry 173 is shown in more detail in FIG. 13. [0067] The EPLD 114 includes DUART selector logic 176 which enables the CPU 62 to address the DUART 100 whenever it writes to it or reads from it. The selector logic 176 is shown in more detail in FIG. 14. Output on output line 176 has an 8530 output signal which is coupled to the CE input of DUART 180 to enable the appropriate selection to be made, as seen in FIG. 7. [0068] The EPLD 114 includes write select circuitry 178 which has inputs from the logic bus 93 to produce outputs on lines 179 and 180 for enabling writing of data to the DUART 100 and memories 126 and 127 respectively. This circuit is shown in more detail in FIG. 15. [0069] The EPLD 114 includes acknowledge signal logic 181 which has inputs derived from the logic bus 93 and produces an input acknowledgment signal on output line 182 for providing an acknowledgment signal for the DUART 100 for indicating to the CPU 62 that the current read or write function has been completed. The logic 181 is shown in more detail in FIG. 16. [0070] The EPLD 114 includes read logic circuitry 183 which has inputs from the logic bus 93 and produces outputs on output lines 184 and 185 for enabling reading of signals from the logic bus to the DUART 100 and for reading signals from the bus into the memories 126 and 127 respectively. The read logic 181 is shown in more detail in FIG. 17. [0071] The EPLD 114 includes acknowledge signal logic 186 which generates acknowledge signals ACK on its output line 187. The logic 186 has inputs derived from the logic bus 93 and its output line 187 is directly coupled to the connector 92 (pin 48) to provide acknowledgment signals to the CPU 62 to provide an indication that reading or writing sequences have been completed. The logic 186 is shown in more detail in FIG. 18. [0072] It will be appreciated by those skilled in the art that the various logical functions carried out by the EPLD 114 can be implemented in a variety of ways. [0073] The JIB software consists of three basic parts: [0074] 1. The Boot Loader Program [0075] 2. The Main Mode Program [0076] 3. The Jackpot Interface Module (JIM) [0077] The first two parts are executed physically by the microprocessor 16 from its software stored in memory 20 and reference is made to the aforementioned patent application. The JIM is an interface between the JIB and a Jackpot Application Program and is executed on the jackpot controller 32 together with the Jackpot Application Program. [0078] The Boot Loader Program operates to boot load the JIB 56. A flow chart of the program is shown in FIG. 19. When the JIB starts up it operates as a cut down or simplified JIB. It does not support the full range of commands but instead the set of commands required to perform software integrity (including signature) checks and software download. The boot program is always to be present in the memory 20 of the JIB; and for it to contain the ability to download new versions of the main code, which is the fully functional software, which is inputted thereto from time to time by the JCC 6. [0079] The Boot Loader Program includes a loop which performs the following main functions as diagrammatically shown in FIG. 19: [0080] 1. Sending an ‘I am awake’ message every 10 seconds; [0081] 2. Continually checking for received ethernet packets; [0082] 3. Checking that a packet has been received recently from the jackpot controller, and [0083] 4. Patting a watchdog (The watchdog circuit reboots the processor should it hang. [0084] Also provided is a power failure detect. This enables important data to be stored in battery backed memory 20 before the power fails completely). [0085] The JIB issues an ‘I am awake’ message regularly and, when the jackpot controller 32 receives these, it will send down series of initialisation messages and may also begin software download to its memory 20. If software download proceeds then this is fully processed within the boot code. Once the boot code receives the start command it immediately jumps to the main code, which has the responsibility of acknowledging the start command. The Boot Loader Program may also include provision of a procedure for initiating encryption of communications between the JIB 56 and jackpot controller 32 in response to an “encrypt” message and encryption key from the jackpot controller 32. [0086] The Main Mode Program includes code which supports all possible commands from the jackpot controller 32, including signature, display commands, event actions, state setting, version, configuration and software download. [0087] When a start command is issued to the JIB boot program by the jackpot controller 32, the main code of the JIB is executed and an acknowledge signal is sent back to the jackpot controller 32 acknowledging the start command. The Main Mode Program performs the following functions: [0088] 1. Receiving network packets and processing the commands appropriately; [0089] 2. Checking if a packet has been received from the jackpot controller within the maximum communications idle time; [0090] 3. Checking for any displays which have had expired duration; [0091] 4. Checking for events which have occurred and subsequently performs the configured actions for those events; [0092] 5. Checking that the maximum communications idle time is not exceeded since the last time the JIB transmitted a network packet. The JIB will transmit a status message before the maximum communications idle time is exceeded; [0093] 6. Operating the on board LED's; and [0094] 7. Preventing the loops from proceeding if a power failure interrupt occurs. [0095] [0095]FIG. 3 diagrammatically illustrates major data flows within the JCC 6. In particular, the central computer 8 implements a jackpot application module 170, a network management module 172 and existing network games such as a KENO module 174. The central computer 8 also executes a LAN control module 176 which supervises and controls access to the LANs 10 and 19. The module 176 controls data flows to the front end processors 15 as shown. FIG. 20 is a flow chart showing major software steps performed by the JCC 6. [0096] Preferably the jackpot controller 32 will have the option to accept its application software downloaded from JCC 6 for carrying out a jackpot game at the venue. The following security measures can be implemented for the download: secure encrypted links through the WAN 4; the signature of the software is verified by central computer 8 before allowing normal operational mode of the jackpot controller 32; and the jackpot controller keeps a history log of every download. [0097] The downloading can be used for retrofitting the jackpot controller software when it is required to update the software. The jackpot controller controls the slip printer 50 and bar code reader 52 through the interface 54. The slip printer 50 is used to produce the jackpot win tickets. The bar code reader 52 is used to validate the jackpot tickets. [0098] Normally, the parameters of the jackpot are established in the jackpot data base maintained in the MIS computer 23 and then transmitted to the various venues by JCC 6 where they are initially processed by the jackpot controllers 32. These inputs can be made through by a JDB terminal (not shown) by an authorised officer. The jackpot parameters may include the period for the random time generation, the upper limit of the jackpot, lower limit of the jackpot, percentage contribution from each EGM, restart values etc. After checking and verification, the parameters can be frozen by a special command issued from the JDB terminal. The locked configuration is then transferred to the jackpot application software module 170 of the central computer 8. The transfer is initiated by a command issued from the command PC 14. [0099] The jackpot configuration is then transmitted to the jackpot controllers 32 of the various venues 26. The jackpot controllers receive the jackpot configuration, perform dependency checks and store it in a battery backed RAM 110. The jackpot controller 32 acknowledges the reception of the configuration to the JCC 6 which acknowledges it to the management information system 21, which includes the JDB. From this moment the entered configuration becomes “active”. Any further changes of the parameters on the JDB will be stored in the “pending” state and need to be activated using the process described above. [0100] When the jackpot controller 32 receives the jackpot configuration it converts it to the form that is acceptable by the JIBs 56 of the participating EGMs. When a JIB 56 is coming on-line, the jackpot controller 32 transmits the jackpot configuration thereto via its ethernet connector 78 and venue jackpot LAN 30. Each JIB 56 receives the configuration, stores it in its RAM 20 and sends an acknowledgment to the jackpot controller 32 via the venue jackpot LAN 30. If a JIB 56 is already on-line, a new jackpot configuration can be transmitted to it by the jackpot controller. Once a JIB 56 receives its jackpot configuration, its microprocessor 16 causes the video mixing device 42 to overlay the unique number of the EGM on the screen of the EGM. [0101] Once the configuration of a jackpot is successfully set up in participating jackpot controllers and EGMs, a start command message can be issued from the command PC 14 at the JCC 6. Once the jackpot controller 32 receives the start command from the JCC 6, it activates the JIBs 56 of participating EGMs and if attached, the interfaces 48 and 54 for jackpot displays 38 and 40. After all the jackpot controllers 32 have acknowledged the reception of the hidden prize value, the JCC 6 will cause the jackpot controllers 32 to activate the JIBs 56 of participating EGMs and the interfaces 48 and 54 for jackpot displays 38 and 40 at the various venues. At each venue, the jackpot controller 32 broadcasts a jackpot open command together with a corresponding message to be displayed. All the messages for the JIBs 56 and interfaces 46 and 48 are identified by message identification signals (message IDs) during the configuration stage. The jackpot controller 32 therefore need only broadcast the message ID to cause the display of the appropriate message. The JIBs 56 will overlay the messages on the EGM's screen and messages will be displayed on the monitors 40 and LED displays 38. [0102] For every $1 played on an EGM, a hard meter input pulse is generated by the EGM logic to increment its amount played hard meter. The JIB 56 receives this input pulse via connector 120 and increments the software counter that contains the accumulated number of pulses (absolute value). The jackpot software executed by the microprocessor 16 converts the counter value into cents by adding 100 for every one detected pulse. The JCC 6 configures the minimum number of contributions before the JIB 56 will report to the jackpot controller 32. This is also controlled by a timeout period. For example, if the JIB 56 is configured to report a minimum contribution of, say, $3 with a time out of 5 seconds, once more than $3 has been incremented (i.e. 3 pulses to the hard meters) the JIB 56 sends a communication packet to the jackpot controller 32 which contains the current time stamp and the software counter value. If the venue jackpot LAN 30, is busy, the JIB 56 will retry next time. This means that the software counter can be incremented more than once between each transmission. [0103] If a contribution of less than the configured minimum limit (e.g. $3) has been received by the JIB 56 but the time since the first of the unreported contributions was received is greater than the timeout period (e.g. 5 seconds) then the unsent contributions are forwarded to the jackpot controller 32 in any event. [0104] Every defined period of time the jackpot controller 32 also sends all individual EGM contributions to the JCC 6 for financial reconciliation purposes. At the JCC 6 all the received contributions are stored in a transaction file 109. [0105] The jackpot controller 32 must continue to communicate with the JCC 6 to continue participation in the jackpot. If the jackpot controller 32 loses the communications with the JCC 6, the jackpot will be suspended and appropriate message will be displayed by all JIBs 56 and optional displays 38 and 40. Likewise, the JIBs must continue to communicate with the jackpot controller 32. If a JIB loses communication with the jackpot controller 32, the JIB stops accepting contributions from the EGM and can, for example, display a message to inform the player that their EGM is no longer in the jackpot. [0106] In the case of a jackpot win, the jackpot controller 32 performs the following actions: [0107] display jackpot win message on a monitor of the jackpot controller for the venue attendant; [0108] commands the interfaces 46 and 48 to display jackpot win messages on the venue displays, the win message including EGM identification number as is displayed by the JIB; [0109] command the JIBs of all non-winning EGMs to display to the players that the jackpot was won by another EGM, this being carried out by broadcasting a particular message ID to the JIBs; and [0110] request the JCC 6 to generate a special jackpot win ticket which is printed on the slip printer 50, the ticket being delivered by the venue attendant to the player of the winning EGM. [0111] There are two possible ways to clear the jackpot win condition on an EGM: (1) the venue attendant will clear the error condition that disabled the EGM; or (2) the EGM will remain disabled until a special clear command has been received from the jackpot controller 32 and originating in the JCC 6. [0112] Information relating to the jackpot win ticket will be stored on the JCC 6 so that the player can redeem the ticket any time after the win. An authentication number on the ticket can be presented in two formats—a number and a bar code. The bar code reader 52 enables easy ticket validation. [0113] [0113]FIG. 22 is a flow chart which diagrammatically sets out the major functional steps of the software carried out in the jackpot controller 22 to give effect to the steps described above. [0114] The Jackpot Interface Module (JIM) executed in jackpot controller 32 provides a connecting interface between the Jackpot Application Program executed at the JCC 6 and the JIBs 56. Briefly, the JIB software and the jackpot controller software can be viewed as consisting of the following functional blocks: [0115] 1. interface functions used by the customer application, this is the set of functions used by the Jackpot Application to communicate with the JIB network; [0116] 2. within the JIM, a set of functions used to process most of the interface functions; [0117] 3. a process which receives network packets on bus 33 and processes them; [0118] 4. a process which periodically checks to see if messages need to be retransmitted and also checks timing of broadcast by the jackpot controller 32 of ‘I am alive’ messages; and [0119] 5. a set of support modules which provide database, ethernet, queue interface functions. [0120] An alternative jackpot scheme is a mystery jackpot value and in this arrangement the mystery jackpot value is generated and maintained by the JCC 6. [0121] Data representing contributions towards that jackpot are transmitted to the JCC 6 via the jackpot controllers 32 at the various venues 26. The JCC 6 operates a software counter to effectively sum data signals representing EGM contributions. When the JCC 6 determines that the jackpot total is reached, it identifies the site where the contribution which lead to reaching the jackpot value. The JCC 6 then transmits a signal to the jackpot controller 32 at the site. The jackpot 32 at that site then declares that the next EGM at that venue to make a contribution is the winner of the jackpot. [0122] [0122]FIG. 21 illustrates a preferred system of the invention which includes display of a Provisional Win message at the venue whilst various checks are carried out. In this system when a random time occurs, the JCC 6 randomly selects a venue (using venue weighting list) and sends a Select EGM message to the jackpot controller 32 at the selected venue. The jackpot controller then waits for the next hard meter input signals from any EGM connected thereto (and participating in the jackpot) and checks if the corresponding JIB software passes software integrity tests. If yes, a Provisional Win message is displayed at the venue and details of the identity of the EGM are sent to the JCC 6. The provisional winning EGM details are sent to the JCC 6 by the jackpot controller 32 and the JCC 6 dispatches a Win Ticket message to all of the jackpot controllers. The jackpot controller receives the Win Ticket message and causes an appropriate message to be displayed on the winning EGM screen. Also a message such as Jackpot Won is displayed on all other EGM screens at the venue. The jackpot controller also sends an acknowledge (ACK) message to the JCC 6. The jackpot controller causes the winning ticket to be printed and displayed on a screen coupled to a venue PC (if provided). The jackpot controller then causes the winning EGM to be disabled so that it cannot proceed with normal play. After the jackpot is won, the JCC is automatically restarted by a start command. The winning EGM will be cleared by a command which originates in the JCC 6. [0123] Many modifications will be apparent to those skilled in the art without departing from the spirit and scope of the invention as defined in the claims appended hereto. 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1998ASAssignmentOwner name: BYTECRAFT SYSTEMS PTY. LTD., AUSTRALIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FOUND, STEPHEN JOHN;MILLAR, ALEX;SHELL, EDDIE;REEL/FRAME:009554/0923Effective date: 19980820Owner name: WINTECH INVESTMENTS PTY. LTD., AUSTRALIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FOUND, STEPHEN JOHN;MILLAR, ALEX;SHELL, EDDIE;REEL/FRAME:009554/0923Effective date: 19980820RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services