Source: http://www.google.com/patents/US7908425?dq=6188988
Timestamp: 2017-05-23 04:33:41
Document Index: 342686229

Matched Legal Cases: ['§120', 'Application No. 10', '§119', 'Application No. 2004', 'Application No. 10', '§ 1']

Patent US7908425 - Method and device for performing cache reading - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsIn a read method for a memory device, a bit line is set with data in a first memory cell; and the data on the bit line is stored in a register. The data in the register is transferred to a data bus while setting the bit line with data in a second memory cell. In another read method for a memory device,...http://www.google.com/patents/US7908425?utm_source=gb-gplus-sharePatent US7908425 - Method and device for performing cache readingAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7908425 B2Publication typeGrantApplication numberUS 12/216,003Publication dateMar 15, 2011Filing dateJun 27, 2008Priority dateMar 30, 2004Fee statusPaidAlso published asCN1677565A, CN1677565B, CN101819813A, CN101819813B, DE102005014815A1, DE102005014815B4, US7421557, US20050226046, US20090019215Publication number12216003, 216003, US 7908425 B2, US 7908425B2, US-B2-7908425, US7908425 B2, US7908425B2InventorsJin-Yub Lee, Sang-Won HwangOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (16), Non-Patent Citations (1), Referenced by (10), Classifications (35), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod and device for performing cache reading
US 7908425 B2Abstract
In a read method for a memory device, a bit line is set with data in a first memory cell; and the data on the bit line is stored in a register. The data in the register is transferred to a data bus while setting the bit line with data in a second memory cell. In another read method for a memory device, a bit line of a first memory cell is initialized and the bit line is pre-charged with a pre-charge voltage. Data in a memory cell on the bit line is developed, and a register corresponding to the bit line is initialized. The data on the bit line is stored in the register. The data in the register is output externally while performing the initializing, pre-charging, making and initializing to set the bit line with data in a second memory cell.
1. A read method in a memory device comprising:
setting a bit line with data of a first memory cell, the setting of the bit line including:
initializing the bit line,
pre-charging the bit line with a pre-charge voltage, and
setting a data state of the bit line to a data state of the first memory cell; and
storing the data on the bit line in a register having a single-latch,
wherein data in the register is transferred to a data bus while setting the bit line with data of a second memory cell.
2. The read method of claim 1, further comprising: initializing the register after the setting of the bit line with data and prior to the storing of the data on the bit line.
3. The read method of claim 2, wherein the register is initialized by electrically connecting the register to the data bus via a switch circuit.
4. The read method of claim 1, wherein the initializing of the bit line is performed with a state of the register being maintained.
5. The read method of claim 1, wherein the first and second memory cells comprise flash memory cells.
6. The read method of claim 1, wherein the single latch is configured to connect with the bit line and to store data on the bit line.
7. A read method in a memory device comprising:
initializing a bit line of a first memory cell;
pre-charging the bit line with a pre-charge voltage;
setting the bit line with data by setting a data state of the bit line to a data state of a memory cell;
initializing a register having a single-latch, the register corresponding to the bit line; and
storing the data on the bit line in the register,
wherein the data in the register is output externally while performing the initializing, pre-charging, setting and initializing to set the bit line with data of a second memory cell.
8. The read method of claim 7, wherein the register is initialized by electrically connecting the register to a data line via a switch circuit.
9. The read method of claim 7, wherein initializing of the bit line is made, with a state of the register being maintained.
10. The read method of claim 7, wherein the single-latch is configured to connect with the bit line and to store data on the bit line. Description
This application is a divisional of, and claims priority under 35 U.S.C. §120 to, Application No. 10/999,174 filed on Nov. 30, 2004, now U.S. Pat. No. 7,421,557, which claims claims priority under 35 U.S.C. §119(a) to Korean Patent Application No. 2004-21654 filed on Mar. 30, 2004. The contents of each of these applications are hereby incorporated by reference in their entirety.
NAND flash memory may include a string of serially connected cells (for example, 16 cells may make up a string). The string may include one or more string select transistors. NAND flash memory may have a relatively small “on” cell current and hence, relatively slow sensing time (for example, 5-10 ms). NAND flash memory may perform a read operation by simultaneously sensing and latching a page unit (for example, 512 bytes) to page buffers. NAND flash memory may read data from page buffers latch at a relatively high speed (for example, 50 ns).
Example embodiments of the present invention are directed to semiconductor devices, such as semiconductor memory devices, including, for example, flash memory, with reduced data transfer time.
Page buffers 130_0-130_n may be connected to bit line pairs (BL0 e, BL0 o)-(BLne, BLno), respectively. The page buffer 130_0 (and/or each page buffer 130_n) may include a latch 131, NMOS transistors TR1-TR7, and a PMOS transistor TR8, which may be connected as shown in FIG. 7. The page buffer 130_0 (and/or each page buffer 130_n) may operate as a register which is used to store data to be programmed or data read out from the memory cell array 110.
The transistors TR1 and TR2 may be used to reset the bit lines BLie and BLio (i=0-n) in a bit line reset period of a read operation and/or to set unselected bit lines to a ground voltage in remaining periods thereof.
During a bit line reset period T1, control signals LVBLe, LVBLo, LBLSHFe, and LBLSHFo may be activated high and a control signal LPLOAD may be inactivated low. As the control signals LVBLe, LVBLo, LBLSHFe, and LBLSHFo are activated high, bit lines BLOe and BLOo may be electrically connected to a power line VIRPWR having a ground voltage (for example, 0V) during a read operation. Thus, the bit lines BLOe and BLOo may be reset to a ground voltage. In particular, a control signal LBLSLT may be maintained low during the bit line reset period T1, so that the latch 131 is not reset.
After resetting the bit line BLOe and BL0 o, during a bit line pre-charge period T2, the selected bit line BLOe may be pre-charged with a given pre-charge voltage (for example, 1.2V).
As the control signals LVBLe and LBLSHFo go to a low level, the selected bit line BLOe may be electrically isolated from the power line VIRPWR, and an unselected bit line BL0 o may be electrically isolated from the ND1 node. Because the control signal LVBLo may be maintained high during the bit line pre-charge period T2, the unselected bit line BLOo may be electrically connected to the power line VIRPWR having a ground voltage. At the same time, as the control signal LPLOAD is activated low, the PMOS transistor TR8 may be turned on. Current supplied from the turned-on transistor TR8 may be transferred to the selected bit line BLOe via the NMOS transistor TR3. At this time, since a voltage (for example, 2.0V) is supplied to the LBLSHFe line as illustrated in FIG. 8, the bit line BLOe may be pre-charged with a voltage of 2.0V-Vth, where Vth is a threshold voltage of transistor TR3.
During a bit line develop period T3, a voltage of the selected bit line BLOe may be maintained at the pre-charged voltage or lowered to a ground voltage depending on a state (i.e. a program state or an erase state) of a selected memory cell. At this time, the selected bit line BLOe may be floated. For example, as the control LBLSHFe goes to a low level of a ground voltage, the NMOS transistor TR3 may be turned off. This electrically isolates the selected bit line BLOe from the ND1 node. Under these conditions, if the selected memory cell has an erase state (or an on-cell), the pre-charged voltage of the selected bit line starts to be discharged to a ground voltage via the selected memory cell of the on state. On the other hand, if the selected memory cell has a program state (or an off-cell), the pre-charged voltage of the selected bit line is maintained.
During a sense period T5, cell data reflected on the selected bit line BLOe may be stored in the latch 131. To achieve this, the control signal LPLOAD may be inactivated high and a voltage (for example 1.2V) may be applied to the LBLSHFe line. Under these conditions, if a memory cell in an erase state (or an on state) is connected to the selected bit line BLOe, a power supply voltage of the ND1 node may be discharged via the on cell.
On the other hand, if a memory cell in a program state (or an off state) is connected to the selected bit line BLOe, the power supply voltage of the ND1 node may be maintained. This is because the NMOS transistor TR3 (Vg=1.2, Vs=1.2V, Vd=Vcc) is shut off.
As is apparent from the above description, data previously stored in the page buffers 130_0-130_n may be transferred to the data bus DB while data stored in the cell is read out and stored in the latch (tR,T1˜T5). Because page data stored in a page (row) of memory cells may be output externally during the bit line set period (T1-T3) of another page (or row), it is possible to reduce a time needed for a continuous read operation.
A cache read operation in accordance with an example embodiment of the present invention may be illustrated in conjunction with FIGS. 11 a and 11 b. As shown in FIG. 11 a, page data may be transferred from the nonvolatile memory 230 to the first buffer memory 240 during a bit line set period T1-T3 (tT), and a previous page data may concurrently be transferred from the second buffer memory 250 to a host 210 during all periods T1-T5 of a read operation (tR) or during a buffer transfer time (tT).
In an example embodiment, all constituent elements of a memory device, such as memory device 220, may be formed on a substrate so as to constitute a single chip. That is, in an example embodiment, the memory device of the present invention may be a single chip, also commonly referred to as a “one-NAND flash memory device”. In a one-NAND flash memory device, a register, such as register 262, may be set and automatically perform a read/write operation based on the set values in the register. A one-NAND flash memory device need not use a command/address/data multiplexed I/O structure that may be utilized in a conventional flash memory device. For this reason, an address transfer path and a data transfer path may be separated outside and/or inside of the host interface 261.
In an example embodiment, if data “0000h” is stored in the register region of F001h, a 0th memory block of a memory cell array in the nonvolatile memory core 230 may be selected. If data “0001h” is stored in the register region of F001h, a 1st memory block of the memory cell array in the nonvolatile memory core 230 may be selected. If data “0000h” is stored in the register region of F002h, a 0th page of a selected memory block may be selected. If “0002h” data is stored in the register region of F002h, a 2nd page of a selected memory block may be selected. If data “0000h” is stored in the register region of F003h, the first page buffer 240 may be selected. If data “0001h” is stored in the register region of F003h, the second page buffer 250 may be selected.
In an example embodiment, referring to FIG. 14 b, when data “0000h” is stored in a register region of F004h, a read operation of the nonvolatile memory 230 may be carried out. In an example embodiment, when data “0001h” or “0002h” is stored in a register region of F004h, a cache read operation for the nonvolatile memory 230 may be carried out. As will be described below, if a cache read command of “0001h” is received, an operation for transferring data from page buffers to a buffer memory may be carried out together with an operation for setting cell data onto a bit line. On the other hand, if a cache read command of “0002h” is received, only the operation for transferring data from page buffers to a buffer memory may be carried out, without the operation for setting cell data onto a bit line.
In an example embodiment, the cache read command of “0001h” may be referred to as a first cache read command and the cache read command of “0002h” may be referred to as a second cache read command.
In an example embodiment, a write operation for the nonvolatile memory 230 may be carried out when data “0003h” is stored in a register region of F004h and an erase operation for the nonvolatile memory 230 may be carried out when data “0004h” is stored in the register region of F004h. A reset operation for the nonvolatile memory 230 may be carried out when data “0005h” is stored in the register region of F004h. FIGS. 14 a and 14 b illustrate the above-described command conditions.
For example, as illustrated in FIG. 16, in register region F001h may be stored data “0000h” and in register region F002h may be stored data “0000h”. Data “0001h” may be stored in register region F003h and data “0001h” may be stored in register region F004h. These conditions may be sued to indicate a first cache read command is received, that a 0th page of a 0th memory block is selected, and that data of the selected page is stored in the second buffer memory 250. After the register 262 is set with the address and command data, the scheduler 262 may activate the interrupt signal INT low.
A memory block (e.g. 0th memory block) of memory blocks may be selected by a row decoder 120, and 0th page of pages in the selected memory block may be selected by the row decoder 120. Assuming that even-numbered bit lines BLie of bit line pairs BLie and BLio (i=0-n) are selected, after all bit lines BLie and BLio are reset to a ground voltage in the bit line reset period T1 (in FIG. 15, S100), the selected bit lines BLie may be pre-charged with a given pre-charge voltage in the bit line pre-charge period T2 (in FIG. 15, S120).
Cell data in memory cells of the selected page may be reflected on the selected bit lines BLie in the bit line develop period T3 (in FIG. 15, S140). After the bit line set period T1-T3, latches 131 of page buffers 130_0-130_n may be reset in the latch reset period T4 by electrically connecting the latches 131 to a data bus DB through a column gate circuit 140 (in FIG. 15, S160). Data values on the selected bit lines may be transferred to corresponding latches 131 in the sense period T5 (in FIG. 15, S180).
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