Source: http://www.google.com/patents/US7351610?dq=5920316
Timestamp: 2017-06-23 20:09:07
Document Index: 670936242

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'arts 407', 'arts 407', 'art 304', 'arts 305', 'art 304']

Patent US7351610 - Method of fabricating a semiconductor multi-package module having a second ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor multi-package module has stacked first and second packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball...http://www.google.com/patents/US7351610?utm_source=gb-gplus-sharePatent US7351610 - Method of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrateAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7351610 B2Publication typeGrantApplication numberUS 11/622,993Publication dateApr 1, 2008Filing dateJan 12, 2007Priority dateOct 8, 2002Fee statusPaidAlso published asUS20070111388Publication number11622993, 622993, US 7351610 B2, US 7351610B2, US-B2-7351610, US7351610 B2, US7351610B2InventorsMarcos KarnezosOriginal AssigneeChippac, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (100), Referenced by (6), Classifications (62), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrate
US 7351610 B2Abstract
A semiconductor multi-package module has stacked first and second packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid array package having a flip-chip in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a flip-chip in a die-up configuration, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
1. A method for making a multi-package module, comprising:
providing a die-up flip chip first package including a first package substrate,
providing a second package including a die and a second package substrate, the second package substrate having a metal layer exposed at an edge thereof,
inverting the second package and stacking the inverted second package over the first package, and
electrically interconnecting the first and second packages by wire bonds connecting the first package substrate and the metal layer exposed at the edge of the second package substrate.
2. The method of claim 1 wherein providing a die-up flip chip first package comprises providing an unsingulated strip of die-up flip chip first packages.
3. The method of claim 2, further comprising singulating the completed module from the strip.
4. The method of claim 1 wherein providing a die-up flip chip first package comprises testing die-up flip chip packages for a performance and reliability requirement, and selecting a package meeting the said requirement as a said first package.
5. The method of claim 4, further comprising providing the first package with an electromagnetic shield.
6. The method of claim 1 wherein providing a second package comprises testing packages for a performance and reliability requirement, and selecting a package meeting the said requirement as a said second package.
7. The method of claim 1 wherein providing a second package comprises providing a land grid array package.
8. The method of claim 1 wherein providing a second package comprises providing a bump chip carrier package.
9. The method of claim 1 wherein stacking the second package over the first package comprises affixing the inverted second package onto a surface of the first package substrate.
10. The method of claim 9 wherein affixing the second package onto a surface of the first package substrate comprises applying an adhesive onto a die attach area of the first package surface substrate and contacting the inverted second package with the adhesive.
11. The method of claim 10 wherein applying the adhesive comprises applying a curable adhesive, and further comprising curing the adhesive.
12. The method of claim 1, further comprising attaching second-level interconnect balls onto the first substrate.
13. The method of claim 1, further comprising encapsulating features over the first substrate with a molding compound.
14. The method of claim 1, further comprising providing the module with a heat spreader.
15. The method of claim 14 wherein providing the module with a heat spreader comprises performing a drop-in molding operation.
16. The method of claim 14 wherein providing the module with a heat spreader comprises affixing a generally planar heat spreader onto an upward facing surface of the inverted second package.
This application is a Continuation of U.S. application Ser. No. 11/374,373, filed Mar. 13, 2006 now U.S. Pat. No. 7,163,842, titled “Semiconductor multi-package module having inverted second package stacked over die-down flip chip ball grid array (BGA) package”, which is a Division of U.S. application Ser. No. 10/681,583, filed Oct. 8, 2003, which issued May 16, 2006 as U.S. Pat. No. 7,045,887, titled “Semiconductor multi-package module having inverted second package stacked over die-up flip chip ball grid array (BGA) package”. U.S. application Ser. No. 10/681,583 claims the benefit of U.S. Provisional Application No. 60/417,277, filed Oct. 8, 2002, titled “Semiconductor multi-package module having inverted second package”. U.S. application Ser. No. 10/681,583 also is a Continuation-in-Part of U.S. application Ser. No. 10/618,933, filed Jul. 14 2003, which issued Apr. 26, 2006 as U.S. Pat. No. 7,034,387, titled “Semiconductor multipackage module including processor and memory package assemblies” U.S. application Ser. No. 10/618,933 claims the benefit of U.S. Provisional Application No. 60/460,541, filed Apr. 4, 2003, also titled “Semiconductor multipackage module including processor and memory package assemblies”. Each of the aforementioned U.S. Patents and U.S. Applications is hereby incorporated herein by reference.
This application is related to U.S. application Ser. No. 10/681,572, which issued Jun. 13, 2006 as U.S. Pat. No. 7,061,088, titled “Semiconductor stacked multi-package module having inverted second package”; U.S. application Ser. No. 10/681,735, which issued Jun. 6, 2006 as U.S. Pat. No. 7,057,269, titled “Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package”; U.S. application Ser. No. 10/681,833, which issued Aug. 23, 2005 as U.S. Pat. No. 6,933,598, titled “Semiconductor stacked multi-package module having inverted second package and electrically shielded first package”; U.S. application Ser. No. 10/681,747, which issued Jun. 14, 2005 as U.S. Pat. No. 6,906,416, titled “Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package”; U.S. application Ser. No. 10/681,584, which issued May 23, 2006 as U.S. Pat. No. 7,049,691, titled “Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package”; U.S. application Ser. No. 10/681,734, which issued May 30, 2006 as U.S. Pat. No. 7,053,477, titled “Semiconductor multi-package module having inverted bump chip carrier second package”; all filed Oct. 8, 2003, and each of which is hereby incorporated by reference.
FIG. 1B is a diagrammatic sketch in a sectional view illustrating the structure of a BGA, generally similar to the BGA 11 shown in FIG. 1A, except that here the molding 117 completely covers the substrate as well as the die and wire bonds, The molding configuration of FIG. 1B is formed by applying the molding compound over an array of a number of BGAs, curing the molding, and then separating the encapsulated packages, for example by saw singulation. Typically the molding in such a package has vertical walls at the edges of the package. In such a package, unlike a BGA as in FIG. 1A, no marginal portion of the upper surface of the substrate 12 is exposed and, accordingly, no electrical traces are exposed on the upper surface of the substrate. Many smaller packages currently are saw-singulated packages, often referred to as “chip scale packages.”
The top BGA in this configuration is similar to the bottom BGA, except that the top 35 BGA has z-interconnect solder balls 338 connected (through solder vias 335 in the top substrate) to the metal layer 331 only at the periphery of the top substrate. Solder balls 338 are reflowed onto the metal layer 31 of the bottom substrate to provide the z-interconnect.
Particularly, the top BGA in this configuration includes a substrate 332 having a patterned metal layer 331 onto which the top BGA die 334 is connected by flip chip bumps 336. Between the top BGA die and substrate is a polymer underfill 333. A structure as in FIG. 3 is more appropriate for high electrical performance applications, but it has similar limitations to configurations of the type shown in of FIG. 2. It presents an improvement over the FIG. 2 configuration in that the bottom BGA has no molding, allowing for use of smaller diameter (h) solder balls at the periphery of the top BGA for connection between the packages.
Referring now to FIG. 5C, bottom package z-interconnect pads 424 are formed by patterning regions of the upper metal layer situated at the margin 401 on the upper surface 425 of the bottom package substrate 412. The margin 401 extends beyond the footprint 426 of the stacked and overlying top package, defined by the edge 511 of the top package substrate 512 . The width of the margin 401 can be less about 1 mm, and, in order to provide adequate clearance for the wire bonding the width of the margin 401 may preferably be greater than about 0.2 mm. Nominally in some embodiments the margin 401 is about 0.5 mm. Where the module is saw-singulated, the margin constitutes approximately the clearance between the edge of the top package substrate and the side of the module molding.
As will be apparent from FIGS. 5A, 5B and 5C, z-interconnection between the top and bottom packages according to the invention is made by wire bond between (either bond-up or bond-down) the top package interconnect pads 524 in the margin 501 of the top package substrate and the bottom package interconnect pads 424 in the margin 401 of the bottom package substrate. The multipackage module structure is protected by formation of a module encapsulant 507 , and solder balls 418 are reflowed onto exposed solder ball pads on the lower metal layer of the bottom package substrate, for connection to underlying circuitry, such as a motherboard (not shown in the FIGS.).
For example, a top heat spreader having a thicker central region can be affixed to the upward facing surface of the top package as shown diagrammatically in a sectional view in FIG. 5D. The construction of the stacked packages in MPM 52 is generally similar to that of MPM 50 in FIG. 5A, and like structures are identified in the FIGS. by like reference numerals. The top heat spreader 530 in the example of FIG. 5D is a generally planar piece of a thermally conductive material having at least the more central area of its planar upper surface exposed to ambient for efficient heat exchange away from the MPM. The top heat spreader 530 has a thicker central portion, inboard of the wire bond sites on the top package, and the thicker portion is affixed to the upward facing side 519 of the top package using an adhesive 532. The thickness of the heat spreader may in some embodiments be in the range 0.2 to 0.6 mm, nominally 0.4 mm. The top heat spreader may be, for example, constructed of metal (such as copper, or aluminum). Where the top heat spreader is made of copper, the lower surface is preferably treated to have a black oxide, for improved adhesion to the attachment material beneath; the exposed upper surface may be treated to form a black oxide, or it may be provided with a matte nickel (plate) surface. The adhesive 532 may optionally be a thermally conductive adhesive, such as a thermally conductive epoxy, to provide improved heat dissipation; and the adhesive may be electrically nonconductive, in embodiments having exposed electrical features on the upward facing (“lower”) side. Usually the top heat spreader is affixed to the top package before the molding material is injected for the MPM encapsulation 507 . The periphery of the top heat spreader may be encapsulated with the MPM molding material. In the embodiment of FIG. 5D a step like re-entrant feature 534 is provided on the periphery of the heat spreader 530 to allow for better mechanical integrity of the structure with less delamination from the molding compound.
The bottom BGA package 400 of multipackage module 60 is provided with a metallic (for example, copper) heat spreader that acts additionally as an electrical shield to electrically contain any electromagnetic radiation from the die in the lower BGA and thereby prevent interference with the die in the upper package. An “upper” planar part of the heat spreader 406 is supported above the substrate 412 and over the die 414 by legs or vented sidewalls 407. Spots or lines 408 of an adhesive serve to affix the heat spreader support 407 to the upper surface of the bottom substrate. The adhesive can be a conductive adhesive, and can be electrically connected to the top metal layer 421 of the substrate 412, particularly to a ground plane of the circuit and thereby establishing the heat spreader as an electrical shield. To provide good shielding, the electric shield is constructed of a highly electrically conductive material, usually a metal such as aluminum or copper. Where it is copper, the copper surface is preferably treated to provide a black oxide surface, or is provided with a nickel plating, to improve adhesion. Or, the adhesive can be non-conductive and in such a configuration the heat spreader acts only as a heat spreading device. The supporting pars and the top pan of the heat spreader 406 enclose the die 414 and the wire bonds 416, and can serve to protect those structures from ambient and from mechanical stress to facilitate handling operations and, particularly, during subsequent testing before the MPM assembly. Accordingly, no separate bottom package molding is necessary in such embodiments (the MPM molding, fills in later), making for decreased manufacturing cost.
The z-interconnection between the top package 500 and the bottom package 400 according to the invention is made by wire bonds 518 between top package interconnect pads in the margin of the top package substrate 512 and bottom package interconnect pads in the margin of the bottom package substrate 400. The wire bonds may be formed in either up-bond or down-bond (forward or reverse bond) fashion. The multipackage module structure is protected by formation of a module encapsulant 607 . Openings (vents) may be provided in the supporting parts 407 of the heat spreader to allow the MPM molding material to fill in the enclosed space during encapsulation.
For example, a top heat spreader having a thicker central region can be affixed to the upward facing surface of the top package as shown diagrammatically in a sectional view in FIG. 6B. The construction of the stacked packages in MPM 62 is generally similar to that of MPM 60 in FIG. 6A, and like structures are identified in the FIGS. by like reference numerals. The top heat spreader 530 in the example of FIG. 6B is a generally planar piece of a thermally conductive material having at least the more central area of its planar upper surface exposed to ambient for efficient heat exchange away from the MPM. The top heat spreader 530 has a thicker central portion, inboard of the wire bond sites on the top package, and the thicker portion is affixed to the upward facing side 519 of the top package using an adhesive 532. The thickness of the heat spreader may in some embodiments be in the range 0.2 to 0.6 mm, nominally 0.4 mm. The top heat spreader may be, for example, constructed of metal (such as copper, or aluminum). Where the top heat spreader is made of copper, the lower surface is preferably treated to have a black oxide, for improved adhesion to the attachment material beneath; the exposed upper surface may be treated to form a black oxide, or it may be provided with a matte nickel (plate) surface. The adhesive 532 may optionally be a thermally conductive adhesive, such as a thermally conductive epoxy, to provide improved heat dissipation; and the adhesive may be electrically nonconductive, in embodiments having exposed electrical features on the upward facing (“lower”) side. Usually the top heat spreader is affixed to the top package before the molding material is injected for the MPM encapsulation 607 . The periphery of the top heat spreader may be encapsulated with the MPM molding material. In the embodiment of FIG. 6B a step like re-entrant feature 534 is provided on the periphery of the heat spreader 530 to allow for better mechanical integrity of the structure with less delamination from the molding compound.
As a further alternative, an MPM as in FIG. 6A can be provided with a simple planar heat spreader, with no supporting members, that is not attached to the upper surface of the top package molding. In such embodiments, as in the embodiment of FIG. 6B the top heat spreader can be a generally planar piece of a thermally conductive material such as, for example, a sheet of metal (such as copper or aluminum), and at least the more central area of the upper surface of the planar heat spreader is exposed to ambient for efficient heat exchange away from the MPM. Here, the heat spreader does not have a thicker central portion inboard of the wire bond sites on the upper package; instead, the space between the lower surface of the simple planar heat spreader and the upper surface 519 of the top package may be filled by a thin layer of the MPM molding, and such a simple planar heat spreader may be affixed to the MPM encapsulant 607 during the molding material curing process. The periphery of such an unattached simple planar top heat spreader can be encapsulated with the MPM molding material, as in the attached planar heat spreader of FIG. 5D, and may be provided with a step-like re-entrant feature on the periphery to allow for better mechanical integrity of the structure with less delamination from the molding compound.
The top LGA package 500 of multipackage module 70 is constructed generally similarly to the top LGA package 500 of the multipackage module 50 of FIG. 5A. Particularly, the top package 500 includes a die 514 attached onto a top package substrate 512. Any of various substrate types may be used, the top package substrate 512 shown by way of example in FIG. 7A has two metal layers 521, 523, each patterned to provide appropriate circuitry and connected by way of vias 522. The die is conventionally attached to a surface of the substrate using an adhesive, typically referred to as the die attach epoxy, shown at 513 in FIG. 7A and, in the configuration in FIG. 7A, the surface of the substrate onto which the die is attached may be referred to as the “upper” surface, and the metal layer on that surface may be referred to as the “upper” metal layer, although the die attach surface need not have any particular orientation in use, and, for purposes of description the die attach side of the upper package substrate is the downward facing side when the top package is inverted in the multi-package module according to the invention.
The z-interconnect between the stacked top package 500 and bottom package 300 is made by way of wire bonds 518 connecting the upward-facing metal layers of the respective package substrates. The multipackage module structure is protected by formation of a module encapsulant 707 , and solder balls 318 are reflowed onto exposed solder ball pads on the lower metal layer of the bottom package substrate, for connection to underlying circuitry, such as a motherboard (not shown in the FIGS.) of a final product, such as a computer. Solder masks 315, 327 are patterned over the metal layers 321, 323 to expose the underlying metal at bonding sites for electrical connection, for example the wire bond sites and bonding pads for bonding the wire bonds 518 and solder balls 318.
The z-interconnection between the top package 500 and the bottom package 300 according to the invention is made by wire bonds 518 between top package interconnect pads in the margin of the top package substrate 512 and bottom package interconnect pads in the margin of the bottom package substrate 300. The wire bonds may be formed in either up-bond or down-bond (forward or reverse bonding) fashion. The multipackage module structure is protected by formation of a module encapsulant 707 . Openings may be provided in the supporting parts 407 of the heat spreader to allow the MPM molding material to fill in the enclosed space during encapsulation.
For example, a top heat spreader having a thicker central region can be affixed to the upward facing surface of the top package as shown diagrammatically in a sectional view in FIG. 7C. The construction of the stacked packages in MPM 74 is generally similar to that of MPM 72 in FIG. 7B, and like structures are identified in the FIGS. by like reference numerals. The top heat spreader 530 in the example of FIG. 7C is a generally planar piece of a thermally conductive material having at least the more central area of its planar upper surface exposed to ambient for efficient heat exchange away from the MPM. The top heat spreader 530 has a thicker central portion, inboard of the wire bond sites on the top package, and the thicker portion is affixed to the upward facing side 519 of the top package using an adhesive 532. The thickness of the heat spreader may in some embodiments be in the range 0.2 to 0.6 mm, nominally 0.4 mm. The top heat spreader may be, for example, constructed of metal (such as copper, or aluminum). Where the top heat spreader is made of copper, the lower surface is preferably treated to have a black oxide, for improved adhesion to the attachment material beneath; the exposed upper surface may be treated to form a black oxide, or it may be provided with a matte nickel (plate) surface. The adhesive 532 may optionally be a thermally conductive adhesive, such as a thermally conductive epoxy, to provide improved heat dissipation; and the adhesive may be electrically nonconductive, in embodiments having exposed electrical features on the upward facing (“lower”) side. Usually the top heat spreader is affixed to the top package before the molding material is injected for the MPM encapsulation 707 . The periphery of the top heat spreader may be encapsulated with the MPM molding material. In the embodiment of FIG. 7C a step like re-entrant feature 534 is provided on the periphery of the heat spreader 530 to allow for better mechanical integrity of the structure with less delamination from the molding compound.
As the FIG. illustrates, this structure provides for a thinner MPM because the bottom package die is on the underside of the bottom package in the area between the peripherally situated solder balls. Such a configuration can have a higher electrical performance not only because it employs a flip chip connection but also because it provides more direct electrical connection of the die to the solder balls, with shorter metal traces and without requiring vias (as are required in a configuration as in FIGS. 7A or 7B or 7C) for connection between the die and the solder balls. Furthermore the die-up configuration enables this package to be netlist compatible to wire bonding, as may be desired in some applications. Netlist is the sum of all pairs of connections between the die and the solder balls. When the die faces up “die-down” it has a connection pattern that is the mirror image of the pattern in the same die when the die is facing down “die-up”.
In a configuration as in FIG. 8A the top LGA package is inverted and attached with adhesive onto the upper side of the BGA, and then is wire bonded and the module is molded. The bottom flip chip BGA package 302 includes a substrate 342 having a patterned metal layer 353 onto parts of which the die 344 is connected by flip chip bumps 346, such as solder bumps, gold stud bumps or anisotropically conducting film or paste. Any of various substrate types may be used; the bottom package substrate 342 shown by way of example in FIG. 8A has two metal layers 351, 363, each patterned to provide appropriate circuitry. Bottom package substrate 342 additionally has a metal layer 355 sandwiched between dielectric layers 354, 356. Metal layer 355 has voids at selected locations, to permit connection of the metal layers 351, 353 by vias therethrough and, accordingly, selected parts of the patterned metal layers 351, 353 are connected by way of vias through the substrate layers 354, 356 and through the voids in the sandwiched metal layer 355. Selected parts of the patterned metal layer 363 are connected by way of vias through substrate layer 356 to sandwiched metal layer 355.
As noted above, the metal layers 361, 353 are patterned to provide appropriate circuitry, and the sandwiched metal layer 355 has voids at selected locations to allow interconnections (without contact with the sandwiched metal layer 356) between selected traces on the upper and lower metal layers 351, 353. Particularly, for example, the lower metal layer is patterned in the die attach area to provide attachment sites for the flip chip interconnect bumps 353; and, for example, the lower metal layer is patterned nearer the margin of the bottom package substrate 342 to provide attachment sites for the second-level interconnect solder balls 348, by which the completed MPM is attached by solder reflow to underlying circuitry (not shown). And particularly, for example, the upper metal layer is patterned near the margin of the bottom package substrate 342 to provide attachment sites for wire bonds connecting the top package to the bottom package. Ground lines in the circuitry of metal layer 353 are connected through vias to the sandwiched metal layer 355; selected ones of the solder balls 348 are ground balls, which will be attached to ground lines in the underlying circuitry when the MPM is installed. Thus, the sandwiched metal layer 355 serves as a ground plane for the MPM. Selected others of the solder balls 348 are input/output balls or power balls, and these are, accordingly, attached to solder ball sites on input/output or power lines, respectively, in the circuitry of metal layer 353.
Particularly, referring to FIG. 8B, the bottom BGA package 300 of multipackage module 82 is provided with a metallic (for example, copper) heat spreader that surrounds the die and acts additionally as an electrical shield to electrically contain any electromagnetic radiation from the die in the lower BGA and thereby prevent interference with the die in the upper package. A lower planar part 304 of the heat spreader is supported on the substrate 342 by legs or sidewalls 306. Spots or lines 306 of an adhesive serve to affix the heat spreader supports 305 to the lower surface of the bottom package substrate. The adhesive can be a conductive adhesive, and can be electrically connected to the lower metal layer 353 of the substrate 342, particularly to a ground plane of the circuit and thereby establishing the heat spreader as an electrical shield. Or, the adhesive can be non-conductive and in such a configuration the heat spreader acts only as a heat spreading device. Alternatively, the shield enclosing the upward-facing bottom package die can be soldered or affixed using adhesive to the printed circuit board (or other installation surface for the module) at the time the solder balls are reflowed to make the connection during installation of the module. Such an arrangement can provide an additional path for heat transfer, and can additionally provide electrical connection of the shield to the installation board, as may be desired for some applications. The supporting parts 305 and the lower planar part 304 of the heat spreader enclose the die 344 , and can serve for protection from ambient and from mechanical stress to facilitate handling operations and, particularly, during subsequent testing before the MPM assembly.
For example, a top heat spreader having a thicker central region can be affixed to the upward facing surface of the top package as shown diagrammatically in a sectional view in FIG. 8C. The construction of the stacked packages in MPM 84 is generally similar to that of MPM 82 in FIG. 8B, and like structures are identified in the FIGS. by like reference numerals. The top heat spreader 530 in the example of FIG. 8C is a generally planar piece of a thermally conductive material having at least the more central area of its planar upper surface exposed to ambient for efficient heat exchange away from the MPM. The top heat spreader 530 has a thicker central portion, inboard of the wire bond sites on the top package, and the thicker portion is affixed to the upward facing side 519 of the top package using an adhesive 532. The thickness of the heat spreader may in some embodiments be in the range 0.2 to 0.6 mm, nominally 0.4 mm. The top heat spreader may be, for example, constructed of metal (such as copper, or aluminum). Where the top heat spreader is made of copper, the lower surface is preferably treated to have a black oxide, for improved adhesion to the attachment material beneath; the exposed upper surface may be treated to form a black oxide, or it may be provided with a matte nickel (plate) surface. The adhesive 532 may optionally be a thermally conductive adhesive, such as a thermally conductive epoxy, to provide improved heat dissipation; and the adhesive may be electrically nonconductive, in embodiments having exposed electrical features on the upward facing (“lower”) side. Usually the top heat spreader is affixed to the top package before the molding material is injected for the MPM encapsulation 807. The periphery of the top heat spreader may be encapsulated with the MPM molding material. In the embodiment of FIG. 8C a step like re-entrant feature 534 is provided on the periphery of the heat spreader 530 to allow for better mechanical integrity of the structure with less delamination from the molding compound.
In as much as no part of the upper surface of the bottom package substrate in the die-up configuration is occupied by the bottom package die, a plurality of top packages can be stacked over a plurality of package attach regions on the bottom package upper surface. This is illustrated by way of example in FIG. 8D. FIG. 8D is a diagrammatic sketch in a sectional view thru an embodiment of a multipackage module generally at 86, having a processor unit affixed to the lower surface of the bottom package generally as shown in FIG. 5A (flip chip mounted in a “die-up” configuration), and a plurality of inverted LGA packages affixed to the upper side of the bottom package substrate according to an aspect of the invention.
In the illustrative embodiment of FIG. 8D, a module substrate 816, also 836, has a “lower” surface onto which solder balls 818 are attached, for connection by solder reflow to, for example, a printed circuit board (not shown). A bottom package die 820 is mounted onto a die mounting portion of the lower surface of the module 816. As shown in this example, the processor 820 has a flip-chip configuration; it includes a die 824 electrically connected by way of balls or bumps 828 to interconnect sites (not shown) in the lower surface of the module substrate, and affixed to the surface using an adhesive underfill material 825. A plurality of top packages 830, 830′ (there may typically be four memory packages; two are shown in the view of FIG. 8D) are mounted on the upper surface of the module substrate 836. In the embodiment illustrated in FIG. 8D the top packages are inverted saw-singulated land grid array (LGA) packages. Referring particularly to LGA package 830, each LGA top package includes a die 834 affixed using an adhesive to a top package substrate 836. The package substrate is, in this example, a two-metal layer laminate, having patterned electrically conductive traces on the upper and lower surfaces of a dielectric layer; selected upper and lower traces are connected by way of vias (not shown) through the dielectric layer. The downward-facing active surface of the die is electrically connected to traces on the die attach “upper” (downward facing) surface of the top package substrate 836 by wire bonds 832. The active surface of the die and the wire bonds are protected by an encapsulant 837. Further referring to FIG. 8D, the inverted top packages 830, 830′ are affixed to the bottom package module substrate 836 using an adhesive material 815, 815′ between the surface of the encapsulant 837 and the upper surface of the bottom package substrate 836; and wire bonds 838 attached to wire bond pads on the upper surface of the top package substrate 835 provide for electrical connection to wire bond pads in the upper surface of the bottom substrate 836. Additionally, passive devices, e.g., 819, can be affixed to and electrically connected to traces in the upper surface of the bottom package substrate 816. Also, in the illustrative example shown in FIG. 8D, a heat spreader 814 is mounted onto the upper surface of the module substrate and covers top packages 830, 830′; and the top packages and the attachment arms of the heat spreader are encapsulated using an encapsulant material 817. A module such as is illustrated by way of example in FIG. 8D, where the processor is a GPU, for example, may typically have a module footprint about 31 mm×31 mm and an overall profile thickness about 2.8 mm or greater, with a 10.5 mm×10.5 mm GPU and 12 mm×12 mm memory BGA packages.
The module as shown for example in FIG. 9B is provided with a top heat spreader. The top heat spreader 530 in the example of FIG. 9B is a generally planar piece of a thermally conductive material having at least the more central area of its planar upper surface exposed to ambient for efficient heat exchange away from the MPM. The top heat spreader 530 has a thicker central portion, inboard of the wire bond sites on the top package, and the thicker portion is affixed to the upward facing side of the top package using an adhesive 532. The thickness of the heat spreader may in some embodiments be in the range 0.2 to 0.6 mm, nominally 0.4 mm. The top heat spreader may be, for example, constructed of metal (such as copper, or aluminum). Where the top heat spreader is made of copper, the lower surface is preferably treated to have a black oxide, for improved adhesion to the attachment material beneath; the exposed upper surface may be treated to form a black oxide, or it may be provided with a matte nickel (plate) surface. The adhesive 532 may optionally be a thermally conductive adhesive, such as a thermally conductive epoxy, to provide improved heat dissipation; and the adhesive may be electrically nonconductive, in embodiments having exposed electrical features on the upward facing (“lower”) side. Usually the top heat spreader is affixed to the top package before the molding material is injected for the MPM encapsulation 907 . The periphery of the top heat spreader may be encapsulated with the MPM molding material. In the embodiment of FIG. 9B a step like re-entrant feature 534 is provided on the periphery of the heat spreader 530 to allow for better mechanical integrity of the structure with less delamination from the molding compound.
FIGS. 10A and 10B show examples of multipackage modules, generally at 100 and at 102, respectively, having inverted BCC top packages 1000, 1020, respectively, stacked over BCC bottom packages 1400 according to the invention. The BCC bottom packages in these examples are BGA packages substantially similar to the BGA bottom package as shown in FIG. 5A, for example, and the various parts, readily identifiable by reference to FIG. 5A, are not separately renumbered in FIGS. 10A and 10B. The top BCC type package 1000 in FIG. 10A includes a die 1002 affixed using an adhesive 1003 to an “upper” surface of a die attach portion 1004 of a built-up lead frame structure additionally having interconnect leads 1006. The die is interconnected by wire bonds 1005 connecting pads on the active side of the die with the “upper” surface of corresponding leads 1006. As noted above, the BCC according to the invention may be a standard BCC, having standoff bumps on the leads; or, because there is no need for standoff, the leads may be substantially flat, as may be preferred. The die 1002, the wire bonds 1005, and the exposed upper surfaces of the leads 1006 are protected by an encapsulation 1007 . The top packages 1000 may be made in array fashion, and saw- or punch-singulated to provide separate top packages for subsequent processing.
FIG. 15 is a flow diagram showing a process for assembly of a multi-package module in which the bottom package is a flip chip package in a die-down configuration. In a step 1502, an unsingulated strip of die-down flip chip ball grid array bottom packages is provided. The BGA packages may or may not be provided with molding, and are provided without second-level interconnect solder balls. The BGA packages in the strip preferably are tested (as indicated in the FIG. by *) for performance and reliability before they are taken to subsequent steps in the process. Only packages identified as “good” are subjected to subsequent treatment. In a step 1504, adhesive is dispensed onto the upper surface (back side) of the die on “good” BGA packages. In a step 1506, singulated land grid array packages are provided. The singulated LGA packages are protected by a molding, and preferably are tested (*) and identified as “good”. In a step 1508, a pick-and-place operation is carried out to invert and place “good” LGA packages on the adhesive over the die on the “good” BGA packages. In a step 1510, the adhesive is cured. In a step 1512, a plasma clean operation is performed in preparation for a step 1614 in which wire bond z-interconnections are formed between the stacked top LGA and bottom BGA packages. In a step 1516, an additional plasma clean may be performed, followed by the formation of the MPM molding in a step 1518. In a step 1520, the second-level interconnect solder balls are attached to the underside of the module. In a step 1522, the completed modules are tested (*) and singulated from the strip, for example by saw singulation or by punch singulation, and packaged for further use.
FIG. 16 is a flow diagram showing a process for assembly of a multi-package module in which the bottom package is a flip chip package in a die-down configuration, and in which the module os further provided with a heat shield. This process is similar to the one shown in FIG. 15, with an additional step interposed for installation of the shield over the bottom package flip chip die. Like steps in the process are identified by like reference numerals in the FIGS. In a step 1602, an unsingulated strip of die-down flip chip ball grid array bottom packages is provided. The BGA packages may or may not be provided with molding, and are provided without second-level interconnect solder balls. The BGA packages in the strip preferably are tested (as indicated in the FIG. by *) for performance and reliability before they are taken to subsequent steps in the process. Only packages identified as “good” are subjected to subsequent treatment. In a step 1603, the electrical shield is affixed over the die on “good” bottom BGA packages. In a step 1604, adhesive is dispensed onto the upper surface of the shield on “good” BGA packages. In a step 1606, singulated land grid array packages are provided. The singulated LGA packages are protected by a molding, and preferably are tested (*) and identified as “good”. In a step 1608, a pick-and-place operation is carried out to invert and place “good” LGA packages on the adhesive over the shields on the “good” BGA packages. In a step 1610, the adhesive is cured. In a step 1612, a plasma clean operation is performed in preparation for a step 1614 in which wire bond z-interconnections are formed between the stacked top LGA and bottom BGA packages. In a step 1616, an additional plasma clean may be performed, followed by the formation of the MPM molding in a step 1618. In a step 1620, the second-level interconnect solder balls are attached to the underside of the module. In a step 1622, the completed modules are tested (*) and singulated from the strip, for example by saw singulation or by punch singulation, and packaged for further use.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5222014Mar 2, 1992Jun 22, 1993Motorola, Inc.Three-dimensional multi-chip pad array carrierUS5229960Dec 4, 1991Jul 20, 1993Matra Marconi Space FranceSolid state memory modules and memory devices including such modulesUS5340771Mar 18, 1993Aug 23, 1994Lsi Logic CorporationTechniques for providing high I/O count connections to semiconductor diesUS5373189Jul 30, 1993Dec 13, 1994Commissariate A L'energie AtomiqueThree-dimensional multichip moduleUS5436203Jul 5, 1994Jul 25, 1995Motorola, Inc.Shielded liquid encapsulated semiconductor device and method for making the sameUS5444296Nov 22, 1993Aug 22, 1995Sun Microsystems, Inc.Ball grid array packages for high speed applicationsUS5495398Jun 5, 1995Feb 27, 1996National Semiconductor CorporationStacked multi-chip modules and method of manufacturingUS5550711May 8, 1995Aug 27, 1996Staktek CorporationUltra high density integrated circuit packagesUS5652185Apr 7, 1995Jul 29, 1997National Semiconductor CorporationMaximized substrate design for grid array based assembliesUS5744863Jun 7, 1995Apr 28, 1998International Business Machines CorporationChip carrier modules with heat sinks attached by flexible-epoxyUS5898219Apr 2, 1997Apr 27, 1999Intel CorporationCustom corner attach heat sink design for a plastic ball grid array integrated circuit packageUS5899705Apr 30, 1998May 4, 1999Akram; SalmanStacked leads-over chip multi-chip moduleUS5903049May 6, 1998May 11, 1999Mitsubishi Denki Kabushiki KaishaSemiconductor module comprising semiconductor packagesUS5977640Jun 26, 1998Nov 2, 1999International Business Machines CorporationHighly integrated chip-on-chip packagingUS5982633Aug 20, 1997Nov 9, 1999Compaq Computer CorporationOpposed ball grid array mountingUS5994166Mar 10, 1997Nov 30, 1999Micron Technology, Inc.Method of constructing stacked packagesUS6025648Apr 16, 1998Feb 15, 2000Nec CorporationShock resistant semiconductor device and method for producing sameUS6034875Jun 17, 1998Mar 7, 2000International Business Machines CorporationCooling structure for electronic componentsUS6075289Nov 4, 1996Jun 13, 2000Tessera, Inc.Thermally enhanced packaged semiconductor assembliesUS6118176Apr 26, 1999Sep 12, 2000Advanced Semiconductor Engineering, Inc.Stacked chip assembly utilizing a lead frameUS6133626Sep 24, 1998Oct 17, 2000Gennum CorporationThree dimensional packaging configuration for multi-chip module assemblyUS6157080Nov 5, 1998Dec 5, 2000Sharp Kabushiki KaishaSemiconductor device using a chip scale packageUS6201266Dec 15, 1999Mar 13, 2001Oki Electric Industry Co., Ltd.Semiconductor device and method for manufacturing the sameUS6201302Dec 31, 1998Mar 13, 2001Sampo Semiconductor CorporationSemiconductor package having multi-diesUS6238949Jun 18, 1999May 29, 2001National Semiconductor CorporationMethod and apparatus for forming a plastic chip on chip package moduleUS6265766Jan 14, 2000Jul 24, 2001Micron Technology, Inc.Flip chip adaptor package for bare dieUS6274930Jun 29, 2000Aug 14, 2001Micron Technology, Inc.Multi-chip module with stacked diceUS6316838Mar 20, 2000Nov 13, 2001Fujitsu LimitedSemiconductor deviceUS6333552Aug 5, 1999Dec 25, 2001Sharp Kabushiki KaishaMillimeter wave semiconductor deviceUS6340846Dec 6, 2000Jan 22, 2002Amkor Technology, Inc.Making semiconductor packages with stacked dies and reinforced wire bondsUS6376904Oct 10, 2000Apr 23, 2002Rambus Inc.Redistributed bond pads in stacked integrated circuit die packageUS6388313Jan 30, 2001May 14, 2002Siliconware Precision Industries Co., Ltd.Multi-chip moduleUS6400007Apr 16, 2001Jun 4, 2002Kingpak Technology Inc.Stacked structure of semiconductor means and method for manufacturing the sameUS6407456Feb 23, 2000Jun 18, 2002Micron Technology, Inc.Multi-chip device utilizing a flip chip and wire bond assemblyUS6413798Apr 9, 2001Jul 2, 2002Kabushiki Kaisha ToshibaPackage having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the sameUS6414381Feb 1, 2000Jul 2, 2002Fujitsu Media Devices LimitedInterposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit boardUS6424050Sep 20, 2000Jul 23, 2002Seiko Epson CorporationSemiconductor deviceUS6441496Jan 23, 2001Aug 27, 2002Wen Chuan ChenStructure of stacked integrated circuitsUS6445064Jul 18, 2001Sep 3, 2002Mitsubishi Denki Kabushiki KaishaSemiconductor deviceUS6462421Apr 10, 2000Oct 8, 2002Advanced Semicondcutor Engineering, Inc.Multichip moduleUS6472732Mar 21, 2000Oct 29, 2002Oki Electric Industry Co., Ltd.BGA package and method for fabricating the sameUS6472741Jul 14, 2001Oct 29, 2002Siliconware Precision Industries Co., Ltd.Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the sameUS6489676Apr 30, 2001Dec 3, 2002Fujitsu LimitedSemiconductor device having an interconnecting post formed on an interposer within a sealing resinUS6492726Sep 22, 2000Dec 10, 2002Chartered Semiconductor Manufacturing Ltd.Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnectionUS6501165Jun 3, 2002Dec 31, 2002Micron Technology, Inc.Stackable semiconductor package having conductive layer and insulating layers and method of fabricationUS6512303Jul 23, 2001Jan 28, 2003Micron Technology, Inc.Flip chip adaptor package for bare dieUS6538319Feb 7, 2001Mar 25, 2003Oki Electric Industry Co., Ltd.Semiconductor deviceUS6545365Feb 13, 2001Apr 8, 2003Mitsubishi Denki Kabushiki KaishaResin-sealed chip stack type semiconductor deviceUS6545366Jun 25, 2001Apr 8, 2003Mitsubishi Denki Kabushiki KaishaMultiple chip package semiconductor deviceUS6552423Feb 15, 2001Apr 22, 2003Samsung Electronics Co., Ltd.Higher-density memory cardUS6555902Jun 28, 2001Apr 29, 2003Siliconware Precision Industries Co., Ltd.Multiple stacked-chip packaging structureUS6570249Jan 30, 2002May 27, 2003Siliconware Precision Industries Co., Ltd.Semiconductor packageUS6583503May 2, 2002Jun 24, 2003Micron Technology, Inc.Semiconductor package with stacked substrates and multiple semiconductor diceUS6590281Jan 30, 2002Jul 8, 2003Siliconware Precision Industries Co., Ltd.Crack-preventive semiconductor packageUS6593647Mar 29, 2002Jul 15, 2003Oki Electric Industry Co., Ltd.Semiconductor deviceUS6593648Aug 30, 2001Jul 15, 2003Seiko Epson CorporationSemiconductor device and method of making the same, circuit board and electronic equipmentUS6593662Aug 2, 2000Jul 15, 2003Siliconware Precision Industries Co., Ltd.Stacked-die package structureUS6599779Sep 24, 2001Jul 29, 2003St Assembly Test Service Ltd.PBGA substrate for anchoring heat sinkUS6607937Aug 23, 2000Aug 19, 2003Micron Technology, Inc.Stacked microelectronic dies and methods for stacking microelectronic diesUS6611063Sep 18, 2000Aug 26, 2003Nec Electronics CorporationResin-encapsulated semiconductor deviceUS6621169Aug 29, 2001Sep 16, 2003Fujitsu LimitedStacked semiconductor device and method of producing the sameUS6621172Apr 27, 2001Sep 16, 2003Seiko Epson CorporationSemiconductor device and method of fabricating the same, circuit board, and electronic equipmentUS6649448Sep 25, 2001Nov 18, 2003Hitachi, Ltd.Method of manufacturing a semiconductor device having flexible wiring substrateUS6650019Aug 20, 2002Nov 18, 2003Amkor Technology, Inc.Method of making a semiconductor package including stacked semiconductor diesUS6657290Jan 15, 2002Dec 2, 2003Sharp Kabushiki KaishaSemiconductor device having insulation layer and adhesion layer between chip laminationUS6667556Nov 22, 2002Dec 23, 2003Micron Technology, Inc.Flip chip adaptor package for bare dieUS6690089Sep 5, 2002Feb 10, 2004Oki Electric Industry Co., Ltd.Semiconductor device having multi-chip packageUS6700178Apr 19, 2001Mar 2, 2004Advanced Semiconductor Engineering, Inc.Package of a chip with beveled edgesUS6706557Apr 24, 2003Mar 16, 2004Micron Technology, Inc.Method of fabricating stacked die configurations utilizing redistribution bond padsUS6716676Sep 19, 2002Apr 6, 2004Siliconware Precision Industries Co., Ltd.Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the sameUS6734539Sep 26, 2001May 11, 2004Lucent Technologies Inc.Stacked module packageUS6734552Jul 11, 2001May 11, 2004Asat LimitedEnhanced thermal dissipation integrated circuit packageUS6737750Dec 7, 2001May 18, 2004Amkor Technology, Inc.Structures for improving heat dissipation in stacked semiconductor packagesUS6746894Apr 19, 2001Jun 8, 2004Micron Technology, Inc.Ball grid array interposer, packages and methodsUS6747361Jul 24, 2001Jun 8, 2004Nec Electronics CorporationSemiconductor device and packaging method thereofUS6762488Mar 7, 2003Jul 13, 2004Nec Electronics CorporationLight thin stacked package semiconductor device and process for fabrication thereofUS6777799Jul 22, 2003Aug 17, 2004Fujitsu LimitedStacked semiconductor device and method of producing the sameUS6777819Oct 23, 2001Aug 17, 2004Siliconware Precision Industries Co., Ltd.Semiconductor package with flash-proof deviceUS6787915Aug 16, 2001Sep 7, 2004Oki Electric Industry Co., Ltd.Rearrangement sheet, semiconductor device and method of manufacturing thereofUS6787916Sep 13, 2001Sep 7, 2004Tru-Si Technologies, Inc.Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavityUS6794749Feb 26, 2002Sep 21, 2004Micron Technology, Inc.Chip package with grease heat sinkUS6818980May 7, 2003Nov 16, 2004Asat Ltd.Stacked semiconductor package and method of manufacturing the sameUS6828665Dec 13, 2002Dec 7, 2004Siliconware Precision Industries Co., Ltd.Module device of stacked semiconductor packages and method for fabricating the sameUS6835598Mar 3, 2003Dec 28, 2004Samsung Electronics Co., Ltd.Stacked semiconductor module and method of manufacturing the sameUS6838761Aug 2, 2003Jan 4, 2005Chippac, Inc.Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shieldUS6847105Sep 21, 2001Jan 25, 2005Micron Technology, Inc.Bumping technology in stacked die configurationsUS6864566May 28, 2002Mar 8, 2005Samsung Electronics Co., Ltd.Duel die packageUS6882057Sep 19, 2003Apr 19, 2005Via Technologies, Inc.Quad flat no-lead chip carrierUS6890798Jan 23, 2001May 10, 2005Intel CorporationStacked chip packagingUS6900528Jun 21, 2001May 31, 2005Micron Technology, Inc.Stacked mass storage flash memory packageUS6906415Jun 27, 2002Jun 14, 2005Micron Technology, Inc.Semiconductor device assemblies and packages including multiple semiconductor devices and methodsUS6906416Oct 8, 2003Jun 14, 2005Chippac, Inc.Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) packageUS6930378Nov 10, 2003Aug 16, 2005Amkor Technology, Inc.Stacked semiconductor die assembly having at least one supportUS6930396Apr 3, 2003Aug 16, 2005Nec Electronics CorporationSemiconductor device and method for manufacturing the sameUS6933598Oct 8, 2003Aug 23, 2005Chippac, Inc.Semiconductor stacked multi-package module having inverted second package and electrically shielded first packageUS6951982Dec 18, 2002Oct 4, 2005Micron Technology, Inc.Packaged microelectronic component assembliesUS6972481Aug 2, 2003Dec 6, 2005Chippac, Inc.Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packagesUS7034387Jul 14, 2003Apr 25, 2006Chippac, Inc.Semiconductor multipackage module including processor and memory package assembliesUS7034388Jun 15, 2004Apr 25, 2006Advanced Semiconductor Engineering, Inc.Stack type flip-chip packageUS7163842 *Mar 13, 2006Jan 16, 2007Chip Pac, Inc.Method of fabricating a semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA)* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7981702 *Mar 8, 2006Jul 19, 2011Stats Chippac Ltd.Integrated circuit package in package systemUS7986043Mar 8, 2006Jul 26, 2011Stats Chippac Ltd.Integrated circuit package on package systemUS8164172Jun 22, 2011Apr 24, 2012Stats Chippac Ltd.Integrated circuit package in package systemUS20070210424 *Mar 8, 2006Sep 13, 2007Stats Chippac Ltd.Integrated circuit package in package systemUS20070210443 *Mar 8, 2006Sep 13, 2007Stats Chippac Ltd.Integrated circuit package on package systemUS20130241044 *Nov 5, 2012Sep 19, 2013Samsung Electronics Co., Ltd.Semiconductor package having protective layer and method of forming the same* Cited by examinerClassifications U.S. Classification438/108, 228/180.22, 257/784, 257/686, 438/109, 257/E25.013, 257/E23.101, 257/E25.023, 257/E25.011International ClassificationB23K31/02, H01L21/48, H01L23/02Cooperative ClassificationH01L2224/48, H01L2924/19105, H01L2924/181, H01L24/73, H01L2224/16225, H01L2224/32225, H01L2224/73204, H01L2924/01078, H01L25/105, H01L25/0652, H01L2924/1532, H01L2924/01029, H01L21/563, H01L23/36, H01L2924/3025, H01L2924/16152, H01L2924/19107, H01L2924/30107, H01L2924/01046, H01L2224/48465, H01L25/03, H01L2924/15331, H01L2924/01079, H01L2225/06589, H01L2225/0651, H01L2224/48227, H01L25/0657, H01L23/4334, H01L2924/15311, H01L23/3128, H01L2924/01013, H01L23/552, H01L2225/06572, H01L2224/73265, H01L2924/1433, H01L2224/48091, H01L2224/73203, H01L2225/1023, H01L2225/1058, H01L2225/1052, H01L2225/1094, H01L2225/1005European ClassificationH01L25/03, H01L23/433E, H01L23/31H2B, H01L23/552, H01L25/10J, H01L25/065M, H01L25/065S, H01L23/36Legal EventsDateCodeEventDescriptionOct 3, 2011FPAYFee paymentYear of fee payment: 4Aug 6, 2015ASAssignmentOwner name: STATS CHIPPAC, INC., DELAWAREFree format text: MERGER AND CHANGE OF NAME;ASSIGNORS:CHIPPAC, INC.;STATS CHIPPAC, INC.;REEL/FRAME:036286/0612Effective date: 20050120Owner name: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITYFree format text: SECURITY INTEREST;ASSIGNORS:STATS CHIPPAC, INC.;STATS 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