Source: https://patents.google.com/patent/US9589607B2/en
Timestamp: 2019-11-21 02:01:45
Document Index: 84294510

Matched Legal Cases: ['Application No. 10', 'Application No. 10', 'Application No. 2016', 'Application No. 201480011890', 'Application No. 2015', 'Application No. 201480050838', 'Application No. 103107275', 'Application No. 14760332']

US9589607B2 - Apparatuses and methods for performing logical operations using sensing circuitry - Google Patents
US9589607B2
US9589607B2 US15/051,112 US201615051112A US9589607B2 US 9589607 B2 US9589607 B2 US 9589607B2 US 201615051112 A US201615051112 A US 201615051112A US 9589607 B2 US9589607 B2 US 9589607B2
US15/051,112
US20160172015A1 (en
2014-11-11 Priority to US14/538,399 priority patent/US9275701B2/en
2016-02-23 Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MANNING, TROY A.
2016-02-23 Priority to US15/051,112 priority patent/US9589607B2/en
2016-02-23 Application filed by Micron Technology Inc filed Critical Micron Technology Inc
2016-06-16 Publication of US20160172015A1 publication Critical patent/US20160172015A1/en
2017-03-07 Publication of US9589607B2 publication Critical patent/US9589607B2/en
This application is a Continuation of U.S. application Ser. No. 14/538,399, filed Nov. 11, 2014, which issues as U.S. Pat. No. 9,275,701 on Mar. 1, 2016, which is a Continuation of U.S. application Ser. No. 13/962,399, filed Aug. 8, 2013, which issued as U.S. Pat. No. 8,971,124 on Mar. 3, 2015, the contents of which are included herein by reference.
The array 230 is coupled to sensing circuitry in accordance with a number of embodiments of the present disclosure. In this example, the sensing circuitry comprises a sense amplifier 206 and a compute component 231. The sensing circuitry can be sensing circuitry 150 shown in FIG. 1. The sense amplifier 206 is coupled to the complementary sense lines D, D— corresponding to a particular column of memory cells. The sense amplifier 206 can be a sense amplifier such as sense amplifier 306 described below in association with FIG. 3. As such, the sense amp 206 can be operated to determine a state (e.g., logic data value) stored in a selected cell. Embodiments are not limited to the example sense amplifier 206. For instance, sensing circuitry in accordance with a number of embodiments described herein can include current-mode sense amplifiers and/or single-ended sense amplifiers (e.g., sense amplifiers coupled to one sense line).
At time t1, the equilibration signal 226 is deactivated, and then a selected row is activated (e.g., the row corresponding to a memory cell whose data value is to be sensed and used as a first input). Signal 204-0 represents the voltage signal applied to the selected row (e.g., row 204-0). When row signal 204-0 reaches the threshold voltage (Vt) of the access transistor (e.g., 202) corresponding to the selected cell, the access transistor turns on and couples the sense line D to the selected memory cell (e.g., to the capacitor 203 if the cell is a 1T1C DRAM cell), which creates a differential voltage signal between the sense lines D and D— (e.g., as indicated by signals 205-1 and 205-2, respectively) between times t2 and t3. The voltage of the selected cell is represented by signal 203. Due to conservation of energy, creating the differential signal between D and D— (e.g., by coupling the cell to sense line D) does not consume energy, since the energy associated with activating/deactivating the row signal 204 can be amortized over the plurality of memory cells coupled to the row.
At time t9, the sense lines D and D— are equilibrated (e.g., equilibration signal 226 is activated), as illustrated by sense line voltage signals 205-1 and 205-2 moving from their respective rail values to the equilibration voltage 225 (VDD/2). The equilibration consumes little energy due to the law of conservation of energy. As described below in association with FIG. 3, equilibration can involve shorting the complementary sense lines D and D— together at an equilibration voltage, which is VDD/2, in this example. Equilibration can occur, for instance, prior to a memory cell sensing operation.
As shown in timing diagrams 285-2 and 285-3, at time t1, equilibration is disabled (e.g., the equilibration signal 226 is deactivated), and then a selected row is activated (e.g., the row corresponding to a memory cell whose data value is to be sensed and used as an input such as a second input, third input, etc.). Signal 204-1 represents the voltage signal applied to the selected row (e.g., row 204-1). When row signal 204-1 reaches the threshold voltage (Vt) of the access transistor (e.g., 202) corresponding to the selected cell, the access transistor turns on and couples the sense line D to the selected memory cell (e.g., to the capacitor 203 if the cell is a 1T1C DRAM cell), which creates a differential voltage signal between the sense lines D and D— (e.g., as indicated by signals 205-1 and 205-2, respectively) between times t2 and t3. The voltage of the selected cell is represented by signal 203. Due to conservation of energy, creating the differential signal between D and D— (e.g., by coupling the cell to sense line D) does not consume energy, since the energy associated with activating/deactivating the row signal 204 can be amortized over the plurality of memory cells coupled to the row.
Since the accumulator was previously activated, activating only Passd (211-1) results in accumulating the data value corresponding to the voltage signal 205-1. Similarly, activating only Passdb (211-2) results in accumulating the data value corresponding to the voltage signal 205-2. For instance, in an example AND/NAND operation (e.g., timing diagram 285-2) in which only Passd (211-1) is activated, if the data value stored in the selected memory cell (e.g., a Row1 memory cell in this example) is a logic 0, then the accumulated value associated with the secondary latch is asserted low such that the secondary latch stores logic 0. If the data value stored in the Row1 memory cell is not a logic 0, then the secondary latch retains its stored Row0 data value (e.g., a logic 1 or a logic 0). As such, in this AND/NAND operation example, the secondary latch is serving as a zeroes (0s) accumulator. Similarly, in an example OR/NOR operation (e.g., timing diagram 285-3) in which only Passdb is activated, if the data value stored in the selected memory cell (e.g., a Row1 memory cell in this example) is a logic 1, then the accumulated value associated with the secondary latch is asserted high such that the secondary latch stores logic 1. If the data value stored in the Row1 memory cell is not a logic 1, then the secondary latch retains its stored Row0 data value (e.g., a logic 1 or a logic 0). As such, in this OR/NOR operation example, the secondary latch is effectively serving as a ones (1s) accumulator since voltage signal 205-2 on D— is setting the true data value of the accumulator.
TABLE 1 Operation FIG. 2B FIG. 2C-1 FIG. 2C-2 FIG. 2D-1 FIG. 2D-2 AND First phase R-1 Last phase iterations NAND First phase R-1 Last phase iterations OR First phase R-1 Last phase iterations NOR First phase R-1 Last phase iterations
As shown in timing diagrams 285-4 and 285-5, at time1, equilibration is disabled (e.g., the equilibration signal 226 is deactivated) such that sense lines D and D— are floating. At time t2, either the InvD signal 213 or the Passd and Passdb signals 211 are activated, depending on which logical operation is being performed. In this example, the InvD signal 213 is activated for a NAND or NOR operation (see FIG. 2D-1), and the Passd and Passdb signals 211 are activated for an AND or OR operation (see FIG. 2D-2).
The sense amp 306 also includes circuitry configured to equilibrate the sense lines D and D_. In this example, the equilibration circuitry comprises a transistor 324 having a first source/drain region coupled to an equilibration voltage 325 (dvc2), which can be equal to VDD/2, where VDD is a supply voltage associated with the array. A second source/drain region of transistor 324 is coupled to a common first source/drain region of a pair of transistors 323-1 and 323-2. The second source drain regions of transistors 323-1 and 323-2 are coupled to sense lines D and D_, respectively. The gates of transistors 324, 323-1, and 323-2 are coupled to control signal 326 (EQ). As such, activating EQ enables the transistors 324, 323-1, and 323-2, which effectively shorts sense line D to sense line D— such that the sense lines D and D— are equilibrated to equilibration voltage dvc2.
The sense amp 306 also includes transistors 332-1 and 332-2 whose gates are coupled to a signal 333 (COLDEC). Signal 333 may be referred to as a column decode signal or a column select signal. The sense lines D and D— are connected to respective local I/O lines 334-1 (IO) and 334-2 (IO_) responsive to enabling signal 333 (e.g., to perform an operation such as a sense line access in association with a read operation). As such, signal 333 can be activated to transfer a signal corresponding to the state (e.g., a logic data value such as logic 0 or logic 1) of the memory cell being accessed out of the array on the I/O lines 334-1 and 334-2.
In operation, when a memory cell is being sensed (e.g., read), the voltage on one of the sense lines D, D— will be slightly greater than the voltage on the other one of sense lines D, D_. The PSA signal is then driven high and the RNL— signal is driven low to activate the sense amplifier 306. The sense line D, D— having the lower voltage will turn on one of the PMOS transistor 329-1, 329-2 to a greater extent than the other of PMOS transistor 329-1, 329-2, thereby driving high the sense line D, D— having the higher voltage to a greater extent than the other sense line D, D— is driven high. Similarly, the sense line D, D— having the higher voltage will turn on one of the NMOS transistor 327-1, 327-2 to a greater extent than the other of the NMOS transistor 327-1, 327-2, thereby driving low the sense line D, D— having the lower voltage to a greater extent than the other sense line D, D— is driven low. As a result, after a short delay, the sense line D, D— having the slightly greater voltage is driven to the voltage of the PSA signal (which can be the supply voltage VDD), and the other sense line D, D— is driven to the voltage of the RNL— signal (which can be a reference potential such as a ground potential). Therefore, the cross coupled NMOS transistors 327-1, 327-2 and PMOS transistors 329-1, 329-2 serve as a sense amp pair, which amplify the differential voltage on the sense lines D and D— and serve to latch a data value sensed from the selected memory cell. As used herein, the cross coupled latch of sense amp 306 may be referred to as a primary latch. In contrast, and as described above in connection with FIG. 2A, a cross coupled latch associated with a compute component (e.g., compute component 231 shown in FIG. 2A) may be referred to as a secondary latch.
sensing circuitry comprising:
a first latch coupled to a sense line of the array; and
a second latch coupled to the first latch; and
a controller configured to control accumulating, in the second latch, a result of a first operation phase of a logical operation and a number of intermediate operation phases of the logical operation;
wherein the first operation phase comprises sensing a memory cell coupled to the sense line;
wherein the number of intermediate operation phases comprise sensing a respective number of different memory cells coupled to the sense line; and
wherein an accumulated result in the second latch is a result of the logical operation.
2. The apparatus of claim 1, wherein the logical operation is at least one of:
an AND operation;
an OR operation;
3. The apparatus of claim 1, wherein the second latch is configured to remain activated during the number of intermediate operation phases.
4. The apparatus of claim 1, wherein the controller is further configured to control the sensing circuitry to store the result of the logical operation in the array without activating an input/output line of the array.
5. The apparatus of claim 1, wherein the second latch comprises a first pair of transistors and a second pair of transistors formed on pitch with the memory cells.
6. The apparatus of claim 1, wherein the memory cell and the respective number of different memory cells are each coupled to different access lines of the array.
a controller configured to control sensing circuitry coupled to the array to:
determine a data value serving as a first input of a logical operation via a sense amplifier coupled to a sense line of the array;
provide the determined data value to a latch of a compute component coupled to the sense amplifier, wherein the compute component comprises transistors formed on pitch with the memory cells of the array;
sense, via the sense amplifier, a number of data values stored in a number of memory cells coupled to the sense line, the number of data values serving as a respective number of additional inputs of the logical operation; and
determine a result of the logical operation using the compute component, wherein the result of the logical operation is stored in the latch of the compute component.
8. The apparatus of claim 7, wherein the sensing circuitry is further configured to store the result of the logical operation in the array without performing a sense line address access.
9. The apparatus of claim 7, further comprising maintaining the latch of the compute component in an activated state during sensing of the number of data values stored in the number of memory cells coupled the sense line.
10. The apparatus of claim 7, wherein the controller is further configured to control the sensing circuitry to store the result of the logical operation in the array without transferring data via an I/O line.
11. The apparatus of claim 7, wherein the latch of the compute component comprises:
a first and a second pair of cross coupled transistors;
a pair of pass transistors; and
a pair of invert transistors.
12. The apparatus of claim 11, wherein the first pair of cross coupled transistors are n-channel transistors and the second pair of cross coupled transistors are p-channel transistors.
13. The apparatus of claim 12, wherein the compute component is configured to perform an accumulate function on the number of data values by enabling only one transistor of the pair of pass transistors.
performing a first operation phase that includes:
activating a first access line of an array of memory cells coupled to sensing circuitry, the sensing circuitry comprising:
a first latch coupled to a sense line; and
a compute component comprising a second latch;
transferring, to the first latch from a memory cell coupled to the first access line and to the sense line, a data value corresponding to a first input of the logical operation; and
transferring, to the second latch, the data value corresponding to the first input;
performing a second operation phase that includes:
activating a second access line of the array;
transferring, to the first latch from a memory cell coupled to the second access line and to the sense line, a data value corresponding to a second input of the logical operation;
wherein the second latch remains activated during the second operation phase; and
transferring a result of the logical operation from the second latch to at least one of:
the array; and
15. The method of claim 14, wherein performing the first operation phase further comprises:
enabling a pair of pass transistors coupled to the first latch and to the second latch;
activating the second latch while the pair of transistors remain enabled such that the data value corresponding to the first input is transferred to the second latch; and
deactivating the first access line and the sense amplifier and disabling the pair of pass transistors.
16. The method of claim 15, wherein performing the second operation phase further comprises:
enabling, based on a particular logical operation being performed, only one of the pair of pass transistors, wherein the second latch remains activated during the second operation phase; and
deactivating the second access line and the first latch and disabling the one of the pair of pass transistors.
17. The method of claim 14, wherein the second operation phase is one of a number of intermediate operation phases each associated with sensing a memory cell coupled to a different access line in order to determine a data value of a memory cell corresponding to another input of the logical operation.
18. The method of claim 14, wherein the logical operation is at least one of:
19. The method of claim 14, wherein the compute component comprises a pair of n-channel transistors, a pair of p-channel transistors, a pair of pass transistors, and a pair of inverting transistors.
wherein the memory cell and the respective number of different memory cells are each coupled to different access lines of the array.
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