Source: https://patents.google.com/patent/KR100949636B1/en
Timestamp: 2020-02-19 12:12:37
Document Index: 233014736

Matched Legal Cases: ['art 1', 'art 2', 'art 3', 'art 3', 'art 3', 'art 4', 'art 4']

KR100949636B1 - Electro-optical device, driving circuit of electro-optical device, and electronic apparatus - Google Patents
Electro-optical device, driving circuit of electro-optical device, and electronic apparatus Download PDF
KR100949636B1
KR100949636B1 KR1020080046508A KR20080046508A KR100949636B1 KR 100949636 B1 KR100949636 B1 KR 100949636B1 KR 1020080046508 A KR1020080046508 A KR 1020080046508A KR 20080046508 A KR20080046508 A KR 20080046508A KR 100949636 B1 KR100949636 B1 KR 100949636B1
KR1020080046508A
KR20080102980A (en
고지 시미즈
2007-05-21 Priority to JP2007133792A priority Critical patent/JP4670834B2/en
2007-05-21 Priority to JP2007134034A priority patent/JP4428401B2/en
2007-05-21 Priority to JPJP-P-2007-00134034 priority
2007-05-21 Priority to JPJP-P-2007-00133792 priority
2008-05-20 Application filed by 엡슨 이미징 디바이스 가부시키가이샤 filed Critical 엡슨 이미징 디바이스 가부시키가이샤
2008-11-26 Publication of KR20080102980A publication Critical patent/KR20080102980A/en
2010-03-26 Publication of KR100949636B1 publication Critical patent/KR100949636B1/en
The present invention provides an electro-optical device, a drive circuit of the electro-optical device, and an electric device capable of suppressing the voltage amplitude of the data line with a relatively simple circuit configuration. To this end, TFTs 152, 154, 156, 158, and 160 are provided in the capacitor lines 132 of each row, and when the scan signal Yi is at the H level, the TFT 156 of the i-th row is turned on and the TFT is turned on. 158 is turned off, and the i-th capacitor line 132 is connected to the first feed line 165 so that the scan signal Yi is at L level and the scan signal Y (i + 1) is at H level. At this time, the i-th TFT 156 is turned off and the TFT 158 is turned on to connect the i-th capacitor line 132 to the second feed line 167. In addition, while all the scanning lines 112 are non-selected, the TFTs 160 corresponding to all the capacitor lines 132 are turned on to forcibly connect all the capacitor lines 132 to the second feed line 167. Alternatively, each capacitor line 132 is provided with a set of TFTs 152, 154, 156, and 158. The gate electrode of the TFT 152 is connected to the gate control line 167, the source electrode is connected to the on voltage feed line 161, the gate electrode of the TFT 154 is connected to the scan line 112, and the source electrode is It is connected to the off voltage feed line 162, and the common drain electrode of the TFTs 152 and 154 is connected to the gate electrode of the TFT 158. The gate electrode of the TFT 156 is connected to the scan line 112, the source electrode is connected to the first feed line 165, the source electrode of the TFT 158 is connected to the second feed line 166, and the TFT 156 is connected. 158 is connected to the capacitor line 132.
ELECTRO-OPTICAL DEVICE, DRIVING CIRCUIT OF ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS}
The present invention relates to, for example, an electro-optical device using an electro-optic material such as a liquid crystal, a drive circuit of the electro-optical device, and an electric device having the electro-optical device. Moreover, it is related with the technique which aims at the fall of display quality.
In an electro-optical device such as a liquid crystal, a pixel capacitance (liquid crystal capacitance) is provided corresponding to the intersection of the scan line and the data line. However, when the pixel capacitance needs to be AC-driven, the voltage amplitude of the data signal becomes positive polarity. In a data line driving circuit that supplies a data signal to a data line, a breakdown voltage corresponding to the voltage amplitude of the component is required. For this reason, a technique for reducing the voltage amplitude of the data signal by providing a storage capacitor in parallel with the pixel capacitor and driving the capacitance line in which the storage capacitors are commonly connected in each row in binary is synchronized with the selection of the scan line. It is proposed (refer patent document 1).
In addition, in the conventional driving method of the display device, as the off period of the pixel switching element, the voltage is reversed every one vertical scanning period to the first wiring connected to the pixel electrode until the next on period of the pixel switching element. It is known to apply a voltage to the display material by applying a modulation signal that changes in the direction to change the potential of the pixel electrode, and superimpose or cancel the change of the potential and the image signal voltage. See Patent Document 2). Accordingly, power consumption of the driving circuit can be reduced by reducing the voltage amplitude of the data line.
[Patent Document 1] See Japanese Patent Laid-Open No. 2001-83943.
[Patent Document 2] Japanese Patent No. 2568659
By the way, in this technique, since the circuit which drives a capacitor line is equivalent to the scanning line drive circuit (actually a shift register) which drives a scan line, the problem that the circuit structure for driving a capacitor line becomes complicated is pointed out. .
Moreover, in the conventional apparatus described in the said patent document 2, the specific structure of the circuit which drives a capacitance line individually is not disclosed. For example, in the case where the circuit is controlled by an externally generated signal, high definition cannot be achieved due to the limitation of the mounting density, and the extension line increases, so-called window frames outside the display area are widened. The cost is high.
In order to avoid this, there is disclosed a configuration in which a storage capacitor is formed on the gate line and the gate voltage is changed to three or more values. In this case, at least three-switch switching circuits are required for each gate line. The circuit for generating the voltage waveform is complicated.
Accordingly, an object of the present invention is to provide an electro-optical device, a drive circuit of an electro-optical device, and an electric device capable of suppressing the voltage amplitude of a data line with a relatively simple circuit configuration.
MEANS TO SOLVE THE PROBLEM In order to solve the said subject, the drive circuit of the electro-optical device which concerns on 1st invention consists of a some scanning line, a some data line, the some capacitance line provided corresponding to the said some scanning line, the said some scanning line, and said some A pixel switching element which is provided corresponding to the intersection of the data lines, wherein each of the pixel switching elements is connected to the data line, the scan line, and the pixel electrode, and the pixel electrode is brought into a conductive state when the connected scan line is selected; A drive circuit for an electro-optical device, comprising: a pixel comprising a pixel capacitor connected between a pixel electrode and a common electrode; and a storage capacitor connected between the pixel electrode and a capacitor line provided corresponding to the scan line. The scanning line driver circuits selected in a predetermined order and the capacitance lines provided corresponding to one scanning line are When one scan line is selected, a first feed line is selected, and a scan line selected after the one scan line is selected as the scan line spaced apart from the one scan line by a predetermined row, and then the second scan line is selected again. A capacitance line driver circuit for selecting a feeder line, applying a voltage of the selected feeder line, and applying a voltage of the second feeder line to all capacitor lines while all scan lines are unselected, and corresponding to the selected scan line A pixel is provided with a data line driving circuit for supplying a data signal corresponding to the gray level of the pixel via a data line.
Accordingly, the power consumption can be reduced by suppressing the voltage amplitude of the data line with a simple configuration. In addition, since the voltage of the second feeder line is forcibly applied to all the capacitor lines while all the scan lines are unselected, even when the refresh period is long, the voltage of the capacitor line can be maintained at the voltage of the second feeder line and blinks. The display quality can be improved by preventing the occurrence of display defects such as such.
In the first aspect of the present invention, in the first aspect of the present invention, the entire display mode in which the entire screen is a display region, and a partial region in the entire screen are used as the display region, and the other region is a non-display region. The partial display mode is configured to be selectable, and the capacitor line driver circuit applies the voltage of the second feed line to all capacitor lines while all the scan lines are non-selected in the partial display mode. I am doing it.
Accordingly, in the partial display mode with a long refresh period, while the scan line is unselected, the voltage of the capacitor line can be maintained at the voltage of the second feed line, thereby preventing display defects such as flickering.
In addition, in the third invention, in the first or second invention, the capacitor line driver circuit has first to fifth transistors corresponding to each of the capacitor lines, and the first capacitor corresponds to one capacitor line. The transistor is connected to a scan line in which a gate electrode is spaced apart from a scan line corresponding to the one capacitor line by a predetermined row, and is connected to an on-voltage feed line that feeds an on voltage for turning on the fourth transistor. The two transistors are connected to an off voltage feed line where a gate electrode is connected to a scan line corresponding to the one capacitor line, and a source electrode supplies an off voltage for turning off the fourth transistor, and the third transistor is connected to a gate. An electrode is connected to the scan line corresponding to the one capacitance line, a source electrode is connected to the first feed line, and the fourth transistor Is a gate electrode commonly connected to drain electrodes of the first and second transistors, a source electrode is connected to the second feed line, and the fifth transistor is an on voltage for turning on or off a gate electrode thereof. Or an on-off voltage feeder for supplying an off voltage, a source electrode connected to the second feeder, a drain electrode of the third, fourth, and fifth transistors connected to the one capacitor line; The voltage of the on-off voltage feeder is controlled to the on voltage while the scan line is unselected.
Accordingly, when the scan line corresponding to one capacitor line is selected, the third transistor is turned on, the fourth transistor is turned off, and the voltage of the first feed line can be applied to the one capacitor line. After the scanning line selected after the one scanning line is selected as the scanning line spaced apart from one scanning line by a predetermined row, the third transistor is turned off and the fourth transistor is turned on until the one scanning line is selected again. The voltage of the second feed line can be applied to the capacitance line of. Therefore, the voltage amplitude of the data line can be suppressed without complicating the circuit configuration of the capacitor line driver circuit.
In addition, while all the scan lines are unselected, the gate electrode of the fourth transistor is pulled up to the on voltage by the fifth transistor, so that the capacitor lines are in the high impedance state even in the partial display mode with a long scan period. It can prevent.
Further, in the fourth invention, in any one of the first to third inventions, the voltage of the one capacitance line is changed when the scanning line spaced apart from the scanning line corresponding to one capacitance line is selected. The voltage of the 1st and 2nd feeder line is set, It is characterized by the above-mentioned.
As a result, the data signal supplied from the data line driver circuit can be set to the voltage at which the voltage change of the pixel electrode due to the voltage change of the capacitor line is predicted, so that the voltage amplitude of the data line can be suppressed.
In a fourth aspect of the invention, in the fourth invention, the voltage of the first feeder is different from two different voltages at predetermined cycles, and the voltage of the second feeder is constant.
Accordingly, in a period in which one scan line is non-selected, the voltage of the capacitor line corresponding to the one scan line can be stabilized to the voltage of the second feeder line, which adversely affects the display quality caused by the voltage variation of the capacitor line. Can be prevented.
Further, in the sixth invention, in any one of the first to fifth inventions, the voltage signal which causes the detected voltage of the capacitor line corresponding to the one scan line to be the target voltage when the one scan line is selected. A correction circuit for supplying the first feed line is provided.
As a result, even if the on resistance of the third transistor is increased, the voltage distortion generated in the capacitor line is not generated, and the display quality can be improved by preventing the occurrence of display irregularities. In addition, since the size of the third transistor can be reduced, the so-called window frame region outside the display region can be made narrower, and the cost can be reduced.
Further, the electro-optical device of the seventh aspect of the invention is provided in correspondence with a plurality of scanning lines, a plurality of data lines, a plurality of capacitance lines provided in correspondence with the plurality of scanning lines, and the intersection of the plurality of scanning lines and the plurality of data lines. And a pixel switching element each connected to a data line, a scan line, and a pixel electrode, wherein the pixel electrode is in conduction state with the data line when the connected scan line is selected, and connected between the pixel electrode and the common electrode. A pixel including a pixel capacitor, a storage capacitor connected between the pixel electrode and a capacitor line provided corresponding to the scan line, a scan line driver circuit for selecting the scan lines in a predetermined order, and a capacitor provided corresponding to one scan line For the line, when the one scan line is selected, a first feed line is selected, and from the one scan line As the scan lines spaced apart from each other, after the scan line selected after the one scan line is selected, the second feed line is selected until the single scan line is selected, and the voltages of the selected feed lines are respectively applied, and all the scan lines are selected. During this non-selection, the capacitor line driver circuit for applying the voltage of the second feed line to all capacitor lines, and the data signal corresponding to the gray level of the pixel for the pixel corresponding to the selected scan line, It is characterized by including the data line driver circuit supplied via.
As a result, it is possible to say that it is an electro-optical device capable of reducing power consumption by reducing the voltage amplitude of the data line with a simple configuration, and improving display quality.
Moreover, the electric machine of 8th invention is provided with the electro-optical device of 7th invention.
As a result, it can be said that the electric device realizes a reduction in power consumption and an improvement in display quality.
In order to achieve the above object, the driving circuit of the electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, a capacitance line provided in each of the plurality of scanning lines, the plurality of scanning lines and the plurality of columns. Each pixel is provided in correspondence with the intersection of the data lines, each of which is connected to the data line, and when the scanning line is selected, the pixel switching element is in a conductive state between one end and the other end, and one end is the pixel switching element. Of an electro-optical device having a pixel connected to the other end of the pixel and the other end connected to a common electrode, and a storage capacitor connected between one end of the pixel capacitor and a capacitor line corresponding to the scanning line. A drive circuit comprising: a scan line driver circuit for selecting the scan lines in a predetermined order and a capacitance line provided corresponding to one scan line; For the pixel corresponding to the selected scan line and the capacitor line driver circuit which is connected to the first feed line when the one scan line is selected and continues the connection to the second feed line after the selection is completed, A data line driving circuit for supplying a data signal corresponding to the gray scale via the data line, and setting a voltage of the first feed line when the one scan line is selected to be different from that of the second feed line It features. According to the present invention, since the connection destination of the capacitance line is completed by the configuration of only connecting the first feed line when the scanning line is selected and connecting the second feed line after the selection is completed, while suppressing the potential variation of the capacitance line. The structure can be simplified.
In the present invention, the voltage of the first feeder may be switched to two different voltages at predetermined cycles, and the voltage of the second feeder may be of a constant configuration, and the voltage of the second feeder may be set at the first feeder. It is good also as an intermediate value of two voltages. At this time, it is preferable to switch the voltage of the first feed line each time the scan line of one row is selected.
In the present invention, the capacitor line driver circuit has first, second, third, and fourth transistors corresponding to each of the plurality of capacitor lines, and the first capacitor corresponds to one capacitor line. The transistor has a gate electrode connected to a gate control line, a source electrode connected to an on voltage feed line for supplying an on voltage for turning on the fourth transistor, and the second transistor has a gate electrode having the one capacitor line. Is connected to a scan line corresponding to a source electrode connected to an off voltage feed line for supplying an off voltage for turning off the fourth transistor, wherein the third transistor has a gate electrode connected to the scan line corresponding to the one capacitor line. A source electrode connected to the first feed line, and a gate electrode connected to drain electrodes of the first and second transistors. It is good also as a structure with which it connected in common, the source electrode is connected to the said 2nd feed line, and the drain electrodes of the said 3rd and 4th transistor are connected to the said one capacitance line. In such a configuration, the gate control signal allows the on-voltage of the fourth transistor to be continued by maintaining the on voltage at the gate electrode of the fourth transistor in a period other than the period in which the scan line is selected.
In this configuration, the plurality of sets of fourth transistors each having a plurality of sets of the first, second and fourth transistors for one capacitor line and connecting the one capacitor line to the second feed line. You may switch in a predetermined order among them. By switching in this way, it becomes possible to reduce the influence by the deterioration of the characteristic of a 4th transistor.
The capacitor line driver circuit further includes a fifth transistor corresponding to each of the plurality of capacitor lines, and the fifth transistor corresponding to one capacitor line has a gate electrode corresponding to the one capacitor line. The configuration may be connected to a scanning line selected next to the scanning line, a source electrode is connected to the on-voltage power supply line, and a drain electrode is connected to the drain electrodes of the first and second transistors.
In addition, the sixth transistor having an operational amplifier and a sixth transistor corresponding to each of the plurality of rows of capacitance lines, wherein the sixth transistor corresponding to one capacitance line has a gate electrode connected to a scan line corresponding to the one capacitance line. The source electrode is connected to the one capacitance line, the drain electrode is connected to the detection line, and the operational amplifier is configured to adjust the voltage of the first feed line such that the voltage of the detection line when the one scan line is selected becomes the target voltage. You may control. Accordingly, since the size of the third transistor is small, the configuration can be simplified, and the display quality is not deteriorated even if the on-resistance of the third transistor in each row is not uniform.
In addition, the present invention can be conceived not only as a driving circuit of the electro-optical device, but also as an electro-optical device or as an electronic device having the electro-optical device.
As described above, the present invention can provide an electro-optical device, a drive circuit of the electro-optical device, and an electric device capable of suppressing the voltage amplitude of the data line with a relatively simple circuit configuration.
1 is a block diagram showing the configuration of an electro-optical device 10 according to the first embodiment.
As shown in this figure, the electro-optical device 10 has a display area 100, and a control circuit 20, a scan line driver circuit 140, and a capacitor line driver circuit (around the display area 100). 150, the data line driver circuit 190 is arranged. Among these, the display area 100 is an area in which the pixels 110 are arranged. In this embodiment, 321 rows of scan lines 112 extend in the row X direction, while 240 columns of data lines 114 Each of the pixels 110 is provided so as to extend in the column Y direction, and the pixel 110 corresponds to the intersection of the scan lines 112 in the 1st to 320th rows and the data lines 114 in the 1st to 240th rows except the final 321st row. Are arranged respectively.
Therefore, in the present embodiment, the scanning line 112 on the 321nd line does not contribute to the vertical scanning of the display area 100 (the operation of selecting the scanning lines in order for voltage writing to the pixel 110).
In the present embodiment, the pixels 110 are arranged in a matrix form in the display area 100 with 320 rows x 240 columns, but the present invention is not intended to be limited to such an arrangement.
In addition, the capacitor lines 132 extend in the X direction to correspond to the scan lines 112 in the 1st to 320th lines, respectively. For this reason, in the present Example, the capacitance line 132 is provided with 1 to 320 rows except for the 321st scan line 112 as a dummy.
In addition, the electro-optical device 10 of the present embodiment has a full screen display mode in which the entire screen of the display area 100 is the display area, a partial area in the full screen as the display area, and the other area is a non-display area. The partial display mode to be set can be selected. In the partial display mode, for example, as shown in Fig. 2, an image (visual time, battery remaining amount, etc.) is displayed using only the region of the pixels in the 80th to 160th rows from the upper end in the vertical direction (y direction) as the display area. No image is displayed in the non-display area, which is the outer area. That is, in the case of normally white, the non-display area is displayed white, and in the case of normally black, black is displayed.
Next, the detailed structure of the pixel 110 is demonstrated.
FIG. 3 is a diagram showing the configuration of the pixel 110, wherein 2x2 corresponds to the intersection of the i row and the (i + 1) row adjacent thereto and the j column and the (j + 1) column adjacent thereto. The structure for 4 pixels in total is shown.
In addition, i is a symbol in the case of generally indicating the row in which the pixel 110 is arranged, and is an integer of 1 or more and 320 or less, and j, (j + 1) is a case in which the column in which the pixel 110 is arranged is generally represented. As a symbol, it is an integer of 1 or more and 240 or less. Here, for (i + 1), when the row in which the pixel 110 is arranged is generally represented, the integer is 1 or more and 320 or less. However, when describing the row of the scan line 112, the 321th row which is a dummy is represented. Since it is necessary to include, it is an integer of 1 or more and 321 or less.
As shown in FIG. 3, each pixel 110 includes an n-channel thin film transistor (hereinafter referred to as TFT) 116, which functions as a pixel switching element, a pixel capacitor (liquid crystal capacitor) 120, Has an accumulation capacity 130. Since each pixel 110 has the same configuration, it is representatively described that it is located in the i row j column. 112, the source electrode is connected to the j-th data line 114, and the drain electrode thereof is connected to the pixel electrode 118 which is one end of the pixel capacitor 120.
The other end of the pixel capacitor 120 is connected to the common electrode 108. As shown in FIG. 1, the common electrode 108 is common across all the pixels 110, and a common signal Vcom is supplied. In the present embodiment, the common signal Vcom is constant at the voltage LCcom in time as described later.
In Fig. 3, Yi and Y (i + 1) represent the scanning signals supplied to the scan lines 112 on the i and (i + 1) lines, respectively, and Ci and C (i + 1) respectively. Voltages of the capacitor lines 132 in the i and (i + 1) th rows are shown.
The display area 100 bonds a pair of substrates between an element substrate on which the pixel electrode 118 is formed and an opposing substrate on which the common electrode 108 is formed, while maintaining a constant gap so that the electrode formation surfaces face each other, The liquid crystal 105 is sealed in this gap. For this reason, the pixel capacitor 120 sandwiches the liquid crystal 105, which is a kind of dielectric, between the pixel electrode 118 and the common electrode 108, and the difference voltage between the pixel electrode 118 and the common electrode 108. It is configured to keep the. In this configuration, in the pixel capacitor 120, the amount of transmitted light varies depending on the effective value of the holding voltage.
In addition, in the present embodiment, for convenience of explanation, when the voltage effective value held in the pixel capacitor 120 is close to zero, the light transmittance is maximized to produce white display, while the amount of light transmitted decreases as the voltage effective value increases. In the end, it is assumed that the normal white mode is set to black display with the smallest transmittance.
In addition, one end of the storage capacitor 130 in the pixel 110 in the i row j column is connected to the pixel electrode 118 (drain electrode of the TFT 116), and the other end thereof is the i-th capacitor line ( 132). Here, the capacitance values in the pixel capacitor 120 and the storage capacitor 130 are referred to as Cpix and Cs, respectively.
Referring back to FIG. 1, the control circuit 20 outputs various control signals to control each unit in the electro-optical device 10, and also controls the first capacitance signal Vc1 to the first feed line 165. The second capacitance signal Vc2 is supplied to the second feed line 166, respectively. The control circuit 20 supplies the on-voltage Von, which will be described later, to the on-voltage feeder 161, and supplies the off-voltage Voff to the off-voltage feeder 163, and also supplies the common signal Vcom. The common electrode 108 is supplied. In addition, the control circuit 20 switches the on voltage Vgon and the off voltage Vgoff, which will be described later, at a predetermined timing and supplies them to the voltage control line cntg.
As described above, peripheral circuits such as the scan line driver circuit 140, the capacitor line driver circuit 150, and the data line driver circuit 190 are provided around the display area 100.
Among these, the scan line driver circuit 140 supplies the scan signals Y1, Y2, Y3, ..., Y320, Y321 to one, two, three over a period of one frame under the control of the control circuit 20. FIG. ,… It supplies to the scanning line 112 of the 320th, 321nd line. That is, the scan line driver circuit 140 may scan the scan lines by 1, 2, 3,... , 320 and 321 lines are selected, and the scan signal to the selected scan line is set to the H level corresponding to the selected voltage Vdd, and the scan signal to the other scan lines is unselected voltage (ground potential ( The level L corresponds to Gnd)).
In detail, as illustrated in FIG. 5, the scan line driver circuit 140 sequentially shifts the start pulse Dy supplied from the control circuit 20 in accordance with the clock signal Cly. The scan signals Y1, Y2, Y3, Y4, ..., Y320, Y321 are output.
In addition, in this embodiment, the period of one frame means the effective scanning period Fa until the scanning signal Y320 becomes L level after the scanning signal Y1 becomes H level, as shown in FIG. And the retrace period Fb from when the dummy scan signal Y321 becomes H level until the scan signal Y1 becomes H level again. In addition, the period in which the scanning line 112 of one row is selected is the horizontal scanning period H. FIG.
In the present embodiment, the capacitor line driver circuit 150 is constituted by a set of TFTs 152, 154, 156, 158, and 160 provided corresponding to the capacitor lines 132 of the 1st to 320th lines. Here, the TFTs 152, 154, 156, 158, and 160 corresponding to the i-th capacitor line 132 will be described. The gate electrode of the TFT 152 (first transistor) is selected after the i-th row. It is connected to the scanning line 112 of the (i + 1) th line, and the source electrode is connected to the on voltage feed line 161. FIG. The gate electrode of the i-th TFT 154 (second transistor) is connected to the i-th scan line 112, and the source electrode thereof is connected to the off voltage feed line 163, and the TFT 152 of the i-th row is connected. And the drain electrodes of 154 are connected to the gate electrode of the i-th TFT 158 (fourth transistor).
On the other hand, the gate electrode of the i-th TFT 156 (third transistor) is connected to the i-th scan line 112, and its source electrode is connected to the first feed line 165. The source electrode of the i-th TFT 158 is connected to the second feed line 166.
The gate electrode of the i-th TFT 160 (fifth transistor) is connected to a voltage control line cntg (on-off voltage feed line), and its source electrode is connected to the second feed line 166.
The drain electrodes of the TFTs 156, 158, and 160 are connected to the capacitor line 132 of the i-th row.
Here, the on voltage Von supplied to the on voltage feed line 161 is in a state where the TFT 158 is turned on (a conduction state between the source and drain electrodes) when it is applied to the gate electrode of the TFT 158. Is the voltage to be made, for example, the voltage Vdd. In addition, the off voltage Voff supplied to the off voltage supply wire 163 turns off the TFT 158 when it is applied to the gate electrode of the TFT 158 (a non-conduction state between the source and drain electrodes). Is a voltage to be zero, for example, a zero voltage (ground potential Gnd).
The voltage control line cntg is supplied with the on voltage Vgon or the off voltage Vgoff from the control circuit 20. In the present embodiment, the control circuit 20 supplies the on voltage Vgon to the voltage control line cntg during the period in which all the scan lines 112 are non-selected in the partial display mode, and the off voltage in other periods. It is configured to supply (Vgoff).
Here, the on voltage Vgon is a voltage which turns on the TFT 160 when it is applied to the gate electrode of the TFT 160, for example, the voltage Vdd. In addition, the off voltage Vgoff is a voltage which turns off the TFT 160 when it is applied to the gate electrode of the TFT 160, and is, for example, a zero voltage (ground potential Gnd).
In addition, the sizes of the TFTs 152, 154, 156, 158, and 160 may be appropriately changed, for example, the TFTs 156 ≥ TFT 158 ≥ TFTs 152, 154 and 160.
The data line driver circuit 190 is a voltage according to the gray level of the pixel 110 positioned on the scan line 112 selected by the scan line driver circuit 140, and the data signal having the polarity voltage designated by the polarity indication signal Pol is determined. (X1, X2, X3, ..., X240) to 1, 2, 3, ... To the 240th data line 114, respectively.
Here, the data line driver circuit 190 has a storage area (not shown) corresponding to a matrix arrangement of 320 rows x 240 columns, and the gray level values (brightness) of the corresponding pixels 110 are respectively provided in each memory area. The designated display data Da is stored. In the case where a change occurs in the display content, the display data Da stored in each storage area is rewritten by being supplied with the changed display data Da together with the address by the control circuit 20.
The data line driver circuit 190 reads the display data Da of the pixel 110 positioned on the selected scan line 112 from the storage area, and reads out the data signal of the polarity voltage designated as the voltage according to the gray scale value. The operation of converting and supplying the data line 114 is performed for each of 1 to 240 columns located in the selected scanning line 112.
Here, the polarity indication signal Pol is a signal for specifying positive writing if it is H level, and for specifying negative writing if it is L level. As shown in Fig. 5, in this embodiment, every period of one frame is used. Reverse polarity. In other words, in the present embodiment, the polarity to be written in the pixels in the period of one frame is made the same, and the surface inversion method in which the writing polarity is inverted for each period of one frame is used. The reason for the polarity inversion as described above is to prevent deterioration of the liquid crystal due to the application of a direct current component.
In addition, with respect to the write polarity in the present embodiment, when the voltage according to the gray level is maintained with respect to the pixel capacitor 120, the potential of the pixel electrode 118 is higher than the voltage LCcom of the common electrode 108. The case where it is called as a positive polarity is called the negative polarity. On the other hand, the voltage is based on the ground potential Gnd of the power supply unless otherwise specified.
In addition, the control circuit 20 supplies the latch pulse Lp to the data line driving circuit 190 at a timing at which the logic level of the clock signal Cly transitions. As described above, the scan line driver circuit 140 sequentially shifts the start pulse Dy in accordance with the clock signal Cly, for example, to scan signals Y1, Y2, Y3, Y4, ..., Y320, Y321. The output timing is a timing at which the logic level of the clock signal Cly transitions. Therefore, the data line driving circuit 190 determines, for example, by how many scan lines are selected by continuing counting the latch pulse Lp over a period of one frame, and by the timing of supply of the latch pulse Lp. The start timing of the selection can be known.
In addition, in the present embodiment, the element substrate is added to the scanning line 112, the data line 114, the TFT 116, the pixel electrode 118, and the storage capacitor 130 in the display region 100. TFTs 152, 154, 156, 158, 160 in the capacitor line driving circuit 150, an on voltage feed line 161, an off voltage feed line 163, a first feed line 165, a second feed line 166, and the like. Is formed.
4 is a plan view showing the configuration of the vicinity of the boundary between the capacitor line driver circuit 150 and the display region 100 among such element substrates.
As shown in this figure, in this embodiment, the TFTs 116, 152, 154, 156, 158, and 160 are amorphous silicon type, and the bottom gate type whose gate electrode is located below the semiconductor layer.
In detail, the gate electrode of the scanning line 112, the capacitance line 132, and the TFT 158 is formed by patterning the gate electrode layer serving as the first conductive layer, and a gate insulating film (not shown) is formed thereon. In addition, the semiconductor layers of the TFTs 116, 152, 154, 156, 158, and 160 are formed in an island shape. On this semiconductor layer, a rectangular pixel electrode 118 is formed by patterning an indium tin oxide (ITO) layer serving as a second conductive layer with a protective layer therebetween, and further, aluminum serving as a third conductive layer. By patterning metal layers such as the data, the data line 114 serving as the source electrode of the TFT 116, the on voltage feed line 161, the off voltage feed line 163, the first feed line 165, and the second feed line 166. The voltage control line cntg is formed, and the drain electrodes of these TFTs are formed.
Here, the gate electrodes of the TFTs 154 and 156 are portions branched in a T-shape from the scanning line 112 in the Y (downward) direction, respectively, and the gate electrodes of the TFT 152 are Y (upward) from the scanning line 112. It is the part which branched to T shape in the direction. In addition, the storage capacitor 130 is a structure in which the gate insulating film is held as a dielectric between the portion of the capacitor line 132 formed to widen in the lower layer of the pixel electrode 118 and the pixel electrode 118. .
The common drain electrode of the TFTs 152 and 154 and the gate electrode of the TFT 158 are electrically connected with a contact hole (x mark in the figure) passing through the gate insulating film. Similarly, the common drain electrode and the capacitor line 132 of the TFTs 156 and 158 are electrically connected with a contact hole interposed therebetween.
In addition, the gate electrode of the TFT 160 is electrically connected with the voltage control line cntg and the contact hole interposed therebetween, and the drain electrode thereof is electrically connected with the capacitor line 132 and the contact hole interposed therebetween. It is planned.
In addition, since the common electrode 108 facing the pixel electrode 118 is formed on the opposing substrate, it does not appear in FIG. 4 which shows a plan view of the element substrate.
In FIG. 4, it is an example to the last, and about TFT type | mold, another structure, for example, arrangement | positioning of a gate electrode may be made into a top gate type, and it may be set as a polysilicon type by a process. In addition, it is good also as a structure which mounts an IC chip in the element board | substrate side, instead of making the element of the capacitor line drive circuit 150 into the display area 100. FIG.
When the IC chip is mounted on the element substrate side, the scan line driver circuit 140 and the capacitor line driver circuit 150 may be collected together with the data line driver circuit 190 as a semiconductor chip, or may be separate chips, respectively. In addition, the control circuit 20 may be connected via an FPC (flexible printed circuit) substrate or the like, or may be configured to be mounted on an element substrate as a semiconductor chip.
In the case where the present embodiment is not a transmissive type but a reflective type, the reflective conductive layer may be patterned with respect to the pixel electrode 118, or may have a separate reflective metal layer. In addition, it is good also as what is called a transflective semireflective type which combined both a transmissive type and a reflective type.
Next, the operation of the electro-optical device 10 according to the present embodiment will be described.
5 is a time chart for explaining the operation in the full screen display mode of the first embodiment.
As described above, in this embodiment, the surface inversion method is used. For this reason, the control circuit 20 writes to the polarity indicating signal Pol at the H level in the period of the predetermined frame (denoted as "n frame") as shown in FIG. Is specified, and the negative polarity write is designated at the L level in the next (n + 1) frame period, and the write polarity is reversed in the same manner every one frame period.
In addition, the control circuit 20 sets the first capacitance signal Vc1 and the second capacitance signal Vc2 as the coincidence voltage Vsl in n frames, while the first capacitor signal in the (n + 1) frames. The capacitance signal Vc1 is taken as the voltage Vsh which is raised relatively by the voltage ΔV from the second capacitance signal Vc2 (voltage Vsl).
In the full screen display mode, the control circuit 20 always sets the control signal supplied to the voltage control line cntg to L level, and applies the off voltage Vgoff Gnd to the gate electrode of the TFT 160. Supply.
First, the operation in n frames will be described. In this n frame, the scanning signal Y1 is first set to the H level by the scanning line driver circuit 140.
When the latch pulse Lp is output at the timing when the scan signal Y1 is at the H level, the data line driving circuit 190 has the first, second, third, and the like. The display data Da of the 240th pixel is read, and the data signals X1, X2, X3,... Of the voltage which are high on the basis of the voltage LCcom by the voltage designated by the display data Da are obtained. , X240), and 1, 2, 3,... To the data line 114 of 240 columns.
Accordingly, for example, in the j-th data line 114, the positive voltage which is higher than the voltage LCcom by the voltage specified by the display data Da of the pixel 110 in the first row j-column is the data signal ( Xj). For this reason, the voltage of positive polarity according to gradation is written in the pixel capacity 120 of 1 row 1 column-1 row 240 columns, respectively.
On the other hand, when the scan signal Y1 is at the H level, the capacitor line driver circuit 150 turns on the TFTs 154 and 156 corresponding to the first capacitor line 132. At this time, since the scanning signal Y2 is at the L level, the TFT 152 is in an off state. In addition, since the control signal supplied to the voltage control line cntg is L level, the TFT 160 is also in an OFF state.
Accordingly, an off voltage Voff is applied to the gate electrode of the TFT 158 so that the TFT 158 is turned off. As a result, the first capacitance line 132 is connected to the first feed line 165 and becomes the voltage Vsl. For this reason, the difference voltage between the positive voltage and the voltage Vsl according to the gray scale is written in the storage capacitors 130 of 1 row 1 column 1 row 240 columns, respectively.
Next, the scan signal Y1 becomes L level and the scan signal Y2 becomes H level. When the scan signal Y1 becomes L level, the TFT 116 in the pixels of one row, one column to one row, 240 columns is turned off. In the capacitor line driver circuit 150, the TFTs 154 and 156 corresponding to the capacitor line 132 of the first row are turned off, and the TFT 152 of the first row is turned on. In addition, since the control signal supplied to the voltage control line cntg maintains the L level, the TFT 160 maintains the off state.
Accordingly, the on voltage Von is applied to the gate electrode of the first row TFT 158 so that the TFT 158 is turned on. As a result, the first capacitance line 132 is connected to the second feed line 166. However, in the n-frame specifying positive writing, the second feed line 166 is the first feed line 165. FIG. Since the voltage is the same as (Vsl), the potential does not change.
The operation in which the capacitor line 132 of the first row maintains the voltage Vsl continues while the scan signal Y1 is at L level, that is, until the scan signal Y1 is at H level again.
Then, if the polarity write signal Pol is instructed to be H level and the positive polarity write is instructed, even if the scan signal Y2 becomes H level, the pixel capacitor 120 and the storage capacitor 130 of one row to one column to 240 columns are stored. No change occurs with the voltages held at
As described above, since the capacitor line 132 of the first row is maintained at the voltage Vsl, the voltage held in the pixel capacitor 120 and the storage capacitor 130 in the first row to the first row to 240 columns is again scanned. The change does not occur until (Y1) becomes H level. As a result, the pixel capacitors 120 in one row, one column, and one row and 240 columns are respectively the voltage of the data signal applied to the pixel electrode 181 and the voltage of the common electrode 108 when the scan signal Y1 becomes H level. The difference voltage with (LCcom), that is, the voltage according to the gray level is continuously maintained.
On the other hand, when the latch pulse Lp is output at the timing when the scan signal Y2 becomes the H level, the data line driving circuit 190 is the first, second, third,... The data signals X1, X2, X3, ... of the positive voltage according to the gray level of the 240th pixel. , X240, 1, 2, 3,... To the data line 114 of 240 columns. As a result, the positive voltages corresponding to the gray levels are written in the pixel capacitors 120 in the 2 rows 1 column to 2 240 columns.
If the scan signal Y2 is at the H level, the capacitor line driver circuit 150 turns on the TFTs 154 and 156 corresponding to the second capacitor line 132, and turns off the TFT 158. For this reason, since the capacitance line 132 of the 2nd row is connected to the 1st feed line 165, and becomes voltage Vsl, in the storage capacitor 130 of 2 rows 1 column-2 rows 240 columns, The difference voltage between the positive voltage and the voltage Vsl according to the gray level is written, respectively.
In the period of n frames where the polarity indication signal Pol becomes H level, the same operation is repeated until the scanning signal Y321 becomes H level. Accordingly, in all the pixel capacitors 120, the voltage of the data signal applied to the pixel electrode 118, that is, the difference voltage between the positive polarity voltage according to the gray level and the voltage LCcom of the common electrode 108 is maintained. In addition, all the storage capacitors 130 maintain the difference voltage between the positive voltage and the voltage Vsl according to the gray scale.
Next, the operation of the (n + 1) frame in which the polarity indication signal Pol becomes L level will be described.
In this (n + 1) frame, the control circuit 20 sets the first capacitance signal Vc1 to a voltage Vsh higher by ΔV than the voltage Vsl as shown in FIG. Further, when the latch pulse Lp is output at the timing when the scan signal Yi is at the H level, the data line driving circuit 190 is the i-th line, which is 1, 2, 3,... The data signals X1, X2, X3, ..., X240 corresponding to the display data Da of the 240th pixel and corresponding to the negative polarity are output.
Therefore, the voltage change of the pixel capacitor 120 in the i row and j columns in the (n + 1) frame is as follows.
First, when the scan signal Yi becomes H level, the TFT 116 in the i row and j columns is turned on, so that the data signal Xj is stored at one end of the pixel capacitor 120 (pixel electrode 118) and the storage capacitor. It is applied to one end of 130, respectively. On the other hand, when the scan signal Yi is at the H level, the TFTs 154 and 156 corresponding to the i-th capacitor line 132 are turned on in the capacitor line driver circuit 150, and the TFT 158 is turned off. The voltage Ci of the capacitor line 132 of the i-th line becomes the voltage Vsh of the first feed line 165. In addition, the common electrode 108 is constant at the voltage LCcom.
Therefore, if the voltage of the data signal Xj at this time is Vj, the voltage Vj-LCcom is charged in the pixel capacitor 120 in the i row j column, and the voltage Vj-Vsh is stored in the storage capacitor 130. Is charged.
Next, when the scan signal Yi becomes L level, the TFT 116 in the i row j columns is turned off. When the scan signal Yi becomes L level, the next scan signal Y (i + 1) becomes H level, so that the capacitor line driver circuit 150 corresponds to the i-th capacitor line 132. Since the TFTs 154 and 156 are turned off and the TFTs 152 are turned on by turning on the TFT 152, the voltage Ci of the capacitor line 132 of the i-th line is changed to that of the second feed line 166. It becomes the voltage Vsl and falls by voltage (DELTA) V compared with the case where scan signal Yi was H level. In contrast, the common electrode 108 is constant at the voltage LCcom. Therefore, the charge accumulated in the pixel capacitor 120 moves to the storage capacitor 130, so that the voltage of the pixel electrode 118 decreases.
Specifically, the voltage of the pixel electrode 118 is lowered by {Cs / (Cs + Cpix)} · ΔV (= ΔVpix) from the voltage Vj of the data signal when the scan signal Yi is at the H level. do. However, the parasitic capacitance of each part is ignored here.
Here, the data signal Xj when the scan signal Yi is at the H level is set to the voltage Vj predicted that the pixel electrode 118 is lowered by the voltage ΔVpix. That is, the voltage of the pixel electrode 118 after being lowered is lower than the voltage LCcom of the common electrode 108 so that the difference voltage between them becomes a value corresponding to the gray level of the i row and j columns.
6 is a diagram illustrating a relationship between a data signal and a holding voltage.
In this embodiment, as shown in Fig. 6, in an n frame for positive writing, the data signal ranges from a voltage Vw (+) corresponding to white w to a voltage Vb (+) corresponding to black b. For example, when the gray level becomes lower (darker) and becomes a voltage higher than the voltage LCcom, the voltage Vb (+) is used when the pixel is white w in the (n + 1) frame that becomes negative writing. When the pixel is black b, the voltage is set to be the voltage Vw (+), and the setting is the same as that of the positive voltage range and the gradation relationship is reversed.
In addition, after writing the voltage of the data signal in the (n + 1) frame, when the pixel electrode 118 drops by the voltage ΔVpix, the voltage of the pixel electrode 118 is a voltage Vw corresponding to negative white. The decrease of the voltage ΔV of the capacitor line 132 (Vsh-Vsl) in the range from (-) to the voltage Vw (-) corresponding to black so as to be symmetrical with the positive voltage on the basis of the voltage LCcom. Set.
As a result, in the (n + 1) frame in which the negative writing is designated, the voltage of the pixel electrode 118 when the voltage ΔVpix is lowered is the negative voltage corresponding to the gray scale, that is, the voltage corresponding to the white w. It is a range from Vw (−) to the voltage Vb (−) corresponding to black b, and shifts to a voltage lower than the voltage LCcom as the gray level becomes low (dark).
As described above, in the present embodiment, the voltage range a of the data line in the (n + 1) frame specifying the negative writing is the same as the n frame specifying the positive writing, but the pixel electrode 118 after shifting. Becomes the negative voltage according to the gray scale. As a result, according to the present embodiment, not only the breakdown voltage of the elements constituting the data line driver circuit 190 is narrowed, but also the voltage amplitude of the parasitic data line 114 is narrow, which leads to the parasitic capacitance. This eliminates unnecessary power consumption.
That is, in the configuration in which the common electrode 108 is maintained at the voltage LCcom and the voltage of the capacitor line 132 is constant over each frame, when the pixel capacitor 120 is driven in alternating current, the pixel electrode ( 118) writes a voltage in the range from the positive voltage Vw (+) to the voltage Vb (+) in accordance with the gray scale in the predetermined frame, if there is no change in the gray scale, the voltage corresponding to the negative polarity in the next frame. As a range from Vw (−) to voltage Vb (−), the voltage inverted based on the voltage LCcom should be written. That is, the voltage of the data signal spans the range b in FIG. Therefore, not only the breakdown voltage of the elements constituting the data line driver circuit 190 needs to correspond to the range b, but also the parasitic capacitance when the voltage changes in the range b in the parasitic data line 114. This leads to an unreasonable occurrence of unnecessary power consumption. In contrast, in the present embodiment, the voltage of the data line is changed in the range a, and is approximately reduced by half as compared with the range b, so that the above described irrationality is eliminated.
Next, the operation in the partial display mode will be described.
7 is a time chart for explaining the operation in the partial display mode of the first embodiment.
In this partial display mode, the control circuit 20 outputs the on voltage Vgon by setting the control signal supplied to the voltage control line cntg to H level while all the scanning lines 112 are non-selected. In other periods, the control signal supplied to the voltage control line cntg is set at the L level to output the off voltage Vgoff.
First, the operation in n frames will be described. In the n frame for designating the positive polarity write, the scan signals Y1, Y2, ..., Y321 are sequentially H level by the scanning line driver circuit 140, which is the same as the n frame in the full screen display mode described above. Performs the operation of.
However, since the 1st to 79th lines and the 161th to 320th lines are non-display areas, voltages corresponding to white are written into the pixel capacitors 120 of the 1st to 79th lines and the 161th to 320th lines, respectively, and the 80th to 80th display areas. Voltages corresponding to gray scales are written in the pixel capacitors 120 in the 160th row, respectively.
By the way, in the full-screen display mode, one frame period is 1/60 second, for example, and data of each pixel is rewritten at 60 Hz. On the other hand, in the partial display mode, the display area is rewritten at about 15 to 30 Hz and the non-display area at about 5 to 10 Hz.
Therefore, in the next (n + 1) frame of n frames, the image data is not rewritten, and the scanning signals Y1 to Y321 become L level in one frame period from the time t1 to t2.
Thus, while all the scanning lines 112 are non-selected, the control signal supplied to the voltage control line cntg becomes H level, and the capacitor line driver circuit 150 corresponds to all the capacitor lines 132. TFT 160 is turned on. At this time, since the scan signals Y1 to Y321 are at the L level, the TFTs 152, 154, and 156 corresponding to each row are in an off state. As a result, the capacitor lines 132 of the 1st to 320th lines are connected to the second feeder line 166 to become the voltage Vsl.
The operation in which the TFT 160 is turned on and the capacitor lines 132 of the 1st to 320th lines maintain the voltage Vsl is performed while the scan signals Y1 to Y321 are all at L level, that is, the display area or non-display again. It continues until rewriting of the image data of an area | region is performed.
Then, it is assumed that the image data of the display area is rewritten in the (n + m) frame specifying the negative writing.
In this (n + m) frame, since rewriting of the image data of the non-display area is not performed, the scanning period of the scanning lines 112 of the first to 79th lines from the time t3 to the time t4 is the scan signal (Y1 ... Y79) becomes L level. Therefore, the control signal supplied to the voltage control line cntg becomes H level, and in the capacitor line driver circuit 150, the TFTs 160 corresponding to all the capacitor lines 132 continue to be in the on state. As a result, the capacitor lines 132 in the 1st to 320th lines are connected to the second feed line 166 to maintain the voltage Vsl.
Next, in the one horizontal scanning period from time t4 to time t5, when the scan signal Y80 of the scan line 112 on the 80th line which is the display area becomes H level, the control signal supplied to the voltage control line cntg becomes L. Is at the level, and the TFT 160 corresponding to all the capacitor lines 132 is turned off. On the other hand, when the scan signal Y80 is at the H level, the capacitor line driver circuit 150 turns on the TFTs 154 and 156 corresponding to the 80th capacitor line 132, and turns off the TFT 158. For this reason, the 80th row capacitance line 132 is connected to the first feed line 165 and becomes the voltage Vsh. The difference voltage between the negative voltage and the voltage Vsh is written.
After that, the scanning signals Y81, Y82, ..., Y160 become H level in order, and the control signal supplied to the voltage control line cntg maintains the L level until time t6. The operation of is repeated until time t6. As a result, the difference voltage between the negative voltage and the voltage Vsh according to the gray level is written in each of the storage capacitors 130 in the 81st to 160th rows.
In the scanning period of the scanning lines 112 of the 161st to 321rd lines from the time t6 to the time t7, the scanning signals Y161 to Y321 become L level. Therefore, the control signal supplied to the voltage control line cntg becomes H level, and in the capacitor line driver circuit 150, the TFTs 160 corresponding to all the capacitor lines 132 continue to be in the on state. As a result, the capacitor lines 132 of the 1st to 320th lines are connected to the second feeder line 166 to become the voltage Vsl.
In this embodiment, even after the scan signal Y (i + 1) is changed to the L level, the gate electrode of the TFT 158 corresponding to the i-th capacitor line 132 is turned on by the parasitic capacitance ( It is held at Von, and as a result of the TFT 158 being turned on, the capacitor line 132 of the i-th line is held at the voltage Vsl of the second capacitor signal Vc2.
In the present embodiment, the write sustain period (refresh period) of the full screen display mode is relatively short 1/60 second, while the refresh period of the partial display mode is 1/15 to 1/30 second in the display area and 1 in the non-display area. / 5 ~ 1/10 second is relatively long. In this manner, when the refresh period is long, the TFT 158 cannot maintain the on voltage due to the charge leakage of the parasitic capacitance of the gate electrode, and the capacitor line 132 is in a high impedance state. At this time, if the scanning line potential changes, there is a possibility that display defects such as thermal flicker may occur. In addition, there is a fear that burn-in or the like may occur due to the potential change of the capacitance line due to the leak current.
On the other hand, in this embodiment, while all the scanning lines 112 are non-selected, the capacitor line 132 is forcibly connected to the second feed line 166 so that the voltage of the capacitor line 132 is converted into the second capacitance signal ( Since the voltage Vsl of Vc2) is set, it is possible to reliably prevent the capacitance line 132 from being in a high impedance state, thereby preventing adverse effects on display quality.
As described above, in the first embodiment, in the capacitor line driver circuit, the first feed line is selected when the one scan line is selected for the capacitor line provided corresponding to one scan line, and the one scan line is unselected. After the second feed line is selected and the voltage of the selected feed line is applied again until the one scan line is selected, the voltage amplitude of the data line can be suppressed, and the consumption generated by the parasitic capacitance along the data line can be reduced. In addition to reducing power, display quality can be improved.
In addition, since the voltage of the second feeder line is forcibly applied to all the capacitor lines while all the scan lines are unselected, the voltage of the capacitor line can be maintained at the voltage of the second feeder line even in the partial display mode with a long refresh period. . In this way, the capacitance line can be prevented from being in the high impedance state by the simple circuit configuration, and the occurrence of display defects such as flickering can be prevented.
When the scan line corresponding to one capacitor line is selected, the third transistor can be turned on, the fourth transistor can be turned off, and the voltage of the first feed line can be applied to the one capacitor line. The third transistor is turned off and the fourth transistor is turned on until the scan line selected after the one scan line is selected as the scan line spaced apart from the scan line of the predetermined line until the one scan line is selected again. The voltage of the second feed line may be applied to the capacitor line. In this way, four TFTs are sufficient to drive the capacitor lines for one row, and no separate control signal or control voltage is necessary. For this reason, the voltage amplitude of a data line can be suppressed, without complicating the circuit structure of a capacitor line driver circuit.
In addition, since the potential of the capacitor line can be controlled by the binary gate voltage, it is possible to avoid an increase in the mounting density and the complexity of the circuit configuration for generating the gate voltage waveform.
In addition, while all the scan lines are unselected, the gate electrode of the fourth transistor is pulled up by the fifth transistor to the on voltage, so that the voltage of the capacitor line is set to the voltage of the second feed line even in the partial display mode with a long scan period. I can keep it. In this manner, display defects such as flickering can be prevented with a simple circuit configuration.
Further, when the scan line spaced apart from the scan line corresponding to one capacitor line by a predetermined row is selected, the voltages of the first and second feed lines are set so that the voltage of the one capacitor line is changed, so that it is supplied from the data line driver circuit. The data signal can be set to a voltage in anticipation of the voltage change of the pixel electrode caused by the voltage conversion of the capacitor line, so that the voltage amplitude of the data line can be suppressed.
In addition, since the above two voltages are switched at predetermined cycles and the voltage of the second feed line is made constant, the voltage amplitude of the data line can be suppressed, and one scan line is unselected. In this period, it is possible to stabilize the voltage of the capacitor line corresponding to the one scanning line to the voltage of the second feeder line, thereby preventing adverse effects on display quality caused by the voltage variation of the capacitor line.
Next, Example 2 in the present invention will be described.
In the second embodiment, in the above-described first embodiment, when the scan line 112 in the i row is selected, the voltage at which the detection voltage of the capacitor line 132 corresponding to the i-th scan line 112 becomes the target voltage. The correction circuit for supplying a signal to the first feed line 168 is added.
8 is a block diagram showing the configuration of the electro-optical device 10 in the second embodiment.
As shown in this FIG. 8, the electro-optical device 10 in Example 2 adds the 1st capacitive signal output circuit 170 and TFT 171 to the electro-optical device 10 shown in FIG. Except for that, since it has the same structure as FIG. 1, it demonstrates centering around a part from which a structure differs.
The TFT 171 is provided corresponding to the capacitance line 132 of the 1st to 320th lines. Referring to the TFT 171 corresponding to the i-th capacitor line 132, the gate electrode of the TFT 171 is connected to the i-th scan line 112, and the source electrode is connected to the potential monitoring line Sence. The drain electrode is connected to the capacitor line 132 of the i-th row.
That is, the TFT 171 is turned on in the period in which the scan signal Yi becomes H level (period in which the TFT 156 is on), and applies the potential of the capacitor line 132 to the potential monitoring line Sence. .
The control circuit 20 outputs various control signals to control the units of the electro-optical device 10 and the like, and supplies the first target signal Vc1ref to the first capacitance signal output circuit 170.
9 is a diagram illustrating a configuration of the first capacitor signal output circuit 170.
As shown in FIG. 9, the first capacitor signal output circuit 170 includes an operational amplifier 172 and a resistor 173. The output terminal of the operational amplifier 172 is connected to the on voltage power supply line 161, and the voltage monitoring line Sence is connected to the inverting input terminal (−) of the operational amplifier 172. In addition, the first target signal Vc1ref from the control circuit 20 is supplied to the non-inverting input terminal (+) of the operational amplifier 172. A resistor 173 is inserted between the output terminal of the operational amplifier 172 and the inverting input terminal (-).
With such a configuration, the first capacitor signal output circuit 170 turns on the voltage feeder on which the first capacitor signal Vc1 is negatively feedback controlled so that the voltage of the capacitor line 132 becomes the first target signal Vc1ref. And outputs to 161. Also, at this time, the TFT 171 operates as a resistor.
Here, the first capacitor signal output circuit 170 and the TFT 171 constitute a correction circuit.
The control circuit 20 sets the polarity specifying signal Pol to the H level and the first target signal Vc1ref to the voltage Vsl over the period of n frames. The control circuit 20 also sets the polarity specifying signal Pol to L level and the first target signal Vc1ref to voltage Vsh over the period of (n + 1) frames.
Here, the operation (full screen display mode) in n frames will be described. In this n frame, the scan line Y1 is first set to the H level by the scan line driver circuit 140.
When the latch pulse Lp is output at the timing at which the scan signal Y1 becomes H level, the data line driving circuit 190 is the first row, and the first, second, third, and the like. The display data Da of the 240th pixel is read, and the data signals X1, X2, X3,..., Of the voltage that are high on the basis of the voltage LCcom by the voltage specified by the display data Da are obtained. , X240), and 1, 2, 3,... To the data line 114 of 240 columns. As a result, positive voltages corresponding to the gray levels are written in the pixel capacitors 120 of one row, one column, and one row and 240 columns, respectively.
On the other hand, when the scan signal Y1 is at the H level, the capacitor line driver circuit 150 turns on the TFTs 154 and 156 corresponding to the first capacitor line 132. As a result, the first capacitance line 132 is connected to the first feed line 165. In the n-frame, the first power supply line 165 is supplied with the first capacitance signal Vc1 controlled by the first capacitance signal output circuit 170 to become the voltage Vsl of the first target signal Vc1ref. Therefore, the voltage of the capacitor line 132 of the first row becomes the voltage Vsl. For this reason, the difference voltage between the positive voltage and the voltage Vsl according to the gradation is written in the storage capacitors 130 of 1 row 1 column 1 row 240 columns, respectively.
Next, the scan signal Y1 becomes L level and the scan signal Y2 becomes H level.
When the latch pulse Lp is output at the timing at which the scan signal Y2 is at the H level, the data line driving circuit 190 is the second row, which is 1, 2, 3,... The data signals X1, X2, X3, ..., X240 of the positive voltage corresponding to the gray level of the 240th pixel are respectively 1, 2, 3,... To the data line 114 of 240 columns. As a result, the positive voltages corresponding to the gray levels are written in the pixel capacitors 120 in the 2 rows 1 column to 2 240 columns.
On the other hand, when the scan signal Y1 becomes L level, the TFT 116 in the pixels of one row, one column to one row, 240 columns is turned off. If the scan signal Y1 is at L level, the capacitor line driver circuit 150 turns off the TFTs 154 and 156 corresponding to the first capacitor line 132, and the scan signal Y2 is at H level. For this reason, the TFT 152 corresponding to the first capacitor line 132 is turned on. As a result, the TFT 158 corresponding to the first line of capacitance line 132 is turned on, and the first line of capacitance line 132 is connected to the second feed line 166, and the first line of capacitance line is 132. The voltage at 132 maintains the voltage Vsl. For this reason, the difference voltage between the positive polarity voltage and the voltage Vsl according to the gray scale is written in the storage capacitors 130 of the 2 rows 1 column-2 rows 240 columns, respectively.
In the period of n frames where the polarity indication signal Pol becomes H level, the same operation is repeated until the scanning signal Y320 becomes H level.
In this manner, the first capacitance signal output circuit 170 is configured such that the voltage of the capacitance line 132 detected through the potential monitoring line Sence becomes the voltage of the first target signal Vc1ref. Since Vc1) is output to the on-voltage feed line 161, the voltage of the i-th capacitor line 132 in the period during which the scan signal Yi becomes H level is positively written even if there is an influence such as noise. Is designated as the voltage Vsl, and when the negative writing is designated, the voltage Vsh is maintained.
Therefore, even if the on resistance of the TFT 156 is large, voltage distortion generated in the capacitor line 132 does not occur, and display unevenness does not occur.
As described above, in the second embodiment, when the scan line of the predetermined row is selected, the voltage of the capacitor line of the row is corrected so as to be the voltage of the first target signal. Thus, even if the ON resistance of the third transistor is increased, The generated voltage distortion is not generated, and the display quality can be improved by preventing the occurrence of display irregularities. In addition, since the size of the third transistor can be reduced, the so-called window frame region outside the display region can be made narrower, and the cost can be reduced.
In the above embodiments, the case where the second capacitance signal Vc2 is made constant at the voltage Vsl has been described. However, the second capacitance signal Vc2 may be made constant at the voltage Vsh. Further, the second capacitance signal Vc2 may be made constant at a voltage between the voltage Vsl and the voltage Vsh.
Incidentally, in each of the above embodiments, the case of driving in the plane inversion method has been described, but it is also possible to drive in the line inversion method in which the write polarity is inverted for each row. In this case, the second capacitance signal Vc2 may be constant at the voltage Vsl or may be constant at the voltage Vsh. In addition, the second capacitor signal Vc2 may be made constant by the voltage LCcom.
In each of the above embodiments, in the partial display mode, the TFT 160 is turned on while all the scanning lines are unselected, so that the voltages of all the capacitor lines are the voltages of the second feed lines. Irrespective of the display mode, the period from when the scan signal Yi becomes L level until the next scan signal Y (i + 1) becomes H level, and the positive write and the negative write are switched. The TFT 160 can be turned on in a period in which all the scanning lines are non-selected, such as a blanking period for each predetermined period.
In each of the above embodiments, as the capacitor line driver circuit 150, the gate electrode of the TFT 152 corresponding to the i-th capacitor line 132 is connected to the next (i + 1) -th scan line 112. Although the case where it is connected to was demonstrated, it can also be set as the structure connected to the scanning line 112 spaced apart by a fixed number of m (m is an integer of 2 or more).
In each of the above embodiments, a case in which m dummy scanning lines 112 are required to be driven to the TFT 152 corresponding to the last 320-th capacitor line 132 will be described. However, for example, when m is "1", the blanking period Fb is eliminated, and the gate electrode of the TFT 152 corresponding to the 320th capacitor line 132 is connected to the scanning line 112 of the first row, It is also possible to have a configuration in which a dummy scanning line is unnecessary.
In addition, in each said Example, although the case where this invention was applied to the electro-optical device using liquid crystal was demonstrated, it can also be applied to the electro-optical device using electro-optic substance other than a liquid crystal. For example, a display panel using an OLED device such as an organic EL or a light emitting polymer as an electro-optic material, or an electrophoretic display panel using a microcapsule containing a colored liquid and white particles dispersed in the liquid as an electro-optic material, polarity Twist ball display panel using twisted balls which are divided and painted in different colors for each of these different regions as an electro-optic material, a toner display panel using black toner as an electro-optic material, and a high-pressure gas such as helium or neon as an electro-optic material The present invention can be applied to various electro-optical devices such as plasma display panels.
Next, Example 3 of the present invention will be described. 10 is a block diagram showing a configuration of an electro-optical device according to Embodiment 1 of the present invention.
As shown in this figure, the electro-optical device 10 has a display area 100, and the scanning line driving circuit 140, the capacitor line driving circuit 150, and the data line driving are disposed around the display area 100. The circuit 190 is arranged. Among these, the display area 100 is an area in which the pixels 110 are arranged. In the present embodiment, 320 scan lines 112 extend in the row X direction while 240 data lines 114 Each is provided so that it may extend in the row Y direction.
The pixels 110 are arranged in correspondence with the intersection of the scan lines 112 in the 1st to 320th lines and the data lines 114 in the 1st to 240th columns. Therefore, in the present embodiment, the pixels 110 are arranged in a matrix form in the display area 100 with 320 rows x 240 columns.
In addition, the capacitor lines 132 extend in the X direction to correspond to the scan lines 112 in the 1st to 320th lines, respectively. For this reason, in the capacitance line 132, it is provided from the 1st line to the 320th line.
Here, the detailed structure of the pixel 110 is demonstrated.
FIG. 11 is a diagram showing the configuration of the pixel 110, wherein 2x2 corresponds to the intersection of the i row and the (i + 1) row adjacent thereto and the j column and the (j + 1) column adjacent thereto. A configuration of four pixels in total is shown.
In addition, i is a symbol in the case of generally indicating the row in which the pixel 110 is arranged, and is an integer of 1 or more and 320 or less, and j, (j + 1) is a case in which the column in which the pixel 110 is arranged is generally represented. As a symbol, it is an integer of 1 or more and 240 or less.
As shown in FIG. 11, each pixel 110 is an n-channel thin film transistor (hereinafter simply abbreviated as "TFT") 116 functioning as a pixel switching element, and a pixel capacitance (liquid crystal capacitance). 120 and the storage capacity 130. Since each pixel 110 has the same configuration, it is representatively described that it is located in the i row j column. In the pixel 110 of the i row j column, the gate electrode of the TFT 116 is the scan line of the i row. 112, the source electrode is connected to the j-th data line 114, and the drain electrode is connected to the pixel electrode 118 which is one end of the pixel capacitor 120.
The other end of the pixel capacitor 120 is connected to the common electrode 108. This common electrode 108 is common across all the pixels 110 as shown in FIG. 10, and a common signal Vcom is supplied. In this embodiment, the common signal Vcom is constant with the voltage LCcom in time as described later.
In Fig. 11, Yi and Y (i + 1) indicate the scanning signals supplied to the scanning lines 112 on the i and (i + 1) lines, respectively, and Ci and C (i + 1) respectively indicate i. and the voltage of the capacitor line 132 in the (i + 1) th row.
The display area 100 bonds a pair of substrates between the element substrate on which the pixel electrode 118 is formed and the opposing substrate on which the common electrode 108 is formed, while maintaining a constant gap so that the electrode formation surfaces face each other. The liquid crystal 105 is sealed in this gap. For this reason, the pixel capacitor 120 holds the liquid crystal 105, which is a kind of dielectric, between the pixel electrode 118 and the common electrode 108. The difference voltage is maintained.
In the pixel capacitor 120, the amount of transmitted light varies depending on the effective value of the holding voltage. However, in the present embodiment, for convenience of explanation, when the voltage effective value held in the pixel capacitor 120 is close to zero, the light transmittance The maximum is the white display, and as the voltage effective value is increased, the amount of light transmitted decreases, and eventually the normal white mode is set to the black display with the smallest transmittance.
In addition, the storage capacitor 130 of the pixel 110 in the i row j column is connected to the pixel electrode 118 (drain electrode of the TFT 116) while one end thereof is connected to the i-th capacitor line. 132 is connected. For this reason, the storage capacitor 130 is electrically connected between the pixel electrode 118 which is one end of the pixel capacitor 120 and the capacitor line 132 of the i-th row.
In addition, the capacitance values in the pixel capacitor 120 and the storage capacitor 130 are set to Cpix and Cs, respectively.
10, the control circuit 20 outputs various control signals such as a clock signal Cly, a start pulse Dy, a latch pulse Lp, and a polarity indication signal Pol. In addition to controlling each part in the apparatus 10, the first capacitance signal Vc1 is connected to the first feed line 165, the second capacitance signal Vc2 is connected to the second feed line 166, and the gate control signal ( Cntg) is supplied to the gate control line 167, respectively.
In addition, the control circuit 20 supplies the on-voltage Von to be described later to the on-voltage power supply line 161, and supplies the off voltage Voff to the off-voltage power supply line 162, and also supplies the common signal Vcom. The common electrode 108 is supplied.
Peripheral circuits such as the scan line driver circuit 140, the capacitor line driver circuit 150, and the data line driver circuit 190 are provided around the display area 100.
Among these, the scan line driver circuit 140 supplies the scan signals Y1, Y2, Y3, ..., Y320 to 1, 2, 3, ... according to control by the control circuit 20, respectively. To the scanning line 112 on the 320th line. As illustrated in FIG. 13, the scan signals Y1 to Y320 are pulses that are at an H level at a width smaller than the half period of the clock signal Cly having a duty ratio of 50%. There is a relationship in which delays are sequentially performed from Y1 to Y320 for every half period of the clock signal Cly. For this reason, the pulses of the scanning signals of the adjacent rows are output with the period between them being at the L level.
For example, the scan line driver circuit 140 shifts the start pulse Dy supplied from the control circuit 20 to the scan signal Y1 to Y320 in accordance with the clock signal Cly, and also the pulse width. Is narrowed down and output, but the details are omitted.
Further, the H level of the scan signals Y1 to Y320 corresponds to the selection voltage Vdd, and the L level corresponds to the non-selection voltage (ground potential Gnd). Here, the scanning line is selected when the scanning signal becomes H level, and is not selected when the scanning signal is L level. In this embodiment, the period of one frame means that the period required for displaying one image is set to H level in order from the scanning signals Y1 to Y320 as shown in the drawing, and the scanning lines are sequentially scanned. It is divided into the effective scanning period Fa (selected) and the return period Fb other than that. However, this return period Fb may not be provided.
In the present embodiment, the capacitor line driver circuit 150 is composed of a set of n-channel TFTs 152, 154, 156, and 158 provided corresponding to the capacitor lines 132 of the 1st to 320th lines. Here, the TFTs 152, 154, 156, and 158 corresponding to the i-th capacitor line 132 will be described. The gate electrode of the TFT 152 (first transistor) is connected to the gate control line 167. The source electrode is connected to the on voltage feed line 161, while the gate electrode of the TFT 154 (second transistor) is connected to the i-th scan line 112, and the source electrode is connected to the off voltage feed line ( In addition to being connected to the 162, the drain electrodes of the TFTs 152 and 154 are commonly connected to the gate electrode of the TFT 158.
Further, the gate electrode of the i-th TFT 156 (third transistor) is connected to the i-th scan line 112, and the source electrode thereof is connected to the first feed line 165, while the TFT 158 is connected. The source electrode of the (fourth transistor) is connected to the second feed line 166 and the drain electrodes of the TFTs 156 and 158 are commonly connected to the i-th capacitor line 132.
Here, the on voltage Von supplied to the on voltage feed line 161 causes the TFT 158 to be in an on state (a conduction state between the source and drain electrodes) when it is applied to the gate electrode of the TFT 158. Voltage, for example, the voltage Vdd equal to the H level of the scan signal. Further, the off voltage Voff supplied to the off voltage feed line 162 causes the TFT 158 to be in an off state (non-conducting state between the source and drain electrodes) even when it is applied to the gate electrode of the TFT 158. This voltage is, for example, zero voltage (ground potential Gnd) equal to the L level of the scan signal.
The data line driver circuit 190 is a voltage according to the gray level of the pixel 110 positioned in the scan line 112 scanned by the scan line driver circuit 140 and is a voltage data signal having a polarity specified by the polarity indication signal Pol. (X1, X2, X3, ..., X240), 1, 2, 3, ... To the 240th data line 114, respectively.
Here, the data line driver circuit 190 has a storage area (not shown) corresponding to a matrix arrangement of 320 rows x 240 columns, and the gray level value (brightness) of the corresponding pixel 110 is assigned to each memory area. Display data Da to be stored is stored. The display data Da stored in each storage area has a configuration in which the changed display data Da is supplied with the address and rewritten by the control circuit 20 when a change occurs in the display contents.
The data line driving circuit 190 reads display data Da of the pixel 110 positioned on the scanning line 112 to be selected (scanned) from the storage area, and also has a voltage having a polarity designated as the voltage according to the gray scale value. The operation of converting the data signal into the data signal 114 and supplying it to the data line 114 is performed for each of 1 to 240 columns positioned on the selection scan line 112.
The polarity indication signal Pol is a signal for specifying positive writing if it is H level, and for specifying negative writing if it is L level. As shown in FIG. 13, in the present embodiment, polarity is reversed every one frame period. . For this reason, in this embodiment, all of the polarities written in the pixels in the period of one frame are the same, and the surface inversion method in which this writing polarity is inverted for each period of one frame. The reason for the polarity inversion as described above is to prevent deterioration of the liquid crystal due to the application of a direct current component.
In addition, with respect to the write polarity in the present embodiment, when the voltage according to the gray level is maintained with respect to the pixel capacitor 120, the potential of the pixel electrode 118 is higher than the voltage LCcom of the common electrode 108. The case where it is called as a positive polarity is called the negative polarity. In addition, the voltage is based on ground potential Gnd (zero voltage) of a power supply, unless there is particular notice.
In addition, the control circuit 20 supplies the latch pulse Lp to the data line driving circuit 190 at a timing at which the logic level of the clock signal Cly transitions (rises or falls). As described above, since the scan signals Y1 to Y320 have a relationship in which pulses having a width narrower than the half period of the clock signal Cly are delayed sequentially from Y1 to Y320 for every half period of the clock signal Cly, the scan signal is The logic level of the clock signal Cly becomes H level on the basis of the timing at which the logic signal transitions. In detail, as shown in FIG. 13, the scanning signal is set to the H level at a timing delayed by a predetermined time from the timing at which the logic level of the clock signal Cly transitions.
In this way, since the scan signal becomes H level on the basis of the transition timing of the clock signal Cly, the data line driving circuit 190 keeps counting the latch pulse Lp over one frame period, for example. It is possible to know the timing at which the scan signal becomes H level by how many rows the scan signal becomes H level and the output timing of the latch pulse Lp.
In addition, the control circuit 20 outputs the following gate control signal Cntg. That is, as shown in FIG. 13, the control circuit 20 receives the pulse signal gate control signal Cntg which becomes H level in the period in which all the scanning signals Y1-Y320 are L level, and the clock signal ( Every half cycle of Cly), i.e., every time the scan line is selected.
In the present embodiment, the element substrate has a capacitor in addition to the scanning line 112, the data line 114, the TFT 116, the pixel electrode 118, and the storage capacitor 130 in the display region 100. TFTs 152, 154, 156, 158 in the line driving circuit 150, on voltage feed lines 161, off voltage feed lines 162, first feed lines 165, second feed lines 166, gate control lines 167 and the like are also formed.
FIG. 12 is a plan view showing the configuration of the vicinity of the boundary between the capacitor line driver circuit 150 and the display region 100 among such element substrates.
As shown in this figure, in the present embodiment, the TFTs 116, 152, 154, 156, and 158 are amorphous silicon type and have a bottom gate type whose gate electrode is located below the semiconductor layer.
Specifically, the gate electrodes of the scan lines 112, the capacitor lines 132, and the TFTs 152 and 158 are formed by patterning the gate electrode layer serving as the first conductive layer, and a gate insulating film (not shown) is formed thereon. In addition, the semiconductor layers of the TFTs 116, 152, 154, 156, and 158 are formed in an island shape. On this semiconductor layer, a rectangular pixel electrode 118 is formed by patterning an indium tin oxide (ITO) layer serving as a second conductive layer with a protective layer (not shown) interposed therebetween, and further, a third conductive layer. By patterning a metal layer such as aluminum, which is a layer, a data line 114 serving as a source electrode of the TFT 116, an on-voltage feed line 161 serving as a source electrode of the TFT 152, and a source of the TFT 154 are formed. Common between the off voltage feed line 162 serving as an electrode, the first feed line serving as a source electrode of the TFT 156, the second feed line serving as a source electrode of the TFT 158, and the TFTs 152 and 154. A drain electrode, a common drain electrode of the TFTs 156 and 158, and a gate control line 167 are formed.
Here, the gate electrodes of the TFTs 154 and 156 branch off from the scanning line 112 in a T-shape in the Y (downward) direction, respectively.
Further, the gate electrode of the L-shaped TFT 152 is undercrossed with respect to the on-voltage feed line 161 and connected to the gate control line 167 through a contact hole (shown in the figure) passing through the gate insulating film. It is. Similarly, the gate electrode of the L-shaped TFT 158 is undercrossed with respect to the second feed line 166 and the off voltage feed line 162, respectively, and the TFTs 152 and 154 through a contact hole penetrating the gate insulating film. Is connected to the common drain electrode.
In addition, the storage capacitor 130 has a structure in which the gate insulating film is held as a dielectric between the portion of the capacitor line 132 formed to widen in the lower layer of the pixel electrode 118 and the pixel electrode 118. to be. The common drain electrode of the TFTs 156 and 158 is connected to the capacitor line 132 via a contact hole passing through the gate insulating film.
In addition, since the common electrode 108 facing the pixel electrode 118 is formed on the opposing substrate, it does not appear in FIG. 12 which shows a plan view of the element substrate.
In addition, the structure shown in FIG. 12 is an example to the last, and about TFT type | mold, another structure, for example, the arrangement | positioning of a gate electrode may be a top gate type, and a process may be polysilicon type.
In Fig. 12, when the transistor sizes of the TFTs 152, 154, 156, and 158 are represented by Tr1, Tr2, Tr3, and Tr4, respectively, they are almost the same as Tr1 = Tr2 = Tr3 = Tr4. The smaller the on-resistance of the TFT 156 is, the better, Tr3? Tr4? Tr1 = Tr2.
In addition, it is good also as a structure which mounts an IC chip in the element board | substrate side, instead of making the element of the capacitor line drive circuit 150 into the display area 100. FIG. When the IC chip is mounted on the element substrate side, the scan line driver circuit 140 and the capacitor line driver circuit 150 may be collected together with the data line driver circuit 190 as one semiconductor chip, or each chip may be used as a chip. good. The control circuit 20 may be connected via an FPC (flexible printed circuit) substrate or the like, or may be configured to be mounted on an element substrate as a semiconductor chip.
In the case where the present embodiment is not a transmissive type but a reflective type, the reflective conductive layer may be patterned with respect to the pixel electrode 118, or a separate reflective metal layer may be provided. In addition, it is good also as what is called a transflective semireflective type which combined both a transmissive type and a reflective type.
As described above, in the present embodiment, the write polarity of the pixel is set to the plane inversion method. For this reason, the control circuit 20 designates the positive polarity write as the H level in the period of the predetermined frame (denoted as "n frame") with respect to the polarity indication signal Pol as shown in FIG. Then, the negative writing is designated as the L level in the next (n + 1) frame period. That is, the control circuit 20 specifies the inversion of the write polarity every period of one frame.
The control circuit 20 makes the first capacitance signal Vc1 and the second capacitance signal Vc2 coincide with each other in n frames, while the first capacitance signal Vc1 is in the (n + 1) frame. Increases relative to the second capacitance signal Vc2 by a voltage ΔV. For this reason, as shown in Fig. 13, when the second capacitance signal Vc2 is constant at the voltage Vsl regardless of the write polarity, the first capacitance signal Vc1 is the second capacitance signal Vc2 in n frames. ) Is the same voltage Vsl, and becomes a voltage Vsh higher by ΔV than the voltage Vsl in the (n + 1) frame.
In this embodiment, the voltage Vsl is lower than the voltage LCcom, and the voltage Vsh is higher than the voltage LCcom. The quantum voltages Vsl and Vsh are symmetrical relationships around the voltage LCcom, and the absolute value of the difference is ΔV. In addition, the high and low relationship of the voltage in a present Example is Gnd <Vsl <LCcom <Vsh <Vdd.
By the way, in the n frame, when the scan signal Y1 becomes H level first by the scan line driver circuit 140, but the latch pulse Lp is output just before the scan signal Y1 becomes H level, the data line As the first row, the drive circuit 190 includes 1, 2, 3,... The display data Da of the 240th pixel is read, and the data signals X1, X2, X3,..., Of the voltage that are high on the basis of the voltage LCcom by the voltage specified by the display data Da are obtained. , X240), and 1, 2, 3,... To the data line 114 of 240 columns.
As a result, for example, in the j-th data line 114, the voltage of positive polarity which is higher than the voltage LCcom by the voltage specified by the display data Da of the pixel 110 in the first row j-column is the data signal ( Xj).
In the present embodiment, the gate control signal Cntg is at the H level at the timing when the data line driver circuit 190 applies the data signals X1 to X240 to the data lines 114 in the 1st to 240th columns. It shall be done. When the gate control signal Cntg is at the H level, in the capacitor line driver circuit 150, the TFTs 152 corresponding to all the capacitor lines 132 of the 1st to 320th lines are turned on, and the TFTs 154 and 156 are turned off. Therefore, the on voltage Von supplied to the on voltage feed line 161 is applied to the gate electrode of the TFT 158. For this reason, since all the TFTs 158 are turned on, the capacitor lines 132 of the 1st to 320th lines are connected to the second feed line 166 to become the voltage Vsl.
Next, when the scan signal Y1 becomes H level, the TFTs 116 in the pixels of one row, one column to one row, 240 columns are turned on, so that these pixel electrodes 118 are provided with data signals X1, X2, X3, ..., X240) are applied. For this reason, in the pixel capacitors 120 of one row, one column, and one row and 240 columns, the difference voltage between the voltage of the data signal applied to the pixel electrode 118 and the voltage LCcom applied to the common electrode 108 is That is, voltages of polarities according to gray levels are written respectively.
On the other hand, when the scan signal Y1 is at the H level, the gate control signal Cntg is at the L level. In the capacitor line driver circuit 150, the TFT 152 corresponding to the first capacitor line 132 is turned off. Then, the TFT 154 is turned on. For this reason, since the gate electrode of the 1st row TFT 158 is connected to the off voltage feed line 162, and the off voltage Voff is applied, the 1st row TFT 158 turns off. When the scanning signal Y1 is at the H level, the TFT 156 of the first row is turned on. For this reason, the capacitor line 132 of the 1st line is connected to the 1st feed line 165, and becomes voltage Vsl.
Therefore, the voltage difference between the voltage of the data signal applied to the pixel electrode 118 and the voltage Vsl is written in the storage capacitors 130 of one row, one column, and one row and 240 columns, respectively.
In addition, in the capacitance line 132 other than the 1st line, it will be in the following states. That is, when the scan signal Y1 is at the H level, all of the TFTs 152, 154, and 156 except the first row are turned off, but the gate electrodes of the TFTs 158 other than the first row are in the immediate state due to their parasitic capacitance. The voltage Von is maintained. For this reason, since the TFTs 158 other than the first row are kept on, the capacitor lines 132 of the second to the 130th rows other than the first row are connected to the second feed line 166 and are fixed to the voltage Vsl. It becomes
Next, although the scan signal Y1 is at the L level, the gate control signal Cntg is at the H level before the scan signal Y2 is at the H level, that is, in the period in which all the scan signals are at the L level. For this reason, in the capacitor line driver circuit 150, since the TFTs 152 corresponding to all the capacitor lines 132 of the 1st to 320th rows are turned on, the on voltage Von is applied to the gate electrode of the TFT 158 again. Is approved. For this reason, since all the TFTs 158 are turned on, the capacitor lines 132 of the 1st to 320th lines are connected to the second feed line 166 to become the voltage Vsl.
In addition, when the scanning signal Y1 becomes L level, the TFT 116 in the pixels of one row, one column to one row and 240 columns is turned off, so that the pixel electrode 118 is connected to the data line 114. Open. For this reason, the series circuit of the pixel capacitor 120 and the storage capacitor 130 in the pixel of 1 row 1 column-1 row 240 columns is electrically connected between the common electrode 108 and the capacitor line 132. It becomes
However, in the n frame, since the first capacitance signal Vc1 supplied to the first feed line 165 and the second capacitance signal Vc2 supplied to the second feed line 166 are the same voltage Vsl. , The voltage of the capacitor line 132 of each row does not change. The common electrode 108 is also constant at the voltage LCcom. For this reason, in the n frame, when the scan signal Y1 becomes H level, the voltages written in the pixel capacitors 120 and the storage capacitors 130 in one row, one column to one, and 240 columns do not fluctuate, respectively.
Subsequently, the scan signal Y2 is at the H level, but if the latch pulse Lp is output just before that, the data line driving circuit 190 is the second row, and the first, second, third, and the like. The display data Da of the 240th pixel is read out and converted into data signals X1, X2, X3, ..., X240 corresponding to the positive polarity, and 1, 2, 3, ..., respectively. To the data line 114 of 240 columns.
When the scan signal Y2 becomes H level, the TFTs 116 in the pixels of two rows, one column to two rows and 240 columns are turned on, so that these pixel electrodes 118 have data signals X1, X2, and X3. , ..., X240). For this reason, the voltage difference between the voltage of the data signal applied to the pixel electrode 118 and the applied voltage LCcom of the common electrode 108 is written in the pixel capacitor 120 of 2 rows 1 column to 2 rows 240 columns, respectively. Will be.
On the other hand, when the scan signal Y2 is at the H level, the gate control signal Cntg is at the L level. In the capacitor line driver circuit 150, the TFT 152 corresponding to the second capacitor line 132 is turned off. Then, the TFT 154 is turned on. Since the off voltage Voff is applied to the gate electrode of the second row TFT 158, the second row TFT 158 is turned off. If the scanning signal Y2 is at the H level, the second row of TFTs 156 is turned on. For this reason, the capacitance line 132 of the 2nd row is connected to the 1st feed line 165, and becomes voltage Vsl.
Therefore, the voltage difference between the voltage of the data signal applied to the pixel electrode 118 and the voltage Vsl is written in the storage capacitors 130 of the 2 rows 1 column 2 rows 240 columns, respectively.
In addition, since the scanning signal Y2 is at the H level, all the TFTs 152, 154, and 156 except the second row are turned off, but the gate electrodes of the TFTs 158 other than the second row are in the immediate state due to their parasitic capacitance. The voltage Von is maintained. For this reason, since the TFTs 158 other than the second row are kept on, the capacitor lines 132 of the first row and the third to the 130th rows other than the second row are connected to the second feed line 166 and are connected to the voltage Vsl. It becomes the confirmed state.
Next, the scan signal Y2 becomes L level, but since the gate control signal Cntg becomes H level before the scan signal Y3 becomes H level, all the TFTs 152 are turned on, and the TFT is turned on. The on voltage is reapplied to the gate electrode of 158. For this reason, since all the TFTs 158 are turned on, the capacitor lines 132 of the 1st to 320th lines are connected to the second feed line 166 to become the voltage Vsl.
When the scanning signal Y2 becomes L level, the TFT 116 in the pixels of two rows, one column to two rows and 240 columns is turned off. However, in n frames, since the voltage of the capacitor line 132 in each row does not change, and the common electrode 108 is also constant at the voltage LCcom, two rows when the scan signal Y2 becomes H level. The voltages written in the pixel capacitors 120 and the storage capacitors 130 in the first to second rows and 240 columns are not changed.
Subsequently, the scan signal Y3 is at the H level, but if the latch pulse Lp is output just before the data signal, the data line driver circuit 190 is the third row. The display data Da of the 240th pixel is read and converted into data signals X1, X2, X3, ..., X240 corresponding to the positive polarity, and 1, 2, 3, ..., respectively. To the data line 114 of 240 columns.
Here, when the scan signal Y3 becomes H level, the TFTs 116 in the pixels of three rows, one column to three rows and 240 columns are turned on, so that these pixel electrodes 118 have data signals X1, X2, X3, ..., X240 are applied, and accordingly, the voltage of the data signal applied to the pixel electrode 118 and the applied voltage of the common electrode 108 are applied to the pixel capacitor 120 of three rows, one column to three rows and 240 columns. The difference voltage with (LCcom) is written respectively.
On the other hand, when the scan signal Y3 is at the H level, the gate control signal Cntg is at the L level. In the capacitor line driver circuit 150, the TFT 152 corresponding to the third capacitor line 132 is turned off. As a result of the TFTs 154 and 156 being turned on, the third capacitor line 132 is connected to the first feed line 165 to become the voltage Vsl. Therefore, the difference voltage between the voltage of the data signal applied to the pixel electrode 118 and the voltage Vsl is written in the storage capacitors 130 of three rows, one column, three rows, and 240 columns.
When the scan signal Y3 is at the H level, all the TFTs 152, 154, and 156 except the third row are turned off, but the gate electrodes of the TFTs 158 other than the third row maintain Von by their parasitic capacitance. Since the ON of the TFTs 158 other than the third row is maintained, the capacitor lines 132 other than the third row are connected to the second feed line 166 to be in a state determined to the voltage Vsl.
In the period of n frames where the polarity indication signal Pol becomes H level, the same operation is repeated until the scanning signal Y320 becomes H level, whereby all the pixel capacitors 120 are pixel electrodes. The difference voltage between the voltage of the data signal applied to 118 and the voltage LCcom of the common electrode 108 and the storage capacitor 130 determine the difference voltage between the voltage of the data signal and the voltage Vsl, respectively. Keep up.
The operation of this (n + 1) frame mainly differs from the operation of n frames at the next two points. That is, firstly, the control circuit 20 sets the first capacitance signal Vc1 to the voltage Vsh higher by ΔV than the voltage Vsl as shown in FIG. 13, and secondly, the scan. When the latch pulse Lp is output at the timing immediately before the signal Yi becomes the H level, the data line driving circuit 190 is the i-th line, which is 1, 2, 3,... The display data Da of the 240th column of pixels is read, and as the data signals X1, X2, X3, ..., X240, the voltage corresponding to the display data Da and the negative polarity (these The meaning is later described), which is different from the operation of n frames.
Therefore, with respect to the operation in the (n + 1) frame, how does the voltage written in the pixel capacitor 120 in the i row and j columns change when the scan signal Yi becomes H level centering on such a difference point? This will be explained in terms of the possibility.
FIG. 14 is a diagram for explaining the voltage change of the pixel capacitor 120 in the i row and j columns in the (n + 1) frame.
First, when the scan signal Yi becomes H level, as shown in Fig. 14A, since the TFT 116 in the i row j columns is turned on, the data signal Xj is one of the pixel capacitors 120. It is applied to one end of the stage (pixel electrode 118) and the storage capacitor 130, respectively.
On the other hand, when the scan signal Yi is at the H level, the TFTs 154 and 156 corresponding to the i-th capacitor line 132 are turned on in the capacitor line driver circuit 150, and the TFTs 152 and 158 are turned off. Therefore, the voltage Ci of the i-th capacitor line 132 becomes the voltage Vsh of the first feed line 165. In addition, the common electrode 108 is constant at the voltage LCcom.
Therefore, when the voltage of the data signal Xj at this time is Vj, the voltage Vj-LCcom is charged in the pixel capacitor 120 in the i row j column, and the voltage Vj-Vsh is stored in the storage capacitor 130. Is charged.
Next, the gate control signal Cntg becomes H level before the scan signal Y1 becomes L level and before the scan signal Y2 becomes H level, i.e., all the scan signals are L level. For this reason, in the capacitor line driver circuit 150, all the TFTs 152 are turned on and all the TFTs 158 are turned on because the on voltage is reapplied to the gate electrode of the TFT 158. For this reason, the capacitance line 132 of the 1st-320th lines is connected to the 2nd feed line 166, and becomes voltage Vsl.
Here, the voltage Ci of the capacitor line 132 in the i-th row is lowered from the voltage Vsh to the voltage Vsl by a voltage ΔV compared with when the scan signal Yi is at the H level, but the common electrode ( 108 is constant with voltage LCcom. Therefore, the charge accumulated in the pixel capacitor 120 moves to the storage capacitor 130 as shown in FIG. 14B, so that the voltage of the pixel electrode 118 decreases. Specifically, in the series connection of the pixel capacitor 120 and the storage capacitor 130, the other end of the storage capacitor 130 is maintained with the other end (common electrode) of the pixel capacitor 120 kept at a constant voltage. Since the stage decreases by the voltage ΔV, the voltage of the pixel electrode 118 also decreases.
For this reason, the voltage of the pixel electrode 118 that is the series connection point is
Vj- {Cs / (Cs + Cpix)} · ΔV
Of the pixel capacitor 120 and the storage capacitor 130 to the voltage change ΔV of the capacitor line 132 of the i-th row, rather than the voltage Vj of the data signal when the scan signal Yi is at the H level. It is lowered by the value multiplied by the capacity ratio {Cs / (Cs + Cpix)}. That is, when the voltage Ci of the capacitor line 132 of the i-th row decreases by ΔV, the voltage of the pixel electrode 118 is less than the voltage Vj of the data signal when the scan signal Yi is at the H level. Cs / (Cs + Cpix)} · ΔV (= ΔVpix) decreases. However, the parasitic capacity of each part is ignored.
Here, in the (n + 1) frame to which the negative writing is designated, the data signal Xj when the scanning signal Yi is at the H level is a voltage at which the pixel electrode 118 is predicted to decrease by the voltage ΔVpix. (Vj) is set.
That is, the voltage of the pixel electrode 118 after being lowered is lower than the voltage LCcom of the common electrode 108 so that the voltage difference between them becomes a value according to the gray level of the i row and j columns. Specifically, in the present embodiment, firstly, as shown in Fig. 16A, in the n frame for the positive writing, the data signal is black b from the voltage Vw (+) corresponding to white w. As a range a up to the voltage Vb (+) corresponding to, when the gray level becomes lower (darker) and is set to be higher voltage than the voltage LCcom, as shown in the drawing (b), negative In the (n + 1) frame to be polarized write, the voltage is set to be the voltage Vb (+) when the pixel is white w, and is set to be the voltage Vw (+) when the pixel is the black b, and the positive voltage range a Same as, reverse the gradation relationship.
Second, after writing the voltage of the data signal in the (n + 1) frame, when the pixel electrode 118 drops by the voltage ΔVpix, the voltage of the pixel electrode 118 corresponds to a negative white color. The decrease in the voltage ΔV of the capacitor line 132 (that is, the voltage) is in the range from Vw (−) to the voltage Vb (−) corresponding to black so as to be symmetrical with the positive voltage with respect to the voltage LCcom. (Vsh, Vsl)).
Accordingly, in the (n + 1) frame for specifying the negative writing, the voltage of the pixel electrode 118 when the voltage is decreased by the voltage ΔVpix is the negative voltage according to the gray scale, that is, the voltage Vw corresponding to the white w. As a range c from (-) to the voltage Vb (-) corresponding to black b, the voltage becomes lower than the voltage LCcom as the gray level becomes lower (darker).
In FIG. 14, the pixel capacitors 120 and the storage capacitors 130 in the i rows and j columns are described, but the same operation is similarly performed for the i rows in which the scan lines 112 and the capacitor lines 132 are combined. In addition, in the (n + 1) frame, the scan signals Y1, Y2, Y3, ..., and Y320 become H levels in order, similarly to the n frame, so that the operation in each row is 1, 2, 3, … The pixels on the 320th line are also executed in order.
Therefore, in the present embodiment, the voltage range a of the data line in the (n + 1) frame specifying the negative writing is the same as the n frame specifying the positive writing, but after the shift, the pixel electrode 118 Becomes the negative voltage according to the gray scale. As a result, according to the present embodiment, not only the breakdown voltage of the elements constituting the data line driver circuit 190 is narrowed, but also the voltage amplitude in the parasitic data line 114 is also narrow, so that the parasitic capacitance This eliminates unnecessary power consumption.
In addition, although the voltage range of the data signal when the positive write is specified and the voltage range of the data signal when the negative write is specified, the data range is changed by the voltage change of the capacitor line 132 even if the voltage range of the data signal is not matched completely. The voltage amplitude of the signal can be suppressed.
The voltage range a in the positive and negative writings of the present embodiment will be described by comparing the conventional configuration. In the conventional configuration, the common electrode 108 is maintained at the voltage LCcom and the capacitor line ( The voltage at 132 is kept constant over each frame.
In this configuration, when the pixel capacitor 120 is driven in alternating current, a voltage in the range from the positive voltage Vw (+) to the voltage Vb (+) is applied to the pixel electrode 118 in accordance with the gradation in a predetermined frame. In this case, if there is no change in the gray scale, it is necessary to apply a voltage inverted based on the voltage LCcom as a range from the voltage Vw (−) corresponding to the negative polarity to the voltage Vb (−) in the next frame. .
For this reason, in the configuration where the voltage of the common electrode 108 is constant, when the voltage of the capacitor line 132 is constant, since the voltage of the data signal is in the range b in FIG. 16 (b), the data line driving circuit The breakdown voltage of the elements constituting 190 must also correspond to the range b. In addition, when the voltage changes in a wide range b in the data line 114 whose capacitance is parasitic, power is consumed unnecessarily by the parasitic capacitance.
In contrast, in the present embodiment, since the voltage range that the data signal supplied to the data line 114 can take in positive and negative writing is a range a narrower than the range b, the data line driving circuit 190 is constituted. While the breakdown voltage of the device can be narrow, the power consumed by the parasitic capacitance of the data line 114 can be suppressed.
According to the present embodiment, the i-th capacitor line 132 is connected to the first feed line 165 by turning on the i-th TFT 156 when the scan signal Yi is at the H level. After the scan signal Yi is changed from H to L level, the gate control signal Cntg becomes H level, so that the gate electrode of the i-th TFT 158 is turned on at the on voltage Von by the parasitic capacitance. Since it is maintained, the TFT 158 keeps on. For this reason, the capacitance line 132 of the i-th row does not become a state (high impedance state) which is not electrically connected to any part.
With respect to this point, when the data signal is changed in voltage, if the capacitor line 132 is in a high impedance state, noise or the like depending on the magnitude and direction of the voltage change in the data signal is superimposed, and the capacitor line 132 It will fluctuate with the voltage Vsl. For example, after the writing of the voltage to the pixel capacitor of the i-th row is finished, the data signal Xj supplied to the data line 114 of the j-th column is used for writing the voltage to the next pixel of the (i + 1) -th row. When the i-th capacitor line 132 is in a high impedance state when it rises, as shown in Fig. 17, the voltage Ci of the capacitor line 132 is increased by the spike noise N in response to the voltage rise. Overlaps. Here, when the i-th capacitor line 132 fluctuates with the voltage Vsl, charge transfer occurs, so that the voltage according to the gray scale cannot be maintained at the i-th pixel capacitor 120, and thus the display quality is reduced. It decreases.
In contrast, in the present embodiment, the on-voltage is periodically applied to the gate electrode of the TFT 158 with the gate control signal Cntg at the H level at the timing while the selection voltage is applied to the scan line 112. The capacitance line 132 of each row is connected to the second feed line 166 to avoid the high impedance state. For this reason, not only the data line 114 but also all the capacitor lines 132 are not affected by the voltage change of the scan lines. For this reason, according to this embodiment, the fall of the display quality according to the electric potential change of the capacitance line 132 is suppressed.
In the above description, 1, 2, 3,... The scanning line 112 is scanned in the order of the 320th row, but recently, the display area 100 is rotated to form 320, 319, 318,... In some cases, scanning may be required in the reverse order of the first row. In the present embodiment, the i-th TFTs 154 and 156 are turned on and off by the scanning signal Yi, but for the i-th TFT 152, the gate control is independent of the scanning direction by the scanning signal. Since the signal Cntg is turned on and off, it only reverses the output order of the scan signal.
In this embodiment, four TFTs 152, 154, 156, and 158 are sufficient to drive the capacitor lines 132 for one row. For this reason, it is also possible to avoid the complexity of the capacitance line driver circuit 150 which drives the capacitance line 132 corresponding to each row.
Fig. 15 is a diagram showing the relationship between the voltage of the scan signal, the capacitor line, and the voltage of the pixel electrode, and shows the change in voltage of the pixel electrode 118 in row i, column j as Pix (i, j). In this figure, the voltage Ci in the i-th capacitor line 132 is connected to the first feed line 165 when the scan signal Yi is at the H level, so that the voltage of the first capacitance signal Vc1 is reduced. When the voltage becomes the voltage and the gate control signal Cntg becomes H level, the on voltage Von is applied to and maintained at the gate electrode of the i-th TFT 158, and is connected to the second feed line 166 so as to be connected to the second feed line 166. It is maintained at the voltage of the two capacitance signals Vc2. For this reason, the voltage Ci is determined to be the voltage Vsl after the scanning signal Yi is changed from H to L level. The voltage Ci is determined as the voltage Vsl when the positive write is designated when the scan signal Yi reaches the H level, and as the voltage Vsh when the negative write is not specified.
<Application and Modification of Example 3 (1)>
In addition, in this description, by making the second capacitance signal Vc2 constant with the voltage Vsl, the voltage of the i-th capacitor line 132 is not changed in the n frame in which the positive writing is designated. In the (n + 1) frame for specifying negative writing, the capacitor line 132 of the i-th row is lowered by the voltage ΔV, and the pixel electrode 118 written when the scan signal Yi is at the H level has the voltage ΔVpix. Although lowered as much, you may reverse this.
That is, as shown in FIG. 18, by making the second capacitance signal Vc2 constant with the voltage Vsh, the voltage of the i-th capacitor line 132 is not changed in the frame specifying the negative writing. On the other hand, in the frame for specifying positive writing, the capacitor line 132 of the i-th line is raised by the voltage ΔV, and the pixel electrode 118 written when the scan signal Yi is at the H level is raised by the voltage ΔVpix. A configuration may be employed.
In this configuration, the voltage relationship of the data signal is inverted from Figs. 16 (a) and 16 (b) with reference to the voltage LCcom, and the positive write is the negative write and the negative write is performed. It is good to switch to positive writing, respectively.
<Application and Modification of Example 3 (2)>
In this explanation, although the polarity to write to the pixels in the period of one frame is set to be all the same, and the write polarity is inverted for each period of one frame, the scanning line for inverting the write polarity for each row is used. It is good also as a (line) inversion system.
In the case of the scanning line inversion method, the polarity indication signal Pol is inverted for each horizontal scanning period H as shown in FIG. 19, and the same scanning signal becomes H level in adjacent frames. When viewed in the period (where the same scan line is selected), the relationship is reversed. The first capacitor signal Vc1 is configured to have a voltage Vsl when the polarity indication signal Pol is at the H level, and to have a voltage Vsh when the polarity indication signal Pol is at the L level.
Accordingly, in the n frame of Fig. 19, the capacitance line 132 of the odd (1, 3, 5, ..., 319) rows has the scan signal for its own row from H to L level, and the gate Although the voltage does not change even when the control signal Cntg becomes H level, the capacitance line 132 of the even (2, 4, 6, ..., 320) row has the scan signal for its row from H to L level. Further, when the gate control signal Cntg becomes H level, the voltage decreases by the voltage ΔV. Therefore, in the n frame of Fig. 19, the positive writing as in Fig. 16A is performed in the odd row, while the negative writing as in Fig. 16B is performed in the even row.
On the other hand, in the (n + 1) frame of Fig. 19, the capacitance line 132 of the odd row has the scan signal for its own row from H to L level, and the gate control signal Cntg is H level. Is reduced by the voltage? V, the capacitor line 132 of the even row has a voltage change even when the scan signal for its row is from H to L level, and the gate control signal Cntg is at H level. I never do that. Therefore, in the (n + 1) frame of Fig. 19, the negative writing as in Fig. 16 (b) is performed in the odd row, while the positive writing as in Fig. 16 (a) is performed in the even row. do.
In addition, although the 2nd capacitance signal Vc2 was made into the voltage Vsl in FIG. 19, you may make it the structure which raises the voltage of the capacitor line 132 by (DELTA) V as voltage Vsh.
<Application and Modification of Example 3 (3)>
In the case where the scanning line inversion method is used in this manner, as shown in FIG. 20, the second capacitor signal Vc2 may be configured to have a constant voltage LCcom. When the second capacitance signal Vc2 is made constant by the voltage LCcom, in the n frame of FIG. 20, the capacitance line 132 of the odd row has the scan signal for its own row from H to L level. Further, when the gate control signal Cntg reaches the H level, the gate control signal Cntg rises from the voltage Vsl to the voltage LCcom, and the capacitor line 132 of the even row has the scan signal for its own row from H to L. When the gate control signal Cntg is at the H level, the voltage is lowered from the voltage Vsh to the voltage LCcom, and in the (n + 1) frame, the capacitance line 132 of the odd row is provided. When the scan signal for its own row goes from H to L level, and when the gate control signal Cntg becomes H level, the capacitor lines of the even row fall from the voltage Vsh to the voltage LCcom. 132, the scan signal for its own row goes from H to L level, and the gate control signal Cntg goes to H level. When taking, it is raised to a voltage (LCcom) from the voltage (Vsl).
Here, when the rising portion LCcom-Vsl from the voltage Vsl to the voltage LCcom and the falling portion Vsh-LCcom from the voltage Vsh to the voltage LCcom are equally set to ΔV, that is, When the voltage DELTA V = LCcom-Vsl = Vsh-LCcom is set, the capacitor line 132 of the i-th line has the scan signal Yi at the L level since the scan signal Yi is at the H level. When the gate control signal Cntg becomes H level, the gate control signal Cntg changes by the voltage? V. Therefore, in this example, Vsh-Vsl is 2ΔV, and the center of these two voltages Vsh and Vsl is the voltage of the second capacitance signal Vc2 and is the voltage LCcom applied to the common electrode 108. do.
21 is a diagram showing the voltage relationship between the scan signal, the capacitor line, and the pixel electrode, in which Pix (i, j) represents the voltage change of the pixel electrode 118 in row i and column j. In this figure, the voltage Ci on the i-th capacitor line 132 becomes the voltage Vsl when the scanning signal Yi becomes H level when the positive writing is specified, and the scanning signal Yi ) Becomes the level from H, and when the gate control signal Cntg becomes the H level, the voltage becomes LCLC and rises by the voltage ΔV. On the other hand, if negative writing is specified, the scan signal Yi is When it becomes H level, it becomes the voltage Vsh, and when the scanning signal Yi becomes level from H, and when the gate control signal Cntg becomes H level, it turns into voltage LCcom and falls by voltage (DELTA) V.
Note that the voltage Ci is connected to the second feed line 166 after the scan signal Yi is changed from H to L level, and is determined as the voltage Vsl as in FIG. 15.
When the capacitor line 132 rises or falls by the voltage ΔV, the pixel electrode 118 rises or falls by the voltage ΔVpix, so that the voltage of the data signal when the scan signal becomes H level predicts the variation of the voltage ΔVpix. Set to voltage.
In detail, when the positive writing is designated, as shown in Fig. 22A, the voltage LCcom is a range from the voltage Vw (+) to the voltage Vb (+) due to the increase in the voltage ΔVpix. Since the voltage may be shifted from the voltage to the voltage according to the gradation from, the voltage of the data signal may be set in the voltage range lowered from the voltage Vw (+) to the voltage Vb (+) by the voltage ΔPix.
On the other hand, if the negative writing is designated, as shown in Fig. 22B, the voltage Vcom (-) to the voltage Vb (-) are ranged from the voltage LCcom to the gray level by the drop of the voltage ΔVpix. Since it is sufficient to shift to a voltage spaced apart by the voltage according to the voltage, the voltage of the data signal may be set in a voltage range in which the voltage Vw (−) to the voltage Vb (−) are reversed by the voltage ΔPix.
At this time, if the voltage ΔV (voltage (Vsh, Vsl)) is set so that the voltage range of the data signal when the positive write is specified and the voltage range of the data signal when the negative write is specified in the range d, Therefore, the voltage amplitude of the data signal can be minimized.
In addition, in the normally white mode, the voltage range a in FIG. 22 is white when the white w side is low and black b is high when the positive writing is designated. The w side becomes high and the black b side becomes low, and the relationship of gradation is reversed.
<Application and Modification of Example 3 (4)>
In the i-th line of the capacitor line driver circuit 150, the period in which the TFTs 154 and 156 are turned on is a period in which the scan signal Yi becomes H level, and the period in which the TFT 152 is turned on is a gate. While the control signal Cntg is a period during which the H level is at the H level, the period during which the i-th TFT 158 is turned on is almost all over the i-th non-selection period (the period during which the scan signal Yi is at L level). Over. For this reason, in the TFT 158, compared with the TFTs 152, 154, and 156, since the period for turning on is considerably longer, transistor characteristics tend to deteriorate. In addition, deterioration of the transistor characteristic here means that the gate voltage (threshold voltage) for turning on as a switch becomes high with time. For this reason, as a long term use, the possibility of the malfunction that the TFT 158 does not turn on in a non-selection period becomes high.
Therefore, an application example aimed at suppressing the possibility of such a malfunction will be described.
Fig. 23 is a block diagram showing the configuration of an electro-optical device according to this application example.
As shown in this figure, in the application example, the TFT 158 is divided into two systems of the TFTs 158a and 158b, and is configured to alternately use.
In detail, in the capacitance line drive circuit 150 which concerns on an application example, it is divided into a system and b system in each row. Among these, the a system has TFTs 152a, 154a, and 158a, among which a source electrode of the TFT 152a is connected to the first on-voltage feed line 161a. Further, the b system has TFTs 152b, 154b, and 158b, among which a source electrode of the TFT 152b is connected to the second on voltage feed line 161b.
In this application example, the control circuit 20 supplies the signal Von-a to the first on voltage feed line 161a and the signal Von-b to the second on voltage feed line 161b, respectively. As an example of the voltage waveforms of the signals Von-a and Von-b, for example, as illustrated in FIG. 24, the signal Von-a becomes the on voltage Von in n frames, and the signal ( Von-b becomes the off voltage Voff, the signal Von-a becomes the off voltage Voff in the next (n + 1) frame, and the signal Von-b becomes the on voltage Von. Becomes
In this example, when the scan signal Yi goes from H to L level and the gate control signal Cntg goes to H level, the i-th capacitor line 132 is connected to the second feed line 166. In the n-frame where the signal Von-a becomes the on-voltage Von, the TFT 158a is used. In the (n + 1) -frame where the signal Von-b becomes the on-voltage Von, the TFT 158b is used. )to be. For this reason, according to the application example, since the period to be turned on when focusing on either of the TFTs 158a and 158b is halved in comparison with the TFT 158 in the third embodiment, malfunction due to long-term use It is possible to suppress the possibility of.
In this application example, all of Figs. 13, 18, 19, and 20 are applicable as the first capacitance signal Vc1, the second capacitance signal Vc2, and the polarity indication signal Pol.
In this application example, the source voltage of the TFT 152a is divided by dividing the on voltage feed line 161 of the third embodiment into a first on voltage feed line 161a and a second on voltage feed line 161b. Although connected to the one on-voltage feed line 161a and the source electrode of the TFT 152b to the second on-voltage feed line 161b, the gate control signal Cntg is divided into two systems, and the gate electrode of the TFT 152a is connected. The gate control signal Cntg of one system may be supplied to the gate control system, and the gate control signal Cntg of the other system may be supplied to the gate electrode of the TFT 152b.
In this application example, the transistors connecting the capacitor line 132 to the second power supply line 166 in the non-selection period are configured to switch at each frame period by the TFTs 158a and 158b. It doesn't work. In addition, it is not necessary to switch periodically, for example, it is good also as a structure which switches every time power supply is turned on (off).
In this application example, the configuration in which the TFTs 158 are divided into two TFTs 158a and 158b is shown. However, three or more TFTs may be used while switching in a predetermined order. That is, the purpose of the application example is to shorten the period for turning on any one of the TFTs 158 (to lengthen the period for turning off) and to reduce deterioration of transistor characteristics. Therefore, a plurality of TFTs ( At least one or more of the 158 may be turned off, one or more may be turned on, and the structure to switch the TFT 158 to be turned on in a predetermined order may be sufficient.
Next, Example 4 of the present invention will be described. 25 is a block diagram showing the configuration of an electro-optical device according to the fourth embodiment.
The configuration shown in this figure differs from that in the third embodiment (see Fig. 10) in that the TFT 155 (fifth transistor) is provided in each row of the capacitor line driving circuit 150. Therefore, with this point in mind, the TFT 155 in the capacitor line driver circuit 150 is provided corresponding to the capacitor lines 132 of 1 to 320 rows. Here, in the i-th row, the gate electrode of the TFT 155 is connected to the scanning line 112 of the (i + 1) -th row, which is the next row, the source electrode is connected to the on-voltage feed line 161, and the drain electrode thereof is It is connected to the gate electrode of the i-th TFT 158 with the drain electrode of the i-th TFT 152,154.
In addition, in Embodiment 4, in order to correspond to the 320th row which is the last row of a pixel array, the 321nd scanning line 112 is provided as a dummy, and the scanning line drive circuit 140 is provided with the scanning signal (the scan line 112 as a dummy). Y321) is provided.
FIG. 26 is a plan view showing the configuration near the boundary between the capacitor line driver circuit 150 and the display region 100 in the element substrate in the fourth embodiment.
In the figure, the portion that differs from the third embodiment (see Fig. 22) is that the TFT 152 is moved upward in the drawing, and the TFT 155 is provided in the area where space is generated by the relocation. It is at that point. The gate electrode of the i-th TFT 155 is a portion branched in a T-shape from the scanning line 112 in the (i + 1) -th row in the Y (upper) direction. In addition, a common drain electrode of the TFTs 152, 154, and 155 is connected to the gate electrode of the TFT 158 via a contact hole.
In FIG. 26, when the transistor size of the TFT 155 is represented by Tr 5, Tr 2 = Tr 3 = Tr 4> Tr 1 = Tr 5. However, as described later, the smaller the on-resistance of the TFT 156 is preferable. Therefore, Tr3 ≥ Tr4 ≥ Tr1 = Tr2 = Tr5.
In the capacitor line driver circuit 150 according to the fourth embodiment, the on voltage Von is applied to the gate electrodes of the TFTs 158 in each row when the gate control signal Cntg becomes H level. Or when the scanning signal of the next row becomes H level. Here, since the scanning signal of the next row becomes H level after the scanning signal of its own row becomes H level, that is, in the i-th row, the scanning signal i of the next row after the scanning signal Yi becomes H level +1) becomes H level. For this reason, according to the second embodiment, even when the gate control signal Cntg is not particularly supplied, the on voltage Von is maintained at the gate electrode of the TFT 158, and the ON of the TFT 158 is maintained so that the capacitor line ( 132 may be determined as the voltage of the second capacitance signal Vcl2.
In recent years, however, in addition to a mode (full screen display mode) in which all pixels are used, a mode of displaying a time, an icon, and the like using only pixels for a part of a row and turning off other pixels ( The partial display mode) can be appropriately switched in accordance with the operation state.
In the partial display mode, since the scanning signal similar to the full screen display mode is supplied to the scanning line of the row used for display, there is no change in the period at which the scanning signal becomes H level. However, since only the off level (white display voltage in normally white mode) is written to the pixel for the scan line of the row that is not used for display (non-display), the period in which the scan signal becomes H level Is extremely long compared to full screen display mode.
For example, in the partial display mode in which the display is performed using the pixels in the 81st to 160th rows among the 1st to 320th rows, and the other rows are not displayed, the scan signals Y1 to Y321 are shown in FIG. 27. For the scanning signals Y81 to Y160, the H level is sequentially set for every one frame period, but for the scanning signals Y1 to Y80 and Y161 to Y321, the H signals are only at the H level only once in a plurality of frame periods.
For this reason, in the configuration shown in FIG. 25, assuming that the configuration does not supply the gate control signal Cntg in the partial display mode, the voltage on the gate electrode of the TFT 158 in the non-displayed row is turned on. The interval at which (Von) is applied becomes long, and the on voltage (Von) cannot be maintained due to the leakage of the gate electrode. When the on-voltage Von cannot be maintained in the gate electrode, the TFT 158 is turned off, so that the capacitor line 132 is in a high impedance state, resulting in a drop in display quality due to voltage fluctuations.
In addition, according to the configuration in which the capacitor is actively added to the gate electrode of the TFT 158, it is possible to suppress the influence due to the leak, but there is a problem in that the window frame is widened by that amount.
Thus, in the case of the partial display mode, as shown in Fig. 27, the i-th TFT TFT is supplied by supplying the gate control signal Cntg, which periodically becomes H level, in the period in which either of the scanning signals becomes L level. Even if the period at which the scan signal i + 1 for the next row becomes H level becomes long, the gate electrode of 158 can be kept at the ON voltage Von without adding a capacitor.
In the example of the gate control signal Cntg shown in FIG. 27, the H level is set at every H frame, but may be H level at regular intervals in the period where all the scanning signals are L level. Therefore, in the example of the gate control signal Cntg, the third embodiment is also included, and in the period in which all the scan signals Y1 to Y320 are L level, for example, in the period in which all the scan signals are L level. The scan line of two rows may be selected to be H level each time.
Next, Example 5 of the present invention will be described. Fig. 28 is a block diagram showing the construction of an electro-optical device according to a fifth embodiment of the present invention.
The configuration shown in this figure differs from that in the third embodiment (see FIG. 10) mainly in that the TFT 159 (sixth transistor) is further provided in each row of the capacitor line driver circuit 150. And the detection line 168, the operational amplifier 30, and the resistance element 32 are provided.
Therefore, with reference to these points, the TFT 159 in the capacitor line driver circuit 150 is provided corresponding to the capacitor lines 132 of 1 to 320 rows. Here, the description will be made with the TFT 159 of the i-th row, the gate electrode is connected to the scanning line 112 of the i-th row, and the source electrode is the capacitor line 132 of the i-th row (that is, the TFTs 156, 158 of the i-th row). Common drain electrode), and the drain electrode is connected to the detection line 168.
On the other hand, in the fifth embodiment, the first capacitance signal Vc1 from the control circuit 20 is supplied to the non-inverting input terminal (+) of the operational amplifier 30, and the detection line 168 of the operational amplifier 30 It is connected to the inverting input terminal (-). The output signal from the operational amplifier 30 is supplied to the first feed line 165 and fed back to the inverting input terminal (-) of the operational amplifier 30 via the resistor element 32.
FIG. 29 is a plan view showing a configuration near the boundary between the capacitor line driver circuit 150 and the display region 100 in the element substrate in Example 5. FIG.
In this figure, portions different from the third embodiment (see FIG. 12) are the TFTs 156 and 158 than the first feed line 165 so that the detection line 168 extends in the Y direction in parallel with the first feed line 165. The TFT 159 is provided for each row.
Here, the gate electrode of the TFT 159 is a portion branched in a T-shape from the scanning line 112 in the Y (downward) direction and shared with the gate electrode of the TFT 156. In addition, the source electrode of the TFT 156 is a wide portion that branches and extends from the first feed line 165 and overcrosses the detection line 168.
The portion of the detection line 168 that crosses the scan line 112 and the capacitor line 132 formed of the gate electrode layer is made of the same third conductive layer as the first feed line 165, but is the source electrode of the TFT 156. The part which intersects with the wide part of the 1st feed line 165 consists of a gate electrode layer. For this reason, in the detection line 168, two contact holes are provided for each row, and are extended in the Y direction while alternately conducting electrical conduction in the wiring portion composed of the third conductive layer and the wiring portion composed of the gate electrode layer. have.
In the electro-optical device 10 according to the fifth embodiment, the operation when the i-th scanning signal Yi becomes H level will be described. 30 is a diagram showing an equivalent circuit of the capacitor line driver circuit 150 when the scan signal Yi is at the H level.
When the scan signal Yi becomes H level, as shown in the figure, the i-th TFTs 154, 156, and 159 in the capacitor line driver circuit 150 are turned on. When the i-th TFT 154 is turned on, the gate electrode of the TFT 158 is connected to the off-voltage feed line 162, so that the i-th TFT 158 is turned off. When the i-th TFTs 156 and 159 are turned on, the first feed line 165 to which the output signal of the operational amplifier 30 is supplied is connected to the i-th capacitor line 132, while Only the capacitor line 132 is connected to the detection line 168.
For this reason, the operational amplifier 30 performs the following operation. That is, when the voltage of the i-th capacitor line 132 detected through the detection line 168 is lower than the voltage of the first capacitance signal Vc1 supplied to the non-inverting input terminal (+), the operational amplifier 30 When the voltage at the output terminal is increased and conversely, when the i-th capacitor line 132 is higher than the voltage of the first capacitor signal Vc1, the voltage at the output terminal is lowered. Therefore, according to the fifth embodiment, when the scan signal Yi is at the H level, the voltage applied to the i-th capacitor line 132 is in balance at a point coinciding with the voltage of the first capacitance signal Vc1. Will be.
This operation is performed when the scan signals Y1, Y2, Y3, ..., Y320 become H level. And each of the capacitor lines 132 of the 320th row.
In addition, it is the same as that of Example 3 except the operation | movement when the scanning signal becomes H level and the capacitor line 132 is connected to the 1st feed line 165. FIG.
In addition, when the gate control signal Cntg is at the H level, that is, when all the scan signals are also at the L level, the detection line 168 is not connected to either of the capacitor lines 132. The amplifier 30 functions as a buffer circuit with voltage amplification factor "+1".
For example, when the voltage (Vsl or Vsh) cannot be applied to the i-th capacitor line 132 at the time of turning on due to lack of capability of the TFT 156, the pre-shift voltage is not correct. It may damage the quality. In contrast, according to the fifth embodiment, when the scan signal Yi becomes H level, the voltage of the first capacitance signal Vc1 is applied to the i-th capacitor line 132 by feedback control by the operational amplifier 30. Since it can apply correctly, display quality is not damaged.
In addition, according to the fifth embodiment, even when the on resistance of the TFT 156 is large, the capacitor line 132 of the i-th line is controlled by the feedback control by the operational amplifier 30 when the scan signal Yi becomes H level. Since the voltage of the first capacitor signal Vc1 can be applied accurately, a large transistor size is not required for the TFT 156. For this reason, in Example 3, the space required for the capacitor line driver circuit 150 becomes small and it becomes possible to narrow what is called a window frame outside the display area.
Further, even if a deviation occurs in the on resistance of the TFTs 156 of the 1st to 320th lines, when the scan signal of the corresponding row reaches the H level across each of the capacitor lines 132 of the 1st to 320th lines, Since the voltage of the single capacitance signal Vc1 can be equally applied, occurrence of display unevenness or the like due to voltage unevenness before the voltage shift can also be suppressed.
<Application and transformation>
In each embodiment, although the liquid crystal 105 is held between the pixel electrode 118 and the common electrode 108 as the pixel capacitor 120, the electric field direction corresponding to the liquid crystal is set to the substrate plane vertical direction. The electrode, the insulating layer, and the common electrode are laminated, and the present invention can also be applied to a configuration in which the electric field direction corresponding to the liquid crystal is in the horizontal direction of the substrate, for example, an IPS (in plain switching) mode or a fringe field switching (FFS) mode thereof.
In each of the embodiments, the vertical scanning direction is a direction from top to bottom in FIG. 10, but the vertical scanning direction may be a direction from the bottom to the up direction as described above.
In each of the above-described embodiments, when the pixel capacitor 120 is regarded as a unit, the write polarity is inverted for each frame period, but the reason is only to drive the pixel capacitor 120 in alternating current. The inversion period may be a period of two frames or more.
In addition, although the pixel capacitance 120 was set as the normally white mode, you may set it as the normally black mode which turns into a dark state in the voltage-free state. In addition, one dot may be formed by three pixels of R (red), G (green), and B (blue), and color display may be performed, and another one color (for example, cyan (C)) may be added. It is also possible to configure one dot with these four color pixels to improve the color reproducibility.
In the above description, the reference polarity of the write polarity is set as the voltage LCcom applied to the common electrode 108. However, this is a case where the TFT 116 in the pixel 110 functions as an ideal switch. Due to the parasitic capacitance between the gate and the drain of 116, the phenomenon that the potential of the drain (pixel electrode 118) decreases when the state changes from on to off (push down, push through, Field through, etc.) occur. In order to prevent deterioration of the liquid crystal, the pixel capacitor 120 should be alternating current driving. However, if the applied voltage LCcom to the common electrode 108 is alternatingly driven as a reference for the write polarity, the negative polarity is written. The effective value of the voltage of the pixel capacitor 120 by the pixel becomes slightly larger than the effective value by the positive write (when the TFT 116 is n-channel). For this reason, in practice, the reference voltage of the write polarity and the voltage LCcom of the common electrode 108 are made separately, and the reference voltage of the write polarity is higher than the voltage LCcom so that the influence of the push-down is canceled in detail. The offset may be set on the side.
In addition, since the storage capacitor 130 is insulated from DC, only the potential difference applied to the 1st feed line 165 and the 2nd feed line 166 should just be in the relationship mentioned above, for example, the voltage LCcom The potential difference between and may be several volts.
Next, an electronic apparatus having the electro-optical device 10 according to the embodiment described above as a display device will be described. 31 is a diagram illustrating a configuration of a mobile telephone 1200 using the electro-optical device 10 according to the embodiment.
As shown in this figure, the cellular phone 1200 includes the electro-optical device 10 described above along with the handset 1204 and the talker 1206 in addition to the plurality of operation buttons 1202. In addition, the component of the part corresponding to the display area 100 among the electro-optical devices 10 does not appear externally.
As the electronic apparatus to which the electro-optical device 10 is applied, in addition to the mobile phone shown in Fig. 31, a digital still camera, a notebook personal computer, a liquid crystal television, a viewfinder (or monitor direct view) video recorder, And a device equipped with a car navigation device, a pager, an electronic notebook, an electronic calculator, a word processor, a workstation, a picture phone, a POS terminal, and a touch panel. It goes without saying that the above-described electro-optical device 10 is applicable as a display device of these various electronic devices.
1 is a block diagram showing the configuration of an electro-optical device in Example 1;
2 is a diagram showing a display area in a partial display mode;
3 is a diagram illustrating a configuration of a pixel;
4 is a diagram illustrating a configuration of a boundary between a display area and a capacitor line driver circuit of Embodiment 1;
5 is a view for explaining the operation of the full screen display mode in the first embodiment;
6 is a diagram showing a relationship between a data signal and a holding voltage of Example 1;
7 is a view for explaining the operation of the partial display mode in Example 1;
8 is a block diagram showing the configuration of an electro-optical device in Example 2;
9 is a diagram showing the configuration of a first capacitor signal output circuit;
10 is a diagram showing the configuration of an electro-optical device according to a third embodiment of the present invention;
11 is a diagram illustrating a configuration of a pixel in the electro-optical device;
12 is a diagram showing a boundary configuration between a display region and a capacitance line driver circuit of the electro-optical device;
13 is a view for explaining the operation of the electro-optical device;
14 is a diagram showing negative writing of the electro-optical device;
15 is a voltage waveform diagram for explaining the operation of the electro-optical device;
16 is a diagram showing a relationship between a data signal and a holding voltage of the electro-optical device;
17 is a diagram illustrating stabilization of a capacitor line voltage in the electro-optical device;
18 is a diagram for explaining another configuration (part 1) of the electro-optical device;
19 is a view for explaining another configuration (part 2) of the electrokinetic optical device;
20 is a diagram for explaining another configuration (part 3) of the electro-optical device;
21 is a voltage waveform diagram for explaining another configuration (part 3);
22 is a diagram showing a relationship between a data signal and a holding voltage in another configuration (part 3);
23 is a diagram for explaining another configuration (part 4) of the electro-optical device;
24 is a view for explaining the operation of another configuration (part 4);
25 is a diagram showing the configuration of an electro-optical device according to a fourth embodiment of the present invention;
Fig. 26 is a diagram showing the boundary configuration between the display area and the capacitor line driver circuit of the electro-optical device;
27 is a view for explaining an operation of the electro-optical device;
28 is a diagram showing the configuration of an electro-optical device according to a fifth embodiment of the present invention;
29 is a diagram showing the boundary configuration between the display area and the capacitor line driver circuit of the electro-optical device;
30 is a diagram showing an equivalent circuit near the capacitance line driver circuit in the electro-optical device;
Fig. 31 is a diagram showing the configuration of a mobile telephone using the electro-optical device according to the embodiment.
10: electro-optical device, 20: control circuit, 30: operational amplifier, 100: display area, 105: liquid crystal, 108: common electrode, 110: pixel, 112: scan line, 114: data line, 116: TFT, 118: pixel Electrode, 120: pixel capacitor, 130: storage capacitor, 132: capacitor line, 140: scan line driver circuit, 150: capacitor line driver circuit, 152, 154, 156, 152, 154, 155, 156, 158, 159, 160, 171: TFT, 161: on voltage feeder, 162: off voltage feeder, 163: off voltage feeder, 165: first feeder, 166: second feeder, 167: gate control line, 168: detection line, 170: first capacitance Signal output circuit, 190: data line driving circuit, 1200: mobile phone
A plurality of scan lines, a plurality of data lines, a plurality of capacitor lines provided in correspondence with the plurality of scan lines, and a plurality of scan lines and the plurality of data lines are provided in correspondence to each other, and each of the data lines, the scan lines, and the pixels is provided. A pixel switching element connected between an electrode and a pixel switching element in which the pixel electrode is in a conductive state with the data line when the scanning line is selected, a pixel capacitor connected between the pixel electrode and a common electrode supplied with a constant voltage, and A driving circuit of an electro-optical device having a pixel including a storage capacitor connected between a pixel electrode and a capacitor line provided corresponding to the scanning line,
A scan line driver circuit for selecting the scan lines in a predetermined order;
For the capacitance line provided corresponding to one scan line, when the one scan line is selected, the first feed line is selected, and the scan line selected after the one scan line as the scan line spaced apart from the one scan line by a predetermined row is selected. The second feed line is selected again until the one scan line is selected, the voltage of each selected feed line is applied, and the voltage of the second feed line is set for all capacitance lines while all the scan lines are unselected. A capacitor line driver circuit to be applied,
A data line driver circuit for supplying a data signal corresponding to the gray level of the pixel via a data line to a pixel corresponding to the selected scan line.
And a drive circuit for the electro-optical device.
It is comprised so that the whole display mode which makes a whole screen into a display area, and the partial display mode which makes a partial area in the said whole screen into a display area, and makes another area into a non-display area can be selected. The line driving circuit applies the voltage of the second feed line to all of the capacitor lines while all the scanning lines are non-selected in the partial display mode.
The capacitor line driving circuit,
Corresponding to each of the capacitor lines, each of the first to fifth transistors includes
The first transistor corresponding to one capacitor line is connected to a scan line in which a gate electrode is spaced apart from a scan line corresponding to the one capacitor line by a predetermined row, and the source electrode supplies an on voltage for turning on the fourth transistor. Connected to the on-voltage feeder,
The second transistor is connected to a scan line corresponding to the one capacitance line, a gate electrode is connected to an off voltage feed line for supplying an off voltage for turning off the fourth transistor,
In the third transistor, a gate electrode is connected to the scan line corresponding to the one capacitor line, a source electrode is connected to the first feed line,
In the fourth transistor, a gate electrode is commonly connected to the drain electrodes of the first and second transistors, a source electrode is connected to the second feed line,
The fifth transistor is connected to an on-off voltage feeder supplying an on voltage or an off voltage for turning on or off a gate electrode thereof, and a source electrode is connected to the second feeder;
Drain electrodes of the third, fourth and fifth transistors are connected to the one capacitor line,
Configured to control the voltage of the on-off voltage feeder to the on voltage while all the scan lines are unselected
A drive circuit for an electro-optical device, characterized by the above-mentioned.
The voltage of the first and second feed lines is set so that the voltage of the one capacitor line is changed when the scan line spaced apart from the scan line corresponding to one capacitor line is selected. Driving circuit.
The voltage of the first feeder is that two different voltages are switched at predetermined cycles, and the voltage of the second feeder is constant.
And a correction circuit for supplying a voltage signal for causing the detection voltage of the capacitor line corresponding to the one scan line to be a target voltage when the one scan line is selected, to the first feed line. Circuit.
A plurality of capacitance lines provided corresponding to the plurality of scanning lines,
Provided in correspondence with the intersection of the plurality of scan lines and the plurality of data lines, each of which is connected to a data line, a scan line, and a pixel electrode, and the pixel electrode is in a conductive state with the data line when the connected scan line is selected. A pixel including a pixel switching element, a pixel capacitor connected between the pixel electrode and a common electrode supplied with a constant voltage, and a storage capacitor connected between the pixel electrode and a capacitor line corresponding to the scanning line;
With respect to the capacitance line provided corresponding to one scan line, when the one scan line is selected, a first feed line is selected, and the scan line selected behind the one scan line is selected as the scan line spaced apart from the one scan line by a predetermined row. After that, the second feeder line is selected until the single scan line is selected, the voltage of the selected feeder line is applied, and the voltage of the second feeder line is applied to all the capacitance lines while all the scanline is non-selected. A capacitor line driving circuit for applying
Electro-optical device comprising a.
The scanning lines of a plurality of rows, the data lines of a plurality of columns, the capacitance lines provided in each of the scanning lines of the plurality of rows, and the intersection of the scanning lines of the plurality of rows and the data lines of the plurality of rows are provided in correspondence with each other, and one end thereof is connected to the data lines. In addition, when the scan line is selected, the pixel switching element in which the one end is connected to the other end is in a conductive state, and the common electrode to which one end is connected to the other end of the pixel switching element, and the other end is supplied with a constant voltage. A drive circuit for an electro-optical device having a pixel capacitor including a pixel capacitor connected to and a storage capacitor connected between one end of the pixel capacitor and a capacitor line corresponding to the scanning line,
A capacitance line driver circuit for the capacitance line provided corresponding to one scanning line, connected to the first feeder line when the one scanning line is selected, and continuing connection to the second feeder line after the selection is finished;
Wherein the voltage of the first feed line when the one scan line is selected is set differently from the voltage of the second feed line.
The voltage of the first feeder is switched to two different voltages at predetermined cycles, and the voltage of the second feeder is constant.
The drive circuit of the electro-optical device, wherein the voltage of the second feed line is set to an intermediate value of two voltages of the first feed line.
A first, second, third and fourth transistors corresponding to each of the plurality of capacitor lines;
The first transistor corresponding to one capacitor line has a gate electrode connected to a gate control line, a source electrode connected to an on voltage feed line for supplying an on voltage for turning on the fourth transistor,
Drain electrodes of the third and fourth transistors connected to the one capacitance line
For one capacitor line, it has a plurality of sets of the first, second and fourth transistors,
Switching a fourth transistor connecting said one capacitor line to said second feed line in a predetermined order from said plurality of sets;
Further having a fifth transistor corresponding to each of the plurality of capacitor lines;
The fifth transistor corresponding to one capacitor line has a gate electrode connected to the scan line selected next to the scan line corresponding to the one capacitor line, a source electrode connected to the on voltage feed line, and a drain electrode connected to the Connected to the drain electrodes of the first and second transistors
With operational amplifiers,
A sixth transistor corresponding to each of the plurality of capacitor lines
In the sixth transistor corresponding to one capacitor line, a gate electrode is connected to the scan line corresponding to the one capacitor line, a source electrode is connected to the one capacitor line, and a drain electrode is connected to the detection line,
Wherein the operational amplifier controls the voltage of the first feed line such that the voltage of the detection line when the one scan line is selected becomes the target voltage.
Multi-line scanning lines,
Multiple columns of data lines,
A capacitance line provided in each of the plurality of scanning lines;
A pixel switching element provided in correspondence with the intersection of the plurality of rows of the scan lines and the plurality of columns of data lines, each of which is connected to the data line and is in a conducting state when a scan line is selected, and one of the pixels A pixel capacitor connected to the other end of the switching element, the other end connected to a common electrode supplied with a constant voltage, and a storage capacitor connected between one end of the pixel capacitor and the capacitor line corresponding to the scanning line. With pixels,
Electro-optical device, characterized in that.
An electronic device having the electro-optical device according to claim 7 or 15.
KR1020080046508A 2007-05-21 2008-05-20 Electro-optical device, driving circuit of electro-optical device, and electronic apparatus KR100949636B1 (en)
JP2007133792A JP4670834B2 (en) 2007-05-21 2007-05-21 Electro-optical device, electric optical device drive circuit, and electric device
JP2007134034A JP4428401B2 (en) 2007-05-21 2007-05-21 Electro-optical device, drive circuit, and electronic device
JPJP-P-2007-00134034 2007-05-21
JPJP-P-2007-00133792 2007-05-21
KR20080102980A KR20080102980A (en) 2008-11-26
KR100949636B1 true KR100949636B1 (en) 2010-03-26
ID=40071986
KR1020080046508A KR100949636B1 (en) 2007-05-21 2008-05-20 Electro-optical device, driving circuit of electro-optical device, and electronic apparatus
US (1) US20080291223A1 (en)
KR (1) KR100949636B1 (en)
TW (1) TWI396166B (en)
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2008-04-15 US US12/103,380 patent/US20080291223A1/en not_active Abandoned
2008-05-19 TW TW97118388A patent/TWI396166B/en not_active IP Right Cessation
2008-05-20 KR KR1020080046508A patent/KR100949636B1/en not_active IP Right Cessation
US20080291223A1 (en) 2008-11-27
KR20080102980A (en) 2008-11-26
TWI396166B (en) 2013-05-11
TW200907917A (en) 2009-02-16
JP2005234533A (en) 2005-09-02 Liquid crystal display and driving method thereof