Source: http://www.google.com/patents/US6754784?dq=system+for+measuring+web+traffic&ei=Lg8FT__TIIr-sQKzxaGRCg
Timestamp: 2015-07-07 18:45:14
Document Index: 83909990

Matched Legal Cases: ['ART1', 'ART 1', 'ART2', 'ART2', 'ART 1', 'ART1', 'ART1', 'ART2', 'ART2']

Patent US6754784 - Methods and circuits for securing encached information - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA system 100 including a central processing unit 101 operates in response to a set of instructions for processing information. A port 134 provides access to selected circuitry forming a part of the system by an external device. A set of non-volatile programmable security elements 136 selectively enable...http://www.google.com/patents/US6754784?utm_source=gb-gplus-sharePatent US6754784 - Methods and circuits for securing encached informationAdvanced Patent SearchPublication numberUS6754784 B1Publication typeGrantApplication numberUS 09/608,055Publication dateJun 22, 2004Filing dateJun 30, 2000Priority dateFeb 1, 2000Fee statusPaidAlso published asEP1256041A2, WO2001057627A2, WO2001057627A3Publication number09608055, 608055, US 6754784 B1, US 6754784B1, US-B1-6754784, US6754784 B1, US6754784B1InventorsGregory Allen North, Matthew Richard Perry, Brian Christopher KircherOriginal AssigneeCirrus Logic, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (19), Referenced by (43), Classifications (16), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethods and circuits for securing encached information
The preferred physical to DRAM addressing is shown in TABLE 6. TABLES 7 and 8 illustrate DRAM address mappings for 32- and 16-bit DRAM memory systems. The 32-bit is assumed to be based on two x16 devices connected to each RAS line with 32-bit DRAM operations selected. The mapping is repeated for every 256 Mbytes in each bank. The placeholder “n” is these tables is equal to 0�C +bank number. The 16/32-bit DRAM selection is programmed by setting a bit in system control register SYSCON2.
Integral to the processor core is a coprocessor which includes a register for translating virtual addresses issued by the CPU into the modified instruction and data virtual addresses (MVA) transmitted on IMVA and DMVA shown in FIG. 1B. Specifically, for addresses to the memory region from 0 to 32 MBytes, the virtual address VA is modified by a 7-bit process identifier as VMA=VA+(ProcID�32 MBytes), where the process identifier ProcID is either a read or write process identifier.
0x8000.0000
0x8000.0001
0x8000.0002
0x8000.0003
Port D data
0x8000.0040
0x8000.0041
0x8000.0042
0x8000.0043
PDDDR
0x8000.0080
Port E data
0x8000.00C0
0x8000.0100
0x8000.0140
SYSFLG
0x8000.0180
0x8000.01C0
0x8000.0200
DRFPR
0x8000.0240
0x8000.0280
0x8000.02C0
0x8000.0300
0x8000.0340
0x8000.0380
RTCDR
0x8000.03C0
RTCMR
0x8000.0400
PMPCON
PWM pump
0x8000.0440
0x8000.0480
UARTDR1
8W/11R
UART1 FIFO
0x8000.04C0
UBLCR1
UART 1 bit
0x8000.0500
0x8000.0540
PALMSW
0x8000.0580
0x8000.05C0
STFCLR
0x8000.0600
BLEOI
0x8000.0640
MCEOI
0x8000.0680
0x8000.06C0
TC1EOI
0x8000.0700
TC2EOI
0x8000.0740
RTCEOI
0x8000.0780
UMSEOI
0x8000.07C0
COEOI
0x8000.0800
0x8000.0840
0x8000.0880
0x8000.0FFF
0x8000.1000
FBADDR
0x8000.1100
SYSCON2
0x8000.1140
SYSFLG2
0x8000.1240
0x8000.1280
0x8000.12C0-
0x80000.147F
0x8000.1480
UARTDR2
UART2 Data
0x8000.14C0
UBLCR2
UART2 bit
0x8000.1500
SS2DR
0x8000.1600
SRXEOF
0x8000.16C0
SS2POP
Write to pop
0x8000.1700
KBDEOI
0x8000.1800
0x8000.1840-
0x8000.1FFF
INTSR1
EXTFIQ
External fast interrupt
Battery low interrupt
Watchdog expired
Media changed interrupt
Codec sound interrupt
TC10I
TC1 underflow interrupt
TC2 underflow interrupt
RTC compare match
64 Hz tick interrupt
UTXINT1
Internal UART 1
URXINT1
Internal UART1 receive
UMSINT
Internal UART1 modem
SSEOTI
INTSR2
KBDINT
SS2RX
Master/slave SSI 16 bytes
SS2TX
UTXINT2
UART2 transmit FIFO empty
URXINT2
UART2 receive FIFO full
INTSR3
MCP interface interrupt
deglitched;
case 20 μs;
PLL/ocs.
approx. 0.25 s
for 20 μs
FASTWAKE =
0, or approx.
500 μs when
that 1 μs
FASTWAKE = 1,
NEINT1-2
deglitched
MEDCHG
As above (note
case 80 μs;
difference if
in 13 MHz mode
of 80 μs
with CLKENSL
least 80 μs
61 μs
(NCS0)
0000.0000-0FFF.FFFF
CS7 (Internal only)
1000.0000-1FFF.FFFF
CS6 (Internal only)
2000.0000-2FFF.FFFF
3000.0000-3FFF.FFFF
4000.0000-4FFF.FFFF
5000.0000-5FFF.FFFF
6000.0000-6FFF.FFFF
7000.0000-7FFF.FFFF
A[27]/DRA[0]
A[26]/DRA[1]
A[25]/DRA[2]
A[24]/DRA[3]
A[23]/DRA[4]
A[22]/DRA[5]
A[21]/DRA[6]
A[20]/DRA[7]
A[19]/DRA[8]
A[18]/DRA[9]
A[17]/DRA[10]
A[16]/DRA[11]
A[15]/DRA[12]
Address Range of Segments
9 Row � 9 Column
n000.0000-n00F.FFFF
10 Row � 10 Column
n000.0000-n03F.FFFF
12 Row � 8 Column
n000.0000-n007.FFFF
n010.0000-n017.FFFF
n040.0000-n047.FFFF
n050.0000-n057.FFFF
n100.0000-n107.FFFF
n110.0000-n117.FFFF
n140.0000-n147.FFFF
n150.0000-n157.FFFF
11 Row � 11 Column
n000.0000-n0FF.FFFF
13 Row � 9 Column
n000.0000-n01F.FFFF
n040.0000-n05F.FFFF
n100.0000-n11F.FFFF
n140.0000-n15F.FFFF
n400.0000-n41F.FFFF
n440.0000-n45F.FFFF
n500.0000-n51F.FFFF
n540.0000-n55F.FFFF
12 Row � 12 Column
n000.0000-n3FF.FFFF
13 Row � 13 Column
n000.0000-nFFF.FFFF
Address Range of Segments(s)
n000.0000-n003.FFFF
n008.0000-n00B.FFFF
n020.0000-n023.FFFF
n028.0000-n02B.FFFF
n080.0000-n083.FFFF
n088.0000-n08B.FFFF
n0A0.0000-n0A3.FFFF
n0A8.0000-n0AB.FFFF
n000.000-n07F.FFFF
n020.0000-n02F.FFFF
n080.0000-n08F.FFFF
n0A0.0000-n0AF.FFFF
n200.0000-n20F.FFFF
n220.0000-n22F.FFFF
n280.0000-n28F.FFFF
n2A0.0000-n2AF.FFFF
n000.0000-n1FF.FFFF
n000.0000-n7FF.FFFF
LCD FIFO
PLL/CLKEN
Pin No. LQFP
SSICCLK
SSICCLK =
PCMCLK =
SSITXFR
SSKTXFR =
PCMSYNC =
LRCK =
TX frame
SSITXDA
SSITXDA =
PCMOUT =
SDOUT =
TX data;
SSIRXDA
SSIRXDA =
PCMIN =
SDIN =
RX data;
SSIRXFR
SSIRXFR =
*p/u = use an 10 k pull-up TABLE 11
SP/Microwire 1
SPI/Microwire 2
MCP Interface
CD quality DACs
Only for use in
the PLL clock
13.0 MHz
18.432-73.728
MHz Operation
ADCCLK Frequency
ADCCLK Fre-
RO Contents
Big Endian Memory
Little Endian Memory
Word +0
44112233
Word +2
33441122
31:0 0x2440
UNIQCHK
0x2450
8 bit hamming code for
159:128
32 bit ID #2
191:160
0x2704
32 bit ID #3
223:192
0x2708
32 bit ID #4
UNIQID5
255:224
0x270C
Hamming codes and flags
UNIQCHK2
UNIQCHK3
UNIQCHK4
ASECEX
Reserved ‘0’
PRIVATE ID number
PRIVHAM
PRIVATE hamming code for
PRIVFLG
Private firmware exists
ID all 0's
CHK all 0's
ID all 1's
CHK all 1's
ID-CHK pair
UNIQVAL
UNIQID-UNIQCHK
UNIQVAL2
0x2720
UNIQID2-UNIQCHK2
UNIQVAL3
0x2724
UNIQID3-UNIQCHK3
UNIQVAL4
UNIQID4-UNIQCHK4
SECVAL1
SECID1-SECCHK1
SECVAL2
0x2544
SECID2-SECCHK2
0x27AC
32 bit general register
TESTCHK
0x2753
8 bit general register
Validation for TESTID-TESTCHK
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711/163, 713/193, 711/138, 711/E12.075International ClassificationG06F1/00, G06F12/12, G06F21/00, G10L19/00Cooperative ClassificationG06F2211/1097, G06F21/71, G06F21/572, G06F12/126European ClassificationG06F21/57A, G06F21/71, G06F12/12B6Legal EventsDateCodeEventDescriptionJun 30, 2000ASAssignmentOwner name: CIRRUS LOGIC, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NORTH, GREGORY ALLEN;PERRY, MATTHEW RICHARD;KIRCHER, BRIAN CHRISTOPHER;REEL/FRAME:010904/0048Effective date: 20000131Dec 26, 2007FPAYFee paymentYear of fee payment: 4Dec 31, 2007REMIMaintenance fee reminder mailedDec 22, 2011FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services