Source: http://www.google.com/patents/US7132720?ie=ISO-8859-1
Timestamp: 2014-03-13 12:52:02
Document Index: 701190057

Matched Legal Cases: ['Application No. 2002', 'art 102', 'art 102', 'art 1', 'art 2', 'art 3', 'art 2', 'art 3', 'art) 4', 'art 1', 'art 2', 'art 4', 'art 4', 'art 102']

Patent US7132720 - Semiconductor device having guard ring and manufacturing method thereof - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn interlayer insulation film is etched to form contact holes in an integrated circuit part. At this time, a trench is not formed in a guard ring part. Subsequently, ion implantation is carried out in source/drain regions in a peripheral circuit part for contact compensation, and high-temperature annealing...http://www.google.com/patents/US7132720?utm_source=gb-gplus-sharePatent US7132720 - Semiconductor device having guard ring and manufacturing method thereofAdvanced Patent SearchPublication numberUS7132720 B2Publication typeGrantApplication numberUS 10/650,810Publication dateNov 7, 2006Filing dateAug 29, 2003Priority dateAug 30, 2002Fee statusPaidAlso published asUS7411257, US20040042285, US20070013011Publication number10650810, 650810, US 7132720 B2, US 7132720B2, US-B2-7132720, US7132720 B2, US7132720B2InventorsKazutaka Yoshizawa, Kazuki Sato, Shinichiroh IkemasuOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (7), Referenced by (2), Classifications (25), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device having guard ring and manufacturing method thereofUS 7132720 B2Abstract An interlayer insulation film is etched to form contact holes in an integrated circuit part. At this time, a trench is not formed in a guard ring part. Subsequently, ion implantation is carried out in source/drain regions in a peripheral circuit part for contact compensation, and high-temperature annealing is carried out in order to activate implanted impurities. Subsequently, an interlayer insulation film, a storage capacitor, and another interlayer insulation film are formed in sequence. Then, contact holes reaching a part of wiring layers are formed in the peripheral circuit part while, in the guard ring part, a trench reaching a diffusion layer is formed. Next, a barrier metal film is formed in each of the contact holes and the trench, and further, a contact plug comprising, for example, a W film is buried therein.
CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-255332, filed on Aug. 30, 2002, the entire contents of which are incorporated herein by reference.
Next, ion implantation for forming an LDD (Lightly Doped Drain) structure is carried out to form a diffusion layer 115. Next, sidewalls 116 comprising Si3N4 are formed. Next, an interlayer insulation film 117 comprising BPSG (Boron-Phospho Silicate Glass) and TEOS (Tetra Ethyl Ortho Silicate) is deposited over the entire surface and reflow of this interlayer insulation film 117 is carried out. This reflow is carried out at a temperature of 800� C. in the atmosphere of N2 for 20 minutes. Then, the interlayer insulation film 117 is planarized by a CMP (Chemical Mechanical Polishing) method or the like. The foregoing steps are MOSFET forming steps in generally known DRAM manufacturing technology.
Subsequently, as shown in FIG. 27, the source/drain portions and the portions requiring the substrate contact such as the diffusion layer resistances inside the peripheral circuit part 102 undergo ion implantation for contact stabilization in the peripheral circuit part 102 between the semiconductor substrate 111 (diffusion layer 115) and wiring layers to be formed thereafter comprising refractory metal. Then, in order to activate implanted impurities, furnace annealing or RTA (Rapid Thermal Annealing) such as ramp annealing is conducted. The temperature of this high-temperature annealing is set to about 1000� C.
Even if high-temperature annealing is sufficiently applied, for example, at 1000� C. for five seconds before the contact holes 121 to 123 are formed, the interlayer insulation film 117 similarly suffers heat shrinkage when it undergoes another heat treatment after these contact holes are formed.
SUMMARY OF THE INVENTION The present invention is made in light of the above problem. It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof which enable the prevention of deformation of contact holes formed in an interlayer insulation film to realize stable contact.
A fourth manufacturing method of a semiconductor device according to the present invention aims at a manufacturing method of a semiconductor device including a semiconductor substrate, an integrated circuit part formed on the semiconductor substrate, and a guard ring part formed on the semiconductor substrate and surrounding the integrated circuit part to prevent moisture intrusion from the outside. According to this manufacturing method, first in the integrated circuit part, a gate insulation film and a gate electrode are formed on the semiconductor substrate, and a pair of impurity diffusion layers are formed in a surface of the semiconductor substrate to sandwich the gate electrode in a plan view. Next, a first interlayer insulation film covering at least the gate electrode and the pair of impurity diffusion layers are formed to extend over the integrated circuit part and the guard ring part, and contact holes reaching at least the pair of impurity diffusion layers and a first trench reaching the semiconductor substrate in the guard ring part are formed in the first interlayer insulation film. Thereafter, a wiring layer connected to at least the pair of the impurity diffusion layers via the contact holes are formed on the first interlayer insulation film, and a first buried conductive layer is buried in the first trench. Note that the temperature of the semiconductor substrate is set to 800� C. or lower during the period from the step of forming the contact holes and the first trench to the step of forming the wiring layer and burying the first buried conductive layer.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view showing the structure of a semiconductor device according to an embodiment of the present invention;
FIG. 8 is a sectional view taken along II�II line in FIG. 1;
FIG. 15 is a sectional view taken along III�III line in FIG. 14;
FIG. 16 is a sectional view taken along IV�IV line in FIG. 14;
FIG. 17 is a sectional view taken along V�V line in FIG. 14;
FIG. 19 is a sectional view taken along VI�VI line in FIG. 18;
FIG. 21A and FIG. 21B are sectional views taken along VI�VII line and VIII�VIII line in FIG. 20, respectively;
FIG. 23A and FIG. 23B are sectional views taken along IX�IX line and X�X line in FIG. 22, respectively;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Concrete explanation of a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be given with reference to the attached drawings. FIG. 1 is a schematic plan view showing the structure of a semiconductor device according to an embodiment of the present invention.
First Embodiment The first embodiment of the present invention will be first explained. A DRAM (semiconductor device) according to this embodiment is roughly defined into a memory cell array part 1 having a memory cell array provided therein, a peripheral circuit part 2 having drive circuits of memory cells and so on, and a dicing line part 3 on an outer periphery of a chip. Between the peripheral circuit part 2 and the dicing line part 3, a guard ring part (moisture resistant ring part) 4 is provided. The memory cell array part 1 and the peripheral circuit part 2 constitute an integrated circuit part.
Next, a sectional structure of the semiconductor device as described above will be explained. Note that the sectional structure of the semiconductor device will be explained along with a manufacturing method thereof for convenience' sake. FIG. 3 to FIG. 7 are sectional views showing a manufacturing method of the semiconductor device according to the first embodiment of the present invention in the order of its steps. Note that FIG. 3 to FIG. 7 are sectional views taken along I�I line in FIG. 1. FIG. 8 is a sectional view taken along II�II line in FIG. 1.
Next, ion implantation for forming an LDD (Lightly Doped Drain) is conducted to form diffusion layers 15. Next, sidewalls 16 comprising, for example, Si3N4 are formed. Thereafter, an interlayer insulation film 17 comprising BPSG (Boron-Phospho Silicate Glass) or TEOS (Tetra Ethyl Ortho Silicate) with a film thickness of, for example, about 1 μm is deposited over the entire surface, and reflow of this interlayer insulation film 17 is carried out. This reflow is carried out under the conditions of, for example, the temperature of 800� C., the atmosphere of N2, and the duration of 20 minutes. Then, the interlayer insulation film 17 is planarized by a method such as CMP (Chemical Mechanical Polishing). The foregoing steps are MOSFET forming steps in generally known DRAM manufacturing technology.
Then, after the resist mask is removed, RTA (Rapid Thermal Annealing) such as ramp annealing is conducted in order to activate the implanted impurities. This RTA is conducted, for example, at a temperature of 1000� C. for five seconds. This series of processes from the ion implantation to the annealing lowers a contact resistance.
Subsequently, after a SiN film and an oxide film to be a capacitor dielectric film 33 are formed by a CVD method, opposing electrodes 34 comprising doped amorphous Si are formed. Through these steps, capacitors are formed. In forming the capacitor dielectric film 33, for example, the SiN film is formed at 650� C. and the oxide film is formed at 680� C. The thickness of the opposing electrodes 34 is, for example, about 10 nm.
Second Embodiment Next, the second embodiment of the present invention will be explained. FIG. 13 is a schematic plan view showing the structure of a semiconductor device according to the second embodiment of the present invention.
Third Embodiment Next, the third embodiment of the present invention will be explained. In the third embodiment, similarly to the first embodiment, a guard ring is formed in a ring shape. But it is different from the first embodiment in a layer structure thereof. FIG. 14 is a schematic plan view showing the structure of a part of a guard ring part of a semiconductor device according to the third embodiment of the present invention. FIG. 15 to FIG. 17 are sectional views taken along III�III line, IV�IV line, and V�V line in FIG. 14, respectively.
Fourth Embodiment Next, the fourth embodiment of the present invention will be explained. FIG. 18 is a schematic plan view showing the structure of a part of a guard ring part of a semiconductor device according to the fourth embodiment of the present invention. FIG. 19 is a sectional view taken along VI�VI line in FIG. 18.
Fifth Embodiment Next, the fifth embodiment of the present invention will be explained. In the fifth embodiment, a guard ring part 4 is structured similarly to any of the first to the fourth embodiment, and a guard ring part for fuse portion having the same structure as that of the guard ring part 4 is provided around a fuse portion provided near a memory cell array part.
FIG. 20 is a schematic plan view showing the structure of the fuse portion of the semiconductor device in the prior art. FIG. 21A is a sectional view taken along VII�VII line in FIG. 20 and FIG. 21B is a sectional view taken along VIII�VIII line in FIG. 20. FIG. 22 is a schematic plan view showing the structure of the fuse portion of a semiconductor device according to the fifth embodiment of the present invention. FIG. 23A and FIG. 23B are sectional views taken along IX�IX line and X�X line in FIG. 22, respectively.
Sixth Embodiment Next, the sixth embodiment of the present invention will be explained. A semiconductor device in the sixth embodiment has the same structure as that of the conventional one shown in FIG. 30 and so on. However, after the contact holes 122, 123 and the trench 147 are formed, annealing for lowering a contact resistance, which is conducted before the wiring layers 125 are buried, is conducted at a temperature of 800� C. or lower. FIG. 24 is a graph showing the correlation between annealing temperature for lowering a contact resistance and a maximum deformation amount of the contact holes 121 to 123 in the peripheral circuit part 102, the horizontal axis taking the annealing temperature and the vertical axis taking the maximum deformation. Note that FIG. 24 also shows for reference the correlation between the annealing temperature and the width of an upper end portion of the trench after the annealing.
As shown in FIG. 24, at the annealing temperature of 800� C. or lower, the contact hole deformation amount is 0.5 nm or smaller even with the same structure as that of the prior art. Therefore, wiring layers can be sufficiently buried in the contact holes.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5196910 *Feb 4, 1991Mar 23, 1993Hitachi, Ltd.Semiconductor memory device with recessed array regionUS5652459 *May 6, 1996Jul 29, 1997Vanguard International Semiconductor CorporationMoisture guard ring for integrated circuit applicationsUS6498089 *Sep 19, 2001Dec 24, 2002Fujitsu LimitedSemiconductor integrated circuit device with moisture-proof ring and its manufacture methodUS6525398 *Aug 29, 2000Feb 25, 2003Samsung Electronics Co., Ltd.Semiconductor device capable of preventing moisture-absorption of fuse area thereofUS6683329 *Feb 28, 2002Jan 27, 2004Oki Electric Industry Co., Ltd.Semiconductor device with slot above guard ringUS20030193090 *Jun 25, 2001Oct 16, 2003Miharu OtaniSemiconductor device and method of manufacturing the semiconductor deviceKR20020017589A * Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7381640 *Jul 10, 2006Jun 3, 2008Hynix Semiconductor Inc.Method of forming metal line and contact plug of flash memory deviceUS7829925 *Aug 6, 2007Nov 9, 2010Nec Electronics CorporationSemiconductor device and method for manufacturing same* Cited by examinerClassifications U.S. Classification257/409, 257/E23.002, 257/E21.657, 257/E21.66, 257/E29.013, 257/E23.019International ClassificationH01L29/94, H01L27/04, G11C7/00, H01L21/8242, H01L23/52, H01L21/82, H01L21/3205, H01L21/822, H01L23/00, H01L27/108, H01L23/485Cooperative ClassificationH01L23/564, H01L27/10885, H01L2924/13091, H01L23/485, H01L27/10894European ClassificationH01L27/108M8, H01L23/564, H01L23/485Legal EventsDateCodeEventDescriptionJul 9, 2010ASAssignmentOwner name: FUJITSU SEMICONDUCTOR LIMITED,JAPANEffective date: 20100401Free format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:24651/744Owner name: FUJITSU SEMICONDUCTOR LIMITED, JAPANFree format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:024651/0744Apr 29, 2010FPAYFee paymentYear of fee payment: 4Dec 9, 2008ASAssignmentOwner name: FUJITSU MICROELECTRONICS LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021976/0089Effective date: 20081104Owner name: FUJITSU MICROELECTRONICS LIMITED,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100203;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100209;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100216;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100223;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100225;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100302;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100316;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100323;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100329;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100330;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100406;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100413;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100420;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100427;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100511;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100518;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;US-ASSIGNMENT DATABASE UPDATED:20100525;REEL/FRAME:21976/89Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:21976/89Aug 29, 2003ASAssignmentOwner name: FUJITSU LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YOSHIZAWA, KAZUTAKA;SATO, KAZUKI;IKEMASU, SHINICHIROH;REEL/FRAME:014448/0960;SIGNING DATES FROM 20030806 TO 20030814RotateOriginal ImageGoogle Home - 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