Source: http://www.google.com/patents/US8117381?dq=7069184
Timestamp: 2016-05-31 12:22:25
Document Index: 296342323

Matched Legal Cases: ['Application No. 200480041681', 'Application No. 200480041681', 'Application No. 200480041681', 'Application No. 2006', 'Application No. 2006', 'Application No. 200480041681']

Patent US8117381 - Adaptive deterministic grouping of blocks into multi-block units - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThe present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where...http://www.google.com/patents/US8117381?utm_source=gb-gplus-sharePatent US8117381 - Adaptive deterministic grouping of blocks into multi-block unitsAdvanced Patent SearchPublication numberUS8117381 B2Publication typeGrantApplication numberUS 13/084,396Publication dateFeb 14, 2012Filing dateApr 11, 2011Priority dateDec 30, 2003Fee statusPaidAlso published asCN1930635A, CN1930635B, DE602004024582D1, EP1700313A1, EP1700313B1, US7970985, US20050144516, US20090292944, US20110191530, WO2005066974A1Publication number084396, 13084396, US 8117381 B2, US 8117381B2, US-B2-8117381, US8117381 B2, US8117381B2InventorsCarlos J. Gonzalez, Alan Douglas Bryce, Sergey Anatolievich Gorobets, Alan David BennettOriginal AssigneeSandisk Technologies Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (24), Non-Patent Citations (9), Referenced by (5), Classifications (21), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetAdaptive deterministic grouping of blocks into multi-block units
The physical means for storing the charge in the memory cell can be implemented by using a floating gate transistor, such as an electrically erasable programmable read only memory (EEPROM). One known problem with floating gate devices such as EEPROMs is that the floating gate eventually wears out and breaks down after a very large number of write, program and erase cycles. When this happens, the cell is no longer usable and must be taken out of the list of available memory cells in the array. This sort of defect is called a “grown” defect. In one commercially available implementation, these defects are dealt with by mapping out the defective cells and substituting the physical addresses of good memory cells for the newly detected defective memory cells. Examples of implementations where defective cells or sectors are mapped out and replaced are described in U.S. Pat. No. 5,659,550 issued on Aug. 19, 1997 by Mebrotra et at; U.S. Pat. No. 5,671,229 issued on Sep. 23, 1997 by Baran et al.; and in U.S. Pat. No. 5,862,080 issued on Jan. 19, 1999 by Harari et al., which applications are expressly incorporated herein in their entirety by this reference.
Generally, the memory system of the present invention maintains in its main non-volatile memory a record of the linking of blocks into multi-block metablock structures. This record contains a defect map of factory and gown defects in a map table that can be read into non-volatile memory on demand. This map is updated as grown defects are encountered and blocks are assigned to new locations. Metablocks are preferable formed by one block in each of several subarrays, or planes, and in this case, the grouping is done preferably with same-numbered blocks in each plane, with the exception of blocks that are marked bad and placed in the map. In one embodiment, the blocks are directly mapped to alternate blocks. Metablocks that would contain the defective block are then reformed with the alternate block in the corresponding plane. Rather than maintain a complete record of the linking of blocks into metablocks within the non-volatile memory, a “standard” linking can be based on an algorithm implanted, for example, in the system's firmware, with only the deviations due to defects from this algorithm needing to be stored. Those standard metablocks with no defects present will be termed usable standard metablocks. The remaining Metablocks are termed unusable standard metablocks, and the component physical blocks will be termed spare blocks.
FIG. 8 shows the state of the array after a third new defect is encountered. The new defect is located at the physical block labeled “C”, located at block 4 on plane 0. This metablock cannot be re-linked because the defective block is located on plane 0. The block located on plane 0 is the block that contains the reference information to the rest of the members of the metablock, and without the block on plane 0, there is no way to reference the metablock under the adopted convention. Therefore, even though a spare block is available at block 1 on plane 0, it cannot be used to complete this metablock. Instead, block 1 on plane 0 is re-mapped into the virtual address space and used as the first block in a new metablock to take advantage of the now redundant blocks in planes 1, 2, and 3 of the former metablock MB4. Thus, defective block “A” can be replaced by block 4 of plane 2. As block 1 of plane 3 has been remapped FIG. 7, it will also need to be replaced. Consequently, a re-linked MB1 can be formed using the spares at block 4 from planes 2 and 3. For plane 1, a block is available in both block 1 and block 4. Although either can be chosen to complete the re-linked MB1, the block formerly in MB4 is used in the example. Consequently, the re-linked MB1 comprises block 1 on plane 0, block 4 on plane 1, block 4 on plane 2 and block 4 on plane 3. At this point, only one spare block remains at block 1 on plane 1.
The defect map aspect of the present invention is illustrated in FIG. 12, which shows a bad block at on plane 1. The bad block is marked with an “X.” Before the block was found to be defective, the second member of the metablock LBN[0] pointed to that block, as shown by dotted line arrow 1201. The collection of spare blocks 1203 has a spare available on the same plane that is shown by the hatch marks. (Alternately, if a spare was available in plane 1 from another linking that had developed an error, as in the process of FIGS. 5-10, it could be used instead of a block from the collection of spares 1203.) The physical block number (PBN) of the spare PBN′ will replace the PBN of the block that failed. As a result, this spare becomes part of the metablock, as shown by arrow 1202.
A “standard” metablock comprises physical blocks whose physical block addresses are a deterministic function of the metablock number. For example, this could be the arrangement of metablock MB0 in FIG. 4 b, which is also used for the example of FIGS. 5-10, where all of the blocks of a standard metablock are in the same row. This arrangement can be represented as MB1=(i,i,i,i), where the nth entry in the parentheses represent the row to which the block in the nth plane belongs.
As noted above with respect to FIG. 4 d, there are also configurations using two dimensional meta-blocks that link block not only across planes and chips, but also in depth within a given plane. FIG. 21 shows an example of re-linking in the two-dimensional case. In FIG. 21, the ‘2-D metablock’ is example of a 2*4 metablock. The maximum benefit in performance can be achieved when all 8 blocks can be accessed in parallel. The main linking and re-linking principles of 1-D linking methods also apply, but with some extensions. As can be seen in the figure, a bad physical block in any of the physical blocks within a plane lead to a metablock being unused; as is shown for Metablock n. When a 2-D metablock is re-linked, as for the upper block of Metablock n+2 in plane 2, only the bad physical block in a given plane needs to be replaced; for example, for the upper block of Metablock n+2 in plane 2 is re-linked while the lower block of Metablock n+2 in plane 2 is not.
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No. 10/750,157 mailed Sep. 15, 2010, 22 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8261174 *Jan 13, 2009Sep 4, 2012International Business Machines CorporationProtecting and migrating memory linesUS8612839Jul 31, 2012Dec 17, 2013International Business Machines CorporationProtecting and migrating memory linesUS8924636 *Sep 11, 2012Dec 30, 2014Kabushiki Kaisha ToshibaManagement information generating method, logical block constructing method, and semiconductor memory deviceUS20100180179 *Jan 13, 2009Jul 15, 2010International Business Machines CorporationProtecting and migrating memory linesUS20130227246 *Sep 11, 2012Aug 29, 2013Kabushiki Kaisha ToshibaManagement information generating method, logical block constructing method, and semiconductor memory device* Cited by examinerClassifications U.S. Classification711/103, 711/209, 711/200, 711/165, 365/230.03, 711/102, 365/185.11, 711/203, 711/100International ClassificationG06F3/06, G06F12/00, G11C29/00, G06F12/02Cooperative ClassificationG06F12/0246, G11C29/76, G11C29/808, G06F2212/7208, G06F2212/7201European ClassificationG11C29/76, G11C29/808, G06F12/02D2E2Legal EventsDateCodeEventDescriptionMar 2, 2012ASAssignmentOwner name: SANDISK TECHNOLOGIES INC., TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:027800/0175Effective date: 20120228Jul 29, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services