Source: http://www.google.com/patents/US6993105?dq=7,339,580
Timestamp: 2014-09-20 18:28:38
Document Index: 613536275

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US6993105 - Linearized digital phase-locked loop - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal and a position of the first edge, (B) determining if the position is within a zone, (C) if the edge is not within the zone, adjusting the clock signal towards the position...http://www.google.com/patents/US6993105?utm_source=gb-gplus-sharePatent US6993105 - Linearized digital phase-locked loopAdvanced Patent SearchPublication numberUS6993105 B1Publication typeGrantApplication numberUS 09/747,257Publication dateJan 31, 2006Filing dateDec 22, 2000Priority dateMay 9, 2000Fee statusPaidPublication number09747257, 747257, US 6993105 B1, US 6993105B1, US-B1-6993105, US6993105 B1, US6993105B1InventorsTerry D. Little, Bertrand J. Williams, Kamal Dalmia, Timothy D. JordanOriginal AssigneeCypress Semiconductor Corp.Export CitationBiBTeX, EndNote, RefManPatent Citations (21), Non-Patent Citations (5), Referenced by (4), Classifications (6), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetLinearized digital phase-locked loopUS 6993105 B1Abstract A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal and a position of the first edge, (B) determining if the position is within a zone, (C) if the edge is not within the zone, adjusting the clock signal towards the position of the edge, (D) detecting a second edge of the data signal and a position of the second edge, (E) determining a in value indicating a position of the second edge, (F) adding the first value to a second value, wherein the second value indicates a position of a third edge of the data signal and (G) adjusting the clock signal based on the result of step (F).
1. A method of synchronizing a clock signal to a data signal, comprising the steps of:
(A) detecting a first edge of said data signal and a position of said first edge;
(B) determining if said position of said first edge is within a zone;
(C) if said first edge is not within said zone, adjusting said clock signal towards said position of said first edge;
(D) detecting a second edge of said data signal and a position of said second edge;
(E) determining a first value indicating said position of said second edge;
(F) adding said first value to a second value to generate a third value, wherein said second value indicates a position of a third edge of said data signal; and
(G) adjusting said clock signal based on the result of said third value.
comparing said third value to a predetermined value and adjusting said clock signal only if said third value is greater than said predetermined value.
determining if said third value is within a predetermined zone and adjusting said clock signal only if said third value is not within said predetermined zone.
comparing said third value to said predetermined zone.
5. The method of claim 1, wherein step (E) further comprises selecting a number of clock phases based upon said third value.
6. The method of claim 1, wherein step (F) further comprises:
adjusting said third value in response to said second value when adding said first value and said second value would cause an overflow or underflow.
incrementing or decrementing said first value.
storing said first value; and
storing said second value.
9. The method according to claim 1, wherein step (E) further comprises:
determining a high or low bandwidth in response to steps (A)�(D).
10. The method according to claim 1, wherein step (E) further comprises:
determining a plurality of phase offset magnitudes in response to steps (A)�(D).
11. The method according to claim 1, wherein step (E) further comprises:
determining a magnitude of said third value.
This application claims the benefit of U.S. Provisional Application No. 60/203,678, filed May 12, 2000, U.S. Provisional Application No. 60/203,616, filed May 12, 2000, U.S. Provisional Application No. 60/203,677, filed May 12, 2000, U.S. Provisional Application No. 60/203,676, filed May 12, 2000, U.S. Provisional Application No. 60/203,718, filed May 12, 2000, U.S. Provisional Application No. 60/203,160, filed May 9, 2000 and are hereby incorporated by reference in its entirety.
CROSS REFERENCE TO RELATED APPLICATIONS The present application may relate to U.S. Pat. No. 6,366,145, U.S. Pat. No. 6,417,698, U.S. Patent No. 6,711,226, U.S. Pat. No. 6,535,023, and co-pending application Ser. No. 09/747,188, filed Dec. 22, 2000, which are each hereby incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION Conventional approaches for implementing PLLs include the bang�bang approach which comprises taking snapshots of the phase error with respect to edges of incoming data. The bang�bang approach corrects on every data edge based solely on the direction (polarity) of the offset. As a result, a bang�bang system is never truly �locked�. In the best case, a bang�bang system is nearly locked and makes a correction at every data edge (i.e., clocks are either switched clockwise or counter clockwise depending on the polarity of the phase offset). The bang�bang approach has the disadvantage of introducing excessive jitter in the resulting recovered clock since the clock is being shrunk or expanded at every edge.
Referring to FIG. 1, a circuit 10 implementing a conventional bang�bang approach for constructing digital phase locked loops is shown. The circuit 10 involves the use of over sampling methods to determine in which quadrant of the clock the data edge resides. The quadrant information is then applied to an adjustment mechanism which moves the clock the appropriate direction at each interval. No information associated with the magnitude of phase error is retained or utilized. Polarity of the error and presence of a data transition are the only information used to adapt the phase of the clock to the incoming datastream.
Referring to FIG. 2, a flow diagram 30 illustrating the operation of the conventional bang�bang circuit 10 is shown. The circuit 10 checks for a data edge and determines the relative polarity between the data and clock. If the polarity of the data relative to the clock is positive, the clocks are switched counterclockwise. If the polarity of the data relative to the clock is negative, the clocks are switched clockwise.
Since the circuit 10 does not use magnitude information, a transfer function is exhibited at the phase detector which has the characteristics typical of a bang�bang approach. Such detectors have an inability to tolerate large input signal distortion, such as the distortion that may be found at the end of typical wired media.
SUMMARY OF THE INVENTION The present invention concerns a method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal and a position of the first edge, (B) determining if the position is within a zone, (C) if the edge is not within the zone, adjusting the clock signal towards the position of the edge, (D) detecting a second edge of the data signal and a position of the second edge, (E) determining a in value indicating a position of the second edge, (F) adding the first value to a second value, wherein the second value indicates a position of a third edge of the data signal and (G) adjusting the clock signal based on the result of step (F).
FIG. 1 is a block diagram of a conventional bang�bang system;
FIG. 2 is a flow diagram illustrating the operation of the conventional bang�bang circuit of FIG. 1;
The circuit 104 generally comprises a circuit 110, a circuit 112, a circuit 114 and a circuit 116. The circuit 104 may also comprise a number of memory elements 118 a�118 n and a number of buffers 120 a�120 n. The circuit 110 may be implemented as an edge detection circuit. The circuit 110 may present a signal (e.g., DATAPULSE) to the logic block 102. The signal DATAPULSE may be generated in response to a signal (e.g., DI�N) and a signal (e.g., DI�P). In one example, the circuit 110 may be configured to generate a pulse signal in response to a transition of a data signal. The circuit 112 may be implemented as a bandwidth limiting circuit. The circuit 112 may present a signal (e.g., LIMIT) to the logic block 102. The signal LIMIT may limit a bandwidth of the logic block 102. The circuit 114 may be implemented, in one example, as a phase lock loop (PLL). The PLL circuit 114 may present a number of clock signals (e.g., PLL�CLK�0�PLL�CLK�N) to the circuit 116. The circuit 116 may be implemented as a multiplexer circuit. The circuit 116 may present a number of signals (e.g., CLK(A:D)). In one example, the circuit 116 may be implemented as a multiple input multiplexer that may present an output signal based on a control signal (e.g., SEL) generated by the logic block 102. The circuit 116 may be configured to select a number of the signals PLL�CLK�0�PLL�CLK�N for presentation as the signals CLK(A:D) in response to the signal SEL.
The filter 124 may accumulate digital numerical values. In a linear system, a capacitance element is utilized to integrate charge into voltage. The phase-switcher 126 combined with a multi-phase reference clock signals PLL�CLK0�PLL�CLK�N and CLK(A:D) effectively emulates VCO performance by allowing continual, though discrete-increment movement, of the clock phase edges into the system.
The operation of the present invention may be easily demonstrated by considering a simple sequence. Presume an incoming datastream DI�N and DI�P is distorted such that the edges occur at −J nS and +K nS, where 0 nS is the ideal non-distorted location of the edges, or the �average� location of the edges. Further presume that mechanisms associated with real systems during acquisition and normal operation are such that the magnitude of J and K are not necessarily equal. The conventional �bang�bang� digital PLL would see −J1, +K1, −J2, +K2, −J3, +K3, etc. and generate a response, as a control to the internal phase-switcher, which would cause the clock to decrement in phase, then increment, decrement, increment, etc, no matter what the values of J and K.
For the USB 2.0 specification (published April 2000 and hereby incorporated by reference in its entirety), a conventional bang�bang digital PLL will be marginal, if operable, to the system specifications for datastream distortion. Alternative implementations of the phase-detector may vary primarily in the exact construction of the numerical slicing/detection method or conversion of phase-alignment to a numerical value or input to the accumulator. Variants of the filter block 124 are ordinarily limited to the magnitude of the accumulator threshold level detection for enabling a phase-adjustment of the phase-switcher block 126. Other filter clock variants may allow for the effective detection limit to adapt to acquisition conditions to allow for combination of fast acquisition and maximum tolerance when acquired. The implementation variants of the phase-switcher 126 and reference clock functions are predominantly associated with the number of raw clock phases available (e.g., 2N) for selection-switching, and the incrementer/decrementer and associated clock-mux design and timing.
The circuit 100 implements a dual bandwidth linearized digital PLL similar to that described in co-pending provisional application (Ser. No. 60/203,678) which is hereby incorporated by reference in its entirety. The system 100 additionally implements the clocks sampled by data method described in co-pending provisional application (Ser. No. 60/203,616), which is hereby incorporated by reference in its entirety.
A detailed description of an operation of the logic block 102 will now be described. An incoming serial data signal DI�N and DI�P may be sampled on the rising and falling edges to generate the signal DATAPULSE. The signal DATAPULSE may be used to clock the current values of the clocks CLK(A:D) into the register REG1. The value of the register REG1 may be encoded into a 3-bit signal (via the coder 130) comprising one bit of polarity information and two bits of magnitude information. The coded value generally represents the offset of the sampled clocks to the ideal sample point in the serial data stream. The coded value is generally clocked into the register REG2 on the falling edge of the signal CLKA (e.g., A(fall)).
When the register REG5 is updated the select values into the PLL clock select multiplexer(s) 116 are changed, thus changing the mapping between the input PLL clocks (PLL�CLK�0�PLL CLK�N) and the internally sampled clocks CLK(A�D). For example, where the input PLL clocks are all 480 MHz clocks with ⅛ bit of phase difference, the selection may result in a ⅛ bit time phase adjustment on the sample clock CLKA.
The value in the register REG4 is generally decoded into a 1 of 8 value that is clocked into the register REG5 on the next falling edge of CLKA. When the register REG5 is updated, select values into the PLL clock select multiplexers are changed, thus changing the mapping between the input PLL clocks PLL�CLK-0�PLL�CLK�N and the internally sampled CLK[A�D]. Using the example where the input PLL clocks PLL�CLK�0�PLL�CLK�N are all 480 MHz clocks with ⅛ bit of phase difference, a ⅛ bit time phase adjustment on the sample clock CLKA may be made. The apparatus for determining the operational mode (e.g., HIGH or LOW bandwidth) is the bandwidth limit logic 112. The logic 112 may be implemented, in one example, as a 4-bit counter that is cleared by an external signal and clocked by the falling edge of CLKA. However, other bit width counters may be implemented accordingly to meet the design criteria of a particular implementation. The counter may assert the signal DATAVALID at a first predetermined count (e.g., seven bit times) and assert the bandwidth limit signal LIMIT at a second predetermined count (e.g., fifteen bit times). The assertion of the bandwidth limit signal LIMIT changes the mode of the PLL from the high bandwidth �acquire� mode to the low bandwidth �tracking� mode. The circuit 100 may present the output clock as the inversion of the current CLKA. The data is generally recovered by sampling the data stream with a falling edge of the signal CLKA (e.g., through two D flip-flops) and then again with a rising edge of the signal CLKA (e.g., through a third D flip-flop) to ensure that it is synchronized with the output recovered clock.
Referring to FIG. 6, a method (or process) 200 is shown. The method 200 generally comprises a decision state 202, a state 204, a state 206, a state 208, a decision state 210, a decision state 212, a decision state 214, a decision state 216, a state 218 and a state 220. The decision state 202 generally determines if a data edge is present. If a data edge is not present, the decision state 202 continues to check for such a condition. If a data edge is present, the state 204 determines a relative polarity and phase-offset magnitude for the data and clock. The state 206 adds the polarity and magnitude to a previously accumulated value stored in the state 208. Next, the state 208 stores the next accumulated value from the state 206. The decision state 210 determines if a high bandwidth condition has occurred. If such high bandwidth condition has occurred, the state 212 determines the polarity from the state 204. If the polarity is positive, the state 218 switches clock counter clockwise and returns to the state 202. If the state 212 determines that the polarity from the state 204 is negative, the state 216 determines if the magnitude in the state 208 is less than −M. If no, the method 200 returns to the state 202. If the magnitude of the value of the state 208 is less than −M, the state 220 switches the clocks clockwise and returns to the state 202.
Referring back to the state 210, if a high bandwidth condition is not detected, the state 214 determines if the magnitude of the state 208 is greater than n. If so, the method moves to the state 218 where the clocks are switched counter clockwise and the method 200 returns to the state 202. If the magnitude stored in the state 208 is not greater than n, the method moves to the state 216.
The present invention may be implemented as a method of synchronizing a clock signal to a data signal, comprising the steps of (A) upon power-up, performing said synchronization with a high bandwidth system, (B) after a predetermined amount of time, performing said synchronization with a low bandwidth system and (C) adding a first value to a second value to produce a third value. The second value represents a position of a second edge of the data signal. The present invention may also be implemented as an apparatus for synchronization of a clock signal to a data signal comprising a detector configured to synchronize with a high bandwidth system. The detector may be configured after a predetermined amount of time to perform the synchronization with a low bandwidth system. The detector may comprise an accumulator that adds a first value to a second value to produce a third value. The second value may represent a position of a second edge of the data signal.
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