Source: https://patents.google.com/patent/EP1005163A2/en
Timestamp: 2019-08-22 23:00:45
Document Index: 717400427

Matched Legal Cases: ['art 11', 'application No. 09', 'application No. 08', 'application No. 09', 'application No. 09', 'application No. 09']

EP1005163A2 - Programmable logic device architectures - Google Patents
EP1005163A2
EP1005163A2 EP99309072A EP99309072A EP1005163A2 EP 1005163 A2 EP1005163 A2 EP 1005163A2 EP 99309072 A EP99309072 A EP 99309072A EP 99309072 A EP99309072 A EP 99309072A EP 1005163 A2 EP1005163 A2 EP 1005163A2
EP99309072A
EP1005163B1 (en
It is a more particular object of this invention to provide arrangements for the logic and memory blocks on large programmable logic devices which facilitate provision of large amounts of anticipated interconnections on a "local" basis, using relatively short interconnection conductors, so that the amount of more "expensive" longer-length interconnection resources can be reduced, thereby helping to limit the fraction of overall device resources that must be devoted to interconnection resources.
Inclusion of a memory region in each super-region helps reduce the need to use the third level of interconnection conductor resources. For example, each memory region can work with the logic regions of the super-region that includes that memory region by using only the first and second level interconnection conductor resources of that super-region. This is illustrative of the ways in which the programmable logic device organizations ("architectures") of this invention help reduce or at least hold down overall interconnection resource requirements on large programmable logic devices.
FIG. 11 (consisting of part lla on the left and part 11b on the right) is a more detailed but still simplified schematic block diagram of the FIG. 9 circuitry.
FIG. 3 also shows that the conductors 100 associated with each column of memory regions 40 (FIG. 1) are divided into two groups: regular conductors 100 and tri-state conductors 100'. Each memory region 40 in a column has a tri-state driver 210 for programmably selectively applying an output of that memory region to selected ones of the tri-state conductors 100' associated with that column. Drivers 210 and conductors 100' are used when several memory regions in a column are being used together to provide a deeper memory than can be provided by one memory region alone. See Pedersen U.S. patent application No. 09/023,251, filed February 13, 1998, for additional information regarding this type of use of several memory regions together. The just-mentioned Pedersen reference is hereby incorporated by reference herein in its entirety.
An illustrative subregion 50 is shown in more detail (although still simplified) in FIG. 6. Further detail regarding possible constructions of subregion 50 can be found in Cliff et al. U.S. patent application No. 08/902,416, filed July 29, 1997, which is hereby incorporated by reference herein in its entirety. However, such further detail is not believed necessary for an understanding of the present invention.
A representative memory region 40 is shown in more detail in FIG. 9. Certain principles of memory region construction that are shown and described in Cliff et al. U.S. patent 5,550,782, Cliff et al. U.S. patent 5,689,195, and Heile U.S. patent application No. 09/034,050, filed March 3, 1998, can be used in memory region 40. Thus additional details regarding certain aspects of memory region 40 can be found in those other references, all of which are hereby incorporated by reference herein in their entireties. However, it is not believed that those additional details are necessary for an understanding of the present invention.
In p-term mode 32 bits of a so-called "p-term literal" are assembled on leads 530 from the 16 leads 514, the six leads 516, the six leads 520, and four leads 526 that are otherwise used for high order read address signals. As is explained in more detail in above-mentioned Pedersen U.S. patent application No. 09/023,251, these high order address bits are used when several memory regions 40 in a column are used together to provide a deeper memory than can be provided by one memory region alone. The signals on leads 530 are inverted by inverters 532, and both the true and complement versions of the lead 530 signals are applied to PLCs 590 via leads 534. In p-term mode PLCs 590 are programmed to apply the signals on leads 534 to leads 592. Accordingly, half the rows in RAM block 510 are read simultaneously, the rows thus read being determined by which bits of the p-term literal on leads 530 are logic 1 and which bits are logic 0. Each column in RAM block 510 outputs via the associated lead 598 the product of the data stored in the rows that are enabled. OR gates and related elements in circuitry 600 allow sums of the products on leads 598 to be formed and output via leads 602. Thus in p-term mode memory region 40 produces sum-of-products output signals on leads 602.
Data can be read from inverters 710/720 by applying logic 1 to row read lead 592. This enables transistor 780. If transistor 770 is also enabled by a logic 1 output from inverter 710, a conductive path is established between source line 598a and drain line 598b. A sense amplifier (600 in FIG. 9) senses whether there is such a conductive path between lines 598a and 598b.
FIG. 11 shows how a representative memory region 40 is connected to the adjacent interconnection conductors. FIG. 11 shows a memory region 40 which is part of a super-region 20 in which the logic regions 30 are to the left of the memory region. If the logic regions 30 were to the right of memory region 40, the circuitry would be a mirror image of FIG. 11. For convenience herein the side of memory region 40 toward the adjacent logic regions 30 is sometimes called the "region side" of the memory region. The side of memory region 40 which is remote from the adjacent logic regions 30 is sometimes called the "super-region side" of the memory region.
The signals that are data signals 514 in FIG. 9 come from circuitry 810 in FIG. 11. Circuitry 810 is a group of registers that can be either (1) used to register signals from the leads 180 feeding that circuitry from the logic region side of memory region 40, or (2) bypassed to allow unregistered connection of those leads 180 to leads 514. The data applied to RAM block 510 via leads 514 can therefore be either "registered or bypassed", based on programmable control of circuitry 810. The "registered or bypassed" option is also available with other signals in FIG. 11 as will be described below.
Circuitry 850 is similar to circuitry 820, except that it provides signals that can be used elsewhere in memory 40 primarily for output control. For example, circuitry 850 produces clock and clear signals usable by registers in "registered or bypassed" circuitries 860 and 870 and in the output stage 640 of circuitry 600. Each of circuitries 860, 870, and 640 can alternatively use the clock and clear signals from circuitry 820. Circuitry 850 receives its inputs from the super-region side of memory region 40. Circuitry 850 also receives an enable signal from circuitry 880. In providing this enable signal, circuitry 880 operates somewhat like circuitry 830. In particular, when several memory regions 40 are to be used together to provide a deeper memory than one memory region can provide, circuitry 880 receives and decodes higher order address signals to determine whether the associated memory region is the one that should currently output data. If so, circuitry 880 outputs a signal for enabling circuitry 850, which in turn applies read enable signal 522 to circuitry 590.
Circuitry 640 is programmable to either pass the memory output signals selected by circuitry 630 or to form desired sums of the product terms ("p-terms") represented by the outputs of sense amplifier circuitry 610. Additional details regarding how circuitry 630 can be constructed are shown in above-mentioned Heile U.S. patent application No. 09/034,050. Thus circuitry 640 includes the OR circuitry needed to form various sums of the applied p-term signals. Circuitry 640 also receives the clock and clear signals from circuitries 820 and 850, and can use these signals in providing a "registered or bypassed" option for either the outputs of circuitry 630 or the sum-of-products signals generated within circuitry 640.
The driver bank 190/200/270 on the left in FIG. 11 (i.e., on the region side of memory region 40) receives (1) subregion output signals 340b from the region 30 to the left, (2) selected outputs 602 of memory region 40, (3) signals from the vertical conductors 100 to the left, and (4) signals from the horizontal conductors 110 associated with the row of super-regions 20 that includes the memory region. This driver bank 190/200/270 is programmable to select from among these signals and drive them out onto selected ones of (1) adjacent local feedback conductors 160b, (2) the immediately above-mentioned vertical conductors 100 and 110, and (3) the global horizontal conductors 140 associated with the super-region 20 that includes the depicted memory region 40.
The driver bank 190/200 on the right in FIG. 11 (i.e., on the super-region side of memory region 40) receives (1) all the outputs 602 of memory region 40, (2) signals from the vertical conductors 100/100' to the right, and (3) signals from the horizontal conductors 110 associated with the row of super-regions 20 that includes the memory region. This driver bank is programmable to select from among these signals and drive them out onto selected ones of the immediately above-mentioned conductors 100 and 110 and the global horizontal conductors 140 associated with the super-region 20 that includes the depicted memory region 40.
FIG. 12 shows in more detail an illustrative construction of the two driver banks 190/200/270 and 190/200 shown in FIG. 11. The driver groups labelled "A" in FIG. 12 can be like the driver groups shown in FIG. 8. (The portion 270 of FIG. 8 is included or not in each group A in FIG. 12 depending on whether or not that group has associated local conductors 160b that may need to be driven.) The driver groups labelled "B" in FIG. 12 are like the above-described alternative to FIG. 8 that can be alternated with the FIG. 8 driver group to produce approximate overall homogeneity to the interconnectivity provided by these drivers. FIG. 12 shows how the 16 outputs 602 of the memory region are distributed to the inputs of the various driver groups A and B, it being understood that in most cases in FIG. 12 the indicated signals 602 take the place of the correspondingly positioned subregion outputs 340 in FIG. 8. For example, in the upper left-hand driver group A in FIG. 12, the two left-hand inputs from subregions 50 are as in FIG. 8, but the two right-hand inputs are memory region outputs 602 for bit 0 and bit 2. As another example, in the upper right-hand driver group A the two individual inputs on the left are memory region outputs 602 for bit 0 and bit 1 and the two inputs on the right are memory region outputs 602 for bit 8 and bit 9. Sufficient connectivity is provided in FIG. 12 to give each memory region output 602 several different ways out to the adjacent conductors 100, 110, and 140. FIG. 12 also shows again the tri-state output to conductors 100' via PLCs 882.
It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the number of logic units at each of the various levels in the hierarchy of logic units can differ from the specific examples mentioned herein. Similarly, the numbers of the various types of interconnection conductors and other elements can deviate from the specific examples mentioned herein. Different types and sizes of logic and memory units can be used if desired. It will also be understood that terms like "row" and "column", "horizontal" and "vertical", "left" and "right", "top" and "bottom", and other directional or orientational terms are used herein only for convenience, and that no fixed or absolute orientations are intended by the use of these terms. For example, the words in each of the word pairs mentioned above can be reversed if desired.
a plurality of super-regions disposed on the device in a two-dimensional array of intersecting rows and columns of such super-regions, each of said super-regions including a plurality of regions of programmable logic and a region of memory, each of said logic regions having a plurality of inputs and a plurality of outputs and being programmable to perform any of several logic functions on its inputs to produce its outputs, and said memory region also having a plurality of inputs and a plurality of outputs and being responsive to its inputs to produce its outputs based at least in part on its inputs and data stored in the memory region; and
programmable interconnection circuitry for selectively connecting said outputs to said inputs.
The device defined in claim 1 wherein, for each of the super-regions, the interconnection circuitry comprises:
a plurality of first interconnection conductors uniquely associated with that super-region, each of the first conductors that is associated with a super-region extending substantially continuously adjacent to all of the regions in that super-region.
The device defined in claim 2 wherein the interconnection circuitry further comprises:
The device defined in claim 1 wherein each of said logic regions includes a plurality of subregions of programmable logic, each of said subregions having a subplurality of the inputs and at least one of the outputs of the logic region that includes that subregion, and each subregion being programmable to perform any of a plurality of logic functions on its input to produce its output.
The device defined in claim 2 wherein each of said logic regions includes a plurality of subregions of programmable logic, each of said subregions having a subplurality of the inputs and at least one of the outputs of the logic region that includes that subregion, and each subregion being programmable to perform any of a plurality of logic functions on its input to produce its output.
The device defined in claim 5 wherein, for each of a multiplicity of subpluralities of said subregions in each of said super-regions, said interconnection circuitry further comprises:
The device defined in claim 6 wherein said interconnection circuitry further comprises:
The device defined in claim 6 wherein, for each of the subpluralities, said interconnection circuitry further comprises:
The device defined in claim 9 wherein said interconnection circuitry further comprises:
The device defined in claim 3 wherein, for each of the super-regions, the interconnection circuitry further comprises:
The device defined in claim 1 wherein each of the memory regions is programmably configurable to provide output signals in parallel on a plurality of different numbers of its outputs.
The device defined in claim 1 wherein each of the memory regions is programmably configurable to operate in a selected one of a random access memory mode and a product-term mode.
The device defined in claim 2 wherein, for each of the super-regions, the interconnection circuitry further comprises:
A printed circuit board on which is mounted a programmable logic device as defined in claim 1.
The printed circuit board defined in claim 19 further comprising:
EP1005163A2 true EP1005163A2 (en) 2000-05-31
EP1005163B1 EP1005163B1 (en) 2006-10-11
EP3345108A4 (en) * 2015-09-01 2019-05-08 Flex Logix Technologies, Inc. Block memory layout and architecture for programmable logic ic, and method of operating same
BURSKY D: "Variable-Grain Architecture Pumps UP FPGA Performance" ELECTRONIC DESIGN, PENTON PUBLISHING, CLEVELAND, OH, US, vol. 46, no. 4, 23 February 1998 (1998-02-23), page 102,104,106 XP002165019 ISSN: 0013-4872 *