Source: https://patents.google.com/patent/US20140063903A1/en
Timestamp: 2019-12-06 22:41:04
Document Index: 504052602

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US20140063903A1 - Resistive random access memory, controlling method and manufacturing method therefor - Google Patents
Resistive random access memory, controlling method and manufacturing method therefor Download PDF
US20140063903A1
US20140063903A1 US13/690,250 US201213690250A US2014063903A1 US 20140063903 A1 US20140063903 A1 US 20140063903A1 US 201213690250 A US201213690250 A US 201213690250A US 2014063903 A1 US2014063903 A1 US 2014063903A1
US13/690,250
US9159916B2 (en
2012-09-04 Priority to TW101132176 priority Critical
2012-09-04 Priority to TW101132176A priority patent/TWI489461B/en
2012-09-04 Priority to TW101132176A priority
2012-11-30 Application filed by Industrial Technology Research Institute filed Critical Industrial Technology Research Institute
2012-12-03 Assigned to INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE reassignment INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, KUAN-CHANG, CHANG, TING-CHANG, CHEN, MIN-CHEN, Jian, Fu-Yen, SYU, YONG-EN
2014-03-06 Publication of US20140063903A1 publication Critical patent/US20140063903A1/en
2015-10-13 Publication of US9159916B2 publication Critical patent/US9159916B2/en
A resistive random access memory (RRAM), a controlling method for the RRAM, and a manufacturing method therefor are provided. The RRAM includes a first electrode layer; a resistance switching layer disposed on the first electrode layer; a diffusion metal layer disposed on the resistance switching layer; and a second electrode layer disposed on the diffusion metal layer, wherein at least one extension electrode is disposed in the resistance switching layer.
This application is based on, and claims the priority benefit of Taiwan Application serial No. 101132176, filed on Sep. 4, 2012, the disclosure of which is hereby incorporated by reference herein in its entirety.
The disclosure relates to a resistive random access memory (RRAM), a controlling method and a manufacturing method therefor.
Memories are generally classified into volatile memories and non-volatile memories, and RRAM is one of the non-volatile memories which can be driven by electric current or voltage and can switch between the high impedance state and the low impedance state so as to store data. In the structure of RRAM, it is composed of a stacked layer of metal-insulator-metal, and the insulator may have reversible switching characteristics. During operations, a pulse voltage is applied to the RRAM to switch its resistance states to perform “data writing” or “data erasing”, and then a small bias is used for capturing current values to determine the impedance state in order to read data.
FIG. 1 is a conventional RRAM 6, which includes two electrode layers 61 spaced apart with each other and made of platinum (Pt) and titanium nitride (TiN), respectively, and a resistance switching layer 62 interposed between the two electrode layers 61 and made of nitroxide silicon oxynitrid (SiON). Then, an endurance experiment is performed on the conventional RRAM 6. That is, an alternate current is applied to the RRAM 6, such that the resistances of the RRAM 6 are continuously switched, and current values in the experiment are recorded and plotted during each switching as shown in FIG. 2. The formation or breaking of a conduction path is occurred in the resistance switching layer 62 during the switching between the high impedance state and the low impedance state; however, because each formation of the conduction path is not fixed, an irregular resistance transition may be occurred. That is, as shown in FIG. 2, the deviations of the solid dots are more obvious, which affects the stability of the RRAM 6.
A resistive random access memory (RRAM) structure according to the disclosure comprises a first electrode layer, a resistance switching layer disposed on the first electrode layer, a diffusion metal layer disposed on the resistance switching layer, and a second electrode layer disposed on the diffusion metal layer, wherein at least one extension electrode is disposed in the resistance switching layer.
Moreover, the RRAM structure further includes a switching base part disposed on the first electrode layer, and a porous part disposed between the switching base part and the diffusion metal layer, wherein the porous part is made of a porous material, when an electric field is applied to the diffusion metal layer, the diffusion metal layer diffuses into the porous part so as to form one or more extension electrodes.
A controlling method for the resistive random access memory according to the disclosure comprises: applying a forming voltage between the first electrode layer and the second electrode layer, such that the diffusion metal in the diffusion metal layer is led by the forming voltage and diffuses into the resistance switching layer to form a plurality of extension electrodes; and applying an operation voltage between the first electrode layer and the second electrode layer such that the resistance switching layer is driven by the operation voltage to change a resistance value.
A manufacturing method of the resistive random access memory according to the disclosure comprises: providing a first electrode layer; forming a resistance switching layer on the first electrode layer; forming a diffusion metal layer on the resistance switching layer; forming a second electrode layer on the diffusion metal layer; and forming at least one extension electrode in the resistance switching layer.
The extension electrode forms a fixed conduction path in the resistance switching layer; therefore, a fixed and regular conduction path may be formed or broken while the resistance switching layer switches between the high impedance state and the low impedance state. In addition, metals have a better diffusion character for porous materials, such that the porous part may contribute the formation of the extension electrode.
FIG. 1 is a side view illustrating a conventional resistive random access memory (RRAM) structure;
FIG. 2 is an endurance experimental data chart of a conventional RRAM illustrating a relationship between the resistance switching numbers and currents corresponding to the high impedance state and the low impedance state.
FIG. 3 is a side view of illustrating a RRAM structure according to a first embodiment of the disclosure.
FIG. 4 is a flow chart illustrating a manufacturing method according the first embodiment of the disclosure.
FIG. 5 is a flow chart illustrating a controlling method according to the first embodiment of the disclosure.
FIG. 6 is an endurance experimental data chart of a RRAM illustrating a relationship between the resistance switching numbers and currents corresponding to the high impedance state and the low impedance state according to the first embodiment of the disclosure.
FIG. 7 is an operation character chart showing a relationship between the conduction currents and the applied voltages.
FIG. 8 is a side view of illustrating a RRAM structure according to a second embodiment of the disclosure.
Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings in such a manner that the technical idea of the disclosure may easily be carried out by a person with ordinary skill in the art to which the disclosure pertains. The disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein.
Referring to FIGS. 3, 5 and 6, the resistive random access memory (RRAM) structure 10 according to a first embodiment of the disclosure comprises: a first electrode layer 2 made of a conductive material, a resistance switching layer 3 disposed on the first electrode layer 2, a diffusion metal layer 4 disposed on the resistance switching layer 3, and a second electrode layer 5 made of a conductive material and disposed on the diffusion metal layer 4.
The RRAM structure 10 is a sandwich layered structure, and the resistance switching layer 3 and the diffusion metal layer 4 are disposed between the first electrode layer 2 and the second electrode layer 5. In an embodiment, the first electrode layer 2 may be made of TiN, and the second electrode layer 5 may be made of Pt according to the first embodiment of the disclosure.
The resistance switching layer 3 may be driven by voltage or current, and may switch between the high impedance state and the low impedance state. In an embodiment, in the structure, the resistance switching layer 3 has a layer-type switching base part 31 on the first electrode layer 2, and a layer-type porous part 32 on the switching base part 31. In the embodiment of the disclosure, the switching base part 31 is made of SiON, and the porous part 32 is made of a porous material. Moreover, the porous part 32 may be any insulators which use a powder metallurgy method, a penetrating casting method, a spray deposition method, a foam molding method or an eutectic unidirectional solidification method to generate a porous state. In addition, the thickness of the switching base part 31 may be in a range between 2 nm and 10 nm, and the thickness of the porous part 32 may be in a range between 2 nm and 10 um.
The porous part 32 is disposed between the diffusion metal layer 4 and the switching base part 31, wherein the diffusion metal layer 4 may be made of a cooper (Cu) material with diffusion characters, which can be drawn by an electric field; therefore, the diffusion metal layer can diffuse into the porous part 32 to form one or more extension electrodes 33 in the porous part 32.
The manufacturing method of the RRAM is illustrated in FIG. 4. Please refer to FIGS. 3, 5 and 6 together for better understanding. The method comprises: forming the switching base part 31 on the first electrode layer 2; forming the porous part 32 on the switching base part 31; forming the diffusion metal layer 4 on the porous part 32 of the resistance switching layer 3; and forming the second electrode layer 5 on the diffusion metal layer 4. After an electric field is applied to the diffusion metal layer 4, the diffusion metal layer 4 diffuses into the porous part 32 to form the extension electrodes 33 in the porous part 32.
Please refer to FIGS. 3, 5 and 7, the control method of the RRAM comprises: applying a forming voltage between the first electrode layer 2 and the second electrode layer 5, such that the diffusion metal in the diffusion metal layer 4 is led by the forming voltage and diffuses into the porous part 32 to form the extension electrodes 33 in the porous part 32; applying an operation voltage between the first electrode layer 2 and the second electrode layer 5, such that the switching base part 31 is driven by the operation voltage to change resistance values. The differences of the resistance values are used for operating the stored data. In an embodiment, the operation voltage is a pulse voltage. When the operation voltage is beyond a predetermined range, that is, the resistance level of the switching base part 31 is changed so as to “data writing” or “data erasing”. In the embodiment of the disclosure, the voltage for “data writing” is −1 voltage, and the voltage for “data erasing” is −1.3 voltage.
The extension electrodes 33 are formed by diffusion, and the concentration of the diffusion is gradually decreased as the diffusion path elongates. Therefore, the width of the extension electrode 33 is gradually reduced, such that the extension electrode 33 may look like a cone shape.
The extension electrode 33 forms a conduction path in the porous part 32; that is, most of electric currents pass through the extension electrodes 33 by the porous part 32 and then conduct to the switching base part 31; therefore, during the switching between the high impedance state and the low impedance state, a conduction path can be formed or broken. Moreover, the extension electrodes 33 may have a point effect due to the cone shape to concentrate the electric field so as to increase the efficiency of resistance transition.
Please refer to FIGS. 3 and 6, FIG. 6 is an endurance experiment for the RRAM structure 10 according to the embodiment of the disclosure. In the FIG. 6, it shows a result of continuously performing about 105 of the resistance switching. The conduct current values form two groups clearly in the figure, and the current values are located on the predetermined range, respectively. The high impedance state and the low impedance state can be clearly and indeed switched, so as to have a better stability of switching characters.
Metals have better a diffusion character for porous materials, that is, the porous part 32 may contribute to form the extension electrode 33, such that the energy consumption and manufacturing time can be reduced in order to increase efficiencies. In addition, the porous size of porous part 32 may affect the end width of the extension electrode 33; that is, the tip portion of the extension electrode 33. If the porous size is small, the tip portion of the extension electrode 33 is narrow. In one embodiment, the size of porous is in a range between 1 nm2 and 10 nm2. In addition, if the porous density of the porous part 32 is too high, the porous part 32 may not be able to support the structure, causing the extension electrode 33 unable to have selectivity. However, if the porous density of the porous part 32 is too low, the power consumption for forming the extension electrode 33 become higher; therefore, the porous density of the porous part 32 is in a range between 1% and 10%.
On the other hand, the switching base part 31 is used to generate a resistance transition character, such that it may be another materials having resistance transition characters, such as semiconductor oxide, semiconductor nitride, semiconductor oxynitride, metal oxide, metal nitride, or metal oxynitride and so on, and is not limited to silicon oxynitride (SiON) of the embodiment of the disclosure.
The diffusion metal layer 4 is used for generating a diffusion effect to form the extension electrode 33 and conduct with the second electrode layer 5. Therefore, the diffusion metal layer 4 may be made of silver (Ag) or tin (Sn) with conductive and diffusion characters, but is not limited to the cooper (Cu) material of the embodiment of the disclosure.
Please refer to FIG. 8, the function and structure of the RRAM structure 10 according to a second embodiment are similar to that of the first embodiment, and they are all include a first electrode layer 2, a resistance switching layer 3 disposed on the first electrode layer 2, a diffusion metal layer 4 disposed on the resistance switching layer 3, and a second electrode layer 5 disposed on the diffusion metal layer 4.
The differences with the first embodiment lie in that: the resistance switching layer 3 according to the present embodiment is made of SiON; that is, the resistance switching layer 3 is a film formed from a single material, and the diffusion metal layer 4 diffuses into the resistance switching layer 3 to from the extension electrode 33.
Since the diffusion metal layer 4 may also diffuse into the SiON material, generate the extension electrode 33, and form or break a conduction path while switching the resistances switching, the extension electrode 33 may also form on the materials with resistance transition characters such as SiON, which may contribute the stability of resistance switching.
Although the disclosure is disclosed above with reference to the above embodiments, the embodiments are not intended to limit the disclosure. Equivalent replacements of variations and modifications made by any person skilled in the art without departing from the spirit and scope of the disclosure still fall with the protection scope of the disclosure.
1. A resistive random access memory (RRAM) structure, including:
a resistance switching layer disposed on the first electrode layer, and at least one extension electrode is disposed in the resistance switching layer;
a diffusion metal layer disposed on the resistance switching layer; and
a second electrode layer disposed on the diffusion metal layer.
2. The RRAM structure of claim 1, wherein the resistance switching layer further includes a switching base part disposed on the first electrode layer, and a porous part disposed between the switching base part and the diffusion metal layer, wherein the porous part is made of a porous material, when an electric field is applied to the diffusion metal layer, the diffusion metal layer diffuses into the porous part to form one or more extension electrodes in the porous part.
3. The RRAM structure of claim 2, wherein a porous density of the porous part is in a range between 1% and 10%.
4. The RRAM structure of claim 2, wherein a porous size of the porous part is in a range between 1 nm2 and 10 nm2.
5. The RRAM structure of claim 2, wherein a width of the extension electrode is gradually decreased toward the switching base part.
6. The RRAM structure of claim 2, wherein a thickness of the switching base part is in a range between 2 nm and 10 nm.
7. The RRAM structure of claim 2, wherein a thickness of the porous part is in a range between 2 nm and 10 um.
8. The RRAM structure of claim 2, wherein the diffusion metal layer is made of one of copper (Cu), tin (Sn), and silver (Ag).
9. The RRAM structure of claim 2, wherein the switching base part is made of one of semiconductor oxide, semiconductor nitride, semiconductor oxynitride, metal oxide, metal nitride, and metal oxynitride.
10. A controlling method for a resistive random access memory including a first electrode layer, a resistive switching layer disposed on the first electrode layer, a diffusion metal layer disposed on the resistive switching layer, and a second electrode layer disposed on the diffusion metal layer, the control method comprising:
applying a forming voltage between the first electrode layer and the second electrode layer, such that diffusion metal in the diffusion metal layer is led by the forming voltage and diffuses into the resistance switching layer to form a plurality of extension electrodes; and
applying an operation voltage between the first electrode layer and the second electrode layer such that the resistance switching layer is driven by the operation voltage to change a resistance value.
11. A manufacturing method of a resistive random access memory, comprising:
forming a resistance switching layer on the first electrode layer;
forming a diffusion metal layer on the resistance switching layer;
forming a second electrode layer on the diffusion metal layer; and
forming at least one extension electrode in the resistance switching layer.
12. The manufacturing method of claim 11, wherein the step of forming the resistance switching layer comprises: forming a switching base part on the first electrode layer; and forming a porous part on the switching base part, wherein the porous part is made of a porous material, and in the step of forming the extension electrode, when an electric field is applied to the diffusion metal layer, the diffusion metal layer diffuses into the porous part to form one or more extension electrodes in the porous part.
13. The manufacturing method of claim 12, wherein a porous density of the porous part is in a range between 1% and 10%.
14. The manufacturing method of claim 12, wherein a porous size of the porous part is in a range between 1 nm2 and 10 nm2.
15. The manufacturing method of claim 12, wherein a thickness of the switching base part is in a range between 2 nm and 10 nm.
16. The manufacturing method of claim 12, wherein a thickness of the porous part is in a range between 2 nm and 10 um.
17. The manufacturing method of claim 12, wherein the diffusion layer is made of one of copper (Cu), tin (Sn), and silver (Ag).
18. The manufacturing method of claim 12, wherein the switching base part is made of semiconductor oxide, semiconductor nitride, semiconductor oxynitride, metal oxide, metal nitride, and metal oxynitride.
US13/690,250 2012-09-04 2012-11-30 Resistive random access memory, controlling method and manufacturing method therefor Active 2033-08-02 US9159916B2 (en)
TW101132176 2012-09-04
TW101132176A TWI489461B (en) 2012-09-04 2012-09-04 Resistive ram, controlling method and manufacturing method
TW101132176A 2012-09-04
US20140063903A1 true US20140063903A1 (en) 2014-03-06
US9159916B2 US9159916B2 (en) 2015-10-13
ID=50187389
US13/690,250 Active 2033-08-02 US9159916B2 (en) 2012-09-04 2012-11-30 Resistive random access memory, controlling method and manufacturing method therefor
US (1) US9159916B2 (en)
CN (1) CN103682091B (en)
TW (1) TWI489461B (en)
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, TING-CHANG;CHEN, MIN-CHEN;SYU, YONG-EN;AND OTHERS;REEL/FRAME:029392/0953