Source: http://www.google.com/patents/US8106424?dq=6016038
Timestamp: 2016-05-01 04:38:38
Document Index: 360489894

Matched Legal Cases: ['application No. 103', 'application No. 103', 'application No. 103', 'application No. 103', 'application No. 103', 'Application No. 2006']

Patent US8106424 - Field effect transistor with a heterostructure - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer...http://www.google.com/patents/US8106424?utm_source=gb-gplus-sharePatent US8106424 - Field effect transistor with a heterostructureAdvanced Patent SearchPublication numberUS8106424 B2Publication typeGrantApplication numberUS 12/860,075Publication dateJan 31, 2012Priority dateDec 23, 2003Fee statusPaidAlso published asDE10360874A1, DE10360874B4, DE502004011345D1, EP1697998A1, EP1697998B1, US7491612, US7804110, US20070013002, US20090121289, US20110031530, WO2005064686A1Publication number12860075, 860075, US 8106424 B2, US 8106424B2, US-B2-8106424, US8106424 B2, US8106424B2InventorsKlaus SchrueferOriginal AssigneeInfineon Technologies AgExport CitationBiBTeX, EndNote, RefManPatent Citations (21), Non-Patent Citations (12), Referenced by (77), Classifications (19), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetField effect transistor with a heterostructure
US 8106424 B2Abstract
A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.
This application is a divisional application of U.S. patent application Ser. No. 12/353,053, filed Jan. 13, 2009, which is a divisional application of U.S. patent application Ser. No. 11/473,430, filed Jun. 23, 2006, which is a continuation of International Application Serial No. PCT/EP2004/053132, filed Nov. 26, 2004, and claims the benefit of priority of German Patent Application No. DE 10360874.5, filed Dec. 23, 2003, all of which are incorporated by reference herein.
The invention is described by way of example below on the basis of a field effect transistor with a heterostructure, Si being used as the first semiconductor material, Ge being used as the second semiconductor material and GexSi1-x being used as the semiconductor alloy. However, it is not restricted thereto and encompasses field effect transistors having alternative semiconductor materials in the same way.
The terms relaxed and strained semiconductor layer that are used repeatedly hereinafter relate in this case to monocrystalline semiconductor layers which are relaxed or strained on account of external boundary conditions,—as a result of which their electrical properties are altered.
FIGS. 2A and 2B respectively show a simplified illustration for illustrating a schematic band edge profile of the layer structure illustrated in FIG. 1 in the case of a flat band voltage, that is to say upon application of a voltage at which the valence and conduction bands exhibit a flat profile, and—in accordance with FIG. 2B—in the case of inversion, that is to say application of a voltage Vg at the gate layer 6, for a p MOS field effect transistor. In this case, f indicates the Fermi level of the semiconductor, while fm shows the Fermi level of the metallic gate layer 6, which corresponds to the conduction band edge in the case of metals. EG respectively designates the bandgap, which essentially defines an energy required for “raising” an electron from the valence band into the conduction band. Furthermore, ΔEc and ΔEV represent the respective band edge discontinuities for the conduction band and the valence band which in each case result at the transition between the relaxed silicon 3 and the strained GexSi1-x semiconductor alloy.
FIG. 4 shows a simplified illustration for illustrating the different possibilities for crystal growth and in particular for realizing a relaxed semiconductor layer on a relaxed starting material or a strained semiconductor layer on a relaxed starting material. Accordingly, the semiconductor alloy GexSi1-x has a larger crystal structure or lattice constant than the semiconductor material Si. If these layers are then joined together, the crystal structures illustrated on the right-hand side may arise, and, either on account of dislocations and surface defects at the boundary layer, a relaxed GexSi1-x layer is formed on a relaxed Si layer or, in the case illustrated underneath, no dislocations of this type are present at the boundary layer and, consequently, the different lattice constants of the crystals are adapted to one another with the occurrence of mechanical strains or stress. In the case illustrated, this results in a strained GexSi1-x semiconductor alloy formed on a relaxed Si layer. More detailed information on such semiconductor heterostructures can be found in particular in the literature reference John C. Bean: “Silicon-Based Semiconductor Heterostructures: Col. IV Bandgap Engineering”, Proceedings of IEEE, Vol. 80, No. 4, April 1992.
Since the selection of such suitable gate layers or “mid gap” metals for the gate electrode is very difficult and often yields only inadequate results, it is possible, in accordance with a second exemplary embodiment, to use an additional relaxed GeySi1-y layer and an additional strained Si layer situated between the relaxed Si and the strained GexSi1-x semiconductor alloy. Symmetrical threshold voltages can thereby also be set using only a single common gate electrode or gate layer and a corresponding composition of the Ge proportions x and y in the semiconductor heterostructure.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5534713May 20, 1994Jul 9, 1996International Business Machines CorporationComplementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layersUS6015981Apr 27, 1998Jan 18, 2000Daimler-Benz AktiengesellschaftHeterostructure field-effect transistors (HFETs') with high modulation effectivityUS6059895May 13, 1999May 9, 2000International Business Machines CorporationStrained Si/SiGe layers on insulatorUS6121661 *Mar 21, 1997Sep 19, 2000International Business Machines CorporationSilicon-on-insulator structure for electrostatic discharge protection and improved heat dissipationUS6350993Mar 12, 1999Feb 26, 2002International Business Machines CorporationHigh speed composite p-channel Si/SiGe heterostructure for field effect devicesUS6682965 *Mar 26, 1998Jan 27, 2004Sony CorporationMethod of forming n-and p- channel field effect transistors on the same silicon layer having a strain effectUS6815738Feb 28, 2003Nov 9, 2004International Business Machines CorporationMultiple gate MOSFET structure with strained Si Fin bodyUS6825507 *Jan 21, 2003Nov 30, 2004Renesas Technology Corp.Semiconductor device having high electron mobility comprising a SiGe/Si/SiGe substrateUS6992319Jun 24, 2002Jan 31, 2006Epitaxial TechnologiesUltra-linear multi-channel field effect transistorUS7001826 *Sep 17, 2003Feb 21, 2006S.O.I.Tec Silicon On Insulator Technologies S.A.Wafer with a relaxed useful layer and method of forming the waferUS20020179946Apr 18, 2001Dec 5, 2002Yoshiro HaraP-channel field-effect transistorUS20030162335Mar 4, 2003Aug 28, 2003Matsushita Electric Industrial Co., Ltd.Semiconductor device and method for fabricating the sameUS20030201497Feb 24, 2003Oct 30, 2003Matsushita Electric Industrial Co., Ltd.Semiconductor device and method for fabricating the sameUS20030227057 *Oct 4, 2002Dec 11, 2003Lochtefeld Anthony J.Strained-semiconductor-on-insulator device structuresUS20040142541Dec 19, 2002Jul 22, 2004Cohen Guy MosheStrained silicon-on-insulator (ssoi) and method to form the sameEP1298712A2Sep 30, 2002Apr 2, 2003Texas Instruments IncorporatedGate structure and method of forming the sameJP2002280568A Title not availableJP2004266064A Title not availableJPH0982944A Title not availableJPH07321222A Title not availableJPH10308503A Title not available* Cited by examinerNon-Patent CitationsReference1Bean, John C., "Silicon-Based Semiconductor Heterostructures: Column IV Bandgap Engineering," Proceedings of the IEEE, vol. 80, No. 4, Apr. 1992, pp. New York, pp. 571-587.2German Office Action (in the German language) dated Aug. 5, 2008, for corresponding German patent application No. 103 60 874.5.3German Office Action (in the German language) dated Jun. 14, 2007, for corresponding German patent application No. 103 60 874.5.4German Office Action (in the German language) dated Sep. 16, 2004, for corresponding German patent application No. 103 60 874.5.5International Preliminary Examination Report (in the German language) for corresponding German patent application No. 103 60 874.5 dated Jul. 15, 2005.6International Search Report (in the German language) dated Feb. 11, 2005, for corresponding German patent application No. 103 60 874.5.7Japanese Patent Application No. 2006-546144 Office Action dated Mar. 18, 2008 in English translation.8Loo et al., "Fabrication of 50 nm high performance strained-SiGe pMOSFETs with selective epitaxial growth," (available online at www.sciencedirect.com), Applied Surface Science 224, (2004) pp. 292-296.9Shima et al., " Channel Strained-SiGe p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance," 2002 Symposium on VLSI Technology Digest of Technical Papers, pp. 94-95.10Shima et al., "<100> Channel Strained-SiGe p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance," 2002 Symposium on VLSI Technology Digest of Technical Papers, pp. 94-95.11Takagi et al., "A Novel High Performance SiGe Channel Heterostructure Dynamic Threshold Pmosfet (HDTMOS)," IEEE Electron Device Letters, vol. 22, No. 5, May 2001, pp. 206-208.12Yeo et al., "Enhanced Performance in Sub-100 mn CMOSFETs Using Strained Epitaxial Silicon-Germanium," paper, Department of Electrical Engineering and Computer Sciences, University of California, Berkley, CA, IEDM 00-753-756-IEDM 00, pp. 32.5.1-32.5.4.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8273617Feb 18, 2010Sep 25, 2012Suvolta, Inc.Electronic devices and systems, and methods for making and using the sameUS8377783Feb 19, 2013Suvolta, Inc.Method for reducing punch-through in a transistor deviceUS8400219Mar 24, 2011Mar 19, 2013Suvolta, Inc.Analog circuits having improved transistors, and methods thereforUS8404551Dec 3, 2010Mar 26, 2013Suvolta, Inc.Source/drain extension control for advanced transistorsUS8421162Apr 16, 2013Suvolta, Inc.Advanced transistors with punch through suppressionUS8461875Feb 18, 2011Jun 11, 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257/190, 257/191, 257/E29.056International ClassificationH01L31/072, H01L29/786, H01L29/80Cooperative ClassificationH01L29/802, Y10S438/936, H01L29/78684, Y10S438/933, H01L29/78687European ClassificationH01L29/786G2, H01L29/80B, H01L29/786GLegal EventsDateCodeEventDescriptionJul 23, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services