Source: http://patents.com/us-7908507.html
Timestamp: 2019-05-25 13:31:26
Document Index: 542664953

Matched Legal Cases: ['Application No. 2007', 'Application No. 2006', 'art.\n5', 'art.\n11', 'art.\n17', 'art 10', 'art 10', 'art 20', 'art 17', 'art 18', 'art 18', 'art 19', 'art 90', 'art 90', 'art 10', 'art 40', 'art 15', 'art 40', 'art 90', 'art 15', 'art 40', 'art 30', 'art 35', 'arts 10', 'art 90', 'art 15', 'art 20', 'art 20', 'art 17', 'art 18', 'art 15']

US Patent # 7,908,507. Apparatus and method for masking input of invalid data strobe signal - Patents.com
United States Patent 7,908,507
Ogura March 15, 2011
Apparatus and method for masking input of invalid data strobe signal
Inventors: Ogura; Kiyonori (Kasugai, JP)
Appl. No.: 11/896,670
11445144 Jun., 2006
Feb 28, 2006 [JP] 2006-052909
Feb 27, 2007 [JP] 2007-048022
Current U.S. Class: 713/500 ; 365/189.15; 365/193; 365/195; 365/196; 713/401; 713/502; 713/503
6621760 September 2003 Ahmad et al.
6680866 January 2004 Kajimoto
6785189 August 2004 Jacobs et al.
6853594 February 2005 Wu et al.
7038953 May 2006 Aoki
7177230 February 2007 Huang
7619404 November 2009 LaBerge
2005/0152209 July 2005 Shin et al.
2003-085974 Mar., 2003 JP
This application is a continuation-in-part of the U.S. patent application Ser. No. 11/445,144, filed Jun. 2, 2006, [now abandoned] and claims the benefit of priority from Japanese Patent Application No. 2007-048022 filed on Feb. 27, 2007 and Japanese Patent Application No. 2006-052909 filed on Feb. 28, 2006. The entire contents of these applications are incorporated herein by reference.
1. A data fetch circuit that masks an input of an invalid data strobe signal when it fetches a data signal synchronously with a data strobe signal with the data signal in accordance with a read instruction signal comprising: a response time measuring part measuring a response time from the input of the read instruction signal to a valid edge of the data strobe signal; and a standby part giving an instruction of a cancel of the mask of the data strobe signal after standing by for a standby time based on the response time in accordance with a standby start signal based on the read instruction signal, wherein the data strobe signal outputs the valid edge which makes a transition from a high impedance to a first logic level in accordance with the read instruction signal; and the response time measuring part comprises: a transition detecting part detecting the transition of the data strobe signal from the high impedance to the first logic level; and a measuring part measuring the response time from the input of the read instruction signal to an output of a detection result of the transition detecting part, and wherein the transition detecting part comprises: a first comparator in which the data strobe signal is inputted to an inversion input terminal and a first threshold voltage detecting the first logic level is inputted to a non-inversion input terminal; a second comparator in which an inversion data strobe signal complementary to the data strobe signal is inputted to a non-inversion input terminal and a second threshold voltage detecting the second logic level is inputted to an inversion input terminal; and a gate circuit that calculate an AND operation of outputs of the first and second comparators.
2. The data fetch circuit according to claim 1, wherein the response time measuring part makes measurement of the response time valid in accordance with a measurement instruction signal.
3. The data fetch circuit according to claim 1, wherein the response time measuring part comprises: a first counter part starting counting clock signals in accordance with the input of the read instruction signal; and a first holding part holding an output of the first counter part in accordance with the valid edge of the data strobe signal.
4. The data fetch circuit according to claim 3 further comprising a standby adjusting part adjusting to make the standby time delay by one cycle of the clock signal with reference to time which depends on holding contents of the first holding part.
5. The data fetch circuit according to claim 4, wherein the standby adjusting part includes a shifter which shifts the holding contents of the first holding part leftward.
6. The data fetch circuit according to claim 4, wherein the standby adjusting part includes a flip-flop which delays the read instruction signal by one cycle of the clock signal.
7. The data fetch circuit according to claim 3, wherein the first counter part includes a shift register to which the read instruction signal is inputted as a data input and the clock signal is inputted as a clock input.
8. The data fetch circuit according to claim 1, wherein the standby part includes a delay line to which the standby start signal is inputted and the response time measuring part includes a selecting part which selects an output tap of the delay line depending on the response time.
9. The data fetch circuit according to claim 8, wherein the selecting part sequentially switches an output tap of the delay line or an output tap of a delay line structurally same as the delay line and detects logic level of the data strobe signal within a time in which the read instruction signal to be inputted to the delay line is outputted with delay.
10. The data fetch circuit according to claim 8, wherein the selecting part includes: a delay line signal holding part which holds a signal of an output tap of the delay line to which the read instruction signal is inputted or a signal of an output tap of a delay line structurally same as the delay line depending on a valid edge of the data strobe signal of each output tap of the delay line; and a detecting part which specifies input timing of the read instruction signal from a signal held in the delay line signal holding part.
11. The data fetch circuit according to claim 9, wherein the read instruction signal is inputted to the delay line provided in the standby part during a measurement of the response time.
12. The data fetch circuit according to claim 10, wherein the read instruction signal is inputted to the delay line provided in the standby part during a measurement of the response time.
13. The data fetch circuit according to claim 1, wherein the response time measuring part includes: a first measuring part measuring a first time in the response time; and a second measuring part measuring a second time corresponding to rest of the response time from which the first time is excluded, and the standby start signal is outputted from the first measuring part and stands by at the standby part for time according to the second time.
14. The data fetch circuit according to claim 13, wherein the first time is a fixed time in the response time and the second time is a variable time in the response time.
15. The data fetch circuit according to claim 13, the first measuring part includes: a second counter part which starts counting a clock signal in response to an input of the read instruction signal; and a second holding part which holds an output of the second counter part depending on the valid edge of the data strobe signal.
16. The data fetch circuit according to claim 1 further comprising a delay adjusting part which variably delays at least one of the following items: measuring timing of the response time meaning part and a measuring result of the standby part.
17. The data fetch circuit according to claim 16 wherein, in case measurement by at least the response time measuring part and the standby part is carried out in accordance with a clock signal, delay of measuring timing by the delay adjusting part is due to delay of a clock signal.
18. A data fetch system comprising: a memory device which outputs a data signal synchronously with a data strobe signal; and a memory control device which masks an input of an invalid data strobe signal when fetching the data signal synchronously with the data strobe signal, wherein the memory control device includes: a response time measuring part measuring a response time from the input of the read instruction signal to a valid edge of the data strobe signal; and a standby part giving an instruction of a cancel of the mask of the data strobe signal after standing by for a standby time based on the response time in accordance with a standby start signal based on the read instruction signal, wherein the data strobe signal outputs the valid edge which makes a transition from a high impedance to a first logic level in accordance with the read instruction signal; and the response time measuring part comprises: a transition detecting part detecting the transition of the data strobe signal from the high impedance to the first logic level; and a measuring part measuring the response time from the input of the read instruction signal to an output of a detection result of the transition detecting part, and wherein the transition detecting part comprises: a first comparator in which the data strobe signal is inputted to an inversion input terminal and a first threshold voltage detecting the first logic level is inputted to a non-inversion input terminal; a second comparator in which an inversion data strobe signal complementary to the data strobe signal is inputted to a non-inversion input terminal and a second threshold voltage detecting the second logic level is inputted to an inversion input terminal; and a gate circuit that calculate an AND operation of outputs of the first and second comparators.
19. A control method of a data fetch circuit that masks an input of an invalid data strobe signal when it fetches a data signal synchronously with a data strobe signal with the data signal in accordance with a read instruction signal comprising: measuring a response time from the input of the read instruction signal to a valid edge of the data strobe signal; and giving an instruction of a cancel of the mask of the data strobe signal after standing by for a standby time based on the response time in accordance with a standby start signal based on the read instruction signal, wherein the data strobe signal outputs the valid edge which makes a transition from a high impedance to a first logic level in accordance with the read instruction signal; and the measuring the response time comprises: detecting the transition of the data strobe signal from the high impedance to the first logic level; and measuring the response time from the input of the read instruction signal to an output of a detection result of the detecting the transition, and wherein the detecting the transition comprises: (1) comparing that the data strobe signal being inputted as an inversion input and a first threshold voltage detecting the first logic level being inputted as a non-inversion input; (2) comparing that an inversion data strobe signal complementary to the data strobe signal being inputted as a non-inversion input and a second threshold voltage detecting the second logic level being inputted as an inversion input terminal; and (3) calculating an AND operation of outputs of the (1) comparing and the (2) comparing.
20. The control method of a data fetch circuit according to claim 19, wherein the measuring the response time further comprises making measurement of the response time valid in accordance with a measurement instruction signal.
21. The control method of a data fetch circuit according to claim 19, wherein the measuring the response time comprises: starting counting clock signals in accordance with the input of the read instruction signal; and holding a count result of the starting the counting clock signals in accordance with the valid edge of the data strobe signal.
22. The control method of a data fetch circuit according to claim 19, wherein the giving the instruction of a cancel of the mask comprises delaying a signal by a delay line in response to the read instruction signal, and the measuring the response time comprises selecting an output tap of the delay line in accordance with the response time.
23. The control method of a data fetch circuit according to claim 22, wherein the selecting the output tap of the delay line comprises switching sequentially an output tap of the delay line or an output tap a delay line structurally same as the delay line, and the sequentially switching sequentially the output tap of the delay line comprises detecting logic level of the data strobe signal within a time in which the read instruction signal to be inputted to the delay line is outputted with delay.
24. The control method of a data fetch circuit according to claim 22, wherein the selecting the output tap of the delay line comprises: holding a signal of an output tap of the delay line to which the read instruction signal is inputted or a signal of an output tap of a delay line structurally same as the delay line depending an on valid edge of the data strobe signal of each output tap of the delay line; and specifying input timing of the read instruction signal from a signal held at the holding the signal of an output tap of the delay line.
25. The control method of a data fetch circuit according to claim 19, wherein the measuring the response time comprises: measuring a first time in the response time; and measuring a second time corresponding to rest of the response time from which the first time is excluded, and the giving the instruction of the cancel of the mask stands by for a time according to the second time.
26. The control method of a data fetch circuit according to claim 25, wherein the first time is a fixed time in the response time and the second time is a variable time in the response time.
27. The control method of a data fetch circuit according to claim 25, wherein the measuring the first time comprises: starting to count a clock signal in response to an input of the read instruction signal; and holding a count result at the measuring the first time.
Here, the clock signal CK is a clock signal of the data fetch circuit 1A having a double frequency of that of the system clock signal SCK. A data read command signal CMD is a signal that a controller (C) (see FIG. 1) instructs the SDRAM (R) (see FIG. 1) to operate. That is, the data read command signal CMD is issued from the controller (C) to the SDRAM (R). In FIG. 5, "CMD (controller)" indicates an output from the controller (C) and "CMD (SDRAM)" indicates an input to the SDRAM(R). Additionally, "(COUNT VALUE IN 51)" indicates a count value of the inside of count comparator 51. The other symbols are symbols based on the signal names shown in FIG. 3 respectively.
Additionally, in FIG. 5, "FT(1)" and "FT(2) indicate a first flight time and second fight time, respectively, and "CL" indicates a CAS latency CL. In the present embodiment, both the flight time FT(1) and the flight time FT(2) are equal to 1.5 and the CAS latency CL is equal to 2.
The data read command signal CMD issued from the controller (C) reaches the SDRAM (R) at the first flight time FT(1). When it is assumed that a read preamble time (tRPRE) of the SDRAM (R) is one cycle of a system clock signal SCK, in the SDRAM (R), the number of clocks to be taken from a receipt of a data readout command signal CMD to a valid edge at which a data strobe signal DQS makes a transition from a high impedance to a low level is "1", a subtraction of "2", the value of the CAS latency, minus "1". Furthermore, the data strobe signal DQS which has made the transition to a low level in the SDRAM (R) reaches the controller (C) at the second flight time FT(2). That is, the latency RL is equal to 4.0 which is the number of clocks from the issuance of a data read command signal CMD of by the controller (C) (transition of the read instruction signal RD to a high level) to a valid edge TRL of the data strobe signal DQS. That is, a response time TRL from an input of the read instruction signal RD to the valid edge of the data strobe signal DQS is represented by a period of 4.0.times. the system clock signal SCK.
In (1) of FIG. 5, when "Read" is issued as the data read command signal CMD and the read instruction signal RD makes the transition to a high level, the RL measuring part 10 starts counting the latency count values RLA. Also in (2), the RL measuring part 10 starts counting the RL count values RLC after delay by a transition time of a delay part 20, that is, one cycle of the clock signal CK. Both the count values of the latency count value RLA and the RL count value RLC are counted by the shift register, thereby taking values shifted bit by bit from the least significant bit. That is, 01, 02, 04, 08, 10, 20, 40 and 80 is outputted in this order by an octal number in either count value.
At the measurement judging part 17, the code signal CODE1 is initialized in response to an input of the measurement instruction signal RLE (S1). After the initialized code signal CODE1 is transmitted to the delay line DL and a delay time of the delay line is initialized, the read instruction signal RD makes a transition to a high level. From the delay line DL, the delay signal RD1 makes a transition to a high level by a time of initialization. In accordance with the transition of the delay signal RD1, a logic level value of the internal data strobe signal EDQS is detected (S2). In case the logic level value of the internal data strobe signal EDQS is a low level (S2: NO), it is detected that data strobe signal DQS is still in a high impedance state. Incrementing the code signal CODE1 by "1" (S3), the processing goes on to (S2) to input a read instruction signal RD again. In case the logic level value of the internal data strobe signal EDQS is a high level (S2: YES), the code signal CODE1 is outputted while the value set for the code signal CODE1 is held (S4). At the same time, the measurement end signal END is outputted.
FIG. 11 is a specific example of the detecting part 18. In the specific example, the detecting part 18 comprises AND gates A0 through AN-1. Among output signals Q0 through QN to be inputted to respective AND gates A0 through AN-1, signals outputted from a descendant-stage delay unit are inversed and then inputted. Thereby, a low-level-to-high-level transition point due to input of a read instruction signal RD can be detected. Signals detected and outputted from the AND gates A0 through AN-1 are decoded at the decoding part 19 and a code signals CODE1 are outputted.
The CL measuring part 90 starts count operation of clock signal CK in response to a high level transition of the read instruction signal RD. The count operation is made in the number of times equal to the number that "1" is subtracted from the CAS latency CL. In this case, the read preamble time (tRPRE) is regarded as one cycle of a clock signal CK. For the data fetch system (FIG. 1), a CAS latency CL is a time in which a data read command signal CMD reaches the SDRAM (R) through a first flight time FT(1) and data is outputted from the SDRAM (R) due to data read operation started the SDRAM (R). The SERAM (R) allows the data strobe signal DQS to make a transition from a high impedance state to a low level state with a timing one cycle advancing to the CAS latency CL. After that, a low-level transition of the data strobe signal DQS goes through the controller (C) at a second flight time FT(2). Since the time for the data strobe signal DQS to make the low-level transition in response to the receipt of a data read command signal CMD by the SDRAM (R) is previously determined as a time that "1" is subtracted from the CAS latency CL, the CL measuring part 90 measures the above determined time.
Moreover, the RL measuring part 10 and the transition detecting part 40, the RL measuring part 15 and the transition detecting part 40, and the CL measuring part 90, the RL measuring part 15 and the transition detecting part 40 are examples of a response time measuring part. The RL count comparing part 30 and the RL count comparing part 35 are examples of the standby part, the read instruction signal RD, the delay read instruction signal RDD, and the CAS latency measurement value CLB are examples of the standby start signal, the RL measuring parts 10, 15, the CL measuring part 90 and the RL measuring part 15 are the examples of the measuring part, the delay part 20 or the shift part 20A is the example of the standby adjusting part. Additionally, the low level is an example of a first logic level, the high level is an example of a second logic level, the low level threshold voltage is an example of a first threshold voltage, and the high level threshold voltage is an example of a second threshold voltage. Additionally, the flip-flops 11A through 11H are the examples of the first counter part, the flip-flops 12A through 12H are the examples of the first holding part. Additionally, the measurement judging part 17, the flip-flops FF0 through FFN and the detecting part 18 are the examples of the selecting part. Additionally, the flip-flops FF0 through FFN are the examples of the delay line signal holding part. Additionally, the CL measuring part is the example of the first measuring part, and the RL measuring part 15 according to the fourth embodiment is the example of the second measuring part. Additionally, cycles of a clock signal CK equivalent to the number that "1" is subtracted from the CAS latency CL, namely, the time from data read operation at the SDRAM (R) to output of the data is the example of the first time, and the first flight time FT(1) and the second flight time FT(2) corresponding to the delay time for a signal to go between the controller (C) and the SDRAM (R) are the examples of the second time.
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