Source: https://patents.google.com/patent/US8906744B2/en
Timestamp: 2019-10-14 15:50:19
Document Index: 558738383

Matched Legal Cases: ['Application No. 200705422', 'Application No. 10', 'Application No. 200880024992', 'Application No. 097128170', 'Application No. 200880024992', 'Application No. 10', 'Application No. 2010', 'Application No. 2010', 'Application No. 200705422', 'Application No. 200705422']

US8906744B2 - Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods - Google Patents
US8906744B2
US8906744B2 US14/029,455 US201314029455A US8906744B2 US 8906744 B2 US8906744 B2 US 8906744B2 US 201314029455 A US201314029455 A US 201314029455A US 8906744 B2 US8906744 B2 US 8906744B2
US14/029,455
US20140015130A1 (en
2007-07-24 Priority to SG200705422 priority
2007-07-24 Priority to SG200705422-4 priority
2007-09-28 Priority to US11/863,425 priority patent/US7843050B2/en
2010-11-29 Priority to US12/955,666 priority patent/US8198720B2/en
2012-06-08 Priority to US13/492,554 priority patent/US8536702B2/en
2013-09-17 Priority to US14/029,455 priority patent/US8906744B2/en
2013-09-17 Application filed by Micron Technology Inc filed Critical Micron Technology Inc
2014-01-16 Publication of US20140015130A1 publication Critical patent/US20140015130A1/en
2014-12-09 Publication of US8906744B2 publication Critical patent/US8906744B2/en
239000011133 lead Substances 0 claims description 101
239000002184 metal Substances 0 abstract claims description title 70
229910052751 metals Inorganic materials 0 abstract claims description title 70
238000009736 wetting Methods 0 claims 4
This application is a divisional of U.S. application Ser. No. 13/492,554 filed Jun. 8, 2012, now U.S. Pat. No. 8,536,702, which is a divisional of U.S. application Ser. No. 12/955,666 filed Nov. 29, 2010, now U.S. Pat. No. 8,198,720, which is a continuation of U.S. application Ser. No. 11/863,425 filed Sep. 28, 2007, now U.S. Pat. No. 7,843,050, which claims foreign priority benefits of Singapore Application No. 200705422-4 filed Jul. 24, 2007, now Singapore Patent No. 149726, each of which is incorporated herein by reference in its entirety.
FIG. 11 is a cross-sectional side view showing an embodiment of a stacked system 400 that includes microelectronic die packages 82 a-d separated by dielectric spacer layers 84 a-d and having corresponding first metal leads 86 a-d and second metal leads 88 a-d respectively coupled together by first and second connectors 414 a-b. In this view, the spacer layer 84 a includes corresponding metal traces 90 a-b, the spacer layer 84 c include corresponding metal traces 91 a-b, the spacer layer 84 d includes a single metal trace 92, but the spacer layer 84 b does not have any corresponding metal traces along this view of the second package 82 b (i.e., the die packages 82 a-d may have a different arrangement of metal traces in other cross-sectional views such that the second package 82 b does not have metal traces along the illustrated cross-section). The first connector 414 a is applied across the first leads 86 a-d to selectively electrically couple first, third, and fourth packages 82 a, 82 c, and 82 d; and the second connector 414 b is applied across the second leads 88 a-d to selectively electrically couple the first and third packages 82 a and 82 c. Thus, one side of the die package 82 d and both sides of the die package 82 b are electrically isolated from the connectors 414 a-b. The process of stacking the die packages 82 a-d can be the same as the process described with reference to FIGS. 1 and 9. The process of forming the die packages 82 a-d can be similar to the method of manufacturing described with reference to FIGS. 2A-8B, but instead of connecting a metal trace to every metal lead, individual metal trace-lead couplings have been omitted.
stacking a first die package having a first dielectric casing and a first bottom side on a top side of a second die package having a second dielectric casing, wherein the first dielectric casing defines at least a portion of the first bottom side, and wherein the second dielectric casing defines at least a portion of the top side;
aligning first metal leads coupled to the first bottom side of the first die package with second metal leads coupled to a second bottom side of the second die package;
attaching the second die package to the first die package with an adhesive layer;
forming individual external inter-package connectors attached to a first portion of individual first leads and to a second portion of individual second leads that are spaced apart from a lateral side of the second casing and project towards the first package; and
coupling package bond pads of the second die package to metal bump pads associated with an interposer substrate.
2. The method of claim 1, further comprising compressing the second metal leads so that the second leads bend towards the lateral side of the second casing.
3. The method of claim 1 wherein forming the connectors comprises wetting metal solder to the first portion of the individual first leads and to the second portion of the individual second leads.
4. The method of claim 3, further comprising wetting the metal solder to interior and exterior surface portions of the individual second leads.
5. The method of claim 1 wherein the individual second leads comprise an L-shape, and wherein the second portion includes an angled portion of the individual second leads.
6. The method of claim 1 wherein the individual second leads comprise a C-shape, and wherein the second portion further includes a tier that projects towards the lateral side of the second casing.
7. A method of manufacturing microelectronic die packages, the method comprising:
forming a first die package by forming a first dielectric casing that at least partially encapsulates a first microelectronic die, wherein the first die package includes a first bottom side and a first lateral side, and wherein the first dielectric casing defines at least a portion of the first bottom side;
forming a second die package by forming a second dielectric casing that at least partially encapsulates a second microelectronic die, wherein the second die package includes a top side, a second bottom side and a second lateral side, and wherein the second dielectric casing defines at least a portion of the top side;
forming individual first metal contacts that have a first lateral portion and a first angled portion, the first lateral portion being coupled to the first bottom side of the first dielectric casing and projecting away from the first lateral side of the first dielectric casing, the first angled portion being spaced apart from the first lateral side of the first dielectric casing and extending away from the first lateral portion such that a first interior surface of the first angled portion faces the first lateral side of the first dielectric casing, and wherein the first angled portion is configured to wet to an external inter-package metal solder connector;
forming individual second metal contacts that have a second lateral portion and a second angled portion, the second lateral portion being coupled to the second bottom side of the second dielectric casing and projecting away from the second lateral side of the second dielectric casing, the second angled portion being spaced apart from the second lateral side of the second dielectric casing and extending away from the second lateral portion such that a second interior surface of the second angled portion faces the second lateral side of the second dielectric casing, and wherein the second angled portion is configured to wet to the external inter-package metal solder connector;
aligning the first metal contacts coupled to the first bottom side of the first die package with the second metal contacts coupled to the second bottom side of the second die package; and
attaching the top side to the first bottom side with an adhesive layer.
8. The method of claim 7, further comprising forming a dielectric spacer layer at the first or second bottom side of the first or second dielectric casing, wherein the dielectric spacer layer includes metal traces that electrically couple the first or second microelectronic die to the first or second metal contacts.
9. The method of claim 8 wherein the metal traces are selectively routed for coupling a portion of the first or second metal contacts to the first or second microelectronic die.
10. The method of claim 7 wherein forming the individual first or second metal contacts further comprises forming a tiered portion that extends from the angled portion inward towards the lateral side of the casing, wherein the tiered portion is configured to wet to the external inter-package metal solder connector.
11. The method of claim 7 wherein the first or second angled portions of the first or second metal contacts are juxtaposed to the first or second lateral side of the first or second dielectric casing.
12. A method of manufacturing a microelectronic device, the method comprising:
forming a first die package having a first dielectric casing and a first bottom side, wherein the first dielectric casing defines at least a portion of the first bottom side;
forming a first metal lead coupled to the first bottom side of the first die package;
forming a second die package having a second dielectric casing, a second bottom side and a top side, wherein the second dielectric casing defines at least a portion of the top side;
forming a second metal lead coupled to the second bottom side of the second die package;
stacking the first die package on the top side of the second die package;
aligning the first metal lead with the second metal lead;
directly attaching the second die package to the first die package with an adhesive layer;
forming an external inter-package connector attached to a first portion of the first lead and to a second portion of the second lead that is spaced apart from a lateral side of the second casing and projects towards the first package; and
coupling a package bond pad of the second die package to a metal bump pad associated with an interposer substrate.
13. The method of claim 12, further comprising compressing the second metal lead so that the second lead bends towards the lateral side of the second casing.
14. The method of claim 12 wherein forming the external inter-package connector comprises wetting metal solder to the first portion of the first lead and to the second portion of the second lead.
15. The method of claim 14, further comprising wetting the metal solder to interior and exterior surface portions of the second lead.
16. The method of claim 12 wherein the second lead comprises an L-shape, and wherein the second portion includes an angled portion.
17. The method of claim 12 further comprising forming a redistribution structure at the second bottom side of the second die package.
18. The method of claim 12 wherein the second portion is substantially perpendicular to the first portion.
US14/029,455 2007-07-24 2013-09-17 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods Active US8906744B2 (en)
SG200705422 2007-07-24
US16/038,621 US10396059B2 (en) 2007-07-24 2018-07-18 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US13/492,554 Division US8536702B2 (en) 2007-07-24 2012-06-08 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US14/564,502 Division US9165910B2 (en) 2007-07-24 2014-12-09 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US20140015130A1 US20140015130A1 (en) 2014-01-16
US8906744B2 true US8906744B2 (en) 2014-12-09
US11/863,425 Active 2028-06-30 US7843050B2 (en) 2007-07-24 2007-09-28 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US12/955,666 Active US8198720B2 (en) 2007-07-24 2010-11-29 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US13/492,554 Active US8536702B2 (en) 2007-07-24 2012-06-08 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US14/029,455 Active US8906744B2 (en) 2007-07-24 2013-09-17 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US14/564,502 Active US9165910B2 (en) 2007-07-24 2014-12-09 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US14/882,088 Active US9653444B2 (en) 2007-07-24 2015-10-13 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US15/474,854 Active US10056359B2 (en) 2007-07-24 2017-03-30 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US16/038,621 Active US10396059B2 (en) 2007-07-24 2018-07-18 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
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