Source: https://patents.google.com/patent/US8707062B2/en
Timestamp: 2019-04-23 21:24:26
Document Index: 129443367

Matched Legal Cases: ['Application No. 11', 'Application No. 200680050111', 'Application No. 200680050111', 'Application No. 2008', 'Application No. 10', 'Application No. 10', 'Application No. 200680050111', 'Application No. 200680050111', 'Application No. 200680050111', 'Application No. 95147692']

US8707062B2 - Method and apparatus for powered off processor core mode - Google Patents
Method and apparatus for powered off processor core mode Download PDF
US8707062B2
US8707062B2 US12/706,631 US70663110A US8707062B2 US 8707062 B2 US8707062 B2 US 8707062B2 US 70663110 A US70663110 A US 70663110A US 8707062 B2 US8707062 B2 US 8707062B2
US12/706,631
US20100146311A1 (en
2005-12-30 Priority to US11/323,254 priority Critical patent/US7664970B2/en
2010-02-16 Application filed by Intel Corp filed Critical Intel Corp
2010-02-16 Priority to US12/706,631 priority patent/US8707062B2/en
2010-06-10 Publication of US20100146311A1 publication Critical patent/US20100146311A1/en
2011-12-28 Priority claimed from US13/339,284 external-priority patent/US8799687B2/en
2014-04-22 Publication of US8707062B2 publication Critical patent/US8707062B2/en
For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.
a first processor core of the processor, the first processor core to save a state of the first processor core and to enter a mode in which the first processor core is powered off;
a second processor core of the processor, the second processor core to save a state of the second processor core and to enter a mode in which the second processor core is powered off; and
a cache memory of the processor, the cache memory to be powered when the first processor core is powered off,
the first processor core to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered, and
the second processor core to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered.
2. The processor of claim 1, wherein the first processor core is to save the state of the first processor core in the cache memory.
3. The processor of claim 1, wherein the first processor core is to enter the mode in which the first processor core is powered off in response to execution of an instruction by the first processor core.
4. The processor of claim 3, wherein the second processor core is to enter the mode in which the second processor core is powered off in response to execution of an instruction by the second processor core.
5. The processor of claim 1, wherein the first processor core is to restore the saved state of the first processor core when reset.
6. The processor of claim 5, wherein the second processor core is to restore the saved state of the second processor core when reset.
7. The processor of claim 1, wherein the first processor core is to transition to the mode in which the first processor core is powered in response to a signal from a power management controller.
8. The processor of claim 7, wherein the second processor core is to transition to the mode in which the second processor core is powered in response to a signal from the power management controller.
9. The processor of claim 1, wherein the first processor core is to save and restore registers of the first processor core.
10. The processor of claim 1, wherein the first processor core is to save and restore a debug state of the first processor core.
a first processor core of the processor, the first processor core to save a state of the first processor core and to enter a mode in which the first processor core is powered off, wherein the first processor core is to enter the mode in which the first processor core is powered off in response to execution of an instruction by the first processor core;
a second processor core of the processor, the second processor core to save a state of the second processor core and to enter a mode in which the second processor core is powered off, wherein the second processor core is to enter the mode in which the second processor core is powered off in response to execution of an instruction by the second processor core; and
the first processor core to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered, wherein the first processor core is to restore the saved state of the first processor core when reset, and
the second processor core to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered, wherein the second processor core is to restore the saved state of the second processor core when reset.
12. The processor of claim 11, wherein the first processor core is to save the state of the first processor core in the cache memory.
13. The processor of claim 11, wherein the first processor core is to transition to the mode in which the first processor core is powered in response to a signal from a power management controller.
14. The processor of claim 13, wherein the second processor core is to transition to the mode in which the second processor core is powered in response to a signal from the power management controller.
15. The processor of claim 11, wherein the first processor core is to save and restore registers of the first processor core.
16. The processor of claim 11, wherein the first processor core is to save and restore a debug state of the first processor core.
saving a state of a first processor core of a processor;
entering a mode in which the first processor core is powered off;
saving a state of a second processor core of the processor;
entering a mode in which the second processor core is powered off;
powering a cache memory of the processor when the first processor core is powered off;
restoring the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered; and
restoring the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered.
18. The method of claim 17, wherein saving the state of the first processor core includes saving the state of the first processor core in the cache memory.
19. The method of claim 17, wherein entering the mode in which the first processor core is powered off is in response to execution of an instruction by the first processor core, and
wherein entering the mode in which the second processor core is powered off is in response to execution of an instruction by the second processor core.
20. The method of claim 17, wherein restoring the saved state of the first processor core occurs when the first processor core is reset, and
wherein restoring the saved state of the second processor core occurs when the second processor core is reset.
US12/706,631 2005-12-30 2010-02-16 Method and apparatus for powered off processor core mode Active 2026-12-01 US8707062B2 (en)
US11/323,254 US7664970B2 (en) 2005-12-30 2005-12-30 Method and apparatus for a zero voltage processor sleep state
US12/706,631 US8707062B2 (en) 2005-12-30 2010-02-16 Method and apparatus for powered off processor core mode
US13/220,413 US20120072750A1 (en) 2005-12-30 2011-08-29 Method and apparatus for a zero voltage processor sleep state
US13/339,284 US8799687B2 (en) 2005-12-30 2011-12-28 Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates
US13/619,998 US20130013945A1 (en) 2005-12-30 2012-09-14 Method and apparatus for a zero voltage processor sleep state
US14/966,708 US9874925B2 (en) 2005-12-30 2015-12-11 Method and apparatus for a zero voltage processor sleep state
US11/323,254 Continuation US7664970B2 (en) 2005-12-30 2005-12-30 Method and apparatus for a zero voltage processor sleep state
US13/220,413 Continuation US20120072750A1 (en) 2005-12-30 2011-08-29 Method and apparatus for a zero voltage processor sleep state
US13/339,284 Continuation-In-Part US8799687B2 (en) 2005-12-30 2011-12-28 Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates
US14/254,413 Continuation US9235258B2 (en) 2004-07-27 2014-04-16 Method and apparatus for a zero voltage processor
US14/496,345 Continuation US9223390B2 (en) 2004-07-27 2014-09-25 Method and apparatus for a zero voltage processor
US20100146311A1 US20100146311A1 (en) 2010-06-10
US8707062B2 true US8707062B2 (en) 2014-04-22
US11/323,254 Active 2027-10-30 US7664970B2 (en) 2005-12-30 2005-12-30 Method and apparatus for a zero voltage processor sleep state
US11/937,139 Active 2027-08-30 US7953993B2 (en) 2005-12-30 2007-11-08 Method and apparatus for a zero voltage processor sleep state
US12/706,631 Active 2026-12-01 US8707062B2 (en) 2005-12-30 2010-02-16 Method and apparatus for powered off processor core mode
US13/149,873 Active US8707066B2 (en) 2005-12-30 2011-05-31 Method and apparatus for a zero voltage processor sleep state
US13/220,413 Abandoned US20120072750A1 (en) 2005-12-30 2011-08-29 Method and apparatus for a zero voltage processor sleep state
US13/619,998 Abandoned US20130013945A1 (en) 2005-12-30 2012-09-14 Method and apparatus for a zero voltage processor sleep state
US14/254,422 Active US9081575B2 (en) 2004-07-27 2014-04-16 Method and apparatus for a zero voltage processor sleep state
US14/254,413 Active US9235258B2 (en) 2004-07-27 2014-04-16 Method and apparatus for a zero voltage processor
US14/496,345 Active US9223390B2 (en) 2004-07-27 2014-09-25 Method and apparatus for a zero voltage processor
US14/496,233 Active US9223389B2 (en) 2004-07-27 2014-09-25 Method and apparatus for a zero voltage processor
US14/630,909 Active US9141180B2 (en) 2004-07-27 2015-02-25 Method and apparatus for a zero voltage processor sleep state
US14/959,549 Active US9841807B2 (en) 2004-07-27 2015-12-04 Method and apparatus for a zero voltage processor sleep state
US14/966,708 Active US9874925B2 (en) 2004-07-27 2015-12-11 Method and apparatus for a zero voltage processor sleep state
US15/280,057 Active US9870044B2 (en) 2004-07-27 2016-09-29 Method and apparatus for a zero voltage processor sleep state
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US20100146311A1 (en) 2010-06-10
US7664970B2 (en) 2010-02-16
US9874925B2 (en) 2018-01-23
CN101351762A (en) 2009-01-21
US20170017297A1 (en) 2017-01-19
US9870044B2 (en) 2018-01-16
US20140310544A1 (en) 2014-10-16
US20160098075A1 (en) 2016-04-07
DE112006004276A5 (en) 2014-12-04
US20150006938A1 (en) 2015-01-01
DE112006004276A8 (en) 2016-11-10
US9841807B2 (en) 2017-12-12
US20120072750A1 (en) 2012-03-22
US20080072088A1 (en) 2008-03-20
US8707066B2 (en) 2014-04-22
US7953993B2 (en) 2011-05-31
CN102306048A (en) 2012-01-04
US20130013945A1 (en) 2013-01-10
DE112006003575B8 (en) 2016-10-20
JP2009516309A (en) 2009-04-16
US20150169043A1 (en) 2015-06-18
US20150058667A1 (en) 2015-02-26
WO2007078925A1 (en) 2007-07-12
TW200739332A (en) 2007-10-16
KR101021405B1 (en) 2011-03-14
US20110231681A1 (en) 2011-09-22
US9223390B2 (en) 2015-12-29
DE112006003575T5 (en) 2008-11-06
US20160091958A1 (en) 2016-03-31
CN104965581A (en) 2015-10-07
CN104965581B (en) 2018-03-02
US9141180B2 (en) 2015-09-22
TWI334979B (en) 2010-12-21
JP4875710B2 (en) 2012-02-15
US9081575B2 (en) 2015-07-14
US9235258B2 (en) 2016-01-12
US20170269672A9 (en) 2017-09-21
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US20150052377A1 (en) 2015-02-19
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DE112006003575B4 (en) 2015-10-08