Source: http://www.google.com/patents/US4307453?dq=5166694
Timestamp: 2015-03-27 07:36:58
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Matched Legal Cases: ['art 31', 'art 32', 'art 32', 'art 31', 'art 33', 'art 33', 'art 33', 'art 31', 'art 31', 'art 31', 'art 32', 'art 33', 'art 201', 'art 31', 'art 202', 'art 201', 'art 201', 'art 202', 'art 202', 'art 202', 'art 33', 'art 202', 'art 202']

Patent US4307453 - Sloping baseline compensation for a chromatographic analyzer - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method and apparatus is disclosed for correcting errors in a chromatographic analysis wherein the trailing edge of a strong peak interferes with the integration of the trailing peak which follows the strong peak. In one embodiment of the invention two functions of the trailing peak are electrically...http://www.google.com/patents/US4307453?utm_source=gb-gplus-sharePatent US4307453 - Sloping baseline compensation for a chromatographic analyzerAdvanced Patent SearchPublication numberUS4307453 APublication typeGrantApplication numberUS 06/046,411Publication dateDec 22, 1981Filing dateJun 7, 1979Priority dateDec 19, 1977Publication number046411, 06046411, US 4307453 A, US 4307453A, US-A-4307453, US4307453 A, US4307453AInventorsLouis D. KleissOriginal AssigneePhillips Petroleum CompanyExport CitationBiBTeX, EndNote, RefManPatent Citations (12), Referenced by (7), Classifications (12) External Links: USPTO, USPTO Assignment, EspacenetSloping baseline compensation for a chromatographic analyzer
US 4307453 AAbstract
1. Apparatus comprising:means for producing a first analog output signal having a varying voltage in time; a first integrating circuit adapted to integrate said first analog output signal over a period beginning at time t1 and ending at time t2 and adapted to establish a first signal representative of the results of the integration of said first analog output signal; means for establishing a second signal having a predetermined relationship to the difference between the voltage level of said first analog output signal at said time t1 and the voltage level of said first analog output signal at said time t2 ; and means for utilizing said second signal to shift the baseline used in the integration of said first analog output signal in such a manner that a correct integration of said first analog output signal may be performed even though the voltage level of said first analog output signal at said time t1 is not equal to the voltage level of said first analog output signal at said time t2. 2. Apparatus in accordance with claim 1 wherein said means for producing said first analog output signal comprises a chromatographic analyzer detector amplifier, wherein a first sample containing a first constituent is analyzed to produce said first analog output signal, wherein the portion of said first analog output signal beginning at said time t1 and ending at said time t2 is a first peak produced in response to the analysis of said first constituent, wherein a second sample substantially identical to said first sample is analyzed to produce a second analog output signal, wherein said second analog output signal has a second peak beginning at a time t3 and ending at a time t4 which is substantially identical to said first peak, and wherein the analysis of said second sample is carried out before the analysis of said first sample.
3. Apparatus in accordance with claim 2 wherein said means for establishing said second signal comprises:means for establishing a third signal representative of the difference between the voltage level of said second analog output signal at said time t3 and the voltage level of said second analog output signal at said time t4, wherein said third signal is substantially equal to the difference in the voltage level of said first analog signal at said time t1 and the voltage level of said analog output signal at said time t2 ; and means for dividing said third signal by -2 to establish said second signal. 4. Apparatus in accordance with claim 3 wherein said means for utilizing said second signal to shift the baseline used in the integration of said first analog output signal comprises means for adding said second signal to the voltage level of said first analog output signal at said time t1 in such a manner that the integration baseline for said first analog output signal, which was originally at the voltage level of said first analog output signal at said time t1, will be shifted to a voltage level which is approximately halfway betweeen the voltage level of said first analog output signal at said time t1 and the voltage level of said first analog output signal at said time t2.
5. A method for integrating a first analog output signal having a varying voltage in time comprising the steps of:integrating said first analog output signal over a period beginning at time t1 and ending at time t2 and establishing a first signal representative of the results of the integration of said first analog output signal; establishing a second signal having a predetermined relationship to the difference between the voltage level of said first analog output signal at said time t1 and the voltage level of said first analog output signal at said time t2 ; and utilizing said second signal to shift the baseline used in the integration of said first analog output signal in such a manner that a correct integration of said first analog output signal may be performed even though the voltage level of said first analog output signal at said time t1 is not equal to the voltage level of said first analog output signal at said time t2. 6. A method in accordance with claim 5 wherein said first analog output signal is the output signal produced by a chromatographic analyzer detector amplifier when a first sample containing a first constituent is analyzed, wherein the portion of said first analog output signal beginning at said time t1 and ending at said time t2 is a first peak produced in response to the analysis of said first constituent, wherein a second sample substantially identical to said first sample is analyzed to produce a second analog output signal, wherein said second analog output signal has a second peak beginning at a time t3 and ending at a time t4 which is substantially identical to said first peak, and wherein the analysis of said second sample is carried out before the analysis of said first sample.
7. A method in accordance with claim 6 wherein said step of establishing said second signal comprises:estabishing a third signal representative of the difference between the voltage level of said second analog output signal at said time t3 and the voltage level of said second analog output signal at said time t4, wherein said third signal is substantially equal to the difference in the voltage level of said first analog signal at said time t1 and the voltage level of said analog output signal at said time t2 ; and dividing said third signal by -2 to establish said second signal. 8. A method in accordance with claim 7 wherein said step of utilizing said second signal to shift the baseline used in the integration of said first analog output signal comprises adding said second signal to the voltage level of said first analog output signal at said time t1 in such a manner that the integration baseline for said first analog output signal, which was originally at the voltage level of said first analog output signal at said time t1, will be shifted to a voltage level which is approximately halfway between the voltage level of said first analog output signal at said time t1 and the voltage level of said first analog output signal at said time t2.
This application is a division of copending application Ser. No. 862,065, filed Dec. 19, 1977, now U.S. Pat. No. 4,170,893.
In a typical chromatographic analyzer, the detector amplifier voltage rises and falls as peaks are eluted at predictable times. An electrical integrator is programmed to operate over a time interval representing a particular peak. Just before the integration begins, the integrator reference voltage is clamped, or zeroed, at the detector amplifier voltage which exists before integration. This establishes a flat baseline against which the peak of interest is integrated. This method of zeroing, well known and widely used, serves well when the peak of interest is distinct from other peaks. However, large measurement error can occur when a small peak of interest closely follows a large peak. The trailing edge of the large peak can overlap the relative small peak of interest. Seen on a voltage recorder, the peak of interest appears as a small hump on a downsloping baseline. When this sloping baseline is ignored, using the conventional flat baseline integration method above, a true integration of the small peak cannot be secured.
FIG. 2 is an illustration of two overlapping peaks in an exemplary output of a chromatographic analysis;
Detector means 17 establishes a differential output by establishing an electrical signal 21 representative of the composition of the carrier fluid carrying the sample passing through the sample portion of detector means 17 and an electrical signal 22 representative of the composition of the carrier gas only in the reference portion of detector means 17. Signals 21 and 22 are then compared by detector amplifier 23 to produce signal 24 representative of a chromatographic analyzer output signal. Signal 24 is supplied to the input board 25. Input board 25 operates on signal 24 to produce signal 26 representative of either the peak height or the peak area of the selected components in the stream. Signal 26 is supplied to recording means 27 where it is stored.
The present invention in a preferred embodiment calculates and adds a baseline correction to the integration described above. This is shown in FIG. 3. The part of FIG. 3 labeled 31 represents the integration carried out as described in connection with FIG. 2. The part of FIG. 3 labeled 32 represents the correction factor for the integration shown in part 31. The shaded area of part 32 is equal to A-B/2 integrated over the time t, where A and B are voltage levels as has been previously stated and where t is the length of the period of integration for the particular peak represented by t2 -t1. When the shaded area shown in part 32 of FIG. 3 is added to the integration performed as shown in part 31 the result is the shaded area shown in part 33. It can be seen that the shaded area of part 33 corresponds more closely to the area under the peak formed by the second component after excluding the effect of the trailing edge of the peak formed by the first component, than would be achieved by zeroing the second signal at voltage level A. Thus the composite integration shown in part 33 is a more accurate representation of the second peak.
FIG. 4 is a preferred embodiment of the input board 25 shown in FIG. 1 which is capable of performing the functions shown in FIG. 3. The output signal 24 from detector amplifier 23 is first processed by the preamplifier circuit 50. Signal 24 from detector amplifier 23 is fed to the non-inverting terminal of operational amplifier 51 through a filter element made up of resistors 52 and 53 and capacitor 54. The output signal 62 from the automatic zeroing circuit 61 is fed to the inverting terminal of operational amplifier 51 through resistor 63. The feedback network for operational amplifier 51 is connected to the inverting terminal and is made up of resistors 55, 56, 57 and capacitor 58.
The output signal 78 from operational amplifier 73 is fed to the noninverting terminal of operational amplifier 81. The feedback network for operational amplifier 81, made up of resistor 82 and capacitor 83 is fed to the inverting terminal of operational amplifier 81 and to ground through resistor 85.
The output signal 87 from operational amplifier 81 is fed through resistor 92 to summing junction 93. Output signal 87 is also provided as an input to the automatic zeroing circuit 61.
The output signal 119 from operational amplifier 113 is supplied to the non-inverting terminal of operational amplifier 121. The feedback circuit for operational amplifier 121, made up of resistor 123 and capacitor 124, is supplied to the inverting terminal of operational amplifier 121 and is supplied to ground through resistor 125. The output signal 127 from operational amplifier 121 is fed as a second input to multiplying means 101. Signal 103 from multiplying means 101 is fed as a second input through resistor 104 to summing junction 93. Resistors 92 and 104 comprise a summing network, and the signal 97 at summing junction 93 is proportional to the sum of signals 87 and 103.
At the start of an integration period, the integrating circuit 71 input is essentially at ground and the output signal 87 has a zero voltage level. Just before the integration period begins, the automatic zero circuit 61 sets the preamplifier circuit 50 output signal 59 to zero which corresponds to voltage level A in part 31 of FIG. 3. The automatic zeroing circuit 61 is well known in the art of chromatography. A typical zeroing circuit which could be utilized in the present invention is described in U.S. Pat. 3,152,301.
When either switching means 64 or 66 is closed the integration is started by the integrating circuit 71. At the end of the integration period the output signal 87 from the integrating circuit 71 is representative of the crosshatched area enclosed by the lines CD, DB and sinal 24 shown in part 31 of FIG. 3 subtracted from the crosshatched area enclosed by the line AC and signal 24 shown in part 31 of FIG. 3.
At the start of each integration period, the output of integration circuit 112 is set to zero. A fixed voltage supplied by voltage generator 110 is integrated, simultaneously with the integration of signal 59, by the integrating circuit 112 for the integration period. The output signal 127 from the integrating circuit 112 is thus proportional to the integration time.
Signal 127 is supplied to multiplying means 101. Multiplying means 101 is also supplied with signal 59 which will be proportional to the voltage difference between A and B shown in FIG. 3 at the end of the integration period. The fixed voltage is selected as the inverse of the multiplier 101 gain divided by two because the area of a triangle is equal to one-half the base times the height. Signals 59 and 127 are multiplied by multiplying means 101 to produce signal 103 which is representative of the triangular crosshatched area shown in part 32 of FIG. 3. Signals 87 and 103 are then summed in the resistor network comprised by resistors 92 and 104 to create signal 97. At the end of the integration period, signal 97 represents the area under the peak formed by signal 24 as shown by the crosshatched area of part 33 of FIG. 3. Switching means 100 closes momentarily at the end of the integration period, and the sample-and-hold circuit 90 clamps signal 94 and delivers it to recording means 27 until another integration is preformed on the next cycle of the analyzer.
A second less preferred solution to the problem of reducing errors in peak integration caused by a drifting baseline introduced by the trailing edge of a preceding large peak is illustrated in FIG. 5. Part 201 of FIG. 5 corresponds to part 31 of FIG. 3 and has been previously described. Part 202 of FIG. 5 presents a solution to the error in the actual area under the measured peak that is shown in part 201. The baseline AD shown in part 201 has been shifted in part 202. Line EFG represents the new baseline. The voltage level represented by the line EFG in part 202 is halfway between voltages A and B. In part 202 the area enclosed by the lines FG, GB and signal 24 is subtracted from the area enclosed by the lines AE, EF and signal 24. The resulting area is substantially equal to the area under the measured peak as is shown in part 33 of FIG. 3.
FIG. 6 presents a less preferred embodiment of the input board shown in FIG. 1 which is capable of performing the baseline shift shown in part 202 of FIG. 5. It assumes that the term, (Voltage A-Voltage B)/2, is substantially constant from one integration to the next. This term is calculated and stored during each integration. During the next integration this stored term is used to bias the integrator reference voltage, thus performing the baseline shift shown in part 202 of FIG. 5. The preamplifier circuit 50, the attenuating circuit 60, the automatic zero circuit 61, the integrating circuit 71 and the sample-and-hold circuit 90 are identical to the circuits illustrated and described in conjunction with FIG. 4.
A drive signal 211 which is at a positive voltage level during an integration cycle and is at a zero or negative voltage level at the end of an integration cycle is supplied through resistor 212 and diode 213 to the base of transistor 214. The emitter of transistor 214 is grounded. The collector of transistor 214 is connected to relay 215. Relay 215 is also connected to a +5 volt power supply shown as signal 216.
A second +5 volt power supply is supplied to the base of transistor 221 through a pulse circuit made up of resistors 222, 223, and 224; capacitor 225; and diode 226 when switching means 227 is closed. The emitter of transistor 221 is grounded. The collector of transistor 221 is connected to relay 228. Relay 228 is also supplied by a +5 V power supply shown as signal 229.
Signal 59 is supplied to a sample and hold circuit 231 when switching means 232 is closed. The sample and hold circuit is made up of capacitor 233, operational amplifier 234, and a variable resistor 235. Signal 59 is fed to the non-inverting input of operational amplifier 234. The feedback loop 237 for operational amplifier 234 is connected to the inverting terminal of operational amplifier 234. The output signal 238 from operational amplifier 234 is supplied through variable resistor 239 to the inverting input of operational amplifier 51 as signal 241 when switching menas 236 is closed.
Signal 59 is supplied to a sample and hold circuit 231 when switching means 232 is closed. The sample and hold circuit is made up of capacitor 233, operational amplifier 234, and a variable resistor 235. Signal 59 is fed to the non-inverting input of operational amplifier 234. The feedback loop 237 for operational amplifier 234 is connected to the inverting terminal of operational amplifier 234. The output signal 238 from operational amplifier 234 is supplied through variable resistor 239 to the inverting input of operational amplifier 51 as signal 241 when switching means 236 is closed.
When the next integration cycle of the peak of interest begins, the drive signal 211 will be at a positive voltage level causing transistor 214 to turn on thus causing relay 215 to close switching means 236. When switching means 236 is closed output signal 238, which is representative of voltage level B, from the sample and hold circuit 231 will be supplied through a variable resistor means 239 to the inverting input of operational amplifier 51. The variable resistor is calibrated so as to provide an input signal 241 to the inverting input of operational amplifier 51 which has the same effect on amplifier output as a detector amplifier voltage change of (-)B/2, where level B is referenced from voltage level A.
The invention has been descried in terms of its presently preferred embodiment as is shown in FIGS. 3 and 4 and a less preferred embodiment shown in FIGS. 5, 6, and 7. For the sake of convenience signals which supply power to the various chips shown in the schematics of FIGS. 4, 6 and 7 have been omitted. Voltage levels required by various chips are specified by the manufacturers and are well known to those familiar with the art.
______________________________________Resistors 52,53        4.99 K&#937;                  TRW/IRCResistors 55,75,116        15 K&#937;                  TRW/IRCResistor 56  7.5 K&#937;                  TRW/IRCResistor 57  220 K&#937;                  TRW/IRCResistor 63  22 K&#937;                  TRW/IRCResistors 72,114        1.8 K&#937;                  TRW/IRCResistors 82/123        820 K&#937;                  TRW/IRCResistors 85,125        8.2 K&#937;                  TRW/IRCResistors 92,104        10 K&#937;                  TRW/IRCResistor 95  2.2 K&#937;                  TRW/IRCResistor 212 560 &#937;                  TRW/IRCResistor 222 200 &#937;                  TRW/IRCResistor 223 100 K&#937;                  TRW/IRCResistor 224 1 K&#937;                  TRW/IRCResistor 323 1 Meg &#937;                  TRW/IRCResistor 316 27 K&#937;                  TRW/IRCPotentiometer 239        20 K&#937;                  BournsPotentiometer 65,232        5 K&#937;                  BournsCapacitor 54 2 &#956;f   SpragueCapacitors 58,233        1 &#956;f   SpragueCapacitors 76,117,311        .001 &#956;f                  SpragueCapacitors 77,118,321        .01 &#956;f SpragueCapacitors 83,124        .002 &#956;f                  SpragueCapacitor 225        20 &#956;f  SpragueCapacitors 322,333,99        .5 &#956;f  SpragueOperational            Ma741C,Amplifier 51           Fairchild ElectronicsOperationalAmplifiers 73,113      3542J, Burr BrownOperationalAmplifiers 81,121      558, SigneticsOperationalAmplifiers 234,98      Philbrook 1009Transistor 214         2N3569, National                  SemiconductorTransistor 221         2N1711, National                  SemiconductorDiodes 213,226         IN4024, National                  SemiconductorMultiplying means 101  No.BO5885 Multiuse Amp.                  Applied Automation, Inc.Relay 215              CR2Z-1008 ClarereedRelay 228,100          W102 MX1, MagnecraftTimer 314              Timer 555, SigneticsRelay 318              AWCB-16411 D414                  Adams &amp; WestlakeSwitching              Quad Bilateralmeans 227,232,236      Switch CD4016C                  National Semiconductor______________________________________
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