Source: https://patents.google.com/patent/JP4539107B2/en
Timestamp: 2020-07-10 01:33:38
Document Index: 476573219

Matched Legal Cases: ['art.\n18', 'art 6', 'art 2', 'art 3', 'art 4', 'art 5', 'art 6', 'art 7', 'art 10', 'art 11', 'art 12', 'art 13', 'art 14', 'art 15']

JP4539107B2 - Transmitting apparatus and bit arrangement method - Google Patents
Transmitting apparatus and bit arrangement method Download PDF
JP4539107B2
JP4539107B2 JP2004035768A JP2004035768A JP4539107B2 JP 4539107 B2 JP4539107 B2 JP 4539107B2 JP 2004035768 A JP2004035768 A JP 2004035768A JP 2004035768 A JP2004035768 A JP 2004035768A JP 4539107 B2 JP4539107 B2 JP 4539107B2
JP2004035768A
JP2005229319A (en
俊治 宮崎
哲也 矢野
2004-02-12 Application filed by 富士通株式会社 filed Critical 富士通株式会社
2004-02-12 Priority to JP2004035768A priority Critical patent/JP4539107B2/en
2005-08-25 Publication of JP2005229319A publication Critical patent/JP2005229319A/en
2010-09-08 Publication of JP4539107B2 publication Critical patent/JP4539107B2/en
The present invention relates to a transmission apparatus, for example, a radio base station and a transmission method in a mobile radio communication system employed in a W-CDMA communication system.
Currently, standardization of the W-CDMA system, which is one system of the third generation mobile communication system, is being promoted by 3GPP (3rd Generation Partnership Project). As one of the themes of standardization, HSDPA (High Speed Downlink Packet Access) that provides a maximum transmission speed of about 14 Mbps in the downlink is defined. HSDPA employs an adaptive coding modulation method, and is characterized by, for example, adaptively switching between a QPSK modulation method and a 16-value QAM method according to the radio environment between a base station and a mobile station. HSDPA employs an H-ARQ (Hybrid Automatic Repeat reQuest) method, and when an error is detected in data transmitted from a base station, retransmission is performed in response to a request from a mobile station.
Main wireless channels used for HSDPA include HS-SCCH (High Speed-Shared Control Channel), HS-PDSCH (High Speed-Physical Downlink Shared Channel), and HS-DPCCH (High Speed-Dedicated Physical Control Channel).
HS-SCCH and HS-PDSCH are both common channels in the downlink direction (that is, the direction from the base station to the mobile station), and HS-SCCH transmits various parameters related to data to be transmitted on HS-PDSCH. Control channel. Examples of the various parameters include modulation type information indicating which modulation scheme is used to transmit data by HS-PDSCH, and information such as the number of assigned spreading codes (number of codes).
On the other hand, the HS-DPCCH is an individual control channel in the uplink direction (that is, the direction from the mobile station to the base station), and ACK and NACK are received depending on whether or not data received via the HS-PDSCH is receivable. Is used when the mobile station transmits to the base station.
In addition, it is also used for measuring the reception quality (for example, SIR) of the received signal from the base station and transmitting the result to the base station as CQI (Channel Quality Indicator). The base station determines whether the downlink radio environment is good or not based on the received CQI. If the base station is good, the base station switches to a modulation method capable of transmitting data at a higher speed. Switch to a modulation scheme for transmitting data (ie, perform adaptive modulation).
・ "Channel structure"
Next, a channel configuration in HSDPA will be described.
FIG. 1 is a diagram for illustrating a channel configuration in HSDPA. Since W-CDMA employs a code division multiplexing system, each channel is separated by a code.
First, the channels not described will be briefly described.
CPICH (Common Pilot Channel) and P-CCPCH (Primary Common Control Channel) are downlink common channels, respectively.
The CPICH is a channel used for channel estimation, cell search, and a timing reference for other downlink physical channels in the same cell in a mobile station, and is a channel for transmitting a so-called pilot signal. P-CCPCH is a channel for transmitting broadcast information.
Next, channel timing relationships will be described with reference to FIG.
As shown in the figure, each channel constitutes one frame (10 ms) by 15 slots. As described above, since CPICH is used as a reference for other channels, the heads of P-CCPCH and HS-SCCH frames coincide with the heads of CPICH frames. Here, the head of the HS-PDSCH frame is delayed by 2 slots with respect to HS-SCCH or the like. However, after the mobile station receives the modulation type information via HS-SCCH, the received modulation type is changed to the received modulation type. This is because HS-PDSCH can be demodulated by a corresponding demodulation method. HS-SCCH and HS-PDSCH constitute one subframe with three slots.
This is because HS-DPCCH is not synchronized with CPICH, but is an uplink channel and is based on timing generated in the mobile station.
The above is a simple description of the channel configuration of HSDPA. Next, a process until transmission data is transmitted via HS-PDSCH will be described with reference to a block diagram.
・ Base station configuration
FIG. 2 shows the configuration of a base station that supports HSDPA.
In the figure, 1 is a CRC adding unit, 2 is a code block dividing unit, 3 is a channel coding unit, 4 is a bit separating unit, 5 is a rate matching unit, 6 is a bit collecting unit, and 7 is a modulating unit.
Next, the operation of each block will be described.
Transmission data transmitted via HS-PDSCH (data stored in one subframe of HS-PDSCH in FIG. 1) is first subjected to CRC calculation processing in one CRC adding unit, and the calculation result is the transmission data Added to the end. The transmission data to which the CRC calculation result is added is input to the code block dividing unit 2 and divided into a plurality of blocks. This is for shortening the data length of the unit for performing error correction coding in consideration of the decoding processing load on the receiving side. When the data length exceeds a predetermined length, it is equally divided into a plurality of blocks. The number of divisions can be an integer greater than or equal to 2, but the case where the number of divisions is 2 will be described below for the sake of simplicity.
Each of the divided transmission data is handled as data to be subjected to separate error correction coding in the channel coding unit 3. That is, error correction coding processing is performed on each of the divided first block and second block. An example of channel coding is turbo coding.
Here, the turbo coding will be briefly described. In turbo coding, if the data to be coded is U, based on U, U itself, U ′ obtained by convolutional coding of U, and U are interleaved (rearrangement processing). Similarly, U ″ obtained by convolutional coding is output. Here, U is referred to as a systematic bit, and is data used in both of the two element decoders in turbo decoding. Since U is frequently used, it can be understood that U is highly important data. On the other hand, U ′ and U ″ are redundant bits, each of which is data used by one of the two element decoders. Since the usage frequency is low, it can be understood that the importance is lower than U.
That is, the systematic bits are more important than the redundant bits, and it can be said that a correct decoding result can be obtained by the turbo decoder when the systematic bits are received more correctly.
Now, the systematic bits and redundant bits generated in this way are input as serial data to the bit bit separator 4, and the bit separator 4 converts the input serial data into U, U ′, U ″. Are divided into three data lines and output as parallel data.
The rate matching unit 5 performs a puncturing process for deleting bits by a predetermined algorithm or a repetition process by repeating bits so as to fit within a subframe composed of 3 slots of HS-SCCH.
In this way, the bits subjected to the bit adaptation processing for the subframe in the rate matching unit 5 are input in parallel to the bit collection unit 6.
For example, the bit collection unit 6 generates and outputs a 4-bit bit string indicating each signal point of 16-level QAM modulation based on the input data.
The modulation unit 7 outputs a 16-value QAM modulated signal having an amplitude and phase corresponding to the signal point indicated by the input bit string, converts the signal to a radio frequency by frequency conversion, and then an antenna (not shown) Send to the side.
・ "Placement method"
Here, the processing of the bit collection unit will be described in more detail.
FIG. 3 is a diagram illustrating an arrangement method in the bit collection unit 6.
Bits including systematic bits, redundant bits, etc. output through the rate matching process need to be associated with a bit string indicating each signal point in 16-value QAM modulation, and thus must be arranged in a 4-bit data string.
The systematic bits and the redundant bits are divided into two systems of the first block and the second block by the code block dividing unit. However, since these are stored in the same subframe, in the bit collecting unit 6, Again, they are combined and handled as one unit.
In FIG. 3, the entire bit string indicated by Nr (4) × Nc (10) corresponds to the combined bit and redundant bit, and the areas indicated by S1, S2, S3, and P2-1 in the first column are , A bit string corresponding to one signal point when performing 16-value QAM modulation, and according to FIG. 3, since there are 10 bit strings, 10 bit strings for 10 signal points are represented.
First, the code block division unit 2 obtains the total number Nsys of systematic bits of each block divided into two (the sum of the systematic bit number of the first block and the systematic bit number of the second block after the rate matching process).
Next, Nsys is divided by the total number Nc of columns (total number of bits 40 ÷ number of bit columns 4 = 10), and the quotient A and the remainder B are obtained.
Then, an area for systematic bits is defined in order from the top for the same number of rows as the quotient A, and for the systematic bits in order from the left side of the next line of the area occupied by the systematic bit area by the same number as the remainder B. Is defined as
According to this, the area shown by the oblique lines in FIG. 3 is defined as the area for systematic bits. The remaining area is defined as an area for redundant bits.
Next, the systematic bits of the first block are assigned to the systematic bit definition area in order from the top in the first row and the first column in the column direction. When the systematic bit area in the first column is filled, The systematic bits in the second column are filled in the same way.
On the other hand, redundant bits are sequentially assigned to the redundant bit area shown in FIG. 3 from the first column. Specifically, if the redundant bit corresponding to U ′ is the first redundant bit and the redundant bit corresponding to U ″ is the second redundant bit, first, the first of the second redundant bits in the first block is the redundant bit. Assigned to the first column of the bit area, then the first of the first redundant bits of the first block is assigned to the second column of the redundant bit area, and then the second of the second redundant bits of the first block Is assigned to the third column. In this way, the redundant bit area is assigned by alternately assigning the second redundant bit and the first redundant bit. In FIG. 3, the arrangement order is clearly indicated by an arrow, and the Nth bit of the Mth redundant bit is clearly indicated by PM-N.
The bit string arranged as described above indicates each signal point on the phase plane shown in FIG. 4. For example, (S1, S2, S3, P2-1) = (1, 0, 1, 1 ) Indicates a signal point A.
Such an arrangement method is disclosed in, for example, the following Non-Patent Document 1.
3G TS 25.213 (3rd Generation Partnership Project: Technical Specificati on Group Radio Access Network; Spreading and modulation (FDD))
The inventor has discovered that problems arise with the prior art as described above.
That is, when multilevel modulation is employed, if mapping on the phase plane as described above is performed, the upper bits (S1, S4, S7,..., S21, S23, S2, S5) of each aligned bit string are performed. , S8,..., S22, S24), lower bits (S3, S6, S9,..., P2-7, P2-8, P2-1, P1-1,..., P1-7, P1-8) Tends to be error-prone at the time of signal point determination on the receiving side due to variations in phase and amplitude during wireless transmission, but when comparing the divided first block and second block as shown in FIG. Four systematic bits of one block are arranged in the lower bits, whereas no systematic bit of the second block is assigned to the lower bits.
As described above, systematic bits can be positioned as important information. However, according to the above-described arrangement method, phase and amplitude fluctuations during radio transmission between blocks due to the arrangement of systematic bits. The durability against is different.
Further, when the systematic bits are small, as shown in FIG. 8, when the divided first block and second block are compared, the redundant bits of the first block are not assigned to the upper bits, whereas Four redundant bits of two blocks are assigned to the upper bits, and according to the arrangement method described above, the durability against phase and amplitude fluctuations during wireless transmission between the blocks due to the arrangement of redundant bits. It will be different.
Therefore, regardless of whether the systematic bit or the redundant bit is the same type of bit between the blocks, there is a difference in durability between the blocks due to the arrangement of the signal points. The reception quality becomes different in the first place, and there is a problem that the fairness of quality between blocks is lost.
One of the objects of the present invention is to equalize durability against errors between blocks.
In addition, when error correction processing such as turbo code is performed, error correction can afford more errors for those with higher durability, but errors with errors that exceed the error correction capability for those with lower durability. There is also a problem that the situation that it occurs easily occurs and is not efficient.
One of the objects of the present invention is to improve error correction efficiency by equalizing durability against errors between blocks when performing error correction processing such as turbo codes.
Also, when adopting a method that cannot identify which of the multiple blocks is wrong, it is actually error-free by increasing the probability that both blocks will be wrong at the same time or not at the same time. Another object is to reduce the chance of transmitting unnecessary signals by retransmitting the side block.
It is to be noted that the present invention is not limited to the above-described object, and is an effect derived from each configuration shown in the best mode for carrying out the invention described later, and has an effect that cannot be obtained by the conventional technique. Can be positioned as one.
(1) In the present invention, a plurality of bit strings are generated using the bits included in the first data block and the bits included in the second data block, and each of the plurality of bit strings is represented by each signal point on the phase plane. In a transmitting apparatus that transmits a signal obtained by performing multi-level modulation according to each signal point, a predetermined bit included in the first data block occupies a predetermined bit position in the bit string A transmission apparatus comprising: a bit string generation means for controlling the generation so that an occupation ratio and an occupation ratio occupied by a predetermined bit included in the second data block are close to each other.
(2) In the present invention, the transmission apparatus according to (1) is further used, wherein the transmission is performed within the same radio frame.
(3) In the present invention, the bit sequence further includes a first bit position and a second bit position that is more susceptible to error than the first bit position due to the correspondence, and the predetermined bit. The position is the first bit position or the second bit position, and the transmission device according to (1) is used.
(4) In the present invention, the first data block and the second data block each include a systematic bit and a redundant bit, and the predetermined bit included in the first data block and the second data block The predetermined bits included are both systematic bits, and the bit string generation unit performs control so that the systematic bits are preferentially arranged at the first bit positions in accordance with the control. (3).
(5) In the present invention, the amplitude phase modulation is 16-value QAM modulation, the first bit position is upper bits (first bit and second bit), and the second bit position is lower order The transmission device according to (3), which is a bit (the third bit and the fourth bit), is used.
(6) In the present invention, each of the first data block and the second data block includes a systematic bit and a redundant bit. The predetermined bit included in the first data block and the second data block The transmission apparatus according to (1) is used, in which the predetermined bits included are both systematic bits or redundant bits.
(7) In the present invention, the first data block and the second data block include systematic bits obtained by turbo coding, first redundant bits, and second redundant bits, and the first data block The predetermined bits included in the block and the predetermined bits included in the second data block are both systematic bits, are both redundant bits, or are both first redundant bits, Alternatively, the transmission device according to (1) is used, both of which are the second redundant bits.
(8) In the present invention, a division unit that divides data and one error detection code for the data into N blocks, and error correction coding that performs error correction coding processing on each of the N blocks , An arrangement means for arranging N kinds of systematic bits and redundant bits obtained after the error correction processing in a plurality of bit strings, and amplitude phase modulation corresponding to each signal point on the phase plane indicated by each of the arranged bit strings A transmission unit that performs transmission after performing the transmission, and the placement unit has a first error that differs in error probability in one bit string due to the correspondence between the bit string and the signal point during the placement. In the case where there are a bit and a second bit, a transmission apparatus is used which equalizes the number of N types of systematic bits arranged in the error-prone bit.
(9) In the present invention, the arrangement means arranges the plurality of bit strings using the bits included in the first block to the bits included in the Nth block in substantially the order, The transmitter according to (8) is used, which is realized by distributing a column that allows the systematic bits to be arranged in the bits on the error-prone side.
(10) In the present invention, the transmission data is divided into two or more bit groups including a first bit group including X bits and a second bit group including Y bits, and the bits of the first bit group And a bit of the second bit group are arranged at each bit position of a predetermined length bit string having a first bit position and a second bit position that is more likely to be erroneous than the first bit position, thereby generating L bit strings. In the bit arrangement method in the bit string generation device, the bit included in the first bit group and the bit included in the second bit group are arranged with priority over the first bit position, and <N> is less than or equal to N When defining the largest integer,
(<(X + Y) ÷ L> +1) × (X + Y − <(X + Y) ÷ L> × L) ≦ X,
2 ≦ (X + Y − <(X + Y) ÷ L> × L)
In this case, the number of bits included in the first bit group arranged at the second bit position is expressed as X + Y − <(X + Y) ÷ L> × L
The bit arrangement method in the bit arrangement apparatus is characterized in that the number of bits included in the second bit group arranged at the second bit position is 1 or more.
(11) Further, in the present invention, a radio base station that supports HSDPA includes a bit collection unit that rearranges data subjected to rate matching processing and generates a 4 × Nc bit string for 16-value QAM. The data includes at least a first data block and a second data block by division in the code block division unit, and <N> is defined as a maximum integer equal to or smaller than N, and A = <Nsys ÷ Nc>, When B = Nsys−A × Nc is defined, the bit collection unit sequentially arranges systematic bits from the first column to the Nc column for the first row to the Ath row, For the row, a radio base station is used, which is characterized in that B systematic bits can be arranged without being continuous from the first column to the Nc column.
Since the durability of at least the bits of the first block and the bits of the second block (for example, the durability of the same type of bits) is made uniform, there is less bias that one is high and the other is low. The overall error occurrence probability can be lowered.
Also, by increasing the probability that both blocks will be mistaken at the same time or not at the same time, it is possible to reduce the chance of transmitting unnecessary signals by retransmitting the block that is actually free of errors. it can.
[A] Description of First Embodiment FIG. 5 is a diagram illustrating a transmission apparatus according to the present invention.
As an example of the transmission apparatus, a transmission apparatus (radio base station) of the W-CDMA communication system corresponding to the HSDPA described above will be described. It is also possible to apply to a transmission device in another communication system.
In the figure, reference numeral 10 denotes a control unit that sequentially outputs transmission data (data to be transmitted within one subframe) transmitted via the HS-DSCH and controls each unit (11 to 25, etc.). Since HS-DSCH is a common channel, transmission data that is sequentially output is allowed to be addressed to different mobile stations.
11 is a CRC attachment unit for performing CRC calculation on sequentially input transmission data (data to be transmitted in the same radio frame) and adding a CRC calculation result to the end of the transmission data; A bit scrambling unit that gives transmission data randomness by scrambling transmission data to which the CRC calculation result is added in units of bits is shown.
13 is a bit input for the purpose of preventing an increase in the amount of calculation of the decoder on the receiving side due to the data length to be encoded becoming too long in the next channel encoding. A code block segmentation unit that divides (for example, approximately equal) when transmission data after scramble exceeds a predetermined data length is shown. In the figure, the output when the input data length exceeds a predetermined data length and is divided into two equal parts (divided into a first data block and a second data block) is shown. Of course, an example in which the number of divisions is other than 2 can be considered, and an example in which the data is not divided equally but divided into different data lengths can be considered.
Reference numeral 14 denotes a channel coding unit that performs error correction coding processing on each divided data separately. Note that the above-described turbo encoder is preferably used as the channel encoding unit 14, and a turbo encoder is also used here.
Therefore, as described above, the first output is obtained by convolutionally encoding the systematic bits (U) and the systematic bits (U), which are the same data as the data to be encoded, for the first block. The obtained first redundant bit (U ′) and the second redundant bit (U ″) obtained by interleaving the systematic bit and then performing convolutional coding in the same manner are included. Similarly, the second output includes a systematic bit (U), a first redundant bit (U ′), and a second redundant bit (U ″) for the second block.
15 is a systematic bit (U), a first redundant bit (U ′), and a second redundant bit (U ″) of the first block and the second block serially input from the channel encoding unit 14 (turbo encoder). ) Shows a bit separation part for separating and outputting each. Since the same applies to the second block, only the output corresponding to the first block is shown.
16, to fit in a predetermined area of the subsequent buffer 17, a first rate matching (1 st rate matching) unit for performing rate matching processing such as puncturing processing (thinning-out).
17 is a buffer in which an area corresponding to the reception processing capability of the mobile station to be transmitted is set by the control unit 10, and the data subjected to the rate matching process by the first rate matching unit 16 is stored in the set area. Indicates the (Buffer) part.
18, the control unit 10 shows a second rate matching (2 nd rate matching) unit for adjusting the data length that can be accommodated in one subframe specified, puncturing (thinning), repetition processing (repetition ) To adjust the data length of the input data so that the specified data length is obtained.
In HS-PDSCH, parameters such as modulation scheme, spreading factor, code number (number of channels), etc. are variable, so the number of bits that can be stored is not constant even for subframes of the same length. 10 notifies the second rate matching unit 18 of the number of bits corresponding to the parameter as a data length that can be stored in one subframe.
Reference numeral 19 denotes a bit collection unit that arranges data from the second rate matching unit 19 into a plurality of bit strings. That is, by arranging the data of the first block and the data of the second block by a bit arrangement method to be described later, a plurality of bit strings for indicating signal points on the phase plane are output. In this embodiment, since the 16-value QAM modulation method is used, the bit string is composed of 4 bits. Of course, an example using another multilevel modulation method (for example, 8-phase PSK) can be considered.
20 divides and outputs the bit string to the same number of systems as the number of spreading codes (number of codes) notified by the control unit 10. In other words, when the number of codes in the transmission parameter is N, a physical channel segmentation unit that outputs the input bit string to the 1 to N systems in order is output.
Reference numeral 21 denotes an interleaving unit that performs interleaving processing on each of the N bit strings and outputs the result.
Reference numeral 22 denotes a constellation re-arrangement for 16 QAM unit that can re-arrange bits in each bit string for each input bit string. For example, at the time of the first transmission, each input bit string can be output as it is, and the bits can be rearranged at the time of retransmission in H-ARQ described above. The bit rearrangement is, for example, processing such as switching the upper bit and the lower bit, and it is preferable to perform bit replacement according to the same rule for a plurality of bit strings. In addition, it is possible to pass through as it is at the time of retransmission.
Reference numeral 23 denotes a physical channel mapping unit that distributes the N-system bit string in the subsequent stage to the corresponding spreading unit of the spreading processing unit 24 in the subsequent stage.
24 includes a plurality of spreading sections, each of which outputs a corresponding I and Q voltage value based on each of N systems of bit strings, and performs a spreading process using different spreading codes, and outputs a spreading process (Spreading) section. Show.
The 4-bit bit string is converted into voltage values of I and Q components according to the following Table 1. However, I1, Q1, I2, and Q2 correspond in order from the upper bit.
The table will be described with an example. If the 4-bit bit string is (0100), I1, I2 = 0, 0, and Q1, Q2 = 1.0, so I = + 1, Q = -1. It will be converted to the voltage.
As a spreading method, for example, as shown in FIG. 6, after conversion by the voltage conversion unit 26 according to the previous table, calculation is performed by a multiplier, an adder, and a subtractor using the I component CI of the spread code and the CQ of the Q component, Implement diffusion processing.
25 synthesizes each signal spread by the spread processing unit 24, performs amplitude phase modulation such as a 16-value QAM modulation system based on this, converts the frequency to a radio signal, and outputs it to the antenna side A modulation unit that enables transmission as a radio signal is shown.
The above is the description of each part name and its operation. A plurality of bit strings are generated using the bits included in the first data block and the second data block, and each bit string is assigned to each signal point on the phase plane. It can be seen that the signal is transmitted after being subjected to phase amplitude modulation corresponding to each signal point.
・ "Bit placement method"
Next, a bit arrangement method in the bit collection unit 19 as an example of the bit string generation unit and the arrangement unit will be described in detail.
FIG. 7 is a diagram for explaining a bit arrangement method in the bit collection unit.
Since the systematic bits and redundant bits output through the rate matching process by the first rate matching unit 16 and the second rate matching unit 18 need to be assigned to each signal point in 16-value QAM modulation, they are aligned in a 4-bit bit string. The Rukoto. When other amplitude / phase modulation is performed, the number of bits may be different from 4 bits.
In the code block dividing unit 13, the divided blocks are stored in the same subframe, and thus need to be combined as one unit. One group is a bit string represented by Nr (4) × Nc (10) shown in FIG. 7, and the total number of bits is a value corresponding to the transmission parameter notified by the control unit 10. The area indicated by S1, S2, S3, and P2-1 in the first column is data corresponding to one signal point when 16-value QAM modulation is performed. According to the figure, there are 10 columns. Data for 10 signal points are represented.
Next, a method for arranging Nr × Nc bits will be described.
First, the total Nsys (= Nsys1 + Nsys2) of the systematic bit number Nsys1 of the first block and the systematic bit number Nsys2 of the second block is divided by the total number Nc of columns (Nc = Nsys ÷ 4 when performing 16-value QAM modulation), Find the quotient A and the remainder B.
Then, the same number of rows as the obtained quotient A is defined as an area for systematic bits in order from the top.
Next, in order to allocate the remainder B equally to the first block and the second block, B is divided by the number of divided blocks to obtain a quotient B1.
As a result, for the first block, as shown in FIG. 7, B1 regions are defined as regions for systematic bits in order from the first column of the (A + 1) th row in the row direction.
Then, for the second block, as shown in FIG. 7, B2 (B−B1) regions in order from the sixth column of the A + 1th row (the column with the smallest column number as the region of the second block) in the row direction. Is defined as an area for systematic bits.
According to this, the area shown by hatching in FIG. 7 is an area for systematic bits, and the rest is an area for redundant bits.
Next, the systematic bits of the first block are assigned to the area defined as the systematic bits in order from the top in the first row and the first column in the column direction, and when the systematic bit area of the first column is filled, The systematic bits in the second column are filled in order. As a result, control is performed so that the systematic bit is preferentially arranged at the upper bit position.
On the other hand, regarding redundant bits, areas (redundant bit areas) other than the systematic bit area shown in FIG. 3 are assigned in order from the first column. Specifically, if the redundant bit corresponding to U ′ is the first redundant bit and the redundant bit corresponding to U ″ is the second redundant bit, first, the first of the second redundant bits in the first block is the redundant bit. Assigned to the first column of the bit area, then the first of the first redundant bits of the first block is assigned to the second column of the redundant bit area, and then the second of the second redundant bits of the first block Is assigned to the third column. In this way, the redundant bit area is assigned by alternately assigning the second redundant bit and the first redundant bit. In FIG. 7, the arrangement order is clearly indicated by an arrow, and the Nth bit of the Mth redundant bit is clearly indicated by PM-N. For example, the first block data and the second block data that are input can be stored in a memory, and the desired arrangement can be easily achieved by read address control or the like.
The bit string arranged as described above indicates each signal point on the phase plane shown in FIG. 4. For example, (S1, S2, S3, P2-1) = (1, 0, 1, 1 ) Indicates the signal point A as described above.
In the case of assigning bit strings to signal points as shown in FIG. 4, the lower bits of the upper bits in the 4-bit bit sequence are signal points on the receiving side due to phase and amplitude fluctuations during wireless transmission. Although there is a tendency to be prone to error depending on the judgment, referring to FIG. 7, the number of systematic bits that are important bits assigned to the low-order bits (here, the third bit and the fourth bit) that are prone to error. Are two each of the first block and the second block, and are equalized between the blocks. Note that there may be cases where the number of systematic bits in the first block and the second block are not exactly the same, such as a difference of several bits, but it is assumed that there is no such bit difference, and equalization is performed as a whole. In some cases, weighting can be performed so that the higher-order bits are assigned as much as possible in consideration of the bit difference.
In other words, the occupancy rate of predetermined bits (for example, systematic bits) included in the first data block with respect to predetermined bit positions in the bit string (for example, low-order bit positions such as the third and fourth bits that are likely to be erroneous), The occupation ratio of predetermined bits (for example, systematic bits) included in two data blocks is controlled so as to approach.
Although the above is an example in which the number of systematic bits is large and the bits are also arranged in the low-order bits that are error-prone bit positions, the number of systematic bits may be small. In this case, according to the arrangement method shown in this embodiment, it becomes as shown in FIG. The meanings of symbols and the like in FIG. 9 are the same as those described in FIG.
As can be seen from FIG. 9, according to the arrangement method in the present embodiment, the first data for a predetermined bit position in the bit string (for example, the upper bit position where the error is unlikely to occur such as the first and second bits). The occupation rate of predetermined bits (for example, redundant bits) included in the block and the occupation rate of predetermined bits (for example, redundant bits) included in the second data block are controlled so as to approach each other.
Therefore, since the durability (for example, the durability of the same type of bit) at least for the first block bit and the second block bit is equalized, there is a bias that one is high and the other is low. This reduces the overall error occurrence probability.
In addition, with regard to systematic bits, which are important information, the endurance against phase and amplitude fluctuations during wireless transmission approaches between blocks, and error correction processing such as turbo codes allows more errors to be allowed for those with higher endurance Nevertheless, the situation where an error that exceeds the error correction capability occurs in a person with weak durability will be alleviated.
In this embodiment, one CRC calculation result, which is a code for detecting a remainder, is added in common in the first block and the second block in order to reduce redundant bits. When an error is detected by receiving data of one block and second block and performing CRC calculation check, a retransmission request is made and retransmission is performed.
At this time, if the difference in durability against errors is not considered in the first block and the second block as in the conventional case, only the block with the weaker durability has a higher probability of error, and retransmissions frequently occur. If an error detection code is added to each block, an error can be detected for each block, so retransmission can be performed only for the wrong block. Cannot identify an incorrect block and must retransmit the entire plurality of blocks including a code block that is not in error.
However, in this embodiment, since the first block and the second block have the same error tolerance, the occurrence of errors in the first block and the second block is reduced, and a plurality of blocks This is in harmony with the common addition of error detection codes.
In other words, the probability that only one of the first block and the second block is wrong is low, and the probability that both are wrong at the same time or not at the same time is increased. This reduces the consumption of useless wireless resources.
・ Summary
As a summary of the first embodiment, a method for calculating each value used in generalized bit alignment when the number of block divisions is M will be described. Note that <N> means the largest integer less than or equal to N.
A = <Nsys / Nc>
B1 = <(Nsys−A × Nc) ÷ M>
B2 = <(Nsys−A × Nc−B1) ÷ (M−1)>
BL = <{(Nsys−A × Nc− (B1 + B2 +... + B (L−1)))
÷ (M- (L-1))>
BM = Nsys−A × Nc− (B1 + B2 +... + B (M−1))
Note that [N] represents the smallest integer greater than or equal to N.
B1 = [(Nsys−A × Nc) ÷ M]
B2 = [(Nsys−A × Nc−B1) ÷ (M−1)]
BL = [{(Nsys−A × Nc− (B1 + B2 +... + B (L−1)))
÷ M- (L-1)}]
It can also be considered.
As described above, according to the present embodiment, transmission data is divided into two or more bit groups including a first bit group including X bits and a second bit group including Y bits. The bits of the bit group and the bits of the second bit group are arranged at each bit position of a bit string of a predetermined length having a first bit position and a second bit position that is more error-prone than the first bit position. In the bit arrangement method in the bit string generation device for generating a bit string, the bit included in the first bit group and the bit included in the second bit group are arranged with priority over the first bit position, and <N> Is defined as the largest integer less than or equal to N,
(<(X + Y) ÷ L> +1) × (X + Y − <(X + Y) ÷ L> × L) ≦ X (1)
2 ≦ (X + Y − <(X + Y) ÷ L> × L) (2)
In this case, the number of bits included in the first bit group arranged at the second bit position is expressed as X + Y − <(X + Y) ÷ L> × L (3)
The number of bits included in the second bit group arranged at the second bit position is 1 or more.
One embodiment of the method is shown.
According to the conventional arrangement method, when the conditions of (1) and (2) are satisfied, the number of bits included in the first bit group arranged at the second bit position matches the value of (3), and the second The number of bits included in the second bit group arranged at the bit position is 0, and the durability differs greatly between both bit groups (between systematic bits). However, in the cases of (1) and (2), the second bit An example of a method in which the number of bits included in the first bit group arranged at the position is made smaller than the value of (3) and the number of bits contained in the second bit group arranged at the second bit position is 1 or more. According to the first embodiment, the difference in durability between the first bit group and the second bit group is alleviated.
If another expression is used, a 4 × Nc bit string for 16-value QAM is generated by rearranging the data subjected to rate matching processing in a radio base station compatible with HSDPA as in this embodiment. And the data includes at least a first data block and a second data block, and <N> is defined as a maximum integer equal to or less than N, and A = If defined as <Nsys ÷ Nc>, B = Nsys−A × Nc, the bit collection unit continuously organizes bits from the first column to the Nc column for the first row to the Ath row. With regard to the (A + 1) th row, B systematic bits can be arranged without being continuous from the 1st column to the (Nc) th column. To B column Since the organization bits must be arranged continuously up to the eyes, the organization bits can be arranged without continuing from the first column to the Nc column, so the durability between the blocks can be adjusted. is there.
[B] Description of Second Embodiment Next, another method for bit arrangement in the bit collection unit will be described in detail.
This method is characterized in the arrangement method of the remaining bits B of the systematic bits described above.
Specifically, although the surplus bit B is arranged in the (A + 1) th row, the column in which the systematic bits are arranged is
1+ <Nc × (k−1) ÷ (Nsys−A × Nc)>
It is. Here, k = 1, 2,..., Nsys−A × Nc.
For example, if Nsys = 24, the number of redundant bits = 16, Nr = 4, and Nc = 10,
Nr = <24 ÷ 10> = 2,
Column 1 in which systematic bits are arranged = 1 = 1 + <10 × (1-1) ÷ (24−2 × 10)> = 1,
Column 2 in which systematic bits are arranged = 1 = 1 + <10 × (2-1) ÷ (24−2 × 10)> = 3,
Column 3 in which systematic bits are arranged = 1 = 1 + <10 × (3-1) ÷ (24−2 × 10)> = 6,
Column 4 in which systematic bits are arranged = 1 = 1 <10 × (4-1) ÷ (24−2 × 10)> = 8
Therefore, the area indicated by the hatched portion in FIG. 8 is defined as an area where the systematic bits are arranged, and the other areas are areas where redundant bits are arranged. Since the arrangement order in each region is the same as that in the first embodiment, the description thereof is omitted here.
In this embodiment, the remaining systematic bits B are distributed in a predetermined bit position (for example, a lower-order bit position that is less durable against errors than the upper-order bits when performing natural arrangement in 16-value QAM) (for example, Since the bits of the first and second blocks are arranged in order from the left without considering the number of blocks, it is easy to block error tolerance. Can be equalized between.
If the correspondence between the bit string and the signal point is defined so that the upper bits are less resistant to errors than the lower bits, an important bit (for example, systematic bits) is assigned to the lower end with strong durability. It is preferable to arrange the bits as much as possible and to equalize the number of important bits (for example, systematic bits) allocated to the bits having low durability between the blocks.
In the first and second embodiments, 16-level QAM has been described as an example of multi-level modulation, but other multi-level modulation such as 8-phase PSK can also be used.
For example, when a 3-bit bit string is assigned to each signal point as shown in FIG. 11, a difference in endurance against errors occurs at the bit position in the bit string. In the example of FIG. 11, for the first bit and the second bit in the 3-bit bit string, the signs of the two adjacent signal points are both the same as the signs of their own signal points. However, for the third bit, there is no such signal point, and all signal points have at least one of the two adjacent signal points as the sign of their own signal point. It is a different code. For this reason, the inter-code distance for the third bit is generally shorter than the first and second bits, and as a result, the bit position where the third bit is likely to be erroneous with respect to the first and second bits. It has become.
Further, in the case of adopting 64-value QAM, due to the correspondence between the bit string and the signal point, the durability against error easiness is divided into three levels (first bit position, second bit position, first bit position). 3 bit position).
In this case, for a predetermined bit position in the bit string, the bit string is such that the occupation ratio occupied by the predetermined bits included in the first data block is close to the occupation ratio occupied by the predetermined bits included in the second data block. Needless to say, it is preferable that the bit string generation means for controlling the generation of any one of the first bit position, the second bit position, and the third bit position as the predetermined bit position.
It is a figure for showing the channel structure in HSDPA. It is a figure which shows the structure of the base station which supports HSDPA. It is a figure which shows the conventional arrangement | positioning method in the bit collection part. It is a figure which shows one example of each signal point on the phase plane in 16 value QAM modulation. It is a figure which shows the transmitter which concerns on this invention. 3 is a diagram illustrating a configuration of a diffusion processing unit 24. FIG. It is a figure for demonstrating the bit arrangement | positioning method based on this invention. It is a figure which shows the arrangement | positioning method in the conventional bit collection part 6. FIG. It is a figure for demonstrating the bit arrangement | positioning method based on this invention. It is a figure for demonstrating arrangement | positioning of the bit string corresponding to 2nd Example. It is explanatory drawing in the case of using 8-phase PSK.
DESCRIPTION OF SYMBOLS 1 CRC addition part 2 Code block division part 3 Channel encoding part 4 Bit separation part 5 Rate matching part 6 Bit collection part 7 Modulation part 10 Control part 11 CRC addition part 12 Bit scrambling part 13 Code division part 14 Channel encoding part 15 Bit separation unit 16 First rate matching unit 17 Buffer unit 18 Second rate matching unit 19 Bit collection unit 20 Physical channel division unit 21 Interleave processing unit 22 Constellation rearrangement unit 23 Physical channel mapping unit 24 Spreading processing unit 25 Modulation unit 26 Voltage converter
A plurality of bit sequences are generated using the bits included in the first data block and the bits included in the second data block, and the plurality of bit sequences are respectively associated with the signal points on the phase plane. In a transmission device that transmits a signal obtained by performing multi-level modulation according to
The first data block and the second data block are obtained by dividing a data block to which an error detection code is added,
The occupation ratio occupied by the predetermined bits included in the first data block with respect to the predetermined bit positions, which are classified by the degree of error probability in the bit string caused by the correspondence, and the second data block Bit string generation means for controlling the generation so that the occupation ratio occupied by the predetermined bits included is close;
The transmission apparatus according to claim 1, wherein the transmission is performed within the same radio frame.
The bit sequence includes a first bit position and a second bit position that is more susceptible to error than the first bit position due to the correspondence,
The predetermined bit position is the first bit position or the second bit position;
The transmission apparatus according to claim 1.
The first data block and the second data block each include a systematic bit and a redundant bit, and the predetermined bit included in the first data block and the predetermined bit included in the second data block are: Both are organizational bits,
The bit string generation means performs control so that the systematic bits are preferentially arranged at the first bit position in accordance with the control.
The transmission apparatus according to claim 3.
The multilevel modulation is 16-value QAM modulation, the first bit position is upper bits (first bit and second bit), and the second bit position is lower bits (third bit and fourth bit). The transmission device according to claim 3, wherein the transmission device is an eye).
The first data block and the second data block each include a systematic bit and a redundant bit, and the predetermined bit included in the first data block and the predetermined bit included in the second data block are: 2. The transmission apparatus according to claim 1, wherein both are systematic bits or both are redundant bits.
The first data block and the second data block include systematic bits obtained by turbo coding, first redundant bits, and second redundant bits, and predetermined bits included in the first data block; The predetermined bits included in the second data block are both systematic bits, are both redundant bits, are both first redundant bits, or are both second redundant bits. is there,
A receiving device that receives a signal transmitted from the transmitting device performs retransmission control based on an error detection result performed using the error detection code.
A dividing unit that divides the data to which the error detection code is added into N blocks;
An error correction encoding unit that performs error correction encoding processing on each of the N blocks;
Arranging means for arranging N types of systematic bits and redundant bits obtained after the error correction processing in a plurality of bit strings;
A transmission unit that performs transmission after performing amplitude phase modulation corresponding to each signal point on the phase plane indicated by each of the arranged bit strings,
The arrangement means, when the arrangement, when there is a first bit and a second bit having different susceptibility to error in one bit string due to the correspondence between the bit string and the signal point, Equalizing the number of each of the N kinds of systematic bits arranged in the error-prone bit;
A transmission apparatus characterized by the above.
The arrangement means arranges the plurality of bit strings using bits from the first block to the bits included in the Nth block in substantially the order,
The equalization is realized by dispersing a column that allows the systematic bits to be arranged in the error-prone bits.
The transmitter according to claim 9.
A plurality of bit sequences are generated using the bits included in the first data block and the bits included in the second data block, and the plurality of bit sequences are respectively associated with the signal points on the phase plane. In a transmission / reception method between a transmission device that transmits a signal obtained by performing multi-level modulation according to a reception device that receives the signal,
The transmission apparatus occupies a predetermined bit position included in the first data block with respect to a predetermined bit position, which is classified according to the degree of error probability in the bit string caused by the correspondence, Control is performed so that the occupation ratio occupied by the predetermined bits included in the second data block is close,
The receiving device receives the signal that is subjected to the control and transmitted from the transmitting device;
A transmission / reception method characterized by the above.
The first data block and the second data block are transmitted in the same radio frame;
The transmission / reception method according to claim 12.
In accordance with the control, control is performed so that the systematic bit is preferentially arranged at the first bit position.
The transmission / reception method according to claim 14.
The multi-level modulation is 16-value QAM modulation, the first bit position is upper bits (first and second bits), and the second bit position is lower bits (third and fourth bits). 15. The transmission / reception method according to claim 14, wherein:
The first data block and the second data block each include a systematic bit and a redundant bit, and the predetermined bit included in the first data block and the predetermined bit included in the second data block are: 13. The transmission / reception method according to claim 12, wherein both are systematic bits or both are redundant bits.
The first data block and the second data block include systematic bits obtained by turbo encoding, first redundant bits, and second redundant bits, and predetermined bits included in the first data block; The predetermined bits included in the second data block are both systematic bits, are both redundant bits, are both first redundant bits, or are both second redundant bits. is there,
The receiving device requests retransmission to the transmitting device when an error is detected by error detection using the error detecting code transmitted from the transmitting device;
Dividing the data with the error detection code added into N blocks,
An error correction coding process is performed on each of the N blocks,
N types of systematic bits and redundant bits obtained after the error correction processing are arranged in a plurality of bit strings,
After performing amplitude phase modulation corresponding to each signal point on the phase plane indicated by each arranged bit string, a radio signal is transmitted from the transmitter,
In the arrangement, when there are a first bit and a second bit having different susceptibility to error in one bit string due to the correspondence between the bit string and the signal point, N kinds of systematic bits Equalize the number of bits placed on the error-prone bits,
The wireless signal transmitted from the transmitter is received by a receiver and used for error correction decoding.
The plurality of bit strings are arranged using the bits included in the first block to the bits included in the Nth block in substantially the order,
The transmission / reception method according to claim 20.
JP2004035768A 2004-02-12 2004-02-12 Transmitting apparatus and bit arrangement method Active JP4539107B2 (en)
JP2004035768A JP4539107B2 (en) 2004-02-12 2004-02-12 Transmitting apparatus and bit arrangement method
US10/899,068 US7860186B2 (en) 2004-02-12 2004-07-27 Transmitting apparatus with bit arrangement method
EP20100184417 EP2293509B1 (en) 2004-02-12 2004-10-15 Transmitting apparatus with bit arrangement method
EP10184588.1A EP2381636B1 (en) 2004-02-12 2004-10-15 Transmitting apparatus with bit arrangement method
EP10184618.6A EP2375667B1 (en) 2004-02-12 2004-10-15 Transmitting apparatus with bit arrangement method
EP20040256381 EP1564954B1 (en) 2004-02-12 2004-10-15 Transmitting apparatus with bit arrangement method
CN200910145463.6A CN101572588B (en) 2004-02-12 2005-02-08 Transmitting apparatus with bit arrangement method
CNB2005100075812A CN100514900C (en) 2004-02-12 2005-02-08 Transmitting apparatus with bit arrangement method
US12/836,860 US7965791B2 (en) 2004-02-12 2010-07-15 Transmitting apparatus with bit arrangement method
US12/948,341 US8213535B2 (en) 2004-02-12 2010-11-17 Transmitting apparatus with bit arrangement method
US13/032,255 US8085872B2 (en) 2004-02-12 2011-02-22 Transmitting apparatus with bit arrangement method
US13/033,715 US8077800B2 (en) 2004-02-12 2011-02-24 Transmitting apparatus with bit arrangement method
JP2005229319A JP2005229319A (en) 2005-08-25
JP4539107B2 true JP4539107B2 (en) 2010-09-08
ID=34697910
JP2004035768A Active JP4539107B2 (en) 2004-02-12 2004-02-12 Transmitting apparatus and bit arrangement method
US (5) US7860186B2 (en)
EP (4) EP2293509B1 (en)
JP (1) JP4539107B2 (en)
CN (2) CN100514900C (en)
AT553580T (en) * 2005-07-26 2012-04-15 Panasonic Corp Bit-operated conversion diversity for aico picture
CN101238697B (en) 2005-08-05 2011-04-06 松下电器产业株式会社 Wireless communication apparatus and wireless communication method
WO2007029734A1 (en) * 2005-09-06 2007-03-15 Kddi Corporation Data transmitting system and data transmitting method
WO2007074524A1 (en) 2005-12-27 2007-07-05 Fujitsu Limited Digital wireless communication method, transmitter and receiver using multilevel modulation scheme
CN101346918A (en) * 2005-12-27 2009-01-14 松下电器产业株式会社 Radio transmitting apparatus and multicarrier signal generating method
JP4675312B2 (en) * 2006-11-30 2011-04-20 富士通株式会社 Encoding device, decoding device, transmitter, and receiver
EP2192713B1 (en) 2007-09-21 2016-03-09 Fujitsu Limited Transmission method and transmission device
CN102415175A (en) * 2009-04-27 2012-04-11 松下电器产业株式会社 Wireless communication device and wireless communication method
WO2010146694A1 (en) * 2009-06-18 2010-12-23 富士通株式会社 Transmission device and reception device
JP5365455B2 (en) * 2009-09-30 2013-12-11 富士通株式会社 Rate adjustment device, rate adjustment method, and rate adjustment program
CN101783719B (en) * 2010-03-18 2013-03-20 华为技术有限公司 Rate matching and rate de-matching method, device and communication system
EP2629442B1 (en) * 2012-02-14 2014-12-10 Telefonaktiebolaget L M Ericsson (publ) Redundancy version selection based on receiving quality and transport format
JP2002164948A (en) * 2000-09-14 2002-06-07 Texas Instruments Inc Method and device for deciding priority of information protection in high-degree modulation symbol mapping
JP2003023373A (en) * 2001-04-04 2003-01-24 Samsung Electronics Co Ltd Apparatus and method for transmitting/receiving data in code division multiple access mobile communication system
JP2005506756A (en) * 2001-10-15 2005-03-03 シーメンス アクチエンゲゼルシヤフトＳｉｅｍｅｎｓ Ａｋｔｉｅｎｇｅｓｅｌｌｓｃｈａｆｔ Transmission method
JP2005522936A (en) * 2002-04-08 2005-07-28 アイピーワイヤレス，インコーポレイテッド System and method for channel mapping in a wireless communication system
JPH01231446A (en) * 1988-03-11 1989-09-14 Nec Corp Bit error rate measuring instrument for tdma channel
EP1367728A1 (en) * 1999-05-19 2003-12-03 Samsung Electronics Co., Ltd. Turbo interleaving aparatus and method
FR2800947B1 (en) 1999-11-04 2003-01-24 Canon Kk Methods and devices for multi-carrier transmission and reception, and systems using the same
CZ20021752A3 (en) * 2000-09-21 2003-03-12 Matsushita Electric Industrial Co., Ltd Radio transmitting apparatus and method of mapping transmitted signal
WO2003039055A1 (en) 2001-10-15 2003-05-08 Siemens Aktiengesellschaft Method and device for representing the initial base of an encoder in the signal space of a qam or psk modulation
KR100445899B1 (en) * 2001-12-14 2004-08-25 한국전자통신연구원 A turbo code encoder and a code rate decreasing method thereof
KR100984626B1 (en) * 2002-01-07 2010-09-30 지멘스 악티엔게젤샤프트 Method and device for transferring data wherein a bit rate adaptation model is signaled between the transmitter and the receiver
2004-02-12 JP JP2004035768A patent/JP4539107B2/en active Active
2004-07-27 US US10/899,068 patent/US7860186B2/en active Active
2004-10-15 EP EP20100184417 patent/EP2293509B1/en active Active
2004-10-15 EP EP10184588.1A patent/EP2381636B1/en active Active
2004-10-15 EP EP10184618.6A patent/EP2375667B1/en active Active
2004-10-15 EP EP20040256381 patent/EP1564954B1/en active Active
2005-02-08 CN CNB2005100075812A patent/CN100514900C/en active IP Right Grant
2005-02-08 CN CN200910145463.6A patent/CN101572588B/en active IP Right Grant
2010-07-15 US US12/836,860 patent/US7965791B2/en active Active
2010-11-17 US US12/948,341 patent/US8213535B2/en active Active
2011-02-22 US US13/032,255 patent/US8085872B2/en active Active
2011-02-24 US US13/033,715 patent/US8077800B2/en active Active
US8213535B2 (en) 2012-07-03
US20100278282A1 (en) 2010-11-04
EP2381636B1 (en) 2016-03-02
EP2381636A1 (en) 2011-10-26
EP2375667B1 (en) 2016-03-02
EP2293509A1 (en) 2011-03-09
US8085872B2 (en) 2011-12-27
EP2293509B1 (en) 2012-10-10
US7860186B2 (en) 2010-12-28
EP2375667A1 (en) 2011-10-12
CN101572588A (en) 2009-11-04
EP1564954A2 (en) 2005-08-17
US20110142167A1 (en) 2011-06-16
US20110142168A1 (en) 2011-06-16
US20050180363A1 (en) 2005-08-18
US20110058625A1 (en) 2011-03-10
US7965791B2 (en) 2011-06-21
CN101572588B (en) 2014-05-07
JP2005229319A (en) 2005-08-25
EP1564954B1 (en) 2012-01-18
EP1564954A3 (en) 2007-09-05
US8077800B2 (en) 2011-12-13
CN100514900C (en) 2009-07-15
CN1655491A (en) 2005-08-17
US8891354B2 (en) 2014-11-18 Method for multiplexing data and control information
JP5714638B2 (en) 2015-05-07 Data interleaving method and apparatus in mobile communication system
JP5929989B2 (en) 2016-06-08 Multi-carrier mobile communication system
US9917674B2 (en) 2018-03-13 System and method for adapting code rate
JP2015144480A (en) 2015-08-06 Method of receiving code blocks, method of channel interleaving, iterative operation method of receiver, and receiver
JP5674061B2 (en) 2015-02-25 Apparatus and method for mapping symbols to resources in a mobile communication system
KR100925444B1 (en) 2009-11-06 A method for transmitting uplink siganl including data and control inforamtion via uplink channel
DE10250867B4 (en) 2010-07-08 A transceiver and method for packet retransmission in a mobile communication system
KR100586343B1 (en) 2006-06-08 Improved turbo code based incremental redundancy
US8634345B2 (en) 2014-01-21 Uplink control information (UCI) multiplexing on the physical uplink shared channel (PUSCH)
JP4353774B2 (en) 2009-10-28 Data transmission method and data reception method, and transmission apparatus and reception apparatus using them
KR101503059B1 (en) 2015-03-19 Apparatus and method for channel encoding and decoding in communication system using low-density parity-check codes
CN101807974B (en) 2015-05-20 System and method for transferring ascending control signals on physical upstream sharing channel
Ref document number: 4539107