Source: http://www.google.com/patents/US6809375?dq=4182933
Timestamp: 2014-03-17 20:17:35
Document Index: 602930722

Matched Legal Cases: ['art 16', 'arts 16', 'arts 12', 'arts 13', 'arts 12', 'arts 13', 'arts 44', 'arts 12', 'arts 13', 'arts 44']

Patent US6809375 - Semiconductor device having shallow trenches and method for manufacturing ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the withstand voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively...http://www.google.com/patents/US6809375?utm_source=gb-gplus-sharePatent US6809375 - Semiconductor device having shallow trenches and method for manufacturing the sameAdvanced Patent SearchPublication numberUS6809375 B2Publication typeGrantApplication numberUS 10/112,056Publication dateOct 26, 2004Filing dateApr 1, 2002Priority dateApr 2, 2001Fee statusPaidAlso published asEP1248300A2, EP1248300A3, US7397082, US20020153558, US20050017294Publication number10112056, 112056, US 6809375 B2, US 6809375B2, US-B2-6809375, US6809375 B2, US6809375B2InventorsToshiyuki Takemori, Masato Itoi, Yuji WatanabeOriginal AssigneeShindengen Electric Manufacturing Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (7), Referenced by (14), Classifications (20), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device having shallow trenches and method for manufacturing the sameUS 6809375 B2Abstract The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the withstand voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer 18. The thickness of a bottom surface part 16 of a gate electrode film 11 is formed so as to be thicker than other parts of the gate electrode film 11. Also, when a P type body layer 19 is formed, an interface between the P type body layer 19 and an N-epitaxial layer 18 is located at a deeper position than a bottom end of the gate electrode film 11. Images(29) Claims(12)
a semiconductor substrate, in which a drain layer of a first conductivity type and a conductive region of a second conductivity type opposite to the first conductivity type are formed with the conductive region over the drain layer; a trench formed in the conductive region, wherein said trench reaches the drain layer; a source region of the first conductivity type, wherein said source region is positioned inside the conductive region, with at least part of the source region being exposed to inner surfaces of the trench; a gate insulating film that is formed on the inner surfaces of the trench; a gate electrode that is formed on inner surfaces of the gate insulating film; and a source electrode that is insulated from the gate electrode and is connected to the source region; wherein the inner surface of the gate insulating film at a bottom of the trench is deeper than the source region but shallower than an interface between the drain layer and the conductive region. 2. A semiconductor device, comprising:
a semiconductor substrate, in which a drain layer of a first conductivity type and a conductive region of a second conductivity type opposite to the first conductivity type are formed with the conductive region over the drain layer; a trench formed in the conductive region, wherein said trench reaches the drain layer but does not extend through an entire thickness of said drain layer; a source region of the first conductivity type, wherein said source region is positioned inside the conductive region, with at least part of the source region being exposed to inner surfaces of the trench; a gate insulating film that is formed on the inner surfaces of the trench so that parts of the gate insulating film that are located beyond a predetermined depth are thicker than other parts of the gate insulating film; a gate electrode that is formed on inner surfaces of the gate insulating film; and a source electrode that is insulated from the gate electrode and is connected to the source region; wherein the predetermined depth is in a range that is deeper than the source region but is shallower than an interface between the drain layer and the conductive region. 3. The semiconductor device according to claim 2, wherein a depth of said trench in the conductive region is greater than in the drain layer.
4. The semiconductor device according to claim 3, wherein, in the conductive region and the drain layer, said gate electrode has first and second dimensions measured in a thickness direction of said trench, respectively, and the first dimension is greater than the second dimension.
a semiconductor substrate, in which a drain layer of a first conductivity type and a conductive region of a second conductivity type opposite to the first conductivity type are formed with the conductive region over the drain layer; a trench formed in the conductive region, wherein said trench reaches the drain layer; a source region of the first conductivity type, wherein said source region is positioned inside the conductive region, with at least part of the source region being exposed to inner surfaces of the trench; a gate insulating film that is formed on the inner surfaces of the trench, wherein a thickness of the gate insulating film decreases towards the source region; a gate electrode that is formed on inner surfaces of the gate insulating film; and a source electrode that is insulated from the gate electrode and is connected to the source region; wherein the gate electrode has a curved surface facing the gate insulating film; and wherein a depth of said trench in the conductive region is greater than in the drain layer. 6. The semiconductor device according to claim 5, wherein, in the conductive region and the drain layer, said gate electrode has first and second dimensions measured in a thickness direction of said trench, respectively, and the first dimension is greater than the second dimension.
a substrate; an epitaxial layer of a first conductivity type formed on top of said substrate; a body layer of a second conductivity type opposite to the first conductivity type formed on top of said epitaxial layer; a trench formed in the body layer, wherein said trench reaches the epitaxial layer; a source region of the first conductivity type formed on said body layer, with at least part of the source region being exposed to inner surfaces of the trench; a gate insulating film that is formed on the inner surfaces of the trench; a gate electrode that is formed within said trench and electrically isolated from said epitaxial layer, said body layer and said source region by the gate insulating film; and a source electrode that is insulated from the gate electrode and connected to the source region; wherein a lowermost end face of said gate electrode is spaced from a first interface between the body layer and the epitaxial layer and a second interface between the epitaxial layer and the substrate by first and second distances, respectively, said distances being measured in a thickness direction of said trench, and the first distance is smaller than the second distance; and wherein the gate electrode ends at a level above the interface between the body layer and the epitaxial layer. 8. A semiconductor device, comprising:
a substrate; an epitaxial layer of a first conductivity type formed on top of said substrate; a body layer of a second conductivity type opposite to the first conductivity type formed on top of said epitaxial layer; a trench formed in the body layer, wherein said trench reaches the epitaxial layer; a source region of the first conductivity type formed on said body layer, with at least part of the source region being exposed to inner surfaces of the trench; a gate insulating film that is formed on the inner surfaces of the trench; a gate electrode that is formed within said trench and electrically isolated from said epitaxial layer, said body layer and said source region by the gate insulating film; and a source electrode that is insulated from the gate electrode and connected to the source region; wherein a lowermost end face of said gate electrode is spaced from a first interface between the body layer and the epitaxial layer and a second interface between the epitaxial layer and the substrate by first and second distances, respectively, said distances being measured in a thickness direction of said trench, and the first distance is smaller than the second distance; wherein a width of the gate electrode, as measured in a direction perpendicular to a thickness direction of said trench, increases towards the source region; and wherein the gate electrode has a step-wise profile. 9. A semiconductor device, comprising:
a substrate; an epitaxial layer of a first conductivity type formed on top of said substrate; a body layer of a second conductivity type opposite to the first conductivity type formed on top of said epitaxial layer; a trench formed in the body layer, wherein said trench reaches the epitaxial layer; a source region of the first conductivity type formed on said body layer, with at least part of the source region being exposed to inner surfaces of the trench; a gate insulating film that is formed on the inner surfaces of the trench; a gate electrode that is formed within said trench and electrically isolated from said epitaxial layer, said body layer and said source region by the gate insulating film; and a source electrode that is insulated from the gate electrode and connected to the source region; wherein a lowermost end face of said gate electrode is spaced from a first interface between the body layer and the epitaxial layer and a second interface between the epitaxial layer and the substrate by first and second distances, respectively, said distances being measured in a thickness direction of said trench, and the first distance is smaller than the second distance; wherein a width of the gate electrode, as measured in a direction perpendicular to a thickness direction of said trench, increases towards the source region; and wherein a depth of said trench in the body layer is greater than in the epitaxial layer. 10. The semiconductor device according to claim 9, wherein the trench does not extend into the substrate.
a substrate; an epitaxial layer of a first conductivity type formed on top of said substrate; a body layer of a second conductivity type opposite to the first conductivity type formed on top of said epitaxial layer; a trench formed in the body layer, wherein said trench reaches the epitaxial layer; a source region of the first conductivity type formed on said body layer, with at least part of the source region being exposed to inner surfaces of the trench; a gate insulating film that is formed on the inner surfaces of the trench; a gate electrode that is formed within said trench and electrically isolated from said epitaxial layer, said body layer and said source region by the gate insulating film; and a source electrode that is insulated from the gate electrode and connected to the source region; wherein a lowermost end face of said gate electrode is spaced from a first interface between the body layer and the epitaxial layer and a second interface between the epitaxial layer and the substrate by first and second distances, respectively, said distances being measured in a thickness direction of said trench, and the first distance is smaller than the second distance; and wherein a depth of said trench in the body layer is greater than in the epitaxial layer. 12. The semiconductor device according to claim 11, wherein the trench does not extend into the substrate.
Trench gate power MOSFETs have been widely used in recent years in a variety of power supply apparatuses, such as DC�DC converters. FIGS. 51A and 51B show one example of a semiconductor device that has a trench gate power MOSFET construction according to the background art, with FIG. 51A being an overhead view of the semiconductor device and FIG. 51B being a cross-sectional view taken along the line A�A in FIG. 51A. In these drawings, numerals 100 a to 100 e are cells, numeral 110 is a trench, numeral 111 is a gate electrode film, numeral 117 is an N+ type silicon substrate, numeral 118 is an N− epitaxial layer, numeral 119 is a P type body layer, numeral 120 is a P+type dispersion region, numeral 121 is an N+type source region, numeral 122 is an interlayer dielectric, numeral 124 is a source electrode film, numeral 125 is a drain electrode film, numeral 127 is a gate insulating film, and numeral 141 is an upper insulating film.
As shown by the cells 100 a to 100 e in FIG. 51A, the present semiconductor device is formed with a large number of cells that are arranged in a hound's-tooth check-like pattern on the surface of the semiconductor device. As shown by cell 100 a, for example, each cell is formed with an N+type source region 121 surrounding a P+type dispersion region.
As shown in FIG. 51B, the cross-sectional form of the present semiconductor device is such that an N− epitaxial layer 118 is formed on top of an N+ type silicon substrate 117, with a P type body layer 119 being formed on top of the N− epitaxial layer 118. P+type dispersion regions 120 and N+type source regions 121 are formed in this P type body layer 119. Trenches 110 that pass through the P type body layer 119 and are deep enough to reach into the N− epitaxial layer 118 are also formed between the cells 100 a to 100 e. The trenches 110 provide an opening to the P type body layer 119 and reach into the N− epitaxial layer 118. A gate insulating film 127 is formed on the side surfaces and bottom surfaces of these trenches 110, with a gate electrode film 111 being formed in the spaces surrounded by the gate insulating film 127. An upper insulating film 141 is formed on top of the gate insulating film 127 and the gate electrode film 111. An interlayer dielectric 122 is also formed on top of the upper insulating film 141 and parts of the N+type source region 121.
A source electrode film 124 is formed on top of the P+type dispersion region 120, the N+ type source region 121, and the interlayer dielectric 122. A drain electrode film 125 is also formed on the other surface of the N+ type silicon substrate 117.
On the other hand, with a semiconductor device of the above construction, the trenches 110 have to be deeply formed in order to make the bottom parts of the gate insulating film 127 thicker than the other parts and so ensure that a suitable withstand voltage is achieved for the gate insulating film 127. For this purpose, as shown in FIG. 51B, the trenches 110 are produced with a large depth D so as to provide sufficient space for making the bottom parts of the gate insulating film 127 thick. If the trenches 110 are deeply formed, an increase can be made in the area of the outer surface of the gate insulating film 127, making it possible to reduce the On resistance Ron.
SUMMARY OF THE INVENTION To solve the problems mentioned above, the present invention has an object of providing a semiconductor device for which the capacitance between the gate electrode film and the drain layer can be reduced while keeping the On resistance low and the withstand voltage of the gate insulating film at a sufficient level.
To achieve the stated object, the present invention is a semiconductor device, including: a semiconductor substrate, in which a drain layer of a first conductivity type and a conductive region of an opposite conductivity-type to the first conductivity type are formed with the conductive region over the drain layer; a trench formed as an opening in the conductive region that reaches the drain layer; a source region of the first conductivity type that is positioned inside the conductive region, with at least part of the source region being exposed to inner surfaces of the trench; a gate insulating film that is formed on the inner surfaces of the trench so that an upper surface of the gate insulating film at a bottom of the trench is deeper than the source region but is shallower than an interface between the drain layer and the conductive region; a gate electrode film that is formed on inner surfaces of the gate insulating film; and a source electrode film that is insulated from the gate electrode film and is connected to the source region.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B show a semiconductor device according to the first embodiment of the present invention, with
FIG. 1A being an overhead view showing the arrangement of cells in the semiconductor device and
FIG. 1B being a cross-sectional view taken along the line B�B.
FIG. 16 is a cross-sectional view (view (l)) illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
FIGS. 51A and 51B show an example of a trench gate power MOSFET-type semiconductor device according to the background art, with FIG. 51A being an overhead view of the semiconductor device and FIG. 51B being a cross-sectional view taken along the line A�A.
The following is a detailed description, with reference to the attached drawings, of a semiconductor device that is a first embodiment of the present invention. FIGS. 1A and 1B show a semiconductor device of this first embodiment of the present invention, with FIG. 1A being an overhead view showing the arrangement of the cells of the semiconductor device and FIG. 1B being a cross-sectional view taken along the line B�B in FIG. 1A. In these drawings, numerals 1 a to 1 e are cells, numeral 10 is a trench, numeral 11 is a gate electrode film, numeral 15 is a side surface part, numeral 16 is a bottom surface part, numeral 17 is an N+ type silicon substrate, numeral 18 is an N− epitaxial layer, numeral 19 is a P type body layer, numeral 20 is a P+type dispersion region, numeral 21 is an N+type source region, numeral 22 is an interlayer dielectric, numeral 24 is a source electrode film, numeral 25 is a drain electrode film, numeral 27 is a gate insulating film, and numeral 41 is an upper insulating film.
As shown in FIG. 1B, the cross-sectional form of the present semiconductor device is such that an N− epitaxial layer 18 is formed on top of an N+ type silicon substrate 17, with a P type body layer 19 being formed on top of the N− epitaxial layer 18. The cell 1 a is produced with a P+type dispersion region 20 and an N+type source region 21 being formed in this P type body layer 19.
An interlayer dielectric 22 is also formed on top of the gate insulating film 27. A source electrode film 24 is formed on top of the P+type dispersion region 20, the N+ type source region 21, and the interlayer dielectric 22. A drain electrode film 25 is also formed on the other surface of the N+ type silicon substrate 17.
In the semiconductor device of this first embodiment of the present invention, the gate electrode film 11 is located so as to be shallower than the interface between the N− epitaxial layer 18 and the P type body layer 19, or in other words, the lower tip of the gate electrode film 11 is positioned above the interface between the N− epitaxial layer 18 and the P type body layer 19. As a result, even if the trenches 10 are formed so as to reach a relatively shallow position in the N− epitaxial layer 18, it is still possible to make the bottom surface parts 16 of the gate insulating film 27 thick enough to ensure that the withstand voltage of the gate insulating film 27 is sufficiently high. Since the trenches 10 are not deeply formed, problems such as the concentration of an electric field at a specific part of the gate insulating film 27 can be avoided.
Next, as shown in FIG. 11, vapor depositing is performed, and a silicon oxide film 51 is formed on the inner surfaces of the trench 10 and on the upper surface of the N− epitaxial layer 18.
Next, as shown in FIG. 12, by performing etching back by anisotropic etching of the silicon oxide film 51, the silicon oxide film above the N− epitaxial layer 18 and inside the trench is removed, leaving remains of silicon oxide film 51 in the bottom part of the trench in a part deeper than a predetermined depth.
After this, as shown in FIG. 15, dry-etching is performed to remove all of the polysilicon film 43 from the top of the silicon oxide film 52 and to remove the polysilicon film 43 from the insides of the trenches 10 up to a position that is slightly deeper than the surface of the N− epitaxial layer 18. As a result of this process, the gate electrode film 11 is formed on the inside of the trenches 10. Next, as shown in FIG. 16, dry-etching is performed so that all of the silicon oxide film 52 is removed from the top of the N− epitaxial layer 18 and the gate insulating film (silicon oxide film) 52 is removed up to a position that is slightly deeper than the upper surface of the gate electrode film 11.
After this, as shown in FIG. 17, a thermal oxidizing process is performed so that a silicon oxide film 41 is formed on the N− epitaxial layer 18, the gate electrode film 11, and the silicon oxide film 52. Boron ions (B+) are implanted into and dispressed within the N− epitaxial layer 18 to form the P type body layer 19. At this point, the interface between the N− epitaxial layer 18 and the P type body layer 19 is set so as to be at a deeper position than the deepest part of the gate electrode 11. Next, as shown in FIG. 18, a photoresist is applied to the entire surface of the silicon oxide film 41, with this then being exposed to light and developed so as to form the photoresist film 45. After this, the photoresist film 45 is used as a mask and boron ions (B+) are implanted into the P type body layer 19. After the photoresist film 45 has been removed, a heat treatment is performed so as to disperse the boron ions (B+) in the P type body layer 19, resulting in the formation of the P+ type dispersed regions 20.
Finally, as shown in FIG. 21, aluminum is sputtered onto the surfaces of the interlayer dielectric 22 and the P type body layer 19 so as to form an aluminum film. A photoresist is then applied, exposed to light and developed. Unnecessary parts (not shown in the drawing) are then removed by dry-etching to form a source electrode film 24. Also, a drain electrode film 25 is formed on the rear surface of the N+ type silicon substrate 17 by forming a metal thin film using vapor deposition.
With the above manufacturing process, it is easy to form a gate electrode film 11 whose bottom part is shallower than the interface between the interface between the N− epitaxial layer 18 and the P type body layer 19. It should be noted that while the N− epitaxial layer 18 is produced in the above process through an epitaxial growth, the N− epitaxial layer 18 may be formed by a surface diffusion method. Also, while the source electrode film 24 is described as being formed of aluminum, a different metal, such as copper, may be used.
FIG. 25 shows a second experimental example of the semiconductor device according to the second embodiment of the present invention. In FIG. 25, the variable Z is the difference in thickness in the horizontal direction between the gate electrode film upper parts 12 and the gate electrode film lower parts 13. It should be noted that the other numerals are the same as in FIG. 3. In the experimental example shown in FIG. 25, the variable A was set at 0.8 μm, the variable B was set at 1.3 μm, the variable C was set at 1.6 μm, the variable T1 was set at 50 nm, and the variable T2 was set at 0.25 μm. As a result, in this experimental example, the lower tips of the gate electrode film upper parts 12 are positioned above the interface between the N− epitaxial layer 18 and the P type body layer 19, while the lower tips of the gate electrode film lower parts 13 are positioned below this interface. For this construction, the same voltages as in the experiment shown in FIG. 3 were applied between the source electrode film 24 and the drain electrode film 25 and between the gate electrode film 11 and the source electrode film 24.
Next, as shown in FIG. 36, anisotropic etching is performed on the N− epitaxial layer 18 that is exposed at the bottom surfaces of the trenches 35, so that the trenches 35 extend deeper into the N− epitaxial layer 18. The digging of the trenches is complete at this point, with the resulting trenches being in the form of the trenches 10. After this, as shown in FIG. 37, a thermal oxidizing process is performed so that the N− epitaxial layer 18 that is exposed at the bottom of the trenches 10 is oxidized.
After this, as shown in FIG. 42, dry-etching is performed to remove all of the polysilicon film 43 from the top of the silicon oxide film 31 and to remove the polysilicon film 43 from the insides of the trenches 10 up to a position that is slightly deeper than the surface of the N− epitaxial layer 18. As a result of this process, the gate electrode film 11 is formed on the inside of the trenches 10. Also, due to the presence of the stepped parts 44 in the trenches 10, the gate electrode film upper parts 12 are thicker than the gate electrode film lower parts 13. Next, as shown in FIG. 43, dry-etching is performed so that all of the silicon oxide film 31 is removed from the top of the N− epitaxial layer 18 and the gate insulating film (silicon oxide film) 42 is removed up to a position that is slightly deeper than the upper surface of the gate electrode film 11.
After this, as shown in FIG. 44, a thermal oxidizing process is performed so that a silicon oxide film 41 is formed on the N− epitaxial layer 18, the gate electrode film 11, and the silicon oxide film 42. Boron ions (B+) are implanted into and dispsressed within the N− epitaxial layer 18 to form the P type body layer 19. At this point, the interface between the N− epitaxial layer 18 and the P type body layer 19 is set so as to be at a deeper position than the stepped parts 44 of the trenches 10. Next, as shown in FIG. 45, a photoresist is applied to the entire surface of the silicon oxide film 41, with this then being exposed to light and developed so as to form the photoresist film 45. After this, the photoresist film 45 is used as a mask and boron ions (B+) are implanted into the P type body layer 19. After the photoresist film 45 has been removed, a heat treatment is performed so as to disperse the boron ions (B+) in the P type body layer 19, resulting in the formation of the P+ type diffused regions 20.
Finally, as shown in FIG. 48, aluminum is sputtered onto the surfaces of the interlayer dielectric 22 and the P type body layer 19 so as to form an aluminum film. A photoresist is then applied, exposed to light and developed. Unnecessary parts (not shown in the drawing) are then removed by dry-etching to form a source electrode film 24. Also, a drain electrode film 25 is formed on the rear surface of the N+ type silicon substrate 17 by forming a metal thin film using vapor deposition.
With the above manufacturing process, it is easy to form a gate electrode film 11 whose upper parts and lower parts have different thicknesses. It should be noted that while the N− epitaxial layer 18 is produced in the above process through an epitaxial growth, the N− epitaxial layer 18 may be formed by a surface diffusion method. Also, while the source electrode film 24 is described as being formed of aluminum, a different metal, such as copper, may be used.
According to the present invention as described above, the lower tip of the gate electrode film is positioned so as to be deeper than the source region but shallower than an interface between the drain layer and the conductive region. This makes it possible to reduce the capacitance between the gate electrode film and the drain layer while keeping the On resistance low and the withstand voltage of the gate insulating film at a sufficient level.
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