Source: http://www.google.com/patents/US20040066617?dq=5251294
Timestamp: 2014-07-22 19:47:31
Document Index: 130643593

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Patent US20040066617 - Circuit board device and its manufacturing method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsThis invention is a circuit board device having a filter element. It has a base board (4), a circuit part (2) mounted on the base board (4), a filter element (5) arranged between the circuit part (2) and the base board (4), and a semiconductor component (3) mounted on the same plate as the circuit part...http://www.google.com/patents/US20040066617?utm_source=gb-gplus-sharePatent US20040066617 - Circuit board device and its manufacturing methodAdvanced Patent SearchPublication numberUS20040066617 A1Publication typeApplicationApplication numberUS 10/467,473PCT numberPCT/JP2002/012723Publication dateApr 8, 2004Filing dateDec 4, 2002Priority dateDec 13, 2001Also published asCN1270403C, CN1491448A, US7187559, WO2003050909A1Publication number10467473, 467473, PCT/2002/12723, PCT/JP/2/012723, PCT/JP/2/12723, PCT/JP/2002/012723, PCT/JP/2002/12723, PCT/JP2/012723, PCT/JP2/12723, PCT/JP2002/012723, PCT/JP2002/12723, PCT/JP2002012723, PCT/JP200212723, PCT/JP2012723, PCT/JP212723, US 2004/0066617 A1, US 2004/066617 A1, US 20040066617 A1, US 20040066617A1, US 2004066617 A1, US 2004066617A1, US-A1-20040066617, US-A1-2004066617, US2004/0066617A1, US2004/066617A1, US20040066617 A1, US20040066617A1, US2004066617 A1, US2004066617A1InventorsTakayuki Hirabayashi, Akihiko OkuboraOriginal AssigneeTakayuki Hirabayashi, Akihiko OkuboraExport CitationBiBTeX, EndNote, RefManReferenced by (66), Classifications (44), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetCircuit board device and its manufacturing methodUS 20040066617 A1Abstract This invention is a circuit board device having a filter element. It has a base board (4), a circuit part (2) mounted on the base board (4), a filter element (5) arranged between the circuit part (2) and the base board (4), and a semiconductor component (3) mounted on the same plate as the circuit part (2) on the base board (4). The semiconductor component (3) is mounted on a thin plate region (17) that is thinner than a thick plate region (16) having its thickness increased by mounting the circuit part (2) on the base board (4). Thus, the thickness of the whole circuit board device is reduced and the filter element (5) is covered with a sufficiently thick dielectric insulating material so as to prevent deterioration in filter characteristic. Images(13) Claims(5)
BEST MODE FOR CARRYING OUT THE INVENTION [0040] An embodiment of the present invention will now be described in detail with reference to the drawings. [0041] A circuit board device 1 to which the present invention is applied, shown in FIGS. 6 and 7, constitutes a high-frequency circuit used in a transmitting/receiving unit provided in a portable communication terminal device or the like and adapted for processing a high-frequency signal. The circuit board device 1 has a structure in which a circuit part 2 and a semiconductor component 3 are electrically connected to and mounted on a major surface (hereinafter referred to as mounting surface) 4 a of a base board 4, for example, by a flip-chip bonding method using solder, and a filter element 5 is arranged between the circuit part 2 and the base board 4. [0042] The circuit part 2 is constructed as plural insulating layers 6 made of a dielectric insulating material and plural patterned wiring layers 7 are alternately stacked. Electric interlayer connection is made by a via-hole 8 penetrating all the plural wiring layers 7 or penetrating the upper and lower layers. [0043] As will be later described in detail, the circuit part 2 is formed as the insulating layers 6 and the wiring layers 7 are sequentially stacked via a peeling layer 21 on a dummy board 20 having a flat major surface and are peeled from the dummy board 20 by the peeling layer 21. Therefore, the structure of the circuit part 2 need not use a core board such as a glass board or an Si board. The dummy board 20 is reused when necessary. [0044] In the circuit part 2, the insulating layers 6 are made of a dielectric insulating material having low Tanδ at a low dielectric constant, that is, having an excellent high-frequency characteristic. Specifically, a mixture of an organic material such as polyphenylene ether (PPE), bismaleidetriazine (BT-resin), polytetrafluoroethylene, polyimide, liquid crystal polymer (LCP), polynorbornene (PNB), phenol resin, or polyolefin resin, and an inorganic material such as ceramics, or a mixture of an organic material such as glass epoxy and an inorganic material is used. [0045] The wiring layers 7 forming the circuit part 2 are pattern wirings formed by conductors made of, for example, copper or nickel plate with gold. The wiring layers 7 are formed, for example, by print processing or lithography processing. [0046] The semiconductor component 3 is a functional circuit element such as a semiconductor chip or an LSI (large-scale integrated circuit) chip and is mounted on the mounting surface 4 a of the base board 4, for example, by a flip-chip bonding method using an element bump part 9. This semiconductor component 3 is mounted on the same plate as the circuit part 2 mounted on the mounting surface 4 a of the base board 4, that is, parallel to the circuit part 2 on the base board 4. [0047] The base board 4 has a structure in which plural insulating layers 10 and plural wiring layers 11 are alternately stacked, and interlayer connection is made by a via-hole 12 penetrating all the plural wiring layers 11 or penetrating plural layers of them. The base board 4 has plural input/output terminal parts 13 on its front and back major surfaces. These input/output terminal parts 13 function, for example, as connection terminals to an external power source, or as bases of electric connection parts for mounting the circuit part 2 and the semiconductor component 3. The plural wiring layers 11 provided in the base board 4 function as wirings for transmitting power, control signals and high-frequency signals supplied from the input/output terminal parts 13 to the circuit part 2 and also function as ground (ground electrodes). [0048] In base board 4, similarly to the circuit part 2, a dielectric insulating material having low Tanδ at a low dielectric constant, that is, having an excellent high-frequency characteristic, is used for the insulating layers 10. Specifically, a mixture of an organic material such as polyphenylene ether (PPE), bismaleidetriazine (BT-resin), polytetrafluoroethylene, polyimide, liquid crystal polymer (LCP), polynorbornene (PNB), phenol resin, or polyolefin resin, and an inorganic material such as ceramics, or a mixture of an organic material such as glass epoxy and an inorganic material is used. [0049] The wiring layers 11 provided in the base board 4, similar to those in the circuit part 2, are pattern wirings formed by conductors made of, for example, copper or nickel plate with gold. The wiring layers 11 are formed, for example, by print processing or lithography processing. The base board 4 is manufactured through a typical multilayer wiring board manufacturing process. [0050] In the filter element 5, a pair of resonator conductor patterns 14 as a part of the wiring layers 7 are arranged to be exposed on a surface (hereinafter referred to as counter-surface) 2 a facing the mounting surface 4 a of the base board 4 of the circuit part 2. Specifically, as the filter element 5, a BPF having a structure in which a ground part 15 a provided in a part of the wiring layer 7 that is second from the mounting surface 4 a of the base board 4 of the circuit part 2 and a ground part 15 b provided in a part of the input/output terminal parts 13 exposed on the mounting surface 4 a of the base board 4 shield the pair of resonator conductor patterns 14 exposed on the counter-surface 2 a of the circuit part 2, that is, a so-called tri-plate structure, extends onto the circuit part 2 and the base board 4. This filter element 5 may be one of a low-pass filter (LPF), a high-pass filter (HPF) and a band-pass filter (BPF). [0051] In the circuit board device 1 of this structure, the circuit part 2 is mounted on the mounting surface 4 a of the base board 4 so that the circuit part 2 and base board 4 hold the pair of resonator conductor patterns 14 of the filter element 5. The thick part where the circuit part 2 is mounted on the base board 4 is a so-called thick plate region 16, whereas the part where the circuit part 2 is not mounted on the base board 4 and that is thinner than the thick plate region 16 is a thin plate region 17. [0052] In this circuit board device 1, the semiconductor component 3 is mounted parallel to the circuit part 2 on the mounting surface 4 a of the base board 4, that is, on the thin plate region 17. The thickness of the whole body including the semiconductor component 3 is made thin. [0053] In the circuit board device 1, the resonator conductor patterns 14 of the filter element 5 are arranged in an inner layer of the thick plate region 16, that is, between the circuit part 2 and the base board 4, and the circuit part 2 and the base board 4 have the insulating layers 6 and 10 made of a dielectric insulating material over multiple layers. Thus, the resonator conductor patterns 14 of the filter element 5 can be covered with the sufficiently thick dielectric insulating material. Therefore, in the circuit board device 1, the thick dielectric insulating material covers the pair of resonator conductor patterns 14 of the filter element 5 and causes no deterioration in degree of electromagnetic coupling between the pair of resonator conductor patterns 14, thereby preventing deterioration in filter characteristic due to reduction in thickness of the dielectric insulating material covering the filter element 5. [0054] In the circuit board device 1 to which the present invention is applied, since the circuit part 2, which is relatively expensive, is mounted only in a necessary part instead of the entire mounting surface 4 a of the base board 4, reduction in cost is realized. [0055] In the circuit board device 1 to which the present invention is applied, different dielectric insulating materials may be used for the insulating layers 6 and the insulating layers 10, respectively. For example, in the circuit board device 1, if a dielectric insulating material having a high dielectric constant is used for the insulating layers 10 of the base board 4, miniaturization is realized by reduction in size of the resonator conductor patterns 14 of the filter element 5. If a dielectric insulating material having a low dielectric constant is used for the insulating layers 10, the loss of parasitic capacitance in the filter element 5 can be reduced. In the circuit board device 1, if a head-resistant dielectric insulating material is used for the insulating layers 6 of the circuit part 2, a passive element such as a capacitor element, a register element, or an inductor element can be provided at a part of the wiring layers 7 of the circuit part 2. [0056] A method for manufacturing the above-described circuit board device 1 will now be described. [0057] To manufacture the circuit board device 1, the circuit part 2 is formed first. When forming the circuit part 2, the dummy board 20 having the peeling layer 21 formed on its major surface 20 a is prepared, as shown in FIG. 8. For the dummy board 20, for example, a glass board, a quartz board or a silicon board having high heat resistance and a highly flattened major surface is used. The peeling layer 21 includes a metal film 21 a of copper, aluminum or the like deposited to a thickness of approximately 1000 Å evenly over the entire major surface 20 a of the dummy board 20 by a sputtering method or a chemical vapor deposition (CVD) method, and a resin film 21 b of polyimide resin or the like deposited to a thickness of approximately 1 to 2 μm over the entire metal film 21 a by a spin coat method. [0058] On the peeling layer 21, a first insulating layer 22 with an even thickness is formed, as shown in FIG. 9. The first insulating layer 22 is formed as a typically known dielectric insulating material as described above in the conventional wiring board manufacturing process is applied onto the peeling layer 21, for example, by a spin coat method, a curtain coat method, a roll coat method, a dip coat method or the like. [0059] Next, in the first insulating layer 22, an aperture 22 a to be the via-hole 8 is formed at a predetermined position by pattern processing. In the case a photosensitive dielectric insulating material is used for the first insulating layer 22, the aperture 22 a is formed by patterning processing using a photolithography technique. In the case a non-photosensitive dielectric insulating material is used for the first insulating layer 22, the aperture 22 a is formed by patterning processing based on dry etching or laser processing using a photoresist and a mask of aluminum or the like. [0060] Next, in the first insulating layer 22, a wiring groove 23 is formed by etching processing, as shown in FIG. 10. An etching mask having an aperture corresponding to the wiring groove 23 is formed on the first insulating layer 22, then dry etching using a reactive ion etching (RIE) method with oxygen plasma is performed in the region except for the etching mask on first insulating layer 22, and then the etching mask is removed. Thus, the wiring groove 23 is formed. [0061] Next, on the first insulating layer 22 having the wiring groove 23 formed therein, a metal plating layer 24 is formed by metal plating processing, as shown in FIG. 11. The metal plating layer 24 is made of a highly conductive metal such as copper. The metal plating processing may be electroplating or electroless plating. The metal plating layer 24 fills the entire major surface of the first insulating layer 22 where the wiring groove 23 is formed and the aperture 22 a, so that the thickest part of the metal plating layer 24 is thicker than the thickest part of the first insulating layer 22. When the metal plating layer 24 is formed by electroplating, the metal film 21 a of the peeling layer 21 functions as a voltage applying electrode. [0062] Next, as flattening processing of the metal plating layer 24 is performed until the first insulating layer 22 is exposed, a first wiring layer 25 embedded in the first insulating layer is formed on the major surface of the first insulating layer 22, as shown in FIG. 12. For the flattening processing, for example, a chemical-mechanical polishing (CMP) method is used in order to simultaneously polish the first insulating layer 22 and the metal plating layer 24, which are made of different materials. The CMP method enables polishing with material selectivity so as to increase the polishing rate of the metal plating layer 24 made of a metal such as copper, and realizes flattening of the polished surface with high accuracy. At this point, the ground part 15 a arranged above the pair of resonator conductor patterns 14 of the filter element 5 is provided at a part of the first wiring layer 25. [0063] Next, a second insulating layer 26 and a second wiring layer 27 are stacked on the first insulating layer 22 having the first wiring layer 25 embedded therein, as shown in FIG. 13. These second insulating layer 26 and second wiring layer 27 are formed through a process similar to the process of forming the first insulating layer 22 and the first wiring layer 25, using materials similar to those of the first insulating layer 22 and the first wiring layer 25. At this point, at certain parts in the second wiring layer 27, the pair of resonator conductor patterns 14 of the filter element S, a first shield part 28 a including plural via-holes as a shield surrounding the pair of resonator conductor patterns 14, and the via-hole 8 for making interlayer connection between the first wiring layer 25 and the second wiring layer 27 are collectively formed. [0064] In the second wiring layer 27, the pair of resonator conductor patterns 14 are linearly formed and arranged substantially parallel to each other so that they face each other in the direction of width, and feeder parts 29 are formed protruding in the direction opposite to the facing direction, from substantially central parts in the longitudinal direction of the pair of resonator conductor patterns 14, as shown in FIG. 14. In the second wiring layer 27, the pair of resonator conductor patterns 14 have a length that is substantially � of the passing wavelength λ in the longitudinal direction. One end in the longitudinal direction of each resonator conductor pattern 14 is connected to the first shield part 28 a and the other end is opened. [0065] The surface of the second insulating layer 26 having the second wiring layer 27 embedded therein is a surface flattened with high accuracy by flattening processing, similarly to the first insulating layer 22. This surface becomes the counter-surface 2 a where the pair of resonator conductor patterns 14 of the filter element 5 are exposed. In this embodiment, the wiring layers of the two-layer structure including the first wiring layer 25 and the second wiring layer 27 are used. However, the structure is not limited to this, and the process of forming the first insulating layer 22 and the first wiring layer 25 may be repeated to form three or more wiring layers. [0066] Next, in the counter-surface 2 a, a second shield part 28 b, for example, made of solder, is formed on the exposed first shield part 28 a, and a bump part 30 is similarly formed on the via-hole 8, as shown in FIG. 15. The second shield part 28 b is electrically connected with the ground part 15 b that is exposed on the mounting surface 4 a of the base board 4 when the circuit part 2 is mounted on the base board 4, and the second shield part 28 b thus shields the pair of resonator conductor patterns 14. The bump part 30 functions as an electric connection part in mounting the circuit part 2 on the base board 4 and may be formed as a nickel/copper plating layer, for example, using electroplating or electroless plating. [0067] The circuit part 2 in which the pair of resonator conductor patterns 14 of the filter element 5 are arranged on the counter-surface 2 a is thus formed. In the circuit part 2, the first insulating layer 22 and the second insulating layer 26 constitute the above-described plural insulating layers 6, and the first wiring layer 25 and the second wiring layer 27 constitute the above-described plural wiring layers 7. [0068] Next, the dummy board 20 is removed together with the peeling layer 21 from the circuit 2, as shown in FIG. 16. Specifically, the dummy board 20 and the peeling layer 21 together with the circuit part 2 are impregnated with an acid solution such as hydrochloric acid or nitric acid. The acid solution slightly dissolves the metal film 21 a of the peeling layer 21 and enters between the metal film 21 a and the resin film 21 b. Thus, peeling between the metal film 21 a and the resin film 21 b proceeds. The dummy board 20 is removed in the state where the resin film 21 b remains on the other major surface 2 b on the side of the first insulating layer 22, of the circuit part 2. In this case, in the circuit part 2, a protection layer for protecting the second wiring layer 27 from the acid solution may be formed on the counter-surface 2 a in advance. The dummy board 20 may also be removed from the circuit part 2, for example, by laser abrasion processing. [0069] Next, the resin film 2 b remaining on the other major surface 2 b of the circuit part 2 is removed by a dry etching method, for example, using as oxygen plasma. This exposes the via-hole 8 on the other major surface 2 b of the circuit part 2. Since the major surface of the dummy board 20 facing the other major surface 2 b is highly flattened, the other major surface 2 b of he circuit part 2 is highly flattened. [0070] Next, the circuit part 2 is mounted on the base board 4 in such a manner that the pair of resonator conductor patterns 14 exposed on the counter-surface 2 a and the ground part 15 b made up of a part of the input/output terminal parts 13 exposed on the mounting surface 4 a of the base board 4 face each other, as shown in FIG. 17. The base board 4 has the plural wiring layers 11 having the ground or the like within the layers and the plural insulating layers 10. On the mounting surface 4 a where the circuit part 2 is to be mounted, the input/output terminal parts 13 exposed from a protection layer 31 made of a resist or the like are formed, and the ground part 15 b as a ground conductor to the pair of resonator conductor patterns 14 is formed at a position facing the filter element 5, on the mounting surface 4 a. [0071] As the circuit part 2 is electrically connected with the input/output terminals 13 exposed on the mounting surface 4 a of the base board 4 via the bump parts 30, the circuit part 2 is mounted on the base board 4. Specifically, an under-filler 32 fills the space between the circuit part 2 and the base board 4 where the bump parts 30 and the input/output terminal parts 13 face each other. The bump parts 30 and the input/output terminal parts 13 are heated, for example, by a solder reflow method, and thus joined together. The circuit part 2 is thus mounted on the mounting surface 4 a of the base board 4. At this point, the second shield part 28 b is electrically connected with the ground part 15 b. The junction between the bump parts 30 and the input/output terminal parts 13 is not limited to the solder reflow method. For example, contraction due to solidification of a resin material filled between the circuit part 2 and the base board 4 may be used for compression bonding. [0072] Thus, in the base board 4, the part where the circuit part 2 is mounted on the mounting surface 4 a is the thick plate region 16, and the part where the circuit part 2 is not mounted on the mounting surface 4 a, that is, the part where the mounting surface 4 a is exposed, is the thin plate region 17. [0073] Next, on the mounting surface 4 a of the base board 4, the semiconductor component 3 such as a semiconductor chip or an LSI chip is mounted in the thin plate region 17, as shown in FIG. 18. This semiconductor component 3 is electrically connected with the mounting surface 4 a of the base board 4 via the element bump part 9 by a flip-chip bonding method. The mounting the semiconductor component 3 is not limited to the flip-chip bonding method. For example, a phase down bonding method such as a tape automated bonding (TAB) method or a lead beam bonding method may be used. [0074] In this manner, the semiconductor component 3 is mounted on the same plane as the circuit part 2 mounted on the mounting surface 4 a of the base board 4, that is, parallel to the circuit part 2 on the base board 4. The circuit board device 1 is thus manufactured. [0075] In the method for manufacturing the circuit board device 1 as described above, the semiconductor component 3 is mounted on the mounting surface 4 a of the base board 4, that is, in the thin plate region 17, so that the semiconductor component 3 becomes parallel to the circuit part 2, and the semiconductor component 3 and the circuit part 2 are mounted on the base board 4 in such a manner that the whole body including the semiconductor component 3 has a small thickness. Therefore, the circuit board device 1 having a reduced thickness is provided. [0076] In the method for manufacturing the circuit board device 1 according to the present invention, the pair of resonator conductor patterns 14 of the filter element 5 are formed in the inner layer of the thick plate region 16, that is, between the circuit part 2 and the base board 4, and the plural insulating layer 6 and 10 made of a dielectric insulating material are arranged above and below the filter element 5. Therefore, the pair of resonator conductor patterns 14 of the filter element 5 can be covered with the sufficiently thick dielectric insulating material, and the circuit board device 1 is provided in which deterioration in filter characteristic due to the thinning of the dielectric insulating material covering the pair of resonator conductor patterns 14 is prevented. [0077] In this method for manufacturing the circuit board device 1, the circuit part 2, which is relatively expensive, is mounted only on a necessary part instead of the entire mounting surface 4 a of the base board 4. Therefore, the circuit board device 1 of lower cost is provided. [0078] In the above-described embodiment, the circuit board device 1 having the circuit part 2 and the semiconductor component 3 mounted parallel to each other on the mounting surface 4 a of the base board 4 is described. However, the present invention is not limited to this and can also be applied to, for example, a circuit board device 40 having a structure as shown in FIG. 19. In FIG. 19, the same structural parts as those of the above-described circuit board device 1 are denoted by the same numerals and will not be described further in detail. [0079] In this circuit board device 40, a thick semiconductor component 41 that is thicker than the circuit part 2 and a thin semiconductor component 42 that is thinner than the circuit part 2 are mounted. In this case, for example, the thick semiconductor component 41 can be mounted in the thin plate region 17 and the thin semiconductor component 42 can be mounted on the other major surface 2 b of the circuit part 2. Thus, in the circuit board device 40, the thickness of the whole body can be reduced to realize reduction in thickness even when a thick and large semiconductor component is mounted. [0080] In this embodiment, the filter element 5 of the tri-plate structure is arranged in the circuit board device 1, as described above. However, the filter element is not limited to this structure. For example, a filter element of a flat structure may also be used, and a coupler element, an antenna element, a capacitor element, a register element or an inductor element based on a lumped constant design, a register element may be used instead of the filter element. [0081] While the invention has been described in accordance with a certain preferred embodiment thereof illustrated in the accompanying drawings and described in the above description in detail, it should be understood by those ordinarily skilled in the art that the invention is not limited to the embodiment, but various modifications, alternative constructions or equivalents can be implemented without departing from the scope and spirit of the present invention as set forth and defined by the appended claims. Industrial Applicability [0082] As described above, according to the present invention, the filter element is arranged between the base board and the circuit part on the major surface of the base board and the semiconductor component is thus mounted immediately on the second region thinner than the thick first region. Therefore, the thickness of the whole circuit board device is reduced and miniaturization is realized. [0083] Moreover, according to the present invention, the filter element is arranged inside the thick first region, that is, between the base board and the circuit part having the dielectric insulating layers, and the filter element can be covered with the sufficiently thick dielectric insulating layers. Therefore, the circuit board device is provided in which deterioration in filter characteristic due to the thinning of the dielectric insulating layers covering the filter element is prevented. [0084] Furthermore, according to the present invention, the circuit part, which is relatively expensive, is mounted only on the necessary part instead of the entire surface of the base board. Therefore, reduction in cost of the circuit board device is realized. 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examinerClassifications U.S. Classification361/750, 257/E23.114, 257/E23.062International ClassificationH01L23/66, H05K3/46, H01P11/00, H01P1/205, H01L23/552, H05K1/18, H01L25/00, H01L21/48, H01P1/203, H01L23/498, H01L21/68, H01P1/00, H05K1/16Cooperative ClassificationH01P11/007, H05K1/16, H01L2924/01079, H01L2924/19041, H01L2924/09701, H01L2924/19011, H01L23/49822, H01L21/6835, H01L23/552, H01P1/20363, H01L2924/3025, H01L2224/16, H01L21/4857, H01L2221/68345, H01L2924/30105, H05K2201/1006, H01L2924/01078, H05K3/4644, H05K1/183, H01L23/66European ClassificationH01L21/683T, H01L23/552, H01L21/48C4D, H01L23/498D, H01P11/00C, H05K1/16, H01L23/66, H01P1/203C2BLegal EventsDateCodeEventDescriptionSep 2, 2010FPAYFee paymentYear of fee payment: 4Aug 8, 2003ASAssignmentOwner name: SONY CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HIRABAYASHI, TAKAYUKI;OKUBORA, AKIHIKO;REEL/FRAME:014686/0143;SIGNING DATES FROM 20030710 TO 20030714RotateOriginal ImageGoogle Home - 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