Source: http://www.google.com/patents/US7442272?ie=ISO-8859-1
Timestamp: 2014-11-21 03:37:42
Document Index: 594119685

Matched Legal Cases: ['art 320', 'art 320', 'art 320', 'art 320', 'art 320', 'art 320', 'art 320', 'arts 420', 'arts 320', 'art 420', 'art 420', 'art 420', 'art 420', 'art 420', 'art 420', 'art 420']

Patent US7442272 - Apparatus for manufacturing semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn apparatus for improving the density and uniformity of plasma in the manufacture of a semiconductor device features a plasma chamber having a complex geometry that causes plasma density to be increased at the periphery or edge of a semiconductor wafer being processed, thereby compensating for a plasma...http://www.google.com/patents/US7442272?utm_source=gb-gplus-sharePatent US7442272 - Apparatus for manufacturing semiconductor deviceAdvanced Patent SearchPublication numberUS7442272 B2Publication typeGrantApplication numberUS 10/875,950Publication dateOct 28, 2008Filing dateJun 25, 2004Priority dateMay 3, 2001Fee statusPaidAlso published asUS6833050, US20020162629, US20040231797Publication number10875950, 875950, US 7442272 B2, US 7442272B2, US-B2-7442272, US7442272 B2, US7442272B2InventorsJeong-sic Jeon, Jin HongOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (20), Classifications (25), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetApparatus for manufacturing semiconductor deviceUS 7442272 B2Abstract An apparatus for improving the density and uniformity of plasma in the manufacture of a semiconductor device features a plasma chamber having a complex geometry that causes plasma density to be increased at the periphery or edge of a semiconductor wafer being processed, thereby compensating for a plasma density that is typically more concentrated at the center of the semiconductor wafer. By mounting a target semiconductor wafer in a chamber region that has a cross-sectional area that is smaller than a cross-sectional area of a plasma source chamber region, a predetermine flow of generated plasma from the source becomes concentrated as it moves toward the semiconductor wafer, particularly at the periphery of the semiconductor wafer. This provides a more uniform plasma density across the entire surface of the target semiconductor wafer than has heretofore been available.
1. An apparatus for manufacturing a semiconductor device using plasma, comprising:
a chamber having a plasma generating region and a plasma processing region adapted to perform a manufacturing process on the semiconductor device under a plasma atmosphere;
a plasma generating means adjacent to the plasma generating region; and a plasma concentrating means adapted to reduce a size of the plasma processing region near the semiconductor device to be processed compared to a size of the plasma generating region, wherein the plasma concentrating means including:
an electrode having a first length on which the semiconductor device to be processed is positioned,
an insulating plate having a second length longer than the first length and facing the electrode, and
a confinement layer contacting the edge of the insulating plate, forming an acute angle to a virtual plane connecting opposing ends of the insulating plate, and extending toward an edge of the electrode,
wherein the insulating plate includes a first part having a first radius of curvature and a second part having a second radius of curvature, which is smaller than the first radius of curvature, and an edge of the second part of the insulating plate being connected to the confinement layer.
2. The apparatus as claimed in claim 1, wherein the plasma generating means is installed outside of the chamber to generate plasma that is introduced into the plasma generating region of the chamber.
3. The apparatus as claimed in claim 2, wherein the plasma generating means comprises a plurality of induction coils mounted on the chamber and a first power supply connected to the plurality of induction coils.
4. The apparatus as claimed in claim 3, wherein the plasma generating means comprises a second power supply connected to the electrode on which the semiconductor device is positioned.
5. The apparatus as claimed in claim 1, wherein the confinement layer is formed of a sidewall of the chamber.
6. An apparatus for manufacturing a semiconductor device using plasma, comprising:
a chamber having a plasma generating region and a plasma processing region adapted to perform a manufacturing process on the semiconductor device under a plasma atmosphere,
a plasma generating means adjacent the plasma generating region; and
a plasma concentrating means adapted to reduce a size of the plasma processing region near the semiconductor device to be processed compared to a size of the plasma generating region, the plasma concentrating means including:
a confinement layer contacting an edge of the insulating plate, forming an acute angle to a virtual plane connecting opposing ends of the insulating plate, and extending toward an edge of the electrode,
wherein the insulating plate has a dome shape having a predetermined radius of curvature, and the second length of the insulating plate being approximately the same as a projected diameter of the insulating plate.
7. The apparatus as claimed in claim 6, further comprising a chuck for supporting a wafer having a third length and disposed on the electrode.
8. The apparatus as claimed in claim 7, wherein the second length is over 140% of the third length.
9. The apparatus as claimed in claim 8, wherein the first length of the electrode is over 120% of the third length.
10. The apparatus as claimed in claim 9, wherein the distance from the edge of the wafer to an associated edge of the electrode is between 10 and 15% of the third length.
11. The apparatus as claimed in claim 9, wherein the second length is approximately 420 mm and the third length is approximately 300 mm.
12. The apparatus as claimed in claim 11, wherein the electrode has a diameter of approximately 360 mm.
13. The apparatus as claimed in claim 6, wherein the acute angle is between 45 and 89 degrees.
14. The apparatus as claimed in claim 6, wherein the confinement layer is formed of a sidewall of the chamber.
15. An apparatus for manufacturing a semiconductor device using plasma, comprising:
chamber having a plasma generating region and a plasma processing region adapted to perform a manufacturing process on the semiconductor device under a plasma atmosphere;
a plasma generating means adjacent to the plasma generating region; and
an electrode having a first length;
an insulating plate having a dome shape, and including a first part having a first radius of curvature and a second part having a second radius of curvature, which is smaller than the first radius of curvature, both of the first part and the second part face the plasma generating region; and
a confinement layer connected to the second part of the insulating plate and extending toward the electrode,
wherein a projected diameter of the second part of the insulating plate over the electrode is smaller than a projected diameter of the first part of the insulating plate, and equal to or larger than the first length of the electrode.
16. The apparatus as claimed in claim 15, wherein the confinement layer is substantially perpendicular to the projected length of the insulating plate.
17. The apparatus as claimed in claim 16, wherein the confinement layer is formed of a sidewall of the chamber.
18. The apparatus as claimed in claim 15, wherein the confinement layer forms an acute angle to a virtual plane connecting opposing ends of the insulating plate.
19. The apparatus as claimed in claim 15, wherein a center radius of curvature of the first part is at a different position than a center radius of curvature of the second part.
This application is a Division of application Ser. No. 10/003,412, filed Dec. 6, 2001 now U.S. Pat. No.6,833,050.
There are significant differences between the apparatus shown in FIG. 1A and the apparatus shown in FIG. 2. First, the diameter M2 of the lower electrode 126 shown in FIG. 2 is preferably smaller than the diameter M1 of the insulating plate 120 of FIG. 2. Second, in the vacuum chamber 112 of FIG. 2, the confinement layer 122, which contacts the edge of the insulating plate 120 and extends toward the lower electrode 126, is preferably not perpendicular to the insulating plate 120, rather it preferably forms an acute angle 1 to the insulating plate 120. For example, it is preferable that the acute angle 1 of the confinement layer 122 be in the range of 45-89 degrees. Accordingly, since the insulating plate 120 and the lower electrode 126 shown in FIG. 2 are circular plates, the confinement layer 122 has a cylindrical shape, the diameter of which is reduced at an end closer to the lower electrode 126. A resulting plasma region 124 has the same shape as the confinement layer 122, i.e., cylindrical. Thus, when compared to an apparatus adopting a confinement layer 22 that is perpendicular to the lower electrode 26 shown in FIG. 1, the apparatus of the present invention produces slight plasma density increases near the edge of the wafer 130, but not near the center of the wafer 130. This produces an overall uniform plasma density on the wafer 130.
According to the above-described embodiment, even though the first and second power supplies, 116 and 118, respectively, do not increase the power and pressure in the vacuum chamber 112, the cross-sectional area of the plasma region 124, which is defined by the cylindrical confinement layer 122, is smaller near the wafer 130 than near the insulating plate 120. This effectively increases the usable plasma density of a given amount of plasma generated, and substantially increases the plasma density near the edge of the wafer. Thus, the uniformity of the distribution of plasma throughout the wafer is improved, thereby producing a uniform etch rate for the patterns.
As described above, the projected diameter of D1 of the insulating plate 220 is greater than the diameter D2 of the lower electrode 226. Like FIG. 2, a confinement layer 222 contacts the edge of the dome-shaped insulating plate 220 and extends toward the wafer 230, forming an acute angle 2 to the projected surface of the insulating plate 220. Thus, plasma density in a plasma region 224 increases in a direction toward the wafer 230, and in particular, plasma density in a plasma region 224 increases significantly near the edge of the wafer 230. As a result, high-density plasma is obtained and the uniformity of etching throughout the wafer 230 is improved.
Reference numbers 218 and 228 indicate a power supply having a high frequency and a chuck for supporting the wafer 230, respectively. Reference numbers 218 and 228 correspond to reference numbers 118 and 128 shown in FIG. 2. D4 represents the distance from the wafer 230 to the confinement layer 222 or the edge of the lower electrode 226 and corresponds to M4 shown in FIG. 2.
For example, an acute angle 2 may be within the range of about 45-89 degrees. The distance spanned by the plurality of induction coils 214 and the projected diameter D1 the insulating plate 220 is preferably over about 140% of the diameter D3 of the wafer 230 and preferably over about 120% of the diameter D2 of the lower electrode 226. The exemplary distance D4 from the edge of the lower electrode 226 to the edge of the wafer 230 would be about 10-15% of the diameter M3 of the wafer 130. For example, for a wafer 230 having a diameter D3 of 300 mm, the diameter D1 of the insulating plate 220 would be approximately 420 mm and the length D2 of the lower electrode 226 would be approximately 360 mm, and D4 would be approximately 30-45 mm.
Reference numbers 312, 314, 316, 318, 326, 328, and 330 in FIG. 4 denote the same members as reference numbers 212, 214, 216, 218, 226, 228, and 230, respectively, in FIG. 3. In the embodiment shown in FIG. 4, plasma is concentrated by adjusting the radius of curvature of a dome-shaped insulating plate 320 rather than by adjusting a slanted confinement layer as shown in FIGS. 2 and 3. The dome-shaped insulating plate 320 is divided into two parts, wherein a first part 320 a preferably has a relatively larger radius of curvature with a second part 320 b having a relatively smaller radius of curvature. Thus, the projected diameter N1 of the first part 320 a is greater than the projected diameter N2 of the second part 320 b. The projected diameter N2 of the second part 320 b denotes the projected diameter of the dome-shaped insulating plate 320. The projected diameter N2 of the second part 320 b may be designed to be substantially equal to the diameter N3 of a lower electrode 326. Here, the radius of curvature or the projected diameter N2 of the second part 320 b may be determined by the diameter N4 of a wafer 330, the distance N5 from the wafer 330 to a confinement layer 322, and the height of the confinement layer 322.
Reference numerals 412, 414, 416, 418, 426, 428, and 430 in FIG. 5 denote the same members as reference numerals 212, 214, 216, 218, 226, 228, and 230, respectively, in FIG. 3. In an etching apparatus shown in FIG. 5, the radius of curvature of an insulating plate 420 is adjusted to concentrate plasma to a predetermined area, and a confinement layer 422 is preferably slanted at a predetermined angle 3 so that plasma is further concentrated to the predetermined area.
A dome-shaped insulating plate 420 includes two parts 420 a and 420 b, similar to the insulating plate 320 having the two parts 320 a and 320 b shown in FIG. 4. In other words, the dome-shaped insulating plate 420 preferably includes a first part 420 a having a relatively larger radius of curvature P1 and a second part 420 b having a relatively smaller radius of curvature P2. The projected diameter of the first part 420 a is greater than the projected diameter P2 of the second part 420 b or the diameter P3 of the lower electrode 426. The projected diameter P2 of the second part 420 b denotes the projected diameter of the dome-shaped insulating plate 420. The confinement layer 422 is connected to the second part 420 b, which extends toward the lower electrode 426, preferably forms an acute angle 3 to the projected surface of the insulating plate 420.
The relationships between the diameter P4 of a wafer 430, the projected diameter P2 of the second part 420 b, the diameter P3 of the lower electrode 426, and the distance P5 from the wafer to the confinement layer 422 and examples thereof may be the same as those described conditions used in the above-described embodiments. The acute angle 3 may be the same as the acute angles of the above-described embodiments.
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