Source: http://www.google.com/patents/US6175517?dq=5,781,788
Timestamp: 2013-12-18 18:06:08
Document Index: 738781335

Matched Legal Cases: ['art 1', 'art 2', 'art 3', 'art 1', 'art 1', 'art 2', 'art 2', 'art 3', 'art 3']

Patent US6175517 - Insertble and removable digital memory apparatus - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsEach device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices...http://www.google.com/patents/US6175517?utm_source=gb-gplus-sharePatent US6175517 - Insertble and removable digital memory apparatusAdvanced Patent SearchPublication numberUS6175517 B1Publication typeGrantApplication numberUS 09/435,495Publication dateJan 16, 2001Filing dateNov 6, 1999Priority dateAug 13, 1996Fee statusPaidAlso published asUS5815426, US6026007, US20010038547, WO1998007098A1Publication number09435495, 435495, US 6175517 B1, US 6175517B1, US-B1-6175517, US6175517 B1, US6175517B1InventorsRobin J. Jigour, David K. WongOriginal AssigneeIntegrated Silicon Solution, Inc., Nex Flash Technologies, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (13), Non-Patent Citations (18), Referenced by (64), Classifications (20), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetInsertble and removable digital memory apparatusUS 6175517 B1Abstract Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required. In particular, a small number of durable contact pads form the contact arrays (314, 324, 334, 344, 354 and 364) on the digital media devices, which in conjunction with corresponding contact pads mounted into a suitable socket provide for easy and convenient insertion and removal and for robust and reliable electrical contact over a long insertion lifetime. Preferably, the digital media devices of the family incorporate flash memory, which permits low voltage operation, low power consumption, and high capacity non-volatile data storage. Preferably, the digital media devices of the family are fabricated using surface mount techniques (310 and 320) or particularly inexpensive �Chip on Board� techniques (330, 340, 350 and 360). The digital media devices interface to the host either directly or through adapters. Access is handled either by a dedicated controller or other logic residing in the adapter or on the host, or by software running on the host.
What is claimed is: 1. An insertable and removable digital data storage apparatus for use in electronic apparatus having digital data storage requirements, comprising:
a high memory capacity digital data storage card for insertion to the digital apparatus in a predetermined direction and removal therefrom, the card having serial data transfer, clock, power, and ground connectivity requirements; and first, second, third, and fourth electrical contacts respectively satisfying the serial data transfer, clock, power, and ground connectivity requirements of the card, the contacts being arranged in first and second rows integral with a surface of the card and generally transverse to the direction of insertion. 2. An apparatus as in claim 1 wherein the serial data transfer connectivity requirement is a serial data input and output requirement.
3. An apparatus as in claim 1 wherein the card comprises non-volatile programmable memory.
4. An apparatus as in claim 3 wherein:
the first row comprises the second and third contacts; and the second row comprises the first and fourth contacts. 5. An apparatus as in claim 3 further comprising:
a write-protect signal generator having a write-protect indication connectivity requirement; and a fifth electrical contact integral with the body and satisfying the write-protect indication connectivity requirement; wherein the fourth and fifth electrical contacts comprise respective portions aligned generally in the direction of insertion.
6. An apparatus as in claim 5 wherein:
the first row comprises the second and third contacts; and the second row comprises the first, fourth and fifth contacts. 7. An apparatus as in claim 6 wherein the contacts are further arranged in first, second and third columns generally parallel to the direction of insertion, the first contact being in row:column position 2:3, the second contact being in row:column position 1:3, the third contact being in row:column position 1:1, the fourth contact being in row:column position 2:1, and the fifth contact being in row:column position 2:2.
8. An apparatus as in claim 7 further having test connectivity requirements and further comprising sixth, seventh and eighth electrical contacts satisfying the test connectivity requirements of the card, the seventh and eighth contacts being further arranged in a fourth column generally parallel to the direction of insertion, the sixth contact being in row:column position 1:2, the seventh contact being in row:column position 1:4, and the eighth contact being in row:column position 2:4.
9. An apparatus as in claim 7 further having first and second chip select connectivity requirements and a ready-busy connectivity requirement, further comprising sixth, seventh and eighth electrical contacts respectively satisfying the first and second chip select connectivity requirements and the ready-busy connectivity requirement of the card, the seventh and eighth contacts being further arranged in a fourth column generally parallel to the direction of insertion, the sixth contact being in row:column position 1:2, the seventh contact being in row:column position 1:4, and the eighth contact being in row:column position 2:4.
10. An apparatus as in claim 5 wherein the serial data transfer connectivity requirement is a serial data output requirement, the card further having a serial data input connectivity and further comprising a sixth electrical contact satisfying the serial data input connectivity requirement of the card.
11. An apparatus as in claim 10 further having first and second chip select connectivity requirements and further comprising seventh and eighth electrical contacts respectively satisfying the first and second chip select connectivity requirements of the card, wherein the contacts are further arranged in first, second, third and fourth columns generally parallel to the direction of insertion, the first contact being in row:column position 2:3, the second contact being in row:column position 1:3, the third contact being in row:column position 1:1, the fourth contact being in row:column position 2:1, the fifth contact being in row:column position 2:2, the sixth contact being in row column position 2:4, the seventh contact being in row:column position 1:2, and the eighth contact being in row:column position 1:4.
12. A storage apparatus comprising:
a substantially inflexible elongated body having a length in excess of 25 mm and a generally planar first major surface; a plurality of electrical contacts integral with the body, at least a portion of each of the electrical contacts being a pad disposed generally level with the first major surface and the body having a general thickness proximate to the electrical contacts of less than about 0.8 mm; and a high capacity digital memory integral with the body, the memory having a serial data node coupled to one of the pads, a power node coupled to one of the pads, a ground node coupled to one of the pads, and a clock node coupled to one of the pads. 13. A storage apparatus as in claim 12 wherein the body comprises a core portion of a rigid or semi-rigid material.
14. A storage apparatus as in claim 13 wherein the rigid or semi-rigid material is selected from the group consisting of plastic, fiberglass, ceramic, PVC, PVCA, and FR4.
15. A storage apparatus as in claim 13 wherein the memory comprises an integrated circuit securely mounted on the core body portion in accordance with a surface mount technique.
16. A storage apparatus as in claim 13 wherein the memory comprises first and second memory integrated circuits securely mounted on the core body portion in accordance with a surface mount technique.
17. A storage apparatus as in claim 13 wherein the memory comprises an integrated circuit securely mounted on the core body portion in accordance with a chip-on-board direct technique.
18. A storage apparatus as in claim 13 wherein the memory comprises first and second memory integrated circuits securely mounted on the core body portion in accordance with a chip-on-board direct technique.
19. A storage apparatus as in claim 13 wherein the memory comprises a memory integrated circuit disposed within the core body portion in accordance with a chip-on-board modular technique.
20. A storage apparatus as in claim 13 wherein the memory comprises first and second memory integrated circuits disposed within the core body portion in accordance with a chip-on-board modular technique.
21. A storage apparatus as in claim 12 wherein the body further has a general thickness of less than about 0.8 mm.
22. A storage apparatus comprising:
a substantially inflexible body having a width of about 15 mm, a length of 25 mm to about 54 mm, a thickness of about 0.8 mm, and a generally planar first major surface; a plurality of electrical contacts integral with the body, at least a portion of each of the electrical contacts being a pad disposed generally level with the first major surface; and a memory integrated circuit securely mounted with respect to the body, the memory integrated circuit having a serial data node coupled to one of the pads, a power node coupled to one of the pads, a ground node coupled to one of the pads, and a clock node coupled to one of the pads.
RELATED APPLICATIONS This application is a divisional of U.S. patent application Ser. No. 09/084,044, filed May 22, 1998, now U.S. Pat. No. 6,026,007, issued Feb. 15, 2000 (Jigour and Wong, �Insertable and Removable High Capacity Digital Memory Apparatus and Methods of Operation Thereof�); which is a continuation of U.S. patent application Ser. No. 08/823,937, filed Mar. 25, 1997, now U.S. Pat. No. 5,815,426, issued Sep. 29, 1998 (Jigour and Wong, �Adapter for Interfacing an Insertable/Removable Digital Memory Apparatus to a Host Data Port�), which is a continuation-in-part of U.S. patent application Ser. No. 08/689,687, filed Aug. 13, 1996, now U.S. Pat. No. 5,877,975, issued Mar. 2, 1999 (Jigour and Wong, �Insertable/Removable Digital Memory Apparatus and Method of Operation Thereof�), all of which are hereby incorporated herein in their entirety by reference thereto.
A variety of add-on cards and modules for use in digital systems such as personal computers (�PC�) have enjoyed a measure of success in various memory-intensive applications. Some of these memory add-on cards use flash memory, and are known as flash PC cards. Flash PC cards have become widely used for mass data storage applications, and are a popular alternative for conventional add-on card implemented non-volatile memory solutions such as rotating hard disks and battery-backed SRAM, especially for notebook computers, personal data assistants (�PDAs�), and some high-end digital cameras. As an alternative to rotating hard disk PC cards, flash PC cards are more rugged and space efficient, are silent, consume less power, provide higher performance (in most cases), and provide a removable form-factor. As an alternative to battery-backed SRAM PC cards, flash PC cards typically offer higher-densities and lower cost per bit and are not as limited by reliability and temperature issues associated with batteries used in the battery-backed SRAM PC cards.
FIG. 1 shows to scale the surface area of a number of high capacity memory card types presently available. The surface area of a flash PC card is shown at 100 in FIG. 1. Flash PC cards are compliant with the Personal Computer Memory Card International Association (�PCMCIA�) standard, which specifies a form factor of approximately 85.6 mm (3.37 inches) by 54 mm (2.126 inches), with a thickness of either about 3 mm for a Type-I card or about 5 mm for a Type-II card. The connector specified by the PCMCIA standard uses 68 pins organized in two rows of 34 pins each with 1.27 mm (50 mils) spacing between pins. The physical specifications for PC cards are described in a publication of the Personal Computer Memory Card International Association/JEIDA entitled PC Card Standard, Volume 3: Physical Specification, Document No. 0295-03-1500, February 1995.
Flash PC cards typically have a high memory capacity of from about 2 Megabytes to 85 Megabytes, although recently even higher capacity cards have been introduced. Like hard-disks, flash PC cards spend about 75 percent of operation time being read from and 25 percent being written to. The two primary PC card interface types are ATA and Linear. PC cards that support the ATA interface use an on-card ATA controller, which allows �plug and play� compatibility between portable computers and PDAs. Linear flash cards do not use a dedicated ATA controller and require software drivers to implement file interface protocol.
While flash PC cards can provide sufficient amounts of memory for a broad range of applications, they have not been widely accepted for use in applications such as mobile and portable electronics or for use in applications having significant cost sensitivity. PC cards simply tend to be too large for many portable applications such as pagers, voice recorders, mobile telephones, and hand-held meters. PC cards are also too bulky and heavy for carrying in a pocket or wallet, as would be desirable for many consumer applications. Current PC cards are also quite expensive, hence are offered generally as after market enhancements or add-ons. PC cards can be made available at extremely high memory capacities because of improved memory technology; however, such extremely high memory capacities are in excess of what is optimal for many mobile and portable applications. Moreover, although the insertion lifetime of 68-pin PC card connectors, which is about 10,000 cycles, is generally adequate for portable computers and PDAs, it is inadequate for other applications involving more frequent insertion and removal of the storage media than encountered in portable computing. In addition, the high number of pins and the tendency of the narrow deep sockets on the PC cards to collect foreign material increase the probability of failure, especially if the PC cards are not carefully handled. Also, PC cards have parallel busses, which are problematical since they permit multiple signal transitions that cause system noise and interference with wireless RF products. Some PC cards commonly available use channel hot electron flash technology, which because of its inherent high current demands tends to make erase/write programming times lengthy and reduce effective battery lifetimes in mobile and portable applications.
As the PCMCIA standard is not entirely suitable for small portable devices, flash memory recently has been used in a variety of removable devices having smaller form factors than the standard PC card, including, for example, compact flash cards, miniature cards, and solid state floppy disk cards (�SSFDC�). The surface areas of these devices are illustrated at 110, 120 and 130 respectively in FIG. 1.
The compact flash card is a small format flash memory card that was initially announced by SanDisk Corporation in 1994. The form factor of the compact flash card is 36�43�3.3 mm, and the surface area thereof, which is shown at 110 in FIG. 1, is approximately ⅓ the surface area of the standard PC Card. The card has a 50 pin connector that is a subset of the PC card interface. The card supports the IDE/ATA interface standard by means of an on-card ATA controller IC. Memory capacity in the range of 2 Megabytes to 15 Megabytes is currently available, although greater memory capacity devices are likely to be introduced. Both 5 volt and 3.3 volt power supplies are supported. A compact flash card is interfaced to notebook computers and PDAs by inserting the card into a special PC card adapter. The compact flash series is described in a publication of the SanDisk Corporation entitled Compact flash Series Preliminary Data Sheet, Document No. 80-11-00015, Rev. 1.0, October 1994.
The miniature card is a small format card that was initially announced by Intel Corporation in 1995. The form factor of the miniature card is 35�33�3.5 mm, and the surface area, which is shown at 120 in FIG. 1, is approximately 25% the surface area of the standard PC card. The miniature card has a 60 pin Elastimeric connector rated at a minimum insertion lifetime of 5,000 cycles. The card supports a linear addressing range of up to 64 Megabytes of memory using a 16-bit data bus. Memory capacity in the range of 2 Megabytes to 4 Megabytes is currently available, although greater memory capacity devices are likely to be introduced. The miniature card specification allows for flash, DRAM and ROM memory types. Both 5 volt and 3.3 volt power supplies are supported by the specification. A miniature card is interfaced to notebook computers and PDAs that support the standard PC card interface with a special PC card adapter. A miniature card specification is described in Miniature Card Specification, Release 1.0, February 1996, available from Intel Corporation of Santa Clara, Calif.
The solid state floppy disk card, or SSFDC, is a small format card initially announced by Toshiba Corporation in 1995. The form factor of the SSFDC card is 45�37�0.76 mm, and the surface area thereof, which is shown at 120 in FIG. 1, is approximately 36% the surface area of the standard PC card. The SSFDC has 22 flat contact pads, some of which are I/O pads for both address and data input and output as well as for command inputs. The card specification is dedicated to byte serial NAND-type flash memory. Memory capacity of 2 Megabytes is currently available, although memory capacity in the range of 512 kilobytes to 8 Megabytes is anticipated. The specification accommodates 5 volt or 3.3 volt power supplies. An SSFDC is interfaced to notebook computers and PDAs that have the standard PC card interface with a special PC card adapter. An illustrative device is type TC5816ADC, which is described in Preliminary TC5816ADC Data Sheet No. NV16030496, April 1996, available from Toshiba America Electronic Components, Inc. of Irvine, Calif. The device is said to be suitable for such applications as solid state file storage, voice recording, image file memory for still cameras, and other systems which require high capacity, non-volatile memory data storage.
Seimens Components of Cupertino, Calif. has described a device known as MultiMediaCards, or MMC; see Portable Design, July 1996, p. 23 et seq. The form factor of the MMC package is 37�45�1.4 mm, and the surface area, which is shown at 140 in FIG. 1, is approximately 36% that of the standard PC card. The MMC package has 6 edge-mounted contact pads with an insertion lifetime of 10,000 cycles, and uses a serial bus. Initially, MMCs are expected to be offered with a choice of 16 Megabit or 64 Megabit ROM memory, but is reported to be teaming up with undisclosed partners to put flash memory on its MMC cards. The specification accommodates a 3.3 volt power supply. The device is said to be suitable for such applications as video games, talking toys, automobile diagnostics, smart phones (tailored operating systems or special programs), PDAs (tailored operating systems or special programs), and notebooks through a PDA adapter.
The Integrated Circuit (IC) card format and the similar Identification (ID) card format, commonly known as smart cards, were introduced in the mid 1980's, and have been standardized by the International Organization for Standardization (ISO); see International Organization for Standardization, Identification Cards�Integrated Circuit Cards with Contacts, Part 1: Physical Characteristics, Document No. ISO 7816-1, July 1987; International Organization for Standardization, Identification Cards�Integrated Circuit Cards with Contacts, Part 2: Dimensions and Location of Contacts, Document No. ISO 7816-2, May 1988; and International Organization for Standardization, Identification Cards�Integrated Circuit Cards with Contacts, Part 3: Electronic Signals and Transmission Protocols, Document No. ISO 7816-3, September 1989. Smart cards are credit card sized and typically contain a microcontroller with a small amount of EEPROM memory, typically 256 to 8K bits. The surface area of the smart card is shown at 210 in FIG. 2. The length and width of the smart card is nearly identical with the length and width of the PC card, but the smart card is much thinner. The cards are popular in Europe and are making inroads into the US market. Primary applications are smart telephone calling cards and stored value cards, the later application being promoted by credit card companies like Visa and Master card as a replacement for paper currency. IC and ID cards have a simple contact pattern of eight flat contact pads designated C1-C8 of which only six are used. Contact signal assignments are C1=VCC (supply voltage), C2=RST (reset), C3=CLK (clock signal), C4=Reserved, C5=GND (ground), C6=VPP (programming voltage), C7=I/O (data input/output) and C8=Reserved. Due to their popularity in Europe, a great infrastructure of connectors and readers is already established for IC and ID cards.
Another low memory capacity card format is known as the Subscriber Identification Module (�SIM�), which is used in conjunction with mobile telephones based on the Global System for Mobile Communications (�GSM�) standard. The SIM specification is set forth in a publication of the European Telecommunication Standard Institute entitled European Digital Cellular Telecommunication System, Global System for Mobile Communications, Phase 2: Specification of Subscriber Identity Module�Mobile Equipment Interface, Document No. GSM11.11, Reference (RE/SMG)-091111PR3, ICS 33.060.50, December 1995. The form factor of the SIM is 25 mm�15 mm�0.76 mm, and the surface area thereof, which is shown at 220 in FIG. 2, is much smaller than the standard PC card. SIMs offer only a very limited amount of memory, typically less than one kilobit. However, this small amount of memory is sufficient to provide a GSM mobile phone with secure identification of the GSM subscriber, and may also hold a small amount of data for call metering, phone number storage, and in some cases very short data messages (less than a few hundred bytes of data). The SIM uses the same 8 pad contact pattern as the IC card, but only five of the pads are required for VCC, RST, CLK, GND, and I/O. The plug-in SIM typically is housed in a small hinged smart card connector similar to the type CCM03 available from ITT Cannon Corporation of Santa Ana, Calif. The small form factor allows the GSM SIM to be placed inside the phone as a plug-in module. Because the GSM SIM typically is removed only if a different GSM phone is to be used, GSM SIM connectors typically are designed for fewer insertion/removal cycles than normally experienced with IC and ID cards.
SUMMARY OF THE INVENTION One embodiment of the present invention is an insertable and removable digital data storage apparatus for use in electronic apparatus having digital data storage requirements. The apparatus comprises a high memory capacity digital data storage card for insertion to the digital apparatus in a predetermined direction and removal therefrom, the card having serial data transfer, clock, power, and ground connectivity requirements; and first, second, third, and fourth electrical contacts respectively satisfying the serial data transfer, clock, power, and ground connectivity requirements of the card, the contacts being arranged in first and second rows integral with a surface of the card and generally transverse to the direction of insertion.
Another embodiment of the present invention is a storage apparatus comprising a substantially inflexible elongated body having a length in excess of 25 mm and a generally planar first major surface; a plurality of electrical contacts integral with the body, at least a portion of each of the electrical contacts being a pad disposed generally level with the first major surface and the body having a general thickness proximate to the electrical contacts of less than about 0.8 mm; and a high capacity digital memory integral with the body, the memory having a serial data node coupled to one of the pads, a power node coupled to one of the pads, a ground node coupled to one of the pads, and a clock node coupled to one of the pads.
A further embodiment of the present invention is a storage apparatus comprising a substantially inflexible body having a width of about 15 mm, a length of 25 mm to about 54 mm, a thickness of about 0.8 mm, and a generally planar first major surface; a plurality of electrical contacts integral with the body, at least a portion of each of the electrical contacts being a pad disposed generally level with the first major surface; and a memory integrated circuit securely mounted with respect to the body, the memory integrated circuit having a serial data node coupled to one of the pads, a power node coupled to one of the pads, a ground node coupled to one of the pads, and a clock node coupled to one of the pads.
FIG. 17 is a cross-sectional view of a clip-on-board-modular digital media device having two chips;
FIG. 3 is a perspective view of a family 300 of removable digital media devices 310, 320, 330, 340, 350 and 360, each of which when plugged into a host permits the host to store data in it or to retrieve data from it. Preferably, the form factors of the digital media devices in the family 300 and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments, illustratively digital media devices 310, 320, 330, 350 and 360 provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family 300 have respective body portions 312, 322, 332, 342, 352 and 362 preferably of a rigid or semi-rigid material such as mylar, poly-vinyl chloride (�PVC�) or PVCA material, which is commonly used in smart cards and modules, or FR4 epoxy glass, which is commonly used for printed circuit boards. Preferably, the digital media devices of the family 300 use serial memory requiring few power and signal lines, so that few electrical contacts are required. In particular, a small number of durable contact pads form respective contact arrays 314, 324, 334, 344, 354 and 364 on the digital media devices 310, 320, 330, 340, 350 and 360, which in conjunction with corresponding contact pads mounted into a suitable socket provide for easy and convenient insertion and removal and for robust and reliable electrical contact over a long insertion lifetime. Preferably, the digital media devices of the family 300 incorporate flash memory, which permits low voltage operation, low power consumption, and high capacity non-volatile data storage. Preferably, the digital media devices of the family 300 are fabricated using surface mount techniques, of which the digital media devices 310 and 320 are illustrative, or particularly inexpensive �Chip on Board�(�COB�) techniques, of which the digital media devices 330, 340, 350 and 360 are illustrative.
Preferably, the form factors of the digital media devices in the family 300 are compact for easy storage and transportation and for minimizing �insertion volume� in a host such as a laptop computer or PDA. Insertion volume is the volume required to house a card or module, or rather the connector of the card or module and as much of the card or module as is required to be contained by the host. Some family members provide an elongated compact form factor that provides easy and firm grasping for insertion and removal, as well as space for additional memory ICs or chips. Other family members are of a length comparable with the length of certain common battery types such as AA and AAA batteries, and are therefor capable of insertion into the battery compartments of personal, portable and mobile equipment.
Preferably, the digital media devices of the family 300 incorporate high density serial flash memory, which requires few power and signal lines and permits low voltage operation, low power consumption, and high capacity non-volatile data storage. A suitable serial flash memory circuit is disclosed in U.S. Pat. No. 5,291,584, issued Mar. 1, 1994 to Challa et al. and entitled �Method and Apparatus for Hard Disk Emulation,� which is hereby incorporated herein by reference in its entirety. One type of serial flash memory includes one or more flash memory arrays, one or more row decoders, column selects, page latches, data shift registers, sense amps, row address shift registers, and control logic and data buffers.
Other serial standards and specifications may also be suitable other than the specification set forth in the aforementioned Challa et al. patent, including, for example, SPI, I2C, COPS and MICROWIRE. However, serial flash memory of the type disclosed in the aforementioned Challa et al. patent is particularly advantageous because it requires a minimum number of electrical contacts, is capable of being manufactured at high memory densities, is of relatively small die size, and has low power consumption. For example, the Challa bit-serial flash memory requires only four outside connections, viz. VCC, ground, data input/output (�I/O�), and clock. Other connections may be desirable in some applications or for other types of flash memory, including, for example, chip select, write protect, ready/busy, and memory test. Typical densities available with current process technology are in the range of 1 Megabit to 16 Megabits, and densities are expected to increase with improvements in process technology. A memory density of, for example, 8 Megabits fabricated with conventional 0.7 μm process technology typically is presently available.
The contact pads of the digital media devices in the family 300 are assigned signal and power functions depending on the interface selected. Preferred serial interface protocols are the Nexcom Serial Interface protocol, or NXS protocol, which is described in the aforementioned Challa et al. patent and specifies a two-wire interface, viz. Clock and Data I/O; and the Serial Peripheral Interface (�SPI�) protocol, which specifies a four-wire interface, viz. Clock, Data In, Data Out, and Chip Select. The NXS and SPI protocols are illustrative, and other protocols may be used if desired. While the use of eight contact pads is described, six pads would be entirely satisfactory for some applications and the interface protocols would be adjusted accordingly.
One set of illustrative pad assignments for the digital media device 700 using the NXS protocol (pad assignments for the digital media devices 500 and 600 are analogous) are as follows: VCC at pad 711, NC (no connection) at pad 712, SCK at pad 713, NC at pad 714, GND and DT (card detect) at pad 715 (the digital media device 500 does not support DT), NC/WP\ and DT\ at pad 716, DIO at pad 717, and NC at pad 718.
FIG. 11 is a block schematic diagram of illustrative electrical connections suitable for this set of illustrative pad assignments. VCC and ground are furnished to an NXS protocol digital media device 1110, which includes, illustratively, the contact pad array 710 (contact pad arrays 510 and 610 are analogous) through respective contact pads 711 and 715. The digital media device 1110 includes two NXS protocol memory integrated circuits 1112 and 1114 (alternatively, the digital media device 1110 may contain one memory integrated circuit or more than two memory integrated circuits). A controller 1100, which is any suitable controller, including, for example, general purpose microcontrollers, digital signal processors, and application-specific integrated circuit logic, furnishes its clock signal SCK to the SCK ports of the NXS protocol memory integrated circuits 1112 and 1114 through the contact pad 713, and its data signal SIO to the DIO ports of the NXS protocol memory integrated circuits 1112 and 1114 through the contact pad 717. As further described in the aforementioned Challa et al. patent, the NXS protocol supports multiple memory integrated circuits by having each memory integrated circuit receive chip select address information through the serial terminal, decode the chip select address information using on-board logic, and self-activate when the decoded address matches the IC's static address. The static addresses of the integrated circuits 1112 and 1114 are established by connecting the A0, A1, A2 and A3 terminals to VCC and ground, as appropriate. Resistor 1102 is a pull-up resistor having a value of, for example, 10,000 ohms, and is useful in card insertion/removal detection. The resistor 1102 is connected between a detect control port DC and a write protect�card detect port WP\-DT\ of the controller 1100. The write protect�card detect port WP\-DT\ of the controller 1100 contacts pad 716 when the digital media card is inserted into it's socket.
Another set of illustrative pad assignments for the digital media device 700 using the NXS protocol (pad assignments for the digital media devices 500 and 600 are analogous) are as follows: VCC at pad 711, A3-1 at pad 712, SCK at pad 713, A3-0 at pad 714, GND and DT (card detect) at pad 715 (the digital media device 500 does not support DT), WP\-DT\ and A2 at pad 716, SIO at pad 717, and A1 at pad 718.
FIG. 12 is a block schematic diagram of illustrative electrical connections suitable for this set of illustrative pad assignments. VCC and ground are furnished to an NXS protocol digital media device 1210, which includes, illustratively, the contact pad array 710 (contact pad arrays 510 and 610 are analogous) through respective contact pads 711 and 715. The digital media device 1210 includes two NXS protocol memory integrated circuits 1212 and 1214 (alternatively, the digital media device 1210 may contain one memory integrated circuit or more than two memory integrated circuits). A controller 1200, which is any suitable controller, including, for example, general purpose microcontrollers, digital signal processors, and application-specific integrated circuit logic, furnishes its clock signal SCK to the SCK ports of the NXS protocol memory integrated circuits 1212 and 1214 through the contact pad 713, and its data signal SIO to the SI and SO ports of the NXS protocol memory integrated circuits 1212 and 1214 through the contact pad 717. As further described in the aforementioned Challa et al. patent, the NXS protocol supports multiple memory integrated circuits by having each memory integrated circuit receive chip select address information through the serial terminal, decode the chip select address information using on-board logic, and self-activate when the decoded address matches the IC's static address. The static addresses of the integrated circuits 1212 and 1214 are established by connecting the AO terminals to VCC and ground, as appropriate. The A1 and A3-0 and A3-1 terminals are brought out for test purposes, or optionally may be tied high or low. The A2 terminal it tied high through resistor 1202, which is a pull-up resistor having a value of, for example, 10,000 ohms, and is useful in card insertion/removal detection. The resistor 1202 is connected between a detect control port DC and a write protect�card detect port WP\-DT\ of the controller 1200. The write protect�card detect port WP\-DT\ of the controller 1200 contacts pad 716 when the digital media card is inserted into it's socket.
One set of illustrative pad assignments for the digital media device 700 using the SPI interface 700 are as follows: VCC at pad 711, CS0\ at pad 712, SCK at pad 713, CS1\ at pad 714, GND and DT at pad 715 (the digital media device 500 does not support DT), WP\ and DT\ at pad 716, SIO at pad 717, and RB (Ready/Busy) at pad 718.
FIG. 13 is a block schematic diagram of illustrative electrical connections suitable for this set of illustrative pad assignments. VCC and ground are furnished to an SPI protocol digital media device 1310, which includes, illustratively, the contact pad array 710 (contact pad arrays 510 and 610 are analogous) through respective contact pads 711 and 715. The digital media device 1110 includes two SPI protocol memory integrated circuits 1312 and 1314 (alternatively, the digital media device 1310 may contain one memory integrated circuit or more than two memory integrated circuits). A controller 1300, which is any suitable controller, furnishes its clock signal SCK to the SCK ports of the SPI protocol memory integrated circuits 1312 and 1314 through the contact pad 713, and its data signal SIO to the SIO port of the SPI protocol memory integrated circuits 1312 and 1314 through the contact pad 717. The SPI protocol supports multiple memory integrated circuits by having each memory integrated circuit activated by a specific chip select signal. Hence, memory integrated circuit 1312 is selected by signal CS0\ applied through pad 712, and memory integrated circuit 1314 is selected by signal CS1\ applied through pad 714. Resistor 1302 is a pull-up resistor having a value of, for example, 10,000 ohms, and is useful in card insertion/removal detection. The resistor 1302 is connected between a detect control port DC and a write protect�card detect port WP\-DT\ of the controller 1300. The write protect�card detect port WP\-DT\ of the controller 1300 contacts pad 716 when the digital media card is inserted into it's socket. A ready-busy port RB of the controller 1300 is connected to corresponding ports of the memory integrated circuits 1312 and 1314 through pad 718.
Another set of illustrative pad assignments for the digital media device 700 using the SPI interface 700 are as follows: VCC at pad 711, CS1\ at pad 712, SCK at pad 713, CS0\ at pad 714, GND and DT at pad 715 (the digital media device 500 does not support DT), WP\ and DT\ at pad 716, SO at pad 717, and SI at pad 718.
FIG. 14 is a block schematic diagram of illustrative electrical connections suitable for this set of illustrative pad assignments. VCC and ground are furnished to an SPI protocol digital media device 1410, which includes, illustratively, the contact pad array 710 (contact pad arrays 510 and 610 are analogous) through respective contact pads 711 and 715. The digital media device 1410 includes two SPI protocol memory integrated circuits 1412 and 1414 (alternatively, the digital media device 1410 may contain one memory integrated circuit or more than two memory integrated circuits). A controller 1400, which is any suitable controller, furnishes its clock signal SCK to the SCK ports of the SPI protocol memory integrated circuits 1412 and 1414 through the contact pad 713, and its data signals SO and SI to the SO and SI ports of the SPI protocol memory integrated circuits 1412 and 1414 through the contact pads 717 and 718, respectively. The SPI protocol supports multiple memory integrated circuits by having each memory integrated circuit activated by a specific chip select signal. Hence, memory integrated circuit 1412 is selected by signal CS0\ applied through pad 714, and memory integrated circuit 1414 is selected by signal CS1\ applied through pad 712. Resistor 1402 is a pull-up resistor having a value of, for example, 10,000 ohms, and is useful in card insertion/removal detection. The resistor 1402 is connected between a detect control port DC and a write protect�card detect port WP\-DT\ of the controller 1400. The write protect�card detect port WP\-DT\ of the controller 1400 contacts pad 716 when the digital media card is inserted into it's socket. Ready-busy ports of the memory integrated circuits 1412 and 1414 are not used, and are factory programmed as no-connect. However, they are tied to GND and VCC respectively.
Optional write protection is achieved using the GND-DT and WP\-DT\ ports. While the following functional description pertains to the NXS controller 1100 and digital media device 700, the NXS controller 1200, the SPI controllers 1300 and 1400, and digital media devices 500 and 600 function in an analogous manner. When write protection is desired, pad 726, which is electrically identical to pad 716, is shorted to pad 725, which is electrically identical to pad 715, using, for example, conductive tape, a conductive edge clip, or an integrated mechanical switch. When the digital media card 700 is inserted into a socket, the WP-DT port of the controller is pulled down, which is sensed as write protect by the controller 1110.
The digital media device 700 supports a card detection function with its unique arrangement of pads in the pad array 710. While the following functional description pertains to the NXS controller 1100, the NXS controller 1200 and the SPI controllers 1300 and 1400 controller 1200 function in an analogous manner unless otherwise mentioned. The detect control or DC port of the controller 1100 goes high at particular times to interrogate the socket. Illustratively, the DC port is periodically brought high for a brief period. If the card detect port or DT port of the controller 1100 is pulled up, it is an indication that no card is present in the socket or that a properly inserted card is present in the socket and is not write protected. A read is then attempted by sending a read opcode and static address on the port SIO for NXS protocol devices or by sending a chip select signal on CS0\ or CS1\ as appropriate and a read opcode on the port SIO (port SI of the controller 1400) for SPI protocol devices, and clocking port SCK. If the read is successful, a digital media device is properly installed and a transaction begins. If the read is not successful, no card is present. However, if the DT\ port is not pulled up, it is an indication that a card is present in the socket but is not properly inserted or that a properly inserted card is present in the socket and is write protected. A read is then attempted. If the read is successful, a write-protected digital media device is properly installed and a transaction begins. If the read is unsuccessful, an improperly inserted card is present and the controller 1100 signals an insertion error.
The digital media device 700 supports a card removal detection function with its unique arrangement of pads in the pad array 710. While the following functional description pertains to the NXS controller 1100, the NXS controller 1200 and the SPI controllers 1300 and 1400 function in an analogous manner. As the digital media device 700 is removed from its socket, pad 716 breaks contact with the WP\-DT\ port and the resistor 1102 pulls up the WP\-DT\ port for a relatively large number of clock cycles. This event is detected by the microcontroller 1100. Next, the ground pad 715 makes contact with the WP\-DT\ port and pulls it down for a relatively large number of clock cycles, an event which is also sensed by the microcontroller 1100. The sequence of a prolonged high and low drive of the WP\-DT\ port is interpreted by the microcontroller 1100 as a card removal operation, and the microcontroller 1100 then begins the process of powering down the interface circuits. During the power down operation, pads 717 and 718 break contact with their respective ports, which are protected since they contact only the non-conductive material of the body of the digital media device 700. Power-down is completed before any pads of the digital media device can come into improper contact with pads of the socket, thereby prevent damage to any circuits of the host or the digital media device.
Preferably, the digital media devices of the family 300 are fabricated using surface mount techniques or �Chip on Board� (�COB�) techniques. Digital media devices 310 and 320 of FIG. 3 and the digital media device 1500 of FIG. 15 are illustrative of surface mount techniques. COB techniques include a chip-on-board modular technique, of which the digital media devices 330, 340 and 350 of FIG. 3 and the digital media devices 1600 and 1700 of FIGS. 16 and 17 are illustrative, and a chip-on-board direct technique, of which the digital media device 360 of FIG. 3 and the digital media device 1800 of FIG. 18 are illustrative. The COB techniques are advantageous in that they are particularly inexpensive.
A digital media device incorporates multiple chips or integrated circuits (�IC�) to achieve greater memory capacity. When two or more chips or integrated circuits compliant with the NXS protocol as described in the aforementioned Challa et al. patent are used, they preferably share common power, ground clock, and data I/O buses. Static address terminals on the chips or integrated circuits are tied to or supplied with VCC or ground as appropriate to impart an address to them so that one of them can be selected in accordance with an address furnished over the data I/O bus. In contrast, the SPI protocol uses separate chip select ports.
As shown in FIG. 24, pin 8 of P1 is assigned to signal 5/3_SEL, which provides dual voltage control (5.0V and 3.3V) via the bit 6 of the parallel port. Pin 7 of P1 is assigned to signal SHUTDOWN, which provides power control via the setting bit 5 on the parallel port. Pin 4 of P1 is assigned to signal CS0, which is a chip select signal common to both GSM or DIP flash memory package types at location device 0. Pin 9 of P1 is assigned to signal CS1, which is another chip select signal for GSM to accommodate a digital media device containing two integrated circuits. A jumper JP1 selects CS1 to TSOP or DIP flash memory package type at the location of device 1. A jumper JP2 selects either low voltage AC or low voltage DC input. A voltage regulator U5 is included. A jumper JP3 selects VDD from either UNREG, which is an external power source, or REG, which is an internal DC voltage regulator. Pin 10 of P1 is assigned to signal WP_DET for device detection.
The adapter 2400 includes various chip sockets U1, U2 and U3 for additional flexibility, and is particularly suitable for use as a development kit. However, the chip sockets U1, U2 and U3 may be omitted and the adapter 2400 packaged with or without the regulator U5 for consumer use, as shown by the adapter 2340 of FIG. 23, which is shown plugged into the parallel port of the laptop computer 2310 and receiving digital media device 2350. It will be appreciated that a �mapping� type adapter may also be packaged in a PC card shell that plugs into the PCMCIA port of the laptop 2310 and receives one or more digital media devices, provided appropriate software is installed on the laptop computer 2310 for controlling access to the digital media device(s).
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ClassificationG06F13/40, G11C19/08, G11C5/06Cooperative ClassificationG06K19/07732, Y02B60/1235, G06K19/07743, Y02B60/1228, G06K19/07741, G06K7/0021, G06F13/409, G11C5/066, G11C2216/30European ClassificationG06F13/40E4, G06K19/077K, G06K7/00K2, G06K19/077G4, G06K19/077E7, G11C5/06MLegal EventsDateCodeEventDescriptionJun 20, 2012FPAYFee paymentYear of fee payment: 12Jul 3, 2008FPAYFee paymentYear of fee payment: 8Mar 2, 2006ASAssignmentOwner name: WINBOND ELECTRONICS CORPORATION, TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEXFLASH TECHNOLOGIES, INC.;REEL/FRAME:017297/0984Effective date: 20060222Jun 9, 2004FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google