Source: http://www.google.com/patents/US7900104?dq=5,371,548
Timestamp: 2016-08-30 07:55:15
Document Index: 311365721

Matched Legal Cases: ['Application No. 60', 'Application No. 04', 'Application No. 00', 'Application No. 00', 'Application No. 04', 'Application No. 04', 'Application No. 00', 'Application No. 04', 'Application No. 2001', 'Application No. 2001', 'Application No. 00']

Patent US7900104 - Test pattern compression for an integrated circuit test environment - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied...http://www.google.com/patents/US7900104?utm_source=gb-gplus-sharePatent US7900104 - Test pattern compression for an integrated circuit test environmentAdvanced Patent SearchPublication numberUS7900104 B2Publication typeGrantApplication numberUS 12/405,409Publication dateMar 1, 2011Filing dateMar 17, 2009Priority dateNov 23, 1999Fee statusPaidAlso published asDE60018101D1, DE60018101T2, DE60030896D1, DE60030896T2, EP1236111A1, EP1236111A4, EP1236111B1, US6327687, US6543020, US7111209, US7509546, US20020053057, US20030131298, US20070016836, US20090259900, WO2001038981A1Publication number12405409, 405409, US 7900104 B2, US 7900104B2, US-B2-7900104, US7900104 B2, US7900104B2InventorsJanusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jerzy TyszerOriginal AssigneeMentor Graphics CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (162), Non-Patent Citations (93), Referenced by (12), Classifications (12), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetTest pattern compression for an integrated circuit test environment
US 7900104 B2Abstract
1. A computer-readable medium storing computer-executable instructions for causing a computer to perform a method for computing a compressed test pattern for testing an integrated circuit, the method comprising:
generating symbolic expressions that are associated with scan cells, the symbolic expressions being a function of input variables to be applied concurrently while the scan cells are being loaded;
3. The computer-readable medium of claim 1, wherein the method further includes solving the equations to obtain the compressed test pattern and, after solving the equations, incrementally appending the set of equations with one or more equations.
4. The computer-readable medium of claim 3, wherein the method further includes:
(c) if the attempt to solve the equations is successful, incrementally appending additional equations onto the set of equations; and
5. The computer-readable medium of claim 1, wherein generating symbolic expressions includes:
6. The computer-readable medium of claim 5, wherein the method further includes assigning each of the output expressions to each scan cell within a scan chain in the integrated circuit.
7. The computer-readable medium of claim 1, wherein the method further includes solving the equations and wherein solving the equations includes performing a Gauss-Jordon elimination method for solving equations.
8. The computer-readable medium of claim 1, wherein the method further includes generating a test cube includes assigning values of a predetermined logic 1 or a predetermined logic 0 to the scan cells for testing a fault in the integrated circuit.
9. The computer-readable medium of claim 1, wherein formulating the set of equations includes:
10. The computer-readable medium of claim 1, wherein generating symbolic expressions includes using simulation of a decompressor or a mathematical representation of a decompressor.
11. A system for computing a compressed test pattern for testing an integrated circuit design, the system comprising:
means for generating symbolic expressions that are associated with scan cells, the symbolic expressions being a function of input variables to be applied concurrently while the scan cells are being loaded;
means for generating a test cube having the scan cells assigned predetermined values; and
means for formulating a set of equations by equating the assigned values in the scan cells to the symbolic expressions.
12. A computer-readable medium storing computer-executable instructions for causing a computer to perform a method, the method comprising:
(c) if the attempt to solve the equations fails, deleting a most recently appended equation;
(e) repeating (b), (c) and (d) to generate a final set of equations; and
13. The computer-readable medium of claim 12, wherein the repeating occurs until a predetermined limiting criteria is reached.
14. The computer-readable medium of claim 12, wherein the method further includes generating symbolic expressions associated with scan cells within the integrated circuit, the symbolic expressions being associated with input variables to be applied concurrently while the scan cells are being loaded.
15. The computer-readable medium of claim 14, wherein the method further includes generating symbolic expressions including:
16. The computer-readable medium of claim 15, wherein the method further includes assigning each of the output expressions to each scan cell within a scan chain in the integrated circuit.
17. The computer-readable medium of claim 12, wherein solving the equations includes performing a Gauss-Jordon elimination method for solving equations.
18. The computer-readable medium of claim 12, wherein the method further includes generating a test cube including assigning values of a predetermined logic 1 or a predetermined logic 0 to scan cells for testing a fault in the integrated circuit.
19. The computer-readable medium of claim 12, wherein the method further includes:
(c) loading scan cells within the integrated circuit with the decompressed test pattern, wherein (a), (b) and (c) occur substantially concurrently.
20. The computer-readable medium of claim 12, wherein generating the final set of equations includes:
21. The computer-readable medium of claim 12, wherein the method further includes generating symbolic expressions that are associated with scan cells in the integrated circuit, wherein generating symbolic expressions includes using a mathematical representation of a decompressor. Description
This application is a continuation of U.S. patent application Ser. No. 11/523,111 filed Sep. 18, 2006, now U.S. Pat. No. 7,509,546, which is a continuation of U.S. patent application Ser. No. 10/355,941 filed Jan. 31, 2003, now U.S. Pat. No. 7,111,209, which is a continuation of U.S. patent application Ser. No. 09/947,160 filed Sep. 4, 2001, now U.S. Pat. No. 6,543,020, which is a continuation of U.S. patent application Ser. No. 09/619,985 filed Jul. 20, 2000, now U.S. Pat. No. 6,327,687, which claims the benefit of U.S. Provisional Application No. 60/167,446 filed Nov. 23, 1999, all of which are hereby incorporated by reference.
Another compression method is based on reseeding of multiple polynomial LFSRs (MP-LFSRs) as proposed in S. Hellebrand et al., “Built-In Test For Circuits With Scan Based On Reseeding of Multiple Polynomial Linear Feedback Shift Registers,” IEEE Trans. On Computers, vol. C-44, pp. 223-233 (1995). In this method, a concatenated group of test cubes is encoded with a number of bits specifying a seed and a polynomial identifier. The content of the MP-LFSR is loaded for each test group and has to be preserved during the decompression of each test cube within the group. The implementation of the decompressor involves adding extra memory elements to avoid overwriting the content of the MP-LFSR during the decompression of a group of test patterns. A similar technique has been also discussed in S. Hellebrand et al., “Pattern generation for a deterministic BIST scheme,” Proc. ICCAD, pp. 88-94 (1995). Reseeding of MP-LFSRs was further enhanced by adopting the concept of variable-length seeds as described in J. Rajski et al., “Decompression of test data using variable-length seed LFSRs”, Proc. VLSI Test Symposium, pp-426-433 (1995) and in J. Rajski et al., “Test Data Decompression for Multiple Scan Designs with Boundary Scan”, IEEE Trans. on Computers, vol. C-47, pp. 1188-1200 (1998). This technique has a potential for significant improvement of test pattern encoding efficiency, even for test cubes with highly varying number of specified positions. The same documents propose decompression techniques for circuits with multiple scan chains and mechanisms to load seeds into the decompressor structure through the boundary-scan. Although this scheme significantly improves encoding capability, it still suffers from the two drawbacks noted above: seed-length limitations and mutually exclusive times for loading the seed and generating test patterns therefrom.
To reduce the data volume of the test response and the time for sending the response to the tester, the circuit 34 can include means for compressing the test response that is read from the scan chains 26. One structure for providing such compression is one or more spatial compactors 38. The compressed test responses produced by the compactors 38 are then compared one by one with compressed reference responses 41. A fault is detected if a reference response does not match an actual response.
TABLE 5 7 6 5 4 3 2 1 0 0 0 a1 0 0 0 a2 0 0 0 a3 a1 0 0 a4 a2 a2 0 a5 a2 ⊕ a3 a1 0 a6 a4 a4 a2 a7 a4 ⊕ a5 a2 ⊕ a3 a1 a8 a6 a6 a2 ⊕ a4 a2 ⊕ a9 a6 ⊕ a7 a4 ⊕ a5 a2 ⊕ a1 ⊕ a10 a8 a3 a8 a2 ⊕ a4 ⊕ a6 a2 ⊕ a4 ⊕ a2 ⊕ a8 ⊕ a6 ⊕ a7 a4 ⊕ a2 ⊕ a3 ⊕ a1 ⊕ a10 a11 a9 a5 a12 a1 ⊕ a2 ⊕ a4 ⊕ a6 ⊕ a2 ⊕ a4 ⊕ a6 ⊕ a1 ⊕ a2 ⊕ a2 ⊕ a8 ⊕ a6 ⊕ a4 ⊕ a5 ⊕ a2 ⊕ a3 ⊕ a10 a8 a13 a4 ⊕ a10 ⊕ a9 a7 a14 a12 a11 Once the symbolic expressions are determined, a system of equations is formulated for each test cube. These equations are obtained by selecting the symbolic expressions corresponding to specified positions of the test cubes (they form the left-hand sides of the equations) and assigning values of these specified positions to the respective expressions. Thus, the right-hand sides of the equations are defined by the specified positions in the partially specified test patterns. As can be seen, the process of finding an appropriate encoding of a given test cube is equivalent to solving a system of linear equations in the Galois field modulo 2. Solving the equations can be carried out very efficiently using Gauss-Jordan elimination by taking advantage of fast bit-wise operations. If the system of linear equations has a solution, it can be treated as a compressed test pattern, i.e. having the property that when provided to the decompressor yields the decompressed test pattern consistent with the initial, partially specified test vector. In order to increase probability of successful encoding, it is desirable to generate test cubes with the smallest achievable number of specified positions. Consequently, it will reduce the number of equations while maintaining the same number of input variables, and thus increasing likelihood of compression.
a2 ⊕ a4 ⊕ a6 a2 ⊕ a6 ⊕ a9 a2 ⊕ a3 ⊕ a4 ⊕ a5 ⊕ a6 ⊕ a7 a4 ⊕ a5 ⊕ a8 a2 ⊕ a4 ⊕ a6 ⊕ a8 a2 ⊕ a4 ⊕ a8 ⊕ a11 a2 ⊕ a4 ⊕ a5 ⊕ a6 ⊕ a7 ⊕
a1 ⊕ a6 ⊕ a7 ⊕ a10 a8 ⊕ a9 a1 ⊕ a2 ⊕ a4 ⊕ a6 ⊕
a1 ⊕ a2 ⊕ a4 ⊕ a6 ⊕
a1 ⊕ a4 ⊕ a6 ⊕ a7 ⊕ a8 ⊕ a9 ⊕
a3 ⊕ a8 ⊕ a9 ⊕ a12 a8 ⊕ a10 a10 ⊕ a13 a10 ⊕ a11 For the sake of illustration, consider an example 8-bit decompressor with two external inputs that drives four 10-bit scan chains as shown in FIG. 10. If this circuit is to generate a test pattern based on the following partially specified test cube (the contents of the four scan chains are shown here horizontally) shown in Table 7:
TABLE 8 a1 ⊕ a2 ⊕ a5 ⊕ a8 ⊕ a9 ⊕ a11 = 0 a5 ⊕ a6 ⊕ a7 ⊕ a9 ⊕ a10 ⊕ a11 ⊕ a12 ⊕ a13 ⊕ a15 ⊕ a18 ⊕ a19 ⊕ a20 ⊕ a21 ⊕ a23 ⊕ a24 = 1 a0 ⊕ a1 ⊕ a3 ⊕ a4 ⊕ a5 ⊕ a6 ⊕ a7 ⊕ a9 ⊕ a12 ⊕ a13 ⊕ a14 ⊕ a15 ⊕ a17 ⊕ a18 = 0 a0 ⊕ a1 ⊕ a3 ⊕ a6 ⊕ a7 ⊕ a8 ⊕ a9 ⊕ a11 ⊕ a12 = 1 a0 ⊕ a1 ⊕ a2 ⊕ a3 ⊕ a5 ⊕ a8 ⊕ a9 ⊕ a10 ⊕ a11 ⊕ a13 ⊕ a14 = 1 a0 ⊕ a1 ⊕ a2 ⊕ a3 ⊕ a4 ⊕ a5 ⊕ a6 ⊕ a11 ⊕ a12 = 1 a0 ⊕ a1 ⊕ a2 ⊕ a7 ⊕ a8 = 1 a4 ⊕ a5 ⊕ a7 ⊕ a8 ⊕ a11 ⊕ a14 ⊕ a15 ⊕ a17 = 1 a1 ⊕ a4 ⊕ a5 ⊕ a12 ⊕ a13 ⊕ a15 ⊕ a16 ⊕ a19 ⊕ a22 ⊕ a23 ⊕ a25 = 0 a2 ⊕ a3 ⊕ a10 ⊕ a11 ⊕ a13 ⊕ a14 ⊕ a17 ⊕ a20 ⊕ a21 ⊕ a23 = 0 It can be verified that the resulting input variables a2, a3, a6 and a12 are equal to the value of one while the remaining variables assume the value of zero. This seed will subsequently produce a fully specified test pattern in the following form (the initial specified position are now underlined) shown in Table 9:
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS519078Aug 22, 1893May 1, 1894 Martin middleton wilsonUS713605Nov 13, 1899Nov 18, 1902Gen ElectricTransformer.US3614400Nov 26, 1969Oct 19, 1971Rca CorpMaximum length pulse sequence generatorsUS3700869Dec 4, 1970Oct 24, 1972NasaPseudonoise sequence generators with three-tap linear feedback shift registersUS4024460Jul 7, 1975May 17, 1977Hewlett-Packard CompanyElectronic line stretcherUS4122399Dec 7, 1977Oct 24, 1978Bell Telephone Laboratories, IncorporatedDistortion generatorUS4161041Oct 6, 1978Jul 10, 1979The United States Of America As Represented By The Secretary Of The Air ForcePseudo random number generator apparatusUS4320509Oct 19, 1979Mar 16, 1982Bell Telephone Laboratories, IncorporatedLSI Circuit logic structure including data compression circuitryUS4503537Nov 8, 1982Mar 5, 1985International Business Machines CorporationParallel path self-testing systemUS4513418Nov 8, 1982Apr 23, 1985International Business Machines CorporationSimultaneous self-testing systemUS4536881Oct 27, 1983Aug 20, 1985Nippon Electric Co., Ltd.Integrated logic circuit adapted to performance testsUS4602210Dec 28, 1984Jul 22, 1986General Electric CompanyMultiplexed-access scan testable integrated circuitUS4687988Jun 24, 1985Aug 18, 1987International Business Machines CorporationWeighted random pattern testing apparatus and methodUS4754215Nov 5, 1986Jun 28, 1988Nec CorporationSelf-diagnosable integrated circuit device capable of testing sequential circuit elementsUS4785410Jun 2, 1986Nov 15, 1988Clarion Co., Ltd.Maximum length shift register sequences generatorUS4801870Feb 1, 1988Jan 31, 1989International Business Machines CorporationWeighted random pattern testing apparatus and methodUS4827476Apr 16, 1987May 2, 1989Tandem Computers IncorporatedScan test apparatus for digital systems having dynamic random access memoryUS4860236Oct 26, 1987Aug 22, 1989University Of ManitobaCellular automaton for generating random dataUS4910735Dec 17, 1987Mar 20, 1990Fujitsu LimitedSemiconductor integrated circuit with self-testingUS4959832Dec 9, 1988Sep 25, 1990International Business MachinesParallel pseudorandom pattern generator with varying phase shiftUS4974184Apr 19, 1990Nov 27, 1990Honeywell Inc.Maximum length pseudo-random test pattern generator via feedback network modificationUS5072178Jun 4, 1990Dec 10, 1991Hitachi, Ltd.Method and apparatus for testing logic circuitry by applying a logical test patternUS5090035Jan 22, 1991Feb 18, 1992Nec CorporationLinear feedback shift registerUS5138619Feb 15, 1990Aug 11, 1992National Semiconductor CorporationBuilt-in self test for integrated circuit memoryUS5167034Nov 19, 1990Nov 24, 1992International Business Machines CorporationData integrity for compaction devicesUS5173906Aug 31, 1990Dec 22, 1992Dreibelbis Jeffrey HBuilt-in self test for integrated circuitsUS5202889Nov 13, 1990Apr 13, 1993International Business Machines CorporationDynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designsUS5258986Sep 19, 1990Nov 2, 1993Vlsi Technology, Inc.Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memoriesUS5268949Aug 31, 1992Dec 7, 1993Ando Electric Co., Ltd.Circuit for generating M-sequence pseudo-random patternUS5293123Sep 4, 1992Mar 8, 1994Tandem Computers IncorporatedPseudo-Random scan test apparatusUS5301199Dec 15, 1992Apr 5, 1994Nippon Telegraph And Telephone CorporationBuilt-in self test circuitUS5325367Aug 22, 1991Jun 28, 1994U.S. Philips CorporationMemory device containing a static ram memory that is adapted for executing a self-test, and integrated circuit containing such a device as an embedded static ram memoryUS5349587Mar 26, 1992Sep 20, 1994Northern Telecom LimitedMultiple clock rate test apparatus for testing digital systemsUS5369648Nov 8, 1991Nov 29, 1994Ncr CorporationBuilt-in self-test circuitUS5394405Apr 24, 1992Feb 28, 1995International Business Machines CorporationUniversal weight generatorUS5412665Jan 10, 1992May 2, 1995International Business Machines CorporationParallel operation linear feedback shift registerUS5414716Sep 22, 1993May 9, 1995Mitsubishi Electronic Research Laboratories, Inc.Weighting system for testing of circuits utilizing determination of undetected faultsUS5416783Aug 9, 1993May 16, 1995Motorola, Inc.Method and apparatus for generating pseudorandom numbers or for performing data compression in a data processorUS5444716Aug 30, 1993Aug 22, 1995At&T Corp.Boundary-scan-based system and method for test and diagnosisUS5446683Mar 31, 1994Aug 29, 1995Hewlett-Packard CompanyMethods and apparatus for generating pseudo-random binary patternsUS5450414May 17, 1993Sep 12, 1995At&T Corp.Partial-scan built-in self-testing circuit having improved testabilityUS5524114Oct 22, 1993Jun 4, 1996Lsi Logic CorporationMethod and apparatus for testing semiconductor devices at speedUS5533128Jan 18, 1995Jul 2, 1996Vobach; ArnoldPseudo-random transposition cipher system and methodUS5553082May 1, 1995Sep 3, 1996International Business Machines CorporationBuilt-in self-test for logic circuitry at memory array outputUS5574733Jul 25, 1995Nov 12, 1996Intel CorporationScan-based built-in self test (BIST) with automatic reseeding of pattern generatorUS5586125Nov 22, 1994Dec 17, 1996Warner; William T.Method for generating test vectors for characterizing and verifying the operation of integrated circuitsUS5588006Oct 21, 1993Dec 24, 1996Kabushiki Kaisha ToshibaLogic circuit having a control signal switching logic function and having a testing arrangementUS5592493Sep 13, 1994Jan 7, 1997Motorola Inc.Serial scan chain architecture for a data processing system and method of operationUS5608870Jun 2, 1995Mar 4, 1997The President And Fellows Of Harvard CollegeSystem for combining a plurality of requests referencing a common target address into a single combined request having a single reference to the target addressUS5612963Jun 7, 1995Mar 18, 1997International Business Machines CorporationHybrid pattern self-testing of integrated circuitsUS5614838Nov 3, 1995Mar 25, 1997International Business Machines CorporationReduced power apparatus and method for testing high speed componentsUS5617531Jul 10, 1995Apr 1, 1997Motorola, Inc.Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processorUS5631913Feb 8, 1995May 20, 1997Matsushita Electric Industrial Co., Ltd.Test circuit and test method of integrated semiconductor deviceUS5642362Jul 20, 1994Jun 24, 1997International Business Machines CorporationScan-based delay tests having enhanced test vector pattern generationUS5668817Jul 11, 1996Sep 16, 1997Northern Telecom LimitedSelf-testable digital signal processor and method for self-testing of integrating circuits including DSP data pathsUS5680543Oct 20, 1995Oct 21, 1997Lucent Technologies Inc.Method and apparatus for built-in self-test with multiple clock circuitsUS5694401Jan 22, 1997Dec 2, 1997Tandem Computers IncorporatedFault isolation using pseudo-random scanUS5694402Oct 22, 1996Dec 2, 1997Texas Instruments IncorporatedSystem and method for structurally testing integrated circuit devicesUS5701308Oct 29, 1996Dec 23, 1997Lockheed Martin CorporationFast bist architecture with flexible standard interfaceUS5701309Dec 2, 1992Dec 23, 1997At&T Global Information Solutions CompanyAutomated test equipment digital tester expansion apparatusUS5717701Aug 13, 1996Feb 10, 1998International Business Machines CorporationApparatus and method for testing interconnections between semiconductor devicesUS5717702Nov 19, 1996Feb 10, 1998Hughes ElectronicsScan testing digital logic with differing frequencies of system clock and test clockUS5719913Jul 25, 1996Feb 17, 1998Mitsubishi Denki Kabushiki KaishaPseudo-random number generating circuit and bidirectional shift registerUS5748497Oct 31, 1994May 5, 1998Texas Instruments IncorporatedSystem and method for improving fault coverage of an electric circuitUS5761489Apr 17, 1995Jun 2, 1998Motorola Inc.Method and apparatus for scan testing with extended test vector storage in a multi-purpose memory systemUS5790562May 6, 1996Aug 4, 1998General Motors CorporationCircuit with built-in test and method thereofUS5790626Sep 10, 1996Aug 4, 1998Hewlett-Packard CompanyBi-directional linear feedback shift registerUS5812561Sep 3, 1996Sep 22, 1998Motorola, Inc.Scan based testing of an integrated circuit for compliance with timing specificationsUS5831992Oct 9, 1997Nov 3, 1998Northern Telecom LimitedMethods and apparatus for fault diagnosis in self-testable systemsUS5848198Jan 12, 1995Dec 8, 1998Penn; Alan IrvinMethod of and apparatus for analyzing images and deriving binary image representationsUS5867507Dec 12, 1995Feb 2, 1999International Business Machines CorporationTestable programmable gate array and associated LSSD/deterministic test methodologyUS5870476Aug 23, 1996Feb 9, 1999Thomson Multimedia S.A.Process for pledging data for a secure data exchange protocolUS5872793Aug 21, 1997Feb 16, 1999Lockheed Martin CorporationFast bist architecture with flexible standard interfaceUS5883906Aug 15, 1997Mar 16, 1999Advantest Corp.Pattern data compression and decompression for semiconductor test systemUS5899961Mar 4, 1997May 4, 1999Hewlett-Packard CompanyElectronic circuit or board tester with compressed data-sequencesUS5905986Jan 7, 1997May 18, 1999Hewlett-Packard CompanyHighly compressible representation of test pattern dataUS5938784Oct 15, 1997Aug 17, 1999Samsung Electronics, Co., Ltd.Linear feedback shift register, multiple input signature register, and built-in self test circuit using such registersUS5968194Mar 31, 1997Oct 19, 1999Intel CorporationMethod for application of weighted random patterns to partial scan designsUS5974179Feb 13, 1995Oct 26, 1999Integrated Device Technology, Inc.Binary image data compression and decompressionUS5974433Jun 29, 1984Oct 26, 1999Currie; Robert JohnHigh speed M-sequence generator and decoder circuitUS5983380Sep 16, 1997Nov 9, 1999International Business Machines CorporationWeighted random pattern built-in self-testUS5991898Mar 10, 1997Nov 23, 1999Mentor Graphics CorporationArithmetic built-in self test of multiple scan-based integrated circuitsUS5991909Oct 15, 1996Nov 23, 1999Mentor Graphics CorporationParallel decompressor and related methods and apparatusesUS6006349Jul 26, 1996Dec 21, 1999Advantest CorporationHigh speed pattern generating method and high speed pattern generator using the methodUS6014763Jan 15, 1998Jan 11, 2000International Business Machines CorporationAt-speed scan testingUS6021513Oct 28, 1998Feb 1, 2000International Business Machines CorporationTestable programmable gate array and associated LSSD/deterministic test methodologyUS6026508Apr 22, 1997Feb 15, 2000International Business Machines CorporationStorage sub-system compression and dataflow chip offering excellent data integrityUS6029263Jun 30, 1994Feb 22, 2000Tandem Computers IncorporatedInterconnect testing using non-compatible scan architecturesUS6041429Aug 4, 1993Mar 21, 2000International Business Machines CorporationSystem for test data storage reductionUS6055658Oct 2, 1995Apr 25, 2000International Business Machines CorporationApparatus and method for testing high speed components using low speed test apparatusUS6061818May 8, 1998May 9, 2000The Board Of Trustees Of The Leland Stanford Junior UniversityAltering bit sequences to contain predetermined patternsUS6072823Jun 9, 1997Jun 6, 2000Matsushita Electric Industrial Co., Ltd.Pseudo-random noise series generatorUS6100716Sep 17, 1998Aug 8, 2000Nortel Networks CorporationVoltage excursion detection apparatusUS6122761Aug 26, 1998Sep 19, 2000Samsung Electronics Co., Ltd.IC chip tester using compressed digital test data and a method for testing IC chip using the testerUS6141669May 6, 1998Oct 31, 2000Nortel Networks CorporationPseudorandom binary sequence block shifterUS6148425Feb 12, 1998Nov 14, 2000Lucent Technologies Inc.Bist architecture for detecting path-delay faults in a sequential circuitUS6158032Mar 27, 1998Dec 5, 2000International Business Machines CorporationData processing system, circuit arrangement and program product including multi-path scan interface and methods thereofUS6178532Jun 11, 1998Jan 23, 2001Micron Technology, Inc.On-chip circuit and method for testing memory devicesUS6181164May 13, 1999Jan 30, 2001Xilinx, Inc.Linear feedback shift register in a programmable gate arrayUS6199182Mar 27, 1998Mar 6, 2001Texas Instruments IncorporatedProbeless testing of pad buffers on waferUS6240432Dec 28, 1998May 29, 2001Vanguard International Semiconductor CorporationEnhanced random number generatorUS6256759Jun 15, 1998Jul 3, 2001Agere Systems Inc.Hybrid algorithm for test point selection for scan-based BISTUS6256760Nov 13, 1998Jul 3, 2001Nortel Networks LimitedAutomatic test equipment scan test enhancementUS6272653Nov 13, 1998Aug 7, 2001Intrinsity, Inc.Method and apparatus for built-in self-test of logic circuitryUS6286119Dec 22, 1998Sep 4, 2001Nortel Networks LimitedDelay fault testing with IEEE 1149.1US6300885Apr 14, 2000Oct 9, 2001International Business Machines CorporationDual aldc decompressors inside printer asicUS6308291Sep 18, 1998Oct 23, 2001Siemens Aktiengesellschaft AgMethod for testing an electronic circuitUS6327685May 12, 1999Dec 4, 2001International Business Machines CorporationLogic built-in self testUS6327687 *Jul 20, 2000Dec 4, 2001Janusz RajskiTest pattern compression for an integrated circuit test environmentUS6330681Dec 22, 1998Dec 11, 2001Logicvision, Inc.Method and apparatus for controlling power level during BISTUS6353842 *Jul 20, 2000Mar 5, 2002Janusz RajskiMethod for synthesizing linear finite state machinesUS6385750Sep 1, 1999May 7, 2002Synopsys, Inc.Method and system for controlling test data volume in deterministic test pattern generationUS6463560Jun 23, 1999Oct 8, 2002Agere Systems Guardian Corp.Method for implementing a bist scheme into integrated circuits for testing RTL controller-data paths in the integrated circuitsUS6467058Sep 3, 1999Oct 15, 2002Nec Usa, Inc.Segmented compaction with pruning and critical fault eliminationUS6510398Jun 22, 2000Jan 21, 2003Intel CorporationConstrained signature-based testUS6539409Sep 18, 2001Mar 25, 2003Janusz RajskiMethod for synthesizing linear finite state machinesUS6543020Sep 4, 2001Apr 1, 2003Janusz RajskiTest pattern compression for an integrated circuit test environmentUS6557129 *Jul 20, 2000Apr 29, 2003Janusz RajskiMethod and apparatus for selectively compacting test responsesUS6590929Jun 8, 1999Jul 8, 2003International Business Machines CorporationMethod and system for run-time logic verification of operations in digital systemsUS6611933Apr 12, 2000Aug 26, 2003International Business Machines CorporationReal-time decoder for scan test patternsUS6618826Oct 26, 2000Sep 9, 2003Cadence Design Systems, Inc.Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port RAMsUS6684358 *Nov 15, 2000Jan 27, 2004Janusz RajskiDecompressor/PRPG for applying pseudo-random and deterministic test patternsUS6694466Oct 27, 1999Feb 17, 2004Agere Systems Inc.Method and system for improving the test quality for scan-based BIST using a general test application schemeUS6708192Jan 16, 2003Mar 16, 2004Janusz RajskiMethod for synthesizing linear finite state machinesUS6763488Mar 9, 2001Jul 13, 2004Texas Instruments IncorporatedGenerator/compactor scan circuit low power adapter with counterUS6829740Jan 29, 2003Dec 7, 2004Janusz RajskiMethod and apparatus for selectively compacting test responsesUS6874109 *Nov 15, 2000Mar 29, 2005Janusz RajskiPhase shifter with reduced linear dependencyUS7001461Sep 8, 2003Feb 21, 2006Advanced Lcd Technologies Development Center Co., Ltd.Crystallization apparatus, crystallization method, and phase shifterUS7093175Dec 15, 2003Aug 15, 2006Janusz RajskiDecompressor/PRPG for applying pseudo-random and deterministic test patternsUS7111209Jan 31, 2003Sep 19, 2006Janusz RajskiTest pattern compression for an integrated circuit test environmentUS7188286Sep 1, 2004Mar 6, 2007On-Chip Technologies, Inc.Accelerated scan circuitry and method for reducing scan test data volume and execution timeUS7197681Jan 5, 2004Mar 27, 2007On-Chip Technologies, Inc.Accelerated scan circuitry and method for reducing scan test data volume and execution timeUS7260591Feb 17, 2004Aug 21, 2007Janusz RajskiMethod for synthesizing linear finite state machinesUS7263641Aug 3, 2004Aug 28, 2007Janusz RajskiPhase shifter with reduced linear dependencyUS7478296Jan 29, 2003Jan 13, 2009Janusz RajskiContinuous application and decompression of test patterns to a circuit-under-testUS7493540 *Jul 20, 2000Feb 17, 2009Jansuz RajskiContinuous application and decompression of test patterns to a circuit-under-testUS7500163Oct 25, 2004Mar 3, 2009Janusz RajskiMethod and apparatus for selectively compacting test responsesUS7506232Aug 11, 2006Mar 17, 2009Janusz RajskiDecompressor/PRPG for applying pseudo-random and deterministic test patternsUS7509546Sep 18, 2006Mar 24, 2009Janusz RajskiTest pattern compression for an integrated circuit test environmentUS7523372Aug 27, 2007Apr 21, 2009Janusz RajskiPhase shifter with reduced linear dependencyUS7563641Jul 21, 2009Harvatek CorporationLaminated light-emitting diode display device and manufacturing method thereofUS7610539 *Nov 5, 2008Oct 27, 2009Nec Laboratories America, Inc.Method and apparatus for testing logic circuit designsUS7610540 *Oct 27, 2009Nec Laboratories America, Inc.Method for generating, from a test cube set, a generator configured to generate a test patternUS7653851Jan 26, 2010Janusz RajskiPhase shifter with reduced linear dependencyUS20020112199Mar 9, 2001Aug 15, 2002Whetsel Lee D.Adapting scan-bist architectures for low power operationUS20020124217Dec 4, 2001Sep 5, 2002Fujitsu LimitedTesting apparatus and testing method for an integrated circuit, and integrated circuitUS20030120988Jan 29, 2003Jun 26, 2003Janusz RajskiContinuous application and decompression of test patterns to a circuit-under-testUS20030131298Jan 31, 2003Jul 10, 2003Mentor Graphics CorporationTest pattern compression for an integrated circuit test environmentUS20040128599Dec 15, 2003Jul 1, 2004Mentor Graphics CorporationDecompressor/PRPG for applying pseudo-random and deterministic test patternsUS20040172431Feb 17, 2004Sep 2, 2004Mentor Graphics CorporationMethod for synthesizing linear finite state machinesUS20050015688Aug 3, 2004Jan 20, 2005Janusz RajskiPhase shifter with reduced linear dependencyUS20050097419Oct 25, 2004May 5, 2005Mentor Graphics CorporationMethod and apparatus for selectively compacting test reponsesEP0108256B1Oct 5, 1983May 13, 1987International Business Machines CorporationSelf-testing method for logic circuitryEP0372226A2Nov 3, 1989Jun 13, 1990International Business Machines CorporationParallel pseudorandom pattern generator with varying phase shift and method for simulating such a generatorEP0438322A3Jan 21, 1991Nov 19, 1992Nec CorporationLinear feedback shift registerEP0481097B1Sep 15, 1990Jun 14, 1995International Business Machines CorporationMethod and apparatus for testing a VLSI deviceEP0549949B1Dec 15, 1992Mar 11, 1998Nippon Telegraph And Telephone CorporationBuilt-in self test circuitEP0887930A3Jan 28, 1998May 10, 2000Motorola, Inc.Signal processing apparatus and method for processing signalsEP1236111B1Nov 15, 2000Feb 9, 2005Mentor Graphics CorporationTest pattern compression for an integrated circuit test environmentEP1475643A1Nov 15, 2000Nov 10, 2004Mentor Graphics CorporationTest pattern compression for an integrated circuit test environmentEP1475643B1Nov 15, 2000Sep 20, 2006Mentor Graphics CorporationTest pattern compression for an integrated circuit test environmentJP3920640B2 Title not available* Cited by examinerNon-Patent CitationsReference1Aitken et al., "A Diagnosis Method Using Pseudo-Random Vectors Without Intermediate Signatures," Proc. ICCAD, pp. 574-577 (1989).2Bardell et al., "Pseudorandom arrays for built-in tests," IEEE Trans. on Computers, vol. C-35, No. 6, pp. 653-658 (1986).3Bardell et al., "Pseudorandom Sequence Generators," in Built in test for VLSI: Pseudorandom Techniques, Chapter 3, pp. 61-88 (1987).4Bardell et al., "Test Response Compression Techniques," in Built-In Test for VLSI Pseudorandom Techniques, Chapter 4, pp. 89-108 (1987).5Bardell, "Design Considerations for Parallel Pseudorandom Pattern Generators", Journal of Electronic Testing: Theory and Applications, vol. 1, pp. 73-87 (1990).6Bassett et al., "Low-Cost Testing of High-Density Logic Components," IEEE Design & Test of Computers, pp. 15-28 (Apr. 1990).7Benowitz et al., "An Advanced Fault Isolation System for Digital Logic," IEEE Trans. on Computers, vol. C-24, No. 5, pp. 489-497 (May 1975).8Bershteyn, "Calculation of Multiple Sets of Weights for Weighted Random Testing," Proc. ITC, pp. 1031-1040 (1993).9Bhattacharya et al., "Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded Cores," VLSI Design, 6 pp. (Jan. 2000).10Chakrabarty et al., "Design of Built-In Test Generator Circuits Using Width Compression," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, No. 10, pp. 1044-1051 (Oct. 1998).11Chakrabarty et al., "Optimal space compaction of test responses," Proc. ITC, pp. 834-843 (1995).12Chakrabarty et al., "Optimal Zero-Aliasing Space Compaction of Test Responses," IEEE Trans. on Computers, vol. 47, No. 11, pp. 1171-1187 (Nov. 1998).13Chakrabarty et al., "Test response compaction using multiplexed parity trees," IEEE Transactions CAD of Integrated Circuits and Systems, vol. CAD-15, No. 11, pp. 1399-1408 (1996).14Chakrabarty et al., "Test Width Compression for Built-In Self Testing," Proc. ITC, pp. 328-337 (Nov. 1997).15Chakrabarty, "Zero-Aliasing Space Compaction Using Linear Compactors With Bounded Overhead," IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 17, No. 5, pp. 452-457 (May 1998).16European Communication dated Apr. 26, 2005, from European Application No. 04 01 7880.17European Communication dated Dec. 22, 2003, from European Application No. 00 97 8684.18European Communication under Rule 51(4) EPC dated Aug. 17, 2004, from European Application No. 00 97 8684.19European Communication under Rule 51(4) EPC dated Feb. 27, 2006, from European Application No. 04 01 7880.20European Decision to Grant dated Aug. 24, 2006, from European Application No. 04 01 7880.21European Decision to Grant dated Dec. 30, 2004, from European Application No. 00 97 8684.22European Search Report dated Sep. 8, 2004, from European Application No. 04 01 7880.23Fagot et al., "On Calculating Efficient LFSR Seeds for Built-In Self Test," IEEE, pp. 7-14 (1999).24Frohwerk, "Signature analysis: a new digital field services method," Hewlett-Packard Journal, pp. 2-8 (May 1977).25Ghosh-Dastidar et al., "Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information," Proc. ITC, pp. 95-102 (Sep. 1999).26Golomb, Shift Register Sequences, Holden Day, San Francisco (1967).27Hamzaoglu et al., "Reducing Test Application Time for Full Scan Embedded Cores," IEEE Proc. FTCS, pp. 260-267 (1999).28Hayes, "Check sum test methods," Proc. FTCS, pp. 114-120 (1976).29Hayes, "Transition count testing of combinational logic circuits," IEEE Transactions on Computers, vol. C-25, No. 6, pp. 613-620 (1976).30Hellebrand et al., "Built-in Test for Circuits With Scan Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers," IEEE Trans. on Computers, vol. C-44, pp. 223-233 (Feb. 1995).31Hellebrand et al., "Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE International Test Conference, pp. 120-129 (1992).32Hellebrand et al., "Pattern Generation for a Deterministic BIST Scheme," Proc. I-ICAD, pp. 88-94 (1995).33Hetherington et al., "Logic BIST for Large Industrial Designs: Real Issues and Case Studies," Proc. ITC, pp. 358-367 (1999).34International Preliminary Examination Report from International Application No. PCT/US00/31377.35International Search Report from International Application No. PCT/US00/31377.36Ireland et al., "Matrix method to determine shift-register connections for delayed pseudorandom binary sequences," Electronics Letters, vol. 4 No. 15, pp. 309-310 (1968).37Ishida et al., "COMPACT: A hybrid method for compressing test data," Proc. VLSI Test Symposium, pp. 62-69 (1998).38Ivanov et al., "Programmable BIST space compactors," IEEE Transactions on Computers, vol. C-45, No. 12, pp. 1393-1404 (1996).39Iyengar et al., "Built-In Self-testing of sequential circuits using precomputed test sets," Proc. VLSI Test Symposium, pp. 418-423 (1998).40Japanese Office Action dated May 26, 2005, including an English-language translation, from Japanese Patent Application No. 2001-540467.41Japanese Office Action dated Sep. 20, 2006, including an English-language translation, from Japanese Patent Application No. 2001-540467.42Jas et al., "Scan vector compression/decompression using statistical coding," Proc. VLSI Test Symposium, pp. 114-120 (1999).43Jas et al., "Test vector decompression via cyclical scan chains and its application to testing core-based designs," Proc. ITC, pp. 458-464 (1998).44Jone et al., "Space compression method for built-in self testing of VLSI circuits," Int. Journal of Computer Aided VLSI Design, vol. 3, pp. 309-322 (1991).45Kapur et al., "Design of an efficient weighted random pattern generation system," Proc. ITC., pp. 491-500 (1994).46Karpovsky et al., "Board-Level Diagnosis by Signature Analysis," Proc. ITC, pp. 47-53 (1988).47Karpovsky et al., "Design of Self-Diagnostic Boards by Multiple Signature Analysis," IEEE Trans. on Computers, vol. 42, No. 9, pp. 1035-1044 (Sep. 1993).48Kiln et al., "On using signature registers as pseudorandom pattern generators in built-in self-testing," IEEE Trans. CAD of IC, vol. CAD-7, No. 8, 1988, pp. 919-928.49Koenemann, c/o IBM Corp. , B56/901, "LFSR-Coded Test Patterns for Scan Designs," Proc. European Test Conference, pp. 237-242 (1991).50Konemann et al., "Built-In Logic Block Observation Techniques," IEEE Test Conference, 6 pp. (1979).51Kundu, "On Diagnosis of Faults in a Scan-Chain," Proc. VLSI Test Symp., pp. 303-308 (1993).52Langdon, Jr., "An Introduction to Arithmetic Coding," IBM J. Res. Develop., vol. 28, No. 2, pp. 135-149 (Mar. 1984).53Latawiec, "New method of generation of shifted linear pseudorandom binary sequences," Proc. IEE, vol. 121, No. 8, pp. 905-906 (1974).54Lew Yan Voon et al., "BIST Linear Generator based on Complemented Outputs," IEEE VLSI Test Symp., pp. 137-142 (1992).55Li et al., "Space compression methods with output data modification," IEEE Trans. CAD if Integrated Circuits and Systems, vol. CAD-6, No. 2, pp. 290-294 (1987).56Mano, "Decoders and Multiplexers," in Computer System Architecture, Chapter 2, pp. 50-54 (1982).57Mrugalski et al., "Synthesis of pattern generators based on cellular automata with phase shifters," Proc. ITC, pp. 368-377 (1999).58Muradali et al., "A new procedure for weighted random built-in self-test," Proc. ITC., pp. 600-669 (1990).59Narayanan et al., "An Efficient Scheme to Diagnose Scan Chains," Proc. ITC, pp. 704-713 (1997).60Pateras et al., "Cube-contained random patterns and their application to the complete testing of synthesized multi-level circuits," Proc. ITC., pp. 473-482 (1991).61Pouya et al., "Synthesis of zero-aliasing elementary-tree space compactors," Proc. VLSI Test Symp., pp. 70-77 (1998).62Rajski et al., "Accumulator-based compaction of test responses," IEEE Trans. on Computers, vol. C-42, No. 6, pp. 643-650 (1993).63Rajski et al., "Automated Synthesis of Large Phase Shifters for Built-In Self-Test," Proc. ITC, Paper 41.1, pp. 1047-1056, (1998).64Rajski et al., "Decompression of Test Data Using Variable-Length Seed LFSRs," Proc. VLSI Test Symp., pp. 426-433, (1995).65Rajski et al., "Design of Phase Shifters for BIST Applications," Proc. VLSI Test Symp., pp. 218-224 (1998).66Rajski et al., "Diagnosis of Scan Cells in BIST Environment," IEEE Trans. on Computers, vol. 48, No. 7, pp. 724-731 (Jul. 1999).67Rajski et al., "Test Data Decompression for Multiple Scan Designs with Boundary Scan," IEEE Trans. on Computers, vol. 47, No. 11, pp. 1188-1200 (Nov. 1998).68Rajski et al., "Test responses compaction in accumulators with rotate carry adders," IEEE Trans. CAD of Integrated Circuits and Systems, vol. CAD-12, No. 4, pp. 531-539 (1993).69Rajski et al., Chapter 3, "Test Response Compaction," and Chapter 4, "Fault Diagnosis," in Arithmetic Built-In Self-Test for Embedded Systems, pp. 87-133 (1998).70Reddy et al., "A Data compression technique for built-in self-test," IEEE Trans. on Computers, vol. C-37, pp. 1151-1156 (1988).71Saluja et al., "Testing Computer Hardware through Data Compression in Space and Time," Proc. ITC, pp. 83-88 (1983).72Savir, "Syndrome-testable design of combinational circuits," IEEE Trans. on Computers, vol. C-29, No. 6, pp. 442-451 (1980).73Saxena et al., "Accumulator compression testing," IEEE Trans. on Computers, vol. C-35, No. 4, pp. 317-321 (1986).74Saxena et al., "Analysis of checksums, extended-precision checksums, and cyclic redundancy," IEEE Trans. on Computers, vol. C-39, No. 7, pp. 969-975, 1990.75Saxena et al., "Extended precision checksums," Proc. FTCS, pp. 142-147 (1987).76Serra et al., "The analysis of one-dimensional linear cellular automata and their aliasing properties," IEEE Trans. CAD of Integrated Circuits and Systems, vol. CAD-9, No. 7, pp. 767-778 (1990).77Smith, "Measures of the effectiveness of fault signature analysis," IEEE Trans. on Computers, vol. C-29, No. 6, pp. 510-514 (1980).78Supplementary European Search Report dated Jul. 24, 2003, from European Application No. 00 97 8684.79Touba et al., "Altering a pseudo-random bit sequence for scan-based BIST," Proc. ITC, pp. 167-175 (1996).80Touba et al., "Transformed pseudo-random patterns for BIST," Proc. VLSI Test Symp., pp. 410-416 (1995).81Tsai et al., "STARBIST: Scan autocorrelated random pattern generation," Proc. DAC, pp. 472-477 (1997).82Venkataraman et al., "An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers," IEEE, pp. 572-577 (1993).83Waicukauski et al., "A method for generating weighted random test patterns," IBM J. Res. Develop., vol. 33, No. 2, pp. 149-161 (Mar. 1989).84Wang, "BIST Using Pseudorandom Test Vectors and Signature Analysis," IEEE Custom Integrated Circuits Conference, pp. 1611-1618 (1998).85Williams et al., "Bounds and analysis of aliasing errors in linear-feedback shift registers," IEEE Trans. CAD of Integrated Circuits and Systems, vol. CAD-7, No. 1, pp. 75-83 (1988).86Wu et al., "Scan-Based BIST Fault Diagnosis," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 18, No. 2, pp. 203-211 (Feb. 1999).87Wunderlich et al., "Bit-flipping BIST," Proc. ICCAD, pp. 337-343 (1996).88Wunderlich, "Multiple distribution for biased random test patterns," Proc. ITC, pp. 236-244 (1988).89Wunderlich, "On computing optimized input probabilities for random tests," Proc. DAC, pp. 392-398 (1987).90Yamaguchi et al., "An efficient method for compressing test data," Proc. ITC, pp. 191-199 (1997).91Yarmolik et al., "Generation and Application of Pseudorandom Sequences for Random Testing," J. Wiley & Sons, New York (1988).92Zacharia et al., "Decompression of Test Data Using Variable Length Seed LFSRs," IEEE, pp. 426-433 (1995).93Zacharia et al., "Two-Dimensional Test Data Decompressor for Multiple Scan Designs," Proc. ITC, pp. 186-194 (1996).Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8024387Sep 20, 2011Mentor Graphics CorporationMethod for synthesizing linear finite state machinesUS8108743Sep 27, 2010Jan 31, 2012Mentor Graphics CorporationMethod and apparatus for selectively compacting test responsesUS8468404 *Jun 18, 2013Cadence Design Systems, Inc.Method and system for reducing switching activity during scan-load operationsUS8533547Jan 25, 2011Sep 10, 2013Mentor Graphics CorporationContinuous application and decompression of test patterns and selective compaction of test responsesUS8966331 *Dec 10, 2012Feb 24, 2015SK Hynix Inc.Test circuit of semiconductor memory apparatus and semiconductor memory system including the sameUS9103881 *Sep 11, 2013Aug 11, 2015Texas Instruments IncorporatedOperating scan path generators and compactors sequentially and capturing simultaneouslyUS9134370Sep 9, 2013Sep 15, 2015Mentor Graphics CorporationContinuous application and decompression of test patterns and selective compaction of test responsesUS20070294327 *Aug 20, 2007Dec 20, 2007Janusz RajskiMethod for synthesizing linear finite state machinesUS20110138242 *Sep 27, 2010Jun 9, 2011Janusz RajskiMethod and apparatus for selectively compacting test responsesUS20110214026 *Sep 1, 2011Mentor Graphics CorporationContinuous application and decompression of test patterns and selective compaction of test responsesUS20140006863 *Dec 10, 2012Jan 2, 2014SK Hynix Inc.Test circuit of semiconductor memory apparatus and semiconductor memory system including the sameUS20140013176 *Sep 11, 2013Jan 9, 2014Texas Instruments IncorporatedAdapting scan-bist architectures for low power operation* Cited by examinerClassifications U.S. Classification714/726, 714/738International ClassificationG01R31/28, G01R31/3183, G06F11/22, G01R31/3185Cooperative ClassificationG01R31/318371, G01R31/318335, G01R31/318547European ClassificationG01R31/3183E, G01R31/3183M, G01R31/3185S3DLegal EventsDateCodeEventDescriptionJul 10, 2009ASAssignmentOwner name: MENTOR GRAPHICS CORPORATION, OREGONFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RAJSKI, JANUSZ;KASSAB, MARK;MUKHERJEE, NILANJAN;AND OTHERS;REEL/FRAME:022942/0366;SIGNING DATES FROM 20000720 TO 20000928Owner name: MENTOR GRAPHICS CORPORATION, OREGONFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RAJSKI, JANUSZ;KASSAB, MARK;MUKHERJEE, NILANJAN;AND OTHERS;SIGNING DATES FROM 20000720 TO 20000928;REEL/FRAME:022942/0366Aug 25, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services