Source: http://www.google.de/patents/US7509546
Timestamp: 2015-02-01 16:40:06
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Matched Legal Cases: ['Application No. 04', 'Application No. 00', 'Application No. 00', 'Application No. 04', 'Application No. 04', 'Application No. 00', 'Application No. 04', 'Application No. 2001', 'Application No. 2001', 'Application No. 00']

Patent US7509546 - Test pattern compression for an integrated circuit test environment - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr »Anmelden Erweiterte Patentsuche PatenteA method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied...http://www.google.de/patents/US7509546?utm_source=gb-gplus-sharePatent US7509546 - Test pattern compression for an integrated circuit test environment Erweiterte Patentsuche Ver�ffentlichungsnummerUS7509546 B2PublikationstypErteilung AnmeldenummerUS 11/523,111 Ver�ffentlichungsdatum24. M�rz 2009Eingetragen18. Sept. 2006 Priorit�tsdatum23. Nov. 1999Geb�hrenstatusBezahltAuch ver�ffentlicht unterDE60018101D1, DE60018101T2, DE60030896D1, DE60030896T2, EP1236111A1, EP1236111A4, EP1236111B1, US6327687, US6543020, US7111209, US7900104, US20020053057, US20030131298, US20070016836, US20090259900, WO2001038981A1 Ver�ffentlichungsnummer11523111, 523111, US 7509546 B2, US 7509546B2, US-B2-7509546, US7509546 B2, US7509546B2 ErfinderJanusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jerzy TyszerUrspr�nglich Bevollm�chtigterJanusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jerzy TyszerZitat exportierenBiBTeX, EndNote, RefManPatentzitate (101), Nichtpatentzitate (90), Referenziert von (7), Klassifizierungen (11), Juristische Ereignisse (2) Externe Links: USPTO, USPTO-Zuordnung, EspacenetTest pattern compression for an integrated circuit test environmentUS 7509546 B2 Zusammenfassung A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.
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Sept. 2011Mentor Graphics CorporationTest scheduling and test access in test compression environment* Vom Pr�fer zitiertKlassifizierungen US-Klassifikation714/718Internationale KlassifikationG06F11/22, G01R31/3185, G01R31/3183, G06F11/00 UnternehmensklassifikationG01R31/318335, G01R31/318371, G01R31/318547 Europ�ische KlassifikationG01R31/3183M, G01R31/3185S3D, G01R31/3183EJuristische Ereignisse DatumCodeEreignisBeschreibung28. Aug. 2012FPAYFee paymentYear of fee payment: 425. Okt. 2006ASAssignmentOwner name: MENTOR GRAPHICS CORPORATION, OREGONFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RAJSKI, JANUSZ;TYSZER, JERZY;KASSAB, MARK;AND OTHERS;REEL/FRAME:018449/0443;SIGNING DATES FROM 20000720 TO 20000928DrehenOriginalbildGoogle-Startseite - Sitemap - USPTO-Bulk-Downloads - Datenschutzerkl�rung - Nutzungsbedingungen - �ber Google Patente - Feedback gebenDaten bereitgestellt von IFI CLAIMS Patent Services.