Source: http://www.google.com/patents/US20020190974?dq=5,381,459
Timestamp: 2018-01-21 01:13:25
Document Index: 519008270

Matched Legal Cases: ['ART0', 'ART11', 'ART0', 'ART11', 'ART0', 'ART10', 'ART1', 'ART2', 'ART9', 'ART2', 'ART11', 'ART0', 'ART11', 'ART0']

Patent US20020190974 - Signal drive circuit, display device, electro-optical device, and signal ... - Google Patents
A signal drive circuit capable of flexibly dealing with the change of the panel size and reducing power consumption, a display device and an electro-optical device using that signal drive circuit, and a signal drive method. A signal driver (signal drive circuit) includes: a shift register which sequentially...http://www.google.com/patents/US20020190974?utm_source=gb-gplus-sharePatent US20020190974 - Signal drive circuit, display device, electro-optical device, and signal drive method
Publication number US20020190974 A1
Application number US 10/154,436
Also published as CN1197050C, CN1388512A, US7030850, US7030869, US20050156850
Publication number 10154436, 154436, US 2002/0190974 A1, US 2002/190974 A1, US 20020190974 A1, US 20020190974A1, US 2002190974 A1, US 2002190974A1, US-A1-20020190974, US-A1-2002190974, US2002/0190974A1, US2002/190974A1, US20020190974 A1, US20020190974A1, US2002190974 A1, US2002190974A1
Original Assignee Akira Morita
Patent Citations (10), Referenced by (60), Classifications (26), Legal Events (4)
US 20020190974 A1
[0014]FIG. 1 is a block diagram schematically showing a display device to which is applied a signal drive circuit (signal driver) according to one embodiment of the present invention.
[0015]FIG. 2 is a block diagram schematically showing a signal driver shown in FIG. 1.
[0016]FIG. 3 is a block diagram schematically showing a scanning driver shown in FIG. 1.
[0017]FIG. 4 is a block diagram schematically showing an LCD controller shown in FIG. 1.
[0018]FIG. 5A shows waveforms of a drive voltage for the signal lines and a common electrode voltage Vcom according to a frame inversion drive method, and FIG. 5B schematically shows the polarity of a voltage to be applied to the liquid crystal capacitance corresponding to each pixel in each frame in the case of performing the frame inversion drive method.
[0019]FIG. 6A shows waveforms of a drive voltage for the signal lines and a common electrode voltage Vcom according to a line inversion drive method, and FIG. 6B schematically shows the polarity of a voltage to be applied to the liquid crystal capacitance corresponding to each pixel in each frame in the case of performing the line inversion drive method.
[0020]FIG. 7 shows drive waveforms of the LCD panel of the liquid crystal device.
[0021]FIGS. 8A and 8B schematically show the connection between the LCD panel and the signal driver.
[0022]FIG. 9 is illustrative of a problem when one frame of an image is displayed on the LCD panel.
[0023]FIGS. 10A and 10B show examples of bypass operation of image data according to one embodiment of the present invention.
[0024]FIGS. 11A, 11B and 11C show an example of a partial display implemented by the signal driver according to one embodiment of the present invention.
[0025]FIGS. 12A, 12B and 12C show another example of a partial display implemented by the signal driver of the present embodiment.
[0026]FIGS. 13A, 13B, and 13C are illustrative of the control by the signal line drive circuit according to one embodiment of the present invention.
[0027]FIGS. 14A and 14B schematically show the signal driver disposed at different positions with respect to the LCD panel.
[0028]FIGS. 15A, 15B, and 15C schematically show the relationship between image data in the line latch and the blocks.
[0029]FIG. 16 is a diagram schematically showing the block controlled by the signal driver of the present embodiment.
[0030]FIG. 17 is illustrative of a block output select register of the signal driver according to one embodiment of the present invention.
[0031]FIG. 18 is illustrative of a partial display select register of the signal driver of one embodiment of the present invention.
[0032]FIG. 19 shows an example of a block data rearrangement circuit according to one embodiment of the present invention.
[0033]FIGS. 20A and 20B schematically show an example of operation of the data bypass circuit according to one embodiment of the present invention.
[0034]FIGS. 21A and 21B schematically show another example of operation of the data bypass circuit according to one embodiment of the present invention.
[0035]FIG. 22 is a diagram showing the configuration of an SR which makes up a shift register according to one embodiment of the present invention.
[0036]FIG. 23 is illustrative of gray scale voltages generated by the DAC according to one embodiment of the present invention.
[0037]FIG. 24 is a circuit diagram showing the configuration of a voltage-follower-connected operational amplifier OP according to one embodiment of the present invention.
[0038]FIG. 25 is a circuit diagram showing the configuration of a reference voltage select signal generation circuit of the present embodiment.
[0039]FIG. 26 is a circuit diagram showing the configuration of a non-display-level voltage supply circuit according to one embodiment of the present invention.
[0040]FIG. 27 is illustrative of the contents controlled by the signal driver according to one embodiment of the present invention.
[0041]FIG. 28 is a timing chart showing waveforms of the signal driver according to one embodiment of the present invention.
[0110]FIG. 1 shows a display device to which a signal drive circuit (signal driver) of one embodiment of the present invention is applied.
[0123]FIG. 2 shows an outline of a configuration of the signal driver shown in FIG. 1.
The image data (DIO) is input to the line latch 34 from the LCD controller 60 in a unit of 18 bits (6 bits (gradation data)×3 (RGB)), for example. The line latch 34 latches the image data (DIO) in synchronization with the enable input/output signal EIO sequentially shifted by the flip-flops of the shift register 32.
[0133]FIG. 3 shows an outline of a configuration of the scanning driver shown in FIG. 1.
[0140]FIG. 4 shows an outline of a configuration of the LCD controller shown in FIG. 1.
[0153]FIGS. 5A and 5B are views for describing the operation of the frame inversion drive method. FIG. 5A schematically shows waveforms of the drive voltage of the signal line and the common electrode voltage Vcom using the frame inversion drive method. FIG. 5B schematically shows the polarity of the voltage applied to the liquid crystal capacitances corresponding to each pixel in each frame in the case of using the frame inversion drive method.
[0156]FIGS. 6A and 6B are views for describing the operation of the line inversion drive method.
[0157]FIG. 6A schematically shows the waveforms of the drive voltage of the signal lines and the common electrode voltage Vcom using the line inversion drive method. FIG. 6B schematically shows the polarity of the voltage applied to the liquid crystal capacitances corresponding to each pixel in each line in the case of performing the line inversion drive method.
[0163]FIG. 7 shows an example of the drive waveform of the LCD panel 20 of the liquid crystal device 10 having the above configuration. This example shows a case of driving the liquid crystal using the line inversion drive method.
[0169]FIGS. 8A and 8B schematically show the connection relation between the size of the LCD panel 20 and the signal driver 30 of the present embodiment.
[0176]FIG. 9 is a view for describing the problem occurring when displaying one image frame on the LCD panel 20.
[0182]FIGS. 10A and 10B show an example of the bypass operation of the image data.
[0189]FIGS. 11A, 11B, and 11C are views schematically showing an example of the partial display realized by the signal driver of this embodiment.
[0192]FIGS. 12A, 12B, and 12C schematically show another example of the partial display realized by the signal driver.
[0197]FIGS. 13A, 13B, and 13C are views schematically showing the control content of the signal line drive circuit of this embodiment.
[0204]FIGS. 14A and 14B are views schematically showing the signal driver 30 mounted at a different position with respect to the LCD panel 20.
[0207]FIGS. 15A, 15B, and 15C are views schematically showing the corresponding relation between the image data held by the line latch and the blocks.
[0216]FIG. 16 shows an outline of the configuration of the block unit controlled by the signal driver 30.
[0230]FIG. 19 shows an example of the configuration of the block data rearrangement circuit.
This example shows a case where the partial display data is rearranged. The block data rearrangement circuit rearranges the order of the partial display data PART0 to PART11 set in the partial display data select register in response to the shift direction switch signal SHL. More specifically, the block data rearrangement circuit selectively outputs either the partial display data PART0 or PART11 as PART0′ in response to the shift direction switch signal SHL. The block data rearrangement circuit selectively outputs either the partial display data PARTl or PART10 as PART1′, either the partial display data PART2 or PART9 as PART2′, . . . , and either the partial display data PART11 or PART0 as PART11′ in response to the shift direction switch signal SHL.
[0242]FIGS. 20A and 20B are views schematically showing an example of the operation of such a data bypass circuit.
[0247]FIGS. 21A and 21B are views schematically showing another example of the operation of the data bypass circuit.
[0255]FIG. 22 schematically shows a configuration of the SR0-1 which makes up the shift register 140 0.
[0265]FIG. 23 is a view for describing the gray scale voltage generated by the DAC0-1.
In this embodiment, the DAC enable signal DACen is generated by the logical product of an enable signal dacen0 and the block output select data BLK (BLK0′) in the block output select register which indicates whether or not to put the signal lines in the block B0 in a high impedance state. The enable signal dacenO is generated by the logical product of a DAC control signal dacen generated by a control circuit (not shown) of the signal driver 30 and the partial display data PART (PART0′) which indicates whether or not to allow the partial display in the block B0 in the partial display select register.
[0277]FIG. 24 shows an example of the configuration of the voltage-follower-connected operational amplifier OP0-1.
[0293]FIG. 25 shows an outline of the configuration of a reference voltage select signal generation circuit which supplies the reference voltage select signal to the first and second differential amplifier circuits 162 0-1 and 164 0-1.
[0308]FIG. 26 shows an example of a configuration of the non-display-level voltage supply circuit VG0-1.
[0314]FIG. 27 shows the control contents of each section of the signal driver 30.
[0320]FIG. 28 shows an example of the operation of the signal driver 30.
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U.S. Classification 345/208, 345/690
Cooperative Classification G09G2340/0478, G09G2340/0471, G09G2310/0232, G09G2330/021, G09G2310/027, G09G3/3677, G09G3/3614, G09G2310/0291, G09G3/3696, G09G2320/0209, G09G3/3666, G09G2310/0283, G09G2310/04, G09G2340/0414, G09G2310/0297, G09G3/3688, G09G2340/0421, G09G2310/0289
European Classification G09G3/36C14A, G09G3/36C2, G09G3/36C8S