Source: http://www.google.com/patents/US5879969?dq=7125605
Timestamp: 2017-07-26 19:32:43
Document Index: 418118572

Matched Legal Cases: ['Application No. 3', 'Application No. 4', 'Application No. 4', 'Application No. 4', 'Application No. 4', 'Application No. 3']

Patent US5879969 - Semiconductor device and method for forming the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsIn a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate electrode and the gate insulating film to prevent invasion of movable...http://www.google.com/patents/US5879969?utm_source=gb-gplus-sharePatent US5879969 - Semiconductor device and method for forming the sameAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS5879969 APublication typeGrantApplication numberUS 08/841,638Publication dateMar 9, 1999Filing dateApr 30, 1997Priority dateMar 6, 1991Fee statusLapsedAlso published asUS5468987Publication number08841638, 841638, US 5879969 A, US 5879969A, US-A-5879969, US5879969 A, US5879969AInventorsShunpei Yamazaki, Hongyong Zhang, Yasuhiko TakemuraOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (29), Referenced by (90), Classifications (37), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and method for forming the same
As is apparent from FIG. 12, the planar type of TFT is so designed as to be very flat over its whole body. This structure is very favorable for a case where it is used as an active element for a liquid crystal display device. This is because in the liquid crystal display device, the thickness of a liquid crystal layer is about 5 to 6 μm, and it is required to control the thickness with accuracy of ±0.1 μm as a whole. Therefore, an element structure having high unevenness (a large number of recesses and projections) causes ununiformity of electric field, so that not only the characteristic of the element is deteriorated, but also the element itself suffers a mechanical damage.
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 101. This glass has high strain temperature, but contains a large amount of lithium and sodium. Therefore, in order to prevent invasion of these movable ions from the substrate, a silicon nitride film 102 was formed in thickness of 10 to 50 nm on the substrate by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film serving as a sealer was formed in thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600° C. for 12 to 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process by the photolithography and the reactive ion etching (RIE) method, thereby forming islandish semiconductor regions 104 (for N-channel TFT) and 105 (for P-channel TFT) as shown in FIG. 1(A).
Through these processes, the structure as shown in FIG. 1(C) was obtained. Naturally, the portion doped with the impurity by the ion injection method had low crystallinity, and thus it was substantially in a non-crystal state (amorphous state, or a polycrystal state close to the amorphous state). Therefore, a laser anneal treatment was conducted to restore crystallinity at the portion. This process may be carried out by a heat annealing treatment at 600° to 850° C. The same laser annealing condition as disclosed in Japanese Patent Application No. 3-237100 for example was adopted.
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 1. This glass has high strain temperature, but contains a large amount of lithium and sodium. Therefore, in order to prevent invasion of these movable ions from the substrate, a silicon nitride film 2 was formed in thickness of 10 to 50 nm on the substrate by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film serving as a sealer was formed in thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600° C. for 12 to 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process by the photolithography and the reactive ion etching (RIE) method, thereby forming islandish semiconductor regions 4 (for N-channel TFT) and 105 (for P-channel TFT) as shown in FIG. 4(A).
Through these processes, the structure as shown in FIG. 4(D) was obtained. Naturally, the portion doped with the impurity by the ion injection method had low crystallinity, and thus it was substantially in a non-crystal state (amorphous state, or a polycrystal state close to the amorphous state). Therefore, a laser anneal treatment was conducted to restore crystallinity at the portion. This process may be carried out by a heat annealing treatment at 600° to 850° C. The same laser annealing condition as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250° to 450° C. under hydrogen atmosphere (1 to 700 torr, preferably 500 to 700 torr), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.).
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 401. A silicon nitride film 402 was formed in thickness of 10 to 50 nm on the substrate by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film 403 serving as a sealer was formed in thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600° C. for 12 to 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process to form islandish semiconductor regions 404 (for N-channel TFT) and 405 (for P-channel TFT) as shown in FIG. 5(A).
Through these processes, the structure as shown in FIG. 5(D) was obtained. In the laser doping technique, unlike the Embodiment 4, no laser annealing process or no heat annealing process is required because the injection of the impurities and the annealing treatment are simultaneously carried out. After the laser doping treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250° to 450° C. under hydrogen atmosphere (1 to 700 torr or 500 to 700 torr), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.).
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 501. A silicon nitride film 502 was formed in thickness of 10 to 50 nm on the substrate by the plasma CVD method or the low pressure CVD method. Further, a silicon oxide film 503 serving as a sealer was formed in thickness of 100 to 800 nm by the sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600° C. for 12 to 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process to form islandish semiconductor regions 504 (for N-channel TFT) and 505 (for P-channel TFT) as shown in FIG. 6(A).
Through these processes, the structure as shown in FIG. 6(D) was obtained. Naturally, the crystallinity of the portions to which the impurities were injected by the ion injection was extremely low, and these portions were substantially in a non-crystal state (amorphous state or polycrystal state close to the amorphous state). Therefore, the crystallinity was restored by the laser annealing treatment. This process may be replaced by the heat annealing treatment at 600° to 850° C. The condition for the laser annealing treatment as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. Here, no short-wavelength ultraviolet rays below 250 nm wavelength is passed through the silicon nitride film 507, so that XeCl laser (308 nm wavelength) or XeF laser (351 nm wavelength) was used.
After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250° to 450° C. under hydrogen atmosphere (1 to 700 torr or 500 to 700 torr), to thereby depress lattice defects (dangling bond, etc.). Actually, delivery of hydrogen was little carried out between the inside of the semiconductor region and the outside thereof because the silicon nitride film 507 exists. Therefore, a large amount of hydrogen atoms are simultaneously injected into the semiconductor region in the plasma doping method, and on the other hand, in the ion injection method, a process of injecting hydrogen atoms is separately required. If the amount of hydrogen atoms is insufficient, hydrogen atoms are required to be separately doped even in the plasma doping method.
An N--O glass produced by Nippon Electric Glass Co., Ltd was used as a substrate 1001. This glass has high strain temperature, however, contains a large amount of lithium and sodium. Therefore, in order to prevent invasion of these movable ions from the substrate and in order to prevent the over-etching, an aluminum oxide film 1002 was formed on the substrate 1001 in thickness of 10 to 50 nm by an organic metal CVD method. Further, a silicon oxide film 1003 serving as a sealer was formed on the aluminum oxide film 1002 in thickness of 100 to 800 nm by the sputtering method. An amorphous silicon film was formed in thickness of 20 to 100 nm on the silicon oxide film 1003 by the plasma CVD method, and then annealed at 600° C. for 12 to 72 hours at nitrogen atmosphere to be crystallized. The result was subjected to the patterning process by the photolithography and the reactive ion etching (RIE) method to form islandish semiconductor regions 1004.
Subsequently, N-type impurity was doped into the semiconductor region 1004 by the well-known ion injection method to form N-type impurity regions (source, drain) 1005 and 1006. In the manner as described above, the structure as shown in FIG. 13(A) was obtained. Naturally, the crystallinity at the portion doped with the impurities by the ion injection method was extremely low, and this portion was substantially in a non-crystal (amorphous state, or polycrystal state close to the amorphous state). Therefore, the crystallinity at the portion was restored by the laser annealing treatment. This process may be replaced by the heat annealing treatment at 600° to 850° C. The laser annealing condition as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250° to 450° C. under hydrogen atmosphere (1 to 700 torr, preferably 500 to 700 torr) to inject hydrogen atoms into the semiconductor region and depress the lattice defect (dangling bond, etc.).
An N--O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 1101. A silicon nitride film 1102 was formed in thickness of 10 to 50 nm on the substrate by the plasma CVD method or the low pressure CVD method. Further, a silicon oxide film 1103 serving as a sealer was formed in thickness of 100 to 800 nm by the sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600° C. for 12 to 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process to form islandish semiconductor regions 1104.
Thereafter, an aluminum film was formed by the sputtering method or the electron beam deposition method, and then subjected to a patterning process to form gate electrode/wirings 1107 to 1109. Further, current was supplied to the gate electrode/wirings 1107 to 1109 in the electrolyte to form aluminum oxide films 1110 to 1112 by the anodic oxidation method. The anodic oxidation condition as disclosed in Japanese Patent Application No. 4-30220 which was invented by the inventor of this application, et.al was adopted in this embodiment. Further, by the laser doping technique (Japanese Patent Application No. 3-283981) which was invented by the inventor of this application, et.al, N-type impurity was doped into the semiconductor region 1104, thereby forming an N-type impurity region (source, drain). The laser doping method requires no laser annealing treatment and no heat annealing treatment which were required for the Embodiment 8 because the injection of the impurities and the annealing treatment were simultaneously carried out. After the laser doping treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250° to 450° C. under hydrogen atmosphere (1 to 700 torr or 500 to 700 torr), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.). This state is shown in FIG. 14(A).
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3634203 *Jul 22, 1969Jan 11, 1972Texas Instruments IncThin film metallization processes for microcircuitsUS3671819 *Jan 26, 1971Jun 20, 1972Westinghouse Electric CorpMetal-insulator structures and method for formingUS3740280 *May 14, 1971Jun 19, 1973Rca CorpMethod of making semiconductor deviceUS4015281 *Mar 5, 1971Mar 29, 1977Hitachi, Ltd.MIS-FETs isolated on common substrateUS4042945 *Jul 14, 1975Aug 16, 1977Westinghouse Electric CorporationN-channel MOS transistorUS4055885 *Sep 10, 1976Nov 1, 1977Hitachi, Ltd.Charge transfer semiconductor device with electrodes separated by oxide region therebetween and method for fabricating the sameUS4469568 *Dec 1, 1982Sep 4, 1984Sharp Kabushiki KaishaMethod for making thin-film transistorsUS4485393 *May 26, 1981Nov 27, 1984Tokyo Shibaura Denki Kabushiki KaishaSemiconductor device with selective nitride layer over channel stopUS4866498 *Apr 20, 1988Sep 12, 1989The United States Department Of EnergyIntegrated circuit with dissipative layer for photogenerated carriersUS5041888 *Jul 16, 1990Aug 20, 1991General Electric CompanyInsulator structure for amorphous silicon thin-film transistorsUS5051794 *Jul 3, 1989Sep 24, 1991Kabushiki Kaisha ToshibaNon-volatile semiconductor memory device and method for manufacturing the sameUS5146301 *Oct 14, 1988Sep 8, 1992Sharp Kabushiki KaishaTerminal electrode structure of a liquid crystal panel displayUS5177577 *Jul 5, 1991Jan 5, 1993Hitachi, Ltd.Liquid crystal display device with TFT's each including a Ta gate electrode and an anodized Al oxide filmUS5225356 *Dec 30, 1991Jul 6, 1993Nippon Telegraph & Telephone CorporationMethod of making field-effect semiconductor device on sotUS5240868 *Dec 20, 1991Aug 31, 1993Samsung Electronics Co., Ltd.Method of fabrication metal-electrode in semiconductor deviceUS5289030 *Mar 5, 1992Feb 22, 1994Semiconductor Energy Laboratory Co., Ltd.Semiconductor device with oxide layerUS5422293 *Dec 18, 1992Jun 6, 1995Casio Computer Co., Ltd.Method for manufacturing a TFT panelUS5576225 *Apr 28, 1993Nov 19, 1996Semiconductor Energy Laboratory Co., Ltd.Method of forming electric circuit using anodic oxidationJPH02159730A * Title not availableJPH02210420A * Title not availableJPH02216129A * Title not availableJPH02228042A * Title not availableJPH03165575A * Title not availableJPH03217059A * Title not availableJPH04299864A * Title not availableJPH04360580A * Title not availableJPS5823479A * Title not availableJPS58106861A * Title not availableJPS63178560A * Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6300228 *Aug 30, 1999Oct 9, 2001International Business Machines CorporationMultiple precipitation doping processUS6323528Jul 29, 1998Nov 27, 2001Semiconductor Energy Laboratory Co,. Ltd.Semiconductor deviceUS6329229 *Nov 3, 1997Dec 11, 2001Semiconductor Energy Laboratory Co., Ltd.Method for processing semiconductor device, apparatus for processing a semiconductor and apparatus for processing semiconductor deviceUS6362027 *Jul 6, 1999Mar 26, 2002Semiconductor Energy Laboratory Co., Ltd.Semiconductor device, active matrix substrate, method of manufacturing the semiconductor device and method of manufacturing the active matrix substrateUS6624450Jan 25, 1999Sep 23, 2003Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the sameUS6709906 *Dec 19, 2000Mar 23, 2004Semiconductor Energy Laboratory Co., Ltd.Method for producing semiconductor deviceUS6794229 *Apr 26, 2001Sep 21, 2004Semiconductor Energy Laboratory Co., Ltd.Manufacturing method for semiconductor deviceUS6822261Oct 18, 2001Nov 23, 2004Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the sameUS6853004Jul 27, 2001Feb 8, 2005Semiconductor Energy Laboratory Co., Ltd.Thin film transistor formed on a resin substrateUS6897100Feb 12, 1997May 24, 2005Semiconductor Energy Laboratory Co., Ltd.Method for processing semiconductor device apparatus for processing a semiconductor and apparatus for processing semiconductor deviceUS6972435Jun 22, 2004Dec 6, 2005Semiconductor Energy Laboratory Co., Ltd.Camera having display device utilizing TFTUS6979841Sep 9, 2003Dec 27, 2005Semiconductor Energy Laboratory Co., Ltd.Semiconductor integrated circuit and fabrication method thereofUS6982194Apr 19, 2002Jan 3, 2006Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the sameUS7170138Sep 8, 2004Jan 30, 2007Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS7189997Mar 26, 2002Mar 13, 2007Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the sameUS7220613Aug 30, 2004May 22, 2007Semiconductor Energy Laboratory Co., Ltd.Manufacturing method for semiconductor deviceUS7253441Feb 4, 2005Aug 7, 2007Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS7301209Dec 7, 2006Nov 27, 2007Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS7414288Oct 21, 2005Aug 19, 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having display deviceUS7446340Aug 6, 2007Nov 4, 2008Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS7569408Apr 30, 1997Aug 4, 2009Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the sameUS7615786Oct 31, 2007Nov 10, 2009Semiconductor Energy Laboratory Co., Ltd.Thin film transistor incorporating an integrated capacitor and pixel regionUS7671369Mar 28, 2003Mar 2, 2010Semiconductor Energy Laboratory Co., Ltd.Semiconductor display deviceUS7687809May 2, 2008Mar 30, 2010Semiconductor Energy Laboratory Co., LtdMethod for producing a semiconductor integrated circuit including a thin film transistor and a capacitorUS7701541Oct 17, 2006Apr 20, 2010Semiconductor Energy Laboratory Co., Ltd.In-plane switching display device having electrode and pixel electrode in contact with an upper surface of an organic resin filmUS7863619Apr 21, 2009Jan 4, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and a method for manufacturing the sameUS7915058Jan 19, 2006Mar 29, 2011Semiconductor Energy Laboratory Co., Ltd.Substrate having pattern and method for manufacturing the same, and semiconductor device and method for manufacturing the sameUS7935581Aug 9, 2007May 3, 2011Samsung Mobile Display Co., Ltd.Method of fabricating thin film transistor array substrateUS7955975Jul 21, 2010Jun 7, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor element and display device using the sameUS7964874May 19, 2008Jun 21, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having a protective circuitUS7994504Jul 31, 2009Aug 9, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor element and display device using the sameUS7999263Aug 4, 2005Aug 16, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor element and display device using the sameUS8008666Feb 24, 2010Aug 30, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor display deviceUS8030658Sep 29, 2008Oct 4, 2011Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS8049275Oct 31, 2005Nov 1, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS8053778Dec 30, 2010Nov 8, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and a method for manufacturing the sameUS8115210Jun 17, 2011Feb 14, 2012Semiconductor Energy Laboratory Co., Ltd.Semiconductor display deviceUS8120031Jul 31, 2007Feb 21, 2012Semiconductor Energy Laboratory Co., Ltd.Display device including an opening formed in a gate insulating film, a passivation film, and a barrier filmUS8120033Jul 21, 2010Feb 21, 2012Semiconductor Energy Laboratory Co., Ltd.Semiconductor element and display device using the sameUS8138101Apr 17, 2007Mar 20, 2012Semiconductor Energy Laboratory Co., Ltd.Manufacturing method for semiconductor deviceUS8212284Jan 20, 2011Jul 3, 2012Semiconductor Energy Laboratory Co., Ltd.Display device and manufacturing method of the display deviceUS8237169Sep 23, 2011Aug 7, 2012Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS8324693Nov 7, 2011Dec 4, 2012Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and a method for manufacturing the sameUS8368072Jul 31, 2008Feb 5, 2013Semiconductor Energy Labratory Co., Ltd.Display device and method of fabricating the sameUS8373173Aug 6, 2012Feb 12, 2013Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS8405149May 16, 2008Mar 26, 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having display deviceUS8415669Aug 25, 2011Apr 9, 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor display deviceUS8502215Feb 15, 2012Aug 6, 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor element and display device using the sameUS8592861Jun 29, 2012Nov 26, 2013Semiconductor Energy Laboratory Co., Ltd.Display device and manufacturing method of the display deviceUS8624400Jul 21, 2010Jan 7, 2014Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the sameUS8643021Feb 13, 2012Feb 4, 2014Semiconductor Energy Laboratory Co., Ltd.Semiconductor device including multiple insulating filmsUS8680532Oct 31, 2011Mar 25, 2014Semiconductor Energy Laboratory Co., Ltd.Method of fabricating a semiconductor deviceUS8698160Feb 11, 2013Apr 15, 2014Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS8709847Jan 31, 2013Apr 29, 2014Semiconductor Energy Laboratory Co., Ltd.Method of fabricating display deviceUS8835271Apr 5, 2013Sep 16, 2014Semiconductor Energy Laboratory Co., Ltd.Semiconductor display deviceUS8928081Mar 21, 2013Jan 6, 2015Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having display deviceUS8946717Aug 2, 2013Feb 3, 2015Semiconductor Energy Laboratory Co., Ltd.Semiconductor element and display device using the sameUS8946718Dec 19, 2013Feb 3, 2015Semiconductor Energy Laboratory Co., Ltd.Semiconductor element and display device using the sameUS8951902Jan 31, 2012Feb 10, 2015Semiconductor Energy Laboratory Co., Ltd.Methods of removing contaminant impurities during the manufacture of a thin film transistor by applying water in which ozone is dissolvedUS8957422Mar 21, 2014Feb 17, 2015Semiconductor Energy Laboratory Co., Ltd.Method of fabricating a semiconductor deviceUS9105727Dec 24, 2014Aug 11, 2015Semiconductor Energy Laboratory Co., Ltd.Semiconductor element and display device using the sameUS9366930Feb 7, 2012Jun 14, 2016Semiconductor Energy Laboratory Co., Ltd.Display device with capacitor elementsUS9406806Jul 16, 2015Aug 2, 2016Semiconductor Energy Laboratory Co., Ltd.Semiconductor element and display device using the sameUS9627460Feb 13, 2015Apr 18, 2017Semiconductor Energy Laboratory Co., Ltd.Method of fabricating a semiconductor deviceUS9666614Sep 9, 2014May 30, 2017Semiconductor Energy Laboratory Co., Ltd.Semiconductor display deviceUS20020175328 *Mar 26, 2002Nov 28, 2002Semiconductor Energy Laboratory Co. Ltd.Semiconductor device and method for manufacturing the sameUS20030164500 *Apr 19, 2002Sep 4, 2003Akira TsunodaSemiconductor device and method for manufacturing the sameUS20030189210 *Mar 28, 2003Oct 9, 2003Semiconductor Energy Laboratory Co., Ltd.Semiconductor display deviceUS20040046174 *Sep 9, 2003Mar 11, 2004Semiconductor Energy Laboratory Co., Ltd., A Japan CorporationSemiconductor integrated circuit and fabrication method thereofUS20040232423 *Jun 22, 2004Nov 25, 2004Semiconductor Energy Laboratory Co., Ltd, A Japan CorporationSemiconductor integrated circuit and fabrication method thereofUS20050026320 *Aug 30, 2004Feb 3, 2005Semiconductor Energy Laboratory Co., Ltd.Manufacturing method for semiconductor deviceUS20050037550 *Jul 9, 2002Feb 17, 2005Myung-Koo KangThin film transistor using polysilicon and a method for manufacturing the sameUS20050040476 *Sep 8, 2004Feb 24, 2005Semiconductor Energy Laboratory Co., Ltd.Semiconductor device, and a method for manufacturing the sameUS20050136578 *Feb 4, 2005Jun 23, 2005Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS20050282305 *Aug 4, 2005Dec 22, 2005Semiconductor Energy Laboratory Co., Ltd.Semiconductor element and display device using the sameUS20060043376 *Oct 21, 2005Mar 2, 2006Semiconductor Energy Laboratory Co., Ltd., A Japan CorporationSemiconductor device having display deviceUS20060051906 *Oct 31, 2005Mar 9, 2006Semiconductor Energy Laboratory Co., Ltd.Method of fabricating a semiconductor deviceUS20060170077 *Jan 19, 2006Aug 3, 2006Semiconductor Energy Laboratory Co., Ltd.Substrate having pattern and method for manufacturing the same, and semiconductor device and method for manufacturing the sameUS20070096224 *Dec 7, 2006May 3, 2007Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and a method for manufacturing the sameUS20080038884 *Aug 9, 2007Feb 14, 2008Eui-Hoon HwangMethod of fabricating thin film transistor array substrateUS20080042584 *Aug 6, 2007Feb 21, 2008Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing thin film transistorUS20080290345 *May 16, 2008Nov 27, 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having display deviceUS20090020762 *Jul 31, 2008Jan 22, 2009Semiconductor Energy Laboratory Co., Ltd.Display device and method of fabricating the sameUS20090026970 *Sep 29, 2008Jan 29, 2009Semiconductor Energy Laboratory Co., Ltd.Method of Manufacturing Thin Film TransistorUS20090200611 *Apr 21, 2009Aug 13, 2009Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and a method for manufacturing the sameUS20100283105 *Jul 21, 2010Nov 11, 2010Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the sameUS20110049522 *Feb 24, 2010Mar 3, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor display deviceUS20110101360 *Dec 30, 2010May 5, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and a method for manufacturing the sameUS20110114936 *Jan 20, 2011May 19, 2011Semiconductor Energy Laboratory Co., Ltd.Display device and manufacturing method of the display deviceCN100587943CAug 9, 2007Feb 3, 2010三星移动显示器株式会社Method of fabricating thin film transistor array substrate* Cited by examinerClassifications U.S. Classification438/151, 438/635, 257/E29.293, 438/595, 438/303, 257/E29.285, 257/E21.413, 438/768, 257/E21.507, 257/E27.111, 257/E29.151, 438/163, 257/E29.29International ClassificationH01L29/786, H01L21/60, G02F1/1362, H01L27/12, H01L29/49, H01L21/336, H01L21/77Cooperative ClassificationH01L29/66757, H01L29/4908, H01L29/78675, G02F2001/136245, G02F1/13454, H01L27/124, H01L21/76897, H01L29/78651, H01L29/78666European ClassificationH01L29/66M6T6F15A2, H01L21/768S, H01L27/12T, H01L29/786E4B2, H01L27/12, H01L29/786E, H01L29/786E4C2, H01L29/49BLegal EventsDateCodeEventDescriptionAug 15, 2002FPAYFee paymentYear of fee payment: 4Aug 18, 2006FPAYFee paymentYear of fee payment: 8Oct 11, 2010REMIMaintenance fee reminder mailedMar 9, 2011LAPSLapse for failure to pay maintenance feesApr 26, 2011FPExpired due to failure to pay maintenance feeEffective date: 20110309RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services