Source: http://www.google.fr/patents/US4646268
Timestamp: 2013-12-12 10:12:12
Document Index: 428567889

Matched Legal Cases: ['art 10', 'art 10', 'art 10', 'art 10', 'art 10', 'art 10', 'art 10', 'art 10', 'art 10', 'art 10', 'art 10']

Brevet US4646268 - Semiconductor bipolar memory device operating in high speed - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Connexion Recherche avanc�e dans les brevets BrevetsA semiconductor memory device composed of bipolar transistors is disclosed. A read/write control circuit includes a voltage producing section which produces a reading-out voltage used for reading out the data stored in the selected memory cell. The voltage producing section includes a first transistor...http://www.google.fr/patents/US4646268?utm_source=gb-gplus-shareBrevet US4646268 - Semiconductor bipolar memory device operating in high speed Num�ro de publicationUS4646268 AType de publicationOctroi Num�ro de demandeUS 06/661,206 Date de publication24 f�vr. 1987 Date de d�p�t15 oct. 1984 Date de priorit�13 oct. 1983�tat de paiement des fraisPay� Num�ro de publication06661206, 661206, US 4646268 A, US 4646268A, US-A-4646268, US4646268 A, US4646268A InventeursKazuo Kuno Cessionnaire d'origineNec CorporationExporter la citationBiBTeX, EndNote, RefManCitations de brevets (2), R�f�renc� par (19), Classifications (15), �v�nements juridiques (6) Liens externes: USPTO, Cession USPTO, EspacenetSemiconductor bipolar memory device operating in high speedUS 4646268 A R�sum� A semiconductor memory device composed of bipolar transistors is disclosed. A read/write control circuit includes a voltage producing section which produces a reading-out voltage used for reading out the data stored in the selected memory cell. The voltage producing section includes a first transistor of an emitter follower type as its output stage, and the data-read operation is thus attained in a high speed. The voltage producing section further includes a diode whose ON voltage is substantially equal to that of a clamping diode provided in a memory cell and a second transistor having an emitter resistor and a collector resistor and supplying the collector resistor with a current determined by the ON voltage of the diode and the emitter resistor. The potential at the collector of the second transistor is applied to the first transistor.
What is claimed is: 1. A memory device comprising a plurality of memory cells, each of said memory cells including first and second transistors for holding data stored therein and first and second diodes for suppressing a lowering of potentials of said transistors, a third transistor having an emitter connected to an emitter of said first transistor, a fourth transistor having an emitter connected to an emitter of said second transistor, a first current source connected to a connection point of the emitters of said first and third transistor, a second current source connected to a connection point of the emitters of said second and fourth transistors, means for generating a first voltage having a level variation characteristic substantially equal to that of each voltage of said first and second diodes, means for providing a current based on the first voltage generated from said generating means, means for converting said current into a second voltage, and means responsive to said second voltage for supplying a third voltage to bases of said third and fourth transistors with a low output impedance, said third voltage taking an intermediate level between potentials appearing at bases of said first and second transistors, whereby one of said third and fourth transistors is made conductive in response to the data stored in a selected memory cell.
DETAILED DESCRIPTION OF THE PRIOR ART Referring to FIG. 1, there is shown a voltage production part 10 in a read/write control circuit according to the prior art in order to facilitate the understanding of features and advantages of the present invention. There is further shown in FIG. 1 one memory cell MC.sub.1. The memory cell MC.sub.1 includes two transistors QC.sub.1 and QC.sub.2 of an NPN type. The base and collector of the transistor QC.sub.1 are connected to the collector and base of the transistor QC.sub.2 to form a flip-flop circuit. The transistors QC.sub.1 and QC.sub.2 are of a multi-emitter type having first and second emitters. The first emitters of the transistors QC.sub.1 and QC.sub.2 are connected in common to a constant current source 1 producing a data-holding current IH. A clamping diode DC.sub.1 and a load resistor RC.sub.1 are connected in parallel between the collector of the transistor QC.sub.1 and a word line WL.sub.1, and the collector of the transistor QC.sub.2 is coupled to the word line WL.sub.1 through a parallel circuit of a clamping diode DC.sub.2 and a load resistor RC.sub.2. Each of the clamping diodes DC.sub.1 and DC.sub.2 is formed by a Schottky diode for the purpose of a high speed operation. The word line WL.sub.1 is connected to a first power supply terminal 15 through an NPN transistor QW.sub.1 supplied at its base with a word line selection signal W.sub.1. The terminal 15 is applied with a power voltage of V.sub.CC.
The second emitter of the transistor QC.sub.1 is connected along with the emitter of an NPN transistor Q.sub.1 to a constant current source 2-1 producing a reading-out current IS, and the second emitter of the transistor QC.sub.2 and emitter of an NPN transistor Q.sub.2 are connected in common to a constant current source 2-2 which also produces a read-out current IS. The outputs at the collectors of the transistors Q.sub.1 and Q.sub.2 are supplied to a sense amplifier (not shown), and the data stored in the memory cell MC.sub.1 is thereby read-out.
When the signal W.sub.1 takes a selective level (being substantially equal to the V.sub.CC level), the memory cell MC.sub.1 is selected, and the word line WL.sub.1 thus takes a level of (V.sub.CC -V.sub.BE1), V.sub.BE1 representing the base-emitter forward voltage of the transistor QW.sub.1. If the data "1" has been stored in the memory cell MC.sub.1, the transistors QC.sub.1 and QC.sub.2 are in a conductive state and in a nonconductive state, respectively. Accordingly, the increase current by the level-up on the word line WL.sub.1 flows into the current source 2-1 through the transistor QC.sub.1. The voltage drop across the resistor RC.sub.1 is thus made large to turn the diode DC.sub.1 on. As a result, the potential at the collector of the transistor QC.sub.1 (i.e., the base potential of the transistor QC.sub.2) is clamped to the level of (V.sub.CC -V.sub.BE1 -V.sub.F1), V.sub.F1 being the forward voltage (or ON voltage) of the diode DC.sub.1. On the other hand, the base current of the transistor QC.sub.1 flows through the resistor RC.sub.2, but the voltage drop across the resistor RC.sub.2 is negligible. Therefore, the potential at base of the transistor QC.sub.1 (or collector potential of the transistor QC.sub.2) is substantially equal to the level of the word line WL.sub.1, i.e., (V.sub.CC -V.sub.BE1).
The transistor Q.sub.1 and Q.sub.2 are supplied at their bases with a reading-out voltage V.sub.R from the voltage production part 10. If the voltage V.sub.R takes the intermediate level between the base potentials of the transistors QC.sub.1 and QC.sub.2, either one of the transistors Q.sub.1 and Q.sub.2 is made conductive to broaden the difference in voltage between the collectors of the transistors QC.sub.1 and QC.sub.2. The read-out operation for the stored data thus becomes possible. Accordingly, the voltage production part 10 should produce the intermediate level between the base potentials of the transistors QC.sub.1 and QC.sub.2, i.e., the following read-out voltage V.sub.R : ##EQU1##
In order to produce the voltage V.sub.R having this level, the voltage production part 10 includes an NPN transistor QR.sub.0, three resistors RR, RR.sub.1 and RR.sub.2, a diode DR, two constant current sources 2-3 and 2-4, and a switch SW. The resistor RR, switch SW and current source 2-4 are connected in series between the first power supply terminal 15 and a second power supply terminal which is grounded. The collector of the transistor QR.sub.0 is connected to the terminal 15, and the base of the same is connected to the junction point of the resistor RR and switch SW. The emitter of QR.sub.0 is grounded through the diode DR and current source 2-3. The resistors RR.sub.1 and RR.sub.2 are connected in series between the anode and cathode of the diode DR. The voltage V.sub.R is derived from the connection point of the resistors RR.sub.1 and RR.sub.2.
Upon the data-read operation, the switch SW is brought into an open state. Accordingly, the voltage of (V.sub.CC -V.sub.BE0) appears at the emitter of the transistor QR.sub.0, V.sub.BE0 being the base-emitter forward voltage. The diode DR is biased by the current IB of the current source 2-3, and thereby produces the forward voltage of V.sub.F0. The voltage at the connection point of the resistors RR.sub.1 and RR.sub.2 thus takes the level lowered by the voltage of ##EQU2## from the emitter potential of the transistor QR.sub.0. That is, the reading-out voltage V.sub.R takes the following level: ##EQU3##
(i) The diode DR is formed of Schottky diode, similarly to the diodes DC.sub.1 and DC.sub.2 in the memory cell.
(ii) RR.sub.1 =RR.sub.2 and RR.sub.1 +RR.sub.2 =RC.sub.1 (=RC.sub.2)
The voltage production part 10 thus produces the reading-out voltage having the intermediate potential between the base potentials of the transistors QC.sub.1 and QC.sub.2.
The resistance values of the resistors RC.sub.1 and RC.sub.2 are selected to an adequate value from the viewpoints of data-holding characteristics, a high speed operation and a low power consumption. In a memory device having memory capacity of 1,024 bits, each of the resistors RC.sub.1 and RC.sub.2 is designed to have a resistance value of about 10 KΩ, and in another memory device of 4096 bits, the values of the resistors RC.sub.1 and RC.sub.2 are choosen to 20 to 30 KΩ. From the above-mentioned condition (ii), the resistance values of the resistors RR.sub.1 and RR.sub.2 are, therefore, selected to 5 KΩ in the first mentioned memory device or to 10 to 15 KΩ in the last mentioned memory device. As apparent from the circuit configuration shown in FIG. 1, the output impedance of the voltage production part 10 is represented as a parallel compound value of the resistors RR.sub.1 and RR.sub.2. Assuming that the total value of input capacitances of the transistor Q.sub.1 and Q.sub.2 and the stray capacitance of an interconnection wiring layer for applying the reading-out voltage is 3 pF, the time constant for reading out the data is as follows:
3[pF]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 2 shows a preferred embodiment according to the present invention, in which the same constituents as those shown in FIG. 1 are denoted by the same reference numerals to omit their description. In FIG. 2, the voltage production part 10 in a read/write control circuit according to the present invention includes two NPN transistors QR.sub.0 and QR.sub.1, four resistors RRC, RRE, RB, and RB.sub.1, two diodes DR.sub.1 and DR.sub.2, a switch SW, and two constant current sources 2-3 and 2-4. The diode DR.sub.1 is formed of Schottky diode similarly to the clamping dodes DC.sub.1 and DC.sub.2 in the memory cell MC.sub.1, and the diode DR.sub.2 is formed of a p-n junction diode using the base-emitter junction of a transistor. The resistor RB.sub.1 and diodes DR.sub.2 and DR.sub.1 are connected in series between the terminal 15 and the ground point, and the resistor RR.sub.1 is connected in parallel with the diode DR.sub.1. The base of the transistor QR.sub.1 is connected to the node N.sub.1 of the resistor RB.sub.1 and diode DR.sub.2, and the emitter thereof is grounded through the resistor RRE. The collector of the transistor QR.sub.1 is connected to the terminal 15 through the resistor RRC. The node N.sub.2 of the transistor QR.sub.1 and the resistor RRC is connected to the base of the transistor QR.sub.0 and further grounded through the switch SW and current source 2-4. The collector of the transistor QR.sub.0 is connected to the terminal 15, and the emitter thereof is grounded through the current source 2-3. Derived from the emitter of the transistor QR.sub.0 is a reading-out voltage V.sub.R which is then supplied to the bases of the transistors Q.sub.1 and Q.sub.2.
Since the diodes DR.sub.1 and DR.sub.2 are biased by the current flowing through the resistor RB.sub.1, the following voltage V.sub.N1 appears at the node N.sub.1 :
V.sub.N1 =V.sub.F10 +V.sub.BE10                            (5)
where the voltages V.sub.F10 and V.sub.BE10 represent the forward voltages (or ON voltages) of the diodes DR.sub.1 and DR.sub.2, respectively, and their values are 0.5 [V] and 0.8 [V], respectively. The load circuit in the memory cell MC.sub.1 is composed of the parallel connection circuit of the diode DC.sub.1 (DC.sub.2) and resistor RC.sub.1 (RC.sub.2), and the diode DR.sub.1 and resistor RR.sub.1 in the voltage production part 10 are connected in parallel. Accordingly, the ON voltages of the diode DR.sub.1 and clamping diode DC.sub.1 (DC.sub.2) become equal to each other by making the current flowing through the resistor RB.sub.1 equal to the current IS of the constant current source 2-1 (2-2). The voltage V.sub.N1 at the node N.sub.1 is used as a base bias voltage of the transistor QR.sub.1. Since the diode DR.sub.2 is formed of the base-emitter junction of a transistor as mentioned above, the forward voltage of the diode DR.sub.2 is substantially equal to the base-emitter forward voltage of the transistor QR.sub.1. Therefore, the voltage drop across the resistor RRE is made equal to the ON voltage of the diode DR.sub.1. The emitter current I.sub.E of the transistor QR.sub.1 thus takes the following value: ##EQU4##
In the data-read operation, the switch SW is brought into the open-state. The base current of the transistor QR.sub.1 is negligible. Therefore, The voltage V.sub.N2 at the node N.sub.2 is: ##EQU5## As a result, the reading-out voltage V.sub.R derived from the emitter of the transistor QR.sub.0 is: ##EQU6## V.sub.BE20 being the base-emitter voltage of the transistor QR.sub.0.
The current IB of the constant current source 2-3 is selected to be equal to the current IS of the current source 2-1 (2-2), and therefore, the base-emitter forward voltages (V.sub.BE1 and V.sub.BE20) of the transistors QW.sub.1 and QR.sub.0 are made equal to each other. Even if the currents IB and IS are different from each other, the voltages V.sub.BE1 and V.sub.BE20 may be substantially equal to each other. The resistance ratio between the resistors RRC and RRE is choosen to be 1:2. Accordingly, the reading-out voltages represented by the equations (1) and (8) are made equal to each other.
Thus, the voltage production part 10 shown in FIG. 2 also produces the reading-out voltage V.sub.R having the intermediate level between the potentials at bases of the transistors QC.sub.1 and QC.sub.2.
In addition, the time constant for reading out the data in this circuit 10 is below 1 [nsec]. More specifically, the resistance value of the resistor RR.sub.1 should be selected to be equal to that of the resistor RC.sub.1 (RC.sub.2) in the memory cell MC.sub.1, but the values of the resistors RRC and RRE can be designed indepently of the resistors RC.sub.1 and RC.sub.2. In this embodiment, the resistance values of the resistors RRC and RRE are choosen to take 200 [Ω] and 400 [Ω], respectively, (i.e., RRC/RRE=1/2). The output impedance of the voltage production part 10 is determined by the impedances of the emitter follower transistor QR.sub.0 and the constant current source 2-3. The impedance of the constant current source 2-3 is extremely high, and therefore the output impedance of the circuit 10 is substantially equal to that of the transistor QR.sub.0. The output impedance of the transistor QR.sub.0 is determined by its current amplification gain h.sub.FE and the value of the resistor RRC, and represented by RRC/h.sub.FE. Accordingly, the time constant for producing the reading-out voltage V.sub.R indicated by the equation (1) (or (8)) at the emitter of the transistor QR.sub.0 is:
when h.sub.FE of the transistor QR.sub.0 is 100 and the total capacitance of input capacitances and stray capacitances is 3 [pF].
The change in ON voltage of the respective clamping diodes DC.sub.1 and DC.sub.2 causes a similar change in ON voltage of the diode DR.sub.1. Therefore, the reading-out voltage takes the intermediate level between the base potentials of the transistors QC.sub.1 and QC.sub.2, irrespective of the variation in potential at bases thereof.
The switch SW controls the data-read mode or data-write mode. When the switch SW is in an open stage, the memory device is brought into the data-read operation to produce the reading-out voltage V.sub.R. The closed state of the switch SW brings the memory device into the data-write mode. In this case, the resistor RRC is supplied with the current IW from the constant current source 2-4 in addition to the collector current of the transistor QR.sub.1. Consequently, the voltage drop across the resistor RRC becomes large to lower the emitter potential of the transistor QR.sub.0. The data stored in the cell is not thereby read-out. The lowering of the reading-out voltage, i.e., the discharge of electric charges in the input capacitances of Q.sub.1 and Q.sub.2 and stray capacitance, is attained by the current IB of the constant current source 2-3. This current IB is also selected indepently of the current flowing through the memory cell MC.sub.1, and thus takes a relatively large value, 3 [mA] for example. In this current value, the discharge time constant is about 0.5 [nsec] .
FIG. 3 shows another embodiment of the present invention, in which the same constituents as those in FIG. 2 are indicated by the same references. The circuit 10 shown in FIG. 3 does not include the resistor RR.sub.1 connected in parallel with the diode DR.sub.1. Accordingly, the current flowing through the diode DR.sub.1 is changed by the following value:
when the resistance value of the resistor RR.sub.1 is 10 KΩ and the ON voltage V.sub.F10 of the diode DR.sub.1 is 0.5 [V]. This change causes the variation in ON voltage V.sub.F10 by 3 [mV], but this variation in ON voltage is negligble in a practical use. Accordingly, the circuit shown in FIG. 3 has a simplified configuration, as compared with that in FIG. 2.
In FIGS. 2 and 3, the resistor RB.sub.1 may be replaced by a constant current source. Further, it is possible that the power supply terminal 15 is applied with the ground potential and the ground potential point is replaced by a power supply terminal applied with -V.sub.cc potential.
Referring to FIG. 4, the construction and operation of a memory device according to the present invention will be described. This memory device is controlled by a chip-select signal supplied to a chip-enable terminal CE. When the chip-select signal takes a high level, transistors Q.sub.70 and Q.sub.71 are turned on. The base voltage of a transistor Q.sub.72 is thereby higher than a reference voltage V.sub.ref at the base of a transistor Q.sub.73 to make transistors Q.sub.74 and Q.sub.75 conductive. As a result, the voltage at a data output terminal D.sub.OUT is held at a low level, irrespective of the levels of signals SA and SA. In other words, the data-read operation is not carried out. The conduction of the transistor Q.sub.71 turns transistors Q.sub.63 and Q.sub.67 on. Accordingly, a second write-control signal WC derived from a transistor Q.sub.65 takes a low level. It should be noted that the collector current of the transistor Q.sub.67 flows through a resistor R.sub.62. The currents of constant current sources 2-4 and 52 are selected to be equal to each other, and therefore the voltage drops across the resistors R.sub.61 and R.sub.62 are equal to each other. As a result, a first write-control signal WC derived through a transistor Q.sub.66 also takes a low level. The signals WC and WC thus take the low level to inhibit a data-write operation. As mentioned above, when the chip-select signal takes the high level, this memory device is unselected.
Row address signals are supplied to row address terminals RA.sub.0 to RA.sub.i. A row address decoder 20 makes the level of one of word signals W.sub.1 to W.sub.n a selective level in response to the row address signals. The remaining ones of word signals W.sub.1 to W.sub.n take an unselective level. Assuming that the signal W.sub.1 takes the selectivel level (being substantial equal to Vcc level), memory cells MC.sub.1 and MC.sub.2 are selected by transistors QW.sub.1 and QW.sub.2 whose bases are supplied with the signal W.sub.1. Each of memory cells MC.sub.1 to MC.sub.6 has the same configuration as shown in FIGS. 2 and 3.
Column address signals are supplied to column address terminals CA.sub.0 to CA.sub.j. A column decoder 30 makes the level of one of digit signals D.sub.1 to D.sub.m a low level and remaining ones of digit signals a high level. If the digit signal D.sub.1 takes a low level, transistors Q.sub.80 and Q.sub.81 are made nonconductive. On the other hand, other transistors (transistors Q.sub.82 and Q.sub.83 in FIG. 4) supplied with remaining digit signals are turned on. A pair of digit lines DL.sub.1 and DL.sub.1 in thus selected. As a result, The memory cell MC.sub.1 is designated.
In a data-read operation, a write-enable signal supplied to a write-enable terminal WE takes a high level. Transistors Q.sub.59, Q.sub.62 and Q.sub.68 are thereby turned on. Accordingly, the second write-control signal WC takes the low level. It should be noted that the collector current of the transistor Q.sub.68 also flows through the resistor R.sub.62. As a result, the first write-control signal WC also takes the low level to inhibit the data-write.
Since the base voltage of the transistor Q.sub.68 is higher than the reference voltage V.sub.ref applied to a transistor Q.sub.69, the switch SW consisting of the transistor Q.sub.69 is brought into an open-state. As a result, the reading-out voltage having a predetermined level is produced from the voltage production part 10 as described in FIG. 2.
If the data "1" is stored in the designated memory cell MC.sub.1, the transistor Q.sub.1-1 is made nonconductive, whereas the transistor Q.sub.2-1 is made conductive. The collector outputs SA and SA of the transistors Q.sub.1-1 and Q.sub.2-1 are supplied to a sense amplifier 40. A voltage drop is thus produced only across a resistor R.sub.70. Accordingly, transistors Q.sub.76 and Q.sub.77 are turned on, and transistors Q.sub.75 and Q.sub.78 are turned off. The data "1" having a high level is thus derived from the data-out terminal Dout.
In the data-write operation, the write-enable signal to the terminal WE takes a low level. The transistor Q.sub.62 and Q.sub.68 are thereby made nonconductive. The transistors Q.sub.63 and Q.sub.67 are in an off-state in a chip-select condition. Accordingly, the transistor Q.sub.69 constituting the switch SW is turned on to lower the level of the reading-out voltage V.sub.R. Both of the transistors Q.sub.1-1 and Q.sub.2-1 are thereby made nonconductive.
The level at a data-in terminal D.sub.IN controls whether the data to be written is "1" or "0". When the level at the terminal D.sub.IN takes a high level, transistors Q.sub.60 and Q.sub.61 are turned on. Accordingly, the second write-control signal WC takes the low level. At this time, the current of the current source 2-4 does not flow through the resistor R.sub.62, and hence the first write-control signal WC takes a high level. Consequently, a transistor Q.sub.50 is made conductive, whereas a transistor Q.sub.51 is made nonconductive. The transistors QC.sub.1 and QC.sub.2 (FIG. 2) of the designated memory cell MC.sub.1 are thus turned off and on, respectively. That is, the data "0" is stored in the cell MC.sub.1.
On the contrary, the terminal D.sub.IN is applied with a low level,and a transistor Q.sub.64 is turned on. The first and second write-control signals WC and WC thus take the low level and the high level, respectively. As a result, the data "1" is stored in the designated memory cell.
BACKGROUND OF THE INVENTION The present invention relates to a semiconductor memory device constituted by bipolar transistors, and more particularly to a read/write control circuit controlling a data-read operation and a data-write operation.
SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide a semiconductor memory device having an improved control circuit for producing a reading-out voltage taking a predetermined potential.
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