Source: https://patents.google.com/patent/JP2010161376A/en
Timestamp: 2020-01-21 17:35:51
Document Index: 130076804

Matched Legal Cases: ['art 134', 'art 136', 'art 136', 'art 134', 'art 137', 'art 135', 'art 234', 'art 236']

JP2010161376A - Resistance variable memory device and method of fabricating the same - Google Patents
Resistance variable memory device and method of fabricating the same Download PDF
JP2010161376A
JP2010161376A JP2010004343A JP2010004343A JP2010161376A JP 2010161376 A JP2010161376 A JP 2010161376A JP 2010004343 A JP2010004343 A JP 2010004343A JP 2010004343 A JP2010004343 A JP 2010004343A JP 2010161376 A JP2010161376 A JP 2010161376A
JP2010004343A
眞浩 ▲呉▼
Hyun Suk Kwon
惠英 朴
正熙 朴
賢俶 權
龍湖 河
2009-01-09 Priority to KR1020090001975A priority Critical patent/KR20100082604A/en
2010-01-08 Priority to US12/684,140 priority patent/US20100176365A1/en
2010-01-12 Application filed by Samsung Electronics Co Ltd, 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． filed Critical Samsung Electronics Co Ltd
2010-07-22 Publication of JP2010161376A publication Critical patent/JP2010161376A/en
<P>PROBLEM TO BE SOLVED: To provide a resistance variable memory device and a method of fabricating the same. <P>SOLUTION: The resistance variable memory device includes at least one bottom electrode, a first insulating layer containing a trench which exposes the at least one bottom electrode, and a resistance variable material layer including respective first and second portions located on opposite sidewalls of the trench, respectively, where the first and second portions of the resistance variable material layer are electrically connected to the at least one bottom electrode. The device further includes a protective layer covering the resistance variable material layer within the trench, and a second insulating layer located within the trench and covering the protective layer within the trench. <P>COPYRIGHT: (C)2010,JPO&INPIT
The present invention relates to a memory element. Specifically, such types of memory elements according to the present invention include, for example, programmable variable resistance memory elements called phase change memory elements.
Any type of non-volatile memory element relies on programmable resistance characteristics such as memory cells for storing data. This type of memory element is generally referred to as a variable resistance memory element (eg, a phase change memory element).
PRAM (phase-change random access memory), well known as OUM (Ovonic Unified Memory), is a chalcogenide mixture that stably changes to a crystalline and amorphous state in response to energy (for example, thermal energy). Phase change materials such as For example, PRAM is disclosed in Patent Document 1 and Patent Document 2.
The phase change material of PRAM exhibits a relatively low resistance in the crystalline state and exhibits a relatively high resistance in the amorphous state. In general, a low resistance crystalline state is represented as 'set' and logically represents '0'. On the other hand, the high resistance amorphous state is represented as 'reset' and logically represents '1'. For example, a multi-bit can be implemented by programming two or more bits in each phase change cell by programming another crystal state having another resistance.
The terms 'crystalline' and 'amorphous' are relative terms depending on the context of the phase change material. That is, when referring to a phase change memory cell being in a crystalline state, one skilled in the art can understand that the phase change material of the cell has a crystalline structure that is more regular than the amorphous state. A crystalline phase change memory cell need not be completely crystalline, and an amorphous phase change memory cell need not be completely amorphous.
In general, the phase change material of PRAM is reset to amorphous by Joule heat exceeding its melting point temperature in a relatively short time. On the other hand, the phase change material is set to be crystalline by heat applied under the melting temperature for a longer time. In each case, the material is cooled to its original temperature after heat treatment. However, cooling generally occurs more rapidly when the phase change material is reset to an amorphous state.
The speed and safety of the phase change characteristics of the phase change material is critical to the operating characteristics of the PRAM. As suggested above, mixtures of chalcogenides have been found to have suitable phase change properties. Specifically, a compound containing germanium (Ge), antimony (Sb), and tellurium (Te) (for example, Ge 2 Sb 2 Te 5 , or GST) is stable and quickly switches between crystalline and amorphous. Changes at a rapid rate.
US Pat. No. 6,487,113 US Pat. No. 6,480,438
The present invention has been made in view of the above-described problems, and an object thereof is to provide a variable resistance memory element having high reliability.
In order to achieve the above-described problem to be solved by the present invention, a variable resistance memory device according to an embodiment of the present invention includes a first insulation including at least one lower electrode and a trench exposing the at least one lower electrode. And a variable resistance material film including first and first portions respectively positioned on opposite sides of the trench, wherein the first and second portions of the variable resistance material film include the at least one It is electrically connected to the two lower electrodes. The device further includes a protective film covering the variable resistance material film in the trench, and a second interlayer insulating film disposed in the trench and covering the protective film in the trench.
The concept according to the present invention will be described. A variable resistance memory device is provided having a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells connected to each word line and each bit line. Each of the memory cells includes a variable resistance material layer located on opposite sides of a trench formed in a material layer interposed between the word line and the bit line, and the variable resistance in the trench. A protective film covering the resistive material film and an insulating film located in the trench and covering the protective film in the trench are included.
The concept according to the present invention will be described. A method of forming a variable resistance memory element includes providing a first insulating film including first and second electrodes, forming a second insulating film on the first insulating film, Forming a trench exposing at least a portion of the first and second electrodes, and forming a variable resistance material film in the trench so as to be in electrical contact with the first and second lower electrodes. Forming a variable resistance material located on the bottom surface and the opposite side surface of the trench. The method includes forming a protective film on the variable resistive material film, removing a part of the protective film, and positioning on the variable resistive material film on the opposing side surfaces of the trench. Forming the separated first and second protective film portions, and a part of the variable resistance material layer on the bottom surface of the trench is exposed between the first and second protective film portions. And removing the exposed portions of the variable resistance material film to define first and second variable resistance material film portions on the opposing sides of the trench. The method further includes filling the trench with a second insulating film and forming first and second upper electrodes electrically connected to the first and second variable resistance material film portions.
According to the present invention, the variable resistance memory device can reduce the driving current required to change the state. The protective film can be protected from the influence of the subsequent process of the variable resistance pattern, and heat loss to the periphery can be reduced.
It is a circuit diagram which shows a part of memory cell of a variable resistance memory element. 1 is a perspective view of a variable resistance memory device according to an embodiment of the present invention. FIG. 3 is a plan view schematically showing the variable resistance memory element of FIG. 2. FIG. 4 is a cross-sectional view taken along the line I-I ′ of FIG. 3. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a variable resistance memory element according to an embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a variable resistance memory element according to an embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a variable resistance memory element according to an embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a variable resistance memory element according to an embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a variable resistance memory element according to an embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a variable resistance memory element according to an embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a variable resistance memory element according to an embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a variable resistance memory element according to an embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a variable resistance memory element according to an embodiment of the present invention. FIG. 5 is a perspective view of a variable resistance memory device according to another embodiment of the present invention. FIG. 7 is a schematic plan view of the variable resistance memory element of FIG. 6. It is sectional drawing cut along I-I 'of FIG. FIG. 5 is a cross-sectional view illustrating a variable resistance memory device according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a variable resistance memory device according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a variable resistance memory device according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a variable resistance memory device according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a variable resistance memory device according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a variable resistance memory device according to another embodiment of the present invention. 1 is a block diagram illustrating a memory system and a device including a variable resistance memory device according to an embodiment of the present invention. 1 is a block diagram illustrating a memory system and a device including a variable resistance memory device according to an embodiment of the present invention. 1 is a block diagram illustrating a memory system and a device including a variable resistance memory device according to an embodiment of the present invention. 1 is a block diagram illustrating a memory system and a device including a variable resistance memory device according to an embodiment of the present invention. 1 is a block diagram illustrating a memory system and a device including a variable resistance memory device according to an embodiment of the present invention. 1 is a block diagram illustrating a memory system and a device including a variable resistance memory device according to an embodiment of the present invention. 1 is a block diagram illustrating a memory system and a device including a variable resistance memory device according to an embodiment of the present invention. 1 is a block diagram illustrating a memory system and a device including a variable resistance memory device according to an embodiment of the present invention.
Various embodiments are described with reference to the drawings, wherein like reference numerals indicate identical or similar configurations. However, the inventive idea can be embodied in various forms and is not limited to the described embodiments.
In the drawings, the relative dimensions of the membrane can be exaggerated for effective explanation. That is, for example, the relative thickness and / or width of the membrane can be varied from that disclosed. For example, unless the technique is specifically stated to be different, if the first film appears thicker than the second film, the second film can have the same thickness, or the second film can be the first film It can be thicker.
For ease of understanding, the number of terms described without limitation is utilized without intending to define the scope of the inventive idea. For example, even if terms such as 'first' and 'second' are used for various elements, such elements are not limited by such terms. Such terms are simply used to distinguish elements from each other. For example, a first element can be named a second element, and similarly, a second element can be named a first element, without limiting or departing from the scope of the inventive idea. Similarly, the idea of the invention is not intended to be limited by the direction of a specific element by relative words such as 'up', 'down', 'upper', 'lower', etc. As used herein, 'and / or' includes all combinations of any one or more of the items described.
And the terminology used here is often quoted in the “film” of matter. Where quoted is a material film, it is understood that the inventive idea is not limited to a single film structure. For example, the insulating film may actually include a multilayer film of an insulating material that performs essentially the same insulating function as a single insulating film. The same principle applies to semiconductor conductive regions and films.
When an element refers to 'connected' or 'coupled' with a different element, this is directly connected or combined with another element, or provided by an intervening element To be understood. On the contrary, when an element refers to 'directly connected' or 'directly connected' with a different element, there is no intervention element. Other words used to describe the relationship between elements (eg, “between” and “directly between”, “adjacent” and “directly adjacent”, etc.) should be interpreted in the same way.
The terminology herein is for the purpose of describing particular embodiments and is not intended to be limiting of the invention. In this specification, the singular forms also include plural forms unless the context clearly indicates otherwise. As used herein, “include” refers to the presence, addition, or addition of one or more other components, steps, operations, elements and / or combinations thereof. Do not exclude.
Unless otherwise defined, all terms used herein (including technical and scientific terms) have the meanings that are commonly understood by one of ordinary skill in the art to which this invention belongs. As generally defined in terms of dictionaries, terms must be interpreted as having a consistent meaning to suit the context of the appropriate field, and are ideal unless expressed herein. Or overly formal meaning.
FIG. 1 is a circuit diagram illustrating a part of a memory cell array of a variable resistance memory device according to an embodiment of the present invention. Referring to FIG. 1, a memory cell array is connected between a plurality of word lines WL and a plurality of bit lines BL, and a plurality of unit memory cells 10 located in a region where the word lines WL and the bit lines BL intersect. Can be included. For example, each unit memory cell 10 may include a variable resistance storage element 11 and a switching element 12. For example, the variable resistance storage element 11 may be a phase change storage element, and the switching element 12 may be a diode or a transistor element.
FIG. 2 is a perspective view of a variable resistance memory device according to an embodiment of the present invention.
Referring to FIG. 2, the variable resistance memory device according to the present embodiment extends over the plurality of word lines WL and the plurality of word lines WL in a direction substantially perpendicular to the plurality of word lines WL. A plurality of upper electrode pairs 161 and 162 are included. As will be described later, the two variable resistance memory cells are located at the intersection regions of the plurality of word lines WL and the upper electrode pairs 161 and 162.
Referring to FIG. 2, the variable resistance memory device includes a pair of selection elements 102 located in regions where the plurality of word lines WL and the upper electrode pairs 161 and 162 intersect each other. One of the pair of selection elements 102 is aligned under the upper electrode 161, and the other one of the pair of selection elements 102 is aligned under the upper electrode 162. For example, the selection element 102 may be implemented with a diode element and / or a transistor element. When the selection element 102 is a diode element, the diode element includes an N-type semiconductor film and a P-type semiconductor layer that are in contact with each other, and the N-type semiconductor layer can be electrically connected to the word line WL. . When the selection element 102 is a transistor element, the transistor element can be controlled by the word line WL, and a lower electrode 112 (described below) and a reference potential (for example, ground potential) can be electrically connected in series. .
The lower electrode 112 is positioned on the corresponding selection element 102 and can be electrically connected to the corresponding selection element 102. For example, each lower electrode 112 can function as a part of a heater by Joule heat of a phase change material (described later) of a corresponding memory cell. The plurality of lower electrodes may be embodied as a single conductive film or a plurality of conductive films. For example, each lower electrode 112 may include an electrical conductive film in contact with the selection element 102 and an electrical / thermal conductive film stacked on the electrical conductive film. An example of the material of the lower electrode 112 is provided with reference to FIG. 5A.
Next, referring to FIG. 2, the pair of variable resistance storage patterns 131/132 is located between each of the upper electrode pair 161/162 and the corresponding lower electrode pair 112. That is, each of the variable resistance storage patterns 131 and 132 extends long below the corresponding upper electrode 161 and 162 and intersects the plurality of lower electrodes 112 in a direction perpendicular to the plurality of word lines WL (for example, Bit line direction and alignment).
A part of each variable resistance storage pattern 131 located on the lower electrode 112 constitutes a storage element that stores one or more bits of data, and a part of the variable resistance storage pattern 132 includes one or more data. The storage element for storing the bits is configured. When each variable resistance storage pattern 131, 132 is made of a phase change material (eg, GST), each storage element of the variable resistance storage pattern 131, 132 can be programmed. For example, the low resistance crystalline state ('set' state) can store '0', or the high resistance amorphous state ('reset' state) can store '1'. . Unlike this, the cell is programmed to another crystal state having another resistance, and two or more bits are stored in each phase change cell, thereby realizing a “multi-bit”. Can be done.
In the example of FIG. 2, each of the variable resistance storage patterns 131 and 132 can generally have an L shape. In addition to this, as shown in the drawing, the L shapes of the storage patterns 131 and 132 face each other. As shown in FIG. 2, the protective film pattern pairs 141 and 142 can cover the facing surfaces of the variable resistance storage patterns 131 and 132, respectively.
The embodiment of FIG. 2 will be described in more detail with reference to FIGS.
3 is a schematic plan view of the variable resistance memory device illustrated in FIG. 2, and FIG. 4 is a cross-sectional view taken along the line I-I 'of FIG.
Referring to FIG. 3, the variable resistance memory device includes a plurality of bit lines BL extending in a direction substantially perpendicular to the plurality of word lines WL on the plurality of word lines WL. The array of the plurality of lower electrodes 112 is located in a region where the plurality of bit lines BL and the plurality of word lines WL intersect. In addition, the pair of variable resistance storage patterns 131 and 132 may be disposed on the lower electrode 112 that is aligned below each adjacent bit line BL and below the length of each bit line BL. Extends long.
Referring to FIG. 4, the first interlayer insulating layer 110 is located on the upper surface of the substrate 101, and the first and second lower electrodes 112 are embedded in the first interlayer insulating layer 110. The As described above, when the memory device employs a phase change material as a variable resistance storage device, the plurality of lower electrodes 112 may include a multilayer film having at least one film functioning as a Joule heat element. A conductive film can be formed. Similarly, the first interlayer insulating film 110 may be formed as a single film or a multilayer film.
Although not shown in FIG. 4, the substrate 101 (and / or one or more films interposed between the substrate 101 and the first interlayer insulating film 110) includes each of the lower electrode 112 and a word line ( A switching element (eg, a diode or a transistor) that is electrically connected to the device (not shown in FIG. 4) may be included.
The second interlayer insulating film 120 (or a plurality of films) is located on the first interlayer insulating film 110, and the etch stop film 121 (or a plurality of films) is located on the second interlayer insulating film 120. According to an exemplary embodiment of the present invention, the second interlayer insulating layer 120 and the etch stop layer 121 are defined inside and aligned on a region between a plurality of adjacent lower electrodes 112. And a trench 122 that is partially overlapped.
The first and second variable resistance storage patterns 131 and 132 are located on sidewalls of the second interlayer insulating film 120 that face the trench 122. Specifically, the first storage pattern 131 includes a bottom part 134 located on the upper surface part of the first lower electrode 112 and a side wall part 136 located on the side surface 124 of the trench 122. For example, the first and second variable resistance storage patterns 131 and 132 may be formed of a phase change material such as a GST compound.
Next, referring to FIG. 4, a plurality of protective film patterns 141 and 142 may cover the exposed surfaces of the variable resistance storage patterns 131 and 132 in the trench 122, respectively. A space in the trench 122 between the plurality of protective film patterns 131 and 132 is filled with the insulating film 150.
As shown in FIG. 4, the third interlayer insulating film 170 (or a plurality of films) is located on the second interlayer insulating film 120. The first and second upper electrodes 161 and 162 are positioned in the third interlayer insulating layer 170 and are in electrical contact with the variable resistance storage patterns 131 and 132, respectively. Each of the first and second upper electrodes 161 and 162 includes a barrier film 163 on the lower surface thereof.
Finally, a plurality of bit lines BL are positioned on or in the third interlayer insulating film 170, and a plurality of contact plugs 171 are connected to the plurality of bit lines BL and the plurality of upper electrodes 161 and 162. The plurality of bit lines BL and the upper electrodes 161 and 162 are electrically connected to each other.
5A to 5I are cross-sectional views illustrating a variable resistance memory device according to an embodiment of the present invention.
Referring to FIG. 5A, a first interlayer insulating layer 110 is formed on the surface of the lower layer 101. In this embodiment, the lower film 101 is a semiconductor film, an SOI substrate, or the like. Although not shown in FIG. 5A, the lower layer 101 may include a switching element (eg, a diode or a transistor) electrically connected to a word line (not shown in FIG. 5A). In this embodiment, the first interlayer insulating film 110 may be either formed in the silicon oxide film SiO 2, or other material is used instead. For example, the first interlayer insulating layer 110 may be formed of BSG (borosilicate glass), PSB (phosphorus silica glass), BPSG (borophosphosilicate glass), PE-TEOS (plasma-enhanced tetralithium, etc.). Can be done.
As shown in FIG. 5A, first and second lower electrodes 112 are formed in the first interlayer insulating layer 110. For example, the plurality of lower electrodes 112 may be used to define a plurality of lower electrodes 112 by etching contact holes in the interlayer insulating layer 110 and then depositing a plurality of material layers of the lower electrodes 112. The material film may be formed by planarizing (for example, CMP).
The shape of the plurality of lower electrodes 112 is not limited. Although not limited to the example, the plurality of lower electrodes 112 may have a circular or quadrangular cylindrical shape, or the plurality of lower electrodes 112 may have a ring-shaped cross-section. As described above, the plurality of lower electrodes 112 may be formed of a multilayer film of another material. The materials constituting the plurality of lower electrodes 112 are Cu, Ti, TiSiX, TiN, TiON, TiAlN, TiAlON, TiSiN, TiBN, W, WSiX, WN, WON, WSiN, WBN, WCN, Ta, TaSiX, TaN, One or more of TaON, TaAlN, TaSiN, TaCN, Mo, MoN, MoSiN, MoAlN, NbN, ZrSiN, ZrAlN, Ru, CoSiX, NiSiX, and conductive carbon can be included, but are not limited thereto.
Referring to FIG. 5B, a second interlayer insulating layer 120 is deposited on the first interlayer insulating layer 110. For example, the second interlayer insulating film 120 may be formed SiO 2, BSG, PSB, PBSG, and the like in PE-TEOS. An etch stop layer 121 may be formed on the second interlayer insulating layer 120 and patterned. The etch stop layer 121 may include SiN, SiON, HfO, and AlO, but is not limited thereto. The etch stop layer 121 has a high etch selectivity with respect to the second interlayer insulating layer 120 and is used as an etching mask for etching the trench 122 in the second interlayer insulating layer 120. The trench 122 is etched to expose at least a part of the upper surface of the pair of lower electrodes 112 adjacent to the bottom surface 123 thereof. As shown in the drawing, the side surface 124 of the trench 122 is formed to be inclined, and the width of the trench 122 may be wider at the upper opening than at the bottom surface 123.
Next, referring to FIG. 5C, a variable resistance material film 130 is deposited along the surface of the structure shown in FIG. 5B. That is, the variable resistance material layer 130 is deposited to conformally cover the etch stop layer 121, the side surface 124 of the trench 122, and the bottom surface 123 of the trench 122. For example, the variable resistance material layer 130 may be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). For example, the variable resistance material layer may be formed of a phase change material. Suitable phase change material films can include, but are not limited to, SeSbTe, GeTeAs, SnTeSn, GeTe, SbTe, SetSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe. In addition, for example, the variable resistance material layer 130 may be doped with carbon, nitrogen, silicon, and / or oxygen.
Next, referring to FIG. 5D, a protective layer 140 may be deposited on the variable resistance material layer 130. For example, the passivation layer 140 is deposited according to the topology of the variable resistance material layer 130 and does not completely fill the trench 122. For example, the depth of the passivation layer 140 may be less than half of the width of the trench 122 to prevent the trench 122 from being filled.
In operation of the manufactured variable resistance memory device, the protective layer 140 may function to prevent heat loss of the variable resistance layer. The protective layer 140 functions to protect the variable resistance material layer 130 from process damage received in a series of manufacturing steps. For example, the passivation layer 140 may protect the variable resistance material layer 130 from etching conditions and / or oxygen exposure (eg, oxygen diffusion) during a series of processes.
For example, the protective film includes, but is not limited to, a silicon nitride film, a silicon carbon nitride film, a carbon nitride film, and / or carbon. For example, the protective layer 140 is a silicon nitride layer formed using PC-CVD (plasma enhanced CVD) at a temperature of about 380 to 400 ° C. As described above, the variable resistance material layer 130 may be doped with carbon, nitrogen, silicon, and / or oxygen. In this case, the volatilization temperature of the doped material can be higher than that of the undoped material.
Next, referring to FIG. 5E, the protective film 140 is removed except for a part of the protective film 140 on the plurality of opposite side walls 124. That is, as shown in the drawing, the protective layer 140 is partially removed, and a plurality of protective layer patterns 141 and 142 are defined on the variable resistance material layer 130 in the trench 122. For example, the plurality of protective film patterns 141 and 142 may be formed by anisotropically etching the protective film 140.
FIG. 5E illustrates the inner edges of the plurality of passivation patterns 141 and 142 aligned with the inner edges of the plurality of lower electrodes 112. However, it is not limited to this embodiment.
Referring to FIG. 5F, the variable resistance material layer 130 is patterned to form a plurality of variable resistance storage patterns 131 and 132. For example, this may be caused by using the exposed portions of the variable resistance material layer 130 (the upper portion of the etching stop layer 121 and the inside of the trench 122) using the plurality of protective layer patterns 141 and 142 as an etching stop layer. Can be removed by etching in the direction. The plurality of protective film patterns 141 and 142 may protect the plurality of variable resistance storage patterns 131 and 132 from damage during the etching process.
According to the result of this etching process, the plurality of variable resistance patterns 131 and 132 are mirror-symmetric with each other under each of the plurality of protective film patterns 141 and 142, and the cross section is generally defined as an L shape. The Specifically, the variable resistance storage pattern 131 includes a sidewall part 136 and a bottom part 134, and the variable resistance pattern 132 includes a sidewall part 137 and a bottom part 135.
Next, referring to FIG. 5G, a gap between the plurality of passivation layer patterns 141 and 142 is filled with an insulating material 150. For example, this can be performed by depositing an insulating material and performing a planarization process. For example, the deposited insulating material may be HDP (high density plasma) oxide, PE-TEOS (plasma-enhanced tetraethylosilicate), BPSG (borophosphosilicate glass), USG (undosp, For example, the planarization may be performed using a chemical mechanical polishing (CMP) or an etch-back process using silicon oxide such as HSQ (hydrosilsesquioxane) and SOG (spin on glass). In other cases, the etch stop layer 121 may be used as a removal stop layer, and during the planarization process, the etch stop layer 121 may be used. Some of the time stop layer 121 (FIG. 5F see) the protruded from a plurality of protective insulation pattern 141 and 142 can be removed to define a structure having a flat upper surface.
Although not shown in the drawing, the planarization process may be followed by plasma treatment using an inert gas. Although not limited thereto, the inert gas includes Ar, He, Ne, Kr and / or Xe. A sputter process is performed after the planarization process, so that damaged or oxidized portions of the plurality of variable resistance film patterns 131 and 132 are removed.
Next, referring to FIG. 5H, a barrier material film and an electrode material film are deposited and patterned using known techniques (eg, deposition, masking, and etching) to form a plurality of layers on the barrier film 163. Upper electrodes 161 and 162 are respectively defined. For example, the material of the plurality of upper electrodes 161 and 162 may be Ti, TiSiX, TiN, TiON, TiW, TiAlN, TiAlON, TiSiN, TiBN, W, WSiX, WN, WON, WSiN, WBN, Including WCN, Ta, TaSiX, TaN, TaON, TaAlN, TaSiN, TaCN, Mo, MoN, MoSiN, MoAlN, NbN, ZrSiN, ZrAlN, Ru, CoSi, NiSi, conductive carbon and copper.
The barrier film 163 can function as an adhesive film, and can prevent diffusion between the plurality of upper electrodes 161 and 162 and a plurality of lower films such as the plurality of lower variable resistance film patterns 131 and 132. For example, the barrier film 163 may include TiN, TiW, TiCN, TiAlN, TiSiC, TaN, TaSiN, WN, MoN, and CN.
If the plurality of variable resistance film patterns 131 and 132 include a phase change material such as a GST (or chalcogenide) material, is the barrier film 163 the same as the plurality of variable resistance film patterns 131 and 132? Alternatively, it can be formed to include other phase change materials. As described above, this may have an advantage that damage that can occur in the plurality of variable resistance film patterns 131 and 132 can be compensated while the insulating film 150 is planarized. For example, the barrier layer 163 may include a structure in which a GST material layer and a conductive layer are stacked.
Next, referring to FIG. 5I, a third interlayer insulating layer 170 is deposited, a plurality of contact plugs 171 are formed in the interlayer insulating layer 170, and a plurality of conductive bit lines BL are connected to the plurality of contact plugs 171. Formed in electrical contact. Techniques and materials well known in the industry can be used to form such devices. As shown in FIGS. 2 and 3, the plurality of bit lines BL extend in a direction parallel to the plurality of variable resistance film patterns 131 and 132.
FIG. 6 is a perspective view illustrating a variable resistance memory device according to another embodiment of the present invention.
As shown in FIG. 2, the variable resistance memory device of this embodiment extends in a direction substantially perpendicular to the plurality of word lines WL on the plurality of word lines WL and the plurality of word lines WL. A plurality of upper electrodes 261 may be included. As will be described later, the variable resistance memory cell is located in a region where the plurality of word lines WL and the upper electrode 261 intersect each other.
Next, referring to FIG. 6, the variable resistance memory device includes a selection element 202 in a region where the plurality of word lines WL and the plurality of upper electrodes 261 intersect each other. One of the plurality of selection elements 202 is aligned under the upper electrode 261. For example, the plurality of selection elements 202 may be implemented by diode elements and / or transistor elements. When the plurality of selection elements 202 are diode elements, the diode elements include a P-type semiconductor layer and an N-type semiconductor layer that are in contact with each other, and the N-type semiconductor layer is electrically connected to the word line WL. be able to. When the selection element 202 is a transistor element, the transistor element can be controlled to the word line WL, and a lower electrode 212 (described later) and a reference potential (for example, ground potential) can be electrically connected in series.
The lower electrode 212 is positioned on the corresponding selection element 202 and is electrically connected to the corresponding selection element 202. For example, each of the lower electrodes 212 functions as a part of the heater due to Joule heat of the phase change material of the corresponding memory cell. The plurality of lower electrodes 212 may be implemented as a single conductive film or a multilayer conductive film. For example, each of the lower electrodes 212 may include an electrical conductive film in contact with the selection element 202 and an electrical / thermal conductive film stacked on the electrical conductive film. An example of the material of the lower electrode 212 will be described later with reference to FIG. 5A.
As shown in FIG. 6, the variable resistance storage pattern 231 is located between each upper electrode 261 and the corresponding lower electrode 212. That is, each variable resistance storage pattern 231 extends long under the corresponding upper electrode 261 and intersects the plurality of lower electrodes 212 in a direction perpendicular to the plurality of word lines WL (for example, in the bit line direction). Alignment).
A part of each variable resistance storage pattern 231 located on the lower electrode 212 constitutes a storage element that stores one or more bits of data. When each of the plurality of variable resistance storage patterns 231 is made of a phase change material (eg, GST), each storage element of the plurality of variable resistance storage patterns 231 can be programmed. For example, a low resistance crystalline state ('set' state) may store '0', or a high resistance amorphous state ('reset' state) may store '1'. Unlike this, the cell is programmed to another crystal state having another resistance, and two or more bits are stored in each phase change cell to implement a “multi-bit”. Can do.
In the embodiment of FIG. 6, each variable resistance storage pattern 231 is generally U-shaped. As shown in FIG. 6, a plurality of protective film patterns 241 are provided to cover the inner surfaces of the U-shaped variable resistance storage patterns 231.
The embodiment of FIG. 6 will be described in more detail with reference to FIGS.
FIG. 7 is a schematic plan view of the variable resistance memory device illustrated in FIG. 6, and FIG. 8 is a cross-sectional view taken along the line I-I 'of FIG.
As shown in FIG. 7, the variable resistance memory device includes a plurality of bit lines BL extending substantially perpendicular to the plurality of word lines WL on the plurality of word lines WL. The plurality of lower electrode 212 arrays are located in a region where the plurality of bit lines BL and the plurality of word lines WL intersect. The variable resistance storage pattern 231 extends long on the plurality of lower electrodes 212 aligned below each bit line BL and below the length direction of each bit line BL.
Referring to the cross-sectional view of FIG. 8, as shown in the drawing, the first interlayer insulating film 210 is located on the upper surface of the substrate 201, and the lower electrode 212 is embedded in the first interlayer insulating film. The As described above, when the memory element employs a phase change material as a variable resistance storage element, the plurality of lower electrodes 212 has a multi-layer conductive structure having at least one film functioning as a Joule heat element. It can be formed of a film. Similarly, the first interlayer insulating film 210 may be formed as a single film or a multilayer film.
Although not shown in FIG. 8, the substrate 201 (and / or one or more films are interposed between the substrate 201 and the first interlayer insulating film 201) may be connected to the lower electrode 212 and the word. It includes a switching element (eg, a diode or a transistor) electrically connected to a line (not shown in FIG. 8).
The second interlayer insulating film 220 (or a plurality of films) is located on the first interlayer insulating film 210, and the etch stop film 221 (or a plurality of films) is located on the second interlayer insulating film 220. According to this embodiment, the second interlayer insulating layer 220 and the etch stop layer 221 are defined therein, aligned on the lower electrode 212, and partially overlap the lower electrode 212. ). In FIG. 8, reference numeral 223 represents the bottom surface of the trench 222, and reference numeral 224 represents the side surface of the trench 222.
The variable resistance storage pattern 231 is located on the opposite side wall 224 and the bottom 223 of the trench 222. Specifically, the variable resistance storage pattern 231 includes a bottom part 234 located on a part of the upper surface of the lower electrode 212 and a side wall part 236 located on the side surface 224 of the trench 222. For example, the variable resistance storage pattern 231 is formed of the same phase change material as the GST compound.
Subsequently, referring to FIG. 8, the protective film pattern 241 covers the exposed surface of the variable resistance storage pattern 231 in the trench 222. The space in the trench 222 is filled with the insulating film 250.
As shown in FIG. 8, the third interlayer insulating film 270 (or a plurality of films) is located on the second interlayer insulating film 220. The upper electrode 261 is located in the third interlayer insulating layer 270 and is in electrical contact with the variable resistance storage pattern 231. For example, the upper electrode 261 includes a barrier film 263 on the lower surface thereof.
Finally, a plurality of bit lines BL are positioned on or in the third interlayer insulating layer 270, and a contact plug 271 extends between the bit line BL and the upper electrode 261. The electrode 261 is electrically connected.
9A to 9F are cross-sectional views for explaining an embodiment of a method for manufacturing the variable resistance memory element of FIGS.
As shown in FIG. 9A, a first interlayer insulating film 210 is formed on the surface of the lower film 201. For example, the lower layer 201 is a semiconductor substrate, an SOI substrate, or the like. Although not shown in FIG. 9A, the lower layer 201 includes a word line (a switching element electrically connected to the diode, for example, a diode or a transistor, not shown in FIG. 9A). For example, the first interlayer insulating layer 210 may be formed of SiO 2 or other materials may be used instead. For example, the first interlayer insulating film may be formed by BSG (borosilicate glass), PSB (phosphosilicate glass), BPSG (borophosphosilicate glass), and PE-TEOS (plasma-enhanced tetraethylate). it can.
As shown in FIG. 9A, the lower electrode 212 is formed in the first interlayer insulating layer 210. For example, the lower electrode 212 is formed by etching a contact hole in the interlayer insulating film 210, then depositing a material film of the lower electrode 212, and then forming the material film to define the lower electrode 212. Can be formed by planarization (eg, CMP). The shape of the lower electrode 212 is not limited. Although not limited to the example, the lower electrode 212 may have a circular or quadrangular cylindrical shape, or the lower electrode 212 may have a ring-shaped cross-section. As described above, the lower electrode 212 may be formed of a multilayer film of another material. For example, the material constituting the lower electrode 212 may be Cu, Ti, TiSiX, TiN, TiON, TiAlN, TiAlON, TiSiN, TiBN, W, WSiX, WN, WON, WSiN, WBN, WCN, One or more of Ta, TaSiX, TaN, TaON, TaAlN, TaSiN, TaCN, Mo, MoN, MoSiN, MoAlN, NbN, ZrSiN, ZrAlN, Ru, CoSiX, NiSiX, and conductive carbon can be included.
Referring to FIG. 9B, a second interlayer insulating layer 220 is deposited on the second interlayer insulating layer 210. For example, the second interlayer insulating layer 220 is formed of SiO2, BSG, PSB, PBSG, PE-TEOS, or the like. An etch stop layer 221 is formed on the second interlayer insulating layer 220 and patterned. For example, the etch stop layer 221 includes SiN, SiON, HfO, and AlO. The etch stop layer 221 has a high etch selectivity with respect to the second interlayer insulating layer 220 and is used as an etching mask for etching the trench 222 in the second interlayer insulating layer 220. The trench 122 is etched and its bottom surface 223 exposes at least a portion of the upper surface of the lower electrode 212. As shown in the drawing, the side surface 224 of the trench 222 is formed to be inclined, and the width of the trench 222 may be wider than the bottom surface 223 of the upper opening.
Next, referring to FIG. 9C, a variable resistance material film 230 is deposited along the surface of the structure shown in FIG. 9B. That is, the variable resistance material layer 230 is deposited to conformally cover the etch stop layer 221, the side surface 224 of the trench 222, and the bottom surface 223 of the trench 222. For example, the variable resistance material layer 230 may be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). For example, the variable resistance material layer 230 may be formed of a phase change material. Suitable phase change material films include SeSbTe, GeTeAs, SnTeSn, GeTe, SbTe, SetSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe. For example, the variable resistance material layer 230 may be doped with carbon, nitrogen, silicon, and / or oxygen.
Subsequently, referring to FIG. 9C, a passivation layer 240 may be deposited on the variable resistance material layer 230. For example, the passivation layer 240 is deposited according to the topology of the variable resistance material layer 230 and does not completely fill the trench 222. For example, the depth of the passivation layer 240 may be less than half the width of the trench 222 in order to prevent the trench 222 from being filled.
In operation of the manufactured variable resistance memory device, the protective layer 240 may function to prevent heat loss of the variable resistance layer. The protective film 240 functions to protect the variable resistance material film 230 from process damage received in a series of manufacturing steps. For example, the passivation layer 240 may protect the variable resistance material layer 230 from an etching state and / or oxygen exposure (eg, oxygen diffusion) during a series of processes.
For example, the protective film 240 includes a silicon nitride film, a silicon carbon nitride film, a carbon nitride film, and / or carbon. For example, the passivation layer 240 is a silicon nitride layer formed using PC-CVD (plasma enhanced CVD) at a temperature of about 380 to 400 ° C. As described above, the variable resistance material layer 230 may be doped with carbon, nitrogen, silicon and / or oxygen. In this case, the volatilization temperature of the doped material can be higher than the temperature of the undoped material.
Next, referring to FIG. 9D, a gap left in the trench 222 is filled with the insulating material 250 by the passivation layer pattern 241. For example, this can be performed by depositing an insulating material followed by a planarization process. For example, the insulating material to be deposited may be HDP (high density plasma) oxide, PE-TEOS (plasma-enhanced tetraethylosilicate), BPSG (borophosphosilicate glass), USG (undopsole, GSG). ), Silicon oxides such as HSQ (hydrosilsesquioxane) and SOG (spin on glass). For example, the planarization process may be a CMP (Chemical Mechanical Polishing) or an etch back process. In other cases, the etch stop layer 221 may be used as a removal stop layer. During the planarization process, as shown in FIG. 9D, the protective film pattern 241 and the variable resistance material film 231 on the etch stop layer 221 are removed to define a structure having a flat upper surface. The variable resistance material film pattern 231 of FIG. 6 is formed by such a method.
Although not shown in the drawing, a plasma treatment using an inert gas may be performed after the planarization process. Although not limited thereto, the inert gas includes Ar, He, Ne, Kr, and / or Xe. A sputter process is performed after the planarization process, so that the damaged or oxidized portion of the variable resistance film pattern 231 is removed.
Next, referring to FIG. 9E, the barrier material film and the electrode material film are deposited and patterned using a known technique (eg, deposition, masking, and etching), so that the barrier film 263 and the upper electrode 261 are formed. Each is defined. For example, the material of the upper electrode 261 is Ti, TiSiX, TiN, TiON, TiW, TiAlN, TiAlON, TiSiN, TiBN, W, WSiX, WN, WON, WSiN, WBN, WCN, Ta, TaSiX, TaN, TaON, TaAlN, TaSiN, TaCN, Mo, MoN, MoSiN, MoAlN, NbN, ZrSiN, ZrAlN, Ru, CoSi, NiSi, conductive carbon, and copper.
The barrier film 263 can function as an adhesive film and can prevent diffusion between the upper electrode 261 and a plurality of lower films such as the lower variable resistance film pattern 231. For example, the barrier film 263 includes TiN, TiW, TiCN, TiAlN, TiSiC, TaN, TaSiN, WN, MoN, and CN.
When the plurality of variable resistance film patterns 231 include a phase change material such as a GST (or chalcogenide) material, the barrier film 263 may be the same as the plurality of variable resistance film patterns 231 or other It can be formed to include a phase change material. As described above, this may have an advantage that damage that may occur in the plurality of variable resistance film patterns 231 can be compensated while the insulating film 250 is planarized. For example, the barrier layer 263 may include a structure in which a GST material layer and a conductive layer are stacked.
Next, referring to FIG. 9F, a third interlayer insulating layer 270 is deposited, a plurality of contact plugs 271 are formed in the interlayer insulating layer 270, and a plurality of conductive bit lines BL are connected to the plurality of contact plugs 271. Formed in electrical contact. Techniques and materials well known in the industry can be used to form such devices. As shown in FIGS. 6 and 7, the plurality of bit lines BL extend long in a direction parallel to the variable resistance film pattern 231.
Various examples of substantial application of the variable resistance memory device will be described. Such applications are collectively referred to herein as memory systems.
FIG. 10 illustrates an apparatus including a variable resistance memory device according to an embodiment of the present invention. As shown in the drawing, the apparatus includes a memory 510 and a memory controller 520. The memory 510 may include the variable resistance memory device described above. The memory controller 520 can supply an input signal for controlling the operation of the memory. For example, the memory controller 520 may supply a command language and an address signal. The memory controller 520 can control the memory 510 based on an input control signal.
FIG. 11 illustrates an apparatus including a variable resistance memory device according to an embodiment of the present invention. As shown, the apparatus includes a memory 510 coupled to an interface 515. The memory 510 may include the variable resistance memory device described above. For example, the interface 515 can supply a command language and an address signal. The interface 515 can control the memory 510 based on an input control signal generated from the outside.
FIG. 12 illustrates an apparatus including a variable resistance memory device according to an embodiment of the present invention. As shown in the drawing, the apparatus is similar to the apparatus of FIG. 10 except that the memory 510 and the memory controller 520 are integrated within a memory card 530. For example, the memory card 530 may be a memory card that satisfies a standard for data compatibility of an electronic device (eg, a digital camera, a PC, or the like). The memory controller 520 can control the memory 510 based on a control signal received by the memory card from another element (for example, an external device).
FIG. 13 illustrates a mobile device 6000 including a variable resistance memory device according to an embodiment of the present invention. The mobile device 6000 may be MP3, video player, video, audio player, or the like. As shown in the drawing, the mobile device 6000 includes the memory 510 and a memory controller 520. The memory 510 includes the variable resistance memory device described above. The mobile device 6000 may include an encoder and decoder 610 (EDC), a presentation configuration 620, and an interface 630. Data such as video or audio can be exchanged between the memory 510 and the EDC 610 via the memory controller 520. As indicated by the dotted lines, data can be exchanged immediately between the memory 510 and the EDC 610. The EDC 610 can encode data for storage in the memory 510. For example, the EDC 610 can encode audio data into an MP3 file, and can store the encoded MP3 file in the memory 510. In contrast, the EDC 610 may encode MPEG video data (eg, MPEG3, MPEG4, etc.) and store the encoded video data in the memory 510. The EDC 610 may include a plurality of encoders that encode other data types according to other data formats. For example, the EDC 610 may include an MP3 encoder for audio data and an MPEG encoder for video data. The EDC 610 can decode output data from the memory 510. For example, the EDC 610 can decode the audio data from the memory 510 into an MP3 file. The EDC 610 can output video data from the memory 510 and decode it into an MPEG file. The EDC 610 may include a plurality of decoders that decode other data types according to other data formats. For example, already encoded data can be transmitted to the EDC 610, decoded, and transmitted to the memory controller 520 and / or the memory 510. The EDC 610 can be received to encode data via the interface 630, or can receive already encoded data. The interface 630 can follow well-known standards (eg, USB, firewire, etc.). Data supplied from the memory 510 may be output through the interface 630. The presentation structure 620 can represent data such as decoded data that can be recognized by a user decoded by the memory 510 and / or the EDC 610. For example, the presentation configuration 620 may include a display screen for displaying video data and a speaker terminal (Jack) for outputting audio data.
FIG. 14 illustrates an apparatus including a variable resistance memory device according to an embodiment of the present invention. As shown in the drawing, the memory 510 may be connected to a host system 7000 (host system). The memory 510 may include the variable resistance memory device described above. The host system 7000 may be the same processing system as a PC, a digital camera, or the like. The memory 510 may be a separable storage medium such as a memory card, a USB memory, or a solid-state driver (SSD). The host system 7000 can supply input signals such as a command language and an address signal that the memory 510 controls operations.
FIG. 15 illustrates an apparatus including a variable resistance memory device according to an embodiment of the present invention. For example, the host system 7000 can be connected to the memory card 530. The host system 7000 can supply a control signal for operating the memory controller 520 that controls the operation of the memory 510 to the memory card 530.
FIG. 16 illustrates an apparatus including a variable resistance memory device according to an embodiment of the present invention. As described above, the memory 510 can be connected to the central processing unit 810 (CPU) of the computer system 8000. For example, the computer system 8000 is a PC, a PDA (personal data assistant), or the like. The memory 510 may be connected to the CPU 810 through a bus.
FIG. 17 illustrates an apparatus including a variable resistance memory device according to an embodiment of the present invention. As shown in FIG. 17, the device 9000 may include a controller 910, a keyboard, a display, or a similar input / output device 920, a memory 930, and an interface 940. Each component constituting the apparatus can be connected to each other through a bus 850. The controller 910 may include at least one of a microprocessor, a digital processor, a microcontroller, or a processor. The memory 930 may store data and / or a command language executed by the controller 910. The interface 940 can be used to transmit data to other systems (eg, a communication network or a communication network). The device 9000 can be a mobile system such as a PDA, portable computer, web tablet, wireless phone, mobile phone, digital music player, memory card, or other system that transmits and receives information.
Although embodiments are disclosed herein and specific terms are used, this is general and is intended to be interpreted in a descriptive sense and is not intended to be limiting. Accordingly, changes in form and detail may be made by one skilled in the art according to the following claims without departing from the scope and spirit of the invention.
101 Substrate 110 First interlayer insulating film 112 Lower electrode 120 Second interlayer insulating film 121 Etching stop film 122 Trench 131, 132 First and second variable resistance storage patterns 134 Bottom 136 Side walls 141, 142 Protective film pattern 150 Insulating film 161, 162 Upper electrode 163 Barrier film 170 Third interlayer insulating film
At least one lower electrode;
A first insulating film including a trench exposing the at least one lower electrode;
A variable resistance material layer electrically connected to the at least one lower electrode and including a first part and a second part, respectively, located on opposite sides of the trench;
A protective film covering the variable resistance material film in the trench;
A variable resistance memory element including a second insulating film located in the trench and covering a protective film in the trench.
The variable resistance memory device of claim 1, wherein the variable resistance material film is a phase change material film.
The at least one lower electrode includes a first lower electrode and a second lower electrode;
A first portion and a second portion of the variable resistance material layer are electrically insulated from each other and electrically connected to the first lower electrode and the second lower electrode;
The variable resistance memory device of claim 1, wherein the first portion and the second portion of the variable resistance material film are storage elements of the first memory cell and the second memory cell, respectively.
4. The variable resistance memory device of claim 3, wherein the variable resistance material film is a phase change material film, and the first memory cell and the second memory cell are phase change memory cells.
The variable resistance memory device of claim 3, wherein each of the first portion and the second portion of the variable resistance material film has a substantially L-shaped cross section.
The first portion and the second portion of the variable resistance material film extend long in the trench and intersect with a plurality of first and second lower electrodes to form a plurality of first and second memory cells. The variable resistance memory element according to claim 3.
The variable resistance memory device according to claim 1, wherein the protective film includes at least one of silicon nitride, silicon carbon nitride, carbon nitride, and carbon.
The variable resistance memory device of claim 3, wherein the protective film includes first and second protective films that are spaced apart and cover the first and second portions of the variable resistance material film, respectively.
The variable resistance memory device of claim 8, wherein the first and second protective films include at least one of silicon nitride, silicon carbon nitride, carbon nitride, and carbon.
The at least one lower electrode comprises a single electrode;
The variable resistance memory device of claim 1, wherein the variable resistance material film is a storage element of the phase change memory cell in which the first and second portions are in continuous contact.
The variable resistance memory device of claim 1, further comprising at least one upper electrode in contact with the first and second portions of the variable resistance material film.
The variable resistance memory device according to claim 11, wherein the upper electrode includes a barrier film.
The variable resistance memory device of claim 12, wherein the variable resistance material layer includes a phase change material, and the barrier layer includes a phase change material.
A plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected to the word lines and the bit lines;
Each memory cell
A variable resistance material layer located on opposite sides of a trench formed in a material layer interposed between the plurality of word lines and the plurality of bit lines;
A variable resistance memory element including an insulating film located in the trench and covering a protective film in the trench.
The variable resistance memory device of claim 14, wherein the variable resistance material film is a phase change material film.
First and second lower electrodes electrically connected to each memory cell and word line;
The variable resistance material layer is provided on opposite side surfaces of the trench, electrically insulated from each other, and electrically connected to the first and second lower electrodes, respectively. Including
The variable resistance memory device of claim 15, wherein the first and second portions of the variable resistance material film are storage elements of the first and second memory cells, respectively.
The variable resistance memory device of claim 16, wherein each of the first and second portions of the variable resistance material film has a substantially L-shaped cross section.
The first and second portions of the variable resistance material film extend long in the trench and intersect with the first and second lower electrodes, respectively, to form a plurality of first and second memory cells, respectively. Item 18. The variable resistance memory element according to Item 17.
15. A storage system comprising the variable resistance memory element of claim 14.
JP2010004343A 2009-01-09 2010-01-12 Resistance variable memory device and method of fabricating the same Granted JP2010161376A (en)
KR1020090001975A KR20100082604A (en) 2009-01-09 2009-01-09 Variable resistive memory device and method of forming thereof
US12/684,140 US20100176365A1 (en) 2009-01-09 2010-01-08 Resistance variable memory devices and methods of fabricating the same
JP2010161376A true JP2010161376A (en) 2010-07-22
ID=42318402
JP2010004343A Granted JP2010161376A (en) 2009-01-09 2010-01-12 Resistance variable memory device and method of fabricating the same
US (1) US20100176365A1 (en)
JP (1) JP2010161376A (en)
KR (1) KR20100082604A (en)
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2009-01-09 KR KR1020090001975A patent/KR20100082604A/en not_active Application Discontinuation
2010-01-08 US US12/684,140 patent/US20100176365A1/en not_active Abandoned
2010-01-12 JP JP2010004343A patent/JP2010161376A/en active Granted
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2013-07-26 A761 Written withdrawal of application