Source: https://patents.google.com/patent/US7279794?oq=flatulence
Timestamp: 2018-02-22 17:14:33
Document Index: 107434788

Matched Legal Cases: ['Application No. 2003', 'art 34', 'art 34', 'art 34', 'art 34', 'art 34', 'art 34', 'art 36', 'art 34', 'art 38', 'art 36', 'art 34', 'art 36', 'art 38', 'art 34', 'art 34', 'art 34', 'art 34']

US7279794B2 - Semiconductor device and electronic device, and methods for manufacturing thereof - Google Patents
US7279794B2
US7279794B2 US11009993 US999304A US7279794B2 US 7279794 B2 US7279794 B2 US 7279794B2 US 11009993 US11009993 US 11009993 US 999304 A US999304 A US 999304A US 7279794 B2 US7279794 B2 US 7279794B2
US11009993
US20050127493A1 (en )
A semiconductor device is provided including a substrate containing a wire pattern having a plurality of leads and a semiconductor chip mounted on the substrate in a manner that an electrode faces the wire pattern. The electrodes are arranged to be classified into a plurality of first groups respectively lined along a plurality of paralleling first straight lines and into a plurality of second groups respectively lined along a plurality of second straight lines extending in a direction so as to intersect with the first straight lines. Each lead includes a connecting part facing one electrode, an extension part extending along the first straight line from the connecting part, and a draw-out part that is drawn from the extension part so as to intersect with the first straight line.
This application claims priority to Japanese Patent Application No. 2003-414830 filed Dec. 12, 2003 which is hereby expressly incorporated by reference herein in its entirety.
(1) The semiconductor device of the present invention includes a substrate having a wire pattern containing a plurality of leads and a semiconductor chip having a plurality of electrodes which are mounted on the substrate so as to face the wire pattern, wherein the electrodes are arranged to be classified into a plurality of first groups respectively lined along a plurality of paralleling first straight lines which extend along one side of the semiconductor chip and into a plurality of second groups respectively lined along a plurality of second straight lines which extend in a direction so as to intersect with the first straight lines, and wherein each lead contains a connecting part facing any one of the electrodes, an extension part extending from the connecting part along any one of the first straight lines, and a draw-out part which is drawn from the extension part and extends in a direction so as to intersect with the first straight line.
FIG. 1 is a diagram illustrating a semiconductor device of an embodiment applying the present invention.
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.
The substrate 20 includes the wire pattern 30 containing a plurality of leads 32. The wire pattern 30 may be formed by laminating, or by using a single layer of, any of copper (Cu), chromium (Cr), titan (Ti), nickel (Ni), titan-tungsten (Ti—W), gold (Au), aluminum (Al), nickel vanadium (NiV), and tungsten (W). If a multilayered substrate is prepared for use as the substrate 20, the wire pattern 30 may be mounted between each of the layers. Further, if a glass substrate is used as the substrate 20, the wire pattern 30 may be formed with a metal layer, or a metal-compound layer, of indium tin oxide (ITO), Cr, or Al, for example, or with a mixed layer of such a metal layer and a metal-compound layer. The method for forming the wire pattern 30 is not particularly designated. The wire pattern 30 may be formed, for example, by sputtering or by an additive process in which the wire pattern 30 is formed by electroless plating. Also, the wire pattern 30 may be plated with solder, tin, gold, or nickel, for example.
As shown in FIG. 3, the lead 32 includes the connecting part 34. The connecting part 34 is the part that faces the electrode 12. As shown in FIG. 4, the lead 32 (the wire pattern 30) and the electrode 12 are electrically connected by having the electrode 12 and the connecting part 34 to face each other. The electrical connecting of the electrode 12 and the connecting part 34 may be conducted by having them in contact with one another as shown in FIG. 4. Alternatively, the electrical connecting thereof may be carried out by intervening a conductive particle between the electrode 12 and the connecting part 34 (not shown). Alternatively, for the electrical connecting of the electrode 12 and the connecting part 34, an alloy junction (e.g., an Au—Au or an Au—Sn junction) may be used. As shown in FIG. 3, the lead 32 includes the extension part 36 which extends along the first straight line 110 from the connecting part 34. As shown in FIG. 3, the lead 32 further includes a draw-out part 38 that is drawn from the extension part 36 and extends in a direction so as to intersect with first straight line 110. Additionally, the lead 32 may be formed by integrating the connecting part 34, the extension part 36, and the draw-out part 38 into one form.
The present process includes aligning the semiconductor chip 10 with the substrate 20 so that the first straight line 110 and the third straight line 130 lie in parallel with each other and so that the electrode 12 faces the connecting part 34 (see FIG. 2). The electrode 12 of one first group 310 may be facing the connecting part 34 of any one of the third groups 330. Then, the electrode 12 and the connecting part 34 are electrically connected. To electrically connect the electrode 12 with the connecting part 34, any well-known method such as an insulating resin junction (e.g., a junction using an NCP or an NCF), an anisotropic conductive-material junction (e.g., a junction using an ACP or an ACF), a metal junction (e.g., an Au—Au or an Au—Sn junction), or a junction by soldering may be employed. Thus, the electrode 12 and the wire pattern 30 may be electrically connected.
Embodiments of the present invention are not limited to the above-described embodiments but can have various alternatives. Hereafter, alternative examples of the semiconductor device of the embodiments applying the present invention will be described. Further, in the following alternative examples, the descriptions already given above shall be employed whenever applicable.
Embodiments of the present invention are not limited to the above-described embodiments but can have various alternatives. Hereafter, alternative examples of the electronic device of the embodiments applying the present invention will be described. Further, in the following alternative examples, the descriptions already given above shall be employed whenever applicable.
US11009993 2003-12-12 2004-12-10 Semiconductor device and electronic device, and methods for manufacturing thereof Active US7279794B2 (en)
JP2003414830A JP3736639B2 (en) 2003-12-12 2003-12-12 A semiconductor device and an electronic device and a method for their preparation
JP2003-414830 2003-12-12
US20050127493A1 true US20050127493A1 (en) 2005-06-16
US7279794B2 true US7279794B2 (en) 2007-10-09
ID=34650547
US11009993 Active US7279794B2 (en) 2003-12-12 2004-12-10 Semiconductor device and electronic device, and methods for manufacturing thereof
US (1) US7279794B2 (en)
JP (1) JP3736639B2 (en)
CN (1) CN100364086C (en)
KR101692956B1 (en) 2010-09-20 2017-01-04 삼성전자 주식회사 Tape Package
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JP2000286291A (en) * 1999-03-30 2000-10-13 Kyocera Corp Mounting structure for semiconductor
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JP3537699B2 (en) 1999-03-30 2004-06-14 京セラ株式会社 Mounting structure of the semiconductor element
JP3736639B2 (en) 2006-01-18 grant
US20050127493A1 (en) 2005-06-16 application
CN100364086C (en) 2008-01-23 grant
JP2005175267A (en) 2005-06-30 application
CN1627513A (en) 2005-06-15 application
JP2002083897A (en) 2002-03-22 Semiconductor device and manufacturing method thereof and, circuit board and electronic apparatus
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