Source: http://www.google.com/patents/US20080312726?ie=ISO-8859-1
Timestamp: 2015-03-07 00:31:58
Document Index: 624741630

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US20080312726 - Implantable Hermetically Sealed Structures - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsImplantable hermetically sealed structures and methods for making the same are provided. Also provided are devices, systems and kits including the hermetically sealed structures, as well as methods of using such devices and systems....http://www.google.com/patents/US20080312726?utm_source=gb-gplus-sharePatent US20080312726 - Implantable Hermetically Sealed StructuresAdvanced Patent SearchPublication numberUS20080312726 A1Publication typeApplicationApplication numberUS 11/794,016PCT numberPCT/US2005/046815Publication dateDec 18, 2008Filing dateDec 22, 2005Priority dateDec 22, 2004Also published asEP1827583A1, EP1827583A4, EP1827583B1, US8195308, WO2006069323A1Publication number11794016, 794016, PCT/2005/46815, PCT/US/2005/046815, PCT/US/2005/46815, PCT/US/5/046815, PCT/US/5/46815, PCT/US2005/046815, PCT/US2005/46815, PCT/US2005046815, PCT/US200546815, PCT/US5/046815, PCT/US5/46815, PCT/US5046815, PCT/US546815, US 2008/0312726 A1, US 2008/312726 A1, US 20080312726 A1, US 20080312726A1, US 2008312726 A1, US 2008312726A1, US-A1-20080312726, US-A1-2008312726, US2008/0312726A1, US2008/312726A1, US20080312726 A1, US20080312726A1, US2008312726 A1, US2008312726A1InventorsJeremy Frank, Vladimir Gelfandbein, Marc Jensen, Mark Zdeblick, Benedict J. CostelloOriginal AssigneeProteus Biomedical, Inc.Export CitationBiBTeX, EndNote, RefManReferenced by (10), Classifications (10), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetImplantable Hermetically Sealed Structures
US 20080312726 A1Abstract
an in vivo corrosion resistant holder having at least one conductive feedthrough; and a sealing layer; wherein said sealing layer and holder are configured to define a hermetically sealed volume. 9. The implantable hermetically sealed structure according to claim 8, wherein said conductive feedthrough is a metal.
an in vivo corrosion resistant integrated circuit holder having at least one conductive feedthrough; at least one integrated circuit present in said holder and electrically coupled to said at least one feedthrough; and a sealing layer; wherein said sealing layer and holder are configured to define a hermetically sealed volume comprising said at least one integrated circuit. 94. The implantable hermetically sealed structure according to claim 93, wherein said integrated circuit is part of an effector.
positioning an effector through an opening in an in vivo corrosion resistant holder; and fabricating a sealing layer over said opening to seal said effector in said holder in a hermetically sealed volume; wherein said method further comprises producing one or more conductive feedthroughs in said holder that is electrically coupled to said effector. 118. A method according to claim 117, wherein said holder comprises two or more conductive feedthroughs insulated from each other.
implanting an implantable medical device according to claim 135 into a subject; and using said effector of said implanted medical device. 150. The method according to claim 149, wherein said effector is a sensor and said using comprises obtaining signals from said sensor.
a hermetically sealed structure according to claim 1; and a control unit. 155. The system according to claim 154, wherein said structure and control unit are electrically coupled by an elongated conductive member.
a hermetically sealed structure according to claim 1; and a control unit. 162. The kit according to claim 160, wherein said kit further includes an elongated conductive member.
Pursuant to 35 U.S.C. � 119 (e), this application claims priority to the filing dates of: U.S. Provisional Patent Application Ser. No. 60/638,692 filed Dec. 22, 2004; U.S. Provisional Patent Application Ser. No. 60/655,609 filed Feb. 22, 2005; U.S. Provisional Patent Application Ser. No. 60/681,919 filed May 16, 2005; and U.S. Provisional Patent Application Ser. No. 60/697,789 filed Jul. 8, 2005; the disclosures of which are herein incorporated by reference.
In certain embodiments, the hermetically sealed structure includes a hermetically sealed volume that houses one or more effectors. The term �effector� is generally used herein to refer to sensors, activators, sensor/activators, actuators (e.g., electromechanical or electrical actuators) or any other device that may be used to perform a desired function. In some embodiments, for example, effectors include a transducer and a processor (e.g., in the form of an integrated circuit (digital or analog). As such, embodiments of the invention include ones where the effector comprises an integrated circuit. The term �integrated circuit� (IC) is used herein to refer to a tiny complex of electronic components and their connections that is produced in or on a small slice of material, i.e., chip, such as a silicon chip. In certain embodiments, the IC is an IC as described in PCT Patent Application Serial No. PCT/US2005/______ titled �Methods And Apparatus For Tissue Activation And Monitoring� filed on Sep. 1, 2005, the disclosure of which is herein incorporated by reference.
Representative fabrication protocols for producing various sensor structures described above are now discussed in greater detail. FIGS. 4A to 4M provide a flow diagram of a processing protocol according to an embodiment of the invention that can be employed to manufacture a hermetically sealed structure, which process may be referred to as a �shadow mask� process. In FIG. 4A, initial structure 400 includes base layer 405 (e.g., silicon, silicon carbide, etc.) which has mask layer 410 present on a first surface 408. Following removal of exposed material, e.g., via plasma etching techniques, shallow recesses 404 (e.g., in the form of trenches) are produced on first surface 408 as shown in FIG. 4B. These recesses will ultimately become the conductive feedthroughs, as shown below. Following removal of mask layer 410, structure 400 includes recesses 404 present on surface 408, as shown in FIG. 4C. Next, a shadow mask 412 is placed on the surface 408 of base layer 405 as shown in FIG. 4D. Shadow mask 412 may be produced using any convenient protocol, e.g., by reactive ion etching, photoetching or electroforming, etc. A conductive layer 417, e.g., of a metal, is then produced across the upper surface 408 and mask 412 of structure 400, as shown in FIG. 4E, e.g., via deposition, plating, etc. The conductive layer 417 completely fills recesses 404 on surface 408. Next, the mask layer 412 is planarized, as shown in FIG. 4F, leaving conductive elements 420 present on surface 408 of base 405. In FIG. 4G, mask layer 425 is produced on bottom surface 422. Next, material is removed from bottom surface 422 as shown in FIG. 4H. Following removal of backing layer 425, structure 400 may be considered a microfabricated chip package that includes: an array of feedthroughs fabricated, e.g., using planar processing techniques, and an array of cavities, e.g., fabricated using planar processing techniques. This step results in the production of holders 430 having side walls 431 and bottoms 432, where the bottoms 432 include conductive elements 420 which are now conductive feedthroughs, e.g., of a metal or a doped semiconductor material. FIG. 41 shows placement of integrated circuits 440 into holders 430, where the integrated circuit traces 441 are electrically isolated from each other by insulative material 443. Also shown are solders 442 which provide for electrical connection between traces 441 and conductive elements (i.e., feedthroughs) 420. Next, insulative material 450, e.g., epoxy, is introduced into holders 430 to fill any gaps between the integrated circuit and holder walls/bottom, as shown in FIG. 4J. In FIG. 4K, surface 422 has been planarized (i.e., lapped) to produce new planar surface 460 that is free of surface irregularities. FIG. 4L shows the production of sealing layer 470 on planar surface 460. In this figure, a structure is shown that includes an array of holders each with integrated feedthroughs, where each chip holder contains an integrated circuit, an insulative material fills the space between the integrated circuit and the walls of the holders. The structure is further characterized in that the insulative material, integrated circuits and array of chip holders has been planarized and a corrosion resistant material that covers the planarized array of chip holders is present. In a final step, structure 400 has been cleaved to produce hermetically sealed integrated circuits 481 and 482, as shown in FIG. 4M.
The subject hermetically sealed structures find use in any medical device and system in which it is desired to implant for an extended period of time a hermetically sealed structure. Devices and systems in which the subject hermetically sealed structures find use include, but are not limited to, those described in: WO 2004/066817 titled �Methods And Systems For Measuring Cardiac Parameters�; WO 2004/066814 titled �Method And System For Remote Hemodynamic Monitoring�; WO 2005/058133 titled �Implantable Pressure Sensors�; WO 2004/052182 titled �Monitoring And Treating Hemodynamic Parameters�; WO 2004/067081 titled �Methods And Apparatus For Enhancing Cardiac Pacing�; U.S. Provisional Patent Application 60/638,928 entitled �Methods and Systems for Programming and Controlling a Cardiac Pacing Device� filed Dec. 23, 2004; U.S. Provisional Patent Application No. 60/658,445 titled �Fiberoptic Cardiac Wall Motion Timer� filed Mar. 3, 2005; U.S. Provisional Patent Application No. 60,667,759 titled �Cardiac Motion Detection Using Fiberoptic Strain Gauges,� filed Mar. 31, 2005; U.S. Provisional Patent Application No. 60/679,625 titled �de Minimus Control Circuit for Cardiac pacing and Signal Collection,� filed May 9, 2005; U.S. Provisional Patent Application No. 60/706,641 titled �Deployable Epicardial Electrode and Sensor Array,� filed Aug. 8, 2005; U.S. Provisional Patent Application No. 60/705,900 titled �Electrical Tomography� filed Aug. 5, 2005; U.S. Provisional Patent Application No. 60/______ (attorney docket no. PRO-P37) titled �Methods and Apparatus for Tissue Activation and Monitoring� filed Aug. 12, 2005; U.S. Provisional Patent Application No. 60/707,913 titled �Measuring Conduction Velocity Using One or More Satellite Devices,� filed Aug. 12, 2005. These applications are herein incorporated into the present application by reference in their entirety.
In FIG. 7 above, one or more of the electrodes of the system depicted in FIG. 7 is coupled to a hermetically sealed integrated circuit, as depicted in FIG. 8. FIG. 8 shows the configuration of electrodes around a hermetically sealed integrated circuit according to an embodiment of the invention. One of four electrodes 1 is distributed around the hermetically sealed IC 2 in a circumferential pattern. Electrode 1 is shown as a solid surface but it may have a finer scale pattern formed into the surface that improves the flexibility of the electrode. IC chip 2 is hermetically sealed and provides a multiplexed connection to conductors in the lead (not shown in this figure). Optionally, top cap 3 is bonded to the integrated circuit. Cap 3 is a component that helps support the electrode to integrated circuit connection. Cap 3 may contain additional circuits or sensors. This assembly would be incorporated into a flexible polymeric material to form the body of the device. The device may be round. It may also be some other shape best suited to the particular location in the body where is would be used. Additional electrode structures in which the subject hermetically sealed integrated circuits find use include, but are not limited to: U.S. Provisional Patent Application Ser. No. 60/638,692 filed Dec. 22, 2004; U.S. Provisional Patent Application Ser. No. 60/655,609 filed Feb. 22, 2005; U.S. Provisional Patent Application Ser. No. 60/655,609 filed Feb. 22, 2005; U.S. Provisional Patent Application Ser. No. 60/______ filed Dec. 15, 2005 titled �Fatigue Resistant IC Chip Connection,� and PCT application serial no. PCT/US2005/______ filed on even date herewith and titled �IMPLANTABLE ADDRESSABLE SEGMENTED ELECTRODES�; the disclosures of which are herein incorporated by reference.
Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8125058Sep 29, 2009Feb 28, 2012Medtronic, Inc.Faraday cage for circuitry using substratesUS8343806Mar 5, 2009Jan 1, 2013Raytheon CompanyHermetic packaging of integrated circuit componentsUS8509899Jan 18, 2011Aug 13, 2013Medtronic, Inc.Multi-electrode implantable systems and assemblies thereofUS8513620Oct 12, 2010Aug 20, 2013Inotera Memories, Inc.Auxiliary stage and method of utilizing auxiliary stageUS8639341Aug 9, 2013Jan 28, 2014Medtronic, Inc.Multi-electrode implantable systems and assemblies thereforUS8688223Oct 26, 2010Apr 1, 2014John D. WahlstrandImplantable medical device impedance measurement module for communication with one or more lead-borne devicesUS8803314Dec 14, 2012Aug 12, 2014Raytheon CompanyHermetic packaging of integrated circuit componentsUS20140130349 *Jan 23, 2014May 15, 2014Advanced Neuromodulation Systems, Inc.Medical leads with segmented electrodes and methods of fabrication thereofWO2010101858A2 *Mar 2, 2010Sep 10, 2010Raytheon CompanyHermetic packaging of integrated circuit componentsWO2010148287A1 *Jun 18, 2010Dec 23, 2010Medtronic, Inc.Medical device encapsulated within bonded dies* Cited by examinerClassifications U.S. Classification607/122, 607/116, 607/119International ClassificationA61N1/05Cooperative ClassificationA61N1/05, A61N1/37205, A61N1/3756, A61N1/375European ClassificationA61N1/05, A61N1/375Legal EventsDateCodeEventDescriptionNov 2, 2012ASAssignmentFree format text: CHANGE OF NAME;ASSIGNOR:PROTEUS BIOMEDICAL, INC.;REEL/FRAME:029228/0436Effective date: 20120705Owner name: PROTEUS DIGITAL HEALTH, INC., CALIFORNIAMar 4, 2008ASAssignmentOwner name: PROTEUS BIOMEDICAL, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FRANK, JEREMY;GELFANDBEIN, VLADIMIER;JENSEN, MARC;AND OTHERS;REEL/FRAME:020636/0929;SIGNING DATES FROM 20080225 TO 20080303Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FRANK, JEREMY;GELFANDBEIN, VLADIMIER;JENSEN, MARC;AND OTHERS;SIGNING DATES FROM 20080225 TO 20080303;REEL/FRAME:020636/0929RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services