Source: http://www.google.com/patents/US20040046175?dq=6008737
Timestamp: 2017-09-24 15:04:46
Document Index: 267997576

Matched Legal Cases: ['art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2', 'art 3', 'art 4', 'art 1', 'art 2', 'art 1', 'art 2', 'art 3', 'art 4', 'art 1', 'art 2', 'art 1', 'art 2', 'art 3', 'art 4']

Patent US20040046175 - Thin film transistor matrix device and method for fabricating the same - Google Patents
A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin...http://www.google.com/patents/US20040046175?utm_source=gb-gplus-sharePatent US20040046175 - Thin film transistor matrix device and method for fabricating the same
Publication number US20040046175 A1
Application number US 10/660,053
Also published as US5742074, US6406946, US6767754, US7075108, US7575960, US7947982, US7947983, US8258513, US8592816, US20020028540, US20020084460, US20060163579, US20090256153, US20100117087, US20100214202, US20130015451
Publication number 10660053, 660053, US 2004/0046175 A1, US 2004/046175 A1, US 20040046175 A1, US 20040046175A1, US 2004046175 A1, US 2004046175A1, US-A1-20040046175, US-A1-2004046175, US2004/0046175A1, US2004/046175A1, US20040046175 A1, US20040046175A1, US2004046175 A1, US2004046175A1
Inventors Hideaki Takizawa, Shougo Hayashi, Takeshi Kinjo, Makoto Tachibanaki, Kenji Okamoto
Patent Citations (14), Referenced by (2), Classifications (22), Legal Events (4)
Thin film transistor matrix device and method for fabricating the same
US 20040046175 A1
A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin film transistors, and outside terminals 20 and outside terminals 30 opposed respectively to the ends of the gate bus lines and the drain bus lines 16, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines 24 for commonly connecting the gate bus lines 14 and drain connection lines 34 for commonly connecting the drain bus lines are formed in regions inner of the outside terminals 20, 30. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.
a plurality of thin film transistors arranged on the transparent insulating substrate in a matrix;
a plurality of picture element electrodes arranged on the transparent insulating substrate in a matrix and connected to the sources of the thin film transistors;
a plurality of bus lines for commonly connecting the gates or the drains of the thin film transistors;
outside terminals formed on a margin of the transparent insulating substrate and opposed to the ends of the bus lines; and
connection lines formed in regions inner of the outside terminals and commonly connecting said plurality of bus lines.
the connection lines include a plurality of connection lines, said plurality of gate bus lines which are adjacent to each other being respectively commonly connected to said plurality of connection lines.
3. A thin film transistor matrix device according to claim 2, further comprising
resistant lines which interconnect said plurality of connection lines and have a higher resistant value than the connection lines.
4. A thin film transistor matrix device according to claims 1, wherein
said plurality of bus lines are electrically disconnected from the connection lines.
5. A thin film transistor matrix device comprising:
a plurality of gate bus lines for commonly connecting the gates of the thin film transistors;
a plurality of drain bus lines for commonly connecting the drains of the thin film transistors;
first outside terminals formed on a margin of the transparent insulating substrate and opposed to the ends of the gate bus lines;
second outside terminals formed on a margin of the transparent insulating substrate and opposed to the ends of the drain bus lines; and
gate connection lines formed in an inner region of the second outside terminals and commonly connecting said plurality of drain bus lines.
6. A thin film transistor matrix device according to claim 5, further comprising
resistant lines for interconnecting the gate connection lines and the drain connection lines, and having a higher resistant value than the gate connection lines and the drain connection lines.
7. A thin film transistor matrix device according to claim 5, wherein
the gate connection lines include a first gate connection line and a second gate connection line, said plurality of gate bus lines which are adjacent to each other being respectively commonly connected to said first gate connection line and said second gate connection line;
the drain connection lines include a first drain connection line and a second drain connection line, said plurality of gate drain lines which are adjacent to each other being respectively commonly connected to said first drain connection and said drain connection line.
8. A thin film transistor matrix device according to claim 7, further comprising
resistant lines for interconnecting the first and the second gate connection lines, and the first and the second drain connection lines and having a resistant value than said plurality of connection lines.
9. A thin film transistor matrix device according to any one of claims 5 to 8, wherein
said plurality of gate bus lines are electrically disconnected from the gate connection lines, and
said plurality of drain bus lines are electrically disconnected from the drain connection lines.
10. A liquid crystal panel comprising: a thin film transistor matrix device according to claim 1; an opposed substrate opposed to the thin film transistor matrix device; and a liquid crystal disposed between the thin film transistor matrix device and the opposed substrate.
11. A liquid crystal panel comprising: a thin film transistor matrix device according to claim 5; an opposed substrate opposed to the thin film transistor matrix device; and a liquid crystal disposed between the thin film transistor matrix device and the opposed substrate.
12. A liquid crystal unit comprising a liquid crystal panel according to claim 10; a circuit substrate having a circuit for driving the liquid crystal panel formed thereon; and connection lines for connecting the liquid crystal panel with the circuit substrate.
13. A liquid crystal unit comprising a liquid crystal panel according to claim 11; a circuit substrate having a circuit for driving the liquid crystal panel formed thereon; and connection lines for connecting the liquid crystal panel with the circuit substrate.
14. A method for fabricating a thin film transistor matrix device comprising:
a first step of forming on a transparent insulating substrate a plurality of gate bus lines for commonly connecting the gates of thin film transistors, first outside terminals opposed to ends of the gate bus lines, and a gate connection line formed in a region inner of the first outside terminals for commonly connecting said plurality of gate bus lines;
a second step of forming a first insulating film on the entire surface; and
a third step of forming on the first insulating film a plurality of drain bus lines for commonly connecting the drains of the thin film transistors, second outside terminals opposed to the ends of the drain bus lines, and a drain connection line formed in a region inner of the second outside terminals for commonly connecting said plurality of drain bus lines.
15. A method for fabricating a thin film transistor matrix device comprising:
a first step of forming on a transparent insulating substrate a plurality of gate bus lines for commonly connecting the gates of thin film transistors, first outside terminals opposed to the ends of the gate bus lines, and a first gate connection line for commonly connecting the gate bus lines of one of groups in which adjacent ones of said plurality of gate bus lines are divided;
a second step of forming a first insulating film on the entire surface;
a third step of forming on the first insulating film a plurality of drain bus lines for commonly connecting the drains of the thin film transistors, second outside terminals opposed to the ends of the drain bus lines, and a first drain connection line for commonly connecting the drain bus lines of one of groups in which adjacent ones of said plurality of drain bus lines are divided;
a fourth step of forming a second insulating film on the entire surface; and
a fifth step of forming on the second insulating film picture element electrodes, a second gate connection line for commonly connecting the gate bus lines of the other of the groups in which adjacent ones of said plurality of gate bus lines are divided, and a second drain connection line for commonly connecting the drain bus lines of the other of the groups in which adjacent ones of said plurality of drain bus lines are divided.
16. A method for fabricating a thin film transistor matrix device comprising:
a first step of forming on a transparent insulating substrate a plurality of gate bus lines for commonly connecting the gates of thin film transistors, first outside terminals opposed to the ends of the gate bus lines, a fist gate connection line for commonly connecting the gate bus lines of one of groups in which adjacent ones of said plurality of gate bus lines are divided, and a first drain connection line for commonly connecting the drain bus lines of one of groups in which adjacent ones of said plurality of drain bus lines are divided;
a third step forming on the first insulating film said plurality of drain bus lines for commonly connecting the drains of the thin film transistors, second outside terminals opposed to the ends of the drain bus lines; a second drain connection line for commonly connecting the drain bus lines of the other of the groups in which adjacent ones of said plurality of drain bus lines are divided, and a second gate connection line for commonly connecting the gate bus lines of the other of the groups in which adjacent ones of said plurality of gate bus lines are divided.
17. A method for fabricating a thin film transistor matrix device comprising:
a first step of forming on a transparent insulating substrate a plurality of gate bus lines for commonly connecting the gates of thin film transistors, first outside terminals opposed to the ends of the gate bus lines, a first gate connection line for commonly connecting the gate bus lines of one of groups in which adjacent ones of said plurality of gate bus lines are divided, and a first drain connection line for commonly connecting the drain bus lines of one of groups in which adjacent ones of said plurality of drain bus lines are divided;
a third step of forming on the first insulating film said plurality of drain bus lines for commonly connecting the drains of the thin film transistors, second outside terminals opposed to the ends of the drain bus lines, a second drain connection line, and a second gate connection line;
a fifth step of forming on the second insulating film picture element electrodes, a first connection line for connecting the drain bus lines of the other of the groups in which adjacent ones of said plurality of drain lines are divided to the second drain connection line, and a second connection line for connecting the gate bus lines of the other of the groups in which adjacent ones of said plurality of gate bus lines are divided to the second gate connection line.
18. A method for fabricating a thin film transistor matrix device according to claim 14, further comprising
a fourth step of forming a second insulating film on the entire surface after the third step; and
a fifth step of forming on the second insulating film picture element electrodes, and a resistant line for interconnecting the gate connection lines and the drain connection lines.
19. A method for fabricating a thin film transistor matrix device according to claim 16, further comprising
20. A method for fabricating a thin film transistor matrix device according to claim 15, wherein
in the fifth step resistant lines for interconnecting the first and the second gate connection lines and the first and the second drain connection lines are formed.
21. A method for fabricating a thin film transistor matrix device according to claim 17, wherein
22. A method for fabricating a thin film transistor matrix device according to claim 14, wherein
after the fabrication steps are over, the gate bus lines are electrically disconnected from the gate connection lines, and the drain bus lines are electrically disconnected from the drain connection lines.
[0024]FIG. 1 is a plan view of the thin film transistor matrix device according to a first embodiment of the present invention.
[0025]FIG. 2 is an enlarged plan view of the thin film transistor matrix device of FIG. 1.
[0026]FIG. 3 is an enlarged plan view of an image display region of the thin film transistor matrix device of FIG. 1.
[0027]FIG. 4 is a sectional view of the thin film transistor matrix device of. FIGS. 2 and 3.
[0028]FIGS. 5A to 5D are sectional views of the thin film transistor matrix device according to the first embodiment of the present invention at the respective steps of a method for fabricating the same (Part 1).
[0029]FIGS. 6A to 6D are sectional views of the thin film transistor matrix device according to the first embodiment of the present invention at the respective steps of a method for fabricating the same (Part 2).
[0030]FIG. 7 is a plan view of the thin film transistor matrix device according to a second embodiment of the present invention.
[0031]FIG. 8 is an enlarged plan view of the thin film transistor matrix device of FIG. 7.
[0032]FIG. 9 is a plan view of the thin film transistor matrix device according to a third embodiment of the present invention.
[0033]FIG. 10 is an enlarged plan view of the thin film transistor matrix device of FIG. 9.
[0034]FIG. 11 is sectional views of the thin film transistor matrix device of FIG. 10.
[0035]FIGS. 12A to 12D are sectional views of the thin film transistor matrix device according to the third embodiment of the present invention at the respective steps of a first method for fabricating the same (Part 1).
[0036]FIGS. 13A to 13D are sectional views of the thin film transistor matrix device according to the third embodiment of the present invention at the respective steps of the first method for fabricating the same (Part 2).
[0037]FIG. 14 is a plan view of the thin film transistor matrix device according to the third embodiment of the present invention at the respective steps of the first method for fabricating the same (Part 1).
[0038]FIG. 15 is a plan view of the thin film transistor matrix device according to the third embodiment of the present invention at the respective steps of the first method for fabricating the same (Part 2).
[0039]FIG. 16 is a plan view of the thin film transistor matrix device according to the third embodiment of the present invention at the respective steps of the first method for fabricating the same (Part 3).
[0040]FIG. 17 is a plan view of the thin film transistor matrix device according to the third embodiment of the present invention at the respective steps of the first method for fabricating the same (Part 4).
[0041]FIGS. 18A to 18D are sectional views of the thin film transistor matrix device according to the third embodiment of the present invention at the respective steps of a second method for fabricating the same (Part 1).
[0042]FIGS. 19A to 19C are sectional views of the thin film transistor matrix device according to the third embodiment of the present invention at the respective steps of the second method for fabricating the same (Part 2).
[0043]FIG. 20 is a plan view of the thin film transistor matrix device according to the third embodiment of the present invention at a step of the second method for fabricating the same (Part 1).
[0044]FIG. 21 is a plan view of the thin film transistor matrix device according to the third embodiment of the present invention at a step of the second method for fabricating the same (Part 2).
[0045]FIG. 22 is a plan view of the thin film transistor matrix device according to the third embodiment of the present invention at a step of the second method for fabricating the same (Part 3).
[0046]FIG. 23 is a plan view of the thin film transistor matrix device according to the third embodiment of the present invention at a step of the second method for fabricating the same (Part 4).
[0047]FIG. 24 is a plan view of the thin film transistor matrix device according to a fourth embodiment of the present invention.
[0048]FIG. 25 is an enlarged plan view of the thin film transistor matrix device of FIG. 24.
[0049]FIG. 26 is sectional views of the thin film transistor matrix device of FIG. 25.
[0050]FIGS. 27A to 27D are sectional views of the thin film transistor matrix device according to the fourth embodiment of the present invention at the respective steps of a first method for fabricating the same (Part 1).
[0051]FIGS. 28A to 28D are sectional views of the thin film transistor matrix device according to the fourth embodiment of the present invention at the respective steps of the first method for fabricating the same (Part 2).
[0052]FIG. 29 is a plan view of the thin film transistor matrix device according to the fourth embodiment of the present invention at a step of the first method for fabricating the same (Part 1).
[0053]FIG. 30 is a plan view of the thin film transistor matrix device according to the fourth embodiment of the present invention at a step of the first method for fabricating the same (Part 2).
[0054]FIG. 31 is a plan view of the thin film transistor matrix device according to the fourth embodiment of the present invention at a step of the fourth method for fabricating the same (Part 3).
[0055]FIG. 32 is a plan view of the thin film transistor matrix device according to the fourth embodiment of the present invention at a step of the fourth method for fabricating the same (Part 4).
[0056]FIG. 33 is a plan view of the thin film transistor matrix device according to a fifth embodiment of the present invention.
[0057]FIG. 34 is an enlarged plan view of the thin film matrix device of FIG. 33.
[0058]FIG. 35 is a plan view of a conventional thin film matrix device.
[0062]FIG. 1 shows a pattern layout of the thin film transistor matrix device according to the present embodiment. FIG. 2 is an enlarged view of a wiring region of the thin film transistor matrix device. FIG. 3 is an enlarged view of an image display region of the thin film transistor matrix device of FIG. 1. FIG. 4 is a sectional view of the thin film transistor matrix device of FIG. 1.
[0073]FIG. 3 shows a plane structure of the image display unit 12. The thin film transistors 40 are disposed at the intersections between the gate bus lines 14 and the drain bus lines 16. The thin film transistors 40 have the gate electrodes 40 g connected to the gate bus lines 14, the drain electrodes 40 d connected to the drain bus lines 16 and the source electrodes 40 s connected to the picture element electrodes 42. Capacitors 44 are disposed at the centers of the picture element electrodes 42.
A sectional structure of the image display unit 12 is shown by the C-C′ sectional view in FIG. 4. On the transparent insulating substrate 10 there are formed the gate bus lines 14 of a metal layer 46 of, e.g., Al or Cr, and capacitor electrodes 46 a of the capacitors 44. The gate bus lines 14 and the capacitor electrodes 46 a share the same layer with the gate electrodes 40 g.
On the metal layer 46 there is formed a first insulating film 48 of an SiN film, a two-layer film of an SiO2 film and an SiN film, or others. The first insulating film 48 shares the same layer with a gate insulating film of the thin film transistors 40.
A second insulating film 54 of, e.g., an SiN film, a two-layer film of an SiO2 film and an SiN film, or others, is formed on the metal layer 52. In the second insulating film 54, contact holes are formed on the source electrodes 40 s and the counter electrodes 52 a.
An transparent electrode film 56 of, e.g., ITO or others, is formed on the second insulating film 54. The transparent electrode film 56 forms the picture element electrodes 42 and is connected to the source electrodes 40 s and the counter electrodes 52 a through the contact holes.
[0102]FIG. 7 shows a pattern layout of the thin film transistor matrix device according to the present embodiment. FIG. 8 is an enlarged view of the wiring region of the thin film transistor matrix device of FIG. 7. The same members and members of the same kinds of the thin film transistor matrix device according to the present embodiment as those of the thin film transistor matrix device according to the first embodiment are represented by common reference numerals to simplify or not to repeat their explanation.
The even number-th gate bus lines 14 b have the bumps 18 b formed on the ends on the left side as viewed in FIG. 7. The bumps 18 b are commonly connected to the gate connection line 24 b through thin connection lines 26 b. The gate connection line 24 b is extended longitudinally in an IC chip region 22 between input terminals 20 and the bumps 18 b.
Odd number-th drain bus lines 16 a have bumps 28 a formed on the ends on the upper side as viewed in FIG. 7. The bumps 28 a are commonly connected to a drain connection line 34 a through thin connection lines 36 a. The drain connection line 34 a is extended widthwise in th IC chip region 32 between the input terminals 30 and the bumps 28 a.
The even number-th drain bus lines 16 b have the bumps 29 b formed on the end on the upper side as viewed in FIG. 7 and the ends on the lower end commonly connected to a drain connection line 34 b. The drain connection line 34 b is extended along the lower edge of the transparent insulating substrate 10.
The gate connection lines 24 a, 24 b and the drain connection lines 34 a, 34 b are interconnected by resistant lines 38 a, 38 b, 38 c, 38 d. The resistant line 38 a interconnects the gate connection line 24 a and the drain connection line 34 a; the resistant line 38 b interconnects the gate connection line 24 a and the drain connection line 34 b; the resistant line 38 c interconnects the gate connection line 24 b and the drain connection line 34 a; and the resistant line 38 d interconnects the gate connection line 24 b and the drain connection line 34 b.
Thus, according to the present embodiment, the gate bus lines 14 a, 14 b are respectively commonly connected to the gate connection lines 24 a, 24 b. The drain bus lines 16 a, 16 b are respectively commonly connected to the drain connection lines 34 a, 34 b, whereby in the processes for fabricating the thin film transistors and the liquid crystal panel, no local charges are present even when electrostatic charges are applied, and electric stresses can be mitigated.
[0115]FIG. 9 shows a pattern layout of the thin film transistor matrix device according to the present embodiment. FIG. 10 is an enlarged view of the wiring region of the thin film transistor matrix device of FIG. 9. FIG. 11 is a sectional view of the thin film transistor matrix device of FIG. 9. The same members or members of the same kinds of the thin film transistor matrix device according to the present embodiment as those of the thin film transistor matrix device according to the first and the second embodiments are represented by common reference numerals to simplify or not to repeat their explanation.
The gate connection lines 24 a, 24 b are extended longitudinally through an IC chip region 22 between input terminals 20 and the bumps 18 a, 18 b.
Bumps 28 a are formed on the ends of the odd number-th bus lines 16 a on the upper side as viewed in FIG. 9. The bumps 28 a are commonly connected to the drain connection line 34 a through thin connection lines 36 a and contact hole 37.
Bums 28 b are formed on the ends of the even number-th drain bus lines 16 b on the upper end as viewed in FIG. 9. The bumps 28 b are commonly connected to the drain connection line 34 b through thin connection lines 36 b.
The drain connection lines 34 a, 34 b are extended transversely through an IC chip region 32 between input terminals 30 and the bumps 28 a, 28 b.
The gate connection lines 24 a, 24 b and the drain connection lines 34 a, 34 b are connected with each other by resistant lines 38 a, 38 b, 38 c, 38 d. The resistant line 38 a interconnects the gate connection line 24 a and the gate connection line 24 b; the resistant line 38 b interconnects the gate connection line 24 a and the drain connection line 34 b; the resistant line 38 c interconnects the gate connection line 24 b and the drain connection line 34 a; and the resistant line 38 d interconnects the drain connection line 34 a and the drain connection line 34 b.
Then, a sectional structure of the thin film transistor matrix device according to the present embodiment will be explained with reference to FIG. 11.
Next, by the use of a fifth mask, the transparent electrode film 56 is patterned to form picture element electrodes 52, the gate connection line 34 b, and the resistant lines 38 a, 38 b, 38 c, 38 d (FIGS. 13D and 17). The resistant lines 38A, 38B, 38C, 38D are patterned so as to interconnect the ends of the gate connection lines 24 a, 24 b, and the ends of the drain connection lines 34 a, 34 b.
Thus, as in the first embodiment, by the use of only 5 masks, the thin film transistor matrix device according to the present embodiment can be fabricated.
[0166]FIG. 24 is a view of the pattern layout of the thin film transistor matrix device according to the present embodiment. FIG. 25 is an enlarged view of the wiring region of the thin film transistor matrix device of FIG. 24. FIG. 26 is sectional views of the thin film transistor matrix device of FIG. 24. The same members and members of the same kinds of the present embodiment as the thin film transistor matrix device according to the first to the third embodiments are represented by common reference numerals to simplify or not to repeat their explanation.
In the thin film transistor matrix device according to the present embodiment as well as the third embodiment, gate connection lines 24 a, 24 b respectively commonly connecting gate bus lines 14 a, 14 b which are adjacent to each other are arranged on the same side of a transparent insulating substrate 10, and drain connection lines 34 a, 34 b respectively commonly connecting drain bus lines 16 a, 16 b are arranged on the same side of the transparent insulating substrate 10, but the present embodiment is different from the third embodiment in the connection structure between the gate bus lines 14 a, 14 b and the gate connection lines 24 a, 24 b and that between the drain bus lines 16 a, 16 b and the drain connection lines 34 a, 34 b.
First, a layout of the thin film transistor matrix device according to the present embodiment in a plane will be explained with reference to FIGS. 24 and 25.
Bumps 18 a are formed on the ends of the odd number-th gate bus lines 14 a on the right side as viewed in FIG. 24. The bumps 18 a are commonly connected to the gate connection line 24 a through thin connection lines 26 a, contact holes 27 b, a connection line 25 and contact holes 27 a.
Bumps 18 b are formed on the ends of the even number-th gate bus lines 14 b on the left side as viewed in FIG. 24. The bumps 18 b are commonly connected to the gate connection line 24 b through thin connection lines 26 b.
The gate connection lines 24 a, 24 b are extended longitudinally through an IC chip region 22 between inputs terminals 20 and the bumps 18 a, 18 b.
Bumps 28 a are formed on the ends of the odd number-th drain bus lines 16 a on the upper end as viewed in FIG. 24. The bumps 28 a are commonly connected to the drain connection line 34 a through thin connection lines 36 a, contact holes 37 b, a connection line 35 and contact holes 37 a.
Bumps 28 b are formed on the ends of the even number-th drain bus lines 16 b on the upper end as viewed in FIG. 24. The bumps 28 b are commonly connected to the drain connection line 34 s through thin connection lines 36 b.
The drain connection lines 34 a, 34 b are extended longitudinally through an IC chip region 32 between input terminals 30 and the bumps 28 a, 28 b.
Resistant lines 38 a, 38 b, 38 c, 38 d interconnect the gate connection lines 24 a, 24 b and the drain connection lines 34 a, 34 b. The resistant line 38 a interconnects the gate connection line 24 a and the gate connection line 24 b; the resistant line 38 b interconnects the gate connection line 24 a and the drain connection line 34 b; the resistant line 38 c interconnects the gate connection line 24 b and the drain connection line 34 a; and the resistant line 38 d interconnects the drain connection line 34 a and the drain connection line 34 b.
Then, a sectional structure of the thin film transistor matrix device according to the present embodiment will be explained.
On a transparent insulating substrate 10, the drain connection line 34 b of the same layer as the metal layer 46 is formed. A first insulating film 48 is formed on the transparent insulating film 10 and the drain connection line 34 b. On the first insulating film 48, the thin connection line 36 b and the drain connection lines 34 a of the same layer as the semiconductor active layer 50 and the metal layer 52. A second insulating film 54 is formed on the metal layer 52. The contact holes 37 a are formed in the first and the second insulating films 48, 54 and reach the drain connection line 34 b. The contact holes 37 b are formed in the second insulating film 54 and reach the thin connection lines 36 b. The connection line 35 of the same layer as an transparent electrode film 56 is formed on the second insulating film 54 and interconnect the thin connection lines 36 b and the drain connection line 34 b through the contact holes 37 a, 37 b.
A sectional structure of the vicinity of the gate connection lines 24 a, 24 b will be explained with reference to the plan view of FIG. 25 and a sectional view along the line B-B′ in FIG. 26.
On the transparent insulating substrate 10, the gate connection line 24 b and the thin connection lines 26 b of the same layer as the metal layer 46 are formed. On the metal layer 46, the first insulating film 48 is formed. On the fist insulating film 48, the gate connection line 24 a of the same layer as the semiconductor active layer 50 and the metal layer 52 is formed. The second insulating film 54 is formed on the first insulating film 54 and the gate connection line 24 a. The contact holes 27 a are formed in the second insulating film 54 and reach the gate connection line 24 a. The contact holes 27 b are formed in the first and the second insulating films 48, 54 and reach the thin connection lines 26 a. On the second insulating film 54, the connection line 25 of the same layer as the transparent electrode film 56 is formed and interconnects the thin connection lines 26 a and the gate connection line 24 b through the contact holes 27 a, 27 b.
4.2 Fabrication Method
Then, the transparent electrode film 56 is patterned by the use of a fifth mask to form the connection line 35, picture element electrodes 42, the gate connection line 24 a, the drain connection line 34 b, the resistant lines 38 a, 38 b, 38 b, 38 d, and the connection line 25 (FIGS. 28D and 32). The resistant lines 38 a, 38 b, 38 c, 38 d are patterned so as to interconnect the ends of the gate connection lines 24 a, 24 b and the ends of the drain connection lines 34 a, 34 b.
Thus, by the use of only 5 masks, the thin film transistor matrix device according to the present embodiment can be fabricated as the first embodiment.
[0200]FIG. 33 is a view of a pattern layout of the thin film transistor matrix device according to the present embodiment. FIG. 34 is an enlarged view of the wiring region of the thin film transistor matrix device of FIG. 33. The same members or members of the same kinds of the present embodiment as the first to the fourth embodiments are represented by common reference numerals to simplify or not to repeat their explanation.
A plurality of gate bus lines 14 are divided into odd number-th gate bus lines 14 a and even number-th gate bus lines 14 b.
Bumps 18 a are formed on the ends of the odd number-th gate bus lines 14 a on the right side as viewed in FIG. 33. Input terminals 20 a for receiving signals from the outside are formed on the right margin of the transparent insulating substrate 10. The gate connection line 24 a is extended longitudinally through an IC chip region 22 between the gate connection line 24 a, and the input terminals 20 a and the bumps 18 a.
Bumps 18 b are formed on the ends of the even number-th gate bus lines 14 b on the left side as viewed in FIG. 33. Input terminals 20 b for receiving signals from the outside are formed on the left margin of the transparent insulating substrate 10. The gate connection line 24 b is extended longitudinally through an IC chip region 22 between the input terminals 20 b and the bumps 18 b.
Bumps 28 a are formed on the ends of the odd number-th drain bus lines 16 a on the upper side as viewed in FIG. 33. Input terminals 30 a for receiving signals from the outside are formed on the upper margin of the transparent insulating substrate 10. The gate connection line 34 a is extended longitudinally through an IC chip region 32 between the input terminals 30 a and the bumps 28 a.
Bumps 28 b are formed on the ends of the even number-th drain bus lines 16 b on the lower end as viewed in FIG. 33. Input terminals 30 b for receiving signals from the outside are formed on the lower margin of the transparent insulating substrate 10. The gate connection line 34 b is extended longitudinally through an IC chip region between the input terminals 30 b and the bumps 28 b.
Resistant lines 38 a, 38 b, 38 c, 38 d interconnect the gate connection lines 24 a, 24 b and the drain connection lines 34 a, 34 b. The resistant line 38 a interconnects the gate connection line 24 a and the drain connection line 34 a; the resistant connection line 38 b interconnects the gate connection line 24 a and the drain connection line 34 b; the resistant line 38 c interconnects the gate connection line 24 b and the drain connection line 34 a; and the resistant line 38 d interconnects the gate connection line 24 b and the drain connection line 34 b.
As described above, the gate bus lines 14 a, 14 b are respectively commonly connected to the gate connection lines 24 a, 24 b, and the drain bus lines 16 a, 16 b are respectively commonly connected to the drain connection lines 34 a, 34 b, whereby in the process for fabricating the thin film transistor matrix device and in the process for forming a liquid crystal panel, even when electrostatic charges are applied, there is no local presence of charges, and electric stresses can be mitigated. Furthermore, according to the present embodiment, the gate bus lines 14 a, 14 b which are adjacent to each other are respectively commonly connected to the gate connection lines, and the drain bus lines 24 a, 24 b which are adjacent to each other are respectively commonly connected to the drain connection lines, whereby different voltages are applied to the gate bus lines which are adjacent to each other and to the drain bus lines which are adjacent to each other, whereby inspection of high precision can be conducted.
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U.S. Classification 257/72, 438/151, 438/149, 257/59, 257/E27.111
International Classification G02F1/1368, G02F1/136, G02F1/1345, H01L21/77, G02F1/1362, H01L27/12, H01L21/84
Cooperative Classification G02F1/1345, H01L27/1244, H01L27/124, G02F1/13454, G02F2001/136254, G02F1/136204
European Classification H01L27/12T, G02F1/1345, G02F1/1362A, H01L27/12