Source: http://www.google.com/patents/US20020066963?dq=6,418,462
Timestamp: 2014-12-25 17:55:13
Document Index: 679301299

Matched Legal Cases: ['art 1200', 'art 1200', 'art 1200', 'art 1200', 'art 1200', 'art 1200', 'art 1200', 'art 1200', 'art 1200', 'art 1200', 'art 1200']

Patent US20020066963 - Ball-less clip bonding - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor component includes a semiconductor chip (120, 1120), an electrically conductive adhesive located over the semiconductor chip, and a clip bond (231, 232, 1231, 1232) located over the electrically conductive adhesive. The clip bond has at least one burr to retain the electrically conductive...http://www.google.com/patents/US20020066963?utm_source=gb-gplus-sharePatent US20020066963 - Ball-less clip bondingAdvanced Patent SearchPublication numberUS20020066963 A1Publication typeApplicationApplication numberUS 09/728,390Publication dateJun 6, 2002Filing dateDec 4, 2000Priority dateDec 4, 2000Also published asUS6479893Publication number09728390, 728390, US 2002/0066963 A1, US 2002/066963 A1, US 20020066963 A1, US 20020066963A1, US 2002066963 A1, US 2002066963A1, US-A1-20020066963, US-A1-2002066963, US2002/0066963A1, US2002/066963A1, US20020066963 A1, US20020066963A1, US2002066963 A1, US2002066963A1InventorsSaat Embong, Chee HiongOriginal AssigneeSemiconductor Components Industries, LlcExport CitationBiBTeX, EndNote, RefManReferenced by (3), Classifications (33), Legal Events (9) External Links: USPTO, USPTO Assignment, EspacenetBall-less clip bondingUS 20020066963 A1Abstract A semiconductor component includes a semiconductor chip (120, 1120), an electrically conductive adhesive located over the semiconductor chip, and a clip bond (231, 232, 1231, 1232) located over the electrically conductive adhesive. The clip bond has at least one burr to retain the electrically conductive adhesive. Images(11) Claims(26)
1. A semiconductor component comprising: a semiconductor chip; an electrically conductive adhesive located over the semiconductor chip; and a clip bond located over the electrically conductive adhesive, the clip bond having at least one burr to retain the electrically conductive adhesive. 2. The semiconductor component of claim 1 wherein: the clip bond further comprises: at least one hole having a perimeter and located over the electrically conductive adhesive, wherein: the at least one burr is located adjacent to the perimeter of the at least one hole. 3. The semiconductor component of claim 1 wherein: the clip bond further comprises: a plurality of burrs to retain the electrically conductive adhesive, the plurality of burrs comprising the at least one burr. 4. The semiconductor component of claim 3 wherein: the clip bond further comprises: at least one hole having a perimeter and located over the electrically conductive adhesive, wherein: the plurality of burrs are located adjacent to the perimeter of the at least one hole. 5. The semiconductor component of claim 4 wherein: each of the plurality of burrs is located adjacent to the perimeter of the at least one hole. 6. The semiconductor component of claim 1 wherein: the clip bond further comprises: a plurality of holes, each having a perimeter and located over the electrically conductive adhesive, wherein: the at least one burr is located adjacent to the perimeter of at least one of the plurality of holes. 7. The semiconductor component of claim 6 wherein: the clip bond further comprises: a plurality of burrs comprising the at least one burr, wherein: the perimeter of each of the plurality of holes is adjacent to at least one of the plurality of burrs. 8. The semiconductor component of claim 7 wherein: the perimeter of each of the plurality of holes is adjacent to a plurality of the plurality of burrs. 9. The semiconductor component of claim 1 further comprising: a plurality of clip bonds located over and electrically coupled to the semiconductor chip, wherein: the plurality of clip bonds comprises the clip bond. 10. The semiconductor component of claim 9 wherein: each of the plurality of clip bonds comprises a plurality of burrs to retain the electrically conductive adhesive; and the plurality of burrs of a first one of the plurality of clip bonds comprises the at least one burr. 11. The semiconductor component of claim 10 wherein: each of the plurality of clip bonds further comprises: a plurality of holes, each having a perimeter, wherein: the perimeter of each of the plurality of holes of the clip bond is located adjacent to a plurality of the plurality of burrs of the clip bond. 12. The semiconductor component of claim 1 further comprising: a lead frame, wherein: the semiconductor chip is located over the lead frame; the clip bond is located over the lead frame; and the clip bond electrically couples together the lead frame and the semiconductor chip. 13. A semiconductor component comprising: a lead frame; a semiconductor chip; a plurality of portions of solder located over and electrically coupled to the semiconductor chip and located over and electrically coupled to the lead frame; and a plurality of clip bonds located over and electrically coupled to the plurality of portions of the solder, each of the plurality of clip bonds having a plurality of burrs to retain the plurality of portions of the solder. 14. The semiconductor component of claim 13 wherein: each of the plurality of clip bonds further comprises: a plurality of holes located over the solder, each of the plurality of holes having a perimeter, wherein: a plurality of the plurality of burrs of the clip bond are located adjacent to the perimeter of each of the plurality of holes of the clip bond. 15. The semiconductor component of claim 14 wherein: a first one of the plurality of portions of the solder is located over a first portion of the lead frame; a second one of the plurality of portions of the solder is located over a second portion of the lead frame; a third one of the plurality of portions of the solder is located over a first portion of the semiconductor chip; a fourth one of the plurality of portions of the solder is located over a second portion of the semiconductor chip; a first one of the plurality of holes of a first one of the plurality of clip bonds is located over the first one of the plurality of portions of the solder; a second one of the plurality of holes of the first one of the plurality of clip bonds is located over the third one of the plurality of portions of the solder; a first one of the plurality of holes of a second one of the plurality of clip bonds is located over the second one of the plurality of portions of the solder; and a second one of the plurality of holes of the second one of the plurality of clip bonds is located over the fourth one of the plurality of portions of the solder. 16. A method of manufacturing a semiconductor component comprising: using at least one burr of a clip bond to retain an electrically conductive adhesive. 17. The method of claim 16 further comprising: coupling the clip bond to a semiconductor chip. 18. The method of claim 16 further comprising: providing the clip bond to have at least one hole, a perimeter of the at least one hole adjacent to the at least one burr. 19. The method of claim 16 further comprising: providing the clip bond coupled to the electrically conductive adhesive. 20. The method of claim 19 further comprising: heating the clip bond and the electrically conductive adhesive. 21. The method of claim 16 further comprising: heating the clip bond and the electrically conductive adhesive; and coupling the clip bond to a semiconductor chip after heating the clip bond and the electrically conductive adhesive. 22. A method of manufacturing a semiconductor component comprising: mounting a semiconductor chip over a lead frame; providing a clip bond coupled to solder, the clip bond having a plurality of burrs to retain the solder and having a plurality of holes adjacent to the plurality of burrs; melting the solder; and coupling the clip bond with the solder to the semiconductor chip and the lead frame. 23. The method of claim 22 further comprising: manufacturing a semiconductor device in the semiconductor chip. 24. The method of claim 22 further comprising: stamping the clip bond to form the plurality of holes in the clip bond and to form the plurality of burrs in the clip bond. 25. The method of claim 22 wherein: coupling the clip bond with the solder to the semiconductor chip and the lead frame occurs after melting the solder. 26. The method of claim 22 further comprising: packaging the semiconductor chip, the clip bond, and at least a portion of the lead frame; trimming leads of the lead frame; and forming the leads of the lead frame.
FIELD OF THE INVENTION [0001] This invention relates to electronics, in general, and to semiconductor components and methods of manufacturing, in particular BACKGROUND OF THE INVENTION [0002] A semiconductor component typically includes a metal lead frame, a semiconductor die mounted on the metal lead frame, and wire bonds electrically connecting the semiconductor die to the metal lead frame. The electrical performance of this type of semiconductor component suffers from high electrical resistance and inductance of each of the wire bonds. Furthermore, the manufacturing process of this type of semiconductor component suffers from low throughput. [0003] Another type of semiconductor component uses clip bonds to electrically connect the semiconductor die to the metal lead frame. This type of semiconductor component does not suffer from the aforementioned problems of high electrical resistance and high electrical inductance of wire bonds. This type of semiconductor component is not, however, compatible with small pitch interconnect schemes because of an electrical shorting problem occurring during solder reflow. [0004] Yet another type of semiconductor component uses a ball grid array and clip bonds to permit more precise interconnect bonding. This type of semiconductor component does not use a metal lead frame. The manufacturing process for this type of semiconductor component, however, is relatively expensive and is not compatible with low cost packaging schemes. Accordingly, a need exists for a semiconductor component having improved electrical performance resulting from low parasitic resistances and low parasitic conductances. A need also exists for the semiconductor component to be compatible with small pitch interconnect schemes. Another need exists for a method of manufacturing the semiconductor component to have a high throughput and low cost.
BRIEF DESCRIPTION OF THE DRAWINGS [0005] The invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures in which: [0006]FIG. 1 illustrates a top view of a portion of a semiconductor component in accordance with and embodiment of the invention; [0007]FIG. 2 illustrates a top view of a clip bond in accordance with an embodiment of the invention; [0008]FIG. 3 illustrates a cross-sectional view of the clip bond of FIG. 2 taken along a section line 3-3 in [0009]FIG. 2 in accordance with an embodiment of the invention; [0010]FIG. 4 illustrates a top view of the portion of the semiconductor component after a later step of a manufacturing process in accordance with an embodiment of the invention; [0011]FIG. 5 illustrates a cross-sectional view of the portion of the semiconductor component of FIG. 4 taken along a section line 5-5 in FIG. 4 in accordance with an embodiment of the invention; [0012]FIG. 6 illustrates a top view of the semiconductor component after a subsequent step in the manufacturing process in accordance with an embodiment of the invention; [0013]FIG. 7 illustrates a cross-sectional view of the semiconductor component of FIG. 6 taken along a section line 7-7 in FIG. 6 in accordance with an embodiment of the invention. [0014]FIG. 8 illustrates a top view of the semiconductor component after an even later step in the manufacturing process in accordance with an embodiment of the invention; [0015]FIG. 9 illustrates a side view of the semiconductor component of FIG. 8 in accordance with an embodiment of the invention; [0016]FIG. 10 illustrates a top view of the semiconductor component after a subsequent step in the manufacturing process in accordance with an embodiment of the invention; [0017]FIG. 11 illustrates a side view of the semiconductor component of FIG. 10 in accordance with an embodiment of the invention; [0018]FIG. 12 illustrates a flow chart of a method of manufacturing a semiconductor component in accordance with an embodiment of the invention; and [0019]FIG. 13 illustrates a cross-sectional view of a different semiconductor component in accordance with an embodiment of the invention. [0020] For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques are omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale, and the same reference numerals in different figures denote the same elements. [0021] Furthermore, the terms first, second, third, fourth, and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is further understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein. Moreover, the terms top, bottom, over, under, and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.
DETAILED DESCRIPTION OF THE DRAWINGS [0022]FIG. 1 illustrates a top view of a portion of a semiconductor component 100. As explained hereinafter, semiconductor component 100 comprises, among other features, a semiconductor chip, an electrically conductive adhesive located over the semiconductor chip, and a clip bond located over the electrically conductive adhesive and the semiconductor chip. The clip bond has at least one burr. The clip bond can also include at least one hole, notch, or via located over the electrically conductive adhesive. The burr or burrs are located adjacent to a perimeter of each of the hole or holes such that the configuration of the hole or holes and the burr or burrs retain or hold the electrically conductive adhesive in place, even when the electrically conductive adhesive is melted. [0023] As illustrated in FIG. 1, semiconductor component 100 includes, among other features, a lead frame 110. In the preferred embodiment, lead frame 110 is a stamped metal lead frame and includes a flag portion 111 and a plurality of leads 112, 113, 114, 115, 116, 117, 118, and 119. Tie bars and dam bars physically coupled together flag portion 111 and leads 112 through 119. One skilled in the art will understand that lead frame 110 is one of a plurality of lead frames formed from a single sheet of metal. In other embodiments, lead frame 110 can be a ceramic chip carrier, a ball grid array substrate, or the like. [0024] Component 100 also includes a semiconductor chip 120. Chip 120 is mounted over flag portion 111 of lead frame 110. Chip 120 includes a semiconductor substrate and can also include a plurality of semiconductor, metal, and dielectric or non-electrically conductive layers. The substrate and layers of chip 120 are patterned and optionally doped to form a semiconductor device within chip 120. In the preferred embodiment, the semiconductor device is a discrete transistor. In another embodiment, the semiconductor device can be an integrated circuit. Chip 120 further includes bonding pads 121 and 122 electrically coupled to the semiconductor device. [0025]FIG. 2 illustrates a top view of a clip bond 231, and FIG. 3 illustrates a cross-sectional view of clip bond 231 taken along a section line 3-3 in FIG. 2. Clip bond 231 includes vias, notches, or holes 233 and 234 located at opposite ends of clip bond 231. As illustrated in FIG. 3, clip bond 231 also includes a plurality of burrs 333 and 334. Burrs 333 and 334 can be protrusions, rough or irregular protuberances, or a ragged edge extending from a main body of clip bond 231. Burrs 333 are located at or adjacent to a perimeter of hole 233, and burrs 334 are located at or adjacent to a perimeter of hole 234. Burrs 333 and 334 are located at an underside or bottom side of clip bond 231. [0026] As illustrated in FIG. 3, a plurality of portions of an electrically conductive adhesive are also located at the bottom side of clip bond 231. In particular, a portion 337 of the electrically conductive adhesive is located adjacent to hole 233 and burrs 333, and a portion 338 of the electrically conductive adhesive is located adjacent to hole 234 and burrs 334. As an example, the electrically conductive material can be solder or a metallic-filled epoxy. [0027] Clip bond 231 and portions 337 and 338 of the electrically conducted adhesive are heated to melt portions 337 and 338 of the electrically conductive adhesive. The configuration of holes 233 and 234 and burrs 333 and 334 serves to hold or retain portions 337 and 338 of the electrically conductive adhesive at holes 233 and 234 and burrs 333 and 334. After portions 337 and 338 of the electrically conductive adhesive are melted, clip bond 231 is coupled to the semiconductor component. [0028] In a different embodiment of clip bond 231, the clip bond can include a single hole. In another embodiment of clip bond 231, the clip bond can have a single burr or multiple burrs without any holes. In yet another embodiment of clip bond 231, regardless of the number of holes present in the clip bond, each hole can have or be adjacent to a single burr. In the preferred embodiment, the burr or burrs are located at or adjacent to a perimeter of a hole to simplify the manufacturing process for the clip-bond and to optimize the retaining or holding characteristic of the hole and its accompanying burr or burrs. [0029]FIG. 4 illustrates a top view of the portion of semiconductor component 100 after a later step of the manufacturing process, and FIG. 5 illustrates a cross-sectional view of the portion of semiconductor component 100 taken along a section line 5-5 in FIG. 4. Clip bond 231 is located over chip 120 and lead frame 110, and clip bond 231 couples chip 120 to lead frame 110. Portion 337 of the electrically conductive adhesive is used to electrically couple and adhere a portion of clip bond 231 adjacent to hole 233 to lead 112 of lead frame of 110. Similarly, portion 338 of the electrically conductive adhesive is used to electrically couple and adhere a portion of clip bond 231 adjacent to hole 234 to bond pad 121 of chip 120. [0030] Component 100 also includes a clip bond 232, which is similar to clip bond 231. Clip bond 232 has a plurality of holes 235. In the embodiment illustrated in FIG. 4, clip bond 232 has six of holes 235, but one skilled in the art will understand that clip bond 232 can have a different number of holes. [0031] Clip bond 232 also includes at least one burr, but preferably a plurality of burrs, located at or adjacent to a perimeter of each of holes 235. The burr or burrs are located at a bottom side of clip bond 232. Portions 239 of the electrically conductive adhesive are located at or adjacent to the plurality of holes 235 and the plurality of burrs at the bottom side of clip bond 232. The electrically conductive adhesive and clip bond 232 electrically couple bond pad 121 of chip 120 to leads 113, 114, and 115 of lead frame 110. [0032] Therefore, FIGS. 4 and 5 illustrate a plurality of portions of an electrically conductive adhesive located over a plurality of portions of semiconductor chip 120 and also over a plurality of portions of lead frame 110. In particular, a first one of the plurality of portions of the electrically conductive adhesive is located over a first portion of lead frame 110, and a second one of the plurality of portions of the electrically conductive adhesive is located over a second portion of lead frame 110. Furthermore, a third one of the plurality of portions of the electrically conductive adhesive is located over a first portion of semiconductor chip 120 and a fourth one of the plurality of portions of the electrically conductive adhesive is located over a second portion of semiconductor chip 120. Moreover, a plurality of clip bonds are located over the plurality of portions of the electrically conductive adhesive and are electrically coupled to semiconductor chip 120 through the plurality of portions of the electrically conductive adhesive. [0033] A portion 560 of the electrically conductive adhesive is used to adhere semiconductor chip 120 to flag portion 111 of lead frame 110. Portion 560 of the electrically conductive adhesive can also be used to electrically couple semiconductor chip 120 to leads 116, 117, 118, and 119. Portion 560 of the electrically conductive adhesive can be the same or different from portions 337, 338, and 239 of the electrically conductive adhesive. As an example, portions 337, 338, and 239 can be comprised of solder or conductive epoxies while portion 560 is comprised of an anisotropic conductive film. [0034]FIG. 6 illustrates a top view of semiconductor component 100 after a subsequent step in the manufacturing process, and FIG. 7 illustrates a cross-sectional view of component 100 taken along a section line 7-7 of FIG. 6. A packaging material 650 is molded around and encapsulates chip 120 (FIGS. 1, 4, and 5), at least a portion of lead frame 110, and the two clip bonds. [0035]FIG. 8 illustrates a top view of semiconductor component 100 after an even later step in the manufacturing process, and FIG. 9 illustrates a side view of component 100 after the even later step in the manufacturing process. Lead frame 110 is trimmed to singulate component 100 and to remove the tie bars and the dam bars from lead frame 110. [0036]FIG. 10 illustrates a top view of a portion of semiconductor component 100 after a subsequent step in the manufacturing process, and FIG. 11 illustrates a side view of semiconductor component 100 after the subsequent step in the manufacturing process. Leads 112 through 119 of lead frame 110 are bent or formed into a gull-wing configuration. Leads 112 through 119 of lead frame 110 can also be bent into other configurations including, but not limited to, a surface-mount configuration. [0037]FIG. 12 illustrates a flow chart 1200 of a method of manufacturing semiconductor components. At a step 1210 of flow chart 1200, a semiconductor chip is provided. The semiconductor chip contains a semiconductor device. Step 1210 can be performed by purchasing a semiconductor chip having the semiconductor device already manufactured in it. Step 1210 can also be performed by manufacturing a semiconductor device in the semiconductor chip. [0038] At a step 1220 of flow chart 1200, a lead frame is provided. The lead frame can be purchased, or the lead frame can be stamped from a sheet of metal. At a step 1230 of flow chart 1200, the semiconductor chip is mounted over the lead frame. [0039] At a step 1240 of flow chart 1200, a clip bond is provided where the clip bond is coupled to an electrically conductive adhesive. The clip bond has at least one burr to retain the electrically conductive adhesive. In the preferred embodiment, the clip bond has a plurality of such burrs. The clip bond can also have at least one hole adjacent to the burr or burrs to retain the electrically conductive adhesive. In the preferred embodiment, the clip bond has a plurality of such holes. [0040] Step 1240 can be performed by purchasing the clip bond or by stamping or punching the clip bond from a sheet of metal. This stamping or punching process can simultaneously define the shape and size of the clip bond and form the holes and burrs in the clip bond. The electrically conductive adhesive can be plated onto the clip bond. [0041] At a step 1250 of flow chart 1200, the clip bond and the electrically conductive adhesive are heated. Step 1250 melts the electrically conductive adhesive. At a step 1260 of flow chart 1200, the pluralities of burrs and holes are used to retain the electrically conductive adhesive. In the preferred embodiment where the electrically conductive material is comprised of solder, the internal cohesive force of the solder and the design of the holes and the burrs will hold the solder, prevent the solder from dripping off of the clip bond, and concentrate the solder at desired bonding locations of the clip bond. [0042] Next, at a step 1270 of flow chart 1200, the clip bond with the melted electrically conductive adhesive is coupled to the semiconductor chip and the lead frame. Step 1270 includes cooling the clip bond and the electrically conductive adhesive. Then, at a step 1280 of flow chart 1200, the semiconductor chip, the clip bond, and at least a portion of the lead frame are packaged or encapsulated in a single package. Subsequently, at a step 1290 of flow chart 1200, the leads of the lead frame are first trimmed and then formed. [0043] One skilled in the art will understand that the method of flow chart 1200 does not need to include a solder reflow step so that the method can include the coupling of a plurality of clip bonds to a single semiconductor chip and lead frame. The coupling step or steps can be easily accomplished without suffering from an electrical shorting problem during a solder reflow process. [0044]FIG. 13 illustrates a cross-sectional view of a semiconductor component 1300. Component 1300 includes a semiconductor chip 1120, which is similar to chip 120 in FIG. 2. Chip 1120 in FIG. 13 includes electrically conductive bond pads 1121 and 1122. [0045] Component 1300 also includes a clip bond 1231, which is similar to clip bond 231 in FIGS. 2 and 3. Clip bond 1231 in FIG. 13 includes vias, notches, or holes 1233 and 1234. A plurality of burrs are located at or adjacent to a perimeter of each of holes 1233 and 1234. The burrs are located at the top and bottom sides of clip bond 1231. Component 1300 also includes a clip bond 1232, which is preferably identical to clip bond 1231. [0046] Portions 1237 and 1238 of an electrically conductive adhesive are located adjacent to holes 1233 and 1234, respectively, of clip bond 1231. Portion 1238 of the electrically conductive adhesive electrically couples and adheres clip bond 1231 to bond pad 1121. Portion 1237 of the electrically conductive adhesive electrically couples and adheres semiconductor component 1300 to an external structure (not shown). Portions 1237 and 1238 of the electrically conductive adhesive are located at opposite sides of surfaces of clip bond 1231. [0047] Semiconductor component 1300 can also include a polyimide tape 1652 for securing ends of clip bonds 1231 and 1232. Component 1300 can also include an elastomer material 1651 located between semiconductor chip 1120 and polyimide tape 1652. Semiconductor component 1300 also includes an encapsulant or packaging material 1650. [0048] Therefore, an improved semiconductor component and method of manufacturing is provided to overcome the disadvantages of the prior art. The semiconductor component has a chip-to-lead frame interconnect system that has low parasitic conductances and resistances because of the use of clip bonds and the elimination of wire bonds. The method of manufacturing has low cost, has high throughput, and is compatible with small pitch interconnect schemes because of the use of clip bonds and the elimination of a solder reflow process. Although the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made without departing from the spirit or scope of the invention. For instance, the numerous details set forth herein such as, for example, the specific shapes, sizes, and configurations of the clip bonds are provided to facilitate the understanding of the invention and are not provided to limit the scope of the invention. Furthermore, the clip bonds described herein can be used in combination with wire bonds or other types of electrical interconnects. Accordingly, the disclosure of embodiments of the invention is intended to be illustrative of the scope of the invention and is not intended to be limiting. It is intended that the scope of the invention shall be limited only to the extent required by the appended claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8384228 *Apr 29, 2009Feb 26, 2013Triquint Semiconductor, Inc.Package including wires contacting lead frame edgeUS8486757Nov 25, 2009Jul 16, 2013Infineon Technologies AgSemiconductor device and method of packaging a semiconductor device with a clipUS8637977Jun 27, 2013Jan 28, 2014Infineon Technologies AgSemiconductor device and method of packaging a semiconductor device with a clip* Cited by examinerClassifications U.S. Classification257/784, 438/611, 257/E23.047, 438/119, 257/E21.514, 257/E23.046International ClassificationH01L23/495, H01L21/60Cooperative ClassificationH01L2924/14, H01L2924/0781, H01L23/49551, H01L2924/30107, H01L2224/838, H01L2924/01082, H01L2224/8319, H01L24/36, H01L24/39, H01L24/40, H01L24/83, H01L23/49548, H01L24/29, H01L2924/01033, H01L2224/2919, H01L2224/29101, H01L2924/0665, H01L2924/014European ClassificationH01L24/26, H01L24/39, H01L24/36, H01L24/40, H01L24/83, H01L23/495G4, H01L23/495G4BLegal EventsDateCodeEventDescriptionApr 24, 2014FPAYFee paymentYear of fee payment: 12Jul 9, 2012ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;REEL/FRAME:028510/0683Owner name: ADZUKI FOUNDATION PTE. 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