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BrowseUploadSign inJoinBooksAudiobooksComicsSheet MusicWelcome to Scribd! Start your free trial and access books, documents and more.Find out moreSAE STANDARD J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE2/15/94
1 1.1 1.2 2 2.1 2.2 2.3 2.4 2.4.1 2.4.2 3 3.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.3.3 3.4 4 4.1 4.2 4.2.1 4.2.2
OBJECTIVES AND SCOPE ............................................................................................................. 1 Objectives.......................................................................................................................................... 1 Scope................................................................................................................................................. 1 REFERENCES AND RELATED DOCUMENTS.............................................................................. 2 SAE Documents ................................................................................................................................ 2 ISO Documents ................................................................................................................................. 2 CISPR Documents ............................................................................................................................ 2 Definitions and Abbreviations ........................................................................................................... 2 Definitions .......................................................................................................................................... 2 Abbreviations / Acronyms ................................................................................................................. 4 DESCRIPTION OF THE ARCHITECTURE..................................................................................... 5 General .............................................................................................................................................. 5 Network Topology ............................................................................................................................. 5 Data Bus Topology............................................................................................................................ 5 Data Bus Control ............................................................................................................................... 5 References to the OSI Model ........................................................................................................... 5 Application Layer............................................................................................................................... 7 Data Link Layer ................................................................................................................................. 7 Physical Layer ................................................................................................................................... 7 Network Implementation ................................................................................................................... 7 APPLICATION LAYER DETAILS..................................................................................................... 9 Normal Vehicle Operation (Down the Road) Messages.................................................................. 9 Diagnostic Messages........................................................................................................................ 9 Diagnostic Parametric Data .............................................................................................................. 9 Diagnostic Malfunction Codes .......................................................................................................... 9
i 2/15/94
.....................4...................................................................................3........................................................... EOF................................4....................4.......... 10 Addressing Strategy........................................................................................................2....................................................2.................................................................3.........4......................................................... 12 Idle Bus (idle)................... 10 Physical Addressing.................................................1 5.................................5 5................................................................3................................................................. 10 Functional Addressing....................... 17 Concept of Valid / Invalid Bit / Symbol Detection ...1.. NB.............................. 9 DATA LINK LAYER DETAILS .3....................4 5.................3 5.................... 11 Frame Elements .........3................................................. 11 Function of SOF..............................3 5 5......................................................................................................3.......3 5............................................................................................................................................................6 5.............................................................................................5 5.... IFS.... 12 Break (BRK) ......... 11 End of Data (EOD) ....2 5........................................4..........................................................................................................7 5....................................3.....4
Frame Filtering .................................................................4.............. 12 Data Byte(s)......................................................................................1 5.................................................2 5................. 14 Error Detection ....................................3.......................3............................................2 5............ and BRK.............................4 5............................................ EOD..........4 5............................4....................................................1 5................................... 11 Maximum Frame Length ...........................1 5...3 5........................................................................7..............3............................. 12 Normalization Bit ....................................................................................................... 10 Network Access and Data Synchronization ...................................................................................................................2 5.. 14 Frame / Message Length ...........................................................................................................3.......................................... 14 Cyclic Redundancy Check (CRC) .........4.......................................2 5.......................................................................................................3..4...............3 5........ 12 In-Frame Response (IFR) ..1 5....... 11 Inter-Frame Separation (IFS)............ 11 Start of Frame (SOF) .........................................1.........................2 5...............................6 5.............................. 17 Out-of-Range.......................... 10 Full Message Buffering ...............1 5.......................3........ 12 Normalization Bit (NB).......................3....................................... 17
....................................................4................................... 11 Bit Ordering ........ 11 End of Frame (EOF)....................................................................................................................... 10 Network Elements and Structure..............1 5..................................4............... 10 Byte Buffering .........
........ 18 Physical Layer Media .....................................5.......................................................................................................6 6................................1 6......................................................................................1 6........................................... 18 Maximum Number of Nodes .............................1...... 19 The One "1" and Zero "0" Bits ...................................................4............................. 24 End Of Data (EOD) .............................................................6......................3 6......................................1............................................4 6..................6...........3 6........... 23 Start Of Frame (SOF).............1........6.............5 5.............................................1.......... 22 Idle Bus (Idle) .................................................................................................................................. 18 Pulse Width Modulation (PWM)...............2..........1.................................................................3
Invalid Bit Detection..................................................... 18 On-Vehicle / Off-Vehicle................4.......................................................................2 5................... 18 Single Wire .............. 24
iii 2/15/94
.......... 22 PWM Symbol Timing Requirements ... 18 Media Characteristics.................................................................................... 18 Routing ..1...........4.................................1........................................................................................ 20 End of Data (EOD) ...................................4 6.... 18 Unit Load Specifications.................................... 21 Break (BRK) .......2 6.2 6.............................................................................................................................................1.............................2 6 6.....................................................................5..........1.........6...................................1........................2 6..........................5 6.............................................. 21 Inter-Frame Separation (IFS)................................................... 17 Invalid Frame Structure Detection ...................................6...................6.............................6.............. 20 End of Frame (EOF).......................................................................................................4............................................................. 17 Transmit............................................................................................................................................................................6................................8 6.....1 6.....................................1 6.............................................................................................6.............................................2....1..........................................................5...............6................................................ 18 Data Bit / Symbol Definition / Detection............................................................................. 23 The One "1" and Zero "0" Bits ..............2 6......................................1 6..................1 5............1 6.......................5 6................................. 17 Receive.......................................................................................................................................... 17 Error Response .... 18 Dual Wires ................... 19 Start of Frame (SOF) ......4...................................3 6......................6........................................................................................................................................2 6...................... 18 Maximum Network Length ....................... 17 PHYSICAL LAYER DETAILS .....6......................... 23 Variable Pulse Width Modulation...............................................................1 5...............6.......6 6.......2...........................................................................7 6.....................
........................................1 7............................. 24 Inter-Frame Separation (IFS)............................................................................. 33 Pulse Width Modulation (PWM) at 41....................................................1....................2 6..............9 6............................................................................7............................... 29 Node Wake-Up Via Physical Layer ................................................8 6......... 30 Biased Network ....................................2.............................4 Kbps .6......................2.................................................................................................................................................................6...............................................................................1 7.1 6...................................5 6.......................1 6...7....7 6.................................... 33 Data Link Layer ....................8................ 26 VPW Symbol Timing Requirements ............................................................. 30 Sleeping Node...6...............................................................................................................8........... 33
............ 27 Contention Detection....................................................1...........9 6.........................................................................................2.....................................................................6....2...............................................................2 6..........3 6............ 26 Idle Bus (Idle) ............................ 29 Frame Priority ...................................................................................... 33 Variable Pulse Width (VPW) at 10.......... 25 Break (BRK) .......... 30 Individual Nodes............................................2............................2..1 6.................... 29 Network Media .....8 6.............2
End of Frame (EOF)....6 6............................................... 30 Awake / Operational..................2 6.......................9................................................................6...8................................................ 30 Required Fault Tolerant Modes ........................................................................................................... 30 Physical Layer Fault Considerations ......... 26 Contention / Arbitration / Priority ......................4 6...........................................................10 7 7............................................................2...............2 6....8.......................2 6.............2............ 30 Optional Fault Tolerant Modes ...................................................2.....................7 6.......... 27 Arbitration Area.......................................................2 7.................................................. 30 Unbiased .....................................................6..................................................................................................................................................................4 6............................................................................... 27 Bit-by-Bit Arbitration ...................................................... 33 Application Layer........................8...........................2.....2.................................6 Kbps ........8............................ 31 EMC Requirements................7...............................9.............7...................................................................1 6................................1 6... 30 Unpowered Node ........................................6................... 31 PARAMETERS................................. 24 In-Frame Response Byte(s) / Normalization Bit.......8......................................................................................................................3 6..................................................................................................................
........................2 7.1 7................................................................................................ 34 PWM DC Parameters .2..................3........................................................3 7........PWM WAVEFORM ANALYSIS .................................................1 7....7..........3...... 33 Pulse Width Modulation (PWM)....................................................... 34 PWM Timing Requirements...................................... 37 VPW DC Parameters .............3..............VPW WAVEFORM ANALYSIS.........................................................1 7.........3..................................... C1 APPENDIX D ...........3....................2
Physical Layer .....................................I/O EMC TEST PLAN .........................2................ B1 APPENDIX C .....................CHECKLIST OF APPLICATION SPECIFIC FEATURES ....................................................................................................................................... 36 Variable Pulse Width Modulation (VPW)................................... 37 VPW Timing Requirements ........3................................ 38
APPENDIX A ............................................................3....................... D1
...................3 7............ 33 General Network Requirements .........................2 7............................................................3.......................................................................................................................... A1 APPENDIX B ...................................................................................3..............
1 OBJECTIVES AND SCOPE 1.1 Objectives - This document constitutes the requirements for a vehicle data communications network. These requirements are related to the lowest two layers of the ISO Open System Interconnect (OSI) model (Ref. ISO 7498). These layers are the Data Link Layer and the Physical Layer. This network has been described using the ISO conventions in ISO/TC 22/SC 3/WG1 N429 E, dated October, 1990. Both documents are intended to describe the same network requirements but using different descriptive styles. If any technical differences are identified, the very latest revision of these documents should be used. This is an SAE Recommended Practice which has been submitted as an American National Standard. As such, its format is somewhat different from the formal ISO description in that descriptions have been expanded, but are in no way less precise. A more textual format has been adopted herein to allow explanations to be included. The vehicle application for this class of data communication (Class B) network is defined (Reference SAE J1213 APR88) to allow the sharing of vehicle parametric information. Also per the definition, this Class B network shall be capable of performing Class A functions. 1.2 Scope - This document establishes the requirements for a Class B Data Communication Network Interface applicable to all On and Off-Road Land Based Vehicles. It defines a minimum set of data communication requirements such that the resulting network is cost effective for simple applications and flexible enough to use in complex applications. Taken in total, the requirements contained in this document specify a data communications network that satisfies the needs of automotive manufacturers. This specification describes two specific implementations of the network, based on media / Physical Layer differences. One Physical Layer is optimized for a data rate of 10.4 Kbps while the other Physical Layer is optimized for a data rate of 41.6 Kbps (see Appendix A for a checklist of application specific features). Although devices may be constructed that can be configured to operate in either of the two primary implementations defined herein, it is expected that most manufacturers will focus specifically on either the 10.4 Kbps implementation or the 41.6 Kbps implementation depending on their specific application and corporate philosophy toward network usage. However, low volume users of network interface devices are expected to find it more effective to use a generic interface capable of handling either of the primary implementations specified in this document. This SAE document is under the control and maintenance of the Vehicle Networks for Multiplexing and Data Communications (Multiplex) Committee. This committee will periodically review and update this document as needs dictate.
2 REFERENCES AND RELATED DOCUMENTS 2.1 SAE Documents J1113 J1211 J1213/1 J1547 J1879 J1930 J1962 J1979 J2012 J2178/1 J2190 2.2 AUG87 Electromagnetic Susceptibility Components Measurements Procedures for Vehicle
NOV78 A Recommended Environmental Procedure for Electronic Equipment Design APR88 Glossary of Vehicle Communications Networks for Multiplexing and Data
OCT88 Electromagnetic Susceptibility Measurement Procedures for Common Mode Injection OCT88 General Qualification and Production Acceptance Criteria for Integrated Circuits in Automotive Applications SEP91 JUN92 DEC91 Electrical/Electronic Systems Diagnostic Terms, Definitions, Abbreviations, & Acronyms Diagnostic Connector E/E Diagnostic Test Modes
MAR92 Diagnostic Codes/Messages JUN92 JUN93 Class B Data Communication Network Messages Enhanced E/E Diagnostic Test Modes
ISO Documents ISO/TC22/SC3/WG1 Road Vehicles - Serial Data Communication for Automotive N429E OCT. 90 Applications, Low Speed (125 Kbps and Below) ISO 7498 Data Processing Systems - Open Systems Interconnection - Standard Reference Model
CISPR Documents CISPR/D/WG2 (Secretariat) 19 Sept 1989 Radiated Emissions Antenna and Probe Test
Definitions and Abbreviations Definitions Active State - The state of a bus wire which results when one or more nodes have "turned on" their physical layer circuitry. This is Voh volts for Bus + (PWM and VPW) and Vol volts for Bus (PWM only). Refer to Tables 4 (PWM DC Parameters) and 6 (VPW DC Parameters) for the values of Voh and Vol. The active state voltage level is determined by the source voltage of the physical layer drive circuitry.
A bit which wins arbitration when contending for the bus. Class A Data Communications ." For this network. Dual Wire .
. parametric data values) is transferred between nodes to eliminate redundant sensors and other system elements.The state of a bus wire which results when all nodes have "turned off" their physical layer circuitry.. This is Vol volts for Bus + (PWM and VPW) and Voh volts for Bus .1 for an example of the typical usage for physical addressing. A Class C network shall also be capable of performing Class A and Class B functions. continues to be transmitted when two or more nodes begin transmitting frames.A system whereby vehicle wiring is reduced by the transmission and reception of multiple signals over the same signal bus between nodes that would have been accomplished by individual wires in a conventionally wired vehicle. A frame is delineated by the Start of Frame (SOF) and End of Frame (EOF) symbols. Class B Data Communications . which may or may not include an "in-frame response. The passive state voltage level is determined by the reference voltage of the bus wire termination resistor(s).The ability of a system to survive a certain number of failures with allowance for possible down-graded performance while maintaining message transmission capability at the specified data rate. Dominant Bit . simultaneously.A system whereby high data rate signals typically associated with real time control systems.1.One complete transmission of information. Pulse Width Modulation (PWM) . Class C Data Communications .(PWM only).All of the data bytes contained in a frame.Two wires that are routed adjacently throughout the network and can be either a twisted or a parallel pair of wires. As such. A Class B network shall also be capable of performing Class A functions. a logic "0" is the dominant bit. are sent over the signal bus to facilitate distributed control and to further reduce vehicle wiring. The nodes in this form of a multiplex system typically already existed as stand-alone modules in a conventionally wired vehicle. The message is what is left after the frame symbols have been removed from the frame.g.A data bit format. For SAE J1850. Functional Addressing . or In-Frame Response data. Message . Fault Tolerance . each frame contains one and only one message. The nodes used to accomplish multiplexed body wiring typically did not exist in the same or similar form in a conventionally wired vehicle.1.2 for an example of the typical usage for functional addressing. where the width of a pulse of constant voltage or current determines the value (typically one or zero) of the data transmitted. or In-Frame Response data. Frame .Labeling of messages based on their operation code or data content.The process of resolving which frame. such as engine controls and anti-lock brakes. See paragraph 5. Refer to Tables 4 (PWM DC Parameters) and 6 (VPW DC Parameters) for the values of Voh and Vol. Passive State .Arbitration .A system whereby data (e. Physical Addressing . the message is the sequence of bytes contained in the frame. See paragraph 5.Labeling of messages for the physical location of their source and/or destination(s).
Variable Pulse Width (VPW) Modulation . This encoding technique is used to reduce the number of bus transitions for a given bit rate. a logic "1" is the recessive bit.Node behavior in a low power consumption standby state waiting to be switched on by a frame or other activity. Sleep-Mode .Recessive Bit . One embodiment would define a "ONE" (1) as a short active pulse or a long passive pulse while a "ZERO" (0) would be defined as a long active pulse or a short passive pulse. general byte or frame times cannot be predicted in advance.A method of using both the state of the bus and the width of the pulse to encode bit information.4. For SAE J1850.A bit which loses arbitration when contending for the bus with a dominant bit. 2.2 Abbreviations / Acronyms BRK: Break CRC: Cyclic Redundancy Check E/E: Electrical and Electronic EMC: Electromagnetic Compatibility EMI: Electromagnetic Interference EOD: End of Data EOF: End of Frame IFR: In-Frame Response (Byte/Bytes) IFS: Inter-Frame Separation ISO: International Standards Organization Kbps: Kilo bits per second NA: Not Applicable NB: Normalization Bit OSI: Open System Interconnect SOF: Start of Frame
. This is distinct from an off mode where the node is disconnected from the power supply. Since a frame is comprised of random 1's and 0's.
All nodes/devices receive all frames at the same time. c. In order to support an open architecture approach.1 Network Topology Data Bus Topology . A single-level bus topology. An open architecture network is one in which the addition or deletion of one or more modules (data nodes) has minimal hardware and/or software impact on the remaining modules. references are included for the application layer since this needs to be included for emission related.2. this Class B network is intended for "masterless" bus control.2 3. This also implies that frame/data contention will not result in lost data. Two disadvantages of the masterless bus concept are that data latency cannot be guaranteed. 3. the requirement to use multiple buses for redundancy purposes does not change the single-level bus topology definition if the following criteria are maintained: a.1 General . The principal advantage of the masterless bus control concept is its ability to provide the basis for an open architecture data communications system.It is the intent of this network to interconnect different electronic modules on the vehicle using an "Open Architecture" approach. This "mapping" is illustrated in Figure 1. References to the OSI Model . the Class B network utilizes the concept of Carrier Sense Multiple Access (CSMA) with non-destructive contention resolution. It includes all nodes and data buses involved in the data bus integration of the vehicle. prioritization of frames is allowed and the highest priority frame will always be completed. Since a master does not exist. in the case of contention. is currently being used in several automotive applications. However. Additionally this network supports the prioritization of frames such that. All nodes/devices transmit and receive from a single path. all nodes are interconnected via the same data bus.Although various methods of data bus control can be used. not all nodes and/or data are of equal importance. In a single-level bus topology.3 DESCRIPTION OF THE ARCHITECTURE 3. except for the single highest system priority frame. the simplest bus topology. However. Communication on each data bus is identical. diagnostic communication legislation requirements. The Class B network maps into the OSI model as described in the following paragraphs.2. and bus utilization extremes are difficult to evaluate. 3.Although this document focuses on the data link layer and the physical layer. The redundancy requirements of a particular application may require a single-level topology to be implemented using multiple interconnecting cables operating in various modes (active or passive).2 Data Bus Control . each node has an equal opportunity to initiate a data transmission once an idle bus has been detected. the higher priority frames will always win arbitration and be completed.3
3.Data bus topology is the map of physical connections of the data bus nodes to the data bus.
Map of SAE J1850 to the ISO OSI Model
Figure 4 shows the specific bit assignments for priority.The primary function of the Data Link Layer is to convert bits and/or symbols to validated error free frames/data. The consolidation of messages has been documented in SAE J2178. An important additional service provided by the Data Link Layer is error checking. Physical Layer .1
Application Layer . messages and tools. This layer establishes the relationship between the various application input and output devices. This layer documents the high level description of the function including control algorithms if appropriate. "Pressing the head lamp button shall cause the low beam head lamp.4
Message ID (256)
One Byte Form of Consolidated Header: Bit 7 x 6 x 5 x 4 H=1 3 x 2 x 1 x 0 x
Message ID (128) FIGURE 2 . and Functional / Physical Address mapping in the three byte header format. they may be corrected or higher layers may be notified. Figure 3 shows the three byte header form.3. voltage/current levels. which previously had been optional. Typical services provided are serialization (parallel to serial conversion) and clock recovery or bit synchronization. Figure 2 shows the general format for single byte header forms. including what is expected of human operators. For a complete description of the "KYZZ" bits shown in Figure 4 refer to SAE J2178/1.The Physical Layer and its associated wiring form the interconnecting path for information transfer between Data Link Layers. marker and tail lamp filaments to be energized. media impedance. Network Implementation .3
3. These header bytes fully define the associated requirements of this network interface. Single Byte Header: Bit 7 6 5 4 3 2 1 0
3." Legislated diagnostics is another area in which application layer requirements need to be specified. The first byte or the first three bytes of these messages are called the "Header" byte(s).2
3.Single Byte Header & One Byte Form of Consolidated Header
. Typical Physical Layer protocol elements include.3.At the top of the OSI reference model is the Application Layer. software. An example of an Application Layer functional description might be. and bit/symbol definition and timing.3.3. In-Frame Response. Data Link Layer .The network implementations based on this document have been reduced to commonize hardware. When errors are detected.
Three Byte Form of Consolidated Header Byte 1 of Three Byte Form of Consolidated Header: Bit 7 P 6 P Priority (0 to 7) 5 P 4 0 H=0 3 K 2 Y 1 Z 0 Z
Message Type (see below)
Bit K Y ZZ
Meaning In-Frame Response (IFR) Addressing Mode Specific Message Type
Value 0 1 0 1 00 01 10 11
Meaning IFR Required IFR Not Allowed Functional Addressing Physical Addressing The meaning for these values are dependant on K & Y above.Three Byte Form of Consolidated Header: Byte 1 See Figure 4 Below Byte 2 Target Address Byte 3 Source Address
FIGURE 3 .First Byte of Three Byte Form of Consolidated Header
. These meanings can be found in J2178/1.
Manufacturer specific test procedures utilizing this network may specify procedures that do not conform to the requirements of this recommended practice. Legislated diagnostics. 4. Regardless of the exact technique used for frame filtering.
4. SAE J1979 and SAE J2190 messages conform to the requirements and limitations of this document. Diagnostic Messages .2. Frame Filtering . SAE J1979 and SAE J2190 define the set of recognized test modes that are available and have been reserved for diagnostic purposes. and some level of voluntary industry standard diagnostics.1 below).g. SAE defined messages and the "Reserved" messages of SAE J2178 shall remain specific to those definitions.1 Normal Vehicle Operation (Down the Road) Messages . the criteria for these filtering operations may include multiple byte comparisons occurring over the first several frame bytes. the code structure of SAE J2012 should be used.It is expected that this network will be used for diagnostics of the devices utilizing the network. 4.1 Diagnostic Parametric Data . In SAE J2178. This transfer of information supports both operational and diagnostic needs.SAE J2012 defines trouble codes to be assigned to various vehicle system malfunctions.4 APPLICATION LAYER DETAILS The application of this communication network is the transfer of information from one node of the network to one or more other nodes. the objective is to reduce the software and processing burden associated with network operations by limiting the number of received frames to just those necessary for any given node. SAE has developed documents describing each of these types of applications. there is also a set of "Reserved . see Paragraph 5.3
. When trouble codes are to be assigned to system malfunctions. and also assigns ranges of codes to be used for manufacturer specific codes. will have meanings specific to a vehicle manufacturer but are likely to be different between manufacturers.2
4. Because this Class B protocol may use more than one type of frame addressing (e.2
4.Manufacturer" messages which. industry standard diagnostics. SAE J1979 and SAE J2190 includes messages to be used to retrieve these codes from the on-vehicle systems. These normal vehicle operation messages are used for communication from a transmitter to one or more receivers across this network. if used.SAE J1979 and SAE J2190 define test modes and frame formats for use by off-vehicle test equipment to obtain diagnostic data from the vehicle. that reference this recommended practice.. or manufacturer specific diagnostic procedures. consistent with this document. should only specify procedures and frames that conform to this recommended practice. The normal operation messages have been developed by the SAE for this communication network and are defined in SAE J2178. functional and physical.2. Diagnostic Malfunction Codes .The network interface device may be capable of filtering frames on the network to select those appropriate to a given node.The messages sent during nondiagnostic operations are called normal vehicle operation messages. These diagnostic procedures may include legislated diagnostics.
Functional Addressing . Each node must be assigned a unique physical address within the network. The controlling device is responsible for the timely servicing of the interface device to keep up with frame traffic.Two types of addressing strategies are defined and can coexist on this network.Frames are exchanged only between two devices based on their "Physical" address within the network. c.5 DATA LINK LAYER DETAILS This section defines the requirements on the following Data Link Layer attributes: a. Message filtering (or screening) is possible in such a device which reduces software burden even further. Physical Addressing .2. Network Access and Data Synchronization .6.1. The two strategies serve different types of tasks and the flexibility to use both types on the same network provides a major benefit. Byte Buffering . Diagnostic access would be one case where identification of a specific module is important.2
5. the function of the message is important and not the physical addresses of the nodes. node synchronization can be derived from bit/symbol transitions on the bus. This approach reduces software burden at the expense of hardware costs. Since a discrete clock wire is not used with this network.7.2. e. This type of addressing strategy is used when the communications involve specific nodes and not the others that may be on the network.The network interface shall implement a multiple access arbitration based protocol using nondestructive bit-by-bit arbitration to transparently resolve simultaneous access to the bus. either as transmitter or receiver. 5.1 Addressing Strategy Network Access and Data Synchronization Frame Elements and Structure Error Detection Error Response
Addressing Strategy . Network access is allowed after detection of an idle bus.1.1
Full Message Buffering .
5. d. b.1.
5. Each node is assigned the set of functions that it cares about.Each byte of a received message (or transmit message) is stored individually in the interface device.2
5.One or more messages exist in their entirety in the interface device. In the case of functional addressing. and can be located anywhere in the network. This type of addressing strategy is used when the physical location of the function is not important but could move around from one module to another. The definition of an idle bus is contained in Paragraph 6.2
5.Frames can be transmitted between many devices based on the function of that frame on the network.
if used. then the bus would remain in the passive state thereby resulting in an End of Frame (EOF). idle: The preceding acronyms are defined as follows: idle:Idle Bus (occurs before SOF and after IFS) SOF: Start of Frame DATA: Data bytes (each 8 bits long) EOD: End of Data (only when IFR is used) CRC: CRC Error Detection Byte (may occur in IFR as well) NB: Normalization Bit (10.3. EOF. Maximum Frame Length .7) is not used.2. and BRK . the originator of the frame will expect the recipient(s) of the frame to drive the network with one or more in-frame response bytes immediately following EOD. DATA_N. End of Data (EOD) . IFR) frame delimiter symbols are defined to allow the data bus to function properly in a multitude of different applications.3
. An overview of these symbols is provided here..3. Function of SOF. and BRK will be byte oriented and must end on byte boundaries. End of Frame (EOF) .. IFS.3.4.3 Start of Frame (SOF) .The maximum number of continuous bit times that a single node is able to control the bus shall not exceed the value specified in Section 7.1 5. NB. IFR_1. MSB first). all receivers will consider the transmission complete.e.
5. EOD.3..4 Kbps only) IFR: In-Frame Response Byte(s) EOF: End of Frame IFS:Inter-Frame Separation Note: Break (BRK) can occur (be sent) on a network at any time.
5. EOF.End of Data (EOD) is used to signal the end of transmission by the originator of a frame.3. CRC.3.4.. NB. SOF.1 5.The first bit of each byte transmitted on the network shall be the most significant bit (i. CRC.e.5. After the last transmission byte (including in-frame response bytes where applicable). Detailed timing requirements on each symbol can be found in Section 7.3
Network Elements and Structure The general format is: idle. data.4.3 5.2
5. When EOF has expired. If the IFR feature (see Paragraph 5..The SOF mark is used to uniquely identify the start of a frame. If a frame includes an IFR..The completion of the EOF defines the end of a frame. Each byte will be 8 bits in length.The frame elements other than the symbols SOF. the bus will be left in a passive state. IFR_N. EOF. EOD. NB.3. . IFS. EOD.3.4
Frame Elements . DATA_0. The SOF mark shall not be used in the calculation of the CRC error detection code.In addition to actual data bytes (i. The in-frame response (IFR) section of the frame. IFS.. begins after the EOD time but before the EOF. . Bit Ordering ..2 5.
Arbitration takes place during the response process so that each recipient.Idle bus is defined as any period of passive bus state occurring after IFS. A single byte transmitted from a single recipient. In-frame response bytes may take one of the following forms (refer to Figure 5): a.3. In-Frame Response (IFR) . Contention may still occur when two or more nodes transmit nearly simultaneously.7
d. it discontinues the transmission process to allow any remaining responders to transmit their byte. then the originator and all receivers must consider the frame complete. EOF minimum has expired and another rising edge has been detected.3. receivers must synchronize to any other SOF occurring after the EOF minimum period in order to accommodate individual clock tolerances.For Variable Pulse Width Modulation. Once a given recipient observes its own unique response byte.5. all from a single recipient. If BRK is used.4. therefore.6
5. c. except only the data in the response is used for the CRC calculation.2.BRK is allowed to accommodate those situations in which bus communication is to be terminated and all nodes reset to a "ready-to-receive" state. However. the total message length (from SOF to EOF) shall not exceed the limit defined in Section 7. Multiple bytes.4
Inter-Frame Separation (IFS) . A CRC byte may be appended to the data byte(s). Idle Bus (idle) .
.6.A number of data bytes. b.5
Normalization Bit (NB) . The CRC byte is calculated as described in Paragraph 5. This Normalization Bit shall define the start of the in-frame response. The effect is to concatenate the individual response bytes into a response "stream". it must adhere to the requirements as specified in Section 6.For In-Frame Response.6
5. re-synchronization to rising edges must continue to occur. However. Data Byte(s) . each eight (8) bits in length. typically a unique identifier (ID) or address. The response byte from each recipient must be unique. The Normalization Bit is defined in Paragraph 6.4 Kbps implementation . a single byte transmitted from each recipient.3. the first bit of In-Frame Response data is also passive and therefore it is necessary to generate a Normalization Bit to follow the EOD symbol.4.1. Break (BRK) . A transmitter must not initiate transmission on the bus before the completion of the IFS minimum period. will retransmit the single byte until the recipient observes its unique byte in the response stream.4.3.4. any node may transmit immediately. A transmitter that desires bus access must wait for either of two conditions before transmitting a SOF: a.3. if arbitration is lost during its response byte. typically a physical address (ID n). If the first bit of the in-frame response byte does not occur at this point and the bus remains passive for a period of time defined as EOF.5. can be transmitted at the discretion of the system designer.Inter-Frame Separation is used to allow proper synchronization of various nodes during back-to-back frame transmissions. the response byte(s) are transmitted by the responders and begin after EOD. One or more data bytes.
5. During an idle bus.3.2.
5.6. IFS minimum have expired.Only applicable to 10. None b.
Refer to SAE J2178/1 for a detailed discussion of the different IFR types and for determination of which message types utilize which IFR types. CRC bytes.2.
FIGURE 5 . If in-frame response bytes are used. the overall frame / message length limit remains in effect.Types of In-Frame Response
. and in-frame response bytes shall not exceed the frame length as specified in Section 7. The sum total of data bytes.
g. h. The Remainder Polynomial R(X) is determined from the following Modulo 2 division equation:
____ ____ e.5. Error Detection . f. In general. The CRC calculation and the CRC checker shift registers (or memory locations) will be located in the sender and receiver nodes. Cyclic Redundancy Check (CRC) . This polynomial is designated as P(X).6. the action taken after an error condition has been detected is manufacturer specific unless it has been specified in this document.) b. The Normalization Bit is described in Paragraph 6.3. Examples of frames with the appropriate CRC bytes are listed in Table 1. A status flag may be used to indicate the occurrence of a received CRC error. counted in bits. The CRC byte is made equal to R(X). An invalid CRC byte may constitute a detected error. where n is equal to the frame length.5.4 Kbps implementation then a "Normalization Bit" is required. All frame bits that occur after SOF and before the CRC field are used to form the Data Segment Polynomial which is designated as D(X).2. and shall be initially set to the "all ones" state during SOF. including the transmitted CRC byte.7. (The setting to "ones" prevents an "all zeros" CRC byte with an all zero data stream. The CRC division polynomial is X + X + X + X + 1.If the In-Frame Response is employed in the 10.The error descriptions in this document are loosely defined and classified.1 5.The CRC is required with either of the header byte systems used. where R(X) is the ones complement of R(X).
Q(X) is the quotient resulting from the division process. through the CRC checker circuit. The method of calculating and checking the CRC byte is defined below.
. respectively. The receiver checking process shifts the entire received frame. a. An error free frame will always result in the 7 6 2 unique constant polynomial of X + X + X (C4 hex) in the checker shift register regardless of the frame content.4. For any given frame. this number can be interpreted as an "n-bit" binary constant. The Frame Polynomial M(X) that is transmitted is:
Install Equation Editor and doubleclick here to view equation. i.
Normalization Bit .
. the previous rules are used to define the CRC. the two circuits may be combined to use only a single shift register for both CRC generation and CRC checking. (Note that the SOF.
When In-Frame Response data is protected by a CRC field. except that the sender and receiver nodes are interchanged.j. EOF. and NB are not used in the CRC calculation and serve as data delimiters. With appropriate gating.Examples of Frames & Appropriate CRC Bytes Data Bytes (hex) 00 F2 0F 00 33 92 FF 00 01 AA FF 22 6B FF 00 83 00 55 55 55 FF FF 55 11 AA BB CC DD EE FF 00 CRC (hex) 59 37 79 B8 CB 8C 74
Note: Figure 6 illustrates a typical CRC generator and Figure 7 illustrates a typical CRC checker. The CRC calculation only includes the in-frame response bytes.)
FIGURE 6 .CRC Generator
FIGURE 7 .CRC Checker
Out-of-Range . Receive .4.
5. Error Response Transmit .4).2
.5 5. Data is recovered by holding the receiver output in the state it was prior to the out-of-range condition for the duration of the interference. one of the error conditions defined in paragraph 5.Regardless of data encoding. After the specified period of IFS or reception of an edge after EOF.If a frame is received which contains an error (i.4.5.e..2
5. may be detected by an out-of-range detector.4. This out-of-range condition.4.4).e. the receiver must not respond to a received frame containing an error. data integrity may be increased by detecting the condition when an EOD or EOF occurs on a non-byte boundary within the data stream. This may constitute a detected error.A frame exceeding its defined length limit may constitute a detected error.4. The following defines the operation of an out-of-range detector: a. one of the error conditions defined in paragraph 5.In some cases. If "In-Frame Response" is being used.4.5. b. This lack of response serves as a signal to the originator that an error was detected by the receiver.4.Data is corrupted in a vehicle network when transient interference is large enough to drive the receiver out of its dynamic range of operation.4 5. the originator is allowed to retransmit the frame. data integrity may be increased by detecting the condition in the data stream where the received data bit does not match the specifications for either a "one" or a "zero" bit.1
Concept of Valid / Invalid Bit / Symbol Detection Invalid Bit Detection .When an originator of a frame detects an error condition on the network (i. or the frame exceeds the maximum frame length.3
Frame / Message Length .
5. If the interfering transient is long enough to corrupt a desired bus symbol. Invalid Frame Structure Detection . the originator must discontinue the transmit operation prior to the start of the next bit.1
5. accurate data recovery may not occur..5. the frame is to be ignored.2 5. where the receiver can no longer accurately decode the data.
will allow the maximum specified number of nodes to be connected to the network. Single Wire .Although this specification focuses on the data carrying media. A unit load is a nominal value which. c.1. Routing . 6.5 6. but the combination of all load values must not exceed the limits for any given system. a rising edge is a transition from the passive to active state.The network medium for the single wire voltage drive shall be a single random lay wire. Dual Wires .1 6. For clarity in the following sections. h. Media Unit Load Specifications Maximum Number of Nodes Maximum Network Length Media Characteristics Data Bit/Symbol Definition/Detection Network Wake-Up Via Physical Layer Physical Layer Fault Considerations EMC Requirements
Specific parametric values associated with the physical layer are contained in Section 7.The electrical loading effect of each device connected to this network will be measured in terms of unit loads. Maximum Network Length .No Restrictions Unit Load Specifications . f. There is no requirement that a given node must be equal to a standard unit load. the allowed maximum on-vehicle loads shall be limited to account for this level of off-vehicle loading.6 PHYSICAL LAYER DETAILS This section defines the requirements on the following physical layer attributes: a.6
.3. or a twisted pair of wires.
6. d.The maximum number of nodes. is specified in Section 7.The network medium for the dual wire voltage drive shall be either a parallel wire pair separated by a constant distance.1. Because all applications must allow for such off-vehicle equipment. b. Data Bit / Symbol Definition / Detection .1. g. Maximum Number of Nodes .The data bus can be in one of two valid states. maximum capacitance value and minimum load / termination resistance values for any off-vehicle equipment have been specified in Section 7.4.1
6.The maximum network length.1 6. it is assumed that each node shall be supplied with appropriate power and ground. i. if all nodes correspond to one unit load. Media Characteristics .2 Physical Layer Media . e.2 6. On-Vehicle / Off-Vehicle .3 6.The maximum medium length between any two nodes shall not exceed the value specified in Section 7. assuming each node is the equivalent of a standard unit load.The characteristics of the media are as specified in Section 7.3 6. active or passive.4 6. and a falling edge is a transition from the active to the passive state.
The following values represent nominal timing. One "1" bit Zero "0" bit Start of Frame (SOF) End of Data (EOD) End of Frame (EOF) Inter-Frame Separation (IFS)
The Normalization Bit (NB). 6.e. The timing diagrams that follow represent the requirements for the logical waveform. The requirements associated with the reception of these bits and symbols are not stated explicitly in this specification.6. In some contention situations. b. Two rising edges shall never be closer than Tp3. meets these specifications).
│<───────── Tp3 ──────────>│<─ Tp1─>│ │ │ │ ┌────────┐ ─ ─ ─ ─┐ ┌────────┐ ┌───── │ │ │ │ │ │ Passive ────────┘ └─ ─ ─ ─ └────────┘ └────────│────────┘ │ │ │ │<────── Previous Bit─────>│<──────── "1" Bit ───────>│ or Mark Active
FIGURE 8 .A "1" bit is characterized by: (1) A rising edge that follows the previous rising edge by at least Tp3. The One "1" and Zero "0" Bits (See Figures 8 and 9): a.1 Pulse Width Modulation (PWM) . Pulse Width Modulation (PWM) and Variable Pulse Width (VPW) modulation.1. It is expected that the receiver will employ a simple clock-driven digital filter and digital integrator or majority vote sampling circuit for decoding data and maintaining "clock" synchronization. It is the transmitter's responsibility to transmit bits / symbols which are valid (i. All timing requirements are specified in Section 7. d.1 6. c. the transmitter will have to re-synchronize to ensure that the falling edge is within specification.There are two methods of bit encoding specified in this document. (2) A falling edge that occurs Tp1 after the rising edge. detailed timing requirements for each bit/symbol can be found in Section 7. is only applicable for VPW implementations and is therefore only defined for VPW. e.6. but are to be derived from transmitter specifications by the module or circuit designer. The following bits/symbols are defined for both PWM and VPW: a. "1" Bit .. f."1" Bit Definition
1."0" Bit Definition 6. A reference rising edge that follows the previous rising edge by at least Tp5. The SOF is characterized by: a.
. begins immediately after the EOD bit (see Figure 11).6. or last In-Frame Response bit. The In-Frame Response (IFR) section of the frame. c.The Start of Frame (SOF) mark has the distinct purpose of uniquely determining the start of a frame (see Figure 10). The rising edge of the first data bit will occur at Tp4 after the reference rising edge. last CRC bit.3 End of Data (EOD) . b.
│<────────────── Tp6 ──────────────>│<───── Tp4 ─────>│ │<───────── Tp5 ──────────>│ │<── Tp7 ──>│ │ │<───── Tp4 ─────>│ │ │ │ │ │ │ │ ┌──┐ ─┐ ┌──┬──┬──│──┐ ┌──┐ ─┐ ┌─ │ │ │ │ │ │ │ │ │ ───┘ └──┴──│──┴──┴──│──┴──┴──│──┴──┴──┘ └──┴──┘ └──┴──┘ ∧ │ ─┘ ∧ │ EOD ∧ │ EOF ∧ │ IFS ∧ │ SOF
Last Bit of Frame
FIGURE 10 . 6.6. If the In-Frame Response feature is not used.1. Two rising edges shall never be closer than Tp3. (2) A falling edge that occurs Tp2 after the rising edge. A falling edge that occurs Tp7 after the reference rising edge. then the bus would remain in the passive state for an additional bit time. "0" Bit .End of Data is used to signal the end of transmission by the originator of a frame.A "0" bit is characterized by: (1) A rising edge that follows the previous rising edge by at least Tp3.2 Start of Frame (SOF) .Frame Symbols Note: Last bit of a frame may be the last data bit.
│<───────── Tp3 ──────────>│<───── Tp2 ─────>│ │ │ │ ┌────────┐ ─ ─ ─ ─┐ ┌────────│────────┐ ┌───── │ │ │ │ │ │ Passive ────────┘ └─ ─ ─ ─ └────────┘ └────────┘ │ │ │ │<────── Previous Bit─────>│<──────── "0" Bit ───────>│ or Mark Active
FIGURE 9 .b. if used. thereby signifying an End of Frame (EOF).
all receivers will consider the transmission complete. or last In-Frame Response bit. an EOD forms the first part of the EOF . the response byte(s) are driven by the responders and begin with the rising edge of the first bit of the response. EOD has been transformed into an EOF). A transmitter that desires bus access must wait for either of two conditions before transmitting a SOF: a.4 End of Frame (EOF) .
6. last CRC bit.End of Data Symbol Note: Last bit of a frame may be the last data bit.1. │<─────── Tp4 ─────────>│ │ │ ┌───┐─ ─┐ ┌───┐─ ─┐ ┌─── │ │ │ │ │ │ │ ──┘ └───┴───│───┴───┴───┘ └───┴───┘ ∧ │ ─┘ ∧ │ EOD ∧ │ └─ First In-Frame Response Bit
FIGURE 11 .The completion of the EOF defines the end of a frame (by definition. IFS minimum has expired (Tp6 after the rising edge of the last bit).1. If the first bit of the response byte does not occur at Tp4.6.e. Inter-Frame Separation (IFS) . EOF minimum and another rising edge has been detected. After the last transmission byte (including inframe response bytes where applicable).(Tp5 after the rising edge of the last bit).For In-Frame Response.Inter-Frame Separation allows proper synchronization of various nodes during back-to-back frame operation. When EOF has expired (Tp5 after the rising edge of the last bit). and the bus remains passive for one additional bit time (total time Tp5) then the originator and all receivers must consider the frame complete (i..6. Tp4 after the rising edge of the last bit sent from the originator of the frame.see Figure 13). 6. b. the bus will be left in a passive state.5
other frames may gain access under the normal rules of arbitration.1. the highest priority frame must then be sent. which will then ignore the current frame. may initiate│ │ │ │ │<──┤ transmission any time. Following the break symbol. therefore. │<───────────── Tp6 ───────────────>│ │<───────── Tp5 ──────────>│ │ │<───── Tp4 ─────>│ │ │ ┌───────────────────────┐ ┌──┐ ─┐ │ Idle bus.PWM Break Sequence
6. last CRC bit. any node may transmit immediately.6. If the "Breaking" device wishes to obtain guaranteed access to the bus. if any. otherwise.Idle bus is defined as any period of passive bus state occurring after IFS minimum (see Figure 13). │<──────────────────── Tp9 ─────────────────>│<───── Tp4 ─────>│ │<─────── Tp4 ───>│ │ │ │<─── Tp8 ────>│ │ │ │ ┌──┬──┬──┼──┬──┐ ┌──┬──┬──┼──┐ ┌─ │ │ │ │ │ ───┘ └──│──┴──┴──│──┴──┴──│──┴──┴──┘ └──┴──┘ │ │ ∧ ∧ ∧ │<───── BRK ─────>│ │ │ │<───── SOF ─────>│ │ EOD EOF │ │<────────────── IFS following BRK ─────────>│ IFS FIGURE 12 . resynchronization to rising edges must continue to occur.│ ─┘ └──┴──│──┴──┴──│──┴──┴──│──┴──┴──│── └───────────────────────┘ ∧ │ EOD ∧ │ EOF ∧ ∧ │ │ ┌───────────────────────┐ │ IFS │ May Transmit if rising│ └───────┤ edge has been detected│ │ after an EOF.6
Break (BRK) . │ └───────────────────────┘
∧ │ Last Bit of Frame ─┘
FIGURE 13 . or last In-Frame Response bit.1.EOF and Idle Bus Definition Note: Last bit of a frame may be the last data bit.6.BRK is allowed to accommodate those situations in which bus communication is to be terminated and all nodes reset to a "ready-to-receive" state (see Figure 12).
. Contention may still occur when two or more nodes transmit nearly simultaneously. an IFS following BRK perioid (Tp9 after the rising edge of the break) is needed to resynchronize the receivers. A node may begin transmission at any time during idle bus. During an idle bus.6.7
Idle Bus (Idle) . The PWM Break symbol is an extended SOF symbol and will be detected as an "invalid" symbol to some devices.
2. The following values represent nominal timing. Paragraph 7. EOF. there is one symbol per transition and one transition per symbol. IFS. The leading edge is used as the only reference because the transition from passive to active appears on the bus wires as a fast clean edge while the transition from active to passive is slow and ambiguous due to variations in network capacitance. The EOD.3. and Break symbols are defined simply by the amount of time that has expired since the last transition.6. The pulse widths change between passive and active bus states in order to accommodate the arbitration and priority requirements as specified in Section 6. and "1" bit are defined by the time between two consecutive transitions and the level of the bus.2
Variable Pulse Width Modulation . "0" bit. ─┐ ┌─ │<──── Tv2 ────>│ └───────────────┘ "1" Bit ┌─────────┐ │<─ Tv1 ─>│ ─┘ └─
6. The transition from active to passive (which occurs within the SOF or data bits) is not used as a timing reference.2.One and Zero Bit Definitions
. and IFS are all passive symbols and the Break is an active symbol.6.1 defines the timing values for PWM at 41.
6.6 Kbps.7.1
─┐ ┌─ │<─ Tv1 ─>│ └─────────┘ "0" Bit
┌───────────────┐ │<──── Tv2 ────>│ ─┘ └─
FIGURE 14 .1. active or passive. Therefore. Values are provided for the transmitter and receiver (based on the suggested bit decoder implementation). Conversely.6.The SOF symbol.A "1" bit is either a Tv2 passive pulse or a Tv1 active pulse. EOF.The symbol timing reference for PWM encoding is based on transitions from the passive state to the active state. The SOF and each data bit in PWM has a "leading edge" from which all subsequent timing is derived. detailed timing requirements for each bit / symbol can be found in Section 7.8
PWM Symbol Timing Requirements .6. EOD. a "0" bit is either a Tv1 passive pulse or a Tv2 active pulse (see Figure 14). The end of the previous symbol starts the current symbol. The One "1" and Zero "0" Bits .
Tv3 in duration (see Figure 16) ───┐ ┌─ │<────── Tv3 ──────>│ └───────────────────┘ "EOD"
FIGURE 16 .3 End Of Data (EOD) . The preferred method is to use an active short bit (Tv1) to indicate that the IFR DOES NOT contain a CRC (i.SOF is a active pulse.6. Tv3 in duration (see Figure 15) ┌───────────────────┐ │<────── Tv3 ──────>│ ───┘ └─ "SOF"
FIGURE 15 . An active long bit (Tv2) would therefore indicate that the IFR DOES contain a CRC (i. all future SAE J1850 applications are urged to implement the normalization bit using the preferred method described above. However. Figure 18 illustrates the IFR using the normalization bit.2.End of Frame (EOF) Symbol 6. The responding device generates the normalization bit prior to sending the IFR data. This normalization bit defines the start of the IFR and can take two forms.Start Of Frame (SOF) Symbol 6.2
Start Of Frame (SOF) .2.. Therefore. The normalization bit can also be used to indicate what type of response is expected during the IFR portion of the frame. Tv4 in duration (see Figure 17) ───┐ ┌─ │<───────── Tv4 ─────────>│ └─────────────────────────┘ "EOF"
FIGURE 17 .2. it is necessary to generate a normalization bit to follow the EOD symbol.The "In-Frame Response" (IFR) is transmitted by the responder and begins after the passive EOD symbol.EOF is a passive pulse.2.. For Variable Pulse Width Modulation.e.
. This is only a preferred method. IFR type 3).6.6.4 End of Frame (EOF) . and individual manufacturers are allowed to implement the normalization bit per their requirements.EOD is a passive pulse.e.End of Data (EOD) Symbol 6. the first bit of the IFR data is also passive. IFR types 1 or 2).5 In-Frame Response Byte(s) / Normalization Bit .6. The first form is an active short period (Tv1) and the second form is an active long period (Tv2).6.
6 Inter-Frame Separation (IFS) .Inter-Frame Separation is used to allow proper synchronization of various nodes during back-to-back frame operation. │ └───────────────────────┘ FIGURE 19 . b.2. Bit ──>│ ───┐ ┌──────────────────┐ │<────── Tv3 ──────>│<── Tv1 or Tv2 ──>│ Passive └───────────────────┘ └── ∧ ∧ ∧ │ │ │ End of Last ┘ EOD Start of ┘ Data Bit IFR Bit Active
FIGURE 18 . CRC byte. IFS minimum has expired (Tv6). EOF minimum and another rising edge has been detected (Tv4). │<────────── Tv6 ─────────>│ │<─────── Tv4 ──────>│ │ │<──── Tv3 ────>│ │ │ ┌───────────────────────┐ Active ──┐ │ │ │<───┤ Idle bus.Normalization Bit 6. may initate │ │ │ │ │ │ transmission any time. the overall frame / message length limit remains in effect. │<─── Norm. A transmitter that desires bus access must wait for either of two conditions before transmitting a SOF (see Figure 19): a. The sum total of data bytes.Inter-Frame Seperation
.6.If in-frame response bytes are used. and in-frame response bytes shall not exceed the value specified in Section 7.│ Passive └──────────────────────────── └───────────────────────┘ ∧ ∧ ∧ ∧ ∧ │ │ │ │ │ ┌───────────────────────┐ End of Last ┘ EOD EOF │ IFS │ May transmit if rising│ Data Bit └───────┤ edge has been detected│ │ after an EOF.
therefore. Other factors that affect the transmitted pulse width are oscillator tolerance and variations in delay through the receiver.
.Idle bus is defined as any period of passive bus state occurring after IFS.BRK is allowed to accommodate those situations in which bus communication is to be terminated and all nodes reset to a "ready-to-receive" state (see Figure 20). Contention may still occur when two or more nodes transmit nearly simultaneously. which are a major contributor to the radiated contents of the signal do not fall within the limits imposed by Tt.max is reduced it becomes more and more difficult to design a driver which also meets the necessary EMI requirements.Break signal 6.max.max.min and Tx. otherwise.max (the area between Vol. As Tt. an IFS period (Tv6) is needed to resynchronize the receivers and the normal IFS rules for transmitting a SOF during back-to-back operation apply.2.min or Vol.2. most of the variation is in the time it takes the driver to leave the current state and start the transition.9 VPW Symbol Timing Requirements . resynchronization to rising edges must continue to occur. The various factors (plus some guard band and allowance for alternative implementations) can be lumped into a single set of limits.7
Break (BRK) .2.6. An idle bus will exist after IFS (Tv6).Tt. 6. other frames may gain access under the normal rules of arbitration.max and Voh. If the "Breaking" device wishes to obtain guaranteed access to the bus.6.6.max and Voh. the corners of the waveform. Tx. bounds the time span between the earliest and latest node to recognize a transition and is a key design parameter. the highest priority frame must then be sent. In this manner.6. noise filter. A node may begin transmission at any time during idle bus.min).min (in either direction).8 Idle Bus (Idle) . if any. Each is measured from the trip point of the previous transition as seen by the transmitting node (assuming a step input) to the beginning or end of the transition at Voh.The most important factor in symbol timing uncertainty is the edge position uncertainty due to the time taken to make a transition between Vol. Following the break symbol. The VPW Break symbol is a long active period (≥ Tv5). which will then ignore the current frame. For a fixed oscillator and a well designed digital filter.max. for each symbol.
│<───── ≥ Tv5 ────────>│<──────────── Tv6 ─────────────>│ │ │<───────── Tv4 ─────────>│ │ Active ┌──────────────────────┐ │ │ │ │ │ │ Passive ──┘ └─────────────────────────────────── │ ∧ ∧ ∧ │<─────── BRK ────────>│ │ │ End of Last ┘ EOF IFS Data Bit
FIGURE 20 . as found in Section 7. The maximum allowable transition time. The VPW Break symbol will be detected as an "invalid" symbol to some devices. and driver.
has detected contention to the transmission of its frame.max + Tt. Bit-by-bit arbitration is based on the use. 6. Only the one frame that wins all conflicts of different symbols and bits with all the other nodes that began transmitting during that frame will not detect contention. The actual acceptance range must be wider to allow for receiver oscillator tolerance and any implementation dependent uncertainties or constraints. The symbol limits defined in Section 7 are consistent with Tt. Tnom is the nominal symbol time with no oscillator error and the receiver detecting the transition at Vt (see analysis in Appendix D).Contention detection is the recognition of conflicting symbols or bits. the contention scheme assures that the highest priority frame always wins regardless of which node started transmitting first. the filter should respond as though a single step input had occurred at some point within that period. In the presence of arbitrary noise during the transition period. can range from Tx. the resultant state on the bus is always active (active state dominates). of two values of the bus.max to Tx.min . This range represents a receiver's required acceptance range for a given symbol.The pulse width as seen by another node. All symbols and bits are encoded on the bus by the physical layer as combinations of active and passive state signals.A contention situation arises when more than one node attempts to access the bus at essentially the same time.Tt.7. Although the fastest or slowest node dominates a particular transition.max and the specified oscillator tolerance. The purpose of the noise filter is to eliminate impulse noise which may exceed the steady state noise margin and to minimize the need for hysteresis at the receiver input. at the physical layer. A node that detects a difference between the symbol or bit it receives and the symbol or bit it is currently transmitting.7. the node must discontinue the transmit operation prior to the start of the next bit.The bit-by-bit arbitration scheme described below settles the conflicts that occur when multiple nodes attempt to transmit frames simultaneously.1 Contention / Arbitration / Priority . called the active state and the passive state. there is no space allocated for an unambiguous (with normal tolerances) forbidden zone between symbols. During simultaneous transmissions of active state and passive state signals on the bus. This scheme is applied to each symbol / bit of the frame. Bit-by-Bit Arbitration . starting with the SOF symbol and continuing until the end of the frame. which may perceive the leading edge either sooner or later than the transmitting node. The process of bit-by-bit arbitration allows conflicting frame transmissions to be detected. The time windows are not affected by multiple nodes trying to transmit at the same time during arbitration. The delay through the filter is compensated for in the timing logic.max in absolute terms. A specific implementation of the filter is not required for compatibility so long as the delay is properly compensated and the uncertainty bounds are not exceeded. This is because a single node effectively dominates each transition. the process used to cease transmission is implementation specific. Some possible options are:
. If the transmitting node detects a signal state on the bus that is different from the state being transmitted by the node during the header portion of the frame. The necessary guard band limits how close together symbols can be defined. It is either the first node to leave the passive state or the last node to leave the active state.7 6. If the transmitting node detects a signal state on the bus that is different from the state being transmitted by the node during the data portion of the frame (following the header). Contention Detection . To keep the symbols short.
Discontinue the transmit operation prior to the start of the next bit (similar to the action taken if contention is detected during the header phase).. care must be taken by receiving nodes not to accept the message as a valid one. based on the two forms of modulation allowed (PWM and VPW). FIGURE 21 . If transmission of a message is prematurely terminated on a byte boundary due to unexpected contention detection following the header.
Sending Node B
Sending Node C
BIT-BY-BIT ARBITRATION ON A VPW BUS Sending Node A A ┌───────┐ ┌────┐ ┌──┐ ┌────┐ ┌──┐ P ─┘ └──┘ └────┘ └──┘ └──┘ └── ─ ─ ─ ─ ─ ─ Contention detected by A ^ A ┌───────┐ ┌────┐ ┌──┐ ┌────┐ ┌────┐ ┌──┬─┐ P ─┘ └──┘ └────┘ └──┘ └──┘ └────┘ └─┴── A ┌───────┐ ┌────┐ ┌──┐ ┌──┐ P ─┘ └──┘ └────┘ └──┘ └── ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ Contention detected by C ^ A ┌───────┐ ┌────┐ ┌──┐ ┌────┐ ┌────┐ ┌──┬─┐ P ─┘ └──┘ └────┘ └──┘ └──┘ └────┘ └─┴── │ SOF │ 0│ 0 │ 1 │ 1│ 0│ 0 │ 0│ 0 │ 1 │ 1│ . Transmit additional bits (< 8) when contention is detected on a byte boundary. b. a node may need to validate the received message to ensure it is of the correct length..a. There is a 1 in 256 chance that the last byte received is the CRC of the previous bytes and would therefore appear to be a valid message.. Bus access is granted to nodes sending an active state signal over nodes sending a passive state signal. BIT-BY-BIT ARBITRATION ON A PWM BUS
Sending Node A
A ┌────┐ ┌──┐ ┌──┐ ┌─┐ ┌─┐ ┌──┐ ┌──┐ ┌─┐ P ─┘ └──┘ └─┘ └─┘ └──┘ └──┘ └─┘ └─┘ └─ ─ ─ ─ ─ ─ ─ Contention detected by A ^ A ┌────┐ ┌──┐ ┌──┐ ┌─┐ ┌─┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌─┬─┐ P ─┘ └──┘ └─┘ └─┘ └──┘ └──┘ └─┘ └─┘ └─┘ └─┘ └─┴─ A ┌────┐ ┌──┐ ┌──┐ ┌─┐ ┌─┐ ┌─┐ P ─┘ └──┘ └─┘ └─┘ └──┘ └──┘ └─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ Contention detected by C ^ A ┌────┐ ┌──┐ ┌──┐ ┌─┐ ┌─┐ ┌──┐ ┌──┐ ┌──┐ ┌──┐ ┌─┬─┐ P ─┘ └──┘ └─┘ └─┘ └──┘ └──┘ └─┘ └─┘ └─┘ └─┘ └─┴─ │ SOF │ 0 │ 0 │ 1 │ 1 │ 0 │ 0 │ 0 │ 0 │ .Arbitration
. Figure 21 shows this operation on the physical layer.. This ensures that a framing error will be received by all other receivers in the case of unexpected contention detection possibly due to noise. In this case.
the lowest value bytes immediately following the SOF will have the highest priority. and that the individual nodes may themselves have both powered and standby states. Two perspectives are used to define the session layer: a. without regard to the individual nodes on the network b. Hence.6." the numerical value of zero will have the absolutely highest priority (that is. 000 is higher priority than 001 or 111). the view from an individual node Both are required for a complete definition of the possible states of network operation. Based on the bit definitions contained in Section 6. 6. nondestructive arbitration will occur based on the bit value within each frame.5 and 6.The arbitration resolution described above concerns all the symbols and bits between the SOF and the EOF including. when arbitration is resolved down to a single transmitter prior to any data values within the frame. In the context of this document the Session Layer controls the transitions between the operating and the standby states. Any remaining nodes will continue to send their symbols / bits until the next contention is detected. the view of the media itself. Therefore. in the case of an in-frame response. Frame Priority .The transition to a functional/operating network from an unpowered or standby state is a common occurrence in vehicle multiplex systems. The bus allows two states .3 Arbitration Area . When unique frames or.7. all the symbols and bits of the in-frame response. all of the nodes still transmitting after the last symbol or bit will detect whether any contention is taking place. The node which obtains sole access to the medium is that which sends its symbols and bits without detecting any contention. frame arbitration occurs in a bit-wise manner.4
. It is expected that a typical vehicle multiplex system may contain a mixture of unpowered and powered nodes. Should two or more nodes attempt to access the bus within the same frame synchronization window (see IFS in Sections 6.active and passive. If a active state bit and a passive state bit are transmitted on the bus simultaneously. by definition. regardless of the number of bits allocated for "frame prioritization. 6.The bit-by-bit arbitration mechanism allows the implementation of a frame priority system.2.7). In other words.1.6.The arbitration process begins with the SOF and continues through all the bits of the frames being sent. a structure of relative frame priority is inherent. more particularly. The result of the arbitration is that the node(s) sending lower priority frame(s) will recognize that they have lost arbitration and will discontinue transmitting before the next bit time. lost arbitration and will discontinue sending any further symbols or bits. arbitration acts throughout the frame. Nodes that detect contention have.6.
6. The node transmitting the highest priority frame will continue transmitting uninterrupted. As each symbol or bit of all the simultaneous frames is transmitted.7.8 Node Wake-Up Via Physical Layer . then the active state bit will override the passive state bit.
An unpowered node is not capable of network communication.2 6.All nodes must continue to meet the network leakage current requirement during a loss of power (or low voltage) condition.1
. and.8.6.2
6. Node Power Loss . it is possible for individual nodes to be in the sleep state on a fully biased network or in the awake state on an unbiased network). Bus Short to Ground . There is no specified requirement for the transition from the awake state to the sleep state. Proper bus bias must be supplied by all nodes designated to supply bias when the network is powered. all nodes which are capable of wake-up from network signals must do so. since this parameter is largely application dependent. Awake / Operational . Sleeping Node .8. b. Biased Network . since this is an implementation specific issue.1. This requirement assures a finite and limited delay to establish communication with nodes which may be in the sleep state.e. In other words. may not even occur (e. The maximum amount of time from the wake-up stimulus until the node is capable of communicating is implementation specific.1 6. but this is not a requirement (i. otherwise these nodes are considered "unpowered".Network data communications may be interrupted but there shall be no damage to any node when the bus is shorted to ground.A sleeping node may have an optional low power standby mode capable of detecting network signal transitions for the purpose of wake-up. A transition of the bus from the passive state to the active state shall be considered a "wake-up" signal to a sleeping node.8.8. Individual nodes on the network may exist in any of the three states described below.The network must meet the requirements as defined per the following failure modes: a. Physical Layer Fault Considerations Required Fault Tolerant Modes .1 6.
6. The media must first be brought to the biased state before communication can take place. No communication is possible on an unbiased network.An unbiased network is all conductors at ground voltage and the impedance of the conductors not controlled..2.2.1.2
Individual Nodes Unpowered Node . The time required for the media to make the transition from the unbiased to the biased state is not defined in this document.
6.An awake / operational node is fully capable of receiving and transmitting frames on the network.g. media always biased).3
Network Media Unbiased Network .2. in fact.9 6. For the same reason the time required for a node to make the transition between the unpowered state and the sleep or awake state is also not defined. Note that nodes which use the optional sleep state are required to wake up from the appropriate network signal within a defined wake-up period. Any interface device in the sleep state can be awakened by any other interface device via network activity or awakened by its host via its interface to the host. The transition of the network from the unbiased to the biased state may serve as a node wake-up signal for certain applications.A biased network is all conductors at the "passive" voltage level (with no communciation occurring) and with appropriate impedances capable of supporting communication.8.. nor wake-up from network signal transitions.8.
The network may optionally meet the requirements as defined per the following failure modes: a. c.2 Optional Fault Tolerant Modes . A philosophical method for classification of functional performance can be found in SAE J1113 Part 1 Appendix B (formerly SAE J1113 Appendix B).10 EMC Requirements . 6. All nodes shall be protected from damage during the presence of these faults such that recovery to normal operation occurs automatically upon removal of the fault (i. Continued communication is not required for the "Double Fault" condition of the Bus "+" wire shorted to the Bus "-" wire.
Bus Short to Battery . Loss of Termination / Bias . for example.
d. b.c. the remaining nodes shall remain capable of communications. Loss of Node Connection to Ground . could be assured of adequate performance for all conditions. Dual Wire Fault Tolerant Operation .Nodes on a dual wire bus may be capable of full communication (sending and receiving frames) at the specified bit rate in the presence of any one of the following faults occurring anywhere on the network: (1) Bus "+" wire Open Circuit (2) Bus "-" wire Open Circuit (3) Bus "+" wire Shorted to Ground (4) Bus "-" wire Shorted to Ground (5) Bus "+" wire Shorted to Battery + (Vbatt) (6) Bus "-" wire Shorted to Battery + (Vbatt) (7) Bus "+" wire Shorted to any voltage between Ground and Battery (8) Bus "-" wire Shorted to any voltage between Ground and Battery Noise immunity and emissions may be somewhat degraded during the faulted period but shall return to normal after the fault is removed. A component manufacturer that designs the interface device to conform to the most severe classification of Class C Region I.9.The vehicle manufacturer shall specify a minimum EMC level of operation for a module that utilizes this network interface device. the remaining nodes shall remain capable of communications.When a node loses its ground connection.. faults shall not propagate through the network).Network data communications may be interrupted but there shall be no damage to any node when the bus is shorted to battery power.
. 6.e.Biasing and termination resistors shall be redundant such that no single point failure will cause the network to become inoperative.When a node becomes disconnected from the network. Loss of Connection to Network .
For reference the levels defined by CISPR/D/WG2 (Secretariat) 19 Sept 1989 may be used. Radiated Emissions Antenna & Probe Test (CISPR/D/WG2(Secretariat) 19Sept1989) Transfer Function. EMC and voltage "level" requirements specified by the Test Plan are given for reference only and the vehicle manufacturer specifications shall be used for compliance testing. The vehicle manufacturers may find SAE J1211 A Recommended Environmental Procedure for Electronic Equipment Design helpful in specifying their multiplex systems. e. Current probe monitoring (SAE J1113 Part 2) Transfer Function. a. Antenna monitoring (SAE J1113 Part 3) RF Susceptibility (SAE J1113 Part 13) Transient Susceptibility (SAE J1113 Part 10)
. c. This document recommends the vehicle manufacturers use the following documents and the outlined EMC test plan defined in Appendix B. b. SAE J1879 A Recommended Practice for General Qualification and Production Acceptance Criteria For Integrated Circuits in Automotive Application also may be utilized for specifying components.The modules that communicate with each other via this interface device shall not generate levels of noise emissions (EMI) large enough to interfere with each other. In general the specifications on wave shaping and transition rise and fall times control the EMI levels. d.
excluding frame delimiters SOF.2 7..4 Kbps .3.e. meters
7. EOF.e. excluding frame delimiters SOF.2.3 7.2 7.2. The maximum number of message bytes (i. pF max. Variable Pulse Width (VPW) at 10.1
Off-vehicle capacitance 500 (each bus wire to signal or chassis ground.The maximum frame length from SOF to EOF inclusive is 101 bit times.7 PARAMETERS 7. EOF. and IFS) is 12 bytes. Physical Layer General Network Requirements (see Table 2) TABLE 2 .6 meters nodes Kohms min.1 Application Layer .General Network Parameters Parameter Description On-Vehicle Network Length Off-Vehicle Network Length Total Vehicle Network Length Maximum number of standard unit loads (including off-vehicle equipment) Off-vehicle load resistance Parameter Value 35 5 meters 40 32 10..The maximum number of message bytes (i.A "0" bit dominates over a "1" bit.6 Kbps . EOD. as measured at the SAE J1962 connector)
. and IFS) is 12 bytes. 7.The following Application Layer requirements shall exist whenever the network is used. EOD.1 Data Link Layer Pulse Width Modulation (PWM) at 41. Bit Dominance .
max ≤ 10 ≤ 18 ≤ 27 ≤ 54 N/A N/A
≤ 32 ≤ 41 N/A
≤ 34 ≤ 43 N/A
EOF transitions into IFS and is not actually a "transmitted" symbol. Receive tolerances include considerations for voltage offsets between transmitter and receiver and other miscellaneous tolerances.2.PWM Pulse Width Times (µsec) Symbol Tp1: Active phase "1" Tp2: Active phase "0" Tp3: Bit time Tp4: SOF / EOD time Tp5: EOF time Tp6: IFS time Tp7: Active SOF Tp8: Active BRK Tp9: BRK to IFS time Tx. physical layer delays (i.2 7.e. An incorrect decision will be detected in the CRC error detection byte.3. Symbols received in the "gray" areas above can be decoded as either the symbol before or after that of the "gray" area. max ≤8 ≤ 16 ≤ 25 ≤ 49 N/A N/A
Rx.. Figure 22 below gives an example of how a signal should be decoded based on the received pulse width. Table 3. turn-on and turn-off delays). are for a nominal bit time of 24 µs or 41.6 Kbps TABLE 3 .
.nom 7 15 24 48 72 96 31 39 120 Tx. For example.min ≥4 ≥ 12 ≥ 21 ≥ 42 ≥ 63 ≥ 84 ≥ 27 ≥ 35 ≥ 105
Rx.3.7. and other miscellaneous tolerances. Maximum IFS ends at next SOF.The following requirements.
Transmit tolerances include oscillator tolerances.1
Pulse Width Modulation (PWM) PWM Timing Requirements . an active pulse of 11 µsec can be decoded as either an active phase "1" (Tp1) or an active phase "0" (Tp2).min ≥6 ≥ 14 ≥ 23 ≥ 47 ≥ 70 ≥ 93 ≥ 29 ≥ 37 ≥ 116 Tx.
a pulse width detected between Tp1(max) and Tp2(min) can be decoded as either an active phase "1" or active phase "0".Example of Receiving a Tp1 or Tp2 Symbol Note that a pulse width detected between Tp1(min) and Tp1(max) must be decoded as an active phase "1" and a pulse width detected between Tp2(min) and Tp2(max) must be decoded as an active phase "0" However.FIGURE 22 .
.80 --85 500 ---------------
Typ ----------5. Therefore.00 3. each wire to ground) Node Capacitance (unit load.load.passive state.active state) Node Leakage Current (each wire .75 180 378 15.25 1.passive state.00 ------------2. wire-to-wire) Node Leakage Current (each wire .000 1.2
PWM DC Parameters (see Table 4) TABLE 4 .7.max.25 2. The product of Rload and Cload must always be less than T.3.880 250 10 -----
Max 6.35 1.80 -1. powered node) Notes:
Symbol Vih Vil Voh Vol Vgo Vsup Vcm Vhys Rload Cload Tload Tt Rul Culg Culw IleakA IleakPU
Min 2.PWM DC Parameters Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Absolute Ground Offset Voltage Bus (+) Driver & Bus (-) Termination Supply Voltage Receiver Input Common Mode Operating Range Receiver Hysteresis & Overdrive Network Resistance (each wire) Network Capacitance (each wire) Network Time Constant Signal Transition Time Node Resistance (unit load.25 2.00 4.2. The network time constant (Tload) is the product of Rload and Cload.80 0.00 5.20 5. some combinations of network resistance and network capacitance are not allowed.75 1.20 1.75 ------100 100
Units volts volts volts volts volts volts volts mvolts ohms pF µsec µsec ohms pF pF µAmp µAmp
IleakPP
µAmp
Refer to Appendix D for an analysis of the PWM waveform. unpowered node) Node Leakage Current (each wire . each wire) Node Capacitance (unit load.
max ≤ 79 ≤ 145 ≤ 218 N/A
Rx.3 7.The following requirements.3.max ≤ 96 ≤ 163 ≤ 239 N/A
≤ 5 msec N/A
Variable Pulse Width Modulation (VPW) VPW Timing Requirements .VPW Pulse Width Times (µsec) Symbol Tv1: Short Pulse Tv2: Long Pulse Tv3: SOF / EOD time Tv4: EOF time Tv5: BRK time Tv6: IFS time Tx. TABLE 5 .nom 64 128 200 280 300 300 Tx. Maximum IFS ends at next SOF.
. Table 5.3.min > 34 > 96 > 163 > 239 > 239 > 280
Rx.0 sec N/A
EOF transitions into IFS and is not actually a "transmitted" symbol.min ≥ 49 ≥ 112 ≥ 182 ≥ 261 ≥ 280 ≥ 280 Tx. show the VPW timing values.3.7.
3.7. The product of Rload and Cload must always be less than T.max.50 2.load.
.544 5.470 -----------
Typ -----------------
Max 20.50 8.600 470 ---
Refer to Appendix C for an analysis of the VPW waveform.3.00 0.2 18. some combinations of network resistance and network capacitance are not allowed.00 3. The network time constant (Tload) is the product of Rload and Cload.2
VPW DC Parameters (see Table 6) TABLE 6 .0
Units volts volts volts volts volts ohms pF µsec µsec ohms pF µAmp
10.25 --6.25 0. Therefore.00 315 2.575 16.max).00 1.VPW DC Parameters Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Absolute Ground Offset Voltage Network Resistance Network Capacitance Network Time Constant Signal Transition Time Node Resistance (unit load) Node Capacitance (unit load) Node Leakage Current
Symbol Vih Vil Voh Vol Vgo Rload Cload Tload Tt Rul Cul Ileak
Min 4.00 1. Individual manufacturers may require a higher upper limit (Vih.
SOF. Single Responder) ERROR DETECTION Cyclic Redundancy Check (CRC) Out of Range Invalid Bit Invalid Symbol Invalid Structure Invalid Message Length Number of Arbitration Bytes FAULT TOLERANCE Node Power Loss Bus Short to Ground Bus Short to Battery Loss of Node Ground Connection Loss of Termination Resistance Loss of Network Connection Tx Rx Comments
. Multiple Responder) Type 3 (Multiple Byte.CHECKLIST OF APPLICATION SPECIFIC FEATURES A The following checklist is provided as an aid to highlight the communication features of J1850. Single Responder) Type 2 (Single Byte.APPENDIX A .Checklist of Application Specific Features FEATURES FRAME ELEMENTS General Frame Elements : IFS. Data. EOF. CRC. End of Data (EOD) Normalization Bit (NB) . TABLE A1 .Tv1/Tv2 BUS ACCESS Idle Bus Break (BRK) IN-FRAME RESPONSE Type 0 (None) Type 1 (Single Byte.
TABLE A1 .4 Kbps Variable Pulse Width Modulation (VPWM) 41. (continued) FEATURES Dual Wire Fault Tolerance HEADER BYTES Single Byte One Byte Consolidated Three Byte Consolidated RATE / SYMBOL ENCODING 10.6 Kbps Pulse Width Modulation (PWM) FEATURE ELEMENTS Maximum Frame Size Wake-Up Capability Tx Rx Comments
.Checklist of Application Specific Features.
Frequency .3 Active Bus State a. Bandwidth .10 KHz to 200 MHz Bandwidth Setting a.1.3 KHz B. Sweep signal off B.(CISPR/D/WG2(Secretariat) 19 Sept 1989) .I/O EMC TEST PLAN B I/O EMC Test Plan B.1 B. Frequency . Bandwidth .Tektronix A6302 (0 .1.See Figure B1 for diagram Radiated Emissions Antenna Test Frequency Range .1.10 KHz to 149 KHz. Recommended probe type .2 Radiated Emissions Probe Test Frequency Range .3 Test Data
B.1.1. Frequency .2. Sweep signal off B.3. Frequency .2.1 Ambient Reference a.1.1.0 GHz Bandwidth Setting a.1 KHz b.10 KHz to 1.1.1.1 B. Recommended probe type .1.APPENDIX B .1 B. Both transmitter and receiver power off c.10 KHz to 149 KHz. Bandwidth .2 Radio Disturbance From Vehicle Components .150 KHz to 1 GHz.1.1. Sweep signal off B.200 MHz) B.1.2 Idle Bus State a. Bandwidth .3. 10 KHz modulation off b.5 cm from part
.2. Both transmitter and receiver power on c.1.3. 10 KHz modulation on b.1.3 Probe Type .1.As required to make measurements a. Both transmitter and receiver power on c. 10 KHz modulation off b.1 B.1 KHz b.3 KHz B.2 B.1.29 MHz) b.150 KHz to 1 GHz.4 Probe Distance .Ailtech 94111-1 (30 .2.1.
Both transmitter and receiver power off c.5.2. Amplitude .5 Test Data
B. Sweep signal off B.1 V peak to peak at test point
.2.1.1 Ambient Reference a.2.1.2 B.30 Hz to 250 KHz b.2 Idle State a. a. 10 KHz modulation on b.5. 10 KHz modulation off b.FIGURE B1 .1 Transfer Function . Sweep signal off B.Electromagnetic Susceptibility Measurement Procedures for Vehicle Components Current Probe Monitoring . Both transmitter and receiver power on c.5.Adapted from SAE J1113 Part 2 (Formerly SAE J1113 (Aug 87) Section 2).2. Both transmitter and receiver power on c.2.3 Active Bus a.EMC Test Setup B. Frequency . 10 KHz modulation off b.1. Sweep signal off B.1.
Test Pulse 3b: +40 volts (Reference)
Antenna Monitoring .3.Adapted from SAE J1113 Part 3 (Formerly SAE J1113 (Aug 87) Section 3). Both transmitter and receiver power on c.3.≈ 25 milliwatts to generate 1 V peak to peak at test point
Transfer Function from Ground to Bus a.3 B.3.100 mA RMS Procedure .Injection and monitoring to be applied to Bus pair only Test Data .1
Test Data Transfer Function from Vcc to Bus a. 10 KHz modulation on b.2.3
RF Susceptibility Electromagnetic Susceptibility Measurement Procedures for Common Mode Injection for compliance.4
Frequency Range .Test per SAE J1113 Part 10 (Adapted from ISO 7637/3) Test Pulse Amplitude a. Sweep signal on
B. Test Pulse 3a: -60 volts (Reference) d.2. Sweep signal on
B.3. Attenuator input power .2.3.B. Both transmitter and receiver power on c. Test Pulse 2: +30 volts (Reference) c.3 B. Frequency .2 B. Test Pulse 1: -30 volts (Reference) b.2. test per SAE J1113 Part 13 (Formerly SAE J1547)
B.1 B. 10 KHz modulation on b.1 MHz to 200 MHz Max Level .Record the nature of any interaction occurring below the test level along with the current and frequency Transient Susceptibility .4 B. a.250 KHz to 200 MHz b.
1.1. Vt .VPW WAVEFORM ANALYSIS C VPW Waveform Analysis Figure C1 shows a drawing of a bus waveform with various voltage levels and trip points.4 C. This is also the highest trip point.3 C. This is also the highest trip point.min .1 C. and is also the lowest trip point with no offset noise.Minimum guaranteed output high voltage.Ideal receiver trip point. with the receiver having no ground offset noise.APPENDIX C . and the source having 2V of noise. Vil.2 C.max .Minimum guaranteed input high voltage. The voltage levels and trip points are defined as follows: C.Voltage Levels and Trip Points
.1.5 Voltage Levels and Trip Points Voh.1.
FIGURE C1 .max . and the receiver having 2V of noise.1 C.Maximum guaranteed output low voltage.1. Vih. and is also the highest trip point with no offset noise.min . with the source having no ground offset noise.Maximum guaranteed input low voltage. Vol.
VPW Pulse Width Analysis Factors that affect the transmitted pulse width are oscillator tolerance and variations in delay through the source driver.Tx. The receiving node may perceive the leading edge sooner or later than the transmitting node (source node).max . The Tx. Therefore the pulse width seen by another node for the this Tx. This sets up the possibility of the receiving node tripping at Vol.Tt.mar Tx.nom and Tt. without regard to whether that edge was due to their own or another transmitter. Figure C2 shows a drawing of this acceptance range.max situation including the oscillator tolerance and guard banding is given by equation C4. For VPW.Tt. The pulse width seen by another node (receiver) can range from Tx. All transmitting nodes reference their transmit timing from their receiver's perception of the previous edge.max to Tx.max situation occurs when a Tx.
.min = (Tnom . The fact that what is seen at the source's own receiver contributes to the transmitted pulse width.min .max. The Tx. Again the actual acceptance range must be wider to allow for the receiving node's oscillator tolerance and any implementation dependent uncertainties or constraints.C.max factors are given in section 7.max for each bus symbol. Figure C2 shows a plot of Tx. Similarly equations C7 and C8 are derived. The Tx.max = (Tnom + Tt.Tt.max /2 factor is equal to zero since an ideal trip point and no ground offset was assumed.max /2) * 2% factor covers the 2% oscillator tolerance.max situation occurs with a Tx. and received by a receiving node with a 2V of ground offset noise. mode synchronization is an integral part of symbol timing.max + Tt.max /2) * 0. Tx.min pulse width is transmitted by a source node with no ground offset noise.min and Tx.min .98 . The equations C1 and C2 are used to generate the transmitted pulse values shown in Table C1: Tx. This range comes from the variations in the transmitted pulse width combined with possible noise offset affects on the transmitted and receiving node. Equation C5 is derived by substituting equation C1 for Tx. and the receiver having no offset.02 + Tx.Tt. Each is measured from the ideal trip point on the leading edge of the waveform.min and Tx. This range represents a receiver's required acceptance range for a given bus symbol. are lumped into a single set of limits called Tx. C2)
The (Tnom + Tt.min . along with some guard banding. This sets up the possibility of the receiver tripping at Voh.min in equation C4.mar factor is assumed to be 7. C1) (Eq.max /2) * 1.min on the leading and trailing edge of the waveform.mar (Eq.0 which covers the rest of the factors (lumped variation in delay through the source driver and medium). the source node having 2V of noise. These factors. implies that the source device could be using echoed back information to shape what is transmitted. and the medium. The Tt.max pulse being transmitted.max + Tt. The Tx.
max and Voh. The waveform dispersion due to transmitter tolerances in oscillator. and starts timing the current symbol. The latest waveform that could trigger the transmitter at point A. The maximum and minimum trigger points of any given transition are illustrated by showing line A cutting through two different waveform transitions. The latest point on waveform "D" that could trigger any other node.
C3 1/6/94
BCDEFSAE J1850
. The earliest waveform that could trigger the transmitter at point A. driver. Take note that a node could trigger at any level of a transition between Vol. This method of illustration allows separating the uncertainties of nodes sensing the beginning and ending of a symbol.FIGURE C2 .Waveform Timing Parameters AThe trigger point on waveform "B" or "D" where the transmitting node sees the transition ending the previous symbol. The earliest point on waveform "B" that could trigger any other node. etc.min.
I .Starts at Voh.max on wave "D"
.Starts at Vol. Notes: Tx.GH-
The total transmitter spread when transition time limits are combined with the other tolerances in "F".min on wave "B". Tx. The shortest legitimate symbol time which can legitimately be seen under worst case conditions.min .The longest legitimate symbol time which can legitimately be seen under worst case conditions.max .
Tt. Tr.The reason for choosing a synchronous data encoding technique is to synchronize at every valid state transition.The calculations for the received Tr. If the delays through the filter.max/2) * 0.mar Tr.mar = 4.max = ([(Tnom + Ttp.max .min )) (Eq.02 + Tx.max = Tt.max) * 0.mar Tr.max) * 0.min .98 . The transmitting node Tt. Ttp.min and Tr. C4) (Eq. and output drivers can be characterized into a constant value this delay can be compensated for by the timing logic. Note these values compare favorably with the values specified in Section 7.max 96 162 237 N/A
Filter Compensation . C8) (Eq.min 49 112 182 261 Tx.min = ([(Tnom .max * ((Vih.Tt.
.0 covers the other uncertainties.98 .mar Tr.02 + Tx.max) * 0.Ttp.Vil. including receiver delay and digital filter delay.mar Tr. C7) (Eq. C5) (Eq.Tr. max 79 145 218 N/A Rx. receiver.mar (Eq. variations in delay and including a safety factor for dead zones between symbols for the Receiving device should be included in the ± 4. then the Source Interface device variations should be included in the ± 5.min . Table 5. All further.nom 64 128 200 280 Tx.max )/(Voh.min 34 95 164 241 Rx.max = (Tx.max factor would be zero (0) if it was a perfect receiver and sensed a transition at the ideal trip point.min = ([(Tnom .Tr. for a real receiver the trip point Ttp. Table C1 shows the VPW Pulse Width Timing Requirements TABLE C1 .max) * 0.mar Tr.mar] . VPW bus symbols allow no forbidden zones between symbols.98 .Tx.mar] + Tt.98 + Tr.Tt.min .max/2) * 1. C6) (Eq.98 .Tt.VPW Pulse Width Times (µsec) Symbol Tv1: Short Pulse Tv2: Long Pulse Tv3: SOF / EOD time Tv4: EOF time Tx.max/2) * 0. C9)
The 2% guard bands cover the oscillator tolerances of both transmitter and receiver and Tr.max can be approximated by equation B3 assuming a liner waveform rise time.max) * 1. However.min and Tx.max + Tt.mar] .Tx.min = (Tx.max/2) * 1.02 + Tr. C3)
The values for this range shown in Table C1 were arrived at using equations C6 and C9.max = ([(Tnom + Tt.max .02 + Tr.min and Tr.98 .max) * 1.Vih.max.0 µs factor defined in Tx.mar] + Tt.max are derived using the factors specified in section 7 for a 2 V ground offset range and a transition rise time of Tt. If variations in delay caused by this Filter and I/O Hardware cannot be easily compensated for.Tr.0 µs factor defined in Tr.
PWM WAVEFORM ANALYSIS D PWM Waveform Analysis Figure D1 shows a drawing of a typical bus waveform with various voltage levels and trip points.Typical PWM Waveform
.APPENDIX D . Table D1 contains the DC parameter specifications.
FIGURE D1 .
25 1. wire-to-wire) Node Leakage Current (each wire . The product of Rload and Cload must always be less than T.load.80 -1. unpowered node) Node Leakage Current (each wire .000 1.
.passive state. each wire to ground) Node Capacitance (unit load.00 3.PWM DC Parameters Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Absolute Ground Offset Voltage Bus (+) Driver & Bus (-) Termination Supply Voltage Receiver Input Common Mode Operating Range Receiver Hysteresis & Overdrive Network Resistance (each wire) Network Capacitance (each wire) Network Time Constant Signal Transition Time Node Resistance (unit load.75 1.00 4.80 0.max.TABLE D1 .80 --85 500 ---------------
Typ ----------5.880 250 10 -----
Max 6.passive state.00 ------------2.00 5. some combinations of network resistance and network capacitance are not allowed. each wire) Node Capacitance (unit load.75 180 378 15.25 2.20 1.75 ------100 100
The network time constant (Tload) is the product of Rload and Cload.25 2. Therefore.00 0.20 5.35 1. powered node) Notes:
Min 2.active state) Node Leakage Current (each wire .
11 D.max is Vil.1.This is the supply voltage which a transmitter must use to drive bus (+) and terminate bus (-). Note that Vol.1.This is the equivalent network capacitance from each bus wire to ground.1.1. bus voltage levels. The passive-to-active edge is driven by the transmitter and shall be no more than Tt.
D.max). Voh . Note that Voh.2 D.1.This is the signal transition time for each bus wire from either the active-to-passive state or passive-to-active state. Vcm .14
.1. Culw . Vol . This capacitance along with the unit load node capacitance wire-to-wire results in the total network capacitance referred to in paragraph C. Vsup . Vog .12
D.This is the equivalent network resistance from each bus wire to the corresponding passive voltage source. This is the product of Rload and Cload of each bus wire. Rload .This is the input low voltage which a transmitter must detect as an active state on bus (-) and as a passive state on bus (+).min is Vih.max minus the absolute maximum ground offset voltage (Vgo.1.min plus the absolute maximum ground offset voltage (Vgo. Tload .4
D. In order for the differential receiver to recognize a valid signal transition.This is the network time constant for each bus wire.6 D.This is the output low voltage which a transmitter must drive bus (-) and the voltage which bus (+) must passively return to.9 D.8 D.10 D.This is the receiver input common mode operating range.D.1. The active-to-passive edge is determined by the network time constant.1 D. Culg .This is the unit load node capacitance of each wire to ground.10.1. The time constant determines the maximum active-to-passive transition time. Cload .5 D.1.1. and the passive state supply voltage level.This is the input high voltage which a receiver must detect as an active state on bus (+) and as a passive state on bus (-).10.This is the output high voltage which a transmitter must drive bus (+) and the voltage which bus (-) must passively return to.3
Voltage Levels and Trip Points Vih . Vil .1.This is the absolute ground offset voltage that can exist between any two nodes on the network.This is the unit load node capacitance wire-to-wire. This capacitance along with the node capacitance of each wire to ground results in the total network capacitance referred to in paragraph C.max.1. Tt . Vhys .max).1.13
D.This is the receiver hysteresis and overdrive voltage including any power supply reference tolerance.1.1.1 D. the bus (+) and bus (-) signals must cross at a voltage within this range.7
75) .max) D.min + Vgo = -1.20 V Vih.1. D8)
) for Bus (-)
(Eq. Vil.max = Vil. Voh.25 (Vsup.18 = 2. Therefore. Vol.1.max)
) for Bus (+)
.17 D.This is the leakage current of each wire when the bus in in the passive state and the node is powered.min = Vih.max = ½ (5. D7) (Eq.max = Voh.00 = 6.81 V Vih.Vgo = 0.00 V Vil.00 + 1.20 µsec.2
IleakA .max)
(Eq.min = Vsup.e Vol.Vgo = 6. Vih and Vil can be derived.max + Vgo = 5. D6) (Eq.min must be satisfied for Bus (-) and Vol.1. IleakPU .max to Voh.Vgo = 2.D. Input Voltage Limits Given the Bus (+) Driver & Bus (-) Termination Supply Voltage (Vsup) and the maximum Receiver Hysteresis & Overdrive Voltage (Vhys). the following relationship for Voh. D.25 V (Eq. D5) (Eq.max and Vih.Vhys.4 Network Time Constant & Signal Transition Time In order to guarantee signal cross over in the Receiver Input Common Mode Operating Range (Vcm) the signal transition time must be less than 2. IleakPP . given ∆t = 2.25 + 1.15 D.00 = 1.min to Vol. D4)
where the ½ factor in Vil.00 = 0 V (Ground Reference) Vol.3 Output Voltage Limits Output voltage limits can be derived directly from the input voltage limits.min (1 .min = (Ground Reference) .This is the leakage current of each wire when the bus in in the passive state and the node is unpowered. D10)
-(∆t / Tload.min) .80 V Voh.min = Vil. D9) (Eq.max) + Vhys.max = Vsup. This is Tt.max + the worst case transition time from Vol.80 + 1.max .00 = 5.1.20 µsec. or Voh.max = ½ (Vsup.min = ½ (4.max = Vih.18 = 2.00 .20 V Voh.max .1.max for Bus (+).min for Bus (+).25 .max for Bus (-).min assumes a receive comparator voltage level of one-half of the supply voltage.0. It turns out this is a good trade-off for voltage ground offset capability versus output drive requirements. D2) (Eq.min + Vgo = 2.max (e
-(∆t / Tload.1.00 = -1. D3) (Eq.min = ½ (Vsup.16 D.This is the leakage current of each wire when the bus in in the active state.00 = 3.25) + 0.20 . D1) (Eq.
max = 2.max) = 2.min (for Bus +) from 2.max(Bus+) = -∆t ÷ ln(Vol.20 ÷ ln(1-(3.49 µsec Choosing a Tload.max to Voh.20 .75)) = 1.20 µsec. D13) (Eq.min) = 2.max = 2.20 . D15) (Eq.44 = 1.max to Voh.39 µsec Tload.min / Voh.min to Vol.75 µsec ensures that the two bus signals will cross within the Common Mode Operating Range.max (ln(1-(Vol.75))) = 0. D14) (Eq.20/4.min to Vol. Tload.max(Bus-) = -∆t ÷ ln(1-(Voh.T(Vol.39 = 1.min)) = -2.20 ÷ ln(1. D12) (Eq.max to Voh.min to Vol.max can be found by subtracting the time from Vol.max) can be derived.20 . D11)
.20/5.44 µsec Tload.max (ln(Voh.0. (Eq.From this.37 µsec Tload. the maximum network time constant (Tload.max / Voh.min))) = -1. of 1.max of 1.35 µsec satisfies both equations.max of 1.35 (ln(3.min / Vsup.min) = -Tload.35 µsec.35 µsec and a signal transition time Tt.max.80/5.25))) = 0. the signal transition time Tt.80/4. Given a maximum network time constant of 1.max / Vsup. D16) (Eq.81 µsec Bus (+): T(Voh. choosing a network time constant Tload.0.max)) = -2.20 .T(Voh.76 µsec Therefore.35 (ln(1-(1.max (for Bus -) or the time from Voh.max) = -Tload.25) = 1. Bus (-): T(Vol.max)) = -1.
PS100 V2.0
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