Source: http://www.google.com/patents/US7023731?dq=5,758,352
Timestamp: 2016-02-06 00:57:34
Document Index: 134120973

Matched Legal Cases: ['art 40', 'art 41', 'art 42', 'art 41', 'art 41', 'art 41', 'art 40', 'art 44', 'art 40', 'art 41', 'art 44', 'art 44', 'art 42', 'art 42', 'art 41', 'art 42', 'art 41', 'art 42', 'art 41', 'art 40']

Patent US7023731 - Semiconductor memory device and portable electronic apparatus - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor memory device including: a memory cell array in which memory cells are arranged; a plurality of terminals for accepting commands issued by an external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling...http://www.google.com/patents/US7023731?utm_source=gb-gplus-sharePatent US7023731 - Semiconductor memory device and portable electronic apparatusAdvanced Patent SearchPublication numberUS7023731 B2Publication typeGrantApplication numberUS 10/849,481Publication dateApr 4, 2006Filing dateMay 18, 2004Priority dateMay 20, 2003Fee statusLapsedAlso published asUS20050002240Publication number10849481, 849481, US 7023731 B2, US 7023731B2, US-B2-7023731, US7023731 B2, US7023731B2InventorsKoji Hamaguchi, Masaru Nawaki, Yoshinao Morikawa, Hiroshi Iwata, Akihide ShibataOriginal AssigneeSharp Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (7), Non-Patent Citations (1), Referenced by (8), Classifications (22), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor memory device and portable electronic apparatus
US 7023731 B2Abstract
A semiconductor memory device including: a memory cell array in which memory cells are arranged; a plurality of terminals for accepting commands issued by an external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling the programming and erasing operations; and an output circuit for outputting an internal signal to the plurality of terminals, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.
a plurality of terminals for accepting commands at least including commands related to programming and erasing operations on the memory cell array issued by an external user;
a command interface circuit for interfacing between the external user and the memory cell array;
a write state machine for controlling the programming and erasing operations on the memory cell array; and
an output circuit for outputting an internal signal to the plurality of terminals, wherein
the write state machine generates a ready signal indicating that the write state machine is not operating when the ready signal is active and indicating that the write state machine is operating when the ready signal is inactive, and an idle signal indicating that the write state machine is suspending the erasing operation when the idle signal is active, and includes a status register indicative of a status of the write state machine,
the command interface circuit includes a user state machine for controlling an operation of the write state machine via control signals including a program control signal and an erase control signal,
the user state machine analyzes a command accepted via the plurality of terminals, makes the program control signal active in the case where the command is a program command, makes the erase control signal active in the case where the command is an erase command, and makes the program control signal and the erase control signal inactive in the case where the command is not a valid command, thereby preventing an unexpected influence on the write state machine,
the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges,
the memory functional element is formed by at least any one of an insulating film including an insulator having the function of retaining charges, an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film of which inner charge is polarized by an electric field and in which the polarized state is held, and
the programming or erasing operation to selected one of the memory functional elements formed on both sides of the gate electrode can be executed independently from the other unselected one by controlling each voltage applied to the diffusion regions and the gate electrode.
the command interface circuit includes an output selection state machine for controlling information output from the output circuit to the external user, and
the output selection state machine analyzes the commands, the ready signal and the idle signal, in the case where the ready signal is inactive, generates a first output control signal so that a signal is not connected to the output circuit irrespective of the command and, in the case where the ready signal is active, when the idle signal is active and the command requests for information from the memory cell array, generates a second output control signal for connecting data from the memory cell array to the output circuit.
a signature signal indicative of signature information of the semiconductor memory device, wherein
the output selection state machine analyzes the command, the ready signal and the idle signal and, in the case where the ready signal is active, when the idle signal is inactive and the command is a command for outputting the signature information, generates a third output control signal for connecting the signature signal to the output circuit.
a test mode latch circuit for storing a test mode start bit which permits start of execution of a test mode when active and prevents start of execution of the test mode when inactive, wherein
the command interface circuit includes a test state machine for controlling the test mode latch circuit, and
the test state machine is connected to the plurality of terminals and the write state machine, analyzes the command to determine whether the command is a command of starting execution of the test mode or not, and responds to a command of starting execution of the test mode by making the test mode start bit active.
the command interface circuit includes a first latch circuit having an input terminal connected to the erase control signal and having an output terminal connected to the write state machine, and a second latch circuit having an input terminal connected to the program control signal and having an output terminal connected to the write state machine.
11. A display comprising the semiconductor memory device according to claim 1.
12. A portable electronic apparatus comprising the semiconductor memory device according to claim 1.
In a flash memory, as shown in FIG. 30, a floating gate 902, an insulating film 907 and a word line (control gate) 903 are formed in this order on a semiconductor substrate 901 via a gate insulating film. On both sides of the floating gate 902, a source line 904 and a bit line 905 are formed by a diffusion region, thereby configuring a memory cell. A device isolation region 906 is formed around the memory cell (see, for example, JP-A 05-304277 (1993)).
In such a flash memory, when the amount of charges in the floating gate changes, a drain current (Id)-gate voltage (Vg) characteristic as shown in FIG. 31 is exhibited. When the amount of negative charges in the floating gate increases, the threshold increases and the Id-Vg curve shifts almost in parallel in the Vg increasing direction.
In order to achieve the object, the present invention provides a semiconductor memory device including: a memory cell array in which memory cells are arranged in a matrix; a plurality of terminals for accepting commands at least including commands related to programming and erasing operations on the memory cell array issued by an external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling the programming and erasing operations on the memory cell array; and an output circuit for outputting an internal signal to the plurality of terminals, wherein the write state machine generates a ready signal indicating that the write state machine is not operating when the ready signal is active and indicating that the write state machine is operating when the ready signal is inactive, and an idle signal indicating that the write state machine is suspending the erasing operation when the idle signal is active, and includes a status register indicative of a status of the write state machine, the command interface circuit includes a user state machine for controlling an operation of the write state machine via control signals including a program control signal and an erase control signal, the user state machine analyzes a command accepted via the plurality of terminals, makes the program control signal active in the case where the command is a program command, makes the erase control signal active in the case where the command is an erase command, and makes the program control signal and the erase control signal inactive in the case where the command is not a valid command, thereby preventing an unexpected influence on the write state machine, and the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.
Further, by employing the write state machine which is generally employed by a conventional flash memory, optimizes and automates a complicated inner procedure in the programming and erasing operations and executes the procedure and, further, providing the command state machine for performing a proper control on the write state machine in order to reliably perform the programming and erasing operations on the memory cell array in the semiconductor memory device according to the present invention and assure the electric characteristics such as the data retaining characteristic and reliability, the interface between the external user and the memory cell array is simplified by a command input, and acceptance of various commands including commands related to the programming and erasing operations on the memory cell array issued by the external user and the complicated programming and erasing algorithm on the memory cell array can be performed automatically.
Further, by regulating a command input to the semiconductor memory device according to the present invention from the external user, the memory cell array can be prevented from being erroneously programmed or erased.
Further, in the semiconductor memory device according to the present invention, the command interface circuit includes an output selection state machine for controlling information output from the output circuit to the external user, and the output selection state machine analyzes the command, the ready signal and the idle signal, in the case where the ready signal is inactive, generates a first output control signal so that a signal is not connected to the output circuit irrespective of the command and, in the case where the ready signal is active, when the idle signal is active and the command requests for information from the memory cell array, generates a second output control signal for connecting data from the memory cell array to the output circuit.
The semiconductor memory device according to the present invention further includes a signature signal indicative of signature information of the semiconductor memory device, wherein the output selection state machine analyzes the command, the ready signal and the idle signal and, in the case where the ready signal is active, when the idle signal is inactive and the command is a command for outputting the signature information, generates a third output control signal for connecting the signature signal to the output circuit.
The semiconductor memory device according to the present invention further includes a test mode latch circuit for storing a test mode start bit which permits start of execution of a test mode when active and p prevents start of execution of the test mode when inactive, wherein the command interface circuit includes a test state machine for controlling the test mode latch circuit, and the test state machine is connected to the plurality of terminals and the write state machine, analyzes the command to determine whether the command is a command of starting execution of the test mode or not, and responds to a command of starting execution of the test mode by making the test mode start bit active.
In the semiconductor memory device according to the present invention, the command interface circuit includes a first latch circuit having an input terminal connected to the erase control signal and having an output terminal connected to the write state machine, and a second latch circuit having an input terminal connected to the program control signal and having an output terminal connected to the write state machine.
The semiconductor memory device according to the present invention can provide an interface between the external user and a mechanism for performing programming of the memory cell array or the like, an interface for controlling reading of information from the memory cell array, and an interface for a test function which is system controlled.
FIG. 6 is a diagram showing the erasing operation of the memory cell first embodiment) in the semiconductor memory device of the present invention;
FIG. 22 is a block diagram showing a configuration example of a peripheral circuit part for interfacing between an external user and a memory cell array in a semiconductor memory device (eleventh embodiment) of the present invention;
FIG. 23 is a block diagram showing a configuration example of a command state machine in the semiconductor memory device (eleventh embodiment) of the present invention;
FIG. 24 is a list showing the relations between states of the command state machine and output signals in the semiconductor memory device (eleventh embodiment) of the present invention;
FIG. 25 is a state transition diagram showing responses of a user state machine logic in the command state machine in the semiconductor memory device (eleventh embodiment) of the present invention;
FIG. 26 is a state transition diagram showing operations of an output selection state machine logic in the command state machine in the semiconductor memory device (eleventh embodiment) of the present invention;
FIG. 27 is a state transition diagram showing operations of a test state machine logic in the command state machine in the semiconductor memory device (eleventh embodiment) of the present invention;
FIG. 28 is a schematic configuration diagram of a liquid crystal display (twelfth embodiment) in which the semiconductor memory device of the present invention is assembled;
FIG. 29 is a schematic configuration diagram of a portable electronic apparatus (thirteenth embodiment) in which the semiconductor memory device of the present invention is assembled;
FIG. 30 is a schematic sectional view showing a main part of a conventional flash memory; and
FIG. 31 is a graph showing electric characteristics of the conventional flash memory.
A semiconductor memory device according to the present invention is mainly configured by a memory cell array in which memory cells are arranged in a matrix, a plurality of terminals for accepting commands at least including commands of programming and erasing operations on the memory cell array issued by the external user, a command interface circuit for interfacing between the external user and the memory cell array, a write state machine for controlling the programming and erasing operations on the memory cell array, and an output circuit for outputting internal signals to the plurality of terminals.
Apart of the diffusion region may extend at a level higher than the surface of the channel region, that is, the lower face of the gate insulating film. In this case, it is proper that, on the diffusion region formed in the semiconductor substrate, the conductive film is laminated so as to be integrated with the diffusion region. The conductive film is made of a semiconductor such as polysilicon or amorphous silicon, silicide, the above-mentioned metals, high-refractory metals, or the like. In particular, polysilicon is preferred. Since impurity diffusion speed of polysilicon is much faster than that of the semiconductor layer, it is easy to make the junction depth of the diffusion region in the semiconductor layer shallow and to suppress the short channel effect. In this case, preferably, a part of the diffusion region is disposed so as to sandwich at least a part of the memory functional element in cooperation with the gate electrode.
In the case where the requirement (9) is not satisfied, specifically, in the case where the electrode having the function of assisting the programming and erasing operations exists on the memory functional element, even if the requirement (6) is not satisfied, specifically, even if the insulator in the memory functional element and the dimension region do not overlap with each other, programming operation can be performed.
On the basis of the result of the device simulation, by fixing W2 to 100 nm and setting W1 to 60 nm and 100 nm as design values, memory cell arrays were produced. In the case where W1 is 60 nm, the silicon nitride film 242 and each of the diffusion regions 212 and 213 overlap with each other by 40 nm as a design value. In the case where W1 is 100 nm, there is no overlap as a design value. Reading time of the memory cell arrays was measured and worst cases in which variations were considered were compared with each other. In the case where W1 was set to 60 nm as a design value, read access time was 100 times as fast as that of the other case. In practice, the read access time is preferably 100 n/sec or less per one bit. When W1=W2, this condition cannot be satisfied. In the case of considering manufacture variations as well, it is more preferable that (W2−W1)>10 nm be satisfied.
As obvious from FIG. 19, in the case of performing a programming operation in an erasing state (solid line), not only the threshold simply increases, but the gradient of a graph remarkably decreases in a sub-threshold region. Consequently, also in a region where a gate voltage (Vg) is relatively high, the drain current ratio between the erasing state and the programming state is high. For example, also at Vg=2.5 V, the current ratio of two digits or more is maintained. The characteristic is largely different from that in the case of a flash memory (FIG. 31).
FIG. 20 shows an example of the configuration of a memory cell array 521. In FIG. 20, 501 aA1 to 501 aA4, 50laB1 to 501 aB4, . . . , and 501 nB1 to 501 nB4 denote memory cells, 508 a to 508 n denote word lines, and A1 to A5 and B1 to B5 denote bit lines. Each memory cell has two memory functional elements. In order to identify the memory functional elements, the arrows A and B are designated to the memory functional elements of only the memory cell 501 aA1, but are omitted to the other memory cells.
An embodiment of a semiconductor memory device of the present invention will now be described. The semiconductor memory device has, for example, a memory cell array as described in the tenth embodiment obtained by arranging a plurality of memory cells described in any of the first to eighth embodiments in a row direction and a column direction so as to form a matrix, and includes: a plurality of terminals for accepting commands at least including commands of programming and erasing operations on the memory cell array issued by the external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling the programming and erasing operations on the memory cell array; and an output circuit for outputting internal signals to the plurality of terminals. The external user herein refers to an external device (such as a CPU or other memory devices) connected to the semiconductor memory device of the present invention (hereinafter, properly referred to as “the inventive device”) via an external data bus and an external address bus to use the inventive device.
FIG. 22 is a block diagram showing the configuration of the inventive device 10. The term “command” in the following description will be used as a command commonly recognized in conventional flash memories. To be specific, the command is input as a digital signal to a data terminal of the inventive device when a control terminal of the inventive device is at a predetermined level. For example, an “array read” command represents an operation permitted by the inventive device by a combination of peculiar digital signals input to a data terminal of the inventive device. On the contrary, an invalid command is a combination of digital signals input to the data terminal and does not represent an operation permitted by the inventive device.
Assuming now that the inventive device 10 has eight data terminals, the number of invalid commands is larger than the number of valid commands. When eight data terminals are used, a part of the number of commands in 256 possible ways is used as valid commands (in the following description, the number of valid commands is only 14). In other words, the command state machine of the inventive device 10 recognizes a great number of invalid commands and prevents an unexpected influence of the invalid commands from being exerted on the inventive device.
As shown in FIG. 22, the inventive device 10 has a command state machine 11 as a main part of the present invention. The command state machine 11 functions as an interface between the external user and the inventive device 10. The inventive device 10 receives input data to data input/output terminals DIO0 to DIO7 denoted by a box 12 in a left upper portion of FIG. 22 and controls transfer of output data to the data input/output terminals DIO0 to DIO7. The inventive device 10 receives control signals by a plurality of terminals denoted by a box 14 shown in a left center portion of FIG. 22. The control signals are a chip enable signal CEB, a program enable signal WEB, an output enable signal OEB, a signal CE2 indicating that a low power state of the inventive device 10 is requested, and the like. Further, the inventive device 10 receives an address signal by a plurality of address input terminals A0 to A16 denoted by a box 15 shown in a left lower portion of FIG. 22.
A data signal received by the data input/output terminals DIO0 to DIO7 is transferred to a DLC circuit 17. The DLC circuit 17 includes a data latch circuit, a comparator, an input/output (RBUS) driver and an input buffer. In the case where the external user programs data to the memory cell array, the program data is stored in the data latch circuit in the DLC circuit 17 and is used by the remaining circuit portion of a write state machine 9 for controlling an actual programming (erasing) operation. The data latch circuit is controlled by the command state machine 11 of the present invention. The comparator in the DLC circuit 17 is used to compare data in the data latch circuit with data to be programmed in the memory cell array and recognize completion of the programming operation. The input/output (RBUS) driver is a test mode register bus driver and drives data to the inventive device 10 in a test mode of the inventive device 10. The input buffer is a buffer circuit for converting the signal level from an external input level of the inventive device 10 to a CMOS level in the inventive device 10. Data supplied to the DLC circuit 17 is either output to an R (input/output) bus to a test module latch or sent to the write state machine 9 under control of the command state machine 11.
An output signal of the inventive device 10 is transferred to the data input/output terminals DIO0 to DIO7 via an output circuit 19. The output circuit 19 has a drain bias circuit, a sense amplifier, an output driver and an output multiplexer. The drain bias circuit and the sense amplifier convert the level of current supplied by the memory cell array into a digital voltage level which can be transmitted to the outside of the inventive device 10. The output driver drives a signal on a terminal to a circuit on the outside of the inventive device 10. The output multiplexer determines a signal to be transmitted to the output driver so as to be transferred to the external circuit of the inventive device 10 under control of the command state machine 11. Outputs which can be transmitted include an output of the sense amplifier in the memory cell array, an output of the test mode register, a signature indicating that a specific chip is operating, and an output of the status register.
Control signals of the plurality of terminals denoted by the box 14 are transferred to a control input circuit 20. The control input circuit 20 includes an input level shifter, an input level buffer, logics of the input level shifter and the input level buffer, a test enable circuit, and a similar circuit using the inner control signals of the inventive device 10. A control signal from the control input circuit 20 is transferred to the command state machine 11 and the output circuit 19.
Address signals appearing at the address terminals A0 to A16 are transferred to two address input circuits 22 and 23. Each of the address input circuits 22 and 23 includes an address latch circuit, an address buffer, an address counter, and a circuit for addressing to the memory cell array. The address signal stored in the address latch circuit is transferred to an address bus (A bus) so as to be used.
A sync circuit 25 shown on the right side of the command state machine 11 synchronizes asynchronous control signals transferred between the command state machine 11 and the write state machine 9. The sync circuit 25 has a circuit for turning on/off a clock signal internally generated by an oscillation circuit (oscillator/phase generating circuit) 27 to the write state machine 9. Since the write state machine 9 is not frequently used, such an on/off control is preferable. It is preferable that, as a result, the power consumption of the inventive device 10 can be regulated when the write state machine 9 is not used.
The oscillator/phase generating circuit 27 is positioned below the sync circuit 25 in FIG. 22. The oscillation/phase generating circuit 27 has, as its name implies, an oscillator and a phase generator for generating two clock signals used in the write state machine 9.
A circuit 28 is a state machine, driver and switch circuit necessary for controlling operations of the other circuits in the write state machine 9. The circuit 28 executes various functions necessary for actual programming and erasing operations of the memory cell array.
A status register circuit 29 enables polling to the write state machine 9 so that the external user can determine the state of the write state machine 9. The command state machine 11 allows reading of the state in the status register circuit 29 when the write state machine 9 is in a busy state (operating) by the programming/erasing operations. The operation is the only another operation which can be executed during the programming and erasing operations.
Circuits 31 and 32 shown in a right lower portion of FIG. 22 are counter circuits for determining the number of pulses applied to the memory cell array during a specific programming or erasing operation and the width of a high-voltage pulse applied to the memory cell array during the programming or erasing operation.
Above the command state machine 11 in FIG. 22, a test mode circuit 34 having various test mode registers is provided. Reading/programming from/to the test mode registers in the test mode circuit 34 by the inventive device 10 is permitted via the command state machine 11 by using the R bus and the A bus. A high voltage interface circuit 36 shown in a right side of FIG. 22 supplies a signal necessary for programming/erasing to the memory cell array under control of the write state machine 9. A system state bus (S bus) provides a signal to the high voltage interface circuit 36 in a manner similar to the other circuits.
FIG. 23 is a block diagram showing the configuration of the command state machine 11. From the following description of functions of various state machine logics of the command state machine 11, a person skilled in the art will understand that the logic of the command state machine 11 can be embodied by a combination of logic gates or by using, for example, firmware or the like in which a micro code is stored for a memory device. A hardware configuration to realize the command state machine 11 is not important in the present invention. The command state machine 11 is configured by three circuit parts of an input part 40, a state machine logic part 41 and an output part 42. The state machine logic part 41 has a user state machine logic 43 for programming/erasing the memory cell array by the means of the write state machine 9 and for polling the status register 29 to determine the state of the write state machine 9. The state machine logic part 41 further includes an output selection state machine logic 46 for controlling the operation of the output multiplexer in the output circuit 19 shown in FIG. 22 to determine information output from the output circuit 19. The state machine logic part 41 further includes a test state machine logic 45 for controlling all of test modes of the inventive device 10 via the test mode circuit 34.
In the embodiment, for the operation of the inventive device 10, a set of eight commands executed by the user state machine logic 43 is provided to the external user. The eight commands are an “erase setup” command, a “program setup” command, a “clear status register” command, a “status register read” command, a “signature read” command, an “erase interrupt” command, an “erase resume” command and an “array read” command. In order to erase program data stored in a specific block in the memory cell array, input of two commands of the “erase setup” command and the subsequent “erase resume” command is requested. Similarly, in order to program or rewrite data into a specific block in the memory cell array, input of two commands of the “program setup” command and the subsequent data to be programmed and an address is requested. The “clear status register” command and the “status register read” command are used to clear/determine the state of the write state machine 9. The “signature read” command is used to transfer a signal indicative of a hardware product for specifying the inventive device 10 and a manufacturer thereof to the outside of the inventive device 10. When the “erase interrupt” command is used together with the “erase resume” command, an erasing operation requiring long time on a part of the memory cell array can be interrupted during a specific operation of the inventive device 10. Finally, by the “array read” command, data stored in the memory cell array can be read. Those commands are commands which can be used by a general user.
As test commands which are not released to a general user, there are a “test latch read” command, a “user mode read” command, a “test mode start” command, a “test mode stop” command and a “test latch program” command. Generally, the test commands are input to the test state machine logic 45 and the output selection state machine logic 46 and are necessary for processes of setting hardware configuring the inventive device 10 and testing the state. The test commands use a test mode latch circuit in the test mode circuit 34 to achieve a test of the memory cell array.
In addition to the “array read” command, a number of signals are generated in response to the operations of the user state machine logic 43, the inventive device 10, and the output selection state machine logic 46 for supplying a proper output from the memory cell array related to a specific operation being executed. This point will be described later in the embodiment.
In FIG. 23, input signals to which the command state machine 11 responds are shown on the left side of the input part 40. A CDWEB signal is a program enable control signal from the control input circuit 20 in FIG. 22. From the CDWEB signal, a number of internal clocks in the command state machine 11 are generated by a non-overlap clock generating circuit 47. WDDIN[7:0] signals are buffered data inputs from the data terminal 12 in FIG. 22. A user command is transferred via the data input to a logic part 44 in the input part 40 and the state machine logic part 41. A PDPWRDN signal input to the logic part 44 is a power down signal to set the inventive device 10 into a low power consumption state. A CDENTSTB signal input to the logic part 44 is an enable signal from the control input circuit 20 in FIG. 22 for accessing the test mode register in the test mode circuit 34.
A CDSETUP signal and a CDTWRITE signal are internal signals generated by the command state machine 11 in response to a user command indicative of a process to be executed. During erase and program setup operations, the CDSETUP signal is fed back to show that a first portion of a predetermined operation has been executed and the command state machine 11 waits for arrival of a second command of the operation. A WDREADY signal and a WDIDLE signal are signals generated by the write state machine 9 and used to synchronize output signals of the command state machine 11 and the write state machine 9 via an interface of the state machines. A signal on the A bus, a chip enable signal (CDCEB), an output enable signal (CDOEB), a program enable signal (CDWE1) and the program enable bar signal (CDWEB) are supplied to a logic circuit 48 in the output part 42 to control timings and use of various operations.
In response to the input signals, the logic circuit 48 in the command state machine 11 provides a CDALE signal and a CDDLE signal as an address in the write state machine 9 and a control signal for a data latch circuit. The logic circuit 48 further provides a CDABUSON (A bus on) signal, a CDLATRB (test latch read) signal, a CDLATWB (test latch program) signal, a CDGOMODE (test mode start) signal and a CDTWRITE (test mode program) signal. All of the signals are supplied for operations of the test mode latch circuit. A latch circuit group 49 in the output part 42 provides a CDERASE (erase) signal, a CDPROG (program) signal, a CDSUSP (suspend) signal and a CDSTATRS (status register reset) signal as output signals transmitted to the write state machine 9 to control the operation of the write state machine 9.
The various commands and signals referred to the above are transferred to the input terminals of the command state machine 11. The signals and commands generate a specific state as will be described later and exert an influence on the logic circuits of the three state machine logics 43, 45 and 46 for generating output signals. The input commands transferred to the state machine logic part 41 are latched by a number of state latches in a present state latch circuit 50 in the output part 42. Three present state latches expressed as NDLAT1, NDLAT2 and NDLAT3 in the present state latch circuit 50 latch a state for a user command. Two present state latches expressed as CDOUTMX1 and CDOUTMX0 latch a state for the output selection state machine logic 46. Two present state latches expressed as CDGOMODE and CDTWRITE latch a state for the test state machine logic 45. Some of the commands exert an influence on only one of the state machine logics 43, 45 and 46, and the other commands exert an influence on two of the state machine logics 43, 45 and 46.
FIG. 24 shows states provided in response to various input signals and commands supplied under rules to the state machine logic part 41. In response to the states listed under “name of state of user state machine logic 43”, the user state machine logic 43 sets the latches in the user state machine logic 43 to logic states listed in a second column group internal state) of the table of FIG. 24, and provides signals as shown in a third column group (output to other state machine) from the output part 42 to output lines. The logic states of the latches in the present state latch circuit 50 are read as follows. “0” in the first column indicates that the latch NDLAT1 is not set and “1” indicates that the latch is set. Similarly, data in the second and third columns also indicates the logic states of the latches NDLAT2 and NDLAT3. In a manner similar to the above, the states started by the output selection state machine logic 46 are listed in the left column in an intermediate level in the table of FIG. 24. A first figure and a second figure in the center column indicate the states of the latches CDOUTMX1 and CDOUTMX0 of the present state latch circuit 50 in a predetermined state for the output selection state machine logic 46. The states of the test state machine logic 45 are also similarly shown in the lower level in FIG. 24. The first column in the second column group (internal state) indicates the state of the latch CDGOMODE and the second column indicates the state of the latch CDTWRITE.
Based on the latch states, output signals are sequentially provided as shown in an output column (outputs to other state machines) on the right part of FIG. 24. For example, as a user state referred to on the basis of the latch state in the “internal state” column, output signals shown in the right five columns are provided. Herein, “1” indicates that an output signal is provided and “0” indicates that an output signal is not provided. The first output signal (left side) is the CDERASE signal, the second signal is the CDPROG signal, the third signal is the CDSTATRS signal, the fourth signal is the CDSUSP signal, and the fifth signal (right side) is the CDSETUP signal.
Each of the states created by the output selection state machine logic 46 is expressed by a combination of the bits of CDOUTMX0, CDOUTMX1 and CDOUTMX2. Each of the states 70, 72 and 71 (see FIG. 26) of ARRAY (array read), SIGNATURE (signature read), and STATUS (status register read) is determined by a combination of CDOUTMX0 and CDOUTMX1 irrespective of the state of the CDOUTMX2.
In the inventive device 10, a number of output terminals can be used, so that the number of possible combinations of outputs reaches a considerable number. Some of the combinations are undefined. For example, since an unpreferable operation in the write state machine 9 and the memory cell array may be caused, it is not desirable that an undefined combination of outputs exerts an influence on the inventive device 10. In the present invention, an undesirable, improper and unclear combination of control signals which may cause a problem during operation of the inventive device 10 and the built-in memory cell array is eliminated.
FIGS. 25, 26 and 27 are state transition diagrams of the state machines in the state machine logic part 41. Each portion surrounded by a square frame in FIGS. 25, 26 and 27 indicates a state of a specific state machine. A state name is indicated in the frame and corresponds to the state name shown in FIG. 24. A combination of a signal and a command related to make the state machine shift from a certain state to another state is generally indicated in text near a branch shown by an arrowed line. To an inactive signal, symbol “!” is attached in front of the name of the signal. Only a signal for making the state machine shift from a certain state to another state is indicated on the side of a branch. Specifically, in the case where a signal and a command “NOT” are indicated on the side of a branch, it is understood that no influence is exerted on determination of the state transition of the state machine in the operation of the state machine. There are exceptions in the state transition diagram of FIG. 26 as will be described later. As long as “NOT” is not indicated, in the case where there is no text on the side of a branch, it is understood that the state machine shifts to the next state irrespective of an input signal and an input command.
FIG. 25 is a state transition diagram showing responses of the user state machine logic 43 to various combinations of input signals and commands. When the inventive device 10 is activated, the user state machine logic 43 enters a “normal read” status 60. In order to shift from the status 60 to another status, the user state machine logic 43 has to receive a “clear status register” command, a “program setup” command or an “erase setup” command. By the other commands, the user state machine logic 43 remains in the “normal read” status 60 as expressed by input commands instructing the status 60. Even if any command except for the three valid commands is given, the user state machine logic 43 remain in the “normal read” status 60. As a result, a command erroneously generated by the user automatically sets the user state machine logic 43 into the “normal read” status 60. In the “normal read” status 60, none of the latches NDLAT1 to NDLAT3 is set. As a result, none of the output signals CDERASE, CDOROG, CDSTATRS, CDSUSP and CDSETUP is generated.
On the other hand, in the case where one of the valid commands is received, the user state machine logic 43 shifts from the “normal read” status 60 to a status corresponding to the command. For example, when the user state machine logic 43 receives the “clear status register” command in the “normal read” status 60, the user state machine logic 43 shifts to a “clear status” status 61. In the status 61, one output signal CDSTATRS transmitted to set the latch NDLAT3 and clear the status register circuit 29 is generated. In the “clear status” status 61, any of commands except for the valid “clear status register” command resets the user state machine logic 43 to the “normal read” status 60. For example, when a valid “erase resume” command is given after the “erase setup” command in the “clear status ” status 61, the user state machine logic 43 shifts to the “normal read” status 60.
The method of making the user state machine logic 43 shift to the “normal read” status 60 on receipt of an invalid command at a certain point in the operation of the command state machine 11 is a part of a method used so that the command state machine 11 does not certainly generate an invalid output status which may exert any influence on the memory cell array in the inventive device 10 or the other circuits.
When a valid “program setup” command is received in the “normal read” status 60 or the “clear status” status 61, the user state machine logic 43 shifts to a “program setup” status 62. As shown in FIG. 24, in the “program setup” status 62, the latch NDLAT2 is set, and the output signal CDSETUP is generated. The signal CDSETUP is fed back to the input part 40 of the command state machine 11 so that the next input to the command state machine 11 has to be interpreted not as a command but as a program address and program data during programming of the memory cell array by the write state machine 9.
After reception of the signal, to shift to a “program active” status 63, the user state machine logic 43 has to receive an address and data for programming the memory cell array. Because of the signal CDSETUP and the “program setup” status 62, only an address and data for programming the memory cell array are valid and any of data appearing at the terminals DIO0 to DIO7 is also used to program the memory cell array.
When data is received in the “program setup” status 62, the user state machine logic 43 shifts to the “program active” status 63, sets the latches NDLAT2 and NDLAT3 and generates the output signal CDPROG to be transferred to the write state machine 9. By the operation, the operation of programming the memory cell array under control of the write state machine 9 is started. During the period in which the write state machine 9 executes the operation of programming the memory cell array, the write state machine 9 returns a signal !WDREADY indicating that any command does not exert an influence on the user state machine logic 43 until the programming operation is completed to the command state machine 11. During the period, only a “status register read” command to the command state machine 11 exerts an influence on the output selection state machine logic 46 so as to detect the status of the write state machine 9.
When the write state machine 9 completes the operation of programming the memory cell array, the write state machine 9 returns the signal WDREADY to the command state machine 11, and the operation of the user state machine logic 43 waits for the next command input. When the next command input is received, if the command is the “clear status register” command, the user state machine logic 43 enters the “clear status” status 61. If the command is the “program setup” command, the user state machine logic 43 enters the “program setup” status 62. If the command is the “erase setup” command, the user state machine logic 43 enters the “erase setup” status 64. When a command other than the above is received, the user state machine logic 43 enters the “normal read” status 60.
If the “erase setup” command is given when the “erase setup” command is valid, the user state machine logic 43 shifts to an “erase setup” status 64. In the “erase setup” status 64, the latch NDLAT1 is set and the output signal CDSETUP is generated. In a manner similar to the “program setup” status, the signal CDSETUP indicates that a setup operation is being executed on the command state machine 11 by the write state machine 9 and any command other than the command of executing the setup operation is invalid in the setup operation. The only valid command on the user state machine logic 43 in the “erase setup” status 64 is the “erase resume” command for shifting the operation to an “erase active” status 65.
When an invalid command is received in the “erase setup” status 64, the operation shifts to an “erase failure” status 66 and all of the latches NDLAT1 to NDLAT3 are set. In the “erase failure” status 66, both of the signals CDERASE and CDPROG which are transferred to the write state machine 9. The write state machine 9 receives the two signals CDERASE and CDPROG and understands that the “erase resume” command was not accepted and an attempt of the erasing operation has failed. The write state machine 9 sets an error bit in the status register 29. Until the error bit is set, the write state machine 9 repeats sending back the signal !WDREADY and the user state machine logic 43 maintains the “erase failure” status 66. After a command error indication is stored in the status register 29, the write state machine 9 sends the signal WDREADY and the user state machine logic 43 waits for the next command input.
When the “erase resume” command is received in the “erase setup” status 64, the operation shifts to the “erase active” status 65. In the “erase active” status 65, the latches NDLAT1 and NDLAT3 are set, and the output signal CDERASE to be transferred to the write state machine 9 is generated. The signal CDERASE starts the erasing operation under control of the write state machine 9. The write state machine 9 generates the signal !WDREADY to the user state machine logic 43 so that commands other than the “erase suspend” command are ignored during the period of the erasing operation, and the user state machine logic 43 remains in the “erase active” status 65. After completion of the erasing operation, the write state machine 9 sends back the signal WDREADY and the user state machine logic 43 waits for another command input.
In order to erase all of the blocks in the memory cell array, considerable time is required. There is consequently a case that it is preferable to suspend the erasing operation in order to execute another command which does not interfere the erasing operation. When the write state machine 9 accepts the “erase suspend” command in the “erase active” status 65 in which the signal !WDREADY is provided, the operation shifts to an “erase suspend” status 67. In the “erase suspend” status 67, the latches NDLAT1 and NDLAT2 are set, and both of the signals CDERASE and CDSUSP which are transferred to the write state machine 9 are generated. When the signal !WDREADY (indicating that the erasing operation is not completed yet) or a signal WDIDLE is returned in the status, the “erase suspend” command resets the user state machine logic 43 into the “erase active” status 65. As long as the write state machine 9 does not indicate occurrence of suspension on completion of the erasing operation, the user state machine logic 43 remains in the “erase suspend” status 67 until the “erase resume” command is received. The write state machine 9 indicates occurrence of suspension on completion of the erasing operation by sending back the signals WDREADY and !WDIDLE. In response to this, the user state machine logic 43 shifts to the “normal read” status 60.
FIG. 26 is a state transition diagram showing operations of the output selection state machine logic 46 in the command state machine 11. FIG. 26 shows predetermined states in which the output selection state machine logic 46 can be shifted among the statuses 70, 71 and 72, but does not show all of states in which the output selection state machine logic 46 is shifted from the statuses 70, 71 and 72 to the other statuses. Therefore, it should be understood that if a condition under which the output selection state machine logic 46 enters a certain status is true in a second status, the condition is a condition under which the output selection state machine logic 46 goes out from the second status. Assuming now that the output selection state machine logic 46 enters the status 71 in response to the signal !WDREADY, it is to be understood that the signal !WDREADY makes the output selection state machine logic 46 shift from the statuses 70 and 72 to the status 71. When the inventive device 10 is started, the operation of the output selection state machine logic 46 enters the “array read” status 70, and the output multiplexer of the output circuit 19 in FIG. 22 is activated so as to transfer data from the memory cell array. In the “array read” status 70, any of the latches CDOUTMX0 and CDOUTMX1 is not set and no output signal is generated.
When the test mode command is received in the “array read” status 70, the “status register read” status 71 or the “signature read” status 72, the output selection state machine logic 46 shifts to the “test mode” status 73. This is indicated by the sign “ATMC (which denotes any test mode command)” below the statuses 70, 71 and 72 in FIG. 26. In the status 72, the output multiplexer in the output circuit 19 is usually set so as to read an output of a result of a test mode operation. The operation uses the R bus (input/output bus) connected to the test mode register. In order to determine if a result of the test mode operation or a data latch is detected, an address on the A bus is detected. If the address on the A bus is other than “F” in hexadecimal notation, a result of the test mode operation is read. If the address on the A bus is “F” in hexadecimal notation, the data latch is read. In the “test mode” status 73, only the “user mode read” command transfers the output selection state machine logic 46 to any one of the user statuses 70, 71 and 72.
With respect to the commands except for one test mode command, the status of the output selection state machine logic 46 depends on the status of the write state machine 9. When the inventive device 10 starts the output selection state machine logic 46 in the “array read” status 70, the write state machine 9 does not perform programming nor erasing but sends back the signal WDREADY as a result. If the operation of the write state machine 9 is not suspended to return the signal !WDREADY, the “signature read” command sets the output selection state machine logic 46 into the “signature read” status 72, and the “status register read” command sets the output selection state machine logic 46 into the “status register read” status 71. In addition to the direct shifting operations, the “erase setup” and “program setup” commands make the output selection state machine logic 46 enter the “status register read” status 71 for the reason that after the write state machine 9 starts the erasing or programming operation, reading of the status register is only a safe operation which can be achieved. Once the write state machine 9 performs programming or erasing, as a result, the signal !WDERADY is returned to the output selection state machine logic 46 in the “status register read” status 71, and any command which is not test mode command makes the output selection state machine logic 46 maintain in the “status register read” status 71. This situation is expressed by a loop “!wdready&!TMC” starting from the “status register read” status 71 and returning to the status 71. The expression of !TMC denotes an arbitrary command other than the test mode command. The “status register read” status 71 is the only valid status of the output selection state machine logic 46 in the operation period by the write state machine 9. In the “status register read” status 71, the latch CDOUTMX1 is set and the status of the inventive device 10 is polled.
On the other hand, in the case where the write state machine 9 does not perform the programming and erasing operations so that the signal WDREADY is sent back, if the signal WDIDLE is sent back, the operation of the memory cell array is suspended, and the “status register read” or “erase resume” command is received, the output selection state machine logic 46 shifts to the “status register read” status 71. This situation is represented by an expression “(wdidle&wdready)*(read status or erase resume)” indicated on the side of one of branches into the “status register read” status 71 in FIG. 26. The reason why the output selection state machine logic 46 shifts to the “status register read” status 71 is obvious in the case of the “status register read” command. However, in the case of the “erase resume” command, the write state machine 9 performs the operation of erasing the memory cell array after that, so that the “status register read” status 71 will become the only possible status. That is, like the user state machine logic 43, the output selection state machine logic 46 resets its status to a status in which an output other than an expected output is not executed even if an erroneous command appears.
In the case where the write state machine 9 does not perform the programming and erasing operations so that the signal WDREADY is sent back, and the signal WDIDLE indicative of suspension of the operation of the memory cell array is sent back, when a command other than the “status register read” command and the “erase resume” command, the output selection state machine logic 46 shifts to the “array read” status 70. This situation is indicated by an expression “(wdidle&wdready)*(command other than read status or erase resume)” indicated on the side of one of branches into the “array read” status in FIG. 26. In such a status, transfer of data read from the memory cell array by the output multiplexer controlled by the output selection state machine logic 46 is a safe operation.
Similarly, if the signal WDREADY (indicating that the write state machine 9 is not performing the programming operation or the erasing operation) and the signal !WDIDLE (indicating that the write state machine 9 is not suspended) appear when the command is the “array read” command or a command other than the “signature read”, “erase setup”, “program setup” and “status register read” commands, the output selection state machine logic 46 shifts to the “array read” status 70. In short, whenever the write state machine 9 is not suspended but does not perform the programming or erasing operation and receives an invalid command, the output selection state machine logic 46 shifts to the “array read” status 70. This status is indicated by an expression “(wdready&wdidle)*(read array or command other than read signature, erase setup, program setup, and read status)” indicated on the side of one of branches into the “array read” status 70 in FIG. 26.
Therefore, as with the user state machine logic 43, the output selection state machine logic 46 returns to the status in which no command can exert an unexpected influence on the inventive device 10. When the write state machine 9 is performing the programming or erasing operation, an arbitrary command makes the output selection state machine logic 46 shift to the “status register read” status 71. This situation is indicated by an expression “wdready” indicated on the side of one of branches into the “status register read” status 71 in FIG. 26. In the case where the write state machine 9 does not perform the programming or erasing operation, all of the “erase setup”, “program setup” and “status register read” commands make the output selection state machine logic 46 shift to the “status register read” status 71. When the operation of the write state machine 9 is suspended during the erasing operation, the “status register read” and “erase resume” commands reset the output selection state machine logic 46 to the safe “status register read” status 71. On the other hand, the other commands shift the operation of the output selection state machine logic 46 to the “array read” status 70 in which data is read from the memory cell array during suspension of the erasing operation. Finally, when the write state machine 9 is not performing the programming or erasing operation and the erasing operation is not suspended, the “array read” command and arbitrary invalid commands transfer the output selection state machine logic 46 to the “array read” status 70 in which only reading of the memory cell array is possible.
As a result, the operations of the two state machine logics 43 and 46 are associated with each other so that the output selection state machine logic 46 does not respond to an invalid command or invalid information is transferred during the period in which the write state machine 9 is performing the operation of programming or erasing the memory cell array. In the method, even if the user gives an invalid command to the inventive device 10, the possibility that the invalid command is transmitted from the command state machine 11 to the write state machine 9 is eliminated by the above-described setting and status.
FIG. 27 shows operations of the test state machine logic 45 in FIG. 23. The test state machine logic 45 is activated in a “non-start” status 75. In the “non-start” status 75, a “test latch program” command makes the test state machine logic 45 shift to a “test program setup non-start” status 76. After a test address and data is programmed, the test state machine logic 45 returns to the “non-start” status 75. The operation loop from the “non-start” status 75 to the “test program setup non-start” status 76 is usually executed a few times until all of test latches are set and setup is completed. If a “test program setup” or “test mode start” command is not received in the “non-start” status 75, the operation simply repeats the “non-start” status 75.
If a “test mode start” command is given in a standby status in which a setup test can be executed, the status of the test state machine logic 45 shifts from the “non-start” status 75 to a “start” status 78. In the “start” status 78, the latch CDGOMODE is set and a specific test mode is executed. In the “start” status, the test state machine logic 45 can accept a “test program setup” command for transferring the test state machine logic 45 to a “test program setup start” status 79. After the latch CDGOMODE is programmed, the test state machine logic 45 returns to the “start” status 78 and executes an arbitrary test mode which has been set up before. The test state machine logic 45 remains in the “start” status 78 until a “test mode stop” command is received. When the “test mode stop” command is received, the test state machine logic 45 returns to the “non-start” status 75.
As described above, various commands used for the operation of the test state machine logic 45 exert an influence to control the output multiplexer so that the output selection state machine logic 46 can evaluate a result of the test mode operation.
As an application example of the semiconductor memory device, for example, as shown in FIG. 28, a rewritable nonvolatile memory for image adjustment of a liquid crystal panel can be mentioned.
The liquid crystal driver 1002 may be externally attached to the liquid crystal panel 1001 as shown in FIG. 28 or formed on the liquid crystal panel 1001.
FIG. 29 shows a portable telephone as a portable electronic apparatus in which the semiconductor memory device is assembled.
In the semiconductor memory device of the present invention, an interface between the external user and the memory cell array is simplified by a command input. Acceptance of various commands including commands related to operations of programming/erasing the memory cell array issued by the external user and a complicated programming/erasing algorithm on the memory cell array can be performed automatically. Further, by regulating a command input to the semiconductor memory device according to the present invention from the external user, the memory cell array can be prevented from being erroneously programmed or erased.
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