Source: http://patents.com/us-9851913.html
Timestamp: 2018-06-20 17:20:18
Document Index: 154226995

Matched Legal Cases: ['art 100', 'art 100', 'art 200', 'art 200', 'art 300', 'art 300', 'art 300']

US Patent # 9,851,913. Methods for operating a memory array - Patents.com
United States Patent 9,851,913
Bedeschi , et al. December 26, 2017
Methods for operating a memory array
Bedeschi; Ferdinando (Biassono, IT), Resta; Claudio (Pavia, IT), Ferraro; Marco (Lecce, IT)
Family ID: 1000003029131
15/012,478
US 20160162213 A1 Jun 9, 2016
13518361 9251897
PCT/IT2009/000603 Dec 31, 2009
Current CPC Class: G06F 3/0622 (20130101); G06F 3/0643 (20130101); G06F 3/0679 (20130101); G11C 13/0004 (20130101); G11C 13/004 (20130101); G11C 13/0069 (20130101); G11C 13/0097 (20130101); G11C 13/02 (20130101); H01L 45/06 (20130101); G11C 13/0059 (20130101); H01L 45/04 (20130101)
Current International Class: G11C 11/00 (20060101); G11C 13/00 (20060101); G06F 3/06 (20060101); H01L 45/00 (20060101); G11C 13/02 (20060101)
Field of Search: ;365/163,189.011,189.15,189.16,189.09
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1. A method of operating a memory array, the method comprising: determining a pattern to be written to the memory array, the determined pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored; writing the determined pattern to the memory array; providing a write password; and erasing the determined pattern from the memory array if the write password is incorrect.
4. The method of claim 2, wherein the one or more hard reset pulses are to allow writing a logical "0," and the one or more soft reset pulses are to allow writing a logical "1" to selected ones of the cells in the memory array.
10. A method of operating a memory array, the method comprising: executing a set sequence on the memory array prior to performing the read of the memory array, the set sequence comprising an all-zero pattern target for the memory array, the pattern being a non-all-zero pattern; performing a read of the memory array to obtain a pattern derived from executing the set sequence, and obtain an additional pattern comprising both real data hits having sensitive information to he stored and data bits having a state that is unimportant to the sensitive information to be stored; and adjusting an internal read reference to maintain a margin for obtaining the additional pattern.
12. The method of claim 10, further comprising: executing a set sequence on the memory array prior to performing the read of the memory array, the set sequence comprisimg a first pattern target for the memory array, the pattern being a second pattern different from the first pattern; and performing the read of the memory array to obtain a pattern derived from executing the set sequence.
15. The method of claim 10, further comprising: issuing a read password prior to performing the read of the memory array; and comparing the read password with information stored in a programmable memory to verify a validity of the read password.
18. A tangible computer-readable medium having no transitory signals and containing instructions that, when executed by one or more hardware-based processors of a machine, cause the machine to perform operations comprising: determining a pattern to be written to the memory array, the determined pattern comprising both data bits having sensitive information to be stored and data hits having a state that is unimportant to the sensitive information to be stored; writing the determined pattern to the memory array; providing a write password; and erasing the determined pattern from the memory array if the write password is incorrect.
19. A tangible computer-readable medium having no transitory signals and containing instructions that, when executed by one or more hardware-based processors of a machine, cause the machine to perform operations comprising: executing a set sequence on the memory array prior to performing the read of the memory array, the set sequence comprising an all-zero pattern target for the memory array, the pattern being a non-all-zero pattern; performing a read of the memory array to obtain a pattern derived from executing the set sequence, the pattern comprising both real data bits having sensitive information to be stored and data hits having a state that is unimportant to the sensitive information to he stored; and adjusting an internal read reference to maintain a margin for obtaining the pattern.
20. A method of operating a memory array, the method comprising: executing a set sequence on the memory array prior to performing the read of the memory array, the set sequence comprising a first pattern target for the memory array, the pattern being a second pattern different from the first pattern; performing a read of the memory array to obtain a pattern derived from executing the set sequence and obtain an additional pattern comprising both real data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored; and adjusting an internal read reference to maintain a margin for obtaining the additional pattern.
21. A tangible computer-readable medium having no transitory signals and containing instructions that, when executed by one or more hardware-based processors of a machine, cause the machine to perform operations comprising: executing a set sequence on the memory array prior to performing the read of the memory array, the set sequence comprising a first pattern target for the memory array, the pattern being a second pattern different from the first pattern; performing a read of the memory array to obtain a pattern derived from executing the set sequence and obtain an additional pattern comprising both real data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored; and adjusting an internal read reference to maintain a margin for obtaining the additional pattern.
This application claims the benefit of priority from U.S. Ser. No. 13/518,361, now issued as U.S. Pat. No. 9,251,897, filed Sep. 30, 2013, and entitled, "METHODS FOR A PHASE-CHANGE MEMORY ARRAY,"which was a U.S. National-Phase Filing under 35 U.S.C. .sctn.371 from International Patent Application Ser. No. PCT/IT2009/000603, filed Dec. 31, 2009, and published as WO 2011/080784 A1 on Jul 7, 2011, each of which is incorporated herein by reference in its entirety.
FIG. 4 includes plots of program pulse amplitude for logic "1" as a function of time and program pulse amplitude for logic "0" as a function of time, in accordance with an embodiment of the present invention.
FIG. 5 includes plots of cell current for logic "1" as a function of time and cell current for logic "0" as a function of time, in accordance with an embodiment of the present invention.
In accordance with embodiments of the present invention, cryptographic methods based on reset and set operations for phase-change memory (PCM) devices are described. Such method may be based on the capability to differentiate the reset (e.g., to hide information with hard or soft pulses) in order to define proper starting conditions for different set states (e.g., to restore information). In an embodiment, PCM cells are reset with different pulse amplitudes, providing a simpler or harder set ability, once a given set pulse is fixed. A logical value may be associated with a given reset amplitude. If a set is then delivered, this logical value may or may not switch. In an embodiment, such an approach leads to "hidden" information. A "fake" reset, e.g. an all zero write command, may be used in such a case after having sent, to the memory, a given pattern to be hidden. For example, starting from an all-zero pattern, after a set pulse, some of the bits which were initially read as 0s will flip to 1, while others will not, thus unveiling the real data pattern (e.g., (b7, . . . b0)=00000000.fwdarw.10011011). In the example, bit6, bit5, bit2 have seen an harder reset than bit7, 4, 3, 1, 0. In this case, 10011011 is the pattern sent to the memory which has to be hidden. Then, a write All zero command may be sent to the memory or may eventually be executed by the internal state machine without additional commands as a consequence of the request of hiding a pattern. This approach provides a reset sequence of proper magnitude in accordance with the logic state of the bits of the pattern to be hidden and into a hidden pattern equal to 00000000 after completion of the sequence.
In accordance with an embodiment of the present invention, a cryptographic method is based on the capability to differentiate the reset (e.g., to hide information) in order to define proper starting conditions resulting in different set states (e.g., to restore info) and, ultimately, in different data read. The pattern may be hidden by a reset operation where, e.g., a logical 0, after decryption, is obtained by a hard reset, while a logical 1, after decryption, results from a soft reset. In an embodiment, the pattern before decryption appears like an all-zero 0 pattern. Starting from the all-zero pattern, after a set pulse, some of the bits which initially have been read as 0s will flip to 1s, some others will not, unveiling the real data pattern. The addresses of the patterns may be fixed inside a one-time-programmable memory by the final customer or by the manufacturer, or by both. In an embodiment, an additional data protection level is provided in case a password is somehow cracked and an array content is undesirably read-out. In a specific embodiment, unless a "fake" set, e.g. an "all 1" write command, is not issued, the real content stays hidden inside the pattern. On the other hand, this approach may provide a way to, without digital password, "erase" a word and force a real pattern to appear.
Referring to operation 106 of Flowchart 100, the method of operating a phase-change memory array also includes executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. In accordance with an embodiment of the present invention, a first one of the proper reset sequences has a first amplitude, and a second one of the proper reset sequences has a second amplitude different from the first amplitude. In one embodiment, the first one of the proper reset sequences is to write a logical "0," and the second one of the proper reset sequences is to write a logical "1." In a specific embodiment, writing the pattern to the phase-change memory array is performed by an internal slate machine. In an embodiment, the method including operations 104 and 106 is for encrypting the phase-change memory array.
Referring to operation 102 of Flowchart 100, the method of operating a phase-change memory array may optionally, in an embodiment, further include issuing a proper write password, and executing the two or more proper reset sequences includes providing the proper write password. In a specific embodiment, the proper write password is compared with information stored in one-time-programmable memory, e.g. such as a password stored by a manufacturer upon a customer request. In an embodiment, a wrong password or sequence generates a "real" erase of the pattern by selecting a very long set pulse such as, but not limited to, a set sweep or a stair case down.
Referring to operation 206 of Flowchart 200, the method of operating a phase-change memory array also includes performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence. In accordance with an embodiment of the present invention, executing the set sequence on the phase-change memory array includes executing the set sequence with an all-zero pattern target for the phase-change memory array, and the pattern is a non-all-zero pattern. In an embodiment, executing the set sequence on the phase-change memory array includes executing the set sequence with a first pattern target for the phase-change memory array, and the pattern is a second pattern different from the first pattern. In an embodiment, the method includes adjusting an internal read reference to maintain a margin for obtaining the pattern. In a specific embodiment, the internal read reference current is slightly increased. In an embodiment, the method including operations 204 and 206 is for decrypting the phase-change memory array. In an embodiment, a "pattern target" is the pattern stored into the location which can eventually be read before the issuing of the sequence which in turn becomes the "pattern" after the sequence, if eventually read.
Referring to operation 202 of Flowchart 200, the method of operating a phase-change memory array may optionally, in an embodiment, further include issuing a proper read password, wherein performing the proper read includes providing the proper read password. In a specific embodiment, the proper read password is compared with information stored in one-time-programmable memory. In an embodiment, a wrong password or sequence generates a "real" erase of the pattern by selecting a very long set pulse such as, but not limited to, a set sweep or a stair ease down. In another optional embodiment, the method further includes, subsequent to performing the proper read, executing two or more proper reset sequences on the phase-change memory array to re-hide the pattern in the phase-change memory array.
Referring to operation 306 of Flowchart 300, the method of operating a phase-change memory array also includes executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. In accordance with an embodiment of the present invention, a first one of the proper reset sequences has a first amplitude, and a second one of the proper reset sequences has a second amplitude different from the first amplitude. In one embodiment, the first one of the proper reset sequences is to write a logical "0," and the second one of the proper reset sequences is to write a logical "1." In a specific embodiment, writing the pattern to the phase-change memory array is performed by an internal state machine.
Referring to operation 302 of Flowchart 300, the method of operating a phase-change memory array may optionally, in an embodiment, further include issuing a proper write password, and executing the two or more proper reset sequences includes providing the proper write password. In a specific embodiment, the proper write password is compared with information stored in one-time-programmable memory, e.g. such as a password stored by a manufacturer upon a customer request. Furthermore, referring to operation 308 of Flowchart 300, the method of operating a phase-change memory array may optionally, in an embodiment, further include issuing a proper read password, wherein performing the proper read includes providing the proper read password. In a specific embodiment, the proper read password is compared with information stored in one-time-programmable memory. In an embodiment, a wrong password (proper read password, proper write password, or both) or sequence generates a "real" erase of the pattern by selecting a very long set pulse such as, but not limited to, a set sweep or a stair case down. In another optional embodiment, the method further includes, subsequent to performing the proper read, executing two or more proper reset sequences on the phase-change memory array to re-hide the pattern in the phase-change memory array.
FIG. 4 includes plots 400 of program pulse amplitude for logic "1" as a function of time and program pulse amplitude for logic "0" as a function of time, in accordance with an embodiment of the present invention.
Referring to FIG. 4, the plot on the left side represents program pulse amplitude for logic "1" as a function of time. A soft reset (Ireset soft) is performed, consistent with a less resistive phase-change memory cell. The plot on the right side represents program pulse amplitude for logic "0" as a function of time. A hard reset (Ireset hard) is performed, consistent with a more resistive phase-change memory cell.
FIG. 5 includes plots 500 of cell current for logic "1" as a function of time and cell current for logic "0" as a function of time, in accordance with an embodiment of the present invention.
Referring to FIG. 5, the plot on the left side represents cell current for logic "1" as a function of time. A relatively high current read (Iread) is sunk under given read bias conditions, relative to the set current (Iset). The plot on the right side represents cell current for logic "0" as a function of time. A relatively low current read (head) is sunk under given read bias conditions, relative to the set current (Iset). Iset is selected to be sufficient to set a less resistive phase-change memory cell, but not a more resistive phase-change memory cell.
In an aspect of the present invention, a phase-change memory cell array includes memory cells that are composed of a storage material in combination with a selector device. For example, FIG. 6 illustrates an array 610 of phase-change memory cells 604, in accordance with an embodiment of the present invention. In an embodiment, array 610 includes phase-change memory cells composed of alloys of elements of group VI of the periodic table, elements such as Te or Se that are referred to as chalcogenides or chalcogenic materials. Chalcogenides may be used advantageously in phase change memory cells to provide data retention and remain stable even after the power is removed from the nonvolatile memory. Taking the phase change material as Ge.sub.2Sb.sub.2Te.sub.5 for example, two phases or more are exhibited having distinct electrical characteristics useful for memory storage. Array 610 includes phase-change memory cells each having a selector device and a memory element. Although the array is illustrated with bipolar selector devices, it should be noted that alternative embodiments may use CMOS selector devices or diodes to identify and selectively change the electrical properties (e.g. resistance, capacitance, etc.) of the chalcogenide material through the application of energy such as, for example, heat, light, voltage potential, or electrical current. The chalcogenic material may be electrically switched between different states intermediate between the amorphous and the crystalline states, thereby giving rise to a multilevel storing capability. To alter the state or phase of the memory material, this embodiment illustrates a programming voltage potential that is greater than the threshold voltage of the memory select device that may be applied to the memory cell. An electrical current flows through the memory material and generates heat that changes the electrical characteristic and alters the memory state or phase of the memory material.
By way of example, heating the phase-change material to a temperature above 900.degree. C. in a write operation places the phase change material above its melting temperature (T.sub.M). Then, a rapid cooling places the phase-change material in the amorphous state that is referred to as a reset state where stored data may have a "0" value. Taking Ge.sub.2Sb.sub.2Te.sub.5 as an example, the time between achieving the melting temperature Tm and quenching after the local heating to achieve the amorphous phase may be less than 50 nanoseconds. On the other hand, to program a memory cell from reset to set, the local temperature is raised higher than the crystallization temperature (Tx) for a time longer than 50 nanoseconds (for Ge.sub.2Sb.sub.2Te.sub.s) to allow complete crystallization. The phase-change material in the crystalline form is referred to as a set state and stored data may have a "1" value. Thus, the cell can be programmed by setting the amplitude and pulse width of the current that will be allowed through the cell. In summary, a higher magnitude, fast pulse will amorphize the cell, whereas a moderate magnitude, longer pulse will allow the cell to crystallize. In a read operation, the bit line (BL) and word line (WL) are selected and an external voltage bias is provided to the selected memory cell. To read a chalcogenide memory device, the current difference between the cell current and a given reference current resulting from the different device resistance is sensed. It is then determined whether data stored in the selected memory cell is a "1" or "0" based on that current difference change caused by a resistance of the phase-change material of the selected memory cell. It is to be appreciated that the association of reset and set with amorphous and crystalline states, respectively, is a convention and that at least an opposite convention may be adopted. Also, other methods for reading the resistance (i.e. the state) may be implemented, such as forcing a current and reading a voltage or pre-charging a capacitance and discharging it thru the cell. The above described approaches are not necessarily dependent on the way the data is read.
In an embodiment, the present invention is provided as a computer program product, or software product, that includes a machine-readable medium having stored thereon instructions, which is used to program a computer system (or other electronic devices) to perform a process according to embodiments of the present invention. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, in an embodiment, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.)), etc. In an embodiment, use of the term "computer-implemented" herein means processor-implemented. In one embodiment, one of the methods described herein is implemented in a portable device, such as a cellular phone, which does not have a computer per se but does have a processor.
FIG. 8 illustrates a diagrammatic representation of a machine in the form of a computer system 800 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, is executed. For example, in accordance with an embodiment of the present invention, FIG. 8 illustrates a block diagram of an example of a computer system configured for encrypting or decrypting, or both, a phase-change memory array. In alternative embodiments, the machine is connected (e.g., networked) to other machines in a Local Area Network (LAN), an intranet, an extranet, or the Internet. In an embodiment, the machine operates in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. In an embodiment, the machine is a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines (e.g., computers or processors) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.
While the machine-accessible storage medium 831 is shown in an embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of embodiments of the present invention. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.
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