Source: http://www.google.com/patents/US8117392?ie=ISO-8859-1&dq=inventor:%22Arthur+R.+Hair%22
Timestamp: 2014-08-30 19:15:22
Document Index: 561919505

Matched Legal Cases: ['Application No. 200480038473', 'Application No. 200480038473', 'Application No. 10', 'Application No. 11', 'Application No. 11', 'Application No. 11', 'Application No. 10', 'Application No. 200480038473']

Patent US8117392 - Method and apparatus for efficient ordered stores over an interconnection ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA physically distributed cache memory system includes an interconnection network, first level cache memory slices, and second level cache memory slices. The first level cache memory slices are coupled to the interconnection network to generate tagged ordered store requests. Each tagged ordered store...http://www.google.com/patents/US8117392?utm_source=gb-gplus-sharePatent US8117392 - Method and apparatus for efficient ordered stores over an interconnection networkAdvanced Patent SearchPublication numberUS8117392 B2Publication typeGrantApplication numberUS 10/691,176Publication dateFeb 14, 2012Filing dateOct 22, 2003Priority dateOct 22, 2003Also published asCN1898653A, CN100530141C, US20050091121Publication number10691176, 691176, US 8117392 B2, US 8117392B2, US-B2-8117392, US8117392 B2, US8117392B2InventorsMark J. Charney, Ravi Rajwar, Pritpal S. Ahuja, Matthew C. MattinaOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (21), Non-Patent Citations (19), Classifications (12), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethod and apparatus for efficient ordered stores over an interconnection networkUS 8117392 B2Abstract A physically distributed cache memory system includes an interconnection network, first level cache memory slices, and second level cache memory slices. The first level cache memory slices are coupled to the interconnection network to generate tagged ordered store requests. Each tagged ordered store requests has a tag including requester identification and a store sequence token. The second level cache memory slices are coupled to the interconnection network to execute ordered store requests in-order across the physically distributed cache memory system in response to each tag of the tagged ordered store requests.
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Feb. 1, 1989.3First Office Action from counterpart China Patent Application No. 200480038473.5, mailed Oct. 10, 2007, 1 page.4Gharachorlon, K., et al., "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors," IEEE, 1990.5H. Cheong & A. Veidenbaum, "A Version Control Apporach to Cache Coherence," Proceedings of the International Conference on Supercomputing 89, Jun. 1989, pp. 322-330.6I. Tartalia et al., "A Survey of Software Solutions for Maintenance of Cache Consistency in shared Memory Multiprocessors," Proceedings of the 28th Annual Hawaii Int'l Conference on System Sciences, 1995, pp. 272-282.7Intel IXP1200 Network Processor Datasheet, pp. 9, 10, & 55, 2001.8Intel IXP1200 Network Processor Family, The Goundation of a Total Development Environment for Next-Generation Networks, Product Brief, Order No. 279040-001, 2001.9Jim Handy, The Cache Memory Book, pp. 140-158, Academic Press, Inc. San Diego, CA 1993.10John L. Hennessy, David A. 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Gharachorloo et al., "Memory Consistency and Event Ordering in Scalable Shared-Memroy Multiprocessors," Computer Systems Laboratory, Stanford University, CA 94305, May 28, 1990, pp. 15-26.12Notice of Grant of Patent Right For Invention Office Action from counterpart China Patent Application No. 200480038473.5, mailed Apr. 20, 2009, 2 pages.13Notice of Preliminary Rejection from counterpart German Patent Application No. 10-2006-7007706, mailed Aug. 21, 2007, 8 pages.14Office Action from counterpart German Patent Application No. 11 2004 001 984.2-53, mailed Feb. 19, 2008, 7 pages.15Office Action from counterpart German Patent Application No. 11 2004 001 984.2-53, mailed May 10, 2010, 5 pages.16Office Action from counterpart German Patent Application No. 11 2004 001 984.2-53, mailed Sep. 17, 2007, 6 pages.17Office Action from counterpart Japan Patent Application No. 10-2006-7007706, mailed Jan. 12, 2010, 12 pages.18Tartalja, I., et al., "A Survey of Software Solutions for Maintenance of Cache Consistency," Proceedings of the 28th Annual Hawaii International Conference on System Sciences-1995, pp. 272-278.19Third Office Action from counterpart China Patent Application No. 200480038473.5, mailed Mar. 21, 2008, 1 page.Classifications U.S. Classification711/122, 711/144, 711/119, 711/141, 711/118International ClassificationG06F13/42, G06F12/08, G06F13/00Cooperative ClassificationG06Q30/0601, G06F12/0813European ClassificationG06F12/08B4N, G06Q30/0601Legal EventsDateCodeEventDescriptionSep 22, 2011ASAssignmentEffective date: 20031020Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR: CARNEY, MARK J. PREVIOUSLY RECORDED ON REEL 014631 FRAME 0830. ASSIGNOR(S) HEREBY CONFIRMS THE CHARNEY, MARK J.;ASSIGNOR:CHARNEY, MARK J.;REEL/FRAME:026953/0674Owner name: INTEL CORPORATION, CALIFORNIAOct 22, 2003ASAssignmentOwner name: INTEL CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CARNEY, MARK J.;RAJWAR, RAVI;AHUJA, PRITPAL S.;AND OTHERS;REEL/FRAME:014631/0830;SIGNING DATES FROM 20031020 TO 20031021Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CARNEY, MARK J.;RAJWAR, RAVI;AHUJA, PRITPAL S.;AND OTHERS;SIGNING DATES FROM 20031020 TO 20031021;REEL/FRAME:014631/0830RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google