Source: https://patents.google.com/patent/US8694735B2/en
Timestamp: 2018-06-22 22:43:46
Document Index: 538593905

Matched Legal Cases: ['Application No. 2006', 'Application No. 05728609', 'Application No. 094104058', 'Application No. 05712043', 'application No. 05', 'application No. 05', 'Application No. 2006', 'Application No. 094104058', 'Application No. 094104058', 'Application No. 094104058', 'Application No. 094104058', 'Application No. 05712043']

US8694735B2 - Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system - Google Patents
US8694735B2
US8694735B2 US13612490 US201213612490A US8694735B2 US 8694735 B2 US8694735 B2 US 8694735B2 US 13612490 US13612490 US 13612490 US 201213612490 A US201213612490 A US 201213612490A US 8694735 B2 US8694735 B2 US 8694735B2
US13612490
US20130007384A1 (en )
This application is a continuation of U.S. patent application Ser. No. 12/840,007, filed Jul. 20, 2010, and issued as U.S. Pat. No. 8,291,173 on Oct. 16, 2012, which is a continuation of U.S. patent application Ser. No. 10/773,583, filed Feb. 5, 2004, and issued as U.S. Pat. No. 7,788,451. These applications and patents are incorporated herein by reference, in their entirety, for any purpose.
1. A method of managing read and write data transmission in a memory logic circuit, comprising:
enabling a write data bypass circuit of a first memory to decouple and store write data from a bidirectional bus responsive, at least in part, to receipt of a read command and transmission of the read command to a second memory further downstream on the bidirectional bus and issuance of a write command; and
restoring the write data to the bidirectional data bus with the write data bypass circuit of the first memory responsive, at least in part, to read data associated with the read command passing upstream on the bidirectional data bus.
2. The method of claim 1, wherein said enabling a write data bypass circuit comprises:
enabling the write data bypass circuit responsive, at least in part, to receipt of an active bypass control signal from a memory controller.
3. The method of claim 1, wherein said restoring the write data to the bidirectional data bus comprises:
enabling an output of a buffer; and
providing the write data from the buffer to the bidirectional data bus.
4. The method of claim 1, wherein the write data comprises a first set of write data, the method further comprising:
providing a second set of write data without any bypass.
5. The method of claim 1, wherein write data is stored in a data bypass register.
6. The method of claim 1, wherein the write command is issued by a memory controller.
decoupling write data associated with a first memory module from a bidirectional data bus with a data bypass circuit of a second memory module when an enable control signal has a first state;
after decoupling the write data from a bidirectional data bus with the data bypass circuit of the second memory module, storing the write data in a data bypass register of the data bypass circuit;
restoring the write data to the bidirectional data bus responsive, at least in part, to the enable control signal switching from the first state to a second state.
8. The method of claim 7, wherein the enable control signal is provided by a bypass select control logic.
9. The method of claim 7, wherein said decoupling write data associated with a first memory module from the bidirectional data bus comprises:
placing an output of a buffer in a high impedance state; and
coupling an output of the data bypass register to an input of the buffer.
10. The method of claim 7, wherein the write data is a first set of write data, the method further comprising:
providing a second set of write data without any bypass when the bypass control signal has the second state.
11. The method of claim 7, wherein the enable control signal has the first state when read data is on the bidirectional data bus.
12. The method of claim 7, wherein restoring the write data to the bidirectional data bus comprises:
coupling an output of an input buffer to an input of an output buffer.
receiving, with a memory module, a read command on a bidirectional data bus from an upstream device;
providing, with the memory module, the read command to a first downstream memory module;
decoupling, with the memory module, write data from the bidirectional data bus and storing the write data, wherein the write data corresponds to a write command issued to a second downstream memory module;
receiving read data corresponding to the read command from the first downstream memory module;
providing the read data to the upstream device; and
responsive to providing the read data to the upstream device, restoring the write data to the bidirectional data bus to provide the write data to the second downstream memory module.
14. The method of claim 13, wherein the first downstream memory module and the second downstream memory module are configured in a point-to-point arrangement.
15. The method of claim 13, wherein said decoupling write data from the bidirectional data bus and storing the write data comprises:
decoupling the write data from a first interface of the data bypass circuit; and
wherein said restoring the write data to the bidirectional data bus comprises:
providing the write data to a second interface of the data bypass circuit.
16. The method of claim 15, wherein said providing the write data to the second interface comprises:
17. The method of claim 13, wherein storing the write data comprises storing the write data in a bypass register.
18. The method of claim 13, wherein said restoring the write data to the bidirectional data bus comprises:
switching the state of a control signal provided to a multiplexer.
19. The method of claim 13, wherein said decoupling write data from the bidirectional data bus and storing the write data comprises:
decoupling the write data from the bidirectional data bus and storing the write data responsive, at least in part, to receipt of an active bypass control signal.
20. The method of claim 13, wherein the upstream device comprises a memory controller.
US13612490 2004-02-05 2012-09-12 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system Active US8694735B2 (en)
US14223443 Continuation US9164937B2 (en) 2004-02-05 2014-03-24 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US20130007384A1 true US20130007384A1 (en) 2013-01-03
US8694735B2 true US8694735B2 (en) 2014-04-08
WO2000029921A9 (en) 1998-11-16 2001-03-22 Infineon Ag Methods and apparatus for detecting data collision on data bus for different times of memory access execution
US20020174284A1 (en) 2001-03-26 2002-11-21 Garcia Serafin E. Device for spatially and temporally reordering for data between a processor, memory and peripherals
US20020196806A1 (en) 1998-11-16 2002-12-26 Ghodrat Fataneh F. Method and apparatus for multi context direct memory access
US6577174B2 (en) 2000-01-10 2003-06-10 Honeywell International Inc. Phase lock loop system and method
WO2002023353A3 (en) 2000-09-18 2003-07-31 Intel Corp Apparatus for implementing a buffered daisy-chain ring connection between a memory controller and memory modules
US20070180171A1 (en) 2004-03-24 2007-08-02 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
JP2008023267A (en) 2006-07-25 2008-02-07 Daikoku Denki Co Ltd Drum type display device for game machine
US20100287323A1 (en) 2004-02-05 2010-11-11 Larson Douglas A Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US20120066461A1 (en) 2004-03-24 2012-03-15 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
US20100019822A1 (en) 2004-04-05 2010-01-28 Laberge Paul A Delay line synchronizer apparatus and method
"Flash Erasable Programmable Read-Only Memory", "Free On-Line Dictionary of Computing". Online May 17, 2004 [http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?flaxh+memory].
"HyperTransport I/O Link Specification", HyperTransport Technology Consortium, 2001, pp. 46-49.
"International Search Report and Written Opinion", International Application No. PCT/US2005/02410; International Filing Date Jan. 25, 2005.
"Micron 1Gb: x4, x8, x18 DDR SDRAM", Micron Technology, Inc, Jul. 2003.
"Offical Notice of Rejection", Japanese Patent Application No. 2006-0552147; mailed Mar. 23, 2010.
"Office Action mailed Sep. 7, 2010 for European Application No. 05728609.8".
"Office Action of the IPO", Taiwan Patent Application No. 094104058; May 30, 2008.
"Supplemental European Search Report", Application No. 05712043.8; mailed Oct. 29, 2009.
Cronin, Jeffrey J. et al., First Office action dated Jan. 22, 2013 for EP application No. 05 712 043.8.
EP Office Action for Appl. No. 05712043.8 dated Sep. 27, 2013.
Extended search report received for EP 12 194 174.4 dated Feb. 8, 2013.
First Office Action dated Jan. 22, 2013 for EP application No. 05 712 043.8.
First Office Action of the People's Republic of China, Patent Application Filing No. 200580010700.8; dated Jan. 20, 2009.
HyperTransport I/O Link Specification, HyperTransport Technology Consortium, 2001, pp. 46-49.
Intel., "Flash Memory PCT Add-In Card for Embedded Systems", Application Note AP-758, Sep. 1997, Sep. 1997, pp. 1-13.
International Search Report and Written Opinion, International Application No. PCT/US2005/02410; International Filing Date Jan. 25, 2005.
Larson, Douglas A. et al., Extended search report received for EP 12 194 174.4 dated Feb. 8, 2013.
Offical Notice of Rejection, Japanese Patent Application No. 2006-0552148; mailed Mar. 23, 2010.
Office Action of the IPO, Taiwan Patent Application No. 094104058; issued Mar. 4, 2009.
Office Action of the IPO, Taiwan Patent Application No. 094104058; May 30, 2008.
Rambus, Inc, "Direct RambusTM Technology Disclosure", 1-16, Oct. 1997.
Rambus, Inc. "Direct RambusTM Technology Disclosure", 1-16, 1997.
Response to Office Action of the IPO, Taiwan Patent Application No. 094104058; filed May 2009.
Response to Taiwan Office Action, Taiwan Patent Application No. 094104058; filed Nov. 2008.
Second Office Action of the People's Republic of China, Patent Application Filing No. 200580010700.8; dated Apr. 17, 2009.
Supplemental European Search Report, Application No. 05712043.8; mailed Oct. 29, 2009.
US20050223161A1 (en) 2005-10-06 Memory hub and access method having internal row caching