Source: http://www.google.com/patents/US8119481?dq=4052565
Timestamp: 2014-11-29 00:39:07
Document Index: 209730759

Matched Legal Cases: ['Application No. 60', 'Application No. 61', 'art 2', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093']

Patent US8119481 - High-κ capped blocking dielectric bandgap engineered SONOS and MONOS - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping...http://www.google.com/patents/US8119481?utm_source=gb-gplus-sharePatent US8119481 - High-κ capped blocking dielectric bandgap engineered SONOS and MONOSAdvanced Patent SearchPublication numberUS8119481 B2Publication typeGrantApplication numberUS 12/881,570Publication dateFeb 21, 2012Filing dateSep 14, 2010Priority dateAug 27, 2007Also published asCN101383353A, CN101383353B, EP2031643A2, EP2031643A3, US7816727, US8330210, US20090059676, US20110003452, US20120146126Publication number12881570, 881570, US 8119481 B2, US 8119481B2, US-B2-8119481, US8119481 B2, US8119481B2InventorsSheng-Chih Lai, Hang-Ting Lue, Chien-Wei LiaoOriginal AssigneeMacronix International Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (95), Non-Patent Citations (50), Classifications (20) External Links: USPTO, USPTO Assignment, EspacenetHigh-κ capped blocking dielectric bandgap engineered SONOS and MONOSUS 8119481 B2Abstract A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.
What is claimed is: 1. A method for manufacturing a charge trapping memory comprising:
CROSS REFERENCE TO RELATED APPLICATIONS The present application is a divisional of co-pending U.S. patent application Ser. No. 12/182,318 filed on 30 Jul. 2008, which application claims the benefit of U.S. Provisional Patent Application No. 60/968,076, filed on 27 Aug. 2007, and of U.S. Provisional Patent Application No. 61/019,178, filed on 4 Jan. 2008, each of which is incorporated by reference as if fully set forth herein.
Technology has been investigated to improve the ability of the blocking dielectric layer to reduce electron injection from the gate for the high electric fields needed for erase. See, U.S. Pat. No. 6,912,163, entitled �Memory Device Having High Work Function Gate and Method of Erasing Same,� Invented by Zheng et al., issued 28 Jun. 2005; and U.S. Pat. No. 7,164,603, entitled �Operation Scheme with High Work Function Gate and Charge Balancing for Charge Trapping Non-Volatile Memory�, invented by Shih et al., Shin et al., �High Reliable SONOS-type NAND Flash Memory Cell with Al2O3 or Top Oxide,� NVSMW, 2003; and Shin et al., �A Novel NAND-type MONOS Memory using 63 nm Process Technology for a Multi-Gigabit Flash EEPROMs�, IEEE 2005. In the just-cited references, the second Shin et al. article describes a SONOS type memory cell in which the gate is implemented using tantalum nitride and the blocking dielectric layer is implemented using aluminum oxide (referred to as the TANOS device), which maintains a relatively thick tunneling dielectric layer at about 4 nm. The relatively high work function of tantalum nitride inhibits electron injection through the gate, and the high dielectric constant of aluminum oxide reduces the magnitude of the electric field through the blocking dielectric layer relative to the electric field for the tunneling dielectric layer. Shin et al. report a trade-off between the breakdown voltage of the memory cell, the thickness of the aluminum oxide layer and the thickness of the tunneling dielectric layer. With a 4 nm thick silicon dioxide tunneling dielectric in a TANOS device, relatively high erase voltages are proposed in order to achieve erase speeds. An increase in erase speeds would require increasing the voltages applied or decreasing the thickness of the tunneling dielectric layer. Increasing the voltage applied for erase is limited by the breakdown voltage. Decreasing the thickness of the tunneling dielectric layer is limited by issues of charge retention, as mentioned above.
SUMMARY OF THE INVENTION A blocking dielectric engineered, charge trapping memory cell is described having a dielectric stack between the gate and the channel including a charge trapping element that is separated from a gate by a blocking dielectric comprising a first layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second layer in contact with said one of the gate and the channel, in which the second layer has a dielectric constant that is higher than that of the first layer, and preferably comprises a high-κ material, and more preferably a material having a dielectric constant more than 7. As described herein, the second layer has a dielectric constant κ2 higher than κ1 of the first layer, and the second layer has a thickness less than κ2/κ1 times that of the first layer. This thickness relationship provides for use of a relatively thick first layer acting as a buffer layer, improving overall reliability, including charge retention, endurance and disturb characteristics of the device, while suppressing gate injection to reduce erase saturation levels.
High-κ top dielectrics are widely considered as a �must� in charge-trapping devices. The original thinking [C. H. Lee et al, IEDM Tech. Dig., pp. 26.5.1-26.5.4, 2003] was an analogy in floating gate device, where gate coupling ratio (GCR) can be increased by using higher-k inter-poly dielectric. However, charge-trapping devices are designed in planar structure and do not depend on the same kind of gate coupling ratio engineering, as do floating gate cells. In fact, for the charge trapping device with a planar structure, the electric field in bottom tunnel oxide is simply determined by |VG−VT|/EOT (where EOT is effective oxide thickness), and independent of the top dielectric. On the other hand, most current MANOS structures uses relatively thick Al2O3 as the blocking layer (to prevent leakage) and have a large EOT (�15 nm) [Y. Shin et al, IEDM Tech. Dig., pp. 327-330, 2005]. Such large EOT should not help in program/erase speed according to the theory.
DETAILED DESCRIPTION A detailed description of embodiments of the present invention is provided with reference to the FIGS. 1-34.
Also, it is found that the ratio of the thickness of the top layer 17B to the thickness of the bottom layer 17A of the blocking dielectric layer can be less than 2 for the combination of silicon oxide (κ1=3.9) and aluminum oxide (κ2=about 8). In general, the top layer 17B can have a thickness that is less than the ratio of the dielectric constants thicker than the bottom layer 17A. Thus, the blocking dielectric layer as described herein includes a first layer 17A having a dielectric constant κ1 contacting the charge trapping dielectric layer and a second layer 17B contacting another one of the channel surface and the gate, the second layer 17B having a dielectric constant κ2 higher than κ1 of the first layer, and the second layer having thickness less than κ2/κ1 times that of the first layer. For aluminum oxide as a top capping layer, the dielectric constant is �8 and the barrier height or conduction band offset is more than 3 eV to obtain the erase saturation VFB<−2V. Since the barrier height of Al2O3 is almost the same as SiO2, the electron barrier height or conduction band offset of aluminum oxide with N+ polysilicon gate is about 3.1 eV.
FIG. 17 shows a memory cell comprising a MONOS multi-layer stack with a high-κcapping layer 717B, without the bandgap engineered tunneling layer of FIG. 1. Referring to FIG. 17, the �High Work Function� gate 718 can comprise any metal gate material or alternatively a polysilicon gate. The high-κ capping layer can well suppress the gate injection so that almost all the metal films can be used, including materials like aluminum in which the work function is as low as 4.3 eV. TaN, TiN, P+ poly-Si gate and N+ poly gate may be preferred. Platinum is also a good metal gate material. Alternatives include Ti, Ta, Al, W, WN, RuO2, etc.
The capping layer 717B is a high dielectric constant layer with the dielectric constant >6, such as Al2O3, HfO2, ZrO2, La2O3, AlSiO, HfSiO and ZrSiO etc., where Al2O3 and HfO2 are preferred in this invention. The thickness of high-κtop-capping layer is 3�20 nm. The buffer layer 717A can be wet conversion SiO2 from nitride, high temperature oxide (HTO) or LPCVD SiO2 etc. However, the wet conversion SiO2 is preferred. The preferred thickness of buffer layer 717A is 0.5�8 nm, where the relative thickness satisfies the relation that is more than κ1/κ2 time the thickness of the capping layer 717B.
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Int'l. Electron Devices Meeting, Dec. 1991 307-310.50Yeh, C.C., et al., "Phines: A Novel Low Power Program/Erase, Small Pitch 2-Bit per Cell Flash Memory," IEDM Tech. Dig. 2002, 931-934.Classifications U.S. Classification438/258, 257/324, 257/E29.309, 438/288, 257/325, 438/287, 257/E21.423International ClassificationH01L21/336Cooperative ClassificationH01L29/4234, H01L27/11568, G11C16/0483, G11C8/10, H01L29/513, H01L21/28282, G11C16/0466European ClassificationH01L27/115G4, H01L21/28G, H01L29/423D2B3, H01L29/51B2, G11C8/10RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google