Source: http://www.google.com/patents/US6370638?ie=ISO-8859-1
Timestamp: 2014-03-11 20:02:46
Document Index: 537612747

Matched Legal Cases: ['art 3', 'art 101', 'art 107', 'art 101', 'art 13', 'art 13', 'art 13', 'art 13', 'art 13', 'art 13', 'art 13', 'art 13', 'art. 202', 'art 13', 'art 13', 'art 13', 'art 13']

Patent US6370638 - Apparatus and method of computer program control in computer systems using ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA program control apparatus for processing an instruction by using a pipeline processing for providing the effective stall control when resource competition is caused by the instructions is disclosed. The NOP field which shows the number of NOP (no operation processing) instruction is assigned in the...http://www.google.com/patents/US6370638?utm_source=gb-gplus-sharePatent US6370638 - Apparatus and method of computer program control in computer systems using pipeline processingAdvanced Patent SearchPublication numberUS6370638 B1Publication typeGrantApplication numberUS 09/195,529Publication dateApr 9, 2002Filing dateNov 18, 1998Priority dateNov 21, 1997Fee statusPaidPublication number09195529, 195529, US 6370638 B1, US 6370638B1, US-B1-6370638, US6370638 B1, US6370638B1InventorsMasayuki YamasakiOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (10), Non-Patent Citations (5), Referenced by (3), Classifications (15), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetApparatus and method of computer program control in computer systems using pipeline processingUS 6370638 B1Abstract A program control apparatus for processing an instruction by using a pipeline processing for providing the effective stall control when resource competition is caused by the instructions is disclosed. The NOP field which shows the number of NOP (no operation processing) instruction is assigned in the instruction code with the possibility to cause the resource competition, and set the number of NOP for the stall and performs the NOP according to the NOP field. When the NOP field of the following instruction shows N, stall is executed by inserting and performing NOP of N piece by the stall control part 3 before the following instruction is executed. When the NOP field is assigned in both a preceding instruction and a following instruction, NOP of predetermined number N piece is inserted after the preceding instruction is executed, NOP of predetermined number M piece is inserted before the following instruction is executed, and the stall is achieved.
SUMMARY OF THE INVENTION Therefore, with the foregoing in mind, it is an object of the present invention to provide a program control apparatus for performing stall control by inserting NOP of the predetermined number into the process referring to the NOP field in an instruction code.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing a case where the register interference occurs and a principle for preventing the register interference by the NOP insertion.
FIG. 1(a) shows one sample of the occurrence of register interference. This timing chart shows the case for four step pipeline, the preceding instruction is data transfer instruction �MOV PR, GR� from GR to PR, the following instruction is move operation �MOV GR, M(PR)� from the data memory to GR addressing by PR value, and both instruction are in series.
NOP field assigned instruction detection part 101 outputs logic �1� when the first instruction code 21 is an instruction with the NOP field and outputs logic �0� when the first instruction code 21 is an instruction without the NOP field. The 102 and the 103 are flip-flops (hereinafter referring to as FF), the 104 and the 105 are OR gates (logical add), the 106 is AND (logical product) gate. NOP number count part 107 is formed with flip-flop 102 and OR gates 104 and 105. When the instruction code has adopted LSB, the NOP field is assumed to be a lower two bits in an instruction code, and signal 111 is a lower bit of 2 bits of the NOP fields, and signal 112 is a upper bit of 2 bits of the NOP fields. The input signal of FF 102 is signal 112. The input signal of FF 103 is an output of AND gate 106, and the output signals of FF 103 is a switch signal 15 and a temporary pipeline stop signal 24. The input signal of the OR gate 104 is output from the FF 102 and signal 112. The input of OP gate 105 is signal 111 and an output signal from the OR gate 104. The input signals of AND gate 106 are an output signal from the OR gate 105 and an output signal from NOP field assigned instruction detection part 101. When the first instruction code 21 is an instruction with the NOP field, the temporary pipeline stop part 13 by this circuit structure outputs a switch signal 25 and a temporary pipeline stop signal 24 for the processing stage corresponding to the specified number of NOP.
The operation of the program control apparatus shown above is described based on FIG. 6, FIG. 7, FIG. 10, FIG. 12, and FIGS. 14-15. FIG. 12 shows the bit field of the preceding instruction code where the NOP field is assigned. Bit 0 and bit 1 are NOP fields. NOP number N=1 is directed when bit 0 is �1�, and NOP number N=2 is directed when bit 1 is �1�. FIG. 14 is a flow chart showing the outline of the processing flow of the program control apparatus of this Embodiment 1. FIG. 15 is a timing chart for a four step pipeline. The move operation (MOV PR,GR) is described as an example of the instruction.
When the signal 111, which is the lower bit of the NOP field, is �1� (as shown by FIG. 15 (a)), the temporary pipeline stop part 13 outputs one cycle of the temporary pipeline stop signal 24 and the switch signal 25. When the signal 112 which is the upper bit of the NOP field is �1� (as shown by FIG. 15 (b)), the temporary pipeline stop part 13 outputs two cycles of the temporary pipeline stop signal 24 and the switch signal 25.
As shown in FIG. 8, the same number is assigned to components having the same function as FIG. 7. The example of the circuit structure of the temporary pipeline stop part 13 is the same circuit structure as shown by FIG. 10 in Embodiment 1. In this Embodiment 2, the temporary pipeline stop part 13 inputs the output signal 26 of the first instruction register, which signal is the latched signal from the first instruction code 21, when the inputted signal is an instruction with NOP field, the temporary pipeline stop part 13 outputs a switch signal 25 and a temporary pipeline stop signal 24 are output signals. The operation of the program control apparatus shown above is described based on FIG. 6, FIG. 8, FIG. 10, FIG. 12, and FIGS. 16-17. The bit field of the following instruction code for which the stall control is applied is the same bit field used in the Embodiment 1 as shown FIG. 12. NOP number N=1 is directed when bit 0 is �1�, and NOP number N=2 is directed when bit 1 is �1�. FIG. 16 is a flow chart showing the outline of the processing flow of the program control apparatus of this Embodiment 2. FIG. 17 is a timing chart for a four step pipeline. The branch operation (BRC Z, JMP) is described as an example of the following instruction.
When the signal 111, which is the lower bit of the NOP field, is �1�(as shown by FIG. 17 (a)), the temporary pipeline stop part 13 outputs one cycle of the temporary pipeline stop signal 24 and the switch signal 25. When the signal 112, which is the upper bit of the NOP field, is �1� (as shown by FIG. 17 (b)), the temporary pipeline stop part 13 outputs two cycles of the temporary pipeline stop signal 24 and the switch signal 25.
It is necessary to detect a preceding instruction with NOP field and the following instruction with NOP field respectively in this Embodiment 3. It is also necessary to output �Temporary pipeline stop signal� and �Switch signal� separately. In FIG. 11, 201 denotes a first NOP field assigned instruction detection part. 202 denotes a second NOP field assigned instruction detection part. Both 201 and 202 input a first instruction code 21 (instruction code other than the NOP field can be used) and can detect whether inputted instruction code has the NOP field or not. The 203 to the 205 are FF, the 207 and the 208 are AND gates (logical product), the 206 is an OR (logical product) gate. When the instruction code has adopted LSB, the NOP field is assumed to be a lowest bit in a instruction code, and signal 111 is a lowest bit of the NOP fields. The FF 203 outputs a first switch signal 25 a, the FF 204 outputs a second switch signal 25 b and a second temporary pipeline stop signal 24 b, the FF 205 outputs a first temporary pipeline stop signal 24 a. In this Embodiment 3, when the preceding instruction with the NOP field is inputted as a first instruction code 21, the temporary pipeline stop part 13 by this circuit structure outputs a first temporary pipeline stop signal 24 a for the processing stage and a first switch signal 25 a corresponding to the specified number of NOP.
FIG. 13 shows the bit field of the preceding instruction code and following instruction code where the NOP field is assigned. The lowest Bit 0 is NOP fields. NOP number N=1 is directed when bit 0 is �1�. FIG. 18 is a flow chart showing the outline of the processing flow of the program control apparatus of this Embodiment 3. FIG. 19 is a timing chart for a four step pipeline. The immediate value move operation (MOV PR, immediate value) and add operation (ADD GR, M(PR)) which includes the access to data memory is described as an example of the instruction.
The first instruction code 21 becomes output 28 of the first multiplexer 12, and the first instruction code 21 is inputted to the temporary pipeline stop part 13 and the second instruction register 14. The first instruction code 21 is outputted as the second instruction code 22 through the second instruction register 14 and the second multiplexer 15. When the signal 111, which is the lowest bit of the NOP field is, �1�(as shown by FIG. 19(a)), the temporary pipeline stop part 13 outputs one cycle of a first temporary pipeline stop signal 24 a and a first switch signal 25 a. (4) Step 5
When the signal 111, which is the lowest bit of the NOP field, is �1�(as shown by FIG. 19(a)), the temporary pipeline stop part 13 outputs one cycle of the second temporary pipeline stop signal 24 b and the second switch signal 25 b. (8) Step 9
According to the embodiment shown above, the stall (delay time) ,the same as the Embodiment 1 and Embodiment 2, can be achieved in spite of reducing the assigned size of the NOP field from two bits to one bit. In the above-mentioned embodiment, the number of NOP specified by the bit row in the NOP field is explained as a binary value. Dedicated coding can be adopted that the combination of the bit row indicates specific value set previously. For instance, the combination of �0� and �1� shown by two bits indicate following specific value. �00� indicates 1, �01� indicates 2, �10� indicates 4, and �11� indicates 6. In a same manner, another dedicated coding of two bit row can be adopted as follows. �00� indicates 0, �01� indicates 3, �10� indicates 6, �11� indicates 9. By using this dedicated coding, when the available field space is small, it is especially effective that the numerical value of four or more can be specified by using two bits.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5150469 *Jul 13, 1990Sep 22, 1992Digital Equipment CorporationSystem and method for processor pipeline control by selective signal deassertionUS5404552 *Dec 12, 1991Apr 4, 1995Mitsubishi Denki Kabushiki KaishaPipeline risc processing unit with improved efficiency when handling data dependencyUS5694574 *Dec 19, 1996Dec 2, 1997Intel CorporationMethod and apparatus for performing load operations in a computer systemUS5958044 *Jan 20, 1998Sep 28, 1999Texas Instruments IncorporatedMulticycle NOPUS5968166 *Mar 19, 1997Oct 19, 1999Matsushita Electric Industrial Co., Ltd.Information processing apparatus and method, and scheduling device for reducing inactivity due to wait stateJPH0338727A Title not availableJPH01119829A Title not availableJPH02178837A Title not availableJPH03136136A Title not availableJPH03180931A Title not available* Cited by examinerNon-Patent CitationsReference1Patent Abstracts of Japan, publication No. 01119829A, published May 11, 1989.2Patent Abstracts of Japan, Publication No. 02178837 A, Date of publication: Jul. 11, 1990.3Patent Abstracts of Japan, Publication No. 03038727 A, Date of publication: Feb. 19, 1991.4Patent Abstracts of Japan, Publication No. 03136136 A, Date of publication: Jun. 10, 1991.5Patent Abstracts of Japan, Publication No. 03180931 A, Date of publication: Aug. 6, 1991.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7069425 *May 18, 2000Jun 27, 2006Sharp Kabushiki KaishaReal-time processor executing predetermined operation defined by program correctly at predetermined timeUS8359425Apr 13, 2011Jan 22, 2013Kabushiki Kaisha ToshibaMemory control device, memory device, and shutdown control methodUS8621186 *Nov 14, 2011Dec 31, 2013Cisco Technology Inc.Obfuscated hardware multi-threading* Cited by examinerClassifications U.S. Classification712/219, 712/245, 712/E09.035, 712/E09.032, 712/E09.049, 712/E09.062International ClassificationG06F9/38, G06F9/30, G06F9/318Cooperative ClassificationG06F9/30079, G06F9/3867, G06F9/3836European ClassificationG06F9/30A8H, G06F9/38E, G06F9/38PLegal EventsDateCodeEventDescriptionSep 20, 2013FPAYFee paymentYear of fee payment: 12Sep 9, 2009FPAYFee paymentYear of fee payment: 8Sep 16, 2005FPAYFee paymentYear of fee payment: 4Nov 18, 1998ASAssignmentOwner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YAMASAKI, MASAYUKI;REEL/FRAME:009867/0634Effective date: 19981112RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google