Source: http://www.google.com/patents/US20040250231?dq=5,222,134
Timestamp: 2016-12-10 11:17:22
Document Index: 207101240

Matched Legal Cases: ['art[7', 'art[15', 'art[23', 'art[31', 'art[15', 'art[23', 'art[31', 'art[31', 'art[23', 'art[23', 'art[15', 'art[15', 'art[7', 'art[7', 'art[31', 'Art[31', 'art[15', 'Art[15', 'art[31', 'art[15']

Patent US20040250231 - Automated processor generation system for designing a configurable processor ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and...http://www.google.com/patents/US20040250231?utm_source=gb-gplus-sharePatent US20040250231 - Automated processor generation system for designing a configurable processor and method for the sameAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20040250231 A1Publication typeApplicationApplication numberUS 10/884,590Publication dateDec 9, 2004Filing dateJul 2, 2004Priority dateFeb 5, 1999Also published asUS6477683, US6760888, US7020854, US8006204, US8875068, US8924898, US20030208723, US20060259878, US20080244471, US20080244506Publication number10884590, 884590, US 2004/0250231 A1, US 2004/250231 A1, US 20040250231 A1, US 20040250231A1, US 2004250231 A1, US 2004250231A1, US-A1-20040250231, US-A1-2004250231, US2004/0250231A1, US2004/250231A1, US20040250231 A1, US20040250231A1, US2004250231 A1, US2004250231A1InventorsEarl Killian, Ricardo Gonzalez, Ashish Dixit, Monica Lam, Walter Lichtenstein, Christopher Rowen, John Ruttenberg, Robert Wilson, Albert Wang, Droe MaydanOriginal AssigneeKillian Earl A., Gonzalez Ricardo E., Dixit Ashish B., Monica Lam, Lichtenstein Walter D., Christopher Rowen, Ruttenberg John C., Wilson Robert P., Wang Albert Ren-Rui, Maydan Droe EliezerExport CitationBiBTeX, EndNote, RefManPatent Citations (14), Referenced by (73), Classifications (9), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetAutomated processor generation system for designing a configurable processor and method for the same
BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention is directed to systems and techniques for designing programmable processing elements such as microprocessors and the like. More particularly, the invention is directed to the design of an application solution containing one or more processors to where the processors in the system are configured and enhanced at the time of their design to improve their suitability to a particular application. [0004] 2. Description of Related Art [0005] Processors have traditionally been difficult to design and to modify. For this reason, most systems that contain processors use ones that were designed and verified once for general-purpose use, and then used by multiple applications over time. As such, their suitability for a particular application is not always ideal. It would often be appropriate to modify the processor to execute a particular application's code better (e.g., to run faster, consume less power, or cost less). However, the difficulty, and therefore the time, cost, and risk of even modifying an existing processor design is high, and this is not typically done. [0006] To better understand the difficulty in making a prior art processor configurable, consider its development. First, the instruction set architecture (ISA) is developed. This is a step which is essentially done once and used for decades by many systems. For example, the Intel Pentiuim® processor can trace the legacy of its instruction set back to the 8008 and 8080 microprocessors introduced in the mid-1970's. In this process, based on predetermined ISA design criteria, the ISA instructions, syntax, etc. are developed, and software development tools for that ISA such as assemblers, debuggers, compilers and the like are developed. Then, a simulator for that particular ISA is developed and various benchmarks are run to evaluate the effectiveness of the ISA and the ISA is revised according to the results of the evaluation. At some point, the ISA will be considered satisfactory, and the ISA process will end with a fully developed ISA specification, an ISA simulator, an ISA verification suite and a development suite including, e.g., an assembler, debugger, compiler, etc. [0007] Then, processor design commences. Since processors can have useful lives of a number of years, this process is also done fairly infrequently—typically, a processor will be designed once and used for many years by several systems. Given the ISA, its verification suite and simulator and various processor development goals, the microarchitecture of the processor is designed, simulated and revised. Once the microarchitecture is finalized, it is implemented in a hardware description language (HDL) and a microarchitecture verification suite is developed and used to verify the HDL implementation (more on this later). Then, in contrast to the manual processes described to this point, automated design tools may synthesize a circuit based on the HDL description and place and route its components. The layout may then be revised to optimize chip area usage and timing. Alternatively, additional manual processes may be used to create a floorplan based on the HDL description, convert the HDL to circuitry and then both manually and automatically verify and lay the circuits out. Finally, the layout is verified to be sure it matches the circuits using an automated tool and the circuits are verified according to layout parameters. [0008] After processor development is complete, the overall system is designed. Unlike design of the ISA and processor, system design (which may include the design of chips that now include the processor) is quite common and systems are typically continuously designed. Each system is used for a relatively short period of time (one or two years) by a particular application. Based on predetermined system goals such as cost, performance, power and functionality; specifications of pre-existing processors; specifications of chip foundries (usually closely tied with the processor vendors), the overall system architecture is designed, a processor is chosen to match the design goals, and the chip foundry is chosen (this is closely tied to the processor selection). [0009] Then, given the chosen processor, ISA and foundry and the simulation, verification and development tools previously developed (as well as a standard cell library for the chosen foundry), an HDL implementation of the system is designed, a verification suite is developed for the system HDL implementation and the implementation is verified. Next, the system circuitry is synthesized, placed and routed on circuit boards, and the layout and timing are re optimized. Finally, the boards are designed and laid out, the chips are fabricated and the boards are assembled. [0010] Another difficulty with prior art processor design stems from the fact that it is not appropriate to simply design traditional processors with more features to cover all applications, because any given application only requires a particular set of features, and a processor with features not required by the application is overly costly, consumes more power and is more difficult to fabricate. In addition it is not possible to know all of the application targets when a processor is initially designed. If the processor modification process could be automated and made reliable, then the ability of a system designer to create application solutions would be significantly enhanced. [0011] As an example, consider a device designed to transmit and receive data over a channel using a complex protocol. Because the protocol is complex, the processing cannot be reasonably accomplished entirely in hard-wired, e.g., combinatorial, logic, and instead a programmable processor is introduced into the system for protocol processing. Programmability also allows bug fixes and later upgrades to protocols to be done by loading the instruction memories with new software. However, the traditional processor was probably not designed for this particular application (the application may not have even existed when the processor was designed), and there may be operations that it needs to perform that require many instructions to accomplish which could be done with one or a few instructions with additional processor logic. [0012] Because the processor cannot easily be enhanced, many system designers do not attempt to do so, and instead choose to execute an inefficient pure software solution on an available general-purpose processor. The inefficiency results in a solution that may be slower, or require more power, or be costlier (e.g., it may require a larger, more powerful processor to execute the program at sufficient speed). Other designers choose to provide some of the processing requirements in special-purpose hardware that they design for the application, such as a coprocessor, and then have the programmer code up access to the special-purpose hardware at various points in the program. However, the time to transfer data between the processor and such special-purpose hardware limits the utility of this approach to system optimization because only fairly large units of work can be sped up enough so that the time saved by using the special-purpose hardware is greater than the additional time required to transfer data to and from the specialized hardware. [0013] In the communication channel application example, the protocol might require encryption, error correction, or compression/decompression processing. Such processing often operates on individual bits rather than a processor's larger words. The circuitry for a computation may be rather modest, but the need for the processor to extract each bit, sequentially process it and then repack the bits adds considerable overhead. [0014] As a very specific example, consider a Huffman decode using the rules shown in TABLE I (a similar encoding is used in the MPEG compression standard). Both the value and the TABLE I Pattern Value Length 0 0 X X X X X X 0 2 0 1 X X X X X X 1 2 1 0 X X X X X X 2 2 1 1 0 X X X X X 3 3 1 1 1 0 X X X X 4 4 1 1 1 1 0 X X X 5 5 1 1 1 1 1 0 X X 6 6 1 1 1 1 1 1 0 X 7 7 1 1 1 1 1 1 1 0 8 8 1 1 1 1 1 1 1 1 9 8 [0015] length must be computed, so that length bits can be shifted off to find the start of the next element to be decoded in the stream. [0016] There are a multitude of ways to code this for a conventional instruction set, but all of them require many instructions because there are many tests to be done, and in contrast with a single gate delay for combinatorial logic, each software implementation requires multiple processor cycles. For example, an efficient prior art implementation using the MIPS instruction set might require six logical operations, six conditional branches, an arithmetic operation, and associated register loads. Using an advantageously-designed instruction set such as the one disclosed in U.S. patent application Ser. No. 09/192,395 to Dixit et al., incorporated herein by reference, the coding is better, but still expensive in terms of time: one logical operation, six conditional branches, an arithmetic operation and associated register loads. [0017] In terms of processor resources, this is so expensive that a 256-entry lookup table is typically used instead of coding the process as a sequence of bit-by-bit comparisons. However, a 256-entry lookup table takes up significant space and can be many cycles to access as well. For longer Huffman encodings, the table size would become prohibitive, leading to more complex and slower code. [0018] A possible solution to the problem of accommodating specific application requirements in processors is to use configurable processors having instruction sets and architectures which can be easily modified and extended to enhance the functionality of the processor and customize that functionality. Configurability allows the designer to specify whether or how much additional functionality is required for her product. The simplest sort of configurability is a binary choice: either a feature is present or absent. For example, a processor might be offered either with or without floating-point hardware. [0019] Flexibility may be improved by configuration choices with finer gradation. The processor might, for example, allow the system designer to specify the number of registers in the register file, memory width, the cache size, cache associativity, etc. However, these options still do not reach the level of customizability desired by system designers. For example, in the above Huffman decoding example, although not known in the prior art the system designer might like to include a specific instruction to perform the decode, e.g. [0020] huff8 t1, t0 [0021] where the most significant eight bits in the result are the decoded value and the least significant eight bits are the length. In contrast to the previously described software implementation, a direct hardware implementation of the Huffman decode is quite simple—the logic to decode the instruction represents roughly thirty gates for just the combinatorial logic function exclusive of instruction decode, etc., or less than 0.1% of a typical processor's gate count, and can be computed by a special-purpose processor instruction in a single cycle, thus representing an improvement factor of 4-20 over using general-purpose instructions only. [0022] Prior art efforts at configurable processor generation have generally fallen into two categories: logic synthesis used with parameterized hardware descriptions; and automatic retargeting of compilers and assemblers from abstract machine descriptions. In the first category fall synthesizable processor hardware designs such as the Synopsys DW8051 processor, the ARM/Synopsys ARM7-S, the Lexra LX-4080, the ARC configurable RISC core; and to some degree the Synopsys synthesizable/configurable PCI bus interface. [0023] Of the above, the Synopsys DW8051 includes a binary compatible implementation of an existing processor architecture; and a small number of synthesis parameters, e.g., 128 or 256 bytes of internal RAM, a ROM address range determined by a parameter rom_addr_size, an optional interval timer, a variable number (0-2) of serial ports, and an interrupt unit which supports either six or thirteen sources. Although the DW8051 architecture can be varied somewhat, no changes in its instruction set architecture are possible. [0024] The ARM/Synopsys ARM7-S processor includes a binary-compatible implementation of existing architecture and microarchitecture. It has two configurable parameters: the selection of a high-performance or low-performance multiplier, and inclusion of debug and in-circuit emulation logic. Although changes in the instruction set architecture of the ARM7-S are possible, they are subsets of existing non-configurable processor implementations, so no new software is required. [0025] The Lexra LX-4080 processor has a configurable variant of the standard MIPS architecture and has no software support for instruction set extensions. Its options include a custom engine interface which allows extension of MIPS ALU opcodes with application-specific operations; an internal hardware interface which includes a register source and a register or 16-bit wide immediate source, and destination and stall signals; a simple memory management unit option; three Mips coprocessor interfaces; a flexible local memory interface to cache, scratchpad RAM or ROM; a bus controller to connect peripheral functions and memories to the processor's own local bus; and a write buffer of configurable depth. [0026] The ARC configurable RISC core has a user interface with on-the-fly-gate count estimation based on target technology and clock speed, instruction cache configuration, instruction set extensions, a timer option, a scratch-pad memory option, and memory controller options; an instruction set with selectable options such as local scratchpad RAM with block move to memory, special registers, up to sixteen extra condition code choices, a 32×32 bit scoreboarded multiply block, a single cycle 32 bit barrel shifter/rotate block, a normalize (find first bit) instruction, writing results directly to a command buffer (not to the register file), a 16 bit MUL/MAC block and 36 bit accumulator, and sliding pointer access to local SRAM using linear arithmetic; and user instructions defined by manual editing of VHDL source code. The ARC design has no facility for implementing an instruction set description language, nor does it generate software tools specific to the configured processor. [0027] The Synopsys configurable PCI interface includes a GUI or command line interface to installation, configuration and synthesis activities; checking that prerequisite user actions are taken at each step; installation of selected design files based on configuration (e.g., Verilog vs. VHDL); selective configuration such as parameter setting and prompting of users for configuration values with checking of combination validity, and HDL generation with user updating of HDL source code and no editing of HDL source files; and synthesis functions such as a user interface which analyzes a technology library to select I/O pads, technology-independent constraints and synthesis script, pad insertion and prompts for technology-specific pads, and translation of technology-independent formulae into technology-dependent scripts. The configurable PCI bus interface is notable because it implements consistency checking of parameters, configuration-based installation, and automatic modification of HDL files. [0028] Additionally, prior art synthesis techniques do choose different mappings based on user goal specifications, allowing the mapping to optimize for speed, power, area, or target components. On this point, in the prior art it is not possible to get feedback on the effect of reconfiguring the processor in these ways without taking the design through the entire mapping process. Such feedback could be used to direct further reconfiguration of the processor until the system design goals are achieved. [0029] The second category of prior art work in the area of configurable processor generation, i.e., automatic retargetting of compilers and assemblers) encompasses a rich area of academic research; see, e.g., Hanono et al., “Instruction Selection, Resource Allocation and Scheduling in the AVIV Retargetable Code Generator” (representation of machine instructions used for automatic creation of code generators); Fauth et al., “Describing Instruction Set Processors Using nML”; Ramsey et al., “Machine Descriptions to Build Tools for Embedded Systems”; Aho et al, “Code Generation Using Tree Matching and Dynamic Programming” (algorithms to match up transformations associated with each machine instruction, e.g., add, load, store, branch, etc., with a sequence of program operations represented by some machine independent intermediate form using methods such as pattern matching); and Cattell, “Formalization and Automatic Derivation of Code Generators” (abstract descriptions of machine architectures used for compiler research). [0030] Once the processor has been designed, its operation must be verified. That is, processors generally execute instructions from a stored program using a pipeline with each stage suited to one phase of the instruction execution. Therefore, changing or adding an instruction or changing the configuration may require widespread changes in the processor's logic so each of the multiple pipeline stages can perform the appropriate action on each such instruction. Configuration of a processor requires that it be re-verified, and that this verification adapt to the changes and additions. This is not a simple task. Processors are complex logic devices with extensive internal data and control state, and the combinatorics of control and data and program make processor verification a demanding art. Adding to the difficulty of processor verification is the difficulty in developing appropriate verification tools. Since verification is not automated in prior art techniques, its flexibility, speed and reliability is less than optimal. [0031] In addition, once the processor is designed and verified it is not particularly useful if it cannot be programmed easily. Processors are generally programmed with the aid of extensive software tools, including compilers, assemblers, linkers, debuggers, simulators and profilers. When the processor changes, the software tools must change as well. It does no good to add an instruction if that instruction cannot be compiled assembled, simulated or debugged. The cost of software changes associated with processor modifications and enhancements has been a major impediment to flexible processor design in the prior art. [0032] Thus, it is seen that prior art processor design is of a level of difficulty that processors generally are not typically designed or modified for a specific application. Also, it can be seen that considerable improvements in system efficiency are possible if processors could be configured or extended for specific applications. Further, the efficiency and effectiveness of the design process could be enhanced if it were able to use feedback on implementation characteristics such as power consumption, speed, etc. in refining a processor design. Moreover, in the prior art once a processor is modified, a great deal of effort is required to verify the correct operation of the processor after modification. Finally, although prior art techniques provide for limited processor configurability, they fail to provide for the generation of software development tools tailored for use with the configured processor. BRIEF SUMMARY OF THE INVENTION [0033] The present invention overcomes these problems of the prior art and has an object of providing a system which can automatically configure a processor by generating both a description of a hardware implementation of the processor and a set of software development tools for programming the processor from the same configuration specification. [0034] It is another object of the present invention to provide such a system which can optimize the hardware implementation and the software tools for various performance criteria. [0035] It is still another object of the present invention to provide such a system that permits various types of configurability for the processor, including extensibility, binary selection and parametric modification. [0036] It is yet another object of the present invention to provide such a system which can describe the instruction set architecture of the processor in a language which can easily be implemented in hardware. [0037] The above objects are achieved by providing an automated processor generation system which uses a description of customized processor instruction set options and extensions in a standardized language to develop a configured definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to generate software for the processor and to verify the processor. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption and speed. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. [0038] To develop an automated processor generation system according to the present invention, an instruction set architecture description language is defined and configurable processor/system configuration tools and development tools such as assemblers, linkers, compilers and debuggers are developed. This is part of the development process because although large portions of the tools are standard, they must be made to be automatically configured from the ISA description. This part of-the design process is typically done by the designer or manufacturer of the automated processor design tool itself. [0039] An automated processor generation system according to the present invention operates as follows. A user, e.g., a system designer, develops a configured instruction set architecture. That is, using the ISA definition and tools previously developed, a configurable instruction set architecture following certain ISA design goals is developed. Then, the development tools and simulator are configured for this instruction set architecture. Using the configured simulator, benchmarks are run to evaluate the effectiveness of the configurable instruction set architecture, and the core revised based on the evaluation results. Once the configurable instruction set architecture is in a satisfactory state, a verification suite is developed for it. [0040] Along with these software aspects of the process, the system attends to hardware aspects by developing a configurable processor. Then, using system goals such as cost, performance, power and functionality and information on available processor fabs, the system designs an overall system architecture which takes configurable ISA options, extensions and processor feature selection into account. Using the overall system architecture, development software, simulator, configurable instruction set architecture and processor HDL implementation, the processor ISA, HDL implementation, software and simulator are configured by the system and system HDL is designed for system on a chip designs. Also, based on the system architecture and specifications of chip foundries, a chip foundry is chosen based on an evaluation of foundry capabilities with respect to the system HDL (not related to processor selection as in the prior art). Finally, using the foundry's standard cell library, the configuration system synthesizes circuitry, places and routes it, and provides the ability to re-optimize the layout and timing. Then, circuit board layouts are designed if the design is not of the single-chip type, chips are fabricated, and the boards are assembled. [0041] As can be seen above, several techniques are used to facilitate extensive automation of the processor design process. The first technique used to address these issues is to design and implement specific mechanisms that are not as flexible as an arbitrary modification or extension, but which nonetheless allow significant functionality improvements. By constraining the arbitrariness of the change, the problems associated with it are constrained. [0042] The second technique is to provide a single description of the changes and is automatically generate the modifications or extensions to all affected components. Processors designed with prior art techniques have not done this because it is often cheaper to do something once manually than to write a tool to do it automatically and use the tool once. The advantage of automation applies when the task is repeated many times. [0043] A third technique employed is to build a database to assist in estimation and automatic configuration for subsequent user evaluation. [0044] Finally, a fourth technique is to provide hardware and software in a form that lends itself to configuration. In the preferred embodiment of the present invention some of the hardware and software are not written directly in standard hardware and software languages, but in languages enhanced by the addition of a preprocessor that allows queries of the configuration database and the generation of standard hardware and software language code with substitutions, conditionals, replication, and other modifications. The core-processor design is then done with hooks that allow the enhancements to be linked in. [0045] To illustrate these techniques, consider the addition of application-specific instructions. By constraining the method to instructions that have register and constant operands and which produce a register result, the operation of the instructions can be specified with only combinatorial (stateless, feedback free) logic. This input specifies the opcode assignments, instruction name, assembler syntax and the combinatorial logic for the instructions, from which tools generate: [0046] instruction decode logic for the processor to recognize the new opcodes; [0047] addition of a functional unit to perform the combinatorial logic function on register operands; [0048] inputs to the instruction scheduling logic of the processor to make sure the instruction issues only when its operands are valid; [0049] assembler modifications to accept the new opcode and its operands and generate the correct machine code; [0050] compiler modifications to add new intrinsic functions to access the new instructions; [0051] disassembler/debugger modifications to interpret the machine code as the new instruction; [0052] simulator modifications to accept the new opcodes and to perform the specified logic function; and [0053] diagnostic generators which generate both direct and random code sequences that contain and check the results of the added instructions. [0054] All of the techniques above are employed to add application specific instructions. The input is constrained to input and output operands and the logic to evaluate them. The changes are described in one place and all hardware and software modifications are derived from that description. This facility shows how a single input can be used to enhance multiple components. [0055] The result of this process is a system that is much better at meeting its application needs than existing art because tradeoffs between the processor and the rest of the system logic can be made much later in the design process. It is superior to many of the prior art approaches discussed above in that its configuration may be applied to many more forms of representation. A single source may be used for all ISA encoding, software tools and high-level simulation may be included in a configurable package, and flow may be designed for iteration to find an optimal combination of configuration values. Further, while previous methods focused only on hardware configuration or software configuration alone without a single user interface for control, or a measurement system for user-directed redefinition, the present invention contributes to complete flow for configuration of processor hardware and software, including feedback from hardware design results and software performance to aid selection of optimal configuration.
BRIEF DESCRIPTION OF THE DRAWINGS [0056] The above and other objects of the present invention will become readily apparent when reading the following detailed description taken in conjunction with the appended drawings in which: [0057] [0057]FIG. 1 is a block diagram of the major components of an automated processor generation system according to a preferred embodiment of the present invention; [0058] [0058]FIG. 2 is a block diagram of the architecture of a configurable processor according to the preferred embodiment; [0059] [0059]FIG. 3 shows a configuration manager in a GUI according to the preferred embodiment; [0060] [0060]FIG. 4 shows a configuration editor in the GUI according to the preferred embodiment; [0061] [0061]FIG. 5 shows different types of configurability according to the preferred embodiment; [0062] [0062]FIG. 6 shows the flow of processor configuration according to the preferred embodiment; [0063] [0063]FIG. 7 is a block diagram of an instruction set simulator according to the preferred embodiment. [0064] [0064]FIG. 8 is a block diagram of an emulation board for use with a processor configured according to the present invention. [0065] [0065]FIG. 9 is a block diagram showing the logical architecture of a configurable processor according to the preferred embodiment; [0066] [0066]FIG. 10 is a block diagram showing the addition of a multiplier to the architecture of FIG. 9; [0067] [0067]FIG. 11 is a block diagram showing the addition of a multiply-accumulate unit to the architecture of FIG. 9; [0068] [0068]FIGS. 12 and 13 are diagrams showing the configuration of a memory in the preferred embodiment; and [0069] [0069]FIGS. 14 and 15 are diagrams showing the addition of user defined functional units in the architecture of FIG. 8.
[0227] where $i is a TPP loop index variable and $ninterrupts is the number of interrupts specified for the processor 60 (obtained from the configuration specification 100 using config_get_value). [0228] Finally, TPP code can be embedded into Verilog™ expressions such as [0229] wire [‘$ninterrupts-1’:0] srInterruptEn; [0230] xtscenflop #(‘$ninterrupts’) srintrenreg (srInterruptEn, [0231] srDataIn_W [‘$ninterrupts-1′:0], srIntrEnWEn, !cReset, CLK); [0232] where: [0233] $ninterrupts defines the number of interrupts and determines the width (in terms of bits) of the xtscenfiop module (a flip flop primitive module); [0234] srInterruptEn is the output of the flip flop, defined to be a wire of appropriate number of bits; [0235] srDataIn_w is the input to the flip flop, but only relevant bits are input based on number of interrupts; [0236] srIntrEnWEn is the write enable of the flip flop; [0237] cReset is the clear input to the flip flop; and [0238] CLK is the input clock to the flip flop. [0239] For example, given the following input to TPP: ; # Timer Interrupt ; if ($IsaUseTimer) { wire [{grave over ( )}$width-1{grave over ( )}:0] srCCount; wire ccountWEn; //-------------------------------------------------------------- // CCOUNT Register //-------------------------------------------------------------- assign ccountWEn = srWEn_W && (srWrAdr_W =— {grave over ( )}SRCCOUNT); xtflop #({grave over ( )}$width{grave over ( )}) srccntreg (srCCount, (ccountWEn ? srDataIn_W srCCount+1),CLK); ; for ($i=0; $i<$TimerNumber; $i++) { //-------------------------------------------------------------- // CCOMPARE Register //-------------------------------------------------------------- wire [{grave over ( )}$width 1{grave over ( )}:0] srCCompare{grave over ( )}$i{grave over ( )}; wire ccompWEn {grave over ( )}$i{grave over ( )}; assign ccompWEn {grave over ( )}$i{grave over ( )} = srWEn_W && (srWrAdr_W == {grave over ( )}SRCCOMPARE{grave over ( )}$i{grave over ( )}); xtenflop #({grave over ( )}$width{grave over ( )}) srccmp{grave over ( )}$i{grave over ( )}reg (srCCompare{grave over ( )}$i{grave over ( )},srDataIn_W,ccompWEn{grave over ( )}$i{grave over ( )},CLK); assign setCCompIntr{grave over ( )}$i{grave over ( )} = (srCCompare{grave over ( )}$i{grave over ( )} == srCCount); assign clrCCompIntr{grave over ( )}$i{grave over ( )} = ccompWEn{grave over ( )}$i{grave over ( )}; ; } ; } ## IsaUseTimer [0240] and the declarations [0241] $IsaUseTimer=1 [0242] $TimerNumber=2 [0243] $width=32 [0244] TPP generates wire [31:0] srCCount; wire ccountWEn; //-------------------------------------------------------------- // CCOUNT Register //-------------------------------------------------------------- assign ccountWEn = srWEn_W && (srWrAdr_W == {grave over ( )}SRCCOUNT); xtflop #(32) srccntreg (srCCount, (ccountWEn ? srDataIn_W : srCCount+1),CLK); //-------------------------------------------------------------- // CCOMPARE Register //-------------------------------------------------------------- wire [31:0] srCCompare0; wire ccompWEn0; assign ccompWEn0 = srWEn_W && (srWrAdr_W == {grave over ( )}SRCCOMPARE0); xtenflop #(32) srccmp0reg (srCCompare0,srDataIn_W, ccompWEn0,CLK); assign setCCompIntr0 = (srCCompare0 == srCCount); assign clrCCompIntr0 = ccompWEn0; //-------------------------------------------------------------- // CCOMPARE Register //-------------------------------------------------------------- wire [31:0] srCCompare1; wire ccompWEnl; assign ccompWEn1 = srWEn_W && (srWrAdr_W == {grave over ( )}SRCCOMPARE1); xtenflop #(32) srccmp1reg (srCCompare1,srDataIn_W,ccompWEn1, CLK); assign setCCompIntr1 = (srCCompare1 == srCCount); assign clrCCompIntr1 = ccompWEn1; [0245] The HDL description 114 thus generated is used to synthesize hardware for processor implementation using, e.g., the DesignCompiler™ manufactured by Synopsys Corporation in block 122. The result is then placed and routed using, e.g., Silicon Ensemble™ by Cadence Corporation or Apollo™ by Avant! Corporation in block 128. Once the components have been routed, the result can be used for wire back-annotation and timing verification in block 132 using, e.g., PrimeTime™ by Synopsys. The product of this process is a hardware profile 134 which can be used by the user to provide further input to the configuration capture routine 20 for further configuration iterations. [0246] As mentioned in connection with the logic synthesis section 122, one of the outcomes of configuring the processor 60 is a set of customized HDL files from which specific gate-level implementation can be obtained by using any of a number of commercial synthesis tools. One such a tool is Design Compiler™ from Synopsys. To ensure correct and high performance gate-level implementation, the preferred embodiment provides scripts necessary to automate the synthesis process in the customer environment. The challenge in providing such scripts is to support a wide variety of synthesis methodologies and different implementation objectives of users. To address the first challenge, the preferred embodiment breaks the scripts into smaller and functionally complete scripts. One such example is to provide a read script that can read all HDL files relevant to the particular processor configuration 60, a timing constraint script to set the unique timing requirement in the processor 60, and a script to write out synthesis results in a way that can be used for the placement and routing of the gate-level netlist. To address the second challenge, the preferred embodiment provides a script for each implementation objective. One such example is to provide a script for achieving fastest cycle time, a script for achieving minimum silicon area, and a script for achieving minimum power consumption. [0247] Scripts are used in other phases of processor configuration as well. For example, once the HDL model of the processor 60 has been written, a simulator can be used to verify the correct operation of the processor 60 as described above in connection with block 132. This is often accomplished by running many test programs, or diagnostics, on the simulated processor 60. Running a test program on the simulated processor 60 can require many steps such as generating an executable image of the test program, generating a representation of this executable image which can be read by the simulator 112, creating a temporary place where the results of the simulation can be gathered for future analysis, analyzing the results of the simulation, and so on. In the prior art this was done with a number of throw-away scripts. These scripts had some built-in knowledge of the simulation environment, such as which HDL files should be included, where those files could be found in the directory structure, which files are required for the test bench, and so on. In the current design the preferred mechanism is to write a script template which is configured by parameter substitution. The configuration mechanism also uses TPP to generate a list of the files that are required for simulation. Furthermore, in the verification process of block 132 it is often necessary to write other scripts which allow designers to run a series of test programs. This is often used to run regression suites that give a designer confidence that a given change in the HDL model does not introduce new bugs. These regression scripts were also often throw-away as they had many built-in assumptions about files names, locations, etc. As described above for the creation of a run script for a single test program the regression script is written as a template. This template is configured by substituting parameters for actual values at configuration time. [0248] The final step in the process of converting an RTL description to a hardware implementation is to use a place and route (P&R) software to convert the abstract netlist into a geometrical representation. The P&R software analyzes the connectivity of the netlist and decides upon the placement of the cells. It then tries to draw the connections between all the cells. The clock net usually deserves special attention and is routed as a last step. This process can be both helped by providing the tools with some information, such as which cells are expected to be close together (known as soft grouping), relative placement of cells, which nets are expected to have small propagation delays, and so on. [0249] To make this process easier and to ensure that the desired performance goals are met—cycle time, area, power dissipation—the configuration mechanism produces a set of scripts or input files for the P&R software. These scripts contain information as described above such as relative placements for cells. The scripts also contain information such as how many supply and ground connections are required, how these should be distributed along the boundary, etc. The scripts are generated by querying a database that contains information on how many soft groups to create and what cells should be contained in them, which nets are timing critical, etc. These parameters change based on which options have been selected. These scripts must be configurable depending on the tools to be used to do the place and route. [0250] Optionally the configuration mechanism can request more information from the user and pass it to the P&R scripts. For example the interface can ask the user the desired aspect ratio of the final layout, how many levels of buffering should be inserted in the clock tree, which side the input and output pins should be located on, relative, or absolute, placement of these pins, width and location of the power and ground straps, and so on. These parameters would then be passed on to the P&R scripts to generate the desired layout. [0251] Even more sophisticated scripts can be used that allow for example a more sophisticated clock tree. One common optimization done to reduce power dissipation is to gate the clock signal. However, this makes clock tree synthesis a much harder problem since it is more difficult to balance the delay of all branches. The configuration interface could ask the user for the correct cells to use for the clock tree and the perform part, or all, of the clock tree synthesis. It would do this by having some knowledge of where the gated clocks are located in the design and estimating the delay form the qualifying gate to the clock input of the flip flops. It would than give a constraint to the clock tree synthesis tool to match the delay of the clock buffer with the delay of the gating cells. In the current implementation this is done by a general purpose Perl script. This script reads gated clock information produced by the configuration agent based on which options are selected. The Perl script is run once the design has been placed and routed but before final clock tree synthesis is done. [0252] Further improvement can be made to the profile process described above. Specifically, we will describe a process by which the user can obtain the similar hardware profile information almost instantaneously without spending hours running those CAD tools. This process has several steps. [0253] The first step in this process is to partition the set of all configuration options into groups of orthogonal options such that effect of an option in a group on the hardware profile is independent of options in any other group. For example, the impact of MAC 16 unit to the hardware profile is independent of any other options. So, an option group with only the MAC 16 option is formed. A more complicated example is an option group containing interrupt options, high-level interrupt options and timer options, since the impact on the hardware profile is determined by the particular combination of these options. [0254] The second step is to characterize the, hardware profile impact of each option groups. The characterization is done by obtaining hardware profile impact for various combinations of options in the group. For each combination, the profile is obtained using a previously-described process in which an actual implementation is derived and its hardware profile is measured. Such information is stored in an estimation database. [0255] The last step is to derive specific formulae for computing hardware profile impact by particular combinations of options in the option groups using curve fitting and interpolation techniques. Depending on the nature of the options, different formulae are used. For example, since each additional interrupt vector adds about the same logic to the hardware, we use linear function to model its hardware impact. In another example, having a timer unit requires the high-priority interrupt option, so the formula for hardware impact of the timer option is conditional formulae involving several options. [0256] It is useful to provide quick feedback on how architectural choices may affect the runtime performance and code size of applications. Several sets of benchmark programs from multiple application domains are chosen. For each domain, a database is prebuilt that estimates how different architectural design decisions will affect the runtime performance and code size of the applications in the domain. As the user varies the architectural design, the database is queried for the application domain that interests the user or for multiple domains. The results of the evaluation are presented to the user so she can get an estimate on the tradeoff between software benefits and hardware costs. [0257] The quick evaluation system can be easily extended to provide the user with suggestions on how to modify a configuration to further optimize the processor. One such example is to associate each configuration option with a set of numbers representing the incremental impact of the option on various cost metrics such as area, delay and power. Computing the incremental cost impact for a given option is made easy with the quick evaluation system. It simply involves two calls to the evaluation system, with and without the option. The difference in the costs for the two evaluations represents the incremental impact of the option. For example, the incremental area impact of the MAC 16 option is computed by evaluating the area cost of two configurations, with and without the MAC 16 option. The difference is then displayed with the MAC 16 option in the interactive configuration system. Such a system can guide the user toward an optimal solution through a series of single-step improvements. [0258] Moving on to the software side of the automated processor configuration process, the preferred embodiment of this invention configures software development tools 30 so that they are specific to the processor. The configuration process begins with software tools 30 that can be ported to a variety of different systems and instruction set architectures. Such retargetable tools have been widely studied and are well-known in the art. The preferred embodiment uses the GNU family of tools, which is free software, including for example, the GNU C compiler, GNU assembler, GNU debugger, GNU linker, GNU profiler, and various utility programs. These tools 30 are then automatically configured by generating portions of the software directly from the ISA description and by using TPP to modify portions of the software that are written by hand. [0259] The GNU C compiler is configured in several different ways. Given the core ISA description, much of the machine-dependent logic in the compiler can be written by hand. This portion of the compiler is common to all configurations of the configurable processor instruction set, and retargeting by hand allows fine-tuning for best results. However, even for this hand-coded portion of the compiler, some code is generated automatically from the ISA description. Specifically, the ISA description defines the sets of constant values that can be used in immediate fields of various instructions. For each immediate field, a predicate function is generated to test if a particular constant value can be encoded in the field. The compiler uses these predicate functions when generating code for the processor 60. Automating this aspect of the compiler configuration eliminates an opportunity for inconsistency between the ISA description and the compiler, and it enables changing the constants in the ISA with minimal effort. [0260] Several aspects of the compiler are configured via preprocessing with TPP. For the configuration options controlled by parameter selection, corresponding parameters in the compiler are set via TPP. For example, the compiler has a flag variable to indicate whether the target processor 60 uses big endian or little endian byte ordering, and this variable is set automatically using a TPP command that reads the endianness parameter from the configuration specification 100. TPP is also used to conditionally enable or disable hand-coded portions of the compiler which generate code for optional ISA packages, based on whether the corresponding packages are enabled in the configuration specification. 100. For example, the code to generate multiply/accumulate instructions is only included in the compiler if the configuration specification includes the MAC 16 option 90. [0261] The compiler is also configured to support designer-defined instructions specified via the TIE language. There are two levels of this support. At the lowest level, the designer-defined instructions are available as macros, intrinsic functions, or inline (extrinsic) functions in the code being compiled. The preferred embodiment of this invention generates a C header file defining inline functions as “inline assembly” code (a standard feature of the GNU C compiler). Given the TIE specification of the designer-defined opcodes and their corresponding operands, generating this header file is a straightforward process of translating to the GNU C compiler's inline assembly syntax. An alternative implementation creates a header file containing C preprocessor macros that specify the inline assembly instructions. Yet another alternative uses TPP to add intrinsic functions directly into the compiler. [0262] The second level of support for designer-defined instructions is provided by having the compiler automatically recognize opportunities for using the instructions. These TIE instructions could be directly defined by the user or created automatically during the configuration process. Prior to compiling the user application, the TEE code is automatically examined and converted into C equivalent functions. This is the same step used to allow fast simulation of TIE instructions. The C equivalent functions are partially compiled into a tree-based intermediate representation used by the compiler. The representation for each TEE instruction is stored in a database. When the user application is compiled, part of the compilation process is a pattern matcher. The user application is compiled into the tree-based intermediate representation. The pattern matcher walks bottom-up every tree in the user program. At each step of the walk, the pattern matcher checks if the intermediate representation rooted at the current point matches any of the TIE instructions in the database. If there is a match, the match is noted. After finishing to walk each tree, the set of maximally sized matches are selected. Each maximal match in the tree is replaced with the equivalent TIE instruction. [0263] The algorithm described above will automatically recognize opportunities to use stateless TIE instructions. Additional approaches can also be used to automatically recognize opportunities to use TIE instructions with state. A previous section described algorithms for automatically selecting potential TIE instructions with state. The same algorithms are used to automatically use the TIE instructions in C or C++ applications. When a TIE coprocessor has been defined to have more registers but a limited set of operations, regions of code are scanned to see if they suffer from register spilling and if those regions only use the set of available operations. If such regions are found, the code in those regions is automatically changed to use the coprocessor instructions and registers 98. Conversion operations are generated at the boundaries of the region to move the data in and out of the coprocessor 98. Similarly, if a TIE coprocessor has been defined to work on different size integers, regions of the code are examined to see if all data in the region is accessed as if it were the different size. For matching regions, the code is changed and glue code is added at the boundaries. Similarly if a TIE coprocessor 98 has been defined to implement a C++ abstract data type, all the operations in that data type are replaced with the TIE coprocessor instructions. [0264] Note that suggesting TIE instructions automatically and utilizing TIE instructions automatically are both useful independently. Suggested TIE instructions can also be manually used by the user via the intrinsic mechanism and utilizing algorithms can be applied to TIE instructions or coprocessors 98 designed manually. [0265] Regardless of how designer-designed instructions are generated, either via inline functions or by automatic recognition, the compiler needs to know the potential side effects of the designer-defined instructions so that it can optimize and schedule these instructions. In order to improve performance, traditional compilers optimize user codes in order to maximize desired characteristics such as run-time performance, code size or power consumption. As is known to one well-versed in the art, such optimizations include things such as rearranging instructions or replacing certain instructions with other, semantically equivalent instructions. In order to perform optimizations well, the compiler must know how every instruction affects different portions of the machine. Two instructions that read and write different portions of the machine state can be freely reordered. Two instructions that access the same portion of the machine state can not always be-reordered. For traditional processors, the state read and/or written by different instructions is hardwired, sometimes by table, into the compiler. In one embodiment of this invention, TIE instructions are conservatively assumed to read and write all the state of the processor 60. This allows the compiler to generate correct code but limits the ability of the compiler to optimize code in the presence of TIE instructions. In another embodiment of this invention, a tool automatically reads the TIE definition and for each TIE instruction discovers which state is read or written by said instruction. This tool then modifies the tables used by the compiler's optimizer to accurately model the effect of each TIE instruction. [0266] Like the compiler, the machine-dependent portions of the assembler 110 include both automatically generated parts and hand-coded parts configured with TPP. Some of the features common to all configurations are supported with code written by hand. However, the primary task of the assembler 110 is to encode machine instructions, and instruction encoding and decoding software can be generated automatically from the ISA description. [0267] Because instruction encoding and decoding are useful in several different software tools, the preferred embodiment of this invention groups the software to perform those tasks into a separate software library. This library is generated automatically using the information in the ISA description. The library defines an enumeration of the opcodes, a function to efficiently map strings for opcode mnemonics onto members of the enumeration (stringToOpcode), and tables that for each opcode specify the instruction length (instructionLength), number of operands (numberOfOperands), operand fields, operand types (i.e., register or immediate) (operandType), binary encoding (encodeOpcode), and mnemonic string (opcodeName) For each operand field, the library provides accessor functions to encode (fieldSetFunction) and decode (fieldGetFunction) the corresponding bits in the instruction word. All of this information is readily available in the ISA description; generating the library software is merely a matter of translating the information into executable C code. For example, the instruction encodings are recorded in a C array variable where each entry is the encoding for a particular instruction, produced by setting each opcode field to the value specified for that instruction in the ISA description; the encodeOpcode function simply returns the array value for a given opcode. [0268] The library also provides a function to decode the opcode in a binary instruction (decode Instruction) This function is generated as a sequence of nested switch statements, where the outermost switch tests the subopcode field at the top of the opcode hierarchy, and the nested switch statements test the subopcode fields progressively lower in the opcode hierarchy. The generated code for this function thus has the same structure as the opcode hierarchy itself. [0269] Given this library for encoding and decoding instructions, the assembler 110 is easily implemented. For example, the instruction encoding logic in the assembler is quite simple: AssembleInstruction (String mnemonic, int arguments[]) begin opcode = stringToOpcode (mnemonic); if (opcode == UNDEFINED) Error(“Unknown opcode”); instruction = encodeOpcode(opcode); numArgs = numberOfOperands(opcode); for i = 0, numArgs−1 do begin setFun = fieldSetFunction(opcode, i); setFun(instruction, arguments[i]); end return instruction; end [0270] Implementing a disassembler 110, which translates binary instructions into a readable form closely resembling assembly code, is equally straightforward: DisassembleInstruction (BinaryInstruction instruction begin opcode = decodeInstruction(instruction); instructionAddress += instructionLength(opcode); print opcodeName(opcode); // Loop through the operands, disassembling each numArgs = numberOfOperands (opcode); for i = 0, numArgs−1 do begin type = operandType(opcode, i); getFun = fieldGetFunction(opcode, i); value = getFun(opcode, i, instruction); if (i != 0) print “,”; // Comma separate operands // Print based on the type of the operand switch (type) case register: print registerPrefix(type), value; case immediate: print value; case pc_relative_label: print instructionAddress + value; // etc. for more different operand types end end [0271] This disassembler algorithm is used in a standalone disassembler tool and also in the debugger 130 to support debugging of machine code. [0272] The linker is less sensitive to the configuration than the compiler and assembler 110. Much of the linker is standard and even the machine-dependent portions depend primarily on the core ISA description and can be hand-coded for a particular core ISA. Parameters such as endianness are set from the configuration specification 100 using TPP. The memory map of the target processor 60 is one other aspect of the configuration that is needed by the linker. As before, the parameters that specify the memory map are inserted into the linker using TPP. In the preferred embodiment of the invention, the GNU linker is driven by a set of linker scripts, and it is these linker scripts that contain the memory map information. An advantage of this approach is that additional linker scripts can be generated later, without reconfiguring the processor 60 and without rebuilding the linker, if the memory map of the target system is different than the memory map specified when the processor 60 was configured. Thus, the preferred embodiment includes a tool to configure new linker scripts with different memory map parameters. [0273] The debugger 130 provides mechanisms to observe the state of a program as it runs, to single-step the execution one instruction at a time, to introduce breakpoints, and to perform other standard debugging tasks. The program being debugged can be run either on a hardware implementation of the configured processor or on the ISS 126. The debugger presents the same interface to the user in either case. When the program is run on a hardware implementation, a small monitor program is included on the target system to control the execution of the user's program and to communicate with the debugger via a serial port. When the program is run on the simulator 126, the simulator 126 itself performs those functions. The debugger 130 depends on the configuration in several ways. It is linked with the instruction encoding/decoding library described above to support disassembling machine code from within the debugger 130. The part of the debugger 130 that displays the processor's register state, and the parts of the debug monitor program and ISS 126 that provide that information to the debugger 130, are generated by scanning the ISA description to find which registers exist in the processor 60. [0274] Other software development tools 30 are standard and need not be changed for each processor configuration. The profile viewer and various utility programs fall into this category. These tools may need to be retargeted once to operate on files in the binary format shared by all configurations of the processor 60, but they do not depend on either the ISA description or the other parameters in the configuration specification 100. [0275] The configuration specification is also used to configure a simulator called the ISS 126 shown in FIG. 13. The ISS 126 is a software application that models the functional behavior of the configurable processor instruction set. Unlike its counterpart processor hardware model simulators such as Synopsys VCS and Cadence Verilog XL and NC simulators, the ISS HDL model is an abstraction of the CPU during its instruction execution. The ISS 126 can run much faster than a hardware simulation because it does not need to model every signal transition for every gate and register in the complete processor design. [0276] The ISS 126 allows programs generated for the configured processor 60 to be executed on a host computer. It accurately reproduces the processor's reset and interrupt behavior allowing low-level programs such as device drivers and initialization code to be developed. This is particularly useful when porting native code to an embedded application. [0277] The ISS 126 can be used to identify potential problems such as architectural assumptions, memory ordering considerations and the like without needing to download the code to the actual embedded target. [0278] In the preferred embodiment, ISS semantics are expressed textually using a C-like language to build C operator building blocks that turn instructions into functions. For example, the rudimentary functionality of an interrupt, e.g., interrupt register, bit setting, interrupt level, vectors, etc., is modeled using this language. [0279] The configurable ISS 126 is used for the following four purposes or goals as part of the system design and verification process: [0280] debugging software applications before hardware becomes available; [0281] debugging system software (e.g., compilers and operating system components); [0282] comparing with HDL simulation for hardware design verification. ISS serves as a reference implementation of the ISA—the ISS and processor HDL are both run for diagnostics and applications during processor design verification and traces from the two are compared; and [0283] analyzing software application performance (this may be part of the configuration process, or it may be used for further application tuning after a processor configuration has been selected). [0284] All the goals require that the ISS 126 be able to load and decode programs produced with the configurable assembler 110 and linker. They also require that ISS execution of instructions be semantically equivalent to the corresponding hardware execution and to the compiler's expectations. For these reasons, the ISS 126 derives its decode and execution behavior from the same ISA files used to define the hardware and system software. [0285] For the first and last goals listed above, it is important for the ISS 126 to be as fast as possible for the required accuracy. The ISS 126 therefore permits dynamic control of the level of detail of the simulation. For example, cache details are not modeled unless requested, and cache modeling can be turned off and on dynamically. In addition, parts of the ISS 126 (e.g., cache and pipeline models) are configured before the ISS 126 is compiled so that the ISS 126 makes very few configuration-dependent choices of behavior at runtime. In this way, all ISS configurable behavior is derived from well-defined sources related to other parts of the system. [0286] For the first and third goals listed above, it is important for the ISS 126 to provide operating system services to applications when these services are not yet available from the OS for the system under design (the target). It is also important for these services to be provided by the target OS when that is a relevant part of the debugging process. In this way the system provides a design for flexibly moving these services between ISS host and simulation target. The current design relies on a combination of ISS dynamic control (trapping SYSCALL instructions may be turned on and off) and the use of a special SIMCALL instruction to request host OS services. [0287] The last goal requires the ISS 126 to model some aspects of processor and system behavior that are below the level specified by the ISA. In particular, the ISS cache models are constructed by generating C code for the models from Perl scripts which extract parameters from the configuration database 100. In addition, details of the pipeline behavior of instructions (e.g., interlocks based on register use and functional-unit availability requirements) are also derived from the configuration database 100. In the current implementation, a special pipeline description file specifies this information in a lisp-like syntax. [0288] The third goal requires precise control of interrupt behavior. For this purpose, a special non-architectural register in the ISS 126 is used to suppress interrupt enables. [0289] The ISS 126 provides several interfaces to support the different goals for its use: [0290] a batch or command line mode (generally used in connection with the first and last goals); [0291] a command loop mode, which provides non-symbolic debug capabilities, e.g. breakpoints, watchpoints, step, etc.—frequently used for all four goals; and [0292] a socket interface which allows the ISS 126 to be used by a software debugger as an execution backend (this must be configured to read and write the register state for the particular configuration selected). [0293] a scriptable interface which allows very detailed debugging and performance analysis. [0294] In particular, this interface may be used to compare application behavior on different configurations. For example, at any breakpoint the state from a run on one configuration may be compared with or transferred to the state from a run on another configuration. [0295] The simulator 126 also has both hand-coded and automatically generated portions. The hand-coded portions are conventional, except for the instruction decode and execution, which are created from tables generated from the ISA description language. The tables decode the instruction by starting from the primary opcode found in the instruction word to be executed, indexing into a table with the value of that field, and continuing until a leaf opcode, i.e., an opcode which is not defined in terms of other opcodes, is found. The tables then give a pointer to the code translated from the TIE code specified in the semantics declaration for the instruction. This code is executed to simulate the instruction. [0296] The ISS 126 can optionally profile the execution of the program being simulated. This profiling uses a program counter sampling technique known in the art. At regular intervals, the simulator 126 samples the PC (program counter) of the processor being simulated. It builds a histogram with the number of samples in each region of code. The simulator 126 also counts the number of times each edge in the call graph is executed by incrementing a counter whenever a call instruction is simulated. When the simulation is complete, the simulator 126 writes an output file containing both the histogram and call graph edge counts in a format that can be read by a standard profile viewer. Because the program 118 being simulated need not be modified with instrumentation code (as in standard profiling techniques), the profiling overhead does not affect the simulation results and the profiling is totally non-invasive. [0297] It is preferable that the system make available hardware processor emulation as well as software processor emulation. For this purpose, the preferred embodiment provides an emulation board. As shown in FIG. 6, the emulation board 200 uses a complex programmable logic device 202 such as the Altera Flex 10K200E to emulate, in hardware, a processor configuration 60. Once programmed with the processor netlist generated by the system, the CPLD device 202 is functionally equivalent to the final ASIC product. It provides the advantage that a physical implementation of the processor 60 is available that can run much faster than other simulation methods (like the ISS 126 or HDL) and is cycle accurate. However, it cannot reach the high frequency targets that the final ASIC device can get to. [0298] This board enables the designer to evaluate various processor configuration options and start software development and debugging early in the design cycle. It can also be used for the functional verification of the processor configuration. [0299] The emulation board 200 has several resources available on it to allow for easy software development, debugging and verification. These include the CPLD device 202 itself, EPROM 204, SRAM 206, synchronous SRAM 208, flash memory 210 and two RS232 serial channels 212. The serial channels 212 provide a communication link to UNIX or PC hosts for downloading and debugging user programs. The configuration of a processor 60, in terms of the CPLD netlist, is downloaded into the CPLD 202 through a dedicated serial link to device's configuration port 214 or through dedicated configuration ROMs 216. [0300] The resources available on the board 200 are configurable to a degree as well. The memory map of the various memory elements on the board can be easily changed, because the mapping is done through a Programmable Logic Device (PLD) 217 which can be easily changed. Also, the caches 218 and 228 that the processor core uses are expandable by using larger memory devices and appropriately sizing the tag busses 222 and 224 that connect to the caches 218 and 228. [0301] Using the board to emulate a particular processor configuration involves several steps. The first step is to obtain a set of RTL files which describe the particular configuration of the processor. The next step is to synthesize a gate-level netlist from the RTL description using any of a number of commercial synthesis tools. One such example is FPGA Express from Synopsys. The gate-level netlist can then be used to obtain a CPLD implementation using tools typica lly provided by vendors. One such tool is Maxplus2 from Altera Corporation. The final step is to download the implementation onto the CPLD chip on the emulation board using programmers provided again by the CPLD vendors. [0302] Since one of the purposes of the emulation board is to support quick prototype implementation for debugging purposes, it is important that the CPLD implementation process. outlined in the previous paragraph is automatic. To achieve this objective, the files delivered to users are customized by grouping all relevant files into a single directory. Then, a fully customized synthesis script is provided to be able to synthesize the particular processor configuration to the particular FPGA device selected by the customer. A fully customized implementation script to be used by the vendor tools is also generated. Such synthesis and implementation scripts guarantee functionally correct implementation with optimal performance. The functional correctness is achieved by including appropriate commands in the script to read in all RTL files relevant to the specific processor configuration by including appropriate commands to assign chip-pin locations based on I/O signals in the processor configuration and by including commands to obtain specific logic implementation for certain critical portions of the processor logic such at gated clocks. The script also improves the performance of the implementation by assigning detailed timing constraint to all processor I/O signals and by special processing of certain critical signals. One such example for timing constraints is assigning a specific input delay to a signal by taking into account the delay of that signal on the board. An example of critical signal treatment is to assign the clock signal to a dedicated global wire in order to achieve low clock skews on the CPLD chip. [0303] Preferably, the system also configures a verification suite for the configured processor 60. [0304] Most verification of complex designs like microprocessors consists of a flow as follows: [0305] build a test bench to stimulate the design and compare output either within the testbench or using an external model like the ISS 126; [0306] write diagnostics to generate the stimulus; [0307] measure coverage of verification using schemes like line coverage of finite state machine coverage HDL, declining bug rate, number of vectors run on the design; and [0308] if the coverage is not sufficient—write more diagnostics and maybe use tools to generate diagnostics to exercise the design further. [0309] The present invention uses a flow that is somewhat similar, but all components of the flow are modified to account for the configurability of the design. This methodology consists of the following steps: [0310] build a testbench for a particular configuration. Configuration of the testbench uses a similar approach as that described for the HDL and supports all options and extensions supported therein, i.e., cache sizes, bus interface, clocking, interrupt generation etc.; [0311] run self-checking diagnostics on a particular configuration of the HDL. Diagnostics themselves are configurable to tailor them for a particular piece of hardware. The selection of which diagnostics to run is also dependent on the configuration; [0312] run pseudo-randomly generated diagnostics and compare the processor state after the execution of each instruction against the ISS 126; and [0313] measure of coverage of verification—using coverage tools that measure functional as well as line coverage. Also, monitors and checkers are run along with the diagnostics to look for illegal states and conditions. All of these are configurable for a particular configuration specification. [0314] All of the verification components are configurable. The configurability is implemented using TPP. [0315] A test bench is a Verilog™ model of a system in which the configured processor 60 is placed. In the case of the present invention these test benches include: [0316] caches, bus interface, external memory; [0317] external interrupts and bus error generation; and [0318] clock generation. [0319] Since almost all of the above characteristics are configurable, the test bench itself needs to support configurability. So, for example, the cache size and width and number of external interrupts are automatically adjusted based on configuration. [0320] The testbench provides stimulus to the device under test—the processor 60. It does this by providing assembly level instructions (from diagnostics) that are preloaded into memory. It also generates signals that control the behavior of the processor 60—for example, interrupts. Also, the frequency and timing of these external signals is controllable and is automatically generated by the testbench. [0321] There are two types of configurability for diagnostics. First, diagnostics use TPP to determine what to test. For example, a diagnostic has been written to test software interrupts. This diagnostic will need to know how many software interrupts there are in order to generate the right assembly code. [0322] Second, the processor configuration system 10 must decide which diagnostics are suitable for this configuration. For example, a diagnostic written to test the MAC unit is not applicable to a processor 60 which does not include this unit. In the preferred embodiment this is accomplished through the use of a database containing information about each diagnostic. The database may contain for each diagnostic the following information: [0323] use the diagnostic if a certain option has been selected; [0324] if the diagnostic cannot be run with interrupts; [0325] if the diagnostic requires special libraries or handlers to run; and [0326] if the diagnostic cannot be run with cosimulation with ISS 126. [0327] Preferably the processor hardware description includes three types of test tools: test generator tools, monitors and coverage tools (or checkers), and a cosimulation mechanism. Test generation tools are tools that create a series of processor instructions in an intelligent fashion. They are sequences of pseudo-random test generators. The preferred embodiment uses two types internally—a specially-developed one called RTPG and another which is based on an external tool called VERA (VSG). Both have configurability built around them. Based on valid instructions for a configuration, they will generate a series of instructions. These tools will also be able to deal with newly defined instructions from TIE—so that these newly defined instructions are randomly generated for testing. The preferred embodiment includes monitors and checkers that measure the coverage of the design verification. [0328] Monitors and coverage tools are tools that are run alongside a regression run. Coverage tools monitor what the diagnostic is doing and the functions and logic of the HDL that it is exercising. All this information is collected throughout the regression run and is later analyzed to get some hints of what parts of the logic need further testing. The preferred embodiment uses several functional coverage tools that are configurable. For example, for a particular finite state machine not all states are included depending on a configuration. So, for that configuration the functional coverage tool must not try to check for those states or transitions. This is accomplished by making the tool configurable through TPP. [0329] Similarly, there are monitors that check for illegal conditions occurring within the HDL simulation. These illegal conditions could show up as bugs. For example on a three-state bus, 2 drivers should not be on simultaneously. These monitors are configurable—adding or removing checks based on whether a particular logic is included or not for that configuration. [0330] The cosimulation mechanism connects the HDL to the ISS 126. It is used to check that the state of the processor at the end of the instruction is identical in the HDL and the ISS 126. It too is configurable to the extent that it knows what features are included for each configuration and what state needs to be compared. So, for example, the data breakpoint feature adds a special register. This mechanism needs to know to compare this new special register. [0331] Instruction semantics specified via TIE can be translated to functionally equivalent C functions for use in the ISS 126 and for system designers to use for testing and verification. The semantics of an instruction in the configuration database 106 are translated to a C function by tools that build a parse tree using standard parser tools, and then code that walks the tree and outputs the corresponding expressions in the C language. The translation requires a prepass to assign bit widths to all expressions and to rewrite the parse tree to simplify some translations. These translators are relatively simple compared to other translators, such as HDL to C or C to assembly language compilers, and can be written by one skilled in the art starting from the TIE and C language specification. [0332] Using a compiler configured using the configuration file 100 and the assembler/disassembler 100, benchmark application source code 118 is compiled and assembled and, using a sample data set 124, simulated to obtain a software profile 130 which also is provided to the user configuration capture routine for feedback to the user. [0333] Having the ability to obtain both the hardware and software cost/benefit characterizations for any configuration parameter selections opens up new opportunities for further optimization of the system by the designers. Specifically this will enable designers to select the optimal configuration parameters which optimize the overall systems according to some figure of merit. One possible process is based on a-greedy strategy, by repeatedly selecting or de-selecting a configuration parameter. At each step, the parameter that has the best impact on the overall system performance and cost is selected. This step is repeated until no single parameter can be changed to improve the system performance and cost. Other extensions include looking at a group of configuration parameters at a time or employing more sophisticated searching algorithms. [0334] In addition to obtaining optimal configuration parameter selection, this process can also be used to construct optimal processor extensions. Because of the large number of possibilities in the processor extensions, it is important to restrict the number of extension candidates. One technique is to analyze the application software and only look at the instruction extensions that can improve the system performance or cost. [0335] Having covered the operation of an automated processor configuration system according to the preferred embodiment, examples now will be given of application of the system to processor microarchitecture configuration. The first example shows the advantages of the present invention as applied to image compression. [0336] Motion estimation is an important component of many image compression algorithms, including MPEG video and H263 conference applications. Video image compression attempts to use the similarities from one frame to the next to reduce the amount of storage required for each frame. In the simplest case, each block of an image to be compressed can be compared to the corresponding block (the same X,Y location) of the reference image (one that closely precedes or follows the image being compressed). The compression of the image differences between frames is generally more bit-efficient than compression of the individual images. In video sequences, the distinctive image features often move from frame to frame, so the closest correspondence between blocks in different frames is often not at exactly the same X,Y location, but at some offset. If significant parts of the image are moving between frames, it may be necessary to identify and compensate for the movement, before computing the difference. This fact means that the densest representation can be achieved by encoding the difference between successive images, including, for distinctive features, an X, Y offset in the sub-images used in the computed difference. The offset in the location used for computing the image difference is called the motion vector. [0337] The most computationally intensive task in this kind of image compression is the determination of the most appropriate motion vector for each block. The common metric for selecting the motion vector is to find the vector with the lowest average pixel-by-pixel difference between each block of the image being compressed and a set-of candidate blocks of the previous image. The candidate blocks are the set of all the blocks in a neighborhood around the location of the block being compressed. The size of the image, the size of the block and size of the neighborhood all affect the running time of the motion estimation algorithm. [0338] Simple block-based motion estimation compares each sub-image of the image to be compressed against a reference image. The reference image may precede or follow the subject image in the video sequence. In every case, the reference image is known to be available to the decompression system before the subject image is decompressed. The comparison of one block of an image under compression with candidate blocks of a reference image is illustrated below. [0339] For each block in the subject image, a search is performed around the corresponding location in the reference image. Normally each color component (e.g., YUV) of the images is analyzed separately. Sometimes motion estimation is performed only on one component, especially luminance. The average pixel-by-pixel difference is computed between that subject block and every possible block in the search zone of the reference image. The difference is the absolute value of the difference in magnitude of the pixel values. The average is proportional to the sum over the N2 pixels in the pair of blocks (where N is the dimension of the block). The block of the reference image that produces the smallest average pixel difference defines the motion vector for that block of the subject image. [0340] The following example shows a simple form of a motion estimation algorithm, then optimizes the algorithm using TIE for a small application-specific functional unit. This optimization yields a speed-up of more than a factor of 10, making processor-based compression feasible for many video, applications. It illustrates the power of a configurable processor that combines the ease of programming in a high-level language with the efficiency of special-purpose hardware. [0341] This example uses two matrices, OldB and NewB, to respectively represent the old and new images. The size of the image is determined by NX and NY. The block size is determined by BLOCKX and BLOCKY. Therefore, the image is composed of NX/BLOCKX by NY/BLOCKY blocks. The search region around a block is determined by SEARCHX and SEARCHY. The best motion vectors and values are stored in VectX, VectY, and VectB. The best motion vectors and values computed by the base (reference) implementation are stored in BaseX; BaseY, and BaseB. These values are used to check against the vectors computed by the implementation using instruction extensions. These basic definitions are captured in the following C-code segment: #define NX 64 /* image width */ #define NY 32 /* image height */ #define BLOCKX 16 /* block width */ #define BLOCKY 16 /* block height */ #define SEARCHX 4 /* search region width */ #define SEARCHY 4 / search region height */ unsigned char 01dB[NX] [NY]; /* old image */ unsigned char NewB[NX] [NY]; /* new image */ unsigned short VectX[NX/BLOCKX] [NY/BLOCKY]; /* X motion vector */ unsigned short VectY[NX/BLOCKX] [NY/BLOCKY]; /* Y motion vector */ unsigned short VectB[NX/BLOCKX] [NY/BLOCKY]; /* absolute difference */ unsigned short BaseX[NX/BLOCKX] /* Base X motion [NY/BLOCKY]; vector */ unsigned short BaseY[NX/BLOCKX] / Base Y motion [NY/BLOCKY]; vector */ unsigned short BaseB[NX/BLOCKX] [NY/BLOCKY]; /* Base absolute difference*/ #define ABS(x) (((x) < 0) ? (−(x)) : (x)) #define MIN (x, y) (((x) < (y)) ? (x) : (y)) #define MAX (x, y) (((x) > (y)) ? (x) : (y)) #define ABSD(x,y) (((x) > (y)) ? ((x) − (y)) : ((y) − (x))) [0342] The motion estimation algorithm is comprised of three nested loops: [0343] 1. For each source block in the old image. [0344] 2. For each destination block of the new image in the surrounding region of the source block. [0345] 3. Compute the absolute difference between each pair of pixels. [0346] The complete code for the algorithm is listed below. /*********************************************************************** Reference software implementation ***********************************************************************/ void motion_estimate_base() { int bx, by, cx, Cyr x, y; int startx, starty, endx, endy; unsigned cliff, best, bestx, best y; for(bx = 0; bx < NX/BLOCKX; bx++) { for (by = 0; by < NY/BLOCKY; by++) { best = bestx = besty = UINT_MAX; startx = MAX(0, bx*BLOCKX − SEARCHX); starty = MAX(0, by*BLOCKY − SEARCHY); endx = MIN(NX−BLOCKX, bx*BLOCKX + SEARCHX); endy = MIN (NY−BLOCKY, by*BLOCKY + SEARCHY); for(cx = startx: cx < endx; cx++) { for(cy = starty; cy < endy; cy++) { diff = 0; for(x = 0; x < BLOCKX; x++) { for(y = 0; y < BLOCKY; y++) { diff += ABSD(OldB[cx+x] [cy+y], NewB[bx*BLOCKX+x] [by*BLOCKY+y]); } } if (diff < best) { best = cliff; bestx = cx; besty = cy; } } } BaseX[bx] [by] = bestx; BaseY[bx] [by] = besty; BaseB[bx] [by] = best; } } } [0347] While the basic implementation is simple, it fails to exploit much of the intrinsic parallelism of this block to block comparison. The configurable processor architecture provides two key tools to allow significant speed-up of this application. [0348] First, the instruction set architecture includes powerful funnel shifting primitives to permit rapid extraction of unaligned fields in memory. This allows the inner loop of the pixel comparison to fetch groups of adjacent pixels from memory efficiently. The loop can then be rewritten to operate on four pixels (bytes) simultaneously. In particular, for the purposes of this example it is desirable to define a new instruction to compute the absolute difference of four pixel pairs at a time. Before-defining this new instruction, however, it is necessary to re-implement the algorithm to make use of such an instruction. [0349] The presence of this instruction allows such improvement in the inner loop pixel difference computation that loop unrolling becomes attractive as well. The C code for the inner loop is rewritten to take advantage of the new sum-of-absolute-differences instruction and the efficient shifting. Part of four overlapping blocks of the reference image can then be compared in the same loop. SAD (x, y) is the new intrinsic function corresponding to the added instruction. SRC (x, y) performs a right shift of the concatenation of x and y by the shift amount stored in the SAR register. /************************************************************ Fast version of motion estimation which uses the SAD instruction. ************************************************************/ void motion_estimate_tie( ) { int bx, by, cx, cy, x; int startx, starty, endx, endy; unsigned diff0, diff1, diff2, diff3, best, bestx, besty; unsigned *N, N1, N2, N3, N4, *O, A, B, C, D, E; for(bx = 0; bx < NX/BLOCKX; bx++) { for(by = 0; by < NY/BLOCKY; by++) { best = bestx = besty = UINT_MAX; startx = MAX(0, bx*BLOCKX − SEARCHX); starty = MAX(0, by*BLOCKY − SEARCHY); endx = MIN(NX−BLOCKX, bx*BLOCKX + SEARCHX); endy = MIN(NY−BLOCKY, by*BLOCKY + SEARCHY); for(cy = starty; cy < endy; cy += sizeof(long)) { for(cx = startx; cx < endx; cx++) { diff0 = diff1 = diff2 = diff3 = 0; for(x = 0; x < BLOCKX; x++) { N = (unsigned *) & (NewB[bx*BLOCKX+x] [by*BLOCKY]); N1 = N[0]; N2 = N[1]; N3 = N[2]; N4 = N[3]; O = (unsigned *) &(OldB[cx+x] [cy]); A = O[0]; B = O[1]; C = O[2]; D = O[3]; E = O[4]; diff0 += SAD(A, N1) + SAD(B, N2) + SAD (C, N3) + SAD(D, N4); SSAI (8): diff1 += SAD(SRC(B,A), N1) + SAD(SRC(C,B), N2) + SAD(SRC(D,C), N3) + SAD(SRC(E,D), N4); SSAI(16); diff2 += SAD(SRC(B,A), N1) + SAD(SRC(C,B), N2) + SAD(SRC(D,C), N3) + SAD(SRC(E,D), N4): SSAI (24); diff3 += SAD(SRC(B,A), N1) + SAD(SRC(C,B), N2) + SAD(SRC(D,C), N3) + SAD(SRC(E,D), N4); O += NY/4; N += NY/4; } if (diff0 < best) { best = diff0; bestx = cx; besty = cy; } if (diff1 < best) { best = diff1; bestx = cx; besty = cy + 1; } if (diff2 < best) { best = diff2; bestx = cx; besty = cy + 2; } if (diff3 < best) { best = diff3; bestx = cx; besty = cy + 3; } } } VectX[bx] [by] = bestx; VectY[bx] [by] = besty; VectB[bx] [by] = best; } } } [0350] This implementation uses the following SAD function to emulate the eventual new instruction: /************************************************************ Sum of absolute difference of four bytes ***********************************************************/ static inline unsigned SAD(unsigned ars, unsigned art) { return ABSD(ars >> 24, art >> 24) + ABSD((ars >> 16) & 255, (art >> 16) & 255) + ABSD((ars >> 8) & 255, (art >> 8) & 255) + ABSD(ars & 255, art & 255); [0351] To debug this new implementation, the following test program is used to compare the motion vectors and values computed by the new implementation and the base implementation: /************************************************************ Main test ************************************************************/ int main(int argc, char **argv) { int passwd; #ifndef NOPRINTF printf(“Block=(%d,%d), Search=(%d,%d), size=(%d,%d)\n”, BLOCKX, BLOCKY, SEARCHX, SEARCHY, NX, NY); #endif init ( ); motion estimate base( ); motion estimate tie( ); passwd = check( ); #ifndef NOPRINTF printf(passwd ? “TIE version passed\n” : “** TIE version failed\n”); #endif return passwd; } [0352] This simple test program will be used throughout the development process. One important convention that must be followed here is that the main program must return 0 when an error is detected and 1 otherwise. [0353] The use of TIE permits rapid specification of new instructions. The configfurable processor generator can fully implement these instructions in both the hardware implementation and the software development tools. Hardware synthesis creates an optimal integration of the new function into the hardware datapath. The configurable processor software environment fully supports the new instructions in the C and C++ compilers, the assembler, the symbolic debugger, the profiler and the cycle-accurate instruction set simulator. The rapid regeneration of hardware and software makes application-specific instructions a quick and reliable tool for application acceleration. [0354] This example uses TIE to implement a simple instruction to perform pixel differencing, absolute value and accumulation on four pixels in parallel. This single instruction does eleven basic operations (which in a conventional process might require separate instructions) as an atomic operation. The following is the complete description: // define a new opcode for Sum of Absolute Difference (SAD) // from which instruction decoding logic is derived opcode SAD opt=4′b0000 CUSTO // define a new instruction class // from which compiler, assembler, disassembler // routines are derived iclass sad (SAD) (out arr, in ars, in art) // semantic definition from which instruction-set // simulation and RTL descriptions, are derived semantic sad-logic (SAD) wire [8:0] diff01, diff11, diff21, diff31; wire [7:0] diffOr, diff1r, diff2r, diff3r; assign diff01 = art[7:0] − ars[7:0]; assign diff11 = art[15:8] − ars[15:8]; assign diff21 = art[23:16] − ars[23:16]; assign diff31 = art[31:24] − ars[31:24]; assign diffOr = ars[7:0] − art [7:0]; assign diff1r = ars[15:8] − art[15:8]; assign diff2r = ars[23:16] − art[23:16]; assign diff3r = ars[31:24] − art[31:24]; assign arr = (diff01[8] ? diffOr : diff01) + (diff11[8] ? diff1r : diff11) + (diff21[8] ? diff2r : diff21) + (diff31[8] ? diff3r : diff31); ) [0355] This description represents the minimum steps needed to define a new instruction. First, it is necessary to define a new opcode for the instruction. In this case, the new opcode SAD is defined as a sub-opcode of CUST0. As noted above, CUST0 is predefined as: [0356] opcode QRST op0=4′b0000 [0357] opcode CUST0 opl=4′b0100 QRST [0358] It is easy to see that QRST is the top-level opcode. CUST0 is a sub-opcode of QRST and SAD in turn a sub-opcode of CUST0. This hierarchical organization of opcodes allow logical grouping and management of the opcode spaces. One important thing to remember is that CUST0 (and CUST1) are defined as reserved opcode space for users to add new instructions. It is preferred that users stay within this allocated opcode space to ensure future re-usability of TIE descriptions. [0359] The second step in this TIE description is to define a new instruction class containing the new instruction SAD. This is where the operands of SAD instruction is defined. In this case, SAD consists of three register operands, destination register arr and source registers ars and art. As noted previously, arr is defined as the register indexed by the r field of the instruction, ars and art are defined as registers indexed by the s and t fields of the instruction. [0360] The last block in this description gives the formal semantic definitions for the SAD instruction. The description is using a subset of Verilog HDL language for describing combination logic. It is this block that defines precisely how the ISS will simulate the SAD instruction and how an additional circuitry is synthesized and added to the configurable processor hardware to support the new instruction. [0361] Next, the TIE description is debugged and verified using the tools previously described. After verifying the correctness of the TIE description, the next step is to estimate the impact of the new instruction on the hardware size and performance. As noted above, this can be done using, e.g., Design Compiler™. When Design Compiler finishes, the user can look at the output for detailed area and speed reports. [0362] After verifying that the TIE description is correct and efficient, it is time to configure and build a configurable processor that also supports the new SAD instruction. This is done using the GUI as described above. [0363] Next, the motion estimation code is compiled into code for the configurable processor which uses the instruction set simulator to verify the correctness of the program and more importantly to measure the performance. This is done in three steps: run the test program using the simulator; run just the base implementation to get the instruction count; and run just the new implementation to get the instruction count [0364] The following is the simulation output of the second step: Block=(16,16), Search=(4,4), size=(32,32) TIE version passed Simulation Completed Successfully Time for Simulation = 0.98 seconds Number per 100 Events Number instrs Instructions 226005 (100.00) Unconditional taken branches 454 (0.20) Conditional branches 37149 (16.44) Taken 26947 (11.92) Not taken 10202 (4.51) Window Overflows 20 (0.01) Window Underflows 19 (0.01) [0365] The following is the simulation output of the last step: [0366] Block=(16,16), Search=(4,4), size=(32,32) [0367] TIE version passed [0368] Simulation Completed Successfully [0369] Time for Simulation=0.36 seconds Block=(16,16), Search=(4,4), size=(32,32) TIE version passed Simulation Completed Successfully Time for Simulation = 0.36 seconds Number per 100 Events Number instrs Instructions 51743 (100.00) Unconditional taken branches 706 (1.36) Conditional branches 3541 (6.84) Taken 2759 (5.33) Not taken 782 (1.51) Window Overflows 20 (0.04) Window Underflows 19 (0.04) [0370] From the two reports one can see that roughly a 4× speedup has occurred. Notice that the the configurable processor instruction set simulator can provide much other useful information. [0371] After verifying the correctness and performance of the program, the next step is to run the test program using a Verilog simulator as described above. Those skilled in the art can glean the details of this process from the makefile of Appendix C (associated files also are shown in Appendix C). The purpose of this simulation is to further verify the correctness of the new implementation and more importantly to make this test program as part of the regression test for this configured processor. [0372] Finally, the processor logic can be synthesized using, e.g., Design Compiler™ and placed and routed using, e.g., Apollo™. [0373] This example has taken a simplified view of video compression and motion estimation for the sake of clarity and simplicity of explanation. In reality, there are many additional nuances in the standard compression algorithms. For example, MPEG 2 typically does motion estimation and compensation with sub-pixel resolution. Two adjacent rows or columns of pixels can be averaged to create a set of pixels interpolated to an imaginary position halfway between the two rows or columns. The configurable processor's user-defined instructions are again useful here, since a parallel pixel averaging instruction is easily implemented in just three or four lines of TIE code. Averaging between pixels in a row again uses the efficient alignment operations of the processor's standard instruction set. [0374] Thus, the incorporation of a simple sum-of-absolute-differences instruction adds just a few hundred gates, yet improves motion estimation performance by more than a factor of ten. This acceleration represents significant improvements in cost and power efficiency of the final system. Moreover, the seamless extension of the software development tools to include the new motionestimation instruction allows for rapid prototyping, performance analysis and release of the complete software application solution. The solution of the present invention makes application-specific processor configuration simple, reliable and complete, and offers dramatic enhancement of the cost, performance, functionality and power-efficiency of the final system product. [0375] As an example focusing on the addition of a functional hardware unit, consider the base configuration shown in FIG. 6 which includes the processor control function, program counter (PC), branch selection, instruction memory or cache and instruction decoder, and the basic integer datapath including the main register file, bypassing multiplexers, pipeline registers, ALU, address generator and data memory for the cache. [0376] The HDL is written with the presence of the multiplier logic being conditional upon the “multiplier” parameter being set, and a multiplier unit is added as a new pipeline stage as shown in FIG. 7 (changes to exception handling may be required if precise exceptions are to be supported). Of course, instructions for making use of the multiplier are preferably added concomitantly with the new unit. [0377] As a second example, a full coprocessor may be added to the base configuration as shown in FIG. 8 for a digital signal processor such as a multiply/accumulate unit. This entails changes in processor control such as adding decoding control signals for multiply-accumulate operations, including decoding of register sources and destinations from extended instructions; adding appropriate pipeline delays for control signals; extending register destination logic; adding control for a register bypass multiplexer for moves from accumulate registers, and the inclusion of a multiply-accumulate unit as a possible source for an instruction result. Additionally, it requires addition of a multiply-accumulate unit which entails additional accumulator registers, a multiply-accumulate array and source select multiplexers for main register sources. Also, addition of the coprocessor entails extension of the register bypass multiplexer from the accumulate registers to take a source from the accumulate registers, and extension of the load/alignment multiplexer to take a source from the multiplier result. Again, the system preferably adds instructions for using the new functional unit along with the actual hardware. [0378] Another option that is particularly useful in connection with digital signal processors is a floating point unit. Such a functional unit implementing, e.g., the IEEE 754 single-precision floating point operation standard may be added along with instructions for accessing it. The floating point unit may be used, e.g., in digital signal processing applications such as audio compression and decompression. [0379] As yet another example of the system's flexibility, consider the 4 kB memory interface shown in FIG. 9. Using the configurability of the present invention, coprocessor registers and datapaths may be wider or narrower than the main integer register files and datapaths, and the local memory width may be varied so that the memory width is equal to the widest processor or coprocessor width (addressing of memory on reads and writes being adjusted accordingly). For example, FIG. 10 shows a local memory system for a processor that supports loads and stores of 32 bits to a processor/coprocessor combination addressing the same array, but where the coprocessor supports loads and stores of 128 bits. This can be implemented using the TPP code function memory(Select,A1,A2,DI1,DI2,W1,W2,DO1,D02) ; $B1 = config get value(“width_of_port_1”); $B2 = config_get_value(“width_of_port 2”); ; $Bytes = config_get_value(“size_of_memory”); ; $Max = max($B1,$B2); $Min = min($B1,$B2); ; $Banks = $Max/$Min; ; $Wide1 = ($Max == $B1); $Wide2 = ($Max == $B2); ; Depth = $Bytes/(log2($Banks)*log2($Max)); wire [‘$Max’*8−1:0] Data1 = ‘$Wide1‘?DI1:{‘$Banks‘{DI1}}; wire [‘$Max’*8−1:0] Data2 = ‘$Wide1‘?DI2:{‘$Banks‘{DI2}}); wire [‘$Max’*8−1:0] D = Select ? Data1 : Data2: wire Wide = Select ? Wide1: Wide2; wire [log2(‘$Bytes‘)−1:0] A = Select? A1 : A2; wire [log2(‘$Bytes‘)−1:0] Address = A[log2(‘$Bytes‘)−1:log2(‘$Banks‘)]: wire [log2(‘$Banks‘)−1:0] Lane = A[log2(‘$Banks’)−1:0]: ; for ($i=0; $i<$Banks; $i++) { wire WrEnable{i} = Wide | (Lane == {i}); wire [log2(‘$Min‘)−1:0] WrData’$i’ = D[({i}+1)*‘$Min‘*8−1: {i}*‘$Min‘*8] ram(RdData‘$i‘,Depth,Address,WrData‘$i‘,WrEnable‘$i‘); ;} wire [‘$Max‘*8−1:0] RdData = { ;for ($i=0; $i<$Banks; $i++) { RdData‘$i‘, ;} } wire [‘$B1‘*8−1:0] DO1 = Wide1?RdData:RdData[(Lane+1)*B1*8−1: Lane*B1*8]; wire [‘$B2‘*8−1:0] D02 = Wide2?RdData:RdData[(Lane+1)*B2*8−1: Lane*B2*8]; [0380] where $Bytes is the total memory size accessed either as width B1 bytes at byte address A1 with data bus D1 under control of write signal W1, or using corresponding parameters B2, A2, D2 and W2. Only one set of signals, defined by Select, is active in a given cycle. The TPP code implements the memory as a collection of memory banks. The width of each bank is given by the minimum access width and the number of banks by the ratio of the maximum and minimum access widths. A for loop is used to instantiate each memory bank and its associated write signals, i.e., write enable and write data. A second for loop is used to gather the data read from all the banks into a single bus. [0381] [0381]FIG. 11 shows an example of the inclusion of user-defined instructions in the base, configuration. As shown in the Figure, simple instructions may be added-to the processor pipeline with timing and interface similar to that of the ALU. Instructions added in this way must generate no stalls or exceptions, contain no state, use only the two normal source register values and the instruction word as inputs, and generate a single output value. If, however, the TIE language has provisions for specifying processor state, such constraints are not necessary. [0382] [0382]FIG. 12 shows another example of implementation of a user-defined unit under this system. The functional unit shown in the Figure, an {fraction (8/16)} parallel data unit extension of the ALU, is generated from the following ISA code: Instruction { Opcode ADD8_4 CUSTOM op2=0000 Opcode MIN16-2 CUSTOM op2=0001 Opcode SHIFT16_2 CUSTOM op2=0002 iclass MY 4ADD8,2MIN16,SHIFT16_2 a<t,a<s,a>t } Implementation input [31:0] art, ars; input [23:0] inst; input ADD8_4, MIN16 _2, SHIFT16_2; output [31:0] arr; wire [31:0] add, min, shift; assign add = (art[31:24] + ars[31:24], art[23:16] + art[23:16], art[15:8] + art[15:8], art[7:0] + art[7:0]); assign min[31:16] = art[31:16] < ars[31:16] ? Art[31:16] : ars[31:16]: assign min[15:0] = art[15:0] < ars[15:0] ? Art[15:0] : ars[15:0]; assign shift[31:16] = art[31:16] ars[31:16]; assign shift[15:0] = art[15:0] ars[15:0]; assign arr = {321ADD8_4}} & add | {32(MIN16_2}} & min | {32{SHIFTI6 2}} & shift; } [0383] Modifications and variations of the preferred embodiment will be readily apparent to those skilled in the art. Such variations are within the scope of the present invention as defined by the appended claims. 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