Source: http://www.google.fr/patents/US6317819
Timestamp: 2013-05-24 22:16:19
Document Index: 160899513

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'ART 9', 'ART 9', 'ART 9', 'ART 9', 'ART 9']

Brevet US6317819 - Digital signal processor containing scalar processor and a plurality of ... - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Historique Web | Connexion Recherche avanc�e dans les brevets BrevetsA digital data processor integrated circuit (1) includes a plurality of functionally identical first processor elements (6A) and a second processor element (5). The first processor elements are bidirectionally coupled to a first cache (12) via a crossbar switch matrix (8). The second processor element...http://www.google.fr/patents/US6317819?utm_source=gb-gplus-shareBrevet US6317819 - Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction Num�ro de publicationUS6317819 B1Type de publicationOctroi Num�ro de demande09/256,961 Date de publication13 nov. 2001 Date de d�p�t24 f�vr. 1999 Date de priorit�22 sept. 1968 InventeursSteven G. Morton Cessionnaire d'origineTevton Digital Application Ag, LlcUnited States Government As Represented By The Secretary Of The Army Classification aux �tats-Unis712/22712/2712/10712/E09.35712/E09.71711/147711/E12.51712/E09.5712/E09.27 Classification internationaleG06F15/80G06F9/38G06F9/30G06F9/45G06F9/318G06F12/08 Classification coop�rativeG06F9/3885G06F9/30072G06F9/30101G06F9/3012G06F9/30141G06F9/30127G06F15/8092G06F9/3887G06F8/45G06F12/0859G06F9/30138 Classification europ�enneG06F 9/30R5G06F 9/30A5G06F 9/38T4G06F 15/80V6G06F 8/45G06F 9/30R6G06F 9/30R5C2G06F 9/30R2G06F 9/30R5XG06F 12/08B6P4G06F 9/38TR�f�rencesCitations de brevets (24) R�f�renc� par (55)Liens externesUSPTO Cession USPTO EspacenetDigital signal processor containing scalar processor and a plurality of vector processors operating from a single instructionUS 6317819 B1 R�sum� A digital data processor integrated circuit (1) includes a plurality of functionally identical first processor elements (6A) and a second processor element (5). The first processor elements are bidirectionally coupled to a first cache (12) via a crossbar switch matrix (8). The second processor element is coupled to a second cache (11). Each of the first cache and the second cache contain a two-way, set-associative cache memory that uses a least-recently-used (LRU) replacement algorithm and that operates with a use-as-fill mode to minimize a number of wait states said processor elements need experience before continuing execution after a cache-miss. An operation of each of the first processor elements and an operation of the second processor element are locked together during an execution of a single instruction read from the second cache. The instruction specifies, in a first portion that is coupled in common to each of the plurality of first processor elements, the operation of each of the plurality of first processor elements in parallel. A second portion of the instruction specifies the operation of the second processor element. Also included is a motion estimator (7) and an internal data bus coupling together a first parallel port (3A), a second parallel port (3B), a third parallel port (3C), an external memory interface (2), and a data input/output of the first cache and the second cache.
CLAIM OF PRIORITY FROM PROVISIONAL PATENT APPLICATION This patent application claims priority under 35 U.S.C. �119(e) from copending Provisional Patent Application No. 60/077,041, filed on Mar. 6, 1998, the disclosure of which is incorporated by reference herein in its entirety.
CROSS-REFERENCE TO A RELATED PATENT APPLICATION This patent application is a continuation-in-part of copending U.S. patent application Ser. No. 09/158,208, filed Sep. 22, 1998, entitled �DSP Having a Plurality of Like Processors Controlled in Parallel by an Instruction Word, and a Control Processor Also Controlled by the Instruction Word� by Steven G. Morton (now U.S. Pat. No. 6,088,783, issued Jul. 11, 2000), which is a continuation of U.S. patent application Ser. No. 08/602,220, filed Feb. 16, 1996, now U.S. Pat. No.: 5,822,606, issued Oct. 13, 1998, which claims priority from Provisional Patent Application No. 60/009,800, filed Jan. 6, 1996. The disclosure of U.S. Pat. No. 5,822,606, issued Oct. 13, 1998, is incorporated by reference herein in its entirety.
STATEMENT OF GOVERNMENT RIGHTS This invention was made with government support under grant number DAAB07-93-C-027 awarded by the U.S. Army SBIR. The government has certain rights in this invention.
FIELD OF THE INVENTION This invention relates generally to digital data processors and, in particular, to digital data processors that are implemented as integrated circuits to process input data in parallel, as well as to techniques for programming such data processors.
BACKGROUND OF THE INVENTION Digital signal processor (DSP) devices are well known in the art. Such devices are typically used to process data in real time, and can be found in communications devices, image processors, video processors, and pattern recognition processors.
OBJECTS AND ADVANTAGES OF THE INVENTION It is a first object and advantage of this invention to provide an improved DSP having a capability to enable a single instruction unit to simultaneously control a plurality of processors in parallel using a group of bits.
DETAILED DESCRIPTION OF THE INVENTION 1. Architecture
Two serial interfaces 9, 10 are provided to provide interfacing with �slow� devices. The UART 9 provides four pins for interfacing with RS-232 devices. The serial bus 10 provides two pins for interfacing with a serial EEPROM, that contains a bootstrap routine, and other devices that utilize a simple 2-wire communication protocol.
The hardware multiplier is a 16-bit�16-bit, two stage, 2's complement multiplier. The multiplier is segmented into two stages to allow for higher frequencies of operation. The first stage is responsible for producing and shifting partial products. The second stage, separated from the first by a register, is responsible for summing the partial products and producing a 32-bit product. The diagram in FIG. 2-5 illustrates the two stages.
A quad packed byte is four contiguous address locations, where each address provides one byte. Rotates move the four byte �window� to any set of four locations. FIG. 3-2 demonstrates two rotate examples.
The second step is to find the absolute value of each of the computed differences. This is performed by determining the sign of the result. Referring to FIG. 4-1, S0, S1, . . . , and S7 represent the sign of the difference result from the vector processor 6A ALUs. If the result is negative then it is transformed into a positive result by inverting and adding a �1� (2's complement) to the sum at some point in the summing tree. If the result is positive then no transformation is performed.
The seven summing nodes in step 3 have carry ins that are derived from the sign bits of the computed differences from step 1. For each difference that is negative, a �1� needs to be added into the final result since the 2's complement of a negative difference was taken.
The best pixel distance value is found by executing a series of pixel distance calculations that are accumulated in the pixel distance register and storing the best result in another register. A series of calculations is typically a 16�16 pixel block. The series is terminated by reading the pixel distance register. A diagram of this process is illustrated in FIG. 4-2.
The scalar processor 5 has a register bank composed of 23 locations. The register bank is implemented as a triple-port SRAM with one read port, A, one read port, B, and a third write port. The address for read port B and the write port are combined. This configuration yields one read port and a read/write port�a two-address device. In a single cycle, two locations, A and B, can be read and location B can be updated.
Scalar I/O Bus The extended registers are accessed via the 24-bit, bi-directional scalar I/O bus. Only the scalar processor 5 can use the I/O bus for transferring data. Although the scalar I/O bus is bi-directional, the scalar processor 5 can only read or only write in a single cycle. Therefore, in the presently preferred (but limiting) embodiment of this invention, it is not possible to perform read-modify-writes with an extended register as it is possible with the scalar registers. The data must instead be read, modified, and stored in a local register�and on a subsequent cycle, the result written back to the appropriate extended register. The scalar I/O bus is driven from the A-mux of the scalar processor 5.
Scalar memory addressing�Whenever the scalar processor 5 addresses the scalar memory it must execute the next instruction that modifies the addressed location.
Inter-processor communications�Whenever the Scalar Processor Broadcast (SPB) register in the vector processors 6A is addressed as a read or write, then the next vector instruction must execute.
Subroutine calls�The instruction unit 4 must complete a subroutine call and begin executing new instructions before additional subroutine calls or hardware interrupts or software interrupts can be executed.
Program jumps�Similar to subroutine calls, program jumps cannot be interrupted until execution begins at the new program location.
Returns (interrupt or subroutine)�A return from interrupt and a return from subroutine are identical, except for which stack is used to retrieve previously stored information. Each causes an interlock until program execution resumes.
The Page Status word for each page in the cache contains information vital to the correct functioning of the cache controller. The Tag Valid status bit is set if the status word is valid indicating that the appropriate cache page is valid. The Dirty status bit is set if the referenced page is dirty�different from the page in main memory. The LRU status bit is set if the referenced page has been used most recently and cleared if used least recently. The 15-bit address tag is matched against the memory address to determine if a page is present of not in the cache. The format of the page status word is:
4 � 16 b � 2 MB
4 � 32 � 1 MB
1 � 16 b � 8 MB
2 � 32 b � 8 MB
4 � 32 b � 1 MB
The DSP Chip 1 supports four different memory configurations. The memory configuration is set from host port pins 7 and 6 (HOST7 and HOST6) when the DSP chip 1 is reset. Two of the memory configurations allow interfacing to 16-bit SDRAMs and the other two are for interfacing with 32-bit SDRAMS. These four memory configurations are illustrated in FIG. 10-11. The default configuration is 4�16b�2 MB.
The interrupt identification register contains an identification code indicating the type of interrupt pending. The UART 9 prioritizes four interrupts and sets the interrupt identification register according to the highest priority received. The contents of the register are �frozen� to prevent additional interrupts from destroying the current status. The interrupts are prioritized according to the table below:
Bit 2: This bit is the parity error indicator. This bit is set by the UART 9 when the received character does not have a stop bit. Reading the contents of the line status register will clear the framing error indicator. If there is a framing error, then the UART 9 assumes that the Start bit to follow is also a Stop bit, therefore the Start bit is �read� twice in order to resynchronize data.
The UART 9 is capable of transmitting using a frequency derived from the CPU clock divided by the value stored in the 16-bit Divisor Latch. The Baud rate can be between CPU_frequency to CPU_frequency�216−1. When the divisor latch access bit is set, then the divisor latch can be accessed as the receiver buffer/transmitter holding buffer for bits 7 . . . 0 and the interrupt enable register for bits 15 . . . 8. Clearing the divisor latch access bit reverts the two aforementioned registers back to their normal state.
Citations de brevets Brevet cit� Date de d�p�t Date de publication D�posant TitreUS462263218 ao�t 198211 nov. 1986Board Of Regents, University Of WashingtonData processing system having a pyramidal array of processorsUS464135017 mai 19843 f�vr. 1987Bunn; Robert F.Fingerprint identification systemUS480711514 oct. 198721 f�vr. 1989Cornell Research Foundation, Inc.Instruction issuing mechanism for processors with multiple functional unitsUS484561013 mars 19874 juil. 1989Ford Aerospace & Communications CorporationTarget recognition using string-to-string matchingUS49929334 mai 199012 f�vr. 1991International Business Machines CorporationSIMD array processor with global instruction control and reprogrammable instruction decodersUS520300227 d�c. 198913 avr. 1993Wetzel; Glen F.System with a multiport memory and N processing units for concurrently/individually executing 2N-multi-instruction-words at first/second transitions of a single clock cycleUS531355111 f�vr. 199117 mai 1994North American Philips CorporationMultiport memory bypass under software controlUS535342629 avr. 19924 oct. 1994Sun Microsystems, Inc.Cache miss buffer adapted to satisfy read requests to portions of a cache fill in progress without waiting for the cache fill to completeUS54653738 janv. 19937 nov. 1995International Business Machines CorporationMethod and system for single cycle dispatch of multiple instructions in a superscalar processor systemUS550493110 mai 19952 avr. 1996Atmel CorporationMethod and apparatus for comparing data setsUS552208322 juin 199428 mai 1996Texas Instruments IncorporatedReconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processorsUS555542810 mars 199510 sept. 1996Hughes Aircraft CompanyActivity masking with mask context of SIMD processorsUS557493929 juin 199512 nov. 1996Massachusetts Institute Of TechnologyMultiprocessor coupling system with integrated compile and run time scheduling for parallelismUS565513313 nov. 19955 ao�t 1997The Dow Chemical CompanyMassively multiplexed superscalar Harvard architecture computerUS568059726 janv. 199521 oct. 1997International Business Machines CorporationSystem with flexible local control for modifying same instruction partially in different processor of a SIMD computer system to execute dissimilar sequences of instructionsUS568249129 d�c. 199428 oct. 1997International Business Machines CorporationSelective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifierUS569221018 nov. 199625 nov. 1997Canon Kabushiki KaishaImage processing apparatus having parallel processors for communicating and performing positional control over plural areas of image data in accordance with designated position instructionUS57272295 f�vr. 199610 mars 1998Motorola, Inc.Method and apparatus for moving data in a parallel processorUS575206830 d�c. 199612 mai 1998Massachusetts Institute Of TechnologyMesh parallel computer architecture apparatus and associated methodsUS57617267 juin 19952 juin 1998Texas Instruments IncorporatedBase address generation in a multi-processing system having plural memories with a unified address space corresponding to each processorUS57650377 juin 19959 juin 1998Biax CorporationSystem for executing instructions with delayed firing timesUS57782447 oct. 19967 juil. 1998Timeplex, Inc.Digital signal processing unit using digital signal processor array with recirculationUS589292630 d�c. 19966 avr. 1999Compaq Computer CorporationDirect media independent interface connection system for network devicesUS603864712 juin 199614 mars 2000Fujitsu LimitedCache memory device and method for providing concurrent independent multiple accesses to different subsets within the device R�f�renc� par Brevet citant Date de d�p�t Date de publication D�posant TitreUS660107731 mars 200029 juil. 2003Intel CorporationDSP unit for multi-level global accumulationUS670148411 ao�t 20002 mars 2004International Business Machines CorporationRegister file with delayed parity checkUS682010229 juil. 200316 nov. 2004Intel CorporationDSP unit for multi-level global accumulationUS685704628 mars 200215 f�vr. 2005Cisco Technology, Inc.Caching for context switching applicationsUS68656618 mai 20028 mars 2005Analog Devices, Inc.Reconfigurable single instruction multiple data arrayUS688305312 oct. 200119 avr. 2005Oki Electric Industry Co., Ltd.Data transfer control circuit with interrupt status registerUS691263828 juin 200228 juin 2005Zoran CorporationSystem-on-a-chip controllerUS69414465 mars 20026 sept. 2005Analog Devices, Inc.Single instruction multiple data array cellUS698323524 avr. 20013 janv. 2006Juniper Networks, Inc.Method and apparatus for implementing constant latency Z-domain transfer functions using processor elements of variable latencyUS700009030 mai 200214 f�vr. 2006Analog Devices, Inc.Center focused single instruction multiple data (SIMD) array systemUS702744618 juil. 200111 avr. 2006P-Cube Ltd.Method and apparatus for set intersection rule matchingUS705118114 janv. 200523 mai 2006Cisco Technology, Inc.Caching for context switching applicationsUS706938610 mai 200427 juin 2006Connex Technology, Inc.Associative memory deviceUS71074784 d�c. 200312 sept. 2006Connex Technology, Inc.Data processing system having a Cartesian ControllerUS71428829 mars 200128 nov. 2006Intellectual Ventures I LlcSingle chip wireless communication integrated circuitUS71876639 oct. 20016 mars 2007Schmidt Dominik JFlexible processing systemUS72635773 mars 200528 ao�t 2007Qualcomm IncorporatedPower saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor stateUS72930284 juin 20026 nov. 2007Sap AgCache-conscious concurrency control scheme for database systemsUS73834214 d�c. 20033 juin 2008Brightscale, Inc.Cellular engine for a data processing systemUS742156518 ao�t 20032 sept. 2008Cray Inc.Method and apparatus for indirectly addressed vector load-add -store across multi-processorsUS743752118 ao�t 200314 oct. 2008Cray Inc.Multistream processing memory-and barrier-synchronization method and apparatusUS749949123 juin 20043 mars 2009Vichip Corp. LimitedApparatus for adaptive multiple-dimentional signal sequences encoding/decodingUS751264722 nov. 200431 mars 2009Analog Devices, Inc.Condensed Galois field computing systemUS751977118 ao�t 200314 avr. 2009Cray Inc.System and method for processing memory instructions using a forced order queueUS752274814 ao�t 200321 avr. 2009Sony CorporationMethod and apparatus for processing image data and semiconductor storage deviceUS752626715 sept. 200628 avr. 2009Gallitzin Allegheny LlcSingle chip wireless communication integrated circuitUS754313318 ao�t 20032 juin 2009Cray Inc.Latency tolerant distributed shared memory multiprocessor computerUS757781618 ao�t 200318 ao�t 2009Cray Inc.Remote translation mechanism for a multinode systemUS762774410 mai 20071 d�c. 2009Nvidia CorporationExternal memory accessing DMA request scheduling in IC of parallel processing engines according to completion notification queue occupancy levelUS76502663 f�vr. 200619 janv. 2010Nvidia CorporationMethod of simulating deformable object using geometrically motivated modelUS773947919 nov. 200315 juin 2010Nvidia CorporationMethod for providing physics simulation dataUS774322318 ao�t 200322 juin 2010Cray Inc.Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor systemUS775749719 janv. 200920 juil. 2010Cray Inc.Method and apparatus for cooling electronic componentsUS779307329 juin 20077 sept. 2010Cray Inc.Method and apparatus for indirectly addressed vector load-add-store across multi-processorsUS789538116 f�vr. 200922 f�vr. 2011Himax Media Solutions, Inc.Data accessing systemUS789541119 nov. 200322 f�vr. 2011Nvidia CorporationPhysics processing unitUS790846119 d�c. 200715 mars 2011Allsearch Semi, LLCCellular engine for a data processing systemUS79248783 ao�t 200612 avr. 2011Intellectual Ventures I LlcFlexible processing systemUS806452627 avr. 200622 nov. 2011Broadcom CorporationSystems, methods, and apparatus for real-time encodingUS80692706 sept. 200529 nov. 2011Cisco Technology, Inc.Accelerated tape backup restorationUS809092828 juin 20023 janv. 2012Intellectual Ventures I LlcMethods and apparatus for processing scalar and vector instructionsUS810865210 sept. 200831 janv. 2012Hui Ronald Chi-ChunVector processing with high execution throughputUS81317886 ao�t 20076 mars 2012Xilinx, Inc.Determining sum of absolute differences in parallelUS826643131 oct. 200511 sept. 2012Cisco Technology, Inc.Method and apparatus for performing encryption of data at rest at a port of a network deviceUS830719418 ao�t 20036 nov. 2012Cray Inc.Relaxed memory consistency modelUS2010015365430 sept. 200917 juin 2010Vorbach MartinData processing method and deviceCN100409221C5 d�c. 20036 ao�t 2008Standard ltd liangData processing system having a Cartesian controller, and method for processing dataCN100440193C5 d�c. 20033 d�c. 2008Standard ltd liangCellular engine for a data processing systemEP1570371A15 d�c. 20037 sept. 2005Connex Technology, Inc.Data processing system having a cartesian controllerWO2004053718A15 d�c. 200324 juin 2004Gemicer, Inc.Cellular engine for a data processing systemWO2005111831A220 sept. 200424 nov. 2005Ageia Technologies, Inc.Physics processing unit instruction set architectureWO2006031425A229 ao�t 200523 mars 2006Alshareef, HusamCmos device having different nitrogen amounts in nmos and pmos gate dielectric layersWO2006094197A23 mars 20068 sept. 2006Bridges, Jeffrey ToddPower saving methods and apparatus to selectively enable comparators in a cam renaming register file based on known processor stateWO2011146337A113 mai 201124 nov. 2011Cognex CorporationSystem and method for processing image data relative to a focus of attention within the overall imageWO2012100316A125 janv. 20112 ao�t 2012Cognivue CorporationApparatus and method of vector unit sharingFaire pivoterImage d'origineAccueil Google - Plan du site - T�l�chargements par lot sur l'USPTO - R�gles de confidentialit� - Conditions d'utilisation - � propos de Google�Brevets - Envoyer des commentairesDonn�es fournies par IFI CLAIMS Patent Services©2012 Google