Source: http://www.google.com/patents/US20050052208?dq=5631832
Timestamp: 2016-10-01 12:19:31
Document Index: 620941155

Matched Legal Cases: ['in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine', 'in fine']

Patent US20050052208 - Dual-gain loop circuitry for programmable logic device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA loop circuit (PLL or DLL) uses a dual-gain voltage-controlled component (VCO or VCDL) to achieve a phase (and frequency) lock with reduced jitter. A coarse control feedback path includes a detector for achieving an approximate lock. This path operates over a wide range and therefore feeds a VCO or...http://www.google.com/patents/US20050052208?utm_source=gb-gplus-sharePatent US20050052208 - Dual-gain loop circuitry for programmable logic deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20050052208 A1Publication typeApplicationApplication numberUS 10/655,853Publication dateMar 10, 2005Filing dateSep 5, 2003Priority dateSep 5, 2003Also published asCN1595806A, US7019570Publication number10655853, 655853, US 2005/0052208 A1, US 2005/052208 A1, US 20050052208 A1, US 20050052208A1, US 2005052208 A1, US 2005052208A1, US-A1-20050052208, US-A1-2005052208, US2005/0052208A1, US2005/052208A1, US20050052208 A1, US20050052208A1, US2005052208 A1, US2005052208A1InventorsGregory StarrOriginal AssigneeAltera Corporation, A Corporation Of DelawareExport CitationBiBTeX, EndNote, RefManPatent Citations (76), Referenced by (14), Classifications (24), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetDual-gain loop circuitry for programmable logic device
US 20050052208 A1Abstract
A loop circuit (PLL or DLL) uses a dual-gain voltage-controlled component (VCO or VCDL) to achieve a phase (and frequency) lock with reduced jitter. A coarse control feedback path includes a detector for achieving an approximate lock. This path operates over a wide range and therefore feeds a VCO or VCDL input with relatively high gain. However, input on that path is fixed once coarse frequency lock is achieved, so it does not contribute to jitter. A fine control path includes a detector whose output fine tunes the lock. Although this path is susceptible to noise, its operating range is relatively small, so its VCO or VCDL input has relatively low gain. Therefore jitter from magnification of noise by that gain is relatively small. The loop circuit can be used in a programmable logic device, in which case various loop parameters may be determined by programmable values. Images(8) Claims(41)
1. A loop circuit having an input terminal for receiving a reference signal and an output terminal for outputting an output signal locked to said reference signal, and comprising: a compensation component for producing said output signal; a high-gain coarse feedback path feeding said compensation component, said high-gain coarse feedback path accepting as inputs said reference signal and said output signal, and causing said compensation component to drive said output signal to within a predetermined variance from said reference signal; and a low-gain fine feedback path feeding said compensation component, said low-gain fine feedback path accepting as inputs said reference signal and said output signal, and causing said compensation component to drive said output to a lock with said reference signal after said coarse feedback path has caused said compensation component to drive said output signal to within said predetermined variance from said reference signal. 2. The loop circuit of claim 1 wherein: said loop circuit is a phase-locked loop; said compensation component comprises an oscillator for producing an output frequency; said reference signal is a reference frequency signal; said output signal has said output frequency and an output phase; said high-gain coarse feedback path accepts as inputs said reference frequency and said output frequency, and causes said oscillator to drive said output frequency to within said predetermined variance from said reference frequency; and said low-gain fine feedback path accepts as inputs said reference frequency and said output frequency, and causes said oscillator to drive said output to a phase-frequency lock with said reference frequency after said coarse feedback path has caused said oscillator to drive said output frequency to within said predetermined variance from said reference frequency. 3. The loop circuit of claim 2 wherein: said coarse feedback path comprises: a frequency detector having inputs connected to said input terminal and said output terminal, said frequency detector producing a coarse-adjust signal based on difference between said output frequency and said reference frequency, and a high-gain signal modifier downstream of said frequency detector; and said fine feedback path comprises: a phase-frequency detector having inputs connected to said input terminal and said output terminal, said phase-frequency detector producing a fine-adjust signal based on difference between said output frequency and said reference frequency, and a low-gain signal modifier downstream of said phase-frequency detector. 4. The loop circuit of claim 3 wherein: said oscillator is a current-controlled oscillator; said low-gain signal modifier is a voltage-to-current converter having a first gain; and said high-gain signal modifier is a voltage-to-current converter having a second gain greater than said first gain. 5. The loop circuit of claim 4 wherein said second gain is twenty times said first gain. 6. The loop circuit of claim 3 wherein: each of said high-gain signal modifier and said low-gain signal modifier has a respective gain; and said gain of said high-gain signal modifier is ten times said gain of said low-gain signal modifier. 7. The loop circuit of claim 3 further comprising a control circuit adapted to disable said fine feedback path until said coarse feedback path is locked and to enable said fine feedback path after said coarse feedback path is locked. 8. The loop circuit of claim 3 wherein said frequency detector is programmable for user adjustment of said predetermined variance. 9. The loop circuit of claim 8 wherein said frequency detector comprises: a reference counter clocked by said reference frequency; a feedback counter clocked by said output frequency; at least one programmable register programmably storing a respective counter value; a reference comparator that compares said reference counter to said respective counter value; a feedback comparator that compares said feedback counter to said respective counter value; and combining circuitry that (a) when said reference counter reaches said respective counter value before said feedback counter, generates a control signal to increase said output frequency, and (b) when said feedback counter reaches said respective counter value before said reference counter, generates a control signal to decrease said output frequency. 10. The loop circuit of claim 9 wherein: said at least one programmable register consists of one programmable register; and said reference comparator and said feedback comparator respectively compare said reference counter and said feedback counter to a single counter value in said one programmable register. 11. The loop circuit of claim 9 wherein: said at least one programmable register comprises two programmable registers, a first one of which corresponds to said reference counter and a second one of which corresponds to said feedback counter; and said reference comparator and said feedback comparator respectively compare said reference counter and said feedback counter to respective counter values in said first and second programmable registers. 12. The loop circuit of claim 11 wherein said respective counter values in said first and second programmable registers are equal to one another. 13. The loop circuit of claim 11 wherein said respective counter values in said first and second programmable registers are different from one another. 14. The loop circuit of claim 9 wherein said combining circuitry comprises: a detector having as inputs outputs of said reference comparator and said feedback comparator, said detector producing a latch signal when either of (a) said reference comparator, and (b) said feedback comparator, produces an output indicative of one of said reference counter and said feedback counter reaching its respective counter value stored in said at least one register; a reference latch and a feedback latch that respectively latch values in said reference counter and said feedback counter when said detector produces said latch signal; and a subtractor that subtracts the value in said feedback latch from the value in said reference latch. 15. The loop circuit of claim 14 wherein said detector comprises an OR gate. 16. The loop circuit of claim 14 wherein said combining circuitry further comprises: a programmable offset generator that generates an offset signal; and an adder for combining said offset signal with said control signal. 17. The loop circuit of claim 3 wherein said coarse feedback path further comprises a digital-to-analog converter between said frequency detector and said high-gain signal modifier. 18. The loop circuit of claim 3 wherein said fine feedback path further comprises a charge pump and loop filter between said phase-frequency detector and said low-gain signal modifier. 19. The loop circuit of claim 2 further comprising an output scaling counter downstream of said output terminal. 20. The loop circuit of claim 2 further comprising an input scaling counter upstream of said input terminal. 21. The loop circuit of claim 2 further comprising a feedback scaling counter between said output terminal and each said feedback path. 22. The loop circuit of claim 1 wherein: said loop circuit is a delay-locked loop; said compensation component comprises a controlled delay line for producing a phase-delayed output signal; said reference signal has an input phase; said output signal has an output phase; said high-gain coarse feedback path accepts as inputs said reference signal and said output signal, and causes said controlled delay line to drive said output phase to within said predetermined variance from said input phase; and said low-gain fine feedback path accepts as inputs said reference frequency and said output frequency, and causes said controlled delay line to drive said output to a phase lock with said reference input signal after said coarse feedback path has caused said controlled delay line to drive said output phase to within said predetermined variance from said input phase. 23. The loop circuit of claim 22 wherein: said coarse feedback path comprises: a first phase detector having inputs connected to said input terminal and said output terminal, said first phase detector producing a coarse-adjust signal based on difference between said output phase and said input phase, and a high-gain signal modifier downstream of said phase detector; and said fine feedback path comprises: a second phase detector having inputs connected to said input terminal and said output terminal, said second phase detector producing a fine-adjust signal based on difference between said output phase and said input phase, and a low-gain signal modifier downstream of said second phase detector. 24. The loop circuit of claim 23 wherein: said controlled delay line is a current-controlled delay line; said low-gain signal modifier is a voltage-to-current converter having a first gain; and said high-gain signal modifier is a voltage-to-current converter having a second gain greater than said first gain. 25. The loop circuit of claim 24 wherein said second gain is twenty times said first gain. 26. The loop circuit of claim 23 wherein: each of said high-gain signal modifier and said low-gain signal modifier has a respective gain; and said gain of said high-gain signal modifier is ten times said gain of said low-gain signal modifier. 27. The loop circuit of claim 23 further comprising a control circuit adapted to disable said fine feedback path until said coarse feedback path is locked and to enable said fine feedback path after said coarse feedback path is locked. 28. The loop circuit of claim 23 wherein said phase detector is programmable for user adjustment of said predetermined variance. 29. The loop circuit of claim 23 wherein said coarse feedback path further comprises a digital-to-analog converter between said phase detector and said high-gain signal modifier. 30. The loop circuit of claim 23 wherein said fine feedback path further comprises a charge pump and loop filter between said phase detector and said low-gain signal modifier. 31. The loop circuit of claim 1 wherein said predetermined variance is programmable. 32. A programmable logic device comprising the loop circuit of claim 1. 33. A digital processing system comprising: processing circuitry; a memory coupled to said processing circuitry; and a programmable logic device as defined in claim 32 coupled to the processing circuitry and the memory. 34. A printed circuit board on which is mounted a programmable logic device as defined in claim 32. 35. The printed circuit board defined in claim 34 further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable logic device. 36. The printed circuit board defined in claim 35 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry. 37. An integrated circuit device comprising the loop circuit of claim 1. 38. A digital processing system comprising: processing circuitry; a memory coupled to said processing circuitry; and an integrated circuit device as defined in claim 37 coupled to the processing circuitry and the memory. 39. A printed circuit board on which is mounted an integrated circuit device as defined in claim 37. 40. The printed circuit board defined in claim 39 further comprising: memory circuitry mounted on the printed circuit board and coupled to the integrated circuit device. 41. The printed circuit board defined in claim 40 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry. Description
BACKGROUND OF THE INVENTION [0001] This invention relates to dual-gain phase-locked loop circuitry and delay-locked loop circuitry with reduced jitter, and particularly to such circuitry for use in a programmable logic device. [0002] It is known to incorporate phase-locked loop (“PLL”) circuitry or delay-locked loop (“DLL”) circuitry on programmable logic devices (“PLDs”). For example, it has become common for PLDs to accommodate various input/output standards, some of which require very accurate high-speed clocks. One way of providing such clocks is to provide PLL or DLL circuitry on the PLD. For convenience, PLLs and DLLs will be referred to collectively herein as “loop circuits” where appropriate. [0003] A basic PLL includes a phase-frequency detector (“PFD”), a charge pump, a loop filter and a voltage-controlled oscillator (“VCO”), connected in series. The input or reference frequency is one input to the PFD. The output of the VCO, which is the output of the PLL, is also fed back to another input of the PFD. If the feedback signal is not locked to the input reference signal, then the PFD output will be a signal (voltage) whose sign is indicative of whether the output leads or lags and whose magnitude is indicative of the amount of lead or lag. That signal is filtered by the charge pump and loop filter and is input to the VCO, causing the output frequency to change. Eventually, the output signal will lock to the phase of the input reference signal. In this simple example, the output signal also will lock to the frequency of the input reference signal, but in most PLLs, counters on the input and output of the PLL are used to divide the input frequency, while a counter/divider in the feedback loop is used to multiply the input frequency. Thus the frequency of the output signal can be any rational multiple of the input frequency, but will be phase-locked to the input frequency. [0004] However, the VCO typically has a substantial voltage gain, which can be correlated to the frequency range over which it is to operate. As a result, slight variations in the input and feedback signals, resulting from process, temperature and supply variations or other sources of noise, can be greatly magnified by the PLL, resulting in an output signal variation known as “jitter.”
[0005] For example, for a PLL constructed using 90 nm integrated circuit technology, for which the minimum expected frequency is fmin=300 MHz, the maximum expected frequency is fmax=1000 MHz, the supply voltage is VCC=1.2 V, and the device saturation voltage is VDSseat=0.2 V, the VCO gain, KVCO, can be estimated as K VCO = ( f max - f min ) / ( V cc - 2 V DSsat ) = ( 1000 - 300 ) / ( 1.2 - 0.4 ) = 875 MHz / V . Thus, even a 1 mV variation in the input signal can give rise to an output frequency variation of almost 1 MHz. Insofar as the voltages involved are almost always in generally the same range, the gain is effectively a function of the desired operating range, which is determined by the particular application. [0011] The situation is similar for a DLL. A basic DLL includes a phase detector (“PD”), a charge pump, a loop filter and a voltage-controlled delay line (“VCDL”), connected in series. The input or reference signal is one input to the PD. An output of the VCDL is also fed back to another input of the PD. If the phase of the feedback signal is not locked to that of the input reference signal, then the PD output will be a signal (voltage) whose sign is indicative of whether the output leads or lags and whose magnitude is indicative of the amount of lead or lag. That signal is filtered by the charge pump and loop filter and is input to the VCDL, delaying the output and causing its phase to change. Eventually, the output signal will lock to the phase of the input reference signal. Unlike PLLs, DLLs do not affect the frequency of the signal; the output frequency will automatically match the input frequency. [0012] However, like a VCO, a VCDL may have a substantial voltage gain. Thus, as with a PLL, slight variations in the input and feedback signals, resulting from process, temperature and supply variations or other sources of noise, can be greatly magnified by the DLL, resulting in output signal jitter. [0013] It would be desirable to be able to reduce the jitter of a loop circuit without regard to its operating range. It would be particularly desirable to be able to control the jitter in a programmable way. SUMMARY OF THE INVENTION [0014] The present invention allows loop filter jitter to be reduced by providing in the loop filter a voltage-controlled compensation component—i.e., a voltage-controlled oscillator in a PLL OR a voltage-controlled delay line in a DLL—having a low-gain input and a high-gain input, and two separate feedback paths, one of which feeds the high-gain input and one of which feeds the low-gain input. [0015] A high-gain coarse feedback path preferably includes in the PLL case a frequency detector (“FD”) and in the DLL case a phase detector (“PD”), as well as a digital-to-analog converter (“DAC”) to provide a voltage for input to the high-gain input of the compensation component. In the case of a PLL, the voltage is used to coarsely lock the VCO onto the correct frequency (without providing a phase lock, except possibly by chance). The degree of coarseness of the frequency lock preferably is programmably adjustable. In the case of a DLL, the voltage is used to coarsely lock the VCDL to the correct phase (frequency not being an issue in a DLL). Again, the degree of coarseness of the phase lock preferably is programmably adjustable. [0016] Once coarse lock is achieved, the high-gain input preferably is fixed and a low-gain fine feedback path preferably is enabled. The low-gain fine feedback path preferably includes, in the PLL case a phase-frequency detector (“PFD”), and in the DLL case a second PD, as well as a charge pump and a loop filter as are commonly provided in loop circuits, to provide fine adjustment of the output frequency in the case of a PLL, as well as phase adjustment in either a PLL or a DLL. However, the compensation component input which the low-gain fine feedback path feeds preferably has a significantly lower gain than the input fed by the coarse feedback path. Therefore, for the same variation in the feedback signal (e.g., if there is a device-wide supply variation), the effect of the low-gain fine feedback path on the output phase (and frequency in the case of a PLL) is much less than the effect of the high-gain coarse feedback path on the output frequency in the case of a PLL or the output phase in the case of a DLL, and by the same token much less than the effect would be on the output phase (and frequency) in a conventional loop circuit. Moreover, the filtering characteristics of the charge pump and loop filter can be selected to better deal with the types of variations expected in the fine-feedback path. For example, the charge pump current can be made much smaller than the charge pump current in a conventional loop circuit. [0017] The dual-gain VCO or VCDL can be constructed from a current-controlled oscillator (“CCO”) or current-controlled delay line (“CCDL”) with two different voltage-to-current converters (“V/Is”), with higher and lower gains, respectively, for the high-gain and low-gain signal paths. The gains of the two V/Is may be fixed, but preferably at least one is controllable or programmable as described in more detail below. [0018] In accordance with this invention, there is provided a loop circuit having an input terminal for receiving a reference signal and an output terminal for outputting an output signal locked to the reference signal. The loop circuit includes a compensation component for producing said output signal. A high-gain coarse feedback path feeds the compensation component, accepting as inputs the reference signal and the output signal, and causing the compensation component to drive the output signal to within a predetermined variance from the reference signal. A low-gain fine feedback path also feeds the compensation component, accepting as inputs the reference signal and the output signal, and causing the compensation component to drive the output to a lock with the reference signal after the coarse feedback path has caused the compensation component to drive the output signal to within the predetermined variance from the reference signal. [0019] The loop circuit may be a phase-locked loop, in which case the compensation component includes an oscillator for producing an output frequency, the reference signal is a reference frequency signal, and the output signal has the output frequency and an output phase. The high-gain coarse feedback path accepts as inputs the reference frequency and the output frequency, and causes the oscillator to drive the output frequency to within a predetermined variance from the reference frequency. The low-gain fine feedback path accepts as inputs the reference frequency and the output frequency, and causes the oscillator to drive the output to a phase-frequency lock with the reference frequency after the coarse feedback path has caused the oscillator to drive the output frequency to within the predetermined variance from the reference frequency. [0020] The loop circuit also may be a delay-locked loop, in which case the compensation component includes controlled delay line for producing a phase-delayed output signal. The reference signal has an input phase and the output signal has an output phase. The high-gain coarse feedback path accepts as inputs the reference signal and the output signal, and causes the controlled delay line to drive the output phase to within the predetermined variance from the input phase. The low-gain fine feedback path accepts as inputs the reference frequency and the output frequency, and causes the controlled delay line to drive the output to a phase lock with the reference input signal after the coarse feedback path has caused the controlled delay line to drive the output phase to within the predetermined variance from the input phase.
BRIEF DESCRIPTION OF THE DRAWINGS [0021] The above and other advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: [0022] FIG. 1 is a block diagram of a preferred embodiment of a phase-locked loop circuit according to the present invention; [0023] FIG. 2 is a block diagram of a preferred embodiment of the dual-gain voltage controlled oscillator shown in FIG. 1; [0024] FIG. 3 is a schematic diagram of a preferred embodiment of a portion of the dual-gain voltage controlled oscillator shown in FIGS. 1 and 2; [0025] FIG. 4 is a schematic diagram of a portion of a preferred embodiment of a scalable version of a voltage-to-current converter of the type shown in FIG. 3; [0026] FIG. 5 is a block diagram of a preferred embodiment of the frequency detector of FIG. 1; [0027] FIG. 6 is a plot showing an example of the variation of the voltage in the high-gain feedback path as a function of time; [0028] FIG. 7 is a schematic diagram showing a portion of a preferred embodiment of the control circuitry of the phase-locked loop circuit of FIG. 1; [0029] FIG. 8 is a block diagram of a preferred embodiment of a delay-locked loop circuit according to the present invention; [0030] FIG. 9 is a block diagram of a preferred embodiment of the dual-gain voltage controlled delay line shown in FIG. 8; [0031] FIG. 10 is a plot showing a preferred embodiment of a determination of coarse phase lock according to the invention; and [0032] FIG. 11 is a simplified block diagram of an illustrative system employing a programmable logic device incorporating a phase-locked loop in accordance with the present invention.
DETAILED DESCRIPTION OF THE INVENTION [0033] As described above, the present invention reduces loop circuit jitter, without decreasing the allowable range of input voltages, by providing two separate feedback paths. A first feedback path provides coarse feedback to set the approximate output frequency of in the case of a PLL, or the approximate output phase in the case of a DLL. Although this path operates at a relatively high gain, its input voltage, and therefore its output frequency or phase component, is fixed once it brings the output frequency or phase within a desired range of the input frequency or phase. Thereafter, the contribution of the high-gain feedback path is constant, regardless of signal fluctuations in the feedback path. A second feedback path provides fine feedback to lock the precise output phase, as well as frequency in the case of a PLL. However, this path operates at a relatively low gain, so that signal noise (e.g., a power supply variation) will not cause a large phase or frequency variation in the loop circuit output. Despite the lower gain of this fine feedback path, the loop circuit of the invention, as a whole, retains a wide operating range as a result of the inclusion as well of the aforementioned coarse feedback path. As stated above, the component contributed by the coarse feedback path becomes fixed before the loop circuit is locked, so that notwithstanding the high gain of the coarse feedback path, voltage variations in the coarse feedback path are not multiplied by the high gain of that path to distort the loop circuit output. [0034] The invention will now be described with reference to FIGS. 1-10. [0035] FIG. 1 shows the basic layout of a preferred embodiment of a PLL 10 in accordance with the invention. In PLL 10, the standard voltage-controlled oscillator of known PLLs is replaced by a dual-gain VCO 11 which provides a basic output signal at node 12 as a function of both a control voltage 13 on a high-gain input 130 and a control voltage 14 on a low-gain input 140. The basic output signal at 12 is fed back on feedback path 15, which splits into a high-gain coarse feedback path 150 producing control voltage 13, and a low-gain fine feedback path 151 producing control voltage 14. [0036] Coarse feedback path 150 preferably includes a frequency detector 152 (described in more detail below) in series with a digital-to-analog converter (which may be conventional). The feedback signal on path 150 preferably is compared to the input signal at node 16 by frequency detector 152, preferably in the manner described below, to provide a signal (preferably digital) representative of how much and in which direction the output frequency must change. That signal preferably is converted back to analog form by DAC 153 for provision as the high-gain control voltage VCTRL — HG 13 to high-gain input 130 of dual-gain VCO 11. [0037] Preferably, as explained in more detail below, as long as the frequency of the basic output signal at 12 varies by more than a predetermined variance from the desired frequency, control 17 holds low-gain control voltage VCTRL — LG 14 constant and allows the output of frequency detector 152 to vary, driving the basic output signal frequency closer to the desired frequency. Once the basic output signal frequency approaches to within that predetermined variance from the desired frequency, control 17 preferably causes high-gain control voltage VCTRL — HG 13 to be locked or fixed at its then-current value by stopping updating of the output of frequency detector 152 so that DAC 153 receives a constant input. Control 17 then turns on low-gain fine feedback path 151. [0038] Fine feedback path 151 preferably is similar to a conventional PLL, having a phase-frequency detector 154, a charge pump 155 and a loop filter 156, providing low-gain control voltage VCTRL — LG 14 as a function of the phase-frequency comparison of the feedback signal to the input signal at 16. Low-gain control voltage VCTRL — LG 14 provides “fine-tuning” of the coarse frequency lock based on high-gain control voltage VCTRL — HG 13, and also provides phase-lock, in the same manner as in a conventional PLL. [0039] Up to now, the discussion has referred to the “basic output signal” at node 12 and the “input signal” at node 16, and has assumed that the feedback signal on path 15 is unchanged when it reaches frequency detector 152 or phase-frequency detector 154. Such a discussion could describe only a PLL that provides a phase-locked output signal with a frequency identical to its input signal. However, while such a PLL has its uses, a major advantage of PLLs is their ability to provide an output signal that is phase-locked to the input signal, but has a different frequency, and that is the reason that counters 180, 181 and 182 are provided. [0040] Counters 180, 181 and 182 preferably serve as integer dividers of the frequencies of the respective signals passing through them. Thus, the frequency of “input signal” 16 is that of user input signal 160 divided by the value, N, stored in input scale counter 180. Similarly, the frequency of user output signal 120 is equal to that of basic output signal 12 divided by the value, K, stored in output scale counter 181. The effect of the value, M, stored in feedback scale counter 182 is to divide by M the frequency of the basic output signal 12 before it is compared to input signal 16 in either frequency detector 152 or phase-frequency detector 154, which has the effect of multiplying the output signal by M. The final result is that the frequency, fout, of user output signal 120 bears the following relationship to the frequency fin, of user input signal 160: f out =f in �M/(NK). Because they derive from counters, the values of M, N and K normally are integers, and preferably are programmable by the user, so that the user can create an output frequency as any desired rational multiple of the input frequency (within the limits of the values of M, N and K that may be entered into the counters). [0042] As explained above, VCO 11 is a dual-gain VCO, having a high-gain input 130 and a low-gain input 140. A preferred embodiment of VCO 11 is shown in FIG. 2, and includes a current-controlled oscillator 20, two voltage-to-current converters 21 and 22, and an adder 23 to add the two currents output by converters 21, 22. Converter 21 is designated the high-gain voltage-to-current converter (V/I)HG, while converter 22 is designated the low-gain voltage-to-current converter (V/I)LG. However, the “high” and “low” designations are relative, and are functions of the expected frequency range, as discussed above. For example, in the case discussed above where the expected frequency range is 300 MHZ to 1000 MHz, it may be that (V/I)HG=2, while the range of fine tuning required in the low-gain feedback path is in the range of 100 MHz to 300 MHz, so that (V/I)LG=0.1. In such an example, the sensitivity of PLL 10 to noise in the low-gain feedback path is 5% of the sensitivity in the high-gain feedback path, with the sensitivity in the high-gain feedback path being comparable to that of a conventional PLL. [0043] One possible implementation of voltage-to-current converters 21, 22 and adder 23 is shown in FIG. 3. In this implementation, in voltage-to-current converter 22 low-gain control voltage 14 is applied to the gate of a NMOS transistor 30 whose source-drain path is connected between ground and a PMOS cascoded current mirror 31 formed by PMOS transistors 32, 33, 320, 330. The current ILG developed in transistor 30 may be given as follows: I LG =K 30(V CTRL — LG −V T30), where VT30 is the threshold voltage of transistor 30 and K30 is a constant for transistor 30 determined as follows: K 30=(μ0 C ox/2)(W/L), where μ0 and Cox are process-determined constants for the semiconductor on which transistor 30 is formed, and W and L are dimensions of transistor 30. [0046] The output current 310 of current mirror 31 has a magnitude AILG. The coefficient A may be considered the gain of voltage-to-current converter 22, and preferably is made relatively low as discussed above. [0047] Similarly, in voltage-to-current converter 21 high-gain control voltage 13 is applied to the gate of a NMOS transistor 34 whose source-drain path is connected between ground and a PMOS cascoded current mirror 35 formed by PMOS transistors 36, 37, 360, 370. The current IHG developed in transistor 34 may be given as follows: I HG =K 34(V CTRL — HG −V T34)2, where VT34 is the threshold voltage of transistor 34 and K34 is a constant for transistor 34 determined in a manner similar to K30 above. [0049] The output current 350 of current mirror 35 has a magnitude BIHG, where B is a coefficient determined by the relative sizes of transistors 36, 37, 360, 370. The coefficient B may be considered the gain of voltage-to-current converter 21, and is made relatively high as discussed above. [0050] Finally, in the implementation of FIG. 3, adder 23 is simply an NMOS cascoded current mirror formed by NMOS transistors 38, 39, 380, 390, adding currents 310 and 350 to provide current 230 to CCO 20. [0051] FIG. 3A shows an alternate embodiment of a current mirror circuit 300 that can be used in place of current mirrors 31 and 35 of FIG. 3. In circuit 300, PMOS transistors 301-304 are arranged as a modified Wilson mirror in which transistors 301, 302, 303, 304 take the places, respectively, of transistor 32 or 36, transistor 320 or 360, transistor 33 or 37, and transistor 330 or 370. Moreover, if NMOS transistors are substituted for PMOS transistors 301-304, the resulting NMOS modified Wilson mirror can be used in place of NMOS current mirror 23. [0052] Another alternate embodiment of a current mirror circuit 305, which is particularly effective in cases of low voltage headroom, is shown in FIG. 3B. The PMOS variant shown in FIG. 3B can be substituted for current mirrors 31, 35, while the NMOS variant (not shown) can be substituted for current mirror 23. In this embodiment, the input voltage 308 is applied to both transistors 306 and 307, while the output is available at terminal 309. [0053] While the coefficients A and B in FIG. 3 are controllable in the sense that the transistor dimensions that determine them can be selected during circuit design, FIG. 4 shows a circuit arrangement 40 that can be used in place of either converter 21 or 22 to provide user-controllable scaling of the output current(s). Although circuit arrangement 40 is based on the embodiment of FIG. 3, similar arrangements can be based on the embodiments of FIGS. 3A and 3B. [0054] In circuit arrangement 40, input 41 is comparable to inputs 13, 14, transistor 42 is comparable to transistors 30, 34, and transistors 43, 430 are comparable to transistors 32, 320 or 36, 360. However, instead of a single output transistor pair 33/330 or 37/370, in arrangement 40 there are n output transistor pairs 44A/440A, 44B/440B, 44C/440C, . . . , 44 n/440 n arranged in parallel. Each of transistor pairs 44A/440A, 44B/440B, 44C/440C, . . . , 44 n/440 n can be turned on or off by respective enable signal ENA, ENB, ENC, . . . , ENn. In a programmable logic device, for example, each of these enable signals can be programmed by a respective configuration bit. The greater the number of transistor pairs 44A/440A, 44B/440B, 44C/440C, . . . , 44 n/440 n that are turned on, the higher the output current at 45 will be. [0055] FIG. 5 shows a preferred embodiment of frequency detector 152 of FIG. 1. Reference input signal 16 is input to a reference counter 50, while feedback signal 15′ (signal 15 after division by M) is input to a feedback counter 51. Comparators 52, 53 compare the values in counters 50, 51, respectively, to values stored in reference compare (COMPAREREF) register 54 and feedback compare (COMPAREFB) register 55. When the value in either reference counter 50 or feedback counter 51 exceeds the respective value in COMPAREREF register 54 or COMPAREFB register 55, as determined by comparator 52 or 53, OR gate 56 causes the respective values in counters 50, 51 to be registered in registers 57, 58, and then to be reset to zero. As counters 50, 51 begin counting again, the value in register 58 is subtracted from the value in register 57 by subtractor 59. [0056] Normally, the values in COMPAREREF register 54 and COMPAREFB register 55 would be made equal. It can then be seen that if the value in register 57 exceeds the value in register 58, then reference counter 50 reached the reference comparison value first, meaning that the feedback frequency is too low. Therefore, the positive difference between the value in register 57 and the value in register 58 yields a positive control signal 500, signaling an increase in the output frequency. On the other hand, if the value in register 58 exceeds the value in register 59, then reference counter 51 reached the reference comparison value first, meaning that the feedback frequency is too high. Therefore, the negative difference between the value in register 57 and the value in register 58 yields a negative control signal 500, signaling a decrease in the output frequency. [0057] An optional offset signal 501 may be added to signal 500 in accumulator 502. Signal 501 can be used to start VCO 11 at a frequency near the desired frequency, so that high-gain coarse frequency path 150 can achieve frequency lock faster. [0058] The values in COMPAREREF register 54 and COMPAREFB register 55, as well as offset register 501, are selectable by the user according to the requirements of the user application. In the case where PLL 10 is being used in a programmable logic device, those registers preferably are among the programmable elements of the device. [0059] As stated above, normally, the values in COMPAREREF register 54 and COMPAREFB register 55 will be the same. However, in certain applications, they may differ. For example, it may be possible to eliminate feedback scale counter 182 and achieve the same result by setting the value in COMPAREFB register 55 to M times the value in COMPAREREF register 54. [0060] FIG. 6 shows the high-gain control voltage 13 resulting from operation of frequency detector 152 as depicted in FIG. 5. The initial value V0 is determined by the offset 501; otherwise the initial value would be the minimum output voltage that DAC 153 is capable of outputting. The voltage steps up in steps 60-65, each of duration T (this is just an example—in another case the voltage could step down instead of up, and/or the number of steps might be different). The value of T is a function of the values in COMPAREREF register 54 and COMPAREFB register 55. While those values may be the same or different, in either case they can be relatively large or relatively small. The larger the values, the longer the duration T of each of steps 60-65, representing a longer sampling period until the required number of clock cycles has been counted. The result would be a more accurate sampling, at the expense of taking longer to achieve a frequency lock. [0061] Final “step” 65 represents a frequency lock condition. This condition may be indicated when the absolute value of the difference computed by subtractor 59 is smaller than a predetermined value. In a preferred embodiment, that predetermined value is 1—i.e., the difference computed by subtractor 59 is −1, 0 or +1. [0062] When a frequency lock condition is thus indicated, the control signal 500, represented by the value in accumulator 502, may be locked by effectively turning off frequency detector 152 so that accumulator 502 is no longer updated. For example, in one embodiment frequency lock may be detected using absolute value comparator 503 to compare the absolute value of control signal 500, representing the difference, to a tolerance value stored at 504, which may be fixed or programmable. If the absolute value of the difference is less than the tolerance value, then signal 505 is set to disable accumulator 502 so that its accumulated value, which is output to DAC 153, no longer increases, but remains constant. Signal 505 (by connections not shown) also causes the other components of FD 152 to be turned off, except that in the aforementioned alternative embodiment in which feedback scale counter 182 is not used, feedback counter 51 may remain active to output feedback signal 15′ to PFD 154 via optional connection 510. [0063] The presence or absence of a frequency lock on high-gain coarse feedback path 150 also determines whether or not low-gain fine feedback path 151 is active. Details of a preferred embodiment of low-gain fine feedback path 151 are shown in FIG. 7. As long as there is no lock in high-gain coarse feedback path 150, low-gain fine feedback path 151 is kept inactive by applying a signal at 70 to disable phase-frequency detector 155, and applying suitable voltages to the gates of transistor 71 (VREFh) and transistor 72 (VREF1) to keep both of those transistors 71, 72 turned on, forcing low-gain control voltage VCTRL — LG 14 to a constant value midway between VCC and ground (assuming identical values for both transistors 71, 72). In other embodiments, voltage 14 could be forced to another value, or a completely different way to deactivate low-gain fine feedback path 151 can be used. [0064] When a frequency lock on high-gain coarse feedback path 150 is detected, low-gain fine feedback path 151 is activated by applying a signal at 70 to enable phase-frequency detector 155, and applying VCC to the gate of transistor 71 (VREFh) and ground to the gate of transistor 72 (VREF1), turning both of transistors 71, 72 off so that low-gain control voltage VCTRL — LG 14 can assume any value required by phase-frequency detector 155. That voltage 14 will apply “fine-tuning” to the output 12 of VCO 11 generated by high-gain control voltage VCTRL — HG 13 to drive the output 12 to a condition in which it is phase- and frequency-locked with input signal 16, as expected in a PLL. [0065] PLL 10 thus gets most of the way to its locked condition based on a high-gain signal, but that signal is fixed after coarse frequency lock is achieved so that input noise does not cause variations in the output of that signal path. Although noise may occur in the signal on the fine control path, because that path has a smaller expected frequency range, it also magnifies the noise by a smaller amount, resulting in a more stable output. [0066] If phase- and/or frequency-lock is lost during low-gain fine-feedback operation, PLL 10 preferably starts over, first seeking coarse frequency lock before again seeking fine phase-frequency lock. It may be on a loss only of phase that PLL 10 remains within the coarse frequency tolerance condition, in which case PLL 10 will revert to the low-gain fine-feedback mode after only one cycle in high-gain coarse feedback mode. [0067] FIG. 8 shows the basic layout of a preferred embodiment of a DLL 80 in accordance with the invention. In DLL 80, the standard voltage-controlled delay line of known DLLs is replaced by a dual-gain VCDL 81. VCDL 81 preferably has a plurality of taps and therefore may provide a plurality of basic output signals at node 82 each having a different phase delay. For example, VCDL 81 may have four taps, each successive tap providing an output 90� from the preceding tap. The basic outputs are a function of both a control voltage 83 on a high-gain input 830 and a control voltage 84 on a low-gain input 840. The plurality of basic output signals may be combined by phase combiner 881 to provide a single output 820. Two of the output signals at 82 are fed back on a high-gain coarse feedback path 850 producing control voltage 83, and a low-gain fine feedback path 851 producing control voltage 84. [0068] Coarse feedback path 850 preferably includes a phase detector 852 in series with a digital-to-analog converter 853 (which may be conventional). The feedback signal on path 850 preferably is compared to the input signal at node 86 by phase detector 852, preferably in the manner described below, to provide a signal (preferably digital) representative of how much and in which direction the output phase must change. That signal preferably is converted back to analog form by DAC 853 for provision as the high-gain control voltage VCTRL — HG 83 to high-gain input 830 of dual-gain VCDL 81. [0069] Preferably, as long as the frequency of the basic output signal on feedback path 850 varies by more than a predetermined variance from the desired phase, control 87 holds low-gain control voltage VCTRL — LG 84 constant and allows the output of phase detector 852 to vary, driving the basic output signal phase closer to the desired phase. Once the basic output signal phase approaches to within that predetermined variance from the desired phase, control 87 preferably causes high-gain control voltage VCTRL — HG 83 to be locked or fixed at its then-current value by stopping updating of the output of phase detector 852 SO that DAC 853 receives a constant input. Control 87 then turns on low-gain fine feedback path 851. [0070] Fine feedback path 851 preferably is similar to a conventional DLL, having a phase detector 854, a charge pump 855 and a loop filter 856, providing low-gain control voltage VCTRL — LG 84 as a function of the phase comparison of the feedback signal to the input signal at 86. Low-gain control voltage VCTRL — LG 84 provides “fine-tuning” of the coarse phase lock based on high-gain control voltage VCTRL — HG 83, in the same manner as in a conventional DLL. [0071] As explained above, VCDL 81 is a dual-gain VCDL, having a high-gain input 830 and a low-gain input 840. A preferred embodiment of VCDL 81 is shown in FIG. 9, and includes a current-controlled delay line 860, two voltage-to-current converters 861 and 862, and an adder 863 to add the two currents output by converters 861, 862. Converter 861 is designated the high-gain voltage-to-current converter (V/I)HG, while converter 862 is designated the low-gain voltage-to-current converter (V/I)LG. However, the “high” and “low” designations are relative, and are functions of the expected phase range, as discussed above in connection with the PLL embodiment, as shown in FIGS. 1 and 2. The specifics of voltage-to-current converters 861, 862 may be similar to those of voltage-to-current converters 21, 22 as shown in FIGS. 3, 3A, 3B and 4. [0072] Similarly, the control circuit used to turn low-gain fine feedback path 851 on or off is similar to that shown in FIG. 7 for the PLL embodiment, and preferably turns path 851 on when it is determined that the phase on coarse feedback path 850 is sufficiently locked to that of input signal 86. One determination of sufficiency is shown in FIG. 10. A precise phase lock occurs when the falling edge on the 180� phase tap of VCDL 81 coincides with the rising edge of the input signal 86 (shown in FIG. 10 as the 0� phase delay). However, the control circuit may be designed to indicate coarse phase lock when the falling edge on the 180� tap is within the range indicated by dashed lines 890, 891 of the rising edge of input signal 86. As shown in FIG. 10, the range is substantially less than �90�, but other ranges may be used. [0073] A programmable logic device (PLD) 700 incorporating a PLL 10 according to the present invention may be used in many kinds of electronic devices. One possible use is in a data processing system 900 shown in FIG. 11. Data processing system 900 may include one or more of the following components: a processor 901; memory 902; I/O circuitry 903; and peripheral devices 904. These components are coupled together by a system bus 905 and are populated on a circuit board 906 which is contained in an end-user system 907. [0074] System 900 can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD 700 can be used to perform a variety of different logic functions. For example, PLD 700 can be configured as a processor or controller that works in cooperation with processor 901. PLD 700 may also be used as an arbiter for arbitrating access to a shared resources in system 900. In yet another example, PLD 700 can be configured as an interface between processor 901 and one of the other components in system 900. It should be noted that system 900 is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims. [0075] Various technologies can be used to implement PLDs 700 as described above and incorporating this invention. [0076] It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention, and the present invention is limited only by the claims that follow. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3473160 *Oct 10, 1966Oct 14, 1969Stanford Research InstElectronically controlled microelectronic cellular logic arrayUS4272729 *May 10, 1979Jun 9, 1981Harris CorporationAutomatic pretuning of a voltage controlled oscillator in a frequency synthesizer using successive approximationUS4473801 *Dec 17, 1979Sep 25, 1984Robert MaurerDemodulator circuit with phase control loopUS4494021 *Aug 30, 1982Jan 15, 1985Xerox CorporationSelf-calibrated clock and timing signal generator for MOS/VLSI circuitryUS4527127 *Jun 30, 1982Jul 2, 1985Motorola Inc.Frequency acquisition circuit for phase locked loopUS4633488 *Nov 13, 1984Dec 30, 1986Digital Equipment CorporationPhase-locked loop for MFM data recordingUS4719593 *Jul 9, 1984Jan 12, 1988Advanced Micro Devices, Inc.Apparatus for generating digital timing waveformsUS4857866 *Aug 17, 1988Aug 15, 1989Nec CorporationPhase-locked loop having elongated time for charge and dischargeUS4868522 *Dec 13, 1988Sep 19, 1989Gazelle Microcircuits, Inc.Clock signal distribution deviceUS4959646 *Jun 17, 1988Sep 25, 1990Dallas Semiconductor CorporationDynamic PLA timing circuitUS4972163 *Nov 20, 1989Nov 20, 1990Stichting Voor De Technische WetenschappenRegenerating device having a phase-locked loop with loop gain compensation and offset compensationUS5072195 *Apr 5, 1990Dec 10, 1991Gazelle Microcircuits, Inc.Phase-locked loop with clamped voltage-controlled oscillatorUS5075575 *Dec 5, 1990Dec 24, 1991Fuji Photo Film Co., Ltd.Externally synchronized programmable deviceUS5079519 *Feb 14, 1991Jan 7, 1992Notorola, Inc.Digital phase lock loop for a gate arrayUS5121014 *Mar 5, 1991Jun 9, 1992Vlsi Technology, Inc.CMOS delay circuit with controllable delayUS5133064 *Apr 22, 1988Jul 21, 1992Hitachi, Ltd.Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devicesUS5204555 *Apr 2, 1992Apr 20, 1993Gazelle Microcircuits, Inc.Logic array having high frequency internal clockingUS5208557 *Feb 18, 1992May 4, 1993Texas Instruments IncorporatedMultiple frequency ring oscillatorUS5239213 *Jun 11, 1992Aug 24, 1993Advanced Micro Devices, Inc.Precision timing control programmable logic deviceUS5349544 *Jun 15, 1988Sep 20, 1994Advanced Micro Devices, Inc.Programmable system synchronizerUS5363419 *Apr 24, 1992Nov 8, 1994Advanced Micro Devices, Inc.Dual phase-locked-loop having forced mid range fine control zero at handoverUS5394116 *Dec 29, 1993Feb 28, 1995At&T Corp.Fractional phase shift ring oscillator arrangementUS5397943 *Jul 8, 1993Mar 14, 1995Dyna Logic CorporationClock distribution method and apparatus for high speed circuits with low skew using counterpropaging true and complement re-generated clock signals with predetermined ramp shapesUS5418499 *Jul 12, 1994May 23, 1995Mitsubishi Denki Kabushiki KaishaRing oscillator having selectable number of inverter stagesUS5420544 *Oct 4, 1993May 30, 1995Mitsubishi Denki Kabushiki KaishaSemiconductor integrated circuit, method of designing the same and method of manufacturing the sameUS5424687 *Aug 19, 1994Jun 13, 1995Nec CorporationPLL frequency synthesizer and PLL frequency synthesizing method capable of obtaining high-speed lock-up and highly-reliable oscillationUS5448191 *Aug 30, 1994Sep 5, 1995Sgs-Thomson Microelectronics S.A.Frequency synthesizer using noninteger division and phase selectionUS5477182 *Apr 1, 1994Dec 19, 1995U.S. Philips CorporationDelay circuit for delaying differential signals includes separately controllable first and second load and clamp circuits for effecting different delay timesUS5506878 *Jul 18, 1994Apr 9, 1996Xilinx, Inc.Programmable clock having programmable delay and duty cycle based on a user-supplied reference clockUS5542083 *Jun 2, 1995Jul 30, 1996Hitachi, Ltd.Information processor and information processing system utilizing clock signalUS5581214 *Aug 30, 1995Dec 3, 1996Mitsubishi Denki Kabushiki KaishaPhase-locked loop circuitUS5629651 *Aug 3, 1995May 13, 1997Nec CorporationPhase lock loop having a reduced synchronization transfer periodUS5642082 *Jun 20, 1996Jun 24, 1997Altera CorporationLoop filter level detection circuit and methodUS5646564 *Apr 12, 1996Jul 8, 1997Xilinx, Inc.Phase-locked delay loop for clock correctionUS5656959 *Nov 24, 1995Aug 12, 1997International Microcircuits, Inc.Clock synthesizer dual function pin system and method thereforUS5691669 *Jan 11, 1996Nov 25, 1997Hewlett-Packard Co.Dual adjust current controlled phase locked loopUS5699020 *Jun 20, 1996Dec 16, 1997Altera CorporationPhase latched differential charge pump circuit and methodUS5739725 *Jan 29, 1996Apr 14, 1998International Business Machines CorporationDigitally controlled oscillator circuitUS5742180 *Feb 10, 1995Apr 21, 1998Massachusetts Institute Of TechnologyDynamically programmable gate array with multiple contextsUS5744991 *Oct 16, 1995Apr 28, 1998Altera CorporationSystem for distributing clocks using a delay lock loop in a programmable logic circuitUS5777360 *Aug 21, 1995Jul 7, 1998Lsi Logic CorporationHexagonal field programmable gate array architectureUS5815016 *Jun 14, 1996Sep 29, 1998Xilinx, Inc.Phase-locked delay loop for clock correctionUS5847617 *Aug 11, 1997Dec 8, 1998Altera CorporationVariable-path-length voltage-controlled oscillator circuitUS5850164 *May 22, 1997Dec 15, 1998Sgs-Thomson Microelectronics S.A.FM demodulation and frequency tuning for a phase-locked loopUS5889436 *Nov 1, 1996Mar 30, 1999National Semiconductor CorporationPhase locked loop fractional pulse swallowing frequency synthesizerUS5900757 *May 1, 1996May 4, 1999Sun Microsystems, Inc.Clock stopping schemes for data bufferUS5952891 *Jun 13, 1997Sep 14, 1999Bull S.A.Variable delay cell with hysteresis and ring oscillator using sameUS5952892 *Sep 29, 1997Sep 14, 1999Lsi Logic CorporationLow-gain, low-jitter voltage controlled oscillator circuitUS5963069 *Nov 17, 1997Oct 5, 1999Altera CorporationSystem for distributing clocks using a delay lock loop in a programmable logic circuitUS5970110 *Jan 9, 1998Oct 19, 1999Neomagic Corp.Precise, low-jitter fractional divider using counter of rotating clock phasesUS5974105 *Mar 13, 1997Oct 26, 1999Industrial Technology Research InstituteHigh frequency all digital phase-locked loopUS5987543 *Aug 29, 1997Nov 16, 1999Texas Instruments IncorporatedMethod for communicating digital information using LVDS and synchronous clock signalsUS5999025 *Mar 27, 1998Dec 7, 1999Xilinx, Inc.Phase-locked loop architecture for a programmable logic deviceUS6014048 *May 27, 1998Jan 11, 2000Advanced Micro Devices, Inc.Clock generator with multiple feedback paths including a delay locked loop pathUS6043677 *Oct 15, 1997Mar 28, 2000Lucent Technologies Inc.Programmable clock manager for a programmable logic device that can implement delay-locked loop functionsUS6069506 *May 20, 1998May 30, 2000Micron Technology, Inc.Method and apparatus for improving the performance of digital delay locked loop circuitsUS6069507 *May 22, 1998May 30, 2000Silicon Magic CorporationCircuit and method for reducing delay line length in delay-locked loopsUS6097777 *Jun 20, 1997Aug 1, 2000Pioneer Electronic CorporationPhase locked loop circuitUS6104222 *Dec 17, 1997Aug 15, 2000Sony CorporationFlexible phase locked loop systemUS6114915 *Mar 23, 1999Sep 5, 2000Altera CorporationProgrammable wide-range frequency synthesizerUS6141394 *Dec 22, 1997Oct 31, 2000Philips Electronics North America CorporationFractional-N frequency synthesizer with jitter compensationUS6144242 *Sep 4, 1998Nov 7, 2000Silicon Image, Inc.Controllable delays in multiple synchronized signals for reduced electromagnetic interference at peak frequenciesUS6157266 *Feb 12, 1998Dec 5, 2000Hewlett-Packard CompanyDelay elements arranged for a signal controlled oscillatorUS6249189 *Aug 5, 1998Jun 19, 2001National Science Council Of Republic Of ChinaFrequency synthesizer accomplished by using multiphase reference signal sourceUS6252419 *Aug 4, 1999Jun 26, 2001Altera CorporationLVDS interface incorporating phase-locked loop circuitry for use in programmable logic deviceUS6278332 *Feb 15, 2000Aug 21, 2001Agere Systems Guardian Corp.Charge pump for low-voltage, low-jitter phase locked loopsUS6320469 *Feb 15, 2000Nov 20, 2001Agere Systems Guardian Corp.Lock detector for phase-locked loopUS6326826 *May 17, 2000Dec 4, 2001Silicon Image, Inc.Wide frequency-range delay-locked loop circuitUS6366174 *Feb 21, 2000Apr 2, 2002Lexmark International, Inc.Method and apparatus for providing a clock generation circuit for digitally controlled frequency or spread spectrum clockingUS6373278 *Jan 11, 2001Apr 16, 2002Altera CorporationLVDS interface incorporating phase-locked loop circuitry for use in programmable logic deviceUS6411150 *Jan 30, 2001Jun 25, 2002Cypress Semiconductor Corp.Dynamic control of input buffer thresholdsUS6462623 *May 17, 2000Oct 8, 2002Parthus Ireland LimitedMethod and apparatus for PLL with improved jitter performanceUS6483886 *Aug 4, 1999Nov 19, 2002Altera CorporationPhase-locked loop circuitry for programmable logic devicesUS6633185 *May 1, 2002Oct 14, 2003Altera CorporationPLL/DLL circuitry programmable for high bandwidth and low bandwidth applicationsUS6680632 *Feb 26, 2002Jan 20, 2004Cypress Semiconductor Corp.Method/architecture for a low gain PLL with wide frequency rangeUS20010033188 *Mar 13, 2001Oct 25, 2001Edward AungClock data recovery circuitry associated with programmable logic device circuitry* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7218176 *Sep 8, 2004May 15, 2007Mediatek Inc.Digital phase-locked loop circuitUS7301380Apr 12, 2006Nov 27, 2007International Business Machines CorporationDelay locked loop having charge pump gain independent of operating frequencyUS7453296Sep 12, 2007Nov 18, 2008International Business Machines CorporationDelay locked loop having charge pump gain independent of operating frequencyUS8143957 *Apr 7, 2006Mar 27, 2012Qualcomm, IncorporatedCurrent-mode gain-splitting dual-path VCOUS8237475 *Oct 8, 2008Aug 7, 2012Altera CorporationTechniques for generating PVT compensated phase offset to improve accuracy of a locked loopUS8781428 *Mar 2, 2010Jul 15, 2014Silicon Laboratories Inc.Frequency synthesizerUS8948330 *Aug 20, 2012Feb 3, 2015Marvell International Ltd.Systems and methods for performing variable structure timing recoveryUS20050062549 *Sep 8, 2004Mar 24, 2005Mediatek IncDigital phase-locked loop circuitUS20070159262 *Apr 7, 2006Jul 12, 2007Xiaohong QuanCurrent-mode gain-splitting dual-path VCOUS20070241798 *Apr 12, 2006Oct 18, 2007Masenas Charles JDelay locked loop having charge pump gain independent of operating frequencyUS20080054962 *Sep 12, 2007Mar 6, 2008Masenas Charles JDelay locked loop having charge pump gain independent of operating frequencyUS20080054963 *Sep 12, 2007Mar 6, 2008Masenas Charles JDelay locked loop having charge pump gain independent of operating frequencyUS20110215848 *Sep 8, 2011Silicon Laboratories Inc.Frequency synthesizerWO2009088790A1 *Dec 24, 2008Jul 16, 2009Qualcomm IncorporatedDigital phase-locked loop with gated time-to-digital converter* Cited by examinerClassifications U.S. Classification327/156International ClassificationH03L7/113, H03L7/189, H03L7/099, H03L7/089, H03L7/06, H03L7/087, H03L7/081, H03J7/06, H03L7/08, H03L7/18, H03L7/197Cooperative ClassificationH03L7/113, H03L7/0891, H03L7/087, H03L7/0818, H03L2207/06, H03L7/18, H03L7/099, H03L7/0812European ClassificationH03L7/081A, H03L7/087, H03L7/099, H03L7/113Legal EventsDateCodeEventDescriptionSep 5, 2003ASAssignmentOwner name: ALTERA CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STARR, GREGORY;REEL/FRAME:014474/0710Effective date: 20030828Aug 21, 2009FPAYFee paymentYear of fee payment: 4Aug 26, 2013FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services