Source: https://patents.google.com/patent/US7925808B2/en
Timestamp: 2018-03-24 18:43:10
Document Index: 798092492

Matched Legal Cases: ['Application No. 60', 'Application No. 200810098473', 'Application No. 2006', 'Application No. 2006', 'Application No. 200810098473', 'Application No. 2006', 'Application No. 200810098473']

US7925808B2 - Memory system and device with serialized data transfer - Google Patents
US7925808B2
US7925808B2 US12116439 US11643908A US7925808B2 US 7925808 B2 US7925808 B2 US 7925808B2 US 12116439 US12116439 US 12116439 US 11643908 A US11643908 A US 11643908A US 7925808 B2 US7925808 B2 US 7925808B2
US12116439
US20080209141A1 (en )
This application is a continuation of Ser. No. 11/549,841 filed on Oct. 16, 2006, now pending, which is a continuation of U.S. patent application Ser. No. 10/385,908 filed Mar. 11, 2003, now U.S. Pat. No. 7,313,639, which application claims priority from U.S. Provisional Application No. 60/439,666 filed Jan. 13, 2003.
The circuitry for generating bit 1 of the mask key, MK[1], includes two summing circuits 3610 and 3611, and an elimination circuit 360. The elimination circuit includes 64 bitwise elimination circuits, E0, each of which corresponds to a respective mask-qualified byte and generates two signals that correspond to the two possible elimination results according to the state of the 0th bit of the mask key, MK[0]. For example, if MK[0] is 0, then all bytes of the mask-qualified byte pool for which bit 0 (b0) is 1 are to be eliminated, and if MK[0]=1, then all bytes for which b0=0 are to be eliminated. Accordingly, each of the bitwise elimination circuits, E0, generates a first qualified bit 1 (qb1 0) which is forced to 0 if b0=1, and set according to b1 if b0=0; and a second qualified bit 1 (qb1 1) which is forced to if b0=0, and equal to b1 if b0=1. In Boolean notation (‘&’ indicating a bitwise AND operation):
qb21=b2&b1&b0;
qb22=b2&b1&b0; and
It should be noted that execution of a two-phase masked-write operation, though effective for resolving a mask conflict, has the undesirable characteristic of requiring two masked-write accesses to the storage subsystem instead of one. Consequently, the greater the frequency of two-phase masked-write operations, the lower the effective memory bandwidth of the memory system. One direct way to reduce the frequency of two-phase masked-write operations is to increase the number of predetermined mask keys from which the mask key is selected. As a statistical matter, assuming a set of R predetermined mask keys and a population of X write data values each having a unique pattern of N constituent bits, each additional mask key decreases the likelihood of a mask conflict by a factor of (X−R)/(2N−R). For example, in a system having a population of 64 write data values (one masked), byte-mask granularity, and two predetermined mask keys, the likelihood of a mask conflict in the population is (63/256)*(62/255)=˜6%. If two additional predetermined mask keys are provided, the likelihood of a mask conflict is reduced to (63/256)*(62/255)* (61/254)*(60/253)=0.34%. Letting P represent the number of predetermined mask keys, the number of constituent bits required in the key selector is log2(P). In general, so long as log2(P) is smaller than the mask granularity, a bandwidth savings is achieved over a mask-key-transfer embodiment.
MD 0 ⁢ : QM ⁢ ⁢ 0 0 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 0 = MK ⁢ ⁢ 0 ) & / M ⁢ ⁢ 0 QM ⁢ ⁢ 0 1 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 0 = MK ⁢ ⁢ 1 ) & / M ⁢ ⁢ 0 QM ⁢ ⁢ 0 2 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 0 = MK ⁢ ⁢ 2 ) & / M ⁢ ⁢ 0 QM ⁢ ⁢ 0 3 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 0 = MK ⁢ ⁢ 3 ) & / M ⁢ ⁢ 0 MD 1 ⁢ : QM ⁢ ⁢ 1 0 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 1 = MK ⁢ ⁢ 0 ) & / M ⁢ ⁢ 1 QM ⁢ ⁢ 1 1 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 1 = MK ⁢ ⁢ 1 ) & / M ⁢ ⁢ 1 QM ⁢ ⁢ 1 2 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 1 = MK ⁢ ⁢ 2 ) & / M ⁢ ⁢ 1 QM ⁢ ⁢ 1 3 ⁢ : ⁢ ⁢ ( WD ⁢ ⁢ 1 = MK ⁢ ⁢ 3 ) & / M ⁢ ⁢ 1 ⁢ ⋮ MD X - 1 ⁢ : QM ⁡ ( X - 1 ) 0 ⁢ : ⁢ ( WD ⁡ ( X - 1 ) = MK ⁢ ⁢ 0 ) & / M ⁡ ( X - 1 ) QM ⁡ ( X - 1 ) 1 ⁢ : ⁢ ( WD ⁡ ( X - 1 ) = MK ⁢ ⁢ 1 ) & / M ⁡ ( X - 1 ) QM ⁡ ( X - 1 ) 2 ⁢ : ⁢ ( WD ⁡ ( X - 1 ) = MK ⁢ ⁢ 2 ) & / M ⁡ ( X - 1 ) QM ⁡ ( X - 1 ) 3 ⁢ : ⁢ ( WD ⁡ ( X - 1 ) = MK ⁢ ⁢ 3 ) & / M ⁡ ( X - 1 )
Still referring to FIG. 22, the qualified signals QM0 0, QM1 0, . . . , QM(X−1)0 all correspond to mask key MK0 (each indicating whether MK0 matches a respective unmasked data value within the write data block), and are supplied to respective inverting inputs of AND logic gate 585 0. Thus, if all the qualified match signals corresponding to MK0 are low, the output of AND logic gate 585 0 (i.e., S0) will be high to indicate that MK0 does not match any unmasked data values within the write data block. Similarly, qualified match signals QM0 1, QM1 1, . . . QM(X−1)1 all correspond to MK1 and are supplied to inverting inputs of AND logic gate 585 1; qualified match signals QM0 2, QM1 2, . . . , QM(X−1)2 all correspond to MK2 and are supplied to inverting inputs of AND logic gate 585 2; and qualified match signals QM0 3, QM1 3, . . . , QM(X−1)3 all correspond to MK3 and are supplied to inverting inputs of AND logic gate 585 3. Thus each of the AND logic gates 585 0-585 3 will output a logic high signal if the corresponding mask key, MK0-MK3, does not match any unmasked data values within the write data block. The outputs of the AND logic gates 585 0-585 3 (i.e., signals S0-S3, respectively) are supplied to the encoder 587 where they are used to set the states of the key selector 552 and conflict signal 556. In one embodiment, the encoder 587 generates a key selector 552 that corresponds to the lowest numbered match key for which the output of the corresponding one of signals S0-S3 is high. That is, KSEL[1:0] is set to 00 to select MK0 if S0 is high; 01 to select MK1 if S0 is low and S1 is high; 10 to select MK2 if S0 is low, S1 is low and S2 is high; and 11 to select MK3 if S0 is low, S1 is low, S2 is low and S3 is high. If signals S0-S3 are all low, then none of the mask keys MK0-MK3 are unique relative to the write data block and a conflict condition exists. In the embodiment of FIG. 22, the encoder 587 asserts the conflict signal 556 to indicate the mask conflict condition, and sets the key selector 552 to select mask key MK0 to be the default mask key for a first phase of a two-phase masked-write. After the first phase of the two-phase masked-write, the encoder 557 sets the key selector to select mask key MK1 to be the default mask key for the second phase of the two-phase masked-write. Other key table selections may be used as the default mask keys for the first and/or second phases of the two-phase masked-write in alternative embodiments.
for each data value that does correspond to a code representing a mask key, not writing the data value into the array of storage cells, so as to not overwrite existing content of the array associated with a position of the data value within the block of data values.
US12116439 2003-01-13 2008-05-07 Memory system and device with serialized data transfer Active 2024-08-16 US7925808B2 (en)
US20080209141A1 true US20080209141A1 (en) 2008-08-28
US7925808B2 true US7925808B2 (en) 2011-04-12
US7171528B2 (en) * 2003-01-13 2007-01-30 Rambus Inc. Method and apparatus for generating a write mask key
"A Logical Overview of Direct Rambus Architecture," Rambus, Inc., Mar. 1998, 150 pages.
"AMD-751 System Controller Data Sheeet", AMD, Mar. 2000.
"AMD-762 System Controller Data Sheet", AMD, Dec. 2001.
"FCRAM I IP CORE", Lattice Semiconductor Corporation, Nov. 2004.
"Virtex Synthesizable High Performance SDRAM Controller", XILINX, XAPP 134, Version 2.1, Sep. 10, 1999.
Chinese Office Action dated Nov. 8, 2010, State Intellectual Property Office, Chinese Patent Application No. 200810098473.4 filed Jan. 13, 2004.
English Translation of Response to Japanese Office Action filed Aug. 23, 2010, Japan Patent Office, Japanese Patent Application No. 2006-500933, filed Jan. 13, 2004.
English Translation of the Abstract of European Patent Publication No. EP0604309 dated Jun. 29, 1994.
Final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 11/549,841, filed Oct. 16, 2006, Jul. 11, 2008.
Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 11/549,841, filed Oct. 16, 2006, Sep. 22, 2008.
Office Action dated Feb. 23, 2010, Japan Patent Office, Japanese Patent Application No. 2006-500933 filed Jan. 13, 2004.
Rambus Inc., "16/18Mbit (2Mx8/9) & 64/72 Mbit (8Mx8/9) Concurrent RDRAM—Advance Information," Rambus Inc. Data Sheet, Jul. 1996, 61 pages.
Rambus Inc., "8/9-Mbit (1Mx8/9) & 16/18Mbit (2Mx8/9) RDRAM—Preliminary Information," Rambus Inc. Data Sheet, Mar. 1, 1996, 30 pages.
Response to Chinese Office Action filed Jan. 5, 2011, State Intellectual Property Office, Chinese Patent Application No. 200810098473.4 filed Jan. 13, 2004.
Response to Final Office Action, U.S. Appl. No. 11/549,841, filed Oct. 16, 2006, Aug. 26, 2008.
Response to Japanese Office Action filed Aug. 23, 2010, Japan Patent Office, Japanese Patent Application No. 2006-500933, filed Jan. 13, 2004.
Response to Office Action dated Feb. 2, 2010, Chinese Patent Application No. 200810098473.4 filed Jan. 13, 2004.