Source: http://www.google.se/patents/US8112655?hl=sv
Timestamp: 2013-05-19 21:59:00
Document Index: 265625010

Matched Legal Cases: ['Application No. 10', 'application No. 07', 'application No. 07', 'application No. 08836238', 'Application No. 11168486', 'application No. 07', 'Application No. 10', 'Application No. 2006800130653']

Patent US8112655 - Mesosynchronous data bus apparatus and method of data transmission - Google PatentS�k Bilder Kartor Play YouTube Nyheter Gmail Drive Mer » Avancerad patents�kning | Webbhistorik | Logga in Avancerad patents�kning PatentA memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination...http://www.google.se/patents/US8112655?utm_source=gb-gplus-sharePatent US8112655 - Mesosynchronous data bus apparatus and method of data transmission PublikationsnummerUS8112655 B2Typ av kung�relseBeviljande Ans�kningsnummer12/245,349 Publiceringsdatum7 feb 2012 Registreringsdatum3 okt 2008�ven publicerat somUS20090150707 UppfinnareJon C. R. BennettKevin D. DruckerJames H. Jones Ursprunglig innehavareViolin Memory, Inc. USA-klassificering713/500713/400375/355713/401714/700713/503375/354 Internationell klassificeringG06F1/00G06F1/12 Kooperativ klassningG06F13/4247G11C7/10G06F13/4243 Europeisk klassificeringG06F 13/42C3SG11C 7/10G06F 13/42DH�nvisningarCitat fr�n patent (109)Citat fr�n andra k�llor (43)Externa l�nkarUSPTO �verl�telse av �gander�tt till patent som har registrerats av USPTO EspacenetMesosynchronous data bus apparatus and method of data transmissionUS 8112655 B2 Sammanfattning A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.
re-sampling the sampled data at a submultiple of the clock frequency and adjusting the phase or time delay of the re-sampling clock so that the overall time delay between the transmitted character from the first node and a character on the same lane transmitted by the second node is substantially constant. Beskrivning
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