Source: http://www.google.com/patents/US7584009?dq=6008737
Timestamp: 2014-10-22 23:09:04
Document Index: 407043589

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US7584009 - Multi-chip PWM synchronization and communication - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsSystems and methods for synchronizing multiple digital audio controller chips, wherein one of the chips is designated as a master and the other chips are designated as slaves. A common line connects all of the chips and is used to transmit synchronization signals from the master to the slaves. Each of...http://www.google.com/patents/US7584009?utm_source=gb-gplus-sharePatent US7584009 - Multi-chip PWM synchronization and communicationAdvanced Patent SearchPublication numberUS7584009 B2Publication typeGrantApplication numberUS 10/805,593Publication dateSep 1, 2009Filing dateMar 19, 2004Priority dateMar 21, 2003Fee statusPaidAlso published asUS20040186602Publication number10805593, 805593, US 7584009 B2, US 7584009B2, US-B2-7584009, US7584009 B2, US7584009B2InventorsJack B. Andersen, Daniel L. W. Chieng, Michael A. Kost, Jan A. LarsonOriginal AssigneeD2Audio CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (11), Non-Patent Citations (1), Referenced by (1), Classifications (19), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetMulti-chip PWM synchronization and communicationUS 7584009 B2Abstract Systems and methods for synchronizing multiple digital audio controller chips, wherein one of the chips is designated as a master and the other chips are designated as slaves. A common line connects all of the chips and is used to transmit synchronization signals from the master to the slaves. Each of the chips listens for an appropriate signal and, when the signal is detected, all of the chips simultaneously begin operation. In one embodiment, the synchronization signal comprises a transition on the shared line to an active state. The transition is repeated at fixed intervals and maintained in the active state for a fixed period in order to enable the chips to determine whether synchronization is being maintained. The signal may be sampled and/or filtered to improve reliability. The chips may be able to drive the shared line active to indicate that synchronization has been lost.
RELATED APPLICATIONS This application claims priority to: U.S. Provisional Patent Application No. 60/469,734, entitled �Multi-chip PWM with Staggered Outputs,� by Jack B. Andersen, et al., filed May 12, 2003; U.S. Provisional Patent Application No. 60/456,414, entitled �Adaptive Anti-Clipping Protection,� by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,430, entitled �Frequency Response Correction,� by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,429, entitled �High-efficiency, High-Performance Sample Rate Converter,� by Andersen, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,421, entitled �Output Device Switch Timing Correction,� by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,422, entitled �Output Filter, Phase Timing Correction,� by Taylor, et al., filed Mar 21, 2003; U.S. Provisional Patent Application No. 60/456,428, entitled �Output Filter Speaker/Load Compensation,� by Taylor,et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,420, entitled �Output Stage Channel Timing Calibration,� by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,427, entitled �Intelligent Over-Current, Over-Load Protection,� by Hand, et al., filed Mar. 21, 2003; each of which is fully incorporated by reference as if set forth herein in its entirety.
SUMMARY OF THE INVENTION One or more of the problems outlined above may be solved by the various embodiments of the invention. Broadly speaking, the invention comprises systems and methods for enabling the use of multiple digital PWM chips in the same system to provide the additional channels and corresponding capabilities of which are required for many applications. In one embodiment, this is achieved by providing a mechanism through which multiple digital PWM chips can be synchronized. This enables the scaling of systems to provide as many channels as are necessary for any given application.
In one embodiment, a plurality of digital audio controllers are implemented on multiple chips. One of the chips is designated as a master, while the other chips are designated as slaves. A common synchronization line connects all of the chips and is used to transmit synchronization signals from the master to the slaves. When the master chip transmits an appropriate signal, all of the chips detect the signal and simultaneously begin synchronized operation. In this context, �synchronized operation� refers to the chips beginning to operate and doing so in a synchronized manner. It should be noted that other embodiments may also use this mechanism to time-align or phase align the outputs of chips that are already running.
As described herein, various embodiments of the invention comprise systems and methods for synchronizing multiple digital audio controller chips (i.e., controllers implemented on different pieces of silicon, so that they cannot be internally synchronized). In one embodiment, one of the chips is designated as a master, while the other chips are designated as slaves. A common line connects all of the chips and is used to transmit synchronization signals from the master to the slaves. When the master chip transmits an appropriate signal, all of the chips simultaneously begin operation. As noted above, �synchronized operation� in this context refers to the chips beginning to operate and doing so in a synchronized manner, but other embodiments may use the same mechanism to time-align or phase align the outputs of chips that are already running.
In a multi chip system in accordance with one embodiment, one chip is the designated master and the other chips are slaves. the is illustrated in FIG. 2. FIG. 2 is a diagram illustrating the master-slave relationship between the PWM controller chips in one embodiment. While the figure depicts four controller chips, there may be n controller chips corresponding to m channels. One of the controller chips, 210, is a master. The remainder of the controller chips, 220, are slaves to master 210. The role of each chip is assigned when the chips are initialized. All of the chips run off a common clock source�either directly off a distributed high speed clock�or off a lower speed distributed clock using PLLs with a common multiplication factor.
One wire 230 which is connected to each of the chips is used for synchronization. (Although the interconnect between the different chips is referred to herein as a �wire�, it should be noted that any suitable type of interconnect can be used.) In one embodiment, the wire can be in one of two states: active or passive. The actual encoding (high/low) will depend on the particular implementation.
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