Source: http://www.google.com/patents/US7464198?ie=ISO-8859-1
Timestamp: 2015-05-06 04:07:46
Document Index: 382769166

Matched Legal Cases: ['Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 04', 'Application No. 04']

Patent US7464198 - System on a chip and a method for programming a DMA controller in a system ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method is provided for programming a DMA controller in a system on a chip. According to the method, a memory management unit translates a programming virtual address into a programming physical address according to a translation table. A first sub-block without discontinuity beginning at the programming...http://www.google.com/patents/US7464198?utm_source=gb-gplus-sharePatent US7464198 - System on a chip and a method for programming a DMA controller in a system on a chipAdvanced Patent SearchPublication numberUS7464198 B2Publication typeGrantApplication numberUS 11/187,601Publication dateDec 9, 2008Filing dateJul 22, 2005Priority dateJul 23, 2004Fee statusPaidAlso published asDE602005003987D1, DE602005003987T2, EP1619589A1, EP1619589B1, US20060168365Publication number11187601, 187601, US 7464198 B2, US 7464198B2, US-B2-7464198, US7464198 B2, US7464198B2InventorsAlbert Martinez, M. William OrlandoOriginal AssigneeStmicroelectronics SaExport CitationBiBTeX, EndNote, RefManPatent Citations (23), Non-Patent Citations (6), Referenced by (5), Classifications (16), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSystem on a chip and a method for programming a DMA controller in a system on a chip
US 7464198 B2Abstract
22. The method for programming a DMA controller according to claim 20, wherein the user program does not have access to the physical addresses of the physical memory space. Description
A silicon integrated system or System on a Chip (SoC) includes at least a central processing unit (CPU) on which programs can be run, a direct memory access controller (DMA controller), a memory and a memory management unit (MMU). Such SoCs are typically included in electronic devices such as general purpose computers, decoder units or �Set-Top-Boxes�, personal digital assistants or PDAs, mobile phones, etc.
Various solutions are proposed in the documents �User-Level DMA without Operating System Kernel Modification�, by Evangelos P. Markatos and Manolis G. H. Katevenis (Institute of Computer Science, Science and Technology Park of Crete, 1997 IEEE), �Protected User-Level DMA for the Shrimp Network Interface�, by M. A. Blumrich et al. (Proc. of the 2nd International Symposium on High Performance Computer Architecture, pages 154-165, February 1996) and �Integration of Message Passing and Shared Memory in the Stanford Flash Multi-Processor�, by J. Heinlein et al. (Proc. of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 38-50, 1994).
According to these solutions, implicit addressing (or �shadow addressing�) is performed, based on the �STORE� instruction and the prefix 1. The drawback of these solutions is that the addressable memory space in practice is reduced by half, which is very detrimental.
In certain other of these known systems on a chip, the OS scans a page table of the physical memory space, generates chained lists indicating the discontinuities and, on DMA programming, supplies the relevant chained list to the DMA controller, which was designed to then be programmed according to this chained list (�scatter gather� mechanism) without the intervention of the OS.
However, the present invention can be implemented in any system on a chip that allows a DMA controller to be programmed directly by a user program. For example, it can be a system on a chip using a �shadow addressing� technique, or even a system corresponding to those considered in French Patent Application No. 04 06666 or French Patent Application No. 04 08084.
The state machine 17 of the DMA controller 11 is designed, when it detects the presence of the base subaddress PA_DMA_BASE in the high-order bits of a word M placed on the address bus BA, to select a predefined register from the registers 13, 14, and 15 of the set 12 according to the current state of the state machine 17 in accordance with an ordered cycle C of states, which comprises a starting �size� state, followed by a �source� state, then a �size� state, then a �destination� state. The state machine 17 stores in the selected register the data then appearing on the data bus BD.
the �Translate� instruction (�T� instruction), whose format is �Translate (argVA; argD)�, where �argVA� is a virtual address argument and �argD� is a data argument, is used to translate the virtual address supplied as an address argument into a corresponding physical address and to store this physical address in the buffer register 7; and
the �StoreDMA� instruction (�S� instruction), whose format is �StoreDMA argVA�, where �argVA� is a virtual address argument, is used to apply the physical address stored in the buffer register 7 to the data bus BD.
�Translate� (VA_SRC; t0)� (instruction �T1�), then:
�StoreDMA VA_SRC� (instruction �S1�).
�Translate� (VA_DEST; t0)� (instruction �T2�), then:
�StoreDMA VA_DEST� (instruction �S2�).
When the second instruction S1 �StoreDMA VA_SRC� of the sequence Seq1 is executed by the user program P, the CPU 2 places the virtual address argument supplied (in this case, VA_SRC) on the bus VA and sets the wire f2 to the high level. The multiplexer 8 receives the virtual address VA_SRC and is controlled by the control block 10 to supply the address to the MMU 4.
In the same way as was detailed previously from the instruction T1 �Translate (VA_SRC; t0)�, on execution of the instruction T2 (�Translate (VA_DEST; t0)�) by the user program P, the CPU 2 places the virtual address argument supplied (in this case, VA_DEST) on the bus VA′, places the data argument supplied (in this case, the size t0) on the bus DATA_0 and sets the wire f1 to the high level.
When the instruction S2 (�StoreDMA VA_DEST�) is executed by the user program P, the CPU 2 places the virtual address argument supplied (in this case, VA_DEST) on the bus VA and sets the wire f2 to the high state. The virtual address VA_DEST is then delivered by the multiplexer 8 to the MMU 4.
Similarly, by carrying out the same steps from the destination virtual address supplied by the user program P via the instruction �T2�, a number (kD+1) of sub-blocks separated by kD discontinuities in the part PPD of the physical memory space is detected, and the memory page Pblocks also contains all the information relating to the address and the size of these (kD+1) sub-blocks.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4849875Aug 10, 1987Jul 18, 1989Tandon CorporationComputer address modification system with optional DMA pagingUS5623692 *May 15, 1995Apr 22, 1997Nvidia CorporationArchitecture for providing input/output operations in a computer systemUS5659798 *Feb 2, 1996Aug 19, 1997Blumrich; Matthias AugustinMethod and system for initiating and loading DMA controller registers by using user-level programsUS5685011 *May 15, 1995Nov 4, 1997Nvidia CorporationApparatus for handling failures to provide a safe address translation in an improved input/output architecture for a computer systemUS5708849Jan 27, 1997Jan 13, 1998Intel CorporationImplementing scatter/gather operations in a direct memory access device on a personal computerUS5721947 *May 15, 1995Feb 24, 1998Nvidia CorporationApparatus adapted to be joined between the system I/O bus and I/O devices which translates addresses furnished directly by an application programUS5740464 *Nov 19, 1996Apr 14, 1998Nvidia CorporationArchitecture for providing input/output operations in a computer systemUS5758182 *Aug 18, 1997May 26, 1998Nvidia CorporationDMA controller translates virtual I/O device address received directly from application program command to physical i/o device address of I/O device on device busUS5887190Sep 12, 1997Mar 23, 1999Nvidia CorporationSystem for determining from a command storing in a storage circuit an application program which has initiated the command to determine an input/output device addressUS5890220May 31, 1995Mar 30, 1999Hitachi, Ltd.Address conversion apparatus accessible to both I/O devices and processor and having a reduced number of index buffersUS6219725Aug 28, 1998Apr 17, 2001Hewlett-Packard CompanyMethod and apparatus for performing direct memory access transfers involving non-sequentially-addressable memory locationsUS6353867 *Jan 14, 2000Mar 5, 2002Insilicon CorporationVirtual component on-chip interfaceUS6615292Mar 23, 2000Sep 2, 2003Nec CorporationData transfer apparatus performing DMA data transfer from non-consecutive addressesUS6766383 *Sep 27, 2000Jul 20, 2004Conexant Systems, Inc.Packet-based direct memory accessUS6775744 *Feb 15, 2002Aug 10, 2004Hitachi, Ltd.Disk memory deviceUS7225316 *Nov 17, 2003May 29, 2007Intel CorporationMemory mapping apparatus, systems, and methodsUS20020174272 *Sep 24, 2001Nov 21, 2002Dai FujiiDMA controller and automatic DMA controller generating apparatusUS20040255072 *Jun 16, 2003Dec 16, 2004Cahide KirisData packing and unpacking engineUS20050172047 *Jan 27, 2005Aug 4, 2005Nextio Inc.Fibre channel controller shareable by a plurality of operating system domains within a load-store architectureUS20060010262 *Jun 16, 2005Jan 12, 2006Stmicroelectronics SaProcedure for processing a virtual address for programming a DMA controller and associated system on a chipEP0447145A2Mar 11, 1991Sep 18, 1991Hewlett-Packard CompanyUser scheduled direct memory access using virtual addressesEP0589664A1Sep 20, 1993Mar 30, 1994International Business Machines CorporationScatter-gather in data processing systemJPH05216809A Title not available* Cited by examinerNon-Patent CitationsReference1Evangelos P. Markatos et al., "User-Level DMA Without Operating System Kernel Modification", High-Performance Computer Architecture, 1997, Third International Symposium on San Antonio, TX, Feb. 1997, XP010213223, pp. 322-331.2French Preliminary Search Report dated Feb. 21, 2005 for French Application No. 04 07763.3French Preliminary Search Report dated Jan. 25, 2005 for French Application No. 04 06666.4French Preliminary Search Report dated Mar. 7, 2005 for French Application No. 04 08084.5French Preliminary Search Report dated Mar. 9, 2005 for French Application No. 04 08202.6Matthias A. Blumrich et al., "Protected, User-Level DMA for the Shrimp Network Interface", High Performance Computer Architecture, 1996, Second International Symposium on San Jose, CA, Feb. 1996, XP010162056, pp. 154-165.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8255475Apr 28, 2009Aug 28, 2012Mellanox Technologies Ltd.Network interface device with memory management capabilitiesUS8645663Sep 12, 2011Feb 4, 2014Mellanox Technologies Ltd.Network interface controller with flexible memory handlingUS8745276Sep 27, 2012Jun 3, 2014Mellanox Technologies Ltd.Use of free pages in handling of page faultsUS8761189Jun 28, 2012Jun 24, 2014Mellanox Technologies Ltd.Responding to dynamically-connected transport requestsUS8914458Sep 27, 2012Dec 16, 2014Mellanox Technologies Ltd.Look-ahead handling of page faults in I/O operationsClassifications U.S. Classification710/22, 711/205, 711/207, 711/209, 711/206, 711/216, 711/E12.067, 710/26, 711/200International ClassificationG06F9/26, G06F12/10, G06F13/28Cooperative ClassificationG06F13/28, G06F12/1081European ClassificationG06F12/10P, G06F13/28Legal EventsDateCodeEventDescriptionMay 25, 2012FPAYFee paymentYear of fee payment: 4Oct 5, 2005ASAssignmentOwner name: STMICROELECTRONICS SA, FRANCEFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MARTINEZ, ALBERT;ORLANDO, M. WILLIAM;REEL/FRAME:016622/0170Effective date: 20050826RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services