Source: http://www.google.com/patents/US5761216?dq=7,603,356
Timestamp: 2015-02-01 12:36:31
Document Index: 232239802

Matched Legal Cases: ['art 210', 'art 66', 'art 66', 'art 266', 'art 266', 'art 266', 'art 266', 'art 31', 'art 32', 'art 210', 'art 230', 'art 31', 'art 31', 'art 210', 'art 230', 'art 230', 'art 230', 'art 31', 'art 32', 'art 32', 'art 210', 'art 230']

Patent US5761216 - Bit error measurement system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA bit error measurement system provides means for generating test patterns, multiplexing means and means for specifying and recording a pattern position. In a first aspect, a bit error measurement system has a pattern generator having M channels of pattern generation and a pattern generation controller...http://www.google.com/patents/US5761216?utm_source=gb-gplus-sharePatent US5761216 - Bit error measurement systemAdvanced Patent SearchPublication numberUS5761216 APublication typeGrantApplication numberUS 08/732,303PCT numberPCT/JP1996/000405Publication dateJun 2, 1998Filing dateFeb 22, 1996Priority dateFeb 24, 1995Fee statusLapsedAlso published asWO1996026451A1Publication number08732303, 732303, PCT/1996/405, PCT/JP/1996/000405, PCT/JP/1996/00405, PCT/JP/96/000405, PCT/JP/96/00405, PCT/JP1996/000405, PCT/JP1996/00405, PCT/JP1996000405, PCT/JP199600405, PCT/JP96/000405, PCT/JP96/00405, PCT/JP96000405, PCT/JP9600405, US 5761216 A, US 5761216A, US-A-5761216, US5761216 A, US5761216AInventorsTetsuo Sotome, Takayuki Nakajima, Kazutaka Osawa, Kazuhiro Shimawaki, Kouichi ShiroyamaOriginal AssigneeAdvantest Corp.Export CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (102), Classifications (15), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetBit error measurement systemUS 5761216 AAbstract A bit error measurement system provides means for generating test patterns, multiplexing means and means for specifying and recording a pattern position. In a first aspect, a bit error measurement system has a pattern generator having M channels of pattern generation and a pattern generation controller 10 for controlling the pattern generation in the M channels so that when one channel is selected to generate a pattern the other channels are controlled to be waiting. In a second aspect, a clock frequency difference detector 150 is provided for counting a frequency of an input clock 111 and comparing the results with the frequency at the time of previous switching to detect whether the frequency change is greater than a predetermined value to judge whether the system is in a measurement state and to permit or prohibit a switching operation of a clock switch circuit. In a third aspect, a pattern position recording part 210 is provided to store pattern position information of a reference pattern generator 262 when an error detection signal 265a is received from a comparator 265.
What is claimed is: 1. A test pattern generator to be used for a bit error measurement and has a M channel selectable pattern generator to generate selected test patterns, characterized in that said test pattern generator having:a pattern generator having M channels for pattern generation: and a pattern generation controller (10) for controlling the pattern generation by sequentially switching each of said channels of said pattern generator in real time such that while one channel of said pattern generator is selected and generating the test pattern, the other channels are waiting for the next pattern generation. 2. A test pattern generator as defined in claim 1, wherein said pattern generator has two channels and said pattern generation controller (10) is characterized in having that:a program counter (12) for repeatedly generating a frame period (12pset) two level means for generating a select signal (16sel) which defines selection time periods of said two channels of said pattern generator through a coincidence comparator (14) which receives frame period data (12dat) from said program counter (12); and a period counter (18) for providing a number of said frame period repeatedly generated. 3. A bit error measurement system to measure a bit error of a device and has a M channel selectable pattern generator to provide the selected test patterns to a device under test and receive the resultant signals from the device under test to measure a bit error, characterized in that said test pattern generator having:a pattern generator having M selectable channels for pattern generation corresponding to a test pattern received signal (61); a pattern generation controller (10) for controlling the pattern generation by sequentially generating a pattern generation period signal for switching each of said channels of said pattern generator such that while one channel of said pattern generator to be provided to a comparator (65) is selected and generating the test patter, the other channels are waiting for the next pattern generation; switching means for selectively switching reference patterns of a reference pattern generator having M channels of pattern generation when receiving a select signal from a pattern generation controller (10) to provide said reference patterns to said comparator (65); and M channel pattern synchronization parts each of which separately detects a synchronization of said pattern and provides a clock mask signal to a corresponding pattern generator when said pattern is not in said synchronization. 4. A bit error measurement system as defined in claims 1 or 3, wherein said M channels of said pattern generator include at least one word pattern generator and at least one PRBS (pseudo random binary sequence) pattern generator.
5. A bit error measurement system as defined in claims 1 or 3, wherein said word pattern generator (62word) generates word patterns by reading out contents in a memory.
6. A bit error measurement system as defined in claims 1 or 3, wherein said PRBS (pseudo random binary sequence) pattern generator (62word) generates pseudo random patterns.
7. A bit error measurement system characterized in having that:a wide band pattern generation circuit for sequentially multiplexing parallel patterns generated by a pattern generator circuit (113) to form a high speed pattern, said wide band pattern generation circuit having an approach detection circuit (131), a clock switch circuit (128), an intermediate retiming circuit (127) and a clock edge switch circuit which cancels delay times (τ0 +τ1 +,,+τm-1) in said intermediate retiming circuit; and a clock frequency difference detector (150) provided in said wide band pattern generation circuit for counting a frequency of an input clock (111) to detect whether the counted frequency exceeds a predetermined difference from the frequency at a previous phase switching to determine either permit or prohibit a phase switch operation in said clock switch circuit (128). 8. A bit error measurement system as defined in claim 7, wherein said clock frequency difference detector (150) includes:means for counting a frequency (fclk) of an input clock to be used for multiplexing said patterns; means for permitting an automatic switching operation of said clock switch circuit (128), by judging that the bit error measurement system is in a adjustment state, when detecting a frequency difference which is greater than a predetermined value by comparing said frequency (fclk) and a previously measured frequency (156old), and for prohibiting said automatic switching operation of said clock switch circuit (128), by judging that the bit error measurement system is in a measurement state, when said frequency difference is smaller than said predetermined value; and means for holding said previously measured frequency (156old) taken at a time when said automatic switching operation is taken place. 9. A bit error measurement system having a reference pattern generator (262), a comparator (265), a pattern synchronization part (266) and an error counter (270) for measuring bit errors of a signal (261) under test characterized in that:said bit error measurement system has a pattern position recording part which stores address information of said reference pattern generator (262) in memory means when receiving an error detection signal (265a) from said comparator (265). 10. A bit error measurement system having a reference pattern generator (262), a comparator (265), a pattern synchronization part (266) and an error counter (270) for measuring bit errors of a signal (261) under test for every N bit parallel characterized in that:said bit error measurement system has a pattern position recording part which stores address information of said reference pattern generator (262) when receiving an error signal in any one of N bit error detection signals (265a) from said comparator (265) and said N bit error detection signals (265a) in memory means. 11. A bit error measurement system as defined in claims 9 or 10, wherein said reference pattern generator is either a word pattern generator or a PRBS pattern generator or a combination of both of said pattern generators.
FIG. 5 shows an example of a test arrangement for a bit error measurement system. A test pattern signal 71pat and a clock signal 73 from a pattern generator 71 are provided to a DUT 74. The resultant output from the DUT 74 which is a signal 61 to be measured and a clock signal 60 are provided to a bit error measurement apparatus 75 whereby a bit error is measured.
FIG. 6 shows an internal structure of the pattern generator 71. For generating a test pattern to be supplied to the DUT 74, the pattern generator 71 includes a PRBS generator 71prbs which generates a PRBS (pseudo random binary sequence) pattern, and a WORD generator 71word which generates a word pattern based on the contents of a memory. Either one of the patterns is fixedly selected by a multiplexer (MUX) 71m and is provided with a desired amplitude and offset voltage by a buffer amplifier 71buf. Then the test pattern is applied to the DUT 74. The contents of the memory and other conditions for the pattern generation are set in advance through an external CPU (computer) to satisfy the desired test conditions.
Since the position of the pattern sequence in the received signal 61 to be tested from the DUT 74 and the position of the bit sequence from the reference pattern generator 62 are undefined, the measurement apparatus includes a pattern synchronization part 66 for synchronizing pattern positions of both of the bit sequence. A synchronization detection counter 66a in the pattern synchronization part 66 is to detect whether the error rate is less than a predetermined value. For example, the synchronization detection counter 66a counts the number of mismatch bits 65err for a fixed clock time period (for example, for a period of 16,384 clock pulses). A comparison test pulse 66tst is given to a comparator 66c whereby the counted number of mismatch and a threshold value are compared. At the same time, the synchronization detection counter 66a is reset to an initial value to repeat the above detection procedure.
If the results of the comparison is greater than the threshold value from a threshold value register 66b, it is considered that the position of the both bit sequence is still not aligned. Thus, a clock mask signal 67 is provided to the reference pattern generator 62 to suspend the pattern generation for one clock time so as to shift the bit sequence.
With respect to the internal structure of the reference pattern generator 62, the two generators, the PRBS generator 62prbs and the word generator 62word are identical to the generators in the test pattern generator 71 except for the clock mask function where the pattern is shifted by one clock time as noted above. The same type of the pattern generator now used in the pattern generator 71 is set in the reference pattern generator to generate the reference pattern 62pat which is supplied to the comparator 65.
The pattern generator is formed of a pattern generation circuit 113, multiplexing circuits 1141 -114n, an intermediate retiming circuit 127, 1/2 divider circuits 1121 -112n, delay circuits 1151 -115n and 115r, a clock switching circuit 128, and an approach detection circuit 131.
Since it is necessary to correctly multiplex and retime the patterns for any clock rates of this wide range input clock 111, the pattern generator includes the delay circuits 1151 -115n for providing delay times (τ0, τ0 +τ1, τ0 +τ1 +τ2,,, τ0 +τ1 +,,+τm-1, τm, τm+,,+τn-1, τm+,,+τn) to the clock signal equivalent to the delay times caused by propagation delays in the circuit components and wiring between the pattern generation circuit 113 and multiplexing circuits. In such a circuit arrangement, in the past, it is necessary for the delay circuits to have longer delay times in the later stages. Further, high quality clock with less jitters is required since the pattern generator operates in high speed. However, the circuit of FIG. 11 alleviates this requirements by having the intermediate retiming circuit 127, the clock switching circuit 128, and the approach detection circuit 131 to cancel the delay times (τ0 +τ1 +,,+τm-1) in the prior stages.
It is stated in the Japanese patent application Ser. No. 218454-1990 that when a retiming clock for the intermediate retiming circuit 127 approaches too close to a transition point of the input pattern to the retiming circuit 127, a correct retiming will not be available. Thus, the Japanese patent application states, that when the retiming clock and the pattern transition point are too close with each other, that situation is detected by the approach detection circuit 131. Based on the detection signal, a phase of the clock, which is provided to the divider circuits to control the multiplexing operation, is switched. As a result, the delay times (τ0 +τ1 +,,+τm-1) in the prior stages are canceled by the foregoing operation.
FIG. 18(a) is a block diagram of a conventional bit error measurement apparatus for explaining the process of bit error measurement. The bit error measurement apparatus is formed of a reference pattern generator 262, a comparator 265, an error counter 270, a pattern synchronization part 266. The pattern synchronization part 266 is provided for synchronizing patterns between the signal 261 to be measured and the reference pattern generator 262. The pattern synchronization part 266 is formed of a synchronization detection counter 266a, a threshold value register 266b and a comparator 266c.
The pattern synchronization within in this context means that even if bit errors exist to a certain extent in the unknown signal 261 to be measured, synchronization is deemed to be established. In other words, if the error rate is lower than a certain level such as shown in the threshold register 266b, it is deemed to be synchronized. The synchronization detection counter 266a is a counter which counts the number of bit errors for every predetermined time period. After the predetermined time period, the counted value and the data from the threshold register 266b are compared by the comparator 266c. When the comparator 266c detects that the number of bit errors is less than the threshold value, a clock mask signal 267 is no longer generated therefrom.
The reference pattern generator 262, when receiving the clock mask signal 267, delays the output phase of the reference pattern signal 262a by one bit to generate the next reference pattern. This process is continued consecutively until the reference pattern 262a matches with the input signal 261 to be measured. When the reference pattern 262a matches with the input signal, the clock mask signal 267 from the comparator 266c is no longer generated, and thus, the reference pattern 262a is maintained in the synchronized situation. In this manner, a pattern synchronization is established between the signal 261 to be measured and the reference pattern generator 262.
As in the foregoing explanation, the pattern synchronization part 266 generates a clock mask signal when the synchronization state is not reached. The divider 263, in receiving the clock mask signal, suspends a divided clock 263a by one bit. The DEMUX 264 receives the divided clock 263a, and will not fetch the input signal to be measured when the divided clock 263a is suspended. The reference pattern generator maintains the reference pattern 262a when the divided clock 263a is suspended. Therefore, a phase difference between a signal under test at the comparator 265 which is an output signal 264a of the DEMUX and the reference pattern signal 262a shifts corresponding to the time (one bit) during which the divided clock 263a is suspended. The relationship between the DEMUX output 264a and the reference pattern signal 262a in this situation is shown in FIG. 19.
In case where the channel M is 2, the pattern generation controller 10, which selects the pattern generator in real time, includes a program counter (PGC) 12 which repeatedly generates a frame period 12pset. In receiving frame period data 12dat from the PGC counter 12, a coincidence detector 14 generates detection signal which is provide to two state means (such as an SR flip-flop) which generates a select signal 16sel for switching between time periods for multiplexing the two channels of the pattern generator. The pattern generation controller 10 also includes a period counter 18 which provides the number of frames during which the patterns will be repeatedly generated.
As a more specific example, the pattern generator of the present invention preferably includes at least one channel of word pattern generator or at least one channel of PRBS pattern generator. There are two pattern generation modes, one is a word generator 71word which generates a word pattern by reading the contents in a memory and a PRBS generation mode 71prbs which generates a pseudo random pattern.
(4) The word pattern synchronization part 31 receives the select signal 16sel from the pattern generation controller 10, and determines whether the patterns are in the synchronization state in a period Toh for generating a word pattern. If the error rate is greater than a predetermined value, the word pattern synchronization part provides a clock mask signal 31inh to the word pattern generator 62word so as to bring the word pattern into the synchronization state.
(5) Similarly, the PRBS pattern synchronization part 32 receives the select signal 16sel from the pattern generation controller 10, and determines whether the patterns are in the synchronization state in a period Tpayload for generating a PRBS pattern. If the error rate is greater than a predetermined value, the word pattern synchronization part provides a clock mask signal 32inh to the PRBS pattern generator 62prbs so as to bring the word pattern into the synchronization state. Namely, both of the pattern synchronization parts are able to separately, i.e., independently between the word pattern and the PRBS pattern, synchronize the pattern.
Accordingly, a wide range pulse pattern generator is realized in which parallel patterns generated by a pattern generator 113 are sequentially multiplexed to generate a high speed pattern. The pulse pattern generator has an approach detection circuit 131 and a clock switch circuit 128 and an intermediate retiming circuit 127 for canceling the delay times ((τ0 +τ1 +,,+τm-1) in the multiplexing circuits in the prior stages of the intermediate retiming circuit 127 by automatically changing the clock edges. The wide range pulse pattern generator of the present invention avoids the unstable operation in the measurement state of the bit error measurement system.
In the frequency difference detector 150, means for measuring a frequency fclk is provided for comparing the frequency fclk and a previous frequency 156old. The frequency difference detector 150 further includes means for prohibiting and allowing the switching operation of the clock switch circuit 128. If the detected frequency difference is greater than a predetermined value, it is determined that the measurement system is in the adjustment state and thus allows the clock switch circuit 128 its automatic switching operation. In contrast, when the frequency difference is smaller than the predetermined value, it is deemed that the system is in the measurement state and thus prohibits the clock switch circuit 128 its automatic switching operation. The frequency difference detector 150 also includes means for holding the frequency value 156old which is a frequency when the clock phase is automatically switched to other clock phase.
To solve the problem, the invention of FIG. 12 includes a pattern position recording part 210 which stores the information regarding the position of the reference pattern generation of a reference pattern generator 262 in a memory 220 when a comparator 265 sends a error detection signal 265a.
To solve the problem, the invention of FIG. 15 includes a pattern position recording part 230 which stores the information regarding the position of the reference pattern generation of the reference pattern generator 262 in a memory 220 when it received either one of N bit error detection signals 265b from a comparator 265. The memory 220 stores both the reference pattern position information and the error detection signal 265b.
FIG. 19 is a diagram showing relationship between a DEMUX 264a and a reference pattern signal 262a concerning the third invention.
For generating this type of test patterns, a bit error test pattern generator of the present invention includes a pattern generation controller 10 as shown in FIG. 1 in addition to the conventional structural components. A PRBS generator 62prbs, a word generator 62word, a multiplexer (MUX) 62m, and a buffer amplifier 62buf are basically the same as that in the conventional technology. However, each of the PRBS generator 62prbs and the word generator 62word has a function of suspending the pattern generation.
The program counter 12 is a counter for down counting by repeatedly presetting the frame period 12pset for every borrow signal 12bor. The program counter 12 generates predetermined frame period data 12dat by counting a clock signal 72. The frame period 12pset is set by an external CPU to meet with desired frame periods.
The set reset flip-flop (SRFF) 16 produces a select signal as shown in FIG. 4 which switches two pattern generators in a frame period. When receiving the frame period data 12dat from the program counter 12, the coincidence comparator 14 detects time data for the 9 byte of the overhead OH and changes the set reset flip-flop 16 to a set state.
When receiving the borrow signal 12bor from the program counter 12, the set reset flip-flop 16 is changed to a reset state. The select signal 16sel thus produced at the output of the flip-flop is provided to the multiplexer 62m. The input patterns are multiplexed in real time by the multiplexer 62m and are provided to the buffer amplifier 71buf. The select signal is also provided to the PRBS generator 62prbs and an address counter 62ctr in the word generator 62word to alternately suspend the pattern generation in the generators.
In this manner, the pattern generator selected by the multiplexer 62m operates while the other pattern generator is in a temporarily waiting state. By alternately repeating this process, the test pattern which is a multiplex of both of the patterns is generated by the pattern generator.
The period counter 18 is to repeat the overhead period for N frame times. The period counter 18 receives the borrow signal 12bor from the program counter 12 to count down the contents. By a borrow signal 181d from the counter 18 is provided to a load input of the address counter 62ctr to set the counter 62ctr to an initial value. The period counter 18 repeats this process by setting itself to an initial value 9�N by the borrow signal 181d. Here, the initial values or the value applied to the coincidence comparator 14 are freely set by the external CPU to form a desired interval of the N frames.
Similar to the bit error test pattern generator 20, a pattern generation controller 10 in the reference pattern generator 34 controls to generate a multiplexed pattern signal 34pat which is provided to one input terminal of a comparator 65.
One synchronization detection path includes the word pattern synchronization part 31. The word pattern repeats for every N frames. The operation of detecting a synchronization position is different from that of the conventional one in that it operates only in the word detection period TOH. Namely, a synchronization detection counter 66a is enabled only during the high level range of the select signal 16sel from the pattern generation controller 10. As in the conventional technology, when the error rate is higher than a predetermined value, a clock mask signal 31inh is provided to the word pattern generator 62word to shift the pattern generation by one clock period. When the error rate reaches the predetermined value, it is deemed that the word pattern reaches the synchronization state and the synchronization detection operation is suspended. Thus, the word pattern synchronization part generates a synchronization detection signal 31sync.
The other synchronization detection path includes the PRBS pattern synchronization part 31. Similar to the description above, the operation of detecting a synchronization position is performed only during the low level range of the select signal 16sel from the pattern generation controller 10. When the error rate is higher than a predetermined value, a clock mask signal 32inh is provided to the PRBS pattern generator 62prbs to shift the pattern generation by one clock period. When the error rate reaches the predetermined value, it is deemed that the PRBS pattern reaches the synchronization state and the synchronization detection operation is suspended, and as a result, a synchronization detection signal 32sync is generated.
The AND gate 170 is connected between the output of a comparator 134 and a clock input of a T flip-flop 135 to prohibit the operation of the T-type flip-flop 135. The clock frequency difference detector 150 receives an intermediate speed clock signal 150in which is a clock signal produced by dividing the input clock to detect the frequency changes. The output signal of the clock frequency difference detector 150, i.e., a phase switch enable signal 160enb, is provided to one input terminal of the AND gate 170 to either allow or prohibit the phase switch operation.
The frequency difference detector 150 measures a frequency of the input clock 111 for every fixed time period, and compares the measured data with the original frequency value. If the frequency change is greater than a predetermined value, the phase switch enable signal 160enb is generated to enable the switch operation of the clock switch circuit 128. The clock frequency difference detector 150 is formed of a reference gate time generator 152, a pulser 153, a frequency counter 154, a count value latch register 156, a subtractor 158, a comparator 159, flip-flops 160, 161, an exclusive NOR (EXNOR) gate 162 and an AND gate 163.
The reference gate time generator 152 is a 16 bit divider to provide a reference gate time to the frequency counter 154 as a count time. The reference gate time generator 152 receives a reference clock 151 (10 MHZ for example) and divides the reference clock 151 by a predetermined division rate 152div to repeatedly produce a divided time signal 152gate. The divided time signal 152gate is provided to an enable terminal of the frequency counter 154 and the pulser 153. Here, the division rate 152div is set freely by the CPU (computer) which is determined such that the 16 bit divider will not overflow in response to the frequency of the intermediate clock signal 150in and the count value will satisfy the desired resolution (0.2% for example).
The pulser 153 is to form a pulse signal 153pls based on the divided time signal 152gate. The pulse signal 153pls is provided to a reset input of the frequency counter 154, clock inputs of the flip-flops 160 and 161, and one input terminal of the AND gate 163.
The frequency counter 154 is a counter for counting the intermediate speed clock signal 150in. When receiving the pulse signal 153pls, the frequency counter 154 resets to an initial value 0, then counts the number of clocks of the intermediate speed clock signal 152in during the high level period of the divided time signal 152gate. During the period when the divided time signal 152gate is in the low level, the counted value 152cnt is maintained and is supplied to one input of the subtractor 158 and to the count value latch register 156.
The subtractor 158 subtracts the previous frequency value 156old held in the count value latch register 156 from the count value 152cnt from the frequency counter 154. The resultant subtracted value 158sub is supplied to one input of the comparator 159.
The comparator 159 compares the subtracted value 158sub and a comparison value 157cmp, and if the subtracted value 158sub is greater than the comparison value 157cmp, the comparator 159 provides a high level signal to an input of the flip-flop 160. The comparison value 157cmp is a value freely set by the CPU, and is set in advance, for example, to a value which is 2-5% different from the intermediate speed clock signal 150in.
The flip-flop 160 latches the output signal of the comparator 159 and outputs a phase switch enable signal 160enb to one input of the AND gate 170 so as to inhibit the operation of the clock switch circuit 128. When the phase switch enable signal is in the high level, the system is in the adjustment state and thus operation of the clock switch circuit 128 is allowed. When the phase enable signal is in the low level, the system is in the measurement state, and thus the operation of the clock switch circuit 128 is prohibited.
To renew the count value latch register 156, a load pulse signal 1561d is produced by the flip-flop 161, the exclusive OR gate 162 and the AND gate 163. More particularly, the flip-flop 161 shifts the signal from the flip-flop 160 to hold the phase switch enable signal 160enb of the previous cycle. Both of the phase switch enable signals are input to the exclusive OR gate 162 so as to determine whether there is any change between the present and previous signals. The output of the exclusive OR gate 162 is provided to the count value latch register 156 through the AND gate 163. Thus, the count value 154cnt is renewed and held in the count value latch register 156 as data for the next comparison.
As in the foregoing, by setting the division value 152div and the comparison value 152cmp to appropriate values, when the rate of frequency change of the input clock 111 is detected to be smaller than the predetermined value (for example, 2-5% frequency ratio), the switch operation of the clock switch circuit 128 is automatically enjoined. As a consequence, a stable wide band pulse pattern generator is accomplished by effectively preventing the unstable operation in the measurement state.
In the foregoing explanation of the embodiment, the input clock signal for the clock frequency difference detector 150 is obtained by the divided clock taken from a 1/2 divider circuit 112n-m as the intermediate speed clock signal 150in. Since it is only necessary to count the input clock 111, it is also possible to directly count the input clock 111. Alternatively, to receive the clock signal from the other 1/2 divider by setting the division value 152div accordingly.
Further, it may be preferable to provide an indicator on a display panel to show the state of the phase enable switch signal 160enb which shows the output state of the flip-flop 160.
In the case of using the word pattern generator 251, the address information is a address signal 251adr itself for the word pattern generator 251. This address signal 251adr (for example, 18 bit length) is provided to a data input of the memory 220.
In receiving a bit error signal 265a from the comparator 265, the error signal is formatted to a pulsed signal by a clock 260 at the gate 212 and is provided to a write enable input of the memory 220. As a consequence, for every bit error, the address information of the pattern position in the word pattern generator 251 is stored in the memory 220.
After acquiring the address information, the CPU reads the contents in the memory 220 and displays address caused the bit errors in various display modes. For example, the error distribution for every fixed address interval is shown in a histogram form of FIG. 14 so that the error analysis, such as to determine as to which position of the reference pattern 262a has caused the error, is easily carried out.
In the case of using the PRBS pattern generator 252, one bit is not enough to show the information of the pattern position of the reference pattern. Thus, in receiving a bit stream 265prbs of the PRBS pattern sequence, the bit stream is converted to n bit parallel data which is deemed to be address information and is provided to a data input of the memory 220. The length of the address information in this case needs a length corresponding to the number of stages in the PRBS. For example, in case where the PRBS has 31 maximum stages, the parallel bit length of the address information must be n=31.
Therefore, in receiving a bit stream 265prbs of the PRBS pattern sequence, the shift register 218 converts the bit stream to 31 bit parallel data. This parallel information is provided to the data input of the memory 220. The remaining operation of the pattern position recording part 210 is the same as described with respect to that of the word pattern generator 251.
As shown in FIG. 16(a), a pattern position recording part 230 for the word pattern generator 251 is basically the same as explained in the above with respect to the serial process. Therefore, if an OR gate 215 detects an error in any bit out of the parallel 16 bits of the bit error detection signal 265b, a gate 212 produces a write enable pulse. A divided clock 263a is a clock produced by dividing the clock 260. The bit error detection signal 265b which is a 16 bit parallel signal is directly provided to a data input of a memory 220. Also, the address signal 251adr of the word pattern generator 251 is provided to a data input of the memory 220. Thus, both data are stored in the memory 220. The other operations are the same as that of the serial process.
As shown in FIG. 16(b), when the pattern generator is the PRBS pattern generator 252, a pattern position recording part 230 needs to store the PRBS address 218adr which is the maximum address length, i.e., n=31 bits, for example, in the memory 220. Thus, the pattern position recording part 230 includes a shift register 218. Other operations are the same as in the serial process.
The word pattern synchronization part 31 receives the select signal 16sel from the pattern generation controller 10, and determines whether the patterns are in the synchronization state in a period Toh for generating a word pattern. If the error rate is greater than a predetermined value, the word pattern synchronization part provides a clock mask signal 31inh to the word pattern generator 62word so as to bring the word pattern generator into the synchronization state.
Similarly, the PRBS pattern synchronization part 32 receives the select signal 16sel from the pattern generation controller 10, and determines whether the patterns are in the synchronization state in a period Tpayload for generating a PRBS pattern. If the error rate is greater than a predetermined value, the word pattern synchronization part 32 provides a clock mask signal 32inh to the PRBS pattern generator 62prbs so as to bring the PRBS pattern generator into the synchronization state. Namely, both of the pattern synchronization parts are able to separately, i.e., independently between the word pattern and the PRBS pattern, synchronize the patterns.
The pattern position recording part 210 stores the information regarding the reference pattern generation of the reference pattern generator in the memory 220 when the comparator sends the error detection signal 265a. The information regarding the reference pattern position is the address of the word pattern generator when the word pattern generator 251 is used. In contrast, when using the PRBS pattern generator 252, the information regarding the reference pattern position is the n bit parallel data which has been converted from the bit stream 265prbs of the PRBS pattern.
The pattern position recording part 230 stores the information regarding the reference pattern generation of the reference pattern generator and as well as the N bit parallel error detection signals 265b in the memory so that the information on which position of the error in the N bit can be specified.
In this arrangement, according to the present invention, the position of the reference pattern 262a which caused the error can be specified, which further facilitates the bit error analysis.
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