Source: http://www.google.com/patents/US7364784?dq=5927278
Timestamp: 2016-06-30 07:57:41
Document Index: 173009753

Matched Legal Cases: ['art 26', 'art 26', 'arts 28', 'arts 28', 'arts 28', 'art 26', 'arts 28', 'art 26', 'arts 28', 'arts 28', 'art 26', 'arts 28', 'arts 28', 'art 26', 'art 26', 'art 26', 'Application No. 10']

Patent US7364784 - Thin semiconductor package having stackable lead frame and method of ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsProvided is a thin semiconductor package comprising a semiconductor chip and a lead frame, the lead frame including a paddle portion configured for mounting the semiconductor chip in a manner that exposes bonding pads within an aperture formed in a center portion of the lead frame and a peripheral terminal...http://www.google.com/patents/US7364784?utm_source=gb-gplus-sharePatent US7364784 - Thin semiconductor package having stackable lead frame and method of manufacturing the sameAdvanced Patent SearchPublication numberUS7364784 B2Publication typeGrantApplication numberUS 10/834,187Publication dateApr 29, 2008Filing dateApr 29, 2004Priority dateAug 23, 2003Fee statusLapsedAlso published asUS7615859, US20050054141, US20080164586Publication number10834187, 834187, US 7364784 B2, US 7364784B2, US-B2-7364784, US7364784 B2, US7364784B2InventorsJin-Ho Kim, Sung-Hwan YoonOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (6), Non-Patent Citations (1), Referenced by (6), Classifications (35), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetThin semiconductor package having stackable lead frame and method of manufacturing the same
US 7364784 B2Abstract
preparing a lead frame blank from a conductive material, the lead frame blank having a substantially uniform blank thickness TB;
removing a portion of the conductive material from a mounting region to form a recess of substantially uniform depth TR0, a substantially planar thinned region having thickness TP and a terminal region having a thickness TT, wherein TB is substantially equal to TR0+TP and TT is substantially equal to TB;
repositioning a central portion of the thinned region within the recess to form a substantially planar paddle region having a upper surface and a lower surface, such that an overall thickness of the lead frame is substantially equal to TB and to form a second recess having a depth TRU between the upper surface of the paddle region and an upper surface of the terminal region and a third recess having a depth TRL between the lower surface of the paddle region and a lower surface of the terminal region, wherein TRU>TRL;
removing a central region of the paddle region;
preparing a semiconductor chip having an active surface and a backside surface, a plurality of bonding pads being arrayed on the active surface;
mounting a portion of the active surface to the paddle region with the bonding pads exposed, which includes forming an adhesive region on an upper surface of the paddle region;
removing a central region of the paddle region, and mounting the active surface of the semiconductor chip on the adhesive region;
providing bonding wires between the bonding pads and corresponding leads to establish a plurality of electrical connections; and
encapsulating the semiconductor chip, the bonding wires and a portion of the lead frame with a polymeric material, the polymeric material having a maximum thickness approximately equal to TB and exposing upper and lower surfaces of the terminal region to form the semiconductor device package.
2. A method of manufacturing a lead frame according to claim 1, wherein:
a ratio of TRU:TRL is between about 2:1 and about 5:1.
3. A method of manufacturing a lead frame according to claim 1, wherein:
the paddle region is connected to the terminal region by an intermediate region having a thickness TI that is approximately equal to TP and wherein a portion of the intermediate region is inclined relative to both a first plane defined by the upper surface of the paddle region and a second plane defined by an upper surface of the terminal region.
4. A method of manufacturing a lead frame according to claim 3, wherein:
a portion of the intermediate region adjacent the terminal region has an upper surface that is substantially coplanar with the upper surface of the terminal region.
5. A method of manufacturing a lead frame according to claim 3, wherein:
forming leads includes forming an etch mask pattern and removing portions of the paddle region, the intermediate region and the terminal region to form a plurality of electrically isolated leads.
6. A method of manufacturing a lead frame according to claim 3, wherein:
forming leads includes forming an etch mask pattern and removing portions of the thinned region and the terminal region before forming the paddle region.
7. A method of manufacturing a lead frame according to claim 1, wherein:
the paddle region is connected to the terminal region by an intermediate region having a thickness TI less than TP and wherein a portion of the intermediate region is inclined relative to both a first plane defined by the upper surface of the paddle region and a second plane defined by an upper surface of the terminal region.
8. A method of manufacturing a lead frame according to claim 7, wherein:
TI is no less than about 75% of TP.
9. A method of manufacturing a lead frame according to claim 7, wherein:
10. A method of manufacturing a semiconductor device package according to claim 1, wherein:
the polymeric material has
an upper surface that is in a substantially planar orientation with the upper surface of the terminal region; and
a lower surface that is in a substantially planar orientation with the lower surface of the terminal region.
11. A method of manufacturing a stacked semiconductor device package comprising:
preparing first and second semiconductor device package according to claim 10;
providing a conductive connector on the upper surface of the terminal region of the first semiconductor device package;
stacking the second semiconductor package on the first semiconductor package whereby the conductive connector provides electrical contact between the terminal region of the first semiconductor device package and a corresponding terminal region of the second semiconductor device; and
encapsulating the stacked first and second semiconductor device packages with a second polymeric material, whereby at least the lower surface of the terminal region of the first semiconductor device package is exposed.
12. A method of manufacturing a stacked semiconductor device package according to claim 11, wherein:
the conductive connector is selected from a group consisting of a solder paste, solder balls and a conductive polymeric composition.
13. A method of manufacturing a stacked semiconductor device package according to claim 11, further comprising:
providing an insulating adhesive layer between the upper surface of the polymeric material of the first semiconductor device package and the lower surface of the polymeric material of the second semiconductor device package, the adhesive layer acting to maintain the relative orientation of the semiconductor device packages.
14. A method of manufacturing a stacked semiconductor device package according to claim 11, wherein:
the second polymeric material has a lower surface that is in a substantially planar configuration with the lower surface of the terminal region of the first semiconductor device package.
15. A method of manufacturing a stacked semiconductor device package according to claim 1, wherein:
removing the portion of the conductive material from the mounting region to form the recess of substantially uniform depth includes
forming a photoresist pattern that exposes the mounting region of the lead frame blank;
etching the mounting region of the lead frame blank to a predetermined depth using the photoresist as a etching mask; and
As illustrated in FIG. 2, a lead frame 20 having a predetermined thickness TB is prepared. The lead frame 20 should be thick enough to form a terminal pad for connecting to an external terminal, and a paddle part where a semiconductor chip will be mounted. For example, 200 μm is an appropriate thickness for the lead frame 20. The lead frame 20 can be formed from conductive metal, typically an alloy such as a copper (Cu) based alloy or an iron-nickel (Fe—Ni) based alloy. If the lead frame 20 is formed from a Fe—Ni alloy, a suitable alloy composition may include about 42 wt % Ni and about 58 wt % Fe. A photoresist pattern 22 may then be formed on the lead frame 20 to expose a central region on the lead frame 20. As illustrated in FIG. 3, a portion of the exposed central region of the lead frame 20 is removed using a suitable etch process to form a recess 24 in the lead frame using photoresist pattern 22 as an etch mask. As illustrated in FIG. 3, more than one half of the thickness of the lead frame 20 may be removed during the etch process, in this instance about 150 μm, to form a recess 24 having a predetermined depth and, correspondingly, leave a suitable thickness of the lead frame 20 for subsequent processing.
As illustrated in FIG. 4, a portion of the lead frame in the thinned central region 20 a of the lead frame 20 may be pressed back into the recess to form paddle part 26 on which a semiconductor chip may be mounted and intermediate leads 30 having a thickness TI that connect the paddle part 26 to the terminal pad parts 28. An edge portion of the thinned central region 20 a that is not pressed back into the recess 24 may be used to form an inner protrusion portion 28 b of terminal pad parts 28 with the outer portion 28 a of the terminal parts being formed from the full thickness edge portions 20 b of the lead frame 20, and inclined intermediate leads 30 formed between the terminal pad parts 28 and the paddle part 26. The completed terminal pad parts 28 include both a plain portion 28 a that defines the periphery of lead frame 20 and a protrusion portion 28 b that protrudes inwardly from the plain portion 28 a. The protrusion portions 28 b provide electrical connection between the plain portions 28 a of the terminal pads and the corresponding intermediate leads 30.
As illustrated in FIG. 4, the upper surface 26 a of the paddle part 26 may be recessed relative to the upper surfaces of the terminal pad parts 28 by a first distance TRU equal to more than one half the depth of the original recess 24. Preferably, the lower surface 26 b of the paddle pad 26 will, in turn, also be recessed relative to the lower surfaces of the terminal pad parts 28 by a second distance TRL, the second distance typically being smaller than the first distance. For example, the upper surface 26 a of the paddle part 26 may be recessed about 100 μm relative to the upper surfaces of the terminal pad parts 28 while the lower surface 26 b of the paddle part may be recessed about 50 μm relative to the lower surfaces of the terminal pad parts 28.
Next, as illustrated in FIG. 4, a layer of one or more adhesive agents 32 may be applied to a bonding region on the upper surface 26 a of the paddle part 26 to allow a semiconductor chip to be attached to the paddle part. The thickness of the adhesive may be approximately 20′ μm. An alternative to applying adhesive to the paddle part 26 is to provide adhesive regions on the active surface of the semiconductor chip with the adhesive regions contacting the paddle part 26 as the semiconductor chip is mounted on the lead frame. The adhesive(s) may be applied as a liquid using a variety of conventional materials and processes or may be applied as a solid such as adhesive tape.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5428248Aug 15, 1994Jun 27, 1995Goldstar Electron Co., Ltd.Resin molded semiconductor packageUS5454905 *Aug 9, 1994Oct 3, 1995National Semiconductor CorporationMethod for manufacturing fine pitch lead frameUS6337510 *Nov 17, 2000Jan 8, 2002Walsin Advanced Electronics LtdStackable QFN semiconductor packageUS6878570 *Jul 29, 2004Apr 12, 2005Samsung Electronics Co., Ltd.Thin stacked package and manufacturing method thereofJPH10200039A Title not availableKR20010064914A Title not available* Cited by examinerNon-Patent CitationsReference1Korean Office Action dated Oct. 31, 2005 for KR Application No. 10-2003-0058508 and translation.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7829988 *Sep 22, 2008Nov 9, 2010Fairchild Semiconductor CorporationStacking quad pre-molded component packages, systems using the same, and methods of making the sameUS7855439Dec 21, 2010Fairchild Semiconductor CorporationMolded ultra thin semiconductor die packages, systems using the same, and methods of making the sameUS8314499Nov 14, 2008Nov 20, 2012Fairchild Semiconductor CorporationFlexible and stackable semiconductor die packages having thin patterned conductive layersUS20100052119 *Mar 4, 2010Yong LiuMolded Ultra Thin Semiconductor Die Packages, Systems Using the Same, and Methods of Making the SameUS20100072590 *Mar 25, 2010Yong LiuStacking Quad Pre-Molded Component Packages, Systems Using the Same, and Methods of Making the SameUS20100123257 *Nov 14, 2008May 20, 2010Yong LiuFlexible and Stackable Semiconductor Die Packages, Systems Using the Same, and Methods of Making the Same* Cited by examinerClassifications U.S. Classification428/123, 257/E23.05, 257/E23.047, 257/E23.039, 257/E23.004, 438/112, 257/E23.124, 257/E25.023, 257/E23.043, 438/106International ClassificationH01L21/44, H01L23/495, H01L21/784, H01L23/31, H01L25/10, H01L23/12Cooperative ClassificationY10T428/24207, H01L2924/07802, H01L24/48, H01L2225/1029, H01L2225/1058, H01L23/4951, H01L23/49551, H01L2224/4826, H01L2224/48091, H01L25/105, H01L2224/48247, H01L2924/01079, H01L23/3107, H01L2224/32245, H01L2224/73215European ClassificationH01L23/495G4B, H01L25/10J, H01L23/31H, H01L23/495A4Legal EventsDateCodeEventDescriptionApr 29, 2004ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, JIN-HO;YOON, SUNG-HWAN;REEL/FRAME:015282/0872Effective date: 20040316Dec 12, 2011REMIMaintenance fee reminder mailedApr 29, 2012LAPSLapse for failure to pay maintenance feesJun 19, 2012FPExpired due to failure to pay maintenance feeEffective date: 20120429RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services