Source: http://www.google.com/patents/US5963729?dq=6317900
Timestamp: 2017-05-26 07:50:07
Document Index: 290569370

Matched Legal Cases: ['Application No. 5', 'Application No. 5', 'Application No. 6', 'Application No. 5', 'Application No. 5', 'Application No. 6']

Patent US5963729 - Method for automated electromigration verification - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping...http://www.google.com/patents/US5963729?utm_source=gb-gplus-sharePatent US5963729 - Method for automated electromigration verificationAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS5963729 APublication typeGrantApplication numberUS 08/882,986Publication dateOct 5, 1999Filing dateJun 26, 1997Priority dateJun 26, 1997Fee statusPaidPublication number08882986, 882986, US 5963729 A, US 5963729A, US-A-5963729, US5963729 A, US5963729AInventorsSandeep A. Aji, Manjunath Doreswamy, Georgios KonstadinidisOriginal AssigneeSun Microsystems Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (12), Non-Patent Citations (10), Referenced by (30), Classifications (9), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetMethod for automated electromigration verification
US 5963729 AAbstract
An automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.
1. A computer-implemented method for detecting electromigration violations in an integrated circuit design, the integrated circuit design having a functional hierarchy including a plurality of top-most level functional blocks each containing a plurality of functional cells, a plurality of external networks each interconnecting two or more of the top-most level functional blocks and together with the interconnected top-most level functional blocks forming a plurality of top-level nets, and further including a plurality of internal networks each contained within a respective one of the top-most level functional blocks and each interconnecting two or more functional cells within the respective one top-most level functional block, each of the external and internal networks including conductive signal traces and each of the functional cells having a drive strength associated therewith, said method comprising:providing electromigration process rules for conductive signal traces of the integrated circuit design; obtaining parasitic resistance and parasitic capacitance values for each conductive signal trace of the integrated circuit design; propagating upward within the functional hierarchy the parasitic resistance and capacitance values of the conductive signal traces of the integrated circuit design; determining a lumped resistance, a lumped capacitance and a lumped drive strength of each of the top-most level functional blocks; determining a lumped resistance and lumped capacitance for each external network; calculating at least one current value for each top-level net from the lumped resistance, the lumped capacitance and the lumped drive strength of the external networks and the top-most level functional blocks interconnected thereby; determining minimum electromigration dimensions for the conductive signal traces of the integrated circuit design based on the at least one current value and said electromigration process rules for each of the top-level nets; determining design dimensions of the conductive signal traces of the integrated circuit design; comparing the design dimensions with the minimum electromigration dimensions; and identifying violations of the fabrication process rules for the conductive signal traces of the integrated circuit when the design dimensions are less than the minimum electromigration dimensions. 2. A computer implemented method as claimed in claim 1, wherein the at least one current value indicates a peak current, and average current and an rms current of each top-level net.
At least one automated tool exists for checking power lines of an integrated circuit design against process rules for electromigration violations. PowerMill™ by Epic Design Technology, Inc. of Santa Clara, Calif. is such a product. However, since power lines tend to be in known locations with known current loads, the checking with respect to power lines can be accomplished. Nevertheless, the automated tool is unable to check signal lines against process rules for electromigration violations.
Broadly speaking, the invention is directed to an automated system for detecting electromigration violations in signal lines of an integrated circuit design to fabricated. The automated system checks conductive traces (e.g., wires), vias and/or contacts that are used to route signals to and from various functional cells within the integrated circuit design against predetermined process rules to detect electromigration violations. The automated method and system according to the invention are able to find all electromigration violations and thus provides complete coverage which is far superior to conventional manual approaches.
The above and other objects and advantages of the present invention will be readily understood by the following detailed description, with reference to the accompanying drawings, in which:
The invention pertains to an automated system for detecting electromigration violations in signal lines of an integrated circuit design to be fabricated. The automated system checks conductive traces (e.g., wires), vias and/or contacts that are used to route signals to and from various functional cells within the integrated circuit design against predetermined process rules to detect electromigration violations.
FIG. 7 conceptually illustrates the results of steps 503-508 described above as applied to the example of the net of FIG. 6. In this drawing, DA is the collapsed drive strength of functional block A; CA, CB and CC are the lumped capacitances of the respective functional blocks A, B and C; CEXT is the lumped capacitance of the external net portion of the net; RA, RB and RC are the lumped resistances of the respective blocks A, B and C; and REXT is the lumped resistance of the external net. This information is used to devise a uniform RC model for the interconnection that is equivalent to an RC distributed model that is more accurate than the simple lumped model.
In a next step 509, all lumped drives D are collected to determined a single drive strength DNET for the top-level net. Similarly, CA, CB, CC and CEXT are lumped to obtain a single lumped capacitance CNET for the top-level net. Finally, RA, RB, RC and REXT are lumped to obtain a single lumped resistance RNET for the top-level net. This is also conceptually shown in FIG. 7, where DNET, CNET and RNET for the top-level net are obtained.
In a preferred embodiment, the DNET, CNET and RNET values for all of the top-level nets are obtained prior to advancing to the layout phase of the process. Thus, at a step 510, a determination is made as to whether the parasitics for all the top-level nets have been determined, and if not, the process returns to step 502 to subject another one of the top level nets to the parasitic analysis. Once all the DNET, CNET and RNET values have been determined for each top-level net, these are stored as multiple net data structures of the top-level hierarchy of the chip layout. The process is now ready to proceed to the layout check executed by the layout processor 102b of FIG. 1.
At step 511, DNET, CNET and RNET are retrieved for a selected one of the top-most level nets. These values were obtained in Steps 501-510 above.
The EM tool of the invention is used to check for peak current Ip, average current Iavg and rms current Irms related EM violations on each net. Step 512 is directed to calculating these values which may be readily obtained from DNET, CNET and RNET. The peak current is calculated by an analytical expression that includes the influence of the interconnect series resistance.
Next, each of the wires within the net are checked for electromigration violations. Initially, wire data for a first wire is retrieved at step 513. Preferably, the wire data is retrieved from the layout file 104. For all the wires of the integrated circuit design, the thickness is assumed to be a predetermined thickness, and the width of the wires varies with the integrated circuit design but is indicated in the wire data. A minimum wire width for the peak current Ip, average current Iavg and rms current Irms is then determined in step 514. Here, the peak current Ip, average current Iavg and rms current Irms are preferably indexed into the rules table to obtain the minimum wire width.
Next, a minimum contact size for the peak current Ip, average current Iavg and rms current Irms is determined at step 520. Here, the peak current Ip, average current Iavg and rms current Irms are preferably used to index into the rules table 112 to obtain the minimum contact size. At step 521, a determination is made as to whether the contact size of the contact is greater than the minimum contact size. If not, the contact is identified at step 522 as having an electromigration violation. For example, if the contact size is one regular contact and the minimum size is two regular contacts (i.e., a double contact), then there is a violation of the process rules pertaining to electromigration. On the other hand, if the contact size of the contact is greater than or equal to the minimum contact size, then the contact is deemed not to have an electromigration error.
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