Source: https://patents.google.com/patent/US20030209802?oq=5754119
Timestamp: 2018-03-22 14:30:56
Document Index: 51088752

Matched Legal Cases: ['Application No. 2002', 'art 1', 'art 2', 'art 3', 'art 4', 'art 1', 'art 2', 'art 3', 'art 4', 'art 1', 'art 2', 'art 3', 'art 36', 'art 36', 'art 36', 'art 36']

US20030209802A1 - Semiconductor device and method for fabricating the same - Google Patents
US20030209802A1
US20030209802A1 US10435471 US43547103A US20030209802A1 US 20030209802 A1 US20030209802 A1 US 20030209802A1 US 10435471 US10435471 US 10435471 US 43547103 A US43547103 A US 43547103A US 20030209802 A1 US20030209802 A1 US 20030209802A1
US10435471
US6800886B2 (en )
The semiconductor device comprises insulation films 30 a-30 f formed on a semiconductor substrate 10, and a thermal conductor 42 buried in the insulation films. The thermal conductor is formed on a tube structure of carbon atoms. The thermal conductor is formed on a tube structure of carbon atoms, which is a material of very high thermal conductivity, can effectively radiate heat of a very high generated in semiconductor elements, etc., such as transistors 24 a , 24 b, etc. Accordingly, the semiconductor device can have good heat radiation characteristics.
This application is based upon and claims priority of Japanese Patent Application No. 2002-136708, filed on May 13, 2002, the contents being incorporated herein by reference.
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically a semiconductor device having good heat radiation characteristics and a method for fabricating the semiconductor device.
The integration degree of semiconductor integrated circuits, such as LSI, etc. has continuously increased in accordance with Moore's law, and the requirement of increases of the computation speed more increases the calories per a unit volume. Accordingly, thermal measurements for the semiconductor integrated circuits are an important problem.
Heating in a semiconductor integrated circuit is more serious when an SOI (Silicon on Insulator) substrate is used as the substrate. This is because the SOI substrate includes an insulation film between the substrate and a semiconductor layer, which makes it difficult to radiate from the side of the substrate the heat generated in the semiconductor elements formed on the semiconductor layer.
The thermal measurements are an important problem also in single transistors of high output powers used in base stations, etc. of portable telephones. This is because the heating deteriorates the performances and lowers the reliability.
In semiconductor integrated circuits and transistors of high output powers, the heat radiation has been conventionally performed by adding heat radiator plates or forced cooling mechanisms, as of fin-type air cooling, water cooling or others.
However, in semiconductor integrated circuits, the thermal radiation is hindered by a number of inter-layer insulation films of low thermal conductivity hinders laid on the semiconductor substrates. In high output power transistors using compound semiconductors, the heat radiation is hindered by the protection films of low thermal conductivity. Even with the heat radiator plates or forced cooling mechanisms added, it has been difficult to make the heat radiation efficiency sufficient.
A technique of providing large openings on the side of the backsides of the semiconductor substrates for the heat radiation through the openings is proposed. However, it is not always easy to provide large openings on the side of the backsides of the semiconductor substrates. This incurs fabrication step increase and resultantly is a factor for cost increase.
An object of the present invention is to provide semiconductor device which can realize good heat radiation characteristics without incurring large cost increase, and a method for fabricating the semiconductor device.
According to one aspect of the present invention, there is provided a semiconductor device comprising: an insulation film formed on a semiconductor substrate; and a thermal conductor buried in the insulation film, the thermal conductor being formed of a self-assembled tube structure of carbon atoms.
According to another aspect of the present invention, there is provided a semiconductor device comprising a thermal conductor buried in a semiconductor substrate, the thermal conductor being formed of a tube structure of carbon atoms.
According to further another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming an insulation film on a semiconductor substrate; and forming an opening in the insulation film; and growing a thermal conductor of a tube structure of carbon atoms in the opening.
According to further another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming an opening in a semiconductor substrate; and growing a thermal conductor of a tube structure of carbon atoms in the opening.
According to the present invention, heat is radiated by means of the thermal conductors of carbon nanotubes, whose is a material of very high thermal conductivity, whereby heat generated in the semiconductor elements, the transistors, etc., can be effectively radiated. Accordingly, the semiconductor device according to the present invention can have good heat radiation characteristics.
[0015]FIGS. 1A and 1B are views of the semiconductor device according to a first embodiment of the present invention.
[0016]FIG. 2 is a graph of the thermal conductivities of iron, silver and diamond.
[0017]FIG. 3 is a graph of relationships between diameters of carbon nanotubes and thermal conductivities.
[0018]FIGS. 4A and 4B are sectional views of the semiconductor device according to the first embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 1).
[0019]FIGS. 5A and 5B are sectional views of the semiconductor device according to the first embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 2).
[0020]FIGS. 6A and 6B are sectional views of the semiconductor device according to the first embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 3).
[0021]FIG. 7 is sectional views of the semiconductor device according to the first embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 4).
[0022]FIG. 8 is a sectional view of the semiconductor device according to a second embodiment of the present invention.
[0023]FIGS. 9A to 9C are sectional views of the semiconductor device according to the second embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which explain the method (Part 1).
[0024]FIGS. 10A to 10C are sectional views of the semiconductor device according to the second embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which explain the method (Part 2).
[0025]FIGS. 1A and 11B are sectional views of the semiconductor device according to the second embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which explain the method (Part 3).
[0026]FIG. 12 is a sectional view of the semiconductor device according to the second embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which explain the method (Part 4).
[0027]FIG. 13 is a sectional view of the semiconductor device according to Modification 1 of the second embodiment of the present invention.
[0028]FIG. 14 is a sectional view of the semiconductor device according to Modification 2 of the second embodiment of the present invention.
[0029]FIG. 15 is a sectional view of the semiconductor device according to Modification 3 of the second embodiment of the present invention.
[0030]FIG. 16 is a sectional view of the semiconductor device according to a third embodiment of the present invention.
[0031]FIGS. 17A to 17D are sectional views of the semiconductor device according to the third embodiment of the present invention in the steps of the method for fabricating the same, which explain the method (Part 1).
[0032]FIGS. 18A to 18C are sectional views of the semiconductor device according to the third embodiment of the present invention in the steps of the method for fabricating the same, which explain the method (Part 2).
[0033]FIG. 19 is sectional views of the semiconductor device according to the third embodiment of the present invention in the steps of the method for fabricating the same, which explain the method (Part 3).
[0034]FIG. 20 is a sectional view of the semiconductor device according to a fourth embodiment of the present invention.
The semiconductor device according to a first embodiment of the present invention and the method for fabricating the semiconductor device will be explained with reference to FIGS. 1A to 7. FIGS. 1A and 1B are views of the semiconductor device according to the present embodiment. FIG. 1A is sectional view of the semiconductor device according to the present embodiment.
First, the semiconductor device according to the present embodiment will be explained with reference to FIGS. 1A and 1B.
As shown in FIG. 1A, element isolation regions 14 for defining element regions 12 are formed on the surface of a semiconductor substrate 10 of, e.g., silicon.
In the element regions 12 defined by the element isolation regions 14 an n-well 16 a and a p-well 16 b are formed.
In the n-well 16 a, a p-channel transistor 24 a having a gate electrode 20 a and a source/drain diffused layer 22 a is formed. A contact layer 26 a heavily doped with a p type dopant is also formed in the n-well 16 a.
In the p-well 16 b, an n-channel transistor 24 b having a gate electrode 20 b and a source/drain diffused layer 22 b is formed. A contact layer 26 b heavily doped with an n type dopant is also formed in the p-well 16 b.
An electrode 28 is formed on the element isolation region 14. The electrode 28 is connected to, e.g., a semiconductor element (not shown) of high calorie.
Inter-layer insulation films 30 a-30 f are sequentially laid one on another on the semiconductor substrate 10 with the transistors 24 a, 24 b formed on. Inter-layer insulation films 30 a-30 f are formed of a SiO2 film and a barrier layer, respectively. The barrier layer is for preventing diffusion of Cu.
Interconnections 32 of, e.g., Cu are suitably formed on the respective inter-layer insulation films 30 a-30 f.
The respective interconnections 32 are suitably connected to the other interconnections 32, the source-drain diffused layers 22 a, 22 b, the contact layers 26 a, 26 b, etc. through vias 34 buried in the inter-layer insulation films 30 a-30 f.
A protection film 36 is formed on the inter-layer insulation film 30 f. The protection film 36 is formed of a SiO2 film and a barrier layer. The barrier layer is for preventing diffusion of Cu.
Openings 38 a, 38 b are formed in the protection film 36 and the inter-layer insulation films 30 a-30 f. The opening 38 a is formed down to, e.g., the electrode 28 or the interconnection 32. The opening 38 b is formed down to the surface of the semiconductor substrate 10 near the transistor 24 a. The openings 38 a, 38 b have a 0.1 μm-diameter.
Cylindrical heat conductors 42 each of a bundle of carbon nanotubes are buried in the openings 38 a, 38 b.
A structure 36 or a part 36 may be added on the inter-layer insulation film 30 f. In this case, the structure 36 or the part 36 is called a package or an interposer.
[0051]FIG. 1B is a perspective view of the heat conductors 42 buried in the openings 38 a, 38 b.
As shown in FIG. 1B, each heat conductor 42 is formed of a bundle of a plurality of carbon nanotubes 40. A diameter of each nanotube 40 is, e.g., about 1 nm. Each heat conductor 42 is formed of a bundle of hundreds to thousands of the carbon nanotubes 40.
Here, the carbon nanotube will be explained.
The carbon nanotube is a self-organized nano structure and a tube structure of carbon atoms. The carbon nanotube is cylindrical. The carbon nanotube is a new carbon-based material noted because of the unique properties. The carbon nanotube has a cylindrical structure of a graphite sheet, in which carbon atoms are combined with each other with the very strong bond, sp2+. The diameter of the carbon nanotube is about 0.4 nm at minimum, and nanotubes of an about several hundreds microns-length are known. Very small size variations are characteristic of the nanotubes. The carbon nanotubes have the electric conduction widely varied from that of semiconductors to that of metals depending on the chilarity.
The thermal conductivity of the carbon nanotubes is as high as above 30 W/(cm·K).
[0056]FIG. 2 shows a graph of the thermal conductivities of iron, silver and diamond.
As seen from FIG. 2, the thermal conductivity of 12C, which is pure diamond, is about 30 W/(cm·K). The carbon nanotubes have very high thermal conductivity which can be compared to that of 12C, the pure diamond.
[0058]FIG. 3 is a graph of relationships between diameters of the carbon nanotubes and thermal conductivities. In FIG. 3, diameters of the carbon nanotubes are taken on the horizontal axis, and thermal conductivities of the carbon nanotubes are taken on the vertical axis.
[0059]FIG. 3 is cited from Thermal Conductivity of Carbon Nanotubes, Jianwei Che, Tahir Cagin and William A. Goddard III, http://www.foresight.org/Conferences/MNT7/Papers/Che/index. html.
The carbon nanotubes, which are a material of such very high thermal conductivity, are used as a material of the thermal conductors 42, whereby heat generated in the semiconductor elements, such as the transistors 24 a, 24 b, etc., is efficiently radiated.
The thermal conductor is connected to the electrode 28 on the left side of the drawing of FIG. 1A, and the thermal conductor 42 is connected to the surface of the semiconductor substrate 10 near the transistor 24 a on the right side of the drawing of FIG. 1A. However, the positions the thermal conductors 42 are connected to are not limited to the above. The thermal conductors 42 may be connected to suitable positions so that required heat radiation can be realized.
A heat radiator plate 44 of, e.g., aluminum is formed on the protection plate 36 and the thermal conductors 42. The heat radiator plate 44 has concavities and convexities 45 for securing a larger surface area.
The heat radiation plate 44 may be added as a part on the protection film 36. In the case that the structure 36 or the part 36 is formed on the inter-layer insulation film 30 f, the heat radiation plate 44 may be added on the structure 36 or the part 36.
The heat radiator plate 44 is to be contact with a heat bath 46 of air, water or others.
The semiconductor device according to the present embodiment is characterized mainly in that the thermal conductors 42 formed of the bundles of the carbon nanotubes 40 are buried in the inter-layer insulation films 30 a-30 f.
In the conventional semiconductor devices, heat generated in semiconductor elements, etc., such as transistors, etc. has not been able to be always effectively radiated.
Inconstant to this, in the present embodiment, the thermal conductors 42 formed of the bundle of the carbon nanotubes 40, which is a material of very high thermal conductivity, are buried in the inter-layer insulation films 30 a-30 f, whereby heat generated in the semiconductor elements, etc., such as the transistors 24 a, 24 b, etc. can be effectively radiated. Thus, according to the present embodiment, the semiconductor device according to the present embodiment can have good heat radiation characteristics.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 4A to 7. FIGS. 4A to 7 are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device, which explain the method.
As shown in FIG. 4A, the element isolation regions 14 for defining element regions 12 are formed on the surface of a semiconductor substrate 10 of, e.g., silicon.
Then, the n-well 16 a and the p-well 16 b are formed in the element regions 12 defined by the element isolation regions 14.
Then, the p-channel transistor 24 a having the gate electrode 20 a and the source/drain diffused layer 22 a is formed in the p-well 16 a. In the p-well 16 a, the contact layer 26 a heavily doped with a p type dopant is formed.
In the p-well 16 b, the n-channel transistor 24 b having the gate electrode 20 band the source/diffused layer 22 b is formed. In the p-well 16 b, the contact layer 26 b heavily doped with an n type dopant is formed.
The electrode 28, etc. are suitably formed. Thus, the electrode 28 connected to, e.g., high calorific value semiconductor elements (not shown) is formed on the element isolation region 14.
Then, the inter-layer insulation films 30 a-39 f of, e.g., SiO2, and the interconnections 32 of, e.g., Cu, etc. are formed on the semiconductor substrate 10 with the transistors 24 a, 24 b, etc. formed on. The interconnections 32 are suitably connected to the other interconnections 32, the source/drain diffused layers 22 a, 22 b, the contact layers 26 a, 26 b, etc. through the vias 34 buried in the inter-layer insulation films 30 a-30 f.
Then, the protection film 36 of SiO2 is formed on the entire surface by, e.g., CVD.
Then, as shown in FIG. 4B, a photoresist film 48 is formed on the entire surface by, e.g., spin coating. Then, the photoresist film 48 is patterned by photolithography. Thus, the openings 50 are formed in the photoresist film 48 down to the protection film. The openings 50 are for forming openings 38 a, 38 b for burying the thermal conductors 42 of the carbon nanotubes 40 in the protection film 36 and the inter-layer insulation films 30 a-30 f.
Next, as shown in FIG. 5A, the protection film 36 and the inter-layer insulation films 30 a-30 f are etched by, e.g., plasma etching with the photoresist film 48 as a mask. Thus the opening 38 a and the opening 38 b are formed respectively down to, e.g., the electrode 28 and e.g., the surface of the semiconductor substrate 10 near the transistor 24 a are formed. As an etching gas is, SF6, for example, can be used.
Then, a catalyst layer 52 is formed on the entire surface by, e.g., evaporation. The catalyst layer 52 is for growing carbon nanotubes. As materials of the catalyst layer 52, transition metals, e.g., Ni, Fe, Co, or others, or alloys of their compounds can be suitably used. The thickness of the catalyst layer 52 may be equivalent to, e.g., several atomic layers.
Then, the photoresist film 48 is lifted off to remove an unnecessary part of the catalyst layer 52. Thus, the catalyst layer 52 is formed only on the bottoms of the openings 38 a, 38 b.
Next, as shown in FIG. 5B, the thermal conductors 42 of the carbon nanotubes 40 are grown on the catalyst layer 52 by, e.g., thermal CVD. The thermal conductors 42 are grown to be above, e.g., the upper surface of the protection film 36. As acetylene gas, for example, can be used. The growth temperature can be, e.g., 400-900° C. Thus, the thermal conductors 42 of the carbon nanotubes 40 can be formed in the openings 38 a, 38 b. The catalyst layer 52 is left on the roots of the carbon nanotubes 40, i.e., the bottom surfaces of the openings 38 a, 38 b.
In the present embodiment, the carbon nanotubes 40 are formed by thermal CVD, but can be formed by not only thermal CVD but also by other growing techniques. For example, the carbon nanotubes 40 can be formed by plasma CVD, and in this case, as a raw material gas, methane gas, for example can be used. The growth temperature may be, e.g., about 400-900° C. In the case that the carbon nanotubes 40 are formed by plasma CVD, the catalyst layer 52 is left on the forward ends of the carbon nanotubes 40, i.e., the upper ends of the thermal conductors 42.
Next, as shown in FIG. 6A, the parts of the thermal conductors 42 projected beyond the protection film 36 are partially etched off by argon ion milling. To partially etching off the thermal conductors 42 projected beyond the protection film 36, Ar ions are injected diagonally to the surface of the substrate.
Next, as shown in FIG. 6B, an about 1 μm-thickness-metal layer 54 of aluminum is formed on the entire surface by, e.g., vacuum evaporation.
Next, a photoresist film 56 is formed on the entire surface by spin coating. Then, the photoresist film 56 is patterned in, e.g., stripes by photolithography.
Next, with the photoresist film 56 as a mask, the metal layer 54 is etching down to a set depth. Thus, the concavity and convexities 45 are formed in the surface of the metal layer 54 to thereby make the surface area of the metal layer 54 larger.
Thus, as shown in FIG. 7, the heat radiator plate 44 of the metal layer 54 is formed.
As described above, the semiconductor device according to the present embodiment is fabricated.
The semiconductor device according to a second embodiment of the present invention and the method for fabricating the semiconductor device will be explained with reference to FIG. 8 to FIG. 12. FIG. 8 is a sectional view of the semiconductor device according to the present embodiment. FIGS. 9A to 12 are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device. The same members of the present embodiment as those of the semiconductor device according to the first embodiment and the method for fabricating the semiconductor device shown in FIGS. 1 to 7 are represented by the same reference numbers not to repeat or to simplify their explanation.
The semiconductor device according to the present embodiment is characterized mainly in that a plurality of thermal conductors 42 a, 42 b are serially connected through interconnections 32 a extended horizontally to the substrate.
As shown in FIG. 8, an opening 38 c is formed in an inter-layer insulation film 30 a down to, e.g., the surface of a semiconductor substrate 10 near a transistor 24 a. The thermal conductor 42 a of a bundle of carbon nanotubes 40 is buried in the opening 38 c.
An interconnection 32 a of, e.g., Cu is formed on an inter-layer insulation film 30 e. The interconnection 32 a is connected to the thermal conductor 42 a.
An opening 38 d is formed in the inter-layer insulation films 30 e, 30 f and a protection film 36 down to the interconnection 32 a. The thermal conductor 42 b of a bundle of nanotubes 40 is buried in the opening 38. The thermal conductor 42 b is serially connected to the thermal conductor 42 a through the interconnection 32 a. The interconnection 32 a functions not only as a usual electric wire, but also as an intermediate thermal conductor for thermally interconnecting the thermal conductor 42 a and the thermal conductor 42 b.
Thus, the semiconductor device according to the present embodiment is formed.
The semiconductor device according to the present embodiment is characterized mainly in that as described above, a plurality of thermal conductors 42 a, 42 b are serially connected to each other through the interconnection 32 a.
In the semiconductor device according to the first embodiment, one thermal conductor 42 is formed from the surface of the protection film 36 down to the surface of the semiconductor substrate 10, which has not made it always easy to ensure regions for the thermal conductors 42 to be buried in. It tends to be more difficult to ensure regions for the thermal conductors 42 to be buried in as a number of especially interconnections is larger.
In contrast to this, according to the present embodiment, the thermal conductors 42 a and the thermal conductor 42 b are serially connected to each other through the interconnection 32 a extended horizontally to the substrate, which makes it easy to ensure region for the thermal conductors to be buried in. Accordingly to the present embodiment, the freedom of layout is higher.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 9A to 12.
The steps up to the step of forming the inter-layer insulation film 30 e including the inter-layer insulation film 30 e forming step are the same as those of the method for fabricating the semiconductor device described above with reference to FIG. 4A, and their explanation will not be repeated.
Next, as shown in FIG. 9A, a photoresist film 58 is formed on the entire surface by spin coating. Then, the photoresist film 58 is patterned by photolithography. Thus, the opening 60 is formed in the photoresist film down to the inter-layer insulation film 30 e. The opening 60 is for forming in the inter-layer insulation films 30 a-30 e the opening 38 c in which the thermal conductor 42 a of a bundle of carbon nanotubes 40 is to be buried.
Then, the inter-layer insulation films 30 a-30 e are etched with the photoresist film 58 as a mask by, e.g., plasma etching. Thus, the opening 38 c is formed down to, e.g., the surface of the semiconductor device 10. As an etching gas, SF6, for example, is used as described above.
Next, as shown in FIG. 9B, a catalyst layer 62 is formed on the entire surface by, e.g., evaporation.
Then, the photoresist film 58 is lifted off to remove unnecessary part of the catalyst layer 62.
Next, as shown in FIG. 9C, the thermal conductor 42 a of the carbon nanotubes 40 is grown in the opening 38 c by, e.g., plasma CVD. Thus, the thermal conductor 42 a of a bundle of the carbon nanotubes 40 is buried in the opening 38 c. In FIG. 9C to FIG. 12, the catalyst layer 62 is omitted.
Then, as shown in FIG. 10A, the insulation film 64 of, e.g., a 500 nm-thickness SiO2 is formed.
Next, a photoresist film 66 is formed on the entire surface by, e.g., spin coating. Then, the photoresist film 66 is patterned by photolithography. Thus the opening 68 is formed in the photoresist film 68.
Then, with the photoresist film 66 as a mask, the insulation film 64 is etched. Thus, grooves 70 for the interconnections 32, 32 a to be buried in are formed in the insulation film 64.
Next, as shown in FIG. 10B, a photoresist film 72 is formed on the entire surface by, e.g., spin coating. Next, the photoresist film 72 is patterned by photolithography. Thus, openings 76 for forming contact holes 74 a, 74 b in the inter-layer insulation film 30 e are formed in the photoresist film 72.
Next, with the photoresist film 72 as a mask, the inter-layer insulation film 30 e is etched. Thus, the contact hole 74 a and the contact hole 74 b are formed in the inter-layer insulation film respectively down to the interconnection 32 and the via 34.
Then, as shown in FIG. 10C, the interconnections 32, 32 a and the vias 34 are buried in the grooves 70 and the contact holes 74 a, 74 b by dual damascene. Specifically, first, a seed layer (hot shown) of, e.g. Ti is formed on the entire surface by, e.g., sputtering. Then, a Cu layer of, e.g., 1 μm-thickness is formed by plating. Then, the Cu layer is polished by CMP (Chemical Mechanical-Polishing) until the surface of the insulation film 64 is exposed. Thus, the interconnections 32, 32 a and the vias 34 are buried in the grooves 70 and the contact holes 74 a, 74 b.
Then, as shown in FIG. 11A, the inter-layer insulation film 30 f, the interconnection 32, the vias 34 and the protection film 36 are suitably formed.
Next, a photoresist film 78 is formed on the entire surface by spin coating. Next, the photoresist film 78 is patterned by photolithography. Thus, the opening 80 is formed in the photoresist film 78 down to the protection film 36. The opening 80 is for forming in the protection film 36 and the inter-layer insulation films 30 e, 30 f the opening 38 d for the thermal conductor 42 b of the carbon nanotubes 40 to be buried in.
Next, with the photoresist film 78 as a mask, the protection film 36 and the inter-layer insulation films 30 e, 30 f are etched by, e.g., plasma etching. Thus, the openings 38 d is formed down to, e.g., the interconnection 32 a. As an etching gas, SF6, for example, can be used as described above.
Next, the catalyst layer 82 is formed on the entire surface by, e.g., evaporation. Thus, the catalyst layer 82 is formed on the bottom surface of the opening 38 d.
Then, the photoresist film 78 is lifted off to remove the unnecessary part of the catalyst layer 82.
Then, as shown in FIG. 11B, the thermal conductor 42 b of a bundle of the carbon nanotubes 40 is formed in the opening 38 d by, e.g., plasma CVD. In FIGS. 11B to 12, the catalyst layer 82 is omitted.
Next, the thermal conductor 42 b projected beyond the protection film 36 is removed by argon ion milling.
Then, in the same way as in the method for fabricating the semiconductor device described above with reference to FIGS. 6B and 7, the heat radiator plate 44 is formed (see FIG. 12).
Next, the semiconductor device according to Modification 1 of the present embodiment will be explained with reference to FIG. 13. FIG. 13 is a sectional view of the semiconductor device according to the present modification.
The semiconductor device according to the present modification is characterized mainly in that thin insulation films 84 a, 84 b are formed respectively between a thermal conductor 42 a, 42 b and an interconnection 32 a which functions as an intermediate thermal conductor.
As shown in FIG. 13, the insulation film 84 a of a 5 nm-film thickness which is formed of, e.g., SiO2 is formed between the thermal conductor 42 a and the interconnection 32 a. The arrow in the drawing indicates the heat conduction path.
The insulation film 84 b of a 5 nm-film thickness which is formed of, e.g., SiO2 is formed between the interconnection 32 a and the thermal conductor 42 b.
As described above, according to the present modification, the insulation films 84 a, 84 b are formed respectively between the thermal conductors 42 a, 42 b and the interconnection 32 a, whereby the thermal conductors 42 a, 42 b can be electrically insulated from the interconnection 32 a. Furthermore, the insulation films 84 a, 84 b, which are thin, do not much hinder the thermal connection between the thermal conductors 42 a and the interconnection 32 a and the thermal connection between the interconnection 32 a and the thermal conductor 42 b. Thus, according to the present modification, the electric insulation between the thermal conductors 42 a, 42 b and the interconnection 32 a is ensured while the thermal conductor 42 a and the thermal conductor 42 b can be thermally connected.
(Modification 2) Next, the semiconductor device according to Modification 2 of the present embodiment will be explained with reference to FIG. 14. FIG. 14 is a sectional view of the semiconductor device according to the present modification.
The semiconductor device according to the present modification is characterized mainly in that a thermal conductor 42 a and a thermal conductor 42 b are thermally connected by means of an interconnection 32 a of a bundle of carbon nanotubes.
As shown in FIG. 14, an interconnection 32 a of a bundle of carbon nanotubes is formed on an inter-layer insulation film 30 e. The carbon nanotubes forming the interconnection 32 a are grown horizontally to the substrate surface. To grow the carbon nonotubes horizontally to the substrate surface, carbon nanotubes are grown by, e.g., plasma CVD or thermal CVD while an electric field is being applied horizontally to the substrate surface.
The interconnection 32 b of a bundle of carbon nanotubes is thermally connected to the thermal conductors 42 a, 42 b respectively through insulation films 84 a, 84 b.
In the semiconductor device shown in FIG. 8 or FIG. 13, the thermal conductor 42 a and the thermal conductor 42 b are thermally connected to each other through the interconnection of, e.g., Cu. Because of the thermal conductivity of Cu used as a material of the interconnection 32 a, which is lower than that of the carbon nanotubes, good thermal conductivity cannot be always obtained.
However, in the present modification, carbon nanotubes, whose thermal conductivity is very high, are used as a material of the interconnection 32 b, and even in the case that the thermal conductor 42 a and the thermal conductor 42 b are thermally connected to each other through the interconnection 32 b, good thermal conductivity can be obtained.
Thus, the semiconductor device according to the present modification can have good heat radiation characteristics.
Next, the semiconductor device according to Modification 3 of the present embodiment will be explained with reference to FIG. 15. FIG. 15 is a sectional view of the semiconductor device according to the present modification.
The semiconductor device according to the present modification is characterized mainly in that an intermediate thermal conductor 42 c which thermally interconnecting a thermal conductor 42 a and a thermal conductor 42 b is formed integral with the thermal conductors 42 a, 42 b.
As shown in FIG. 15, the intermediate thermal conductor 42 c of a bundle of carbon nanotubes is formed on an inter-layer insulation film 30 e horizontally to the substrate. The intermediate thermal conductor 42 c is formed integral with the thermal conductor 42 a. The intermediate thermal conductor 42 c is formed separate from an interconnection 32.
To grow carbon nanotubes horizontally to the substrate and integrally with the thermal conductor 42 a, the carbon nanotubes are grown after the thermal conductor 42 a has been formed, by, e.g., plasma CVD or thermal CVD while an electric field is being applied horizontally to the substrate surface. Carbon nanotubes are thus grown to thereby form the intermediate thermal conductor 42 c integral with the thermal conductor 42 a.
The thermal conductor 42 b which has been grown perpendicularly to the substrate is formed at the end of the intermediate thermal conductor 42 c. The thermal conductor 42 b is formed integral with the intermediate thermal conductor 42 c.
To form the thermal conductor 42 b integral with the intermediate thermal conductor 42 c, after the thermal conductor 42 c has been grown, carbon nanotubes are grown by, e.g., plasma CVD or thermal CVD while an electric field is being applied perpendicularly to the substrate surface.
Thus, the thermal conductor 42 a, the intermediate thermal conductor 42 b and the thermal conductor 42 c may be formed integral.
The semiconductor device according to a third embodiment of the present invention and the method for fabricating the semiconductor device will be explained with reference to FIG. 16 to FIG. 19. FIG. 16 is a sectional view of the semiconductor device according to the present embodiment. FIGS. 17A to 19 are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device, which explain the method. The same members of the present embodiment as those of the semiconductor device according to the first and the second embodiments and the method for fabricating the semiconductor device shown in FIGS. 1 to 15 are represented by the same reference numbers not to repeat or to simplify their explanation.
First, the semiconductor device according to the present embodiment will be explained with reference to FIG. 16.
The semiconductor device according to the present embodiment is characterized mainly in that thermal conductors 42 d are buried in a semiconductor substrate 10, and heat can be radiated at the underside of the semiconductor substrate 10.
As shown in FIG. 16, the thermal conductors 42 d of a bundle carbon nanotubes are buried in the semiconductor substrate 10.
A heat radiator plate 44 a is formed on the underside of the semiconductor substrate 10 with the thermal conductors 42 d buried in.
The heat radiator plate 44 contacts a heat bath 46 of air, water of others.
The present embodiment has very high freedom of burying the thermal conductors 42 a because the thermal conductors 42 d are buried in the semiconductor substrate 10. Accordingly, the present embodiment facilitates the layout in design.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 17A to 19.
First, as shown in FIG. 17A, transistors 24 a, 24 b, etc. are formed on the semiconductor substrate 10. Then, the inter-layer insulation film 30 a is formed on the entire surface.
Then, as shown in FIG. 17B, the semiconductor substrate 10 is turned upside down.
Next, a photoresist film 86 is formed on the entire surface by spin coating. Then, the photoresist film 86 is patterned by photolithography. Thus, openings 88 are formed in the photoresist film 86 down to the semiconductor substrate 10. The openings 88 are for forming in the semiconductor substrate 10 openings 90 for carbon nanotubes 42 d to be buried in.
Next, the semiconductor substrate 10 is etched by, e.g., plasma etching with the photoresist film 86 as a mask. Thus the opening 90 a, 90 b and the opening 90 c, 90 d are formed respectively down to the inter-layer insulation film 30 a and the element isolation region 14.
Next, as shown in FIG. 17C, a catalyst layer 92 is formed on the entire surface by, e.g., evaporation.
Then, the photoresist film 86 is lifted off to remove unnecessary part of the catalyst layer 92.
Next, as shown in FIG. 17D, the thermal conductors 42 d of bundles of carbon nanotubes are formed in the openings 90 a-90 d by, e.g., plasma CVD. The carbon nanotubes are grown by plasma CVD, which leaves the catalyst layer 92 on the upper ends of the thermal conductors 42 d.
Then, as shown in FIG. 18A, the thermal conductors 42 d and the catalyst layer 92 which are projected beyond the semiconductor substrate 10 are removed by argon ion milling.
Then, as shown in FIG. 18B, a metal layer of 1 μm-thickness aluminum is formed on the entire surface by, e.g., vacuum evaporation. Thus, the heat radiator 44 a is formed of the meal layer.
Then, the semiconductor substrate 10 is turned upside down.
Next, in the same way as in the method for fabricating the semiconductor device described above with reference to FIG. 4A, inter-layer insulation films 30 b-30 f, an interconnection 32, vias 34, a protection film 36, etc. are suitably formed (see FIG. 19).
The semiconductor device according to a fourth embodiment of the present invention will be explained with reference to FIG. 20. FIG. 20 is a sectional view of the semiconductor device according to the present embodiment. The same members of the present embodiment as those of the semiconductor device according to the first to the third embodiments and the method for fabricating the semiconductor device shown in FIGS. 1 to 19 are represented by the same reference numbers not to repeat or to simplify their explanation.
The semiconductor device according to the present embodiment is characterized mainly in that thermal conductors 42 have the upper ends connected to a Peltier device 94 as a thermoelectric cooling element.
The Peltier device 94 comprises a p-semiconductor and an n-semiconductor arranged thermally in parallel and electrically serially and causes heat absorption (cooling) and heat radiation (heating) by Peltier effect.
As shown in FIG. 20, an inter-layer insulation film 30 g is formed on the inter-layer insulation film 30 f.
The Peltier device 94 is buried in the inter-layer insulation film 30 g. The Peltier device 94 has the underside as the lower-temperature side and the upper side as the higher-temperature side.
The thermal conductors 42 have the upper sides connected to the underside of the Peltier device 94, i.e., the lower-temperature side.
Interconnections 96 a, 96 b are formed on the inter-layer insulation film 30 g and the Peltier device 94. The interconnections 96 a, 96 b provide an electric power source for the Peltier device 94.
A heat radiator plate 44 is formed on the interconnections 96 a, 96 b. The heat radiator plate 44 is thermally connected to the upper side of the Peltier device 94, i.e., the higher-temperature side through the interconnections 96 a, 96 b.
According to the present embodiment, the Peltier device 94 as the thermoelectric cooling device is disposed between the heat radiator plate 44 and the thermal conductors 42, whereby the thermal conductors 42 can be further cooled. Accordingly, in the present embodiment, the semiconductor elements, such as the transistors 24 a, 24 b, etc., can be further cooled.
For example, in the above-described embodiments, the heat radiator plate is provided but is not essential. For example, the thermal conductors may contact directly the heat bath. However, the provision of the heat radiator plate makes the heat radiation more effective.
In the above-described embodiments, the thermal conductors are formed of bundles of carbon nanotubes, but bundles of nanotubes are not essential. The thermal conductor may be formed of one carbon nanotube.
In the third embodiment, no cavities and convexities are formed in the surface of the heat radiator plate 44 a. However, concavities and convexities may be formed in the surface of the heat radiator plate 44 a, which can improve the heat radiation characteristics.
an insulation film formed on a semiconductor substrate; and
a thermal conductor buried in the insulation film,
the thermal conductor being formed of a tube structure of carbon atoms.
another thermal conductor thermally connected to said thermal conductor,
said another thermal conductor being formed of a tube structure of carbon atoms.
an intermediate thermal conductor which thermally interconnects said thermal conductor and said another thermal conductor.
an insulation film formed at least between said thermal conductor and said intermediate thermal conductor or between said another thermal conductor and said intermediate thermal conductor.
the intermediate thermal conductor functions also as an electric interconnection.
6. A semi conductor device according to claim 4, wherein
7. A semiconductor device according to claim 3, wherein
the intermediate thermal conductor is formed integral with at least said thermal conductor or said another thermal conductor.
8. A semiconductor device according to claim 3, wherein
the intermediate thermal conductor is formed of a tube structure of carbon atoms.
9. A semiconductor device according to claim 4, wherein
10. A semiconductor device according to claim 5, wherein
11. A semiconductor device according to claim 6, wherein
13. A semiconductor device comprising a thermal conductor buried in a semiconductor substrate,
14. A semiconductor device according to claim 1, further comprising:
a heat radiator plate thermally connected to the thermal conductor.
15. A semiconductor device according to claim 9, wherein
the heat radiator plate is formed of a metal.
16. A semiconductor device according to claim 1, further comprising:
a thermoelectric cooling element connected to the thermal conductor.
17. A semiconductor device according to claim 2, further comprising:
18. A semiconductor device according to claim 3, further comprising:
forming an insulation film on a semiconductor substrate; and
forming an opening in the insulation film; and
growing a thermal conductor of a tube structure of carbon atoms in the opening.
20. A method for fabricating a semiconductor device comprising the steps of:
US10435471 2002-05-13 2003-05-12 Semiconductor device and method for fabricating the same Active US6800886B2 (en)
JP2002-136708 2002-05-13
US20030209802A1 true true US20030209802A1 (en) 2003-11-13
US6800886B2 US6800886B2 (en) 2004-10-05
US10435471 Active US6800886B2 (en) 2002-05-13 2003-05-12 Semiconductor device and method for fabricating the same
WO2006003620A1 (en) * 2004-06-30 2006-01-12 Koninklijke Philips Electronics N.V. Method for manufacturing an electric device with a layer of conductive material contacted by nanowire
WO2006048843A2 (en) 2004-11-04 2006-05-11 Koninklijke Philips Electronics N.V. Integrated circuit nanotube-based substrate
US20070035011A1 (en) * 2005-08-11 2007-02-15 Hall David R Integrated Circuit Apparatus with Heat Speader
US20080044954A1 (en) * 2004-02-12 2008-02-21 International Business Machines Corporation Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby
EP1945840A2 (en) * 2005-08-26 2008-07-23 Smoltek AB Interconnects and heat dissipators based on nanostructures
US20090120482A1 (en) * 2007-11-09 2009-05-14 Mccullough Edward D Device and method for generating electrical power
US20090250091A1 (en) * 2008-04-08 2009-10-08 James Ping Huang Device and method for generating electrical power
US7700978B2 (en) 2004-10-22 2010-04-20 Fujitsu Microelectronics Limited Semiconductor device and method of manufacturing the same
WO2010061236A1 (en) * 2008-11-25 2010-06-03 Mantovani, Sascha Device for rapidly transferring thermal energy
US20100264544A1 (en) * 2006-01-20 2010-10-21 Jang-Eun Heo Device including contact structure and method of forming the same
US20110260325A1 (en) * 2010-04-27 2011-10-27 Canon Kabushiki Kaisha Semiconductor device
US8786077B2 (en) 2011-06-07 2014-07-22 Kabushiki Kaisha Toshiba Semiconductor device having a first substrate containing circuit element connected to radiation plate on a cover plate with metal vias
US20160300775A1 (en) * 2014-09-28 2016-10-13 Texas Instruments Incorporated Integration of heat spreader for beol thermal management
DE102015122804A1 (en) * 2015-12-23 2017-06-29 Infineon Technologies Ag A semiconductor device comprising a heat sink structure
DE112009005017T5 (en) * 2009-06-29 2012-07-26 Fujitsu Limited Semiconductor device and method of manufacturing a semiconductor device
JP5577665B2 (en) * 2009-10-07 2014-08-27 富士通セミコンダクター株式会社 A method of manufacturing a semiconductor device
JP5870758B2 (en) * 2012-02-28 2016-03-01 富士通株式会社 Electronic device and method of manufacturing the same
JP5624600B2 (en) * 2012-12-27 2014-11-12 株式会社東芝 A method for manufacturing a wiring and the semiconductor device
JP5626400B2 (en) * 2013-04-22 2014-11-19 株式会社ニコン Stacked semiconductor device
US7820502B2 (en) * 2004-02-12 2010-10-26 International Business Machines Corporation Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby
WO2005119800A2 (en) * 2004-05-19 2005-12-15 Intel Corporation Thermoelectric nano-wire devices
WO2005119800A3 (en) * 2004-05-19 2006-03-23 Intel Corp Thermoelectric nano-wire devices
CN100568495C (en) 2004-11-04 2009-12-09 台湾积体电路制造股份有限公司 Integrated circuit nanotube-based substrate
US7566945B2 (en) * 2005-05-07 2009-07-28 Samsung Electronics Co., Ltd. Semiconductor devices including nanotubes
EP1945840B1 (en) * 2005-08-26 2017-03-08 Smoltek AB Integrated circuit comprising nanostructures
US7982318B2 (en) * 2006-01-20 2011-07-19 Samsung Electronics Co., Ltd. Device including contact structure and method of forming the same
US8633371B2 (en) 2007-11-09 2014-01-21 The Boeing Company Device and method for generating electrical power
WO2009064551A3 (en) * 2007-11-09 2009-12-03 The Boeing Company Device and method for generating electrical power
WO2009064551A2 (en) * 2007-11-09 2009-05-22 The Boeing Company Device and method for generating electrical power
US9054273B2 (en) 2008-04-08 2015-06-09 The Boeing Company Device and method for generating electrical power
JP2003332504A (en) 2003-11-21 application
US6800886B2 (en) 2004-10-05 grant
JP4416376B2 (en) 2010-02-17 grant
US5874777A (en) 1999-02-23 Semiconductor device with enhanced thermal conductivity
US5229643A (en) 1993-07-20 Semiconductor apparatus and semiconductor package
US5955781A (en) 1999-09-21 Embedded thermal conductors for semiconductor chips
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AWANO, YUJI;REEL/FRAME:014064/0931