Source: http://www.google.com/patents/US7415565?dq=5,941,947
Timestamp: 2016-12-03 22:03:35
Document Index: 607537290

Matched Legal Cases: ['Application No. 38', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 11', 'Application No. 11', 'Application No. 11']

Patent US7415565 - Methods and systems for a storage system with a program-controlled switch ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, a section controller, and a switch. The switch is capable of reading a data request including a data block identifier and routing...http://www.google.com/patents/US7415565?utm_source=gb-gplus-sharePatent US7415565 - Methods and systems for a storage system with a program-controlled switch for routing dataAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7415565 B2Publication typeGrantApplication numberUS 10/284,278Publication dateAug 19, 2008Filing dateOct 31, 2002Priority dateOct 31, 2002Fee statusLapsedAlso published asUS20040088514Publication number10284278, 284278, US 7415565 B2, US 7415565B2, US-B2-7415565, US7415565 B2, US7415565B2InventorsMelvin James Bullen, Steven Louis Dodd, William Thomas Lynch, David James HerbisonOriginal AssigneeRing Technology Enterprises, LlcExport CitationBiBTeX, EndNote, RefManPatent Citations (83), Non-Patent Citations (63), Referenced by (18), Classifications (14), Legal Events (9) External Links: USPTO, USPTO Assignment, EspacenetMethods and systems for a storage system with a program-controlled switch for routing data
As will be obvious to one of skill in the art, other embodiments of the memory interface device are possible, without departing from the scope of the invention. For example, although each memory interface device is described as only having one read or write shift register array, the memory interface device may include any number of write or read chains of shift register arrays. Further, the shift registers 76 rather than being 1 bit shift registers may be of any depth. For example, the shift register arrays could be, for example, N×M arrays such as, for example, 2×8, 4×32, 8×16, etc. arrays as determined by the system designers for their particular implementation. Additionally, the shift registers arrays may be configured in a ring, such that the data once loaded into a chain circulates synchronously in the chain. A more detailed description of memory access using shift register arrays is set forth in the aforementioned U.S. patent application Ser. No. 10/284,198 by William T. Lynch and David J. Herbison entitled “Methods and Apparatus for Improved Memory Access” (issued as U.S. Pat. No. 6,879,526) filed on the same day as the present application.
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