Source: http://www.google.com/patents/US6541294?dq=7095053
Timestamp: 2016-08-30 21:35:26
Document Index: 530317639

Matched Legal Cases: ['Application No. 6', 'application No. 09', 'application No. 09', 'application No. 09', 'Application No. 7', 'Application No. 8']

Patent US6541294 - Semiconductor device and manufacturing method thereof - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsBy providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing...http://www.google.com/patents/US6541294?utm_source=gb-gplus-sharePatent US6541294 - Semiconductor device and manufacturing method thereofAdvanced Patent SearchPublication numberUS6541294 B1Publication typeGrantApplication numberUS 09/618,930Publication dateApr 1, 2003Filing dateJul 18, 2000Priority dateJul 22, 1999Fee statusLapsedAlso published asUS6743649, US7335911, US7968890, US8624248, US20030180996, US20040192004, US20090101901, US20110254008, US20140117364Publication number09618930, 618930, US 6541294 B1, US 6541294B1, US-B1-6541294, US6541294 B1, US6541294B1InventorsShunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yasuyuki AraiOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (38), Non-Patent Citations (27), Referenced by (184), Classifications (37), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and manufacturing method thereof
US 6541294 B1Abstract
What is claimed is: 1. A semiconductor device comprising a pixel TFT disposed in a pixel section and a driver circuit comprising a p-channel TFT and an n-channel TFT disposed in a periphery of the pixel section, over a substrate, wherein:
the n-channel TFT of the driver circuit comprises: a gate electrode which has a tapered portion; a channel forming region; a first impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to partly overlap the gate electrode; and a second impurity region which forms a source region or a drain region that is disposed on the outside of the first impurity region; the p-channel TFT of the driver circuit comprises: a gate electrode which has a tapered portion; a channel forming region; a third impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to overlap the gate electrode; and a fourth impurity region which forms a source region or a drain region which is disposed on the outside of the third impurity region; the pixel TFT comprises a gate electrode which has a tapered portion; a channel forming region; a first impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to partly overlap the gate electrode; and a second impurity region which forms a source region or a drain region that is disposed on the outside of the first impurity region; a concentration of an impurity element of one conductivity type in a region of the first impurity region that overlaps the gate electrode and a concentration of an impurity region of the other conductivity type in the third impurity region are set to become higher as the distance from channel forming regions that are in contact increase; and a pixel electrode that is disposed in the pixel section and has a light reflective surface is formed over a second interlayer insulating film comprising an organic insulating material; and is connected to the pixel TFT through an opening disposed at least in a first interlayer insulating film comprising an inorganic insulating material which is disposed over the gate electrode of the pixel TFT and in the second interlayer insulating film formed in close contact with the insulating film. 2. A semiconductor device comprising a pixel TFT disposed in a pixel section and a driver circuit comprising a p-channel TFT and an n-channel TFT disposed in a periphery of the pixel section, over a substrate, wherein:
the n-channel TFT of the driver circuit comprises: a gate electrode which has a tapered portion; a channel forming region; a first impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to partly overlap the gate electrode; and a second impurity region which forms a source region or a drain region that is disposed on the outside of the first impurity region; the p-channel TFT of the driver circuit comprises: a gate electrode which has a tapered portion; a channel forming region; a third impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to overlap the gate electrode; and a fourth impurity region which forms a source region or a drain region that is disposed on the outside of the third impurity region; the pixel TFT comprises a gate electrode which has a tapered portion; a channel forming region; a first impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to partly overlap the gate electrode; and a second impurity region which forms a source region or a drain region that is disposed on the outside of the first impurity region; a concentration of an impurity element of one conductivity type in a region of the first impurity region that overlaps the gate electrode and a concentration of an impurity region of the other conductivity type in the third impurity region are set to become higher as the distance from channel forming regions that are in contact increase; and a pixel electrode that is disposed in the pixel section and has a light transmitting property is formed over a second interlayer insulating film comprising an organic insulating material; and is connected to a conductive metal wiring which is connected to the pixel TFT, through an opening disposed at least in a first interlayer insulating film comprising an inorganic insulating material that is formed over the gate electrode of the pixel TFT and in the second interlayer insulating film formed in close contact with the insulating film. 3. A semiconductor device which holds liquid crystal between a pair of substrates, wherein:
one substrate which comprises a pixel TFT disposed in a pixel section and a driver circuit comprising a p-channel TFT and an n-channel TFT in the periphery of the pixel section is characterized in that: the n-channel TFT of the driver circuit comprises: a gate electrode which has a tapered portion; a channel forming region; a first impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to partly overlap the gate electrode; and a second impurity region which forms a source region or a drain region that is disposed on the outside of the first impurity region; the p-channel TFT of the driver circuit comprises: a gate electrode which has a tapered portion; a channel forming region; a third impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to overlap the gate electrode; and a fourth impurity region which forms a source region or a drain region which is disposed on the outside of the third impurity region; the pixel TFT comprises a gate electrode which has a tapered portion; a channel forming region; a first impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to partly overlap the gate electrode; and a second impurity region which forms a source region or a drain region that is disposed on the outside of the first impurity region; a concentration of an impurity element of one conductivity type in a region of the first impurity region that overlaps the gate electrode and a concentration of an impurity region of the other conductivity type in the third impurity region are set to become higher as the distance from channel forming regions that are in contact increase; a pixel electrode that is disposed in the pixel section and has a light reflective surface is formed over a second interlayer insulating film comprising an organic insulating material; and is connected to the pixel TFT through an opening disposed at least in a first interlayer insulating film comprising an inorganic insulating material which is disposed over the gate electrode of the pixel TFT and in the second interlayer insulating film formed in close contact with the insulating film; and it is stuck to the other substrate which is formed with a transparent conductive film, through at least one columnar spacer formed above the opening formed in the second interlayer insulating film. 4. A semiconductor device which holds a liquid crystal between a pair of substrates, wherein:
one substrate which comprises a pixel TFT disposed in a pixel section and a driver circuit comprising a p-channel TFT and an n-channel TFT in the periphery of the pixel section is characterized in that: the n-channel TFT of the driver circuit comprises: a gate electrode which has a tapered portion; a channel forming region; a first impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to partly overlap the gate electrode; and a second impurity region which forms a source region or a drain region that is disposed on the outside of the first impurity region; the p-channel TFT of the driver circuit comprises: a gate electrode which has a tapered portion; a channel forming region; a third impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to overlap the gate electrode; and a fourth impurity region which forms a source region or a drain region which is disposed on the outside of the third impurity region; the pixel TFT comprises a gate electrode which has a tapered portion; a channel forming region; a first impurity region which forms an LDD region that is disposed in contact with the channel forming region and so as to partly overlap the gate electrode; and a second impurity region which forms a source region or a drain region that is disposed on the outside of the first impurity region; a concentration of an impurity element of one conductivity type in a region of the first impurity region that overlaps the gate electrode and a concentration of an impurity region of the other conductivity type in the third impurity region are set to become higher as the distance from channel forming regions that are in contact increase; a pixel electrode that is disposed in the pixel section and has a light transmitting property is formed over a second interlayer insulating film comprising an organic insulating material; and is connected to a conductive metal wiring which is connected to the pixel TFT, through an opening disposed at least in a first interlayer insulating film comprising an inorganic insulating material that is formed over the gate electrode of the pixel TFT and in the second interlayer insulating film formed in close contact with the insulating film; and it is stuck to the other substrate which is formed with a transparent conductive film, through at least one columnar spacer formed above the opening formed in the second interlayer insulating film. 5. A semiconductor device according to claim 1 wherein the gate electrodes of the pixel TFT and the p-channel TFT and the n-channel TFT of the driver circuit comprise a heat resistant conductive material and a gate wiring that is connected to the gate electrode is extended from the driver circuit comprises a low resistivity conductive material.
6. A semiconductor device according to claim 2 wherein the gate electrodes of the pixel TFT and the p-channel TFT and the n-channel TFT of the driver circuit comprise a heat resistant conductive material and a gate wiring that is connected to the gate electrode is extended from the driver circuit comprises a low resistivity conductive material.
7. A semiconductor device according to claim 3 wherein the gate electrodes of the pixel TFT and the p-channel TFT and the n-channel TFT of the driver circuit comprise a heat resistant conductive material and a gate wiring that is connected to the gate electrode is extended from the driver circuit comprises a low resistivity conductive material.
8. A semiconductor device according to claim 4 wherein the gate electrodes of the pixel TFT and the p-channel TFT and the n-channel TFT of the driver circuit comprise a heat resistant conductive material and a gate wiring that is connected to the gate electrode is extended from the driver circuit comprises a low resistivity conductive material.
9. A semiconductor device according to claim 5 wherein the heat resistant conductive material is selected from a group consisting of: an element selected from tantalum (Ta), titanium (Ti) or tungsten (W); a compound which comprises the element; a compound which comprises a combination of the element; a nitride which comprises the element; and a silicide which comprises the element.
10. A semiconductor device according to claim 6 wherein the heat resistant conductive material is selected from a group consisting of: an element selected from tantalum (Ta), titanium (Ti) or tungsten (W); a compound which comprises the element; a compound which comprises a combination of the element; a nitride which comprises the element; and a silicide which comprises the element.
11. A semiconductor device according to claim 7 wherein the heat resistant conductive material is selected from a group consisting of: an element selected from tantalum (Ta), titanium (Ti) or tungsten (W); a compound which comprises the element; a compound which comprises a combination of the element; a nitride which comprises the element; and a silicide which comprises the element.
12. A semiconductor device according to claim 8 wherein the heat resistant conductive material is selected from a group consisting of: an element selected from tantalum (Ta), titanium (Ti) or tungsten (W); a compound which comprises the element; a compound which comprises a combination of the element; a nitride which comprises the element; and a silicide which comprises the element.
13. A semiconductor device according to claim 1 wherein an angle of the tapered portion of the gate electrode is between 5 and 45�.
14. A semiconductor device according to claim 2 wherein an angle of the tapered portion of the gate electrode is between 5 and 45�.
15. A semiconductor device according to claim 3 wherein an angle of the tapered portion of the gate electrode is between 5 and 45�.
16. A semiconductor device according to claim 4 wherein an angle of the tapered portion of the gate electrode is between 5 and 45�.
17. A semiconductor device according to claim 1 wherein the semiconductor device is one selected from a group consisting of: a personal computer; a video camera; a portable information terminal; a digital camera, a digital video disc player; an electronic game machine; and a projector.
18. A semiconductor device according to claim 2 wherein the semiconductor device is one selected from a group consisting of: a personal computer; a video camera; a portable information terminal; a digital camera, a digital video disc player; an electronic game machine; and a projector.
19. A semiconductor device according to claim 3 wherein the semiconductor device is one selected from a group consisting of: a personal computer; a video camera; a portable information terminal; a digital camera, a digital video disc player; an electronic game machine; and a projector.
20. A semiconductor device according to claim 4 wherein the semiconductor device is one selected from a group consisting of: a personal computer; a video camera; a portable information terminal; a digital camera, a digital video disc player; an electronic game machine; and a projector.
a pixel section comprising at least one pixel TFT over a substrate; a driver circuit comprising at least one n-channel TFT and at least one p-channel TFT over the substrate; a first interlayer insulating film comprising an inorganic insulating material over the pixel TFT; a second interlayer insulating film comprising an organic insulating material over the first interlayer insulating film; and at least one pixel electrode having a light reflective surface over the second interlayer insulating film, and connected to the pixel TFT through an opening disposed in the first interlayer insulating film and the second interlayer insulating film, wherein each of the pixel TFT and the n-channel TFT comprises a gate electrode having a tapered portion, a channel forming region, a first impurity region forming an LDD region disposed in contact with the channel forming region and so as to partly overlap the gate electrode, and a second impurity region forming a source region or a drain region disposed on the outside of the first impurity region, wherein a concentration of an impurity element of one conductivity type in a region oft he first impurity region that overlaps the gate electrode is set to become higher as the distance from channel forming regions that are in contact increase. 22. A semiconductor device comprising:
a pixel section comprising at least one pixel TFT over a substrate; a driver circuit comprising at least one n-channel TFT and at least one p-channel TFT over the substrate: a first interlayer insulating film comprising an inorganic insulating material over the pixel TFT; a second interlayer insulating film comprising an organic insulating material over the first interlayer insulating film; and at least one pixel electrode having a light transmitting property over the second interlayer insulating film, and connected to a conductive metal wiring connected to the pixel TFT through an opening disposed in the first interlayer insulating film and the second interlayer insulating film, wherein each of the pixel TFT and the n-channel TFT comprises a gate electrode having a tapered portion, a channel forming region, a first impurity region forming an LDD region disposed in contact with the channel forming region and so as to partly overlap the gate electrode, and a second impurity region forming a source region or a drain region disposed on the outside of the first impurity region, wherein a concentration of an impurity element of one conductivity type in a region of the first impurity region that overlaps the gate electrode is set to become higher as the distance from channel forming regions that are in contact increase. 23. A semiconductor device holding a liquid crystal between a first substrate and a second substrate comprising:
a pixel section comprising at least one pixel TFT over the first substrate; a driver circuit comprising at least one n-channel TFT and at least one p-channel TFT over the first substrate; a first interlayer insulating film comprising an inorganic insulating material over the pixel TFT; a second interlayer insulating film comprising an organic insulating material over the first interlayer insulating film; and at least one pixel electrode having a light reflective surface over the second interlayer insulating film, and connected to the pixel TFT through an opening disposed in the first interlayer insulating film and the second interlayer insulating film, wherein each of the pixel TFT and the n-channel TFT comprises a gate electrode having a tapered portion, a channel forming region, a first impurity region forming an LDD region disposed in contact with the channel forming region and so as to partly overlap the gate electrode, and a second impurity region forming a source region or a drain region disposed on the outside of the first impurity region, wherein a concentration of an impurity element of one conductivity type in a region of the first impurity region that overlaps the gate electrode is set to become higher as the distance from channel forming regions that are in contact increase, wherein the first substrate is stuck to the second substrate formed on a transparent conductive film, through at least one columnar spacer formed above the opening. 24. A semiconductor device holding a liquid crystal between a first substrate and a second substrate comprising:
a pixel section comprising at least one pixel TFT, over the first substrate; a driver circuit comprising at least one n-channel TFT and at least one p-channel TFT over the first substrate; a first interlayer insulating film comprising an inorganic insulating material over the pixel TFT; a second interlayer insulating film comprising an organic insulating material over the first interlayer insulating film; and at least one pixel electrode having a light transmitting property over the second interlayer insulating film, and connected to a conductive metal wiring connected to the pixel TFT through an opening disposed in the first interlayer insulating film and the second interlayer insulating film, wherein each of the pixel TFT and the n-channel TFT comprises a gate electrode having a tapered portion, a channel forming region, a first impurity region forming an LDD region disposed in contact with the channel forming region and so as to partly overlap the gate electrode, and a second impurity region forming a source region or a drain region disposed on the outside of the first impurity region, wherein a concentration of an impurity element of one conductivity type in a region of the first impurity region that overlaps the gate electrode is set to become higher as the distance from channel forming regions that are in contact increase, wherein the first substrate is stuck to the second substrate formed on a transparent conductive film, through at least one columnar spacer formed above the opening. 25. A semiconductor device according to claim 21 wherein the gate electrodes of the pixel TFT and the p-channel TFT and the n-channel TFT of the driver circuit comprise a heat resistant conductive material and a gate wiring that is connected to the gate electrode is extended from the driver circuit comprises a low resistivity conductive material.
26. A semiconductor device according to claim 22 wherein the gate electrodes of the pixel TFT and the p-channel TFT and the n-channel TFT of the driver circuit comprise a heat resistant conductive material and a gate wiring that is connected to the gate electrode is extended from the driver circuit comprises a low resistivity conductive material.
27. A semiconductor device according to claim 23 wherein the gate electrodes of the pixel TFT and the p-channel TFT and the n-channel TFT of the driver circuit comprise a heat resistant conductive material and a gate wiring that is connected to the gate electrode is extended from the driver circuit comprises a low resistivity conductive material.
28. A semiconductor device according to claim 24 wherein the gate electrodes of the pixel TFT and the p-channel TFT and the n-channel TFT of the driver circuit comprise a heat resistant conductive material and a gate wiring that is connected to the gate electrode is extended from the driver circuit comprises a low resistivity conductive material.
29. A semiconductor device according to claim 25 wherein the heat resistant conductive material is selected from a group consisting of: an element selected from tantalum (Ta), titanium (Ti) or tungsten (W); a compound which comprises the element; a compound which comprises a combination of the element; a nitride which comprises the element; and a suicide which comprises the element.
30. A semiconductor device according to claim 26 wherein the heat resistant conductive material is selected from a group consisting of: an element selected from tantalum (Ta), titanium (Ti) or tungsten (W); a compound which comprises the element; a compound which comprises a combination of the element; a nitride which comprises the element; and a silicide which comprises the element.
31. A semiconductor device according to claim 27 wherein the heat resistant conductive material is selected from a group consisting of: an element selected from tantalum (Ta), titanium (Ti) or tungsten (W); a compound which comprises the element; a compound which comprises a combination of the element a nitride which comprises the element; and a suicide which comprises the element.
32. A semiconductor device according to claim 28 wherein the heat resistant conductive material is selected from a group consisting of: an element selected from tantalum (Ta), titanium (Ti) or tungsten (W); a compound which comprises the element; a compound which comprises a combination of the element; a nitride which comprises the element; and a silicide which comprises the element.
33. A semiconductor device according to claim 21 wherein an angle of the tapered portion of the gate electrode is between 5 and 45�.
34. A semiconductor device according to claim 22 wherein an angle of the tapered portion of the gate electrode is between 5 and 45�.
35. A semiconductor device according to claim 23 wherein an angle of the tapered portion of the gate electrode is between 5 and 45�.
36. A semiconductor device according to claim 24 wherein an angle of the tapered portion of the gate electrode is between 5 and 45�.
37. A semiconductor device according to claim 21 wherein the semiconductor device is one selected from a group consisting of: a personal computer; a video camera; a portable information terminal; a digital camera, a digital video disc player; an electronic game machine; and a projector.
38. A semiconductor device according to claim 22 wherein the semiconductor device is one selected from a group consisting of: a personal computer; a video camera; a portable information terminal; a digital camera, a digital video disc player; an electronic game machine; and a projector.
39. A semiconductor device according to claim 23 wherein the semiconductor device is one selected from a group consisting of: a personal computer; a video camera; a portable information terminal; a digital camera, a digital video disc player; an electronic game machine; and a projector.
40. A semiconductor device according to claim 24 wherein the semiconductor device is one selected from a group consisting of: a personal computer; a video camera; a portable information terminal; a digital camera, a digital video disc player; an electronic game machine; and a projector.
However, there is another point that must be given attention to besides the above off current value and the on current value. For example, the bias state of the pixel TFT and the TFT of the driver circuit such as the shift resist circuit or the buffer circuit is not necessarily the same. For example, in the pixel TFT, a large reverse bias (a negative voltage in an n-channel TFT) is applied to a gate, whereas the TFT of the driver circuit basically does not operate in the reverse bias state. Also, regarding the operating velocity, the pixel TFT may be {fraction (1/100)} or less than that of the TFT of the driver circuit. The GOLD structure is highly effective in preventing the deterioration of the on current value, but on the other hand, there arises a problem in that the off current value becomes higher compared with the usual structure of an LDD. Therefore, the GOLD structure is not a preferred structure for applying to the pixel TFT. Contrarily, although the usual structure of the LDD is highly effective in suppressing the off current value, it has a low effect in relaxing :the electric field in the vicinity of a drain and in preventing deterioration caused by the hot carrier injection. It is thus not always preferable to form all TFTs to have the same structure in a semiconductor device that has a plurality of integrated circuits different from one another in the operation condition, as in active matrix liquid crystal display device. The problem as such becomes apparent especially as the characteristics of crystalline silicon TFTs are enhanced and more is demanded for the performance of active matrix liquid crystal display devices.
Thus, while reducing the number of photomasks, appropriate structures of TFTs arranged in various circuits are formed in accordance with the respective circuits. Specifically, it is desired that in the structure of a TFT for functioning as a. switching element, importance be placed on reducing the off current value rather than the operating speed. A multi-gate structure is adopted as such a structure. On the other hand, the structure of a TFT to be provided in the driver circuit in which high speed operation is required, it is desired that importance be placed on increasing the operating speed, and at the same time, on repressing degradation caused by hot carrier injection, which becomes a serious problem as the operating speed is increased. Various ideas have been added to the LDD region of the TFT to construct such a structure. In other words, the LDD region provided between the channel forming region and the drain region is characterized by having a concentration gradient in which the concentration of conductivity controlling impurity element gradually rises as it nears the drain region. This structure is remarkably effective in relaxing the electric field that will concentrate in a depletion layer in the vicinity of the drain region.
The material used for forming the gate electrode is a heat-resistant conductive material formed from an element chosen from the group consisting of tungsten (W), tantalum (Ta), and titanium (Ti), or a compound or an alloy having the above elements as a constituent. Speedy and precise etching is performed on such heat-resistant conductive materials, and to further form the edge portion into a taper shape, dry etching, using high-density plasma is applied. As a means of achieving high-density plasma, an etching apparatus that utilizes a microwave or ICP (Inductively Coupled Plasma) is suitable. Particularly, the ICP etching apparatus can easily control plasma as well as deal with the operation of processing a large area surface substrate.
FIG. 19A schematically shows the structure of such a plasma treatment apparatus (for example, an etching apparatus) using ICP. An antenna coil 903 is arranged on a quartz substrate 905 in the upper portion of the reaction space, and the antenna coil 903 is connected to a first high frequency power source 901 through a matching box 907. The first high frequency power source 901 is set to between 6 and 60 MHz, typically 13.56 MHz. Further, a second high frequency power source 902 is connected through: a matching box 912 to a lower electrode 904 that holds a substrate 906 which is the piece to be processed. The second high frequency power source 902 is set to between 100 kHz and 60 MHz (for example between 6 and 29 MHz). If a high frequency electric power is applied to the antenna coil 903, then a high frequency current J flows in the θ direction in the antenna coil 903 and a magnetic field B develops in the Z direction (Equation 1). An induced electric field E develops in the θ direction in accordance with Faraday's law of electromagnetic induction (Equation 2).
μ0J=r o t B (Equation 1)
If the etching apparatus using the ICP to which such multi-spiral coil is applied is employed, then the etching of the heat-resistant conductive materials may be performed well. A dry etching apparatus using the multi-spiral ICP of Matsushita Electric Corp. (model E645-ICP) is employed here. Shown in FIGS. 20A and 20B are the results of examining the taper shape of the patterned edge portion of a W film, which has been formed into a given pattern on the glass substrate. Here, the angle of the taper portion is defined as the angle of the inclination portion of the taper portion and. the substrate surface (level surface) (the angle indicated by θ1 in FIG. 4). As common conditions, the electric discharge power (high frequency power to be applied to the coil, 13.56 MHz) is set to 3.2 W/cm2, the pressure is set to 1.0 Pa, and CF4 and Cl2 are used as the etching gas. FIG. 20A shows the dependency of the angle of the taper portion on the bias power (13.56 MHz) to be applied to the substrate. The flow rate of the etching gas CF4 and Cl2 are both set to 30 SCCM. It has become apparent that the angle of the taper portion can be altered between 70� and 20� within a range of the bias power 128 to 384 mW/cm2.
Using a first photomask (PM1),a resist pattern is then formed on the crystalline semiconductor layer 103 b by employment of a photolithography technique. Then the crystalline semiconductor layer is partitioned into islands by dry etching to from island semiconductor layers 104 to 108 as shown in FIG. 1C. A mixed gas of CF4 and O2 is used in the dry etching of the crystalline silicon film.
With respect to this type of island semiconductor layers, an impurity element that imparts p-type may be doped into the entire surface of the island semiconductor layers at a concentration of about 1�1016 to 5�1017 atoms/cm3 in order to control the threshold voltage (Vth) of the TFT. Periodic table group 13 elements such as boron (B), aluminum (Al), and gallium (Ga) are known as impurity elements which impart p-type to a semiconductor. Ion implantation and ion doping (or ion shower doping) can be used as the doping method. The ion doping is suitable for forming a large area substrate as a source gas. Boron (B) is doped here by ion doping using diborane (B2H6). Doping of impurity elements as such is not always necessary and there is no obstacle in omitting it, but it is a method appropriately used especially for placing the threshold voltage of the n-channe TFT within a predetermined range.
On the other hand, when using a TaN film for the conductive layer (A) 110, and Ta film for the conductive layer (B) 111, similarly both films may be formed by sputtering. The TaN film is formed using Ta as a target and a mixed gas of Ar and nitrogen as a sputtering gas. The Ta film is formed using Ar as the sputtering gas. Further, if a suitable amount of Xe or Kr is added to these sputtering gasses, then the internal stresses in the films formed can be relieved, and peeling can be prevented. The resistivity of an α-phase Ta film is about 20 μΩcm and it can be suitably used in the gate electrode, but a β-phase Ta film has a resistivity of about 180 μΩcm and it is unsuitable for the gate electrode. A TaN film possesses a crystal structure which is close to the α-phase, and therefore the α-phase Ta film can be easily obtained provided that a Ta film is formed on the TaN film. Note that although not shown in the figures, it is effective to form a silicon film doped with phosphorus (P), with a thickness of about 2 to 20 nm, below the conductive layer (A) 110. By doing so, along with improving the adhesiveness of the conductive film formed on the silicon film and preventing oxidation, trace amounts of alkaline metal elements contained in the conductive layer (A) 110 or in the conductive layer (B) 111 can be prevented from diffusing into the gate insulating film 109 . Whichever is done, it is preferable that the resistivity of the conductive layer (B) 111 be in the range of 10 to 50 μΩcm.
At this point, the etching is carried out such that at least taper portions are formed at edge portions of the gate electrodes 118 to 122. The ICP etching apparatus is used in this etching process and the details of this technique are as explained above. Etching is performed at the following specific etching conditions: a mixed gas of CF4 and Cl2 is used as the etching gas, their flow rates are set to 30 SCCM, respectively, the electric discharge power is set to 3.2 W/cm2 (13.56 MHz), the bias power is set to 224 mW/cm2 (13.56 MHz), and the reaction pressure is set to 1.0 Pa. In the edge portions of the gate electrodes 118 to 122, taper portions that gradually increase in thickness inwards from the edge portions are formed under such etching conditions. The angles of these taper portions are 5� to 45�, preferably 10� to 30�. An angle of the taper portions is the angle illustrated in FIG. 4 as θ1. The angle θ1 greatly influences the concentration gradient of a first impurity region for forming LDD regions in a later step. It is to be noted that the angle of the taper portion θ1 is expressed as Tan (θ1)=HG/WG, wherein (WG) is the length of the taper portions and (HG) is the thickness of the taper portions.
Thereafter, a first interlayer insulating film 142 is formed on the gate electrode and the gate insulating film as shown in FIG. 3A. It is appropriate to form the first interlayer insulating film from the silicon oxide film, the silicon oxynitride film, the silicon nitride film, or a laminate film of a combination of these films. Whichever it is, the first interlayer insulating film 142 is formed from an inorganic insulating material. The film thickness of the first interlayer insulating film 142 is between 100 and 200 nm. For the case of using the silicon oxide film here, the silicon oxide film can be formed by plasma CVD in which TEOS and O2 are mixed, the reaction pressure is set to 40 Pa, and the substrate temperature is set between 300� C. and 400� C., and electric discharge is conducted at a high frequency (13.56 MHz) power density of 0.5 to 0.8 W/cm2. Also, when using the silicon oxynitride film, it may be formed from a silicon oxynitride film that is manufactured from SiH4, N2O, and NH3, or from SiH4 and N2O by plasma CVD. In this case, the manufacturing conditions are as follows: the reaction pressure is set to between 20 and 200 Pa, and the substrate temperature is set between 300� C. and 400� C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W/cm2. Further, a hydrogenated silicon oxynitride film that is manufactured from SiH4, N20, and H2 is also applicable. Similarly, the silicon nitride film may also be manufactured from SiH4 and NH3 by plasma CVD.
By forming the second interlayer insulating film with an organic insulating material in this way, a good flat surface can be formed. In addition, organic resin materials are generally low in dielectric, and therefore parasitic capacitance can be reduced. However, because the second interlayer insulating film has absorbency, it is not suitable as a protecting film. Therefore, as in this embodiment, the silicon oxide film the silicon nitride oxide film, the silicon nitride film, or a combination of these films that form the first interlayer insulating film 142 may be combined with the organic insulating film for the second interlayer insulating film.
A predetermined patterned resist mask is formed next by using a fifth photomask (PM5), and contact holes that reach the source regions and the drain regions formed in the respective island semiconductor layer are formed. These contact holes are formed by means of dry etching. In this case, first the second interlayer insulating film 143 made of an organic resin material is etched using a mixed gas of CF4, O2 and He as etching gas, and then the first interlayer insulating film 142 is etched with CF4 and O2 as etching gas. Furthermore, in order to raise the selective ratio with the island semiconductor layer, the etching gas is switched to CHF3 to etch the gate insulating film 130 whereby a contact hole can be nicely formed.
A conductive metallic film is formed next by sputtering or vacuum evaporation. Then a resist mask pattern is formed by using a sixth photomask (PM6) and then etched to thereby form source wirings 144 to 148 and drain wirings 149 to 153. The drain wiring 153 here is for functioning as the pixel electrode. A drain wiring 154 indicates the pixel electrode belonging to a neighboring pixel. Although not shown in the figures, in this embodiment, these wirings are formed such that a Ti film is formed at a thickness of between 50 and 100 nm, a contact is formed with a semiconductor film that forms the source or the drain region of the island semiconductor layer, and an aluminum (Al) film is formed at a thickness of between 300 and 400 nm superposing the Ti film(indicated by the reference numerals 144 a to 154 a in FIG. 3C). A transparent conductive film is further formed on top of the aluminum film at a thickness of between 80 and 120 nm (indicated by the reference numerals 144 b to 154 b in FIG. 3C). An indium oxide/zinc oxide alloy (In2O3—ZnO) and a zinc oxide (ZnO) are also suitable materials for the transparent conductive film. In order to further improve the transmissivity of visible light and conductivity, zinc oxide added with gallium (Ga) (ZnO:G), etc. may be used preferably.
Thereafter, similar to Embodiment 1, by forming the second interlayer insulating film 147 made of an organic insulating material, source wirings 148 to 151 and 167, and drain wirings 153 to 156 and 168, the active matrix substrate can thus be completed. FIGS. 6A and 6B show top views of this state, and the cross sections taken along the line B-B′ of FIG. 6A and the line C-C′ of FIG. 6B correspond to the A-A′ and C-C′ cross sections, respectively, in FIG. 5C. Although the gate insulating film, the first interlayer insulating film, and the second interlayer insulating are omitted from the FIGS. 6A and 6B, the source and drain regions of the island semiconductor layers 104, 105, and 108 not shown in the figure are connected to the source wirings 144, 145 and 148, and drain wirings 149, 150 and 153 through contact holes. Further, the cross sections taken along the line D-C′ of FIG. 6A and the line E-E′ of FIG. 6B are shown in FIGS. 7A and 7B, respectively. The gate wiring 233 is formed overlapping the gate electrodes 118 and 119, and the gate wiring 234 is formed overlapping the gate electrode 122 in the outside of the island semiconductor layers 104, 105, and 108. Thus, the conductive layer (C) and the conductive layer (D) are in close contact to be electrically communicated. By forming the gate wiring from a low-resistant conductive material in this way, the wiring resistance can be sufficiently reduced. Accordingly, the present invention can be can be applied to a display device that has pixel portion (screen size) of 4-inch class or more.
Similarly, FIGS. 12A to 12C also show an example of a crystallization method using a catalytic element in which a layer containing a catalytic element is formed by sputtering. First, base films 1202 a and 1202 b and a semiconductor layer 1203 having an amorphous structure formed at a thickness of between 25 to 80 nm are formed over a glass substrate 1201 similar to Embodiment 1. Then about a 0.5 to 5 nm thick oxide film is formed on the surface of the semiconductor layer 1203 having an amorphous structure (not shown in the Figure). As an oxide film having such thickness, an appropriate coating may be actively formed by plasma CVD or sputtering, but the oxide film may also be formed by exposing the surface of the semiconductor layer 1203 having an amorphous structure to an oxygen atmosphere in which the substrate has been heated at 100� C. to 300� C. and plasma treated, or exposing the surface of the semiconductor layer 1203 having an amorphous structure to a solution containing hydrogen peroxide (H2O2). The oxide film may also be formed by irradiating infrared light into an atmosphere containing oxygen to generate ozone and then exposing the semiconductor layer 1203 having an amorphous structure to the ozone atmosphere.
A method of manufacturing an active matrix liquid. crystal display device from the active matrix substrate fabricated in Embodiment 1 will be explained here in this Embodiment. As shown in FIG. 14A, first a spacer made from a column-shape spacer is formed on the active matrix substrate in the state of FIG. 3C. The spacer may be provided by a method of spraying several μm of grains. A method of forming the spacer by patterning after forming a resin film on the entire surface of the substrate is adopted here in this embodiment. The material for such kind of spacer is not limited. For example, using the JSR product NN700, after application to the substrate by a spinner, a predetermined pattern is formed by exposure and development treatment. Furthermore, it is cured by being heated in a clean oven at 150� C. to 200� C. The shape of the spacer formed in this way may be made different depending on the conditions of the exposure and development treatment. As shown in FIG. 15, the spacer is formed so that its shape becomes a column-shape with a flat top, which is a preferred shape because when an opposing substrate is bonded to this substrate, its mechanical strength as a liquid crystal display panel can be ensured. The shape of the spacer such as a conical shape or a pyramid shape is not specially limited thereto. For example, when the spacer is a conical shape, its specific measurements are as follows: the height H is set between 1.2 and 5 μm, the average radius L1 is set between 5 and 7 μm, and the ratio of the average radius L1 and the radius of the bottom portion L2 is set to 1 to 1.5. The taper angle of the side surface at this point is �15� or less.
Thereafter, an alignment film 407 is formed. A polyimide resin is often used for the alignment film of a liquid crystal display device. After forming the alignemnt films, a rubbing process is performed so that the liquid crystal molecules are oriented with a certain fixed pre-tilt angle. The rubbing process is performed such so that an area of 2 μm or less from the edge portion of the column-shape spacer 406 provided in the pixel portion to the rubbing direction, is not rubbed. Further, since the generation of static electricity from the rubbing process is often a problem, an effect of protecting the; TFT from the static electricity can be attained by forming the spacers 405 a to 405 e formed on the TFT of the driver circuit. Although not described in the figures, the substrate may have a structure in which the alignment film 407 is formed before forming the spacers 406 and 405 a to 405 e. A light shielding film 402, a transparent conductive film 403, and an alignment film 404 are formed on an opposing substrate 401, which is opposed to the active matrix substrate. The light shielding film 402 is formed of films such as a Ti film, a Cr film, and an Al film at a thickness of between 50 and 300 μm. The active matrix substrate, on which the pixel portion and the driver circuit are formed, and the opposing substrate are then joined together by a sealing agent 408. A filler (not shown in the figures) is mixed into the sealing agent 408, and the two substrates are joined together with a uniform spacing by the filler and the spacers 406 and 405 a to 405 e. Next, a liquid crystal material 409 is injected between both substrates. A known liquid crystal material may be used as the liquid crystal material. For example, besides the TN liquid crystal, a thresholdness antiferroelectric mixed liquid crystal that indicates electro-optical response characteristics of continuously changing transmittance with respect to an electric field may also be used. Among such thresholdness antiferroelectric mixture liquid crystal, there is a type that indicates a V-shaped electro-optical response characteristic. In this way the active matrix type liquid crystal display device shown in FIG. 14B is completed.
In FIG. 14A the column-shape spacer 406 provided in the pixel portion may be provided not only to each pixel, but also to every several pixels or several tens of the pixels arranged in a matrix manner as shown in FIG. 16. In other words, it is possible to set the ratio of the total number of pixels composing the pixel portion to the number of spacers between 20% and 100%. In addition, the spacers 405 a to 405 e provided in the driver circuits portion may be formed so as to cover the entire surface of the circuits, or may be provided in accordance with the position of the source wiring and the drain wiring of each TFT. In FIG. 16, reference numerals 610 to 612 denote the arrangement of the spacers provided in the driver circuits portion. In FIG. 16, the sealing agent 619 is formed on the exterior of the pixel portion 604, the scanning signal driver circuit 605, the image signal driver circuit 606, and the signal processing circuit 607 of the other circuits, and on the interior of an external input/output terminal 602, that are formed over the substrate 101,.
Next, the structure of this kind of active matrix liquid crystal display device is explained using the perspective view of FIG. 17. In FIG. 17, the active matrix substrate comprises the pixel portion 604, the scanning signal driver circuit 605, the image signal driver circuit 606, and the signal processing circuit 607 of the other circuits formed over the glass substrate 101. The pixel TTF 204 and the storage capacitor 205 are provided in the pixel portion 204, and the driver circuit formed in the periphery thereof is structured based on a CMOS circuit. The scanning signal driver circuit 605 and the image signal driver circuit 606 are connected to the pixel TFT 204 by the gate wiring 122 and the source wiring 148, respectively, extending to the pixel portion 604. Further, an FPC (flexible print circuit) 613 is connected to the external input/output terminal 602 to be utilized for inputting signals such as image signals. The FPC 613 is firmly adhered in this area by a strengthening resin 614. The connecting wiring 603 is connected to the respective driver circuits. Further, though not shown in the figure, a light shielding film and a transparent conductive film are provided on the opposing substrate 401.
The image signal driver circuit 606 comprises a shift resister circuit 501 a, a level shifter circuit 502 a, a buffer circuit 503 a, and a sampling circuit 504. In addition, the scanning signal driver circuits (A) and (B) 185 comprises of a shift resister circuit 501 b, a level shifter circuit 502 b, and a buffer circuit 503 b. The driving voltages of the shift resister circuits 501 a and 501 b are between 5 and 16V (typically 10V). A TFT of a CMOS circuit for forming this circuit is formed of the first p-channel TFT (A) 200 a and the first n-channel TFT (A) 201 a of FIG. 3C, or the TFT may be formed of the first p-channel TFT (B) 200 b and the first n-channel TFT (B) 201 b shown in FIG. 8A. In addition, since the driving voltage of the level shifter circuits 502 a and 502 b and the buffer circuits 503 a and 503 b become as high as 14 to 16V, it is preferable that the TFT structure be formed into a multi-gate structure as shown in FIG. 8A. Forming the TFT into a multi-gate structure is effective in raising voltage-resistance and improving the reliability of the circuits.
The sampling circuit 504 comprises an analog switch and its driving voltage is between 14 to 16V. Since the polarity alternately reverses to be driven and there is a necessity to reduce the off current value, it is desired that the sampling circuit 504 be formed of the second p-channel TFT (A) 202 a and the second n-channel TFT (A) 203 a as shown in FIG.3C. Alternatively, the sampling circuit may be formed of the second p-channel TFT (B) 200 b and the second n-channel TFT (B) 201 b of FIG. 8B in order to effectively reduce the off current value.
Further, the driving voltage of the pixel portion is: between 14 and 16 V. From a viewpoint of reducing power consumption, there is a demand to further reduce the off current value than that of the sampling circuit. Accordingly, as a basic structure, the pixel portion is formed into a multi-gate structure as the pixel TFT 204 shown in FIG. 3C.
Note that the structure of this Embodiment can be readily realized by manufacturing the TFT in accordance with the steps shown in Embodiments 1 through 3. The structures of the pixel portion and the driver circuits only are shown in this embodiment. Other circuits such as a signal divider circuit, a frequency dividing circuit, a D/A converter, a γ correction circuit, an op-amp circuit, and further signal processing circuits such as a memory circuit and an arithmetic operation circuit, and still further a logic circuits may all be formed on the same substrate in accordance with the processes of Embodiments 1 through 3.
FIG. 22E shows a digital camera, which is composed of a main body 2501, a display device 2502, an eye piece portion 2503, operation switches 25 04, and an image receiving unit (not shown in the figure). The present invention can be applied to the display device 2502 and to other signal control circuits.
In a TFT having the gate electrode formed from a heat-resistant conductive material and the gate wiring formed from a low-resistant conductive material, the active matrix substrate structure in which LDD regions of the p-channel TFT of the driver circuit is formed to overlap the gate electrode, and LDD structure of the n-channel TFT and the pixel TFT are made to partially overlap the gate electrodes, can be manufactured by using 6 photomasks in accordance with the manufacturing method of the semiconductor device of the present invention. The reflection type liquid crystal display device: can be manufactured from this kind of active matrix substrate. In addition, the transmission type liquid crystal display device can be manufactured by using 7 photomasks in accordance with the manufacturing method of the present invention.
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HIDEOMI;ONO, KOJI;AND OTHERS;REEL/FRAME:013014/0910;SIGNING DATES FROM 20000630 TO 20000703Sep 8, 2006FPAYFee paymentYear of fee payment: 4Sep 1, 2010FPAYFee paymentYear of fee payment: 8Nov 7, 2014REMIMaintenance fee reminder mailedApr 1, 2015LAPSLapse for failure to pay maintenance feesMay 19, 2015FPExpired due to failure to pay maintenance feeEffective date: 20150401RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services