Source: http://www.google.es/patents/US20040026696
Timestamp: 2017-12-16 05:34:07
Document Index: 430529434

Matched Legal Cases: ['art 220', 'art 3003', 'art 3003', 'art 3011', 'art 3012', 'art 3013', 'art 3016', 'art 3012', 'art 3021', 'art 3023', 'art 3023', 'art 3031', 'art 3033', 'art 3033', 'art 3041', 'art 3042', 'art 3042', 'art 3051', 'art 3053', 'art 3061', 'art 3062', 'art 3063', 'art 3064', 'art 3064']

Patente US20040026696 - Semiconductor element and semiconductor device using the same - Google Patentes
A semiconductor element with high current drive capability, capable of high-speed operation, and having little variation in pluralities of semiconductor elements is provided. It is characterized by the fact that semiconductor elements have a first crystalline semiconductor region including pluralities...http://www.google.es/patents/US20040026696?utm_source=gb-gplus-sharePatente US20040026696 - Semiconductor element and semiconductor device using the same
Número de publicación US20040026696 A1
Número de solicitud US 10/377,725
También publicado como CN1444285A, CN100350617C, CN101217150A, CN101217150B, US7705357
Número de publicación 10377725, 377725, US 2004/0026696 A1, US 2004/026696 A1, US 20040026696 A1, US 20040026696A1, US 2004026696 A1, US 2004026696A1, US-A1-20040026696, US-A1-2004026696, US2004/0026696A1, US2004/026696A1, US20040026696 A1, US20040026696A1, US2004026696 A1, US2004026696A1
Inventores Shunpei Yamazaki, Kiyoshi Kato, Atsuo Isobe, Hidekazu Miyairi, Hideomi Suzawa
Citas de patentes (83), Citada por (51), Clasificaciones (34), Eventos legales (2)
Semiconductor element and semiconductor device using the same
US 20040026696 A1
Recesses may satisfactorily be formed by direct etching processing over the surface of the insulating substrate, or may be formed by indirect etching processing using silicon oxide, silicon nitride or silicon oxynitride film and carrying out etching processing of those films. Recesses are formed according to a semiconductor element, and the arrangement of the island-shaped semiconductor film including a channel formation region of a transistor especially, and preferably formed in agreement with the channel formation region at least. Moreover, the recesses are provided in an extending manner in the direction of channel length. The width of the recesses (the channel width direction in case of defining as a channel formation region) is formed by 0.01 μm or more and 2 μm or less, or formed by 0.1 μm to lm preferably, and the depth is formed by 0.1 μm or more and 3 μm or less, or 0.1 μm or more and 2 μm or less preferably.
[0027]FIG. 1 is a perspective view explaining a crystallization method of this invention.
[0028]FIG. 2 is a perspective view explaining a crystallization method of this invention.
[0029]FIG. 3 is a perspective view explaining a crystallization method of this invention.
[0030]FIG. 4 is a perspective view explaining a crystallization method of this invention.
[0031]FIGS. 5A to 5E are longitudinal sectional views explaining the relation of the form of an aperture part and the form of a crystalline semiconductor film in crystallization.
[0032]FIGS. 6A to 6D are a top view and longitudinal sectional views explaining a manufacture process of a transistor of this invention.
[0033]FIGS. 7A to 7D are a top view and longitudinal sectional views explaining the manufacture process of a transistor of this invention.
[0034]FIGS. 8A to 8D are a top view and longitudinal sectional views explaining the manufacture process of a transistor of this invention.
[0035]FIGS. 9A to 9E are a top view and longitudinal sectional views explaining the manufacture process of a transistor of this invention.
[0036]FIGS. 10A to 10E are a top view and longitudinal sectional views explaining the manufacture process of a transistor of this invention.
[0037]FIGS. 11A to 11F are a top view and longitudinal sectional views explaining the manufacture process of a transistor of this invention.
[0038]FIGS. 12A to 12F are a top view and longitudinal sectional views explaining the manufacture process of a transistor of this invention.
[0039]FIGS. 13A to 13C are longitudinally sectional views showing an example of a gate structure applicable in a transistor of this invention.
[0040]FIGS. 14A to 14F are a top view and longitudinally sectional views explaining the manufacture process of a transistor of this invention.
[0041]FIGS. 15A to 15F are a top view and longitudinally sectional views explaining the manufacture process of a transistor of this invention.
[0042]FIGS. 16A to 16C are longitudinally sectional views explaining the manufacture process of a transistor of this invention.
[0043]FIG. 17 is a longitudinally sectional view explaining the manufacture process of a transistor of this invention.
[0044]FIGS. 18A to 18D are a top view and longitudinally sectional views explaining the manufacture process of a transistor of this invention.
[0045]FIG. 19 is an external view showing an example of a semiconductor device of this invention.
[0046]FIGS. 20A to 20G are views showing an example of an electronic device of this invention.
[0047]FIG. 21 is a view showing a laser irradiation device used for operation of this invention.
[0048]FIGS. 22A to 22D are views showing the constitution of a laser beam used for operation of this invention.
[0049]FIGS. 23A and 23B are a TEM photograph and its schematic diagram observing the upper surface of a crystalline silicon film obtained by this invention after Seco etching of the crystalline silicon film.
[0050]FIGS. 24A and 24B are a TEM photograph and its schematic diagram observing the upper surface of the crystalline silicon film obtained by this invention after Seco etching of the crystalline silicon film.
[0051]FIG. 25 is EBSP mapping data showing the crystal orientations formed in recesses.
[0052]FIGS. 26A and 26B are a TEM photograph and its schematic diagram observing the upper surface of the crystalline silicon film obtained by this invention.
[0053]FIGS. 27A and 27B are a TEM photograph and its schematic diagram observing the section of the crystalline silicon film.
[0054]FIGS. 28A and 28B are a TEM photograph and its schematic diagram observing the section of the crystalline silicon film.
[0055]FIGS. 29A and 29B are longitudinally sectional views explaining the manufacture process of a transistor of this invention.
[0078]FIG. 5 is a conceptual diagram showing the information of the crystallization obtained from the experiment result by this inventor. FIG. 5A to FIG. 5E is a schematic diagram showing the relation between the depth and interval of recesses formed by a first insulating film and a second insulating film, and a crystal growth.
t02:thickness of the amorphous semiconductor films of recesses;
[0087]FIG. 5A is a view showing the case where d<t02, W1 and W2 are comparable to 1 μm or less, when the depth of the recesses is smaller than the amorphous semiconductor film 204, since the recesses are shallow even after subjected to the melting crystallization process, the surface of the crystalline semiconductor film 205 is not planarized enough. Namely, the surface state of the crystalline semiconductor film 205 is in the state where the irregular form of a ground material is reflected.
[0088]FIG. 5B is a view showing the case where d≧t02, and W1, W2 are comparable to 1 μm or less. In the case where the depth of the recesses almost equal to the amorphous semiconductor film 203 or larger, surface tension works so as to be collected in the recesses. Thereby the surface becomes almost flat as shown in FIG. 5B under solidified state. In this case, it is set to t11<t12, and stress concentrates on the thin part 220 of the second insulating film 202, with the result that deviation is accumulated here and the crystal grain boundary is formed thereon.
[0091]FIG. 23B is a schematic diagram of the photograph of FIG. 23A. In this figure, numeral 31 denotes an insulating film (a second insulating film) extending in linear stripe pattern. Situation that the crystal grain boundary 33 exposed by secco etching and intensively collected in projection 32 can be checked. In addition, region 34 indicated to be a disappearance portion is a field equivalent to the starting point of the stripe pattern, and the scan of laser beams is started from this starting point. Detailed reason is unknown. However, this is a region where the second insulating film located in this starting point is exposed when the silicon film on this starting point is melted, thereby being pushed aside in the scanning direction. Since secco-solution etches silicon oxide films, the region located on this starting point has been disappeared by the secco etching.
[0096]FIG. 5C is a view showing the case where d≧t02 and W1, W2 are comparable to 1 μm or a little larger. When the width of recesses spreads, the recesses are filled up with crystalline semiconductor film 205, having influence on planarizing. However, crystal grain boundary occurs near the center of the recesses. Also, stress concentrates similarly on the second insulating film, accumulating deviation here, and a crystal grain boundary is formed. It is estimated that when an interval spreads, stress relief effect is decreased. Since crystal grain boundary may arise also in a semiconductor region used as a channel formation region on this condition, it is not preferable.
[0097]FIG. 5D is a view showing a case where d≧t02 and W1, W2 are larger than 1.0 μm, wherein the state of FIG. 5C is further exposed. The current state is an unfavorable situation due to a crystal grain boundary which is highly likely to generate in a semiconductor region serving as a channel formation region.
[0100]FIG. 5E is a referential example in this invention, showing the case where d>>t02, and W1, W2 are 1 μm or less. Namely, when thickness d of the second insulating film is too thick compared with thickness t02 of the amorphous semiconductor film in recesses, formation is made in such a way that the recesses are filled up with the crystalline semiconductor film 204, hardly remaining on the second insulating film 203. Therefore, the crystalline semiconductor film on the second insulating film cannot be used as this invention shows, as a contact part of a source region and a source electrode (or a drain region and a drain electrode).
In addition, at the time of the crystallization process, the effect that the second insulating film eases the stress by contraction of the semiconductor film can be expected in case the second insulating film is a soft insulating film (Low density insulating film), as described above. On the contrary, in case of a hard insulating film (High density insulating film), stress occurs so as to oppose the contraction or expansion of the semiconductor film. Therefore, stress deviation after crystallization is likely to be left, causing a crystal defect. For example, with well-known Graphoepitaxy use (“M. W. Geis, D. C. Flanders, H. I. Smith: Appl. Phys. Lett. 35 (1979) pp71”), irregularities on a substrate is directly formed by hard quartz glass. In this case, it becomes clear that orientation axis of crystal Si is a [100] axis, and main orientation axis is {100} surface.
Next, as shown in FIG. 7, the third insulating film 305 consisting of oxidation film and silicon oxynitride film, and the amorphous silicon film 306 are formed continuously on the first insulating film 302 and the second insulating film 303 using the same plasma CVD apparatus and without exposing to an atmosphere. The amorphous silicon film 305 is formed by the semiconductor film containing silicon as the main composition, and formed by the plasma CVD method using SiH4 as material gas. In this stage, as shown in the figure, the bottom and the flank side of recess 304 are covered, presenting the surface which is not flat.
The structure of a transistor shown in FIG. 13A is an example of forming a gate electrode by nitride metal 340 a-such as titanium nitride or tantalum nitride, and metal 340 b of high melting point such as tungsten, or tungsten alloy. And spacer 341 is formed in the flank side of the gate electrode 340 b. Spacer 341 may be formed with either insulators such as silicon oxide or n type multi-crystal silicon in order to give conductivity, and formed by anisotropic dry etching. LDD regions 342 a and 342 b can be formed self-aligned to gate electrode 340 b, before this spacer is formed. When a spacer is formed with a conductive material, LDD regions 342 a and 342 b can be structured as Gate-Overlapped LDD structure substantially superimposed on a gate electrode.
[0180]FIG. 20A is an example where a TV set is completed with the application of this invention, which is constituted by case 3001, support stand 3002, and display part 3003. Various integrated circuits other than the display part 3003, such as various logic circuits, a high frequency circuit, a memory, a microprocessor, a media processor, and LSI for graphics, can be formed and incorporated on glass to thereby constitute a TV set according to this invention.
[0181]FIG. 20B is an example where a video camera is completed with the application of this invention, which is constituted by main part 3011, display part 3012, voice input part 3013, operation switch 3014, battery 3015, and television part 3016. Various integrated circuits other than the display part 3012, such as various logic circuits, a high frequency circuit, a memory, a microprocessor, a media processor, and LSI for graphics, can be formed and incorporated on glass to thereby constitute a video camera according to this invention.
[0182]FIG. 20C is an example where a personal computer of a note type is completed with the application of this invention, which is constituted by main part 3021, case 3022, display part 3023, and keyboard 3024. Various integrated circuits other than the display part 3023, such as various logic circuits, a high frequency circuit, a memory, a microprocessor, a media processor, LSI for graphics and code LSI, can be formed and incorporated on glass to thereby constitute a personal computer according to this invention.
[0183]FIG. 20D is an example where PDA is completed (Personal Digital Assistant) with the application of this invention, which is constituted by main part 3031, stylus 3032, display part 3033, operation button 3034, and external interface 3035. Various integrated circuits other than the display part 3033, various logic circuits, a high frequency circuit, a memory, a microprocessor, a media processor, LSI for graphics, and code LSI can be formed and incorporated on glass to thereby constitute a PDA according to this invention.
[0184]FIG. 20E is an example where a sound playback apparatus such as on-board audio device specifically is completed with the application of this invention, which is constituted by main part 3041, display part 3042, operation switch 3043 and 3044. Various integrated circuits other than the display part 3042, such as various logic circuits, a high frequency circuit, a memory, a microprocessor, a media processor, LSI for graphics, and an amplification circuit can be formed and incorporated on glass to thereby constitute an audio apparatus according to this invention.
[0185]FIG. 20F is an example where a digital camera is completed with the application of this invention, which is constituted by main part 3051, display part A 3052, eyepiece part 3053, operation switch 3054, display part B 3055, and battery 3056. Various integrated circuits other than the display part A 3052 and display part B 3055 such as various logic circuits, a high frequency circuit, a memory, a microprocessor, a media processor, LSI for graphics, and code LSI can be formed and incorporated on glass to thereby constitute a digital camera according to this invention.
[0186]FIG. 20G is an example where a cellular phone is completed, and constituted by main part 3061, voice output part 3062, voice input part 3063, display part 3064, operation switch 3065, and antenna 3066. Various integrated circuits other than the display part 3064 such as various logic circuits, a high frequency circuit, a memory, a microprocessor, a media processor, LSI for graphics, and code LSI, and LSI for cellular phone can be formed and incorporated on glass to thereby constitute a cellular phone according to this invention.
In FIG. 29A, second insulating film 602 with recesses formed on glass substrate 601 in the predetermined shape with silicon oxide or silicon oxynitride is formed. Details are the same as embodiment 3. Wet etching or dry etching is sufficient as formation of the recesses. However, dry etching using CHF3 gas is used in this embodiment. In this case, gas flux may be set to 30 to 40 sccm and reaction pressure may be set to 2.7 to 4.0 KPa, impression electric power may be set to 500W and substrate temperature may be set to 20° C.
[0225]FIG. 26A is a TEM (transmission type electron microscope) photograph in the state (state shown in FIG. 8) where the crystalline silicon film 307 is formed, and FIG. 26B is a schematic diagram of the same. Laminates of first insulating film 302 and second insulating film 303 exists in the state where it is buried completely under crystalline silicon film 307.
[0226]FIG. 27A is a cross-sectional TEM photograph observing the section of FIG. 26A, and FIG. 27B is a schematic diagram of the same. On the second insulating film 303 (recesses) formed in stripe pattern, crystalline silicon film 307 a is formed so that it may be filled up. And crystalline silicon film 307 b is formed on the upper surface part (projections) of the second insulating film 303.
[0227]FIG. 28A is a cross-sectional TEM photograph performing colonoscopic observation of the section of FIG. 27A, and FIG. 28B is a schematic diagram of the same. Third insulating film 305 is observed by this photograph. Neither crystal boundary nor defects-like things can be observed inside crystalline silicon film 307 a. This shows a very high crystallizability.
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Clasificación de EE.UU. 257/66, 257/E29.003, 257/E29.151, 257/E29.293, 257/E21.413, 257/E21.134, 257/E27.111, 257/E29.295, 257/E29.278
Clasificación internacional H01L29/786, H01L21/84, H01L21/20, H01L29/49, H01L21/77, H01L21/336, H01L29/04, H01L27/12
Clasificación cooperativa H01L29/78696, H01L29/04, H01L29/4908, H01L29/78621, H01L29/66757, H01L29/78675, H01L29/78603, H01L27/1281, H01L27/12, H01L21/2026
Clasificación europea H01L29/66M6T6F15A2, H01L27/12T, H01L29/04, H01L29/786E4C2, H01L27/12, H01L29/786S, H01L29/786B4B