Source: http://www.google.com/patents/USRE39016?dq=%22melissa+white%22
Timestamp: 2014-09-21 15:18:17
Document Index: 499907867

Matched Legal Cases: ['art. 26', 'art.\n76', 'art. 77', 'art.\n78', 'art.\n79', 'art.\n81', 'art.\n82', 'art. 83', 'art. 84', 'art.\n86', 'art.\n87', 'art.\n88', 'art.\n90', 'art. 107', 'Application No. 60', 'Application No. 60']

Patent USRE39016 - Memory module assembly using partially defective chips - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsMethods and devices for using less-than-perfect memory chips and packages in the manufacture of memory modules. In the preferred method the failed I/O lines in primary memory packages are disconnected and replaced by selected I/O lines from flawless or partially defective backup parts all mounted on...http://www.google.com/patents/USRE39016?utm_source=gb-gplus-sharePatent USRE39016 - Memory module assembly using partially defective chipsAdvanced Patent SearchPublication numberUSRE39016 E1Publication typeGrantApplication numberUS 10/242,536Publication dateMar 14, 2006Filing dateSep 11, 2002Priority dateAug 12, 1996Also published asUS6119049Publication number10242536, 242536, US RE39016 E1, US RE39016E1, US-E1-RE39016, USRE39016 E1, USRE39016E1InventorsCharles I. PeddleOriginal AssigneeCeletron Usa, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (23), Non-Patent Citations (3), Referenced by (3), Classifications (13), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMemory module assembly using partially defective chipsUS RE39016 E1Abstract Methods and devices for using less-than-perfect memory chips and packages in the manufacture of memory modules. In the preferred method the failed I/O lines in primary memory packages are disconnected and replaced by selected I/O lines from flawless or partially defective backup parts all mounted on the same module. The various processes comprise sorting of partially defective parts according to the results of wafer or packages test, judicious distribution of backup parts on a PC board module and routing of their I/O lines, optimized patching techniques and multi-level tests and repatching routines. The methods and processes are equally applicable to Chip On Board assemblies as well as package assemblies.
Images(48) Claims(109)
the method comprising the steps of: testing a plurality of independent memory parts for failed I/O data line segments; sorting the parts according to the results of the testing; identifying failed and working I/O data line segments in the sorted parts; selecting at least one primary part having at least one I/O data line failure, and at least one different partially defective backup memory part from said sorted parts; and combining working I/O data line segments of different selected memory parts, including at least one working I/O data line segment of at least one partially defective backup memory part and working I/O data line segments of a primary part to form a fully functional transparent memory module. 2. A memory module made by the method of claim 1.
testing the completed memory module as to its operational status to approve the module for use or to identify any operating problems; and, as required, changing the combination of working segments of memory parts to overcome any such identified problem. 5. A memory module formed by the method of claim 4.
comprising the steps of: assembling the selected chips as primary chips and backup chips onto a chip-on-board memory module assembly; testing the assembled module for failed I/O data lines in the chips; identifying operating I/O data line segments in the chips; and combining identified working I/O data line segments of a partially defective primary chip with a required number of working I/O data line segments of backup memory chips. 9. A chip-on-board memory module made by the method of claim 8.
pretesting the parts while in die form; and sorting the parts according to the results of the pretesting. 11. A chip-on-board memory module made by the method in claim 10.
testing the primary memory parts and the backup memory parts before mounting the parts on a board to; identify operating and failed I/O data line segments of the primary parts and of the backup memory parts; determining which operating I/O data lines from the backup memory parts to use for selectively patching failed I/O data lines segments of the primary memory parts; and substituting said determined operating I/O data lines from the backup parts for failed I/O data lines in one or more primary parts to form a completed memory module. 13. A memory module made by the method of claim 12.
testing the completed memory module as to its operational status to approve the module for use or to identify any operating problems; and, as required, the step of replacing at least one of the parts with a replacement part to overcome any such identified operating problem. 16. A memory module made by the method of claim 15, wherein the memory module comprises all good, partially defective, and replacement parts.
perform a wafer test on memory die; identify the working and nonworking segments in the parts; package the primary and partially defective parts according to working segments; test the parts; give each part an identification code, the identification code containing a quadrant test pattern of the part; select parts for assembly on a module board; assemble the parts on the module board according to the nature and location of the parts' working segments; fill in the solder-dot locations of the primary parts, wherein the solder-dot locations of the back-up parts are left open; test the module on a full function circuit tester, wherein failed bits are noted, and the module is assigned a new identification code designating the failed bits; generate patching instruction charts for the module, wherein the development of the patching instruction charts includes an optimization pass designed to maximize use of smaller patch parts, leaving the larger parts available for patching later-discovered failures; disconnect solder-dot connections on the primary parts to isolate the failed line; fill the solder-dot connections to patch in the substitute lines, the solder-dot connections selected as identified in the patching instruction charts; and re-test the module, including high temperature stress testing of the module. 20. The method of claim 19 wherein the disconnecting and filling steps are automated.
scanning bits of wider parts; identifying unused bits in the smaller parts, wherein the unused bits will be used for substitution; optimizing the selection of the parts to use in patching; generating patching instructions; and implementing the generated patching instructions into a traveler chart. 26. The method of claim 25, wherein at least one computer is used to automate all of the steps.
at least one primary part, the primary part having at least one line failure; a plurality of partially defective parts; a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing any failing primary part I/O lines to be replaced by I/O substitute lines from the backup parts. 28. The module of claim 27, wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the substitute line having the equivalent function as the failing line so that the module is transparent to the user.
at least two primary parts, at least one of the primary parts having at least one line failure; a plurality of partially defective parts; a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing the failing primary part lines to be replaced by I/O substitute lines from the partially defective parts; wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the substitute line having the equivalent function as the failing line so that the module is transparent to the user. 34. The module of claim 33 wherein the selection of substitute lines are identified in patching instruction charts developed for the module, wherein the development of the patching instruction charts includes part optimization.
four primary parts, each of the primary parts having at least one line failure; eight partially defective backup parts; a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing the failing primary part lines to be replaced by I/O substitute lines from the backup parts; wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the replacement line having the equivalent function as the failing line so that the module is transparent to the user. 41. The memory module of claim 40, wherein the memory module is a 2MX32 memory module, the four primary parts consist of 1MX16 packages, and the backup parts consist of eight 1MX4 packages.
at least one primary part, the primary part having at least one line failure; a plurality of partially defective parts; a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing any failing primary part I/O lines to be replaced by I/O substitute lines from the backup parts; wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the replacement line having the equivalent function as the failing line so that the chip-on-board module is transparent to the user. 48. The memory module of claim 47, wherein the four primary parts consist of 1MX16 parts, and the backup parts consist of eight 1MX4 parts.
performing a wafer test on a memory die; selecting, as primary parts, partially defective dies that have a reasonable probability of being patched successfully; selecting, as backup parts, other partially defective dies that test to be suitable for patching; assembling the selected primary and backup parts on the PC module; applying a plastic over coating to the assembled parts; and testing the module using a chip test applied at the module pins; and patching failed segments of the primary parts with working segments of the backup parts. 51. A method for selecting and assembling primary parts and backup parts on a chip-on-board module assembly comprising patterns of solder dot locations for the primary and backup parts,
the process comprising the steps of: performing a wafer test on a memory die; selecting, as primary parts, dies that have a reasonable probability of being patched successfully; selecting, as backup parts, other dies for assembly on a PC module; assembling the selected primary and backup parts on the PC module; applying a plastic over coating to the assembled parts; and test the module using a chip test applied at the module pins; assigning a bar code to the module to identify failed bits; fill in the solder-dot locations of the primary parts, the solder-dot locations of the back-up parts are left open; test the module on a full function circuit tester, wherein failed bits are noted, and the module is assigned a bar-code identifying the failed bits; generate patching instruction charts for the module, wherein the development of the patching instruction charts includes an optimization pass designed to maximize use of smaller patch parts, leaving the larger parts available for patching later-discovered failures; disconnect solder-dot connections on the primary parts to isolate any failed line; fill the solder-dot connections to patch in substitute lines, the solder-dot connections selected as identified in the patching instruction charts; re-test the module, including high temperature stress testing of the module. 52. The method of claim 51 wherein the disconnecting and filling steps are automated.
at least four primary parts, the primary parts having at least one line failure, and the primary parts are laid out horizontally with a card edge; at least four partially defective parts; a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing any failing primary part I/O lines to be replaced by I/O substitute lines from the backup parts; wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the replacement line having the equivalent function as the failing line so that the module is transparent to the user. 54. The memory module of claim 53, wherein the four primary parts consist of 1MX16 parts, and the backup parts consists of 1MX4 memory parts.
primary part memory means for storing data; independent backup part memory means for storing data; connection means for selectively substituting an operational I/O data line of said backup memory means for a failed I/O data line of said primary memory means; said memory module has a target memory capability X, said primary part memory means has a memory capacity X minus the capacity of any defective I/O data lines therein; and said independent backup part memory means has available memory capacity at least equal to the capacity of said defective I/O data lines. 66. A memory module in accordance with claim 65 wherein:
said connection means comprises a pattern of solder dot connections. 67. A memory module in accordance with claim 65 wherein:
said connection means comprises a pattern of jumper wire connections. 68. A memory module in accordance with claim 65 wherein:
said primary part memory means comprise 1MX16 parts; and said backup part memory means comprise 1MX4 parts. 69. A method for constructing a fully functional memory module which utilizes partially defective independent memory circuit parts comprising:
(a) testing and classifying memory parts in a set of defined classifications; (b) selecting a primary memory part having a selected classification; (c) selecting a backup memory part having a selected different classification; (d) constructing a memory module wherein any defective data lines of the selected primary memory part are replaced by operational data lines of the backup circuit structure; and (e) testing constructing step (d) comprises: providing a selected pattern of solder dot connections. 70. A memory module constructed in accordance with any of the claimsmethod of claim 69.
(a) testing and classifying memory parts in a set of defined classifications (b) selecting a primary memory part having a selected classification; (c) selecting a backup memory part having a selected different classification; (d) constructing a memory module wherein: any defective data lines of the selected primary memory part are replaced by operational data lines of the backup circuit structure; (e) testing said so constructed module as to its operational status to approve use of said module or to identify any operating problem in said module; (f) reconstructing said module to remove any identified operating problem; (g) testing said module as to its operational status to approve use as reconstructed or to identify any operating problems; and (j)(h) repeating steps (h) and (i)(f) and (g) as required until the module is approved for service. 72. A method of manufacturing a fully functional transparent memory module including an assembly of selected independent primary and independent backup memory parts, the method comprising the steps of:
testing a plurality of independent memory parts to identify failed I/O data line segments and working I/O data line segments, sorting said tested memory parts into a plurality of categories by patterns of failed and working I/O data line segments, selecting at least one primary part having at least one failed I/O segment, and at least one partially defective backup part from said sorted parts, and combining working I/O data line segments of different selected primary parts and of partially defective backup parts to form a fully functional transparent memory module. 73. The method of manufacturing a fully functional memory module of claim 72 wherein said step of selecting includes utilizing primary parts and backup memory parts from different categories of tested parts and additionally includes the step of optimizing use of a smaller working segment of said backup memory part to leave larger working segments of said backup parts available for subsequent I/O segment failure repair.
74. The method of manufacturing a fully functional transparent memory module of claim 72 additionally including the step of mounting said selected primary parts and said selected backup memory parts on a printed circuit type board having a plurality of conductive strips connectable to respective I/O data line segments of said primary parts and the additional step of positioning said selected primary parts and said selected backup memory parts on said printed circuit board in accordance with the location of each part's working segments relative to said primary parts.
75. The method of manufacturing a fully functional memory module of claim 74 wherein the step of combining working I/O data segments includes selectively interrupting at least one of said conductive strips of said printed circuit board and connecting the interrupted line segment to replace it with a selected working line segment of a backup memory part.
76. The method of manufacturing a functional transparent module of claim 72 wherein the step of combining comprises the steps of disconnecting one or more solder-dot connections for the primary parts to isolated failed I/O line segments and of selectively connecting replacement line segments of said backup part. 77. The method of manufacturing a fully functional memory module of claim 72 wherein the step of combining comprises bit patching to replace a failed I/O line segment of a primary part with an operational segment of said backup part.
78. The method of claim 72 wherein the step of combining comprises the steps of selectively interrupting a failed I/O segment output connection of a primary part and replacing the interrupted I/O segment with a selected working I/O line segment of said backup part.
79. A transparent, fully functional memory module fabricated in accordance with the method of claim 78.
80. The method of claim 72 wherein the step of combining comprises bit steering to replace a failed I/O line segment of a primary part with an operable segment of said backup part.
81. The method of claim 72 wherein the step of combining comprises the steps of electrically interrupting an output of a failed I/O segment of said primary part and replacing the interrupted output segment with an electrical jumper to connect a selected working I/O output segment of said backup part.
82. A fully operational transparent memory module including primary parts and partially defective backup parts wherein said primary parts and said backup parts have been functionally tested and classified into a plurality of groups according to working I/O segments of said primary part and said backup parts, comprising:
at least one primary part, said primary part having at least one failed output segment, at least one partially defective backup part, said backup part having a different group classification than said primary part to facilitate replacement of failed output segments of said primary part, a printed circuit module board having a pattern of conductive lines for forming electrical connections to the I/O output segments of said primary part, and connector for selectively interrupting output segments of said primary part and for replacement thereof with a working line segment of said backup part. 83. The transparent memory module of claim 82 wherein said connector means comprises a solder-dot connector means for selectively replacing failed primary part output segments with a working output segment of said backup part. 84. The transparent memory module of claim 82 wherein said connector means comprises an electrical jumper connection on said printed circuit board.
85. The transparent memory module of claim 82 wherein said connector means comprises an optimized bit patching means for replacing a failed output segment of said primary part with a working output segment of said backup part.
86. The transparent memory module of claim 82 wherein said connector means comprises an optimized bit steering means for replacing a failed output line segment of said primary part with a working output segment of said backup part.
87. The method of claim 1 wherein the combination of working segments comprises bit patching to replace failed I/O data lines with working I/O data lines of said backup memory part.
88. A memory module formed by the method described in claim 87.
89. The method of claim 1 wherein the combination of working segments comprises bit steering means to replace failed I/O data lines of said primary part with working I/O data lines of said backup memory part.
90. The method of claim 12 wherein the step of substituting comprises bit patching to replace failed I/O data line segments of said primary parts with selected operable I/O data line segments of said backup memory parts.
91. A memory module formed by the method described in claim 90.
92. The method of claim 12 wherein the step of substituting comprises bit steering to replace failed I/O data line segments of said primary parts with selected operable I/O data line segments of said backup memory parts.
93. A method for patching primary memory parts of a memory module with segments of partially defective backup memory parts to produce a fully operational transparent memory module, said method comprising the steps of:
performing a wafer test on a plurality of independent memory die, identifying the respective working and non-working segments in each of said memory die, packaging said plurality of memory die into primary and backup memory parts according to working and non-working segments, selecting packaged parts for assembly on a printed circuit type board, assembling the selected parts on said printed circuit board in accordance with test data identifying working segments of said parts, selectively connecting output segments of the primary memory parts to said printed circuit board connectors, subjecting the assembled primary parts to a full function circuit test to determine any failed output bits, generating patching instructions to optimize repair of any failed output bits of said primary parts, disconnecting any failed output bits of said primary parts in accordance with said test results, and substituting working segments of said backup parts for failed bits of said primary parts in accordance with said patching instructions. 94. The method of claim 93 wherein the step of substituting comprises bit patching to replace failed output bits of said primary parts with working segments of said backup parts.
95. A transparent, fully functional memory module fabricated in accordance with the method of claim 94.
96. The method of claim 93 wherein the step of substituting comprises bit steering to replace failed output bits of said primary parts with working output bit segments of said backup parts.
97. A SIMM memory module made up of primary parts and partially defective backup parts, comprising:
at least two primary parts with at least one of the primary parts having at least one line failure, a plurality of partially defective independent backup parts, a printed circuit module board having conductive strips on at least one surface of said board, and connector means on said board for selectively disconnecting failed primary part lines to facilitate replacement thereof by substitute lines of said partially defective backup parts having an equivalent function as the failed line whereby the repaired memory module is fully functional and transparent to a user. 98. The SIMM memory module of claim 97 wherein the connector means comprises an optimal bit patching means for replacing a failed primary part line with a substitute line from said backup part having the equivalent function as the failed line whereby the repaired memory module is fully functional and transparent to a user.
99. The SIMM memory module of claim 97 wherein the connector means comprises an optimal bit steering means for replacing a failed primary part line with a substitute line from said backup part having the equivalent function as the failed line whereby the repaired memory module is fully functional and transparent to a user.
100. A chip-on-board memory module made up of a plurality of primary die parts and a plurality of partially defective backup die parts, comprising: a printed circuit board having a plurality of conductors arranged on at least one surface for supporting said primary die parts and said backup die parts, at least one primary die part mounted on said printed circuit board and connected to selected ones of said conductors and said primary die part having at least one failed line, a plurality of partially defective backup die parts mounted on said printed circuit board in accordance with predetermined working and non-working line segments data, means for identifying the respective working and non-working lines of said primary and backup die parts, and connector means for selectively optimizing replacement of a non-working line of said primary part with a working line of said backup part having the equivalent function as said failed line so that the repaired memory module is fully functional and transparent to a user. 101. The memory module of claim 100 wherein said connector means comprises an optimal bit patching means for replacing said failed non-working line of said primary part with a working line of one of said backup parts having an equivalent function as said failed line so the repaired memory module is fully functional and transparent to a user. 102. The memory module of claim 100 wherein said connector means comprises an optimal bit steering means for replacing said failed non-working line of said primary part with a working line of one of said backup parts having the equivalent function as said failed line so the repaired memory module is fully functional and transparent to a user. 103. A semiconductor memory module fabricated to facilitate repair of defective components, the memory module comprising:
a printed circuit-type board having a plurality of conductive pathways on at least one surface thereof and individual pathways being connected to I/O lines of said board, at least one primary memory die part mounted on said printed circuit board having individual leads thereof connected to individual ones of said conductive pathways, a plurality of independent partially defective backup memory die parts being mounted on said printed circuit board in positions determined in accordance with pre-assembly die test data to optimize backup capabilities of said backup memory die parts, and bit patching means for selectively rerouting ones of said conductive pathways to selectively replace a non-working I/O line of said primary memory die part with a working I/O line of one of said backup memory die parts having an equivalent function as said failed I/O line to form a fully functional memory module. 104. The semiconductor memory module of claim 103 wherein said bit patching means comprises connector means for increasing the electrical resistance of failed I/O lines to be replaced with working I/O lines of said backup die parts.
105. The memory module of claim 104 wherein said bit steering means comprises connector means for selectively electrically interrupting failed I/O lines of said primary die part and for selectively connecting as replacement therefore a working I/O line of one of said backup die parts.
106. The memory module of claim 103 wherein said backup memory die parts each have different group classifications determined by pre-assembly test data to facilitate replacement of failed I/O lines of said primary die part. 107. A semiconductor memory module fabricated to facilitate repair of defective components, the memory module comprising:
a printed circuit-type board having a plurality of conductive pathways on at least one surface thereof and the individual pathways being connected to I/O lines of said board, at least one primary memory die part mounted on said printed circuit board with predetermined leads electrically connected to pre-selected ones of said conductive pathways, a plurality of independent partially defective backup memory die parts positioned on said printed circuit board in accordance with pre-assembly die test data to optimize backup capabilities of said mounted backup die parts, and bit steering means for selectively combining working I/O lines of ones of said backup memory die parts and for electrically connecting said selected working I/O lines to replace non-working I/O lines of said primary die part to form thereby a fully functional memory module. 108. The semiconductor memory module of claim 107 wherein said bit steering means comprises connector means for increasing the electrical resistance of failed I/O lines to be replaced with working I/O lines of said backup die parts.
109. The memory module of claim 108 wherein said bit steering means comprises connector means for selectively electrically interrupting failed I/O lines of said primary die part and for selectively connecting as replacement a working I/O line of said backup memory die part.
RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 60/023,255 filed Aug. 12, 1996, and U.S. Provisional Application No. 60/049,667 filed Jun. 16, 1997.
FIELD OF THE INVENTION This invention relates to electronic memory modules, and more specifically to the manufacture of memory modules that selectively use operating segments of a plurality of less-than-perfect chips or packages exclusively, or in combination with perfect ones.
BACKGROUND OF THE INVENTION An Integrated Circuit (IC) comprises millions of individual transistor or logical circuits, e.g., memory cells.
IC manufacturers use various types of self-correcting techniques in order to improve the quality of their chips. For example, a series of redundant or spare cells are built into a die. At the wafer level, the die is tested. The defective cells are isolated and some of the spare cells are wired in their place such as by blowing fuse sections prebuilt on the chip. In spite of these highly effective correction techniques, defects are still detected in chips before and after they are encapsulated into packages or assembled on COB modules. The packaging and assembly processes sometimes cause some chips failure. The high cost of high-density chips make the use of less-than-perfect ones an economic necessity. Yet, the prior art does not offer a systematic and efficient approach to the combination of less-than-perfect chips or packages with or without �perfect� ones in order to create economically advantageous memory modules. The instant invention results from a search for quick, versatile and economical processes to assemble memory modules out of less-than-perfect chips.
SUMMARY OF THE INVENTION The principal and secondary objects of this invention are to selectively utilize operating segments of partially defective memory chips and packages by identifying the working segments in a series of chips before they are encapsulated or a series of packages before or after they are assembled on a memory module and combining their working segments in the most effective manner in a cohesive memory assembly. This invention allows utilization of a maximum number of chips in cost-effective applications transparent to the user.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A-1G are a circuit diagram of a SIMM manufactured according to the invention;
DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION Memories are organized by design into a series of usable configurations. A memory containing sixteen million bits of information storage is usually organized in small blocks of physical locations which have a common address. In the patching method disclosed herein, this organization is called a quadrant. Physical layout and connection define a block for addressing simplicity and minimum layout. On most large memories the quadrant usually comprises either 64 or 128K of bits, where K stands for the power-of-two which most closely corresponds to the actual size of the quadrant. Each memory location has a specific power of two address defined during the layout and accessed by address lines during the standard memory addressing sequence. Half the address is selected with the Row Address Select (RAS) signal, and the second half is selected with the Column Address Select (CAS) signal. Since memory circuit flaws tend to be very random and of small size, only a single area of a quadrant is usually affected, leaving the remainder of the memory circuit fully functional. Chips or packages which are partially functional can be combined on a single PC board to create a complete memory module. There are two basic approaches to the combination of parts to build a particular memory module, patching and bit-steering. For the purposes of these illustrations we will focus on the popular SIMM/DIMM application. Any combination of memory circuits that requires multiple outputs in a controlled layout from a module containing memory devices of any kind can be created using the described techniques.
Typically the sorted dice are broken into those that demonstrate specific types, numbers and concentrations of working quadrants. For instances a type is selected such that when the dice are packaged the memory part will function as one that is � good i.e., which has three quarters of its I/O lines functioning. In the case of a die with 4 output, three of the 4 I/O lines will be fully functional.
Parts with more random defects are grouped into �mostly good� memory devices based on the number of quadrants that are working, and �less good� memory devices where only a few quadrants are working. Parts that are not functional because of severe damage are discarded.
The deeper configuration chips are analyzed for the maximum working widths and the categorized as either a �wide lesser part� or a �deeper less I/O part�. The decision criteria may vary depending upon the requirement of the final application. For instance, in the case of the 4 Meg part that has an ability to be either a fully functioning 256 k by 4 or a 1 meg by 1, the determination will depend upon the availability of patch parts for the bigger 256�16 applications. A table is used to reach the packaging scheme that is the most appropriate taking into account the various parameters.
While, in the above-description of the pretesting and grouping processes, the terms �die�, �dice�, and �parts� have been used, it should be understood that the processes are similarly applicable to dice (e.g., in COB modules) as well as packages in which one or more dice have been encapsulated.
If at any time during the process a failure 23 in any primary part of the module is detected, it is isolated to a bit location and the above-process is used to correct the defect. If failure occurs 24 in a patching part, that part is removed 25 from the board and bar-coded as a next lower level part for future use. For example, an originally all good part would be degraded to a � before being reused. The patch part is replaced and the test process restarted 22. If the failure occurs in a large part, a replacement bit is chosen from the same tables using the same logic, if possible. This results either in a new 1�1 being added, or an existing patch part being removed and a higher grade patch part being substituted for it. The effect of failure in a secondary test is handled the same as one occurring in the initial test. Modules that pass 25 the test are readied for shipment.
For those parts which have had four or more bits fail or which have conflicting outputs not patchable with another patch chip, the 1M�16 primary part is preferably mounted on a board such as that disclosed above and shown in FIG. 4. Therefore, the more extensive routing algorithm of the COB board in FIG. 4 can be used to patch the part on the board.
This board allows for unburned-in-parts which have tested �all good� at the die level to be directly mounted and processed through the burn-in and test process, assuming that in most cases the parts will either pass resulting in a 4 chip solution or require on average only one patch chip. Parts that can not be patched are removed and used on other more comprehensive boards.
Table III shows the various patching arrangements for each failed bit of the primary parts U1, U2, U4 and U5. For each bit that has failed in one of the primary parts and that is flagged in the PIN column, the chart shows the appropriate primary part connection in the �u con� column, which solder dot must be disconnected to isolate the failing bit in the �1�16 dot� column, which solder-dot must be filled to patch in the substitute bits in the �patch Dot� column and finally which solder-dot location must be filled to enable a patch
Patch Dot
CAS Dot
RAS Dot
1 U1 0
2 U1 1
4 U1 2
8 U1 3
1 U1 4
2 U1 5
4 U1 6
8 U1 7
4 U2 2
8 U2 3
1 U2 4
2 U2 5
4 U2 6
8 U2 7
1 U1 8
2 U1 9
4 U1 10
8 U1 11
1 U1 12
2 U1 13
4 U1 14
8 U1 15
1 U2 8
2 U2 9
4 U2 10
8 U2 11
1 U2 12
2 U2 13
4 U2 14
8 U2 15
1 U4 0
2 U4 1
4 U4 2
8 U4 3
1 U4 4
2 U4 5
4 U4 6
8 U4 7
1 U5 0
2 U5 1
4 U5 2
8 U5 3
1 U5 4
2 U5 5
4 U5 6
8 U5 7
1 U4 8
2 U4 9
4 U4 10
8 U4 11
1 U4 12
2 U4 13
4 U4 14
8 U4 15
1 U5 8
2 U5 9
4 U5 10
8 U5 11
1 U5 12
2 U5 13
4 U5 14
8 U5 15
TABLE IV 1 � 16 patch patch patch patch pin u con dot Dot Cas dot bit ras dot cas dot bit ras dot F0 1 U1 0 19 21 11 8A 147 22 15 9A 151 F1 2 U1 1 23 25 11 8D 147 26 15 9B 151 F2 4 U1 2 27 29 11 8B 147 30 15 9C 151 F3 8 U1 3 31 33 11 8C 147 34 15 9D 151 F4 1 U1 4 35 37 11 8A 147 38 15 9A 151 F5 2 U1 5 39 41 11 8D 147 42 15 9B 151 F6 4 U1 6 43 45 11 8B 147 46 15 9C 151 F7 8 U1 7 47 49 11 8C 147 50 15 9D 151 F8 1 U2 0 51 53 13 7A 149 54 17 10A 153 F9 2 U2 1 55 57 13 7B 149 58 17 10B 153 F10 4 U2 2 59 61 13 7C 149 62 17 10C 153 F11 8 U2 3 63 65 13 7D 149 66 17 10D 153 F12 1 U2 4 67 69 13 7A 149 70 17 10A 153 F13 2 U2 5 71 73 13 7B 149 74 17 10B 153 F14 4 U2 6 75 77 13 7C 149 78 17 10C 153 F15 8 U2 7 79 81 13 7D 149 82 17 10D 153 F16 1 U1 8 83 85 12 8A 147 86 16 9A 151 F17 2 U1 9 87 89 12 8D 147 90 16 9B 151 F18 4 U1 10 91 93 12 8B 147 94 16 9C 151 F19 8 U1 11 95 97 12 8C 147 98 16 9D 151 F20 1 U1 12 99 101 12 8A 147 102 16 9A 151 F21 2 U1 13 103 105 12 8D 147 106 16 9B 151 F22 4 U1 14 107 109 12 8B 147 110 16 9C 151 F23 8 U1 15 111 113 12 8C 147 114 16 9D 151 F24 1 U2 8 115 117 14 7A 149 118 18 10A 153 F25 2 U2 9 119 121 14 7B 149 122 18 10B 153 F26 4 U2 10 123 125 14 7C 149 126 18 10C 153 F27 8 U2 11 127 129 14 7D 149 130 18 10D 153 F28 1 U2 12 131 133 14 7A 149 134 18 10A 153 F29 2 U2 13 135 137 14 7B 149 138 18 10B 153 F30 4 U2 14 139 141 14 7C 149 142 18 10C 153 F31 8 U2 15 143 145 14 7D 149 146 18 10D 153 B0 1 U4 0 20 22 15 9A 152 21 11 8A 148 B1 2 U4 1 24 26 15 9B 152 25 11 8D 148 B2 4 U4 2 28 30 15 9C 152 29 11 8B 148 B3 8 U4 3 32 34 15 9D 152 33 11 8C 148 B4 1 U4 4 36 38 15 9A 152 37 11 8A 148 B5 2 U4 5 40 42 15 9B 152 41 11 8D 148 B6 4 U4 6 44 46 15 9C 152 45 11 8B 148 B7 8 U4 7 48 50 15 9D 152 49 11 8C 148 B8 1 U5 0 52 54 17 10A 154 53 13 7A 150 B9 2 U5 1 56 58 17 10B 154 57 13 7B 150 B10 4 U5 2 60 62 17 10C 154 61 13 7C 150 B11 8 U5 3 64 66 17 10D 154 65 13 7D 150 B12 1 U5 4 68 70 17 10A 154 69 13 7A 150 B13 2 U5 5 72 74 17 10B 154 73 13 7B 150 B14 4 U5 6 76 78 17 10C 154 77 13 7C 150 B15 8 U5 7 80 82 17 10D 154 81 13 7D 150 B16 1 U4 8 84 86 16 9A 152 85 12 8A 148 B17 2 U4 9 88 90 16 9B 152 89 12 8D 148 B18 4 U4 10 92 94 16 9C 152 93 12 8B 148 B19 8 U4 11 96 98 16 9D 152 97 12 8C 148 B20 1 U4 12 100 102 16 9A 152 101 12 8A 148 B21 2 U4 13 104 106 16 9B 152 105 12 8D 148 B22 4 U4 14 108 110 16 9C 152 109 12 8B 148 B23 8 U4 15 112 114 16 9D 152 113 12 8C 148 B24 1 U5 8 116 118 18 10A 154 117 14 7A 150 B25 2 U5 9 120 122 18 10B 154 121 14 7B 150 B26 4 U5 10 124 126 18 10C 154 125 14 7C 150 B27 8 U5 11 128 130 18 10D 154 129 14 7D 148 B28 1 U5 12 132 134 18 10A 154 133 14 7A 150 B29 2 U5 13 136 138 18 10B 154 137 14 7B 150 B30 4 U5 14 140 142 18 10C 154 141 14 7C 150 B31 8 U5 15 144 146 18 10D 154 145 14 7D 150 part in the �patch bit column� with the appropriate CAS line in the �CAS dot� column. When all the dots are finished, the patch parts are chosen by the outputs required. For example, if bit 3 of U1 failed, solder-dot 31 must be disconnected to isolate the failed bit. Solder-dot 33 must then be filled to patch in the substitute bits in the �patch Dot.� Cas line 11 is then dotted and patch bit 8C is selected to be filled.
Alternatively, the board, shown in FIG. 5, can be slightly revised to have dottable RAS connections, thus, enhancing flexibility by allowing two patch parts to patch a single primary part if the other side of the board is �all good.� This revised embodiment is shown in FIGS. 7a, 7b and 7c. the diagrams for the primary parts and patch parts are shown in FIGS. 7a and 7b. The primary difference between the embodiments shown in FIGS. 5 and 7 are the dottable RAS connections, shown on the right hand side of FIG. 7b. Referring to Table IV, which is prepared for the memory module of FIG. 7, assuming the same failure scenario described about with respect to FIG. 5 (i.e., bits 3 and 7 fail), once the process determines that patch bit 8C has already been selected to solve the bit 3 failure, solder-dot 49, which had previously been dotted, must now be undotted, and as a replacement, solder-dot 50 is dotted. The corresponding CAS line 15 is dotted, and subsequently, solder dot 9D is filled, and RAS line 151 is dotted, thereby connecting RAS0 to patch part U9. Thus, flexibility is improved in the embodiment of FIG. 7 due to the allowance of two patch parts to patch a single part.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3714637 *Sep 30, 1970Jan 30, 1973IbmMonolithic memory utilizing defective storage cellsUS3753235 *Aug 18, 1971Aug 14, 1973IbmMonolithic memory module redundancy scheme using prewired substratesUS3781826 *Nov 15, 1971Dec 25, 1973IbmMonolithic memory utilizing defective storage cellsUS3984860 *Dec 13, 1974Oct 5, 1976International Business Machines CorporationMulti-function LSI wafersUS4333152 *Jun 13, 1980Jun 1, 1982Best Robert MTV Movies that talk backUS4445187 *May 13, 1982Apr 24, 1984Best Robert MVideo games with voice dialogUS4569026 *Oct 31, 1984Feb 4, 1986Best Robert MTV Movies that talk backUS4992984 *Dec 28, 1989Feb 12, 1991International Business Machines CorporationMemory module utilizing partially defective memory chipsUS5006987 *Mar 25, 1986Apr 9, 1991Harless William GAudiovisual system for simulation of an interaction between persons through output of stored dramatic scenes in response to user vocal inputUS5208178 *Jul 31, 1991May 4, 1993Hitachi, Ltd.Testing macrocells before connecting wiresUS5240866 *Feb 3, 1992Aug 31, 1993At&T Bell LaboratoriesMethod for characterizing failed circuits on semiconductor wafersUS5347306 *Dec 17, 1993Sep 13, 1994Mitsubishi Electric Research Laboratories, Inc.Animated electronic meeting placeUS5444366 *Feb 4, 1994Aug 22, 1995Texas Instruments IncorporatedWafer burn-in and test systemUS5448488 *Feb 25, 1994Sep 5, 1995Sony CorporationComputer-controlled individual chip management system for processing wafersUS5461714 *Jul 8, 1994Oct 24, 1995Kabushiki Kaisha ToshibaApparatus for synthesizing an object described in an object-oriented language on the basis of a predetermined specificationUS5490232 *Apr 5, 1994Feb 6, 1996Daiwa House Industry Co., Ltd.Computer-aided thought process simulation design systemUS5598341 *Mar 10, 1995Jan 28, 1997Advanced Micro Devices, Inc.Real-time in-line defect disposition and yield forecasting systemUS5615387 *Jan 22, 1996Mar 25, 1997International Business Machines CorporationMethod and apparatus for reworking printed circuit boards using surface coating and selective removal of an electrically conductive materialUS5657281 *Mar 11, 1996Aug 12, 1997Cirrus Logic, Inc.Systems and methods for implementing inter-device cell replacementsUS5691907 *Apr 18, 1995Nov 25, 1997Xilinx Inc.Device for programming multiple arrays of semiconductor devicesUS5832595 *Jun 14, 1994Nov 10, 1998Hitachi, Ltd.Method of modifying conductive lines of an electronic circuit board and its apparatusUS5835378 *Nov 20, 1995Nov 10, 1998Lsi Logic CorporationComputer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chipUS5887343 *May 16, 1997Mar 30, 1999Harris CorporationDirect chip attachment method* Cited by examinerNon-Patent CitationsReference1 *A Robot Organizing Purposive Behavior By Itself Abstract, Author: Ikeda et al., Published Jun. 30, 1992.2 *F.J. Aichelmann, Jr., "Multiplexed Partial-Good Chip Scheme . . . ", IBM Technical Discosure Bulletin, vol. 22, No. 1, pp. 138-139, Jun. 1979.3 *L.J. Bosch and C.F. Hardiman, "Dynamic Selection of Partial Good Array Chips by Bit Address Selection," IBM Technical Disclosure Bulletin, vol. 25, No. 3B, pp. 1485-1487, Aug. 1982.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8515837 *Mar 14, 2008Aug 20, 2013Denso CorporationMethod of boxing fuel injectorsUS20080235117 *Mar 14, 2008Sep 25, 2008Tetsuji KudohMethod of boxing fuel injectorsUS20130100752 *Oct 20, 2011Apr 25, 2013Fluiditech Ip LimitedMethod of restoring reconstructed memory spaces* Cited by examinerClassifications U.S. Classification700/121, 365/230.03, 365/200, 365/225.7, 700/117, 700/97, 29/832, 29/840, 700/110International ClassificationG11C29/44, G06F19/00Cooperative ClassificationG11C29/44European ClassificationG11C29/44Legal EventsDateCodeEventDescriptionDec 9, 2013ASAssignmentFree format text: SECURITY AGREEMENT;ASSIGNOR:JABIL CIRCUIT, INC.;REEL/FRAME:031785/0829Owner name: CELETRONIX USA, INC, CALIFORNIAEffective date: 20060913Aug 4, 2005ASAssignmentOwner name: JABIL CIRCUIT, INC., FLORIDAFree format text: PATENT COLLATERAL ASSIGNMENT AND SECURITY INTEREST;ASSIGNOR:CELETRONIX USA, INC.;REEL/FRAME:016345/0981Effective date: 20050321Owner name: JABIL CIRCUIT, INC., FLORIDAFree format text: PATENT COLLATERAL ASSIGNMENT AND SECURITY INTEREST;ASSIGNOR:CELETRONIX INTERNATIONAL, LTD.;REEL/FRAME:016354/0022Jan 29, 2003ASAssignmentOwner name: CELETRON USA, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TANDON ASSOCIATES, INC.;REEL/FRAME:013706/0824Effective date: 20010501RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google