Source: http://www.google.com/patents/US7692263?dq=6,232,546
Timestamp: 2015-07-04 16:05:56
Document Index: 228565393

Matched Legal Cases: ['Application No. 02769655', 'Application No. 06851411', 'Application No. 02', 'Application No. 01', 'Application No. 2', 'Application No. 07253716', 'Application No. 08250197', 'Application No. 10', 'Application No. 2003', 'Application No. 02769655', 'Application No. 08250197', 'Application No. 2002', 'Application No. 10', 'Application No. 02818502']

Patent US7692263 - High voltage GaN transistors - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer...http://www.google.com/patents/US7692263?utm_source=gb-gplus-sharePatent US7692263 - High voltage GaN transistorsAdvanced Patent SearchPublication numberUS7692263 B2Publication typeGrantApplication numberUS 11/603,427Publication dateApr 6, 2010Filing dateNov 21, 2006Priority dateNov 21, 2006Fee statusPaidAlso published asEP1965433A2, EP1965433A3, EP2485262A1, US7893500, US8169005, US20080116492, US20100109051, US20110114997, US20120223366Publication number11603427, 603427, US 7692263 B2, US 7692263B2, US-B2-7692263, US7692263 B2, US7692263B2InventorsYifeng Wu, Primit Parikh, Umesh MishraOriginal AssigneeCree, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (49), Non-Patent Citations (58), Referenced by (24), Classifications (13), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetHigh voltage GaN transistors
US 7692263 B2Abstract
a gate, in electrical contact with said active region, between said source and said drain;
a first insulating spacer layer disposed over said active region between said source and said gate;
a second insulating spacer layer disposed over said active region between said drain and said gate;
a first conducting field plate, disposed on said first spacer layer between said source and said gate, electrically connected to said gate and extending toward said source;
a second conducting field plate, disposed on said second spacer layer between said drain and said gate, electrically connected to said gate and extending toward said drain;
a third insulating spacer layer, disposed on said first spacer layer, said second spacer layer, said first field plate, said gate, and said second field plate, between said source and said drain; and
a third conducting field plate, disposed on said third spacer layer over said gate, said second field plate, and said second spacer layer, electrically connected to said source and extending toward said drain, wherein said transistor has an Lg length ranging from approximately 1.2 microns to approximately 1.5 microns, an Lgd length ranging from approximately 13.3 microns to approximately 18 microns, a Lds length ranging from approximately 16 microns to 21.5 microns, an Lfd1 length ranging from approximately 1.5 microns to 1.8 microns, and an Lfd2 length of approximately 4.5 microns.
2. The transistor of claim 1, wherein said transistor has an Lg length of approximately 1.2 microns, an Lgd length of approximately 13.3 microns, an Lds length of approximately 16 microns, an Lfd1 length of approximately 1.8 microns, and an Lfd2 length of approximately 4.5 microns and the transistor is configured to exhibit a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2.
3. The transistor of claim 1, wherein said transistor has an Lg length of approximately 1.2 microns, an Lgd length of approximately 13.3 microns, an Lds length of approximately 16 microns, an Lfd1 length of approximately 1.8 microns, and an Lfd2 length of approximately 4.5 microns and the transistor is configured to exhibit a blocking voltage of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2.
4. The transistor of claim 1, wherein said transistor has an Lg length of approximately 1.5 microns, an Lgd length of approximately 18 microns, an Lds length of approximately 21.5 microns, an Lfd1 length of approximately 1.5 microns, and an Lfd2 length of approximately 4.5 microns and the transistor is configured to exhibit a blocking voltage of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2.
5. The transistor of claim 1, wherein said transistor has an Lg length of approximately 1.5 microns, an Lgd length of approximately 18 microns, an Lds length of approximately 21.5 microns, an Lfd1 length of approximately 1.5 microns, and an Lfd2 length of approximately 4.5 microns and the transistor is configured to exhibit a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.
6. The transistor of claim 1, wherein said first spacer layer and said second spacer layer comprise portions of a single layer disposed on the surface of said active region.
7. The transistor of claim 1, wherein said transistor comprises a high electron mobility transistor.
8. The transistor of claim 7, wherein said transistor further comprises:
a buffer layer disposed on said substrate; and
a barrier layer disposed on said buffer layer,
the active region being defined by a two dimensional electron gas induced at the heterointerface between the buffer layer and the barrier layer.
9. The transistor of claim 8, wherein said substrate comprises a semi-insulating SiC substrate.
10. The transistor of claim 8, wherein said buffer layer comprises a GaN buffer layer.
11. The transistor of claim 8, wherein said barrier layer comprises an AlGaN barrier layer.
12. The transistor of claim 8, wherein said barrier layer comprises an AlN layer and an AlGaN layer.
13. The transistor of claim 8, wherein said first spacer layer comprises a first SiN spacer layer, said second spacer layer comprises a second SiN spacer layer, and said third spacer layer comprises a third SiN spacer layer.
14. The transistor of claim 8, wherein said first field plate comprises a first metal field plate, said second field plate comprises a second metal field plate, and said third field plate comprises a third metal field plate.
15. A multiple field plate high electron mobility transistor, comprising:
a buffer layer disposed on said substrate;
a barrier layer disposed on said buffer layer;
the heterointerface between the buffer layer and the barrier layer inducing a two dimensional electron gas to define an active region;
a source electrode on said barrier layer and in electrical contact with said active region;
a drain electrode on said barrier layer and in electrical contact with said active region;
a gate, on said barrier layer and in electrical contact with said active region, between said source and said drain;
a first insulating spacer layer disposed on said barrier layer between said source and said gate;
a second insulating spacer layer disposed on said barrier layer between said drain and said gate;
a third conducting field plate, disposed on said third spacer layer over said gate, said second field plate, and said second spacer layer, electrically connected to said source and extending toward said drain, wherein said transistor has length ranging from approximately 1.2 microns to approximately 1.5 microns, an Lgd length ranging from approximately 13.3 microns to approximately 18 microns, an Lds length ranging from approximately 16 microns to 21.5 microns, an Lfd1 length ranging from approximately 1.5 microns to 1.8 microns, and an Lfd2 length of approximately 4.5 microns.
16. The transistor of claim 15, wherein said transistor has an Lg length of approximately 1.2 microns, an Lgd length of approximately 13.3 microns, an Lds length of approximately 16 microns, an Lfd1 length of approximately 1.3 microns, and an Lfd2 length of approximately 4.5 microns and wherein said transistor is configured to exhibit a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2.
17. The transistor of claim 15, wherein said transistor has an Lg length of approximately 1.2 microns, an Lgd length of approximately 13.3 microns, an Lds length of approximately 16 microns, an Lfd1 length of approximately 1.8 microns, and an Lfd2 length of approximately 4.5 microns and wherein said transistor is configured to exhibit a blocking voltage of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2.
18. The transistor of claim 15, wherein said transistor has an Lg length of approximately 1.5 microns, an Lgd length of approximately 18 microns, an Lds length of approximately 21.5 microns, an Lfd1 length of approximately 1.5 microns, and an Lfd2 length of approximately 4.5 microns and wherein said transistor is configured to exhibit a blocking voltage of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2.
19. The transistor of claim 15, wherein said transistor has an Lg length of approximately 1.5 microns, an Lgd length of approximately 18 microns, an Lds length of approximately 21.5 microns, an Lfd1 length of approximately 1.5 microns, and an Lfd2 length of approximately 4.5 microns and wherein said transistor is configured to exhibit a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.
The singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises” and/or “comprising,” when used in this specification, identify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The term “approximately” used to describe measurements of length in this disclosure refers to dimensions falling within plus or minus 0.2 microns of the length specified.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4551905Nov 9, 1983Nov 12, 1985Cornell Research Foundation, Inc.Fabrication of metal lines for semiconductor devicesUS4947232Nov 28, 1988Aug 7, 1990Sharp Kabushiki KaishaHigh voltage MOS transistorUS5192987May 17, 1991Mar 9, 1993Apa Optics, Inc.High electron mobility transistor with GaN/Alx Ga1-x N heterojunctionsUS5196359Jun 5, 1991Mar 23, 1993Texas Instruments IncorporatedMethod of forming heterostructure field effect transistorUS5296395Mar 3, 1993Mar 22, 1994Apa Optics, Inc.Method of making a high electron mobility transistorUS5399886Jan 26, 1994Mar 21, 1995Fujitsu LimitedHeterojunction FET with a high potential barrier layer and gate structureUS5885860Jun 16, 1997Mar 23, 1999Motorola, Inc.Silicon carbide transistor and methodUS6033948Oct 26, 1998Mar 7, 2000Lg Semicon Co., Ltd.Method of making high voltage metal oxide silicon field effect transistorUS6046464Aug 13, 1997Apr 4, 2000North Carolina State UniversityIntegrated heterostructures of group III-V nitride semiconductor materials including epitaxial ohmic contact comprising multiple quantum wellUS6071780Apr 5, 1999Jun 6, 2000Fujitsu LimitedCompound semiconductor apparatus and method for manufacturing the apparatusUS6100571Jun 7, 1999Aug 8, 2000Nec CorporationFet having non-overlapping field control electrode between gate and drainUS6307232Nov 25, 1997Oct 23, 2001Mitsubishi Denki Kabushiki KaishaSemiconductor device having lateral high breakdown voltage elementUS6316793Jun 12, 1998Nov 13, 2001Cree, Inc.Nitride based transistors on semi-insulating silicon carbide substratesUS6316820Aug 28, 1998Nov 13, 2001Hughes Electronics CorporationPassivation layer and process for semiconductor devicesUS6346451Jun 30, 1999Feb 12, 2002Philips Electronics North America CorporationLaterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrodeUS6445038Dec 7, 1998Sep 3, 2002Infineon Technologies AgSilicon on insulator high-voltage switchUS6468878Feb 27, 2001Oct 22, 2002Koninklijke Philips Electronics N.V.SOI LDMOS structure with improved switching characteristicsUS6483135Aug 26, 1999Nov 19, 2002Nec Compound Semiconductor Devices, Ltd.Field effect transistorUS6559513Apr 22, 2002May 6, 2003M/A-Com, Inc.Field-plate MESFETUS6586781Jan 29, 2001Jul 1, 2003Cree Lighting CompanyGroup III nitride based FETs and HEMTs with reduced trapping and method for producing the sameUS20010015446Dec 8, 2000Aug 23, 2001Kaoru InoueSemiconductor deviceUS20010023964Jan 29, 2001Sep 27, 2001Yifeng WuGroup III nitride based FETs and hemts with reduced trapping and method for producing the sameUS20020005528Jul 17, 2001Jan 17, 2002Fujitsu Quantum Devices LimitedHigh-speed compound semiconductor device operable at large output power with minimum leakage currentUS20020017648Jun 27, 2001Feb 14, 2002Kensuke KasaharaSemiconductor deviceUS20020137318Mar 15, 2002Sep 26, 2002Koninklijke Philips Electronics N.V.Field effect transistor structure and method of manufactureUS20020155646Feb 27, 2001Oct 24, 2002John PetruzzelloSoi ldmos structure with improved switching characteristicsUS20030006437Sep 9, 2002Jan 9, 2003Nec CorporationField effect transistorUS20030085409Nov 2, 2001May 8, 2003Yu-Chen ShenIndium gallium nitride separate confinement heterostructure light emitting devicesUS20030107081May 22, 2002Jun 12, 2003Lee Dae WooExtended drain metal oxide semiconductor field effect transistor with a source field plate and a method for fabricating the sameUS20030183844Feb 10, 2003Oct 2, 2003Fujitsu Quantum Devices LimitedSemiconductor device and method of fabricating the sameUS20030222327Mar 17, 2003Dec 4, 2003Kabushiki Kaisha ToshibaSemiconductor device and method of manufacturing semiconductor deviceUS20040207313Apr 21, 2004Oct 21, 2004Sharp Kabushiki KaishaLED device and portable telephone, digital camera and LCD apparatus using the sameUS20050051796Aug 31, 2004Mar 10, 2005Cree, Inc.Wide bandgap transistor devices with field platesUS20050062069Mar 23, 2004Mar 24, 2005Wataru SaitoPower semiconductor deviceUS20050173728Feb 5, 2004Aug 11, 2005Saxler Adam W.Nitride heterojunction transistors having charge-transfer induced energy barriers and methods of fabricating the sameUS20060019435 *Jul 23, 2004Jan 26, 2006Scott SheppardMethods of fabricating nitride-based transistors with a cap layer and a recessed gateUS20060202272 *Mar 11, 2005Sep 14, 2006Cree, Inc.Wide bandgap transistors with gate-source field platesUS20070090383Nov 30, 2006Apr 26, 2007Toyoda Gosei Co., Ltd.Light emitting deviceUS20080036364May 23, 2007Feb 14, 2008Intematix CorporationTwo-phase yellow phosphor with self-adjusting emission wavelengthEP0069429A2Jul 2, 1982Jan 12, 1983Philips Electronics N.V.Insulated gate field effect transistorEP0792028A2Feb 6, 1997Aug 27, 1997Oki Electric Industry Co., Ltd.Solid-state antenna switch and field-effect transistorEP0936682A1Jul 29, 1997Aug 18, 1999Nichia Chemical Industries, Ltd.Light emitting device and display deviceEP1336989A2Jan 23, 2003Aug 20, 2003Infineon Technologies AGTransistor deviceEP1577951A2Mar 11, 2005Sep 21, 2005Kabushiki Kaisha ToshibaA semiconductor device and method of its manufactureJPH0521793A Title not availableWO1998056043A1May 22, 1998Dec 10, 1998Daimler Benz AgSemiconductor component and method for producing the sameWO2003038905A2Oct 22, 2002May 8, 2003Koninkl Philips Electronics NvLateral soi field-effect transistorWO2004068590A1Jan 29, 2003Aug 12, 2004Hiromichi OhashiPower semiconductor deviceWO2005114743A2Apr 14, 2005Dec 1, 2005Cree IncWide bandgap transistors with multiple field plates* Cited by examinerNon-Patent CitationsReference1"Enhancement of Base Conductivity Via the Piezoelectric Effect in AlGaN/GaN HBTs", Asbeck et al., Aug. 18, 1999, Solid State Electronics 44 (2000) 211 219, pp. 211-219.2"New UV Light Emitter based on AlGaN Heterostructures with Graded Electron and Hole Injectors", Johnson et al., XP-002505432, Mat. Res. Soc. Symp. Proc. vol. 743, 2003, Materials Research Society, pp. 1.2.4.1-1.7.4.6.3"Polarization-Induced 3-Dimensional Electron Slabs in Graded AlGaN Layers", Simon et al., XP-002505433, Mater. Res. Soc. Symp. Proc. vol. 892, 2006 Materials Research Society, pp. 1-6.4Ando et al., "10-W/mm AlGaN-GaN HFET With a Field Modulating Plate", IEEE Electron Device Letters, vol. 24, No. 5, May 2003, pp. 289-291.5Asano K et al, "Novel High Power AlGaAs/GaAs HFET With a Field-Modulating Plate Operated at 35 V Drain Voltage", Electron Devices Meeting 1998, IEDM 98 Technical Digest, International San Francisco, CA USA Dec. 6-9, 1998, Piscataway, NJ USA IEEE US Dec. 6, 1998, pp. 59-62 XP010321500.6B. Gelmont, et al. "Monte Carlo Simulation of Electron Transport in Gallium Nitride", J. Appl. Phys. 74, 1993, pp. 1818-1821.7Chini et al., Power and Linearity Characteristics of Field-Plated Recessed-Gate AlGaN-GaN HEMTS, IEEE Electron Device Letters, vol. 25, No. 5, May 2004, pp. 229-231.8CRC Press, The Electrical Engineering Handbook, Second Edition, DORF, pp. 994, 1997 "Three-terminal Active Microwave Devices".9European Search Report, Feb. 24, 2009, re related European Application No. EP 08253301.10Examination Report from related European Patent Application No. 02769655.8-1235, Dated: Nov. 3, 2008.11Examination Report from related European Patent Application No. 06851411.6-2203, dated: Jan. 26, 2009.12Examination Report re European Application No. 02 792 174.1-1235, Dated Oct. 7, 2008.13Examination Report re related European Application No. 01 905 364.4, dated: Jun. 24, 2009.14Examiner's Report from related Canada Patent Application No. 2,399,547, Dated: Mar. 4, 2009.15Extended European Search Report, for related European Application No. 07253716.0, Dated: Jun. 25, 2009.16First Examination Report from related European Patent Application No. 08250197.4, dated: Jul. 28, 2009.17G. Sullivan et al., "High Power 10-GHz Operation of AlGaN HFET's in Insulating SiC", IEEE Electron Device Letters, vol. 19, No. 6, Jun. 1998, p. 198.18Gaska, et al., "High-Temperature Performance of AlGaN/GaN HFETS on SiC Substrates", IEEE Electron Device Letters, vol. 18, No. 10, Oct. 1997, pp. 492-494.19IEEE Electron Device Letters, vol. 21, No. 2, Feb. 2000, pp. 63-65, "AlGaN/GaN Metal Oxide Semiconductor Heterostructure Field Effect Transistor,", M. Asif Khan et al.20IEEE Electron Device Letters, vol. 21, No. 9, Sep. 2000, pp. 421-423, "High Breakdown GaN HEMT with Overlapping Gate Structure," N.-Q. Zhang et al.21Japanese Patent Application Public Disclosure 2000-68498, Date: Mar. 3, 2000.22Japanese Patent Application Public Disclosure 2001-77353, dated Mar. 23, 2001.23Japanese Publication No. Hei 11-224881, Aug. 17, 1999, Compound Semiconductor Apparatus.24Karmalkar et al., "Enhancement of Breakdown Voltage in AlGaN/GaN High Electron Mobility Transistors Using a Field Plate", IEEE Trans. Electron Devices, vol. 48, No. 8, Aug. 2001, pp. 1515-1521.25Karmalkar S. et al. "Very High Voltage AlGaN/GaN High Electron Mobility Transistors Using a Field Plate Deposited on a Stepped Insulator", Solid State Electronics, Elsevier Science Publishers, Barking. GB, vol. 45, No. 9, Sep. 2001, pp. 1645-1652, XP004317729.26Khan et al., "AlGaN/GaN Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors on SiC Substrates", Applied Physics Letters vo. 77, No. 9, Aug. 2000. pp. 1339-1341.27L. Eastman et al., "GaN Materials for High Power Microwave Amplifiers", Materials Research Society vol. 512 WOCSEMMAD, Monterey, CA Feb. 1998, pp. 3-7.28Li, et al. "High Breakdown Voltage GaN HFET With Field Plate", Electronics Letters, IEE Stevenage GB vol. 37, No. 3, Feb. 1, 2001, pp. 196-197, XP006016221.29Lu et al., "AlGaN/GaN HEMTS on SiC With Over 100 GHz ft and Low Microwave Noise", IEEE Transactions on Electron Devices, vol. 48, No. 3, Mar. 2001, pp. 581-585.30M. Micovic et al., "AlGaN/GaN Heterojunction Field Effect Transistors Grown by Nitrogen Plasma Assisted Molecular Beam Epitaxy", IEEE Trans. Electron Devices, vol. 48, No. 3, Mar. 2001, pp. 591-596.31Mok P. et al, "A Novel High-Voltage High-Speed MESFET Using a Standard GAAS Digital IC Process", IEEE Transactions on Electron Devices, IEEE Inc. New York, US. vol. 41, No. 2, Feb. 1, 1994, pp. 246-250 XP00478051.32Notice Requesting Submission of Opinion re related Korean Application No. 10-2004-7001033, dated: Mar. 9, 2009.33Office Action for family related U.S. Appl. No. 11/356,791, dated: Sep. 2, 2008.34Office Action for family related U.S. Appl. No. 11/799,786, dated Sep. 8, 2008.35Official Rejection of Japanese Patent Application No. 2003-535260, dated: Jun. 19, 2009.36Patent Abstracts of Japan, Pub. 10-223901, Pub. Date: Aug. 21, 1998.37Ping et al., "DC and Microwave Performance of High Current AlGaN Heterostructure Field Effect Transistors Grown on P-Type SiC Substrates", IEEE Electron Device Letters, vol. 19, No. 2, Feb. 1998, p. 54.38R. Gaska et al., "Electron Transport in AlGaN-GaN Heterostructures Grown on 6H-SiC Substrates", Appl. Phys. Lett. 72, No. 6, Feb. 1998, pp. 707-709.39Related European Examination Report for European Patent Application No. 02769655.8, dated: Dec. 8, 2008.40Related Extended European Search Report re European Application No. 08250197.4-1235/1973163, Dated: 11-06-0.41Related Office Action from Japanese Patent Office re Japanese Patent Application No. 2002-590421, dated: Oct. 21, 2008.42Result of Examination for related Korean Application No. 10-2004-7001027, Dec. 15, 2009.43Saito et al., Solid-State Electronics, "Theoretical Limit Estimation of Lateral Wide Bandgap Semiconductor Power-Switching Device", Apr. 1, 2003, pp. 1555-1562.44Saito W. et al. "Design and Demonstration of High Breakdown Voltage GaN High Electron Mobility Transistor (HEMT) Using Field Plate Structure for Power Electronics Applications", Japanese Journal of Applied Physics, Japan Society of Applied Physics, Tokyo, JP vol. 43, No. 4B, Apr. 2004, pp. 2239-2242, ISSN: 021-4922.45Sakai et al., "Experimental Investigation of Dependence of Electrical Characteristics on Device Parameters in Trench MOS Barrier Shottky Diodes", Proceedings of 1998 International Symposium on Power Semiconductor Devices & ICs, Kyoto, pp. 293-296, Jun. 1998.46Second Office Action from related China Application No. 02818502.1., Dated: Feb. 19, 2009.47W. Saito et al., "600V AlGaN/GaN Power-HEMT; Design, Fabrication and Demonstration on High Voltage DC-DC Converter", IEEE IEDM vol. 23, No. 7, 2003, pp. 587-590.48Wakejima A et al. "High Power Density and Low Distortion INGAP Channel FETS With Field-Modulating Plate", IEICE Transactions on Electronics, Institute of Electronics Information and Comm. Eng. Tokyo, Japan, vol. E85-C, No. 12, Dec. 2002, pp. 2041-2045 XP001161324.49Wu et al., "30-W/mm GaN HEMTS by Field Plate Optimization", IEEE Electron Device Letters, vol. 25, No. 3, Mar. 2004, pp. 117-119.50Wu et al., "GaN-Based FETS for Microwave Power Amplification", IEICE Trans. Electron. vol. E82-C, No. 11, Nov. 1999, pp. 1895-1905.51Wu et al., "High Al-Content AlGaN/GaN HEMTS on SiC Substrates With Very-High Power Performance", IEDM-1999 Digest, pp. 925-927, Washington D.C., Dec. 1999.52Wu et al., "High Al-Content AlGaN/GaN MODFETS for Ultrahigh Performance", IEEE Electron Device Letters vol. 19, No. 2, Feb. 1998, pp. 50-53.53Wu et al., "High-Gain Microwave GaN HEMTS With Source-Terminated Field-Plates", CREE Santa Barbara Technology Center.54Wu et al., Bias-Dependent Performance of High-Power AlGaN/GaN HEMTS, IEDM-2001, Washington D.C., Dec. 2-6, 2001, pp. 378-380.55Xing, "High Breakdown Voltage AlGaN-GaN HEMTS Achieved by Multiple Field Plates", IEEE Electron Device Letters, vol. 25, No. 4, Apr. 2004, pp. 161-163.56Y.F. Wu et al. "Very-High Power Density AlGaN/GaN HEMTS", IEEE Transactions on Electronic Devices, vol. 48, Issue 3, Mar. 2001, p. 586.57Zhang AP et al, "Comparison of GaN P-I-N. and Schottky Rectifier Performance" IEEE Transactions on Electron Devices, IEEE Inc. New York, US, vol. 48, No. 3, pp. 407-411, Mar. 2001.58Zhang et al., "High Breakdown GaN HEMT With Overlapping Gate Structure", IEEE Electron Device Letters, vol. 21, No. 9, Sep. 2000, pp. 421-423.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8237198Jan 18, 2011Aug 7, 2012Transphorm Inc.Semiconductor heterostructure diodesUS8289065Sep 9, 2009Oct 16, 2012Transphorm Inc.Inductive load power switching circuitsUS8389977Dec 10, 2009Mar 5, 2013Transphorm Inc.Reverse side engineered III-nitride devicesUS8390000Aug 28, 2009Mar 5, 2013Transphorm Inc.Semiconductor devices with field platesUS8493129Sep 14, 2012Jul 23, 2013Transphorm Inc.Inductive load power switching circuitsUS8519438Apr 23, 2008Aug 27, 2013Transphorm Inc.Enhancement mode III-N HEMTsUS8531232Sep 14, 2012Sep 10, 2013Transphorm Inc.Inductive load power switching circuitsUS8541818Jun 26, 2012Sep 24, 2013Transphorm Inc.Semiconductor heterostructure diodesUS8587031Jul 25, 2012Nov 19, 2013Massachusetts Institute Of TechnologyDual-gate normally-off nitride transistorsUS8598937Oct 7, 2011Dec 3, 2013Transphorm Inc.High power semiconductor electronic components with increased reliabilityUS8643062Feb 2, 2011Feb 4, 2014Transphorm Inc.III-N device structures and methodsUS8692294Jan 24, 2013Apr 8, 2014Transphorm Inc.Semiconductor devices with field platesUS8716141Mar 4, 2011May 6, 2014Transphorm Inc.Electrode configurations for semiconductor devicesUS8742459May 14, 2009Jun 3, 2014Transphorm Inc.High voltage III-nitride semiconductor devicesUS8742460Dec 15, 2010Jun 3, 2014Transphorm Inc.Transistors with isolation regionsUS8772842Mar 4, 2011Jul 8, 2014Transphorm, Inc.Semiconductor diodes with low reverse bias currentsUS8816751Aug 5, 2013Aug 26, 2014Transphorm Inc.Inductive load power switching circuitsUS8841702Jul 30, 2013Sep 23, 2014Transphorm Inc.Enhancement mode III-N HEMTsUS8860495Oct 31, 2013Oct 14, 2014Transphorm Inc.Method of forming electronic components with increased reliabilityUS8895421Dec 11, 2013Nov 25, 2014Transphorm Inc.III-N device structures and methodsUS8895423May 28, 2014Nov 25, 2014Transphorm Inc.Method for making semiconductor diodes with low reverse bias currentsUS8901604Sep 6, 2011Dec 2, 2014Transphorm Inc.Semiconductor devices with guard ringsUS8916459Oct 30, 2013Dec 23, 2014Fujitsu LimitedCompound semiconductor device with mesa structureUS20090057719 *Jul 25, 2008Mar 5, 2009Fujitsu LimitedCompound semiconductor device with mesa structure* Cited by examinerClassifications U.S. Classification257/488, 257/E21.407, 257/E21.403, 257/E29.009, 257/367International ClassificationH01L29/93Cooperative ClassificationH01L29/2003, H01L29/7786, H01L29/404, H01L29/66462European ClassificationH01L29/66M6T6E3, H01L29/778E, H01L29/40P2Legal EventsDateCodeEventDescriptionJan 30, 2007ASAssignmentOwner name: CREE, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WU, YIFENG;PARIKH, PRIMIT;MISHRA, UMESH;REEL/FRAME:018827/0724Effective date: 20070126Owner name: CREE, INC.,CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WU, YIFENG;PARIKH, PRIMIT;MISHRA, UMESH;US-ASSIGNMENT DATABASE UPDATED:20100406;REEL/FRAME:18827/724Owner name: CREE, INC.,CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WU, YIFENG;PARIKH, PRIMIT;MISHRA, UMESH;REEL/FRAME:018827/0724Effective date: 20070126Owner name: CREE, INC.,CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WU, YIFENG;PARIKH, PRIMIT;MISHRA, UMESH;US-ASSIGNMENT DATABASE UPDATED:20100406;REEL/FRAME:18827/724Effective date: 20070126Sep 28, 2010CCCertificate of correctionSep 4, 2013FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services