Source: http://www.google.de/patents/US20090153165
Timestamp: 2013-05-19 01:25:00
Document Index: 620877876

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US20090153165 - High Density Interconnect System Having Rapid Fabrication Cycle - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr » Erweiterte Patentsuche | Webprotokoll | Anmelden Erweiterte Patentsuche PatenteAn improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises...http://www.google.de/patents/US20090153165?utm_source=gb-gplus-sharePatent US20090153165 - High Density Interconnect System Having Rapid Fabrication Cycle Ver�ffentlichungsnummerUS20090153165 A1PublikationstypAnmeldung Anmeldenummer12/354,520 Ver�ffentlichungsdatum18. Juni 2009Eingetragen15. Jan. 2009 Priorit�tsdatum27. Mai 1999Auch ver�ffentlicht unterUS7872482US7884634US20080246500 Ver�ffentlichungsnummerUS 2009/0153165 A1US2009/0153165A1 ErfinderFu Chiung ChongAndrew KaoAnna LitzaDouglas McKayDouglas ModlinSammy MokNitin ParekhZhaohui ShanFrank John SwiatowiecUrspr�nglich Bevollm�chtigterAdvantest (Singapore) Pte LtdNanonexus (Assignment For The Benefit Of Creditors), LlcVerigy (Singapore) Pte. Ltd. US-Klassifikation324/754.829/825Internationale KlassifikationH05K7/06G01R1/073G01R31/28G01R31/02 UnternehmensklassifikationG01R1/07378G01R31/2889 Europ�ische KlassifikationG01R31/28G5CReferenzen Referenziert von (1)Externe LinksUSPTO USPTO-Zuordnung EspacenetHigh Density Interconnect System Having Rapid Fabrication CycleUS 20090153165 A1 Zusammenfassung An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the top surface to the bottom surface, said electrical conductors forming a pattern of electrical connections on the bottom surface of said motherboard substrate; a plurality of probe springs for providing electrical connections to at least one integrated circuit device on a semiconductor wafer, said probe springs having electrical connections to a plurality of standard connections on a probe spring mounting surface, said standard connections corresponding to said pattern of electrical connections on said bottom surface of said motherboard substrate; a standardized vertical translation block having a motherboard interface surface and a probe spring mounting surface comprising a plurality of electrical conductors corresponding to the pattern of electrical connections on the bottom surface of said motherboard substrate, said electrical conductors extending from said motherboard surface to said probe spring mounting surface thereby forming a standardized component for providing a plurality of electrically conductive connections between said pattern of electrical connections on the bottom surface of said motherboard substrate and said probe spring mounting surface extending over a predetermined vertical translation distance.
2. The apparatus of claim 1, said motherboard substrate comprising a multi-layered printed wiring board.
3. The apparatus of claim 1, said standardized vertical translation block comprising any of a ceramic, a multilayered ceramic, and a co-fired ceramic
4. The apparatus of claim 1, wherein said probe springs are plated.
providing a plurality of customizable components, each having a rapid design and fabrication process cycle time; providing a plurality of standard components, wherein design and fabrication process cycle time of at least one of said standard components is longer than the rapid design and fabrication process cycle time for the customizable components; and assembling and testing a probe card from both the customizable components and the standard components, wherein the probe card assembly and test cycle time is no greater than that of the longest of the cycle times for the customizable components.
wherein the customizable components having rapid cycle times comprise any of a mother board and a probe chip assembly; and wherein the standard components having cycle times that may be longer than those of the mother board and probe chip comprise any of a probe tip support substrate and at least one interposer.
CROSS REFERENCE TO RELATED APPLICATIONS This Application is a Divisional of U.S. patent application Ser. No. 11/858,064, entitled High Density Interconnect System Having Rapid Fabrication Cycle, filed 19 Sep. 2007, which is a Continuation of U.S. patent application Ser. No. 11/133,021 (NNEX0001CIP3), entitled High Density Interconnect System Having Rapid Fabrication Cycle, filed 18 May 2005, which claims priority to (NNEX0019PR) U.S. Provisional Application No. 60/573,541, entitled Quick-Change Probe Chip, filed 20 May 2004; (NNEX0021PR) U.S. Provisional Application No. 60/592,908, entitled Probe Card Assembly with Rapid Fabrication Cycle, filed 29 Jul. 2004; and (NNEX0015PR) U.S. Provisional Application No. 60/651,294, entitled Nano-Contactor Embodiments for IC Packages and Interconnect Components, filed 8 Feb. 2005.
U.S. patent application Ser. No. 11/133,021 (NNEX0001CIP3), entitled High Density Interconnect System Having Rapid Fabrication Cycle, filed 18 May 2005, is also a Continuation-In-Part of U.S. patent application Ser. No. 10/870,095 (NNEX0001CIP2), entitled Enhanced Compliant Probe Card Systems Having Improved Planarity, US Filing Date 16 Jun. 2004, which is a Continuation-In-Part of U.S. patent application Ser. No. 10/196,494 (NNEX0012), entitled Mosaic Decal Probe, filed 15 Jul. 2002, issued as U.S. patent Ser. No. 6,710,609 on 23 Mar. 2004.
U.S. patent application Ser. No. 10/870,095 (NNEX0001CIP2), entitled Enhanced Compliant Probe Card Systems Having Improved Planarity, US Filing Date 16 Jun. 2004, is also a Continuation-In-Part of U.S. patent application Ser. No. 10/178,103 (NNEX0001CIP), entitled Construction Structures and Manufacturing Processes for Probe Card Assemblies and Packages Having Wafer Level Springs, US Filing Date 24 Jun. 2002, issued as U.S. patent Ser. No. 6,917,525 on 12 Jul. 2005, which is a Continuation-In-Part of U.S. patent application Ser. No. 09/980,040 (NNEX0003), entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date 27 Nov. 2001, issued as U.S. patent Ser. No. 6,799,976 on 5 Oct. 2004, which claims priority from PCT patent application Ser. No. PCT/US00/21012 (NNEX0003P), filed Jul. 27, 2000, which claims priority from U.S. Provisional Application No. 60/146,241 (NNEX0003PR), filed on 28 Jul. 1999.
U.S. patent application Ser. No. 09/980,040 (NNEX0003), entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date 27 Nov. 2001, issued as U.S. patent Ser. No. 6,799,976 on 5 Oct. 2004, also claims priority from PCT Patent Application Serial No. PCT/US00/14164 (NNEX0001P), entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, filed 23 May 2000, which claims priority from U.S. Provisional Application No. 60/136,636 (NNEX0001PR), entitled Wafer Interface for High Density Wafer Probe Card, filed on 27 May 1999.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Introductory disclosure regarding structures, processes and systems disclosed herein is seen in: U.S. Provisional Application No. 60/136,636 (NNEX0001PR), entitled Wafer Interface for High Density Probe Card, filed 27 May 1999; U.S. Provisional Application No. 60/146,241 (NNEX0003PR), entitled Method of Massively Parallel Testing of Circuits, filed 28 Jul. 1999; U.S. Provisional Application No. 60/573,541 (NNEX0019PR), entitled Quick-Change Probe Chip, filed 20 May 2004; U.S. Provisional Application No. 60/592,908 (NNEX0021 PR), entitled Probe Card Assembly with Rapid Fabrication Cycle, filed 29 Jul. 2004; U.S. Provisional Application No. 60/651,294 (NNEX0015PR), entitled Nano-Contactor Embodiments for IC Packages and Interconnect Components, filed 8 Feb. 2005; U.S. patent application Ser. No. 10/870,095 (NNEX0001CIP2), entitled Enhanced Compliant Probe Card Systems Having Improved Planarity, US Filing Date 16 Jun. 2004; U.S. patent application Ser. No. 10/178,103 (NNEX0001CIP), entitled Construction Structures and Manufacturing Processes for Probe Card Assemblies and Packages Having Wafer Level Springs, US Filing Date 24 Jun. 2002; U.S. patent application Ser. No. 09/980,040 (NNEX0003), entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date 27 Nov. 2001; PCT patent application Ser. No. PCT/US00/21012 (NNEX0003P), filed 27 Jul. 2000; PCT patent application Ser. No. PCT/US00/14164 (NNEX0001P), entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date 23 May 2000; and U.S. patent application Ser. No. 10/069,902 (NNEX0004), entitled Systems for Testing and Packaging Integrated Circuits, filed 28 Jun. 2002, which is incorporated herein in its entirety by this reference thereto.
Probe Chip Planarization FIG. 15 shows a first step 270 in a probe chip planarization process 275, in which a plane 280 of optimum probe tip planarity is determined for a probe chip 68 as fabricated. As seen in FIG. 15, a probe chip 68 comprises a probe chip substrate 272 having a probing surface 93 a and a bonding surface 93 b opposite the probing surface 93 a, a plurality of spring probes 180 on the probing surface 93 a arranged 273 to correspond to the bonding pads of an integrated circuit 20 and extending from the probing surface 93 a to define a plurality of probe tips 181, a corresponding second plurality of bonding pads 278 located on the bonding surface 93 b and arranged in the second standard configuration 275, and electrical connections 274 extending from each of the spring probes 180 to each of the corresponding second plurality of bonding pads 278.
Probe Card Calibration Data Mechanical parallelism calibration data, such as but not limited to shim thicknesses and/or differential screw settings, are preferably taken at the factory for the PCIA 62 and for non-parallel probe chip assemblies 68. The calibration data can be stored in a data base or in non-volatile memory chips mounted on the PCIA 62 or the probe chip assemblies 68. The PCIA calibration data provides the information required to establish the probe chip mounting reference plane 92 relative to the PCIA mounting surface 48. The probe chip assembly calibration data in combination with the PCIA calibration data provides the information required to set the PCIA planarity adjustments to make the stress metal spring (SMS) probe tips 181 on the probe chip 68 parallel to the plane of PCIA mounting surface 48.
Z-Block Calibration Tool A Z-block calibration tool is used to establish the probe chip assembly mounting reference plane 92 within a PCIA 62. This tool is fabricated to function as a mechanical reference standard with a sufficiently high degree of flatness and parallelism between its surfaces, to accurately determine the parallelism adjustment parameters of the probe chip assembly mounting reference plane 92.
In-Situ Calibration Probe Chip Assembly Some embodiments of the probe chip assemblies 68 preferably designed to be installed and used for accelerated testing and verification of PCIA using a specific wafer prober 12, or a API PrecisionPoint VX, or other tool having a similar function, in which the tool may be used to adjust the planarity of the probe chip assembly mounting reference plane 92 in the PCIA 62. The calibration probe chip assembly is designed to include test structures that aid in reliability, accuracy, and diagnostic testing of the PCIA and/or the Probe Chip technology.
Parallelism Error Measurement and Correction The parallelism error for a probe chip assembly mounting reference plane (92) for a probe chip interface assembly (PCIA) 62 can be measured and corrected, such as by:
System Advantages The quick change probe chip system 64 and method 220 lowers cost of ownership by allowing users to easily change probe chip assemblies 68, without the need to send an entire probe card assembly 68 back to the manufacturer. The quick change probe chip system 64 and method 220 allows a trained user or field service engineer to quickly change the probe chip 68 at the user site.
Referenziert von Zitiert von PatentEingetragen Ver�ffentlichungsdatum Antragsteller TitelUS815411931. M�rz 201010. Apr. 2012Toyota Motor Engineering & Manufacturing North America, Inc.Compliant spring interposer for wafer level three dimensional (3D) integration and method of manufacturingDrehenOriginalbildGoogle-Startseite - Sitemap - USPTO-Bulk-Downloads - Datenschutzerkl�rung - Nutzungsbedingungen - �ber Google Patente - Feedback gebenDaten bereitgestellt von IFI CLAIMS Patent Services.© 2012 Google