Source: https://patents.google.com/patent/US4872107?oq=6981235
Timestamp: 2018-03-23 09:33:08
Document Index: 123809520

Matched Legal Cases: ['art 1', 'art 2', 'art 1', 'art 2', 'art 2', 'art 2']

US4872107A - Floppy disk controller with means to change clock rate automatically - Google Patents
Floppy disk controller with means to change clock rate automatically Download PDF
US4872107A
US4872107A US06487793 US48779383A US4872107A US 4872107 A US4872107 A US 4872107A US 06487793 US06487793 US 06487793 US 48779383 A US48779383 A US 48779383A US 4872107 A US4872107 A US 4872107A
US06487793
Melvyn J. Marple
Andrew S. Potemski
A processor and disk controller are arranged to operate with either of two types of disk drive, a drive for a five and one-fourth inch disk or a drive for an eight inch disk, and a method and apparatus are provided to test a port to detect which type disk is connected. The disk drives do not directly signal their type, and in one operation this information is derived from "drive ready", signals that are supplied separately by each disk type. In an alternative method and apparatus, this information is derived by a test in which the clock speed is changed.
This invention relates to a data processing system having a central processor, floppy disk peripheral storage devices, and a controller for operating the disk according to functions specified by the processor. More specifically the invention relates to a method and apparatus for operating the system with two disk drives that differ in some of their connections and operations with the controller and processor.
An application Ser. No. 06/487,660, filed on the same day as this application, describes a display system that is used with the data processor of this invention.
This invention has been embodied in a data processing system that is described in two publications, "Computer System Operating System Reference Manual Part 1 Operating System" and "Computer System Operating System Reference Manual Part 2 Logical I/O and System Services", which are available from the assignee of this invention and which are incorporated by reference in this specification. They will be referred to as "Part 1" and "Part 2" respectively.
The floppy disk is a familiar component of many data processing systems. Commonly, a disk is five and one-quarter inches in diameter or eight inches in diameter. A component that is called the disk drive rotates the disk and contains a read/write head. A component called a controller has circuits that perform specialized control functions in response to generalized commands from a processor. The description of the preferred embodiment of the invention will point out other conventional features that are significant in understanding this invention.
In the system of this invention, the processor is provided with ports that can accept connections to a drive for a five and one-quarter inch disk or a drive for an eight inch disk. A clock circuit provides clock pulses at the required rate for either drive, and the system of the invention is operable automatically to test a port to detect the type of drive that is connected and to control the clock for the correct speed. The system is also operable to detect an error that may be caused if a user connects a different drive at a port without manually signalling the system. When such an error is detected, the system changes the clock to the speed for a different drive and makes a test to determine whether this change has corrected the error condition.
FIG. 1 is a diagram of the data processing system of this invention.
THE PREFERRED EMBODIMENT 1. Introduction
Section 2 introduces the conventional features of the preferred system. Section 3 describes a clock circuit that supplies clock signals for both disk sizes. Sections 4 and 5 describe three registers that are used for status and control information in the operation of the invention. Section 5 describes the ready signals for the two drives. Section 6 summarizes a description in "Part 2" that explains operations to read and load these registers. Section 7 describes an operation to select the disk. Section 8 describes an additional operation to select the disk.
2. Introduction--Conventional Features
The drawing shows a processor 12, a disk drive 14, a disk drive controller 15, a bi-directional bus 16 that interconnects the processor and the controller, and a two part connector 18, 19 and a cable 21 that interconnect the disk drive with the other components. The processor has four ports where a disk drive can be connected. The drawing shows only one port which will be called port 1. Each port has a fixed plug connection 18 for receiving a separable plug 19 from a drive for a five and one-quarter inch disk or from a drive for an eight inch disk. The plug connection 18 at the processor enclosure may be two separate plugs, but it is shown as a single functional block in the drawing because many of the connections are identical for both drives and because the drawing is intended to represent the situation in which the system does not know what drive has been connected to the port.
3. The Clock Circuit
It will be helpful to review the general function of a clock in a magnetic recording system. The recording track of a disk is conceptually divided into a sequence of spaces where a 1 bit or a 0 bit can be recorded. A mark is recorded on the track by a change in the direction of magnetization of a magnetic material on the surface of the disk. As an example, a mark in a bit space can represent a 1 bit and the absence of a mark in a bit space can represent a 0 bit. A clock circuit has an oscillator that produces pulses at the same rate that the bit positions pass under the read/write head as the disk is rotated. The clock provides additional pulses at multiple or sub-multiple frequencies. In some systems a clock mark is recorded at the beginning of each bit space so that the absence of a mark following the clock mark can be easily interpreted as a 0 bit. In other systems the oscillator pulses indicate the location of a bit space and clock marks are recorded only as necessary to provide a combination of clock marks and 1 bit marks that is sufficient to keep the oscillator synchronized through a sequence of 0 bits where there would otherwise be no recording marks.
4. The Control Register 27
A register 27 receives a byte of control information from the processor on bus 16 and has connections to transmit this information to the selected disk drive 14 and to the controller 15. A 1 bit in register position 1 selects port 1 which is shown in the drawing. A 1 bit in one of the register positions 2 to 4 selects the corresponding one of the other three disk drive ports. The controller and the other components of the drawing operate the four disk drives one at a time, and logic circuits that are not shown enable circuit paths between the selected drive and the components of the drawing.
5. The Status Registers 30 and 32
An eight bit register 30 receives an input at bit position 2 from a line 28 that signals that a drive for a five and one quarter inch disk is ready for read and write operations. This signal will be called "Drive Status" to distinguish it from a corresponding signal for the eight inch disk drive. Other positions of this register are not significant in this description.
6. Related Operations of the Processor
A read or write operation on a disk takes place through the cooperation of a user program and several programs of the operating system. The operating of the preferred system is described in "Part 2", but it will be helpful to summarize the features that particularly apply to this invention.
Suppose that the system has an eight inch disk drive at port 1 and that the processor is turned on. The diskette driver loads a 1 bit into position 5 of field PDBFLG of the PDB to show that the actual configuration of port 1 has not been entered into field PDBSEL, and it begins its routine to test each disk drive port to determine whether a disk drive is attached and whether it is for five and one quarter inch disk or an eight inch disk. Note that a port must be selected before the status lines 28 and 33 are valid. The program first selects for an eight inch drive and tests status and, if this test is unsuccessful, selects for a five and one quarter inch disk drive and tests for status.
8. A Further Improvement
Suppose that the system has been operating normally with a five and one-quarter inch disk drive at port 1 and that the user has disconnected this drive and has connected a drive for an eight inch disk. When the disk at port 1 is next accessed, the diskette driver loads register 27 from the PDBSEL which has bit 7 set for the clock rate for a five and one-quarter inch drive. The drive will operate normally for a read operation to find an addressed track except that the data is garbled because the clock speed is wrong. As the invention has been described so far, the controller circuit would signal an error in its internal status register 32 and the diskette driver would branch to an error routine which would print an error message on the associated display screen. The user might recognize the cause of the error and turn the processor off and back on again or the user might perform this operation as a random recovery try. When the processor is turned off and then turned back on again, the diskette driver would construct the appropriate PDB in the way that has already been described.
From the detailed description of a preferred embodiment of the invention, those skilled in the art will recognize various modifications in implementation within the spirit of the invention and the scope of the claims.
1. In a data processing system having a processor (12) and an I/O controller (15), said controller having a plurality of ports, each port having a plug (18) for connecting the processor and the controller to operate a peripheral device (14) of a first type (8" diskette) or a second type (51/4 diskette), each of said devices having means for signaling a ready condition, said controller having means (bit positions 1-4 in register 27) for selecting one of said ports, wherein the improvement comprises,
a first ready signal line (33) connected to each port plug for signaling a ready condition from a device of the first type and a second ready signal line (28) connected to each port plug for signaling a ready condition from a device of the second type,
first binary storage means (PDBSEL) in the processor for each port for registering information that a port has a device of the first type or of the second type connected and a second binary storage means (PDBFLG) for registering information that the type is undetermined, and means (diskette driver) operable when the processor is initialized for resetting the second storage means to its undetermined signal state and resetting the first storage means to said first one of said types,
a first register (27) for holding the information in the first binary storage means for a selected port, including the device type information,
logic and storage means responsive to the device type information in said first register and to said ready signal lines for signaling whether a device of the selected type is ready,
driver program means (diskette driver) responsive to a signal in said secondary binary storage means that the type is undetermined to access a peripheral device at the selected port according to the type signaled in the first storage means and for testing said signal that a device of the selected type is ready, and
means responsive to a signal that a device of said first type is not ready to make a similar test for a device of the second type.
2. In a system having a processor (12) and a controller (15) for a first drive for a floppy disk of a first clock rate and alternately for a second drive for a floppy disk of a second clock rate, wherein the improvement comprises,
a clock (24) providing signals of the first clock rate (25) or signals of the second clock rate (26) to the controller, according to a binary control signal (register 27 bit 7),
a first line (33) connectable to a drive of the first clock rate and a second line (28) releasably connectable to a drive of the second clock rate for separately receiving a ready signal from a first drive or a second drive,
means (27) providing a binary signal to control the clock rate,
logic and storage means responsive to said binary control signal and to said ready signals for signaling that the clock rate is correct or not correct for a device connected to the controller,
device driver program means (diskette driver) responsive to said signal that the clock rate is correct or not correct for a connected device for setting said binary control signal for the clock rate of the drive that is connected.
3. In a data processing system having a processor (12) and releasable means connecting the processor to operate with an I/O device having a first clock rate or with a device having a second clock rate comprising,
plug means (18) for connecting a device (14) having a first clock rate to operate with the processor and to provide a ready signal at a first ready signal terminal of the system (33) and alternatively for connecting a device having a second clock rate to operate with the processor and to provide a ready signal at a second ready signal terminal of the system (28),
a clock (24) operable at the first rate or at the second rate and means (27) for supplying a binary signal to select the clock rate,
logic and storage means responsive to said binary control signal and to said ready signal terminals for signaling that the clock rate is correct or not correct for a device connected to the controller,
device driver program means (diskette driver) for initially setting said means for supplying a binary signal for operating the clock at one of said rates and for testing said signal that the clock rate is correct for a connected device and responsive to a signal that the clock rate is not correct to change to said second clock rate and test the second ready terminal.
4. The system of claim 1 wherein said means for signaling that a device of the selected type is ready comprises,
a second register (32) having a bit position (seven) for signaling an error to said device driver program,
a logic circuit responsive to the selection of a device of said second type (51/4 inch drive) signaled in said first register (27) to register in said second register the ready or not ready status of a device of said first type (8" disk) and responsive to said first register on the selection of a device of said second type for registering a non-error in said second register,
wherein said device driver program means comprises means for carrying out the following sequence of steps,
loading said first register for selection of a device of said first type,
testing said second register (32) for an error and proceeding with operations for said first type device in the absence of an error,
in the presence of an error, resetting said first register (27) for a device of said second type and thereby clearing the error condition at the second register (32) and testing said ready line for the device of the second type and proceeding with operations for said second type device if the line signals ready.
US06487793 1983-04-22 1983-04-22 Floppy disk controller with means to change clock rate automatically Expired - Fee Related US4872107A (en)
US06487793 US4872107A (en) 1983-04-22 1983-04-22 Floppy disk controller with means to change clock rate automatically
US4872107A true US4872107A (en) 1989-10-03
ID=23937139
US06487793 Expired - Fee Related US4872107A (en) 1983-04-22 1983-04-22 Floppy disk controller with means to change clock rate automatically
US (1) US4872107A (en)
EP0467520A2 (en) * 1990-07-19 1992-01-22 International Business Machines Corporation Personal computer with drive identification
Grofton, Peter W., "Mastering Serial Communications", Sybex, pp. 2-3.
Grofton, Peter W., Mastering Serial Communications , Sybex, pp. 2 3. *
EP0467520A3 (en) * 1990-07-19 1992-09-02 International Business Machines Corporation Personal computer with drive identification
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATON ARMONK,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:MARPLE, MELVYN J.;POTEMSKI, ANDREW S.;REEL/FRAME:004155/0134
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATON,NEW YOR
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MARPLE, MELVYN J.;POTEMSKI, ANDREW S.;REEL/FRAME:004155/0134