Source: http://www.google.com/patents/US8115586?dq=5,072,412
Timestamp: 2017-07-23 19:08:42
Document Index: 65675604

Matched Legal Cases: ['§371', 'Application No. 2006', 'art 118', 'art 118', 'art 118', 'art 191']

Patent US8115586 - Variable resistance element, and its manufacturing method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsProvided are a variable resistive element having a configuration that the area of an electrically contributing region in a variable resistor body is smaller than the area defined by an upper electrode or a lower electrode, and a method for manufacturing the variable resistive element. The cross section...http://www.google.com/patents/US8115586?utm_source=gb-gplus-sharePatent US8115586 - Variable resistance element, and its manufacturing methodAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8115586 B2Publication typeGrantApplication numberUS 12/298,089PCT numberPCT/JP2007/052833Publication dateFeb 14, 2012Filing dateFeb 16, 2007Priority dateApr 28, 2006Fee statusPaidAlso published asCN101432879A, CN101432879B, US20090096568, WO2007125668A1Publication number12298089, 298089, PCT/2007/52833, PCT/JP/2007/052833, PCT/JP/2007/52833, PCT/JP/7/052833, PCT/JP/7/52833, PCT/JP2007/052833, PCT/JP2007/52833, PCT/JP2007052833, PCT/JP200752833, PCT/JP7/052833, PCT/JP7/52833, PCT/JP7052833, PCT/JP752833, US 8115586 B2, US 8115586B2, US-B2-8115586, US8115586 B2, US8115586B2InventorsYasunari Hosoi, Kazuya Ishihara, Takahiro Shibuya, Tetsuya Ohnishi, Takashi NakanoOriginal AssigneeSharp Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (15), Non-Patent Citations (5), Referenced by (13), Classifications (21), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetVariable resistance element, and its manufacturing method
US 8115586 B2Abstract
1. A variable resistive element comprising;
This application is a National Phase filing under 35 U.S.C. §371 of International Application No. PCT/JP2007/052833 filed on Feb. 16, 2007, and which claims priority to Japanese Patent Application No. 2006-125766 filed on Apr. 28, 2006.
The present invention relates to a variable resistive element comprising an electrode, another electrode and a variable resistor body, wherein the variable resistor body is provided between the one electrode and the other electrode, and an electrical resistance of the variable resistive element is changed by applying a voltage pulse to between both of the electrodes, and relates to it's manufacturing method.
In recent years, a variety of device structures are presented, such as a ferroelectric random access memory (FeRAM), a magnetic RAM (MRAM), a phase change RAM (PRAM), or the like, as a next generation nonvolatile RAM (NVRAM) for fast operation possible taking the place of a flash memory. And then a keen development race is performed from points of view of a higher performance, a higher reliability a lower cost and a higher integrity of manufacturing processes. However, each of such the current memory devices has both advantages and disadvantages respectively, and it is still a long way away from realizing an ideal universal memory having every advantage of a static RAM (SRAM), a dynamic RAM (DRAM) and the flash memory.
Patent document 1: U.S. Pat. No. 6,204,139 Nonpatent document 1: S. Q. Liu et al., “Electric-pulse-induced reversible Resistance change effect in magnetoresistive films”, Applied Physics Letters, vol. 76, pp. 2749-2751 (2000) Nonpatent document 2: H. Pagnia et al., “Bistable Switching in Electroformed Metal-Insulator-Metal Devices”, Phys. Stat. Sol. (a), vol. 108, pp. 11-65 (1988) Patent document 2: Japanese published patent publication 2002-537627 Nonpatent document 3: I. G. Baek et al., “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, IEDM 04, pp. 587-590 (2004) DISCLOSURE OF THE INVENTION
At the period of writing operation regarding data in the above mentioned nonvolatile memory device, that is to say, in the period from starting applying an electric pulse to between the upper electrode and the lower electrode to reaching a predetermined resistance value regarding the variable resistor body, a transient current flows through the variable resistive element (R). Such the current is called a programming current or an erasing current corresponding to a direction of change regarding the electrical resistance respectively. For example, in the case of using the oxide of transition metal element as the material for variable resistor body, there is reported in the nonpatent document 3 wherein the NiO layer is used that the programming current and the erasing current for an electrode surface area of 0.3×0.7 μm2 are approximately 1 mA respectively. Both amounts of such the currents correspond to an area of an electrically contributing region in the variable resistor body, and then it is able to suppress the programming current and the erasing current by decreasing such the area, and it becomes able to suppress a current consumption in the nonvolatile memory device as well.
For achieving the above mentioned object, a variable resistive element according to the present invention is characterized by comprising a variable resistor body provided between two electrodes, wherein an electrical resistance of between the two electrodes is changed by applying a voltage pulse to between the two electrodes, a cross-sectional shape of a current path, in which an electric current flows through between the two electrodes via the variable resistor body at the time of applying the voltage pulse to between the two electrodes, is formed with a line width of narrower than that of any of the two electrodes and the line width of the cross-sectional shape is smaller than a minimum work dimension regarding manufacturing processes.
In the variable resistive element of the present invention, the cross-sectional shape of the current path, in which the electric current flows through between the upper and the lower electrodes via the variable resistor body at the time of applying the voltage therebetween, that is the electrically contributing region in the variable resistor body is formed with the line width of narrower than that of any of the upper and the lower electrodes and of smaller than the minimum work dimension regarding the manufacturing processes. Therefore, it becomes able to reduce the current consumption at the period of programming or erasing thereby, and then it becomes able to manufacture the memory element reproducibly with the stable switching operation without becoming the programming impossible due to the low electrical resistance thereof.
FIG. 1 is a brief cross sectional view showing a configuration of a variable resistive element according to the first embodiment of the present invention.
R: Variable Resistive Element
Preferred embodiments will be described in detail below with reference to the drawings regarding a variable resistive element (referred to as the present invention element hereinafter) and it's manufacturing method (referred to as the present invention method hereinafter) according to the present invention.
The first embodiment according to the present invention element and the present invention method (properly referred to as the present embodiment hereinafter) will be described in detail below with reference to FIG. 1 to FIG. 5.
First, a base insulating layer 15 is to be formed on a semiconductor substrate 16 that peripheral circuits and the like (not shown) are properly formed on. According to the present embodiment, after depositing the base insulating layer 15 of borophosphosilicate glass (BPSG) with a thickness of 1500 nm, a surface of such the layer is flattened by polishing the surface of the BPSG layer 15 on a top surface of the semiconductor substrate 16 to be the thickness of 800 nm using a so-called chemical mechanical polishing (CMP) method. Next, a material layer 11 to be a lower electrode wiring is to be deposited thereon. According to the present embodiment, a Ti layer of 5 nm thickness, a TIN layer of 20 nm thickness, an Al—Cu layer of 200 nm thickness, another Ti layer of 5 nm thickness, and another TiN layer of 100 nm thickness are to be deposited in order using a spattering method respectively, as a multilayer structure of TiN/Ti/Al—Cu/TiN/Ti. Moreover, an SiN layer 17 is to be deposited with the thickness of 150 nm on the material layer 11 to be the lower electrode wiring using a chemical vapor deposition (CVD) method. Next, the lower electrode wiring is to be formed by etching the SiN layer 17 and the material layer 11 to be the lower electrode wiring using a photolithography method with a resist as a mask (not shown) patterned as a line and space (L/S) shape shown as the lower electrode wiring BE in FIG. 2. And then as shown in FIG. 3A, an SiO2 layer 18 is to be deposited with the thickness of 600 nm using the CVD method thereunto.
Next, a TiO2 layer 13 is to be formed by thermal oxidizing in an atmosphere including oxygen at a temperature of between 250 and 450° C. as one example of the variable resistor body formed by oxidizing an exposed apical part of the bump electrode material 12 comprised of the TiN layer, as shown in FIG. 4F. According to the present embodiment, the variable resistor body is to be the TiO2 layer, however, it is also possible to form a TiO2-xNx layer having a characteristic of variable electrical resistance by controlling properly an oxidation condition, such as an oxidation temperature, an oxygen concentration, or the like.
Next, a material layer 14 to be an upper electrode wiring is to be formed over the surface thereof. According to the present embodiment, a TiN layer of 20 nm thickness, an Al—Cu layer of 200 nm thickness, a Ti layer of 5 nm thickness, and another TiN layer of 100 nm thickness are to be deposited in order using the spattering method respectively, as a multilayer structure of TiN/Ti/Al—Cu/TiN. Next, the upper electrode wiring 14 is to be formed by etching the material layer 14 to be the upper electrode wiring, using the photolithography method with the resist as the mask (not shown) patterned as the line and space (L/S) shape shown as the upper electrode wiring TE in FIG. 2. Moreover, an interlayer insulating layer 20 is to be deposited thereunto, and then a contact wiring (not shown) and a metal wiring (not shown) are to be formed for the upper electrode wiring 14 and the lower electrode wiring 11 respectively, as shown in FIG. 4G.
The second embodiment according to the present invention element and the present invention method (properly referred to as the present embodiment hereinafter) will be described in detail below with reference to FIG. 6 to FIG. 9. Here, a detailed description for a process overlapping that of the first embodiment is properly omitted with mentioning that effect.
First, a base insulating layer 65 is to be formed on a semiconductor substrate 66 that peripheral circuits and the like (not shown) are properly formed. According to the present embodiment as well as the first embodiment, after depositing the base insulating layer of BPSG 65 with the thickness of 1500 nm, the surface of the layer is flattened by polishing the surface of the BPSG layer 65 using the CMP method to be the thickness of 800 nm on the top surface of the semiconductor substrate 66. Next, a material layer 61 to be a lower electrode wiring is to be deposited thereon. According to the present embodiment, the Ti layer of 5 nm thickness, the TiN layer of 20 nm thickness, the Al—Cu layer of 200 nm thickness, the other Ti layer of 5 nm thickness, and the other TiN layer of 100 nm thickness are to be deposited in order using the spattering method respectively, as the multilayer structure of TiN/Ti/Al—Cu/TiN/Ti. Moreover, an SiN layer 67 is to be deposited using the CVD method with the thickness of 150 nm on the material layer 61 to be the lower electrode wiring. Next, the lower electrode wiring is to be formed as shown in FIG. 7A, by etching the SiN layer 67 using the photolithography method with the resist as the mask (not shown) patterned as the line and space (L/S) shape shown as the lower electrode wiring BE in FIG. 2, by removing the resist thereafter, and by etching the material layer 61 to be the lower electrode wiring using such the patterned SiN layer 67 as the other mask thereafter.
Next, a TiO2 layer 63 as one example of the variable resistor body is to be formed by thermal oxidizing the top part of the exposed bump electrode material 62 comprised of the TiN layer in the atmosphere including oxygen at the temperature of between 250 and 450° C., as shown in FIG. 8F.
Next, a material layer 64 to be the upper electrode wiring is to be formed over the surface thereof. According to the present embodiment, the TiN layer of 20 nm thickness, the Al—Cu layer of 200 nm thickness, the Ti layer of 5 nm thickness, and the other TiN layer of 100 nm thickness are to be deposited in order using the spattering method respectively, as the multilayer structure of TiN/Ti/Al—Cu/TiN. Next, the upper electrode wiring 64 is to be formed by etching the material layer 64 to be the upper electrode wiring using the photolithography method with the resist as the mask (not shown) patterned as the line and space (L/S) shape shown as the upper electrode wiring TE in FIG. 2. Moreover, an interlayer insulating layer 69 is to be deposited thereunto, and then the contact (not shown) and the metal wiring (not shown) are to be formed for the upper electrode wiring 64 and the lower electrode wiring 61 respectively, as shown in FIG. 8G.
The third embodiment according to the present invention element and the present invention method (properly referred to as the present embodiment hereinafter) will be described in detail below with reference to FIG. 10 to FIG. 13.
First, a base insulating layer 114 is to be formed on a semiconductor substrate 115 that peripheral circuits and the like (not shown) are properly formed on. According to the present embodiment, after depositing the base insulating layer 114 of borophosphosilicate glass (BPSG) with the thickness of 1500 nm, the surface of the layer is to be flattened by polishing the surface of the BPSG layer 114 using the so-called chemical mechanical polishing (CMP) method to be the thickness of 800 nm on the top surface of the semiconductor substrate 115. Next, a material layer 113 to be the lower electrode wiring is to be deposited thereon. According to the present embodiment, the Ti layer of 5 nm thickness, the TiN layer of 20 nm thickness, the Al—Cu layer of 200 nm thickness, the other Ti layer of 5 nm thickness, and the other TiN layer of 100 nm thickness are to be deposited in order using the spattering method respectively as the multilayer structure of TiN/Ti/Al—Cu/TiN/Ti. Moreover, an SiN layer 116 is to be deposited using the chemical vapor deposition (CVD) method with the thickness of 150 nm on the material layer 113 to be the lower electrode wiring. Next, the lower electrode wiring is to be formed by etching the SiN layer 116 and the material layer 113 to be the lower electrode wiring using the photolithography method with the resist as the mask (not shown) patterned as the line and space (L/S) shape shown as the lower electrode wiring BE in FIG. 2. And then as shown in FIG. 11A, an SiO2 layer 117 is to be deposited using the CVD method with the thickness of 600 nm thereunto.
Next, a TiO2 layer 112 as one example of the material layer for variable resistor body is to be deposited over the surface thereof. According to the present embodiment, the CVD method is used as one example for depositing the TiO2 layer by reacting TiCl4 with oxygen at a substrate temperature of between 350 and 400° C. And then it is able to form the TiO2 layer 112 with the thickness of 25 nm deposited on the SiO2 layer 117 and with the thickness of 20 nm formed along the inner sidewall of the open part 118 for example. Here, the TiO2 layer 112 is formed along the open part 118, so that the inside of the open part 118 may be not to be filled therewith. Moreover, an SiO2 layer 119 is to be deposited using the CVD method with the thickness of 600 nm over the surface thereof, as shown in FIG. 11D.
Next, a material layer 111 to be the upper electrode wiring is to be formed over the surface thereof. According to the present embodiment, the TiN layer of 20 nm thickness, the Al—Cu layer of 200 nm thickness, the Ti layer of 5 nm thickness, and the other TiN layer of 100 mm thickness are to be deposited in order using the spattering method respectively, as the multilayer structure of TiN/Ti/Al—Cu/TiN. Next, the upper electrode wiring 111 is to be formed by etching the material layer 111 to be the upper electrode wiring using the photolithography method with the resist as the mask (not shown) patterned as the line and space (L/S) shape shown as the upper electrode wiring TE in FIG. 2. Moreover, an interlayer insulating layer 120 is to be deposited thereunto, and then the contact (not shown) and the metal wiring (not shown) are to be formed for the upper electrode wiring 111 and the lower electrode wiring 113 respectively, as shown in FIG. 12F.
The fourth embodiment according to the present invention element and the present invention method (properly referred to as the present embodiment hereinafter) will be described in detail below with reference to FIG. 14 to FIG. 17.
First, a base insulating layer 144 is to be formed on a semiconductor substrate 145 that peripheral circuits and the like (not shown) are properly formed on. According to the present embodiment as well as the third embodiment, after depositing the base insulating layer of BPSG 144 with the thickness of 1500 nm, the surface of the layer is to be flattened by polishing the surface of the BPSG layer 144 using the CMP method to be the thickness of 800 nm on the top surface of the semiconductor substrate 145. Next, a material layer 143 to be a lower electrode wiring is to be deposited thereon. According to the present embodiment, the Ti layer of 5 nm thickness, the TiN layer of 20 nm thickness, the Al—Cu layer of 200 nm thickness, the other Ti layer of 5 nm thickness, and the other TiN layer of 100 nm thickness are to be deposited in order using the spattering method respectively, as the multilayer structure of TiN/Ti/Al—Cu/TiN/Ti. Moreover, an SiN layer 146 is to be deposited using the CVD method with the thickness of 150 nm on the material layer 143 to be the lower electrode wiring. Next, the lower electrode wiring is to be formed as shown in FIG. 15A, by etching the SiN layer 146 using the photolithography method with the resist as the mask (not shown) patterned as the line and space (L/S) shape shown as the lower electrode wiring BE in FIG. 2, by removing the resist thereafter, and by etching the material layer 143 to be the lower electrode wiring using the patterned SiN layer 146 as the other mask thereafter.
Next, a material layer 141 to be the upper electrode wiring is to be formed over the surface thereof. According to the present embodiment, the TiN layer of 20 nm thickness, the Al—Cu layer of 200 nm thickness, the Ti layer of 5 nm thickness, and the other TiN layer of 100 nm thickness are to be deposited in order using the spattering method respectively, as the multilayer structure of TiN/Ti/Al—Cu/TiN. Next, the upper electrode wiring 141 is to be formed by etching the material layer 141 to be the upper electrode wiring using the photolithography method with the resist as the mask (not shown) patterned as the line and space (L/S) shape shown as the upper electrode wiring TE in FIG. 2. Moreover, an interlayer insulating layer 148 is to be deposited thereunto, and then the contact (not shown) and the metal wiring (not shown) are to be formed for the upper electrode wiring 141 and the lower electrode wiring 143 respectively, as shown in FIG. 16F.
The fifth embodiment according to the present invention element and the present invention method (properly referred to as the present embodiment hereinafter) will be described in detail below with reference to FIG. 18 and FIG. 19.
The sixth embodiment according to the present invention element and the present invention method (properly referred to as the present embodiment hereinafter) will be described in detail below with reference to FIG. 20 to FIG. 25.
First, a base insulating layer 184 is to be formed on a semiconductor substrate 185 that peripheral circuits and the like (not shown) are properly formed. According to the present embodiment as well as the third embodiment, after depositing the base insulating layer of BPSG 184 with the thickness of 1500 nm, the surface of the layer is flattened by polishing the surface of the BPSG layer 184 using the CMP method to be the thickness of 800 nm on the top surface of the semiconductor substrate 185. Next, a material layer 183 to be a lower electrode wiring is to be deposited thereon. According to the present embodiment, the Ti layer of 5 nm thickness, the TiN layer of 20 nm thickness, the Al—Cu layer of 200 nm thickness, the other Ti layer of 5 nm thickness, and the other TiN layer of 105 nm thickness are to be deposited in order using the spattering method respectively, as the multilayer structure of TiN/Ti/Al—Cu/TiN/Ti. Next, the lower electrode wiring 183 is to be formed as shown in FIG. 21A, by etching the material layer 183 to be the lower electrode wiring using the photolithography method with the resist as the mask (not shown) patterned as the line and space (L/S) shape shown as the lower electrode wiring BE in FIG. 2. Moreover, an SiO2 layer 186 is to be deposited using the CVD method with the thickness of 600 nm over the surface thereof.
Next, a TiO2 layer 182 as one example of the material layer for variable resistor body is to be deposited over the surface thereof, as shown in FIG. 22H. According to the present embodiment, the CVD method is used for depositing the TiO2 layer by reacting TiCl4 with oxygen at the substrate temperature of between 350 and 400° C. According to such the process, the TiO2 layer 182 to be the variable resistor body is implanted into the open part 191 inside formed at the part of the top surface of the lower electrode wiring 183.
Next, a material layer 181 to be the upper electrode wiring is to be formed over the surface thereof. According to the present embodiment, the TiN layer of 20 nm thickness, the Al—Cu layer of 200 nm thickness, the Ti layer of 5 nm thickness, and the other TiN layer of 100 nm thickness are to be deposited in order using the spattering method respectively, as the multilayer structure of TiN/Ti/Al—Cu/TiN. Next, the upper electrode wiring 181 is to be formed by etching the material layer 81 to be the upper electrode wiring using the photolithography method with the resist as the mask (not shown) patterned as the line and Space (L/S) shape shown as the upper electrode wiring TE in FIG. 2. Moreover, an interlayer insulating layer 192 is to be deposited thereunto, and then the contact (not shown) and the metal wiring (not shown) are to be formed for the upper electrode wiring 181 and the lower electrode wiring 183 respectively, as shown in FIG. 23I.
Moreover, according to the above mentioned each of the embodiments regarding the present invention, the upper electrode and the lower electrode are to be the TiN layer, or the layer of multilayer structure comprised of the TiN layer, Ti layer and the Al—Cu layer, however, the present invention is not limited thereto. For example, it is able to select arbitrarily from other transition metals, an alloy of such the transition metal elements, a rare metal of such as Pt, Ir, Ru, Os, Rh, Pd, or the like, a metal element of such as Al or the like, or other sort of alloys.
The variable resistive element and it's manufacturing method according to the present invention are applicable to a nonvolatile semiconductor memory device.
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