Source: http://www.google.com/patents/US20030046473?ie=ISO-8859-1
Timestamp: 2014-07-10 23:11:31
Document Index: 75900136

Matched Legal Cases: ['art 500', 'art 600', 'art 600', 'art 500', 'art 500', 'art 600', 'art 500']

Patent US20030046473 - Method and interface for improved efficiency in performing bus-to-bus read ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA novel method and interface is provided for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a split-transaction bus. Embodiments of the present invention permit the initiator device to �post� a read request for a specified amount of data...http://www.google.com/patents/US20030046473?utm_source=gb-gplus-sharePatent US20030046473 - Method and interface for improved efficiency in performing bus-to-bus read data transfersAdvanced Patent SearchPublication numberUS20030046473 A1Publication typeApplicationApplication numberUS 09/939,800Publication dateMar 6, 2003Filing dateAug 28, 2001Priority dateAug 28, 2001Also published asEP1288785A2, EP1288785A3, EP1288785B1, US6766386, US20040221075Publication number09939800, 939800, US 2003/0046473 A1, US 2003/046473 A1, US 20030046473 A1, US 20030046473A1, US 2003046473 A1, US 2003046473A1, US-A1-20030046473, US-A1-2003046473, US2003/0046473A1, US2003/046473A1, US20030046473 A1, US20030046473A1, US2003046473 A1, US2003046473A1InventorsWilliam Dobson, Joel DanzigOriginal AssigneeDobson William Gordon Keith, Joel DanzigExport CitationBiBTeX, EndNote, RefManReferenced by (9), Classifications (6), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod and interface for improved efficiency in performing bus-to-bus read data transfersUS 20030046473 A1Abstract A novel method and interface is provided for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a split-transaction bus. Embodiments of the present invention permit the initiator device to �post� a read request for a specified amount of data from a specified address on the split-transaction bus to an interface that resides between the single-transaction bus and the split-transaction bus. The requested read data is then retrieved over the split-transaction bus and presented in a high-speed memory within the interface for direct access by the initiator device over the single-transaction bus. Latency is avoided because the initiator device is not required to wait for the emergence of the requested read data from the split-transaction bus but, instead, may continue to perform other activities on the single-transaction bus and then obtain the requested read data at a later time. Images(9) Claims(30)
[0054] In response to the writing of the command register 408, the read request generation logic 410 generates a read request for issuance on the split-transaction bus 308 as shown at step 512. In embodiments, the read request includes the previously-written address information from the address register 406, as well as a source identifier (ID) generated by the read request generation logic 410 that uniquely identifies the read request. The read request may also include other information derived from the command information in the command register 408, such as routing information, the amount of data to retrieve (e.g., a number of words of data to retrieve), and the like. At step 514, the read request is issued to the target device 306 on the split-transaction bus 308 via the split-transaction bus interface 404. [0055] At step 516, a read response is received by the posted read interface 310 over the split-transaction bus 308 and is transferred to the read response routing logic 412. At step 518, the read response routing logic 412 receives the read response and determines if it corresponds to the read request issued in step 514. In embodiments, the read response routing logic 412 makes this determination by checking to see if the read response includes the same source ID as that included in the read request issued in step 514. If the read response does not correspond to the read request issued in step 514, then the read response is treated as a response to a regular read transaction on the single-transaction bus 304 (as opposed to a posted read) and is routed directly to the single-transaction bus interface 402, as shown in step 520. [0056] If the read response corresponds to the read request issued in step 514, then the read data associated with the read response is stored in the read data memory 416 as shown in step 522. In embodiments, the read data is comprised of a series of words. In order to store the read data in the read data memory 416, the read data is received by the FIFO write control 414, which operates to generate values that identify storage addresses in the read data memory 416 and to store the read data at the identified addresses. In embodiments, as each word of the read data is received by the FIFO write control 414, the FIFO write control 414 generates an incrementing value that identifies an address within the read data memory 416 and stores the word to the identified address in a first-in-first-out fashion. [0057] As indicated at step 524, the FIFO write control 414 also writes status information to the status register 418 that indicates that the read data has been stored in the read data memory 416 and is, therefore, directly available to devices on the single-transaction bus 304. This status information may comprise a single �posted read done� bit, which, when set, indicates that the requested read data is available in the read data memory 416. In embodiments, the FIFO write control 414 writes the status information to the status register 418 concurrently with the storing of the read data in the read data memory 416. In alternate embodiments, the FIFO write control 414 writes the status information to the status register 418 after it has stored the read data in the read data memory 416. [0058] In accordance with embodiments of the present invention, while the posted read interface 310 retrieves and stores the requested read data as described in reference to steps 512, 514, 516, 518, 520, 522 and 524, above, the initiator device 302 is free to initiate other transactions on the single-transaction bus 304. This is because the initiator device 302 initiates the read data transfer by performing single-transaction writes to the address register 406 and the command register 408. Because writes are performed, the initiator device 302 is not occupied for the entire time it takes to extract the read data from the split-transaction bus, as it would be in the case of a conventional single-transaction read. Instead, the initiator device 302 is free to retrieve the requested read data from the read data memory 416 at some later point in time. [0059] In the method depicted by flowchart 500, the initiator 302 polls the status register to determine if the read data is available at some point in time after writing to the command register 408, as shown at step 506. In embodiments, the polling may occur periodically at a predefined interval or, alternately, during periods when the initiator device 302 has sufficient available bandwidth. The polling may occur concurrently with any of steps 512, 514, 516, 518, 520, 522 and 524 as described above. As shown in step 508, if the read data is not available, then the polling process continues. However, if the read data is available, the initiator device 302 reads the read data directly from the read data memory 416, as shown at step 510, and the read data transfer is completed. [0060] As discussed above, in embodiments, the read data memory 416 comprises a RAM that stores a specified number of individually-addressable words of read data that are directly accessible by the initiator device 302. In accordance with such embodiments, the initiator device 302 can access the words stored in the read data memory 416 in any order, read selected words, and skip undesired words. This presents a distinct advantage over, for example, a FIFO, in which each preceding word of data must be read in order to access a desired word of data. [0061]FIG. 6 depicts a flowchart 600 of an alternate method for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a split-transaction bus in accordance with embodiments of the present invention. The method depicted in flowchart 600 is identical to that described in reference to the flowchart 500, above, except that an interrupt technique, as opposed to a polling technique, is used to alert the initiator device 302 to the presence of the requested read data in the read data memory 416. [0062] In particular, after the requested read data has been stored in the read data memory 416, the FIFO write control 414 issues an interrupt signal to the initiator device 302 via the interrupt line 420 and the single-transaction bus interface 402, as shown at step 602. Upon receiving the interrupt signal at step 604, the initiator device 302 performs a direct read to the read data memory 416 to obtain the requested read data, thus completing the read transfer as shown in step 606. [0063] While two techniques have been described herein for alerting the initiator device 302 to the presence of requested read data in the read data memory 416, it is expected that in most applications the polling technique described in reference to flowchart 500 will operate more efficiently than the interrupt technique described in reference to flowchart 600. This expectation is based on the fact that, in most systems, interrupts cause a context switch that entails register swapping and other data transfers that may substantially degrade overall system bandwidth. [0064]FIG. 7 illustrates the latency reduction that results from conducting a read data transfer in accordance with embodiments of the present invention. In particular, FIG. 7 shows the bus activity on the single-transaction bus 304 and the split-transaction bus 308 during a read data transfer in accordance with the method described above in reference to flowchart 500. As shown in block 702, the read data transfer is initiated when the initiator device 302 writes a read command to the command register 408 over the single-transaction bus 304. As shown in block 708, the writing of the command register causes the read request generation logic 410 to issue a read request on the split-transaction bus 308. Subsequently, a read response is received by the posted read interface 310 over the split-transaction bus 308, as depicted in block 710. Finally, at some later time, the initiator device 302 polls the status register 418 to determine if the requested read data is available, and, since the data is available, the initiator device 302 obtains the read data from the read data memory 416, as shown in blocks 704 and 706. [0065] As shown by FIG. 7, the total latency on the single-transaction bus 304 is equal only to the time required for the initiator device to write to the command register 408, to poll the status register 418, and to retrieve the requested data from the local memory 416 when it becomes available. Note that this latency is substantially less than that involved in conventional read transfers between a split-transaction and single-transaction bus, as described in reference to FIG. 2, above. This is due, in part, to the fact that no disconnects and retries are induced on the single-transaction bus 304. As a result, the initiator device 302 is free to handle other tasks in the system during the interval between the issuance of the read request and the scheduled polling of the status register 418. [0066] E. Conclusion [0067] While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Alternate implementations are within the spirit and scope of the present invention. For example, FIG. 8 depicts an alternate embodiment of the posted read interface 310 of FIG. 4, denoted 310′, that concurrently accommodates four posted reads rather than one This is achieved by utilizing four times the number of address registers, command registers, status registers, FIFO write controls, and read data memories as utilized in the posted read interface embodiment described above in reference to FIG. 4. [0068] In particular, the posted read interface 310′ depicted in FIG. 8 includes four address registers 406 a, 406 b, 406 c, and 406 d and four corresponding command registers 418 a, 418 b, 418 c, and 418 d. Each address and command register pair supports a single posted read. The read request generation logic 410′ generates and issues a separate read request in response to the population of each of the four command registers. The read request generation logic 410′ also assigns a unique source ID to each of the four read requests so that responses to the requests may be properly routed by the read response routing logic 412′. [0069] Upon receiving responses to the read requests, the read response routing logic 412′ routes each response to one of four FIFO write controls 414 a, 414 b, 414 c, 414 d for storage to a corresponding one of four read data memories 416 a, 416 b, 416 c, and 416 d. Additionally, each FIFO write control writes to a corresponding one of four status registers 408 a, 408 b, 408 c, 408 d to indicate that requested data is available. Alternately, each FIFO may generate one of four interrupt signals 420 a, 420 b, 420 c, and 420 d to interrupt an initiator device to indicate that requested data is available. [0070] As demonstrated by the above example, various changes in form and details may be made to the above-described embodiments without departing from the spirit and scope of the present invention as defined in the appended claims. Accordingly, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6731292 *Mar 6, 2002May 4, 2004Sun Microsystems, Inc.System and method for controlling a number of outstanding data transactions within an integrated circuitUS6766405 *Mar 28, 2002Jul 20, 2004International Business Machines CorporationAccelerated error detection in a bus bridge circuitUS6807593 *Nov 1, 2001Oct 19, 2004Lsi Logic CorporationEnhanced bus architecture for posted read operation between masters and slavesUS6892259 *Sep 29, 2001May 10, 2005Hewlett-Packard Development Company, L.P.Method and apparatus for allocating computer bus device resources to a priority requester and retrying requests from non-priority requestersUS6931473 *Jul 16, 2002Aug 16, 2005International Business Machines CorporationData transfer via Host/PCI-X bridgesUS7124230 *Apr 30, 2002Oct 17, 2006Intel CorporationUse of bus transaction identification codesUS7549004 *Aug 20, 2004Jun 16, 2009Altera CorporationSplit filtering in multilayer systemsUS20110119679 *Dec 23, 2009May 19, 2011Muppirala Kishore KumarMethod and system of an i/o stack for controlling flows of workload specific i/o requestsUS20120047306 *Jun 13, 2011Feb 23, 2012Sony CorporationBus system and bridge circuit connecting bus system and connection apparatus* Cited by examinerClassifications U.S. Classification710/306International ClassificationG06F13/36, G06F13/40, G06F3/00Cooperative ClassificationG06F13/4004European ClassificationG06F13/40DLegal EventsDateCodeEventDescriptionDec 27, 2011FPAYFee paymentYear of fee payment: 8Jan 18, 2008FPAYFee paymentYear of fee payment: 4Feb 22, 2005CCCertificate of correctionNov 28, 2001ASAssignmentOwner name: BROADCOM CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DOBSON, WILLIAM GORDON KEITH;DANZIG, JOEL;REEL/FRAME:012325/0068Effective date: 20011107Owner name: BROADCOM CORPORATION 16215 ALTON PARKWAYIRVINE, CAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DOBSON, WILLIAM GORDON KEITH /AR;REEL/FRAME:012325/0068RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google