Source: https://patents.google.com/patent/US9769274
Timestamp: 2018-02-25 04:03:48
Document Index: 697409019

Matched Legal Cases: ['§371', 'Application No. 9910280', 'Application No. 9910280', 'Application No. 00', 'Application No. 00', 'Application No. 00']

US9769274B2 - Data transfer, synchronising applications, and low latency networks - Google Patents
US9769274B2
US9769274B2 US14492800 US201414492800A US9769274B2 US 9769274 B2 US9769274 B2 US 9769274B2 US 14492800 US14492800 US 14492800 US 201414492800 A US201414492800 A US 201414492800A US 9769274 B2 US9769274 B2 US 9769274B2
US14492800
US20150081925A1 (en )
Data transfer, synchronizing applications, and low latency networks are disclosed. An example method includes maintaining a first buffer in a first computing device, the first buffer to receive discrete units of data from a second computing device; maintaining a second buffer in the first computing device, the second buffer to store size data identifying a size of respective ones of the discrete units of data received from the second computing device; and reading from the first buffer according to a first value of a first pointer and a corresponding one of the sizes stored in the second buffer.
This patent arises from a continuation of U.S. patent application Ser. No. 13/802,400, filed Mar. 13, 2013, now U.S. Pat. No. 8,842,655, which is a continuation of U.S. patent application Ser. No. 12/105,412, filed Apr. 18, 2008, now U.S. Pat. No. 8,423,675, which is a divisional of U.S. patent application Ser. No. 11/198,043, filed on Aug. 5, 2005, which is a divisional of U.S. patent application Ser. No. 09/980,539, which is a §371 of International Application No. PCT/GB00/01691, filed May 3, 2000, which claims the benefit of United Kingdom Patent Application No. 9910280.8, filed on May 4, 1999. U.S. patent application Ser. No. 13/802,400, U.S. patent application Ser. No. 12/105,412, U.S. patent application Ser. No. 11/198,043, U.S. patent application Ser. No. 09/980,539, International Application No. PCT/GB00/01691, and United Kingdom Patent Application No. 9910280.8 are hereby incorporated herein by reference in their entireties and priority to each of these cases is claimed.
FIG. 8b shows how the protocol of FIG. 8a is transcribed onto the G-LINK physical layer. The first word in any packet contains an 18-bit network address. Each word of 63 is split into two words in 64; the lower 16 bits carry high and low addresses or data, corresponding to the address/data bus; the next 4 bits carry either byte enables or parity data. During the address phase, the byte enable field (only 2 bits of which are available, owing to the limitations of G-LINK) is used to carry a 2-bit code indicating read, write or escape packet use. Escape packets are normally used to carry diagnostic or error information between nodes, or as a means of carrying the Xon/Xoff-style protocol when no other data is in transit. The G-LINK nCAV signal corresponds to the ADS signal of 63; nDAV is active throughout the rest of the burst and the combination of nDAV inactive and nCAV inactive signals the end of a burst, or nCAV active indicates the immediate beginning of another burst.
FIG. 8c , shows a read data burst 65; this is the same as a write burst 64, except data bit 16 is set to 0. On the outbound request, the data field contains the network address for the read data to be returned to. When the data for a read returns 66, it travels like a write burst, but is signified by there only being one nCAV active (signifying the network address) along with the first word. An additional bit, denoted FLAG in FIG. 8, is used to carry Xon/Xoff style information when a burst is in progress. It is not necessary therefore to break up a burst in order to send an Escape packet containing the Xon/Xoff information. The FLAG bit also serves as an additional end of packet indicator.
In FIG. 8c , 67,68 shows an escape packet; after the network address, this travels with 68 or without 67 a payload as defined by data bit 16 in the first word of the burst.
This method can be extended to provide support for 120 and the forthcoming Next Generation 110 (NGIO) standard. Here, the transmit, receive and completion queues are located on the NIC rather than in the physical memory of the computer, as is currently the case for the VIA standard.
storing in a first buffer of a first computing device discrete units of data received from a second computing device;
storing in a second buffer of the first computing device size data identifying sizes of respective ones of the discrete units of data received from the second computing device, the first computing device and the second computing device operating on different parts of the first buffer simultaneously;
storing on the first computing device, a read pointer representing a start position of a first one of the discrete units of data available for reading in the first buffer;
storing on the second computing device a copy of the read pointer;
reading the first discrete unit from the first buffer based on a value of the read pointer and a corresponding one of the sizes stored in the second buffer;
updating the value of the read pointer on the first computing device; and
updating the value of the copy of the read pointer on the second computing device.
2. The method as defined in claim 1, wherein the updating of the value of the copy of the read pointer includes the first computing device communicating with the second computing device via a network.
3. The method as defined in claim 1, wherein the updating of the value of the copy of the read pointer includes the first computing device conveying a last-read section of the first buffer to the second computing device.
4. The method as defined in claim 1, further including a write pointer stored on the second computing device and a copy of the write pointer stored on the first computing device, a value of the write pointer and a value of the copy of the write pointer updated by the second computing device after the first buffer receives the discrete units of data.
5. The method as defined in claim 1, further including configuring the first and second buffers as circular buffers.
a first buffer to received discrete units of data from a second computing device;
a second buffer to store size data identifying sizes of respective ones of the discrete units of data received from the second computing device;
a read pointer, the read pointer representing a starting position of a first one of the discrete units available for reading from the first buffer;
reading the first discrete unit from the first buffer based on the read pointer and a corresponding one of the sizes identified by the size data stored in the second buffer, the second computing device able to operate on different locations within the first buffer while the first discrete unit is being read from the first buffer; and
updating the read pointer and a copy of the read pointer on the second computing device.
7. The first computing device as defined in claim 6, wherein the updating of the copy of the read pointer includes communicating with the second computing device via a network.
8. The first computing device as defined in claim 6, wherein the updating of the copy of the read pointer includes conveying a last-read section of the first buffer to the second computing device.
9. The first computing device as defined in claim 6, further including a write pointer stored on the second computing device and a copy of the write pointer stored on the first computing device, the write pointer and the copy of the write pointer to be updated by the second computing device after the first buffer receives the discrete units of data.
10. The first computing device as defined in claim 6, further including configuring the first and second buffers as circular buffers.
11. A tangible machine readable storage device including instructions that, when executed, cause a first computing device to perform operations comprising:
storing discrete units of data from a second computing device in a first buffer;
storing metadata identifying sizes of respective ones of the discrete units of data received from the second computing device in a second buffer;
storing a read pointer representing a starting position from which to begin reading from in the first buffer;
storing a copy of the read pointer on the second computing device;
reading data from the first buffer to based on the read pointer stored on the first computing device and a corresponding one of the sizes stored in the second buffer, the second computing device able to operate on different locations within the first buffer while the data is being read from the first buffer; and
updating the read pointer on the first computing device and the copy of the read pointer on the second computing device.
12. The storage device as defined in claim 11, wherein the updating of the copy of the read pointer includes communicating with the second computing device via a network.
13. The storage device as defined in claim 11, wherein the updating of the copy of the read pointer includes conveying a last-read section of the first buffer from the first computing device to the second computing device.
14. The storage device as defined in claim 11, further including a write pointer stored on the second computing device and a copy of the write pointer stored on the first computing device, and further including updating the write pointer and the copy of the write pointer after the first buffer receives the discrete units of data.
US14492800 1999-05-04 2014-09-22 Data transfer, synchronising applications, and low latency networks Active 2021-01-07 US9769274B2 (en)
US11198043 US20060034275A1 (en) 2000-05-03 2005-08-05 Data transfer, synchronising applications, and low latency networks
US12105412 US8423675B2 (en) 1999-05-04 2008-04-18 Data transfer, synchronising applications, and low latency networks
US13802400 US8843655B2 (en) 1999-05-04 2013-03-13 Data transfer, synchronising applications, and low latency networks
US14492800 US9769274B2 (en) 1999-05-04 2014-09-22 Data transfer, synchronising applications, and low latency networks
US13802400 Continuation US8843655B2 (en) 1999-05-04 2013-03-13 Data transfer, synchronising applications, and low latency networks
US20150081925A1 true US20150081925A1 (en) 2015-03-19
US9769274B2 true US9769274B2 (en) 2017-09-19
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