Source: http://www.google.com/patents/US7523617?dq=5,832,511
Timestamp: 2014-07-25 11:32:14
Document Index: 595534116

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US7523617 - Thin film thermoelectric devices for hot-spot thermal management in ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA structure, system and method for controlling a temperature of a heat generating device in a solid medium, wherein heat is extracted from the medium into at least one heat extraction device, the heat extraction device dissipates heat into an environment apart from the medium by a heat sink thermally...http://www.google.com/patents/US7523617?utm_source=gb-gplus-sharePatent US7523617 - Thin film thermoelectric devices for hot-spot thermal management in microprocessors and other electronicsAdvanced Patent SearchPublication numberUS7523617 B2Publication typeGrantApplication numberUS 10/970,378Publication dateApr 28, 2009Filing dateOct 22, 2004Priority dateOct 22, 2004Fee statusPaidAlso published asUS7997087, US20060086118, US20090282852, WO2007015701A2, WO2007015701A3Publication number10970378, 970378, US 7523617 B2, US 7523617B2, US-B2-7523617, US7523617 B2, US7523617B2InventorsRama Venkatasubramanian, Randall G. Alley, Pratima Addepalli, Anil J. Reddy, Edward P. Siivola, Brooks C. O'Quinn, Kip D. Coonley, John Posthill, Thomas ColpittsOriginal AssigneeNextreme Thermal Solutions, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (87), Referenced by (4), Classifications (14), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetThin film thermoelectric devices for hot-spot thermal management in microprocessors and other electronicsUS 7523617 B2Abstract A structure, system and method for controlling a temperature of a heat generating device in a solid medium, wherein heat is extracted from the medium into at least one heat extraction device, the heat extraction device dissipates heat into an environment apart from the medium by a heat sink thermally coupled to the heat extraction device; and heat from the medium is dissipated into the heat sink by a first thermal interface material thermally coupling the heat sink to the medium.
1. A structure for controlling a temperature of a heat generating device in a solid medium, comprising:
at least one heat extraction device configured to be thermally coupled to the medium;
a heat sink thermally coupled to the heat extraction device and configured to dissipate heat from the heat extraction device into an environment apart from the medium; and
a first thermal interface material configured to thermally couple the heat sink to the solid medium wherein the thermal interface material is between the heat sink and the solid medium and wherein the thermal interface material and the heat extraction device are thermally coupled in parallel between the heat sink and the solid medium;
wherein a first thermal conductance K1 including a thermal conductance of the first thermal interface material for a region extending no more than a width of the heat extraction device from a side of the heat extraction device is less than a second thermal conductance K2 between a base of the heat extraction device against the heat sink and the heat sink.
2. The structure of claim 1, wherein the first thermal conductance and the second thermal conductance define a ratio (K1/K2) that ranges from 0.001 to 0.5.
3. The structure of claim 1, wherein said first thermal conductance further comprises a conductance coupled between the heat generating device and the first thermal interface material.
4. The structure of claim 3, wherein the first thermal conductance and the second thermal conductance define a ratio (K1/K2) that ranges from 0.001 to 0.5.
5. The structure of claim 4, wherein the first thermal conductance is lower than a third thermal conductance K3 between the heat sink and a region apart from the at least one heat-generating device, said third thermal conductance K3 including a thermal conductance of the first thermal interface material for a region extending farther than a width of the heat extraction device from the side of the heat extraction device.
6. The structure of claim 1, wherein the first thermal interface material comprises:
an insulating film formed on a side of the medium adjacent the heat extraction device; and
at least one of a thermal grease, a conductive compound, a conductive elastomer, and a conductive adhesive tape.
a second thermal interface material configured to be disposed between the heat extraction device and the medium.
8. The structure of claim 7, wherein the second thermal interface material comprises a material having a thermal conductance higher than the first thermal interface material.
9. The structure of claim 7, wherein the second thermal interface material comprises:
at least one metallic structure extending in a direction between the heat extraction device and the medium.
10. The structure of claim 7, wherein the first thermal interface material and the second thermal interface material comprises the same material.
a recess in said medium in which the heat extraction device is disposed.
12. The structure of claim 11, wherein the recess has an aspect ratio of depth to width that ranges from 0.0025 to 2 cm−1.
13. The structure of claim 11, wherein the recess has a depth equal to or greater than a height of the heat extraction device.
14. The structure of claim 1, wherein the heat extraction device comprises at least one of a thermoelectric device, a thermionic device, and a thermo-tunneling device.
15. The structure of claim 1, wherein the heat extraction device comprises a thin film thermoelectric device.
16. The structure of claim 1, wherein the heat extraction device comprises:
a thermoelectric device including a material having a figure of merit of at least 1.
17. The structure of claim 1, wherein the heat extraction device comprises:
a thermoelectric device including a material having a figure of merit of at least 2.
18. The structure of claim 1, wherein the heat extraction device comprises:
a thermoelectric device including at least one of a superlattice and a quantum dot superlattice.
19. The structure of claim 18, wherein the superlattice comprises:
at least one of a Bi2Te3/Sb2Te3 superlattice, a SiGe superlattice, and a PbTe/PbSe superlattice.
a support plate configured to support the heat extraction device and thermally coupled to the heat sink.
21. The structure of claim 20, wherein the support plate comprises a plate having slits extending partially through the plate.
22. The structure of claim 20, wherein the support plate comprises:
a recess in which the heat extraction device is disposed.
23. The structure of claim 22, wherein the recess has an aspect ratio of depth to width that ranges from 0.0025 to 2 cm−1.
24. The structure of claim 22, wherein the recess has tapered side walls forming an enlarged opening on a side of the recess toward the medium.
25. The structure of claim 22, wherein the recess has a depth equal to or greater than a height of the heat extraction device.
26. The structure of claim 1, further comprising:
a second thermal interface material disposed between the heat extraction device and the heat sink.
27. The structure of claim 26, wherein the second thermal impedance material comprises:
at least one metallic structure extending in a direction between the heat extraction device and the heat sink.
28. The structure of claim 1, further comprising:
electrical connections to said heat extraction device, having a resistance less than 1/10th of an Ohmic resistance of the thermoelectric pair.
29. The structure of claim 28, wherein the electrical connections comprise metal connections.
30. The structure of claim 29, wherein the metal connections comprise Cr/Au/Ni/Au contacts to said thermoelectric pair.
31. The structure of claim 1, wherein the heat sink comprises:
an electrically conducting member and an electrical insulation formed on the electrically conducting member; and
a conductor formed on the electrical insulation and connecting to said heat extraction device.
32. The structure of claim 31, wherein the electrically conducting member comprises at least one of Al, Cu, doped Si, and doped SiC.
33. The structure of claim 1, wherein the heat sink comprises:
an electrically insulating plate; and
a thermal conductor provided on the electrically insulating plate and connecting to said heat extraction device.
34. The device of claim 33, wherein the electrically insulating plate comprises at least one of AlN, SiC, Si, and diamond.
35. The structure of claim 34, wherein the electrically insulating plate comprises AlN and the conductive layer comprises at least one of Al and Cu.
36. The structure of claim 1, wherein the heat sink comprises:
37. The structure of claim 36, wherein the recess has an aspect ratio of depth to width that ranges from 0.0025 to 2 cm−1.
38. The structure of claim 36, wherein the recess has a depth equal to or greater than a height of the heat extraction device.
39. The structure of claim 1, further comprising:
a header connected to the heat extraction device; and
a radiative coupler configured to couple heat from the header to the heat sink.
40. The structure of claim 39, wherein the radiative coupler comprises a Purcell-enhancement cavity transmitter/receiver structure.
41. The structure of claim 40, wherein the Purcell-enhancement cavity transmitter/receiver structure comprises:
a thermally conductive layer having dispersed therein at least one of metal, semimetal, and semiconductor particles.
42. The structure of claim 41, wherein the Purcell-enhancement cavity transmitter/receiver structure comprises:
at least one of Φm-size and sub-micron-size radiation fins.
43. The structure of claim 1, further comprising:
an intermediate heat sink disposed between the heat extraction device and the heat sink, said intermediate heat sink having a surface area larger than a surface area of the heat generating device and having a thermal conductivity of at least 1 W/cm-K.
44. The structure of claim 43, wherein the intermediate heat sink comprises a silicon member.
45. The structure of claim 43, wherein the intermediate heat sink comprises:
46. The structure of claim 45, wherein the recess has an aspect ratio of depth to width that ranges from 0.0025 to 2 cm−1.
47. The structure of claim 45, wherein the recess has a depth equal to or greater than a height of the heat extraction device.
48. The structure of claim 1, further comprising:
said medium and said heat generating device;
said medium comprising a first material in which the heat generating device is disposed and a second material separate from the first material; and
said second material having a recess therein by which the heat extracting device is disposed in contact with the first material.
49. The structure of claim 48, wherein the first material comprises a semiconductor, and the second material comprises an electrically insulating material.
50. The structure of claim 1, further comprising:
a processor configured to operate plural heat extraction devices in at least one of a cooling mode, a heat pump mode, and a power conversion mode to equilibrate temperatures across the solid medium.
51. The structure of claim 50, further comprising:
a plurality of temperature sensors thermally connected to at least one of the medium and the heat extraction devices.
52. The structure of claim 51, wherein the processor comprises:
inputs configured to receive temperature measurements from the plurality of temperature sensors and at least one of operating voltages, currents, and temperatures in the heat extraction devices.
53. The structure of claim 52, wherein the processor comprises:
a mapping unit configured to map a thermal profile of the plural heat generating devices from the temperature measurements.
54. The structure of claim 52, wherein the processor comprises:
a mapping unit configured to produce from the temperature measurements of a semiconductor chip and the at least one of operating voltages, currents, and temperatures a power dissipation map for integrated circuits on the semiconductor chip.
55. The structure of claim 50, wherein the processor comprises a neural network processor.
56. The structure of claim 1, wherein the heat extraction device comprises:
a power converter configured to convert waste heat from the integrated circuits into power.
57. The structure of claim 1, wherein the heat extraction device comprises:
a thermoelectric pair having a thermal conduction channel area smaller than an area of a header connecting the thermoelectric pair such that the thermal conduction channel area is a packing fraction of the area of said header, and said packing fraction is less than 50%.
58. The structure of claim 57, wherein said packing fraction is less than 20%.
59. The structure of claim 57, wherein said packing fraction is less than 10%.
60. The structure of claim 57, wherein said packing fraction is less than 1%.
61. The structure of claim 57, wherein said packing fraction is less than 0.5%.
62. The structure of claim 1 wherein the thermal interface material is between the heat sink and the solid medium in a direction perpendicular with respect to a surface of the solid medium.
63. A structure for controlling a temperature of a heat generating device in a solid medium, comprising:
a heat sink thermally coupled to the heat extraction device and configured to dissipate heat from the heat extraction device into an environment apart from the medium;
a first thermal interface material configured to thermally couple the heat sink to the medium; and
wherein the heat extraction device comprises a thermoelectric pair having a thermal conduction channel area smaller than an area of a header connecting the thermoelectric pair such that the thermal conduction channel area is a packing fraction of the area of said header, and said packing fraction is less than 50%.
64. The structure of claim 63, wherein said packing fraction is less than 20%.
65. The structure of claim 63, wherein said packing fraction is less than 10%.
66. The structure of claim 63, wherein said packing fraction is less than 1%.
67. The structure of claim 63, wherein said packing fraction is less than 0.5%.
a solid medium;
a heat generating device in the solid medium;
wherein a first thermal conductance K1 between the heat sink and the heat generating device, including a thermal conductance through the first thermal interface material for a region extending no more than a width of the heat extraction device from a side of the heat extraction device, is less than a second thermal conductance K2 between a base of the heat extraction device against the heat sink and the heat sink.
69. The system of claim 68, wherein the first thermal conductance and the second thermal conductance define a ratio (K1/K2) that ranges from 0.001 to 0.5.
70. The system of claim 69, wherein the first thermal conductance is lower than a third thermal conductance K3 between the heat sink and a region apart from the heat-generating device on a surface of the medium opposite the heat extraction device, said third thermal conductance K3 including a thermal conductance of the first thermal interface material for a region extending farther than a width of the heat extraction device from the side of the heat extraction device.
71. The system of claim 68, wherein the heat extraction device comprises:
72. The system of claim 68 wherein the thermal interface material is between the heat sink and the solid medium in a direction perpendicular with respect to a surface of the solid medium.
a heat sink thermally coupled to the heat extraction device and configured to dissipate heat from the heat extraction device into an environment apart from the solid medium; and
at least one of said solid medium and said heat sink include thermal conductance structures that define a first thermal conductance K1 between the heat sink and the heat generating device, including a thermal conductance through a first thermal interface material between the heat generating device and the heat sink for a region extending no more than a width of the heat extraction device from a side of the heat extraction device, which is less than a second thermal conductance K2 between a base of the heat extraction device against the heat sink and the heat sink.
74. The system of claim 73, wherein one of the thermal conductance structures defining K1 comprises:
at least one of a thermal grease, a conductive compound, a conductive elastomer, and a conductive adhesive tape in contact with the insulating film.
75. The system of claim 73, wherein one of the thermal conductance structures defining K2 comprises:
at least one metallic structure extending in a direction and disposed between the heat extraction device and the medium.
76. The system of claim 73, wherein one of the thermal conductance structures defining K2 comprises:
at least one metallic structure extending in a direction and disposed between the heat extraction device and the heat sink.
77. The system of claim 73, wherein the thermal conductance structures have a third thermal conductance K3 between the heat sink and a region apart from the at least one heat-generating device that is higher than the first thermal conductance, said third thermal conductance K3 including a thermal conductance of the first thermal interface material for a region extending farther than a width of the heat extraction device from the side of the heat extraction device.
78. The system of claim 77, wherein one of the thermal conductance structures for K3 comprises:
at least of said medium and said heat sink having a recess in which the heat extraction device is disposed.
79. The system of claim 78, wherein the recess has an aspect ratio of depth to width that ranges from 0.0025 to 2 cm−1.
80. The system of claim 78, wherein the recess has tapered side walls forming an enlarged opening on a side of the recess toward the medium.
81. The system of claim 78, wherein the recess has a depth equal to or greater than a height of the heat extraction device.
82. The system of claim 73, wherein the heat extraction device comprises:
83. The system of claim 73 wherein the thermal interface material is between the heat sink and the solid medium in a direction perpendicular with respect to a surface of the solid medium.
84. A system for controlling a temperature of a heat generating device in a solid medium, comprising:
a heat extraction device configured to be thermally coupled to the medium;
a first heat sink themmily coupled to the heat extraction device and configured to dissipate heat from the heat extraction device into an environment apart from the medium; and
a thermal conductance structure configured in parallel to the heat extraction device to thermally conduct heat from the medium wherein the thermal conductance structure comprises a thermal impedance disposed between a base of the heat extraction device and the medium so as to impede heat flow from the base back into the medium,
wherein the thermal impedance has a first thermal conductance K1 including a thermal conductance of the first thermal interface material for a region extending no more than a width of the heat extraction device from a side of the heat extraction device is less than a second thermal conductance K2 between a base of the heat extraction device against the first heat sink and the first heat sink.
85. The system of claim 84, wherein the first thermal conductance is lower than a third thermal conductance K3 between the first heat sink and a region apart from the at least one heat-generating device, said third thermal conductance K3 including a thermal conductance of the first thermal interface material for a region extending farther than a width of the heat extraction device from the side of the heat extraction device.
86. The system of claim 84, wherein the heat extraction device comprises at least one of a thermoelectric device, a thermionic device, and a thermo-tunneling device.
87. The system of claim 84, wherein the heat extraction device comprises a thin film thermoelectric device.
88. The system of claim 84, wherein the heat extraction device comprises:
89. The system of claim 84, wherein the heat extraction device comprises:
90. The system of claim 84, wherein the heat extraction device comprises:
91. The system of claim 90, wherein the superlattice comprises:
92. The system of claim 84, wherein the first heat sink comprises a heat pipe conducting heat from a first side of the medium containing the heat generating device.
93. The system of claim 92, wherein said thermal conductance structure comprises a second heat sink thermally coupled to a second side of the medium opposite the heat extraction device.
94. A system for controlling a temperature of a heat generating device in a solid medium, comprising:
a first heat sink thermally coupled to the heat extraction device and configured to dissipate heat from the heat extraction device into an environment apart from the medium; and
a thermal conductance structure configured in parallel to the heat extraction device to thermally conduct heat from the medium;
95. The system of claim 94, wherein said packing fraction is less than 20%.
96. The system of claim 94, wherein said packing fraction is less than 10%.
97. The system of claim 94, wherein said packing fraction is less than 1%.
98. The system of claim 94, wherein said packing fraction is less than 0.5%. Description
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH The U.S. Government, by the following contracts, may have a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms, as provided for by the terms in High-Performance Thin-film Thermoelectric Devices for Cooling and Power Generation, DARPA/ONR Contract No. N00014-97-C-0211, Thin-film Thermoelectric Palm Power Technologies, DARPA/ARO Contract No. DAAD19-01-C-0070, and Meta-Material Structures for Super-Radiant Structures, DARPA/AFOSR Contract No. F49620-01-C-0038.
CROSS-REFERENCE TO RELATED DOCUMENTS This application is related to U.S. Provisional Application No. 60/372,139 entitled �Thermoelectric device technology utilizing double-sided Peltier junctions� filed on Apr. 15, 2002, the entire contents of which is incorporated herein by reference. This application is related to U.S. Pat. No. 6,300,150 entitled �Thin-film thermoelectric device and fabrication method of same� issued Oct. 9, 2001, the entire contents of which is incorporated herein by reference. This application is related to U.S. Pat. No. 6,071,351 entitled �Low temperature chemical vapor depositor and etching apparatus and method� issued Jun. 6, 2002, the entire contents of which is incorporated herein by reference. This application is related to U.S. Pat. No. 6,505,468 entitled �Cascade cryogenic thermoelectric cooler for cryogenic and room temperature applications� issued Jan. 14, 2003, the entire contents of which is incorporated herein by reference. This application is also related to U.S. Provisional Application No. 60/253,743 entitled �Spontaneous emission enhanced heat transport method and structures for cooling, sensing, and power generation�, filed Nov. 29, 2000, the entire contents of which is incorporated herein by reference, and subsequently filed as PCT Application No. PCT/US01/44517 filed Nov. 29, 2001. This application is related to U.S. Provisional Application No. 60/428,753, �Three-Thermal-Terminal (T3) Trans-Thermoelectric Device�, filed Nov. 25, 2002, the entire contents of which is incorporated herein by reference. This application is related to U.S. Provisional Application No. 60/528,479, �Thin Film Thermoelectric Devices for Power Conversion and Cooling�, filed Dec. 11, 2003, the entire contents of which is incorporated herein by reference. This application is related to U.S. Ser. No. 10/265,409, �Phonon-Blocking Electron-Transmitting Low-Dimensional Structures�, filed Oct. 7, 2002, the entire contents of which is incorporated herein by reference.
A thermoelectric cooler can address these issues, for example, by removing heat from regions in the die (i.e., a medium) where heat dissipation is the highest. The thermoelectric device can be seen as a cooling device in which the cooling medium consists of electrons being electrically directed from the regions of heat generation to more remote regions where the heat contained in the electrons is dissipated. One advantage of a thermoelectric cooler in this application is that it does not require that fluids, such as for example as would be required with a heat pipe or a freon cooler, be integrated into the chip platform. Further, a thermoelectric device pumps heat to a region where more effective �passive� dissipation of heat into the environment around the chip platform is possible. More specifically, the heat is pumped to the hot side of the thermoelectric device which is in more intimate contact with the heat dissipating medium than the original heat generating region. Indeed, it is well known that passive cooling devices have a limited capacity to dissipate heat unless the passive cooling devices use microchannels which in turn require high fluid pressures
Thermoelectric coolers have been used to lower the operating temperature of semiconductor devices such as lasers. Conventionally, TE coolers have been developed separately from the integrated circuit device. The importance of developing TE coolers for semiconductor devices is evidenced by the extensive technological development directed to the subject, as seen in recent patent literature. U.S. Pat. No. 4,238,759, the entire contents of which are incorporated herein by reference, describes a Peltier device that cools an adjacent P-N junction. The Peltier junction is located a few microns from the lasing junction in this device. U.S. Pat. No. 4,279,292, the entire contents of which are incorporated herein by reference, describes a TE cooler in contact with a thermal heat sink that is in turn thermally connected to a charge coupled device. U.S. Pat. No. 5,012,325, the entire contents of which are incorporated herein by reference, describes a TE IC package in which the metalllizations of the IC constitute Peltier coolers. U.S. Pat. No. 5,362,983, the entire contents of which are incorporated herein by reference, describes a TE cooling module formed with ceramic substrate supports for the TE elements. U.S. Pat. No. 5,419,780, the entire contents of which are incorporated herein by reference, describes a Peltier cooler directly contacting an IC that is connected to a heat sink having a fan for additional cooling.
SUMMARY OF THE INVENTION One object of the present invention is to provide a thermoelectric device structure and method in which thermoelectric devices are integrated onto the device chip structure in order to cool the heat-dissipating integrated circuit devices.
BRIEF DESCRIPTION OF THE DRAWINGS The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee. A more complete appreciation of the present invention and many attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
FIG. 7 is a schematic depicting a table showing the sequential formation of a thermoelectric device of the present invention onto a semiconductor device chip.
FIG. 8A-8B are schematics depicting the bonding of a thermoelectric device structure of the present invention to a chip die;
FIG. 12 is a false color schematic depicting hot-spot thermal management of the present invention on an Insulated Gate Bipolar Transistor.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference numerals designate identical, or corresponding parts throughout the several views, and more particularly to FIG. 1 thereof, FIG. 1 depicts a schematic of one embodiment of a thermoelectric device structure according to the present invention. As shown in FIG. 1, a thermoelectric device structure 1 of the present invention is coupled to a heat-generating device 2 a such as, for example, an integrated circuit chip contained in the medium 8. For example, integrated circuit devices requiring cooling of hot spots 2 include microprocessors, graphic processors and other heat-generating devices fabricated in mediums 8 such as for example silicon, germanium, silicon-germanium, gallium arsenide, or any such semiconductor material. The thermoelectric device structure 1 of the present invention permits the temperature of the hot spot 2 of the heat-generating device 2 a to be reduced such as, for example, by 5� C. relative to a temperature that the hot spot 2 would operate at if the thermoelectric device structure 1 were not present (i.e., if the region shown in FIG. 1 where the thermoelectric device structure 1 is present were merely a thermal interface material 7 or a thermal interface compound). In some applications of the present invention, the hot spot temperature can be reduced from at least 0.5� C. to as much as 200� C., depending on the particular cooling application.
The thermoelectric device structure 1 of the present invention addresses several issues in integrating the thermoelectric device coolers to an IC chip. The thermoelectric device structure 1 of the present invention includes various heat extraction devices such as for example the thermoelectric devices 3 shown in FIG. 1, each having lower side headers 4 that dissipate heat from the thermoelectric device 3 into a heat sink 5. Other heat extraction devices suitable for the present invention include thermionic devices and a thermo-tunneling devices known in the art, as described by U.S. Pat. Nos. 6,323,414 and 6,417,060, the entire contents of which are incorporated herein by reference.
Thus, according to the present invention, there is a thermal conductance (K1′) between the boundary of the semiconductor material 8 and the thermal interface material 7 and the hot spot 2 of the integrated circuit 2 a, a thermal conductance (K1″) between the hot-side of the thermoelectric device 3 (i.e., from the lower side header 4) and the boundary between the semiconductor material 8 and the thermal interface material 7, a thermal conductance (K2) between hot-side of the thermoelectric device 3 (i.e., the lower side header 4) and the heat sink 5, and a thermal conductance (K3) between the backside of the integrated circuit 2 a and the heat sink 5. K1″ is the thermal conductance of the material adjacent to the thermoelectric device, that is in a region between 0.01 and 1.0 times the width of the thermoelectric device and preferably in region between 0.01 and 0.5 times the width of the thermoelectric device. K3 is the thermal conductance of the material beyond the material associated with K1″. A higher K3 will enable better dissipation of heat from the backside of the integrated circuit 2 a through the heat sink to the environment. A higher thermal conductance K2 will allow better dissipation of heat from the lower side header 4 through the heat sink to the environment. It is preferred that K2 be as large as possible such that the majority of the heat being thermoelectrically pumped away from the hot spot 2, by thermoelectric device 3 to lower side header 4, will be dissipated through the heat sink 5 rather than being allowed to return to the hot spot 2 (i.e., through the TIM 7 and the semiconductor material 8), which would reduce the benefit of thermoelectric device 3. According to the present invention, the typical the ratio of K1″/K2 ranges from 0.001 to 0.5.
Utilization of thinner TIM materials in the present invention is accomplished by preferably inserting an electrical isolation film 9 on one side or another of the TIM 7. The TIM 7 materials have a low coefficients of thermal expansion (CTE) or a CTE matched to that of the silicon chip as an example. Plasma deposited or evaporated films of silicon nitride or silicon dioxide or multilayers of these layers are suitable for the present invention. Further, these oxides and oxides such as Ta2O5 in thickness range of 100 to 5000 Angstroms are suitable. In one embodiment of the present invention, a highly thermally-conducting TIM material (such as for example materials with thermal conductivities in the range of 1 to 20 W/mK) can be utilized for thermal conduction while a thin (e.g., 10 nm) oxide coating provides electrical isolation.
Further, the headers (i.e., the upper side and lower side headers 4 and 6) of the present invention can be made from silicon having for example a thermal conductivity of �1.2 to 1.6 W/cm-K having a thin (i.e. �10 nm to 1000 nm) SiO2 or SixNy layer of a thermal conductivity of �0.015 W/cm-K deposited thereon. Additionally, the headers of the present invention can also be made from a Cu substrate of a thermal conductivity of �4 W/cm-K having a thin (i.e. �100 to 1000 nm) SiO2 or SixNy layer of a thermal conductivity of �0.015 W/cm-K deposited thereon.
The thermoelectric device 3 of the present invention preferably operates with a high active flux through each of the thermoelements 3 a and 3 b while having a low input/output flux across the entirety of the thermoelectric device. As described herein, this aspect of the present invention is referred as High Active Flux-Low Input-Output Flux (HAF-LIOF). In this aspect, the heat flux through the heat gatherer (e.g. an upper side header 6) and the heat spreader (e.g. an lower side header 4) is smaller than the heat flux through the n and p-type thermoelements 3 a and 3 b due to the reduced packing fraction of the thermoelements. A packing fraction of the thermoelements relative to the area of the headers 4 and 6 permits the utilization of thinner thermoelements, thereby reducing the fabrication costs that would be involved should for example thicker sections of high ZT materials be required to maintain the requisite ΔT across the thermoelectric device.
The packing fraction of thermoelements (i.e., the fraction of area occupied by the pair of n and p-type thermoelements 3 a and 3 b relative to a unit area of for example the upper-side header 6) in one embodiment of the present invention is less than 50%, preferably less than 20%, and can be significantly lower, such as for example 0.5-1%. A unit area for the heat spreader is defined as that fraction of the total area of the heat spreader which principally conducts heat into one of the associated pairs of n and p-type thermoelements attached to the heat spreader. For a single pair of n and p-type thermoelements, the unit area would be one half area of the upper side header 6 shown in FIG. 1. For instance, while the total heat flux into upper-side header 6 and out the lower-side header 4 can be on the order of 10-30 W/cm2, the heat flux through each thermoelectric pair 3 a and 3 b can be as much as a factor of 100 times higher. As such, a high internal heat-flux exists within the individual thermoelectric elements (e.g., �900 W/cm2 for a ΔT across each stage of 40K). Meanwhile, a low external heat-flux exists across the entirety of the thermoelectric device (e.g., a range from 5 to 15 W/cm2). Details of the packing fraction selection and determination are described in U.S. Provisional Application No. 60/528,479.
The concepts of the present invention are not restricted to any particular family of thermoelectric materials. The use of superlattice material or other high ZT material improves thermoelectric device efficiency of the HAF-LIOF thermoelectric device of the present invention. Selection of appropriate materials for the thermoelements are likewise described in detail in U.S. Provisional Application No. 60/528,479. As described therein, high ZT thin films in the PbTe/PbSe and in the SiGe material systems can be used in superlattice configurations or other quantum-confined structures such as for example, PbTe-based quantum-dot superlattices (QDSL). Additionally, Bi2Te3-superlattice/PbTe/SiGe material combinations and superlattices of Si/Ge, PbTe/PbSe, ZnSb/CdSb, InAs/InSb, CdTe/HgCdTe, GaxIn1-xAs/GayIn1-yAs can be used. As further described in U.S. Provisional Application No. 60/528,479, p and n-type Bi2Te3-based superlattice elements having ZT�3.5 in p-type superlattices and �2.0 in n-type can be utilized. Utilization of high ZT materials improves power conversion efficiencies and cooling efficiencies for the thermoelectric devices of the present invention.
The contacts of the present invention can include multi-layer metallizations of Cr/Au/Ni/Au and Ni/Au. Examples of other conductive metal layers suitable for use in the present invention include Au, Cu, Ni, Ag, Pd, Pt, Al, Ga, In, and alloys containing these metals. The use of Cr is desired for improving or obtaining better adhesion of the metal layer to the superlattice surface. Examples of other adhesion promoters suitable for use in the present invention besides Cr are NiCr, Ti, Mo, W, and alloys containing these metals. Ni is included to provide a diffusion barrier to bonding materials such as Pb�Sn, which are needed in bonding the thermoelectric devices to a heat-source or heat-sink header from diffusing into the superlattice. Examples of other diffusion barriers suitable for use in the present invention besides Ni include Cr, Pd, Fe, and other metals, thickness of a few thousand Angstroms to several microns, with a lattice structure different from the superlattice materials.
The thickness of various ohmic metallizations of the present invention can be Cr/Au/Ni/Au of 300 Å/3000 Å/300 Å/3000 Å and Ni/Au of 300 Å/3000 Å, upon which additional metals such as thick Au or Pb�Sn can be used to reduce spreading resistances.
For the 10 Å/50 Å Bi2Te3/Sb2Te3 superlattice shown in FIG. 3 b, the measured cross-plane electrical resistivity (ρ⊥) is 8.47E-4 Ohm-cm. With an in-plane electrical resistivity (ρin-plane) of 9.48E-4 Ohm-cm, ρ⊥/ρin-plane or μ⊥/μin-plane is �1.12. For the sample in FIG. 3 c, ρ ⊥ is 5.26e-4 Ohm-cm and the ρin-plane is 5.5E-4 Ohm-cm, and the anisotropy is �1.05.
In addition to managing electrical contact resistances, thermal interface resistances are reduced in the metal-to-dielectric interfaces of the present invention by deep-annealing of a metal into the dielectric bulk or by utilizing an AlN-diffused Al�Cu interface or AlN fused onto Cu. The AlN can be ionic fused onto copper directly or Al on Copper can be preferentially oxidized or nitrided or AlN plates can be soldered onto copper plates. The use of ionic fused materials are discussed separately elsewhere. Regardless of technique employed, the thermal interface should have a thermal conductivity of 0.1 W/cm2K to 0.001 W/cm2K.
Various methods are available for the manufacturing of the devices and the device components of the present invention. Such methods are described in U.S. Provisional Application No. 60/528,479 and referred to therein as inverted-couple processing. The table shown in FIG. 7 illustrates the inverted processing approach suitable for the present invention.
A top, pre-patterned metallization header can, in one embodiment of the present invention, be attached to the metallized sections to function as the aforementioned heat pipe. Alternatively, the header itself prior to metallization can be patterned to provide the aforementioned heat pipe. The formed pair of thermoelements (i.e., the n thermoelement and the p-thermoelement) including the attached header can then be flipped and bonded to a second header. The second header, referred to herein as the lower side header, thermally connects the n thermolelement to the p-thermoelement, but contains patterned electrical connections such that electrically the n thermoelement 3 a and the p-thermoelement 3 b are individually connected, as shown in FIG. 1. The lower side header 4 thus functions as an electrical member having, as shown in FIG. 1, a split electrical contact (i.e., an electrical contact only contacting individually the n-type and p-type thermoelements 3 a and 3 b), while as a thermal member the bottom header functions as a continuous thermal contact.
For example, the bonding techniques described in U.S. Provisional Application No. 60/528,479 can be used join the semiconductor chip to the heat spreader. For example, a AgCuP eutectic bond or a AuIn eutectic bond or an InSn eutectic bond can be used. In one embodiment of the present invention, as described in U.S. Provisional Application No. 60/528,479, radiant thermal energy transfer can also be used to thermally connect the thermoelectric devices to the intergrated circuit devices. Radiant thermal energy transfer utilize Purcell-enhancement cavity transmitter/receiver structures such as those described in the afore-mentioned U.S. Provisional Application No. 60/253,743, the entire contents of which are incorporated herein by reference, entitled �Spontaneous emission enhanced heat transport method and structures for cooling, sensing, and power generation� for heat transfer.
1. utilization of thermal adhesives or thermally conductive epoxy,
2. soldering,
3. diffusion bonding using electroplated or evaporated metal contacts,
4. utilization of anisotropic thermal adhesives,
5. utilization of thermoplastic conductive polymers, and
6. utilization of silicon to silicon molecular bonding (in the case where the cooling header of the thermoelectric device is made from silicon).
Regardless of approach, a thermally conductive and mechanically stable connection or bond between the thermoelectric device and the integrated circuit device is preferred.
(1) attaching a pre-fabricated thermoelectric module to a device wafer,
(2) building a thermoelectric device from the backside of a device wafer, or
(3) building a part of a thermoelectric device onto the backside of a device wafer and completing fabrication by attachment of remaining pre-fabricated components.
For attachment, several attachment methods can be used including: (1) soldering, (2) brazing, (3) friction bonding, and (4) insulator-insulator bonding similar to wafer bonding. Furthermore, in a preferred embodiment, a hybrid �reactive� bonding process is utilized in which insulator surfaces, having a thin reactive metal layer, are placed opposed to one another and then contacted and heated to react the metal layer with the insulator surfaces and thereby bond the opposed components together. Such a metal include for example Ti, W, Cr, Mo, etc., or alloys thereof. These metals readily oxidize and form in a preferred embodiment silicides which melt at temperatures of 300� C. or less. The hybrid reactive bonding process of the present invention relies on the reactivity of the thin metal layer with the respective insulators to achieve a bond. In one embodiment of the present invention, the metal layer is preferably thin (e.g., less than 500 Å) such that all of the reactive layer is consumed, or reacts with, the insulating layers. In hybrid reactive bonding, bonding is achieved when the surfaces are brought into contact and then heated such that the metal reacts with one or both insulating surfaces.
Another alternative approach of the present invention for integrating the various thermoelectric conversion stages utilizes radiant thermal energy transfer using Purcell-enhancement cavity transmitter/receiver structures such as those described in the afore-mentioned U.S. Provisional Application No. 60/253,743, the entire contents of which are incorporated herein by reference, entitled �Spontaneous emission enhanced heat transport method and structures for cooling, sensing, and power generation� for heat transfer from one thermoelectric power conversion stage to another. In this approach, the radiant portion, if not the dominant process, plays a substantial role in managing thermal stress by providing less-rigidly-bonded interfaces. Indeed, the present invention can utilize Purcell enhancement from an enhanced density of radiative modes in small-scale structures (similar to enhanced electronic density of states in quantum-confined systems) for enhanced spontaneous emission using patterned/μm-size-range, appropriately-spaced, structures for specific temperatures, on the heat spreader. FIG. 9 is a schematic (not to scale) depicting the utilization of radiant coupling in the present invention. Thus, engineered micro-fins 16 as shown in FIG. 9 can also potentially enhance spontaneous radiative heat transport. The engineered micro-fins 16 have μm-size geometries achievable with photolithography a large-area wafers for a cost-effective implementation.
Spontaneous emission enhanced heat transport (SEEHT) may additionally enhance emission at infra-red wavelengths near 300K. The incorporation of micron or sub-micron size Purcell cavities, will provide for the theoretical maximum radiative emission at peak wavelengths of 10 μm which will enhance heat transport by as much as a factor of 1000 at 300K, leading to a radiative dissipative flux of ΦSEEHT of 44 W/cm2. Such micron size particles incorporated by impregnation or self-assembly, followed by overgrowth, permit the scope for radiative heat transfer mechanisms to be considerably enhanced. Such particles can further be incorporated in high-thermal conductivity heat spreader such as SiC, AlN, Si, diamond, etc. While not limited to the following theory, the present invention recognizes that of enhanced emission with these Purcell cavity structures can be further enhanced/realized if there is matching of �increased density of states� in emitters with �increased density of states� with receivers/absorbers, i.e., resonant thermal energy transfer. In addition to �resonant thermal energy transfer� by Purcell-cavity effects, other �proximity coupling of radiative infrared modes� can be exploited as well, in the present invention. Utilization of radiation coupling will, according to the present invention, reduce thermal stress, by removing (strong) physical interfacial contacts between various stages. Further, the mechanical alignment of the resonant structures will not be a significant issue, given that the typical size of the inverted couple headers are �300 μm�300 μm.
In this configuration, thermoelectric devices 3 are positioned as needed on the back of the microprocessor die 20 opposite areas of increased heat dissipation, or �hot spots.� The location of the hot spots, and the associated thermoelectric device, will be dictated by the particular design and architecture employed for that microprocessor. In this example, power and control signals are routed between the thermoelectric devices 3 using a series electrical connection 24, but alternate methods may include, but are not limited to, parallel connection schemes and separate control lines. Associated with each thermoelectric device 3 is a control circuit 26 which receives signals from the analytical processor 22 (e.g., the above-noted neural net processor) and sets the appropriate current as specified by the signal from the neural net processor 22.
Additionally, hot-spot problems are not unique to logic and digital signal processing chips. Hot-spot problems are observed in power electronic building blocks, commonly referred to as PEBB, and other high-power RF communication devices. An example is an Insulated Gate Bipolar Transistor (IGBT) chip which can have one or more hot-spots. One example of conventional passive heat sink cooling of IGBT chips is shown in FIG. 12. In that approach, the design of the heat sink must as a whole accommodate the local hot spots. Instead of designing the entire cooling system to manage the hot-spots, the present invention can cool the hot-spots selectively by the cooling technology described in the present invention. For example, the configuration shown in FIG. 2A is particularly suited for such an IGBT cooling situation, where the thermal impedance on the active side of the silicon chip for heat-removal is significantly low, when contrasted with microprocessor hot-spots, to enable direct, localized, active heat-pumping.
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Hutchby et al., Center for Semiconductor Research, Research Triangle Institute, Research Triangle Park, NC 27709, USA, Solar-Energy Materials and Solar Cells 35 (1994) pp. 9-24.28High-Quality Eutectic-Metal-Bonded AlGaAs-GaAs Thin Films on Sl Substrates, Rama Venkatasubramanian et al., Appl. Phys. Lett., vol. 60, No. 7, Feb. 17, 1992, pp. 886-888.29High-Temperature Performance and Radiation Resistance of High-Efficiency Ge and Si0.07Ge0.03 Solar Cells on Lightweight Ge Substrates, Rama Venkatasubramanian et al., pp. 85-98.30Hofmeister, Rudolf et al., New Photorefractive Mechanism in Centrosymmetric Crystals: A Strain-Coordinated Jahn-Teller Relaxation, Physical Review Letters, vol. 69, No. 9, Aug. 31, 1992, pp. 1459-1462.31Ideal Electronic Properties of a p-Ge/p-Al0.85Ga0.15As Interface, Rama Venkatsubramanian et al., Appl. Phys. Lett., vol. 59, No. 3, Jul. 15, 1991, pp. 318-320.32Improved Photoluminescence of GaAs in ZnSe/GaAs Heterojuncations grown by Organometallic Epitaxy, S.K. Ghandhi et al., Electrical Computer, and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, New York 12180, Appl. Phys. Lett. vol. 53 No. 14, Oct. 3, 1988, pp. 1308-1310.33Incorporation Processes in MBE Growth of ZnSe, Rama Venkatasubramanian et al., Journal of Crystal Growth 95 (1989) pp. 533-537.34In-Plane Thermoelectric Properties of Freestanding Si/Ge Superlattice Structures, Rama Venkatasubramanian et al., 17th International Conference on Thermoelectrics (1998), pp. 191-197.35In-situ Monitoring of the Growth of Bi2 Te3 and Sb2 Te3 Superlattice Using Spectroscopic Ellipsometry Hao Cui et al. Journal of Electronic Materials, vol. 30, No. 11 2001, Special Issue Paper, pp. 1376-1381.36Interface-Free GaAs Structures-From Bulk to the Quantum Limit, D.J. Wolford, et al, Inst. Phys. Conf. Ser. No. 120: Chapter 9, pp. 401-406.37International Search Report and Written Opinion for PCT/US2005/034574; Aug. 28, 2007.38International Search Report and Written Opinion for PCT/US2006/014377; date of mailing Jan. 12, 2007.39International Search Report for PCT/US2005/034574 dated Jun. 6, 2007.40Intrinsic Recombination and Interface Characterization in "surface-free" GaAs Structures, D.J. Wolford et al., J. Vac. Sci. Technol. B. vol. 9, No. 4, Jul./Aug. 1991, pp. 2369-2376.41IR-Mediated PCR http://faculty.virginia.edu/landers/lrframe.htm.42Lattice Thermal Conductivity Reduction and Phonon Localizationlike Behavior in Superlattice Structures, Rama Venkatasubramanian, Research Triangle Institute, Research Triangle Park, North Carolina 27709, Physical Review B., vol. 61, No. 4, Jan. 15, 2000-II, pp. 3091-3097.43Low-temperature Organometallic Epitaxy and Its Application to Superlattice Structures in Thermoelectrics, Rama Venkatasubramanian, a), et al., Sandra Liu and Nadia El-Masry, Michael Lamvik, Applied Physics Letters, vol. 75, No. 8, Aug. 23, 1999, pp. 1104-1106.44Magnetoresistance Technique for Determining Cross-Plane Mobility in Superlattice Devices, S.W. Johnson et al., National Renewable Energy Laboratory, Golden, CO, USA, Research Triangle Institute, Research Triangle Park, NC, USA, 18th International Conference on Thermoelectrics (1999), pp. 675-686.45Material and Device Characterization Toward High-Efficiency GaAs Solar Cells on Optical-Grade Polycrystalline Ge Substrates, Rama Venkatasubramanian, et al., R. Ahrenkiel, et. al, First WCPEC; Dec. 5-0, 1994; Hawaii, 1994 IEEE pp. 1692-1696.46Measurement of Al/GaAs/AlGaAs Interface Recombination Velocities Using Time-Resolved Photoluminescence, M.L. Timmons, et al., Appl. Phys. Lett. vol. 56, No. 19, May 7, 1990, pp. 1850-1852.47MOCVD of Bi2Te3 and Their Superlattice Structures for Thin-Film Thermoelectric Applications, Rama Venkatasubramanian et al., Journal of Crystal Growth 170 (1997), pp. 817-821.48Nanostructured Superlattice Thin-Film Thermoelectric Devices; Nanotechnology and the Environment Applications and Implications; American Chemical Society (2005) (ACS Symposium Series 890) Chapter 47, pp. 347-352.49Nature Publishing Group, Materials Update, Cool Future for Semiconductors, Oct. 11, 2001. pp. 1-3.50ONR Contributes to Thermoelectric Research (Office of Naval Research) (Brief Article), Ozone Depletion Network Online Today, Contact ONR, website http://www.onr.navy.mil., Nov. 2001.51Optical Constants of Bi2Te3 and Sb2Te3 Measured Using Spectroscopic Ellipsometry, Hao Cui 1I.B. Bhat1,3 and Rama Venkatsubramanian2, 1-Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY 12180-3590, USA. 2.-Research Triangle Institute, Research Triangle Park, NC 27709, USA, 3-e-mail:bhati@.rpi.edu., Journal of Electronics Materials, vol. 28, No. 10, 1999, pp. 1111-1114.52Optimization of the Heteroepitaxy of Ge on GaAs for Minority-Carrier Lifetime, Rama Venkatasubramanian, et al., Journal of Crystal Growth 112 (1991) pp. 7-13, Received Aug. 9, 1990; manuscript received in final form Dec. 14, 1990.53Optoelectronic Properties of Eutectic-Metal-Bonded (EMB) GaAs-AlGaAs Structures on Si Substrates, Rama Venkatasubramanian, et al., Solid-State Electronics vol. 37, No. 11, pp. 1809-1815, 1994.54Phonon Blocking Electron Transmitting Superlattice Structures as Advanced Thin Film Thermoelectric Materials, Rama Venkatasubramanian, Research Triangle Institute, Research Triangle Park, NC, Chapter 4, Semiconductors and Semimetals, Vol., pp. 175-201.55Phonon-Blocking Electron-Transmitting Structures, Rama Venkatasubramanian et al., Research Triangle Institute, Research Triangle Park, NC, USA, 18 International Conference on Thermoelectric (1999), pp. 100-103.56Photoexcited Carrier Lifetimes and Spatial Transport in Surface-free GaAS Homostructures, L.M. Smith et al., J. Vac. Sci. Technol. B, vol. 8, No. 4 Jul./Aug. 1990, pp. 787-792.57Photoluminescence of Porous Silicon Buried Underneath Epitaxial GaP, J.C., Campbell, et al., Appl. Phys. Lett., vol. 60, No. 7, Feb. 17, 1992, pp. 889-891.58Photoreflectance Characterization of InP and GaAs Solar Cells, R.G. Rodrigues et al., 1993 IEEE pp. 681-685.59Physical Basis and Characteristics of Light Emission From Quantized Planar Ge Structures, Rama Venkatasubramanian, et al., pp. 15.4.1-15.4.4.60Potential of Si-based Superlattice Thermoelectric Materials for Integration with Si Microelectronics, Rama Venkatasubramanian et al., 1998 IEEE, p. 869.61Properties and Use of Cycled Grown OMVPE GaAs: Zn, GaAs:Se, and GaAS:Si Layers for High-Conductance GaAS Tunnel Junctions, Rama Venkatasubramanian et al., National Renewable Energy Laboratory, Golden, CO 80401, pp. 893-899.62Radiative Recombination in Surface free n+In-In+ GaAs Homostructures, L.M. Smith and D.J. Wolford et al., Appl. Phys. Lett., vol. 57, No. 15, Oct. 8, 1990, pp. 1572-1574.63Reddy et al. "Measurement and Analysis of Power Conversion Efficiency in Thin-Film and Segmented Thermoelectric Devices" Thermoelectrics, ICT 2005, 24th International Conference pp. 72-75 (2005).64RTI International Annual Report 2001, Turning Knowledge into Practice, pp. 4-37.65RTI International, "New Thermoelectric Materials Can Keep Chips Cool Advances in Fiber Optics and in Biotechnology also are Likely" Oct. 9, 2001.66RTI Research Yields Major Advance in Thermoelectrics, Rama Venkatsubramanian et al., pp. 8-9.67Samuel K. Moore, Making Chips, IEEE Spectrum, Biotechnology, Mar. 2001, pp. 54-60.68Selective Plasma Etching of Ge Substrates for Thin Freestanding GaAs-AlGaAs Heterostructures, Rama Venkatasubramanian et al., Appl. Phys. Lett., vol. 59, No. 17, Oct. 21, 1991, pp. 2153-2155.69Semiconductors are Cool, News and Views, Cronin B. Vining, 2001 Macmillan Magazines Ltd., Nature, vol. 413, Oct. 11, 2001, www.nature.com, pp. 577-578.70Shakouri et al; "On-Chip Solid-State Cooling for Integrated Circuits Using Thin-Film Microrefrigerators"; XP-002428271, IEEE Transactions on Components and Packaging Technologies, vol. 28, No. 1, Mar. 2005, pp. 65-69.71Silicon and GAAS/GE Concentrator Power Plants: A Comparison of Cost of Energy Produced, R.A. Whisnant et al., First WCPEC; Dec. 5-9, 1994; Hawaii, 1994 IEEE pp. 1103-1106.72Smaller, Faster, Efficient Thermoelectric Cooling, Rama Venkatasubramanian, vol. 30, No. 41, Oct. 17, 2001 ISSN: 0300-757X, pp. 1-2.73Sneak Preview, Optical Device Transfers Data Fast, Rama Venkatasubramanian, design news Dec. 17, 2001. p. 14.74Superlattice Thin-film Thermoelectric Materials and Devices; Rama Venkatasubramanian et al.; Mat. Res. Soc. Symp. Proc. vol. 793 (2004 Materials Research Society) pp. 51-58.75Supplementary Partial European Search Report, Application No. EP 02 72 5575 (Apr. 4, 2006).76The Growth and Radiation Response of N+p Deep Homojunction InP Solar Cells, M.J. Panunto et al., M.L. Timmons, et al., First WCPEC; Dec. 5-9, 1994; Hawaii, pp. 2192-2195.77The New Face of A.I., Michael Powell, Merger Maniac Europe's CD Underworld, The Supercheap Future of Flying, Mar. 2002, Hacking the Racetrack, Insife Nuke University, Wired, A New Kind of Cool, Rama Venkatasubramanian.78Thermal Characterization of Bi2, Te3/Sb2 Te3 Superlattices, M.N. Touzelbaev and P. Zhou, Department of Mechanical Engineering, Stanford University, Stanford, California 94305-3030, Rama Venkatasubramanian, Center for Semiconductor Research, Research Triangle Institute, Research Triangle Park, Durham, NC 27709-2195, K.E. Goodson Electronic mail goodson@vk.stanford.edu, Journal of Applied Physics, vol. 90, No. 2, Jul. 15, 2001, pp. 763-767.79Thermal Conductivity of Si-Ge Superlattices, S.-M. Lee and David G. Cahilla), Rama Venkatasubramanian, Appl. Phys. Lett. vol. 70, No. 22, Jun. 2, 1997, pp. 2957-2959.80Thermoelectric Boost, Richard Babyak, Appliance Manufacturer, Design and Engineering Solutions for the Global Appliance Industry, http://www.ammagazine.com/CDA/ArticleInformation/features/BNP Features Item/0.260... Jul. 18, 2002, pp. 1-2.81Thermoelectronics from Hot to Cool, New Technology Offers Efficient way to Heat or Cool ICS in Operation, Jeff Dorsch, Semiconductor Magazine, http://www.semi.org/web/wmagazine.nsf/4f55b97743c2d02e882565bf006c2459/27e74866ea ..., Jun. 20, 2002, pp. 1-3.82Thin-Film Technology, Research Triangle Institute, Investment Opportunities, in Thermoelectronics, Apr. 6, 2001, website http://www.rti.org/units/es.cfm, pp. 1-2.83Thin-Film Thermoelectric Devices with High Room-Temperature Figures of Merit, Rama Venkatasubramanian et al., Research Triangle Institute, Research Triangle Park, North Carolina 27709, USA, 2001 Macmillian Magazines Lt., Nature, vol. 413, Oct. 11, 2001, www.nature.com pp. 597-602.84US 6,381,965, 05/2002, Ghoshal (withdrawn)85Venkatasubramanian et al., "Thin-film thermoelectric devices with high room0temperature figures of merit"; XP-001090991, Nature vol. 413 (Oct. 11, 2001) pp. 597-602.86Visible Light Emission From Quantized Ge Structures, Rama Venkatasubramanian et al., Appl. Phys. Lett., vol. 59, No. 13, Sep. 23, 1991, pp. 1603-1605.87Zhang et al.; "High Speed Localized Cooling Using SiGe Superlattice Microrefrigerators"; 19th IEEE (2003) Semi-Therm Symposium pp. 61-65.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7914271Nov 29, 2007Mar 29, 2011Husky Injection Molding Systems Ltd.Gate insert heating and coolingUS8665592 *Oct 25, 2011Mar 4, 2014Advanced Micro Devices, Inc.Heat management using power management informationUS20120039041 *Oct 25, 2011Feb 16, 2012Mowry Anthony CHeat management using power management informationUS20120317993 *Jun 17, 2011Dec 20, 2012Advanced Ion Beam Technology, Inc.Apparatus and method for controlling workpiece temperature* Cited by examinerClassifications U.S. Classification62/3.7, 62/259.2, 361/718, 165/104.33, 62/3.2International ClassificationH05K7/20, F25B21/02, F28D15/00, F25D23/00Cooperative ClassificationF25B2321/003, H01L35/30, F25B21/02European ClassificationH01L35/30, F25B21/02Legal EventsDateCodeEventDescriptionOct 29, 2012FPAYFee paymentYear of fee payment: 4Aug 12, 2009ASAssignmentOwner name: NAVY, UNITED STATES OF AMERICA, THE, AS REPRESENTEFree format text: CONFIRMATORY LICENSE;ASSIGNOR:RESEARCH TRIANGLE INSTITUTE;REEL/FRAME:023084/0011Effective date: 20081222Jun 23, 2009CCCertificate of correctionMar 13, 2009ASAssignmentOwner name: NEXTREME THERMAL SOLUTIONS, INC., NORTH CAROLINAFree format text: RE-RECORD TO ADD CORPORATE SUFFIX TO COMPANY NAME AND UPDATE COMPANY ADDRESS ON A DOCUMENT PREVIOUSLY RECORDED AT REEL 015849, FRAME 0040. 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