Source: http://www.google.com/patents/US20030113969?dq=7,444,563
Timestamp: 2015-03-01 04:59:38
Document Index: 546690272

Matched Legal Cases: ['Application No. 2001', 'art 134', 'art 134', 'art 151', 'art 134', 'art 134', 'art 134']

Patent US20030113969 - Method of forming flash memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe present invention provides a method of forming a split gate type flash memory. After exposure of a floating gate layer between silicon nitride layers, a conductive layer spacer is formed on a sidewall of the silicon nitride layer pattern. The conductive layer spacer is formed in a floating gate of...http://www.google.com/patents/US20030113969?utm_source=gb-gplus-sharePatent US20030113969 - Method of forming flash memoryAdvanced Patent SearchPublication numberUS20030113969 A1Publication typeApplicationApplication numberUS 10/277,848Publication dateJun 19, 2003Filing dateOct 22, 2002Priority dateDec 18, 2001Also published asUS6730565Publication number10277848, 277848, US 2003/0113969 A1, US 2003/113969 A1, US 20030113969 A1, US 20030113969A1, US 2003113969 A1, US 2003113969A1, US-A1-20030113969, US-A1-2003113969, US2003/0113969A1, US2003/113969A1, US20030113969 A1, US20030113969A1, US2003113969 A1, US2003113969A1InventorsMin-Soo Cho, Dong-Jun Kim, Jin-woo KimOriginal AssigneeSamsung Electronics Co.,Ltd.Export CitationBiBTeX, EndNote, RefManReferenced by (8), Classifications (17), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod of forming flash memory
RELATED APPLICATION [0001] This application relies for priority upon Korean Patent Application No. 2001-80483, filed on Dec. 18, 2001, the contents of which are herein incorporated by reference in their entirety. FIELD OF THE INVENTION [0002] The present invention relates to a method of forming a flash memory and, more particularly, to a split gate type flash memory. BACKGROUND OF THE INVENTION [0003] Flash memories are non-volatile memory devices with a structure that is suitable for high integration density. Accordingly, recently, the flash memories are intensively studied and developed. In a conventional flash memory device, a memory cell gate pattern is made of a floating gate, a control gate, and a dielectric film interposed therebetween. [0004] A novel dual gate type non-volatile memory is being developed, in which an erase operation is performed toward wordlines from a floating gate to generate a relatively lower erase voltage. Since the floating gate and a control gate of the novel memory are horizontally disposed, an opposite side thereof is relatively reduced and F-N tunneling is centralized to a tip of the floating gate (U. S. Pat. No. 5,029,130). [0005]FIG. 1 and FIG. 2 are cross-sectional views illustrating programming and erasing methods performed in a cell transistor of a non-volatile memory device having a floating gate and a control gate that are horizontally separated with a dielectric film interposed therebetween. [0006] Referring now to FIG. 1, for programming, a high voltage Vdd is applied to a common source line 21 and a threshold voltage Vth is applied to a control gate line 120. Further, a zero voltage (0V) is applied to a drain region 109 and a substrate 100. Thus, electrons are moved from the drain region 109 to a source region 110. By passing a tunneling gate insulating layer 15, the electrons are accumulated into the floating gate 130. That is, the programming is performed. [0007] Referring now to FIG. 2, for erasing, a zero voltage (0V) is applied to the common source line 21 and a high voltage Vdd is applied to the control gate line 120. Further, a zero voltage (0V) is applied to the drain region 109 and the substrate 100. Thus, the electrons accumulated into the floating gate 130 are induced to the high voltage Vdd of the control gate line 120. The induced electrons are moved to the control gate line through the tunneling gate insulating layer 15. That is, the erasing is performed. Since an electric field is centralized to a tip 23 of the floating gate 130, the electrons of the floating gate 130 are moved to the control gate line 109 through an insulating layer adjacent to the tip 23. [0008]FIG. 3 is a top plan view showing a layout in the case where a transistor device is realized in a cell area of a conventional split gate type flash memory. FIG. 4 through FIG. 8 are cross-sectional views, taken along a line A-A of FIG. 3, showing the steps of forming the layout of FIG. 3. [0009] Referring now to FIG. 3, a device isolation layer 103 is formed to define an active region 101 that is formed along line A-A. A common source region or a common source line 21 is formed along a line C-C. A spacer oxide layer 115, a control gate line or a wordline 120, a spacer nitride layer 125, and a substrate-exposing part are formed parallel to both sides of the common source region 21 or the common source line. [0010] At an intersection of the active region 101 and the substrate-exposing part, a drain region 109 is formed at a substrate. In the drain region 109, a bitline contact 107 will be formed in a subsequent process. As illustrated by bold lines, bitlines 105 are formed along the line A-A to cover the active region 101. At an intersection of the active region 101 and the spacer oxide layer 115, a floating gate 130 is formed under the spacer oxide layer 115. [0011] Referring now to FIG. 3 and FIG. 4, after stacking a tunneling gate insulating layer 15 and a floating gate layer on a substrate 100, a trench type field oxide layer (trench type device isolation layer 103 of FIG. 3) is formed. The floating gate layer is partially removed to remain as a floating gate pattern 131. Alternatively, a tunneling gate insulating layer and a floating gate layer are formed on a device-isolated substrate and by a patterning process, the floating gate pattern may remain only over the active region. A silicon nitride layer 115 is formed on an entire surface of the substrate 100, and then a patterning process is carried out to form a silicon nitride pattern 135 exposing the common source region 110 and the spacer oxide layer 115 of FIG. 3. The floating gate pattern 131 exposed between the silicon nitride patterns 135 is partially subjected to the thermal oxidation. An upper part of the floating gate pattern 135 is then oxidized to cause a bird's beak where an oxide layer 133 penetrates into a lower part of the silicon nitride pattern 135 at an interface between the patterns 131 and 135. [0012] Referring to now FIG. 3 and FIG. 5, a silicon oxide layer for a spacer is conformally formed on an entire surface of a substrate where the oxidized upper part of the floating gate pattern 131 is removed or unremoved. The silicon oxide layer is etched back to make the spacer oxide layer 115 remain on a sidewall of the silicon oxide layer pattern 135. An unoxidized floating gate pattern 131 is exposed between the spacer oxide layers 115. Using the spacer oxide layer 115 and the silicon nitride pattern 135 as an etch mask, the floating gate pattern 131 is continuously etched to remove the exposed floating gate pattern 131. Concurrently, a tunneling gate insulating layer 15 is removed to expose the substrate 100. Afterwards, impurities are implanted to form a source region 110 at an exposed substrate 100. In one embodiment, this is performed with a dose of 1015 ions/cm2. In a subsequent annealing process, the source region 110 will be extended to partially overlap with a floating gate region. [0013] A section of the floating gate pattern 131 is exposed to a lower part of the spacer oxide layer 115 at a substrate 100 exposed to the source region 110. After/before the implantation of the impurities, a thermal oxidation process is performed or a thin CVD oxide layer is formed to cover the section of the floating gate layer 131. [0014] Referring now to FIG. 3 and FIG. 6, the silicon oxide layer of the source region 110 is removed. A polysilicon layer is then stacked on an entire surface of the substrate to fill a space between the spacer oxide layers. By means of a CMP or an etch-back technique, the polysilicon layer is removed on an upper surface of the silicon nitride pattern 135. As a result, the polysilicon layer remains only in the space between the spacer oxide layers 115 to form a common source line 21. [0015] Referring now to FIG. 3 and FIG. 7, the silicon nitride pattern 135 is removed by phosphoric acid or the like. By means of an anisotropic etch using the spacer oxide layer 115 as an etch mask, the floating gate pattern 131 is removed to form a floating gate 130. Concurrently, an upper part of the common source line 21 may be partially removed. Further, the tunneling gate insulating layer 15 may be concurrently removed to expose the substrate 100. A thin CVD oxide layer is conformally formed on an entire surface of the substrate 100. Alternatively, a thermal oxidation process is carried out to form an oxide layer 116 covering a sidewall of the floating gate 130 exposed below the spacer oxide layer 115 and the exposed substrate 100. During this procedure, the sidewall of the floating gate 130 may be partially oxidized to be laterally protruded. [0016] Referring now to FIG. 8, a polysilicon layer 143 and a silicon nitride layer 145 are conformally formed on an entire surface of the substrate 100 in order to form a control gate or a wordline. The silicon nitride layer 145 may be substituted by a silicon oxynitride layer or the like. [0017] Referring now to FIG. 9, an entire surface of the resultant structure of FIG. 8 is planarized by a CMP process to be even with a top surface of the common source line 21. Thus, the polysilicon layer 143′ is exposed toward the side of the spacer oxide layer 115. On the other hand, the polysilicon layer 143′ covered with a silicon nitride layer 145′ is not exposed. An exposed common source line 21 and the exposed polysilicon layer 143′ are thermally oxidized to form a silicon oxide layer 147. [0018] Referring now to FIG. 10, using the silicon oxide layer 147 and the space oxide layer 115 as an etch mask, the silicon nitride layer 145′ and the polysilicon layer 143′ are sequentially removed. Thus, a polysilicon pattern remains on an opposite side of the common source line 21 of the spacer oxide layer 115 to form a wordline 120. [0019] Alternatively, in the steps of FIG. 8, the polysilicon layer 143 is conformally stacked and anisotropically etched back to make a spacer-shaped polysilicon pattern remain on a sidewall of the spacer oxide layer 115. [0020] Referring now to FIG. 11, another silicon nitride layer is stacked and anisotropically etched back to make the spacer nitride layer 125 remain on the opposite side of the spacer oxide layer 115 of the wordline 120. Heavily doped impurities are implanted into an exposed active region of the substrate 100 to form a drain region 109. In a subsequent annealing process, the drain region 109 may be extended toward a lower part of the spacer nitride layer 125. [0021] After stacking and planarizing an interlayer insulating layer on an entire surface of a resultant structure, a bitline contact hole is formed. A conductive layer, i.e., a metal layer, is stacked on the bitline. The conductive layer is then patterned to form a bitline contact and a bitline. [0022] A cell transistor of a flash memory formed by the foregoing procedure has a few drawbacks. For example, in order to expedite an erase operation, a tip of a floating gate is formed with an acute angle so that an electric field may be concentrated on the tip, as shown in FIG. 2. With reference to a procedure of forming the floating gate in FIG. 4 through FIG. 8, key steps of forming the tip with an acute angle lie in FIG. 4 and FIG. 8. In the step of partially oxidizing the floating gate pattern 131 of FIG. 4, a bird's beak of both ends of an oxide layer 131 must be short and steep-sloped. In the etching step of FIG. 8, the floating gate pattern 131 must be anisotropically etched. [0023] But in the oxidizing step of FIG. 4, only an upper part of the floating gate pattern 131 must be oxidized because a lower part thereof is to be a floating gate. Due to this restriction, it is hard to form a thick oxide layer by thermally oxidizing the upper part of the floating gate pattern 131. It is also hard to form a steep-sloped bird's beak at an interface between the floating gate pattern 131 and the silicon nitride pattern 135. As a result, it is hard to form a tip (23 of FIG. 1) with an acute angle. [0024] Furthermore, when the floating gate pattern 131 is partially oxidized (FIG. 4), the oxidization is not limited thereto. As shown in FIG. 12A taken along a line B-B of FIG. 3, an upper part of the floating gate pattern 131 as well as a lateral part 134 adjacent to the device isolation layer 103 is exposed. Therefore, as shown in FIG. 12B, a lateral part 134 and a lower part 151 are oxidized by oxygen that is introduced through the lateral part when an upper oxide layer 133 of the floating gate pattern 131 is formed. [0025] When a lower part of the floating gate pattern 131 is oxidized near the device isolation layer 103, the tunneling gate insulating layer 15 is to be thick at both lateral parts of a channel (see 151 of FIG. 12B). In a program operation, it is difficult for electrons to pass the thick tunneling gate insulating layer. Therefore, it takes a longer time to accumulate electrons in a floating gate. That is, a program operation speed is lowered in a cell memory transistor. [0026] Moreover, when the lateral part 134 of the floating gate pattern is oxidized, an active region is partially covered with the-oxidized lateral part 134, as partially shown in FIG. 12B. In the etch-back for forming the spacer oxide layer 115 of FIG. 5, the oxidized lateral part 134 is removed to expose the substrate 100 adjacent to the floating gate pattern 131. When the floating gate pattern 131 is etched for exposing a source region, the exposed substrate 100 is etched. [0027] As a result, in FIG. 13 taken along a line C-C of FIG. 3, a substrate 20 contacted with both edges of the source region 110 is removed to form grooves 161, which is called a pitting phenomenon. If implantation of ions into the common source region 110 is not sufficiently deep, a common source line part filling the groove 161 is in direct contact with a neighboring substrate 100 to cause a leakage current. SUMMARY OF THE INVENTION [0028] An object of the invention is to provide a method of forming a split gate type flash memory where a tip is formed with an acute angle. [0029] Another object of the invention is to provide a method of forming a split gate type flash memory that prevents a gate insulating layer below a floating gate from becoming thick. [0030] Still another object of the invention is to provide a split gate type flash memory that prevents a pitting phenomenon and a leakage current in a source region. [0031] The present invention provides a method of forming a split gate type flash memory. The invention comprises exposing a floating gate layer between silicon nitride patterns. A conductive layer spacer is formed on a sidewall of the silicon nitride pattern, and subsequent processes are carried out. In the flash memory, the conductive layer spacer forms a tip of the floating gate. Conventionally, the exposed floating gate layer is oxidized to form a bird's beak. This part is anisotropically etched to a tunneling tip of the floating gate. However, in this invention, a spacer is formed on the sidewall of the silicon nitride pattern to form a tunneling tip over the floating gate layer. [0032] According to an aspect of the invention, in a method of forming a split gate type flash memory, a tunneling gate insulating layer and a first conductive layer are formed on a substrate. An auxiliary layer pattern is formed on the first conductive layer. The auxiliary layer pattern includes a linear gap along a first direction, and has an etch selectivity with respect to the first conductive layer. A second conductive layer is conformally stacked and etched back to form a second conductive layer spacer on a sidewall of the auxiliary layer pattern. The second conductive layer spacer is coupled to the first conductive layer. A first insulating material layer is conformally stacked on the second conductive layer spacer. The first insulating material layer has an etch selectivity with respect to the first conductive layer and the auxiliary layer. The first insulating material layer is anisotropically etched back to form a first spacer so that the linear gap is partially filled and the first conductive layer is exposed to the center of the linear gap. [0033] In one embodiment, the first and second conductive layers include polysilicon. The auxiliary layer includes silicon nitride. The first insulating material layer includes CVD oxide. [0034] In the present invention, a trench type device isolation layer is generally formed after stacking the tunneling gate insulating layer and the first conductive layer. In this case, a second conductive layer pattern is formed, and then a surface thereof is oxidized. [0035] Alternatively, the device isolation layer may be formed before formation of the tunneling gate insulating layer. If the first conductive layer is formed after formation of the device isolation layer, the first conductive layer is patterned. In the case where the first conductive layer is patterned, the first conductive layer and the second conductive layer spacer are removed along a second direction across the first direction. Thus, isolation is clearly accomplished between neighboring floating gates. [0036] As described above, a second conductive layer spacer is formed when a first conductive layer is exposed between auxiliary layer patterns. Alternatively, a surface of the first conductive layer for forming a bird's beak is first oxidized. After removing an oxidized part of the first conductive layer, the second conductive layer spacer is formed to strengthen the tip. Preferably, the surface of the first conductive layer is oxidized after forming the second conductive layer spacer. [0037] Processes following formation of the first spacer may be the same as those in a conventional method of forming a split gate type flash memory. That is, using the first spacer and the auxiliary layer pattern as an etch mask, the first conductive layer is etched to be removed. Using the first spacer and the auxiliary layer pattern as an ion implanting mask, impurities are implanted to form a source region at a central substrate of the linear gap. A conductive layer is stacked and planarized to form a common source line coupled to the source region. After the auxiliary layer pattern is etched and removed, the first conductive layer below the auxiliary layer pattern is anisotropically etched and removed to form a floating gate. The floating gate includes a first conductive layer remaining below the fist spacer and a second conductive layer spacer. A fourth conductive layer pattern, which is contacted with a sidewall of the first spacer exposed by removing the auxiliary layer pattern, is formed to constitute a wordline. As a subsequent process, impurities are implanted into a drain region. In addition, before formation of the drain region, a second spacer may be formed on a sidewall of the wordline. The second spacer is made of a second insulating material such as, for example, silicon nitride. [0038] In order to form the wordline, a fourth conductive layer is conformally stacked. A second auxiliary layer is conformally stacked on the fourth conductive layer. An entire surface of the substrate is planarized to be upper than the fourth conductive layer. The exposed common source line and a surface of the fourth conductive layer are thermally oxidized to form an oxide layer. Using the oxide layer as an etch mask, the second auxiliary layer and the fourth conductive layer are anisotropically etched. The fourth and third conductive layers are made of polysilicon. The second conductive layer includes silicon nitride or silicon oxynitride.
BRIEF DESCRIPTION OF THE DRAWINGS [0039] The foregoing and other objects, features and advantages of the invention will be apparent from the more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. [0040]FIG. 1 and FIG. 2 are cross-sectional views illustrating programming and erasing methods performed in a cell transistor of a split gate type non-volatile memory device. [0041]FIG. 3 is a top plan view of a layout where a transistor device is constructed in a cell region of a conventional split gate type flash memory. [0042]FIG. 4 through FIG. 11 are cross-sectional views, taken along a line A-A of FIG. 3, showing partial steps of forming the layout shown in FIG. 3. [0043]FIG. 12A and FIG. 12B are cross-sectional views, taken along a line B-B of FIG. 3, for illustrating drawbacks of the prior art. [0044]FIG. 13 is a cross-sectional view, taken along a line C-C of FIG. 3 in the step of FIG. 5, for illustrating drawbacks of the prior art. [0045]FIG. 14A through FIG. 17B are cross-sectional views showing the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS [0046]FIG. 14A through FIG. 17B are cross-sectional views illustrating the present invention. FIGS. 14A, 15A, 16A and 17A are analogous to cross sections taken along line A-A of FIG. 3. FIGS. 14B, 15B, 16B and 17B are analogous to cross sections taken along line C-C of FIG. 3. Referring to FIGS. 14A and 14B, a substrate 201 is thermally oxidized to form a tunneling gate insulating layer 203 thereon to a thickness of 50-100 angstroms. A first conductive layer 205 is formed on the tunneling gate insulating layer 203. The first conductive layer 205 is made of polysilicon to a thickness of 400 angstroms. The first conductive layer 205 is patterned to form a trench type device isolation layer at the substrate 201. Similar to the case of FIG. 1, an active region is formed along one direction over the substrate 201. An active region 101 is formed across a device isolation layer 103 or a field oxide layer. The tunneling gate insulating layer 203 and the first conductive layer pattern 205 sequentially cover the active region. After formation of an etch-stop layer pattern used for forming the device isolation layer 103, an auxiliary layer is formed on an entire surface of the substrate 201. The auxiliary layer is made of silicon nitride to a thickness of 3000-4000 angstroms. The auxiliary layer is patterned to form an auxiliary layer pattern 207 having a gap along a first direction that is perpendicular to the one direction. In this case, the first conductive layer pattern 205 covers an active region exposed by the gap, and the device isolation layer 103 is slightly etched in a cleaning process or the like to be nearly even with the substrate 201. [0047] Referring to FIGS. 15A and 15B, a second conductive layer is conformally stacked on an entire surface of the substrate 201. The second conductive layer is made of polysilicon to a thickness of 200-300 angstroms. Before formation of the second conductive layer, a thermal oxide layer may be formed on the first conductive layer pattern 205 that is already exposed by thermally oxidizing the substrate 201. After causing a bird's beak at a boundary of the auxiliary layer pattern 207, the thermal oxide layer may be removed. The second conductive layer is anisotropically etched back to a second conductive layer spacer 209 on a sidewall of the auxiliary layer pattern 207. A spacer 211 is also formed at a step between the first conductive layer pattern 205 and the device isolation layer 103. Preferably, a height of the second conductive layer spacer 209 is lowered by reducing an etching anisotropy. [0048] Referring to FIGS. 16A and 16B, the structure, where the second conductive layer spacer 209 is formed, is thermally oxidized to form a thermal oxide layer 215 on the second conductive layer spacer 209 and the first conductive layer pattern 205. In this case, as shown in FIG. 16A, a contacted part of the spacer 209 with the auxiliary layer pattern 207 and a first conductive layer pattern 205′, i.e., an inner part of the spacer 209 is not thermally oxidized and remains as a conductive layer. Thus, it is possible to form a sharp tip of a later-completed floating gate. A spacer 211 of FIG. 15B serves to prevent oxygen from diffusing into a substrate of an active region during the thermal oxidation, as shown in FIG. 15B. The spacer 211 is almost oxidized itself, but fairly suppresses oxidation of a substrate and the first conductive layer pattern 205′. As a result, the tunneling gate insulating layer 203 around the device isolation layer 103 does not become thick. Moreover, a sidewall of the first conductive layer pattern 205 is oxidized and removed in a subsequent process to prevent a pitting phenomenon from occurring at both sides of a source region. [0049] Although a second conductive layer spacer is formed on a bottom sidewall of an auxiliary layer to remain in a device isolation layer region, it is almost oxidized in a subsequent thermal oxidation process. Therefore, interconnection of the floating gates can be prevented. Particularly, in an embodiment where a tunneling gate insulating layer and a first conductive layer are formed after formation of a device isolation layer, a second conductive layer spacer is formed, and then a patterning process is carried out to remove the first and second conductive layer patterns over the device isolation layer. As a result, the interconnection of the floating gates is not as a central problem. [0050]FIG. 17A and FIG. 17B are flow diagrams showing the post steps of forming a split gate type flash memory. Except a floating gate tip 219, the shapes are the same as those in FIG. 5. [0051] The subsequent steps may also be the same as those in FIG. 6 through FIG. 11, and will be carried out without changes except the tip of the floating gate. [0052] While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6716699 *Jan 29, 2003Apr 6, 2004Samsung Electronics Co., Ltd.Method for manufacturing flash memory deviceUS6974748 *Aug 18, 2004Dec 13, 2005Samsung Electronics Co., Ltd.Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor deviceUS7375391Oct 11, 2005May 20, 2008Samsung Electronics Co., Ltd.Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor deviceUS7906418 *Dec 3, 2003Mar 15, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor device having substantially planar contacts and bodyUS8207034 *Jul 26, 2010Jun 26, 2012Renesas Electronics CorporationSemiconductor memory device and method of manufacturing semiconductor memory deviceUS8241975 *Aug 4, 2011Aug 14, 2012National Semiconductor CorporationSystem and method for providing low voltage high density multi-bit storage flash memoryUS20110037114 *Jul 26, 2010Feb 17, 2011Renesas Electronics CorporationSemiconductor memory device and method of manufacturing semiconductor memory deviceUS20110287596 *Aug 4, 2011Nov 24, 2011National Semiconductor CorporationSystem and method for providing low voltage high density multi-bit storage flash memory* Cited by examinerClassifications U.S. Classification438/257, 257/E21.682, 257/E21.209, 257/E27.103International ClassificationH01L27/115, H01L21/8247, H01L21/28, H01L29/792, H01L29/788Cooperative ClassificationH01L21/28273, H01L27/11521, H01L27/11519, H01L27/115European ClassificationH01L21/28F, H01L27/115, H01L27/115F2, H01L27/115F4Legal EventsDateCodeEventDescriptionSep 21, 2011FPAYFee paymentYear of fee payment: 8Sep 20, 2007FPAYFee paymentYear of fee payment: 4May 31, 2005CCCertificate of correctionOct 22, 2002ASAssignmentOwner name: SAMSUNG ELECTRONICS, CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHO, MIN-SOO;KIM, DONG-JUN;KIM, JIN-WOO;REEL/FRAME:013418/0275;SIGNING DATES FROM 20020905 TO 20020920RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services