Source: http://www.google.de/patents/US8227848?hl=de
Timestamp: 2013-05-24 23:42:02
Document Index: 508682054

Matched Legal Cases: ['Application No. 2005', 'arTW383494', 'Application No. 11150568', 'Application No. 06', 'Application No. 2005', 'Application No. 06001359', 'Application No. 2005', 'Application No. 095102823']

Patent US8227848 - Semiconductor device - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr » Erweiterte Patentsuche | Webprotokoll | Anmelden Erweiterte Patentsuche PatenteA substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film...http://www.google.de/patents/US8227848?utm_source=gb-gplus-sharePatent US8227848 - Semiconductor device Ver�ffentlichungsnummerUS8227848 B2PublikationstypErteilung Anmeldenummer12/461,136 Ver�ffentlichungsdatum24. Juli 2012Eingetragen3. Aug. 2009 Priorit�tsdatum29. Sept. 2005Auch ver�ffentlicht unterCN1941371ACN100495707CEP1770764A2EP1770764A3EP2302663A2EP2302663A3US7586143US20070069384US20090294905US20120175736 ErfinderKenichi WatanabeUrspr�nglich Bevollm�chtigterFujitsu Semiconductor Limited US-Klassifikation257/303257/758257/751Internationale KlassifikationH01L27/108 UnternehmensklassifikationH01L23/5226H01L23/5223H01L28/40H01L28/60 Europ�ische KlassifikationH01L28/40H01L28/60H01L23/522EH01L23/522C4ReferenzenPatentzitate (44)Nichtpatentzitate (6)Externe LinksUSPTO USPTO-Zuordnung EspacenetSemiconductor deviceUS 8227848 B2 Zusammenfassung A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1. Zeichnungen(68) Anspr�che
a second metal layer embedded into the hole covered with the first metal layer;
a third metal layer formed on the interlayer insulating film and connected to the first metal layer and the second metal layer forming a lower electrode of a capacitor;
a dielectric insulating film formed on the third metal layer; and
a second wiring layer formed on the dielectric insulating film forming an upper electrode of the capacitor having the dielectric insulating film pinched between the lower electrode and the upper electrode. Beschreibung
CROSS-REFERENCE TO RELATED APPLICATION This application is a divisional application of Ser. No. 11/339,701, filed Jan. 26, 2006 which is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-285223, filed Sep. 29, 2005, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION The invention relates to a semiconductor device having a MIM (Metal-Insulator-Metal) structure.
[Patent document 1] Japanese Patent Application Laid-Open Publication No. 2001-237375 [Patent document 2] Japanese Patent Application Laid-Open Publication No. 2003-264235 [Patent document 3] Japanese Patent Application Laid-Open Publication No. 2004-63990 SUMMARY OF THE INVENTION The technologies described above made a variety of proposals for assembling the MIM structure and the Cu wiring into the semiconductor device. There was not necessarily, however, made sufficient consideration for reducing the parasitic resistance and the parasitic capacitance in a structural aspect. It is an object of the invention to provide a technology capable of further reducing the parasitic resistance and the parasitic capacitance than by the prior arts and improving a high-frequency characteristic.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing an example of a basic structure of a semiconductor device;
DETAILED DESCRIPTION OF THE INVENTION A semiconductor device according to a best mode (which will hereinafter be termed an embodiment) for carrying out the invention will hereinafter be described with reference to the drawings. A configuration of the following embodiment is an exemplification, and the invention is not limited to the configuration of the embodiment.
As shown in FIG. 1, the MIM structure 360 is constructed of a 3-layered structure such as, from the upper layer, titan nitride (TiN)/silicon oxide film (SiO2)/titan nitride (TiN), and a layer of silicon nitride (SiN) or silicon carbide (SiC) is further formed over the upper layer thereof.
Moreover, the silicon oxide film 335/the silicon nitride film 334/the interlayer insulating film 333 are etched till the silicon nitride film 331 on the metal wiring 311 is exposed, and the resist is peeled off. Hereat, the hole 337B at the upper portion of the upper electrode stops in a way that bears etching-over by SiN on the TiN film corresponding to the upper electrode (the SiN film is previously formed properly relatively thick). The hole 337A at the upper portion of the lower electrode stops due to a selection ratio depending on a difference in material on the lower electrode (TiN).
Subsequently, a resin (a material that does not cause mixing with the subsequence resist) is coated over inside the holes 337A-337C, the resin remains only within the holes 337A-337C by dissolution, and a mask pattern corresponding to a wiring layer 336 (the trench 339) is formed by the photoresist (the mask employed for this pattern formation will hereinafter be called, for example, Mx+1L in the embodiment). On this occasion, a mark pattern, which will become an alignment mark on the layout within the pre-formed hole pattern, is formed beforehand. When forming the wiring pattern, the alignment is conducted by utilizing the stepped portion of the mark pattern, whereby the hole pattern (the layer including the holes 337A-337C) can be precisely aligned with the wiring pattern.
Moreover, a diffusion preventive film 353, a metal layer 351 (Al(Cu)) and a diffusion preventive film 352 are sequentially formed. Then, the resist for forming the aluminum wiring 340 is subjected to coating, exposing and developing. Hereat, a stepped portion (a step pattern preset in the mask Mx+1C) formed along with the formations of the holes 347A-347C is employed as an alignment mark for the alignment with the base. Thereafter, the aluminum wiring 340 is formed by the RIE.
Further, the alignment between the metal wiring layer by Mx+1L and the contact layer designated by Mx+1C, involves making use of a stepped portion formed in the interlayer insulating film on the Damascene wiring. This stepped portion is formed when forming the contact layer designated by Mx+1C.
First Embodiment The semiconductor device according to a first embodiment of the invention will hereinafter be described with reference to the drawings in FIGS. 4A through 16A. In the semiconductor device, the metal (Al) wiring and the plug layer of tungsten are formed on the upper layer of the Damascene structure, and the MIM elements are formed in a way that decreases the addition of the number of the processes to the greatest possible degree. The processes of manufacturing the semiconductor device will be explained.
Herein, FIGS. 4A-15B include pairs of drawings as FIGS. 4A and 4B are paired. Throughout the drawings, FIG. nA (n=4 through 15) show the structures of the MIM area and of the normal area on one sheet of semiconductor substrate. Further, FIG. nB (n=4 through 15) show the structures of the mark areas formed in other areas on the same semiconductor substrate. Herein, the MIM area represents an area where the MIM structure is built up, the normal area represents an area where the substantial elements or wirings of the semiconductor device are formed, and the mark area represents an area where the alignment mark for the alignment is formed. FIG. nB, however, illustrate basically the same processes as the processes shown in the drawings in FIG. nA.
FIGS. 16A through 16C are plan views with respect to the sectional structure built up by the processes explained in the first embodiment. In FIGS. 16A through 16C, the solid lines represent patterns of a barrier metal film 114, a metal layer 115 and a barrier metal film 116, which include the upper electrode P1. Further, the dotted line indicates a pattern of a dielectric insulating film 135, a one-dotted chain line represents the glue layer 112 serving as the lower electrode, the solid square lines each containing a cross-line represent hole patterns (including trenches and wide trenches each filled with a metal 113 such as tungsten, thus forming a plug layer 113A), and the elongate dotted line indicates a metal layer 111 (the Damascene wiring 111A). An X1-X2 portion in FIG. 16A corresponds to the sectional view in FIG. 15A. Similarly, a Y1-Y2 portion in FIG. 16B corresponds to the sectional view in FIG. 15B, and a Z1-Z2 portion in FIG. 16C corresponds to the sectional view in FIG. 15C.
As shown in FIG. 16A, the metal layer 111 (the Damascene wiring 111A) is connected via the plug layer 113A to the upper electrode P1 and the lower electrode (the glue layer 112). An example in FIG. 16A is that the upper electrode P1 embraces the area of the entire capacitance area (the dielectric insulating film 135) within the plane area, and, on the further internal side, the glue layer 112 as the lower electrode is formed. On the other hand, in the normal area, the normal wirings (the metal wirings 114 through 116 and the Damascene wiring 111A) functioning as a circuit area is formed.
Second Embodiment A second embodiment of the invention will hereinafter be described with reference to the drawings in FIGS. 17A through 18B. The first embodiment takes the construction, wherein, as shown in FIG. 16A, the plane area, on which the upper electrode P1 is projected towards the lower layer, embraces the plane area of the pattern of the dielectric insulating film 135. Conversely, however, such a construction is allowable that the plane area of the upper electrode P1 is partially included in the area of the dielectric insulating film 135 or the area of the lower electrode (the glue layer 112). Namely, the construction may be taken, wherein the plane area of the dielectric insulating film 135 or the plane area of the lower electrode (the glue layer 112) embraces at least partially the plane area of the upper electrode P1. The second embodiment exemplifies this type of semiconductor device. Other configurations and operations of the semiconductor device in the second embodiment are the same as those in the first embodiment. This being the case, the same components are marked with the same numerals and symbols, and their explanations are omitted.
FIG. 18A shows a plan view of the semiconductor device configuring (corresponding to) the sectional view in FIG. 17A. On the plan view in FIG. 18A, part of the upper electrode P1 extends over the existence of the dielectric insulating film 135 upwards in the plan view in FIG. 18A. This is because of forming an overlapping area in which the upper electrode P1 is overlapped with an extending area of the Damascene wiring 11A. This extending area P1A is required for forming the overlapping area between the upper electrode P1 and the Damascene wiring 111A in such a case that the upper electrode P1 is formed on the uppermost layer.
Third Embodiment A third embodiment of the invention will hereinafter be described with reference to the drawings in FIGS. 19 through 23. In the first embodiment and the second embodiment, the hole 112A configuring the plug layer 113A takes the rectangular shape roughly similar to a square shape in its section. The sectional shape of the hole 112A is not, however, necessarily limited to such shapes. The third embodiment will give a description of a modified example of the sectional shape of the hole 112A of the plug layer 113A for connecting the Damascene wiring to the upper/lower electrodes and the normal wiring area. Other configurations and operations in the third embodiment are the same as those in the cases of the first embodiment and the second embodiment. This being the case, the same components as those in the first embodiment and the second embodiment are marked with the same numerals and symbols, and their explanations are omitted.
FIG. 21 shows a construction, wherein the width of the Damascene wiring area in FIG. 20 remains widened, and there is increased the number of the holes 112A of the plug layer 113A connecting the lower electrode (the glue layer 112) to the Damascene wiring 111A. With this construction also, in the same way as in FIGS. 19 and 20, it is possible to reduce the resistance parasitic to the lower electrode, i.e., the resistance between the glue layer 112 forming the lower electrode and the metal layer 113 and the connecting resistance to the Damascene wiring 111A from the lower electrode.
Fourth Embodiment The semiconductor device according to a fourth embodiment of the invention will hereinafter be described with reference to the drawings in FIGS. 24 through 26. In the first through third embodiments, the plug layer 113A leading to the Damascene wiring 111A from the lower electrode (the glue layer 112, the metal layer 113) is basically formed under the lower electrode. Further, the hole 112A of the plug layer 113A is disposed on the underside (the plane area on the interlayer insulating film where the dielectric insulating film 135 is projected towards the lower layer) of the dielectric insulating film 135 and on the underside (the plane area on the interlayer insulating film where the upper electrode P1 is projected towards the lower layer) of the upper electrode P1.
Fifth Embodiment The semiconductor device according to a fifth embodiment of the invention will hereinafter be described with reference to FIG. 27. In the fifth embodiment, the pattern layout condition of the MIM structure 160 and the plug layer 113A is the same as in the fourth embodiment. The fifth embodiment will, however, exemplify the semiconductor device in which the plural dielectric insulating films each sandwiched in between the upper electrode P1 and the lower electrode (the glue layer 112 and the metal layer 113) are stacked.
e0: the vaccum dielectric constant 8.854�10−10 [F/m]
Sixth Embodiment The semiconductor device according to a sixth embodiment of the invention will hereinafter be described with reference to FIG. 28. In the fifth embodiment, the stacked structure including the first dielectric insulating film 140 and the second dielectric insulating film 141 is formed on the dielectric insulating layer. The sixth embodiment will exemplify, as a modified example thereof, the semiconductor device in which an edge of the dielectric insulating layer is partially aligned with an edge of the upper electrode P1. Other configurations and operations in the sixth embodiment are the same as those in the fifth embodiment. This being the case, the same components as those in the fifth embodiment are marked with the same numerals and symbols, and their explanations are omitted.
Seventh Embodiment A seventh embodiment of the invention will hereinafter be described with reference to the drawings in FIGS. 29 through 33. The fifth embodiment and the sixth embodiment each have exemplified the semiconductor device in which the dielectric insulating films are stacked. The seventh embodiment will exemplify a structure forming method capable of increasing the insulating capacitance of the MIM area by further decreasing the thickness of the stacked dielectric insulating films. Namely, in the seventh embodiment, the second dielectric insulating film is used as a dummy insulating film. The dummy connotes the insulating film which, though existing as an etching mask in the pattern formation process, disappears after the pattern formation but does not become the component of the MIM elements. As a result, the dielectric insulating layer is composed of the insulating films other than the dummy insulating film.
Eighth Embodiment The semiconductor device according to an eighth embodiment of the invention will hereinafter be described with reference to the drawings in FIGS. 34 through 39. The respective embodiments discussed so far have given the descriptions about the basic processes of the MIM area and of the normal area, the planar layout of the upper electrode and the lower electrode, the planar layout of the hole pattern, the detailed method of forming the dielectric insulating film and the modified examples thereof. The eighth embodiment will exemplify a technological modification about how the parasitic resistance of the lower electrode itself is reduced. Other configurations and operations are the same as those in the first through seventh embodiments. This being the case, the same components as those in the embodiments given above are marked with the same numerals and symbols, and their explanations are omitted.
Other Modified Examples Shown are other planar layouts. FIG. 42 illustrates the semiconductor device taking such a structure that the upper electrode shape in FIG. 25 remains substantially as it is, the Damascene wiring is arranged in the form along the periphery of the upper electrode P1 and is overlapped with only the upper electrode leading area (the extended area P1A) of the upper electrode P1, and none of the wiring is arranged under the upper electrode P1. The hole pattern 112A is not disposed under the overlapping area between the upper electrode P1 and the lower electrode (the glue layer 112). Because of the structure of not disposing the hole pattern in the overlapping area between the lower electrode and the upper electrode P1, there is the structure having no occurrence of the stepped portion in the capacitance element area in the MIM area.
Note that in each of the cases in FIGS. 45 and 46, a roughly U-shaped (a C- or L-and-I combination shaped) opening 170 is formed on the upper electrode P1. Further, the plug layer 113A for connecting the upper electrode P1 to the Damascene wiring 111A connects a protruded area 171 of the upper electrode P1, formed protruding into the opening 170, to the Damascene wiring 111A. Thus, the area size of the upper electrode P1 existing in the vicinity of the boundary of the MIM area can be reduced by providing the upper electrode P1 with the opening 170 and the protruded area 171. For instance, in the example in FIG. 45, the windows 135B of the dielectric insulating layer and the window 112B of the lower electrode, which configure the MIM area, are formed just under the opening 170. In the vicinity of such windows in the MIM area, the height (in the film thickness direction) of the upper electrode P1 might be different from the normal area where the MIM area is not formed. Namely the fluctuation of the height in the vicinity of MIM area might be caused by traversing the edge (boundary) of the area of the lower electrode and by traversing the edge (boundary) of the area of the dielectric insulating layer. The fluctuation of the height of the upper electrode P1 in the vicinity of MIM area affects the photo-lithography process. Thus there may be a probability that the line width of the upper electrode P1 (wirings) may fluctuate. Accordingly, in these areas, the characteristic of the capacitance element due to the MIM area is easy to fluctuate.
Other Effects of Embodiments FIG. 49 shows an alignment system using the alignment marks in the first through eighth embodiments. As shown in FIG. 49, in the construction of the semiconductor device illustrated in FIGS. 4A through 48, the mark 150 defined as the stepped portion when forming the hole 112A enables the alignment of the lower electrode (the mask CAP1) in the MIM area of the upper layer. Accordingly, as in FIGS. 1 through 3, the digging layer designated by CAL is not required to be formed by a separate mask, whereby the number of the masks and the number of the processes can be reduced.
OTHERS The disclosures of Japanese patent application No. JP2000-285223 filed on Sep. 29, 2005 including the specification, drawings and abstract are incorporated herein by reference.
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