Source: http://www.google.com/patents/US6167078?dq=6978253
Timestamp: 2013-12-13 19:37:37
Document Index: 669721188

Matched Legal Cases: ['ART. 3', 'ART. 4', 'ART 28', 'ART 44', 'ART 44', 'ART 28', 'ART 44', 'ART 44', 'ART 44', 'ART 44', 'ART 44']

Patent US6167078 - Conservation of power in a serial modem - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA serial modem (14) having a phase-locked loop (22), a central processing unit (20), a serial buffer (26) and a universal asynchronous receiver transmitter (UART) (28), wherein the serial buffer (26) and the UART (28) are connected to a host device (10) via an asynchronous serial interface (32). The...http://www.google.com/patents/US6167078?utm_source=gb-gplus-sharePatent US6167078 - Conservation of power in a serial modemAdvanced Patent SearchPublication numberUS6167078 APublication typeGrantApplication numberUS 09/050,285Publication dateDec 26, 2000Filing dateMar 30, 1998Priority dateMar 30, 1998Fee statusPaidAlso published asUS6301297Publication number050285, 09050285, US 6167078 A, US 6167078A, US-A-6167078, US6167078 A, US6167078AInventorsDavid W. RussoOriginal AssigneeMotorolaExport CitationBiBTeX, EndNote, RefManPatent Citations (3), Non-Patent Citations (1), Referenced by (12), Classifications (7), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetConservation of power in a serial modemUS 6167078 AAbstract A serial modem (14) having a phase-locked loop (22), a central processing unit (20), a serial buffer (26) and a universal asynchronous receiver transmitter (UART) (28), wherein the serial buffer (26) and the UART (28) are connected to a host device (10) via an asynchronous serial interface (32). The central processing unit (20) enters a sleep mode when data is not being received. A start bit s received at a predetermined baud rate via the asynchronous serial interface (32). An interrupt is activated to start a wake-up transition at the central processing unit (20) upon receipt of the start bit. A series of bits following the start bit is sampled and stored in the serial buffer (26) until the central processing unit (20) is enabled. After the central processing unit (20) is enabled, a remainder of the series of bits are sampled and stored at the UART (28).
I claim: 1. In a serial modem having a phase-locked loop, a central processing unit, a serial buffer and a universal asynchronous receiver transmitter (UART), wherein the serial buffer and the UART are connected to a host device via an asynchronous serial interface, a method for conserving power in the serial modem comprising:entering a sleep mode at the central processing unit when data is not being received; receiving a start bit at a predetermined baud rate via the asynchronous serial interface; activating an interrupt to start a wake-up transition at the central processing unit upon receipt of the start bit; and sampling and storing a series of bits following the start bit in the serial buffer until the central processing unit is enabled; and sampling and storing a remainder of the series of bits in the UART after the central Processing unit is enabled, wherein the UART samples the remainder of the series of bits at a clock speed of sixteen times the predetermined baud rate. 2. In a serial modem having a phase-locked loop, a central processing unit, a serial buffer and a universal asynchronous receiver transmitter (UART), wherein the serial buffer and the UART are connected to a host device via an asynchronous serial interface, a method for conserving power in the serial modem comprising:entering a sleep mode at the central processing unit when data is not being received; receiving a start bit at a predetermined baud rate via the asynchronous serial interface; activating an interrupt to start a wake-up transition at the central processing in unit upon receipt of the start bit; sampling and storing a series of bits following the start bit in the serial buffer until the central processing unit is enabled; sampling and storing a remainder of the series of bits in the UART after the central processing unit is enabled; and further comprising, at the central processing unit, extracting the series of bits stored in the serial buffer before extracting the remainder of the series of bits stored in the WART. 3. An apparatus for conserving power in a serial modem comprising:a low frequency oscillator; an asynchronous serial interface for receiving asynchronous data: a phase-locked loop coupled to the low-frequency oscillator; a central processing unit coupled to the phase-locked loop, a switch, having a first state and a second state, coupled to the asynchronous serial interface for receiving asynchronous data; a serial buffer having an interrupt logic component, wherein the serial buffer is coupled to the low-frequency oscillator, coupled to the asynchronous serial interface and couplable to the central processing unit via the interrupt logic component; a universal asynchronous receiver transmitter (UART) coupled to the central processing unit and to the switch when the switch is drawn in the second state; and a baud-rate generator coupled to both the phase-locked loop and the UART. 4. An apparatus for conserving power in a serial modem comprising:a low-frequency oscillator; an asynchronous serial interface for receiving asynchronous data; a phase-locked loop coupled to the low-frequency oscillator; a central processing unit coupled to the phase-locked loop, a switch, having a first state and a second state, coupled to the asynchronous serial interface for receiving asynchronous data; a serial buffer having an interrupt logic component, wherein the serial buffer is coupled to the low-frequency oscillator, coupled to the asynchronous serial interface and couplable to the central processing unit via the interrupt logic component; a universal asynchronous receiver transmitter (UART) coupled to the central processing unit and to the switch when the switch is drawn in the second state, wherein the serial buffer, the UART and the switch are combined into a dual mode receive UART, and wherein the dual mode receive UART comprises: a first shift register coupled to a delay clock and to the asynchronous serial interface; a second shift register coupled to the first shift register and to the delay clock; a clock generator coupled to a low frequency oscillator; a majority vote component coupled to the first and second shift registers and to the clock generator; a compare equal component coupled to the first and second shift registers and to the clock generator; a receive state machine coupled to the compare equal component, a baud rate generator and a control register; a third shift register coupable to the clock generator and coupable to the majority vote component; a memory component coupled to the third shift register and to the control register; an interrupt logic component coupled to the clock generator and the control register; and the control register coupled to the interrupt logic component, to the receive state machine and to the memory component. 5. A method of conserving power in a serial modem, wherein the serial modem comprises a central processing unit and a phase-locked loop, the method comprising:providing a dual mode receive universal asynchronous receiver transmitter (UART) having a receive clock, a first mode and a second mode; switching the receive clock to the first mode when the central processing unit is in a sleep state with the phase-locked loon being non operative; switching the receive clock to the second mode after the central processing unit enters an active state with the phase-locked loop operating with a stabilized frequency; and after the step of switching the receive clock to the first mode at the dual mode UART, waiting idly in the first mode until a start bit is received; activating an interrupt to the central processing until upon receipt of the start bit at a predetermined baud rate to start a wake-up transition at the central processing unit while operating in the first mode; and sampling and storing a series of bits following the start bit at two times the predetermined baud rate while operating in the first mode; and after the step of switching the received clock to the second mode, sampling and storing a remainder of the series of bits received at sixteen times the predetermined baud rate while operating in the second mode. Description
Referring to the figures, FIG. 1 illustrates a general block diagram according to the preferred embodiment of the present invention. As shown, an asynchronous serial interface 32 connects a host device 10 with a radio frequency modem 12, wherein the radio frequency modem 12 comprises a serial modem 14 and a radio 16. The radio 16 communicates to a wireless network 13. The wireless network 13 comprises any network which is capable of Supporting untethered computer communications. It is important to note that the present invention is applicable to any battery operated packet modem connected to a serial port, such as DataTAC�, Global System Mobile (GSM) packet radio systems, integrated Digital Enhanced Network (iDEN)� and ReFLEX� based serial modems manufactured by Motorola, Inc.
As shown in FIG. 3, the number of clock pulses and the timing of the clock pulses is determined by the baud rate configured within the control register 38. FIG. 3 depicts a timing diagram for operation of the serial buffer of FIG. 2, at two times ( second (bps)), when the serial buffer 26 receives the asynchronous bit stream. Operating the serial buffer 26 at a low clock speed (i.e., includes simple power savings of a lower frequency clock source and an optimal number of oscillators (e.g., one) which reduces the cost of the device and the ability to operate the CPU 20 in a low power sleep state. For example, the clock generator 36 begins searching for a start bit at rising edge 48. Rising edge 50 of the clock source is used to determine that a start edge transition occurred. The third falling clock edge 52 after the start edge transition is used to latch the received bit 0 into a serial shift register 40. The second falling edge is used thereafter. This continues until the pre-configured number of bits are loaded into the shift register 40. If the baud rate was 9,600 bps, as opposed to 19,200 bps, every fourth clock edge would be sampled.
As shown in FIG. 2, when the CPU 20 is functioning, the serial buffer 26 is disabled, switch 24 is closed and the asynchronous bit stream is directed back to the UART 28. Asynchronous serial ports (i.e., UARTs), however, are not normally run at very slow clock speeds. The industry standard is to use a clock operating at sixteen times ( clock operating at permit accurate bit level detection of the received symbol.
FIG. 4 illustrates a block diagram according to a second embodiment of the present invention. The second embodiment of the present invention embeds the above technique within a dual mode receive UART 44. The dual mode receive UART 44 replaces the serial buffer 26, the switch 24, and the industry standard UART 28 in FIG. 1. Thus, instead of operating as an industry standard UART when the CPU 20 is in a low power sleep state, the receive clock in the dual mode receive UART 44 is switched to the LFO 18 (i.e., receive UART 44 generates an interrupt to start a wake-up transition for the CPU 20 and the PLL 22. When the CPU 20 and the PLL 22 are operational, the CPU 20 signals the dual mode receive UART 44 to switch clock sources back to the x16 clock and the dual mode receive UART 44 operates as an industry standard UART.
In operation, switches 80 and 82 are in the drawn state and the dual mode receive UART 44 functions as an industry standard UART. The one-bit shift registers 71 and 72 and the compare equal component 76 sample the asynchronous bit stream in search of a start bit. When all three bit samples agree, the compare equal component 76 determines the acceptance of a valid start bit. Acceptance of a valid start bit signals the receive state machine 78 to generate proper timing clocks for the shift register 40. The majority vote component 74 is used to sample the receive bit multiple times at the perceived center of the bit to determine the most likely state of the bit to present to the shift register 40 (as described above in the first embodiment). When the CPU 20 wants to enable the power sleep state, it requests switches 80 and 82 to change state via the control register 38. Switching of the clocks (i.e., switches 80 and 82) has to be controlled in an intelligent manner as described above in the first embodiment. The clocks cannot be switched in the middle of receiving characters. The receive state machine 78 has to wait until the an idle period on the asynchronous serial interface 32 such that there is no active character in process before performing the switch over. Once the clocks the data into the shift register 40 at a best time and triggers an interrupt to the PLL 22 to activate the CPU 20.
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