Source: https://patents.google.com/patent/US20030014082
Timestamp: 2018-02-24 04:49:14
Document Index: 619854446

Matched Legal Cases: ['art 264', 'art 264', 'art 264', 'art 264', 'art 640', 'art 640']

US20030014082A1 - Power dissipation reduction in medical devices using adiabatic logic - Google Patents
US20030014082A1
US20030014082A1 US10136776 US13677602A US2003014082A1 US 20030014082 A1 US20030014082 A1 US 20030014082A1 US 10136776 US10136776 US 10136776 US 13677602 A US13677602 A US 13677602A US 2003014082 A1 US2003014082 A1 US 2003014082A1
US10136776
This application is a Continuation-In-Part application (CIP). This application is based upon and claims priority from U.S. patent application Ser. No. 09/181,460 for “Power Consumption Reduction in Medical Devices Employing Multiple Digital Signal Processors,” to Thompson, filed Oct. 28, 1998, hereby incorporated by reference in its entirety.
The power consumption of CMOS circuits consists generally of two power consumption factors, namely “dynamic” power consumption and “static” power consumption. Static power consumption is due to current leakage as the quiescent current of such circuits is zero. Dynamic power consumption is the dominant factor of power consumption for CMOS technology. Dynamic power consumption is basically due to the current required to charge internal and load capacitances during switching, i.e., the charging. and discharging of such capacitances. The dynamic power (P) is equal to: CVDD 2F, where C is the nodal capacitance, F is the clock or switching frequency, and VDD is the supply voltage for the CMOS circuit. As can be seen from the formula for calculating dynamic power (P), such dynamic power consumption of CMOS circuits is proportional to the square of the supply voltage (VDD). In addition, the dynamic power (P) is proportional to the nodal capacitance (C) and the switching or clock frequency (F).
In accordance with the formula for dynamic power consumption, it is effective conventionally in CMOS integrated circuit designs to scale down the supply voltage for an entire device (e.g., hybrid) or integrated circuit (IC), i.e., operate .the circuit at low supply voltages, to reduce power consumption for such designs. For example, in the Medtronic Spectrax®, circa 1979, IC circuitry is powered by one LiI cell versus two cells. This reduced the supply voltage to 2.8 volts from 5.6 volts, thus reducing overhead current. Voltages required to be greater than 2.8 volts are generated by a voltage doubler, or alternatively by a charge pump (e.g., output pacing pulses). Further, for example, in the Medtronic Symbios®, circa 1983, the logic circuitry is powered by a voltage regulator controlling the IC supply voltage to a “sum of thresholds” supply. This regulator provides a supply to the IC (i.e., VDD) of several hundred millivolts above the sum of the n-channel and p-channel thresholds of the CMOS transistors making up the IC. This regulator is self-calibrating regarding manufacturing variations of the transistor thresholds.
Other devices reduce power consumption in other varied manners. For example, various device designs shutdown analog blocks and/or shut-off clocks to logic blocks not used at particular times, thereby reducing power. Further, for example, microprocessor-based devices historically use a “burst clock” design to operate a microprocessor at a very high clock rate (e.g., generally 500-1000 Kilohertz (kHz)), for relatively short periods of time to gain the benefit of a “duty cycle” to reduce average current drain. A much lower frequency clock (e.g., generally 32 kHz) is used for other circuitry and/or the processor when not in the high clock rate mode, i.e., burst clock mode. Many known processor-based implanted devices utilize the burst clock technique. For example, implanted devices available from Medtronic, Vitatron, Biotronic, ELA, Intermedics, Pacesetters, In Control, Cordis, CPI, etc., utilize burst clock techniques. A few illustrative examples which describe the use of a burst clock are provided in U.S. Pat. No. 4,561,442 to Vollmann et al., entitled “Implantable Cardiac Pacer With Discontinuous Microprocessor Programmable Anti Tachycardia Mechanisms and Patient Data Telemetry,” issued Dec. 31, 1985; U.S. Pat. No. 5,022,395 to Russie, entitled “Implantable Cardiac Device With Dual Clock Control of Microprocessor,” issued Jun. 11, 1991; U.S. Pat. No. 5,388,578 to Yomtov et al., entitled “Improved Electrode System For Use With An Implantable Cardiac Patient Monitor,” issued Feb. 14, 1995; and U.S. Pat. No. 5,154,170 to Bennett et al., entitled “Optimization for Rate Responsive Cardiac Pacemaker,” issued Oct. 13, 1992.
[0008]FIG. 1 represents a graphical illustration of energy/delay versus supply voltage for CMOS circuits such as a CMOS inverter 10 shown in FIG. 2 for illustrative purposes. The inverter 10 is provided with a supply voltage, VDD, which is connected to the source of a PMOS field effect transistor (FET) 12. PMOS FET 12 has its drain connected to the drain of an NMOS FET 14 whose source is connected to ground. In this configuration, an input Vi applied to both the gates of FETs 12, 14 is inverted to provide output Vo. Simply stated, with each clock cycle or logic level change, the input Vi is inverted and produces output Vo.
4,561,442 Vollmann et al. 31 Dec. 1985
4,791,318 Lewis et al. 13 Dec. 1988
5,154,170 Bennett et al. 13 Oct. 1992
5,185,535 Farbetal. 09 Feb. 1993
5,388,578 Yomtov et al. 14 Feb. 1995
5,610,083 Chanetal. 11 March 1997
In comparison to known techniques for reducing power consumption in circuit designs, various embodiments of the present invention may provide one or more of the following advantages: (a) reduced power consumption through the use of adiabatic logic; (b) reduced power consumption due to a decreased clock frequency for circuit designs; (c) increased longevity of circuits, particularly implantable device circuitry; (d) reduced product size and minimization of static leakage current losses, i.e., static power consumption; and (e) multi-processor designs, DSP designs, and high performance processing designs with additional features/function opportunities due to the ability to reduce power dissipation associated with chip-to-chip and intrachip data and/or address bus signals.
[0016]FIG. 1 is a graphical illustration showing energy/delay versus supply voltage for CMOS circuit operation.
[0017]FIG. 2 shows a prior art CMOS inverter that is used as a building block in many CMOS circuit designs.
[0018]FIG. 3 is a block diagram of a just-in-time clocking system according to the present invention.
[0020]FIG. 5 is a block diagram illustration of a multiple supply voltage system according to the present invention.
[0021]FIG. 6 is a block diagram illustrating a variable supply voltage system according to the present invention.
[0022]FIG. 7 is a block diagram of clock controlled processing circuitry according to the present invention.
[0023]FIG. 8 is a diagram illustrating an implantable medical device in a body.
[0024]FIG. 9 is a block diagram of the circuitry of a pacemaker for use in illustrating one or more embodiments of the present invention.
[0025]FIG. 10 is a schematic block diagram of an implantable pacemaker/cardioverter/defibrillator (PCD) for use in illustrating one or more embodiments of the present invention.
[0026]FIG. 11 is a schematic block diagram illustrating a variable clock/variable supply voltage digital signal processing system according to the present invention.
[0027]FIG. 12 is a schematic block diagram illustrating an implantable medical device according to the present invention.
[0028]FIG. 13 is a circuit diagram illustrating an embodiment of the present invention utilizing adiabatic logic for use within the implantable medical device.
[0029]FIGS. 14A and 14B are graphs representing voltage versus time for various embodiments of the present invention.
[0030]FIG. 15 is a circuit diagram illustrating the embodiment of the present invention shown in FIG. 13 including numerous transistors.
[0031]FIG. 16 is a circuit diagram illustrating another embodiment of the present invention utilizing adiabatic logic within the implantable medical device.
[0032]FIG. 17 is a circuit diagram illustrating the embodiment of the present invention shown in FIG. 16 including numerous transistors.
[0033]FIG. 18 is a circuit diagram illustrating yet another embodiment of the present invention utilizing adiabatic logic within the implantable medical device.
[0034]FIG. 19 is a graph representing voltage versus time for the circuit shown in FIG. 18.
[0035]FIG. 20 is a circuit diagram illustration yet another embodiment of the present invention utilizing adiabatic logic within the implantable medical device.
[0037]FIG. 3 shows a general block diagram of a just-in-time clock system 30. The just-in-time clock system 30 includes an integrated circuit 32 and a clock source 34. The integrated circuit 32 includes a plurality of circuits C1-Cn. Each circuit when operable is capable of performing one or more circuit functions. A function is defined as any operation performed on one or more inputs in a plurality of cycles resulting in an output. Generally, the functions performed by the various circuits C1-Cn are performed in a predetermined number of clock cycles. Clock source 34 is operable for providing clock signals at a plurality of clock frequencies generally shown as clock1-clockn.
With just-in-time clocking according to the present invention, as shown in FIG. 4A, substantially the entire time period x is used to perform the one or more functions, which are completed in n cycles. In other words, the clock frequency, e.g., one of clock1-clockn, for the circuit performing the one or more functions during the time period x is set such that the one or more functions are completed in the maximum time available for performing such functions, i.e., the clock frequency is at its lowest possible value. In other words, a lower frequency clock is used such that the one or more functions are performed just-in-time for other circuit or routine functionality to be performed. In such a just-in-time manner, the clock frequency used to control the performance of such functions by the particular CMOS circuitry is lowered resulting in reduced power consumption by the CMOS circuitry, e.g., according to the calculations of dynamic power, the lower frequency results in proportional power reduction. With the lowering of the clock frequency, the integrated circuit 32 including the various circuits C1-Cn can be designed to operate at a lower frequency, e.g., as opposed to burst frequency, and also at various other frequencies depending upon need.
[0045]FIG. 4C shows an illustrative timing example for processing circuitry, which performs multiple functions. For example, the cardiac cycle of a patient is represented in FIG. 4C as time period x. During time period 71, i.e., during a QRS complex of the cardiac cycle, high speed processing is performed at a high clock frequency relative to a lower clock frequency used to control operation of the processing circuitry during time period y. During the time period y, when the processing circuitry is operated at a lower clock frequency, such lower clock frequency may be set such that the functions performed during z cycles are performed in substantially the entire maximum time period available for such processing, i.e., time period y. Once again, a small remainder time period 75 of the cardiac cycle time period x may exist. Such time period may be, for example, in the range of about 1.0 millisecond to about 10.0 milliseconds when the cardiac cycle is in the range of about 400 milliseconds to about 1200 milliseconds.
[0046]FIG. 5 shows a general block diagram of a multiple supply voltage system 100 wherein one or more supply voltages are available and tailored for application to various circuits in an IC. The multiple supply voltage system 100 includes integrated circuit 102 and supply voltage source 106. Integrated circuit 102 includes circuits C1-Cn. Supply voltage source 106 is operable for providing a plurality of supply voltages V1-Vn. Each supply voltage from supply voltage source 106 is tailored to be applied to one or more circuits of circuits C1-Cn. As illustrated, supply voltage V1 is applied to circuit C1, supply voltage V2 is applied to circuit C2 and C3, and so forth.
[0054]FIG. 6 shows a general block diagram of a variable supply voltage/variable clock system 150 according to the present invention. The system 150 includes integrated circuit 152, clock source 156, supply voltage source 154, and clock/supply voltage interface 155. Supply voltage source 154 is operable for providing a plurality of supply voltages V1-Vn to a plurality of circuits C1-Cn of integrated circuit 152. Further, the clock source 156 of system 150 is operable for providing clock signals at a plurality of frequencies, clock1-clockn. The circuits C1-Cn are of a similar nature to those described with reference to FIG. 3, the clock source 156 is similar to the clock source 34 as described with reference to FIG. 3, and the supply voltage source 154 is similar to the supply voltage source 106 as described with reference to FIG. 5. However, in the variable supply voltage/variable clock system 150, a clock/voltage interface 155 is used to adjust the supply voltages V1-Vn applied to the circuits C1-Cn “on the fly” as required by specific timing functions required by the circuits C1-Cn.
[0057]FIG. 7 shows a general block diagram of a clock controlled processing system 200 according to the present invention. The clock controlled processing system 200 includes processor 202 (e.g., a CMOS microprocessor or CMOS digital signal processor), clock source 204, supply voltage source 206, voltage regulator 212, regulator interface 210, clock control 208, and optional back gate bias source 214. In a manner similar to that described with reference to FIG. 6, the supply voltage 206 applied to processor 202 is changed “on the fly” as required by specific circuit timing requirements.
[0063]FIG. 4C illustrates one embodiment of the clock control processing system 200. As shown therein, during the overall cardiac cycle of predetermined time period x, a high frequency is used for controlling operation of processor 202 during time period 71 of the cardiac cycle time period x, e.g., during processing of the QRS complex. Thereafter, a lower clock frequency is used during time period y for controlling operation of processor 202 to perform any of a number of other different functions, such as cardiac event/EMI differentiation functions. During operation of the processor 202 at the higher clock frequency during time period 71, a higher supply voltage from supply voltage source 206 is applied to the CMOS devices of processor 202. Likewise, during operation of the processor 202 at the relatively lower clock frequency, a lower supply voltage from supply voltage source 206 is applied to the CMOS devices of processor 202 during time period y of the overall cardiac cycle time period x.
[0065]FIG. 8 is a simplified diagram of an implantable medical device 260 for which the present invention is useful. The implantable device 260 is implanted in a body 250 near a human heart 264. The implanted medical device is connected to the heart by leads 262. In the case where the device 260 is a pacemaker, leads 262 are pacing and sensing leads to sense electrical signals attendant to the depolarization and repolarization of the heart 264 and provide pacing pulses in the vicinity of the distal ends thereof. Implantable medical device 260 may be any implantable cardiac pacemaker such as those disclosed in U.S. Pat. No. 5,158,078 to Bennett et al., U.S. Pat. No. 5,312,453 to Shelton et al., or U.S. Pat. No. 5,144,949 to Olson, all hereby incorporated herein by reference in their respective entireties and which can all be modified according to the present invention.
Alternatively, implantable medical device 260 may be an implantable nerve stimulator or muscle stimulator such as those disclosed in U.S. Pat. No. 5,199,428 to Obel et al., U.S. Pat. No. 5,207,218 to Carpentier et al., or U.S. Pat. No. 5,330,507 to Schwartz, or an implantable monitoring device such as that disclosed in U.S. Pat. No. 5,331,966 issued to Bennet et al., all of which are hereby incorporated by reference herein in their respective entireties. The present invention is believed to find wide application to any form of electrical device which uses CMOS circuit design and is believed to be particularly advantageous where low power is desired, particularly in implantable medical devices.
[0070]FIG. 9 shows a block diagram illustrating the components of a pacemaker device 300 in accordance with one embodiment of the present invention. Pacemaker device 300 has a microprocessor-based architecture. However, the illustrative pacemaker device 300 of FIG. 9 is only one exemplary embodiment of such devices and it will be understood that it could be implemented in any logic-based, custom integrated circuit architecture, if desired, as can any microprocessor-based system.
[0081]FIG. 10 is a functional schematic diagram from U.S. Pat. No. 5,447,519 to Peterson, which shows an implantable PCD 400 in which the present invention may usefully be practiced. This diagram is an illustration to be taken only as an exemplary type of device in which the invention may be embodied, and not as limiting to the scope of the present invention. Other implantable medical devices as previously described having functional organizations wherein the present invention may be useful may also be modified in accordance with the present invention. For example, the present invention is also believed to be useful in conjunction with implantable PCDs as disclosed in prior U.S. Pat. No. 4,548,209 to Wielders et al.; U.S. Pat. No. 4,693,253 to Adams et al.; U.S. Pat. No. 4,830,006 to Haluska et al.; and U.S. Pat. No. 4,949,730 to Pless et al.; all of which are incorporated herein by reference in their entireties.
The illustrative PCD device 400 is provided with six electrodes 401, 402, 404, 406, 408, and 410. For example, electrodes 401 and 402 may be a pair of closely-spaced electrodes positioned in the ventricle of the heart 264. Electrode 404 may correspond to a remote, indifferent electrode located on the housing of the implantable PCD 400. Electrodes 406, 408, and 410 may correspond to large surface area defibrillation electrodes located on leads to the heart 264 or epicardial electrodes.
[0095]FIG. 11 shows a variable clock/variable supply voltage digital signal processing system 500 which may be used in conjunction with and/or in the alternative to certain circuits shown in FIGS. 9 and 10. For example, the digital signal processing system 500 according to FIG. 11 may be used in place of activity circuit 352, pressure circuit 354, sense amplifier circuit 346 (for P-wave, R-wave- and/or T-wave sense amplifiers), and further may be provided with additional functionality with use of a pseudo EKG signal 502. Generally, any number of analog signals 499, for example, such as pseudo EKG signals 502, activity sensor signal 503 and pressure and onset sensor signal 504, are provided through respective amplifiers 505-507. The amplified signals are presented to multiplexer 510 which provides them to analog to digital converter (ADC) 516 in a cycled fashion. The signals 502-504 can be cycled at different rates by cycling through the outputs of the several amplifiers/preamplifiers 505-507 such as described in pending U.S. patent application Ser. No. 08/801,335, Medtronic Docket No. P4521, entitled “Method for Compressing Digitized Cardiac Signals Combining Lossless Compression and Non-linear Sampling,” which describes variable compression via ADC sampling and which is incorporated herein by reference in its entirety. The ADC may also have variable conversion rates as described in U.S. Pat. No. 5,263,486 and U.S. Pat. No. 5,312,446 which are also incorporated herein by reference in their entireties.
[0097]FIG. 12 is a schematic block diagram illustrating implantable medical device 600 according to the present invention. Implantable medical device 600 further includes integrated circuit 602, integrated circuit 604, sensors 606, and output integrated circuit 608. Integrated circuit 602 further includes memory 610, microprocessor 612, clock 614, timer 616, miscellaneous logic 618, digital signal processors 620A-620E, analog-to-digital converters 622, and analog circuitry 624. Integrated circuit 604 further comprises memory 628, microprocessor 630, clock 632, timer 634, and miscellaneous logic 636.
Implantable medical device 600 is implanted into a patient in proximity to heart 640 by employing techniques such as those previously described with references to FIGS. 8 and 9. Implantable medical device 600 can be embodied as any one of a variety of implantable medical devices, such as those previously discussed, including a pacemaker or a defibrillator. Implantable medical device 600 is connected to heart 640 via leads 642. Leads 642 can be pacing or sensing leads that provide electrical stimulation to the heart in accordance with the present invention.
Minimization and control of power dissipation is one of the significant aspects of the present invention. Specifically, efficient implementation of power systems in implantable medical device 600 enables conservation of space and volume in addition to reduction in weight while maintaining a desired output. Low efficiency results in higher costs, primarily because of a waste of energy and the need for larger power supplies. For example, dynamic power (P) of a given circuit of implantable medical device 600 is equal to: ½CVDD 2F, where C is the nodal capacitance of the circuit, F is the clock frequency of the circuit, and VDD is the supply voltage for the circuit. Medical device 600, according to the present invention, utilizes a relatively low system clock frequency to generate various logic signals. Use of a relatively low system clock frequency, preferably less than 500 kHz, enables substantial reduction in power dissipation.
Supply voltages V1-VN are used to charge capacitor 682. In one preferred embodiment, supply voltages V1-VN are evenly distributed between ground and VN so that the voltage difference between any two adjacent supplies is the same. Each of the supply voltages is selectively applied to capacitor 682 by N switches including the first switch S1 and N-1 additional switches. To reset the voltage on capacitor 684 to an initial condition, switch 684 is closed. To charge the load, switch 684 is opened and supply voltages V1-VN are connected to capacitor 682 in succession by selectively closing the switches, that is, by momentarily closing switch S1, opening switch S1, momentarily closing switch S2, etc. To discharge the load, the supply voltages, VN-1 through V1 are switched in reverse order. Switch 684 is then closed, connecting the output to ground.
Estep=½CLV2
[0115]FIG. 14A is a timing diagram illustrating voltage versus time at capacitor 682 shown in FIG. 13. As shown in FIG. 14A, the voltage at capacitor 682 is gradually ramped up from zero volts to supply voltage V. Similarly, the voltage is then ramped down from supply voltage V to zero volts. With the transition of ramped logic signal 686 from low to high and high to low in a gradual manner, minimal energy is released in the form of dissipated power during a switching operation.
[0117]FIG. 15 is a schematic diagram illustrating the embodiment of the invention shown in FIG. 13 including numerous transistors. Circuitry 700 is similar to circuitry 680 shown in FIG. 13, with the exception of transistors T1-TN replacing switches S1-SN. In one preferred embodiment, transistors T1-TN are either N channel or P channel CMOS devices. Circuitry 700 operates similar to circuitry 680 shown in FIG. 13. For example, circuitry 700 provides ramped logic signal 706 to circuitry within implantable medical device 600. Further, in one preferred embodiment, circuitry 700 operates at a frequency of less than 500 kilohertz. Further, supply voltages V1-VN are evenly distributed between ground and VN so that the voltage difference between any two adjacent supplies is the same. Each of the voltages is selectively applied to capacitor 682 by N transistors including first transistor T1 and N-1 additional transistors. As in the previous circuit, transistors T1-TN and transistor 702 are controlled by controller 688. Transistor 702 can be used to set an initial, known condition on capacitor 682. To charge the capacitor 682, transistor 702 is open and supply voltages V1-VN are connected to capacitor 682 in succession by selectively turning on the transistors, that is, by momentarily closing transistor T1, opening transistor T1, momentarily closing transistor T2, etc. To discharge the load, the supply voltages V1-VN are applied to the load in reverse order. Transistor 702 is then closed, connecting the output to ground. The above-discussed sequence would produce a timing diagram such as illustrated in FIG. 14A.
Circuitry 710, shown in FIG. 16 discloses another embodiment of the present invention that utilizes adiabatic logic to minimize power consumption within an implantable medical device. Circuitry 710 provides ramped logic signal 714 to circuitry within implantable medical device 600. Circuitry 710, is similar to circuitry 680 shown in FIG. 13, operating at a frequency of less than 500 kilohertz. However, capacitors C1-CN-1 replaces voltage sources V1-VN-1 connected between ground and switches S1-SN-1, respectively. In one preferred embodiment, capacitors C1-CN-1 are tank capacitors with a capacitance much larger (e.g., in order of magnitude) than capacitor 682. Once again, in one preferred embodiment, capacitor 682 represents an internal capacitance comprising the total capacitance of the internal nodes connected to a bus. In one preferred embodiment, capacitors C1-CN-1 have identical values to produce a symmetrical logic signal 714.
Circuitry 720, shown in FIG. 17, is similar to circuitry 710, shown in FIG. 16, with the exception that transistors T1-TN replace switches S1-SN. As previously discussed, capacitors C1-CN-1 can be tank capacitors and transistors T1-TN and 702 can be controlled by control 704. In one preferred embodiment, transistors T1-TN can be either N channel or P channel devices. Circuitry 720 provides ramped logic signal 722 to circuitry within implantable medical device 600.
[0122]FIG. 18 discloses yet another embodiment of the present invention. Circuitry 730, shown in FIG. 18, provides exponential logic signal 740 to circuitry within implantable medical device 600. Once again, capacitor 682 represents an internal capacitance comprising the total capacitance of the internal nodes connected to a bus, such as buses 626A-626F, 638, and 660. Circuitry 730 also includes voltage source V, current sources 734 and 736, and switch 738. Current source 734 is connected between voltage source V and switch 738, while current source 736 is connected between switch 738 and ground. The position of switch 738 determines whether capacitor 682 is charging or discharging. Due to the charging and discharging capabilities of capacitor 682, circuitry 730 will produce exponential logic signal 740 as shown in FIG. 19. As can be seen in FIG. 19, circuitry 730 produces an exponentially increasing first portion of exponential logic signal 740, while also producing an exponentially decreasing second portion of exponential logic signal 740. In one preferred embodiment, current source 734 and 736 would have identical values, such as in the range of 10-1000 pA.
[0123]FIG. 20 is yet another embodiment which discloses an adiabatic logic system which minimizes power dissipation of a continuously switching clock signal. While the embodiment shown in FIGS. 13 and 15-18 are used in conjunction with a bus within implantable medical device 600, circuitry 750, shown in FIG. 20, is used within implantable medical device 600 in conjunction with a clock signal. For example, circuitry 750, shown in FIG. 20, can be used within clocks 614 or 632, or in conjunction with timers 616 or 634 shown in FIG. 20. As shown in FIG. 20, circuitry 750 includes buffer circuit 752, inductor 754, and inverter circuit 756. Buffer circuit 752 further includes transistors 758 and 760, voltage sources VDD and VSS, and resistor 762, which represents an output resistance of buffer 752. Inverter circuit 756 further comprises inverter element 764 and capacitor 766, which represents an internal nodal input capacitance of inverter circuit 756.
[0124]FIG. 20 represents circuit 750. The major segments of circuit 750 include inductor 754 in series with buffer circuit 752 and inverter circuit 756. Buffer circuit 752 includes transistors 758 and 760 set across voltage sources VDD and VSS. The transistors are in series with resistor 762, which is in turn serially connected to inductor 754. Similarly, inverter circuit 756 includes inverter element 764 connected in series with inductor 754. Capacitor 766 represents an internal capacitance between an input of inventor element 764 and ground.
1. A system for generating a logic signal which is provided to a portion of an implantable medical device and which minimizes power dissipation within the implantable medical device, the system comprising:
a capacitive element associated with a bus within the implantable medical device, wherein the capacitive element is operatively coupled to a first potential;
N voltage supplies;
a controller operatively coupled to the N switches and to the first switch to control the N switches and the first switch.
2. The system of claim 1, wherein the capacitive element includes an internal capacitance within the bus between a first electrical component and a second electrical component of the implantable medical device.
6. A system for generating a logic signal which is provided to a portion of an implantable medical device and which minimizes power dissipation within the implantable medical device, the system comprising:
a first switch operatively coupled to a first voltage potential;
a capacitive element associated with a bus within the implantable medical device operatively coupled to a second voltage potential;
a second switch operatively coupled to the second voltage potential in parallel with the capacitive element;
N parallel capacitors operatively coupled to the first voltage potential;
N parallel switches corresponding to the N parallel capacitors, each switch being operatively coupled between a corresponding one of the N capacitors and the capacitive element; and
a controller operatively coupled to the first switch, the second switch, and the N parallel switches to control the first switch, the second switch, and the N switches.
7. The system of claim 6, wherein the capacitive element has an internal capacitance within the bus between a first electrical component and a second electrical component of the implantable medical device.
8. The system of claim 7, wherein the logic signal generated across the capacitive element is provided to the first electrical component.
9. The system of claim 7, wherein the logic signal generated across the capacitive element is provided to the second electrical component.
10. The system of claim 6, wherein the logic signal generated across the capacitive element operates at a frequency of less than 500 kilohertz.
11. A system for generating a voltage signal which is provided to a portion of an implantable medical device and which minimizes power dissipation within the implantable medical device, the system comprising:
a first current source operatively coupled to a first voltage potential;
a second current source operatively coupled to a second voltage potential;
a capacitive element associated with a bus within the implantable medical device operatively coupled to the second voltage potential;
a switch operatively coupled between the capacitive element and the first and second current sources for operatively coupling one of the first and second current sources to the capacitive element; and
a controller operatively coupled to the switch to control the switch.
12. The system of claim 11, wherein the capacitive element has an internal capacitance within the bus between a first electrical component and a second electrical component of the implantable medical device.
13. The system of claim 12, wherein the voltage signal generated across the capacitive element is provided to the first electrical component.
14. The system of claim 12, wherein the voltage signal generated across the capacitive element is provided to the second electrical component.
15. The system of claim 11, wherein the voltage signal generated across the capacitive element operates at a frequency of less than 500 kilohertz.
16. A system for generating a logic signal which is provided to a portion of an implantable medical device and which minimizes power dissipation within the implantable medical device, the system comprising:
a clock having an output clock signal;
an inverter having an input, an output, and a resistance, wherein the output clock signal of the clock is operatively coupled to the input of the inverter;
an inductive element operatively coupled to the output of the inverter;
a buffer having an input, an internal input capacitance, and an output, wherein the input is operatively coupled to the inductive element; and
wherein the logic signal is generated at the output of the buffer and is provided to a portion of the implantable medical device.
17. The system of claim 16, wherein the logic signal generated at the output of the buffer operates at a frequency of less than 500 kilohertz.
18. An implantable medical device having an adiabatic scheme which is provided to a portion of an implantable medical device and which minimizes power dissipation from a sub-component of the implantable medical device, the implantable medical device comprising:
a first sub-circuit;
a second sub-circuit;
an electrical connection between the first and second sub-circuits, the. electrical connection including a capacitive element;
means for generating a logic signal having a frequency of less than 500 kilohertz, the logic signal including a plurality of repeating cycles, each cycle further comprising:
a first cycle portion where the ramped logic signal is at a first voltage;
a second cycle portion where the ramped logic signal is ramped from the first voltage to a second voltage;
a third cycle portion where the logic signal is at the second voltage;
a fourth cycle portion where the logic signal is ramped from the second voltage to the first voltage; and
means for supplying the logic signal to one of the first and second sub-circuits.
19. A method of generating a logic signal for a portion of an implantable medical device which minimizes power dissipation within the implantable medical device, the method comprising:
charging a capacitive element associated with a bus to generate a logic signal including a plurality of repeating cycles, each cycle comprising:
a first cycle portion where the logic signal is at a first voltage;
supplying the logic signal to the portion of the implantable medical device.
20. The method of claim 19, wherein the step of charging a capacitive element further comprises the step of:
charging an internal capacitance within the bus between a first electrical component and a second electrical component of the implantable medical device.
21. The method of claim 20, wherein the step of supplying the logic signal further comprises the step of:
supplying the logic signal to the first electrical component.
22. The method of claim 20, wherein the step of supplying the logic signal further comprises the step of:
supplying the logic signal to a second electrical component.
23. The method of claim 19, wherein the step of charging a capacitive element further comprises the step of:
charging a capacitive element associated with a bus to generate a logic signal which operates at a frequency of less than 500 kilohertz.
US10136776 1998-04-29 2002-04-30 Power dissipation reduction in medical devices using adiabatic logic Abandoned US20030014082A1 (en)
US09467288 Division US6438422B1 (en) 1998-04-29 1999-12-20 Power dissipation reduction in medical devices using adiabatic logic
US20030014082A1 true true US20030014082A1 (en) 2003-01-16
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US09467288 Expired - Fee Related US6438422B1 (en) 1998-04-29 1999-12-20 Power dissipation reduction in medical devices using adiabatic logic
US10136776 Abandoned US20030014082A1 (en) 1998-04-29 2002-04-30 Power dissipation reduction in medical devices using adiabatic logic
US (2) US6438422B1 (en)
DE (1) DE10061666A1 (en)
FR (1) FR2803959B1 (en)
US8575975B1 (en) * 2009-01-28 2013-11-05 Cirrus Logic, Inc. Stepped voltage drive for driving capacitive loads
US5473269A (en) * 1993-05-28 1995-12-05 At&T Corp. Adiabatic dynamic logic
FR2803959A1 (en) 2001-07-20 application
US6438422B1 (en) 2002-08-20 grant
DE10061666A1 (en) 2001-08-02 application
FR2803959B1 (en) 2004-07-16 grant
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