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Patent US6261929 - Methods of forming a plurality of semiconductor layers using spaced trench ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsMethods of forming compound semiconductor layers include the steps of forming a plurality of selective growth regions at spaced locations on a first substrate and then forming a plurality of semiconductor layers at spaced locations on the first substrate by growing a respective semiconductor layer on...http://www.google.com/patents/US6261929?utm_source=gb-gplus-sharePatent US6261929 - Methods of forming a plurality of semiconductor layers using spaced trench arraysAdvanced Patent SearchPublication numberUS6261929 B1Publication typeGrantApplication numberUS 09/512,242Publication dateJul 17, 2001Filing dateFeb 24, 2000Priority dateFeb 24, 2000Fee statusPaidAlso published asUS6486042, US20020013036, WO2001063654A2, WO2001063654A3Publication number09512242, 512242, US 6261929 B1, US 6261929B1, US-B1-6261929, US6261929 B1, US6261929B1InventorsThomas Gehrke, Kevin J. Linthicum, Robert F. DavisOriginal AssigneeNorth Carolina State UniversityExport CitationBiBTeX, EndNote, RefManPatent Citations (54), Non-Patent Citations (74), Referenced by (109), Classifications (23), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetMethods of forming a plurality of semiconductor layers using spaced trench arraysUS 6261929 B1Abstract Methods of forming compound semiconductor layers include the steps of forming a plurality of selective growth regions at spaced locations on a first substrate and then forming a plurality of semiconductor layers at spaced locations on the first substrate by growing a respective semiconductor layer on each of the selective growth regions. The first substrate is then divided into a plurality of second smaller substrates that contain only a respective one of the plurality of semiconductor layers. This dividing step is preferably performed by partitioning (e.g., dicing) the first substrate at the spaces between the selective growth regions. The step of forming a plurality of semiconductor layers preferably comprises growing a respective compound semiconductor layer (e.g., gallium nitride layer) on each of the selective growth regions. The growing step may comprise pendeoepitaxially growing a respective gallium nitride layer on each of the selective growth regions. Each of the selective growth regions is also preferably formed as a respective plurality of trenches that have sidewalls which expose compound semiconductor seeds from which epitaxial growth can take place.
FEDERALLY SPONSORED RESEARCH This invention was made with Government support under Office of Naval Research Contract No. N00014-98-1-0384. The Government may have certain rights to this invention.
FIELD OF THE INVENTION The present invention relates to methods of forming semiconductor substrates and substrates formed thereby, and more particularly to methods of forming compound semiconductor substrates and compound semiconductor substrates formed thereby.
BACKGROUND OF THE INVENTION Compound semiconductor materials such as gallium nitride (GaN) have been widely investigated as suitable substrate materials for microelectronic devices including but not limited to transistors, field emitters and optoelectronic devices. It will be understood that, as used herein, compound semiconductor materials may include III-V and II-VI alloys, for example. Reference to specific compound semiconductors such as gallium nitride will also be understood to include a family of gallium nitride alloys such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride.
It also is known to produce low defect density gallium nitride layers by forming a mask on a layer of gallium nitride, the mask including at least one opening that exposes the underlying layer of gallium nitride, and laterally growing the underlying layer of gallium nitride through the at least one opening and onto the mask. This technique often is referred to as �Epitaxial Lateral Overgrowth� (ELO). The layer of gallium nitride may be laterally grown until the gallium nitride coalesces on the mask to form a single layer on the mask. In order to form a continuous layer of gallium nitride with relatively low defect density, a second mask may be formed on the laterally overgrown gallium nitride layer, that includes at least one opening that is offset from the underlying mask. ELO then again is performed through the openings in the second mask to thereby overgrow a second low defect density continuous gallium nitride layer. Microelectronic devices then may be formed in this second overgrown layer. ELO of gallium nitride is described, for example, in the publications entitled Lateral Epitaxy of Low Defect Density GaN Layers Via Organometallic Vapor Phase Epitaxy to Nam et al., Appl. Phys. Lett. Vol. 71, No. 18, Nov. 3, 1997, pp. 2638-2640; and Dislocation Density Reduction Via Lateral Epitaxy in Selectively Grown GaN Structures to Zheleva et al, Appl. Phys.
It also is known to produce a layer of gallium nitride with low defect density by forming at least one trench or post in an underlying layer of gallium nitride to define at least one sidewall therein. A layer of gallium nitride is then laterally grown from the at least one sidewall which acts as a �seed�. Lateral growth preferably takes place until the laterally grown layers coalesce within the trenches. Lateral growth also preferably continues until the gallium nitride layer that is grown from the sidewalls laterally overgrows onto the tops of the posts. In order to facilitate lateral growth and produce nucleation of gallium nitride and growth in the vertical direction, the top of the posts and/or the trench floors may be masked.
Lateral growth from the sidewalls of trenches and/or posts also is referred to as �pendeoepitaxy� and is described, for example, in publications by Zheleva et al, entitled �Pendeo-Epitaxy: A New Approach for Lateral Growth of Gallium Nitride Films�, Journal of Electronic Materials, Vol. 28, No. 4, pp. L5-L8, February (1999) and Linthicum et al, entitled �Pendeoepitaxy of Gallium Nitride Thin Films� Applied Physics Letters, Vol. 75, No. 2, pp. 196-198, July (1999), the disclosures of which are hereby incorporated herein by reference. Pendeoepitaxy has also been shown to be successful at reducing threading dislocations and cracks caused by lattice mismatch by about three to four orders of magnitude relative to other conventional heteroepitaxy techniques. Nonetheless, because pendeoepitaxy may not always be successful in preventing the formation of cracks and bowing when large compound semiconductor layers such as gallium nitride are cooled to room temperature during back-end processing steps, there continues to be a need for improved methods of forming compound semiconductor layers with reduced susceptibility to cracking and bowing.
SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide improved methods of forming compound semiconductor substrates and substrates formed thereby.
Advantageously, because each selective growth region is separated from a next adjacent selective growth region by a wide trench the preferably has a width at least about ten (10) times greater than the widths of the narrower trenches within a respective selective growth region, adjacent monocrystalline compound semiconductor layers preferably do not coalesce with each other. Nonetheless, because each monocrystalline compound semiconductor layer is of sufficiently large dimension to ultimately serve as a separate compound semiconductor substrate or �platform� once the supporting substrate has been diced along the dicing streets defined by each wide trench, the failure of the adjacent compound semiconductor layers to coalesce into a single wafer-sized layer need not limit the suitability of the preferred methods for large scale integrated circuit and optoelectronic applications. Instead, by preventing adjacent compound semiconductor layers from coalescing with each other, the likelihood that the compound semiconductor layers will bow or crack upon cooling, as a result of lattice mismatch and thermal expansion coefficient differences, is substantially reduced. In other words, by growing separate compound semiconductor �platforms� separated by wide trenches, the lattice stress and concomitant build-up in strain within each �platform�, caused by differences in the thermal expansion coefficients of the compound semiconductor material and underlying substrate is greatly reduced relative to a large fully coalesced pendeoepitaxially formed compound semiconductor layer.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan layout view of a semiconductor wafer having a plurality of selective growth regions at spaced locations therein, according to an embodiment of the present invention.
DESCRIPTION OF PREFERRED EMBODIMENTS The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being �on� another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being �directly on� another element, there are no intervening elements present.
Referring now to FIGS. 1-4, preferred methods of forming a plurality of compound semiconductor substrates will be described. In particular, FIGS. 1-2 illustrate preferred steps of forming a plurality of selective growth regions 12 at spaced locations across a composite semiconductor substrate 10. These selective growth regions 12 may be rectangular in shape and have an area greater than about 1�104 μm2. According to one aspect of the present invention, the substrate 10 may comprise a (111) silicon wafer having a plurality of semiconductor layers stacked thereon. In particular, the plurality of semiconductor layers may include an underlying silicon carbide (SiC) layer, an intermediate aluminum nitride (AIN) layer on the silicon carbide layer and a gallium nitride (GaN) seed layer on the intermediate aluminum nitride layer, as described more fully hereinbelow with respect to FIGS. 5A-5J. Alternative exemplary substrates are also described in U.S. application Ser. No. 09/441,754, entitled �Methods of Fabricating Gallium Nitride Microelectronic Layers on Silicon Layers and Gallium Nitride Microelectronic Structures Formed Thereby�, filed Nov. 17, 1999, the disclosure of which is hereby incorporated herein by reference. Other substrates including those containing sapphire and/or compound semiconductor seed layers besides gallium nitride may also be used.
Referring now to FIG. 2, each of the selective growth regions 12 is preferably formed by selectively etching the substrate 10 to define a plurality of narrow parallel stripe-shaped trenches 14 and a plurality of parallel stripe-shaped semiconductor mesas 16 extending between the narrow trenches 14. The depths of these trenches 14 are preferably selected so that the sidewalls thereof expose portions of an underlying compound semiconductor seed layer. As illustrated, the semiconductor mesas 16 may be formed to have a uniform width �Wm� and the narrow trenches 14 may formed to have a uniform width �Wt�. These widths may also be nonuniform. Typical values of Wm and Wt may be about 1.0 μm and 4.0 μm, respectively. Each of the selective growth regions 12 may also have a width �Wsg� and may be spaced from a next adjacent selective growth region 12 by a respective wide trench 18 having a width �Wds�. Typical values for Wsg and Wds may be 500 μm and 50 μm, respectively. The value of Wds is also preferably set at a level greater than about ten (10) times Wt. As will be understood by those skilled in the art, the narrow trenches 14 and wide trenches 18 may be formed simultaneously by anisotropically etching the substrate 10 using a photolithographically patterned mask having openings therein where the trenches are to be formed. Typical etching techniques include reactive ion etching (RI E) and inductively coupled plasma (ICP). Selective growth techniques may also be used to define the mesas 16.
Referring now specifically to FIGS. 3-4, pendeoepitaxial growth techniques are preferably used to form a separate monocrystalline compound semiconductor layer 20 on each of the selective growth regions 12. In particular, pendeoepitaxial growth techniques may be used to grow a respective monocrystalline gallium nitride layer from gallium nitride �seeds� that are exposed by the sidewalls of the mesas 16 within each selective growth region 12. Exemplary pendeoepitaxial growth techniques are more fully described in U.S. application Ser. No. 09/198,784, entitled �Pendeoepitaxial Methods of Fabricating Gallium Nitride Semiconductor Layers on Silicon Carbide Substrates by Lateral Growth from Sidewalls of Masked Posts, and Gallium Nitride Semiconductor Structures Fabricated Thereby, filed Nov. 24, 1998, now U.S. Pat. No. 6,177,688, and in U.S. application Ser. No. 09/468,995, entitled �Pendeoepitaxial Methods of Fabricating Gallium Nitride Semiconductor Layers on Weak Posts, and Gallium Nitride Semiconductor Structures Fabricated Thereby, filed Dec. 21, 1999, the disclosures of which are hereby incorporated herein by reference.
Advantageously, because each selective growth region 12 is separated from a next adjacent selective growth region 12 by a wide trench that preferably has a width at least about ten (10) times greater than the widths of the narrow trenches within a respective selective growth region 12, adjacent monocrystalline compound semiconductor layers 20 preferably do not coalesce with each other. However, because each monocrystalline compound semiconductor layer 20 is of sufficiently large dimension to ultimately serve as a separate compound semiconductor substrate or �platform� once the supporting substrate 10 has been diced along the dicing streets defined by each wide trench 18, the failure of the adjacent compound semiconductor layers 20 to coalesce into a single wafer-sized layer need not limit the suitability of the preferred methods for large scale integrated circuit and optoelectronic applications. Instead, by preventing adjacent compound semiconductors 20 from coalescing with each other, the likelihood that the compound semiconductor layers 20 will bow or crack upon cooling, as a result of lattice mismatch and thermal expansion coefficient differences, is substantially reduced. In other words, by growing separate compound semiconductor �platforms� separated by wide trenches, the lattice stress and concomitant build-up in strain within each �platform� caused by differences in the thermal expansion coefficients of the compound semiconductor material and underlying substrate is greatly reduced relative to a large fully coalesced pendeoepitaxially formed compound semiconductor layer.
Referring now to FIGS. 5A-5J, an exemplary method of forming a respective gallium nitride semiconductor layer on a central portion of a selective growth region 12 will be described. According to this exemplary method, a (111) silicon SIMOX supporting substrate 202 is provided. As illustrated by FIG. 5A, this substrate 202 includes a buried layer of silicon dioxide 202 b therein that defines a (111) silicon surface layer 202 c on an underlying (111) silicon substrate 202 a. The buried layer of silicon dioxide may be fabricated by implanting oxygen into a (111) silicon substrate to define a (111) silicon surface layer on the (111) silicon substrate. This process generally is referred to as SIMOX and is described for example in an article by Chen, entitled �Silicon-on-Insulator Why, How, and When�, AIP Conference Proceedings, Vol. 167, No. 1, pp. 310-319, Sep. 15, (1988).
FIGS. 5G-5I now will show the use of pendeoepitaxy to laterally grow the underlying seed layer of 2H-gallium nitride 204 into a monocrystalline gallium nitride semiconductor layer. As described in the aforementioned U.S. application Ser. No. 09/441,754, pendeoepitaxial techniques may be used advantageously to grow a monocrystalline gallium nitride semiconductor layer having an average defect density level therein of less than about 105 cm−3. Referring to FIG. 5G, the underlying gallium nitride layer 204 may be formed to have a plurality of sidewalls 205 therein. It will be understood by those having skill in the art that the sidewalls 205 may be thought of as being defined by a plurality of spaced apart posts 206, that also may be referred to as �mesas�, �pedestals� or �columns�. The sidewalls 205 also may be thought of as being defined by a plurality of trenches 207, also referred to as �wells� in the underlying gallium nitride layer 204. The sidewalls 205 may also be thought of as being defined by a series of alternating trenches 207 and posts 206. It will be understood that the posts 206 and the trenches 207 that define the sidewalls 205 may be fabricated by selective etching, selective epitaxial growth and/or other conventional techniques. Moreover, it also will be understood that the sidewalls need not be orthogonal to the substrate 202, but rather may be oblique thereto. Finally, it also will be understood that although the sidewalls 205 are shown in cross-section in FIG. 5G, the posts 206 and trenches 207 may define elongated regions that are straight, V-shaped or have other shapes. The trenches 207 may also extend into the buffer layer 202 e and into the underlying silicon carbide layer 202 c′/202 d′, so that subsequent gallium nitride growth occurs preferentially on the sidewalls 205 rather than on the trench floors. In other embodiments, the trenches may not extend into the silicon carbide layer 202 c′/202 d′, and also may not extend into buffer layer 202 e, depending, for example, on the trench geometry and the lateral versus vertical growth rates of the gallium nitride seed layer.
Referring now to FIG. 5H, the sidewalls 205 of the underlying gallium nitride layer 204 are laterally grown to form a lateral gallium nitride layer 208 a in the trenches 207. Lateral growth of gallium nitride may be obtained at 1000-1100� C. and 45 Torr. The precursors TEG at 13-39 μmol/min and NH3 at 1500 sccm may be used in combination with a 3000 sccm H2 diluent. If gallium nitride alloys are formed, additional conventional precursors of aluminum or indium, for example, may also be used. As used herein, the term �lateral� means a direction that is orthogonal to the sidewalls 205. It will also be understood that some vertical growth on the posts 206 may also take place during the lateral growth from sidewalls 205. As used herein, the term �vertical� denotes a directional parallel to the sidewalls 205.
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EventsDateCodeEventDescriptionJan 2, 2013FPAYFee paymentYear of fee payment: 12Dec 4, 2008FPAYFee paymentYear of fee payment: 8Apr 20, 2005ASAssignmentOwner name: NAVY, SECRETARY OF THE UNITED, STATES OF AMERICA,Free format text: CONFIRMATORY LICENSE;ASSIGNOR:NORTH CAROLINA STATE UNIVERSITY;REEL/FRAME:016470/0193Effective date: 20041008Owner name: NAVY, SECRETARY OF THE UNITED, STATES OF AMERICA 8Free format text: CONFIRMATORY LICENSE;ASSIGNOR:NORTH CAROLINA STATE UNIVERSITY /AR;REEL/FRAME:016470/0193Dec 21, 2004FPAYFee paymentYear of fee payment: 4Feb 24, 2000ASAssignmentOwner name: NORTH CAROLINA STATE UNIVERSITY OFFICE OF THE VICEFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GEHRKE, THOMAS;LINTHICUM, KEVIN J.;DAVIS, ROBERT F.;REEL/FRAME:010584/0389Effective date: 20000215RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google