Source: https://patents.google.com/patent/US9311226B2/en
Timestamp: 2020-04-10 04:12:11
Document Index: 21427612

Matched Legal Cases: ['application No. 2013', 'application No. 200980106241', 'application No. 200980106241', 'application No. 2010548134', 'application No. 200980106241', 'application No. 201310136995', 'Application No. 10']

US9311226B2 - Managing operational state data of a memory module using host memory in association with state change - Google Patents
Managing operational state data of a memory module using host memory in association with state change Download PDF
US9311226B2
US9311226B2 US13/451,951 US201213451951A US9311226B2 US 9311226 B2 US9311226 B2 US 9311226B2 US 201213451951 A US201213451951 A US 201213451951A US 9311226 B2 US9311226 B2 US 9311226B2
US13/451,951
US20130282957A1 (en
2012-04-20 Application filed by Memory Technologies LLC filed Critical Memory Technologies LLC
2012-04-20 Priority to US13/451,951 priority Critical patent/US9311226B2/en
2012-05-10 Assigned to NOKIA CORPORATION reassignment NOKIA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MYLLY, KIMMO J.
2013-04-18 Assigned to NOKIA INC. reassignment NOKIA INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NOKIA CORPORATION
2013-04-18 Assigned to MEMORY TECHNOLOGIES LLC reassignment MEMORY TECHNOLOGIES LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NOKIA INC.
2013-10-24 Publication of US20130282957A1 publication Critical patent/US20130282957A1/en
2016-04-12 Publication of US9311226B2 publication Critical patent/US9311226B2/en
The specification and drawings present a new apparatus and method for managing/configuring by the memory module controller storing operational state data for operating the memory module controller into an extended random access memory comprised in a memory module and in a host system memory of a host device during various operational modes/conditions of the memory module and the host system memory. Essentially, the memory module controller operated as a master for the data transfers as described herein. The operational state data typically comprises state information, a logical to physical (L2P) mapping table and register settings.
The exemplary and non-limiting embodiments of this invention relate generally to memory storage systems, and, more specifically, relate to managing/configuring by a memory module controller storing operational state data for a memory module.
MMM, MM mass memory module or memory module
MMCO memory module controller
P2L physical to logical
PCRAM phase change random access memory
SATAIO serial advanced technology attachment international organization
SM system memory or host system memory
According to a first aspect of the invention, a method, comprising: dynamically managing, by a memory module controller of a mass memory module, storage of all or a portion of operational state data for operating the memory module controller into an extended random access memory comprised in a memory of the mass memory module and in a host system memory of a host device; and reading, by the memory module controller after waking up from a shut down or a sleep state of the mass memory module, at least a part of the operational state data from one or more of: the extended random access memory and a non-volatile mass memory to restore an operational state of the memory module controller.
According to a second aspect of the invention, an apparatus, comprising: a mass memory module comprising an extended random access memory together with a portion of a host system memory in a host device; and a memory module controller configured to dynamically manage storage of all or a portion of operational state data for operating the memory module controller into an extended random access memory comprised in a memory of the mass memory module and in the host system memory of the host device, and further configured to read, after waking up from a shut down or a sleep state of the mass memory module, a part of the operational state data from one or more of: the extended random access memory and a non-volatile mass memory of the mass memory module to restore an operational state of the memory module controller.
FIG. 1A reproduces FIG. 2 from JEDEC Standard, Embedded MultiMediaCard (eMMC) Product Standard, High Capacity, JESD84-A42, June 2007, JEDEC Solid State Technology Association, and shows a functional block diagram of an eMMC;
FIG. 1B reproduces FIG. 1 of Lin et al., and shows an example of an overall block diagram of a NAND flash controller architecture for a SD/MMC card;
FIG. 2 is a simplified block diagram of a host device connected with a mass storage memory device, and is helpful in describing the exemplary embodiments of the invention;
FIG. 3 is a signal/message flow diagram that describes an embodiment of the invention described in commonly-assigned U.S. patent application Ser. No. 12/455,763, where the mass storage memory device of FIG. 2 can allocate, use and de-allocate RAM of the host device;
FIG. 4 is a signal/message flow diagram that describes another embodiment of the invention described in commonly-assigned U.S. patent application Ser. No. 12/455,763, where the mass storage memory device of FIG. 2 has a built-in file system;
FIGS. 5A and 5B, collectively referred to as FIG. 5, are representations of the host device and mass memory module in accordance with embodiments of the invention;
FIG. 6 is a logic flow diagram that illustrates the operation of a method, and a result of execution of computer program instructions embodied on a computer readable memory, further in accordance with the exemplary embodiments of this invention;
FIGS. 7A and 7B are examples of memory maps of the memory module controller in the memory module when utilization of system resources such as the portion DRAM 14G is disabled (FIG. 7A) or enabled (FIG. 7b );
FIG. 8 is a diagram demonstrating embodiments shown in the flow chart in FIG. 6 relating to responding by a memory module controller to a command (or an attribute in the command) from a host device; and
FIG. 9 shows a block diagram of one exemplary embodiment of the host device when embodied as a wireless communication device.
FIG. 2 shows a simplified block diagram of a host system or device 10 connected with a mass storage memory 20 via a mass storage memory bus (MSMB) 18. The MSMB 18 may be compatible with any suitable mass memory interface standard such as MMC or UFS, as two non-limiting examples. The MSMB 18 may include signal lines such as those shown in FIG. 1A for an eMMC embodiment. The host device 10 includes at least one controller, such as a CPU 12 that operates in accordance with stored program instructions. The program instructions may be stored in a RAM 14 or in another memory or memories. The CPU 12 is connected with the RAM 14 and a MSMB interface (I/F) 16 via at least one internal bus 17. The MSMB interface 16 may include a memory controller (MC), or may be coupled with a MC unit associated with the CPU 12. The host device 10 may be a computer, a cellular phone, a digital camera, a gaming device or a PDA, as several non-limiting examples. Note that the RAM 14 may be any read/write memory or memory device, such as semiconductor memory or a disk-based memory.
The mass storage memory 20 includes a microcontroller or, more simply, a controller 22 that is connected via at least one internal bus 27 with a volatile RAM 24, a non-volatile mass memory 26 (e.g., a multi-gigabyte flash memory mass storage) and a MSMB interface (I/F) 28. The controller 22 operates in accordance with stored program instructions. The program instructions may be stored in the RAM 24 or in a ROM or in the mass memory 26. The mass storage memory 20 may be embodied as an MMC, eMMC, UFS or a SD device, as non-limiting examples, and may be external to (plugged into) the host device 10 or installed within the host device 10. Note that the mass memory 26 may, in some embodiments, store a file system (FS) 26A. In this case then the RAM 24 may store FS-related metadata 24A, such as one or more data structures comprised of bit maps, file allocation table data and/or other FS-associated information.
In accordance with certain embodiments of the invention described in commonly-assigned U.S. patent application Ser. No. 12/455,763 the mass storage memory device 20 is provided with a mechanism to interrupt/send a message to host device 10 to initiate an allocation of space in the RAM 14. The interrupt/message is sent over the MSMB 18, and may be considered as an extension to current command sets. Referring to FIG. 3, an allocate memory command is sent during operation 3-1. If the allocation request succeeds (indicated during operation 3-2) the controller 22 is enabled to extend its own RAM 24 with the RAM 14 of the host device 10. The mass storage memory device 20 may store, for example, large tables into the RAM 14 using a RAM WRITE command or it may fetch data from the host device RAM 14 using a RAM READ command. The read or write operation is shown as interleaved operations 3-3, 3-4, 3-5, 3-6, . . . , 3-(N−1), 3-N. When the mass storage memory device 20 completes the operation with the RAM 14 it may free the host device RAM 14 using another command that requests that the host 10 RAM memory be de-allocated (operation 3-(N+1)).
Having thus provided an overview of various non-limiting and exemplary embodiments of the invention described in the commonly-assigned U.S. patent application Ser. No. 12/455,763, a description is now made of the exemplary embodiments of this invention. In a managedNAND memory (e.g., eMMC, SSD, UFS, microSD) the memory controller (such as the controller 22 shown in FIG. 2) takes care of the flash management functions such as bad block management and wear leveling. In a typical low cost implementation there is only a small input/output (IO) buffer SRAM in the managedNAND. Embedded in the controller in higher end managedNANDs such as SSDs there may be tens to hundreds of megabits of discrete DRAM as cache. In the future some new memory technologies such as MRAM could serve as very fast non-volatile cache also.
The embedded memory in the controller is not sufficient enough to store all the run time data needed by the module and thus some portion of the run time data is stored/mirrored in non-volatile memory (e.g. NAND) of the module. This is also necessary to avoid loss of (operation) data in case of sudden power down. The non-volatile mass memory, such as NAND, is very slow for storing/reading such data, if compared to typical volatile/non-volatile execution memories like SRAM/DRAM/MRAM. This causes delay to operation of the memory module. For example, after power up the whole mass memory subsystem needs to be re-initialized from NAND and this may take time up to 1 s (e.g. eMMC, SD, SATAIO devices).
Reference can be made to FIG. 5 where those components described in reference to FIG. 2 are numbered accordingly. In FIGS. 5A and 5B a portion 14G of the system RAM (e.g., DRAM) 14 is allocated for use by the mass memory module 20 (described here in a non-limiting embodiment as a UFS memory module or a memory module). The host device 10 includes an application processor that can be embodied as the CPU 12. Included with or coupled to the application processor 12 may be a DRAM controller 11 for the DRAM 14. Also present is the above-mentioned mass memory module 20 (e.g., UFS) host controller 13. The host controller 13 can be embodied as the CPU 12 or it can be embodied as a separate device. The mass memory module (MMM) 20 (which is also called herein a memory module, MM, 20) may be connected to the host device through an interface 22 a, e.g., via a bus (e.g., like the mass storage memory bus 18 shown in FIG. 2) Also the memory module 20 can be a part of the host device 10 as shown in FIG. 5a or it may be a separate device as shown in FIG. 2.
Furthermore, the memory module 20 may comprise a non-volatile memory (e.g., NAND) 26 (or mass memory) with a portion 26A allocated for the memory controller and a memory controller 22 with an SRAM 24. For the purpose of this invention, the SRAM 24 and a portion 14G of the system DRAM 14 may be considered as an extended random access memory. It should be noted that an execution memory 24 of the memory controller 22 and/or the host system memory 14 could be a non-volatile memory such as MRAM, PCRAM and/or RRAM.
FIG. 5B shows that the system DRAM 14 stores an operating system (OS) 14 a and application programs (applications) 14 b. The system DRAM 14 also typically stores a file system cache 14 c associated with a file system (part of the OS). In the embodiment of FIG. 5B a portion of the system DRAM 14 is allocated as a transfer buffer 14 d. Another portion of the system DRAM 14 is allocated to store an access list 14F. Also included is the DRAM portion 14G that is allocated for the memory module 20, and into which the operation state data can be moved for the memory module 20.
The commonly-assigned U.S. patent application Ser. No. 12/455,763 further describes enabling the memory module to utilize the system DRAM to store data to and read data from (e.g., see FIGS. 3-4 above). This could be further utilized in embodiments described herein to enable the mass storage memory module, for example, to store its state into the system DRAM, then go to sleep/power down and after wake up/power up read back quickly the previous state. In a managed NAND environment this storing and reading of the state of operation could be taken care by the mass memory module 20 itself and in particular by the memory module controller 22, rather than by the host device 10 as the memory module itself knows best which data is needed to be stored and which portion of the run time data is allowed to be lost, e.g., during power down.
A new method and apparatus are presented for managing/configuring by the memory module controller (e.g., memory module controller 22 shown in FIG. 5a ) storing operational state data for operating the memory module controller into extended random access memory comprised in a memory module and host system memory (e.g., DRAM 14) during various operational modes/conditions of the memory module 20 and the host system memory (e.g., the DRAM 14). Essentially, the memory module controller operated as a master for the data transfers as described herein. The operational state data typically comprises one or more of state information, a logical to physical (L2P) mapping table and register settings.
The memory module controller, after waking up from a shut down or a sleep state of the mass memory module, can read at least a part of the operational state data from the extended random access memory and/or from a non-volatile mass memory to restore an operational state of the memory module controller. The reading can be based on settings of the mass memory module or based on a command or an attribute of a command from the host device which can override the settings of the mass memory module. Alternatively, the setting can override the command or the attribute from the host device.
The settings of the mass memory module may be registers settings visible also outside (e.g., access to DRAM disabled/enabled) or internal settings visible only to the memory module controller, e.g., information from which source (extended random access memory or flash memory) it would be most efficient to load the operational state data.
It is also noted that a command/attribute from the host (at an initialization phase) may override above mentioned internal settings in the mass memory module, for example, by denying access to DRAM in the host device (compromised data case) or alternatively the command may indicate that the mass memory module is free to initialize from any source.
Furthermore, the operational state data may be divided at least into high priority data (e.g., at least state information and possibly some L2L mapping table) and low priority data (e.g., register settings), so that the high priority data is stored in the DRAM portion 14G of the extended random access memory. But more than two priority levels can be used as well for classifying the operational state data, e.g. lowest priority data may be stored in the portion 26A of the non-volatile memory.
The fundamental principle for such data transfers is based on utilizing fast extended random access memory both in the memory module 20 and in a host system memory (DRAM portion 14G) of the host device 10 whenever possible over relatively slow non-volatile memory 26. This can gain an advantage for faster waking up and saving power as the memory module can be powered down more often.
FIG. 6 shows a logic flow diagram that illustrates the operation of a method, and a result of execution of computer program instructions embodied on a computer readable memory, further in accordance with the exemplary embodiments of the invention as described herein. It is noted that the order of steps shown in FIG. 6 is not absolutely required, so in principle, the various steps may be performed out of the illustrated order. Also certain steps may be skipped, different steps may be added or substituted, or selected steps or groups of steps may be performed in a separate application.
In a method according to the exemplary embodiments, as shown in FIG. 6, in a first step 70, a memory module controller (MMCO), e.g., the memory module controller 22, dynamically manages/configures storing operational state data for operating the MMCO into one or more of: an extended random access memory (ERAM) comprised in both the memory module (MM) 20 (e.g., SRAM 24) and a host system memory (or system memory, SM) 14 (e.g., a dedicated portion 14G), and in a non-volatile memory (e.g., a dedicated portion 26A of the NAND memory 26 in the MM 20). For example, if both the MM and the SM are enabled to operate in a normal condition, the storing can be configured based on predefined rules. The important (high priority) data like the state information, and all or partial logical to physical (L2P) mapping tables may be stored (written) into DRAM portion 14G of ERAM and lower priority data into SRAM 24 portion of ERAM, but the lowest priority data (e.g., register settings) may be stored in the non-volatile memory 26 (e.g., in the portion 26A). Some of the high priority data of the operational state data may be also stored in the non-volatile memory 26 (and possibly in the SRAM 22) as a duplicate of the data stored in the DRAM portion 14G-. Moreover, this storing arrangement of both MM 20 and SM 14 may be configured by the MMCO 22 automatically using a predetermined default arrangement.
Furthermore, the flow chart in FIG. 6 shows 3 scenarios, which may trigger reconfiguring by the MMCO 22 the storing arrangement established in step 70.
In one scenario, in step 71, the memory module 20 is to be disabled, e.g., going to shut down or sleep. In other words, the memory module can receive at least one of the following indications: power down indication or go to sleep/dormant mode command/state change from the host device, or automatically go to sleep/dormant mode after some defined timeout in the memory module.
In a next step 72, the MMCO reconfigures storing the operational state data in the SM (DRAM portion 14G) and possibly in the non-volatile memory (NAND 26) of the MM 20. For example, the MMCO 22 can add (write) in the DRAM portion 14G additional operational state data if possible (e.g., to the maximum capacity of the DRAM portion 14G) and further to back up (duplicate) the high priority data in the non-volatile memory. Also the low priority data such as register settings can be stored in the non-volatile memory portion 26A if not stored in the DRAM portion 14G. Step 72 may be performed by the MMCO 22 automatically based on the predefined procedure for the situation described in step 71.
In a next step 73, the MM is enabled (power up/wake up).
In a next step 74, the MMCO reads (during initialization) at least the operational state data stored in the DRAM portion 14G to restore an operational state of the MMCO 22. Also the information stored in the non-volatile memory portion NAND 26A as described in step 72 could be possibly used for restoring the operational state of the MMCO 22.
In another scenario, in step 75, the MMCO 22 ascertains (e.g., receiving a command from the host device or an attribute comprised in the command) that the SM (DRAM portion 14G) of the host device 10 is unavailable and/or to be disabled, and/or the data stored in the DRAM portion 14G is compromised.
Then in a next step 76, the MMCO 22 can store the operational state data from the DRAM portion 14G into the non-volatile memory 26A and/or SRAM 22 of the MM 20 before the SM in the host device becomes unavailable/disabled. If the operational state data stored in the SM is compromised, then the MMCO 22 can restore/rebuild needed information from the non-volatile memory (NAND 26) if that data is not available in the SRAM 22.
In a next step 77, the SM in the host device is enabled (power up/wake up which is signals to the MM 20).
In a next step 78, the MMCO 22 reconfigures storing at least important operational state data into the SM (DRAM 14) as in step 70.
Yet in another scenario, in step 79, both the memory module 20 and SM 14 are to be disabled, e.g., shut down or going to sleep. For example, the host device may issue a command of a total shutdown. In a next step 80, the MMCO reconfigures storing the operational state data in the non-volatile memory (NAND 26) of the MM.
In a next step 81, both the memory module 20 and SM 14 in host device are enabled (power up/wake up). In a next step 82, the MMCO configures recovering and storing the operational state data like in step 70 using information stored in the non-volatile memory (NAND 26) of the MM. It is further noted that this step may include the mass memory module initializing itself using all or selected operational state data stored in the non-volatile memory at step 80.
It is noted that reading and writing steps (e.g., see steps 72, 76, 80, 74, 78 and 82) may be performed by the MMCO 22 based on the command (or the attribute in the command) from the host device 10 and/or using its own judgment.
FIGS. 7a-7b and 8 further illustrate different embodiments disclosed in the flow chart of FIG. 6. For example, FIGS. 7a and 7b show examples of memory maps of the MMCO 22 in the MM 20 when utilization of system resources such as the DRAM portion 14G is disabled (FIG. 7a ) and when utilization of system resources is enabled (FIG. 7b ).
FIG. 7a (when DRAM portion 14G is not accessible/disabled) provides operational details for a non-volatile memory portion such as NAND portions 26A and SRAM 24 identified in FIG. 5. As shown in FIG. 7a , the NAND portion 26A shown on the left can store a small boot section from which to load first pieces of a code to initialize the memory module controller 22. The SRAM 24 can provide run time execution memory storing of necessary code to run the MM 20 and storing at least pieces of metadata like P2L mapping data. Also the NAND portion 26A shown on the right can be a paging memory for the MMCO 22 if there is not enough SRAM 24 to store the whole P2L mapping table; also NAND portion 26A can be a permanent storage for registers and P2L mapping table.
FIG. 7b (when DRAM 14G is accessible/enabled) provides operational details for NAND portions 26A, SRAM 24 and DRAM portion 14G identified in FIG. 5, where SRAM 24 and DRAM 14G form the extended random access memory. As shown in FIG. 7b , the NAND portion 26A on the left can store a small boot section from which to load first pieces of a code to initialize the memory controller. In addition, the NAND portion 26A can store information from which it would be beneficial to reinitialize after a power cycle. The SRAM 24 (as in FIG. 7a ) can provide run time execution memory storing of necessary code to run the MM 20 and storing at least pieces of metadata like P2L mapping data. The NAND portion 26A on the right can also be mainly a permanent storage for registers and P2L mapping table. The main difference with FIG. 7a is now in the enabled state of the DRAM portion 14G which becomes an extension of the SRAM 24 (forming the extended random access memory) for storing run time data like state information, P2L mapping table, etc., especially for data which is needed to reinitialize the MMCO 22 after power cycle as fast as possible.
It is noted that the areas 26A shown in 7 a and 7 b could be also beside each other. Left side could be realized also by some boot ROM embedded in the MMCO, at least partly. It is further noted that memory map of the MMCO could be also a kind of a virtual map, not physical (as shown in FIGS. 7a and 7b ).
FIG. 8 demonstrates another aspect of the embodiments shown in the flow chart in FIG. 6 relating operation of the MMCO 22 to a command (or an attribute in the command) from the host device 10. If the host device 10 (e.g., its CPU 12) knows that the data in the DRAM portion 14G has been compromised, it can send a command to the MM 20 to deny reading from the host system memory DRAM portion 14G thus forcing the MMCO 22 to read from the non-volatile memory like NAND portion 26A for any setting in the MM 20. Then the operation state of the MMCO 22 is read from the NAND portion 26A.
If the host device 10 (CPU 12) does not impose any restriction on reading from the DRAM portion 14G, then the operation state of the MMCO 22 is read from the DRAM portion 14G and possibly from the NAND portion 26A (for low-priority data).
It is noted that, the commands/attributes send by the host device 10 to the memory module 20 (e.g., through the interface 22 a as shown in FIG. 5a ) may have different levels of enforcement on the memory module controller 22. For example, the command for denying reading from the host system memory, i.e., from the DRAM portion 14G in reference to FIG. 8, may have a high enforcement level. Similarly another command or an attribute in a command of the host device forbidding writing in the host system memory (e.g., no extra space is available) additional information related to the operational state data may be also a high enforcement level command which cannot be overridden by the MMCO 22. An example of a low enforcement command/attribute by the host device may be when it enables utilization of 14G (or is not disabling it), leaving it up to the MMCO to decide. Low enforcement command/attribute could also be indication of power down by the host device, so that the MMCO can make the decision whether to perform read/write operation with the state data or not.
FIG. 9 illustrates one non-limiting embodiment of the host device 10 used with the mass storage memory device 20, referred to in FIG. 6 simply as a memory card 20. The mass storage memory device 20 can be removable or it can be embedded in the device 10. In this exemplary embodiment the host device 10 is embodied as a user equipment (UE), shown in both plan view (left) and sectional view (right). In FIG. 9 the host device (UE) 10 has a graphical display interface 120 and a user interface 122 illustrated as a keypad but understood as also encompassing touch screen technology at the graphical display interface 120 and voice recognition technology received at a microphone 124. A power actuator 126 controls the device being turned on and off by the user. The exemplary UE 10 may have a camera 128 which is shown as being forward facing (e.g., for video calls) but may alternatively or additionally be rearward facing (e.g., for capturing images and video for local storage). The camera 128 is controlled by a shutter actuator 30 and optionally by a zoom actuator 32 which may alternatively function as a volume adjustment for the speaker(s) 34 when the camera 128 is not in an active mode.
Within the sectional view of FIG. 9 are seen multiple transmit/receive antennas 36 that are typically used for cellular communication. The antennas 36 may be multi-band for use with other radios in the UE. The operable ground plane for the antennas 36 is shown by shading as spanning the entire space enclosed by the UE housing though in some embodiments the ground plane may be limited to a smaller area, such as disposed on a printed wiring board on which the power chip 38 is formed. The power chip 38 controls power amplification on the channels being transmitted and/or across the antennas that transmit simultaneously where spatial diversity is used, and amplifies the received signals. The power chip 38 outputs the amplified received signal to a radio frequency (RF) chip 40 which demodulates and downconverts the signal for baseband processing. A baseband (BB) chip 42 detects the signal which is then converted to a bit stream and finally decoded. Similar processing occurs in reverse for signals generated in the host device 10 and transmitted from it.
The processors 38, 40, 42, 44, 46, 50, if embodied as separate entities in a UE 10, may operate in a slave relationship to the main processor (CPU) 12, which may then be in a master relationship to them. Certain embodiments may be disposed across various chips and memories as shown, or disposed within another processor that combines some of the functions described above for FIG. 9. Any or all of these various processors of FIG. 9 access one or more of the various memories, which may be on chip with the processor or separate from the chip with the processor. Note that the various integrated circuits (e.g., chips 38, 40, 42, etc.) that were described above may be combined into a fewer number than described and, in a most compact case, may all be embodied physically within a single chip.
dynamically managing, by a memory module controller of a memory module, storage of operational state data into an extended random access memory, the extended random access memory including random access memory in the memory module and random access memory in a host device, the operational state data for operating the memory module controller; and
determining, by the memory module controller in association with a wake up from a shut down state or from a sleep state of the memory module, whether to read at least some of the operational state data from the random access memory in the host device, the determining being based at least on a transmission, from the host device, indicating that the random access memory in the host device is compromised.
2. The method as in claim 1, wherein a part of the operational state data is stored by the memory module controller in a non-volatile memory in the memory module.
3. The method as in claim 1, wherein the at least some of the operational state data is stored in a dedicated portion of the random access memory in the host device.
4. The method as in claim 1, wherein the operational state data includes at least high priority and low priority data, the high priority data being stored in the random access memory in the host device, and the low priority data being stored in a non-volatile memory in the memory module.
5. The method as in claim 4, wherein the high priority data includes at least state information.
6. The method as in claim 1, wherein the operational state data comprises one or more of: state information, a logical to physical mapping table, or register settings.
7. The method as in claim 1, wherein before the dynamically managing, the method further comprises:
receiving from the host device a command or an attribute in a command to disable the memory module, wherein the dynamically managing comprises reconfiguring, by the memory module controller responsive to the command or the attribute in the command, storage of the operational state data into both the random access memory in the host device and a non-volatile memory in the memory module.
8. The method as in claim 7, wherein the dynamically managing includes duplicating at least part of the operational state data in both the random access memory in the host device and the non-volatile memory in the memory module.
9. The method as in claim 1, wherein the memory module transitions into the sleep state responsive to completion of a predefined timeout, and the dynamically managing comprises, responsive to the completion of the predefined timeout, reconfiguring the storage of the operational state data into the random access memory in the host device and a non-volatile memory in the memory module.
receiving from the host device another transmission indicating that the random access memory in the host device will be shut down; and
responsive to the other transmission, further dynamically configuring by the memory module controller the storage of the operational state data into a non-volatile memory in the memory module.
restoring, by the memory module controller of the memory module, in association with the wake up from the shut down or the sleep state of the memory module, responsive at least to the random access memory in the host device being compromised, the operational state data using a non-volatile memory in the memory module.
receiving from the host device a command to disable the memory module, the command or an attribute in the command indicating that the random access memory in the host device will be shut down; and
responsive at least to the command, dynamically reconfiguring by the memory module controller the storage of the at least some of the operational state data into a non-volatile memory in the memory module.
13. The method of claim 12, further comprising, in association with the wake up from the shut down state or from the sleep state of the memory module, initializing the memory module using at least a portion of the at least some of the operational state data stored in the non-volatile memory in the memory module.
receiving from the host device another transmission indicating that the random access memory in the host device is being enabled; and
responsive to the other transmission, dynamically configuring by the memory module controller the storage of at least a portion of the at least some of the operational state data into the random access memory in the host device.
receiving from the host device a command or an attribute in a command forbidding writing additional information related to the operational state data to the random access memory in the host device.
16. The method as in claim 1, wherein a setting of the memory module indicates to read the at least some of the operational state data from the random access memory in the host device.
17. The method as in claim 16, wherein the setting of the memory module includes the memory module controller is to default to restoring at least a part of the operational state data from the random access memory in the host device.
overriding the setting of the memory module based at least partly upon the transmission from the host device indicating that the random access memory in the host device is compromised; and
restoring the at least a part of the operational state data from a non-volatile memory in the memory module.
19. The method as in claim 1, further comprising restoring the at least some of the operational state data from a non-volatile memory in the memory module based on the determining.
a memory module controller configured to:
dynamically manage storage of operational state data for operating the memory module controller into an extended random access memory, the extended random access memory including the memory and random access memory in a host device; and
determine, in association with a wake up from a shut down or sleep state of the memory module and based at least on a transmission from the host device indicating that the random access memory in the host device is compromised, whether to read at least some of the operational state data from the random access memory in the host device.
21. The memory module of claim 20, wherein the memory module controller is further configured to store at least a part of the operational state data in the non-volatile memory.
22. The memory module of claim 20, wherein the memory module is in the host device.
23. The memory module as in claim 20, wherein:
the memory of the memory module is at least one of one of a static random access memory, a magnetic random access memory, a phase change random access memory, or a resistive random access memory; and
the random access memory in the host device is one of a dynamic random access memory, a magnetic random access memory, a phase change random access memory, or a resistive random access memory.
24. The memory module as in claim 20, wherein the memory module controller is further configured to determine, in association with the wake up from the shut down state or from the sleep state of the memory module, whether to read at least a portion of the at least some of the operational state data from the random access memory in the host device based at least further on a setting of the memory module.
25. The memory module as in claim 24, wherein the setting of the memory module configures the memory module controller to default to restoring at least a part of the at least some of the operational state data from the random access memory in the host device.
26. The memory module as in claim 25, wherein the memory module controller is further configured to:
override the setting of the memory module based at least partly upon the transmission from the host device indicating that the random access memory in the host device is compromised; and
restore the operational state data from the non-volatile memory.
27. The memory module as in claim 20, wherein the memory module controller is further configured to read at least a portion of the at least some of the operational state data from the random access memory in the host device based on another transmission indicating that the random access memory in the host device is not compromised.
28. The memory module as in claim 20, wherein the memory module controller is further configured to restore the at least some of the operational state data from the non-volatile memory based on the transmission.
29. The memory module as in claim 20, wherein the operational state data includes at least high priority data and low priority data, the high priority data being stored in the random access memory in the host device, and the low priority data being stored in the non-volatile memory.
30. The memory module as in claim 20, wherein the memory module controller is further configured to:
receive from the host device a command or an attribute in a command to disable the memory module; and
responsive to the command or the attribute in the command, reconfigure storage of the operational state data into both the random access memory in the host device and the non-volatile memory.
31. The memory module as in claim 30, wherein the memory module controller is further configured to duplicate at least a part of the operational state data in both the random access memory in the host device and the non-volatile memory.
32. The memory module as in claim 20, wherein the memory module controller is further configured to, responsive to completion of a predefined timeout by the memory module subsequent to which the memory module transitions into the sleep state, reconfigure the storage of the operational state data into the random access memory in the host device and the non-volatile memory.
33. The memory module as in claim 20, wherein the memory module controller is further configured to:
receive from the host device another transmission indicating that the random access memory in the host device will be shut down; and
dynamically configure, responsive to the other transmission, the storage of the operational state data into the non-volatile memory.
34. The memory module as in claim 20, wherein the memory module controller is further configured to, in association with the wake up from the shut down or sleep state of the memory module, responsive at least to the random access memory in the host device being compromised, restore the operational state data using the non-volatile memory.
35. The memory module as in claim 20, wherein the memory module controller is further configured to:
receive from the host device a command to disable the memory module, the command or an attribute in the command indicating that the random access memory in the host device will be shut down; and
responsive at least to the command, dynamically configure the storage of the at least some of the operational state data into the non-volatile memory.
36. The memory module as in claim 35, wherein the memory module controller is further configured to, in association with the wake up from the shut down state or from the sleep state of the memory module, initialize the memory module using the at least some of the operational state data stored in the non-volatile memory.
37. The memory module as in claim 35, wherein the memory module controller is further configured to:
receive from the host device a subsequent transmission indicating that the random access memory in the host device is being enabled; and
dynamically configure, responsive to the subsequent transmission, the storage of the at least some of the operational state data into the random access memory in the host device.
38. The memory module as in claim 20, wherein the memory module controller is further configured to determine whether to read at least some of the operational state data from the random access memory in the host device further based on another transmission from the host device indicating that the random access memory in the host device is unavailable.
39. The memory module as in claim 20, wherein the memory module controller is further configured to determine whether to read at least some of the operational state data from the random access memory in the host device further based on another transmission from the host device indicating that the memory module is permitted to read the operational state data from any source.
40. The memory module as in claim 20, wherein the memory module controller is further configured to determine whether to read at least some of the operational state data from the random access memory in the host device further based on another transmission from the host device indicating that the memory module is denied permission to read the operational state data from the random access memory in the host device.
41. A host device, comprising:
a random access memory configured to store operational state data for operating a memory module controller of a memory module; and
a processor configured to transmit to the memory module, in association with a wake up from a shut down state or from a sleep state of the memory module, an indication that the random access memory is compromised.
42. The host device of claim 41, wherein the indication is part of a command transmitted to the memory module to wake up from the shut down state or from the sleep state of the memory module.
43. The host device of claim 41, wherein the random access memory includes a portion allocated to the memory module, and wherein the at least some of the operational state data for operating the memory module controller is stored in the portion.
44. The host device of claim 41, wherein the operational state data includes high priority data and low priority data, the high priority data being stored in the random access memory.
45. The host device of claim 41, wherein at least portions of the operational state data are not stored in the random access memory.
46. The host device of claim 41, further comprising the memory module, the memory module configured to restore, in association with the wake up from the shut down state or from the sleep state of the memory module, and responsive at least to the random access memory in the host device being compromised, the operational state data using a non-volatile memory in the memory module.
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