Source: http://www.google.com/patents/US8022556?dq=5,579,517
Timestamp: 2014-07-14 08:31:00
Document Index: 141117232

Matched Legal Cases: ['Application No. 2004', 'Application No. 07', 'Application No. 09', 'Application No. 10', 'Application No. 11', 'Application No. 2001']

Patent US8022556 - Electrical component having a reduced substrate area - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn electrical component includes a substrate, component structures on the substrate, and solder metal platings electrically connected to the component structures. The substrate is electrically and mechanically connected in a flip chip arrangement to a carrier via connections formed by solder bumps. The...http://www.google.com/patents/US8022556?utm_source=gb-gplus-sharePatent US8022556 - Electrical component having a reduced substrate areaAdvanced Patent SearchPublication numberUS8022556 B2Publication typeGrantApplication numberUS 10/542,841PCT numberPCT/EP2003/014349Publication dateSep 20, 2011Filing dateDec 16, 2003Priority dateJan 20, 2003Also published asDE10301934A1, US20070029679, WO2004066491A1Publication number10542841, 542841, PCT/2003/14349, PCT/EP/2003/014349, PCT/EP/2003/14349, PCT/EP/3/014349, PCT/EP/3/14349, PCT/EP2003/014349, PCT/EP2003/14349, PCT/EP2003014349, PCT/EP200314349, PCT/EP3/014349, PCT/EP3/14349, PCT/EP3014349, PCT/EP314349, US 8022556 B2, US 8022556B2, US-B2-8022556, US8022556 B2, US8022556B2InventorsPeter Selmeier, Tobias KremsOriginal AssigneeEpcos AgExport CitationBiBTeX, EndNote, RefManPatent Citations (34), Non-Patent Citations (6), Classifications (19), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetElectrical component having a reduced substrate areaUS 8022556 B2Abstract An electrical component includes a substrate, component structures on the substrate, and solder metal platings electrically connected to the component structures. The substrate is electrically and mechanically connected in a flip chip arrangement to a carrier via connections formed by solder bumps. The solder bumps mate to the solder metal platings. At least one of the solder bumps is on a first solder metal plating. The first solder metal plating has first and second dimensions, where the first dimension is larger than the second dimension.
TECHNICAL FIELD The present invention relates to the chip layout of electrical components, whose substrate is electrically and mechanically connected in a flip chip arrangement to a carrier via bump connections formed by solder bumps.
BACKGROUND SAW components typically contain one or more piezoelectric substrates and a housing and/or a carrier for receiving the piezoelectric substrate(s).
A typical DMS filter has two acoustic tracks, each of which comprises a middle interdigital transducer having two busbars and bond pads, framed by a further interdigital transducer on each side and two reflectors on the two ends of these interdigital transducers. The bond pads of the middle interdigital transducer are, for example, connected on one side to the ground bond pads of the neighboring reflector, on the other side, the busbar is electrically connected to the busbar of the corresponding interdigital transducer from the second track. The connection pad used for the connection is electrically �floating� in relation to the electrical potentials of the middle interdigital transducer.
If the two features �ellipsoidal and/or non-round solder metal plating� and �beveled reflector structures� are combined, a further reduction of the chip area may be achieved in many applications.
DESCRIPTION OF THE DRAWINGS FIG. 1 shows a known 2-track DMS filter having round solder metal platings
DETAILED DESCRIPTION FIG. 1 shows, in the same top view, a known DMS filter for symmetrical/symmetrical operation without impedance transformation. Two acoustic tracks AS1, AS2, which in turn comprise the middle interdigital transducer, two external interdigital transducers, and a reflector at each end, are positioned on a piezoelectric substrate S. The busbars, which each point outward, of the two middle interdigital transducers are split and connected to a solder metal plating�round in this case�in each case. In each case the interdigital fingers of the inwardly directed polarity of the middle interdigital transducer each are connected to a single busbar respectively. This busbar is electrically �floating� and therefore not expanded to the size of a bond pad. The external interdigital transducers are connected on one side to the ground bond pad of the neighboring reflector, on the other side, the busbar is electrically connected to the busbar of the corresponding interdigital transducer from the second track. The connection pads are also electrically �floating�. The solder metal plating for the input is identified by E1 and E2, that one for the output by A1 and A2.
FIG. 4 shows a third embodiment according to the present invention. This comprises a modified chip layout for a DMS filter for asymmetrical/symmetrical operation with impedance transformation. The DMS filter comprises two acoustic tracks, which in turn comprise the middle interdigital transducer, the two external interdigital transducers, and a reflector at each end. The middle interdigital transducer of the first track AS1 is split at the external busbar and connected to two different busbars. The symmetrical operation thus results. The interdigital fingers of the inwardly directed polarity of the middle interdigital transducer are connected to a single busbar. This busbar is electrically �floating� and therefore not expanded to the size of a bond pad.
The external interdigital transducers are connected on one side to the ground bond pad of the neighboring reflector, and on the other side the busbar is electrically connected to the busbar of the corresponding interdigital transducer from the second track AS2. The connection pads are also electrically �floating�.
FIG. 6 shows a fifth embodiment according to the present invention of a modified chip layout for a DMS filter for asymmetrical/asymmetrical or asymmetrical/symmetrical operation without impedance transformation. The DMS filter comprises two acoustic tracks AS1, AS2, which in turn comprise the middle interdigital transducer, the two external interdigital transducers, and a reflector at each end. The bond pads of the middle interdigital transducer are electrically insulated. The external interdigital transducers are connected on one side to the ground bond pads of the neighboring reflector, and on the other side to the busbar of the corresponding interdigital transducer from the second track. The connection pad is electrically �floating� in relation to the electric potentials of the middle interdigital transducer.
FIG. 9 shows a modified chip layout for a DMS filter for asymmetrical/asymmetrical or asymmetrical/symmetrical operation without impedance transformation as a seventh embodiment. The DMS filter comprises two acoustic tracks, which in turn comprise the middle interdigital transducer, the two external interdigital transducers, and a reflector at each end. The bond pads of the middle interdigital transducer are electrically insulated. The external interdigital transducers are connected on one side to the ground bond pad of the neighboring reflector, and on the other side the busbar is electrically connected to the busbar of the corresponding interdigital transducer from the second track. The connection pad is electrically �floating� in relation to the electrical potentials of the middle interdigital transducer.
There is a multiport resonator at each of the symmetrical gates LA1, LA2; LA3, LA4, an insulated bond pad being electrically connected to one half of each multiport resonator. The DMS track is located between the two multiport resonators. The DMS track comprises a middle interdigital transducer, the two external interdigital transducers, and a reflector at each end. The interdigital fingers of the middle interdigital transducer are split on one side and their busbars are each electrically connected to an interdigital transducer of the second multiport resonator. On the other side, they connected to a single busbar. This busbar is electrically �floating� and therefore not expanded to the size of a bond pad.
The DMS track comprises a middle interdigital transducer, the two external interdigital transducers, and a reflector at each end. The interdigital fingers of the middle interdigital transducer are divided on the side of the symmetrical gate and their busbars are each electrically connected to an interdigital transducer of the multiport resonator. On the other side, they are connected to a single busbar. This busbar is electrically �floating� and therefore not expanded to the size of a bond pad.
To electrically connect two series resonators, the output busbar of the first series resonator RS1 is linked to the input busbar of the second series resonator RS2 using a line. A branch of this connection line to the input busbar of the parallel resonator RP1 generates the electrical connection of the parallel resonator lying between them. Only the external busbar of the parallel resonators RP and of the first and last series resonators RS1, RS5, to which no further resonator is connected to, are expanded into bond pads. The reflectors are either electrically connected to the ground bond pad LAm or �floating�. In order to obtain the smallest possible chip dimension in the x and y directions, the solder metal platings for the insulated bond pads LA are placed laterally next to the tracks and implemented as ellipsoidal, so that the acoustic tracks may be shifted close together. Depending on the application, two or even four ground bond pads may be used.
use of more than one chip on a housing and/or carrier, each of which is implemented per se according to the present invention, however use of a different filter technology than those described here another shape of the solder metal platings components other than SAW or BAW filters or combination of SAW or BAW filters with further components. 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