Source: https://patents.google.com/patent/CN105047634A/en
Timestamp: 2020-01-18 02:14:10
Document Index: 709749693

Matched Legal Cases: ['art 110', 'art 112', 'art 110', 'art 112', 'art 110', 'art 112', 'art 110', 'art 112', 'art 110', 'art 112', 'art 110', 'art 112', 'art 110', 'art 110', 'art 110', 'art 112', 'art 110', 'art 110', 'art 110', 'art 112', 'art 110', 'art 110', 'art 110', 'art 112', 'art 112', 'art 112', 'art 110', 'art 112', 'art 110', 'art 112', 'art 110', 'art 112', 'art 110', 'art 112', 'art 110', 'art 112', 'art 210', 'art 212', 'art 210', 'art 210', 'art 210', 'art 210', 'art 210', 'art 210', 'art 212', 'art 212', 'art 212', 'art 210', 'art 210', 'art 212', 'art 212', 'art 217', 'art 212', 'art 210', 'art 212', 'art 212', 'art 212', 'art.\n8']

CN105047634A - Isolation between semiconductor components - Google Patents
Isolation between semiconductor components Download PDF
CN105047634A
CN105047634A CN201510015097.8A CN201510015097A CN105047634A CN 105047634 A CN105047634 A CN 105047634A CN 201510015097 A CN201510015097 A CN 201510015097A CN 105047634 A CN105047634 A CN 105047634A
CN201510015097.8A
约翰·康斯坦丁诺
蒂姆瓦·卢克
艾哈迈德·阿什拉夫扎德
罗伯特·L·克劳泽
埃坦·莎萨穆
玛丽亚·克莱门斯·伊皮尔·基诺内斯
雅努什·布雷泽克
2015-01-09 Priority to US14/593,642 priority patent/US9735112B2/en
2015-01-09 Priority to US14/593,642 priority
2015-01-12 Application filed by 飞兆半导体公司, 快捷半导体(苏州)有限公司 filed Critical 飞兆半导体公司
2015-11-11 Publication of CN105047634A publication Critical patent/CN105047634A/en
The present invention relates to isolation between semiconductor components. In some general aspects, an apparatus may include a first semiconductor die near to a first lead frame part, a second semiconductor die near to a second lead frame part, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.
Isolation between semiconductor device
The priority of the U.S. Provisional Patent Application 61/926,030 that patent application claims was submitted on January 10th, 2014 and rights and interests, this patent application is incorporated herein by reference accordingly in full.
This explanation relates to the isolation of semiconductor device.
Isolator can be used, to isolate these circuit but to permit the exchanges data between these circuit between with multiple semiconductor circuits of different voltage level work.Routinely, these isolation can comprise optical coupler, capacitor, transformer, small magnetic coil or huge magnetic register (GMR) as the isolated component between semiconductor circuit.But, in some conventional methods, isolator can by integrated (or structure) in semiconductor device itself, metal capacitance between its use metal layer at top and bottom metal layers (and intermediate layer) forms the insulator based on electric capacity, and this insulation is what to be provided by the oxide skin(coating) between the metal level in semiconductor device main body or thin polyimides band.The thickness of the dielectric stack between capacitor top spacing contact and bottom spacing contact determines and insulate penetration range and limit the maximum isolation voltage that can realize.Routinely, these isolators are restricted in its insulation penetration range, and this may reduce insulation property and increase static discharge (ESD) risk, thus reduces the insulation characterisitic of device.
In some are general, device can comprise the first semiconductor element being set to contiguous first leadframe part, second semiconductor element being set to contiguous second leadframe part, and is couple to the capacitive character buffer circuit of the first semiconductor element and the second semiconductor element.Capacitive character buffer circuit can be arranged on the first semiconductor element and the second semiconductor element is outside.First semiconductor element, the second semiconductor element and capacitive circuit can be included in the mouldings of semiconductor packages.
The details of one or more concrete enforcement is given in accompanying drawing and following explanation.Other features will be apparent from explanation and accompanying drawing and in accessory rights requirement.
Fig. 1 shows the device for providing the isolation between multiple semiconductor element;
Fig. 2 A to Fig. 2 E shows the various views of the semiconductor packages using reversion substrate and flip-chip configuration;
Fig. 3 shows the pretreatment process of the semiconductor packages for structural map 2A to Fig. 2 E;
Fig. 4 shows the encapsulation assembling flow path of the semiconductor packages for structural map 2A to Fig. 2 E;
Fig. 5 shows the handling process of the semiconductor packages for structural map 2A to Fig. 2 E;
Fig. 6 A and Fig. 6 B shows the view of semiconductor packages;
Fig. 7 A to Fig. 7 C shows the perspective view of isolated substrate bridger;
Fig. 8 A to Fig. 8 C shows the various views of isolated substrate bridger;
Fig. 9 A to Fig. 9 E shows the various views of semiconductor packages;
Figure 10 shows semiconductor packages; And
Figure 11 shows the handling process of the semiconductor packages for structural map 9 or Figure 10.
This paper's is open relevant to a kind of semiconductor device, this semiconductor device provides based on non-optical capacitive character buffer circuit between the first semiconductor element and the second semiconductor element, make capacitive character buffer circuit not only provide the electric current between the first semiconductor element and the second semiconductor element to isolate, and serve as to cross over the transmission system that capacitive character buffer circuit transmits data.In addition, to be provided at the first semiconductor element and the second semiconductor element outside but in the mouldings of semiconductor packages for capacitive character buffer circuit.First semiconductor element and the second semiconductor element can be couple to lead frame (or its part).In other words, contrary with routine techniques, not in the main body of semiconductor element itself, form (or structure) isolator, but capacitive character buffer circuit is set in semiconductor element outside (but still in semiconductor mouldings), make it possible to increase insulation penetration range.Therefore, the semiconductor device with capacitive character buffer circuit can be supported in the application in relative compact encapsulation with relatively high-voltage level, thus sufficient isolation is provided between multiple semiconductor element, permit crossing over insulation barrier in a secure manner simultaneously and carry out relatively transmitting fast.
Fig. 1 shows the device 100 for providing the isolation between multiple semiconductor element.In some are specifically implemented, device 100 provides the electric current between multiple semiconductor element to isolate.Electric current isolation can refer to such concept: the function section of insulating electron device is to stop or substantially stop current flowing (such as, not having direct conduction path) but allow (such as electric capacity) by other means to carry out information exchange.Device 100 can comprise be set to contiguous (such as, disposed thereon, be couple to, be directly coupled to) the first semiconductor element 102 of the first leadframe part 110, be set to contiguous (such as, disposed thereon, be couple to, be directly coupled to) the second semiconductor element 108 of the second leadframe part 112, and be couple to the first semiconductor element 102 via the first conductive component 104-1 and be couple to the capacitive character buffer circuit 106 of the second semiconductor element 108 via the second conductive component 104-2.In some are specifically implemented, device 100 can be included in the mouldings (not shown) of semiconductor packages.Such as, the mouldings of semiconductor packages can comprise the material of one or more type (such as, when comprising polytype material, in mold compound form), such as metal, plastics, resin, epoxy resin, phenolic hardeners, silica-base material, pigment, glass, ceramic shell and/or like this, and can parts containing (or encapsulating) at least Fig. 1.
First semiconductor element 102 and/or the second semiconductor element 108 can be or comprise the semi-conducting material with integrated circuit, processor, microprocessor, memory and/or any semiconductor device or circuit.In some are specifically implemented, one or more in semiconductor element 102,108 can comprise multiple semiconductor device.In some are specifically implemented, the first semiconductor element 102 can work under the voltage level different from the second semiconductor element 108.In some are specifically implemented, one or more in semiconductor element 102,108 can be and maybe can comprise discrete-semiconductor device.Specifically, one or more in semiconductor element 102,108 can be maybe can comprise horizontal orientation transistor device (such as, lateral mosfet (MOSFET) device) and/or machine-direction oriented transistor device (such as, vertical nMOSFET device).In some are specifically implemented, one or more in semiconductor element 102,108 can be and maybe can comprise bipolar junction transistor (BJT) device, diode component, insulated gate bipolar transistor (IGBT) device and/or like this.In some are specifically implemented, one or more in semiconductor element 102,108 can be and maybe can comprise circuit, such as filter circuit, controller circuitry, drive circuit, telecommunication circuit (such as, receiver and/or reflector) and/or like this.In some are specifically implemented, one or more in semiconductor element 102,108 can be the circuit of any type of the function for any type.In some are specifically implemented, one or more the comprised dedicated logic circuit in semiconductor element 102,108, combinational logic, field programmable gate array (FPGA), application-specific integrated circuit (ASIC) (ASIC).In some are specifically implemented, semiconductor element 102 and/or semiconductor element 108 are alternately module (such as, discrete device module, packaging module).In some are specifically implemented, each one comprised single integrated circuit in the first semiconductor element 102 and the second semiconductor element 108 or can be stand-alone integrated circuit.In some are specifically implemented, to provide additional semiconductor die with reference to the mode described by Figure 27 in semiconductor packages (such as, blend options or 3 tube core configurations).In some are specifically implemented, semi-conducting material can be the semiconductor substrate of electronic-grade silicon or any other type.As object lesson, first semiconductor element 102 can be the controller tube core comprising the controller device be formed on semi-conducting material, and the second semiconductor element 108 can be the driver tube core comprising the driver device be formed on semi-conducting material, and vice versa.In some are specifically implemented, driver tube core can be regarded as maybe can serving as output tube core.
In some are specifically implemented, the first leadframe part 110 and the second leadframe part 112 can be included in same lead frame, but can be the different piece of same lead frame.In other are specifically implemented, the first leadframe part 110 and the second leadframe part 112 can relate to two individual leads frames.Such as, the first leadframe part 110 can be included in a part for the first lead frame, and the second leadframe part 112 can be included in the second lead frame a part of separating with the first lead frame in.In any one situation, the first leadframe part 110 and the second leadframe part 112 can be the conductive structure of any type that can use in semiconductor packages, comprise copper, copper alloy, aluminium and/or like this.
In some are specifically implemented, as shown in Figure 1, the first semiconductor element 102 can be arranged on the top surface of the first leadframe part 110, and the second semiconductor element 108 can be arranged on the top surface of the second leadframe part 112.As discussed herein, term " top " and " bottom " refer to the relative position of the corresponding component when device 100/ semiconductor package is contained in certain orientation.In some are specifically implemented, the part of device 100 or can be described as top section or upward direction away from the direction (substantially along direction A1) of leadframe part 110,112.In some are specifically implemented, the part of device 100 or can be described as base section or in downward direction away from the direction (substantially along direction A1) of leadframe part 110,112.To aim at or parallel with plane A4 and orthogonal with direction A1 and A2 along plane A4 perpendicular to the inside direction A3 (showing for round dot) of paper.In concrete enforcement as herein described, vertical direction is perpendicular to certain plane, and semiconductor element 102,108 is aimed at along this plane (such as, plane A4).For the sake of simplicity, the equal user of some views in each view of the concrete enforcement described in all figure is to A1, A2, A3 and plane A4.
In addition, it should be noted that, although Fig. 1 describes the first semiconductor element 102 and the second semiconductor element 108 at top and aims at the inward flange 103 of the first leadframe part 110 and the inward flange 105 of the second leadframe part 112 respectively, the first semiconductor element 102 and the second semiconductor element 108 can be arranged on any position of the top surface along its respective leadframe part 110,112.Such as, by arranging these semiconductor elements 102,108 along direction A2 away from the position of the inward flange 103,105 of leadframe part 110,112, make the first semiconductor element 102 and the second semiconductor element 108 spaced apart further.No matter along the top surface of leadframe part position how, use the die attach material of any type (such as, conductive epoxy resin, solder projection, adhesive etc.), first semiconductor element 102 can be couple to the top surface of the first leadframe part 110, and the second semiconductor element 108 can be couple to the top surface of the second leadframe part 112.
In other are specifically implemented, first semiconductor element 102 can be arranged on (along vertical direction) above the first leadframe part 110, below the first leadframe part 110 (along vertical direction) and/or adjacent to the first leadframe part 110 (along horizontal direction), and the second semiconductor element 108 can be arranged on above the second leadframe part 112, below the second leadframe part 112 or adjacent to the second leadframe part 112.In some are specifically implemented, first semiconductor element 102 and the second semiconductor element 108 can be supported by capacitive character buffer circuit 106 at least in part, and the first semiconductor element 102 and the second semiconductor element 108 can use the attach material of conductive epoxy resin, conductive plate, solder projection or any type to be substantially couple to its respective leadframe part.
As shown in Figure 1, capacitive character buffer circuit 106 can be couple to the first semiconductor element 102 via the first conductive component 104-1, and capacitive character buffer circuit 106 can be couple to the second semiconductor element 108 via the second conductive component 104-2.In some are specifically implemented, the first conductive component 104-1 and the second conductive component 104-2 can be bonding wire, solder or epoxy resin, or their any combination.Such as, bonding wire can be conduction (such as, metal) lead-in wire, such as aluminium, copper or gold, or their any combination.Solder can be meltable electrical conductivity alloy (such as, metal alloy).In specifically implementing at one, solder can be multiple soldered ball.Epoxy resin can be the conductive epoxy resin of any type.In addition, capacitive character buffer circuit 106 can be arranged on any position relative to the first semiconductor element 102 and the second semiconductor element 108, as further described.
In general, capacitive character buffer circuit 106 can limit capacitive couplings network in isolator, and it can permit the first semiconductor element 102 and the second semiconductor element 108, transmitting data through insulating material or substrate.Such as, the first semiconductor element 102 can send data via capacitive character buffer circuit 106 to the second semiconductor element 108 or receive data from the second semiconductor element 108.Such as, capacitive character buffer circuit 106 can be the structure providing transmission path in isolated material via electric field.In some are specifically implemented, capacitive character buffer circuit 106 can comprise one, two or more transmission paths or transmission line, and they can be formed in above capacitive character buffer circuit 106, below or be embedded in the dielectric substrate of capacitive character buffer circuit 106.In some are specifically implemented, capacitive character buffer circuit 106 (or with reference to any capacitive character buffer circuit that any accompanying drawing describes) can support Differencing communication.In some are specifically implemented, capacitive character buffer circuit 106 (or with reference to any capacitive character buffer circuit that any accompanying drawing describes) can support two-way difference communication.Relative to two-way difference communication, capacitive character buffer circuit 106 can limit two-way difference communication channel.In order to realize two-way difference communication, in some are specifically implemented, capacitive character buffer circuit 106 can comprise two different transmission networks (such as, one for a direction, and another is for rightabout), wherein each transmission network can comprise pair of conductive transmission line, and this is used for carrying out differential sensing at the first semiconductor element 102 and/or the second semiconductor element 108 place to conductive transmission line.In some are specifically implemented, capacitive character buffer circuit 106 optionally comprises the single transmission network for two-way difference communication.In some are specifically implemented, two-way difference communication channel can be formed by two pairs of conductive transmission line, and such as, the first pair of conductive transmission line will in order to transmit data in one direction, and second pair of conductive transmission line will in order to transmit data in the other directions.In addition, capacitive character buffer circuit 106 can be configured to support multiple two-way channel, such as dual two-way difference communication channel (such as, eight pairs of conductive transmission line).But in general, any capacitive character buffer circuit described herein or isolated substrate bridger can support the communication network of any type.These and other features of capacitive character buffer circuit 106 further describe hereinafter.
In some are specifically implemented, capacitive character buffer circuit 106 can be configured to allowance first semiconductor element 102 and communicate under relatively high voltage level with the second semiconductor element 108, such as up to and higher than any voltage level of 20KV.As described further below, capacitive character buffer circuit 106 can provide insulation penetration range (it is described in more detail hereinafter), this insulation penetration range permitting apparatus 100 works under these high-voltage levels comparatively safely, and static discharge (ESD) or other high voltage events cause the risk of damage to reduce to isolation barrier, meet the pitch requirements be assemblied in compact semiconductor encapsulation simultaneously.
In generality is specifically implemented, capacitive character buffer circuit 106 can comprise dielectric material or substrate, the first conductive layer and the second conductive layer.In some are specifically implemented, capacitive character buffer circuit 106 can comprise dielectric substrate, and it has the conductor going up and/or be embedded in dielectric substrate being at least partially positioned at top surface, basal surface.
In some are specifically implemented, first conductive layer (also can be described as electrode, top metal pad, line, plate etc.) can be formed in going up at least partially of the top surface of dielectric substrate, and the second conductive layer (also can be described as electrode, bottom metal pad, line, plate etc.) can be formed in going up at least partially of the basal surface of dielectric material.In addition, in some are specifically implemented, dielectric substrate can be single continuous sheet, and what wherein conductor was positioned at every side of dielectric substrate goes up and/or be embedded in dielectric substrate (such as, isolated substrate bridger is specifically implemented) at least partially.In other examples, dielectric material can be the dielectric material of two independent sectors, the conductor (such as, as shown in Figure 3A) that the useful one or more bonding wire of its interlayer connects.
Dielectric substrate can be insulation or the isolated material of any type.In some are specifically implemented, dielectric substrate can be the material that dielectric constant is greater than any type of air.In some are specifically implemented, dielectric substrate can be the glass material (such as based on the glass material of silicon dioxide) of any type, burns the ceramic material (such as based on the ceramic material of aluminium oxide) of dielectric and/or any type altogether.In some are specifically implemented, the thickness of dielectric material can provide the insulation penetration range equaling or exceeding 0.1 millimeter (mm).Hereafter further illustrate insulation penetration range.The conductor of capacitive character buffer circuit 106 and dielectric material can form capacitor network in capacitive character buffer circuit 106.In simplified characterization, capacitor network can be described to use the conductive layer of capacitive character buffer circuit 106 and dielectric material to limit at least two capacitors.Then, this signal is sent to the second semiconductor element 108-by modulation signal with the capacitor making it cross over capacitive character buffer circuit 106 in electric field it can use one or more conductive transmission line by the first semiconductor element 102.
In some are specifically implemented, capacitive character buffer circuit 106 can limit the coupling network with at least two capacitor networks, and described capacitor network is such as arranged on first capacitor network at the first semiconductor element 102 top and is arranged on second capacitor network at the second semiconductor element 108 top.Each one in first capacitor network and the second capacitor network can be limited by top conductive plate, bottom conductive plate and the dielectric material be arranged between bottom conductive plate and top conductive plate.In this is specifically implemented, the base plate of the first capacitor network can be couple to the conductive pad of the first semiconductor element 102 (such as via the first conductive component 104-1, metal gasket), and the base plate of the second capacitor network can be couple to the conductive pad of the second semiconductor element 108 via the second conductive component 104-2.In addition, capacitive character buffer circuit 106 can comprise bonding wire, and it is couple to the top board of the first capacitor network and the top board of the second capacitor network.But capacitive character buffer circuit 106 can comprise other configurations, as further illustrated with reference to other accompanying drawings.
No matter how, as shown in Figure 1, capacitive character buffer circuit 106 is arranged on the first semiconductor element 102 and the second semiconductor element 108 is outside for the type of the concrete enforcement of capacitive character buffer circuit 106.Such as, each one the comprised top conductive layer (or top conductive contact pad) in the first semiconductor element 102 and the second semiconductor element 108 and bottom conductive layer.Top conductive contact pad can be contact point or the tie point of semiconductor element.In addition, these semiconductor elements 102,108 can comprise other intermediate layers and silicon dioxide layer between the conductive layers.In some are specifically implemented, the top conductive contact pad (and bottom conductive layer) that capacitive character buffer circuit 106 can be arranged on the first semiconductor element 102 and the second semiconductor element 108 is outside.But the first semiconductor element 102, second semiconductor element 108 and capacitive character buffer circuit 106 are included in the mouldings of semiconductor packages.In some are specifically implemented, the mouldings of semiconductor packages can be and maybe can comprise conductor, plastics, glass or ceramic shell, and it contains the parts of Fig. 1, comprises the first semiconductor element 102, second semiconductor element 108 and capacitive character buffer circuit 106.Like this, compared with conventional insulators, insulation penetration range can be increased, as described further below.
In some are specifically implemented, the capacitive character buffer circuit 106 (or with reference to any isolator that any accompanying drawing is discussed) discussed with reference to figure 1 can provide the insulation penetration range being more than or equal to 0.1mm, it is greater than the insulation penetration range (such as, existing digital isolation scheme only can realize the insulation penetration range of tens micron number magnitudes) that existing digital isolation scheme can realize.In some instances, insulation penetration range can based on the spacing (D3) between the first leadframe part 110 and the second leadframe part 112, and the thickness of the dielectric material of capacitive character buffer circuit 106 (T).D1, D2, D3 can refer to various distance or path.More generally, the penetration range that insulate can be restricted to the shortest path between the conducting element on the first semiconductor element side and the conducting element on the second semiconductor element side.In one example in which, the distance (D3) between the first leadframe part 110 and the second leadframe part 112 can be regarded as a path.In addition, the combination dielectric thickness (2T) of the dielectric material of capacitive character buffer circuit 106 can be regarded as another path (D1+D2).Shorter one in these two paths can limit insulation penetration range.
In limiting examples, the dielectric thickness (T) of dielectric material can be 0.5mm.Like this, in this path, insulation penetration range can be 1mm, because modulation is penetrated the thickness (via D1) of dielectric material in the first semiconductor element 102 side by signal, and penetrate thickness (T) (via the D2) of dielectric material in the second semiconductor element 108 side by again modulating.In FIG, path (D1+D2) is only shown for the sake of clarity and in one direction.Such as, relative to a direction, path (D1+D2) is shown, but this path also can in the opposite direction (D2+D1).In addition, it should be noted that any other accompanying drawing also can be this situation.The combination thickness (2T) of dielectric material can refer to that signal must be modulated and penetrate so that the thickness (such as, D1+D2) of dielectric material that is received of the one place in semiconductor element 102,108.Continue this example, if the distance (D3) between the first leadframe part 110 and the second leadframe part 112 is 0.5mm, then the penetration range that insulate will be 0.5mm, because insulation penetration range is restricted to the shortest person in two paths.Like this, according to an embodiment, the combination thickness (2T) of the dielectric material of capacitive character buffer circuit 106 can be equal to or greater than the distance (D3) between the first leadframe part 110 and the second leadframe part 112.In addition, the combination thickness (2T) of the dielectric material of capacitive character buffer circuit 106 can be restricted to any value being more than or equal to 0.1mm, and this value can be equal to or greater than the distance (D3) between the first leadframe part 110 and the second leadframe part 112.These concepts of insulation penetration range be applicable to other accompanying drawings various described herein other specifically implement.
With capacitor is integrated in semiconductor element itself contrary to provide electric current to isolate, capacitive character buffer circuit 106 is structured in the structure outside of semiconductor element (such as, surface external outside, at volumes-outer) but in semiconductor packages, make to increase insulation penetration range by required mode.Therefore, except the spacing restriction of semiconductor packages, compared with the non-optical isolation of routine be configured in by its isolator in the oxide skin(coating) of semiconductor element itself, insulation penetration range is unrestricted.Such as, the thickness of the oxide of conventional isolators is restricted due to cracking and other uniformity problems, and the penetration range that therefore insulate is limited to the value being less than 0.1mm.In addition, if use magnetic transformer (formed with capacitor and contrast), between transformer coil, then provide extra space (such as, to increase insulation penetration range) transmission path generation problem can be caused, because will signal coupling do not had.Therefore, capacitive character isolator circuit 106 can provide the insulation penetration range (D1+D2) being equal to or greater than 0.1mm when being assemblied in relatively little semiconductor packages.
Fig. 2 A shows the cross-sectional view of the semiconductor packages 200 using reversion substrate and flip-chip configuration.Fig. 2 B shows the more detailed view of a part for the cross-sectional view of Fig. 2 A.In this configuration, an end section 213 of isolated substrate bridger 201 is couple to the top surface of the first leadframe part 210, and another end section 215 of isolated substrate bridger 201 is couple to the top surface of the second leadframe part 212.In addition, the top surface of isolated substrate bridger 201 is couple to (such as with by semiconductor element 202,208, its with leadframe part 210,212 relative) contrary, semiconductor element 202,208 is couple to the same basal surface (such as, in same plane A4) for being attached leadframe part 210,212 of isolated substrate bridger 201.In this linguistic context, the configuration of the isolated substrate bridger 201 of Fig. 2 A to Fig. 2 B can be regarded as being inverted.
With reference to figure 2A, isolated substrate bridger 201 can be couple to and be arranged on the top surface of leadframe part 210,212.First semiconductor element 202 can be couple to via conductive component (such as, 232,230 and/or 236) and be arranged in a part for contiguous first leadframe part 210 of isolated substrate bridger 201.Specifically, the first semiconductor element 202 can be arranged on isolated substrate bridger 201 and is connected on the same basal surface of the first leadframe part 210.In some are specifically implemented, the first semiconductor element 202 can be arranged on certain position on the basal surface of isolated substrate bridger 201, and this position has the specific range (D4) from the first leadframe part 210.Second semiconductor element 208 can be couple to and be arranged in a part for contiguous second leadframe part 212 of isolated substrate bridger 201.Specifically, the second semiconductor element 208 can be arranged on isolated substrate bridger 201 and is connected on the same basal surface of the second leadframe part 212.In some are specifically implemented, the second semiconductor element 208 can be arranged on certain position on the basal surface of isolated substrate bridger 201, and this position has the specific range (D5) from the second leadframe part 212.Distance (D4) and distance (D5) may be the same or different, and contain any value.In some are specifically implemented, first semiconductor element 202 and the second semiconductor element 208 can be arranged on by certain mode and be couple on the same basal surface of isolated substrate bridger 201, make the first semiconductor element 202 approximate alignment first leadframe part 210 but distance (D4) place be positioned at from the first leadframe part 210, and the second semiconductor element 208 approximate alignment second leadframe part 212 but distance (D5) place be positioned at from the second leadframe part 212.
Still with reference to figure 2A, isolated substrate bridger 201 can comprise dielectric substrate, this dielectric substrate has integrated capacitor network 214, the second capacitor network 214-2 being such as configured in the first capacitor network 214-1 in a part for isolated substrate bridger 201 and being configured in another part of isolated substrate bridger 201.The structure of capacitor network 214 is further described with reference to figure 7 and Fig. 8.Isolated substrate bridger 201 can comprise be arranged on isolated substrate bridger 201 top surface (such as, relative with the surface with semiconductor element 202,208 surface) on one or more conductive transmission line 203.In some are specifically implemented, towards the position of the mid portion of isolated substrate bridger 201 on the surface that conductive transmission line 203 can be arranged on isolated substrate bridger 201.In some are specifically implemented, any position on the top surface that the part of conductive transmission line 203 can be arranged on isolated substrate bridger 201 between the first semiconductor element 202 and the second semiconductor element 208.In some are specifically implemented, conductive transmission line 203 can be copper.But in general, conductive transmission line 203 can by can the material of any type of signal transmission form.Conductive transmission line 203 can be the relative thin and long conductive strap that extend to another position dielectric substrate from the position of in dielectric material.But conductive transmission line 203 can have the structure illustrated with reference to any accompanying drawing.In other are specifically implemented, isolated substrate bridger 201 can comprise multiple conductive transmission line, makes these conductive transmission line be configured to multiple communication channel, as described further below.
With reference to figure 2A, in some are specifically implemented, the first semiconductor element 202 can be configured to transmit data (vice versa) with the second semiconductor element 208.Specifically, signal can be modulated and penetrate dielectric material (via D1), and described one or more conductive transmission line 203 is crossed in transmission, and modulation subsequently penetrates dielectric material (via D2).In this example embodiment, insulation penetration range (2T) can be limited based on the thickness of dielectric material (T).As mentioned above, if the thickness of dielectric material (T) for 0.5mm (such as, combination thickness (2T) will be 1mm, this be due to signal via D1 modulation through dielectric material and via D2 modulation through the fact of dielectric material), then the penetration range that insulate will be 1mm.Therefore, according to described embodiment, the distance (D3) between the first semiconductor element 202 and the second semiconductor element 208 can be equal to or greater than minimum combination thickness (2T).In addition, in some are specifically implemented, insulation penetration range (T) can be more than or equal to 0.1mm.
Fig. 2 B shows the more detailed view of the part 217 (such as, being described by the rectangle frame with dotted line) of the semiconductor packages 200 of Fig. 2 A.Such as, Fig. 2 B shows a part for the basal surface of isolated substrate bridger 201, the connection between the second leadframe part 212 and a part for the second semiconductor element 208.
In general, each semiconductor element 202,208 can use the electric conducting material of any type (such as solder) to be attached to the surface of isolated substrate bridger 201.In certain embodiments, each semiconductor element 202,208 can use be arranged on corresponding semiconductor tube core 202 or 208 end section on two conductive components be attached to the basal surface of isolated substrate bridger 201.In certain embodiments, each semiconductor element 202,208 can use the following to be attached to isolated substrate bridger 201:(1) be stacked on conductive component 230 between the end section of its respective leadframe part 210,212 of vicinity of semiconductor element 202,208 and the basal surface of isolated substrate bridger 201 (such as, projection), electric conducting material 232 (such as, solder) and conductive component 236; (2) conductive component 230 between another end section of another semiconductor element 202,208 of vicinity of semiconductor element 202,202 and the basal surface of isolated substrate bridger 201 is formed in (such as, projection) and electric conducting material 232 (such as, solder).
Fig. 2 B shows the more detailed view of a part for the second semiconductor element 208, the connection between the second leadframe part 212 and the end section of isolated substrate bridger 201.With reference to figure 2B, towards the end section of contiguous second leadframe part 212 of isolated substrate bridger 201 on the basal surface that conductive component 236 can be arranged on isolated substrate bridger 201.In certain embodiments, conductive component 236 can be regarded as the conductive plate that extends on the A2 of direction.Conductive component 236 can be arranged on isolated substrate bridger 201 or cover the only part of (such as, coated) isolated substrate bridger 201.In some are specifically implemented, conductive component 236 can be couple to the second leadframe part 212 via the solder of any type or adhesive connecting material, and extend along a part for the basal surface of isolated substrate bridger 201, wherein another end section of conductive component 236 is in order to be connected to the second semiconductor element 208.
Second semiconductor element 208 can be shifted from dielectric substrate via conductive component 230.In some are specifically implemented, conductive component 230 can be metal coupling, such as copper bump.In some are specifically implemented, conductive component 230 can be the extension of the second semiconductor element 208, and can be regarded as the conductive pad of the one external point of contact providing the second semiconductor element 208.Conductive component 230 can be couple to conductive component 236 via electric conducting material 232 (such as conductive solder).In other are specifically implemented, omit conductive component 230, and the conductor of the second semiconductor element 208 can be couple to conductive component 236 via electric conducting material (such as the electric conducting material of conductive epoxy resin, solder or any other type).
Fig. 2 C to Fig. 2 E shows the semiconductor packages 200 with the multipair semiconductor element communicated on single channel substrate.Fig. 2 C shows the top view of semiconductor packages 200, and Fig. 2 D shows the bottom view of semiconductor packages 200, and Fig. 2 E shows another perspective view of semiconductor packages 200.In general, Fig. 2 C to Fig. 2 E illustrates that semiconductor packages 200 has reversion substrate for multipair semiconductor element 202,208 and flip-chip configuration, and every a pair along the transmission line communication forming single channel substrate.In some are specifically implemented, each substrate can comprise two transmission lines for unidirectional Differencing communication.These two substrates can transmission signal in the opposite direction.
With reference to figure 2C to Fig. 2 E, isolated substrate bridger 201 (such as, having dielectric substrate) can connect the first semiconductor element 202 and the second semiconductor element 208.In addition, semiconductor packages 200 can comprise connect with isolated substrate bridger another to semiconductor element, its can with semiconductor element 202,208 and isolated substrate bridger 201 identical or different.As shown in Figure 2 C, isolated substrate bridger 201 can comprise be arranged on isolated substrate bridger 201 surface on multiple conductive transmission line 203.In some are specifically implemented, each isolated substrate bridger 201 can comprise two conductive transmission line 203.In addition, except the option physically separated shown in Fig. 2, extra channel or conductive transmission line 203 accessible site are in same group of semiconductor element 202,208 and same isolated substrate bridger 201.
Fig. 3 shows the pretreatment process 300 of the semiconductor packages 200 for structural map 2A to Fig. 2 E according to embodiment.Although Fig. 3 is shown as continuously orderly operating list, should be appreciated that some or all of operation or can walk abreast or repeatedly occur by different order, or can be overlapping in time.
Can on isolated substrate bridger printing solder (302), and the first semiconductor element and the second semiconductor element can be attached to isolated substrate bridger (304).Solder reflow (306) and scaling powder removing (308) can be performed.By being that the part with the first semiconductor element and the second semiconductor element is separated (310) to perform substrate (such as, ceramic substrate) by substrate cut.Therefore, pretreatment process can produce multiple part, and wherein each part comprises and is arranged on the first semiconductor element on isolated substrate bridger and the second semiconductor element.With reference to figure 3, in (311), top illustrates the end face of single part in the drawings, and bottom illustrates the back side of this part in the drawings.
Fig. 4 shows the encapsulation assembling flow path 400 of the semiconductor packages 200 for structural map 2A to Fig. 2 E.Fig. 4 can be the continuity of Fig. 3.Although Fig. 4 is shown as continuously orderly operating list, should be appreciated that some or all of operation or can walk abreast or repeatedly occur by different order, or can be overlapping in time.
Can in leadframe part printing solder or adhesive (402), and the isolated substrate bridger (404) being loaded with semiconductor element can be attached.Such as, the isolated substrate bridger of loading can be and has this isolated substrate bridger to coupling semiconductor tube core, as shown in (411) of Figure 15.Solder reflow/adhesive solidification (406), scaling powder removing (if using solder) (408) and plasma cleaning (410) can be performed.Then, can molded semiconductor device and to its carry out molded after baking (PMB) (412).Prune and be shaped (414), electric test (416) can be performed, prune and be shaped (418), and comprise the refine (420) of mark and TNR.
Fig. 5 shows the handling process 500 of the semiconductor packages 200 for structural map 2A to Fig. 2 E according to embodiment.Such as, handling process 500 can be the alternative arrangement of the handling process of Fig. 3 and Fig. 4.Although Fig. 5 is depicted as continuously orderly operating list, should be appreciated that some or all of operation or can walk abreast or repeatedly occur by different order, or can be overlapping in time.Solder printing (502), ceramic substrate attachment (504), high melting point solder backflow (506) can be performed, flux and input flip-chip attachment (508), flux and export flip-chip attachment (510), remove (512), plasma cleaning (514), molded, PMB, plating posttreatment without PB solder reflow and flux, and SRB (516), prune and be shaped (518) and test and refine (520).
Fig. 6 A to Fig. 6 B shows the semiconductor packages 600 being configured to double-channel communication equipment, and it has a pair semiconductor element 602,608 and isolated substrate bridger 601.Fig. 6 A shows the top view of semiconductor packages 600, and Fig. 6 B shows the bottom view of semiconductor packages 600.Semiconductor packages 600 can be the semiconductor packages of Fig. 2 A to 2B, and it has reversion substrate and flip-chip configuration, but is configured to dual communication channel.
With reference to figure 6A to Fig. 6 B, isolated substrate bridger 601 (such as, having dielectric substrate) can connect the first semiconductor element 602 and the second semiconductor element 608.As shown in Figure 6A, isolated substrate bridger 601 can comprise be arranged on isolated substrate bridger 601 surface on multiple conductive transmission line 603.In some are specifically implemented, isolated substrate bridger 601 can comprise two groups of two conductive transmission line 603, wherein often organizes conductive transmission line 603 and can be used as the work of differential transfer network.
Fig. 7 A to Fig. 7 C shows the various perspective views of isolated substrate bridger 701, and this isolated substrate bridger can be used for providing the isolation between a pair semiconductor element.Isolated substrate bridger 701 can be the various concrete enforcement (such as, being arranged on a pair semiconductor element on single isolated substrate bridger) of the isolated substrate bridger 701 of Fig. 2 C to Fig. 2 E, and it can comprise reversion substrate and flip-chip configuration.Fig. 7 A shows the perspective view of isolated substrate bridger 701.Fig. 7 B shows the top view of isolated substrate bridger 701.Fig. 7 C shows the bottom view of isolated substrate bridger 701.It should be noted that, compared with the view of Fig. 2 C to Fig. 2 E, isolated substrate bridger 701 is inverted (such as, in Fig. 7 A to Fig. 7 C, conductive transmission line 703 appears on the bottom of substrate, and this is contrary with the situation on the top surface of substrate of Fig. 2 C to Fig. 2 E).
With reference to figure 7A to Fig. 7 C, isolated substrate bridger 701 can comprise the multiple frame conductors 722 on two end sections of the upper surface being arranged on isolated substrate bridger 701.In some are specifically implemented, frame conductors 722 can be the conductive plate (such as, copper) for being connected to leadframe part.In addition, isolated substrate bridger 701 can comprise setting on an upper for two the tube core conductors 736 being connected to the first semiconductor element, and arranges on an upper for two the tube core conductors 736 being connected to the second semiconductor element.In some are specifically implemented, tube core conductor 736 can be regarded as capacitor pad, condenser armature and/or capacitor conductor.In some are specifically implemented, conductor 736 can have the structure based on circulator.In addition, isolated substrate bridger 701 can comprise two conductive transmission line 703 on basal surface.Conductive transmission line 703 can have the structure described with reference to any accompanying drawing.Two conductive transmission line 703 be formed on isolated substrate bridger 701 can serve as the communication channel in order to the swapping data at semiconductor element 702,708.
In some are specifically implemented, the capacitor network of isolated substrate bridger 701 can by tube core conductor 736 and conductive transmission line 703, and the dielectric material be arranged between tube core conductor 736 and conductive transmission line 703 is formed.
Fig. 8 A to Fig. 8 C shows the various perspective views of isolated substrate bridger 801, and this isolated substrate bridger can be used for providing the isolation between a pair semiconductor element.Isolated substrate bridger 801 can be the various concrete enforcement of the isolated substrate bridger 601 of Fig. 6 A to Fig. 6 B, its can comprise reversion substrate and flip-chip configuration to make multiple differential channel two-way transfer of data.Fig. 8 A shows the perspective view of isolated substrate bridger 801.Fig. 8 B shows the top view of isolated substrate bridger 801.Fig. 8 C shows the bottom view of isolated substrate bridger 801.It should be noted that, compared with the view of Fig. 6 A to 6B, isolated substrate bridger 801 is inverted (such as, in Fig. 8 A to Fig. 8 C, conductive transmission line 803 appears on the bottom of substrate, and this is contrary with the situation on the top surface of substrate of Fig. 6 A to Fig. 6 B).
With reference to figure 8A to Fig. 8 C, isolated substrate bridger 801 can comprise the multiple frame conductors 822 on two end sections of the upper surface being arranged on isolated substrate bridger 801.In some are specifically implemented, frame conductors 822 can be the conductive plate (such as, copper) for being connected to leadframe part.In addition, isolated substrate bridger 801 can comprise for being connected to two groups of two tube core conductors 836 of the first semiconductor element on upper surface, and for being connected to two groups of two tube core conductors 836 of the second semiconductor element on upper surface.In some are specifically implemented, tube core conductor 836 can be regarded as capacitor pad, condenser armature and/or capacitor conductor.Tube core conductor 836 can comprise the structure based on circle.In addition, isolated substrate bridger 801 can comprise setting two groups of two conductive transmission line 803 on the bottom.Conductive transmission line 803 can have the structure illustrated with reference to other accompanying drawings.
In some are specifically implemented, the capacitor network of isolated substrate bridger 801 can by tube core conductor 836 and conductive transmission line 803, and the dielectric material be arranged between tube core conductor 836 and conductive transmission line 803 is formed.
In some are specifically implemented; the semiconductor packages of Fig. 2 to Fig. 8 can provide some beneficial effects; such as on the opposite side of substrate, isolate transmission line and itself and other metal structure is isolated (such as; relatively good insulation blocking is provided), structural focus is simple (such as around encapsulation middle part, substrate layout; the cost of baseplate material such as pottery can be reduced), pre-plated lead frame, and/or there is no wire bonding.
Fig. 9 A to Fig. 9 E shows the various views of semiconductor packages 900, and this semiconductor packages has the first semiconductor element 902 and the second semiconductor element 904 being couple to nothing lead-in wire substrate 901 with flip-chip configuration.Fig. 9 A shows the plane graph of semiconductor packages 900.Fig. 9 B shows the end view of semiconductor packages 900.Fig. 9 C shows the finished figure of semiconductor packages 900.Fig. 9 D shows the interior view of semiconductor packages 900.Fig. 9 E shows another interior view of semiconductor packages 900.In flip-chip configuration, the first semiconductor element 902 and the second semiconductor element 908, by upside-down mounting, make its conductor (such as, conductive pad) locate (along vertical direction A1) down.Semiconductor packages 900 can be non-leaded package configuration.
As shown in Fig. 9 B to Fig. 9 E, semiconductor packages 900 comprises substrate 901.Substrate 901 can be any isolated substrate bridger discussed with reference to front figure.In some instances, the dielectric substrate of substrate 901 to be thickness be T.Semiconductor packages 900 can comprise be arranged on isolated substrate 901 top surface on the first mold compound 992-1 and be arranged on the second mold compound 992-2 on the basal surface of isolated substrate 901.First mold compound 991-1 and the second mold compound 992-2 can be epoxy resin mould produced compounds (EMC).
Semiconductor packages 900 can comprise be arranged on semiconductor packages 900 the first end section 980 and the second end section 981 on multiple stacking 990.Stacking 990 can be Ceramic copper redistribution (RDL) stacking.Each stacking 990 are connected to the different terminals of the first semiconductor element 902 and the second semiconductor element 908 via trace 991.Trace 991 can be the conductor based on metal, and it provides stacking 990 and first connectednesses between semiconductor element 902 and the second semiconductor element 908.Trace 991 can be arranged on the top surface of substrate 901, wherein stacking 990 is arranged on the end section of trace 991, and the first semiconductor element 902 and the second semiconductor element 908 are arranged on other end sections of trace 991.In some instances, the first semiconductor element 902 and the second semiconductor element 908 are couple to trace 991 via attachment component 910.Attachment component 910 can be adhesive, solder, or guide pillar and solder combinations (such as, making the first semiconductor element 902 and the second semiconductor element 908 raise a little from the top surface of substrate 901).Each stacking 990 comprise the solder terminal 994 given prominence at least partly above the outer surface of the first mold compound 992-1.
First semiconductor element 902 can and the second semiconductor element 908 isolate to stop or substantially stop current flowing between the first semiconductor element 902 and the second semiconductor element 908 (such as, there is no direct conduction path), but allow via the first capacitor network 940-1 and the second capacitor network 940-2 exchange message.First capacitor network 940-1 can comprise by condenser armature 936, transmission line 903, and is arranged on the capacitor that the substrate 901 between condenser armature 936 and transmission line 903 formed.Because the second capacitor network 940-2 comprises same parts, so omit the details of the second capacitor network 940-2 for clarity.
With reference to figure 9B, the first semiconductor element 902 and the second semiconductor element 908 can be arranged on the top surface of substrate 901, wherein the first semiconductor element 902 and the second semiconductor element 908 spacing distance D3.Condenser armature 936 is arranged on substrate 901, and condenser armature 936 is arranged between the first semiconductor element 902 and the top surface of substrate 901.Condenser armature 936 can be the material based on conducting metal.Condenser armature 936 can extend towards the second semiconductor element 908.In some instances, condenser armature 936 extends in two or more directions, and has two or more width.First semiconductor element 902 is couple to condenser armature 936 via attachment component 910.
Transmission line 903 can be couple to the basal surface of substrate 901, makes the thickness T of transmission line 903 and condenser armature 936 spacer substrate 901.Transmission line 903 can be the material based on conducting metal.Transmission line 903 can be the slender member with one or more amplification sections.In some instances, transmission line 903 can be regarded as condenser armature.Second semiconductor element 908 can be couple to embedded conductor 937 and conductor extension 938.Conductor extension 938 is couple to the second semiconductor element 908 via attachment component 910.Embedded conductor 937 can extend through substrate 901 between the second semiconductor element 908 and transmission line 901 on the A2 of direction.In some instances, embedded conductor 937 is the through holes being filled with metal (such as, being filled with copper).
By the first capacitor network 940-1, the first semiconductor element 902 can be configured to transmit data (vice versa) with the second semiconductor element 908.Such as, signal can be crossed over condenser armature 936 and send, modulation penetrates the thickness T (in the direction di) of substrate 901, transmission line 903 is crossed in transmission, embedded conductor 937 (in the direction d 2) is crossed in transmission, and the conductor extension 938 of transmission leap subsequently arrives the second semiconductor element 908.In this example embodiment, the thickness T that thickness is substrate 901 is isolated.But according to another embodiment, embedded conductor 937 and/or conductor extension 938 capacitors available plate 936 are replaced, and as shown in figure 34, thus make isolation double thickness (2T).
Figure 10 shows semiconductor packages 1000, and this semiconductor packages has the first semiconductor element 1002 and the second semiconductor element 1008 being couple to substrate 1001, and wherein condenser armature 1036 is used for the second semiconductor element 1008 by substrate 1001.Semiconductor packages 1000 can be similar to the semiconductor packages 900 of Fig. 9, and the embedded conductor 937 electricity container plate 1036 unlike Fig. 9 is replaced.Semiconductor packages 1000 comprises the substrate 1001 be arranged between the first mold compound 1092-1 and the second mold compound 1092-2.First semiconductor element 1002 and the second semiconductor element 1008 are connected to stacking 1090 via trace 1091, and stacking 1090 have solder (heap) terminal 1094.First semiconductor element 1002 is isolated, but is capacitively couple to the second semiconductor element 1008 via two capacitor networks.Relative to a capacitor network, first semiconductor element 1002 can cross over substrate 1001 (such as, from the condenser armature 1036 of the first semiconductor to transmission line 1003) send signal, make this signal spans transmission line 1003 then cross over substrate 1001 (such as, from the condenser armature 1036 of transmission line 1003 to the second semiconductor) to return.
Figure 11 shows the handling process 1100 for the semiconductor packages 900 of structural map 9 and the semiconductor packages 1000 of Figure 10 according to embodiment.Although Figure 11 is shown as continuously orderly operating list, should be appreciated that some or all of operation or can walk abreast or repeatedly occur by different order, or can be overlapping in time.Can perform pre-assembled, such as solder printing, ceramic panel attachment and solder reflow (1102).The flux (1104) of the first flip-chip can be removed, and the flux (1108) of the second flip-chip can be removed.FC solder reflow (1108) can be performed and flow and plasma cleaning (1110).Framework auxiliary ceramic panel can be performed be molded with PMC (1115), bottom package grinding (1114), without PB solder printing (1116), terminal solder reflow (1118), encapsulate cutting and separating (1120), and test, mark and TNR (1122).
In some are general, capacitive character buffer circuit can be couple to the first semiconductor element via the first conductive component, and capacitive character buffer circuit can be couple to the second semiconductor element via the second conductive component.Capacitive character buffer circuit can comprise capacitor and transmission line, and they form at least one capacitor network to transmit data between the first semiconductor element and the second semiconductor element.Capacitive character buffer circuit can comprise the first conductive layer, the second conductive layer, and is arranged on the dielectric material between the first conductive layer and the second conductive layer.Dielectric material can comprise the one in glass material and ceramic material.Capacitive character buffer circuit can comprise the dielectric thickness providing the insulation penetration range being equal to or greater than 0.1mm.Capacitive character buffer circuit can have the insulation penetration range of the minimum range be more than or equal between the first leadframe part and the second leadframe part.Capacitive character buffer circuit can comprise the differential communication channel for communicating between the first semiconductor element with the second semiconductor element.This differential communication channel can comprise the first conductive transmission line and the second conductive transmission line.Each one comprised top conductive layer in first semiconductor element and the second semiconductor element and bottom conductive layer.Capacitive character buffer circuit can be formed in top conductive layer and bottom conductive layer is outside.
In some are general, capacitive character buffer circuit can comprise: the first capacitor network, and it has the first conductive layer and the second conductive layer, wherein between the first conductive layer and the second conductive layer, is provided with dielectric material; Second capacitor network, it has the first conductive layer and the second conductive layer, wherein between the first conductive layer and the second conductive layer, is provided with dielectric material; Bonding wire, it is couple to the first conductive layer of the first capacitor and the first conductive layer of the second capacitor network.Second conductive layer of the first capacitor can be couple to the conductor of the first semiconductor element, and the second conductive layer of the second capacitor network can be couple to the conductor of the second semiconductor element.
In some are general, capacitive character buffer circuit can comprise isolated substrate bridger, and this isolated substrate bridger has dielectric material and at least one conductive transmission line, and described conductive transmission line can couple the first semiconductor element and the second semiconductor element communicatedly.At least one conductive transmission line described can comprise multiple conductive transmission line.Isolated substrate bridger can be at least partially disposed on the first semiconductor element top and be at least partially disposed on the first semiconductor element top, and at least one conductive transmission line described can be arranged on the top surface of dielectric material.Isolated substrate bridger can be arranged between the first semiconductor element and the second semiconductor element, and between the first leadframe part and the second leadframe part.At least one conductive transmission line described can be arranged on the basal surface of dielectric material.At least one conductive transmission line described can be embedded in dielectric material.Isolated substrate bridger can be arranged on the first lead portion at least partially, the top at least partially of the first semiconductor element, the second semiconductor element and the second lead portion.At least one conductive transmission line described can be arranged on the top surface of dielectric material.Isolated substrate bridger can comprise the Part II in the Part I being couple to the first semiconductor element, the region being arranged between the first semiconductor element and the second semiconductor element, and is couple to the Part III of the second semiconductor element.
In some are general, the first semiconductor element is set to contiguous first leadframe part, and the second semiconductor element is set to contiguous second leadframe part, and capacitive circuit is couple to the first semiconductor element and is couple to the second semiconductor element.Capacitive circuit can have the insulation penetration range of the minimum range be more than or equal between the first conductive component and the second conductive component.
In some are general, capacitive character buffer circuit can comprise isolated substrate bridger, and this isolated substrate bridger has dielectric material and at least one conductive transmission line, and described conductive transmission line can couple the first semiconductor element and the second semiconductor element communicatedly.At least one conductive transmission line described can comprise the multiple conductive transmission line being configured to two-way difference channel.Isolated substrate bridger can be at least partially disposed on the first semiconductor element top and be at least partially disposed on the first semiconductor element top, and at least one conductive transmission line described can be arranged on the top surface of dielectric material.Isolated substrate bridger can be arranged between the first semiconductor element and the second semiconductor element, and between the first leadframe part and the second leadframe part.At least one conductive transmission line described can be arranged on the basal surface of dielectric material.At least one conductive transmission line described can be embedded in dielectric material.
In some are general, device can comprise the first semiconductor element being set to contiguous first leadframe part, second semiconductor element being set to contiguous second leadframe part, and is set to the isolated substrate bridger of contiguous first semiconductor element and the second semiconductor element.Isolated substrate bridger can be configured to the communication between support first semiconductor element and the second semiconductor element.
In some are general, isolated substrate bridger can comprise the differential communication channel for communicating between the first semiconductor element with the second semiconductor element.This device can comprise the 3rd semiconductor element be arranged in the 3rd leadframe part.Each one comprised top conductive layer in first semiconductor element and the second semiconductor element and bottom conductive layer.Isolated substrate bridger can be formed in top conductive layer and bottom conductive layer is outside.
The concrete enforcement of various technology as herein described can realize in Fundamental Digital Circuit or in computer hardware, firmware, software or in their combination.The part of method also can by dedicated logic circuit (such as, FPGA (field programmable gate array) or ASIC (application-specific integrated circuit (ASIC))) perform, and device can be embodied as dedicated logic circuit (such as, FPGA (field programmable gate array) or ASIC (application-specific integrated circuit (ASIC))).
Concrete enforcement can realize in computing systems, this computing system comprises aft-end assembly (such as, data server), or comprise middleware component (such as, application server), or comprise front end assemblies (such as, there is the client computer (user is by this client computer and specifically implement interaction) of graphic user interface or web browser), or the combination in any of such aft-end assembly, middleware component or front end assemblies.Assembly interconnects by any form of digital data communications or medium (such as, communication network).The example of communication network comprises local area network (LAN) (LAN) and wide area network (WAN), as the Internet.
Also will be understood that, when certain one deck be called as be positioned on another layer or substrate time, it can be located immediately on another layer or substrate, or also can there is interlayer.Also will understand, be called as at element (such as layer, region or substrate) and be positioned on another element or when being connected to, being electrically connected to, being coupled to or being electrically coupled to another element, element can be located immediately on another element or connects or be coupled to another element, or can there is one or more intervening elements.By contrast, element be called as be located immediately on another element or layer or be connected directly to or be directly coupled to another element or layer time, there is not intervening elements or interlayer.Although may not use in whole embodiment term " be located immediately at ... on ", " being connected directly to " or " being directly coupled to ", to connect or the element that directly couples can be called as such situation for be located immediately on it, directly shown in figure.Can the claim of revised version patent application, to enumerate the exemplary relation described in specification or shown in figure.
Some specifically implement to use various semiconductor machining and/or encapsulation technology to realize.Some embodiments can use the various types of semiconductor processing technologies relevant to semiconductor substrate to realize, described semiconductor substrate includes but not limited to (such as) silicon (Si), GaAs (GaAs), carborundum (SiC), etc.
Although some feature of described concrete enforcement has been shown as described herein, those skilled in the art now can expect many amendments, substituted, change and equivalents.Therefore, should be appreciated that claims be intended to cover fall into described embodiment scope in these type of modifications and changes all.Should be appreciated that described embodiment only presents by way of example instead of in a restricted way, and various change can be carried out in form and details.Any portion of device as herein described and/or method can be combined with any combination, but except the combination mutually repelled.Embodiment as herein described can comprise various combination and/or the sub-portfolio of the function of described different embodiments, assembly and/or feature.
First semiconductor element, it is set to contiguous first leadframe part;
Second semiconductor element, it is set to contiguous second leadframe part; And
Capacitive character buffer circuit, it is couple to described first semiconductor element and described second semiconductor element, described capacitive character buffer circuit is arranged on described first semiconductor element and described second semiconductor element is outside, and described first semiconductor element, described second semiconductor element and described capacitive circuit are included in the mouldings of semiconductor packages.
2. device according to claim 1, wherein said capacitive character buffer circuit is couple to described first semiconductor element via the first conductive component, and described capacitive character buffer circuit is couple to described second semiconductor element via the second conductive component.
3. device according to claim 1, wherein said capacitive character buffer circuit comprises capacitor and transmission line, and described capacitor and transmission line form at least one capacitor network to transmit data between described first semiconductor element and described second semiconductor element.
4. device according to claim 1, wherein said capacitive character buffer circuit comprises the first conductive layer, the second conductive layer, and is arranged on the dielectric material between described first conductive layer and described second conductive layer.
5. device according to claim 4, wherein said dielectric material comprises the one in glass material and ceramic material.
6. device according to claim 1, wherein said capacitive character buffer circuit comprises the dielectric thickness providing the insulation penetration range being equal to or greater than 0.1mm.
7. device according to claim 1, wherein said capacitive character buffer circuit has the insulation penetration range of the minimum range be more than or equal between described first leadframe part and described second leadframe part.
8. device according to claim 1, wherein said capacitive character buffer circuit comprises the differential communication channel for communicating between described first semiconductor element with described second semiconductor element.
9. device according to claim 1, at least one in wherein said first semiconductor element and described second semiconductor element comprises top conductive layer and bottom conductive layer, and wherein said capacitive character buffer circuit is formed in described top conductive layer and described bottom conductive layer is outside.
10. device according to claim 1, wherein said capacitive character buffer circuit comprises isolated substrate bridger, described isolated substrate bridger has dielectric material and at least one conductive transmission line, and at least one conductive transmission line described couples described first semiconductor element and described second semiconductor element.
11. 1 kinds of devices, comprising:
Capacitive circuit, it is couple to described first semiconductor element and is couple to described second semiconductor element, and described capacitive circuit has the insulation penetration range of the minimum range be more than or equal between the first conductive component and the second conductive component.
12. devices according to claim 11, wherein said capacitive character buffer circuit comprises isolated substrate bridger, described isolated substrate bridger has dielectric material and at least one conductive transmission line, and at least one conductive transmission line described can couple described first semiconductor element and described second semiconductor element communicatedly.
13. devices according to claim 12, wherein said isolated substrate bridger is at least partially disposed on described first semiconductor element top and is at least partially disposed on described second semiconductor element top, and at least one conductive transmission line described is arranged on the top surface of described dielectric material.
14. devices according to claim 12, wherein said first semiconductor element and described second semiconductor element are arranged on described isolated substrate bridger top, and at least one conductive transmission line described is arranged on the basal surface of described dielectric material.
CN201510015097.8A 2014-01-10 2015-01-12 Isolation between semiconductor components CN105047634A (en)
US14/593,642 US9735112B2 (en) 2014-01-10 2015-01-09 Isolation between semiconductor components
US14/593,642 2015-01-09
CN105047634A true CN105047634A (en) 2015-11-11
CN201510015097.8A CN105047634A (en) 2014-01-10 2015-01-12 Isolation between semiconductor components
EP1763043B1 (en) 2005-09-09 2010-03-17 SGS-THOMSON MICROELECTRONICS S.r.l. Inductive structure
CN101952961B (en) 2008-02-25 2013-01-30 飞兆半导体公司 Micromodules including integrated thin film inductors and methods of making the same
CN102017142B (en) 2008-05-09 2012-08-15 国立大学法人九州工业大学 Three-dimensionally integrated semiconductor device and method for manufacturing the same
DE102015000317A1 (en) 2015-07-16
CN102194718B (en) 2015-10-14 Semiconductor device and manufacture method thereof
CN101996896B (en) 2016-01-20 Semiconductor device and manufacture method thereof
EP1089337A1 (en) 2001-04-04 Semiconductor device
CN104201162A (en) 2014-12-10 Semiconductor device, method for producing the same, millimeter-wave dielectric transmission device, method for producing the same, and millimeter-wave dielectric transmission system
2018-05-04 CB02 Change of applicant information
Applicant after: Ficho Semiconductor Co.
Applicant after: Fairchild Semiconductor (Suzhou) Co., Ltd.
Applicant before: Ficho Semiconductor Co.
Applicant before: Fairchild Semiconductor (Suzhou) Co., Ltd.