Source: https://patents.google.com/patent/US9978449B2/en
Timestamp: 2020-01-20 09:33:08
Document Index: 187359550

Matched Legal Cases: ['Application No. 104136217', 'Application No. 2015', 'Application No. 10', 'Application No. 2015', 'Application No. 2014', 'Application No. 10', 'Application No. 10', 'Application No. 101132496', 'Application No. 2014', 'Application No. 10', 'Application No. 10', 'Application No. 101132496', 'Application No. 104136217', 'Application No. 2015', 'Application No. 101132496']

US9978449B2 - Path isolation in a memory device - Google Patents
US9978449B2
US9978449B2 US15/633,454 US201715633454A US9978449B2 US 9978449 B2 US9978449 B2 US 9978449B2 US 201715633454 A US201715633454 A US 201715633454A US 9978449 B2 US9978449 B2 US 9978449B2
US15/633,454
US20170330621A1 (en
2012-09-21 Priority to US201213496378A priority
2014-12-22 Priority to US14/579,885 priority patent/US9293202B2/en
2016-02-08 Priority to US15/018,585 priority patent/US9466365B2/en
2016-09-09 Priority to US15/261,301 priority patent/US9691481B2/en
2017-06-26 Priority to US15/633,454 priority patent/US9978449B2/en
2017-06-26 Application filed by Intel Corp filed Critical Intel Corp
2017-07-14 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CASTRO, HERNAN A.
2017-11-16 Publication of US20170330621A1 publication Critical patent/US20170330621A1/en
2018-05-22 Publication of US9978449B2 publication Critical patent/US9978449B2/en
This application is a continuation of U.S. patent application Ser. No. 15/261,301, filed Sep. 9, 2016, entitled “PATH ISOLATION IN A MEMORY DEVICE”, which is a continuation of U.S. patent application Ser. No. 15/018,585, filed Feb. 8, 2016, entitled “PATH ISOLATION IN A MEMORY DEVICE”, and is now U.S. Pat. No. 9,466,365, which is a continuation of U.S. patent application Ser. No. 14/579,885, filed Dec. 22, 2014, entitled “PATH ISOLATION IN A MEMORY DEVICE”, and is now U.S. Pat. No. 9,293,202, which is a continuation of U.S. patent application Ser. No. 13/496,378, filed Sep. 21, 2012, entitled “PATH ISOLATION IN A MEMORY DEVICE,” and is now U.S. Pat. No. 8,917,534, which is a national stage application of PCT application PCT/US11/51073, filed Sep. 9, 2011, entitled “PATH ISOLATION IN A MEMORY DEVICE,” and claims priority to the PCT application. The entire specifications of which are hereby incorporated by reference in their entireties for all purposes.
a bit-line electrode coupled with a single transistor bit-line that is coupled with the plurality of memory cells;
a word-line electrode coupled with a single transistor word-line that is coupled with the plurality of memory cells, a capacitance of the word-line electrode is lower than a capacitance of the bit-line electrode, and a maximum voltage of the word-line electrode is lower than a maximum voltage of the bit-line electrode; and
write circuitry coupled with the word-line electrode, the write circuitry to perform a write operation to at least one memory cell of the plurality of memory cells.
a selection module coupled with the word-line electrode, the selection module to have current-limiting circuitry to facilitate a selection operation of the at least one memory cell, the current-limiting circuitry to include a current-mirror circuit.
sensing circuitry coupled with the word-line electrode, the sensing circuitry to perform a read operation of the at least one memory cell via a comparison of a first voltage generated responsive to a first load on the single transistor word-line to a second voltage generated by a second load to a reference current, the first load equivalent to the second load.
4. The apparatus of claim 1, wherein the plurality of memory cells are included in a three-dimensional array, the single transistor word-line is a first single transistor word-line extending in a first dimension of the three-dimensional array, the single transistor bit-line extends in a second dimension of the three-dimensional array, and the plurality of memory cells are a first plurality of memory cells, the apparatus further comprising:
a second plurality of memory cells included in the three-dimensional array, the second plurality of memory cells arranged in a stacked configuration with the first plurality of memory cells such that the second plurality of memory cells are stacked in a third dimension of the three-dimensional array; and
a second single transistor word-line coupled with the word-line electrode and further coupled with the second plurality of memory cells, the single transistor bit-line to extend between the first single transistor word-line and the second single transistor word-line.
5. The apparatus of claim 1, comprising the plurality of memory cells, the single transistor bit-line, and the single transistor word-line are part of a tile, the tile to include:
other memory cells separate from the plurality of memory cells;
other single transistor bit-lines coupled with the other memory cells;
other single transistor word-lines coupled with the other memory cells;
a first linear dimension that extends in a direction that is parallel to a lengthwise dimension of the single transistor bit-line and the other single transistor bit-lines;
a second linear dimension that extends in a direction that is parallel to a lengthwise dimension of the single transistor word-line and the other single transistor word-lines, wherein the first linear dimension is greater than the second linear dimension; and
a ratio of two single transistor word-lines for each single transistor bit-line.
6. The apparatus of claim 1, comprising the write circuitry to include a current profile generator to generate a current profile for a set or reset operation to perform the write operation to the at least one memory cell.
9. The apparatus of claim 1, the plurality of memory cells comprising phase change memory cells.
10. The apparatus of claim 9, comprising the phase change memory cells including chalcogenide glass.
a first plurality of memory cells of a three-dimensional array of memory cells;
a single transistor bit-line coupled with the first plurality of memory cells, the single transistor bit-line extends in a first dimension of the three-dimensional array of memory cells;
a first single transistor word-line coupled with the first plurality of memory cells, the first single transistor word-line extends in a second dimension of the three-dimensional array of memory cells;
a bit-line electrode coupled with the single transistor bit-line;
a word-line electrode coupled with the first single transistor word-line, a maximum voltage of the word-line electrode is lower than a maximum voltage of the bit-line electrode; and
a selection module coupled with the word-line electrode, the selection module to have current-limiting circuitry to facilitate a selection operation to at least one memory cell of the plurality of first memory cells.
a second plurality of memory cells of the three-dimensional array of memory cells, the second plurality of memory cells arranged in a stacked configuration with the first plurality of memory cells such that the second plurality of memory cells are stacked in a third dimension of the three-dimensional array of memory cells; and
sensing circuitry coupled with the word-line electrode, the sensing circuitry to perform a read operation of the first and second plurality of memory cells via a comparison of respective first voltages generated responsive to a first load on the respective first and second single transistor word-lines to a second voltage generated by a second load to a reference current, the first load equivalent to the second load.
write circuitry coupled with the word-line electrode, the write circuitry to perform a write operation to the first and second plurality of memory cells.
16. The apparatus of claim 15, comprising the write circuitry to include a current profile generator to generate a current profile for a set or reset operation to perform the write operation to the first and second plurality of memory cells.
18. The apparatus of claim 16, comprising the current profile for a rest operation to include a rectangle current profile.
19. The apparatus of claim 16, the first and second plurality of memory cells comprising phase change memory cells.
20. The apparatus of claim 19, comprising the phase change memory cells including chalcogenide glass.
a single transistor bit-line coupled with the plurality of memory cells;
a single transistor word-line coupled with the plurality of memory cells;
a word-line electrode coupled with the single transistor word-line, a maximum voltage of the word-line electrode is lower than a maximum voltage of the bit-line electrode; and
sensing circuitry coupled with the word-line electrode, the sensing circuitry to perform a read operation of at least one memory cell of the plurality of memory cells via a comparison of a first voltage generated responsive to a first load on the single transistor word-line to a second voltage generated by a second load to a reference current, the first load equivalent to the second load,
wherein the plurality of memory cells, the single transistor bit-line, and the single transistor word-line are part of a tile, the tile to include:
other memory cells separate from the plurality of memory cells
a higher number of word-lines compared to bit-lines.
a selection module coupled with the word-line electrode, the selection module having current-limiting circuitry to facilitate a selection operation of the at least one memory cell.
write circuitry coupled with the word-line electrode, the write circuitry to perform a write operation to the at least one memory cell.
24. The apparatus of claim 21, the plurality of memory cells comprising phase change memory cells.
25. The apparatus of claim 24, comprising the phase change memory cells including chalcogenide glass.
US15/633,454 2011-09-09 2017-06-26 Path isolation in a memory device Active US9978449B2 (en)
US201213496378A true 2012-09-21 2012-09-21
US14/579,885 US9293202B2 (en) 2011-09-09 2014-12-22 Path isolation in a memory device
US15/018,585 US9466365B2 (en) 2011-09-09 2016-02-08 Path isolation in a memory device
US15/261,301 US9691481B2 (en) 2011-09-09 2016-09-09 Path isolation in a memory device
US15/633,454 US9978449B2 (en) 2011-09-09 2017-06-26 Path isolation in a memory device
US15/983,746 US20180330789A1 (en) 2011-09-09 2018-05-18 Path isolation in a memory device
US15/261,301 Continuation US9691481B2 (en) 2011-09-09 2016-09-09 Path isolation in a memory device
US15/983,746 Continuation US20180330789A1 (en) 2011-09-09 2018-05-18 Path isolation in a memory device
US20170330621A1 US20170330621A1 (en) 2017-11-16
US9978449B2 true US9978449B2 (en) 2018-05-22
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CASTRO, HERNAN A.;REEL/FRAME:043004/0021