Source: https://patents.google.com/patent/US20040136360?oq=6%2C163%2C776
Timestamp: 2018-05-26 04:52:19
Document Index: 199998070

Matched Legal Cases: ['art 700', 'art 700', 'art 700', 'art 800', 'art 800', 'art 800']

US20040136360A1 - Systems and methods for serial packet synchronization in a voice processing system - Google Patents
Systems and methods for serial packet synchronization in a voice processing system Download PDF
US20040136360A1
US20040136360A1 US10689935 US68993503A US2004136360A1 US 20040136360 A1 US20040136360 A1 US 20040136360A1 US 10689935 US10689935 US 10689935 US 68993503 A US68993503 A US 68993503A US 2004136360 A1 US2004136360 A1 US 2004136360A1
US10689935
US7602816B2 (en )
[0011]FIG. 1 is a high level block diagram of a cable modem system configured for voice processing in accordance with embodiments of the present invention.
[0012]FIG. 2 is a schematic block diagram of a cable modem termination system (CMTS) in accordance with embodiments of the present invention.
[0013]FIG. 3 is a schematic block diagram of a cable modem in accordance with embodiments of the present invention.
[0014]FIG. 4 illustrates an exemplary serial packet sync data stream in accordance with embodiments of the present invention.
[0015]FIG. 5 is a schematic block diagram of a serial packet sync encoder in accordance with embodiments of the present invention.
[0016]FIG. 6 is a schematic block diagram of a serial packet sync decoder in accordance with embodiments of the present invention.
[0017]FIG. 7 is a flowchart of a method for performing serial packet encoding for synchronization in a voice processing system in accordance with embodiments of the present invention.
[0018]FIG. 8 is a flowchart of a method for performing serial packet decoding for synchronization in a voice processing system in accordance with embodiments of the present invention.
[0019]FIG. 9 illustrates an exemplary VoIP clock signal in accordance with embodiments of the present invention.
[0023]FIG. 1 is a high level block diagram of an example cable modem system 100 in accordance with embodiments of the present invention. The cable modem system 100 enables voice communications, video and data services based on a bi-directional transfer of packet-based traffic, such as Internet protocol (IP) traffic, between a cable system headend 102 and a plurality of cable modems 108 over a hybrid fiber-coaxial (HFC) cable network 110. In the example cable modem system 100, only two cable modems 108 are shown for clarity. In general, any number of cable modems 108 can be included in the cable modem system of the present invention.
[0032]FIG. 2 depicts a schematic block diagram of an implementation of the CMTS 104 of cable modem system 100, which is presented by way of example, and is not intended to limit the present invention. The CMTS 104 is configured to receive and transmit signals to and from the HFC network 110, a portion of which is represented by the optical fiber 202 of FIG. 2. Accordingly, the CMTS 104 will be described in terms of a receiver portion and a transmitter portion.
[0039]FIG. 3 depicts a schematic block diagram of an implementation of cable modem 108 of cable modem system 100, which is presented by way of example, and is not intended to limit the present invention. The cable modem 108 is configured to receive and transmit signals to and from the HFC network 110 via the coaxial connector 332 of FIG. 3. Accordingly, the cable modem 108 will be described in terms of a receiver portion and a transmitter portion.
[0050]FIG. 5 is a schematic block diagram of a serial packet sync encoder 338 in accordance with embodiments of the present invention. Serial packet sync encoder 338 is responsible for encoding the serial packet sync datastream 402. Serial packet sync encoder 338 is comprised of a serial packet sync transmitter 502 and serial packet sync encoder logic 508. In an embodiment, serial packet sync transmitter 502 is implemented in the form of a shift register. In this way, the serial packet sync datastream 402 can be synchronously fed in and out of the serial packet sync transmitter 502. When a grant is issued, the MAC 314 issues a packet sync strobe (FIG. 3) and packet sync vector 406. The packet sync strobe is a signal used to validate data or other signals, such as the packet sync vector 406, for example. In response, the packet sync vector 406 is latched into the serial packet sync transmitter 502.
[0056]FIG. 7 depicts a flowchart 700 of a method for supporting serial packet synchronization in a voice processing system in accordance with embodiments of the present invention. The invention, however, is not limited to the description provided by the flowchart 700. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings provided herein that other functional flows are within the scope and spirit of the present invention. The flowchart 700 will be described with continued reference to the example CMTS 104 and cable modem 108 of the cable modem system 100, as well as in reference to the example hardware implementation of the cable modem 108 of FIG. 3.
[0064]FIG. 8 depicts a flowchart 800 of a method for supporting serial packet synchronization in a voice processing system in accordance with embodiments of the present invention. The invention, however, is not limited to the description provided by the flowchart 800. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings provided herein that other functional flows are within the scope and spirit of the present invention. The flowchart 800 will be described with continued reference to the example CMTS 104 and cable modem 108 of the cable modem system 100, as well as in reference to the example hardware implementation of the cable modem 108 of FIG. 3.
synchronously receiving each bit of said serial packet sync datastream into a serial packet sync receiver;
a media access controller that asserts a packet sync vector in response to receiving a grant;
a serial packet sync encoder that encodes a serial packet sync datastream; and
a serial packet sync receiver that receives said serial packet sync datastream on a single pin.
17. The system of claim 12, wherein after receiving a grant, said serial packet sync datastream is comprised of said packet sync vector and said preamble.
18. The system of claim 17, wherein said preamble is a preselected unique bit sequence.
19. A system for transmitting indication of an event, comprising:
20. A system for receiving indication of an event, comprising:
a serial packet sync receiver that receives a serial packet sync datastream on a single pin,
a preamble comparator that compares said received serial packet sync datastream to determine if said received serial packet sync datastream matches a preamble and
US10689935 2003-01-13 2003-10-22 Systems and methods for serial packet synchronization in a voice processing system Expired - Fee Related US7602816B2 (en)
US43946103 true 2003-01-13 2003-01-13
US10689935 US7602816B2 (en) 2003-01-13 2003-10-22 Systems and methods for serial packet synchronization in a voice processing system
US12577526 US9634783B2 (en) 2003-01-13 2009-10-12 Systems and methods for serial packet synchronization in a voice processing system
US12577526 Continuation US9634783B2 (en) 2003-01-13 2009-10-12 Systems and methods for serial packet synchronization in a voice processing system
US20040136360A1 true true US20040136360A1 (en) 2004-07-15
US7602816B2 US7602816B2 (en) 2009-10-13
ID=32718088
US10689935 Expired - Fee Related US7602816B2 (en) 2003-01-13 2003-10-22 Systems and methods for serial packet synchronization in a voice processing system
US12577526 Active 2028-03-25 US9634783B2 (en) 2003-01-13 2009-10-12 Systems and methods for serial packet synchronization in a voice processing system
US (2) US7602816B2 (en)
KR20000069751A (en) * 1997-10-29 2000-11-25 요트.게.아. 롤페즈 Device for encoding/decoding n-bit source words into corresponding m-bit channel words, and vice versa
US9634783B2 (en) 2017-04-25 grant
US7602816B2 (en) 2009-10-13 grant
US20100040051A1 (en) 2010-02-18 application
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, ROBERT J.;REEL/FRAME:014622/0148