Source: http://www.google.com/patents/US20030139202?dq=5,960,411
Timestamp: 2014-03-13 21:10:05
Document Index: 574809361

Matched Legal Cases: ['art 1', 'art 2011', 'art 2011', 'art 6', 'art 6', 'art 20', 'art 20', 'art 20', 'art 40', 'art 40', 'art 60', 'art 60', 'art 100', 'art 120', 'art 120', 'art 130', 'art 130', 'art 6', 'art 6', 'art 60', 'art 100', 'art 128', 'art 2100']

Patent US20030139202 - Radio - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA received signal vector (X(t)) from an array antenna (#1 to #4) is subjected to frequency offset correction by a frequency offset correction part (6) and thereafter subjected to adaptive array processing. An error signal (e(t)) is referred to on the basis of an output signal (y(t)) from the adaptive...http://www.google.com/patents/US20030139202?utm_source=gb-gplus-sharePatent US20030139202 - RadioAdvanced Patent SearchPublication numberUS20030139202 A1Publication typeApplicationApplication numberUS 10/239,853PCT numberPCT/JP2001/002835Publication dateJul 24, 2003Filing dateMar 30, 2001Priority dateApr 3, 2000Also published asCN1194481C, CN1432225A, EP1274180A1, EP1274180A4, US7020492, WO2001076101A1Publication number10239853, 239853, PCT/2001/2835, PCT/JP/1/002835, PCT/JP/1/02835, PCT/JP/2001/002835, PCT/JP/2001/02835, PCT/JP1/002835, PCT/JP1/02835, PCT/JP1002835, PCT/JP102835, PCT/JP2001/002835, PCT/JP2001/02835, PCT/JP2001002835, PCT/JP200102835, US 2003/0139202 A1, US 2003/139202 A1, US 20030139202 A1, US 20030139202A1, US 2003139202 A1, US 2003139202A1, US-A1-20030139202, US-A1-2003139202, US2003/0139202A1, US2003/139202A1, US20030139202 A1, US20030139202A1, US2003139202 A1, US2003139202A1InventorsYoshiharu Doi, Takeo MiyataOriginal AssigneeYoshiharu Doi, Takeo MiyataExport CitationBiBTeX, EndNote, RefManReferenced by (7), Classifications (17), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetRadioUS 20030139202 A1Abstract A received signal vector (X(t)) from an array antenna (#1 to #4) is subjected to frequency offset correction by a frequency offset correction part (6) and thereafter subjected to adaptive array processing. An error signal (e(t)) is referred to on the basis of an output signal (y(t)) from the adaptive array and a reference signal (d(t)) held in a memory (30) in a reference signal section or a replica signal (d′(t)) output from a forced phase-locking processing part (20) in a section having no reference signal, so that a frequency offset quantity (Δθ) is extracted therefrom by an offset extraction part (100). Images(15) Claims(10)
[0033] In other words, it follows that the signal Srx1(t) transmitted from the first user in the two users is obtained in the output signal yt(t). [0034] Referring to FIG. 14, the input signal STX(t) for the adaptive array 2100 is supplied to the transmission part 1T in the adaptive array 2100, to be supplied to the first inputs of the multipliers 2015-1, 2015-2, 2015-3, . . . , 2015-n. The weight vectors w1i, w2i, w3i, . . . , wni calculated by the weight vector control part 2011 on the basis of the received signals as described above are copied and applied to the second inputs of these multipliers respectively. [0035] The input signals weighted by these multipliers are sent and transmitted to the corresponding antennas #1, #2, #3, . . . , #n through the corresponding switches 2010-1, 2010-2, 2010-3, . . . , 2010-n. [0036] The users PS1 and PS2 are identified in the following manner. A radio signal from a portable telephone set is transmitted in a frame structure. The radio signal from the portable telephone set is roughly formed by a preamble consisting of a signal series known to the radio base station and data (voice etc.) consisting of a signal series unknown to the radio base station. [0037] The signal series of the preamble includes a signal string of information for identifying whether or not this user is a desired user for making communication with the radio base station. The weight vector control part 2011 of the adaptive array radio base station 1 compares the training signal corresponding to the user A fetched from the memory 2014 with the received signal series and performs weight vector control (decision of a weight coefficient) to extract a signal seeming to include the signal series corresponding to the user PS1. [0038] In general, QPSK modulation or the like which is a modulation system based on PSK modulation is employed as a modulation system applied to transmission/receiving in a portable telephone or the like. [0039] In the PSK modulation, synchronous detection performing detection by integrating a signal synchronous with a carrier on a received signal is generally carried out. [0040] In the synchronous detection, a local oscillator generates a complex conjugate carrier synchronized with the center frequency of a modulated wave. When the synchronous detection is performed, however, frequency errors referred to as frequency offsets are generally present in oscillators on the transmission end and the receiving end. When the received signal is expressed on an IQ plane, the position of the received signal point is rotated on the receiver side due to the errors. Therefore, it is difficult to perform the synchronous detection unless compensating for the frequency offsets. [0041] Such frequency offsets are generated not only by the precision of a local oscillation frequency in the aforementioned transmission/receiving period but also by a set error, temperature fluctuation, time change and the like, and the receiving characteristic is abruptly deteriorated due to a carrier frequency component remaining in the signal input in the receiver. [0042] A technique of providing the so-called �automatic frequency control function (AFC)� in the communication system is known as a method of suppressing such carrier frequency offsets. In such a generally performed automatic frequency control function, however, there is the possibility that a sufficient operation cannot be expected under mobile communication having a transmission condition such as wide band modulation, high-speed phasing, burst signal transmission, multi-path delay distortion, common-frequency interference or the like. DISCLOSURE OF THE INVENTION [0043] An object of the present invention is to provide a radio unit employed for a base station capable of allocating a common channel to a plurality of users in a common cell by a spatial division multiple access system for compensating for a carrier frequency offset between a terminal and the base station while improving utilization efficiency of the channel. [0044] Briefly stated, the present invention provides a radio unit comprising an array antenna including a plurality of antennas and an adaptive array processing part for receiving signals from the plurality of antennas and extracting a signal from a prescribed terminal, while the adaptive array processing part includes a frequency offset compensation part for compensating for a frequency offset of a received signal in response to a supplied offset compensation quantity, and the radio unit further comprises an offset quantity detection part for receiving an output of the adaptive array processing part and extracting the frequency offset at prescribed timing and an offset compensation quantity operation part updating the offset compensation quantity on the basis of the result of detection by the offset quantity detection part. [0045] Preferably in the radio unit, the received signal is divided into a plurality of slots to be transmitted, each slot includes a first partial signal including a predetermined reference signal and a second partial signal including transmitted data, and the offset quantity detection part includes a first storage part for holding the reference signal, a forced phase-locking part forcibly synchronizing the phase of an output from the adaptive array processing part with a prescribed phase, an error signal generation part outputting the difference between the reference signal stored in the first storage part and the output from the adaptive array processing part in a period when the adaptive array processing part outputs the first partial signal while outputting the difference between an output from the forced phase-locking part and the output from the adaptive array processing part in a period when the adaptive array processing part outputs the second partial signal, and an offset extraction part for extracting the frequency offset on the basis of the output from the error signal generation part. [0046] More preferably in the radio unit, the offset compensation quantity operation part includes a second storage part for storing the offset compensation quantity at any time and a calculation part calculating an update value θ′ for the offset compensation quantity as θ′=θ+μ�Δθ on the basis of the offset compensation quantity θ stored in the second storage part and the output Δθ from the offset extraction part assuming that μ represents a prescribed coefficient. [0047] Or, more preferably in the radio unit, the offset compensation quantity operation part includes a second storage part for storing the offset compensation quantity at any time and a calculation part calculating an update value θ′ for the offset compensation quantity on the basis of the offset compensation quantity θ stored in the second storage part and the output Δθ from the offset extraction part while reducing the quantity changed in updating as the updating progresses. [0048] Or, more preferably in the radio unit, the offset compensation quantity operation part further includes a second storage part for storing the offset compensation quantity at any time and a calculation part calculating an update value θ′ for the offset compensation quantity on the basis of the offset compensation quantity θ stored in the second storage part and the output Δθ from the offset extraction part while increasing the quantity changed in updating in response to the magnitude of the absolute value of the output from the error signal generation part. [0049] Or, more preferably in the radio unit, the offset compensation quantity operation part includes a second storage part for storing the offset compensation quantity at any time and a calculation part calculating an update value θ′ for the offset compensation quantity i) on the basis of the offset compensation quantity θ stored in the second storage part and the output Δθ from the offset extraction part while increasing the quantity changed in updating in response to the magnitude of the absolute value of the output from the error signal generation part in a period when the adaptive array processing part outputs the first partial signal, or ii) as θ′=θ+μ�Δθ in a period when the adaptive array processing part outputs the second partial signal, assuming that μ represents a prescribed coefficient. [0050] Preferably, the received signal is divided into a plurality of slots to be transmitted, each slot includes a first partial signal including a predetermined reference signal and a second partial signal including transmitted data, and the offset quantity detection part includes a forced phase-locking part forcibly synchronizing the phase of the output from the adaptive array processing part with a prescribed phase, an error signal generation part outputting the difference between an output from the forced phase-locking part and the output from the adaptive array processing part in a period when the adaptive array processing part outputs the second partial signal and an offset extraction part for extracting the frequency offset on the basis of the output from the error signal generation part. [0051] According to the present invention, therefore, deterioration of a receiving characteristic can be suppressed by controlling the array antenna by adaptive array processing thereby compensating for the frequency offset while allocating a plurality of users to a common channel and improving channel utilization efficiency.
[0068]FIG. 1 is a schematic block diagram showing the structure of an SDMA base station 1000 according to a first embodiment of the present invention. [0069] Referring to FIG. 1, the SDMA base station 1000 comprises RF circuits 2-1 to 2-4 receiving signals from an array antenna formed by a plurality of antennas #1 to #4 respectively and down-converting the same and analog-to-digital converters 4-1 to 4-4 for receiving the signals from the RF circuits 2-1 to 2-4 respectively for converting the signals to digital signals and outputting the same as received signal vectors X(t). [0070] While it is assumed in FIG. 1 that four antennas form the array antenna for simplifying the illustration, the number of the antennas may more generally be n (n: natural number of n≧2). [0071] The received signal vectors X(t) are vectors having the signals received from the four antennas as elements. [0072] The SDMA base station 1000 further includes a frequency offset correction part 6 receiving the signals X(t) from the analog-to-digital converters 4-1 to 4-4 and performing complex multiplication on the signals X(t) and a frequency offset correction value θ(t) derived as described later thereby outputting the results as signals X′(t) subjected to correction of frequency offsets, multipliers 12-1 to 12-4 receiving the signals X′(t) output from the frequency offset correction part 6 respectively and multiplying the same by elements of weight vectors W(t) respectively, an adder 14 receiving and adding up outputs from the multipliers 12-1 to 12-4 and outputting the result as a received signal y(t), and a forced phase-locking processing part 20 receiving the output from the adder 14 for forcibly synchronizing the phase of the signal y(t) with a prescribed phase point on an IQ plane. [0073] It is assumed here that the signal y(t) is a signal extracted from a desired terminal among a plurality of terminals, for example, and subjected to QPSK modulation, for example. Therefore, it follows that the forced phase-locking processing part 20 performs processing of forcibly synchronizing the signal subjected to QPSK modulation with a signal point corresponding to a prescribed phase on the IQ plane. [0074] A signal output from the forced phase-locking processing part 20 is hereinafter referred to as a replica signal d′(t). [0075] The SDMA base station 1000 further comprises a memory 30 previously holding a reference signal included in a preamble among symbols (for example, 120 symbols) included in a signal of one slot and outputting the same as a signal d(t), a timing control part 40 detecting whether a section having the reference signal is received or a section (data part) having no reference signal is received in the received signal of one slot, a switching circuit 50 receiving the replica signal d′(t) from the forced phase-locking processing part and the reference signal d(t) from the memory 30 for outputting either signal under control of the timing control part 40, an adder 70 for adding up the output from the switching circuit 50 and the output from the adder 14 after inverting the signs thereof, and a weight calculation circuit 10 receiving an output from the adder 70 for calculating the weight vectors W(t) by known adaptive array processing. [0076] The SDMA base station 1000 further comprises an adder 80 adding up a signal obtained by inverting the sign of an error signal e(t) output from the adder 70 and the reference signal d(t) or the replica signal d′(t) output from the switching circuit 50, a complex conjugate processing part 60 receiving the output from the switching circuit 50 and outputting a signal d*(t) of a complex conjugate, a multiplier 90 for multiplying the output from the complex conjugate processing part 60 by the output from the adder 80, an offset extraction part 100 receiving an output from the multiplier 90 and extracting the imaginary part thereof thereby extracting a frequency offset Δθ, a step coefficient holding part 120 holding a step coefficient μ for obtaining the offset compensation value, a multiplier 110 multiplying the step coefficient μ output from the step coefficient holding part 120 by the frequency offset quantity Δθ, a memory 140 for storing an update value for the offset compensation quantity, and an offset compensation value calculation part 130 for calculating the offset compensation quantity θ(t) in response to an offset compensation value in precedent processing stored in the memory 140 and an output from the multiplier 110. [0077] In response to an output from the offset compensation value calculation part 130, the frequency offset correction part 6 corrects the frequency offsets in the outputs from the analog-to-digital converters 4-1 to 4-4. [0078]FIG. 2 is a conceptual diagram for illustrating the structure of a signal transferred between a terminal and the SDMA base station 1000 in the present invention. [0079] A signal of one frame is divided into eight slots, so that the first four slots are employed for receiving, for example, and the rear four slots are employed for transmission, for example. [0080] Each slot is formed by 120 symbols, and the signal of one frame is allocated to four users with a set of a single receiving slot and a single transmission slot in the example shown in FIG. 2. [0081]FIG. 3 is a flow chart for illustrating operations of the SDMA base station 1000 shown in FIG. 1. [0082] Schematically illustrating the processing carried out in FIG. 3, the signals X(t) from the array antennas #1 to #4 are subjected to complex multiplication with the frequency offset compensation value θ(t), and thereafter subjected to adaptive array processing as described with reference to FIG. 1. [0083] The error e(t) is obtained from the output signal y(t) output from the adaptive array and the reference signal d(t) so that the weight calculation circuit 10 performs adaptive array learning on the basis of the error e(t), thereby calculating the weight vector W(t) having the receiving weight corresponding to each antenna as the element. [0084] At this time, a circumferential error of a carrier frequency component on the IQ plane, i.e., the frequency offset value Δθ is extracted from the output signal y(t) from the adaptive array and the reference signal d(t), for calculating the offset compensation value θ(t). [0085] As to processing for updating the frequency offset in the section having the reference signal in the slot of the received signal, the offset compensation value θ(t) is also sequentially updated when the weight vector W(t) is updated from the reference signal d(t) and the received signal vector X(t) by adaptive array learning. [0086] In the section (data part) having no reference signal, the weight vector W(t) and the frequency offset compensation value θ(t) are sequentially updated by adaptive learning no the basis of the replica signal d′(t) obtained by forcibly phase-locking the output y(t) from the adaptive array with the reference signal point and the error in the output of the adaptive array. [0087] As hereinabove described, the SDMA base station 1000 according to the first embodiment performs array learning and offset update processing on all symbols included in one slot. In other words, offset correction of the received signal, array processing and offset compensation value update processing are sequentially performed every symbol. It is assumed that the value of the step coefficient μ employed in offset updating is previously set by an experiment in response to applied environment, for example. [0088] It is also assumed that an offset compensation value θ(1) is set to zero as the initial value of the processing loop. [0089] When applied to a PHS system, for example, the radio unit updates the offset compensation value with the reference signal d(t) stored in the memory 30 between the first and 12th symbols forming a known signal section. For sections having no reference signal following the 13th symbol, the radio unit employs the signal obtained by forcibly phase-locking the array output y(t) with a reference signal point of π/4 QPSK as the replica signal d′(t) of the reference signal for updating the offset compensation value. [0090] In the following description, �t� denotes a variable expressing a time such that t of the offset compensation value θ(t) expresses an elapsed time from a reference point of time, for example, for expressing a quantity corresponding to a symbol number, for example. [0091] Referring to FIG. 3, when receiving is started (step S100), the value of a variable i for counting the symbol number is initialized to 1 (step S102). [0092] Then, whether or not the value of the variable i exceeds 12 is determined (step S104), so that the frequency offset correction part 6 corrects the vector X(i) of the signal received in the antenna on the basis of the frequency offset compensation value θ(i) according to the following equation if the variable i is not more than 12: [0093] where j represents an imaginary unit, and Z* represents the complex conjugate of a complex number Z. [0094] Then, the weight calculator 10 calculates and updates the weight vector W(i) with the reference signal d(i) output from the adder 70 and the adaptive array output y(t) obtained from the offset-compensated vector X′(i) of the received signal (step S108). [0095] On the other hand, the adder 80, the complex conjugate processing part 60, the multiplier 90 and the offset extraction part 100 perform processing corresponding to the following operations from the reference signal d(i) output from the switching circuit 50 and the error signal e(i) output from the adder 70, thereby calculating the frequency offset value:
[0187] In a section having no reference signal, the step coefficient control part 128 sets the step coefficient μ′(t) to an initial value μ′(t). [0188] According to the aforementioned processing, an error signal e(i) is reduced below a constant value in the section having the reference signal when array processing is quickly converged, while an offset update speed is gradually increased if it is estimable that array processing is converged. It is assumed that constant threshold limitation is provided not to excessively increase the offset update speed. [0189] When reaching the section having no reference signal in addition, the offset update speed is returned to an initially set value, to reach a constant value. Thus, it follows that the update speed is limited. [0190]FIG. 11 is a flow chart for illustrating operations of the SDMA base station 1800 according to the fifth embodiment shown in FIG. 10. [0191] The processing shown in FIG. 11 is similar to the processing according to the first embodiment shown in FIG. 3 except that the step coefficient for updating an offset compensation quantity is changed as described above in a step S111 corresponding to the step S110, and hence redundant description is not repeated. [0192] Therefore, a larger number of offset updating opportunities is supplied as compared with the third embodiment, whereby convergence is quickly made. In addition, while the offset update speed is so excessively increased that there is a possibility for divergence overflow of the variable if errors are reduced in the fourth embodiment, it is possible to advantageously avoid this. [0193] It follows that offset updating is performed after array processing is converged due to the aforementioned processing, whereby offset estimation precision is improved and convergence of the offset compensation value can be quickly performed. [0194] The embodiments disclosed this time must be considered illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the scope of claim for patent, and it is intended that all modifications within the meaning and range equivalent to the scope of claim for patent are included. BRIEF DESCRIPTION OF THE DRAWINGS [0052]FIG. 1 is a schematic block diagram showing the structure of an SDMA base station 1000 according to a first embodiment of the present invention. [0053]FIG. 2 is a conceptual diagram for illustrating the structure of a signal transferred between a terminal and the SDMA base station 1000. [0054]FIG. 3 is a flow chart for illustrating operations of the SDMA base station 1000 shown in FIG. 1. [0055]FIG. 4 is a schematic block diagram for illustrating the structure of an SDMA base station 1200 according to a second embodiment of the present invention. [0056]FIG. 5 is a flow chart for illustrating operations of the SDMA base station 1200 according to the second embodiment. [0057]FIG. 6 is a schematic block diagram for illustrating the structure of an SDMA base station 1400 according to a third embodiment of the present invention. [0058]FIG. 7 is a flow chart for illustrating operations of the SDMA base station according to the third embodiment. [0059]FIG. 8 is a schematic block diagram for illustrating the structure of an SDMA base station 1600 according to a fourth embodiment of the present invention. [0060]FIG. 9 is a flow chart for illustrating operations of the SDMA base station 1600 according to the fourth embodiment. [0061]FIG. 10 is a schematic block diagram for illustrating the structure of an SDMA base station 1800 according to a fifth embodiment of the present invention. [0062]FIG. 11 is a flow chart for illustrating operations of the SDMA base station 1800 according to the fourth embodiment. [0063] FIGS. 12(a) to 12(c) illustrate arrangements of channels in various types of communication systems, i.e., a frequency division multiple access system, a time division multiple access system and a spatial division multiple access system. [0064]FIG. 13 is a schematic block diagram showing the structure of a transmission/receiving system 2000 of a conventional SDMA base station. [0065]FIG. 14 is a block diagram showing the structure of a transmission/receiving part 2100 a corresponding to a single user in an adaptive array 2100.
Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6911954 *Jul 26, 2002Jun 28, 2005Shidong LiMethod for constructing mobile wireless antenna systemsUS7020107 *Jan 21, 2003Mar 28, 2006Arraycomm, LlcMethods for reliable user switchback on a PHS spatial division multiple access channelUS7149491Nov 18, 2002Dec 12, 2006Sanyo Electric Co., Ltd.Radio reception apparatus symbol timing control method, and symbol timing control programUS7269202 *Dec 21, 2001Sep 11, 2007Sanyo Electric Co., Ltd.Radio apparatus, swap detecting method and swap detecting programUS7446728 *Feb 13, 2007Nov 4, 2008Shidong LiMethod and apparatus for constructing general wireless antenna systemsUS7840189Dec 15, 2004Nov 23, 2010Freescale Semiconductor, Inc.Frequency generation in a wireless communication unitUS8320343 *Sep 18, 2003Nov 27, 2012Kyocera CorporationRadio cell station apparatus, reference signal allocation method and reference signal allocation program* Cited by examinerClassifications U.S. Classification455/562.1International ClassificationH04J3/00, H04B7/06, H04B7/08, H04L27/34, H01Q3/26, H04L27/22, H04B7/10, H04J99/00Cooperative ClassificationH04L2027/0053, H04L2027/0065, H04B7/0851, H04B7/01, H04L27/0014European ClassificationH04B7/08C4J1, H04B7/01, H04L27/00RLegal EventsDateCodeEventDescriptionAug 28, 2013FPAYFee paymentYear of fee payment: 8Aug 26, 2009FPAYFee paymentYear of fee payment: 4Oct 10, 2002ASAssignmentOwner name: SANYO ELECTRIC CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DOI, YOSHIHARU;MIYATA, TAKEO;REEL/FRAME:013902/0806;SIGNING DATES FROM 20020822 TO 20020827RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google