Source: http://patents.com/us-9491866.html
Timestamp: 2017-11-23 00:09:26
Document Index: 650003976

Matched Legal Cases: ['Application No. 10', 'Application No. 2013', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 100124219', 'art 40', 'art 40', 'art 40']

US Patent # 9,491,866. Method for manufacturing a printed circuit board - Patents.com
United States Patent 9,491,866
Lee; Sang Myung (Seoul, KR), Kim; Byeong Ho (Seoul, KR), Kim; Jin Su (Seoul, KR), Nam; Myoung Hwa (Seoul, KR), Seo; Yeong Uk (Seoul, KR), Yoon; Sung Woon (Seoul, KR)
Lee; Sang Myung
Kim; Byeong Ho
Kim; Jin Su
Nam; Myoung Hwa
Seo; Yeong Uk
Family ID: 1000002220187
13/809,083
PCT/KR2011/004975
WO2012/005524
US 20130192881 A1 Aug 1, 2013
Jul 8, 2010 [KR] 10-2010-0065775
Dec 24, 2010 [KR] 10-2010-0134482
Current CPC Class: H05K 3/062 (20130101); H05K 3/0026 (20130101); H05K 3/02 (20130101); H05K 3/108 (20130101); H05K 3/465 (20130101); H05K 2203/0554 (20130101); H05K 2203/0557 (20130101); Y10T 29/49167 (20150115); H05K 3/0032 (20130101); H05K 3/045 (20130101)
Current International Class: H05K 3/06 (20060101); H05K 3/00 (20060101); H05K 3/10 (20060101); H05K 3/02 (20060101); H05K 3/46 (20060101); H05K 3/04 (20060101)
5998066 December 1999 Block
6250933 June 2001 Khoury
7562447 July 2009 Lee et al.
8072052 December 2011 Ko et al.
2008/0265254 October 2008 Nishiura
2009/0023236 January 2009 Miyairi
2009/0152743 June 2009 Jomaa et al.
2009/0220867 September 2009 Fujikawa et al.
2012/0308718 December 2012 Watanabe
05-323574 Dec 1993 JP
07-080675 Mar 1995 JP
07-241690 Sep 1995 JP
11-238970 Aug 1999 JP
2000-315868 Nov 2000 JP
2001-024332 Jan 2001 JP
2002-368383 Dec 2002 JP
10-2007-0109042 Nov 2007 KR
10-0841987 Jun 2008 KR
10-2009-0009155 Jan 2009 KR
10-2009-0033316 Apr 2009 KR
10-2009-0064327 Jun 2009 KR
10-2009-0096212 Sep 2009 KR
200903672 Jan 2009 TW
Notice of Allowance dated Feb. 26, 2013 in Korean Application No. 10-2010-0134482, filed Dec. 24, 2010. cited by applicant .
Japanese Office Action, dated Jan. 28, 2014, in Japanese Application No. 2013-518276. cited by applicant .
International Search Report in International Application No. PCT/KR2011/004975, filed Jul. 7, 2011. cited by applicant .
Notice of Allowance dated Apr. 17, 2012 in Korean Application No. 10-2010-0065775, filed Jul. 8, 2010. cited by applicant .
Office Action dated Aug. 1, 2011 in Korean Application No. 10-2010-0065775, filed Jul. 8, 2010. cited by applicant .
Office Action dated Dec. 21, 2011 in Korean Application No. 10-2010-0134482, filed Dec. 24, 2010. cited by applicant .
Office Action dated Apr. 25, 2013 in Taiwanese Application No. 100124219, filed Jul. 8, 2011. cited by applicant.
1. A method for manufacturing a printed circuit board, the method comprising: preparing an insulation board; forming a first circuit pattern groove and a via hole by removing a surface of the insulation board by using a multi tone mask or a gray tone mask, wherein the first circuit pattern groove has an edge; forming a second circuit pattern groove by removing the edge of the first circuit pattern groove, wherein the second circuit pattern groove is a final result of etching the edge of the first circuit pattern groove to form a curved shape; and forming a circuit pattern and a via to fill the second circuit pattern groove and the via hole; wherein the multi tone mask or the gray tone mask have a first region for forming an outer circumference of the via hole and the first circuit pattern groove, a second region for forming a central area of the via hole, and a third region defined in a region that is not etched; wherein the first region comprises a first part spaced apart from the second region, and a second part surrounding the second region; wherein the first circuit pattern groove and the via hole are formed at the same time by using the first region, the second region, and the third region of the multi tone mask or the gray tone mask; and wherein the second circuit pattern groove has a semicircle cross-sectional shape.
2. The method according to claim 1, wherein the forming of the first circuit pattern groove and the via hole comprises: irradiating a laser through the first to third mask regions of the multi tone mask or the gray tone mask.
4. The method according to claim 2, wherein the second region has a hole region through which the laser completely passes, the third region has a non-transmitting region through which the laser is blocked, and the first region has a low-transmitting region for selectively transmitting the laser.
7. The method according to claim 1, wherein the multi tone mask comprises: a base transparent board formed of a quartz or glass material; and a plurality of light transmitting parts formed on the base transparent board, the plurality of light transmitting parts being formed of one or more materials of Cr and CrO.
8. The method according to claim 1, wherein the forming of the circuit pattern comprises: plating a first metal layer on a surface of the second circuit pattern groove; forming a second metal layer filling the second circuit pattern groove by using the first metal layer as a seed layer; and etching the first and second metal layers except the second circuit pattern groove to expose the surface of the insulation board.
9. The method according to claim 1, wherein the forming of the circuit pattern comprises: filling a conductive paste into the second circuit pattern groove; and drying the filled conductive paste.
10. The method according to claim 1, wherein the preparing of the insulation board comprises: preparing an insulation plate; patterning a copper film layer on the insulation plate to form a base circuit pattern; and forming an insulation layer covering the base circuit pattern on the insulation plate, wherein the first circuit pattern groove and the second circuit pattern groove are formed in a surface of the insulation layer.
Specifically, each of engraved patterns formed in the second insulation layer 130 using the excimer laser, i.e., the circuit pattern 30, the via hole 70, and the pad part 40 may have a certain width and depth. For example, the circuit pattern 30 may have an engraved width of about 3 .mu.m to about 25 .mu.m and an engraved depth of about 3 .mu.m to about 25 .mu.m. Also, the via hole 70 may have an engraved diameter of about 30 .mu.m to about 80 .mu.m or less and an engraved depth of about 20 .mu.m to about 100 .mu.m or less. Also, the pad part 40 may have an engraved diameter of about 30 .mu.m to 200 .mu.m and an engraved depth of about 1 .mu.m to about 20 .mu.m or less.
Alternatively, the process for forming the electroless copper plating layer, i.e., the conductive seed layer 170, may be performed using a sputtering process in which ion particles (e.g., Ar+) of gas generated by plasma collide with a copper target to form a metal layer on the substrate. Also, the conductive seed layer 170 may be formed of Cu using the electroless plating or sputtering process. Alternatively, the conductive seed layer 170 may be formed of a Ni--Pd alloy or Ni--Cr alloy using the electroless plating or sputtering process. Also, in a process (S4-1-2), the entire surfaces of the circuit pattern 30, the via hole 70, and the pad part 40 may be filled using the electro plating process. Also, in the process for forming the electro copper plating layer 180, the second insulation layer 130 may be immersed into a copper plating box and then the electro copper plating process may be performed using a DC rectifier. In the electro copper plating process, an area to be plated may be calculated to apply a proper current into the DC rectifier, thereby extracting copper.
The circuit pattern groove 131 may have a pattern width of about 3 .mu.m to about 25 .mu.m and a pattern depth of about 3 .mu.m to about 25 .mu.m. The via hole may have an engraved diameter of about 80 .mu.m or less and a depth of about 100 .mu.m or less.
Previous Patent US 9,491,865 | Next Patent US 9,491,867