Source: https://patents.google.com/patent/KR101483825B1/en
Timestamp: 2019-11-16 03:07:41
Document Index: 755981811

Matched Legal Cases: ['art 160', 'art 160', 'art 160', 'art 140', 'art 150', 'arts 140', 'arts 150', 'art 141', 'arts 140', 'arts 150', 'art 140', 'art 160', 'art 150', 'art\n160', 'arts\n161']

KR101483825B1 - Substrate embedding electronic component and manufacturing mehtod thereof - Google Patents
Substrate embedding electronic component and manufacturing mehtod thereof Download PDF
KR101483825B1
KR101483825B1 KR20120139727A KR20120139727A KR101483825B1 KR 101483825 B1 KR101483825 B1 KR 101483825B1 KR 20120139727 A KR20120139727 A KR 20120139727A KR 20120139727 A KR20120139727 A KR 20120139727A KR 101483825 B1 KR101483825 B1 KR 101483825B1
KR20120139727A
KR20140071769A (en
2012-12-04 Application filed by 삼성전기주식회사 filed Critical 삼성전기주식회사
2012-12-04 Priority to KR20120139727A priority Critical patent/KR101483825B1/en
2014-06-12 Publication of KR20140071769A publication Critical patent/KR20140071769A/en
2015-01-16 Publication of KR101483825B1 publication Critical patent/KR101483825B1/en
The present invention relates to a substrate on which electronic components are embedded, a cavity formed in at least one insulating layer provided inside an electronic component built-in substrate, At least a part of which is inserted into the cavity; And a cavity plating unit formed on a surface of the cavity opposite to at least one side of the electronic component. Even when the size of the external electrode of the electronic component is smaller than that of the conventional case, the electrical connection between the external electrode and the via is improved .
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an electronic component-
Recently, mobile devices such as smart phones and tablet PCs are required to have high portability while dramatically improving their performance, and studies for miniaturization, slimming, and high performance of electronic components used in such mobile devices have continued .
Here, in the electronic component built-in board introduced in Patent Document 1 or the like, it is possible to secure a space in which an extra component can be mounted on the surface by embedding the electronic component inside the board, And is becoming popular as a method for realizing miniaturization, slimness and high performance of parts.
Particularly, as the performance of the semiconductor chip is improved, the stability of the power supplied to the semiconductor chip becomes more important. To this end, a so-called decoupling capacitor or a bypass capacitor is provided between the semiconductor chip and the power supply line It removes noise from the power supply and ensures stable current supply to the semiconductor chip even when the power supply current changes suddenly.
In this case, when the semiconductor chip is mounted on the substrate with the capacitor embedded therein, the distance between the decoupling capacitor and the semiconductor chip can be minimized, so that stable power supply to the high performance semiconductor chip can be achieved and miniaturization and slimming can be achieved.
According to Patent Document 1, a cavity is formed at a position where an electronic component is to be inserted, a capacitor is fixed, a thermo-compression bonding is performed using an insulating material, and then a micro via hole is formed with a laser, And a method of forming an electrical connection through plating is introduced.
That is, in order to electrically connect an electronic component built in a substrate and a circuit pattern provided on the substrate surface, a method of processing a via hole using a laser and filling a via hole with a conductive material by plating or the like is commonly used It has been applied.
According to such a general method, depending on the factors such as the placing tolerance that occurs when the electronic component is embedded in the substrate, the via hole processing tolerance, and the size of the via hole, the minimum condition of the area of the via contact portion to be formed in the built- Can be determined.
However, as the size of the electronic component decreases, the via contact portion also becomes smaller. Therefore, as the size of the electronic component becomes smaller, the matching error between the via and the electronic component becomes a serious problem.
Korean Patent Publication No. 2007-0101183
SUMMARY OF THE INVENTION It is an object of the present invention, which is created to solve the above-mentioned problems, to provide an electronic component built-in substrate improved in electrical connectivity of an electronic component embedded in the substrate.
It is another object of the present invention to provide a method of manufacturing an electronic component built-in substrate in which electrical connection of electronic components built in the substrate is improved.
According to another aspect of the present invention, there is provided an electronic component built-in substrate having electronic components embedded therein, the substrate including at least one insulation A cavity formed in the layer; At least a part of which is inserted into the cavity; And a cavity plating portion formed on a surface of the cavity facing at least one side of the electronic component.
In this case, an external electrode may be provided on a side surface of the electronic component, and a conductive filling part may be further provided to electrically connect the cavity plating part and the external electrode by filling a conductive material between the cavity plating part and the external electrode. have.
In addition, it may further include at least one area selected from at least a part of the external electrodes, at least part of the conductive filling part, and at least part of the cavity plating part.
The outer electrode may include at least two electrodes separated from each other on the surface of the electronic component, and the cavity plating unit may be connected to the electrodes such that the electrodes are electrically disconnected from each other. And each of the cavity plating portions electrically separated by the disconnection portions and the conductive filling portion may be filled between the electrodes.
In addition, an insulating material may be filled in the space between the electrodes, between the disconnection portions, and between the conductive filling portions.
In addition, it may further comprise a metal pattern provided on a surface of the insulating layer and electrically connected to the cavity plating portion, wherein at least a part of the external electrode, at least a part of the conductive filling portion, at least a part of the cavity plating portion, And at least one region selected from at least a part of the metal patterns.
At this time, the external electrode is composed of at least two electrodes separated from each other on the surface of the electronic part, and the cavity plating part connected to the electrodes is formed with disconnection parts so that the electrodes are electrically isolated from each other And each of the cavity plating portions electrically separated by the disconnection portions and the conductive filling portion may be filled between the electrodes.
In addition, a plurality of the electronic parts may be inserted into the cavity, and at least two of the plurality of electronic parts may be connected to each other in parallel.
Meanwhile, an external electrode may be provided on a side surface of the electronic component, and the cavity plating portion and the external electrode may be in contact with each other to be electrically connected.
In this case, at least one of the external electrodes and at least one of the cavity plating portions may be provided with a via contacting one surface thereof.
The outer electrode may include at least two electrodes separated from each other on the surface of the electronic component, and the cavity plating unit may be connected to the electrodes such that the electrodes are electrically disconnected from each other. .
In addition, an insulating material may be filled in spaces between the electrodes and between the disconnection portions.
In addition, it is preferable to further include a metal pattern provided on a surface of the insulating layer and electrically connected to the cavity plating part, wherein at least a part of the external electrodes, at least part of the cavity plating part, And at least one region that is in contact with at least one surface of the substrate.
At this time, the external electrode is composed of at least two electrodes separated from each other on the surface of the electronic part, and the cavity plating part connected to the electrodes is formed with disconnection parts so that the electrodes are electrically isolated from each other .
An electronic component built-in substrate according to an embodiment of the present invention includes a hexahedral body portion and two external electrodes covering two opposed faces of the body portion, A cavity formed in at least one insulating layer provided inside the electronic component built-in substrate; And a cavity plating unit formed on a surface of the cavity facing the external electrode.
An electronic component built-in substrate according to an embodiment of the present invention includes a substrate having a first metal pattern on a lower surface thereof, a second metal pattern on an upper surface thereof, and a cavity penetrating between an upper surface and a lower surface thereof. 1 insulating layer; An electronic component having at least one external electrode on its surface, and at least a part of which is inserted into the cavity; A cavity plating portion formed on a surface of the cavity facing the external electrode, the cavity plating portion being electrically connected to at least one of the first metal pattern and the second metal pattern; A conductive filling part formed by filling a conductive material between the cavity plating part and the external electrode; A second insulating layer covering the first metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the exposed surface of the electronic component; A first circuit pattern formed on a surface of the second insulating layer; And at least one area selected from at least a part of the external electrodes, at least part of the conductive filling part, at least part of the cavity plating part, and at least part of the first metal pattern contacting the cavity plating part, And a first via contacting the other surface of the first circuit pattern.
At this time, the electronic component is provided with at least two external electrodes formed in regions separated from each other on the surface of the electronic component, and in the cavity plating portion connected to the external electrodes, the electrodes are electrically isolated from each other And the conductive filler portion may be filled between each of the cavity plating portions electrically isolated by the disconnection portions and each of the external electrodes.
In addition, a material forming the second insulating layer may be filled in the space between the external electrodes, between the disconnection portions, and between the conductive filling portions.
The first metal pattern may further include a fifth via which is in contact with at least a portion of the first metal pattern except for the contact with the cavity plating portion, and at least a portion of the first circuit pattern contacts the other face.
A third insulating layer covering the second metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the exposed surface of the electronic component; A second circuit pattern formed on a surface of the third insulating layer; And at least one area selected from at least a part of the external electrodes, at least a part of the conductive filling part, at least part of the cavity plating part, and at least part of the part of the second metal pattern contacting the cavity plating part, And a third via contacting the other surface of the second circuit pattern.
At this time, at least one of the material constituting the first insulating layer and the material constituting the second insulating layer may be filled in the space between the external electrodes, between the disconnection portions and between the conductive filling portions.
The sixth metal pattern may further include a sixth via which is in contact with at least a portion of the second metal pattern except for the contact with the cavity plating portion, and at least a portion of the second circuit pattern contacts the other face.
A method of manufacturing an electronic component built-in substrate according to an embodiment of the present invention includes the steps of: (A) Forming a cavity in at least one insulating layer and plating a conductive material on the surface of the cavity to form a cavity plating portion; And (B) inserting at least a portion of the electronic component into the cavity.
In this case, after the step (B), filling the space between the electronic component and the cavity plating unit with a conductive material may further include filling the space between the electronic component and the cavity plating unit.
The step (A) may include the steps of: (A1) forming a first temporary cavity of a "C" shape and a second temporary cavity of a shape symmetric with the first temporary cavity, Forming a temporary remainder on a part of the region where the cavity is to be formed; (A2) plating a surface of the first temporary cavity and the surface of the second temporary cavity with a conductive material; And (A3) removing the temporary residue.
The step (A) includes the steps of: (a1) forming a first protrusion formed by protruding the insulating layer from one surface of the cavity in the direction of the facing surface, and a second protrusion formed on a surface of the first protrusion, Forming a third temporary cavity in a region other than a second projection formed to be symmetrical with respect to the first projection; (a2) plating a surface of the third temporary cavity with a conductive material; And (a3) removing a portion of the first projecting portion and the second projecting portion.
According to an embodiment of the present invention, there is provided a method of manufacturing an electronic component built-in substrate, comprising: (a) providing a first insulating layer having a first metal pattern on a lower surface thereof and a second metal pattern on an upper surface thereof; (b) forming a cavity in the first insulating layer, and plating a conductive material on the cavity forming surface to form a cavity plating portion electrically connected to at least one of the first metal pattern and the second metal pattern step; (c) bonding a detent film to a lower surface of the first metal pattern; (d) inserting at least a part of an electronic component having a plurality of external electrodes on a surface thereof into the cavity, thereby bonding the lower surface of the electronic component to the detetch film; (e) filling a conductive material between the cavity plating portion and the external electrodes to form a conductive filling portion; (f) forming an insulating material on the exposed surfaces of the second metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component to form a third insulating layer; (g) a portion of at least a portion of the external electrodes, at least a portion of the conductive filler, at least a portion of the cavity plating portion, and a portion of the second metal pattern that is in contact with the cavity plating portion, Processing a via hole exposing at least one region selected from at least a portion; And (h) filling the via hole with a conductive material, and forming a second circuit pattern on the upper surface of the third insulating layer.
The step (b) includes the steps of: (b1) forming a first temporary cavity having a "C" shape and a second temporary cavity having a shape symmetric with the first temporary cavity, Forming a temporary remainder on a part of the region where the cavity is to be formed; (b2) plating a surface of the first temporary cavity and the second temporary cavity with a conductive material; And (b3) removing the temporary residue.
The step (b) may further include the steps of: (b1 ') forming a first protrusion formed by protruding the insulating layer from one surface of the cavity in the direction of the facing surface, and a second protrusion formed on the surface of the first protrusion, Forming a third temporary cavity in an area other than a second protrusion that is formed to be symmetrical with the protrusion; (b2 ') plating a surface of the third temporary cavity with a conductive material; And (b3 ') removing a portion of the first protrusion and the second protrusion.
A method of manufacturing an electronic component built-in substrate according to an embodiment of the present invention includes the steps of: (f1) inserting an insulating layer on an exposed surface of the second metal pattern, the first insulating layer, the cavity plating portion, Applying a material to form a third insulating layer; (f2) After removing the detent film, an insulating material is applied to the exposed surfaces of the first metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component to form a second insulating layer ; (g1) forming a first via through the second insulating layer and a first circuit pattern provided on a lower surface of the second insulating layer and connected to the first via; And (g2) forming a third via hole penetrating the third insulating layer and a second circuit pattern provided on an upper surface of the third insulating layer and connected to the third via, The via is formed in at least one region selected from at least a portion of the external electrodes, at least a portion of the conductive filler portion, at least a portion of the cavity plating portion, and at least a portion of the first metal pattern contacting the cavity- Wherein at least a part of the external electrodes, at least a part of the conductive filling parts, at least part of the cavity plating parts and at least one of the cavity plating parts of the second metal patterns And may be formed so that one surface is in contact with at least one region selected from a part.
In this case, the step (d) may be performed such that a plurality of the electronic parts are inserted into the cavity, and the lower surface of the electronic part is bonded to the detent film.
In addition, at least two of the plurality of electronic components may be connected to each other in parallel.
According to the present invention configured as described above, even when the size of the external electrode of the electronic component becomes smaller than the conventional one, the allowable area where the via for electrically connecting the electronic component built in the substrate and the outer layer circuit pattern is extended, It is possible to solve the problem of lowering electrical connectivity due to factors such as positional tolerances generated during mounting of electronic components, via hole processing tolerances generated in via hole processing, and via hole size.
In addition, since the electrical connection path to the electronic component built in the substrate is widened, the charge transfer speed between the electronic component and other elements electrically connected can be improved.
1 is a cross-sectional view schematically showing an electronic component built-in substrate according to an embodiment of the present invention.
2 is a plan view showing a surface cut along a line I-I 'in FIG. 1 in an electronic component built-in substrate according to an embodiment of the present invention.
3 is a plan view showing a plane cut along a line I-I 'in FIG. 1 in an electronic component built-in substrate according to another embodiment of the present invention.
4 is a plan view showing a surface cut along a line I-I 'in FIG. 1 in an electronic component built-in substrate according to another embodiment of the present invention.
5A to 5I are process flow diagrams schematically showing a method of manufacturing an electronic component built-in substrate according to an embodiment of the present invention,
5A is a cross-sectional view schematically illustrating a state in which a first metal pattern and a second metal pattern are formed in the first insulating layer,
5B is a cross-sectional view schematically illustrating a state where a cavity is formed in the first insulating layer,
5C is a cross-sectional view schematically illustrating a state in which a cavity plating portion is formed in the cavity,
5D is a cross-sectional view schematically showing a state in which the detach film is bonded to the first metal pattern,
5E is a cross-sectional view schematically illustrating a state in which an electronic component is inserted into a cavity,
5F is a cross-sectional view schematically showing a state in which a conductive filling part is formed,
5G is a cross-sectional view schematically showing a state in which the third insulating layer is formed,
5H is a cross-sectional view schematically showing a state in which the second insulating layer is formed,
5I is a cross-sectional view schematically illustrating a state in which first through sixth vias are formed with a first circuit pattern and a second circuit pattern.
6A to 6D are process flow diagrams schematically illustrating a process of forming a cavity having a cavity plating portion in a first insulating layer in a method of manufacturing an electronic component embedded board according to an embodiment of the present invention.
6A is a plan view schematically illustrating a state in which a first temporary cavity and a second temporary cavity are formed,
6B is a plan view schematically illustrating a state in which a resist portion is formed,
6C is a plan view schematically illustrating a state in which the plating process is performed,
6D is a plan view schematically illustrating a state where the temporary residue and the resist portion are removed.
FIGS. 7A to 7C are process flowcharts schematically illustrating a process of forming a cavity having a cavity plating portion in a first insulating layer in a method of manufacturing an electronic component embedded board according to another embodiment of the present invention.
7A is a plan view schematically illustrating a state in which the first projection and the second projection are formed,
7B is a plan view schematically illustrating a state in which the plating process is performed,
7C is a plan view schematically illustrating a state in which the first projection and the second projection are removed.
For simplicity and clarity of illustration, the drawings illustrate the general manner of construction and the detailed description of known features and techniques may be omitted so as to avoid unnecessarily obscuring the discussion of the described embodiments of the invention. Additionally, elements of the drawings are not necessarily drawn to scale. For example, to facilitate understanding of embodiments of the present invention, the dimensions of some of the elements in the figures may be exaggerated relative to other elements. Like reference numerals in different drawings denote like elements, and like reference numbers may indicate similar elements, although not necessarily.
The terms "first", "second", "third", and "fourth" in the specification and claims are used to distinguish between similar components, if any, Or to describe the sequence of occurrences. It will be understood that the terminology used is such that the embodiments of the invention described herein are compatible under suitable circumstances to, for example, operate in a sequence other than those shown or described herein. Likewise, where the method is described as including a series of steps, the order of such steps presented herein is not necessarily the order in which such steps may be performed, any of the described steps may be omitted and / Any other step not described will be additive to the method.
Terms such as "left", "right", "front", "back", "upper", "bottom", "above", "below" And does not necessarily describe an unchanging relative position. It will be understood that the terminology used is intended to be interchangeable with the embodiments of the invention described herein, under suitable circumstances, for example, so as to be able to operate in a different direction than that shown or described herein. The term "connected" as used herein is defined as being directly or indirectly connected in an electrically or non-electrical manner. Objects described herein as "adjacent" may be in physical contact with one another, in close proximity to one another, or in the same general range or region as are appropriate for the context in which the phrase is used. The presence of the phrase "in one embodiment" herein means the same embodiment, although not necessarily.
1 is a cross-sectional view schematically showing an electronic component built-in substrate 100 according to an embodiment of the present invention.
1, an electronic component built-in substrate 100 according to an embodiment of the present invention includes a first insulating layer 110 having a cavity 111 formed thereon, a cavity plating unit 110 formed on a surface of the cavity 111, 140 and an electronic component 160.
The first insulating layer 110 may be formed of a general insulating material or a core board such as CCL.
In addition, metal patterns 120 and 130 may be formed on at least one surface of the first insulating layer 110.
Referring to FIG. 1, a first metal pattern 120 may be formed on the lower surface of the first insulating layer 110, and a second metal pattern 130 may be formed on the upper surface of the second insulating layer 171. .
At this time, if a through via hole or the like for realizing the cavity 111 or the through via (VT) is formed using the CO 2 laser, the first metal pattern 120 and the second The metal pattern 130 may serve as a mask.
Of course, a via hole or a cavity 111 may be formed using a YAG laser or the like.
The electronic component 160 is inserted into the cavity 111 and may be a passive element such as a capacitor, a resistor, an inductor, a filter, or an active element such as an IC.
Particularly, when the electronic part 160 such as a capacitor having the external electrode 161 formed on the surface or the side surface is embedded in the substrate, it is difficult to secure a sufficient area for realizing the electrical connection to the electronic part 160.
For example, when a via hole is formed using a CO 2 laser, a via contact area of about 150 μm is required, and a position tolerance of about 50 μm may be generated when mounting an electronic component. Therefore, the size of the via contact is minimum It is necessary to secure more than 200um.
A capacitor having a size of 1.0 x 0.5 mm, which is commonly used, can realize a size of one side of the external electrode of 200 mu m or more.
However, the width of the chip capacitor external electrode 161 such as a miniature MLCC (Multi Layer Ceramic Capacitor) or the like is about 100 to 200 μm in the case of a 0603 chip (600 μm × 300 μm), 0402 chip (400 μm × 200 μm) It is only about 70 to 140 μm.
However, when a via hole is processed using a CO 2 laser, since a via contact width of at least 200 μm is required, it is extremely difficult to embody such an ultra-small MLCC in a substrate and realize electrical connection using a via.
That is, an error may occur due to the problems of the positional tolerance of the electronic component 160, the via hole machining allowance, the via diameter, etc. Such an error occurrence rate becomes more serious as the size of the electronic component 160 becomes smaller You can.
In order to solve such a problem, in the electronic component built-in substrate 100 according to the embodiment of the present invention, the cavity plating portion 140 is formed on the surface of the cavity 111. [
That is, in the related art, since the electrical connection of the electronic component 160 is realized by making the vias contact with a part of the upper surface or the lower surface of the electronic component 160, a problem occurs when the area of the via connection is narrowed. So that the electrical connection is ensured even when the part 160 passes through the cavity plating part 140, thereby solving the conventional problem. In particular, the MLCC and the like generally include a body 162 having a rectangular parallelepiped shape including a magnetic body and an internal electrode, and two external electrodes 161 covering both sides of the opposite sides and covering a part of the other sides, When the MLCC is inserted into the cavity 111 of the board 100, and the external electrode 161 and the cavity plating unit 140 are electrically connected to each other, the effect is maximized .
In this case, when the size of the cavity 111, the size of the electronic component 160, the thickness of the cavity plating section 140, and the like are precisely controlled, the cavity plating section 140 and the electronic component 160 can be directly contacted have.
If it is difficult to precisely control the gap between the cavity plating unit 140 and the electronic component 160, a predetermined clearance may be provided between the cavity plating unit 140 and the electronic component 160. In this case, The electrical connection between the cavity plating portion 140 and the electronic component 160 can be ensured by filling the conductive filler 150 with the material.
The cavity plating unit 140 may be in contact with the first metal pattern 120, the second metal pattern 130, and the like formed on the surface of the first insulating layer 110.
Therefore, in forming the via in the electronic component built-in substrate 100 according to an embodiment of the present invention, not only the external electrode 161 of the electronic component 160 but also at least the margin of the thickness of the cavity plating portion 140 Further, the via connection can be extended to the conductive filler 150, the first or second metal pattern 130, or the like.
Therefore, conventionally, since a via has to be connected to the external electrode 161 of the electronic component 160, a problem has occurred when the width of the external electrode 161 is narrowed. In contrast to this, The area where the vias can be connected can be greatly extended in the component-embedded board 100 as compared with the prior art, and thus the conventional problem can be solved.
1, an electronic component built-in substrate 100 according to an embodiment of the present invention includes a second insulating layer 171, a third insulating layer 172, a first circuit pattern 181, A circuit pattern 182, first through sixth vias V6 and through vias VT, and the like.
The second insulating layer 171 is formed under the first insulating layer 110 and includes a first metal pattern 120, a first insulating layer 110, a cavity plating portion 140, a conductive filling portion 150, And the exposed surface of the electronic component 160.
The third insulating layer 172 is formed on the first insulating layer 110 and includes a second metal pattern 130, a first insulating layer 110, a cavity plating portion 140, a conductive filling portion 150, And the exposed surface of the electronic component 160.
The first circuit pattern 181 may be formed on the lower surface of the second insulating layer 171 and the second circuit pattern 182 may be formed on the upper surface of the third insulating layer 172.
The first through fourth vias V1 through V4 function to electrically connect the electronic component 160 embedded in the substrate with other components.
At this time, the first via V1 and the second via V2 are electrically connected to the external electrode 161 of the electronic component 160, the conductive filling portion 150, the cavity plating portion 140 and the first metal pattern 120 And the pattern to be in contact with the cavity plating unit 140. [
The third via V3 and the fourth via V4 are electrically connected to the external electrode 161 of the electronic component 160, the conductive filling portion 150, the cavity plating portion 140 and the second metal pattern 130 And the pattern to be in contact with the cavity plating unit 140. [
That is, as illustrated in FIG. 1, a portion of the external electrode 161, such as the third via V3, or a part of the external electrode 161, such as the second via V2, may be in direct contact with the external electrode 161 of the electronic component 160, The portion 150 and the cavity plating portion 140 can be contacted. It is also possible to make contact with a pattern of the first metal pattern 120 that contacts the cavity plating portion 140 as the first via V1 or to contact the cavity plating portion 140 of the second metal pattern 130 as the fourth via V4 140, thereby making it possible to realize the electrical connection of the electronic component 160. [
In addition to the first to fourth vias V4 described above, the fifth via V5, the second metal pattern 130, and the third via pattern V4, which are connected between the first metal pattern 120 and the first circuit pattern 181, A sixth via V6 connected between the first and second circuit patterns 182 and 184 and a second via pattern V6 connecting the first metal pattern 120 and the second metal pattern 130 through the first insulating layer 110, And the like.
2 is a plan view showing a surface cut along a line I-I 'in FIG. 1 in an electronic component built-in substrate 100 according to an embodiment of the present invention.
2, an electronic component 160 configured to cover two side surfaces of the body portion 162 and to be separated from each other on the other side is positioned at the center of the cavity 111, The filling part 150 is in contact with the surface of each of the external electrodes 161 and two cavity plating parts 140 may be formed on the surface of the cavity 111 so as to be in contact with the surface of each of the conductive filling parts 150 .
That is, when the electronic component 160 is a capacitor, both electrodes need to be electrically disconnected, so that they need to be configured as shown in FIG.
At this time, a disconnection part 141 for ensuring insulation may be provided between the two cavity plating parts 140 and the two conductive filling parts 150 in the cavity 111. [ The disconnection portion 141 may be filled with an insulating material 172 ', and the material constituting the second insulating layer 171 or the third insulating layer 172 illustrated in FIG. 1 may be filled in the disconnection portion 141 .
3 is a plan view showing a surface cut along a line I-I 'in FIG. 1 in an electronic component built-in substrate 100 according to another embodiment of the present invention.
Referring to FIG. 3, a plurality of electronic components 160 may be inserted into the cavity 111 of the electronic component built-in substrate 100 according to another embodiment of the present invention. At this time, Can be connected in parallel with each other.
4 is a plan view showing a surface cut along a line I-I 'in FIG. 1 in an electronic component built-in substrate 100 according to another embodiment of the present invention.
4, a plurality of electronic components 160 are inserted into a cavity 111 of a substrate 100 having an electronic component according to another embodiment of the present invention, and all the electronic components 160 are connected in parallel It will be understood that they may be connected in parallel and partly separated.
As illustrated in FIG. 3 and FIG. 4, by connecting the electronic components 160, in particular, the capacitors in various combinations in parallel, various capacitances can be implemented as needed by using capacitors that are standardized and produced in large quantities.
5A to 5I are process flowcharts schematically showing a method of manufacturing an electronic component built-in substrate according to an embodiment of the present invention.
5A and 5B, first, a cavity 111 is formed in the first insulating layer 110 using a CO 2 laser, a YAG laser, or the like.
At this time, the first metal pattern 120 and the second metal pattern 130 may be formed on the first insulating layer 110.
In addition, when the cavity 111 is processed using the CO 2 laser, the first metal pattern 120 or the second metal pattern 130 may serve as a mask.
In this process, a via hole for forming a through via (VT) can also be processed.
Next, referring to FIG. 5C, a cavity plating unit 140 is formed on the surface of the cavity 111 formed in the first insulation layer 110.
5D and 5E, the electronic component 160 is inserted into the cavity 111 with the detach film DF adhered to the first metal pattern 120, So that the electronic component 160 is fixed to the detent film DF.
Next, referring to FIG. 5F, a space between the cavity plating part 140 and the electronic part 160 is filled with an insulating material to form the conductive filling part 150. In this case, when the cavity plating unit 140 and the electronic component 160 are brought into direct contact with each other, the conductive filling unit 150 may not be formed.
In this state, it is possible to check whether the electronic component 160 is well connected, whether there is a disconnected portion in the first and second metal patterns 130, and the like.
Next, referring to FIG. 5G, on the upper surface of the first metal pattern 120, the first insulating layer 110, the cavity plating portion 140, the conductive filling portion 150, and the electronic component 160, 3 insulating layer 172 is formed. At this time, the disconnection portion 141 can be filled with an insulating material such as resin, as illustrated in Figs. 2 to 4, and this insulating material may be used to implement the third insulating layer 172. [
Next, referring to FIG. 5H, the second insulating layer 171 may be formed by laminating the interlayer insulating material after removing the deterrent film DF.
Next, referring to FIG. 5I, the first through sixth vias V6 and the first circuit pattern 181 and the second circuit pattern 182 may be formed.
As shown in the figure, the first metal pattern 120 or the second metal pattern 130, the cavity plating portion 140, the third metal pattern 120, or the like, such as the first via V1, the third via V3, and the fourth via V4, A via hole may be formed in a selected region of the conductive filler 150 and the external electrode 161 to form a via.
Conventionally, as the size of the electronic component 160 is reduced, it is difficult to process a via hole that accurately exposes the external electrode 161 of the electronic component 160. However, according to the method of manufacturing an electronic component embedded substrate according to an embodiment of the present invention It will be understood that the electrical connection of the electronic component 160 can be secured even if a via hole is formed in a wider area than in the prior art.
In addition, when the electronic component 160 is a capacitor, since the cavity plating portion 140 and the external electrode 161 are in contact with each other over a large area, a low resistance can be realized on the charge transfer path of the electronic component 160 , There is an advantage that connection reliability can be improved.
In the above description, a process of manufacturing by a substractive process has been described as an example, but the process may be implemented by an additive process.
6A to 6D illustrate a process of forming a cavity 111 having a cavity plating portion 140 in a first insulation layer 110 in a method of manufacturing an electronic component embedded board according to an embodiment of the present invention. Fig.
First, referring to FIG. 6A, a first temporary cavity 111a and a second temporary cavity 111b may be formed in the first insulating layer 110. FIG.
At this time, the first temporary cavity 111a has a "C" shape, and the second cavity 111 can have a first temporary cavity 111a that is inverted from left to right, that is, "⊃" shape.
The first temporary cavity 111a and the second temporary cavity 111b are formed so that their opened directions are opposed to each other so that a temporary gap 112 is formed between the first temporary cavity 111a and the second temporary cavity 111b. Can be formed.
6B and 6C, a resist portion R may be formed to perform a plating process, and a cavity plating portion 140 may be formed on the surface of the cavity 111 by electroless or electrolytic plating .
6C and 6D, the temporary plating layer 112 is removed along the cutting line CL and the resist portion R is also removed to form the cavity plating portion 140 ) Can be formed.
In this case, the plating unit 140 'formed in the area indicated by the dotted line may perform the function of improving the electrical connection between the second metal pattern and the cavity plating unit 140.
7A to 7C are schematic views illustrating a process of forming a cavity 111 having a cavity plating portion 140 in a first insulating layer 110 in a method of manufacturing an electronic component embedded board according to another embodiment of the present invention Fig.
First, referring to FIG. 7A, a part of the first insulating portion is processed to form a third temporary cavity 111c having a first protrusion 113 and a second protrusion 114 formed therein.
At this time, the first protrusion 113 and the second protrusion 114 may be formed to be symmetrical with respect to each other.
7B and 7C, a conductive material is coated on the surface of the third temporary cavity 111c by an electroless or electrolytic plating method, and then the first protrusion 113 and the second protrusion 113 are formed along the cutting line CL, The cavity plating portion 140 can be formed by removing a part of the two protrusions 114. [
100: electronic component built-in substrate
110: first insulating layer
111: cavity
111a: first temporary cavity
111b: second temporary cavity
111c: third temporary cavity
112: Temporary remainder
113: first protrusion
114: second protrusion
120: first metal pattern
130: second metal pattern
140, 340: Cavity plating section
141, 341, 342:
150, 250, 350: conductive filling part
160: Electronic parts
161: external electrode
171: second insulating layer
172: third insulating layer
172 ': Insulation material
181: first circuit pattern
182: second circuit pattern
VT: Survia
V1: 1st Via
V3: Third Via
V4: fourth vias
V6: 6th Via
DF: DITTECH film
R: resist portion
An electronic component built-in substrate having an electronic component provided with an external electrode on a side surface,
A cavity formed in at least one insulating layer provided inside the electronic component built-in substrate;
At least a part of which is inserted into the cavity;
A cavity plating unit formed on a surface of the cavity facing at least one surface of the electronic component and contacting the external electrode; And
At least one of the external electrodes and at least one of the cavity plating portions being in contact with one surface at the same time;
Electronic component embedded board.
A cavity plating unit formed on a surface of the cavity facing at least one surface of the electronic component;
A conductive filling part filled with a conductive material between the cavity plating part and the external electrode to electrically connect the cavity plating part and the external electrode; And
At least one of the external electrodes and at least one of the conductive fillers being simultaneously in contact with one surface;
At least one of the external electrodes, at least one of the conductive filling parts, and at least one of the cavity plating parts,
Wherein the external electrode comprises at least two electrodes separated from each other at a surface of the electronic component,
The cavity plating unit connected to the electrodes may be provided with a plurality of disconnection units so that the electrodes are electrically isolated from each other,
Each of the cavity plating portions electrically separated by the disconnection portions and the conductive filling portions are filled between the respective electrodes
A space between the electrodes, between the disconnection portions, and between the conductive filling portions is filled with an insulating material
And a metal pattern provided on a surface of the insulating layer and electrically connected to the cavity plating portion,
Wherein one side of the via is also in contact with at least a portion of the metal pattern
The cavity plating unit connected to the electrodes may be formed with a plurality of disconnection units so that the electrodes are electrically isolated from each other.
A plurality of the electronic parts are inserted into the cavity, and at least two of the plurality of electronic parts are connected in parallel with each other
The cavity plating unit connected to the electrodes may be formed with a plurality of disconnection units so that the electrodes are electrically isolated from each other
And a space between the electrodes and between the disconnection portions is filled with an insulating material
The cavity plating portions connected to the electrodes are formed with disconnection portions so that the electrodes are electrically isolated from each other
A first insulating layer having a first metal pattern on a lower surface, a second metal pattern on an upper surface thereof, and a cavity penetrating between the upper surface and the lower surface;
An electronic component having at least one external electrode on its surface, and at least a part of which is inserted into the cavity;
A cavity plating portion formed on a surface of the cavity facing the external electrode, the cavity plating portion being electrically connected to at least one of the first metal pattern and the second metal pattern;
A conductive filling part formed by filling a conductive material between the cavity plating part and the external electrode;
A second insulating layer covering the first metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the exposed surface of the electronic component;
A first circuit pattern formed on a surface of the second insulating layer; And
Wherein at least a part of the external electrodes, at least part of the conductive filling parts, at least part of the cavity plating part and at least part of the part of the first metal pattern which is in contact with the cavity plating part are simultaneously contacted, A first via that is in contact with the pattern;
Wherein the electronic component is provided with at least two external electrodes formed in regions separated from each other on a surface of the electronic component,
The cavity plating unit connected to the external electrodes may be provided with a plurality of cut-outs to electrically disconnect the electrodes,
The conductive filler portion is filled between each of the cavity plating portions electrically isolated by the disconnection portions and each of the external electrodes
Wherein a material forming the second insulating layer is filled in spaces between the external electrodes, between the single-wire portions, and between the conductive filling portions
A fifth via which is in contact with at least a part of the first metal pattern except for the contact with the cavity plating part, and the other face is in contact with at least a part of the first circuit pattern;
A third insulating layer covering the second metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the exposed surface of the electronic component;
A second circuit pattern formed on a surface of the third insulating layer; And
At least one area selected from at least a part of the external electrodes, at least a part of the conductive filling part, at least part of the cavity plating part, and at least part of the part of the second metal pattern contacting the cavity plating part, A third via contacting the other surface of the second circuit pattern;
Wherein at least one of the material forming the first insulating layer and the material forming the second insulating layer is filled in the space between the external electrodes, between the disconnection portions, and between the conductive filling portions
A sixth via which is in contact with at least a part of the second metal pattern except for the contact with the cavity plating portion, and the other face is in contact with at least a part of the second circuit pattern;
A method of manufacturing an electronic component built-in substrate for manufacturing an electronic component built-in substrate having an electronic component provided with external electrodes,
(A) forming a cavity in at least one insulating layer provided inside the electronic component built-in substrate, and plating a conductive material on the surface forming the cavity to form a cavity plating portion;
(B) inserting at least a portion of the electronic component into the cavity; And
(C) forming a via which is in contact with at least a part of the external electrodes and at least a part of the cavity plating part simultaneously;
A method of manufacturing an electronic component embedded board.
Between the step (B) and the step (C)
Further comprising the step of filling a space between the electronic component and the cavity plating portion with a conductive material
(A1) a first temporary cavity of a "C" -shaped shape and a second temporary cavity of a shape symmetrical to the first temporary cavity are machined to face each other while being spaced apart from each other at a predetermined interval in the insulating layer, Forming a temporary residue in a portion of the region;
(A2) plating a surface of the first temporary cavity and the surface of the second temporary cavity with a conductive material; And
(A3) removing the temporary residue;
A method of manufacturing an electronic component built-in substrate for manufacturing an electronic component built-in substrate having an electronic component,
(A) forming a cavity in at least one insulating layer provided inside the electronic component built-in substrate, and plating a conductive material on the surface forming the cavity to form a cavity plating portion; And
(B) inserting at least a portion of the electronic component into the cavity;
(a1) a first protrusion formed by protruding the insulating layer from one surface of the cavity in the direction of the facing surface, and a second protrusion formed on the surface of the cavity, the protrusion being formed to be symmetrical with the first protrusion, Forming a third temporary cavity in the excluded region;
(a2) plating a surface of the third temporary cavity with a conductive material; And
(a3) removing a portion of the first protrusion and the second protrusion;
(a) providing a first insulating layer having a first metal pattern on its lower surface and a second metal pattern on its upper surface;
(b) forming a cavity in the first insulating layer, and plating a conductive material on the cavity forming surface to form a cavity plating portion electrically connected to at least one of the first metal pattern and the second metal pattern step;
(c) bonding a detent film to a lower surface of the first metal pattern;
(d) inserting at least a part of an electronic component having a plurality of external electrodes on a surface thereof into the cavity, thereby bonding a lower surface of the electronic component to the detetch film;
(e) filling a conductive material between the cavity plating portion and the external electrodes to form a conductive filling portion;
(f) forming an insulating material on the exposed surfaces of the second metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component to form a third insulating layer;
(g) a portion of at least a portion of the external electrodes, at least a portion of the conductive filler, at least a portion of the cavity plating portion, and a portion of the second metal pattern that is in contact with the cavity plating portion, Processing a via hole exposing at least one region selected from at least a portion; And
(h) filling the via hole with a conductive material and forming a second circuit pattern on the upper surface of the third insulating layer;
(b1 ') a first protrusion formed by protruding the insulating layer from one surface of the cavity in the direction of the facing surface, and a second protrusion formed on the surface facing the first protrusion to be symmetrical with the first protrusion, Forming a third temporary cavity in an area other than the first temporary cavity;
(b2 ') plating a surface of the third temporary cavity with a conductive material; And
(b3 ') removing a portion of the first protrusion and the second protrusion;
(d) inserting at least a part of an electronic component having a plurality of external electrodes on a surface thereof into the cavity, thereby bonding the lower surface of the electronic component to the detetch film;
(f1) forming a third insulating layer by coating an insulating material on the exposed surfaces of the second metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component;
(f2) After removing the detent film, an insulating material is applied to the exposed surfaces of the first metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component to form a second insulating layer ;
(g1) forming a first via through the second insulating layer and a first circuit pattern provided on a lower surface of the second insulating layer and connected to the first via; And
(g2) forming a third via hole penetrating the third insulating layer and a second circuit pattern provided on an upper surface of the third insulating layer and connected to the third via;
Wherein the first via is formed on at least a part of the external electrodes, at least a part of the conductive filling part, at least part of the cavity plating part, and at least part of the contact part of the first metal pattern, Contacted,
The third via is formed on at least a part of the outer electrodes, at least a part of the conductive filling part, at least part of the cavity plating part, and at least part of the contact part of the second metal pattern, Is formed to contact
A plurality of the electronic components are inserted into the cavity and the lower surface of the electronic component is bonded to the detent film
Wherein at least two of the plurality of electronic components are connected in parallel with each other
KR20120139727A 2012-12-04 2012-12-04 Substrate embedding electronic component and manufacturing mehtod thereof KR101483825B1 (en)
KR20120139727A KR101483825B1 (en) 2012-12-04 2012-12-04 Substrate embedding electronic component and manufacturing mehtod thereof
TW102140974A TW201433226A (en) 2012-12-04 2013-11-12 Electronic component embedded substrate and manufacturing method thereof
JP2013235071A JP2014110423A (en) 2012-12-04 2013-11-13 Circuit board with built-in electronic component and manufacturing method therefor
US14/090,469 US20140151104A1 (en) 2012-12-04 2013-11-26 Electronic component embedded substrate and manufacturing method thereof
KR20140071769A KR20140071769A (en) 2014-06-12
KR101483825B1 true KR101483825B1 (en) 2015-01-16
ID=50824330
US (1) US20140151104A1 (en)
JP (1) JP2014110423A (en)
KR (1) KR101483825B1 (en)
TW (1) TW201433226A (en)
KR20160091050A (en) 2015-01-23 2016-08-02 삼성전기주식회사 A printed circuit board comprising embeded electronic component within and a method for manufacturing
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WO2012157426A1 (en) * 2011-05-13 2012-11-22 イビデン株式会社 Circuit board and manufacturing method thereof
JP5721541B2 (en) * 2011-05-31 2015-05-20 エルナー株式会社 Manufacturing method of component mounting printed wiring board
2012-12-04 KR KR20120139727A patent/KR101483825B1/en active IP Right Grant
2013-11-12 TW TW102140974A patent/TW201433226A/en unknown
2013-11-13 JP JP2013235071A patent/JP2014110423A/en active Pending
2013-11-26 US US14/090,469 patent/US20140151104A1/en not_active Abandoned
US20140151104A1 (en) 2014-06-05
KR20140071769A (en) 2014-06-12
JP2014110423A (en) 2014-06-12
TW201433226A (en) 2014-08-16
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CN103141164B (en) 2016-06-08 Component-embedded substrate and manufacturing method thereof