Source: https://patents.google.com/patent/JP3668673B2/en
Timestamp: 2020-06-02 22:03:44
Document Index: 283116619

Matched Legal Cases: ['Application No. 8', 'art 216', 'art 218', 'art 222', 'art 216', 'art 218', 'art 222', 'art 216', 'art 218', 'art 222', 'art, 5', 'art, 6', 'art, 7']

JP3668673B2 - Error correction code configuration method, decoding method, transmission apparatus, network - Google Patents
Error correction code configuration method, decoding method, transmission apparatus, network Download PDF
JP3668673B2
JP3668673B2 JP2000179377A JP2000179377A JP3668673B2 JP 3668673 B2 JP3668673 B2 JP 3668673B2 JP 2000179377 A JP2000179377 A JP 2000179377A JP 2000179377 A JP2000179377 A JP 2000179377A JP 3668673 B2 JP3668673 B2 JP 3668673B2
JP2000179377A
JP2001358597A (en
隆 森
2000-06-09 Application filed by 株式会社日立コミュニケーションテクノロジー filed Critical 株式会社日立コミュニケーションテクノロジー
2000-06-09 Priority to JP2000179377A priority Critical patent/JP3668673B2/en
2001-12-26 Publication of JP2001358597A publication Critical patent/JP2001358597A/en
2005-07-06 Publication of JP3668673B2 publication Critical patent/JP3668673B2/en
The present invention relates to an error correction code configuration method, a decoding method, a transmission apparatus, and a network configuration suitable for an optical communication network.
Today, with the development of digital signal processing technology such as LSI, encoding / decoding technology of error correction codes is used in a wide field for the purpose of ensuring high signal quality. In particular, among block codes having a mathematically ordered system, codes called systematic codes are exclusively used for engineering because of information transparency. In this method, a continuous signal sequence is divided into fixed blocks and coding is performed for each block. The original signal information is manipulated only by adding a check bit to a predetermined empty area in the signal. It has the feature that it is not. As the block code, a Hamming code, a BCH code (Bose-Chudhuri-Hocquenhem code), a Reed-Solomon code, and the like have been used for a long time. Hereinafter, encoding / decoding of an error correction code is simply referred to as encoding / decoding.
On the other hand, optical fiber communication capable of large-capacity data transmission uses a relatively high-quality transmission line called an optical fiber as a medium, and the bit error rate is usually 10 minus 10 or less. Further, the path switching at the time of signal deterioration can be easily realized by adopting a redundant system configuration including a standby optical fiber with respect to the working optical fiber. For this reason, the system does not presuppose the use of error correction codes. A typical example of this optical fiber communication is a digital synchronous transmission system in which a global standard exists. This system is recommended by the International Telecommunications Union (hereinafter referred to as ITU-T) as recommended by G. As SDH (Synchronous Digital Hierarchy) (established in 1988) defined in 707, etc., and SONET (Synchronous Optical Network) (established in 1991) defined by the American Standardization Committee (hereinafter referred to as ANSI) in the standard T1.105, Widely used in trunk transmission networks around the world.
As an exception to the introduction of error correction codes into optical fiber communications, ITU-T recommends G. One example is one in which eight error correction Reed-Solomon codes (255, 239) are applied to the frame format specified in 975 (established in 1996). Further, JP-A-62-2212223 is known as a known example closest to the present invention.
Coupled with today's widespread use of Internet communication, trunk networks and regional networks using optical fiber communication have been forced to increase the capacity of data to be transmitted. Time division multiplexing, wavelength division multiplexing, and their combined technologies Is being realized.
However, as the time division multiplexing increases, the signal bit width becomes narrower, and the signal quality deteriorates due to the effects of various dispersions and nonlinearities that are the physical properties inherent to optical fibers. Transmission distance can be reduced. In optical fiber communication, a bit error rate of 10 minus 12 or less is often guaranteed as quality, and the multiplicity tends to increase every multiple of 2. Also, because of the dispersion and nonlinearity of the optical fiber, the distance that can be transmitted for a given transmission light power is inversely proportional to the square of the multiplicity, so when the multiplicity is doubled, the distance that can be transmitted is A quarter. Since this corresponds to a degradation loss of 6 dB, a loss compensation of 6 dB or more is required to upgrade the transmission capacity by two times by time division multiplexing while maintaining the transmission distance. Therefore, when this loss compensation is obtained using an error correction code, a coding gain of 6 dB or more is required. The gain of the 8 error correcting Reed-Solomon codes is 5.4 dB with respect to a bit error rate of 10 minus 12 in consideration of a transmission rate increase of about 7%. Not enough to realize double transmission capacity.
Further, as the wavelength division multiplexing increases, the wavelength intervals of a plurality of optical signals transmitted through one optical fiber core line are adjacent to each other, the degree of separation is deteriorated, and the transmission distance is shortened as described above. . Alternatively, even if the wavelength intervals are sufficiently far apart so as not to degrade the degree of separation, if the bit rates of each wavelength are not all the same, the transmission distance is determined by the highest bit rate, so an optical signal with a low bit rate Although it is possible to transmit to farther distances, it can only be used with limited transmission distance. Although the bit rates of a plurality of optical signals transmitted through one optical fiber core wire differ depending on the generation period, the ratio is often about twice as long as one period. Therefore, for the same reason as in the above example, in wavelength division multiplex transmission, in order to maximize the transmission distance when optical signals of different bit rates are mixed, loss compensation of 6 dB or more is required for high bit rate signals. However, 8 error correcting Reed-Solomon codes alone are not sufficient to realize.
Further, in order to reduce the cost related to network construction instead of increasing the transmission capacity, the distance between the relay devices and terminal devices that electrically reproduce digital signals (hereinafter simply referred to as the relay interval) is increased. When the number of signals is reduced, the signal quality deteriorates as the relay interval becomes longer. For example, when the relay interval is quadrupled, loss compensation of 6 dB or more is necessary, but eight error correcting Reed-Solomon codes are not sufficient to realize.
In addition, the increase in Internet communication has increased demand for 1000Base-SX, 1000Base-LX, and 1000Base-CX commonly called geyser signals as defined by IEEE 802.3z standard of Institute of Electrical and Electronics Engineers, Inc. There is a need to transmit a long-distance section within a regional network that accommodates a Gigaisa signal as an optical signal or a trunk network. Since the Gigaisa signal uses a retransmission request method called ARQ (Auto Repeat Request) based on end-to-end communication in a layer higher than the link layer, it does not have an error correction code.
Also, Recommendation G. The 975 error correction method parallelizes an SDH STM-16 signal having a bit rate of 2.48832 Gbit / s for each bit and divides it into (8 × n) subframes each having a length of 238 bits. Then, 8 error correction Reed-Solomon codes (255, 239) are converted into 8 subframes, the check bits and the information for the framing structure are added, and the subframe length is converted to 255 bits each. The (8 × n) subframes are interleaved bit by bit to form an FEC frame having a bit rate of about 2.666 Gbit / s. In order to easily configure an encoder and a decoder, a method of setting the value of n described above to 16 is often used. In this case, the processing speed of one subframe is about 21 (accurately 19. 44 × 255 ÷ 238) Mbit / s.
However, when an SDH STM-64 or SONET OC-192 signal with a bit rate of 9.95328 Gbit / s, which is four times the above, is converted into an FEC frame, it is first divided into four STM-16 equivalent signals in parallel. There is a need to. Recommendation G. This is because the 975 error correction method uses the STM-16 signal as the minimum unit. Therefore, in this case, the value of n is quadrupled from 16 to 64, and the processing speed in the encoder or decoder is the same as the previous approximately 21 Mbit / s, but a quadruple scale is required. Become. For example, when an encoder / decoder having a processing capacity of about 170 Mbit / s is used for each STM-16 signal, only 16 are required for the STM-16 signal, but 64 STM-64 signals are required. In the case of using an encoder / decoder having a processing capacity of about 2.7 Gbit / s per one, it is necessary to have four pieces which are only one. This increase in scale is proportional to the increase in bit rate. For this reason, when the client signal is STM-64 or the like, the codec device including the encoder / decoder becomes large, and the price of the device increases.
The object of the present invention is to maintain the original transmission distance when the time division multiplexing of an optical signal is increased, or to maximize the transmission distance when optical signals of different bit rates are mixed under wavelength division multiplexing. Another object of the present invention is to provide a method for constructing an error correction code suitable for increasing the relay interval under the condition that the multiplicity of time division is not changed, and a transmission apparatus and network using the same.
In particular, when the time division multiplexing of an optical signal transmitted through a single optical fiber is doubled, or when such an optical signal is wavelength-multiplexed, the original transmission distance is maintained, It is an object of the present invention to provide a method for constructing an error correction code having a gain sufficient to realize a four-fold increase in the relay interval, and a transmission apparatus and network using the error correction code.
Furthermore, it is possible to provide a method of constructing an error correction code having a higher gain while ensuring the interoperability with an existing transmission network in which eight error correction Reed-Solomon codes are introduced, and a transmission apparatus and a network using the same. It is in.
Another object of the present invention is to provide an error correction code configuration method suitable for long-distance transmission of a Geiger signal, and a transmission apparatus and network using the same.
It is another object of the present invention to provide a method for constructing an error correction code that suppresses an increase in device scale when a client signal has a bit rate of STM-16 or higher, and a transmission device and a network using the same.
In order to solve the above-described problems, the error correction code configuration method according to the present invention divides a client signal having a constant bit rate into a code information block for each a byte, and has a code information block and an empty area of b bytes. Then, the bit rate is increased so that the c / a ratio becomes 110% or more to obtain a code block 3 of c bytes, and the code information block in the code block is changed with respect to a bit error rate of 10 minus 12 Error correction coding was performed so as to have a coding gain of 6 dB or more, and the check bits were arranged in the empty area to form a super FEC signal.
Alternatively, a client signal having a constant bit rate is divided into (Kr × Kc) bytes to form an information block 100, and the bit rate of the information block 100 is increased by {(Nr × Nc) ÷ (Kr × Kc)} times, An encoding block 130 of (Nr × Nc) bytes is used, and the information block 100 is interleaved Kr times every arbitrary δ bytes and arranged in (Kr rows × Kc columns) in the encoding block 130, and an empty area 110B, 110C, and 120B are created. Then, k error correction encoding (C1 encoding) is performed for each Kr number of code sub-blocks 10-i (i = 1, 2, 3,..., Kr), and the check bits are stored in the empty area 110B. Deploy. Thereafter, m bytes consecutive from each of the Kr code sub-blocks 10-i are taken out, and jm (m × Nr) -byte code sub-blocks 20-j (j = 1, 2, 3,..., j error correction coding (C2 coding) is performed every jm), and the check bits are arranged in the empty area 120B.
Then, a pseudo product code or a concatenated code in which {(Nr × Nc) ÷ (Kr × Kc)} is 110% to 130% at 100 minutes and C1 encoding and C2 encoding are combined Thus, a super FEC signal having a coding gain of 6 dB or more with respect to a bit error rate of 10 to the -12th power is obtained.
The same frame structure is used regardless of the type of client signal.
Hereinafter, it demonstrates in detail, using drawing.
The signal applied to the present embodiment is a signal having a certain bit rate that can be divided into code blocks having a certain length, and the applied error correction code is a systematic code. For example, a transmission signal of SDH or SONET is a framed signal with a period of 125 microseconds, and can be arbitrarily divided into fixed-length code blocks, and thus is included in the above category.
Hereinafter, the Reed-Solomon code is a code on the Galois field (256), and the BCH code is a binary BCH code. The Reed-Solomon code is simply abbreviated as RS code.
An embodiment of the error correction coding method according to the embodiment of the present invention will be described with reference to FIGS. 1, 2, 20, and 21. FIG.
1 and 2 show information data areas and encoding areas as frame diagrams.
(Explanation on the encoding side)
A coding side that receives a client signal from a communication channel on the client side and performs error correction coding and then transmits it as a super FEC signal to the super line side will be described.
The client signal may actually be either an electrical signal or an optical signal. In the case of an optical signal, the client signal is converted into an electrical signal.
A client signal whose bit sequence is serial in time series is divided into (Kr × Kc) byte blocks (referred to as first encoded information blocks), and each of the first encoded information blocks is continuously predetermined. Parallel development is performed in Kr stages every byte (every δ bytes).
Here, Kr and Kc are arbitrary integer values, for example, Kr = 16 and Kc = 238. An area 100 shown in white in FIG. 1 represents a first encoded information block that is developed in parallel. 1 indicates one byte, and the direction of the bits in the byte may be in the row direction or the column direction. In the row direction, parallel expansion for Kr bits is performed. In the column direction, ( Parallel development for Kr × 8) bits. In the following, it is treated as parallel expansion of Kr stages regardless of the direction of the bits in the byte. However, in the case of the column direction, (Kr × 8) may be newly set as Kr and processed similarly.
Further, the order of parallel expansion is such that the consecutive δ bytes on the serial client signal are mapped to the serial δ bytes on the first row in FIG. This is done by mapping to the serial δ bytes in the second row. The value of δ may be an arbitrary divisor of Kc, and may be 1, for example, or may be the number of interleaved bytes of the multiplexing rule when the client signal is a SONET / SDH signal. Further, in this parallel development, every δ bits may be used instead of every δ bytes. In the case of every δ bits, “every δ bytes” may be replaced with “every δ bits” in the following description. FIG. 20 shows the relationship between the serial bit or byte sequence of the client signal and that of the parallel signal. Kc * in the figure is a value obtained by dividing Kc by δ.
FIG. 20 shows the relationship of the arrangement of data bits and bytes when the client signal is converted into a parallel client signal or vice versa.
When the client signal is parallelized with the parallel client signal, the continuous δ bytes (# 1-1) on the serial client signal are converted into the serial δ bytes (# 1-1) of the first row of the parallel signal. ) And the subsequent consecutive δ bytes (# 2-1, # 3-1,..., # Kr-1) on the serial client signal are assigned to the second to Kr rows of the parallel signal. Is mapped to δ bytes (# 2-1, # 3-1,..., # Kr-1), thereby paralleling (Kr × δ) bytes on the serial client signal to Kr pieces in parallel. To do. On the serial client signal, the subsequent consecutive (Kr × δ) bytes are parallelized to Kr in the same manner as described above. Of course, the signals paralleled in this way are transmitted simultaneously in each column in the apparatus.
Conversely, when serializing a parallel client signal into a client signal, the reverse operation is performed.
The first encoded information block signal of (Kr × Kc) bytes expanded in parallel is received, the bit rate is increased (Nc ÷ Kc) times, and an empty area of {Kr × (Nc−Kc)} bytes is obtained. create. Areas 110B and 110C indicated by right oblique lines in FIG. 1 correspond to this. Here, Nc is an arbitrary integer value, for example, 255.
Next, first, each Kr number of rows (each Nc byte) is set as a code sub-block 10-i (i = 1, 2,..., Kr), and the first encoding (for each code sub-block 10-i is performed independently). (Referred to as C1 code). Specifically, in each of the code sub-blocks 10-i, check bit calculation of C1 encoding is performed on the total (Kc + 1) bytes from the first column to the (Kc + 1) th column in the area 110A, and the check bits are stored in the area. It is arranged in the total (Nc−Kc−1) bytes from the (Kc + 2) th column to the Ncth column in 110B.
As an example of the C1 code, a φ error correction RS code (na, ka) or a η error correction BCH code (nb, kb) can be used.
Here, in general, the notation of the RS code (na, ka) means that the code length is na symbols, the information length is nb symbols, and the check bit is (na−nb) symbols. In the case of codes on the field (256), one symbol is 1 byte. The notation of the BCH code (nb, kb) means that the code length is nb bits, the information length is kb bits, and the check bit is (nb-kb) bits.
As for the above RS code, when Nc is 255 or less, each parameter is
1 ≦ φ ≦ [(Nc−Kc−1) ÷ 2]
na = Nc
ka = na-2 × φ
A code that satisfies the following equations can be used.
When Nc is 256, it is necessary to exclude one byte from the code area. When the first column is an excluded area, each parameter is
na = Nc-1
RS codes that satisfy the following equations can be used,
If the 256th column is to be excluded, each parameter is
1 ≦ φ ≦ [(Nc−Kc−2) ÷ 2]
RS codes satisfying the following equations can be used. Here, [z] represents the maximum integer less than or equal to z.
On the other hand, for the above BCH code, the number of bits of each code sub-block 10-i is Np, and the number of bits from the second column to the (Kc + 1) -th column of each code sub-block 10-i is Kp. ,
If Np is not a factorial of 2, then r
Np <(2 to the power of r)
Each parameter is the smallest integer that satisfies
1 ≦ η ≦ [(Np−Kp−s) ÷ r]
nb = Np
kb = nb−r × φ
A BCH code based on a Galois field (2 to the power of r) that satisfies the following equations can be used.
When Np is 2 to the power of r, it is necessary to exclude one bit from the code area. For example, with the last 1 bit of each code sub-block 10-i as an excluded area, each parameter is
1 ≦ η ≦ [(Np−Kp−s−1) ÷ r]
nb = Np-1
Here, s is the number of parallel expansions of Kr stage parallel expansions (Kr × 8) bits, and each bit constitutes a code sub-block 10-i (i = 1, 2,..., Kr × 8). 1 only in some cases, 8 otherwise.
When ka is larger than (Kc + 1) or kb is larger than (Kp + s), an area other than the area necessary for the check bit in the area 110B may be used as an encoding information area, or virtual. It may be a fixed value.
Further, in the case of the C1 code, when the above na is less than 255 or when nb is less than ((2 to the power of r) -1), the theoretically short information is virtually reduced to zero. It is a sign.
Next, the entire (Kr × Nc) bytes of the C1 encoded Kr code sub-blocks 10-i (i = 1, 2,... Kr) are used as the second encoded information block, and the number of parallel stages is changed from Kr to Nr. To an empty area of {(Nr−Kr) × Nc} bytes. The area 120A shown in white in FIG. 2 corresponds to the second encoded information block, and the area 120B shown in the right oblique line corresponds to the empty area. Here, Nr is an arbitrary integer value larger than Kr, for example, 18.
Each of the signals after the increase in the number of parallel stages is divided into arbitrary m columns, that is, (Nr × m) bytes, as code sub-blocks 20-j (j = 1, 2,..., Jm). The second encoding (referred to as C2 code) is performed independently for each block 20-j. Specifically, in each of the code sub-blocks 20-j, C2 encoding check bit calculation is performed on the total (Kr × m) bytes from the first row to the Kr-th row in the area 120A, and the check bits are stored in the area. It is arranged within the total {(Nr−Kr) × m} bytes from the (Kr + 1) th row to the Nrth row in 120B. Here, jm is <Nc ÷ m>, and <z> represents a minimum integer value equal to or greater than z.
Here, it is also possible to shift the check bits of the code sub-block 20-j (j = 1, 2,..., Jm) to the check bit area in the next code sub-block 20- (j + 1). Thus, it is possible to suppress the occurrence of delay time in encoding. In this case, the check bit of the last code sub-block 20-jm is arranged in the code sub-block 20-1 of the next frame.
When m is not a divisor of Nr including 1, the number of columns of the last code sub-block 20-jm is less than m. In such a case, the code sub-block 20-jm may be excluded from the C2 encoding target, or may be C2 encoded with no break across the next second encoded information block. In the latter case, appropriate encoding / decoding can be realized by inserting a specific framing pattern as described later in the usage method in the first column.
As an example of the C2 code, a λ error correcting RS code (nd, kd) or a ρ error correcting BCH code (ne, ke) can be used.
As the above RS code, when Nr is 255 or less, each parameter is
1 ≦ λ ≦ [(Nr−Kr) × m ÷ 2]
nd = Nr
kd = nd−2 × λ
When Nr is 256, it is necessary to exclude one byte from the code area. A predetermined byte in the area 120B is an excluded area, and each parameter is
1 ≦ λ ≦ [{(Nr−Kr) × m−1} ÷ 2]
nd = Nr-1
RS codes satisfying the following equations can be used.
On the other hand, for the BCH code, the number of bits of each of the code sub-blocks 20-j is Nq, and the number of bits from the first row to the Nr-th row of each of the code sub-blocks 20-j is Kq.
If Nq is not a factorial of 2, then r
Nq <(2 to the power of r)
1 ≦ ρ ≦ [(Nq−Kq) ÷ r]
ne = Nq
ke = ne−r × ρ
In addition, when Np is 2 to the power of r, it is necessary to exclude one bit from the code area. A predetermined bit in the area 120B is set as an excluded area, and each parameter is
1 ≦ ρ ≦ [(Nq−Kq−1) ÷ r]
ne = Nq-1
When kd is larger than (Kr × m) or ke is larger than Kq, an area other than the area necessary for the check bit in the area 120B may be used as an information area for encoding, or a virtual area It may be a fixed value.
In addition, when the above nd is less than 255 in the C2 code or when ne is less than ((2 to the power of r) -1), the theoretically insufficient information is virtually reduced to zero. It is a coded code.
As described above, the (Nr × Nc) byte-pre-coded block 130 encoded with C1 and C2 is executed for each ε byte in the reverse order when the first encoded information block is first developed in parallel. Nr-stage interleaving is performed from line to line to convert the bit sequence into a digital signal that is serial in time series, scrambled as necessary, and then transmitted as a super FEC signal to the super line side. Here, the interleaving order is such that the continuous ε bytes in the first row in FIG. 2 are mapped to the continuous ε bytes on the serial digital signal, and the continuous ε bytes in the second row are serial digital. Mapping to the next consecutive ε bytes on the signal and so on. The value of ε may be any divisor as long as it is a divisor of Nc. For example, it may be 1, or may be the same as δ. If the client signal is a SONET / SDH signal, it may be the number of interleaved bytes of the multiplexing rule. . In the above, every ε bits may be used instead of every ε bytes. In the case of every ε bits, “every ε bytes” may be replaced with “every ε bits” in the above and the following description. FIG. 21 shows the relationship between the parallel bits and the serial bit and byte arrangement of the serialized super FEC signal. Nc * in the figure is a value obtained by dividing Nc by ε.
FIG. 21 shows the relationship between the arrangement of bits and bytes of data when the super FEC signal is converted into a parallel signal or vice versa.
When the super FEC signal is converted into a parallel signal, the continuous ε byte (# 1-1) on the serial super FEC signal is converted into the serial ε byte (# 1-1) of the first row of the parallel signal. After mapping, the subsequent ε bytes (# 2-1, # 3-1,..., # Nr-1) on the super FEC signal are each ε in the second to Nr rows of the parallel signal. By mapping to the bytes (# 2-1, # 3-1,..., # Nr-1), the continuous (Nr × ε) bytes on the super FEC signal are parallelized to Nr. On the super FEC signal, the subsequent (Nr × ε) bytes are parallelized to Nr in the same manner as described above. Of course, the signals paralleled in this way are transmitted simultaneously in each column in the apparatus.
Conversely, when serializing a parallel signal to a super FEC signal, the reverse operation is performed.
Note that the parallel signal in FIG. 21 includes the parallel signal in FIG. 20 with the check bit for the C1 code and the check bit for the C2 code.
As a result, the bit rate of the super FEC signal is {(Nr ÷ Kr) × (Nc ÷ Kc)} times the bit rate of the client signal. Note that scrambling may be performed in an appropriate parallel manner, for example, it may be performed on Nr-stage parallel signals before interleaving.
In the above, after dividing a client signal having a constant bit rate for each first encoded information block of (Kr × Kc) bytes, the bit rate is {(Nr × Nc) ÷ (Kr × Kc)} times at a time. To (Nr × Nc) bytes of the pre-encoded block 130, and the (Kr × Kc) -byte first encoded information block is interleaved Kr times for each byte and the pre-encoded block It may be arranged within (Kr rows × Kc columns) within 130 to create empty areas 110B, 110C, 120B.
(How to use the first column, insertion method)
In the first column of FIGS. 1 and 2, a framing pattern for establishing synchronization at the receiving side and overhead for OAM & P (Operation, Administration, Maintenance and Provisioning) of the transmission network are inserted. Specifically, in the stage after the bit rate of the first encoded information block of (Kr × Kc) bytes is increased (Nc ÷ Kc) times, a framing pattern is applied to a part or all of the first column. In the remaining area, the overhead for OAM & P of the transmission network is inserted. The overhead for OAM & P may not be inserted separately.
Here, it is assumed that at least two or more kinds of predetermined fixed values are inserted into the framing pattern, and those having the same pattern value are continuously arranged in the interleaving direction. For example, the same value (F6) hex as the A1 byte defined by SONET or SDH is set in the ix byte framing area F1 from the first row to the ixth row, and (ii) from the (ix + 1) th row to the yyth row. -Ix) The same value (28) hex as the A2 byte defined by SONET or SDH is inserted into the byte framing area F2. Here, (z) hex is expressed in hexadecimal. Ix and iy are arbitrary integer values satisfying 1 ≦ ix <ii ≦ Nr. For example, ix is an arbitrary integer value not less than 1 and not more than [Nr ÷ 2], and (ix, iy) = (iz, It may be iz × 2).
Of course, the framing pattern value may be other than this, and may be a pattern value in which the same value as a bit value is not continuous as much as possible.
Alternatively, a plurality of (p) second encoded information blocks or a plurality (p) already encoded blocks are set as one multiframe, and the first second encoded code in one multiframe. A predetermined framing pattern is inserted into a part or all of the first column of the encoded information block or the plurality of already-encoded blocks, and the remaining columns and the first column of the second to pth blocks The overhead for OAM & P of the transmission network may be inserted into the network.
Further, when m is not a divisor of Nr including 1 as described above, the last code sub-block 20-jm of the current second encoded information block is spanned to the next second encoded information block. When C2 encoding is performed without a break, a framing pattern set A is inserted into the first column of the current second encoded information block, and a certain code sub-block 20-jp starts from the next second encoded information block. A framing pattern set B different from the framing pattern set A is inserted into the first column of each block up to the second encoded information block (1 ≦ jp ≦ jm) that ends at the Nrth column. On the decoding side, by detecting this framing pattern set A, the code sub-block 20-1 can detect the second encoded information block starting from the first column, and the decoding operation is performed when the block position is first detected. An appropriate decoding operation can be realized by starting. As an example of the framing pattern set A, the insertion value to the framing area F1 is (F6) hex and the insertion value to the framing area F2 is (28) hex. As an example of the framing pattern set B at this time, to the framing area F1 The insertion value of (AA) hex and the insertion value to the framing area F2 may be (33) hex.
Instead of framing pattern set B, overhead for OAM & P of the transmission network may be inserted.
Further, when the super FEC signal is scrambled as described above, the framing pattern insertion area is not scrambled.
(Description on decryption side)
The decoding side that receives the super FEC signal and performs decoding and then transmits it as a client signal to the communication path on the client side will be described.
On the decoding side, the signals are processed in the reverse order to that on the encoding side. The super FEC signal encoded as described above is received via the transmission line on the super line side, frame synchronization is performed, descrambling is performed as necessary, and an encoded code for each (Nr × Nc) byte Each of the divided blocks is expanded in parallel (deinterleaved) into Nr stages every ε bytes. The entire area of FIG. 2 corresponds to the already-encoded block expanded in parallel. Note that frame synchronization and descrambling may be performed in parallel as appropriate. For example, at this stage, ε bytes may be developed in parallel in Nr stages.
Here, as shown in FIG. 21, the deinterleaving sequence is performed by mapping the continuous ε bytes on the serial super FEC signal to the serial ε bytes on the first row in FIG. The next consecutive ε bytes are mapped to the serial ε bytes of the second row.
After that, first, C2 code decoding (referred to as C2 decoding) is performed independently on the jm code sub-blocks 20-j (j = 1, 2,... Jm) in the order received.
Next, the C2 code check bit area 120B of {(Nr−Kr) × Nc} bytes in jm code sub-blocks 20-j (j = 1, 2,... Jm) subjected to C2 decoding is terminated and erased. Or ignore it in the rest of the process.
Each of the Kr code sub-blocks 10-i (i = 1, 2,... Kr) after C2 decoding is independently decoded with C1 code (referred to as C1 decoding).
Finally, the bit rate of the code sub-block 10-i (i = 1, 2,... Kr) after C1 decoding is reduced by (Kc ÷ Nc) times and used for a C1 code of {Kr × (Nc−Kc)} bytes. After erasing the check bit area, framing pattern area, and overhead area, Kr stage interleaving is performed from the first line to the Kr line in FIG. A client signal that is serial in time series is restored, converted into an optical signal as necessary, and output to a communication path on the client side. Here, as shown in FIG. 20, the interleaving sequence is performed by mapping the continuous δ bytes in the first row of FIG. 1 to the continuous δ bytes on the serial client signal, and continuing in the second row. This is done by mapping δ bytes to the next consecutive δ bytes on the serial client signal.
(Explanation of overhead separation / termination and performance monitoring method)
Note that the overhead separation / termination process for OAM & P in the transmission network is performed after the frame synchronization is established, and the bit rate for the code sub-block 10-i (i = 1, 2,... Kr) after C1 decoding is reduced. It shall be performed at a specific position before. In addition, regarding the performance monitoring of the number of bit errors and bit error rate in the transmission network, a parity of BIP (Bit Interleaved Parity) is added to the overhead for OAM & P, and either one before decoding or after decoding at the decoding side. The performance monitoring may be performed from the number of error bits that can be detected by the BIP parity check in FIG. 1, or the performance monitoring may be performed from the number of error bits directly corrected in the decoder. Furthermore, when either the C1 code or the C2 code is a Reed-Solomon code or a BCH code and the generator polynomial G (z) includes a factor of (z + 1), the result of the syndrome calculation regarding α to the zero power in the decoder May be used to perform performance monitoring. This utilizes the fact that the syndrome calculation relating to the zero power of α has a function equivalent to the parity check of BIP. Here, α is a primitive n-th root of a Galois field (2 to the nth power) based on the Reed-Solomon code or the BCH code.
Also, thresholds for bit error count and bit error rate were set from an external control system, and compared with the actual bit error count and bit error rate obtained by the above performance monitoring method, the threshold was exceeded. In such a case, a method of notifying the external control system of a deterioration alarm may be used.
Compensation method of RS polynomial and BCH code generator polynomial, check bit calculation method, decoding algorithm, that is, syndrome calculation method, error position and error value calculation method based on this, code length shortening Since the method to do is widely known, the details are omitted.
According to the present embodiment, an error correction code having a sufficient gain of 6 dB or more with respect to a bit error rate of 10 minus 12 can be easily configured. As a result, the transmission distance is maintained when the multiplicity in time division multiplexing is increased, the transmission distance is maximized when optical signals of different bit rates are mixed in wavelength division multiplexing, and the time division multiplicity is changed. It is possible to easily construct an error correction code suitable for increasing the relay interval under no conditions.
Another embodiment of the error correction coding method according to the present invention is shown in FIGS. Here, FIGS. 3 and 4 show data encoding areas as frame diagrams.
FIGS. 3 and 4 are the same as those in FIGS. 1 and 2, respectively, in the case of Kc = 238, Nc = 255, Kr = 16, and Nr = 18.
Further, assuming that δ = 1, the client signal is parallelized to 16 bytes for each byte. Each of 16 parallelized bytes corresponds to 16 rows. Furthermore, each byte is parallelized for each bit, and as a result, 128 client signals are parallelized.
Assuming that the code sub-block 10-i for C1 encoding is 16 sub-blocks each having a length of 255 bytes corresponding to 16 rows, as a C1 code,
・ 8 error correction RS codes (255, 239)
-11 error correction shortened BCH codes (2040, 1919) based on Galois field (2048)
Either of these can be applied. Of course, a code with a lower correction capability can also be used.
Further, if the code sub-block 10-i for C1 encoding is 128 sub-blocks each having a length of 255 bits corresponding to 128 parallel bits, as a C1 code,
Two error correcting BCH codes (255, 239) based on Galois field (256)
If m is 1 in FIG. 4, there are 255 code sub-blocks 20-j for C2 encoding, and the bit arrangement thereof is a serial arrangement in the column direction. In this case, as the C2 code,
-1 error correction shortened RS code (18, 16)
-Two error correction shortened BCH codes (144, 128) based on Galois field (256)
Either of these can be applied.
Alternatively, m is set to 2, 128 code sub-blocks 20-j for C2 encoding are created, and one column that is insufficient for the last code sub-block 20-128 is virtually regarded as zero. ,
・ 2 error correction shortened RS codes (36, 32)
-Three error correction shortened BCH codes (288, 261) based on Galois field (512)
Alternatively, m is set to 8, 32 code sub-blocks 20-j for C2 encoding are created, and one column which is insufficient for the last code sub-block 20-32 is virtually regarded as zero, so that C2 code is obtained. ,
・ 8 error correction shortened RS codes (144,128)
-11 error correction shortened BCH codes (1152, 1031) based on Galois field (2048)
Note that the bit rate of the super FEC signal of this embodiment is about 1.2054 times that of the client signal.
According to the present embodiment, an error correction code having a gain of about 8 dB with respect to a bit error rate of 10 minus 12 can be easily configured. As a result, the transmission distance is maintained when the multiplicity in time division multiplexing is increased, the transmission distance is maximized when optical signals of different bit rates are mixed in wavelength division multiplexing, and the time division multiplicity is changed. It is possible to easily construct an error correction code suitable for increasing the relay interval under no conditions.
Another embodiment of the error correction coding method according to the present invention is shown in FIGS. Here, FIGS. 5 and 6 show data encoding areas as frame diagrams.
FIGS. 5 and 6 are the same as the embodiments of FIGS. 1 and 2, respectively, in the case of Kc = 232, Nc = 256, Kr = 56, and Nr = 64.
Similarly to (Example 2), δ = 1 and the client signal is parallelized to 56 bytes for each byte. Each of the 56 bytes parallelized corresponds to 56 rows. Further, each 1 byte is parallelized for each bit, and as a result, 448 client signals are parallelized.
By making the code sub-block 10-i for C1 encoding into 56 sub-blocks each having a length of 256 bytes corresponding to 56 rows, as a C1 code,
11 error correction RS codes (255, 233) excluding the last 1 byte from the code area
16 error correction BCH codes (2047, 1904) based on Galois field (2048) with the last one bit excluded from the code area
Further, if the code sub-block 10-i for C1 encoding is 448 sub-blocks each having a length of 256 bits corresponding to 448 parallelized bits, as a C1 code,
Two error correcting BCH codes (255, 239) based on Galois field (256) excluding the last one bit from the code area
In FIG. 6, when m is 1, as C2 code,
・ 4 error correction shortened RS codes (64, 56)
7 error correction BCH codes (511, 448) based on Galois field (512) with the last one bit excluded from the code area
Alternatively, if m is 2, the C2 code is
・ 8 error correction shortened RS codes (128, 112)
12 error correction BCH codes (1023, 448) based on Galois field (1024) excluding the last one bit from the code area
Alternatively, if m is 4, the C2 code is
15 error correcting RS codes (255, 225) excluding the last 1 byte from the code area
23 error correction BCH codes (2047, 1794) based on Galois field (2048) with the last one bit excluded from the code area
Note that the bit rate of the super FEC signal of this embodiment is about 1.2611 times that of the client signal.
According to the present embodiment, an error correction code having a higher gain than that of the second embodiment can be easily configured.
In each of the above embodiments, the bit rate of the first encoded information block of (Kr row × Kc column) is increased and converted into the already-encoded block of (Nr row × Nc column). A predetermined check bit area may be created by increasing the number of columns while keeping the number of rows Kr constant. The following (Example 4) and (Example 5) show this example.
Another embodiment of the error correction encoding method according to the present invention is shown in FIG. Here, FIG. 7 shows a data encoding area as a frame diagram.
The present embodiment is based on the C1 encoding / decoding of FIG. 1 described in (Embodiment 1), and is further configured to be the C2 encoding / decoding of FIG. 7, and the check bit area for the C2 code is set to (implementation). Example 1) is different from FIG. 2 in that it is arranged at a different position. This difference is described below.
In the previous embodiment, the (Nr-Kr) rows created by increasing the number of parallel stages during C2 encoding are used as the C2 code check bit area 120B.
On the other hand, in the embodiment of FIG. 7, only when Nc is an integer multiple of m and (Nr × m) is an integer multiple of Kr, the code sub-block 10-i (i = 1, 2, ... Kr) is increased by (Nr ÷ Kr) times, and {(Nr−Kr) × m ÷ Kr} (an mc) empty area for every m columns And a C2 code check bit area 120C-j (j = 1, 2,..., Jm). The result is a total of (Nc + jm × mc) columns. This is also equal to (Nc × Nr ÷ Kr). Here, in this embodiment, jm is (Nc ÷ m).
Then, each divided by (m + mc) columns, that is, every (Nr × m) bytes is set as a code sub-block 21-j (j = 1, 2,... Jm). Here, the area 100 corresponding to the original first encoded information block is divided into code sub-blocks 21-j to be areas 100B-j (j = 1, 2,..., Jm).
C2 encoding is performed independently for each code sub-block 21-j partitioned as described above. For example, when Kr = 16, Nr = 18, and m = 8, mc = 1.
In addition, when converting to a serial super FEC signal after C2 encoding, interleaving of Kr stages is performed instead of Nr stages. As a result, the bit rate of the super FEC signal is {(Nr ÷ Kr) × (Nc ÷ Kc)} times the bit rate of the client signal, which is the same as in the first embodiment.
According to the present embodiment, the check bit of the C2 code can be arranged at the end of the C2 code in the transmission order, in other words, the reception order, and the scheme for parallel processing of encoding / decoding of the C2 code can be simplified. It is possible to suppress the occurrence of delay time in encoding.
Another embodiment of the error correction encoding method according to the present invention is shown in FIG. Here, FIG. 8 shows a data encoding area as a frame diagram.
This embodiment is the same as the previous (Embodiment 4), except that a more general method including (Embodiment 4) is adopted. This point will be described below.
In (Embodiment 4), the code sub-block 10-i (i = 1, 2, under the condition that “Nc is an integer multiple of m and (Nr × m) is an integer multiple of Kr”). ... Kr) is increased by (Nr ÷ Kr) times to create an empty area of {(Nr−Kr) × m ÷ Kr} columns for every m columns, and check bits for C2 code Area 120C-j (j = 1, 2,..., Jm) was used.
On the other hand, in the present embodiment, the bit rate of each of the code sub-blocks 10-i (i = 1, 2,... Kr) is increased by {1+ (ξ ÷ m)} times, and is arbitrarily set for every m columns. Ξ number of empty areas were created and used as C2 code check bit areas 120C-j (j = 1, 2,..., Jm). The result is a total of (Nc + jm × ξ) columns.
Then, the code sub-block 21-j (j = 1, 2,..., Jm) is divided into (m + ξ) columns, that is, divided into {Kr × (m + ξ)} bytes. Here, the area 100 corresponding to the original first encoded information block is divided into code sub-blocks 21-j to be areas 100B-j (j = 1, 2,..., Jm).
C2 encoding is performed independently for each code sub-block 21-j partitioned as described above.
Also, when converting to a serial super FEC signal after C2 encoding, Kr stage interleaving is performed. As a result, the bit rate of the super FEC signal is {{1+ (ξ ÷ m)} × (Nc ÷ Kc)} times the bit rate of the client signal.
According to the present embodiment, the check bit of the C2 code can be arranged in an arbitrary amount at the end of the C2 code in the transmission order, and the scheme for parallel processing of encoding / decoding of the C2 code can be simplified. This makes it possible to more flexibly configure a code that can suppress the occurrence of delay time.
The transmission order shown in FIGS. 1 to 8 indicates the order of transmission on the client signal and the order of transmission on the super FEC signal. The transmission order as the parallel signal is the “2nd direction of the transmission order” shown in each figure, that is, each row is simultaneously transmitted and processed. In addition, when performing C1 encoding / decoding, processing may be performed in a further parallel manner, for example, (Kr × 4 stages) or (Kr × 16 stages). Alternatively, at the time of C2 encoding / decoding, each column may be processed at the same time by transmitting in the “first direction of transmission order” shown in each figure.
In addition to 110C as an overhead area, a predetermined area in 120B, which is a check bit area for C2 code, is used as a second overhead area, and a part or all of information for OAM & P of a framing pattern and transmission network is inserted here. May be.
Another embodiment of the encoding method when the client signal already has the frame structure of FIG. 1 will be described.
When a client signal is received and converted into a super FEC signal, the bit rate is not increased by (Nc ÷ Kc) times for creating a check bit area for C1 code, but the client signal is reframed and C1 encoded. , A single wrapper that transitions to the C2 encoding process, ie, bit rate increase for C2 code, C2 encoding and overhead insertion. Here, the reframing of the client signal is to detect the framing pattern of the client signal and arrange it as shown in FIG. 1, terminate the information in the overhead area 110C of the client signal, and reinsert new information as necessary. It is.
Furthermore, when the client signal is already encoded with the same code as the C1 code, the existing C1 code may be C1 decoded once and then newly C1 encoded (method 1). The C1 code may be ignored and a new C1 encoding may be performed (method 2), or the existing C1 code may be once C1 decoded and left as it is (method 3), and then each C2 encoding process is performed. You may migrate.
Of course, a double wrapper may be used in which the bit rate is increased and C1 encoding is performed, and then the process proceeds to the C2 encoding process, without regard to the frame format of the client signal in the same manner as in the above embodiment. (Method 4).
Furthermore, the overhead area 110C may be processed transparently without being used as an overhead area, and a predetermined area in 120B, which is a check bit area for C2 code, may be used as the second overhead area.
Conversely, when a super FEC signal is received and converted into a client signal, when (method 1) to (method 3) are used on the encoding side, after C1 decoding, after C1 decoding once for C1 code New C1 encoding may be performed again (method 1B), new C1 encoding may be performed again without performing C1 decoding (method 2B), or the C1 decoding may be performed as is (method 3B). Each bit rate may be output as a client signal without reducing the bit rate by (Kc ÷ Nc). Alternatively, when (Method 4) is used on the encoding side, the bit rate may be reduced and output as a client signal after C2 decoding and C1 decoding using the same method as in the above embodiment (Method 4B) . Here, for example, when (Method 1) is performed on the encoding side, any of (Method 1B) to (Method 3B) may be performed on the decoding side.
Also, on the encoding side, the operation to be performed among these (Method 1) to (Method 4) may be selected based on the setting from the external control system.
Furthermore, the selection of which operation to perform among (Method 1B) to (Method 4B) on the decoding side may be performed based on the setting from the external control system, or may be performed automatically. When performing automatically, for example, an arbitrary predetermined area of the overhead for OAM & P in the first column is defined as an FSI byte, and a predetermined code value corresponding to a decoding operation instruction is inserted into the FSI byte on the encoding side To do. On the decoding side, the code value of the FSI byte is detected, and one of the above (Method 1B) to (Method 4B) corresponding to the code value is selected and operated. Even in this case, on the encoding side, the code value corresponding to which operation instruction is inserted into the FSI byte may be selected based on the setting from the external control system.
According to the present embodiment, it is possible to configure a higher gain code as a super FEC signal while ensuring the interconnectivity when the client signal is already C1 encoded.
In any of the above-described embodiments, it is possible to reverse the order of C1 encoding and C2 encoding on the encoding side, and reverse the order of C1 decoding and C2 decoding on the decoding side. In this case, the encoding side first increases the bit rate by (Nr ÷ Kr) times, and encodes jmb code sub-blocks 20-j (j = 1, 2,..., Jmb) with a C2 code. After that, the bit rate is increased (Nc ÷ Kc) times, and Nr code sub-blocks 10-i (i = 1, 2,..., Nr) are encoded with the C1 code. Here, jmb is <Kc ÷ m>. On the decoding side, the reverse process is performed.
In any of the above-described embodiments, the two bit rate increases of (Nc ÷ Kc) times, (Nr ÷ Kr) times or {1+ (ξ ÷ m)} times may be performed first. Good. In this case, the bit rate of the serial data before receiving the client signal and developing in parallel, or {(Nc ÷ Kc) × (Nr ÷ Kr)} times each bit rate after developing in parallel, or It increases {(Nc ÷ Kc) × {1+ (ξ ÷ m)}} times, and the first encoded information block is rearranged at a predetermined position.
In the embodiment described above, after the C2 decoding, the C2 code check bit area 120B or 120C is left as it is, and the C2 code check bit area 120B or 120C is ignored and the C1 decoding is performed, and then the C2 decoding is performed again. You may go. Further, after this, C1 decoding may be performed again, and thereafter, C2 decoding and C1 decoding may be repeated alternately. Finally, the bit rate may be reduced to {(Kr ÷ Nr) × (Kc ÷ Nc)} times to be the original client signal. Alternatively, when each of C2 decoding and C1 decoding is finally finished, the bit rate is reduced to (Kr / Nr) and (Kc / Nc) times in each process so that the original client signal is obtained. Good.
According to the present embodiment, it is possible to obtain a higher gain than when decoding one by one by sequentially repeating C2 decoding and C1 decoding.
FIG. 9A shows an example of a C1 code applicable to a combination of Kc and Nc, and FIG. 9B shows an example of a C2 code applicable to a combination of Kr, Nr, m, and ξ.
FIG. 9B shows the C2 code for the set of (Kr, Nr, m) in (Embodiment 1) to (Embodiment 4), and (Kr, m, ξ) in (Embodiment 5) according to the following relationship. The C2 code for the set) is also shown. That is, a certain set (Kr, Nr, m) = (a, b, c) and a set (Kr, m, ξ) = (c, a, b) have the same code length and check bit area. Therefore, the same code can be applied. Also, the set of (Kr, Nr, m) = (a, b, c) and the set of (Kr, Nr, m) = (a × β, b × β, c ÷ β) have the same code length. Since it has a check bit area, the same code can be applied. Furthermore, (a × c) and (d × f) for the set of (Kr, Nr, m) = (a, b, c) and the set of (Kr, Nr, m) = (d, e, f) ) Are equal, and (b × c) and (e × f) are equal, the same code can be applied. Similarly, for the set of (Kr, m, ξ) = (a, b, c) and the set of (Kr, m, ξ) = (d, e, f), (a × b) and (d × The same code can be applied when e) is equal and (a × c) and (d × f) are equal. Here, a, b, and c are arbitrary integers, and β is an arbitrary integer that divides c.
As a C2 code, a short code length, for example, 127 to 144 bits / byte, and a simple code of a decoding algorithm, for example, 1 to 3 error correcting RS / BCH codes, instead of a low correction capability, encoding and decoding Can reduce the delay time and simplify each scheme.
In general, in an optical fiber, the transmission distance is inversely proportional to the square of the bit rate due to dispersion and nonlinear effects, and even if the bit rate is increased and the check bit area is increased, the error correction code Since the increase in the coding gain is gradually slowed down, the most efficient code can be obtained by encoding with the bit rate increase limited to 110% to 130%. Therefore, the ratio of the bit rate of each of the super FEC signal and the client signal is set to 110% to 130% as a percentage, and C1 coding and C2 coding are performed so that this redundant bit, that is, the check bit fits in the empty area. And
According to the present embodiment, C1 encoding and C2 encoding can be performed flexibly, and the most efficient code that maximizes the transmittable distance can be configured.
Another embodiment of the error correction code according to the present invention is shown in FIG.
The present embodiment is different in that after performing the C2 encoding described in (Embodiment 1) to (Embodiment 5), the sequence of each column is exchanged and then Nr stages of interleaving are performed. This difference is described below.
After performing C2 encoding, jm pieces of the first column 20-j-1 of each sub-block of the code sub-block 20-j (j = 1, 2,... Jm) are arranged in order from the sub-block having the smallest j. Make a line. Next, the second column 20-j-2 of each sub-block of the code sub-block 20-j is similarly arranged in order from the sub-block having the smallest j to make a total of (2 × jm) columns. Thereafter, the same operation is performed on the third column 20-j-3 to the m-th column 20-j-m of each of the sub-blocks of the code sub-block 20-j, for a total (m × jm). Make a line. The signals rearranged in this way are used as already-encoded blocks, and Nr stages of interleaving is performed from row to row for each ε byte in the same manner as in (Embodiment 1) to (Embodiment 5) to obtain a super FEC signal. On the decoding side, reverse arrangement (reverse arrangement) is performed to restore the arrangement of the original code sub-blocks 20-j (j = 1, 2,... Jm), and then C2 decoding and C1 decoding are performed.
Further, if Nr is replaced with Kr and m is replaced with mc, the present embodiment can be applied to (Embodiment 4), and if Nr is replaced with Kr and m is replaced with (m + ξ). , (Example 5).
Of course, this embodiment can also be applied to (Embodiment 6) and (Embodiment 7).
Furthermore, if Nr is replaced with Kr and jm is replaced with an appropriate value of 2 or more, and C1 encoding is performed and rearrangement is performed in the same manner as described above, it can be applied to single encoding using C1 code. Is possible.
Further, the super FEC signal rearranged in this way is regarded as a client signal, and the bit rate is further increased to perform C1 encoding and C2 encoding as in the above-described embodiment, or such rearrangement is performed. It may be repeated a plurality of times to obtain a super FEC signal. In this case, on the decoding side, the operation opposite to that on the encoding side, that is, reverse arrangement → C2 decoding → C1 decoding → bit rate reduction is repeated the same number of times as the encoding side.
In the above description, after performing C2 encoding, the order of each column is exchanged. However, immediately after C1 encoding is performed, the order of each column can be exchanged to perform C2 encoding. In this case, as in the case of single encoding using the C1 code, if Nr is replaced with Kr, jm is replaced with an appropriate value of 2 or more, C1 encoding is performed, and then rearrangement is performed as described above. Good.
According to this embodiment, even if a long burst error occurs in the super FEC signal, they are distributed to different C1 code areas and different C2 code areas due to reverse arrangement on the decoding side, so that the super FEC signal has a large error correction. Can have ability.
The present embodiment is different in that after performing the C2 encoding described in the first to third embodiments, each row is moved back and forth little by little and then Nr stages of interleaving are performed. This difference is described below.
After performing the C2 encoding, first, for each row corresponding to the total Nr rows of the code sub-block 10-i (i = 1, 2,..., Kr) and the (Nr-Kr) rows for the C2 code. The second line (130-1-2 in the figure) is shifted backward by jd bytes at the temporal position. Here, jd is an arbitrary integer value of 1 or more. Next, the third row (130-1-3 in the figure) is shifted backward by (2 × jd) bytes at the temporal position. Thereafter, the same operation is performed on the third to Nr-th rows, and the Nr-th row (130-1-Nr in the figure) is shifted backward (Nr × jd) bytes at the temporal position. Will be placed. As a result, at least (Nr × jd) columns after rearrangement, the data of the adjacent already-encoded blocks before rearrangement coexists.
Here, in FIG. 11, the first column of the already-encoded block 130 is excluded from the rearrangement so that the framing pattern can be easily detected on the decoding side. It is.
The signals rearranged in this way are subjected to Nr-stage interleaving from row to row for every ε bytes in the same manner as in (Embodiment 1) to (Embodiment 3) to obtain super FEC signals. On the decoding side, reverse arrangement (reverse arrangement) is performed to restore the original row arrangement, and then C2 decoding and C1 decoding are performed.
Further, if Nr is replaced with Kr, the present embodiment can be applied to (Embodiment 4) and (Embodiment 5).
Of course, the present embodiment can also be applied to (Embodiment 6) to (Embodiment 7).
Furthermore, if Nr is replaced with Kr and rearrangement is performed in the same manner as described above after performing C1 encoding, the present invention can also be applied to single encoding using C1 code.
In the above description, the position of each row is shifted after C2 encoding. However, the position of each row can be shifted immediately after C1 encoding. In this case, similar to the single encoding with the C1 code, the above-described Nr may be replaced with Kr, and after C1 encoding is performed, rearrangement may be performed in the same manner as described above.
The framing pattern area of the super FEC signal and the overhead area for OAM & P of the transmission network, for example, the first column in FIGS. 1 to 7 may be excluded from the target of C1 encoding or C2 encoding. When excluding the first column, the first column is virtually encoded as (00) hex on the encoding side, and the first column is virtually decoded as (00) hex on the decoding side. Moreover, you may control whether it removes from an external control system. In this case, when “excluded” / “not excluded” is set, the value in the first column is used as it is or is virtually set to (00) hex to perform encoding / decoding. You can do it. Further, in each of C1 decoding and C2 decoding on the decoding side, whether to exclude the first column from the C1 code area or the C2 code area may be performed based on the setting from the external control system, It may be done automatically. When performing automatically, for example, an arbitrary predetermined area of OAM & P overhead in the first column is defined as an FSIB byte, and a predetermined value corresponding to whether or not the first column is an encoding target on the encoding side Insert the code value into the FSIB byte. On the decoding side, the code value of the FSIB byte is detected, and an operation corresponding to the code value is performed. The FSIB byte may be the FSI byte described above. Further, the above setting and automatic operation may be performed independently for the framing pattern area and the OAM & P overhead area of the transmission network. Furthermore, the overhead area for OAM & P may be divided into a plurality of areas, and the above setting and automatic operation may be performed independently for each area. Further, the above setting and automatic operation may be performed independently for the C1 code and the C2 code.
According to the present embodiment, for each of the C1 code and the C2 code, it is possible to independently set whether to encode the framing pattern area and the overhead area for OAM & P, so that the OAM & P of the transmission network is more flexible. In addition, the transmission network OAM & P can be automatically performed without the intervention of an operator.
Similar to the automatic operation method of the eleventh embodiment, the decoding operation may be automatically turned ON or OFF. For example, an arbitrary predetermined area of the overhead for OAM & P in the first column is defined as an FSIC byte, and a predetermined code value corresponding to whether or not encoding is performed on the encoding side is inserted into the FSIC byte. On the decoding side, the code value of the FSIC byte is detected, and if it is encoded, the decoding operation is turned ON, and if it is not encoded, the decoding operation is turned OFF. Here, the FSIC byte may be the FSI byte or the FSIB byte described above. In addition, when changing from a non-encoded state to an encoded state, the FSIC bytes belonging to the block that is temporally earlier than the first encoded block and the second encoded block that actually start encoding. A predetermined code value corresponding to encoding may be inserted. Further, the decoding side may perform an operation corresponding to the code value only when the same value is detected M times in succession when detecting the code value of the FSIC byte. Further, the code value insertion or automatic decoding as described above may be performed independently for the C1 code and the C2 code as described above.
According to this embodiment, each of the C1 code and the C2 code can be automatically decoded independently, making the OAM & P of the transmission network more flexible and easy, and further, making the OAM & P of the transmission network without operator intervention. It can be done automatically.
In all the embodiments described above, the client signal may be any of the following. Other than these, an arbitrary binary digital signal having a constant bit rate in time, or a signal obtained by converting it into an optical signal may be used.
SONET standard OC-1, OC-3, OC-12, OC-48, OC-192, or OC-768 signal.
SDH standard STM-1, STM-4, STM-16, STM-64, STM-256 signal.
Any one of 1000Base-SX, 1000Base-LX, and 1000Base-CX signals (commonly called Geiger signals) defined in IEEE standard 802.3z.
A signal obtained by converting the bit rate to 125% using an 8B10B code defined by IEEE standard 802.3z.
A signal obtained by terminating the 8G10B code of the Gigaisa signal or the signal having the 8B10B code and converting the bit rate to 80%.
A signal obtained by compressing an arbitrary data signal using a predetermined data compression tool.
An output signal of the multiplex transmission apparatus disclosed in Japanese Patent Application No. 8-138011.
ITU-T Recommendation G. A signal specified in 975.
ITU-T Recommendation G. 872 (established in 1999), an OCh (Optical Channel) layer signal.
For any one of the above signals, a signal obtained by time-division multiplexing an arbitrary plurality of signals, for example, two signals having a bit rate of 4.97664 Gbit / s obtained by time-division multiplexing two OC-48 signals A signal having a bit rate of 19.90656 Gbit / s obtained by time-division multiplexing of STM-64 signals of four, and a signal having a bit rate of 5.0 Gbit / s obtained by time-division multiplexing four 1.25 Gbit / s Gigaiser signals.
A signal obtained by increasing the bit rate by multiplying one of the above signals by (255/238) or (256/240).
A signal encoded by a convolutional code with a coding rate of 1/2 by increasing the bit rate of any of the above signals by a factor of two.
A super FEC signal encoded as described in the above embodiment using any one of the above signals as a client signal.
A signal obtained by time-division multiplexing a plurality of super FEC signals.
As an example, when an OC-48 signal having a bit rate of 2.48832 Gbit / s or an STM-16 signal is used as a client signal, the parallel expansion stage number Kr is set to 4 and all bits in each byte are expanded in parallel. For example, a total of 32 bits are developed in parallel, and the bit rate per bit is 77.76 Mbit / s (Mega Bit Per Second). Alternatively, if Kr is 8, the bit rate per bit is 38.88 Mbit / s, and if Kr is 16, the bit rate per bit is 19.44 Mbit / s.
Similarly, when an OC-192 signal or a STM-64 signal having a bit rate of 9.95328 Gbit / s is used as a client signal, the number of stages Kr of parallel expansion is set to 16, and all bits in each byte are expanded in parallel. For example, a total of 128 bits are developed in parallel, and the bit rate per bit is 77.76 Mbit / s. Alternatively, if Kr is 32, the bit rate per bit is 38.88 Mbit / s, and if Kr is 64, the bit rate per bit is 19.44 Mbit / s.
In addition, when the number of stages Kr of parallel expansion is fixed to 16, that is, a total of 128 bits, and the bit rate per 1 bit is an OC-192 signal or an STM-64 signal, each bit of the parallel signal is 1 bit. Per bit rate is 77.76 Mbit / s, when the client signal is OC-48 signal or STM-16 signal, 19.44 Mbit / s, and when the client signal is OC-12 signal or STM-4 signal, 4 It may be changed according to the bit rate of the client signal, such as .86 Mbit / s.
Also, when the above-mentioned Giga-sa signal or 8B10B encoded signal is used as the client signal, the 8B10B code may be terminated while the bit rate may be maintained as it is. Here, the end of the 8B10B code means restoring the data before the 8B10B encoding. By doing so, the data amount is reduced to 80%, and the remaining 20% capacity, that is, 25% capacity with respect to the data amount after the end of the 8B10B code, can be freely used. For example, in the case of a 1.25 Gbit / s gigaisa signal, a 0.25 Gbit / s capacity is an empty area that can be used freely. At the end of the 8B10B code, the idle pattern before the end of the 8B10B code may be removed, and an appropriate delimiter pattern may be inserted so that the delimiter between the packets can be recognized. May be converted into an appropriate pattern for identification so that the capacity becomes Y% (Y <100) after the end of the 8B10B code. Alternatively, each 8-bit data after the termination of the 8B10B code can be converted into 9 bits by a predetermined method to reduce the bit rate to 90%. For example, one bit of “zero” value is added to the beginning of each 8 bits of the packet to make a total of 9 bits, while the value of the first 1 bit is “1” as a delimiter pattern between packets, A total of 9 bits having an arbitrary predetermined pattern of 8 bits may be used. In any case, when an empty area having a capacity of 6% or more with respect to the data capacity after the end of the 8B10B code can be freely used, this is set as the C1 code check bit position, or further, the C2 code check bit position. As described above, the C1 encoding or the C2 encoding of the embodiment described above can be performed. Then, when the client signal is reproduced on the decoding side, the 8B10B code may be reproduced. This makes it possible to construct a super FEC signal without increasing the bit rate.
In addition, while compressing the data amount of an arbitrary data signal using a predetermined data compression tool, a signal whose bit rate is kept as it is is 6% or more of the compressed data capacity. Similarly, a super FEC signal can be configured without increasing the bit rate when the capacity is an empty area that can be used freely.
In addition, the above-described encoding / decoding can be performed by using each wavelength signal of a wavelength division multiplexed signal in one optical fiber as a client signal, or a signal obtained by time division multiplexing of each wavelength signal. The above-described encoding / decoding can also be performed using as a client signal. It is also possible to perform wavelength division multiplex transmission through one optical fiber core by setting the wavelengths of the plurality of super FEC signals to different wavelengths.
In any of the above-described embodiments, a pseudo product code or a concatenated code in which the C1 code is an outer code and the C2 code is an inner code is used. However, encoding may be performed using only a single code. . For example, as in the above embodiment, the client signal is converted into the frame structure of FIG. 1 and C1 encoding is performed, and the C1-encoded data is subjected to Kr stage interleaving for each ε byte as it is and the super FEC is performed. Signal. On the decoding side, reverse processing is performed to restore the client signal.
As an example in this case, δ relating to parallelization of a client signal having a bit rate of (ζ) Gbit / s is set to 1, Kr is set to 16, and all bits in each byte are parallelized to be parallelized to a total of 128. , Kc is set to 238, Nc is set to 255, C1 code is set to 8 error correction Reed-Solomon codes (255, 239), and the encoding processing speed for each of a total of 128 parallel signals is set as the bit rate. Before the increase, {(ζ ÷ 128) × 1000} Mbit / s, and after the bit rate increase, {(ζ ÷ 128) × (255 ÷ 238) × 1000} Mbit / s. The decoding processing speed is also the same. For example, when the client signal is an OC-192 signal or a STM-64 signal having a bit rate of 9.95328 Gbit / s, the processing speed of each parallel signal is set to 77.76 Mbit / s before the bit rate is increased. And about 83.4 Mbit / s after the bit rate is increased. For example, for a client signal having a bit rate of 12.5 Gbit / s, the processing speed of each parallel signal is set to 97.65625 Mbit / s and about 104.7 Mbit / s. For example, for a client signal having a bit rate of 19.90656 Gbit / s, the processing speed of each parallel signal is set to 155.52 Mbit / s and about 166.7 Mbit / s. For example, for a client signal having a bit rate of 39.83112 Gbit / s, the processing speed of each parallel signal is 311.04 Mbit / s and about 333.3 Mbit / s. In any case, since the parallel signals are encoded and decoded independently for each of the 16 parallel signals in which 8 parallel signals are one system, the encoding and decoding are performed regardless of the bit rate of the client signal. The scale of the device for decoding is constant at 16 sets. In this way, regardless of the bit rate of the client signal, a constant parallel processing scheme is used, so that even if the bit rate of the client signal increases, the number of parallelizations is constant, so It is possible to suppress an increase in the scale of a device that performs decoding.
Furthermore, the client signal is parallelized in the same manner as described above for an OC-192 signal or STM-64 signal or a signal having a bit rate of 12.5 Gbit / s. For a signal having, the number of parallelizations may be an integer multiple (ω times). For example, for a signal with a bit rate of 9.95328 Gbit / s, Kr is set to 16 as described above, and all bits in each byte are parallelized to a total of 128, whereas (ω × 9.95328) For a bit rate signal of Gbit / s, Kr is set to (ω × 16), all bits in each byte are parallelized to a total of (ω × 128), and so on. It is. In this way, the processing speed of each parallel signal can be fixed at 77.76 Mbit / s before the bit rate is increased, and about 83.4 Mbit / s after the bit rate is increased. It is possible to suppress an increase in the scale of an apparatus that is suitable for the operating speed of the LSI that performs encoding and decoding.
An example of the super FEC signal transmitter according to the embodiment of the present invention is shown in FIG. Here, FIG. 12 is a block diagram of the super FEC signal transmitter 2.
The super FEC signal transmitter 2 receives the client signal 200 and outputs it as a super FEC signal 250. The clock extraction unit 210 reproduces and outputs a clock signal 210C having the same bit rate as the received client signal 200. The clock dividing unit 211 converts the clock signal 210C from the clock extracting unit 210 into the initial processing rate in the super FEC signal transmitter 2, for example, the frequency is one times Kr of the original clock signal, or (8 × Kr) The frequency is divided by a factor of 1 and output as the clock signal 211C. Further, a clock signal having a predetermined frequency is received from the outside as necessary, and this signal is synchronized with the clock signal extracted by the clock extraction unit 210 using a PLL (Phase Locked Loop) circuit or the like as the clock signal 211C. Also good.
The serial / parallel converter 212 outputs the received client signal 200 in parallel at Kr stages every δ bytes so that the period and phase of one bit are equal to that of the clock signal 211C.
The first clock rate converter 213 increases the frequency of the clock signal 211C from the clock divider 211 by (Nc ÷ Kc) times and outputs it as the first clock signal 213C.
The first frame conversion unit 214 converts each of the parallel data signals from the serial / parallel conversion unit 212 to the bit rate (Nc ÷ Kc) using the timing of the first clock signal 213C from the first clock rate conversion unit 213. ), And the original parallel data signal is arranged and output in an area 100 in the frame format as shown in FIGS.
The overhead processor unit 215 generates overhead information, framing patterns, etc. for OAM & P of the transmission network to be inserted and transmitted on the super-FEC signal, and includes a first overhead insertion unit 216, a second overhead insertion unit 217, and a third overhead. A part or all of the above-mentioned various pieces of information to be processed by each of them is output to the insertion unit 218 215a, 215b, 215c.
The first overhead insertion unit 216 stores various information 215a from the overhead processor unit 215 in a predetermined position in the data signal from the first frame conversion unit 214, for example, the areas of FIGS. It is inserted at a predetermined position in 110C and output.
The first encode processor unit 217 performs the C1 encoding described in the above embodiment on the output data signal from the first overhead insertion unit 216. C1 encoding is performed independently and simultaneously on each of the Kr code sub-blocks 10-i (i = 1, 2,..., Kr). The processor unit 217 may be configured with Kr C1 encoding modules 217-MDJ-i (i = 1, 2,..., Kr) that handle each of the Kr code sub-blocks 10-i.
The second overhead insertion unit 218 sends the various information 215b from the overhead processor unit 215 to a predetermined position in the data signal from the first encode processor unit, for example, the area 110C in FIGS. Is inserted into a predetermined position and output.
The second clock rate conversion unit 219 increases the frequency of the first clock signal 213C from the first clock rate conversion unit 213 by (Nr ÷ Kr) times or {1+ (ξ ÷ m)} times to increase the second clock. Output as signal 219C.
The second frame conversion unit 220 converts each of the parallel data signals from the second overhead insertion unit 218 to the bit rate using the timing of the second clock signal 219C from the second clock rate conversion unit 219 ( Nr ÷ Kr) times or {1+ (ξ ÷ m)} times, and the original parallel data signal is arranged and output in an area 100B in the frame format as shown in FIG. This case is referred to as (Case 1). Alternatively, a parallel area of (Nr-Kr) stages is created in parallel with the data signal from the second overhead insertion unit 218, and the original parallel data signal is stored in the area 100 in the frame format as shown in FIGS. Place and output. This case is referred to as (Case 2).
The second encoding processor unit 221 performs the C2 encoding described in the above embodiment on the output data signal from the second frame conversion unit 220. At this time, the code subblock 20-j (j = 1, 2,..., Jm) is encoded with the code subblock 20-1 after the C2 encoding or during the encoding. -2 C2 encoding is started, and C2 encoding is performed in time series. Each one of the code sub-blocks 20-j is processed in a state where the code sub-blocks 20-j are developed in parallel in Kr stages or Nr stages. For example, in calculating check bits, Kr bytes or Nr bytes of parallel input may be subjected to a digit increase according to the parallel position of each byte or bit, and then division by a generator polynomial may be performed. . By using a short code length code with a small m as the C2 code, the delay time associated with the coding can be reduced.
The third overhead insertion unit 222 sends various information 215c from the overhead processor unit 215 to a predetermined position in the data signal from the second encode processor unit 221, for example, the areas shown in FIGS. It is inserted at a predetermined position in 110C and output.
The clock frequency multiplier 223 increases the frequency of the second clock signal 219C from the second clock rate converter 219 by an integer multiple, for example, when the second frame converter 220 is (Case 1), Kr times (8 In the case 2, the frequency is multiplied by Nr times or (8 × Nr) times and output as the third clock signal 223C. Further, if necessary, a third clock signal 223C may be received by receiving a clock signal having a predetermined frequency from the outside.
The scrambler 224 randomizes and outputs so that the same bit value is not transmitted continuously. For example, the serial data signal from the next parallel / serial converter 225 is processed in parallel so as to obtain the same result as when the primitive polynomial of a predetermined order is scrambled as a generator polynomial. The scrambler 224 may be positioned behind the parallel / serial conversion unit 225 to be a 1-bit serial processing scrambler.
The parallel / serial conversion unit 225 interleaves the Kr-stage or Nr-stage parallel data signal from the scrambler 224 every ε bytes so that the period and phase of one bit are equal to that of the third clock signal 223C. The bit sequence is serialized in time series and output as a super FEC signal 250.
Of the above-described units, the units from the first overhead insertion unit 216 to the second overhead insertion unit 218 operate at the timing of the clock signal 213C. Each unit from the second encode processor unit 221 to the scrambler 224 operates at the timing of the clock signal 219C.
In the above, the super FEC signal transmitter 2 may be controlled from the external control system 9. For example, with respect to the overhead processor unit 215, a part or all of overhead information for OAM & P to be generated, a framing pattern, a first overhead insertion unit 216, a second overhead insertion unit 218, and a third overhead insertion unit 222 Which OAM & P overhead information or framing pattern is inserted may be controlled by the control signal 9a. Alternatively, with respect to the first encoding processor unit 217 and the second encoding processor unit 221, which operation is performed among (Method 1) to (Method 4) described in (Example 6), and (Example 11). As described above, the control signal 9b determines whether or not the framing pattern area and the OAM & P overhead area are to be encoded, and whether or not C1 encoding or C2 encoding is performed as described in (Example 12). , 9c. Further, when it is detected that the client signal 200 is in an abnormal state such as signal disconnection, or when the operation of the super FEC signal transmitter 2 is in an abnormal state, an alarm 299 is notified to the external control system 9. Also good.
According to the present embodiment, error correction having a sufficient gain of 6 dB or more with respect to a bit error rate of 10 minus 12 is obtained by performing C1 coding on the client signal and then C2 coding to convert it into a super-FEC signal. A super-FEC transmitter that realizes encoding into codes can be easily configured.
FIG. 13 shows another example of the super FEC signal transmitter according to the embodiment of the present invention.
The configuration and operation of the super FEC signal transmitter 2 of the present embodiment are the same as those of the embodiment of FIG. 12, but the first frame conversion unit 214 and the second frame conversion unit 220 are arranged together to perform the first clock rate conversion. The difference is that the unit 213 and the second clock rate conversion unit 219 are arranged together, and a selector 227 and a selector 228 are added. Furthermore, a parallel data signal 204 having a data format equivalent to the data format of the output signal of the second frame conversion unit 220, and a clock signal 205 synchronized with the parallel data signal 204 and having the same frequency as the second clock signal 219C. And the phase pulse signal 206 indicating the phase of the parallel data signal 204 is received from the outside.
The operations of the first clock rate conversion unit 213, the first frame conversion unit 214, and the second clock rate conversion unit 219 are the same as those in the thirteenth embodiment.
The second frame conversion unit 220 performs the same processing as in (Example 13) for each of the parallel data signals from the first frame conversion unit 214. Further, in the case (Case 1), the first frame conversion unit 214 can be removed. In this case, each of the parallel data signals from the serial / parallel conversion unit 212 is converted from the second clock rate conversion unit 219. Using the timing of the 2-clock signal 219C, the bit rate is directly converted to {(Nr ÷ Kr) × (Nc ÷ Kc)} times or {{1+ (ξ ÷ m)} × (Nc ÷ Kc)}} times. Then, the original parallel data signal may be arranged and output in the area 100B in the frame format as shown in FIGS.
The selector 227 receives the parallel data signal from the second frame conversion unit 220 and the parallel data signal 204 received from the outside, and selects and outputs either of them.
The selector 228 receives the second clock signal 219C from the second clock rate conversion unit 219 and the clock signal 205 received from the outside, selects either of them, and outputs it as the clock signal 228C.
Note that the selector 227 and the selector 228 select signals of the same system. That is, when the selector 227 selects the parallel data signal from the second frame conversion unit 220, the selector 228 selects the second clock signal 219C. Conversely, when the selector 227 selects the parallel data signal 204, the selector 228 selects the clock signal 205. The external control system 9 may control which one is selected by the control signal 9f.
When the parallel data signal 204 is selected by the selector 227, the frame position of the parallel data signal 204 is recognized based on the phase pulse signal 206 received from the outside in each process after the first overhead insertion unit 216.
The operations of the other units are different only in that the first overhead insertion unit 216 processes the data signal from the selector 227 and the second encode processor unit 221 processes the data signal from the second overhead insertion unit 218. The others are the same as in (Example 13).
According to the present embodiment, the client signal is increased to a predetermined bit rate in advance, and then C1 coding and C2 coding are performed to convert the client signal into a super-FEC signal, whereby an error correction code having a sufficient gain can be obtained. A super-FEC transmitter that realizes encoding can be configured more easily.
Also, when performing single encoding using the C1 code, the second clock rate conversion unit 219, the second frame conversion unit 220, the second encode processor unit 221, and the third overhead insertion unit 222 are removed in FIGS. Then, this can be simply connected through.
Alternatively, in FIG. 12 and FIG. 13, any one, two, or three of the first overhead insertion part 216, the second overhead insertion part 218, and the third overhead insertion part 222 are removed and simply through connection is made. It is good. When removing all three, a predetermined framing pattern is inserted in either the first encode processor unit 217 or the second encode processor unit 221.
An example of a super FEC signal receiver which is an embodiment of the present invention is shown in FIG. Here, FIG. 14 is a block diagram of the super FEC signal receiver 3.
The super FEC signal receiver 3 receives the super FEC signal 350 and outputs it as a client signal 300. The clock extraction unit 330 reproduces and outputs a clock signal 330C having the same bit rate as the super FEC signal 350.
The clock divider 331 converts the clock signal 330C extracted by the clock extractor 330 into a first stage processing rate in the super FEC signal receiver 3, for example, a frequency that is 1 / Pr of the original clock signal, or (8 × Pr ) Frequency-divided by a factor of 1 and output as a clock signal 331C. Further, if necessary, a clock signal having a predetermined frequency may be received from the outside, and this signal may be synchronized with the clock signal extracted by the clock extraction unit 330 using a PLL circuit or the like and output as the clock signal 331C. .
Here, in the super FEC signal transmitter 2 of FIG. 12 that is the transmission source of the super FEC signal 350, when the second frame conversion unit 220 performs frame conversion by the method of (Case 1), Pr = Kr, When frame conversion is performed by the method of (Case 2), Pr = Nr. The former case is referred to as (transmission source case 1), and the latter case is referred to as (transmission source case 2).
The first clock rate converter 332 reduces the frequency of the clock signal 331C from the clock divider 331 to (Pr / Nr) times or {m / (m + ξ)} times and outputs it as the first clock signal 332C. . The second clock rate conversion unit 333 reduces the frequency of the first clock signal 332C from the first clock rate conversion unit 332 to (Kc ÷ Nc) times and outputs the second clock signal 333C. The clock multiplication unit 334 multiplies the second clock signal 333C from the second clock rate conversion unit 333 by an integral multiple, for example, Kr times or (8 × Kr) times, to generate a third clock signal 334C. Output as. Further, if necessary, a third clock signal 334C may be received by receiving a clock signal having a predetermined frequency from the outside.
The serial / parallel converter 311 outputs the super FEC signal 350 in parallel to the Pr stage every ε bytes so that the cycle and phase of one bit are equal to that of the clock signal 331C. The frame synchronization unit 312 detects a predetermined framing pattern with respect to the parallel data signal from the serial / parallel conversion unit 311 and rearranges the signals in an appropriate order. 7 frame format signals are output.
The descrambler 313 performs an operation opposite to that performed by the scrambler 224 in the super FEC signal transmitter 2 of FIG. Restore the data before scrambled.
The first overhead extraction unit 314 extracts information on a predetermined position in the data signal from the descrambler 313, for example, information on a predetermined position in the area 110C in FIGS. 2, 4, 6, and 7. Thereafter, the data signal is output to the first decode processor unit 315 as it is, and the extracted information 340 a is output to the overhead processor unit 340.
The first decode processor unit 315 performs C2 decoding of the above-described embodiment on the output data signal from the first overhead extraction unit 314 and outputs the decoded data signal to the second overhead extraction unit 316. The C2 decoding result 341a (the number of corrected bits, the estimated number of uncorrectable bits when an uncorrectable error exists, the number of erroneously corrected bits when erroneously corrected) is output to the FEC performance monitor unit 341. Here, C2 decoding is performed after C2 decoding of code sub-block 20-1 for each of jm code sub-blocks 20-j (j = 1, 2,..., Jm), similarly to C2 encoding. Or, C2 decoding of the code sub-block 20-2 is started during decoding. Each one of the code sub-blocks 20-j is processed in a state where the code sub-blocks 20-j are developed in parallel in Kr stages or Nr stages. For example, in the calculation of the syndrome, the syndrome calculation may be performed after performing a digit increase according to the parallel position of each byte or bit for the parallel input of Kr bytes or Nr bytes. The calculation of each polynomial coefficient of Error Locator Polynomial (abbreviated as ELP) indicating an error position and Error Evaluator Polynominal (abbreviated as EVP) indirectly indicating an error value from the result of syndrome calculation is a method using Euclidian division. Is widely known and does not depend on the parallel state for Kr bytes or Nr bytes. The error position calculation is performed by substituting the element of the Galois field corresponding to the symbol position in the RS code and the bit position in the BCH code into the ELP polynomial, and depending on whether or not it becomes “zero”, there is an error in the corresponding symbol position or bit position. Determine if it exists. In the error value calculation, a Galois field element corresponding to the symbol position or bit position is substituted into an EVP polynomial or ELP differential polynomial, and an error value is calculated when an error exists at the corresponding symbol position or bit position.
This error position calculation and error value calculation are performed simultaneously with independent calculation corresponding to the parallel position of each byte or bit for Kr bytes or Nr bytes. At that time, it is only necessary to calculate with a digit increase corresponding to each parallel position.
While performing the above error position calculation and error value calculation for the corresponding bit, it is possible to perform sequential decoding so that the error of the corresponding bit is corrected and output, or error position calculation and error for all bit positions After performing the value calculation, the error at the position where the error exists may be corrected and output. In the latter case, since it is possible to detect the irrationality of the ELP polynomial and the EVP polynomial that occur when an error exceeding the error correction capability occurs, erroneous correction can be suppressed.
In ELP and EVP polynomial coefficient calculation and error value calculation, Galois field division, that is, multiplication by an inverse element is required. As a method for deriving the inverse element of the Galois field, a method for finding and finding an element whose multiplication result with the element of the predetermined Galois field is “1” (denoted as a search method), and an element of the predetermined Galois field element A method for obtaining an inverse element by creating an adjoint matrix and calculating an inverse matrix, or an upper triangulation matrix or a lower triangulation matrix (denoted as a matrix formation technique), and an inverse element corresponding to all elements of a Galois field in advance. Any of the techniques (denoted as a memory technique) for obtaining an inverse element by storing information in a memory and reading information in a memory corresponding to a predetermined Galois field element may be used.
Furthermore, the above calculation inside the processor unit 315 may be accelerated, that is, performed using a local clock obtained by appropriately multiplying the first clock signal 331C.
Alternatively, the error position and the error value corresponding to the syndrome pattern may be stored in the memory in advance, and the information in the memory corresponding to the calculation result of the syndrome may be read out to perform direct decoding.
If a code with low correction capability is used as the C2 code, the polynomial coefficient of ELP or EVP can be obtained in advance as a mathematical expression using the syndrome as a variable, and the calculation can be simplified.
When the C2 code is a BCH code, EVP polynomial coefficient calculation and error value calculation are not required. Further, by using a short code length code with a small m as the C2 code, the delay time associated with decoding can be reduced.
The second overhead extracting unit 316 is information on a predetermined position in the data signal from the first decode processor unit 315, for example, a predetermined position in the area 110C in FIGS. 2, 4, 6, and 7. , The data signal is output as it is to the first frame conversion unit 317, and the extracted information 340b is output to the overhead processor unit 340.
In the case of (transmission source case 1), the first frame conversion unit 317 converts each of the parallel data signals from the second overhead extraction unit 316 into the first clock signal 332C from the first clock rate conversion unit 332. The bit rate is converted to (Kr ÷ Nr) times or {m ÷ (m + ξ)} times using the timing, and the original parallel data signal is an area in the frame format as shown in FIGS. 100 and output. Alternatively, in the case of (transmission source case 2), the parallel signal corresponding to the (Nr-Kr) stage, which is the check bit area for the C2 code of the data signal from the second overhead extracting unit 316, is deleted or terminated and The original parallel data signal is arranged in the area 100 in the frame format as shown in FIG. 1, FIG. 3, and FIG.
The second decode processor unit 318 performs C1 decoding of the output data signal from the first frame conversion unit 317, outputs the decoded data signal to the third overhead extraction unit 319, and The C1 decoding result 341b (the number of corrected bits, the estimated number of uncorrectable bits when an uncorrectable error exists, the number of erroneously corrected bits when an error is corrected) is output to the FEC performance monitor unit 341. Here, C1 decoding is performed independently and simultaneously on each of the Kr code sub-blocks 10-i (i = 1, 2,..., Kr), similarly to the C1 encoding. The processor unit 318 may be composed of Kr C1 decode modules 318-MDJ-i (i = 1, 2,..., Kr) that handle each of the Kr code sub-blocks 10-i. Each of the C1 decode modules 318-MDJ-i calculates the syndrome from the input data, the ELP and EVP polynomial coefficients from the syndrome, the error position calculation from the ELP and EVP polynomial coefficients, and the error value Perform the calculation.
Here, the calculation of the ELP and EVP polynomial coefficients from the syndrome may be shared by each of the C1 decode modules 318-MDJ-i. In this case, for example, the ELP and EVP polynomial coefficients are calculated for the code sub-block 10-1, and then the ELP and EVP polynomial coefficients are calculated for the code sub-block 10-2. The processing may be performed in order for each sub-block 10-i, and the code sub-block to be shared is divided into 10-1 to 10-is (is <Kr) and 10- (is + 1) to 10-Kr. Or may be divided into four. As with the first decode processor unit 315, the ELP and EVP polynomial coefficient calculation and error value calculation require division of the Galois field, that is, multiplication by the inverse element. The inverse element can be derived using either the method or the memory implementation method. Of course, the above calculation in the processor unit 318 may be accelerated, that is, performed using a local clock obtained by appropriately multiplying the second clock signal 332C. Alternatively, the error position and the error value corresponding to the syndrome pattern may be stored in the memory in advance, and the information in the memory corresponding to the calculation result of the syndrome may be read out to perform direct decoding. When the C1 code is a BCH code, EVP polynomial coefficient calculation and error value calculation are not required.
The third overhead extraction unit 319 extracts information on a predetermined position in the data signal from the second decode processor unit 318, for example, information on a predetermined position in the area 110C in FIGS. Thereafter, the data signal is output to the second frame conversion unit 320 as it is, and the extracted information 340 c is output to the overhead processor unit 340.
The second frame conversion unit 320 converts each of the parallel data signals from the third overhead extraction unit 319 using the timing of the second clock signal 333C from the second clock rate conversion unit 333, and converts the bit rate thereof to ( Kc ÷ Nc) times to restore the parallel data equivalent to the input to the first frame conversion unit 214 in the super FEC signal transmitter 2 of FIG.
The parallel / serial conversion unit 321 interleaves the Kr-stage parallel data signal from the second frame conversion unit 320 every δ bytes so that the period and phase of one bit are equal to that of the third clock signal 334C. Then, the bit sequence is serialized and output as the client signal 300.
As described above, the output client signal 300 is obtained by restoring the client signal 200 received by the super FEC signal transmitter 2 of FIG.
The overhead processor unit 340 edits the overhead information 340a, 340b, and 340c for OAM & P of the transmission network received from the first overhead extraction unit 314, the second overhead extraction unit 316, and the third overhead extraction unit 319, or from this information It is judged whether or not the super FEC signal 350 is normal, or it is judged whether or not the performance quality such as the bit error rate and the number of bit errors is deteriorated, or the operation state and the maintenance state of the transmission network. And the PM information 397 is notified to the external control system 9.
The FEC performance monitor unit 341 totals each decoding result from the C1 decoding result 341b and the C2 decoding result 341a received from the first decoding processor unit 315 and the second decoding processor unit 318, and each decoding result and the total result Is notified to the external control system 9 as the FEC-PM result 398.
Among the above units, the units from the frame synchronization unit 312 to the second overhead extraction unit 316 operate at the timing of the clock signal 331C. The second decode processor unit 318 and the third overhead extraction unit 319 operate at the timing of the clock signal 332C.
In the above, the super FEC signal receiver 3 may be controlled from the external control system 9. For example, with respect to the first decode processor unit 315 and the second decode processor unit 318, which operation is to be performed among (Method 1B) to (Method 4B) described in (Example 6), and (Example 11). Control signals 9d and 9e control whether the framing pattern area and the overhead area for OAM & P are to be decoded as described above, and whether C1 decoding or C2 decoding is performed as described in (Example 12). May be. Further, when it is detected that the super FEC signal 350 is in an abnormal state such as a signal disconnection, or when the operation of the super FEC signal receiver 3 is in an abnormal state, an alarm 399 is notified to the external control system 9. May be.
According to the present embodiment, the super FEC signal is C2 decoded and then C1 decoded and converted into a client signal, thereby generating a sufficient gain of 6 dB or more for a bit error rate of 10 minus 12 power. An FEC receiver can be easily configured.
FIG. 15 shows another example of the super FEC signal receiver according to the embodiment of the present invention.
The configuration and operation of the super FEC signal receiver 3 of the present embodiment are the same as those of the embodiment of FIG. 14, except that the first frame conversion unit 317 and the second frame conversion unit 320 are arranged last, The difference is that the clock rate conversion unit 332 and the second clock rate conversion unit 333 are arranged together. Furthermore, one parallel data signal 304 branched from the parallel data signal from the third overhead extraction unit 319 and a clock signal synchronized with the parallel data signal 304, that is, one clock branched from the clock signal from the clock frequency dividing unit 331. The difference is that the signal 305 and the phase pulse signal 306 indicating the phase of the parallel data signal 304 are output to the outside of the super FEC signal receiver 3.
The operations of the first clock rate conversion unit 332, the first frame conversion unit 317, and the second clock rate conversion unit 333 are the same as those in the fifteenth embodiment.
The second frame conversion unit 320 performs the same processing as that in the fifteenth embodiment for each of the parallel data signals from the first frame conversion unit 317. Further, in the case of (transmission source case 1), the first frame conversion unit 317 can be removed. In this case, each of the parallel data signals from the third overhead extraction unit 319 is transferred from the second clock rate conversion unit 333. The bit rate is directly converted to {(Kr ÷ Nr) × (Kc ÷ Nc)} or {{m ÷ (m + ξ)} × (Kc ÷ Nc)} times using the timing of the second clock signal 333C. The parallel data equivalent to that input to the first frame conversion unit 214 in the super FEC signal transmitter 2 of FIG.
The operations of the other units are the same as in Example 15 except that the second decode processor unit 318 only processes the data signal from the second overhead extraction unit 316.
According to the present embodiment, a super-FEC receiver that generates sufficient gain can be more easily configured by converting the super-FEC signal to a predetermined bit rate after performing C2 decoding and C1 decoding and then converting it to a client signal. can do.
When performing single decoding using the C1 code, the first clock rate conversion unit 332, the first frame conversion unit 317, the first decode processor unit 315, and the first overhead extraction unit 314 are removed in FIGS. You can simply connect through here.
14 and 15, each of the first overhead extraction unit 314, the second overhead extraction unit 316, and the third overhead extraction unit 319 is the transmission source of the super FEC signal 350 in the super FEC signal transmitter 2 of FIG. The first overhead insertion part 216, the second overhead insertion part 218, and the third overhead insertion part 222 may be removed corresponding to the first overhead insertion part 216, the second overhead insertion part 218, and the third overhead insertion part 222.
Furthermore, in FIGS. 12 to 15, instead of the client signals 200 and 300, parallel client signals 201 and 301 that are appropriately parallelized may be used.
In addition to the parallel client signals 201 and 301, the clock signals 202 and 302 synchronized with these and having a bit rate equal to these bit rates may be received or transmitted.
In addition, of the total data capacity of the client signal 200 and the client signal 201, a capacity corresponding to at least {(Nr × Nc−Kr × Kc) ÷ (Nr × Nc)} times is a free area that can be freely used. In such a case, the first frame conversion unit 214 and the second frame conversion unit 220 do not need to convert the bit rate, and it is only necessary to appropriately rearrange the data positions in the client signal 200 and the client signal 201. .
Further, the data formats of the client signal 200 and the parallelized client signal 201 are already as shown in FIGS. 1 to 7, and the areas 110B, 110C, 120B, and 120C are all free areas that can be freely used. In such a case, the first frame conversion unit 214 and the second frame conversion unit 220 are not necessary. In this case, a device for transmitting the client signal 200 and a super FEC signal transmitter are further inserted by inserting or separating and collating a predetermined diagnostic pattern at an arbitrary position in the areas 110B, 110C, 120B and 120C. 2, or between the device to which the client signal 300 is transmitted and the super FEC signal receiver 3, diagnosis relating to signal transmission / reception can be performed. Further, periodic phase pulse signals 203 and 303 indicating predetermined positions in the data formats of the client signals 200 and 300 and the parallel client signals 201 and 301 may be received or transmitted.
Similarly, the super FEC signals 250 and 350 may be parallel super FEC signals 251 and 351 appropriately parallelized. In addition to the parallel super FEC signals 251 and 351, the clock signals 252 and 352, the super FEC signals 250 and 350, and the parallel super FEC signals 251 and 351 having the same bit rate as these bit rates are synchronized with these. Periodic phase pulse signals 253 and 353 indicating predetermined positions in the data format may be received or transmitted.
The first encode processor unit 217 and the second encode processor unit 221, and the first decode processor unit 315 and the second decode processor unit 318 are LSIs or FPGAs in which the encoding / decoding logic is fixedly mounted. Alternatively, the microprocessor may be implemented by operating each logic as software. Moreover, both may be mounted on the same LSI / FPGA, or may be the same CPU that operates both of the software and operates in a time-sharing manner.
FIG. 16 shows an example of a transmission apparatus using a super FEC signal transmitter and a super FEC signal receiver according to an embodiment of the present invention.
The transmission apparatus 1 of the present invention includes the super FEC signal transmitter 2 of FIG. 13 and the super FEC signal receiver 3 of FIG.
The super FEC signal transmitter 2 converts the client signal 200 received from the transmission line 50 on the client side into a super FEC signal 250 and outputs it to the electrical / optical converter 260.
The electrical / optical converter 260 converts the super FEC signal 250 from the super FEC signal transmitter 2 into an optical signal 259 having a waveform equivalent to the super FEC signal 250 and having a predetermined wavelength and optical power density. Output to path 60.
The optical / electrical converter 360 converts the optical signal 359 received from the optical fiber transmission line 61 on the superline side into an electrical signal having a waveform equivalent to this and outputs it as a super FEC signal 350.
The super FEC signal receiver 3 converts the received super FEC signal 350 into the client signal 300 and outputs it to the transmission path 51 on the client side, and also the parallel data signal 304, clock signal 305, and phase pulse signal after C1 decoding and C2 decoding. 306 is output to the super FEC signal transmitter 2.
The above is referred to as operation mode A.
Operating the super FEC signal transmitter 2 as described below, which is different from the above, is referred to as an operation mode B.
That is, the parallel data signal 204, the clock signal 205, and the phase pulse signal 206 (connected to 304, 305, and 306, respectively) received by the super FEC signal transmitter 2 from the super FEC signal receiver 3 are converted back to the super FEC signal 250 again. The operation state output to the electrical / optical conversion unit 260 is referred to as an operation mode B.
Which of the two types of operation modes is selected may be selected by fixed wiring on hardware, or may be controlled by the external control system 9 via the monitoring control line 19.
When the transmission apparatus is operated in the operation mode A, the conversion between the client signal and the super FEC signal can be performed bidirectionally. When the transmission apparatus is operated in the operation mode B, the super FEC signal is relayed. It becomes possible to do.
Further, the client signal 300 from the super FEC signal receiver 3 may be branched and looped back to the super FEC signal transmitter 2, and in this case, the operation mode A is performed.
Alternatively, FIG. 12 may be used instead of FIG. 13 as the super FEC signal transmitter 2, and FIG. 14 instead of FIG. 15 may be used as the super FEC signal receiver 3. In this case, only the operation mode A is performed.
According to the present embodiment, it is possible to configure a transmission apparatus that converts a client signal into a super FEC signal and transmits it, or relays and transmits a super FEC signal.
FIG. 17 shows another example of a transmission apparatus using a super FEC signal transmitter and a super FEC signal receiver according to an embodiment of the present invention.
The configuration of the transmission apparatus 1B of the present invention is different from the configuration of the seventeenth embodiment in that a first cross-connect switch unit 4A, a first multiplexing unit 5A, and a first separation unit 6A are further added.
The first cross-connect switch unit 4A includes a plurality of input sub-client signals 240-i (i = 1, 2,..., U) and a plurality of intermediate client signals 243-j (j = 1, 2, .., V) are independently cross-connected / branched to obtain a plurality of sub-client signals 241-i (i = 1, 2,..., U) and a plurality of intermediate client signals 242-j (j = 1, 2, ...) are output.
The first multiplexing unit 5A time-division multiplexes the intermediate client signal 242-j (j = 1, 2,..., V) from the first cross-connect switch unit 4A to produce the client signal 200, and outputs it to the super FEC signal transmitter 2 To do.
The first separation unit 6A separates the client signal 300 from the super FEC signal receiver 3 into intermediate client signals 243-j (j = 1, 2,..., V), and outputs them to the first cross-connect switch unit 4A.
Other parts are the same as those in the seventeenth embodiment. Further, FIG. 12 may be used instead of FIG. 13 as the super FEC signal transmitter 2, and FIG. 14 may be used as the super FEC signal receiver 3 instead of FIG.
According to the present embodiment, it is possible to configure a transmission apparatus that converts a plurality of sub-client signals into a super FEC signal and transmits them, or relays and transmits a super FEC signal.
FIG. 18 shows another example of a transmission apparatus using a super FEC signal transmitter and a super FEC signal receiver according to an embodiment of the present invention.
The configuration of the transmission apparatus 1C of the present invention is different in that a plurality of configurations of the seventeenth and eighteenth embodiments are used and a second cross-connect switch unit 4B, a second multiplexing unit 5B, and a second separation unit 6B are added. .
Each of the r client / super FEC conversion units 7-k (k = 1, 2,..., r) is the same as the configuration of the transmission apparatus 1A in FIG. 16 or the transmission apparatus 1B in FIG. To work. Specifically, the client signal 200-k is converted into a super FEC signal optical signal 255-k, while the super FEC signal optical signal 355-k is converted into a client signal 300-k.
The second cross-connect switch unit 4B includes r optical signals 255-a (a = 1, 2) input from r client / super FEC converters 7-k (k = 1, 2,..., R). ,..., R) and wi optical signals 356-b (b = 1, 2,..., Wi) input from the second separation unit 6B are independently cross-connected / branched to r pieces. An optical signal 355-c (c = 1, 2,..., R) and wo optical signals 256-d (d = 1, 2,..., Wo) are output.
The second multiplexing unit 5B wavelength-division-multiplexes the wo optical signals 256-d (d = 1, 2,..., Wo) from the second cross-connect switch unit 4B, and outputs them as wavelength multiplexed signals 257 on the superline side. Output to the transmission line 60.
The second separation unit 6B separates the wavelength-multiplexed signal 357 received from the transmission line 61 on the superline side for each wavelength to obtain wi optical signals 356-b (b = 1, 2,..., Wi). Output to the second cross-connect switch unit 4B.
Here, the client / super FEC conversion unit 7-k (k = 1, 2, etc.) so that the wavelengths of light of the wo optical signals 256-d (d = 1, 2,..., Wo) are different from each other. .., R) and the second cross-connect switch unit 4B are adjusted. That is, the wavelength is adjusted by either assigning the wavelength in the former or converting the wavelength in the latter, or both.
Further, when the second cross-connect switch unit 4B has an electrical signal process inside and the interface is an optical signal process, the input r optical signals 255-a (a = 1, 2,..., R) and wi The optical signals 356-b (b = 1, 2,..., Wi) are converted into electrical signals, subjected to cross connect / branch processing, and then converted into optical signals to r optical signals 355-c (c). = 1, 2,..., R) and wo optical signals 256-d (d = 1, 2,..., Wo).
In this case, an electrical signal may be further provided between the second cross-connect switch unit 4B and the client / super FEC conversion unit 7-k (k = 1, 2,..., R). In this case, each of the electrical / optical conversion unit 260 and the optical / electrical conversion unit 360 of the client / super FEC conversion unit 7-k is not necessary, and the super line side of the second cross-connect switch unit 4B, that is, wo opticals. Electric-to-optical conversion and optical-to-electrical conversion are performed between the signal 256-d (d = 1, 2,..., Wo) and the wi optical signals 356-b (b = 1, 2,..., Wi). Just do it.
In the nineteenth embodiment, the second multiplexing unit 5B and the second separation unit 6B may be time division multiplexing / time division separation instead of wavelength division multiplexing / wavelength division separation. In this case, r optical signals 255-a (a = 1, 2,..., R), wi optical signals 356-b (b = 1, 2,..., Wi), and r optical signals 355. “C” (c = 1, 2,..., R) and “wo” optical signals 256-d (d = 1, 2,..., Wo) may be read as “electrical signals”. Of course, in this case, the client / super FEC conversion unit 7-k (k = 1, 2,..., R) and the second cross-connect switch unit 4B do not need a conversion function between an electric signal and an optical signal. In the second multiplexing unit 5B, the wo electrical signals 256-d (d = 1, 2,..., Wo) are time-division multiplexed and then converted into an optical signal 257 and output. In the second demultiplexing unit 6B, The optical signal 357 is converted into an electrical signal, and then time-division-separated and output as wi electrical signals 356-b (b = 1, 2,..., Wi).
An example of a network configuration using the transmission apparatus according to the embodiment of the present invention is shown in FIG.
The super FEC domain 400 is a network for transmitting and receiving a super FEC signal through an optical fiber or an electrical transmission line therein, and processes network elements 500 to 509 similar to the transmission apparatus of the previous embodiment. An optical fiber or electrical transmission line connecting them, and an operating system 9 that controls the network elements 500 to 509 and executes OAM & P of the domain 400 are configured.
The super FEC domain 410 is a network that transmits and receives a super FEC signal via an optical fiber or an electrical transmission line therein, and each of the network elements 510 and 511 is a network element 509 in the super FEC domain 400. , 508. For example, the network elements 508 and 511 are connected by an optical fiber or an electrical transmission line, and the signal from the network element 508 to 511 and the signal from the opposite network element 511 to 508 are both super FEC signals. Here, the network elements 510 and 511 are the same as the transmission apparatus of the previous embodiment.
G. The 975 FEC domains 420 to 422 have an ITU-T Recommendation G. A network that transmits and receives signals defined by 975 (referred to as G.975 signals) and processes the signals, and connects each of the network elements 520 to 522 to the network elements 500, 502, and 504 in the super FEC domain 400. . For example, the network elements 500 and 520 are connected by an optical fiber or an electrical transmission line, and the signal from the network element 500 to 520 and the signal from the network element 520 to 500 in the opposite direction are both G. The signal is defined as 975.
The non-FEC domains 430 to 434 are networks in which an arbitrary digital signal is transmitted and received via a transmission line. It is not a 975 signal nor a super FEC signal. Then, each of the network elements 530 to 534 is connected to the network elements 501, 503, and 505 to 507 in the super FEC domain 400. For example, the network elements 503 and 531 are connected by an optical fiber or an electrical transmission line, and the signals from the network elements 503 to 531 and the signals from the reverse network elements 531 to 503 are both the same as in the non-FEC domain. This is a format signal (this is called a non-FEC signal). Further, the network element 530 in the non-FEC domain 430 is connected to the G. In the case of providing an interface that handles signals defined in 975, both the signals from the network elements 501 to 530 and the signals from the network elements 530 to 501 in the reverse direction are connected to the G. It can also be a 975 signal.
With the network configured as described above, the network elements 500 to 509 in the super FEC domain 400 are connected to the external super FEC domain 410, G. 975 FEC domains 420 to 422 and non-FEC domains 430 to 434 are used as client signals, conversion to super FEC signals described in the previous embodiment, multiplexing / demultiplexing / relay / cross-connect switching Or notifying the operating system 9 of various information for OAM & P of the network.
The operating system 9 executes OAM & P of the super FEC domain 400 based on various information for OAM & P notified from each of the network elements 500 to 509 and setting information from the operator. Further, the operating system 9 controls the network elements 500 to 509 to execute appropriate operations according to the type of client signal, and performs multiplexing / demultiplexing / relaying between super FEC signals and between client signals. Cross-connect switching is controlled, and in some cases, protection switching / restoration switching between super FEC signals is controlled.
In FIG. 19, as a cable for connecting the network elements, a cable that transmits a super FEC signal is indicated by three lines. One that transmits a 975 signal is indicated by a single solid line, and one that transmits a non-FEC signal is indicated by a single broken line.
Further, the number of connection cables between the network elements is not necessarily one, and may be two or any number corresponding to the signal transmission direction.
Further, the network topology in the super FEC domain 400 does not have to be a ring type as shown in FIG. 19, for example, a linear type, a mesh type, a star type, or a composite of these, Also good.
According to the present embodiment, it is possible to easily configure a wide area network in which various existing networks are regarded as local area networks, various client signals from these networks are converted into super FEC signals and transmitted over a long distance, and It becomes possible to configure a network having good mutual consistency with an existing network that handles 975 signals.
When the error correction code encoding method of the present invention is used, an error correction code having a sufficient gain of 6 dB or more with respect to a bit error rate of 10 to the -12th power is obtained when the multiplicity in time division multiplexing is increased. Suitable for maintaining the transmission distance, maximizing the transmission distance when optical signals of different bit rates are mixed in wavelength division multiplexing, and increasing the relay interval under conditions that do not change the time division multiplicity. Error correction code and an error correction code having a higher gain can be easily constructed while ensuring the interoperability with an existing transmission network in which eight error correction Reed-Solomon codes are introduced. Furthermore, if the super FEC signal transmitter and receiver of the present invention are used, a transmission apparatus and a network having the above characteristics can be easily realized.
FIG. 1 is a frame diagram showing an error correction coding method according to an embodiment of the present invention.
FIG. 2 is a frame diagram illustrating an error correction coding method according to an embodiment of the present invention.
FIG. 3 is a frame diagram showing an error correction coding method according to another embodiment of the present invention.
FIG. 4 is a frame diagram showing an error correction coding method according to another embodiment of the present invention.
FIG. 5 is a frame diagram showing an error correction coding method according to another embodiment of the present invention.
FIG. 6 is a frame diagram showing an error correction encoding method according to another embodiment of the present invention.
FIG. 7 is a frame diagram showing an error correction coding method according to another embodiment of the present invention.
FIG. 8 is a diagram illustrating a code type of the error correction encoding method according to the embodiment of the present invention.
FIG. 9A is a diagram showing code types of the error correction encoding method according to the embodiment of the present invention.
FIG. 9B is a diagram illustrating a code type of the error correction encoding method according to the embodiment of this invention.
FIG. 10 is a frame diagram showing an error correction coding method according to another embodiment of the present invention.
FIG. 11 is a frame diagram showing an error correction coding method according to another embodiment of the present invention.
FIG. 12 is a block diagram showing a configuration of an encoding apparatus according to an embodiment of the present invention.
FIG. 13 is a block diagram showing a configuration of an encoding apparatus according to another embodiment of the present invention.
FIG. 14 is a block diagram showing a configuration of a decoding apparatus according to an embodiment of the present invention.
FIG. 15 is a block diagram showing a configuration of a decoding apparatus according to another embodiment of the present invention.
FIG. 16 is a block diagram illustrating a configuration of a transmission apparatus according to an embodiment of the present invention.
FIG. 17 is a block diagram showing a configuration of a transmission apparatus according to another embodiment of the present invention.
FIG. 18 is a block diagram showing a configuration of a transmission apparatus according to another embodiment of the present invention.
FIG. 19 is a configuration diagram of a network according to an embodiment of the present invention.
FIG. 20 is a diagram illustrating a time-series relationship between a parallel signal, a client signal, and a super FEC signal.
FIG. 21 is a diagram illustrating a time-series relationship between a parallel signal, a client signal, and a super FEC signal.
DESCRIPTION OF SYMBOLS 1, 1B, 1C ... Transmission apparatus, 2 ... Super FEC signal transmitter, 3 ... Super FEC signal receiver, 4A, 4B ... Cross-connect switch part, 5A, 5B ... Multiplexing part, 6A, 6B ... Separation part, 7-1 7-r: client / super FEC conversion unit, 9: external control system, 9a, 9b, 9c, 9d, 9e, 9f ... control signal,
10-1 to 10-Kr, 20-1 to 20-jm, 21-1 to 21-jm, code sub-block, 20-i-1 to 20-ij: j-th column of code sub-block 20-i , 19 ... monitoring control lines, 50-1 to 50-u, 51-1 to 51-u ... transmission line on the client side, 60, 61 ... optical fiber transmission line on the superline side,
100, 110B, 110C, 120A, 120B ... Area, 100B-1 to 100B-jm, 120C-1 to 120C-jm ... Area, 130, 130-1, 130-2 ... Pre-coded block, 130-1-1 ˜130-1-Nr... Nr rows from the first row of the pre-coded block 130-1, 130-2-1 to 130-2-Nr... Nr rows from the first row of the pre-coded block 130-2, 200 , 200-1 to 200-r ... client signal, 201 ... parallelized client signal, 202 ... clock signal, 203 ... phase pulse signal, 204 ... parallel data signal,
205 ... Clock signal, 206 ... Phase pulse signal, 210 ... Clock extraction unit, 210C ... Clock signal, 211 ... Clock division unit, 211C ... Clock signal, 212 ... Serial / parallel conversion unit, 213 ... First clock rate conversion unit 213C ... first clock signal, 214 ... first frame conversion unit, 215 ... overhead processor unit, 215a, 215b, 215c ... various information, 216 ... first overhead insertion unit, 217 ... first encode processor unit, 217-MDJ -1 to 217-MDJ-Kr ... C1 encoding module,
218 ... second overhead insertion unit, 219 ... second clock rate conversion unit, 219C ... second clock signal, 220 ... second frame conversion unit 220, 221 ... second encoding processor unit, 222 ... third overhead insertion unit, 223 ... clock doubler, 223C ... third clock signal, 224 ... scrambler,
225... Parallel / serial converter, 227, 228... Selector, 228C... Clock signal, 240-1 to 240-u, 241-1 to 241-u... Sub client signal, 242-1 to 242-v, 243-1 243 -v ... intermediate client signal, 250 ... super FEC signal, 251 ... parallelized super FEC signal, 252 ... clock signal, 253 ... phase pulse signal, 255-1 to 255-r, 256-1 to 256-wo ... Optical signal, 257 ... wavelength multiplexed signal,
259 ... Optical signal, 260 ... Electric / optical converter, 299 ... Alarm, 300, 300-1 to 300-r ... Client signal, 301 ... Parallelized client signal,
302 ... Clock signal, 303 ... Phase pulse signal, 304 ... Parallel data signal, 305 ... Clock signal, 306 ... Phase pulse signal, 311 ... Serial / parallel converter, 312 ... Frame synchronizer, 313 ... Descrambler,
314: first overhead extracting unit, 315: first decoding processor unit, 316: second overhead extracting unit, 317: first frame converting unit, 318: second decoding processor unit, 318-MDJ-1 to 318-MDJ- Kr ... C1 decoding module, 319 ... third overhead extraction unit, 320 ... second frame conversion unit, 321 ... parallel / serial conversion unit, 330 ... clock extraction unit, 330C ... clock signal, 331 ... clock division unit, 331C ... Clock signal, 332... First clock rate conversion unit, 332C... First clock signal, 333... Second clock rate conversion unit, 333C... Second clock signal, 334... Clock multiplication unit, 334C. ... Overhead processor section, 340a, 340b, 340 ... overhead information, 341 ... FEC performance monitor, 341a ... C2 decoding result, 341b ... C1 decoding result, 350 ... super FEC signal, 351 ... parallelized super FEC signal, 352 ... clock signal, 353 ... phase pulse signal, 355 1 to 355-r, 356-1 to 356-wi ... optical signal, 357 ... wavelength multiplexed signal,
359 ... optical signal, 360 ... optical / electrical converter, 397 ... PM information, 398 ... FEC-PM result, 399 ... alarm, 400, 410 ... super FEC domain, 420 to 422 ... G. 975 FEC domain, 430-434 ... non-FEC domain, 500-511, 520-522, 530-534 ... network elements.
A method of constructing an error correction code for error correcting encoding a client signal having a constant bit rate, comprising:
Sequentially repeating the parallel Kr system for each consecutive δ bytes of the client signal, to obtain Kr parallel client signals;
Separating each of the Kr parallel client signals into Kc bytes to form a first encoded information block of (Kr × Kc) bytes;
Increase the bit rate of each of the first encoded information blocks of (Kr × Kc) bytes by (Nc ÷ Kc) times, increase the length from Kc bytes to Nc bytes, and Kr C1 code sub A block step;
The information of the first encoded information block is arranged from the second column to the (Kc + 1) th column in the time series of each of the Kr C1 code sub-blocks, and the first column and the (Kc + 2) th column ) The empty area created by increasing the bit rate from the column to the Nc column, the first column of the empty areas as the overhead area, and the area from the (Kc + 2) column to the Nc column A check bit area for C1 code,
Each of the Kr C1 code sub-blocks is independently encoded with a C1 code, and the check bits are arranged in the C1 code check bit area to form Kr C1 encoded sub-blocks. Steps,
The number of parallel stages of the Kr C1 encoding sub-blocks is increased from Kr to Nr to create an empty area of ((Nr−Kr) × Nc) bytes,
Making the empty area a check bit area for C2 code;
A total (Nr × Nc) byte area composed of the Kr C1 encoding sub-blocks and the C2 code check bit area is divided into m columns, and each divided (Nr × m) byte is Re-segmenting into a total of jm C2 code sub-blocks as one C2 code sub-block;
Each of the jm C2 code sub-blocks is independently encoded with a C2 code, and the check bits are arranged in the C2 code check bit area to form jm C2 encoded sub-blocks. Steps,
Inserting a framing pattern indicating a start position of the C1 encoding subblock and the C2 encoding subblock and a plurality of pieces of information for OAM & P of the network in the overhead area;
Considering the jm C2 encoded sub-blocks as one C2 encoded block;
Applying a predetermined scramble to the C2 encoded block to form a scrambled C2 encoded block;
From each of the Nr parallel signals of the scrambled C2 coding block, interleaving is performed every successive ε bytes, and the bit rate is ((Nc ÷ Kc) × (Nr ÷ Kr)) times the client signal. And a step of making one serial super FEC signal,
A method of constructing an error correction code wherein δ, Kr, Kc, Nc, Nr, jm, and ε are set to predetermined integer values, and m is an integer of 2 or more.
Sequentially repeating paralleling the client signal into Kr systems for each successive δ bytes, to obtain a Kr parallelized client signal;
Increase the bit rate of each of the first encoded information blocks of (Kr × Kc) bytes by (Nc ÷ Kc) times and increase the length from Kc bytes to Nc bytes to increase Kr C1 code sub A step to block,
The information of the first encoded information block is arranged from the second column to the (Kc + 1) th column in the time series of each of the Kr C1 code sub-blocks, and the first column and the (Kc + 2) th column ) The empty area created by increasing the bit rate from the column to the Nc column, the first column as the overhead area, and the area from the second column to the (Kc + 1) column among the empty areas A check bit area for C1 code,
Increasing the bit rate of each of the Kr C1 encoding sub-blocks to (Nr ÷ Kr) times to make the number of parallel stages an area of total (Nr × Nc) bytes of Kr;
For each m columns of the (Nr × Nc) byte area, mc columns of empty areas created by increasing the bit rate are arranged, and the information of the C1 coding subblock is included in the m columns. And vacating the mc columns of empty areas as C2 code check bit areas;
Dividing the (Nr × Nc) byte area into (m + mc) columns, and setting the delimited (m + mc) columns as one C2 code sub-block;
Re-segmenting the (Nr × Nc) byte area into jm C2 code sub-blocks;
In the overhead area, a framing pattern indicating a start position of the C1 encoding subblock and the C2 encoding subblock, and a plurality of information for network OAM & P are inserted,
From each of the Kr parallel signals of the scrambled C2 coding block, interleaving is performed every successive ε bytes, and the bit rate is ((Nc ÷ Kc) × (Nr ÷ Kr)) times the client signal. And a step of making one serial super FEC signal,
A method of constructing an error correction code wherein δ, Kr, Kc, Nc, jm, ε, and mc are set to predetermined integer values, and m is an integer of 2 or more.
A decoding method for error correction decoding a super FEC signal having a predetermined frame structure, a predetermined overhead area, and a predetermined error correction code,
Serially repeating paralleling the super FEC signal into Nr systems for each successive ε bytes to form Nr parallelized FEC signals;
Detecting a framing pattern inserted in the overhead area, adjusting a temporal alignment and a parallel alignment of the parallelized FEC signals, and reproducing an arrangement of scrambled C2 encoded blocks;
Performing a predetermined descrambling on the scrambled C2 encoded block to reproduce a C2 encoded block;
Extracting a plurality of pieces of information for OAM & P of a network inserted at a predetermined position in the overhead area and performing a predetermined process;
Reconstructing jm C2 encoded sub-blocks from the C2 encoded block, divided into m consecutive columns for each parallel signal;
Performing decoding with C2 code independently for each of the jm C2 encoded sub-blocks to obtain jm C2-decoded C2 code sub-blocks;
Reproducing an area of the total (Nr × Nc) bytes of the number of parallel stages Nr and the length of the column Nc from the jm C2 decoded C2 code sub-blocks, and Kr from the (Nr × Nc) byte area Reproducing C1 encoded sub-blocks;
Performing K1 code decoding independently for each of the Kr C1 encoded sub-blocks to obtain Kr C1-decoded C1 code sub-blocks;
Reduce the bit rate of each of the Kr C1 decoded C1 code sub-blocks by (Kc ÷ Nc) times, reduce the length from Nc bytes to Kc bytes, overhead area and check bit area for C1 code Regenerating the first encoded information block of (Kr × Kc) bytes leaving information from the second column to the (Kc + 1) th column in time series,
Interleaving is performed for each successive δ bytes from each of the first encoded information blocks, and one serial number whose bit rate is ((Kc ÷ Nc) × (Kr ÷ Nr)) times the super FEC signal. Recovering a valid client signal,
A decoding method in which each of the δ, Kr, Kc, Nc, Nr, jm, and ε is a predetermined value, the C2 code and the C1 code are predetermined codes, and the m is an integer of 2 or more.
Serially repeating paralleling the super FEC signal into Kr systems for each successive ε bytes to obtain Kr parallelized FEC signals;
Extracting a plurality of pieces of information for OAM & P of a network inserted at a predetermined position in an overhead area of the C2 coding block and performing a predetermined process;
Reconstructing jm C2 encoded sub-blocks from the C2 encoded block by separating each (m + mc) sequence for each parallel signal;
Reconstructing an area of the total number of parallel Kr (Nr × Nc) bytes from the jm C2 decoded C2 code sub-blocks;
Reduce the bit rate of the (Nr × Nc) byte area to (Kr ÷ Nr) times, remove the C2 code check bit area from the (Nr × Nc) byte area, and encode Kr C1 codes Steps to reproduce sub-blocks;
Reduce the bit rate of each of the Kr C1 decoded C1 code sub-blocks by (Kc ÷ Nc) times, reduce the length from Nc bytes to Kc bits, overhead area and check bit area for C1 code Regenerating the first encoded information block of (Kr × Kc) bytes leaving information from the second column to the (Kc + 1) th column in time series,
Interleaving is performed every successive δ bytes from each of the first encoded information blocks of (Kr × Kc) bytes, and the bit rate is ((Kc ÷ Nc) × (Kr ÷ Nr) of the super FEC signal. A step of restoring one serial client signal of a double,
Each of δ, Kr, Kc, Nc, jm, ε, mc, Kr is set to a predetermined value, the C2 code and C1 code are set to predetermined codes, and the m is an integer of 2 or more. A decoding method.
A method of constructing an error correction code according to claim 1,
The δ is set to 1, the Kr is set to 128, the Kc is set to 238, the (Nc ÷ Kc) is set to 15/14, the Nc is set to 255, and the ((Nr−Kr) × Nc) is set to 16. The Nr is 144, the jm is 255, the ε is 1, and the eight error correcting Reed-Solomon codes (255, 239) on the Galois field (256) as the C1 code, or the Galois field (2048) One of 11 error correction shortened BCH codes (2040, 1919) based on
One error correction shortened Reed-Solomon code (18, 16) on Galois field (256) as C2 code or two error correction shortened BCH code (144, 128) based on Galois field (256) Any one of them is used, and an error correction code construction method.
The decoding method according to claim 3, wherein
One error correction shortened Reed-Solomon code (18, 16) on Galois field (256) as C2 code or two error correction shortened BCH code (144, 128) based on Galois field (256) A decoding method characterized by using either one.
A method for constructing an error correction code according to claim 1, comprising:
The δ is set to 1, the Kr is set to 112, the Kc is set to 238, the (Nc ÷ Kc) is set to 15/14, the Nc is set to 255, and the ((Nr−Kr) × Nc) is set to 16. The Nr is set to 128, the jm is set to 255, the ε is set to 1, and the eight error correcting Reed-Solomon codes (255, 239) on the Galois field (256) as the C1 code or the Galois field (2048) One of 11 error correction shortened BCH codes (2040, 1919) based on
Either one error correction shortened Reed-Solomon code (16, 14) on the Galois field (256) as the C2 code, or two error correction BCH codes (127, 113) based on the Galois field (128) A method for constructing an error correction code, characterized in that
Either one error correction shortened Reed-Solomon code (16, 14) on the Galois field (256) as the C2 code, or two error correction BCH codes (127, 113) based on the Galois field (128) A decoding method characterized by using
A method of constructing an error correction code according to claim 2,
The δ is 1, the Kr is 128, the Kc is 238, the (Nc ÷ Kc) is 15/14, the Nc is 255, the jm is 19, the ε is 1, m is 112, mc is 8, and (Nr ÷ Kr) is 15/14,
Either 8 error correcting Reed-Solomon codes (255, 239) on Galois field (256) as C1 code, or 11 error correction shortened BCH codes (2040, 1919) based on Galois field (2048) Use
The C2 code is an 8 error correction shortened Reed-Solomon code (240, 224) on the Galois field (256) or an 11 error correction shortened BCH code (1920, 1799) based on the Galois field (2048). Any one of them is used, and an error correction code composition method.
The decoding method according to claim 4, wherein
The C2 code is an 8 error correction shortened Reed-Solomon code (240, 224) on the Galois field (256) or an 11 error correction shortened BCH code (1920, 1799) based on the Galois field (2048). A decoding method characterized by using either one.
A capacity that is {1- (Kr ÷ (Nc ÷ Kc) ÷ Nr)} times or more of the capacity of the client signal is an empty area that can be used freely.
The bit rate of the client signal or the super FEC signal is not converted, and part or all of the empty area is regarded as the check bit area for C1 code, the check bit area for C2 code, and the overhead area,
The data of the client signal or the super FEC signal is arranged at a predetermined position to be the C1 code subblock, the C2 code subblock, the C1 encoding subblock, or the C2 encoding subblock. A method of constructing a characteristic error correction code.
The data of the client signal or the super FEC signal is arranged at a predetermined position to be the C1 code subblock, the C2 code subblock, the C1 encoding subblock, or the C2 encoding subblock. A characteristic decoding method.
An empty area in which a capacity of {1- (1 ÷ (Nc ÷ Kc) ÷ (Nr ÷ Kr))} or more of the capacity of the client signal can be freely used;
A method of constructing an error correction code according to any one of claims 1, 2, 5, 7, or 9,
When converting the client signal into the super FEC signal, first, each of the J C2 code sub-blocks is encoded with the C2 code, and then the G intermediate sub-blocks or the Encoding each of the Kr intermediate sub-blocks with the C1 code,
When the super FEC signal is converted into the client signal, first, the area of (Nr × Nc) bytes is decoded by the C1 code, and then each of the jm C2 encoded sub-blocks. A method for constructing an error correction code, wherein the order of encoding and decoding with the C2 code and the C1 code is switched by performing decoding with the C2 code.
A decoding method according to any one of claims 3, 4, 6, 8, or 10,
When the client signal is converted into the super FEC signal, first, each of the jm C2 code sub-blocks is encoded with the C2 code, and then the (Nr × Nc) byte area is obtained. Encoding with the C1 code as described above;
When the super FEC signal is converted into the client signal, first, the area of (Nr × Nc) bytes is decoded by the C1 code, and then each of the jm C2 encoded sub-blocks. The decoding method is characterized in that the order of encoding and decoding by the C2 code and the C1 code is changed by performing decoding by the C2 code.
A method for constructing an error correction code according to any one of claims 1, 5, or 7,
When encoding the jm C2 code sub-blocks with the C2 code, the check bits of each C2 code sub-block are arranged in the check bit area of the subsequent C2 code sub-block,
An error characterized in that when performing decoding by C2 code on the jm C2 coded sub-blocks, the check bit of each C2 coded sub-block is calculated as being in the subsequent C2 coded sub-block Correction code construction method.
A decoding method according to any one of claims 3, 6 or 8, comprising:
When the Cm code is encoded with respect to the jm C2 code sub-blocks, check bits of each C2 code sub-block are arranged in the check bit area of the subsequent C2 code sub-block,
Decoding characterized in that when performing decoding by C2 code on the jm C2 encoded sub-blocks, the check bit of each C2 encoded sub-block is calculated as being in the subsequent C2 encoded sub-block Method.
ITU-T Recommendation G. SDH signal specified in 707,
SONET signal defined in ANSI recommendation T1.105,
ITU-T Recommendation G. A signal to be error correction encoded using eight error correction Reed-Solomon codes (255, 239) on a Galois field (256) defined in 975;
ITU-T Recommendation G. OCh layer signal defined in 872,
1000Base-SX, 1000Base-LX, or 1000Base-CX signal defined by IEEE standard 802.3z,
Or a signal obtained by arbitrarily time-division multiplexing these,
The method of constructing an error correction code according to claim 1, wherein the error correction code is any one of the following.
The client signal is an ITU-T recommendation G. SDH signal specified in 707,
Alternatively, one of 1000Base-SX, 1000Base-LX, and 1000Base-CX signals defined by IEEE standard 802.3z,
The decoding method according to claim 3, wherein the decoding method is any one of the above.
The client signal is a signal encoded by the same code Φ as the C1 code,
When converting the client signal to the super FEC signal,
The client signal is converted to a predetermined bit rate and encoded by the C2 code to be the super FEC signal,
The client signal is once decoded by the code Φ, then converted to a predetermined bit rate and encoded by the C2 code to form the super FEC signal,
Whether the client signal is once decoded by the code Φ and then encoded again by the C1 code, then converted to a predetermined bit rate and encoded by the C2 code to form the super FEC signal Or
The client signal is converted to a predetermined bit rate and encoded by the C1 code, and then encoded by the C2 code to be the super FEC signal.
When converting the super FEC signal to the client signal,
The super FEC signal is decoded by the C2 code and then converted to a predetermined bit rate to be the client signal,
The super FEC signal is decoded by the C2 code, then converted to a predetermined bit rate and decoded by the C1 code to be the client signal,
The super FEC signal is decoded by the C2 code, converted to a predetermined bit rate, once decoded by the C1 code, and then encoded again by the code Φ as the client signal. Or
The super FEC signal is decoded by the C2 code and the C1 code, and then converted into a predetermined bit rate to be the client signal.
Any one of the above, a method for constructing an error correction code.
The super FEC signal is decoded by the C2 code and then converted to a predetermined bit rate and decoded by the C1 code to be the client signal, or
Any one of the methods described above.
A method of constructing an error correction code according to claim 21,
The δ is 1, the Kc is 238, the Nc is 255,
The C1 code is an eight error correcting Reed-Solomon code (255, 239) on the Galois field (256),
ITU-T Recommendation G. A method of constructing an error correction code, characterized in that a signal subjected to error correction encoding is performed using eight error correction Reed-Solomon codes (255, 239) on a Galois field (256) defined in 975.
The decoding method according to claim 22,
ITU-T Recommendation G. A decoding method characterized in that a signal subjected to error correction coding using eight error correction Reed-Solomon codes (255, 239) on a Galois field (256) defined in 975 is provided.
Information indicating which of the four types of conversion has been performed is inserted into a predetermined FSI byte position in the overhead area of the super FEC signal,
Conversely, when converting the super FEC signal to the client signal,
A configuration of an error correction code, wherein information of a predetermined FSI byte position in the overhead area of the super FEC signal is extracted, and based on this, it is determined which of the four types of conversion is performed. Method.
A decoding method, comprising: extracting information on a predetermined FSI byte position in the overhead area of the super FEC signal and determining which of the four types of conversion is to be performed based on the extracted information.
A method of decoding a super FEC signal according to claim 3 or claim 4,
A decoding method, wherein the decoding using the C1 code and the decoding using the C2 code are alternately repeated a plurality of times.
In a predetermined FSIB byte position in the overhead area of the super FEC signal,
When encoding is performed using the C1 code and the C2 code, information indicating whether the calculation including the overhead area is inserted,
Whether or not to calculate including the overhead area when extracting information of a predetermined FSIB byte position in the overhead area of the super FEC signal and decoding with the C2 code and the C1 code based on this information A method for constructing an error correction code, characterized by:
When encoding is performed using the C1 code and the C2 code, information indicating whether or not the calculation including the overhead area is performed,
Whether or not to calculate including the overhead area when extracting information of a predetermined FSIB byte position in the overhead area of the super FEC signal and decoding with the C2 code and the C1 code based on this information A decoding method characterized by determining.
Inserting information on whether or not encoding is performed by the C1 code and the C2 code at a predetermined FSIC byte position in the overhead area of the super FEC signal,
Extracting information on a predetermined FSIC byte position in the overhead area of the super FEC signal and determining whether to decode with the C2 code and whether to decode with the C1 code based on the extracted information. A method of constructing a featured error correction code.
Extracting information on a predetermined FSIC byte position in the overhead area of the super FEC signal and determining whether to decode with the C2 code and whether to decode with the C1 code based on the extracted information. A characteristic decoding method.
A method of constructing an error correction code according to claim 1 or claim 2,
In each of the jm C2 code sub-blocks, time-synchronized continuous (Nr ÷ Kr) bits corresponding to the number of parallels are regarded as Kr bits, or Nr bits are regarded as one column, and the jm A total of jm columns are extracted from each of the C2 code sub-blocks and arranged so as to be continuous in time series, and this rearrangement is performed for all columns of the jm C2 code sub-blocks. And then re-encoding it as jm C2 code sub-blocks with the C2 code, or
A total of jm columns are extracted from each of the jm C2 encoding sub-blocks after encoding with the C2 code, and arranged so as to be continuous in time series. After iterating over all columns of jm C2 code sub-blocks, this is newly set as jm C2 encoded sub-blocks,
A method for constructing an error correction code, wherein a super FEC signal is used.
A method for constructing an error correction code according to claim 1 or 2, comprising:
Each of the Kr C1 encoding sub-blocks, each grouped every S, is shifted by a fixed time interval from each other to form a new Kr C1 encoding sub-block, or
The N2 or Kr parallel signals of the C2 encoded block, each of which is grouped for each arbitrary S signals, are shifted from each other by a fixed time interval to form a new C2 encoded block,
The Kr is either 16 or 32 or 64;
The client signal is a SONET OC-192 signal specified in ANSI recommendation T1.105, or
ITU-T Recommendation G. SDH STM-64 signal specified in 707,
8. A method of constructing an error correction code, wherein eight error correction Reed-Solomon codes (255, 239) on a Galois field (256) are used as C1 codes.
The decoding method according to claim 3 or 4, wherein:
8. A decoding method characterized by using eight error correcting Reed-Solomon codes (255, 239) on a Galois field (256) as C1 codes.
A signal obtained by terminating an 8B10B code of a digital signal encoded using an 8B10B code defined by IEEE standard 802.3z and reducing the bit rate at an appropriate rate with respect to that before the 8B10B code termination, Alternatively, the error correction according to any one of claims 1, 2, 11, and 13, wherein a signal that terminates the 8B10B code and maintains the bit rate is used as a client signal. Code construction method.
A signal obtained by terminating an 8B10B code of a digital signal encoded using an 8B10B code defined by IEEE standard 802.3z and reducing the bit rate at an appropriate rate with respect to that before the 8B10B code termination, 15. The decoding method according to claim 3, wherein the 8B10B code is terminated and a signal maintaining the bit rate is used as a client signal. .
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US11/344,579 US7512867B2 (en) 2000-06-09 2006-01-30 Method for encoding/decoding error correcting code, transmitting apparatus and network
JP2001358597A JP2001358597A (en) 2001-12-26
JP3668673B2 true JP3668673B2 (en) 2005-07-06
ID=18680663
JP2000179377A Expired - Fee Related JP3668673B2 (en) 2000-06-09 2000-06-09 Error correction code configuration method, decoding method, transmission apparatus, network
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