Source: http://www.google.com/patents/US6103601?dq=7222078
Timestamp: 2015-05-06 19:23:50
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Matched Legal Cases: ['art 1', 'art 1', 'art 1', 'art 1', 'art 2', 'art 2']

Patent US6103601 - Method and apparatus for improving film stability of halogen-doped silicon ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA fluorine-doped silicate glass (FSG) layer having a low dielectric constant and a method of forming such an insulating layer is described. The FSG layer is treated with a post-treatment step to make the layer resistant to moisture absorption and outgassing of fluorine atoms. In one embodiment, the post-treatment...http://www.google.com/patents/US6103601?utm_source=gb-gplus-sharePatent US6103601 - Method and apparatus for improving film stability of halogen-doped silicon oxide filmsAdvanced Patent SearchPublication numberUS6103601 APublication typeGrantApplication numberUS 09/330,247Publication dateAug 15, 2000Filing dateJun 10, 1999Priority dateOct 26, 1995Fee statusPaidAlso published asUS6374770Publication number09330247, 330247, US 6103601 A, US 6103601A, US-A-6103601, US6103601 A, US6103601AInventorsPeter W. Lee, Stuardo Robles, Anand Gupta, Virendra V. S. Rana, Amrita VermaOriginal AssigneeApplied Materials, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (30), Non-Patent Citations (42), Referenced by (40), Classifications (30), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod and apparatus for improving film stability of halogen-doped silicon oxide films
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Yoo et al., Intermetal Dielectric Gap Fill By Plasma Enhanced Chemical Vapor Deposited Fluorine Doped Silicon Dioxide Films, Japanese Journal of Applied Physics , vol. 35, part 2, No. 3A, pp. L273 L275 (Mar. 1996).* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6165915 *Aug 11, 1999Dec 26, 2000Taiwan Semiconductor Manufacturing CompanyForming halogen doped glass dielectric layer with enhanced stabilityUS6180540 *Feb 18, 1999Jan 30, 2001Taiwan Semiconductor Manufacturing CompanyMethod for forming a stabilized fluorosilicate glass layerUS6211570 *Aug 26, 1999Apr 3, 2001Fujitsu LimitedSemiconductor device having a multilayer interconnection structureUS6258730 *Feb 9, 1999Jul 10, 2001Advanced Micro Devices, Inc.Ultra-thin gate oxide formation using an N2O plasmaUS6303518 *Sep 30, 1999Oct 16, 2001Novellus Systems, Inc.Methods to improve chemical vapor deposited fluorosilicate glass (FSG) film adhesion to metal barrier or etch stop/diffusion barrier layersUS6372670 *Jan 4, 2000Apr 16, 2002Canon Sales Co., Inc.Method and apparatus for forming an interlayer insulating film, and semiconductor deviceUS6395092Apr 17, 2000May 28, 2002Applied Materials, Inc.Apparatus for depositing high deposition rate halogen-doped silicon oxide layerUS6413871 *Jun 22, 1999Jul 2, 2002Applied Materials, Inc.Nitrogen treatment of polished halogen-doped silicon glassUS6418875 *Jul 9, 2001Jul 16, 2002Koninklijke Philips Electronics N.V.Method of improving adhesion of cap oxide to nanoporous silica for integrated circuit fabricationUS6429105 *Jul 10, 2000Aug 6, 2002Mitsubishi Denki Kabushiki KaishaMethod of manufacturing semiconductor deviceUS6444593 *Aug 12, 1999Sep 3, 2002Advanced Micro Devices, Inc.Surface treatment of low-K SiOF to prevent metal interactionUS6455444Feb 2, 2001Sep 24, 2002Fujitsu LimitedSemiconductor device having a multilayer interconnection structureUS6461955 *Mar 9, 2000Oct 8, 2002Texas Instruments IncorporatedYield improvement of dual damascene fabrication through oxide fillingUS6465365 *Apr 7, 2000Oct 15, 2002Koninklijke Philips Electronics N.V.Method of improving adhesion of cap oxide to nanoporous silica for integrated circuit fabricationUS6489230 *Jun 22, 2001Dec 3, 2002Advanced Micro Devices, Inc.Integration of low-k SiOF as inter-layer dielectricUS6521545 *Oct 23, 2001Feb 18, 2003United Microelectronics Corp.Method of a surface treatment on a fluorinated silicate glass filmUS6551921 *Feb 20, 2001Apr 22, 2003Mitsubishi Denki Kabushiki KaishaMethod of polishing a stack of dielectric layers including a fluorine containing silicon oxide layerUS6632478Feb 22, 2001Oct 14, 2003Applied Materials, Inc.Process for forming a low dielectric constant carbon-containing filmUS6723639May 24, 2001Apr 20, 2004Taiwan Semiconductor Manufacturing CompanyPrevention of post CMP defects in Cu/FSG processUS6737328Feb 2, 2000May 18, 2004Micron Technology, Inc.Methods of forming silicon dioxide layers, and methods of forming trench isolation regionsUS6759306 *Jul 10, 1998Jul 6, 2004Micron Technology, Inc.Methods of forming silicon dioxide layers and methods of forming trench isolation regionsUS6794700 *Apr 10, 2003Sep 21, 2004Texas Instruments IncorporatedCapacitor having a dielectric layer including a group 17 elementUS6815072 *Sep 27, 2002Nov 9, 2004Taiwan Semiconductor Manufacturing Company, Ltd.Method to solve particle performance of FSG layer by using UFU season film for FSG processUS6867126Nov 7, 2002Mar 15, 2005Taiwan Semiconductor Manufacturing Company, Ltd.Method to increase cracking threshold for low-k materialsUS7018908Mar 30, 2004Mar 28, 2006Micron Technology, Inc.Methods of forming silicon dioxide layers, and methods of forming trench isolation regionsUS7091600Mar 2, 2004Aug 15, 2006Taiwan Semiconductor Manufacturing Company Ltd.Prevention of post CMP defects in CU/FSG processUS7211499Feb 23, 2006May 1, 2007Micron Technology, Inc.Methods of forming silicon dioxide layers, and methods of forming trench isolation regionsUS7250370Sep 19, 2003Jul 31, 2007Taiwan Semiconductor Manufacturing Company, Ltd.Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical propertiesUS7285503Jun 21, 2004Oct 23, 2007Applied Materials, Inc.Hermetic cap layers formed on low-k films by plasma enhanced chemical vapor depositionUS7399364Jun 12, 2006Jul 15, 2008Applied Materials, Inc.Hermetic cap layers formed on low-κ films by plasma enhanced chemical vapor depositionUS7771796Nov 4, 2005Aug 10, 2010Tokyo Electron LimitedPlasma processing method and film forming methodUS7811912 *Jun 27, 2008Oct 12, 2010Hynix Semiconductor Inc.Method for manufacturing semiconductor deviceUS8053357Aug 9, 2006Nov 8, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Prevention of post CMP defects in CU/FSG processUS8158521Jul 23, 2007Apr 17, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical propertiesUS8399359Jun 1, 2011Mar 19, 2013United Microelectronics Corp.Manufacturing method for dual damascene structureUS8647991Jul 30, 2012Feb 11, 2014United Microelectronics Corp.Method for forming dual damascene openingUS8735295Jun 19, 2012May 27, 2014United Microelectronics Corp.Method of manufacturing dual damascene structureUS8921226Jan 14, 2013Dec 30, 2014United Microelectronics Corp.Method of forming semiconductor structure having contact plugUS8962490Oct 8, 2013Feb 24, 2015United Microelectronics Corp.Method for fabricating semiconductor deviceEP1467401A2 *Apr 8, 2004Oct 13, 2004Texas Instruments IncorporatedA Capacitor Having a Dielectric Layer Including a Group 17 Element and a Method of Manufacture Therefor* Cited by examinerClassifications U.S. Classification438/513, 438/774, 438/763, 438/787, 257/E21.241, 438/783, 257/E21.276International ClassificationC23C16/56, H01L21/316, H01L21/768, H01L21/31, H01L21/3105, C23C16/40, H01L23/522Cooperative ClassificationH01L21/02131, H01L21/3105, C23C16/56, H01L21/31629, C23C16/401, H01L21/0234, H01L21/02274, H01L21/02362European ClassificationH01L21/02K2C1L1F, H01L21/02K2T8U, H01L21/02K2T8H2, H01L21/02K2E3B6B, C23C16/40B, C23C16/56, H01L21/3105, H01L21/316B6Legal EventsDateCodeEventDescriptionJan 27, 2012FPAYFee paymentYear of fee payment: 12Jan 7, 2008FPAYFee paymentYear of fee payment: 8Dec 23, 2003FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services