Source: http://www.google.com/patents/US20080062744?dq=6,910,205
Timestamp: 2016-12-09 02:06:49
Document Index: 651387968

Matched Legal Cases: ['§120', '§119', 'Application No. 60', '§120', '§119', 'Application No. 60']

Patent US20080062744 - Random access memory including nanotube switching elements - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsRandom access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes conductive terminals, a nanotube article and control circuitry capable of controllably form and unform an...http://www.google.com/patents/US20080062744?utm_source=gb-gplus-sharePatent US20080062744 - Random access memory including nanotube switching elementsAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20080062744 A1Publication typeApplicationApplication numberUS 11/879,352Publication dateMar 13, 2008Filing dateJul 17, 2007Priority dateAug 13, 2003Also published asUS7583526, US7944735, US20100005645Publication number11879352, 879352, US 2008/0062744 A1, US 2008/062744 A1, US 20080062744 A1, US 20080062744A1, US 2008062744 A1, US 2008062744A1, US-A1-20080062744, US-A1-2008062744, US2008/0062744A1, US2008/062744A1, US20080062744 A1, US20080062744A1, US2008062744 A1, US2008062744A1InventorsClaude Bertin, Thomas Rueckes, Brent SegalOriginal AssigneeBertin Claude L, Thomas Rueckes, Segal Brent MExport CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (2), Classifications (36), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetRandom access memory including nanotube switching elements
US 20080062744 A1Abstract
Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes conductive terminals, a nanotube article and control circuitry capable of controllably form and unform an electrically conductive channel between the conductive terminals. The electronic memory is a volatile storage device capable of storing a logic state in response to electrical stimulus. In certain embodiment the electronic memory has cross-coupled first and second inverters in electrical communication with the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or can operate in a shadow memory or store mode (e.g., when power is interrupted) to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode where the state of the nanotube switching elements may be transferred to the electronic memory. Images(4) Claims(24)
1. A memory cell, comprising first and second nanotube switching elements, each nanotube switching element capable of at least two memory states and each nanotube switching element comprising: first and second conductive terminals; a nanotube article having at least one electrically conductive nanotube, said article physically disposed between and capable of electrical communication with the first and second conductive terminals; control circuitry capable of controllably forming and unforming an electrically conductive channel between said first and second conductive terminals wherein said channel includes said nanotube article; and an electronic memory element capable of at least two memory states and having cross-coupled first and second inverters wherein an input node of the first inverter is coupled to an output node of the second inverter and an input node of the second inverter is coupled to an output node of the first inverter; wherein the input node of the first inverter is coupled to the control structure of the first nanotube switching element and to the second conductive terminal of the second nanotube switching element; and wherein the input node of the second inverter is coupled to the control structure of the second nanotube switching element and to the second conductive terminal of the first nanotube switching element; and wherein the control circuitry selectively transfers the state of the electronic memory to the state of the nanotube switching elements and selectively transfers the state of the nanotube switching elements to the state of the electronic memory. 2. The memory cell of claim 1 wherein the control circuitry includes a pair of electrodes disposed on opposite sides of the nanotube article, capable of electromechanically deflecting the nanotube article to controllably form and unform the conductive channel. 3. The memory cell of claim 1 wherein the control circuitry includes a channel voltage line and wherein the first conductive terminal of the second nanotube switching element and the first conductive terminal of the first nanotube switching element are coupled to the channel voltage line. 4. The memory cell of claim 1 wherein the first and second nanotube switching elements comprise nonvolatile state devices. 5. A memory circuit, comprising: a plurality of memory cells, each memory cell in electrical communication with a bit line pair, a word line, and a control line, and each memory cell including: a cell selection circuit coupled to the bit line pair and the word line to select the memory cell in response to the activation of the bit line pair and the word line; a mode selection circuit coupled to the control line to select an operation mode; a pair of nanotube switching elements, each nanotube switching element capable of storing at least two memory states and having an input node, an output node, a nanotube element and a control circuit capable of controlling electrical conductivity between the input node and the output node through the nanotube element corresponding to the memory state; an electronic memory element comprising a cross-coupled pair of first and second inverters, wherein an input node of the first inverter is coupled to the control circuit of the first nanotube switching element and to the output node of the second nanotube switching element and wherein the input node of the second inverter is coupled to the control circuit of the second nanotube switching element and to the output node of the first nanotube switching element; wherein the control circuits of the nanotube switching elements are coupled to the at least one control line; and a memory operation circuit capable of applying electrical stimulus to the bit line pair, the word line, and the control line corresponding to each of the plurality of memory cells thereby operating each of the cell selection circuits and mode selection circuits; wherein the cell selection circuits and mode selection circuits corresponding to each of the plurality of memory cells controllably set memory states stored in each of the corresponding pairs of nanotube switching elements and each electronic memory element. 6. The memory circuit of claim 5 wherein the memory states of each of the plurality of memory cells are non-volatile. 7. The memory circuit of claim 5 further comprising a release line coupled to the control circuit of each nanotube switching element to further unform an electrically conductive path between the input node and the output node of each nanotube switching element. 8. The memory circuit of claim 5 wherein for a first combination of electrical stimuli to the bit line pair, the word line, and the control line corresponding to each of the plurality of memory cells, each of the plurality of memory cells is operable in an electronic operation mode whereby a state of the corresponding electronic memory element is set. 9. The memory circuit of claim 8, wherein for a second combination of electrical stimuli to the bit line pair, the word line, and the control line corresponding to each of the plurality of memory cells, each of the plurality of memory cells is operable in a shadow memory mode whereby the shadow memory mode transfers the state of the electronic memory element to the state of the nanotube switching elements. 10. The memory circuit of claim 9 wherein for a third combination of electrical stimuli to the bit line pair, the word line, and the control line corresponding to each of the plurality of memory cells, each of the plurality of memory cells is operable in a recall mode whereby the recall mode transfers the state of the nanotube switching elements to the state of the electronic memory element. 11. The memory circuit of claim 10 wherein the memory operation circuit is further capable of resetting the memory states stored in each of the corresponding pairs of nanotube switching elements. 12. The memory circuit of claim 5 wherein for each nanotube switching element, a first non-volatile memory state corresponds to an electrically conductive channel between the input node and the output node and a second memory state corresponds to an electrically non-conductive channel between the input node and the output node. 13. The memory circuit of claim 5 wherein the electronic memory element comprises an SRAM cell. 14. A method of making a memory cell comprising: providing an electronic memory element capable of storing a memory state, the electronic memory having cross-coupled first and second inverters wherein an input node of the first inverter is coupled to an output node of the second inverter and the input node of the second inverter is coupled to an output node of the first inverter; forming first and second nanotube switching elements capable of storing a memory state, the first and second nanotube switching elements disposed over the electronic memory element; electrically coupling the input node of the first inverter to the control structure of the first nanotube switching element and to the second conductive terminal of the second nanotube switching element and the first conductive terminal of the second nanotube switching element is coupled to a channel voltage line; and electrically coupling the input node of the second inverter to the control structure of the second nanotube switching element and to the first conductive terminal of the first nanotube switching element and the first conductive terminal of the first nanotube switching element is coupled to the channel voltage line. 15. The method of claim 14 wherein forming each nanotube switching element further comprises: providing first and second conductive terminals; providing a nanotube article having at least one electrically conductive nanotube, the nanotube article physically disposed between the first and second conductive terminals; and providing a control circuit capable of controllably forming and unforming an electrically conductive channel between the first and second conductive terminals wherein the channel includes the nanotube article. 16. The method of claim 14 wherein providing an electronic memory element comprises providing an SRAM cell on a wafer substrate. 17. The method of claim 14 wherein the first and second inverters comprise CMOS inverters. 18. The method of claim 14 wherein the first and second nanotube switching elements are non-volatile state devices. 19. The method of claim 14 further comprising providing a control circuit capable of operating the memory cell in a shadow memory mode wherein the shadow memory mode transfers a state of the electronic memory to a state of the nanotube switching elements. 20. The method of claim 19, further comprising providing a voltage line to supply voltage used by the electronic memory cell, wherein the control circuit is capable of operating the memory cell in a recall mode, and wherein the recall mode transfers the state of the nanotube switching elements to the state of the electronic memory cell. 21. A non-volatile memory cell, comprising: a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and first and second nonvolatile nanotube switches coupled to the volatile storage device, each of the first and second non-volatile nanotube switches comprising a nanotube article and control circuitry, wherein the nanotube article non-volatile stores the corresponding logic state in response to electrical stimulus by the control circuitry. 22. The non-volatile memory cell of claim 21, wherein the volatile storage device comprises an SRAM cell, the SRAM cell comprising cross-coupled first and second inverters. 23. The non-volatile memory cell of claim 22, wherein an input node of the first inverter is coupled to the control structure of the first nanotube switch and wherein an input node of the second inverter is couple to the control structure of the second nanotube switch. 24. The non-volatile memory cell of claim 23, wherein each of the first and second non-volatile nanotube switches further comprise an input node and an output node, wherein the control circuitry comprises a set electrode and a release electrode, and wherein electrical stimulus at the control circuitry activates at least one of the set electrode and the release electrode and forms or unforms a conductive channel between the input and output nodes through the nanotube article in order to store the corresponding logic state.
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of and claims priority under 35 U.S.C. §120 to U.S. patent application Ser. No. 11/231,213, filed on Sep. 20, 2005, entitled Random Access Memory Including Nanotube Switching Elements, which claims priority under 35 U.S.C. §119(e) to U. S. Provisional Application No. 60/612,300 filed on Sep. 22, 2004, entitled Random Access Memory Including Nanotube Switching Elements, which is incorporated herein by reference in its entirety, and which is also a continuation-in-part of and claims priority under 35 U.S.C. §120 to U.S. patent application Ser. No. 10/918,085, now U.S. Pat. No. 6,990,009, filed on Aug. 13, 2004, entitled Nanotube-Based Switching Elements with Multiple Controls, which claims priority under 35 U.S.C. §119(e) to U.S. Provisional Application No. 60/561,330 filed Apr. 12, 2004, entitled Nanotube-Based Switching Elements with Multiple Controls, which is also incorporated herein by reference in its entirety.
BACKGROUND [0002] 1. Technical Field [0003] The present application generally relates to nanotube switching circuits and in particular to nanotube switching circuits that can be used to provide non-volatile storage functionality to otherwise conventional random access memory (RAM). [0004] 2. Discussion of Related Art [0005] Digital logic circuits are used in personal computers, portable electronic devices such as personal organizers and calculators, electronic entertainment devices, and in control circuits for appliances, telephone switching systems, automobiles, aircraft and other items of manufacture. Early digital logic was constructed out of discrete switching elements composed of individual bipolar transistors. With the invention of the bipolar integrated circuit, large numbers of individual switching elements could be combined on a single silicon substrate to create complete digital logic circuits such as inverters, NAND gates, NOR gates, flip-flops, adders, etc. However, the density of bipolar digital integrated circuits is limited by their high power consumption and the ability of packaging technology to dissipate the heat produced while the circuits are operating. The availability of metal oxide semiconductor (“MOS”) integrated circuits using field effect transistor (“FET”) switching elements significantly reduces the power consumption of digital logic and enables the construction of the high density, complex digital circuits used in current technology. The density and operating speed of MOS digital circuits are still limited by the need to dissipate the heat produced when the device is operating. [0006] Digital logic integrated circuits constructed from bipolar or MOS devices do not function correctly under conditions of high heat or extreme environments. Current digital integrated circuits are normally designed to operate at temperatures less than 100 degrees centigrade and few operate at temperatures over 200 degrees centigrade. In conventional integrated circuits, the leakage current of the individual switching elements in the “off” state increases rapidly with temperature. As leakage current increases, the operating temperature of the device rises, the power consumed by the circuit increases, and the difficulty of discriminating the off state from the on state reduces circuit reliability. Conventional digital logic circuits also short internally when subjected to certain extreme environments because electrical currents are generated inside the semiconductor material. It is possible to manufacture integrated circuits with special devices and isolation techniques so that they remain operational when exposed to such environments, but the high cost of these devices limits their availability and practicality. In addition, such digital circuits exhibit timing differences from their normal counterparts, requiring additional design verification to add protection to an existing design. [0007] Integrated circuits constructed from either bipolar or FET switching elements are volatile. They only maintain their internal logical state while power is applied to the device. When power is removed, the internal state is lost unless some type of non-volatile memory circuit, such as EEPROM (electrically erasable programmable read-only memory), is added internal or external to the device to maintain the logical state. Even if non-volatile memory is utilized to maintain the logical state, additional circuitry is necessary to transfer the digital logic state to the memory before power is lost, and to restore the state of the individual logic circuits when power is restored to the device. Alternative solutions to avoid losing information in volatile digital circuits, such as battery backup, also add cost and complexity to digital designs. [0008] Important characteristics for logic circuits in an electronic device are low cost, high density, low power, and high speed. Conventional logic solutions are limited to silicon substrates, but logic circuits built on other substrates would allow logic devices to be integrated directly into many manufactured products in a single step, further reducing cost. [0009] Devices have been proposed which use nanoscopic wires, such as single-walled carbon nanotubes, to form crossbar junctions to serve as memory cells. (See WO 01/03208, Nanoscopic Wire-Based Devices, Arrays, and Methods of Their Manufacture; and Thomas Rueckes et al., “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing,” Science, vol. 289, pp. 94-97, 7 Jul., 2000.) Hereinafter these devices are called nanotube wire crossbar memories (NTWCMs). Under these proposals, individual single-walled nanotube wires suspended over other wires define memory cells. Electrical signals are written to one or both wires to cause them to physically attract or repel relative to one another. Each physical state (i.e., attracted or repelled wires) corresponds to an electrical state. Repelled wires are an open circuit junction. Attracted wires are a closed state forming a rectified junction. When electrical power is removed from the junction, the wires retain their physical (and thus electrical) state thereby forming a non-volatile memory cell. [0010] U.S. Patent Publication No. 2003-0021966 discloses, among other things, electromechanical circuits, such as memory cells, in which circuits include a structure having electrically conductive traces and supports extending from a surface of a substrate. Nanotube ribbons that can electromechanically deform, or switch are suspended by the supports that cross the electrically conductive traces. Each ribbon comprises one or more nanotubes. The ribbons are typically formed from selectively removing material from a layer or matted fabric of nanotubes. [0011] For example, as disclosed in U.S. Patent Publication No. 2003-0021966, a nanofabric may be patterned into ribbons, and the ribbons can be used as a component to create non-volatile electromechanical memory cells. The ribbon is electromechanically-deflectable in response to electrical stimulus of control traces and/or the ribbon. The deflected, physical state of the ribbon may be made to represent a corresponding information state. The deflected, physical state has non-volatile properties, meaning the ribbon retains its physical (and therefore informational) state even if power to the memory cell is removed. As explained in U.S. Patent Publication No. 2003-0124325, three-trace architectures may be used for electromechanical memory cells, in which the two of the traces are electrodes to control the deflection of the ribbon. [0012] The use of an electromechanical bi-stable device for digital information storage has also been suggested (c.f. U.S. Pat. No. 4,979,149: Non-volatile memory device including a micro-mechanical storage element). [0013] The creation and operation of bi-stable, nano-electro-mechanical switches based on carbon nanotubes (including mono-layers constructed thereof) and metal electrodes has been detailed in a previous patent application of Nantero, Inc. (U.S. Pat. Nos. 6,574,130, 6,643,165, 6,706,402, 6,784,028, 6,835,591, 6,911,682, 6,919,592, and 6,924,538; and U.S. patent application Ser. Nos. 10/341,005, 10/341,055, 10/341,054, 10/341,130, and 10/776,059, the contents of which are hereby incorporated by reference in their entireties). SUMMARY [0014] The present invention provides random access memory including nanotube switching elements. [0015] Under one aspect of the invention a memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control structure having a set electrode and a release electrode disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said channel electrode and said output node. The electronic memory has cross-coupled first and second inverters. The input node of the first inverter is coupled to the set electrode of the first nanotube switching element and to the output node of the second nanotube switching element. The input node of the of the second inverter is coupled to the set electrode of the second nanotube switching element and to the output node of the first nanotube switching element; and the channel electrode is coupled to a channel voltage line. [0016] Under another aspect of the invention, the release electrode of the first nanotube switching element is coupled to the release electrode of the second nanotube switching element and wherein both release electrodes are coupled to a release line. [0017] Under another aspect of the invention, the first and second inverters are CMOS inverters. [0018] Under another aspect of the invention, the first and second nanotube switching elements are non-volatile state devices. [0019] Under another aspect of the invention, the first and second nanotube switching elements are fabricated in circuit layers above circuit layers used to fabricate the electronic memory. [0020] Under another aspect of the invention, the channel voltage line is set to one-half the supply voltage used by the electronic memory, when the circuit operates in an electronic memory mode. The channel voltage line is set to nanotube channel switching voltage, when the circuit operates in a shadow memory mode. In shadow memory mode, the state of the electronic memory transfers to the state of the nanotube switching elements. [0021] Under another aspect of the invention, the channel voltage line is set to the supply voltage used by the electronic memory, when the circuit operates in a recall mode. In the recall mode the state of the nanotube switching elements transfers to the state of the electronic memory. [0022] Under another aspect of the invention, the release electrode of the first nanotube switching element is coupled to the release electrode of the second nanotube switching element and both are coupled to a release line. After the recall mode transfers the state of the nanotube switching elements to the state of the electronic memory, the release line is activated to reset the state of the nanotube switching elements.
BRIEF DESCRIPTION OF THE DRAWINGS [0023] In the Drawing, [0024] FIGS. 1A-1D illustrate cross-sectional views and a plan view of a nanotube switching element of certain embodiments in two different states and include a plan view of such element; [0025] FIG. 2 is a schematic view of a non-volatile random access storage element in accordance with certain embodiments of the invention.
DETAILED DESCRIPTION [0026] Preferred embodiments of the invention provide switching elements in which a nanotube-based switching element is included with an otherwise conventional RAM cell. The nanotube switching element may then be used to provide non-volatile storage functionality, for example, to act as a shadow ram. Moreover, the design of preferred embodiments of the nanotube switching elements may be included as extra layers on top of already formed RAM cells. [0027] First, the nanotube switching element will be described. Second, the integration of such an element with a RAM cell will be explained. Nanotube Switching Element [0028] FIG. 1A is a cross sectional view of a preferred nanotube switching element 100. Nanotube switching element includes a lower portion having an insulating layer 117, control electrode 111, output electrodes 113 c,d. Nanotube switching element further includes an upper portion having release electrode 112, opposing output electrodes 113 a,b, and signal electrodes 114 a,b. A nanotube channel element 115 is positioned between and held by the upper and lower portions. [0029] Release electrode 112 is made of conductive material and is separated from nanotube channel element 115 by an insulating material 119. The channel element 115 is separated from the facing surface of insulator 119 by a gap height G102. [0030] Opposing output electrodes 113 a,b are made of conductive material and are separated from nanotube channel element 115 by insulating material 119. [0031] Output electrodes 113 c,d are likewise made of conductive material and are separated from nanotube channel element 115 by a gap height G103. Notice that the output electrodes 113 c,d are not covered by insulator. [0032] Control electrode 111 is made of conductive material and is separated from nanotube channel element 115 by an insulating layer (or film) 118. The channel element 115 is separated from the facing surface of insulator 118 by a gap height G104. [0033] Signal electrodes 114 a,b each contact the nanotube channel element 115 and can therefore supply whatever signal is on the signal electrode to the channel element 115. This signal may be a fixed reference signal (e.g., VDD or Ground) or varying (e.g., a Boolean discrete value signal that can change). Only one of the electrodes 114 a,b need be connected, but both may be used to reduce effective resistance. [0034] Nanotube channel element 115 is a lithographically-defined article made from a porous fabric of nanotubes (more below). It is electrically connected to signal electrodes 114 a,b. The electrodes 114 a,b and support 116 pinch or hold or pin the channel element 115 at either end, and it is suspended in the middle in spaced relation to the output electrodes 113 a-d and the control electrode 111 and release electrode 112. The spaced relationship is defined by the gap heights G102-G104 identified above. For certain embodiments, the length of the suspended portion of channel element 115 is about 300 to 350 nm. [0035] Under certain embodiments the gaps G103, G104, G102 are in the range of 5-30 nm. The dielectric on terminals 112, 111, and 113 a and 113 b are in the range of 5-30 nm, for example. The carbon nanotube fabric density is approximately 10 nanotubes per 0.2×0.2 um area, for example. The suspended length of the nanotube channel element is in the range of 300 to 350 nm, for example. The suspended length to gap ratio is about 5 to 15 to 1 for non-volatile devices, and less than 5 for volatile operation, for example. [0036] FIG. 1B is a plan view or layout of nanotube switching element 100. As shown in this figure, electrodes 113 b,d are electrically connected as depicted by the notation ‘X’ and item 102. Likewise opposing output electrodes 113 a,c are connected as depicted by the ‘X’. In preferred embodiments the electrodes are further connected by connection 120. All of the output electrodes collectively form an output node 113 of the switching element 100. [0037] Under preferred embodiments, the nanotube switching element 100 of FIGS. 1A and 1B operates as shown in FIGS. 1C and D. Specifically, nanotube switching element 100 is in an OPEN (OFF) state when nanotube channel element is in position 122 of FIG. 1C. In such state, the channel element 115 is drawn into mechanical contact with dielectric layer 119 via electrostatic forces created by the potential difference between electrode 112 and channel element 115. Opposing output electrodes 113 a,b are in mechanical contact (but not electrical contact) with channel element 115. Nanotube switching element 100 is in a CLOSED (ON) state when channel element 115 is elongated to position 124 as illustrated in FIG. 1D. In such state, the channel element 115 is drawn into mechanical contact with dielectric layer 118 via electrostatic forces created by the potential difference between electrode 111 and channel element 115. Output electrodes 113 c,d are in mechanical contact and electrical contact with channel element 115 at regions 126. Consequently, when channel element 115 is in position 124, signal electrodes 114 a and 114 b are electrically connected with output terminals 113 c,d via channel element 115, and the signal on electrodes 114 a,b may be transferred via the channel (including channel element 115) to the output electrodes 113 c,d. [0038] By properly tailoring the geometry of nanotube switching element 100, the nanotube switching element 100 may be made to behave as a non-volatile or a volatile switching element. By way of example, the device state of FIG. 1D may be made to be non-volatile by proper selection of the length of the channel element relative to the gap G104. (The length and gap are two parameters in the restoring force of the elongated, deflected channel element 115.) Length to gap ratios of greater than 5 and less than 15 are preferred for non-volatile device; length to gap ratios of less than 5 are preferred for volatile devices. [0039] The nanotube switching element 100 operates in the following way. If signal electrode 114 and control electrode 111 (or 112) have a potential difference that is sufficiently large (via respective signals on the electrodes), the relationship of signals will create an electrostatic force that is sufficiently large to cause the suspended, nanotube channel element 115 to deflect into mechanical contact with electrode 111 (or 112). (This aspect of operation is described in the incorporated patent references.) This deflection is depicted in FIGS. 1D (and 1C). The attractive force stretches and deflects the nanotube fabric of channel element 115 until it contacts the insulated region 118 of the electrode 111. The nanotube channel element is thereby strained, and there is a restoring tensil force, dependent on the geometrical relationship of the circuit, among other things. [0040] By using appropriate geometries of components, the switching element 100 then attains the closed, conductive state of FIG. 1D in which the nanotube channel 115 mechanically contacts the control electrode 111 and also output electrode 113 c,d. Since the control electrode 111 is covered with insulator 118 any signal on electrode 114 is transferred from the electrode 114 to the output electrode 113 via the nanotube channel element 115. The signal on electrode 114 may be a varying signal, a fixed signal, a reference signal, a power supply line, or ground line. The channel formation is controlled via the signal applied to the electrode 111 (or 112). Specifically the signal applied to control electrode 111 needs to be sufficiently different in relation to the signal on electrode 114 to create the electrostatic force to deflect the nanotube channel element to cause the channel element 115 to deflect and to form the channel between electrode 114 and output electrode 113, such that switching element 100 is in the CLOSED (ON) state. [0041] In contrast, if the relationship of signals on the electrode 114 and control electrode 111 is insufficiently different, then the nanotube channel element 115 is not deflected and no conductive channel is formed to the output electrode 113. Instead, the channel element 115 is attracted to and physically contacts the insulation layer on release electrode 112. This OPEN (OFF) state is shown in FIG. 1C. The nanotube channel element 115 has the signal from electrode 114 but this signal is not transferred to the output node 113. Instead, the state of the output node 113 depends on whatever circuitry it is connected to and the state of such circuitry. The state of output node 113 in this regard is independent of channel element voltage from signal electrode 114 and nanotube channel element 115 when the switching element 100 is in the OPEN (OFF) state. [0042] If the voltage difference between the control electrode 111 (or 112) and the channel element 115 is removed, the channel element 115 returns to the non-elongated state (see FIG. 1A) if the switching element 100 is designed to operate in the volatile mode, and the electrical connection or path between the electrode 115 to the output node 113 is opened. [0043] Preferably, if the switching element 100 is designed to operate in the non-volatile mode, the channel element is not operated in a manner to attain the state of FIG. 1A. Instead, the electrodes 111 and 112 are expected to be operated so that the channel element 115 will either be in the state of FIG. 1C or 1D. [0044] The output node 113 is constructed to include an isolation structure in which the operation of the channel element 115 and thereby the formation of the channel is invariant to the state of the output node 113. Since in the preferred embodiment the channel element is electromechanically deflectable in response to electrostatically attractive forces, a floating output node 113 in principle could have any potential. Consequently, the potential on an output node may be sufficiently different in relation to the state of the channel element 115 that it would cause deflection of the channel element 115 and disturb the operation of the switching element 100 and its channel formation; that is, the channel formation would depend on the state of an unknown floating node. In the preferred embodiment this problem is addressed with an output node that includes an isolation structure to prevent such disturbances from being caused. [0045] Specifically, the nanotube channel element 115 is disposed between two oppositely disposed electrodes 113 b,d (and also 113 a,c) of equal potential. Consequently, there are equal but opposing electrostatic forces that result from the voltage on the output node. Because of the equal and opposing electrostatic forces, the state of output node 113 cannot cause the nanotube channel element 115 to deflect regardless of the voltages on output node 113 and nanotube channel element 115. Thus, the operation and formation of the channel is made invariant to the state of the output node. [0046] The nanotube switching element described above, along with various alternatives to such, is explained in greater detail in U.S. patent application Ser. No. 10/918,085, filed on Aug. 13, 2004, entitled Nanotube-Based Switching Elements with Multiple Controls, which is hereby incorporated by reference in its entirety. Ram with Nanotube Switching Element [0047] In preferred versions, storage elements are constructed from conventional storage cell designs, for example using CMOS transistors, with additional nanotube-based non-volatile switching elements like those described above. In preferred versions, the storage circuitry operates using non-volatile switching of nanotubes. [0048] However, 4-terminal device 100 is non-volatile and also includes a release node R. The outputs have opposing electrodes. The input electrode I has a dielectric layer over it so the CNT comes in physical but not electrical contact with the input electrode. The release electrode R has a dielectric layer under it so the CNT comes in physical but not electrical contact with the release electrode. [0049] The 4-terminal non-volatile CNT device may be used as a shadow device, for example, on each of the flip flop nodes of SRAM cells. These 4-terminal devices are added at or near the end of the process for an SRAM, and are used to store information when power is lost or removed. [0050] FIG. 2 illustrates a memory cell 200 having a flip-flop based non-volatile RAM cell with an SRAM structure 202 and two CNT 4-terminal structures 204 and 206, one for each node N1 and N2 of the flip flop cell 202. See U.S. patent application Ser. No. 10/918,085, filed on Aug. 13, 2004, entitled Nanotube-Based Switching Elements with Multiple Controls. This implementation offers various advantages discussed above because the CNTs can be added to an existing SRAM product and added to existing wafers. Operation is described below. The assumptions for this discussion of the operation of this implementation are as follows: The CNT switching elements 204 and 206 are in a released state (CNT in contact with the insulator of release plate R) during SRAM operation, prior to the STORE operation The CNT voltage VCNT applied to CNT channel element N is at VDD/2 so that the FF 202 does not activate the CNTs prior to the STORE operation The STORE operation for initially storing data in the cell, is as follows: STORE: SRAM operation is stopped The CNT voltage VCNT transitions from VDD/2 to VSW, the voltage required to switch the CNTs. CNT switching element activation takes place between the input I that is held at ground by the flip flop and CNT channel element N which transitions to VCNT=VSW. The CNT switching element turns ON, and voltage VCNT is applied to the output electrode of the CNT device by contact with CNT channel element N. The output electrode is connected to the opposite side of the flip flop which is positive. The CNT switching element with input voltage=0 switches, the CNT switching element output is positive, and therefore does not disturb the flip flop state. The other CNT switching element remains in the released (OFF) position Power supply VDD goes to zero [0059] The nanotube switching elements retain the logic state of the flip flop cell especially if the storage element is powered down or if the power is interrupted, for example. The procedure for recalling stored data from a storage element is as follows: RECALL: The CNT switching elements 204 and 206 are powered up. VCNT=VDD The SRAM is powered up to VDD Flip flops assume state corresponding to the logic state of the non-volatile CNT switching elements. CNT switching elements are reset to the erase position (in contact with oxide on release plate). This is accomplished by raising the release line voltage VRL to high enough voltage to overcome electrostatic forces between the input and the NT. This voltage may be greater than VDD. SRAM operation resumes [0066] The inventors envision additional configurations of volatile and nonvolatile or mixed nanoelectromechanical designs depending upon the specific application, speed, power requirements and density desired. Additionally the inventors foresee the use of multiwalled carbon nanotubes or nanowires as the switching element of contact points within the switch. As the technology node decreases in size from 90 nm to 65 nm and below down to the size of individual nanotubes or nanowires the inventors foresee adapting the basic electromechanical switching elements and their operation to a generation of nanoscale devices with scaleable performance characteristics concomitant with such size reduction. [0067] The devices and articles shown in the preceding embodiments are given for illustrative purposes only, and other techniques may be used to produce the same or equivalents thereof. Furthermore, the articles shown may be substituted with other types of materials and geometries in yet other embodiments. For example, rather than using metallic electrodes, some embodiments of the present invention may employ nanotubes. In fact, devices comprising nanotube and nanofabric articles in place of the electrodes shown above can be constructed as well. [0068] The above embodiments utilized nanotube switching elements operating in a non-volatile manner. Volatile operation of nanofabric switches is within the scope of certain versions of the present invention, however. In addition, coordination of volatile and non-volatile elements may be advantageous for simultaneously generating logic and memory functions or as part of overall logic functionality or for improved electrical characteristics; for example, the above-described or incorporated embodiments of volatile nanotube switching elements (like the non-volatile elements) do not necessarily draw DC current and may only dissipate power when they switch. [0069] Volatile and non-volatile switches, and switching elements of numerous types of devices, can be thus created. In certain preferred embodiments, the articles include substantially a monolayer of carbon nanotubes. In certain embodiments the nanotubes are preferred to be single-walled carbon nanotubes. Such nanotubes can be tuned to have a resistance between 0.2-100 kOhm/□ or in some cases from 100 kOh/□ to 1 GOhm/□. [0070] The following patent references refer to various techniques for creating nanotube fabric articles and switches and are assigned to the assignee of this application. Each is hereby incorporated by reference in their entirety: U.S. Pat. No. 6,919,592, entitled Electromechanical Memory Array Using Nanotube Ribbons and Method for Making Same; U.S. Pat. No. 6,784,028, entitled Methods of Making Electromechanical Three-Trace Junction Devices; U.S. Pat. No. 6,706,402, entitled Nanotube Films and Articles; U.S. patent application Ser. No. 10/341,005, filed on Jan. 13, 2003, entitled Methods of Making Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles; U.S. patent application Ser. No. 10/776,059, filed Feb. 11, 2004, entitled Devices Having Horizontally-Disposed Nanofabric Articles and Methods of Making The Same; and U.S. Pat. No. 6,924,538, entitled Devices Having Vertically-Disposed Nanofabric Articles and Methods of Making the Same. [0077] The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of the equivalency of the claims are therefore intended to be embraced therein.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6809361 *Jan 9, 2004Oct 26, 2004Infineon Technologies AgMagnetic memory unit and magnetic memory arrayUS6969651 *Mar 26, 2004Nov 29, 2005Lsi Logic CorporationLayout design and process to form nanotube cell for nanotube memory applicationsUS6990009 *Aug 13, 2004Jan 24, 2006Nantero, Inc.Nanotube-based switching elements with multiple controlsUS7245520 *Sep 20, 2005Jul 17, 2007Nantero, Inc.Random access memory including nanotube switching elementsUS7262991 *Jun 30, 2005Aug 28, 2007Intel CorporationNanotube- and nanocrystal-based non-volatile memoryUS7385839 *Dec 1, 2005Jun 10, 2008International Business Machines CorporationMemory devices using carbon nanotube (CNT) technologies* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7940557 *Dec 21, 2010May 10, 2011Agate Logic, Inc.Non-volatile electromechanical configuration bit arrayUS20110122686 *Dec 21, 2010May 26, 2011Agate Logic, Inc.Non-volatile electromechanical configuration bit array* Cited by examinerClassifications U.S. Classification365/151, 977/943, 365/166International ClassificationG11C11/00Cooperative ClassificationG11C23/00, H01H1/0094, H01H1/027, H01L51/0048, G11C2213/17, G11C14/00, G11C13/025, H01L29/0673, H01L27/28, Y10T29/49002, H01L29/0665, H01L51/0508, B82Y10/00, H01L29/78, H01L29/73, G11C11/412, Y10S977/943, Y10S977/936, Y10S977/938European ClassificationB82Y10/00, H01H1/00N, H01L51/00M4D, G11C23/00, H01L29/06C6W2, H01L29/06C6, H01L29/78, H01L29/73, H01L51/05B2, H01L27/28, G11C11/412, G11C14/00, G11C13/02NLegal EventsDateCodeEventDescriptionAug 20, 2008ASAssignmentOwner name: LOCKHEED MARTIN CORPORATION, MARYLANDFree format text: LICENSE;ASSIGNOR:NANTERO, INC.;REEL/FRAME:021411/0337Effective date: 20080813Owner name: LOCKHEED MARTIN CORPORATION,MARYLANDFree format text: LICENSE;ASSIGNOR:NANTERO, INC.;REEL/FRAME:021411/0337Effective date: 20080813Mar 1, 2013FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services