Source: https://patents.google.com/patent/US9905624B2/en
Timestamp: 2018-11-13 21:13:50
Document Index: 164607362

Matched Legal Cases: ['Application No. 201110330443', 'Application No. 201110330443', 'Application No. 02024970', 'Application No. 2002', 'Application No. 91132611', 'Application No. 02024970']

US9905624B2 - Light emitting device - Google Patents
US9905624B2
US9905624B2 US15433007 US201715433007A US9905624B2 US 9905624 B2 US9905624 B2 US 9905624B2 US 15433007 US15433007 US 15433007 US 201715433007 A US201715433007 A US 201715433007A US 9905624 B2 US9905624 B2 US 9905624B2
US15433007
US20170162642A1 (en )
This application is a divisional of U.S. application Ser. No. 14/730,334, filed Jun. 4, 2015, now allowed, which is a continuation of U.S. application Ser. No. 14/172,943, filed Feb. 5, 2014, now U.S. Pat. No. 9,054,199, which is a continuation of U.S. application Ser. No. 13/689,888, filed Nov. 30, 2012, now U.S. Pat. No. 8,648,338, which is a continuation of U.S. application Ser. No. 13/432,009, filed Mar. 28, 2012, now U.S. Pat. No. 8,154,015, which is a divisional of U.S. application Ser. No. 12/758,862, filed Apr. 13, 2010, now U.S. Pat. No. 8,154,015, which is a divisional of U.S. application Ser. No. 10/286,868, filed Nov. 4, 2002, now U.S. Pat. No. 7,723,721, which claims the benefit of a foreign priority application filed in Japan as Serial No. 2001-344671 on Nov. 9, 2001, and Serial No. 2002-010766 on Jan. 18, 2002, all of which are incorporated by reference.
Furthermore, when the pixel structure shown in FIGS. 5 and 6 is adopted, without forming a capacitance portion for the formation of the retention capacitance, the oxide film capacitance Cox, can be partially used as the retention capacitance. However, in one pixel, the retention capacitance and a memory (SRAM, DRAM or the like) may be formed. Still furthermore, in one pixel, a plurality of TFTs (two or more TFTs) and various circuits (current mirror circuit or the like) may be incorporated.
Next, after the oxide film on the surface of the silicon film having a crystalline structure is removed by dilute hydrofluoric acid or the like, irradiation of first laser light (XeCl: wavelength of 308 nm) for raising a crystallization rate and repairing defects remaining in crystal grains is performed in an atmosphere or in an oxygen atmosphere. Excimer laser light with a wavelength of 400 nm or less, or second harmonic wave or third harmonic wave of a YAG laser is used for the laser light. In any case, pulse laser light with a repetition frequency of approximately 10 to 1000 Hz is used, the pulse laser light is condensed to 100 to 500 mJ/cm2 by an optical system, and irradiation is performed with an overlap ratio of 90 to 95%, whereby the silicon film surface may be scanned. Here, the irradiation of the first laser light is performed in an atmosphere with a repetition frequency of 30 Hz and energy density of 470 mJ/cm2. Note that an oxide film is formed on the surface by the first laser light irradiation since the irradiation is conducted in an atmosphere or in an oxygen atmosphere. Though an example of using the pulse laser is shown here, the continuous oscillation laser may also be used. When a crystallization of an amorphous semiconductor film is conducted, it is preferable that the second harmonic through the fourth harmonic of basic waves is applied by using the solid state laser which is capable of continuous oscillation in order to obtain a crystal in large grain size. Typically, it is preferable that the second harmonic (with a thickness of 532 nm) or the third harmonic (with a thickness of 355 nm) of an Nd: YVO4 laser (basic wave of 1064 nm) is applied. Specifically, laser beams emitted from the continuous oscillation type YVO4 laser with 10 W output is converted into a harmonic by using the non-linear optical elements. Also, a method of emitting a harmonic by applying crystal of YVO4 and the non-linear optical elements into a resonator. Then, more preferably, the laser beams are formed so as to have a rectangular shape or an elliptical shape by an optical system, thereby irradiating a substance to be treated. At this time, the energy density of approximately 0.01 to 100 MW/cm2 (preferably 01. to 10 MW/cm2) is required. The semiconductor film is moved at approximately 10 to 2000 cm/s rate relatively corresponding to the laser beams so as to irradiate the semiconductor film.
The second etching treatment is performed without removing a resist mask. Here, CF4 and Cl2 are used as etching gases, the flow rate of the gases is set to 30/30 sccm, and RF (13.56 MHz) power of 500 W is applied to a coil-shape electrode with a pressure of 1 Pa to generate plasma, thereby performing etching for about 60 seconds. RF (13.56 MHz) power of 20 W is also applied to the substrate side (sample stage) to substantially apply a negative self-bias voltage. Thereafter, the fourth etching treatment is performed without removing a resist mask, CF4, Cl2, and O2 are used as etching gases, the flow rate of the gases is set to 20/20/20 seecm, and RF (13.56 MHz) power of 500 W is applied to a coil-shape electrode with a pressure of 1 Pa to generate plasma, thereby performing etching for about 20 seconds. RF (13.56 MHz) power of 20 W is also applied to the substrate side (sample stage) to substantially apply a negative self-bias voltage. Here, the third etching condition and the fourth etching condition are referred to as the second etching treatment. At this stage, the gate electrode and electrodes 304 and 305 to 307 comprised of the first conductive layer 304 a as a lower layer and the second conductive layer 304 b as a upper layer are formed. At this state, the upper structure of pixels may be formed as shown in FIG. 6.
Then, a step of activating the impurity element added to the respective semiconductor layers is conducted. In this activation step, a rapid thermal annealing (RTA) method using a lamp light source, a method of irradiating light emitted from a YAG laser or excimer laser from the back surface, beat treatment using a furnace, or a combination thereof is employed.
a semiconductor layer comprising a channel formation region, a source region, and a drain region;
a first insulating film over the semiconductor layer;
a gate wiring over the first insulating film;
a first source wiring over the second insulating film;
a second source wiring over the second insulating film; and
a power supply line over the second insulating film,
wherein the second source wiring overlaps with the semiconductor layer,
wherein the power supply line is electrically connected to one of the source region and the drain region,
wherein the power supply line overlaps with the channel formation region,
wherein the channel formation region comprises a serpentine shape,
wherein the serpentine shape comprises a first region which extends in a direction along the gate wiring and a second region which extends in a direction along the first source wiring,
wherein the first region is longer than the second region, and
wherein a ratio of a channel width W of the channel formation region to a channel length L thereof is from 0.1 to 0.01.
wherein the second region is longer than the first region, and
a source wiring over the second insulating film; and
wherein the source wiring overlaps with the semiconductor layer,
wherein the power supply line includes a region that a width of the power supply line is larger than a width of the source wiring,
wherein the channel formation region comprises a serpentine shape, and
US15433007 2001-11-09 2017-02-15 Light emitting device Active US9905624B2 (en)
US15894981 US20180190745A1 (en) 2001-11-09 2018-02-13 Light emitting device
US14730334 Division US9577016B2 (en) 2001-11-09 2015-06-04 Light emitting device
US15894981 Continuation US20180190745A1 (en) 2001-11-09 2018-02-13 Light emitting device
US20170162642A1 true US20170162642A1 (en) 2017-06-08
US9905624B2 true US9905624B2 (en) 2018-02-27
US10286868 Expired - Fee Related US7723721B2 (en) 2001-11-09 2002-11-04 Light emitting device having TFT
US15894981 Pending US20180190745A1 (en) 2001-11-09 2018-02-13 Light emitting device
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US20180190745A1 (en) 2018-07-05 application
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:UDAGAWA, MAKOTO;HAYAKAWA, MASAHIKO;KOYAMA, JUN;AND OTHERS;SIGNING DATES FROM 20021025 TO 20021028;REEL/FRAME:041949/0737