Source: http://www.google.de/patents/US5517664
Timestamp: 2013-05-25 09:01:18
Document Index: 495882197

Matched Legal Cases: ['art 11', 'art 12', 'art 15', 'art 12', 'art 13', 'art 14', 'art 13', 'art 14', 'art 24', 'art 14', 'art 23', 'art 14', 'art 14', 'art 13', 'art 14', 'art 14', 'art 11', 'art 11', 'art 11', 'art 15', 'art 15', 'art 112', 'art 113', 'art 114', 'art 121', 'art 117', 'art 118', 'art 119', 'art 120', 'art 12', 'art 213', 'art 212', 'art 214']

Patent US5517664 - RISC system with instructions which include register area and displacement ... - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr » Erweiterte Patentsuche | Webprotokoll | Anmelden Erweiterte Patentsuche PatenteIn a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register...http://www.google.de/patents/US5517664?utm_source=gb-gplus-sharePatent US5517664 - RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing Ver�ffentlichungsnummerUS5517664 APublikationstypErteilung Anmeldenummer08/459,965 Ver�ffentlichungsdatum14. Mai 1996Eingetragen2. Juni 1995 Priorit�tsdatum14. Apr. 1986Auch ver�ffentlicht unterEP0241909A2EP0241909A3EP0241909B1EP0517282A1EP0517282B1US5214786US5307502US5450610 ErfinderYugo KashiwagiKeiichi KurakazuTohru NojiriKeisuke ToyamaTan WatanabeUrspr�nglich Bevollm�chtigterHitachi, Ltd.Renesas Electronics Corporation US-Klassifikation712/41712/E09.23712/E09.82712/E09.25712/E09.35712/228Internationale KlassifikationG06F9/355G06F9/48G06F12/02G06F9/42G06F15/00G06F12/00G06F9/46G06F9/318G06F9/30G06F9/40 UnternehmensklassifikationG06F9/30105G06F9/30134G06F9/30138G06F9/461G06F9/3012G06F9/342G06F9/30181G06F9/4425G06F9/462G06F9/30127 Europ�ische KlassifikationG06F9/30XG06F9/30R5SG06F9/30R5C2G06F9/30R5G06F9/34XG06F9/30R5XG06F9/44F1AG06F9/30R4G06F9/46GG06F9/46G2ReferenzenPatentzitate (5)Nichtpatentzitate (2) Referenziert von (20)Externe LinksUSPTO USPTO-Zuordnung EspacenetRISC system with instructions which include register area and displacement portions for accessing data stored in registers during processingUS 5517664 A Zusammenfassung In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing.
The instruction decoder 10 extracts instructions from an instruction sequence directly given by a user as an instruction sequence for this information processing apparatus or from an instruction sequence generated by a language processor, in a predetermined order from the main memory 2, and it subjects each individual instruction to processes corresponding to the roles of the respective constituent parts of the instruction. A typical instruction has an operation code part 11 indicating the kind of an operation, a register designator part 12 and a main memory designator part 15. The register designator part 12 further includes an area register part 13 and a register displacement part 14 having a length of l bits. Letting i denote the value of the area register part 13 of a certain instruction, the value i is sent to the area register selection circuit 20 of the register access mechanism 5, and the R.sub.i register 21 in the register block 3 is selected as an area register. Letting b.sub.i denote the content of the R.sub.i register 21, the value b.sub.i is sent to the register area pointer 22. While the bit length of the register displacement part 14 has been denoted by l, the register selection circuit 31 is supplied with a logical sum obtained by inputting the content of the lower l bit part 24 of the register address of L bits and that of the register displacement part 14 to the OR circuit 30. In addition, the upper (L-l) bits of the register address are set as the value itself of the upper (L-l) bit part 23 of the register area pointer 22.
When the value of the area register 21 is expressed by b.sub.i and a binary number whose lower l bits are O's is set beforehand, the register address synthesized by the OR circuit 30 as stated above becomes equal to the arithmetical sum b.sub.i +d between the value b.sub.i and the value d of the register displacement part 14. The lower l bits of the content of the area register 21 need not always be set at O's. Let l' denote a number equal to or smaller than the bit length l of the register displacement part 14, the content of a certain area register is set at a number with its lower l' bits being O's. In an instruction wherein the address of the area register is used in the area register part 13, if the value of the register displacement part is limited to numbers expressible with l' bits, the register No. synthesized by the OR circuit 30 as described above becomes equal to a value obtained by taking the arithmetical sum between both the values of the area register and the register displacement part. What value is to be set as the number l' for limiting the value to be put in the register displacement part 14 can be selected by software. Therefore, the value l' can be varied for every use of the area register. Moreover, even for one area register, it can be varied depending upon the time of use.
Now, when the register No. b.sub.i +d is synthesized in the above way out of the value b.sub.i of the area register 21 selected by a certain instruction and the value d of the register displacement part 14 and is sent to the register selection circuit 31, the (R.sub.b.sbsb.i.sub.+d) register 32 of register address b.sub.i +d is selected as a register for use in the instruction. If the content of the operation code part 11 of the instruction indicates an instruction whose operand is the content of the selected register, then the content of the register R.sub.b.sbsb.i.sub.+d is sent to the ALU 4, and the operation is executed there. On the other hand, if the content of the operation code part 11 indicates an instruction the result register of which is the selected register, then a result from the ALU 4 is put in the register R.sub.b.sbsb.i.sub.+d. If the content of the operation code part 11 is a load instruction, the content of a main memory address indicated by the main memory designator part 15 is put in the register R.sub.b.sbsb.i.sub.+d, and if it indicates a store instruction, the content of the register R.sub.b.sbsb.i.sub.+d is stored in a main memory of the address indicated by the main memory designator part 15. The transfer register 41 in the main memory access mechanism 6 is a register for temporarily holding information which is transferred between the main memory 2 and the instruction processor 1, while the main memory address register 42 is a register for temporarily holding the address of the main memory 2 which is selected at that time.
FIG. 2(b) shows an instruction the main memory designator part 112 of which includes a register designator part 113 for designating a base register, a register designator part 114 for designating an index register, and a main memory displacement part 121. In this instruction, a register R.sub.b to be used as the base register is found in the foregoing way on the basis of an area register part 117 and a register displacement part 118 on one side, while a register R.sub.x to be used as the index register is found in the foregoing form on the basis of an area register part 119 and a register displacement part 120 on the other side, and an address obtained by taking the arithmetical sum of the three, the content of the base register R.sub.b, the content of the index register R.sub.x and the value of the main memory displacement part 12 is set as the address of the main memory 2 for use in the instruction.
FIG. 3 is an arrangement diagram of the essential portions of an information processing apparatus showing the second embodiment of the present invention. In this embodiment, an area register block 207 which is a set of special-purpose area registers is disposed separately from a general register block 203 within an instruction processor 201. The general register block 203 is composed of general registers R.sub.0, R.sub.1, . . . and R.sub.N, while the area register block 207 is composed of area registers Q.sub.0, Q.sub.1, . . . and Q.sub.K. When the content i of an area register part 213 included in the register designator part 212 of an instruction is sent to an area register selection circuit 220 in a register access mechanism 205, the content b.sub.i of the area register (Q.sub.i) 221 in the area register block 207 is sent to a register area pointer 222. This content b.sub.i of the area register Q.sub.i and the content d of the register displacement part 214 of the instruction are added by a register address calculator 230, and the sum value b.sub.i +d is sent to a register selection circuit 231. As a result, the (R.sub.b.sbsb.i.sub.+d) register 232 is selected from within the general register block 203 as a register for use in this instruction. The other portions such as an ALU 204 and a main memory access mechanism 206 are the same as in the first embodiment described with reference to FIG. 1.
FIGS. 5(a) and 5(b) are diagrams showing the arrangements of register blocks in FIG. 4. As illustrated in FIG. 5(a), the ring bank 304 is configured of m banks RB.sub.0, RB.sub.1, RB.sub.2, . . . and RB.sub.m-1, each of which is composed of l registers R.sub.0, R.sub.1, R.sub.2, . . . R.sub.l-1. Here, RB.sub.x at numeral 351 denotes any desired one of the banks, and numeral 352 denotes the register block in the bank.
As illustrated in FIG. 5(b), the global bank set 305 is configured of n global banks GB.sub.0, GB.sub.1, GB.sub.2, . . . and GB.sub.n-1, each of which is composed of k registers R.sub.0 ', R.sub.1 ', R.sub.2 ', . . . and R.sub.k-1 '. Here GB.sub.y at numeral 353 denotes any desired one of the banks, and numeral 354 denotes the register block in the global bank.
As instructions pertaining to the call of a subprogram, an advance ring bank instruction and a retrieve ring bank instruction exist besides a call instruction and a return instruction. At the subprogram call, information to be delivered as an argument is set in the register of a current bank, whereupon information called a save indicator vector as shown at numeral 429 in FIG. 8 is set in the 0th register 440 of the current bank 439, namely, a bank indicated by the current bank pointer 312. The save indicator vector 429 is information having a length of l bits where l denotes the number of registers in each bank. Letting i denote an integer value from 0 to (l-1), the value of the i-th bit b.sub.i at numeral 433 in the save indicator vector 429 is "1" if the content of the i-th register R.sub.i at numeral 443 in the current bank 439 is to be saved, and the value is "0" if the content need not be saved. The 0th bit b.sub.0 at numeral 430 is always set to "1." When the call instruction is executed after setting the save indicator vector in the 0th register R.sub.0 440 of the current bank, an address next to the instruction is stacked in a stack for subprogram reference, and the execution of the instruction queue of the designated subprogram is started.
At the head of the instruction sequence of the subprogram, the advance ring bank instruction is executed. When the advance ring bank instruction is executed, the values of the current bank pointer (CBNR) 312 and the previous bank pointer (PBNR) 311 in FIG. 4 advance, and if necessary, also the values of the valid bank pointer (VBNR) 313 and the bank stack pointer (BSP) 324 change. Hereinbelow, the functions of the advance ring bank instruction will be elucidated using symbols CBNR.sub.1, PBNR.sub.1, VBNR.sub.1 and BSP.sub.1 which denote the values of the four pointers before the execution of the advance ring bank instruction, respectively, and symbols CBNR.sub.2, PBNR.sub.2, VBNR.sub.2 and BSP.sub.2 which denote the values of the four pointers after the execution of the advance ring bank instruction, respectively. In executing the advance ring bank instruction, first of all, the value CBNR.sub.1 which indicates the current bank before the execution of this instruction is set as the value PBNR.sub.2 of the previous bank pointer after the execution of the instruction, and the value of the current bank pointer is updated to a value mod(CBNR.sub.1 +1, m). Here, the mod(a, b) denotes a remainder obtained by dividing an integer a by an integer b, and m denotes the number of registers within one bank. On this occasion, if CBNR.sub.1 =VBNR.sub.1 holds, that is, if the value of the current bank pointer before the updating is equal to that of the valid bank pointer before the updating, then among the registers of a bank indicated by the value CBNR.sub.2 of each current bank pointer after the updating, the register indicated by the save indicator vector contained in the 0th register of the indicated bank has its content selectively saved in a place indicated by the bank stack pointer BSP.sub.1.
Further, the mechanism of this bank saving will be detailed with reference to FIG. 8. In the bank 439 indicated by the current bank pointer CBNR.sub.2 after the updating, there are l registers; the 0th register R.sub.0 440, the first register R.sub.1 441, the second register R.sub.2 442, . . . and the (l-1)-th register R.sub.l-1 444. Also in the save indicator vector 429, there are l bits; the 0th bit b.sub.0 430, the first bit b.sub.1 431, the second bit b.sub.2 432, . . . and the (l-1)-th bit b.sub.l-1 434. If, for 0≦i≦l-1, the content of the i-th register 443 is to be saved, the i-th bit b.sub.i 433 of the save indicator vector is set at "1" beforehand, and if the content need not be saved, the bit b.sub.i is set at "0." This save indicator vector 429 is stored in the 0th register R.sub.0 440 of the bank 439. If the value CBNR.sub.1 of the current bank pointer before the updating, namely, the value PBNR.sub.2 of the previous bank pointer after the updating is equal to the value VBNR.sub.1 of the valid bank pointer before the updating, then the save indicator vector 429 which is stored in the 0th register R.sub.0 440 of the new current bank 439 indicated by the value CBNR.sub.2 of the current bank pointer after the updating is scanned in a direction from the bit b.sub.l-1 434 toward the bit b.sub.0 430. If the bit b.sub.i for 0≦i≦(l-1) is "1", the value of the bank stack pointer (BSP) 324 is advanced in the amount of one register, and the content of the register R.sub.i is stored in a position indicated by the new value of the bank stack pointer in the bank stack 325. If the bit b.sub.i is "0" , the bank stack pointer 324 is not advanced, and the store of the register R.sub.i is not executed, either. The value of the bank stack pointer 324 at the time at which the save indicator vector 429 has been scanned while changing i to l-1, l-2, . . . , 2, 1 and 0 and the necessary register store operations have been repeated, is the value BSP.sub.2 updated by the advance ring bank instruction. Since the 0th bit b.sub.0 of the save indicator vector is always set at "1", the value of the register R.sub.0 of the saved bank is stored in a position indicated by the bank stack pointer after the updating, namely, the uppermost part of the bank stack 325.
In returning from the subprogram, a function value or the like to be given back to a calling side is set in the register of the current bank if it is necessary, and thereafter the retract ring bank instruction is executed, followed by the execution of the return instruction. When the retrieve ring bank instruction is executed, the values of the current bank pointer CBNR 312 and the previous bank pointer PBNR 311 retract, and the values of the valid bank pointer VBNR 313 and the bank stack pointer BSP 324 change if it is necessary. Hereinbelow, the functions of the retract ring bank instruction will be elucidated using symbols CBNR.sub.3, PBNR.sub.3, VBNR.sub.3 and BSP.sub.3 which denote the values of the four pointers before the execution of this instruction, respectively, and symbols CBNR.sub.4, PBNR.sub.4, VBNR.sub.4 and BSP.sub.4 which denote the values of the four pointers after the execution of the instruction, respectively.
The mechanism of this bank restoration will be described with reference to FIG. 8. First, the content of the uppermost part of the bank stack 325 indicated by the value BSP.sub.3 of the bank stack pointer 324 before the updating is put in the 0th register R.sub.0 of a bank indicated by the value PBNR.sub.4 of the previous bank pointer 311 after the updating, and the value of the bank stack pointer 324 is retracted in the amount of one register. In the uppermost part of the bank stack 325, the save indicator vector has been faced at the time of the subprogram call. With the above operations, therefore, the save indicator vector 429 is put in the R.sub.0 register 440. Subsequently, the content of the save indicator vector 429 is scanned in a direction from the b.sub.i bit 431 toward the b.sub.l-1 bit 434. If the value of the b.sub.i bit 433 for 1≦i≦l-1 is "1," the data of a position indicated by the new value of the bank stack pointer 324 within the bank stack 325 is transferred to the R.sub.i register 443, and the value of the bank stack pointer 324 is retracted in the amount of one register. If the value of the b.sub.i bit is "0," the transfer to the R.sub.i register 443 is not performed, and the bank stack pointer 324 is not retracted, either. The value of the bank stack pointer 324 obtained as the result of repeating these operations (l-1) times while changing i to 1, 2, 3, . . . and l-1, is the value BSP.sub.4 thereof after the updating by the retract ring bank instruction. Thereafter, the value of the valid bank pointer 313 is retracted by one. That is, VBNR.sub.4 =mod(VBNR.sub.3 -1, m) is established. This value is the same as the value of the previous bank pointer after the updating.
FIG. 9 is an arrangement diagram of the essential portions of an information processing apparatus showing the fourth practicable example based on the construction as shown in FIG. 4. In this example, a register block 503 in an instruction processor 501 is configured of n global banks GB.sub.0 at numeral 510, GB.sub.1 at numeral 511, . . . and GB.sub.n-1 at numeral 513, and n ring banks R.sub.0 at numeral 520, R.sub.1 at numeral 521, . . . and R.sub.n-1 at numeral 523 Each of the global banks GB.sub.0, GB.sub.1, . . . and GB.sub.n-1 is composed of k' registers as shown in FIG. 5(b). As shown in FIG. 5(a), each of the ring banks R.sub.0, R.sub.1, . . . and R.sub.n-1 is composed of m banks, each of which is composed of l registers.
In the RISC I, there are bank of 32 logical registers which can be assigned by instructions, and a total of 138 physical registers exist. Letting L.sub.0, L.sub.1, . . . and L.sub.31 denote the logical registers to be assigned by the instructions, and letting R.sub.0, R.sub.1, . . . and R.sub.137 denote the physical registers, the registers L.sub.0, L.sub.1, . . . and L.sub.9 correspond respectively to registers R.sub.0, R.sub.1, . . . and R.sub.9 at all times. The registers L.sub.10, L.sub.11, . . . and L.sub.31 are respectively held in correspondence with registers R.sub.116, R.sub.117, . . . and R.sub.137 at the time of initialization. However, they are respectively brought into correspondence with the registers R.sub.100, R.sub.101, . . . and R.sub.121 after the call of the first subprogram, and with the registers R.sub.84, R.sub.85, . . . and R.sub.105 after the call of a subprogram directly below the level of the first subprogram. In this manner, the correspondence of the registers is shifted downwards or advanced by 16 registers in conformity with the nest level of the subprogram call. At the time of return from a subprogram, the correspondence is brought back upwards or retracted by 16 registers. The logical registers L.sub.26, L.sub.27, . . . and L.sub.31 before the subprogram call indicate the same physical registers as those corresponding to the registers L.sub.10, L.sub.11, . . . and L.sub.15 after the subprogram call, respectively.
Furthermore, in a case where one ring bank is provided in which banks each including l.sub.0 registers are grouped in m banks and where one set of global banks is configured of n banks, the respective global banks being constructed of l.sub.1, l.sub.2, . . . and l.sub.n registers, registers numbering l.sub.0 whole. In this case, the maximum number of registers l.sub.0, l.sub.1, l.sub.2, . . . l.sub.n can be assigned by the register displacement part of the instruction. Each bank of the ring bank is used in a form allocated to the corresponding one of the nest levels of the nested subprogram calls, while each global bank is used in a form allocated to the corresponding one of the tasks which are executed asynchronously. More specifically, as regards the ring bank, when the nest level of the subprogram call deepens by one, a bank at the next position in terms of the ring-shaped position is used as a current bank, and a bank having been used as a current bank till then is set as a previous bank. When the nest level shallows by one owing to the return from a subprogram, the ring-shaped position retracts by one to set a previous bank as a current bank, and a bank at the preceding position in terms of the ring-shaped position is set as a new previous bank. The global bank can have the allocation varied at the task switch, but in calling and returning a subprogram within an identical task, the allocation is held invariable and the content is not automatically saved and restored. One of the global banks is fixedly used by a system task for handling interruption etc., and that global bank shall be called the "system bank."
In a case where the position of a register is expressed as a register address of a binary number, where the number in registers of each register area is made the power of 2 and where the value of an area register is set to be an integral times the power of 2, the position of the register to be actually used can be generated by an OR circuit on the basis of the value of the area register therefore, its a value specified in a register displacement part, and processing can be increased in speed. In a case where register positions are expressed by binary numbers from 0 to 2.sup.p -1, the succeeding register and preceding register of a register of register address i can be readily calculated as registers having register addresses mod(i+1, 2.sup.p) and mod(i-1, 2.sup.p), respectively. When, in a ring bank prepared by grouping 2.sup.r register banks each of which consists of 2.sup.q registers, the value of a bank control pointer is set to be an integral times as large as 2.sup.q, the succeeding bank and preceding bank of a bank beginning with an address i readily calculated as banks having head register addresses mod((i+1) 2.sup.p+q), respectively.
In a case where the numbers of registers of the respective global banks of a global bank set are identical to a fixed number l.sub.1, where the numbers of banks of respective ring banks are identical to a fixed number m and where the numbers of registers included in the respective banks of the ring bank are identical to a fixed number l.sub.0, one program can be run whichever global bank or ring bank is selected.
In the information processing apparatus of the present invention, the value of an area register is set in a part preceding the execution of an instruction using general registers, such as in the head part of one program or subprogram. In a case where a register area for use is changed according to the kind of information to be handled, different area registers may be used for the individual kinds of information. When an instruction having an area register part i and a register displacement part d comes under the condition that the value of an area register i is set at A.sub.i, the address of a register which is actually used by the instruction becomes A.sub.i +d. In case of synthesizing a register address by means of an OR circuit on the basis of the value of an area register and a register displacement value, a program is drawn up so that a register displacement value may be restricted to a numerical value which can be expressed by at most l' bits, l' denoting a number smaller than the bit length of a register displacement part, and that the value of the area register may be restricted to a numerical value the lower l' bits of which are O's. Then, a synthesized value in the OR circuit becomes equal to an added value in an adder, so that no malfunction occurs.
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