Source: https://patents.justia.com/patent/6835954
Timestamp: 2019-11-11 22:21:40
Document Index: 99743469

Matched Legal Cases: ['art 372', 'art 373', 'art 374', 'art 372', 'art 373', 'art 374', 'art 372', 'art 373', 'art 374']

US Patent for Active matrix organic electroluminescent display device Patent (Patent # 6,835,954 issued December 28, 2004) - Justia Patents Search
Justia Patents In Array Having Structure For Use As Imager Or Display, Or With Transparent ElectrodeUS Patent for Active matrix organic electroluminescent display device Patent (Patent # 6,835,954)
In addition, because the organic electroluminescence display (ELD) device is a self-luminescent, it has a high contrast ratio and is suitable for an ultra-thin type display device. Moreover, because it has a simple manufacturing process, the degree of environmental contamination is relatively low. Besides, the organic electroluminescence display (ELD) device has a few microseconds (&mgr;s) response time so that it is suitable for displaying moving images. The organic electroluminescence display (ELD) device has no limit in a viewing angle and is stable in low temperature condition. Because it is driven with a relatively low voltage between 5V and 15V, a manufacturing and design of a driving circuit is easy.
In FIG. 2, a buffer layer 11 is formed on a substrate, and then a first polycrystalline silicon layer having first to third portions 12a, 12b and 12c and a second polycrystalline silicon layer 13a are formed on the buffer layer 11. The first polycrystalline silicon layer is divided into the first portion 12a (i.e., an active region) where impurities are not doped and the second and third portions 12b and 12c (i.e., respectively, a drain region and a source region) where the impurities are doped. The second polycrystalline silicon layer 13a becomes one of the capacitor electrodes. A gate insulation layer 14 is disposed on the active region 12a and a gate electrode 15 is disposed on the gate insulation layer 14. A first interlayer insulator 16 is formed on the gate electrode 15 and on the gate insulation layer 14 while covering the drain and source regions 12b and 12c and the second polycrystalline silicon layer 13a. A power line 17 is disposed on the first interlayer insulator 16 particularly above the second polycrystalline silicon layer 13a (i.e., the capacitor electrode). Although not shown in FIG. 2, the power line 17 extends as a line in one direction. The power line 17 and the second polycrystalline silicon layer 13a form a storage capacitor with the first interlayer insulator 16 therebetween. On the first interlayer insulator 16, a second interlayer insulator 18 is formed while covering the power line 17.
Meanwhile, first and second contact holes 18a and 18b, which penetrate both the first and second interlayer insulators 16 and 18, expose the drain region 12b and source region 12c, respectively. Additionally, a third contact hole 18c, which penetrates the second interlayer insulator 18, is formed and exposes a portion of the power line 17. A drain electrode 19a and a source electrode 19b are formed on the second interlayer insulator 18. The drain electrode 19a contacts the drain region 12b through the first contact hole 18a. The source electrode 19b contacts both the source region 12c and the power line 17 through the second contact hole 18b and through the third contact hole 18c, respectively. A first passivation layer 20 is formed on the drain and source electrodes 19a and 19b and on the exposed portions of the second interlayer insulator 18. The first passivation layer 20 has a fourth contact hole 20a that exposes a portion of the drain electrode 19a. An anode electrode 21 that is made of a transparent conductive material is disposed on the first passivation layer 20 and contacts the drain electrode 19a through the fourth contact hole 20a. A second passivation layer 22 is formed on the anode electrode 21 and on the exposed portions of the first passivation layer 20. The second passivation layer 22 has a well 22a that exposes a portion of the anode electrode 21. An electroluminescent layer 23 is formed on the second passivation layer 22 and into the well 22a. A cathode electrode 24 is formed entirely on the exposed portions of the second passivation layer 22 and on the electroluminescent layer 23. The cathode electrode 24 is formed of an opaque metallic conductive material.
In FIG. 3B, an insulator of silicon nitride or silicon oxide and a conductive material of metal are sequentially deposited on the first polycrystalline silicon layer 12 and then patterned using a second mask, thereby sequentially forming a gate insulation layer 12 and a gate electrode 15 on the first polycrystalline semiconductor layer 12. Thereafter, impurities such as p-type ions are doped on the exposed portions of the first and second polycrystalline semiconductor layers 12 and 13. During doping, since the gate electrode 15 acts as a mask, the first polycrystalline semiconductor layer 12 is divided into an active region 12a where the impurities are not doped and drain and source regions 12b and 12c where the impurities are doped. Further, the second polycrystalline semiconductor layer 13 on which the impurities are fully doped becomes a capacitor electrode 13a. The drain and source regions 12b and 12c are located on both sides of the active region 12a.
Referring to FIG. 3C, a first interlayer insulator 16 is formed on the entire surface of the buffer layer 11 to cover the gate electrode 15, the drain and source regions 12b and 12c, and the capacitor electrode 13a. After forming the first interlayer insulator 16 over the entire surface of the substrate 10, a power line 17 of metal is formed through a third mask process on the first interlayer insulator 16 particularly to overlap the capacitor electrode 13a. Since the power line 17 is formed right above the capacitor electrode 13a, it forms a storage capacitor with the capacitor electrode 13a and with the interposed first interlayer insulator 16.
In FIG. 3D, a second interlayer insulator 18 is formed on the first interlayer insulator 16 and on the power line 17. Thereafter, first to third contact holes 18a, 18b and 18c are formed using a fourth mask process. The first contact hole 18a exposes the drain region 12b; the second contact hole 18b exposes the source region 12c; and the third contact hole 18c exposes the power line 17.
In FIG. 3E, a metal layer is formed on the second passivation layer 18 and then patterned through a fifth mask process, thereby forming a drain electrode 19a and a source electrode 19b. The drain electrode 19a contacts the drain region 12b through the first contact hole 18a, while the source electrode 19b contacts the source region 12c through the second contact hole 18b. Furthermore, the source electrode 19b contacts the power line 17 through the third contact hole 18c.
Through the previous process, a driving thin film transistor having the semiconductor layer 12, the gate electrode 15, the drain and source electrodes 19a and 19b is completed. Moreover, a region corresponding to the power line 17 and the capacitor electrode 13a forms the storage capacitor. Although not shown in FIG. 3E, but shown in FIG. 1, the storage electrode 13 is connected to the gate electrode 15 of the driving thin film transistor and the power line 17 is parallel to the signal line.
In FIG. 3F, a first passivation layer 20 having a fourth contact hole 20a resulting from a sixth mask process is formed on the second interlayer insulator while covering the drain and source electrodes 19a and 19b. The fourth contact hole 20a exposes a portion of the drain electrode 19a.
In FIG. 3G, a transparent conductive material is deposited on the first passivation layer 20 and then patterned using a seventh mask process, thereby forming an anode electrode 21 that contacts the drain electrode 19a through the fourth contact hole 20a.
In FIG. 3H, a second passivation layer 22 is formed on the anode electrode 21 and on the exposed portion of the first passivation layer 20. Thereafter, the second passivation layer 22 is patterned using an eighth mask process, thereby forming a well 22a that exposes a portion of the anode electrode 21.
Now in FIG. 3I, an organic electroluminescent layer 23 is formed on the second passivation layer to contact the anode electrode 21 through the well 22a. Thereafter, a cathode electrode 24 is formed on the organic electroluminescent layer 23 and on the exposed portion of the second passivation layer 22. The cathode electrode 24 entirely covers the substrate 10.
Meanwhile, first and second contact holes 361 and 362, which penetrate both the interlayer insulator 360 and the gate insulation layer 340, are formed to expose the drain region 332 and source region 333, respectively. Additionally, third and fourth contact holes 363 and 364, which penetrate the interlayer insulator 360, gate insulation layer 340 and buffer layer 330, are formed with the first and second contact holes 361 and 362 to expose portions of the ground layer 320. A cathode electrode 371, a drain electrode 372, a source electrode 373 and a second capacitor electrode 374 are formed on the interlayer insulator 360. The cathode electrode 371 has a single-layered structure, while the drain electrode 372, the source electrode 373 and the second capacitor electrode 374 may have a double-layered structure. The cathode electrode 371 is made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), for example. Further, the lower part 372a of the drain electrode 372, the lower part 373a of the source electrode 373 and the lower part 374a of the second capacitor electrode 374 are also made of the transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO). On the contrary, the upper part 372b of the drain electrode 372, the upper part 373b of the source electrode 373 and the upper part 374b of the second capacitor electrode 374 are made of an opaque conductive material, such as metal, for example. The cathode electrode 371 is connected to the lower part 372a of the double-layered drain electrode 372, which contacts the drain region 332 through the first contact hole 361. The lower part 373a of the source electrode 373 contacts both the drain region 333 and the ground layer 320 through the second contact hole 362 and through the third contact hole 363, respectively. The lower part 374a of the second capacitor electrode 374 contacts the ground line 320 through the fourth contact hole 364. The first and second capacitor electrodes 352 and 374 with the interposed interlayer insulator 360 form a storage capacitor.
Therefore, to overcome this problem of thermal or light energy dispersion, another embodiment of the present invention provides a ground layer that has a plurality of openings each corresponding in position to the semiconductor layer. The ground layer having the plurality of openings is illustrated in FIG. 10. The ground layer 421 has the plurality of openings 421a therein in a row-and-column formation. Each opening 421a corresponds to the thin film transistor, especially to the semiconductor layer having the active, drain and source regions. When using the ground layer 421 of FIG. 10, the semiconductor layer of polycrystalline silicon can have the large grains.
FIG. 11 is a photo showing the polycrystalline silicon layer that is formed above the ground layer shown in FIG. 10. Due to the opening 421a of the ground layer 421, the amorphous silicon is not deprived of the thermal or light energy when the amorphous silicon is crystallized. Thus, the grains of polycrystalline semiconductor layer become larger, as shown in FIG. 11. The thin film transistor having this large-sized polycrystalline silicon semiconductor layer can have the good electrical properties and characteristics.
a ground layer on the substrate;
a buffer layer on the ground layer;
a polycrystalline semiconductor layer on the buffer layer,
the polycrystalline semiconductor layer having an active region, a drain region and a source region, wherein the active region is disposed in the middle of the polycrystalline silicon layer and the drain and source regions are disposed to both sides of the active region;
a gate insulation layer on the buffer layer to cover the polycrystalline silicon layer;
a gate electrode on the gate insulation layer, the gate electrode above the active region of the polycrystalline silicon layer;
a first capacitor electrode on the gate insulation layer;
an interlayer insulator made of an organic material on the gate insulation layer covering the gate electrode and the first capacitor electrode;
drain and source electrodes on the interlayer insulator, the drain and source electrodes contacting the drain and source regions through first and second contact holes that penetrate the interlayer insulator and the gate insulation layer, respectively
a cathode electrode on the interlayer insulator and connected to the drain electrode;
a second capacitor electrode on the interlayer insulator, the second capacitor electrode being electrically connected to the ground layer;
a passivation layer on the interlayer insulator covering the drain and source electrodes, the cathode electrode and the second capacitor electrode, the passivation layer having a well that exposes the cathode electrode;
an organic electroluminescent layer on the passivation layer and into the well, the organic electroluminescent layer contacting the cathode electrode through the well; and
an anode electrode on the exposed portion of the passivation layer and on the organic electroluminescent layer.
2. The device according to claim 1, wherein the gate electrode is electrically connected to the first capacitor electrode.
6696105 February 24, 2004 Hiroki et al.
2001-267086 September 2001 JP
Patent number: 6835954
Patent Publication Number: 20030127652
Inventors: Jae-Yong Park (Annyang-si), Joon-Kyu Park (Seoul)
Application Number: 10/330,128
Current U.S. Class: In Array Having Structure For Use As Imager Or Display, Or With Transparent Electrode (257/72); In Array Having Structure For Use As Imager Or Display, Or With Transparent Electrode (257/59); Field Effect Device In Amorphous Semiconductor Material (257/57)
International Classification: H01L/2915; H01L/2904;