Source: http://patents.com/us-9489285.html
Timestamp: 2018-11-21 02:42:05
Document Index: 604099577

Matched Legal Cases: ['Application No. 12762008', 'Application No. 13760362', 'Application No. 13761389', 'Application No. 13760760', 'Application No. 13760324', 'Application No. 13761271', 'Application No. 13760503', 'Application No. 13760531', 'Application No. 13761846', 'Application No. 201380014676']

US Patent # 9,489,285. Modifying run-time-instrumentation controls from a lesser-privileged state - Patents.com
United States Patent 9,489,285
Farrell , et al. November 8, 2016
Farrell; Mark S. (Pleasant Valley, NY), Gainey, Jr.; Charles W. (Poughkeepsie, NY), Shum; Chung-Lung K. (Wappingers Falls, NY), Slegel; Timothy J. (Staatsburg, NY)
Family ID: 1000002217907
13/792,283
US 20130247014 A1 Sep 19, 2013
13422598 Mar 16, 2012
Current CPC Class: G06F 11/3644 (20130101); G06F 9/30076 (20130101); G06F 9/30101 (20130101); G06F 11/3636 (20130101); G06F 11/3648 (20130101)
Current International Class: G06F 11/36 (20060101); G06F 9/30 (20060101)
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1. A computer implemented method for executing a modifying run-time-instrumentation controls (MRIC) instruction from either a supervisor state or a lesser-privileged state, the MRIC instruction for setting only a subset of run-time-instrumentation controls, wherein all of said run-time-instrumentation controls are loadable by a privileged load run-time-instrumentation controls (LRIC) instruction, the method comprising: fetching the MRIC instruction, the MRIC instruction including an address of a run-time-instrumentation control block (RICCB); fetching, by a processor, the RICCB, the RICCB including a plurality of values for modifying said subset of run-time-instrumentation controls of the processor, the plurality of values of the RICCB comprising: a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location, the RIB for holding runtime instrumentation information of events recognized by the processor during program execution; and one or more of: a control to manage details of run-time-instrumentation data sampling; a control to manage details of run-time-instrumentation data collection; a control to manage details of run-time-instrumentation data reporting into a program buffer; a control to manage detection of instruction-cache misses; a control to manage detection of data-cache misses; a control to manage a size of a reporting group; a control to manage a current address within an output program buffer at which a next reporting group is stored; controls to manage data collection of data on call-type, return-type, and transfer-type branches; and controls to manage data collection of branches that are correctly or incorrectly predicted as taken or not taken; loading the plurality of values into the run-time-instrumentation controls; and using the loaded plurality of values to provide run-time-instrumentation event information to the RIB.
3. The method according to claim 2, wherein based on one of the plurality of values of the RICCB being the control to manage a size of a reporting group, the method further comprises: loading the model dependent limited value; based on a K field of the run-time-instrumentation controls having a first value, setting a current address to a value of an origin address of the RICCB; and based on the K field run-time-instrumentation controls having a second value, setting the current address to a value of a specified RICCB current address value.
6. The method according to claim 1, wherein the MRIC instruction is defined for a first computer architecture, and the fetching and parsing is executed by a second processor of an alternate computer architecture, the fetching and parsing by the second processor comprising: identifying a software routine for emulating execution of the MRIC instruction on the first computer architecture; and executing the MRIC instruction with the software routine.
In a mainframe, architected machine instructions are used by programmers, usually today "C" programmers often by way of a compiler application. These instructions stored in the storage medium may be executed natively in a z/Architecture IBM Server, or alternatively in machines executing other architectures. They can be emulated in the existing and in future IBM mainframe servers and on other machines of IBM (e.g. pSeries.RTM. Servers and xSeries.RTM. Servers). They can be executed in machines running Linux on a wide variety of machines using hardware manufactured by IBM.RTM., Intel.RTM., AMD.TM., Sun Microsystems and others. Besides execution on that hardware under a Z/Architecture.RTM., Linux can be used as well as machines which use emulation by Hercules, UMX, Fundamental Software, Inc. (FSI) or Platform Solutions, Inc. (PSI), where generally execution is in an emulation mode. In emulation mode, emulation software is executed by a native processor to emulate the architecture of an emulated processor.
One or more of the components of the emulated host computer system 21 are further described in "IBM.RTM. z/Architecture Principles of Operation," Publication No. SA22-7932-08, 9th Edition, August, 2010 which is hereby incorporated herein by reference in its entirety. IBM is a registered trademark of International Business Machines Corporation, Armonk, N.Y., USA. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.
A specific instruction being emulated is decoded, and a subroutine called to perform the function of the individual instruction. An emulation software function emulating a function of an emulated processor 29 is implemented, for example, in a "C" subroutine or driver, or some other method of providing a driver for the specific hardware as will be within the skill of those in the art after understanding the description of the preferred embodiment.
Alternatively, the program code may be embodied in the computer memory 2, and accessed by the processor 1 using a processor bus (not shown). Such program code includes an operating system which controls the function and interaction of the various computer components and one or more application programs. Program code is normally paged from a dense media such as the storage device 11 to computer memory 2 where it is available for processing by the processor 1. The techniques and methods for embodying software program code in memory, on physical media, and/or distributing software code via networks are well known and will not be further discussed herein. Program code, when created and stored on a tangible medium (including but not limited to electronic memory modules (RAM), flash memory, compact discs (CDs), DVDs, Magnetic Tape and the like is often referred to as a "computer program product." The computer program product medium is typically readable by a processing circuit preferably in a computer system for execution by the processing circuit.
Programming code 111 may be embodied in the memory 105, and accessed by the processor 106 using the processor bus. Such programming code includes an operating system which controls the function and interaction of the various computer components and one or more application programs 112. Program code is normally paged from long-term storage 107 to high-speed memory 105 where it is available for processing by the processor 106. The techniques and methods for embodying software programming code in memory, on physical media, and/or distributing software code via networks are well known and will not be further discussed herein. Program code, when created and stored on a tangible medium (including but not limited to electronic memory modules (RAM), flash memory, Compact Discs (CDs), DVDs, Magnetic Tape and the like is often referred to as a "computer program product". The computer program product medium is typically readable by a processing circuit preferably in a computer system for execution by the processing circuit.
Still referring to FIG. 2, the networks may also include mainframe computers or servers, such as a gateway computer (client server) 206 or application server (remote server) 208 which may access a data repository and may also be accessed directly from a workstation 205. A gateway computer 206 serves as a point of entry into each network 207. A gateway is needed when connecting one networking protocol to another. The gateway computer 206 may be preferably coupled to another network (the Internet 207 for example) by means of a communications link. The gateway computer 206 may also be directly coupled to the one or more workstations 101, 201, 202, 203, and 204 using a communications link. The gateway computer may be implemented utilizing an IBM eServer.TM. zSeries.RTM. z9.RTM. Server available from International Business Machines Corporation.
Referring to FIG. 3, an exemplary processor embodiment is depicted for processor 106. One or more levels of cache 303 are employed to buffer memory blocks in order to improve the performance of the processor 106. The cache 303 is a high speed buffer holding cache lines of memory data that are likely to be used. Typical cache lines are 64, 128 or 256 bytes of memory data. In an embodiment, separate caches are employed for caching instructions than for caching data. Cache coherence (synchronization of copies of lines in memory and the caches) is often provided by various "snoop" algorithms well known in the art. Main storage, such as memory 105 of a processor system is often referred to as a cache. In a processor system having 4 levels of cache 303 memory 105 is sometimes referred to as the level 5 (L5) cache since it is typically faster and only holds a portion of the non-volatile storage (DASD, Tape etc) that is available to a computer system. Memory 105 "caches" pages of data paged in and out of the memory 105 by the operating system.
In an embodiment, an instruction fetch unit 305 is employed to fetch instructions on behalf of the processor 106. The instruction fetch unit 305 either fetches the "next sequential instructions," the target instructions of branch taken instructions, or the first instructions of a program following a context switch. In an embodiment, the instruction fetch unit 305 employs prefetch techniques to speculatively prefetch instructions based on the likelihood that the prefetched instructions might be used. For example, the instruction fetch unit 305 may fetch 16 bytes of instructions that include the next sequential instruction and additional bytes of further sequential instructions.
Preferably addresses that an application program "sees" are often referred to as virtual addresses. Virtual addresses are sometimes referred to as "logical addresses" and "effective addresses." These virtual addresses are virtual in that they are redirected to physical memory location by one of a variety of DAT technologies such as the DAT 312 of FIG. 3, including, but not limited to prefixing a virtual address with an offset value, translating the virtual address via one or more translation tables, the translation tables including at least a segment table and a page table alone or in combination, preferably, the segment table having an entry pointing to the page table. In z/Architecture, a hierarchy of translations is provided including a region first table, a region second table, a region third table, a segment table and an optional page table. The performance of the address translation is often improved by utilizing a translation look-aside buffer (TLB) which comprises entries mapping a virtual address to an associated physical memory location. The entries are created when DAT 312 translates a virtual address using the translation tables. Subsequent use of the virtual address can then utilize the entry of the fast TLB rather than the slow sequential translation table accesses. The TLB content may be managed by a variety of replacement algorithms including least recently used (LRU).
In the case where the processor 106 is a processor of a multi-processor system, each processor has responsibility to keep shared resources such as I/O, caches, TLBs and Memory interlocked for coherency. In an embodiment, "snoop" technologies will be utilized in maintaining cache coherency. In a snoop environment, each cache line may be marked as being in any one of a shared state, an exclusive state, a changed state, an invalid state and the like in order to facilitate sharing.
The one or more applications 518 include software applications compiled to execute on a specific operating system, interpreted code executing on an interpreter (e.g., Java.TM.), or operating system support threads (e.g., process management, daemons, etc.). Each of the one or more operating systems 516 and or the one or more applications 518 may execute an instruction to trigger the instrumentation module 506 to start, or to stop, the collecting instrumentation data.
FIG. 6 depicts an MRIC instruction in an embodiment. In an embodiment, the MRIC instruction 600 includes an operation code 602 and 604 (also referred to as "opcode" or "split opcode" in this particular case). The opcode 602 and 604 identifies the MRIC instruction 600 to the processor, such as the processor 106 of FIG. 5. The MRIC instruction 600 also includes an operand address which is determined from a base register field 606 (B.sub.2), and a set of displacement fields 608 and 610, taken together. The sum of the contents of the base register plus the displacement indicates the location of a run-time-instrumentation controls control block (RICCB) that includes the run-time-instrumentation control settings that will be updated by the MRIC instruction. The displacement fields 608 and 610 indicate a displacement from the address contained in the base register indicated by the base register field 606 whose summation lines up with the RICCB. FIG. 6 depicts an embodiment of the MRIC instruction for purposes of clarity. It will be understood by those of ordinary skill in the art that the MRIC instruction may be formatted differently and/or contain different operands and opcodes in other embodiments.
The SF field 1040 contains a 64-bit unsigned integer whose value is a scaling factor count of units. The dimension of the units is determined from the sampling mode field 1008 (M field). When the value in the RSIC field 1042 is zero, the SF field 1040 provides an initial value of the RSIC field 1042 that is decremented to zero at which point the current instruction is recognized as a sample instruction, and the interval count is refreshed from the SF field 1040 value. A valid value of the SF field 1040 is in the range one to 2.sup.64-1. If zero is specified, a value of one is assumed. However, each model may have both a minimum and a maximum value of the SF field 1040. The minimum and maximum values may also be different based on the sampling mode field 1008. If a value less than the minimum is specified, the model-dependent minimum value is loaded. If a value greater than the maximum value is specified, the model-dependent maximum value is loaded.
The reporting group size field 1044 (RGS) is a 3-bit unsigned integer whose value specifies the number of records of a reporting group (RRG). The number of records in a reporting group may vary from two records, including a begin/timestamp record and an instruction last record, up to two hundred fifty-six records. In an embodiment, the upper limit may be model dependent. The number of 16-byte records placed into a reporting group is 2.sup.(RGS+1).
The collection buffer 508 may be referred to as a "hardware collection buffer" because the collection buffer 508 is located in the processor and in an embodiment implemented as an array of register pairs for storing an instruction address and event metadata for a given event. An example of an event is a taken branch for which the register pair may hold the instruction address of the branch, and the metadata may hold the target of the branch as well as information regarding the historic behavior of the branch. In an embodiment, the register pairs are ordered and updated sequentially as events occur in the instruction stream. A counter is maintained to indicate the index of the most recently updated entry in the array. In an embodiment the collection buffer 508 is a circular buffer, and when the collection buffer 508 is full, the next event overwrites the first entry in the array, and sequential updating of the array's register pairs re-starts on subsequent events. As such, assuming an array CB[0] to CB[N-1] and a counter i indicating the latest updated index, the trace of events captured would be represented by the sequence CB[i], CB[i-1] . . . CB[1], CB[0], CB[N-1], CB[N-2] . . . CB[i+1]. In another embodiment, two pointers are used: a head pointer pointing to the oldest entry in the buffer, and a tail/current pointer pointing to the newest entry in the buffer.
An embodiment of the collection buffer 508 stores up to thirty-two entries (i.e., information about thirty-two events), with each instruction address specified by sixty-four bits (e.g., bits 0:63), and event metadata by sixty-four bits (e.g., bits 64:127). The size of the collection buffer (RCB) is a model dependent count, representing a number of records. In an embodiment, the byte size of the collection buffer 508 is a multiple of a sixteen byte record size. The size of the collection buffer (RCB) is a number of records greater than or equal to the difference between the count of the largest reporting group (RRG) of the model and the count of the records in a reporting group that are not acquired from the collection buffer (RNC). Thus, in an embodiment, the size of the collection buffer is expressed as: RCB.gtoreq.(RRG-RNC).
In accordance with embodiments, other data collected may not be from the collection buffer 508 and not from the instruction-data buffer. Examples include data used to form parts of the following: (1) the first record of a reporting group: timestamp or begin record; and (2) additional types of records may be created for every reporting group and thus not stored in the collection buffer 508, such records, when present, may be placed in the extra or machine-dependent section of a reporting group. These records are referred to herein as "system information records."
FIG. 12 depicts a high-level example of a reporting group 1200 stored to program buffer 522 at a sample point. The size of a reporting group in records is represented by R.sub.RG, equals 2.sup.(RGS+1), where RGS is the reporting group size as an exponent. A model-dependent number of records (R.sub.NC) copied from a location other than the collection buffer 508 may or may not be copied non-destructively when used in a reporting group. In the example of FIG. 12, R.sub.RG=8, R.sub.GS=2, and R.sub.NC=4. The example reporting group 1200 shown in FIG. 12 includes a header section 1202, a body section 1204, an extra records section 1206, and a footer section 1208.
The header section 1202 may include a begin record or a timestamp record to hold status, tracking, and/or timing information. A begin record is stored in the header section 1202 for the first reporting group stored in a program buffer (i.e., when the RCA 1006 is equal to the ROA 1002). In an embodiment, the begin record includes a record type field of "02", a number of reporting groups (NRG) field for indicating how many reporting groups are currently stored in the program buffer, a RGS field to indicate the size of the reporting groups, a stopped (S) field for indicating whether or not the program buffer 522 is full, a halted (H) field for indicting whether the run-time instrumentation is halted, and a time of day (TOD) clock field for indicating when the begin record was written. In an embodiment, at least a subset of the fields in the begin record are sourced from the RI control block (e.g., RICCB). An embodiment of the timestamp record has a record type of "03" and includes a TOD clock field for indicating when the record was stored. In an embodiment, a timestamp record is stored in the header section 1202 for each reporting group other than the first reporting group.
In an embodiment, an emit record is created and stored in the collection buffer 508 upon a successful execution of a RIEMIT instruction. An embodiment of the emit record includes a record type field of "10", an instruction address code field to indicate how the instruction address bit positions of the current PSW are represented in the emit record, an instruction address field which varies depending on the addressing mode (e.g., 64, 31 or 24 bit) and contains the instruction address of the RIEMIT instruction or execute type instruction if the RIEMIT was the target of an execute type instruction, and an emit data field for storing the data from the general register specified by the RIEMIT instruction.
In an embodiment, a transactional execution mode abort record is created and stored in the collection buffer 508 by either an implicit abort or by execution of a transaction abort instruction. An embodiment of the abort record includes a record type field of "11", an instruction address code field to indicate how the instruction address bit positions of the current PSW are represented in the transactional-execution abort record, an instruction address field which varies depending on the addressing mode (e.g., 64, 31 or 24 bit) and contains the instruction address of the aborted instruction or execute type instruction if the aborted instruction was the target of an execute type instruction, and a field for any model dependent data associated with the abort.
In an embodiment, a call record is created by execution of a call type branch instruction, such as: BRANCH AND SAVE (BASR) when the R2 field is nonzero, BRANCH AND SAVE (BAS), BRANCH RELATIVE AND SAVE LONG, BRANCH RELATIVE AND SAVE, BRANCH AND LINK (BALR) when the R2 field is nonzero, BRANCH AND LINK (BAL), and BRANCH AND SAVE AND SET MODE when the R2 field is nonzero. An embodiment of the call record includes a record type field of "12", an instruction address code field to indicate how the instruction address bit positions of the current PSW are represented in the call record, an instruction address field which varies depending on the addressing mode (e.g., 64, 31 or 24 bit) and contains the address of the branch instruction or execute type instruction if the branch instruction was the target of an execute type instruction, and a well behaved field for indicating whether or not the branch was correctly predicted, and a target address field containing the branch target address (also referred to as the "called location").
Return records and transfer records may have the same format as the call records. In an embodiment, a return record has a record type field of "13" and is created by execution of a return type branch instruction such as a BRANCH ON CONDITION (BCR) when the R2 field is nonzero and the mask is 15. For the return record, the instruction address field contains the address of the branch instruction or execute type instruction if the branch is the target of an execute type instruction, and the target address field contains the return location.
In an embodiment, a transfer record has a record type field of "14" and is created by execution of a return type branch instruction such as: a. BRANCH ON CONDITION (BCR) when the R2 field is nonzero and the mask is in the range 1-14; b. BRANCH ON CONDITION (BC) when the J bit is zero or the mask is in the range 1-14; c. BRANCH ON COUNT (BCT, BCTR, BCTG, BCTGR); d. BRANCH ON INDEX HIGH (BXH, BXHG); e. BRANCH ON INDEX LOW OR EQUAL(BXLE, BXLEG); f. BRANCH RELATIVE ON CONDITION(BRC); g. BRANCH RELATIVE ON CONDITION LONG (BRCL); h. BRANCH RELATIVE ON COUNT (BRCT,BRCTG); i. BRANCH RELATIVE ON COUNT HIGH(BRCTH); j. BRANCH RELATIVE ON INDEX HIGH(BRXH, BRXHG); k. BRANCH RELATIVE ON INDEX LOW OR EQUAL (BRXLE, BRXLG); l. COMPARE AND BRANCH (CRB, CGRB); m. COMPARE AND BRANCH RELATIVE (CRJ,CGRJ); n. COMPARE IMMEDIATE AND BRANCH(CIB, CGIB); o. COMPARE IMMEDIATE AND BRANCH RELATIVE (CIJ, CGU); p. COMPARE LOGICAL AND BRANCH(CLRB, CLGRB); q. COMPARE LOGICAL AND BRANCH RELATIVE(CLRJ, CLGRJ); r. COMPARE LOGICAL IMMEDIATE AND BRANCH (CLIB, CLGIB); and s. COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (CLIJ, CLGIJ). The transfer record is created when the branch is taken. For the transfer record, the instruction address field contains the address of the branch instruction or execute type instruction if the branch is the target of an execute type instruction, and the target address field contains the return location.
A filler record is used in a reporting group when the number of valid records in the collection buffer 508 is not sufficient to fill a reporting group of the current RGS. An embodiment of a filler record includes record type field of "00" to indicate that the record is a filler record and the remaining bytes are undefined.
The extra records section 1206, when present, may contain model-dependent records. In an embodiment, the format of an extra record is similar to the filler record except for the record type is set to "01" to indicate that the record is an extra record and the remaining bytes of the extra record may contain model dependent data.
The footer section 1208 can include an instruction record containing information about execution of a sample instruction. An instruction record is created when a reporting group is stored for a sample instruction. An embodiment of the instruction record includes a record type field of "04", an instruction address code field to indicate how the instruction address bit positions of the current PSW are represented in the instruction record, an instruction address field which varies depending on the addressing mode (e.g., 64, 31 or 24 bit) and contains the instruction address of the sample instruction or execute type instruction if the sample instruction was the target of an execute type instruction, and an instruction-data buffer (IDB) field containing any model dependent data collected from the IDB.
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