Source: https://patents.google.com/patent/US6770535B2/en
Timestamp: 2018-06-23 04:51:17
Document Index: 774083656

Matched Legal Cases: ['arts 2', 'arts 2', 'arts 2', 'arts 2', 'arts 2', 'arts 2', 'arts 2']

US6770535B2 - Semiconductor integrated circuit device and process for manufacturing the same - Google Patents
Semiconductor integrated circuit device and process for manufacturing the same Download PDF
US6770535B2
US6770535B2 US09767830 US76783001A US6770535B2 US 6770535 B2 US6770535 B2 US 6770535B2 US 09767830 US09767830 US 09767830 US 76783001 A US76783001 A US 76783001A US 6770535 B2 US6770535 B2 US 6770535B2
US09767830
US20010025973A1 (en )
A reduction of the junction electric field intensity is accomplished in the semiconductor regions for the sources and drains of field effects transistors. For this purpose, a structure is provided where the gate electrodes 9 of the MIS.FETQs for memory cell selection of a DRAM are buried within the trenches 7 a and 7 b created in the semiconductor substrate 1. The bottom corners within the trench 7 b are rounded so as to have a radius of curvature in accordance with the sub-threshold coefficient of the MIS.FETQs for memory cell selection. In addition, the gate insulating film 8 within the trench 7 b is made to have a laminated structure of a thermal oxide film and a CVD film.
The present invention relates to a process for manufacture of a semiconductor integrated circuit device and to a semiconductor integrated circuit device technology. In particular, the invention relates to a process for manufacture of a semiconductor integrated circuit device having capacitor elements for information storage and to a technology which is effective in the application of such a semiconductor integrated circuit device.
The present inventors have, however, found that the above described technologies have the following problems.
FIG. 1 is a cross-sectional view of the main part of a semiconductor integrated circuit device during processing according to one embodiment of the present invention;
In the following, the embodiments of the present invention will be described in detail with reference to the drawings. Here, elements having the same function throughout all of the drawings are all referred to by the same numerals and repetitive descriptions of them are omitted. In addition, in the present embodiments, a p channel type MIS.FET (Metal Insulator Semiconductor Field Effect Transistor) is abbreviated as pMIS, while an n channel type MIS.FET is abbreviated as nMIS. In addition, in the present specification, an MIS.FET of an ordinary gate electrode structure refers to an MIS.FET with a structure having gate electrodes formed by patterning a conductive film deposited on the semiconductor substrate. In addition, in the present specification, a high concentration region is a region where the concentration of impurities which become donors or acceptors is comparatively high in comparison with a low concentration region. In addition, corner parts inside the trenches or angles of the bottoms inside the trenches include, in addition to angled parts formed between side surfaces and the bottoms inside the trenches, parts of which the radius of curvature is the smallest in the inside of the trenches.
Then, an insulating film 4 made of silicon oxide, or the like, having a thickness of approximately 10 nm, is formed on the surface of the semiconductor substrate 1 by oxidizing the surface of the semiconductor substrate 1 through a thermal oxidation method, or the like, and, after that, a p well (first semiconductor region) 3P and an n well 3N are formed in the semiconductor substrate 1. The p well 3P and the n well 3N are formed by introducing separate impurities, respectively, using a separate photoresist (hereinafter referred to merely as resist) film as a mask, respectively, and, after that, by carrying out heat treatment. The p well 3P, wherein MIS.FETs for selecting memory cells are formed, is formed by implanting, for example, boron (B) at 300 keV, 130 keV and 40 keV, respectively, in the amount of 1×1013/cm2, 2×1012/cm2 and 1×1012/cm2 and, after that, by carrying out a heat treatment at, for example, 1000° C. for 30 minutes. Here, for example, phosphorous (P) or arsenic (As) is introduced in the n well 3N.
One reason is that the trenches can be formed without generating etching residue of the semiconductor substrate (silicon) at the bottom of the trenches for forming word lines. That is to say, there are some cases in which etching residue is generated at the bottom of the trenches when the trenches 7 a are formed after the trenches 7 b are formed. This is because, as shown in FIG. 6, if the trenches 7 b are first created, tapers are formed on the side surfaces of the isolation parts 2, since the width of the isolation parts 2 becomes gradually narrower in the downward direction in FIG. 6, so that the parts which contact the isolation parts 2 at the bottom of the trenches 7 b are in a shadow so as to result in the etching residue of the semiconductor substrate (silicon). Under this condition, as shown in FIG. 7, when the insulating film 2 b of the isolation parts 2 is shaved to form the trenches 7 a, microscopic protrusions of the semiconductor substrate are formed at the bottom of the trenches for forming word lines constructed of the trenches 7 a and 7 b. Those protrusions become the cause of defects related to the withstanding voltage, or the like, of the gate insulating film. Another reason is that, after removing the insulating film 2 b (silicon oxide film) through etching, boron ions, or the like, can be implanted for the purpose of selectively increasing the element isolation within the trenches 7 a.
In addition, the reason why the insulating film 5 made of silicon nitride is used as a mask at the time of formation of the trenches 7 b is, for example, as follows. One reason is that a silicon nitride film is hard to etch at the time when the semiconductor substrate 1 made of silicon is etched. Another reason is that a polycrystal silicon film is polished in a later step and the silicon nitride film functions as a stopper at that time. In addition, another reason is that even if the trenches 7 b are created at the same time when the trenches 7 a are created, it is hard to etch silicon oxide of the isolation parts 2 b and silicon of the semiconductor substrate 1 at an equal rate. On the other hand, the thickness of the resist film 6 a is not sufficient for carrying out etching divided into two stages. Though it is necessary for the resist film to be thick enough to avoid falling down due to the surface tension of the developer in the drying step after developing, the resist film ordinarily falls down when the height of the resist film exceeds approximately three times the width of the resist film. When the width of the resist film 6 a is, for example, approximately 0.13 μm, the limit of the height of the resist film 6 a becomes approximately 0.4 μm. In the case of the formation of the trenches 7 a and 7 b, the depth of the etching corresponds to the thickness of the reflection preventive film (approximately 100 nm)+the thickness of the silicon nitride film (approximately 100 nm)+the thickness of silicon oxide film (approximately 200 nm)+the depth of the trenches in the silicon (approximately 200 nm); and, therefore, the resist film 6 a is eliminated during etching, which results in the failure of trench pattern formation.
After the above-described implantation of impurities for adjusting the threshold voltage, the sacrificial oxide film is removed with, for example, hydrofluoric acid. At this time the etching rate of the insulating film 2 b of the isolation parts 2, which is exposed from the trenches 7 a, is larger than that of the sacrificial oxide film, and this is taken into consideration so as to have a difference between the depths of the trenches 7 a and 7 b, and, therefore, as shown in FIG. 8, the trenches 7 a are not deeper than the trenches 7 b. Here, though a case is shown in which the trenches 7 b after the above step are deeper than the trenches 7 a, they may be approximately equal. At this stage, it is preferable for the bottom of the interface between those trenches 7 a and 7 b not to have large and steep steps or unevenness compared to that at the time of the formation of the trenches 7 a and 7 b.
In addition, in the present Embodiment 1, the gate trenches are formed through the above-described step etching method, and, thereby, the undercuts beneath the hard mask can be prevented and trenches of a desired depth which have a large radius of curvature of the bottom corners of the above-described trenches can be obtained. Thereby, the characteristics of the MIS.FETs of a buried gate electrode structure, especially the sub-threshold characteristics, can be increased (sub-threshold coefficient can be made smaller). That is to say, the divergence of the electric field in the vicinity of the bottom corners within the trenches 7 b can be relaxed so that the channel resistance can be reduced and a desired drain current can be obtained at a predetermined threshold voltage. Therefore, it becomes possible to increase the element driving performance. In addition, it becomes unnecessary to make the transistors of the depletion type, and, therefore, the increase of the leakage current can be prevented, and it also becomes possible to prevent an increase of power consumption. In the present Embodiment 1, the radius of curvature of the bottom corners within the trenches 7 b is made to be, for example, 10 nm or more, or, for example, approximately 30 nm. The radius of curvature in the bottom corners within the trenches 7 b will be described in more detail later.
After that, as shown in FIG. 15, after an insulating film 10 made of, for example, silicon nitride, is deposited through a CVD method, or the like, by etching back the insulating film 10 through an isotropic dry etching method, an insulating film 10 is filled in the voids on the upper surface of the gate electrode forming film 9 a, which is filled into the trenches 7 a and 7 b, as shown in FIG. 16. At this time the insulating film 10 is supposed not to leave a residue on the upper side walls of the trenches 7 a and 7 b.
Next, as shown in FIG. 17, the gate electrode forming film 9 a is, again, etched back through an isotropic dry etching treatment. At this time, the insulating film 5 on the semiconductor substrate 1 and the insulating film 10, which is filled in the voids of gate electrode forming film 9 a, are used as an etching mask. The reason why the insulating film 10 is formed in the voids in this way is that, if the insulating film 10 does not exist, the etching proceeds more in the void parts than in other parts at the time of the etching back treatment of the gate electrode forming film 9 a, and, therefore, the gate insulating film 8 b is exposed so as to include the risk of defects. Accordingly, in case such a problem doesn't occur, the step of formation of the insulating film 10 may be eliminated. Then, an oxidization process is applied to the semiconductor substrate 1 and, thereby, amorphous silicon is oxidized, and, after that, the part oxidized by this is removed by hydrofluoric acid, or the like. Thereby, it becomes possible to remove the residue of amorphous silicon even if it remains within the trenches 7 a and 7 b. After that, as shown in FIG. 18, a conductive film 11 made of, for example, titanium (Ti), or the like, is deposited through a CVD method, a sputtering method, or the like, and then the conductive film 11 and the gate electrode forming film 9 a cause a silicidation reaction through the process of annealing. After that, by removing the conductive film 11, which hasn't reacted, using hydrogen peroxide, or the like, word lines WL (gate electrodes 9) made of, for example, titanium silicide, or the like, are formed within the trenches 7 a and 7 b, as shown in FIGS. 19 and 20. In the present Embodiment 1, microscopic trenches 7 a and 7 b are filled in with amorphous silicon which makes an effective filling in possible, and, after that, the amorphous silicon is made to be silicide through silicidation, and, thereby, the gate electrodes 9 made of titanium silicide, or the like, which is of low resistance, can be formed within the trenches 7 a and 7 b in an effective filled in manner. Here, the filled in gate electrode material is not limited to titanium silicide, but, rather, can be changed in a variety of ways. For example, the surface of the titanium silicide can be further nitrided so as to gain a structure where titanium nitride is layered. In this case, it becomes possible to increase the withstanding characteristics of the gate electrode at the time of the cleaning treatment after contact holes are created in the insulating film so that gate electrodes are exposed in the later steps. In addition, by using metal, such as tungsten, the resistance of the word lines WL can be reduced to a great extent. Furthermore, a structure can be gained wherein, for example, a polycrystal silicon of low resistance, tungsten nitride and tungsten are stacked in this order from the lower layer. In this case, by making the lowest layer of polycrystal silicon p-type, the threshold voltage can be made larger by the difference of work function with the n-type silicon, and, therefore, it becomes possible to secure a desired threshold voltage under the condition where the impurity concentration of the semiconductor substrate 1 is made lower. This effect can be gained in the case where tungsten is used as a gate electrode material. In addition, the gate electrodes may be constructed of, only, a polycrystal silicon of low resistance.
Next, after depositing an insulating film 14 made of, for example, silicon oxide, on the main surface of the semiconductor substrate 1 through a CVD method, or the like, this is patterned so that the regions for forming word lines WL (buried gate electrodes 9) are exposed and other regions are covered through a photolithographic technology and a dry etching technology. Then, impurities for sources and drains of MISFETs of the buried gate electrode structure are introduced in the semiconductor substrate 1 using the insulating film 14 as a mask. Here, for example, phosphorous is introduced at 20 keV in approximately 2×1013/cm2. Thereby, low concentration regions (second semiconductor regions) 15 a, in which the impurity concentration is relatively low, are formed within the semiconductor regions for sources and drains. And, after that, the insulating film 14 is removed by hydrofluoric acid, or the like.
Next, the effects of an increase in the sub-threshold characteristics (sub-threshold coefficient becomes smaller) through the formation of rounding in the bottom corners within the trenches 7 b will be described. The sub-threshold coefficient S is the width of the gate voltage which is required to change the drain current by one digit and can be expressed by S=ln10·T/q(1+(Cd+Cit)/Cox); and, the smaller the value is, the more preferable it is. Here, the depletion layer capacitance is denoted as Cd, the interface level (equivalent capacitance) is denoted as Cit and the gate capacitance is denoted as Cox.
In addition, here, in the case where the threshold voltage of the MIS.FETQs for memory cell selection is low at the time of completion, impurities (for example, boron) for adjusting this threshold voltage may be implanted in the amount of approximately 1×1012/cm2 to 1×1013/cm2 at, for example, the energy level of approximately 20 keV to 50 keV, through the contact holes 21. Thereby, as shown in FIG. 45, p-type semiconductor regions 43 are formed below the low concentration regions 15 a to which bit lines are connected. After that, for example, phosphorous is ion implanted through the contact holes 21 so as to form high concentration regions 15 b.
Next, as shown in FIG. 46, after depositing an insulating film 44 made of silicon oxide of, for example, the thickness of approximately 300 nm on the semiconductor substrate 1, contact holes 45 for capacitors are created in the insulating films 44 and 20. At this time, also, in the present Embodiment 3, by carrying out the etching under the condition where the etching rate for silicon nitride is faster than that for silicon oxide, the contact holes 45 can be prevented from reaching the gate electrodes 9 because of the slow etching rate of the cap insulating film 42 a even in the case where over-etching takes place at the time of the formation of the contact holes 45. That is to say, the contact holes 45 can be formed in a self-aligned manner with respect to the gate electrodes 9. In addition, in the same way as in the above-described Embodiment 2, even in the case where parts of the isolation parts 2 are exposed from the contact holes 45, they are not shaved off to a great extent through etching.
In addition, here, for example, phosphorous is ion implanted in the amount of approximately 1×1013/cm2 to 3×1013/cm2 at the energy level of approximately 20 keV to 50 keV through the contact holes 45, and, thereby, n-type semiconductor regions 46, in which the impurity concentration is lower than the low concentration regions 15 a, are formed. These n-type semiconductor regions 46 have the function of relaxing the junction electric field intensity in the semiconductor regions for the sources and drains of the MIS.FETs for memory cell selection of the above-described buried gate structure.
In the present Embodiment 4, the low concentration regions 48 a and 49 a, respectively, are formed so as to be distributed in deeper positions than the low concentration regions 15 a of the MIS.FETQs for memory cell selection, while the high concentration regions 48 b and 49 b are formed so as to be distributed in deeper positions than the high concentration regions 15 b of the MIS.FETQs for memory cell selection. Thereby, it becomes possible to increase the driving performance of the nMISQn and pMISQp which form the peripheral circuit. Here, the borders between the low concentration regions 48 a and the high concentration regions 48 b, as well as the borders between the low concentration regions 49 a and the high concentration regions 49 b are positioned so as to be shallower than the upper surface of the gate electrodes 9. In addition, the borders between the low concentration regions 48 a and the p well 3P, as well as the borders between the low concentration regions 49 a and the n well 3N, are positioned at a depth between the top and bottom of the gate electrodes 9. Here, a conductive film 50 made of, for example, titanium silicide is formed on the contact interface between the high concentration regions 48 b and 49 b and the plugs 25 so that it becomes possible to reduce the contact resistance between the plugs 25 and the high concentration regions 48 b and 49 b.
According to the present Embodiment 4, as described above, it becomes possible to gain the following effects, in addition to the effects gained from the above described Embodiments 1 to 3.
1. A process for a semiconductor integrated circuit device where a plurality of memory cells which have field effect transistors formed in a semiconductor substrate and capacitor elements connected to the source and drain regions of said field effect transistors are provided, comprising the steps of:
(a) forming trenches of which the radius of curvature of the bottom corners is larger than 10 nm in a first semiconductor region of said semiconductor substrate;
(b) forming a first gate insulating film through a deposition method inside of said trenches;
(c) forming gate electrodes within said trenches and placing said gate electrodes on said first gate insulating film; and
(d) forming a second semiconductor region and a third semiconductor region in said first semiconductor region such that said second and said third semiconductor regions have a depth shallower than that of said first semiconductor region and that of said trenches,
wherein said second and said third semiconductor regions serve as source and drain regions of said field effect transistor such that a channel forming region thereof is effected at the bottom surface of said trench and two side surfaces of said trench between said second semiconductor region and said third semiconductor region.
2. A process for a semiconductor integrated circuit device according to claim 1 characterized by having the step of forming a second gate insulating film by oxidizing the inner walls of said trenches.
(a) forming trenches in a first semiconductor region of a semiconductor substrate;
(b) forming a gate insulating film inside of said trenches;
(c) forming gate electrodes which are completely, or partially, buried within said trenches under the condition where said gate insulating film is interposed between said gate electrodes and said semiconductor substrate within said trenches;
(d) forming semiconductor regions for the sources and drains in said semiconductor substrate; and
(e) forming a second semiconductor region and a third semiconductor region in said first semiconductor region such that said second and said third semiconductor regions have a depth shallower than that of said first semiconductor region and that of said trenches,
wherein said second and said third semiconductor regions serve as said source and said drain regions of a field effect transistor such that a channel forming region thereof is effected at the bottom surface of said trench and two side surfaces of said trench between said second semiconductor region and said third semiconductor region, and
wherein said Step (a) contains the step of rounding the bottom corners within said trenches so that the sub-threshold coefficient of said field effect transistors does not exceed a predetermined value, and said Step (b) contains the step of forming said gate insulating film through a deposition method.
5. A process for a semiconductor integrated circuit device according to claim 4, wherein said Step (a) contains the step of carrying out an etching process by switching to etching conditions of rounding the corner parts within the trenches during the etching process proceeding in the direction of the trench depth after carrying out an etching process under etching conditions of relatively strong anisotropy.
(a) forming a first trench in said semiconductor substrate;
(b) forming element isolation parts by forming an insulating film in said first trench;
(c) forming a mask which has apertures crossing over said element isolation parts;
(d) forming a second trench in the element isolation parts which have been exposed through said apertures;
(e) forming a third trench in the semiconductor substrate which has been exposed through said apertures and the second trench; and
(f) forming said wires in said second and third trenches.
9. A process for a semiconductor integrated circuit device according to claim 8, wherein the inclination angle of the side walls of said first and third trenches, with respect to the main surface of said semiconductor substrate, is smaller than 90 degrees.
(a) forming a first trench by etching said semiconductor substrate;
(b) forming element isolation parts by forming an insulator film inside of said first trench;
(c) forming a mask which has first apertures formed so as to cross over said element isolation parts;
(d) forming a second trench by etching the element isolation parts which have been exposed through said first apertures;
(e) forming a third trench by etching the semiconductor substrate which has been exposed through said first apertures and said second trench; and
(f) forming a gate insulating film on the inside walls of said third trench and forming the first wire inside of said second and third trenches.
11. A process for a semiconductor integrated circuit device according to claim 10, wherein the inclination angle of the side walls of said first and third trenches, with respect to the main surface of said semiconductor substrate, is smaller than 90 degrees.
(a) forming a first trench in a semiconductor substrate;
(b) forming isolation parts by forming an insulating film for isolation in said first trench;
(c) forming a mask having aperture parts which expose both of said isolation parts and said semiconductor substrate on said semiconductor substrate;
(d) forming a second trench in the isolation parts which have been exposed from said aperture parts and, after that, forming a third trench in the semiconductor substrate which has been exposed from said aperture parts and said second trench;
(e) forming an insulating film on the surface of the semiconductor substrate within said second and third trenches; and
(f) forming wires within said second and third trenches.
18. A process for a semiconductor integrated circuit device according to claim 17, wherein at the time of forming said second trench, at the stage after said Step (f), said insulating film for isolation remains at the bottom of said second trench so that no parasitic elements are formed below the wires formed inside of said second trench.
filling in said second and third trenches with a first film for forming said wires;
removing said first film so that a part thereof remains inside of said second and third trenches; forming a second film which fills in the recesses of the surface of the first film which has remained inside of said second and third trenches; and removing said first film, after the formation of said second film, so that a part thereof remains inside of said second and third trenches.
27. A process for a semiconductor integrated circuit device according to claim 26 characterized by having the step of forming a first insulating film on the wires inside of said second and third trenches by removing the first insulating film so that a part thereof remains inside of said second and third trenches after depositing the first insulating film on said semiconductor substrate subsequent to the formation of said wires.
in said step of forming holes, said holes are formed by carrying out an etching process under conditions where the etching rate of said second insulating film is faster than that of said first insulating film.
29. A process for a semiconductor integrated circuit device according to claim 28, wherein after filling in said holes with a conductive film, semiconductor regions are formed in a semiconductor substrate through impurity diffusion into the semiconductor substrate from the conductive film.
(a) forming first semiconductor regions in said semiconductor substrate;
(b) forming a first trench in said semiconductor substrate;
(c) forming a gate insulating film, gate electrodes and a first insulating film inside said first trench;
(d) forming a second insulating film on the semiconductor substrate and, further, over said first insulating film;
(e) forming apertures, in said second insulating film, which overlap said first semiconductor regions in a plane manner through a method where the etching rate of said second insulating film is faster than the etching rate of the first insulating film;
(f) forming a conductive film inside of said apertures; and
(g) forming second semiconductor regions in said semiconductor substrate through an impurity diffusion from said conductive film such that said first and second semiconductor regions serve as said source and drain regions.
34. A process for a semiconductor integrated circuit device according to claim 33, wherein said first insulating film is formed of a silicon nitride film and said second insulating film is formed of a silicon oxide film.
(a) forming an element isolation region in a first semiconductor region of a semiconductor substrate such that said element isolation region defines a first region of said first semiconductor region so as to surround said first region;
(b) forming a trench in said first semiconductor region and in said element isolation region such that said trench crosses said first region;
(c) forming a gate insulating film of a field effect transistor on said first semiconductor region inside of said trench;
(d) after said step (c), burying a gate electrode of said field effect transistor into said trench;
(e) after said step (d), introducing an impurity in said first region in self-alignment with said element isolation region and said gate electrode so as to form a second semiconductor region and a third semiconductor region in said first semiconductor region such that said second and said third semiconductor regions have a depth shallower than that of said first semiconductor region and that of said trench,
wherein said second and said third semiconductor regions serve as said source and said drain region of said field effect transistor such that a channel forming region thereof is to be formed at the bottom surface of said trench and two side surfaces of said such trench between said second semiconductor region and said third semiconductor region.
36. A method of manufacturing a semiconductor integrated circuit according to claim 35, wherein said step (b) includes substeps of:
(b1) etching said element isolation region to form a first trench in said element isolation region; and
(b2) after said substep (b1), etching said first semiconductor region to form a second trench in said first region.
37. A method of manufacturing a semiconductor integrated circuit according to claim 36, wherein a depth of said second semiconductor region is uniform within said source and drain region such that an entire circumference of the bottom of said second semiconductor region contacts the element isolation region or said trench.
US09767830 2000-01-25 2001-01-24 Semiconductor integrated circuit device and process for manufacturing the same Active 2022-01-27 US6770535B2 (en)
JP2000-015604 2000-01-25
JP2000015604A JP4860022B2 (en) 2000-01-25 2000-01-25 The method of manufacturing a semiconductor integrated circuit device
US10866018 US20040224476A1 (en) 2000-01-25 2004-06-14 Semiconductor integrated circuit device
US10866018 Division US20040224476A1 (en) 2000-01-25 2004-06-14 Semiconductor integrated circuit device
US20010025973A1 true US20010025973A1 (en) 2001-10-04
US6770535B2 true US6770535B2 (en) 2004-08-03
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US09767830 Active 2022-01-27 US6770535B2 (en) 2000-01-25 2001-01-24 Semiconductor integrated circuit device and process for manufacturing the same
US10866018 Abandoned US20040224476A1 (en) 2000-01-25 2004-06-14 Semiconductor integrated circuit device
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