Source: http://www.google.com/patents/US7573768?dq=6,998,619
Timestamp: 2017-03-30 10:02:54
Document Index: 797735273

Matched Legal Cases: ['Application No. 10', 'arts 150', 'arts 150', 'art 150', 'art 150', 'art 150', 'application No. 2004']

Patent US7573768 - Low voltage semiconductor memory device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; and a reference cell block including a plurality of reference cell units,...http://www.google.com/patents/US7573768?utm_source=gb-gplus-sharePatent US7573768 - Low voltage semiconductor memory deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7573768 B2Publication typeGrantApplication numberUS 11/126,744Publication dateAug 11, 2009Filing dateMay 10, 2005Priority dateDec 22, 2004Fee statusPaidAlso published asCN1794454A, CN100423268C, US20060133131Publication number11126744, 126744, US 7573768 B2, US 7573768B2, US-B2-7573768, US7573768 B2, US7573768B2InventorsHee-bok Kang, Jin-Hong AhnOriginal AssigneeHynix Semiconductor Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (24), Referenced by (2), Classifications (10), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetLow voltage semiconductor memory device
US 7573768 B2Abstract
A semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; and a reference cell block including a plurality of reference cell units, each including a reference capacitor, a first reference transistor for connecting a first terminal of the reference capacitor to the bit line, a second reference transistor for connecting the first terminal of the reference capacitor to the bit line bar, and a third reference transistor connected to a reference voltage for supplying the reference voltage to the first terminal of the reference capacitor.
a normal cell block including a plurality of normal cells, which are pairs in a folded bit line structure, each pair being commonly applied with a plate voltage and being coupled to a bit line and a bit line bar for storing a data;
a reference cell block including a plurality of reference cell units, each including a reference capacitor, a first reference transistor for connecting a first terminal of the reference capacitor to the bit line, a second reference transistor for connecting the first terminal of the reference capacitor to the bit line bar, and a third reference transistor connected to a reference voltage for supplying the reference voltage to the first terminal of the reference capacitor, wherein two reference cell units per four bit lines are laid out at both end portions of each bit line;
a sense amplifying block for sensing and amplifying the data by using a core voltage for operating the semiconductor memory device and a high voltage having a higher voltage level than the core voltage,
wherein the high voltage is inputted to the sense amplifying block during a predetermined period from a timing of starting to sense and amplify the data wherein the core voltage is inputted to the sense amplifying block after the predetermined period,
wherein the normal cell block includes:
a first normal cell including a first normal capacitor and a first normal transistor for connecting the normal capacitor to the bit line; and
a second normal cell including a second normal capacitor laid out with the same pattern as the first normal capacitor and a second normal transistor laid out with the same pattern as the first normal transistor to connect the second normal capacitor to the bit line bar; and
a contact plug, contacted with a normal storage node corresponding to each source of the first and the second normal transistors.
2. The semiconductor memory device as recited in claim 1, wherein the precharge block includes:
a first metal oxide semiconductor (MOS) transistor for receiving a precharge signal and supplying the ground to the bit line in response to the precharge signal; and
a second MOS transistor for receiving the precharge signal and supplying the ground to the bit line bar as a precharge voltage in response to the precharge signal.
3. The semiconductor memory device as recited in claim 1, wherein the sense amplifying block includes:
4. The semiconductor memory device as recited in claim 1, further comprising a data output block for delivering the data amplified by the sense amplifying block into a data line and a data line bar or delivering an inputted data through the data line and the data line bar into the sense amplifying block.
5. The semiconductor memory device as recited in claim 4, wherein the data output block includes:
7. The semiconductor memory device as recited in claim 6, wherein the connection signal, which is based on inputted address and command, is activated during a precharging operation.
8. The semiconductor memory device as recited in claim 1, wherein the first to the third reference transistors are laid out with the same pattern as the second normal transistor, and the reference capacitor is laid out with the same pattern as the second normal capacitor.
9. The semiconductor memory device as recited in claim 8, wherein each source of the first and second reference transistors and a drain of the third reference transistor are laid out to be connected to each contact plug in order for connection with a common reference storage node.
10. The semiconductor memory device as recited in claim 8, wherein the cell array area includes:
a first active area for the second normal transistor;
a second active area for the first normal transistor and the first reference transistor;
a third active area for the second reference transistor;
a fourth active area for the third reference transistor;
a first word line for the second normal transistor arranged across the first active area;
a second word line for the first normal transistor arranged across the second active area;
a third word line for the first reference transistor arranged across the second active area, the third word line being spaced apart from the second word line by a predetermined distance;
a fourth word line for the second reference transistor arranged across the third active area;
a fifth word line for the third reference transistor arranged across the fourth active area;
a first bit line contact plug and a first storage node contact plug for the second normal transistor, the first bit line contact plug and the first storage node contact plug being laid out to be respectively connected to an upper portion and a lower portion of the first active area;
a second storage node contact plug for the first normal transistor, the second storage node contact plug being laid out to be connected to an upper portion of the second active area;
a second bit line contact plug for the first normal transistor and the first reference transistor, the second bit line contact plug being laid out to be connected at a middle area of the second active area;
a third storage node contact plug for the first and second reference transistors, the third storage node contact plug being laid out to be commonly connected to a lower portion of the second active area and an upper portion of the third active area;
a third bit line contact plug for the second reference transistor, the third bit line contact plug being laid out to be connected to a lower portion of the third active area;
a fourth bit line contact plug for the third reference transistor, the fourth bit line contact plug being laid out to be an upper portion of the fourth active area;
a first normal capacitor arranged at the upper portion of the second active area and connected to the second storage node contact plug;
the reference capacitor arranged at the lower portion of the second active area and connected to the third storage node contact plug;
the bit line intersected with the first to fourth word lines and connected to the second bit line contact plug;
the bit line bar intersected with the first to fourth word lines and connected to the first and third bit line contact plugs; and
an auxiliary connection pattern laid out with the same conductive layer as the bit line and connected to the fourth bit line contact plug and the third bit line contact plug.
11. The semiconductor memory device as recited in claim 10, wherein the first to the fifth word lines are laid out with the same intervals.
a first dummy capacitor arranged on the same layer as the reference capacitor and laid out on the third active area; and
a second dummy capacitor arranged on the same layer as the reference capacitor and laid out on the fourth active area.
13. A semiconductor memory device having a cell array area, comprising:
a normal cell block including a plurality of normal cells, which are pairs in a folded bit line structure, each pair being commonly applied with a plate voltage and being coupled to a bit line and a bit line bar;
a reference cell block including a plurality of reference cell units, each including a reference capacitor, wherein two reference cell units per four bit lines are laid out at both end portions of each bit line;
a switching block for connecting the reference cell units to one of the bit line and the bit line bar
a supplying block for supplying a reference voltage to the reference cell units.
14. The semiconductor memory device as recited in claim 13, wherein the switching block includes first reference transistors for connecting a first terminal of one of the reference cell units to the bit line and second reference transistors for connecting the first terminal of one of the reference cell units to the bit line bar.
15. The semiconductor memory device as recited in claim 14, wherein the supplying block includes third reference transistors connected to the reference voltage for supplying the reference voltage to the first terminal of one of the reference cell units.
16. The semiconductor memory device as recited in claim 13, further comprising:
a sense amplifying block for sensing and amplifying data by using a core voltage for operating the semiconductor memory device and a high voltage having a higher voltage level than the core voltage.
17. The semiconductor memory device as recited in claim 16, wherein the high voltage is inputted to the sense amplifying block during a predetermined period from a timing of starting to sense and amplify the data.
18. The semiconductor memory device as recited in claim 17, wherein the core voltage is inputted to the sense amplifying block after the predetermined period.
19. The semiconductor memory device as recited in claim 16, wherein the precharge block includes:
a second MOS transistor for receiving the precharge signal and supplying the ground to the bit line bar in response to the precharge signal.
20. The semiconductor memory device as recited in claim 16, wherein the sense amplifying block includes:
21. The semiconductor memory device as recited in claim 16, further comprising a data output block for delivering the data amplified by the sense amplifying block into a data line and a data line bar or delivering an inputted data through the data line and the data line bar into the sense amplifying block.
22. The semiconductor memory device as recited in claim 21, wherein the data output block includes:
23. The semiconductor memory device as recited in claim 16, further comprising a connection block for connecting or disconnecting the normal cell block to the sense amplifying block in response to a connection signal.
24. The semiconductor memory device as recited in claim 23, wherein the connection signal, which is based on inputted address and command, is activated during a precharging operation.
25. The semiconductor memory device as recited in claim 15, wherein the each pair of normal cells includes:
a second normal cell including a second normal capacitor laid out with the same pattern as the first normal capacitor and a second normal transistor laid out with the same pattern as the first normal transistor to connect the second normal capacitor to the bit line bar.
26. The semiconductor memory device as recited in claim 25, wherein the first to the third reference transistors are laid out with the same pattern as the second normal transistor, and the reference capacitor is laid out with the same pattern as the second normal capacitor.
27. The semiconductor memory device as recited in claim 26, further including contact plugs to be contacted with a normal storage node corresponding to each source of the first and the second normal transistors, or a common reference storage node wherein each source of the first and second reference transistors and a drain of the third reference transistor are laid out to be connected.
28. The semiconductor memory device as recited in claim 26, wherein the cell array area includes:
29. The semiconductor memory device as recited in claim 28, wherein the first to the fifth word lines are laid out with the same intervals.
30. The semiconductor memory device as recited in claim 29, further including:
This application claims priority to Korean Patent Application No. 10-2004-0110403 filed Dec. 22, 2004.
Referring to FIG. 2, the cell array of the semiconductor memory device includes a plurality of unit cells disposed at intersections of word line WL0, WL1, . . . WL4 and WL5 and bit lines BL and /BL.
Then, the sensed and amplified data latched on the two bit line pair BL and BL/are outputted external data lines LDB and LDBB.
Referring to FIG. 3, sense amplifier parts 150 and 170 are provided among cell arrays 110, 130, and 180. Each of the sense amplifier parts 150 and 170 includes a plurality of sense amplifiers for sensing and amplifying data of unit cells contained in the cell arrays 110, 130, and 180.
Referring to FIG. 4, the sense amplifier part 150 operates in responsive to a first and a second sense amplifier power supply signal SAP and SAN. The sense amplifier part 150 includes a sense amplifier 152 a, a precharge unit 155 a, a first equalization unit 154 a, a second equalization unit 157 a, and a data output unit 156 a. The sense amplifier 152 a senses and amplifies signal difference between the bit line pair BL and /BL. The precharge unit 155 a is enabled in response to a precharge signal BLEQ outputted when the sense amplifier 152 a does not operate, and precharges the bit line pair BL and /BL to a bit line precharge voltage VBLP. In response to the precharge signal BLEQ, the first equalizer 154 a equalizes voltage levels of the bit line pair BL and /BL connected between a cell array 0 110. In response to the bit line precharge signal BLEQ, the second equalizer 157 a equalizes voltage levels of bit line pair BL and /BL connected to a cell array 1 130.
Accordingly, the voltage of the bit line BL precharged to the ½ core voltage increases. At this point, even though the capacitor is charged to the core voltage level, a capacitance Cc of the capacitor of the unit cell is very small compared with a parasitic capacitance Cb of the bit line BL. Thus, the voltage of the bit line does not increase up to the core voltage Vcore, but increases by a predetermined voltage ΔV from the ½ core voltage.
During the sense period, voltage levels of the first and the second sense amplifier power supply signals SAP and SAN maintaining the ½ core voltage during the precharge period are respectively supplied to the core voltage and the ground voltage. Thus, the bit line sense amplifier 152 a senses and amplifies a voltage difference between the two bit lines BL and /BL. At this point, the bit line sense amplifier 152 a amplifies the relatively higher voltage level to the core voltage Vcore and the relatively lower voltage level to the ground voltage.
Then, the precharge period again begins. The voltage levels of the first and the second sense amplifier power supply signals SAP and SAN supplied to the sense amplifier are maintained at the ½ core voltage. The precharge signal BLEQ is activated to enable the first and second equalization units 154 a and 157 a and the precharge unit 155 a, so that the precharge voltage VBLP is supplied to the bit line pair BL and /BL. Due to the activation of the first and second connection units 151 a and 153 a, the sense amplifier part 150 is connected to the cell arrays 110 and 130 provided at the one side and the other side.
Also, the required power supply voltage is reduced to 2.0 V or 1.5 V, and even 1.0 V. Under such a situation, it is difficult to maintain the required operating speed only by reducing the manufacturing technology.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; and a reference cell block including a plurality of reference cell units, each including a reference capacitor, a first reference transistor for connecting a first terminal of the reference capacitor to the bit line, a second reference transistor for connecting the first terminal of the reference capacitor to the bit line bar, and a third reference transistor connected to a reference voltage for supplying the reference voltage to the first terminal of the reference capacitor.
FIGS. 11A to 18A are layouts of the semiconductor memory device in accordance with the present invention; and
FIGS. 11B to 18B are sectional views of the semiconductor memory device shown in FIGS. 11A to 18A.
FIG. 7 is a block diagram of a semiconductor memory device in accordance with an embodiment of the present invention. Referring to FIG. 7, the semiconductor memory device in accordance with an embodiment of the present invention includes has a folded bit line architecture. Cell arrays 300 c and 300 d include bit line BL and bit line bar /BL arranged alternately. A plate voltage PL is commonly applied to capacitors constituting two unit cells.
Referring to FIG. 8, the semiconductor memory device includes a first cell array 300 c, a bit line sense amplifier 210, a precharge unit 220, a first reference cell block 400 c, and a second reference block 400 d. The first cell array 300 c applies data signal on a bit line BL1 or a bit line bar /BL1. When the data signal is applied on the bit line BL1 or the bit line bar /BL1, the bit line sense amplifier 210 senses and amplifies a voltage difference between the bit line BL1 and the bit line bar /BL1. The precharge unit 220 supplies a ground voltage GND to the bit line BL1 and the bit line bar /BL1 in response to a precharge signal BLEQ. The first reference cell block 400 c applies a reference signal to the bit line bar /BL1 when the data signal is applied on the bit line BL1. The second reference cell block 400 d applies the reference signal to the bit line BL1 when the data signal is applied on the bit line bar /BL1.
Also, the bit line sense amplifier 210 is driven with a high voltage Vpp higher than a core voltage Vcore inputted as a driving voltage during a predetermined initial period in which the voltage difference between the bit line and the bit line bar is sensed and amplified.
Also, the precharge unit 220 includes a first precharge MOS transistor TP1 and a second precharge MOS transistor TP2. The first precharge MOS transistor TP1 receives the precharge signal BLEQ through a gate and supplies a ground voltage GND inputted from one terminal to the bit line BL1 as the precharge voltage through the other terminal. The second precharge MOS transistor TP2 receives the precharge signal BLEQ through a gate and supplies the ground voltage GND inputted from one terminal to the bit line bar /BL1 as the precharge voltage through the other terminal.
The bit line sense amplifier 210 includes a first PMOS transistor TS1, a second PMOS transistor TS2, a first NMOS transistor TS3, and a second NMOS transistor TS4. The first PMOS transistor TS1 has a gate commonly connected to the bit line and the bit line bar, one terminal receiving the high voltage Vpp or the core voltage Vcore as the driving voltage, and the other terminal connected to the bit line BL1 and the bit line bar /BL1. The second PMOS transistor TS2 has a gate commonly connected to the bit line BL1 and the bit line bar /BL1, one terminal receiving a high voltage Vpp or a core voltage Vcore as a driving voltage, and the other terminal connected to the bit line BL1 and the bit line bar /BL1. The first NMOS transistor TS3 has a gate commonly connected to the bit line BL1 and the bit line bar /BL1, one terminal receiving a ground voltage GND, and the other terminal connected to the bit line BL and the bit line bar /BL1. The second NMOS transistor TS4 has a gate commonly connected to the bit line BL1 and the bit line bar /BL1, one terminal receiving the ground voltage GND, and the other terminal connected to the bit line BL1 and the bit line bar /BL1.
Referring to FIG. 9, the first reference cell block 400 c includes reference capacitors RC1 and RC2, a first switching MOS transistor RT1, a second switching MOS transistor RT2, and a third switching MOS transistor REFT.
Here, each of the MOS transistors RT1 to RT4 is turned on in response to control signals REF_SEL1 and /REF_SEL1, and the MOS transistor REFT is turned on in response to the precharge control signal REF PCG.
If the number of the normal capacitors corresponding to one word line in the cell array is 512, 512 capacitors are additionally provided for the reference capacitors. Only one of two adjacent capacitors is connected to the MOS transistors RT1 and RT2 and is used as the reference capacitors RC1, RC2, . . . The other capacitor is used as a dummy capacitor. The reason is to manufacture the reference capacitors together with the normal capacitors.
Meanwhile, in the reference cell block connected to the bit line bar /BL, ½ of the charges stored in the capacitor of the unit cell are supplied to the bit line bar /BL in response to the control signal /REF SEL1, thereby increasing the voltage of the bit line bar /BL. Accordingly, the rising voltage level in the bit line bar /BL becomes about half the rising voltage level in the bit line /BL.
Then, during a predetermined period (t2), the voltage level of the first sense amplifier power supply signal SAP is the high voltage Vpp higher than the core voltage Vcore and the bit line sense amplifier senses and amplifies the signal difference between the bit line and the bit line bar. Since the voltage level of the bit line BL is higher than that of the bit line bar /BL, the level of the bit line BL is amplified to the core voltage Vcore that is the driving voltage, and the level of the bit line bar /BL is amplified to the ground voltage.
After the restore operation is finished (t5), the word line WL is deactivated to a low level, the first sense amplifier power supply signal SAP is not supplied to the sense amplifier, and the precharge signal BLEQ is activated to a high level. When the precharge signal BLEQ is activated to the high level, the bit line pair BL and /BL are precharged to the ground voltage.
Till now, the operation of reading the data “1” in the semiconductor memory device has been described. An operation of reading data “0” will be described below.
Meanwhile, the reference signal Y1 stored in the reference capacitor RC1 is applied to the bit line bar /BL and thus increases by a predetermined voltage level. The applied reference signal supplies charges from the reference cell blocks 400 c and 400 d the bit line bar /BL by ½ of the charges accumulated in the capacitor that stores the data as described above. The charges corresponding to the reference signal are set to ½ of the data signal so as to determine the data “1”.
When the driving voltage is high (e.g., about 5 V), even though ½ core voltage is used as the precharge voltage, there is no problem in amplifying the voltage from 2.5 V to 5 V or 0 V. However, when the driving voltage is low (e.g., about 1.5), the voltage to be amplified is low to about 0.75 V. Thus, an error may occur when noise is generated. That is, due to noise that is spontaneously at 0.75 V, the sense amplifier may amplify the voltage level of the bit line to the core voltage or the ground voltage. At this point, the voltage level of the bit line may be amplified inversely to the voltage level to be amplified.
However, since the present invention uses the ground voltage as the precharge voltage, the voltage that must be amplified when the driving voltage is 1.5V (in the case of the data “1”). Accordingly, even when the driving voltage level is low, the stable amplifying operation can be possible. In the case of the data “0”, the voltage level of the bit line opposite to the bit line to which the reference voltage is applied is amplified up to the core voltage of 1.5 V.
Second, it is possible to prevent the bleed current occurring when the word line and the bit line in the unit cell are electrically shorted. As described above, even though the defective word line is replaced with the dummy word line, the bleed current continuously flows, resulting in the unnecessary power consumption.
FIGS. 11A, 12A, . . . , and 18A are layouts of the semiconductor memory device in accordance with the present invention. In particular, the cell array and the reference cell block are illustrated. FIGS. 11B, 12B, . . . , and 18B are sectional views of the semiconductor memory device shown in FIGS. 11A, 12A, . . . , and 18A respectively.
That is, the semiconductor memory device described above can be directly laid out.
By implementing the MOS transistors RT1 and RT2 and the capacitors RC1 and RC2 for the reference cell at one side of the cell array, the same layers used to manufacturing the MOS transistors of the unit cells are used. Since the design rule applied to the MOS transistors of the unit cells are identically used, additional cost is not required and additional time necessary for development of the product is not required.
Here, a main cell area represents an area where the unit cell of the cell array is formed, and a reference cell area represents an area where the reference capacitors RC1 and RC2 and the reference MOS transistors RT1, RT2 and REFT are formed.
As shown in FIG. 11A, an active area (N+) is formed on a substrate. FIG. 11B is a sectional view of the active area (N+). In FIG. 11A, there are shown sections taken along the lines A-A′, B-B′, C-C′, D-D′ and E-E′ of FIG. 11A.
As shown in FIGS. 12A and 12B, the word lines are formed.
In FIG. 12A, two upper word lines WL are provided for the normal MOS transistors. The reference MOS transistors receive the control signals REF SEL1 and /REF SEL1.
Also, the precharge control signal REF PGC is provided for the reference MOS transistor REFT.
As shown in FIGS. 13A and 13B, the landing plugs LP are formed.
As shown in FIGS. 14A and 14B, the bit line contact plug (BLC) is formed on the landing plug where the bit line contact plug of the normal cell area and the reference cell area is to be formed.
Also, the bit line contact plug BLC is formed on the active area where the MOS transistor REFT is formed. The bit line contact plug is also formed at an end of the landing plug connected at one node in the reference cell area.
As shown in FIGS. 15A and 15B, the bit line BL is formed to contact with the bit line contact plug BLC. At this point, the bit lines intersected with the word lines form the bit line and the bit line bar alternately.
The bit line contact plug formed at the active area where the MOS transistor REFT is formed and the bit line contact plug connected to the landing plug connected to the reference cell area are not connected to the bit line formed at the normal cell area (refer to the RN connection).
This is done for the purpose of supplying the reference voltage to the node RN through the MOS transistor REFT.
As shown in FIGS. 16A and 16B, the storage node contact plug SNC is formed on the landing plug to be contacted with the storage node contact plug.
At this point, the normal cell area forms a plurality of storage node contact plugs SNC at regular intervals. Since only one of the four capacitors formed at the reference cell area is used as the reference capacitor, one storage node contact plugs SNC are formed.
Accordingly, three MOS transistors and one reference capacitor provided at the reference cell are laid out per four bit lines. If the reference cell is arranged on both ends of four bit lines, the reference cell arranged at one side is provided for two bit lines, and the reference cell for the remaining two bit lines is provided at the other side.
As shown in FIGS. 17A and 17B, the storage nodes (lower electrodes) of the capacitors are formed in a matrix at regular intervals.
Also, since one storage node contact plug per four areas is formed at the reference cell area, only one of the storage nodes of the four adjacent capacitors is connected to the storage node contact plug formed at the lower portion, even though the capacitors are all formed at regular intervals.
As shown in FIGS. 18A and 18B, a dielectric layer and a plate electrode of the capacitor are formed.
The present application contains subject matter related to Korean patent application No. 2004-110403, filed in the Korean Patent Office on Dec. 22, 2004, the entire contents of which being incorporated herein by reference.
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