Source: https://patents.google.com/patent/JP5282021B2/en
Timestamp: 2019-12-08 20:38:59
Document Index: 127372652

Matched Legal Cases: ['art 101', 'art 102', 'art 101', 'art 102', 'art 101', 'art 102', 'art 102', 'art 102', 'art 101', 'art 101', 'art 101']

JP5282021B2 - Semiconductor processing system and semiconductor processing method - Google Patents
Semiconductor processing system and semiconductor processing method Download PDF
JP5282021B2
JP5282021B2 JP2009282995A JP2009282995A JP5282021B2 JP 5282021 B2 JP5282021 B2 JP 5282021B2 JP 2009282995 A JP2009282995 A JP 2009282995A JP 2009282995 A JP2009282995 A JP 2009282995A JP 5282021 B2 JP5282021 B2 JP 5282021B2
JP2009282995A
JP2011124496A5 (en
JP2011124496A (en
2009-12-14 Application filed by 株式会社日立ハイテクノロジーズ filed Critical 株式会社日立ハイテクノロジーズ
2009-12-14 Priority to JP2009282995A priority Critical patent/JP5282021B2/en
2011-06-23 Publication of JP2011124496A publication Critical patent/JP2011124496A/en
2013-03-07 Publication of JP2011124496A5 publication Critical patent/JP2011124496A5/en
2013-09-04 Publication of JP5282021B2 publication Critical patent/JP5282021B2/en
In a processing system of a linear tool in which plural carrying robots are arranged in carrying mechanical units to which processing modules are coupled and a processing target is delivered and received between the plural carrying robots, in the case where there are plural carrying routes on which the processing target is carried, the present invention provides a technique for determining the carrying route on which the highest throughput can be obtained. In the processing system of a linear tool, in the case where there are plural carrying routes on which the processing target is carried, the throughputs of the respective carrying routes are compared to each other, and the carrying route is determined by a unit for selecting the carrying route with the highest throughput.
The present invention relates to a processing system in the field of semiconductor manufacturing, and more particularly to a processing system for a linear tool.
In semiconductor processing systems, a processing system having a structure called a cluster tool is widely used. This cluster tool has a problem that a large space is required for installing the processing system, and the required space becomes larger as the diameter of the wafer increases. Therefore, a processing system having a structure called a linear tool that can be installed even in a small space has appeared (Patent Document 1).
The difference between the cluster tool and the linear tool is the structure of the internal transfer part that carries the wafer into and out of the processing module. In the cluster tool, there is usually one transfer robot that transfers wafers at the internal transfer site, and a single transfer robot transfers wafers between the load lock and the processing module, which are the entrance and exit to the internal transfer site. Do. On the other hand, in the linear tool, a plurality of transfer robots are arranged at an internal transfer site, a wafer is transferred between the plurality of transfer robots, and transfer between the load lock and the processing module is performed. However, the transfer robot for transfer differs depending on the position of the processing module at the transfer destination. Depending on the position of the processing module, the transfer may be performed by only one transfer robot, or may not be transferred without a plurality of transfer robots.
In a semiconductor processing system, it is also important to improve throughput. A general processing system has a plurality of processing modules, and a plurality of wafers are processed in parallel. At this time, if the transfer robot does not transfer a plurality of wafers in order, the throughput is lowered. Therefore, a method using scheduling is known as a method for improving throughput. The method by scheduling is to calculate the timing of the transfer and processing of each wafer so as to increase the throughput while taking into consideration the restriction of the operation of the transfer robot, and transfer according to the calculated timing (Patent Document) 2).
In this scheduling method, when a certain transport route is given, the transport and processing timing for improving the throughput in the transport route is calculated. Here, the transfer route is a route through which a wafer to be processed passes after it is loaded into the processing system, processed by the processing module, and unloaded from the processing system. This is determined when the carry-in port, the transfer destination processing module, and the carry-out port are determined. Particularly in the case of a processing system having a plurality of processing modules, unless a processing module as a transfer destination is determined for each wafer to be transferred, the transfer route is not determined and scheduling cannot be performed. Thus, as a method for determining a processing module as a transfer destination, a method is known in which wafers to be transferred are assigned in order from the processing module with the earlier processing completion time (Patent Document 3).
Special table 2007-511104 gazette Japanese translation of PCT publication No. 2002-511193 JP-A-10-189687
In the cluster tool, the highest throughput could be obtained by the conventional method of determining the transport route. Because there is only one transfer robot that performs transfer at the internal transfer site, even if the transfer route is different, the transfer robot related to transfer is the same, and the time required for transfer and the restrictions related to transfer are also the same. It is. Therefore, since the difference in the transport route does not affect the throughput, the method for determining the transport route considering only the processing time of the processing module is sufficient.
However, in the linear tool, the transfer robot related to the transfer at the internal transfer site differs depending on the position of the processing module at the transfer destination. Will also be different. Therefore, there is a high possibility that the highest throughput cannot be obtained by the conventional method for determining the transport route.
Therefore, the problem to be solved by the present invention is to determine a transport route that can obtain the highest throughput in the linear tool.
A semiconductor processing system according to a representative embodiment of the present invention includes a plurality of transfer modules having a transfer robot for transferring a loaded object to be processed, a plurality of processing modules for processing the object to be processed, a transfer module, An operation control unit for controlling the operation of the processing module, and in the semiconductor processing system having a configuration in which the processing module is connected to one of the transfer modules and the transfer modules are connected to each other, the operation control unit is carried in For the plurality of objects to be processed, the transport route of each object to be processed is determined based on the time required for the transport operation in the transport module and the time required for the processing in the processing module .
In addition, a semiconductor processing method according to an embodiment of the present invention includes a plurality of transfer modules each having a transfer robot that transfers an object to be processed, and a plurality of processing modules that process the object to be processed. A semiconductor processing apparatus having a configuration in which the transfer modules are connected to each other and determining a transfer route of the object to be processed. Enter the time required and the time required for processing in the processing module.
Based on the input time required for the transfer operation and the time required for processing, the transfer routes of the plurality of objects to be transferred are determined .
According to the present invention, in the linear tool processing system, thereby improving the throughput.
It is a figure explaining composition of a semiconductor processing system. It is a figure explaining the variation of the structure of a semiconductor processing system. It is a figure which shows the transfer relationship of the information required for semiconductor processing system control. It is a figure explaining the flow of the process which determines a conveyance route. It is a figure explaining the process and input / output data which calculate the candidate of a conveyance route. It is a figure explaining the process which calculates a throughput, and input-output data. It is the figure explaining the process and input / output data which select a conveyance route. It is a figure explaining the conveyance order in a certain conveyance route candidate. It is the figure which showed the specific example of the process target wafer information. It is the figure which showed the specific example of the process process information. It is the figure which showed the specific example of the processing module information. It is the figure which showed the specific example of usable process module information. It is the figure which showed the specific example of conveyance destination candidate information. It is the figure which showed the specific example of apparatus structure information. It is the figure which showed the specific example of conveyance route candidate information. It is the figure which showed the specific example of operation time information. It is the figure which showed the specific example of the throughput information.
As shown in FIG. 1, the linear tool according to the present invention described below includes a plurality of transfer robots (105 to 106) disposed in an internal transfer region 102, and transfers wafers between the plurality of transfer robots, thereby performing load lock. 103 and the processing modules (107 to 110). By the way, a cluster tool usually has one transfer robot for transferring a wafer at an internal transfer site, but a linear tool is greatly different from a cluster tool in having a plurality of transfer robots.
FIG. 1 is a diagram illustrating a configuration of a semiconductor processing system according to the present invention. The processing system includes an external transfer part 101 that performs a physical transfer operation, an internal transfer part 102, and an operation control unit 113 that controls the operation thereof. In many semiconductor processing systems, the inside of the external transfer part 101 is kept in an atmospheric pressure state, and the inside of the internal transfer part 102 is kept in a vacuum state. The processing system 124 is connected to the host computer 122 via the network 123, and can acquire information from the host computer 122 as necessary. Hereinafter, each part will be described.
The external transfer site 101 loads and unloads a wafer to be processed outside the processing system into the processing system, and further loads and unloads the wafer to and from the load lock 103 connected to the internal transfer site 102. . The load lock 103 can perform depressurization and pressurization. After the wafer is transferred from the external transfer portion 101, the load lock 103 is depressurized and is brought into the same vacuum state as the internal transfer portion 102, thereby transferring the wafer to the internal transfer portion 102. Can be sent out. On the contrary, the wafer can be sent out to the external transfer part 101 by bringing the wafer from the internal transfer part 102 and then pressurizing it to bring it to atmospheric pressure.
The internal transfer part 102 includes a standby space 104 installed between the transfer modules 105 and 106 and a plurality of transfer modules and processing modules 107, 108, 109 and 110. A transfer robot 111 is provided in the transfer module 105, and a transfer robot 112 is provided in the transfer module 106. Processing modules adjacent to the transfer module, load lock, loading and unloading of wafers in a standby space, and processing modules thereof, Wafer moves between load lock and standby space.
The processing module has a function of performing processing such as etching on the wafer. A gate valve is installed at the wafer loading / unloading port of the processing module, and is closed when processing is performed, and is opened when wafers are loaded and unloaded.
The standby space includes a space for placing a wafer, and each transfer robot of an adjacent transfer module can carry in and out the wafer. Therefore, after one transfer robot carries the wafer into the standby space and the operation is finished, the other transfer robot can carry out the wafer from the standby space, so that delivery can be performed between the transfer modules.
The operation control unit 113 is a computer configured by a microprocessor, a memory, and the like, and includes a transport route determination calculation unit 114, an operation instruction calculation unit 115, and a storage unit 116. The transport route determination calculation unit 114 performs processing related to determination of the transport route of the present invention.
Based on the transfer route determined by the transfer route determination calculation unit 114, the operation instruction calculation unit 115 loads and unloads and moves the wafer by the transfer robot, depressurizes and pressurizes the load lock, processes the processing module, and opens and closes the gate valve. Control individual operations. The storage unit 116 holds processing target wafer information 117, operation time information 118, processing step information 119, apparatus structure information 120, and processing module information 121, which are information necessary for arithmetic processing. Among these, the processing module information 121 is generated by sensors in the processing modules 107, 108, 109, and 110 and is transmitted to the operation control unit 113 as needed.
On the other hand, the processing target wafer information 117, the operation time information 118, the processing process information 119, and the apparatus structure information 120 are managed in the host computer 122 connected to the semiconductor processing system through the network 123. The data is transmitted from the host computer 122 to the operation control unit 113.
What is constituted by the internal transfer part 102, the operation control unit 113, the host computer 122, and the like described above will be referred to as a semiconductor processing system 124 herein.
The semiconductor processing system 124 can change the structure of the internal transfer site 102. As illustrated in FIGS. 2a) and b), processing modules (207-212 or 207′-212 ′), transport modules (213-215 or 213′-215 ′), standby spaces (202-203 or 202′- 203 ') can be freely changed. As a condition for arrangement, the processing module and the standby space are always adjacent to the transfer module. In the description of the present embodiment, the description will be made on the assumption of the arrangement of the internal conveyance site shown in FIG. 1, but this is an example and does not limit the present invention.
Next, operation control of the semiconductor processing system 124 will be described. First, a transfer route is determined for each wafer to be processed. Here, unless otherwise specified, the transfer route used in the present embodiment is processed in the processing module after the wafer to be processed is loaded into the processing system, and is carried out of the processing system. It shall indicate the route that passes by. Based on the transfer route and the transfer route, individual operations such as wafer loading / unloading and movement by the transfer robot, load lock pressure reduction and pressurization, processing module processing, and gate valve opening / closing are performed. There are the following methods for determining the individual operations.
(1) Schedule method In the schedule method, individual operations necessary for transporting each wafer to be processed on the determined transport route are calculated in advance, and individual operations are determined in advance, and individual operations are performed accordingly. The operation is performed. There are various variations in the logic for calculating the individual operations depending on the purpose. The purpose includes maximizing the operation rate of the processing module and maximizing the throughput.
(2) Dispatch method In the dispatch method, conditions for starting operations are set for individual operations such as wafer loading / unloading and movement by a transfer robot, load lock decompression and pressurization, processing module processing and gate valve opening / closing. In addition, this is a method in which the operation is performed when the conditions are met. For example, as a condition for opening a gate valve of a certain processing module, “the transfer robot holds a wafer to be loaded into the processing module” “no processing is performed on another wafer in the processing module” "A gate valve of another processing module is closed" is set as a rule, and when the condition is met, an operation of opening the gate valve is performed.
Such operating condition rules are set for each individual operation. In addition, for a plurality of operations, the conditions for starting the operation may be met. In such a case, a priority rule that determines which operation has priority is also set. As an example of the priority rule, there is one that performs the operation with the operation start conditions all the fastest.
As described above, there are several methods of operation control, and there are various variations in the detailed calculation logic and conditions. In the description of the present embodiment, a semiconductor processing system in which operation control is performed so that priority is given to an operation having the operation start condition that is the earliest as a priority rule when the operation start condition is simultaneously prepared in the dispatch method. Although described as a premise, this is an example and does not limit the present invention.
Next, a series of operations of the processing system 124 for one wafer to be processed will be described. In the following, descriptions of operations are listed in order using FIG. Note that FIG. 3 shows the exchange relationship of information required for control of the semiconductor processing system 301, and the reference numerals corresponding to those in FIG.
The processing target wafer information 117 [305], operation time information 118 [306], processing step information 119 [307], and apparatus structure information 120 [308] are received from the host computer 122 [302] before the processing target wafer arrives. It is transmitted to the operation control unit 113 [303].
The processing module information 121 is transmitted from the processing modules 107 to 110 to the operation control unit as needed.
When the wafer to be processed arrives, the external transfer part 101 reads the identification information of the target wafer and transmits the information to the operation control unit 113.
Since the operation control unit 113 holds in advance the data of the processing steps corresponding to the target wafer and the state of the processing modules 107 to 110, based on the data and the data of the target wafer, the operation control unit 103 determines the transfer route. To decide.
Suppose that the processing module 109 becomes the processing module of the transfer destination.
The external transfer site 101 carries the wafer into the load lock 103.
After the gate valve on the external transfer site 101 side of the load lock 103 is closed, the load lock 103 is depressurized and the inside of the load lock 103 is evacuated.
The gate valve on the internal transfer site 103 side opens, and the transfer robot 111 unloads the wafer from the load lock 103.
The transfer robot 111 turns while holding the wafer until it faces the standby space, and then places the wafer in the standby space 104.
The other transfer robot 112 takes out the wafer from the standby space 104.
The transfer robot 112 is rotated until it faces the processing module 109 while holding the wafer, and then the gate valve of the processing module 109 is opened, and the transfer robot 112 carries the wafer into the processing module 109.
Processing is performed by the processing module 109.
After the processing is completed, the gate valve of the processing module 109 is opened, and the transfer robot 112 unloads the wafer from the processing module 109.
The transfer robot 112 turns while holding the wafer until it faces the standby space 104, and then places the wafer in the standby space 104.
The other transfer robot 111 takes out the wafer from the standby space 104.
The transfer robot 111 turns while holding the wafer until it faces the load lock 103, then the gate valve of the load lock 103 is opened, and the transfer robot 111 carries the wafer into the load lock 103.
-After the gate valve on the internal conveyance site 102 side of the load lock 103 is closed, the load lock 103 is pressurized to bring the inside of the load lock 103 into an atmospheric pressure state.
The gate valve on the external transfer part 101 side of the load lock 103 is opened, and the external transfer part 101 carries the wafer out of the load lock 103.
The external transfer site 101 stores the wafer in a wafer storage location outside the semiconductor processing system 124 [301].
As shown in FIG. 3, the control signal from the host computer 302 is transmitted to the semiconductor processing system 301 via the network 300.
The series of operations described here is for a single wafer, but the semiconductor processing system 124 can handle a plurality of wafers simultaneously. A lot case loaded with a plurality of wafers arrives at the semiconductor processing system 124 [301], and performs the above operation on each wafer. It is also possible to simultaneously target a plurality of lot cases. When carrying and processing multiple wafers simultaneously in this way, the start conditions of individual operations such as opening and closing of the transfer robot and gate valve may be satisfied at the same time. Done in order.
Next, the outline of the transport route determination process of the present invention will be described with reference to FIG. First, a transport route candidate calculation 401 is performed. In the transfer route candidate calculation process 401, available process module candidates are calculated from the process steps and process module states according to the wafer type for the processing target wafer, and the transfer route candidates are calculated based on the calculated process module candidates. To do. Details of the processing will be described later.
Next, the throughput is calculated 402 for each conveyance route candidate calculated in the process 401. In the throughput calculation process 402, scheduling is performed based on the given transfer route, the transfer order in the transfer route is calculated, and the throughput, which is the number of transfer wafers per unit time, is calculated based on this. Details of the processing will be described later. This process 402 is repeated until completion for all the conveyance routes. When the process 402 is completed for all the conveyance routes, the best conveyance route is selected. In the transport route selection process 403, the throughputs of the respective transport route candidates calculated in the process 402 are compared, and the transport route having the best throughput is selected. Details of the processing will be described later. From the above, the best transport route is determined.
Next, details of the conveyance route candidate calculation process will be described with reference to FIG. First, in the available processing module extraction step 501, processing target wafer information 305, processing process information 307, and processing module information 309 are input, and usable processing module information 502 is generated 503. The processing target wafer information 305 is information representing a wafer number that is an identification number of the processing target wafer as illustrated in FIG. 9 and processing steps to be performed on each wafer. The processing process information 307 is information indicating the processing process as illustrated in FIG. 10, the process order included in the processing process, the condition of the processing module performing the process in the process order, and the processing time in the process. It is. For example, in process step 1, process module condition A and process time 20 in process order 1 and process module condition B and process time 20 in process order 2 mean process module condition A for a wafer having process process 1. This means that processing is performed in a processing module satisfying the condition 20 in processing time 20 and then processing is performed in processing time 20 in a processing module satisfying processing module condition B. The processing module information 309 is information representing each processing module as exemplified in FIG. 11 and the conditions of the processing module. By combining the above information, usable processing module and processing time information can be obtained in each process order of each wafer as illustrated in FIG. When there are a plurality of usable processing modules in a certain process sequence of a certain wafer, all the processing modules are usable processing modules.
Next, in the use processing module candidate generation step 503, the available processing module information 502 is input, and the transport destination candidate information 504 is generated. In this step, one processing module to be used is selected in each process order of each wafer, and it is set as one of the transfer destination candidates. Next, in a certain process order of a certain wafer, the selected processing module is changed to another usable processing module as another transfer destination candidate. The above procedure is repeated until all usable processing modules are selected in each process order of each wafer, and the transfer destination candidates are exhaustively extracted. Thereby, transport destination information as illustrated in FIG. 13 is generated.
Next, in transport route candidate generation step 503, transport destination candidate information 504 and apparatus structure information 308 are input to generate transport route candidates. The device structure information 308 is information representing a module of a device as illustrated in FIG. 14 and a transfer robot connected thereto. Here, regarding the symbols used in FIG. 14, the correspondence with FIG. 1 is summarized. In the following, for the sake of simplicity, the reference numerals are indicated by numerals, and the respective reference numerals are those shown in FIG. That is, LL: 103, VR1 to VR2: 111 to 112, WS1: 104, PM1 to PM4: 107 to 110 are in correspondence.
For example, LL in FIG. 14 represents the load lock 103, which indicates that the load lock is connected to the transport robot VR1 (111). Similarly, PM1, PM2, PM3, and PM4 represent processing modules, and WS1 represents a standby space, which are connected to the transfer robots VR1 and VR2, respectively. In this step, a transfer route that passes through the use processing module in the order of the set process order is extracted based on the apparatus structure information for a wafer with a transfer destination candidate in the transfer destination candidate information 504.
The wafer transfer starts from a load lock (LL), is transferred by a connected transfer robot, is processed by each processing module, and is transferred to the load lock by the transfer robot. For example, as shown in FIG. 13, for transfer destination candidate number 2 and wafer number W1, processing is performed by processing module PM1 in process order 1 and processing module PM3 in process order 2. In this case, as shown in FIG. 14, since VR1 is connected to both LL and PM1 when first transported from LL to PM1, it is transported from LL to PM1 by VR1. This transport operation is described as LL → PM1 (see FIG. 15).
Next, when transferring from PM1 to PM3, PM1 is connected to VR1, PM3 is connected to VR2, and VR1 and VR2 are connected to WS1, so VR1 and VR2 deliver wafers by WS1. Therefore, the sheet is conveyed from PM1 to the standby space WS1 by VR1. This transport operation is described as PM1 → WS1 (see FIG. 15).
Next, it is conveyed from WS1 to PM3 by VR2. This transport operation is described as WS1 → PM3. Similarly, when transporting from PM3 to LL, transport operations of PM3 → WS1 and WS1 → LL are performed (see FIG. 15). This transfer operation order is defined as a transfer order, and for each wafer of a certain transfer destination candidate, the transfer operation, transfer order, and transfer robot extracted are set as transfer route candidates. This transport route candidate extraction is performed for all transport destination candidates. The result is conveyance route candidate information as illustrated in FIG.
Next, details of the throughput calculation process will be described with reference to FIG. Throughput calculation processing 601 receives transport destination candidate information 504, transport route candidate information 506, and operation time information 306, and generates throughput information 602. In this step, first, for a certain transport route candidate, processing in the transport destination candidate module from the transport route candidate information 506 to the transport order, transport operation, transport robot information, and the transport destination candidate number corresponding to the transport destination candidate number from the transport destination candidate information 504 From the time information and the operation time information 306, information on the corresponding transfer robot and the operation time of the transfer operation is extracted. The extracted information is used as an input for simulation. The simulation is performed according to a method set as operation control.
In the description of the present embodiment, a simulation based on the premise of operation control in which priority is given to an operation having the operation start condition that is the earliest will be described as a priority rule in the dispatch method when the operation start conditions are simultaneously prepared. .
Simulation is a calculation procedure that arranges operations while advancing time. As a simulation calculation example, the transport destination candidate number 1 illustrated in FIG. 15 will be described. As a condition, when a lot having wafer numbers W1, W2, and W3 arrives, another lot has already been processed, and the wafer number W0 of the other lot is being processed in PM4 and the remaining processing time 35 is being simulated. Shall be performed. Further, it is assumed that the rules are input in the order of W1, W2, and W3. In the explanation of this example, for the sake of simplicity, the operation of the external transfer part and the operation of the gate valve are omitted, and only the operation of the transfer robot and the processing module is simulated.
The operation simulation will be described below with reference to FIG.
First, at time 0, W1 is stored in LL, no wafer is stored in PM1 and PM2, and W0 is stored in PM4, and processing starts. In this case, the operation start condition for VR1 to carry W1 out of LL and carry it into PM1 is satisfied. Therefore, the operations are arranged as shown in the figure. Next, the time is advanced to a time when any operation is completed and the operation start condition may be changed. In this example, the operation of LL → PM1 (W1) by VR1 is the required time 10 based on the conditions shown in FIG. Therefore, the time is advanced to 10. Here, it is checked whether or not there is an operation that satisfies the operation start condition. Since W1 is carried into PM1, the operation start condition for the processing of PM1 is satisfied. Therefore, the operations of W1 in PM1 are arranged with time 10 as the starting point.
Next, from the condition shown in FIG. 16, the processing time for W1 in PM1 is 20, so the time is advanced to 30. Here, the operation of PM1 → PM2 (W1) by VR1 is an operation start condition and the processing for W0 by PM4 is completed, and the operation start condition of PM4 → WS1 (W0) by VR2 is satisfied. Line up as
Next, if it advances to time 35, operation of PM4-> WS1 (W0) by VR2 will be completed. Here, there is no operation with the same operation start condition, but there is a processed wafer in WS1 which is one of the operation start conditions of WS1 → LL (W0) by VR1, and VR1 does not hold a wafer. It will wait for it to become a state. Here, at time 40, it is assumed that W2 is stored in LL by the external conveyance site. Therefore, when the time is advanced to time 40, VR1 is in a state of not holding the wafer, and WS1 → LL (W0) by VR1, LL → PM1 (W2) by VR1, and the operation start conditions of the processing of W1 by PM2 are respectively set. It is filled. Here, WS1 → LL (W0) by VR1 and LL → PM1 (W2) by VR1 are both VR1 operations and cannot be performed simultaneously. Therefore, according to the priority rule that priority is given to the operation having the operation start condition that is the earliest, in this example, WS1 → LL (W0) by VR1 is waiting for the state in which VR1 is not holding a wafer from time 35. Therefore, give priority to this operation. Further, since the processing of W1 can be performed in parallel with PM2, WS1 → LL (W0) by VR1 and the processing of W1 with PM2 are arranged with time 40 as the starting point.
Next, when time 45 is reached, since the operation start condition of LL → PM1 (W2) by VR1 is satisfied, the time 45 is arranged as the start point. The process of arranging the operations while advancing the time as described above is repeated until all the operations from the completion of the processing to the transfer to the outside are completed for all the processing target wafers. In this example, the VR1 arranges the operations for transferring the wafer W3 from PM2 to LL, so that all the operations are completed.
From the result of this simulation, the completion time of the operation with the latest completion time among all the operations can be obtained. Since this time is the time required for transfer and processing, the throughput, which is the number of processed wafers per unit time, can be calculated by dividing the number of processed wafers by this required time. For example, in the example of FIG. 8, PM2 → LL (W3) by VR1 is the last operation, and the time is 165. Therefore, the throughput in the case of the transport route candidate number 1 is 3 / 165≈0.018. By performing such simulation and calculation of throughput calculation for all transport route candidates, throughput information for each transport route candidate as illustrated in FIG. 17 is obtained.
Next, the transport route selection process will be described with reference to FIG. The transport route selection processing 701 inputs throughput information 602 and generates transport route information 702. The transport route information 702 is a transport route for actually transporting, and the transport operation is controlled based on this information. In this step, the throughput is compared based on the throughput information of each conveyance route candidate calculated in the throughput calculation process, and the conveyance route candidate having the highest throughput is determined as the conveyance route. In this example, as shown in FIG. 17, the transport route candidate 1 is 0.018 and the transport route candidate 2 is 0.019, so the transport route of the transport route candidate 2 has the highest throughput. As determined.
As another embodiment of the present invention, instead of the transport route candidate calculation process, a form in which a plurality of transport routes are given from another system or a form input by a person may be used.
As another embodiment of the present invention, instead of the throughput calculation process, the throughput may be obtained from the throughput information separately prepared for each transport route.
101: External conveyance site,
102: Internal conveyance site,
103: load lock,
104: waiting space,
105, 106: transfer module,
107, 108, 109, 110: processing modules,
111, 112: transfer robot,
113: Operation control unit,
114: Transport route determination calculation,
115: Operation instruction calculation unit,
116: Storage unit,
117: Process target wafer information,
118: Operating time information,
119: Processing process information,
120: Device structure information,
121: Processing module information,
122, 302: host computer,
123,300: network,
124, 301: Semiconductor processing system,
401: Transport route candidate calculation processing,
402: Throughput calculation processing,
403: Transport route selection processing.
A plurality of transfer modules having a transfer robot for transferring a workpiece to be loaded;
A plurality of processing modules for processing the object to be processed;
An operation control unit that controls operations of the transfer module and the processing module,
In the semiconductor processing system, the processing module is connected to one of the transfer modules, and the transfer modules are connected to each other.
The operation control unit generates a plurality of transport routes for the target object for a plurality of target objects to be carried in , based on the time required for the transport operation in the transport module and the time required for the process in the processing module, A semiconductor processing system , wherein one transport route is determined from the plurality of transport routes by calculating a throughput of each transport route .
2. The semiconductor processing system according to claim 1, wherein a time required for the transfer operation in the transfer module is determined for each transfer operation in a route in which the object to be processed is transferred.
2. The semiconductor processing system according to claim 1, wherein a time required for processing in the processing module is determined for each object to be processed.
The semiconductor processing system according to claim 1 .
The operation control unit selects and determines a transport route having the highest throughput from among the plurality of transport routes for the transport route of the object to be processed.
The operation control unit includes a processing module extraction unit that extracts an available processing module from the plurality of processing modules;
A transport route generating means for generating a plurality of transport routes based on the extracted information of available processing modules;
A semiconductor processing system comprising:
The semiconductor processing system according to claim 5 .
The operation control unit generates transport destination candidate information to transport the object to be processed based on the extracted information of the available processing modules,
The transfer route generation means generates a transfer route for transferring the object to be processed using the generated transfer destination candidate information and the structure information of the semiconductor processing apparatus stored in advance in a storage device. A characteristic semiconductor processing system.
The semiconductor processing system according to claim 6 .
The operation control unit performs a plurality of simulations for arranging operations performed by the transfer module and the processing module in time series based on the transfer destination candidate information, the transfer route candidate information, and the structure information of the semiconductor processing apparatus. A semiconductor processing system characterized in that the throughput of the plurality of transport routes is calculated from the result of each simulation performed on the transport routes.
The transfer module and the processing module are kept in a vacuum state, and one of the transfer modules is connected to a load lock capable of switching between a vacuum state and an atmospheric pressure state by depressurization and pressurization, body is a semiconductor processing system according to any one of claims 1 to 7, characterized in that it is carried to one of the transfer module via the load lock.
The semiconductor processing system according to any one of claims 1 to 8 wherein the plurality of transport modules, characterized in that it is connected to each processing module.
A plurality of transfer modules each having a transfer robot for transferring an object to be processed; and a plurality of processing modules for processing the object to be processed; the processing module being connected to one of the transfer modules; and the transfer module A method of determining a transport route of the object to be processed in a semiconductor processing apparatus having a configuration in which they are connected to each other,
For the object to be loaded, input the time required for the transfer operation in the transfer module and the time required for the process in the processing module,
For each of the plurality of objects to be carried in, a plurality of transfer routes are generated, and the throughput of each transfer route is calculated based on the input time required for the transfer operation and the time required for processing in the processing module. A semiconductor processing method characterized in that one transport route is determined from the plurality of transport routes .
The semiconductor processing method according to claim 10 , wherein a time required for the transfer operation in the transfer module is determined for each transfer operation in a route in which the object to be processed is transferred.
The semiconductor processing method according to claim 10 , wherein a time required for processing in the processing module is determined for each object to be loaded.
11. The semiconductor processing method according to claim 10 , wherein a transfer route having the highest throughput is selected and determined from among the plurality of transfer routes for the transfer route of the object to be processed.
The semiconductor processing method according to claim 10 .
Extract available processing modules from the plurality of processing modules;
A semiconductor processing method, comprising: generating a plurality of transfer routes based on the extracted information of available processing modules.
The semiconductor processing method according to claim 14 .
Based on the extracted information on the available processing modules, the transport destination candidate information for transporting the object to be processed is generated,
A semiconductor processing method characterized by generating a transfer route for transferring the object to be processed using the generated transfer destination candidate information and structure information of a semiconductor processing apparatus stored in a storage device in advance.
The semiconductor processing method according to claim 15 .
Based on the transfer destination candidate information, the transfer route candidate information, and the structure information of the semiconductor processing apparatus, a simulation for arranging the operations performed by the transfer module and the processing module in time series is performed for a plurality of transfer routes. A semiconductor processing method, wherein throughput of the plurality of transport routes is calculated from a result of each simulation.
The transfer module and the processing module are kept in a vacuum state, and one of the transfer modules is connected to a load lock capable of switching between a vacuum state and an atmospheric pressure state by depressurization and pressurization, body is a semiconductor processing method according to any one of claims 10 to 16, characterized in that it is carried to one of the transfer module via the load lock.
Wherein the plurality of transport modules, semiconductor processing method according to any one of claims 10 to 17, characterized in that it is connected to each processing module.
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