Source: https://patents.justia.com/patent/8846498
Timestamp: 2020-01-19 10:48:53
Document Index: 267846609

Matched Legal Cases: ['Application No. 61', 'art 100', 'art 100', 'art 100', 'art 100', 'art 100']

US Patent for Wafer dicing using hybrid multi-step laser scribing process with plasma etch Patent (Patent # 8,846,498 issued September 30, 2014) - Justia Patents Search
Justia Patents By Electromagnetic Irradiation (e.g., Electron, Laser, Etc.)US Patent for Wafer dicing using hybrid multi-step laser scribing process with plasma etch Patent (Patent # 8,846,498)
Wafer dicing using hybrid multi-step laser scribing process with plasma etch
Jan 6, 2014 - Applied Materials, Inc.
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a multi-step laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.
This application is a continuation of U.S. patent application Ser. No. 13/851,442, filed on Mar. 27, 2013, which claims the benefit of U.S. Provisional Application No. 61/622,398, filed Apr. 10, 2012, the entire contents of which are hereby incorporated by reference herein.
Embodiments of the present invention pertain to methods of, and apparatuses for, dicing semiconductor wafers or substrates.
In an embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a multi-step laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The multi-step laser scribing process involves scribing with two or more offset but overlapping Gaussian beam passes and, subsequently, scribing with a top hat beam pass overlapping the Gaussian beam passes. The method also involves etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.
In another embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a multi-step laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The multi-step laser scribing process involves scribing with two or more offset but overlapping Gaussian beam passes and, subsequently, scribing with a broad Gaussian beam pass overlapping the Gaussian beam passes. The method also involves etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.
In another embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask layer above a silicon substrate, the mask layer covering and protecting integrated circuits disposed on the silicon substrate. The integrated circuits include a layer of silicon dioxide disposed above a layer of low K material and a layer of copper. The method also involves patterning the mask layer, the layer of silicon dioxide, the layer of low K material, and the layer of copper with a multi-step laser scribing process to provide a patterned mask layer with gaps, exposing regions of the silicon substrate between the integrated circuits. The multi-step laser scribing process involves scribing with two or more offset but overlapping Gaussian beam passes and, subsequently, scribing with a top hat beam pass or with a broad Gaussian beam pass overlapping the Gaussian beam passes. The method also involves etching the silicon substrate through the gaps in the patterned mask layer to singulate the integrated circuits.
FIG. 3 illustrates a schematic of (a) a Gaussian beam profile and (b) a top hat beam profile, in accordance with an embodiment of the present invention.
FIGS. 4A-4D illustrate representative operations in a multi-step laser beam ablation process, in accordance with an embodiment of the present invention.
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon, are described. In the following description, numerous specific details are set forth, such as multi-step laser scribing approaches and plasma etching conditions and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
One or more embodiments described herein are directed to multi-step femto-send laser scribing of wafers. In one embodiment, a laser scribing plus plasma etch hybrid process is used to singulate integrated circuit (IC) chips from wafers. Other embodiments include MEMs wafer dicing. For a femtosecond laser scribing plus plasma etch hybrid process, a femtosecond laser may be used to cleanly remove a mask layer, organic and inorganic dielectric layers and device layers and etch stop layers. Subsequently, a plasma may be used to etch through a silicon layer to achieve chip singulation or dicing. The femtosecond laser based technology may have unique advantages when a wafer thickness is approximately 100 microns or thinner, especially around 50 microns or less. Femtosecond laser based technology may also have unique advantages when kerf width of around 15 microns or less is sought.
For IC memory chips, as memory capacity increases, multichip functions and continuous packaging miniaturization may require ultra thin wafer dicing. For logic device chips/processors, major challenges lie in IC performance increase, low k materials and other material adoption. Wafer thickness reduction such a case may not be a major driver and, typically, wafer thicknesses in the range of approximately 100 microns to 760 microns are used for major applications to ensure sufficient chip integrity. Processor chip designers/chip makers may place test element groups (TEGs or test patterns) as well as alignment patterns in wafer streets. On one hand, such test patterns may be completely removed during a chip singulation process. On the other hand, the complexity of the test patterns may dictate that the dimensions of the test patterns remain relatively large, typically in the 50 micron to 100 micron range perpendicular to the wafer street. A kerf width approximately in the range of 50 microns to 100 microns, at least at the top surface of the wafer, may thus be needed to completely remove the test patterns. As such, for logic device wafer singulation, a major focus is to achieve delamination-free and efficient dicing processes.
Thus, in an aspect of the present invention, a combination of a multi-step laser scribing process with a plasma etching process may be used to dice a semiconductor wafer into singulated integrated circuits. FIG. 1 is a Flowchart 100 representing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits, in accordance with an embodiment of the present invention. FIGS. 2A-2C illustrate cross-sectional views of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operations of Flowchart 100, in accordance with an embodiment of the present invention.
Referring to operation 104 of Flowchart 100, and corresponding FIG. 2B, the mask 202 is patterned with a multi-step laser scribing process to provide a patterned mask 208 with gaps 210, exposing regions of the semiconductor wafer or substrate 204 between the integrated circuits 206. As such, the laser scribing process is used to remove the material of the streets 207 originally formed between the integrated circuits 206. In accordance with an embodiment of the present invention, patterning the mask 202 with the multi-step laser scribing process includes forming trenches 212 partially into the regions of the semiconductor wafer 204 between the integrated circuits 206, as depicted in FIG. 2B.
In an embodiment, the multi-step laser scribing process includes scribing with two or more offset but overlapping Gaussian beam passes and, subsequently, scribing with a top hat beam pass overlapping the Gaussian beam passes. In one such embodiment, the two or more offset but overlapping Gaussian beam passes are performed sequentially. In another such embodiment, the two or more offset but overlapping Gaussian beam passes are performed simultaneously. In an alternative embodiment, the overlapping Gaussian beam passes are followed instead by a subsequent Gaussian pass of a beam diameter and parameter set different from the initial offset Gaussian passes. For example, in one embodiment, a subsequent broad Gaussian approach using a properly defocused beam or a large focused beam may be used for the cleaning in place of a top hat beam.
In an embodiment, a multi-step laser scribing process includes a bulk target layer material removal. First, a solid state UV laser Gaussian beam is used to scribe the wafer surface to remove a mask layer, a passivation layer, and a device layer to the desired kerf width. The scribing process may be a single beam with multiple passes with each pass overlaps to certain level to the next pass in the direction normal to the laser scribing direction (or along with street width direction) to achieve a desired kerf width, or a single pass scribing via multiple beams. In either case, in one embodiment, the first aspect of the scribing process is used to completely remove test pattern features. The UV laser may have a wavelength approximately in the range of 250 nanometers to 400 nanometers, and more particularly approximately in the range of 300 nanometers to 380 nanometers. The pulse width may be approximately in the range of 1 picosecond to 50 nanoseconds, and more particularly approximately in the range of 5 picoseconds to 50 picoseconds. Such a pulse width range may not necessarily fully eliminate delamination and chipping, but at least may be used to control delamination and chipping near the scribed trench generated by not penetrating through a sealing rings of the individual dies. The focused laser spot diameter may be approximately in the range of 20 microns to 75 microns, and more particularly approximately in the range of 25 microns to 50 microns.
It is to be understood that it may be difficult to meet pulse energy requirements with a femtosecond laser as a larger laser spot is typically required. For example, if 2 microjoules (2 uJ) is needed for a 10 micron spot, the equivalent pulse energy for a 50 microns spot is (50/10)^2×2 uJ=50 uJ in order to maintain a same fluence or intensity. Such a proportionality may be very expensive to achieve on a femtosecond UV laser, but may be fairly inexpensive easy for a nanosecond or picosecond UV laser. In an embodiment, an approximately 10-20 micron or thicker mask layers is used for etching thick wafers. In an embodiment, the laser has a pulse repetition frequency approximately in the range of 80 kHz to 1 MHz, and particularly approximately in the range of 100 kHz to 500 kHz.
Throughout the above described first laser scribing operation, in one embodiment, most target materials are removed and silicon substrate is primarily exposed. However, due to the overlapping of multiple passes or multiple beams, heavy debris deposition on the opened substrate surface may not be directly etchable. Furthermore, the formed trench bottom surface may be quite rough.
Existing plasma etch technology has been focused on target material with a flat surface, since understanding of etch performance on a very rough surface may be limited. However, an etch rate (both directional and isotropic) may be homogeneous at different spots regardless of the surface topography (e.g., regardless if the surface is flat/smooth or rough). As such, the rough surface topography should be maintained as the formed trench is etched deeper. But in reality, in an embodiment, for a slightly rough surface, the surface is smoothened as etching proceeds. For a very rough surface, however, the etch depth at different location (trough or ridge locations) may be non-matching. Thus, in one embodiment, so long as the scribed surface is relatively smooth and free of debris, a good clean etch is achieved.
Accordingly, in an embodiment, following the bulk target layer material removal, a scribed trench cleaning operation is performed prior to etching. In one such embodiment, a top-hat spatial profiled solid state UV laser beam with the dimension (diameter in case of a round top hat beam or side length of a square top hat beam) approximately in the range of roughly 50 to 75% of the trench width opened in the first laser scribing operation is applied to gently clean and smoothen the trench surface as to remove the debris. Trench cleaning with a large top hat beam in a single pass may be important for the subsequent plasma etch characteristic. In one such embodiment, the trench opened via laser scribing has to be clean enough in order to achieve a consistently clean etched channel. Although a qualified trench for clean plasma etch may be generated in a single operation (with one or more passes) of laser scribing, in an embodiment, the laser-scribing-for-etching process is partitioned into two phases: phase 1 includes bulk removal of target material by laser ablation to form the trench, while phase is directed to trench cleaning to expose the silicon substrate uniformly and consistently by laser ablation. The post-laser scribing trench may be a fresh silicon surface free of metals, dielectrics and polymers. However, due to the wide kerf width generated with multiple passes/multiple beams, it may be conceived that the cross-contamination between the newly generated pass and the previous pass is unavoidable. Accordingly, it may not be feasible to use only a Gaussian beam to uniformly clean the wide trench without significantly melting the silicon substrate. In an embodiment, the subsequently used top hat beam is set at roughly 25%-50% of the average fluence of that used in the first (Gaussian) step, with a guideline that it may gently melt the silicon surface at maximum.
In an example, FIG. 3 illustrates a schematic of (a) a Gaussian beam profile 300 and (b) a top hat beam profile 320, which are shown overlying one another in plot 340, in accordance with an embodiment of the present invention.
In another example, FIGS. 4A-4D illustrate representative operations in a multi-step laser beam ablation process, in accordance with an embodiment of the present invention. Referring to FIG. 4A, a water soluble mask 402 is applied to a wafer 404. Referring to FIG. 4B, a UV Gaussian beam is applied for bulk material removal. In this example, three passes 406, 408 and 410 are used. The three passes may be performed sequentially or simultaneously, and with the same or with different beams. Referring to FIG. 4C, a UV top hat beam trench cleaning operation is performed to provide a unified trench 412. Referring to FIG. 4D, a plasma etch is performed to provide a deep trench 414. Although not depicted, following the beam passes and the etch process, the water soluble mask 402 may then be washed away.
In an embodiment, the above described multi-step laser ablation process is used for dicing wafers having a thickness greater than approximately 100 microns. Advantages may include avoidance of back side chipping otherwise caused by diamond saw dicing (e.g., the average size of back side chipping in a laser+saw dicing process is approximately 20 microns versus the average size of backside chipping in a pure saw dicing is approximately 40 microns.) The plasma etching process that follows (examples of which are provided below) may enable higher overall process throughput compared to laser plus saw dicing. Furthermore, front side defects (such as chipping propagation due to mechanical stress generated by mechanical dicing) may be reduced. The adoption of a nanosecond or picosecond UV laser may enable ablation of very thick mask layers which may be necessary to carry the thick silicon etch process in addition to the polyimide layers and other layers on wafers since abundant pulse energy may be available on such lasers even at high frequency.
Even with the use of multi-step laser scribing, the use of a femtosecond-based laser (versus, e.g., a picoseconds-based laser or a nanosecond-based laser) may be used to further optimize ablation performance of a complex stack of layers undergoing a singulation process. Thus, in an embodiment, patterning the mask 206 with the laser scribing process includes using a laser having a pulse width in the femtosecond range. Specifically, a laser with a wavelength in the visible spectrum plus the ultra-violet (UV) and infra-red (IR) ranges (totaling a broadband optical spectrum) may be used to provide a femtosecond-based laser, i.e., a laser with a pulse width on the order of the femtosecond (10−15 seconds). In one embodiment, ablation is not, or is essentially not, wavelength dependent and is thus suitable for complex films such as films of the mask 202, the streets 207 and, possibly, a portion of the semiconductor wafer or substrate 204.
Under conventional laser irradiation (such as nanosecond-based or picosecond-based laser irradiation), the materials of street 600 behave quite differently in terms of optical absorption and ablation mechanisms. For example, dielectrics layers such as silicon dioxide, is essentially transparent to all commercially available laser wavelengths under normal conditions. By contrast, metals, organics (e.g., low K materials) and silicon can couple photons very easily, particularly in response to nanosecond-based or picosecond-based laser irradiation. In an embodiment, a multi-step laser scribing process is used to pattern a layer of silicon dioxide, a layer of low K material, and a layer of copper with a femtosecond-based laser scribing process by ablating the layer of silicon dioxide prior to ablating the layer of low K material and the layer of copper.
Referring to operation 106 of Flowchart 100, and corresponding FIG. 2C, the semiconductor wafer 204 is etched through the gaps 210 in the patterned mask 208 to singulate the integrated circuits 206. In accordance with an embodiment of the present invention, etching the semiconductor wafer 204 includes ultimately etching entirely through semiconductor wafer 204, as depicted in FIG. 2C, by etching the trenches 212 initially formed with the multi-step laser scribing process.
In an embodiment, etching the semiconductor wafer 204 includes using a plasma etching process. In one embodiment, a through-silicon via type etch process is used. For example, in a specific embodiment, the etch rate of the material of semiconductor wafer 204 is greater than 25 microns per minute. An ultra-high-density plasma source may be used for the plasma etching portion of the die singulation process. An example of a process chamber suitable to perform such a plasma etch process is the Applied Centura® Silvia™ Etch system available from Applied Materials of Sunnyvale, Calif., USA. The Applied Centura® Silvia™ Etch system combines the capacitive and inductive RF coupling, which gives much more independent control of the ion density and ion energy than was possible with the capacitive coupling only, even with the improvements provided by magnetic enhancement. This combination enables effective decoupling of the ion density from ion energy, so as to achieve relatively high density plasmas without the high, potentially damaging, DC bias levels, even at very low pressures. This results in an exceptionally wide process window. However, any plasma etch chamber capable of etching silicon may be used. In an exemplary embodiment, a deep silicon etch is used to etch a single crystalline silicon substrate or wafer 404 at an etch rate greater than approximately 40% of conventional silicon etch rates while maintaining essentially precise profile control and virtually scallop-free sidewalls. In a specific embodiment, a through-silicon via type etch process is used. The etch process is based on a plasma generated from a reactive gas, which generally is a fluorine-based gas such as SF6, C4F8, CHF3, XeF2, or any other reactant gas capable of etching silicon at a relatively fast etch rate. In an embodiment, the mask layer 208 is removed after the singulation process, as depicted in FIG. 2C.
Accordingly, referring again to Flowchart 100 and FIGS. 2A-2C, wafer dicing may be preformed by initial ablation using a multi-step laser scribing process to ablate through a mask layer, through wafer streets (including metallization), and partially into a silicon substrate. Die singulation may then be completed by subsequent through-silicon deep plasma etching. A specific example of a materials stack for dicing is described below in association with FIGS. 7A-7D, in accordance with an embodiment of the present invention.
Referring to FIG. 7B, the mask 702, the device layer 704 and a portion of the substrate 706 are patterned with a multi-step laser scribing process 712 to form trenches 714 in the substrate 706. Referring to FIG. 7C, a through-silicon deep plasma etch process 716 is used to extend the trench 714 down to the die attach film 708, exposing the top portion of the die attach film 708 and singulating the silicon substrate 706. The device layer 704 is protected by the photo-resist layer 702 during the through-silicon deep plasma etch process 716.
A single process tool may be configured to perform many or all of the operations in a hybrid multi-step laser ablation and plasma etch singulation process. For example, FIG. 8 illustrates a block diagram of a tool layout for laser and plasma dicing of wafers or substrates, in accordance with an embodiment of the present invention.
In an embodiment, the laser scribe apparatus 810 houses a laser apparatus configured to perform a multi-step laser scribing process. The laser is suitable for performing a laser ablation portion of a hybrid laser and etch singulation process, such as the laser ablation processes described above. In one embodiment, a moveable stage is also included in laser scribe apparatus 810, the moveable stage configured for moving a wafer or substrate (or a carrier thereof) relative to the laser. In a specific embodiment, as described above the laser is also moveable. The overall footprint of the laser scribe apparatus 810 may be, in one embodiment, approximately 2240 millimeters by approximately 1270 millimeters, as depicted in FIG. 8.
In an embodiment, the laser scribe apparatus 810 includes a power-attenuation aperture placed along each beam path to finely adjust laser power and beam size. In an embodiment, an attenuating element is placed along each beam path to attenuate the beam portion, adjusting an intensity or strength of the pulses in that portion. In an embodiment, a shutter is placed along each beam path to control the shape of each pulse of the beam portion.
In accordance with an embodiment of the present invention, a machine-accessible storage medium has instructions stored thereon which cause a data processing system to perform a method of dicing a semiconductor wafer having a plurality of integrated circuits. The method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a multi-step laser scribing process to provide a patterned mask with gaps. Regions of the semiconductor wafer are exposed between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.
Thus, methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, have been disclosed. In accordance with an embodiment of the present invention, a method includes dicing a semiconductor wafer having a plurality of integrated circuits includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The method also includes patterning the mask with a multi-step laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also includes etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits. In one embodiment, the multi-step laser scribing process includes scribing with two or more offset but overlapping Gaussian beam passes and, subsequently, scribing with a top hat beam pass overlapping the Gaussian beam passes.
patterning the mask and a portion of the semiconductor wafer with a multi-step laser scribing process to provide a patterned mask and trenches in the semiconductor wafer between the integrated circuits, the multi-step laser scribing process comprising: scribing with two or more offset but overlapping Gaussian beam passes; and, subsequently, scribing with a top hat beam pass overlapping the Gaussian beam passes; and
plasma etching the semiconductor wafer to extend the trenches and to singulate the integrated circuits.
2. The method of claim 1, wherein the two or more offset but overlapping Gaussian beam passes are performed sequentially.
3. The method of claim 1, wherein the two or more offset but overlapping Gaussian beam passes are performed simultaneously.
4. The method of claim 1, wherein each of the two or more offset but overlapping Gaussian beam passes are performed using a UV laser having a wavelength approximately in the range of 300-380 nanometers.
5. The method of claim 1, wherein each of the two or more offset but overlapping Gaussian beam passes are performed using a UV laser having a pulse width approximately in the range of 5-50 picoseconds.
6. The method of claim 1, wherein each of the two or more offset but overlapping Gaussian beam passes are performed using a UV laser having a laser spot diameter approximately in the range of 25-50 microns.
7. The method of claim 1, wherein the top hat beam pass is performed at approximately 25%-50% of the average fluence of the Gaussian beam passes.
8. The method of claim 1, wherein forming the mask above the semiconductor wafer comprises forming a water soluble mask.
9. The method of claim 1, wherein the trenches in the semiconductor wafer each have a width, and wherein plasma etching the semiconductor wafer to extend the trenches comprises forming corresponding extended trenches each having the width.
10. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
patterning the mask and a portion of the semiconductor wafer with a multi-step laser scribing process to provide a patterned mask and trenches in the semiconductor wafer between the integrated circuits, the multi-step laser scribing process comprising: scribing with two or more offset but overlapping Gaussian beam passes; and, subsequently, scribing with a broad Gaussian beam pass overlapping the offset Gaussian beam passes; and
11. The method of claim 10, wherein the two or more offset but overlapping Gaussian beam passes are performed sequentially.
12. The method of claim 10, wherein the two or more offset but overlapping Gaussian beam passes are performed simultaneously.
13. The method of claim 10, wherein each of the two or more offset but overlapping Gaussian beam passes are performed using a UV laser having a wavelength approximately in the range of 300-380 nanometers.
14. The method of claim 10, wherein each of the two or more offset but overlapping Gaussian beam passes are performed using a UV laser having a pulse width approximately in the range of 5-50 picoseconds.
15. The method of claim 10, wherein each of the two or more offset but overlapping Gaussian beam passes are performed using a UV laser having a laser spot diameter approximately in the range of 25-50 microns.
16. The method of claim 10, wherein forming the mask above the semiconductor wafer comprises forming a water soluble mask.
17. The method of claim 10, wherein the trenches in the semiconductor wafer each have a width, and wherein plasma etching the semiconductor wafer to extend the trenches comprises forming corresponding extended trenches each having the width.
18. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask layer above a silicon substrate, the mask layer covering and protecting integrated circuits disposed on the silicon substrate, the integrated circuits comprising a layer of silicon dioxide disposed above a layer of low K material and a layer of copper;
patterning the mask layer, the layer of silicon dioxide, the layer of low K material, the layer of copper, and the silicon substrate with a multi-step laser scribing process to provide a patterned mask layer and trenches in the silicon substrate between the integrated circuits, the multi-step laser scribing process comprising: scribing with two or more offset but overlapping Gaussian beam passes; and, subsequently, scribing with a top hat beam pass or with a broad Gaussian beam pass overlapping the Gaussian beam passes; and
plasma etching the silicon substrate to extend the trenches and to singulate the integrated circuits.
19. The method of claim 18, wherein patterning the layer of silicon dioxide, the layer of low K material, the layer of copper, and the silicon substrate with the multi-step laser scribing process comprises ablating the layer of silicon dioxide prior to ablating the layer of low K material and the layer of copper.
20. The method of claim 18, wherein the two or more offset but overlapping Gaussian beam passes are performed sequentially.
21. The method of claim 18, wherein the two or more offset but overlapping Gaussian beam passes are performed simultaneously.
22. The method of claim 18, wherein forming the mask layer above the silicon substrate comprises forming a water soluble mask layer.
23. The method of claim 18, wherein the trenches in the silicon substrate each have a width, and wherein plasma etching the silicon substrate to extend the trenches comprises forming corresponding extended trenches each having the width.
1649965 April 2006 EP
International Search Report and Written Opinion for PCT Patent Application No. PCT/US2013/034841 mailed Jul. 1, 2013, 10 pgs.
Patent number: 8846498
Patent Publication Number: 20140120698
Application Number: 14/148,499
International Classification: H01L 21/00 (20060101); H01L 21/78 (20060101);