Source: https://patents.justia.com/patent/8871627
Timestamp: 2019-08-20 13:47:56
Document Index: 647408336

Matched Legal Cases: ['Application No. 2008', 'Application No. 2008', 'Application No. 200910132909', 'Application No. 10', 'Application No. 2006', 'Application No. 2006', 'Application No. 095146789']

US Patent for Semiconductor device having low dielectric insulating film and manufacturing method of the same Patent (Patent # 8,871,627 issued October 28, 2014) - Justia Patents Search
Justia Patents Selectively Interconnecting (e.g., Customization, Wafer Scale Integration, Etc.)US Patent for Semiconductor device having low dielectric insulating film and manufacturing method of the same Patent (Patent # 8,871,627)
Nov 15, 2013 - Tera Probe, Inc.
A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
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This is a Continuation of U.S. application Ser. No. 12/156,822, filed Jun. 4, 2008, which is a Continuation-in-part of U.S. application Ser. No. 12/001,878, filed Dec. 13, 2007. The present application is based upon and claims the benefit of priority from prior Japanese Patent Applications No. 2007-244977, filed Sep. 21, 2007, and No. 2008-047090, filed Feb. 28, 2008, the entire contents of both of which are incorporated herein by reference.
The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly a semiconductor device having wiring lines on a low dielectric film.
As semiconductor devices to be mounted on small-sized electronic devices represented by portable electronic devices and the like, there are known chip size packages (CSPs) each having dimensions substantially equal to that of a semiconductor substrate. Among the CSPs, a CSP in which packaging is completed in a wafer state and which is separated into individual semiconductor devices by dicing is also referred to as a wafer level package (WLP).
In the conventional semiconductor device as described above (refer to, for example, Jpn. Pat. Appln. KOKAI Publication No. 2004-349461), wiring lines are extended from connection pads on the upper surface of an insulating film which covers the connection pads formed on the semiconductor substrate, a number of columnar electrodes are respectively arranged on the upper surfaces of connection pad portions formed on ends of the extended wiring lines, and a sealing film is formed so as to cover the wiring lines between the columnar electrodes on the upper surface of the insulating film. The sealing film is formed so that the upper surface of the sealing film and the upper surfaces of the columnar electrodes are on one plane. Solder balls are respectively provided on the upper surfaces of the columnar electrodes.
Among such semiconductor devices as described above, there is a device in which an interlayer insulating film wiring line laminated structure portions each including a laminated structure of interlayer insulating films and the wiring lines is provided between the semiconductor substrate and the insulating film. In this device, when an interval between the wiring lines of the interlayer insulating film wiring line laminated structure portion decreases with miniaturization of the semiconductor devices, a capacity between the wiring lines increases, with the result that a delay of a signal which transmits through the wiring lines increases.
To improve this point, as a material of the interlayer insulating film, much attention is paid to a low dielectric material such as a low-k material having a dielectric constant lower than a dielectric constant of 4.2 to 4.0 of silicon oxide which is generally used as the material of the interlayer insulating film. Examples of the low-k material include SiOC obtained by doping silicon oxide (SiO2) with carbon (C), and SiOCH further containing H. To further lower the dielectric constant, air-containing porous type low dielectric films are also being investigated.
In the above semiconductor device including the low dielectric film, especially the low dielectric film represented by the porous type low dielectric film having a hollow structure has a small mechanical strength and is easily influenced by moisture. As a result, there is a problem that the low dielectric film easily peels from an underlayer.
An object of the present invention is to provide a semiconductor device capable of significantly avoiding a problem of peeling of a low dielectric film, and a method for manufacturing the same.
A semiconductor device according to one aspect of the present invention comprises a semiconductor substrate and a low dielectric film wiring line laminated structure portion which is provided on one surface of the semiconductor substrate. The low dielectric film wiring line laminated structure portion has a laminated structure including a plurality of low dielectric films and a plurality of wiring lines, each of the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed at least on the low dielectric film wiring line laminated structure portion. On the insulating film, there are provided a connection pad portion for an electrode so as to be connected to a connection pad portion of an uppermost wiring line of the low dielectric film wiring line laminated structure portion, a bump electrode for external connection, provided on the connection pad portion for the electrode, and a sealing film made of an organic resin and provided at least on a part of the insulating film which surrounds the pump electrode for the external connection. Side surfaces of the low dielectric film wiring line laminated structure portion are covered with one of the insulating film and the sealing film.
A method for manufacturing a semiconductor device according to another aspect of the present invention comprises preparing a semiconductor wafer, on one surface of which a low dielectric film wiring line laminated structure portion is formed, the low dielectric film wiring line laminated structure portion including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. In the next, parts of the low dielectric film wiring line laminated structure portion in regions above dicing streets and regions on opposite sides of the dicing streets are removed by applying laser beams, thereby forming a groove exposing side surfaces of the low dielectric film wiring line laminated structure portion. Thereafter, an organic resin film covering the side surfaces of the low dielectric film wiring line laminated structure portion is formed. Then, the organic resin film and the semiconductor wafer are cut along the dicing streets, thereby obtaining a plurality of, semiconductor devices.
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention;
FIG. 2 is a sectional view of an assembly first prepared during manufacturing of the semiconductor device shown in FIG. 1;
FIG. 3 is a sectional view of an assembly in a step subsequent to FIG. 2;
FIG. 4 is a sectional view of an assembly in a step subsequent to FIG. 3;
FIG. 5 is a sectional view of an assembly in a step subsequent to FIG. 4;
FIG. 6 is a sectional view of an assembly in a step subsequent to FIG. 5;
FIG. 7 is a sectional view of an assembly in a step subsequent to FIG. 6;
FIG. 8 is a sectional view of an assembly in a step subsequent to FIG. 7;
FIG. 9 is a sectional view of an assembly in a step subsequent to FIG. 8;
FIG. 10 is a sectional view of an assembly in a step subsequent to FIG. 9;
FIG. 11 is a sectional view of an assembly in a step subsequent to FIG. 10;
FIG. 12 is a sectional view of an assembly in a step subsequent to FIG. 11;
FIG. 13 is a sectional view of an assembly in a step subsequent to FIG. 12;
FIG. 14 is a sectional view of a semiconductor device as a second embodiment of the present invention;
FIG. 15 is a sectional view of an assembly in a predetermined step during manufacturing of the semiconductor device shown in FIG. 14;
FIG. 16 is a sectional view of an assembly in a step subsequent to FIG. 15;
FIG. 17 is a sectional view of an assembly in a step subsequent to FIG. 16;
FIG. 18 is a sectional view of an assembly in a step subsequent to FIG. 17;
FIG. 19 is a sectional view of an assembly in a step subsequent to FIG. 18;
FIG. 20 is a sectional view of a semiconductor device as a third embodiment of the present invention;
FIG. 21 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention;
FIG. 22 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention; and
FIG. 23 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.
FIG. 1 shows a sectional view of a semiconductor device as a first embodiment of the present invention. This semiconductor device includes a silicon substrate (a semiconductor substrate) 1. On the upper surface of the silicon substrate 1, a number of active semiconductor elements, such as transistors, are provided (not shown). In a peripheral portion of the upper surface of the substrate 1, a number of connection pads 2 made of an aluminum-based metal or the like are electrically connected to the respective semiconductor elements, although the figure shows only two pads. The connection pads 2 are input and/or output terminals of each semiconductor element, and/or a power supply terminal.
On the upper surface of the silicon substrate 1, excluding peripheral portions outside the connection pads 2, a low dielectric film/wiring line/laminated structure portion 3 is provided. The laminated structure portion 3 has a structure in which there are alternately laminated a plurality of layers, for example, four layers of low dielectric films 4 and the same number of layers of wiring lines 5 made of copper or an aluminum-based metal or the like.
Examples of a material of the low dielectric films 4 include a polysiloxane-based material having an Si—O bond and an Si—H bond (HSQ: Hydrogen silsesquioxane having a relative dielectric constant of 3.0), a polysiloxane-based material having an Si—O bond and an Si—CH3 bond (MSQ: Methyl silsesquioxane having a relative dielectric constant of 2.7-2.9), carbon-doped silicon oxide (SiOC having a relative dielectric constant of 2.7-2.9) and an organic polymer-based low-k material. The materials having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher can be used.
Examples of the organic polymer-based low-k material include “SILK (having a relative dielectric constant of 2.6)” produced by Dow Chemical Company and “FLARE (having a relative dielectric constant of 2.8)” produced by Honeywell Electronic Materials Company. The glass transition temperature of 400° C. or higher is a condition for tolerance to a temperature in a manufacturing step or steps to be described later. A porous type of each of the above materials may also be used.
Besides the above, the material of the low dielectric films 4 may also be a material which has a relative dielectric constant higher than 3.0 in a normal condition, but can have a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher when it becomes porous. For example, fluorinated silicate glass (FSG having a relative dielectric constant of 3.5-3.7), boron-doped silicate glass (BSG having a relative dielectric constant of 3.5) or silicon oxide (having a relative dielectric constant of 4.0-4.2) may be used.
In the low dielectric film wiring line laminated structure portion 3, the wiring lines 5 between the low dielectric films 4 are electrically connected to each other through holes formed in the films 4. One end portion of the wiring line 5 of the lowermost layer is electrically connected to the connection pad 2 via an opening 6 formed in the low dielectric film 4 of the lowermost layer. Connection pad portions 5a of the wiring lines 5 of an uppermost layer are arranged on an upper surface peripheral portion of the low dielectric film 4 of the uppermost layer.
A passivation film 7 made of an inorganic material such as silicon oxide is provided on the upper surfaces of the uppermost wiring lines 5 and the low dielectric films 4 of the uppermost layer. Openings 8 are formed through the passivation film 7 in portions corresponding to the connection pad portions 5a of the wiring lines 5 of the uppermost layer. On the upper surface of the passivation film 7, there is provided a protective film (insulating film) 9 made of an organic material containing polyimide, epoxy, phenol, bismaleimide, acryl, synthetic rubber, polybenzoxide or the like as a main component. Openings 10 are formed through the protective film 9 in portions corresponding to the openings 8 of the passivation film 7.
On the upper surface of the protective film 9, metallic underlayers 11 made of copper or the like are provided. On the whole upper surface of each of the metallic underlayers 11, an upper layer wiring line 12 made of copper is provided. End portions of the upper layer wiring line 12 and the metallic underlayers 11, are connected to the connection pad portions 5a of the wiring lines 5 of the uppermost layer via the openings 8, 10 of the passivation film 7 and the protective film 9. On the upper surfaces of connection pad portions (connecting pad portions for electrodes) of the upper layer wiring lines 12, there are provided columnar electrodes (bump electrodes for external connection) 13 made of copper.
On the upper surfaces of the upper layer wiring lines 12 and the protective film 9, and the upper surface of the peripheral portion of the silicon substrate 1, there is provided a sealing film 14 made of an organic material such as an epoxy-based resin so that the upper surface of the sealing film and the upper surfaces of the columnar electrodes 13 are on one plane. In this state, the side surfaces of the low dielectric film wiring line laminated structure portion 3, the passivation film 7 and the protective film 9 form substantially one plane and are entirely covered with the sealing film 14. Solder balls 15 are provided on the upper surfaces of the columnar electrodes 13.
As described above, in this semiconductor device, a region on the silicon substrate 1 except the peripheral portion is provided with the low dielectric film wiring line laminated structure portion or structure portions 3 each including the laminated structure of the low dielectric films 4 and the wiring lines 5, and the side surfaces of the low dielectric film wiring line laminated structure portion 3, the passivation film 7 and the protective film 9 are covered with the sealing film 14. Therefore, the low dielectric film wiring line laminated structure portion 3 does not easily peel from the silicon substrate 1.
Next, one example of a method for manufacturing the semiconductor device mentioned above will be described. First, as shown in FIG. 2, an assembly is prepared, in which on a silicon substrate (hereinafter referred to as a semiconductor wafer 21) of a wafer state, there are arranged the connection pads 2 and the low dielectric film wiring line laminated structure portions 3 each including four layers of low dielectric films 4 and wiring lines 5. In the assembly, the passivation film 7 is provided on the laminated structure portions 3, and the centers of the connection pad portions 5a of the wiring lines 5 of the uppermost layer are exposed via the openings 8 provided in the passivation film 7.
Examples of a low dielectric film material 4 may be those, including a porous type, as described above, which have a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. It is to be noted that regions denoted with reference numeral 22 in FIG. 2 are regions corresponding to dicing streets.
Next, as shown in FIG. 3, by a screen printing process, a spin coating process or the like, the protective film 9 made of an organic material such as a polyimide-based resin is formed on the upper surface of the passivation film 7 and the upper surfaces of the connection pad portions 5a of the wiring lines 5 of the uppermost layer exposed via the openings 8 of the passivation film 7. Then, as shown in FIG. 4, a water-soluble protective film 17, made of water-soluble polymers such as polyvinyl alcohol (PVA) or polyacrylamide (PAM), is formed on the upper surface of the protective film 9 by a screen printing process, a spin coating process or the like.
Next, as shown in FIG. 5, by laser processing which emits a laser beam, there are removed portions of the water soluble protective film 17, the protective film 9, the passivation film 7 and four layers of the low dielectric films 4 positioned in regions of the dicing streets 22 and regions on opposite sides of the streets to form latticed grooves 23. Further, the openings 8 and 10 are formed through the passivation film 7 and the water soluble protective film 17 in portions corresponding to the connection pad portions 5a of the wiring lines 5 of the uppermost layer.
In this process, when the laser beam is radiated on the low dielectric films 4, the low dielectric films 4 melt and scatter as low dielectric film pieces. The scattered low dielectric film pieces drop on and stick into the upper surface of the water soluble protective film 17, not the upper surface of the protective film 9. Then, when the water soluble protective film 17 is washed with water and removed, the low dielectric film pieces stuck into the upper surface of the water soluble protective film 17 are also removed simultaneously. If the scattered low dielectric film pieces are sucked by evacuation, the water soluble protective film 17 may be unnecessary.
The low dielectric films 4 are brittle. Therefore, if the grooves 23 are cut in the films 4 by using a blade, the cut surface of the low dielectric films 4 will have many notches and cracks. In view of this, it is recommended that the low dielectric films 4 be cut by the laser beam to make grooves 23. If the grooves 23 are worked by the laser beam, the upper surface of the silicon substrate 1 melts, when irradiated with the laser beam, and molten silicon particles jump and then fall onto the silicon substrate 1. Inevitably, each groove 23 will have an uneven bottom surface as shown in FIG. 5.
In this state, that is, in the state where the water soluble protective film 17 has been removed, as shown in FIG. 6, the upper surface of the semiconductor wafer 21 in the regions of the dicing streets 22 and the regions on opposite sides of the streets is exposed via the grooves 23. Moreover, portions of the four layers of the low dielectric films 4, the passivation film 7 and the protective film 9 laminated on the semiconductor wafer 21 are separated from one another by the grooves 23. In consequence, a plurality of low dielectric film wiring line laminated structure portions 3 independent of one another are formed on the wafer 21, as shown in FIG. 1.
As one example, a width of the groove 23 is 10 to 1000 μm×2 plus a width of the dicing street (a dicing cutter) 22. As a result, in the completed device shown in FIG. 1, a width of the portion of the sealing film 14 which covers the side surfaces of the low dielectric film wiring line laminated structure portion 3, the passivation film 7 and the protective film 9 is 10 to 1000 μm.
Next, as shown in FIG. 7, the metallic underlayers 11 are formed on the upper surfaces of the connection pad portions 5a of the wiring lines 5 of the uppermost layer exposed via the openings 8, 10 of the passivation film 7 and the protective film 9, on the portions of the upper surface of the semiconductor wafer 21 exposed via the grooves 23, and on the whole upper surface of the protective film 9. In this case, the metallic underlayers 11 may be formed by an only copper layer formed by electroless plating, an only copper layer formed by sputtering, or a copper layer formed by the sputtering on a thin film layer of titanium or the like formed by the sputtering.
Next, plating resist films 24 are formed on the upper surfaces of the metallic underlayers 11, and followed by patterning. As a result, openings 25 are formed in portions of the plating resist films 24 corresponding to regions in which the upper layer wiring lines 12 are formed. Next, electrolytic plating of copper is performed by use of the metallic underlayers 11 as plating current paths to thereby form the upper layer wiring lines 12 on the upper surfaces of the metallic underlayers 11 in the openings 25 of the plating resist films 24. Next, the plating resist films 24 are peeled.
Next, as shown in FIG. 8, on the upper surfaces of the metallic underlayers 11 and the upper layer wiring lines 12, a plating resist film 26 is formed by depositing and then patterning. Thus, in this case, openings 27 are formed in the plating resist film 26 in portions corresponding to the connection pad portions (regions where the columnar electrodes 13 are formed) of the upper layer wiring lines 12. Next, the electrolytic plating of copper is performed by use of the metallic underlayers 11 as the plating current paths, whereby the columnar electrodes 13 each having a height of 50 to 150 μm are formed on the upper surfaces of the connection pad portions of the upper layer wiring lines 12 in the openings 27 of the plating resist film 26. Next, the plating resist film 26 is entirely peeled or removed. Then, unnecessary portions of the metallic underlayers 11 are etched and removed by use of the upper layer wiring lines 12 as masks. Consequently, as shown in FIG. 9, the metallic underlayers 11 only under the upper layer wiring lines 12 are left.
Next, as shown in FIG. 10, by a screen printing process, a spin coating process or the like, the sealing film (organic resin film) 14 made of an organic material such as an epoxy-based resin is entirely formed on the upper surfaces of the upper layer wiring lines 12, the columnar electrodes 13 and the protective film 9, as well as on the upper surface of the semiconductor wafer 21 exposed via the grooves 23 so that a thickness of the sealing film 14 is larger than a height of the columnar electrodes 13. Therefore, in this state, the upper surfaces of the columnar electrodes 13 are covered with the sealing film 14. The side surfaces of the protective film 9, the passivation film 7 and four layers of the low dielectric films 4 are also entirely covered with the sealing film 14.
Next, a portion of the upper surface of the sealing film 14 is appropriately ground to expose the upper surfaces of the columnar electrodes 13 as shown in FIG. 11. Moreover, the exposed upper surfaces of the columnar electrodes 13 and the upper surface of the sealing film 14 are flattened so that these upper surfaces are on one plane. In flattening this upper surface of the sealing film 14, upper surface portions of the columnar electrodes 13 may be ground together with the upper portion of the sealing film 14 as much as several to ten or more micrometers.
Next, as shown in FIG. 12, the solder balls 15 are formed on the upper surfaces of the columnar electrodes 13. Next, as shown in FIG. 13, the sealing film 14 and the semiconductor wafer 21 are cut along the dicing streets 22 in the centers of the grooves 23. As described above, since the grooves 23 have been formed to be wider than the dicing streets 22, there are obtained a plurality of semiconductor devices each having a structure in which, as shown in FIG. 1, the side surfaces of the low dielectric film wiring line laminated structure portion 3 are covered with the sealing film 14, and further the side surfaces of the passivation film 7 and the upper surface and the side surfaces of the protective film 9 are also covered with the sealing film 14.
In the above embodiment, the exposed part of the upper surface of the semiconductor wafer 21 is shown like a bottom portion of the groove 23, but the upper surface of the semiconductor wafer 21 may be partially removed by a laser beam to form the groove 23, so that the bottom portion of the groove 23 may be below the upper surface of the semiconductor wafer 21. If an insulating film such as a field oxide film is formed on the upper surface of the semiconductor wafer 21, the upper surface of this field oxide film or an intermediate portion of a film thickness thereof may be the bottom portion of the groove 23, and the bottom portion of the groove 23 may be positioned above the upper surface of the semiconductor wafer 21.
FIG. 14 shows a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the upper surface and the side surfaces of the passivation film 7 and the side surfaces of the low dielectric film wiring line laminated structure portion 3 are covered with the protective film 9, and the side surfaces of the protective film 9 is covered with the sealing film 14.
As one example of manufacturing this semiconductor device, an assembly shown in FIG. 2 is prepared. Then, as shown in FIG. 15, the water-soluble protective film 17, made of water-soluble polymers such as polyvinyl alcohol (PVA) or polyacrylamide (PAM), is formed on the upper surface of the passivation film 7 and the connecting pad portions 5a of the wiring lines 5 of the uppermost layer, which are exposed via the opening 8 of the passivation film 7, by a screen printing process, a spin coating process or the like.
Thereafter, as shown in FIG. 16, by laser processing which emits a laser beam, the grooves 23 are formed in the water soluble protective film 17, the passivation film 7 and four layers of the low dielectric films 4 in regions of the dicing streets 22 and regions on opposite sides of the streets. In this process also, when the laser beam is radiated on the low dielectric films 4, the low dielectric films 4 melt and scatter as low dielectric film pieces. The scattered low dielectric film pieces drop on and stick into the upper surface of the water soluble protective film 17, not the upper surface of the passivation film 7. Then, when the water soluble protective film 17 is washed with water and removed, the low dielectric film pieces stuck into the upper surface of the water soluble protective film 17 are also removed simultaneously. In this case also, if the scattered low dielectric film pieces are sucked by evacuation, the water soluble protective film 17 may be unnecessary.
In this state, that is, in the state where the water soluble protective film is removed as shown in FIG. 17, the upper surfaces of the semiconductor wafer 21 in the dicing streets 22 and the regions on opposite sides of the streets are exposed via the grooves 23. Moreover, units which are laminated on the semiconductor wafer 21 and which are each constituted of four layers of the low dielectric films 4 and the passivation film 7 are separated from one another along the grooves 23. In consequence, a plurality of low dielectric film wiring line laminated structure portions 3 shown in FIG. 14 are formed on the semiconductor wafer 21.
Next, as shown in FIG. 18, by a screen printing process, a spin coating process or the like, the protective film (organic resin film) 9 made of an organic material such as a polyimide-based resin is formed on the upper surfaces of the connection pad portions 5a of the wiring lines 5 of the uppermost layer exposed via the openings 8 of the passivation film 7, on the upper surface of the passivation film 7, and on the upper surfaces of portions of the semiconductor wafer 21 exposed via the grooves 23. It is preferable that the upper surface of the passivation film 7 and the protective film 9 formed in the grooves 23 have substantially flat surfaces.
Next, as shown in FIG. 19, by laser processing which emits a laser beam or photolithography, grooves 23a slightly narrower than the aforementioned grooves 23 are formed in the protective film 9 in the regions of the dicing streets 22 and the regions on opposite sides of the streets, and openings 8 and 10 are formed in portions of the passivation film 7 and the protective film 9 corresponding to the connecting pad portions 5a of the wiring lines 5 in the uppermost layer. Since the subsequent steps are similar to the steps of FIG. 7 et seq. of the first embodiment, description thereof is omitted.
FIG. 20 shows a sectional view of a semiconductor device as a third embodiment of the present invention. The third embodiment is different from the semiconductor device shown in FIG. 14 in that the protective film (organic resin film) 9 which covers the upper surface and the side surfaces of the passivation film 7 and the side surfaces of the low dielectric film wiring line laminated structure portions 3 is extended to the same plane as that of the side surface of the silicon substrate 1.
To produce the above semiconductor device, the groove 23 is completely filled with a part of the protective film 9, as shown in FIG. 18, so that the groove 23a as shown in FIG. 19 may not be formed. In this case, therefore, the sealing film 14, the protective film 9 and the semiconductor wafer 21 are cut along the dicing streets 22 in the last step.
FIG. 21 is a sectional view of a semiconductor device according to a fourth embodiment of this invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the outer side surfaces 9a of the protective film 9 are located inward from the outer side surfaces of the low dielectric film wiring line laminated structure portion 3 and the passivation film 7. In other words, the protective film 9 is formed on the passivation film 7 to be smaller than the passivation film 7 in a plane size. In this case, each of the outer side surfaces of the passivation film 7 and each of the low dielectric film wiring line laminated structure portion 3 substantially form one plane (vertical plane in FIG. 21).
An example of the method for manufacturing the semiconductor device will be described. For example, as shown in FIG. 3, the protective film (organic resin film) 9 is formed on the entire surface of the passivation film 7. Then, the protective film 9 is patterned by means of photolithography, thereby forming the protective film as shown in FIG. 21. The patterning of the protective film 9 is carried out such that a side surface 9a may not reach the dicing line 22. The side surface 9a of the protective film 9 is deviated from the side surfaces of the passivation film 7 and the low dielectric film wiring line limited structure portion 3 by a distance greater than a positioning deviation that may occur in the next step of laser radiation. Thereafter, the water soluble protective film may be formed on the entire surface, if necessary, and laser beams are applied to the passivation film 7 and the low dielectric film wiring line laminated structure portion 3, making grooves 23.
Another example of the method for manufacturing the semiconductor device will be described. In this example, as shown in FIG. 17, before the protective film 9 is formed, the laser beams are applied to the passivation film 7 and the low dielectric film 4, thereby forming the grooves 23. Then, as shown in FIG. 18, after the laser beams are applied to form the grooves 23, the protective film 9 is patterned. Next, the protective film 9 is formed on the entire surface of the passivation film 7 including the insides of the grooves 23 by spin coating or the like. Then, the protective film 9 is patterned by means of photolithography so as to remove those parts of the protective film 9 in the grooves 23 and peripheries of the passivation film 23, thereby forming the protective film as shown in FIG. 21.
In both the above examples of the method for manufacturing the semiconductor device, the passivation film 7 and the low dielectric film 4 are processed with the laser beams, and the protective film 9 is not. Therefore, this method is particularly effective in the case where the protective film 9 is made of a material, such as a polyimide-based resin, which easily absorbs laser energy and cannot be easily cut by radiation of laser beams.
FIG. 22 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 21 in that the outer side surfaces of the passivation film 7 are located inward from those of the protective film 9. In other words, the passivation film 7 is formed on the low dielectric film wiring line laminated structure portion 3 to be smaller than the protective film 9 in a plane size, and the protective film 9 has side portions downwardly extending to cover the side surfaces of the passivation film 7.
To manufacture this semiconductor device, the passivation film 7 is formed on the overall surface of the low dielectric film 4 of the uppermost layer, as shown in FIG. 2. Then, the passivation film 7 is patterned by means of photolithography. Thereafter, the protective film 9 is formed on the passivation film 7 and parts of the low dielectric film 4 of the uppermost layer which are not covered by the passivation film 7. Thereafter, the protective film 9 is patterned by means of photolithography. Then, if necessary, the water soluble protective film may be formed on the entire surface, and the low dielectric film 4 is processed by radiation of laser beams, thereby forming grooves 23.
In the above method for manufacturing the semiconductor device, only the low dielectric film 4 is processed with laser beams, and the passivation film 7 and the protective film 9 are not. Optimal laser-beam process conditions can therefore be set for the processing of the low dielectric film 4. Hence, the low dielectric film 4 can be processed efficiently with high precision. It is to be noted that the passivation film 7 may be of the same size as the protective film 9, so that the side surfaces of the passivation film 7 and the side surfaces of the protective film 9 form substantially the same plane.
FIG. 23 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 21 in that the low dielectric film wiring line laminated structure portion 3 has a lower passivation film 16 between the uppermost wiring line 5 and the uppermost low dielectric film 4.
In this case, the upper passivation film 7 and the lower passivation film 16 may be formed of the same inorganic material, such as silicon oxide. Alternatively, the passivation film 7 may be formed of silicon nitride, while the lower passivation film 16 may be formed of silicon oxide.
For example, in the first embodiment, after the process shown in FIG. 3, the metallic underlayers 11 may be formed on the entire upper surface of the protective film 9. Then, the upper wiring lines 12 and the columnar electrodes 13 may be formed by electrolytic plating. Then, unnecessary portions of the metallic underlayers 11 may be etched and removed by use of the upper layer wiring lines 12 as masks. Thereafter, the water soluble protective film may be formed on the entire surface, if necessary, and laser beams are applied, to the protective film 9, the passivation film 7 and the low dielectric film 4, making grooves 23. In this case, if the water soluble protective film is removed after forming the grooves 23, the structure as shown in FIG. 9 can be obtained.
Referring to FIG. 21, for example, the uppermost low dielectric film 4 of the low dielectric film wiring line limited structure portion 3 may be a lower passivation film. In other words, the low dielectric film wiring line limited structure portion 3 may have a lower passivation film formed between the uppermost wiring line 5 and the second uppermost wiring line 5.
In this case, the passivation film 7 and the lower passivation film may be formed of the same inorganic material, such as silicon oxide. Alternatively, the passivation film 7 may be formed of silicon nitride, while the lower passivation film may be formed of silicon oxide.
In the above embodiments, the upper wiring lines 12 are formed on the protective film 9 and the columnar electrodes 13 are formed on the connection pad portion on the upper wiring lines 12. However, this invention is applicable to a structure in which only the connection pad portion is formed on the protective film 9 and bump electrodes for external connection, such as solder balls 15, are formed on the connection pad portion.
As described above, according to the present invention, the low dielectric film wiring line laminated structure portion having a laminated structure of the low dielectric films, which has a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher, and the wiring lines are provided in regions excluding the peripheral portions of the semiconductor substrate. The side surfaces of the low dielectric film wiring line laminated structure portion are covered by one of the insulating film formed of organic resin or the sealing film. Therefore, the problem of peeling of the low dielectric films can be significantly avoided.
preparing a semiconductor wafer on an upper surface of which a low dielectric film wiring line laminated structure portion is formed, the low dielectric film wiring line laminated structure portion including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower, and a passivation film made of an inorganic material being formed on the low dielectric film wiring line laminated structure portion;
removing parts of the low dielectric film wiring line laminated structure portion in regions of dicing streets and regions on opposite sides of each of the dicing streets by applying laser beams, thereby forming grooves which expose side surfaces of the low dielectric film wiring line laminated structure portion;
forming a first organic resin film covering the side surfaces of the low dielectric film wiring line laminated structure portion; and
cutting the semiconductor wafer along the dicing streets, thereby obtaining a plurality of semiconductor devices.
2. The method according to claim 1, wherein forming the grooves includes forming a water soluble protective film entirely covering the upper surface of the semiconductor wafer before forming the grooves, and removing the water soluble protective film after forming the grooves.
3. The method according to claim 2, further comprising forming an electrode for external connection over the low dielectric film wiring line laminated structure portion.
4. The method according to claim 2, wherein forming the first organic resin film includes forming an insulating film made of an organic resin covering at least a part of an upper side and exposed side surfaces of the passivation film and the exposed side surfaces of the low dielectric film wiring line laminated structure portion.
5. The method for manufacturing a semiconductor device according to claim 2, further comprising:
forming a second organic resin film on an upper side of the passivation film;
wherein forming the first organic resin film includes forming an insulating film made of an organic resin covering at least a part of an upper side and exposed side surfaces of the second organic resin film, and the exposed side surfaces of the low dielectric film wiring line laminated structure portion.
6. The method according to claim 1, further comprising forming a bump electrode for external connection over the low dielectric film wiring line laminated structure portion.
7. The method according to claim 6, wherein forming the first organic resin film includes forming an insulating film made of an organic resin covering at least a part of an upper side and exposed side surfaces of the passivation film and the exposed side surfaces of the low dielectric film wiring line laminated structure portion.
forming a second organic resin film on the passivation film;
9. The method according to claim 6, wherein preparing the semiconductor wafer includes patterning the passivation film.
10. The method according to claim 8, wherein forming the second organic resin film includes patterning the second organic resin film to prevent the second organic resin film from extending in the dicing streets.
11. The method according to claim 8, wherein forming the grooves includes removing parts of the second organic resin film and the low dielectric film wiring line laminated structure portion in the regions of the dicing streets and the regions on the opposite sides of each of the dicing streets by applying the laser beams, such that the grooves expose side surfaces of the second organic resin film and the side surfaces of the low dielectric film wiring line laminated structure portion.
preparing the semiconductor wafer includes preparing the low dielectric film wiring line laminated structure portion on which the passivation film and a lower passivation film made of an inorganic material are formed, the lower passivation film being formed under the passivation film; and
forming the first organic resin film includes forming the insulating film made of the organic resin covering the exposed side surfaces of the passivation film, exposed side surfaces of the lower passivation film, and the side surfaces of the low dielectric film wiring line laminated structure portion.
13. The method according to claim 10, wherein forming the second organic resin film includes forming the second organic resin film on the passivation film and patterning the second organic resin film such that side surfaces of the second organic resin film are located inward from the side surfaces of the low dielectric film wiring line laminated structure portion.
14. The method according to claim 6, further comprising forming a third organic resin film covering an upper surface of the first organic resin film at least around the bump electrode for external connection.
15. The method according to claim 1, wherein forming the first organic resin film includes forming an insulating film made of an organic resin which is filled in the grooves and from which a part corresponding to a central portion of each of the grooves is removed by one of (i) patterning the first organic resin film to prevent the first organic resin film from extending above the dicing street and (ii) cutting the first organic resin film along the dicing streets.
forming the first organic resin film includes: forming an insulating film made of an organic resin which is filled in the grooves and from which a part corresponding to a central portion of each of the grooves is removed; and
forming the third organic resin film includes: filling the removed part of the first organic resin film with the organic resin; and covering the side surfaces of the first organic resin film with the third organic resin film.
forming a connecting pad portion for an electrode on the second organic resin film so as to be connected to a connection pad portion of an uppermost wiring line of the low dielectric film wiring line laminated structure portion; and
forming a bump electrode for external connection on the connecting pad portion for the electrode;
wherein forming the first organic resin film includes forming an insulating film made of an organic resin covering an upper surface of the second organic resin film at least around the bump electrode for external connection, side surfaces of the second organic resin film, and the side surfaces of the low dielectric film wiring line laminated structure portion.
forming a connecting pad portion for an electrode on the first organic resin film so as to be connected to a connection pad portion of an uppermost wiring line of the low dielectric film wiring line laminated structure portion;
forming a bump electrode for external connection on the connecting pad portion for the electrode; and
forming a third organic resin film covering an upper surface of the first organic resin film at least around the bump electrode for external connection.
19. The method according to claim 1, wherein the low dielectric film includes one of a polysiloxane-based material having an Si—O bond and an S—H bond, a polysiloxane-based material having an Si—O bond and an Si—CH3 bond, a carbon-doped silicon oxide and an organic polymer-based low-k material, or a porous type of one of a fluorine-doped silicon oxide, boron-doped silicon oxide and silicon oxide.
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Patent number: 8871627
Patent Publication Number: 20140073090
Assignee: Tera Probe, Inc. (Kanagawa)
Inventors: Aiko Mizusawa (Kunitachi), Osamu Okada (Hamura), Takeshi Wakabayashi (Sayama), Ichiro Mihara (Tachikawa)
Assistant Examiner: Krista Soderholm
Application Number: 14/081,303
Current U.S. Class: Selectively Interconnecting (e.g., Customization, Wafer Scale Integration, Etc.) (438/598); Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device (438/107); Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization) (438/622); Including Organic Insulating Material Between Metal Levels (438/623); Separating Insulating Layer Is Laminate Or Composite Of Plural Insulating Materials (438/624); Multiple Layers (438/761); Insulative Material Deposited Upon Semiconductive Substrate (438/778); Depositing Organic Material (e.g., Polymer, Etc.) (438/780); Bump Leads (257/737); Of Specified Configuration (257/773); Leads, I.e., Metallizations Or Lead Frames On Insulating Substrates, E.g., Chip Carriers (epo) (257/E23.06); Partial Encapsulation Or Coating (epo) (257/E23.129); Chip Mounted On Chip (257/777); Via (interconnection Hole) Shape (257/774)
International Classification: H01L 23/488 (20060101); H01L 23/00 (20060101); H01L 21/78 (20060101); H01L 23/31 (20060101); H01L 23/525 (20060101);