Source: http://www.google.com/patents/US5862316?dq=7,117,286
Timestamp: 2015-04-01 14:05:57
Document Index: 346650457

Matched Legal Cases: ['art 140', 'art 140', 'art 160', 'art 160', 'art 180', 'art 300', 'art 300', 'art 140', 'art 300', 'art 300', 'art 310', 'art 310', 'art 160', 'art 310', 'art 310']

Patent US5862316 - Multiprocessing system having coherency-related error logging capabilities - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsProtocol agents involved in the performance of global coherency activity detect errors with respect to the activity being performed. The errors are logged by a computer system such that diagnostic software may be executed to determine the error detected and to trace the error to the erring software or...http://www.google.com/patents/US5862316?utm_source=gb-gplus-sharePatent US5862316 - Multiprocessing system having coherency-related error logging capabilitiesAdvanced Patent SearchPublication numberUS5862316 APublication typeGrantApplication numberUS 08/674,276Publication dateJan 19, 1999Filing dateJul 1, 1996Priority dateJul 1, 1996Fee statusPaidAlso published asDE69727856D1, DE69727856T2, EP0817051A2, EP0817051A3, EP0817051B1Publication number08674276, 674276, US 5862316 A, US 5862316A, US-A-5862316, US5862316 A, US5862316AInventorsErik E. Hagersten, John R. Catenzaro, William A. Nesheim, Monica C. Wong-Chan, Robert C. Zak, Jr., Paul N. LoewensteinOriginal AssigneeSun Microsystems, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (23), Non-Patent Citations (18), Referenced by (44), Classifications (10), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMultiprocessing system having coherency-related error logging capabilities
US 5862316 AAbstract
Protocol agents involved in the performance of global coherency activity detect errors with respect to the activity being performed. The errors are logged by a computer system such that diagnostic software may be executed to determine the error detected and to trace the error to the erring software or hardware. In particular, information regarding the first error to be detected is logged. Subsequent errors may receive more or less logging depending upon programmable configuration values. Additionally, those errors which receive full logging may be programmably selected via error masks. The protocol agents each comprise multiple independent state machines which independently process requests. If the request which a particular state machine is processing results in an error, the particular state machine may enter a freeze state. Information regarding the request which is collected by the state machine may thereby be saved for later access. A state machine freezes upon detection of the error if a maximum number of the multiple state machines are not already frozen and the aforementioned error mask indicates that full error logging is employed for the detected error. Therefore, at least a minimum number of the multiple state machines remain functioning even in the presence of a large number of errors. Still further, prior to entering the freeze state, the protocol state machines may transition through a recovery state in which resources not used for error logging purposes are freed from the erring request.
1. An apparatus for logging errors, comprising:a protocol agent configured to perform a coherency action in response to an access to a coherency unit by a processing node wherein said protocol agent includes a plurality of state machines, and a first of said plurality of state machines is configured to perform said coherency action in response to said access concurrent with others of said plurality of state machines performing other coherency actions; and a storage device configured to store an indication of said protocol agent upon detection of an error by said protocol agent, said error corresponding to said coherency action; wherein said indication further identifies one of said plurality of state machines, and wherein said one of said plurality of state machines is performing said coherency action for which said error is detected. 2. The apparatus as recited in claim 1 wherein said protocol agent comprises a home agent.
3. The apparatus as recited in claim 1 wherein said protocol agent comprises a request agent.
4. The apparatus as recited in claim 3 wherein said request agent is further configured to log errors detected by a slave agent.
5. The apparatus as recited in claim 1 wherein said error comprises a timeout in which a predefined time interval expires from initiation of said access before said access is completed.
6. The apparatus as recited in claim 1 wherein said error comprises a receipt of an unexpected coherency action by said protocol agent.
7. The apparatus as recited in claim 1 further comprising a third storage device configured to store data identifying a transaction for which said error is detected.
8. A method for logging errors comprising:detecting an error with respect to a transaction being handled by one of a plurality of state machines comprising a protocol agent; transitioning to a recovery state within said one of said plurality of state machines upon said detecting, whereby resources occupied by said transaction are freed; and transitioning to a freeze state within said one of said plurality of state machines, whereby transaction information regarding said transaction is preserved, wherein said transitioning to a freeze state is replaced with transitioning to an idle state if more than a maximum number of said plurality of state machines are in said freeze state. 9. The method as recited in claim 8 wherein said maximum number is programmable.
10. The method as recited in claim 8 further comprising transition to said idle state instead of said freeze state if said error is disabled via a programmable mask field.
11. The method as recited in claim 8 further comprising storing an indication of said error in a register.
12. The method as recited in claim 8 wherein said protocol agent comprises a request agent.
13. The method as recited in claim 12 wherein said detecting comprises receiving an indication of said error from a slave agent.
14. A computer system comprising:a first processing node including a request agent, wherein said request agent is configured to detect and log a first error with respect to a coherency request initiated therefrom, and wherein said coherency request indicates an access right requested by said first processing node for a particular coherency unit, and wherein said coherency request is conveyed to a home node of said coherency unit; and a second processing node including a home agent, wherein said home agent is configured to detect and log a second error with respect to a coherency demand initiated therefrom in response to said coherency request, and wherein said coherency demand indicates a coherency state to be stored with respect to said particular coherency unit by a particular processing node receiving said coherency demand. 15. The computer system as recited in claim 14 further comprising a third processing node including a slave agent, wherein said slave agent is configured to detect a third error with respect to a coherency demand received therein, and wherein said slave agent is configured to transmit an indication of said third error to said request agent.
16. An apparatus for logging errors, comprising:a first protocol agent configured to perform a coherency action in response to an access to a coherency unit by a processing node, wherein said protocol agent includes a plurality of state machines, and a first of said plurality of state machines is configured to perform said coherency action in response to said access concurrent with others of said plurality of state machines performing other coherency actions; and a storage device configured to store an indication of said protocol agent upon detection of an error by said protocol agent, said error corresponding to said coherency action; wherein said one of said plurality of state machines which detects said error includes a freeze state, and wherein said freeze state is entered upon detection of said error if at least a remaining one of said plurality of state machines continues operating to handle other transactions; wherein said one of said plurality of state machines includes an idle state from which another coherency action may be initiated by said one of said plurality of state machines, and wherein said one of said plurality of state machines is configured to transition to said idle state upon detecting said error instead of transitioning to said freeze state if a maximum number of said plurality of state machines are in said freeze state. 17. The apparatus as recited in claim 16 wherein said one of said plurality of state machines transitions to said freeze state through a recovery state, wherein resources occupied by said access are freed.
This invention relates to the field of multiprocessor computer systems and, more particularly, to error logging functionality within multiprocessor computer systems.
Multiprocessing computer systems include two or more processors which may be employed to perform computing tasks. A particular computing task may be performed upon one processor while other processors perform unrelated computing tasks. Alternatively, components of a particular computing task may be distributed among multiple processors to decrease the time required to perform the computing task as a whole. Generally speaking, a processor is a device configured to perform an operation upon one or more operands to produce a result. The operation is performed in response to an instruction executed by the processor.
A popular architecture in commercial multiprocessing computer systems is the symmetric multiprocessor (SMP) architecture. Typically, an SMP computer system comprises multiple processors connected through a cache hierarchy to a shared bus. Additionally connected to the bus is a memory, which is shared among the processors in the system. Access to any particular memory location within the memory occurs in a similar amount of time as access to any other particular memory location. Since each location in the memory may be accessed in a uniform manner, this structure is often referred to as a uniform memory architecture (UMA).
Processors are often configured with internal caches, and one or more caches are typically included in the cache hierarchy between the processors and the shared bus in an SMP computer system. Multiple copies of data residing at a particular main memory address may be stored in these caches. In order to maintain the shared memory model, in which a particular address stores exactly one data value at any given time, shared bus computer systems employ cache coherency. Generally speaking, an operation is coherent if the effects of the operation upon data stored at a particular memory address are reflected in each copy of the data within the cache hierarchy. For example, when data stored at a particular memory address is updated, the update may be supplied to the caches which are storing copies of the previous data. Alternatively, the copies of the previous data may be invalidated in the caches such that a subsequent access to the particular memory address causes the updated copy to be transferred from main memory. For shared bus systems, a snoop bus protocol is typically employed. Each coherent transaction performed upon the shared bus is examined (or "snooped") against data in the caches. If a copy of the affected data is found, the state of the cache line containing the data may be updated in response to the coherent transaction.
Unfortunately, shared bus architectures suffer from several drawbacks which limit their usefulness in multiprocessing computer systems. A bus is capable of a peak bandwidth (e.g. a number of bytes/second which may be transferred across the bus). As additional processors are attached to the bus, the bandwidth required to supply the processors with data and instructions may exceed the peak bus bandwidth. Since some processors are forced to wait for available bus bandwidth, performance of the computer system suffers when the bandwidth requirements of the processors exceeds available bus bandwidth.
Additionally, adding more processors to a shared bus increases the capacitive loading on the bus and may even cause the physical length of the bus to be increased. The increased capacitive loading and extended bus length increases the delay in propagating a signal across the bus. Due to the increased propagation delay, transactions may take longer to perform. Therefore, the peak bandwidth of the bus may decrease as more processors are added.
These problems are further magnified by the continued increase in operating frequency and performance of processors. The increased performance enabled by the higher frequencies and more advanced processor microarchitectures results in higher bandwidth requirements than previous processor generations, even for the same number of processors. Therefore, buses which previously provided sufficient bandwidth for a multiprocessing computer system may be insufficient for a similar computer system employing the higher performance processors.
Another structure for multiprocessing computer systems is a distributed shared memory architecture. A distributed shared memory architecture includes multiple nodes within which processors and memory reside. The multiple nodes communicate via a network coupled there between. When considered as a whole, the memory included within the multiple nodes forms the shared memory for the computer system. Typically, directories are used to identify which nodes have cached copies of data corresponding to a particular address. Coherency activities may be generated via examination of the directories.
Distributed shared memory systems are scaleable, overcoming the limitations of the shared bus architecture. Since many of the processor accesses are completed within a node, nodes typically have much lower bandwidth requirements upon the network than a shared bus architecture must provide upon its shared bus. The nodes may operate at high clock frequency and bandwidth, accessing the network when needed. Additional nodes may be added to the network without affecting the local bandwidth of the nodes. Instead, only the network bandwidth is affected.
Since distributed shared memory computer systems support a large number of processors, these computer systems are often employed to perform so-called "mission critical" applications. Mission critical applications are applications upon which a particular business is highly dependent. If the mission critical application is unavailable, the operation of the business is seriously impacted. Accordingly, such a computer system is required to have an extremely high degree of availability and reliability. One measure of availability and reliability is the fault tolerance of the computer system. A computer system is fault tolerant if an error, whether hardware or software generated, does not cause the computer system to cease functioning. The faulting software may have its execution terminated. Similarly, the faulting hardware may be deactivated.
In addition to fault tolerance and possibly other properties enhancing the availability and reliability of the computer system, it is desirable for the computer system to provide error logging capabilities. By logging information regarding a detected error, a technician servicing the machine may be able to more easily locate the hardware or software which is generating the error. An error logging system for a distributed shared memory computer system is therefore desirable.
The problems outlined above are in large part solved by a computer system in accordance with the present invention. Protocol agents involved in the performance of global coherency activity detect errors with respect to the activity being performed. The errors are logged by the computer system such that diagnostic software may be executed to determine the error detected and to trace the error to the erring software or hardware. In particular, information regarding the first error to be detected is logged. Subsequent errors may receive more or less logging depending upon programmable configuration values. Additionally, those errors which receive full logging may be programmably selected via error masks.
In one embodiment, the protocol agents each comprise multiple independent state machines. Each state machine processes one request independent of other state machines processing other requests. If the request which a particular state machine is processing results in an error, the particular state machine may enter a freeze state. Information regarding the request which is collected by the state machine may thereby be saved for later access. A state machine freezes upon detection of the error if a maximum number of the multiple state machines are not already frozen and the aforementioned error mask indicates that full error logging is employed for the detected error. Therefore, at least a minimum number of the multiple state machines remain functioning even in the presence of a large number of errors.
Still further, prior to entering the freeze state, the protocol state machines may transition through a recovery state in which resources not used for error logging purposes are freed from the erring request. In this manner, subsequent requests may continue to be serviced properly. The computer system may therefore exhibit a high degree of reliability and availability.
Broadly speaking, the present invention contemplates an apparatus for logging errors, comprising a protocol agent and a storage device. The protocol agent is configured to perform a coherency action in response to an access to a coherency unit by a processing node. The storage device is configured to store an indication of the protocol agent upon detection of an error by the protocol agent.
The present invention further contemplates a method for logging errors. An error is detected with respect to a transaction being handled by one of a plurality of state machines comprising a protocol agent. A recovery state within one of the plurality of state machines is entered upon the detection, whereby resources occupied by the transaction are freed. Subsequently, a freeze state is entered within one of the plurality of state machines. In this manner, transaction information regarding the transaction is preserved.
The present invention still further contemplates a computer system comprising a first processing node and a second processing node. The first processing node includes a request agent configured to detect and log a first error with respect to a coherency request initiated therefrom. The second processing node includes a home agent configured to detect and log a second error with respect to a coherency demand initiated therefrom.
FIG. 1 is a block diagram of a multiprocessor computer system.
FIG. 1A is a conceptualized block diagram depicting a non-uniform memory architecture supported by one embodiment of the computer system shown in FIG. 1.
FIG. 1B is a conceptualized block diagram depicting a cache-only memory architecture supported by one embodiment of the computer system shown in FIG. 1.
FIG. 2 is a block diagram of one embodiment of a symmetric multiprocessing node depicted in FIG. 1.
FIG. 2A is an exemplary directory entry stored in one embodiment of a directory depicted in FIG. 2.
FIG. 3 is a block diagram of one embodiment of a system interface shown in FIG. 1.
FIG. 4 is a diagram depicting activities performed in response to a typical coherency operation between a request agent, a home agent, and a slave agent.
FIG. 5 is an exemplary coherency operation performed in response to a read to own request from a processor.
FIG. 6 is a flowchart depicting an exemplary state machine for one embodiment of a request agent shown in FIG. 3.
FIG. 7 is a flowchart depicting an exemplary state machine for one embodiment of a home agent shown in FIG. 3.
FIG. 8 is a flowchart depicting an exemplary state machine for one embodiment of a slave agent shown in FIG. 3.
FIG. 9 is a table listing request types according to one embodiment of the system interface.
FIG. 10 is a table listing demand types according to one embodiment of the system interface.
FIG. 11 is a table listing reply types according to one embodiment of the system interface.
FIG. 12 is a table listing completion types according to one embodiment of the system interface.
FIG. 13 is a table describing coherency operations in response to various operations performed by a processor, according to one embodiment of the system interface.
FIG. 14 is a flow chart depicting an exemplary state machine for a request agent including states for error logging.
FIG. 15 is a flow chart depicting an exemplary state machine for a home agent including states for error logging.
FIG. 16 is a diagram depicting a set of registers used to store information pertaining to detected errors.
FIG. 17 is a table listing information stored in an error status register shown in FIG. 16 according to one embodiment of the error status register.
FIG. 18 is a logic diagram depicting one embodiment of a counter circuit.
Turning now to FIG. 1, a block diagram of one embodiment of a multiprocessing computer system 10 is shown. Computer system 10 includes multiple SMP nodes 12A-12D interconnected by a point-to-point network 14. Elements referred to herein with a particular reference number followed by a letter will be collectively referred to by the reference number alone. For example, SMP nodes 12A-12D will be collectively referred to as SMP nodes 12. In the embodiment shown, each SMP node 12 includes multiple processors, external caches, an SMP bus, a memory, and a system interface. For example, SMP node 12A is configured with multiple processors including processors 16A-16B. The processors 16 are connected to external caches 18, which are further coupled to an SMP bus 20. Additionally, a memory 22 and a system interface 24 are coupled to SMP bus 20. Still further, one or more input/output (I/O) interfaces 26 may be coupled to SMP bus 20. I/O interfaces 26 are used to interface to peripheral devices such as serial and parallel ports, disk drives, modems, printers, etc. Other SMP nodes 12B-12D may be configured similarly.
Generally speaking, computer system 10 is configured to detect and log errors. More particularly, request agents and home agents involved in coherency activity are configured to detect errors related to the coherency activity being performed. The errors are logged, as well as information regarding the activity being performed when the error is detected. Additionally, resources within computer system 10 which are occupied by the transaction which initiated the coherency activity are freed, such that subsequent transactions and coherency operations may continue. For example, the transaction for which the error is detected may be reissued within the local node to free the reissue queue entry within system interface 24 occupied by the transaction. Still further, processor resources occupied by the transaction may be freed by allowing the transaction to complete. The reissue transaction may indicate that the transaction is completing with an error, such that the initiating processor may trap and allow corrective action to be taken by the operating system which controls computer system 10. Advantageously, coherency related errors are detected and remedied by computer system 10. Computer system 10 may continue to function despite the presence of such errors, enhancing the availability and reliability of the system.
In one embodiment, request agents and home agents implement a freeze state within the multiple independent state machines included therein. When an error is detected with respect to a transaction, the state machine handling that transaction is frozen. In other words, the state machine does not process any new transactions until specifically cleared by software. Therefore, information regarding the transaction and collected by the state machine is available for analysis. Debugging of the problem which caused the error may be simplified by the presence of the information. Still further, a recovery state may be entered prior to entry into the freeze state. The recovery state allows for actions to be taken to free resources occupied by the transaction for which the error is detected (if those resources are not useful for debugging purposes). Because multiple state machines are employed, other state machines may continue to process subsequent transactions while the state machines which detected the errors remain frozen. A programmable property of system interface 24 defines the maximum number of state machines which may be simultaneously frozen. Errors detected after the maximum number is reached are logged, but the state machine is not frozen. In this manner, at least a minimum number of state machines remain operating even in the presence of frequent errors.
Generally speaking, a memory operation is an operation causing transfer of data from a source to a destination. The source and/or destination may be storage locations within the initiator, or may be storage locations within memory. When a source or destination is a storage location within memory, the source or destination is specified via an address conveyed with the memory operation. Memory operations may be read or write operations. A read operation causes transfer of data from a source outside of the initiator to a destination within the initiator. Conversely, a write operation causes transfer of data from a source within the initiator to a destination outside of the initiator. In the computer system shown in FIG. 1, a memory operation may include one or more transactions upon SMP bus 20 as well as one or more coherency operations upon network 14.
Each SMP node 12 is essentially an SMP system having memory 22 as the shared memory. Processors 16 are high performance processors. In one embodiment, each processor 16 is a SPARC processor compliant with version 9 of the SPARC processor architecture. It is noted, however, that any processor architecture may be employed by processors 16.
Typically, processors 16 include internal instruction and data caches. Therefore, external caches 18 are labeled as L2 caches (for level 2, wherein the internal caches are level 1 caches). If processors 16 are not configured with internal caches, then external caches 18 are level 1 caches. It is noted that the "level" nomenclature is used to identify proximity of a particular cache to the processing core within processor 16. Level 1 is nearest the processing core, level 2 is next nearest, etc. External caches 18 provide rapid access to memory addresses frequently accessed by the processor 16 coupled thereto. It is noted that external caches 18 may be configured in any of a variety of specific cache arrangements. For example, set-associative or direct-mapped configurations may be employed by external caches 18.
SMP bus 20 accommodates communication between processors 16 (through caches 18), memory 22, system interface 24, and I/O interface 26. In one embodiment, SMP bus 20 includes an address bus and related control signals, as well as a data bus and related control signals. Because the address and data buses are separate, a split-transaction bus protocol may be employed upon SMP bus 20. Generally speaking, a split-transaction bus protocol is a protocol in which a transaction occurring upon the address bus may differ from a concurrent transaction occurring upon the data bus. Transactions involving address and data include an address phase in which the address and related control information is conveyed upon the address bus, and a data phase in which the data is conveyed upon the data bus. Additional address phases and/or data phases for other transactions may be initiated prior to the data phase corresponding to a particular address phase. An address phase and the corresponding data phase may be correlated in a number of ways. For example, data transactions may occur in the same order that the address transactions occur. Alternatively, address and data phases of a transaction may be identified via a unique tag.
Memory 22 is configured to store data and instruction code for use by processors 16. Memory 22 preferably comprises dynamic random access memory (DRAM), although any type of memory may be used. Memory 22, in conjunction with similar illustrated memories in the other SMP nodes 12, forms a distributed shared memory system. Each address in the address space of the distributed shared memory is assigned to a particular node, referred to as the home node of the address. A processor within a different node than the home node may access the data at an address of the home node, potentially caching the data. Therefore, coherency is maintained between SMP nodes 12 as well as among processors 16 and caches 18 within a particular SMP node 12A-12D. System interface 24 provides internode coherency, while snooping upon SMP bus 20 provides intranode coherency.
In addition to maintaining internode coherency, system interface 24 detects addresses upon SMP bus 20 which require a data transfer to or from another SMP node 12. System interface 24 performs the transfer, and provides the corresponding data for the transaction upon SMP bus 20. In the embodiment shown, system interface 24 is coupled to a point-to-point network 14. However, it is noted that in alternative embodiments other networks may be used. In a point-to-point network, individual connections exist between each node upon the network. A particular node communicates directly with a second node via a dedicated link. To communicate with a third node, the particular node utilizes a different link than the one used to communicate with the second node.
It is noted that, although four SMP nodes 12 are shown in FIG. 1, embodiments of computer system 10 employing any number of nodes are contemplated.
FIGS. 1A and 1B are conceptualized illustrations of distributed memory architectures supported by one embodiment of computer system 10. Specifically, FIGS. 1A and 1B illustrate alternative ways in which each SMP node 12 of FIG. 1 may cache data and perform memory accesses. Details regarding the manner in which computer system 10 supports such accesses will be described in further detail below.
Turning now to FIG. 1A, a logical diagram depicting a first memory architecture 30 supported by one embodiment of computer system 10 is shown. Architecture 30 includes multiple processors 32A-32D, multiple caches 34A-34D, multiple memories 36A-36D, and an interconnect network 38. The multiple memories 36 form a distributed shared memory. Each address within the address space corresponds to a location within one of memories 36.
Architecture 30 is a non-uniform memory architecture (NUMA). In a NUMA architecture, the amount of time required to access a first memory address may be substantially different than the amount of time required to access a second memory address. The access time depends upon the origin of the access and the location of the memory 36A-36D which stores the accessed data. For example, if processor 32A accesses a first memory address stored in memory 36A, the access time may be significantly shorter than the access time for an access to a second memory address stored in one of memories 36B-36D. That is, an access by processor 32A to memory 36A may be completed locally (e.g. without transfers upon network 38), while a processor 32A access to memory 36B is performed via network 38. Typically, an access through network 38 is slower than an access completed within a local memory. For example, a local access might be completed in a few hundred nanoseconds while an access via the network might occupy a few microseconds.
Data corresponding to addresses stored in remote nodes may be cached in any of the caches 34. However, once a cache 34 discards the data corresponding to such a remote address, a subsequent access to the remote address is completed via a transfer upon network 38.
NUMA architectures may provide excellent performance characteristics for software applications which use addresses that correspond primarily to a particular local memory. Software applications which exhibit more random access patterns and which do not confine their memory accesses to addresses within a particular local memory, on the other hand, may experience a large amount of network traffic as a particular processor 32 performs repeated accesses to remote nodes.
Turning now to FIG. 1B, a logic diagram depicting a second memory architecture 40 supported by the computer system 10 of FIG. 1 is shown. Architecture 40 includes multiple processors 42A-42D, multiple caches 44A-44D, multiple memories 46A-46D, and network 48. However, memories 46 are logically coupled between caches 44 and network 48. Memories 46 serve as larger caches (e.g. a level 3 cache), storing addresses which are accessed by the corresponding processors 42. Memories 46 are said to "attract" the data being operated upon by a corresponding processor 42. As opposed to the NUMA architecture shown in FIG. 1A, architecture 40 reduces the number of accesses upon the network 48 by storing remote data in the local memory when the local processor accesses that data.
Architecture 40 is referred to as a cache-only memory architecture (COMA). Multiple locations within the distributed shared memory formed by the combination of memories 46 may store data corresponding to a particular address. No permanent mapping of a particular address to a particular storage location is assigned. Instead, the location storing data corresponding to the particular address changes dynamically based upon the processors 42 which access that particular address. Conversely, in the NUMA architecture a particular storage location within memories 46 is assigned to a particular address. Architecture 40 adjusts to the memory access patterns performed by applications executing thereon, and coherency is maintained between the memories 46.
In a preferred embodiment, computer system 10 supports both of the memory architectures shown in FIGS. 1A and 1B. In particular, a memory address may be accessed in a NUMA fashion from one SMP node 12A-12D while being accessed in a COMA manner from another SMP node 12A-12D. In one embodiment, a NUMA access is detected if certain bits of the address upon SMP bus 20 identify another SMP node 12 as the home node of the address presented. Otherwise, a COMA access is presumed. Additional details will be provided below.
In one embodiment, the COMA architecture is implemented using a combination of hardware and software techniques. Hardware maintains coherency between the locally cached copies of pages, and software (e.g. the operating system employed in computer system 10) is responsible for allocating and deallocating cached pages.
FIG. 2 depicts details of one implementation of an SMP node 12A that generally conforms to the SMP node 12A shown in FIG. 1. Other nodes 12 may be configured similarly. It is noted that alternative specific implementations of each SMP node 12 of FIG. 1 are also possible. The implementation of SMP node 12A shown in FIG. 2 includes multiple subnodes such as subnodes 50A and 50B. Each subnode 50 includes two processors 16 and corresponding caches 18, a memory portion 56, an address controller 52, and a data controller 54. The memory portions 56 within subnodes 50 collectively form the memory 22 of the SMP node 12A of FIG. 1. Other subnodes (not shown) are further coupled to SMP bus 20 to form the I/O interfaces 26.
As shown in FIG. 2, SMP bus 20 includes an address bus 58 and a data bus 60. Address controller 52 is coupled to address bus 58, and data controller 54 is coupled to data bus 60. FIG. 2 also illustrates system interface 24, including a system interface logic block 62, a translation storage 64, a directory 66, and a memory tag (MTAG) 68. Logic block 62 is coupled to both address bus 58 and data bus 60, and asserts an ignore signal 70 upon address bus 58 under certain circumstances as will be explained further below. Additionally, logic block 62 is coupled to translation storage 64, directory 66, MTAG 68, and network 14.
For the embodiment of FIG. 2, each subnode 50 is configured upon a printed circuit board which may be inserted into a backplane upon which SMP bus 20 is situated. In this manner, the number of processors and/or I/O interfaces 26 included within an SMP node 12 may be varied by inserting or removing subnodes 50. For example, computer system 10 may initially be configured with a small number of subnodes 50. Additional subnodes 50 may be added from time to time as the computing power required by the users of computer system 10 grows.
Address controller 52 provides an interface between caches 18 and the address portion of SMP bus 20. In the embodiment shown, address controller 52 includes an out queue 72 and some number of in queues 74. Out queue 72 buffers transactions from the processors connected thereto until address controller 52 is granted access to address bus 58. Address controller 52 performs the transactions stored in out queue 72 in the order those transactions were placed into out queue 72 (i.e. out queue 72 is a FIFO queue). Transactions performed by address controller 52 as well as transactions received from address bus 58 which are to be snooped by caches 18 and caches internal to processors 16 are placed into in queue 74.
Similar to out queue 72, in queue 74 is a FIFO queue. All address transactions are stored in the in queue 74 of each subnode 50 (even within the in queue 74 of the subnode 50 which initiates the address transaction). Address transactions are thus presented to caches 18 and processors 16 for snooping in the order they occur upon address bus 58. The order that transactions occur upon address bus 58 is the order for SMP node 12A. However, the complete system is expected to have one global memory order. This ordering expectation creates a problem in both the NUMA and COMA architectures employed by computer system 10, since the global order may need to be established by the order of operations upon network 14. If two nodes perform a transaction to an address, the order that the corresponding coherency operations occur at the home node for the address defines the order of the two transactions as seen within each node. For example, if two write transactions are performed to the same address, then the second write operation to arrive at the address' home node should be the second write transaction to complete (i.e. a byte location which is updated by both write transactions stores a value provided by the second write transaction upon completion of both transactions). However, the node which performs the second transaction may actually have the second transaction occur first upon SMP bus 20. Ignore signal 70 allows the second transaction to be transferred to system interface 24 without the remainder of the SMP node 12 reacting to the transaction.
Therefore, in order to operate effectively with the ordering constraints imposed by the out queue/in queue structure of address controller 52, system interface logic block 62 employs ignore signal 70. When a transaction is presented upon address bus 58 and system interface logic block 62 detects that a remote transaction is to be performed in response to the transaction, logic block 62 asserts the ignore signal 70. Assertion of the ignore signal 70 with respect to a transaction causes address controller 52 to inhibit storage of the transaction into in queues 74. Therefore, other transactions which may occur subsequent to the ignored transaction and which complete locally within SMP node 12A may complete out of order with respect to the ignored transaction without violating the ordering rules of in queue 74. In particular, transactions performed by system interface 24 in response to coherency activity upon network 14 may be performed and completed subsequent to the ignored transaction. When a response is received from the remote transaction, the ignored transaction may be reissued by system interface logic block 62 upon address bus 58. The transaction is thereby placed into in queue 74, and may complete in order with transactions occurring at the time of reissue.
It is noted that in one embodiment, once a transaction from a particular address controller 52 has been ignored, subsequent coherent transactions from that particular address controller 52 are also ignored. Transactions from a particular processor 16 may have an important ordering relationship with respect to each other, independent of the ordering requirements imposed by presentation upon address bus 58. For example, a transaction may be separated from another transaction by a memory synchronizing instruction such as the MEMBAR instruction included in the SPARC architecture. The processor 16 conveys the transactions in the order the transactions are to be performed with respect to each other. The transactions are ordered within out queue 72, and therefore the transactions originating from a particular out queue 72 are to be performed in order. Ignoring subsequent transactions from a particular address controller 52 allows the in-order rules for a particular out queue 72 to be preserved. It is further noted that not all transactions from a particular processor must be ordered. However, it is difficult to determine upon address bus 58 which transactions must be ordered and which transactions may not be ordered. Therefore, in this implementation, logic block 62 maintains the order of all transactions from a particular out queue 72. It is noted that other implementations of subnode 50 are possible that allow exceptions to this rule.
Data controller 54 routes data to and from data bus 60, memory portion 56 and caches 18. Data controller 54 may include in and out queues similar to address controller 52. In one embodiment, data controller 54 employs multiple physical units in a byte-sliced bus configuration.
Processors 16 as shown in FIG. 2 include memory management units (MMUs) 76A-76B. MMUs 76 perform a virtual to physical address translation upon the data addresses generated by the instruction code executed upon processors 16, as well as the instruction addresses. The addresses generated in response to instruction execution are virtual addresses. In other words, the virtual addresses are the addresses created by the programmer of the instruction code. The virtual addresses are passed through an address translation mechanism (embodied in MMUs 76), from which corresponding physical addresses are created. The physical address identifies a storage location within memory 22.
Address translation is performed for many reasons. For example, the address translation mechanism may be used to grant or deny a particular computing task's access to certain memory addresses. In this manner, the data and instructions within one computing task are isolated from the data and instructions of another computing task. Additionally, portions of the data and instructions of a computing task may be "paged out" to a hard disk drive. When a portion is paged out, the translation is invalidated. Upon access to the portion by the computing task, an interrupt occurs due to the failed translation. The interrupt allows the operating system to retrieve the corresponding information from the hard disk drive. In this manner, more virtual memory may be available than actual memory in memory 22. Many other uses for virtual memory are well known.
Referring back to the computer system 10 shown in FIG. 1 in conjunction with the SMP node 12A implementation illustrated in FIG. 2, the physical address computed by MMUs 76 is a local physical address (LPA) defining a location within the memory 22 associated with the SMP node 12 in which the processor 16 is located. MTAG 68 stores a coherency state for each "coherency unit" in memory 22. When an address transaction is performed upon SMP bus 20, system interface logic block 62 examines the coherency state stored in MTAG 68 for the accessed coherency unit. If the coherency state indicates that the SMP node 12 has sufficient access rights to the coherency unit to perform the access, then the address transaction proceeds. If, however, the coherency state indicates that coherency activity should be performed prior to completion of the transaction, then system interface logic block 62 asserts the ignore signal 70. Logic block 62 performs coherency operations upon network 14 to acquire the appropriate coherency state. When the appropriate coherency state is acquired, logic block 62 reissues the ignored transaction upon SMP bus 20. Subsequently, the transaction completes.
Generally speaking, the coherency state maintained for a coherency unit at a particular storage location (e.g. a cache or a memory 22) indicates the access rights to the coherency unit at that SMP node 12. The access right indicates the validity of the coherency unit, as well as the read/write permission granted for the copy of the coherency unit within that SMP node 12. In one embodiment, the coherency states employed by computer system 10 are modified, owned, shared, and invalid. The modified state indicates that the SMP node 12 has updated the corresponding coherency unit. Therefore, other SMP nodes 12 do not have a copy of the coherency unit. Additionally, when the modified coherency unit is discarded by the SMP node 12, the coherency unit is stored back to the home node. The owned state indicates that the SMP node 12 is responsible for the coherency unit, but other SMP nodes 12 may have shared copies. Again, when the coherency unit is discarded by the SMP node 12, the coherency unit is stored back to the home node. The shared state indicates that the SMP node 12 may read the coherency unit but may not update the coherency unit without acquiring the owned state. Additionally, other SMP nodes 12 may have copies of the coherency unit as well. Finally, the invalid state indicates that the SMP node 12 does not have a copy of the coherency unit. In one embodiment, the modified state indicates write permission and any state but invalid indicates read permission to the corresponding coherency unit.
As used herein, a coherency unit is a number of contiguous bytes of memory which are treated as a unit for coherency purposes. For example, if one byte within the coherency unit is updated, the entire coherency unit is considered to be updated. In one specific embodiment, the coherency unit is a cache line, comprising 64 contiguous bytes. It is understood, however, that a coherency unit may comprise any number of bytes.
System interface 24 also includes a translation mechanism which utilizes translation storage 64 to store translations from the local physical address to a global address (GA). Certain bits within the global address identify the home node for the address, at which coherency information is stored for that global address. For example, an embodiment of computer system 10 may employ four SMP nodes 12 such as that of FIG. 1. In such an embodiment, two bits of the global address identify the home node. Preferably, bits from the most significant portion of the global address are used to identify the home node. The same bits are used in the local physical address to identify NUMA accesses. If the bits of the LPA indicate that the local node is not the home node, then the LPA is a global address and the transaction is performed in NUMA mode. Therefore, the operating system places global addresses in MMUs 76 for any NUMA-type pages. Conversely, the operating system places LPAs in MMU 76 for any COMA-type pages. It is noted that an LPA may equal a GA (for NUMA accesses as well as for global addresses whose home is within the memory 22 in the node in which the LPA is presented). Alternatively, an LPA may be translated to a GA when the LPA identifies storage locations used for storing copies of data having a home in another SMP node 12.
The directory 66 of a particular home node identifies which SMP nodes 12 have copies of data corresponding to a given global address assigned to the home node such that coherency between the copies may be maintained. Additionally, the directory 66 of the home node identifies the SMP node 12 which owns the coherency unit. Therefore, while local coherency between caches 18 and processors 16 is maintained via snooping, system-wide (or global) coherency is maintained using MTAG 68 and directory 66. Directory 66 stores the coherency information corresponding to the coherency units which are assigned to SMP node 12A (i.e. for which SMP node 12A is the home node).
It is noted that for the embodiment of FIG. 2, directory 66 and MTAG 68 store information for each coherency unit (i.e., on a coherency unit basis). Conversely, translation storage 64 stores local physical to global address translations defined for pages. A page includes multiple coherency units, and is typically several kilobytes or even megabytes in size.
Software accordingly creates local physical address to global address translations on a page basis (thereby allocating a local memory page for storing a copy of a remotely stored global page). Therefore, blocks of memory 22 are allocated to a particular global address on a page basis as well. However, as stated above, coherency states and coherency activities are performed upon a coherency unit. Therefore, when a page is allocated in memory to a particular global address, the data corresponding to the page is not necessarily transferred to the allocated memory. Instead, as processors 16 access various coherency units within the page, those coherency units are transferred from the owner of the coherency unit. In this manner, the data actually accessed by SMP node 12A is transferred into the corresponding memory 22. Data not accessed by SMP node 12A may not be transferred, thereby reducing overall bandwidth usage upon network 14 in comparison to embodiments which transfer the page of data upon allocation of the page in memory 22.
It is noted that in one embodiment, translation storage 64, directory 66, and/or MTAG 68 may be caches which store only a portion of the associated translation, directory, and MTAG information, respectively. The entirety of the translation, directory, and MTAG information is stored in tables within memory 22 or a dedicated memory storage (not shown). If required information for an access is not found in the corresponding cache, the tables are accessed by system interface 24.
Turning now to FIG. 2A, an exemplary directory entry 71 is shown. Directory entry 71 may be employed by one embodiment of directory 66 shown in FIG. 2. Other embodiments of directory 66 may employ dissimilar directory entries. Directory entry 71 includes a valid bit 73, a write back bit 75, an owner field 77, and a sharers field 79. Directory entry 71 resides within the table of directory entries, and is located within the table via the global address identifying the corresponding coherency unit. More particularly, the directory entry 71 associated with a coherency unit is stored within the table of directory entries at an offset formed from the global address which identifies the coherency unit.
Valid bit 73 indicates, when set, that directory entry 71 is valid (i.e. that directory entry 71 is storing coherency information for a corresponding coherency unit). When clear, valid bit 73 indicates that directory entry 71 is invalid.
Owner field 77 identifies one of SMP nodes 12 as the owner of the coherency unit. The owning SMP node 12A-12D maintains the coherency unit in either the modified or owned states. Typically, the owning SMP node 12A-12D acquires the coherency unit in the modified state (see FIG. 13 below). Subsequently, the owning SMP node 12A-12D may then transition to the owned state upon providing a copy of the coherency unit to another SMP node 12A-12D. The other SMP node 12A-12D acquires the coherency unit in the shared state. In one embodiment, owner field 77 comprises two bits encoded to identify one of four SMP nodes 12A-12D as the owner of the coherency unit.
Sharers field 79 includes one bit assigned to each SMP node 12A-12D. If an SMP node 12A-12D is maintaining a shared copy of the coherency unit, the corresponding bit within sharers field 79 is set. Conversely, if the SMP node 12A-12D is not maintaining a shared copy of the coherency unit, the corresponding bit within sharers field 79 is clear. In this manner, sharers field 79 indicates all of the shared copies of the coherency unit which exist within the computer system 10 of FIG. 1.
Write back bit 75 indicates, when set, that the SMP node 12A-12D identified as the owner of the coherency unit via owner field 77 has written the updated copy of the coherency unit to the home SMP node 12. When clear, bit 75 indicates that the owning SMP node 12A-12D has not written the updated copy of the coherency unit to the home SMP node 12A-12D.
Turning now to FIG. 3, a block diagram of one embodiment of system interface 24 is shown. As shown in FIG. 3, system interface 24 includes directory 66, translation storage 64, and MTAG 68. Translation storage 64 is shown as a global address to local physical address (GA2LPA) translation unit 80 and a local physical address to global address (LPA2GA) translation unit 82.
System interface 24 also includes input and output queues for storing transactions to be performed upon SMP bus 20 or network 14. Specifically, for the embodiment shown, system interface 24 includes input header queue 84 and output header queue 86 for buffering header packets to and from network 14. Header packets identify an operation to be performed, and specify the number and format of any data packets which may follow. Output header queue 86 buffers header packets to be transmitted upon network 14, and input header queue 84 buffers header packets received from network 14 until system interface 24 processes the received header packets. Similarly, data packets are buffered in input data queue 88 and output data queue 90 until the data may be transferred upon SMP data bus 60 and network 14, respectively.
SMP out queue 92, SMP in queue 94, and SMP I/O in queue (PIQ) 96 are used to buffer address transactions to and from address bus 58. SMP out queue 92 buffers transactions to be presented by system interface 24 upon address bus 58. Reissue transactions queued in response to the completion of coherency activity with respect to an ignored transaction are buffered in SMP out queue 92. Additionally, transactions generated in response to coherency activity received from network 14 are buffered in SMP out queue 92. SMP in queue 94 stores coherency related transactions to be serviced by system interface 24. Conversely, SMP PIQ 96 stores I/O transactions to be conveyed to an I/O interface residing in another SMP node 12. I/O transactions generally are considered non-coherent and therefore do not generate coherency activities.
SMP in queue 94 and SMP PIQ 96 receive transactions to be queued from a transaction filter 98. Transaction filter 98 is coupled to MTAG 68 and SMP address bus 58. If transaction filter 98 detects an I/O transaction upon address bus 58 which identifies an I/O interface upon another SMP node 12, transaction filter 98 places the transaction into SMP PIQ 96. If a coherent transaction to an LPA address is detected by transaction filter 98, then the corresponding coherency state from MTAG 68 is examined. In accordance with the coherency state, transaction filter 98 may assert ignore signal 70 and may queue a coherency transaction in SMP in queue 94. Ignore signal 70 is asserted and a coherency transaction queued if MTAG 68 indicates that insufficient access rights to the coherency unit for performing the coherent transaction is maintained by SMP node 12A. Conversely, ignore signal 70 is deasserted and a coherency transaction is not generated if MTAG 68 indicates that a sufficient access right is maintained by SMP node 12A.
Transactions from SMP in queue 94 and SMP PIQ 96 are processed by a request agent 100 within system interface 24. Prior to action by request agent 100, LPA2GA translation unit 82 translates the address of the transaction (if it is an LPA address) from the local physical address presented upon SMP address bus 58 into the corresponding global address. Request agent 100 then generates a header packet specifying a particular coherency request to be transmitted to the home node identified by the global address. The coherency request is placed into output header queue 86. Subsequently, a coherency reply is received into input header queue 84. Request agent 100 processes the coherency replies from input header queue 84, potentially generating reissue transactions for SMP out queue 92 (as described below).
Also included in system interface 24 is a home agent 102 and a slave agent 104. Home agent 102 processes coherency requests received from input header queue 84. From the coherency information stored in directory 66 with respect to a particular global address, home agent 102 determines if a coherency demand is to be transmitted to one or more slave agents in other SMP nodes 12. In one embodiment, home agent 102 blocks the coherency information corresponding to the affected coherency unit. In other words, subsequent requests involving the coherency unit are not performed until the coherency activity corresponding to the coherency request is completed. According to one embodiment, home agent 102 receives a coherency completion from the request agent which initiated the coherency request (via input header queue 84). The coherency completion indicates that the coherency activity has completed. Upon receipt of the coherency completion, home agent 102 removes the block upon the coherency information corresponding to the affected coherency unit. It is noted that, since the coherency information is blocked until completion of the coherency activity, home agent 102 may update the coherency information in accordance with the coherency activity performed immediately when the coherency request is received.
Slave agent 104 receives coherency demands from home agents of other SMP nodes 12 via input header queue 84. In response to a particular coherency demand, slave agent 104 may queue a coherency transaction in SMP out queue 92. In one embodiment, the coherency transaction may cause caches 18 and caches internal to processors 16 to invalidate the affected coherency unit. If the coherency unit is modified in the caches, the modified data is transferred to system interface 24. Alternatively, the coherency transaction may cause caches 18 and caches internal to processors 16 to change the coherency state of the coherency unit to shared. Once slave agent 104 has completed activity in response to a coherency demand, slave agent 104 transmits a coherency reply to the request agent which initiated the coherency request corresponding to the coherency demand. The coherency reply is queued in output header queue 86. Prior to performing activities in response to a coherency demand, the global address received with the coherency demand is translated to a local physical address via GA2LPA translation unit 80.
According to one embodiment, the coherency protocol enforced by request agents 100, home agents 102, and slave agents 104 includes a write invalidate policy. In other words, when a processor 16 within an SMP node 12 updates a coherency unit, any copies of the coherency unit stored within other SMP nodes 12 are invalidated. However, other write policies may be used in other embodiments. For example, a write update policy may be employed. According to a write update policy, when an coherency unit is updated the updated data is transmitted to each of the copies of the coherency unit stored in each of the SMP nodes 12.
Turning next to FIG. 4, a diagram depicting typical coherency activity performed between the request agent 100 of a first SMP node 12A-12D (the "requesting node"), the home agent 102 of a second SMP node 12A-12D (the "home node"), and the slave agent 104 of a third SMP node 12A-12D (the "slave node") in response to a particular transaction upon the SMP bus 20 within the SMP node 12 corresponding to request agent 100 is shown. Specific coherency activities employed according to one embodiment of computer system 10 as shown in FIG. 1 are further described below with respect to FIGS. 9-13. Reference numbers 100, 102, and 104 are used to identify request agents, home agents, and slave agents throughout the remainder of this description. It is understood that, when an agent communicates with another agent, the two agents often reside in different SMP nodes 12A-12D.
Upon receipt of a transaction from SMP bus 20, request agent 100 forms a coherency request appropriate for the transaction and transmits the coherency request to the home node corresponding to the address of the transaction (reference number 110). The coherency request indicates the access right requested by request agent 100, as well as the global address of the affected coherency unit. The access right requested is sufficient for allowing occurrence of the transaction being attempted in the SMP node 12 corresponding to request agent 100.
Upon receipt of the coherency request, home agent 102 accesses the associated directory 66 and determines which SMP nodes 12 are storing copies of the affected coherency unit. Additionally, home agent 102 determines the owner of the coherency unit. Home agent 102 may generate a coherency demand to the slave agents 104 of each of the nodes storing copies of the affected coherency unit, as well as to the slave agent 104 of the node which has the owned coherency state for the affected coherency unit (reference number 112). The coherency demands indicate the new coherency state for the affected coherency unit in the receiving SMP nodes 12. While the coherency request is outstanding, home agent 102 blocks the coherency information corresponding to the affected coherency unit such that subsequent coherency requests involving the affected coherency unit are not initiated by the home agent 102. Home agent 102 additionally updates the coherency information to reflect completion of the coherency request.
Home agent 102 may additionally transmit a coherency reply to request agent 100 (reference number 114). The coherency reply may indicate the number of coherency replies which are forthcoming from slave agents 104. Alternatively, certain transactions may be completed without interaction with slave agents 104. For example, an I/O transaction targeting an I/O interface 26 in the SMP node 12 containing home agent 102 may be completed by home agent 102. Home agent 102 may queue a transaction for the associated SMP bus 20 (reference number 116), and then transmit a reply indicating that the transaction is complete.
A slave agent 104, in response to a coherency demand from home agent 102, may queue a transaction for presentation upon the associated SMP bus 20 (reference number 118). Additionally, slave agents 104 transmit a coherency reply to request agent 100 (reference number 120). The coherency reply indicates that the coherency demand received in response to a particular coherency request has been completed by that slave. The coherency reply is transmitted by slave agents 104 when the coherency demand has been completed, or at such time prior to completion of the coherency demand at which the coherency demand is guaranteed to be completed upon the corresponding SMP node 12 and at which no state changes to the affected coherency unit will be performed prior to completion of the coherency demand.
When request agent 100 has received a coherency reply from each of the affected slave agents 104, request agent 100 transmits a coherency completion to home agent 102 (reference number 122). Upon receipt of the coherency completion, home agent 102 removes the block from the corresponding coherency information. Request agent 100 may queue a reissue transaction for performance upon SMP bus 20 to complete the transaction within the SMP node 12 (reference number 124).
It is noted that each coherency request is assigned a unique tag by the request agent 100 which issues the coherency request. Subsequent coherency demands, coherency replies, and coherency completions include the tag. In this manner, coherency activity regarding a particular coherency request may be identified by each of the involved agents. It is further noted that non-coherent operations may be performed in response to non-coherent transactions (e.g. I/O transactions). Non-coherent operations may involve only the requesting node and the home node. Still further, a different unique tag may be assigned to each coherency request by the home agent 102. The different tag identifies the home agent 102, and is used for the coherency completion in lieu of the requester tag.
Turning now to FIG. 5, a diagram depicting coherency activity for an exemplary embodiment of computer system 10 in response to a read to own transaction upon SMP bus 20 is shown. A read to own transaction is performed when a cache miss is detected for a particular datum requested by a processor 16 and the processor 16 requests write permission to the coherency unit. A store cache miss may generate a read to own transaction, for example.
A request agent 100, home agent 102, and several slave agents 104 are shown in FIG. 5. The node receiving the read to own transaction from SMP bus 20 stores the affected coherency unit in the invalid state (e.g. the coherency unit is not stored in the node). The subscript "i" in request node 100 indicates the invalid state. The home node stores the coherency unit in the shared state, and nodes corresponding to several slave agents 104 store the coherency unit in the shared state as well. The subscript "s" in home agent 102 and slave agents 104 is indicative of the shared state at those nodes. The read to own operation causes transfer of the requested coherency unit to the requesting node. The requesting node receives the coherency unit in the modified state.
Upon receipt of the read to own transaction from SMP bus 20, request agent 100 transmits a read to own coherency request to the home node of the coherency unit (reference number 130). The home agent 102 in the receiving home node detects the shared state for one or more other nodes. Since the slave agents are each in the shared state, not the owned state, the home node may supply the requested data directly. Home agent 102 transmits a data coherency reply to request agent 100, including the data corresponding to the requested coherency unit (reference number 132). Additionally, the data coherency reply indicates the number of acknowledgments which are to be received from slave agents of other nodes prior to request agent 100 taking ownership of the data. Home agent 102 updates directory 66 to indicate that the requesting SMP node 12A-12D is the owner of the coherency unit, and that each of the other SMP nodes 12A-12D is invalid. When the coherency information regarding the coherency unit is unblocked upon receipt of a coherency completion from request agent 100, directory 66 matches the state of the coherency unit at each SMP node 12.
Home agent 102 transmits invalidate coherency demands to each of the slave agents 104 which are maintaining shared copies of the affected coherency unit (reference numbers 134A, 134B, and 134C). The invalidate coherency demand causes the receiving slave agent to invalidate the corresponding coherency unit within the node, and to send an acknowledge coherency reply to the requesting node indicating completion of the invalidation. Each slave agent 104 completes invalidation of the coherency unit and subsequently transmits an acknowledge coherency reply (reference numbers 136A, 136B, and 136C). In one embodiment, each of the acknowledge replies includes a count of the total number of replies to be received by request agent 100 with respect to the coherency unit.
Subsequent to receiving each of the acknowledge coherency replies from slave agents 104 and the data coherency reply from home agent 102, request agent 100 transmits a coherency completion to home agent 102 (reference number 138). Request agent 100 validates the coherency unit within its local memory, and home agent 102 releases the block upon the corresponding coherency information. It is noted that data coherency reply 132 and acknowledge coherency replies 136 may be received in any order depending upon the number of outstanding transactions within each node, among other things.
Turning now to FIG. 6, a flowchart 140 depicting an exemplary state machine for use by request agents 100 is shown. Request agents 100 may include multiple independent copies of the state machine represented by flowchart 140, such that multiple requests may be concurrently processed.
Upon receipt of a transaction from SMP in queue 94, request agent 100 enters a request ready state 142. In request ready state 142, request agent 100 transmits a coherency request to the home agent 102 residing in the home node identified by the global address of the affected coherency unit. Upon transmission of the coherency request, request agent 100 transitions to a request active state 144. During request active state 144, request agent 100 receives coherency replies from slave agents 104 (and optionally from home agent 102). When each of the coherency replies has been received, request agent 100 transitions to a new state depending upon the type of transaction which initiated the coherency activity. Additionally, request active state 142 may employ a timer for detecting that coherency replies have not be received within a predefined time-out period. If the timer expires prior to the receipt of the number of replies specified by home agent 102, then request agent 100 transitions to an error state (not shown). Still further, certain embodiments may employ a reply indicating that a read transfer failed. If such a reply is received, request agent 100 transitions to request ready state 142 to reattempt the read.
If replies are received without error or time-out, then the state transitioned to by request agent 100 for read transactions is read complete state 146. It is noted that, for read transactions, one of the received replies may include the data corresponding to the requested coherency unit. Request agent 100 reissues the read transaction upon SMP bus 20 and further transmits the coherency completion to home agent 102. Subsequently, request agent 100 transitions to an idle state 148. A new transaction may then be serviced by request agent 100 using the state machine depicted in FIG. 6.
Conversely, write active state 150 and ignored write reissue state 152 are used for write transactions. Ignore signal 70 is not asserted for certain write transactions in computer system 10, even when coherency activity is initiated upon network 14. For example, I/O write transactions are not ignored. The write data is transferred to system interface 24, and is stored therein. Write active state 150 is employed for non-ignored write transactions, to allow for transfer of data to system interface 24 if the coherency replies are received prior to the data phase of the write transaction upon SMP bus 20. Once the corresponding data has been received, request agent 100 transitions to write complete state 154. During write complete state 154, the coherency completion reply is transmitted to home agent 102. Subsequently, request agent 100 transitions to idle state 148.
Ignored write transactions are handled via a transition to ignored write reissue state 152. During ignored write reissue state 152, request agent 100 reissues the ignored write transaction upon SMP bus 20. In this manner, the write data may be transferred from the originating processor 16 and the corresponding write transaction released by processor 16. Depending upon whether or not the write data is to be transmitted with the coherency completion, request agent 100 transitions to either the ignored write active state 156 or the ignored write complete state 158. Ignored write active state 156, similar to write active state 150, is used to await data transfer from SMP bus 20. During ignored write complete state 158, the coherency completion is transmitted to home agent 102. Subsequently, request agent 100 transitions to idle state 148. From idle state 148, request agent 100 transitions to request ready state 142 upon receipt of a transaction from SMP in queue 94.
Turning next to FIG. 7, a flowchart 160 depicting an exemplary state machine for home agent 102 is shown. Home agents 102 may include multiple independent copies of the state machine represented by flowchart 160 in order to allow for processing of multiple outstanding requests to the home agent 102. However, the multiple outstanding requests do not affect the same coherency unit, according to one embodiment.
Home agent 102 receives coherency requests in a receive request state 162. The request may be classified as either a coherent request or an other transaction request. Other transaction requests may include I/O read and I/O write requests, interrupt requests, and administrative requests, according to one embodiment. The non-coherent requests are handled by transmitting a transaction upon SMP bus 20, during a state 164. A coherency completion is subsequently transmitted. Upon receiving the coherency completion, I/O write and accepted interrupt transactions result in transmission of a data transaction upon SMP bus 20 in the home node (i.e. data only state 165). When the data has been transferred, home agent 102 transitions to idle state 166. Alternatively, I/O read, administrative, and rejected interrupted transactions cause a transition to idle state 166 upon receipt of the coherency completion.
Conversely, home agent 102 transitions to a check state 168 upon receipt of a coherent request. Check state 168 is used to detect if coherency activity is in progress for the coherency unit affected by the coherency request. If the coherency activity is in progress (i.e. the coherency information is blocked), then home agent 102 remains in check state 168 until the in-progress coherency activity completes. Home agent 102 subsequently transitions to a set state 170.
During set state 170, home agent 102 sets the status of the directory entry storing the coherency information corresponding to the affected coherency unit to blocked. The blocked status prevents subsequent activity to the affected coherency unit from proceeding, simplifying the coherency protocol of computer system 10. Depending upon the read or write nature of the transaction corresponding to the received coherency request, home agent 102 transitions to read state 172 or write reply state 174.
While in read state 172, home agent 102 issues coherency demands to slave agents 104 which are to be updated with respect to the read transaction. Home agent 102 remains in read state 172 until a coherency completion is received from request agent 100, after which home agent 102 transitions to clear block status state 176. In embodiments in which a coherency request for a read may fail, home agent 102 restores the state of the affected directory entry to the state prior to the coherency request upon receipt of a coherency completion indicating failure of the read transaction.
During write state 174, home agent 102 transmits a coherency reply to request agent 100. Home agent 102 remains in write reply state 174 until a coherency completion is received from request agent 100. If data is received with the coherency completion, home agent 102 transitions to write data state 178. Alternatively, home agent 102 transitions to clear block status state 176 upon receipt of a coherency completion not containing data.
Home agent 102 issues a write transaction upon SMP bus 20 during write data state 178 in order to transfer the received write data. For example, a write stream operation (described below) results in a data transfer of data to home agent 102. Home agent 102 transmits the received data to memory 22 for storage. Subsequently, home agent 102 transitions to clear blocked status state 176.
Home agent 102 clears the blocked status of the coherency information corresponding to the coherency unit affected by the received coherency request in clear block status state 176. The coherency information may be subsequently accessed. The state found within the unblocked coherency information reflects the coherency activity initiated by the previously received coherency request. After clearing the block status of the corresponding coherency information, home agent 102 transitions to idle state 166. From idle state 166, home agent 102 transitions to receive request state 162 upon receipt of a coherency request.
Turning now to FIG. 8, a flowchart 180 is shown depicting an exemplary state machine for slave agents 104. Slave agent 104 receives coherency demands during a receive state 182. In response to a coherency demand, slave agent 104 may queue a transaction for presentation upon SMP bus 20. The transaction causes a state change in caches 18 and caches internal to processors 16 in accordance with the received coherency demand. Slave agent 104 queues the transaction during send request state 184.
During send reply state 186, slave agent 104 transmits a coherency reply to the request agent 100 which initiated the transaction. It is noted that, according to various embodiments, slave agent 104 may transition from send request state 184 to send reply state 186 upon queuing the transaction for SMP bus 20 or upon successful completion of the transaction upon SMP bus 20. Subsequent to coherency reply transmittal, slave agent 104 transitions to an idle state 188. From idle state 188, slave agent 104 may transition to receive state 182 upon receipt of a coherency demand.
Turning now to FIGS. 9-12, several tables are shown listing exemplary coherency request types, coherency demand types, coherency reply types, and coherency completion types. The types shown in the tables of FIGS. 9-12 may be employed by one embodiment of computer system 10. Other embodiments may employ other sets of types.
FIG. 9 is a table 190 listing the types of coherency requests. A first column 192 lists a code for each request type, which is used in FIG. 13 below. A second column 194 lists the coherency requests types, and a third column 196 indicates the originator of the coherency request. Similar columns are used in FIGS. 10-12 for coherency demands, coherency replies, and coherency completions. An "R" indicates request agent 100; an "S" indicates slave agent 104; and an "H" indicates home agent 102.
A read to share request is performed when a coherency unit is not present in a particular SMP node and the nature of the transaction from SMP bus 20 to the coherency unit indicates that read access to the coherency unit is desired. For example, a cacheable read transaction may result in a read to share request. Generally speaking, a read to share request is a request for a copy of the coherency unit in the shared state. Similarly, a read to own request is a request for a copy of the coherency unit in the owned state. Copies of the coherency unit in other SMP nodes should be changed to the invalid state. A read to own request may be performed in response to a cache miss of a cacheable write transaction, for example.
Read stream and write stream are requests to read or write an entire coherency unit. These operations are typically used for block copy operations. Processors 16 and caches 18 do not cache data provided in response to a read stream or write stream request. Instead, the coherency unit is provided as data to the processor 16 in the case of a read stream request, or the data is written to the memory 22 in the case of a write stream request. It is noted that read to share, read to own, and read stream requests may be performed as COMA operations (e.g. RTS, RTO, and RS) or as NUMA operations (e.g. RTSN, RTON, and RSN).
A write back request is performed when a coherency unit is to be written to the home node of the coherency unit. The home node replies with permission to write the coherency unit back. The coherency unit is then passed to the home node with the coherency completion.
The invalidate request is performed to cause copies of a coherency unit in other SMP nodes to be invalidated. An exemplary case in which the invalidate request is generated is a write stream transaction to a shared or owned coherency unit. The write stream transaction updates the coherency unit, and therefore copies of the coherency unit in other SMP nodes are invalidated.
I/O read and write requests are transmitted in response to I/O read and write transactions. I/O transactions are non-coherent (i.e. the transactions are not cached and coherency is not maintained for the transactions). I/O block transactions transfer a larger portion of data than normal I/O transactions. In one embodiment, sixty-four bytes of information are transferred in a block I/O operation while eight bytes are transferred in a non-block I/O transaction.
Flush requests cause copies of the coherency unit to be invalidated. Modified copies are returned to the home node. Interrupt requests are used to signal interrupts to a particular device in a remote SMP node. The interrupt may be presented to a particular processor 16, which may execute an interrupt service routine stored at a predefined address in response to the interrupt. Administrative packets are used to send certain types of reset signals between the nodes.
FIG. 10 is a table 198 listing exemplary coherency demand types. Similar to table 190, columns 192, 194, and 196 are included in table 198. A read to share demand is conveyed to the owner of a coherency unit, causing the owner to transmit data to the requesting node. Similarly, read to own and read stream demands cause the owner of the coherency unit to transmit data to the requesting node. Additionally, a read to own demand causes the owner to change the state of the coherency unit in the owner node to invalid. Read stream and read to share demands cause a state change to owned (from modified) in the owner node.
Invalidate demands do not cause the transfer of the corresponding coherency unit. Instead, an invalidate demand causes copies of the coherency unit to be invalidated. Finally, administrative demands are conveyed in response to administrative requests. It is noted that each of the demands are initiated by home agent 102, in response to a request from request agent 100.
FIG. 11 is a table 200 listing exemplary reply types employed by one embodiment of computer system 10. Similar to FIGS. 9 and 10, FIG. 11 includes columns 192, 194, and 196 for the coherency replies.
A data reply is a reply including the requested data. The owner slave agent typically provides the data reply for coherency requests. However, home agents may provide data for I/O read requests.
The acknowledge reply indicates that a coherency demand associated with a particular coherency request is completed. Slave agents typically provide acknowledge replies, but home agents provide acknowledge replies (along with data) when the home node is the owner of the coherency unit.
Slave not owned, address not mapped and error replies are conveyed by slave agent 104 when an error is detected. The slave not owned reply is sent if a slave is identified by home agent 102 as the owner of a coherency unit and the slave no longer owns the coherency unit. The address not mapped reply is sent if the slave receives a demand for which no device upon the corresponding SMP bus 20 claims ownership. Other error conditions detected by the slave agent are indicated via the error reply.
In addition to the error replies available to slave agent 104, home agent 102 may provide error replies. The negative acknowledge (NACK) and negative response (NOPE) are used by home agent 102 to indicate that the corresponding request is does not require service by home agent 102. The NACK transaction may be used to indicate that the corresponding request is rejected by the home node. For example, an interrupt request receives a NACK if the interrupt is rejected by the receiving node. An acknowledge (ACK) is conveyed if the interrupt is accepted by the receiving node. The NOPE transaction is used to indicate that a corresponding flush request was conveyed for a coherency unit which is not stored by the requesting node.
FIG. 12 is a table 202 depicting exemplary coherency completion types according to one embodiment of computer system 10. Similar to FIGS. 9-11, FIG. 12 includes columns 192, 194, and 196 for coherency completions.
A completion without data is used as a signal from request agent 100 to home agent 102 that a particular request is complete. In response, home agent 102 unblocks the corresponding coherency information. Two types of data completions are included, corresponding to dissimilar transactions upon SMP bus 20. One type of reissue transaction involves only a data phase upon SMP bus 20. This reissue transaction may be used for I/O write and interrupt transactions, in one embodiment. The other type of reissue transaction involves both an address and data phase. Coherent writes, such as write stream and write back, may employ the reissue transaction including both address and data phases. Finally, a completion indicating failure is included for read requests which fail to acquire the requested state.
Turning next to FIG. 13, a table 210 is shown depicting coherency activity in response to various transactions upon SMP bus 20. Table 210 depicts transactions which result in requests being transmitted to other SMP nodes 12. Transactions which complete within an SMP node are not shown. A "-" in a column indicates that no activity is performed with respect to that column in the case considered within a particular row. A transaction column 212 is included indicating the transaction received upon SMP bus 20 by request agent 100. MTAG column 214 indicates the state of the MTAG for the coherency unit accessed by the address corresponding to the transaction. The states shown include the MOSI states described above, and an "n" state. The "n" state indicates that the coherency unit is accessed in NUMA mode for the SMP node in which the transaction is initiated. Therefore, no local copy of the coherency unit is stored in the requesting nodes memory. Instead, the coherency unit is transferred from the home SMP node (or an owner node) and is transmitted to the requesting processor 16 or cache 18 without storage in memory 22.
A request column 216 lists the coherency request transmitted to the home agent identified by the address of the transaction. Upon receipt of the coherency request listed in column 216, home agent 102 checks the state of the coherency unit for the requesting node as recorded in directory 66. D column 218 lists the current state of the coherency unit recorded for the requesting node, and D' column 220 lists the state of the coherency unit recorded for the requesting node as updated by home agent 102 in response to the received coherency request. Additionally, home agent 102 may generate a first coherency demand to the owner of the coherency unit and additional coherency demands to any nodes maintaining shared copies of the coherency unit. The coherency demand transmitted to the owner is shown in column 222, while the coherency demand transmitted to the sharing nodes is shown in column 224. Still further, home agent 102 may transmit a coherency reply to the requesting node. Home agent replies are shown in column 226.
The slave agent 104 in the SMP node indicated as the owner of the coherency unit transmits a coherency reply as shown in column 228. Slave agents 104 in nodes indicated as sharing nodes respond to the coherency demands shown in column 224 with the coherency replies shown in column 230, subsequent to performing state changes indicated by the received coherency demand.
Upon receipt of the appropriate number of coherency replies, request agent 100 transmits a coherency completion to home agent 102. The coherency completions used for various transactions are shown in column 232.
As an example, a row 234 depicts the coherency activity in response to a read to share transaction upon SMP bus 20 for which the corresponding MTAG state is invalid. The corresponding request agent 100 transmits a read to share coherency request to the home node identified by the global address associated with the read to share transaction. For the case shown in row 234, the directory of the home node indicates that the requesting node is storing the data in the invalid state. The state in the directory of the home node for the requesting node is updated to shared, and read to share coherency demand is transmitted by home agent 102 to the node indicated by the directory to be the owner. No demands are transmitted to sharers, since the transaction seeks to acquire the shared state. The slave agent 104 in the owner node transmits the data corresponding to the coherency unit to the requesting node. Upon receipt of the data, the request agent 100 within the requesting node transmits a coherency completion to the home agent 102 within the home node. The transaction is therefore complete.
It is noted that the state shown in D column 218 may not match the state in MTAG column 214. For example, a row 236 shows a coherency unit in the invalid state in MTAG column 214. However, the corresponding state in D column 218 may be modified, owned, or shared. Such situations occur when a prior coherency request from the requesting node for the coherency unit is outstanding within computer system 10 when the access to MTAG 68 for the current transaction to the coherency unit is performed upon address bus 58. However, due to the blocking of directory entries during a particular access, the outstanding request is completed prior to access of directory 66 by the current request. For this reason, the generated coherency demands are dependent upon the directory state (which matches the MTAG state at the time the directory is accessed). For the example shown in row 236, since the directory indicates that the coherency unit now resides in the requesting node, the read to share request may be completed by simply reissuing the read transaction upon SMP bus 20 in the requesting node. Therefore, the home node acknowledges the request, including a reply count of one, and the requesting node may subsequently reissue the read transaction. It is further noted that, although table 210 lists many types of transactions, additional transactions may be employed according to various embodiments of computer system 10.
Turning now to FIG. 14, a flow chart 300 is shown depicting an exemplary request agent state machine which may be employed by request agent 100 in an embodiment of computer system 10 employing error logging. Multiple copies of the exemplary state machine may be employed by request agent 100 for concurrent processing of multiple coherency requests. Flow chart 300 includes states 142, 144, 146, 148, 150, 152, 154, 156, and 158 similar to flow chart 140 (shown in FIG. 6). Additionally, flow chart 300 includes a recovery state 302 and a freeze state 304.
In addition to the transitions to read complete state 146, write active state 150, and ignored write reissue state 152, request active state 144 is configured to transition to recovery state 302 upon detection of an error with respect to the active request. The error may be of several types. A first type of error is referred to as a timeout error. Request agent 100 implements a counter for each state machine included therein which is incremented on a regular basis while the state machine is in request active state 144. If the counter reaches a programmably defined maximum value before the state machine transitions out of the request active state 144, then the state machine transitions to recovery state 302. The maximum value is selected such that it is substantially longer than a coherency request requires if computer system 10 is operating properly. Therefore, if the timeout error occurs, then some component of computer system 10 may be malfunctioning.
A second type of error detected by request agent 100 is errors conveyed by a slave agent 104. For example, table 200 lists an ERR coherency reply, an ANM coherency reply, and an SNO coherency reply. If these coherency replies are received from a slave agent 104 by request agent 100, then the corresponding transaction is in error. Finally, request agent 100 detects a third type of error. The third type of error includes receiving an unexpected reply for a transaction or a parity error upon access to LPA2GA translation 82. Upon detection of the second and third types of errors, a transition from request active state 144 to recovery state 302 is performed.
Upon transition to recovery state 302, request agent 100 attempts to release as many resources as possible from the erring transaction such that the resources may be directed to other transactions. Certain resources may not be released (e.g. the state machine itself) so that information regarding the transaction may be accessible at a later time for diagnostic purposes.
In one particular embodiment, request agent 100 performs the following actions during recovery state 302:
(i) reissue a coherent transaction for which the ignore signal was asserted. The reissue transaction includes an address encoding which indicates an error, such that the initiating processor traps to an operating system routine;
(ii) reissue an I/O read transaction with a data packet indicating the I/O read completed with an error; and
(iii) reissue an interrupt transaction indicating that the interrupt received a NACK reply from the corresponding slave agent. By performing such activities when the corresponding transaction results in an error, the initiating processor may be informed of the error. It is noted that transactions other than those listed above may not require any recovery activity. For example, a transaction may not occupy an resources which require release. Additionally, the SMP node 12A-12D in which the error is detected may continue to operate despite the presence of the detected error.
From recovery state 302, the request agent state machine either transitions to idle state 148 or freeze state 304. If the request agent state machine determines that it may not freeze, then the request agent state machine transitions to idle state 148. Subsequently, the request agent state machine may accept a new transaction and begin performing coherency requests. On the other hand, the request agent state machine represented by flow chart 300 transitions to freeze state 304 if the request agent state machine determines that it may freeze.
Several factors may determine whether or not the request agent state machine shown in FIG. 14 may freeze upon detection of an error and subsequent performance of recovery steps. In one embodiment, a maximum number of frozen request agent state machines is defined. If the number of other request agent state machines which are frozen at the time a request agent state machine is ready to transition from recovery state 302 is equal to the maximum number of frozen request agent state machines, then the state machine transitions to idle state 148. Additionally, the embodiment includes a programmable mask which allows certain detectable errors to cause the detecting request agent state machine to freeze while other detectable errors do not. If the programmable mask indicates that the detected error is masked, then the request agent state machine transitions to idle state 148. Otherwise, the request agent state machine transitions to freeze state 304.
Once the request agent state machine has entered freeze state 304, the request agent state machine remains in that state until explicitly released. In one embodiment, a request agent state machine is released by updating a corresponding bit in a control register (described below). The information held by the request agent state machine regarding the transaction may thereby be examined by software (e.g. the operating system or diagnostic software). Upon completion of the examination, the software may update the control register to allow the request agent state machine to process transactions again. Upon being released, the request agent state machine transitions to idle state 148.
Turning now to FIG. 15, a flow chart 310 is shown depicting an exemplary home agent state machine which may be employed by home agent 102 in an embodiment of computer system 10 which implements error logging. Multiple copies of the exemplary state machine may be employed by home agent 102 for concurrent processing of multiple coherency demands. Flow chart 310 includes states 162, 164, 165, 166, 168, 170, 172, 174, 176, and 178 similar to flow chart 160 (shown in FIG. 7). Additionally, flow chart 310 includes a recovery state 312 and a freeze state 314.
The states within flow chart 310 are configured to transition to the freeze state 314 upon detection of an error with respect to the transaction for which coherency activity is being performed, if a freeze is allowable at the time of the transition (arc 316). Otherwise, a transition to the idle state 166 is performed (arc 318). Similar to request agent 100, home agent 102 includes a programmable maximum number of frozen home agent state machines. Upon detection of an error, a home agent state machine may freeze if the number of frozen agents is less than the maximum. Additionally, a programmable mask defines the errors which cause a freeze. The home agent state machine transitions to freeze state 314 if the programmable mask indicates that the detected error is a freezable error.
The errors detected by home agent 102 are of several types, according to one embodiment. A first type is the timeout error, similar to the timeout error described above. A second type of error is the receipt of an unexpected coherency operation; either an unexpected request or an unexpected completion. An unexpected request is detected if a request is received having an invalid transaction type (i.e. the type is not one of those listed in table 190 shown in FIG. 9. An unexpected completion is a completion received for a transaction which is not outstanding within home agent 102. A third type of error includes detecting a parity error while accessing the directory, detecting a request for an address which is not shareable with other nodes, and accessing a directory entry which indicates that an error was detected for the node.
As opposed to the request agent state machine depicted in FIG. 14, many transitions due to error are directly to freeze state 314 or idle state 166. In other words, recovery state 312 is not used for these transitions. Because home agent 102 is often not involved in transactions upon SMP bus 20 within the local node, typically there are no resources within system interface 24 and processors 16 to be freed due to the detected error. However, transactions which are serviced via send state 164 do cause a transaction upon SMP bus 20 within the home node. The transactions are I/O transactions, interrupt transactions, and administrative transactions. Upon detection of an error for these types of transactions, a transition to recovery state 312 is performed. From recovery state 312, the home agent state machine reissues the transaction upon SMP bus 20 within the home node, in a manner similar to the operation of recovery state 312 shown in FIG. 14. Subsequently, a transition to either freeze state 314 or idle state 166 is performed based on the freezability of the state machine as defined above.
Turning now to FIG. 16, a block diagram of registers employed by one embodiment of system interface 24 to support error logging is shown. Other embodiments may employ dissimilar or similar registers. FIG. 16 depicts an agent status register 320, an error status register 322, a request agent configuration register 324, a home agent configuration register 326, an agent freeze mask 328, a request agent state machine register 330, and a home agent state machine register 332.
Agent status register 320 stores information regarding the agent state machines which have detected errors. Agent status register 320 includes a first home field 334 and a first request field 336 which store an indication of the first home agent state machine and the first request agent state machine to detect errors, respectively. In other words, first home field 334 stores an indication of the home agent state machine which detected an error while all home agent state machines were still functioning normally. In one embodiment, sixteen copies of the home agent state machine and sixteen copies of the request agent state machine are included within home agent 102 and request agent 100, respectively. Therefore, first home field 334 and first request field 336 comprise four bits each and store a number assigned to the corresponding state machine which detected the first error.
Agent status register 320 further includes a home frozen field 338 and a request frozen field 340. Home frozen field 338 includes a bit for each home agent state machine. The bit is set if the corresponding home agent state machine is frozen. The bit is clear if the corresponding home agent state machine is not frozen (i.e. is functioning normally). Similarly, request frozen field 340 contains a bit for each request agent state machine indicating the frozen/not frozen status of the state machine. In the exemplary embodiment, home frozen field 338 and request frozen field 340 each comprise 16 bits.
Software may access agent status register 320 in order to determine which home agent state machine and/or request agent state machine detected the first error to occur within computer system 10. This information may be useful in that, once a first error has occurred, it may be more likely that additional errors will occur which may be an indirect result of the first error or in some way related to the first error. Therefore, by examining the conditions related to the first error, diagnostic procedures may more quickly determine the problem which lead to the detected error. Additionally, software may determine which home agent state machines and request agent state machines are frozen by examining home frozen field 338 and request frozen field 340. Furthermore, software may release a state machine from the frozen state (i.e. the arc labeled release in FIGS. 14 and 15) by updating the corresponding bit within the corresponding frozen field. In one embodiment, system interface 24 detects a binary one being stored into a particular bit in response to a software command and clears the particular bit in response, releasing the corresponding state machine.
Error status register 322 is used to store a general error status for a particular SMP node 12A-12D. FIG. 17, described below, indicates the status stored in error status register 322 for the exemplary embodiment.
Request agent 100 is configured using request agent configuration register 324. A freeze limit field 342, a counter freeze bit 344, a freeze enable bit 346, a timeout limit field 348, and an I/O limit field 350 are included in the embodiment of request agent configuration register shown in FIG. 16. Freeze limit field 342 codes a maximum number of request agent state machines which may be concurrently frozen. In this manner, at least a minimum number of request agent state machines will continue to service requests even if a large number of errors are incurred. The value of freeze limit field 342 is therefore used in determining if a request agent state machine transitions from the recovery state 302 to the freeze state 304 or to the idle state 148. Counter freeze bit 344 is used to freeze the timeout counters implemented by each of the request agent state machines to detect timeout errors. When the counter freeze bit 344 is set, the timeout counters do not increment. Therefore, timeout errors are not detected when the counter freeze bit 344 is set. Freeze enable bit 346 enables the request agent state machines to enter freeze state 302 in response to a timeout error. If freeze enable bit 346 is clear, then timeout errors do not cause a transition to freeze state 302.
Timeout limit field 348 encodes the timeout limit for transactions (i.e. the number of cycles which are allowed to elapse before detecting a timeout error). In one embodiment, timeout limit field 348 comprises three bits encoded as shown in Table 1 below:
TABLE 1______________________________________Encoding of Timeout Limit field 348Encoding     Limit (cycles)______________________________________0            2k1            1M2            2M3            4M4            8M______________________________________
It is often desirable to set the timeout limit to a value which will allow the request agent to time out before lower level hardware (e.g. processors 16 or other hardware within SMP nodes 12) time out. Such lower level hardware often shuts down when a timeout error occurs, but more graceful error handling is desired. A guideline for calculating the time out may be as follows:
______________________________________TO &lt;=   (lower level timeout * number of non-freezable   request agents) / (number of subnodes in a node   * maximum number of outstanding transactions per   node)______________________________________
The equation allows for request agent timeouts to occur for the worst possible case without generating a lower level timeout (i.e. the maximum number of transactions are outstanding, all the transactions are going to time out in request agent 100, and the maximum number of request agents are frozen). For example, if 8 of the sixteen request agents may be frozen (as encoded in freeze limit field 342), 16 Mcycles elapse before a lower level hardware timeout, and there are 16 subnodes in a node from which 7 transactions may be concurrently outstanding, the time out limit should be less than or equal to 1.14 Mcycles. Therefore, an encoding of 1 Mcycles may be suitable for such a configuration.
Finally, I/O limit field 350 encodes the maximum number of request agent state machines which may be concurrently servicing I/O requests. If an I/O transaction is queued in SMP PIQ 96 and the maximum number of I/O requests are being concurrently serviced by request agent state machines, the I/O transaction is not initiated until the completion of one of the outstanding I/O transactions.
Similar to request agent configuration register 324, home agent configuration register 326 includes freeze limit field 342, counter freeze bit 344, freeze enable bit 346, timeout limit field 348, and I/O limit field 350. However, these fields encode properties of the home agent state machines when included in home agent configuration register 326. Additionally, a DC size field 352 is included. DC size field 352 encodes the size (in bytes) of the directory cache line size. In one embodiment, DC size field 352 comprises two bits encoded as shown in table 2 below.
TABLE 2______________________________________DC Size Field Encoding  Encoding (binary)            Bytes______________________________________  00         8  01        16  10        32  11        64______________________________________
Agent freeze mask register 328 stores the aforementioned masks which allow request agent 100 and home agent 102 to be configured to freeze upon detection of certain errors while not freezing upon detection of other errors. In one embodiment, each mask includes a bit for each of the errors detected by the corresponding agent. If the bit is set, then a state machine within the agent freezes upon detection of the corresponding error. Alternatively, the agent does not freeze upon detection of an error for which the corresponding bit is clear. Agent freeze mask register 328 includes a request error mask field 354 and a home error mask field 356 corresponding to request agent 100 and home agent 102, respectively.
Each request agent state machine is accorded a request agent state machine register 330 for storing information regarding the transaction being serviced thereby. Request agent state machine register 330 includes an address field 358, a replies received field 360, an error code field 362, an original transaction field 364, an SNO bit 366, and a state field 368. Address field 358 stores the address of the transaction with which the error is associated. Replies received field 360 includes a bit for each SMP node 12A-12D. If the bit is set, a reply was received from the corresponding SMP node 12A-12D. Error code field 362 stores a code indicating the detected error. In one embodiment, error code field 362 comprises three bits encoded as shown in table 3 below.
TABLE 3______________________________________Error Code Field 362 EncodingEncoding (binary)         Error______________________________________001           Timeout010           Unexpected Reply011           LPA2GA Parity Error100           Slave Error101           Received ANM reply______________________________________
Original transaction field 364 stores an indication of the transaction as received from SMP bus 20. SNO bit 366 is set if an SNO reply is received from the owner slave agent 104. Finally, state field 368 indicates the state which the request agent state machine was in when the error was detected.
Similarly, each home agent state machine is accorded a home agent state machine register 332. Home agent state machine register 332 includes an address field 358, an original directory field 370, an error code field 372, a request field 374, a source ID field 376, and a source node field 378. Original directory field 370 stores the directory entry corresponding to the address stored in address field 358. The stored directory entry is the state of the directory entry prior to initiation of the operation for which the error was detected. Error code field 372 stores an indication of the detected error. In one embodiment, error code field 372 comprises three bits encoded as shown in table 4 below.
TABLE 4______________________________________Encoding for Error Code Field 372Encoding (Binary)        Error______________________________________001          Timeout010          Access to Directory Entry in the Error        state011          Directory Parity Error100          Non-shareable address requested101          Unexpected Request110          Unexpected Completion______________________________________
Request field 374 indicates the original request received from a request agent 100. Source ID field 376 stores the transaction ID of the transaction which caused initiation of the request being serviced by the home agent state machine. Finally, source node field 378 stores the node from which the request was received.
Turning now to FIG. 17, a table 380 is shown listing the contents of one embodiment of error status register 322. Table 380 lists the fields of the register (column 382) and a description of the field (column 384). A NIAC-- HW field is used to store hardware errors detected in system interface 24 itself. An IDQ-- PTR-- ERROR bit indicates, when set, that a parity error was detected within a packet received from network 14. The parity error is detected upon a field which indicates which entry within input data queue 92 is to store the data transmitted therewith. A GA2LPA-- VIOLA bit indicates that a violation is detected upon access to the GA2LPA cache by a slave agent. A violation is detected if the operation for which the slave agent accesses the GA2LPA cache is not allowed by the GA2LPA translation (i.e. a write to a read only coherency unit). The GA2LP-- PERR bit is set if a parity error is detected on access to the GA2LPA cache. A NETWORK-- ERROR bit is set if an error is detected upon network 14.
An AGENT-- ERROR bit is set if any of the bits within home frozen field 338 or request frozen field 340 are set. A HOME-- LOG field is used to log those errors for which the corresponding home agent state machine does not freeze (via home error mask field 356). One bit within the HOME-- LOG field corresponds to each of the errors detected by the home agent state machines. If an error is detected and a freeze does not occur, then the corresponding bit within the HOME-- LOG field is set. Similarly, the REQ-- LOG field logs errors which do not cause the detecting request agent state machine to freeze.
The ADM-- ERR bit is set if an unexpected administrative request is received. The HOME-- CERR bit is set if a frozen or idle home agent state machine receives a coherency completion. Similarly, the REQ-- RERR bit is set if a frozen or idle request agent state machine receives a coherency reply. Finally, the ECC-- PCE, ECC-- PUE, ECC-- CCE, and ECC-- CUE bits are set if an ECC error is detected upon SMP bus 20 with respect to the types of transactions listed in table 380.
Turning now to FIG. 18, an exemplary counter circuit 390 is shown. Counter circuit 390 may be employed as the timeout counter for the request agent state machines and/or home agent state machines. Counter circuit 390 includes a counter storage 392 having a counter field 394 and a carry bit 396 as well as a multiplexor 398. Multiplexor 398 selects the clock input for the counter circuit from a fast clock line 400 and a slow clock line 402. Carry bit 396 provides the selection control for multiplexor 398.
When counter circuit 390 is reset, both counter field 394 and carry bit 396 are cleared. The fast clock is selected via multiplexor 398, and the count value stored in counter field 394 begins incrementing at a rate of one increment per cycle of the fast clock. When the counter value overflows counter field 394, carry bit 396 is set. Counter field 394 returns to a cleared value. Because carry bit 396 is now set, the slow clock upon slow clock line 402 is used to increment counter circuit 390.
Counter circuit 390 advantageously implements the counter function using a small number of bits, yet still maintains the granularity to allow detection of the first of several timeouts which may occur relatively near to each other in time. The counter counts using the fast clock first, followed by a more slow counting using the slow clock. Since the slow counting does not begin until one overflow of the counter using the fast clock, operations which are initiated relatively close to each other in time begin counting on the slow clock at dissimilar times. The first initiated operation begins counting upon the slow counter first, followed by the second, etc. Therefore, the first operation times out before the second operation, etc. Whenever a carry bit 396 is initially set, an extra pulse is generated upon the slower clock to maintain the granularity generated by using the faster clock. In this manner, the counter which began counting with the slower clock first remains ahead of any counters which subsequently begin counting with the slower clock. By switching to the slower clock, a smaller number of bits may be used to count through a constant number of clock cycles than would be required if the fast clock were used throughout.
For example, the fast clock may be configured with a period of 4 clock cycles (wherein the clock defining the clock cycle is the clock supplied to system interface 24). If a timeout value of approximately 1 Mcycles is desired, then the counter circuit would require 18 bits (i.e. 218 ≅250 kcycle*4 clocks/fast clock period). However, using clock circuit 390 and a slow clock having a period of 2000 cycles, counter field 394 may comprise only nine bits (i.e. 29 =512*(2000 clocks/slow clock period+4 clocks/fast clock period)).
Although SMP nodes 12 have been described in the above exemplary embodiments, generally speaking an embodiment of computer system 10 may include one or more processing nodes. As used herein, a processing node includes at least one processor and a corresponding memory. Additionally, circuitry for communicating with other processing nodes is included. When more than one processing node is included in an embodiment of computer system 10, the corresponding memories within the processing nodes form a distributed shared memory. A processing node may be referred to as remote or local. A processing node is a remote processing node with respect to a particular processor if the processing node does not include the particular processor. Conversely, the processing node which includes the particular processor is that particular processor's local processing node.
It is noted that request agent 100 and home agent 102 have been described above as performing error logging. However, any protocol agent may perform similar error logging functionality. Generally speaking, a protocol agent is one or more state machines which perform a coherency action in response to a transaction for which coherency activity is necessary. A coherency action comprises a portion of the coherency activity used to acquire appropriate access rights to perform a particular transaction. The coherency action is performed by a single processing node involved in the coherency activity.
In accordance with the above disclosure, a computer system has been described which performs error logging with respect to coherency activity performed therein. The errors are logged for later diagnostic access, but the computer system remains functioning. Advantageously, the computer system exhibits a high degree of availability and reliability, enabling mission critical applications to be performed thereon.
Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, although various blocks and components shown herein have been described in terms of hardware embodiments, alternative embodiments may implement all or a portion of the hardware functionality in software. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4674038 *Dec 28, 1984Jun 16, 1987International Business Machines CorporationRecovery of guest virtual machines after failure of a host real machineUS5019971 *Aug 21, 1989May 28, 1991Prime Computer, Inc.High availability cache organizationUS5113514 *Feb 20, 1990May 12, 1992Prime Computer, Inc.System bus for multiprocessor computer systemUS5155731 *May 11, 1990Oct 13, 1992Fujitsu LimitedError logging data storing systemUS5253359 *Jun 11, 1990Oct 12, 1993Supercomputer Systems Limited PartnershipControl and maintenance subsystem network for use with a multiprocessor computer systemUS5355471 *Aug 14, 1992Oct 11, 1994Pyramid Technology CorporationIn a computer systemUS5361267 *Apr 24, 1992Nov 1, 1994Digital Equipment CorporationScheme for error handling in a computer systemUS5406504 *Jun 30, 1993Apr 11, 1995Digital EquipmentMultiprocessor cache examiner and coherency checkerUS5418794 *Dec 18, 1992May 23, 1995Amdahl CorporationIn a data processing systemUS5418927 *Dec 23, 1992May 23, 1995International Business Machines CorporationI/O cache controller containing a buffer memory partitioned into lines accessible by corresponding I/O devices and a directory to track the linesUS5428766 *Dec 1, 1992Jun 27, 1995Digital Equipment CorporationError detection scheme in a multiprocessor environmentUS5452430 *Mar 23, 1994Sep 19, 1995International Business Machines CorporationSystem and method for storing persistent and non-persistent queued data and for recovering the persistent data responsive to a system restartUS5463768 *Mar 17, 1994Oct 31, 1995General Electric CompanyMethod and system for analyzing error logs for diagnosticsUS5491788 *Sep 10, 1993Feb 13, 1996Compaq Computer Corp.Method of booting a multiprocessor computer where execution is transferring from a first processor to a second processor based on the first processor having had a critical errorUS5557748 *Feb 3, 1995Sep 17, 1996Intel CorporationDynamic network configurationUS5574849 *Jun 7, 1995Nov 12, 1996Tandem Computers IncorporatedSynchronized data transmission between elements of a processing systemUS5581713 *Nov 15, 1995Dec 3, 1996Pyramid Technology CorporationMultiprocessor computer backplane bus in which bus transactions are classified into different classes for arbitrationUS5581729 *Mar 31, 1995Dec 3, 1996Sun Microsystems, Inc.Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor systemUS5598550 *Nov 30, 1994Jan 28, 1997Motorola Inc.Cache controller for processing simultaneous cache accessesUS5608878 *Oct 3, 1994Mar 4, 1997International Business Machines CorporationDual latency status and coherency reporting for a multiprocessing systemUS5615335 *Nov 10, 1994Mar 25, 1997Emc CorporationStorage system self-test apparatus and methodUS5619644 *Sep 18, 1995Apr 8, 1997International Business Machines CorporationSoftware directed microcode state save for distributed storage controllerUS5629950 *Jul 8, 1996May 13, 1997Digital Equipment CorporationFault management scheme for a cache memory* Cited by examinerNon-Patent CitationsReference1Cox et al., "Adaptive Cache Coherency for Detecting Migratory Shared Data," Proc. 20th Annual Symposium on Computer Architecture, May 1993, pp. 98-108.2 *Cox et al., Adaptive Cache Coherency for Detecting Migratory Shared Data, Proc. 20 th Annual Symposium on Computer Architecture, May 1993, pp. 98 108.3D. Lenosky, PhD, "The Description and Analysis of DASH: A Scalable Directory-Based Multiprocessor," DASH Prototype System, Dec. 1991, pp. 36-56.4 *D. Lenosky, PhD, The Description and Analysis of DASH: A Scalable Directory Based Multiprocessor, DASH Prototype System , Dec. 1991, pp. 36 56.5Hagersten et al., "Simple COMA Node Implementations," Ashley Saulsbury and Anders Landin Swedish Institute of Computer Science, 12 pages.6Hagersten et al., "Simple COMA," Ashley Saulsbury and Anders Landin Swedish Institute of Computer Science, Jul. 1993, pp. 233-259.7 *Hagersten et al., Simple COMA Node Implementations, Ashley Saulsbury and Anders Landin Swedish Institute of Computer Science, 12 pages.8 *Hagersten et al., Simple COMA, Ashley Saulsbury and Anders Landin Swedish Institute of Computer Science, Jul. 1993, pp. 233 259.9Kourosh et al., "two Techniques to Enhance the Performance of Memory Consistency Models," 1991 International Conference on Parallel Processing, pp. 1-10.10 *Kourosh et al., two Techniques to Enhance the Performance of Memory Consistency Models, 1991 International Conference on Parallel Processing, pp. 1 10.11Li et al., "Memory Coherence in Shared Virtual Memory Systems," 1986 ACM, pp. 229-239.12 *Li et al., Memory Coherence in Shared Virtual Memory Systems, 1986 ACM, pp. 229 239.13Saulsbury et al., "An Argument for Simple COMA," Swedish Institute of Computer Science, 10 pages.14 *Saulsbury et al., An Argument for Simple COMA, Swedish Institute of Computer Science, 10 pages.15 *Stenstr o m et al., An Adaptive Cache Coherence Protocal Optimized for Migratory Sharing, Proc. 20 th Annual Symposium on Computer Architecture, May 1993 IEEE, pp. 109 118.16Stenstrom et al., "An Adaptive Cache Coherence Protocal Optimized for Migratory Sharing," Proc. 20th Annual Symposium on Computer Architecture, May 1993 IEEE, pp. 109-118.17 *Wolf Dietrich Weber et al., Analysis of Cache Invalidation Patterns in Multiprocessors , Computer Systems Laboratory, Stanford University, CA, pp. 243 256.18Wolf-Dietrich Weber et al., "Analysis of Cache Invalidation Patterns in Multiprocessors", Computer Systems Laboratory, Stanford University, CA, pp. 243-256.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6249520 *Oct 24, 1997Jun 19, 2001Compaq Computer CorporationHigh-performance non-blocking switch with multiple channel ordering constraintsUS6343236 *Apr 2, 1999Jan 29, 2002General Electric CompanyMethod and system for analyzing fault log data for diagnosticsUS6401174 *Sep 4, 1998Jun 4, 2002Sun Microsystems, Inc.Multiprocessing computer system employing a cluster communication error reporting mechanismUS6405322 *Apr 13, 1999Jun 11, 2002Hewlett-Packard CompanySystem and method for recovery from address errorsUS6446185 *Jun 5, 2001Sep 3, 2002Sun Microsystems, Inc.Selective address translation in coherent memory replicationUS6487643Sep 29, 2000Nov 26, 2002Intel CorporationMethod and apparatus for preventing starvation in a multi-node architectureUS6536000Oct 15, 1999Mar 18, 2003Sun Microsystems, Inc.Communication error reporting mechanism in a multiprocessing computer systemUS6618823Aug 15, 2000Sep 9, 2003Storage Technology CorporationMethod and system for automatically gathering information from different types of devices connected in a network when a device failsUS6622264Nov 22, 1999Sep 16, 2003General Electric CompanyProcess and system for analyzing fault log data from a machine so as to identify faults predictive of machine failuresUS6658603Apr 17, 2000Dec 2, 2003International Business Machines CorporationMethod and apparatus for efficiently generating and implementing engine error codes and verifying the correctness of the implementation of the engine error codesUS6701464 *Mar 1, 2001Mar 2, 2004International Business Machines CorporationMethod and system for reporting error logs within a logical partition environmentUS6721918Dec 29, 2000Apr 13, 2004Intel CorporationMethod and apparatus for encoding a bus to minimize simultaneous switching outputs effectUS6772298Dec 20, 2000Aug 3, 2004Intel CorporationMethod and apparatus for invalidating a cache line without data return in a multi-node architectureUS6791412Dec 28, 2000Sep 14, 2004Intel CorporationDifferential amplifier output stageUS6810312Sep 30, 2002Oct 26, 2004General Electric CompanyMethod for identifying a loss of utilization of mobile assetsUS6826619Aug 21, 2000Nov 30, 2004Intel CorporationMethod and apparatus for preventing starvation in a multi-node architectureUS6947797Jul 24, 2002Sep 20, 2005General Electric CompanyMethod and system for diagnosing machine malfunctionsUS6971098Jun 27, 2001Nov 29, 2005Intel CorporationMethod and apparatus for managing transaction requests in a multi-node architectureUS6973643 *Aug 17, 2001Dec 6, 2005International Business Machines CorporationMethod, system and program for handling errors occurring in function callsUS6993675Jul 31, 2002Jan 31, 2006General Electric CompanyMethod and system for monitoring problem resolution of a machineUS7069479 *Nov 7, 2002Jun 27, 2006International Business Machines CorporationMethod and apparatus for obtaining diagnostic data for a device attached to a computer systemUS7085869 *Apr 4, 2001Aug 1, 2006Advanced Micro Devices, Inc.Arrangement for managing transmitted packets requiring acknowledgement in a host channel adapterUS7107411 *Dec 16, 2003Sep 12, 2006International Business Machines CorporationApparatus method and system for fault tolerant virtual memory managementUS7234029Dec 28, 2000Jun 19, 2007Intel CorporationMethod and apparatus for reducing memory latency in a cache coherent multi-node architectureUS7251755 *Feb 13, 2004Jul 31, 2007Intel CorporationApparatus and method for maintaining data integrity following parity error detectionUS7266726Nov 24, 2003Sep 4, 2007Time Warner Cable Inc.Methods and apparatus for event logging in an information networkUS7424653 *May 9, 2003Sep 9, 2008Hewlett-Packard Development Company, L.P.System and method for error capture and logging in computer systemsUS7483997 *Nov 13, 2001Jan 27, 2009Mitsubishi Electric CorporationData distribution control device and data distribution control methodUS7500141 *Nov 29, 2005Mar 3, 2009International Business Machines CorporationSaving state data in parallel in a multi-processor systemUS7506314Jul 7, 2003Mar 17, 2009International Business Machines CorporationMethod for automatically collecting trace detail and history dataUS7685573 *Aug 28, 2003Mar 23, 2010Sun Microsystems, Inc.Flexible error trace mechanismUS7698606Aug 31, 2007Apr 13, 2010Time Warner Cable Inc.Methods and apparatus for event logging in an information networkUS7805634 *Sep 16, 2006Sep 28, 2010International Business Machines CorporationError accumulation register, error accumulation method, and error accumulation systemUS7904760Jul 6, 2005Mar 8, 2011Cisco Technology, Inc.Method and system for using presence information in error notificationUS7913123Sep 12, 2008Mar 22, 2011International Business Machines CorporationConcurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffersUS7979750Jun 23, 2008Jul 12, 2011International Business Machines CorporationSynchronizing triggering of multiple hardware trace facilities using an existing system busUS7992051Sep 9, 2008Aug 2, 2011International Business Machines CorporationMethod, apparatus, and computer program product in a processor for dynamically during runtime allocating memory for in-memory hardware tracingUS7996625Apr 30, 2007Aug 9, 2011Intel CorporationMethod and apparatus for reducing memory latency in a cache coherent multi-node architectureUS8024607Aug 31, 2007Sep 20, 2011Time Warner Cable Inc.Methods and apparatus for event logging in an information networkUS8046636Mar 3, 2010Oct 25, 2011Time Warner Cable Inc.Methods and apparatus for event logging in an information networkUS8127181 *Nov 2, 2007Feb 28, 2012Nvidia CorporationHardware warning protocol for processing unitsUS8181161 *Oct 31, 2008May 15, 2012International Business Machines CorporationSystem for automatically collecting trace detail and history dataUS8250308Feb 15, 2008Aug 21, 2012International Business Machines CorporationCache coherency protocol with built in avoidance for conflicting responsesUS8799723Nov 26, 2012Aug 5, 2014Time Warner Cable Enterprises LlcMethods and apparatus for event logging in an information network* Cited by examinerClassifications U.S. Classification714/15, 714/49, 707/999.201International ClassificationG06F11/00, G06F11/22, G06F12/08, G06F11/34Cooperative ClassificationY10S707/99952, G06F11/2205European ClassificationG06F11/22ALegal EventsDateCodeEventDescriptionJun 16, 2010FPAYFee paymentYear of fee payment: 12Jun 23, 2006FPAYFee paymentYear of fee payment: 8Mar 14, 2002FPAYFee paymentYear of fee payment: 4Sep 18, 1996ASAssignmentOwner name: SUN MICROSYSTEMS, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HAGERSTEN, ERIK E.;CATENZARO, JOHN K.;NESHEIM, WILLIAM A.;AND OTHERS;REEL/FRAME:008171/0986Effective date: 19960912RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services