Source: http://www.google.com/patents/US7788391?ie=ISO-8859-1&dq=7,346,539
Timestamp: 2014-03-16 04:24:23
Document Index: 772401580

Matched Legal Cases: ['Application No. 2006', 'Application No. 2006', 'Application No. 2007502782', 'Application No. 200606011', 'Application No. 93119637', 'Application No. 200480042550', 'Application No. 04756431', 'Application No. 2007', 'Application No. 200606011', 'Application No. 200606011']

Patent US7788391 - Using a threshold value to control mid-interrupt polling - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsIn one embodiment, a method is provided. The method of this embodiment provides performing packet processing on a packet, and placing the packet in a placement queue; if no read buffer is available, determining if the size of the placement queue exceeds a threshold polling value; and if the size of the...http://www.google.com/patents/US7788391?utm_source=gb-gplus-sharePatent US7788391 - Using a threshold value to control mid-interrupt pollingAdvanced Patent SearchPublication numberUS7788391 B2Publication typeGrantApplication numberUS 10/973,790Publication dateAug 31, 2010Filing dateOct 25, 2004Priority dateMar 31, 2004Fee statusPaidAlso published asCN1926834A, CN1926834B, DE602004020273D1, EP1730919A1, EP1730919B1, US7525967, US7783769, US8121125, US8238360, US20050223128, US20050223133, US20050223134, US20050238019, US20060072564, US20130201998, WO2005104486A1Publication number10973790, 973790, US 7788391 B2, US 7788391B2, US-B2-7788391, US7788391 B2, US7788391B2InventorsSujoy Sen, Anil Vasudevan, Linden Cornett, Prafulla DeuskarOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (35), Non-Patent Citations (27), Referenced by (2), Classifications (18), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetUsing a threshold value to control mid-interrupt pollingUS 7788391 B2Abstract In one embodiment, a method is provided. The method of this embodiment provides performing packet processing on a packet, and placing the packet in a placement queue; if no read buffer is available, determining if the size of the placement queue exceeds a threshold polling value; and if the size of the placement queue exceeds the threshold polling value: if there are one or more pending DMM (data movement module) requests, polling a DMM to determine if the DMM has completed the one or more pending DMM requests for data associated with an application; and if the DMM has completed the one or more pending DMM requests, then sending a completion notification to the application to receive the data.
PRIORITY INFORMATION This application is a continuation-in-part of U.S. patent application Ser. No. 10/815,895 entitled �Accelerated TCP (Transport Control Protocol) Stack Processing�, filed Mar. 31, 2004, and claims the benefit of priority thereof.
FIELD Embodiments of this invention relate to using a threshold value to control mid-interrupt polling.
U.S. patent application Ser. No. 10/815,895 describes an accelerated protocol for processing TCP/IP packets. One of the components of this accelerated protocol is the ability to optimize the TCP flow by offloading the data copy from the host to a data movement module (hereinafter �DMM�), such as a DMA (direct memory access) engine. This data copy offload is furthermore overlapped with the protocol processing. However, as protocol processing is further optimized using faster processors, the data copy time may fall behind. As a consequence, the processor stays within the current interrupt utilizing valuable processing power. Furthermore, since the DMM is not polled for data copy completions until the driver completes protocol processing for the current interrupt, and since the application requesting the data won't post new buffers or repost the used buffers until data receives are completed, a significant latency may result from the data copy lag time.
FIG. 1 illustrates a network 100 in which embodiments of the invention may operate. Network 100 may comprise a plurality of nodes 102A, . . . 102N, where each of nodes 102A, . . . 102N may be communicatively coupled together via a communication medium 104. As used herein, components that are �communicatively coupled� means that the components may be capable of communicating with each other via wirelined (e.g., copper wires), or wireless (e.g., radio frequency) means. Nodes 102A . . . 102N may transmit and receive sets of one or more signals via medium 104 that may encode one or more packets.
Bus 206 may comprise a bus that complies with the Peripheral Component Interconnect (PCI) Local Bus Specification, Revision 2.2, Dec. 18, 1998 available from the PCI Special Interest Group, Portland, Oreg., U.S.A. (hereinafter referred to as a �PCI bus�). Alternatively, bus 106 instead may comprise a bus that complies with the PCI-X Specification Rev. 1.0a, Jul. 24, 2000, (hereinafter referred to as a �PCI-X bus�), or a bus that complies with the PCI-E Specification Rev. PCI-E (hereinafter referred to as a �PCI-E bus�), as specified in �The PCI Express Base Specification of the PCI Special Interest Group�, Revision 1.0a, both available from the aforesaid PCI Special Interest Group, Portland, Oreg., U.S.A. Also, alternatively, bus 106 may comprise other types and configurations of bus systems.
System 200 may additionally comprise I/O (input/output) subsystem 238 having a network component 212. �Network component� refers to any combination of hardware and/or software on an I/O (input/output) subsystem that may process one or more packets sent and/or received over a network. In one embodiment, I/O subsystem 238 may comprise, for example, a NIC (network interface card), and network component 212 may comprise, for example, a MAC (media access control) layer of the Data Link Layer as defined in the Open System Interconnection (OSI) model for networking protocols. The OSI model is defined by the International Organization for Standardization (ISO) located at 1 rue de Varemb�, Case postale 56 CH-1211 Geneva 20, Switzerland. I/O subsystem 238 may be comprised, for example, in a circuit card 250. Alternatively, it may be comprised on circuit board 218 as a component.
As used herein, a �DMM� refers to a module for moving data from a source to a destination without using the core processing module of a host processor, such as host processor 202. In one embodiment, DMM 210 may comprise a DMA engine. By using the DMM 210 for placement of data, host processor 202 may be freed from the overhead of performing data movements, which may otherwise result in the host processor 202 running at much slower memory speeds compared to the core processing module speeds.
At block 508, if the DMM has completed pending DMM requests, then TCP-A driver 222 may send a completion notification to the application to receive the data. As used herein, a �completion notification� refers to a notification that data is available from a read buffer, and �completing a receive� refers to data being read from the read buffer. Once application 218 has completed a receive, application 218 may post more buffers, and/or repost the buffers. For example, application 218 may read data from read buffer 214C so that it can repost read buffer 214C for further data. Furthermore, the packet on PQ 240 corresponding to the DMM completion may be removed from PQ 240, which may result in reducing the size of PQ 240.
Alternatively, in one embodiment, the interrupt may be a DMM interrupt. This interrupt refers to an interrupt that may indicate the completion of one or more pending DMM requests. A �pending DMM request� refers to a pending write of payload associated with a packet from a post buffer to a read buffer, where the payload has already been indicated to DMM for placement. Upon receipt of an interrupt, pending DMM requests may be from a previous interrupt, such as the interrupt immediately preceding the current interrupt. In one embodiment, pending DMM requests may be stored in SQ 246. SQ 246 may store pending DMM requests by storing pointers to the packets corresponding to the pending DMM requests. For example, if there are one or more packets 228 for which the associated payload 232 is to be copied from post buffer 214B to read buffer 214C, and the payload 232 has already been scheduled for DMM placement, then the pending DMM requests may be found in SQ 246. In one embodiment, if size of SQ 246 is greater than 0, then there are pending DMM requests. The method may continue to block 304.
At block 304, TCP-A driver 222 may determine if there are pending DMM requests. In one embodiment, this may be determined by checking SQ 246. In one embodiment, pending DMM requests for a particular context may be checked. Pending DMM requests for a particular context may be stored in SQC (scheduled queue-context) 244 such that if size of SQC 244 for the given context is >0, then there are pending DMM requests for the given context. SQC 244 may store pending DMM requests for a given context by storing pointers to the packets corresponding to the pending DMM requests for the given context. A �previous context� refers to a protocol context prior to the current interrupt received at block 302. As used herein, �protocol context�, hereinafter referred to as a �connection context� refers to information about a connection. For example, the information may comprise the sequence number of the last packet sent/received, and amount of memory available. A �connection� as used herein refers to a logical pathway to facilitate communications between a first node on a network and a second node on the network.
At block 314, DMM 210 may be polled for DMM completions of pending DMM requests. �DMM completions� refer to the completion of pending DMM requests. Since DMM polling is based on TPV 242, the rate of DMM polling may be controlled. In one embodiment, a completed pending DMM request means that DMM 210 has moved data associated with the pending DMM request from buffer 214B to buffer 214C. The method may continue to block 316.
In one embodiment, TCP-A driver 222 may program DMM 210 to transmit data if the data is small, and TCP-A driver 222 may queue a buffer, such as queued buffer 214E, if the data is large. As used herein, �queuing a buffer� means to notify a component that there is a buffer from which it can access data. For example, TCP acknowledgment packets to acknowledge receipt of packets may typically be relatively small-sized packets, and may be sent by TCP-A driver 222 to network component 212 by TCP-A driver 222 programming DMM 210 to transmit data 234. As another example, storage applications that send large files over the network may be relatively large, and may therefore be sent by TCP-A driver 222 to network component 212 by queuing buffer 214E.
CONCLUSION Therefore, in one embodiment, a method may comprise performing packet processing on a packet, and placing the packet in a placement queue; if no read buffer is available, determining if the size of the placement queue exceeds a threshold polling value; and if the size of the placement queue exceeds the threshold polling value: if there are one or more pending DMM (data movement module) requests, polling a DMM to determine if the DMM has completed the one or more pending DMM requests for data associated with an application; and if the DMM has completed the one or more pending DMM requests, then sending a completion notification to the application to receive the data.
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No. 11/027,719, mailed on Jun. 13, 2008, pp. 15.27Written Opinion of the International Searching Authority, mailed Oct. 12, 2006.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8121125Dec 30, 2004Feb 21, 2012Intel CorporationAccelerated TCP (transport control protocol) stack processingUS8238360May 26, 2005Aug 7, 2012Intel CorporationHeader replication in accelerated TCP (transport control protocol) stack processingClassifications U.S. Classification709/230, 370/351International ClassificationG06F15/173, G06F13/28, H01L29/40, G06F15/16, H04L29/06, H04L12/56Cooperative ClassificationH04L49/9042, H04L49/90, H04L69/163, H04L69/161, H04L69/16European ClassificationH04L29/06J7, H04L29/06J3, H04L49/90K, H04L49/90, H04L29/06JLegal EventsDateCodeEventDescriptionDec 17, 2013FPAYFee paymentYear of fee payment: 4Oct 25, 2004ASAssignmentOwner name: INTEL CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SEN, SUJOY;VASUDEVAN, ANIL;CORNETT, LINDEN;AND OTHERS;REEL/FRAME:015936/0351Effective date: 20041019RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google