Source: https://patents.google.com/patent/JP2006278906A/en
Timestamp: 2020-01-27 23:21:43
Document Index: 429925483

Matched Legal Cases: ['art 300', 'art 300', 'art 300', 'art 300', 'art 300', 'art 701']

JP2006278906A - Semiconductor device and its manufacturing method - Google Patents
JP2006278906A
JP2006278906A JP2005098591A JP2005098591A JP2006278906A JP 2006278906 A JP2006278906 A JP 2006278906A JP 2005098591 A JP2005098591 A JP 2005098591A JP 2005098591 A JP2005098591 A JP 2005098591A JP 2006278906 A JP2006278906 A JP 2006278906A
JP2005098591A
良実 江川
2005-03-30 Application filed by Oki Electric Ind Co Ltd, 沖電気工業株式会社 filed Critical Oki Electric Ind Co Ltd
2005-03-30 Priority to JP2005098591A priority Critical patent/JP2006278906A/en
2006-10-12 Publication of JP2006278906A publication Critical patent/JP2006278906A/en
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which poor connection between a wiring board and a semiconductor chip can be reduced during heat treatment, and poor connection between the wiring board and the mounting substrate can be reduced during packaging accompanying heat treatment. <P>SOLUTION: The semiconductor device comprises a semiconductor substrate having a first surface, a second surface which is the rear surface of the first surface, and a first through electrode penetrating the first and second surfaces, a semiconductor chip composed of the same kind of a material as that of the semiconductor substrate and mounted on the first surface of the semiconductor substrate while being connected electrically with the first through electrode, a flexible stress relax portion formed on the second surface of the semiconductor substrate while being connected electrically with the first through electrode, and an external connection terminal connected with a first conductor on the stress relax portion. <P>COPYRIGHT: (C)2007,JPO&INPIT
The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a three-dimensional mounting type semiconductor device and a manufacturing method thereof.
Conventionally, in order to satisfy the demand for downsizing of a semiconductor device, a multi-chip package (Multi Chip Package) in which a plurality of semiconductor chips are mounted in a single package to increase the mounting density of the semiconductor device is used. One of them is a three-dimensional mounting structure in which a plurality of semiconductor chips are stacked in a vertical direction on a wiring board (interposer), and signal transmission is performed via through electrodes provided in the wiring board and each semiconductor chip. Compared with a planar mounting structure in which a plurality of semiconductor chips are planarly mounted on a wiring board, the three-dimensional mounting structure having a through electrode has a wiring length between the wiring board on which the chip is mounted and the semiconductor chip, In addition, since the wiring length between the semiconductor chips can be shortened, signal transmission between the functional elements formed on each semiconductor chip can be performed at high speed. In addition, since it can be connected to the mounting board via an external connection terminal provided on the lower surface of the wiring board, the wiring length for external connection is short, and signal transmission with the outside can be performed at high speed.
As this type of technology, for example, as in Patent Document 1, a three-dimensional mounting type structure using a semiconductor material for a wiring board is known. The wiring substrate 1 made of a semiconductor material has wirings (L11, L12, L13, L123) formed by a semiconductor process such as photolithography etching on the semiconductor chip mounting surface 1a. As a result, the wiring width and wiring pitch can be reduced as compared with the wiring of a wiring substrate (hereinafter referred to as an insulating substrate) that cannot use a semiconductor process. Further, by configuring the wiring board 1 and the semiconductor chip 2 with the same kind of semiconductor material, it is possible to reduce connection failures between the wiring board 1 and the semiconductor chip 2 caused by the difference in linear expansion coefficient during the heat treatment. it can.
JP 2003-110084 A
However, since a substrate on which a semiconductor device is mounted (hereinafter referred to as a mounting substrate) is generally not a semiconductor material, when a semiconductor material is used as a wiring substrate as in the technique disclosed in Patent Document 1, a semiconductor material is used. The linear expansion coefficients of the wiring board 1 (hereinafter referred to as a semiconductor substrate) configured as described above and the mounting board 10 are different. Since the linear expansion coefficients are different, there is a possibility of causing a connection failure after mounting, such as a crack occurring in the external connection terminal 8 connected to the mounting substrate 10 during the heat treatment performed when the semiconductor device is mounted on the mounting substrate 10. there were.
In order to solve the above-described problem, one of the representative inventions of the present application includes a first surface and a second surface that is the back surface of the first surface. A semiconductor substrate having a first through electrode penetrating through the second surface, and mounted on the first surface of the semiconductor substrate, made of the same material as the semiconductor substrate, and electrically connected to the first through electrode. A semiconductor chip having a circuit element connected to the semiconductor substrate and a second surface of the semiconductor substrate, electrically connected to the first through electrode of the semiconductor substrate, and having flexibility. A semiconductor device comprising: a stress relaxation portion including one conductor; and an external connection terminal connected to the first conductor on the stress relaxation portion.
According to the representative invention of the present application, it is possible to reduce the connection failure between the wiring substrate and the semiconductor chip that occurs during the heat treatment, and the wiring substrate and the mounting substrate that are generated when the mounting accompanied by the heat treatment is performed. It is possible to provide a semiconductor device that can reduce connection failures between the two.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is provided to the same structure through all the drawings.
FIG. 1 is a plan view showing the structure of the semiconductor device 001 according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line 2-2 ′ of FIG. Note that FIG. 1 is a plan view in which the semiconductor chip 501 and the first conductive film 201 are seen through in order to facilitate understanding of the structure of the semiconductor device 001 in the first embodiment.
As shown in FIGS. 1 and 2, the semiconductor device 001 according to the first embodiment of the present invention includes a semiconductor substrate 101, a stress relaxation unit 300 formed on the second surface 112 of the semiconductor substrate 101, a stress The external connection terminal 303 formed on the relaxing part 300, the semiconductor chip 501a and the semiconductor chip 501b stacked on the first surface 111 of the semiconductor substrate 101, and the first surface 111 and the semiconductor chip 501a of the semiconductor substrate 101. And a sealing body 602 that covers the semiconductor chip 501b. Further, the semiconductor substrate 101 has a first through electrode 102.
In addition, the stress relaxation unit 300 includes a first conductor 301 having flexibility, and the first conductor 301 is connected to the first through electrode 102 via the second conductive film 202. Connected. Here, the flexibility means that stress generated between the semiconductor substrate 101 and the mounting substrate 401 having different linear expansion coefficients during mounting accompanied by heat treatment is relaxed, and a connection failure occurs in the external connection terminal 303. It shows the extent of not letting it. The external connection terminal 303 is connected to the first conductor 301. Further, the semiconductor chip 501a has a second through electrode 502a and a circuit element 503a (not shown), and the second through electrode 502a is interposed between the first conductive film 201 and the connection bump 504a. Are connected to the first through electrode 102. Further, the semiconductor chip 501b has a second through electrode 502a and a circuit element 503b (not shown). The second through electrode 502b is connected to the second through electrode via the connection bump 504b and the connection bump 504c. The electrode 502a is connected. A sealing layer 601 is formed between the semiconductor substrate 101 and the semiconductor chip 501a and between the semiconductor chip 501a and the semiconductor chip 501b.
Next, the structure of the stress relaxation part 300 in this embodiment is demonstrated.
As shown in FIG. 2, the stress relaxation unit 300 faces the second surface 112 and is connected to the third surface 311 connected to the second conductive film 202 and the fourth surface connected to the external connection terminal 303. The first conductor 301 is provided with a surface 312 and a side surface 313 connecting the third surface 311 and the fourth surface 312. The shape of the first conductor 301 is preferably a cylindrical shape, for example. The first conductor 301 is made of, for example, copper. Furthermore, the stress relieving portion 300 is formed so as to cover the side surface 313 of the first conductor 301 and has a first insulator 302 having elasticity. The first insulator 302 is made of a resin such as an epoxy resin, for example.
In the present embodiment, since the stress relaxation part 300 is formed, stress due to a difference in thermal expansion or thermal contraction occurs between the semiconductor substrate 101 and the mounting substrate 401 having different linear expansion coefficients during mounting with heat treatment. Even if the first conductor 301 is inclined in the direction of the second surface 112, the external connection terminal 303 can be displaced in the direction of the second surface 112. As a result, it is possible to relieve the stress generated during mounting accompanied by heat treatment, and it is possible to prevent a connection failure due to a crack or the like of the external connection terminal 303 that occurs during mounting. In addition, since the first insulator 302 is formed so as to cover the side surface 313 of the first conductor 301, the inclination angle of the first conductor 301 can be controlled, and the generated stress depends on the generated stress. Connection failure such as disconnection of the conductor 301 can be prevented. Further, since the generated stress is relieved when the first conductor 301 is inclined, the distance between the third surface 311 and the fourth surface 312 of the first conductor 301, that is, the height of the conductor 301 is increased. The thickness is desirably in the range of 50 μm to 200 μm. By setting the height of the first conductor 301 to the above condition, the stress can be relaxed and the semiconductor device 001 can be thinned.
Next, configurations other than the stress relaxation unit 300 will be described.
First, the semiconductor substrate 101 is made of the same semiconductor material (for example, silicon) as the semiconductor chip 501a and the semiconductor chip 501b to be mounted. Thereby, since the linear expansion coefficients of the semiconductor substrate 101, the semiconductor chip 501a, and the semiconductor chip 501b can be matched, the stress generated from the difference between thermal expansion and thermal contraction can be reduced. Since the main material of the semiconductor substrate 101, the semiconductor chip 501a, and the semiconductor chip 501b may be the same type, for example, a silicon substrate on which a thin film of a material different from silicon or an SOI (Silicon on Insulator) is the same type. It becomes a semiconductor material.
The semiconductor substrate 101 includes a first through electrode 102 that penetrates the first surface 111 and the second surface 112 on which the semiconductor chip 501a is mounted. The first through electrode 102 is electrically connected to the mounted semiconductor chip 501 a, semiconductor chip 501 b, first conductor 301, and external connection terminal 303. The first through electrode 102 is made of a conductor, for example, copper, aluminum, polysilicon, or the like. The first through electrode 102 is formed by a semiconductor process. For example, after a mask is formed by photolithography etching and a groove is formed by dry etching, the groove is filled with a conductor by an electroplating method, and the back surface is chemically formed. It is formed by performing mechanical mechanical polishing. As a result, the diameter of the first through electrode 102 can be reduced to about 10 to 20 μm, and it is possible to cope with the increase in the number of pins and the function of the semiconductor device 001.
The first surface 111 includes a first portion connected to the second through electrode 502a of the semiconductor chip 501a and a second portion connected to the first through electrode 102 of the semiconductor substrate 101. A conductive film 201 is formed. The first conductive film 201 is made of a conductor such as copper or aluminum, for example. The first conductive film 201 is referred to as rewiring, and as shown in FIG. 1, the first conductive film 201 is extended across the first through electrode 102 and the connection bump 504a, whereby the semiconductor chip 501a. It is possible to set the connection bump 504a, which is a joint portion of the second through electrode 502a, at a predetermined position. The first conductive film 201 is formed by a semiconductor process. For example, the first conductive film 201 is formed by forming a conductive film on the entire first surface 111 of the semiconductor substrate 101 by sputtering and patterning it by photolithography etching. Thereby, the wiring width of the semiconductor substrate 101 can be reduced to about 5 μm, and it is possible to cope with the increase in the number of pins and the function of the semiconductor device 001.
A second conductive film 202 including a third portion connected to the first through electrode 102 and a fourth portion connected to the first conductor 301 is formed on the second surface 112. . By extending the second conductive film 202 across the first through electrode 102 and the first conductor 301, the first conductor 301 can be set at a predetermined position. Note that the second conductive film 202 has a structure similar to that of the first conductive film 201.
An external connection terminal 303 is connected to the fourth surface 312 of the first conductor 301. The external connection terminal 303 is connected to the mounting substrate 401 at the time of mounting. The external connection terminal 303 is made of a conductor such as solder, lead-free solder, or lead tin. In FIG. 2, the external connection terminal 303 is spherical. However, for example, a plating layer may be formed on the fourth surface 312 of the first conductor 301 and the plating layer may be used as the external connection terminal 303.
In the semiconductor chip 501a mounted on the semiconductor substrate 101, a second through electrode 502a penetrating the fifth surface 511a having the circuit element 503a and the sixth surface 512a is formed. The second through electrode 502a is connected to the circuit element 503a through a wiring formed on the fifth surface 511a. The second through electrode 502a is made of a conductor, for example, copper, aluminum, polysilicon, or the like. Further, the second through electrode 502a only needs to be formed so that at least a part of the end of the second through electrode 502a is exposed at the fifth surface 511a and the sixth surface 512a. The sectional shape of the two through electrodes 502a is not particularly specified. The second through electrode 502a is formed by a semiconductor process. Accordingly, the second through electrode 502a can be manufactured without significantly increasing the manufacturing cost because the circuit element 503a can be formed in the same process as the manufacturing process.
Connection bumps 504a and connection bumps 504b are formed on both ends of the second through electrode 502a of the semiconductor chip 501a, respectively. The connection bump 504a and the connection bump 504b are made of a conductor such as solder or lead-free solder, copper, or gold, for example.
Next, in the semiconductor chip 501b mounted on the semiconductor chip 501a, the second through electrode 502b penetrating the fifth surface 511b and the sixth surface 512b having the circuit element 503b is formed. Note that the semiconductor chip 501b and the second through electrode 502b have the same configuration as the semiconductor chip 501a and the second through electrode 502a.
On the fifth surface 511b of the semiconductor chip 501b, connection bumps 504c connected to the second through electrodes 502b and the connection bumps 504b of the semiconductor chip 501a are formed. Note that the connection bump 504c has the same configuration as the connection bump 504a and the connection bump 504b.
As described above, signal transmission between the semiconductor substrate 101, the semiconductor chip 501a, and the semiconductor chip 501b is performed via the second through electrode 502a and the second through electrode 502b, so that the semiconductor substrate 101, the semiconductor chip 501a, and the semiconductor are performed. Compared with a semiconductor device in which the chip 501b is connected via a wire, the wiring length between the semiconductor substrate 101 and the semiconductor chip 501a and between the semiconductor chip 501a and the semiconductor chip 501b can be shortened. For this reason, signal transmission of the circuit element 503a and the circuit element 503b can be performed at high speed, and the mounting density can be improved. In addition, since the semiconductor substrate 101, the semiconductor chip 501a, and the semiconductor chip 501b are connected through the second through electrode 502a and the second through electrode 502b, the surface on which the circuit elements 503a and 503b are formed is particularly designated. Not. For example, the circuit element 503a may be formed on the fifth surface 511a of the semiconductor chip 501a, and the circuit element 503b may be formed on the sixth surface 512b of the semiconductor chip 501b.
Between the semiconductor substrate 101 and the semiconductor chip 501a and between the semiconductor chip 501a and the semiconductor chip 501b, side portions of the first conductive film 201, the connection bump 504a, the connection bump 504b, and the connection bump 504c of the semiconductor substrate 101, A sealing layer 601 is formed so as to cover the second through electrode 502a, the second through electrode 502b, the circuit element 503a, and the circuit element 503b. The sealing layer 601 is made of an insulator, and is made of, for example, a solid resin such as epoxy, a liquid resin, or the like. Accordingly, the possibility that the first conductive film 201, the circuit element 503a, the circuit element 503b, the connection bump 504a, the connection bump 504b, and the connection bump 504c come into contact with each other at a place other than the predetermined portion and the short circuit is reduced. it can. In addition, the possibility that the first conductive film 201, the circuit element 503a, the circuit element 503b, the connection bump 504a, the connection bump 504b, and the connection bump 504c are partially disconnected can be reduced. Further, the sealing layer 601 includes a space between the semiconductor substrate 101 and the semiconductor chip 501a provided by forming the connection bump 504a, and a semiconductor chip provided by forming the connection bump 504b and the connection bump 504c. It is desirable to fill the space between 501a and the semiconductor chip 501b. Thereby, the reflow tolerance of the semiconductor device 001 can be improved.
A sealing body 602 includes at least the semiconductor chip 501a, the semiconductor chip 501b, the first surface 111, and the first conductive film 201 around the first surface 111 of the semiconductor substrate and the semiconductor chip 501a and the semiconductor chip 501b. It is formed to cover. The sealing body 602 is an insulator and is made of, for example, a resin such as an epoxy resin. Thereby, the possibility that the first conductive film 201 contacts and short-circuits at a place other than the predetermined part can be reduced. In addition, the possibility that a part of the first conductive film 201 is disconnected can be reduced. Further, the sealing body 602 is capable of sealing leakage in the space between the semiconductor chip 501a and the semiconductor substrate 101 sealed by the sealing layer 601 and the space between the semiconductor chip 501a and the semiconductor chip 501b. Therefore, the reflow resistance of the semiconductor device 001 can also be improved. In addition, it is desirable to mix glass particles into the sealing body 602. When glass particles are mixed, the cut surface becomes rough when the wafer is singulated, but the reflow resistance can be improved and the warp of the semiconductor device 001 can be reduced. That is, the ease of singulation processing is in a trade-off relationship with improvement in reflow resistance and reduction in warpage of the semiconductor device 001. Thereby, by mixing glass particles, it becomes possible to set three of reflow resistance, warpage, and easiness of singulation processing to predetermined conditions. Furthermore, it is desirable that the sealing body 602 includes ceramic. Thereby, the heat dissipation of the semiconductor device 001 can be improved.
Next, a modification of the first embodiment of the present invention will be described. FIG. 3 is a plan view showing a modified example of the structure of the semiconductor device 001 in the first embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line 4-4 ′ of FIG. Note that FIG. 3 is a plan view through which the semiconductor chip 501 and the first conductive film 201 are seen in order to facilitate understanding of the configuration of the semiconductor device 001 in the modification of the first embodiment.
In the modification of the present embodiment, the stress relaxation part 300 is formed so as to expose at least a part of the surface of the first through electrode 102 on the second surface 112 of the semiconductor substrate 101 as shown in FIG. A first insulator 321 having elasticity, a fifth portion formed on the second surface 112 and connected to the first through electrode 102, an external connection terminal 303, and the first insulator 321. And a first conductor 322 having flexibility.
Since the stress relaxation unit 300 has the above-described configuration, even if thermal expansion or thermal contraction stress is generated between the semiconductor substrate 101 and the mounting substrate 401 having different linear expansion coefficients, the first insulator 321 is By the deformation, the first conductor 322 can be deformed, and the position of the external connection terminal 303 can be displaced in the direction of the second surface 112. As a result, it is possible to relieve the stress generated during mounting with heat treatment, and it is possible to prevent connection failures due to cracks or the like of the external connection terminals 303 that occur during mounting. The first insulator 321 is made of an elastic material, such as an epoxy resin, and the shape of the first insulator 321 is preferably, for example, a protrusion as shown in FIG. Further, the first conductor 322 is made of, for example, copper.
In addition, about structures other than the stress relaxation part 300, it shall have the structure similar to 1st Embodiment.
A method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described as a second embodiment of the present invention. For ease of explanation, the processes until the second through electrode 502a, the second through electrode 502b, the connection bump 504a, the connection bump 504b, and the connection bump 504c are formed on the semiconductor chip 501a and the semiconductor chip 501b (semiconductor A manufacturing process of the semiconductor chip 501a and the semiconductor chip 501b performed before being mounted on the substrate 101) is referred to as a first process, and the subsequent processes are referred to as a second process and will be described. The first step is shown in FIG. 5, and the second step is shown in FIGS.
First, the first step of the second embodiment will be described. Hereinafter, only the process of forming the second through electrode 502a, the connection bump 504a, and the connection bump 504b on the semiconductor chip 501a will be described, and the second through electrode 502b and the connection bump are formed on the semiconductor chip 501b, which is a similar process. The step of forming 504c is omitted.
First, as shown in FIG. 5A, a wafer 500 having a plurality of partitioned circuit element regions is prepared.
Next, a groove 701 is formed in the fifth surface 511 a having the circuit element 503 a of the wafer 500. For example, the groove 701 is formed by dry etching after a mask is formed by photolithography etching. The depth of the groove 701 is, for example, 100 μm or more with respect to the wafer thickness of 760 μm. Moreover, the diameter of the groove part 701 is 10-20 micrometers, for example.
Next, as illustrated in FIG. 5B, the side surface and the bottom surface of the groove portion 701 are covered with an insulating film 702. The insulating film 702 is made of an insulator such as silicon oxide, for example. The insulating film 702 is formed by a chemical vapor deposition (CVD) method or the like.
Further, it is preferable that the groove 701 covered with the insulating film 702 be covered with the third conductive film 703. The third conductive film 703 is made of a conductor such as copper. The third conductive film 703 is formed by CVD or the like and serves as a base for the second conductor 704 formed by an electrolytic plating method.
Next, a second conductor 704 is formed so as to fill the groove 701 covered with the insulating film 702 and the third conductive film 703. The second conductor 704 is made of a conductor such as copper, aluminum, or polysilicon, for example. The second conductor 704 is formed by filling a groove 701 with a conductor by electrolytic plating after forming a mask at a position excluding the groove 701 by photolithography etching. As another forming method, the second conductor 704 is deposited on the fifth surface 511a on which the groove 701 is formed by electroplating until the groove 701 is filled, and then mechanical polishing or chemical mechanical processing is performed. There is also a method in which the fifth surface 511a is polished until the second conductor 704 formed on the portion other than the groove 701 can be removed by chemical polishing (CMP) or the like.
Next, a wiring for electrically connecting the second conductor 704 in the groove 701 and the circuit element 503a is formed on the fifth surface 511a (not shown). For example, a conductive film such as copper or aluminum is formed on the fifth surface 511a of the wafer 500 by CVD or the like, and is patterned by photolithography etching to connect the second conductor 704 in the groove 701 and the circuit element 503a. Wiring can be formed. Further, it is preferable that an electrode pad is formed in advance in the process of forming the circuit element 503a, and the groove 701, the insulating film 702, the conductive film 703, and the second conductor 704 are formed in the electrode pad portion. Accordingly, after forming the second conductor 704, a step of forming a wiring electrically connected to the circuit element 503a can be omitted.
Next, connection bumps 504a connected to the second conductor 704 of the groove 701 are formed on the fifth surface 511a. The connection bump 504a is formed by forming a mask at a position excluding the second conductor 704 by photolithography etching, forming a conductor on the upper surface of the second conductor 704 by sputtering, plating, etc., and then removing the mask. Is done.
Next, as shown in FIG. 5C, the connection bumps 504a formed on the fifth surface 511a are attached to the support base 402, and the sixth surface 512a is at least exposed until the second conductor 704 is exposed. Grind. This polishing is performed by, for example, mechanical polishing or chemical mechanical polishing. By exposing the second conductor 704 in the groove 701, the second through electrode 502a can be formed. Since the formation process of the second through electrode 502a can be formed by a semiconductor process similarly to the formation process of the circuit element 503a, the second through electrode 502a can be manufactured without significantly increasing the manufacturing cost. Further, it is desirable to polish the wafer 500 that becomes the semiconductor chip 501a so as to have a thickness of 20 to 100 μm. By polishing under the above conditions, the semiconductor chip 501a can be prevented from cracking, and the semiconductor chip 501a can be thinned, so that the mounting density of the semiconductor device 001 can be increased.
Next, as shown in FIG. 5D, connection bumps 504b connected to the second through electrodes 502a are formed on the sixth surface 512a. Note that the manufacturing method of the connection bump 504b is the same as that of the connection bump 504a.
Finally, as shown in FIG. 5E, the wafer 500 on which a plurality of circuit element regions are formed is divided into individual pieces for each circuit element region by, for example, a mechanical process, thereby connecting bumps 504a. Then, a semiconductor chip 501a connected to the connection bump 504b is formed.
In the first step, the connection bump 504a is formed on the fifth surface 511a, the sixth surface 512a is polished, and the connection bump 504a is formed on the sixth surface 512a. After the surface 512a is polished, connection bumps 504a and 504b may be formed on the fifth surface 511a and the sixth surface 512a, respectively. In addition, since the semiconductor chip 501a is connected to the semiconductor chip 501b and the semiconductor substrate 101 via the second through electrode 502a, the circuit element 503a is on either the fifth surface 511a or the sixth surface 512a. It may be formed.
Next, the second step of the second embodiment will be described.
First, as shown in FIG. 6A, a wafer 100 having a plurality of chip regions on which semiconductor chips 501a and 501b are mounted is prepared.
Next, the first through electrode 102 is formed on the wafer 100. Note that the manufacturing method of the first through electrode 102 of the wafer 100 is the same as the manufacturing method of the second through electrode 502a of the wafer 500 of the present embodiment. Furthermore, it is desirable to polish the wafer 100 to be the semiconductor substrate 101 so that the thickness of the wafer 100 becomes 200 to 500 μm by dividing into pieces. By polishing under the above conditions, the semiconductor substrate 101 can be prevented from being bent when the semiconductor chip 501a and the semiconductor chip 501b are stacked, and the semiconductor substrate 101 can be thinned to reduce the mounting density of the semiconductor device 001. It becomes possible to raise.
Next, a first conductive film 201 is formed on the first surface 111 of the wafer 100. A first conductive film 201 is formed on the first surface 111 of the wafer 100 by forming a conductive film on the first surface 111 of the wafer 100 by sputtering and patterning by photolithography.
Next, after the wafer 100 is turned over, a second conductive film 202 is formed on the second surface 112 of the wafer 100. A second conductive film 202 is formed on the second surface 112 of the wafer 100 by forming a conductive film on the second surface 112 of the wafer 100 by sputtering and patterning by photolithography etching.
Next, as shown in FIG. 6B, a first conductor 301 connected to the second conductive film 202 is formed on the second surface 112 of the wafer 100. The first conductor 301 is formed by patterning the mask by photolithography, then depositing a conductor at a predetermined position by electrolytic plating, and then removing the mask.
Next, a first insulator 302, for example, a resin is formed on the second surface 112 of the wafer 100 on which the second conductive film 202 and the first conductor 301 are formed. At this time, the first insulator 302 is formed so as to cover the second surface 112 of the wafer 100, the second conductive film 202, and the first conductor 301.
Next, as illustrated in FIG. 6C, the first insulator 302 is polished so that the fourth surface 312 of the first conductor 301 is exposed. Polishing is performed by, for example, mechanical polishing or chemical mechanical polishing. By forming the first conductor 301 and the first insulator 302 as described above, the stress relieving portion 300 including the first conductor 301 and the first insulator 302 is manufactured. Further, it is desirable to polish so that the distance between the second surface 112 of the wafer 100 and the fourth surface 312 of the first conductor 301 is 50 to 200 μm. By polishing under the above conditions, connection failure after mounting can be reduced, the stress relaxation portion 300 can be thinned, and the mounting density of the semiconductor device 001 can be increased.
Next, after turning the wafer 100 upside down, as shown in FIG. 6D, semiconductor chips 501 a are mounted on the first surface 111 of the wafer 100 for each of a plurality of chip regions of the wafer 100. At this time, the first conductive film 201 and the connection bump 504a are formed to be connected. Further, the semiconductor chip 501b is mounted on the sixth surface 512a of the semiconductor chip 501a. At this time, the connection bump 504b of the semiconductor chip 501a and the connection bump 504c of the semiconductor chip 501b are formed to be connected.
Next, the sealing layer 601 is injected between the wafer 100 and the semiconductor chip 501a and between the semiconductor chip 501a and the semiconductor chip 501b from the sides of the wafer 100, the semiconductor chip 501a, and the semiconductor chip 501b. The sealing layer 601 at this time is made of, for example, a liquid resin. Alternatively, after the semiconductor chip 501a and the semiconductor chip 501b are mounted, the sealing layer 601 may be injected at once, or the semiconductor chip 501a and the semiconductor chip 501b may be stacked while the sealing layer 601 is injected as needed. You may connect.
In addition, the sealing layer 601 can be formed by the following method. First, the sealing layer 601 is applied in advance to one or both surfaces of the semiconductor chip 501a and the semiconductor chip 501b. At this time, at least the circuit element 503a (not shown), the circuit element 503b (not shown), the connection bump 504a, the connection bump 504b, and the side of the connection bump 504c may be covered. Thereafter, the semiconductor chip 501a and the semiconductor chip 501b are stacked, and heat treatment is performed to form the sealing layer 601. The sealing layer 601 at this time is made of, for example, a solid resin.
Next, as shown in FIG. 7A, a sealing body 602 is formed so as to cover the first surface 111 of the wafer 100, the first conductive film 201, the semiconductor chip 501a, and the semiconductor chip 501b.
Next, as shown in FIG. 7B, the upper surface of the sealing body 602 is polished. This polishing is performed by, for example, mechanical polishing or chemical mechanical polishing. Further, it is desirable to polish so that the distance between the sixth surface 512b of the semiconductor chip 501b and the upper surface of the sealing body 602 is 100 μm or less. Thereby, the mounting density of the semiconductor device 001 can be increased. Note that the sealing body 602 may be formed in advance so that the distance between the sixth surface 512b of the semiconductor chip 501b and the upper surface of the sealing body 602 is 100 μm or less. As a result, the step of polishing the sealing body 602 can be omitted.
Next, as shown in FIG. 7C, an external connection terminal 303 connected to the fourth surface 312 of the first conductor 301 is formed.
Finally, as shown in FIG. 7D, a semiconductor in which a semiconductor chip 501a and a semiconductor chip 501b are stacked on a semiconductor substrate 101 by separating the wafer 100 into individual chip regions by, for example, a mechanical process. Device 001 is obtained. In the above steps, the first insulator 302 formed on the second surface 112 is polished until the first conductor 301 is exposed before mounting the semiconductor chip 501a and the semiconductor chip 501b. The semiconductor chip 501a and the semiconductor chip 501b may be mounted and the sealing may be performed after the sealing body 602 is formed on the first surface 111.
Next, a manufacturing method corresponding to a modification of the first embodiment of the present invention will be described as a modification of the second embodiment. Steps until the second through electrode 502a, the second through electrode 502b, the connection bump 504a, the connection bump 504b, and the connection bump 504c are formed on the semiconductor chip 501a and the semiconductor chip 501b (mounted on the semiconductor substrate 101). The first step, which is the manufacturing step of the semiconductor chip 501a and the semiconductor chip 501b performed before, is omitted because it is the same as that of the second embodiment, and only the second step, which is a subsequent step, will be described. The second step is shown in FIGS.
First, as shown in FIG. 8A, a wafer 100 having a plurality of chip regions on which semiconductor chips 501a and 501b are mounted is prepared.
Next, the first through electrode 102 is formed on the wafer 100. The manufacturing method of the first through electrode 102 is the same as that of the second embodiment of the present invention.
Next, after the wafer 100 is turned over, a first conductive film 201 is formed on the first surface 111 of the wafer 100. Note that the manufacturing method of the first conductive film 201 is the same as that of the second embodiment of the present invention.
Next, as illustrated in FIG. 8B, a first insulator 321, for example, a resin is formed on the second surface 112 of the wafer 100. At this time, the first through electrode 102 is formed so as to be exposed.
Next, a first conductor 322 is formed on the second surface 112 so as to be connected to the first through electrode 102 and to cover at least the upper surface of the first insulator 321.
Next, a second insulator 323, for example, a resin is formed over the second surface 112 and the first insulator 321. At this time, the second insulator 323 is formed so as to cover the second surface 112 of the wafer 100 and the first conductor 322.
Next, as shown in FIG. 8C, the second insulator 323 is polished so that the upper portion of the first conductor 322 is exposed. This polishing is performed by, for example, mechanical polishing or chemical mechanical polishing.
Next, after turning the wafer 100 upside down, as shown in FIG. 8D, the semiconductor chip 501 a and the semiconductor chip 501 b are sequentially mounted on the first surface 111 of the wafer 100 for each of a plurality of chip regions of the wafer 100. The first through electrode 102, the second through electrode 502a, and the second through electrode 502b are connected through the connection bump 504a, the connection bump 504b, and the connection bump 504c, respectively. The mounting method and connection method of the semiconductor chip 501a and the semiconductor chip 501b are the same as those in the second embodiment of the present invention.
Next, the sealing layer 601 is injected between the wafer 100 and the semiconductor chip 501a and between the semiconductor chip 501a and the semiconductor chip 501b from the sides of the wafer 100, the semiconductor chip 501a, and the semiconductor chip 501b. The manufacturing method of the sealing layer 601 is the same method as that of the second embodiment of the present invention.
Next, as shown in FIG. 9A, a sealing body 602 is formed so as to cover the first surface 111 of the wafer 100, the first conductive film 201, the semiconductor chip 501a, and the semiconductor chip 501b. The manufacturing method of the sealing body 602 is the same method as that of the second embodiment of the present invention.
Next, as shown in FIG. 9B, the upper surface of the sealing body 602 is polished. Note that the polishing method of the sealing body 602 is the same method as in the second embodiment of the present invention.
Next, as shown in FIG. 9C, external connection terminals 303 connected to the first conductor 322 exposed from the second insulator 323 are formed.
Finally, as shown in FIG. 9D, the semiconductor device 001 in which the semiconductor chip 501a and the semiconductor chip 501b are stacked on the semiconductor substrate 101 is obtained by dividing the wafer 100 into individual chip regions. Note that the method of dividing the wafer 100 into individual pieces is the same as in the second embodiment of the present invention.
It is a top view explaining the structure of the semiconductor device of 1st Embodiment. It is sectional drawing explaining the structure of the semiconductor device of 1st Embodiment. It is a top view explaining the structure of the semiconductor device which is a modification of 1st Embodiment. It is sectional drawing explaining the structure of the semiconductor device which is a modification of 1st Embodiment. It is process drawing explaining the 1st process in the manufacturing method of the semiconductor device of 2nd Embodiment. It is process drawing explaining the 2nd process in the manufacturing method of the semiconductor device of 2nd Embodiment. It is process drawing explaining the 2nd process in the manufacturing method of the semiconductor device of 2nd Embodiment. It is process drawing explaining the 2nd process in the manufacturing method of the semiconductor device which is a modification of 2nd Embodiment. It is process drawing explaining the 2nd process in the manufacturing method of the semiconductor device which is a modification of 2nd Embodiment.
001 Semiconductor device 100, 500 Wafer 101 Semiconductor substrate 102 First through electrode 201 First conductive film 202 Second conductive film 111 First surface 112 Second surface 300 Stress relaxation portion 301, 321 First conductor 302, 322 First insulator 303 External connection terminal 311 Third surface 312 Fourth surface 313 Side surface 323 Second insulator 401 Mounting substrate 401
402 support base 402
501a, 501b Semiconductor chips 502a, 502b Second through electrodes 503a, 503b Circuit elements 504a, 504b, 504c Connection bumps 511a, 511b Fifth surface 512a, 512b Sixth surface 601 Sealing layer 602 Sealing body 701 Groove 702 Insulating film 703 Third conductive film 704 Second conductor
A semiconductor substrate having a first surface and a second surface that is the back surface of the first surface, and having a first through electrode penetrating the first surface and the second surface; ,
A semiconductor chip mounted on the first surface of the semiconductor substrate and made of the same material as the semiconductor substrate and having a circuit element electrically connected to the first through electrode;
A stress comprising a first conductor formed on the second surface of the semiconductor substrate, electrically connected to the first through electrode of the semiconductor substrate, and having flexibility. The mitigation department,
A semiconductor device comprising: an external connection terminal connected to the first conductor on the stress relaxation portion.
The first conductor of the stress relaxation portion is opposite to the second surface of the semiconductor substrate and is electrically connected to the first through electrode, and the third surface. And a side surface connecting the third surface and the fourth surface, the semiconductor device comprising: a fourth surface connected to the external connection terminal; and a side surface connecting the third surface and the fourth surface.
The stress relaxation portion is formed on the second surface of the semiconductor substrate so as to cover the side surface of the first conductor and the second surface of the semiconductor substrate, and has elasticity. A semiconductor device having one insulator.
The semiconductor device according to claim 3,
The semiconductor device, wherein the first insulator is made of a resin.
A semiconductor device according to any one of claims 2 to 4,
A first portion formed on the first surface of the semiconductor substrate and connected to the first through electrode of the semiconductor substrate; and a second portion electrically connected to the circuit element of the semiconductor chip. A semiconductor device comprising: a first conductive film comprising:
A semiconductor device comprising: a sealing layer formed to cover the first conductive film between the semiconductor substrate and the semiconductor chip.
The semiconductor device is characterized in that the sealing layer is made of a resin.
A semiconductor device according to claim 2,
A fourth portion formed on the second surface of the semiconductor substrate and connected to the first through electrode of the semiconductor substrate and connected to the third surface of the first conductor. And a second conductive film provided with a portion.
The semiconductor chip includes a fifth surface facing the first surface of the semiconductor substrate, and a sixth surface that is the back surface of the fifth surface, and the fifth surface and the sixth surface. A second penetrating electrode electrically connected to the circuit element, and
The semiconductor substrate is formed between the first surface of the semiconductor substrate and the fifth surface of the semiconductor chip, is connected to the fourth portion of the second conductive film of the semiconductor substrate, and the semiconductor A semiconductor device comprising a connection bump connected to the second through electrode of the chip.
A semiconductor device according to any one of claims 1 to 9,
A semiconductor device comprising: a sealing body that covers the semiconductor chip and the first surface of the semiconductor substrate.
The semiconductor device is characterized in that the sealing body is made of resin.
The semiconductor device according to claim 10 or 11,
The sealing device includes a ceramic as a material, and a semiconductor device.
The stress relaxation portion is formed to expose at least part of the surface of the first through electrode on the second surface of the semiconductor substrate, and has a first insulator having elasticity,
A fifth portion formed on the second surface of the semiconductor substrate and connected to the first through electrode; and formed between the external connection terminal and the first insulator; A semiconductor device comprising: a first conductor including a connection portion and a sixth portion connected to the connection terminal.
A semiconductor device according to claim 13,
A distance between the second surface of the semiconductor substrate and the external connection terminal is 50 μm or more.
A chip region including a first surface, a second surface which is the back surface of the first surface, and a first through electrode penetrating the first surface and the second surface is a matrix shape. A step of preparing a plurality of wafers formed in
Forming, on the second surface of each of the chip regions, a stress relaxation portion including a flexible first conductor that is electrically connected to the first through electrode;
Forming an external connection terminal on each of the stress relaxation portions so as to be electrically connected to the first conductor;
Mounting the semiconductor chip on the first surface of each chip region so that the circuit element of the semiconductor chip and the first through electrode are electrically connected;
And a step of dividing the wafer into individual pieces for each of the chip regions.
Forming a stress relaxation portion on the second surface of each chip region,
A third surface facing the second surface and electrically connected to the first through electrode on the second surface of each chip region; and a back surface of the third surface; Forming a first conductor having a fourth surface connected to the external connection terminal, and a side surface connecting the third surface and the fourth surface. Device manufacturing method.
A method of manufacturing a semiconductor device according to claim 17,
After performing the step of forming the first conductor on the second surface of each chip region,
Forming a first insulator on the second surface of each chip region so as to cover the fourth surface, the side surface, and the second surface of the first conductor;
And a step of polishing the first insulator until the first conductor is exposed.
A method of manufacturing a semiconductor device according to claim 18,
Polishing the first insulator until the first conductor is exposed,
A method of manufacturing a semiconductor device, wherein the first conductor is polished until it has a thickness in the range of 50 μm to 200 μm.
A method for manufacturing a semiconductor device according to any one of claims 16 to 19, comprising:
Further, a first portion connected to the first through electrode and a second portion connected to the third surface of the first conductor are formed on the second surface of each chip region. A method for manufacturing a semiconductor device, comprising: forming a first conductive film provided.
A method for manufacturing a semiconductor device according to any one of claims 16 to 20, comprising:
Furthermore, on the first surface of each chip region, a third portion connected to the first through electrode of the chip region, and a fourth portion electrically connected to the circuit element of the semiconductor chip A method for manufacturing a semiconductor device, comprising: forming a second conductive film comprising:
A method of manufacturing a semiconductor device according to claim 21,
Furthermore, the circuit element is electrically connected to the semiconductor chip having a fifth surface facing the first surface of the chip region and a sixth surface which is the back surface of the fifth surface. Forming a second through electrode penetrating the fifth surface and the sixth surface;
Forming a first connection bump connected to the fourth portion of the second conductive film on the fifth surface of the semiconductor chip.
Forming the second through electrode on the semiconductor chip,
Forming a groove in a circuit forming surface on which the circuit element of the semiconductor chip is formed;
Coating at least a side of the groove with an insulating film;
Filling the groove covered with the insulating film with a second conductor;
Polishing the back surface of the circuit formation surface of the semiconductor chip until the second conductor is exposed.
A method of manufacturing a semiconductor device according to claim 23, wherein
Polishing the back surface of the circuit element forming surface of the semiconductor chip is performed so that the semiconductor chip has a thickness in the range of 20 μm to 100 μm.
A method for manufacturing a semiconductor device according to claim 23 or 24, wherein:
And a step of forming a sealing layer so as to cover the second conductive film between the first surface of each chip region and the fifth surface of each semiconductor chip. A method of manufacturing a semiconductor device.
A method for manufacturing a semiconductor device according to any one of claims 16 to 25, comprising:
Furthermore, a step of covering each semiconductor chip and each first surface with a sealing body,
And a step of polishing the upper surface of the sealing body.
27. A method of manufacturing a semiconductor device according to claim 26, comprising:
Polishing the upper surface of the sealing body is performed so that a distance between the upper surface of the sealing body and the sixth surface of the semiconductor chip is 100 μm or less. .
Forming a stress relaxation portion including a flexible first conductor on the second surface of each chip region;
Forming a first insulator so as to expose at least part of the surface of the first through electrode on the second surface of each chip region;
On the second surface of each chip region, a sixth portion formed between the fifth portion connected to the first through electrode, the external connection terminal, and the first insulator. Forming a first conductor having a portion. A method for manufacturing a semiconductor device, comprising:
A third surface formed on the second surface of the semiconductor substrate, facing the second surface of the semiconductor substrate and electrically connected to the first through electrode; A first conductor having a fourth surface which is the back surface of the third surface, and a side surface connecting the third surface and the fourth surface;
A semiconductor device comprising: an external connection terminal formed on the fourth surface of the first conductor.
30. The semiconductor device according to claim 29, wherein
A first insulator having elasticity is formed on the second surface of the semiconductor substrate so as to cover the side surface of the first conductor and the second surface of the semiconductor substrate. A semiconductor device.
JP2005098591A 2005-03-30 2005-03-30 Semiconductor device and its manufacturing method Pending JP2006278906A (en)
JP2005098591A JP2006278906A (en) 2005-03-30 2005-03-30 Semiconductor device and its manufacturing method
US11/406,232 US8143718B2 (en) 2005-03-30 2006-04-19 Semiconductor device having stress relaxation sections
JP2006278906A true JP2006278906A (en) 2006-10-12
ID=37069374
JP2005098591A Pending JP2006278906A (en) 2005-03-30 2005-03-30 Semiconductor device and its manufacturing method
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JP (1) JP2006278906A (en)
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