Source: http://www.google.com/patents/US7129182?dq=artistshare
Timestamp: 2016-05-29 02:07:57
Document Index: 402487160

Matched Legal Cases: ['art 203', 'art 203', 'art 203', 'art 203', 'art 203', 'art 203']

Patent US7129182 - Method for etching a thin metal layer - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer....http://www.google.com/patents/US7129182?utm_source=gb-gplus-sharePatent US7129182 - Method for etching a thin metal layerAdvanced Patent SearchPublication numberUS7129182 B2Publication typeGrantApplication numberUS 10/704,498Publication dateOct 31, 2006Filing dateNov 6, 2003Priority dateNov 6, 2003Fee statusLapsedAlso published asUS20050101134Publication number10704498, 704498, US 7129182 B2, US 7129182B2, US-B2-7129182, US7129182 B2, US7129182B2InventorsJustin K. Brask, Mark L. Doczy, Jack Kavalieros, Uday Shah, Matthew V. Metz, Robert S. Chau, Robert B. Turkot, Jr.Original AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (33), Non-Patent Citations (16), Referenced by (18), Classifications (15), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod for etching a thin metal layer
US 7129182 B2Abstract
A method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer.
The present invention relates to methods for etching metal layers, in particular, those formed when making semiconductor devices.
It may be desirable to use a metal gate electrode when making a MOS field-effect transistor that includes a high-k gate dielectric. When forming such a metal gate electrode, it may be necessary to remove portions of a previously deposited very thin metal layer. As shown in FIG. 1 a, patterned masking layer 102 may define sections of metal layer 101 to be removed. If a wet etch process is applied to remove part of metal layer 101, that process may etch metal layer 101 isotropically. As a consequence, part of metal layer 101 may be etched from beneath masking layer 102, as FIG. 1 b illustrates. The resulting undercut may have adverse consequences.
FIGS. 1 a–1 b illustrate a process for etching a metal layer.
FIGS. 2 a–2 b represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention.
FIGS. 3 a–3 c identify hexa-dentate chelating agents that may be used in an embodiment of the method of the present invention.
FIGS. 4 a–4 c represent cross-sections of structures that may be formed when carrying out a second embodiment of the method of the present invention.
FIGS. 5 a–5 g represent cross-sections of structures that may be formed when carrying out a third embodiment of the method of the present invention.
A method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer. In the following description, a number of details are set forth to provide a thorough understanding of the present invention. It will be apparent to those skilled in the art, however, that the invention may be practiced in many ways other than those expressly described here. The invention is thus not limited by the specific details disclosed below.
FIGS. 2 a–2 b illustrate structures that may be formed, when carrying out an embodiment of the method of the present invention. Initially, metal layer 201 is formed on substrate 200. Masking layer 202 is then deposited and patterned to generate the FIG. 2 a structure. Metal layer 201 preferably is less than about 100 angstroms thick, and more preferably is between about 25 angstroms and about 50 angstroms thick. Metal layer 201 may comprise any metal that may be etched. Examples of such metals include: hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, metal carbides and conductive metal oxides. Metal layer 201 may be formed on substrate 200 using a conventional PVD or CVD process, as will be apparent to those skilled in the art. Masking layer 202 preferably comprises a silicon nitride or silicon dioxide hard mask, which may be deposited and patterned in the conventional manner.
After masking layer 202 is patterned, exposed part 203 of metal layer 201 is removed, generating the FIG. 2 b structure. In the method of the present invention, exposed part 203 of metal layer 201 is removed using a wet etch chemistry that comprises an active ingredient. That active ingredient preferably comprises an etchant that is associated with a sufficient number of water molecules to solubilize the etchant. The resulting complex—which may have a quasi-spherical configuration and may be identified as a “hydrated etchant”—must have a diameter that exceeds the thickness of metal layer 201.
In a particularly preferred embodiment, a wet etch chemistry comprising an aqueous solution that includes a chelating agent (e.g., an organic compound that may bind to a metal ion to form a chelate) is applied to exposed part 203 of metal layer 201 to remove that part of that layer. Examples of potentially useful chelating agents include those that have been employed to remove metallic contaminants from semiconductor substrates. Particularly preferred are hexa-dentate chelating agents (i.e., chelating agents with six bonding atoms). FIGS. 3 a–3 c identify some hexa-dentate chelating agents that may be used, including carboxylic acid based chelating agents 301 and 302 (EDTA and CDTA, respectively); catechol 303 (representative of phenol derivatives that may be used); and phosphonic acid based chelating agents 304 and 305 (c-TRAMP and DTPMP). When such well known chelating agents are added to an aqueous solution to etch metal layer 201, they should be included at a concentration of between about 0.5 and about 5.0 moles/liter.
In contrast to the method that FIGS. 1 a–1 b illustrate, the method described above ensures that significant amounts of metal layer 201 will not be removed from beneath masking layer 202, when exposed part 203 of metal layer 201 is removed. In a preferred embodiment, less than about 100 angstroms of metal layer 201 are removed from beneath masking layer 202, when exposed part 203 of metal layer 201 is removed. In a more preferred embodiment, less than about 50 angstroms of metal layer 201 are removed from beneath masking layer 202, when exposed part 203 of metal layer 201 is removed.
FIGS. 4 a–4 c illustrate a process for making a semiconductor device that employs the method of the present invention. Initially, high-k gate dielectric layer 401 is formed on substrate 400, and metal layer 402 is formed on high-k gate dielectric layer 401. Part of metal layer 402 is then masked by masking layer 403—generating the FIG. 4 a structure.
FIGS. 5 a–5 g illustrate a process for making a CMOS semiconductor device that employs the method of the present invention. FIG. 5 a represents a cross-section of a structure that includes: high-k gate dielectric layer 501, which is formed on substrate 500; first metal layer 502, which is formed on high-k gate dielectric layer 501; and masking layer 503, which is formed on first metal layer 502.
Dopants may be added to first metal layer 502, as it is formed or after it is formed, to shift layer 502's workfunction to ensure that it falls within the desired range. The optimal concentration of any dopant that is added to first metal layer 502 to shift its workfunction to a targeted level may depend upon the composition and properties of layer 502 (including its initial workfunction), the type of dopant used, and the target workfunction. Metal layers that are doped as, or after, they are deposited fall within the definition of “metal layer,” as that term is used in this application.
In this embodiment, second metal layer 504 is then deposited on first metal layer 502 and on the exposed portion of high-k gate dielectric layer 501—generating the structure illustrated by FIG. 5 c. When first metal layer 502 comprises an n-type metal, second metal layer 504 preferably comprises a p-type metal. Examples of potentially suitable p-type metals for forming second metal layer 504 include: ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.
Although a few examples of materials that may be used to form first and second metal layers 502 and 504 are described here, those layers may be made from many other materials. The term “metal layer,” as applied in this embodiment, thus encompasses any conductive material from which a metal gate electrode may be derived.
When second metal layer 504 and first metal layer 502 comprise multiple components, a wet etch chemistry for etching those layers may include multiple chelating agents—with different agents having an affinity to bind to different components that are contained in those layers. The relative concentration of each chelating agent included in such a solution may be proportional to the relative amounts of each component included in the metal layers.
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