Source: http://www.google.es/patents/US8164517?dq=flatulence
Timestamp: 2013-05-22 23:10:44
Document Index: 338757510

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'art 1000']

Patente US8164517 - Global positioning system receiver timeline management - Google PatentesB�squeda Im�genes Maps Play YouTube Noticias Gmail Drive M�s » B�squeda avanzada de patentes | Historial web | Iniciar sesi�n B�squeda avanzada de patentesPatentesSatellite positioning system (SATPS) receiver that has a plurality of modes and channels, where a timeline module configures the channels based on the mode of operation of the SATPS receiver and reconfigures the channels if the mode of operation of the SATPS changes....http://www.google.es/patents/US8164517?utm_source=gb-gplus-sharePatente US8164517 - Global positioning system receiver timeline management N�mero de publicaci�nUS8164517 B2Tipo de publicaci�nConcesi�n N�mero de solicitud12/091,798 Fecha de publicaci�n24 Abr 2012 Fecha de presentaci�n28 Oct 2006 Fecha de prioridad2 Sep 2003Tambi�n publicado comoEP1952173A2US7719464US20070103365US20090219198US20120188127WO2008024123A2WO2008024123A3 InventoresPaul UnderbrinkGengsheng ZhangQingwen Zhang Cesionario originalCsr Technology Inc.Sirf Technology, Inc. Clasificaci�n de EE.UU.342/357.46342/357.77342/357.4 Clasificaci�n internacionalG01S19/30G01S19/03G01S19/29G01S19/37G01S19/09G01S19/48G01S19/25 Clasificaci�n cooperativaG01S19/05G01S19/37 Clasificaci�n europeaG01S 19/37G01S 19/05ReferenciasCitas de patentes (110)Otras citas (3)Enlaces externosUSPTO Cesi�n de USPTO EspacenetGlobal positioning system receiver timeline managementUS 8164517 B2 Resumen Satellite positioning system (SATPS) receiver that has a plurality of modes and channels, where a timeline module configures the channels based on the mode of operation of the SATPS receiver and reconfigures the channels if the mode of operation of the SATPS changes.
a memory that has at least one data structure; and
a timeline manager module that controls a respective processing time of at least one of a number of time multiplexed channels for data flow over a common pipeline between the signal processing subsystem and the FFT subsystem,
wherein the at least one respective processing time is adjusted based on requirements of the satellite positioning receiver.
2. The satellite positioning receiver of claim 1, including a plurality of channels in the satellite positioning receiver that are associated with positioning data stored in the at least one data structure.
3. The satellite positioning receiver of claim 2, where the data structure is a circular data structure having a plurality of records.
4. The satellite positioning receiver of claim 2, where the size of the records in the data structure is determined by the timeline manager module based upon a mode of the satellite positioning receiver.
5. The satellite positioning receiver of claim 4, where the size of the records in the data structure is changed in response to a change in the mode of the satellite positioning receiver.
6. The satellite positioning receiver of claim 4, including an additional end margin portion at the end of the record.
7. The satellite position receiver of claim 6, including an additional start margin portion at the beginning of the record.
8. The satellite positioning receiver of claim 1, where the timeline manager module, signal processing subsystem and FFT subsystem share the memory.
9. A method of timeline management in a satellite positioning receiver, comprising the steps of:
configuring a number of time multiplexed channels each having a respective processing time for a memory that contains satellite positioning signal data accessed by a signal processing subsystem and a Fast Fourier Transfer (FFT) subsystem over a common pipeline; and
minimizing stall times when the signal processing subsystem and the FFT subsystems are accessing the number of channels by adjusting at least one of the respective processing times.
10. The method of timeline management of claim 9, where configuring a number of channels, further includes the steps of:
determining an operation mode of the satellite positioning receiver; and
setting the size of the channel is based upon the operation mode.
11. The method of timeline management of claim 10, where setting the size of the channel further includes the step of configuring a circular data structure having a plurality of records, where each record in the circular data structure is associated with a channel in the number of channels.
12. The method of timeline management of claim 10, including the steps of:
determining a change in the operation mode; and
changing the size of the channel in response to the change in the operation mode.
13. The method of timeline management of claim 10, where setting the size of the channel further includes the step of accounting for a margin portion within the channel.
14. The method of timeline management of claim 13, where accounting for the margin portion occurs at the beginning of the channel.
15. The method of timeline management of claim 13, where accounting for the margin portion occurs at the end of the channel.
16. Computer-readable storage medium storing instructions that upon execution by a processor cause the method of timeline management in a satellite positioning receiver to occur, the medium having stored instructions that cause the system processor to perform the steps comprising:
17. The medium of claim 16, where configuring the number of channels further includes:
setting a size of the channel in the memory is based upon the operation mode.
18. The medium of claim 17, where setting the size of the channel further includes configuring a circular data structure having a plurality of records, where each record in the circular data structure is associated with a channel in the number of channels.
19. The medium of claim 17, further including the steps of:
20. The medium of claim 17, where setting the size of the channel further includes accounting for a margin portion within the channel.
21. The medium of claim 20, where accounting for the margin portion occurs at the beginning of the channel.
22. The medium of claim 20, where accounting for the margin portion occurs at the end of the channel.
RELATED APPLICATIONS This application is a continuation in part of patent application Ser. No. 10/570,578, filed on now U.S. Pat. No. 8,013,787and titled �CONTROL AND FEATURES FOR SATELLITE POSITIONING SYSTEM RECEIVERS�, that claimed priority to PCT Patent Application No. PCT/US2004/028542, filed on Sep. 2, 2004, and titled �CONTROL AND FEATURES FOR SATELLITE POSITIONING SYSTEM RECEIVERS�, that claimed priority to U.S. Provisional Patent Application No. 60/546,816, filed on Feb. 23, 2004, U.S. Provisional Patent Application No. 60/547,385, filed on Feb. 23, 2004, and U.S. Provisional Patent Application No. 60/499,961, filed on Sep. 2, 2003; and is a continuation-in-part of U.S. patent application Ser. No. 10/570,833, filed on Oct. 5, 2009, and titled �SIGNAL PROCESSING SYSTEM FOR SATELLITE POSITIONING SIGNALS�, that claimed priority to PCT Patent Application No. PCT/US2004/028926, filed on Sep. 2, 2004, and titled �SIGNAL PROCESSING SYSTEM FOR SATELLITE POSITIONING SIGNALS�, that claimed priority to U.S. Provisional Patent Application No. 60/546,816, filed on Feb. 23, 2004, U.S. Provisional Patent Application No. 60/547,385, filed on Feb. 23, 2004, and U.S. Provisional Patent Application No. 60/499,961, filed on Sep. 2, 2003; and claims priority to U.S. Provisional Patent Application No. 60/731,208, filed on Oct. 28, 2005, with all applications being incorporated by reference herein.
SUMMARY Systems consistent with the present invention enable a SATPS signal processor or a controller acting as a SATPS signal processor to employ a single-signal processing pipeline that may be time multiplexed among a number of channels. The single-signal processing pipeline enables continuous processing of data and may be achieved with a circular data structure of channel records associated with each of the channels that may be processed by the SATPS signal processor or the controller acting as the SATPS signal processor. The SATPS signal processor or other controller enables the assignment and configuration of channels for satellite acquisition, verification, bit synchronization, or tracking satellites by configuration of the sequencing and control of a timeline managed by a timeline manager module. The optimization of the timeline occurs by the SATPS signal processor or other controller acting as a SATPS signal processor having a code phase value for the running channels set up and maintained by the timeline manager module. The timeline manager module may be a hardware device running software, or a software process being executed within the hardware of the SATPS signal processor or the controller acting as a SATPS signal processor.
DETAILED DESCRIPTION The discussion below is directed to a hardware and software architecture that provides control and features in a receiver for use in satellite positioning systems (SATPS), such as the United States Global Positioning Satellite System commonly referred to as a GPS system. Specific features of the architecture of a SATPS receiver include, as examples: initialization of memory; control of data processing; subsystem communication; power control management, and an expert system receiver manager. The SATPS receiver may have a timeline manager module that is responsible for setting up channels used by a SATPS signal processor and fast Fourier transfer (FFT) processor, while minimizing stall time. The architecture and features of the SATPS receiver described below are not limited to the precise implementations described, but may vary from system to system according to the particular needs or design constraints of those SATPS receivers.
Turning to FIG. 1, a block diagram of an embodiment of a SATPS receiver 100, including a radio frequency (�RF�) component 102 and a SATPS signal processor (baseband component) 104. In one embodiment, the RF component 102 and the SATPS signal processor 104 may interface with additional functionality provided by an original equipment manufacturer (�OEM�) subsystem, or �host� processor 106 and OEM memory 108 over a bus 110. As will be described below, the SATPS signal processor 104 may communicate with a memory component 112. The memory component 112 may be separate from the SATPS signal processor 104. In other implementations the memory component 112 may be implemented within the SATPS signal processor 104. The RF component 102 may be directly coupled to an antenna 114 and dedicated to the RF component 102. In other implementations, the antenna 114 may be shared by the RF component 102 and an OEM receiver (not shown). Optionally, the OEM memory 108 may be separate from the memory component 112 and independent from the baseband component 104. Other possible arrangements may include one or more RF components and one or more baseband components being on one or more chips with all of the required memory and processing power to perform the SATPS functions. In yet other implementations, multiple chips may be used to implement the SATPS receiver 100 and may be combined with technology such as flip-chip packaging.
The SATPS receiver 100 may operate without aiding information, or alternatively, it may operate with aiding information from a variety of sources and have additional hardware circuitry and software to communicate with a communication network or communicate with another network via the OEM processor 106. The communication may be implemented using standards, such as those adopted by the Institute of Electrical Engineers, International Standards Organization, or Cellular communication standards, or by using a proprietary communication approach. Furthermore, the SATPS signal processor 104 may also include such circuitry as a digital signal processor (�DSP�), an ARM processor, clock components, various memory components, various interface components for external and internal communication, etc.
In FIG. 2, a block diagram shows subsystems of an embodiment of the SATPS signal processor (baseband chip) 104 from the SATPS receiver 100 of FIG. 1, one of which subsystems includes a timeline manger module 214. The SATPS signal processor 104 may include an input sample subsystem 202, a signal processing subsystem 204, a FFT subsystem 206, a memory subsystem 208, a sequencer subsystem 210, and other �miscellaneous� subsystems 212. One of the miscellaneous subsystems 212 may be a timeline manager module 214. For convenience herein, the subsystems may be referred to as groups of processes or tasks implemented along with associated hardware. The division of tasks or functionality between the subsystems typically is determined by design choice.
Turning to FIG. 4, a channel sequencing control diagram 400 illustrating the communication between signal processing subsystem 204 of FIG. 2 and FFT subsystem 206 of FIG. 2, using the memory subsystem 208 of FIG. 2. The signal processing subsystem 204 is shown with a circular link list of input sample buffers or channels 402, 404, 406, 408, 410, and 412. The �FIFO zone� is an area in the memory subsystem 208 that contains the buffer pointers 422 in addition to the registers 426 and pointers 424 used to process data through the signal processing subsystem 204 and the FFT subsystem 204. An area in memory is also allocated for a channel record 420 that contains semaphores associated with the different channels. Similarly, the FFT subsystem 206 executes on the same plurality of channels 402, 404, 406, 408, 410, and 412. The �FIFO zone� 208 also has buffer pointers 422, pointers 424 and registers 426.
The signal processor may be configured to process a circular linked list of channel records, as shown in FIG. 4. The channels may be assigned to perform satellite acquisition, verification, bit synchronization, or tracking. The control of the sequencing operations occurs via three processing threads (signal processing thread, FFT thread, and software thread). These threads each execute independently, but are synchronized by interaction of data flow through the �FIFO zone� 208.
Acqcnt[24:12]-codephase[31:19]>(fifo size in units of blocks<<Shift). The input sample buffer is in an underflow condition when:
Acqcnt[24:12]-codephase[31:19]<(margin for turn on time in units of blocks<<shift),
Acqcnt[24:5]-codephase[31:12]>((fifo size in units of blocks <<shift)<<7). The input sample buffer is in an underflow condition when:
Acqcnt[24:5]-codephase[31:12]<((margin for turn on time in units of blocks <<shift)<<7). When a channel overflow is detected, an interrupt is once again generated, but the channel keeps running until the number of milliseconds of data to be processed are processed. When a channel underflow is detected, that channel will stall until the input sample buffer 502 has additional data. This continues until the entire context time is complete.
FIG. 6 illustrates a table 600 of Fast Fourier Transfer Modes used by FFT 332 of FIG. 3. The FFT throughput for the different modes of processing may be determined using the formulas in the table shown in FIG. 6, where corrMod is the number of taps, t1cntsize is the number of t1s in a PDI (pre-detection interval), and t1 is the coherent integration time for one FFT input point, and enHalfChip identifies if spacing is a � chip or full chip.
idealCodePhase ⁢ ⁢ ( k ) = codePhase ⁡ ( chBase ) + ∑ i = 0 k - 1 ⁢ ( T p i + T c i ) - ∑ i = 0 chBase - 1 ⁢ ( T p i + T c i ) - bias ⁡ ( chBase ) , where chBase is the base channel the timeline manager module uses to set up the ideal codephase values for the other channels, and bias is the difference between the base channel codephse value and its idealCodePhase value.
To support the minus one millisecond adjustment on the context time, the start margin portion 802 should not be less than one millisecond and the end margin portion 902 should be large enough to store the incoming samples during the channel processing, i.e., the margin should be larger than or equal to max(Tp k+Tc k), where superscript k stands for channel k. Therefore the minimum input sample buffer size should be ((endM sec+3)+max(Tp k+Tc k)).
FIG. 10 is a chart 1000 that illustrates the five types of channel alignment 1002, 1004, 1006, 1008 and 1010. The timeline manager module 214, when starting a channel, computes the desired start time and then sends the desired start time to the timeline manager module 214. It is the timeline manager module's 214 responsibility to start the channels correctly. The timeline manager module 214 determines the actual start time of the channel based on the type of alignment required, the desired start time, and existing timeline. The first type of alignment is the NO_ALIGNMENT 1002 type of alignment and is employed when the full C/A code search is performed and the search does not require NAV bit alignment. The second type of alignment is the 1MS_ALIGNMENT 1004 type and is a one-millisecond alignment when the partial C/A code search is performed and the search does not require NAV bit alignment. The third type of alignment is a PDI_ALIGNMENT 1006 type alignment and is employed when the search requires NAV bit alignment and PDI is less than 20 milliseconds (The PDI is also a factor of 20 milliseconds). The fourth type of alignment is 20MS_ALIGNMENT 1008, and is the twenty milliseconds alignment that is used when NAV bit alignment and PDI are equal to or an integer multiple of 20 milliseconds. The fifth type of alignment is NAVBIT_ALIGNMENT 1010, and is an integer multiple of NAV bits alignment that is used when Nav Bit Aiding is performed by the SATPS receiver 100.
FIG. 11 is a diagram 1100 of the relationship of signal processing subsystem 204 and FFT subsystem 206 of FIGS. 2 and 4. The signal processing subsystem starts processing at codePhase and the FFT subsystem starts at pdiBaseCntSav. The data between codePhase and the pdiBaseCntSave may be ignored by the FFT subsystem because it has not started. Once started the FFT subsystem begins processing the data from the channels.
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