Source: http://www.google.com/patents/US20070198792?dq=5,266,072
Timestamp: 2016-02-07 21:52:58
Document Index: 309267754

Matched Legal Cases: ['in fine', 'in fine', 'in fine', 'in fine', 'art 202', 'art 203', 'art 203', 'art 400', 'art 500', 'art 500', 'art 500', 'art 500', 'art 900', 'art 900', 'in fine', 'art 1000', 'art 1000', 'in fine']

Patent US20070198792 - Methods and apparatus to implement parallel transactions - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA computer system includes multiple processing threads that execute in parallel. The multiple processing threads have access to a global environment including different types of metadata enabling the processing threads to carry out simultaneous execution depending on a currently selected type of lock...http://www.google.com/patents/US20070198792?utm_source=gb-gplus-sharePatent US20070198792 - Methods and apparatus to implement parallel transactionsAdvanced Patent SearchPublication numberUS20070198792 A1Publication typeApplicationApplication numberUS 11/475,262Publication dateAug 23, 2007Filing dateJun 27, 2006Priority dateFeb 22, 2006Also published asUS7496716, US7669015, US8065499, US20070198519, US20070198781, US20070198978, US20070198979Publication number11475262, 475262, US 2007/0198792 A1, US 2007/198792 A1, US 20070198792 A1, US 20070198792A1, US 2007198792 A1, US 2007198792A1, US-A1-20070198792, US-A1-2007198792, US2007/0198792A1, US2007/198792A1, US20070198792 A1, US20070198792A1, US2007198792 A1, US2007198792A1InventorsDavid Dice, Nir ShavitOriginal AssigneeDavid Dice, Shavit Nir NExport CitationBiBTeX, EndNote, RefManPatent Citations (22), Referenced by (65), Classifications (15), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethods and apparatus to implement parallel transactions
US 20070198792 A1Abstract
A computer system includes multiple processing threads that execute in parallel. The multiple processing threads have access to a global environment including different types of metadata enabling the processing threads to carry out simultaneous execution depending on a currently selected type of lock mode. A mode controller monitoring the processing threads initiates switching from one type of lock mode to another depending on current operating conditions such as an amount of contention amongst the multiple processing threads to modify the shared data. The mode controller can switch from one lock mode another regardless of whether any of the multiple processes are in the midst of executing a respective transaction. A most efficient lock mode can be selected to carry out the parallel transactions. In certain cases, switching of lock modes causes one or more of the processing threads to abort and retry a respective transaction according to the new mode. Images(11) Claims(20)
1. A method comprising: maintaining an environment to execute multiple processing threads in parallel; and during execution of the multiple processing threads, switching a manner of the execution between transactional memory usage and non-transactional memory usage of a region of respective shared data. 2. A method as in claim 1, wherein switching the manner of execution includes: switching between multiple types of lock modes including a centralized lock mode associated with non-transactional memory usage in which the multiple processing threads compete to obtain a coarse-grained lock over respective shared data and a distributed lock mode associated with transactional memory usage in which the multiple processing threads compete to obtain finer-grained locks over sub-portions of the respective shared data, the method further comprising: monitoring a level of contention of the multiple processing threads competing to obtain locks and, thereafter, modify contents of the respective shared data; and wherein switching the manner of the execution occurs in response to detecting that one of the central lock mode and the distributed lock mode is more suitable for carrying out the execution of the multiple processing threads. 3. A method as in claim 1, wherein switching the manner of the execution occurs in response to detecting which one of the transactional memory usage and the non-transactional memory usage would be a more efficient memory usage mode to carry out the execution of the multiple processing threads; and the method further comprising initiating a change of a currently implemented memory usage mode associated with the environment to the more efficient memory usage mode. 4. A method as in claim 1 further comprising: maintaining globally accessible mode setting information enabling each of the multiple processing threads to identify a current memory usage mode of the environment for executing the multiple processing threads in parallel. 5. A method as in claim 4 further comprising: enabling the multiple processing threads to identify a type of memory usage mode and selectively abort further execution. 6. A method as in claim 1 further comprising: initiating the non-transactional memory usage to include global version information and a respective global lock bit accessible by the multiple processing threads, the global version information being updated by a respective processing thread each time the respective processing thread modifies contents of the respective shared data, the respective global lock bit enabling each of the multiple processing threads to obtain a lock over the respective shared data preventing other processing threads from modifying the contents of the shared data. 7. A method as in claim 6 further comprising: initiating the transactional memory usage to include a distributed lock mode, the distributed lock mode including corresponding segment version information and a respective segment lock bit for each of multiple segments of the respective shared data accessible by the multiple processing threads, the corresponding segment version information being updated by a respective processing thread each time the respective processing thread modifies contents of the corresponding segment of the respective shared data, the respective segment lock bit enabling each of the multiple processing threads to obtain a lock over the corresponding segment of the respective shared data preventing other processing threads from modifying the contents of the corresponding segment. 8. A method as in claim 2, wherein switching the manner of the execution between the multiple types of lock modes initially requires that a global lock bit associated with the centralized lock mode be in an inactive state in which none of the multiple processing threads currently has a lock over the respective shared data. 9. A method as in claim 2, wherein switching the manner of the execution between the multiple types of lock modes at least in part includes performing an atomic write to a repository in order to simultaneously change: i) mode information identifying a current lock mode setting of the environment, ii) version information normally used to indicate that contents of the respective shared data have been updated, and iii) global lock information to indicate release of a respective lock over the respective shared data. 10. A method as in claim 2 further comprising: for the centralized lock mode, providing global version information that changes to a new respective data value each time one of the multiple processing threads modifies contents of the respective shared data, a given processing thread of the multiple processing threads accessing the global version information multiple times during execution of a respective transaction in order to identify whether any other processing threads modified the contents of the globally accessible shared data during execution of the given thread. 11. A method as in claim 1 further comprising: implementing the non-transactional memory usage of shared data in which a given processing thread carries out steps of: during a read phase, verifying that no other processing threads modifies contents of the respective shared data by monitoring global version information that is updated to a new value upon each modification to the respective shared data; after the read phase, checking whether any one of the other processing threads currently has a lock on the respective shared data; if there is a lock as indicated by the checking, then abort and re-execute a given processing thread; if there is not a lock as indicated by the checking, initiating a respective commit phase with respect to the given processing thread, the commit phase including: i) obtaining a respective lock on the respective shared data which prevents the other processing threads from modifying the respective shared data, ii) initiate modification of the respective shared data in accordance with a respective transaction outcome associated with the given processing thread, and iii) after the modification of the respective shared data, updating a respective data value associated with the global version information to indicate to the other processing threads that the respective shared data has been modified. 12. A method as in claim 11, further comprising: implementing the transactional memory usage of respective shared data in which a given processing thread carries outs steps of: maintaining copies of version information associated with respective segments of the shared data in a locally managed read set associated with a respective transaction carried out by the given processing thread, the read set not being accessible by the other processes using the respective shared data, the read set identifying versions associated with each of the respective segments of shared data used to generate a respective transaction outcome, the copies of version information indicating respective versions of multiple accessed segments at a time when the respective transaction retrieves respective data values associated with the multiple segments of shared data from the environment; and after acquiring a respective lock associated with a given segments of the respective shared data, verifying that current version information associated with each of the multiple segments of shared data previously used to generate the respective transaction outcome matches the version information in the locally managed read set associated with the respective transaction. 13. A computer readable media encoded with a computer program including: instructions to initiate execution of at least one processing thread of multiple processing threads executed in parallel; and instructions to switch a manner of the execution of the at least one processing thread between transactional memory usage and non-transactional memory usage of a region of shared data. 14. A computer readable media as in claim 13, wherein the transactional memory usage is a multi-lock based transactional memory usage and the non-transactional memory usage is a single-lock based memory usage of the region of shared data, the computer program further including: instructions to carry out a respective transaction in accordance with a centralized lock mode in which the multiple processing threads compete to obtain a coarse-grained lock over the region of shared data; and instructions to carry out a respective transaction in accordance with a distributed lock mode in which the multiple processing threads compete to obtain finer-grained locks over sub-portions of the region of shared data. 15. A computer readable media as in claim 13, the computer program further comprising: instructions to check globally accessible information indicating a current respective memory usage mode for carrying out the multiple processing threads in parallel; and instructions to switch the manner of the execution of the at least one processing thread in response to detecting a change from one of the transactional memory usage and the non-transactional memory usage to a more suitable memory usage mode for carrying out the execution of the multiple processing threads. 16. A computer readable media as in claim 13, the computer program further comprising: instructions to abort execution of a respective transaction associated with the at least one processing thread after identifying a change in a type of memory usage to either transactional memory usage or non-transactional memory usage. 17. A computer system including: multiple processing threads executing in parallel; and a global environment accessible by the multiple processing threads, the global environment including i) shared data utilized by the multiple processing threads, ii) mode setting information indicating a current lock mode for executing the multiple processing threads in parallel, the current lock mode being one of a first lock mode for implementing multi-lock based transactional memory usage and a second lock mode for implementing single-lock based memory usage of the shared data. 18. A computer system as in claim 17, wherein the first lock mode is a centralized lock mode in which the multiple processing threads compete to obtain a coarse-grained lock over the shared data; and wherein the second lock mode is a distributed lock mode in which the multiple processing threads compete to obtain finer-grained locks over sub-portions of the shared data. 19. A computer system as in claim 17, wherein the global environment includes: global lock information enabling a respective one of the multiple processing threads to obtain a respective lock and prevent other processing threads from modifying any of the shared data when in the first lock mode; and segment lock information for each of multiple segments of the region of shared data, the segment lock information enabling a respective one of the multiple processing threads to obtain a respective lock and prevent other processing threads from modifying contents of a corresponding segment of the shared data when in the second lock mode. 20. A computer system as in claim 19, wherein the global environment includes: global version information enabling a respective one of the multiple processing threads to identify whether contents of the shared data has been modified by another processing thread because each of the multiple processing threads updates a value of the global version information upon modification of the shared data when in the first lock mode; and segment version information for each of multiple segments of the shared data, the segment version information associated with the multiple segments enabling a respective one of the multiple processing threads to identify whether contents of any corresponding segments of the shared data have been modified by another processing thread because each of the multiple processing threads updates a value of corresponding segment version information upon modification of the corresponding segment of shared data when in the second lock mode. Description
RELATED APPLICATIONS [0001] This application claims the benefit of and priority to U.S. Provisional Patent Application Ser. No. 60/775,564 [Attorney's docket no. SUN06-01(060711)p], filed on Feb. 22, 2006, entitled “Switching Between Read-Write Locks and Transactional Locking,” the entire teachings of which are incorporated herein by this reference. [0002] This application is related to U.S. Patent Application identified by Attorney's docket no. SUN06-03(060711), filed on same date as the present application, entitled “METHODS AND APPARATUS TO IMPLEMENT PARALLEL TRANSACTIONS,” which itself claims the benefit of and priority to U.S. Provisional Patent Application Ser. No. 60/775,564 (Attorney's docket no. SUN06-01(06071 1)p, filed on Feb. 22, 2006, entitled “Switching Between Read-Write Locks and Transactional Locking,” the entire teachings of which are incorporated herein by this reference. [0003] This application is related to U.S. Patent Application identified by Attorney's docket no. SUN06-04(060720), filed on same date as the present application, entitled “METHODS AND APPARATUS TO IMPLEMENT PARALLEL TRANSACTIONS,” which itself claims the benefit of and priority to U.S. Provisional Patent Application Ser. No. 60/775,580 (Attorney's docket no. SUN06-02(060720)p, filed on Feb. 22, 2006, entitled “Transactional Locking,” the entire teachings of which are incorporated herein by this reference. [0004] This application is related to U.S. Patent Application identified by Attorney's docket no. SUN06-06(060908), filed on same date as the present application, entitled “METHODS AND APPARATUS TO IMPLEMENT PARALLEL TRANSACTIONS,” which itself claims the benefit of and priority to U.S. Provisional Patent Application Ser. No. 60/789,483 (Attorney's docket no. SUN06-05(060908)p, filed on Apr. 5, 2006, entitled “Globally Versioned Transactional Locking,” the entire teachings of which are incorporated herein by this reference.
BACKGROUND [0005] There has been an ongoing trend in the information technology industry to execute software programs more quickly. For example, there are various conventional advancements that provide for increased execution speed of software programs. [0006] One technique for increasing execution speed of a program is called parallelism. Parallelism is the practice of executing or performing multiple things simultaneously. Parallelism can be possible on multiple levels, from executing multiple instructions at the same time, to executing multiple threads at the same time, to executing multiple programs at the same time, and so on. Instruction Level Parallelism or ILP is parallelism at the lowest level and involves executing multiple instructions simultaneously. Processors that exploit ILP are typically called multiple-issue processors, meaning they can issue multiple instructions in a single clock cycle to the various functional units on the processor chip. [0007] There are different types of conventional multiple-issue processors. One type of multiple-issue processor is a superscalar processor in which a sequential list of program instructions are dynamically scheduled. A respective processor determines which instructions can be executed on the same clock cycle, and sends them out to their respective functional units to be executed. This type of multi-issue processor is called an in-order-issue processor since issuance of instructions is performed in the same sequential order as the program sequence, but issued instructions may complete at different times (e.g., short instructions requiring fewer cycles may complete before longer ones requiring more cycles). [0008] Another type of multi-issue processor is called a VLIW (Very Large Instruction Width) processor. A VLIW processor depends on a compiler to do all the work of instruction reordering and the processor executes the instructions that the compiler provides as fast as possible according to the compiler-determined order. Other types of multi-issue processors issue out of order instructions, meaning the instruction issue order is not be the same order as the order of instructions as they appear in the program. [0009] Conventional techniques for executing instructions using ILP can utilize look-ahead techniques to find a larger amount of instructions that can execute in parallel within an instruction window. Looking-ahead often involves determining which instructions might depend upon others during execution for such things as shared variables, shared memory, interference conditions, and the like. When scheduling, a handler associated with the processor detects a group of instructions that do not interfere or depend on each other. The processor can then issue execution of these instructions in parallel thus conserving processor cycles and resulting in faster execution of the program. [0010] One type of conventional parallel processing involves a use of coarse-grained locking. As its name suggests, coarse-grained locking over a large segment of shared data prevents conflicting groups of code from operating on different processes at the same time based on use of lockouts. Accordingly, this technique enables non-conflicting transactions or sets of instructions to execute in parallel. [0011] Another type of conventional parallel processing involves a use of fine-grain locking. As its name suggests, fine-grain locking over a small region of memory prevents conflicting instructions from being simultaneously executed in parallel based on use of lockouts. This technique therefore enables non-conflicting instructions to execute in parallel. SUMMARY [0012] Conventional applications that support parallel processing can suffer from a number of deficiencies. For example, although easy to implement from the perspective of a software developer, coarse-grained locking techniques provide very poor performance because of limitations on parallelism. Although fine-grain lock-based concurrent software can perform exceptionally well during run-time, developing such code can be a very difficult task for a respective one or more software developers. [0013] Techniques discussed herein deviate with respect to conventional applications such as those discussed above as well as other techniques known in the prior art. For example, embodiments herein include novel techniques for enhancing performance associated with transactions executing in parallel. [0014] In general, the present disclosure describes a unique way for each of multiple processes to operate in parallel using a common set of data (e.g., shared data) without causing corruption to the shared data. For example, as will be discussed later in this specification, a computer system includes multiple processing threads that execute in parallel. The computer system maintains an environment for executing the multiple processing threads in parallel. During execution of the multiple processing threads, the computer system can support switching a manner of the execution between transactional memory usage and non-transactional memory usage of a region of respective shared data. [0015] The multiple processing threads have access to a global environment including shared data utilized by the multiple processing threads to produce a respective transaction outcome. The global environment includes different types of metadata associated with the shared data. A first type of metadata in the global environment enables multiple parallel processing threads to implement transactional memory usage according to a first type of lock mode. A second type of metadata in the global environment enables the multiple parallel processing threads to implement transactional memory usage according to a second type of lock mode. [0016] In one embodiment, for purposes of implementing a first type of lock mode such as a centralized lock mode, the global environment includes global version information and respective global lock information enabling a respective one of the multiple processing threads to initiate coarse-grained locking and modifications to any portion of the shared data. In the centralized lock mode, only a single processing thread holding a lock can modify the shared data. [0017] For purposes of implementing a second type of lock mode such as a distributed lock mode, the global environment includes segment version information and respective segment lock information associated with each corresponding portion (e.g., segment) of the shared data. Based on use of the segment lock information, each of multiple processing threads can hold different respective locks on corresponding segments of the shared data and perform modifications while in the distributed lock mode. The segment version information enables the processing threads to update and identify when the corresponding segments of shared data have been modified. Thus, in this latter mode, multiple processing threads can simultaneously modify contents of the shared data without causing data corruption. Recall that the centralized lock mode enables only one processing thread to modify the shared data at a time. [0018] Depending on current operating conditions such as an amount of contention amongst the multiple processing threads to modify the shared data, a most efficient lock mode can be selected to carry out the parallel transactions. A mode controller can initiate switching from one type of lock mode to another regardless of whether any of the multiple processes are in the midst of executing a respective transaction according to a given mode setting. [0019] This technique of enabling switching between different types of lock modes is useful in applications that experience changes in operating conditions such as changing conditions in which multiple processing threads execute many more reads than writes or vise versa. For example, at a given moment in time, a first type of lock mode may be inefficient for carrying out parallel processing while a second type of lock mode is well suited for carrying out respective transactions. At another moment in time, the first type of lock mode may be more efficient for carrying out parallel processing while the second type of lock mode may be inefficient for carrying out respective transactions. As discussed above, depending on current conditions such as whether or not there is a lot of contention amongst the parallel processing threads to write to a common region of shared data, an appropriate lock mode can be selected for carrying out the parallel processing threads. In one embodiment, the lock mode can be changed to a new lock mode even though one or more of multiple processing threads is currently is in the midst of operating according to an old lock mode. [0020] Techniques herein are well suited for use in applications such as those executing multiple processing threads in parallel and it is beneficial to switch between different types of lock modes for modifying shared data. However, it should be noted that configurations herein are not limited to such use and thus configurations herein and deviations thereof are well suited for use in other environments as well. [0021] In addition to the embodiments discussed above, other embodiments herein include a computerized device (e.g., a host computer, workstation, etc.) configured to support the techniques disclosed herein such as use of a globally accessible variable (e.g., version information) supporting parallel execution of transaction performed by different processes. In such embodiments, a computer environment can include a memory system, a processor (e.g., a processing device), a respective display, and an interconnect connecting the processor and the memory system. The interconnect can also support communications with the respective display (e.g., display screen or display medium). The memory system can be encoded with one or more applications that, when executed on a respective processor, supports parallel processing according to techniques herein. [0022] Yet other embodiments of the present disclosure include software programs to perform the method embodiment and operations summarized above and disclosed in detail below in the Detailed Description section of this disclosure. More specifically, one embodiment herein includes a computer program product (e.g., a computer-readable medium). The computer program product includes computer program logic (e.g., software instructions) encoded thereon. Such computer instructions can be executed on a computerized device to support parallel processing according to embodiments herein. [0023] For example, the computer program logic, when executed on at least one processor associated with a computing system, causes the processor to perform the operations (e.g., the methods) indicated herein as embodiments of the present disclosure. Such arrangements as further disclosed herein can be provided as software, code and/or other data structures arranged or encoded on a computer readable medium such as an optical medium (e.g., CD-ROM), floppy or hard disk, or other medium such as firmware or microcode in one or more ROM or RAM or PROM chips or as an Application Specific Integrated Circuit (ASIC). The software or firmware or other such configurations can be installed on a computerized device to cause one or more processors in the computerized device to perform the techniques explained herein. [0024] Yet another more particular technique of the present disclosure is directed to a computer program product or computer environment that includes a computer readable medium having instructions stored thereon to facilitate use of shared information among multiple processes. Each of the multiple processes can support a technique of: i) initiating execution of a given processing thread including multiple instructions, the given processing thread producing a respective transaction outcome based on use of globally accessible shared data also accessible by other processing threads executing in parallel; and ii) during execution of the given thread, initiate multiple reads of data from the globally accessible shared data for purposes of producing the transaction outcome; and iii) selectively switching execution of the given processing thread according to one of multiple different types of lock modes including a centralized lock mode in which the given processing thread competes with the multiple processing threads to obtain a coarse-grained lock over respective shared data and a distributed lock mode in which the given processing thread competes with the multiple processing threads to obtain finer-grained locks over sub-portions of the respective shared data. [0025] Other embodiments of the present disclosure include hardware and/or software programs to perform any of the method embodiment steps and operations summarized above and disclosed in detail below. [0026] It is to be understood that the system of the invention can be embodied as a software program, as software and hardware, and/or as hardware alone. Example embodiments of the invention may be implemented within computer systems, processors, and computer program products and/or software applications manufactured by Sun Microsystems Inc. of Palo Alto, Calif., USA.
BRIEF DESCRIPTION OF THE DRAWINGS [0027] The foregoing and other objects, features, and advantages of the present application will be apparent from the following more particular description of preferred embodiments of the present disclosure, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, with emphasis instead being placed upon illustrating the embodiments, principles and concepts. [0028] FIG. 1 is a diagram illustrating a computer environment including multiple parallel processes that access shared data according to embodiments herein. [0029] FIG. 2 is a diagram illustrating switching between multiple lock modes according to embodiments herein. [0030] FIG. 3 is a diagram of a first type of lock mode according to embodiments herein. [0031] FIG. 4 is a diagram of a process maintaining a respective read-set and write-set according to embodiments herein. [0032] FIG. 5 is a respective flowchart associated with a lock mode according to embodiments herein. [0033] FIG. 6 is a respective flowchart associated with a lock mode according to embodiments herein. [0034] FIG. 7 is a diagram of a second type of lock mode according to embodiments herein. [0035] FIG. 8 is a diagram of a sample architecture supporting shared use of data according to embodiments herein. [0036] FIG. 9 is a diagram of a flowchart illustrating a technique supporting simultaneous execution of multiple processing threads according to an embodiment herein. [0037] FIG. 10 is a diagram of a flowchart illustrating a technique supporting simultaneous execution of multiple processing threads according to an embodiment herein.
DETAILED DESCRIPTION [0038] According to one embodiment, a computer system includes multiple processing threads that execute in parallel. The computer system can include an environment for switching of the processing threads amongst transactional memory usage and non-transactional memory usage of a region of respective shared data. The memory usage modes can be lock-free or lock-based memory usage modes although specific embodiments herein discuss use of lock-based memory usage modes. [0039] For example, the multiple processing threads have access to a global environment including different types of metadata enabling the processing threads to carry out respective simultaneous executions depending on a currently selected type of memory usage mode such as a transactional memory usage and non-transactional memory usage. Each of the transactional memory usage and non-transactional memory usage modes can be lock free or include a lock mode. According to one embodiment herein, implementing transactions according to a currently selected lock mode prevents data corruption as a result of multiple processing threads simultaneously changing shared data. [0040] In one embodiment, a mode controller monitoring the processing threads initiates switching from one type of memory usage mode to another. For example, the mode controller can initiate switching from one lock mode to another depending on current operating conditions such as an amount of contention amongst the multiple processing threads to modify the shared data. The mode controller can switch from one lock mode another regardless of whether any of the multiple processes are in the midst of executing a respective transaction. A most efficient memory usage mode and/or type of memory lock mode can be selected to carry out the parallel transactions. In certain cases, switching of modes causes one or more of the processing threads to abort and/or retry a respective transaction according to the new mode. [0041] FIG. 1 is a block diagram of a computer environment 100 according to an embodiment herein. As shown, computer environment 100 includes shared data 125 (e.g., which can be partitioned according to segments 210) and corresponding metadata 135 in global environment 102 (e.g., a respective repository such as memory) that is globally accessible by multiple processes 140 such as process 140-1, process 140-2, . . . process 140-M. Mode setting information 120-3 identifies a current selection of a lock mode for carrying out simultaneous execution by the multiple processes 140 (e.g., process 140-1, process 140-2, . . . , process 140-M). To carry out execution according to mode A (e.g., a so-called M4 lock mode), each of processes 140 (e.g., processing threads) utilizes global version information 120-1 and global lock bit 120-2 and has an associated local repository 110-1 (e.g., an exclusive portion of memory). For example, in one embodiment, each of processes 140 (e.g., processing threads) has a corresponding local repository 110 for storing information such as an instantaneous value of version information 120-1 at different times during execution of a corresponding set of multiple instructions. To carry out execution according to mode B (e.g., a so-called TL or transactional locking mode), each of processes 140 (e.g., processing threads) utilizes version information 220 and global lock bit 230 to maintain an associated read-set 150 and write-set 160 (e.g., exclusive portions of memory). [0042] As discussed above, the present disclosure describes a unique way for each of multiple processes 140 to operate in parallel using a common set of shared data 125 without causing corruption to the shared data 125. For example, computer environment 100 includes multiple processes 140 that execute in parallel. The multiple processes 140 access shared data 125 in the global environment 102 (e.g., memory). [0043] Global environment 102 includes different types of metadata 135 associated with the shared data 125. For example, global environment 102 includes metadata 135-1 and metadata 135-2. The first type of metadata 135-1 enables the processes 140 to implement memory usage according to mode A (e.g., a non-transactional memory usage mode. The second type of metadata 135-2 enables the processes 140 to implement transactional memory usage according to a second type of mode (e.g., mode B or a transactional memory usage mode). [0044] Transactional memory usage according to one embodiment herein basically involves breaking up a program to atomic chunks of code called transactions. The transactions pass data to each other through use of shared memory. In such a mode, the transactions are stored in a location other than the shared memory such as a write buffer, cache, etc. until the transaction completes execution. When the transaction ends, the transaction commits results to memory. At the point of committing the results, any uncommitted transactions of the other processing threads that used the same data as the processing thread committing its results must roll back (e.g., via an undo log) and re-execute the transaction. [0045] For purposes of implementing a centralized type of lock mode (e.g., a non-transactional memory usage mode based on a first type of lock mode), the global environment 102 includes global version information 120-1 and a respective global lock bit 120-2 (e.g., global lock information) enabling a respective one of the multiple processes 140 to initiate coarse-grained locking and modifications to an overall region of shared data 125 including multiple segments such as segment 210-1, segment 210-2, . . . , segment 210-N. In the centralized lock mode, only a single processing thread or process 140 holding a single lock (e.g., the global lock bit 120-2) can modify the shared data 125. After completing modification to shared data 125, a respective process 140 releases a lock by changing a state of the global lock bit 120-1 back to the free mode. [0046] For purposes of implementing parallel transaction while in a distributed lock mode (e.g., a transactional memory usage mode having an associated second type of lock mode), the global environment 102 includes segment version information 220 and respective segment lock bit information 230 associated with respective segments 210 (e.g., portions) of shared data 125. Based on use of the segment lock bit information 230, each of multiple processing threads can hold different respective locks on corresponding segments of the shared data while in the distributed lock mode. For example, one process can hold a lock on one segment while another process holds at least lock on another segment, and so on. Respective segment version information 220 enables the processes 140 to identify when the corresponding segment of shared data has been modified. Accordingly, when in mode B, multiple processes can simultaneously modify contents of the shared data 125 without causing data corruption. [0047] Depending on current operating conditions such as an amount of contention amongst the multiple processes to modify the shared data 125, a most efficient memory usage mode can be selected to carry out the parallel transactions. In the context of one embodiment, a mode controller 124 can initiate switching from one type of lock mode (e.g., transactional memory usage) to another type of mode (e.g., a non-transactional memory usage by modifying contents of mode setting information 120-3 in global environment 102) regardless of whether any of the multiple processes 140 are in the midst of executing a respective transaction. The mode controller 124 can base a current setting of the current lock mode type depending on input from lock contention monitor 122. In one embodiment, lock contention monitor 122 monitors how often each of the processes 140 has to abort as a result of contention with other processes. [0048] As shown and as discussed above, the mode controller 124 can be implemented as a separate entity with respect to processes 140. In one embodiment, functionality associated with the mode controller 124 can instead be provided by one or more of processes 140. For example, any or all of processes 140 can be programmed to modify respective mode setting information 120-3 to change a current mode setting of global environment 102. The mode setting options can include a transactional memory usage mode and a non-transactional memory usage mode for executing the processing threads. Other types of selectable modes include a centralized lock-based mode (e.g., a non-transactional memory usage mode) versus a distributed lock mode (e.g., a transactional memory usage mode). [0049] This disclosed technique of enabling switching between different types of memory usage modes is useful in applications that experience changes in operating conditions such as multiple processing threads that execute many more reads than writes and vise versa. For example, at a given moment in time, a first type of mode may be inefficient for carrying out parallel processing while a second type of lock mode is well suited for carrying out respective transactions. At another moment in time, the first type of mode may be more efficient for carrying out parallel processing while the second type of mode may be inefficient for carrying out respective transactions. [0050] Depending on current conditions such as whether or not there is a lot of contention amongst the processes 140 to write to a common region of shared data 125, an appropriate mode (e.g., mode A or mode B or yet other possible modes) can be selected for carrying out the parallel processing threads. As mentioned above, the mode can be changed to a new mode even though one or more of multiple processes 140 happens to be in the midst of operating according to an old lock mode. If a process 140-1 cannot gracefully complete without causing data corruption as a result of a mode change, then the respective one or more processes 140 can be aborted (e.g., self-aborted). [0051] FIG. 2 is a block diagram illustrating how to switch modes (e.g., modify mode setting information 120-3 from a transactional memory usage to non-transactional memory usage or from a centralized lock mode to a distributed type lock mode) according to an embodiment herein. Flowchart 202 illustrates how mode controller 124 (in FIG. 1) switches from mode A (e.g., a centralized type of transactional memory lock mode) to mode B (e.g., a distributed type of memory lock mode) if there exists high lock contention amongst the multiple processes 140 executing in parallel. Flowchart 203 illustrates how mode controller 124 (in FIG. 1) switches from mode B (e.g., a distributed transactional memory usage mode) to mode A (e.g., a centralized non-transactional memory usage memory lock mode) if there exists low lock contention amongst the multiple processes 140 executing in parallel. Note that the mode controller 124 can also occasionally or periodically switch from one mode to another for purposes of testing which mode is best suited at any given moment. [0052] To switch from mode A (e.g., a non-transactional memory usage mode) to mode B (e.g., a transactional memory usage mode), the mode controller 124 initially verifies that the global lock bit 120-2 is inactive (e.g., set to a logic low or unasserted state) indicating that none of the processes 140 owns a lock over shared data 125 in step 282. [0053] If there is no lock, the mode controller 124 acquires a respective lock by setting the global lock bit 120-2 to a logic one to activate a lock over the shared data 125 in step 284. Once obtained, the lock obtained by the mode controller 124 prevents the processes 140 from obtaining a respective lock and modifying shared data 125. This technique of waiting to acquire the global lock bit 120-2 (when it is free) enables another process 140 holding the lock to complete committing results to shared data 125. Thus, such a process will not need to abort as a result of a mode change from mode A to mode B. [0054] In step 286, after obtaining the lock, the mode controller 124 updates (e.g., increments) the global version information 120-1, sets the mode setting 120-3 to mode B setting for global environment 102. After completion of these operations, the mode controller 124 releases the lock over shared data 125 by setting the global lock bit 120-2 back to a logic zero. [0055] To switch from mode B to mode A according to flowchart 203, the mode controller 124 initially verifies that the global lock bit 120-2 is inactive indicating that none of the processes 140 owns a lock over shared data 125 in step 292. [0056] If there is no lock present as initiated by the other processes 140, the mode controller 124 acquires a respective lock by setting the global lock bit 120-2 to a logic one to activate a lock over the shared data 125 in step 294. Once obtained, the lock prevents the processes from obtaining a respective lock and modifying shared data 125. This technique of waiting to acquire the global lock bit 120-2 when it is free enables another process 140 holding the lock to complete committing results to shared data 125. Thus, such a process holding the lock will not need to abort as a result of a mode change from mode B to mode A. [0057] In step 296, the mode controller 124 updates (e.g., increments) the global version information 120-1, sets the mode setting 120-3 to mode A setting for global environment 102. After completion of these operations, the mode controller 124 releases the lock over shared data 125 by setting the global lock bit 120-2 back to a logic zero. [0058] Note that step 292 and step 293 may not be performed according to one embodiment herein. For example, when switching from mode B to mode A, the mode controller 124 changes the mode setting 120-3 without regard to whether another process 140 has a current lock over shared data 125. [0059] FIG. 3 is a diagram more particularly illustrating details associated with a respective process operating in mode B (e.g., a centralized lock mode) according to embodiments herein. For clarity sake, FIG. 3 illustrates read and write operations that can be performed by any one of the multiple processes 140 while in mode B. For example, each of the multiple processes 140 can simultaneously perform read operations. In general, the processes 140 do not compete with each other to perform read type of operations. However, a respective process must obtain a lock over global environment 102 (e.g., shared data 125) before modifying or writing to contents of shared data 125. [0060] Each of the multiple processes 140 can perform a respective read operation 205-1 to retrieve one or more data values associated with shared data 125. Assume in the following example that process 140-1 carries out read operation 205-1. Note that each process 140 can simultaneously operate in a similar manner while in mode A. Brief Description of Utilizing Mode A (e.g., M4 mode) [0061] In step 208, a given process 140-1 (e.g., any one of multiple processes 140) executing a read operation checks mode setting information 120-3 to identify whether global environment 102 is set to mode B (e.g., a transactional memory usage mode) as opposed to mode A (e.g., a non-transactional memory usage mode). If so, the given process aborts. Additionally, in step 208, the given process checks whether there is a corresponding segment lock (e.g., a leftover lock existing from a process operating in mode B as will be discussed later in this specification) a present for a respective portion of data to be read from shared data 125. For example, the given process looks at respective lock bit information 230 associated with the segment (or portion thereof) to be read. If there is a lock present, another process is currently modifying the segment and the given process aborts. Otherwise, after passing these above tests, processing continues as follows. [0062] When carrying out such a read operation as illustrated in step 210, process 140-1 first checks whether a respective global lock bit 120-2 has been set by another process currently modifying shared data 125. If the global lock bit 120-2 is not set, the respective process fetches and stores a current value of global version information 120-1 in its local repository 110-1. For example, the version information at a time of this first read may be 000145. The process 140-1 stores this instantaneous data value of 000145 in its local repository 110-1. Note that the local repository can be a specific location of shared data assigned for use by only a respective process. [0063] In step 215, the given process performs a read of a portion (e.g., one or more locations) of shared data 125. In one embodiment, the given process can fetch the global version information again after performing the read of data to verify whether or not to abort a respective transaction. Also, note that an ordering of steps 210 and 215 can be reversed depending according to different embodiments. [0064] The process 140-1 eventually performs subsequent reads as indicated in step 220. For each subsequent read of shared data 125, the process verifies that the global lock bit 120-2 is not set by another one of the multiple processes 140. Additionally, the process 140-1 checks whether a current value of the version information 120-1 has been modified since the last read. In one embodiment, a transactional load associated with step 220 can be carried out by first fetching data from memory and thereafter fetching (& validating) the version information based on a comparison technique as discussed above. [0065] For example, after obtaining a current value of global version information 120-1 after a respective read, the process 140-1 compares an instantaneous data value of the retrieved global version information 120-1 (at a time of the subsequent read) to the data value stored in local repository 110-1. If they match (e.g., the instantaneous data value of the version information 120-2 is still 000145), the process 140-1 can continue executing a respective transaction. If not, such as when the instantaneous data value of the version information 120-1 is 000146 indicating that another process modified shared data 125, then the process 140-1 aborts the transaction and retries from the start. [0066] Note that in one embodiment, each of the processes 140 increments a respective value of the version information 120-1 upon committing corresponding results of a transaction to shared data 125. In this latter case resulting in abortion, any intermediate data values generated by a respective processing thread prior to abortion are disregarded. [0067] Also, as mentioned, steps 210 through 220 can be carried out in any order according to other embodiments herein. For example, in one embodiment, a transactional load can be carried out by first fetching and validating the global version information and thereafter retrieving data from memory. For a respective first load transaction, the order of operation can include first fetching the shared data, then fetching the version information, for storage in the local repository associated with the given process. [0068] Each of the processes 140 can also perform a write operation 205-2. A write operation involves modifying contents of shared data 125 during a so-called write phase. At the write-time in M4, if there were any prior writes in the thread's transaction, then the current thread must hold the write-lock. In this case the commit operation is a no-op. An M4 operation is guaranteed to commit normally (no aborts) if the thread manages to acquire (and validate) the M4 lock at the time of the first transactional write. [0069] For example, in step 255, a respective process 140-1 can initially verify that current global version information 120-1 matches the data value of version information 120-1 stored in its local repository 110-1. As discussed above, the process can abort itself if the version information changes during a course of executing a respective processing thread or transaction. [0070] The process 140-1 also can retrieve the global lock bit 120-2 to identify whether another process currently has a lock on shared data 125. If the lock bit is set, process 140-1 aborts a respective transaction. The process 140-1 also can retrieve mode setting information 120-3 to detect a current mode. If the global environment 102 is currently set to mode B, then the process 140-1 can abort itself. [0071] If the global lock bit is not set and the mode is set to mode A, the process 140-1 sets the global lock bit 120-2 to an active state to obtain the lock over shared data 125. Once a lock is obtained, no other processes can modify contents of shared data 125. [0072] In step 256, upon each store, the process 140-1 checks if there is a mode B type of lock on a portion of shared data 125 to be modified. In one embodiment, if the process 140-1 plans to modify contents of segment 210-1, the process 140-1 verifies that lock bit 230-1 is not set; if the process 140-1 plans to modify contents of segment 210-2, the process 140-1 verifies that lock bit 230-2 is not set, and so on. If necessary, the process 140-1 can spin to obtain the lock over shared data 125. [0073] After obtaining a respective lock in step 260, the process 140-1 initiates modification of shared data 125 according to a respective transaction outcome. [0074] In step 265, after modifying shared data 125 the process 140-1 updates the global version information 120-1 with a new value (e.g., to a data value of 000146) and sets the global lock bit 120-2 to an inactive state (e.g., the process releases a respective lock where the lock bit and version information are co-located in a single lock-word). In one embodiment, the process 140-1 simultaneously sets the global lock bit 120-2 low at a same time of updating the global version information 120-1. More Details Associated with Mode A (e.g., M4 Mode) [0075] In the context of a general embodiment herein, metadata 135 enables each of processes 140 to identify whether content associated with shared data 125 has been “locked” (e.g., via checking lock information 120-2). Additionally, metadata 135 enables the processes 140 to identify whether any portions of shared data 125 have changed during execution of a respective transaction (e.g., via use of version information 120-1). [0076] In one embodiment, version information 120-2 and version information 120-1 form lock-word. A lock-word is a shared global variables that contain version information 120-1 and a lock-bit information 120-2. A given globally accessible shared data structure (e.g., segment) is associated with only one lock-word. We say that lock-word protects or guards that data structure. The lock-word is meta-data that moderates access to the shared data structure. [0077] Each of processes 140 competes to obtain a respective lock on shared data 125. To obtain a lock preventing other processes from modifying shared data 125, a given process writes a logic one to a respective lock bit of lock information 120-2. When set to a logic one, processes 140 other than a respective process holding the lock are, by protocol, unable to modify contents of shared data 125. Critically, M4 is a cooperative protocol. Threads use M4 to avoid races or undesirable interference. It's cooperative in the sense that all threads accessing the shared data will, by convention, use appropriate access protocol. Nothing would stop an errant from accessing the data. Upon release of a lock based on a respective process setting the lock bit to a logic zero, the processes 140 can again compete to obtain a lock on shared data 125. [0078] In addition to lock information 120-2, metadata 135 includes version information 120-1 that is updated each time a respective process modifies contents of shared data 125. Accordingly, the processes 140 can monitor the version information to identify whether shared data 125 has been modified during a respective execution of a processing transaction (e.g., multiple software instructions). [0079] In one embodiment, each of processes 140 stores an instantaneous data value (e.g., sampled version value or sampled version number) of current version information 120-1 in a respective local repository 110 at least some time during a respective execution of a transaction. Throughout this specific, the instantaneous data value is defined as a current value of the version information 120-1 at a time of reading. As discussed throughout this specific, this value changes over time as each of the processes 140 modifies the respective shared data 125 and updates this version information 120-1 to a new value. [0080] Some time after an initial load of version information 120-1 associated with shared data 125, a respective process compares a data value associated with version information 120-1 in global environment 102 to the data value previously stored in its local repository 110 to identify whether another process 140 modified contents of shared data 125. As will be discussed further in this specification, a respective process can abort itself and try again if version information 120-1 changes during respective execution. [0081] Accordingly, the above algorithm includes a single lock that protects all transactions. Conceptually, the technique herein (e.g., a so-called M4 algorithm) is a read-write lock that provides automatic and transparent upgrade from read state to read-write state at the time of the 1st store in a transaction. The lock consists of a version field with the low-order bit serving as a write-lock. We describe M4 here as a specific example of a locking algorithm it may be beneficial to switch with, but anyone skilled in the art will know how to make the described switching mechanism work for another mechanism that implements transactions by having a single lock protect all executed transactions. [0082] One embodiment of the M4 algorithm works as follows. We assume a read-write lock implemented using a single word, which we call the “lockword” (e.g., lock information 120-2) with a version field (e.g., version information 120-1). [0000] 1. According to one embodiment, on a transactional load: [0083] (a) if the loading thread holds the write-lock the load simply executes the load as normal. [0084] (b) If the thread doesn't hold the write-lock it loads the lockword. [0085] i. If the lockword indicates that some other thread holds the write-lock, the reading thread aborts immediately and retries. [0086] ii. Otherwise: [0087] A. if this is the 1 st transactional load, the thread saves the fetched lockword (which contains the version subfield) into a thread-local variable and then executes the requested load. [0088] B. If this is not the 1st transactional load the thread checks the just-loaded version against the version saved in the thread's thread-local variable. If they disagree then the thread aborts immediately, otherwise the load executes as normal. [0089] Note that the last two steps A and B can be modified to carry yet another embodiment herein. For example, in one embodiment, a transactional load can be carried out by first fetching data from memory and thereafter fetching (& validating) the version information. However, if this is a first load transaction, then the order of operation can include fetching the version information first, then fetching the shared data, and then fetching the version information again. [0000] 2. According to one embodiment, on a transactional store: [0090] (a) if the storing thread already holds the write-lock, the store executes normally. [0091] (b) if the storing thread does not hold the write-lock: [0092] i. If there was a previous transactional load, the thread attempts to CAS (atomic Compare and Swap instruction) the write-lock bit with the previously observed version. If the CAS is successful the thread now holds the write-lock and the store executes normal. If the CAS fails then the transaction aborts immediately. [0093] ii. If there was no prior transactional load in this transaction the thread loops, trying to toggle the low-order write-lock bit in the lockword from 0 to 1. Once the thread has acquired the write-lock it executes the store or write operation. [0094] According to the M4 technique, there's no need to track read-sets or write-sets so the overhead is quite low. A read set is a set of data locations read during a transaction. A write set is a set of data locations written to during a transaction as discussed in related applications. After a thread acquires the write-lock, it can simply store directly into the global fields without the need to save stores in a log file (e.g., a log file used for undo puporses). Likewise, loads don't need to look-aside into the store-log. Once the write-lock is acquired the operation can't abort. [0095] In a related manner (since there's only one lock) there's no possibility of livelock or deadlock. A classic read-write lock can't normally be upgraded or promoted from read to read-write state without the application having been explicitly and intentionally written to refresh any cached values seen during the read phase. That's because the read-write lock implementation might need to drop the lock to avoid deadlock during the upgrade to a read-write state. The M4 technique as described herein provides for automatic and transparent upgrade from a read-only lock to a read-write lock. M4 tends to be more profitable (e.g., more efficient) in circumstances where read-parallelism exists. [0096] Consider, for example, a hash table where most operations are queries. According to M4, pure readers may operate completely in parallel. Furthermore, the readers do not need to store into a shared location to acquire a lock. Note that traditional SMP systems use snoop- or directory-based cache coherency protocols, concurrent sharing of or access to cache lines tend to incur high latency and consume precious coherency bandwidth if stores to the shared line are frequent. Pure read sharing, however, is typically inexpensive. [0097] Furthermore, A number of variations are possible and it'll pay to enumerate them in the application. To keep things straight I'll call them Validate-after-each-ld (VAL) and validate-at-commit-time (VAC). [0098] Transactional Load in VAL-mode: if (the loading thread holds the write lock) then execute the load of the global variable as normal else if (this is 1st load in the thread's txn) then load lock-word if (lock-word lock-bit is set) then optionally spin, waiting for lock-bit to clear abort current txn else save previously fetched lock-word version into thread-local txn version variable execute the load of the global variable placing result in thread-local temporary variable load the lock-word if (the lock-word's lock-bit is set OR the lock-word's version # differs from the thread's txn version variable) then abort the txn. return the temporary variable (previously fetched value) as the result of the txn load [0099] Transactional load in VAC-mode: if (the loading thread holds the write lock) then execute the load of the global variable as normal else if (this is 1st load in the thread's txn) then load lock-word if (lock-word lock-bit is set) then optionally spin, waiting for lock-bit to clear abort current txn else save lock-word version into thread-local txn version variable execute the load of the global variable as normal [0100] In VAL-mode we don't need to re-check the version at commit-time whereas we must validate the version at commit-time in VAC-mode. The differences between VAC and VAL boil down to when and where do we validate that the saved t�n version remains unchanged. VAC mode moves validation from the t�n LD operation to the commit operator and defers validation until commit-time. Recall that validation tells us if the previously read global variables are mutually consistent. VAL mode is one embodiment as it doesn't admit so-called “zombie” transactions. A zombie is a transaction that has read inconsistent data and is doomed, but has yet to validate and abort. Zombies can misbehave, dereferencing illegal pointers, generating divide-by-zero traps, or entering infinite loops. VAC-mode is slightly more efficient, but admits zombies. Zombies require “containment” to prevent their misbehavior from effecting the rest of the system. [0101] Note that VAL- and VAC-mode define two ends of a spectrum. Another valid scheme is to validate periodically during the transaction—less frequently than at every t�n load, but more frequently than just at commit-time. Critically, VAL mode is still more efficient than the read-set validation performed by previous software transactional memory implementations (STMs). [0102] FIGS. 4 through 6 are diagrams illustrating details of respective read-sets 150 and write-sets 160 associated with a distributed type of lock mode (e.g., mode B) according to embodiments herein. In general, a distributed type of lock mode according to embodiments herein includes one in which each of multiple processes 140 compete to simultaneously obtain different locks and modify respective different portions of shared data 125. [0103] As discussed above, to carry out execution of processing threads in mode B (e.g., a transactional locking mode), respective processes 140 utilize respective read-sets 150, respective write-sets 160, and segments of shared data 210, segment version information 220, and segment lock bit information 230. When in mode B, each of multiple processes 140 operate in a similar way as discussed below. [0104] More specifically, as shown in FIG. 4, a sample process such as process 140-1 executes transaction 351 (e.g., a set of software instructions). Read-set 150-1 stores retrieved version information 320-1, retrieved version information 320-2, . . . , retrieved version information 320-K associated with corresponding data values (or segments) accessed from shared data 125 during execution of transaction 351. Accordingly, the process 140-1 can keep track of version information associated with any globally accessed data. [0105] Write-set 160-1 stores shared variable identifier information 340 (e.g., address information, variable identifier information, etc.) for each respective globally shared variable that is locally modified during execution of the transaction 351. Local modification involves maintaining and modifying locally used values of shared variables in write-set 160-1 rather than actually modifying the global variables during execution of transaction 351. As discussed above and as will be further discussed, the process 140-1 attempts to globally commit information in write-set 160-1 to shared data 125 upon completion of transaction 351. In the context of the present example, process 140-1 maintains write-set 160-1 to include i) shared variable identifier information 340-1 (e.g., segment or variable identifier information) of a respective variable accessed from shared data 125 and corresponding locally used value of shared variable 350-1, ii) shared variable identifier information 340-2 (e.g., segment or variable identifier information) of a variable or segment accessed from shared data 125 and corresponding locally used value of shared variable 350-2, an so on. Accordingly, process 140-1 uses write-set 160-1 as a scratch-pad to carry out execution of transaction 351 and keep track of locally modified variables and corresponding identifier information. [0106] FIG. 5 is a flowchart illustrating a more specific use of read-sets 150, write-sets 160, version information 220, and lock information 230 according to embodiments herein. In general, flowchart 400 indicates how each of multiple processes 140 utilizes use of read-sets 150 and write-sets 160 while carrying out a respective transaction. [0107] Step 405 indicates a start of a respective transaction. As previously discussed, a transaction can include a set of software instructions indicating how to carry out one or more computations using shared data 125. [0108] In step 410, a respective process 140 executes an instruction associated with the transaction identifying a specific variable in shared data 125. [0109] In step 415, the respective process checks whether the variable exists in its respective write-set 160. If the variable already exists in its respective write-set 160 in step 420, then processing continues at step 440 in which the respective process 140 fetches a locally maintained value from its write-set 160. [0110] If a locally stored data value associated with the variable does not already exist in its respective write-set 160 (e.g., because the variable was never fetched yet and/or modified locally) as identified in step 415, then processing continues at step 420 in which the respective process 140 attempts to globally fetch a data value associated with the variable based on a respective access to shared data 125. For example, as further indicated in step 425, the process 140 checks whether the variable to be globally fetched is locked by another process. As previously discussed, another process may lock variables, segments, etc. of shared data 125 to prevent others from accessing the variables. Globally accessible lock information 230 (e.g., a single bit of information) in metadata 135 indicates which variables have been locked for use. [0111] If an active lock is identified in step 425, the respective process initiates step 430 to abort and retry a respective transaction or initiate execution of a so-called back-off function to access the variable. In the latter instance, the back-off function can specify a random or fixed amount of time for the process to wait before attempting to read the variable again with hopes that a lock will be released. The respective lock on the variable may be released by during a second or subsequent attempt to read the variable. [0112] If no lock is present on the variable during execution of step 425, the respective process initiates step 435 to globally fetch a data value associated with the specified variable from shared data 125. In addition to globally accessing the data value associated with the shared variable, the respective process retrieves version information 220 associated with the globally fetched variable. The process stores retrieved version information associated with the variable in its respective read-set 150 for later use during a commit phase. [0113] In step 445, the respective process utilizes the fetched data value associated with the variable to carry out one or more computations associated with the transaction. Based on the paths discussed above, the data value associated with the variable can be obtained from either write-set 160 or shared data 125. [0114] In step 450, the process performs a check to identify whether use of the fetched variable (in the transaction) involve modifying a value associated with the fetched variable. If so, in step 455, the process modifies the locally used value of shared variable 350 in write-set 160. The respective process skips executing step 455 if use of the variable (as specified by the executed transaction) does not involve modification of the variable. [0115] In step 460, the respective process identifies whether a respective transaction has completed. If not, the process continues at step 410 to perform a similar loop for each of additional variables used during a course of executing the transaction. If the transaction has completed in step 460, the respective process continues at step 500 (e.g., the flowchart 500 in FIG. 5) in which the process attempts to globally commit values in its write-set 160 to globally accessible shared data 125. [0116] Accordingly, in response to identifying that a corresponding data value associated with one or more shared variable was modified during execution of the transaction, a respective process can abort a respective transaction in lieu of modifying a data value associated with shared data 125 and initiate execution of the transaction again at a later time to produce attempt to produce a respective transaction outcome. [0117] FIG. 6 is a flowchart 500 illustrating a technique for committing results of a transaction to shared data 125 according to embodiments herein. Up until his point, the process executing the respective transaction has not initiated any locks on any shared data yet although the process does initiate execution of computations associated with accessed shared data 125. Waiting to obtain locks at the following “commit phase” enables other processes 140 to perform other transactions in parallel because a respective process initiating storage of results during the commit phase holds the locks for a relatively short amount of time. In [0118] In step 505, the respective process that executed the transaction attempts to obtain locks associated with each variable in its write-set 160. For example, the process checks whether lock information in metadata 135 indicates whether the variables to be written to (e.g., specific portions of globally accessible shared data 125) are locked by another process. The process initiates locking the variables (or segments as the case may be) to block other process from using or locking the variables. In one embodiment, a respective process attempts to obtain locks according to a specific ordering such as an order of initiating local modifications to retrieved shared variables during execution of a respective transaction, addresses associated with the globally shared variables, etc. [0119] If all locks cannot be immediately obtained in step 510, then the process can abort and retry a transaction or initiate a back-off function to acquire locks associated with the variables that are locally modified during execution of the transaction. [0120] After all appropriate locks have been obtained by writing respective lock information 230, processing continues at step 520 in which the process obtains the stored version information associated with variables read from shared data 125. As previously discussed, the version information 230 of metadata 135 indicates a current version of the respective variables at a time when they were read during execution of the transaction. [0121] In step 525, the respective process compares the retrieved version information in the read-set 150 saved at a time of accessing the shared variables to the current globally available version information 220 from metadata 135 for each variable in the read-set 150. [0122] In step 530, if the version information is different in step 525, then the process acknowledges that another process modified the variables used to carry out the present transaction. Accordingly, the process releases any obtained locks and retries the transaction again. This prevents the respective process from causing data corruption. [0123] In step 535, if the version information is the same in step 525, then the process acknowledges that no other process modified the variables used to carry out the present transaction. Accordingly, the process can initiate modification of shared data to reflect the data values in the write-set 160. This prevents the respective process from causing data corruption during the commit phase. [0124] Finally, in step 540, after updating the shared data 125 with the data values in the write-set 160, the process updates version information 220 associated with modified variables or segments and releases the locks. The locks can be released in any order or in a reverse order relative to the order of obtaining the locks. [0125] Note that during the commit phase as discussed above in flowchart 500, if a lock associated with a location in the process's write-set 160 also appears in the read-set 150, then the process must atomically: a) acquire a respective lock and b) validate that current version information associated with the variable (or variables) is the same as the retrieved version information stored in the read-set 150. In one embodiment, a CAS (Compare and Swap) operation can be used to accomplish both a) and b). [0126] Also, note that each of the respective processes 140 can be programmed to occasionally, periodically, sporadically, intermittently, etc. check (prior to the committal phase in flowchart 500) whether current version information 220 in metadata 135 matches retrieved version information in its respective read-set 150 for all variables read from shared data 125. Additionally, each of the respective processes 140 can be programmed to also check (in a similar way) whether a data value and/or corresponding segment has been locked by another process prior to completion. If a change is detected in the version information 220 (e.g., there is a difference between retrieved version information 320 in read-set 150 and current version information 220) and/or a lock is implemented on a data value or segment used by a given process, the given process can abort and retry the current transaction, prior to executing the transaction to the commit phase. Early abortion of transactions doomed to fail (because of an other process locking and modifying) can increase overall efficiency associated with parallel processing. [0127] Use of version information and lock information according to embodiments herein can prevent corruption of data. For example, suppose that as an alternative to the above technique of using version information to verify that relied upon information (associated with a respective transaction) has not changed by the end of a transaction, a process reads data values (as identified in a respective read-set) from shared data 125 again at commit time to ensure that the data values are the same as were when first being fetched by the respective process. Unfortunately, this technique can be misleading and cause errors because of the occurrence of race conditions. For example, a first process may read and verify that a globally accessible data value in shared data 125 has not changed while soon after (or at nearly the same time) another respective process modifies the globally accessible data value. This would result in corruption if the first process committed its results to shared data 125. The techniques herein are advantageous because use of version and lock information in the same word prevents corruption as a result of two different processes accessing the word at the same or nearly the same time. [0128] FIG. 7 is a diagram summarizing respective read and write operations associated with a so-called distributed type of lock mode (e.g., mode B) according to embodiments herein. Because a type of lock mode can change during execution, processes 140 operate in a slightly different manner than when a respective processing environment supports only a distributed type of lock mode. [0129] For example, in step 706 of read operation 705-1, a given process verifies that there is no lock on a segment of shared data to be accessed. [0130] In step 710, the process performs a read of content from a segment of shared data. During execution of a respective transaction, the given process creates a respective read-set 150 and write-set 160 as discussed above. [0131] In step 715, the given process checks the global version information 120-1 and the mode setting information 120-3. If the current mode setting of global environment 102 is mode A or there is a change in the global version information 120-1, then the given process aborts. Otherwise processing can continue until the given process commits its results to memory via write operation 705-2. [0132] In step 785, during a respective write phase, if no stores were encountered during a transaction, the given process reads mode setting information 120-3. If the given process detects a mode change or version information change (e.g., in global version information 120-1), the given process aborts and attempts re-execution of the transaction. Otherwise, processing continues in the following step. [0133] In step 790, if the given process encounters one or more store instructions, then the given process completes execution via mode B. Upon completion of acquiring locks of segments to be modified, the given process checks the central register (e.g., a single register including global version information 120-1, global lock bit 120-2, and mode setting information 120-3). If the central register indicates that a current mode setting is mode A or there is a change with respect to the global version information 120-1 and the global environment 102 is set to mode B, then the given process aborts the transaction. Otherwise, the given process modifies segments of shared data 125 as discussed above in FIG. 4-6. [0134] FIG. 8 is a block diagram illustrating an example computer system 610 (e.g., an architecture associated with computer environment 100) for executing parallel processes 140 (e.g., processing threads) and other related processes according to embodiments herein. Computer system 610 can be a computerized device such as a personal computer, workstation, portable computing device, console, network terminal, processing device, etc. [0135] As shown, computer system 610 of the present example includes an interconnect 111 that couples a memory system 112 storing shared data 125 (e.g., globally accessible shared data), metadata 135 (e.g., global version information 120-1, global lock bit 120-2, mode setting information 120-3, segment version information 220, and segment lock bit information 230), one or more processors 113 executing processes 140 (e.g., process 140-1, process 140-2, . . . , process 140-M), an I/O interface 114, and a communications interface 115. Peripheral devices 116 (e.g., one or more optional user controlled devices such as a keyboard, mouse, display screens, etc.) can couple to processor 113 through I/O interface 114. I/O interface 114 also enables computer system 610 to access repository 180 (that also potentially stores shared data 125 and/or metadata 135). Communications interface 115 enables computer system 610 to communicate over network 191 to transmit and receive information from different remote resources. [0136] Note that each of processes 140 can be executed by the same processor 113 supporting parallel processing of processes 140 or executed by a different set of respective processors executing one or more of processes 140. In one embodiment, each of processes 140 executes a respective transaction associated with the same overall application. However, the processes 140 can be associated with different respective applications. [0137] Further note that functionality associated with processes 140 and/or computer environment 100 can be embodied as software code such as data and/or logic instructions (e.g., code stored in the memory or on another computer readable medium such as a disk) that support functionality according to different embodiments described herein. Alternatively, the functionality associated with processes 140 can be implemented via hardware or a combination of hardware and software code. Processor 113 can be one or multiple separate processors executing multiple processing threads. [0138] It should be noted that, in addition to the processes 140 themselves, embodiments herein include a respective application and/or set of instructions to carry out processes 140. Such a set of instructions associated with processes 140 can be stored on a computer readable medium such as a floppy disk, hard disk, optical medium, etc. The set of instruction can also be stored in a memory type system such as in firmware, RAM (Random Access Memory), read only memory (ROM), etc. or, as in this example, as executable code. [0139] Collective attributes associated with processes 140, global environment 102, and computer environment 100, etc. will now be discussed with respect to flowcharts in FIGS. 9-11. For purposes of this discussion, global environment 102, processes 140 and/or computer environment 100 can execute or carry out the steps described in the respective flowcharts. Note that the steps in the below flowcharts need not always be executed in the order shown. [0140] Now, more particularly, FIG. 9 is a flowchart 900 illustrating a technique supporting execution of parallel transactions in computer environment 100 according to an embodiment herein. Note that techniques discussed in flowchart 900 overlap and summarize some of the techniques discussed above. [0141] In step 910, the computer system 610 herein maintains an environment to execute multiple processing threads (e.g., processes 140) in parallel. [0142] In step 920, during execution of multiple processing threads, the computer system 610 enables switching a manner of the execution between multiple types of lock modes including a centralized lock mode in which the multiple processing threads compete to obtain a coarse-grained lock over respective shared data and a distributed lock mode in which the multiple processing threads compete to obtain finer-grained locks over sub-portions of the respective shared data. [0143] FIG. 10 is a flowchart 1000 illustrating a technique supporting parallel execution of processes 140 according to embodiments herein. Note that techniques discussed in flowchart 1000 overlap with the techniques discussed above in the previous figures. [0144] In step 1010, computer system 610 maintain an environment to execute multiple processing threads in parallel [0145] In sub-step 1015 of step 1010, the computer system 610 implements a centralized lock mode to include global version information 120-1 and a respective global lock bit 120-2 accessible by the multiple processing threads. The global version information 120-1 gets updated by a respective processing thread each time a respective processing thread modifies contents of the respective shared data. The respective global lock bit 120-2 enables each of the multiple processing threads to obtain a lock over the respective shared data 125 preventing other processing threads from modifying the contents of the shared data 125. [0146] In sub-step 1020 of step 1010, the computer system 610 implements a distributed lock mode that includes corresponding segment version information 220 and a respective segment lock bit 230 for each of multiple segments of the respective shared data 125. The corresponding segment version information 220 is updated by a respective processing thread each time the respective processing thread modifies contents of the corresponding segment of the respective shared data. The respective segment lock bit 230 enables each of the multiple processing threads to obtain a lock over the corresponding segment of the respective shared data preventing other processing threads from modifying the contents of the corresponding segment. [0147] In step 1025, a lock contention monitor 122 monitors a level of contention of the multiple processing threads (i.e., processes 140) competing to obtain one or more locks and, thereafter, modify contents of shared data 125. [0148] In step 1030, a mode controller 124 detect that one of a centralized lock mode and a distributed lock mode is more efficient for carrying out the execution of the multiple processing threads. [0149] In step 1035, during execution of the multiple processing threads, the mode controller 124 switches a manner of the execution between the multiple types of lock modes. For example, the mode controller 124 switches between the centralized lock mode in which the multiple processing threads compete to obtain a coarse-grained lock over respective shared data and the distributed lock mode in which the multiple processing threads compete to obtain finer-grained locks over sub-portions of the respective shared data. [0150] As discussed above, techniques herein are well suited for use in applications such as those that support parallel processing threads in the same processor or in different processors. However, it should be noted that configurations herein are not limited to such use and thus configurations herein and deviations thereof are well suited for use in other environments as well. [0151] While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application as defined by the appended claims. Such variations are covered by the scope of this present disclosure. As such, the foregoing description of embodiments of the present application is not intended to be limiting. Rather, any limitations to the invention are presented in the following claims. Note that the different embodiments disclosed herein can be combined or utilized individually with respect to each other. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5301290 *Mar 14, 1990Apr 5, 1994International Business Machines CorporationMethod for minimizing lock processing while ensuring consistency among pages common to local processor caches and a shared external storeUS5596754 *Oct 27, 1995Jan 21, 1997Digital Equipment CorporationMethod for performing private lock managementUS5649200 *Dec 2, 1996Jul 15, 1997Atria Software, Inc.Dynamic rule-based version control systemUS5950199 *Jul 11, 1997Sep 7, 1999International Business Machines CorporationParallel file system and method for granting byte range tokensUS5956731 *Apr 23, 1997Sep 21, 1999Oracle CorporationSharing snapshots for consistent readsUS5987506 *May 2, 1997Nov 16, 1999Mangosoft CorporationRemote access and geographically distributed computers in a globally addressable storage environmentUS6101590 *Oct 10, 1995Aug 8, 2000Micro Unity Systems Engineering, Inc.Virtual memory system with local and global virtual address translationUS6148377 *Nov 22, 1996Nov 14, 2000Mangosoft CorporationShared memory computer networksUS6393437 *Jan 27, 1998May 21, 2002Microsoft CorporationWeb developer isolation techniquesUS6757893 *Dec 17, 1999Jun 29, 2004Canon Kabushiki KaishaVersion control system for software codeUS6810470 *Aug 14, 2000Oct 26, 2004Ati Technologies, Inc.Memory request interlockUS6826570 *Jul 18, 2000Nov 30, 2004International Business Machines CorporationDynamically switching between different types of concurrency control techniques to provide an adaptive access strategy for a parallel file systemUS7313794 *Jan 30, 2003Dec 25, 2007Xilinx, Inc.Method and apparatus for synchronization of shared memory in a multiprocessor systemUS7395263 *Oct 12, 2005Jul 1, 2008International Business Machines CorporationRealtime-safe read copy update with lock-free readersUS7467378 *Feb 9, 2004Dec 16, 2008Symantec CorporationSystem state rollback after modification failureUS7536517 *Jul 29, 2005May 19, 2009Microsoft CorporationDirect-update software transactional memoryUS20040117531 *Dec 9, 2003Jun 17, 2004Mckenney Paul E.Adaptive reader-writer lockUS20050038961 *Aug 10, 2004Feb 17, 2005Chao-Wu ChenCache and memory architecture for fast program space accessUS20060106996 *Nov 15, 2004May 18, 2006Ahmad Said AUpdating data shared among systemsUS20060161919 *Dec 23, 2004Jul 20, 2006Onufryk Peter ZImplementation of load linked and store conditional operationsUS20060236039 *Apr 19, 2005Oct 19, 2006International Business Machines CorporationMethod and apparatus for synchronizing shared data between components in a groupUS20070124546 *Nov 29, 2005May 31, 2007Anton BlanchardAutomatic yielding on lock contention for a multi-threaded processor* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7362762 *Jul 16, 2004Apr 22, 2008Cisco Technology, Inc.Distributed packet processing with ordered locks to maintain requisite packet orderingsUS7626987Nov 12, 2003Dec 1, 2009Cisco Technology, Inc.Using ordered locking mechanisms to maintain sequences of items such as packetsUS7630376Apr 3, 2008Dec 8, 2009Cisco Technology, Inc.Distributed packet processing with ordered locks to maintain requisite packet orderingsUS7664897Dec 1, 2005Feb 16, 2010Cisco Technology Inc.Method and apparatus for communicating over a resource interconnectUS7739426Oct 31, 2006Jun 15, 2010Cisco Technology, Inc.Descriptor transfer logicUS7861093 *Aug 30, 2006Dec 28, 2010International Business Machines CorporationManaging data access via a loop only if changed locking facilityUS7890707 *Jun 27, 2007Feb 15, 2011Microsoft CorporationEfficient retry for transactional memoryUS7890725 *Jul 9, 2007Feb 15, 2011International Business Machines CorporationBufferless transactional memory with runahead executionUS8139488May 30, 2008Mar 20, 2012Cisco Technology, Inc.Cooperative flow locks distributed among multiple componentsUS8161247Jun 26, 2009Apr 17, 2012Microsoft CorporationWait loss synchronizationUS8200947 *Mar 24, 2008Jun 12, 2012Nvidia CorporationSystems and methods for voting among parallel threadsUS8214625 *Nov 26, 2008Jul 3, 2012Nvidia CorporationSystems and methods for voting among parallel threadsUS8229907Jun 30, 2009Jul 24, 2012Microsoft CorporationHardware accelerated transactional memory system with open nested transactionsUS8250331Jun 26, 2009Aug 21, 2012Microsoft CorporationOperating system virtual memory management for hardware transactional memoryUS8356166Jun 26, 2009Jan 15, 2013Microsoft CorporationMinimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriersUS8370577Jun 26, 2009Feb 5, 2013Microsoft CorporationMetaphysically addressed cache metadataUS8384736Oct 14, 2009Feb 26, 2013Nvidia CorporationGenerating clip state for a batch of verticesUS8402218Dec 15, 2009Mar 19, 2013Microsoft CorporationEfficient garbage collection and exception handling in a hardware accelerated transactional memory systemUS8484235Mar 28, 2011Jul 9, 2013International Business Machines CorporationDynamically switching the serialization method of a data structureUS8489864Jun 26, 2009Jul 16, 2013Microsoft CorporationPerforming escape actions in transactionsUS8533440Dec 15, 2009Sep 10, 2013Microsoft CorporationAccelerating parallel transactions using cache resident transactionsUS8538977Mar 5, 2012Sep 17, 2013International Business Machines CorporationDynamically switching the serialization method of a data structureUS8539465Dec 15, 2009Sep 17, 2013Microsoft CorporationAccelerating unbounded memory transactions using nested cache resident transactionsUS8542247Jul 17, 2009Sep 24, 2013Nvidia CorporationCull before vertex attribute fetch and vertex lightingUS8564616Jul 17, 2009Oct 22, 2013Nvidia CorporationCull before vertex attribute fetch and vertex lightingUS8631173 *Mar 18, 2008Jan 14, 2014Kabushiki Kaisha ToshibaSemiconductor deviceUS8645650 *Jan 29, 2010Feb 4, 2014Red Hat, Inc.Augmented advisory lock mechanism for tightly-coupled clustersUS8688951Jul 20, 2012Apr 1, 2014Microsoft CorporationOperating system virtual memory management for hardware transactional memoryUS8706982 *Dec 30, 2007Apr 22, 2014Intel CorporationMechanisms for strong atomicity in a transactional memory systemUS8812467 *May 25, 2012Aug 19, 2014Fuji Xerox Co., Ltd.Information processing apparatus and computer readable medium for performing history cancellation processingUS8812796Jun 26, 2009Aug 19, 2014Microsoft CorporationPrivate memory regions and coherence optimizationsUS8930644May 2, 2008Jan 6, 2015Xilinx, Inc.Configurable transactional memory for synchronizing transactionsUS8943502 *Mar 15, 2010Jan 27, 2015International Business Machines CorporationRetooling lock interfaces for using a dual mode reader writer lockUS8976195Oct 14, 2009Mar 10, 2015Nvidia CorporationGenerating clip state for a batch of verticesUS9047139 *Jun 27, 2008Jun 2, 2015Microsoft Technology Licensing, LlcPrimitives for software transactional memoryUS9092253Dec 15, 2009Jul 28, 2015Microsoft Technology Licensing, LlcInstrumentation of hardware assisted transactional memory systemUS20050100017 *Nov 12, 2003May 12, 2005Cisco Technology, Inc., A California CorporationUsing ordered locking mechanisms to maintain sequences of items such as packetsUS20050220112 *Jul 16, 2004Oct 6, 2005Cisco Technology, Inc.Distributed packet processing with ordered locks to maintain requisite packet orderingsUS20080059808 *Aug 30, 2006Mar 6, 2008International Business Machines CorporationManaging data access via a loop only if changed locking facilityUS20080181229 *Apr 3, 2008Jul 31, 2008Cisco Technology, Inc. A Corporation Of CaliforniaDistributed Packet Processing With Ordered Locks To Maintain Requisite Packet OrderingsUS20080244240 *Mar 18, 2008Oct 2, 2008Kabushiki Kaisha ToshibaSemiconductor deviceUS20090007070 *Jun 27, 2007Jan 1, 2009Microsoft CorporationEfficient retry for transactional memoryUS20090019247 *Jul 9, 2007Jan 15, 2009Praun Christoph VonBufferless Transactional Memory with Runahead ExecutionUS20090172306 *Dec 31, 2007Jul 2, 2009Nussbaum Daniel SSystem and Method for Supporting Phased Transactional Memory ModesUS20090172317 *Dec 30, 2007Jul 2, 2009Bratin SahaMechanisms for strong atomicity in a transactional memory systemUS20090276599 *Nov 5, 2009Xilinx, Inc.Configurable transactional memory for synchronizing transactionsUS20090296580 *May 30, 2008Dec 3, 2009Cisco Technology, Inc., A Corporation Of CaliforniaCooperative Flow Locks Distributed Among Multiple ComponentsUS20090327291 *Jun 27, 2008Dec 31, 2009Microsoft CorporationPrimitives for software transactional memoryUS20100250507 *Mar 31, 2009Sep 30, 2010Microsoft CorporationEnumeration of a concurrent data structureUS20100332538 *Jun 30, 2009Dec 30, 2010Microsoft CorporationHardware accelerated transactional memory system with open nested transactionsUS20100332716 *Jun 26, 2009Dec 30, 2010Microsoft CorporationMetaphysically addressed cache metadataUS20100332753 *Jun 26, 2009Dec 30, 2010Microsoft CorporationWait loss synchronizationUS20100332771 *Jun 26, 2009Dec 30, 2010Microsoft CorporationPrivate memory regions and coherence optimizationsUS20100332807 *Jun 26, 2009Dec 30, 2010Microsoft CorporationPerforming escape actions in transactionsUS20100332808 *Jun 26, 2009Dec 30, 2010Microsoft CorporationMinimizing code duplication in an unbounded transactional memory systemUS20110145304 *Dec 15, 2009Jun 16, 2011Microsoft CorporationEfficient garbage collection and exception handling in a hardware accelerated transactional memory systemUS20110145498 *Jun 16, 2011Microsoft CorporationInstrumentation of hardware assisted transactional memory systemUS20110145516 *Jun 16, 2011Ali-Reza Adl-TabatabaiUsing buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadataUS20110145553 *Dec 15, 2009Jun 16, 2011Microsoft CorporationAccelerating parallel transactions using cache resident transactionsUS20110191561 *Aug 4, 2011Red Hat, Inc.Augmented advisory lock mechanism for tightly-coupled clustersUS20110225585 *Sep 15, 2011International Business Machines CorporationRetooling lock interfaces for using a dual mode reader writer lockUS20130018860 *Jan 17, 2013Microsoft CorporationParallel nested transactions in transactional memoryUS20130166579 *May 25, 2012Jun 27, 2013Fuji Xerox Co., Ltd.Information processing apparatus and computer readable mediumEP2075690A1 *Dec 30, 2008Jul 1, 2009Intel CorporationMechanism for strong atomicity in a transactional memory systemWO2009134541A1 *Mar 16, 2009Nov 5, 2009Xilinx, IncConfigurable transactional memory for synchronizing transactions* Cited by examinerClassifications U.S. Classification711/163International ClassificationG06F12/14Cooperative ClassificationG06F12/0893, G06F9/526, G06F12/0806, G06F12/0815, G06F9/52, G06F9/466European ClassificationG06F9/52, G06F9/52E, G06F12/08B4P, G06F12/08B22, G06F9/46T, G06F12/08B4, G06F17/30CLegal EventsDateCodeEventDescriptionJun 27, 2006ASAssignmentOwner name: SUN MICROSYSTEMS, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DICE, DAVID;SHAVIT, NIR N.;SIGNING DATES FROM 20060620 TO 20060621;REEL/FRAME:018017/0735May 6, 2015FPAYFee paymentYear of fee payment: 4Dec 16, 2015ASAssignmentOwner name: ORACLE AMERICA, INC., CALIFORNIAFree format text: MERGER AND CHANGE OF NAME;ASSIGNORS:ORACLE USA, INC.;SUN MICROSYSTEMS, INC.;ORACLE AMERICA, INC.;REEL/FRAME:037311/0134Effective date: 20100212RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services