Source: http://www.google.com/patents/US7941636?dq=7,181,690
Timestamp: 2016-05-29 22:10:08
Document Index: 669127837

Matched Legal Cases: ['Application No. 01', 'Application No. 02', 'Application No. 63', 'Application No. 01', 'Application No. 55', 'Application No. 59', 'Application No. 59', 'Application No. 61']

Patent US7941636 - RISC microprocessor architecture implementing multiple typed register sets - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsDisclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands...http://www.google.com/patents/US7941636?utm_source=gb-gplus-sharePatent US7941636 - RISC microprocessor architecture implementing multiple typed register setsAdvanced Patent SearchPublication numberUS7941636 B2Publication typeGrantApplication numberUS 12/650,998Publication dateMay 10, 2011Priority dateJul 8, 1991Fee statusLapsedAlso published asDE69230057D1, DE69230057T2, EP0547216A1, EP0547216B1, EP0911724A2, EP0911724A3, US5493687, US5560035, US5682546, US5838986, US6044449, US6249856, US7555631, US7685402, US20010034823, US20030115440, US20070113047, US20100106942, WO1993001543A1Publication number12650998, 650998, US 7941636 B2, US 7941636B2, US-B2-7941636, US7941636 B2, US7941636B2InventorsSanjiv Garg, Derek J. Lentz, Le Trong Nguyen, Sho Long ChenOriginal AssigneeIntellectual Venture Funding LlcExport CitationBiBTeX, EndNote, RefManPatent Citations (350), Non-Patent Citations (145), Classifications (33), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetRISC microprocessor architecture implementing multiple typed register sets
US 7941636 B2Abstract
Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or more fields and is configured to store results of execution of the instructions in a destination defined by the one or more fields. The register file includes (i) a first register set having a register configured to store data of a single data type and (ii) a second register set having a register configured to store data of a plurality of data types. The register file is responsive to the one or more fields in at least one of the instructions to retrieve an operand of the at least one of the instructions from, or to store a result of the at least one of the instructions into, one of the registers of the first register set or the second register set as defined by the one or more fields of the at least one of the instructions.
an execution unit configured to execute instructions including one or more fields; and
a register file configured to store operands defined by the one or more fields and configured to store results of execution of the instructions in a destination defined by the one or more fields,
wherein the register file includes:
a first register set having a register configured to store data of a single data type; and
a second register set having a register configured to store data of a plurality of data types, and
wherein the register file is responsive to the one or more fields in at least one of the instructions to retrieve an operand of the at least one of the instructions from, or to store a result of the at least one of the instructions into, one of the registers of the first register set or the second register set as defined by the one or more fields of the at least one of the instructions.
the shadow set of registers has a same number of registers as a number of registers in the second subset of registers, and
in a first operating mode each operand access to the second subset of registers is directed to the second subset of registers, and in a second operating mode each operand access to the second subset of registers is directed to the shadow set of registers.
6. The apparatus of claim 1, wherein the register file further comprises a third register set comprising a plurality of registers, each of which is configured to store a Boolean value.
decoding the instruction having one or more fields;
accessing a register file, wherein the register file includes first and second register sets that store operands defined by the one or more fields and that store results of execution of the instruction in a destination defined by the one or more fields,
wherein the first register set stores data of a first data type, and
wherein the second register set stores data of the first data type or data of a second data type;
retrieving an operand of the instruction from one of the plurality of registers in one of the plurality of register sets as defined by the one or more fields; and
storing a result of the execution of the instruction into one of the plurality of registers in one of the plurality of register sets as defined by the one or more fields.
using a first subset of registers, a second subset of registers, and a shadow set of registers as a first register set, wherein the shadow subset of registers has a same number of registers as a number of registers in the second subset of registers;
in a second operating mode, directing each operand access to the second subset of registers to the shadow subset of registers.
directing each access to the first subset of registers to the first subset of registers.
including a third register set in the register file, the third register set comprising a plurality of registers, at least one of which is configured to store a Boolean value. Description
The present application is a continuation of application Ser. No. 11/651,009, filed Jan. 9, 2007, now U.S. Pat. No 7,685,402, which is a continuation of application Ser. No. 10/060,086, filed Jan. 31, 2002, now U.S. Pat. No. 7,555,631, which is a continuation of application Ser. No. 09/840,026, filed Apr. 24, 2001, now abandoned, which is a continuation of application Ser. No. 09/480,136, filed Jan. 10, 2000, now U.S. Pat. No. 6,249,856, which is a continuation of application Ser. No. 09/188,708, filed Nov. 10, 1998, now U.S. Pat. No. 6,044,449, which is a continuation of application Ser. No. 08/937,361, filed Sep. 25, 1997, now U.S. Pat. No. 5,838,986, which is a continuation of application Ser. No. 08/665,845, filed Jun. 19, 1996, now U.S. Pat. No. 5,682,546, which is a continuation of application Ser. No. 08/465,239, filed Jun. 5, 1995, now U.S. Pat. No. 5,560,035, which is a continuation of application Ser. No. 07/726,773, filed Jul. 8, 1991, now U.S. Pat. No. 5,493,687. Each of the above-referenced applications is incorporated by reference in its entirety herein.
Each individual register in the register set RFB [ ] may hold either a floating point value or an integer value. The register set RFB[ ] may include optional hardware for preventing accidental access of a floating point value as though it were an integer value, and vice versa. In one embodiment, however, in the interest of simplifying the register set RFB[ ], it is simply left to the software designer to ensure that no erroneous usages of individual registers are made. Thus, the execution engine 14 simply makes an access request on line 52, specifying an offset into the register set RFB[ ], without specifying whether the register at the given offset is intended to be used as a floating point register or an integer register. Within the execution engine 14, various entities may use either the full sixty-four bits provided by the register set RFB[ ], or may use only the low order thirty-two bits, such as in integer operations or single-precision floating point operations.
A first register RFB [0] 51 contains the constant value zero, in a form such that RB[0] is a thirty-two-bit integer zero (0000hex) and RF[0] is a sixty-four-bit floating point zero (00000000hex). This provides the same advantages as described above for RA[0].
0-3 Integer and floating point
register-to-register instructions
In order to perform the integer addition instruction, the integer functional unit 66 is responsive to the identification in I[14:10] and I[4:0] of the first and second source registers. The integer functional unit 66 places an identification of the first and second source registers at ports S1 and S2, respectively, onto the integer functional unit bus 72 which is coupled to both SMC units A and B 74 and 76. In one embodiment, the SMC units A and B are each coupled to receive BO-2, from the instruction I[ ]. In one embodiment, a zero in any respective Bn indicates register set A, and a one indicates register set B. During load/store operations, the source ports of the integer and floating point functional units 66 and 68 are utilized as a base port and an index port, B and I, respectively.
After obtaining the first and second operands from the indicated register sets on the bus 72, as explained below, the integer functional unit 66 performs the indicated operation upon those operands, and provides the result at port D onto the integer functional unit bus 72. The SMC units A and B are responsive to BO to route the result to the appropriate register set A or B.
IEU mode integer switch 34 is further responsive to I[20:16], I[14:10], and I[4:0].
If a given indicated destination or source is in RA[23:0], the IEU mode integer switch 34 automatically couples the data between lines 42 and 36.
However, for registers RA[31:24], the IEU mode integer switch 34 determines whether data on line 42 is connected to line 38 or line 40, and vice versa. When interrupts are enabled, IEU mode integer switch 34 connects the SMC unit A to the second subset 28 of integer registers RA[31:24]. When interrupts are disabled, the IEU mode integer switch 34 connects the SMC unit A to the shadow registers RT[31:24]. Thus, an instruction executing within the integer functional unit 66 need not be concerned with whether to address RA[31:24] or RT[31:24]. It will be understood that SMC unit A may advantageously operate identically whether it is being accessed by the integer functional unit 66 or by the floating point functional unit 68.
I[23, 22, 9, 8]
RA[1] : = 0;
IF (((RA[2] = RA[3]) AND (RA[4] > RA[5])) OR
(RA[6] < RA[7]) OR
(RA[8] < > RA[9])) THEN
Y( );
RA[10] : = 1;
RA[1], 0
RA[2], RA[3]
RA[4], RA[5]
RA[6], RA[7]
RA[8], RA[9]
RA[10], 1
The second portion of the Boolean function is the comparison of RA[6] to RA[7], at line 6 of Table 4, which again sets and clears the appropriate status flags. If the condition “less than” is indicated by the status flags, the complex Boolean function is passed, and execution may immediately branch to the DO-IF label. In various prior microprocessors, the “less than” condition may be tested by examining the minus flag. If RA[7] was not less than RA[6], the third portion of the test must be performed. The statement at line 8 of Table 4 compares RA[8] to RA[9]. If this comparison is failed, the “ELSE” code should be executed; otherwise, execution may simply fall though to the “IF” code at line 10 of Table 4, which is followed by an additional jump around the “ELSE” code. Each of the conditional branches in Table 4, at lines 3, 5, 7 and 9, results in a separate pipeline stall, significantly increasing the processing time required for handling this complex Boolean function.
RC[11], RA[2], RA[3], EQ
RC[12], RA[4], RA[5], GT
RC[13], RA[6], RA[7], LT
RC[14], RA[8], RA[9], NE
RC[15], RC[11], RC[12]
RC[16], RC[13], RC[14]
RC[17], RC[15], RC[16]
RC[17], DO-ELSE
As seen in FIG. 2, the register set FB 20 is a multi-ported register set. In one embodiment, the register set FB 20 has two write ports WFB0-1, and five read ports RDFB0-4. The floating point functional unit 68 of FIG. 1 is comprised of the ALU2 102, FALU 104, MULT 106, and NULL 108 of FIG. 2. All elements of FIG. 2 except the register set 20 and the elements 102-108 comprise the SMC unit B of FIG. 1. External, bidirectional data bus EX-DATA[ ] provides data to the floating point load/store unit 122. Immediate floating point data bus LDF_IMED[ ] provides data from a “load immediate” instruction. Other immediate floating point data are provided on busses RFF1_IMED and RFF2_IMED, such as is involved in an “add immediate” instruction. Data are also provided on bus EX_SR_DT[ ], in response to a “special register move” instruction. Data may also arrive from the integer portion, shown in FIG. 3, on busses 114 and 120.
The floating point register set's two write ports WFBO and WFBI are coupled to write multiplexers 110-0 and 110-1, respectively. The write multiplexers 110 receive data from: the ALU0 or SHF0 of the integer portion of FIG. 3; the FALU; the MULT; the ALU2; either EX_SR_DT[ ] or LDF-IMED[ ]; and EX_DATA[ ]. Those skilled in the art will understand that control signals (not shown) determine which input is selected at each port, and address signals (not shown) determine to Which register the input data are written. Multiplexer control and register addressing are within the skill of persons in the art, and will not be discussed for any multiplexer or register set in the present invention.
The floating point register set's five read ports RDFBO to RDFB4 are coupled to read multiplexers 112-0 to 112-4, respectively. The read multiplexers each also receives data from: either EX_SR_DT[ ] or LDF_IMED[ ], on load immediate bypass bus 126; a load external data bypass bus 127, which allows external load data to skip the register set FB; the output of the ALU2 102, which performs non-multiplication integer operations; the FALU 104, which performs non-multiplication floating point operations; the MULT 106, which performs multiplication operations; and either the ALU0 140 or the SHF0 144 of the integer portion shown in FIG. 3, which respectively perform non-multiplication integer operations and shift operations. Read multiplexers 112-1 and 112-3 also receive data from RFF1_IMED[ ] and RFF2_IMED[ ], respectively.
External data bus EX_DATA[ ] provides data to the integer load/store unit 152. Immediate integer data on bus LDI_IMED[ ] are provided in response to a “load immediate” instruction. Other immediate integer data are provided on busses RFA1_IMED and RFA2_IMED in response to non-load immediate instructions, such as an “add immediate.” Data are also provided on bus EX_SR-DT[ ] in response to a “special register move” instruction. Data may also arrive from the floating point portion (shown in FIG. 2) on busses 116 and 118.
The Boolean register set's five read ports RDCO to RDC3 are coupled to read multiplexers 172-0 to 172-4, respectively. The read multiplexers 172 receive the same set of inputs as the write multiplexers 170 receive. The Boolean combinational unit 70 receives inputs from read multiplexers 170-0 and 170-1. Read multiplexers 172-2 and 172-3 respectively provide signals BLBP_CPORT and BLBP_DPORT. BLBP_CPORT is used as the basis for conditional branching instructions in the IEU. BLBP_DPORT is used in the “add with Boolean” instruction, which sets an integer register in the A or B set to zero or one (with leading zeroes), depending upon the content of a register in the C set. Read port RDC4 is presently unused, and is reserved for future enhancements of the Boolean functionality of the IEU.
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