Source: http://www.google.com/patents/US20080049504?dq=6,970,917
Timestamp: 2016-10-21 21:13:03
Document Index: 673062819

Matched Legal Cases: ['art 3', 'art 3', 'art 3', 'art 3', 'art 4', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3']

Patent US20080049504 - Memory Control Circuit, Nonvolatile Storage Apparatus, and Memory Control Method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn address at which a writing error occurs is held, and after a completion of a series of writings, the data of the held address is read. Then, a faulty-block processing is performed only for the addresses, for which it is determined that retry of writing is required, thereby preventing an increase of...http://www.google.com/patents/US20080049504?utm_source=gb-gplus-sharePatent US20080049504 - Memory Control Circuit, Nonvolatile Storage Apparatus, and Memory Control MethodAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20080049504 A1Publication typeApplicationApplication numberUS 11/568,564PCT numberPCT/JP2005/008681Publication dateFeb 28, 2008Filing dateMay 12, 2005Priority dateMay 19, 2004Also published asCN1957337A, CN100407178C, US7849382, WO2005111812A1Publication number11568564, 568564, PCT/2005/8681, PCT/JP/2005/008681, PCT/JP/2005/08681, PCT/JP/5/008681, PCT/JP/5/08681, PCT/JP2005/008681, PCT/JP2005/08681, PCT/JP2005008681, PCT/JP200508681, PCT/JP5/008681, PCT/JP5/08681, PCT/JP5008681, PCT/JP508681, US 2008/0049504 A1, US 2008/049504 A1, US 20080049504 A1, US 20080049504A1, US 2008049504 A1, US 2008049504A1, US-A1-20080049504, US-A1-2008049504, US2008/0049504A1, US2008/049504A1, US20080049504 A1, US20080049504A1, US2008049504 A1, US2008049504A1InventorsTetsushi Kasahara, Tomoaki Izumi, Masahiro Nakanishi, Kazuaki Tamura, Kiminori Matsuno, Yoshihisa Inagaki, Manabu InoueOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (132), Classifications (8), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMemory Control Circuit, Nonvolatile Storage Apparatus, and Memory Control Method
DESCRIPTION OF REFERENCE NUMERALS [0000] 1 Memory card 2 Host interface 3 Controller 3 a Write part 3 b Determination part 3 c Management table update part 3 d Error correction part 3 e Termination control part 4 RAM 5 Instruction ROM 6 Buffer memory 7 Flash memory 41 Work RAM 42 First management table 43 Second management table 44 Error address register BEST MODE FOR CARRYING OUT THE INVENTION [0041] A memory card that is a nonvolatile storage apparatus in an embodiment of the present invention and its memory control circuit will be described below with referring figures. FIG. 1 is a block diagram showing a configuration of a memory card 1 including the memory control circuit according to the embodiment of the present invention. In FIG. 1, the memory card 1 is used by attaching to an electronic device (not shown) such as a digital still camera (DSC) and personal computer (PC). The memory card 1 mainly includes a host interface 2, controller 3, RAM 4, instruction ROM 5, buffer memory 6, and rewritable nonvolatile memory, for example, a flash memory 7. A part including the controller 3, RAM 4, instruction ROM 5, and buffer memory 6 is referred to as a memory control circuit. [0042] The host interface 2 executes an interface with an electronic device body (hereinafter referred to as a host) attaching the memory card 1, and sends and receives read/write data and commands and clocks for various controls to the flash memory 7. The controller 3 controls the whole of the memory card 1 and is composed of a micro processor (MPU). The controller 3 has various program execution parts described below. The controller 3 controls the RAM 4, flash memory 7, and buffer memory 6 according to control programs stored in the instruction ROM 5. A write part 3 a, determination part 3 b, management table update part 3 c, error correction part 3 d, and termination control part 3 e are there as the program execution parts. [0043] The instruction ROM 5 is a read only nonvolatile memory and stores a control program for achieving functions of the abovementioned program execution parts. The RAM 4 is composed of a volatile memory and has memory areas which are called work RAM 41 that is a work area of the controller 3, first block management table 42, second block management table 43, and error address register 44. [0044] The first block management table 42 and second management table 43 are management tables for retaining a use state of the flash memory 7 as management data. An example of management data in the management table is shown in FIG. 2. The management data in the management table records logical block address (physical address) and logical block address (logical address) corresponding to this, whether each block address is in use or not, and so on. Data area of the management data has same format in the both tables but their update timings are different. The management data in the first management table 42 is updated in every data writing to a block, while the management data in the second management table is updated in predetermined writing unit such as a unit of data transfer from the host. Concretely, when transfer of some data from the host is completed, management data of the first management table 42 is copied to the second management table 43. This means that the first management table 42 shows a present data storage state, while the second management table 43 shows a previous data storage state. [0045] Generally, reading and writing to a block of physics (physical block) of the flash memory 7 are executed after designating an address of a block of logic (logical block) given from the host. A role of the first management table 42 is this conversion of a logical address of this logical block to a physical address of a physical block. FIG. 2 shows correspondence relationships between physical blocks as block addresses and logical addresses, and shows whether the physical addresses (blocks designated by addresses) are in use or not. [0046] For instance, in an example shown in FIG. 2, it is written whether physical blocks are in use or not and logical address numbers allotted to each physical block are written. When “0” is listed on a column showing whether in use or not, there is a case where logical address is not written in spite of in use. The example of FIG. 2 shows that a physical address “6” corresponds to the state mentioned above and that the physical block is a bad block. In this case, this block is not selected as a writing address. The buffer memory 6 is a memory for temporarily retaining data transferred from the host. In addition, the flash memory 7 is a nonvolatile memory for writing the data transferred from the host. [0047] Data write processing of the memory card 1 composed as mentioned above will be explained with referring to flow charts shown in FIG. 3 and FIG. 4. The flow charts shown in FIG. 3 and FIG. 4 are put in practice by the controller 3 of FIG. 1. First, at step SI shown in FIG. 3, when receiving a write command from the host via the host interface, the controller 3 temporarily retains data transferred from the data in the buffer memory 6 and transfers data to the flash memory 7 in block units. [0048] Next, at step S2, the controller 3 refers to block management data recorded in the first management table 42, and searches a writable physical address, namely an unused physical address whose management data showing in use or not in use is “1”, that is, calculates a write address. And next, at step S3, data is written in the physical block searched in step S2. This step S3 achieves a function of the write part 3 a for writing new data in block units to the flash memory 7 of the nonvolatile memory based on management data of the first management table 42. [0049] Next, at step S4, a status read command is issued to the flash memory 7 and it is determined whether a processing status of data writing is normally executed or not according to a reply from the flash memory 7. This step S4 achieves a function of the determination part 3 b for determining whether data writing is normally executed or not. When it is determined that data writing is normally executed at step S4, corresponding management data on the first management table 42 is changed from “1” to “0” and logical block number that is logical address is written at step S5. [0050] On the contrary, when it is determined that data writing is not normally executed at step S4, processing progresses to step S6. After registering address occurring error to error address register 44, corresponding management data on the first management table 42 is changed from “1” to “0” and the logical block number that is logical address occurring error is written at step S5. When update of the first management table 42 is completed at step S5, processing progresses to step S7. At step 7, when this writing is not the last writing from the host, a step returns to step S1 and processing from step S1 to step S7 is repeated. [0051] At step S7, when the writing is the last writing from the host, processing progresses to step S8 in FIG. 4 and it is determined whether error address exists in the error address register 44 or not. If error address is not retained here, processing progresses to step S9, then management data of the first management table 42 is copied to the second management table 43, and writing is normally terminated (step S10). [0052] On the contrary, if error address is retained at step S8 of FIG. 4, processing progresses to step S11, then data of error address is read. At next step S12, the error correction part 3 d determines whether error is correctable or not. If the error is correctable, processing progresses to step S13 and it is determined whether the number of the error is within, for example, 1 bit or not, and if within 1 bit, the error is left. On the other hand, if the error is over 1 bit at step S13, processing progresses to step S14 and error of read data is corrected. [0053] Next, the controller 3 refers to each block's management data written in the first management table 42, and searches a writable physical address, that is, calculates a writing address. In next step S16, data is written to the physical block searched at step S15. Next, at step S17, corresponding management data on the first management table 42 is changed from “1” to “0” and logical block number as logical address is written. In addition, management data corresponding to an address having error on the first management table 42 is changed from “1” to “0” and a bad block processing is executed. Contents of the first management table 42 are updated in this manner. [0054] When a processing of step S17 completes, when it is determined that data error is within 1 bit at step S13, and when it is determined that error correction is impossible at step S12, a process progresses to step S18. When other error addresses remain in the error address register 44 at step S18, processing returns to step S11 but when processing to all error addresses completes, processing progresses to step S19. [0055] It is checked whether uncorrectable address exists or not and when uncorrectable address does not exist, processing progresses to step S9. When uncorrectable address exists, processing progresses to step S20. At step S9, management data of the first management table 42 is copied to the second management table 43. Writing processing normally terminates in this manner (Step S10). [0056] On the other hand, when error correction of read data is impossible, management data of the second management table 43 is copied to the first management table 42 to invalidate all the series of writing at step S20. This means that the first management table 42 is back to the previous state. At next step S21, management data corresponding to uncorrectable address on the first management table 42 is changed from “1” to “0” and a bad block processing is executed. Next, management data updated at step S21 of the first management table 42 is copied to the second management table 43 at step S22. Write processing abnormally terminates in this manner (step S23). [0057] In processing described above, step S5, step S17, and step S21 achieve a function of the management table update part 3 c for updating management data to prevent rewriting to a written block. In addition, step S11, step S12, step S13, and step S14 achieve a function of the error correction part 3 d for sequentially reading data of address retained by the error address register 44 and detecting and correcting error after completion of writing in predetermined units. Further, step S9, step S10, step S19, step S20, step S21, step S22, and step S23 achieve a function of the termination control part 3 e for copying management data of the first management table 42 to the second management table 43 and normally terminating when the writing in predetermined units is valid according to a data error state of address retained in the error address register 44, and for copying management data of the second management table 43 to the first management table 42 and abnormally terminating when the writing in predetermined units is invalid according to a data error state of address retained in the error address register 44. [0058] According to the embodiment as described above, since bad block processing is executed only for an address uncorrectable at step S12 and address determined as retry of writing at step S13, increase of bad blocks can be prevented. [0059] When error is equal to or over 2 bits, retry of writing is executed and bad block processing is executed in the embodiment described above. That is to say, it is supposed to be m=2 and n=2, but n may be equal to or larger than m, for example, it may be m=1 and n=2, or m=2 and n=3. [0060] To simplify the description, only an uncorrectable address detected first is set to a bad block and processing abnormally terminates, however, data of all addresses retained in error address may be read and all uncorrectable addresses may be set to bad blocks. [0061] A case applied for a memory card having a nonvolatile memory has been described. However, the other nonvolatile memories incorporated into, for example, an electronic device can he carried out in a similar manner and the present invention is not limited in a memory card. In addition, the RAM 4 is composed of a volatile memory, however, the RAM 4 may be a nonvolatile memory, and may be a combination of a volatile memory and nonvolatile memory. INDUSTRIAL APPLICABILITY [0062] A memory control circuit and memory control method of the present invention are suitably used in a nonvolatile storage apparatus including a controller and nonvolatile memory. And they can be applied for various electronic device incorporating a nonvolatile memory. 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TETSUSHI;IZUMI, TOMOAKI;NAKANISHI, MASAHIRO;AND OTHERS;REEL/FRAME:018880/0622Effective date: 20070118Nov 21, 2008ASAssignmentOwner name: PANASONIC CORPORATION, JAPANFree format text: CHANGE OF NAME;ASSIGNOR:MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;REEL/FRAME:021897/0606Effective date: 20081001Owner name: PANASONIC CORPORATION,JAPANFree format text: CHANGE OF NAME;ASSIGNOR:MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;REEL/FRAME:021897/0606Effective date: 20081001May 7, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services