Source: https://patents.google.com/patent/US9588575B2/en
Timestamp: 2019-09-21 22:43:45
Document Index: 371549312

Matched Legal Cases: ['§120', 'Application No. 201010227120', 'Application No. 201010227120', 'Application No. 201010227120', 'Application No. 112010002776', 'Application No. 112010002776']

US9588575B2 - Link power savings with state retention - Google Patents
Link power savings with state retention Download PDF
US9588575B2
US9588575B2 US14/321,402 US201414321402A US9588575B2 US 9588575 B2 US9588575 B2 US 9588575B2 US 201414321402 A US201414321402 A US 201414321402A US 9588575 B2 US9588575 B2 US 9588575B2
US14/321,402
US20150074440A1 (en
2014-07-01 Application filed by Intel Corp filed Critical Intel Corp
2014-07-01 Priority to US14/321,402 priority patent/US9588575B2/en
2015-03-12 Publication of US20150074440A1 publication Critical patent/US20150074440A1/en
2017-03-07 Publication of US9588575B2 publication Critical patent/US9588575B2/en
Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.
This Application is a continuation (and claims the benefit of priority under 35 U.S.C. §120) of U.S. application Ser. No. 12/495,706, filed Jun. 30, 2009, now issued as U.S. Pat. No. 8,831,666 and entitled LINK POWER SAVINGS WITH STATE RETENTION.
The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to link power savings with state retention.
As integrated circuit (IC) fabrication technology improves, manufacturers are able to integrate additional functionality onto a single silicon substrate. As the number of these functionalities increases, however, so does the number of components on a single IC chip. Additional components add additional signal switching, in turn, generating more heat. The additional heat may slow down, cause malfunction, or even damage an IC chip. Also, the additional heat may limit usage locations and/or applications of a computing device that includes such chips. For example, a portable computing device may solely rely on battery power. Hence, as additional functionality is integrated into portable computing devices, the need to reduce power consumption becomes increasingly important, for example, to maintain battery power for an extended period of time. Non-portable computing systems also face cooling and power generation issues as their IC components use more power and generate more heat.
FIG. 2 illustrates a flow diagram of low power entry and exit sequence, according to an embodiment.
FIG. 3 illustrates a sample detect hold-off time calculation and detect circuit according to some embodiments.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, some embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments. In an embodiment, I/O circuit(s), internal clock(s), and/or a forwarded clock are turned off while retaining link state in internal memory. It should be noted that internal memory used to save state generally has significantly lower power consumption than analog I/O and clocks, and hence results in significant power savings without impacting link resumption.
Some embodiments discussed herein are generally related to reducing power consumption and/or heat dissipation by link(s) (such as point-to-point or serial links) between two agents when the link(s) are idle, e.g., without sacrificing endpoint state. Such techniques may allow for faster turn off and/or lower wakeup latency of serial links. Also, these techniques may provide further improved performance, power saving, and/or heat dissipation when communication amongst coupled agents is sporadic.
More specifically, in one implementation, in the absence of activity on the link, either agent on a link may need to maintain the link state thereby consuming power. Therefore, the I/O (Input/Output) circuits and associated clock circuitry may remain operational. This approach may provide wake latency in the order of 10 s of nanoseconds. However, maintaining I/O circuits and associated clock circuitry can be very power consuming. Another implementation may turn off a physical port (e.g., I/O and clock circuitry as well as internal logic/storage elements that maintain a link active). This approach may have a wakeup latency of several milliseconds. Accordingly, such techniques suffer from performance loss due to long wakeup time, albeit dissipating lower power. Further, turning-off the physical port completely may have impact on other interface layers upstream, such as link layer, protocol layer, etc. Accordingly, some solutions may not have the ability to turn-off power hungry I/O circuits for brief periods of time and resume the link almost instantaneously when link activity is detected.
To this end, an embodiment provides a mechanism to turn-off power consuming I/O drivers, I/O receivers, and/or physical layer clocks while retaining the link state in each agent. As discussed herein, retaining link state of an agent herein generally refers to maintaining the state in all layers above the physically (PHY) including link layer, protocol layer etc. When activity resumes, agents may quickly turn-on I/O and clock circuitry and become operational. In some embodiments, the link resumption time is in the order of 10 microseconds, and does not impact system components outside the link physical layer (e.g., processor/chipset architectural state, display, etc.). Accordingly, such a power savings feature allows products with superior power and/or thermal characteristics. Ability to turn-off the link and resuming activity instantaneously (e.g., 10 microseconds) may result in battery savings for mobile devices. All devices incorporating such features may also dissipate less heat, and hence reduce cost of platform thermal solution.
For example, when a computer is being used in presentation mode, only the display needs to be active all the time. No inter-agent communication over the links interface is required when discussion is focused on a foil (which can last few 10 s of seconds to several minutes). When activity resumes, usually through some form of user interface (e.g., keyboard, mouse, pointer, etc.), the link responds immediately to advance through the presentation. The time required to resume the link, using some embodiments discussed herein, can not be perceptible (10 microseconds) to the human eye.
Various computing systems may be used to implement embodiments discussed herein, such as the systems discussed with reference to FIGS. 1 and 4-5. More particularly, FIG. 1 illustrates a block diagram of a computing system 100, according to an embodiment of the invention. The system 100 may include one or more agents 102-1 through 102-M (collectively referred to herein as “agents 102” or more generally “agent 102”). In an embodiment, one or more of the agents 102 may be any of components of a computing system, such as the computing systems discussed with reference to FIG. 4 or 5. In some embodiments, an agent may be a hardware accelerators (e.g., which may be Field-Programmable Gate Array (FPGA) based). The agent may also be a SoC (System on Chip), MCP (Multi-Chip Package), a tandem/redundant/lock-step agent, system management controllers, combinations thereof, etc.
As illustrated in FIG. 1, the agents 102 may communicate via a network fabric 104. In one embodiment, the network fabric 104 may include a computer network that allows various agents (such as computing devices or their components) to communicate data. Also, the network fabric 104 may include non-electrical media, e.g., fiber-optic links, magnetically coupled links. Moreover, in some embodiments, parts of the network may include links conforming to other protocols for signaling and power-saving. In an embodiment, the network fabric 104 may include one or more interconnects (or interconnection networks) that communicate via a serial (e.g., point-to-point) link and/or a shared communication network. For example, some embodiments may facilitate component debug or validation on links that allow communication with fully buffered dual in-line memory modules (FBD), e.g., where the FBD link is a serial link for coupling memory modules to a host controller device (such as a processor or memory hub). Debug information may be transmitted from the FBD channel host such that the debug information may be observed along the channel by channel traffic trace capture tools (such as one or more logic analyzers).
Generally, cache memory in computing systems may be kept coherent using a snoopy bus or a directory based protocol. In either case, a memory address is associated with a particular location in the system. This location is generally referred to as the “home node” of the memory address. In a directory based protocol, processing/caching agents may send requests to the home node for access to a memory address with which a “home agent” is associated. Additionally, at least of the agents 102 may be a home agent and one or more of the agents 102 may be requesting agents. Further, in an embodiment, one or more of the agents 102 may maintain entries in a storage device (e.g., implemented as a table, queue, buffer, linked list, etc.) to track information about requests. Such storage device may be local (e.g., memory 112-1) to an agent or otherwise accessible by a given agent 102.
FIG. 2 illustrates a flow diagram of low power entry and exit sequence, according to an embodiment. Ports A and B, respectively, refer to ports on two agents coupled via a serial link. In some embodiments, entering and exiting a low power consumption state (referred to herein as “L1” or “Level 1”) is controlled by the Link layers of the two agents. Even though FIG. 2 indicates exit from L1 is initiated by the mater (e.g., Port A), exit from L1 may also be initiated by the slave (e.g., Port B) in some embodiments. Moreover, a Link layer protocol is responsible for bringing the Link layers to the threshold of L1 entry and then causing the Physical layers to enter L1. In the L1 master (e.g., Port A), a command (such as LinkEnterL1) may cause the Physical layer to enter L1 and issue an inband reset signal. In the L1 slave (e.g., Port B), a command (such as LinkEnterL1) may cause the Physical layer to enter L1 when it receives this inband reset from the master. Entering L1 causes the slave to issue an inband reset signal to the master in an embodiment. In an embodiment, the two agents may be on different integrated circuit die but in the same package.
Both directions of the link may be used to enter into L1 state. In L1 state, circuits in electrical sub-block are turned-off and logical sub-block is functionally turned off. In some embodiments, electrical circuits/sub-blocks may include sense amplifiers, filters, equalizers, voltage and resistance offsets, phase interpolators, signal drift trackers, phase-locked loop (PLL) clock, etc. Moreover, an embodiment provides a mechanism to turn-off power consuming I/O drivers, I/O receivers, and/or physical layer clocks while retaining the link state in each agent (associated with ports A and B). In some embodiments, power may be maintained to the logical sub-block to ensure Physical layer configuration is not lost during L1. Also, in some embodiments, the Physical layer internal (e.g., phase locked loop (PLL)) clock may be turned off (e.g., by the platform). Prior to entering L1, each port may also configure itself such that calibration is bypassed upon exit from L1 (e.g., for faster power on). In an embodiment, all Rx (Receiver) terminations meet ZRX_HIGH_CM (e.g., high impedance state which the Tx port uses to determine/detect whether a link is down) in L1 state.
As shown in FIG. 2, Link layer on local port A signals (or otherwise indicates to) its Physical layer that an entry into L1 is impending and starts sending out one or more messages (for example in the form of packets) indicating L1 entry, such as Packet #1 or #2 at A1 and A2, respectively, to remote port B. The Link layer on remote port B, after receiving L1 packet(s) at B1 or B2, signals its Physical layer that an entry into L1 is to be expected, and acknowledges local port A's L1 entry request (L1 ACK #1 or #2 messages) at B1 or B2.
When Link layer on local port A receives remote port B's ACK indication/message/signal (e.g., L1 ACK #1 at A3), it instructs local Physical layer of port A to enter L1. Local Physical layer of port A responds to this signal by sending an Inband Reset signal to remote Physical layer of port B at A3 and enters an L1 state. The remote Physical layer interprets this Inband Reset at B3 as an entry in L1 based on a previous signal from port A Link layer and enters L1. At this point, e.g., after A3 for port A and B3 for port B, both port A and port B are in L1 state.
The remote port B may also choose to send NACK (Negative Acknowledgement) in response to an L1 entry request from the local port A, in which case remote Physical layer is not informed of this L1 request. Link layer on the local port A, upon receiving remote NACK, abandons its L1 request and instructs its local Physical layer not to expect an entry into L1 until further notice. The ports continue to remain in current power consumption state (e.g., Level 0 (L0) which generally refers to the normal operation mode).
In some embodiments, Cyclic Redundancy Code (CRC) errors detected by either port after an L1 entry sequence has started would result in both sides ignoring this L1 sequence. For instance, if remote Link layer detected a CRC error either on L1 entry packet or flits prior to it, it sends a retry request to local Link layer. In this case, the remote port is not aware of the L1 request, and hence continues to stay in L0. The local Link layer, upon receiving a retry request, may abandon current L1 sequence and continues to stay in L0. Conversely, if local Link layer sees a CRC error after sending an L1 entry packet, it may abandon the current L1 sequence and send a retry request to remote port. The remote port, which is expecting an Inband Reset signal to enter L1, abandons the current L1 sequence upon seeing this retry request. In some embodiments, when a Link layer abandons its L1 sequence, it instructs the Physical layer accordingly to ensure that a subsequent Inband Reset is not interpreted as an indication to enter L1.
As shown in FIG. 2, exiting from L1 (at A5) is initiated by a higher layer (e.g., the Link layer) and may not occur prior to the detect hold-off period described below. As shown in FIG. 2, at A6, Port A may be in detect clock termination mode (e.g., waiting for signal to exit from L1). Upon exit from L1, at B4, Port B may wait for a period (e.g., T-debounce) before entering into detect clock termination at B5. Since the exit is not accompanied by a platform synchronizing event (like reset) or software re-programming of electrical and logical configuration registers, both agents are expected to maintain correct count of the synchronization counter and the values in their configuration register(s) (e.g., or values stored in memory 112-1) through these states. Implementations may also need alternative timing methods in L1 since link clock may be turned off. For example, implementations may qualify the detection of terminations to avoid spurious exits due to noise (such qualification could be as simple as detecting terminations continuously or for an extended period of time). In an embodiment, Rx terminations (e.g., including clock lane) meet ZRX_HIGH_CM_DC (e.g., high impedance state which the Tx port uses to determine/detect whether a link is down) in L1 state. Since this change on the clock lane will take time (e.g., due to Resistor-Capacitor (RC) charging) to be observed at Tx (Transmit) side detect circuit (see, e.g., FIG. 3 which illustrates a detect hold-off time calculation and sample detect circuit according to some embodiments), the results of detection are ignored for some platform-dependent time.
For example, in FIG. 3: assume 2 pf of component capacitance at each end of the clock lane and 25 inches of trace at 1 pf per inch of capacitance with link detection resistor value (Z_tx_link_detect) of 2 Kohm and leakage at each end of 10 Kohm. Allowing for four time constants before observing the voltage level would require a detect hold-off for 4*RC (e.g., 4*(2*5/(5+2))*(2+25+2) or about 165 ns). Note that the final settling voltage=(Reff/R_Link)*Vcc which is lower than Vcc. Therefore users may need to ensure that this is still above their detection threshold.
In an embodiment, exit from L1 to L0 uses the detect scheme used by Physical layer during link initialization. Termination detectors on each port's Tx differential pairs are turned on in L1. A port receiving an implementation specific L1 exit signal would turn-on terminations on clock lane(s)—clock Rx terminations must now meet ZRX_LOW_CM (e.g., low impedance state which the Tx port uses to determine/detect whether a link is up). Termination detectors at clock Tx on remote port may sense Rx clock terminations and use this as an indication to exit from L1.
FIG. 4 illustrates a block diagram of an embodiment of a computing system 400. One or more of the agents 102 of FIG. 1 may comprise one or more components of the computing system 400. The computing system 400 may include one or more central processing unit(s) (CPUs) 402 (which may be collectively referred to herein as “processors 402” or more generically “processor 402”) coupled to an interconnection network (or bus) 404. The processors 402 may be any type of processor such as a general purpose processor, a network processor (which may process data communicated over a computer network 405), etc. (including a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC)). Moreover, the processors 402 may have a single or multiple core design. The processors 402 with a multiple core design may integrate different types of processor cores on the same integrated circuit (IC) die. Also, the processors 402 with a multiple core design may be implemented as symmetrical or asymmetrical multiprocessors.
The processor 402 may include one or more caches, which may be private and/or shared in various embodiments. Generally, a cache stores data corresponding to original data stored elsewhere or computed earlier. To reduce memory access latency, once data is stored in a cache, future use may be made by accessing a cached copy rather than refetching or recomputing the original data. The cache(s) may be any type of cache, such a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3), a mid-level cache, a last level cache (LLC), etc. to store electronic data (e.g., including instructions) that is utilized by one or more components of the system 400. Additionally, such cache(s) may be located in various locations (e.g., inside other components to the computing systems discussed herein, including systems of FIG. 1 or 5).
A chipset 406 may additionally be coupled to the interconnection network 404. Further, the chipset 406 may include a graphics memory control hub (GMCH) 408. The GMCH 408 may include a memory controller 410 that is coupled to a memory 412. The GMCH may also include one or more memory bridges in some embodiments. The memory 412 may store data, e.g., including sequences of instructions that are executed by the processor 402, or any other device in communication with components of the computing system 400. Also, in one embodiment of the invention, the memory 412 may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), etc. Nonvolatile memory may also be utilized such as a hard disk. Additional devices may be coupled to the interconnection network 404, such as multiple processors and/or multiple system memories.
As shown in FIG. 4, a hub interface 418 may couple the GMCH 408 to an input/output control hub (ICH) 420. The ICH 420 may provide an interface to input/output (I/O) devices coupled to the computing system 400. The ICH may include one or more host controllers, hubs, and/or bridges in some embodiments. The ICH 420 may be coupled to a bus 422 through a peripheral bridge (or controller) 424, such as a peripheral component interconnect (PCI) bridge that may be compliant with the PCIe specification, a universal serial bus (USB) controller, etc. The bridge 424 may provide a data path between the processor 402 and peripheral devices. Other types of topologies may be utilized. Also, multiple buses may be coupled to the ICH 420, e.g., through multiple bridges or controllers. Further, the bus 422 may comprise other types and configurations of bus systems. Moreover, other peripherals coupled to the ICH 420 may include, in various embodiments of the invention, integrated drive electronics (IDE), Serial Advanced Technology Attachment (SATA), Solid State Drive (SSD, or small computer system interface (SCSI) drive(s), USB port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), etc.
The bus 422 may be coupled to an audio device 426, one or more disk drive(s) 428, and a network adapter 430 (which may be a NIC in an embodiment). In one embodiment, the network adapter 430 or other devices coupled to the bus 422 may communicate with the chipset 406. Other devices may be coupled to the bus 422. Also, various components (such as the network adapter 430) may be coupled to the GMCH 408 in some embodiments of the invention. In addition, the processor 402 and the GMCH 408 may be combined to form a single chip. In an embodiment, the memory controller 410 may be provided in one or more of the CPUs 402. Further, in an embodiment, GMCH 408 and ICH 420 may be combined into a Peripheral Control Hub (PCH).
The network 405 may include any type of computer network. The network adapter 430 may further include a direct memory access (DMA) engine, which writes packets to buffers (e.g., stored in the memory 412) assigned to available descriptors (e.g., stored in the memory 412) to transmit and/or receive data over the network 405. Additionally, the network adapter 430 may include a network adapter controller, which may include logic (such as one or more programmable processors) to perform adapter related operations. In an embodiment, the adapter controller may be a MAC (media access control) component. The network adapter 430 may further include a memory, such as any type of volatile/nonvolatile memory (e.g., including one or more cache(s) and/or other memory types discussed with reference to memory 412). Moreover, the network adapter 430 network adapter may include capability for IPC (Inter-Process Communication) and RMA (Remote Memory Access) across the network 405.
In at least one embodiment, the agents discussed herein may be present in the processors 502,504 and/or MCH 506,508. Other embodiments of the invention, however, may exist in other circuits, logic units, or devices within the system 500 of FIG. 5. Furthermore, other embodiments of the invention may be distributed throughout several circuits, logic units, or devices illustrated in FIG. 5.
a first agent to be coupled to a second agent via a link, the first agent to:
assert a link entry signal to cause physical layer associated with the first agent to send an in-band reset signal to the second agent; and
enter the low power link state in response to an acknowledgement message to the link entry signal from the second agent;
wherein an electrical sub-block is to be turned off and power is to be maintained at a logical sub-block of the first agent in the low power link state to preserve configuration of the physical layer associated with the first agent.
2. The apparatus of claim 1, wherein the electrical sub-block comprises a phase locked loop (PLL) clock.
3. The apparatus of claim 1, wherein all lane transmitter and receivers and forwarded clocks of the link are to be disabled during the low power link state.
4. The apparatus of claim 1, wherein the low power link state comprises the lowest power state available to the link without removing its power supplies.
5. The apparatus of claim 1, wherein the acknowledgement comprises an in-band reset signal from the physical layer associated with the second agent.
6. The apparatus of claim 1, wherein the second agent is to exit the low power link state in response to a signal from the first agent.
7. The apparatus of claim 1, wherein the first agent is to exit the low power link state in response to a signal from the second agent.
8. The apparatus of claim 1, wherein the first agent is to detect terminations on the link during the low power link state.
9. The apparatus of claim 8, wherein a detect hold-off time is to be applied in the detection of the terminations.
10. The apparatus of claim 8, wherein the first agent is further to qualify detection of the terminations.
11. The apparatus of claim 1, wherein both directions of the link are to enter the low power link state.
12. The apparatus of claim 1, wherein the second agent is transmit the acknowledgement message in response to entry of a physical layer associated with the second agent into the low power link state.
a controller to interface between at least a first processor to recognize a first instruction set and second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising interface logic to couple to a link comprising a plurality of lanes;
the interface logic to:
send a link entry signal to indicate that a physical layer is to enter a low power link state, wherein the low power link state comprises a lowest power state available to the link without removing power supplies to the link; and
enter the low power link state in response to an acknowledgement to the link entry signal, wherein an electrical sub-block of the physical layer is to be turned off and a logical sub-block of the physical layer is to be functionally shut down with power maintained at the logical sub-block in the low power link state to preserve configuration of the physical layer.
asserting a link entry signal to cause a physical layer associated with a first agent to enter a low power link state and send an in-band reset signal to a second agent;
receiving an acknowledgment from the second agent, wherein the second agent is to transmit the acknowledgement message in response to a physical layer associated with second agent entering the low power link state; and
causing the first agent to enter the low power link state in response to the acknowledgement;
a second agent communicatively coupled to the first agent via a serial data link;
wherein the first agent is to send a signal to the second agent to indicate an attempt to enter a low power link state, the second agent is to enter the low power link state based on the signal and send an acknowledgment to the first agent, and the first agent is to enter the low power link state based on the acknowledgment, wherein clock circuitry of the first agent is to be turned-off and power is to be maintained at a logical sub-block of the first agent to maintain configuration of a physical layer of the first agent during the low power link state.
16. The system of claim 15, wherein the first and second agents are agents on a same computing chip package.
17. The system of claim 16, wherein the first and second agents are agents on a same die on the computing chip package.
18. The system of claim 16, wherein the first and second agents are agents on different die on the computing chip package.
19. The system of claim 15, wherein the first and second agents each comprise respective physical layer logic and respective link layer logic.
20. The system of claim 19, wherein entry and exit of the low power link state is to be initiated by the link layer logic.
US14/321,402 2009-06-30 2014-07-01 Link power savings with state retention Active 2029-09-09 US9588575B2 (en)
US14/321,402 US9588575B2 (en) 2009-06-30 2014-07-01 Link power savings with state retention
US15/451,645 US10175744B2 (en) 2009-06-30 2017-03-07 Link power savings with state retention
US12/495,706 Continuation US8831666B2 (en) 2009-06-30 2009-06-30 Link power savings with state retention
US15/451,645 Division US10175744B2 (en) 2009-06-30 2017-03-07 Link power savings with state retention
US20150074440A1 US20150074440A1 (en) 2015-03-12
US9588575B2 true US9588575B2 (en) 2017-03-07
US12/495,706 Active 2031-07-27 US8831666B2 (en) 2009-06-30 2009-06-30 Link power savings with state retention
US14/321,402 Active 2029-09-09 US9588575B2 (en) 2009-06-30 2014-07-01 Link power savings with state retention
US15/451,645 Active US10175744B2 (en) 2009-06-30 2017-03-07 Link power savings with state retention
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