Source: http://www.google.com/patents/US7398455?dq=7222078
Timestamp: 2013-12-12 00:22:29
Document Index: 576333342

Matched Legal Cases: ['application No. 10', 'application No. 03146510', 'application No. 03254214', 'application No. 03254214', 'application No. 03254214', 'application No. 03254214', 'application No. 03254214', 'application No. 2003', 'application No. 2003', 'application No. 10']

Patent US7398455 - Method and system for decoding low density parity check (LDPC) codes - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsAn approach is provided for transmitting messages using low density parity check (LDPC) codes. Input messages are encoded according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The LDPC codes are transmitted over a radio...http://www.google.com/patents/US7398455?utm_source=gb-gplus-sharePatent US7398455 - Method and system for decoding low density parity check (LDPC) codesPublication numberUS7398455 B2Publication typeGrantApplication numberUS 11/059,938Publication dateJul 8, 2008Filing dateFeb 17, 2005Priority dateJul 3, 2002Fee statusPaidAlso published asUS7020829, US8145980, US20040005865, US20050166133, US20080065947Publication number059938, 11059938, US 7398455 B2, US 7398455B2, US-B2-7398455, US7398455 B2, US7398455B2InventorsMustafa Eroz, Feng-Wen Sun, Lin-nan LeeOriginal AssigneeThe Directv Group, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (73), Non-Patent Citations (55), Referenced by (4), Classifications (49), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for decoding low density parity check (LDPC) codesUS 7398455 B2Abstract An approach is provided for transmitting messages using low density parity check (LDPC) codes. Input messages are encoded according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The LDPC codes are transmitted over a radio communication system (e.g., satellite network), wherein a receiver communicating over the radio communication system is configured to iteratively decode the received LDPC codes according to a signal constellation associated with the LDPC codes. The receiver is configured to iteratively regenerating signal constellation bit metrics after one or more decoding iterations.
iteratively exchanging probability information with a low density parity check (LDPC) decoder to regenerate signal constellation bit metrics after one or more decoding iterations, wherein the signal constellation metrics are determined based on distance vector information,
wherein the decoder is configured to output decoded messages based on the regenerated signal constellation bit metrics.
2. A method according to claim 1, wherein the probability information includes a posteriori probability information based on a priori probability information based on the distance vector information that includes information on distances between received noisy symbol points and symbol points of the signal constellation.
3. A method according to claim 2, wherein the decoder is further configured to determine whether parity check equations associated with the LDPC codes are satisfied according to the a priori probability and the a posteriori probability information.
4. A method according to claim 2, wherein the decoder is further configured to determine extrinsic information based on the a posteriori probability information and a priori probability information, and to output symbol probabilities associated with the signal constellation according to the extrinsic information.
5. A method according to claim 1, wherein symbols of the signal constellation are Gray coded, whereby more vulnerable bits of Gray coded symbol constellation are assigned at least as many parity checks as less vulnerable bits of Gray coded symbol constellation.
6. A method according to claim 1, wherein information regarding bit nodes and check nodes of the LDPC codes are stored in contiguous physical memory locations.
7. A method according to claims 1, wherein the signal constellation Includes one of 31-PSK (Phase Shift Keying), 39-QAM (Quadrature Amplitude Modulation), or QPSK (Quadrature Phase Shift Keying).
8. A method according to claim 1, wherein the LDPC codes are received over a satellite network.
a bit generator configured to iteratively exchange probability information with a low density parity check (LDPC) decoder to regenerate signal constellation bit metrics after one or more decoding iterations, wherein the signal constellation metrics are determined based on distance vector information,
10. An apparatus according to claim 9, wherein the probability information includes a posteriori probability information based on a priori probability information based on the distance vector information that includes information on distances between received noisy symbol points and symbol points of the signal constellation.
11. An apparatus according to claim 10, wherein the decoder is further configured to determine whether parity check equations associated with the LDPC codes are satisfied according to the a priori probability and the a posteriori probability information.
12. An apparatus according to claim 10, wherein the decoder is further configured to determine extrinsic information based on the a posteriori probability information and a priori probability information, and to output symbol probabilities associated with the signal constellation according to the extrinsic information.
13. An apparatus according to claim 9, wherein symbols of the signal constellation are Gray coded, whereby more vulnerable bits of Gray coded symbol constellation are assigned at least as many parity checks as less vulnerable bits of Gray coded symbol constellation.
14. An apparatus according to claim 9, wherein information regarding bit nodes and check nodes of the LDPC codes are stored in contiguous physical memory locations.
15. An apparatus according to claims 9, wherein the signal constellation includes one of 31-PSK (Phase Shift Keying), 39-QAM (Quadrature Amplitude Modulation), or QPSK (Quadrature Phase Shift Keying).
16. An apparatus according to claim 9, wherein the LDPC codes are received over a satellite network.
a low density purity check (LDPC) decoder configured to iteratively decode LDPC codes according to a signal constellation associated with the LDPC codes; and
a bit generator coupled to the decoder and to iteratively regenerate signal constellation bit metrics after one or more decoding iterations, wherein the signal constellation metrics are determined based an distance vector information,
wherein the decoder is further configured to output decoded messages based on the regenerated signal constellation bit metrics.
18. A system according to claim 17, wherein the decoder is further configured to transmit a posteriori probability information based on the a priori probability information generated by the bit metric generator based the distance vector information, the decoder being further configured to determine whether parity check equations associated with the LDPC codes are satisfied according to the a priori probability and the a posteriori probability information.
19. A system according to claim 18, wherein the distance vector information includes information on distances between received noisy symbol points and symbol points of the signal constellation.
20. A system according to claim 18, wherein the decoder is further configured to determine extrinsic information based on the a posteriori probability information and a priori probability information, and to output symbol probabilities associated with the signal constellation according to the extrinsic information.
RELATED APPLICATIONS This application is a continuation of U.S. patent application No. 10/454,439 filed Jun. 4, 2003 now U.S. Pat. No. 7,020,829. This application is related to, and claims the benefit of the earlier filing date under 35 U.S.C. �119(e) at U.S. Provisional Patent Application (Ser. No. 60/393,457) filed Jul. 3, 2002, entitled �Code Design and Implementation Improvements for Low Density Parity Check Codes,� U.S. Provisional Patent Application (Ser. No. 60/398,760) filed Jul. 26, 2002, entitled �Code Design and Implementation Improvements for Low Density Parity Check Codes,� U.S. Provisional Patent Application (Ser. No. 60/403,812) filed Aug. 15, 2002, entitled �Power and Bandwidth Efficient Modulation and Coding Scheme for Direct Broadcast Satellite and Broadcast Satellite Communications,� U.S. Provisional Patent Application (Ser. No. 60/421,505), filed Oct. 25, 2002, entitled �Method and System for Generating Low Density Parity Check Codes,� U.S. Provisional Patent Application (Ser. No. 60/421,999), filed Oct. 29, 2002, entitled �Satellite Communication System Utilizing Low Density Parity Check Codes,� U.S. Provisional Patent Application (Ser. No. 60/423,710), filed Nov. 4, 2002, entitled �Code Design and Implementation Improvements for Low Density Parity Check Codes.� U.S. Provisional Patent Application (Ser. No. 60/440,199) filed Jan. 15, 2003, entitled �Novel Solution to Routing Problem in Low Density Parity Check Decoders,� U.S. Provisional Patent Application (Ser. No. 60/447,641) filed Feb. 14, 2003, entitled �Low Density Parity Check Code Encoder Design,� U.S. Provisional Patent Application (Ser. No. 60/451,548) filed Mar. 3, 2003, entitled �System and Method for Advanced Modulation and Coding,� and U.S. Provisional Patent Application (Ser. No. 60/456,220) filed Mar. 20, 2003, entitled �Description LDPC and Encoders�; the entireties of which are incorporated herein by reference.
FIELD OF THE INVENTION The present invention relates to communication systems, and more particularly to coded systems.
BACKGROUND OF THE INVENTION Communication systems employ coding to ensure reliable communication across noisy communication channels. These communication channels exhibit a fixed capacity that can be expressed in terms of bits per symbol at certain signal to noise ratio (SNR), defining a theoretical upper limit (known as the Shannon limit). As a result, coding design has aimed to achieve rates approaching this Shannon limit. One such class of codes that approach the Shannon limit is Low Density Parity Check (LDPC) codes.
Traditionally, LDPC codes have not been widely deployed because of a number of drawbacks. One drawback is that the LDPC encoding technique is highly complex. Encoding an LDPC code using its generator matrix would require storing a very large, non-sparse matrix. Additionally, LDPC codes require large blocks to be effective; consequently, even though parity check matrices of LDPC codes are sparse, storing these matrices is problematic.
Therefore, there is a need for a LDPC communication system that employs simple encoding and decoding processes. There is also a need for using LDPC codes efficiently to support high data rates, without introducing greater complexity. There is also a need to improve performance of LDPC encoders and decoders. There is also a need to minimize storage requirements for implementing LDPC coding. There is a further need for a scheme that simplifies the communication between processing nodes in the LDPC decoder.
SUMMARY OF THE INVENTION These and other needs are addressed by the present invention, wherein ad approach for decoding a structured Low Density Parity Check (LDPC) codes is provided. Structure of the LDPC codes is provided by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between processing nodes of the decoder becomes very simple. Also, the approach can advantageously exploit the unequal error protecting capability of LDPC codes on transmitted bits to provide extra error protection to more vulnerable bits of high order modulation constellations (such as 8-PSK (Phase Shift Keying)). The decoding process involves iteratively regenerating signal constellation bit metrics into an LDPC decoder after each decoder iteration or several decoder iterations. The above arrangement provides a computational efficient approach to decoding LDPC codes.
According to one aspect of an embodiment of the present invention, a method for decoding low density parity check (LDPC) codes is disclosed. The method includes receiving a priori probability information based on distance vector information relating to distances between received noisy symbol points and symbol points of a signal constellation associated with the LDPC codes. The method also includes transmitting a posteriori probability information based on the a priori probability information. The method includes determining whether parity check equations associated with the LDPC codes are satisfied according to the a priori probability and the a posteriori probability information. Additionally, the method includes selectively regenerating the signal constellation bit metrics based on the determining step. Further, the method includes outputting decoded messages based on the regenerated signal constellation bit metrics.
According to another aspect of an embodiment of the present invention, a system for decoding low density parity check (LDPC) codes is disclosed. The system includes means for receiving a priori probability information based on distance vector information relating to distances between received noisy symbol points and symbol points of a signal constellation associated with the LDPC codes. The system also includes means for transmitting a posteriori probability information based on the a priori probability information. Additionally, the system includes means for determining whether parity check equations associated with the LDPC codes are satisfied according to the a priori probability and the a posteriori probability information. The system includes means for selectively regenerating the signal constellation bit metrics based on the determination. Further, the system includes means for outputting decoded messages based on the regenerated signal constellation bit metrics.
According to another aspect of an embodiment of the present invention, a receiver for decoding low density parity check (LDPC) codes is disclosed. The receiver includes a bit metric generator configured to generate a priori probability information based on distance vector information relating to distances between received noisy symbol points and symbol points of a signal constellation associated with the LDPC codes. The receiver also includes a decoder configured to output a posteriori probability information based on the a priori probability information received from the bit metric generator, wherein the decoder is further configured to determine whether parity check equations associated with the LDPC codes are satisfied according to the a priori probability and the a posteriori probability information. The decoder outputs decoded messages based on a regenerated signal constellation bit metrics if the parity check equations are not satisfied.
According to another aspect of an embodiment of the present invention, a method for transmitting messages using low density parity check (LDPC) codes is disclosed. The method includes encoding input messages according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The method also includes transmitting the LDPC codes over a radio communication system, wherein a receiver communicating over the radio communication system is configured to iteratively decode the received LDPC codes according to a signal constellation associated with the LDPC codes. The receiver is configured to iteratively regenerating signal constellation bit metrics after one or more decoding iterations.
FIG. 2 is a diagram of an exemplary transmitter in the system of FIG. 1;
DESCRIPTION OF THE PREFERRED EMBODIMENT A system, method, and software for efficiently decoding structured Low Density Parity Check (LDPC) codes are described. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It is apparent, however, to one skilled in the art that the present invention may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the present invention.
FIG. 2 is a diagram of an exemplary transmitter in the system of FIG. 1. A transmitter 200 is equipped with an LDPC encoder 203 that accepts input from an information source 201 and outputs coded stream of higher redundancy suitable for error correction processing at the receiver 105. The information source 201 generates k signals from a discrete alphabet, X. LDPC codes are specified with parity check matrices. On the other hand, encoding LDPC codes require, in general, specifying the generator matrices. Even though it is possible to obtain generator matrices from parity check matrices using Gaussian elimination, the resulting matrix is no longer sparse and storing a large generator matrix can be complex.
Encoder 203 generates signals from alphabet Y to a modulator 205 using a simple encoding technique that makes use of only the parity check matrix by imposing structure onto the parity check matrix. Specifically, a restriction is placed on the parity check matrix by constraining certain portion of the matrix to be triangular. The construction of such a parity check matrix is described more fully below in FIG. 6. Such a restriction results in negligible performance loss, and therefore, constitutes an attractive trade-off.
Modulator 205 maps the encoded messages from encoder 203 to signal waveforms that are transmitted to a transmit antenna 207, which emits these waveforms over the communication channel 103. Accordingly, the encoded messages are modulated and distributed to a transmit antenna 207. The transmissions from the transmit antenna 207 propagate to a receiver, as discussed below.
FIG. 4 is a diagram of a sparse parity check matrix, in accordance with an embodiment of the present invention. LDPC codes are long, linear block codes with sparse parity check matrix H(n−k)xn. Typically the block length, n, ranges from thousands to tens of thousands of bits. For example, a parity check matrix for an LDPC code of length n=8 and rate � is shown in FIG. 4. The same code can be equivalently represented by the bipartite graph, per FIG. 5.
From check nodes to bit nodes, each check node provides to an adjacent bit node an estimate (�opinion�) regarding the value of that bit node based on the information coming from other adjacent bit nodes. For instance, in the above example if the sum of n4, n5 and n8 �looks like� 0 to m1, then m1 would indicate to n1 that the value of n1 is believed to be 0 (since n1+n4+n5+n8=0); otherwise m1 indicate to n1 that the value of n1 is believed to be 1. Additionally, for soft decision decoding, a reliability measure is added.
H(n−k)xn=[A(n−k)xkB(n−k)x(n−k)],
a 00 i 0 +a 01 i 1 + . . . +a 0,k−1 i k−1 +p 0=0 Solve p 0, a 10 i 0 +a 11 i 1 + . . . +a 1,k−1 i k−1 +b 10 p 0 +p 1=0 Solve p 1 and similarly for p2, p3, . . . , pn−k−1. FIG. 7 is a graph showing performance between codes utilizing unrestricted parity check matrix (H matrix) versus restricted H matrix of FIG. 6. The graph shows the performance comparison between two LDPC codes: one with a general parity check matrix and the other with a parity check matrix restricted to be lower triangular to simplify encoding. The modulation scheme, for this simulation, is 8-PSK. The performance loss is within 0.1 dB. Therefore, the performance loss is negligible based on the restriction of the lower triangular H matrices, while the gain in simplicity of the encoding technique is significant. Accordingly, any parity check matrix that is equivalent to a lower triangular or upper triangular under row and/or column permutation can be utilized for the same purpose.
When 8-PSK (or similar higher order) modulation is utilized with a binary decoder, it is recognized that the three (or more) bits of a symbol are not received �equally noisy�. For example with Gray 8-PSK labeling, the third bit of a symbol is considered more noisy to the decoder than the other two bits. Therefore, the LDPC code design does not assign a small number of edges to those bit nodes represented by �more noisy� third bits of 8-PSK symbol so that those bits are not penalized twice.
d i = - E s N 0 ⁢ { ( r x - s i , x ) 2 + ( r y - s i , y ) 2 } ⁢ ⁢ i = 0 , 1 , � ⁢ ⁢ 7. The 8-PSK bit metric generator 307 communicates with the LDPC decoder 305 to exchange a priori probability information and a posteriori probability information, which respectively are represented as u, and a. That is, the vectors u and a respectively represent a priori and a posteriori probabilities of log likelihood ratios of coded bits.
e j =a j −u j j=0,1,2.
Next, 8-PSK symbol probabilities, pi i=0,1, . . . ,7, are determined.
*y j=−�(0,e j) j=0,1,2 where �(a,b)=max(a,b)+LUTf(a,b) with LUTf(a,b)=ln(1+e −|a−b|)*x j =y j +e j j=0,1,2*p 0 =x 0 +x 1 +x 2 p 1 =x 0 +x 1 +y 2 p 2 =x 0 +y 1 +x 2 p 3 =x 0 +y 1 +y 2 p 4 =y 0 +x 1 +x 2 p 5 =y 0 +x 1 +y 2 p 6 =y 0 +y 1 +x 2 p 7 =y 0 +y 1 +y 2 Next, the bit metric generator 307 determines a priori log likelihood ratios of the coded bits as input to LDPC decoder 305, as follows:
u 0=�(d 0 +p 0 ,d 1 +p 1 ,d 2 +p 2 ,d 3 +p 3)−�(d 4 +p 4 ,d 5 +p 5 ,d 6 +p 6 ,d 7 +p 7)−e 0 u 1=�(d 0 +p 0 ,d 1 +p 1 ,d 4 +p 4 ,d 5 +p 5)−�(d 2 +p 2 ,d 3 +p 3 ,d 6 +p 6 ,d 7 +p 7)−e 1 u 2=�(d 0 +p 0 ,d 2 +p 2 ,d 4 +p 4 ,d 6 +p 6)−�(d 1 +p 1 ,d 3 +p 3 ,d 5 +p 5 ,d 7 +p 7)−e 2 It is noted that the function �(.) with more than two variables can be evaluated recursively; e.g. �(a,b,c)=�(�(a,b),c).
The operation of the LDPC decoder 305 utilizing non-Gray mapping is now described. In step 1001, the LDPC decoder 305 initializes log likelihood ratios of coded bits, ν, before the first iteration according to the following (and as shown in FIG. 12A):
νn→k i =un, n=0,1, . . . , N−1, i=1,2, . . . , deg(bit node n)
Here, νn→k i denotes the message that goes from bit node n to its adjacent check node ki, un denotes the demodulator output for the bit n and N is the codeword size.
In step 1003, a check node, k, is updated, whereby the input ν yields the output w. As seen in FIG. 12B, the incoming messages to the check node k from its dc adjacent bit nodes are denoted by νn 1 →k, νn 2 →k, . . . , νn dc →k. The goal is to compute the outgoing messages from the check node k back to dc adjacent bit nodes. These messages are denoted by
wk→n 1 ,wk→n 2 , . . . ,wk→n dc , where wk→n i =g(νn 1 →k, νn 2 →k, . . . , νn i−1 →k, νn n+1 →k, . . . , νn dc →k).
g(a,b)=sign(a)�sign(b)�{min(|a|,|b|)}+LUTg(a,b),
where LUTg(a,b)=ln(1+e−|a+b|)−ln(1+e−|a−b|). Similar to function �, function g with more than two variables can be evaluated recursively.
Next, the decoder 305, per step 1005 outputs a posteriori probability information (FIG. 12C), such that:
a n = u n + ∑ j ⁢ w k j -> n . Per step 1007, it is determined whether all the parity check equations are satisfied. If these parity check equations are not satisfied, then the decoder 305, as in step 1009, re-derives 8-PSK bit metrics and channel input un. Next, the bit node is updated, as in step 1011. As shown in FIG. 14C, the incoming messages to the bit node n from its dν adjacent check nodes are denoted by wk 1 →n, wk 2 →n, . . . , wk dν →n The outgoing messages from the bit node n are computed back to dν adjacent check nodes; such messages are denoted by
νn→k 1 , νn→k 2 , . . . , νn→k dν , and computed as follows: v n -> k i = u n + ∑ j ≠ i ⁢ w k j -> n In step 1013, the decoder 305 outputs the hard decision (in the case that all parity check equations are satisfied):
c ^ n = { 0 , a n ≥ 0 1 , a n < 0 ⁢ ⁢ Stop ⁢ ⁢ if ⁢ ⁢ H ⁢ c ^ T = 0 The above approach is appropriate when non-Gray labeling is utilized. However, when Gray labeling is implemented, the process of FIG. 11 is executed.
FIG. 11 is a flow chart of the operation of the LDPC decoder of FIG. 3 using Gray mapping, according to an embodiment of the present invention. When Gray labeling is used, bit metrics are advantageously generated only once before the LDPC decoder, as re-generating bit metrics after every LDPC decoder iteration may yield nominal performance improvement. As with steps 1001 and 1003 of FIG. 10, initialization of the log likelihood ratios of coded bits, ν, are performed, and the check node is updated, per steps 1101 and 1103. Next, the bit node n is updated, as in step 1105. Thereafter, the decoder outputs the a posteriori probability information (step 1107). In step 1109, a determination is made whether all of the parity check equations are satisfied; if so, the decoder outputs the hard decision (step 1111). Otherwise, steps 1103-1107 are repeated.
Referring to FIG. 12B, the incoming messages to the check node k from dc adjacent bit nodes are denoted by νn 1 →k, νn 2 →k, . . . , νn dc →k. It is desired that the outgoing messages are computed from the check node k back to dc adjacent bit nodes; these outgoing messages are denoted by wk→n 1 , wk→n 2 , . . . , wk→n dc .
Under the forward-backward approach to computing these outgoing messages, forward variables, �1, �2, . . . , �dc, are defined as follows:
�1=ν1→k �2=g(�1,ν2→k) �3=g(�2,ν3→k) : : : �dc=g(�dc−1,νdc→k)
In step 1301, these forward variables are computed, and stored, per step 1303.
bdc=νdc→k bdc−1=g(bdc,νdc−1→k) : : : b1=g(b2,ν1→k)
In step 1305, these backward variables are then computed. Thereafter, the outgoing messages are computed, as in step 1307, based on the stored forward variables and the computed backward variables. The outgoing messages are computed as follows:
wk→1=b2 wk→i=g(�i−1,bi+1) i=2,3, . . . ,dc−1 wk→dc=�dc−1 Under this approach, only the forward variables, �2, �3, . . . , �dc, are required to be stored. As the backward variables bi are computed, the outgoing messages, wk→i, are simultaneously computed, thereby negating the need for storage of the backward variables.
FIG. 13B is a flowchart of process for computing outgoing messages between the check nodes and the bit nodes using a parallel approach, according to an embodiment of the present invention. For a check node k with inputs νn 1 →k, νn 2 →k, . . . , νn dc →k from dc adjacent bit nodes, the following parameter is computed, as in step 1311:
γk=g(νn 1 →k,νn 2 →k, . . . ,νn dc →k). It is noted that the g(.,.) function can also be expressed as follows:
g ⁡ ( a , b ) = ln ⁢ ⁢ 1 + ⅇ a + b ⅇ a + ⅇ b . Exploiting the recursive nature of the g(.,.) function, the following expression results:
γ k = ln ⁢ ⁢ 1 + ⅇ g ⁡ ( v n 1 -> k ⁢ �v n i - 1 -> k � v n i - 1 -> k ⁢ �v n d ⁢ ⁢ c -> k ) + v n i -> k ⅇ g ⁡ ( v n 1 -> k ⁢ �v n i - 1 -> k � v n i + 1 -> k ⁢ �v n d ⁢ ⁢ c -> k ) + ⅇ v n i -> k = ln ⁢ ⁢ 1 + ⅇ w k -> n i + v n i -> k ⅇ w k -> n i + ⅇ v n i -> k Accordingly, wk→n i can be solved in the following manner:
w k -> n i = ln ⁢ ⁢ ⅇ v n i -> k + γ k - 1 ⅇ v n i -> k - γ k - 1 - γ k The ln(.) term of the above equation can be obtained using a look-up table LUTx that represents the function ln|ex−1| (step 1313). Unlike the other look-up tables LUTf or LUTg, the table LUTx would likely requires as many entries as the number of quantization levels. Once γk is obtained, the calculation of wk→n i for all ni can occur in parallel using the above equation, per step 1315.
FIGS. 14A-14C are graphs showing simulation results of LDPC codes generated in accordance with various embodiments of the present invention. In particular, FIGS. 14A-14C show the performance of LDPC codes with higher order modulation and code rates of 3/4 (QPSK, 1.485 bits/symbol), 2/3 (8-PSK, 1.980 bits/symbol), and 5/6 (8-PSK, 2.474 bits/symbol).
The second approach to implementing LDPC codes is to physically realize only a subset of the total number of the nodes and use only these limited number of �physical� nodes to process all of the �functional� nodes of the code. Even though the LDPC decoder operations can be made extremely simple and can be performed in parallel, the further challenge in the design is how the communication is established between �randomly� distributed bit nodes and check nodes. The decoder 305 (of FIG. 3), according to one embodiment of the present invention, addresses this problem by accessing memory in a structured way, as to realize a seemingly random code. This approach is explained with respect to FIGS. 15A and 15B.
FIGS. 15A and 15B are diagrams of the top edge and bottom edge, respectively, of memory organized to support structured access as to realize randomness in LDPC coding, according to an embodiment of the present invention. Structured access can be achieved without compromising the performance of a truly random code by focusing on the generation of the parity check matrix. In general, a parity check matrix can be specified by the connections of the check nodes with the bit nodes. For example, the bit nodes are divided into groups of 392 (392 is provided for the purposes of illustration). Additionally, assuming the check nodes connected to the first bit node of degree 3, for instance, are numbered as a, b and c, then the check nodes connected to the second bit node are numbered as a+p, b+p and c+p, the check nodes connected to the third bit node are numbered as a+2p, b+2p and c+2p etc. For the next group of 392 bit nodes, the check nodes connected to the first bit node are different from a, b, c so that with a suitable choice of p, all the check nodes have the same degree. A random search is performed over the free constants such that the resulting LDPC code is cycle-4 and cycle-6 free.
The above arrangement facilitates memory access during check node and bit node processing. The values of the edges in the bipartite graph can be stored in a storage medium, such as random access memory (RAM). It is noted that for a truly random LDPC code during check node and bit node processing, the values of the edges would need to be accessed one by one in a random fashion. However, such an access scheme would be too slow for a high data rate application. The RAM of FIGS. 15A and 15B are organized in a manner, whereby a large group of relevant edges can be fetched in one clock cycle; accordingly, these values are placed �together� in memory. It is observed that, in actuality, even with a truly random code, for a group of check nodes (and respectively bit nodes), the relevant edges can be placed next to one another in RAM, but then the relevant edges adjacent to a group of bit nodes (respectively check nodes) will be randomly scattered in RAM. Therefore, the �togetherness,� under the present invention, stems from the design of the parity check matrices themselves. That is, the check matrix design ensures that the relevant edges for a group of bit nodes and check nodes are simultaneously placed together in RAM.
As seen in FIGS. 15A and 15B, each box contains the value of an edge, which is multiple bits (e.g., 6). Edge RAM, according to one embodiment of the present invention, is divided into two parts: top edge RAM (FIG. 15A) and bottom edge RAM (FIG. 15B). Bottom edge RAM contains the edges between bit nodes of degree 2, for example, and check nodes. Top edge RAM contains the edges between bit nodes of degree greater than 2 and check nodes. Therefore, for every check node, 2 adjacent edges are stored in the bottom RAM, and the rest of the edges are stored in the top edge RAM.
Continuing with the above example, a group of 392 bit nodes and 392 check nodes are selected for processing at a time. For 392 check node processing, q consecutive rows are accessed from the top edge RAM, and 2 consecutive rows from the bottom edge RAM. In this instance, q+2 is the degree of each check node. For bit node processing, if the group of 392 bit nodes has degree 2, their edges are located in 2 consecutive rows of the bottom edge RAM. If the bit nodes have degree d>2, their edges are located in some d rows of the top edge RAM. The address of these d rows can be stored in non-volatile memory, such as Read-Only Memory (ROM). The edges in one of the rows correspond to the first edges of 392 bit nodes, the edges in another row correspond to the second edges of 392 bit nodes, etc. Moreover for each row, the column index of the edge that belongs to the first bit node in the group of 392 can also be stored in ROM. The edges that correspond to the second, third, etc. bit nodes follow the starting column index in a �wrapped around� fashion. For example, if the jth edge in the row belongs to the first bit node, then the (j+1)st edge belongs to the second bit node, (j+2)nd edge belongs to the third bit node, and (j−1)st edge belongs to the 392th bit node.
With the above organization (shown in FIGS. 15A and 15B), speed of memory access is greatly enhanced during LDPC coding.
FIG. 16 illustrates a computer system 1600 upon which an embodiment according to the present invention can be implemented. The computer system 1600 includes a bus 1601 or other communication mechanism for communicating information, and a processor 1603 coupled to the bus 1601 for processing information. The computer system 1600 also includes main memory 1605, such as a random access memory (RAM) or other dynamic storage device, coupled to the bus 1601 for storing information and instructions to be executed by the processor 1603. Main memory 1605 can also be used for storing temporary variables or other intermediate information during execution of instructions to be executed by the processor 1603. The computer system 1600 further includes a read only memory (ROM) 1607 or other static storage device coupled to the bus 1601 for storing static information and instructions for the processor 1603. A storage device 1609, such as a magnetic disk or optical disk, is additionally coupled to the bus 1601 for storing information and instructions.
The computer system 1600 also includes a communication interface 1617 coupled to bus 1601. The communication interface 1617 provides a two-way data communication coupling to a network link 1619 connected to a local network 1621. For example, the communication interface 1617 may be a digital subscriber line (DSL) card or modem, an integrated services digital network (ISDN) card, a cable modem, or a telephone modem to provide a data communication connection to a corresponding type of telephone line. As another example, communication interface 1617 may be a local area network (LAN) card (e.g. for Ethernet� or an Asynchronous Transfer Model (ATM) network) to provide a data communication connection to a compatible LAN. Wireless links can also be implemented. In any such implementation, communication interface 1617 sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information. Further, the communication interface 1617 can include peripheral interface devices, such as a Universal Serial Bus (USB) interface, a PCMCIA (Personal Computer Memory Card International Association) interface, etc.
The network link 1619 typically provides data communication through one or more networks to other data devices. For example, the network link 1619 may provide a connection through local network 1621 to a host computer 1623, which has connectivity to a network 1625 (e.g. a wide area network (WAN) or the global packet data communication network now commonly referred to as the �Internet�) or to data equipment operated by service provider. The local network 1621 and network 1625 both use electrical, electromagnetic, or optical signals to convey information and instructions. The signals through the various networks and the signals on network link 1619 and through communication interface 1617, which communicate digital data with computer system 1600, are exemplary forms of carrier waves bearing the information and instructions.
The computer system 1600 can send messages and receive data, including program code, through the network(s), network link 1619, and communication interface 1617. In the Internet example, a server (not shown) might transmit requested code belonging to an application program for implementing an embodiment of the present invention through the network 1625, local network 1621 and communication interface 1617. The processor 1603 may execute the transmitted code while being received and/or store the code in storage device 169, or other non-volatile storage for later execution. In this manner, computer system 1600 may obtain application code in the form of a carrier wave.
The term �computer-readable medium� as used herein refers to any medium that participates in providing instructions to the processor 1603 for execution. Such a medium may take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 1609. Volatile media include dynamic memory, such as main memory 1605. Transmission media include coaxial cables, copper wire and fiber optics, including the wires that comprise bus 1601. Transmission media can also take the form of acoustic, optical, or electromagnetic waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, CDRW, DVD, any other optical medium, punch cards, paper tape, optical mark sheets, any other physical medium with patterns of holes or other optically recognizable indicia, a RAM, a PROM, and EPROM, a FLASH-EPROM, any other memory chip or cartridge, a carrier wave, or any other medium from which a computer can read.
Accordingly, the various embodiments of the present invention provide an approach for generating structured Low Density Parity Check (LDPC) codes, as to simplify the encoder and decoder. Structure of the LDPC codes is provided by restricting the parity check matrix to be lower triangular. Also, the approach can advantageously exploit the unequal error protecting capability of LDPC codes on transmitted bits to provide extra error protection to more vulnerable bits of high order modulation constellations (such as 8-PSK (Phase Shift Keying)). The decoding process involves iteratively regenerating signal constellation bit metrics into an LDPC decoder after each decoder iteration or several decoder iterations. The above approach advantageously yields reduced complexity without sacrificing performance.
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