Source: https://patents.google.com/patent/US8707130B2/en
Timestamp: 2018-07-20 13:08:17
Document Index: 584948547

Matched Legal Cases: ['Application No. 342663', 'Application No. 267844', '§ 1', 'art 563', 'art 563', 'art 563', 'art 563', 'art 563', 'art 563']

US8707130B2 - Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program - Google Patents
US8707130B2
US8707130B2 US12888184 US88818410A US8707130B2 US 8707130 B2 US8707130 B2 US 8707130B2 US 12888184 US12888184 US 12888184 US 88818410 A US88818410 A US 88818410A US 8707130 B2 US8707130 B2 US 8707130B2
US20110007565A1 (en )
A semiconductor device having multilevel memory cells is disclosed. In one embodiment, the device is operable to determine a state of a first bit of a memory cell by application of a first voltage to the memory cell, with the first voltage having a value to cause the memory cell to provide an output indicative of the state of the first bit. The device is further operable to select between a second voltage and a third voltage based on the output, and to determine a state of a second bit of the memory cell by application of the selected voltage to the memory cell, with the selected voltage having a value to cause the memory cell to provide an output indicative of the state of the second bit.
The present application is a continuation of U.S. application Ser. No. 11/513,907 , filed Aug. 31, 2006 (now U.S. Pat. No. 7,805,660), which is a continuation of U.S. application Ser. No. 10/642,764, filed Aug. 19, 2003 (now U.S. Pat. No. 7,139,895), which is a divisional of U.S. application Ser. No. 09/438,295, filed Nov. 12, 1999 (now U.S. Pat. No. 6,857,099), which is a divisional of U.S. application Ser. No. 08/931,519, filed Sept. 16, 1997 (now U.S. Pat. No. 6,023,781), which also claims the benefit of priority Japanese Application No. 342663, filed Dec. 6, 1996, and Japanese Application No. 267844, filed Sept. 18, 1996; the disclosures of each of the above-referenced applications are incorporated by reference herein in their entireties.
The semiconductor device applied with the second modification is a sixteen-level memory device, in which the threshold voltage of each memory cell is set to any of sixteen levels (0V, 1V, 1.25V, 1,5V, 1.75V, 2V, 2.25V, 2.5V, 2.75V, 3V, 3.25V, 3.5V, 3.75V, 4V, 4.25V, 4.5V) corresponding to four-bit data (0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111) to be stored. The second modification follows a specific coding standard in which a single error per bit of a code word can be corrected and two errors per bit of a code word can be detected.
a plurality of memory cells operable to store a corresponding plurality of charges to provide a corresponding plurality of memory cell voltages within ranges that correspond to values of two bits stored in individual ones of the plurality of memory cells;
determine a state of a first bit of the two bits of a corresponding one of the plurality of memory cells by application of a first voltage to the one of the plurality of memory cells, with the first voltage having a value to cause the one of the plurality of memory cells to provide an output indicative of the state of the first bit;
select between a second voltage and a third voltage based on the output; and
determine a state of a second bit of the two bits of the one of the plurality of memory cells by application of the selected voltage to the one of the plurality of memory cells, with the selected voltage having a value to cause the one of the plurality of memory cells to provide an output indicative of the state of the second bit.
the one of the plurality of memory cells includes a configuration to provide the output indicating that the first voltage has a value greater than a one of the plurality of memory cell voltages corresponding to the one of the plurality of memory cells or to provide the output indicating that the first voltage has a value less than the one of the plurality of memory cell voltages corresponding to the one of the plurality of memory cells.
the physical addresses of the ones of the plurality of memory cells have a corresponding second set of logical addresses within the logical address space of the device.
for individual ones of the plurality of memory cells, the memory cell voltage has a value of one of a first range of memory cell voltage, a second range memory cell voltage, a third range of memory cell voltage, or a fourth range of memory cell voltage, with the first voltage having a value between the second range of memory cell voltage and the third range of memory cell voltage, with the second voltage having a value between the first range of memory cell voltage and the second range of memory cell voltage, and with the third voltage having a value between the third range of memory cell voltage and the fourth range of memory cell voltage.
the circuit includes a configuration to determine the state of the first bit of the two bits as a logical 1 responsive to the first voltage having a value greater than the memory cell voltage and the circuit includes a configuration to determine the state of the first bit of the two bits as a logical 0 responsive to the first voltage having a value less than the memory cell voltage.
the circuit includes a configuration to determine the state of the second bit of the two bits as a logical 1 responsive to the second voltage having a value greater than the memory cell voltage or the third voltage having a value less than the memory cell voltage.
the circuit includes a configuration to determine the state of the second bit of the two bits as a logical 0 responsive to the second voltage having a value less than the memory cell voltage or the third voltage having a value greater than the memory cell voltage.
a plurality of memory cells operable to store a corresponding plurality of charges to provide a corresponding plurality of memory cell voltages within ranges that correspond to values of at least three bits stored in individual ones of the plurality of memory cells; and
determine a state of a first bit of the at least three bits of a corresponding one of the plurality of memory cells by application of a first voltage to the one of the plurality of memory cells, with the first voltage having a value to cause the one of the plurality of memory cells to provide an output indicative of the state of the first bit;
based on the state of the first bit, select between a second voltage and a third voltage; and
determine a state of a second bit of the at least three bits of the one of the plurality of memory cells by application of the selected voltage the one of the plurality of memory cells, with the selected voltage having a value to cause the one of the plurality of memory cells to provide an output indicative of the state of the second bit.
16. The device as recited in claim 14, wherein:
for individual ones of the plurality of memory cells, the memory cell voltage has a value of one of a first range of memory cell voltage, a second range memory cell voltage, a third range of memory cell voltage, a fourth range of memory cell voltage, a fifth range of memory cell voltage, a sixth range of memory cell voltage, a seventh range of memory cell voltage, or an eighth range of memory cell voltage, with the first voltage having a value between the fourth range of memory cell voltage and the fifth range of memory cell voltage.
the circuit includes a configuration to determine the state of the first bit of the at least three bits as a logical 1 responsive to the first voltage having a value greater than the memory cell voltage and the circuit includes a configuration to determine the state of the first bit of the at least three bits as a logical 0 responsive to the first voltage having a value less than the memory cell voltage.
US20110007565A1 true US20110007565A1 (en) 2011-01-13
US8707130B2 true US8707130B2 (en) 2014-04-22
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