Source: http://www.google.com/patents/US7177964?dq=7,172,682
Timestamp: 2014-04-18 05:47:19
Document Index: 576111082

Matched Legal Cases: ['Application No. 01', 'art 1', 'art 1', 'art 1', 'art 1', 'application No. 01815580']

Patent US7177964 - Multiple removable non-volatile memory cards serially communicating with a host - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsTwo or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are normally communicated between the...http://www.google.com/patents/US7177964?utm_source=gb-gplus-sharePatent US7177964 - Multiple removable non-volatile memory cards serially communicating with a hostAdvanced Patent SearchPublication numberUS7177964 B2Publication typeGrantApplication numberUS 11/205,342Publication dateFeb 13, 2007Filing dateAug 16, 2005Priority dateAug 17, 2000Fee statusPaidAlso published asCN1208735C, CN1455897A, DE1309919T1, DE60132780D1, DE60132780T2, EP1309919A2, EP1309919B1, EP1903448A2, EP1903448A3, EP1903448B1, EP2278475A2, EP2278475A3, EP2278476A2, EP2278476A3, EP2278476B1, EP2278477A2, EP2278477A3, EP2278478A2, EP2278478A3, EP2278479A2, EP2278479A3, EP2278479B1, EP2278480A2, EP2278480A3, EP2278480B1, EP2278481A2, EP2278481A3, EP2278481B1, EP2278482A2, EP2278482A3, EP2278483A2, EP2278483A3, EP2306326A1, EP2312449A1, EP2312449B1, US6820148, US6941403, US6948016, US7305505, US7590782, US7895377, US8015340, US8386678, US20040215862, US20040215863, US20060026324, US20070130405, US20080077719, US20090240854, US20100199032, US20110113158, US20130138846, WO2002015020A2, WO2002015020A3Publication number11205342, 205342, US 7177964 B2, US 7177964B2, US-B2-7177964, US7177964 B2, US7177964B2InventorsYoram Cedar, Micky Holtzman, Yosi PintoOriginal AssigneeSandisk CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (21), Non-Patent Citations (13), Referenced by (6), Classifications (27), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMultiple removable non-volatile memory cards serially communicating with a hostUS 7177964 B2Abstract Two or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are normally communicated between the host and the cards by a single circuit commonly connected between the host and all of the sockets but during initialization of the system a unique relative card address is confirmed to have been written into each card inserted into the sockets by connecting the command and status circuit to each socket one at a time in sequence. This is a fast and relatively simple way of setting card addresses upon initialization of such a system. According to a second aspect of the disclosure, the host adapts to transferring data between it and different cards of the system over at least two different number of the data lines commonly connected between the host and all of one or more sockets, each card permanently storing a host readable indication of the number of parallel data lines the card is capable of using. This allows increasing the rate of data transfer when the need justifies an increased card circuit complexity. According to a third aspect of the disclosure, a serial stream of data is sent over a number of data lines from one to many by alternately connecting bits of the stream to a particular number of individual lines.
1. A method of operating an enclosed electronics circuit card containing re-writable non-volatile memory therein and having a plurality of external electrical contacts, comprising:
transferring data to and from the memory from outside of the card through one or more of the external data contacts,
electronically storing within the memory card a read-only indication of the one or more external data contacts that are operable for transferring data to and from the memory, and
providing for the stored indication to be read through the external contacts, whereby data communication may be established with the memory through the indicated one or more contacts.
2. The method of claim 1, wherein the stored indication includes a number selected from the group of one, two or four of the external contacts.
3. The method of claim 1, wherein the stored indication includes a number selected from the group of one or four of the external contacts.
4. The method of claim 1, additionally comprising, when the stored indication is two or more of the contacts, of receiving and sending a stream of data therethrough during writing data into and reading of data from the memory, respectively, by alternately sequentially transmitting packets of multiple bits of the data stream in parallel through the indicated two or more contacts.
5. The method of claim 1, additionally comprising, when the stored indication is two or more of the contacts, of receiving and sending a stream of data therethrough during writing data into and reading of data from the memory, respectively, by alternately sequentially transmitting individual bits of the data stream in parallel through the indicated two or more contacts.
electronically storing within the memory card an address of the card in a manner to be readable through the external contacts, and
upon initialization of the card, generating a number within the card that is stored as the card address.
7. The method of claim 6, wherein generating a number includes generating a random number from a random number generator included within the card.
8. A method of operating an enclosed electronics circuit card containing re-writable non-volatile memory therein and having a plurality of external electrical contacts, comprising:
9. The method of claim 8, wherein generating a number includes generating a random number from a random number generator included within the card.
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of application Ser. No. 10/849,748, filed May 19, 2004, now U.S. Pat. No. 6,948,016, which in turn is a continuation of application Ser. No. 09/641,023, filed Aug. 17, 2000, now U.S. Pat. No. 6,820,148, which applications are incorporated herein in their entirety by this reference.
FIG. 6 is a flow diagram illustrating operation of the memory system of FIGS. 4 and 5A�D;
FIG. 11 is a flow diagram illustrating one aspect of operation of the memory system of FIGS. 7�9; and
FIG. 12 is a flow diagram illustrating another aspect of operation of the memory system of FIGS. 7�9.
DESCRIPTION OF THE MMC PRODUCT AND SYSTEM With reference to FIG. 1, an existing MMC card 10 of the type described in the Background above is insertable into a slot 19 of a socket 20. The card 10 includes a row of seven electrical contacts 11�17 in a surface of the card and extending along one of its short edges. The socket 20 includes seven mating contact pins 1�7 connected to respective lines 21�27. The card contact 12 serially receives command signals from a host and serially sends a response (status signals) to a host. Mating socket pin 2 is thus connected with a command/response (�CMD�) line 22. Serial data is received through the card contact 17 for storage in its non-volatile memory, and serial data is sent through the contact 17 when read from the memory. The line 27, connected to the socket pin 7 that mates with the card contact 17, is the socket's serial data (�DAT�) line. These two lines 22 and 27, along with a clock signal input line 25, which is connected with the card contact 15 through the socket pin 5, provide an interface with a host computer or other device for operating the memory system within the card 10. Three card contacts 13, 14 and 16 receive an operating voltage from a host system or device, connected through respective socket pins 3, 4 and 6 to external lines 23 (�Vss�), 24 (�Vdd�) and 26 (�Vss2�). Card contact 11, and thus the socket pin 1 and line 21, are not used but were included for possible future use.
Pertinent portions of the memory and controller system within each MMC card10 are illustrated in FIG. 2. An array 31 of flash EEPROM cells provides non-volatile storage of digital data. A controller 33 manages operation of the array 31 and interfaces with a host system through the card contacts 12�17. Data serially received through the contact 17 are written to a register 35, transferred in parallel into a data storage buffer memory 36, from the buffer 36 to the controller 33 and then to the memory cell array 31 for storage therein. Conversely, data read from the memory cell array 31 are transferred in parallel by the controller 33 into the buffer 36 and from the buffer 36 in parallel into the register 35. The read data are then serially transferred out of the register 35 through the card contact 17.
Such a memory system is illustrated in FIG. 3, wherein a host device 51, which can be a personal computer, hand-held organizer, digital camera, audio reproduction system, or similar type of device, is connected over lines 22�27 with a plurality of card sockets 53, 55 and 57 that receive respective MMC cards 59, 61 and 63. Such a multi-card system includes at least two such sockets and often many more. As mentioned above, commands and responses are communicated over a single CMD line 22 that is connected with the pin 2 of each of the sockets in the system. The unique relative address stored in the RCA register 42 (FIG. 2) of one of the cards 59, 61 or 63 inserted into the sockets is sent by the host 51 with or as part of the command to address only one of those cards to receive and act upon the command. Similarly, data is transferred between the host and the cards over the single DAT line 21 that is connected with the pin 7 of each of the sockets. A constant frequency clock signal is also connected (not shown in FIG. 3) from the host to pin 5 of each of the sockets over a single line 25. The MMC specification calls for the clock to be up to 20 Megahertz.
A modified system that makes it easier for individual addresses to be assigned to multiple cards, without having to change the cards' internal circuitry in any significant way, is illustrated in FIG. 4, where elements common with those of FIGS. 1�3 are given the same reference numbers. A host 51′ is similar to the host 51 (FIG. 3) but includes a controller 52 that interfaces differently with the memory cards' command/response lines. Instead of a common command and response line being connected to pin 2 of each of the sockets, separate lines 71, 73 and 75 are connected to pin 2 of respective sockets 53, 55 and 57. Each of the separate command/response lines 71, 73 and 75 is one output of switching logic 65 which operates to switch a single command/response line 67 of the controller 52 among the individual lines 71, 73 and 75 in response to a control signal from the host in a circuit 69. The permitted connections of the switching logic 65 are shown in FIGS. 5A�D. The switching logic 65 can select any one of the individual socket command/response lines 71,73 or 75 for connection by itself to the line 67, as shown in FIGS. 5A-C, respectively. In any of these cases, signals pass in both directions through the logic 65 between line 67 and the selected one of the lines 71, 73, 75 etc. In another connection illustrated in FIG. 5D, all of the lines 71, 73, 75 etc. are connected together to the line 67 to enable the host to simultaneously broadcast commands to all card sockets. The logic 65 preferably, however, allows only one card socket command/response line to be connected with the line 67 at a time when the host is receiving responses from a card. Of course, although three individual socket command/response lines are illustrated, two such lines will be used if the system contains only two card sockets. If the system contains more than three card sockets, more than three command/response lines are used, one for each socket.
A second aspect of the present invention is shown in FIGS. 7�12, wherein the data transfer feature of the new SD Card is described. The rate at which data is transferred between the host and an individual card is increased by increasing the number of data lines connected to each card socket over which data are simultaneously transferred. In this example, four data lines are shown, which contribute to increase the rate of data transfer by up to four. Data is transferred over only one of the multiple data lines between a host and an MMC card. In the specific implementation of the SD Card, the number of data lines used at one time is either one or four.
The SD Card 90 and mating socket 100 are shown in FIG. 7. Although the first aspect of the present invention, described above with respect to FIGS. 4�6, may be implemented with a card having the same number of contacts as the MMC card 10 of FIG. 1, this aspect of the present invention causes the SD Card to have an increased number of electrical contacts. The SD Card 90 has the same contacts 11�17 as the MMC card 10 of FIG. 1, and in the same relative positions, but also has two new contacts 91 and 92 added for the transmission of data. The spare contact 11 of the MMC card is now also used by the SD Card for data transfer. Thus, four contacts 11, 17, 91 and 92 are used by the SD Card for transferring data into and out of the memory within the card 90. A mating socket 100 (FIG. 7) similarly has the same pins 1�7 as the socket 20 of FIG. 1, plus two additional pins 8 and 9. The result is four data lines 27 (pin 7), 101 (pin 8), 102 (pin 9), and 21 (pin 1) connected to each card socket.
The modified system is shown in FIG. 8, where a host 51″ has been modified to enable simultaneous transfer of data over more than one data line to each of multiple sockets 104, 106 and 108 that individually have the structure of the socket 100 (FIG. 7). The four data lines 21, 27, 101 and 102 are commonly connected each of the sockets and to a multiplexer 105 through switching logic circuits 110, 111, 112 and 113. A single stream of data in a line 107 that is to be stored into a card inserted into one of the sockets 106�108 is alternately switched by the multiplexer, in response to a control signal from the host controller 52′ in a line 109, among the four switching logic circuits 110�113 in time sequence. Similarly, when data are being read from a card, such a single data stream is assembled in the line 107 by the multiplexer 105 switching between the circuits 110�113.
One of the switching logic circuits 110�113 is provided for each of the multiple data lines that are connected to the card sockets, circuit 110 for data line DAT 0, circuit 111 for data line DAT 1, circuit 112 for data line DAT 2 and circuit 113 for data line DAT 3. They are controlled by signals on the lines 114 to the host controller 52′. During a write operation to a card in any one of the multiple sockets 104, 106 and 108, each of the switching logic circuits 110�113 has all four of its outputs connected to its input. Thus, data to be written is broadcasted to all of the sockets. When data are being read from one of the cards, however, each of the circuits 110�113 is switched to connect to the input line only the output line that is connected to the socket in which the memory card being read is inserted.
In order to accommodate the multiple data lines, the data register 35 of FIG. 2 and its operation, are modified in the SD Card, in a specific example, in a manner shown in FIGS. 9 and 10A-E. During writing, the host controller 52′ (FIG. 8) generates a single stream of data in the line 107. Such a stream is illustrated in FIG. 10A, where the letters A, B, C etc. each represent one data bit. The multiplexer 105 connects the logic circuits 110�113 one at a time to the line 107 in sequence for the transfer of only one bit. This is indicated in FIG. 10B for the case of a memory card having four data contacts, and thus when all four of the data lines DAT 0, DAT 1, DAT 2 AND DAT 3 are being used. The multiplexer 105 sends the first bit A over data line DAT 0, the second bit B over data line DAT 1, the third bit C over data line DAT 2, the fourth bit D over DAT 3, and then starts over by sending the bit E to the data line DAT 0, and so forth. These four streams of data are received by the data register 35′ and reassembled into the data sequence of FIG. 10A, which is then transferred in parallel through circuits 38′ to a data buffer like the buffer 36 of FIG. 2. Each individual serial stream of data is preferably sent over its respective data line by accumulating its bits into blocks that each also include cyclic redundancy check (�CRC�) bits calculated from the block's data. Each block includes a start bit, then the data, followed by the CRC and then a stop bit, in a specific example.
In order to be able to use cards with different numbers of data lines in the same system, a read-only field is preferably provided in the individual cards that is read by the host to determine over how many data lines it can communicate with that card. In a specific implementation, this is included in an SD Card Configuration Register (�SCR�) that is added to the registers shown in FIG. 2 for the MMC card. The host 51′ reads this field upon power-up, an initialization at some other time or whenever a new card is inserted into a socket, and thereafter transfers data addressed to each card over the number of data lines that the card can accommodate. But since there is some cost involved to provide additional circuitry necessary for each added data line, some cards are designed to work with a lesser number of data lines. Conversely, the host can be designed to operate with a lesser number of data lines than possible. If the added speed of data transfer is not necessary for a particular application, then the added complexity and cost to provide the higher data transfer rates can be avoided, both in cards and in host systems.
The ability to dynamically select the width of the data bus between a host and one or more memory cards results in the host being able to maximize the transfer rate of data between it and whatever memory cards are inserted into the system. Although other techniques of breaking up a data stream between the multiple data lines are certainly possible, the techniques described above and illustrated in FIGS. 10A�10E are preferred for the adapting the host to cards with different data bus widths, to do so dynamically as cards are substituted or added, and even communicate with each of a mixture of cards having different bus widths by using the maximum number of data lines of the individual cards. Another technique is to alternate sending packets of multiple sequential data bits along each data line. But this requires some overhead to keep track of the packets and the like. It is simpler to alternate sequential bits of a data stream through multiple parallel data paths one bit at a time, as described above, particularly when the system needs to adapt to cards having different numbers of data lines. Indeed, this data transfer technique has other applications than the memory system being described here.
The flow chart of FIG. 11 illustrates one aspect of a method of operating the memory system of FIGS. 7�10E, wherein the host 51″ ascertains the number of data lines with which each card installed in the two or more sockets 104, 106 and 108 is designed to operate. In a first step 121, the host addresses one of the cards over the command/response line 22 by the card's relative address that has already been written in its RCA register 42 (FIG. 2). Next, in a step 125, the number of data lines for the card is read by the host from its SCR register. This number is then stored by the host, as indicated by a step 125, preferably in a table form. If all the cards in the sockets of the system have been read, the process ends but if not, a step 129 addresses another of the cards of the system and the steps 123 and 125 are repeated for that other card.
FIG. 12 is a flow chart that illustrates how the host 51″ uses the stored data of the number of data lines for the cards in the system. Whenever a particular card socket is addressed by the host, as indicated by a step 131 the host reads the number of data lines for that card from an internal table constructed by the process of FIG. 11. This is indicated by a step 133. The host then, as indicated by a step 135, operates the multiplexer 105 to transfer data over the number of the four data lines DAT 0, DAT 1, DAT 2 and DAT 3 that is read from that table. In a next step 137, data is transferred over that number of data lines, whether to or from the card. In the case of a card with only one data line, in a specific example, the host preferably transfers data with the card over the line 27 (DAT 0) since that utilizes the same card contact 17 as the MMC products, thus making the system compatible with MMC cards. MMC cards can be used in the system of FIGS. 8�10E as well as the SD Cards. The host preferably communicates with each card over only the DAT 0 line during initialization in order to determine whether the card is an MMC or SD card, and, if an SD Card, the number of data lines it uses and other information about the card that enables the system to operate efficiently.
The system of FIG. 8 can use either a single command/response line 22 (not shown) according to the MMC design or the multiple command/response line system described above with respect to FIGS. 4�6. This choice does not affect the structure or circuitry of the card.
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communicating with a hostUS8015340 *Apr 16, 2010Sep 6, 2011Sandisk CorporationEnhanced data communication by a non-volatile memory cardUS8386678 *Jan 18, 2011Feb 26, 2013Sandisk CorporationEnhanced data storage device* Cited by examinerClassifications U.S. Classification710/104, 710/9, 235/380, 711/115International ClassificationG06F3/08, G06K19/07, G06K17/00, G06F12/00, G06F12/06, G06F3/06, G06F13/14, G06F13/16, G06F13/38, G06F13/00Cooperative ClassificationG06F13/1694, G06F13/387, G06F13/385, G06F12/0661, G06F13/4239, G06F2212/2022, G06F12/0653, G06F2213/0052European ClassificationG06F13/38A4, G06F12/06K2, G06F12/06K2D, G06F13/38A2, G06F13/42C3ALegal EventsDateCodeEventDescriptionOct 23, 2013ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CEDAR, YORAM;HOLTZMAN, MICKY;PINTO, YOSI;REEL/FRAME:031462/0231Effective date: 20001004Owner name: SANDISK CORPORATION, CALIFORNIAJul 14, 2010FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - 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