Source: https://patents.google.com/patent/US8044898?oq=patent%3A3079728
Timestamp: 2018-03-17 04:45:56
Document Index: 599376407

Matched Legal Cases: ['art 9', 'art 9', 'art 8', 'art 10', 'art 9', 'art 9', 'art 10']

US8044898B2 - LED display apparatus having a column and row controller - Google Patents
LED display apparatus having a column and row controller
US8044898B2
US8044898B2 US11979042 US97904207A US8044898B2 US 8044898 B2 US8044898 B2 US 8044898B2 US 11979042 US11979042 US 11979042 US 97904207 A US97904207 A US 97904207A US 8044898 B2 US8044898 B2 US 8044898B2
US11979042
US20080252574A1 (en )
The display matrix part 9 comprises six parallel-connected LED circuits 7 a, 7 b, 7 c, and 7 f as shown in FIG. 1. Then, the LEDs 2 . . . form a matrix array. The display matrix circuit part 9 is connected to the power circuit part 8 at the hot line connection point and to the ground at the ground connection point. The LED circuit 7 a is constituted by serially-connecting five LEDs 2 . . . and a single first switching element 3 a and parallel-connecting a second switching element 4 . . . to each one of the LEDs 2 . . . . In this case, the first switching element 3 a is an n-type FET 3 aq and the second switching elements 4 . . . are n-type FETs 4 q . . . . In the figure, the number 23 presents a bidirectional zener diode connected between the gate and the sources of each FET 4 q . . . . The LED circuits 7 b, 7 c, 7 d, and 7 f other than the LED circuit 7 e have the same structure as the LED circuit 7 a. The LED circuit 7 e has the same structure as the LED circuit 7 a except that four LEDs 2 . . . are provided. In FIG. 1, the numbers 3 b, 3 c, 3 d, . . . , and 3 f present the first switching elements and the second switching elements 4 . . . are omitted in the LED circuits 7 b, 7 c, 7 d, . . . , and 7 f. The circuits Xs enclosed by dash-dot-dot lines in the LED circuits 7 b . . . other than the LED circuit 7 a are the same as Xs enclosed by dash-dot-dot lines in the LED circuit 7 a.
The LEDs 2 . . . in one or more LED circuits 7 a . . . extend over multiple digits (figures Na, Nb, . . . ) as shown in FIG. 2. For example, the LED circuit 7 b has two LEDs 2 . . . provided for the least significant digit (the figure Na), two LEDs 2 . . . provided for the next higher digit (the figure Nb), and one LED 2 provided for the most significant digit (the figure Nc). In FIG. 2, the circuit Xo enclosed by dash-dot-dot lines in the LED circuit 7 a and the open blocks Xo are the same. This arrangement of the LEDs 2 . . . advantageously allows the LED circuits 7 a . . . to easily have an equal control voltage and accordingly an equal luminance.
The control circuit part 10 comprises a column control circuit 10 v and a row control circuit 10 h controlling the columns and the rows of the display matrix circuit part 9, respectively. The column control circuit 10 v has a function to turn on/off the first switching elements 3 a of the display matrix circuit part 9, in other words a function to turn on the first switching elements 3 a for a given time period (Ts) in sequence. Therefore, the gates of the FETs 3 aq . . . are connected to the column control circuit 10 v.
On the other hand, the row control circuit 10 h has a function to simultaneously turn on/off a row La, Lb, Lc, . . . , or Le of six second switching elements 4 extending across the LED circuits 7 a, 7 b, 7 c, . . . , and 7 f, in other words a function to turn on/off a row La, Lb, Lc, . . . , or Le of six second switching elements 4 in correspondence with the first switching elements 3 a being turned on. To do so, the row control circuit 10 h has five third switching elements 5 a, 5 b, 5 c, . . . , and 5 e for simultaneously turning on/off a row La, Lb, Lc, . . . , or Le of six second switches 4 extending across the LED circuits 7 a, 7 b, 7 c, . . . , and 7 f as shown in FIG. 2. The third switching elements 5 a, 5 b . . . are connected to the constant current power source 8 p (the cathode of the constant current diode 22) via current limiting resistors Ra, Rb, Rc, . . . , and Re, respectively. In this case, the third switching elements 5 a, 5 b, . . . , and 5 e are n-type FETs 5 aq, 5 bq . . . . The number 24 presents a bidirectional zener diode connected between the gate and the sources of each FET 5 aq . . . . Then, the gates of the FET 4 q . . . are connected to the drains of the corresponding FET 5 aq, 5 bq . . . (see the circuit Xo in FIG. 2) and the gates of the FETs 5 aq, 5 bq . . . are connected to the row control circuit 10 h.
The third switching elements 5 a . . . and current limiting resistors Ra . . . are provided for the following reasons. The gate voltage for turning on the FETs 4 q . . . (second switching elements 4 . . . ) has to be higher than the source voltage at least by 1 [V]. The source voltage of the FETs 4 q . . . varies depending on the number of subsequent LEDs 2 . . . connected to be turned on and becomes higher as the number is increased. Then, the voltage for turning on the FET 4 q . . . must be very high in some cases. In such a case, the output port that cannot supply a higher voltage than the power voltage of the microcomputer (processor 41) may not be useful for controlling. Therefore, the gate voltage of the FETs 4 q . . . is supplied from the cathode of the constant current diode 22 via the FETs 5 aq, 5 bq . . . (third switching elements 5 a, 5 b . . . ) and the row control circuit 10 h is used to turn on/off the FETs 5 aq, 5 bq . . . . In this way, when the third switching elements 5 a, 5 b . . . consist of the FETs 5 aq, 5 bq . . . , respectively, the gate voltage of the FETs 5 aq, 5 bq . . . can be approximately 1 [V] provided that the source voltage is at the ground level. In this way, the FETs 5 aq . . . (third switch elements 5 a . . . ) can be controlled with low voltage and constant voltage using the output port of the microcomputer (processor 41) and the FETs 4 q . . . (second switching elements 4 . . . ) can also be controlled. The current limiting resistors Ra, Rb, . . . , and Re serve to prevent the supply current Ip from the constant current diode 22 from branching into the third switching elements 5 a . . . . With the above structure, the second switching elements 4 . . . can be turned on/off in a stable manner regardless of the number of the LEDs 2 . . . in each LED circuit 7 a . . . .
Furthermore, a fourth switching element 6 is connected between the constant current power source 8 p and the ground. The column control circuit 10 v (control circuit part 10) has a function to turn on the fourth switching element 6 for a given time period Tm . . . including the turn-off period To . . . of the first switching elements 3 a, 3 b . . . . The fourth switching element 6 is an n-type FET 6 q, the gate of which is connected to the column control circuit 10 v. The number 25 . . . presents a bidirectional zener diode connected between the gate and the source of the FET 6 q. The fourth switching element 6 serves as a dummy circuit for the LED circuits 7 a . . . to achieve a magnitude-stabilized (continuous) supply current Ip, thereby reducing the switching noise that occurs when the first switching elements 3 a . . . are turned on/off.
12. The LED display apparatus according to claim 11, wherein said connection includes a serial circuit of a direct current power source and a receiver in a two-line transfer system via a connection cable.
US11979042 2007-04-16 2007-10-30 LED display apparatus having a column and row controller Active 2030-07-16 US8044898B2 (en)
JP2007-106977 2007-04-16
JP2007106977A JP5180510B2 (en) 2007-04-16 2007-04-16 Led display
US20080252574A1 true US20080252574A1 (en) 2008-10-16
US8044898B2 true US8044898B2 (en) 2011-10-25
ID=39853258
US11979042 Active 2030-07-16 US8044898B2 (en) 2007-04-16 2007-10-30 LED display apparatus having a column and row controller
US (1) US8044898B2 (en)
JP (1) JP5180510B2 (en)
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CN104835437A (en) * 2015-05-19 2015-08-12 陕西赛雷博瑞新能源科技有限公司 Low-power-consumption controller controlling digital tube dynamic display and control method
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SAKAI, HIROYUKI;KOYAMA, TAKEHIRO;MURAMATSU, HIDEKI;AND OTHERS;REEL/FRAME:020109/0740;SIGNING DATES FROM 20070913 TO 20070914
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SAKAI, HIROYUKI;KOYAMA, TAKEHIRO;MURAMATSU, HIDEKI;AND OTHERS;SIGNING DATES FROM 20070913 TO 20070914;REEL/FRAME:020109/0740