Source: http://www.google.com/patents/US5917689?dq=6,957,233
Timestamp: 2014-04-18 06:45:55
Document Index: 124941050

Matched Legal Cases: ['application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08']

Patent US5917689 - General purpose EOS/ESD protection circuit for bipolar-CMOS and CMOS ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn apparatus and method for protecting integrated circuits from electrical overstress and eletrostatic discharge is provided. The apparatus includes a primary EOS/ESD protection device and a feedback circuit. The feedback circuit maintain the primary EOS/ESD protection device in an off state during normal...http://www.google.com/patents/US5917689?utm_source=gb-gplus-sharePatent US5917689 - General purpose EOS/ESD protection circuit for bipolar-CMOS and CMOS integrated circuitsAdvanced Patent SearchPublication numberUS5917689 APublication typeGrantApplication numberUS 08/710,183Publication dateJun 29, 1999Filing dateSep 12, 1996Priority dateSep 12, 1996Fee statusPaidPublication number08710183, 710183, US 5917689 A, US 5917689A, US-A-5917689, US5917689 A, US5917689AInventorsStephen T. English, Eric Nestler, Andrew H. OlneyOriginal AssigneeAnalog Devices, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (84), Non-Patent Citations (6), Referenced by (24), Classifications (9), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetGeneral purpose EOS/ESD protection circuit for bipolar-CMOS and CMOS integrated circuitsUS 5917689 AAbstract An apparatus and method for protecting integrated circuits from electrical overstress and eletrostatic discharge is provided. The apparatus includes a primary EOS/ESD protection device and a feedback circuit. The feedback circuit maintain the primary EOS/ESD protection device in an off state during normal operation of the integrated circuit and switches the primary protection device to an state when an EOS/ESD event occurs at a first input pad with respect to a second input pad of the integrated circuit.
What is claimed is: 1. A transient protection circuit for protecting a semiconductor device from EOS/ESD events, the transient protection circuit comprising:a first input adapted to connect to an Input/Output (I/O) pad of the semiconductor device; a second input adapted to connect to a reference supply voltage of the semiconductor device; a third input adapted to connect to a supply voltage of the semiconductor device; a first clamping circuit having first and second inputs and an output, the first input of the first clamping circuit being connected to the first input of the transient protection circuit and the output being connected to the second input of the transient protection circuit, the first clamping circuit being arranged to operate in one of a first and a second operational state in response to a value of a control signal received on the second input of the first clamping circuit, wherein in the first operational state, the first clamping circuit provides substantially a short circuit between the first input of the first clamping circuit and the output of the first clamping circuit and in the second operational state, the first clamping circuit provides substantially an open circuit between the first input of the first clamping circuit and the output of the first clamping circuit; and a first feedback circuit including: a first input coupled to the first input of the transient protection circuit, a second input coupled to the second input of the transient protection circuit, an output coupled to the second input of the first clamping circuit, a first switching device having a first input, a second input coupled to the third input of the transient protection circuit, and an output coupled to the second input of the first clamping circuit, the first input of the first switching device being connected to the first input of the transient protection circuit to provide substantially a short circuit between the first input of the first switching device and the output of the first switching device as soon as a voltage at the first input of the transient protection circuit with respect to the second input of the transient protection circuit exceeds a threshold voltage of the first switching device, and a pull down device having a first input coupled to the output of the first switching device, a second input coupled to the second input of the first switching device and an output coupled to the second input of the transient protection circuit, the pull down device being arranged such that, in the absence of an overvoltage condition at the first input of the transient protection circuit, a voltage across the pull down device from the first input of the pull down device to the output of the pull down device is substantially equal to zero; and wherein the first feedback circuit is arranged to provide the control signal having a first value to the first clamping circuit to select the first operational state in response to an overvoltage condition at the first input of the transient protection circuit with respect to the second input of the transient protection circuit being detected and to provide the control signal having a second value to the first clamping circuit to select the second operational state in response to the overvoltage condition at the first input of the transient protection circuit with respect to the second input of the transient protection circuit not being detected. 2. The transient protection circuit of claim 1, wherein the first switching device includes a PMOS transistor having a source, a gate and a drain respectively coupled to the first input of the first switching device, the second input of the first switching device and the output of the first switching device.
SUMMARY OF THE INVENTION Embodiments of the present invention provide an EOS/ESD protection circuit that overcomes the above-described limitations of prior art devices. Specifically, EOS/ESD protection circuits in accordance with embodiments of the present invention include a primary EOS/ESD protection device coupled to a feedback circuit that ensures that the primary EOS/ESD protection device is well-controlled and is turned on uniformly in response to an EOS/ESD event.
DETAILED DESCRIPTION An EOS/ESD protection device is disclosed in U.S. patent application Ser. No. 08/496,933 titled "Electrostatic Discharge Protection Circuit For Protecting CMOS Transistors on Integrated Circuit Processes" and assigned to the assignee of the present application. In the device disclosed, a PMOS transistor is used to turn on an NMOS transistor of an inverter when an ESD event occurs at the output of the inverter. The ESD event is discharged through the NMOS device. This protection device is used on inverters and the NMOS transistor of the inverter must be sufficiently robust to safely discharge the ESD current.
TABLE 2______________________________________ESD Test ResultsIntegrated  SampleCircuit  Size     Lowest Pass                      Lowest Pass                               Lowest PassUnder  Per ESD  Voltage HBM                      Voltage MM                               Voltage CDMTest   Model    Test (volts)                      Test (volts)                               Test (volts)______________________________________IC1    3        .+-.6500   .+-.400  .+-.1500______________________________________
All pins on each of the three samples of the integrated circuit were also tested for latch-up susceptibility using the test method outlined in Joint Electron Device Engineering Council (JEDEC) Standard Number 17 with the supply voltages for the integrated circuit under test set for a voltage of 7.0 volts. The testing was conducted initially with all input pins grounded and subsequently with all input pins set to 5.0 volts. Each of the input and output pins was tested using positive and negative current pulses having a 50 microsecond rise time, 10 millisecond duration, and an amplitude increased in .+-.50 milliamp increments from .+-.50 milliamps to .+-.300 milliamps. No latch-up conditions were detected.
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29, 2010FPAYFee paymentYear of fee payment: 12Dec 29, 2006FPAYFee paymentYear of fee payment: 8Jan 15, 2003REMIMaintenance fee reminder mailedDec 30, 2002FPAYFee paymentYear of fee payment: 4Sep 12, 1996ASAssignmentOwner name: ANALOG DEVICES, INC., MASSACHUSETTSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ENGLISH, STEPHEN T.;NESTLER, ERIC;OLNEY, ANDREW H.;REEL/FRAME:008159/0713;SIGNING DATES FROM 19960802 TO 19960830RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google