Source: http://www.google.com/patents/US6316738?dq=645576
Timestamp: 2017-06-25 14:41:34
Document Index: 590177853

Matched Legal Cases: ['arts 36', 'arts 36', 'art 36', 'art 36', 'art 36', 'art 36', 'art 36']

Patent US6316738 - Printed wiring board and manufacturing method thereof - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA printed wiring board in which an opening existing around a pad which is a photovia land is arranged so that it is not overlapped with the pad, the area of an opening existing around a pad and that of another opening are equalized, the quantity of resin which is filled in each opening or is equalized...http://www.google.com/patents/US6316738?utm_source=gb-gplus-sharePatent US6316738 - Printed wiring board and manufacturing method thereofAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6316738 B1Publication typeGrantApplication numberUS 08/894,342PCT numberPCT/JP1996/003718Publication dateNov 13, 2001Filing dateDec 19, 1996Priority dateJan 11, 1996Fee statusPaidAlso published asCN1098023C, CN1178625A, DE69636010D1, DE69636010T2, EP0817548A1, EP0817548A4, EP0817548B1, EP1677582A2, EP1677582A3, EP1677582B1, US6342682, WO1997025839A1Publication number08894342, 894342, PCT/1996/3718, PCT/JP/1996/003718, PCT/JP/1996/03718, PCT/JP/96/003718, PCT/JP/96/03718, PCT/JP1996/003718, PCT/JP1996/03718, PCT/JP1996003718, PCT/JP199603718, PCT/JP96/003718, PCT/JP96/03718, PCT/JP96003718, PCT/JP9603718, US 6316738 B1, US 6316738B1, US-B1-6316738, US6316738 B1, US6316738B1InventorsYoji Mori, Yoichiro KawamuraOriginal AssigneeIbiden Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (20), Non-Patent Citations (2), Referenced by (13), Classifications (30), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetPrinted wiring board and manufacturing method thereof
US 6316738 B1Abstract
What is claimed is: 1. A printed wiring board, comprising a conductor pattern which is formed in a mesh on one side or both sides of a base material and provided with plural openings where no conductor exists, a conductor pad provided among the openings of said conductor pattern and a filled resin layer formed by resin filled in each opening, wherein:
a surface of the filled resin layer and a surface of the conductor pad constitute a same plane, and the openings existing around the conductor pad are arranged so as not to be overlapped with said conductor pad. 2. A printed wiring board according to claim 1, wherein said conductor pad is utilized for a photovia land.
3. A printed wiring board, comprising a conductor pattern which is formed in a mesh on one side or both sides of a base material on which an adhesive layer for electroless plating is formed, the conductor pattern being provided with plural openings where no conductor exists, a conductor pad provided among the openings of said conductor pattern and a plating resist formed in each opening, wherein:
a surface of the plating resist and a surface of the conductor pad constitute a same plane, and the openings existing around the conductor pad are arranged so as not to be overlapped with said conductor pad. 4. A multilayer printed wiring board in which a photosensitive interlayer insulating layer is formed on a base material on which a metallic area which functions as a power plane or a ground plane is formed, a conductor circuit is formed on the interlayer insulating layer and the conductor circuit is connected to the metallic area via a via hole formed in the interlayer insulating layer, the multilayer printed circuit board further comprising:
a pad connected to the via hole, the pad being formed in said metallic area; a blank portion provided around said pad to partially separate said pad from said metallic area, wherein: said pad is electrically connected to at least one point in said metallic area. 5. A multilayer printed wiring board according to claim 4, wherein one of a filled resin layer and a plating resist layer is formed in said blank portion.
6. A method of manufacturing a multilayer printed wiring board including steps of:
forming a photosensitive interlayer insulating layer on a base material on which a metallic area which functions as a power plane or a ground plane is formed; providing a mask film where a pattern for forming a via hole is formed on the photosensitive interlayer insulating layer; forming the via hole in the photosensitive interlayer insulating layer by exposing through the mask film and developing; forming a conductor circuit and a conductive layer in the via hole; and forming a pad connected to the conductive layer of the via hole in a metallic area and at least one blank portion around said pad to partially separate said pad from said metallic area, thereby said pad is electrically connected to at least one point of said metallic area. 7. A method of manufacturing a multilayer printed wiring board according to claim 6, wherein:
the blank portion is formed by etching said metallic area around said pad, the method further comprising: filling resin in said blank portions, and polishing both a pad surface of the pad and a resin surface of the resin filled in the blank potion, thereby both the pad surface and the resin surface constitute a same plane. 8. A method of manufacturing a multilayer printed wiring board according to claim 6, wherein:
said metallic area and said pad are formed by electroless plating treatment after a plating resist layer is formed corresponding to the blank portion around the pad connecting to the via hole. 9. A multilayer printed wiring board in which a core material is provided with a through hole, an interlayer insulating layer is formed on the core material, a via hole with a conductive layer therein is formed in the interlayer insulating layer and the conductive layer of the via hole and the through hole are electrically connected, wherein:
the through hole and a land for said through hole are formed by a continuous conductor layer, the land for said through hole being formed in a substantially tear-like shape; and said conductive layer of the via hole is connected to the land through a narrow part of the land with the tear-like shape. 10. A multilayer printed wiring board according to claim 9, wherein:
a land for the via hole provided in said interlayer insulating layer is formed in a substantially tear-like shape; and an opening of said via hole is formed in a widened part of the land for the via hole with the tear-like shape. 11. A multilayer printed wiring board according to claim 9, wherein:
a land for the via hole provided in said interlayer insulating layer is formed in a substantially elliptic shape; and an opening of said via hole is formed at one end of the land for the via hole with the elliptic shape in a direction of a longer axis. 12. A multilayer printed wiring board according to claim 9, further comprising a pad formed on the interlayer insulating layer having a substantially tear-like shape, wherein:
a land for the via hole provided in said interlayer insulating layer is formed in a substantially tear-like shape; an opening of said via hole is formed in a widened part of the land for the via hole with the tear-like shape; and the conductive layer of said via hole is electrically connected to the pad. 13. A multilayer printed wiring board according to claim 9, wherein a plurality of said via holes are collectively formed within a pad formed on the interlayer insulating layer.
14. A multilayer printed wiring board in which a first interlayer insulating layer is formed on a base material on which a lower conductor circuit is formed, an intermediate conductor circuit including a pad is formed on the first interlayer insulating layer, a second interlayer insulating layer is further formed on the intermediate conductor circuit, an upper conductor circuit is formed on the second interlayer insulating layer and the lower and upper conductor circuits are electrically connected to the pad through via holes provided in both the first interlayer insulating layer and the second interlayer insulating layer, wherein:
said pad is a substantially elliptic shape; the via hole connected to the upper conductor circuit in the second interlayer insulating layer is connected to the pad at one end of the pad with the elliptic shape in a direction of a longer axis; and an opposite end of the pad constitutes a part of a land of the via hole in the first interlayer insulating layer to connect the pad to a lower conductor circuit. 15. A multilayer printed wiring board according to claim 14, wherein said elliptic shape of the pad is formed so that both sides opposite to each other in an ellipse or a rectangle draw an arc outward.
16. A multilayer printed wiring board according to claim 14, wherein:
a land for the via hole in the second interlayer insulating layer to connect the pad to said upper conductor circuit is formed in a substantially tear-like shape; and an opening of said via hole in the second interlayer insulating layer is formed in a widened part of the land with the tear-like shape. 17. A multilayer printed wiring board according to claim 14, wherein:
a land for the via hole in the second interlayer insulating layer to connect the pad to said upper conductor circuit is formed in a substantially elliptic shape; and an opening of said via hole in the second interlayer is formed at one end of the land with the elliptic shape in a direction of a longer axis. 18. A multilayer printed wiring board according to claim 14, wherein:
a land for the via hole in the second interlayer insulating layer to connect the pad to said upper conductor circuit is formed in a substantially tear-like shape; an opening of said via hole in the second interlayer insulating layer is formed in a widened part of the land; and said via hole in the second interlayer insulating layer is electrically connected to the pad. 19. A multilayer printed wiring board in which a first interlayer insulating layer is formed on a base material on which a lower conductor circuit is formed, an intermediate conductor circuit is formed on the first interlayer insulating layer, a second interlayer insulating layer is further formed on the intermediate conductor circuit, an upper conductor circuit is formed on the second interlayer insulating layer, a land for a via hole connected to the lower conductor circuit and a pad connected to the upper conductor circuit are provided in the intermediate conductor circuit and the land and the pad are electrically connected, wherein:
said pad and land are formed in a substantially tear-like shape; and both narrow parts in the pad and the land are mutually connected. 20. A multilayer printed wiring board in which an interlayer insulating layer is formed on a base material on which a lower conductor circuit is formed, an upper conductor circuit is formed on the interlayer insulating layer and the lower and upper conductor circuits are electrically connected through a via hole provided in the interlayer insulating layer, wherein:
a land for said via hole is formed in a substantially tear-like shape; and an opening of said via hole is formed in a widened part of the land. 21. A multilayer printed wiring board in which a base material is provided with a through hole, an interlayer insulating layer is formed on the base material, a via hole is formed in the interlayer insulating layer and the via hole and the through hole are electrically connected, wherein:
the through hole and a land for said through hole are formed by a continuous conductor layer, the land for said through hole being formed in a substantially elliptic shape. 22. A multilayer printed wiring board in which an interlayer insulating layer is formed on a base material on which a lower conductor circuit is formed, an upper conductor circuit is formed on the interlayer insulating layer and the lower and upper conductor circuits are electrically connected through a via hole provided in the interlayer insulating layer, wherein:
said lower conductor circuit includes a pad to which the via hole is connected, and the pad is formed in a substantially tear-like shape. 23. A multilayer printed wiring board in which an interlayer insulating layer is formed on a base material on which a lower conductor circuit is formed, an upper conductor circuit is formed on the interlayer insulating layer and the lower and upper conductor circuits are electrically connected through a via hole provided in the interlayer insulating layer, wherein:
said lower conductor circuit includes a pad to which the via hole is connected, and the pad is formed in a substantially elliptic shape. 24. A method of manufacturing a multilayer printed wiring board including steps of:
forming a photosensitive interlayer insulating layer on a base material on which a metallic area which functions as a power plane or a ground plane is formed; providing a via hole in the photosensitive interlayer insulating layer by exposing through a mask film and developing; forming a conductor pad connected to a conductive layer of the via hole in a metallic area and at least one blank portion around said pad to partially separate said pad from said metallic area, thereby said pad is electrically connected to at least one point of said metallic area; filling resin in said blank portion; and polishing both a pad surface of the pad and a resin surface of resin filled in the blank portion, thereby both the pad surface and the resin surface constitute a same plane. Description
As a result, the quantity of resin which can fill the exposed area 204L around the pad 203L is smaller than that of resin which can fill another exposed area 204 and when the exposed areas 204 and 204L are filled with resin, the quantity of filled resin overflowing from the exposed area 204L around the pad 203L is more than that overflowing from another exposed area 204 and even if the respective surfaces of the conductor circuit 203 and the filled resin layer 205 are polished so that they are smooth after the filled resin is hardened to be the filled resin layer 205, the filled resin 205L is left on the pad 203L as shown in FIG. 32 which is a sectional view viewed along a line B—B′ in FIG. 31.
Under such a situation, heretofore, the multilayer connecting structure of a multilayer printed wiring board is realized by connecting a connecting pad and a pattern via a via hole in order. Referring to FIG. 39, connection structure for connecting a connecting pad formed on the core material of a conventional multilayer printed wiring board and a pattern on an interlayer insulating layer provided on the core material via a via hole will be described below. FIGS. 39 show connection structure for connecting a connecting pad formed on the core material of a conventional multilayer printed wiring board and a pattern on an interlayer insulating layer via a via hole, FIG. 39 (A) is a plan showing a multilayer printed wiring board and FIG. 39 (B) is a sectional view showing the multilayer printed wiring board.
As shown in FIGS. 39 (A) and (B), a multilayer printed wiring board 300 is provided with a base material 301 which is a core material and a through hole 302 is formed in this base material 301. A conductor layer 303 is formed on the inner wall of the through hole 302 by through hole plating and a circular through hole land 304 connected to the conductor layer 303 is provided on the upper and lower sides of the base material 301. The through hole land 304 is connected to a circular connecting pad 306 on the upper surface of the base material 301 via a connecting pattern 305. A connecting pad 306 is also formed in a position separated from the through hole land 304 on the lower surface of the base material 301. Resin 307 is filled inside the through hole 302 or between the through hole land 304, the connecting pattern 305, the connecting pad 306 or other circuit pattern on the double sides of the base material 301.
Next, referring to FIG. 40, connection structure for connecting a connecting pad formed on the interlayer insulating layer and a pattern on another interlayer insulating layer via a via hole will be described below. FIGS. 40 show connection structure for connecting a connecting pad formed on an interlayer insulating layer in a conventional multilayer printed wiring board and a pattern on another interlayer insulating layer via a via hole, FIG. 40 (A) is a plan showing a printed wiring board and FIG. 40 (B) is a sectional view showing the printed wiring board.
As shown in FIGS. 40 (A) and (B), a printed wiring board 320 is provided with a base material 321 which is a core material, a connecting pad 322 is formed on the upper surface of this base material 321 and a filled resin layer 323 is provided around the connecting pad 322. An interlayer insulating layer 324 is formed on the upper surface of the connecting pad 322 and the filled resin layer 323, a via hole 326 inside which a conductor layer 325 is formed is provided in a position of the interlayer insulating layer 324 opposite to the connecting pad 322 and a circuit pattern 327 connected to the conductor layer 325 is formed. A connecting pad 328 is formed at the end of the circuit pattern 327 as shown at the left end in FIGS. 40 (A) and (B). Hereby, the connecting pad 322 on the base material 321 is connected to the connecting pad 328 on the interlayer insulating layer 324 via the conductor layer 325 of the via hole 326 and the circuit pattern 327. A plating resist layer 329 required when the conductor layer 325, the circuit pattern 327 and the connecting pad 328 are formed by electroless plating is formed around the conductor layer 325 of the via hole 326, the circuit pattern 327 and the connecting pad 328.
(3) Further, to achieve the above third object, a multilayer printed wiring board according to the present invention is constituted so that a through hole land is in the shape of a tear and a via hole is connected at the narrower portion of the tear-shaped land based upon a multilayer printed wiring board wherein its core material is provided with a through hole, an interlayer insulating layer is formed on the core material, a via hole is formed in the interlayer insulating layer and the via hole and the through hole are electrically connected. In this multilayer printed wiring board, a through hole land is in the shape of a tear, as a via hole is connected in the through hole land, the through hole land and a pad for connecting to the via hole are integrated and therefore, the area for connection of the bottom of the via hole can be enlarged. Hereby, when an interlayer insulating layer which is formed on a core material and on which the mask film is stuck is exposed with the light blocking pattern of the mask film corresponding to a part in which the via hole is to be formed to form the via hole, the range of allowable misregistration of the light blocking pattern of the mask film to a part in which the via hole is to be formed is greatly widened and even if the pad and the mask film are dislocated in the direction of the narrower side of the tear-shaped pad if misregistration is caused between a pad and the master film, the via hole and the pad can be stably connected reliably. The narrower side of the tear-shaped pad means Y side in FIG. 17 (A).
A multilayer printed wiring board according to the present invention is constituted so that a land for a via hole provided in the above interlayer insulating layer is in the shape of a tear and the opening of the via hole is formed in a part in which the tear-shaped land is widened. In such a multilayer printed wiring board, a through hole land and a via hole land are both in the shape of a tear, as the opening of the via hole is formed in the enlarged part of such a land, an allowable range in which the opening of the via hole is formed on the pad is enlarged, compared with the case of the above printed wiring board, therefore the range of allowable misregistration of the light blocking pattern of the mask film to a part in which the via hole is to be formed is greatly widened and if misregistration is caused between the pad and the mask film, the via hole and the pad can be also stably connected reliably independent of the direction of misregistration, for example both on the narrower side and on the enlarged side of the tear shape. The enlarged side of the tear shape means X side in FIG. 17 (A).
A multilayer printed wiring board according to the present invention is also constituted so that a land for a via hole for connecting to the above upper conductor circuit is in the shape of a tear, the opening of the via hole is formed at the enlarged part, and the land is electrically connected to a tear-shaped pad formed on an interlayer insulating layer. In such a multilayer printed wiring board, a pad for an intermediate layer conductor circuit is elliptic in addition to the above constitution, a land for a via hole for connecting to the upper conductor circuit is in the shape of a tear and as the opening of the via hole is formed in the enlarged part, the area for connection of the bottom of the via hole connected to the pad can be enlarged. Hereby, when an interlayer insulating layer which is formed on a base material and on which a mask film is stuck is exposed with the light blocking pattern of the mask film corresponding to a part in which a via hole is to be formed to form the via hole, the range of allowable misregistration of the light blocking pattern of the mask film to a part in which the via hole is to be formed is greatly widened and if misregistration is caused between a pad and the mask film, the via hole and the pad can be also stably connected reliably even if misregistration is caused in the direction of the narrower side of the tear- shaped pad.
Further, a multilayer printed wiring board according to the present invention is constituted so that a pad and a land are in the shape of a tear and they are connected each other on the narrower side of the tear shape based upon a multilayer printed wiring board wherein an interlayer insulating layer is formed on a core material on which the lower conductor circuit is formed, an intermediate layer conductor circuit is formed on the interlayer insulating layer, an interlayer insulating layer is further formed on the intermediate layer conductor circuit, the upper conductor circuit is formed on the interlayer insulating layer, a land for a via hole for connecting to the lower conductor circuit and a pad for connecting to the upper conductor circuit are provided to the above intermediate layer conductor circuit and the above land and the pad are electrically connected. In such a multilayer printed wiring board, as a pad connected to the upper conductor circuit formed on the intermediate layer conductor circuit and a land for a via hole for connecting to the lower conductor circuit are both in the shape of a tear and each pad and the land are connected each other on the narrower side, the area for connection of the bottom of the via hole connected to a pad can be enlarged. Hereby, when an interlayer insulating layer which is formed on a base material and on which a mask film is stuck is exposed with the light blocking pattern of the mask film corresponding to a part in which a via hole is to be formed to form the via hole, the range of allowable misregistration of the light blocking pattern of the mask film to a part in which the via hole is to be formed is greatly widened and if misregistration is caused between a pad and the mask film, the via hole and the pad can be also stably connected reliably even if misregistration is caused in the direction of the narrower side of the tear- shaped pad. Stress is hardly converged to a connection in which the pad and the land are connected each other and hereby, an interlayer insulating layer can be also prevented from being cracked in a heat cycle.
FIG. 17 (A) is a plan showing the multilayer printed wiring board;
FIG. 17 (B) is a sectional view showing the multilayer printed wiring board;
FIG. 17 (C) is a sectional view showing the multilayer printed wiring board with a different separation between the through a hole and the via hole;
FIG. 17 (D) is a plan view showing the multilayer printed circuit board with a different separation between the through hole and the via hole.
FIG. 20 is a plan showing a multilayer printed wiring board, equivalent to a fourth embodiment;
FIG. 21 (A) is a plan showing the multilayer printed wiring board;
FIG. 21 (B) is a sectional view showing the multilayer printed wiring board;
FIG. 25 (A) is a plan showing the multilayer printed wiring board;
FIG. 25 (B) is a sectional view showing the multilayer printed wiring board;
FIG. 26 show connection structure in which a connecting pad on a base material and a pattern on an interlayer insulating layer are connected via a via hole in a multilayer printed wiring board equivalent to a tenth embodiment,
FIG. 26 (A) is a plan showing the multilayer printed wiring board;
FIG. 26 (B) is a sectional view showing the multilayer printed wiring board;
FIG. 26 C-E depict variations in the shape pf the via hole as a function of misregistration
FIG. 27 (A) is a plan showing the multilayer printed wiring board;
FIG. 27 (B) is a sectional view showing the multilayer printed wiring board; and FIGS. 27 (C) and 27 (D) are plans showing the multilayer printed wiring board provided with different connection structures.
FIG. 39 (A) is a plan showing the multilayer printed wiring board;
FIG. 39 (B) is a sectional view showing the multilayer printed wiring board;
FIG. 40 (A) is a plan showing the printed wiring board; and
FIG. 40 (B) is a sectional view showing the printed wiring board.
Next, the copper-clad laminate 10 in which a conductor circuit 12 is formed out of the copper layer 9 is obtained by laminating a photosensitive dry film where the pattern of the conductor circuit 12 which is a first conductor circuit is printed on the double sides of the copper-clad laminate 10 and etching after exposure and development. FIG. 2 shows the copper-clad laminate 10 in which the conductor circuit 12 is formed. FIG. 3 (A) is a sectional view of the copper-clad laminate 10 viewed along a line A—A′ in FIG. 2. FIGS. 4 to 11 are also sectional views of the copper-clad laminate 10 viewed along the line A—A′ in FIG. 2.
Further, as shown in FIG. 3 (B), a plating resist 16L for electroless plating is formed in the opening 8L so as to form conductor circuits in a mesh by electroless plating.
Next, as shown in FIG. 10, a second resin layer 18 consisting of the same resin as the first resin layer 14 and a second adhesive layer 19 consisting of the same resin as the first adhesive layer 15 are formed on the surface of the plating resist 16 and the conductor circuit 17A as also shown in FIG. 5 and the surface of the second adhesive layer 19 is roughed by removing a resin particle dispersed in the second adhesive layer 19 by acid or an oxidizing agent so as to form an anchor in the shape of an octopus trap. As the second resin layer 18 and the second adhesive layer 19 are provided with electrical insulating property, both function as an interlayer insulating layer.
(4) The composition of resin constituting the first resin layer 14 shown in FIG. 5 is produced as follows: That is, a compound of 70 weight of acryl equivalent to 25% and cresol novolac epoxy resin (manufactured by Nihon Chemical, molecular weight: 2500) dissolved in diethylene glycol dimethyl ether (DMDG), polyether sulfonate (PES) of 30 weight, an imidazole hardening agent of 4 weight (manufactured by Shikoku Chemical, trade name: 2E4MZ-CN), caprolactone denatured tris (acroxyethyl) isocyanate which is a photosensitive monomer of 10 weight (manufactured by Toa Gosei, trade name: Aronix M325), benzophenone of 5 weight (manufactured by Kanto Chemical) as an initiator and Michler's ketone of 0.5 weight (manufactured by Kanto Chemical) as a sensitizing agent are mixed adding NMP, are adjusted using a disperser so that their viscosity is 1.2 Pa·s (23±10° C.) and are kneaded by a three- roll kneader.
The adhesive solution for forming the first adhesive layer 15 shown in FIG. 5 is produced as follows: That is, a compound of 70 weight of acryl equivalent to 25% and cresol novolac epoxy resin (manufactured by Nihon Chemical, molecular weight: 2500) dissolved in diethylene glycol dimethyl ether (DMDG), polyether sulfonate (PES) of 30 weight, an imidazole hardening agent of 4 weight (manufactured by Shikoku Chemical, trade name: 2E4MZ-CN), caprolactone denatured tris (acroxyethyl) isocyanate which is a photosensitive monomer of 10 weight (manufactured by Toa Gosei, trade name: Aronix M325), benzophenone of 5 weight (manufactured by Kanto Chemical) as an initiator and Michler's ketone of 0.5 weight (manufactured by Kanto Chemical) as a sensitizing agent are mixed, an epoxy resin particle of 35 weight with the mean particle diameter of 5.5 μm (manufactured by Toray Industries, trade name: Trepal) and the epoxy resin particle of 5 weight with the mean particle diameter of 0.5 μm) are added to these mixture and mixed adding NMP, they are adjusted using a disperser so that their viscosity is 1.2 Pa·s (23±1° C.) and are kneaded by a three-roll kneader.
The composition of resin constituting the first resin layer 14 produced as described above is applied using a roll coater and dried (prebaked) at the temperature of 60° C. after leaving it for 20 minutes in a horizontal state. The adhesive solution of the first adhesive layer 15 produced as described above is also similarly applied using a roll coater and dried (prebaked) at the temperature of 60° C. after leaving it for 20 minutes in a horizontal state.
Epoxy resin is used for the above first resin layer 14 and the above first adhesive layer 15, however, in addition, thermosetting resin such as polyimide resin, bismaleimidetriazine resin and phenol resin and photosensitive resin of these, thermoplastic resin such as polyether sulfonate, a complex of thermoplastic resin and thermosetting resin and a complex of photosensitive resin and thermoplastic resin may be used. Epoxy acrylate generated by reacting epoxy resin with acrylic acid or methacrylic acid and a complex of epoxy acrylate and polyether sulfonate are desirable out of these. It is desirable that such epoxy acrylate is obtained by reacting 20 to 80% of all epoxy radicals with acrylic acid or methacrylic acid.
Further, It is desirable that a resin particle for the first adhesive layer 15 is selected out of (1) heat-resistant resin powder 10 μm or less in a mean particle diameter, (2) a condensed particle generated by condensing heat-resistant resin powder 2 μm or less in a mean particle diameter, (3) a mixture of heat-resistant resin powder 10 μm or less in a mean particle diameter and heat-resistant resin powder 2 μm or less in a mean particle diameter and (4) a psuedoparticle generated by depositing at least one of heat-resistant resin powder 2 μm or less in a mean particle diameter and/or inorganic powder on the surface of heat-resistant resin powder 2 to 10 μm in a mean particle diameter. It is because these can form a complicated anchor that these are used.
(6) The catalytic nucleus shown in FIG. 7 is beforehand processed in the solution of PdCl2.2H2O 0.2 g/l, SnCl2,2 H2O 15 g/l or HCl 30 g/l. For liquid photosensitive resist, liquid photosensitive resist on the market is used and applied so that a layer is 30 μm thick. The plating resist 16 is formed so that the width is 50 μm.
For liquid photosensitive resist, a composition consisting of epoxy acrylate generated by reacting epoxy resin with acrylic acid or metacrylic acid and an imidazole hardening agent and a composition consisting of epoxy acrylate, polyether sulfonate and an imidazole hardening agent may be used. It is desirable that the ratio of epoxy acrylate and polyether sulfonate is approximately 50 to 50 to 80 to 20, it is because if epoxy acrylate is too much, flexibility is reduced and if it is too small, the characteristics of photosensitivity, resistance to a base, resistance to acid and resistance to an oxidizing agent are deteriorated.
Metallic salt . . . CuSO4.5H2O ; 6.0 mM (1.5 g/l)
. . . NiSO4.6H2O ; 95.1 mM (25 g/l)
Complexing agent . . . Na3C6H5O7; 0.23 M (60 g/l)
Reducing agent . . . NaPH2O2.H2O ; 0.19 M (20 g/l)
pH modifier . . . NaOH; 0.75 M (pH=9.5)
Stabilizer . . . Nitrate; 0.2 mM (80 ppm)
A copper-nickel-phosphorus plated thin film 17B approximately 1.7 μm thick is formed in a part in which the resist 16 is not formed by performing primary plating under the conditions described above. Afterward, the base material is lifted out of the plating bath and plating bath which adheres on-the surface is washed away by water.
Metallic salt . . . CuSO4.5H2O; 8.6 mM
Complexing agent . . . TEA; 0.15 M
Reducing agent . . . HCHO; 0.02 M
Others . . . Stabilizer such as bipyridyl and potassium ferrocyanide a little bit
To reduce a metallic ion to a metallic element, a reducing agent is used and it is desirable that at least one of aldehyde, hypophosphite (called phosphinate), hydrobonate and hydrazine is selected for a reducing agent. It is because these reducing agents are water soluble and excellent in reducing power. If hypophosphite is used, nickel can be precipitated.
When the pad 12L of the conductor circuit 12 in the multilayer printed wiring boards 1 in the first embodiment and in the comparative example is observed with an optical microscope, the filled resin 13 is left on the pad 12L of the conductor circuit 12 for connecting the conductor circuits 12 and 17A in the multilayer printed wiring board 1 in the comparative example. In the meantime, in the multilayer printed wiring board 1 equivalent to the first embodiment, no filled resin 13 cannot be verified on the pad 12L of the conductor circuit 12 for connecting the conductor circuits 12 and 17A which is equivalent to the same location as the above- described.
Next, a printed wiring board and its manufacturing method equivalent to a second embodiment will be described referring to FIGS. 12 to 16. First, the structure of the printed wiring board equivalent to the second embodiment will be described referring to FIGS. 12 (A), 12 (B) and 13. FIGS. 12 are sectional views showing the printed wiring board and FIG. 13 is a plan showing the printed wiring board.
As shown in FIGS. 12 and 13, a printed wiring board 31 is constituted by a base material 35 on which a metallic area 32 with large area such as a power plane and a ground plane, a connecting pad 33 with normal area which is smaller than the area of the metallic area 32 and a predetermined circuit pattern are formed as a core. In this embodiment, a copper-clad clad laminate where copper foil is laminated on the single side or the double sides of the base material 35 is used and the metallic area 32, the connecting pad 33 and the circuit pattern 34 are formed on the single side or the double sides by applying predetermined etching to the copper-clad laminate.
The form of the blank portion 36 will be described in details referring to FIG. 13. As shown in FIG. 13, the blank portion 36 is constituted by four arc-shaped window parts 36A into which a circular window with predetermined width is divided. A conductor 37 partitioned by the inner circle and separated from the metallic area 32 by the blank portion 36 is formed so that the area of the conductor is larger than that of the mask area 42 of the mask film 41 and the center of the conductor 37 is coated with the mask film via the mask area 42 with the mask film 41 stuck on the interlayer insulating layer 39. It is desirable that the diameter of the inner circle of the blank portion 36 is 125 to 350 μm, the diameter of the outer circle is 225 to 800 μm and an interval between the windows 36A is approximately 50 to 250 μm.
As described above, an interlayer insulating layer 39 is applied and formed on each upper surface of the metallic area 32, the connecting pad 33, the circuit pattern 34 and the filled resin layer 36 or a plating resist layer 38′ which constitute one surface. As the filled resin layer 38 or the plating resist layer 38′ is formed between blank portions 36, between the metallic area 32 and the circuit pattern 34, between the circuit patterns 34 and between the connecting pad 33 and the circuit pattern 34 and each upper surface constitutes one surface as described above when such an interlayer insulating layer 39 is applied and formed, the interlayer insulating layer 39 can be uniformly applied and formed. The interlayer insulating layer 39 can be applied and formed using a variety of photosensitive resin and for example, for resin material for forming the interlayer insulating layer 39, an adhesive for electroless plating is suitable. For an adhesive for electroless plating, an adhesive generated by dispersing a heat-resistant resin particle soluble in acid or an oxidizing agent in heat-resistant resin refractory in acid or an oxidizing agent can be used. The adhesive for electroless plating is provided with the same composition as an adhesive described in Japanese published examined patent applications No. Hei 4-55555, No. Hei 5- Hei 18476 and No. Hei 7-34505.
2) three-layer structure consisting of interlayer insulating layers provided between the upper and lower conductor circuits in which filling resin material is filled between the interlayer insulating layer and the lower conductor circuit, the respective surfaces of the lower conductor circuit and this filled rein material are equalized in a level, a heat-resistant resin layer refractory in acid or an oxidizing agent is formed on it, further an adhesive for electroless plating generated by dispersing a heat-resistant resin particle soluble in acid or an oxidizing agent in heat- resistant resin refractory in acid or an oxidizing agent is formed on it.
Next, a method of manufacturing the printed wiring board 31 constituted as described above will be described referring to FIG. 16. FIG. 16 is a process drawing showing a manufacturing process of the printed wiring board 31. As shown in FIG. 16 (A), first, a base material on which a metallic area 32 with large area such as a power pattern and a ground pattern, plural blank portions 36 formed in the metallic area 32 consisting of four arc-shaped window parts 36A (in the center of each window part 36A, a conductor 37 exists) in which no conductor exists, a connecting pad 33 and a circuit pattern 34 are formed is manufactured by applying predetermined etching to a copper-clad laminate.
Next, filling resin is applied on the surface of the base material 35 and a filled resin layer 38 formed by filling resin in the window parts of each blank portion 36, between the metallic area 32 and the circuit pattern 34, between the circuit patterns 34 and between the connecting pad 33 and the circuit pattern 34 is formed as shown in FIG. 16 (B). Further, as in this state, the irregularities of the filled resin exist on the surface of the base material 35, the surface of the base material 35 is polished by a well-known method for polishing. Hereby, the filled resin layer 38, the metallic area 32, the connecting pad 33 and the circuit pattern 34 constitute one surface as shown in FIG. 16 (C).
Next, an interlayer insulating layer 39 is applied and formed by applying photosensitive resin on the respective surfaces of the metallic area 32, the connecting pad 33, the circuit pattern 34 and the filled resin layer 38 which are polished so that they are at the same level in the above process as shown in FIG. 16 (D). At this time, as the respective surfaces of the filled resin layer 38, the metallic area 32, the connecting pad 33 and the circuit pattern 34 are at the same level, the interlayer insulating layer 39 can be applied and formed so that the thickness is uniform.
Further, a mask film 41 is stuck on the interlayer insulating layer 39 so that the mask area 42 of the mask film 41 is opposite to the conductor 37 and the connecting pad 33 in the metallic area 32. Afterward, light from a light source is radiated from over the mask film 41 to expose the interlayer insulating layer 39 as shown in FIG. 16 (E). At this time, as described above, as the interlayer insulating layer 39 is applied and formed so that the thickness is uniform on the metallic area 32 and the filled resin layer 38, the interlayer insulating layer 39 can be exposed on the boundary of the mask area 42 of the mask film 41 at satisfactory exposure resolution. The blank portion 36 in which no conductor exists consisting of each window part 36A is formed around the conductor 37 opposite to the mask area 42 and as the filled resin layer 38 is formed in each window part 36A, a great deal of light radiated as described above closely outside the mask area 42 is absorbed in the filled resin layer 38 and is not scattered, and light scattered on the metallic area 32 outside the blank portion 36 is hardly incident to the interlayer insulating layer 39 existing under the mask area 42. Hereby, as the interlayer insulating layer 39 can be exposed on the boundary of the mask area 42 at satisfactory resolution as described above, the interlayer insulating layer 39 existing under the mask area 42 can be efficiently prevented from being hardened by scattered light scattered from the metallic area 32.
The interlayer insulating layer 39 which is in an unhardened state on the conductor 37 can be completely removed by developing the printed wiring board 31 after exposure as described above and a via hole 40 from which the conductor 37 is completely exposed can be formed without leaving no interlayer insulating layer 39 on the conductor 37. Afterward, the continuous circuit pattern 43 is formed on the interlayer insulating layer 39 and inside the via hole 40 by electroless plating described above. Hereby, the printed wiring board 31 is manufactured as shown in FIG. 16 (F). However, the interlayer insulating layer 39 hardened by exposure is left on the base material as it is.
The blank portion 36 in which no conductor exists consisting of each window part 36A is formed around the conductor 37 which is opposite to the mask area 42 and functions as a connecting pad and as the filled resin layer 38 or the plating resist layer 38 ′ is formed in each window part 36A, a great deal of light radiated as described above closely outside the mask area 42 is absorbed in the filled resin layer 38 and is not scattered, and light scattered on the metallic area 32 outside the blank portion 36 is hardly incident to the interlayer insulating layer 39 existing under the mask area 42. Hereby, as the interlayer insulating layer 39 can be exposed on the boundary of the mask area 42 at satisfactory resolution as described above, the interlayer insulating layer 39 existing under the mask area 42 can be efficiently prevented from being hardened by scattered light scattered from the metallic area 32. As a result, the interlayer insulating layer 39 which exists in an unhardened state on the conductor 37 can be completely removed by developing the printed wiring board 31 after exposure as described above and a via hole 40 from which the conductor 37 is completely exposed can be formed without leaving the interlayer insulating layer 39 on the conductor 37.
Further, the blank portion 36 is provided around the conductor 37 which functions as the connecting pad and as the filled resin 38 is filled in this blank portion 36 or the plating resist layer 38 ′ is formed in this blank portion 36, the blank portion is excellent in the adhesion between the blank portion and the interlayer insulating layer formed on it, compared with a case that the blank portion 36 is not formed.
In this second embodiment, as the filled resin 38 and the plating resist layer 38 ′ are formed in the blank portion 36 around the conductor 37 which functions as the connecting pad to which the via hole is connected in the metallic area and resin and the interlayer insulating layer are in concord, compared with the case of metal and the interlayer insulating layer, the interlayer insulating layer can be prevented from being peeled.
FIGS. 17 show connection structure in which a connecting pad formed on a core material and a pattern on an interlayer insulating layer are connected via a via hole in the multilayer printed wiring board equivalent to the first embodiment, FIGS. 17 (A) and (D) are plan views showing the multilayer printed wiring board and FIGS. 17 (B) and (C) are sectional views showing the multilayer printed wiring board.
As shown in FIGS. 17 (A), (B), (C) and (D), a multilayer printed wiring board 51 is provided with a base material 52 which is a core material and a through hole 53 is formed on this base material. A conductor layer 54 is formed on the inner wall of the through hole 53 by plating the through hole and a circular through hole land 55 connected to the conductor layer 54 is provided on the upper and lower double sides of the base material 52. The through hole land 55 is in the shape of a tear or an ellipse on the upper surface of the base material 52 and hereby, one end of the through hole land 55 (the right end in FIGS. 17 (A) and (B) functions as a connecting pad for connecting to a via hole 60 described later. A connecting pad 56 is formed in a position separated from the through hole land 55 in the lower part of the base material 52. Filling resin 57 is filled inside the through hole 53, between the through hole land 55 and the connecting pad 56, between the through hole land 55 and the other circuit pattern and between the connecting pad 56 and the other circuit pattern.
For interlayer insulating material, an adhesive for electroless plating is desirable. For the adhesive for electroless plating, an adhesive for electroless plating generated by dispersing a heat-resistant resin particle soluble in acid or an oxidizing agent in heat-resistant resin refractory in acid or an oxidizing agent is the most suitable. It is because an anchor in the shape of an octopus trap can be formed on the surface by roughing and removing a heat- resistant resin particle soluble in acid or an oxidizing agent and the adhesion between the conductor circuit and the interlayer insulating layer can be improved.
In the multilayer printed wiring board 51 equivalent to the first embodiment constituted as described above, the through hole land 55 is in the shape of a tear, as the via hole 60 is connected to the through hole land 55, the through hole land 55 and a pad for connecting the via hole 60 are integrated and therefore, connection area for connecting the bottom of the via hole 60 to the right end of the through hole land 55 can be enlarged. Hereby, when the mask film is stuck on the interlayer insulating layer 58 on the base material 52 and the interlayer insulating layer is exposed with the light blocking pattern of the mask film opposite to a part in which the via hole is to be formed so as to form the via hole 60, the range of allowable misregistration of the light blocking pattern of the mask film to a part in which the via hole is to be formed can be greatly widened and the via hole 60 and the right end (equivalent to a pad) of the through hole land 55 can be stably connected reliably even if misregistration is caused in the direction shown by an arrow in FIG. 17 (A) between the right end of the through hole land 55 and the mask film.
In the multilayer printed wiring board 51 equivalent to the second embodiment formed as described above, the through hole land 55 and the via hole land 63 are both in the shape of a tear and further, as the opening 64 of the via hole 60 is formed in the enlarged part of the land 63, an allowable range for forming the opening 64 of the via hole 60 at the right end of the through hole land 55 is further widened, compared with the allowable range of the multilayer printed wiring board 51 equivalent to the above first embodiment. Therefore, the range of allowable misregistration of the light blocking pattern of a mask film to a part in which the via hole is to be formed can be greatly widened and even if misregistration is caused between the through hole land 55 and the mask film, the via hole 60 and the through hole land 55 can be stably connected reliably independent of the direction of misregistration as shown by arrows in FIG. 18
Next, a multilayer printed wiring board equivalent to a fifth embodiment will be described referring to FIG. 21. This multilayer printed wiring board is provided with connection structure in which a connecting pad formed on an interlayer insulating layer and a pattern on another interlayer insulating layer are connected via a via hole. FIG. 21 show connection structure in which a connecting pad formed on an interlayer insulating layer and a pattern on another interlayer insulating layer are connected via a via hole in the multilayer printed wiring board equivalent to the fifth embodiment, FIG. 21 (A) is a plan showing the multilayer printed wiring board and FIG. 21 (B) is a sectional view showing the multilayer printed wiring board.
As shown in FIGS. 21 (A) and (B), in a printed wiring board 70, a connecting pad 72 constituting a part of a lower conductor circuit 72A is formed on a base material 71 and a filled resin layer 73 is provided around the connecting pad 72. An interlayer insulating layer 74 is formed on the connecting pad 72 and the filled resin layer 73 and a substantially elliptic connecting pad 77 including a via hole 76 inside which a conductor layer 75 is formed and which is located in a position opposite to the connecting pad 72 in the interlayer insulating layer 74 is formed.
The elliptic connecting pad 77 constitutes a part of an intermediate conductor circuit, a via hole 82 constituting a part of an upper conductor circuit 84 formed on an interlayer insulating layer 80 described later is connected to one end thereof in the direction of the longer axis of the ellipse and the other end in the direction of the longer axis of the ellipse constitutes a part of a via hole land 78 of the via hole 76. Hereby, the connecting pad 72 on the base material 71 is connected to the connecting pad 77 via the conductor layer 75 of the via hole 76. The ellipse of the connecting pad 77 is formed in the shape which looks as if the opposite sides of a rectangle draw an arc outward as shown in FIG. 21 (A) and further, it need scarcely be said that the connecting pad may be in the shape which looks as if the opposite sides of an ellipse draw an arc outward.
Furthermore other interlayer insulating layer 80 is provided on the interlayer insulating layer 74, a via hole 82 inside which a conductor layer 81 is formed is provided in a position opposite to one end (the right end in FIGS. 21 (A) and (B)) of the connecting pad 77 in the interlayer insulating layer 80 and the upper conductor circuit 84 including a circuit pattern 83 connected to the conductor layer 81 is formed on the interlayer insulating layer. Hereby, the connecting pad 77 on the interlayer insulating layer 74 is connected to the circuit pattern 83 via the conductor layer 81 of the via hole 82. A plating resist layer 85 required when the conductor layer 81 and the circuit pattern 83 are formed by electroless plating is formed around the conductor layer 81 of the via hole 82 and the circuit pattern 83.
The multilayer printed wiring board 70 equivalent to the fifth embodiment constituted as described above is provided with the connecting pad 77 in which the via hole land 78 of the via hole 76 connected to the connecting pad 72 of the lower conductor circuit 72A and a pad of the via hole 82 for the upper conductor circuit 84 are integrated and the connecting pad 77 is in the shape of an ellipse which looks as if the opposite sides of an ellipse or a rectangle draw an arc outward. Therefore, no location to which stress is collectively applied exists in the connecting pad 77 and hereby, the interlayer insulating layers 74 and 80 can be securely prevented from being cracked even in a heat cycle. The connection area at the bottom of the via hole 82 opposite to the connecting pad 77 can be widened as in the above first embodiment and hereby, when the interlayer insulating layer 80 on the base material 71 is exposed with the light blocking pattern of a mask film stuck on the interlayer insulating layer 80 opposite to a part in which a via hole is to be formed to form the via hole 82, the range of allowable misregistration of the light blocking pattern of the mask film to the part in which the via hole is to be formed is greatly widened and even if misregistration is caused between the connecting pad 77 and the mask film in the directions shown by arrows in FIG. 21 (A), the via hole 82 and the connecting pad 77 can be stably connected reliably. The base material may be formed of a multilayer printed wiring board.
Next, a multilayer printed wiring board equivalent to a ninth embodiment will be described referring to FIG. 25. This multilayer printed wiring board is provided with connection structure in which a connecting pad formed on an interlayer insulating layer and a pattern on another interlayer insulating layer are connected via a via hole as the multilayer printed wiring board 70 equivalent to the above fifth embodiment. FIGS. 25 show connection structure in which a connecting pad formed on an interlayer insulating layer and a pattern on another interlayer insulating layer are connected via a via hole in a multilayer printed wiring board equivalent to a ninth embodiment, FIG. 25 (A) is a plan showing the multilayer printed wiring board and FIG. 25 (B) is a sectional view showing the multilayer printed wiring board.
As shown in FIGS. 25 (A) and (B), a printed wiring board 100 is provided with a base material 101, a circular connecting pad 102 constituting a part of a lower conductor circuit 102A is formed on this base material 101 and a filled resin layer 103 is provided around the connecting pad 102. An interlayer insulating layer 104 is formed on the connecting pad 102 and the filled resin layer 103 and an intermediate conductor circuit 108 including a via hole 106 inside which a conductor layer 105 is formed in a position opposite to the connecting pad 102 in the interlayer insulating layer 104 and provided with a via hole land 106A in the shape of a tear around the via hole 106 and a connecting pad 107 in the shape of a tear connected to the narrower part of the via hole land 106A via a circuit pattern 106B is provided. The connecting pad 107 is connected to the circuit pattern 106B on the side of the narrower part in the shape of a tear as the via hole land 106A.
Next, a multilayer printed wiring board equivalent to a tenth embodiment will be described referring to FIG. 26. FIGS. 26 show connection structure in which a connecting pad on a base material and a pattern on an interlayer insulating layer are connected via a via hole in the multilayer printed wiring board equivalent to the tenth embodiment, FIGS. 26 (A), (C), (D) and (E) are plan views showing the multilayer printed wiring board and FIG. 26 (B) is a sectional view showing the multilayer printed wiring board.
As shown in FIGS. 26 (A), (B), (C), (D) and (E), a printed wiring board 120 is provided with a base material 121, a connecting pad 122 constituting a part of a lower conductor circuit 122A is formed on this base material 121 and a filled resin layer 123 is provided around the connecting pad 122. An interlayer insulating layer 124 is formed on the connecting pad 122 and the filled resin layer 123, and an upper conductor circuit 127 including a via hole 126 inside which a conductor layer 125 is formed in a position opposite to the connecting pad 122 in the interlayer insulating layer 124 and provided with a via hole land 126A in the shape of a tear or an ellipse around the via hole 126 and a circuit pattern 126B is connected to the narrower part of the via hole land 126A in the case of a tear shape is provided. In the case that the via hold land 126 is formed in the shape of an ellipse, alternatively, the upper conductor circuit 127 is provided with a circuit pattern 126B connected to an end of the elliptic via hole land 126A in its longer diameter. Hereby, the connecting pad 122 on the base material 121 is connected to the circuit pattern 126B via the conductor layer 125 of the via hole 126. The opening 129 of the via hole 126 is formed in the widened part of the via hole land 126A in the shape of a tear as shown in FIG. 26.
Furthermore, as shown in FIGS. 26 (D) and (E), the lower conductor circuit to be connected with the via hole may be formed to have a pad in the shape of a tear or an ellipse. In this case, the range of allowable misregistration with respect to the via hole forming part can be widened. There is no location at which stress is converged in any of the tear-shaped and the ellipse-shaped via hole land 126A, so that the plating resist layer and the interlayer insulating layer, both of which are in connecting with the pad, can be also prevented from being cracked.
Next, a multilayer printed wiring board equivalent to an eleventh embodiment will be described referring to FIG. 27. The multilayer printed wiring board equivalent to the eleventh embodiment is basically provided with the same constitution as that of the multilayer printed wiring board 70 equivalent to the above fifth embodiment and is provided with connection structure in which a connecting pad formed on an interlayer insulating layer and a pattern on another interlayer insulating layer are connected via a via hole. FIGS. 27 show connection structure in which a connecting pad formed on an interlayer insulating layer and a pattern on another interlayer insulating layer are connected via a via hole in a multilayer printed wiring board equivalent to an eleventh embodiment, FIG. 27 (A) is a plan showing the multilayer printed wiring board and FIG. 27 (B) is a sectional view showing the multilayer printed wiring board.
As shown in FIGS. 27 (A) and (B), a printed wiring board 130 is provided with a base material 131, a connecting pad 132 constituting a part of a lower conductor circuit 132A is formed on this base material 131 and a filled resin layer 133 is provided around the connecting pad 132. An interlayer insulating layer 134 is formed on the connecting pad 132 and the filled resin layer 133 and a substantially elliptic connecting pad 137 including plural via holes 136 (three in FIG. 27) inside which a conductor layer 135 is formed in a position opposite to the connecting pad 132 in the interlayer insulating layer 134.
Further the other interlayer insulating layer 140 is provided on the interlayer insulating layer 134, three via holes 142 inside each of which a conductor layer 141 is formed are provided in a position opposite to one end (the right end in FIGS. 27 (A) and (B)) of the connecting pad 137 in this interlayer insulating layer 140 and the upper conductor circuit 144 including a circuit pattern 143 connected to the conductor layer 141 is formed. Hereby, the connecting pad 137 on the interlayer insulating layer 134 is connected to the circuit pattern 143 via the conductor layer 141 of each via hole 142.
In the multilayer printed wiring board 130 equivalent to the eleventh embodiment constituted as described above, in case the connecting pad 132 on the base material 131 which is formed of an insulating base material or a multilayer printed wiring board and the connecting pad 137 on the interlayer insulating layer 134 are connected and in case the connecting pad 137 and the connection 146 of the upper conductor circuit 144 on the interlayer insulating layer 140 are connected, connection is performed via the plural via holes 136 and 142 and as the plural via holes 136 and 142 share each land and are formed collectively as described above, secure connection is enabled via the residual via holes 136 and 142 even if some via holes 136 and 142 are disconnected. Hereby, the probability of the disconnection of the multilayer printed wiring board 130 can be greatly reduced. The shape of the connection 146 in the upper conductor circuit 144 may be circular or in the shape of a tear as shown in FIGS. 27 (C) and (D).
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