Source: http://www.google.com/patents/US6577318?dq=6181294
Timestamp: 2014-03-14 21:31:55
Document Index: 580039917

Matched Legal Cases: ['art 405', 'art 406', 'art 406', 'art 406', 'art 405', 'art 406', 'art 406', 'art 406']

Patent US6577318 - Integrated circuit device and display device with the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn integrated circuit device includes a first memory unit and a conversion part for converting the parallel data read from the first memory unit into serial data. The integrated circuit device also includes a second memory unit that can write and read the data indicating the order of reading the parallel...http://www.google.com/patents/US6577318?utm_source=gb-gplus-sharePatent US6577318 - Integrated circuit device and display device with the sameAdvanced Patent SearchPublication numberUS6577318 B1Publication typeGrantApplication numberUS 09/469,195Publication dateJun 10, 2003Filing dateDec 21, 1999Priority dateDec 22, 1998Fee statusLapsedPublication number09469195, 469195, US 6577318 B1, US 6577318B1, US-B1-6577318, US6577318 B1, US6577318B1InventorsNobuyasu DoiOriginal AssigneeNec Electronics CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (12), Non-Patent Citations (2), Referenced by (1), Classifications (15), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetIntegrated circuit device and display device with the sameUS 6577318 B1Abstract An integrated circuit device includes a first memory unit and a conversion part for converting the parallel data read from the first memory unit into serial data. The integrated circuit device also includes a second memory unit that can write and read the data indicating the order of reading the parallel data from the first memory unit and the order of converting the parallel data into the serial data.
11. The integrated circuit device of claim 10, wherein said first memory unit has an nth row of data, an mth row in said second memory unit corresponds to said nth row of said first memory unit and includes a first portion of control data having the integer value �n� and a second portion of said control data having a bit flag value indicating that said mth row of data is converted from parallel data to serial data starting with an end of said mth row and ending with a beginning of said mth row, said control data of said mth row indicating that said nth row of data is said mth row of data read from said first memory unit, m and n being equal.
14. The display device of claim 13, wherein said first memory unit has an nth row of data, an mth row in said second memory unit corresponds to said nth row of said first memory unit and includes a first portion of control data having the integer value �n� and a second portion of said control data having a bit flag value indicating that said mth row of data is converted from parallel data to serial data starting with an end of said mth row and ending with a beginning of said mth row, said control data of said mth row indicating that said nth row of data is said mth row of data read from said first memory unit, m and n being equal.
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an integrated circuit device that allows a user to arbitrarily select the position of the input terminal of printed circuit board to be connected to each output terminal for an anode, and that allows the wiring on the printed circuit board to be simpler and reduced in wiring region.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 7 is a block diagram of the integrated circuit device 400 in accordance with a preferred embodiment of the present invention, which drives the fluorescent display tube 100 in FIG. 1.
On the other hand, as shown in FIG. 9, in the second memory unit 408, stored are data that designate the order of reading display data stored in the first memory unit 407. For example, the data that designate the order of reading the display data of 5 bits per column, stored in the column addresses C0-C4, are stored as 3-bit data in the row addresses r0-r7 and the column addresses c1-c3. The display data of 5 bits per column, stored in the column addresses C0-C4 of the first memory unit 407, are read as 1-byte parallel data. And, for example, the data that designate the serial direction when converting display data from parallel data for each byte into serial data are stored as 1-bit data in the row addresses r0-r7 and the column address c0. By the 1-bit data, whether the serial direction is, for example, �the direction from the address C0 to the address C4� or �the direction from the address C4 to the address C0� is determined.
When a first count signal from the counting part 405 is supplied for the second memory unit 408, the data stored in the row address r0 and the column addresses c0-c3 of the second memory unit 408 are read. Next, the 3-bit data �111� of the row address r0 and the column addresses c1-c3 are supplied for the first memory unit 407 as reading order data, as well as the 1-bit data �1� of the column address c0 are supplied for the parallel/serial conversion part 406 as serial direction data.
When the reading order data �111� is supplied for the first memory unit 407, the data stored in the row address R7 corresponding to the reading order data �111� out of the row addresses R0-R7 and the column addresses C0-C4 are read, and supplied for the parallel/serial conversion part 406.
The parallel data from the row address R7 and column addresses C0-C4 supplied for the parallel/serial conversion part 406, are serialized into the direction from the address C4 to the address C0, based on the serial direction data �1� in row address r0. And the serialized data are outputted as the display data of anodes A40-A36.
When a next count signal from the counting part 405 is supplied for the second memory unit 408, the data stored in the row address r1 and the column addresses c0-c3 of the second memory unit 408 are read. Next, the 3-bit data �110� in the row address r1 and the column addresses c1-c3 are supplied for the first memory unit 407 as reading order data, as well as the 1-bit data �1� in the column address c0 are supplied for the parallel/serial conversion part 406 as serial direction data.
When the reading order data �110� is supplied for the first memory unit 407, the data stored in the row address R6 corresponding to the reading order data �110� out of the row addresses R0-R7 and the column addresses C0-C4 are read, and supplied for the parallel/serial conversion part 406.
The parallel data from the row address R6 and column addresses C0-C4 supplied for the parallel/serial conversion part 406, are serialized into the direction from the address C4 to the address C0, based on the serial direction data �1� in the row address r1. And the serialized data are outputted as the display data of anodes A35-A31.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3735383 *Jan 25, 1971May 22, 1973Ise Electronics CorpDisplay apparatus utilizing cathode ray tubesUS4408197 *Apr 30, 1981Oct 4, 1983Hitachi, Ltd.Pattern display apparatusUS5036247 *Mar 7, 1990Jul 30, 1991Pioneer Electronic CorporationDot matrix fluorescent display deviceUS5172028 *Sep 13, 1990Dec 15, 1992Futaba Denshi Kogyo K.K.Fluorescent display deviceUS5311211 *Sep 25, 1991May 10, 1994Texas Instruments IncorporatedApparatus and method for providing a raster-scanned display with converted address signals for VRAMUS5323175 *Jan 17, 1992Jun 21, 1994Mitsubishi Denki Kabushiki KaishaScreen display elementUS5459374 *Jul 5, 1994Oct 17, 1995Delco Electronics CorporationCombination fixed segment and active matrix vacuum fluorescent displayUS5610622 *Sep 20, 1994Mar 11, 1997Hitachi, Ltd.Display control deviceUS5701134 *Jun 23, 1994Dec 23, 1997U.S. Philips CorporationPicture display device with uniformity correction of electron supplyUS5793158 *May 29, 1997Aug 11, 1998Wedding, Sr.; Donald K.Gas discharge (plasma) displaysUS5952985 *Aug 16, 1996Sep 14, 1999Core Engineering, Inc.Update method for displaying highly dynamic events in multiplexed character displaysUS6078316 *May 3, 1995Jun 20, 2000Canon Kabushiki KaishaDisplay memory cache* Cited by examinerNon-Patent CitationsReference1M. Ishidoh, et al., "FIP(TM) Controller and Driver", NEC Corporation (1992).2M. Ishidoh, et al., "FIP� Controller and Driver", NEC Corporation (1992).Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6989825 *May 9, 2001Jan 24, 2006Mitsubishi Denki Kabushiki KaishaDisplay control device* Cited by examinerClassifications U.S. Classification345/565, 345/467, 345/571, 345/537International ClassificationG09G5/00, H03M9/00, G09G3/30, G11C7/10, G09G3/20, G09G3/06Cooperative ClassificationG09G3/06, G11C7/1051, G11C2207/107European ClassificationG11C7/10R, G09G3/06Legal EventsDateCodeEventDescriptionJul 31, 2007FPExpired due to failure to pay maintenance feeEffective date: 20070610Jun 10, 2007LAPSLapse for failure to pay maintenance feesDec 27, 2006REMIMaintenance fee reminder mailedMar 3, 2003ASAssignmentOwner name: NEC ELECTRONICS CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013784/0714Effective date: 20021101Owner name: NEC ELECTRONICS CORPORATION 1753 SHIMONUMABE, NAKAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION /AR;REEL/FRAME:013784/0714Dec 21, 1999ASAssignmentOwner name: NEC CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DOI, NOBUYASU;REEL/FRAME:010508/0526Effective date: 19991213Owner name: NEC CORPORATION MINATO-KU 7-1 SHIBA 5-CHOME TOKYORotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google