Source: https://patents.google.com/patent/US20020119651?oq=%22peter+l+basel%22+%22lsi+logic%22
Timestamp: 2018-02-20 00:40:19
Document Index: 608264083

Matched Legal Cases: ['art 130', 'art 140', 'art 150', 'art 160', 'art 230', 'art 240', 'art 250', 'art 230', 'art 240', 'art 250']

US20020119651A1 - Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device - Google Patents
US20020119651A1
US20020119651A1 US10128264 US12826402A US2002119651A1 US 20020119651 A1 US20020119651 A1 US 20020119651A1 US 10128264 US10128264 US 10128264 US 12826402 A US12826402 A US 12826402A US 2002119651 A1 US2002119651 A1 US 2002119651A1
US10128264
[0010]FIG. 55 is a graph illustrating the measured data of TDDB characteristics of a copper interconnection, an aluminum interconnection and a tungsten interconnection. The TDDB and electric field strength are plotted along the ordinate and abscissa, respectively. When the characteristics (data A) of the aluminum interconnection and those (data B) of the tungsten interconnection are extrapolated, the TDDB at an electric field strength of 0.2 MV/cm (ordinary using condition) easily exceeds 3×108 sec (10 years), which is a development target of the present inventors. When the characteristics (data C) of the copper interconnection is extrapolated, on the other hand, there is almost no margin for the development target of 10 years. The aluminum interconnection is formed by film deposition and patterning by photolithography, while the tungsten interconnection is formed by the damascene method similar to the copper interconnection. The copper interconnection and tungsten interconnection differ only in the material. There is no difference in their structures. A marked difference in TDDB characteristics between these two materials suggests that it results from the difference in the interconnection material. Here, the TDDB characteristics are measured at 140° C.
[0078]FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a manufacturing method of a semiconductor integrated circuit device according to one embodiment (Embodiment 1) of the present invention;
[0079]FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1;
[0080]FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1;
[0081]FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1;
[0082]FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1;
[0083]FIG. 6(a) is a plan view illustrating the manufacturing method of Embodiment 1 and FIG. 6(b) is a fragmentary cross-sectional view illustrating the manufacturing method of Embodiment 1;
[0084]FIG. 7(a) is a plan view illustrating the manufacturing method of Embodiment 1 and FIG. 7(b) is a fragmentary cross-sectional view illustrating the manufacturing method of Embodiment 1;
[0085]FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1;
[0086]FIG. 9 is a schematic view illustrating one example of the whole constitution of a CMP apparatus used for the formation of a Cu-embedded interconnection;
[0087]FIG. 10 is a schematic view illustrating a part of the CMP apparatus used for the formation of a Cu-embedded interconnection;
[0088]FIG. 11 is a perspective view illustrating a scrub washing method of a wafer;
[0089]FIG. 12 is a schematic view illustrating another example of the whole constitution of a CMP apparatus used for the formation of a Cu-embedded interconnection;
[0090]FIG. 13 is a schematic view illustrating a further example of the whole constitution of a CMP apparatus used for the formation of a Cu-embedded interconnection;
[0091]FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1;
[0092]FIG. 15(a) is a schematic cross-sectional view of a plasma treating apparatus used for ammonia plasma treatment an deposition of a silicon nitride film and FIG. 15(b) is a plan view of the apparatus;
[0093]FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1;
[0094]FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1;
[0095]FIG. 18 is a flow chart illustrating the manufacturing method of the semiconductor integrated circuit device of Embodiment 1;
[0096]FIG. 19 is a schematic cross-sectional view illustrating the semiconductor integrated circuit device of Embodiment 1;
[0097]FIG. 20 is a graph illustrating TDDB;
[0098]FIG. 21 is a graph illustrating TDDB;
[0105]FIG. 28 is a TEM photograph of the interconnection portion of Embodiment 1;
[0106]FIG. 29 is TEM photograph for comparison;
[0107]FIG. 30 is a graph illustrating interconnection resistance;
[0108]FIG. 31(a) is a TEM photograph of the interconnection portion without treatment, FIG. 31(b) is a TEM photograph of the interconnection portion of Embodiment 1, and FIGS. 31(c) and 31(d) are traced drawings of FIGS. 31(a) and 31(b), respectively;
[0110]FIG. 33 is a graph illustrating the TDDB life;
[0111]FIG. 34 is a schematic view illustrating one example of the whole constitution of a CMP apparatus used for a manufacturing method of a semiconductor integrated circuit device according to Embodiment 2 of the present invention;
[0112]FIG. 35 is a schematic view illustrating a part of a CMP apparatus used for the formation of a Cu-embedded interconnection;
[0113]FIG. 36 is a schematic view of a CMP apparatus illustrating the polished condition of a Cu film;
[0114]FIG. 37 is a fragmentary cross-sectional view of a semiconductor substrate illustrating the manufacturing method of a semiconductor integrated circuit device according to Embodiment 2;
[0115]FIG. 38(a) is a fragmentary plan view of the semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2 and FIG. 38(b) is a fragmentary cross-sectional view of the substrate;
[0116]FIG. 39 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2;
[0117]FIG. 40(a) is a fragmentary plan view of the semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2 and FIG. 40(b) is a fragmentary cross-sectional view of this substrate;
[0118]FIG. 41 is a fragmentary cross-sectional view of a semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2;
[0119]FIG. 42(a) is a fragmentary plan view of the semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2 and FIG. 42(b) is a fragmentary cross-sectional view of this substrate;
[0120]FIG. 43 is a flow chart showing the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2;
[0121]FIG. 44 is a graph illustrating TDDB;
[0122]FIG. 45 is a flow chart showing a manufacturing method of a semiconductor integrated circuit device according to Embodiment 3;
[0123]FIG. 46 is a graph illustrating TDDB;
[0124]FIG. 47 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a manufacturing method of a semiconductor integrated circuit device according to Embodiment 4;
[0125]FIG. 48(a) is a fragmentary plan view of a semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 4 and FIG. 48(b) is a fragmentary cross-sectional view of this substrate;
[0126]FIG. 49 is a fragmentary cross-sectional view of a semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 4;
[0127]FIG. 50 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a manufacturing method of a semiconductor integrated circuit device according to another Embodiment;
[0128]FIG. 51 is a fragmentary cross-sectional view of a semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to another Embodiment;
[0129]FIG. 52(a) is a fragmentary plan view of a semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to another embodiment and FIG. 52(b) is a fragmentary cross-sectional view of this substrate;
[0130]FIG. 53 is a fragmentary cross-sectional view of a semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to another Embodiment;
[0131]FIG. 54 is a fragmentary cross-sectional view of a semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to another Embodiment;
[0132]FIG. 55 is a graph showing measured data of TDDB characteristics of copper, aluminum and tungsten interconnections;
[0134]FIG. 57 is a schematic view illustrating the summary of the measurement; and
[0135]FIG. 58 illustrates one example of measuring results of current and voltage.
The term “TDDB” as used herein means time (lifetime) determined by applying a relatively high voltage between electrodes under measuring conditions of a predetermined temperature (ex. 140° C.), drawing a graph wherein time from application of voltage to dielectric breakdown is plotted against applied electric field, and extrapolating the practical electric field strength (ex. 0.2 MV/cm) in the graph. FIG. 56 illustrates a sample used in the present application for the measurement of TDDB, wherein FIG. 56(a) is a plan view, and FIGS. 56(b) and 56(c) are cross-sections taken along lines B-B′ and C-C′ of FIG. 56(a), respectively. This sample can be formed practically in a TEG (Test Equipment Group) region of a wafer. As illustrated in FIG. 56, a pair of comb-like interconnections L are formed in the second interconnection layer M2 and are connected with pats P1,P2 of the uppermost layer. An electric current is measured by applying an electric field between these comb-like interconnections L. The pads 1,2 are measuring terminals. The width, distance between any two adjacent interconnections and thickness of the comb-like interconnections L are each 0.5 μm. The length of the interconnection is formed to 1.58×105 μm. FIG. 57 is a schematic view illustrating the summary of measurement. The sample is supported on a measuring stage S and a current-voltage measuring apparatus (I/V measuring apparatus) is connected between the pads P1 and P2. The sample stage S is heated by a heater H to adjust the temperature of the sample to 140° C. FIG. 58 shows one example of the measuring results of current-voltage under the conditions of the sample temperature of 140° C. and electric field strength of 5 MV/cm. Although TDDB is measured by either one of the constant voltage stress method and low current stress method, the former one wherein an average electric field applied to an insulating film shows a fixed value is employed in the present application. After application of voltage, the current density decreases with the passage of time and then, a drastic increase in the current (dielectric breakdown) is observed. Here, the time until the leak current density reaches 1 μA/cm2 is designated as TDDB (the TDDB at 5 MV/cm). The term “TDDB” as used herein means the breakdown time (lifetime) at 0.2 MV/cm unless otherwise specifically referred to, but in a broader sense, it is sometimes used as a time until breakdown at a preliminarily designated electric field strength. Unless otherwise specifically described, the TDDB means that at the sample temperature of 140° C. The TDDB is measured using the above-described comb-like interconnections L, but it is needless to say that it reflects the breakdown lifetime between actual interconnections.
[0177]FIG. 9 is a schematic view illustrating a single-wafer type CMP apparatus 100 to be used for the polishing of the Cu film 46. This CMP apparatus 100 is equipped with a loader 120 for accommodating therein a plurality of the substrates 1 each having the Cu film 46 formed on the surface thereof, a polishing treatment part 130 for polishing and flattening the Cu film 46, a corrosion treatment part 140 for subjecting the surface of the substrate 1 to corrosion treatment after completion of polishing, an immersion treatment part 150 for maintaining the substrate 1 to have a wet surface until the post washing of the substrate 1 after completion of the corrosion treatment, a post-washing treatment part 160 for post-washing the substrate 1 after completion of the corrosion treatment and an unloader 170 for accommodating therein a plurality of substrates 1 after completion of post-washing.
As illustrated in FIG. 13, the substrate 1 may be carried into the drying treatment part rightly after the polishing treatment, in other words, right before the initiation of the electrochemical corrosion due to the oxidizing agent in the polishing slurry left on the surface of the substrate and the water content in the polishing slurry may be removed by forced drying. The CMP apparatus 200 shown in FIG. 13 is equipped with a loader 220 for accommodating a plurality of substrates 1 each having a Cu-film-formed surface, a polishing treatment part 230 for polishing and flattening the Cu film, thereby forming an interconnection, a drying treatment part 240 for drying the surface of the substrate 1 after completion of the polishing, a post-washing part 250 for post-washing the substrate 1 and an unloader 260 for accommodating therein a plurality of the substrates 1 after completion of the post-washing. According to the Cu interconnection forming process using this CMP apparatus 200, the substrate 1 subjected to polishing treatment in the polishing treatment part 230 is transferred to the drying treatment part 240 rightly after the polishing treatment, in other words, rightly before the initiation of the electrochemical corrosion reaction due to the oxidizing agent in the polishing slurry left on the surface and in the drying treatment part, the water content in the polishing slurry is removed by forced drying. Then, the substrate I under a dried condition is transferred into the post-washing treatment part 250 and after the post-washing treatment, it is rinsed with pure water, spin-dried and then accommodated in the unloader 260. In this case, the surface of the substrate 1 is kept drying during the time just after the polishing treatment to the initiation of the post-washing so that the initiation of the electrochemical corrosion is inhibited, which makes it possible to prevent the corrosion of the Cu interconnection effectively.
The substrate 1, for example, having a size of 8 inches can be subjected to plasma treatment under the conditions of a treating pressure of 5.0 Torr, RF electric power of 600 W, substrate temperature of 400° C. and ammonia flow rate of 200 sccm and treating time of 10 seconds. The distance between any two adjacent electrodes is set at 600 mils. It is needless to say that the plasma treatment conditions are not limited to the above-described ones. According to the study of the present inventors, a reduction in the plasma damage can be attained by a higher pressure and a reduction in the scatter of TDDB and an increase in TDDB can be attained by a higher substrate temperature. It has also been found that hillocks tend to appear on the surface of Cu at a higher substrate temperature, a lager RF electric power or a long treating time. In consideration of these findings and a difference in the conditions depending on the constitution of the apparatus, the plasma treatment conditions can be set within a range of from 0.5 to 6 Torr for treating pressure, 300 to 600 W for RF electric power, 350 to 450° C. for substrate temperature, 20 to 500 sccm for ammonia flow rate, 5 to 180 seconds for treating time and 300 to 600 mils for a distance between electrodes.
By the plasma treatment, as described above, on the surface of each of the Cu interconnections 46 a to 46 e and silicon oxide film 39, a thin nitride film of each of the underlying films can be formed over the surface of each of the Cu interconnections 46 a to 46 e and silicon oxide film 39, whereby adhesion between the cap film (silicon nitride film) which will be described later, and each of the Cu interconnections 46 a to 46 e and silicon-oxide film 39 can be improved, leading to a marked improvement in the TDDB characteristics.
[0203]FIG. 19 illustrates one example of CMOS-LSI in which the formation of the interconnections of the first to the seventh layers has already been finished. The first interconnection layer (M1) is made of a tungsten film, as described above. The second interconnection (M2) to the fifth interconnection (M5) layers are formed in a similar manner to that employed for the formation of the above-described Cu interconnection. In each of the second (M2) and third interconnection (M3) layers, the width, distance between the adjacent two interconnections and height are each formed to 0.5 μm. In each of the fourth interconnection (M4) and fifth interconnection (M5) layers, on the other hand, the width, distance between adjacent two interconnections and height (thickness) are each formed to 1 μm. The sixth interconnection (M6) is formed to have three layers, that is, tungsten film, aluminum film and tungsten film, while the seventh interconnection layer (M7) is constituted from an aluminum film. A bump or the like is formed on the seventh interconnection layer (M7), but it is not illustrated.
[0205]FIG. 21 illustrates the data (Line B) when the silicon oxide film 39 used in this embodiment is replaced by a silicon nitride film which is denser and firmer than the silicon oxide film. Replacement of the insulating film from silicon oxide to silicon nitride does not bring about any difference (Line Ref) unless it is subjected to ammonia plasma treatment. The TDDB characteristics can be improved more than those according to this embodiment by the use of the silicon nitride film as the insulating film, followed by ammonia plasma treatment. The improvement is however not so marked, indicating that the ammonia plasma treatment rather than the replacement has a dominant influence. It suggests that not an insulating film itself but its interface is a dominant factor which controls TDDB.
FIGS. 24(a) and 24(b) illustrate the analysis results of the surface of the Cu interconnection which has been oxidized, followed by ammonia plasma treatment. The peak of CuO almost disappears, while the peak of N1s appears strongly, which is presumed to owe to the reduction of the Cu surface and removal of oxygen, and at the same time, nitriding of the Cu surface. For comparison, the surface it of the oxidized Cu interconnection subjected to hydrogen thermal treatment at 350° C. was analyzed. The results are shown in FIGS. 24(c) and 24(d). When FIG. 24(c) is compared with FIG. 24(a) concerning the peak of Cu2p, hydrogen thermal treatment is more reducing, because FIG. 22(a) shows the Cu interconnection in a more as-deposited state. Judging from that N1s peak is hardly observed, the Cu surface is only reduced by the hydrogen thermal treatment.
[0211]FIG. 25 is a graph illustrating the results of XPS analysis on the silicon oxide film, while FIGS. 26 and 27 each illustrates the results of the mass spectrometric analysis (TDS-APIMS) of the silicon oxide film. The analysis was conducted on each of the silicon oxide film after CMP and post-washing (Profile C), that subjected to hydrogen plasma treatment after CMP and post-washing (Profile D), that subjected to ammonia plasma treatment after CMP and post-washing (Profile E) and that subjected to nitrogen plasma treatment after CMP and post-washing (Profile F). A deviation toward the high energy direction of about 1 eV in Profile C is caused by the influence of charge up.
[0216]FIG. 25(f) shows the amount of N estimated from the ratio of the Si peak to N peak. Substantially equal nitriding is considered to be conducted in ammonia plasma treatment and nitrogen plasma treatment.
[0222]FIG. 28 is a TEM photograph of the ammonia-plasma-treated interface between the interconnection layer and silicon nitride film (cap film) according to this embodiment, while FIG. 29 is a TEM photograph of the ammonia-plasma-treatment-free interface. Existence of a thin film on the interface (shown by an arrow) can be confirmed in FIG. 28. This thin film is presumed to be a nitride layer as described above. In FIG. 29, on the other hand, such a film cannot be confirmed.
[0233]FIG. 34 is a schematic view illustrating one example of the whole constitution of the CMP apparatus employed for the formation of a Cu-embedded interconnection.
[0258]FIG. 45 is a general flow chart of the formation process of the Cu interconnections 46 a to 46 e. As illustrated in this drawing, this process is similar to that of Embodiment 1 except that a washing step with HF or citric acid is added.
As illustrated in FIG: 49, a plug 508 made of titanium nitride and tungsten is formed in the connecting hole 507. Upon deposition of titanium nitride, an Si—O—N bond is released as in Embodiment 1, whereby the interface between titanium nitride and the silicon oxide film 50 of a low dielectric constant is improved and adhesion therebetween is heightened.
(a) forming a first interconnection groove in a first insulating film over the first main surface of a wafer,
(b) forming, over the first main surface of the wafer having the first interconnection groove formed therein, a first metal film having copper as a main component to embed the first interconnection groove with the first metal film,
(c) removing the first metal film outside the first interconnection groove by first chemical mechanical polishing of the first main surface of the wafer having the first metal film formed therein,
(d) subjecting the first main surface of the wafer, from which the first metal film outside the first interconnection groove has been removed, to first plasma treatment in a first gas-phase reducing atmosphere, thereby subjecting the upper surface of the first copper-embedded interconnection embedded in the first interconnection groove to reducing treatment, and
(e) forming a cap insulating film, which has inhibitory action against the diffusion of copper atoms or copper-containing ions into an insulating film, over the first insulating film and first copper-embedded interconnection over the first main surface of the wafer subjected to reducing treatment.
2. A manufacturing method according to claim 1, wherein the first gas-phase atmosphere has nitriding action to the copper surface.
3. A manufacturing method according to claim 2, wherein the first gas-phase atmosphere contains an ammonia gas.
4. A manufacturing method according to claim 3, wherein the cap insulating film is a silicon nitride film.
5. A manufacturing method according to claim 4, wherein the ammonia gas concentration of the first gas-phase atmosphere is at least 5%.
6. A manufacturing method according to claim 5, wherein the first gas-phase atmosphere is a mixed atmosphere of ammonia (NH3) and a diluting gas, and the diluting gas is at least one gas selected from ammonia (NH3), nitrogen (N2), argon (Ar) and helium (He).
7. A manufacturing method according to claim 6, wherein the chemical mechanical polishing is abrasive-grain-free one.
8. A manufacturing method according to claim 1, wherein the first gas-phase atmosphere comprises a hydrogen gas.
9. A manufacturing method of a semiconductor integrated circuit device, comprising:
(c) removing the first metal film outside the first interconnection groove by subjecting the first main surface of the wafer having the first metal film formed therein to first abrasive-grain-free chemical mechanical polishing,
(d) subjecting the first main surface of the wafer from which the first metal film outside the first interconnection groove has been removed to first gas-phase treatment in a first gas-phase reducing atmosphere, thereby subjecting the upper surface of the first copper-embedded interconnection embedded in the first interconnection groove to reducing treatment, and
10. A manufacturing method according to claim 9, wherein the first gas-phase atmosphere has nitriding action to the surface of copper.
11. A manufacturing method according to claim 10, wherein the first gas-phase atmosphere contains an ammonia gas.
12. A manufacturing method according to claim 11, wherein the cap insulating film is a silicon nitride film.
13. A manufacturing method according to claim 12, wherein the first gas-phase treatment is plasma treatment.
14. A manufacturing method according to claim 13, wherein the ammonia gas concentration of the first gas-phase atmosphere is at least 5%.
15. A manufacturing method according to claim 14, wherein the first gas-phase atmosphere is a mixed atmosphere of ammonia (NH3) and a diluting gas, and the diluting gas is at least one gas selected from ammonia (NH3), nitrogen (N2), argon (Ar) and helium (He).
16. A manufacturing method according to claim 15, wherein the chemical mechanical polishing is abrasive-grain-free one.
17. A manufacturing method according to claim 9, wherein the first gas-phase atmosphere comprises a hydrogen gas.
US10128264 1999-08-10 2002-04-24 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device Abandoned US20020119651A1 (en)
US10128264 US20020119651A1 (en) 1999-08-10 2002-04-24 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
US66605300 Division 2000-09-20 2000-09-20
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