Source: http://www.google.com/patents/US8166223?dq=6246862
Timestamp: 2015-05-22 18:37:30
Document Index: 340598993

Matched Legal Cases: ['Application No. 200480037044', 'Application No. 200480037044', 'Application No. 04813430', 'Application No. 2006', 'Application No. 93138128', 'Application No. 93138128', 'Application No. 200480037044', 'Application No. 93138128']

Patent US8166223 - Apparatuses to provide a message signaled interrupt to generate a PCI ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsMachine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered...http://www.google.com/patents/US8166223?utm_source=gb-gplus-sharePatent US8166223 - Apparatuses to provide a message signaled interrupt to generate a PCI express interruptAdvanced Patent SearchPublication numberUS8166223 B2Publication typeGrantApplication numberUS 12/636,027Publication dateApr 24, 2012Filing dateDec 11, 2009Priority dateDec 19, 2003Also published asCN1894680A, CN100468376C, DE602004022980D1, EP1695224A1, EP1695224B1, EP2112600A2, EP2112600A3, US7409483, US7743194, US20050138220, US20080263250, US20100095038, WO2005066815A1Publication number12636027, 636027, US 8166223 B2, US 8166223B2, US-B2-8166223, US8166223 B2, US8166223B2InventorsJoseph A. BennettOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (22), Non-Patent Citations (20), Referenced by (3), Classifications (8), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetApparatuses to provide a message signaled interrupt to generate a PCI express interrupt
US 8166223 B2Abstract
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5410708 *Jul 19, 1991Apr 25, 1995Kabushiki Kaisha ToshibaMulti-register interrupt controller with multiple interrupt detection capabilityUS5925115 *Mar 10, 1997Jul 20, 1999Vlsi Technology, Inc.Method and system for extending interrupt sources and implementing hardware based and software based prioritization of interrupts for an embedded processorUS5983308 *Dec 18, 1997Nov 9, 1999Advanced Micro Devices, Inc.Multi-tiered interrupt structure with global interrupt enablementUS5987560 *Sep 11, 1997Nov 16, 1999Advanced Micro Devices, Inc.Integrated programmable logic circuit for conditioning received input signals, detecting transitions of conditioned signals, and generating an associated interrupt respectivelyUS6205509 *Dec 17, 1999Mar 20, 20013Com CorporationMethod for improving interrupt response timeUS6219742 *Apr 29, 1998Apr 17, 2001Compaq Computer CorporationMethod and apparatus for artificially generating general purpose events in an ACPI environmentUS6253275Nov 25, 1998Jun 26, 2001Advanced Micro Devices, Inc.Interrupt gating method for PCI bridgesUS6370607Apr 13, 1999Apr 9, 2002Advanced Micro Devices, Inc.Automatic disabling of interrupts upon entry into interrupt service routineUS6629179Jul 31, 2000Sep 30, 2003Adaptec, Inc.Message signaled interrupt generating device and methodUS6772257 *Dec 23, 1999Aug 3, 2004Intel CorporationMethod and apparatus for processing interruptsUS6775730Apr 18, 2001Aug 10, 2004Sony CorporationSystem and method for implementing a flexible interrupt mechanismUS6789142 *Dec 18, 2002Sep 7, 2004Intel CorporationMethod, system, and program for handling interrupt requestsUS6920516Aug 31, 2001Jul 19, 2005Hewlett-Packard Development Company, L.P.Anti-starvation interrupt protocolUS6941398 *Apr 4, 2001Sep 6, 2005Via Technologies, Inc.Processing method, chip set and controller for supporting message signaled interruptUS6968411 *Mar 19, 2002Nov 22, 2005Intel CorporationInterrupt processing apparatus, system, and methodUS7409483 *Dec 19, 2003Aug 5, 2008Intel CorporationMethods and apparatuses to provide message signaled interrupts to level-sensitive driversUS20010032287 *Apr 4, 2001Oct 18, 2001Jiin LaiProcessing method, chip set and controller for supporting message signaled interruptUS20030167366 *Mar 1, 2002Sep 4, 2003Intel CorporationInterrupt disabling apparatus, system, and methodUS20030182484 *Mar 19, 2002Sep 25, 2003Intel CorporationInterrupt processing apparatus, system, and methodUS20050033895 *Aug 9, 2003Feb 10, 2005Lueck Andrew W.System for signaling serialized interrupts using message signaled interruptsWO2001006363A1Jul 13, 2000Jan 25, 20013Com CorpA method for improving interrupt response timeWO2005066815A1Dec 8, 2004Jul 21, 2005Joseph BennettDriver transparent message signaled interrupts* Cited by examinerNon-Patent CitationsReference1Final Office Action for U.S. Appl. No. 10/742,375 Mailed Jun. 12, 2007.2Final Office Action for U.S. Appl. No. 10/742,375 Mailed Jun. 30, 2006.3Final Office Action for U.S. Appl. No. 12/214,662 Mailed Oct. 14, 2009.4Foreign OA: Office Action from EP04818430.8 mailed Jul. 27, 2011, 7 pages.5International Preliminary Report on Patentability for PCT Patent Application No. PCT/US2004/041108 Mailed Jun. 29, 2006, 7 Pages.6International Search Report and Written Opinion for PCT Patent Application No. PCT/US2004/041108 Mailed Apr. 29, 2005, 11 Pages.7Non-Final Office Action 1st for Chinese Patent Application No. 200480037044.6 Mailed Oct. 26, 2007, 16 Pages.8Non-Final Office Action 2nd for Chinese Patent Application No. 200480037044.6 Mailed May 30, 2008, 6 Pages.9Non-Final Office Action for European Patent Application No. 04813430.8 Mailed Jul. 6, 2007, 5 Pages.10Non-Final Office Action for Japanese Patent Application No. 2006-542891 Mailed Jun. 2, 2009, 3 Pages.11Non-Final Office Action for Taiwan Patent Application No. 93138128 Mailed Jun. 23, 2006, 5 Pages.12Non-Final Office Action for Taiwan Patent Application No. 93138128 Mailed Mar. 21, 2006, 5 Pages.13Non-Final Office Action for U.S. Appl. No. 10/742,375 Mailed Dec. 21, 2006.14Non-Final Office Action for U.S. Appl. No. 10/742,375 Mailed Nov. 30, 2005.15Non-Final Office Action for U.S. Appl. No. 10/742,375 Mailed Sep. 18, 2007.16Non-Final Office Action for U.S. Appl. No. 12/214,662 Mailed Mar. 19, 200917Notice of Allowance and Fees for U.S. Appl. No. 10/742,375 Mailed Mar. 27, 2008.18Notice of Allowance and Fees for U.S. Appl. No. 12/214,662 Mailed Feb. 12, 201019Notice of Allowance for Chinese Patent Application No. 200480037044.6 Mailed Oct. 31, 2008, 2 Pages.20Notice of Allowance for Taiwan Patent Application No. 93138128 Mailed Apr. 27, 2007, 3 Pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8914566 *Jun 19, 2012Dec 16, 2014Teradyne, Inc.Managing interruptsUS9009377Nov 1, 2012Apr 14, 2015Apple Inc.Edge-triggered interrupt conversion in a system employing level-sensitive interruptsUS20130339803 *Jun 19, 2012Dec 19, 2013David VandervalkManaging interrupts* Cited by examinerClassifications U.S. Classification710/261, 710/268, 710/267International ClassificationG06F13/24Cooperative ClassificationG06F13/4291, G06F13/24European ClassificationG06F13/42S4, G06F13/24Legal EventsDateCodeEventDescriptionJun 17, 2011ASAssignmentOwner name: INTEL CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BENNETT, JOSEPH A.;REEL/FRAME:026476/0206Effective date: 20040527RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services