Source: http://www.google.com/patents/US7816727?dq=%223do%22+dna
Timestamp: 2014-10-22 03:36:43
Document Index: 8642152

Matched Legal Cases: ['art 2', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093']

Patent US7816727 - High-κ capped blocking dielectric bandgap engineered SONOS and MONOS - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping...http://www.google.com/patents/US7816727?utm_source=gb-gplus-sharePatent US7816727 - High-κ capped blocking dielectric bandgap engineered SONOS and MONOSAdvanced Patent SearchPublication numberUS7816727 B2Publication typeGrantApplication numberUS 12/182,318Publication dateOct 19, 2010Filing dateJul 30, 2008Priority dateAug 27, 2007Fee statusPaidAlso published asCN101383353A, CN101383353B, EP2031643A2, EP2031643A3, US8119481, US8330210, US20090059676, US20110003452, US20120146126Publication number12182318, 182318, US 7816727 B2, US 7816727B2, US-B2-7816727, US7816727 B2, US7816727B2InventorsSheng-Chih Lai, Hang-Ting Lue, Chien-Wei LiaoOriginal AssigneeMacronix International Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (92), Non-Patent Citations (50), Referenced by (16), Classifications (27), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetHigh-κ capped blocking dielectric bandgap engineered SONOS and MONOSUS 7816727 B2Abstract A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.
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