Source: https://patents.google.com/patent/JP5891382B2/en
Timestamp: 2020-03-29 16:50:41
Document Index: 110409699

Matched Legal Cases: ['art 29', 'art 28', 'art 35', 'art 38', 'art 39', 'art 25', 'art 35', 'art 25', 'art 25', 'art 25', 'art, 31', 'art, 33']

JP5891382B2 - Method for manufacturing photoelectric conversion element - Google Patents
Method for manufacturing photoelectric conversion element Download PDF
JP5891382B2
JP5891382B2 JP2013507402A JP2013507402A JP5891382B2 JP 5891382 B2 JP5891382 B2 JP 5891382B2 JP 2013507402 A JP2013507402 A JP 2013507402A JP 2013507402 A JP2013507402 A JP 2013507402A JP 5891382 B2 JP5891382 B2 JP 5891382B2
JP2013507402A
JPWO2012132995A1 (en
大樹 橋口
豊 桐畑
2011-03-25 Priority to JP2011067625 priority Critical
2011-03-25 Priority to JP2011067625 priority
2012-03-19 Application filed by パナソニックＩｐマネジメント株式会社 filed Critical パナソニックＩｐマネジメント株式会社
2012-03-19 Priority to PCT/JP2012/057006 priority patent/WO2012132995A1/en
2012-03-19 Priority to JP2013507402A priority patent/JP5891382B2/en
2014-07-28 Publication of JPWO2012132995A1 publication Critical patent/JPWO2012132995A1/en
2016-03-23 Publication of JP5891382B2 publication Critical patent/JP5891382B2/en
The present invention relates to a method for manufacturing a photoelectric conversion element.
Various photoelectric conversion elements using single crystal silicon, polycrystalline silicon, or amorphous silicon have been developed. As an example, Patent Document 1 discloses that a semiconductor substrate made of single crystal silicon having a light receiving surface and a back surface provided on the opposite side of the light receiving surface, and a conductive type formed along a predetermined direction on the back surface. A first semiconductor layer and a second semiconductor layer made of amorphous silicon in which different layers are alternately arranged along the back surface; an insulating layer formed from the second semiconductor layer to the first semiconductor layer; A photoelectric conversion element is disclosed that includes a transparent electrode layer covering a semiconductor layer and a second semiconductor layer, and a collecting electrode layer formed on the transparent electrode layer.
JP 2009-200277 A
By the way, in the photoelectric conversion element that generates carriers in the semiconductor substrate, the characteristics of the interface between the single crystal silicon semiconductor substrate and the amorphous silicon semiconductor layer have a great influence on the power generation efficiency. In addition, the contact resistance at the collecting electrode for taking out the carrier from the semiconductor substrate has a great influence on the power generation efficiency.
A method for manufacturing a photoelectric conversion element according to the present invention includes a first step of forming a first amorphous semiconductor layer on a light receiving surface of a crystalline semiconductor substrate, and a second amorphous layer on the back surface of the crystalline semiconductor substrate. A second step of forming a semiconductor layer, and a third step of forming a protective layer on the first amorphous semiconductor layer and the second amorphous semiconductor layer after finishing the first step and the second step When, with the third step is characterized that you form a protective layer on the first amorphous-based semiconductor layer after forming the protective layer on the second amorphous-based semiconductor layer.
ADVANTAGE OF THE INVENTION According to this invention, the electric power generation characteristic of a photoelectric conversion element can be improved.
In embodiment which concerns on this invention, it is sectional drawing of a photoelectric conversion element. In embodiment concerning this invention, it is a flowchart which shows the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
Embodiments according to the present invention will be described below in detail with reference to the drawings. Also, in the following, in all the drawings, the same symbols are attached to the same elements, and the duplicate description is omitted. In the description in the text, the symbols described before are used as necessary.
FIG. 1 is a cross-sectional view of the photoelectric conversion element 10. The photoelectric conversion element 10 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an i-n stacked portion 21, and i. The p-layer unit 31, the insulating layer 24, the n-side electrode unit 25 and the p-side electrode unit 35 are provided. Here, an arrow A shown in FIG. 1 indicates a direction in which light such as sunlight enters the photoelectric conversion element 10. The “light receiving surface” means a surface on which light such as sunlight is mainly incident. The “back surface” means a surface opposite to the light receiving surface.
The n-type single crystal silicon substrate 18 is a power generation layer that receives light incident from the light receiving surface and generates carriers. In this embodiment, the n-type single crystal silicon substrate 18 is used. However, the present invention is not limited to this, and an n-type or p-type conductive crystal semiconductor substrate can be used. In addition to the single crystal silicon substrate, for example, a polycrystalline silicon substrate, a gallium arsenide substrate (GaAs), an indium phosphorus substrate (InP), or the like can be used.
The i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 are passivation layers formed on the light-receiving surface of the n-type single crystal silicon substrate 18. The i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 constitute an amorphous semiconductor layer formed on the light receiving surface. The i-type amorphous silicon layer 16 is a layer made of an intrinsic amorphous semiconductor film. The n-type amorphous silicon layer 14 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant. For example, the n-type amorphous silicon layer 14 preferably has an n-type dopant concentration of 1 × 10 21 / cm 3 or more.
Note that in this embodiment mode, the amorphous silicon layer includes a microcrystalline semiconductor film. A microcrystalline semiconductor film is a film in which crystal grains are precipitated in an amorphous semiconductor. The average grain size of the crystal grains is not limited to this, but is estimated to be about 1 nm to 80 nm.
The antireflection layer 12 is formed on the n-type amorphous silicon layer 14 and reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10. The antireflection layer 12 also functions as a protective layer that protects the surface of the n-type amorphous silicon layer 14. The antireflection layer 12 is made of a transparent material and has a refractive index that reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10 in relation to the refractive index of the layer covered by the antireflection layer 12. And a film thickness is preferred. The antireflection layer 12 includes, for example, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, and the like.
The i-n stacked unit 21 is formed on the back surface of the n-type single crystal silicon substrate 18 and includes an i-type amorphous silicon layer 22 and an n-type amorphous silicon layer 23. It is preferable that the i-n stacked unit 21 is arranged so that more current can be collected from the surface of the photoelectric conversion element 10 in the n-side electrode unit 25 described later. It is preferable that the i-n laminated portion 21 has, for example, a comb shape in which a plurality of finger portions extend in parallel.
The i-type amorphous silicon layer 22 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18. The n-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22. The i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 constitute a part of an amorphous semiconductor layer formed on the back surface. The i-type amorphous silicon layer 22 is a layer made of an intrinsic amorphous semiconductor film. The n-type amorphous silicon layer 23 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant. For example, the n-type amorphous silicon layer 23 preferably has an n-type dopant concentration of 1 × 10 21 / cm 3 or more.
The insulating layer 24 is formed to electrically insulate the i-n stacked unit 21 and the i-p stacked unit 31. The insulating layer 24 also functions as a protective layer formed on the n-type amorphous silicon layer 23. The insulating layer 24 may be any material having electrical insulation properties, but preferably includes, for example, aluminum nitride, silicon nitride, silicon oxide, and the like.
The n-side electrode portion 25 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10. The n-side electrode unit 25 includes a transparent conductive layer 26, a metal layer 27, a first electrode unit 28, and a second electrode unit 29.
The transparent conductive layer 26 is formed on the n-type amorphous silicon layer 23. The transparent conductive layer 26 is composed of metal oxides such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), titanium oxide (TiO 2 ), and indium tin oxide (ITO). It is configured to include at least one. Here, the transparent conductive layer 26 is described as being formed using indium tin oxide (ITO).
The metal layer 27 is formed on the transparent conductive layer 26. The metal layer 27 is a seed layer including a metal such as copper (Cu) or an alloy, for example. Here, the “seed layer” refers to a layer that is a starting point for plating growth.
The first electrode portion 28 is an electrode formed on the metal layer 27 by plating. The first electrode unit 28 includes, for example, copper (Cu).
The second electrode part 29 is an electrode formed on the first electrode part 28 by plating. For example, the second electrode unit 29 includes tin (Sn).
The i-p stacked portions 31 are formed on the back surface of the n-type single crystal silicon substrate 18 so as to be alternately arranged with the i-n stacked portions 21. The i-p stacked portion 31 includes an i-type amorphous silicon layer 32 and a p-type amorphous silicon layer 33, and in the p-side electrode portion 35 described later, more from the surface of the photoelectric conversion element 10. It is preferable to arrange so that the current can be collected. For example, it is preferable that the i-p stacked portion 31 has a comb shape in which a plurality of finger portions extend in parallel.
The i-type amorphous silicon layer 32 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18. The p-type amorphous silicon layer 33 is formed on the i-type amorphous silicon layer 32. The i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 constitute a part of an amorphous semiconductor layer formed on the back surface. The i-type amorphous silicon layer 32 is a layer made of an intrinsic amorphous semiconductor film. The p-type amorphous silicon layer 33 is a layer made of an amorphous semiconductor film containing a p-type conductive dopant. For example, the p-type amorphous silicon layer 33 preferably has a p-type dopant concentration of 1 × 10 21 / cm 3 or more.
The p-side electrode portion 35 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10. The p-side electrode part 35 includes a transparent conductive layer 36, a metal layer 37, a first electrode part 38, and a second electrode part 39.
The transparent conductive layer 36 is formed on the p-type amorphous silicon layer 33. On the transparent conductive layer 36, a metal layer 37, a first electrode portion 38, and a second electrode portion 39 are formed. Here, the materials and the like of the transparent conductive layer 36, the metal layer 37, the first electrode portion 38, and the second electrode portion 39 are the same as those of the transparent conductive layer 26, the metal layer 27, the first electrode portion 28, and the second electrode portion 29. Therefore, detailed description is omitted.
Next, an example of a method for manufacturing the photoelectric conversion element 10 will be described. FIG. 2 is a flowchart showing the procedure of the method for manufacturing the photoelectric conversion element 10. In addition, the manufacturing method of the photoelectric conversion element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
First, an n-type single crystal silicon substrate 18 is prepared, and the light receiving surface and the back surface of the n-type single crystal silicon substrate 18 are cleaned (S1). Here, the n-type single crystal silicon substrate 18 can be cleaned using, for example, an HF aqueous solution.
Next, a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S2). Here, for the formation of the texture structure, for example, an anisotropic etching solution such as a potassium hydroxide aqueous solution (KOH aqueous solution) is used. Thereby, a pyramidal uneven shape can be formed on the light receiving surface of the n-type single crystal silicon substrate 18.
Then, as shown in FIG. 3, an i-type amorphous silicon layer 16 and an n-type amorphous silicon layer 14 are formed on the light receiving surface of the n-type single crystal silicon substrate 18, and the n-type single crystal silicon is formed. An i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a are formed on the back surface of the substrate 18 (S3). Here, each of the i-type amorphous silicon layer 16, the n-type amorphous silicon layer 14, the i-type amorphous silicon layer 22a, and the n-type amorphous silicon layer 23a is formed by, for example, a plasma CVD method or the like. can do.
Subsequently, as shown in FIG. 4, an insulating layer 24a is formed on the n-type amorphous silicon layer 23a (S4). The insulating layer 24a can be formed by, for example, a thin film forming method such as a sputtering method or a plasma CVD method.
Thereafter, as shown in FIG. 5, the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S5). The antireflection layer 12 can be formed by, for example, a thin film forming method such as a sputtering method or a plasma CVD method.
Next, as shown in FIG. 6, the insulating layer 24a is etched to remove a part of the insulating layer 24a (S6). Specifically, the insulating layer 24b is formed by removing a portion of the insulating layer 24a located on a region for forming the ip stacked portion 31 on the n-type single crystal silicon substrate 18 in a later step. . Here, for the etching of the insulating layer 24a, for example, an acidic etching solution such as an HF aqueous solution is used.
Then, as shown in FIG. 7, using the insulating layer 24b patterned in S6 as a mask, the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched (S7). Specifically, the portions other than the portion covered with the insulating layer 24b are removed from the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a. Thus, the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 are formed by exposing a portion of the back surface of the n-type single crystal silicon substrate 18 where the insulating layer 24b is not located. Here, for etching the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a, for example, an alkaline etching solution such as an aqueous solution containing sodium hydroxide (NaOH) is used.
Subsequently, as shown in FIG. 8, the insulating layer 24b, the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23, and the exposed back surface of the n-type single crystal silicon substrate 18 are covered. An i-type amorphous silicon layer 32a and a p-type amorphous silicon layer 33a are formed (S8). The i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a can be formed by, for example, a plasma CVD method or the like.
Thereafter, as shown in FIG. 9, a part of the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a located on the insulating layer 24b is etched (S9). Thereby, the i-type amorphous silicon layer 32b and the p-type amorphous silicon layer 33b are formed. Here, for etching the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a, for example, an alkaline etching solution such as an aqueous solution containing sodium hydroxide (NaOH) is used.
Next, as shown in FIG. 10, the insulating layer 24b is etched to further remove a portion of the insulating layer 24b (S10). Specifically, the insulating layer 24 is formed by removing the exposed portion of the insulating layer 24b by etching using the i-type amorphous silicon layer 32b and the p-type amorphous silicon layer 33b as a mask. Here, for the etching of the insulating layer 24b, for example, an acidic etching solution such as an HF aqueous solution is used.
Then, as shown in FIG. 11, a transparent conductive layer 26a and a metal layer 27a are formed (S11). Specifically, it is formed by a thin film forming method such as a plasma CVD method or a sputtering method.
Subsequently, as shown in FIG. 12, the transparent conductive layers 26 and 36 and the metal layers 27 and 37 are separated by dividing a portion of the transparent conductive layer 26a and the metal layer 27a located on the insulating layer 24. Form (S12). Here, the transparent conductive layer 26a and the metal layer 27a are divided by, for example, etching using a resist mask.
Thereafter, as shown in FIG. 13, the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating, and the first electrode portion 38 and the second electrode portion 29 are formed on the metal layer 37. The electrode portions 39 are sequentially formed (S13). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
In general, in order to suppress recombination of carriers generated in the n-type single crystal silicon substrate 18 of the photoelectric conversion element 10, the interface between the n-type single crystal silicon substrate 18 and the i-type amorphous silicon layer 16, and It is preferable to keep the interface between the n-type single crystal silicon substrate 18 and the i-type amorphous silicon layers 22 and 32 clean. Here, due to the difference in the degree of vacuum at the time of film formation and the wraparound of the source gas, the film formation of the antireflection layer 12 and the insulating layer 24 is performed more than the film formation of the i-type amorphous silicon films 22 and 32. The degree of contamination on the opposite side of the membrane is large. Therefore, in the present embodiment, the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 are formed on the light receiving surface of the n-type single crystal silicon substrate 18, and the i-type amorphous silicon layer 14 is formed on the back surface. After the silicon layer 22 and the n-type amorphous silicon layer 23 are formed, the antireflection layer 12 and the insulating layer 24 are formed, so that both surfaces of the n-type single crystal silicon substrate 18 are at least i-type amorphous silicon. After being covered with the layers 16 and 22, the antireflection layer 12 and the insulating layer 24 are formed. This prevents the interface between the n-type single crystal silicon substrate 18 and the i-type amorphous silicon layers 16, 22, and 32 from being contaminated when the antireflection layer 12 and the insulating layer 24 are formed. Therefore, the i-type amorphous silicon layers 16, 22, and 32 can be suitably functioned as passivation layers, and the power generation characteristics of the photoelectric conversion element 10 can be improved.
Further, as the order of forming the antireflection layer 12 and the insulating layer 24, the insulating layer 24 located on the back surface side is formed before the antireflection layer 12 located on the light receiving surface side is formed. That is, the n-type amorphous silicon layer 23 is covered by forming the insulating layer 24, and the source gas for forming the subsequent antireflection layer 12 flows around the n-type amorphous silicon layer 23. Is preventing. As a result, the surface of the n-type amorphous silicon layer 23 in contact with the n-side electrode part 25 that directly contributes to the collection of carriers can be kept clean, and the contact resistance with the n-side electrode part 25 can be reduced. Can do. Therefore, the current collection efficiency in the n-side electrode portion 25 is improved, and the power generation characteristics of the photoelectric conversion element 10 can be improved.
In general, the insulating layer 24a has higher mechanical strength than the n-type amorphous silicon layer 23a. By covering the n-type amorphous silicon layer 23a with the insulating layer 24a, the surface of the n-type amorphous silicon layer 23a can be prevented from being damaged during the manufacturing process of the photoelectric conversion element 10, and the n side The electrical contact with the electrode part 25 is increased, and the contact resistance can be reduced. Therefore, the current collection efficiency in the n-side electrode portion 25 is improved, and the power generation characteristics of the photoelectric conversion element 10 can be improved.
10 photoelectric conversion element, 12 antireflection layer, 24, 24a, 24b insulating layer, 14, 23, 23a n-type amorphous silicon layer, 16, 22, 22a, 32, 32a, 32b i-type amorphous silicon layer, 18 n-type single crystal silicon substrate, 21 i-n laminated portion, 25 n-side electrode portion, 26, 26a, 36 transparent conductive layer, 27, 27a, 37 metal layer, 28, 38 first electrode portion, 29, 39 first 2 electrode part, 31 ip laminated part, 33, 33a, 33b p-type amorphous silicon layer, 35 p side electrode part.
A first step of forming a first amorphous semiconductor layer on a light receiving surface of a crystalline semiconductor substrate;
A second step of forming a second amorphous semiconductor layer on the back surface of the crystalline semiconductor substrate;
A third step of forming a protective layer on the first amorphous semiconductor layer and the second amorphous semiconductor layer after finishing the first step and the second step;
The third step includes
Method of manufacturing a photoelectric conversion element characterized that you form the protective layer on the first amorphous-based semiconductor layer after forming the protective layer on the second amorphous-based semiconductor layer.
In the manufacturing method of the photoelectric conversion element of Claim 1 ,
The crystalline semiconductor substrate is n-type,
The first amorphous semiconductor layer includes
A first i-type amorphous semiconductor layer formed on the light-receiving surface of the crystalline semiconductor substrate;
A first n-type amorphous semiconductor layer formed on the first i-type amorphous semiconductor layer;
The second amorphous semiconductor layer includes
A second i-type amorphous semiconductor layer formed on the back surface of the crystalline semiconductor substrate;
A second n-type amorphous semiconductor layer formed on the second i-type amorphous semiconductor layer;
A process for producing a photoelectric conversion element comprising:
In the manufacturing method of the photoelectric conversion element of Claim 2 ,
A first electrode portion formed in a first region on the second n-type amorphous semiconductor layer;
A second electrode portion formed in a second region different from the first region among regions on the second p-type amorphous semiconductor layer formed on the back surface;
A process for producing a photoelectric conversion element, comprising:
In the manufacturing method of the photoelectric conversion element of any one of Claims 1-3 ,
The method for manufacturing a photoelectric conversion element, wherein the protective layer includes any one of aluminum oxide, aluminum nitride, silicon nitride, and silicon oxide.
JP2013507402A 2011-03-25 2012-03-19 Method for manufacturing photoelectric conversion element Active JP5891382B2 (en)
JP2011067625 2011-03-25
PCT/JP2012/057006 WO2012132995A1 (en) 2011-03-25 2012-03-19 Method for producing photoelectric conversion element
JP2013507402A JP5891382B2 (en) 2011-03-25 2012-03-19 Method for manufacturing photoelectric conversion element
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JP5891382B2 true JP5891382B2 (en) 2016-03-23
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JP2013507402A Active JP5891382B2 (en) 2011-03-25 2012-03-19 Method for manufacturing photoelectric conversion element
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