Source: http://www.google.com/patents/US8183686?dq=5910382
Timestamp: 2017-11-19 03:11:50
Document Index: 31077417

Matched Legal Cases: ['art 7', 'art 8', 'art 9', 'art 7', 'art 8', 'art 9', 'art 7']

Patent US8183686 - Semiconductor device - Google Patents
Between a logic LSI (4) arranged on one side of a DRAM (1) and jointed to the DRAM and a radiating member (6) arranged on the other side of the DRAM (1) for irradiating the heats of the DRAM (1) and the logic LSI (4), there is disposed a heat bypass passage (5), which extends inbetween while bypassing...http://www.google.com/patents/US8183686?utm_source=gb-gplus-sharePatent US8183686 - Semiconductor device
Publication number US8183686 B2
Application number US 12/530,093
PCT number PCT/JP2008/053769
Also published as US8878358, US20100102441, US20120205792, WO2008108335A1
Publication number 12530093, 530093, PCT/2008/53769, PCT/JP/2008/053769, PCT/JP/2008/53769, PCT/JP/8/053769, PCT/JP/8/53769, PCT/JP2008/053769, PCT/JP2008/53769, PCT/JP2008053769, PCT/JP200853769, PCT/JP8/053769, PCT/JP8/53769, PCT/JP8053769, PCT/JP853769, US 8183686 B2, US 8183686B2, US-B2-8183686, US8183686 B2, US8183686B2
US 8183686 B2
10. The semiconductor device according to claim 1, wherein the first substrate is a logic LSI and the second substrate is a memory.
The semiconductor device 10 comprises an overmold 2, which is a protection member for protecting the DRAM 1. The overmold 2 is formed from, for example, epoxy resin and ceramic, and is disposed to surround the upper and side portions of the DRAM 1. The thermal conductivity of the overmold 2 is 0.7 W/m° C. in the example of the figure.
The heat bypass path 5 has a first bypass part 7, a second bypass part 8, and a third bypass part 9. Each of the first bypass part 7, second bypass part 8 and third bypass part 9 is formed from, for example, copper or aluminum. In the case where each bypass part 7, 8, 9 is formed from copper, each thermal conductivity is 392 W/m° C.
In the embodiments shown in FIG. 1 through FIG. 4, an example where the heat radiating fin 6 is disposed on the overmold 2 is shown. Alternatively, the heat radiating fin 6 may be disposed above the top-layer semiconductor chip 1 a in the plurality of stacked semiconductor chips 1 a so that the heat radiating fin 6 is joined to the top-layer semiconductor chip 1 a. In this case, the heat radiating fin 6 may be joined to the top-layer semiconductor chip 1 a by, for example, adhesive. In the stacking process for the plurality of semiconductor chips 1 a, the heat radiating fin 6 is used as one layer and the heat radiating fin 6 can be joined by stacking the heat radiating fin 6 on the top-layer semiconductor chip 1 a.
Thus, the heat radiating fin 6 can be easily assembled by joining the heat radiating fin 6 to the DRAM 1 in the above stacking process.
JP2002110869A Title not available
JP2005005529A Title not available
JP2005166752A Title not available
JP2006210892A Title not available
JPS6336052A Title not available
1 International Search Report, Japanese Patent Office, May 21, 2008.
U.S. Classification 257/714, 257/E23.08
Cooperative Classification H01L2225/06589, H01L23/4334, H01L23/427, H01L25/18, H01L2924/15321
European Classification H01L23/427, H01L23/433E, H01L25/18
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SUGAYA, ISAO;REEL/FRAME:023197/0159