Source: http://www.google.com/patents/US6272581?dq=6,976,008
Timestamp: 2015-01-31 10:07:36
Document Index: 378305996

Matched Legal Cases: ['art 7', 'art 7', 'art 7', 'art 7', 'art 7', 'art 7', 'art 7', 'art 7', 'art 7', 'art 7']

Patent US6272581 - System and method for encapsulating legacy data transport protocols for IEEE ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA data transfer protocol encapsulates legacy transport protocols (e.g., TCP/IP, UDP/IP, IPX/SPX, etc.) for transfer of data over a memory mapped, high-speed serial bus conforming to the IEEE 1394 standard. The data transfer protocol is implemented as a databus manager layer interposed between the 1394...http://www.google.com/patents/US6272581?utm_source=gb-gplus-sharePatent US6272581 - System and method for encapsulating legacy data transport protocols for IEEE 1394 serial busAdvanced Patent SearchPublication numberUS6272581 B1Publication typeGrantApplication numberUS 09/561,383Publication dateAug 7, 2001Filing dateApr 27, 2000Priority dateMay 20, 1997Fee statusLapsedAlso published asUS5938752, US5938752, US6038628, US6038628, US6266729Publication number09561383, 561383, US 6272581 B1, US 6272581B1, US-B1-6272581, US6272581 B1, US6272581B1InventorsYuen Yu Leung, Shaun D. PierceOriginal AssigneeMicrosoft CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (10), Non-Patent Citations (14), Referenced by (6), Classifications (9), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSystem and method for encapsulating legacy data transport protocols for IEEE 1394 serial busUS 6272581 B1Abstract A data transfer protocol encapsulates legacy transport protocols (e.g., TCP/IP, UDP/IP, IPX/SPX, etc.) for transfer of data over a memory mapped, high-speed serial bus conforming to the IEEE 1394 standard. The data transfer protocol is implemented as a databus manager layer interposed between the 1394 bus and an existing network layer (e.g., SCSI, Ethernet, FDDI, token ring, etc.). A databus manager resides at every node on the 1394 bus. Each databus manager has an array of memory cells to temporarily hold discrete data units transferred over the serial bus from a remote node. Each databus manager also has a cell availability register and a cell servicing register. The cell availability register holds information indicating whether one or more remote memory cells at the remote node are available to receive a data unit to be transferred over the serial bus. The cell servicing register holds information indicating whether one or more of the local memory cells are ready to be serviced.
What is claimed is: 1. In a distributed computing system, a method for transmitting legacy formatted data from a source node to a memory cell at a destination node over a serial bus, the method comprising the steps of:
determining whether the memory cell at the destination node is available; segmenting the legacy formatted data into an ordered plurality of data packets at the source node, each of the ordered plurality of data packets conforming to a specified packet size for transmission over the serial bus, and furthermore, each of the ordered plurality of data packets not encoding information for ordering the ordered plurality of data packets; transmitting the ordered plurality of data packets from the source node to the destination node; storing the ordered plurality of data packets in the memory cell at the destination node; and generating a signal at the source node indicating that the memory cell at the destination node is unavailable for additional write operations. 2. The method of claim 1 further including the step of generating a signal at the destination node indicating that the memory cell at the destination node is unavailable for additional write operations.
maintaining a cell availability register at the source node that holds information indicating whether the memory cell at the destination node is available to receive one or more data units; maintaining a cell servicing register at the destination node that holds information indicating whether the memory cell at the destination node is ready to be serviced; determining if the message is larger than the packet size; segmenting the message into a sequence of data units, each of the data units not encoding information for ordering the sequence of data units, when the message is larger than the packet size; examining the cell availability register at the source node to determine if the memory cell at the destination node is available to receive any data units; transmitting the sequence of data units from the source node to the destination node over the serial bus; storing the sequence of data units in the memory cell at the destination node such that the message may be recreated from the sequence of data units in the memory cell at the destination node; updating the cell availability register at the source node to indicate that the memory cell at the destination node is unavailable; and updating the cell servicing register at the destination node to indicate that the memory cell at the destination node is ready to be serviced. 11. The method of claim 10 further including the step of servicing the memory cell at the destination node.
a local memory cell array located at the local node disposed to temporarily store messages as discrete data units transmitted over the IEEE 1394 serial bus; a remote memory cell array located at the remote node disposed to temporarily store messages as discrete data units transferred over the IEEE 1394 serial bus, the remote memory cell array including a selected memory cell; a local databus manager at the local node for managing an exchange of the data units over the IEEE 1394 serial bus, the local databus manager segmenting data as a sequence of data units lacking encoded ordering information; and a remote databus manager disposed to receive the sequence of data units, and building the message in the selected memory cell from the sequence in which the data units are placed in the selected memory cell at the remote node. 15. A method for sending data from a source node to a destination node across an IEEE 1394 compliant serial bus, the serial bus included in a distributed computing environment, the method comprising the steps of:
generating data packets at the source node that are capable of being transmitted over an interconnected network of computers but not over an IEEE 1394 compliant serial bus; converting the data packets at the source node into compatible data packets that are in a format which is compatible with transmission over the IEEE 1394 compliant serial bus without removing data stored in the data packets; transmitting the compatible data packets over the IEEE 1394 compliant serial bus from the source node to the destination node; and indicating that transmission of a predetermined number of compatible data packets has been completed. 16. A method for sending data from a source node to a destination node across an IEEE 1394 compliant serial bus, the serial bus included in a distributed computing environment, the method comprising the steps of:
generating data packets at the source node that are capable of being transmitted over an interconnected network of computers but not over an IEEE 1394 compliant serial bus; converting the data packets at the source node into compatible data packets that are in a format which is compatible with transmission over the IEEE 1394 compliant serial bus without removing data stored in the data packets; transmitting the compatible data packets over the IEEE 1394 compliant serial bus from the source node to the destination node; and determining that a memory cell in a buffer at the destination node is available to receive one or more data packets. 17. A method for sending data from a source node to a destination node across an IEEE 1394 compliant serial bus, the serial bus included in a distributed computing environment, the method comprising the steps of:
generating data packets at the source node that are capable of being transmitted over an interconnected network of computers but not over an IEEE 1394 compliant serial bus; converting the data packets at the source node into compatible data packets that are in a format which is compatible with transmission over the IEEE 1394 compliant serial bus without removing data stored in the data packets; transmitting the compatible data packets over the IEEE 1394 compliant serial bus from the source node to the destination node; and providing a first signal to indicate that a memory cell at the destination node is unavailable to receive one or more data packets.
RELATED APPLICATIONS This is a continuation of U.S. patent application Ser. No. 09/272,059, filed Mar. 18, 1999, which is a divisional of U.S. patent application Ser. No. 08/859,613, filed May 20, 1997, which issued as U.S. Pat. No. 5,938,752 on Aug. 17, 1999.
TECHNICAL FIELD This invention relates to data transfer protocols for a high speed serial bus, such as a serial bus that conforms to the IEEE 1394 standard More particularly, this invention relates to systems, data structures, and methods implemented at nodes on the serial bus for encapsulating data packets from various legacy protocols and transferring those packets over the serial bus.
BACKGROUND OF THE INVENTION IEEE 1394 specifies a standard for a high performance serial bus (hereinafter the �1394 bus�). The 1394 bus uses a generic data transfer protocol to facilitate communication among nodes. One of the intended uses of the 1394 bus is to transfer data, and to be used in conjunction with legacy data transfer protocols. Using a legacy data transfer protocol and transport layer is advantageous because existing hardware and software already support them.
FIG. 3 shows a hardware/software architecture of the network protocol layers implemented at the nodes A and B. Each node contains the same hierarchic architecture. The top layer is the file system 42 of the operating system. At this layer, data exists as high level files that can be handled by applications running on the computers. For discussion purposes, the same components in FIG. 3 are generally described with a single number, such as file system layer �42�, but the illustrated blocks are referenced with ;an extension of �A� or �B� to differentiate the nodes at which the components reside.
FIG. 6 shows the registers and memory cells at this point. Two packets X and Y are located in memory cells A1 and A4 of memory array 50A, and two packets P and Q are located in memory cells B2 and B6 of memory array 50B. At the source node A, the cell availability register 52A shows that the remote memory cells B2 and B6 are not available, as represented by the asserted �1� bit in the corresponding bit map. The binary �0� value in the cell availability register 52A indicates that the memory cells B1, B3, B4 and 5 at destination node B are available to receive data. Of course, a different logic arrangement may be used, such as setting a �1� bit when the remote cell is available and resetting a �0� bit when the remote cell is not available. The cell servicing register 54A indicates that local memory cells A1 and A4 of the local memory array 50A are ready to be serviced.
FIG. 7 shows the packet R being written to memory cell B3. At this point, memory cell B3 is no longer available to receive data. Accordingly, the source databus manager 40A updates its cell availability register 52A to reflect that the destination memory cell is no longer available (step 76 in FIG. 5). This is done by changing the bit value in register space B3 of register 52A, which corresponds to the destination remote memory cell B3, from a binary �0� to a binary �1�.
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