Source: http://www.google.com/patents/US4272776?dq=7,003,515
Timestamp: 2013-12-06 08:27:55
Document Index: 418172444

Matched Legal Cases: ['arts 42', 'art 123', 'art 108', 'art 107', 'arts 214', 'arts 232']

Patent US4272776 - Semiconductor device and method of manufacturing same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsAn inset oxide isolated integrated circuit, with multiple levels of inset oxide, polycrystalline regions, and channel stops....http://www.google.com/patents/US4272776?utm_source=gb-gplus-sharePatent US4272776 - Semiconductor device and method of manufacturing samePublication numberUS4272776 APublication typeGrantApplication numberUS 05/254,604Publication dateJun 9, 1981Filing dateMay 18, 1972Priority dateMay 22, 1971Also published asCA975467A1, DE2224634A1, DE2224634C2Publication number05254604, 254604, US 4272776 A, US 4272776A, US-A-4272776, US4272776 A, US4272776AInventorsWilhelmus H. C. G. Verkuijlen, Bernard H. WeijlandOriginal AssigneeU.S. Philips CorporationPatent Citations (19), Non-Patent Citations (3), Referenced by (24), Classifications (48) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and method of manufacturing sameUS 4272776 AAbstract An inset oxide isolated integrated circuit, with multiple levels of inset oxide, polycrystalline regions, and channel stops.
What is claimed is: 1. A semiconductor device comprising a body, said body comprising a monocrystalline substrate, at least a first layer consisting of silicon semiconducor material on a surface of said substrate, at least part of said first layer being monocrystalline, a second layer of insulating material located at only part of the said substrate surface and buried within the body, the buried second layer consisting at least partly of silicon nitride, and means forming an isolation zone for isolating part of the first semiconductor layer which is monocrystalline from another part of the semiconductor layer, said isolation zone comprising at least partly a third layer of insulating material inset in the first semiconductor layer from its surface and extending down to and at least partly adjoining the second insulating layer, said third layer consisting of silicon oxide formed by in situ conversion of the semiconductor material of the first semiconductor layer, the lateral extent of the second layer being different from the lateral extent of the third layer where it adjoins the second layer.
7. A semiconductor device as claimed in claim 2, wherein the second layer is inset in the substrate to a depth of more than 0.5.mu..
As regards depths of inset, depths of more than 0.5.mu., preferably at least 1μ, are preferably used. Since the inset insulation layer on its lower side adjoins a buried insulation layer, a continuous zone, if any, of one conductivity type, formed along the edge of the insulation layer by accumulation and/or extraction of impurities, is divided into two zones present on either side of the inset insulation layer and separated from each other by insulating material.
The manufacture of an embodiment of a semiconductor device according to the invention will now be described with reference to FIGS. 1 to 8 which are cross-sectional views of a detail of such a device in various stages of its manufacture. Starting material is a semiconductor body consisting of monocrystalline p-type silicon having a resistivity of 1 ohm cm (see FIG. 1). Such a disc-shaped silicon body 1 can be obtained in normal manner by dividing a rod-shaped monocrystal in known manner into slices and reducing said slices, if desired, to the desired thickness, for example 150μ, by known material-removing treatments. On one side the surface of the silicon body is provided with an insulation layer 2 the lower part of which may consist of boron-doped silicon oxide and the upper part of which may consist of undoped silicon oxide, which layer may have an overall thickness of 0.5.mu. and be provided by deposition at low temperature, for example, by reaction of SiH.sub.4 with oxygen. The boron may be added in the form of boron hydride.
Windows 3 are etched in the insulation layer 2 by means of a conventional photoetching method. The remaining insulation layer thereby obtains the form of a network the windows 3 of which form the meshes. The resulting stage is shown diagrammatically in FIG. 1. The silicon body is then subjected to a conventional diffusion treatment with arsenic, the insulation layer 2 serving as a mask. The resulting stage is shown diagrammatically in FIG. 2. A comparatively shallow arsenic diffusion has taken place in the windows, the n-conductive layers 5, 6, 7 and 8 being formed. Simultaneously with the arsenic diffusion, boron is diffused into the underlying silicon from the insulation layer 2 so that at that area a highly doped p-conductive zone 4 is formed which adjoins the p-conductive material of the body and which forms a lateral separation of the n-conductive regions 5, 6, 7 and 8. The semiconductor body thus treated now serves as a substrate for providing a semiconductor layer of silicon. The silicon may be deposited, for example, from a gas mixture, of SiH.sub.4 and hydrogen to which a little PH.sub.3 has been added. The thickness of the provided layer 10 is approximately 2.5.mu. (see FIG. 3). From the semiconductor surface in the windows 3 the silicon grows epitaxially and forms monocrystalline n-conductive regions 12, 13, 14 and 15. Silicon likewise deposits on the insulation layer 2 but in a polycrystalline form. As a result of this the layer 10 consists of a network of polycrystalline material 11 which laterally separates the monocrystalline regions 12, 13, 14 and 15 from each other. The layer 2 now forms a buried insulation layer in the resulting semiconductor body. The layer 10 is provided at its surface with a silicon nitride layer 16, thickness for example 0.15.mu., obtained by deposition from a silicon hydride and ammonia-containing gas mixture. If desirable a thin oxide layer may be provided previously below the silicon nitride. Windows are etched in the silicon nitride layer by means of known photo etching methods, of which the windows 20, 22 and 24 are provided above the polycrystalline material 11. Together they again constitute a network. Windows 21 and 23, respectively, are furthermore provided locally on the monocrystalline regions 13 and 14, each window having the form of a strip which adjoins on either side the network of windows which is provided on the polycrystalline material 11. The resulting stage is shown in FIG. 3.
Inset insulation layers are then made by using a deep oxidation at the area of the grooves, the silicon nitride layer 16 being now used as a local masking of the underlying silicon against the oxidizing treatment. Since the silicon is converted into oxide, an increase in volume takes place so that when as a result of the oxidation process the depth increases, the groove itself will gradually be filled by formed silicon oxide. As a result of this the oxide layers 30, 31, 32, 33 and 34, respectively, having depths of well over 2μ (see FIG. 5) are formed at the area of the grooves 25, 26, 27, 28 and 29, respectively. Such a deep oxidation is obtained, for example, by heating the silicon body for 32 hours at 900 and 34 adjoin the buried oxide layer 2 with their lower sides. The inset oxide layers 31 and 33 extend down to the buried n-type silicon layers 6 and 7, respectively, which in the meantime may have expanded in the silicon layer 10 from the substrate by further diffusion of arsenic. Beside the inset oxide layers 32 and 34, parts 42 and 44 of the polycrystalline silicon zone 11 have been maintained. The low-ohmic n-type epitaxial regions 13 and 14 have been divided into the regions 36, 37 and 38, 39, respectively, by the formation of the inset insulation layers 31 and 33, respectively. The resulting stage is shown in FIG. 5.
Semiconductor devices can now be formed in the resulting islands which are isolated from each other, for example, n-p-n transistors in the regions 13 and 15 and a diode in the region 14. For this purpose the silicon nitride layer 16 is removed by means of an etching method known per se from the regions 12, 36, 38 and 15 but is maintained on the regions 37 and 39 (see FIG. 6). Boron is in-diffused from the surface of said regions, p-conductive regions 56, 57, 58 and 59 being formed which are laterally bounded by insulation material and on their lower side adjoin with a substantially flat p-n junction the underlying n-type material as this was originally provided epitaxially during the formation of the layer 10. The zones 57 and 59 serve to form the base zones of the transistors. P-type zone 58 and n-type zone 38 form the electrodes of the diode. A possibly formed oxide skin on the p-type zones 56, 57, 58 and 59 is removed by etching and a fresh oxide skin 51, 52, 53 and 54 is provided at that area, for example, by means of a known oxidation reaction during which a thin oxide layer of, for example, 0.5.mu. is formed. The remaining nitride layer 16 serves as a mask for protecting the regions 37, 42 and 39, 44. The resulting stage is shown in FIG. 6. It is to be noted that a silicon nitride mask, to be removed afterwards, for diffusion processes is preferably used if the temperatures used during the diffusion process are not too high, for example, remain below 1100 nitride which is heated at at least 1100 easily. However, it is possible to remove the silicon nitride entirely for the diffusion treatment to form the zones 56, 57, 58 and 59 and to use locally a diffusion mask of, for example, silicon oxide.
The body is then subjected to an oxidation treatment to form inset insulation layers, the silicon nitride 110 serving as an oxidation mask for this treatment. For that purpose the body is subjected to an oxidation treatment with steam similar to that described above with reference to FIGS. 1 to 8. The temperature used is, for example, 1000 the duration of the treatment is approximately 16 hours. At the area of the grooves 115, 116 and 117 the adjoining silicon is converted to such a depth that the formed oxide adjoins the buried nitride layer 102. As a result of the increase in volume associated with the conversion, the grooves 115, 116 and 117 are entirely filled with silicon oxide. In this manner, at the area of the windows 111, 112 and 113 in the silicon nitride layer 110, inset insulation layers of silicon oxide 120, 121 and 122, respectively, are formed which on their lower side adjoin the buried insulation layer 102. Of the original polycrystalline strip 106 a part 123 remains which is laterally bounded by the inset insulation layers 120 and 121 and is bounded on its upper and lower side by the silicon nitride layers 110 and 102, respectively. A region 124 of the polycrystalline part 108 is maintained between the inset insulation layer 122 and the epitaxially provided part 107 of the layer 105. On its lower side this region is bounded by the buried insulation layer 102 of silicon nitride.
The masking layer 137 is now removed entirely after which a silicon oxide layer 170 is formed on the exposed silicon parts, for example, by means of a conventional oxidation process by means of a gas mixture from water vapour and nitrogen. This oxide layer has a thickness, for example, of 0.3.mu.. By means of a conventional photoetching method the oxide layer 170 is entirely removed from the silicon regions present between the inset insulation layers 158 and 159. At the same time, a window 171 is provided in the part of the oxide layer present on the region 132 which window has laterally remained at a small distance from the highly doped p-type peripheral zone 166. Phosphorus is then indiffused in the usual manner, the remaining silicon oxide layer 170 serving as a mask. A p-type emitter 173 is formed in the region 132. At the same time a low-ohmic n-type region 174 present at the surface is formed in the region 134. The phosphorus simultaneously diffuses in the exposed polycrystalline regions 163 and 165. As a result of the larger diffusion rate of phosphorus in polycrystalline silicon, said regions are doped with phosphorus throughout their depth in a comparatively high concentration. Should in the monocrystalline region 134 the diffusion of the phosphorus from the surface and the diffusion of the phosphorus from the buried layer 125 be insufficient to make the region 134 entirely n type, as a result of which a thin p-type zone would remain, a sufficiently conductive connection would all the same be obtained between the regions 174 and 125 via the re-doped polycrystalline regions 163 and 165. The resulting stage is shown in FIG. 18. During the phosphorus diffusion a thin phosphate glass layer 174 may be formed on the free surface parts.
Reference numeral 200 in FIG. 20 denotes a substrate body which consists of monocrystalline p-type silicon having a resistivity of 2-5 ohm cm. On this body a silicon nitride masking 201 is provided in known manner, in a window of which a highly doped n-type zone 202 is provided by indiffusion of arsenic. On this an oxide pattern of boron-containing silicon oxide is provided in known manner as a result of which an oxide pattern in the form of a grating or mesh of strips 203, 204, 205 and 206 is formed on the highly doped n-type layer 202. A high-ohmic p-type silicon layer having a thickness of 0.5.mu. is then provided in known manner. On the exposed silicon of the monocrystalline substrate body the deposited silicon of the layer 207 is epitaxial and on the now buried insulation layers of silicon nitride and boron-containing silicon oxide, the deposit is polycrystalline. The resistivity of the monocrystalline p-type silicon is 0.5 ohm cm. In this manner monocrystalline regions 213, 214, 215, 216 and 217 which are separated from each other are formed. The regions 214 and 216 are destined for the bases of the transistors to be manufactured, the buried n-type layer 202 of which forms the common emitter. Phosphorus is indiffused in the regions 213, 215 and 217. A layer 220 of high-ohmic n-type silicon is then deposited, the deposit on the monocrystalline parts of the previously provided layer 207 being epitaxial, and the deposit on the polycrystalline parts of the layer 207 being polycrystalline. The thickness of the layer 220 is 1.5.mu.. An inset oxide pattern is then provided in the two layers 220 and 207 in the above described manner by means of a silicon nitride masking, etching grooves, and a deep oxidation. The inset insulation layers 240, 241, 242, 243, 244 and 245 are obtained which adjoin on their lower sides the buried insulation layers 201, 203, 204, 205, 206 and 201, respectively.
The semiconductor body has now obtained the configuration shown in FIG. 20. In two islands transistor configurations have been obtained in which the buried n-type layer 202 forms a common emitter. The epitaxially provided p-type regions 214 and 216 form the bases. Since the arsenic doping in the buried layer 202 has a small diffusion coefficient, the comparatively high-ohmic p-type regions 214 and 216 which form parts of the provided layer 207 are only partly re-doped by diffusion from the layer 202 during the thermal treatments for the formation of the semiconductor device. The expansion of the n-type buried layer 202 in the epitaxially provided parts 214 and 216 is approximately 0.2.mu.. The remaining p-type zones which have thicknesses of approximately 0.3.mu. constitute the bases of the two transistors. The epitaxially provided n-type parts 232 and 234 constitute the collectors of the transistors.
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