Source: https://patents.justia.com/patent/9171756
Timestamp: 2019-10-23 08:16:55
Document Index: 256313844

Matched Legal Cases: ['§120', 'Application No. 2013', 'Application No. 095129638', 'Application No. 200680032364', 'Application No. 2008', 'Application No. 905', 'Application No. 095129638', 'application No. 2', 'Application No. 2012', 'Application No. 200680032364', 'Application No. 200680032364', 'Application No. 06789507', 'Application No. 06', 'Application No. 189173', 'Application No. 200680032364', 'Application No. 2008', 'Application No. 200680032364', 'Application No. 2012', 'Application No. 2008', 'Application No. 2008']

US Patent for 3D IC method and device Patent (Patent # 9,171,756 issued October 27, 2015) - Justia Patents Search
Justia Patents Assembly Of Plural Semiconductive Substrates Each Possessing Electrical DeviceUS Patent for 3D IC method and device Patent (Patent # 9,171,756)
Mar 6, 2014 - ZIPTRONIX, INC.
This application is a divisional of and claims the benefit of priority under 35 U.S.C. §120 from U.S. application Ser. No. 13/783,553, filed Mar. 4, 2013, which is a continuation of U.S. application Ser. No. 12/270,585, filed Nov. 13, 2008, now U.S. Pat. No. 8,389,378, which is a continuation of U.S. application Ser. No. 11/201,321, filed Aug. 11, 2005, now U.S. Pat. No. 7,485,968, the entire contents of each of which is incorporated herein by reference.
This application is related to application Ser. No. 09/532,886, now U.S. Pat. No. 6,500,794, Ser. No. 10/011,432, now U.S. Pat. No. 7,126,212, Ser. No. 10/359,608, now U.S. Pat. No. 6,962,835, Ser. No. 10/688,910, now U.S. Pat. No. 6,867,073, and Ser. No. 10/440,099, now U.S. Pat. No. 7,109,092.
Die 14-16 may be of the same technology as wafer 10, or of different technology. Die 14-16 may each be the same or different devices or materials. Each of die 14-16 has conductive structures 17 formed in a device region 18. Structures 17 are spaced apart to leave a gap therebetween, or may be a single structure with an aperture which may extend across the entire contact structure. In other words, the aperture may be a hole in contact structure or may divide the contact structure in two. The size of the gap or aperture may be determined by the photolithographic design rules for the particular technology being bonded. For example, a minimum lateral width of contact structures 12 and 17 may be required to subsequently form a reliable, low resistance electrical connection with interconnect metal.
An additional factor that determines the optimum size of the gap or aperture is a ratio of a distance given by the vertical separation between contact structures 17 and 12 plus the thickness of the contact structure 17 to the size of the gap or aperture. This defines an aspect ratio of a via that will subsequently be formed between contact structures 17 and 12 to enable an electrical interconnection between contact structures 17 and 12. This vertical separation is typically 1-5 microns, or less, for oxide to oxide direct bonding, as described in application Ser. No. 09/505,283, the contents of which are incorporated herein by reference, or potentially zero for metal direct bonding, as described in application Ser. No. 10/359,608, the contents of which are herein incorporated by reference. Furthermore, the contact structure 17 thickness is typically 0.5 to 5 microns. With a typical desired via aspect ratio of 0.5 to 5 depending on the process technology used, a typical range of the size of the gap is 0.3-20 microns for oxide to oxide bonding or ˜0.1-10 microns for metal direct bonding. The metal direct bonding case is described below in the fourth embodiment.
As shown in FIG. 3A, a conformal dielectric film 30 is formed over surface 13 of substrate 10 and dies 14-16. This film may be formed by, for example, CVD, PVD or PECVD and preferably consists of an oxide film such as silicon oxide of typical thickness range 0.1 to 1.0 micron. Also, a filler material such as a deposited or spun-on oxide or polymer 32 such as polyimide or benzocyclobutene may be formed over and/or between dies 14-16, as shown in FIG. 3B. Material 32 may be formed at various points in the process. FIG. 3B shows the example where material 32 is formed prior to forming films 30 and 40. Filler, material may also be formed after forming the structure shown in FIG. 3A, after forming hard mask 40 (FIG. 4), or at various other points in the process depending on many factors such as the materials chosen or temperature considerations. Other techniques may be used for forming filler material. For example a dielectric filler, for example, silicon oxide, may be used by successive or iterative steps of dielectric formation, for example using methods described above, and chemical-mechanical polishing. Alternatively, a conductive filler, for example metal formed by, for example, electroplating, may be used by successive or iterative steps of metal formation and chemo-mechanical polishing. Having a flat surface may improve forming photoresist and other films on the surface and forming apertures in such films, for example, aperture 41 shown in FIG. 4.
Note that protective hard mask 61 may also be selectively deposited on hard mask 40. An example is when hard mask 40 is conductive and deposition of protective hard mask 61 is accomplished with electroless plating. This may be advantageous for decreasing the required thickness of hard mask 40. A further advantage of deposition of protective hard mask material 61 on hard mask 40 may be a restriction of the aperture of via 50 resulting in shadowing of a portion of contact structures 17 from anisotropic etching of via 60. FIG. 7A illustrates one of the die 14-16 in detail to more clearly illustrate the subsequent steps. A conformal insulative film 70 is formed over mask 40 and contact structures 12 and 17, and the sidewall of vias 50 and 60, partially filling vias 50 and 60. Examples of a suitable insulative film are silicon oxide, silicon nitride or Parylene. The insulative film may be formed using a number of typical deposition methods including but not limited to physical vapor deposition, chemical vapor deposition, and vapor phase deposition. An example of physical vapor deposition is sputtering, an example of chemical vapor deposition is plasma enhanced chemical vapor deposition, and an example of vapor phase deposition is vaporization of a solid, followed by pyrolysis and then deposition.
A second embodiment of the method according to the invention is illustrated in FIG. 12. A hard mask 101 is formed on die 14-16 without any intervening dielectric layer. A typical range of hard mask 101 thickness is 0.1 to 1.0 microns. The hard mask 101 is preferably comprised of a material that has a high etch selectivity to a subsequent etch process or processes used to etch a via through thinned substrate 21 and device regions 18 and 11 to contact structures 12. An example of a hard mask is aluminum, tungsten, platinum, nickel, or molybdenum and an example of an etch process is an SF6-based reactive ion etch to etch a via through a thinned silicon substrate and a CF4-based reactive ion etch to etch a subsequent via through device regions 18 and 11 to contact structures 12. Apertures 102 are formed in mask 101 and the structure is processed as in the first embodiment to etch through the die substrates and device regions to expose structures 12 and 17, while preferably exposing the top surface of structures 17 to form a ledge (such as 27 shown in FIGS. 8A and 8B). Metallization is carried out as shown in FIGS. 7-9 using mask 103 to form metal contact 104, to produce the structure shown in FIG. 13. After CMP (FIG. 14), metal 105 is planarized, and the structure is suitable for subsequent processing including but not limited to photolithography-based interconnect routing or underbump metallization to support wirebonding or flip-chip packaging, similar to the metallization structure shown in FIG. 11. This processing may include the formation of an electrically insulating material on the exposed side of die 14-16 to provide electrical isolation for said interconnect routing or underbump metallization that is routed over the exposed side of die 14-16. To further assist interconnect routing or underbump metallization, a planarizing material as described in the first embodiment, for example a dielectric or a metal, or alternatively, a polyimide or benzocyclobutene material may be formed to planarize the surface of the structure, for example by filling any spaces between die, apertures or grooves, either before or after the CMP process.
The portion of surfaces of die 114-116 excluding contact structures 123 and the portion of surface 113 excluding contact structures 122 are preferably a non-conductive material, for example silicon oxide, silicon nitride, silicon oxynitride, or an alternate isolating material compatible with semiconductor integrated circuit manufacturing. Die 114-116 with exposed contact structures 123 are bonded to surface 113 with exposed contact structures 122, as described in application Ser. No. 10/359,608, with an alignment accuracy sufficient to align a portion of exposed contact structures 123 in the surface of die 114-116 with a portion of exposed contact structures 122 in surface 113 and align the non-conductive material portion of the surface of die 114-116 with a the non-conductive material portion of surface 113. The bond between the non-conductive material portion of surface of die 114-116 and the non-conductive material portion of surface 113 is preferably a direct bond as described in application Ser. No. 10/359,608. An alternate type of direct bond, for example as described in application Ser. No. 10/440,099 may also be used. The bond energy, preferably in excess of 1 J/m2, of the direct bond generates an internal pressure of contact structures 122 against contact structures 123 that results in an electrical connection between contact structures 122 and 123. It is thus preferred to use a direct bond that results in a higher bond energy at low temperature, for example those described above, in order to generate the highest internal pressure; however, a direct bond that results in a lower bond energy at low temperature, or requires a higher temperature to obtain a higher bond energy may also be acceptable for some applications. For example, a conventional direct bond that requires moderate temperature, for example less than 400 EC, or moderate pressure, for example less than 10 kg/cm2, to achieve a high bond energy, for example greater than 1 J/m2 may also be used.
The internal pressure of contact structures 122 against contact structures 123 resulting from the bond between the non-contact structures 123 portion of the surface of die 114-116 and the non-contact structures 122 portion of surface 113 may not be adequate to achieve a bond or result in an electrical connection with a preferably low resistance due to, for example, a native oxide or other contamination, for example, hydrocarbons, on the exposed metal surface of die 114-116 or surface 113. An improved bond or preferably lower resistance electrical connection between contact structures 123 and 122 may be achieved by removing the native oxide on contact structures 123 or 122. For example, dilute hydrofluoric acid may be used before contacting surface 113 with die surfaces 114-116. Furthermore, surface 113 and the surfaces of die 114-116 may be exposed to an inert ambient, for example nitrogen or argon, after removing the native oxide until contacting surface 113 with die surfaces 114-116. Alternatively, an improved bond or preferably lower resistance electrical connection between contact structures 123 and 122 may be achieved after bonding non-contact structures 123 portion of the surface of die 114-116 and the non-contact structures 122 portion of surface 113 by increasing the temperature of, e.g. heating, contact structures 122 and 123. Temperature increase can result in a preferably low resistance electrical connection by reduction of the native oxide or other contamination or by increasing the internal pressure between contact structures 123 and 122, for example if contact structures 123 or 122 have a higher thermal expansion coefficient relative to the non-metal material surrounding contact structures 123 and 122, or by both reduction of native oxide or other contamination and increase in internal pressure. The temperature increase may also increase interdiffusion between contact structures, such as 122 and 123 to result in a preferable low-resistance electrical connection. The temperature increase may thus enhance the metal bonding, metal contact, metal interconnect or conduction between contact structures 123 and 122. Contact resistances less than 1 ohm/:m2 have been achieved. For example, for two contact structures of about a 5 and 10:m in diameter and each about 1:m thick, resistances less than 50 mohms have been obtained.
If there are ICs, for example silicon ICs, in die 114-116 or in layer 111 below surface 113, the temperature increase is preferably less than 400 EC for 2 hours and further preferably less than 350 EC for 2 hours to avoid damage to the ICs, contact structures or other metal structures. The temperature increase resulting in enhanced metal bonding, metal contact, metal interconnect or conduction between contact structures 122 and 123 may be very low, for example as low as 50 EC for 10 minutes, if contact structures are comprised of a conductive material with susceptibility to thermal expansion or internal pressure or negligible native oxide, for example, gold.
The maximum internal pressure of contact structures 122 against contact structures 123 that can be generated from the bond between the portion of the surface of die 114-116 around contact structures 123 and portion of surface 113 around contact structures 122 or accommodated by post-bond temperature increase depends on the bond area of this portion of the surface of die 114-116 to this portion of surface 113 and the area of contact structures 123 against the area of contact structures 122. The sum of these two areas is typically less than the entire area of die 114-116 against surface 113 due to a residual area of contact structures 123 aligned with a non-contact structures 122 portion of surface 113 and a residual area of contact structures 122 aligned with a non-contact structures 123 portion of the surface of die 114-116 that results from a difference in lateral dimension between contact structures 123 and 122 and a bond misalignment between the surfaces of die 114-116 and surface 113. The maximum internal pressure that can be generated by bonding or accommodated by post-bond temperature increase can be approximated by the fracture strength of the bond between the portion of the surface of die 114-116 and the portion of surface 113 times the ratio of the area of this bond to the area of contact structures 123 against the area of contact structures 122. For example, if the portion of the surfaces of die 114-116 and the portion of surface 113 is comprised of silicon oxide with a fracture strength of 16,000 psi and the direct bond between the aligned portion of these portions has a fracture strength about one half that of silicon oxide, or 8,000 psi, and the contact structures 123 and 122 are circular with a diameter of 4 microns on a pitch of 10 microns, and perfectly aligned, a maximum internal pressure between contact structures 123 and 122 in excess of 60,000 psi is possible. This pressure is typically significantly greater than that generated by a post-bond temperature increase. For example, if contact structures 123 and 122 are comprised of copper with a CTE of 17 ppm and a shear modulus of 6,400,000 psi and the portion of the surface of die 114-116 and the portion of surface 113 is comprised of silicon oxide with a CTE of 0.5, and contact structures 123 are planar with the portion of die 114-116 and contact structures 122 are planar with the portion of surface 113, a stress of approximately 37,000 psi between contact structures 123 and 122 is expected at a post-bond temperature increase of 350 EC.
Following the single masking process described for the preceding embodiments, the structure shown in FIG. 19A may be produced when a plurality of contact structures 123 contacts a single contact structure 122 without covering the entirety of a single contact structure 122, where metal seed layer 90 forms an electrical interconnection to both contact structures 122 and 123. Alternatively, metal seed layer 90 may only contact structures 123, particularly if contact structures 123 cover the entirety of contact structures 122. The structure shown in FIG. 19A may be further processed to form a surface similar to surface 113 in FIG. 18 as described earlier in this embodiment and shown in FIG. 19B where contact structure 59 is similar to contact structure 122 and planarized material 58 is similar to the non-contact 122 portion of surface 113. Additional die with exposed contact structures 123 may then be bonded and interconnected to the surface with exposed contact 59 similar to the bonding of die 114-116 with exposed contact structures 123 to exposed contact structure 122. FIG. 19C illustrates a filled via with contact 124 without an aperture or gap.
For example, in FIG. 21C, where only one of the die 134-136 is shown, the step of etching a via 129 to expose contact structures 132 and 137 is simplified because there is no substrate portion 127 through which a via is required to be etched. Via 129 can thus be substantially less deep than the vias described in earlier embodiments, resulting in a substantial reduction in via cross section and corresponding increase in via density. In another example, in FIG. 21D, where only one of the die 134-136 is shown, the step of forming an electrical interconnection 128 between exposed contact structures 132 and 137 is simplified because there is no substrate portion 127 that requires a sidewall to electrically isolate electrical interconnection 128. FIG. 21E illustrates this embodiment including contact structures bonded in direct contact. It is noted that the structure shown in FIG. 21E may also include the contact structures configured as shown in die 135 and similar to contact structures 124 and 122 in FIG. 19C.
If thinned die substrate 161 is non-conductive, revealed contact structures 142 and contact structures 147 (154) may be interconnected with the formation of conductive material overlapping contact structures 142 and contact structures 147 (154). Alternatively, if thinned die substrate 161 is conductive, for example if thinned die substrate is comprised of silicon, an isolating sidewall electrically isolating thinned die substrate 161 from conductive material interconnecting contact structures 142 and contact structures 147 (154) is preferred. An isolating non-selective sidewall as described in earlier embodiments, for example sidewall 70 in FIG. 8A or 8B, can be formed after bonding of die 144-146 and subsequent thinning of die 144-146 to leave thinned die substrate 161 as shown in FIG. 23F for sidewall 62 when exposed contact structure 142 is planar to surface 143, similar to that shown in FIG. 23A and via 159 formed as shown in FIG. 22H, instead of sidewall formation before bonding as shown previously in FIG. 22K or FIG. 22L for via 163 formed as shown in FIG. 22I. An isolating selective sidewall similar to that described in the first embodiment but formed after bonding, thinning of die substrate, and revealing vias can also be used. As described in previous embodiments, sidewall formation is preferred to prevent undesired electrical conduction between the thinned die substrate and electrical interconnection between contact structures 142 and contact structures 147 (154).
The formation of thinned substrate 161, for example from substrate 140 in FIG. 22C, may compromise the mechanical integrity if the vias are not sufficiently deep. For example, a via depth of less than approximately 0.1 to 0.3 mm for a thinned substrate of 200 mm diameter and comprised of silicon is typically sufficient. This depth for vias below which mechanical integrity is compromised will be greater for a thinned substrate of greater diameter and less for a thinned substrate of lesser diameter. This compromise in mechanical integrity can be avoided by attaching the opposing side of the exposed surface of substrate 140 to a handle wafer 44 before the thinning of substrate 140 as shown in FIG. 24B for via 155 and contact structures 147 (154) formed as shown in FIG. 22C. The handle wafer 44 attachment can be done with a variety of bonding methods including direct bonding or adhesive bonding. After attaching the opposing side of the exposed surface of substrate 140 to a handle wafer 44 and thinning substrate 140 to formed thinned substrate 161 and reveal via 155, the thinned substrate 161 may be used as a bonding surface or a dielectric, for example, silicon oxide, may be deposited as a bonding layer as described above. After forming the preferred bonding surface, die 144-146 are singulated and bonded to surface 143 of substrate 140, and the singulated portion(s) of handle wafer 44 is removed. Singulation may done with at least one of dicing or scribing. Removal of the singulated portion(s) of handle wafer 44 may be done with at least one or a combination of grinding, chemical mechanical polishing, or etching.
Alternative to etching and filling vias through the die device region and a portion of the die substrate, the vias can be etched, or etched and filled, into only a portion of the die substrate, or a portion of the die device region and a portion of the die substrate, before formation of devices or completion of the die device region. For example, as shown in FIG. 25A, vias 172 are etched into die substrate 140 and through a portion of die device region 171, for example the semiconductive portion of a device region comprised of a layer of semiconductor transistors and a multilevel interconnect structure comprised of conducting material (not shown), for example metal, and insulating material, for example silicon oxide or other suitable materials, or where the device region would reside in the substrate. If portion of die device region 171 and die substrate 140 are comprised of a conducting material, for example semiconductor materials with sufficiently low resistivity, for example silicon used in typical CMOS wafer fabrication, a sidewall is preferably formed as described earlier in this and earlier embodiments and as shown in FIG. 25B for selective sidewall 173 that is also formed on the bottom of via 172 as described in earlier embodiments. Furthermore, if the structure in FIG. 25A is comprised of silicon, a very thin, for example, 5-50 nm, high quality selective silicon dioxide sidewall can be thermally grown, facilitating the lateral dimensions of via 172 to be substantially less than one micron enabling a very high areal density of vias in excess of 100,000,000 per square centimeter to be fabricated. Alternatively, a non-selective sidewall can be formed on the sidewall of via 172 without formation on the bottom of via 172 as described in earlier embodiments. Via 172 can then be lined with a suitable barrier layer, if needed, and filled with conductive material 174 forming, for example, a metal filled via as described above. Via 172 may also be filled with conductive polysilicon. Contact structures 123 may be formed in contact with the filled vias as shown in FIG. 25D. Alternatively, further processing may be conducted on the structure of FIG. 25C prior to formation of contact structures 123 to complete the fabrication of die device region 148, followed by formation of contact structures 123 in the upper portion of die device region 148, as shown in FIG. 25E. For example a multilevel interconnect structure may be formed comprised of conducting material, for example metal, and insulating material, for example similar to or identical with typical CMOS wafer fabrication. Typical metals include copper and aluminum and typical insulating materials include silicon oxide and low-k dielectrics. Contact structures 123 in die 114-116 can be formed as described in the fourth embodiment and shown in FIG. 25E. The device region 148 may include the formation of a conducting material 176 to electrically interconnect contact structures 123 with metal filled via 174. Conducting material 176 is shown in FIG. 25E to be vertical between conductive material 174 and contact structures 123 but may also include or entirely consist of lateral components, for example as provided for by the routing of interlevel metal in the fabrication of typical integrated circuits, for example CMOS wafer fabrication. See FIG. 25F with conducting material 178.
In this variation, after bonding, post-bond thinning reveals a via filled with metal instead of a via not filled with metal, for example as shown in the left-hand-side of FIG. 23L. In either variation, the die substrate portion may be entirely removed as described in the sixth embodiment. In addition, in either variation, bonding to a substrate without a device region but with contact structures prepared as described in the fourth embodiment is also possible, for example, as a replacement for a chip to package interposer substrate in a Ball Grid Array IC package.
Furthermore, in either variation, the exposed surface may comprise vias filled with metal. This surface may be suitably prepared for bonding with electrical interconnections described in the fourth embodiment using a combination of filler material to planarize the surface as described in the first embodiment and via revealing and contact structure formation as described in the tenth embodiment, if required. Additional die from the same or different wafers with exposed contact structures can then be bonded to the post-bond thinned surface with revealed metal filled vias as described in the fourth embodiment. Alternatively, under bump metallization may be formed in preparation for flip chip packaging can be implemented as described in earlier embodiments. This is illustrated in FIGS. 23M and 23N where a second die is bonded to the first die. Many combinations are possible in connecting the conductive material and/or contacts of one die to another die using the configurations described above and below. FIG. 23M shows three examples. where die 181 having its conductive material 168 connected using contact structure 179 to the conductive material 168 of the lower die, die 182 having contact 147(154) connected to contact 147 and conductive material 168 of the lower die, and die 183 having contact 147 and conductive material 168 connected to contact 147 and conductive material 168 of the lower die.
In FIG. 23N, the left-hand structure has two die bonded in the die-down configuration. The middle structure has a die with contact structure 147(154) bonded to a substrate 149, such as an interposer, having a contact structure 142. Contact structure 147 (154) and conductive material 168 are connected through conductive material 187 formed after bonding. The right-hand structure has conductive material 187 connecting conductive material 168 in substrate 149 and contact structure 154.
Alternatively, the process may include the depositing and polishing of contact structures, with or without a dielectric, to result in a bonding surface that is suitably planar with contact structures and comprised of substrate, for example, substrate 140 in FIG. 25F.
Further alternatively, if exposed conductive fill is above the bonding surface, contact structures may also be formed on conductive material 174 in a manner similar to that described in the fourth embodiment. This formation may include the deposition and polishing of contact structures and a dielectric, for example silicon oxide, to result in a bonding surface that is suitably planar and electrically insulating, with the exception of the contact structures 179. Contact structures 179 may be formed of a comparable, smaller, or larger lateral dimension than conductive material 174.
1. A method of integrating a first element having a first contact structure with a second element having a second contact structure, comprising:
forming said first and second contact structures from a metal selected from copper, tungsten, nickel, gold or alloys thereof;
forming said first and second contact structures to have an upper surface below respective surfaces of said first and second elements by no more than 20 nm;
forming a conductive pad connected to at least said first contact structure;
bonding a material in said first element to a material in said second element such that said first contact structure is directly connected to said second contact structure; and
heating said first and second elements at a temperature less than 400° C. to increase pressure between said first and second contact structures.
2. The method recited in claim 1, comprising:
heating at a temperature below 350° C.
3. The method recited in claim 1, comprising:
removing a native oxide from at least one of the first and second contact structures.
4. The method recited in claim 1, wherein said heating comprises forming a mechanical connection between the first and second contact structures.
5. The method recited in claim 1, comprising:
forming a palladium layer on at least one of said first and second contact structures.
6. The method recited in claim 1, comprising:
forming said first and second contact structures to have an upper surface below respective surfaces of said first and second elements by no more than 10 nm.
7. The method recited in claim 1, comprising:
forming said second contact structure to have a lateral area smaller than a lateral area of said first contact structure.
8. The method recited in claim 1, comprising:
forming said second contact structure having a first perimeter completely within a second perimeter of said first contact structure.
etching a surface of at least one of said first and second elements adjacent to said first and second contact structures, respectively.
10. The method recited in claim 1, comprising:
controlling a height of a surface of at least one of said first and second elements with respect to said first and second contact structures, respectively.
11. The method recited in claim 10, comprising:
controlling said height using chemo-mechanical polishing.
12. The method recited in claim 10, comprising:
controlling said height using etching of said surface.
13. The method recited in claim 10, comprising:
controlling said height using a metal layer formed on said contact structures.
14. The method recited in claim 1, comprising:
heating said first and second elements after bonding to thermally expand at least one of said first and second contact structures.
15. The method recited in claim 1, comprising:
thinning one of said first and second elements after said bonding; and
performing said heating after said thinning.
16. The method recited in claim 1, comprising:
preferentially heating said first and second contact structures with respect to said materials of said first and second elements.
17. The method recited in claim 1, wherein said 20 nm is an average distance over an extent of the first and second contact structures.
18. An integration method, comprising:
forming a first contact structure in a first element electrically connected to a conductive pad, said first element having a first substrate;
forming a second element having at least one second contact structure;
forming said first and second contact structures to have an upper surface below respective surfaces of said first substrate and second element by no more than 20 nm;
removing a portion of said first substrate;
bonding said first substrate to said second element after said removing; and
directly contacting said first contact structure with said second contact structure.
19. The method recited in claim 18, wherein said 20 nm is an average distance over an extent of the first and second contact structures.
20. The method recited in claim 18, comprising:
21. The method recited in claim 18, comprising:
22. The method recited in claim 18, comprising:
23. The method recited in claim 18, comprising:
24. The method recited in claim 18, comprising:
25. The method recited in claim 24, comprising:
26. The method recited in claim 24, comprising:
27. The method recited in claim 24, comprising:
28. The method recited in claim 18, comprising:
heating said first and second elements after said bonding to thermally expand at least one of said first and second contact structures.
29. The method recited in claim 18, comprising:
30. The method recited in claim 18, comprising:
31. The method recited in claim 18, comprising:
heating said first and second elements at a temperature to increase pressure between said first and second contact structures.
32. The method recited in claim 31, comprising:
heating said first and second elements at a temperature to reduce the resistance of contact between said first and second contact structures.
33. The method recited in claim 31, comprising:
heating at a temperature less than 400° C.
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Patent number: 9171756
Patent Publication Number: 20140187040
Inventors: Paul M. Enquist (Cary, NC), Gaius Gillman Fountain, Jr. (Youngsville, NC), Qin-Yi Tong (Durham, NC)
Application Number: 14/198,723
International Classification: H01L 21/4763 (20060101); H01L 21/768 (20060101); H01L 23/48 (20060101); H01L 23/00 (20060101); H01L 25/065 (20060101); H01L 25/00 (20060101);