Source: http://www.google.com/patents/US7770050?dq=6,128,731
Timestamp: 2015-03-05 08:49:37
Document Index: 206737072

Matched Legal Cases: ['application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60']

Patent US7770050 - Method and apparatus for resolving clock management issues in emulation ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsMethods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is interpreted to generate interpreted code instructions that emulate a first component on the host system. A second set of code...http://www.google.com/patents/US7770050?utm_source=gb-gplus-sharePatent US7770050 - Method and apparatus for resolving clock management issues in emulation involving both interpreted and translated codeAdvanced Patent SearchPublication numberUS7770050 B2Publication typeGrantApplication numberUS 11/696,699Publication dateAug 3, 2010Filing dateApr 4, 2007Priority dateMay 3, 2006Fee statusPaidAlso published asUS8234514, US20070277052, US20100281292Publication number11696699, 696699, US 7770050 B2, US 7770050B2, US-B2-7770050, US7770050 B2, US7770050B2InventorsStewart Sargaison, Victor Suba, Brian WatsonOriginal AssigneeSony Computer Entertainment Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (58), Non-Patent Citations (36), Referenced by (9), Classifications (6), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod and apparatus for resolving clock management issues in emulation involving both interpreted and translated code
US 7770050 B2Abstract
Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is interpreted to generate interpreted code instructions that emulate a first component on the host system. A second set of code instructions is translated to generate translated code instructions that emulate a second component of the target system on the host system. The interpreted instructions, are executed based on a first clock (which may be a fixed clock) and the translated instructions are executed based on a second clock (which may be a variable clock). The host system adjusts the first or second clock, execution of the translated or interpreted instructions or a memory access to maintain a desired synchronization between the translated instructions and the interpreted instructions.
This application claims the benefit of priority of U.S. provisional application No. 60/746,273, entitled METHOD AND APPARATUS FOR RESOLVING CLOCK MANAGEMENT ISSUES IN EMULATION INVOLVING BOTH INTERPRETED AND TRANSLATED CODE, filed May 3, 2006, the entire disclosures of which are incorporated herein by reference. This application claims the benefit of priority of U.S. provisional application No. 60/746,267, to Stewart Sargaison et al, entitled TRANSLATION BLOCK INVALIDATION PREHINTS IN EMULATION OF A TARGET SYSTEM ON A HOST SYSTEM, filed May 3, 2006, the entire disclosures of which are incorporated herein by reference. This application claims the benefit of priority of U.S. provisional application No. 60/746,268, to Stewart Sargaison et al, entitled REGISTER MAPPING IN EMULATION A TARGET SYSTEM ON A HOST SYSTEM, filed May 3, 2006, the entire disclosures of which are incorporated herein by reference. This application claims the benefit of priority of U.S. provisional application No. 60/797,762, to Victor Suba, entitled STALL PREDICTION THREAD MANAGEMENT, filed May 3, 2006, the entire disclosures of which are incorporated herein by reference. This application claims the benefit of priority of U.S. provisional application No. 60/797,435, to Stewart Sargaison et al, entitled DMA AND GRAPHICS INTERFACE EMULATION, filed May 3, 2006, the entire disclosures of which are incorporated herein by reference. This application also claims the benefit of priority of U.S. provisional application No. 60/797,761, to Stewart Sargaison et al, entitled CODE TRANSLATION AND PIPELINE OPTIMIZATION, filed May 3, 2006, the entire disclosures of which are incorporated herein by reference.
Embodiments of this invention relate to emulation of a target computer platform on a host computer platform and more particularly to clock management where certain components of the target platform are emulated by interpretation and other components are emulated by translation.
The process of emulating the functionality of a first computer platform (the �target system�) on a second computer platform (the �host system�) so that the host system can execute programs designed for the target system is known as �emulation.� Emulation has commonly been achieved by creating software that converts program instructions designed for the target platform (target code instructions) into the native-language of a host platform (host instructions), thus achieving compatibility. More recently, emulation has also been realized through the creation of �virtual machines,� in which the target platform's physical architecture�the design of the hardware itself�is replicated via a virtual model in software.
To overcome the above disadvantages, embodiments of the invention are directed to methods and systems for resolving clock management issues in emulation of a target system on a host system. A first set of code instructions of a target program is interpreted to generate interpreted code instructions that emulate a first component on the host system. A second set of code instructions is translated to generate translated code instructions that emulate a second component of the target system on the host system. The interpreted instructions are executed based on a first clock and the translated instructions are executed based on a second clock. The host system adjusts the first or second clock, execution of the translated or interpreted instructions or a memory access to maintain a desired synchronization between the translated instructions and the interpreted instructions.