Source: http://www.google.fr/patents/US6826633
Timestamp: 2013-05-19 12:34:03
Document Index: 205761372

Matched Legal Cases: ['ART1', 'ART2', 'ART1', 'ART2', 'ART1', 'ART2']

Brevet US6826633 - Microcomputer incorporating peripheral circuits - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Historique Web | Connexion Recherche avanc�e dans les brevets BrevetsA microcomputer including a plurality of peripheral circuits has a connecting circuit that permits the interconnection among those peripheral circuits to be controlled through execution of a program. This makes it possible to realize intelligent peripheral circuit functions, such as are associated rather...http://www.google.fr/patents/US6826633?utm_source=gb-gplus-shareBrevet US6826633 - Microcomputer incorporating peripheral circuits Num�ro de publicationUS6826633 B2Type de publicationOctroi Num�ro de demande10/021,020 Date de publication30 nov. 2004 Date de d�p�t19 d�c. 2001 Date de priorit�26 d�c. 2000Autre r�f�rence de publicationCN1199113CCN1362674AEP1220109A2EP1220109A3EP1220109B1US20020083220 InventeursTadahiro Ushiro Cessionnaire d'origineSharp Kabushiki Kaisha Classification aux �tats-Unis710/12710/316 Classification internationaleG06F15/78G06F15/76G06F13/12G06F15/00 Classification coop�rativeG06F15/7853 Classification europ�enneG06F 15/78P1ER�f�rencesCitations de brevets (16)Liens externesUSPTO Cession USPTO EspacenetMicrocomputer incorporating peripheral circuitsUS 6826633 B2 R�sum� A microcomputer including a plurality of peripheral circuits has a connecting circuit that permits the interconnection among those peripheral circuits to be controlled through execution of a program. This makes it possible to realize intelligent peripheral circuit functions, such as are associated rather with a special-purpose microcomputer than with a general-purpose microcomputer, without using special manufacturing techniques or processes or spending a long time as in the development of a special-purpose microcomputer.
A general-purpose microcomputer is so devised as to achieve intelligent functions through interlocked operation of a plurality of peripheral circuits. For example, there is known a function called �input capture,� which is realized through interlocked operation of a timer-counter and an I/O port.
If the cause is a rising edge in the external input signal EXT_IN (�Yes� in S801), the value in the register R is saved as the period (hereinafter the �low period�) for which the external input signal EXT_IN remains at a low level (S802). If not (�No� in S801), the value in the register R is saved as the period (hereinafter the �high period�) for which the external input signal EXT_IN remains at a high level (S803).
When an interrupt request has occurred due to the external input signal EXT_IN1, if the cause of the interrupt request is a rising edge in the external input signal EXT_IN1 (�Yes� in S901), the value in the corresponding register R1 is saved as the low period (S902). On the other hand, when an interrupt request has occurred due to the external input signal EXT_IN2, the value calculated by subtracting the low period saved in the register R1 from the value in the corresponding register R2 is saved as the high period (S1001).
SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer having intelligent peripheral circuit functions, such as are associated rather with a special-purpose microcomputer than with a general-purpose microcomputer, without using special manufacturing techniques or processes or spending a long time as in the development of a special-purpose microcomputer.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a microcomputer embodying the invention. In this figure, reference numeral 1 represents a CPU, reference numeral 2 represents an input register, reference numeral 3 represents an output register, reference numeral 4 represents a connecting circuit, reference numeral 5 represents a first timer, reference numeral 6 represents a second timer, reference numeral 7 represents a logic circuit, and reference numeral 8 represents a data bus.
The count value is decremented by one at a time in synchronism with a clock signal (not shown). Counting is started on the rising edge of the input to the terminal �Start,� and is stopped on the rising edge of the input to the terminal �Stop.� From the terminals OUT0 to OUT7 are output 8-bit signals representing the current count value. When an overflow occurs in the count value (i.e. when the count value becomes equal to 00(Hex)), the output from the terminal �Overflow� turns to a high level. In the present specification, (Hex) denotes a hexadecimal number.
On a rising edge in the input to the terminal �Reset,� resetting is performed. Specifically, the count value is set to be equal to the value represented by the 8-bit signals input to the terminals IN0 to IN7, and the output from the terminal �Overflow� is turned to a low level. Moreover, as long as the input to the terminal �Reset� remains at a high level, the input to the terminal �Start� is ignored (i.e. even when a rising edge appears in the input to the terminal �Start,� counting is not started).
The connecting circuit 4 is composed of selectors 401 to 412, shown in FIG. 7, and selectors 413 to 416, shown in FIG. 8. In each of the selectors 401 to 412, according to the states of the signals input to terminals S0, S1, and S2, one of terminals D0, D1, D2, D3, D4, and D5 is selected, and the signal input to the selected terminal is output from a terminal OUT. FIG. 9 shows the relationship between the states of the signals input to the terminals S0, S1, and S2 and the selected terminal. In this figure, �1� represents a high level, and �0� represents a low level.
Each of the selectors 401 to 412 receives, at its terminals D0, D1, D2, D3, and D5 respectively, the signal OVERFLOW1 output from the terminal �Overflow� of the first timer 5, the signal OVERFLOW2 output from the terminal �Overflow� of the second timer 6, the output signals OUT1 and OUT2 of the logic circuit 7, and an interrupt-causing external input signal EXT_IN/INT that is fed in from outside the microcomputer. Here, an interrupt-causing external input signal denotes a signal of which rising and trailing edges cause interrupt requests in the circuit to which it is fed.
The signal output from the terminal OUT of the selector 401 is used as a signal START1 that is input to the terminal �Start� of the first timer 5. The signal output from the terminal OUT of the selector 402 is used as a signal RESET1 that is input to the terminal �Reset� of the first timer 5. The signal output from the terminal OUT of the selector 403 is used as a signal STOP1 that is input to the terminal �Stop� of the first timer 5.
The signal output from the terminal OUT of the selector 404 is used as a signal START2 that is input to the terminal �Start� of the second timer 6. The signal output from the terminal OUT of the selector 405 is used as a signal RESET2 that is input to the terminal �Reset� of the second timer 6. The signal output from the terminal OUT of the selector 406 is used as a signal STOP2 that is input to the terminal �Stop� of the second timer 6.
A program uses 32-bit registers Reg0 to Reg31 (not shown) to achieve input from and output to the data bus 8. Specifically, the signal CPU_BUS0 on the data bus 8 turns to a high level when the bit in the register Reg0 is turned to �1,� and turns to a low level when the register Reg0 is turned to �0.� The value in the register Reg0 is �1� if evaluated when the signal CPU_BUS0 on the data bus 8 is at a high level, and is �0� if evaluated when the signal CPU_BUS0 on the data bus 8 is at a low level. The same relationship applies between the register Reg1 and the signal CPU_BUS1 on the data bus 8, between the register Reg2 and the signal CPU_BUS2 on the data bus 8, . . . , and between the register Reg31 and the signal CPU_BUS31 on the data bus 8.
As a result of the operations performed in S101 to S104, now the output signal OUT2 from the inverter 707 of the logic circuit 7, the output signal OUTREG17 from the terminal O17 of the output register 3, and the output signal OUT1 from the OR gate 706 of the logic circuit 7 are used respectively as the input signal START1 to the terminal �Start� of the first timer 5, the input signal RESET1 to the terminal �Reset,� and the input signal STOP1 to the terminal �Stop.�
Moreover, the output signal OUT1 from the OR gate 706 of the logic circuit 7, the output signal OUTREG20 from the terminal O20 of the output register 3, and the output signal OUT2 from the inverter 707 of the logic circuit 7 are used respectively as the input signal START2 to the terminal �Start� of the second timer 6, the input signal RESET2 to the terminal �Reset,� and the input signal STOP2 to the terminal �Stop.�
Next, the values of the registers Reg0 to Reg7 are all set at �1,� the values of the registers Reg8 to Reg15 are all set at �1,� the value of the register Reg17 is set at �1,� the value of the register Reg20 is set at �1,� the value of the register R23 is set at �0,� the value of the register R24 is set at �0,� the value of the register R25 is set at �0,� and the value of the register R26 is set at �1� (S107).
As a result of the operations performed in S107 and S108, now, in the first and second timers 5 and 6, the inputs to the terminals IN0 to IN7 are all at a high level, the input to the terminal �Reset� is at a high level. Moreover, in the logic circuit 7, the two inputs to the OR gate 701 other than the external input signal EXT_IN are at a low level, the input to the terminal R of the flip-flop 702 is at a high level, and the input to the inverter 703 and one of the inputs to the AND gate 705 are at a high level.
Thus, every time the external input signal EXT_IN/INT rises, the input to the terminal �Start� of the first timer 5 and the input to the terminal �Stop� of the second timer 6 rise. Moreover, every time the external input signal EXT_IN/INT falls, the input to the terminal �Stop� of the first timer 5 and the input to the terminal �Start� of the second timer 6 rise.
However, now, since the input to the terminal �Reset� of the first timer 5 and the input to the terminal �Reset� of the second timer 6 are at a high level, the first and second timers 5 and 6 are in a reset state, and thus do not perform counting.
FIG. 12 shows a flow chart of an example of the program for starting the measurement of the high and low periods of the external input signal EXT_IN/INT. First, the value in the register Reg17 is set at �0,� the value in the register Reg20 is set at �0,� the value in the register Reg23 is set at �0,� the value in the register Reg24 is set at �0,� the value in the register Reg25 is set at �0,� and the value in the register Reg26 is set at �1� (S201). Next, the address to which to make access is set in the output register 3. Specifically, write access is made to the address F0000004(Hex) (S202).
As a result of these operations, now, in the logic circuit 7, the two inputs to the OR gate 701 other than the external input signal EXT_IN are at a low level, the input to the terminal R of the flip-flop 702 is at a high level, and the input to the inverter 703 and one of the inputs to the AND gate 705 are at a high level. Moreover, the input to the terminals �Reset� of the first and second timers 5 and 6 are at a low level, and thus the first and second timers 5 and 6 recovers from the reset state.
If, in step S302, a rising edge is recognized (�Yes� in S302), the values in the registers Reg0 to Reg7 are saved in a RAM or the like used when a software procedure is executed (S303). Next, the values in the registers Reg0 to Reg7 are all set at �1,� the value in the register Reg17 is set at �1,� the value in the register Reg20 is set at �0,� the value in the register Reg23 is set at �1,� the value in the register Reg24 is set at �0,� the value in the register Reg25 is set at �0,� and the value in the register Reg26 is set at �1� (S304).
Next, the address to which to make access is set in the output register 3. Specifically, write access is made to the address F0000004(Hex) (S305). Next, the value in the register Reg17 is set at �0� (S306). Next, the address to which to make access is set in the output register 3 (S311).
By contrast, if, in S302, a rising edge is not recognized (�No� in S302), the values in the registers Rge8 to Reg15 are saved in a RAM or the like used when a software procedure is executed (S307). Next, the values in the registers Reg8 to Reg15 are all set at �1,� the value in the register Reg17 is set at �0,� the value in the register Reg20 is set at �1,� the value in the register Reg23 is set at �0,� the value in the register Reg24 is set at �0,� the value in the register Reg25 is set at �0,� and the value in the register Reg26 is set at �1� (S308).
Next, the address to which to make access is set in the output register 3. Specifically, write access is made to the address F0000004(Hex) (S309). Next, the value in the register Reg20 is set at �0� (S310). Next, the address to which to make access is set in the output register 3 (S311).
As a result of the operations performed in S401 to 404, now, the output signal OUT2 from the inverter 707 of the logic circuit 7 and the output signals OUTREG17 and OUTREG18 from the terminals O17 and O18 of the output register 3 are used respectively as the input signal START1 to the terminal �Start� of the first timer 5, the input signal RESET1 to the terminal �Reset,� and the input signal STOP1 to the terminal �Stop.�
Moreover, the output signal OVERFLOW1 from the terminal �Overflow� of the first timer 5, the output signal OUTREG20 from the terminal O20 of the output register 3, and the output signal OUTREG21 from the terminal O21 are used respectively as the input signal START2 to the terminal �Start� of the second timer 6, the input signal RESET2 to the terminal �Reset,� and the input signal STOP2 to the terminal �Stop.�
Moreover, the output signal OVERFLOW1 from the terminal �Overflow� of the first timer 5, the output signal OVERFLOW2 from the terminal �Overflow� of the second timer 6, the output signal OUTREG24 from the terminal O24 of the output register 3, the output signal OUTREG25 from the terminal O25, and the output signal OUTREG26 from the terminal O26 are used respectively as the input signals IN1, IN2, and IN3 to the OR gate 701 of the logic circuit 7, the input signal TRG to the inverter 703 and the AND gate 705, and the input signal D_RESET to the terminal R of the flip-flop 702. Moreover, the output signal OUT1 from the OR gate 706 of the logic circuit 7 is used as the external output signal EXT_OUT.
Next, the values in the registers Reg0 to Reg7 are set at 06(Hex), the values in the registers Reg8 to Reg15 are set at 02(Hex), the value in the register Reg17 is set at �1,� the value in register Reg18 is set at �0,� the value in register Reg20 is set at �1,� the value in register Reg21 is set at �0,� the value in register Reg24 is set at �0,� the value in register Reg25 is set at �1,� and the value in register Reg26 is set at �1� (S407).
As a result of the operations performed in S407 to S408, with the first and second timers 5 and 6 receiving, at their terminals IN0 to IN7, values 06(Hex) and 02(Hex) respectively, the inputs to their terminals �Reset� turn to a high level. Moreover, now, in the logic circuit 7, the three inputs to the OR gate 701 are all at a low level, the input to the terminal R of the flip-flop 702 is at a high level, and the input to the inverter 703 and one of the inputs to the AND gate 705 are at a high level. Thus, the first and second timers 5 and 6 are in a reset state, with their count values set at 06(Hex) and 02(Hex) respectively. Moreover, the external output signal EXT_OUT is kept at a high level.
FIG. 17 shows a flow chart of an example of the program for starting the output of pulses having predetermined high and low periods as the external output signal EXT_OUT. First, the value in the register Reg17 is set at �0,� the value in the register Reg18 is set at �0,� the value in the register Reg20 is set at �0,� the value in the register Reg21 is set at �0,� the value in the register Reg24 is set at �1,� the value in the register Reg25 is set at �1,� and the value in the register Reg26 is set at �0� (S501).
Next, the address to which to make access is set in the output register 3. Specifically, write access is made to the address F0000004(Hex) (S502). Next, the value in the register Reg24 is set at �0� (S503). Next, the address to which to make access is set in the output register 3 (S504).
As a result of these operations, the inputs to the terminals �Reset� of the first and second timers 5 and 6 are inverted to a low level, and thus the first and second timers 5 and 6 recover from the reset state. Moreover, in the logic circuit 7, one of the inputs to the OR gate 701 is inverted to a high level and then back to a low level, and in addition the input to the terminal R of the flip-flop 702 is inverted to a low level. Thus, the external output signal EXT_OUT is inverted to a low level. In addition, the input to the �Start� of the first timer 5 is inverted to a high level, and this makes the first timer 5 start counting with a count value 06(Hex).
Thereafter, when an overflow occurs in the count value of the first timer 5, the output from the terminal �Overflow� of the first timer 5 is inverted to a high level, and the input to the terminal �Start� of the second timer 6 and one of the inputs to the OR gate 701 of the logic circuit 7 are inverted to a high level. Thus, the second timer 6 starts counting with a count value 02(Hex). In addition, the external output signal EXT_OUT is inverted to a high level and the input to the terminal �Start� of the first timer 5 is inverted to a low level.
The overflow in the first timer 5 causes an interrupt request. On occurrence of this interrupt request, a program as shown in a flow chart in FIG. 18 is executed. First, the values in the registers Reg0 to Reg7 are set at 04(Hex), the value in the register Reg17 is set at �1,� the value in the register Reg18 is set at �0,� the value in the register Reg20 is set at �0,� the value in the register Reg21 is set at �0,� the value in the register Reg24 is set at �0,� the value in the register Reg25 is set at �1,� the value in the register Reg26 is set at �0� (S601).
Next, the address to which to make access is set in the output register 3. Specifically, write access is made to the address F0000004(Hex) (S602). Next, the value in the register Reg17 is set at �0� (S603). Next, the address to which to make access is set in the output register 3 (S604).
As a result of these operations, in the first timer 5, with the value input to the terminals IN0 to IN7 kept at 04(Hex), the input to the terminal �Reset� turns to a high level and then back to a low level. Thus, the first timer 5 is reset momentarily, so that its count value is set at 04(Hex). In addition, the output from the terminal �Overflow� of the first timer 5 is inverted to a low level, and this turns all the three inputs to the OR gate 701 of the logic circuit 7 to a low level.
Thereafter, when an overflow occurs in the count value of the second timer 6, the output from the terminal �Overflow� of the second timer 6 is inverted to a high level, and one of the inputs to the OR gate 701 of the logic circuit 7 is inverted to a high level. As a result, the external output signal EXT_OUT is inverted to a low level. In addition, the input to the terminal �Start� of the first timer 5 is inverted to a high level, and this makes the first timer 5 start counting with a count value 04 (Hex).
The overflow in the second timer 6 causes an interrupt request. On occurrence of this interrupt request, a program as shown in a flow chart in FIG. 19 is executed. First, the values in the registers Reg8 to Reg5 are set at 0A(Hex), the value in the register Reg17 is set at �0,� the value in the register Reg18 is set at �0,� the value in the register Reg20 is set at �1,� the value in the register Reg21 is set at �0,� the value in the register Reg24 is set at �0,� the value in the register Reg25 is set at �1,� the value in the register Reg26 is set at �0� (S701).
Next, the address to which to make access is set in the output register 3. Specifically, write access is made to the address F0000004(Hex) (S702). Next, the value in the register Reg20 is set at �0� (S703). Next, the address to which to make access is set in the output register 3 (S704).
As a result of these operations, in the second timer 6, with the value input to the terminals IN0 to IN7 kept at 0A(Hex), the input to the terminal �Reset� turns to a high level and then back to a low level. Thus, the second timer 6 is reset momentarily, so that its count value is set at 0A(Hex). In addition, the output from the terminal �Overflow� of the second timer 6 is inverted to a low level, and this turns all the three inputs to the OR gate 701 of the logic circuit 7 to a low level.
First, in the initial state where the program shown in FIG. 15 has just been executed, the external output signal EXT_OUT is kept at a high level. Moreover, the first and second timers 5 and 6 are in a reset state, with their count values set at 06(Hex) and 02(Hex) respectively. When the program shown in FIG. 17 is executed, as the letter �A� indicates in FIG. 20, the external output signal EXT_OUT is inverted to a low level, and the first timer 5 starts counting with a count value 06 (Hex).
A period of 1.5 [μs] thereafter, an overflow occurs in the first timer 5. Thus, the program shown in FIG. 18 is executed, and as a result, as the letter �B� indicates in FIG. 20, the external output signal EXT_OUT is inverted to a high level. Moreover, the second timer 6 starts counting with a count value 02(Hex). In addition, the first timer 5 is reset, and its count value is set at 04(Hex).
A period of 0.5 [μs] thereafter, an overflow occurs in the second timer 6. Thus, the program shown in FIG. 19 is executed, and as a result, as the letter �C� indicates in FIG. 20, the external output signal EXT_OUT is inverted to a low level. Moreover, the first timer 5 starts counting with a count value 04(Hex). In addition, the second timer 6 is reset, and its count value is set at 0A(Hex).
A period of 1.0 [μs] thereafter, an overflow occurs in the first timer 5. Thus, the program shown in FIG. 18 is executed, and as a result, as the letter �D� indicates in FIG. 20, the external output signal EXT_OUT is inverted to a high level. Moreover, the second timer 6 starts counting with a count value 0A(Hex). In addition, the first timer 5 is reset, and its count value is set at 04(Hex).
A period of 2.5 [μs] thereafter, an overflow occurs in the second timer 6. Thus, the program shown in FIG. 19 is executed, and as a result, as the letter �E� indicates in FIG. 20, the external output signal EXT_OUT is inverted to a low level. Moreover, the first timer 5 starts counting with a count value 04(Hex). In addition, the second timer 6 is reset, and its count value is set at 0A(Hex).
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