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Patent US5856215 - Method of fabricating a CMOS transistor - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsThe present invention relates to a method of fabricating a CMOS transistor which can further reduce the size of a chip since it is not necessary to consider the metal contact process margin since a gate electrode of a PMOS transistor and a gate electrode of an NMOS transistor are directly connected with...http://www.google.com/patents/US5856215?utm_source=gb-gplus-sharePatent US5856215 - Method of fabricating a CMOS transistorAdvanced Patent SearchPublication numberUS5856215 APublication typeGrantApplication numberUS 08/701,585Publication dateJan 5, 1999Filing dateAug 22, 1996Priority dateAug 25, 1995Fee statusLapsedAlso published asCN1058809C, CN1149763APublication number08701585, 701585, US 5856215 A, US 5856215A, US-A-5856215, US5856215 A, US5856215AInventorsChae Hyun JungOriginal AssigneeHyundai Electronics Industries Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (3), Classifications (13), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetMethod of fabricating a CMOS transistorUS 5856215 AAbstract The present invention relates to a method of fabricating a CMOS transistor which can further reduce the size of a chip since it is not necessary to consider the metal contact process margin since a gate electrode of a PMOS transistor and a gate electrode of an NMOS transistor are directly connected with a polysilicon wiring during a process of forming the gate electrodes, which can prevent the formation of a parasitic transistor by forming a cell space region in an active region below the polysilicon wiring.
What is claimed is: 1. A method of fabricating a CMOS transistor, comprising:forming an N-well in a portion of a P-substrate; defining field regions and active regions on said N-well and said P-substrate using an element separation process; forming a field oxide film in said field regions, respectively; forming a first N+ diffusion region between said active regions at an edge of said N-well; forming a common gate electrode on said P-substrate and said N-well; forming a first source and drain in said N-well having said common sate electrode as a first gate to form a PMOS transistor; forming a second source and drain in said P-substrate having said common gate electrode as a second gate to form an NMOS transistor; forming a second N+ diffusion region along said edge of said N-well, wherein said second N+ diffusion region is connected to said first N+ diffusion region at said edge of said N-well; forming an interlayer insulation film on the resulting structure after forming said second N+ diffusion region; and connecting, through a metal contact process, said first junction portion and said third junction portion with a first metal wiring, and second junction portion and said fourth junction portion with a second metal wiring. 2. The method as claimed in claim 1, wherein said common gate electrode of said PMOS transistor and NMOS transistor is formed to pass over said first N+ diffusion region.
3. The method as claimed in claim 1, further comprising an oxide film which is formed between said first N+ diffusion region and common gate electrode.
4. The method as claimed in claim 3, wherein said oxide film is formed during a process of forming a gate oxide film of said NMOS and PMOS transistors.
BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a method of fabricating a Complementary Metal Oxide Semiconductor(CMOS) and particularly to a method of fabricating a CMOS transistor which can prevent formation of a parasitic transistor between a PMOS transistor and an NMOS transistor, and also reduce the size of the chip.
BACKGROUND OF THE INVENTION In general, a CMOS transistor is fabricated by forming an N-well in a portion of a P-substrate, forming the PMOS transistor in the N-well, forming the NMOS transistor in the P-substrate, and interconnecting a gate electrode of the PMOS transistor and a gate electrode of the NMOS transistor. The gate electrode is generally formed from a polysilicon. In the operation of the CMOS transistor, a latch-up phenomenon occurs to lower the reliability of the transistor. To prevent the latch-up phenomenon, in the process of separation of elements to define a field region and an active region, a pick-up region is formed by making an edge portion of the N-well to be included in the active region and implanting N+ impurity ions into the active region of the edge portion of the N-well. In the case where the pick-up region is formed along the edge of the N-well, as described above, wiring for interconnecting the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor passes over the pick-up region. An insulation film is formed between the wiring and the pick-up region. In the case where the wiring is formed from the polysilicon which forms the gate electrode, there is a disadvantage in that the polysilicon wiring and the pick-up region which are formed have the insulation film between them act as a parasitic transistor, which can degrade the electrical performance of the CMOS transistor. A method for solving such a disadvantage is described below with reference to FIGS. 1, 2A and 2B.
FIG. 1 is a layout of a prior art CMOS transistor, FIG. 2A is a sectional view taken along a line X-X' of FIG. 1, and FIG. 2B is a sectional view taken along a line Y-Y' of FIG. 1.
Referring to FIGS. 1, 2A and 2B, N-well 11 is formed in a portion of P-substrate 1. After the field region and active region are defined by the element separation process, the filed oxide film 2 is formed in the field region through an oxidation process. The PMOS transistor 10 is formed in the N-well 11, and the NMOS transistor 20 is formed in the P-substrate 1. The PMOS transistor 10 comprises the first gate electrode 12 and a first and second junction parts 13A and 13B for source and drain. The NMOS transistor 20 comprises the second gate electrode 22 and a third and fourth junction parts 23A and 23B for source and drain. The first and second gate electrodes 12 and 22 are formed by a polysilicon depositing process and patterning process, respectively. The pick-up region 3 is formed along the edge of the N-well 11 through N+ impurity ion implantation process. After the pick-up region 3 is formed, an interlayer insulation film 4 is formed on the resulting structure. Thereafter, through a metal contact process, the first junction part 13A of the PMOS transistor 10 and the third junction part 23A of the NMOS transistor 20 are connected by a first metal wiring 5A, the second junction part 13B of the PMOS transistor 10 and the fourth junction part 23B of the NMOS transistor 20 are led out to other portions by a second metal wiring 5B, and the first gate electrode 12 of PMOS transistor 10 and the second gate electrode 22 of NMOS transistor 20 are connected by a third metal wiring 5C.
Since the first and second gate electrodes 12 and 22 are interconnected by utilizing a metal, the formation of the parasitic transistor in the portion of the pick-up region 3 can be prevented. The areas of the first gate electrode 12 and the second gate electrode 22 have to be large considering the contact margin, which limits the reduction of the size of the chip.
SUMMARY OF THE INVENTION Therefore, the object of the present invention is to provide a CMOS transistor which can prevent formation of a parasitic transistor between a PMOS transistor and an NMOS transistor, and also reduce the size of a chip.
A method of fabricating a CMOS transistor to achieve the above described object is characterized in that it comprises the steps of: defining a field region and active region in a P-substrate formed with an N-well through an element separation process; forming a field oxide film in the field region through an oxidation process; forming a cell space region in a selected portion of an edge of the N-well by a cell N+ impurity ion implantation process; forming a PMOS transistor having a common gate electrode, a first junction portion and a second junction portion in said N-well, and an NMOS transistor having the common gate, a third junction portion and a fourth junction portion; forming a pick-up region along the edge of the N-well by a N+ impurity ion implantation process; forming an interlayer insulation film on the entire top after forming the pick-up region; and connecting, through a metal contact process, the first junction portion and the third junction portion with a first metal wiring, and the second junction portion and the fourth junction portion with a second metal wiring.
FIG. 1 is a layout of a prior art CMOS transistor;
FIG. 2A is a sectional view taken along a line X-X' of FIG. 1;
FIG. 2B is a sectional view taken along a line Y-Y' of FIG. 1;
FIG. 3 is a layout of a prior art CMOS transistor;
FIG. 4A is a sectional view taken along a line X-X' of FIG. 3; and
FIG. 4B is a sectional view taken along a line Y-Y' of FIG. 3.
DETAILED DESCRIPTION OF THE INVENTION FIG. 1 is a layout of a prior art CMOS transistor, FIG. 2A is a sectional view taken along a line X-X' of FIG. 1, FIG. 2B is a sectional view taken along a line Y-Y' of FIG. 1, and these drawings are already discussed above.
Referring to FIGS. 3, 4A and 4B, N-well 11 is formed in a portion of P-substrate 1. After the field region and active region are fixed by the element separation process, the field oxide film 2 is formed in the field region through an oxidation process. A cell space region 100 is formed in a selected portion of the edge of N-well 11 by a cell N+ impurity ion implantation process. The PMOS transistor 10 is formed in N-well 11, and the NMOS transistor 20 is formed in the P-substrate 1. The PMOS transistor 10 comprises a common gate electrode 120 and the first and second junction parts 13A and 13B for source and drain. The NMOS transistor 20 comprises a common gate electrode 120 and the third and fourth junction parts 23A and 23B for source and drain. The common gate electrode 120 is formed through the polysilicon deposition process and patterning process so as to interconnect the PMOS transistor 10 and NMOS transistor 20 and pass over the cell space region 100. A thick oxide film 110 is formed between the cell space region 100 and the common gate electrode 120 which passes over the cell space region 100, and this thick oxide film 110 is formed during the process of forming the gate oxide film of the transistors 10 and 20. The pick-up region 3 is formed along the edge of the N-well 11 through the N+ impurity ion implantation process and is connected to the cell space region 100. After the pick-up region 3 is formed, the interlayer insulation film 4 is formed on the resulting structure. Thereafter, through a metal contact process, the first junction part of the PMOS transistor 10 and the third junction part 23A of the NMOS transistor 20 are connected by the first metal wiring 5A, and the second junction part 13B of the PMOS transistor 10 and the fourth junction part 23B of the NMOS transistor 20 are led out to other portions by a second metal wiring 5B.
Since the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor are directly connected with the polysilicon wiring during the process of forming the gate electrodes as described above, it is not necessary to consider the metal contact process margin so that the size of the chip can be further reduced, and since the cell space region is formed in the active region below the polysilicon wiring, the formation of the parasitic transistor can be prevented.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4782037 *Oct 30, 1986Nov 1, 1988Hatachi, LtdNonpeelingUS4853340 *Mar 31, 1988Aug 1, 1989Nec CorporationSemiconductor device isolated by a pair of field oxide regionsUS5338986 *May 18, 1993Aug 16, 1994Oki Electric Industry Co., Ltd.Latch-up resistant CMOS output circuitUS5464789 *Jul 23, 1993Nov 7, 1995Kabushiki Kaisha ToshibaMethod of manufacturing a CMOS semiconductor deviceUS5506161 *Oct 24, 1994Apr 9, 1996Motorola, Inc.Method of manufacturing graded channels underneath the gate electrode extensionsJPH0340463A * Title not availableJPH01289157A * Title not availableJPS5817655A * Title not availableJPS57107066A * Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6737709 *Dec 14, 1998May 18, 2004Sony CorporationSemiconductor deviceUS7009260 *Dec 8, 2003Mar 7, 2006Hynix Semiconductor Inc.Well structure in high voltage deviceUS7652525 *Feb 22, 2008Jan 26, 2010Seiko Instruments Inc.Current mirror circuit* Cited by examinerClassifications U.S. Classification438/199, 257/274, 257/E21.641, 438/297, 438/225, 257/E27.063International ClassificationH01L21/8238, H01L27/092, H01L29/739Cooperative ClassificationH01L21/823871, H01L27/0921European ClassificationH01L27/092B, H01L21/8238TLegal EventsDateCodeEventDescriptionFeb 22, 2011FPExpired due to failure to pay maintenance feeEffective date: 20110105Jan 5, 2011LAPSLapse for failure to pay maintenance feesAug 9, 2010REMIMaintenance fee reminder mailedJun 9, 2006FPAYFee paymentYear of fee payment: 8Jun 13, 2002FPAYFee paymentYear of fee payment: 4Aug 22, 1996ASAssignmentOwner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, RFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JUNG, CHAE HYUN;REEL/FRAME:008161/0087Effective date: 19960819RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google