Source: https://patents.google.com/patent/JP3678239B2/en
Timestamp: 2020-02-20 03:33:26
Document Index: 333315815

Matched Legal Cases: ['art 22', 'art 24', 'art 22', 'art 24', 'art 24', 'art 222', 'art 224', 'art 222', 'art, 24', 'art, 26', 'art, 28', 'art, 30', 'art, 52', 'art, 56', 'art, 58', 'art, 88', 'art, 90', 'art, 94', 'art, 96', 'art, 100', 'art, 130']

JP3678239B2 - Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus - Google Patents
JP3678239B2
JP3678239B2 JP2003187455A JP2003187455A JP3678239B2 JP 3678239 B2 JP3678239 B2 JP 3678239B2 JP 2003187455 A JP2003187455 A JP 2003187455A JP 2003187455 A JP2003187455 A JP 2003187455A JP 3678239 B2 JP3678239 B2 JP 3678239B2
JP2003187455A
JP2005026301A (en
康則 黒澤
2003-06-30 Application filed by セイコーエプソン株式会社 filed Critical セイコーエプソン株式会社
2003-06-30 Priority to JP2003187455A priority Critical patent/JP3678239B2/en
2005-01-27 Publication of JP2005026301A publication Critical patent/JP2005026301A/en
2005-08-03 Publication of JP3678239B2 publication Critical patent/JP3678239B2/en
Japanese Patent Laid-Open No. 11-8250
When a semiconductor device is mounted face-down on a substrate, it is important to relieve stress applied to external terminals such as solder. Conventionally, a structure in which an external terminal is formed on a stress relaxation layer (resin layer) has been applied, but a sufficient effect may not be obtained. In particular, a wafer level CSP (Chip Size / Scale Package) that performs packaging on a wafer basis has been expected to improve reliability.
An object of the present invention is to effectively relieve stress applied to a wiring layer or an external terminal in a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device.
(1The semiconductor device according to the present invention is an integrated circuit.And electrodes electrically connected to the integrated circuitA semiconductor substrate formed with,
A resin layer formed above the semiconductor substrate;
Formed on the resin layerLand partAnd a line portion extending from the electrode to the land portionA wiring layer having
Wiring layerAnd provided between the resin layerAn underlayer,
The land portion is the base layer.Overlap withA first part;While being spaced from the resin layerThe underlayer andDo not overlapA second portion. According to the present invention, the second portion of the land portion is,UnderlayerWithout overlapContactless. That is, no underlayer is formed immediately below the second portion of the land portion. Accordingly, the land portion can be deformed or moved following the external stress, and the stress can be effectively relieved.
(2In this semiconductor device,
The insulating layer may further include an opening that covers the line portion and exposes a part of the land portion.
(3In this semiconductor device,
The insulating layer may be embedded in an interval between the resin layer and the second portion of the land portion. According to this, when the insulating layer is softer than the base layer, the degree of freedom of the land portion is further improved, and the stress can be relaxed.
(4In this semiconductor device,
The width of the first portion of the land portion may be smaller than the width of the exposed portion of the land portion from the insulating layer. By doing so, the degree of freedom of the land portion is further improved with respect to the stress applied to the exposed portion of the land portion, and the stress can be effectively relaxed.
(5In this semiconductor device,
The insulating layer may further include an opening that covers the line portion and exposes the entire land portion.
(6In this semiconductor device,
The land portion may have the first portion at a central portion and the second portion at an end portion. According to this, the land portion can move while being inclined with the center of the planar shape as an axis, and the stress applied to the land portion can be relaxed.
(7In this semiconductor device,
The planar shape of the first portion of the land portion may be elongated in the direction in which the line portion extends. By doing so, for example, the land portion can be inclined and moved easily with the extension line of the line portion as an axis. Therefore, disconnection of the connection part of a line part and a land part can be prevented.
(8In this semiconductor device,
The foundation layer may be formed as a foundation only for the land portion.
(9In this semiconductor device,
The foundation layer may be formed as a foundation for the line portion and the land portion.
(10In this semiconductor device,
The thickness of the foundation layer may be larger than the thickness of the wiring layer. According to this, since the space immediately below the second portion of the land portion can be increased, the degree of freedom of the land portion is further improved.
(11In this semiconductor device,
An external terminal provided on the land portion may be further included. According to this, the freedom degree of an external terminal increases, the freedom degree of a land part and an external terminal improves more with respect to the stress applied to the base part of an external terminal, and can relieve | moderate a stress effectively.
(12The circuit board according to the present invention has the semiconductor device mounted thereon.
(13The electronic apparatus according to the present invention includes the semiconductor device.
(14) A method of manufacturing a semiconductor device according to the present invention includes: (a) forming a conductive layer on a semiconductor substrate on which an integrated circuit is formed;
(B) forming a wiring layer having a line portion and a land portion connected to the line portion so that at least the land portion is based on the conductive layer;
(C) overetching the conductive layer more than the area of the land portion to form a base layer;
The land portion is the base layer.Overlap withA first portion and the underlayerDo not overlapA second portion. According to the present invention, the second portion of the land portion is the base layer.Without overlappingMake contactless. That is, the base layer is not formed immediately below the second portion of the land portion. Accordingly, the land portion can be deformed or moved following the external stress, and the stress can be effectively relieved.
(15) A method of manufacturing a semiconductor device according to the present invention includes: (a) forming a base layer on a semiconductor substrate on which an integrated circuit is formed;
(B) avoiding the base layer and forming a planarizing layer in its peripheral region;
(C) A wiring layer having a line portion and a land portion connected thereto, wherein the land portion is the base layer.Overlap withA first portion and the underlayerDo not overlapForming a second portion;
including. According to the present invention, the second portion of the land portion is the base layer.Without overlappingMake contactless. That is, the base layer is not formed immediately below the second portion of the land portion. Accordingly, the land portion can be deformed or moved following the external stress, and the stress can be effectively relieved.
(16) In this semiconductor device manufacturing method,
The step (c) may further include removing the planarization layer.
1 to 9D are diagrams showing a semiconductor device and a manufacturing method thereof according to the first embodiment of the present invention. 1 is a plan view in which a part of the semiconductor device (such as the insulating layer 34 and the covering layer 38) is omitted, FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1, and FIG. It is III sectional view. FIG. 4 is a plan view of the wiring layer and the base layer.
The semiconductor device according to the present embodiment has a semiconductor substrate 10. The semiconductor substrate 10 may be a semiconductor chip as shown in FIG. 1 or a semiconductor wafer. As shown in FIG. 2, an integrated circuit 12 is formed on the semiconductor substrate 10, and a plurality of electrodes (for example, pads) 14 electrically connected to the integrated circuit 12 are formed. One integrated circuit 12 is formed on the semiconductor chip, and one group of a plurality of electrodes 14 is formed. A plurality of integrated circuits 12 are formed on the semiconductor wafer, and a plurality of groups of electrodes 14 are formed. As shown in FIG. 1, the plurality of electrodes 14 may be arranged along an end portion (for example, two or four sides facing each other) of a semiconductor chip (a region that becomes a semiconductor chip after a piece if it is a semiconductor wafer). Good. A passivation film (for example, SiN, SiO) is formed on the surface of the semiconductor substrate 10 (the surface on which the electrode 14 is formed).2, MgO) 16 is formed.
On the surface of the semiconductor substrate 10 on which the electrode 14 is formed (for example, on the passivation film 16), a resin layer 18 composed of at least one layer is formed. The resin layer 18 is formed avoiding the electrode 14. As shown in FIG. 1, the resin layer 18 may be formed in a range surrounded by the plurality of electrodes 14. The side surface of the resin layer 18 may be inclined such that the opposite surface (bottom surface) is larger than the top surface. The resin layer 18 may have a stress relaxation function. The resin layer 18 can be formed of a resin such as polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO).
The semiconductor device has a wiring layer 20. The wiring layer 20 is formed on the electrode 14 side in the semiconductor substrate 10. The wiring layer 20 is a conductive layer (for example, a copper (Cu) layer), and is formed of a single layer or a plurality of layers. The wiring layer 20 is electrically connected to the electrode 14. As shown in FIG. 2, the wiring layer 20 may overlap the electrode 14. The wiring layer 20 extends so as to reach the upper surface of the resin layer 18.
As illustrated in FIG. 1, the wiring layer 20 includes a line portion 22 and a land portion 24 connected to the line portion 22. The line part 22 and the land part 24 are integrally formed. The line portion 22 extends from the electrode 14 to the land portion 24. The line part 22 may extend linearly or may be bent. The land portion 24 is provided on the resin layer 18. The land part 24 is an electrical connection part. The land portion 24 may be provided with an external terminal 32. The width of the land portion 24 in the planar shape is larger than the width of the line portion 22 in the planar shape. The planar shape of the land portion 24 is often a circular shape, but is not limited thereto. The width of the planar shape of the connection portion between the line portion 22 and the land portion 24 may be larger than the width of the planar shape of the line portion 22.
As shown in FIG. 2, the semiconductor device includes a base layer 30 of the wiring layer 20. The foundation layer 30 is the foundation of the wiring layer 20. The underlayer 30 is formed immediately below a part of the land portion 24. The underlayer 30 may also be formed directly below all or part of the line portion 22 (for example, a region narrower than the line portion 22). The underlayer 30 may be a conductive layer, and is formed of a single layer or a plurality of layers. The underlayer 30 may include a barrier layer. The barrier layer prevents the wiring layer 20 or a seed layer described later from diffusing into the resin layer 18 or the like. The barrier layer can be formed of, for example, titanium (Ti), chromium (Cr), nickel (Ni), titanium tungsten (TiW), or the like. When the wiring layer 20 is formed by electroplating, the foundation layer 30 may include a seed layer. The seed layer is formed on the barrier layer. The seed layer is formed of the same material as the wiring layer 20 (for example, copper (Cu)). The thickness of the foundation layer 30 may be the same as or smaller than the thickness of the wiring layer 20.
The semiconductor device may have an external terminal 32. The external terminal 32 is electrically connected to the wiring layer 20. An external terminal 32 may be formed on the land portion 24. The external terminal 32 is a conductive metal (for example, an alloy) and is used for melting and achieving electrical connection (for example, solder). The external terminal 32 may be formed of either soft solder or hard solder. The external terminal 32 may have a spherical shape, for example, a solder ball.
An insulating layer (for example, solder resist) 34 is formed on the semiconductor substrate 10. The insulating layer 34 covers a part of the wiring layer 20. The wiring layer 20 may be entirely covered with the insulating layer 34 except for the portion where the external terminals 32 are provided. By doing so, oxidation, corrosion, and electrical failure of the wiring layer 20 can be prevented. The insulating layer 34 may be formed excluding a part of the land portion 24 (for example, the central portion). That is, the insulating layer 34 may have an opening 36 that exposes a part of the land portion 24 (for example, the central portion). The insulating layer 34 may cover the end portion of the land portion 24. As shown in FIG. 4, the planar shape of the opening 36 (planar shape of the exposed portion of the land portion 24) may be similar to the planar shape of the land portion 24 (for example, a circular shape). The external terminal 32 may be formed in the opening 36 (exposed portion of the land portion 24). The insulating layer 34 may cover the connection portion between the line portion 22 and the land portion 24. By doing so, disconnection of the connecting portion between the line portion 22 and the land portion 24 can be prevented.
A coating layer 38 may be provided on the insulating layer 34. The covering layer 38 has an insulating property, and may be formed of, for example, a resin. The covering layer 38 also covers the base portion (lower end portion) of the external terminal 32. The covering layer 38 has a portion formed on the insulating layer 34 and a portion that rises from this portion and covers the root portion of the external terminal 32. The covering layer 38 reinforces at least the root portion of the external terminal 32. After the semiconductor device is mounted on the circuit board, the stress applied to the external terminals 32 by the coating layer 38 can be relaxed.
As shown in FIG. 3, the land portion 24 includes a first portion 26 that is in contact with the base layer 30 and a second portion 28 that is not in contact with the base layer 30. That is, the first portion 26 overlaps the base layer 30, and the second portion 28 does not overlap the base layer 30. According to this, since the foundation layer 30 is not formed immediately below the second portion 28 of the land portion 24, the land portion 24 can be deformed or moved following the stress, and the stress can be effectively applied. Can be relaxed. The first portion 26 may be disposed at the center portion of the land portion 24, and the second portion 28 may be disposed at the end portion of the land portion 24. According to this, it becomes possible for the land portion 24 to move while being inclined with the center of the planar shape as an axis, and the stress applied to the land portion 24 can be relaxed. Moreover, when the external terminal 32 is provided in the land part 24, the freedom degree of the external terminal 32 increases and the stress added to the root part of the external terminal 32 can be reduced. As shown in FIG. 4, the second portion 28 may be disposed on the entire circumference of the first portion 26 except for the connection portion between the line portion 22 and the land portion 24. In that case, the second portion 28 may be arranged with a substantially constant width (except for the vicinity of the connection portion between the line portion 22 and the land portion 24) around the entire circumference of the first portion 26. When the land portion 24 is formed on the resin layer 18 via the base layer 30, the second portion 28 of the land portion 24 is disposed with a space from the resin layer 18. As shown in FIG. 3, an insulating layer 34 may be filled in the interval. According to this, when the insulating layer 34 is softer than the base layer 30, the degree of freedom of the land portion 24 is further improved and the stress can be relaxed.
As shown in FIG. 3 or FIG. 4, the width (for example, the maximum width) A of the first portion 26 and the width (for example, the maximum shape) of the exposed portion of the land portion 24 (the planar shape of the opening 36). Significantly) B
It is preferable to have the following relationship. By doing so, the underlayer 30 is disposed inside the contact portion between the land portion 24 and the external terminal 32, and the stress applied to the exposed portion of the land portion 24 (stress applied to the root portion of the external terminal 32). The degree of freedom of the land portion 24 and the external terminal 32 is further improved, and the stress can be effectively relieved. The planar shape of the first portion 26 may be similar to the planar shape of the land portion 24 (for example, a circular shape). The planar shape of the first portion 26 may be similar to the planar shape of the opening 36 (for example, a circular shape).
5 to 8 are views showing modifications of the semiconductor device according to the present embodiment, and are plan views of a wiring layer and a base layer. In the following modifications, the contents described in the above embodiment are omitted.
As shown in the modification of FIG. 5, the land portion 50 may have a square shape (for example, a square shape). In that case, the planar shape of the first portion 26 with which the base layer 30 contacts may be a similar shape (for example, a circular shape) to the planar shape of the opening 36.
As shown in the modification of FIG. 6, the base layer 52 may be formed as a base of only the land portion 24. The underlayer 52 may be formed only directly below a part of the land portion 24. In the present modification, the base layer 52 is not formed immediately below the line portion 22. The contents of the underlayer 30 can be applied to other configurations of the underlayer 52. In the example shown in FIG. 6, the second portion 28 is arranged on the entire circumference of the first portion 26.
As shown in FIGS. 7 and 8, the planar shape of the first portion 54 may be elongated in the direction in which the line portion 22 extends. For example, the planar shape of the first portion 54 may be an ellipse or a rectangle. By doing so, the lateral width (width in the width direction of the line portion 22) of the second portion 56 can be secured wider than the vertical width (width in the direction in which the line portion 22 extends), and the land portion 24 can be secured to the line portion. It becomes easy to move by inclining about the extension line of 22 as an axis. Therefore, disconnection of the wiring layer 20 (specifically, the connection portion between the line portion 22 and the land portion 24) can be prevented. As shown in FIG. 7, the foundation layer 58 may be formed directly below a part of the line portion 22. Alternatively, as shown in FIG. 8, the foundation layer 60 may be formed only directly below a part of the land portion 24.
The semiconductor device according to the present embodiment is configured as described above, and can effectively relieve the stress applied to the wiring layer 20 or the external terminal 32. The details of the effect are as described above.
Next, a method for manufacturing a semiconductor device according to the present embodiment will be described. As shown in FIG. 9A, an integrated circuit (see FIG. 2) is formed, and a conductive layer 62 is formed on the semiconductor substrate 10 on which the passivation film 16 is formed. The conductive layer 62 may be formed on the surface side of the semiconductor substrate 10 on which the electrode (see FIG. 2) is formed. The conductive layer 62 may be formed so as to be electrically connected to the electrode (for example, overlapped with the electrode). The resin layer 18 may be formed on the semiconductor substrate 10 (passivation film 16), and the conductive layer 62 may be formed on the entire region of the resin layer 18 and the other passivation film 16. The conductive layer 62 may be formed by sputtering, plating (electroplating or electroless plating), or a combination thereof. Alternatively, the conductive layer 62 may be formed by applying an inkjet method or a printing method. The conductive layer 62 becomes the base layer 30 of the wiring layer 20 (see FIG. 9D).
As shown in FIG. 9B, the wiring layer 20 is formed. The wiring layer 20 may be formed by applying a lithography technique. For example, the resist 64 may be patterned to have the opening 66, and the wiring layer 20 may be formed in the portion of the conductive layer 62 exposed in the opening 66. The wiring layer 20 may be formed by plating (for example, electroplating). The wiring layer 20 may be formed by electroplating using the conductive layer 62 as a power feeding layer. The wiring layer 20 is formed by patterning so as to have a line portion (see FIG. 2) and a land portion 24. Both the line portion and the land portion 24 (that is, the entire wiring layer 20) may be formed with the conductive layer 62 as a base. In the case of electroplating, the conductive layer 62 is disposed immediately below the entire land portion 24. When the resist 64 is formed, the resist 64 is then removed as shown in FIG. Thus, the wiring layer 20 can be formed on the conductive layer 62. In addition to the above, the wiring layer 20 may be formed by applying an inkjet method, a printing method, or the like. The wiring layer 20 is formed so that at least the land portion 24 has the conductive layer 62 as a base.
As shown in FIG. 9D, the conductive layer 62 is over-etched from the area of the land portion 24 to form the base layer 30. That is, the etching amount is controlled (for example, by time) so that the etchant enters inside the region of the land portion 24. The underlayer 30 may be formed by wet etching. As shown in FIG. 9D, a surfactant (eg, soap) is added to the etchant (eg, etchant) so that the etchant can easily enter the space between the land portion 24 and the resin layer 18 (or the passivation film 16). May be mixed. Thus, the land portion 24 having the first portion 26 that is in contact with the underlayer 30 and the second portion 28 that is not in contact with the underlayer 30 can be formed. As shown in FIG. 9D, the first portion 26 may be disposed at the center portion of the land portion 24, and the second portion 28 may be disposed at the end portion of the land portion 24. It should be noted that the portion of the conductive layer 62 that becomes the base of the line portion may be over-etched in the same manner, or may be just etched along the region of the line portion. Thereafter, the insulating layer 34, the external terminal 32, and the covering layer 38 may be formed as necessary (see FIG. 3).
You may perform the above-mentioned process with respect to the semiconductor substrate 10 as a semiconductor wafer. In that case, the semiconductor substrate 10 is cut | disconnected for every integrated circuit 12 after completion | finish of the above-mentioned process. In this way, it can be separated into a plurality of semiconductor devices having semiconductor chips. According to this, since packaging is performed in wafer units, productivity is high. In addition, regarding the other matters, the contents described above for the semiconductor device correspond to the method for manufacturing the semiconductor device according to the present embodiment.
FIGS. 10A to 11D are views showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIGS. 12A and 12B show the semiconductor device. It is a figure which shows the modification of this manufacturing method.
First, the base layer 30 is formed over the semiconductor substrate 10 (see FIG. 10C). For example, as shown in FIG. 10A, a conductive layer 70 is formed on the surface of the semiconductor substrate 10 on which the electrodes are formed, and a part of the conductive layer 70 is etched, for example, as shown in FIG. (For example, dry etching or wet etching). By applying a lithography technique, a part of the conductive layer 70 may be covered with the resist 72, and the remaining part of the conductive layer 70 may be removed. Thereafter, the resist 72 is removed, and the base layer 30 is formed as shown in FIG. As a method for forming the conductive layer 70, the content of the conductive layer 62 described in the first embodiment may be applied.
Next, as shown in FIG. 10D, a planarizing layer 74 is formed in the peripheral region avoiding the base layer 30. The peripheral region may be a region surrounding the base layer 30. The planarizing layer 74 may be adhered to the outer wall surface of the foundation layer 30. By forming the planarizing layer 74, the step between the base layer 30 and its peripheral region can be eliminated (or reduced), and the wiring layer 90 can be easily formed.
Next, the wiring layer 90 is formed (see FIG. 11D). First, as shown in FIG. 11A, a first conductive layer 76 is formed. The first conductive layer 76 is a power feeding layer for forming a second conductive layer 82 to be described later by electroplating, and the details of the conductive layer 62 described in the first embodiment are applied to the details. be able to.
As shown in FIG. 11B, a second conductive layer 82 is formed over the first conductive layer 76. For example, the resist 78 may be patterned so as to have the opening 80 by applying a lithography technique, and the second conductive layer 82 may be formed in the portion of the first conductive layer 76 exposed in the opening 80. . For the details of the second conductive layer 82, the contents of the wiring layer 20 described in the first embodiment can be applied.
Thereafter, as shown in FIG. 11C, the resist 78 is removed, and unnecessary portions of the first conductive layer 76 are removed by, for example, etching. The first conductive layer 76 may be patterned so as to have the same planar shape as that of the second conductive layer 82 patterned in the previous step.
Thus, as shown in FIG. 11D, a plurality of wiring layers 90 including the first and second conductive layers 82 and 84 can be formed. The wiring layer 90 has a line portion and a land portion 92 connected to the line portion. The land portion 92 includes a first portion 86 that is in contact with the foundation layer 30 and a second portion 88 that is not in contact with the foundation layer 30. As shown in FIG. 11D, the planarization layer 74 may be removed. In that case, a portion interposed between the second portion 88 and the resin layer 18 in the planarizing layer 74 may also be removed. Another material (for example, the insulating layer 34 (see FIG. 3)) may be formed in the interval between the second portion 88 and the resin layer 18. As a modification, the planarizing layer 74 may be left without being removed. The planarization layer 74 may be left at least in the interval between the second portion 88 and the resin layer 18. In that case, the planarization layer 74 is preferably formed of a material softer than the base layer 30. By doing so, the planarization layer 74 improves the degree of freedom of the land portion 92 or the external terminal provided thereon, and can relieve stress. The planarization layer 74 may be, for example, a resin (for example, the same material as the above-described resin layer 18), and preferably has a stress relaxation function.
12A and 12B, after the planarization layer 74 is formed in the peripheral region avoiding the base layer 30 (see FIG. 10D), the wiring layer 100 is formed. Form. In this modification, the wiring layer 100 is formed by performing electroless plating (for example, electroless copper plating). As shown in FIG. 12A, a mushroom-shaped wiring layer 100 may be formed without forming a resist (mask). Alternatively, a resist (mask) may be formed, and the wiring layer 100 having a straight wall shape in cross section may be formed along the inner wall of the opening of the resist. The wiring layer 100 includes a line portion and a land portion 102 connected to the line portion. The land portion 102 is not in contact with the first portion 94 that is in contact with the underlayer 30 and the underlayer 30. A second portion 96. As shown in FIG. 12B, the planarization layer 74 may be removed or may be left without being removed. The details described above can be applied to other details.
FIG. 13 is a diagram showing a semiconductor device according to the third embodiment of the present invention. In the present embodiment, a base layer 130 is formed instead of the base layer 30. The thickness of the foundation layer 130 is larger than the thickness of the wiring layer (for example, the land portion 24). The underlayer 130 may be formed by electroless plating (for example, electroless nickel plating). According to this, a thick layer can be easily formed as compared with the case of forming by sputtering. Alternatively, the base layer 130 may be formed thicker than the wiring layer by performing electroless plating on the thin film formed by sputtering. According to the present embodiment, since the space immediately below the second portion 28 of the land portion 24 (for example, the interval between the second portion 28 and the resin layer 18) can be increased, the land portion 24 or the external terminal 32 is provided. The degree of freedom can be further improved, and the stress can be effectively relieved. The details described above can be applied to other details.
FIG. 14 is a diagram showing a semiconductor device according to the fourth embodiment of the present invention. In the present embodiment, an insulating layer 134 is formed instead of the insulating layer 34. The insulating layer 134 is formed except for the entire land portion 24. That is, the insulating layer 134 has an opening 136 that exposes the entire land portion 24. The planar shape of the opening 136 may be similar to the planar shape of the land portion 24 (for example, a circular shape). The external terminal 32 may be provided inside the opening 136 and in contact with the entire land portion 24. Also in the present embodiment, since the base layer 30 is not formed immediately below the second portion 28 of the land portion 24, the stress can be effectively relieved. In the case where the coating layer 38 is provided, the coating layer 38 may be filled in the gap between the second portion 28 and the resin layer 18. The covering layer 38 may be formed of a material softer than the base layer 30. The details described above can be applied to other details.
15 and 16 are views showing a semiconductor device according to a fifth embodiment to which the present invention is applied. FIG. 15 is a partial enlarged view of the semiconductor device shown in FIG. The semiconductor device according to the present embodiment includes a semiconductor chip 200, a substrate 210 on which the semiconductor chip 200 is mounted, a wiring layer 220 formed on the substrate (for example, an interposer) 210, a base layer 230 of the wiring layer 220, including.
In the semiconductor chip 200, an integrated circuit 202 is formed, and a plurality of electrodes 204 electrically connected to the integrated circuit 202 are formed. The electrode 204 may include a pad and a bump thereon. The semiconductor chip 200 may be face-down bonded to the substrate 210 or may be face-up bonded. When face-down bonding is performed, an underfill material (in many cases, resin) 206 is filled between the semiconductor chip 200 and the substrate 210. The substrate 210 may have the wiring layer 220 formed on both sides thereof. In that case, the wiring layer 220 includes a through hole for conducting to each surface of the substrate 210. The semiconductor chip 200 is mounted, and the wiring layer 220 is electrically connected to the integrated circuit 202.
The wiring layer 220 includes a line part 222 and a land part 224 connected to the line part 222. The land portion 224 may be disposed on the surface of the substrate 210 opposite to the semiconductor chip 200. An external terminal 232 may be provided on the wiring layer 220 (for example, the land portion 224). The base layer 230 of the wiring layer 220 may be formed on the surface of the substrate 210. The base layer 230 may be formed by forming the conductive layer and the wiring layer 220 thereon on the substrate 210 and then overetching the conductive layer over the region of the land portion 224 (FIGS. 9A to 9). (See (D)). Alternatively, the base layer 230 is formed on the substrate 210, a planarization layer (not shown) is formed in the peripheral region avoiding the base layer 230, and the wiring layer 220 is formed on the base layer 230 and the planarization layer. It is also possible (see FIGS. 10A to 12B). The planarizing layer may be removed or left. In addition, an insulating layer 234 that covers a part of the wiring layer 220 may be formed on the substrate 210. In the example shown in FIG. 15, the insulating layer 234 has an opening 236 that exposes a part (for example, the center) of the land 224. The details described above can be applied to the wiring layer 220, the base layer 230, and the insulating layer 234.
As shown in FIG. 15, the land portion 224 includes a first portion 226 that is in contact with the base layer 230 and a second portion 228 that is not in contact with the base layer 230. Also in the present embodiment, since the base layer 230 is not formed immediately below the second portion 228 of the land portion 224, the land portion 224 can be deformed or moved following the stress. Can be effectively mitigated. For the other details, the contents described above (contents described in the first to fourth embodiments (including modifications)) can be applied.
FIG. 17 shows a circuit board 1000 on which the semiconductor device 1 according to the embodiment of the present invention is mounted. As an electronic apparatus having the semiconductor device according to the embodiment of the present invention, FIG. 18 shows a notebook personal computer 2000 and FIG. 19 shows a mobile phone 3000.
FIG. 2 is a cross-sectional view taken along the line II-II of FIG.
FIG. 4 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention.
FIG. 5 is a diagram illustrating a semiconductor device according to a variation of the first embodiment of the present invention.
FIG. 6 is a diagram for explaining a semiconductor device according to a modification of the first embodiment of the present invention.
FIG. 7 is a diagram for explaining a semiconductor device according to a modification of the first embodiment of the present invention.
FIG. 8 is a diagram illustrating a semiconductor device according to a variation of the first embodiment of the present invention.
FIG. 9A to FIG. 9D are views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
FIGS. 10A to 10D are views showing a method for manufacturing a semiconductor device according to the second embodiment of the invention. FIGS.
FIGS. 11A to 11D are views showing a method for manufacturing a semiconductor device according to the second embodiment of the invention. FIGS.
FIGS. 12A and 12B are views showing a method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention.
FIG. 13 is a diagram showing a semiconductor device according to a third embodiment of the present invention.
FIG. 15 is a diagram showing a semiconductor device according to a fifth embodiment of the present invention.
FIG. 16 is a diagram showing a semiconductor device according to a fifth embodiment of the present invention.
FIG. 17 is a diagram showing a circuit board according to an embodiment of the present invention.
FIG. 18 is a diagram showing an electronic apparatus according to an embodiment of the present invention.
FIG. 19 is a diagram showing an electronic apparatus according to an embodiment of the present invention.
DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 12 ... Integrated circuit, 14 ... Electrode, 18 ... Resin layer, 20 ... Wiring layer, 22 ... Line part, 24 ... Land part, 26 ... First part, 28 ... Second part, 30 ... Underlayer, 32 ... External terminal, 34 ... Insulating layer, 50 ... Land part, 52 ... Underlayer, 54 ... First part, 56 ... Second part, 58 ... Underlayer, 60 ... Underlayer, 70 ... Conductive Layer, 74 ... planarization layer, 76 ... first conductive layer, 82 ... second conductive layer, 86 ... first part, 88 ... second part, 90 ... wiring layer, 92 ... land part, 94 ... 1st part, 96 ... 2nd part, 100 ... wiring layer, 102 ... land part, 130 ... underlayer, 134 ... insulating layer, 136 ... opening, 200 ... semiconductor chip, 202 ... integrated circuit, 204 ... electrode 210 ... Substrate, 220 ... Wiring layer 222 ... line section, 224 ... land portion, 226 ... first portion, 228 ... second portion, 230 ... base layer, 232 ... external terminals, 234 ... insulating layer, 236 ... opening
A semiconductor substrate on which an integrated circuit and an electrode electrically connected to the integrated circuit are formed;
A wiring layer having a land portion formed on the resin layer and a line portion extending from the electrode to the land portion ;
An underlayer provided between the wiring layer and the resin layer ;
The land portion includes a first portion that overlaps the base layer, and a second portion that is spaced from the resin layer and does not overlap the base layer.
A semiconductor device further comprising an insulating layer that covers the line portion and has an opening that exposes a portion of the land portion.
A semiconductor device in which the insulating layer is buried in an interval between the resin layer and the second portion of the land portion.
The semiconductor device according to claim 2 or claim 3,
The width of the first portion of the land portion is a semiconductor device smaller than the width of the exposed portion of the land portion from the insulating layer.
A semiconductor device further comprising an insulating layer covering the line portion and having an opening exposing the entire land portion.
The land portion is a semiconductor device having the first portion at a central portion and the second portion at an end portion.
The planar shape of the first portion of the land portion is a semiconductor device formed to be elongated in the direction in which the line portion extends.
The base layer is a semiconductor device formed as a base only for the land portion.
The base layer is a semiconductor device formed as a base for the line portion and the land portion.
The thickness of the foundation layer is a semiconductor device larger than the thickness of the wiring layer.
A semiconductor device further comprising an external terminal provided on the land portion.
12. A circuit board on which the semiconductor device according to claim 1 is mounted.
The electronic device which has a semiconductor device in any one of Claims 1-11.
(A) forming a conductive layer on a semiconductor substrate on which an integrated circuit is formed;
(B) forming a wiring layer having a line part and a land part connected to the line part so that at least the land part is based on the conductive layer;
The land portion has a first portion overlapping said base layer, a method of manufacturing a semiconductor device having a second portion not the underlying layer overlap.
(A) forming a base layer on a semiconductor substrate on which an integrated circuit is formed;
(C) A wiring layer having a line portion and a land portion connected to the line portion includes a first portion where the land portion overlaps with the base layer, and a second portion which does not overlap with the base layer. Forming,
A method of manufacturing a semiconductor device, further comprising removing the planarization layer after the step (c).
JP2003187455A 2003-06-30 2003-06-30 Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus Active JP3678239B2 (en)
JP2003187455A JP3678239B2 (en) 2003-06-30 2003-06-30 Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
CNB2004100619573A CN100536101C (en) 2003-06-30 2004-06-29 Semiconductor device and method of manufacturing the same
US10/880,352 US7218008B2 (en) 2003-06-30 2004-06-29 Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US11/695,525 US7981792B2 (en) 2003-06-30 2007-04-02 Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
JP2005026301A JP2005026301A (en) 2005-01-27
JP3678239B2 true JP3678239B2 (en) 2005-08-03
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JP2003187455A Active JP3678239B2 (en) 2003-06-30 2003-06-30 Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
US (2) US7218008B2 (en)
JP (1) JP3678239B2 (en)
CN (1) CN100536101C (en)
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2003-06-30 JP JP2003187455A patent/JP3678239B2/en active Active
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US20050006765A1 (en) 2005-01-13
US7218008B2 (en) 2007-05-15
US20070170566A1 (en) 2007-07-26
CN100536101C (en) 2009-09-02
JP2005026301A (en) 2005-01-27
CN1577783A (en) 2005-02-09
US7981792B2 (en) 2011-07-19
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