Source: https://patents.justia.com/patent/9041214
Timestamp: 2020-08-14 06:30:03
Document Index: 20521894

Matched Legal Cases: ['Application No. 100121500', 'Application No. 1056122', 'Application No. 1056122', 'Application No. 201104206', 'Application No. 201104206', 'Application No. 10', 'Application No. 10', 'Application No. 201110201962']

US Patent for Bonded processed semiconductor structures and carriers Patent (Patent # 9,041,214 issued May 26, 2015) - Justia Patents Search
Justia Patents Via (interconnection Hole) ShapeUS Patent for Bonded processed semiconductor structures and carriers Patent (Patent # 9,041,214)
May 22, 2013 - SOITEC
METHOD FOR PRODUCING A LAYER
Methods of fabricating semiconductor structures including cavities filled with a sacrificial material
Advanced solid electrolyte and method of fabrication
Method for measuring thickness variations in a layer of a multilayer semiconductor structure
This application is a divisional of U.S. patent application Ser. No. 12/839,203, filed Jul. 19, 2010, now U.S. Pat. No. 8,461,017, issued Jun. 11, 2013, the disclosure of which is hereby incorporated herein by this reference in its entirety.
By way of example and not limitation, the process known in the industry as the SMARTCUT® process may be used to separate or detach the portion of the material 202′ from the transferred layer of material 202″. Such processes are described in detail in, for example, U.S. Pat. No. RE39,484 to Bruel; U.S. Pat. No. 5,374,564 to Bruel; U.S. Pat. No. 6,303,468 to Aspar et al.; U.S. Pat. No. 6,335,258 to Aspar et al.; U.S. Pat. No. 6,756,286 to Moriceau et al.; U.S. Pat. No. 6,809,044 to Aspar et al.; and U.S. Pat. No. 6,946,365 to Aspar et al., the disclosures of each of which are incorporated herein in their entirety by this reference.
Embodiment 1: A method of fabricating a semiconductor structure, comprising: forming a first semiconductor structure including at least a portion of an integrated circuit on a first substrate; implanting ions into a carrier wafer to form a weakened region within the carrier wafer; directly bonding the carrier wafer to a first side of the first semiconductor structure; processing the first semiconductor structure while the carrier wafer is attached to the first semiconductor structure using the carrier wafer to handle the first semiconductor structure; directly bonding a second semiconductor structure including at least a portion of an integrated circuit to a second side of the first semiconductor structure opposite the first side of the semiconductor structure to which the carrier wafer is directly bonded; and separating a layer of material from the carrier wafer from a remaining portion of the carrier wafer along the weakened region therein.
Embodiment 2: The method of Embodiment 1, further comprising forming at least one through wafer interconnect (TWI) extending at least partially through the first substrate.
Embodiment 3: The method of Embodiment 1 or Embodiment 2, wherein processing the first semiconductor structure comprises removing a portion of the first substrate from the second side of the first semiconductor structure and exposing at least one conductive structure of the at least a portion of the integrated circuit of the first semiconductor structure.
Embodiment 4: The method of Embodiment 3, wherein exposing at least one conductive structure of the at least a portion of the integrated circuit of the first semiconductor structure comprises exposing a through wafer interconnect (TWI) in the first semiconductor structure.
Embodiment 5: The method of Embodiment 4, wherein directly bonding the second semiconductor structure to the second side of the first semiconductor structure comprises directly bonding the through wafer interconnect of the first semiconductor structure to at least one conductive element of the second semiconductor structure.
Embodiment 6: The method of any one of Embodiments 1 through 5, wherein directly bonding the second semiconductor structure to the second side of the first semiconductor structure comprises directly bonding metal of at least one conductive element of the first semiconductor structure to metal of at least one conductive element of the second semiconductor structure.
Embodiment 7: The method of any one of Embodiments 1 through 6, wherein directly bonding the second semiconductor structure to the second side of the first semiconductor structure comprises directly bonding at least one of a semiconductor material and an oxide material of the second semiconductor structure to at least one of a semiconductor material and an oxide material of the first semiconductor structure.
Embodiment 8: The method of any one of Embodiments 1 through 7, wherein separating the layer of material of the carrier wafer from a remaining portion of the carrier wafer along the weakened region therein comprises annealing the carrier wafer at a temperature of at least 100° C. and detaching a portion of the carrier wafer overlying the weakened region from another portion of the carrier wafer remaining attached to the first semiconductor structure.
Embodiment 9: The method of any one of Embodiments 1 through 8, wherein separating the layer of material from the carrier wafer along the weakened region comprises leaving a layer of material of the carrier substrate having a thickness of between about 10 nm and about 1000 nm attached to the first semiconductor structure.
Embodiment 10: The method of any one of Embodiments 1 through 9, wherein the direct bonding of the second semiconductor structure to the second side of the first semiconductor structure results in the separating of the layer of material from the carrier wafer along the weakened region therein.
Embodiment 11: The method of Embodiment 10, wherein the direct bonding of the carrier wafer to the first side of the first semiconductor structure comprises weakening the carrier wafer along the weakened region therein without dividing the carrier wafer along the weakened region therein.
Embodiment 12: A method of fabricating a semiconductor structure, comprising: implanting ions into a first semiconductor structure and forming a weakened region therein; directly bonding a surface of the first semiconductor structure to a surface of a second semiconductor structure to form a bonded semiconductor structure including the first semiconductor structure and the second semiconductor structure; handling the bonded semiconductor structure using the first semiconductor structure while removing a portion of the second semiconductor structure and exposing at least one conductive structure extending at least partially through the second semiconductor structure; aligning the at least one conductive structure exposed through the second semiconductor structure with at least one conductive structure of a third semiconductor structure; heating the bonded semiconductor structure and the third semiconductor structure; directly bonding the at least one conductive structure exposed through the second semiconductor structure to the at least one conductive structure of the third semiconductor structure responsive to heating the bonded semiconductor structure and the third semiconductor structure; and dividing the first semiconductor structure along the weakened region responsive to heating the bonded semiconductor structure and the third semiconductor structure and leaving a portion of the first semiconductor structure on the second semiconductor structure.
Embodiment 13: The method of Embodiment 12, further comprising forming the at least one conductive structure exposed through the second semiconductor structure to comprise a through wafer interconnect (TWI).
Embodiment 14: The method of Embodiment 12 or Embodiment 13, wherein implanting ions into the first semiconductor structure comprises exposing a surface of the semiconductor wafer to the ions at a dose of between 1×1016 ions/cm2 and 2×1017 ions/cm2 and an energy of between 10 KeV and 150 KeV.
Embodiment 15: The method of any one of Embodiments 12 through 14, wherein implanting ions into the first semiconductor structure comprises implanting the ions into a carrier wafer and forming a weakened region within the carrier wafer at a depth of between about 10 nm and about 1000 nm from a flat major surface of the carrier wafer.
Embodiment 16: The method of any one of Embodiments 12 through 15, wherein directly bonding the surface of the first semiconductor structure to the surface of the second semiconductor structure to form the bonded semiconductor structure comprises bonding a surface of a silicon carrier wafer to a surface of a silicon or a silicon dioxide material of the second semiconductor structure.
Embodiment 17: The method of any one of Embodiments 12 through 16, wherein directly bonding the surface of the first semiconductor structure to the surface of the second semiconductor structure to form the bonded semiconductor structure comprises bonding a surface of a silicon dioxide material on a silicon carrier wafer to a surface of a silicon or a silicon dioxide material of the second semiconductor structure.
Embodiment 18: The method of any one of Embodiments 12 through 17, wherein aligning the at least one conductive structure exposed through the second semiconductor structure with at least one conductive structure of a third semiconductor structure comprises aligning at least one copper through wafer interconnect (TWI) exposed through the second semiconductor structure with at least one copper bond pad of the third semiconductor structure.
Embodiment 19: The method of Embodiment 18, wherein heating the bonded semiconductor structure and the third semiconductor structure comprises heating the bonded semiconductor structure and the third semiconductor structure to a temperature of between about 100° C. and about 400° C.
Embodiment 20: The method of any one of Embodiments 12 through 19, further comprising processing the portion of the first semiconductor structure on the second semiconductor structure after dividing the first semiconductor structure along the weakened region and forming at least one device structure on or in the portion of the first semiconductor structure on the second semiconductor structure.
Embodiment 21: The method of any one of Embodiments 12 through 19, further comprising removing the portion of the first semiconductor structure from the second semiconductor structure after dividing the first semiconductor structure along the weakened region.
Embodiment 22: A bonded semiconductor structure, comprising: a plurality of bonded processed semiconductor structures; and a carrier die or wafer bonded to at least one processed semiconductor structure of the plurality of bonded processed semiconductor structures, the carrier die or wafer having a weakened zone comprising a plurality of implanted ions therein at an average depth of between 10 nm and 1000 nm from a surface of the carrier die or wafer bonded to the at least one processed semiconductor structure of the plurality of bonded processed semiconductor structures.
Embodiment 23: The bonded semiconductor structure of Embodiment 22, wherein the plurality of bonded processed semiconductor structures are structurally and electrically coupled together at least partially by through wafer interconnects.
Embodiment 24: The bonded semiconductor structure of Embodiment 22 or 23, wherein the plurality of bonded processed semiconductor structures are directly bonded together without using an adhesive material therebetween.
Embodiment 25: The bonded semiconductor structure of any one of Embodiments 22 through 24, wherein the carrier die or wafer is directly bonded to the at least one processed semiconductor structure of the plurality of bonded processed semiconductor structures.
at least one bonded semiconductor structure including two or more processed semiconductor structures that are attached together; and
a temporary carrier die or wafer bonded to one processed semiconductor structure of the at least one bonded semiconductor structure, the temporary carrier die or wafer having a weakened zone comprising a plurality of implanted ions therein at an average depth of between 10 nm and 1000 nm from a surface of the temporary carrier die or wafer bonded to the one processed semiconductor structure of the at least one bonded semiconductor structure.
2. The semiconductor structure of claim 1, wherein the two or more processed semiconductor structures are structurally and electrically coupled together at least partially by through wafer interconnects.
3. The semiconductor structure of claim 1, wherein the two or more processed semiconductor structures are directly bonded together without using an adhesive material therebetween.
4. The semiconductor structure of claim 3, wherein the temporary carrier die or wafer is directly bonded to the at least one bonded semiconductor structure.
5. The semiconductor structure of claim 1, wherein the temporary carrier die or wafer is directly bonded to the at least one bonded semiconductor structure.
6. The semiconductor structure of claim 5, wherein at least one of the two or more processed semiconductor structures comprises a substrate and a device region on the substrate, the device region including a plurality of device structures.
7. The semiconductor structure of claim 6, wherein the substrate has a warp of less than about thirty micrometers (30 μm), a bow of less than about ten micrometers (10 μm), and a total thickness variation of less than about one micrometer (1 μm).
8. The semiconductor structure of claim 6, wherein the plurality of device structures includes a plurality of through wafer interconnects extending through the device region and at least partially through the substrate.
9. The semiconductor structure of claim 8, wherein at least one of the through wafer interconnects is exposed at a back surface of the substrate.
10. The semiconductor structure of claim 5, further comprising a bonding material between the temporary carrier die or wafer and the at least one bonded semiconductor structure.
11. The semiconductor structure of claim 10, wherein the bonding material comprises at least one of an oxide, a nitride, and an oxynitride.
12. The semiconductor structure of claim 11, wherein the temporary carrier die or wafer comprises a silicon die or wafer.
13. The semiconductor structure of claim 1, wherein the two or more processed semiconductor structures include a stack of processed semiconductor structures, each processed semiconductor structure comprising a die or wafer including at least a portion of an integrated circuit.
14. The semiconductor structure of claim 13, wherein the processed semiconductor structures of the stack are bonded together using metal-to-metal bonds between active conductive features of the processed semiconductor structures.
15. The semiconductor structure of claim 13, wherein the stack of processed semiconductor structures comprises at least one semiconductor die.
16. The semiconductor structure of claim 15, wherein the stack of processed semiconductor structures comprises at least one semiconductor wafer.
17. The semiconductor structure of claim 15, wherein the temporary carrier die or wafer is a temporary carrier die.
18. The semiconductor structure of claim 15, wherein the temporary carrier die or wafer is a temporary carrier wafer.
19. The semiconductor structure of claim 13, wherein the stack of processed semiconductor structures comprises at least one semiconductor wafer.
20. The semiconductor structure of claim 19, wherein the temporary carrier die or wafer is a temporary carrier wafer.
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Patent number: 9041214
Patent Publication Number: 20130256907
Current U.S. Class: Via (interconnection Hole) Shape (257/774); Stacked Arrangement (257/686); Configuration Or Pattern Of Bonds (257/786)
International Classification: H01L 23/52 (20060101); H01L 21/20 (20060101); H01L 21/683 (20060101); H01L 21/768 (20060101); H01L 23/538 (20060101); H01L 23/00 (20060101); H01L 25/00 (20060101);