Source: http://www.google.com/patents/US5497190?ie=ISO-8859-1&dq=6272333
Timestamp: 2014-07-24 08:33:01
Document Index: 85636709

Matched Legal Cases: ['art 5', 'art 6', 'art 7', 'art 7', 'art 5', 'art 7', 'art 6', 'art 7', 'art 7', 'art 2', 'art 3', 'art 3', 'art 1', 'art 3', 'art 2', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3']

Patent US5497190 - Digital to analog converter arithmetic circuit - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsIn a DAC-output circuit of a TV set, an output judging part lowers a multiplying factor of sub-data as user data come close to zero, to converge the output onto zero in accordance with the turning down of the user data....http://www.google.com/patents/US5497190?utm_source=gb-gplus-sharePatent US5497190 - Digital to analog converter arithmetic circuitAdvanced Patent SearchPublication numberUS5497190 APublication typeGrantApplication numberUS 08/271,300Publication dateMar 5, 1996Filing dateJul 6, 1994Priority dateJul 7, 1993Fee statusPaidAlso published asCN1044305C, CN1099534APublication number08271300, 271300, US 5497190 A, US 5497190A, US-A-5497190, US5497190 A, US5497190AInventorsMasahiko OkamuraOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (7), Classifications (7), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetDigital to analog converter arithmetic circuitUS 5497190 AAbstract In a DAC-output circuit of a TV set, an output judging part lowers a multiplying factor of sub-data as user data come close to zero, to converge the output onto zero in accordance with the turning down of the user data.
What is claimed is: 1. A DAC arithmetic circuit comprising:a user data part having adjustable user data; a sub-data part having sub-data for compensating for irregularities in characteristics of an IC; an output judging part which includes a sub-data correction part for modifying said sub-data to reduce a value thereof in response to a decrease in said user data when said user data is below a predetermined value, said output judging part issuing output data based on said sub-data and said user data; and an output circuit for receiving and issuing said output data. 2. A DAC arithmetic circuit in accordance with claim 1, whereinsaid user data are of at least one of volume, tone color density, hue, brightness, contrast and sharpness. 3. A DAC arithmetic circuit comprising:a user data part having at least one user adjustable data value; a sub-data part having a preset sub-data value; and an output judging part for adding the at least one user adjustable value and the sub-data value and providing an output therefrom, wherein the output judging part includes a sub-data correction part for modifying the output judging part output when the user adjustable data value exceeds a predetermined value. 4. The DAC arithmetic circuit of claim 3 wherein when the at least one user data adjustable value is substantially equal to zero, the sub-data correction part modifies the output judging part output to also be substantially equal to zero.
The present invention relates to a DAC (Digital-to-Analog Converter) output arithmetic circuit used in a TV set etc.
In recent years, there has been an insatiable need of providing an audio-visual apparatus with high convenience in its functions. The audio-visual apparatus has a user data part which is adjustable by the user. With the progress of digital processing technology, an output of the user data part was transmitted in the form of digital data via a serial communication line.
FIG. 4 is a block diagram showing a block configuration of the conventional DAC-output arithmetic circuit. In FIG. 4, information of a user data part 5 and information of a sub-data part 6 are input to an output judging part 7. An output circuit 8 issues an output in response to an output issued from the output judging part 7.
When each of several user's data such as volume, tone, color density, hue, brightness, contrast and sharpness is given to the user data part 5, this data is input to the output judging part 7. The sub-data part 6 has sub-data for compensating irregularities in characteristics of IC. These sub-data are also input to the output judging part 7. The output judging part 7 makes a sum of the user data and the sub-data, and a resultant output value is forwarded to an output circuit 8. The output circuit 8 transmits the output value via a serial communication line (not shown).
However, even when the user lowers the user data to the minimum value (zero), sometimes an output sum value is not zero because the sub-data for compensating the irregularity of IC has a specific value other than zero. For example, although the user wants to kill the sound, volume level can not be made zero. Also, although the user wants to turn the TV to be monochromic, the color remains dimly. Thus, in the conventional TV set, control of the picture does not follow the way the user want it to.
OBJECT AND SUMMARY OF THE INVENTION An object of the present invention is to offer a DAC-output arithmetic circuit which controls an output value just as the user demands.
In order to achieve the above-mentioned object, a DAC-output arithmetic circuit of the present invention comprises:
a user data part having user data adjustable by a user;
a sub-data part having sub-data for compensating irregularity in characteristic of IC;
an output judging part which adjusts the sub-data in response to values of the user data and issues output data based on the sub-data and the user data; and
an output circuit for receiving and issuing the output data.
According to the present invention, when the user of a TV set adjusts the user data close to zero, the output data of the DAC-output circuit converges on zero. When the user adjusts the user data zero, the output data of the DAC-output circuit is also zero. Therefore, adjustments of volume, tone, color density, hue, brightness, contrast and sharpness are executed exactly as the user wishes.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a part of inner circuits for a TV set including a DAC-output arithmetic circuit 10 of the present invention;
FIG. 2 is a block diagram showing a configuration of the DAC-output circuit of the present invention;
FIG. 3 is a flow chart showing Judging procedures of the DAC-output circuit of the present invention; and
FIG. 4 is a block diagram showing the conventional configuration of the DAC-output circuit.
FIG. 1 is a block diagram showing a part of inner circuits for a TV set. As shown in FIG. 1. TV signals are processed through a tuner circuit 11, a VIF circuit (Video Intermediate Frequency amplifier circuit) 12 and a video-chroma jungle circuit 13, and output video signals are displayed on a CRT 14. The video-chroma jungle circuit 13 receives control signals from a DAC-output arithmetic circuit 10 via a serial communication line 15 to thereby adjust the displaying condition for the CRT 14. The DAC-output arithmetic circuit 10 also controls audio signals of the TV signals.
FIG. 2 is a block diagram showing a block configuration of the DAC-output arithmetic circuit 10 shown in FIG. 1. In FIG. 2. information of a user data part i and information of a sub-data part 2 are input to an output judging part 3. An output circuit 4 issues an output in response to an output issued from the output judging part 3.
When each of several user's data such as volume, tone, color density, hue, brightness, contrast and sharpness is given to the user data part 1, this data is input to the output judging part 3. The sub-data part 2 has sub-data for compensating irregularity in characteristics of IC. This sub-data is also input to the output judging part 3. The output judging part 3 includes a sub-data correction part 3a which is provided to lower the sub-data with specific multiplying factors in compliance with a predetermined flow chart shown in FIG. 3. The output judging part 3 calculates a desirable output value based on the user data and the sub-data. Typically, the above-mentioned block circuit configuration is realized by a microcomputer and necessary memories.
In FIG. 3, when the user data (e.g., 64-bit value) is larger than 3, step advances up to a step 105 is executed through steps 101,102, 103 and 104. At the step 105, a temporary memory value defined as "WORK" is set equal to the sub-data. Next, at a step 110, the user data is added to the value "WORK", and a resultant output value is issued to the output circuit 4 (FIG. 2) from the output judging part 3 (FIG. 2).
When the user data is 3, a step advance from the step 101 to a step 106 is executed. At the step 106, the value "WORK" is set equal to a half of the sub-data. Next, at the step 110, the user data is added to the value "WORK", and a resultant output value is issued to the output circuit 4 (FIG. 2) from the output judging part 3 (FIG. 2).
When the user data is 2, a step advance from the step 102 to a step 107 is executed. At the step 107, the value "WORK" is set equal to a quarter of the sub-data. Next, at the step 110, the user data is added to the value "WORK", and a resultant output value is issued to the output circuit 4 (FIG. 2) from the output judging part 3 (FIG. 2).
When the user data is 1, a step advance from the step 103 to a step 108 is executed. At the step 108, the value "WORK" is set equal to a value of ((sub-data)/8). Next, at the step 110, the user data is added to the value "WORK", and a resultant output value is issued to the output circuit 4 (FIG. 2) from the output judging part 3 (FIG. 2).
When the user data is 0, a step advance from the step 104 to a step 109 is executed. At the step 109, the value "WORK" is set zero. Next, at the step 110, the user data is added to the value "WORK", and a resultant output value is issued to the output circuit 4 (FIG. 2) from the output judging part 3 (FIG. 2).
In FIG. 2, the output circuit 4 transmits the output value via the serial communication line 15 (FIG. 1).
Apart from the above-mentioned embodiment wherein the output value converges on zero by diminishing weights of the sub-data with multiplying factors of 1/2, 1/4 and 1/8, another embodiment may be such that the multiplying factors are, for example, 3/4, 2/4 and 1/4, respectively.
Also, though four-level (the user data are 3, 2, 1 and 0) data conversion is performed in the above-mentioned embodiment, five-level (the user data are 4, 3, 2, 1 and 0) or any other higher level can be applied.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4272837 *Apr 20, 1978Jun 9, 1981Kabushiki Kaisha Daini SeikoshaElectronic timepiece with rotation detectorUS4309627 *Mar 27, 1979Jan 5, 1982Kabushiki Kaisha Daini SeikoshaDetecting circuit for a power source voltageUS4658301 *Mar 17, 1986Apr 14, 1987Kyodo News ServicePhototelegraphic apparatus for transmitting images of film and dataUS4831458 *Apr 24, 1987May 16, 1989Kabushiki Kaisha ToshibaImage information scanner apparatus with adjustment state display functionJPH01138856A * Title not availableJPH04286492A * Title not availableJPS6195629A * Title not available* Cited by examinerClassifications U.S. Classification348/189, 348/673, 348/E05.096, 348/572International ClassificationH04N5/44Cooperative ClassificationH04N5/44European ClassificationH04N5/44Legal EventsDateCodeEventDescriptionAug 10, 2007FPAYFee paymentYear of fee payment: 12Aug 12, 2003FPAYFee paymentYear of fee payment: 8Aug 31, 1999FPAYFee paymentYear of fee payment: 4Jul 6, 1994ASAssignmentOwner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OKAMURA, MASAHIKO;REEL/FRAME:007073/0726Effective date: 19940624RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google