Source: http://www.google.com/patents/US4831325?dq=5343970
Timestamp: 2014-03-10 02:56:39
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Patent US4831325 - Capacitance measuring circuit - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA variable capacitor, which may be a humidity sensitive capacitor, and a fixed reference capacitor are connected at a node. The node is clamped at a reference potential during a first phase of a two phase measuring cycle as the variable capacitor is charged to a fixed voltage and the fixed capacitor...http://www.google.com/patents/US4831325?utm_source=gb-gplus-sharePatent US4831325 - Capacitance measuring circuitAdvanced Patent SearchPublication numberUS4831325 APublication typeGrantApplication numberUS 07/032,664Publication dateMay 16, 1989Filing dateApr 1, 1987Priority dateApr 1, 1987Fee statusPaidAlso published asCA1283168C, DE3886244D1, DE3886244T2, EP0285070A1, EP0285070B1Publication number032664, 07032664, US 4831325 A, US 4831325A, US-A-4831325, US4831325 A, US4831325AInventorsCharles W. Watson, Jr.Original AssigneeGeneral Signal CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (13), Non-Patent Citations (12), Referenced by (51), Classifications (11), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetCapacitance measuring circuitUS 4831325 AAbstract A variable capacitor, which may be a humidity sensitive capacitor, and a fixed reference capacitor are connected at a node. The node is clamped at a reference potential during a first phase of a two phase measuring cycle as the variable capacitor is charged to a fixed voltage and the fixed capacitor is charged to a feedback voltage. The node is unclamped during the second phase and the capacitors are connected in a series loop to allow a redistribution of the charge in the capacitors or force a reversal of that charge with a voltage source. The deviation of the node from its reference potential after charge redistribution occurs is used as input to a feedback circuit which integrates that deviation over a number of cycles until it provides a feedback voltage of magnitude sufficient to cause the node deviation to be reduced to zero. A second reference capacitor can be supplied to provide an offset. The capacitors are constructed by simultaneous deposition on a substrate of a first plate followed by a dielectric film and a second plate. The second plate of the variable capacitor is porous to admit water molecules and the second plate of the fixed capacitor is impervious to water. The simultaneous deposition provides similar characteristics for the capacitors.
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a simplified circuit which illustrates the operation of both the method and apparatus of this invention. In FIG. 1 a variable capacitor, C.sub.x, such as a capacitive sensor for measuring relative humidity, is connected in series with a fixed or reference capacitor, C.sub.r, at a node 10. In a first phase of a measuring cycle having two non-overlapping phases, the switches 1 and 2 are closed, as shown, so that the fixed voltage source 3 provides a voltage V.sub.t across C.sub.x and the variable voltage source 4 provides a voltage V.sub.o across the capacitor C.sub.r. In the second phase of the measuring cycle the capacitors C.sub.x and C.sub.r are connected in series with a fixed sampling voltage, as supplied by source 5, by the making of the switch 6 and the disconnection of the switches 1 and 2. The charges in the capacitors are allowed to redistribute themselves, and then the high impedance detector 7 detects or measures the difference between the existing potential at the junction between the capacitors and a predetermined balance value for that potential. In FIG. 1 that difference is detected or measured by looking at the difference between the potential at the node 10 and at a reference point 8, the balance value. If the deviation or difference is not zero then the variable voltage source 4 is modified. In the circuit shown, the modification would be in a direction corresponding with the deviation detected. In other words, if the potential difference between node 10 and reference point 8 is negative the voltage V.sub.o is decreased. The reference point 8 may be at any of a number of potentials; for example, circuit common potential, which allows elimination of the resistors R.sub.1 and R.sub.2, or a potential representing half of the drop across the source 5, in which case the resistors will be of equal value.
The value of the voltage V.sub.o will be found to be proportional to the changing value of the capacitance of capacitor C.sub.x if the deviation of the difference detected by 7 from the predetermined balance value is kept at zero. This results from the fact that, as the capacitance of C.sub.x changes with a resulting change in the charge it carries after its charging in the first phase, the charging voltage on C.sub.r is changed to similarly change the charge it carries. Then, the redistribution of charges which occurs during the second phase will provide a changed balance between the resulting voltages across the two capacitors such that there will be a reduction of the deviation detected by the detector. After a number of iterations in the proper sense the deviation will reach zero and V.sub.o will be a measure of the capacitance of C.sub.x.
Proper operation of the circuit of FIG. 1 does not require that the sampling voltage be a certain polarity of magnitude-indeed the magnitude may be zero-or that the output voltage V.sub.o be a certain polarity. The reversal of the polarity of the sampling voltage wil only invert the relationship of V.sub.o and the variable capacitance being measured, whereas the polarity of V.sub.o will generally be a function of other parameters.
In FIG. 2, there is shown in more detail a circuit which follows the principles of operation illustrated by FIG. 1. In FIG. 2, the reference point 8 of FIG. 1 is circuit common potential and the detector 7 is comprised of cascaded logic inverters and an integrating amplifier with its associated switches. The predetermined potential difference across the reference capacitor to be detected by the detector 7 as an indication of balance is the trigger voltage of the inverters as established by the shorting of their inputs and outputs. That trigger voltage is also the voltage to which C.sub.x is charged, namely V.sub.t. in FIG. 2, the variable capacitor C.sub.x, which may be a capacitive humidity sensor, is connected in a network with reference capacitor C.sub.r and an additional reference capacitor C.sub.o by connecting one terminal of each to the node 10. The other terminals of these capacitors are selectively connected by way of switching elements 11-16 to either the output voltage, V.sub.o, or to a predetermined sampling voltage, V.sub.s, or to circuit common. For the purpose of this circuit the switching elements 11- 15 are MOS transistor switches and switch 16 is a CMOS switch. In addition to the capacitors mentioned, there will, of course, be a stray capacitance, which is represented in FIG. 1 by C.sub.y. As will be demonstrated later, the stray capacitance will only have a second order effect.
In the operation of this circuit the switches 11, 13, and 16 are closed, and the remainder of the switches are open during the first, setup phase, φ.sub.1, of a two phase clock which is used to time the two phases of the measuring cycle. This clock, which is shown in FIG. 5 and described subsequently, provides two non-overlapping clock signals of both polarities, P.sub.1 and P.sub.1 -, during the first phase; and P.sub.2 and P.sub.2 -during the second, or sampling phase, φ.sub.2. During the second, sampling phase the switches 12, 14 and 15 are closed and switches 11, 13, and 16 are open.
As shown in FIG. 2, the node 10 is connected to the input circuit of a logic inverter, which is in turn connected through capacitor 22 to another logic inverter 24. The output of inverter 24 is then connected through still another logic inverter and through CMOS switch 28 to terminal 29, which connects through capacitor 30 to circuit common. The terminal 29 is, as shown, connected through CMOS switch 32 to the inverting input of an operational amplifier 34. That amplifier has the capacitor 36 in its negative feedback circuit so as to form an integrating amplifying circuit. Also, as shown, the non-invertinng input to amplifier 34 is connected to a voltage V.sub.a, and the output of the amplifier is an output voltage V.sub.o, which is fed back to one side of switch 16 and is also provided to any indicating or recording circuits which may be utilized to obtain a readout of the measured capacitance value of C.sub.x.
The switches 28 and 32 are driven by the clock signals so that 32 is closed and 28 is open during the setup phase, when the charge on capacitor 30 is effective to cause the output of amplifier 34 to change and hence the charge on capacitor 36 to change until the potential at the inverting input of the amplifier is equal to the potential at the non-inverting input, V.sub.a. This provides an output V.sub.o which is the integral of the voltages to which the capacitor 30 is charged during consecutive sampling phases. During the sampling phase, the switches 28 and 32 are reversed and the capacitor 30 is charged from the output of the logic inverters in proportion to the change in potential at node 10 which occurs upon switching from the setup phase to the sampling phase.
It will be evident that the timing of the clock and the parameters of the capacitors C.sub.x, C.sub.o and C.sub.r must be such that the capacitors are allowed to obtain their full charge as appropriate for the voltages applied to them during each phase. Thus, the transients caused by the switching of the connections are allowed to settle out before the circuit is again switched.
FIG. 3 shows a circuit which can be used for the logic inverter 20. In that circuit the CMOS amplifiers 40 and 42 provide the amplification and the logic inversion while the CMOS switches 44 and 46 provide the shorting of the amplifier's input and output as is required during the setup phase of the measuring cycle in order to keep the node 10 at a fixed potential. In this case that fixed potential will be the threshold potential of the logic inverters, known as the trigger voltage, V.sub.t, which during the first phase is V.sub.t1. The switches 44 and 46 are closed to short the input and output of the inverter during the setup phase and are open during the sampling phase of the measuring cycle so that the node 10 is clamped at the threshold potential, V.sub.t1, during the setup phase and potential at the node 10, V.sub.t2, is allowed to float during the sampling phase.
It is, of course, evident that the logic inverter 20 will not draw any significant current during the sampling phase, but will supply any necessary current to charge the capacitors during the setup phase to hold node 10 at V.sub.t1. The other logic inverters 22 and 24 can be constructed as shown for inverter 20 in FIG. 3. The inverters 22-24 will also have their inputs tied to their outputs during the setup phase; and capacitors, such as capacitor 22, can be provided between inverters for accomodating any differences between their individual threshold voltages. In FIG. 2 only the interstage capacitor 22 is shown, for it is not always necessary to incorporate such capacitance between the remaining stages. As is characteristic of logic inverters of the type described, the output of these units will go low when the input deviates from the threshold voltage in a positive direction and will go high when the deviation is in the opposite direction. This characteristic is illustrated in inverter transfer characteristic shown in FIG. 4 which shows V.sub.o vs. V.sub.in. It will be noted that any small change of the input from the trigger voltage, V.sub.t, will cause a considerable change in the output. The slope of the steep portion of the characteristic will be dependent on the particular way in which the element is manufactured.
FIG. 5 shows a clock circuit which can be used to time the two phases of the measuring cycle. In this circuit a non-overlapping clock module 50 is driven by D-flop 52 whose input is from the multivibrator 53. As shown, the output of the clock module is the plus and minus potentials of φ.sub.1, P.sub.1 and P.sub.1 -, and the plus and minus potentials of φ.sub.2, P.sub.2 and P.sub.2 -.
The operation of the measuring circuit of FIG. 2 may be considered by examining the charges on the capacitors C.sub.x, C.sub.o and C.sub.r during the two phases φ.sub.1 and φ.sub.2.
During φ.sub.1 the voltage on node 10 is held at the trigger voltage, V.sub.t1, and during φ.sub.2 the voltage on node 10 is allowed to float at voltage V.sub.t2, as determined by the charges on the capacitors in the network. The charges on the capacitors are as follows:
______________________________________for &#966;.sub.1       for &#966;.sub.2______________________________________Q.sub.x1 = C.sub.x (-V.sub.t1)                 Q.sub.x2 = C.sub.x (V.sub.s - V.sub.t2)Q.sub.o1 = C.sub.o (V.sub.s - V.sub.t1)                 Q.sub.o2 = C.sub.o (-V.sub.t2)Q.sub.r1 = C.sub.r (V.sub.o - V.sub.t1)                 Q.sub.r2 = C.sub.r (-V.sub.t2)Q.sub.y1 = C.sub.y (-V.sub.t1)                 Q.sub.y2 = C.sub.y (-V.sub.t2).If &#916;Q = Q.sub.1 - Q.sub.2 and &#916;V.sub.t = V.sub.t2 - V.sub.t1,then &#916;Q.sub.x = C.sub.x (-V.sub.s + &#916;V.sub.t),&#916;Q.sub.o = C.sub.o (V.sub.s + &#916;V.sub.t),&#916;Q.sub.r = C.sub.r (V.sub.o + &#916;V.sub.t),and &#916;Q.sub.y =  C.sub.y (&#916;V.sub.t).______________________________________
&#916;Q.sub.x +&#916;Q.sub.o +&#916;Q.sub.r +&#916;Q.sub.y =0;
&#931;C=C.sub.x +C.sub.o +C.sub.r +C.sub.y,
C.sub.x (-V.sub.s +&#916;V.sub.t)+C.sub.o (V.sub.s +&#916;V.sub.t)+C.sub.r (V.sub.o +&#916;V.sub.t)+C.sub.y (&#916;V.sub.t)=0,
V.sub.s (C.sub.o -C.sub.x)+C.sub.r V.sub.o +&#931;C&#916;V.sub.t =0.
Since ΔV.sub.t =0 is the network condition defined as balance, and V.sub.o is a measure of C.sub.x ; ##EQU1##
Thus, it can be seen that the output voltage is a function of the variable capacitance C.sub.x plus a constant offset determined by the capacitance of C.sub.o.
It will be evident to those skilled in the art that the capacitor C.sub.o and its associated switching elements can be omitted if it is not desired to offset the relationship between the output voltage and the indicated value of C.sub.x.
It is also evident that the value of the stray capacitance C.sub.y does not affect the accuracy of the resulting measure of the variable capacitor since it does not appear as a term in the final relationship between C.sub.x and V.sub.o, as derived above. The stray capacitance, C.sub.y, does, however, affect the sensitivity.
The voltage V.sub.a on the non-inverting input of the amplifier 34 should be approximately equal to V.sub.s /2. If V.sub.a is not exactly equal to V.sub.s /2 the effect is only to introduce a small asymmetry in step size for raise steps as compared with lower steps in the integrator output V.sub.o.
As has been stated, where the variable capacitor is a capacitive humidity sensor, it is desirable to have all capacitors in the measuring network on the same substrate and to construct them with the same plate area and the same dielectic constant. The area of the plates can be carefully controlled by photolithography, but the thickness of the dielectric and hence the dielectric constant is not as easily controlled. It can, however, be matched to better than 0.1% by known techniques which use the same substance for all capacitors in the network. Care must be exercised in completely sealing the capacitors C.sub.o and C.sub.r from humidity, but C.sub.x must allow moisture to quickly penetrate the dielectric in order to obtain fast response to humidity changes.
The capacitor C.sub.x may be constructed as shown in FIG. 6 using well known integrated circuit techniques. In this structure the n-type silicon has a p+diffused region forming one plate of the capacitor. That plate is covered by the polyimide dielectric which is bounded by a field oxide. Over the dielectric is deposited an aluminum foil as the second plate of the capacitor. This foil is sufficiently thin so that it allows the water molecules to permeate the dielectric from the surrounding atmosphere after it has permeated the protective coating of polyimide covering the foil.
The capacitors C.sub.o and C.sub.r can be constructed as shown in FIG. 7, in which the second electrode is constructed of a thick aluminum plate instead of a thin foil as in FIG. 6. The thick plate is designed to prevent the water molecules from permeating to the dielectric of these capacitors, for they must not be sensitive to changes in the relative humidity of the surrounding atmosphere. The polyimide protective coating shown in FIG. 6 can be omitted since it is not necessary to protect the top plate from contaminents.
In applications where it is not possible to protect the capacitors C.sub.o and C.sub.r from the changes in humidity of the surrounding atmosphere, it is desirable to construct these capacitors differently so that they will not have a dielectric which changes its dielectric constant with changes in the humidity of the surroundings. For this type of service the capacitors C.sub.o and C.sub.r can be constructed as shown in FIG. 8 In that arrangement, it has been found useful to use SiO.sub.2 as the dielectric. That material is not humidity sensitive so there is no need to seal the capacitors from water vapor. Using a different dielectric as compared to that use for C.sub.x will, of course, cause the capacitors C.sub.o and C.sub.r to fail to track C.sub.x with changes in temperature and humidity. More importantly, it will cause the circuits to have different span and range magnitudes due to the fact that the capacitor C.sub.x is not being produced at the same time and by the same process as C.sub.o and C.sub.r and therefore can not be expected to have exactly the same characteristics.
By way of example, C.sub.x can have a value of 8-10 pf, C.sub.o can have a value of 7 pf, and C.sub.r can have a value of 3 pf. The voltage V.sub.a can be 2.5 volts and V.sub.t will normally be approximately 2.5 volts. V.sub.s can be in the area of 5-6 volts. Clock frequencies on the order of 8 Khz have been used so that the capacitors will be allowed to charge completely during each phase of the measuring cycle. Capacitor 22 can be 20 pf and capacitor 30 can be 0.3 pf with capacitor 36 having a value of 200 pf. The voltage V.sub.o will vary in a range between 1-5 volts which provides a desirable voltage range for use in measuring systems.
This unit provides a digital readout of 2000 counts. In order to provide for a scale factor other than unity, circuitry is required to determine the reference voltage for the A/D converter to accomodate the scale factor. Also, it is necessary to accomodate the offset at the zero humidity point by introducing an appropriate voltage at the low input terminal, IN LO, of the 7126. The circuit of FIG. 9 is arranged to provide these accomodations and to provide them in such a way that there is no necessity for making more than one potentiometer adjustment when one is using capacitors C.sub.o and C.sub.r of the type shown in FIG. 8. This simplifies the manufacture of the circuit of FIG. 9 considerably, for it is only necessary to adjust the circuit at one value of relative humidity instead of two in calibrating the units so that they will be interchangeable. Separate adjustments at different humidities would normally be required for offset and range.
1. The dielectric of the measuring capacitor C.sub.x is of different material (a polyimide) than the dielectric of C.sub.o and C.sub.r (SiO.sub.2). Thus, the capacitance of the measuring capacitor varies with humidity while the capacitance of the others do not.
2. C.sub.o /C.sub.r is a constant for each circuit since the two capacitors are manufactured at the same time by the same process so that their characteristics are inherently the same.
3. C.sub.x /C.sub.r varies from unit to unit due to variations in the manufacturing processes by which the two capacitors are made.
4. The capacitance of C.sub.x at full scale (100% relative humidity) is designated as C.sub.x (100) and the capacitance of C.sub.x at 0% relative humidity is designated as C.sub.x (0). The ratio C.sub.x (100)/C.sub.x (0) is designated as α.
It is evident from the above that it is desired to provide a circuit that can correct for C.sub.x /C.sub.r and, as stated, it is desired to do this with a single potentiometer.
The following equation may be written to express the quantity C.sub.x (100)-C.sub.x (0), which shall be referred to as the gain G.
G=(&#945;-1)C.sub.x (0) (V.sub.s)/C.sub.r
Since V.sub.os, the output voltage of the circuit of FIG. 2 at 0% humidity, is as follows
G=(&#945;-1)V.sub.os +((&#945;-1)C.sub.o)/C.sub.r V.sub.s.
Since α and C.sub.o /C.sub.r are constants, the latter term in the above equation can be represented by a divider on V.sub.s. This is shown in FIG. 4 as the divider which consists of the resistors 72 and 74. Thus, the voltage introduced to the REF HI pin 36 over line 76 accomodates for the constant term of the equation. The first term is taken care of by resistor 78 which forms part of another divider circuit with resistor 72 and thus also influences REF HI. REF LO, pin 35, is connected to circuit common, as shown. The result of the divider and resistor 78 which together provide the input to pin 36 is to accomodate the span of the measuring circuit to the span of the A/D converter so that the voltage V.sub.o which corresponds to 100% relative humidity, for example, will cause the readout of the 7126 to be full scale.
As shown in FIG. 9, the input V.sub.o from the output of the circuit of FIG. 2 is introduced to the IN HI pin 34 through resistor 100, which may be of 1M, and across the capacitor 102, which may be 0.002 f.
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