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Timestamp: 2014-07-11 08:15:33
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Patent US7970358 - Adaptive radio transceiver with a local oscillator - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including...http://www.google.com/patents/US7970358?utm_source=gb-gplus-sharePatent US7970358 - Adaptive radio transceiver with a local oscillatorAdvanced Patent SearchPublication numberUS7970358 B2Publication typeGrantApplication numberUS 12/782,405Publication dateJun 28, 2011Filing dateMay 18, 2010Priority dateOct 21, 1999Also published asUS6404293, US6417737, US6608527, US7031668, US7555263, US7720444, US8041294, US20030042984, US20030067359, US20060205374, US20090286487, US20100295598Publication number12782405, 782405, US 7970358 B2, US 7970358B2, US-B2-7970358, US7970358 B2, US7970358B2InventorsHooman Darabi, Ahmadreza Rofougaran, Maryam RofougaranOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (72), Non-Patent Citations (1), Referenced by (1), Classifications (31) External Links: USPTO, USPTO Assignment, EspacenetAdaptive radio transceiver with a local oscillatorUS 7970358 B2Abstract An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
1. A wireless spread spectrum communications device, comprising:
a quadrature oscillator configured to generate a first signal having a first frequency,
a quadrature frequency divider configured to generate a second signal from the first signal, the second signal having a second frequency, and
a first quadrature mixer configured to mix the first signal and the second signal and configured to provide a third signal having a third frequency; and
a transmitter that transmits wireless radio signals, wherein the transmitter is operatively coupled to the local oscillator, wherein the transmitter comprises a second quadrature mixer configured to mix the third signal and a fourth signal, and
wherein the local oscillator and the transmitter are integrated on a single integrated circuit chip.
2. The wireless spread spectrum communications device according to claim 1, wherein the local oscillator and the transmitter employ CMOS technology.
3. The wireless spread spectrum communications device according to claim 1, wherein the third frequency comprises a sum of the first frequency and the second frequency.
4. The wireless spread spectrum communications device according to claim 1, wherein the fourth signal comprises a baseband signal.
5. The spread spectrum wireless communications device according to claim 1, wherein the quadrature frequency divider is programmable.
6. The wireless spread spectrum communications device according to claim 1, wherein the quadrature oscillator comprises a voltage controlled oscillator.
7. The wireless spread spectrum communications device according to claim 6, wherein the local oscillator comprises a phase locked loop that is configured to control the first frequency of the first signal generated by the voltage controlled oscillator.
8. The wireless spread spectrum communications device according to claim 7,
wherein the local oscillator comprises a second quadrature oscillator and a second frequency divider,
wherein the second frequency divider is operatively coupled to the second oscillator and the voltage controlled oscillator, and
wherein the second quadrature oscillator receives an output of the second frequency divider.
9. The wireless spread spectrum communications device according to claim 8, wherein the second frequency divider comprises a programmable divisor input.
10. The wireless spread spectrum communications device according to claim 1, comprising:
a receiver that receives second wireless radio signals, wherein the receiver comprises a third quadrature mixer that is configured to mix the third signal and a fifth signal.
11. The wireless spread spectrum communications device according to claim 8, comprising:
a receiver that receives second wireless radio signals, wherein the receiver comprises a third quadrature mixer that is configured to mix an output of the second quadrature oscillator with a fifth signal.
12. The wireless spread spectrum communications device according to claim 1, wherein the wireless spread spectrum communications device performs orthogonal frequency division multiplexing.
13. The wireless spread spectrum communications device according to claim 1, wherein the wireless spread spectrum communications device performs spread spectrum modulation.
14. The wireless spread spectrum communications device according to claim 1, wherein the wireless spread spectrum communications device performs frequency hopping.
15. The wireless spread spectrum communications device according to claim 1, wherein the wireless spread spectrum communications device performs direct sequence spread spectrum modulation.
16. The wireless spread spectrum communications device according to claim 1, wherein the local oscillator or the transmitter employs CMOS technology.
17. The wireless spread spectrum communications device according to claim 1, wherein the wireless spread spectrum communications device can be programmed to support a plurality of different wireless spread spectrum modulation techniques.
18. The wireless spread spectrum communications device according to claim 1, wherein the wireless spread spectrum communications device supports a plurality of different wireless spread spectrum modulation techniques.
19. The wireless spread spectrum communications device according to claim 1, wherein the wireless spread spectrum communications device supports wireless communications using at least two of the following: orthogonal frequency division multiplexing communications, spread spectrum communications, Bluetooth communications and wireless local area network communications.
20. The wireless spread spectrum communications device according to claim 1, wherein the wireless spread spectrum communications device supports wireless communications using Bluetooth communications and wireless communications using wireless local area network communications. Description
CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a CONTINUATION of co-pending U.S. application Ser. No. 11/340,038, filed Jan. 26, 2006, which is a CONTINUATION of U.S. application Ser. No. 10/165,464, filed Jun. 7, 2002, now issued U.S. Pat. No. 7,031,668, which is a CONTINUATION of U.S. application Ser. No. 09/691,633, filed Oct. 18, 2000, now issued U.S. Pat. No. 6,404,293, which is a CONTINUATION of U.S. application Ser. No. 09/634,552, filed Aug. 8, 2000, now issued U.S. Pat. No. 7,555,263. Said U.S. application Ser. No. 09/634,552 makes reference to, claims priority to and claims benefit from U.S. Provisional Application No. 60/160,806, filed Oct. 21, 1999; U.S. Provisional Application No. 60/163,487, filed Nov. 4, 1999; U.S. Provisional Application 60/163,398, filed Nov. 4, 1999; U.S. Provisional Application No. 60/164,442, filed Nov. 9, 1999, U.S. Provisional Application No. 60/164,194, filed Nov. 9, 1999; U.S. Provisional Application No. 60/164,314, filed Nov. 9, 1999; U.S. Provisional Application No. 60/165,234, filed Nov. 11, 1999; U.S. Provisional Application No. 60/165,239, filed Nov. 11, 1999; U.S. Provisional Application No. 60/165,356, filed Nov. 12, 1999; U.S. Provisional Application No. 60/165,355, filed Nov. 12, 1999; U.S. Provisional Application No. 60/172,348, filed December 16, 1999; U.S. Provisional Application No. 60/201,335, filed May 2, 2000; U.S. Provisional Application No. 60/201,157, filed May 2, 2000; U.S. Provisional Application No. 60/201,179, filed May 2, 2000; U.S. Provisional Application No. 60/202,997, filed May 10, 2000; and U.S. Provisional Application No. 60/201,330, filed May 2, 2000. The above-identified applications are hereby incorporated herein by reference in their entirety.
Said U.S. application Ser. No. 11/340,038, filed Jan. 26, 2006, is also a CONTINUATION of U.S. application Ser. No. 09/634,552, filed Aug. 8, 2000, now issued U.S. Pat. No. 7,555,263, which claims priority to and benefit from U.S. Provisional Application No. 60/160,806, filed Oct. 21, 1999; U.S. Provisional Application No. 60/163,487, filed Nov. 4, 1999; U.S. Provisional Application 60/163,398, filed Nov. 4, 1999; U.S. Provisional Application No. 60/164,442, filed Nov. 9, 1999, U.S. Provisional Application No. 60/164,194, filed Nov. 9, 1999; U.S. Provisional Application No. 60/164,314, filed Nov. 9, 1999; U.S. Provisional Application No. 60/165,234, filed Nov. 11, 1999; Application No. 60/165,239, filed Nov. 11, 1999; U.S. Provisional Application No. 60/165,356, filed Nov. 12, 1999; U.S. Provisional Application No. 60/165,355, filed Nov. 12, 1999; U.S. Provisional Application No. 60/172,348, filed Dec. 16, 1999; U.S. Provisional Application No. 60/201,335, filed May 2, 2000; U.S. Provisional Application No. 60/201,157, filed May 2, 2000; U.S. Provisional Application No. 60/201,179, filed May 2, 2000; U.S. Provisional Application No. 60/202,997, filed May 10, 2000; and U.S. Provisional Application No. 60/201,330, filed May 2, 2000. The above-identified applications are hereby incorporated herein by reference in their entirety.
SUMMARY OF THE INVENTION In one aspect of the present invention, an oscillator circuit includes an oscillator to generate a first signal having a first frequency, a second oscillation source to generate a second signal having a second frequency, and a mixer to mix to the first and second signals.
DETAILED DESCRIPTION Exemplary Embodiments of a Transceiver In accordance with an exemplary embodiment of the present invention, a tranceiver utilizes a combination of frequency planning, circuit design, layout and implementation, differential signal paths, dynamic calibration, and self-tuning to achieve robust performance over process variation and interference. This approach allows for the full integration of the transceiver onto a single IC for a low cost, low power, reliable and more compact solution. This can be achieved by (1) moving external bulky and expensive image reject filters, channel select filters, and baluns onto the RF chip; (2) reducing the number of off-chip passive elements such as capacitors, inductors, and resistors by moving them onto the chip; and (3) integrating all the remaining components onto the chip. As those skilled in the art will appreciate, the described exemplary embodiments of the transceiver do not require integration into a single IC and may be implemented in a variety of ways including discrete hardware components.
f LO =f RF−(M�f OSC/nL)(1+1/N)=f OSC /L where fRF is frequency of the transmitter output.
V O ⁢ ⁢ I = A ⁢ ( 1 + j ⁢ ⁢ R ⁢ ⁢ C ⁢ ⁢ ω ) ⁢ V II + 2 ⁢ QV IQ ( 1 + j ⁢ ⁢ R ⁢ ⁢ C ⁢ ⁢ ω ) 2 + 4 ⁢ Q 2 ⁢ ⁢ and ( 1 ) V OQ = A ⁢ - 2 ⁢ QV II + ( 1 + j ⁢ ⁢ R ⁢ ⁢ C ⁢ ⁢ ω ) ⁢ V IQ ( 1 + j ⁢ ⁢ R ⁢ ⁢ C ⁢ ⁢ ω ) 2 + 4 ⁢ Q 2 ( 2 ) FIG. 7 shows the frequency response for the complex biquad filter.
H ⁡ ( jω ) = V o V I ⁢ ( jω ) = A 1 + j ⁢ ⁢ R ⁢ ⁢ C ⁢ ⁢ ω - j ⁢ ⁢ 2 ⁢ Q ( 3 ) This shows a passband gain of A 122 at a center frequency of 2Q/RC 124, with a 3-dB bandwidth of 2RC 126. Thus, the quality factor of the second-order stage will be Q. For the image signal however, the signal at the I branch leads, and as a result:
H ⁡ ( jω ) = A 1 + j ⁢ ⁢ R ⁢ ⁢ C ⁢ ⁢ ω + j ⁢ ⁢ 2 ⁢ Q ( 4 ) which shows that the image located at 2Q/RC is rejected by
1 ( 1 + ( 4 ⁢ ⁢ Q ) ⁢ 2 . Therefore, the biquad stage has an asymmetric frequency response, that is, the desired signal may be assigned to positive frequencies, whereas the image is attributed to negative frequencies. In general, the frequency response of the biquad stage is obtained by applying the following complex-domain transformation to a normalized real-domain lowpass filter:
α i � BW = - 1 RC ⁢ ⁢ and ( 7 ) ω o + β i � BW = 2 ⁢ ⁢ Q RC ( 8 ) Since the LP equivalent poles are located in the left-half plane, ai is always negative. The above equations set the value of Q and RC in each stage. The gain of each biquad stage can be adjusted based on the desired gain in the complex filter, and noise-linearity trade-off: increasing the gain of one biquad stage lowers the noise contributed by the following biquad stages, but it also degrades the linearity of the complex filter.
H ⁡ ( jω ) = A ⁢ 1 - RC z A ⁢ ω 1 + j ⁢ ⁢ RC ⁢ ⁢ ω - j2 ⁢ ⁢ Q ( 14 ) Equation (14) is analogous to equation (3), with the difference that now a zero at A/RCz is added to the biquad stage of the complex filter. By knowing the LP equivalent characteristics of the biquad stage, the poles are calculated based on equation (6). The value of Q and RC in each biquad stage is designed by using equation (7) and equation (8). If the normalized LP zeros are at �ωz,LP, then the biquad stage should be realized with two biquad stages cascoded, and the frequency of zeros in the biquad stages will be (equation (5)):
ωz1,2=ω0�ωz,LP �BW (15)
y=β2Vin 2 (20)
Ideal ⁢ ⁢ Dynamic ⁢ ⁢ Range = 20 ⁢ log ⁢ S S A n = 20 ⁢ log ⁢ ⁢ A n = 20 ⁢ ( n ) ⁢ log ⁢ ⁢ A ( 22 ) However, in the case of a large amount of gain, the input level will be limited with the input noise and the dynamic range will also be limited to:
A 2β2νin 2 +A 4β4νin 4 + . . . +A 2(n-m)νin 2(n-m) +mβ 2 S 2 =RSSI (25)
Ideal RSSI=C log Vin 2 (28)
Max ⁢ ⁢ RSSI - Min ⁢ ⁢ RSSI = C ⁢ ⁢ log ⁢ ⁢ A 2 ⁢ ⁢ n ( 29 ) Δ ⁢ ⁢ RSSI = C ⁢ ⁢ log ⁢ ⁢ A 2 ⁢ ⁢ n ( 30 ) C = Δ ⁢ ⁢ RSSI 2 ⁢ ⁢ n ⁢ ⁢ log ⁢ ⁢ A ( 31 ) ( Ideal ) ⁢ RSSI = Δ ⁢ ⁢ RSSI 2 ⁢ ⁢ n ⁢ ⁢ log ⁢ ⁢ A ⁢ log ⁢ ⁢ V in 2 ( 32 ) To find the relation between the gain of a differential amplifier, the gain of a rectifier, and the maximum input range of the combined differential amplifier and the rectifier, the RSSI will be calculated for the two consecutive differential amplifier and rectifier combinations (see equations (33) and (34)) for both ideal RSSI equations (32) and approximated RSSI equation (27):
V in ⁢ ⁢ 1 = S ( A ) n - m ( 33 ) V in ⁢ ⁢ 2 = S ( A ) n - m - 1 ( 34 ) ( Ideal ) ⁢ RSSI 2 - RSSI 1 = log ⁡ ( A ) 2 ( 35 ) ( Approximated ) ⁢ RSSI 2 - RSSI 1 = β 2 ⁢ S 2 ( 36 ) Therefore,
C log(A)2=β2 S 62 (37)
RSSI = 1 ( A ⁢ ⁢ β ) 2 - 1 ⁢ ( A ⁢ ⁢ β ) 2 ⁢ ( n - m ) ⁢ V in 2 + m ⁢ Δ ⁢ ⁢ RSSI n ; ⁢ ⁢ S A n - m < V in < S A n - m - 1 ( 39 ) FIG. 16( a) shows a schematic diagram for an exemplary embodiment of the differential amplifier used in the type II core amplifier. The differential input signal is fed to the gates of transistor amplifiers 955, 957. The amplified differential output signal is provided at the drains of the transistor amplifiers 955, 957. The gain of the transistor amplifiers is set by load transistors 958, 860, each connected between the drain of one of the transistor amplifiers and a power source. More particularly, the gain of the differential amplifier is determined by the ratio of the square root of transistor amplifiers-to-load transistors.
Gain ⁡ ( A ) = w in w in = 200 6 ≈ 5.8 ( 40 ) The sources of the transistor amplifiers 955, 957 are connected in common and coupled to a constant current source transistor 952. In the described exemplary embodiment, the controller provides the bias to the gate of the transistor 952 to set the current.
if ⁢ ⁢ Δ ⁢ ⁢ I SQM ⁢ ⁢ 1 = ( I D ⁢ ⁢ 1 + I D ⁢ ⁢ 4 ) - ( I D ⁢ ⁢ 2 + I D ⁢ ⁢ 3 ) = 2 ⁢ ( I DC + I SQ ) = 2 ⁢ k - 1 k + 1 ⁢ I o - 4 ⁢ k ⁡ ( k - 1 ) ⁢ β N ( k + 1 ) 2 ⁢ V I 2 ( 41 ) The input dynamic range of the full rectifier is then:
if ⁢ ⁢ Δ ⁢ ⁢ I SQM ⁢ ⁢ 1 = O , V i = � I o β N ⁢ k + 1 2 ⁢ ⁢ k ( 42 ) The full-wave rectifier includes two unbalanced differential pairs with a unidirectional current output. One rectifier 976 taps each differential pair and sums their currents into a 10 kW resistor RL.
β 2 ⁢ S 2 = 4 ⁢ k ⁡ ( k - 1 ) ⁢ β N ( k + 1 ) 2 ⁢ V i 2 ⁢ R L ( 43 ) By plugging the Vi from equation (42) and replacing β3 2S2 from equation (38), the following relation is obtained:
Δ ⁢ ⁢ RSSI n = 2 ⁢ k - 1 k + 1 ⁢ I o ⁢ R L ( 44 ) For ΔRSSI=1V, n=7 stages, RL=10000 Ω, and k=4, from the above equation Io is calculated to be 12 mA. Therefore, each rectifier will be biased with two 12 mA current sources (one 12 ma current source for the I signal and a second 12 ma current source for the Q channel). This results in an approximately logarithmic voltage, which indicates the received signal-strength (RSSI).
The controller provides RC calibration to keep the differentiation gain process invariant. In order to reduce the effect of any high frequency coupling to the differentiator input, the differentiator gain is flattened out for frequencies beyond the band of interest. In addition to frequency discrimination, the differentiation process adds a 90 degrees phase shift to the incoming signal. This phase shift is inherent to differentiation process. Since the output is in quadrature phase with the input (except for differing amplitude), cross multiplication of the input and output-results in frequency information.
For N=2, the LO generator output will have a frequency of 1.5 f1, and the closest spurs will be located �f1 away from the output. These spurs can be rejected by positioning LC filters (not shown) at the output of each circuit in the LO generator. A second-order LC filter tuned to f0, with a quality factor Q, rejects a signal at a frequency off as given in the following equation:
 H ⁡ ( f )  = f Qf 0 [ 1 - ( f f 0 ) 2 ] 2 + ( f Qf 0 ) 2 ( 49 ) The following discussion changes based on the Q value. Considering a Q of about 5 for the inductor, with f0=1.5 f1, the spur located at 2.5 f1 is rejected by about 15 dB by each LC circuit. This spur is produced at the LO generator output due to the mixing of the VCO third harmonic (at 3 f1) with the divider output (at 0.5 f1). This signal is attenuated by 10 dB since the third harmonic of a square-wave is one third of the main harmonic, 15 dB at the LC resonator at the mixers output tuned to 1.5 f1, and another 15 dB at the output of the buffers (900, 902 in FIG. 33). This gives a total rejection of 40 dB. When applied to the mixers in the transmitter, this LO generator output will upconvert the baseband data to 2.5 f1. With LC filters (not shown) positioned at the upconversion mixers and PA output in the transmitter, another 15+15=30 dB rejection is obtained (FIG. 33).
FIG. 33( a) shows a signal passing through a limiting buffer 910 (such as the buffers implemented in the LO generator). When a large signal at a frequency off accompanied with a small interferer at a frequency of Δf 902 away pass through a limiting buffer, at the limiter output the interferer produces two tones �Δf 914, 916 away from the main signal, each with 6 dB lower amplitude. Therefore, the spur at 2.5 f1 will actually be 10+15+15+6=46 dB attenuated when it passes through the buffer, instead of the 40 dB calculated above. It will also produce an image at 0.5 f1 which is 10+15+22+6=53 dB lower than the main signal. This will dominate the spur at 0.5 f1 because of the third harmonic of the divider mixed with the VCO signal, which is more than 75 dB lower than the main signal.
V out � I=Cos(ω2 t)�Cos(ω1 t+θ)−Sin(ω2 t)�Sin(ω1 t) (50)and V out � Q=Cos(ω2 t)�Sin(ω1 t)+Sin(ω2 t)�Cos(ω1 tθ) (51)
V out_I = - Sin ⁡ ( θ 2 ) � Sin ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 2 ) + Cos ⁡ ( θ 2 ) � Cos ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 2 ) ⁢ ⁢ ⁢ and ( 52 ) V out_Q = - Sin ⁡ ( θ 2 ) � Cos ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 2 ) + Cos ⁡ ( θ 2 ) � Sin ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 2 ) ( 53 ) The above equations show that regardless of the value of θ, the outputs are always in quadrature. However, other effects should be evaluated. First, a spur at ω1−ω2=0.5 ω1 is produced at the output. This spur can be attenuated by 2�22=44 dB by the LC filters at the mixer and its buffer outputs. Thus, for 60 dB rejection, the single sideband mixers need to provide an additional 16 dB of rejection (about 0.158). Based on equation (53), tan(θ/2)=0.158, or θ≈18�, phase accuracy of better than 18� can generally be achieved. Second, phase error at the VCO output lowers the mixer gain (term Cos(θ/2) in equation (52) or (53)). For a phase error of 18�, the gain reduction is, however, only 0.1 dB, which is negligible. For θ=90� (a single-phase VCO), both sidebands are equally upconverted at the mixer output. However, the LC filters reject the lower sideband by about 44 dB. The mixer gain will also be 3 dB lower. This will slightly increase the power consumption of the LO generator. If θ=180� (the VCO I and Q outputs are switched), the lower sideband is selected, and the desired sideband is completely rejected.
The controller performs adaptive programming and calibration of the receiver, transmitter and LO generator (see FIG. 2). An exemplary embodiment of the controller in accordance with one aspect of the present invention is shown in FIG. 38. A control bus 17 provides two way communication between the controller and the external processing device (not shown). This communication link can be used to externally program the transceiver parameters for different modulation schemes, data rates and IF operating frequencies. In the described exemplary embodiment, the external processing device transmits data across the control bus 17 to a bank of addressable registers 900-908 in the controller. Each addressable register 900-908 is configured to latch data for programming one of the components in the transmitter, receiver LO generator. By way of example, the power amplifier register 900 is used to program the gain of the power amplifier 62 in the transmitter (see FIG. 2). The LO register 902 is used to program the IF frequency in the LO generator. The demodulator register 903 is used to program the demodulator for FSK demodulation, or alternatively in the described exemplary embodiment, program the AID converter to handle different modulation schemes. The AGC register 905 programs the gain of the programmable multiple stage amplifier when in the AGC mode. The filter registers 901, 904, 906 program the frequency and bandwidth of their respective filters.
With an input dynamic range of 50 dB, the RSSI circuit is designed to detect the levels of rejection provided by the polyphase filtering. The outputs of RSSI block 284 and RSSI block 285 are coupled to a comparator 280 where the level of signal rejection of each polyphase filter is compared by comparator 280. The outputs of the RSSI blocks are also coupled to the control logic 286. The control logic 286 determines from the RSSI outputs which polyphase filter has a lower amount of signal suppression. Then, the control logic 286 adjusts the frequency tuning of that filter in an incremental step via the control logic 286. This is done by either increasing the tuned frequency of the first filter (polyphase A) filter 280, or by decreasing the tuned frequency of the second filter (polyphase B) 282 by changing the appropriate 4-bit control word. This process continues in successive steps until the 4-bit control word in each branch are identical, at which point, the RC values of the two polyphase filters are equal. The 4-bit control word provides a maximum deviation of only �5%
Two branches of polyphase filtering are used in this algorithm. Two 4-bit control words are used to control the value of the capacitances in each polyphase filter. The initial control words set the capacitance in the first filter (Polyphase A) to its maximum value and the capacitance in the second filter (Polyphase B) to its minimum value. This provides an initial condition in which the filters have maximum signal suppression set at frequencies (ωlow and ωhigh) that are approximately �40% of the frequency of the input signal XIN for the case of nominal process variation. For a sinusoidal input XIN, the calibration circuit depicted in FIG. 40 would require only a single-stage polyphase filter in each branch. The single-stage filters would attenuate the sinusoid input signal, generating outputs at XA and XB with the dominant one still at the same frequency as the input signal. However, the reference clock from the LO generator is a digital rail-to-rail clock. Because the input is not a pure sinusoid, multiple-stage filters may provide greater calibration accuracy. In the case of a single-stage filter with a digital clock, the filter would suppress the fundamental frequency component at ωin to a significant degree but the harmonics would pass through relatively unaffected. The RSSI block would then detect and limit the third harmonic component of the input signal at 3 ωin, as it becomes the dominant frequency component after the fundamental is suppressed. This could result in an inaccurate calibration code.
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