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Timestamp: 2015-07-02 05:21:05
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Patent US6891236 - Semiconductor device and method of fabricating the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device using a TFT structure with high reliability is realized. As an insulating film used for the TFT, for example, a gate insulating film, a protecting film, an under film, an interlayer insulating film, or the like, a silicon nitride oxide film (SiNXBYOz) containing boron is formed...http://www.google.ca/patents/US6891236?utm_source=gb-gplus-sharePatent US6891236 - Semiconductor device and method of fabricating the sameAdvanced Patent SearchPublication numberUS6891236 B1Publication typeGrantApplication numberUS 09/479,262Publication date10 May 2005Filing date5 Jan 2000Priority date14 Jan 1999Fee statusPaidAlso published asUS7491655, US20050023579Publication number09479262, 479262, US 6891236 B1, US 6891236B1, US-B1-6891236, US6891236 B1, US6891236B1InventorsShunpei YamazakiOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (33), Non-Patent Citations (30), Referenced by (11), Classifications (45), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and method of fabricating the same
US 6891236 B1Abstract
A semiconductor device using a TFT structure with high reliability is realized. As an insulating film used for the TFT, for example, a gate insulating film, a protecting film, an under film, an interlayer insulating film, or the like, a silicon nitride oxide film (SiNXBYOz) containing boron is formed by a sputtering method. As a result, the internal stress of this film becomes −5�1010 dyn/cm2 to 5�1010 dyn/cm2, preferably −1010 dyn/cm2 to 1010 dyn/cm2, and the film has high thermal conductivity, so that it typically becomes possible to prevent deterioration due to heat generated at the time of an on operation of the TFT.
a gate electrode formed on an insulating surface; a gate insulating film comprising at least a single layer on said gate electrode; and a source region, a drain region, and a channel formation region formed between said source region and said drain region, the respective regions being in contact with said gate insulating film; wherein said gate insulating film includes a layer of a silicon nitride oxide film containing boron. 2. A semiconductor device according to claim 1, wherein a composition ratio of boron in said silicon nitride oxide film is 0.1 to 50 atoms %.
a source region, a drain region, and a channel formation region formed between said source region and said drain region, the respective regions being in contact with an insulating surface; a gate insulating film comprising at least a single layer on said channel formation region; and a gate electrode to be in contact with said gate insulating film; wherein said gate insulating film includes a layer of a silicon nitride oxide film containing boron. 8. A semiconductor device according to claim 7, wherein a composition ratio of boron in said silicon nitride oxide film is 0.1 to 50 atoms %.
an insulating film formed on an insulating surface; and a semiconductor component formed on said insulating film, said semiconductor component comprising as a source region, a drain region, and a channel formation region formed between the source region and the drain region, the respective regions being in contact with said insulating; wherein said insulating film is a silicon nitride oxide film containing boron. 14. A semiconductor device according to claim 13, wherein a composition ratio of boron in said silicon nitride oxide film is 0.1 to 50 atoms %.
a semiconductor component formed on an insulating surface, said semiconductor component comprising a source region, a drain region, and a channel formation region; and an insulating film for protecting said semiconductor component, said insulation film being in contact with the source region, the drain region, and the channel formation region; wherein said insulating film is a silicon nitride oxide film containing boron. 20. A semiconductor device according to claim 19, wherein a composition ratio of boron in said silicon nitride oxide film is 0.1 to 50 atoms %.
25. A semiconductor device according to claim 1, wherein an internal stress of said silicon nitride oxide film is a range of −5�1010 dyn/cm2 to 5�1010 dyn/cm2.
26. A semiconductor device according to claim 7, wherein an internal stress of said silicon nitride oxide film is a range of −5�1010 dyn/cm2 to 5�1010 dyn/cm2.
27. A semiconductor device according to claim 13, wherein an internal stress of said silicon nitride oxide film is a range of −5�1010 dyn/cm2 to 5�1010 dyn/cm2.
28. A semiconductor device according to claim 19, wherein an internal stress of said silicon nitride oxide film is a range of −5�1010 dyn/cm2 to 5�1010 dyn/cm2.
In order to attain the foregoing objects, the present invention is characterized in that an insulating film (SiNxByOz: where, X, Y and Z are values expressing the composition ratio, and X>0, Y>0, and Z>0) superior in thermal conductivity, which is formed by using a sputtering method in which film formation can be made at a low temperature and productivity is superior, is used as an insulating film of a semiconductor component or a semiconductor device. Since the insulating film (SiNxByOz) of the present invention contains boron of 0.1 to 50 atoms % or 1 to 50 atoms %, preferably 1 to 10 atoms %, the film has high thermal conductivity, and has an effect to prevent deterioration of characteristics due to heat of a semiconductor device. Moreover, since the insulating film (SiNxByOz) of the present invention has a blocking effect to movable ions such as sodium, the film has also an effect to prevent these ions from intruding into the semiconductor device, especially into a channel formation region from the substrate or the like. In addition, since the insulating film (SiNxByOz) of the present invention contains oxygen of 1 to 30 atoms %, the internal stress of the film can be made typically −5�1010 dyn/cm2 to 5�1010 dyn/cm2, preferably −1010 dyn/cm2 to 1010 dyn/cm2, stresses of the respective films are reduced, and it is possible to make film peeling hard to cause.
The first forming method of the present invention is a sputtering method using a target of single crystal silicon added with boron in an atmosphere containing the nitric oxide gas. In the present invention, a semiconductor target of single crystal or polycrystal preferably added with boron of 1�1017 cm−3 or more is used. The composition ratio of boron in the silicon nitride oxide film (SiNxByOz) can be changed by changing the boron content of the target. Moreover, an insulating film having a further complicated composition ratio can be obtained by using a plurality of targets, for example, a target added with boron and a target added with an impurity (for example, gallium (Ga)) to give another conductivity type at the same time.
By using the foregoing first forming method or the second forming method, it is possible to form the silicon nitride oxide film (SiNxByOz) 103 a in which boron of 0.1 to 50 atoms % or 1 to 50 atoms %, preferably 0.1 to 10 atoms % is contained in the film to raise thermal conductivity, and oxygen of 1 to 30 atoms % is contained in the film to raise adhesion. Since this silicon nitride oxide film (SiNxByOz) 103 a contains boron, the film has high thermal conductivity as compared with a conventional silicon nitride film (SiN). Moreover, since this silicon nitride oxide film (SiNxByOz) 103 a contains oxygen of 1 to 30 atoms %, it has high adhesion as compared with a conventional silicon nitride film (SiN), so that film peeling is hard to cause. It is preferable that the internal stress of this silicon nitride oxide film (SiNxByOz) is typically −5�1010 dyn/cm2 to 5�1010 dyn/cm2, preferably −1010 dyn/cm2 to 1010 dyn/cm2 (values obtained in stress measurement by Model-30114 of Ionic System Inc.). Of course, it is needless to say that this silicon nitride oxide film (SiNxByOz) has a sufficient insulation property. Especially, when the silicon nitride oxide film (SiNxByOz) is formed to be in contact with a gate electrode, heat generated at the time of driving a TFT can be quickly and easily dissipated. Thus, it is possible to effectively equalize a heat distribution all over the semiconductor device.
First, as a substrate 101, a glass substrate (Corning 1737; distortion point 667� C.) was prepared. Next, a gate wiring line (including a gate electrode) 102 of a laminate structure (not shown for simplification) was formed on the substrate 101. In this embodiment, a sputtering method was used to form a laminate of a tantalum nitride film (thickness of 50 nm) and a tantalum film (thickness of 250 nm), and the gate wiring line (including the gate electrode) 102 having the laminate structure was formed by using a photolithography method of a well-known patterning technique.
Next, an insulating film 103 b and an amorphous semiconductor film 104 were sequentially formed without opening to the air (FIG. 1B). In this embodiment, the silicon oxide film 103 b(thickness of 125 nm) was formed so to make a laminate by a plasma CVD method, so that a gate insulating film of laminate structure was formed. In this embodiment, although the two-layer insulating film is adopted as the gate insulating film, a single layer or a laminate layer of not less than three layers may be adopted. Besides, in this embodiment, a noncrystalline silicon film (amorphous silicon film) having a thickness of 54 nm was formed as the amorphous semiconductor film 104 on the gate insulating film by a plasma CVD method. Incidentally, in order to prevent adhesion of a pollutant from the air to the interface of any layers, laminate formation was sequentially made without opening to the air. Thereafter, a heat treatment (500� C., 1 hour) for reducing the concentration of hydrogen in the amorphous silicon film, which blocked crystallization of the semiconductor film, was carried out.
Next, a resist mask 109 covering a part of an n-channel TFT or a p-channel TFT was formed by patterning using a photomask, and a step of adding an impurity to give an n type to the crystalline semiconductor film was carried out, so that a first impurity region (n+ region) 110 a was formed (FIG. 2A). In this embodiment, phosphorus was used as the impurity to give the n type conductivity. As a doping gas, phosphine (PH3) diluted with hydrogen to 1 to 10% (in this embodiment, 5%) was used, and the dose amount was made 5�1014 atoms/cm2, and the acceleration voltage was made 10 kV. Further, when an operator suitably sets the pattern of the resist mask 109, the width of the n+ region is determined, and it is possible to relatively easily obtain the n+ region having a desired width and the channel formation region.
Next, a step of adding an impurity element to give the n type to the crystalline semiconductor film with its surface on which the insulating film 111 was provided was carried out, so that a second impurity region (n− region) 112 was formed (FIG. 2C). However, since the impurity is added through the insulating film 111 to the crystalline semiconductor film thereunder, it is important to suitably set the doping condition in view of the thickness of the insulating film 111. In this embodiment, phosphine diluted with hydrogen to 1 to 10% (in this embodiment, 5%) was used as a doping gas, the dose amount was made 3�1013 atoms/cm2, and the acceleration voltage was made 60 kV. By adding the impurity element through this insulating film 111, it was possible to form the impurity region having a desired concentration (1�1018 to 1�1019 atoms/cm3 in SIMS analysis). The thus formed second impurity region 112 functions as the LDD region. At this time, the impurity was further added so that a first impurity region 110 b was formed, and an intrinsic crystalline semiconductor region remained just under the channel protecting film. However, although not shown, actually, the impurity element is slightly bent around the channel protecting film toward the inside and is added.
Next, a resist mask 114 covering the n-channel TFT was formed using a photomask, and a step of adding an impurity element to give a p type to the crystalline semiconductor film was carried out, so that a third impurity region (p− region) 113 was formed (FIG. 2D). In this embodiment, B (boron) was used as the impurity element to give the p type. As a doping gas, diborane (B2H6) diluted by hydrogen to 1 to 10% was used, and the dose amount was made 4�1015 atoms/cm3, and the acceleration voltage was made 30 kV.
Next, the resist mask 114 was removed, and after an activation treatment of the impurity by laser annealing or thermal annealing was carried out, a heat treatment (350� C., 1 hour) was carried out in a hydrogen atmosphere, so that the whole was hydrogenated (FIG. 3A). Thereafter, an active layer having a desired shape was formed by a well-known patterning technique, and the channel protecting film 108 and the insulating film 111 covering the active layer were removed (FIG. 3B).
After the state shown in FIG. 4B was obtained, a heat treatment at a temperature of 550� C. for 4 hours was carried out in a nitrogen atmosphere, so that the amorphous silicon film 104 a was crystallized. By this crystallizing step, a crystalline silicon film 204 b was obtained. Since this crystal growth proceeds from the surface of the amorphous silicon film 104 a to which nickel was added toward the substrate 101 (vertical direction), this crystal growth will be referred to as “vertical growth” in this specification (FIG. 4C). Incidentally, in this embodiment, although the nickel containing layer is formed on the whole surface, such a structure may be adopted that the nickel containing layer is selectively formed using a resist or the like, so that crystallization proceeds in the direction parallel to the substrate surface (lateral direction).
The heat treatment can be made in an electronic furnace at 500 to 700� C., preferably 550 to 650 � C. At this time, it is necessary that the upper limit of the heating temperature is made lower than the glass distortion point of the glass substrate 101 used. If the temperature exceeds the glass distortion point, a warp, a shrinkage, or the like of the glass substrate becomes tangible. It is sufficient if the heating time is made about 1 to 12 hours. This heat treatment is carried out by furnace annealing (heat treatment in an electronic furnace). Heating means such as lamp annealing can also be used.
Although this laser irradiation step can be omitted, an effect to improve efficiency of a subsequent gettering step, in addition to the improvement in crystallinity, can be obtained by the laser irradiation. After the laser irradiation, the maximum value of the concentration of remaining nickel by SIMS is about 1�1019 to 2�1019 atoms/cm3.
A gettering technique (Japanese Patent Application Laid-open No. Hei. 10-270363) to remove or reduce a catalytic element remaining in the crystalline silicon film may be used. The publication discloses a technique of carrying out a heat treatment (300 to 700� C., 1 to 12 hours) after phosphorus is added to the whole surface or selectively. Alternatively, a method with a liquid phase using high temperature sulfuric acid, a method with a vapor phase containing a halogen element, or a method of adding boron and heating may be used.
Next, a resist mask 209 covering a part of an n-channel TFT or a p-channel TFT was formed by patterning with a photomask, and a step of adding an impurity element (phosphorus) to give an n type to the crystalline semiconductor film the surface of which was exposed was carried out, so that a first impurity region (n+ region) 210 a was formed (FIG. 5A). In this embodiment, phosphine (PH3) diluted with hydrogen to 1 to 10% (in this embodiment, 5%) was used as a doping gas, the dose amount was made 5�1014 atoms/cm2, and the acceleration voltage was made 10 kV.
Next, a step of adding an impurity to give an n type to the crystalline semiconductor film with the surface on which the control insulating film 211 was provided was carried out, so that a second impurity region (n− region) 212 was formed (FIG. 5C). In this embodiment, phosphine (PH3) diluted with hydrogen to 1 to 10% (in this embodiment, 5%) was used as a doping gas, the dose amount was made 3�1013 atoms/cm2, and the acceleration voltage was made 60 kV. By adding the impurity element through this control insulating film 211, it was possible to form the impurity region of a desired concentration (1�1018 to 1�1019 atoms/cm3 by SIMS analysis). The second impurity region 212 formed in this way functions as an LDD region. At this time, the impurity was further added to form a first impurity region 210 b, and an intrinsic crystalline semiconductor region remained just under the channel protecting film.
Next, a resist mask 214 covering the n-channel TFT was formed by using a photomask, and a step of adding an impurity to give a p type to the crystalline semiconductor film was carried out, so that a third impurity region (p+ region) 213 was formed (FIG. 5D). In this embodiment, diborane (B2H6) diluted with hydrogen to 1 to 10% was used as a doping gas, the dose amount was made 4�1015 atoms/cm2, and the acceleration voltage was made 30 kV.
Next, the resist mask 214 was removed, a heat treatment at 300 to 700� C. for 1 to 12 hours was carried out, and a technique to lower the concentration of nickel (Japanese Patent Application Laid-open No. Hei. 8-330602) was applied to this embodiment. In this embodiment, a heat treatment at 600� C. for 8 hours was carried out, so that nickel remaining in the inside of the LDD region and the channel formation region was moved to a high concentration impurity region (source region and drain region) (FIG. 6A). In this way, the channel formation region in which the concentration of nickel is lowered (1�1018 atoms/cm3 or less, preferably 1�1016 atoms/cm3 or less by SIMS analysis) is obtained. At the same time as the lowering of the catalytic element by this heat treatment, recovery of damage of crystallinity at the time of doping and an activation treatment of the impurities by thermal annealing are carried out. In addition, furnace annealing, laser annealing, or lamp annealing may be carried out. Thereafter, a heat treatment (350� C., 1 hour) was carried out in a hydrogen atmosphere, so that the whole was hydrogenated.
The semiconductor layer is formed to a thickness of 10 to 100 nm, typically 50 nm. Although hydrogen of 10 to 40 atom % is contained in the amorphous semiconductor film fabricated by the plasma CVD method, it is desirable that hydrogen is removed from the film by carrying out a heat treatment at 400 to 500� C. prior to the step of crystallization so that hydrogen content is made 5 atom % or less. Although the amorphous silicon film may be formed by another fabricating method such as a sputtering method or an evaporation method, it is desirable that an impurity element such as oxygen or nitrogen contained in the film is sufficiently lowered in advance.
Then, a step of adding a first impurity element to give an n type was carried out. As an impurity element to give the n type to a crystalline semiconductor material, phosphorus (P), arsenic (As), antimony (Sb) or the like is known. Here, phosphorus was used, and an ion doping method using phosphine (PH3) was carried out. In this step, for the purpose of adding phosphorus through the gate insulating film 506 and the first conductive film 507 to the semiconductor layer thereunder, the acceleration voltage was set as high as 80 keV. It is preferable that the concentration of phosphorus added to the semiconductor layer is within the range of 1�1016 to 1�1019 atoms/cm3, and here, it was made 1�1018 atoms/cm3. Then, regions 513 and 514 where phosphorus was added to the semiconductor layer were formed. A part of the region added with phosphorus and formed here is made a second impurity region functioning as an LDD region (FIG. 9B).
A step of adding a third impurity element to give a p type was carried out to a part of the semiconductor layer where the p-channel TFT was to be formed, while the resist masks 516, 517, 518 and 519 were made to remain as they were. As the impurity element to give the p type, boron (B), gallium (Ga) or the like is known, and here, boron was used as the impurity element, and was added by an ion doping method using diborane (B2H6). Also here, the acceleration voltage was made 80 keV, and boron was added at a concentration of 2�1020 atoms/cm3. Then, third impurity regions 552 and 553 where boron was added at a high concentration were formed as shown in FIG. 9D.
Then, a step of adding a second impurity element to give an n type was carried out. As a result, a first impurity region 537 which became a source region and a first impurity region 536 which became a drain region were formed. Here, an ion doping method using phosphine was carried out. Also in this step, for the purpose of adding phosphorus through the gate insulating film 506 to the semiconductor layer thereunder, the acceleration voltage was set as high as 80 keV. The concentration of phosphorus in this region is high as compared with the step of adding the first impurity element to give the n type, and it is preferable to make the concentration 1�1019 to 1�1021 atoms/cm3, and here, the concentration was made 1�1020 atoms/cm3(FIG. 10A).
It was necessary to carry out the step of the heat treatment in order to activate the impurity elements to give the n type or p type added at each concentration. This step may be carried out by a thermal annealing method using an electronic furnace, the laser annealing method using the excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. However, in the laser annealing method, although activation can be made at a low substrate heating temperature, it has been difficult to make activation up to a region concealed under the gate electrode. Thus, here, the step of activation was made by the thermal annealing method. The heat treatment was carried out in a nitrogen atmosphere at 300 to 700� C., preferably 350 to 550� C., here, 450� C. for 2 hours.
Next, after a dehydrogenating step at 500� C. for 1 hour was carried out, a heat treatment at 500 to 650 � C. for 4 to 24 hours (in this embodiment, at 550� C. for 14 hours) was carried out, so that a crystalline silicon film 605 was formed. The crystalline silicon film (also called polysilicon) 605 obtained in this way had extremely superior crystallinity (FIG. 11B).
Next, a heat treatment at 500 to 650� C. for 4 to 24 hours (in this embodiment, at 580� C. for 14 hours) was carried out, so that a crystalline silicon film 707 was formed. In this crystallizing process, a portion with which nickel is in contact is first crystallized, and crystal growth proceeds in the lateral direction therefrom. The thus formed crystalline silicon film 707 is made of a collective of rod-like or needle-like crystals, and the respective crystals macroscopically grow with certain directionality. Thus, there is an advantage that crystallinity is uniform.
The technique disclosed in the application is such that a catalytic element used for crystallization of an amorphous semiconductor film is removed after crystallization by using a gettering function of phosphorus. By using the technique, it is possible to reduce the concentration of a catalytic element in a crystalline semiconductor film to 1�1017 atoms/cm3 or less, preferably 1�1016 atoms/cm3 or less.
In this state, when a heat treatment at 550 to 800� C. for 5 to 24 hours (in this embodiment, at 600� C. for 12 hours) was carried out in a nitrogen atmosphere, the region 805 where phosphorus was added in the crystalline silicon film functioned as a gettering site, so that it was possible to move the catalytic element remaining in the crystalline silicon film 803 into the region 805 added with phosphorus.
By removing the silicon oxide film 804 for masking and the region 805 added with phosphorus through etching, it was possible to obtain a crystalline silicon film in which the concentration of the catalytic element used in the step of crystallization was reduced to 1�1017 atoms/cm3 or less. It was possible to use this crystalline silicon film without any change as the semiconductor layer of the TFT of the present invention described in Embodiment 4.
Here, a substrate having heat resistance of at least about 700 to 1100� C. was necessary and a quartz substrate 900 was used. A silicon oxide was used for an upper layer of an under film 901, and a silicon nitride oxide (SiNxByOz) containing boron was used for a lower layer, so that deterioration of characteristics due to heat of the semiconductor device was prevented. If film peeling does not occur, an amorphous silicon film may be formed to be in contact with the silicon nitride oxide (SiNxByOz). Then, the technique disclosed in Embodiment 5 was used to form a crystalline semiconductor film. For the purpose of transforming this into an active layer of a TFT, this was patterned into island-like regions so that semiconductor layers 902 and 903 were formed. A gate insulating film 904 covering the semiconductor layers 902 and 903 was formed of a film containing silicon oxide as its main ingredient. In this embodiment, a silicon nitride oxide film having a thickness of 70 nm was formed by a plasma CVD method (FIG. 14A).
Then, a heat treatment was carried out in an atmosphere containing a halogen (typically, chlorine) and oxygen. In this embodiment, the heat treatment was carried out at 950� C. for 30 minutes. Incidentally, it was appropriate that the treatment temperature was selected within the range of 700 to 1100� C. and the treatment time was selected within the range of 10 minutes to 8 hours (FIG. 14B).
Next, the whole substrate 1001 is immersed in a liquid phase (in this embodiment, a sulfuric acid solution) heated to a temperature of 300� C., so that nickel used for crystallization is removed or reduced. In this embodiment, although gettering is carried out before patterning of an active layer is carried out, the gettering may be carried out after the patterning of the active layer is carried out. As another means for establishing contact with sulfuric acid, a method of uniformly dropping a heated sulfuric acid solution onto the substrate may be used.
In this step, nickel resolves and dissolves in the heated sulfuric acid, and is easily removed from the vicinity of the surface. Then, nickel in the inside diffuses to the vicinity of the surface having a low concentration, and more nickel is dissolved. This phenomenon is repeated, so that nickel used for crystallization is removed or reduced from the crystalline silicon film. In this way, by carrying out the lowering treatment of the catalytic element through the liquid phase, the concentration of the catalytic element in the crystalline silicon film 1106 can be lowered to 1�1017 atoms/cm3, preferably 1�1016 atoms/cm3(FIG. 15B).
Next, a gate insulating film and an amorphous silicon film are continuously formed to cover the gate electrode. In the case of an amorphous silicon TFT, although the gate insulating film may be made a multi-layer film similarly to Embodiment 1, since boron is not activated and does not influence the conductivity even if boron is mixed in an active layer made of amorphous silicon, in this embodiment, a silicon nitride oxide film added with boron and an amorphous silicon film were continuously formed in the same chamber. Since oxygen is contained, the internal stress of the silicon nitride oxide film added with boron is typically −5�1010 dyn/cm2 to 5�1010 dyn/cm2, preferably −1010 dyn/cm2 to 1010 dyn/cm2, which is a preferable stress range in adhesion to the amorphous silicon film.
As described above, since the film (SiNxByOz) containing silicon nitride as its main ingredient according to the present invention contains boron of 0.1 to 50 atoms % or 1 to 50 atoms %, preferably 0.1 to 10 atoms %, the film has high thermal conductivity, and has an effect to prevent deterioration of characteristics due to heat of a semiconductor device. Moreover, since the film containing silicon nitride as its main ingredient according to the present invention has a blocking effect to movable ions such as sodium, it has also an effect to prevent these ions from intruding into the semiconductor device, especially a channel formation region from a substrate or the like. In addition, since the film (SiNxByOz) containing silicon nitride as its main ingredient according to the present invention contains oxygen of 1 to 30 atoms %, the internal stress becomes typically −5�1010 dyn/cm2 to 5�1010 dyn/cm2, preferably −1010 dyn/cm2 to 1010dyn/cm2, and the film has high adhesion (adhesion between a crystalline semiconductor film and the SiNxByOz film, or adhesion between an amorphous semiconductor film and the SiNxByOz film) as compared with a conventional silicon nitride film (SiN).
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