Source: http://www.google.com/patents/US7536691?dq=%22Meaning-based+advertising+and+document+relevance+determination%22
Timestamp: 2016-04-30 15:34:00
Document Index: 320867744

Matched Legal Cases: ['art 4000', 'art 4000', 'art 4000', 'art 4000', 'art 4000', 'art 4000', 'art 4000', 'art 4000', 'art 4000', 'art 4000', 'art 400', 'art 4100']

Patent US7536691 - Method and apparatus for software-based allocation and scheduling of ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn architecture and method for dynamic resource allocation and scheduling in a communication device is disclosed herein. The method of controlling hardware resources in a communication device having a processor, a computer readable memory, and at least one hardware resource coupled to each other includes...http://www.google.com/patents/US7536691?utm_source=gb-gplus-sharePatent US7536691 - Method and apparatus for software-based allocation and scheduling of hardware resources in a wireless communication deviceAdvanced Patent SearchPublication numberUS7536691 B2Publication typeGrantApplication numberUS 09/927,906Publication dateMay 19, 2009Filing dateAug 9, 2001Priority dateAug 9, 2001Fee statusPaidAlso published asUS20030033411Publication number09927906, 927906, US 7536691 B2, US 7536691B2, US-B2-7536691, US7536691 B2, US7536691B2InventorsChakki Kavoori, Keith Rieken, David M. HolmesOriginal AssigneeInfineon Technologies AgExport CitationBiBTeX, EndNote, RefManPatent Citations (10), Non-Patent Citations (1), Referenced by (2), Classifications (16), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod and apparatus for software-based allocation and scheduling of hardware resources in a wireless communication device
20. A method of operating a plurality of hardware resources of a wireless communication device comprising:
a) locating a current address in a memory, the current address containing operating information associated with a current hardware resource of the plurality of hardware resources;
b) transmitting to the current hardware resource operating information associated with the current address to the current hardware resource;
c) reading a pointer in the memory, which is associated with the current address, that identifies another address containing operating information for operating another hardware resource of the plurality of hardware resources; and
d) determining whether the current hardware resource is reused within a system cycle,
wherein if the current hardware resource is reused within a system cycle, further comprising the steps of:
e) saving the current hardware resource information from a current use; and
f) repeating steps b), c), and d) until the current hardware resource is not reused within a system cycle.
21. The method of claim 20, wherein a hardware resource is at least one of a searcher element, a downlink transmitter element, matched filter element, or tracker element.
22. A method of operating a plurality of hardware resources of a wireless communication device comprising:
d) determining whether the current hardware resource is reused within a system cycle, wherein if the current hardware resource is not reused within a system cycle, further comprising the steps of:
e) determining whether operation of the current hardware resource should be terminated; and
f) if operation of the current hardware resource should not be terminated, repeating steps a), b), c), and d) for another hardware resource of the plurality of hardware resources that becomes the current hardware resource.
23. An apparatus for dynamically implementing changes for scheduling hardware resources in a wireless communication device having a memory, the apparatus comprising:
a) means for locating a current address in the memory, the current address containing operating information associated with a current hardware resource;
b) means for transmitting operating information associated with the current address to the current hardware resource;
c) means for reading a pointer associated with the current address; that identifies another address containing operating information for another hardware resource of the device; and
d) means for determining whether the current hardware resource is reused within a system cycle;
wherein if the current hardware resource is reused within a system cycle, further comprising:
e) means for saving the current hardware resource information from a current use,
wherein the changes for scheduling hardware resources are implemented in real time while the wireless communication device is operating.
24. The apparatus of claim 23, wherein a hardware resource is at least one of a searcher element, a downlink transmitter element, matched filter element, or tracker element.
25. An apparatus for dynamically implementing changes for scheduling hardware resources in a wireless communication device having a memory, the apparatus comprising:
c) means for reading a pointer associated with the current address, that identifies another address containing operating information for another hardware resource of the device; and
wherein if the current hardware resource is not reused within a system cycle, further comprising:
e) means for determining whether operation should be terminated,
wherein the changes for scheduling hardware resources are implemented in real time while the wireless communication device is operating. Description
IMPROVED APPARATUS AND METHOD FOR MULTI-THREADED SIGNAL PROCESSING Ser. No. 09/492,634, filed on Jan. 27, 2000 METHOD AND APPARATUS FOR TIME-SLICED AND MULTI-THREADED DATA PROCESSING IN A COMMUNICATION SYSTEM Ser. No. 09/920,093, filed Jul. 31, 2001 DYNAMICALLY RECONFIGURABLE UNIVERSAL TRANSMITTER SYSTEM Ser. No. 09/922,484, filed Aug. 3, 2001, now U.S. Pat. No. 7,233,810, issued Jun. 19, 2007 TECHNICAL FIELD
An additional situation encountered in real-time operation of an electronic communication device is the frequent change in the device's operating environment or processing needs. For example, a wireless communication system has frequent changes in the number of users (calls are initiate and terminated) and the quality and quantity of signals (e.g., the multipaths signal to noise ratio and strength, quantity of data transmitted, type of data transmitted, etc.). In short, a communication system can be extremely dynamic in many aspects. If an ASIC controller is utilized, its ability to accommodate the changes in the system may be limited to those conceived of during the design of the hardware-based controller. Consequently, its ability to accommodate new variations in system dynamics can be limited. The performance of a controller can also be compromised by inefficient use of hardware resources in the dynamic environment, by system interruptions, system crashes, and compounded fragmenting due to the dynamically changing environment. Thus, a need arises for a controller that can overcome the limitations of, system interruptions, system crashes, compounded fragmenting, and inefficient use of hardware resources due to the dynamically changing environment and other factors. Furthermore, a need arises for a controller that can effectively accommodate the changes in the system without compromising the integrity of the system itself, including processes that have not changed.
In particular, the present invention is applicable to the following exemplary list of digital direct sequence spread spectrum communication applications. One fixed wireless application to which the present invention may be applied is a metropolitan multipoint distribution system (MMDS). Examples include wireless cable broadcast, or two-way wireless local loop (WLL) systems. Some examples of a W-LAN, that can communicate digitized audio and data packets, for which the present invention can be applied, include Open Air and the Institute of Electrical and Electronics Engineers (IEEE) specification 802.1b. In yet another application, a specific example of an unlicensed FCC application to which the present invention may be applied include the Industrial, Scientific, and Medical band (ISM) devices, which can include cordless telephony products. Personal base stations can utilize either cordless or cellular telephony wireless communication standards. Lastly, the cellular telephony systems in which the present invention can be applied includes, but is not limited to, IS-95, IS2000, ARIB, 3GPP-FDD, 3GPP-TDD, 3GPP2, 1EXTREME, or other user-defined protocols. The range of code sequences utilized in the exemplary spread spectrum applications disclosed herein, are useful to define the class of functions for which the present configurable code generator unit is applicable. The present invention can also be utilized in any electronic device needing to control hardware resources.
Referring now to FIG. 1A, a block diagram of an electronic communication device that uses software-based allocation and scheduling of hardware resources is shown in accordance with one embodiment of the present invention. Electronic communication device 100 a provides an exemplary application of the present invention in a wireless direct sequence spread spectrum (DSSS) base transceiver station (BTS).
Communication system 100 a includes a receiver processor 102, a downlink processor 106, a searcher processor 110, and a matched filter processor 111. Receiver processor 102 includes tracking scheduler 102 a coupled to hardware resources 102 b. Transmit processor 106 includes downlink scheduler coupled to hardware resources 106. Similarly, searcher processor 110 includes searcher scheduler 110 a coupled to hardware resources 110 b while matched filter processor 111 includes filter scheduler 111 a coupled to hardware resources 111 b. Each scheduler 102 a, 106 a, 110 a and 111 a provides respective a software-based scheduler/allocator of hardware resources 102 b, 106 b, 110 b, and 111 b. The details of the components and processes for software-based allocation and scheduling of hardware resources are described in more detail in subsequent hardware figures and flowchart figures.
Communication device 100 a also includes an antenna 101, a front-end processing block 103, a base band processing block 116, a data processing block 119, a microprocessor (μP)/controller 130, a memory block 120, and a bus 117. Front-end processing block 103 is coupled to base band processing block 116, both of which are coupled to μP 130 and memory block 120 via bus 117. Microprocessor 130 and memory block 120 supports the exchange of data, control, or status information between the various components of communication device 100 a. Base band processor block 116 is coupled to front-end processing block 103 and is provided to receive signals while transmit processor block 106 is provided to transmit signals.
Base band processing block 116 is operable to process the band of frequencies of the signal delivered by a source, e.g., via front end processing and antenna 101. Base band processing block 116 includes a code generator unit (CGU) 104, a searcher processor block 110, a parameter estimator block 112 and a combiner block 108 all coupled to the receiver processor block 102. CGU 104, combiner(s) 108, and parameter estimator 112 have components and provide functions that are known by those skilled in the art. For example, receiver processor 102 performs despreading and demodulation functions known by those skilled in the art, while searcher processor 110 provides searching and filtering functions known to those skilled to locate signals. Transmit processor performs modulation functions known by those skilled in the art. Matched filter processor 111 performs detection functions.
Controller information to operate tracking scheduler 102 a, downlink scheduler 106 a, and searcher scheduler 110 a, are provided by pointer list input 142, and hardware parameters input 144. The delivery of the inputs can be provided by a variety of different sources and mediums, as described in subsequent figures.
Tracking scheduler 102 includes a memory block 152 coupled to a controller, or microprocessor (uP), block 154. Memory block 152 and uP block 152 have conventional construction known to those skilled in the art in the present embodiment. For example, memory can be any kind of suitable memory such as flash memory, non-volatile memory, registers etc. By using a local controller 154, receiver processor 102 can operate quasi-autonomously from the balance of communication device 100 a of FIG. 1A, and thereby reduce overhead and avoid interrupts.
Elements 156 a through 156 n of hardware resource 102 b include a conventional ASIC portion 157 coupled to a programmable and distributed micro digital signal processing units (micro DSP) 159 in the present embodiment. Both types of devices are coupled together to perform a desired function. The uDSP can perform repetitive functions, e.g., math operations, useful for a given application while the ASIC performs more function specific tasks for finger element 156 a. Additional information on the content and function of a uDSP is provided in co-pending U.S. patent application Ser. No. 09/912,721 entitled “Distributed Micro Instruction Set Processor Architecture for High-Efficiency Signal Processing” by Chen et al., filed Jul. 24, 2001. This related application is commonly assigned, and is hereby incorporated by reference. In another embodiment, elements of hardware resources 102 b can be either all ASIC or all uDSP or any combination thereof.
In another embodiment, hardware resources 102B, e.g., finger elements 156 a through 156 n, are limited to performing a single communication protocol, while in another embodiment; hardware resources are configurable to perform any one of a wide range of communication protocols. For example, co-pending U.S. patent application Ser. No. 09/751,783, entitled “A Configurable All-Digital Coherent Demodulator System for Spread Spectrum”, by Ravi Subramanian, filed Dec. 29, 2000, now U.S. Pat. No. 7,010,061, issued Mar. 7, 2006, is configurable to accommodate a wide range of communication protocols. This related application is commonly assigned, and is hereby incorporated by reference.
System cycle 162 is defined by a given application. For example, a communication protocol can have a system cycle with 2560 chips. However, the present invention is well suited to any length of system cycle that is defined by any variable, e.g., time, quantity of data, occurrence of events, etc. Each of the multiple virtual uses, 166, 168, through 170 of a single physical resource, e.g., hardware element A 172, within a given cycle, e.g., a system cycle 162, can be referred to as a virtual resource. Even though only one physical resource exists, its use for multiple contexts, e.g., users, occurs within a given period of time, e.g., cycle 162, and thus appears to be a resource that is operating in parallel to an observer that simply looks for a result in a period of a system cycle. However, virtual uses actually occur in series as shown by the sequential nature of process 166 b, 168 b through 170 b. Hardware element A is a physical finger element A 156 a of FIG. 1B in the present embodiment.
By reusing hardware, a given system can be tailored to individual needs by scaling the clock rate and thereby the virtual resources created by the multiple processing cycles with a given system cycle. M can be any value for a given application. The greater the number of virtual resources required, the higher a clock rate for the resource can be scaled. Also, the greater the number of virtual resources, the greater the amount of memory required to store context data save from one virtual use, and used to setup the virtual use for the next system cycle. Because each virtual use of a given hardware element is completed within a given system cycle, they appear to be performed in parallel as concurrent operations, though only a single hardware resource is used. More information on time-sharing of hardware resources is described in co-pending U.S. patent application Ser. No. 09/920,093 entitled “METHOD AND APPARATUS FOR TIME-SLICED ANT) MULTI-THREADED DATA PROCESSING IN A COMMUNICATION SYSTEM,” by Rieken et al., filed Jul. 31, 2001. This related application is commonly assigned, and is hereby incorporated by reference. Additional information is also provided in co-pending U.S. patent application Ser. No. 09/492,634 entitled “IMPROVED APPARATUS AND METHOD FOR MULTI-THREADED SIGNAL PROCESSING” by Subramanian et al., filed Jan. 27, 2000, now abandoned. This related application is commonly assigned, and is hereby incorporated by reference.
Components for communication device 100 a are shown in FIG. 1A and not repeated here for purposes of clarity. The operation of device 202 is discussed in a subsequent flowchart. Controller information 203 from external processor device 202 is communicated to configurable communicating device by interface 209. Interface 209 is a wired communication link that couples external processor device 202 and configurable communication device 100 a in one embodiment. However, in another embodiment, interface 209 is an electronic storage medium, e.g., CD-ROM and host device, which provides configuration information 203 to configurable communication device 100 a. In yet another embodiment, interface 209 is a wireless transmission from external processor device 202, or another communication device, e.g., a wireless base station or wireless test platform. In another aspect of the present invention, configuration information is provided at the time configurable communication device 100 a is manufactured and/or initially programmed for operation in the field, for the present embodiment. However, in another embodiment, configuration information is dynamically implemented at a time configurable communication device 100 a is in operation in the field.
Input of control information 232 b includes information related to implementing parameters for hardware resources via the software controller. For example, control information can include overhead information and sequencing information of multiple virtual uses, such as the overlapping stages shown in FIG. 1B. Control information can indicates configuration settings for configurable hardware resources in order to conform to a desired one of many possible communication protocols, e.g., as described in FIG. 1B. Control information can include user-defined parameters, performances and proprietary and non-proprietary algorithms including information such as threshold values, coefficient values, filter order, etc. The control information input 232 b can include management algorithms that account for dynamic changes in control of the flexible scheduler. For example, the conditions under which a hardware resource, such as a finger, is dropped and thus skipped by the controller may be indicated in the control information input. This input can affect quality of service provided by the communication device, as well as other performance metrics. The dynamic implementation of the control information is explained in subsequent tables and flowcharts.
Input of desired quantity of hardware resources 232 c is provided by the user as any value equivalent or less than the maximum number of resources available in the system in one embodiment defined by input 232 a. Similarly, input of computing resources 234 a accounts for any one of many possible computing resources used in a data processing device for which flexible control is desired. For example if an power PC processor is utilized as the host microprocessor 130 of communication device 100 a of FIG. 1A, then control information that interacts appropriately with the constraints and special commands of the power PC processor are provided to the function.
Protocol format input 234 b. Protocol format includes the appropriate word lengths and structure appropriate for the memory, e.g., 152, used in tracking scheduler 102 a. More information is provided on the specific structure of the memory and information stored thereon for controlling, in subsequent FIGS. 3A and 3B.
Other columns in table 300A represent the information, or class of information, that is actually stored in the memory buffers, e.g., memory 152 of FIG. 1B. For example, column 306 entitled hardware (H/W) control parameters set by software (S/W) represents a category of information stored in table 300A. In one embodiment, contents of column 306 are provided by a user via inputs 232 a-232 c in function block 230 of FIG. 2C in conjunction with computer 202 in FIG. 2B, in one embodiment. Parameters in column 306 can include hardware resource configurations required to conform to one of multiple possible communication (e.g., 3GPP) or data processing (e.g., IEEE 802.11b) protocols. Parameters in column 306 can also be user-defined performances, such as thresholds or state changes, as well as user-defined proprietary algorithmic settings for hardware within a given communication protocol. A user can be defined as a system operator, an infrastructure provider, or any other entity associated with the operation of a device using the flexible scheduler. In one embodiment, the possible settings for the function blocks are defined in Appendix A of the CBE, incorporated by reference hereinabove.
Each row represents a unique combination of both a hardware resource and a virtual use. Thus, equation [1] referred to above, indicates the number of rows necessary, e.g., M�N rows. Each row has data entries listed for each the columns described hereinabove. The entire table 300A is traversed according to the link list sequence within a given system cycle, e.g., cycle s162 of FIG. 1C, in the present embodiment.
Referring now to FIG. 3C, a table of computer memory fields that provide a hierarchy of software-based allocation and scheduling of hardware resources is shown, in accordance with one embodiment of the present invention. FIG. 3C includes an ID table 350, a resource A table 352 and a resource B table 354. ID table 350 includes a column for ID in which entries for ID-1, ID-2, and ID-N are shown. Resources tables 352 and 354 have a link in column 383 that point to the ID table. When a new user, e.g., mobile, first requests use of hardware resources in communication device 100 a, their ID can be entered into table 350 to allow tracking of the user for multiple processes and hardware resource allocations throughout the communication device. Pointers in the resource tables 352 and 354 provide a backtracking reference of determining the user.
Referring now to FIG. 3D is a table of computer memory fields that track users of software-based allocation and scheduling of hardware resources, in accordance with one embodiment of the present invention. Primary table 380A lists groups of hardware resources by a group identification in column 381 and by a pointer to a secondary table that identifies the start location for the control information on the hardware resources slated for the group. Primary table can provide a reference back to an ID table, e.g., table 350. The last entry in primary table is for B, after which the fist line in primary table is resume, e.g., pointer end traverses to the first line of the table. Secondary table includes an on/off column to turn control parameters for a hardware resource either on or off. No link list is listed in column 389 for all the entries in a group, e.g., first block A 370. This is because each entry has a default pointer to the next line in the table. In this manner, total flexibility throughout the table is eliminated at the benefit of ease of implementation and speed through which the table may be traversed. However, a link address can be implemented for any line of a hardware resource. This list can be referred to as a chunk list in that all the hardware elements in first block A 370 are implemented in a sequential fashion as the default address link sequence. While the present embodiment provides a specific quantity of table and columns in each table, the present invention is well suited to utilizing more or less columns with different types of information for other purposes. The flexibility and implementation ease of the present invention is still maintained with these alternative embodiments. Additional information on the design and implementation of primary and secondary tables 308A and 380B respectively, is provided in co-pending U.S. patent application Ser. No. 09/922,484 entitled “DYNAMICALLY RECONFIGURABLE UNIVERSAL TRANSMITTER SYSTEM” by Medlock et al., filed Aug. 3, 2001, now U.S. Pat. No. 7,233,810, issued Jun. 19, 2007. This related application is commonly assigned, and is hereby incorporated by reference.
Flowchart 4000 begins with step 4002. In step 4002 of the present embodiment, the initial address is located in memory. Step 4002 is implemented by a higher-level controller/microprocessor locating the first line of the controller instruction. In one embodiment, controller 130 of communication device 100 a in FIG. 1A locates the first line of controller memory, via pointer input 4002 a, with address ‘0001’ represented literally in address column 302 for controlling hardware resources 102 b of receiver processor 102. Step 4002 can be implemented by local controller 154 of FIG. 1B in another embodiment. Step 4002 can also be implemented by another table in memory 152 providing the pointer, such as that shown in FIG. 3C by primary table 380A fro Group A pointer to location of ‘0001’ in secondary table 380B. Following step 4002, flowchart 4000 proceeds to step 4004.
In step 4004 of the present embodiment, the information associated with address for controlling a hardware resource is transmitted. Information includes hardware (H/W) parameter from software (S/W) output 4004 a and H/W parameter from H/W output 4004 b in the present embodiment, as defined for column 306 and 308 respectively in FIG. 3A. However, step 4004 can include fewer or greater parameters as well as different types of parameters in another embodiment. Tracking scheduler 102 a is hard coded to the finger elements 156 a through 156 n of FIG. 1B, with appropriate interface to accommodate the virtual use context switching over time. Step 4004 can include a setup stage to provide parameters and state information to the hardware resource for the given user profile accessing the hardware resource, e.g., the virtual resource for this particular use. By using a setup stage, processing for one virtual use, e.g., virtual use 1 166, can occur while a subsequent virtual use is being setup in memory local to the hardware for another virtual use, e.g., virtual use 2 168, as shown in FIG. 1C. Following step 4004, flowchart 4000 proceeds to step 4006.
Flowchart 4000, and tracking scheduler 102 a, does not utilize a conventional handshake protocol in the present embodiment to confirm completion of a given process, e.g., process 166 b, for a given virtual use, e.g., virtual use 1 166, as shown in FIG. 1C. Rather, by limiting the virtual use to a predetermined length of time, the scheduler assumes that a given virtual use is completed after the elapse of the predetermined time. In the present invention, the processing stage, e.g., 166 b of FIG. 1C, is limited a priori to a specific quantity or duration of processing to ensure completion of all processing cycles of all virtual uses within system cycle 162. However, the present invention is well suite to using a handshaking protocol to confirm completion of a processing stage.
In step 4010 of the present embodiment, an inquiry determines whether the hardware resource is reused within a system cycle. If a given hardware resource is reused within a system cycle, then flowchart 4000 proceeds to step 4012. Alternatively, if the given hardware resource is not reused within the system cycle, then flowchart 4000 proceeds to step 4014.
In step 4012 of the present embodiment, the hardware resource information from the current use is saved. The hardware resource information can include states and timing information of the process being executed that are required to continue the process in the next cycle for the given user, e.g., mobile. The save stage saves appropriate parameters and states of the hardware resource following the processing stage. The setup and save stages of a use of a given hardware resource are performed in parallel with a process. Step 4012 is implemented in one embodiment by save stage 166 c for virtual use 1 which is occurring at the same time that setup stage for virtual use 2 is loading data into finger A 156A in FIG. 1B, from memory 152, for hardware resource to utilize. The setup and save can use local cache (not shown) in element, e.g., finger A 156A in one embodiment. Alternatively, any type of series or parallel processing is possible, given the appropriate memory and communication lines. The state and timing information can be saved in column 306 of table 300B.
In step 4014 of the present embodiment, an inquiry determines whether the end pointer is found. If the end pointer is found, then flowchart 4000 proceeds to step 4018. However, if an end pointer is not found, then flowchart 4000 proceeds to step 4016. Step 4014 provides logic for flowchart 4000 to repeatedly execute lines of control information for subsequent virtual uses of hardware resources. Step 4014 also provides the logic for flowchart 4000 to cease the execution of lines and return control to some external entity, e.g., host controller or a higher-level scheduler table such as primary table 380A. Table 300A provides an pointer at the end of the table entries, and it points back to an appropriate starting location, as shown by path 317.
In step 4016 of the present embodiment, control is advanced to the subsequent address. In the present embodiment, the link address can move control anywhere in the table as shown in FIG. 3A. In another embodiment, the link address simply moves to the next executable line in the table that has been predetermined. This latter embodiment can provide a change in the link address at either all entries or only at certain break points, e.g., at the end of a group of elements such as group block A 370 of FIG. 3D. Following step 4016, flowchart 400 returns to step 4004.
In step 4018 of the present embodiment, the end pointer is executed. Step 4018 is implemented by local controller 154 reading the end pointer and returning to some higher level table, e.g., primary table 380A, or higher level controller, e.g., host controller 130. Only the last element desired to be implemented the link address of ‘end’ or ‘null’ in column 389 that returns it to the primary table 380A. The end pointer can exist at the end of a group of elements, e.g., block A 370, or can exist only at the end of a list of all elements. By using a pointer, the present system does not need interrupt signals because control is passed with known steps. This process also makes changes in the sequence and allocation of elements easier to implement because he changes can be made at the predetermined times and implemented at known cycles of the control handoff.
In step 4106 of the present embodiment, operation information for operating each of the hardware resources is received. Operation information, which can include control information, that is received includes semi-static hardware parameters 4106 a input, e.g., hardware control parameters set by software of Table 3A. Operation information is described as parameters set for column 306 of FIG. 3A in one embodiment. That is, input 4104 is provided in column 306 of Table 300 in FIG. 3A and as input 232 b in FIG. 2C. In the present embodiment, all the control parameters for a given function are the same. However in another embodiment, the control parameters can be different for different channels, e.g., tailored depending on type of user, application, etc. within the communication device. This operation information is generated in one embodiment by FIGS. 2B and 2C and stored as controller information 203 in external processor device 202, and communicated via medium 209 to communication device 100 a as shown in FIG. 2A. A user can provide this operation information input per proprietary or well-known algorithmic solutions to a given data processing application, including but not limited to wireless communication. Operation information generated externally can be received in terms of parameter settings 144 at communication device 144. Following step 4106, flowchart 4100 proceeds to step 4107.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4967375 *Mar 17, 1986Oct 30, 1990Star Technologies, Inc.Fast architecture for graphics processorUS5446889 *Jul 21, 1994Aug 29, 1995Unisys CorporationComputer-based methods for determining the head of a linked listUS5673259 *May 17, 1995Sep 30, 1997Qualcomm IncorporatedRandom access communications channel for data servicesUS5692204 *Jun 19, 1996Nov 25, 1997International Business Machines CorporationMethod and apparatus for computer system power managementUS6353846 *Nov 2, 1998Mar 5, 2002Harris CorporationProperty based resource manager systemUS6598151 *Oct 1, 1999Jul 22, 2003Texas Instruments IncorporatedStack Pointer ManagementUS6608638 *Feb 7, 2000Aug 19, 2003National Instruments CorporationSystem and method for configuring a programmable hardware instrument to perform measurement functions utilizing estimation of the hardware implentation and management of hardware resourcesUS6826672 *May 15, 2001Nov 30, 2004Massachusetts Institute Of TechnologyCapability addressing with tight object boundsUS20010041594 *Feb 16, 2001Nov 15, 2001Commil Ltd.Wireless private branch exchange (WPBX) and communicating between mobile units and base stationsUS20020120710 *Feb 23, 2001Aug 29, 2002Murthy ChintalapatiMechanism for caching dynamically generated content* Cited by examinerNon-Patent CitationsReference1 *"Cisco Telephony Controller Software Release 4 Dial Plan Provisioning Guide", Apr. 19, 1999 (date located on the top of pp. 2-14), Appendix A, pp. 1-14.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS9172678 *Jun 28, 2011Oct 27, 2015At&T Intellectual Property I, L.P.Methods and apparatus to improve security of a virtual private mobile networkUS20130007232 *Jun 28, 2011Jan 3, 2013Wei WangMethods and apparatus to improve security of a virtual private mobile network* Cited by examinerClassifications U.S. Classification718/104, 718/101, 709/226International ClassificationG06F9/445, H04L12/28, G06F15/173, H04L29/06, H04L12/56, G06F9/46Cooperative ClassificationH04L69/12, H04W88/02, G06F9/44521, H04L29/06, H04W72/1215European ClassificationH04L29/06, G06F9/445LLegal EventsDateCodeEventDescriptionNov 20, 2003ASAssignmentOwner name: INFINEON TECHNOLOGIES AG, GERMANYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:M DISSOLUTION CORPORATION (FORMERLY KNOWN AS MORPHICS TECHNOLOGY, INC.);REEL/FRAME:014146/0100Effective date: 20030401Owner name: INFINEON TECHNOLOGIES AG,GERMANYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:M DISSOLUTION CORPORATION (FORMERLY KNOWN AS MORPHICS TECHNOLOGY, INC.);REEL/FRAME:014146/0100Effective date: 20030401Sep 8, 2009CCCertificate of correctionNov 16, 2012FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services