Source: http://www.google.com/patents/US7023268?ie=ISO-8859-1
Timestamp: 2014-07-10 07:13:09
Document Index: 610779923

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US7023268 - Systems and methods for automatically adjusting channel timing - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsSystems and methods for automatically adjusting the alignment of high-side and low-side pulse width modulated signals to improve dead time and shoot-through conditions. In one embodiment, a system includes a digital amplifier controller, an amplifier output stage coupled to the controller and configured...http://www.google.com/patents/US7023268?utm_source=gb-gplus-sharePatent US7023268 - Systems and methods for automatically adjusting channel timingAdvanced Patent SearchPublication numberUS7023268 B1Publication typeGrantApplication numberUS 10/805,741Publication dateApr 4, 2006Filing dateMar 22, 2004Priority dateMar 21, 2003Fee statusPaidPublication number10805741, 805741, US 7023268 B1, US 7023268B1, US-B1-7023268, US7023268 B1, US7023268B1InventorsWilson E. Taylor, Jack B. Andersen, Michael Rovner, Michael A. KostOriginal AssigneeD2Audio CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (10), Classifications (10), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSystems and methods for automatically adjusting channel timingUS 7023268 B1Abstract Systems and methods for automatically adjusting the alignment of high-side and low-side pulse width modulated signals to improve dead time and shoot-through conditions. In one embodiment, a system includes a digital amplifier controller, an amplifier output stage coupled to the controller and configured to receive audio signals from the controller, and one or more sensors coupled to the output stage. The sensors are configured to detect and/or measure various parameters, such as shoot-through current and distortion, which are associated with the operation of the output stage. The sensors provide feedback to an internal processor or modulator of the controller, which then adjusts the timing of the high-side and low-side signals to improve the operating conditions of the output stage by minimizing shoot-through current and/or distortion.
RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 60/456,421, entitled �Output Device Switch Timing Correction,� by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,414, entitled �Adaptive Anti-Clipping Protection,� by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,430, entitled �Frequency Response Correction,� by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,429, entitled �High-Efficiency, High-Performance Sample Rate Converter,� by Andersen, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,422, entitled �Output Filter, Phase/Timing Correction,� by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,428, entitled �Output Filter Speaker/Load Compensation,� by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,420, entitled �Output Stage Channel Timing Calibration,� by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,427, entitled �Intelligent Over-Current, Over-Load Protection,� by Hand, et al., filed Mar. 21, 2003; U.S. patent application Ser. No. 10/805,594, entitled �Systems and Methods for Protection of Audio Amplifier Circuits,� by Kost, et al., filed Mar. 19, 2004; each of which is fully incorporated by reference as if set forth herein in its entirety.
The FETs, however, do not turn on and off instantaneously, but instead require a certain amount of time to change between the �on� state and the �off� state. There may therefore be some overlap between the times each of the FETs is turned on. If there is little overlap, a �dead time� is introduced during which the signal produced by the output stage does not follow the input signal�and thus distortion is created. If there is a substantial amount of overlap, there will generally be less distortion, but the output stage may draw a great deal of current because both FETs are turned on and the current is allowed to flow essentially directly from a voltage source to ground. This current is referred to as �shoot-through� current. It is desirable to be able to adjust the amount of overlap between the signals in order to control the balance of the dead time and shoot-through current. This is particularly true since there are a number of factors that cause variations in the delays incurred by each of the signals, including component variations, environmental conditions (e.g., temperature), etc.
SUMMARY OF THE INVENTION One or more of the problems outlined above may be solved by the various embodiments of the invention. Broadly speaking, the invention comprises systems and methods for automatically adjusting the alignment of high-side and low-side pulse width modulated signals to improve dead time and shoot-through conditions.
The shoot-through current arises when both FETs in the output stage are turned on at the same time. In other words, one FET begins to turn on before the other FET is completely turned off. If both FETs are turned on, current �shoots through� both FETs from the voltage source to ground. The greater the overlap in time that both FETs are turned on, the greater the magnitude of the shoot-through current. Because the current that shoots through the FETs is wasted, it is desirable to minimize the shoot-through current. This is done by adjusting the relative timing of the high-side and low-side signals that turn the respective FETs on and off to minimize the overlap of the two FETs being turned on. The distortion, on the other hand, arises in the case when one FET begins to turn off, while the other FET is not yet completely turned on. In other words, there is a certain amount of �dead time� in the transition between one FET being turned on and the other being turned off, and vice versa. Because neither of the FETs is completely turned on during the dead time, the output stage cannot accurately reproduce the audio signal. The distortion is minimized by adjusting the relative timing of the high-side and low-side signals that turn the respective FETs on and off to reduce the dead time in the transition between on and off states.
setMaxDeadtime( ); repeat {
resetDetect( ); runPWM( ); shortenDeadtime( ); } until (shootThroughDetected( )==1) expand Deadtime( ); As used in this algorithm, the setMaxDeadtime( ) function sets the high-side and low-side signal delays so that the dead time between high-side and low-side pulses is at the predetermined maximum value. The shortenDeadtime( ) function incrementally decreases the dead time, while the expandDeadtime( ) function increases the dead time by a predetermined amount.
resetDetect( ); runPWM( ); shortenDeadtime( ); } until (shootThroughDetected( )==1) expandDeadtime( ); while(distortion( )<C_THRESHOLD)
increaseDeadTime( ) decreaseDeadTime( ) If this algorithm were implemented, dead time would be reduced until unacceptable shoot-through is detected. At that point, dead time would be increased until performance was unacceptable. The dead time would then be reduced again. This algorithm searches for optimal relative channel timing by optimizing shoot-through current first, and audio performance second. Alternatively, it is possible to optimize for distortion first and shoot-through second, as shown by the following exemplary algorithm:
setMaxDeadtime( ) while(distortion( )>C_THRESHOLD)
decreaseDeadTime( ); if(shootThroughDetect( )==1)
expandDeadTime( ); While the exemplary methods described above are designed to make use of relatively direct measurements of shoot-through current and distortion, indirect measurements or metrics could be used as well. For example, in one embodiment, control signals having a 50% duty cycle could be generated. The FETs would then be turned on and turned off for equal amounts of time. In this situation, the output of the output stage would have no differential current (or DC offset.) If the relative channel timing varies, however, in a way that alters the 50% duty cycle at the output stage, each of the FETs will be turned on/off more than they are turned off/on. This difference in the amount of time the FETs are turned on/off will result in a differential current at the output of the output stage.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4554512 *Aug 27, 1984Nov 19, 1985Aerotech, Inc.Switching amplifier with MOSFET driver circuitUS6294954 *Jan 11, 2000Sep 25, 2001Audiologic, IncorporatedAdaptive dead time control for switching circuitsUS6373334 *Jun 12, 2000Apr 16, 2002Cirrus Logic, Inc.Real time correction of a digital PWM amplifierUS6737917 *Jan 18, 2001May 18, 2004Dlogix Co., Ltd.Digital power amplifierUS20040184627 *Mar 19, 2004Sep 23, 2004Kost Michael A.Systems and methods for protection of audio amplifier circuits* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7800437May 19, 2009Sep 21, 2010Silicon Laboratories Inc.Closed loop timing feedback for PWM switching amplifiers using predictive feedback compensationUS7859331May 19, 2009Dec 28, 2010Silicon Laboratories Inc.Predictive feedback compensation for PWM switching amplifiersUS8022756May 15, 2007Sep 20, 2011Qualcomm, IncorporatedOutput circuits with class D amplifierUS8194424May 7, 2008Jun 5, 2012Harman International Industries, IncorporatedAutomatic zero voltage switching mode controllerUS8471627Apr 27, 2010Jun 25, 2013St-Ericsson SaCross current minimizationUS8536938Aug 4, 2011Sep 17, 2013Qualcomm, IncorporatedOutput circuits with class D amplifierUS8633763Aug 4, 2011Jan 21, 2014Qualcomm IncorporatedOutput circuits with class D amplifierEP2249476A1 *Apr 28, 2009Nov 10, 2010ST-Ericsson SACross current minimisationWO2008144134A1 *Apr 14, 2008Nov 27, 2008Qualcomm IncOutput circuits with class d amplifierWO2010125066A1 *Apr 27, 2010Nov 4, 2010St-Ericsson Sa (St-Ericsson Ltd)Cross current minimisation* Cited by examinerClassifications U.S. Classification330/10International ClassificationH03F3/38Cooperative ClassificationH03F1/32, H03F2200/03, H03F2200/331, H03F3/217, H03F3/181European ClassificationH03F3/217, H03F3/181, H03F1/32Legal EventsDateCodeEventDescriptionMar 18, 2014ASAssignmentOwner name: D2AUDIO LLC, DELAWAREFree format text: CHANGE OF NAME;ASSIGNOR:D2AUDIO CORPORATION;REEL/FRAME:032463/0767Effective date: 20111223Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:D2AUDIO LLC;REEL/FRAME:032463/0447Owner name: INTERSIL AMERICAS LLC, CALIFORNIAEffective date: 20130329Oct 4, 2013FPAYFee paymentYear of fee payment: 8Sep 4, 2013FPAYFee paymentYear of fee payment: 8May 5, 2010ASAssignmentOwner name: MORGAN STANLEY & CO. INCORPORATED,NEW YORKFree format text: SECURITY AGREEMENT;ASSIGNORS:INTERSIL CORPORATION;TECHWELL, INC.;INTERSIL COMMUNICATIONS, INC. AND OTHERS;US-ASSIGNMENT DATABASE UPDATED:20100505;REEL/FRAME:24337/395Effective date: 20100427Free format text: SECURITY AGREEMENT;ASSIGNORS:INTERSIL CORPORATION;TECHWELL, INC.;INTERSIL COMMUNICATIONS, INC. AND OTHERS;REEL/FRAME:24337/395Free format text: SECURITY AGREEMENT;ASSIGNORS:INTERSIL CORPORATION;TECHWELL, INC.;INTERSIL COMMUNICATIONS, INC.;AND OTHERS;REEL/FRAME:024337/0395Owner name: MORGAN STANLEY & CO. INCORPORATED, NEW YORKOct 5, 2009FPAYFee paymentYear of fee payment: 4Mar 22, 2004ASAssignmentOwner name: D2AUDIO CORPORATION, TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TAYLOR, WILSON E.;ANDERSON, JACK B.;ROVNER, MICHAEL;AND OTHERS;REEL/FRAME:015123/0312Effective date: 20040322RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google