Source: http://www.google.com.tw/patents/US7263340
Timestamp: 2013-05-19 11:09:41
Document Index: 380380465

Matched Legal Cases: ['Application No. 0212737', 'Application No. 0212725', 'Application No. 0212729', 'Application No. 0212723', 'Application No. 0212735', 'Application No. 0212732']

�M�Q US7263340 - PLL circuit having a multi-band oscillator and compensating oscillation ... - Google �M�Q�j�M �Ϥ� �a�� Play YouTube �s�D Gmail ���ݵw�� ��h »�i���M�Q�j�M | �������� | �n�J�i���M�Q�j�M�M�QA semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance...http://www.google.com.tw/patents/US7263340?utm_source=gb-gplus-share�M�Q US7263340 - PLL circuit having a multi-band oscillator and compensating oscillation frequency���}��US7263340 B2�X���������v�ӽЮѽs��11/491,978�o�G���2007�~8��28���ӽФ��2006�~7��25�� �u���v���2002�~5��31����L���}�M�Q��US7269402US20060258312US20060258313�o��HToshiya UozumiSatoshi TanakaMasumi KasaharaHirotaka OosawaYasuyuki KimuraRobert Astle Henshaw��M�Q�v�HRenesas Technology CorporationTtp Com Limited ���M�Q������455/255455/258455/252.1331/44331/176��ڱM�Q������H03L7/187H03L7/099H03L7/10H04B1/40H04B1/06 �X�@����H03L7/087H03L1/02H03L7/187H03L7/099H03L7/183 �ڬw������H03L7/099H03L7/187H03L7/183H03L7/087H03L1/02�ѦҤ��m�M�Q�ޥ� (40)�D�M�Q�ޥ� (1)�Q�H�U�M�Q�ޥ� (3)�~���s�����M�Q�ӼЧ� ���M�Q�ӼЧ��M�Q����T�� �ڬw�M�Q��PLL circuit having a multi-band oscillator and compensating oscillation frequencyUS 7263340 B2�K�n A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.
CROSS-REFERENCES TO RELATED APPLICATIONS The following applications, including this one, are being filed concurrently, and the disclosure of the other applications are incorporated by reference into this application in their entirety for all purposes:
U.K. Patent Application No. 0212737.1 (filed on May 31, 2002) entitled ��APPARATUS FOR RADIO TELECOMMUNICATION SYSTEM AND METHOD OF BUILDING UP OUTPUT POWER��
U.K. Patent Application No. 0212725.6 (filed on May 31, 2002) entitled ��A COMMUNICATION SEMICONDUCTOR INTEGRATED CIRCUIT, A WIRELESS COMMUNICATION APPARATUS, AND A LOOP GAIN CALIBRATION METHOD��
U.K. Patent Application No. 0212729.8 (filed on May 31, 2002) entitled ��TRANSMITTER AND SEMICONDUCTOR INTEGRATED CIRCUIT FOR COMMUNICATION��
U.K. Patent Application No. 0212723.1 (filed on May 31, 2002) entitled ��SEMICONDUCTOR INTEGRATED CIRCUIT FOR COMMUNICATION, RADIO-COMMUNICATIONS APPARATUS, AND TRANSMISSION STARTING METHOD��
U.K. Patent Application No. 0212735.5 (filed on May 31, 2002) entitled ��SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR COMMUNICATION��
U.K. Patent Application No. 0212732.2 (filed on May 31, 2002) entitled ��APPARATUS FOR MOBILE COMMUNICATION SYSTEM��
BACKGROUND OF THE INVENTION The present invention relates to a technique effectively applied to a PLL (Phase Locked Loop) circuit in which a VCO (Voltage Controlled Oscillator) is provided and an oscillation frequency can be switched. For example, the present invention relates to a technique effectively used in a radio frequency integrated circuit device provided with a PLL circuit that generates an oscillation signal having a predetermined frequency to be synthesized with a received signal or a transmitted signal in a mobile communication device such as a mobile phone or the like capable of receiving/transmitting signals in multiple bands. Furthermore, the present invention relates to a technique effectively applied to a wireless communication system using this radio frequency integrated circuit device.
SUMMARY OF THE INVENTION In recent years, with respect to the mobile phone as described above, a triple-band mobile phone has been demanded, which can process a signal of PCS (Personal Communication System) having a frequency band of 1900 MHz in addition to the GSM and the DCS, and a technique concerning such a triple-band mobile phone has been also proposed. It can be expected that demands for a mobile phone capable of handling more bands will be emphasized in the future.
BRIEF DESCRIPTIONS OF THE DRAWINGS FIG. 1 is an explanatory diagram showing the characteristic of the VCO oscillation frequency vs the VCO tuning voltage of a VCO having multiple oscillation bands, in a method of minimizing the influence which the fluctuation of the VCO oscillation frequency due to temperature change exerts on the time of an automatic band selection according to an embodiment of the present invention.
DESCRIPTIONS OF THE PREFFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail based on the accompanying drawings. Note that components having the same function are denoted by the same reference symbol throughout all the drawings for describing the embodiments, and the repetitive description thereof will be omitted.
In the PLL circuit, the oscillation frequency of the VCO fluctuates depending on temperature. Therefore, the calibration table constructed by the automatic calibration at the time of the switch-on comes to no optimum one due to the temperature change. Thus, the PLL circuit serving as the premise technique of the present invention has a possibility that it can not select the appropriate band. For its solution, in the present invention, two methods, namely, ��1-1. A method of minimizing the influence exerted by the fluctuation of a VCO oscillation frequency due to temperature change at the time of an automatic band selection�� and ��1-2. A method of performing a recalibration�� are implemented.
�GfVCO/�GT=−2KVCO(�GVB/�GT) (1),
where �GfVCO, KVCO, �GVB, and �GT are defined as the change in the oscillation frequency of the RFVCO 1, the sensitivity of the oscillation frequency vs the tuning voltage of the RFVCO 1, the change in the DC voltage of the DC voltage source 9, and the temperature change, respectively.
For example, if the voltage value of the DC voltage source is constant (e.g., 1.5V) and has no temperature dependence like the PLL circuit according to the premise technique of the present invention, then when the temperature at the time of the switch-on is −25�X C. as shown in FIG. 4, 3750 MHz is counted and memorized as the calibration table 16 of the band 8. Thereafter, when the temperature rises to +75�X C., 3750 MHz is equivalent to the tuning voltage Vtune of 2V. This produces the same result as the case where the voltage value of the DC voltage source is 2V on such the environment that the temperature at the time of the switch-on is +75�X C.
Similarly, such the environment that the temperature at the time of the switch-on is +75�X C. and thereafter the temperature falls to −25�X C. is equal to the case where the temperature at the time of the switch-on is −25�X C. and where the voltage value of the DC voltage source is 1V. More specifically, this corresponds a 1V fluctuation of the DC voltage source equivalently from 1V to 2V due to temperature change. In the constitution of the PLL circuit according to the premise technique of the present invention, the tuning voltage Vtune at the time of the normal operation operates by using the voltage value of the DC voltage source as a base point. Therefore, that the DC voltage source fluctuates large means that the base point of the tuning voltage Vtune at the time of the normal operation fluctuates large.
Contrary to this, if a temperature characteristic is thought to be given to the voltage value of the DC voltage source 9 like the PLL circuit of the present invention, as shown in FIG. 5, in the case where the temperature at the time of the switch-on is −25�X C. and where the VCO tuning voltage is 1.25V at the time of this, 3725 MHz is counted and memorized as the calibration table 16 of the band 8. If the temperature rises to +75�X C., the 3725 MHz corresponds to the tuning voltage Vtune of 1.75V. This means the environment in which the temperature at the time of the switch-on is +75�X C., and results in the same as the case where the voltage value of the DC voltage source 9 is 1.75V.
Similarly, such an environment that the temperature at the time of the switch-on is +75�X C. and the VCO tuning voltage is 1.75V at the time of this and thereby the temperature falls to −25�X C. is equal to the case where the temperature at the time of the switch-on is −25�X C. and where the voltage value of the DC voltage source 9 is 1.25V. More specifically, this corresponds to a 0.5V fluctuation of the DC voltage source 9 from 1.25V to 1.75V due to the temperature change. This shows that the fluctuation in the base point of the tuning voltage Vtune becomes smaller in comparison to the case where the DC voltage source has no temperature characteristic. In this case, �GfVCO, KVCO, �GVB, and �GT are −50 MHz, 50 MHz/V, 0.5V, and 100 deg, respectively, each of which satisfies the expression (1).
V3=R3�PI3=R3�PI2=R3(V1−VBE)/R2 (4)
dV3/dT=−d(R3/R2)��dVBE/dT (6)
(1) In the case where the frequency of the PLL circuit is set, the band of the VCO oscillation frequency is selected based on the previous calibration table 16. The recalibration is performed relative to only this selected band. The configuration of the PLL circuit used in this method is the same as that of the PLL circuit shown in FIG. 2. The timing diagram in this case is shown in FIG. 7. In the aforementioned calibration at the time of the switch-on shown in FIG. 3, the counting operations are performed relative to all of the bands and the total time is Ta+16��Tb. Meanwhile, in this case shown in FIG. 7, a counting operation is performed relative to only one band and the total time is Ta+Tb. After the counting, the error of the previous calibration table 16 is calculated and the calculated error is added to the calibration tables 16 of all bands.
Although not particularly limited, the PLL circuit in this embodiment is a PLL circuit using, for example, eight band switches of the bands 0 to 7 and controlling an IFVCO having the characteristic of the VCO oscillation frequency vs the VCO tuning voltage, wherein a target frequency has 320 MHz in the IF (Intermediate Frequency) band and a variable range is ��4 MHz as shown in FIG. 10.
Although the PLL circuit in this embodiment has the same configuration as that shown in FIG. 2, the PLL circuit in this embodiment also has a configuration as shown in FIG. 11 in order to be applied to an intermediate frequency band. More specifically, the PLL circuit is constituted such that the RFVCO 1 is replaced with an IFVCO 1 a, and a target frequency of a memory circuit 12 a is inputted to one of the inputs of a comparator 13 a as a fixed value, and a counter value of a frequency counter 11 a is inputted to the other of the inputs of the comparator 13 a. FIG. 11 is shown in which ��a�� is added to each of reference symbols (numerals) of components corresponding to the components shown in FIG. 2 and each component of the PLL circuit has the same function. Therefore, detailed descriptions thereof will be omitted here.
Also, in this method, the decision speed of the PLL circuit can be made to speed up, by setting a constant intermediate voltage (0.5��Vcc) in the LPF 7 a of the PLL circuit prior to the measurement thereof. More specifically, since the intermediate voltage is set at the VCO tuning voltage and the two comparators 37 and 38 are used, it is possible to determine whether the band number of the IFVCO 1 a should be incremented or decremented. When the VCO tuning voltage is too low, the band number is incremented and when the VCO tuning voltage is too high, the band number is decremented.
VCO tuning sensitivity=�Gfn/�GV (7)
For example, as shown in FIG. 29, the VCO tuning sensitivity of the RFVCO 1 increases as the band becomes higher. Assuming that the tuning sensitivity of the band 0 is �Gf0/�GV and the tuning sensitivity of the band 15 is �Gf15/�GV, the relation of (�Gf15/�GV)>(�Gf0/�GV) can be obtained. Therefore, since the loop bandwidth of the PLL circuit is changed depending on the selected band, the designs of the LPF 7 and the like of the PLL circuit become difficult. More specifically, this is because the PLL bandwidth is determined depending on the tuning sensitivity of the RFVCO 1, and the variable division ratio of the RFVCO 1, and the current value of the charge pump 6, and the frequency characteristic of the LPF 7.
Meanwhile, the oscillation frequency of the RFVCO 1 is set at 3840 to 3980 MHz in the case of the GSM, at 3580 to 3730 MHz in the case of the DCS, and at 3860 to 3980 MHz in the case of the PCS, respectively. This frequency is divided into one-fourth in the divider circuit 62 in the case of the GSM or divided into half in the cases of the DCS and the PCS, and then is supplied to the mixer 64. In the mixer 64, a signal is outputted which corresponds to the difference between this frequency and the frequency of the oscillation signal for transmission sent from the TXVCO 54, and the transmission PLL circuit is operated so as to correspond to the frequencies of the difference signal and the modulation signal. In the above-mentioned embodiment, it has been described that a frequency band, at the time when the VCO tuning voltage has first a value equal to or less than the threshold corresponding to the target frequency, is selected. However, a frequency band, at the time when the VCO tuning voltage has first a value less than the threshold corresponding to the target frequency, may be selected. Note that, in the present application, ��a value equal to or less than the threshold�� also includes ��a value less than the threshold��.
�M�Q�ޥ� �ޥΪ��M�Q�ӽФ���o�G��� �ӽЪ��M�Q�W��US47468791986�~8��28��1988�~5��24��Astec International, Ltd., A Corp. Of Hong KongDigitally temperature compensated voltage-controlled oscillatorUS48475691987�~2��20��1989�~7��11��Wavetek CorporationAutomatic calibration system for a voltage control oscillatorUS49069441988�~8��17��1990�~3��6��Rockwell International CorporationIntegrator controlled time compensated clock oscillatorUS49214671988�~5��31��1990�~5��1��Multitone Electronics PlcLocal oscillators for radio receiversUS50362951990�~7��30��1991�~7��30��Mitsubishi Denki Kabushiki KaishaFrequency synthesizer allowing rapid frequency switchingUS51825281991�~11��12��1993�~1��26��Ilatron Ltd.Frequency synthesizer having microcomputer supplying analog and digital control signals to VCOUS52764521992�~6��24��1994�~1��4��Raytheon CompanyScan compensation for array antenna on a curved surfaceUS55924901995�~1��20��1997�~1��7��Arraycomm, Inc.Spectrally efficient high capacity wireless communication systemsUS56253251995�~12��22��1997�~4��29��Microtune, Inc.System and method for phase lock loop gain stabilizationUS58151981996�~5��31��1998�~9��29��Georgia Tech Research CorporationMethod and apparatus for analyzing an image to detect and identify defectsUS58390591994�~5��13��1998�~11��17��Nokia Telecommunications OyMethod for starting a radio transmitter, and a radio transmitter using a start-up estimated control voltage needed for locking onto selected output frequencyUS59125951997�~12��16��1999�~6��15��Ma; John Y.Digitally temperature compensated voltage-controlled oscillator tunable to different frequency channelsUS59743551997�~3��31��1999�~10��26��Fujitsu LimitedAutomatic time series pattern creating methodUS61415671999�~6��7��2000�~10��31��Arraycomm, Inc.Apparatus and method for beamforming in a changing-interference environmentUS61753311999�~4��20��2001�~1��16��Sonetech CorporationMethod and apparatus for determining and forming delayed waveforms for forming radio frequency transmitting or receiving beams for an array of radio frequency transmitting or receiving elementsUS61779061999�~4��1��2001�~1��23��Arraycomm, Inc.Multimode iterative adaptive smart antenna processing method and apparatusUS63512371999�~11��29��2002�~2��26��Metawave Communications CorporationPolarization and angular diversity among antenna beamsUS63661772000�~2��2��2002�~4��2��Tropian Inc.High-efficiency power modulatorsUS63777841999�~2��9��2002�~4��23��Tropian, Inc.High-efficiency modulation RF amplifierUS67443242003�~4��14��2004�~6��1��Cisco Technology, Inc.Frequency synthesizer using a VCO having a controllable operating point, and calibration and tuning thereofUS68038302002�~6��21��2004�~10��12��Texas Instruments IncorporatedPhase-locked loop and method for automatically setting its output frequencyUS68361922002�~1��16��2004�~12��28��Microtune (San Diego), Inc.Methods and apparatuses for tuning voltage controlled oscillatorsUS68501252001�~8��15��2005�~2��1��Gallitzin Allegheny LlcSystems and methods for self-calibrationUS68710492003�~3��13��2005�~3��22��Cognio, Inc.Improving the efficiency of power amplifiers in devices using transmit beamformingUS69036132002�~12��20��2005�~6��7��Cypress Semiconductor CorporationVoltage controlled oscillatorUS70385522003�~10��7��2006�~5��2��Analog Devices, Inc.Voltage controlled oscillator having improved phase noiseUS71033372003�~2��26��2006�~9��5��Hitachi, Ltd.PLL circuit having a multi-band oscillator and compensating oscillation frequencyUS200100145931999�~2��9��2001�~8��16��Panasonic CorporationHigh-efficiency modulating rf amplifierUS200100175722000�~12��12��2001�~8��30��Sony United Kingdom LimitedChanging the output frequency of a phase-locked loopUS200200365452001�~8��13��2002�~3��28��Fridi Ahmed RedaPhase lock loopUS200200750802000�~12��13��2002�~6��20��Lucent Technologies Inc.VCO gain self-calibration for low voltage phase lock-loop applicationsUS200301711052002�~3��6��2003�~9��11��Dunworth Jeremy D.Calibration techniques for frequency synthesizersUS200401021762003�~10��23��2004�~5��27��Hayashi NorioSemiconductor integrated circuit device and wireless communication systemEP1047196A11999�~4��21��2000�~10��25��SGS-THOMSON MICROELECTRONICS S.r.l.Method and circuit for minimizing glitches in phase locked loopsEP1115206A22000�~12��21��2001�~7��11��Nokia Mobile Phones Ltd.Voltage controlled oscillator assemblyEP1189351A22001�~8��17��2002�~3��20��Texas Instruments IncorporatedMethod for tuning a voltage controlled oscillatorGB2361119A �W�٤���GB2361122A �W�٤���GB2370435A �W�٤���JP2002111492A �W�٤����D�M�Q�ޥ��ѦҤ��m1Weili et al., IEEE 0018-926x/01, vol. 49, No. 10, Oct. 2001.�Q�H�U�M�Q�ޥ� �ޥΥ��M�Q�ӽФ���o�G��� �ӽЪ��M�Q�W��US76091212008�~3��28��2009�~10��27��International Business Machines CorporationMultiple status e-fuse based non-volatile voltage control oscillator configured for process variation compensation, an associated method and an associated design structureUS76753782008�~5��2��2010�~3��9��International Business Machines CorporationMultiple status e-fuse based non-volatile voltage control oscillator configured for process variation compensation, an associated method and an associated design structureUS80447262009�~3��17��2011�~10��25��Qualcomm IncorporatedSystems and methods for self testing a voltage controlled oscillator������l�Ϥ�Google ���� - Sitemap - USPTO �j�q�U�� - ���p�v�F�� - �A�ȱ�� - ���� Google �M�Q - �N���^�X��ƬO�Ѭ��ӷ~�M�Q��Ʈw (IFI CLAIMS Patent Services) ����©2012 Google