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Timestamp: 2014-10-01 13:34:58
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Patent US5748201 - Semiconductor memory device having multiple modes that allow the cell array ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA semiconductor memory device including a serial I/O buffer; DRAM cells; and SAM cells arranged in line, the SAM cells corresponding to the DRAM cells in one row. In the device in a first mode, the SAM cells are divided into N first portions each having boundaries, data stored in the SAM cells being...http://www.google.com/patents/US5748201?utm_source=gb-gplus-sharePatent US5748201 - Semiconductor memory device having multiple modes that allow the cell array to be divided into a variable number of portionsAdvanced Patent SearchPublication numberUS5748201 APublication typeGrantApplication numberUS 08/405,497Publication dateMay 5, 1998Filing dateMar 16, 1995Priority dateMar 16, 1994Fee statusLapsedAlso published asEP0673036A2, EP0673036A3, US5890197Publication number08405497, 405497, US 5748201 A, US 5748201A, US-A-5748201, US5748201 A, US5748201AInventorsShigeki NagasakaOriginal AssigneeKabushiki Kaisha ToshibaExport CitationBiBTeX, EndNote, RefManPatent Citations (9), Non-Patent Citations (3), Referenced by (4), Classifications (9), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor memory device having multiple modes that allow the cell array to be divided into a variable number of portionsUS 5748201 AAbstract A semiconductor memory device including a serial I/O buffer; DRAM cells; and SAM cells arranged in line, the SAM cells corresponding to the DRAM cells in one row. In the device in a first mode, the SAM cells are divided into N first portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer sequentially until the SAM cells in the boundaries of the first portions are transferred to the serial I/O buffer. In a second mode, the SAM cells are divided into M (N>M) second portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer sequentially until the SAM cells in the boundaries of the second portions are transferred to the serial input output buffer. The semiconductor memory device further includes a circuit for detecting changes from the first mode to the second mode and from the second mode to the first mode. The semiconductor memory device further includes a circuit for generating first and second signals. When the mode is changed from the first mode to the second mode, the circuit generates the first signal. When the mode is changed from the second mode to the first mode the circuit generates the second signal.
What is claimed is: 1. A semiconductor memory device comprising:a serial input output buffer; a RAM cell array having a plurality of DRAM cells arranged in a matrix; and a SAM cell array having a plurality of SAM cells arranged in a line, the SAM cells corresponding to the DRAM cells in one row, wherein in a first mode, the SAM cell array is divided into N first portions each having boundaries, data stored in the SAM cells being transferred to the serial input output buffer sequentially until the SAM cells in the boundaries of the first portions are transferred to the serial input output buffer, in a second mode, the SAM cell array is divided into M (N>M, where N and M are positive integers) second portions each having boundaries, data stored in the SAM cells being transferred to the serial input output buffers sequentially until the SAM cells in the boundaries of the second portions are transferred to the serial input output buffer, and the semiconductor memory device further comprises a detecting means for detecting changes from the first mode to the second mode and from the second mode to the first mode, and a controlling means for receiving an output of the detecting means and controlling the operation of the SAM cell array in a composite mode made up of a split transfer SRT mode, a CBRS (CAS before RAS refresh stop) mode, and a CBR (CAS before RAS refresh option reset) mode on the basis of the output of the detecting means. 2. The semiconductor memory device as defined in claim 1, further comprising:a generating means for generating first and second signals, wherein when a mode is changed from the first mode to the second mode, the generating means generates the first signal, and when the mode is changed from the second mode to the first mode the generating means generates the second signal. 3. The semiconductor memory device as defined in claim 1, wherein when a mode is changed from the first mode to the second mode, the data stored in the SAM cells is transferred continuously to the serial input output buffer in spite of the SAM cells in the boundaries of the first portions.
4. A semiconductor memory device comprising:a serial input output buffer; a RAM cell array having a plurality of DRAM cells arranged in a matrix; and a SAM cell array having a plurality of SAM cells arranged in a line, the SAM cells corresponding to the DRAM cells in one row, wherein the SAM cell array is divided into a plurality of portions each having boundaries, data stored in the SAM cells being transferred to the serial input output buffer sequentially until the SAM cells in the boundaries are transferred to the serial input output buffer, a division of the SAM cell array is changed in response to externally supplied signals, and the semiconductor memory device further comprises a detecting means for detecting a change in the division of the SAM cell array, and a controlling means for receiving an output of the detecting means and controlling the operation of the SAM cell array in a composite mode made up of a split transfer SRT mode, a CBRS (CAS before RAS refresh stop) mode, and a CBR (CAS before RAS refresh option reset) mode on the basis of the output of the detecting means. 5. The semiconductor memory device as defined in claim 4, further comprising:a generating means for generating first and second signals, wherein when the division of the SAM cell array is increased the generating means generates the first signal, and when the division of the SAM cell array is decreased the generating means generates the second signal. 6. The semiconductor memory device as defined in claim 5, wherein when the generating means generates the second signal, the data stored in the SAM cells is transferred continuously to the serial input output buffer in spite of the SAM cells in the boundaries of the previous division.
7. A method for controlling a semiconductor memory device of the type having:a serial input output buffer, a RAM cell array having a plurality of DRAM cells arranged in a matrix; and a SAM cell array having a plurality of SAM cells arranged in a line, the SAM cells corresponding to the DRAM cells in one row, wherein the SAM cell array is divided into a plurality of portions each having boundaries, data stored in the SAM cells being transferred to the serial input output buffer sequentially until the SAM cells in the boundaries are transferred to the serial input output buffer, and a division of the SAM cell array is changed in response to externally supplied signals, the method comprising the steps of:(a) in a first mode,dividing the SAM cell array into N of the portions; and continuously transferring data from the SAM cells in the SAM cell array while comparing a first address of the SAM cells from which data is transferred and a second address of the SAM cells at the boundaries; (b) for a predetermined time period after a change from the first mode to a second mode,continuously transferring data from the SAM cells without comparing the first address and the second address; and (c) in the second mode after the lapse of the predetermined time period,dividing the SAM cell array into M (N>M, where N and M are positive integers) of the portions; and continuously transferring data from the SAM cells in the SAM cell array while comparing the first address and the second address. Description
FIG. 1 is the configuration diagram of the dual-port semiconductor memory. In FIG. 1, data in the dynamic random access memory cells (512�512�4 random access memory cell array) are transferred to registers in an upper SAM or registers in a lower SAM through transfer gate. The data in the registers in the upper SAM and the lower SAM are selected by serial selectors 87 and transferred to an external device (not shown). An address to select one of the register in the upper SAM and the lower SAM by the serial selectors 87 is transferred from a serial address counter 80.
The data readout from the registers of the SAM under the split transfer mode is initiated at the register addressed by a top address point ("TAP") address which has been set in this split transfer cycle (SRT cycle) and the data readout is completed at the register indicated by a boundary address which has been previously set.
As shown in FIG. 1, a TAP address is transferred to a first internal address register 81 in the serial address counter 80 from a column address buffer (register) 71 of 9 bits through first transfer gate 810 while a column address strobe signal/CAS is at the low level.
Boundary addresses are transferred to a boundary address register 86 from a row address buffer (9 bits) 60 when a row address strobe signal/RAS is changed to the low level.
The column address or the TAP address stored in the second internal address register 82 is transferred to the third internal address register in the third internal address register 83 when receiving a control signal FSCT. This control signal FSCF is generated by the first comparator 84 when a first serial clock SC is received after the SAM counter address SAi is agreed with the boundary address BDAi.
In controlling the SAM counter address in the SAM counter address register 72, with a SAM counter address (SAi) is incremented by "1" such as SAi=(SAi+1) according to receive the serial clock SC under the normal operation mode, not under the split transfer mode.
The control signal NLM1SC is used for a WRAP AROUND mode which is the normal operation mode, not under the split transfer mode. The control signal NLM1SC is changed from the low level to the high level when the SAM counter address (SAi) 72 is agreed with the boundary address--1. By sing the control signal NLM1SC, the control signal QSF is changed within two cycles.
The control signal NLM1SC is changed to the high level when the serial clock SC is equal to the cycle of the boundary address--1, for example at the timing T4 shown in FIG. 3. In this case, data in the memory cells in the upper RAM or the lower RAM are latched into the registers in one of the upper SAM and the lower SAM indicated by the control signal QSF. The data stored in the registers in the SAM are transferred to an external device (not shown) from the SC cycle in which the serial clock SC is agreed with the boundary address.
On the contrary, when a first serial clock 1st-SC after the boundary address is agreed with the address stored in the SAM counter address register 72 is received at the first comparator 84 after the SRT2 cycle, this 1st-SC is the first SC for the first split transfer SRT1 cycle and this serial clock SC (255) is equal to the boundary address for the next split transmission SRT2 cycle. Accordingly, the value of the control signal QSF must be changed and a next TAP address (100) for the next split transfer SRT2 cycle must be set into the third internal address register 83. In this case, there is no serial clock SC which is a boundary address--1. In other words, the control signal NLM1SC has no high level pulse after the SRT2 (100) cycle. This is a problem. In order to avoid this problem, a control signal ATAP is used in the conventional dual-port semiconductor memory device.
(1) CBRS mode is a/CAS before/RAS refresh stop register set mode. A boundary address can be changed in the CBRS mode.
(3) CBR mode is a/CAS before/RAS refresh option reset mode (CBR mode). In the CBR mode, registers in a SAM are divided into two SAM, each of which is a same memory size and a boundary address is reset for the two SAM. For example, a SAM address is 0 to 511, the address of the registers in the first SAM is 0 to 255, and the address of the registers in the second SAM is 256 to 511. In the CBR mode, the addresses 255 and 511 are set as the boundary addresses.
With this type of a conventional memory, irregularities are produced in one part of the composite modes CBRS (/CAS before/RAS refresh stop register set), SRT (split transfer), and CBR (/CAS before/RAS refresh option reset).
In FIG. 5, boundary addresses can be changed only in the CBRS and CBR cycles. In the case of the CBRS cycle a new boundary address is effective following to the split transfer SRT cycle after the CBRS cycle. For this reason, the internal boundary address is changed with a new boundary address after a falling edge (at timing T50) of the row address strobe/RAS for the SRT2 cycle in the example 1 shown in FIG. 5.
As shown in FIG 5, the boundary addresses are 255, 511 (two division) in the SRT1 cycle. Following the CBRS cycle, the boundary addresses are changed to new boundary addresses, 127, 255, 383, and 511 (four division) at the timing T50 after the SRT2 cycle. Thus, the boundary addresses are changed only after the CBRS cycle and the CBR cycle.
In the Example 3 shown in FIG. 7, the boundary addresses for the SRT1 cycle are 127, 255, 383, and 511 which are stored in the boundary address register 86. The level of the control signal QSF is changed to the high level from the low level at the timing T70 after the serial clock SC(127) shown as "*f" in FIG. 7 is received, because the SAM counter address (127) in the SAM counter address register 72 is equal to the boundary address (127). Subsequently, the SRT2 cycle and the CBR cycle follow. In the case of the CBR cycle, the boundary addresses (127, 255, 383, and 511 for the four division) are changed to new boundary addresses (255 and 511 for the two division) at the timing 171 immediately following the CBR cycle.
Accordingly, even if the boundary address is changed in the CBR cycle, the next serial clock (383) designated by the reference "*g" is not received before the timing T73, so that the erroneous of the control signal QSF is occurred at the timing T74 at which the first serial clock SC (383) is received. At the timing 174, the level of the control signal QSF must not be changed to the low level.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is, with due consideration to the drawbacks of such conventional dual-port semiconductor memory devices, to provide a dual-port semiconductor memory device wherein the selection of SAM parts in a SAM is reliably controlled in a composite mode made up of the split transfer SRT mode, the CBRS mode, and the CBR mode.
As a preferred embodiment of the present invention, a semiconductor memory device includes: a serial input output buffer; a RAM cell array having a plurality of DRAM cells arranged in matrix; and a SAM cell array having a plurality of SAM cells arranged in line, the SAM cells corresponding to the DRAM cells in one row; wherein: in a first mode, the SAM cell array is divided into N first portions each having boundaries, data stored in the SAM cells being transferred to the serial input output buffer sequentially until the SAM cells in the boundaries of the first portions are transferred to the serial input output buffer; and in a second mode, the SAM cell array is divided into M (N>M, where N, M are positive integers) second portions each having boundaries, data stored in the SAM cells being transferred to the serial input output buffer sequentially until the SAM cells in the boundaries of the second portions are transferred to the serial input output buffer;
a counter comprising a first counter register, a second counter register, a third counter register, and a fourth counter register, the first counter register receiving a TAP address and storing the TAP address, the second counter register and the fourth counter register receiving the TAP address from the first counter register and storing the TAP address, and the third counter register receiving the TAP address from the second counter register and generating a current address obtained by incrementing the TAP address when receiving a serial clock and transferring the current address to the serial selector;
a counter comprising a first counter register, a second counter register, a third counter register; and a fourth counter register,
FIG. 8D is a configuration diagram of a row decoder in the semiconductor memory device shown in FIG. 8A.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Other features of this invention will become apparent in the course of he following description of exemplary embodiments which are given for illustration of the invention and are not intended to be limiting thereof.
A dual-port semiconductor memory device having a split transfer unction as an embodiment of the present invention used for graphics will now be explained.
The dual-port semiconductor memory device comprises a plurality of RAM cell arrays (including 512�512�4 RAM cell arrays), each RAM cell array including a plurality of dynamic random access memory (DRAM) cells arranged in a matrix which is divided into the two parts (an upper part 1--1 and a lower part 1-2), a column decoder(CD) 2, a sense amplifier(S/A) 3, a SAM divided into the upper SAM 4 and the lower SAM 5, two transfer gates 6 and 7, serial selectors 8 and 9, a row decoder 16, column address buffer (register) 13, a row address buffer 14, a refresh counter 15, a boundary address register 17, a serial address counter 12, a QSF circuit 11 for generating a control signal QSF, a control signal generator 18-1, a timing generation circuit (a timing generator) 18-2, a SAM switch 5, a serial output buffer 19-1, a serial input buffer 19-2, and a RAM port (input/output buffer).
In order to simplify the explanation of the present invention, the DRAM cells in the cell array 1 are divided into the upper part 1--1 and the lower part 1-2. The SAM is also divided into two parts, an upper SAM 4, and a lower SAM 5. The number of registers in the SAM is 512. Therefore the registers in the SAM are addressed by the SAM addresses of 512 bits (0 to 511). A control signal SC(n) indicates the n-th register in the SAM, and a SRT(m) indicates a split transfer mode or cycle having a tap address of m.
For example, memory cells CELL1 and CELL2 connected to a word line WL1 are selected by the row decoder 16. Bit lines BL1,/BL1, BL2, and /BL2 are equalized by the equalizer EQ 34. The data in the memory cells CELL1 and CELL2 selected by the row decoder 16 are transferred to bit lines BL1 and /BL1 which are selected through column selection lines CSL1 by the column decoder 2.
The sense amplifier (S/A) 3 includes two P channel MOS transistors (PMOS pair) connected between bit lines BL1 and /BL1, and BL2 and /BL2 in series and two N type MOS transistors (NMOS pair) connected between the bit lines BL1 and /BL1, and BL2 and /BL2 in series. Both sides of the PMOS pair are connected to the bit lines BL1 and /BL1, and BL2 and /BL2. Both sides of the NMOS pair are also connected to the bit lines BL1 and /BL1, and BL2 and /BL2. An intermediate point between the PMOS pair is connected to a control signal SAP line. An intermediate point between the NMOS pair is connected to a control signal/SAN line. Both gates of the PMOS transistor and the NMOS transistor are connected to the bit line/BL1 and /BL2. Both gates of the PMOS transistor and the NMOS transistor are connected to the bit line BL1 and BL2.
FIG. 8C is a sense amplifier driver (SAD) 33 for the sense amplifier (S/A) 3 in the dual-port semiconductor memory device shown in FIG. 8B. The operation of the sense amplifier driver SAD33 is controlled by a control signal SAD transferred from the timing generator 18-2. FIG. 8D is a configuration diagram of a row decoder in the dual-port semiconductor memory device shown in FIG. 8A. A row address (RAi) from the row address buffer 14 is received by the row decoder 16 in order to select one of the word lines WL1, WL2, WL3 . . .
A split transfer under the split transfer mode is a mode in which the memory cells in a row in the RAM cell array 1 are divided into the upper part 1--1 and the lower part 1-2. The data stored in the registers in the upper SAM 4 and the lower SAM 5 in the SAM are transferred sequentially to the external device through the serial output buffer 19-1, alternately. In a normal readout transfer, synchronization of the timing of the data transfer from the RAM cell array 1 to the SAM 4 and 5 and the timing of the input of a serial clock SC is very strict so that the data output from the SAM occurs without interruption because next transfer data must be transferred to the registers in the SAM from the memory cells in a next row while an address pointer indicating a readout position in the registers in the SAM returns to a start address position in the registers of the SAM.
The registers in the upper SAM 4 and the lower SAM 5 are divided into 2n parts (where n=1, 2, 3, . . .) by using boundary addresses so that the data read out from the registers in the upper SAM 4 and the lower SAM 5 are efficiently displayed on the screen. In the case where the data readout from the registers in the upper SAM 4 and the lower SAM 5 are in a continuous split transfer mode, a pointer indicating an address of a register in the upper SAM 4 and the lower SAM 5 jumps to another register in the SAM as a next data readout position indicated by a next TAP address for a next split transfer after a pointer indicating the register in the upper SAM 4 and the lower SAM 5 as a readout position reaches a boundary address of the current split transfer.
In FIG. 8A, data stored in the memory cells of the upper part 1-2 or the lower part 1-2 in a row in the RAM 1 are transferred to registers in the upper SAM 4 or in the lower SAM 5 through the transfer gate 6 or the transfer gate 7. The data in the registers in the upper SAM 4 and the lower. SAM 5 are selected by the serial selector 8 or 9 and transferred to the external device (not shown). An address to select one of the register in the upper SAM 4 and the lower SAM 5 is transferred from a serial address counter 12 to the serial selectors 8 and 9.
As shown in FIG. 8A, a TAP address is transferred to first internal address register 25 in the serial address counter 12 from the column address register 13 of 9 bits through first transfer gates 26 while a column address strobe signal/CAS is changed to the low level.
Boundary addresses are transferred to a boundary address register 17 from a row address buffer (9 bits) 14 when a row address strobe signal/RAS is changed to the low level.
FIG. 11C shows a detailed configuration diagram of the second comparator 28. The control signal QSF is generated by comparing the SAM counter address (SAi, where i=0, 1, . . . ,8) stored in the SAM counter address register 20, the boundary address (BDAi, where i=0, 1, . . . ,8) stored in the boundary address register 17, and a TAP address (AiCZ or AiCQ, where i=0, 1, . . . ,8) stored in the first internal address register 25.
In controlling the SAM counter address stored in the SAM counter address register 20, with a SAM counter address (SAi) is incremented by "1" such as SAi=(SAi+1) according to receive the serial clock SC at a counter section 21-1 in the third internal address register circuit 21 under the normal operation mode, not under the split transfer mode.
In FIGS. 8A, 9, and 10, the TAP address is transferred to the first internal address register 25 in the serial address counter 12 from the column address register 13 of 9 bits through first transfer gate 26 while a column address strobe signal/CAS is changed to the low level.
A boundary address transferred from the row address buffer (9 bits) 14 is transferred to a boundary address register 17 when a row address strobe signal/RAS is at the low level.
(3) the CBR mode is a "/CAS before/RAS refresh option reset mode" (CBR mode).
The timing generator 18-2 receives control signals, a row address strobe/RAS, a column address strobe/CAS, a special function control/DSF, a serial clock SC, a serial enable/SE, a write per bit/ a write enable/WB and /WE, a data transfer/output enable/DT and /OE, and then generates control signals a CBR for indicating the CBR mode, a CBRS for indicating the CBRS mode, a SRT for indicating the SRt mode, a SAD for driving the sense amplifier driver 33.
Timings or electrical potential levels of these control signals/RAS, /CAS,/DSF are set optionally by a user of a semiconductor memory device.
In other words, the control signal FINE and the control signal ROUGH are generated by the control signal generator 18-1 for judging whether the umber of divisions of the boundary addresses is rough (or is decreased) or fine (or increased) when the boundary address is changed by the CBRS or CBR cycles.
In FIG. 11B, the first comparator 27 compares a boundary address (BDAi, i=1,2, . . . ,8) stored in the boundary address register 17 with the SAM counter address (SAi, i=1, 2, . . . ,8) in the SAM counter address register 20, then shows agreement of them, the first comparator 27 generates the control signal STPA of the high level. The control signal STPA changes to the high level when the serial clock SC is agreed with the boundary address (BDAi, i=1, 2, . . . ,8) compared by the first comparator 84.
As a result, as shown in FIG. 12, even if the number of divisions of 15 boundary addresses is occurred in the SRT2 cycle by the CBRS cycle, the first serial clock SC(127) designated by the character reference "*b" following the SRT1 cycle is not regarded as an erroneous boundary address, and the SAM counter address operates correctly.
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