Source: https://patents.google.com/patent/US7899924B2/en
Timestamp: 2019-06-26 20:23:19
Document Index: 31765208

Matched Legal Cases: ['application No. 60', 'Application No. 03718402', 'Application No. 03721674', 'Application No. 03746989', 'Application No. 03718402', 'Application No. 03721674', 'Application No. 03746989', 'Application No. 05775427', 'Application No. 092109078']

US7899924B2 - Flexible streaming hardware - Google Patents
Flexible streaming hardware Download PDF
US7899924B2
US7899924B2 US10/369,306 US36930603A US7899924B2 US 7899924 B2 US7899924 B2 US 7899924B2 US 36930603 A US36930603 A US 36930603A US 7899924 B2 US7899924 B2 US 7899924B2
US10/369,306
US20030229778A1 (en
Richard T. Oesterreicher
Beach Unlimited LLC
2002-04-19 Priority to US37399102P priority Critical
2002-04-19 Priority to US37409002P priority
2002-04-19 Priority to US37408602P priority
2002-04-19 Priority to US37403702P priority
2003-02-19 Priority to US10/369,306 priority patent/US7899924B2/en
2003-02-19 Application filed by Beach Unlimited LLC filed Critical Beach Unlimited LLC
2003-05-13 Assigned to MIDSTREAM TECHNOLOGIES, INC. reassignment MIDSTREAM TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OESTERREICHER, RICHARD T., MURPHY, CRAIG
2003-05-15 Assigned to COMERICA BANK-CALIFORNIA, SUCCESSOR IN INTEREST TO IMPERIAL BANK reassignment COMERICA BANK-CALIFORNIA, SUCCESSOR IN INTEREST TO IMPERIAL BANK SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MIDSTREAM TECHNOLOGIES, INC.
2003-12-11 Publication of US20030229778A1 publication Critical patent/US20030229778A1/en
2005-07-18 Assigned to BEACH UNLIMITED LLC reassignment BEACH UNLIMITED LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MIDSTREAM TECHNOLOGIES, INC.
2011-03-01 Publication of US7899924B2 publication Critical patent/US7899924B2/en
2015-10-20 Assigned to XYLON LLC reassignment XYLON LLC MERGER (SEE DOCUMENT FOR DETAILS). Assignors: BEACH UNLIMITED LLC
2026-04-03 Adjusted expiration legal-status Critical
A hardware engine that streams media asset data from a media buffer to a network under instructions provided by a host PC is disclosed. The PC preferably stores control blocks that provide packet header formatting instructions in a media buffer along with the media asset data to be streamed. In a preferred embodiment, the hardware engine comprises programmable logic devices so that the engine can be upgraded. The present invention further comprises methods for designing the hardware engine, methods for upgrading the hardware engine, and methods for streaming digital media asset data.
This application claims benefit of U.S. provisional patent application Ser. No. 60/374,086, filed Apr. 19, 2002, entitled “Flexible Streaming Hardware,” U.S. provisional patent application Ser. No. 60/374,090, filed Apr. 19, 2002, entitled “Hybrid Streaming Platform,” U.S. provisional patent application Ser. No. 60/374,037, filed Apr. 19, 2002, entitled “Optimized Digital Media Delivery Engine,” and U.S. patent application Ser. No. 60/373,991, filed Apr. 19, 2002, entitled “Optimized Digital Media Delivery Engine,” each of which is hereby incorporated by reference for each of its teachings and embodiments.
This invention relates to the field of digital media servers.
A digital media server is a computing device that streams digital media content onto a digital data transmission network. In the past, digital media servers have been designed using a general-purpose personal computer (PC) based architecture in which PCs provide all significant processing relating to wire packet generation. But digital media are, by their very nature, bandwidth intensive and time sensitive, a particularly difficult combination for PC-based architectures whose stored-computing techniques require repeated data copying. This repeated data copying creates bottlenecks that diminish overall system performance especially in high-bandwidth applications. And because digital media are time sensitive, any such compromise of server performance typically impacts directly on the end-user's experience when viewing the media.
FIG. 1 demonstrates the required steps for generating a single wire packet in a traditional media server comprising a general-purpose PC architecture. The figure makes no assumptions regarding hardware acceleration of any aspect of the PC architecture using add-on cards. Therefore, the flow and number of memory copies are representative of the prior art whether data blocks read from the storage device are reassembled in hardware or software.
Referring now to FIG. 1, in step 101, an application program running on a general-purpose PC requests data from a storage device. Using direct memory access (DMA), a storage controller transfers blocks of data to operating system (OS) random access memory (RAM). In step 102, the OS reassembles the data from the blocks in RAM. In step 103, the data is copied from the OS RAM to a memory location set aside by the OS for the user application (application RAM). These first three steps are performed in response to a user application's request for data from the memory storage device.
In step 104, the application copies the data from RAM into central processing unit (CPU) registers. In step 105, the CPU performs the necessary data manipulations to convert the data from file format to wire format. In step 106, the wire-format data is copied back into application RAM from the CPU registers.
In step 107, the application submits the wire-format data to the OS for transmission on the network and the OS allocates a new memory location for storing the packet format data. In step 108, the OS writes packet-header information to the allocated packet memory from the CPU registers. In step 109, the OS copies the media data from the application RAM to the allocated packet RAM, thus completing the process of generating a wire packet. In step 110, the completed packet is transferred from the allocated packet RAM to OS RAM.
Finally, the OS sends the wire packet out to the network. In particular, in step 111, the OS reads the packet data from the OS RAM into CPU registers and, in step 112, computes a checksum for the packet. In step 113, the OS writes the checksum to OS RAM. In step 114, the OS writes network headers to the OS RAM. In step 115, the OS copies the wire packet from OS RAM to the network interface device over the shared I/O bus, using a DMA transfer. In step 116, the network interface sends the packet to the network.
As will be recognized, a general-purpose-PC architecture accomplishes the packet-generation flow illustrated in FIG. 1 using a number of memory transfers. These memory transfers are described in more detail in connection with FIG. 2.
As shown in FIG. 2, the transfer from storage device 201 to file system cache 202 uses a fast Direct Memory Access (DMA) transfer. The transfer from file system cache 202 to file format data 203 requires each 32 bit word to be copied into a CPU register and back out into random access memory (RAM). This kind of copy is often referred to as a mem copy (or memcpy from the C language procedure), and is a relatively slow process when compared to the wire speed at which hardware algorithms execute. The copy from file format data 203 to wire format data 204 and from wire format data 204 to OS Kernel RAM 205 are also mem copies. Network headers are added to the data while in the OS Kernel RAM 205, which requires a write of header information from the CPU to OS Kernel RAM. Determining the checksum requires a complete read of the entire data packet, and exhibits performance similar to a mem copy. The copy from the OS Kernel RAM 205 to Network Interface Card 206 is a DMA transfer across a shared peripheral component interconnect (PCI) bus. Thus, a total of 5 copies, and 1 complete iterative read into the CPU, of the payload data are required to generate a single network wire packet.
In a preferred embodiment, the present system and method comprise a hardware engine adapted to transfer media asset data from a media buffer to a network. The hardware engine receives media asset streaming instructions from a general-purpose PC via control blocks stored in the buffer along with the media asset data. The hardware engine eliminates the redundant copying of data and the shared I/O bus, bottlenecks typically found in a general-purpose PC that delivers digital media. By eliminating these bottlenecks, the hardware engine improves overall delivery performance and significantly reduces the cost and size associated with delivering digital media to a large number of end users.
In a preferred embodiment, the hardware engine comprises a programmable logic device (PLD) to provide significantly higher data processing speeds than a general-purpose CPU. Advantageously, such PLDs can be reprogrammed without replacing hardware components such as read-only memories. Consequently, the present system provides flexibility and future-proofing not usually found in a dedicated hardware device, while maintaining hardware-level wire-speed performance.
In addition to extending the life cycle of the hardware solution by providing the ability to incorporate additional functional components in the future, the hardware engine's wire-speed performance increases the number of unique streams that can be processed and delivered by the digital media server. This increase in stream density in a smaller physical package (compared to servers that use a general-purpose PC architecture) leads to improved scalability which can be measured by reduced space requirements and lower environmental costs, such as air conditioning and electricity. Because each server unit has a higher stream density than previous media server units, fewer servers are required, which directly relates to a smaller capital investment for deployment of streaming video services. Fewer servers also result in lower operating costs such as reducing the need for operations personnel to maintain and upgrade the servers.
In one aspect, the present invention is directed to a system under the control of a general-purpose computer for converting digital media assets into wire data packets for transmission to a client, the assets being stored on a digital media storage device comprising an input interface for retrieving digital media asset data from the storage device, a media buffer for receiving the digital media asset data from the storage interface, a programmable logic device adapted to transfer the digital media asset data from the input interface to the media buffer, process the digital media asset data from the media buffer, and generate wire data packets, a network interface coupled to the device and adapted to transmit the wire data packets to the client, and a general-purpose interface coupled to the device and adapted to receive control information from the general-purpose computer for storage in the media buffer and to enable the device to communicate with the general-purpose computer.
In another aspect of the present invention, the media buffer is further adapted to store control blocks comprising packet header formatting instructions and digital media asset payload information, and the programmable logic device is further adapted to generate packet headers from the instructions.
In another aspect of the present invention, the digital media asset payload information comprises a pointer to the digital media asset data.
In another aspect of the present invention, the digital media asset payload information comprises the digital media asset data.
In another aspect of the present invention, the programmable logic device is a field programmable gate array.
In another aspect of the present invention, the network interface comprises a Gigabit Ethernet interface.
In another aspect of the present invention, the data generation rate is greater than or equal to the data transmission rate, the programmable logic device data reception rate is greater than or equal to the data generation rate, and the media buffer data reception rate is greater than or equal to the programmable logic device data reception rate.
In another aspect of the present invention, two or more programmable logic devices cooperatively increase the data transmission rate of the system.
In another aspect of the present invention, the programmable logic device comprises an MPEG-2 stitching engine for targeted ad insertion.
In another aspect of the present invention, the programmable logic device is further adapted to encrypt the data stream thereby increasing the quality of content security.
In another aspect, the present invention is directed to a secure method of providing an upgrade package for changing the logic in a field programmable gate array used as an engine for streaming digital media, comprising encrypting the upgrade package, compressing the upgrade package, distributing the upgrade package, decompressing the upgrade package, loading the package into the field programmable gate array, supplying a key to the field programmable gate array for decrypting the upgrade package, and rebooting the field programmable gate array; thereby installing the upgrade package.
In another aspect, the present invention is directed to a method of streaming a block of a digital media asset across a digital network using a hardware engine, comprising transferring the block of the asset into a media buffer, writing wire packet generation control instructions into the media buffer, fragmenting the block into one or more data packets, generating packet headers for a packet in accordance with the instructions, calculating a checksum for the packet, transmitting the packet onto the network, and repeating the generating, calculating, and transmitting steps until all the data packets have been transmitted.
In another aspect of the present invention, the method further comprises the steps of receiving a message to process the instructions and sending a message that the block has been sent.
In another aspect, the present invention is directed to a method for designing a streaming media hardware engine, comprising: (a) identifying one or more components that comprise the hardware engine, (b) designing a last component having a fully saturated output bandwidth greater than or equal to the required bandwidth of the hardware engine (c) calculating the input bandwidth required to fully saturate the designed component, (d) designing an adjacent preceding component having a fully saturated output bandwidth greater than or equal to the input bandwidth calculated in step (c), and recursively repeating steps (c) and (d) for remaining components identified in step (a).
FIG. 1 is a flow chart illustrating a process for generating wire data packets in a general-purpose personal computer;
FIG. 2 is a block diagram that illustrates hardware and software components in a general-purpose personal computer used to generate a wire packet;
FIG. 3 is a block diagram that illustrates components of a hardware engine in one embodiment;
FIG. 4 is a block diagram that illustrates an embodiment of the hardware engine that uses a field programmable gate array, and depicts the internal architecture of same;
FIG. 5 is a block diagram that illustrates an embodiment of the internal architecture of a format conversion and packet generation engine found in the field programmable gate array;
FIG. 6 is a flow chart that illustrates an embodiment of the design methodology for a media asset streaming hardware engine;
FIG. 7 is a flow chart that illustrates an embodiment of the installation of an upgrade package in an FPGA;
FIG. 8 is an example control block for a Quick Time media file streamed over RTP/UDP/IP;
FIG. 9 is an example control block for an MPEG-2 file streamed over UDP/IP;
FIG. 10 is a flow diagram illustrating the process of generating wire packets in a preferred embodiment;
FIG. 11 is a diagram of the Ethernet header or media access control layer (MAC) control block entry structure;
FIG. 12 is a diagram of the internet protocol (IP) header control block entry structure;
FIG. 13 is a diagram of the user datagram protocol (UDP) header control block entry structure;
FIG. 14 is a diagram of the transport control protocol (TCP) header control block entry structure;
FIG. 15 is a diagram of the hypertext transport protocol (HTTP) header control block entry structure;
FIG. 16 is a diagram of the realtime transport protocol (RTP) header control block entry structure; and
FIG. 17 is a diagram of the payload data control block entry structure.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hardware Engine Components
One preferred embodiment of a hardware engine for streaming digital media assets is shown in FIG. 3. As shown in FIG. 3, hardware engine 300 preferably comprises several components including dedicated buses 310, an input interface 320, a media buffer 330, a network interface 340, a general-purpose interface 350, and one or more programmable logic devices (PLDs) 360. Dedicated buses 310 provide an exclusive data pathway between PLD 360 and other hardware engine components. Input interface 320 is preferably adapted to control data storage devices containing media assets to be streamed and transmits asset data through PLD 360 to media buffer 330, as described below. Network interface 340 provides a controller for communicating with other devices across a data network. General-purpose interface 350 provides a controller for communicating with a general-purpose computing device. PLD 360 translates asset data that is held in media buffer 330 into wire data packets and sends the packets out to the network through network interface 340.
FIG. 4 is a block diagram depicting a preferred embodiment of PLD 360. In the preferred embodiment of FIG. 4, PLD 360 comprises a Field Programmable Gate Array (FPGA) device. Those skilled in the art will recognize that other PLDs may alternatively be used.
As shown in FIG. 4, FPGA device 400 preferably comprises a plurality of objects created using Hardware Description Language (HDL). These HDL objects preferably comprise interface objects 420-460, a series of first-in, first-out (FIFO) queues 471-475, and a packet engine 480. Interface objects 420-460 provide the necessary control and addressing signals through dedicated buses 310 to communicate with interface devices 320-350. FIFO queues 471-475 provide internal data communication paths between interface objects and packet engine 480. Packet engine 480 converts asset data held in media buffer 330 into wire data packets that are sent out to the network.
In more detail, interface objects 420-460 preferably comprise a storage peripheral component interface (PCI) interface 420, a media buffer interface 430, a gigabit Ethernet controller interface 440, a general-purpose PCI interface 450, and a security interface 460. Interface HDL objects 420-460 provide the signals required to send or receive data from the FPGA to components 320-360, respectively.
The series of FIFO queues preferably comprises five sets of FIFO queues 471-475. FIFO queue HDL objects 471-475 buffer the flow of data between the interface HDL objects and packet engine 480 in FPGA device 400.
FIG. 5 is a block diagram of a preferred embodiment of packet engine 480. As shown in FIG. 5, engine 480 preferably comprises a collection of state machines. There are three main groups of state machines: parser state machines 510, header formatter state machines 520, and packet assembler state machines 530. Parser state machines 510 read control blocks stored in media buffer 330 and retrieve the associated media asset data for processing. Header formatter state machines 520 generate the protocol headers for the communications protocols used in each data packet. Packet assembler state machines 530 create wire data packets by connecting the generated packet headers with the asset data and generating checksums for the data. Packet engine 480 further comprises memory writing state machine 540 for sending information back to media buffer 330. Memory writing state machine 540 updates control block entries for TCP, and RTP packets, as described below in the Streaming Media Operation section.
Parser state machines 510 preferably comprise three components, a control block parser 519, a payload builder 517, and a facilitator 515. Control block parser 519 is adapted to read a control block stored in media buffer 330 and pass appropriate data from the control block to header formatting state machines 520. Under control of control block parser 519, payload builder 517 reads asset data from media buffer 330. Facilitator 515 is adapted to schedule the output from packet header formatters 520.
Packet header formatter state machines 520 preferably comprise state machines that produce packet headers which adhere to the communication protocols necessary for streaming video across an Internet Protocol data network including IP 521, UDP 522, TCP 523, RTP 524 and HTTP 525. Each packet header formatter is responsible for generating a packet header in the appropriate format for inclusion in the wire packet. The packet headers are preferably generated from control block data determined by control block parser 519.
Packet assembly state machines preferably comprise a multiplexer 531, a payload packer engine 532, a header packer 533, a checksum generator 534, and a packet writer 535. Multiplexer 531 multiplexes the output of the various header format state machines and the payload builder into packets. Payload packer engine 532 shifts and concatenates the data to eliminate empty bytes in the packet data stream. Packer 533 shifts and concatenates the packet headers to eliminate empty bytes in the packet data stream. Checksum generator 534 generates the checksum of the wire data packet. Packet writer 535 sends the wire data packet out to the gigabit Ethernet controller. It manages payload buffers included in gigabit Ethernet controller 440, inserts checksums into the packet data stream, and creates a data entry indicating that the asset has been sent.
In an alternative preferred embodiment, packet engine 480 may include additional packet generation and protocol engines that replace many of the algorithms traditionally executed on a general-purpose CPU. For example, packet engine 480 may comprise an MPEG-2 stitching engine for targeted ad insertion, or a unique stream-encryption engine for increasing the quality of content security.
Design Methodology for Hardware Engine
Each component in hardware engine 300 is designed specifically for the sustained delivery of digital media so that any given component will not restrict the flow of data and form a bottleneck in the device. Preferably, the criterion used to calculate how much input bandwidth is required for a component is determined from the full bandwidth saturation of the output interface of the component. By determining the amount of input bandwidth that will achieve a desired output bandwidth for a particular component, the output bandwidth of its upstream component can be selected so that the upstream component will supply at least the bandwidth required at the component's input to saturate its output.
This design principle is preferably applied to all components in hardware engine 300, including those that may have a higher input bandwidth than output bandwidth at full saturation. This situation may occur where some of the data supplied to a component is not transmitted by the component. Illustratively, a component that reads data storage blocks from a hard drive and processes the blocks into data packets may not use the entire contents of the block. The packet data required may be slightly larger than one block, requiring that two blocks be read into media buffer 330. Although two full blocks are read, only a small percentage of the second block is required for generating the packet. Thus, the output bandwidth for the component may be less than its input bandwidth.
This design process is illustrated in more detail in FIG. 6. In step 610, the components of the hardware engine are identified. Then, the components in the data stream generating chain are evaluated in reverse order. In step 620, the last component in the data stream generation chain is designed so that it has an output bandwidth greater than or equal to the required bandwidth that the hardware engine must supply. Next, the input necessary to saturate this output is calculated based on the selected component's functions and data it processes (step 630). If the selected component is not the first component in the data streamer generation chain (step 640), the next upstream component is designed to have an output bandwidth greater than or equal to the calculated input bandwidth of the previously selected component (step 650). Once the first component has been evaluated (step 640), the design process is complete.
Because the throughput of each component and bus are selected or designed to fully saturate the next component, bottlenecks within the device are eliminated and the device operates with fully saturated output connections.
Reprogramming the FPGA
In a preferred embodiment, upgrade packages may be used to reprogram the FPGA using the hardware description language (HDL). By replacing the FPGA's configuration, the HDL components included in the FPGA are changed. The process for installing an upgrade package is illustrated in FIG. 7.
As shown in FIG. 7, in step 710 upgrade packages are created to replace the configuration in the FPGA. In step 720, these packages are preferably encrypted to protect their contents from scrutiny, and in step 730, compressed for distribution. The upgrade package may then be downloaded (step 740), decompressed (step 750), and decrypted (step 755) before it is copied into the FPGA (step 760). In step 770, after the upgrade package is loaded into the FPGA, the FPGA is stopped and rebooted. When the system restarts, the FPGA is reloaded with the upgraded logic.
In a preferred embodiment, security interface 560 protects the logic programmed into the FPGA from being copied. As known in the art, different security interfaces may be designed or purchased that provide varying degrees of security and implementation overhead. Those skilled in the art may balance competing desires to maximize security while minimizing implementation time and cost in selecting an appropriate security interface for the FPGA.
The flexibility achieved by reprogramming the hardware device is illustrated by the following example. Suppose that the initial hardware description language implemented in the FPGA includes packetization algorithms and protocols specific to MPEG-2 transport streams. In the future, users may require delivery of media content in other formats such as MPEG-4. Because hardware engine 300 comprises an FPGA, new algorithms for manipulating MPEG-4 formats can be added to the layout of the chip using HDL in the form of an upgrade package.
FSH Streaming Media Operation
In operation, hardware engine 300 assembles wire packets in accordance with instructions specified in a control block found in media buffer 330. In a preferred embodiment the control block is a 128-byte data structure comprising a series of control block entries (CBE) of at least eight bytes in length. Each CBE either contains data that will be part of a media packet, or a pointer to that data. The media packet can be constructed by traversing the entire control block and concatenating the data contained in each entry or data pointed at by each entry.
FIG. 8 illustrates an exemplary control block for a Quick Time media file streamed over RTP/UDP/IP. The exemplary control block comprises a cookie control block entry 810 that uniquely identifies a data stream. The exemplary control block further comprises a series of format CBEs 820-850, along with a series of one or more media packet payload CBEs 860-890. Media packet payload CBEs 860-890 identify the address of the associated media packets in media buffer 330. Hardware engine 300 processes control blocks and associated media packet payload data to generate wire data packets, as described below.
FIG. 9 is an example control block for an MPEG-2 file streamed over UDP/IP. Analogous control blocks may be created for use with other public domain or proprietary streaming formats. Each such control block also comprises a cookie control block entry, one or more format CBEs, and one or more media packet payload CBEs.
FIG. 10 illustrates a preferred embodiment of a process for streaming media. As shown in FIG. 10, in step 1010, a block of media asset data is moved from data storage through the hardware engine's input interface 310 and placed into media buffer 330 under control of a general-purpose PC as described in copending U.S. patent application No. 60/374,090, entitled “Hybrid Streaming Platform,” filed on even date herewith, which is hereby incorporated by reference in its entirety for each of its teachings and embodiments. In step 1020, a control block is written to media buffer 330. The control block preferably identifies the location of the media asset in the media buffer and includes instructions for processing the media asset data. In step 1030, hardware engine 300 receives a data message to commence streaming the media asset data. The message preferably contains a pointer to the control block and a stream identifier corresponding to the control block.
Engine 300 then converts the media packet payload from file format to wire format. If the media packet is larger than the maximum transmission unit (MTU), this conversion process preferably comprises fragmentation of the media packet into several wire format data packets (step 1040). In step 1050, engine 300 generates protocol format headers specified in the CBEs for insertion into the wire packet. Next, in step 1060, engine 300 assembles the packet and calculates a checksum for the wire packet. In step 1070, engine 300 sends a wire packet out thorough gigabit Ethernet interface 340. If the last wire packet has not been sent (step 1080), engine 300 updates packet headers and checksum and sends the next wire packet. After the last packet has been transmitted, engine 300 generates a message that indicates the control block has been processed.
A preferred header-formatting process is now described in more detail. In a preferred embodiment, engine 300 adds an Ethernet header to every packet unless the control block has a “pass thru” identifier. The Ethernet header control block contains a source address, destination address, and a packet type field. In a preferred embodiment, header information for the Ethernet header is included in a CBE, as shown, for example, in FIG. 11. When transmitting packets, engine 300 preferably uses the same Ethernet header information from the control block for every packet in a particular stream. If necessary, the destination address can be changed as directed by a separate CBE. Each packet is also preferably provided with any additional headers required by its associated CBE.
In a preferred embodiment, when the packet includes an IP header, the CBE preferably includes the following fields, illustrated in FIG. 12: a version, a header length, a type-of-service field, a total length, an identification field, flags, a fragment offset, a time-to-live field, a protocol byte field, a header checksum, a source IP address and a destination IP address. Before sending the wire packet, engine 300 preferably performs the following functions. First, engine 300 computes the total length in bytes by adding up the length fields from all CBEs. Next, engine 300 computes the header checksum by setting the field to zero, then computing the 16-bit sum over the IP header only. Finally, engine 300 stores the 16-bit ones-complement of the sum in the header checksum field, and copies the other fields to generate the IP packet header.
In a preferred embodiment, when the packet includes a UDP header, the CBE preferably includes fields for a source port number, destination port number, UDP length, and UDP checksum fields as shown in FIG. 13. Before sending the wire packet, engine 300 preferably performs the following functions. First, engine 300 computes the UDP length by adding up the length fields from all CBEs including and after the one pointing to the UDP header. Then, engine 300 computes the UDP checksum by performing a 16-bit add of the source IP address field from the IP packet header, the destination IP address field from the IP header, the protocol field (as the lower 8 bits) from the IP header, the UDP length as calculated above, and the entire UDP header, plus the remaining wire packet headers and media packet payload. Then the ones-complement of the sum is stored in the UDP checksum field, and the remaining fields are copied into the UDP header from the UDP control block. For more details of the generation of IP/UDP packets by hardware engine 300, see copending U.S. patent application Ser. No. 10/369,307, entitled “Optimized Digital Media Delivery Engine,” filed on even date herewith, which is hereby incorporated by reference in its entirety for each of its teachings and embodiments.
In a preferred embodiment, when the packet includes an TCP header, the CBE preferably includes fields for a source port number, destination port number, a sequence number, an acknowledgment number, a header length, a reserved field, flags, a window size, a TCP checksum, and an urgent pointer, as shown in FIG. 14. Before sending the wire packet, engine 300 preferably performs the following functions. First, the TCP checksum is calculated by performing a 16-bit add of the source IP address from the IP header, the destination IP address from the IP header, the protocol field (as the lower 8 bits) from the IP header, the total-length field from the IP header, the entire TCP header, plus the remaining wire packet headers and media packet payload. Then the ones-complement of the sum is stored in the TCP checksum field, and the remaining fields are copied from the TCP CBE to generate the TCP packet header.
After sending the wire packet, engine 300 preferably increments the sequence number in the TCP control block entry. If the TCP packet is segmented, the sequence number is preferably updated in every wire data packet sent, but the sequence number in the control block is incremented after the entire media packet has been processed.
In a preferred embodiment, when the packet includes an HTTP header, the CBE preferably contains a “$” character, an HDCE byte field, and a total length field, as shown in FIG. 15. Before sending the wire packet, engine 300 preferably fills in the total length field based on the payload length field from the IP CBE and any headers that follow the HTTP header, such as RTP, to generate the HTTP packet header.
In a preferred embodiment, when the packet includes an RTP header, the CBE preferably includes flags, a CSRC count field, a payload type field, a sequence number, a timestamp, and a SSRC identifier, as shown in FIG. 16. Engine 300 copies the RTP CBE in order to generate the RTP packet header before sending out the wire packet.
After sending the wire packet, engine 300 preferably increments the sequence number field in the RTP CBE by 1.
In a preferred embodiment, the control block contains a payload data CBE, as shown in FIG. 17. The payload CBE contains a flag field, ID field, payload length field, and either an address to the payload data or a null value if the ID field indicates that the payload data is appended to the end of the CBE. The length field is used by engine 300 to determine whether to fragment the payload and for inclusion in the packet header fields. The address field is used by engine 300 to locate the payload data in media buffer 330.
In an alternative preferred embodiment, multiple PLDs may be pipelined together to execute additional algorithms, or more complex algorithms, in tandem. Embodiments comprising multiple PLDs preferably comprise additional communications structures in the PLD for inter-process communications between the PLDs in order to execute parallel algorithms.
1. A server system for transmitting digital media asset data to a client, comprising:
a programmable logic device configured to generate a wire data packet according to control information, said control information contained in a control block for storage in a media buffer, said control block comprising:
a first plurality of control block entries,
a second plurality of control block entries, and
said control information,
wherein individual entries of the first plurality of control block entries comprise a pointer to a first subset of media packet payload data, and
wherein individual entries of the second plurality of control block entries comprise a second subset of media packet payload data,
said programmable logic device comprising:
a parser state machine configured to read said control block and generate a media packet payload by:
determining an address in said media buffer for the first subset of media packet payload data referenced by the pointer in ones of the first plurality of control block entries and determining the second subset of media packet payload data contained in ones of the second plurality of control block entries, and
concatenating the first subset of media packet payload data referenced by the ones of the first plurality of control block entries and the second subset of media packet payload data contained in the ones of the second plurality of control block entries according to the control information;
a header formatter state machine configured to:
generate a first header associated with a first protocol according to said control information, and
generate a second header associated with a second protocol according to said control information; and
a packet assembler state machine configured to:
multiplex said first header, said second header, and said media packet payload, and
assemble said wire data packet comprising said multiplexed first header, second header, and media packet payload.
2. The system of claim 1, wherein said control information comprises packet header formatting instructions and digital media asset payload information.
3. The system of claim 1, wherein a media buffer data reception rate is greater than or equal to a programmable logic device data reception rate.
4. The system of claim 1, wherein said first protocol is User Datagram Protocol (UDP) and said second protocol is Internet Protocol (IP).
5. The system of claim 1, wherein the programmable logic device is a field programmable gate array.
6. The system of claim 1, further comprising a network interface configured to transmit said wire data packet at a wire data packet transmission rate, wherein said programmable logic device is further configured to generate a plurality of wire data packets at a wire data packet generation rate greater than or equal to the wire data packet transmission rate.
7. The system of claim 6, wherein a programmable logic device data reception rate is greater than or equal to the wire data packet generation rate.
8. The system of claim 6, wherein two or more programmable logic devices cooperatively increase the wire data packet transmission rate of the system.
9. The system of claim 1, wherein the programmable logic device further comprises an MPEG-2 stitching engine for targeted ad insertion.
10. The system of claim 1, wherein the programmable logic device is further adapted to encrypt the wire data packet.
11. A method for assembling digital media asset data into wire data packets, said method comprising:
storing a control block in a media buffer, the control block comprising:
control information,
wherein individual entries of the second plurality of control block entries comprise a second subset of media packet payload data;
assembling a wire data packet from said digital media asset data by a programmable logic device according to said control information, wherein said assembling comprises:
generating, by a header formatter state machine, a first header associated with a first protocol according to said control information,
generating, by said header formatter state machine, a second header associated with a second protocol according to said control information,
generating, by a parser state machine, a media packet payload by:
determining an address in said media buffer for the first subset of media packet payload data referenced by ones of the first plurality of control block entries,
determining the second subset of media packet payload data contained in ones of the second plurality of control block entries, and
concatenating the first subset of media packet payload data referenced by the pointer in the ones of the first plurality of control block entries and the second subset of media packet payload data contained in the ones of the second plurality of control block entries according to the control information, and
multiplexing, by a packet assembler state machine, said first header, said second header, and said media packet payload, and assembling said wire data packet comprising said multiplexed first header, second header, and media packet payload.
12. The method of claim 11, wherein said control information comprises packet header formatting instructions and digital media asset payload information.
13. The method of claim 11, wherein a media buffer data reception rate is greater than or equal to a programmable logic device data reception rate.
14. The method of claim 11, wherein said first protocol is User Datagram Protocol (UDP) and said second protocol is Internet Protocol (IP).
15. The method of claim 11, wherein the programmable logic device is a field programmable gate array.
16. The method of claim 11, further comprising transmitting, by a network interface, said wire data packet at a wire data packet transmission rate, wherein said programmable logic device is further configured to generate a plurality of wire data packets at a wire data packet generation rate greater than or equal to the wire data packet transmission rate.
17. The method of claim 16, wherein a programmable logic device data reception rate is greater than or equal to said wire data packet generation rate.
18. The method of claim 16, wherein two or more programmable logic devices cooperatively increase the wire data packet transmission rate.
19. The method of claim 11, further comprising inserting a targeted ad in the wire date packet.
20. The method of claim 11, further comprising encrypting said wire data packet.
21. A system for assembling digital media asset data into wire data packets, said system comprising:
means for storing a control block in a media buffer, said control block comprising:
means for reading, by a programmable logic device said control block, said programmable logic device comprising:
means for generating, by a header formatter state machine, a first header associated with a first protocol according to said control information,
means for generating, by said header formatter state machine, a second header associated with a second protocol according to said control information,
means for generating, by a parser state machine, a media packet payload by:
determining an address in said media buffer for the first subset of media packet payload data referenced by the pointer in ones of the first plurality of control block entries,
means for multiplexing, by a packet assembler state machine, said first header, said second header, and said media packet payload, and generating said wire data packet comprising said multiplexed first header, second header, and media packet payload.
22. The system of claim 21, wherein said control information comprises packet header formatting instructions and digital media asset payload information.
23. The system of claim 21, wherein a media buffer data reception rate is greater than or equal to a programmable logic device data reception rate.
24. The system of claim 21, wherein said first protocol is User Datagram Protocol (UDP) and said second protocol is Internet Protocol (IP).
25. The system of claim 21, wherein the programmable logic device is a field programmable gate array.
26. The system of claim 21 further comprising means for transmitting, by a network interface, said wire data packet at a wire data packet transmission rate, wherein said programmable logic device is further configured to generate a plurality of wire data packets at a wire data packet generation rate greater than or equal to the wire data packet transmission rate.
27. The system of claim 26, wherein a programmable logic device data reception rate is greater than or equal to the wire data packet generation rate.
28. The system of claim 26, wherein two or more programmable logic devices cooperatively increase the wire data packet transmission rate.
29. The system of claim 21, further comprising means for inserting a targeted ad in said wire date packet.
30. The system of claim 21, further comprising means for encrypting said wire data packet.
US10/369,306 2002-04-19 2003-02-19 Flexible streaming hardware Active 2026-04-03 US7899924B2 (en)
US37399102P true 2002-04-19 2002-04-19
US37409002P true 2002-04-19 2002-04-19
US37408602P true 2002-04-19 2002-04-19
US37403702P true 2002-04-19 2002-04-19
US10/369,306 US7899924B2 (en) 2002-04-19 2003-02-19 Flexible streaming hardware
CA 2483017 CA2483017A1 (en) 2002-04-19 2003-04-14 Flexible streaming hardware
AU2003221941A AU2003221941A1 (en) 2002-04-19 2003-04-14 Flexible streaming hardware
EP03718402A EP1497666A4 (en) 2002-04-19 2003-04-14 Flexible streaming hardware
PCT/US2003/011575 WO2003089944A1 (en) 2002-04-19 2003-04-14 Flexible streaming hardware
TW92109078A TWI316341B (en) 2002-04-19 2003-04-18 Flexible streaming hardware
US20030229778A1 US20030229778A1 (en) 2003-12-11
US7899924B2 true US7899924B2 (en) 2011-03-01
ID=29254388
US10/369,306 Active 2026-04-03 US7899924B2 (en) 2002-04-19 2003-02-19 Flexible streaming hardware
US (1) US7899924B2 (en)
EP (1) EP1497666A4 (en)
AU (1) AU2003221941A1 (en)
CA (1) CA2483017A1 (en)
TW (1) TWI316341B (en)
WO (1) WO2003089944A1 (en)
US20110087721A1 (en) * 2005-11-12 2011-04-14 Liquid Computing Corporation High performance memory based communications interface
WO2013100986A1 (en) * 2011-12-28 2013-07-04 Intel Corporation Systems and methods for integrated metadata insertion in a video encoding system
JP2005204001A (en) * 2004-01-15 2005-07-28 Hitachi Ltd Data distribution server, software, and system
US20070162972A1 (en) * 2006-01-11 2007-07-12 Sensory Networks, Inc. Apparatus and method for processing of security capabilities through in-field upgrades
US20080212942A1 (en) * 2007-01-12 2008-09-04 Ictv, Inc. Automatic video program recording in an interactive television environment
CN102301652A (en) * 2009-04-27 2011-12-28 国际商业机器公司 Message Conversion
KR101394884B1 (en) * 2012-06-18 2014-05-13 현대모비스 주식회사 Congestion Control Device and Method for Inter-Vehicle Communication
US20180205621A1 (en) * 2017-01-13 2018-07-19 A.T.E. Solutions, Inc. Systems and methods for dynamically reconfiguring automatic test equipment
US4800431A (en) * 1984-03-19 1989-01-24 Schlumberger Systems And Services, Inc. Video stream processing frame buffer controller
EP0473102A2 (en) 1990-08-29 1992-03-04 Honeywell Inc. Data communication system with checksum calculating means
US5333299A (en) 1991-12-31 1994-07-26 International Business Machines Corporation Synchronization techniques for multimedia data streams
US5367636A (en) 1990-09-24 1994-11-22 Ncube Corporation Hypercube processor network in which the processor indentification numbers of two processors connected to each other through port number n, vary only in the nth bit
US5375233A (en) 1988-12-22 1994-12-20 International Computers Limited File system
US5515379A (en) 1993-10-18 1996-05-07 Motorola, Inc. Time slot allocation method
US5638516A (en) 1994-08-01 1997-06-10 Ncube Corporation Parallel processor that routes messages around blocked or faulty nodes by selecting an output port to a subsequent node from a port vector and transmitting a route ready signal back to a previous node
EP0781002A2 (en) 1995-12-21 1997-06-25 THOMSON multimedia Optimizing performance in a packet slot priority packet transport system
US5715356A (en) 1993-09-16 1998-02-03 Kabushiki Kaisha Toshiba Apparatus for processing compressed video signals which are be recorded on a disk or which have been reproduced from a disk
US5737525A (en) 1992-05-12 1998-04-07 Compaq Computer Corporation Network packet switch using shared memory for repeating and bridging packets at media rate
US5768598A (en) 1993-09-13 1998-06-16 Intel Corporation Method and apparatus for sharing hardward resources in a computer system
US5815516A (en) * 1996-04-05 1998-09-29 International Business Machines Corporation Method and apparatus for producing transmission control protocol checksums using internet protocol fragmentation
US5848192A (en) 1994-08-24 1998-12-08 Unisys Corporation Method and apparatus for digital data compression
US5995974A (en) 1997-08-27 1999-11-30 Informix Software, Inc. Database server for handling a plurality of user defined routines (UDRs) expressed in a plurality of computer languages
US6023731A (en) 1997-07-30 2000-02-08 Sun Microsystems, Inc. Method and apparatus for communicating program selections on a multiple channel digital media server having analog output
US6088360A (en) * 1996-05-31 2000-07-11 Broadband Networks Corporation Dynamic rate control technique for video multiplexer
US6108695A (en) 1997-06-24 2000-08-22 Sun Microsystems, Inc. Method and apparatus for providing analog output and managing channels on a multiple channel digital media server
TW406227B (en) 1997-09-17 2000-09-21 Sony Electronics Inc High speed bus structure in a multi-port bridge for a local area network
US6157051A (en) 1998-07-10 2000-12-05 Hilevel Technology, Inc. Multiple function array based application specific integrated circuit
US6182206B1 (en) 1995-04-17 2001-01-30 Ricoh Corporation Dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
TW421972B (en) 1996-03-18 2001-02-11 Hitachi Ltd Method of coding and decoding image
US6192027B1 (en) 1998-09-04 2001-02-20 International Business Machines Corporation Apparatus, system, and method for dual-active fibre channel loop resiliency during controller failure
US6222838B1 (en) 1997-11-26 2001-04-24 Qwest Communications International Inc. Method and system for delivering audio and data files
TW435028B (en) 1998-03-27 2001-05-16 Nexabit Networks Llc AMPIC DRAM system
US20010004767A1 (en) 1997-01-13 2001-06-21 Diva Systems Corporation System for interactively distributing information services
TW447201B (en) 1998-09-24 2001-07-21 Alteon Web Systems Inc Distributed load-balancing internet servers
TW452701B (en) 1998-12-18 2001-09-01 Ibm Mechanism allowing asynchronous access to graphics adapter frame buffer physical memory linear aperture in a multi-tasking environment
TW452690B (en) 1998-11-02 2001-09-01 Ibm Reservation management in a non-uniform memory access (NUMA) data processing system
TW453080B (en) 1997-02-14 2001-09-01 Advanced Micro Devices Inc Method and apparatus for selectively discarding packet for blocked output queues in the network switch
TW454132B (en) 1998-10-22 2001-09-11 Ibm Digital content preparation system
TW457444B (en) 1997-02-11 2001-10-01 Xaqti Corp Media access control architectures and network management systems
TW460781B (en) 1998-10-14 2001-10-21 Hitachi Ltd A data cache system
US20010037443A1 (en) 2000-03-01 2001-11-01 Ming-Kang Liu Logical pipeline for data communications system
TW465211B (en) 1998-10-27 2001-11-21 Port Corp C Digital communications processor
TW465209B (en) 1999-03-25 2001-11-21 Telephony & Amp Networking Com Method and system for real-time voice broadcast and transmission on Internet
US20020000831A1 (en) * 2000-06-30 2002-01-03 Akya Limited Modular software definable pre-amplifier
US20020007417A1 (en) 1999-04-01 2002-01-17 Diva Systems Corporation Modular storage server architecture with dynamic data management
TW475111B (en) 1998-11-04 2002-02-01 Inventec Corp Method for testing image data transmission between memories
US20020067745A1 (en) * 2000-12-06 2002-06-06 David Coupe System and method for remultiplexing of a filtered transport stream
US20020105905A1 (en) * 2000-12-27 2002-08-08 Boyle William B. Data stream control system for associating counter values with stored selected data packets from an incoming data transport stream to preserve interpacket time interval information
US20020107989A1 (en) 2000-03-03 2002-08-08 Johnson Scott C. Network endpoint system with accelerated data path
US6498897B1 (en) * 1998-05-27 2002-12-24 Kasenna, Inc. Media server system and method having improved asset types for playback of digital media
US6535557B1 (en) 1998-12-07 2003-03-18 The University Of Tokyo Method and apparatus for coding moving picture image
US6594775B1 (en) 2000-05-26 2003-07-15 Robert Lawrence Fair Fault handling monitor transparently using multiple technologies for fault handling in a multiple hierarchal/peer domain file server with domain centered, cross domain cooperative fault handling mechanisms
US20030221197A1 (en) 2002-05-23 2003-11-27 Fries Robert M. Interactivity emulator for broadcast communication
US6687757B1 (en) * 1999-07-05 2004-02-03 Flextronics Semiconductor Inc. Packet processor
US20040034712A1 (en) * 2000-02-03 2004-02-19 Doron Rajwan Data streaming
CN1484898A (en) 2000-11-17 2004-03-24 艾劳普提克公司 Point-to-multipoint passive optica network that utilizes variable length packets
US6842785B1 (en) 1996-01-22 2005-01-11 Svi Systems, Inc. Entertainment and information systems and related management networks for a remote video delivery system
US6876653B2 (en) * 1998-07-08 2005-04-05 Broadcom Corporation Fast flexible filter processor based architecture for a network device
US6879598B2 (en) * 2003-06-11 2005-04-12 Lattice Semiconductor Corporation Flexible media access control architecture
US6944152B1 (en) 2000-08-22 2005-09-13 Lsi Logic Corporation Data storage access through switched fabric
US6944585B1 (en) 2000-09-01 2005-09-13 Oracle International Corporation Dynamic personalized content resolution for a media server
US6956853B1 (en) * 1998-05-01 2005-10-18 3Com Corporation Receive processing with network protocol bypass
US6971043B2 (en) 2001-04-11 2005-11-29 Stratus Technologies Bermuda Ltd Apparatus and method for accessing a mass storage device in a fault-tolerant server
US6996618B2 (en) 2001-07-03 2006-02-07 Hewlett-Packard Development Company, L.P. Method for handling off multiple description streaming media sessions between servers in fixed and mobile streaming media systems
US7035295B2 (en) 2001-07-23 2006-04-25 Koninklijke Philips Electronics N.V. Direct RTP delivery method and system over MPEG network
US7035278B2 (en) 1998-07-31 2006-04-25 Sedna Patent Services, Llc Method and apparatus for forming and utilizing a slotted MPEG transport stream
US7042899B1 (en) * 2001-05-08 2006-05-09 Lsi Logic Corporation Application specific integrated circuit having a programmable logic core and a method of operation thereof
US20060146780A1 (en) 2004-07-23 2006-07-06 Jaques Paves Trickmodes and speed transitions
US7174086B2 (en) 2001-10-23 2007-02-06 Thomson Licensing Trick mode using dummy predictive pictures
US7200670B1 (en) * 2000-06-30 2007-04-03 Lucent Technologies Inc. MPEG flow identification for IP networks
US7228358B1 (en) 2000-07-25 2007-06-05 Verizon Services Corp. Methods, apparatus and data structures for imposing a policy or policies on the selection of a line by a number of terminals in a network
US7240113B1 (en) 1998-05-06 2007-07-03 Sony United Kingdom Limited Networked conditional access module
US7260576B2 (en) 2002-11-05 2007-08-21 Sun Microsystems, Inc. Implementing a distributed file system that can use direct connections from client to disk
US7359955B2 (en) 2001-03-02 2008-04-15 Kasenna, Inc. Metadata enabled push-pull model for efficient low-latency video-content distribution over a network
US7460531B2 (en) * 2003-10-27 2008-12-02 Intel Corporation Method, system, and program for constructing a packet
US6944154B2 (en) * 2000-12-06 2005-09-13 International Business Machines Corporation System and method for remultiplexing of a filtered transport stream with new content in real-time
US6904057B2 (en) * 2001-05-04 2005-06-07 Slt Logic Llc Method and apparatus for providing multi-protocol, multi-stage, real-time frame classification
2003-02-19 US US10/369,306 patent/US7899924B2/en active Active
2003-04-14 EP EP03718402A patent/EP1497666A4/en not_active Withdrawn
2003-04-14 CA CA 2483017 patent/CA2483017A1/en not_active Abandoned
2003-04-14 AU AU2003221941A patent/AU2003221941A1/en not_active Abandoned
2003-04-14 WO PCT/US2003/011575 patent/WO2003089944A1/en not_active Application Discontinuation
2003-04-18 TW TW92109078A patent/TWI316341B/en not_active IP Right Cessation
US20010019336A1 (en) 1997-01-13 2001-09-06 Diva Systems Corp. Method and apparatus for providing a menu structure for an interactive information distribution system
"A Bit-Parallel Search Algorithm for Allocating Free Space," Modeling, Analysis and Simulation of Computer and Telecommunications Systems, Ninth International Symposium, Aug. 15-18, 2001, 302-310.
"A Distributed Hierarchical Storage Manager for a Video-on-Demand System," Storage and Retrieval for Image and Video Databases (SPIE), Feb. 1994, 1-13.
"Agere unveils 3G baseband-processing scheme," Electronic Engineering Times, Feb. 16, 2004, p. 37.
"Evolving the Vnode Interface," UNENIX Summer Conference Proceedings, 1990, 107-117.
"HAMFS File System," Reliable Distributed Systems, Proceedings of the 18th IEEE Symposium an Lausanne, Switzerland, Los Alamitos, California, Oct. 19-22, 1999, 190-201.
"Judge upholds jury decision in nCUBE-SeaChange patent spat," CED Broadband Direct News, Apr. 13, 2004, retrieved online at: http://www.cedmagazine.com/cedailydirect/2004/0404/cedaily040413.htm 1 page.
"The Cluster File System: Integration of High Performance Communication and I/O in Clusters," IEEE Computer Society, Cluster Computing and the Grid 2nd IEEE/ACM International Symposium, Berlin, Germany, May 21, 2002, 173-182.
"Thirdspace investment insulates Concurrent from VOD patent war," from CED Broadband Direct, Jun. 10, 2002, retrieved online at: http://lwww.broadbandweek.com/news/020610/020610-content-third.htm, 1 page.
"Thirdspace investment insulates Concurrent from VOD patent war," from CED Broadband Direct, Jun. 10, 2002, retrieved online at: http://lwww.broadbandweek.com/news/020610/020610—content—third.htm, 1 page.
"Vnodes: An Architecture for Multiple File System Types in Sun UNIX," USENIX Association: Summer Conference Proceedings, 1986, 1-10.
A High-Throughput Digital Media Server for Video-on-Demand Service, May 14, 2002 Retrieved online at http://www.csupomona.edu/~ece/eceweb/program/srproject.html.
A High-Throughput Digital Media Server for Video-on-Demand Service, May 14, 2002 Retrieved online at http://www.csupomona.edu/˜ece/eceweb/program/srproject.html.
Altera Corporation, Application Note 132, "Implementing Multiprotocol Label Switching with Altera PLDs," Jan. 2001, ver. 1.0, pp. 1-12.
Brochure for RAM-SAN(TM) RamSan-320, Jul. 1, 2003.
Brochure for RAM-SAN™ RamSan-320, Jul. 1, 2003.
Communication forwarding Supplementary EP Search Report dated Dec. 20, 2007, in corresponding EP Application No. 03718402.5.
Communication forwarding Supplementary EP Search Report dated Dec. 20, 2007, in corresponding EP Application No. 03721674.4.
Communication forwarding Supplementary EP Search Report dated Dec. 20, 2007, in corresponding EP Application No. 03746989.7.
Communication issued by the Examining Division dated Jun. 20, 2008, in corresponding EP Application No. 03718402.5.
Communication issued by the Examining Division dated Jun. 20, 2008, in corresponding EP Application No. 03721674.4.
Communication issued by the Examining Division dated Jun. 20, 2008, in corresponding EP Application No. 03746989.7.
Communication issued by the Examining Division dated Oct. 30, 2008, in corresponding EP Application No. 05775427.7.
Digital Program Insertion White Paper, nCube, Inc.
DVB Master PCI Bus DVB/ASI Receive or Send Interface, (visited May 14, 2002).
DVB Master PCI Bus DVB/ASI Receive or Send Interface, <http://www.linsys.ca/products/hardware/dvb.htm> (visited May 14, 2002).
FPGA-based MPEG TMultiple-Channel Transport Stream Generator, <http://www.csupomona.edu/~ece/eceweb/program/srproject.html (visited May 14, 2002).
FPGA-based MPEG TMultiple-Channel Transport Stream Generator, <http://www.csupomona.edu/˜ece/eceweb/program/srproject.html (visited May 14, 2002).
FPGA-based MPEG TMultiple-Channel Transport Stream Generator, May 14, 2002 Retrieved online at http://www.csupomona.edu/~ece/eceweb/program/srproject.html.
FPGA-based MPEG TMultiple-Channel Transport Stream Generator, May 14, 2002 Retrieved online at http://www.csupomona.edu/˜ece/eceweb/program/srproject.html.
Implementing Multiprotocol Label Switching with Altera PLDs, Jan 2001.
IP Fragmentation: Questions & Answers, Oct. 28, 1999, pp. 1-4.
MCS4,MPEG2 Stream Controller PCI Card, (visited May 14, 2002).
MCS4,MPEG2 Stream Controller PCI Card, <http://www.norpak.ca/TES8.htm> (visited May 14, 2002).
Microsoft Computer Dictionary, 1999, Microsoft Press, 4th Edition, p. 124.
PCT International Preliminary Examination Report on Patentability issued Apr. 8, 2004, in corresponding International Application No. PCT/US03/11575.
PCT International Preliminary Examination Report on Patentability issued Dec. 12, 2003, in corresponding International Application No. PCT/US03/11576.
PCT International Preliminary Examination Report on Patentability issued Jan. 23, 2007, in corresponding International Application No. PCT/US2005/026011.
PCT International Preliminary Examination Report on Patentability issued Jun. 14, 2004, in corresponding International Application No. PCT/US03/11577.
PCT International Search Report mailed Apr. 6, 2006, in corresponding International Application No. PCT/US2005/026011.
PCT International Search Report mailed Aug. 26, 2003, in corresponding International Application No. PCT/US03/11575.
PCT International Search Report mailed Jul. 24, 2003, in corresponding International Application No. PCT/US03/11576.
PCT International Search Report mailed Jul. 7, 2003, in corresponding International Application No. PCT/US03/11577.
Product Review, Amphion Announces Rijndael Encryption Cores, (visited May 10, 2002).
Product Review, Amphion Announces Rijndael Encryption Cores, <http://www.chipcenter.com/pld/products—600-699/prod627.htm> (visited May 10, 2002).
RFC 2326: "Real Time Streaming Protocol (RTSP)." IETF, Apr. 1998, pp. 1-92.
Shapiro, A., "Fastest Way to Concatenate Strings," Usenet Post to comp.lang.java.programmer, Jan. 31, 1998, 1 page, .
Shapiro, A., "Fastest Way to Concatenate Strings," Usenet Post to comp.lang.java.programmer, Jan. 31, 1998, 1 page, <http://groups.google.com/group/comp.lang.java.programmer/msg/7ee5c7305d4b8148>.
Silicon Server White Paper, Blue Arc, Inc. (2002).
Taiwan Patent Application No. 092109078, Search Report dated Apr. 2, 2009.
Ulmer et al., Active SANs: Hardware Support for Integrating Computation and Communication.
United States Patent and Trademark Office: Final Office Action dated Apr. 13, 2009, U.S. Appl. No. 10/369,305.
United States Patent and Trademark Office: Final Office Action dated Aug. 1, 2008, U.S. Appl. No. 10/369,305.
United States Patent and Trademark Office: Final Office Action dated Dec. 16, 2009, U.S. Appl. No. 10/369,305.
United States Patent and Trademark Office: Final Office Action dated Jan. 12, 2006, U.S. Appl. No. 10/369,305.
United States Patent and Trademark Office: Final Office Action dated Jan. 18, 2007, U.S. Appl. No. 10/369,305.
United States Patent and Trademark Office: Final Office Action dated Oct. 14, 2009, U.S. Appl. No. 10/369,307.
United States Patent and Trademark Office: Final Office Action dated Oct. 3, 2007, U.S. Appl. No. 10/369,307.
United States Patent and Trademark Office: Final Office Action dated Sep. 5, 2008, U.S. Appl. No. 10/369,307.
United States Patent and Trademark Office: Non-Final Office Action dated Apr. 2, 2008, U.S. Appl. No. 10/369,307.
United States Patent and Trademark Office: Non-Final Office Action dated Apr. 21, 2005, U.S. Appl. No. 10/369,305.
United States Patent and Trademark Office: Non-Final Office Action dated Aug. 9, 2007, U.S. Appl. No. 10/369,305.
United States Patent and Trademark Office: Non-Final Office Action dated Dec. 30, 2009, U.S. Appl. No. 10/369,307.
United States Patent and Trademark Office: Non-Final Office Action dated Feb. 11, 2008, U.S. Appl. No. 10/369,305.
United States Patent and Trademark Office: Non-Final Office Action dated Feb. 21, 2007, U.S. Appl. No. 10/369,307.
United States Patent and Trademark Office: Non-Final Office Action dated Jul. 27, 2009, U.S. Appl. No. 10/369,305.
United States Patent and Trademark Office: Non-Final Office Action dated Jun. 16, 2006, U.S. Appl. No. 10/369,307.
United States Patent and Trademark Office: Non-Final Office Action dated Jun. 28, 2006, U.S. Appl. No. 10/369,305.
United States Patent and Trademark Office: Non-Final Office Action dated Mar. 17, 2009, U.S. Appl. No. 10/369,307.
United States Patent and Trademark Office: Non-Final Office Action dated Oct. 24, 2008, U.S. Appl. No. 10/369,305.
US8284802B2 (en) * 2005-11-12 2012-10-09 Liquid Computing Corporation High performance memory based communications interface
AU2003221941A1 (en) 2003-11-03
EP1497666A4 (en) 2008-01-23
TW200308155A (en) 2003-12-16
EP1497666A1 (en) 2005-01-19
WO2003089944A1 (en) 2003-10-30
TWI316341B (en) 2009-10-21
US20030229778A1 (en) 2003-12-11
CA2483017A1 (en) 2003-10-30
US8005966B2 (en) 2011-08-23 Data processing system using internet protocols
EP1730919B1 (en) 2009-03-25 Accelerated tcp (transport control protocol) stack processing
US8218770B2 (en) 2012-07-10 Method and apparatus for secure key management and protection
US7383483B2 (en) 2008-06-03 Data transfer error checking
JP4504977B2 (en) 2010-07-14 Data processing for the tcp connection using an offload unit
JP4444510B2 (en) 2010-03-31 Method and apparatus for delivery of byte code embedded in the transport stream
US6546428B2 (en) 2003-04-08 Methods, systems and computer program products for transferring a file using a message queue
EP1912124B1 (en) 2012-12-05 Apparatus and system for implementation of service functions
US7454610B2 (en) 2008-11-18 Security association updates in a packet load-balanced system
US5983274A (en) 1999-11-09 Creation and use of control information associated with packetized network data by protocol drivers and device drivers
US5802366A (en) 1998-09-01 Parallel I/O network file server architecture
US6038628A (en) 2000-03-14 System and method for encapsulating legacy data transport protocols for IEEE 1394 serial bus
US8631140B2 (en) 2014-01-14 Intelligent network interface system and method for accelerated protocol processing
CN101317166B (en) 2013-04-17 Unified dma
US20080040519A1 (en) 2008-02-14 Network interface device with 10 Gb/s full-duplex transfer rate
CA2548966C (en) 2010-06-01 Increasing tcp re-transmission process speed
EP1358562B1 (en) 2011-11-16 Method and apparatus for controlling flow of data between data processing systems via a memory
Owner name: MIDSTREAM TECHNOLOGIES, INC., WASHINGTON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OESTERREICHER, RICHARD T.;MURPHY, CRAIG;REEL/FRAME:014065/0257;SIGNING DATES FROM 20030408 TO 20030501
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OESTERREICHER, RICHARD T.;MURPHY, CRAIG;SIGNING DATES FROM 20030408 TO 20030501;REEL/FRAME:014065/0257
Free format text: SECURITY INTEREST;ASSIGNOR:MIDSTREAM TECHNOLOGIES, INC.;REEL/FRAME:014079/0191
Owner name: BEACH UNLIMITED LLC, NEVADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MIDSTREAM TECHNOLOGIES, INC.;REEL/FRAME:016277/0032
Free format text: MERGER;ASSIGNOR:BEACH UNLIMITED LLC;REEL/FRAME:036899/0682