Source: http://www.google.com/patents/US7778106?dq=7,634,557
Timestamp: 2015-07-05 13:55:56
Document Index: 19429396

Matched Legal Cases: ['Application No. 096107259', 'Application No. 07', 'Application No. 07', 'Application No. 10', 'Application No. 096107259', 'Application No. 096107259']

Patent US7778106 - Read operation for non-volatile storage with compensation for coupling - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsShifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly...http://www.google.com/patents/US7778106?utm_source=gb-gplus-sharePatent US7778106 - Read operation for non-volatile storage with compensation for couplingAdvanced Patent SearchPublication numberUS7778106 B2Publication typeGrantApplication numberUS 12/357,368Publication dateAug 17, 2010Filing dateJan 21, 2009Priority dateMar 3, 2006Fee statusPaidAlso published asUS7499319, US7613068, US7911838, US8199571, US8427873, US20070206421, US20090129159, US20090129160, US20100074018, US20110141810, US20110225473Publication number12357368, 357368, US 7778106 B2, US 7778106B2, US-B2-7778106, US7778106 B2, US7778106B2InventorsNima MokhlesiOriginal AssigneeSandisk CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (99), Non-Patent Citations (15), Referenced by (4), Classifications (9), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetRead operation for non-volatile storage with compensation for coupling
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5428569Mar 29, 1993Jun 27, 1995Kabushiki Kaisha ToshibaNon-volatile semiconductor memory deviceUS5532962Mar 21, 1995Jul 2, 1996Sandisk CorporationSoft errors handling in EEPROM devicesUS5539690Jun 2, 1994Jul 23, 1996Intel CorporationWrite verify schemes for flash memory with multilevel cellsUS5657332Mar 20, 1995Aug 12, 1997Sandisk CorporationSoft errors handling in EEPROM devicesUS5764572Jun 3, 1997Jun 9, 1998Sgs-Thomson Microelectronics LimitedIntegrated circuit memory deviceUS5862074Oct 6, 1997Jan 19, 1999Samsung Electronics Co., Ltd.Integrated circuit memory devices having reconfigurable nonvolatile multi-bit memory cells therein and methods of operating sameUS5867429Nov 19, 1997Feb 2, 1999Sandisk CorporationHigh density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gatesUS5943260Feb 20, 1998Aug 24, 1999Nec CorporationMethod for high-speed programming of a nonvolatile semiconductor memory deviceUS5946231May 5, 1998Aug 31, 1999Kabushiki Kaisha ToshibaNon-volatile semiconductor memory deviceUS5995417Oct 20, 1998Nov 30, 1999Advanced Micro Devices, Inc.Scheme for page erase and erase verify in a non-volatile memory arrayUS6044019Oct 23, 1998Mar 28, 2000Sandisk CorporationNon-volatile memory with improved sensing and method thereforUS6046935Jan 27, 1999Apr 4, 2000Kabushiki Kaisha ToshibaSemiconductor device and memory systemUS6107658Dec 22, 1999Aug 22, 2000Kabushiki Kaisha ToshibaNon-volatile semiconductor memory deviceUS6144580Dec 8, 1999Nov 7, 2000Cypress Semiconductor Corp.Non-volatile inverter latchUS6154157Nov 25, 1998Nov 28, 2000Sandisk CorporationNon-linear mapping of threshold voltages for analog/multi-level memoryUS6160739Apr 16, 1999Dec 12, 2000Sandisk CorporationNon-volatile memories with improved endurance and extended lifetimeUS6175522Sep 30, 1999Jan 16, 2001Advanced Micro Devices, Inc.Read operation scheme for a high-density, low voltage, and superior reliability nand flash memory deviceUS6181599Apr 13, 1999Jan 30, 2001Sandisk CorporationMethod for applying variable row BIAS to reduce program disturb in a flash memory storage arrayUS6222762Aug 7, 1997Apr 24, 2001Sandisk CorporationMulti-state memoryUS6259632Jan 19, 2000Jul 10, 2001Stmicroelectronics S.R.L.Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memoriesUS6285593May 5, 1999Sep 4, 2001Sandisk CorporationWord-line decoder for multi-bit-per-cell and analog/multi-level memories with improved resolution and signal-to-noise ratioUS6345000Nov 25, 1998Feb 5, 2002Sandisk CorporationFlash memory permitting simultaneous read/write and erase operations in a single memory arrayUS6349055Nov 6, 2000Feb 19, 2002Cypress Semiconductor Corp.Non-volatile inverter latchUS6363014Oct 23, 2000Mar 26, 2002Advanced Micro Devices, Inc.Low column leakage NOR flash array-single cell implementationUS6418061Mar 20, 2000Jul 9, 2002Fujitsu LimitedNon-volatile semiconductor memory device permitting data-read operation performed during data-write/erase operationUS6456528Sep 17, 2001Sep 24, 2002Sandisk CorporationSelective operation of a multi-state non-volatile memory system in a binary modeUS6462988May 17, 1999Oct 8, 2002Sandisk CorporationHighly compact EPROM and flash EEPROM devicesUS6504762Mar 29, 1999Jan 7, 2003Sandisk CorporationHighly compact EPROM and flash EEPROM devicesUS6522580Jun 27, 2001Feb 18, 2003Sandisk CorporationOperating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data statesUS6525969Aug 10, 2001Feb 25, 2003Advanced Micro Devices, Inc.Decoder apparatus and methods for pre-charging bit linesUS6532556Jan 27, 2000Mar 11, 2003Multi Level Memory TechnologyData management for multi-bit-per-cell memoriesUS6535423Dec 29, 2000Mar 18, 2003Intel CorporationDrain bias for non-volatile memoryUS6542407Jan 18, 2002Apr 1, 2003Sandisk CorporationTechniques of recovering data from memory cells affected by field coupling with adjacent memory cellsUS6570785Oct 31, 2000May 27, 2003Sandisk CorporationMethod of reducing disturbs in non-volatile memoryUS6570790Nov 17, 1993May 27, 2003Sandisk CorporationHighly compact EPROM and flash EEPROM devicesUS6614070Jul 10, 2000Sep 2, 2003Cypress Semiconductor CorporationSemiconductor non-volatile memory device having a NAND cell structureUS6643188Jan 22, 2002Nov 4, 2003Kabushiki Kaisha ToshibaNon-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cellUS6657891Feb 4, 2003Dec 2, 2003Kabushiki Kaisha ToshibaSemiconductor memory device for storing multivalued dataUS6717847Aug 26, 2002Apr 6, 2004Sandisk CorporationSelective operation of a multi-state non-volatile memory system in a binary modeUS6717851Jan 10, 2001Apr 6, 2004Sandisk CorporationMethod of reducing disturbs in non-volatile memoryUS6760068Dec 31, 1998Jul 6, 2004Sandisk CorporationCorrection of corrupted elements in sensors using analog/multi-level non-volatile memoryUS6760257Aug 29, 2002Jul 6, 2004Macronix International Co., Ltd.Programming a flash memory cellUS6771536Feb 27, 2002Aug 3, 2004Sandisk CorporationOperating techniques for reducing program and read disturbs of a non-volatile memoryUS6781877Sep 6, 2002Aug 24, 2004Sandisk CorporationTechniques for reducing effects of coupling between storage elements of adjacent rows of memory cellsUS6807095Dec 18, 2002Oct 19, 2004Sandisk CorporationMulti-state nonvolatile memory capable of reducing effects of coupling between storage elementsUS6847553Feb 3, 2003Jan 25, 2005Sandisk CorporationTechniques of recovering data from memory cells affected by field coupling with adjacent memory cellsUS6859397Mar 5, 2003Feb 22, 2005Sandisk CorporationSource side self boosting technique for non-volatile memoryUS6870766Nov 19, 2002Mar 22, 2005Samsung Electronics Co., Ltd.Multi-level flash memory with temperature compensationUS6870768Aug 20, 2004Mar 22, 2005Sandisk CorporationTechniques for reducing effects of coupling between storage elements of adjacent rows of memory cellsUS6888752Jul 1, 2003May 3, 2005Sandisk CorporationMethod of reducing disturbs in non-volatile memoryUS6888758Jan 21, 2004May 3, 2005Sandisk CorporationProgramming non-volatile memoryUS6898121Jan 28, 2003May 24, 2005Sandisk CorporationDeep wordline trench to shield cross coupling between adjacent cells for scaled NANDUS6914817Feb 11, 2003Jul 5, 2005Sandisk CorporationHighly compact EPROM and flash EEPROM devicesUS6956770Sep 17, 2003Oct 18, 2005Sandisk CorporationNon-volatile memory and method with bit line compensation dependent on neighboring operating modesUS6967872Dec 18, 2001Nov 22, 2005Sandisk CorporationMethod and system for programming and inhibiting multi-level, non-volatile memory cellsUS6975538Oct 8, 2003Dec 13, 2005Micron Technology, Inc.Memory block erasing in a flash memory deviceUS7009881Jul 12, 2004Mar 7, 2006Kabushiki Kaisha ToshibaSemiconductor memory deviceUS7020017Apr 6, 2004Mar 28, 2006Sandisk CorporationVariable programming of non-volatile memoryUS7170788Sep 9, 2005Jan 30, 2007Sandisk CorporationLast-first mode and apparatus for programming of non-volatile memory with reduced program disturbUS7310272Jun 2, 2006Dec 18, 2007Sandisk CorporationSystem for performing data pattern sensitivity compensation using different voltageUS7436733Mar 17, 2006Oct 14, 2008Sandisk CorporationSystem for performing read operation on non-volatile storage with compensation for couplingUS7440324Dec 29, 2006Oct 21, 2008Sandisk CorporationApparatus with alternating read modeUS7450421Jun 2, 2006Nov 11, 2008Sandisk CorporationData pattern sensitivity compensation using different voltageUS20020126532Mar 6, 2002Sep 12, 2002Kabushiki Kaisha ToshibaNon-volatile semiconductor memory deviceUS20020159315Mar 29, 2002Oct 31, 2002Kabushiki Kaisha ToshibaSemiconductor memoryUS20040047182Sep 6, 2002Mar 11, 2004Raul-Adrian CerneaTechniques for reducing effects of coupling between storage elements of adjacent rows of memory cellsUS20040057283Sep 24, 2002Mar 25, 2004Sandisk CorporationHighly compact non-volatile memory and method therefor with internal serial busesUS20040057285Sep 24, 2002Mar 25, 2004Sandisk CorporationNon-volatile memory and method with reduced neighboring field errorsUS20040057287Sep 24, 2002Mar 25, 2004Sandisk CorporationNon-volatile memory and method with reduced source line bias errorsUS20040057318Sep 24, 2002Mar 25, 2004Sandisk CorporationNon-volatile memory and method with reduced bit line crosstalk errorsUS20040060031Sep 24, 2002Mar 25, 2004Sandisk CorporationHighly compact non-volatile memory and method thereofUS20040079988Oct 28, 2002Apr 29, 2004Sandisk CorporationFlash memory cell arrays having dual control gates per memory cell charge storage elementUS20040080980Aug 13, 2003Apr 29, 2004Chang-Hyun LeeMethods of programming non-volatile semiconductor memory devices including coupling voltages and related devicesUS20040109357Sep 17, 2003Jun 10, 2004Raul-Adrian CerneaNon-volatile memory and method with improved sensingUS20040153826Aug 19, 2003Aug 5, 2004Nippon Steel CorporationMultilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read programUS20040156241Feb 6, 2003Aug 12, 2004Nima MokhlesiSystem and method for programming cells in non-volatile integrated memory devicesUS20040179404Mar 24, 2004Sep 16, 2004Quader Khandker N.Method and system for programming and inhibiting multi-level, non-volatile memory cellsUS20040190337Apr 5, 2004Sep 30, 2004Jian ChenSelective operation of a multi-state non-volatile memory system in a binary modeUS20040213031Jun 20, 2003Oct 28, 2004Kabushiki Kaisha ToshibaNon-volatile semiconductor memory device and electric device with the sameUS20050057967Sep 17, 2003Mar 17, 2005Shahzad KhalidNon-volatile memory and method with bit line compensation dependent on neighboring operating modesUS20050157564Mar 11, 2005Jul 21, 2005Kabushiki Kaisha ToshibaNon-volatile semiconductor memory device and electric device with the sameUS20050162913Jan 26, 2004Jul 28, 2005Jian ChenMethod of reading NAND memory to compensate for coupling between storage elementsUS20050174852Feb 6, 2004Aug 11, 2005Hemink Gerrit J.Self-boosting system for flash memory cellsUS20050254302Jul 12, 2004Nov 17, 2005Kabushiki Kaisha ToshibaSemiconductor memory deviceUS20060120161Oct 27, 2005Jun 8, 2006Stmicroelectronics S.R.I.Programming method of multilevel memories and corresponding circuitUS20060221660Dec 6, 2005Oct 5, 2006Hemink Gerrit JErasing non-volatile memory using individual verification and additional erasing of subsets of memory cellsUS20060221692Apr 5, 2005Oct 5, 2006Jian ChenCompensating for coupling during read operations on non-volatile memoryUS20070047314Aug 31, 2005Mar 1, 2007Micron Technology, Inc.Programming method for NAND EEPROMUS20070121383Jan 17, 2007May 31, 2007Jian ChenBehavior based programming of non-volatile memoryUS20070206421Mar 17, 2006Sep 6, 2007Nima MokhlesiRead operation for non-volatile storage with compensation for couplingUS20070242510Apr 28, 2006Oct 18, 2007Hermink Gerrit JReducing the impact of program disturb during readUS20080056000Nov 1, 2007Mar 6, 2008Nima MokhlesiSystem for performing data pattern sensitivity compensation using different voltageUS20080056001Nov 1, 2007Mar 6, 2008Nima MokhlesiSystem for performing data pattern sensitivity compensation using different voltageUS20080158946Dec 29, 2006Jul 3, 2008Nima MokhlesiAlternating read modeDE10164149A1Dec 27, 2001Jul 18, 2002Samsung Electronics Co LtdProgramming non-volatile semiconducting memory involves applying voltage sequence to trough regions, programming voltage to word lines as trough area biased by coupling voltageEP1271553A2Jun 26, 2002Jan 2, 2003Kabushiki Kaisha ToshibaOperating techniques for reducing effects of coupling between storage elements of a non-volatile memory in multiple-data statesEP1329898A2Jan 14, 2003Jul 23, 2003SanDisk CorporationTechniques of recovering data from memory cells affected by field coupling with adjacent memory cellsKR20030009090A Title not availableWO2003025512A2Oct 2, 2001Mar 27, 2003Alexei V NikitinMethod and apparatus for analysis of variablesNon-Patent CitationsReference1Aritome, "Reliability Issues of Flash Memory Cells," Proceedings of the IEEE, IEEE. New York, vol. 81, No. 5, May 1, 1993.2English translation of Amended Claims and Drawings filed with Response to Taiwan Office Action dated May 4, 2010, Taiwan Patent Application No. 096107259.3European Office Action dated Jan. 11, 2010, European Patent Application No. 07 751 706.8.4European Official Action dated Mar. 9, 2009 in European Patent Application No. 07 751 706.8.5International Preliminary Report on Patentability dated Jun. 30, 2009 in PCT Application No. PCT/US2007/088787.6International Preliminary Report on Patentability dated Sep. 9, 2008 in PCT Application No. PCT/US2007/004967, filed Feb. 27, 2007.7Korean Office Action dated Apr. 28, 2010, Korean Patent Application No. 10-2008-7023384.8Notice of Allowance and Fee(s) Due dated Mar. 20, 2009 in U.S. Appl. No. 11/933,632.9Notice of Allowance dated Aug. 31, 2009, U.S. Appl. No. 12/357,364, filed Jan. 21, 2009.10Office Action dated Jun. 11, 2009, U.S. Appl. No. 12/357,364, filed Jan. 21, 2009.11Response to Taiwan Office Action dated May 4, 2010, Taiwan Patent Application No. 096107259.12Taiwan Office Action dated Jan. 22, 2010, Taiwan Patent Application No. 096107259.13U.S. Appl. No. 12/357,364, filed Jan. 21, 2009, by Mokhlesi.14Written Opinion of the International Searching Authority dated Jun. 30, 2009 in PCT Application No. PCT/US2007/088787.15Written Opinion of the International Searching Authority, dated Sep. 9, 2008 in PCT Application No. PCT/US2007/004967, filed Feb. 27, 2007.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8233324 *Mar 25, 2010Jul 31, 2012Sandisk Il Ltd.Simultaneous multi-state read or verify in non-volatile storageUS8509000Jun 7, 2012Aug 13, 2013Sandisk Il Ltd.Simultaneous multi-state read or verify in non-volatile storageUS8873285Jul 9, 2013Oct 28, 2014SanDisk II, Ltd.Simultaneous multi-level binary search in non-volatile storageUS20110235420 *Mar 25, 2010Sep 29, 2011Eran SharonSimultaneous multi-state read or verify in non-volatile storage* Cited by examinerClassifications U.S. Classification365/230.06, 365/185.18International ClassificationG11C8/00Cooperative ClassificationG11C11/5642, G11C16/3418, G11C16/0483European ClassificationG11C16/04N, G11C16/34D, G11C11/56D4Legal EventsDateCodeEventDescriptionJan 22, 2009ASAssignmentOwner name: SANDISK CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOKHLESI, NIMA;REEL/FRAME:022139/0212Effective date: 20060317Jun 2, 2011ASAssignmentEffective date: 20110404Owner name: SANDISK TECHNOLOGIES INC., TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:026378/0911Jan 22, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services