Source: http://www.google.com/patents/US6421058?dq=KOI-18
Timestamp: 2016-07-26 14:52:35
Document Index: 139742434

Matched Legal Cases: ['application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'application No. 60', 'Application No. 60', 'Application No. 09', 'application No. 09']

Patent US6421058 - Graphics command stream for calling a display object in a graphics system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes;...http://www.google.com/patents/US6421058?utm_source=gb-gplus-sharePatent US6421058 - Graphics command stream for calling a display object in a graphics systemAdvanced Patent SearchPublication numberUS6421058 B2Publication typeGrantApplication numberUS 09/886,047Publication dateJul 16, 2002Filing dateJun 22, 2001Priority dateOct 28, 1999Fee statusPaidAlso published asUS6424348, US6452600, US6456290, US6466218, US6489963Publication number09886047, 886047, US 6421058 B2, US 6421058B2, US-B2-6421058, US6421058 B2, US6421058B2InventorsVimal Parikh, Robert Moore, Howard ChengOriginal AssigneeNintendo Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (97), Non-Patent Citations (109), Referenced by (112), Classifications (17), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetGraphics command stream for calling a display object in a graphics system
US 6421058 B2Abstract
An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.
We claim: 1. A graphics system command stream for use in a graphics system to call a display list, the command stream comprising:
a bit pattern “01000000”, followed by a pad, followed by a 25-bit value indicating the address of the display list in memory, followed by a pad, followed by a 25-bit value indicating the size of the display list in 32-byte chunks, wherein upon execution of the command stream the display list is called. 2. A computer readable storage medium encoded with executable instructions for calling a display list in memory, comprising:
a bit pattern “01000000”, followed by a bit pattern “0000000”, followed by a 25-bit value indicating the address of the display list in memory, followed by a bit pattern “0000000”, followed by a 25-bit value indicating the size of the display list in 32-byte chunks, wherein upon execution of the encoded instructions the display list is called. 3. A graphics command stream decoder comprising:
a first decoding section decoding a bit pattern “01000000”, a second decoding section decoding a bit pattern “0000000”, a third decoding section decoding a 25-bit value indicating the address of a display list in memory, a fourth decoding section decoding a bit pattern “0000000”, a further decoding section decoding a 25-bit value indicating the size of the display list in 32-byte chunks. 4. A method of calling a display list in a graphics system using a graphics command stream, the method comprising:
generating a bit pattern “01000000”, then generating a bit pattern “0000000”, then generating a 25-bit value indicating the address of the display list in memory, then generating a bit pattern “0000000”, then generating a 25-bit value indicating the size of the display list in 32-byte chunks, wherein upon execution of the command stream the display list is called.
This application is a continuation of U.S. application Ser. No. 09/723,336, filed Nov. 28, 2000.
Application Ser. No. 09/465,754, filed Dec. 17, 1999 of Moore et al. entitled “Vertex Cache For 3D Computer Graphics”; claiming benefit from provisional application No. 60/161,915, filed Oct. 28, 1999,
Application Ser. No. 09/726,215, filed Nov. 28, 2000, of Fouladi et al. entitled “Method and Apparatus for Buffering Graphics Data in a Graphics System” claiming benefit from provisional application No. 60/226,912 filed Aug. 23, 2000;
Application Ser. No. 09/722,367, filed Nov. 28, 2000 of Debrin et al. entitled “Recirculating Shade Tree Blender For A Graphics System” claiming benefit from provisional application No. 60/226,888, filed Aug. 23, 2000;
Application Ser. No. 09/722,663, filed Nov. 28, 2000 of Fouladi et al. entitled “Graphics System With Copi Out Conversions Between Embedded Frame Buffer And Main Memory” claiming benefit from provisional application No. 60/227,030, filed Aug. 23, 2000;
Application Ser. No. 09/722,390, filed Nov. 28, 2000 of Demers, entitled “Low Cost Graphics System With Stitching Hardware Support For Skeletal Animation” claiming benefit from provisional application No. 60/226,914, filed Aug. 23, 2000;
Application Ser. No. 09/726,216, filed Nov. 28, 2000 of Drebin et al., entitled “Achromatic Lighting in a Graphics System and Method” claiming benefit from provisional application No. 60/227,007, filed Aug. 23, 2000.
The present invention relates to computer graphics, and more particularly to interactive graphics systems including but not limited to home video game platforms. Still more particularly this invention relates to an advantageous software programming interface including binary command functions for controlling a graphics chip and to methods for generating, storing and decoding same.
A problem graphics system designers confronted in the past was how to provide a control interface for a graphics system that enables fast, efficient and flexible use of the graphics system by applications designed to be executed thereon. Various application programming interfaces (APIs) and application binary interfaces (ABIs) have been developed in the past for the purpose of enabling graphics application programmers to control the operation of a graphics chip provided in a graphics system. Perhaps the most commonly-used 3D graphics application programming interfaces in current use are Microsoft's Direct3D interface and the OpenGL interface developed through cooperation with Silicon Graphics. See, for example, Kovach, Inside Direct 3D: The Definitive Guide to Real-Time 3D Power and Performance for Microsoft Windows (Microsoft Press 2000); and Neider et al., OpenGL Progamming Guide: The Official Guide to Learning OpenGL Release 1 (Addison-Wesley Publishing Co. 1993).
As explained in the Kovach book, Microsoft's DirectX application programming interface (API) provides a set of interfaces offering efficient control of multimedia hardware on a computer running Microsoft Windows. Kovach states that DirectX lets programmers work with commands and data structures that are very close to those that the hardware can natively process, without being so low level that code has to be written differently for each device. By writing device-independent code, programmers can create software that will theoretically always perform at its best (according to Kovach)—even as users enhance their systems with new and improved 3D graphics accelerators, sound cards, input devices and other system capabilities.
One prior approach is described in U.S. patent application Ser. No. 08/990,133 filed Dec. 12, 1997 by Van Hook et al., entitled “Interface For A High Performance Low Cost Video Game System With Coprocessor Providing High Speed Efficient 3D Graphics And Digital Audio Signal Processing.” However, further improvements are possible and desirable. In particular, some people criticized the interface described in this prior Van Hook et al., patent application because they thought it was difficult to write applications to. In the home video game arena, it is desirable to maximize performance while keeping the interface used to invoke and control such performance and capabilities as simple and easy to use as possible. Requiring application programmers to write to an unduly complicated interface may increase the time it takes to develop such applications. This can have devastatingly negative effects when it comes time to launch a new video game platform—since the success of the platform may often depend on achieving a certain “critical mass” in terms of the number of games or other applications available at launch time. As some developers of prior new home video game platforms found out, no one wants to buy a new video game system if there are no games to play on it. It is therefore desirable to provide a graphics programming interface that is simple and easy to use and yet is very powerful and flexible.
a main memory 112 and
Example system 50 includes a video encoder 120 that receives image signals from graphics and audio processor 114 and converts the image signals into analog and/or digital video signals suitable for display on a standard display device such as a computer monitor or home color television set 56. System 100 also includes an audio codec (compressor/decompressor) 122 that compresses and decompresses digitized audio signals and may also convert between digital and analog audio signaling formats as needed. Audio codec 122 can receive audio inputs via a buffer 124 and provide them to graphics and audio processor 114 for processing (e.g., mixing with other audio signals the processor generates and/or receives via a streaming audio output of mass storage access device 106). Graphics and audio processor 114 in this example can store audio related information in an audio memory 126 that is available for audio tasks. Graphics and audio processor 114 provides the resulting audio output signals to audio codec 122 for decompression and conversion to analog signals (e.g., via buffer amplifiers 128L, 128R) so they can be reproduced by loudspeakers 61L, 61R. Graphics and audio processor 114 has the ability to communicate with various additional devices that may be present within system 100. For example, a parallel digital bus 130 may be used to communicate with mass storage access device 106 and/or other components. A serial peripheral bus 132 may communicate with a variety of peripheral or other devices including, for example:
Command processor 200 receives display commands in binary format from main processor 110 and parses and decodes them—obtaining any additional data necessary to process them from shared memory 112. The command processor 200 provides a stream of vertex commands to graphics pipeline 180 for 2D and/or 3D processing and rendering. Graphics pipeline 180 generates images based on these commands. The resulting image information may be transferred to main memory 112 for access by display controller/video interface unit 164—which displays the frame buffer output of pipeline 180 on display 102.
bump map processing for computing texture coordinate displacements for bump mapping, pseudo texture and texture tiling effects (500 b), and indirect texture processing (500 c).
Texture unit 500 outputs filtered texture values to the texture environment unit 600 for texture environment processing (600 a). Texture environment unit 600 blends polygon and texture color/alpha/depth, and can also perform texture fog processing (600 b) to achieve inverse range based fog effects. Texture environment unit 600 can provide multiple stages to perform a variety of other interesting environment-related functions based for example on color/alpha modulation, embossing, detail texturing, texture swapping, clamping, and depth blending..
As described above, main processor 110 sends graphics commands to graphics and audio processor 114. These graphics commands tell the graphics and audio processor 114 what to do. For example, the graphics commands can tell the graphics and audio processor 114 to draw a particular image onto display device 56. Commands might also tell the graphics and audio processor 114 to produce a particular sound for output by loudspeakers 61. Still other commands might tell the graphics and audio processor 114 to perform so-called “housekeeping” commands and/or to set up a particular state in preparation for a subsequent to “action” command.
Another source of graphics commands for graphics and audio processor 114 is mass storage access device 106. It takes some time for main processor 110 to dynamically create graphics commands. When system 50 is animating a scene in response to real-time inputs from hand controllers 52 or the like, there may be no alternative other than for main processor 110 to dynamically create the graphics commands telling the graphics and audio processor 114 to draw a particular cartoon or other character in a particular position. That way, as the user operates hand controllers 52 of system 50 responds to other input devices, main processor 110 can dynamically adjust or animate the displayed scene in response to those real-time inputs to provide interactive animation. Such fun and exciting interactive animation is generally provided by main processor 110 dynamically creating graphics commands “on the fly.”
In the example embodiment graphics and audio processor 114 may receive register and other commands from main processor 110 and/or some other source (e.g., main memory 112) in the form of a graphics command stream. Generally, the data that is sent from main processor 110 to the graphics and audio processor 114 can be called the “command stream.” The command stream holds drawing commands along with vertices and their attributes and mechanisms for loading registers and changing modes in the graphics pipeline 180. The stream of graphics commands are sent to the graphics and audio processor 114 for processing in a generally sequential manner. Such stream commands can be provided in a so-called “immediate mode” directly from main processor 110 to the graphics and audio processor 114 through a write gatherer arrangement (see FIG. 4) to provide very efficient transfer of graphics and audio commands from the main processor 110 to the graphics and audio processor 114. The graphics command stream can also be provided to graphics and audio processor 114 via main memory 112 or other memory or other data communications capabilities within system 50. The cache/command processor 200 within the graphics and audio processor 114 performs tasks such as, for example, fetching the command stream from main memory 112; fetching vertex attributes (e.g., either from the command stream or from arrays in main memory); converting attribute types to appropriate formats (e.g., floating point); and transferring complete vertices to the remainder of the graphics pipeline 180 for processing.
As shown in FIG. 5, the command stream is fetched from the first-in-first-out buffer 210 (see also above-referenced Provisional Application No. 60/226,912, filed Aug. 23, 2000 and its corresponding utility Application No. 09/726,215, filed Nov. 28, 2000, both entitled “Method and Apparatus for Buffering Graphics Data in a Graphics System”, and read into a FIFO buffer 216. The command processor 200 strips and decodes the commands to decide the number of data associated with it. The data is then taken from the stream and/or fetched from an array in main memory 112, based on an index value. The vertex attributes are converted to floating point data that can be consumed by the transform engine 300.
Opcode (7:0)
10000vat (2:0)
10010vat (2:0)
Draw_Triangle_strip
10011vat (2:0)
10100vat (2:0)
10101vat (2:0)
10110vat (2:0)
10111vat (2:0)
Address [7:0]
(N + 2)*32 bits
(This is used for load-
ing all XF registers,
15:00 register
including matrices. It
address in XF
can be used to load
19:16 number
matrices with
of 32 bit
immediate data)
registers to be
loaded (N + 1,
0 means 1. 0xff
means 16)
Next N + 1 32
31:00 register
11:0 register
15:12 number
of 32 bit data,
(0 means 1,
31:16 Index to
Array D
25:5 address
(need to be 32
byte align)
25:5 count (32
byte count)
VS_Invalidate
0110, SUattr
As shown in Table I above, the graphics command stream can include register load commands. Register commands are, in general, commands that have the effect of writing particular state information to particular registers internal to s the graphics and audio processor 114. The graphics and audio processor 114 has a number of internal registers addressable by main processor 110. To change the state of the graphics and audio processor 114 in particular way, main processor 110 can write a particular value to a particular register internal to the graphics and audio processor 114. Register commands have the advantage of allowing the graphics pipeline to retain drawing state information that main processor 110 can selectively change by sending further register load commands.
For example, the vertices in a draw command can all share the same vertex attribute data structure defining a number of attributes associated with a vertex. Sending all of the vertex attribute information before a draw command could be costly. It therefore may be desirable to store most of the common vertex types in registers within the graphics and audio processor 114, and to simply pass an index to the stored table. These tables may not need to be updated each time a new draw command is sent down, but may only need to be updated every once in a while. In the example embodiment, command processor 200 holds a vertex command descriptor register (VCD) and a eight-entry vertex attribute table (VAT) defining whether the attribute is present and if so whether it is indexed or direct. A “load_VCD” register command is used to update the register whenever updating is necessary.
Register address [7:0]
5:0 index for position/
0 PosMatIndx
3 Tex2atIdex
VCD_-Hi
0111x, vat [2:0]
16:13 ColorDiffused para-
20:17 ColorSpecular para-
29:21 Tex0Coord para-
VAT_group1
1000x, vat [2:0]
08:00 Tex1Coord para-
17:09 Tex2Coord para-
26:18 Tex3Coord para-
30:27 Tex4Coord para-
meters sub-field [3:0]
1001x, vat [2:0]
04:00 Tex4Coord para-
meters sub-field [8:4]
13:05 Tex5Coord para-
22:14 Tex6Coord para-
31:23 Tex7Coord para-
1010, array [3:0]
array [3:0]:
25:00 Base (25:0)
0000 = attribute9 base
0001 = attribute10 base
0010 = attribute11 base
0011 = attribute12 base
0100 = attribute13 base
0101 = attribute14 base
0110 = attribute15 base
0111 = attribute16 base
1000 = attribute17 base
1001 = attribute18 base
1010 = attribute19 base
1011 = attribute20 base
1100 = IndexRegA base
1101 = IndexRegB base
1110 = IndexRegC base
1111 = IndexRegD base
1011, array [3:0]
07:00 Stride (7:0)
0000 = attribute9 stride
stream (in words)
Geometry information in
single precision floating
Color0 per vertex (RGBA)
Color1 per vertex (RGBA)
Sn, Tn in 32b SPFP
FIG. 6 shows an example summary flow chart of steps that may be performed by system 50 under control of an application such as a video game program to develop graphics for display on the display 56. System 50 is first booted from boot ROM 134 (block 610). During or after system boot, main processor 110 and graphics and audio processor 114 are initialized and the operating system is also initialized (block 612). System 50 is then ready to have its logic set up for a specific application, such as a videogame (block 614). The state of the graphics and audio processor 114 is set by sending an appropriate graphics command stream to the graphics and audio processor (block 616). The system 50 is then ready to process vertex information provided through a further command stream describing a primitive in terms of vertex data structure, and draw commands (block 618). Once the embedded frame buffer 702 has a completed frame of data, further commands sent to the graphics and audio processor 114 cause the processor to copy its embedded frame buffer to an external frame buffer 113 allocated in main memory 112 (block 620). The video interface 164 is then used to display the image data in the external frame buffer on a display device (block 622). Once a completed frame is copied from the embedded frame buffer, the system is ready to begin processing the next frame, as indicated by the frame loop 624 in FIG. 6. FIG. 7 shows is greater detail some of the possible graphics commands that can be performed in connection with each of the various steps shown in FIG. 6.
One example initialization may be to clear (set) the internal embedded frame buffer 702 to an all-black color value with z (distance) of the corresponding embedded depth buffer being set to infinite distance at each location. Such a “set copy clear” instruction effectively sets up a clean canvas onto which graphics and audio processor 114 can draw the next image, and is re-formed during an embedded frame buffer copy operation in the example embodiment. FIG. 9 shows an example binary data stream that may be sent to the graphics and audio processor 114 to control it to clear (set) its internal frame buffer 113 to a black color at each and every pixel location and to set the corresponding internal depth buffer to infinite distance at every pixel. In the particular example shown, such a command stream comprises three pixel engine register load commands:
In this example, the first portion of each register load command includes a “cp_cmd_su_bypass” command string (0x61) (where “0x” indicates hexadecimal). As explained in Table I above, this command string provides access to registers within graphics pipeline 180 below transform unit 300. This string is followed by a pixel engine register designation (0x4F in the case of a pixel engine copy clear alpha/red command), a 1-byte pad; and a 1-byte alpha value and a 1-byte red value (FF for black).
In response to receipt of the FIG. 9 commands, pixel engine 700 writes the specified alpha, red, green, blue and z values into embedded frame buffer 702.
Referring once again to FIG. 8, a next step in preparing to display an image onto display 56 may be to define the various data structures associated with the vertices of the primitive to be drawn. The FIG. 10 diagram shows, for purposes of illustration, example vertex and vertex attribute descriptors that can be used to describe vertices. In the example embodiment, all vertices within a given primitive share the same vertex descriptor and vertex attribute format. The vertex descriptor in the example embodiment describes which attributes are present in a particular vertex format and how they are transmitted from the main processor 110 (or other source) to the graphics processor 114 (e.g., either direct or indexed). The vertex attribute format describes the format (e.g., type, size, format, fixed point scale, etc.) of each attribute in a particular vertex format. The vertex attribute format together with the vertex descriptor may be thought of as the overall vertex format.
The following is an example of a vertex attribute table (VAT) (see also above-referenced application Ser. No. 09/465,754 filed Dec. 17, 1999 entitled “Vertex Cache For 3D Computer Graphics”) indexed by a draw command “vat” field, with each entry in the table specifying characteristics for all of the thirteen attributes:
Position/normal matrix index. Always
0: not present
are stored in 2 separate RAMs in the
Xform unit, but there is a one to one
correspondence between normal and
position index. If index “A” is used for
the position, then index “A” needs to be
used for the normal as well.
TexCoord0 matrix index, always direct
00: reserved
Memory address=ArrayBase[I]+index*ArrayStride[I],
where I is the attribute number. In one particular implementation, the ArrayBase value is a 26-bit byte address, and ArrayStride is an 8-bit value.
FIG. 11 shows an example “set array” command used to help define a vertex format (see FIG. 8 block 1004, “Define and Align Vertex Arrays”). In the example embodiment, the example “set array” command sets the command processor array base register for a particular vertex array and also sets the array stride register for the array. FIG. 11 shows particular example binary bit patterns that may be used for this command. In this example, to set an array base register, the graphics command stream may include:
an initial “0x08” value indicating “cp_cmd_load reg” (i.e., load a command processor 200 register) followed by
In this particular example, the 2-byte value indicating which array base register is to be loaded has the format “0xAx”, where the byte “x” following the “A” value encodes a particular one of the attributes set forth in Table IV above. Note that some of the Table IV attributes (i.e., the matrix indices) are not included in the encoding in the example embodiment. In the example embodiment, the 4-byte address in memory is encoded by providing six initial bits of 0 padding followed by a 26-bit address. Setting the array stride register value is similar except that the third and fourth bytes indicate an array stride register (e.g., “0xBx”and the following value comprises four bytes containing an initial 24-bit 0 padded value and an 8-bit stride value for the array.
Referring once again to FIG. 8, a further step preliminary to issuing a draw command may be to set up a vertex descriptor and a vertex attribute table (block 1006). FIG. 12 shows an example command stream used to set a vertex descriptor. In the example embodiment, setting a vertex descriptor involves setting two associated register values (“vcd_lo”“vcd_hi”) within command processor 200 in order to specify the particular vertex descriptor attributes associated with the primitive to be displayed. FIG. 12 shows particular binary encodings used to tell the graphics and audio processor 114 to load the vcd_lo and vcd_hi registers (e.g., “0x0850” for an example vcd_lo register and “0x0860” to specify loading a cp_vcd hi register). Values following each of these 4-byte commands indicates particular vertex attribute values as shown in Table 4 above, and as encoded in the particular binary bit patterns slots shown in FIG. 12.
In more detail, the vertex descriptor stored in the VCD_lo VCD_hi register includes at least one bit for each of the twenty attributes shown in Table IV, that bit generally indicating whether the attribute is provided directly or via an array. In the example embodiment, the VCD_lo register contains a 17-bit value, providing bit flags indicating direct or indexed for each of the first twelve attributes in Table IV. The particular bit encodings are shown in the last column of Table IV. Note that certain attribute encodings indicate whether or not the attribute is present (since the attribute is always direct if it is present), and certain other encodings span multiple bits and provide information as to the type of index if the attribute is indexed (e.g., the “position” value may span two bits with a value “01” for direct, “10” for 8-bit index, and “11” for 16-bit index). Similarly, the VCD_hi register contains bit fields corresponding to attributes 13-20 (i.e., texture 0 coordinate through texture 7 coordinate) as shown in Table IV above.
Color_0, GX_VA_CLR0.
Color_1, GX_VA_CLR1.
A texture matrix index, GX_VA_TEXOMTXIDX-GX_VA_TEX7MTXIDX.
2 GX_VA_TEX0MTXIDX
10 GX_VA_NRM or GX_VA_NBT
11 GX_VA_CLR0 12 GX_VA_CLR1 13 GX_VA_TEX0 14 GX_VA_TEX1 15 GX_VA_TEX2 16 GX_VA_TEX3 17 GX_VA_TEX4 18 GX_VA_TEX5 19 GX_VA_TEX6 20 GX_VA_TEX7 Texture coordinates are enabled sequentially, starting at GX_VA_TEX0 Describing Attribute Data Formats
// format index attribute n elements format n frac bits
GXSetVtxAttrFmt(GX_VTXFMT0, GX_VA_POS, GX_POS_XYZ,
GX_S8, 0);
GXSetVtxAttrFmt(GX_VTXFMT0, GX_VA_CLR0, GX_CLR_RGBA,
GX_RGBA8, 0);
The high-level code above defines vertex attribute format zero. GX_VTXFMT0 indicates that “position” is a 3-element coordinate (x, y, z) where each element is an 8-bit 2's complement signed number. The scale value indicates the number of fractional bits for a fixed-point number, so zero indicates that the data has no fractional bits. The second command specifies that the GX_VA_CLR0 attribute has four elements (r, g, b, a) where each element is 8 bits. The matrix index format is not specified in the table because it is always an unsigned 8-bit value. The scale value is implied for normals (scale=6 or scale=14) and not needed for colors. Also, normals are assumed to have three elements, Nx, Ny, Nz (for GX_VA_NRM), and nine elements, Nx, Ny, N:, Bx, By, Bz, Tx, Ty, Tz (for GX_VA_NBT). Normals are generally always signed values. The normal format (GX_VA_NRM) is also used for binormals/tangents (GX_VA_NBT) when they are enabled in the current vertex descriptor. The VAT in the Graphics Processor has room for eight vertex formats. The application can describe most of its attribute quantization formats early in the application, loading this table as required. Then the application provides an index into this table, which specifies the vertex attribute data format, when it starts drawing a group of primitives. If the application requires more than eight vertex formats it must manage the VAT table by reloading new vertex formats as needed.
FIGS. 13A and 13B show example binary-level commands for controlling the graphics and audio processor 114 to load an example vertex attribute table (VAT). In the example embodiment, the VAT spins three separate register loads (VAT_A, VAT_B, VAT C) so that setting a vertex attribute format involves writing values to three internal “VAT” registers within the graphics and audio processor 114, i.e.:
“0x0870” [4-byte value] to write to the cp_VAT_A register,
“0x0880” [4-byte value] to write to the cp_VAT_B register, and
“0x0890” [4-byte value] to write to the cp_VAT_C register.
As shown in FIG. 13A, the binary bit field encoding for the VAT_A register write involves providing position, normal, color 1, color 2, texture 0 coordinate, and other information (i.e., byte dequantization and normal index bits) in the binary pattern slots shown. Similarly, the binary bit field encoding for the VAT_B register write involves providing formatting information for texture coordinate 1, texture coordinate 2, texture coordinate 3 and part of texture coordinate 4; and the information to be stored in the VAT_C register provides attribute format information for the rest of texture coordinate 4, texture coordinate 5, texture coordinate 6 and texture coordinate 7. FIGS. 13A and 13B show the particular bit pattern encodings that may be used. Additional explanation of these particular attributes is set forth in Table V:
.CompCount
sub-field (0)
.CompSize sub-field (3:1)
.Shift amount sub-field (8:4)
0: ubyte
1: byte
2: ushort
3: short
GX_POINTS—draws a point at each of the n vertices.
GX_LINES—draws a series of unconnected line segments. Segments are drawn between v0 and v1, v2 and v3, etc. The number of vertices drawn should be a multiple of 2.
GX_LINESTRIP—draws a series of connected lines, from v0 to v1, then from v1 to v2, and so on. If n vertices are drawn, n-1 lines are drawn.
GX_TRIANGLES—draws a series of triangles (three-sided polygons) using vertices v0, v1, v2, then v3, v4, v5, and so on. The number of vertices drawn should be a multiple of 3 and the minimum number is 3.
GX_TRIANGLSTRIP—draws a series of triangles (three-sided polygons) using vertices v0, v1, v2, then v1, v3, v2 (note the order), then v2, v3, v4, and so on.
The number of vertices must be at least 3.
GX_TRIANGLEFAN—draws a series of triangles (three-sided polygons) using vertices v0, v1, v2, then v0, v2, v3, and so on. The number of vertices must be at least 3.
GX_QUADS—draws a series of non-planar quadrilaterals (4-sided polygons) beginning with v0, v1, v2, v3, then v4, v5, v6, v7, and so on. The quad is actually drawn using two triangles, so the four vertices are not required to be coplanar it is noted that the diagonal common edge between the two triangles of a quad is oriented as shown in FIG. 11. The minimum number of vertices is 4.
The application draws primitives by calling vertex functions (GXPosition, GXColor, etc.) between GXBegin/GXEnd pairs. The application should call a vertex function for each attribute it enables using GXSetVtxDesc( ). Each vertex function has a suffix of the form GXData[n][t], which describes the number (n) and type (t) of elements passed to the vertex function.
GXPosition1x8(0); // index to position
GXColor1x6(0); // index to color
FIG. 16 shows an example binary bit stream used to load a projection matrix into transform unit 300 (see FIG. 8, block 1004). As described above in connection with FIG. 8, the application generally defines a projection matrix in order to transform a primitive from one space into another space (e.g., object space to world space). The transform unit 300 automatically transforms the vertices in the primitive using this projection matrix.
FIG. 16 shows an example binary bit stream that can be used to load a projection matrix into transform unit 300. In the example embodiment, this loading process involves sending a binary bit pattern of “0x10” to the graphics and audio processor 114 indicating “cp_cmd_xf_loadregs” followed by a 4-byte value. In this 4-byte value, the first eleven bits are 0 padding and the succeeding bits indicate a register address within the transform unit 300 (bits 0-15) and the number of 32-bit registers within the transform unit to be loaded (bits 16-19). Following these bit patterns are a sequence of from one to sixteen 32-bit words specifying projection matrix values.
In the example embodiment, every register in the transform unit 300 is mapped to a unique 32b address. All addresses are available to the xform register load command (command 0�30). The first block is formed by the matrix memory. Its address range is 0 to 1 k, but only 256 entries are used. This memory is organized in a 64 entry by four 32b words. Each word has a unique address and is a single precision floating point number. For block writes, the addresses auto increment. The memory is implemented in less than 4-32b rams, then it is possible that the memory writes to this block will require a minimum write size larger than 1 word:
The second block of memory is mapped to the 1 k˜1.5 k range. This memory is the normal matrix memory. It is organized as 32 rows of 3 words. Each word has a unique address and is a single precision floating point number. Also, each word written is 32b, but only the 20 most significant bits are kept. For simplicity, the minimum granularity of writes will be 3 words:
Normal Ram words 0, 1, 2
The fourth block of memory is the light memory. This holds all the lighting information (light vectors, light parameters, etc.). Both global state and ambient state are stored in this memory. Each word written is 32b, but only the 20 most significant bits are kept. Each row is 3 words wide. Minimum word write size is 3 words.
As described in the above-referenced patent application No. 09/726,215, filed Nov. 28, 2000 entitled “Method and Apparatus for Buffering Graphics Data in a Graphics System,” system 50 includes a capability for calling a display list. FIG. 17 shows an example binary bit stream format used to call a display object such as a display list. In the example shown, the binary bit pattern format includes an initial “0x40” indicating “CP_CMD_CALLOBJECT”, followed by a 4-byte address of the display list in memory as well as a 4-byte count or size of the display list. The 4-byte address field may include an initial seven bits of 0 padding followed by a 25-bit value. The 4-byte count value may include an initial seven bits of padding followed by a 25-bit count value indicating the count or size of the display list in 32-byte chunks.
As one example, in the case where the software is written for execution on a platform using an IBM PowerPC or other specific processor and the host 1201 is a personal computer using a different (e.g., Intel) processor, emulator 1203 fetches one or a sequence of binary-image program instructions from storage medium 1305 and converts these program instructions to one or more equivalent Intel binary-image program instructions. The emulator 1203 also fetches and/or generates graphics commands and audio commands intended for processing by the graphics and audio processor 114, and converts these commands into a format or formats that can be processed by hardware and/or software graphics and audio processing resources available on host 1201. As one example, emulator 1303 may convert these commands into commands that can be processed by specific graphics and/or sound hardware of the host 1201 (e.g., using standard DirectX, OpenGL and/or sound APIs).
//Color value to clear the framebuffer to during copy.
//24 bit Z value to clear the framebuffer to during copy.
//Index into the Vertex Attribute Table (0-7).
//Locatin of decimal point for fixed point format types.
//Address (25:0) of the attribute data array in main memory.
//Number of bytes between successive elements in the attribute array.
//Indicates if the projection is orthographic.
Perspective Projection [ X Y Z W ] = [ p   0 0 p   1 0 0 p   2 p   3 0 0 0 p   4 p   5 0 0 - 1 0 ]  [ Xe Ye Ze 1 ] Orthographic Projection: [ X Y Z W ] = [ p   0 0 0 p   1 0 p   2 0 p   3 0 0 p   4 p   5 0 0 0 1 ]  [ Xe Ye Ze 1 ] All documents referred to herein are expressly incorporated by reference as if expressly set forth.
As used herein, the notation “0x” indicates a hexadecimal value. For example, “0x61” indicates a hexadecimal value. For example, “0x61” indicates a two-byte hexadecimal value of “61”—which people of ordinary skill in the art understand has a binary format of “01100001”. See Table VI below for conversion of hexadecimal notation to binary notation:
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Updates in a Windowing System Using a Programmable Graphics Processing Unit* Cited by examinerClassifications U.S. Classification345/522, 345/553, 712/208, 711/E12.02, 345/567, 719/328International ClassificationG06T15/00, G06T15/04, G06F12/08Cooperative ClassificationG06T15/04, A63F2300/203, G06T15/005, G06F12/0875, G06T2210/32European ClassificationG06T15/04, G06T15/00A, G06F12/08B14Legal EventsDateCodeEventDescriptionDec 28, 2005FPAYFee paymentYear of fee payment: 4Dec 22, 2009FPAYFee paymentYear of fee payment: 8Dec 30, 2013FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services