Source: https://patents.justia.com/patent/10325986
Timestamp: 2019-08-18 04:57:27
Document Index: 328951368

Matched Legal Cases: ['Application No. 61', 'Application No. 61', 'Application No. 61', 'artz\n20070040222', 'Application No. 201180035830', 'Application No. 10', 'Application No. 2016', 'Application No. 2016', 'Application No. 2012', 'Application No. 2012', 'Application No. 2012', 'Application No. 2012', 'Application No. 201180019710', 'Application No. 201080054378', 'Application No. 201180019710', 'Application No. 2012', 'Application No. 2015144418', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'application No. 2015', 'Application No. 10', 'Application No. 10', 'Application No. 10']

US Patent for Advanced transistors with punch through suppression Patent (Patent # 10,325,986 issued June 18, 2019) - Justia Patents Search
Justia Patents Characterized By Sectional Shape, E.g., T-shape, Inverted T, Spacer (epo)US Patent for Advanced transistors with punch through suppression Patent (Patent # 10,325,986)
Oct 20, 2016 - MIE FUJITSU SEMICONDUCTOR LIMITED
An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
This application is a continuation of U.S. application Ser. No. 14/977,887 filed Dec. 22, 2015 which is a divisional of U.S. application Ser. No. 14/188,218 filed Feb. 24, 2014 which is a divisional of Ser. No. 13/787,073 filed Mar. 6, 2013, now abandoned, which is a continuation of U.S. application Ser. No. 12/895,813 now U.S. Pat. No. 8,421,162 which claims the benefit of U.S. Provisional Application No. 61/357,492 filed Jun. 22, 2010, and is a CIP of U.S. application Ser. No. 12/708,497 filed Feb. 18, 2010, now U.S. Pat. No. 8,273,617, and claims benefit of U.S. Provisional Application No. 61/262,122 filed Nov. 17, 2009 and U.S. Provisional Application No. 61/247,300 filed Sep. 30, 2009, the disclosure of each being incorporated by reference herein.
This disclosure relates to structures and processes for forming advanced transistors with improved operational characteristics, including enhanced punch through suppression.
Fitting more transistors onto a single die is desirable to reduce cost of electronics and improve their functional capability. A common strategy employed by semiconductor manufacturers is to simply reduce gate size of a field effect transistor (FET), and proportionally shrink area of the transistor source, drain, and required interconnects between transistors. However, a simple proportional shrink is not always possible because of what are known as “short channel effects”. Short channel effects are particularly acute when channel length under a transistor gate is comparable in magnitude to depletion depth of an operating transistor, and include reduction in threshold voltage, severe surface scattering, drain induced barrier lowering (DIBL), source-drain punch through, and electron mobility issues.
Conventional solutions to mitigate some short channel effects can involve implantation of pocket or halo implants around the source and the drain. Halo implants can be symmetrical or asymmetrical with respect to a transistor source and drain, and typically provide a smoother dopant gradient between a transistor well and the source and drains. Unfortunately, while such implants improve some electrical characteristics such as threshold voltage rolloff and drain induced barrier lowering, the resultant increased channel doping adversely affects electron mobility, primarily because of the increased dopant scattering in the channel.
Many semiconductor manufacturers have attempted to reduce short channel effects by employing new transistor types, including fully or partially depleted silicon on insulator (SOI) transistors. SOI transistors are built on a thin layer of silicon that overlies an insulator layer, have an undoped or low doped channel that minimizes short channel effects, and do not require either deep well implants or halo implants for operation. Unfortunately, creating a suitable insulator layer is expensive and difficult to accomplish. Early SOI devices were built on insulative sapphire wafers instead of silicon wafers, and are typically only used in specialty applications (e.g. military avionics or satellite) because of the high costs. Modem SOI technology can use silicon wafers, but require expensive and time consuming additional wafer processing steps to make an insulative silicon oxide layer that extends across the entire wafer below a surface layer of device-quality single-crystal silicon.
One common approach to making such a silicon oxide layer on a silicon wafer requires high dose ion implantation of oxygen and high temperature annealing to form a buried oxide (BOX) layer in a bulk silicon wafer. Alternatively, SOI wafers can be fabricated by bonding a silicon wafer to another silicon wafer (a “handle” wafer) that has an oxide layer on its surface. The pair of wafers are split apart, using a process that leaves a thin transistor quality layer of single crystal silicon on top of the BOX layer on the handle wafer. This is called the “layer transfer” technique, because it transfers a thin layer of silicon onto a thermally grown oxide layer of the handle wafer.
As would be expected, both BOX formation or layer transfer are costly manufacturing techniques with a relatively high failure rate. Accordingly, manufacture of SOI transistors not an economically attractive solution for many leading manufacturers. When cost of transistor redesign to cope with “floating body” effects, the need to develop new SOI specific transistor processes, and other circuit changes is added to SOI wafer costs, it is clear that other solutions are needed.
Another possible advanced transistor that has been investigated uses multiple gate transistors that, like SOI transistors, minimize short channel effects by having little or no doping in the channel. Commonly known as a finFET (due to a fin-like shaped channel partially surrounded by gates), use of finFET transistors has been proposed for transistors having 28 nanometer or lower transistor gate size. But again, like SOI transistors, while moving to a radically new transistor architecture solves some short channel effect issues, it creates others, requiring even more significant transistor layout redesign than SOI. Considering the likely need for complex non-planar transistor manufacturing techniques to make a finFET, and the unknown difficulty in creating a new process flow for finFET, manufacturers have been reluctant to invest in semiconductor fabrication facilities capable of making finFETs.
A more complete understanding of embodiments of the invention will be apparent from the detailed description taken in conjunction with the accompanying drawings wherein like reference numerals represent like parts, in which:
FIG. 1 illustrates a DDC transistor with a punch through suppression;
FIG. 2 illustrates a dopant profile of a DDC transistor with enhanced punch through suppression;
FIGS. 3-7 illustrate alternative useful dopant profiles; and
FIG. 8 is a flow diagram illustrating one exemplary process for forming a DDC transistor with a punch through suppression.
Unlike silicon on insulator (SOI) transistors, nanoscale bulk CMOS transistors (those typically having a gate length less than 100 nanometers) are subject to significant adverse short channel effects, including body leakage through both drain induced barrier lowering (DIBL) and source drain punch through. Punch through is associated with the merging of source and drain depletion layers, causing the drain depletion layer to extend across a doped substrate and reach the source depletion layer, creating a conduction path or leakage current between the source and drain. This results in a substantial increase in required transistor electrical power, along with a consequent increase in transistor heat output and decrease in operational lifetime for portable or battery powered devices using such transistors.
An improved transistor manufacturable on bulk CMOS substrates is seen in FIG. 1. A Field Effect Transistor (FET) 100 is configured to have greatly reduced short channel effects, along with enhanced punch through suppression according to certain described embodiments. The FET 100 includes a gate electrode 102, source 104, drain 106, and a gate dielectric 108 positioned over a channel 110. In operation, the channel 110 is deeply depleted, forming what can be described as deeply depleted channel (DDC) as compared to conventional transistors, with depletion depth set in part by a highly doped screening region 112. While the channel 110 is substantially undoped, and positioned as illustrated above a highly doped screening region 112, it may include simple or complex layering with different dopant concentrations. This doped layering can include a threshold voltage set region 111 with a dopant concentration less than screening region 112, optionally positioned between the gate dielectric 108 and the screening region 112 in the channel 110. A threshold voltage set region 111 permits small adjustments in operational threshold voltage of the FET 100, while leaving the bulk of the channel 110 substantially undoped. In particular, that portion of the channel 110 adjacent to the gate dielectric 108 should remain undoped. Additionally, a punch through suppression region 113 is formed beneath the screening region 112. Like the threshold voltage set region 111, the punch through suppression region 113 has a dopant concentration less than screening region 112, while being higher than the overall dopant concentration of a lightly doped well substrate 114.
In operation, a bias voltage 122 VBS may be applied to source 104 to further modify operational threshold voltage, and P+ terminal 126 can be connected to P-well 114 at connection 124 to close the circuit. The gate stack includes a gate electrode 102, gate contact 118 and a gate dielectric 108. Gate spacers 130 are included to separate the gate from the source and drain, and optional Source/Drain Extensions (SDE) 132, or “tips” extend the source and drain under the gate spacers and gate dielectric 108, somewhat reducing the gate length and improving electrical characteristics of FET 100.
In this exemplary embodiment, the FET 100 is shown as an N-channel transistor having a source and drain made of N-type dopant material, formed upon a substrate as P-type doped silicon substrate providing a P-well 114 formed on a substrate 116. However, it will be understood that, with appropriate change to substrate or dopant material, a nonsilicon P-type semiconductor transistor formed from other suitable substrates such as Gallium Arsenide based materials may be substituted. The source 104 and drain 106 can be formed using conventional dopant implant processes and materials, and may include, for example, modifications such as stress inducing source/drain structures, raised and/or recessed source/drains, asymmetrically doped, counter-doped or crystal structure modified source/drains, or implant doping of source/drain extension regions according to LDD (low doped drain) techniques. Various other techniques to modify source/drain operational characteristics can also be used, including, in certain embodiments, use of heterogeneous dopant materials as compensation dopants to modify electrical characteristics.
The gate electrode 102 can be formed from conventional materials, preferably including, but not limited to, metals, metal alloys, metal nitrides and metal silicides, as well as laminates thereof and composites thereof. In certain embodiments the gate electrode 102 may also be formed from polysilicon, including, for example, highly doped polysilicon and polysilicon-germanium alloy. Metals or metal alloys may include those containing aluminum, titanium, tantalum, or nitrides thereof, including titanium containing compounds such as titanium nitride. Formation of the gate electrode 102 can include silicide methods, chemical vapor deposition methods and physical vapor deposition methods, such as, but not limited to, evaporative methods and sputtering methods. Typically, the gate electrode 102 has an overall thickness from about 1 to about 500 nanometers.
The gate dielectric 108 may include conventional dielectric materials such as oxides, nitrides and oxynitrides. Alternatively, the gate dielectric 108 may include generally higher dielectric constant dielectric materials including, but not limited to hafnium oxides, hafnium silicates, zirconium oxides, lanthanum oxides, titanium oxides, barium-strontium-titanates and lead-zirconate-titanates, metal based dielectric materials, and other materials having dielectric properties. Preferred hafnium-containing oxides include HfO2, HfZrOx, HfSiOx, HfTiOx, HfAlOx, and the like. Depending on composition and available deposition processing equipment, the gate dielectric 108 may be formed by such methods as thermal or plasma oxidation, nitridation methods, chemical vapor deposition methods (including atomic layer deposition methods) and physical vapor deposition methods. In some embodiments, multiple or composite layers, laminates, and compositional mixtures of dielectric materials can be used. For example, a gate dielectric can be formed from a SiO2-based insulator having a thickness between about 0.3 and 1 nm and the hafnium oxide based insulator having a thickness between 0.5 and 4 nm. Typically, the gate dielectric has an overall thickness from about 0.5 to about 5 nanometers.
The channel region 110 is formed below the gate dielectric 108 and above the highly doped screening region 112. The channel region 110 also contacts and extends between, the source 104 and the drain 106. Preferably, the channel region includes substantially undoped silicon having a dopant concentration less than 5×1017 dopant atoms per cm3 adjacent or near the gate dielectric 108. Channel thickness can typically range from 5 to 50 nanometers. In certain embodiments the channel region 110 is formed by epitaxial growth of pure or substantially pure silicon on the screening region.
As disclosed, the threshold voltage set region 111 is positioned under the gate dielectric 108, spaced therefrom, and above screening region 112, and is typically formed as a thin doped layer. Suitably varying dopant concentration, thickness, and separation from the gate dielectric and the screening region allows for controlled slight adjustments of threshold voltage in the operating FET 100. In certain embodiments, the threshold voltage set region 111 is doped to have a concentration between about 1×1018 dopant atoms per cm3 and about 1×1019 dopant atoms per cm3. The threshold voltage set region 111 can be formed by several different processes, including 1) in-situ epitaxial doping, 2) epitaxial growth of a thin layer of silicon followed by a tightly controlled dopant implant, 3) epitaxial growth of a thin layer of silicon followed by dopant diffusion of atoms from the screening region 112, or 4) by any combination of these processes (e.g. epitaxial growth of silicon followed by both dopant implant and diffusion from the screening layer 112).
Position of a highly doped screening region 112 typically sets depth of the depletion zone of an operating FET 100. Advantageously, the screening region 112 (and associated depletion depth) are set at a depth that ranges from one comparable to the gate length (Lg/1) to a depth that is a large fraction of the gate length (Lg/5). In preferred embodiments, the typical range is between Lg/3 to Lg/1.5. Devices having an Lg/2 or greater are preferred for extremely low power operation, while digital or analog devices operating at higher voltages can often be formed with a screening region between Lg/5 and Lg/2. For example, a transistor having a gate length of 32 nanometers could be formed to have a screening region that has a peak dopant density at a depth below the gate dielectric of about 16 nanometers (Lg/2), along with a threshold voltage set region at peak dopant density at a depth of 8 nanometers (Lg/4).
In certain embodiments, the screening region 112 is doped to have a concentration between about 5×1018 dopant atoms per cm3 and about 1×1020 dopant atoms per cm3, significantly more than the dopant concentration of the undoped channel, and at least slightly greater than the dopant concentration of the optional threshold voltage set region 111. As will be appreciated, exact dopant concentrations and screening region depths can be modified to improve desired operating characteristics of FET 100, or to take in to account available transistor manufacturing processes and process conditions.
To help control leakage, the punch through suppression region 113 is formed beneath the screening region 112. Typically, the punch through suppression region 113 is formed by direct implant into a lightly doped well, but it may be formed by out-diffusion from the screening region, in-situ growth, or other known process. Like the threshold voltage set region 111, the punch through suppression region 113 has a dopant concentration less than the screening region 112, typically set between about 1×1018 dopant atoms per cm3 and about 1×1019 dopant atoms per cm3. In addition, the punch through suppression region 113 dopant concentration is set higher than the overall dopant concentration of the well substrate. As will be appreciated, exact dopant concentrations and depths can be modified to improve desired operating characteristics of FET 100, or to take in to account available transistor manufacturing processes and process conditions.
Forming such a FET 100 is relatively simple compared to SOI or finFET transistors, since well developed and long used planar CMOS processing techniques can be readily adapted.
Together, the structures and the methods of making the structures allow for FET transistors having both a low operating voltage and a low threshold voltage as compared to conventional nanoscale devices. Furthermore, DDC transistors can be configured to allow for the threshold voltage to be statically set with the aid of a voltage body bias generator. In some embodiments the threshold voltage can even be dynamically controlled, allowing the transistor leakage currents to be greatly reduced (by setting the voltage bias to upwardly adjust the VT for low leakage, low speed operation), or increased (by downwardly adjusting the VT for high leakage, high speed operation). Ultimately, these structures and the methods of making structures provide for designing integrated circuits having FET devices that can be dynamically adjusted while the circuit is in operation. Thus, transistors in an integrated circuit can be designed with nominally identical structure, and can be controlled, modulated or programmed to operate at different operating voltages in response to different bias voltages, or to operate in different operating modes in response to different bias voltages and operating voltages. In addition, these can be configured post-fabrication for different applications within a circuit.
As will be appreciated, concentrations of atoms implanted or otherwise present in a substrate or crystalline layers of a semiconductor to modify physical and electrical characteristics of a semiconductor are be described in terms of physical and functional regions or layers. These may be understood by those skilled in the art as three-dimensional masses of material that have particular averages of concentrations. Or, they may be understood as sub-regions or sub-layers with different or spatially varying concentrations. They may also exist as small groups of dopant atoms, regions of substantially similar dopant atoms or the like, or other physical embodiments. Descriptions of the regions based on these properties are not intended to limit the shape, exact location or orientation. They are also not intended to limit these regions or layers to any particular type or number of process steps, type or numbers of layers (e.g., composite or unitary), semiconductor deposition, etch techniques, or growth techniques utilized. These processes may include epitaxially formed regions or atomic layer deposition, dopant implant methodologies or particular vertical or lateral dopant profiles, including linear, monotonically increasing, retrograde, or other suitable spatially varying dopant concentration. To ensure that desired dopant concentrations are maintained, various dopant anti-migration techniques are contemplated, including low temperature processing, carbon doping, in-situ dopant deposition, and advanced flash or other annealing techniques. The resultant dopant profile may have one or more regions or layers with different dopant concentrations, and the variations in concentrations and how the regions or layers are defined, regardless of process, mayor may not be detectable via techniques including infrared spectroscopy, Rutherford Back Scattering (RBS), Secondary Ion Mass Spectroscopy (SIMS), or other dopant analysis tools using different qualitative or quantitative dopant concentration determination methodologies.
To better appreciate one possible transistor structure, FIG. 2 illustrates a dopant profile 202 of a deeply depleted transistor taken at midline between a source and drain, and extending downward from a gate dielectric toward a well. Concentration is measured in number of dopant atoms per cubic centimeter, and downward depth is measured as a ratio of gate length Lg. Measuring as a ratio rather than absolute depth in nanometers better allows cross comparison between transistors manufactured at different nodes (e.g. 45 nm, 32 nm, 22 nm, or 15 nm) where nodes are commonly defined in term of minimum gate lengths.
As seen in FIG. 2, the region of the channel 210 adjacent to the gate dielectric is substantially free of dopants, having less than 5×1017 dopant atoms per cm3 to a depth of nearly Lg/4. A threshold voltage set region 211 increases the dopant concentration to about 3×1018 dopant atoms per cm3, and the concentration increases another order of magnitude above 3×1018 dopant atoms per cm3 to form the screening region 212 that sets the base of the depletion zone in an operating transistor. A punch through suppression region 213 having a dopant concentration of about 1×1019 dopant atoms per cm3 at a depth of about Lg/1 is intermediate between the screening region and the lightly doped well 214. Without the punch through suppression region, a transistor constructed to have, for example, a 30 nm gate length and an operating voltage of 1.0 volts would be expected to have significantly greater leakage. When the disclosed punch through suppression region is implanted, punch through leakage is reduced, making the transistor more power efficient, and better able to tolerate process variations in transistor structure without punch through failure.
This is better seen with respect to the following Table 1, which indicates expected performance improvements for a range of punch through dosage and threshold voltage:
TABLE 1 Ioff (nA/um) Idsat (mA/um) Vt (V)
Target Punchthrough layer 2 0.89 0.31 No Punchthrough layer 70 1 0.199 Higher Dose Punchthrough 0.9 0.54 0.488 Very deep Punchthrough 15 1 0.237
Alternative dopant profiles are contemplated. As seen in FIG. 3, an alternative dopant profile 203 that includes a slightly increased depth for the low doped channel is shown. In contrast to the embodiments of FIG. 2, the threshold voltage set region 211 is a shallow notch primarily formed by out-diffusion into an epitaxially deposited layer of silicon from the screening region 212. The screening region 212 itself is set to have a dopant concentration greater than 3×1019 dopant atoms per cm3. The punch through suppression region 213 has a dopant concentration of about 8×1018 dopant atoms per cm3, provided by a combination of out-diffusion from the screening region 212 and a separate low energy implant.
As seen in FIG. 4, an alternative dopant profile 204 that includes a greatly increased depth for the low doped channel is shown. In contrast to the embodiments of FIGS. 2 and 3, there is no distinct notch, plane or layer to aid in threshold voltage setting. The screening region 212 is set to be greater than 3×1019 dopant atoms per cm3 and the punch through suppression region 213 has a similarly high, yet narrowly defined dopant concentration of about 8×1018 dopant atoms per cm3, provided by with a separate low energy implant.
Yet another variation in dopant profile is seen in FIG. 5, which illustrates a transistor dopant profile 205 for a transistor structure that includes a very low doped channel 210. The threshold voltage set region 211 is precisely formed by in-situ or well controlled implant doping of thin epitaxial layer grown on the screening region. The screening region 212 is set to be about 1×1019 dopant atoms per cm3 and the punch through suppression region 213 also has narrowly defined dopant concentration of about 8×1018 dopant atoms per cm3, provided by with a separate low energy implant. The well implant 214 concentration is gradually reduced to about 5×1017 dopant atoms per cm3.
As seen in FIG. 6, a dopant profile 206 includes a low doped channel 210 adjacent to the gate dielectric, and a narrowly defined threshold voltage set region 211. The screening region 212 increases to a narrow peak set to be about 1×1019 dopant atoms per cm3 and the punch through suppression region 213 also has broadly peak dopant concentration of about 5×1018 dopant atoms per cm3, provided by with a separate low energy implant. The well implant 214 concentration is high to improve bias coefficient of the transistor, with a concentration of about 8×1017 dopant atoms per cm3.
In contrast to the narrow screen region peak dopant concentration of FIG. 6, the dopant profile 207 of FIG. 7 has a broad peak 212. In addition to a narrow undoped channel 210, the transistor structure includes a well defined partially retrograde threshold set 211, and a distinct separate punch through suppression peak 213. The well 214 doping concentration is relatively low, less than about 5×1017 dopant atoms per cm3.
FIG. 8 is a schematic process flow diagram 300 illustrating one exemplary process for forming a transistor with a punch through suppression region and a screening region suitable for different types of FET structures, including both analog and digital transistors. The process illustrated here is intended to be general and broad in its description in order not to obscure the inventive concepts, and more detailed embodiments and examples are set forth below. These along with other process steps allow—for the processing and manufacture of integrated circuits that include DDC structured devices together with legacy devices, allowing for designs to cover a full range of analog and digital devices with improved performance and lower power.
In Step 302, the process begins at the well formation, which may be one of many different processes according to different embodiments and examples. As indicated in 303, the well formation may be before or after STI (shallow trench isolation) formation 304, depending on the application and results desired. Boron (B), indium (I) or other P-type materials may be used for P-type implants, and arsenic (As) or phosphorous (P) and other N-type materials may be used for N-type implants. For the PMOS well implants, the P+ implant may be implanted within a range from 10 to 80 keV, and at NMOS well implants, the boron implant B+ implant may be within a range of 0.5 to 5 keV, and within a concentration range of 1×1013 to 8×1013/cm2. A germanium implant Ge+, may be performed within a range of 10 to 60 keV, and at a concentration of 1×1014 to 5×1014/cm2. To reduce dopant migration, a carbon implant, C+ may be performed at a range of 0.5 to 5 keV, and at a concentration of 1×1013 to 8×1013/cm2. Well implants may include sequential implant, and/or epitaxial growth and implant, of punch through suppression regions, screen regions having a higher dopant density than the punch through suppression region, and threshold voltage set regions (which previously discussed are typically formed by implant or diffusion of dopants into a grown epitaxial layer on the screening region).
In some embodiments the well formation 302 may include a beam line implant of Ge/B (N), As (P), followed by an epitaxial (EPI) pre-clean process, and followed finally non-selective blanket EPI deposition, as shown in 302A. Alternatively, the well may be formed using a plasma implant of B (N), As (P), followed by an EPI pre-clean, then finally a non-selective (blanket) EPI deposition, 302B. The well formation may alternatively include a solid-source diffusion of B(N), As(P), followed by an EPI pre-clean, and followed finally by a non-selective (blanket) EPI deposition, 302C. The well formation may alternatively include a solid-source diffusion of B (N), As (P), followed by an EPI pre-clean, and followed finally by a non-selective (blanket) EPI deposition, 302D. As yet another alternative, well formation may simply include well implants, followed by in-situ doped selective EPI of B (N), P (P). Embodiments described herein allow for anyone of a number of devices configured on a common substrate with different well structures and according to different parameters.
Shallow trench isolation (STI) formation 304, which, again, may occur before or after well formation 302, may include a low temperature trench sacrificial oxide (TSOX) liner 304A at a temperature lower than 900° C. The gate stack 306 may be formed or otherwise constructed in a number of different ways, from different materials, and of different work functions. One option is a poly/SiON gate stack 306A. Another option is a gate-first process 306B that includes SiON/Metal/Poly and/or SiON/Poly, followed by High-K/Metal Gate. Another option, a gate-last process 306C includes a high-K/metal gate stack wherein the gate stack can either be formed with “Hi-K first-Metal gate last” flow or and “Hi-K last-Metal gate last” flow. Yet another option, 306D is a metal gate that includes a tunable range of work functions depending on the device construction, N(NMOS)/P(PMOS)N(PMOS)/P(NMOS)/Mid-gap or anywhere in between. In one example, N has a work function (WF) of 4.05 V±200 mV, and P has a WF of 5.01 V±200 mV.
Next, in Step 308, Source/Drain tips may be implanted, or optionally may not be implanted depending on the application. The dimensions of the tips can be varied as required, and will depend in part on whether gate spacers (SPCR) are used. In one option, there may be no tip implant in 308A. Next, in optional steps 310 and 312, PMOS or NMOS EPI layers may be formed in the source and drain regions as performance enhancers for creating strained channels. For gate-last gate stack options, in Step 314, a Gate-last module is formed. This may be only for gate-last processes 314A.
Die supporting multiple transistor types, including those with and without a punch through suppression, those having different threshold voltages, and with and without static or dynamic biasing are contemplated. Systems on a chip (SoC), advanced microprocessors, radio frequency, memory, and other die with one or more digital and analog transistor configurations can be incorporated into a device using the methods described herein. According to the methods and processes discussed herein, a system having a variety of combinations of DDC and/or transistor devices and structures with or without punch through suppression can be produced on silicon using bulk CMOS. In different embodiments, the die may be divided into one or more areas where dynamic bias structures, static bias structures or no-bias structures exist separately or in some combination. In a dynamic bias section, for example, dynamically adjustable devices may exist along with high and low VT devices and possibly DDC logic devices.
1. A field effect transistor structure having a gate dielectric under a gate with length Lg, comprising:
a well in the substrate doped to have a first concentration of a first conductivity type dopant,
a substantially undoped channel under the gate dielectric and extending to a source and a drain, the source and the drain being doped to have a second conductivity type dopant different from the first conductivity type dopant, the substantially undoped channel having a second concentration of the first conductivity type dopant less than the first concentration,
a screening region positioned above the well and under the gate dielectric, the screening region extending to the source and drain and having a third concentration of the first conductivity type dopant, the screening region setting a depth of a depletion region below the gate in a direction from the substantially undoped channel toward the screening region, a ratio of the third concentration to the second concentration being more than ten, a profile of the first conductivity type dopant having a peak in the screening region,
at least one punch through suppression region having a fourth concentration of the first conductivity type dopant intermediate between the first concentration and the third concentration, with the punch through suppression region positioned above the well and beneath the screening region, and
a threshold voltage set region having a fifth concentration of the first conductivity type dopant intermediate between the second concentration and the third concentration, with the threshold voltage set region positioned under the substantially undoped channel and above the screening region, the threshold voltage set region extending to the source and drain.
2. The field effect transistor structure of claim 1, wherein the screening region is positioned at a depth below the gate dielectric of between about Lg/5 and about Lg/1.
3. The field effect transistor structure of claim 1, wherein the channel is formed as a blanket epitaxial layer.
4. The field effect transistor structure of claim 1, wherein the punch through suppression region has a dopant concentration different from the screening region.
5. The field effect transistor structure of claim 1, wherein each of the screening region and the punch through suppression region establishes a notch in the profile of the first conductivity type dopant.
6. The field effect transistor structure of claim 1, wherein the third concentration is larger than the fourth concentration and the fifth concentration, the fourth concentration is larger than the first concentration.
7. The field effect transistor structure of claim 1, wherein the depletion region does not go through the screening region, regardless of a voltage of the well when a voltage of the gate equals to the threshold voltage.
8. The field effect transistor structure of claim 1, wherein there is not a local minimum between the threshold voltage set region and the screening region in the profile of the first conductivity type dopant.
3958266 May 18, 1976 Athanas
4000504 December 28, 1976 Berger
4021835 May 3, 1977 Etoh
4242691 December 30, 1980 Kotani
4276095 June 30, 1981 Beilstein, Jr.
4315781 February 16, 1982 Henderson
4506434 March 26, 1985 Ogawa
4518926 May 21, 1985 Swanson
4559091 December 17, 1985 Allen
4578128 March 25, 1986 Mundt
4617066 October 14, 1986 Vasudev
4662061 May 5, 1987 Malhi
4761384 August 2, 1988 Neppl
4780748 October 25, 1988 Cunningham
4819043 April 4, 1989 Yazawa
4885477 December 5, 1989 Bird
4908681 March 13, 1990 Nishida
4945254 July 31, 1990 Robbins
4956311 September 11, 1990 Liou
5034337 July 23, 1991 Mosher
5144378 September 1, 1992 Hikosaka
5156989 October 20, 1992 Williams
5156990 October 20, 1992 Mitchell
5166765 November 24, 1992 Lee
5208473 May 4, 1993 Komori
5242847 September 7, 1993 Ozturk
5294821 March 15, 1994 Iwamatsu
5298435 March 29, 1994 Aronowitz
5298457 March 29, 1994 Einthoven
5298763 March 29, 1994 Shen
5369288 November 29, 1994 Usuki
5373186 December 13, 1994 Schubert
5384476 January 24, 1995 Nishizawa
5426279 June 20, 1995 Dasgupta
5426328 June 20, 1995 Yimaz
5444008 August 22, 1995 Han
5552332 September 3, 1996 Tseng
5559368 September 24, 1996 Hu
5583361 December 10, 1996 Morishita
5594264 January 14, 1997 Shirahata et al.
5608253 March 4, 1997 Liu
5622880 April 22, 1997 Burr
5625568 April 29, 1997 Edwards
5641980 June 24, 1997 Yamaguchi
5663583 September 2, 1997 Matloubian
5675172 October 7, 1997 Miyamoto
5712501 January 27, 1998 Davies
5719422 February 17, 1998 Burr
5726488 March 10, 1998 Watanabe
5731626 March 24, 1998 Eaglesham
5736419 April 7, 1998 Naem
5753555 May 19, 1998 Hada
5754826 May 19, 1998 Gamal
5756365 May 26, 1998 Kakumu
5763921 June 9, 1998 Okumura
5780899 July 14, 1998 Hu
5847419 December 8, 1998 Imai
5861334 January 19, 1999 Rho
5877049 March 2, 1999 Liu
5879998 March 9, 1999 Krivokapic
5885876 March 23, 1999 Dennen
5889315 March 30, 1999 Farrenkopf
5895954 April 20, 1999 Yasumura
5899714 May 4, 1999 Farremkopf
5918129 June 29, 1999 Fulford, Jr.
5923985 July 13, 1999 Aoki
5923987 July 13, 1999 Burr
5946214 August 31, 1999 Heavlin
5985705 November 16, 1999 Seliskar
5989963 November 23, 1999 Luning
6020227 February 1, 2000 Bulucea
6040610 March 21, 2000 Noguchi
6043139 March 28, 2000 Eaglesham
6060345 May 9, 2000 Hause
6060364 May 9, 2000 Maszara
6066533 May 23, 2000 Yu
6072217 June 6, 2000 Burr
6087210 July 11, 2000 Sohn
6087691 July 11, 2000 Hamamoto
6088518 July 11, 2000 Hsu
6091286 July 18, 2000 Blauschild
6096611 August 1, 2000 Wu
6103562 August 15, 2000 Son
6121153 September 19, 2000 Kikkawa
6124156 September 26, 2000 Widmann
6147383 November 14, 2000 Kuroda
6153920 November 28, 2000 Gossmann
6157073 December 5, 2000 Lehongres
6175582 January 16, 2001 Naito
6184112 February 6, 2001 Maszara
6190979 February 20, 2001 Radens
6194259 February 27, 2001 Nayak
6198157 March 6, 2001 Ishida
6218892 April 17, 2001 Soumyanath
6218895 April 17, 2001 De
6221724 April 24, 2001 Yu
6229188 May 8, 2001 Aoki
6232164 May 15, 2001 Tsai
6235597 May 22, 2001 Miles
6245618 June 12, 2001 An
6268640 July 31, 2001 Park
6271070 August 7, 2001 Kotani
6271551 August 7, 2001 Schmitz
6288429 September 11, 2001 Iwata
6297132 October 2, 2001 Zhang
6300177 October 9, 2001 Sundaresan
6313489 November 6, 2001 Letavic
6319799 November 20, 2001 Ouyang
6320222 November 20, 2001 Forbes
6323525 November 27, 2001 Noguchi
6326666 December 4, 2001 Bernstein
6335233 January 1, 2002 Cho
6358806 March 19, 2002 Puchner
6380019 April 30, 2002 Yu
6391752 May 21, 2002 Colinge
6426260 July 30, 2002 Hshieh
6426279 July 30, 2002 Huster
6432754 August 13, 2002 Assaderaghi
6444550 September 3, 2002 Hao
6444551 September 3, 2002 Ku
6449749 September 10, 2002 Stine
6461920 October 8, 2002 Shirahata
6461928 October 8, 2002 Rodder
6472278 October 29, 2002 Marshall
6482714 November 19, 2002 Hieda
6489224 December 3, 2002 Burr
6492232 December 10, 2002 Tang
6500739 December 31, 2002 Wang
6501131 December 31, 2002 Divakaruni
6503801 January 7, 2003 Rouse
6503805 January 7, 2003 Wang
6506640 January 14, 2003 Ishida
6518623 February 11, 2003 Oda
6521470 February 18, 2003 Lin
6524903 February 25, 2003 Ootsuka
6534373 March 18, 2003 Yu
6541328 April 1, 2003 Whang
6541829 April 1, 2003 Nishinohara
6548842 April 15, 2003 Bulucea
6551885 April 22, 2003 Yu
6552377 April 22, 2003 Yu
6573129 June 3, 2003 Hoke
6576535 June 10, 2003 Drobny
6600200 July 29, 2003 Lustig
6620671 September 16, 2003 Wang
6624488 September 23, 2003 Kim
6627473 September 30, 2003 Oikawa
6630710 October 7, 2003 Augusto
6660605 December 9, 2003 Liu
6662350 December 9, 2003 Fried
6667200 December 23, 2003 Sohn
6670260 December 30, 2003 Yu
6693333 February 17, 2004 Yu
6730568 May 4, 2004 Sohn
6737724 May 18, 2004 Hieda
6743291 June 1, 2004 Ang
6743684 June 1, 2004 Liu
6751519 June 15, 2004 Satya
6753230 June 22, 2004 Sohn
6760900 July 6, 2004 Rategh
6770944 August 3, 2004 Nishinohara
6787424 September 7, 2004 Yu
6797553 September 28, 2004 Adkisson
6797602 September 28, 2004 Kluth
6797994 September 28, 2004 Hoke
6808004 October 26, 2004 Kamm
6808994 October 26, 2004 Wang
6813750 November 2, 2004 Usami
6821825 November 23, 2004 Todd
6821852 November 23, 2004 Rhodes
6822297 November 23, 2004 Nandakumar
6831292 December 14, 2004 Currie
6835639 December 28, 2004 Rotondaro
6852602 February 8, 2005 Kanzawa
6852603 February 8, 2005 Chakravarthi
6881641 April 19, 2005 Wieczorek
6881987 April 19, 2005 Sohn
6891439 May 10, 2005 Jachne
6893947 May 17, 2005 Martinez
6900519 May 31, 2005 Cantell
6901564 May 31, 2005 Stine
6916698 July 12, 2005 Mocuta
6917237 July 12, 2005 Tschanz
6927463 August 9, 2005 Iwata
6928128 August 9, 2005 Sidiropoulos
6930007 August 16, 2005 Bu
6930360 August 16, 2005 Yamauchi
6957163 October 18, 2005 Ando
6963090 November 8, 2005 Passlack
6995397 February 7, 2006 Yamashita
7002214 February 21, 2006 Boyd
7008836 March 7, 2006 Algotsson
7015546 March 21, 2006 Herr
7015741 March 21, 2006 Tschanz
7022559 April 4, 2006 Barnak
7036098 April 25, 2006 Eleyan
7038258 May 2, 2006 Liu
7039881 May 2, 2006 Regan
7045456 May 16, 2006 Murto
7057216 June 6, 2006 Ouyang
7061058 June 13, 2006 Chakravarthi
7064039 June 20, 2006 Liu
7064399 June 20, 2006 Babcock
7071103 July 4, 2006 Chan
7078325 July 18, 2006 Curello
7078776 July 18, 2006 Nishinohara
7089513 August 8, 2006 Bard
7089515 August 8, 2006 Hanafi
7091093 August 15, 2006 Noda
7105399 September 12, 2006 Dakshina-Murthy
7109099 September 19, 2006 Tan
7112856 September 26, 2006 Cho et al.
7119381 October 10, 2006 Passlack
7122411 October 17, 2006 Mouli
7127687 October 24, 2006 Signore
7132323 November 7, 2006 Haensch
7169675 January 30, 2007 Tan
7170120 January 30, 2007 Datta
7176137 February 13, 2007 Perug
7186598 March 6, 2007 Yamauchi
7189627 March 13, 2007 Wu
7199430 April 3, 2007 Babcock
7202517 April 10, 2007 Dixit
7208354 April 24, 2007 Bauer
7211871 May 1, 2007 Cho
7221021 May 22, 2007 Wu
7223646 May 29, 2007 Miyashita
7226833 June 5, 2007 White
7226843 June 5, 2007 Weber
7230680 June 12, 2007 Fujisawa
7235822 June 26, 2007 Li
7256639 August 14, 2007 Koniaris
7259428 August 21, 2007 Inaba
7260562 August 21, 2007 Czajkowski
7294877 November 13, 2007 Rueckes
7297994 November 20, 2007 Wieczorek
7301208 November 27, 2007 Handa
7304350 December 4, 2007 Misaki
7307471 December 11, 2007 Gammie
7312500 December 25, 2007 Miyashita
7323754 January 29, 2008 Ema
7332439 February 19, 2008 Lindert
7348629 March 25, 2008 Chu
7354833 April 8, 2008 Liaw
7380225 May 27, 2008 Joshi
7398497 July 8, 2008 Sato
7402207 July 22, 2008 Besser
7402872 July 22, 2008 Murthy
7416605 August 26, 2008 Zollner
7427788 September 23, 2008 Li
7442971 October 28, 2008 Wirbeleit
7449733 November 11, 2008 Inaba
7462908 December 9, 2008 Bol
7469164 December 23, 2008 Du-Nour
7470593 December 30, 2008 Rouh
7485536 February 3, 2009 Jin
7487474 February 3, 2009 Ciplickas
7491988 February 17, 2009 Tolchinsky
7494861 February 24, 2009 Chu
7496862 February 24, 2009 Chang
7496867 February 24, 2009 Turner
7498637 March 3, 2009 Yamaoka
7501324 March 10, 2009 Babcock
7503020 March 10, 2009 Allen
7507999 March 24, 2009 Kusumoto
7514766 April 7, 2009 Yoshida
7521323 April 21, 2009 Surdeanu
7531393 May 12, 2009 Doyle
7531836 May 12, 2009 Liu
7538364 May 26, 2009 Twynam
7538412 May 26, 2009 Schulze
7562233 July 14, 2009 Sheng
7564105 July 21, 2009 Chi
7566600 July 28, 2009 Mouli
7569456 August 4, 2009 Ko
7586322 September 8, 2009 Xu
7592241 September 22, 2009 Takao
7595243 September 29, 2009 Bulucea
7598142 October 6, 2009 Ranade
7605041 October 20, 2009 Ema
7605060 October 20, 2009 Meunier-Beillard
7605429 October 20, 2009 Bertsein
7608496 October 27, 2009 Chu
7615802 November 10, 2009 Elpelt
7622341 November 24, 2009 Chudzik
7638380 December 29, 2009 Pearce
7642140 January 5, 2010 Bae
7644377 January 5, 2010 Saxe
7645665 January 12, 2010 Kubo
7651920 January 26, 2010 Siprak
7655523 February 2, 2010 Babcock
7673273 March 2, 2010 Madurawe
7675126 March 9, 2010 Cho
7675317 March 9, 2010 Perisetty
7678638 March 16, 2010 Chu
7681628 March 23, 2010 Joshi
7682887 March 23, 2010 Dokumaci
7683442 March 23, 2010 Burr
7696000 April 13, 2010 Liu
7704822 April 27, 2010 Jeong
7704844 April 27, 2010 Zhu
7709828 May 4, 2010 Braithwaite
7723750 May 25, 2010 Zhu
7737472 June 15, 2010 Kondo
7741138 June 22, 2010 Cho
7741200 June 22, 2010 Cho
7745270 June 29, 2010 Shah
7750374 July 6, 2010 Capasso
7750381 July 6, 2010 Hokazono
7750405 July 6, 2010 Nowak
7750682 July 6, 2010 Bernstein
7755144 July 13, 2010 Li
7755146 July 13, 2010 Helm
7759206 July 20, 2010 Luo
7759714 July 20, 2010 Itoh
7761820 July 20, 2010 Berger
7795677 September 14, 2010 Bangsaruntip
7808045 October 5, 2010 Kawahara
7808410 October 5, 2010 Kim
7811873 October 12, 2010 Mochizuki
7811881 October 12, 2010 Cheng
7818702 October 19, 2010 Mandelman
7821066 October 26, 2010 Lebby
7829402 November 9, 2010 Matocha
7831873 November 9, 2010 Trimberger
7846822 December 7, 2010 Seebauer
7855118 December 21, 2010 Hoentschel
7859013 December 28, 2010 Chen
7863163 January 4, 2011 Bauer
7867835 January 11, 2011 Lee
7883977 February 8, 2011 Babcock
7888205 February 15, 2011 Herner
7888747 February 15, 2011 Hokazono
7895546 February 22, 2011 Lahner
7897495 March 1, 2011 Ye
7906413 March 15, 2011 Cardone
7906813 March 15, 2011 Kato
7910419 March 22, 2011 Fenouillet-Beranger
7919791 April 5, 2011 Flynn
7926018 April 12, 2011 Moroz
7935984 May 3, 2011 Nakano
7941776 May 10, 2011 Majumder
7945800 May 17, 2011 Gomm
7948008 May 24, 2011 Liu
7952147 May 31, 2011 Ueno
7960232 June 14, 2011 King
7960238 June 14, 2011 Kohli
7968400 June 28, 2011 Cai
7968411 June 28, 2011 Williford
7968440 June 28, 2011 Seebauer
7968459 June 28, 2011 Bedell
7989900 August 2, 2011 Haensch
7994573 August 9, 2011 Pan
8004024 August 23, 2011 Furukawa
8012827 September 6, 2011 Yu
8029620 October 4, 2011 Kim
8039332 October 18, 2011 Bernard
8046598 October 25, 2011 Lee
8048791 November 1, 2011 Hargrove
8048810 November 1, 2011 Tsai
8051340 November 1, 2011 Cranford, Jr.
8053340 November 8, 2011 Colombeau
8063466 November 22, 2011 Kurita
8067279 November 29, 2011 Sadra
8067280 November 29, 2011 Wang
8067302 November 29, 2011 Li
8076719 December 13, 2011 Zeng
8097529 January 17, 2012 Krull
8103983 January 24, 2012 Agarwal
8105891 January 31, 2012 Yeh
8106424 January 31, 2012 Schruefer
8106481 January 31, 2012 Rao
8110487 February 7, 2012 Griebenow
8114761 February 14, 2012 Mandrekar
8119482 February 21, 2012 Bhalla
8120069 February 21, 2012 Hynecek
8129246 March 6, 2012 Babcock
8129797 March 6, 2012 Chen
8134159 March 13, 2012 Hokazono
8143120 March 27, 2012 Kerr
8143124 March 27, 2012 Challa
8143678 March 27, 2012 Kim
8148774 April 3, 2012 Mori
8163619 April 24, 2012 Yang
8169002 May 1, 2012 Chang
8170857 May 1, 2012 Joshi
8173499 May 8, 2012 Chung
8173502 May 8, 2012 Yan
8176461 May 8, 2012 Trimberger
8178430 May 15, 2012 Kim
8179530 May 15, 2012 Levy
8183096 May 22, 2012 Wirbeleit
8183107 May 22, 2012 Mathur
8185865 May 22, 2012 Gupta
8187959 May 29, 2012 Pawlak
8188542 May 29, 2012 Yoo
8196545 June 12, 2012 Kurosawa
8201122 June 12, 2012 Dewey, III
8214190 July 3, 2012 Joshi
8217423 July 10, 2012 Liu
8225255 July 17, 2012 Ouyang
8227307 July 24, 2012 Chen
8236661 August 7, 2012 Dennard
8239803 August 7, 2012 Kobayashi
8247300 August 21, 2012 Babcock
8255843 August 28, 2012 Chen
8258026 September 4, 2012 Bulucea
8266567 September 11, 2012 El Yahyaoui
8273617 September 25, 2012 Thompson
8286180 October 9, 2012 Foo
8288798 October 16, 2012 Passlack
8299562 October 30, 2012 Li
8324059 December 4, 2012 Guo
8421162 April 16, 2013 Shifren
8541824 September 24, 2013 Thompson
8604527 December 10, 2013 Thompson
8604530 December 10, 2013 Thompson
8645878 February 4, 2014 Clark
8735987 May 27, 2014 Hoffmann
8975128 March 10, 2015 Thompson
20010014495 August 16, 2001 Yu
20020033511 March 21, 2002 Babcock et al.
20020042184 April 11, 2002 Nandakumar
20020043665 April 18, 2002 Ootsuka et al.
20030006415 January 9, 2003 Yokogawa
20030038668 February 27, 2003 Zhang
20030047763 March 13, 2003 Hieda
20030122203 July 3, 2003 Nishinohara
20030173626 September 18, 2003 Burr
20030183856 October 2, 2003 Wieczorek
20030215991 November 20, 2003 Sohn
20030215992 November 20, 2003 Sohn
20040053457 March 18, 2004 Sohn
20040075118 April 22, 2004 Heinemann
20040075143 April 22, 2004 Bae
20040084731 May 6, 2004 Matsuda
20040087090 May 6, 2004 Grudowski
20040126947 July 1, 2004 Sohn
20040175893 September 9, 2004 Vatus
20040180488 September 16, 2004 Lee
20040207011 October 21, 2004 Iwata
20050056877 March 17, 2005 Rueckes
20050093021 May 5, 2005 Ouyang
20050106824 May 19, 2005 Alberto
20050116282 June 2, 2005 Pattanayak
20050250289 November 10, 2005 Babcock
20050276094 December 15, 2005 Yamaoka
20050280075 December 22, 2005 Ema
20060017100 January 26, 2006 Bol
20060022270 February 2, 2006 Boyd
20060049464 March 9, 2006 Rao
20060068555 March 30, 2006 Huilong
20060068586 March 30, 2006 Pain
20060076622 April 13, 2006 Wang
20060091481 May 4, 2006 Li
20060154428 July 13, 2006 Dokumaci
20060157794 July 20, 2006 Doyle
20060163674 July 27, 2006 Cho
20060197158 September 7, 2006 Babcock
20060203581 September 14, 2006 Joshi
20060220114 October 5, 2006 Miyashita
20060223248 October 5, 2006 Venugopal
20060273299 December 7, 2006 Stephenson
20070022951 February 1, 2007 Spartz
20070040222 February 22, 2007 Van Camp
20070117326 May 24, 2007 Tan
20070158790 July 12, 2007 Rao
20070194383 August 23, 2007 Kato
20070212861 September 13, 2007 Chidambarrao
20070238253 October 11, 2007 Tucker
20070242497 October 18, 2007 Joshi
20080067589 March 20, 2008 Ito
20080079493 April 3, 2008 Hamlin
20080108208 May 8, 2008 Arevalo
20080138953 June 12, 2008 Challa
20080169493 July 17, 2008 Lee
20080169516 July 17, 2008 Chung
20080197439 August 21, 2008 Goerlach
20080203522 August 28, 2008 Mandelman et al.
20080227250 September 18, 2008 Ranade
20080237661 October 2, 2008 Ranade
20080258198 October 23, 2008 Bojarczuk
20080272409 November 6, 2008 Sonkusale
20090003105 January 1, 2009 Itoh
20090004806 January 1, 2009 Siprak
20090057746 March 5, 2009 Sugll
20090057762 March 5, 2009 Bangsaruntip
20090108350 April 30, 2009 Cai
20090121298 May 14, 2009 Furukawa
20090134468 May 28, 2009 Tsuchiya
20090194824 August 6, 2009 Wirbeleit
20090224319 September 10, 2009 Kohli
20090302388 December 10, 2009 Cai
20090309140 December 17, 2009 Khamankar
20090311837 December 17, 2009 Kapoor
20090321849 December 31, 2009 Miyamura
20100012988 January 21, 2010 Yang
20100038724 February 18, 2010 Anderson
20100072455 March 25, 2010 Crowder
20100100856 April 22, 2010 Mittal
20100148153 June 17, 2010 Hudait
20100149854 June 17, 2010 Vora
20100187641 July 29, 2010 Zhu
20100207182 August 19, 2010 Paschal
20100270600 October 28, 2010 Inukai
20110059588 March 10, 2011 Kang
20110073961 March 31, 2011 Dennard
20110074498 March 31, 2011 Thompson
20110079860 April 7, 2011 Verhulst
20110079861 April 7, 2011 Shifren
20110095811 April 28, 2011 Chi
20110147828 June 23, 2011 Murthy
20110169082 July 14, 2011 Zhu
20110175170 July 21, 2011 Wang
20110180880 July 28, 2011 Chudzik
20110193164 August 11, 2011 Zhu
20110212590 September 1, 2011 Wu
20110230039 September 22, 2011 Mowry
20110242921 October 6, 2011 Tran
20110248352 October 13, 2011 Shifren
20110294278 December 1, 2011 Eguchi
20110309447 December 22, 2011 Arghavani
20120021594 January 26, 2012 Gurtej
20120034745 February 9, 2012 Colombeau
20120056275 March 8, 2012 Cai
20120065920 March 15, 2012 Nagumo
20120108050 May 3, 2012 Chen
20120132998 May 31, 2012 Kwon
20120138953 June 7, 2012 Cai
20120146155 June 14, 2012 Hoentschel
20120167025 June 28, 2012 Gillespie
20120168864 July 5, 2012 Dennard
20120187491 July 26, 2012 Zhu
20120190177 July 26, 2012 Kim
20120223363 September 6, 2012 Kronholz
20140077312 March 20, 2014 Thompson
101180737 December 2004 CN
200910109443.3 August 2009 CN
101661889 September 2011 CN
201194816 September 2011 CN
0274278 July 1988 EP
0312237 April 1989 EP
0683 515 November 1995 EP
0889502 January 1999 EP
0 951 071 October 1999 EP
1 265 277 December 2002 EP
1 450 394 August 2004 EP
59193066 November 1984 JP
S63305566 December 1988 JP
04-179160 June 1992 JP
4186774 July 1992 JP
H05 183154 July 1993 JP
06-097432 April 1994 JP
06-236967 August 1994 JP
8153873 June 1996 JP
1996172187 July 1996 JP
08-293557 November 1996 JP
8288508 November 1996 JP
09-008296 January 1997 JP
09-121049 May 1997 JP
H09-121049 May 1997 JP
H09-246534 September 1997 JP
10-135348 May 1998 JP
10-189766 July 1998 JP
10-340998 December 1998 JP
11-500873 January 1999 JP
11-340472 December 1999 JP
200-243958 September 2000 JP
2000-243958 September 2000 JP
2000-299462 October 2000 JP
2001 068674 March 2001 JP
2001-102582 April 2001 JP
2002-158293 May 2002 JP
2002-198529 July 2002 JP
2002-237575 August 2002 JP
2003-031803 January 2003 JP
2003-031813 January 2003 JP
2003 086706 March 2003 JP
2004-47933 February 2004 JP
2004-047933 February 2004 JP
2004087671 March 2004 JP
2004-214578 July 2004 JP
2005-522038 July 2005 JP
2005-217391 August 2005 JP
2006-093507 April 2006 JP
2006093507 April 2006 JP
2007-013025 January 2007 JP
2007-259463 October 2007 JP
2009-170472 July 2009 JP
794094 January 2008 KR
522548 August 2008 TW
WO 97/23000 June 1997 WO
WO 2003/083950 October 2003 WO
WO 2004/075295 September 2004 WO
WO 2005/065385 July 2005 WO
WO 2006/113077 October 2006 WO
WO 2007/023979 March 2007 WO
2007/136102 November 2007 WO
WO 2009/053327 April 2009 WO
WO 2009/055173 April 2009 WO
US 7,011,991 B1, 03/2006, Li (withdrawn)
State Intellectual Property Office of the People's Republic of China, The First Office Action, Application No. 201180035830.2; with English language translation, 15 pages, dated May 6, 2014.
Japanese Office Action issued in JP Appl. No. 2013-516663; 7 pages with English translation, dated Apr. 21, 2015.
Banerjee, et al. “Compensating Non-Optical Effects using Electrically-Driven Optical Proximity Correction”, Proc. of SPIE vol. 7275 7275OE, 2009.
Cheng, et al. “Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-Chip Applications”, Electron Devices Meeting (IEDM), Dec. 2009.
Cheng, et al. “Fully Depleted Extremely Thin SOI Technology Fabricated by a Novel Integration Scheme Feturing Implant-Free, Zero-Silicon-Loss, and Faceted Raised Source/Drain”, Symposium on VLSI Technology Digest of Technical Papers, pp. 212-213, 2009.
Drennan, et al. “Implications of Proximity Effects for Analog Design”, Custom Integrated Circuits Conference, pp. 169-176, Sep. 2006.
Hook, et al. “Lateral Ion Implant Straggle and Mask Proximity Effect”, IEEE Transactions on Electron Devices, vol. 50, No. 9, pp. 1946-1951, Sep. 2003.
Hori, et al., “A 0.1 μm CMOS with a Step Channel Profile Formed by Ultra High Vacuum CVD and In-Situ Doped Ions”, Proceedsing of the International Electron Devices Meeting, New York, IEEE, US, pp. 909-911, Dec. 5, 1993.
Matshuashi, et al. “High-Performance Double-Layer Epitaxial-Channel PMOSFET Compatible with a Single Gate CMOSFET”, Symposium on VLSI Technology Digest of Technical Papers, pp. 36-37, 1996.
Shao, et al., “Boron Diffusion in Silicon: The Anomalies and Control by Point Defect Engineering”, Materials Science and Engineering R: Reports, vol. 42, No. 3-4, pp. 65-114, Nov. 1, 2003.
Sheu, et al. “Modeling the Well-Edge Proximity Effect in Highly Scaled MOSFETs”, IEEE Transactions on Electron Devices, vol. 53, No. 11, pp. 2792-2798, Nov. 2006.
Abiko, H et al., “A Channel Engineering Combined with Channel Epitaxy Optimization and TED Suppression for 0.15 μm n-n Gate CMOS Technology”, 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 23-24.
Chau, R et al., “A 50nm Depleted-Substrate CMOS Transistor (DST)”, Electron Device Meeting 2001, IEDM Technical Digest, IEEE International, pp. 29.1.1-29.1.4.
Ducroquet, F et al. “Fully Depleted Silicon-On-Insulator nMOSFETs with Tensile Strained High Carbon Content Sil-yCy Channel”, ECS 210th Meeting, Abstract 1033, 2006.
Ernst, T et al., “Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features”, ECS Trans. 2006, vol. 3, Issue 7, pp. 947-961, 2006.
Hokazono, A et al., “Steep Channel & Halo Profiles Utilizing Boron-Diffusion-Barrier Layers (Si:C) for 32 nm Node and Beyond”, 2008 Symposium on VLSI Technology Digest of Technical Papers, pp. 112-113.
Hokazono, A et al., “Steep Channel Profiles in n/pMOS Controlled by Boron-Doped Si:C Layers for Continual Bulk-CMOS Scaling”, IEDM09-676 Symposium, pp. 29.1.1-29.1.4, 2009.
Holland, OW and Thomas, DK “A Method to Improve Activation of Implanted Dopants in SiC”, Oak Ridge National Laboratory, Oak Ridge, TN, 2001.
Kotaki, H., et al., “Novel Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS”, IEDM 96, pp. 459-462, 1996.
Lavéant, P. “Incorporation, Diffusion and Agglomeration of Carbon in Silicon”, Solid State Phenomena, vols. 82-84, pp. 189-194, 2002.
Noda, K et al., “A 0.1-μm Delta-Doped MOSFET Fabricated with Post-Low-Energy Implanting Selective Epitaxy” IEEE Transactions on Electron Devices, vol. 45, No. 4, pp. 809-814, Apr. 1998.
Ohguro, T et al., “An 0.18-μm CMOS for Mixed Digital and Analog Aplications with Zero-Volt-Vth Epitaxial-Channel MOSFET's”, IEEE Transactions on Electron Devices, vol. 46, No. 7, pp. 1378 -1383, Jul. 1999.
Pinacho, R et al., “Carbon in Silicon: Modeling of Diffusion and Clustering Mechanisms”, Journal of Applied Physics, vol. 92, No. 3, pp. 1582-1588, Aug. 2002.
Komaragiri, R. et al., “Depletion-Free Poly Gate Electrode Architecture for Sub 100 Nanometer CMOS Devices with High-K Gate Dielectrics”, IEEE IEDM Tech Dig., San Francisco CA, 833-836, Dec. 13-15, 2004.
Samsudin, K et al., “Integrating Intrinsic Parameter Fluctuation Description into BSIMSOI to Forecast sub-15nm UTB SOI based 6T SRAM Operation”, Solid-State Electronics (50), pp. 86-93, 2006.
Wong, H et al., “Nanoscale CMOS”, Proceedings of the IEEE, Vo. 87, No. 4, pp. 537-570, Apr. 1999.
PCT Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority for International Application No. PCT/US10/48998; 10 pages, dated Jan. 6, 2011.
PCT Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority for International Application No. PCT/US2010/049000; 9 pages, dated Jan. 12, 2011.
Shao, et al. “Boron diffusion in silicon: the anomalies and control by point defect engineering” Materials Science and Engineering R: Reports, vol. 42, No. 3-4, Nov. 1, 2003 pp. 65-114.
PCT Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority for International Application No. PCT/US2011/041156; dated Sep. 21, 2011; 12 pages.
Yan, et al., “Scaling the Si MOSFET: From Bulk to SOI to Bulk”, IEEE Transactions on Electron Devices, IEEE Service Center, Pisacataway, NJ, US, vol. 39, No. 7, Jul. 1, 1992 pp. 1704-1710.
PCT Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority for International Application No. PCT/US2011/041165; dated Nov. 2, 2011; 6 pages.
USPTO Office Action for U.S. Appl. No. 12/895,695, filed Sep. 30, 2010 in the name of Lucian Shifren, et al. 27 pages, dated May 27, 2011.
USPTO Office Action for U.S. Appl. No. 12/895,695, filed Sep. 30, 2010 in the name of Lucian Shifren, et al. 30 pages, dated Oct. 24, 2011.
Robertson, LS et al., “The Effect of Impurities on Diffusion and Activation of Ion Implanted Boron in Silicon”, Mat. Res. Soc. Symp. vol. 610, 2000.
Scholz, R et al., “Carbon-Induced Undersaturation of Silicon Self-Interstitials”, Appl. Phys. Lett. 72(2), pp. 200-202, Jan. 1998.
Scholz, RF et al., “The Contribution of Vacancies to Carbon Out-Diffusion in Silicon”, Appl. Phys. Lett., vol. 74, No. 3, pp. 392-394, Jan. 1999.
Stolk, PA et al., “Physical Mechanisms of Transient Enhanced Dopant Diffusion in Ion-Implanted Silicon”, J. Appl. Phys. 81(9), pp. 6031-6050, May 1997.
Thompson, S et al., “MOS Scaling: Transistor Challenges for the 21st Century”, Intel Technology Journal Q3' 1998, pp. 1-19.
Wann, C. et al., “Channel Profile Optimization and Device Design for Low-Power High-Performance Dynamic-Threshold MOSFET”, IEDM 96, pp. 113-116, 1996.
Werner, P et al., “Carbon Diffusion in Silicon”, Applied Physics Letters, vol. 73, No. 17, pp. 2465-2467, Oct. 1998.
Japanese Office Action issued in Appl. No. 2013-516663; 5 pages including English Concise Explanation of Office Action, dated Feb. 18, 2016.
Japanese Office Action issued in Appl. No. 2013-516663; 5 pages including English Concise Explanation of Office Action, dated Sep. 6, 2016.
Korean Intellectual Property Office Notice of Preliminary Rejection, Korean Patent Application No. 10-2013-7001668 (with English translation), dated Apr. 18, 2017.
The First Office Action and Search Report; Peoples Republic of China Patent Office; Appl. No. 201510494596.X, dated Aug. 6, 2017.
Japanese Patent Office; Decision on Appeal Office Action; Appl. No. JP 2000-243958; 19 pages including English translation summary, dated Oct. 31, 2017.
Japanese Patent Office; Notification of Reasons for Refusal Office Action; Appl. No. JP 2016-236397; 8 pages including English translation summary, dated Nov. 6, 2017.
Japanese Patent Office Notification of Reasons for Refusal of Patent Application No. 2016-244655 (with machine translation) dated Feb. 20, 2018.
Japanese Patent Office Decision of Refusal for Patent Application No. 2016-236397 (with machine translation) dated Feb. 20, 2018.
Korean Intellectual Property Office Notice of Preliminary Rejection; Korean Pat. Appl. No. 10-2018-7000155 dated Apr. 2, 2018.
Summons to Attend Oral Proceedings; Appl. No. 10821022.0-1211/2483915; Reference P126380EPPC/DNL, Mar. 29, 2018.
Summons to Attend Oral Proceedings; Appl. No. 10821021.2-1211/2483916; Reference P126379EPPC/DNL, Mar. 29, 2018.
Chinese 2nd Office Action re: Chinese appl. No. 201510494596X; ref: 11-00057CNB; 4 pages including English summary, dated Apr. 23, 2018.
Korean Intellectual Property Office Notice of Preliminary Rejection; KR Patent Appl. No. 10-2012-7024293; from BB 083852.0307; transation included, dated Jan. 30, 2018.
Request for Continued Examination and Amendment; U.S. Appl. No. 15/241,337; dated Mar. 22, 2018.
Response to non-final OA; U.S. Appl. No. 15/398,471; dated Mar. 9, 2018.
Yulin Thong et al, “Selective Low-Pressure Chemical Vapor Deposition of Sil-xGex Alloys in a Rapid Thermal Processor Using Dichlorosilane and Germane,” , Appl. Phys. Lett, vol. 57, No. 20, Dec. 1990, p. 2092-2094, Dec. 1990.
PCT Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority for international Application No. PCT/US2010/055762; 8 pages, dated Jan. 5, 2011.
PCT Notice of Transmittal of the International Search Report and the Written Opinion of the International Search Authority, or the Declaration, PCT/US2011/025284, 13 pp, dated Apr. 19, 2011.
PCT Notice of Transmittal of the International Search Report and the Written Opinion of the International Search Authority, or the Declaration, PCT/US2011/025278, 14 pp. dated Jun. 17, 2011.
Ex Parte Quayle Action; U.S. Appl. No. 12/708,497; dated Jun. 28, 2012.
Response to ExParte Quayle Action; U.S. Appl. No. 12/708,497; dated Jul. 17, 2012.
Notice of Allowance and Fees Due; U.S. Appl. No. 14/082,931; dated Aug. 8, 2012.
Ex Parte Quayle Action; U.S. Appl. No. 13/553,593; dated Jun. 27, 2013.
Response to ExParte Quayle Action; U.S. Appl. No. 13/553,593; dated Jul. 8, 2013.
Ex Parte Quayle Action; U.S. Appl. No. 13/616,053; dated Jul. 10, 2013.
Response to Ex Parte Quayle Action; U.S. Appl. No. 13/616,053; dated Jul. 19, 2013.
Ex Parte Quayle Action; U.S. Appl. No. 13/616,809; dated Jul. 22, 2013.
Response to Ex Parte Quayle Action; U.S. Appl. No. 13/616,859; dated Jul. 23, 2013.
Notice of Allowance and Fees Due; U.S. Appl. No. 13/553,593; dated Jul. 29, 2013.
Notice of Allowance and Fees Due; U.S. Appl. No. 13/616,859; dated Aug. 5, 2013.
Notice of Allowance and Fees Due; U.S. Appl. No. 13/616,053; dated Aug. 6, 2013.
S. E. Thompson, U.S. Appl. No. 14/082,931, Election Restriction Requirement dated Jan. 22, 2014.
S. E. Thompson, U.S. Appl. No. 14/082,931, Response to Election Restriction Requirement dated Mar. 20, 2014.
China First Office Action; App. No. 201080054379.4; dated May 26, 2014.
China First Office Action; App. No. 201080054378.X; dated Jun. 4, 2014.
China First Office Acion; App. No. 201180019743.8; dated Jun. 4, 2014.
Ex Parte Quayle Avtion; U.S. Appl. No. 14/082,931; dated Aug. 18, 2014.
China First Office Action; App. No. 201080061745.9; dated Sep. 3, 2014.
Response to Ex Parte Quayle Action; U.S. Appl. No. 14/082,931; dated Oc. 17, 2014.
Japan Patent Office Official Action (with Translation) in Japan Patent Application No. 2012-554028 dated Oct. 21, 2014, reported to Applicants Dec. 1, 2014, 8 pages, dated Oct. 21, 2014.
Japan Patent Office Official Action (with Translation) in Japan Patent Application No. 2012-532104 dated Nov. 4, 201, reported to Applicants Dec. 19, 2014, 13 pages, dated Nov. 4, 2014.
Japan Patent Office Official Action (with translation) in Japan Patent Application No. 2012-532105 dated Nov. 4, 2014, reported to Applicants Dec. 19, 2014, 11 pages, dated Nov. 4, 2014.
Japan Patent Office Official Action (with Translation) in Japan Patent Applicantion No. 2012-539939 dated Nov. 4, 2014, reported to Applicants Dec. 19, 2014, 13 pages, dated Nov. 4, 2014.
Notice of Allowance and Fees Due; U.S. Appl. No. 14/082,931; dated Nov. 5, 2014.
Japan Patent Office Official Action (with Translation) in Japan Patent Application No. 2012-554029 dated Nov. 11, 2014, reported to Applicants Dec. 1, 2014, 9 pages, dated Nov. 11, 2014.
First Office Action from Chinese Patent Office for Chinese Patent Application No. 201180019710.3, 9 pages dated Nov. 27, 2014.
Second Office Action from Chinese Patent Office for Chinese Patent Application No. 201080054378.X, dated Dec. 26, 2014.
Second Office Action; App. No. 201080054379.4; dated Feb. 9, 2015.
Second Office Action; App. No, 201080061745.9; dated Apr. 8, 2015.
Second Japanese Office Action; 078023.0410; 2012-554029; 5 pages including translation, dated Apr. 21, 2015.
Japanese Office Action issued in Appl. No. 2012-532104, 6 pages, dated Apr. 21, 2015.
European Patent Offices; Supplementary European Search Report; Jun. 1, 2015; App. No. 10821022.0-1555 / 2483915 PCT/US2010049000; 8 pages, dated Jun. 1, 2015.
European Patent Office: Supplementary European Search Report; Jun. 1, 2015; App. No. 10821021.2-1555 / 2483916 PCT/US2010048998; 7 pages, dated Jun. 1, 2015.
The State Intellectual Property Office of the People's Republic of China; Second Office Action; Application No. 201180019710.3; 8 pages including translation dated Jul. 10, 2015.
Third Office Action; Iss. No. 2015091101204940; dated Sep. 16, 2015.
USPTO Non-Final Rejection; U.S. Appl. No. 14/642,156; dated Oct. 19, 2015.
Taiwan Patent Office; Office Action for Applicant No. 099132985; 11 pages including translation, dated Nov. 4, 2015.
Decision to Refuse, Japanese Patent Office re: Patent Application No. 2012-539939; 2 pages including translation, dated Nov. 4, 2015.
S. E. Thompson, U.S. Appl. No.14/642,156, Response to Non-final Office Action dated Jan. 8, 2016.
USPTO Notice of Allowance and Fees Due; U.S. Appl. No. 14/642,156; dated Mar. 9, 2016.
Request for Controlled Examination, U.S. Appl. No. 14/642,156; dated Apr. 26, 2016.
USPTO Non-Final Rejection; U.S. Appl. No. 14/642,156; dated May 12, 2016.
S. E. Thompson. U.S. Appl. No. 14/642,156, Response to Non-Final Office Action, dated Jun. 15, 2016.
USPTO Notice of Allowance and Fees Due; U.S. Appl. No. 14/642,156; dated Jul. 22, 2016.
Office Action from Japanese Patent Office for Application No. 2015144418; 8 pages including English translation, dated Aug. 2, 2016.
Korean Intellectual Propert Office Notice of Preliminary Rejection for Application No. 10-2012-7024299; 18 pages; including English translation, dated Sep. 6, 2016.
Korean Intellectual Property Office Notice of Preliminary Rejection for Application No. 10-2012-7011021; 12 pages; including English translation, dated Oct. 4, 2016.
Korean Intellectual Property Office Notice of Preliminary Rejection for Application No. 10-2012-7011008; 5 pages; including English translation only, dated Oct. 4, 2016.
Korean Intellectual Property Office Notice of Preliminary Rejection for Application No. 10-2012-7015629; 10 pages; including English translation, dated Oct. 4, 2016.
S. E. Thompson, U.S. Appl. No. 15/241,337, Notice of Allowance dated Oct. 13, 2016.
Japanese Office Action; application No. 2015-162854; 6 pages including translation, dated Oct. 18, 2016.
USPTO Notice of Allowance and Fees Due; U.S. Appl. No. 14/642,156, dated Dec. 7, 2016.
S. E. Thompson, U.S. Appl. No. 14/642,156, RCE, dated Dec. 14, 2016.
European Office Action; App. No. 10 821 021.2-1555; 6 pages, dated Jan. 10, 2017.
European Office Action; App. No. 10 821 022.0-1555; 5 pages, dated Jan. 10, 2017.
S. E. Thompson, U.S. Appl. No. 14/642156, Notice of Allowance, dated Jan. 17, 2017.
USPTO Office Action; U.S. Appl. No. 90/000,176, dated Feb. 1, 2017.
S. E. Thompson, U.S. Appl. No. 15/241,337, Request for continued Examination, dated Feb, 24, 2017.
S. E. Thompson, U.S. Appl. No. 14/642,156, RCE, dated Feb. 27, 2017.
S. E. Thompson, U.S. Appl. No. 14/642,156, Notice of Allowance, dated Feb. 28, 2017.
Notice of Allowance, U.S. Appl. No. 15/241,337, dated Mar. 10, 2017.
Response to Ex-Parte Reexamination; U.S. Appl. No. 96/000,176, dated Mar. 22, 2017.
Supplemental Response to Ex-Parte Examination; U.S. Appl. No. 96/000,176, dated Apr. 13, 2017.
Non-Final Rejection Dismissing Allowance; U.S. Appl. No. 14/642,156, dated Apr. 13, 2017.
Korean Intellectual Property Office Notice of Final Rejection for Patent Application No. 10-2012-7024299, dated Apr. 28, 2017.
Request for Continued Examination; U.S. Appl. No. 15/241,337, dated May 9, 2017.
Non-Final Office Action in a Reexam; U.S. Appl. No. 96/000,176, dated May 22, 2017.
Response to non-final Office Action; U.S. Appl. No. 14/642,156, filed Jul. 13, 2017.
Notice of Preliminary Rejection; Korean Intellectual Property Office; RE: Korean Pat. Appl. No. 10-2012-7024293, dated Jul. 14, 2017.
Response to Non-Final Office Action in a Reexam; U.S. Appl. No, 96/000,176, dated Jul. 19, 2017.
Non-Final Office Action for U.S. Appl. No. 15/241,337, dated Aug. 3, 2017.
Korean Intellectual Property Office Second Notice of Final Rejection for Patent Application No. 10-2012-7024299 (with translation) dated Aug. 31, 2017.
Japanese Office Action re; Appl. No. 2016-244655; 8 pages including English translation, dated Nov. 6, 2017.
Korean Intellectual Property Office Notice of Preliminary Rejection for Patent Application No. 10-2017.7022958 (with translation) dated Nov. 15, 2017.
USPTO; Final Office Action; Reexam U.S. Appl. No. 96/000,176; 14 pages, dated Nov. 22, 2017.
Notice of Allowance and Fees Due; U.S. Appl. No. 12/708,497; dated Aug. 8, 2012.
China First Office Action; App. No. 201180019743.8; dated Jun. 4, 2014.
Response to Ex Parte Quayle Action; U.S Appl. No. 14/082,931; dated Oct. 17, 2014.
Second Japanese Office Action Decision of Refusal; 2012-554029; 9 pages including translation, dated Jul. 14, 2015.
Third Japanese Office Action Notification of Reasons for Refusal; Appl No. 2012-554029; 6 pages including translation, dated Jan. 26, 2016.
Non-Final Office Action re: U.S. Appl. No. 15/398,471; dated Jan. 2, 2018.
Final Office Action re: Appl. U.S. Appl. No. 15/241,337; dated Dec. 29, 2017.
USPTO; Final Office Action; U.S. Appl. No. 15/398,471; dated Jun. 28, 2018.
USPTO; Non-Final Office Action: U.S. Appl. No. 15/241,337; dated Jun. 27, 2018.
The State Intellectual Property Office of the People's Republic of China; First Office Action; Appl. No. 2016102523402; dated Jun. 22, 2018.
Response to Non Final Office Action re: U.S. Appl. No. 15/241,337; dated Jul. 23, 2018.
Request for Continued Examination and Amendment re: U.S. Appl. No, 15/398,471; dated Aug. 27, 2018.
China National Intellectual Property Administration; The Second Office Action re: 2016102523402; dated Mar. 5, 2019.
Korean Intellectual Property Trail and Appeal Board; Decision re; 10-2012-7024299; translation attached, dated Apr. 2, 2019.
Patent number: 10325986
Patent Publication Number: 20170040419
Inventors: Lucian Shifren (San Jose, CA), Pushkar Ranade (Los Gatos, CA), Paul E. Gregory (Palo Alto, CA), Sachin R. Sonkusale (Los Gatos, CA), Weimin Zhang (San Jose, CA), Scott E. Thompson (Gainesville, FL)
Application Number: 15/298,913
Current U.S. Class: Characterized By Sectional Shape, E.g., T-shape, Inverted T, Spacer (epo) (257/E21.205)
International Classification: H01L 29/10 (20060101); H01L 21/8234 (20060101); H01L 27/088 (20060101); H01L 29/66 (20060101); H01L 29/78 (20060101); H01L 27/092 (20060101); H01L 29/08 (20060101); H01L 29/36 (20060101);