Source: http://www.google.com/patents/US8154923?dq=7,177,838
Timestamp: 2017-04-25 16:09:18
Document Index: 422787929

Matched Legal Cases: ['Application No. 200580049799', 'Application No. 10000203', 'Application No. 05', 'Application No. 2008', 'Application No. 2008', 'Application No. 2007', 'Application No. 094116919', 'Application No. 094116919']

Patent US8154923 - Non-volatile memory and method with power-saving read and program-verify ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative...http://www.google.com/patents/US8154923?utm_source=gb-gplus-sharePatent US8154923 - Non-volatile memory and method with power-saving read and program-verify operationsAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8154923 B2Publication typeGrantApplication numberUS 13/114,481Publication dateApr 10, 2012Filing dateMay 24, 2011Priority dateMar 16, 2005Fee statusPaidAlso published asCN101180682A, CN101180682B, DE602005019789D1, EP1859448A1, EP1859448B1, EP2169684A1, US7251160, US7570513, US7957185, US8542529, US20060209592, US20070014156, US20070014161, US20110222345, US20120243332, WO2006101500A1Publication number114481, 13114481, US 8154923 B2, US 8154923B2, US-B2-8154923, US8154923 B2, US8154923B2InventorsYan Li, Seungpil Lee, Siu Lung ChanOriginal AssigneeSandisk Technologies Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (74), Non-Patent Citations (16), Referenced by (5), Classifications (11), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetNon-volatile memory and method with power-saving read and program-verify operations
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Method With Power-Saving Read and Program-Verify OperationsJP10233096A Title not availableJP2000276887A Title not availableJP2001067884A Title not availableJPH10233096A Title not availableWO2004029975A1Sep 18, 2003Apr 8, 2004Sandisk CorporationNon-volatile memory and method with reduced bit line crosstalk errors* Cited by examinerNon-Patent CitationsReference1China State Intellectual Property Office, "Office Action," corresponding Chinese Patent Application No. 200580049799.2, mailed on Nov. 6, 2009, 5 pages (including translation.).2Communication Relating to the Results of the Partial International Search for SanDisk Corporation, International Application No. PCT/US2005/016516 mailed Dec. 28, 2005, 2 pages.3Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.4EPO, "Search Report," corresponding European Patent Application No. 10000203.9, mailed on Mar. 2, 2010, 5 pages.5EPO/International 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(including translation.).8JPO, "Notification of Reasons for Refusal," corresponding Japanese Patent Application No. 2008-5-1855, mailed on Nov. 24, 2010, 4 pages (including translation.).9KRO, "Notice of Preliminary Rejection," corresponding Korean Patent Application No. 2007-7022221, mailed on Jul. 29, 2011, 4 pages. (including translation.).10Taiwanese Patent Office, "Office Action," corresponding Taiwanese Patent Application No. 094116919 on Dec. 25, 2007, 4 pages (translation included.).11Taiwanese Patent Office, "Preliminary Notice of Rejection of the IPO," corresponding in related Taiwan Patent Application No. 094116919, mailed on Dec. 27, 2006, 2 pages.12USPTO, "Notice of Allowance and Fee(s) Due" mailed in related U.S. Appl. No. 11/534,307 on Mar. 30, 2009, 15 pages.13USPTO, "Office Action" mailed in related U.S. Appl. No. 11/534,307 on Nov. 14, 2008, 10 pages.14USPTO, "Office Action" mailed in related U.S. Appl. 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No. 11/083,514 mailed Sep. 29, 1996, 12 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS9208833Apr 23, 2013Dec 8, 2015Micron TechnologySequential memory operation without deactivating access line signalsUS9502124Jul 2, 2014Nov 22, 2016Samsung Electronics Co., Ltd.Nonvolatile memory device and method controlling word line setup time based on difference in setup voltage levelsUS9564234Feb 21, 2014Feb 7, 2017Samsung Electronics Co., Ltd.Sequentially accessing memory cells in a memory deviceUS9595345 *Aug 7, 2014Mar 14, 2017Sandisk Technologies LlcAdaptive selective bit line pre-charge for current savings and fast programmingUS20160042802 *Aug 7, 2014Feb 11, 2016Sandisk Technologies IncAdaptive Selective Bit Line Pre-Charge For Current Savings And Fast Programming* Cited by examinerClassifications U.S. Classification365/185.03, 365/185.25, 365/185.22, 365/185.17, 365/185.33, 365/185.12International ClassificationG11C11/34Cooperative ClassificationG11C2211/5621, G11C16/26, G11C11/5642European ClassificationG11C11/56D4Legal EventsDateCodeEventDescriptionMar 16, 2012ASAssignmentOwner name: SANDISK TECHNOLOGIES INC., TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:027876/0666Effective date: 20120314Jun 26, 2012CCCertificate of correctionSep 23, 2015FPAYFee paymentYear of fee payment: 4May 25, 2016ASAssignmentOwner name: SANDISK TECHNOLOGIES LLC, TEXASFree format text: CHANGE OF NAME;ASSIGNOR:SANDISK TECHNOLOGIES INC;REEL/FRAME:038807/0850Effective date: 20160516RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services