Source: http://www.google.com/patents/US6960932?dq=4,923,986
Timestamp: 2013-12-09 14:49:55
Document Index: 466118698

Matched Legal Cases: ['art. 2', 'Application No. 2002', 'art 10', 'art 10', 'art 14', 'art 10', 'art 10', 'art 14', 'art 10']

Patent US6960932 - Apparatus and method to correct a reference voltage - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsAn apparatus and method thereof to correct a reference voltage, Vref, include a first digital device and a second digital device to input/output digital data via a bus, an adjustable resistor providing a main supply voltage VDD, a fixed resistor, wherein the adjustable resistor and the fixed resistor...http://www.google.com/patents/US6960932?utm_source=gb-gplus-sharePatent US6960932 - Apparatus and method to correct a reference voltagePublication numberUS6960932 B2Publication typeGrantApplication numberUS 10/690,502Publication dateNov 1, 2005Filing dateOct 23, 2003Priority dateNov 6, 2002Fee statusPaidAlso published asUS20040108870Publication number10690502, 690502, US 6960932 B2, US 6960932B2, US-B2-6960932, US6960932 B2, US6960932B2InventorsWan-Seok KoOriginal AssigneeSamsung Electronics Co., Ltd.Patent Citations (11), Classifications (8), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetApparatus and method to correct a reference voltageUS 6960932 B2Abstract An apparatus and method thereof to correct a reference voltage, Vref, include a first digital device and a second digital device to input/output digital data via a bus, an adjustable resistor providing a main supply voltage VDD, a fixed resistor, wherein the adjustable resistor and the fixed resistor generate a Vref correction by dividing the main supply voltage VDD. A Vref setup selecting part of the apparatus and method selects the Vref correction and a Vref controller changes a resistance value of the adjustable resistor according to a selection of the Vref correction through the Vref setup selecting part, determines an optimum resistance value of the adjustable resistor, and outputs an optimum Vref correction.
1. An apparatus to correct a reference voltage (Vref) of a digital device to input/output digital data, comprising:
a Vref setup selecting part selecting a correction of the Vref; a Vref adjusting circuit adjusting the Vref of the digital device; and a Vref control storing part storing a Vref control program to change setup of the Vref adjusting circuit to vary the Vref output from the Vref adjusting circuit to be varied, detecting a transmission state of the digital data of the digital device, determining an optimum setup of the Vref adjusting circuit to allow error bits of the digital data to be minimized, and setting up the Vref adjusting circuit according to selection of the Vref correction through the Vref setup selecting part. 2. The apparatus for correcting the reference voltage according to claim 1, wherein the Vref control program comprises a BIOS program.
3. The apparatus to correct the reference voltage according to claim 1, wherein the Vref adjusting circuit comprises:
an adjustable resistor, and a fixed resistor to generate the Vref correction by dividing a main supply voltage of the digital device, wherein the Vref control program changes a resistance value of the adjustable resistor according to the selection of the Vref correction through the Vref setup selecting part, detects the transmission state of the digital data of the digital devices, determines an optimum resistance value of the adjustable resistor to allow the error bits of the digital data to be minimized, and sets up the resistance value of the adjustable resistor as the optimum resistance value. 4. The apparatus for correcting the reference voltage according to claim 2, wherein the Vref adjusting circuit comprises:
an adjustable resistor, and a fixed resistor to generate the Vref correction by dividing a main supply voltage of the digital device, wherein the Vref control program changes a resistance value of the adjustable resistor according to the selection of the Vref correction through the Vref setup selecting part, detects the transmission state of the digital data of the digital devices, determines an optimum resistance value of the adjustable resistor to allow the error bits of the digital data to be minimized, and sets up the resistance value of the adjustable resistor as the optimum resistance value. 5. The apparatus for correcting the reference voltage according to claim 1, further comprising:
a Vref optimum setup storing part to store data of optimum setup condition of the Vref adjusting circuit. 6. An apparatus to correct a reference voltage, Vref, comprising:
a first digital device and a second digital device inputting/outputting digital data via a bus; an adjustable resistor providing a main supply voltage VDD; a fixed resistor, wherein the adjustable resistor and the fixed resistor generate a Vref correction by dividing the main supply voltage VDD; a Vref setup selecting part selecting the Vref correction; and a Vref controller changing a resistance value of the adjustable resistor according to a selection of the Vref correction through the Vref setup selecting part, determining an optimum resistance value of the adjustable resistor, and outputting an optimum Vref correction. 7. The apparatus to correct the reference voltage according to claim 6, wherein the Vref controller analyzes signals input/output between the first and second digital devices by transmitting through the bus a digital signal corresponding to the change of the resistance value of the adjustable resistor.
8. The apparatus to correct the reference voltage according to claim 7, wherein the Vref controller confirms a transmission state of the digital signal according to the change of the resistance value of the adjustable resistor and confirms if error bits occur in the digital signal.
9. The apparatus to correct the reference voltage according to claim 6, wherein the Vref controller calculates the optimum resistance value where the occurrence of the error bits is low and sets up the resistance value of the adjustable resistor as the calculated optimum resistance value.
10. The apparatus to correct the reference voltage according to claim 6, further comprising:
an optimum resistance storing part storing the optimum resistance value. 11. The apparatus to correct the reference voltage according to claim 6, wherein the Vref controller comprises a BIOS program.
12. A method to correct a reference voltage, Vref, of digital device having a Vref adjusting circuit to adjust the Vref, comprising:
selecting a reference voltage correction; changing a setup of the Vref adjusting circuit to vary the Vref; detecting a transmission state of digital data output from the digital device, according to the changed setup of the Vref adjusting circuit; determining an optimum setup of the Vref adjusting circuit to allow error bits of the digital data to be minimized; and setting up the Vref adjusting circuit according to the optimum setup. 13. A method to correct a reference voltage, Vref, between first and second digital devices, comprising:
selecting a Vref correction via a BIOS setup menu; adjusting a resistance value; loading a digital signal corresponding to a change of the resistance value through a bus; confirming a state that the digital signal is transmitted; calculating an optimum resistance value where a Vref correction is output to minimize error bits of the transferred digital signal; setting up the resistance value as a calculated optimum resistance value; and storing the optimum resistance value. 14. The method to correct the reference voltage according to claim 13, further comprising:
analyzing signals input/output between the first and second digital devices by transmitting through the bus the digital signal corresponding to the change of the resistance value. 15. The method to correct the reference voltage according to claim 13, wherein the confirmation of the state of transmission of the digital signal according to the change of the resistance value.
16. The method to correct the reference voltage according to claim 15, further comprising:
confirming whether error bits occur in the digital signal; calculating the optimum resistance value where the occurrence of the error bits is low; and setting up the resistance value as the calculated optimum resistance value.
CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of Korean Application No. 2002-68486, filed Nov. 6, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
The present invention relates to an apparatus and a method to correct a reference voltage, more especially to an apparatus and a method to correct a reference voltage to enable the reference voltage of electric devices to be corrected using software.
Each of electric devices included in a digital system exchange data via a bus. The data exchanged via the bus has a digital form represented as an electrical 1 (high) or 0 (low). The electric devices recognize the data by recognizing a combination of 0 and 1 in transferred digital signals.
Accordingly, the electric devices have a reference voltage (Vref) to discriminate whether a received signal is 0 or 1. That is, if a voltage of the received signal is higher than the Vref, then the electric devices recognize the received signal as 1, or else if the voltage for the received signal is lower than the Vref, then the electrical devices recognize the received signal as 0.
FIG. 3 is a schematic view illustrating a circuit of a conventional device supplying the reference voltage Vref. Specifically FIG. 3 illustrates the circuit to supply the reference voltage Vref to two electric devices exchanging the digital data via the bus connected between each other.
As shown in FIG. 3, digital devices A and B 101 and 103 are provided to input/output the digital data between each other via a bus 105. The digital data is in a form of a signal electrically discriminated as 1 or 0, and, thus, the digital device A 101 and B 103 receive the Vref in order to discriminate the received signal.
The Vref is generally laid out so as to be output from a node between two resistors R1 120 and R2 106 connected in series to a VDD line, which is a main supply voltage of digital devices. The R1 120 and the R2 106 are fixed resistors and, thus, once laid out, it is impossible to adjust a resistance of the resistors R1 120 and R2 106.
Recently, as an operating speed of the electric devices is gradually increasing, noise in the digital data signal frequently occurs. Accordingly, accuracy of the Vref has been emphasized for accurate recognition of the digital data signal.
Also, in a case of transforming characteristics of the digital data signal with respect to (electromagnetic interference) EMI and, thus, tuning data transfer efficiency, the Vref is also to be adjusted according to the transformed data signal. In a case of adjusting the Vref, a user cannot manually connect resistors having different resistance values to a circuit in order to find appropriate new resistors R1 and R2 corresponding to an intended Vref, and if the user finds the appropriate new resistors R1 and R2, then the user has to change the old R1 and R2 to the new ones having an appropriate resistance value manually.
SUMMARY OF THE INVENTION In accordance with an aspect of the present invention, there is provided an apparatus for reference voltage correction and a method therefor to enable a reference voltage of electric devices to be corrected using software.
The foregoing and/or other aspects of the present invention are achieved by providing an apparatus for correcting a reference voltage (Vref) of a digital device to input/output digital data, including a Vref setup selecting part selecting a correction of the Vref; a Vref adjusting circuit adjusting the Vref of the digital device; and a Vref control storing part storing a Vref control program to change a setup of the Vref adjusting circuit to vary the Vref output from the Vref adjusting circuit to be varied, detecting a transmission state of the digital data of the digital device, determining an optimum setup of the Vref adjusting circuit to allow error bits of the digital data to be minimized, and setting up the Vref adjusting circuit according to selection of the Vref correction through the Vref setup selecting part.
According to an aspect of the present invention, the Vref control program includes a BIOS program.
According to an aspect of the present invention, the Vref adjusting circuit includes an adjustable resistor, and a fixed resistor to generate the Vref correction by dividing a main supply voltage of the digital device, wherein the Vref control program changes a resistance value of the adjustable resistor according to the selection of the Vref correction through the Vref setup selecting part, detects the transmission state of the digital data of the digital devices, determines an optimum resistance value of the adjustable resistor to allow the error bits of the digital data to be minimized, and sets up the resistance value of the adjustable resistor as the optimum resistance value.
According to an aspect of the present invention, the apparatus for correcting the reference voltage further includes a Vref optimum setup storing part to store data of optimum setup condition of the Vref adjusting circuit.
The foregoing and/or other aspects of the present invention are also achieved by providing a method to correct a reference voltage, Vref, of digital device having a Vref adjusting circuit to adjust the Vref, including selecting a reference voltage correction; changing a setup of the Vref adjusting circuit to vary the Vref; detecting a transmission state of digital data output from the digital device, according to the changed setup of the Vref adjusting circuit; determining an optimum setup of the Vref adjusting circuit to allow error bits of the digital data to be minimized; and setting up the Vref adjusting circuit according to the optimum setup.
According to an aspect of the present invention, there is provided a method to correct a reference voltage, Vref, between first and second digital devices using fixed and variable resistors, including: selecting a Vref correction via a BIOS setup menu; adjusting a resistance value of the adjustable resistor; loading a digital signal corresponding to a change of the resistance value of the adjustable resistor through a bus; confirming a state that the digital signal is transmitted; calculating an optimum resistance value of the adjustable resistor where a Vref correction is output to minimize error bits of the transferred digital signal; setting up the resistance value of the adjustable resistor as a calculated optimum resistance value; and storing the optimum resistance value.
According to an aspect of the present invention, there is provided an apparatus to correct a reference voltage, Vref, including: a first digital device and a second digital device inputting/outputting digital data via a bus; an adjustable resistor providing a main supply voltage VDD; a fixed resistor, wherein the adjustable resistor and the fixed resistor generate a Vref correction by dividing the main supply voltage VDD; a Vref setup selecting part selecting the Vref correction; and a Vref controller changing a resistance value of the adjustable resistor according to a selection of the Vref correction through the Vref setup selecting part, determining an optimum resistance value of the adjustable resistor, and outputting an optimum Vref correction.
According to an aspect of the present invention, there is provided a method to correct a reference voltage, Vref, between first and second digital devices, including: selecting a Vref correction via a BIOS setup menu; adjusting a resistance value; loading a digital signal corresponding to a change of the resistance value through a bus; confirming a state that the digital signal is transmitted; calculating an optimum resistance value where a Vref correction is output to minimize error bits of the transferred digital signal; setting up the resistance value as a calculated optimum resistance value; and storing the optimum resistance value.
FIG. 1 is a block diagram illustrating a control system of an apparatus to correct a reference voltage, according to an aspect of the present invention;
FIG. 2 is a flow chart illustrating a method to correct the reference voltage, according to an aspect of the present invention; and
FIG. 3 is a schematic view illustrating a circuit of a conventional device to supply the reference voltage.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Reference will now be made in detail to the aspects of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The aspects are described below in order to explain the present invention by referring to the figures.
FIG. 1 is a block diagram illustrating a control system of an apparatus to correct a reference voltage, according to an aspect of the present invention. As shown in FIG. 1, the apparatus for reference voltage correction includes a digital device A1 and a digital device B3 to input/output digital data via a bus 5, an adjustable resistor 18 and a fixed resistor 16 to generate a Vref (reference voltage) correction by dividing a main supply voltage VDD of the digital device A1 and B3, a Vref setup selecting part 10 to select the Vref correction, and a Vref controller 12 to change a resistance value of the adjustable resistor 18 according to a selection of the Vref correction through the Vref setup selecting part 10, thereby determining an optimum resistance value of the adjustable resistor 18 and outputting an optimum Vref. The Vref controller 12 allows setting up the adjustable resistor 18 so as to have the optimum resistance value. The apparatus also includes an optimum resistance storing part 14 to store the optimum resistance value.
The Vref setup selecting part 10 is provided for a user's selection of the Vref correction. Digital devices including the Vref correction may be of various types, such as a CPU, a memory, etc. Thus, the Vref setup selecting part 10 of a user interface adapted for one of the digital devices to be optimized, may be provided in a form of a BIOS menu.
The Vref controller 12 changes a resistance value of the adjustable resistor 18 by several mΩ, according to the selection of the Vref correction, and analyzes signals input into the digital device A1 and the digital device B3 by transmitting through the bus 5 a digital signal corresponding to the change of the resistance value of the adjustable resistor 18. The Vref controller 12 confirms a transmission state of the digital signal according to the change of the resistance value of the adjustable resistor 18 and, thus, confirms if error bits occur in the received signal. The Vref controller 12 calculates the optimum resistance value where the occurrence of the error bits is notably low and sets up the resistance value of the adjustable resistor 18 as the calculated optimum resistance value.
Furthermore, the Vref controller 12 stores the optimum resistance storing part 14 with the calculated optimum resistance value and sets up the resistance value of the adjustable resistor 18 as the optimum resistance value. Thus, until the optimum resistance value is set up again, the resistance value of the adjustable resistor 18 is set up as the calculated optimum resistance value, so that an optimum Vref can be provided.
The Vref controller 12 is implemented by software, such as a BIOS to perform the control process described above. Accordingly, the Vref setup selecting part 10 to select an optimum voltage setup of the digital devices A1 and B3 may be a BIOS setup menu provided by the BIOS.
As shown in FIG. 2, a Vref correction process for the apparatus using the reference voltage correction previously described is illustrated. Hereinafter, for illustrative purposes, it is assumed that the Vref controller 12 of the apparatus for the reference voltage correction is implemented using the BIOS software.
At operation S10, if the user selects a Vref correction via the BIOS setup menu, the Vref controller 12, or the BIOS adjusts the resistance value of the adjustable resistor 18. The Vref controller 12 transmits [loads a] the digital signal corresponding to the change of the resistance value of the adjustable resistor 18 through the bus 5, and, thus, at operation S14, confirms a state that the digital signal is transmitted. At operation S16, the Vref controller 12 calculates the optimum resistance value of the adjustable resistor 18 where the Vref correction is output to minimize the error bits of the transferred digital signal. At operation S18, the Vref controller 12 sets up the resistance value of the adjustable resistor 18 as the calculated optimum resistance value, and, at operation S20, stores the optimum resistance value. Accordingly, the digital device A1 and B3 can receive the optimum Vref. Further in a case that adjustment of the Vref is needed in the future, the Vref can be easily adjusted by repeating the above process.
In the meanwhile, in accordance with an aspect of the present invention, the resistance of the adjustable resistor is adjusted and set up, but according to an aspect of the present invention, the setup of the Vref adjusting circuit through which the optimum Vref is obtained may be maintained and updated by using software. Thus, an aspect of the present invention may be adapted to various kinds of circuits to adjust the Vref with the adjustable resistor.
With the above description, according to the present invention, when digital signals are transferred to a digital device, a Vref adjusting circuit determines, maintains, and updates an optimum Vref where error bits of the digital signals are minimized, to thereby enable the Vref to be corrected easily in an optimum condition.
As described above, according to the present invention, there is provided an apparatus and a method for correcting a reference voltage to enable the reference voltage to be corrected using software.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5132555 *Jan 31, 1991Jul 21, 1992Hitachi, Ltd.Semiconductor integrated circuitUS5568064 *May 8, 1995Oct 22, 1996International Business Machines CorporationBidirectional transmission line driver/receiverUS5966086Sep 18, 1997Oct 12, 1999Mitsubishi Denki Kabushiki KaishaMicrocomputer having an output circuit with a resistor ladderUS6876248 *May 28, 2002Apr 5, 2005Rambus Inc.Signaling accommodationJP2000207381A Title not availableJP2001109530A Title not availableKR19980048996A Title not availableKR19980060859A Title not availableKR19980079463A Title not availableKR20000003572A Title not availableKR20000015310A Title not available* Cited by examinerClassifications U.S. Classification326/33, 326/30, 327/538International ClassificationG05F1/10, G05F1/56, G05F3/18Cooperative ClassificationG05F1/56European ClassificationG05F1/56Legal EventsDateCodeEventDescriptionMar 15, 2013FPAYFee paymentYear of fee payment: 8Apr 1, 2009FPAYFee paymentYear of fee payment: 4Oct 23, 2003ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KO, WAN-SEOK;REEL/FRAME:014635/0076Effective date: 20031003RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google