Source: https://patents.google.com/patent/US7796969?oq=3723653
Timestamp: 2018-03-25 02:15:53
Document Index: 260951820

Matched Legal Cases: ['§119', 'Application No. 60', '§119', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'application No. 02']

US7796969B2 - Symmetrically and asymmetrically stacked transistor group RF switch - Google Patents
Symmetrically and asymmetrically stacked transistor group RF switch Download PDF
US7796969B2
US7796969B2 US11347014 US34701406A US7796969B2 US 7796969 B2 US7796969 B2 US 7796969B2 US 11347014 US11347014 US 11347014 US 34701406 A US34701406 A US 34701406A US 7796969 B2 US7796969 B2 US 7796969B2
US11347014
US20060194567A1 (en )
A silicon-on-insulator (SOI) RF switch adapted for improved power handling capability using a reduced number of transistors is described. In one embodiment, an RF switch includes pairs of switching and shunting stacked transistor groupings to selectively couple RF signals between a plurality of input/output nodes and a common RF node. The switching and shunting stacked transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. In one embodiment, the transistor groupings are “symmetrically” stacked in the RF switch (i.e., the transistor groupings all comprise an identical number of transistors). In another embodiment, the transistor groupings are “asymmetrically” stacked in the RF switch (i.e., at least one transistor grouping comprises a number of transistors that is unequal to the number of transistors comprising at least one other transistor grouping). The stacked configuration of the transistor groupings enable the RF switch to withstand RF signals of varying and increased power levels. The asymmetrically stacked transistor grouping RF switch facilitates area-efficient implementation of the RF switch in an integrated circuit. Maximum input and output signal power levels can be withstood using a reduced number of stacked transistors.
This application is a Continuation-in-Part (CIP) of commonly assigned U.S. patent application Ser. No. 10/922,135, filed Aug. 18, 2004 now U.S. Pat. No. 7,123,898, entitled “Switch Circuit and Method of Switching Radio Frequency Signals”, which is a continuation of U.S. Pat. No. 6,804,502 issued Oct. 12, 2004, entitled “Switch Circuit and Method of Switching Radio Frequency Signals”, filed on Oct. 8, 2002 as application Ser. No. 10/267,531, which claims the benefit under 35 U.S.C. §119 (e) of U.S. Provisional Application No. 60/328,353, filed Oct. 10, 2001, entitled “Silicon-on-Insulator RF Switches”; this application also claims the benefit under 35 U.S.C. §119 (e) of U.S. Provisional Application No. 60/650,033, filed Feb. 3, 2005, entitled “Symmetrically and Asymmetrically Stacked Transistor Grouping RF Switch”; and the contents of application Ser. No. 10/922,135, U.S. Pat. No. 6,804,502, its related provisional application (U.S. Provisional Application No. 60/328,353), and the related provisional application, U.S. Provisional Application No. 60/650,033 are incorporated by reference herein in their entirety.
The present invention relates to switches, and particularly to a switch circuit and method of switching radio frequency (RF) signals within an integrated circuit. In one embodiment, the switch circuit comprises Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices implemented on a silicon-on-insulator (SOI) substrate, for use in RF applications such as wireless communications, satellites, and cable television.
These RF switch performance parameters can be more readily described with reference to a prior art RF switch design shown in the simplified circuit schematics of FIGS. 1 a-1 c. FIG. 1 a shows a simplified circuit diagram of a prior art single pole, single throw (SPST) RF switch 10. The prior art SPST switch 10 includes a switching transistor M1 5 and a shunting transistor M2 7. Referring now to FIG. 1 a, depending upon the state of the control voltages of the two MOSFET transistors M1 5 and M2 7 (i.e., depending upon the DC-bias applied to the gate inputs of the MOSFET switching and shunting transistors, M1 and M2, respectively), RF signals are either routed from an RF input node 1 to an RF output node 3, or shunted to ground through the shunting transistor M2 7. Actual values of the DC bias voltages depend upon the polarity and thresholds of the MOSFET transistors M1 5 and M2 7. Resistor R0 9 represents the impedance of the RF source, which typically is approximately 50 ohms. FIG. 1 b shows the “on” state of the RF switch 10 of FIG. 1 a (i.e., FIG. 1 b shows the equivalent small-signal values of the transistors M1 and M2 when the RF switch 10 is “on”, with switching transistor M1 5 on, and shunting transistor M2 7 off). FIG. 1 c shows the “off” state of the switch 10 of FIG. 1 a (i.e., FIG. 1 c shows the equivalent small-signal values of the transistors M1 and M2 when the RF switch 10 is “off”, with switching transistor M1 5 off, and shunting transistor M2 7 on).
IL is approximately equal to: 10r/R0 ln (10)=0.087 r (in dB). Equation 1:
The shunting transistor M2 7 of FIG. 1 c is turned on when the switching transistor M1 5 is turned off. In this condition, the shunting transistor M2 7 acts primarily as a resistor having a value of r1. By design, the value of r1 is much less than the characteristic impedance of the RF source. Consequently, r1 greatly reduces the voltage at the input of the switching transistor M1 5. When the value of r1 is much less than the source resistance R0 9 and the feedthrough capacitive resistance of the shunting transistor M2 7, isolation is easily calculated. Switch isolation for the off state of the RF switch 10 is determined as the difference between the maximum available power at the input to the power at the output.
Switch compression occurs in one of two ways. To understand how switch compression occurs, operation of the MOSFET transistors shown in the RF switch 10 of FIGS. 1 a-1 c are described. As is well known in the transistor design arts, MOSFETs require a gate-to-source bias that exceeds a threshold voltage, Vt, to turn on. Similarly, the gate-to-source bias must be less than Vt for the switch to be off. Vt is positive for enhancement mode “type-N” MOSFETs and negative for enhancement mode “type-P” MOSFETs. Enhancement mode type-N MOSFETs were selected for the RF switch 10 of FIGS. 1 a-1 c. The source of a type-N MOSFET is the node with the lowest potential.
As shown in FIG. 2, two control voltages are used to control the operation of the prior art RF switch. The control voltages, labeled “SW”, and its inverse “SW_”, control the operation of the transistors 23, 24, 27 and 28. The control voltages are arranged to alternatively enable (turn on) and disable (turn off) selective transistor pairs. For example, as shown in FIG. 2, when SW is on (in some embodiments this is determined by the control voltage SW being set to a logical “high” voltage level, e.g., “+Vdd”), the switching transistor 23 is enabled, and its associated shunting transistor 28 is also enabled. However, because the inverse of SW, SW_, controls the operation of the second switching transistor 24, and its associated shunting transistor 27, and the control signal SW_ is off during the time period that SW is on (in some embodiments this is determined by SW being set to a −Vdd value), those two transistors are disabled, or turned off, during this same time period. In this state (SW “on” and SW_ “off”), the RF, input signal is coupled to the RF common port 25 (through the enabled switching transistor 23). Because the second switching transistor 24 is turned off, the RF2 input signal is blocked from the RF common port 25. Moreover, the RF2 input signal is further isolated from the RF common port 25 because it is shunted to ground through the enabled shunting transistor 28. As those skilled in the transistor designs arts shall easily recognize, the RF2 signal is coupled to the RF common port 25 (and the RF, signal is blocked and shunted to ground) in a similar manner when the SW control signal is “off” (and SW_ is “on”).
A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit may be used in wireless applications, and may be fabricated in a silicon-on-insulator technology. In one embodiment, the RF switch is fabricated on an Ultra-Thin-Silicon (“UTSi”) substrate. In one embodiment, the RF switch includes a plurality of switching (or “pass”) “stacked” (i.e., two or more transistors are coupled together in series forming a stacked transistor grouping) transistor groupings and a plurality of shunting stacked transistor groupings. In one embodiment, a first switching stacked transistor grouping is coupled to a first RF input port. A second switching stacked transistor grouping is coupled to a second RF input port. Both the first and second switching stacked transistor groupings are coupled to an RF common port. In this embodiment, a first node of a first shunting stacked transistor grouping is coupled to the first RF input port. A second node of the first shunting stacked transistor grouping is coupled to ground. A first node of a second shunting stacked transistor grouping is coupled to the second RF input port. A second node of the second shunting stacked transistor grouping is coupled to ground.
In one embodiment, the RF switch comprises a “symmetrically” stacked transistor grouping RF switch, wherein all of the stacked transistor groupings comprise an equal number of transistors. In another embodiment, the RF switch comprises an “asymmetrically” stacked transistor grouping RF switch, wherein not all of the stacked transistor groupings comprise an equal number of transistors. Stated in other terms, in this embodiment, the asymmetrically stacked RF switch includes at least one stacked transistor grouping comprising a number of transistors that is unequal to the number of transistors comprising at least one other stacked transistor grouping. In another embodiment, more than two RF input ports are switchably coupled to an RF common port (in one exemplary embodiment, an antenna) via asymmetrically stacked transistor groupings in an asymmetrically stacked transistor grouping RF switch.
The inventive symmetrically and asymmetrically stacked transistor grouping RF switch accommodates RF input signals having differing input and output power levels. The asymmetrically stacked transistor grouping RF switch accommodates various power levels in a highly area-efficient manner. In accordance with the present inventive asymmetrically stacked transistor grouping RF switch, a minimum number of transistors can be used in order to withstand the maximum power levels in any selected input/output path. As a result, an RF switch integrated circuit (IC) can be implemented wherein the RF switch accommodates maximum power levels in any input/output path using a minimum number of transistors. This yields improved RF switch designs, and vastly reduces the IC area required for RF switch implementations.
FIG. 5 a is a simplified block diagram of one exemplary embodiment of the negative voltage generator shown in the simplified block diagram of FIG. 4;
FIG. 5 b is an electrical schematic of a first embodiment of a charge pump circuit that is used to generate a negative supply voltage to the RF switch of FIG. 4.
FIG. 6 a is an electrical schematic of a first embodiment of an inventive level shifting circuit;
FIG. 6 b is an electrical schematic of one embodiment of the inverters used to implement the level shifter shown in FIG. 6 a.
FIG. 7 a is a voltage amplitude versus time plot of a digital input signal and corresponding output signal generated by the inventive level shifter of FIG. 6 a;
FIG. 7 b is a simplified logic symbol for the inventive level shifter of FIG. 6 a.
FIG. 8 a is an electrical schematic of one embodiment of a two-stage level shifter and RF buffer circuit including a first stage level shifter and a second stage RF buffer circuit;
FIG. 8 b is a simplified block diagram of the digital control input and interface to the RF buffer circuit of FIG. 8 a.
FIG. 9 a is an electrical schematic of one embodiment of a low current voltage divider (LCVD) circuit made in accordance with the present RF switch invention;
FIG. 9 b is a simplified logic symbol used to represent the voltage divider of FIG. 9 a.
FIG. 13 illustrates an embodiment of a symmetrically stacked transistor grouping single-pole double-throw (SPDT) RF switch.
FIG. 14 illustrates an embodiment of an asymmetrically stacked transistor grouping single-pole double-throw (SPDT) RF switch.
FIG. 15 illustrates another embodiment of an asymmetrically stacked transistor grouping RF switch implemented as a single-pole 4-throw RF switch.
FIGS. 16A-D illustrate equivalent circuits corresponding to the switching states of the asymmetrically stacked transistor grouping RF switch of FIG. 15.
In one embodiment of the present inventive RF switch, the MOSFET transistors (e.g., the transistors M37A, M37B, and M37C) are implemented using a fully insulating substrate silicon-on-insulator (SOI) technology. More specifically, and as described in more detail hereinbelow, the MOSFET transistors of the inventive RF switch are implemented using “Ultra-Thin-Silicon (UTSi)” (also referred to herein as “ultrathin silicon-on-sapphire”) technology. In accordance with UTSi manufacturing methods, the transistors used to implement the inventive RF switch are formed in an extremely thin layer of silicon on an insulating sapphire wafer. The fully insulating sapphire substrate enhances the performance characteristics of the inventive RF switch by reducing the deleterious substrate coupling effects associated with non-insulating and partially insulating substrates. For example, improvements in insertion loss are realized by lowering the transistor on resistances and by reducing parasitic substrate resistances. In addition, switch isolation is improved using the fully insulating substrates provided by UTSi technology. Owing to the fully insulating nature of silicon-on-sapphire technology, the parasitic capacitance between the nodes of the RF switch 30 are greatly reduced as compared with bulk CMOS and other traditional integrated circuit manufacturing technologies. Consequently, the inventive RF switch exhibits improved switch isolation as compared with the prior art RF switch designs.
In one embodiment, the transistor grouping gate resistors comprise approximately 30 K ohm resistors, although alternative resistance values can be used without departing from the spirit or scope of the present invention. In addition, in some embodiments of the present invention, the gate resistors comprise any resistive element having a relatively high resistance value. For example, reversed-biased diodes may be used to implement the gate resistors in one embodiment. As described in more detail below, the gate resistors help to increase the effective breakdown voltage across the series connected transistors.
The control voltages are connected to alternatively enable and disable selective pairs of transistor groupings. For example, as shown in FIG. 3, when SW is on (in some embodiments this is determined when the control voltage SW is set to a logical “high” voltage level), the switching transistor grouping 33 is enabled (i.e., all of the transistors in the grouping 33 are turned on), and its associated shunting transistor grouping 38 is also enabled (i.e., all of the transistors in the grouping 38 are turned on). However, similar to the operation of the switch of FIG. 2, because the inverse of SW, SW_, controls the operation of the second switching transistor grouping 34, and its associated shunting transistor grouping 37, these two transistors groupings are disabled (i.e., all of the transistors in the groupings 34, 37 are turned off) during this time period. Therefore, with SW on, the RF1 input signal is coupled to the RF common port 35. The RF2 input signal is blocked from the RF common port 35 because the switching transistor grouping 34 is off. The RF2 input signal is further isolated from the RF common port 35 because it is shunted to ground through the enabled shunting transistor grouping 38. As those skilled in the RF switch design arts shall recognize, the RF2 signal is coupled to the RF common port 35 (and the RF, signal is blocked and shunted to ground) in a similar manner when the SW control signal is off (and the SW_ control signal is on).
Fabrication of devices on an insulating substrate requires that an effective method for forming silicon MOSFET devices on the insulating substrate be used. The advantages of using a composite substrate comprising a monocrystalline semiconductor layer, such as silicon, epitaxially deposited on a supporting insulating substrate, such as sapphire, are well-recognized, and can be realized by employing as the substrate an insulating material, such as sapphire (Al2O3), spinel, or other known highly insulating materials, and providing that the conduction path of any inter-device leakage current must pass through the substrate.
Examples of and methods for making such silicon-on-sapphire devices are described in U.S. Pat. Nos. 5,416,043 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); 5,492,857 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); 5,572,040 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); 5,596,205 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); 5,600,169 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); 5,663,570 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); 5,861,336 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); 5,863,823 (“Self-aligned edge control in silicon on insulator”); 5,883,396 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); 5,895,957 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); 5,920,233 (“Phase locked loop including a sampling circuit for reducing spurious side bands”); 5,930,638 (“Method of making a low parasitic resistor on ultrathin silicon on insulator”); 5,973,363 (“CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator”); 5,973,382 (“Capacitor on ultrathin semiconductor on insulator”); and 6,057,555 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”). All of these referenced patents are incorporated herein in their entirety for their teachings on ultrathin silicon-on-sapphire integrated circuit design and fabrication.
Using the methods described in the patents referenced above, electronic devices can be formed in an extremely thin layer of silicon on an insulating synthetic sapphire wafer. The thickness of the silicon layer is typically less than 150 nm. Such an “ultrathin” silicon layer maximizes the advantages of the insulating sapphire substrate and allows the integration of multiple functions on a single integrated circuit. Traditional transistor isolation wells required for thick silicon are unnecessary, simplifying transistor processing and increasing circuit density. To distinguish these above-referenced methods and devices from earlier thick silicon embodiments, they are herein referred to collectively as “ultrathin silicon-on-sapphire.”
As described and claimed in these patents, high quality silicon films suitable for demanding device applications can be fabricated on insulating substrates by a method that involves epitaxial deposition of a silicon layer on an insulating substrate, low temperature ion implantation to form a buried amorphous region in the silicon layer, and annealing the composite at temperatures below about 950° C. Any processing of the silicon layer which subjects it to temperatures in excess of approximately 950° C. is performed in an oxidizing ambient environment. The thin silicon films in which the transistors are formed typically have an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×1011 cm−2.
For a MOSFET switch, the design of the off transistor also limits the 1 dB compression point of the switch. As is well known in the transistor design arts, MOS transistors have a fundamental breakdown voltage between their source and drain. When the potential across the device exceeds this breakdown voltage, a high current flows between source and drain even when a gate potential exists that is attempting to keep the transistor in an off state. Improvements in switch compression can be achieved by increasing the breakdown voltage of the transistors. One method of fabricating a MOS transistor with a high breakdown voltage is to increase the length of the gate. Unfortunately, an increase in gate length also disadvantageously increases the channel resistance of the device thereby increasing the insertion loss of the device. The channel resistance can be decreased by making the device wider, however this also decreases the switch isolation. Hence, tradeoffs exist in MOS switch designs.
In contrast, in accordance with the present RF switch invention, using UTSi technology, the circuitry necessary for the proper operation and functioning of the RF switch can be integrated together on the same integrated circuit as the switch itself. For example, and as described below in more detail, by implementing the RF switch in UTSi technology, the RF switch can be integrated in the same integrated circuit with a negative voltage generator and the CMOS control logic circuitry required to control the operation of the RF switch. The complexity of the RF switch is also reduced owing to the reduction in control lines required to control the operation of the switch. Advantageously, the RF switch control logic can be implemented using low voltage CMOS transistors. In addition, even for high power RF switch implementations, a single, relatively low power external power supply can be used to power the present inventive RF switch. This feature is advantageous as compared to the prior art GaAs implementations that require use of a relatively high power external power supply and power generation circuitry necessary to generate both positive and negative power supplies. For example, in the exemplary embodiments described below with reference to FIGS. 4-12, the present inventive RF switch requires only a single 3 V external power supply. The prior art switch designs typically require at least a 6 volt external power supply, and external voltage generation circuitry to generate both positive and negative power supplies.
Negative Voltage Generator-Charge Pump—A First Embodiment
Referring again to FIG. 6 a, the level shifter uses a feedback approach to shift the digital input signals to voltage levels ranging from −Vdd to +Vdd. Specifically, the output of the second group of inverters (308, 310, 312) on the second output node 316 (i.e., the “out” signal) is provided as feedback to an input of the first group of inverters at the input of the inverter 304. Similarly, the output of the first group of inverters (302, 304, 306) on the first output node 314 (i.e., the “out” output signal) is provided as input to the second group of inverters, specifically, is provided as input to the inverter 310.
When the digital input signal on the input node 318 reaches a logical “high” state (i.e., in some embodiments, when the input signal transitions from GND to +Vdd), the “in” signal (at the node 324) and the “in_” signal (at the node 326) go to ground (e.g., 0 VDC) and Vdd (e.g., 3 VDC), respectively. The “out” signal at the first output node 314 is driven to +Vdd. At the same time, the “out” signal at the second output node 316 is driven towards −Vdd. The feedback (of “out_” fed back to the input of the inverter 304 and “out” fed forward to the input of the inverter 310) configuration ensures the rapid change in state of the level shifter 300. The level shifter 300 works similarly when the input signal transitions from a logic high to a logic low state (i.e., transitions from +Vdd to GND). When the digital input signal on the input node 318 reaches a logic “low” state, the “in” signal (at the node 324) and the “in_” signal (at the node 326) go to Vdd (e.g., 3 VDC), and ground, respectively. The “out” signal at the first output node 314 is driven to −Vdd. At the same time, the “out_” signal at the second output node 316 is driven towards +Vdd. The feedback again ensures the rapid change in state of the level shifter 300. The grounding contribution ensures that the level shifter inverters never see more than a full Vdd voltage drop across the source/drain nodes of the MOSFET transistors of the inverters.
Thus, using the present inventive level shifter 300, digital input signals that initially range from GND to +Vdd are shifted to range from −Vdd to +Vdd. FIG. 7 a shows a voltage amplitude versus time plot of the digital input signal and the corresponding output signal that is generated by the inventive level shifter 300 of FIG. 6 a. As shown in FIG. 7 a, the digital input signal ranges from ground, or 0 VDC to Vdd. The output of the inventive level shifter 300 ranges from −Vdd to +Vdd. In one embodiment of the present inventive RF switch, the input signal ranges from 0 VDC to +3 VDC, and the output of the level shifter 300 ranges from −3 VDC to +3 VDC. Other values of power supply voltages can be used without departing from the scope or spirit of the present invention. For example, in one embodiment, the input signal can range from 0 to +3.5 VDC, or from 0 to −4 VDC. In this embodiment, the level shifter shifts the signal to range from −3.5 (or −4) VDC, to +3.5 (or +4) VDC.
The RF buffer electrically isolates the digital control signals (such as those generated by the CMOS logic block 110 of FIG. 4) from the RF switch 30 described above with reference to FIG. 3. The RF buffer 402 functions to inhibit drooping of the control voltages (SW, SW_, which are also referred to herein and shown in FIG. 8 a as the control signals “out” and “out_, respectively) that control the enabling and disabling of the transistors in the RF switch 30. As described below in more detail, the RF buffer 402 also functions to prevent coupling of large power RF signals to the negative power supply (i.e., −Vdd) that is generated by the charge pump circuit 206 described above with reference to FIGS. 5 a-5 c. More specifically, the RF buffer 402 prevents large power RF signals extant in the RF switch 30 from RF-coupling to, and thereby draining current from, the negative power supply generated by the charge pump 206 (FIG. 5 b).
More specifically, and referring again to FIG. 8 a, the level shifter 300 inputs the digital control signals “in” and its inverse signal “in_” at the nodes 328, 330 respectively (as described in more detail above with reference to FIG. 6 a). The first output of the level shifter 300, “out1”, at the output node 314, is fed back to the input of the inverter 310 as shown. Similarly, the second output of the level shifter 300, “out1_”, at the output node 316, is fed back to the input of the inverter 304. As described above, because of this feedback topology, RF coupling occurs (i.e., the level shifter output signals have RF signals superimposed thereon) if the output signals of the level shifter are used to directly control the RF switch transistors (i.e., in the absence of the buffer circuit 402). Therefore the inventive RF buffer circuit 402 is used without feedback of the output signals to isolate the input signals (i.e., the digital input signals “in” and “in”) from the RF signals present in the RF switch. As shown in FIG. 8 a, the first output signal “out1” of the level shifter 300 is input to the inverters 404, 406 of the RF buffer circuit. Similarly, the second output signal “out1_” of the level shifter 300 is input to the inverters 410, 412 of the buffer circuit. The two control outputs of the RF buffer circuit 402 (“out” and “out_”) control the enabling and disabling of the transistors of the RF switch and are not provided as feedback to the level shifter. Hence, improved isolation between the RF switch and the digital logic circuitry is achieved.
The diode devices are used to divide the voltage of an input signal provided to the voltage divider 500 at an input node 514. As shown in FIG. 9 a, the signal that is divided by the voltage divider 500 is provided as input to the drain (and connected gate) of the first device 502. Once the input signal exceeds a positive voltage level of (n*Vthn), where “n” is the number of diode devices used to implement the voltage divider 500, and Vthn is the threshold voltage of the device (i.e., the “diode-drop” from the drain to the source of the device), the diode devices (502, 504, 506, and 508) begin to conduct current heavily. In the embodiment shown in FIG. 9 a, n=4, and Vthn=0.7 volts, although alternative values for “n” and Vthn can be used without departing from the scope or spirit of the present invention. For example, in other embodiments, the input signal provided to the divider can be limited to any desired voltage level by varying the number of diode devices used to implement the voltage divider 500 (i.e., by varying the value of “n”). In the embodiment shown in FIG. 9 a, once the input voltage exceeds a voltage level of (4*0.7), or 2.8 volts, the stacked diode devices begin conducting heavily.
A ballast resistor, R 516, is connected to the source of the output diode device 508 as shown. Once the diode devices turn on fully, the ballast resistor R 516 drops any additional input voltage that exceeds the value of n*Vthn. In the embodiment shown in FIG. 9 a, the ballast resistor R 516 drops any additional input voltage exceeding the value of (input voltage −(4*Vthn)). The output of the voltage divider 500 is tapped from the connected gate-drain of the output diode device 508. The voltage-divided output signal is provided on an output node 520. Due to the diode voltage drops of the diode devices 502, 504, 506, (i.e., 3*Vthn), and the voltage dropped across the ballast resistor R 516, the output at the output node 520 is guaranteed to never exceed approximately (input voltage−(3*Vthn)). For Vthn=approximately 0.7 volts, and a maximum input voltage of approximately 3 volts, the output node 520 will never exceed (3 VDC−(3*0.7 VDC)), or 0.9 VDC. Thus, in the embodiment shown in FIG. 9 a, for an input voltage ranging between −3 VDC to +3 VDC, the voltage divider 500 limits the output of the output node 520 to a range of −3 VDC to 0.9 VDC.
In one embodiment, the ballast resistor R 516 has a value of 100 k-ohms. In one embodiment all of the devices of the voltage divider 500 have the same length. For example, in one embodiment, all of the devices have a length of 0.8 micro-meters. In one embodiment, all of the diode devices (502, 504, 506, and 508) have identical physical dimensions. In one embodiment, the diode devices each have a width of 2 micro-meters, the device M3 510 has the same width of 2 micro-meters, and the output MOSFET M2 512 has a width of 14 micro-meters. Those skilled in the integrated circuit design, arts shall recognize that other values and alternative configurations for the devices shown in FIG. 9 a can be used without departing from the scope or spirit of the present invention. For example, those skilled in the electrical circuit design arts shall recognize that other voltage divider output levels can easily be accommodated by varying the number “n” of diode elements, varying the values of Vthn, or by tapping the output node 520 at a different point in the stack of diode devices (e.g., by tapping the output from the drain of diode device 506, or 504, instead of from the drain of device 508 as shown).
By reducing the voltages that are applied to the gate oxides of the RF switch transistors, the voltage divider 500 of FIG. 9 a and 9 b advantageously can be used to increase the reliability of the transistors in both the level shifter 300 and the charge pump circuit described above. For example, FIG. 10 shows a modified level shifter 600 using the voltage divider 500 of FIG. 9 a in combination with the level shifter 300 of FIG. 6 a. As shown in FIG. 10, the output (at output node 314) of the inverter 306 of the level shifter 300 is applied to an input of a first voltage divider 500′. Similarly, the output (at the output node 316) of the inverter 312 of the level shifter 300 is applied to an input of a second voltage divider 500″. The outputs of the voltage dividers are fed back to the input of the feedback inverters 304, 310 as shown in FIG. 10. Specifically, and referring to FIG. 10, the output of the first voltage divider, “out”, on the output node 520′ is fed back to the input of the feedback inverter 310. Similarly, the output of the second voltage divider, “out_”, on the output node 520″ is fed back to the input of the feedback inverter 304. As described above with reference to FIG. 9 a, the level shifters 500′ and 500″ reduce the feedback voltages to ranges of −Vdd to approximately +0.9 VDC. This reduced voltage swing on the feedback paths does not alter the function of the level shifter 600.
The RF buffer inverters 702, 704 are used to control the power supply voltages of a first RF output inverter 712. Similarly, the RF buffer inverters 708, 710 are used to control the power supply voltages of a second RF output inverter 714. In this embodiment, the RF buffer output signals, “out” and “out_” are used to control the RF switch (i.e., output signal “out” acts as control voltage “SW”, while “out_” acts as control voltage “SW_”).
The four modified level shifters generate the half-rail clock control signals that are used to control the charge pump 206′. Specifically, as shown in FIG. 12, the four level shifters generate the “CLK1POS_”, “CLK1NEG_”, “CLK2POS”, and “CLK2NEG” control signals that are input to the charge pump transistor gate control nodes 250, 252, 254 and 256, respectively. In the embodiment shown in FIG. 12, the level shifters 806 and 808 generate the four transistor gate control signals “CLK1POS_”, “CLK1NEG_”, “CLK2POS”, and “CLK2NEG”. The level shifter 806 generates the “CLK1POS_”, and “CLK1NEG_” gate control signals, while the level shifter 808 generates the “CLK2POS”, and “CLK2NEG” gate control signals. More specifically, as shown in FIG. 12, the “out_pos” output of the level shifter 806 (“CLK1POS_”) is coupled to control the transistor gate input 250 of the transistor 208. The “out_neg” output of the level shifter 806 (“CLK1NEG_”) is coupled to control the transistor gate input 252 of the transistor 210. Similarly, the “out_pos” output of the level shifter 808 (“CLK2POS”) is coupled to control the transistor gate input 254 of the transistor 214. Finally, the “out_neg” output of the level shifter 808 (“CLK2NEG”) is coupled to control the transistor gate input 256 of the transistor 214. The clock generation circuit 802 functions to prevent excessive voltages across the gate oxides of the charge pump transistors.
Transistor Stacking—Symmetrically Stacked Transistor Grouping RF Switch
Referring again to FIG. 3, as noted above, the RF switch 30 can accommodate input signals of increased and varying power levels. Owing to the serial coupling of the individual MOSFET transistors (i.e., “stacking”) comprising the transistor groupings (i.e., the switching and shunting transistor groupings 33, 34, 37 and 38), increased power signals can be presented at the RF input nodes (i.e., at the input nodes 31 and 32) without detrimentally affecting switch operation. Transistor stacking advantageously aids the RF switch 30 in withstanding increased power level signals applied to the RF input/receive ports. For example, the shunting stacked transistor grouping 37 comprises the stacked transistors M37A, M37B, M37 coupled together in series. In one embodiment, each stacked transistor in the transistor grouping shares an equal voltage drop across its source and drain. Hence, as larger power levels are applied to either of the RF input nodes 31, 32, the serially coupled stacked transistors share voltage drops equally. Because each of the transistor groupings shown in the switch 30 of FIG. 3 comprises an equal number of serially coupled transistors, the RF switch is referred to herein as a “symmetrically” stacked transistor grouping RF switch.
Those skilled in the IC and transistor design arts art shall recognize that increased RF input/output power levels can easily be accommodated within the RF switch by increasing the number of transistors per transistor grouping. By simply increasing the number of serially coupled stacked transistors, the RF switch can accommodate increased maximum input/output RF power levels. In one embodiment, increases in RF input/output power levels can also be accommodated by varying the physical implementation of the stacked transistors. For example, in one embodiment, the transistors comprise approximately 0.5×2,100 micro-meters in dimension. However, other physical configurations of the transistors can be used without departing from the scope or spirit of the present invention. In yet another embodiment, increased RF input/output power levels are accommodated within the RF switch by both increasing the number of stacked transistors per transistor grouping, and by varying the physical implementation of the stacked transistors.
Referring now to FIG. 13 another embodiment of a symmetrically stacked transistor grouping RF switch is shown. More specifically, FIG. 13 shows an embodiment of a symmetrically stacked transistor grouping single-pole double-throw (SPDT) RF switch. Although a symmetrically stacked transistor grouping SPDT RF switch is shown in FIG. 13 and described herein, those skilled in the electronic design arts shall appreciate that switches having virtually any practical combination and number of poles and/or throws may be implemented in accordance with the present teachings. Therefore, although the present disclosure describes the symmetrically stacked transistor grouping RF switch using an exemplary single-pole double-throw configuration, configurations of symmetrically stacked transistor grouping RF switches having any practical combination and number of poles and/or throws fall within the spirit and scope of the present teachings. As shown in FIG. 13, the RF switch 1300 uses five stacked transistors for each transistor grouping in the RF switch 1300. Similar to the RF switch 30 of FIG. 3, the RF switch 1300 is symmetrically stacked wherein each transistor grouping, 1304, 1306, 1310, and 1314, comprises an equal number of stacked transistors. Operation of the RF switch 1300 is similar to the operation of the RF switch 30 described above with reference to FIG. 3. However, by increasing the number of stacked transistors in the transistor groupings from three to five, the RF switch is able to withstand input and receive RF signals having power levels that are increased by a ratio of (5/3)2. Note that power levels are proportional to voltage levels squared.
Transistor stacking may be implemented using different fabrication technologies, such as, for example, Gallium-Arsenide, thin-film SOI CMOS, and SOS CMOS. Other implementation technologies may be employed without departing from the sprit and scope of the invention.
Transistor Stacking—Asymmetrically Stacked Transistor Grouping RF Switch
Referring now to FIG. 14, an asymmetrically stacked transistor grouping RF switch 1400 is shown. More specifically, FIG. 14 illustrates an embodiment of an asymmetrically stacked transistor grouping single-pole double-throw (SPDT) RF switch. As many applications do not require symmetric stacking, the inventive asymmetrically stacked transistor grouping RF switch 1400 advantageously preserves physical area in an RF switch integrated circuit. Physical area occupied by a group of stacked transistors increases as the square of the number of transistors increases. The physical area occupied by a group of transistors increases according to the well-known “square-law”, as illustrated in equation 2 shown below:
A∝N 2 Equation 2
Equation 2 describes that the area (“A”) occupied by the transistors in a stacked transistor group increases with the square of the number of transistors in a group (“N”). For example, if an on resistance (“Ron”) of a transistor comprises 5 ohms, and a FET resistance (“RFET”) comprises a channel impedance of 10 ohms-mm, a single FET group has a channel width of 2 mm, which closely approximates the width of the FET group. If an additional FET is added to the group, thereby making the total FET group comprising two FETs, the stack height is doubled. Further, the channel width of each FET must be doubled to maintain a total resistance of 5 ohms. Therefore, the area of the two FET group must be approximately four times as large as the area of the single FET group. Hence, by asymmetrically stacking transistors in an RF switch in accordance with the present teachings, circuit designers can vastly reduce the physical area occupied by transistor devices in applications where IC real estate is a premium.
Referring again to FIG. 14, one exemplary embodiment of asymmetrically stacked switching and shunting transistor groupings in an RF switch is shown. Although an asymmetrically stacked transistor grouping SPDT RF switch is shown in FIG. 14 and described herein, those skilled in the electronic design arts shall appreciate that asymmetrically stacked RF switches having virtually any practical combination and number of poles and/or throws may be implemented in accordance with the present teachings. Therefore, although the present disclosure describes the asymmetrically stacked transistor grouping RF switch using an exemplary single-pole configuration, configurations of asymmetrically stacked transistor grouping RF switches having any practical combination and number of poles and/or throws fall within the spirit and scope of the present teachings. For exemplary purposes, each transistor is assumed to have a 2.5 volt peak voltage (i.e., 5 volt peak-to-peak) drop (between drain and source), however other voltage drops are contemplated and depend on the system and process parameters. In one embodiment, wherein the input port TX 1402 is coupled (via operation of control signals SW and SW_ applied to the gates of the transistors in the transistor groupings) to an antenna 1426, a 5 volt peak voltage maximum signal is applied to TX 1402, and RX 1412 is grounded at its input (via the turned-on transistor grouping 1410).
In the illustrated embodiments, the highest voltage appearing on any one particular path dictates the number of transistors that are required in other paths, in order to withstand the voltage in the highest voltage path. Referring again to FIG. 14, assume that an RF transmit signal appearing on the RF input node TX 1402 comprises the highest voltage present on any of the paths (e.g., higher than the maximum voltage present on the receive input node RX 1412). For example, when a 5 volt peak voltage RF transmit signal is applied to the RF input node TX 1402, and therefore is applied to the antenna 1426 (via the turned-on transistor grouping 1406), the transistor grouping 1408 must comprise a number of stacked transistors sufficient to withstand this maximum RF power level (e.g., sufficient to withstand the 5 volts peak voltage signal applied to the RF input node TX 1402). The number of transistors required to implement the transistor grouping 1408 is dictated by the maximum peak voltage signal applied to the input port TX 1402. In this example, 5 volts peak voltage is applied to the input node 1402. Assuming that each stacked transistor in the transistor grouping has a 2.5 V voltage drop (drain-to-source), two transistors are required to implement the switching transistor grouping 1408 (i.e., 5.0 volts divided by 2.5 voltage drop per transistor). Similarly, the shunting transistor grouping 1404 must also be able to withstand the maximum power level applied to the RF input node 1402 when the shunting transistor grouping 1404 is turned off. In this example, because the maximum voltage applied to the RF input node TX 1402 comprises 5 volts peak voltage, the shunting transistor grouping 1404 requires two transistors (again, assuming that each transistor in the transistor grouping has a 2.5 volt voltage drop).
Extending this example to higher power level RF signals, if a voltage applied at TX 1402 comprises a 10 volt peak voltage RF signal, for the reasons set forth above, four transistors are required to implement the transistor groupings 1404 and 1408. And the shunt transistor grouping 1404 must also comprise 4 transistors in order to withstand the 10 volts on the input of TX 1402, which is the greatest power path.
In a lower voltage path, such as, for example, the receive RF output node RX 1412, when the shunting transistor grouping 1410 is turned off, the shunting transistor grouping 1410 must withstand the maximum voltage applied on the receive output node RX 1412. If the maximum voltage appearing on RX 1412 is 2.5 volts peak voltage, the shunting transistor grouping 1410 requires only one transistor. In this example, if the 2.5 volt peak voltage signal is applied to the receive output node RX 1412, the switching transistor grouping 1406 requires only a single transistor to withstand the 2.5 volts applied at RX 1412. Alternatively, if the maximum voltage applied to the receive output node RX 1412 comprises 5 volts peak voltage, two transistors are required to implement the shunting transistor grouping 1410, and two transistors are required to implement the switching transistor grouping 1406. Those skilled in the IC and transistor design arts shall appreciate that more or less stacked transistors can be used to accommodate RF signals of virtually any power level.
Referring now to FIG. 15, another embodiment of an asymmetrically stacked transistor grouping RF switch is shown in a single-pole 4-throw configuration. As shown in FIG. 15, a plurality of asymmetrically stacked transistor grouping RF switches can be used to implement switching between a plurality of RF transmit and receive ports, such as, for example, RF ports TX1 1518, TX2 1542, RX1 1548, and RX2 1532. In one embodiment, the RF input port TX1 1518 receives an RF signal having a maximum voltage of 20 volts peak voltage, whereas the RF input port TX2 1542 inputs an RF signal having a maximum voltage of 17.5 volts peak voltage. As described below in more detail, each transistor in FIG. 15 is presumed to have a 2.5 volt drop across it, however depending on system requirements and IC processes, other voltage drops and respective transistor stacking configurations are contemplated and fall within the scope of the present inventive RF switch.
A description of the operation of the asymmetrically stacked transistor grouping RF switch 1500 of FIG. 15 is described below with reference to a description of FIGS. 16A-D. FIGS. 16A-D illustrate different equivalent circuits, corresponding to various operational aspects and switching states of the asymmetrically stacked transistor grouping RF switch 1500 of FIG. 15. More specifically, FIGS. 16A, 16B, 16C, and 16D illustrate equivalent circuits corresponding to four different switching states of the RF switch 1500 of FIG. 15 (namely, the “TX1”, “TX2”, “RX1”, and “RX2” states). If a transistor grouping is turned on, an equivalent circuit for the transistor grouping is modeled as a resistor. If a transistor grouping is turned off, an equivalent circuit for the turned-off transistor grouping is modeled as a capacitor.
FIG. 16A shows an equivalent circuit of the switch 1500 of FIG. 15 wherein the transmit path TX1 1518 is connected to an antenna 1550, through the turned-on transistor grouping 1502 (i.e., when the RF switch 1500 is configured in the “TX1” state). The input port TX1 1518 of FIG. 15 is represented in FIG. 16A as an equivalent input port 1602, and the turned-on transistor grouping 1502 is represented in FIG. 16A as a resistor 1604. Turned-off transistor groupings 1504, 1510, and 1512 of FIG. 15 are represented in FIG. 16A as capacitive elements 1608, 1628, and 1630, respectively. In one exemplary embodiment, the RF signal applied to the RF input port TX1 1518 comprises a 20 volts peak voltage signal. Hence, each capacitive element 1608, 1628, and 1630 of FIG. 16A must be able to withstand a maximum voltage of 20 volts peak voltage. Similarly, each corresponding transistor grouping 1504, 1510, and 1512 of the RF switch 1500 of FIG. 15 must also be able to withstand a maximum voltage of 20 volts peak voltage when in their turned-off state. Assuming a 2.5 v maximum peak voltage drop across each stacked transistor, each of these transistor groupings (1504, 1510, and 1512) must comprise a minimum of eight transistors in order to withstand the maximum 20 volts peak voltage input signal.
A shunting capacitive element 1612 of FIG. 16A is the equivalent circuit element for the turned-off shunting transistor grouping 1506 of FIG. 15. The shunting capacitive element 1612 must withstand the 20 volts peak voltage input signal applied to the input node 1602. Similarly, the shunting transistor grouping 1506 must also withstand the 20 volts peak voltage signal applied to the RF input node TX1 1518. Therefore, assuming a 2.5 v maximum peak voltage drop per transistor, the shunting transistor grouping 1506 comprises a minimum of eight transistors.
FIG. 16B shows an equivalent circuit of the asymmetrically stacked transistor grouping RF switch 1500 of FIG. 15 wherein the input transmit node TX2 1542 is coupled to the antenna 1550 via the turned-on transistor grouping 1510 (i.e., when the RF switch 1500 is configured in the “TX2” state). The RF input port TX2 1542 of FIG. 15 is represented in FIG. 16B as an equivalent RF input port 1622, and the turned-on transistor grouping 1510 is represented in FIG. 16B as a resistor 1662. Turned-off transistor groupings 1502, 1504, and 1512 of FIG. 15 are represented in FIG. 16B as capacitive elements 1638, 1608, and 1630, respectively. In one exemplary embodiment, the RF signal applied to the RF input port TX2 1542 comprises a 17.5 volts peak voltage signal. Hence, each capacitive element 1638, 1608, and 1630 of FIG. 16B must be able to withstand a voltage of 17.5 volts peak voltage. Similarly, each corresponding transistor grouping, 1502, 1504, and 1512, respectively, must be able to withstand an applied voltage of 17.5 volts peak voltage. Assuming a 2.5 v peak voltage drop across each stacked transistor, each of these transistor groupings (1502, 1504 and 1512) must comprise a minimum of seven transistors (17.5 volts divided by a 2.5 volt drop across each transistor) in order to withstand the maximum 17.5 volts peak voltage input signal when the switch is in the TX2 state. However, due to the voltage withstand requirements of the TX1 state, the 1504 and 1512 transistor groupings comprise a minimum of eight transistors as described above.
A shunting capacitive element 1658 of FIG. 16B comprises an equivalent circuit element for the turned-off shunting transistor grouping 1514. The shunting transistor grouping 1514 must withstand the 17.5 volts peak voltage signal applied to the input node TX2 1542. Therefore, assuming that each transistor has a 2.5 volt peak voltage drop, the shunting transistor grouping 1514 requires a minimum of seven transistors (17.5 volts divided by a 2.5 volt drop per transistor).
FIG. 16C shows an equivalent circuit of the asymmetrically stacked transistor grouping RF switch 1500 of FIG. 15 wherein the RF output receive node RX1 1548 is coupled to the antenna 1550 via the turned-on transistor grouping 1504 (i.e., when the RF switch 1500 is configured in the “RX1” state). The RF output port RX1 1548 of FIG. 15 is represented in FIG. 16C as an equivalent RF output port 1610, and turned-on transistor grouping 1504 is represented in FIG. 16C as a resistor 1674. Turned-off transistor groupings 1502, 1510, and 1512 of FIG. 15 are represented in FIG. 16C as capacitive elements 1638, 1628, and 1630, respectively. A shunting capacitive element 1682 comprises an equivalent circuit element of the turned-off shunting transistor grouping 1508 of FIG. 15. In one exemplary embodiment, the RF signal output at the output receive node RX1 1548 has a maximum voltage of 2.5 volts peak voltage. In this embodiment, the shunting capacitive element 1682 must be able to withstand the 2.5 volts maximum peak voltage signal that is applied to output node 1610. Similarly, the shunting transistor grouping 1508 must also be able to withstand the 2.5 volts maximum peak voltage signal that is applied to the output receive node RX1 1548. Assuming again that each transistor has a 2.5 volt maximum peak voltage drop, the shunting transistor grouping 1508 therefore requires a minimum of one transistor (2.5 volts divided by a 2.5 volt drop per transistor).
FIG. 16D shows an equivalent circuit of the asymmetrically stacked transistor grouping RF switch 1500 of FIG. 15 wherein the RF output receive node RX2 1532 is coupled to the antenna 1550 via the turned-on transistor grouping 1512 (i.e., when the RF switch 1500 is configured in the “RX2” state). The RF output port RX2 1532 of FIG. 15 is represented in FIG. 16D by an equivalent RF output port 1620, and the turned-on transistor grouping 1512 is represented in FIG. 16D as a resistor 1615. Turned-off transistor groupings 1502, 1504, and 1510 of FIG. 15 are represented in FIG. 16D as capacitive elements 1638, 1608, and 1628, respectively. A shunting capacitive element 1627 comprises an equivalent circuit element of the turned-off shunting transistor grouping 1516 of FIG. 15. In one exemplary embodiment, the RF signal output at the output receive node RX2 1532 has a maximum voltage of 2.5 volts peak voltage. In this embodiment, the shunting capacitive element 1627 must be able to withstand the maximum 2.5 volts peak voltage signal that is applied to output node 1620. Similarly, the turned-off shunting transistor grouping 1516 must also be able to withstand the maximum 2.5 volts peak voltage signal that is applied to the output receive node RX2 1532. Assuming that each transistor has a 2.5 volt voltage drop, the shunting transistor grouping 1516 therefore requires a minimum of one transistor (2.5 volts divided by a 2.5 volt drop per transistor).
A novel stacked transistor grouping RF switch is provided wherein the switch is fabricated using an SOI CMOS process. Fabricating the switch on an SOI substrate results in lack of substrate bias and allows the stacked transistor grouping to be implemented. Further, using an SOI CMOS process allows the integration of key CMOS circuit building blocks in conjunction with the stacked transistor grouping RF switch elements. Integration of the CMOS building blocks with RF switch elements provides a fully integrated RF switch solution that requires use of only a single external power supply (i.e., the negative power supply voltage is generated internally by a charge pump circuit integrated with the RF switch). This results in improvements in RF switch isolation, insertion loss and compression. In one embodiment, the RF switch has a 1 dB compression point exceeding approximately 1 Watt, an insertion loss of less than approximately 0.5 dB, and switch isolation as high as approximately 40 dB. The inventive switch also provides improvements in switching times.
A number of embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, although single pole switches (e.g., the SPDT switches according to FIGS. 3, 13, and 14, and the single-pole 4-throw switch according to FIG. 15) have been described for exemplary purposes, persons skilled in the arts of electronics design will understand that switches with arbitrary numbers of poles and/or throws) may be designed, fabricated and used in accordance with the present teachings.
1. An asymmetrically stacked transistor grouping RF switch circuit for switching RF signals, comprising:
a) at least one switch-shunt circuit controlled by a switch control signal, comprising:
(1) at least one switching transistor grouping controlled by the switch control signal, wherein the at least one switching transistor grouping comprises at least one switching stacked transistor grouping; and
(2) at least one shunting transistor grouping controlled by the switch control signal, wherein the at least one shunting transistor grouping comprises at least one shunting stacked transistor grouping;
wherein the stacked transistor groupings comprise one or more FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, and wherein a number of FETs comprising at least one of the shunting transistor groupings is unequal to a number of FETs comprising at least one transistor grouping selected from the following: 1) the at least one switching transistor grouping, and 2) the at least one shunting transistor grouping.
a) a first switching transistor grouping operatively coupled to selectively convey a first RF signal between a first node and an RF common node;
b) a first shunting transistor grouping operatively coupled to selectively convey the first RF signal between the first node and a ground;
c) a second switching transistor grouping operatively coupled to selectively convey a second RF signal between a second node and the RF common node; and
d) a second shunting transistor grouping operatively coupled to selectively convey the second RF signal between the second node and the ground;
wherein the first shunting transistor grouping comprises a number of FETs that is unequal to at least one of the following: 1) a number of FETs comprising the first switching transistor grouping, 2) a number of FETs comprising the second switching transistor grouping, and 3) a number of FETs comprising the second shunting transistor grouping.
3. The RF switch of claim 2, wherein a first selected maximum voltage (RFvmax1) of the first RF signal is unequal to a second selected maximum voltage (RFvmax2) of the second RF signal, and wherein the number of FETs comprising the first shunting transistor grouping is selected such that the RVvmax1 divided by the number of FETs comprising the first shunting transistor grouping does not exceed a selected maximum FET source-to-drain voltage (SDvmax), and wherein the number of FETs comprising the second shunting transistor grouping is selected such that the RFvmax2 divided by the number of FETs comprising the second shunting transistor grouping does not exceed the SDvmax.
4. The RF switch of claim 1, wherein the RF switch comprises one of the following switch types: a single-pole, single-throw switch; a single-pole, multi-throw switch; a multi-pole, single-throw switch; and a multi-pole, multi-throw switch.
5. The RF switch of claim 1, wherein the switch circuit is fabricated using at least one of the following silicon-on-insulator (SOI) technologies: SIMOX, bonded wafers having a thin silicon layer bonded to an insulating layer, silicon-on-sapphire, and ultrathin silicon-on-sapphire.
6. A symmetrically stacked transistor grouping RF switch circuit for switching RF signals, comprising:
wherein the stacked transistor groupings comprise one or more FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, and wherein the switching and shunting stacked transistor groupings comprise an equal number of FETs, and wherein the number of FETs is determined by maximum power levels applied by the RF signals.
7. The RF switch of claim 6, further comprising:
d) a second shunting transistor grouping operatively coupled to selectively convey the second RF signal between the second node and the ground.
8. The RF switch of claim 6, wherein the RF switch comprises one of the following switch types: a single-pole, single-throw switch; a single-pole, multi-throw switch; a multi-pole, single-throw switch; and a multi-pole, multi-throw switch.
9. The RF switch of claim 6, wherein the switch circuit is fabricated using at least one of the following silicon-on-insulator (SOI) technologies: SIMOX, bonded wafers having a thin silicon layer bonded to an insulating layer, silicon-on-sapphire, and ultrathin silicon-on-sapphire.
10. The RF switch of claim 6, wherein the RF signals have a selected maximum voltage (RFvmax), and wherein the number of FETs comprising the switching and shunting stacked transistor groupings is selected such that the RFvmax divided by the number of FETs does not exceed a selected maximum FET source-to-drain voltage (SDvmax).
11. An asymmetrically stacked transistor grouping RF switch circuit for switching RF signals, comprising:
(g) a second shunt transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said second shunt transistor grouping has a first node coupled to the first input port and a second node coupled to ground, wherein the second shunt transistor grouping is controlled by the inverse (SW_) of the switch control signal (SW);
wherein, when SW is enabled, the first switch and shunt transistor groupings are enabled while the second switch and shunt transistor groupings are disabled, thereby passing the first RF input signal through to the RF common port and shunting the second RF input signal to ground, and wherein when SW is disabled, the second switch and shunt transistor groupings are enabled while the first switch and shunt transistor groupings are disabled, thereby passing the second RF input signal through to the RF common port and shunting the first RF input signal to ground, and wherein a number of FETs comprising at least one of the shunt transistor groupings is unequal to a number of FETs comprising at least one transistor grouping selected from the following: 1) the first switch transistor grouping, 2) the second switch transistor grouping; 3) the first shunt transistor grouping, and 4) the second shunt transistor grouping.
12. The asymmetrically stacked transistor grouping RF switch circuit of claim 11, wherein the switch circuit is fabricated in a silicon-on-insulator (SOI) technology.
13. The RF switch circuit of claim 11, intended for switching RF signals having an operating period 1/Fo, wherein the gate of each FET has a capacitance Cg to its channel, and the gate is coupled to a control voltage via a gate resistor Rg having a value such that Rg*Cg>1/Fo.
14. The RF switch circuit of claim 11, wherein the gate of each FET is coupled to a control voltage via a gate resistor Rg having a value of at least about 30 kΩ.
15. The RF switch circuit of claim 12, wherein the circuit is designed for switching RF signals at an operating frequency Fo, the FETs are MOSFETs, the gate of each FET has a capacitance Cg to its channel, and the gate is coupled to a control voltage via a gate resistor Rg having a value such that Rg*Cg>1/Fo.
16. The RF switch circuit of claim 15, wherein stacked MOSFETs of each transistor grouping share the signal voltage substantially equally without a need for ballast resistors parallel to a conduction path of such stacked MOSFETs, and wherein all Rg of the MOSFETs of each particular transistor grouping are commonly controlled by a corresponding switching voltage.
17. The RF switch circuit of claim 16, wherein gate resistors coupled to transistor gate nodes of the second switch and shunt transistor groupings are commonly coupled to the inverse switch control signal SW_.
18. The RF switch circuit of claim 11, wherein the FETs are MOSFETs having associated gate capacitance and an associated gate resistor coupling the gate to a drive signal, wherein RC time constants associated with each MOSFET within the transistor groupings are functions of the associated gate resistors and the associated gate capacitances, and wherein the RC time constant of each transistor far exceeds a period of the RF input signals thereby causing RF voltages to be shared equally across the MOSFETs.
19. The RF switch circuit of claim 11, wherein a breakdown voltage across the plurality of stacked MOSFET transistors of a selected transistor grouping is n times a breakdown voltage of an individual MOSFET transistor in the selected transistor grouping, wherein n comprises the total number of MOSFET transistors in the selected transistor grouping.
20. The RF switch circuit of claim 11, wherein the RF signals provided to the input ports may swing about a zero reference voltage.
21. The RF switch circuit of claim 15, wherein the first and second RF input signals have associated input power levels, and wherein increased input power levels can be accommodated by the RF switch circuit by increasing the number of MOSFET transistors per transistor grouping.
22. The RF switch circuit of claim 15, wherein the first and second RF input signals have associated input power levels, and wherein increased input power levels can be accommodated by the RF switch circuit by varying the physical size of the transistors used in implementing the transistor groupings.
23. A fully integrated RF switch circuit, comprising:
(a) the RF switch circuit as set forth in claim 11;
24. A method of switching RF signals, comprising:
(b) inputting a second RF input signal to a second switch transistor grouping and a second shunt transistor grouping, wherein both the second switch and second shunt transistor groupings comprise a plurality of stacked FETs, each of which has a gate that is insulated from its channel, wherein a number of FETs comprising at least one of the shunt transistor groupings is unequal to a number of FETs comprising at least one transistor grouping selected from the following: 1) the first switch transistor grouping, 2) the second switch transistor grouping; 3) the first shunt transistor grouping, and 4) the second shunt transistor grouping;
(c) enabling the first switch transistor grouping while disabling the first shunt transistor grouping, and simultaneously disabling the second switch transistor grouping while enabling the second shunt transistor grouping, thereby passing the first RF input signal and shunting the second RF input signal; and, at exclusively alternative times; and
25. The method of claim 24, wherein the RF signals are expected to have a minimum operating frequency Fo, and wherein each FET has a gate capacitance Cg between its gate and its channel, and is coupled to a drive signal via an associated gate resistor Rg, the method further comprising ensuring that a product of Rg times Cg is greater than 1/Fo.
26. The method of claim 25, wherein the FETs are MOSFETs, and the method further comprises fabricating the switch circuit on a fully insulating sapphire wafer.
27. The method of claim 26, wherein the method further comprises fabricating the switch circuit on an Ultra-Thin-Silicon (“UTSi”) substrate.
28. The method of claim 24, wherein each FET is coupled to a drive signal via an associated gate resistor Rg having a value of at least about 30 kΩ.
29. A symmetrically stacked transistor grouping RF switch circuit for switching RF signals, comprising:
wherein, when SW is enabled, the first switch and shunt transistor groupings are enabled while the second switch and shunt transistor groupings are disabled, thereby passing the first RF input signal through to the RF common port and shunting the second RF input signal to ground, and wherein when SW is disabled, the second switch and shunt transistor groupings are enabled while the first switch and shunt transistor groupings are disabled, thereby passing the second RF input signal through to the RF common port and shunting the first RF input signal to ground, and wherein the switch and shunt transistor groupings comprise an equal number of FETs, and wherein the number of FETs is determined by maximum power levels applied by the RF signals.
30. The RF switch circuit of claim 29, intended for switching RF signals having an operating period 1/Fo, wherein the gate of each FET has a capacitance Cg to its channel, and the gate is coupled to a control voltage via a gate resistor Rg having a value such that Rg*Cg>1/Fo.
US11347014 2001-10-10 2006-02-03 Symmetrically and asymmetrically stacked transistor group RF switch Active 2025-11-16 US7796969B2 (en)
US32835301 true 2001-10-10 2001-10-10
US10267531 US6804502B2 (en) 2001-10-10 2002-10-08 Switch circuit and method of switching radio frequency signals
US10922135 US7123898B2 (en) 2001-10-10 2004-08-18 Switch circuit and method of switching radio frequency signals
US65003305 true 2005-02-03 2005-02-03
US11347014 US7796969B2 (en) 2001-10-10 2006-02-03 Symmetrically and asymmetrically stacked transistor group RF switch
US20060194567A1 true US20060194567A1 (en) 2006-08-31
US7796969B2 true US7796969B2 (en) 2010-09-14
ID=36932524
US11347014 Active 2025-11-16 US7796969B2 (en) 2001-10-10 2006-02-03 Symmetrically and asymmetrically stacked transistor group RF switch
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