Source: http://www.google.com/patents/US7839696?dq=5,966,702
Timestamp: 2016-10-23 10:02:11
Document Index: 208351248

Matched Legal Cases: ['art 2', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093']

Patent US7839696 - Method of programming and erasing a p-channel BE-SONOS NAND flash memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state....http://www.google.com/patents/US7839696?utm_source=gb-gplus-sharePatent US7839696 - Method of programming and erasing a p-channel BE-SONOS NAND flash memoryAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7839696 B2Publication typeGrantApplication numberUS 12/365,810Publication dateNov 23, 2010Priority dateMay 5, 2006Fee statusPaidAlso published asCN101067970A, CN101067970B, US7391652, US7512016, US20070258289, US20080212375, US20090141555Publication number12365810, 365810, US 7839696 B2, US 7839696B2, US-B2-7839696, US7839696 B2, US7839696B2InventorsHang-Ting LueOriginal AssigneeMacronix International Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (93), Non-Patent Citations (36), Referenced by (3), Classifications (14), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMethod of programming and erasing a p-channel BE-SONOS NAND flash memory
US 7839696 B2Abstract
A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.
This is a continuation of U.S. patent application Ser. No. 12/121,791 filed on 16 May 2008, now allowed, which application is a divisional of U.S. patent application Ser. No. 11/381,760, filed on 5 May 2006, now U.S. Pat. No. 7,391,652. The entirety of the above-mentioned patent applications are hereby incorporated by reference herein and made a part of this specification.
In accordance with an embodiment of the present invention, there is provided a programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate, by applying a first voltage to the gate, resulting in negative Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.
The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown as follows.
Reference will now be made in detail to the invention and the presently preferred embodiments thereof, examples of which are illustrated in the accompanying drawings. Wherever possible, the same or similar references are used in the drawings and the description to refer to the same or like parts. It should be noted that the non-graph drawings are in greatly simplified form and are not to precise scale. In reference to the disclosure herein, for purposes of convenience and clarity only, directional terms, such as top, bottom, left, right, up, down, above, below, beneath, rear, and front, are used with respect to the accompanying drawings. Such directional terms used in conjunction with the following description of the drawings should not be construed to limit the scope of the invention in any manner not explicitly set forth in the appended claims. Although the disclosure herein refers to certain illustrated embodiments, it is to be understood that these embodiments are presented by way of example and not by way of limitation. It is to be understood and appreciated that the process steps and structures described herein do not cover a complete process flow for the manufacture of entire integrated circuits. The present invention may be practiced in conjunction with various integrated circuit fabrication techniques that are known in the art or to be developed.
FIG. 4A is cross-sectional view of the BE-SONOS p-channel memory cell 200 for performing a self-convergent −FN programming method of the device 200 of FIG. 2. A self-convergent programming operation is generally known in the art and will not be described further herein. However, the self-convergent −FN programming of the present invention provides greater performance and scalability, which facilitates multi-level cell (MLC) devices and applications. Applying a high −FN voltage 405 on the gate 205 (i.e., Vg=−18V), a hole inversion channel 415 is formed in a NAND string 330 of the plurality of memory cells 200 in the p-channel device 400. “Hot” holes then tunnel through the ONO tunneling dielectric layer 220 and are injected into the nitride storage layer 215 (N2). At the same time, “hot’ electrons tunnel 410 through the top oxide (O3) layer 210 from the gate 205 into N2 215. The injected holes and electrons will cancel one another until an equilibrium state is reach, thereby setting the threshold voltage of the memory cell 200. The self-convergent programming method of the present invention provides a dynamic balancing condition in the memory cell 200, obviating the need for precise voltage threshold control in programming operations.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4630086Sep 23, 1983Dec 16, 1986Hitachi, Ltd.Nonvolatile MNOS memoryUS5286994Jun 23, 1992Feb 15, 1994Rohm Co., Ltd.Semiconductor memory trap film assembly having plural laminated gate insulating filmsUS5319229Apr 27, 1992Jun 7, 1994Noriyuki ShimojiSemiconductor nonvolatile memory with wide memory window and long data retention timeUS5572464Apr 3, 1995Nov 5, 1996Nippon Steel CorporationSemiconductor memory device and method of using the sameUS5687118Nov 14, 1995Nov 11, 1997Programmable Microelectronics CorporationPMOS memory cell with hot electron injection programming and tunnelling erasingUS5877524 *Feb 5, 1996Mar 2, 1999Mitsubishi Denki Kabushiki KaishaNon-volatile semiconductor memory deviceUS5952692Oct 28, 1997Sep 14, 1999Hitachi, Ltd.Memory device with improved charge storage barrier structureUS6011725Feb 4, 1999Jan 4, 2000Saifun Semiconductors, Ltd.Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trappingUS6026026Dec 5, 1997Feb 15, 2000Hyundai Electronics America, Inc.Self-convergence of post-erase threshold voltages in a flash memory cell using transient responseUS6074917Nov 11, 1998Jun 13, 2000Advanced Micro Devices, Inc.LPCVD oxide and RTA for top oxide of ONO film to improve reliability for flash memory devicesUS6140676 *May 20, 1998Oct 31, 2000Cypress Semiconductor CorporationSemiconductor non-volatile memory device having an improved write speedUS6169693Oct 28, 1999Jan 2, 2001Hyundai Electronics America, Inc.Self-convergence of post-erase threshold voltages in a flash memory cell using transient responseUS6172397Dec 30, 1998Jan 9, 2001Mitsubishi Denki Kabushiki KaishaNon-volatile semiconductor memory deviceUS6218700Oct 28, 1998Apr 17, 2001Stmicroelectronics S.A.Remanent memory deviceUS6288943 *Jul 12, 2000Sep 11, 2001Taiwan Semiconductor Manufacturing CorporationMethod for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gateUS6469343Oct 5, 2000Oct 22, 2002Nippon Steel CorporationMulti-level type nonvolatile semiconductor memory deviceUS6512696Nov 13, 2001Jan 28, 2003Macronix International Co., Ltd.Method of programming and erasing a SNNNS type non-volatile memory cellUS6556481May 9, 2001Apr 29, 2003Aplus Flash Technology, Inc.3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cellUS6605840Feb 7, 2002Aug 12, 2003Ching-Yuan WuScalable multi-bit flash memory cell and its memory arrayUS6671209 *Oct 22, 2001Dec 30, 2003Macronix International Co., Ltd.Erasing method for p-channel NROMUS6709928Jul 31, 2001Mar 23, 2004Cypress Semiconductor CorporationSemiconductor device having silicon-rich layer and method of manufacturing such a deviceUS6720630May 30, 2001Apr 13, 2004International Business Machines CorporationStructure and method for MOSFET with metallic gate electrodeUS6740928Jan 24, 2003May 25, 2004Matsushita Electric Industrial Co., Ltd.Semiconductor deviceUS6784480Feb 12, 2002Aug 31, 2004Micron Technology, Inc.Asymmetric band-gap engineered nonvolatile memory deviceUS6801456 *Dec 17, 2003Oct 5, 2004Ememory Technology Inc.Method for programming, erasing and reading a flash memory cellUS6815764Mar 17, 2003Nov 9, 2004Samsung Electronics Co., Ltd.Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the sameUS6818558Jun 28, 2002Nov 16, 2004Cypress Semiconductor CorporationMethod of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devicesUS6858906Jun 27, 2002Feb 22, 2005Samsung Electronics Co., Ltd.Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layersUS6888753Oct 6, 2003May 3, 2005Infineon Technologies AgMemory cell array comprising individually addressable memory cells and method of making the sameUS6897533Sep 18, 2002May 24, 2005Advanced Micro Devices, Inc.Multi-bit silicon nitride charge-trapping non-volatile memory cellUS6912163Sep 9, 2003Jun 28, 2005Fasl, LlcMemory device having high work function gate and method of erasing sameUS6922363 *Dec 22, 2003Jul 26, 2005Ememory Technology Inc.Method for operating a NOR-array memory module composed of P-type memory cellsUS6952369 *Dec 22, 2003Oct 4, 2005Ememory Technology Inc.Method for operating a NAND-array memory module composed of P-type memory cellsUS6977201Dec 30, 2003Dec 20, 2005Dongbuanam Semiconductor Inc.Method for fabricating flash memory deviceUS7012299Sep 23, 2003Mar 14, 2006Matrix Semiconductors, Inc.Storage layer optimization of a nonvolatile memory deviceUS7075828Jun 24, 2004Jul 11, 2006Macronix International Co., Intl.Operation scheme with charge balancing erase for charge trapping non-volatile memoryUS7115469Jan 8, 2004Oct 3, 2006Spansion, LlcIntegrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) processUS7115942Dec 8, 2004Oct 3, 2006Chih-Hsin WangMethod and apparatus for nonvolatile memoryUS7133313Jun 24, 2004Nov 7, 2006Macronix International Co., Ltd.Operation scheme with charge balancing for charge trapping non-volatile memoryUS7133316Jun 2, 2004Nov 7, 2006Macronix International Co., Ltd.Program/erase method for P-channel charge trapping memory deviceUS7180125 *Oct 8, 2004Feb 20, 2007Chih-Hsin WangP-channel electrically alterable non-volatile memory cellUS7187590Jun 24, 2004Mar 6, 2007Macronix International Co., Ltd.Method and system for self-convergent erase in charge trapping memory cellsUS7200040 *Sep 8, 2005Apr 3, 2007Powerchip Semiconductor Corp.Method of operating p-channel memoryUS7391652 *May 5, 2006Jun 24, 2008Macronix International Co., Ltd.Method of programming and erasing a p-channel BE-SONOS NAND flash memoryUS7442988Nov 28, 2006Oct 28, 2008Samsung Electronics Co., Ltd.Semiconductor devices and methods of fabricating the sameUS7473589Oct 13, 2006Jan 6, 2009Macronix International Co., Ltd.Stacked thin film transistor, non-volatile memory devices and methods for fabricating the sameUS7551494 *May 22, 2008Jun 23, 2009Ememory Technology Inc.Single-poly non-volatile memory device and its operation methodUS7646056Mar 15, 2006Jan 12, 2010Samsung Electronics Co., Ltd.Gate structures of a non-volatile memory device and methods of manufacturing the sameUS20030030100Jul 2, 2002Feb 13, 2003Samsung Electronics Co., Ltd.Non-volatile memory device and method for fabricating the sameUS20030032242Jul 12, 2002Feb 13, 2003Samsung Electronics Co., Ltd.Method of forming non-volatile memory having floating trap type deviceUS20030042534Aug 30, 2001Mar 6, 2003Micron Technology, Inc.Scalable flash/NV structures and devices with extended enduranceUS20030224564Jun 4, 2002Dec 4, 2003Samsung Electronics Co., LtdNon-volatile memory cell having a silicon-oxide nitride-oxide-silicon gate structure and fabrication method of such cellUS20040079983Oct 14, 2003Apr 29, 2004Chae Soo-DooNonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon memoryUS20040251489Jun 10, 2004Dec 16, 2004Sang-Hun JeonSONOS memory device and method of manufacturing the sameUS20040256679Jun 17, 2003Dec 23, 2004Hu Yongjun J.Dual work function metal gates and method of formingUS20050006696May 21, 2004Jan 13, 2005Kabushiki Kaisha ToshibaSemiconductor memoryUS20050023603Aug 30, 2004Feb 3, 2005Micron Technology, Inc.Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulatorsUS20050062098Sep 23, 2003Mar 24, 2005Matrix Semiconductor, Inc.Storage layer optimization of a nonvolatile memory deviceUS20050093054Nov 4, 2004May 5, 2005Jung Jin H.Non-volatile memory devices and methods of fabricating the sameUS20050219906May 20, 2005Oct 6, 2005Macronix International Co., Ltd.Operation scheme for programming charge trapping non-volatile memoryUS20050237801Jun 24, 2004Oct 27, 2005Macronix International Co., Ltd.Operation scheme with charge balancing for charge trapping non-volatile memoryUS20050237809Jun 24, 2004Oct 27, 2005Macronix International Co., Ltd.Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memoryUS20050237813Jun 24, 2004Oct 27, 2005Macronix International Co., Ltd.Method and system for self-convergent erase in charge trapping memory cellsUS20050237815Jun 24, 2004Oct 27, 2005Macronix International Co., Ltd.Operation scheme with charge balancing erase for charge trapping non-volatile memoryUS20050237816Jun 24, 2004Oct 27, 2005Macronix International Co., Ltd.Operation scheme for spectrum shift in charge trapping non-volatile memoryUS20050270849Jun 2, 2004Dec 8, 2005Macronix International Co. Ltd.Program/erase method for p-channel charge trapping memory deviceUS20050281085May 20, 2005Dec 22, 2005Macronix International Co., Ltd.Operation scheme for programming charge trapping non-volatile memoryUS20060118858Oct 11, 2005Jun 8, 2006Samsung Electronics Co., Ltd.Non-volatile semiconductor memory device with alternative metal gate materialUS20060158930Jan 18, 2005Jul 20, 2006Mammen ThomasCACT-TG (CATT) low voltage NVM cellsUS20060198189Jan 3, 2006Sep 7, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysUS20060198190Jan 3, 2006Sep 7, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysUS20060202252Jan 3, 2006Sep 14, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysUS20060202261Jan 3, 2006Sep 14, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysUS20060258090May 12, 2005Nov 16, 2006Micron Technology, Inc.Band-engineered multi-gated non-volatile memory device with enhanced attributesUS20060261401May 17, 2005Nov 23, 2006Micron Technology, Inc.Novel low power non-volatile memory and gate stackUS20060281260May 4, 2006Dec 14, 2006Hang-Ting LueMethods of operating p-channel non-volatile memory devicesUS20070012988Jul 14, 2005Jan 18, 2007Micron Technology, Inc.High density NAND non-volatile memory deviceUS20070029625Aug 4, 2005Feb 8, 2007Macronix International Co., Ltd.Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layerUS20070031999Aug 4, 2005Feb 8, 2007Macronix International Co. Ltd.Non-volatile memory cells and methods of manufacturing the sameUS20070045718Aug 31, 2005Mar 1, 2007Micron Technology, Inc.Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injectionUS20070069283Sep 27, 2005Mar 29, 2007Macronix International Co., Ltd.Method of forming bottom oxide for nitride flash memoryUS20070109872Apr 28, 2006May 17, 2007Chrong-Jung LinSingle-poly non-volatile memory device and its operation methodUS20070138539Dec 15, 2005Jun 21, 2007Macronix International Co., Ltd.Non-volatile memory device having a nitride-oxide dielectric layerUS20070181937Feb 9, 2006Aug 9, 2007Yen-Tai LinP-channel non-volatile memory and operating method thereofUS20080080248Oct 3, 2006Apr 3, 2008Macronix International Co., Ltd.Cell operation methods using gate-injection for floating gate nand flash memoryUS20090039417Feb 17, 2005Feb 12, 2009National University Of SingaporeNonvolatile Flash Memory Device and Method for Producing Dielectric Oxide Nanodots on Silicon DioxideUSRE31083Dec 5, 1980Nov 16, 1982International Business Machines CorporationNon-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structureEP0016246A1Oct 3, 1979Oct 1, 1980International Business Machines CorporationSemiconductor field effect structure of the Metal-Insulator-Metal or Metal-Insulator-Semiconductor type, and memory device comprising such structureEP1411555A2Apr 14, 2003Apr 21, 2004Samsung Electronics Co., Ltd.Nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon memoryEP1677311A1Jan 3, 2006Jul 5, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysEP1677312A1Jan 3, 2006Jul 5, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysJP2004363329A Title not availableJPH1140682A Title not available* Cited by examinerNon-Patent CitationsReference1Aminzadeh et al., "Conduction and Charge Trapping in Polysilicon-Silicon Nitride-Oxide-Silicon Structures under Positive Gate Bias," IEEE Trans. on Electron Dev. 35(4) Apr. 1998 459-467.2Baik, Seung, et al., "High Speed and Nonvolatile Si Nanocrystal Memory for Scaled Flash Technology using Highly Field-Sensitive Tunnel Barrier," IEEE IEDM 03-545 22.3.1-22.3.4, 2003.3Blomme et al., "Multilayer tunneling barriers for nonvolatile memory applications," Device Research Conf, 2002 60th DRC Digest 153-154.4Blomme et al., "Write/Erase Cycling Endurance of Memory Cells with SiO2/HfO2 Tunnel Dielectric," IEEE Trans. on Dev. and Materials Reliability 4(3), Sep. 2004 345-351.5Buckley, J., et al., "Engineering of 'Conduction Band-Crested Barriers' or 'Dielectric Constant-Crested Barriers' in view of their application of floating-gate non-volatile memory devices," VLSI 2004, 55-56.6Buckley, J., et al., "Engineering of ‘Conduction Band-Crested Barriers’ or ‘Dielectric Constant-Crested Barriers’ in view of their application of floating-gate non-volatile memory devices," VLSI 2004, 55-56.7Chindalore, et al., "A New Combination-Erase Technique for Erasing Nitride Based (SONOS) Nonvolatile Memories," IEEE Electron Dev. Lett. 24(4) Apr. 2003, 257-259.8Cho, et al., "Simultaneous Hot-Hole Injection at Drain and Source for Efficient Erase and Excellent Endurance in SONOS Flash EEPROM Cells," IEEE Electron Device Letters, vol. 24, No. 4, Apr. 2003, 260-262.9DiMaria, D.J., et al., "Conduction Studies in Silicon Nitride: Dark Currents and Photocurrents," IBM J. Res. Dev. May 1977, 227-244.10Eitan, et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Lett 21(11) Nov. 2000, 543-545.11Govoreanu et al., "An Investigation of the Electron Tunneling Leakage Current Through Ultrathin Oxides/High-k Gate Stacks at Inversion Conditions," IEEE SISPAD Intl. Conf. Sep. 3-5, 2003 287-290.12Govoreanu et al., "Simulation of Nanofloating Gate Memory with High-k Stacked Dielectrics," IEEE SISPAD Intl. Conf. Sep. 3-5, 2003 299-302.13Govoreanu et al., "VARIOT: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices," IEEE Electron Dev. Lett. 24(2) Feb. 2003 94-10.14Hijiya, S., et al., "High-Speed Write/Erase EAROM Cell with Graded Energy Band-Gap Insulator," Electronics and Communications in Japan, Part 2, vol. 68, No. 2, Jun. 6, 1984, 28-36.15Hinkle, C.L., et al., "Enhanced tunneling in stacked gate dielectrics with ultra-thin HfO2 (ZrO2) layers sandwiched between thicker SiO2 layers," Surface Science, Sep. 20, 2004, vol. 566-568, 1185-1189.16Ito, et al., "A Novel MNOS Technology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory Applications." 2004 Symp. on VLSI Tech Dig. of Papers 2004, 80-81.17Kim et al., "Robust Multi-Bit Programmable Flash Memory Using a Resonant Tunnel Barrier," Electron Dev. Mtg. Dec. 5-7, 2005, IEDM Technical Digest 861-864.18Lee, Chang, et al., "A Novel SONOS Structure of SiO2/Si2827I203 with TaN Metal Gate for Multi-Giga Bit Flash Memories," IEEE 2003 4 pages.19Lee, Chungho, et al., "Operational and Reliability Comparison of Discrete-Storage Nonvolatile Memories: Advantages of Single-and Double-Layer Metal Nanocrystals," IEEE IEDM 03-557 22.6.1-22.6.4, 2003.20Likharev, "Layered Tunnel Barriers for Nonvolatile Memory Devices,"Appl. Phys. Lett. 73(15) Oct. 1998 2137-2139.21Lue et al., "A Novel P-Channel NAND-Type Flash memory 2-bit/cell Operation and High Programming Throughput (>20 MB/sec)," IEEE 2005, 4 pages.22Lue et al., "BE-SONOS: A Bangap Engineered SONOS with Excellent Performance and Retention Time," IEDM Tech. Digest Dec. 2005 547-550.23Minami, et al., "New Scaling Guidelines for MNOS Nonvolatile Memory Devices," IEEE Trans on Electron Devices 38(11) Nov. 1991 2519-2526.24Search Report mailed Feb. 14, 2007 in European Application No. 06000064.3 filed on Jan. 3, 2006, 7 pages.25Search Report mailed Feb. 14, 2007 in European Application No. 06000093.2 (Pub. No. EP-01677312) filed on Jan. 3, 2006, 7 pages.26Search Report mailed May 9, 2008 in European Application No. 06000064.3 filed on Jan. 3, 2006, 3 pages.27Search Report mailed May 9, 2008 in European Application No. 06000093.2 (Pub. No. EP-01677312) filed on Jan. 3, 2006, 4 pages.28Search Report mailed Nov. 14, 2007 in European Application No. 06000064.3 (Pub. No. EP-01677312) filed on Jan. 3, 2006, 4 pages.29Search Report mailed Nov. 14, 2007 in European Application No. 06000093.2 (Pub. No. EP-01677312) filed on Jan. 3, 2006, 4 pages.30Shih et al., "A Novel 2-bit/cell Nitride Storage Flash Memory with Greater than 1M P/E-cycle Endurance," IEEE IEDM 2004 881-884 (36.3.1-36.3.4).31Sung et al., "Multi-Layer SONOS with Direct Tunnel Oxide for High Speed and Long Retention Time," IEEE Silicon Nanoelectronics Workshop Jun. 2002 83-84.32Takata, M., et al., "New Non-Volatile Memory with Extremely High Density Metal Nano-Dots," IEEE IEDM 03-553, 22.5.1-22.5.4, 2003.33Walker et al., "3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications," 2003 Symposium on VLSI Tech Digest of Technical Papers, 29-30.34White et al., "On the Go with SONOS" IEEE Circuits and Devicces, Jul. 2000, 22-31.35Yamada et al., "A self-convergence erasing scheme for a simple stacked gate flash EEPROM," Proc. Int'l. Electron Devices Meeting, Dec. 1991 307-310.36Yeh, C.C., et al., "PHINES: A Novel Low Power Program/Erase, Small Pitch 2-Bit per Cell Flash Memory," IEDM Tech. Dig. 2002, 931-934.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8995195 *Feb 12, 2013Mar 31, 2015Sandisk Technologies Inc.Fast-reading NAND flash memoryUS9111627Feb 25, 2015Aug 18, 2015Sandisk Technologies Inc.Fast-reading NAND flash memoryUS20140226402 *Feb 12, 2013Aug 14, 2014Sandisk Technologies Inc.Fast-Reading NAND Flash Memory* Cited by examinerClassifications U.S. Classification365/185.28, 365/185.17, 365/185.18International ClassificationG11C16/04Cooperative ClassificationG11C16/0466, G11C16/0483, G11C16/3418, G11C16/12, G11C16/3427European ClassificationG11C16/04N, G11C16/34D, G11C16/04M, G11C16/12, G11C16/34D4Legal EventsDateCodeEventDescriptionApr 6, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services