Source: http://www.google.com/patents/US7254283?dq=5,890,152
Timestamp: 2015-05-03 10:06:29
Document Index: 151588074

Matched Legal Cases: ['art 101', 'art 101', 'art 101', 'art 101', 'art 101', 'art 101', 'art 101', 'art 205']

Patent US7254283 - Image processor processing image data in parallel with a plurality of processors - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsIn order to efficiently process image data in a circuit dividing single image data into a plurality of data and processing the data with a plurality of MPUs in parallel with each other, the MPUs process image data input through an input image data in parallel with each other. An address bus inputs addresses...http://www.google.com/patents/US7254283?utm_source=gb-gplus-sharePatent US7254283 - Image processor processing image data in parallel with a plurality of processorsAdvanced Patent SearchPublication numberUS7254283 B1Publication typeGrantApplication numberUS 09/438,247Publication dateAug 7, 2007Filing dateNov 12, 1999Priority dateNov 13, 1998Fee statusPaidPublication number09438247, 438247, US 7254283 B1, US 7254283B1, US-B1-7254283, US7254283 B1, US7254283B1InventorsJunji Nishigaki, Atsushi Ishikawa, Kenichi Sawada, Kazuhiro Ishiguro, Hiroyuki SuzukiOriginal AssigneeMinolta Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (41), Referenced by (5), Classifications (12), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetImage processor processing image data in parallel with a plurality of processors
US 7254283 B1Abstract
FIG. 2 illustrates a specific example of the status register 103. The status register 103 stores the states of the MPU1 to MPU4. Each MPU has five states, i.e., �standby�, �input�, �processing�, �end of processing� and �output� states.
The MPU performs no processing in the �standby� state, and receives image data from the input image bus in the �input� state. The MPU processes the input image data in the �processing� state, and terminates processing the image data in the �end of processing� state. The MPU outputs the image data through the output image bus in the �output� state.
The status register 103 indicates the current state of each MPU with FIG. 3 is a flowchart showing processing of the data flow control part 101. Referring to FIG. 3, the data flow control part 101 confirms the contents (see FIG. 2) of the status register 103 at a step S101. The data flow control part 101 determines whether or not any MPU is in the �standby� state at a step S103. If the determination is of YES, the data flow control part 101 instructs the MPU to receive and process image data at a step S105. The data flow control part 101 determines whether or not processing of all image data is terminated at a step S107, and ends this routine if the determination is of YES.
FIG. 4 is a flowchart showing processing of one of the MPU1 to MPU4. Referring to FIG. 4, the MPU enters the �standby� state at a step S201. This state is recorded in the status register 103.
A determination is made at a step S203 as to whether or not an instruction is received from the data flow control part 101, and the processing from the step S201 is repeated until the determination is of YES. If the determination at the step S203 is of YES, the state of the MPU in the status register 103 is changed at a step S205. More specifically, �0� is written in the column of �standby� and �1� is written in the column of �input�.
At a step S211, �0� is set in the column of �input� in the status register 103 while �1� is set in the column of �processing�. The input image is processed at a step S213. If the processing is terminated, �0� is set in the column of �processing� and �1� is set in the column of �end of processing� in the status register 103 at a step S215.
The MPU enters a standby state at a step S217, to wait for an output instruction from the data flow control part 101 at a step S219. When receiving the output instruction, �0� is set in the column of �end of processing� and �1� is set in the column of �output� in the status register 103 at a step S221. At a step S223, the image data processed by the MPU is output through the output image bus, along with the address data stored by the corresponding one of the memories M1 to M4 through the address bus. At a step S225, �0� is set in the column of �output� and �1� is set in the column of �standby� in the status register 103. Thereafter the process returns to the step S201.
FIG. 7 is a block diagram showing the structure around the selector 227 in detail. Referring to FIG. 7, the selector 227 includes a MIN value detection circuit 229 and transfer gates 231 a to 231 d. FIG. 8 is a flowchart showing operations of the selector 227. Referring to FIG. 8, the selector 227 activates a read signal RE of each of the FIFO memories 215 a to 215 d and 217 a to 217 d for one pixel in response to an output start instruction from the data flow control part 205 at a step S301. The selector 227 stores read data in each of the buffer memories 219 to 225. The MIN value detection circuit 229 detects the minimum one from address data stored in the buffer memories 219 to 225 and outputs a common read signal to the FIFO memory, the buffer memory and the transfer gate corresponding to the minimum address data. Thus, image data corresponding to the minimum address data is selected as output data, and data from the FIFO memories 215 a to 215 d and 217 a to 217 d are newly stored in the buffer memories 219 to 225. This operation is performed in synchronization with an output clock. Thus, image data stored in the FIFO memories 215 a to 215 d and 217 a to 217 d at random are sequentially sorted by an output unit and output along the sequence of the addresses.
Referring to FIG. 21, �counter� indicates a counter counting a data output number. �Address T� indicates addresses of the address memory 405 and the output buffer memory 403. �Data ADR� indicates data stored in the address memory 405. �Data Dout� indicates data stored in the output buffer memory 403.
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