Source: http://www.google.com/patents/US6134699?dq=6,034,652
Timestamp: 2017-09-22 22:03:05
Document Index: 420973944

Matched Legal Cases: ['application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 08']

Patent US6134699 - Method and apparatus for detecting virtual address parity error for a ... - Google Patents
A method and apparatus are provided for detecting virtual address parity error for a translation lookaside buffer in a computer system. The computer system includes a processor unit, a cache coupled to the processor unit, a main memory, and a storage control unit including a translation lookaside buffer...http://www.google.com/patents/US6134699?utm_source=gb-gplus-sharePatent US6134699 - Method and apparatus for detecting virtual address parity error for a translation lookaside buffer
Publication number US6134699 A
Application number US 09/016,244
Publication number 016244, 09016244, US 6134699 A, US 6134699A, US-A-6134699, US6134699 A, US6134699A
Inventors James Anthony Steenburgh, Sandra S. Woodward
Patent Citations (20), Non-Patent Citations (13), Referenced by (8), Classifications (7), Legal Events (5)
Method and apparatus for detecting virtual address parity error for a translation lookaside buffer
US 6134699 A
1. Apparatus for detecting virtual address parity error for a translation lookaside buffer in a computer system, said apparatus comprising:
means for generating a virtual address parity (VAP) for each entry written in a segment lookaside buffer (SLB);
means for generating a virtual address parity (VAP) for each virtual address entry written in the translation lookaside buffer (TLB);
means utilizing said SLB virtual address parity (VAP) and said TLB virtual address parity (VAP) for identifying a translation miss condition; and
means utilizing said SLB virtual address parity (VAP) and predetermined effective address bits for generating a virtual address parity predict (VAPP).
2. Apparatus for detecting virtual address parity error for a translation lookaside buffer in a computer system as recited in claim 1 wherein said means utilizing said SLB virtual address parity (VAP) and said TLB virtual address parity (VAP) for identifying said translation miss condition include means for comparing said virtual address parity predict (VAPP) and said TLB virtual address parity (VAP).
7. A computer implemented method for detecting virtual address parity error for a translation lookaside buffer in a computer system, said method comprising the steps of:
generating a virtual address parity (VAP) for each entry written in a segment lookaside buffer (SLB);
generating a virtual address parity (VAP) for each virtual address entry written in the translation lookaside buffer (TLB);
utilizing said SLB virtual address parity (VAP) and said TLB virtual address parity (VAP) for identifying a translation miss condition;
generating a virtual address parity predict (VAPP) utilizing said SLB virtual address parity (VAP) and predetermined effective address bits;
comparing said VAPP and said TLB virtual address parity (VAP); and
detecting said translation miss condition responsive to said VAPP and said TLB virtual address parity (VAP) not matching.
8. A computer implemented method for detecting virtual address parity error for a translation lookaside buffer as recited in claim 7 includes the steps responsive to identifying said translation miss condition for performing a search of page table entries; identifying a least recently used (LRU) TLB entry and writing a new TLB entry replacing said LRU TLB entry.
9. A computer implemented method for detecting virtual address parity error for a translation lookaside buffer as recited in claim 7 wherein said step of utilizing said SLB virtual address parity (VAP) and said TLB virtual address parity (VAP) for identifying said translation miss condition includes the steps of
comparing virtual address entries from said TLB and said SLB;
detecting said translation miss condition responsive to said compared virtual address entries not matching.
a storage control unit including a translation lookaside buffer (TLB) and a segment lookaside buffer (SLB);
11. A computer system as recited in claim 10, includes means for comparing said virtual address parity predict (VAPP) and said TLB virtual address parity (VAP) for identifying said translation miss condition.
JPH08147779A * Title not available
1 * U.S. application No. 08/473,692, filed Jun. 7, 1995, entitled Method and System for High Performance Multithread Operation in a Data Processing System, by R.J. Eickemeyer et al.
2 * U.S. application No. 08/675,315, filed Jul. 3, 1996, entitled Multi Threaded Cell for a Memory, by A.G. Aipperspach et al.
3 U.S. application No. 08/675,315, filed Jul. 3, 1996, entitled Multi-Threaded Cell for a Memory, by A.G. Aipperspach et al.
4 * U.S. application No. 08/761,378, filed Dec. 9, 1996, entitled Multi Entry Fully Associative Transition Cache, by D.L. Freerksen et al.
5 U.S. application No. 08/761,378, filed Dec. 9, 1996, entitled Multi-Entry Fully Associative Transition Cache, by D.L. Freerksen et al.
6 * U.S. application No. 08/761,379, filed Dec. 9, 1996, entitled Method and Apparatus for Tracking Processing of a Command, by D.L. Freerksen et al.
7 * U.S. application No. 08/761,380, filed Dec. 9, 1996, entitled Method and Apparatus for Prioritizing and Routing Commands from a Command Source to a Command Sink, by D.L. Freerksen et al.
8 * U.S. application No. 08/773,572, filed Dec. 27, 1996, entitled Background Completion of Instruction and Associated Fetch Request in a Multithreaded Processor, by J.M. Borkenhagen et al.
9 * U.S. application No. 08/956,577, filed Oct. 23, 1997, entitled Method and Apparatus to Force a Thread Switch in a Multithreaded Processor, by J.M. Borkenhagen et al.
10 * U.S. application No. 08/956,875, filed Oct. 23, 1997, entitled an Apparatus and Method to Guarantee Forward Progress in a Multithreaded Processor, by J.M. Borkenhagen et al.
11 * U.S. application No. 08/957,002, filed Oct. 23, 1997, entitled Thread Switch Control in a Multithreaded Processor System, by J.M. Borkenhagen et al.
12 * U.S. application No. 08/958,716, filed Oct. 23, 1997, entitled Method and Apparatus for Selecting Thread Switch Events in a Multithreaded Processor, by J.M. Borkenhagen et al.
13 * U.S. application No. 08/958,718, filed Oct. 23, 1997, entitled Altering Thread Priorities in a Multithreaded Processor, by J.M. Borkenhagen et al.
WO2009024886A2 * Aug 8, 2008 Feb 26, 2009 Nxp B.V. System and method for error protection of a memory
WO2009024886A3 * Aug 8, 2008 Apr 30, 2009 Nxp Bv System and method for error protection of a memory
U.S. Classification 714/803, 714/E11.037, 714/53, 714/758
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:STEENBURGH, JAMES ANTHONY;WOODWARD, SANDRA S.;REEL/FRAME:008978/0963;SIGNING DATES FROM 19980119 TO 19980127