Source: http://www.google.com/patents/US6133058?dq=7125605
Timestamp: 2017-03-27 22:48:56
Document Index: 400697483

Matched Legal Cases: ['Application No. 8', 'Application No. 8', 'Application No. 8', 'Application No. 8', 'art 2', 'art 2']

Patent US6133058 - Fabrication of semiconductor light-emitting device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor light-emitting device with a double hetero structure, including: an active layer made of Ga1-x Inx N (0≦x≦0.3) doped with a p-type impurity and an n-type impurity; and first and second cladding layers provided so as to sandwich the active layer....http://www.google.com/patents/US6133058?utm_source=gb-gplus-sharePatent US6133058 - Fabrication of semiconductor light-emitting deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6133058 APublication typeGrantApplication numberUS 09/243,648Publication dateOct 17, 2000Filing dateFeb 3, 1999Priority dateJul 21, 1994Fee statusPaidAlso published asDE69533511D1, DE69533511T2, EP0772247A1, EP0772247A4, EP0772247B1, EP1473781A2, EP1473781A3, US5751013, US5895225, WO1996003776A1Publication number09243648, 243648, US 6133058 A, US 6133058A, US-A-6133058, US6133058 A, US6133058AInventorsIsao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Kiyoshi Ohnaka, Yuzaburo Ban, Minoru KuboOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (38), Non-Patent Citations (9), Referenced by (26), Classifications (52), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetFabrication of semiconductor light-emitting device
US 6133058 AAbstract
1. A method for producing a semiconductor light-emitting device, comprising the steps of:forming a semiconductor structure, on a substrate, including an active layer and first and second cladding layers sandwiching the active layer; removing portions of the active layer and the first and second cladding layers to form a projected portion and a concave portion in the semiconductor structure; forming first and second electrodes on the concave portion and the projected portion of the semiconductor structure, respectively; and providing the semiconductor structure on a heat sink having a first portion and a second portion in such a manner that the second electrode comes into contact with the second portion of the heat sink after the first electrode comes into contact with the first portion of the heat sink. 2. A method for producing a semiconductor light-emitting device according to claim 1, wherein the first and second portions of the heat sink are respectively disposed on the heat sink at such positions that when facing the first and second portions to the first and second electrodes, a distance between the first portion and the first electrode is shorter than a distance between the second portion and the second electrode.
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Ltd.Gallium nitride device substrate containing a lattice parameter altering elementUS7314672Oct 6, 2004Jan 1, 2008Nec CorporationSemiconductor layer formed by selective deposition and method for depositing semiconductor layerUS7526007 *Dec 15, 2005Apr 28, 2009Palo Alto Research Center IncorporatedBuried lateral index guided lasers and lasers with lateral current blocking layersUS7655485Nov 9, 2007Feb 2, 2010Nec CorporationSemiconductor layer formed by selective deposition and method for depositing semiconductor layerUS7764721Dec 15, 2005Jul 27, 2010Palo Alto Research Center IncorporatedSystem for adjusting the wavelength light output of a semiconductor device using hydrogenationUS7843982Dec 15, 2005Nov 30, 2010Palo Alto Research Center IncorporatedHigh power semiconductor device to output light with low-absorbtive facet windowUS8039869Aug 14, 2007Oct 18, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Gallium nitride device substrate containing a lattice parameter altering elementUS8486771Sep 21, 2009Jul 16, 2013SoitecMethods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including sameUS8637383Dec 23, 2010Jan 28, 2014SoitecStrain relaxation using metal materials and related structuresUS8836081Aug 22, 2012Sep 16, 2014SoitecSemiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strainUS9312339Jan 27, 2014Apr 12, 2016SoitecStrain relaxation using metal materials and related structuresUS9324912May 16, 2012Apr 26, 2016Toyoda Gosei Co., Ltd.Group III nitride semiconductor light-emitting element and method for producing sameUS9368344Jun 30, 2014Jun 14, 2016SoitecSemiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strainUS20040046166 *Apr 23, 2003Mar 11, 2004Samsung Electronics Co., Ltd.High-efficiency light emitting diodeUS20050056853 *Oct 6, 2004Mar 17, 2005Nec CorporationSemiconductor layer formed by selective deposition and method for depositing semiconductor layerUS20070032041 *Aug 1, 2005Feb 8, 2007Lester Steven DGallium nitride device substrate containing a lattice parameter altering elementUS20070153851 *Dec 15, 2005Jul 5, 2007Palo Alto Research Center IncorporatedOn-chip integration of passive and active optical components enabled by hydrogenationUS20070153852 *Dec 15, 2005Jul 5, 2007Palo Alto Research Center IncorporatedSystem for adjusting the wavelength light output of a semiconductor device using hydrogenationUS20070153853 *Dec 15, 2005Jul 5, 2007Palo Alto Research Center IncorporatedBuried lateral index guided lasers and lasers with lateral current blocking layersUS20070153857 *Dec 15, 2005Jul 5, 2007Palo Alto Research Center IncorporatedHigh power semiconductor device to output light with low-absorbtive facet windowUS20070278622 *Aug 14, 2007Dec 6, 2007Lester Steven DGallium Nitride Device Substrate Contaning A Lattice Parameter Altering ElementUS20080070336 *Nov 9, 2007Mar 20, 2008Nec CorporationSemiconductor layer formed by selective deposition and method for depositing semiconductor layerUS20100176490 *Sep 21, 2009Jul 15, 2010Fabrice LetertreMethods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including sameCN1909190BAug 1, 2006Mar 21, 2012台湾积体电路制造股份有限公司Gallium nitride device substrate containing a lattice parameter altering element* Cited by examinerClassifications U.S. Classification438/47International ClassificationH01S5/02, H01L33/06, H01L33/36, H01S5/223, H01S5/323, H01S5/16, H01S5/20, H01S5/327, H01L33/32, H01S5/024, H01S5/042, H01S5/30, H01S5/022, H01L33/00, H01L33/02, H01L33/64Cooperative ClassificationH01L33/325, H01S5/2063, H01S5/2059, H01L33/32, H01S5/0213, H01S5/3063, H01S5/02236, H01L33/007, H01L33/642, H01S5/305, H01S5/2231, H01S5/3086, H01S5/0224, H01S5/162, H01S5/0422, H01S5/02272, H01S5/32341, H01L2933/0075, H01S5/327, H01L33/025, H01L2224/83192, H01L24/81, H01L24/16, H01L2224/73204, H01L24/17, H01L24/14European ClassificationH01L33/64C, H01S5/327, H01S5/223B, H01S5/323B4, H01S5/30P, H01L33/00G3B2, H01L33/32C, H01L33/02C, H01L33/32Legal EventsDateCodeEventDescriptionMar 10, 2004FPAYFee paymentYear of fee payment: 4Apr 4, 2008FPAYFee paymentYear of fee payment: 8Mar 20, 2012FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services