Source: http://www.google.com/patents/US7902677?ie=ISO-8859-1
Timestamp: 2015-04-19 04:38:38
Document Index: 530900180

Matched Legal Cases: ['art 2', 'art 141', 'art 141', 'art 141', 'art 141', 'art 141', 'art 141', 'art 2', 'art 2']

Patent US7902677 - Composite layered chip package and method of manufacturing same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA composite layered chip package includes a plurality of subpackages stacked. Each subpackage includes a main body, and wiring disposed on a side surface of the main body. The main body has a main part that includes at least one first-type layer portion. For any two vertically adjacent subpackages, the...http://www.google.com/patents/US7902677?utm_source=gb-gplus-sharePatent US7902677 - Composite layered chip package and method of manufacturing sameAdvanced Patent SearchPublication numberUS7902677 B1Publication typeGrantApplication numberUS 12/588,808Publication dateMar 8, 2011Filing dateOct 28, 2009Priority dateOct 28, 2009Fee statusPaidPublication number12588808, 588808, US 7902677 B1, US 7902677B1, US-B1-7902677, US7902677 B1, US7902677B1InventorsYoshitaka Sasaki, Hiroyuki Ito, Hiroshi Ikejima, Atsushi IijimaOriginal AssigneeHeadway Technologies, Inc., Sae Magnetics (H.K.) Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (15), Non-Patent Citations (1), Referenced by (12), Classifications (51), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetComposite layered chip package and method of manufacturing same
US 7902677 B1Abstract
A composite layered chip package includes a plurality of subpackages stacked. Each subpackage includes a main body, and wiring disposed on a side surface of the main body. The main body has a main part that includes at least one first-type layer portion. For any two vertically adjacent subpackages, the main body of the lower subpackage has a plurality of first terminals that are arranged on the top surface of the main part, while the main body of the upper subpackage has a plurality of second terminals that are arranged on the bottom surface of the main part. The main part of the main body of at least one of the plurality of subpackages includes at least one second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, while the second-type layer portion includes a defective semiconductor chip.
1. A composite layered chip package comprising a plurality of subpackages stacked, every two vertically adjacent subpackages being electrically connected to each other, wherein:
each of the plurality of subpackages includes: a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body;
the main body has a main part, the main part including at least one first-type layer portion and having a top surface and a bottom surface;
for any two vertically adjacent subpackages, the main body of a lower subpackage further has a plurality of first terminals that are arranged on the top surface of the main part and electrically connected to the wiring, while the main body of an upper subpackage further has a plurality of second terminals that are arranged on the bottom surface of the main part and electrically connected to the wiring, and the plurality of second terminals of the main body of the upper subpackage are electrically connected to the plurality of first terminals of the main body of the lower subpackage;
the main part of the main body of at least one of the plurality of subpackages further includes at least one second-type layer portion;
each of the first-type layer portion and the second-type layer portion includes a semiconductor chip; and
the first-type layer portion further includes a plurality of electrodes, each of the electrodes being electrically connected to the semiconductor chip and having an end face located at the at least one of the side surfaces of the main body on which the wiring is disposed, whereas the second-type layer portion does not include the plurality of electrodes, and the wiring is electrically connected to the end faces of the plurality of electrodes.
2. The composite layered chip package according to claim 1, wherein the semiconductor chip of the first-type layer portion is a normally functioning one whereas the semiconductor chip of the second-type layer portion is a malfunctioning one.
3. The composite layered chip package according to claim 1, wherein the main body of a lowermost one of the plurality of subpackages further has the plurality of second terminals.
4. The composite layered chip package according to claim 1, wherein the main body of an uppermost one of the plurality of subpackages further has the plurality of first terminals.
5. The composite layered chip package according to claim 1, wherein the respective main bodies of all of the plurality of subpackages each have the plurality of first terminals and the plurality of second terminals.
6. The composite layered chip package according to claim 1, wherein:
each of the first-type layer portion and the second-type layer portion further includes an insulating portion that covers at least one of the four side surfaces of the semiconductor chip; and
7. A manufacturing method for the composite layered chip package according to claim 1, the method comprising the steps of
fabricating the plurality of subpackages; and
stacking the plurality of subpackages and, for any two vertically adjacent subpackages, electrically connecting the plurality of second terminals of the upper subpackage to the plurality of first terminals of the lower subpackage.
8. The manufacturing method according to claim 7, wherein the semiconductor chip of the first-type layer portion is a normally functioning one whereas the semiconductor chip of the second-type layer portion is a malfunctioning one.
wherein the step of fabricating the plurality of subpackages includes, as a series of steps for forming each subpackage,
the step of fabricating at least one substructure that includes a plurality of preliminary layer portions arrayed, each of the preliminary layer portions being intended to be made into any one of the layer portions included in the main part, the substructure being intended to be cut later at a position of a boundary between every adjacent preliminary layer portions; and
the step of fabricating the subpackage by using the at least one substructure,
and wherein the step of fabricating the at least one substructure includes the steps of:
fabricating a pre-substructure wafer including a plurality of pre-semiconductor-chip portions that are arrayed and intended to be made into the individual semiconductor chips;
forming the plurality of electrodes in the normally functioning pre-semiconductor-chip portions while not forming the plurality of electrodes in the malfunctioning pre-semiconductor-chip portions, so as to make the pre-substructure wafer into the substructure.
10. The manufacturing method according to claim 9, wherein the step of forming the plurality of electrodes includes the steps of:
forming a photoresist layer that is intended to be used for forming the plurality of electrodes and includes a plurality of areas corresponding to all the pre-semiconductor-chip portions;
forming a frame by patterning the photoresist layer by photolithography, the frame having a plurality of openings that are intended to accommodate the plurality of electrodes later; and
forming the plurality of electrodes in the plurality of openings of the frame.
11. The manufacturing method according to claim 7, wherein the main body of a lowermost one of the plurality of subpackages further has the plurality of second terminals.
12. The manufacturing method according to claim 7, wherein the main body of an uppermost one of the plurality of subpackages further has the plurality of first terminals.
13. The manufacturing method according to claim 7, wherein the respective main bodies of all of the plurality of subpackages each have the plurality of first terminals and the plurality of second terminals.
14. The manufacturing method according to claim 7, wherein:
The present invention relates to a composite layered chip package that includes a plurality of subpackages stacked and a method of manufacturing the same.
A case will now be considered where a memory device such as a flash memory is formed using a layered chip package. For a memory device such as a flash memory, a redundancy technique of replacing a defective column of memory cells with a redundant column of memory cells is typically employed so that the memory device can normally function even when some memory cells are defective. The redundancy technique can also be employed in the case of forming a memory device using a layered chip package. This makes it possible that, even if some of memory cells included in any chip are defective, the memory device can normally function while using the chip including the defective memory cells. Suppose, however, that a chip including a control circuit and a plurality of memory cells has become defective due to, for example, a wiring failure of the control circuit, and the chip cannot function normally even by employing the redundancy technique. In such a case, the defective chip is no longer usable. While the defective chip can be replaced with a conforming one, it increases the cost for the layered chip package.
US 2007/0165461 A1 discloses a technique of identifying one or more defective flash memory dies in a flash memory device having a plurality of flash memory dies, and disabling memory access operations to each identified die.
In the case of forming a memory device using a layered chip package, one or more defective chips included in the layered chip package may be identified and disabled in the same way as the technique disclosed in US 2007/0165461 A1.
If, however, a layered chip package including a predetermined number of chips is able to implement a memory device having a desired memory capacity only when all the chips included in the layered chip package are conforming, simply disabling a defective chip included in the layered chip package cannot achieve the implementation of the memory device having such a desired memory capacity.
It is an object of the present invention to provide a composite layered chip package including a plurality of semiconductor chips stacked and its manufacturing method, the composite layered chip package being capable of providing, even if it includes a malfunctioning semiconductor chip, the same functions as those for the case where no malfunctioning semiconductor chip is included.
A composite layered chip package according to the present invention includes a plurality of subpackages stacked, every two vertically adjacent subpackages being electrically connected to each other. Each of the plurality of subpackages includes: a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body. The main body has a main part, the main part including at least one first-type layer portion and having a top surface and a bottom surface.
For any two vertically adjacent subpackages, the main body of the lower subpackage further has a plurality of first terminals that are arranged on the top surface of the main part and electrically connected to the wiring, while the main body of the upper subpackage further has a plurality of second terminals that are arranged on the bottom surface of the main part and electrically connected to the wiring. The plurality of second terminals of the main body of the upper subpackage are electrically connected to the plurality of first terminals of the main body of the lower subpackage. The main part of the main body of at least one of the plurality of subpackages further includes at least one second-type layer portion. Each of the first-type layer portion and the second-type layer portion includes a semiconductor chip. The first-type layer portion further includes a plurality of electrodes, each of the electrodes being electrically connected to the semiconductor chip and having an end face located at the at least one of the side surfaces of the main body on which the wiring is disposed, whereas the second-type layer portion does not include the plurality of electrodes. The wiring is electrically connected to the end faces of the plurality of electrodes.
In the composite layered chip package according to the present invention, the semiconductor chip of the first-type layer portion may be a normally functioning one whereas the semiconductor chip of the second-type layer portion may be a malfunctioning one.
In the composite layered chip package according to the present invention, the main body of a lowermost one of the plurality of subpackages may further have the plurality of second terminals.
In the composite layered chip package according to the present invention, the main body of an uppermost one of the plurality of subpackages may further have the plurality of first terminals.
In the composite layered chip package according to the present invention, the respective main bodies of all of the plurality of subpackages may each have the plurality of first terminals and the plurality of second terminals.
In the composite layered chip package according to the present invention, the semiconductor chip may have four side surfaces, and each of the first-type layer portion and the second-type layer portion may further include an insulating portion that covers at least one of the four side surfaces of the semiconductor chip. In this case, the insulating portion may have at least one end face that is located at the at least one of the side surfaces of the main body on which the wiring is disposed.
A manufacturing method for the composite layered chip package according to the present invention includes the steps of: fabricating a plurality of subpackages; and stacking the plurality of subpackages and, for any two vertically adjacent subpackages, electrically connecting the plurality of second terminals of the upper subpackage to the plurality of first terminals of the lower subpackage.
In the manufacturing method for the composite layered chip package according to the present invention, the semiconductor chip of the first-type layer portion may be a normally functioning one whereas the semiconductor chip of the second-type layer portion may be a malfunctioning one.
In this case, the step of fabricating the plurality of subpackages may include, as a series of steps for forming each subpackage, the step of fabricating at least one substructure that includes a plurality of preliminary layer portions arrayed, each of the preliminary layer portions being intended to be made into any one of the layer portions included in the main part, the substructure being intended to be cut later at the position of the boundary between every adjacent preliminary layer portions; and the step of fabricating the subpackage by using the at least one substructure. The step of fabricating the at least one substructure may include the steps of: fabricating a pre-substructure wafer including a plurality of pre-semiconductor-chip portions that are arrayed and intended to be made into the individual semiconductor chips; distinguishing the plurality of pre-semiconductor-chip portions included in the pre-substructure wafer into normally functioning pre-semiconductor-chip portions and malfunctioning pre-semiconductor-chip portions; and forming the plurality of electrodes in the normally functioning pre-semiconductor-chip portions while not forming the plurality of electrodes in the malfunctioning pre-semiconductor-chip portions, so as to make the pre-substructure wafer into the substructure.
The step of forming the plurality of electrodes may include the steps of: forming a photoresist layer that is intended to be used for forming the plurality of electrodes and includes a plurality of areas corresponding to all the pre-semiconductor-chip portions; forming a frame by patterning the photoresist layer by photolithography, the frame having a plurality of openings that are intended to accommodate the plurality of electrodes later; and forming the plurality of electrodes in the plurality of openings of the frame.
In the manufacturing method for the composite layered chip package according to the present invention, the main body of a lowermost one of the plurality of subpackages may further have the plurality of second terminals.
In the manufacturing method for the composite layered chip package according to the present invention, the main body of an uppermost one of the plurality of subpackages may further have the plurality of first terminals.
In the manufacturing method for the composite layered chip package according to the present invention, the respective main bodies of all of the plurality of subpackages may each have the plurality of first terminals and the plurality of second terminals.
In the manufacturing method for the composite layered chip package according to the present invention, the semiconductor chip may have four side surfaces, and each of the first-type layer portion and the second-type layer portion may further include an insulating portion that covers at least one of the four side surfaces of the semiconductor chip. In this case, the insulating portion may have at least one end face that is located at the at least one of the side surfaces of the main body on which the wiring is disposed.
The composite layered chip package according to the present invention includes a plurality of subpackages stacked. For any two vertically adjacent subpackages, the plurality of second terminals of the main body of the upper subpackage are electrically connected to the plurality of first terminals of the main body of the lower subpackage. The main part of the main body of each of the plurality of subpackages includes at least one first-type layer portion. The main part of the main body of at least one of the plurality of subpackages further includes at least one second-type layer portion. The first-type layer portion includes a plurality of electrodes, each of the electrodes being electrically connected to the semiconductor chip and having an end face located at the at least one of the side surfaces of the main body on which the wiring is disposed, whereas the second-type layer portion does not include the plurality of electrodes. According to the present invention, a package including a plurality of semiconductor chips stacked can be easily implemented by stacking a plurality of subpackages, the package being capable of providing, even if it includes a malfunctioning semiconductor chip, the same functions as those for the case where no malfunctioning semiconductor chip is included.
FIG. 1 is a perspective view of a composite layered chip package according to an embodiment of the invention.
FIG. 9 is a plan view showing a pre-substructure wafer fabricated in a step of a manufacturing method for the composite layered chip package according to the embodiment of the invention.
FIG. 16 is an explanatory diagram showing an example of the configuration of an exposure apparatus for use in the manufacturing method for the composite layered chip package according to the embodiment of the invention.
FIG. 17 is a flow chart showing an exposure step for forming the plurality of electrodes in the manufacturing method for the composite layered chip package according to the embodiment of the invention.
FIG. 50 is perspective view showing a first modification example of the subpackage of the embodiment of the invention.
FIG. 51 is perspective view showing a second modification example of the subpackage of the embodiment of the invention.
A preferred embodiment of the present invention will now be described in detail with reference to the drawings. Reference is first made to FIG. 1 to FIG. 6 to describe the configuration of a composite layered chip package according to the embodiment of the invention. FIG. 1 is a perspective view of the composite layered chip package according to the embodiment of the invention. FIG. 2 is a perspective view showing the composite layered chip package of FIG. 1 as viewed from below. FIG. 3 is an exploded perspective view of the composite layered chip package of FIG. 1. FIG. 4 is an exploded perspective view of the composite layered chip package of FIG. 2. FIG. 5 is a perspective view of the composite layered chip package of FIG. 1 drawn such that respective end faces of a plurality of electrodes are visible. FIG. 6 is a side view of the composite layered chip package of FIG. 1.
The composite layered chip package 1 according to the present embodiment includes a plurality of subpackages stacked, every two vertically adjacent subpackages being electrically connected to each other. FIG. 1 to FIG. 6 show an example where the composite layered chip package 1 includes two subpackages 1A and 1B, the subpackage 1A being placed on the subpackage 1B. FIG. 3 and FIG. 4 show the state where the subpackages 1A and 1B are separated from each other. In the following description, any subpackage will be generally designated by reference numeral 1S.
In the present embodiment, the main body 2 of the lowermost subpackage 1S may further have the plurality of second terminals 5, and the main body 2 of the uppermost subpackage 15 may further have the plurality of first terminals 4. The respective main bodies 2 of all of the plurality of subpackages 15 may each have the plurality of first terminals 4 and the plurality of second terminals 5. In the example shown in FIG. 1 to FIG. 6, the main bodies 2 of both of the subpackages 1A and 1B each have the plurality of first terminals 4 and the plurality of second terminals 5. Consequently, in this case, the main body 2 of the lowermost subpackage 1B has the plurality of second terminals 5, and the main body 2 of the uppermost subpackage 1A has the plurality of first terminals 4.
With a plurality of layer portions 10 included in the main part 2M of its main body 2, a subpackage 1S itself is a layered chip package, which is combined with one or more other subpackages 1S to constitute the composite layered chip package 1.
The semiconductor chips 30 are not limited to memory chips, and may be used for implementing other devices such as CPUs, sensors, and driving circuits for sensors. The composite layered chip package 1 according to the present embodiment is particularly suitable for implementing an SiP.
Reference is now made to FIG. 8 to describe an example of the device included in the semiconductor chip 30. By way of example, the following description will be given for a case where the device included in the semiconductor chip 30 is a circuit including a plurality of memory cells that constitute a memory. FIG. 8 shows one of the plurality of memory cells.
The memory cell 40 includes a source 42 and a drain 43 formed near a surface of a P-type silicon substrate 41. The source 42 and the drain 43 are both N-type regions. The source 42 and the drain 43 are disposed at a predetermined distance from each other so that a channel composed of a part of the P-type silicon substrate 41 is provided between the source 42 and the drain 43. The memory cell 40 further includes an insulating film 44, a floating gate 45, an insulating film 46, and a control gate 47 that are stacked in this order on the surface of the substrate 41 at the location between the source 42 and the drain 43. The memory cell 40 further includes an insulating layer 48 that covers the source 42, the drain 43, the insulating film 44, the floating gate 45, the insulating film 46 and the control gate 47. The insulating layer 48 has contact holes that open at the tops of the source 42, the drain 43 and the control gate 47, respectively. The memory cell 40 includes a source electrode 52, a drain electrode 53, and a control gate electrode 57 that are formed on the insulating layer 48 at locations above the source 42, the drain 43 and the control gate 47, respectively. The source electrode 52, the drain electrode 53 and the control gate electrode 57 are connected to the source 42, the drain 43 and the control gate 47, respectively, through the corresponding contact holes.
Next, a description will be given of a manufacturing method for the composite layered chip package 1 according to the present embodiment. The manufacturing method for the composite layered chip package 1 according to the present embodiment includes the steps of: fabricating a plurality of subpackages 15; and stacking the plurality of subpackages 1S and, for any two vertically adjacent subpackages 1S, electrically connecting the plurality of second terminals 5 of the upper subpackage 1S to the plurality of first terminals 4 of the lower subpackage 1S.
The step of fabricating at least one substructure will now be described in detail with reference to FIG. 9 to FIG. 25. The following description will be given for a case where a plurality of substructures are fabricated. In the step of fabricating at least one substructure, a pre-substructure wafer 101 is first fabricated. The pre-substructure wafer 101 includes a plurality of pre-semiconductor-chip portions 30P that are arrayed and intended to be made into the individual semiconductor chips 30. FIG. 9 is a plan view of the pre-substructure wafer 101. FIG. 10 is a magnified plan view showing a part of the pre-substructure wafer 101 of FIG. 9. FIG. 11 shows a cross section taken along line 11-11 of FIG. 10.
As shown in FIG. 11, the pre-semiconductor-chip portions 30P include a device-forming region 33 that is formed near one of the surfaces of the semiconductor wafer 100. The device-forming region 33 is a region where devices are formed by processing the one of the surfaces of the semiconductor wafer 100. The pre-semiconductor-chip portions 30P further include a plurality of electrode pads 34 that are arranged on the device-forming region 33, and a passivation film 35 that is made of an insulating material and disposed over the device-forming region 33. The passivation film 35 has a plurality of openings for exposing the top surfaces of the plurality of electrode pads 34. The plurality of electrode pads 34 are located at positions corresponding to the plurality of electrodes 32 to be formed later, and are electrically connected to the devices formed in the device-forming region 33. Hereinafter, the surface of the pre-substructure wafer 101 located closer to the plurality of electrode pads 34 and the passivation film 35 will be referred to as a first surface 101 a. The surface on the opposite side will be referred to as a second surface 101 b. In the step of fabricating at least one substructure, next, a wafer sort test is performed to distinguish the plurality of pre-semiconductor-chip portions 30P included in the pre-substructure wafer 101 into normally functioning pre-semiconductor-chip portions and malfunctioning pre-semiconductor-chip portions. In this step, a probe of a testing device is brought into contact with the plurality of electrode pads 34 of each pre-semiconductor-chip portion 30P so that whether the pre-semiconductor-chip portion 30P functions normally or not is tested with the testing device. In FIG. 9, the pre-semiconductor-chip portions 30P marked with �NG� are malfunctioning ones, and the other pre-semiconductor-chip portions 30P are normally functioning ones. This step provides location information on the normally functioning pre-semiconductor-chip portions 30P and the malfunctioning pre-semiconductor-chip portions 30P in each pre-substructure wafer 101. The location information is used in an exposure step for forming a frame to be described later.
FIG. 15 shows a step that follows the step shown in FIG. 14. In this step, a plurality of openings 106 a for exposing the plurality of electrode pads 34 are formed in the insulating layer 106. If the insulating layer 106 is formed of a photosensitive material, the openings 106 a of the insulating layer 106 may be formed by photolithography. If the insulating layer 106 is formed of a non-photosensitive material, the openings 106 a of the insulating layer 106 may be formed by selectively etching the insulating layer 106. The insulating layer 106 may include a first layer that fills the plurality of grooves 104, and a second layer that covers the first layer and the plurality of electrode pads 34. In this case, the openings 106 a are formed in the second layer. Both of the first layer and the second layer may be formed of a resin such as an epoxy resin or a polyimide resin. The second layer may be formed of a photosensitive material such as a polyimide resin containing a sensitizer. If the second layer is formed of a photosensitive material, the openings 106 a may be formed in the second layer by photolithography. If the second layer is formed of a non-photosensitive material, the openings 106 a may be formed in the second layer by selectively etching the second layer. The first layer may be flattened at the top by, for example, ashing or chemical mechanical polishing (CMP), and then the second layer may be formed on the first layer.
If the pre-semiconductor-chip portion 30P is judged as a malfunctioning one (N) in Step S102, the area of the photoresist layer corresponding to the malfunctioning pre-semiconductor-chip portion 30P is subjected to an overall exposure by using a mask 201 that entirely passes light, or without using any mask 201 (Step S104). As a result, any latent image corresponding to a plurality of electrodes that are connected to the malfunctioning pre-semiconductor-chip portion 30P and each have an end face located at the at least one of the side surfaces of the main body 2 on which the wiring 3 is disposed is not formed in the area of the photoresist layer corresponding to the malfunctioning pre-semiconductor-chip portion 30P. To be more specific, the entire area of the photoresist layer corresponding to the malfunctioning pre-semiconductor-chip portion 30P becomes insoluble in the developing solution. If the second-type layer portion 10 includes any electrode or wiring that is other than one configured to be electrically connected to the defective semiconductor chip 30 and to have an end face located at the at least one of the side surfaces of the main body 2 on which the wiring 3 is disposed, an exposure is performed in Step S104 so that a latent image corresponding to such an electrode or wiring is formed, instead of the overall exposure. In this case also, any latent image corresponding to a plurality of electrodes that are connected to the malfunctioning pre-semiconductor-chip portion 30P and each have an end face located at the at least one of the side surfaces of the main body 2 on which the wiring 3 is disposed is not formed in the area of the photoresist layer corresponding to the malfunctioning pre-semiconductor chip portion 30P.
According to the present embodiment, a plurality of subpackages 15 whose respective main bodies 2 each have the second terminals 5 may be mounted on a wiring board, and the wiring of the wiring board and the second terminals 5 of the subpackages 1S may be used to establish electrical connection between the plurality of subpackages 1S. In such a case, if the respective main bodies 2 of the subpackages 1S mounted on a single wiring board each have the first terminals 4, the first terminals 4 of one of the subpackages 15 may be electrically connected to the first terminals 4 of another one of the subpackages 1S by wire bonding, for example.
The subpackage 15 is preferably such one that the main body 2 has both the first terminals 4 and the second terminals 5. With such a subpackage 1S, it is possible to stack three or more subpackages 1S and establish electrical connection therebetween. FIG. 44 shows an example where four subpackages 1S are stacked and electrically connected to each other, the respective main bodies 2 of the four subpackages 1S each having both the first terminals 4 and the second terminals 5.
According to the present embodiment, some misalignment between the terminals 4 and 5 is thus acceptable when stacking a plurality of subpackages 1S. This facilitates the alignment between two vertically adjacent subpackages 15. Consequently, according to the present embodiment, it is possible to reduce the manufacturing cost of an electronic component that includes a plurality of subpackages 1S stacked.
FIG. 47 shows an example of the method of manufacturing an electronic component that includes a plurality of subpackages 1S stacked. The method shown in FIG. 47 uses a heatproof container 141. The container 141 has an accommodating part 141 a in which a plurality of subpackages 1S can be stacked and accommodated. The accommodating part 141 a has such a size that the side surfaces of the subpackages 1S accommodated in the accommodating part 141 a and the inner walls of the accommodating part 141 leave a slight gap therebetween. In this method, the plurality of subpackages 1S are stacked and accommodated in the accommodating part 141 a of the container 141, and then the container 141 and the plurality of subpackages 1S are heated at temperatures at which the solder bumps 4B and 5B melt. This melts the solder bumps 4B and 5B of the terminals 4 and 5, whereby the terminals 4 and 5 of every two vertically adjacent subpackages 1S are bonded to each other. According to this method, it is possible to perform the alignment between the plurality of subpackages 1S easily by stacking and accommodating the subpackages 15 in the accommodating part 141 a of the container 141. This makes it easy to manufacture an electronic component that includes a plurality of subpackages 1S stacked.
The composite layered chip package 1 according to the present embodiment includes a plurality of subpackages 1S stacked. For any two vertically adjacent subpackages 1S of the composite layered package 1, the plurality of second terminals 5 of the main body 2 of the upper subpackage 15 are electrically connected to the plurality of first terminals 4 of the main body 2 of the lower subpackage 1S. The main part 2M of the main body 2 of each of the plurality of subpackages 1S includes at least one first-type layer portion 10A. The main part 2M of the main body 2 of at least one of the plurality of subpackages 1S further includes at least one second-type layer portion 10B. The first-type layer portion 10A includes a conforming semiconductor chip 30. The second-type layer portion 10B includes a defective semiconductor chip 30. The first-type layer portion 10A includes a plurality of electrodes 32 that are electrically connected to the semiconductor chip 30 and that each have an end face located at the at least one of the side surfaces of the main body 2 on which the wiring 3 is disposed, whereas the second-type layer portion 10B does not include the electrodes 32.
The manufacturing method for the composite layered chip package 1 according to the present embodiment includes the steps of fabricating a plurality of subpackages 1S; and stacking the plurality of subpackages 1S and electrically connecting, for any two vertically adjacent subpackages 1S, the plurality of second terminals 5 of the upper subpackage 1S to the plurality of first terminals 4 of the lower subpackage 1S.
The step of forming the plurality of electrodes 32 includes the steps of forming a photoresist layer 108P that is intended to be used for forming the plurality of electrodes 32 and includes a plurality of areas corresponding to all the pre-semiconductor-chip portions 30P; forming a frame 108 by patterning the photoresist layer 108P by photolithography, the frame 108 having a plurality of openings 108 a that are intended to accommodate the plurality of electrodes 32 later; and forming the plurality of electrodes 32 in the plurality of openings 108 a of the frame 108.
In the present embodiment, a composite layered chip package 1 including a required number of conforming semiconductor chips 30 can be formed by combining a plurality of subpackages 1S in various configurations. FIG. 48 and FIG. 49 show examples where a composite layered chip package 1 including eight conforming semiconductor chips 30 is formed by combining a plurality of subpackages 15 in different configurations from the configuration of the example of FIG. 1 to FIG. 6.
The composite layered chip package 1 shown in FIG. 48 includes two subpackages 1C and 1D that are stacked and electrically connected to each other. The subpackage 1C includes seven first-type layer portions 10A and a single second-type layer portion 10B. The subpackage 1D includes a single first-type layer portion 10A and a single second-type layer portion 10B.
This composite layered chip package 1 thus includes eight first-type layer portions 10A and two second-type layer portions 10B.
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Ltd.Layered chip package and method of manufacturing same* Cited by examinerClassifications U.S. Classification257/777, 257/686, 257/724, 438/107International ClassificationH01L23/29, H01L23/28, H01L23/48Cooperative ClassificationH01L2924/07802, H01L2225/1064, H01L2225/1035, H01L2924/14, H01L21/6835, H01L23/3171, H01L2224/05647, H01L2924/3025, H01L2224/13099, H01L2924/01004, H01L2224/05553, H01L25/0657, H01L2924/01029, H01L2924/01082, H01L2225/06513, H01L2221/68359, H01L2924/01005, H01L2224/18, H01L2924/014, H01L24/06, H01L24/29, H01L25/50, H01L2924/01006, H01L24/73, H01L2924/01014, H01L2924/30105, H01L24/25, H01L2924/01033, H01L2924/01078, H01L24/16, H01L25/105, H01L2924/078, H01L24/96, H01L2225/06551European ClassificationH01L25/065S, H01L25/10J, H01L23/31P6, H01L21/683T, H01L24/96, H01L24/06, H01L24/16, H01L24/25, H01L24/73, H01L25/50Legal EventsDateCodeEventDescriptionMay 15, 2014FPAYFee paymentYear of fee payment: 4Jan 29, 2010ASAssignmentOwner name: SAE MAGNETICS (H.K.) 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