Source: http://www.google.com/patents/US20050145941?dq=6680675
Timestamp: 2015-01-28 02:25:50
Document Index: 230013156

Matched Legal Cases: ['art 350', 'art 350', 'art 350', 'art 350', 'art 350', 'art 350', 'art 350', 'art 350', 'art 350', 'art 450', 'art 450', 'art 450', 'art 450', 'art 450', 'art 450']

Patent US20050145941 - High performance strained silicon FinFETs device and method for forming same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET....http://www.google.com/patents/US20050145941?utm_source=gb-gplus-sharePatent US20050145941 - High performance strained silicon FinFETs device and method for forming sameAdvanced Patent SearchPublication numberUS20050145941 A1Publication typeApplicationApplication numberUS 10/751,916Publication dateJul 7, 2005Filing dateJan 7, 2004Priority dateJan 7, 2004Also published asUS7705345, WO2005067677A2, WO2005067677A3Publication number10751916, 751916, US 2005/0145941 A1, US 2005/145941 A1, US 20050145941 A1, US 20050145941A1, US 2005145941 A1, US 2005145941A1, US-A1-20050145941, US-A1-2005145941, US2005/0145941A1, US2005/145941A1, US20050145941 A1, US20050145941A1, US2005145941 A1, US2005145941A1InventorsStephen Bedell, Kevin Chan, Dureseti Chidambarrao, Silke Christiansen, Jack Chu, Anthony Domenicucci, Kam-Leung Lee, Anda Mocuta, John Ott, Qiqing OuyangOriginal AssigneeInternational Business Machines CorporationExport CitationBiBTeX, EndNote, RefManReferenced by (35), Classifications (18), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetHigh performance strained silicon FinFETs device and method for forming sameUS 20050145941 A1Abstract A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET. Images(10) Claims(36)
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION Referring now to the drawings, and more particularly to FIGS. 1-8D, there are shown exemplary embodiments of the method and structures according to the present invention. Exemplary Embodiment Turning to FIG. 1, the device layout of a strained FinFET 100 according to the present invention is shown. As shown, the FinFET device 100 includes a Fin device structure (typically below sub-50 nm in Fin width) made out of relaxed silicon germanium (SixGe1-x) on insulator (SGOI)) with strained Si epitaxially formed on the sidewalls of the SixGe1-x FIN structures. In FIG. 1, the FinFET 100 includes a fin 101, formed adjacent a source and drain 102A, 102B. A gate 103 (e.g., preferably formed of polysilicon, but of course metal could be employed as would be known by one of ordinary skill in the art) is formed adjacent the fin 101. The FinFET 100 is formed on a silicon-on-insulator (SOI) layer 104 which can be formed of an oxide, nitride, etc. The SOI layer 104 is formed on a bulk silicon substrate 105. With the invention, processes have been developed to generate the new FINFET device structures with strained Si sidewalls. FIGS. 2-5 highlight the details of the invention, the inventive process development, and experimental results to demonstrate the successful fabrication of the strained Si sidewall structure according to the present invention, with the new processes and the existence of strain in the epitaxially grown Si using Convergent Beam Electron Diffraction (CBED) analysis in high resolution scanning transmission electron microscope. Turning to FIG. 2, a cross-section 200 of the gate area of the FinFET 100 of FIG. 1 with the cross-sectional view being shown along arrows II-II of FIG. 1. In FIG. 2, an SOI layer 204 is formed on a bulk silicon substrate 205. In the gate area, a fin 201 is formed of relaxed SiGe preferably having a composition of Ge within a range of about 20% to about 70% Ge, and preferably having a thickness in a range of about 50 nm to about 100 nm. On sidewalls of the relaxed SiGe fin 201, a strained silicon 208 is formed, via selective epitaxial growth. Preferably, the strained silicon sidewalls have a thickness of about 5 nm to about 20 nm. A gate oxide, preferably formed of silicon dioxide and preferably having a thickness of about 1 nm to about 5 nm, is formed adjacent the strained silicon sidewalls, and adjacent (e.g., over) the top of the relaxed SiGe fin 201. Instead of oxide, other materials could be employed such as HFO2 (e.g., a high K dielectric). A gate 203 (e.g., formed of polysilicon or metal) is formed over the gate oxide 207, over relaxed SiGe fin 201 and the strained silicon sidewalls 208, to complete the structure. In operation, voltage is supplied to the drain and source contacts. When voltage is applied to the gate and is above threshold voltage, current flows between the source and drain region of this fin connecting to the source and drain. Therefore, since the gate covers both sides of the fin, twice the amount of current flow between source and drain for the given gate voltage compared with the planar single gate device. First Exemplary Method Turning now to FIGS. 3A-3H and the flowchart 350 of FIG. 31, a process of forming a FinFET 300 according to the present invention is shown. First, in FIG. 3A (and step 355 of the flowchart 350 in FIG. 31), over a substrate (e.g., a silicon-on-insulator (SOI) layer 302 formed on a bulk silicon 301), a relaxed SiGe layer 303 is formed. Preferably, the thickness of the SiGe layer 303 is within a range of about 50 nm to about 100 nm. Preferably, the SiGe layer 303 is a graded layer formed by epitaxial growth. Additionally, the percentage of Ge in the SiGe layer is preferably within a range of about 20% to about 70%, and more preferably about 20% to about 40%. As the percentage of Ge is increased, the strain increases and the carrier mobility similarly increases. Thus, for a 20% composition of Ge in the SiGe layer, electron mobility will be increased about 1.8 times that of conventional silicon. For a 30% composition of Ge in the SiGe layer, electron mobility will be increased about 2.0 times that of conventional silicon, and for a 40% composition of Ge in the SiGe layer, mobility will be increased about 2.5 times that of conventional silicon. However, increasing the % of Ge about 40% generally will not increase the carrier mobility substantially any more, and thus a plateau is reached. FIG. 3J shows a graph illustrating a relationship of mobility vs. Ge content. In FIG. 3B (and step 360 of the flowchart 350 in FIG. 31), the relaxed SiGe layer is patterned and etched, preferably by a reactive ion etch (RIE) or the like. In FIG. 3C (and step 365 of the flowchart 350 in FIG. 31), a special low temperature CVD grown oxide 304 with a very thin sidewall (e.g., preferably having a thickness within a range of about 10 nm to about 20 nm) is deposited by CVD over the relaxed SiGe and exposed portions of the SOI layer 302. The oxide will be thinner on the sidewalls, but will be thicker (e.g., within a range of about 30 nm to about 50 nm) on the gate/top of the relaxed SiGe layer and the silicon-on-insulator layer. In FIG. 3D (and step 370 of the flowchart 350 in FIG. 31), as shown at reference numeral 305, the thin sidewall LTO is removed, for example, by wet chemical etch. The LTO formed over the exposed portions of the SOI layer 302 and the top surface of the relaxed SiGe 303 is left. As also shown, the LTO overhangs the sidewall. Then, in FIG. 3E (and step 375 of the flowchart 350 in FIG. 31), as shown at reference numeral 306, strained silicon is selectively epitaxially grown on the sidewall of the relaxed SiGe layer. Preferably, the strained silicon has a thickness of about 5 nm to about 20 nm. Then, in FIG. 3F (and step 380 of the flowchart 350 in FIG. 3I), the LTO 304 is removed from the top of the relaxed SiGe and from the SOI layer 302, preferably by a wet chemical etch. Thus, the selective epitaxial strained silicon is left on the sidewalls of the relaxed SiGe layer. Thereafter, in FIG. 3G (and step 385 of the flowchart 350 in FIG. 3I), a gate oxide 307 (e.g., such as SiO2 or HFO2, preferably having a thickness in a range of about 1 nm to about 5 nm) is formed conformally over the strained silicon sidewall and the top of the relaxed SiGe layer 303. Finally, in FIG. 3H (and step 390 of the flowchart 350 in FIG. 31), a gate, preferably formed of polysilicon or metal, and preferably having a thickness in a range of about 100 nm to about 150 nm, is formed over the structure, and a gate etch is performed. The gate etch also removes the thin gate oxide, as shown in FIG. 3H. It is noted that the source and drain are formed before the gate is formed. With the unique and unobvious exemplary aspects of the present invention, a new FinFET device (and method for forming the same) is provided with a FIN device structure (typically below sub-50 nm in FIN width) made out of a relaxed SixGe1-x on insulator (SGOI)) with strained Si epitaxially formed on the sidewalls of the SixGe1-x Fin structures. Thus, the first exemplary embodiment of the present invention forms a FINFET device structure with a strained Si sidewall. Hence, the invention provides a combination of strained silicon with a silicon FinFET. The epitaxially strained Si on the SixGe1-x Fin structure provides additional enhanced channel mobility over the conventional all-silicon FinFET structures, and improves device performance over conventional all-silicon FinFET devices. It is noted that as mentioned above, the SiGe layer 303 is a graded buffer layer, and will gradually become more and more relaxed in a direction away from the silicon surface of the SOI layer. That is, in a direction away from the silicon, the lattice of the SiGe will take the form of a SiGe lattice completely (e.g., as though the SiGe was formed as a bulk SiGe structure, assuming such a structure would be possible). Strain leads to a mismatch of the crystal plane. To make up for the strain, the structure attempts to compensate, and thereby dislocations and misfits are typically formed in the lattice cell, as described above. The dislocations and misfits result in threading defects. Such threading defects are problematic as they tend to propagate to the strained silicon and build up, thereby potentially damaging or destroying the device. However, the inventive structure using the FinFET, is less prone to such threading defects since the fin's width (SiGe and strained Si) is small (i.e., <0.1 μm). Thus, the inventive structure will have a smaller defect density than the conventional all-silicon, single gate devices. It is noted that while the invention discloses beginning with a relaxed substrate, this is not required. Indeed, one can obtain relaxed SiGe with strained sidewalls by starting with relaxed SiGe, or as a second option one can start with strained SiGe (e.g., so-called psuedomorphic structure), which will then self-relax when the SiGe fin width is less than 0.1 μm. Second Exemplary Embodiment A second exemplary embodiment, as shown in FIGS. 4A-4E, is advantageous as it allows the invention to minimize the number of mask steps. Indeed, it allows the invention to avoid a mask step since as shown and described below, there is a fin oxide hard mask above, and an oxide layer below, the relaxed SiGe layer. It is noted that thin silicon (�5-10 nm) from the SOI is removed after the SiGe Fin RIE. As a result, the second exemplary embodiment provides a process which is automatically self-aligned, thereby providing a more simple and elegant method even for a small gate. Hence, this embodiment provides self-aligned masking for selective growth. Moreover, there is no need to remove the hard mask to dope the top of the structure, as the invention allows doping on the sides of the structure. Turning now to FIGS. 4A-4E and the flowchart 450 of FIG. 4F, a process of forming a FinFET 400 according to the present invention is shown. First, in FIG. 4A (and step 455 of the flowchart 450 in FIG. 4F), over a substrate (e.g., a silicon-on-insulator (SOI) layer 402 formed, for example, on a bulk silicon 401), a relaxed SiGe layer 403 is formed. Preferably, the thickness of the SiGe layer 43 is within a range of about 50 nm to about 100 nm. Preferably, the SiGe layer 403 is a graded layer formed by epitaxial growth. Additionally, as before, the percentage of Ge in the SiGe layer is preferably within a range of about 20% to about 70%, and more preferably about 20% to about 40%. On top of the relaxed SiGe layer 403, a fin hard oxide mask 404 is formed. The mask 404 may be formed from low temperature CVD oxide materials with a thickness of the mask being between about 30 nm to about 50 nm. In FIG. 4B (and step 460 of the flowchart 450 in FIG. 4F), the relaxed SiGe layer 403 and the fin oxide hard mask 404 are patterned and etched, preferably by a reactive ion etch (RIE) or the like. In FIG. 4C (and step 465 of the flowchart 450 in FIG. 4F), strained silicon 406 is selectively epitaxially grown on the sidewalls of the relaxed SiGe layer 403. Preferably, the strained silicon has a thickness of about 5 nm to about 20 nm. Then, in FIG. 4D (and step 470 of the flowchart 450 in FIG. 4F), a gate oxide 407 (e.g., such as SiO2 or HFO2, preferably having a thickness in a range of about 1 nm to about 5 μm) is deposited. Finally, in FIG. 4E (and step 475 of the flowchart 450 in FIG. 4F), a gate 408, preferably formed of polysilicon or metal, and preferably having a thickness in a range of about 100 nm to about 150 nm, is formed over the fin body structure, and a gate etch is performed, to complete the structure. It is again noted that the source and drain would be formed before the gate is formed. Thus, this aspect of the invention minimizes a number of mask steps, and specifically allows the invention to avoid a masking step since the hard mask 404 is provided above, and the SOI layer 402 is provided below, the relaxed SiGe layer 403. As a result, less steps are required, and the process is automatically self-aligned (e.g., no need for additional patterning or etching), thereby providing a more simple and elegant method even for a small gate width. Hence, this embodiment provides self-aligned masking for selective grown. Moreover, there is no need to remove the hard mask to dope the top of the structure, as the invention allows doping on the sides of the structure. FIG. 5 illustrates schematically the computed lattice spacing distribution in different parts of the stained FINFET formed exemplarily of 16% relaxed SiGe layer on SiGe on insulator (SGOI). Reference numeral 506 represents strained silicon epitaxially grown on the sidewalls of the SiGe (16%) fin, whereas reference numeral 510 represents that the epitaxial silicon is tensile strained along the Y-Z plane. The number 85-100% represents the degree of relaxation deduced from distribution. As shown in the experimental results of FIGS. 6-8D, the invention has been demonstrated to be very advantageous over the conventional all-silicon single gate structures. FIG. 6 is a transmission electron micrograph (TEM) 600 which shows at reference numeral 610 selective Si epitaxial growth on the sidewall of a psuedomorphic SiGe fin. The psuedomorphic SiGe is deposited by a RTCVD method. FIG. 7 is a transmission electron micrograph (TEM) 700 which shows selective Si epitaxial growth on the sidewall of a 20% Ge 95% relaxed SiGe fin. The SiGe fin is deposited by RTCVD. FIGS. 8A-8D illustrate a convergent beam electron diffraction (CBED) for strain measurements in different regions (e.g., Regions 8A-8C shown in FIGS. 8B-8D respectively) of the SiGe buffer layer structure with selective epitaxially grown silicon. Specifically, FIG. 8B shows that similar distinct high order Laue zone lines indicate that region B in the SiGe structure is relaxed and not strained. FIG. 8C shows that distinct high order Laue zone lines obtained with CBED in a relaxed region of the SiGe buffer layer. In FIG. 8D, the blurred Laue zone lines in region C in the SiGe indicate strain in this part of the SiGe. The strain in SiGe region C is induced by the strain in the selectively grown epitaxial Si layer with 2 dimensionally limited geometry. The two-dimensional limited geometry refers to small fin sidewall dimensions. Thus, as discussed above, with the unique and unobvious exemplary aspects of the present invention, a new FinFET device (and method for forming the same) is provided with a Fin device structure (typically below sub-50 nm in Fin width) made out of a relaxed SixGe1-x on insulator (SGOI)) with strained Si epitaxially formed on the sidewalls of the SixGe1-x Fin structures. The present invention provides many advantages over conventional FinFETs and other advanced double gate devices including that epitaxially strained Si on SixGe1-x Fin structures provide additional enhanced channel mobility over current all silicon FinFET structures and this improves device performance over conventional all-silicon FinFET devices. Additionally, the epitaxially strained Si on the sidewall of the SixGe1-x Fin structures is less affected by threading defects that arise from the relaxed graded buffer layer and which are always found in the planar strained silicon CMOS devices. Hence, this invention leads to much better yield in manufacturing over planar strained silicon CMOS devices. While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. Further, it is noted that, Applicant's intent is to encompass equivalents of all claim elements, even if amended later during prosecution. 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SciencesFinFET with improved short channel effect and reduced parasitic capacitanceUS8598662 *Mar 2, 2011Dec 3, 2013Institute of Microelectronics, Chinese Academy of SciencesSemiconductor device and method for forming the sameUS8741703Sep 17, 2013Jun 3, 2014Institute of Microelectronics, Chinese Academy of SciencesMethod for manufacturing FinFET with improved short channel effect and reduced parasitic capacitanceUS8816392 *Mar 2, 2011Aug 26, 2014Institute of Microelectronics, Chinese Academy of SciencesSemiconductor device having gate structures to reduce the short channel effectsUS20120001229 *Mar 2, 2011Jan 5, 2012Institute of Microelectronics, Chinese Academy of SciencesSemiconductor Device and Method for Forming the SameUS20120126332 *Feb 24, 2011May 24, 2012Huilong ZhuSemiconductor device and method for forming the sameUS20120223331 *Mar 2, 2011Sep 6, 2012Institute of Microelectronics, Chinese Academy of SciencesSemiconductor device and method for forming the sameUS20130240828 *Dec 28, 2012Sep 19, 2013Kensuke OtaSemiconductor device and method of manufacturing the sameUS20130320399 *May 30, 2012Dec 5, 2013International Business Machines CorporationEmbedded planar source/drain stressors for a finfet including a plurality of finsWO2006002410A2 *Jun 21, 2005Jan 5, 2006Kevin K ChanCompressive sige <110> growth mosfet devicesWO2011038598A1 *Jun 24, 2010Apr 7, 2011Institute of Microelectronics, Chinese Academy of SciencesSemiconductor device and method thereof* Cited by examinerClassifications U.S. Classification257/348, 257/E21.703, 257/E29.275, 257/E27.112, 257/E29.298International ClassificationH01L27/01, H01L21/84, H01L29/786, H01L21/336, H01L27/12Cooperative ClassificationH01L29/785, H01L21/845, H01L29/66795, H01L27/1211European ClassificationH01L29/66M6T6F16F, H01L21/84F, H01L27/12B4, H01L29/78SLegal EventsDateCodeEventDescriptionApr 11, 2014FPAYFee paymentYear of fee payment: 4Apr 11, 2014SULPSurcharge for late paymentDec 6, 2013REMIMaintenance fee reminder mailedJun 9, 2004ASAssignmentOwner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BEDELL, STEPHEN W.;CHAN, KEVIN K.;CHIDAMBARRAO, DURESETI;AND OTHERS;REEL/FRAME:014713/0674;SIGNING DATES FROM 20040128 TO 20040217Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION,NEW YOFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BEDELL, STEPHEN W.;CHAN, KEVIN K.;CHIDAMBARRAO, DURESETIAND OTHERS;SIGNED BETWEEN 20040128 AND 20040217;US-ASSIGNMENT DATABASE UPDATED:20100427;REEL/FRAME:14713/674Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BEDELL, STEPHEN W.;CHAN, KEVIN K.;CHIDAMBARRAO, DURESETI;AND OTHERS;SIGNING DATES FROM 20040128 TO 20040217;REEL/FRAME:014713/0674RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services