Source: http://www.google.com/patents/US6878884?dq=5,867,764
Timestamp: 2014-07-10 17:11:17
Document Index: 513555889

Matched Legal Cases: ['art.\n6', 'art.\n7', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20']

Patent US6878884 - Wiring board, and electronic device with an electronic part mounted on a ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn electronic device is mounted on a wiring board, which includes: a substrate having through holes, and lands extending on surfaces of the substrate and adjacent to openings of the through holes. Further, at least one coating layer is provided, which coats at least one part of an outer peripheral region...http://www.google.com/patents/US6878884?utm_source=gb-gplus-sharePatent US6878884 - Wiring board, and electronic device with an electronic part mounted on a wiring board, as well as method of mounting an electronic part on a wiring boardAdvanced Patent SearchPublication numberUS6878884 B2Publication typeGrantApplication numberUS 10/419,197Publication dateApr 12, 2005Filing dateApr 21, 2003Priority dateApr 22, 2002Fee statusPaidAlso published asCN1271896C, CN1454039A, CN1747627A, US7273988, US20030196831, US20050146019, US20050230147Publication number10419197, 419197, US 6878884 B2, US 6878884B2, US-B2-6878884, US6878884 B2, US6878884B2InventorsYuki MomokawaOriginal AssigneeNec CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (10), Referenced by (1), Classifications (28), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetWiring board, and electronic device with an electronic part mounted on a wiring board, as well as method of mounting an electronic part on a wiring boardUS 6878884 B2Abstract An electronic device is mounted on a wiring board, which includes: a substrate having through holes, and lands extending on surfaces of the substrate and adjacent to openings of the through holes. Further, at least one coating layer is provided, which coats at least one part of an outer peripheral region of the at least one land, in order to cause that the at least one part is separated from a lead-less solder, thereby preventing any peel of the land from the surface of the substrate.
a wiring board comprising at least one through hole; and an electronic part mounted on said wiring board, said electronic part comprising at least one lead inserted into said at least one through hole and bonded to said at least one through hole via a lead-less solder, wherein said wiring board comprises: a substrate comprising said at least one through hole; and at least one land extending on at least one surface of said substrate, said at least one land extending adjacent to an opening of said at least one through hole, wherein a projecting length of said at least one lead from said at least one surface of said substrate is not greater than one half of a horizontal size of said at least one land, where said projecting length being defined to be a length of a projecting part of said at least one lead, which projects from said at least one surface of said substrate, and wherein said lead-less solder comprises a flat fillet directly contacting an entirety of said at least one land. 2. The electronic device as claimed in claim 1, wherein said projecting length is not greater than zero, and said at least one lead is free of any project part from said at least one surface of said substrate.
3. The electronic device as claimed in claim 1, wherein at least one coating layer is provided on a first surface of said substrate, and said first surface faces to said electronic part, and said at least one coating layer coats at least one part of an outer peripheral region of said at least one land, so that said at least one part of said outer peripheral region of said at least one land is separated from said lead-less solder, and
wherein a second-side projecting length of said at least one lead from a second surface of said substrate is not greater than one half of a horizontal size of said at least one land on said second surface, where said second-side projecting length is defined to be a length of a projecting part of said at least one lead, which projects from said second surface of said substrate, and said land on said second surface of said substrate is in contact with a flat fillet of said lead-less solder. 4. The electronic device as claimed in claim 3, wherein said second-side projecting length is not greater than zero, and said at least one lead is free of any second-side project part from said second surface of said substrate.
5. The electronic device as claimed in claim 3, wherein said at least one coating layer is spatially separated from said electronic part.
6. The electronic device as claimed in claim 3, wherein said at least one coating layer is in contact with said electronic part.
7. The electronic device as claimed in claim 3, wherein said projecting length comprises a length greater than zero.
8. The electronic device as claimed in claim 1, wherein at least one spacer is provided between said electronic part and a first surface of said substrate, and said first surface faces to said electronic part, so that said at least one part of said outer peripheral region of said at least one land is separated from said lead-less solder, and
wherein a second-side projecting length of said at least one lead from a second surface of said substrate is not greater than one half of a horizontal size of said at least one land on said second surface, where said second-side projecting length is defined to be a length of a projecting part of said at least one lead, which projects from said second surface of said substrate, and said land on said second surface of said substrate is in contact with a fiat fillet of said lead-less solder. 9. The electronic device as claimed in claim 8, wherein said second-side projecting length is not greater than zero, and said at least one lead is free of any second-side projecting part from said second surface of said substrate.
10. The electronic device as claimed in claim 8, wherein said at least one spacer coats said land on said first surface of said substrate.
11. The electronic device as claimed in claim 8, wherein said at least one spacer does not coat said land on said first surface of said substrate, and at least one coating layer is further provided on said first surface of said substrate, and said at least one coating layer coats at least one part of an outer peripheral region of said land on said first surface of said substrate.
12. The electronic device as claimed in claim 11, wherein said at least one coating layer coats both an entirety of said land on said first surface of said substrate and a first side opening of said at least one through hole.
13. The electronic device as claimed in claim 8, wherein said projecting length comprises a length greater than zero.
14. The electronic device as claimed in claim 1, wherein said wiring board further includes:
a first conductive film extending on an inner wall of said at least one through hole, and said first conductive film being connected with said at least one land; at least one circuit wiring extending on said at least one surface of said substrate, and said at least one circuit wiring being connected with a connecting part of an outer peripheral region of said at least one land; and at least one protection film covering said at least one circuit wiring. 15. The electronic device as claimed in claim 14, wherein a confronting surface of said electronic part is adjacent to said at least one protection film, and said confronting surface faces to a first surface of said substrate, and said land on said first surface of said substrate is in contact with at least one flat fillet of said lead-less solder.
16. The electronic device as claimed in claim 1, wherein said projecting length is greater than zero and not greater than one half of a horizontal size of said at least one land.
17. The electronic device as claimed in claim 16, wherein said projecting length is not greater than 1 millimeter.
18. The electronic device as claimed in claim 1, wherein said flat fillet directly contacts said at least one land.
19. The electronic device as claimed in claim 18, wherein said flat fillet directly contacts an entirety of said at least one land.
20. The electronic device as claimed in claim 1, wherein said lead-less solder comprises at least one of a tin-zinc-based solder, a tin-silver-based solder and a tin-copper-based solder.
21. The electronic device as claimed in 20, wherein said lead-less solder comprises a composition selected from the group consisting of tin-9.0 wt % zinc, tin-8.0 wt % zinc-3.0 wt % bismuth, tin-3.5 wt % silver, tin-3.0 wt % silver-0.5 wt % copper, tin-3.5 wt % silver-0.75 wt % copper, tin-0.7 wt % copper, and tin-0.7 wt % copper-0.3 wt % silver.
22. The electronic device as claimed in claim 1, wherein said projecting length comprises a length greater than zero.
23. The electronic device as claimed in claim 1, wherein a slope of said flat fillet comprises a substantially small included angle.
a wiring board comprising: at least one through hole; a substrate comprising said at least one through hole; and at least one land extending on at least one surface of said substrate, said at least one land extending adjacent to an opening of said at least one through hole; and an electronic part mounted on said wiring board, said electronic part comprising at least one lead inserted into said at least one through hole and bonded to said at least one through hole via a lead-less solder, wherein said lead-less solder comprises a flat fillet directly contacting an entirety of said at least one land. 25. The electronic device as claimed in claim 24, wherein a projecting length of said at least one lead from said at least one surface of said substrate is not greater than one half of a horizontal size of said at least one land, said projecting length being defined to be a length of a projecting part of said at least one lead, which projects from said at least one surface of said substrate.
26. The electronic device as claimed in claim 25, wherein said projecting length is not greater than zero, and said at least one lead is free of any projecting part from said at least one surface of said substrate.
27. The electronic device as claimed in claim 24, wherein at least one coating layer is provided on a first surface of said substrate, and said first surface faces to said electronic part, and said at least one coating layer coats at least one part of an outer peripheral region of said at least one land, so that said at least one part of said outer peripheral region of said at least one land is separated from said lead-less solder, and
wherein a second-side projecting length of said at least one lead from a second surface of said substrate is not greater than one half of a horizontal size of said at least one land on said second surface, said second-side projecting length being defined to be a length of a projecting part of said at least one lead, which projects from said second surface of said substrate, and said land on said second surface of said substrate is in contact with a flat fillet of said lead-less solder. 28. The electronic device as claimed in claim 24, wherein said projecting length comprises a length greater than zero.
The opposite surfaces of the copper-clad lamination substrate 11 are covered by solder resist layers 17, except for the lands 15 and peripheral portions thereof. For example, the circuit wirings 16 on each of the opposite surfaces of the copper-clad lamination substrate 11 are covered by the solder resist layer 17. The solder resist layer 17 serves as a protection layer which protects the surface of the copper-clad lamination substrate 11 from soldering with a tin-lead solder 31, except for the land 15 which is soldered with the tin-lead solder 31 The solder resist layer 17 may be formed by printing a paste on the each surface of the copper-clad lamination substrate 11 and subsequent exposure to a light. The solder resist layer 17 is so formed as not covering the land 15, in order to allow formation of a fillet 31A of the tin-lead solder 31 without any disturbance.
An electric part 20 is mounted on the wiring board 110A. The electric part 20 has a body 21 and a plurality of leads 22, one of which is shown in FIG. 2. The lead 22 is inserted into the through hole 14 of the wiring board 110A, so that the lead 22 completely penetrates the through hole 14, whereby a top of the lead 22 projects from the opposite surface to the surface in the side of the electric part 20. The lead 22 is bonded to the through hole 14 via the tin-lead solder 31. Since the solder resist layer 17 is so formed as not covering the land 15, the fillet 31A of the tin-lead solder 31 is formed. A typical example of the tin-lead solder 31 is a tin-lead eutectic solder containing 63% by weight of Sn and 37% by weight of Pb, which will hereinafter be referred to as Pb-63Sn. The tin-lead solder 31 relaxes a stress which is caused by a miss-match or a difference in thermal expansion coefficient between different materials of the lead 22 and the copper-clad lamination substrate 11, whereby no defect is caused on the connection between the electric part 20 and the wiring board 110A.
It is the fact that a large number of the read-made products are as shown in FIG. 2 and free of any countermeasure to suppress the peeling of the land 15. In case that the electronic part 20 becomes defect and should be replaced by a new electronic part, if the new electronic part may be mounted on the wiring board 110A by use of a lead-less solder 32, then this may cause that the land 15 is peeled as described above. In order to avoid this problem, it may be effective that instead of the above wiring board 110A, the new electronic part is mounted onto the wiring board 110B.
It is also possible that the at least one coating layer omnidirectionally coats an entirety of the outer peripheral region of the at least one land.
An eighth aspect of the present invention is a method of mounting an electronic part having at least one lead onto a wiring, board having at least one through hole for allowing an insertion of the at least one lead. The method includes the steps of:
After the soldering process, the melt lead-less solder 32 is cooled and shows a solidifying shrinkage. As shown in FIG. 9, the solidifying shrinkage of the lead-less solder 32 applies a force or a tension to the land 15. For example, a position �P� of the land 15, which is aligned to the inner periphery 18-1 of the coating layer 18, is applied with a tension �T� which is directed along a slope direction of the base portion of the fillet 32A of the lead-less solder 32, wherein the slope direction has an included angle �θ� to the surface of the land 15. The tension �T� has a vertical component �T sin θ� which is vertical to the surface of the land 15. The vertical component �T sin θ� of the applied tension �T� to the land 15 opposes to an adhesion force �W� effective for adhering or securing the land 15 to the surface of the copper-clad lamination substrate 11. The vertical component �T sin θ� may be considered to be a peeling force to peel the land 15 from the surface of the copper-clad lamination substrate 11. The adhesion force �W� is opposed to the peeling force �T sin θ�.
The peel of the land 15 is caused if the peeling force �T sin θ� is larger than the adhesion force �W�. The adhesion force �W� becomes weaken as the position becomes outwardly, and becomes stronger as the position becomes inwardly. The coating layer 18, which overlies the outer peripheral region of the land 15, blocks or defines the base portion of the fillet 32A of the lead-less solder 32. Namely, the fillet 32A is in contact with the land 15 except for the outer peripheral region thereof. This means that the land 15 receives the tension or the peeling force, except for the outer peripheral region thereof. In other words, the presence of the coating layer 18, which overlies the outer peripheral region of the land 15, ensures that the outer peripheral region of the land 15 is separated from the fillet 32A of the lead-less solder 32, whereby the outer peripheral region of the land 15 receives no tension from the solidifying shrinkage of the fillet 32A of the lead-less solder 32. The inside region of the land 15, which is inside of the outer peripheral region thereof, has larger adhesion forces than the peripheral region thereof. No application of the tension or the peeling force to the outer peripheral region of the land 15 having the weak adhesion force contributes to avoid that the adhesion force �W� of the inside land region is smaller than the peeling force �T sin θ� applied to the inside land region. This may suppress the land 15 from being peeled or floated from the surface of the copper-clad lamination substrate 11.
The manufacturing cost for the coating layer 18 is lower than the manufacturing cost for the above-described solder resist 117 shown in FIG. 5 The use of the coating layer 18 instead of the above-described solder resist 117 realizes suppression to the peel of the land 15 and allows the electronic device to have a long life-time and a high reliability at the low cost.
The above described technique for mounting the electronic part 20 onto the wiring board 10 in accordance with the present invention is applicable to not only the process for formation of the new product but also the other process for repairing the used product by changing the defective or failure electronic part to the new non-defective electronic part. In case that the defective or failure electronic part is mounted on the wiring board 110A free of the coating layer 18, then the coating layer 18 is provided on the wiring board 110A, before the new non-defective electronic part 20 is mounted onto the wiring board 110A with the coating layer 18 by use of the lead-less solder 32, there y preparing the electronic device by use of the lead-less solder 32 without disposal of the wiring board 110A.
It is also possible as yet more modification that a wiring board 10B has a coating layer 18A which overlies the entirety of a first surface of the copper-clad lamination substrate 11 and the coating layer 18 which overlies the solder resist 17 and the outer peripheral region of the land 15 on the second surface of the copper-clad lamination substrate 11, wherein the first surface is closer to the electronic part 20 and the second surface is opposite to the first surface. FIG. 12 is a fragmentary cross sectional elevation view of a second modification to the first novel structure of a wiring board with through holes for mounting an electronic part thereon in a second modification to the first embodiment in accordance with the present invention. FIG. 13 is a fragmentary cross sectional elevation view of the second modification to the first novel structure of the wiring board, on which the electronic part is mounted via the through holes in the second modification to the first embodiment in accordance with the present invention. A modified wiring board 10B has: the copper-clad lamination substrate 11. On the first surface, which is closer to the electronic part 20, of the copper-clad lamination substrate 11, the coating layer 18B has no opening and overlies the entirety of the first surface of the copper-clad lamination substrate 11, for example, not only the solder resist 17 but also the entirety of the land 15 and the through hole 14. Namely, on the first surface of the copper-clad lamination substrate 11, the through hole 14 is blocked or closed by the coating layer 18B.
On the second surface opposite to the first surface, the presence of the coating layer 18, which overlies the outer peripheral region of the land 15, ensures that the outer peripheral region of the land 15 is separated from the fillet 32A of the lead-less solder 32, whereby the outer peripheral region of the land 15 receives no tension from the solidifying shrinkage of the fillet 32A of the lead-less solder 32. The inside region of the land 15, which is inside of the outer peripheral region thereof, has larger adhesion forces than the peripheral region thereof. No application of the tension or the peeling force to the outer peripheral region of the land 15 having the weak adhesion force contributes to avoid that the adhesion force �W� of the inside land region is smaller than the peeling force �T sin θ� applied to the inside land region. This may suppress the land 15 from being peeled or floated from the surface of the copper-clad lamination substrate 11.
After the soldering process, the melt lead-less solder 32 with the flat fillet 32B is cooled and shows a solidifying shrinkage. As shown in FIG. 20, the solidifying shrinkage of the lead-less solder 32 with the flat fillet 32B applies a force or a tension to the land 15. For example, a position �P� of the outer periphery 15A of the land 15 is applied with a tension �T� which is directed along a slope direction of the base portion of the flat fillet 32B of the lead-less solder 32, wherein the slope direction has a small included angle �θ� to the surface of the land 15. The tension �T� has a vertical component �T sin θ� which is vertical to the surface of the land 15. The vertical component �T sin θ� of the applied tension �T� to the land 15 opposes to an adhesion force �W� effective for adhering or securing the land 15 to the surface of the copper-clad lamination substrate 11. The vertical component �T sin θ� may be considered to be a peeling force to peel the land 15 from the surface of the copper-clad lamination substrate 11. The adhesion force �W� is opposed to the peeling force �T sin θ�.
The peel of the land 15 is caused if the peeling force �T sin θ� is larger than the adhesion force �W�. The adhesion force �W� becomes weaken as the position becomes outwardly, and becomes stronger as the position becomes inwardly. The flat fillet 32B makes the small included angle �θ� of the tension �T� to the surface of the land 15. The small included angle �θ� means that the small peeling force �T sin θ� is small. Namely, the land 15 receives the small tension or the small peeling force �T sin θ� when the lead-less solder 32 shows the solidifying shrinkage. As long as the small peeling force �T sin θ� is smaller than the weakest adhering force �W� at the outer periphery of the land 15, the application of the small peeling force �T sin θ� to the land 15 ensures suppressing the land 15 from being peeled or floated from the surface of the copper-clad lamination substrate 11.
Consequently, the above-described strict conditions, that the projecting length of the lead 22 is not larger than one half of the horizontal size of the land 15 on the second surface of the copper-clad lamination substrate 11, ensures formation of the flat fillet 32B of the lead-less solder 32 through the soldering process for mounting the electronic part 20 onto the wiring board 110A free of any coating layer, so that the solidifying shrinkage of the lead-less solder 32 causes the flat fillet 32B to apply the small peeling force �T sin θ� to the land 15, thereby to suppress the peel of the land 15. This allows the electronic device to have a long life-time and a high reliability. It is easy to satisfy the above-described strict conditions for the projecting length of the lead 22 by adjusting the projecting length of the lead 22 at a low cost. The suppression of the peel of the land 15 to manufacture the electronic device with the long life-time and the high reliability can be realized at a low cost.
Consequently, interposing the spacer 41 between the first surface of the copper-clad lamination substrate 11 and the body 21 of the electronic part 20 makes it easy to satisfy the above-described strict conditions, that the projecting length of the lead 22 is not larger than one half of the horizontal size of the land 15 on the second surface of the copper-clad lamination substrate 11. The satisfaction to the above-described strict conditions for the projecting length ensures formation of the flat fillet 32B of the lead-less solder 32 through the soldering process for mounting the electronic part 20 onto the wiring board 110A free of any coating layer, so that the solidifying shrinkage of the lead-less solder 32 causes the flat fillet 32B to apply the small peeling force �T sin θ� to the land 15, thereby to suppress the peel of the land 15. This allows the electronic device to have a long life-time and a high reliability. The suppression of the peel of the land 15 to manufacture the electronic device with the long life-time and the high reliability can be realized at a low cost.
Consequently, interposing the spacer 42 between the first surface of the copper-clad lamination substrate 11 and the body 21 of the electronic part 20 makes it easy to satisfy the above-described strict conditions, that the projecting length of the lead 22 is not larger than one half of the horizontal size of the land 15 on the second surface of the copper-clad lamination substrate 11. The satisfaction to the above-described strict conditions for the projecting length ensures formation of the flat fillet 32B of the lead-less solder 32 through the soldering process for mounting the electronic part 20 onto the wiring board 110A free of any coating layer, so that the solidifying shrinkage of the lead-less solder 32 causes the flat fillet 32B to apply the small peeling force �T sin θ� to the land 15, thereby to suppress the peel of the land 15. This allows the electronic device to have a long life-time and a high reliability. The suppression of the peel of the land 15 to manufacture the electronic device with the long life-time and the high reliability can be realized at a low cost.
Consequently, the provision of the body 21 in contact with the solder resist 17 on the first surface of the copper-clad lamination substrate 11 results in the formation of the flat fillet 32B in contact with the land 15 on the first surface of the copper-clad lamination substrate 11. The satisfaction is ensured to the above-described strict conditions, that the projecting length of the lead 22 is not larger than one half of the horizontal size of the land 15 on the second surface of the copper-clad lamination substrate 11. The flat fillets 32B on the first and second surfaces of the copper-clad lamination substrate 11 apply the small peeling force �T sin θ� to the land 15 upon the solidifying shrinkage of the lead-less solder 32, thereby to suppress the peel of the land 15. This allows the electronic device to have a long life-time and a high reliability. The suppression of the peel of the land 15 to manufacture the electronic device with the long life-time and the high reliability can be realized at a low cost.
FIGS. 28A through 28C are cross sectional elevation views illustrative of sequential processes for mounting the electronic part 20 onto the wiring board 110A. As shown in FIG. 28A, leads 22 with the original full length are attached to the body 21, thereby to form an electronic part 20. As shown in FIG. 28B, the leads 22 are cut to shorten the original full length into a shortened length, thereby to form an electronic part 20A with length-adjusted leads 23. As shown in FIG. 28C, the electronic part 20A with the length-adjusted leads 23 are mounted onto the wiring board 110A by the soldering process using the lead-less solder 23, wherein the length-adjusted leads 23 are inserted into the through holes 14 of the wiring board 110A. The length-adjusted leads 23 do not project from the second surface of the wiring board 110A.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4170819 *Apr 10, 1978Oct 16, 1979International Business Machines CorporationMethod of making conductive via holes in printed circuit boardsUS4410928 *May 1, 1981Oct 18, 1983Clarion Co., Ltd.Connector fixing deviceUS5398166 *May 19, 1994Mar 14, 1995Murata Manufacturing Co., Ltd.Electronic component and mounting structure thereofUS5953214 *May 24, 1996Sep 14, 1999International Business Machines CorporationDual substrate package assembly coupled to a conducting memberUS6512185 *Mar 14, 2001Jan 28, 2003Sony CorporationPrinted-wiring boardUS6657135 *Mar 14, 2001Dec 2, 2003Matsushita Electric Industrial Co., Ltd.Connection structure and electronic circuit boardJP2001244614A Title not availableJP2001332851A Title not availableJPH1051111A Title not availableJPH11251728A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7098407 *May 21, 2004Aug 29, 2006Samsung Electronics Co., Ltd.Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate* Cited by examinerClassifications U.S. Classification174/260, 361/760, 361/779, 174/262International ClassificationH05K3/30, H05K1/11, H05K1/03, H05K3/34Cooperative ClassificationH05K3/3447, H05K2203/1394, H05K2203/0588, H05K2201/2036, H05K2201/2081, H05K2201/10901, H05K3/3463, H05K2201/10575, H05K3/301, H05K3/3452, H05K2203/0577, H05K2201/10568, H05K2201/10909, H05K2203/1189, H05K3/306, H05K2203/0182, H05K2201/099European ClassificationH05K3/30D, H05K3/34E, H05K3/34DLegal EventsDateCodeEventDescriptionSep 12, 2012FPAYFee paymentYear of fee payment: 8Sep 22, 2008FPAYFee paymentYear of fee payment: 4Apr 21, 2003ASAssignmentOwner name: NEC CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOMOKAWA, YUKI;REEL/FRAME:013991/0115Effective date: 20030421Owner name: NEC CORPORATION 7-1, SHIBA 5-CHOME MINATO-KUTOKYO,Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOMOKAWA, YUKI /AR;REEL/FRAME:013991/0115RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google