Source: http://www.google.com/patents/US6849535?dq=6859936
Timestamp: 2017-07-27 23:57:31
Document Index: 340530717

Matched Legal Cases: ['art) 150', 'art 150', 'art 230', 'art 240', 'art 250', 'art 230', 'art 240', 'art 250', 'art 401', 'art 402', 'art 402', 'art 409', 'art 409', 'art 402', 'art 401', 'art 401', 'art 402', 'art 409', 'art 409', 'art 402']

Patent US6849535 - Semiconductor integrated circuit device and manufacturing method of ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor device comprises a semiconductor substrate; a first insulating film overlying a surface of the semiconductor substrate, an upper surface of the first insulating film being nitrided; a first copper-embedded interconnection embedded in the first insulating film, and which first copper-embedded...http://www.google.com/patents/US6849535?utm_source=gb-gplus-sharePatent US6849535 - Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6849535 B2Publication typeGrantApplication numberUS 10/128,265Publication dateFeb 1, 2005Filing dateApr 24, 2002Priority dateAug 10, 1999Fee statusPaidAlso published asUS6716749, US6756679, US6797606, US6797609, US6815330, US6864169, US20020113271, US20020119651, US20020127842, US20020127843, US20020142576, US20030001183, US20030001277, US20030001280, US20030017692, US20030045086, US20080138979Publication number10128265, 128265, US 6849535 B2, US 6849535B2, US-B2-6849535, US6849535 B2, US6849535B2InventorsJunji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchi, Nobuo OwadaOriginal AssigneeRenesas Technology Corp.Export CitationBiBTeX, EndNote, RefManPatent Citations (55), Non-Patent Citations (9), Referenced by (8), Classifications (54), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
US 6849535 B2Abstract
A semiconductor device comprises a semiconductor substrate; a first insulating film overlying a surface of the semiconductor substrate, an upper surface of the first insulating film being nitrided; a first copper-embedded interconnection embedded in the first insulating film, and which first copper-embedded interconnection contains copper as a main component; a copper nitride film overlying an upper surface of the first copper-embedded interconnection; a cap insulating film overlying an upper surface of the first insulating film and an upper surface of the copper nitride film; and a second insulting film overlying the cap insulating film.
(a) forming a first interconnection groove in a first interlayer insulating film over a first main surface of a wafer; (b) forming a first barrier metal film over the first interlayer insulating film both outside and inside the first interconnection groove; (c) forming a first interconnection metal film containing copper as a main component over the first barrier metal film both outside and inside the first interconnection groove so as to fill the first interconnection groove; (d) removing the first interconnection metal film outside the first interconnection groove by first chemical mechanical polishing using a first polishing slurry; (e) after step (d), removing the first barrier metal film outside the first interconnection groove by second chemical mechanical polishing using a second polishing slurry different from the first polishing slurry in composition; (f) after step (e), performing ammonia plasma treatment to upper surfaces of both the first interlayer insulating film and the first interconnection metal film; and (g) after step (f), forming a copper diffusion barrier insulating film on the treated upper surfaces by plasma CVD. 2. The method according to claim 1, wherein the first chemical mechanical polishing is performed using a first polishing pad, and the second chemical mechanical polishing is performed using a second polishing pad different from said first polishing pad.
3. The method according to claim 2, wherein the copper diffusion barrier insulating film is a silicon nitride film.
This application is a division of application Ser. No. 09/666,053 filed Sep. 20, 2009 now abandoned, which is a continuation of application Ser. No. 09/621,536 filed Jul. 21, 2000 now abandoned.
This invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, in particular, a technique effective when adapted for the so-called damascene method wherein an interconnection having copper as a main conductive layer is formed by cutting a groove in an insulating film, forming a copper film to be embedded in the groove and polishing by CMP (Chemical Mechanical Polishing).
The present inventors have found the below-described problems in the interconnection forming technique, so called damascene method, which comprises forming the above-described interconnection groove, forming a metal film (ex. copper film) to be embedded in the groove and removing the copper film outside the interconnection groove by CMP.
FIG. 55 is a graph illustrating the measured data of TDDB characteristics of a copper interconnection, an aluminum interconnection and a tungsten interconnection. The TDDB and electric field strength are plotted along the ordinate and abscissa, respectively. When the characteristics (data A) of the aluminum interconnection and those (data B) of the tungsten interconnection are extrapolated, the TDDB at an electric field strength of 0.2 MV/cm (ordinary using condition) easily exceeds 3×108 sec (10 years), which is a development target of the present inventors. When the characteristics (data C) of the copper interconnection is extrapolated, on the other hand, there is almost no margin for the development target of 10 years. The aluminum interconnection is formed by film deposition and patterning by photolithography, while the tungsten interconnection is formed by the damascene method similar to the copper interconnection. The copper interconnection and tungsten interconnection differ only in the material. There is no difference in their structures. A marked difference in TDDB characteristics between these two materials suggests that it results from the difference in the interconnection material. Here, the TDDB characteristics are measured at 140° C.
After the polishing step but prior to plasma treatment, the surface of each of the first insulating film and interconnection can be washed with an acid. For washing, an aqueous solution of hydrogen fluoride (HF) or citric acid (C(CH2COOH)2(OH)(COOH)) can be employed.
In another aspect, the present invention provides a manufacturing method which comprises forming a first insulating film over a semiconductor substrate, forming a groove in the first insulating film, forming a first conductive film and a second conductive film to embed the groove therewith, polishing the second and first conductive films to form an interconnection in the groove, subjecting the surface of each of the first insulating film and interconnection to reducing treatment and nitriding treatment with a plasma, and then depositing a'second insulating film over the first insulating film and interconnection.
(a) forming a first insulating film over a semiconductor substrate and forming a groove in the first insulating film, (b) depositing a first conductive film over the first insulating film and forming a second conductive film to embed the groove therewith, (c) removing the second conductive film and first conductive film over the first insulating film outside the groove and forming an interconnection in the groove, (d) treating the surface of each of the first insulating film and interconnection with a plasma of reducing atmosphere, and (e) after completion of the plasma treating step, depositing a second insulating film over the first insulating film and interconnection. 2. A manufacturing method according to the item 1, wherein the plasma of reducing atmosphere is an ammonia (NH3) plasma or hydrogen (H2) plasma.
3. A manufacturing method according to the item 1, wherein the plasma of reducing atmosphere is mixed gas plasma of ammonia (NH3) and a diluting gas, and the diluting gas contains one or more gases selected from hydrogen (H2), nitrogen (N2), argon (Ar) and helium (He)
4. A manufacturing method according to the item 3, wherein the concentration of ammonia (NH3) is at least 5 wt. % based on the mixed gas.
5. A manufacturing method according to the item 1, wherein the plasma of reducing atmosphere is a mixed gas plasma of hydrogen (H2) and a diluting gas and the diluting gas contains one or more gases selected from ammonia (NH3), nitrogen (N2), argon (Ar) and helium (He).
6. A manufacturing method according to the item 5, wherein the concentration of hydrogen (H2) is at least 5 wt. % based on the mixed gas.
7. A manufacturing method according to the item 1, wherein the first insulating film is a silicon oxide film and the second conductive film is made of copper.
8. A manufacturing method according to the item 7, wherein the second insulating film is a silicon nitride film.
9. A manufacturing method according to the item 8, wherein the plasma of reduced atmosphere is an ammonia (NH3) plasma or a hydrogen (H2) plasma, or a mixed gas plasma thereof with one or more gases selected from nitrogen (N2), argon (Ar) and helium (He).
10. A manufacturing method according to the item 9, wherein the copper has a purity as high as 99.99% or greater.
11. A manufacturing method according to the item 1, which further comprises washing the surface of each of the first insulating film and interconnection with an acid between the steps (c) and (d).
12. A manufacturing method according to the item 11, wherein an aqueous solution of hydrogen fluoride (HF) or citric acid (C(CH2COOH)2(OH) (COOH) is used as the acid for washing.
13. A manufacturing method according to the item 12, wherein the first insulating film, the second conductive film and the second insulating film are a silicon oxide film, copper and a silicon nitride film, respectively.
14. A manufacturing method according to the item 12, wherein the plasma of reduced atmosphere is an ammonia (NH3) plasma or a hydrogen (H2) plasma, or a mixed gas plasma thereof with one or more gases selected from nitrogen (N2), argon (Ar) and helium (He).
15. A manufacturing method according to the item 14, wherein the copper has a purity as high as 99.99% or greater.
16. A manufacturing method according to the item 1, wherein abrasive-grain-free chemical mechanical polishing is employed for the polishing in the step (c).
17. A manufacturing method according to the item 16, wherein the polishing in the step (c) is conducted in three stages, that is, first polishing by abrasive-grain-free chemical mechanical polishing, second polishing by abrasive-grain-using chemical mechanical polishing and third polishing by selective chemical mechanical polishing at a first conductive film:second conductive film selection ratio of at least 5.
18. A manufacturing method according to the item 17, wherein the first insulating film, the second conductive film and the second insulating film are a silicon oxide film, copper and a silicon nitride film, respectively.
19. A manufacturing method according to the item 18, wherein the plasma of reduced atmosphere is an ammonia (NH3) plasma or a hydrogen (H2) plasma, or a mixed gas plasma thereof with one or more gases selected from nitrogen (N2), argon (Ar) and helium (He).
20. A manufacturing method according to the item 19, which further comprises, between the steps (c) and (d), washing the surface of each of the first insulating film and interconnection with an aqueous solution of hydrogen fluoride (HF) or citric acid (C(CH2COOH)2(OH)(COOH).
21. A manufacturing method according to the item 20, wherein the copper has a purity as high as 99.99% or greater.
22. A manufacturing method of a semiconductor integrated circuit device, which comprises:
(a) forming a first insulating film over a semiconductor substrate and forming a groove in the first insulating film, (b) depositing a first conductive film over the first insulating film and forming a second conductive film to embed the groove therewith, (c) removing the second conductive film and first conductive film over the first insulating film outside the groove by polishing and forming an interconnection in the groove, (d) subjecting the surface of each of the first insulating film and interconnection to reducing treatment and nitriding treatment with a plasma, and (e) depositing the second insulating film over the first insulating film and interconnection. 23. A manufacturing method according to the item 22 wherein the plasma is an ammonia (NH3) plasma or a mixed gas plasma thereof with a diluting gas, and the diluting gas is at least one gas selected from hydrogen (H2), nitrogen (N2), argon (Ar) and helium (He).
24. A manufacturing method of a semiconductor integrated circuit having a first insulating film formed over a semiconductor substrate and a protecting film formed thereover for preventing the invasion of impurities, which comprises:
(a) forming a first insulating film having a dielectric constant lower than that of a silicon oxide film contained in the protecting film, (b) forming a groove or opening in the first insulating film, (c) treating the exposed surface of the first insulating film with a plasma of reducing atmosphere, (d) depositing a first conductive film to cover the surface including the inside wall of the groove or opening and forming a second conductive film to embed therewith the groove or opening, and (e) removing the second conductive film and first conductive film outside the groove or opening by polishing and forming a conductive member in the groove or opening. 25. A manufacturing method according to the item 24, wherein the plasma of reduced atmosphere is an ammonia (NH3) plasma or a hydrogen (H2) plasma, or a mixed gas plasma thereof with one or more gases selected from nitrogen (N2), argon (Ar) and helium (He).
26. A manufacturing method according to the item 25, wherein a second insulating film is formed over the first insulating film, a groove or opening is formed in the first and second insulating films in the step (b) and the surface of the first insulating film exposed to the inside wall of the groove or opening is treated with a plasma of reducing atmosphere.
27. A semiconductor integrated circuit device having a first insulating film formed over a semiconductor substrate, an interconnection embedded in a groove of the first insulating film and a second insulating film formed over the first insulating film and interconnection, wherein a nitride film is formed on the interface between the first insulating film and interconnection, and the second insulating film.
28. A semiconductor integrated circuit device according to the item 27, wherein the first insulating film, interconnection and second insulating film are a silicon oxide film, copper and silicon nitride film, respectively.
29. A semiconductor integrated circuit device according to the item 28, wherein the nitrogen concentration of the nitride film becomes higher from the first insulating film and interconnection toward the second insulating film.
30. A manufacturing method according to the item 1, which further comprises, after the completion of the step (d), depositing the second insulating film over the first insulating film and interconnection continuously while maintaining a reduced-pressure or inactive condition without exposing the semiconductor substrate to the atmosphere.
FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a manufacturing method of a semiconductor integrated circuit device according to one embodiment (Embodiment 1) of the present invention;
FIG. 9 is a schematic view illustrating one example of the whole constitution of a.CMP apparatus used for the formation of a Cu-embedded interconnection;
FIGS. 25(a) to 25(e) are graphs each illustrating XPS data and FIG. 25(f) is a table showing a component ratio;
FIGS. 56(a) to 56(c) illustrate a sample used in the present application for the measurement of TDDB, wherein
FIG. 56(a) is a plan view, and FIGS. 56(b) and 56(c) are cross-sections taken along lines B-B′ and C-C′ of FIG. 56(a), respectively;
The general meaning of each of the terms used in this application will next be described.
The term “TDDB” as used herein means time (lifetime) determined by applying a relatively high voltage between electrodes under measuring conditions of a predetermined temperature (ex. 140° C.), drawing a graph wherein time from application of voltage to dielectric breakdown is plotted against applied electric field, and extrapolating the practical electric field strength (ex. 0.2 MV/cm) in the graph. FIG. 56 illustrates a sample used in the present application for the measurement of TDDB, wherein FIG. 56(a) is a plan view, and FIGS. 56(b) and 56(c) are crosssections taken along lines B-B′ and C-C′ of FIG. 56(a), respectively. This sample can be formed practically in a TEG (Test Equipment Group) region of a wafer. As illustrated in FIG. 56, a pair of comb-like interconnections L are formed in the second interconnection layer M2 and are connected with pats P1,P2 of the uppermost layer. An electric current is measured by applying an electric field between these comb-like interconnections L. The pads 1,2 are measuring terminals. The width, distance between any two adjacent interconnections and thickness of the comb-like interconnections L are each 0.5 μm. The length of the interconnection is formed to 1.58×105 μm. FIG. 57 is a schematic view illustrating the summary of measurement. The sample is supported on a measuring stage S and a current-voltage measuring apparatus (I/V measuring apparatus) is connected between the pads P1 and P2. The sample stage S is heated by a heater H to adjust the temperature of the sample to 140° C. FIG. 58 shows one example of the measuring results of current-voltage under the conditions of the sample temperature of 140° C. and electric field strength of 5 MV/cm. Although TDDB is measured by either one of the constant voltage stress method and low current stress method, the former one wherein an average electric field applied to an insulating film shows a fixed value is employed in the present application. After application of voltage, the current density decreases with the passage of time and then, a drastic increase in the current (dielectric breakdown) is observed. Here, the time until the leak current density reaches 1 μA/cm2 is designated as TDDB (the TDDB at 5 MV/cm). The term “TDDB” as used herein means the breakdown time (lifetime) at 0.2 MV/cm unless otherwise specifically referred to, but in a broader sense, it is sometimes used as a time until breakdown at a preliminarily designated electric field strength. Unless otherwise specifically described, the TDDB means that at the sample temperature of 140° C. The TDDB is measured using the above-described comb-like interconnections L, but it is needless to say that it reflects the breakdown lifetime between actual interconnections.
The term “plasma treatment” as used herein means treatment of exposing the surface of a substrate or, when a member such as insulating film or metal film is formed on the substrate, the surface of the member to the circumstance under plasma condition and giving chemical or mechanical (bombardment) action of the plasma to the surface. Plasma is usually formed by, while supplementing a specific gas (treating gas) as needed in a reaction chamber substituted with the gas, ionizing the gas by the action of high-frequency electric field or the like. In practice, however, it is impossible to completely substitute the chamber with the treating gas. In the present application, therefore, the term “ammonia plasma” does not indicate complete ammonia plasma and existence of impurity gases (nitrogen, oxygen, carbon dioxide, water vapor and/or the like) contained in the plasma is permitted. It is needless to say that the plasma may contain a diluting gas or additive gas.
The term “plasma of reducing atmosphere” as used herein means the plasma circumstance wherein reactive radicals, ions, atoms or molecules having reducing action, that is, oxygen pulling action, predominantly exist. Radicals and ions embrace atomic or molecular radicals and ions. In the plasma circumstance, not only single reactive one but also plural reactive ones may be contained. For example, a hydrogen radical and NH2 radical may coexist in the circumstance.
The term “made of copper” as used herein means that copper is used as a main component. High-purity copper inevitably contains impurities so that a member made of copper is permitted to contain additives or impurities. The term “made of high-purity copper” as used herein means that copper is a high-purity material (ex. 4N (99.99%) and contains any impurities of about 0.01%. This will apply to, not only copper, but also another metal (titanium nitride, or the like).
The term “gas concentration” as used herein means a flow rate of a gas in the mass flow. Described specifically, when the concentration of gas A in a mixture of gas A and gas B is 5%, it means Fa/(Fa+Fb)=0.05 wherein Fa represents the mass flow rate of gas A and Fb represents the mass flow rate of gas B.
The term “polishing liquid (slurry)” usually means a suspension obtained by mixing abrasive grains in a chemical etching agent, but in this application, it embraces a polishing liquid free of an abrasive grain for the convenience sake of this invention.
The term “abrasive grains (slurry grains)” usually means powder such as alumina or silica contained in a slurry.
The term “chemical mechanical polishing (CMP)” usually means polishing of a surface to be polished by relatively moving a polishing pad, which is made of a relatively soft cloth-like sheet material, in a surface direction under the condition brought into contact with the polishing pad, while supplying a slurry. This invention also embraces CML (Chemical Mechanical Lapping) wherein polishing is conducted by moving a surface to be polished relative to the surface of a hard abrasive.
The term “abrasive-grain-free chemical mechanical polishing” means chemical mechanical polishing using a slurry having a weight concentration of the abrasive grains less than 0.5%, while the term “abrasive-grain-using chemical mechanical polishing” means chemical mechanical polishing using a slurry having a weight concentration of the abrasive grain not less than 0.5%. They are however relative naming. In the case where chemical mechanical polishing is conducted using abrasive grains in each of the first and second steps, that in the first step is sometimes called abrasive-grain-free chemical mechanical polishing if the polishing concentration of the first step is smaller by at least one figure, desirably at least 2 figures, than that of the second step.
The term “anticorrosive” means a chemical for preventing or suppressing the progress of polishing by CMP by forming an anticorrosive and/or hydrophobic protecting film on the metal surface and benzotriazole (BTA) is usually employed as the chemical (refer to Japanese Patent Application Laid-Open No. HEI 8-64594, for further details).
The term “conductive barrier layer” is usually a layer for preventing atoms or ions, which constitute an embedded interconnection material, from being transported (including, being diffused) and thereby having an adverse effect on an underlying element and it means a layer made of a conductive material having a comparatively higher conductivity than an insulating film and having diffusion-inhibiting properties, for example, a metal such as Ti, a metal nitride such as TiN, a conductive oxide or a conductive nitride.
The term “selective removal”, “selective polishing”, “selective etching” or “selective chemical mechanical polishing” means that having a selection ratio of at least 5.
The term “embedded interconnection” usually means an interconnection formed by an interconnection forming technique such as single damascene or dual damascene, more specifically, by embedding a conductive film inside of a groove or the like, which has been formed in an insulating film, and then removing an unnecessary portion of the conductive film on the insulating film.
With regards to the selection ratio, when a selection ratio of “A to B” (or “A relative to B”) is X, it means, if the case of polishing rate is taken, that the selection ratio becomes X according to the calculation of a polishing rate of A based on that of B.
The term “semiconductor integrated circuit device” as used herein means not only that formed over a single crystal silicon substrate but also that formed over an SOI (silicon on insulator) substrate, a substrate for the production of TFT (Thin Film Transistor) liquid crystals or the like unless otherwise specifically indicated. The term “wafer” means a single crystal silicon substrate (substantially disk-shape in general), SOS substrate, glass substrate, another insulating, semi-insulating or semiconductor substrate or a composite substrate thereof, which is employed for the fabrication of a semiconductor integrated circuit device.
As illustrated in FIG. 1, after formation of an element isolating groove 2 of about 350 nm deep is formed, by photolithography and dry etching, in a semiconductor substrate (which will hereinafter be called “substrate”) 1 having a specific resistance of about 1 to 10 Ωcm and being made of p-type single crystal silicon, a silicon oxide film 3 is deposited, by CVD, over the substrate 1 including the inside of the groove. The surface of the silicon oxide film 3 over the groove is then flattened by chemical mechanical polishing (CMP), followed by ion implantation of p-type impurities (boron) and n-type impurities (phosphorus) to the substrate 1, whereby a p-type well 4 and an n-type well 5 are formed. Then, by steam oxidation of the substrate 1, a gate oxide film 6 of about 6 nm thick is formed over the surface of each of the p-type well 4 and n-type well 5.
As illustrated in FIG. 2, a gate electrode 7 having a low-resistance polycrystalline silicon film, WN (tungsten nitride) film and W (tungsten) film is formed over the gate oxide film 6. The polycrystalline silicon film can be formed by CVD, while the WN and W films can be formed by sputtering. The gate electrode 7 is formed by patterning of these deposited films. The gate electrode 7 may be formed by the laminate film of a low-resistance polycrystalline silicon film and W silicide film. After the formation of the gate electrode, n− type semiconductor region 11 of a low impurity concentration and a p− type semiconductor region 12 of a low impurity concentration are formed in the p-type well 4 and n-type well 5, respectively, by ion implantation.
As illustrated in FIG. 8, after deposition, by sputtering, of a thin TiN (titanium nitride) film 45 of about 50 nm thick over the silicon oxide film 39 including the insides of the interconnection grooves 40 to 44, a Cu film 46 sufficiently thicker (ex. about 800 nm) than the depth of each of the interconnection grooves 40 to 44 is deposited over the TiN film 45 by sputtering. Then, the substrate 1 is heat treated in a non-oxidizing atmosphere (ex. hydrogen atmosphere) of about 475° C. to cause reflow of the Cu film 46, whereby the Cu film 46 is fully embedded inside of each of the interconnection grooves 40 to 44.
Here, the Cu film 46 is formed by sputtering and it is embedded in the groove by reflow. Alternatively, a thin Cu film can be formed by sputtering, followed by the formation. of another Cu film corresponding to the Cu film 46 by plating.
Accordingly, when a Cu interconnection is formed inside of each of the interconnection grooves 40 to 44, it is necessary to dispose a barrier layer which can suppress diffusion of Cu between the silicon oxide film 39 and Cu film 46 and at the same time, has high adhesion to an insulating material. Furthermore, when the Cu film 46 is embedded inside of each of the interconnection grooves 40 to 44 by the reflow sputtering method as described above, the barrier layer is required to have properties to improve the wetness of the Cu film 46 upon reflow.
High melting-point metal nitrides, such as TiN, WN and: TaN (tantalum nitride), which hardly react with Cu are suited as such a barrier layer. It is also possible to use as the barrier layer a high-melting point metal nitride added with Si (silicon) or a high-melting-point metal such as Ta, Ti, W or TiW alloy which hardly reacts with Cu.
As illustrated in FIG. 12, it is possible to prevent the surface of the substrate 1 during storage from being. exposed to an illumination light by forming the immersion treatment part (wafer storing part) 150, which serves to prevent surface drying of the substrate 1 after completion of the corrosion treatment, to have a light shading structure. By this structure, generation of a short-circuit current due to the photovoltaic effect can be prevented. The immersion treatment part 150 is formed to have a light shading structure by covering the immersion tank (storage container) with a shade sheet or the like, thereby reducing the illuminance inside of the immersion tank (storage container) to 500 lux or less, preferably 300 lux or less, more preferably 100 lux or less.
As illustrated in FIG. 13, the substrate 1 may be carried into the drying treatment part rightly after the polishing treatment, in other words, right before the initiation of the electrochemical corrosion due to the oxidizing agent in the polishing slurry left on the surface of the substrate and the water content in the polishing slurry may be removed by forced drying. The CMP apparatus 200 shown in FIG. 13 is equipped with a loader 220 for accommodating a plurality of substrates 1 each having a Cu-film-formed surface, a polishing treatment part 230 for polishing and flattening the Cu film, thereby forming an interconnection, a drying treatment part 240 for drying the surface of the substrate 1 after completion of the polishing, a post-washing part 250 for post-washing the substrate 1 and an unloader 260 for accommodating therein a plurality of the substrates 1 after completion of the post-washing. According to the Cu interconnection forming process using this CMP apparatus 200, the substrate 1 subjected to polishing treatment in the polishing treatment part 230 is transferred to the drying treatment part 240 rightly after the polishing treatment, in other words, rightly before the initiation of the electrochemical corrosion reaction due to the oxidizing agent in the polishing slurry left on the surface and in the drying treatment part, the water content in the polishing slurry is removed by forced drying. Then, the substrate 1 under a dried condition is transferred into the post-washing treatment part 250 and after the post-washing treatment, it is rinsed with pure water, spin-dried and then accommodated in the unloader 260. In this case, the surface of the substrate 1 is kept drying during the time just after the polishing treatment to the initiation of the post-washing so that the initiation of the electrochemical corrosion is inhibited, which makes it possible to prevent the corrosion of the Cu interconnection effectively.
The chambers 302 a,302 b can be evacuated to make their insides highly vacuum and a treating gas and high-frequency electric power are fed from a gas port 315. The treating gas is fed to the vicinity of the substrate 1, passing through the mesh-like electrode 309. The treating gas is discharged from a vacuum manifold 316. The pressure is controlled by adjusting the gas flow rate and discharging rate. The high-frequency electric power is applied to the electrode 309, whereby a plasma is generated-between the susceptor 306 and electrode 309. The high-frequency electric power having, for example, a frequency of 13.56 MHz is employed.
The substrate 1, for example, having a size of 8 inches can be subjected to plasma treatment under the conditions of a treating pressure of 5.0 Torr, RF electric power of 600 W, substrate temperature of 400° C. and ammonia flow rate of 200 sccm and treating time of 10 seconds. The distance between any two adjacent electrodes is set at 600 mils. It is needless to say that the plasma treatment conditions are not limited to the above-described ones. According to the study of the present inventors, a reduction in the plasma damage can be attained by a higher pressure and a reduction in the scatter of TDDB and an increase in TDDB can be attained by a higher substrate temperature. It has-also been found that hillocks tend to appear on the surface of Cu at a higher substrate temperature, a lager RF electric power or a long treating time. In consideration of these findings and a difference in the conditions depending on the constitution of the apparatus, the plasma treatment conditions can be set within a range of from 0.5 to 6 Torr for treating pressure, 300 to 600 W for RF electric power, 350 to 450° C. for substrate temperature, 20 to 500 sccm for ammonia flow rate, 5 to 180 seconds for treating time and 300 to 600 mils for a distance between electrodes.
By the plasma treatment, as described above, on the surface of each of the Cu interconnections 46 a to 46 e and silicon oxide film 39, a thin nitride film of each of the underlying films can be formed over the surface of each of the Cu interconnections 46 a to 46 e and silicon oxide film, 39, whereby adhesion between the cap film (silicon nitride film) which will be described later, and each of the Cu interconnections 46 a to 46 e and silicon oxide film 39 can be improved, leading to a marked improvement in the TDDB characteristics.
The substrate 1 is then transported into the treating chamber 302 b by the robot 304. After the gate valve 305 of; the treating chamber 302 b is closed and the treating chamber 302 b is evacuated to a sufficient vacuum degree, a mixed gas of silane (SiH4), ammonia and nitrogen is introduced into the treating chamber 302 b and the pressure of the chamber is adjusted and maintained at a predetermined pressure. An electric field is applied to the electrode 309 from the high-frequency electric source to generate a plasma, whereby the silicon nitride film 47 (cap film) is deposited over the surface of each of the Cu interconnections 46 a to 46 e and silicon oxide film 39 as illustrated in FIG. 17. After a lapse of a predetermined time, the high-frequency electric field is terminated, whereby the plasma is stopped. The treating chamber 302 b is evacuated, followed by opening of the gate valve 305 and transportation of the substrate 1 into the load lock chamber 301 by the robot 304. The substrate 1 is then discharged into the cassette interface 303 by using the robot 304.
FIGS. 22 to 24.are graphs each illustrating the results of XPS analysis (X-ray Photo-electron Spectroscopy) on the surface of the Cu interconnection, wherein (a) and (c) are results of spectral analysis of Cu2p and (b) and (d) are those of N1s.
FIGS. 24(a) and 24(b) illustrate the analysis results of the surface of the Cu interconnection which has been oxidized, followed by ammonia plasma treatment. The peak of CuO almost disappears, while the peak of N1s appears strongly, which is presumed to owe to the reduction of the Cu surface and removal of oxygen, and at the same time, nitriding of the Cu surface. For comparison, the surface of the oxidized Cu interconnection subjected to hydrogen thermal treatment at 350° C. was analyzed. The results are shown in FIGS. 24(c) and 24(d). When FIG. 24(c) is compared with FIG. 24(a) concerning the peak of Cu2p, hydrogen thermal treatment is more reducing, because FIG. 22(a) shows the Cu interconnection in a more as-deposited state. Judging from that N1s peak is hardly observed, the Cu surface is only reduced by the hydrogen thermal treatment.
From the above-described results, it has been found. that the surface of each of the Cu interconnections 46 a to 46 e has been reduced and at the same time, a nitride film has been formed on the surface. This nitride layer is considered to serve to suppress formation of copper silicide by preventing the reaction between copper and silane contained in the raw material gas upon deposition of the silicon nitride film after ammonia plasma treatment. Prevention of silicide formation is presumed to suppress an increase in the interconnection resistance.
In FIG. 25(b), a broad peak is observed on the lower energy side (at 102 eV) of hydrogen plasma treatment (Profile D), which is presumed to owe to the formation of an Si—H bond on the surface of the silicon oxide film by the hydrogen plasma treatment.
In FIG. 25(a), peaks of the ammonia plasma treatment (Profile E) and nitrogen plasma treatment (Profile F) at 105 eV are broad on the lower energy side and are therefore asymmetrical. The peak at the asymmetrical part (103.5 eV) is presumed to result from an Si—O—N bond. The surface of the silicon oxide film is considered to be nitrided by the ammonia plasma treatment and nitrogen plasma treatment. The comparison between FIGS. 25(a) and 25(b) suggests that the nitriding is stronger on the surface portion. The nitriding due to ammonia plasma treatment and nitrogen plasma treatment can also be confirmed from FIG. 25(c).
It is apparent from FIG. 25(e) that carbon can hardly be detected in the hydrogen plasma treatment (Profile D), suggesting that organic matters on the surface have been removed by hydrogen plasma treatment. The peak at 289 eV after CMP (Profile C) is presumed to result from a C—O bond. A slurry is considered to remain after CMP.
FIGS. 26(a), 26(b), 26(c) and 26(d) are graphs illustrating the measurement results of the mass number 41 (Ar—H), mass number 27 (C2H3), mass number 57 (C4H9) and mass number 59 (C3H7O), respectively. FIGS. 27(a), 27(b), 27(c) and 27(d) are graphs illustrating the measurement results of the mass number 28 (Si, C2H4), mass number 44 (SiO, C3H6), mass number 29 (SiH, C2H5) and mass number 31 (SiH3), respectively.
It has been revealed from FIG. 26(a) that there is almost no difference in the hydrogen release amount by the plasma treatment, but the release temperature of the hydrogen plasma treatment (Profile D) is 520° C. which is lower than another case (560° C.).
FIGS. 26(a), 26(b) and 26(c) suggest the release of organic matters in each process, while FIGS. 27(a) to 27(d) suggest the existence of a peak which does not result from the release of organic matters. The peaks of FIGS. 27(a). to 27(d) existing within a range of from 300 to 400° C. are presumed to result from Si, SiO, SiH, SiH3, respectively. According to the comparison among these drawings, release of SiO is observed in each of the hydrogen, ammonia and nitrogen plasma treatments, but release of each of SiH and SiH3 is hardly observed in the ammonia plasma treatment. In other words, an Si—O—N bond is formed by the ammonia plasma treatment and release occurs easily at a relatively low energy. The energy necessary for release is the highest in the nitrogen plasma treatment, while it is almost the same in the hydrogen plasma treatment and ammonia plasma treatment.
The above-described results indicate that an Si—OH or Si—O— bond which will be a cause for the dangling bond on the surface of the silicon oxide film is terminated as a weak Si—O—N bond by the ammonia plasma treatment. Upon formation of a silicon nitride film after the ammonia plasma treatment, the Si—O—N on the very surface is released and the Si—O bond of the bulk and Si—N of the silicon nitride film form a strong bond, whereby a continuous interface is formed. This is presumed to be a mechanism for improving the adhesion at the interface. Without the ammonia plasma treatment, on the other hand, the surface of the silicon oxide film rich in an Si—OH bond and ammonia which is a raw material gas of the silicon nitride film would undergo condensation, leading to the formation of a number of Si—O— bonds, thereby causing a dangling bond. If a number of dangling bonds exist on the interface between the silicon oxide film and silicon nitride film, a leak path is inevitably formed there, which will be a cause for leak current between interconnections and, in turn, dielectric break.
In addition, resistance of the Cu interconnection can be reduced according to this embodiment. FIG. 30 illustrates the measuring results of the resistance of each of the Cu interconnections subjected to various treatments. The resistance without treatment (without plasma treatment) or after ammonia plasma treatment is significantly low compared with that after another treatment (hydrogen plasma treatment, hydrogen annealing or nitrogen plasma treatment). FIGS. 31 and 32 are each a TEM photograph of the interface between the Cu interconnection and cap film (silicon nitride film) subjected to one of these treatments. Nothing particular can be observed from the interface free of treatment or after ammonia plasma treatment (FIG. 31), while a copper silicide (CuSi) layer has been formed on the interface subjected to hydrogen annealing or nitrogen plasma treatment (FIG. 32). This silicide layer is presumed to cause an increase in the resistance. Such a silicide layer is formed by the reaction with a silane gas upon formation of the silicon nitride film. By the ammonia treatment, however, a markedly thin nitride film is formed on the Cu surface and it functions as a blocking layer against the silicide formation. It is presumed that in the case of hydrogen annealing or the like, however, only the reduction of the copper surface causes exposure of the active Cu surface, thereby accelerating reaction with silicon, resulting in a tendency to form a silicide layer. In the case of hydrogen plasma treatment (FIGS. 32(c), 32(f)), something is formed on the interface. It is not always the case so that the degree of silicide formation is presumed to be small in the case of hydrogen plasma treatment. In FIGS. 31 and 32, in addition to the TEM photographs (FIGS. 31(a) and 31(b), FIGS. 32(a) to 32(c)), corresponding traced drawings (FIGS. 31(c) and 31(d), FIGS. 32(d) to 32(f)) are shown below the, TEM photographs for reference.
Based on the above-described analysis results, the following model can be indicated as a deteriorating mechanism of the TDDB characteristics. Without ammonia treatment of the present embodiment, copper oxide (CuO) is formed on the surface of the Cu interconnection and upon formation of a cap film (silicon nitride film 47), copper silicide is formed. Such copper oxide or copper silicide is ionized easier than pure copper. Ionized copper is drifted by an electric field between interconnections and diffused into the insulating film between interconnections. The interface between the insulating film (silicon oxide film 39) having copper interconnections embedded therein and cap film (silicon nitride film 47) is discontinuous due to many dangling bonds formed thereon and is therefore poor in adhesion when it is free from ammonia treatment of this embodiment. Such dangling bonds serve to accelerate diffusion of copper ions so that copper ions are drifted and diffused along the interface. In other words, a leak path is formed on the interface between the interconnections. Owning to the leak action for long hours and, in addition, thermal stress by electric current, an increase of leak current passing through the leak path is accelerated, leading to breakdown (TDDB).
The above-described analysis suggests that TDDB can also be improved by hydrogen plasma treatment. Described specifically, by the hydrogen plasma treatment, the Cu surface is reduced and a dangling bond such as Si—O— or Si—OH which will be a cause therefor is terminated as Si—H. Upon formation of the silicon nitride film, the Si—H having a weak bond surface is released and substituted by Si—N. As a result, a continuous interface is formed between the silicon oxide film and silicon nitride film. The interconnection resistance, however, increases as described above. FIG. 33 is a graph illustrating the data of the TDDB after hydrogen plasma treatment. For reference, Line Ref (without treatment) and Line A (ammonia plasma treatment) are shown. The graph clearly shows that the hydrogen plasma treatment (Line C) brings about a marked improvement in TDDB. Relaxation of the plasma damage is expected in the hydrogen plasma treatment so that the use of a material, as a cap film, which is replaceable for the silicon nitride film and at the same time, does not form a reaction product with Cu is particularly effective. The nitrogen plasma treatment (Line D), on the contrary, lowers TDDB, which is presumed to occur owing to an increase in the deposit of an organic matter by the nitrogen plasma treatment as is apparent from FIG. 26 or FIG. 27.
Downstream of the polishing treatment part 401, a post-washing part 402 is disposed for scrub washing of the surface of the substrate 1 which has finished preliminary washing. The post-washing part 402 is equipped with a loader 408, first washing part 409A, second washing part 409B, spin drier 410 and unloader 411. The post-washing part 402 is surrounded by a shading wall 430 to prevent the surface of the substrate 1 from being exposed to light during washing and its inside is dark with an illuminance of 180 lux, preferably 100 lux or less. This shading wall is disposed because, if the substrate 1 having a polishing liquid attached to the surface thereof is exposed to light under wet condition, a short-circuit current passes through the pn junction by the photoelectromotive force of silicon, and Cu ions are dissociated from the surface of the Cu interconnection connected to the p side (+ side) of the pn junction, which causes corrosion of the interconnection.
As illustrated in FIG. 35, the first disk 403A is turned and driven within a horizontal plane by a driving mechanism 412 disposed below the disk. The first disk 403A has, on the upper surface thereof, a polishing pad 413 which has been formed by uniformly adhering a synthetic resin such as polyurethane having a number of pores. A wafer carrier 415 turned and driven vertically within a horizontal plane by a driving mechanism 414 is disposed above the first disk 403A. The substrate 1 is supported by a wafer chuck 416 and retainer ring 417, each disposed at the lower end of the wafer carrier 415, with its main surface (a surface to be polished) down; and is pressed against the polishing pad 413 under a predetermined load. Between the surface of the polishing pad 413 and the surface of the substrate 1 to be polished, a slurry (polishing liquid). S is fed through a slurry feeding pipe 418, whereby the surface of the substrate 1 to be polished is chemically and mechanically polished. Above the first disk 403A, a dresser 420 turned and driven vertically within a horizontal plane by a driving mechanism 419 is disposed. The dresser 420 has, at the lower end thereof, a base having thereon electrodeposited diamond particles, by which the surface of the polishing pad 413 is periodically shaven in order to prevent clogging with the abrasive grains. The constitution of the second disk 403B is almost similar to that of the first disk 403A except that it has two slurry feeding pipes 418 a, 418 b. For the formation of the Cu-interconnection by the above-described CMP apparatus 400, the substrate 1 accommodated in the loader 406 is transported to the polishing treatment part 401 by the rotary arm 405, followed by chemical mechanical polishing (abrasive-grain-free chemical mechanical polishing) (CMP of the first step) using an abrasive-grain-free slurry, as illustrated in FIG. 36, on the first disk 403A to remove the Cu film 46 outside the interconnection grooves 40 to 44 (FIG. 37).
The term “abrasive-grain-free chemical mechanical polishing” as used herein means chemical mechanical polishing using a polishing liquid (slurry) containing abrasive grains made of powders such as alumina and silica in an amount less than 0.5%. As the content of the abrasive grains in the polishing liquid, an amount less than 0.1 wt. % is preferred, with that less than 0.01 wt. % being more preferred.
The TiN film 45 outside the interconnection grooves 40 to 44 and the Cu film 46 which has partially remained thereover are removed by transferring the substrate 1 from the first disk 403A to the second disk 403B and subjecting it to chemical mechanical polishing (abrasive-grain-using chemical mechanical polishing) (CMP of the second step) using an abrasive-grain-containing polishing liquid (slurry). The term “abrasive-grain-using chemical mechanical polishing” as used herein means chemical mechanical polishing with a polishing liquid containing abrasive grains made of powders such as alumina and silica in an amount not less than 0.5 wt. %. In this embodiment, a polishing liquid obtained by mixing 5 vol. % of hydrogen peroxide, 0.03 wt. % of citric acid and 0.5 wt. % of abrasive grains with pure water is used, but it is not limited thereto. This polishing liquid is fed to the polishing pad 413 of the second disk 403B through the above-described slurry feeding pipe 418 a. In abrasive-grain-using chemical mechanical polishing, the Cu film 46 which has partially remained over the TiN film 45 is removed, followed by the removal of the TiN film 45 outside the interconnection grooves 40 to 44. The polishing of the surface of the Cu film 46 inside of the interconnection grooves 40 to 44 is suppressed by polishing under the conditions to give a polishing selection ratio of the Cu film 46 to the TiN film (barrier layer) not greater than that for the above-described abrasive-grain-free chemical mechanical polishing, for example, not greater than 3.
The polishing is conducted using a polishing pad “IC1400” produced by Rodel Inc., for example, under the conditions of a load of 120 g/cm2, wafer rotational number of 30 rpm, disk rotational number of 25 rpm and slurry flow rate of 150 cc/min. The amount corresponding to the film thickness of the TiN film 45 is polished and the end point of polishing is controlled by the time calculated from the thickness and the polishing rate of the TiN film 45.
The above-described selective chemical mechanical polishing is conducted using a mixture of a polishing. liquid, as used in the above-described abrasive-grain-using chemical mechanical polishing, which contains at least 0.5 wt. % of abrasive grains; and an anticorrosive. The anticorrosive is a chemical for preventing or controlling the progress of polishing by forming an anticorrosive protective film on the surface of the Cu film 46. Examples include BTA derivatives such as benzotriazole (BTA) and BTA carboxylic acid, dodecyl mercaptan, triazole and tolyl triazole. A particularly stable protective film is formed by the use of BTA.
On the surface of the substrate 1 having Cu-embedded interconnections 46 a to 46 e formed thereon, the slurry residue containing particles such as abrasive grains or metal particles such as Cu oxide has been attached. In order to remove this slurry residue, the substrate 1 is washed with BTA-containing pure water in the clean station. 404 as shown in FIG. 34. At this time, megasonic washing wherein high-frequency vibration of 800 kHz or greater is applied to the washing liquid to release the slurry residue from the surface of the substrate 1 may be used in combination. Then, the substrate 1, which is maintained under a wet condition to prevent surface drying, is transported from the polishing treatment part 401 to the post-washing part 402. In the first washing part 409A, the substrate 1 is subjected to scrub washing with a washing liquid containing 0.1 wt. % of NH4OH, followed by scrub washing with pure water in the second washing part 409B. As described above, the post-washing part 402 is covered with a shading wall 430 to prevent corrosion of the Cu interconnections 46 a to 46 e due to exposure of the surface of the substrate 1 to light during washing.
The steps after the scrub washing are similar to those of Embodiment 1. FIG. 43 illustrates the whole flow chart of the above-described formation process of the Cu interconnections 46 a to 46 e. According to this embodiment, the TDDB characteristics can be improved more than that of Embodiment 1. FIG. 44 is a graph illustrating TDDB and that of this embodiment is shown by Line E. For reference, TDDB (Line Ref) without treatment and that (Line A) subjected to abrasive-grain-using chemical mechanical polishing (Embodiment 1) are shown together. The TDDB is improved, as shown in Line F, only by the abrasive-grain-free chemical mechanical polishing without ammonia plasma treatment. Such an improvement in TDDB is presumed to occur because damage to the silicon oxide film can be reduced in the case of the abrasive-grain-free CMP. In the case of the abrasive-grain-using CMP, on the other hand, the slurry contains abrasive grains (such as alumina) having a particle size (secondary particle size) of 2 to 3 μm. These abrasive grains make micro scratches and cause a damage to the surface of the silicon oxide film 39. The abrasive-grain-free slurry does not contain abrasive grains or contains, if any, a very small amount or them so that the damage can be lessened to the minimum. The improvement in TDBB is presumed to be brought about because of the above-described reasons.
Alternatively, citric acid washing can be employed instead of HF washing. For the citric acid washing, brush scrub washing can be employed and it can be conducted under: the conditions of a citric acid concentration of 5% and washing time for 45 seconds.
By the HE or citric acid washing, the surface layer damaged by CMP or the like can be removed, which improves the TDDB characteristics. FIG. 46 is a graph illustrating TDDB, wherein Line H shows the data of citric acid washing, while Line I shows the data of HF washing, each according to this embodiment. For reference, the data without treatment (Line Ref) and that of Embodiment 1 (Line A) are shown on the same graph. As apparent from Line J. the TDDB characteristics show an improvement only by the HF washing without ammonia plasma treatment, which is presumed to result from an improvement in the properties of the interface by the removal of the damaged layer.
The silicon oxide film 505 of a low dielectric constant is made of a silicon oxide insulating film having a specific dielectric constant (ε) not greater than 3.0, for example, coating type insulating film such as an inorganic SOG film formed using hydrogen silsesquioxane as a raw material or an organic SOC film formed using tetraalkoxy silane and alkyl alkoxy silane as raw materials, or a fluorocarbon polymer film formed by the plasma CVD. Use of such a silicon oxide film having a low dielectric constant makes it possible to reduce the parasitic capacitance between interconnections, thereby avoiding the problem of delay between interconnections.
A connecting hole 507 is then opened as shown in FIG. 48(b) according to the pattern as shown in FIG. 48(a). Photolithography and etching are applied to the opening of the connecting hole 507. The silicon oxide film 505 of a low dielectric constant has a rough surface and contains many Si—OH bonds. Experience has revealed that the quality of the film formed over such a silicon oxide film or the condition of the interface therebetween are poor and that formation of a barrier film (titanium nitride) which will be described in the subsequent step over the silicon oxide film without any treatment leads to inferior TDDB characteristics. The exposed portion of the silicon oxide film 505 inside of the connecting hole 507 is therefore subjected to ammonia plasma treatment as described in Embodiment 1. Then, the Si—OH bonds on the surface are modified and converted into the Si—O—N bonds as described in Embodiment 1.
As illustrated in FIG. 49, a plug 508 made of titanium nitride and tungsten is formed in the connecting hole 507. Upon deposition of titanium nitride, an Si—O—N bond is released as in Embodiment 1, whereby the interface between titanium nitride and the silicon oxide film 50 of a low dielectric constant is improved and adhesion therebetween is heightened.
As illustrated in FIG. 53, after deposition of a TiN film 45 as thin as about 50 nm over the silicon oxide film 39 including the inside of each of the interconnection grooves 50 to 54, a Cu film 46 sufficiently thicker than the depth of each of the interconnection grooves 50 is formed over the TiN film 45. The interconnection grooves 50 to 54 which also serve as throuqh-holes have a larger aspect ratio than the above-described interconnection grooves 40 to 44, so that the TiN film 45 is deposited by the CVD. The Cu film 46 is deposited by repeating sputtering at least twice. Instead of sputtering, CVD, electroplating or electroless plating method can be adopted. The formation of the Cu film 46 by the plating method requires a step for forming a Cu seed layer below the interconnection grooves 50 to 54 by sputtering or the like.
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Homma et al., "Control of Photocorrosion in the Copper Damascene Process", Journal of the Electrochemical Society, 147 (3), 2000, pp. 1193-1198.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8105937Aug 13, 2008Jan 31, 2012International Business Machines CorporationConformal adhesion promoter liner for metal interconnectsUS8753975Feb 1, 2013Jun 17, 2014Globalfoundries Inc.Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting deviceUS8859419Feb 1, 2013Oct 14, 2014Globalfoundries Inc.Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting deviceUS9318436Aug 27, 2014Apr 19, 2016Globalfoundries Inc.Copper based nitride liner passivation layers for conductive copper structuresUS20040266185 *Jun 30, 2003Dec 30, 2004Texas Instruments IncorporatedMethod for reducing integrated circuit defectsUS20050239289 *Jun 23, 2005Oct 27, 2005Doke Nilesh SMethod for reducing integrated circuit defectsUS20100038789 *Aug 13, 2008Feb 18, 2010International Business Machines CorporationConformal adhesion promoter liner for metal interconnectsWO2014026287A1 *Aug 14, 2013Feb 20, 2014Powerdisc Development Corporation Ltd.Fuel cell components, stacks and modular fuel cell systems* Cited by examinerClassifications U.S. Classification438/622, 438/653, 257/E21.311, 438/643, 257/E21.582, 438/687, 257/E21.576, 257/E21.588, 257/E21.591, 438/637, 257/E21.304, 438/692, 257/E21.577, 257/E21.583International ClassificationH01L21/28, H01L21/768, H01L21/70, H01L21/3205, H01L23/532, H01L21/321, H01L21/3213, H01L21/02Cooperative ClassificationH01L21/76886, H01L21/76883, H01L21/32136, H01L21/76834, H01L21/7684, H01L21/76838, H01L21/02074, H01L21/3212, H01L2924/0002, H01L21/76882, H01L21/67115, H01L21/76826, H01L21/02063, H01L23/53238, H01L21/68792, H01L21/3185, H01L21/76829European ClassificationH01L21/02F4B2, H01L21/318B, H01L21/768B8P, H01L21/67S2H6, H01L21/768C4P, H01L21/768B10, H01L21/687S22, H01L21/768B10S, H01L21/321P2, H01L21/768C2, H01L23/532M1C4, H01L21/768C4E, H01L21/02F4D4, H01L21/768C8, H01L21/768CLegal EventsDateCodeEventDescriptionDec 11, 2003ASAssignmentOwner name: RENESAS TECHNOLOGY CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HITACHI, LTD.;REEL/FRAME:014244/0278Effective date: 20030912Jul 16, 2008FPAYFee paymentYear of fee payment: 4Aug 13, 2010ASAssignmentOwner name: RENESAS ELECTRONICS CORPORATION, JAPANFree format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:024864/0635Effective date: 20100401Owner name: NEC ELECTRONICS CORPORATION, JAPANFree format text: MERGER;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:024879/0190Effective date: 20100401Jul 5, 2012FPAYFee paymentYear of fee payment: 8Jul 21, 2016FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services