Source: http://www.google.com/patents/US20050145941?dq=6317900
Timestamp: 2016-06-27 08:30:15
Document Index: 395398033

Matched Legal Cases: ['art 350', 'art 450', 'art 350', 'art 350', 'art 350', 'art 350', 'art 350', 'art 350', 'art 350', 'art 350', 'art 350', 'art 450', 'art 450', 'art 450', 'art 450', 'art 450', 'art 450']

Patent US20050145941 - High performance strained silicon FinFETs device and method for forming same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET....http://www.google.com/patents/US20050145941?utm_source=gb-gplus-sharePatent US20050145941 - High performance strained silicon FinFETs device and method for forming sameAdvanced Patent SearchPublication numberUS20050145941 A1Publication typeApplicationApplication numberUS 10/751,916Publication dateJul 7, 2005Filing dateJan 7, 2004Priority dateJan 7, 2004Also published asUS7705345, WO2005067677A2, WO2005067677A3Publication number10751916, 751916, US 2005/0145941 A1, US 2005/145941 A1, US 20050145941 A1, US 20050145941A1, US 2005145941 A1, US 2005145941A1, US-A1-20050145941, US-A1-2005145941, US2005/0145941A1, US2005/145941A1, US20050145941 A1, US20050145941A1, US2005145941 A1, US2005145941A1InventorsStephen Bedell, Kevin Chan, Dureseti Chidambarrao, Silke Christiansen, Jack Chu, Anthony Domenicucci, Kam-Leung Lee, Anda Mocuta, John Ott, Qiqing OuyangOriginal AssigneeInternational Business Machines CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (172), Classifications (18), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetHigh performance strained silicon FinFETs device and method for forming same
US 20050145941 A1Abstract
A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET. Images(10) Claims(36)
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention generally relates to a semiconductor device, and more particularly to a high performance strained silicon, Fin field effect transistor (FinFET) device. [0003] 2. Description of the Related Art [0004] Fin FETs are considered promising candidates for complementary metal oxide semiconductor (CMOS) device scaling (e.g., see Hu Chenming et al., U.S. Pat. No. 6,413,802 entitled “FinFET transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture”). [0005] Indeed, FinFETs are a type of double gate structure which offer high silicon current delivery than single gate devices. Further, FinFETs improve the short channel characteristics of the device and are easier to scale down from. [0006] The fabrication of a FinFET is generally simpler than most other double-gate structures, although the channel thickness control is problematic in most known approaches (e.g., see U.S. Pat. No. 6,413,802; Yang-Kyu Choi et al., “Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era”, Solid-State Electronics, 46, p. 1595, (2002)). [0007] Additionally, to increase the device current drive, high carrier mobility is required. MOSFETs with high carrier mobility are made by fabricating the device on strained silicon (e.g., see K. Rim et al. “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET's”, IEEE Trans. Electron Devices, 47 (7), p. 1406, (2000)). A MOSFET fabricated in 001-oriented silicon under biaxial tensile strain exhibits higher carrier mobilities than a conventional MOSFET (e.g., see K. Rim, J. L. Hoyt, J. F. Gibbons, “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET's”, IEEE Trans. Electron Devices, 47 (7), p. 1406, (2000)). The higher carrier mobility leads to a higher current drive and thus a faster/shorter switching time is obtained. [0008] The “strained” silicon film is typically formed by growing an epitaxial silicon layer on top of a strain-relaxed, graded SiGe layer structure (e.g., see P. M. Mooney, Materials Science and Engineering Reports R17, p. 105 (1996) and references therein). [0009] As known, Ge has a lattice constant which is approximately 4% larger than the lattice constant of Si, and the lattice constant of the alloy, Si1-xGex, increases approximately linearly with increasing Ge mole fraction, x, of the alloy. Since these semiconductors have cubic symmetry, the in-plane and out-of-plane lattice constants are equal in unstrained crystalline films or bulk crystals. [0010] Herein, “strained” (or fully strained) means that the in-plane lattice constant of the SiGe layer, which is larger than that of the Si substrate, is compressed so that it matches that of the Si substrate, thereby resulting in a corresponding expansion of the out-of-plane lattice parameter such that the in-plane and out-of-plane lattice parameters of the SiGe layer are no longer equal. A SiGe layer is partially strained or partially relaxed when the in-plane lattice parameter is larger than that of Si, but still smaller than the out-of-plane SiGe lattice parameter. The SiGe is fully “relaxed” or unstrained when the in-plane and out-of-plane lattice parameters are equal. For Si under biaxial tensile strain (e.g., when it is grown epitaxially on a partially or fully relaxed SiGe layer), the in-plane lattice parameter is larger than the out-of-plane lattice parameter. [0011] Thus, strained silicon is useful for increasing the performance over conventional silicon devices. Indeed, a strained silicon (e.g., tensilely strained or compressively strained) may offer 1.5 times the carrier mobility over conventional silicon devices. [0012] The conventional techniques for making strained silicon are applicable for planar devices such as the conventional MOSFET. Examples for such techniques are a graded buffer SiGe layer (e.g., see P. M. Mooney, Materials Science and Engineering Reports R17, p. 105 (1996) and references cited therein), and the relaxation by ion implantation and anneal (e.g., see U.S. Pat. No. 6,593,625 by S. H. Christiansen et al., entitled “Relaxed SiGe layers on Si or silicon on insulator substrates by ion implantation and thermal annealing”). [0013] Thus, strained Si complementary metal oxide semiconductor (CMOS) devices with strained Si channel on a relaxed Si1-xGex buffer layer are known to offer better device performance over conventional Si CMOS because of the enhancement in both channel electron and hole mobilities in the strained silicon film. [0014] That is, a MOSFET fabricated in 001-oriented silicon under biaxial tensile strain exhibits higher carrier mobilities than a conventional MOSFET (e.g., see K. Rim, J. L. Hoyt, J. F. Gibbons, “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET's”, IEEE Trans. Electron Devices, 47 (7), p. 1406, (2000)). The higher carrier mobility leads to a higher current drive and thus a faster/shorter switching time is obtained. [0015] The “strained” silicon film is typically formed by growing an epitaxial silicon layer on top of a strain-relaxed, graded SiGe layer structure (e.g., see P. M. Mooney, Materials Science and Engineering Reports R17, p. 105 (1996) and references therein). [0016] A thin SiGe layer grown epitaxially on a Si(001) substrate will be strained, with the in-plane lattice parameter matching that of the Si substrate. In contrast, when a thicker layer is grown, the strain will be relaxed by the introduction of dislocations, specifically 600 misfit dislocations when the lattice mismatch is <2%. The thicker the layer, the more dislocations present and the more relaxed the SiGe layer is. The misfit dislocation is the boundary of a missing plane of atoms. It is typically a half loop, with a misfit segment running parallel to the SiGe/Si interface terminating in threading arms that go the wafer surface. The presence of the misfit dislocation creates an atomic step at the wafer surface. Strain relaxation by the introduction of crystal defects is known as “plastic strain relaxation”. [0017] Plastic strain relaxation results in a rough surface that exhibits a cross hatch pattern, which raises surface roughness/topography issues as described below, and a threading dislocation density in the range of 105-108 cm−2 in the upper part of the relaxed SiGe layer and the strained Si film. The strain fields from the misfit dislocation network introduce so-called mosaic structure in the SiGe and Si layers, which is detected as a broadening of the x-ray rocking curve. Triple-axis x-ray diffraction measurements can distinguish mosaic broadening from other effects, such as a non-uniform SiGe lattice parameter or alloy composition, that can also cause a broadening of the x-ray rocking curve. The exact nature of the mosaic structure in the upper part of the SiGe film and the strained Si layer is determined by the arrangement of the misfit dislocations, which will vary depending on the SiGe layer structure and the epitaxial growth conditions used to fabricate the structure. [0018] Thus, such strained silicon channels improve and increase the silicon current delivery capability, and improve the short channel characteristics. Additionally, such strained silicon devices are easier to scale down from. Further, strained silicon is used to increase performance by making the channel strained (tensile), an increase of 1.5 times the mobility of conventional silicon can be achieved. [0019] However, such strained silicon channels have not been demonstrated for devices as small as 50 nm or less. [0020] As mentioned above, another conventional device is the FinFET, which has found advantageous use because of its double gate structure. That is, conventional devices have typically used a single gate structure. The FinFET uses a double gate structure, thereby to allow more control and to reduce power. [0021] However, for FinFET devices, strained silicon has been difficult to integrate due to the geometry of the fin and the gate and the fabrication process. [0022] Thus, prior to the present invention, there has been no effective method (nor structure resulting from the method), in which FinFET devices have been formed with strained silicon. Such a combination of strained silicon with a silicon FinFET would offer enhanced channel mobility and be substantially defect-free. SUMMARY OF THE INVENTION [0023] In view of the foregoing and other exemplary problems, drawbacks, and disadvantages of the conventional methods and structures, an exemplary feature of the present invention is to provide a method and structure in which a silicon FinFET device is formed having strained silicon under the gate. [0024] In a first aspect of the present invention, a Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form at least a fin of the FinFET. [0025] With the unique and unobvious exemplary aspects of the present invention, a new FinFET device (and method for forming the same) is provided with FIN device structure (typically below sub-50 nm in FIN width) made out of relaxed SixGe1-x on insulator (SGOI)) with strained Si epi on the sidewalls of the SixGe1-x FIN structures. [0026] With the invention, new processes are provided for forming the new FinFET device structures with strained Si sidewall. Thus, the invention provides a combination of strained silicon with a silicon FinFET. [0027] As a result, numerous advantages of the FinFETs device structures of the present invention accrue over the conventional FinFETs and other advanced double gate devices. [0028] First, the epitaxially strained Si on SixGe1-x FIN structures provide additional enhanced channel mobility over conventional all-silicon FinFET structures and this improves device performance over conventional all-silicon FINFET devices. [0029] Additionally, the epitaxially-strained Si on the sidewalls of the SixGe1-x FIN structures is less affected by threading defects that arise from the relaxed graded buffer layer, and which are always found in the conventional planar strained silicon CMOS devices. [0030] Thus, the invention results in much better yield in manufacturing over planar strained silicon CMOS devices. BRIEF DESCRIPTION OF THE DRAWINGS [0031] The foregoing and other exemplary purposes, aspects and advantages will be better understood from the following detailed description of exemplary embodiments of the invention with reference to the drawings, in which: [0032] FIG. 1 illustrates a device layout of a strained FinFET device 100 according to the present invention; [0033] FIG. 2 illustrates a cross-sectional view of the strained FinFET device of FIG. 1 in a gate area thereof according to the present invention; [0034] FIGS. 3A-3H illustrate a process for forming a strained FinFET 300 according to the present invention; [0035] FIG. 3I illustrates a flowchart 350 of the processing of FIGS. 3A-3H; [0036] FIG. 3J shows a graph illustrating a relationship of mobility vs. Ge content; [0037] FIGS. 4A-4E illustrate a process for forming a strained FinFET 400 according to the present invention; [0038] FIG. 4F illustrates a flowchart 450 of the processing of FIGS. 4A-4E; [0039] FIG. 5 illustrates schematically the lattice spacing distribution in different parts of the strained FinFET formed exemplarily of 16% relaxed SiGe layer on SiGe on insulator (SGOI); [0040] FIG. 6 is a transmission electron micrograph (TEM) which shows Si epitaxial growth on the sidewall of the rapid thermal chemical vapor deposition (RTCVD) with 20% Ge psuedomorphic SiGe step; [0041] FIG. 7 is a transmission electron micrograph (TEM) which shows Si epitaxial growth on the sidewall of the ultra high chemical vapor deposition (UHCVD) with 20% Ge 95% relaxed SiGe step; and [0042] FIGS. 8A-8D illustrate a convergent beam electron diffraction (CBED) for strain measurements in different regions (e.g., Regions 8A-8C shown in FIGS. 8B-8D respectively) of the SiGe buffer layer step structure with selective epitaxially grown silicon.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION [0043] Referring now to the drawings, and more particularly to FIGS. 1-8D, there are shown exemplary embodiments of the method and structures according to the present invention. Exemplary Embodiment [0044] Turning to FIG. 1, the device layout of a strained FinFET 100 according to the present invention is shown. [0045] As shown, the FinFET device 100 includes a Fin device structure (typically below sub-50 nm in Fin width) made out of relaxed silicon germanium (SixGe1-x) on insulator (SGOI)) with strained Si epitaxially formed on the sidewalls of the SixGe1-x FIN structures. [0046] In FIG. 1, the FinFET 100 includes a fin 101, formed adjacent a source and drain 102A, 102B. A gate 103 (e.g., preferably formed of polysilicon, but of course metal could be employed as would be known by one of ordinary skill in the art) is formed adjacent the fin 101. The FinFET 100 is formed on a silicon-on-insulator (SOI) layer 104 which can be formed of an oxide, nitride, etc. The SOI layer 104 is formed on a bulk silicon substrate 105. [0047] With the invention, processes have been developed to generate the new FINFET device structures with strained Si sidewalls. FIGS. 2-5 highlight the details of the invention, the inventive process development, and experimental results to demonstrate the successful fabrication of the strained Si sidewall structure according to the present invention, with the new processes and the existence of strain in the epitaxially grown Si using Convergent Beam Electron Diffraction (CBED) analysis in high resolution scanning transmission electron microscope. [0048] Turning to FIG. 2, a cross-section 200 of the gate area of the FinFET 100 of FIG. 1 with the cross-sectional view being shown along arrows II-II of FIG. 1. In FIG. 2, an SOI layer 204 is formed on a bulk silicon substrate 205. [0049] In the gate area, a fin 201 is formed of relaxed SiGe preferably having a composition of Ge within a range of about 20% to about 70% Ge, and preferably having a thickness in a range of about 50 nm to about 100 nm. [0050] On sidewalls of the relaxed SiGe fin 201, a strained silicon 208 is formed, via selective epitaxial growth. Preferably, the strained silicon sidewalls have a thickness of about 5 nm to about 20 nm. [0051] A gate oxide, preferably formed of silicon dioxide and preferably having a thickness of about 1 nm to about 5 nm, is formed adjacent the strained silicon sidewalls, and adjacent (e.g., over) the top of the relaxed SiGe fin 201. Instead of oxide, other materials could be employed such as HFO2 (e.g., a high K dielectric). [0052] A gate 203 (e.g., formed of polysilicon or metal) is formed over the gate oxide 207, over relaxed SiGe fin 201 and the strained silicon sidewalls 208, to complete the structure. [0053] In operation, voltage is supplied to the drain and source contacts. When voltage is applied to the gate and is above threshold voltage, current flows between the source and drain region of this fin connecting to the source and drain. Therefore, since the gate covers both sides of the fin, twice the amount of current flow between source and drain for the given gate voltage compared with the planar single gate device. [0000] First Exemplary Method [0054] Turning now to FIGS. 3A-3H and the flowchart 350 of FIG. 31, a process of forming a FinFET 300 according to the present invention is shown. [0055] First, in FIG. 3A (and step 355 of the flowchart 350 in FIG. 31), over a substrate (e.g., a silicon-on-insulator (SOI) layer 302 formed on a bulk silicon 301), a relaxed SiGe layer 303 is formed. Preferably, the thickness of the SiGe layer 303 is within a range of about 50 nm to about 100 nm. [0056] Preferably, the SiGe layer 303 is a graded layer formed by epitaxial growth. [0057] Additionally, the percentage of Ge in the SiGe layer is preferably within a range of about 20% to about 70%, and more preferably about 20% to about 40%. [0058] As the percentage of Ge is increased, the strain increases and the carrier mobility similarly increases. Thus, for a 20% composition of Ge in the SiGe layer, electron mobility will be increased about 1.8 times that of conventional silicon. For a 30% composition of Ge in the SiGe layer, electron mobility will be increased about 2.0 times that of conventional silicon, and for a 40% composition of Ge in the SiGe layer, mobility will be increased about 2.5 times that of conventional silicon. However, increasing the % of Ge about 40% generally will not increase the carrier mobility substantially any more, and thus a plateau is reached. FIG. 3J shows a graph illustrating a relationship of mobility vs. Ge content. [0059] In FIG. 3B (and step 360 of the flowchart 350 in FIG. 31), the relaxed SiGe layer is patterned and etched, preferably by a reactive ion etch (RIE) or the like. [0060] In FIG. 3C (and step 365 of the flowchart 350 in FIG. 31), a special low temperature CVD grown oxide 304 with a very thin sidewall (e.g., preferably having a thickness within a range of about 10 nm to about 20 nm) is deposited by CVD over the relaxed SiGe and exposed portions of the SOI layer 302. The oxide will be thinner on the sidewalls, but will be thicker (e.g., within a range of about 30 nm to about 50 nm) on the gate/top of the relaxed SiGe layer and the silicon-on-insulator layer. [0061] In FIG. 3D (and step 370 of the flowchart 350 in FIG. 31), as shown at reference numeral 305, the thin sidewall LTO is removed, for example, by wet chemical etch. The LTO formed over the exposed portions of the SOI layer 302 and the top surface of the relaxed SiGe 303 is left. As also shown, the LTO overhangs the sidewall. [0062] Then, in FIG. 3E (and step 375 of the flowchart 350 in FIG. 31), as shown at reference numeral 306, strained silicon is selectively epitaxially grown on the sidewall of the relaxed SiGe layer. Preferably, the strained silicon has a thickness of about 5 nm to about 20 nm. [0063] Then, in FIG. 3F (and step 380 of the flowchart 350 in FIG. 3I), the LTO 304 is removed from the top of the relaxed SiGe and from the SOI layer 302, preferably by a wet chemical etch. Thus, the selective epitaxial strained silicon is left on the sidewalls of the relaxed SiGe layer. [0064] Thereafter, in FIG. 3G (and step 385 of the flowchart 350 in FIG. 3I), a gate oxide 307 (e.g., such as SiO2 or HFO2, preferably having a thickness in a range of about 1 nm to about 5 nm) is formed conformally over the strained silicon sidewall and the top of the relaxed SiGe layer 303. [0065] Finally, in FIG. 3H (and step 390 of the flowchart 350 in FIG. 31), a gate, preferably formed of polysilicon or metal, and preferably having a thickness in a range of about 100 nm to about 150 nm, is formed over the structure, and a gate etch is performed. The gate etch also removes the thin gate oxide, as shown in FIG. 3H. It is noted that the source and drain are formed before the gate is formed. [0066] With the unique and unobvious exemplary aspects of the present invention, a new FinFET device (and method for forming the same) is provided with a FIN device structure (typically below sub-50 nm in FIN width) made out of a relaxed SixGe1-x on insulator (SGOI)) with strained Si epitaxially formed on the sidewalls of the SixGe1-x Fin structures. [0067] Thus, the first exemplary embodiment of the present invention forms a FINFET device structure with a strained Si sidewall. Hence, the invention provides a combination of strained silicon with a silicon FinFET. The epitaxially strained Si on the SixGe1-x Fin structure provides additional enhanced channel mobility over the conventional all-silicon FinFET structures, and improves device performance over conventional all-silicon FinFET devices. [0068] It is noted that as mentioned above, the SiGe layer 303 is a graded buffer layer, and will gradually become more and more relaxed in a direction away from the silicon surface of the SOI layer. [0069] That is, in a direction away from the silicon, the lattice of the SiGe will take the form of a SiGe lattice completely (e.g., as though the SiGe was formed as a bulk SiGe structure, assuming such a structure would be possible). Strain leads to a mismatch of the crystal plane. To make up for the strain, the structure attempts to compensate, and thereby dislocations and misfits are typically formed in the lattice cell, as described above. The dislocations and misfits result in threading defects. [0070] Such threading defects are problematic as they tend to propagate to the strained silicon and build up, thereby potentially damaging or destroying the device. [0071] However, the inventive structure using the FinFET, is less prone to such threading defects since the fin's width (SiGe and strained Si) is small (i.e., <0.1 μm). Thus, the inventive structure will have a smaller defect density than the conventional all-silicon, single gate devices. [0072] It is noted that while the invention discloses beginning with a relaxed substrate, this is not required. Indeed, one can obtain relaxed SiGe with strained sidewalls by starting with relaxed SiGe, or as a second option one can start with strained SiGe (e.g., so-called psuedomorphic structure), which will then self-relax when the SiGe fin width is less than 0.1 μm. Second Exemplary Embodiment [0073] A second exemplary embodiment, as shown in FIGS. 4A-4E, is advantageous as it allows the invention to minimize the number of mask steps. Indeed, it allows the invention to avoid a mask step since as shown and described below, there is a fin oxide hard mask above, and an oxide layer below, the relaxed SiGe layer. It is noted that thin silicon (˜5-10 nm) from the SOI is removed after the SiGe Fin RIE. [0074] As a result, the second exemplary embodiment provides a process which is automatically self-aligned, thereby providing a more simple and elegant method even for a small gate. Hence, this embodiment provides self-aligned masking for selective growth. Moreover, there is no need to remove the hard mask to dope the top of the structure, as the invention allows doping on the sides of the structure. [0075] Turning now to FIGS. 4A-4E and the flowchart 450 of FIG. 4F, a process of forming a FinFET 400 according to the present invention is shown. [0076] First, in FIG. 4A (and step 455 of the flowchart 450 in FIG. 4F), over a substrate (e.g., a silicon-on-insulator (SOI) layer 402 formed, for example, on a bulk silicon 401), a relaxed SiGe layer 403 is formed. Preferably, the thickness of the SiGe layer 43 is within a range of about 50 nm to about 100 nm. [0077] Preferably, the SiGe layer 403 is a graded layer formed by epitaxial growth. Additionally, as before, the percentage of Ge in the SiGe layer is preferably within a range of about 20% to about 70%, and more preferably about 20% to about 40%. [0078] On top of the relaxed SiGe layer 403, a fin hard oxide mask 404 is formed. The mask 404 may be formed from low temperature CVD oxide materials with a thickness of the mask being between about 30 nm to about 50 nm. [0079] In FIG. 4B (and step 460 of the flowchart 450 in FIG. 4F), the relaxed SiGe layer 403 and the fin oxide hard mask 404 are patterned and etched, preferably by a reactive ion etch (RIE) or the like. [0080] In FIG. 4C (and step 465 of the flowchart 450 in FIG. 4F), strained silicon 406 is selectively epitaxially grown on the sidewalls of the relaxed SiGe layer 403. Preferably, the strained silicon has a thickness of about 5 nm to about 20 nm. [0081] Then, in FIG. 4D (and step 470 of the flowchart 450 in FIG. 4F), a gate oxide 407 (e.g., such as SiO2 or HFO2, preferably having a thickness in a range of about 1 nm to about 5 μm) is deposited. [0082] Finally, in FIG. 4E (and step 475 of the flowchart 450 in FIG. 4F), a gate 408, preferably formed of polysilicon or metal, and preferably having a thickness in a range of about 100 nm to about 150 nm, is formed over the fin body structure, and a gate etch is performed, to complete the structure. It is again noted that the source and drain would be formed before the gate is formed. [0083] Thus, this aspect of the invention minimizes a number of mask steps, and specifically allows the invention to avoid a masking step since the hard mask 404 is provided above, and the SOI layer 402 is provided below, the relaxed SiGe layer 403. [0084] As a result, less steps are required, and the process is automatically self-aligned (e.g., no need for additional patterning or etching), thereby providing a more simple and elegant method even for a small gate width. Hence, this embodiment provides self-aligned masking for selective grown. Moreover, there is no need to remove the hard mask to dope the top of the structure, as the invention allows doping on the sides of the structure. [0085] FIG. 5 illustrates schematically the computed lattice spacing distribution in different parts of the stained FINFET formed exemplarily of 16% relaxed SiGe layer on SiGe on insulator (SGOI). [0086] Reference numeral 506 represents strained silicon epitaxially grown on the sidewalls of the SiGe (16%) fin, whereas reference numeral 510 represents that the epitaxial silicon is tensile strained along the Y-Z plane. The number 85-100% represents the degree of relaxation deduced from distribution. [0087] As shown in the experimental results of FIGS. 6-8D, the invention has been demonstrated to be very advantageous over the conventional all-silicon single gate structures. [0088] FIG. 6 is a transmission electron micrograph (TEM) 600 which shows at reference numeral 610 selective Si epitaxial growth on the sidewall of a psuedomorphic SiGe fin. The psuedomorphic SiGe is deposited by a RTCVD method. [0089] FIG. 7 is a transmission electron micrograph (TEM) 700 which shows selective Si epitaxial growth on the sidewall of a 20% Ge 95% relaxed SiGe fin. The SiGe fin is deposited by RTCVD. [0090] FIGS. 8A-8D illustrate a convergent beam electron diffraction (CBED) for strain measurements in different regions (e.g., Regions 8A-8C shown in FIGS. 8B-8D respectively) of the SiGe buffer layer structure with selective epitaxially grown silicon. [0091] Specifically, FIG. 8B shows that similar distinct high order Laue zone lines indicate that region B in the SiGe structure is relaxed and not strained. [0092] FIG. 8C shows that distinct high order Laue zone lines obtained with CBED in a relaxed region of the SiGe buffer layer. [0093] In FIG. 8D, the blurred Laue zone lines in region C in the SiGe indicate strain in this part of the SiGe. The strain in SiGe region C is induced by the strain in the selectively grown epitaxial Si layer with 2 dimensionally limited geometry. The two-dimensional limited geometry refers to small fin sidewall dimensions. [0094] Thus, as discussed above, with the unique and unobvious exemplary aspects of the present invention, a new FinFET device (and method for forming the same) is provided with a Fin device structure (typically below sub-50 nm in Fin width) made out of a relaxed SixGe1-x on insulator (SGOI)) with strained Si epitaxially formed on the sidewalls of the SixGe1-x Fin structures. [0095] The present invention provides many advantages over conventional FinFETs and other advanced double gate devices including that epitaxially strained Si on SixGe1-x Fin structures provide additional enhanced channel mobility over current all silicon FinFET structures and this improves device performance over conventional all-silicon FinFET devices. [0096] Additionally, the epitaxially strained Si on the sidewall of the SixGe1-x Fin structures is less affected by threading defects that arise from the relaxed graded buffer layer and which are always found in the planar strained silicon CMOS devices. Hence, this invention leads to much better yield in manufacturing over planar strained silicon CMOS devices. [0097] While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. [0098] Further, it is noted that, Applicant's intent is to encompass equivalents of all claim elements, even if amended later during prosecution. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS6413802 *Oct 23, 2000Jul 2, 2002The Regents Of The University Of CaliforniaFinfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufactureUS6475869 *Feb 26, 2001Nov 5, 2002Advanced Micro Devices, Inc.Method of forming a double gate transistor having an epitaxial silicon/germanium channel regionUS6593625 *Apr 3, 2002Jul 15, 2003International Business Machines CorporationRelaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealingUS6774390 *Feb 21, 2003Aug 10, 2004Kabushiki Kaisha ToshibaSemiconductor deviceUS6800910 *Dec 31, 2002Oct 5, 2004Advanced Micro Devices, Inc.FinFET device incorporating strained silicon in the channel regionUS6891229 *Apr 30, 2003May 10, 2005Freescale Semiconductor, Inc.Inverted isolation formed with spacers* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7105390Dec 30, 2003Sep 12, 2006Intel CorporationNonplanar transistors with metal gate electrodesUS7187059 *Jun 24, 2004Mar 6, 2007International Business Machines CorporationCompressive SiGe <110> growth and structure of MOSFET devicesUS7193279 *Jan 18, 2005Mar 20, 2007Intel CorporationNon-planar MOS structure with a strained channel regionUS7221032 *Feb 4, 2005May 22, 2007Kabushiki Kaisha ToshibaSemiconductor device including FinFET having vertical double gate structure and method of fabricating the sameUS7268058Jan 16, 2004Sep 11, 2007Intel CorporationTri-gate transistors and methods to fabricate sameUS7279375Jun 30, 2005Oct 9, 2007Intel CorporationBlock contact architectures for nanoscale channel transistorsUS7326634Mar 22, 2005Feb 5, 2008Intel CorporationBulk non-planar transistor having strained enhanced mobility and methods of fabricationUS7326656Feb 24, 2006Feb 5, 2008Intel CorporationMethod of forming a metal oxide dielectricUS7348284 *Aug 10, 2004Mar 25, 2008Intel CorporationNon-planar pMOS structure with a strained channel region and an integrated strained CMOS flowUS7358121Aug 23, 2002Apr 15, 2008Intel CorporationTri-gate devices and methods of fabricationUS7365401 *Mar 28, 2006Apr 29, 2008International Business Machines CorporationDual-plane complementary metal oxide semiconductorUS7368791Aug 29, 2005May 6, 2008Intel CorporationMulti-gate carbon nano-tube transistorsUS7402875Aug 17, 2005Jul 22, 2008Intel CorporationLateral undercut of metal gate in SOI deviceUS7427794May 6, 2005Sep 23, 2008Intel CorporationTri-gate devices and methods of fabricationUS7504678Nov 7, 2003Mar 17, 2009Intel CorporationTri-gate devices and methods of fabricationUS7514346Dec 7, 2005Apr 7, 2009Intel CorporationTri-gate devices and methods of fabricationUS7531393Mar 9, 2006May 12, 2009Intel CorporationNon-planar MOS structure with a strained channel regionUS7531437Feb 22, 2006May 12, 2009Intel CorporationMethod of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric materialUS7624192Nov 24, 2009Microsoft CorporationFramework for user interaction with multiple network devicesUS7679145 *Mar 16, 2010Intel CorporationTransistor performance enhancement using engineered strainsUS7714397Jul 25, 2006May 11, 2010Intel CorporationTri-gate transistor device with stress incorporation layer and method of fabricationUS7736956Mar 26, 2008Jun 15, 2010Intel CorporationLateral undercut of metal gate in SOI deviceUS7777250Aug 17, 2010Taiwan Semiconductor Manufacturing Company, Ltd.Lattice-mismatched semiconductor structures and related methods for device fabricationUS7781771Aug 24, 2010Intel CorporationBulk non-planar transistor having strained enhanced mobility and methods of fabricationUS7799592Sep 21, 2010Taiwan Semiconductor Manufacturing Company, Ltd.Tri-gate field-effect transistors formed by aspect ratio trappingUS7820513Oct 28, 2008Oct 26, 2010Intel CorporationNonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabricationUS7825481Dec 23, 2008Nov 2, 2010Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabricationUS7858481Jun 15, 2005Dec 28, 2010Intel CorporationMethod for fabricating transistor with thinned channelUS7859053Jan 18, 2006Dec 28, 2010Intel CorporationIndependently accessed double-gate and tri-gate transistors in same process flowUS7871876Jan 18, 2011International Business Machines CorporationMethod of forming a dual-plane complementary metal oxide semiconductorUS7875958Sep 27, 2007Jan 25, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Quantum tunneling devices and circuits with lattice-mismatched semiconductor structuresUS7879675Feb 1, 2011Intel CorporationField effect transistor with metal source/drain regionsUS7893506Feb 22, 2011Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabricationUS7898040 *Mar 1, 2011Infineon Technologies AgDual gate FinFETUS7898041Sep 14, 2007Mar 1, 2011Intel CorporationBlock contact architectures for nanoscale channel transistorsUS7902014Jan 3, 2007Mar 8, 2011Intel CorporationCMOS devices with a single work function gate electrode and method of fabricationUS7915167Mar 29, 2011Intel CorporationFabrication of channel wraparound gate structure for field-effect transistorUS7960794Jun 14, 2011Intel CorporationNon-planar pMOS structure with a strained channel region and an integrated strained CMOS flowUS7989280Dec 18, 2008Aug 2, 2011Intel CorporationDielectric interface for group III-V semiconductor deviceUS8067818Nov 24, 2010Nov 29, 2011Intel CorporationNonplanar device with thinned lower body portion and method of fabricationUS8071983May 8, 2009Dec 6, 2011Intel CorporationSemiconductor device structures and methods of forming semiconductor structuresUS8084818Jan 12, 2006Dec 27, 2011Intel CorporationHigh mobility tri-gate devices and methods of fabricationUS8173551May 8, 2012Taiwan Semiconductor Manufacturing Co., Ltd.Defect reduction using aspect ratio trappingUS8183627May 22, 2008May 22, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Hybrid fin field-effect transistor structures and related methodsUS8183646May 22, 2012Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabricationUS8193567Dec 11, 2008Jun 5, 2012Intel CorporationProcess for integrating planar and non-planar CMOS transistors on a bulk substrate and article made therebyUS8202780Jul 31, 2009Jun 19, 2012International Business Machines CorporationMethod for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regionsUS8216951Dec 20, 2010Jul 10, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Quantum tunneling devices and circuits with lattice-mismatched semiconductor structuresUS8237151Jan 8, 2010Aug 7, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Diode-based devices and methods for making the sameUS8253211Aug 28, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor sensor structures with reduced dislocation defect densitiesUS8268709Sep 18, 2012Intel CorporationIndependently accessed double-gate and tri-gate transistors in same process flowUS8273626Sep 29, 2010Sep 25, 2012Intel CorporationnNonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabricationUS8274097Sep 25, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Reduction of edge effects from aspect ratio trappingUS8294180Mar 1, 2011Oct 23, 2012Intel CorporationCMOS devices with a single work function gate electrode and method of fabricationUS8304805Jan 8, 2010Nov 6, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor diodes fabricated by aspect ratio trapping with coalesced filmsUS8324660Jul 28, 2010Dec 4, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabricationUS8329541Dec 11, 2012Taiwan Semiconductor Manufacturing Company, Ltd.InP-based transistor fabricationUS8344242Jan 1, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Multi-junction solar cellsUS8362566Jun 23, 2008Jan 29, 2013Intel CorporationStress in trigate devices using complimentary gate fill materialsUS8368135Apr 23, 2012Feb 5, 2013Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabricationUS8384196Sep 23, 2011Feb 26, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Formation of devices by epitaxial layer overgrowthUS8399922Mar 19, 2013Intel CorporationIndependently accessed double-gate and tri-gate transistorsUS8405164Apr 26, 2010Mar 26, 2013Intel CorporationTri-gate transistor device with stress incorporation layer and method of fabricationUS8461650 *Mar 3, 2011Jun 11, 2013Institute of Microelectronics, Chinese Academy of SciencesSemiconductor device and method for manufacturing the sameUS8502263Oct 19, 2007Aug 6, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Light-emitter-based devices with lattice-mismatched semiconductor structuresUS8502351Sep 23, 2011Aug 6, 2013Intel CorporationNonplanar device with thinned lower body portion and method of fabricationUS8519436Nov 19, 2012Aug 27, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabricationUS8552477Jun 24, 2010Oct 8, 2013Institute of Microelectronics, Chinese Academy of SciencesFinFET with improved short channel effect and reduced parasitic capacitanceUS8581258Oct 20, 2011Nov 12, 2013Intel CorporationSemiconductor device structures and methods of forming semiconductor structuresUS8598662 *Mar 2, 2011Dec 3, 2013Institute of Microelectronics, Chinese Academy of SciencesSemiconductor device and method for forming the sameUS8617945Feb 3, 2012Dec 31, 2013Intel CorporationStacking fault and twin blocking barrier for integrating III-V on SiUS8624103Sep 27, 2010Jan 7, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Nitride-based multi-junction solar cell modules and methods for making the sameUS8629045Aug 22, 2012Jan 14, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Reduction of edge effects from aspect ratio trappingUS8629047Jul 9, 2012Jan 14, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Quantum tunneling devices and circuits with lattice-mismatched semiconductor structuresUS8629446Apr 1, 2010Jan 14, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Devices formed from a non-polar plane of a crystalline material and method of making the sameUS8629477May 28, 2013Jan 14, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabricationUS8664694Jan 28, 2013Mar 4, 2014Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabricationUS8741703Sep 17, 2013Jun 3, 2014Institute of Microelectronics, Chinese Academy of SciencesMethod for manufacturing FinFET with improved short channel effect and reduced parasitic capacitanceUS8741733Jan 25, 2013Jun 3, 2014Intel CorporationStress in trigate devices using complimentary gate fill materialsUS8749026Jun 3, 2013Jun 10, 2014Intel CorporationNonplanar device with thinned lower body portion and method of fabricationUS8765510Oct 12, 2012Jul 1, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor diodes fabricated by aspect ratio trapping with coalesced filmsUS8796734Dec 12, 2013Aug 5, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabricationUS8809106Aug 24, 2012Aug 19, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Method for semiconductor sensor structures with reduced dislocation defect densitiesUS8816392 *Mar 2, 2011Aug 26, 2014Institute of Microelectronics, Chinese Academy of SciencesSemiconductor device having gate structures to reduce the short channel effectsUS8816394Dec 20, 2013Aug 26, 2014Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabricationUS8822248Jan 3, 2012Sep 2, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Epitaxial growth of crystalline materialUS8847279Apr 13, 2012Sep 30, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Defect reduction using aspect ratio trappingUS8860160Dec 17, 2013Oct 14, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Quantum tunneling devices and circuits with lattice-mismatched semiconductor structuresUS8878243May 4, 2010Nov 4, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Lattice-mismatched semiconductor structures and related methods for device fabricationUS8896062 *Feb 24, 2011Nov 25, 2014Institute of Microelectronics, Chinese Academy of SciencesSemiconductor device and method for forming the sameUS8907406 *Dec 28, 2012Dec 9, 2014Kabushiki Kaisha ToshibaTransistor having impurity distribution controlled substrate and method of manufacturing the sameUS8933458Oct 8, 2013Jan 13, 2015Intel CorporationSemiconductor device structures and methods of forming semiconductor structuresUS8981427Jul 15, 2009Mar 17, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Polishing of small composite semiconductor materialsUS8987028Jun 24, 2014Mar 24, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabricationUS8994070Dec 17, 2013Mar 31, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Reduction of edge effects from aspect ratio trappingUS9018055 *Mar 11, 2014Apr 28, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Hybrid fin field-effect transistor structures and related methodsUS9024355 *May 30, 2012May 5, 2015International Business Machines CorporationEmbedded planar source/drain stressors for a finFET including a plurality of finsUS9029908May 27, 2014May 12, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor diodes fabricated by aspect ratio trapping with coalesced filmsUS9040331Jul 20, 2012May 26, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Diode-based devices and methods for making the sameUS9048314Aug 21, 2014Jun 2, 2015Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabricationUS9099559 *Sep 16, 2013Aug 4, 2015Stmicroelectronics, Inc.Method to induce strain in finFET channels from an adjacent regionUS9105522Sep 12, 2014Aug 11, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Quantum tunneling devices and circuits with lattice-mismatched semiconductor structuresUS9105549Jul 16, 2014Aug 11, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor sensor structures with reduced dislocation defect densitiesUS9153645Jul 25, 2008Oct 6, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabricationUS9153670Dec 2, 2014Oct 6, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor device and fabricating the sameUS9184294 *Sep 24, 2014Nov 10, 2015Intel CorporationHigh mobility strained channels for fin-based transistorsUS9190518May 8, 2014Nov 17, 2015Intel CorporationNonplanar device with thinned lower body portion and method of fabricationUS9219112Mar 2, 2015Dec 22, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabricationUS9224754May 8, 2014Dec 29, 2015Intel CorporationStress in trigate devices using complimentary gate fill materialsUS9231073Mar 31, 2015Jan 5, 2016Taiwan Semiconductor Manufacturing Company, Ltd.Diode-based devices and methods for making the sameUS9287128Mar 2, 2015Mar 15, 2016Taiwan Semiconductor Manufacturing Company, Ltd.Polishing of small composite semiconductor materialsUS9299562Dec 13, 2013Mar 29, 2016Taiwan Semiconductor Manufacturing Company, Ltd.Devices formed from a non-polar plane of a crystalline material and method of making the sameUS9318325Jul 30, 2014Apr 19, 2016Taiwan Semiconductor Manufacturing Company, Ltd.Defect reduction using aspect ratio trappingUS9337307Nov 18, 2010May 10, 2016Intel CorporationMethod for fabricating transistor with thinned channelUS9356103Feb 24, 2015May 31, 2016Taiwan Semiconductor Manufacturing Company, Ltd.Reduction of edge effects from aspect ratio trappingUS9365949Jul 30, 2014Jun 14, 2016Taiwan Semiconductor Manufacturing Company, Ltd.Epitaxial growth of crystalline materialUS9368583May 1, 2015Jun 14, 2016Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabricationUS20040036126 *Aug 23, 2002Feb 26, 2004Chau Robert S.Tri-gate devices and methods of fabricationUS20040094807 *Nov 7, 2003May 20, 2004Chau Robert S.Tri-gate devices and methods of fabricationUS20050148137 *Dec 30, 2003Jul 7, 2005Brask Justin K.Nonplanar transistors with metal gate electrodesUS20050158970 *Jan 16, 2004Jul 21, 2005Robert ChauTri-gate transistors and methods to fabricate sameUS20050193143 *Dec 30, 2003Sep 1, 2005Meyers Brian R.Framework for user interaction with multiple network devicesUS20050199950 *May 6, 2005Sep 15, 2005Chau Robert S.Tri-gate devices and methods of fabricationUS20050218438 *Mar 22, 2005Oct 6, 2005Nick LindertBulk non-planar transistor having strained enhanced mobility and methods of fabricationUS20050242406 *Jun 30, 2005Nov 3, 2005Hareland Scott ANonplanar device with stress incorporation layer and method of fabricationUS20050285159 *Jun 24, 2004Dec 29, 2005International Business Machines CorporationCompressive SiGe <110> growth and structure of MOSFET devicesUS20060011977 *Feb 4, 2005Jan 19, 2006Kabushiki Kaisha ToshibaSemiconductor device and method of fabricating the sameUS20060033095 *Aug 10, 2004Feb 16, 2006Doyle Brian SNon-planar pMOS structure with a strained channel region and an integrated strained CMOS flowUS20060043579 *Aug 31, 2004Mar 2, 2006Jun HeTransistor performance enhancement using engineered strainsUS20060128131 *Jan 18, 2006Jun 15, 2006Chang Peter LIndependently accessed double-gate and tri-gate transistors in same process flowUS20060138552 *Feb 22, 2006Jun 29, 2006Brask Justin KNonplanar transistors with metal gate electrodesUS20060138553 *Feb 24, 2006Jun 29, 2006Brask Justin KNonplanar transistors with metal gate electrodesUS20060157687 *Jan 18, 2005Jul 20, 2006Doyle Brian SNon-planar MOS structure with a strained channel regionUS20060157794 *Mar 9, 2006Jul 20, 2006Doyle Brian SNon-planar MOS structure with a strained channel regionUS20060172497 *Jun 27, 2003Aug 3, 2006Hareland Scott ANonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabricationUS20060186484 *Feb 23, 2005Aug 24, 2006Chau Robert SField effect transistor with narrow bandgap source and drain regions and method of fabricationUS20060197163 *Feb 27, 2006Sep 7, 2006Seiko Epson CorporationSemiconductor device and method for manufacturing semiconductor deviceUS20060214231 *May 23, 2006Sep 28, 2006Uday ShahNonplanar device with thinned lower body portion and method of fabricationUS20060228840 *Dec 7, 2005Oct 12, 2006Chau Robert STri-gate devices and methods of fabricationUS20060292719 *May 17, 2006Dec 28, 2006Amberwave Systems CorporationLattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabricationUS20070001219 *Jun 30, 2005Jan 4, 2007Marko RadosavljevicBlock contact architectures for nanoscale channel transistorsUS20070034972 *Oct 25, 2006Feb 15, 2007Chau Robert STri-gate devices and methods of fabricationUS20070040223 *Aug 17, 2005Feb 22, 2007Intel CorporationLateral undercut of metal gate in SOI deviceUS20070063277 *Sep 22, 2005Mar 22, 2007International Business Machines CorporationMultiple low and high k gate oxides on single gate for lower miller capacitance and improved drive currentUS20070090416 *Sep 28, 2005Apr 26, 2007Doyle Brian SCMOS devices with a single work function gate electrode and method of fabricationUS20070148837 *Dec 27, 2005Jun 28, 2007Uday ShahMethod of fabricating a multi-cornered filmUS20070235818 *Mar 28, 2006Oct 11, 2007Anderson Brent ADual-plane complementary metal oxide semiconductorUS20070238273 *Mar 31, 2006Oct 11, 2007Doyle Brian SMethod of ion implanting for tri-gate devicesUS20070275532 *May 24, 2006Nov 29, 2007International Business Machines CorporationOptimized deep source/drain junctions with thin poly gate in a field effect transistorUS20070281409 *Aug 29, 2005Dec 6, 2007Yuegang ZhangMulti-gate carbon nano-tube transistorsUS20080113476 *Jan 16, 2008May 15, 2008International Business Machines CorporationDual-plane complementary metal oxide semiconductorUS20080187018 *Oct 19, 2007Aug 7, 2008Amberwave Systems CorporationDistributed feedback lasers formed via aspect ratio trappingUS20080308861 *Jun 18, 2007Dec 18, 2008Infineon Technologies Agam CampeonDual gate finfetUS20100065888 *Jan 12, 2006Mar 18, 2010Shaheen Mohamad AHigh mobility tri-gate devices and methods of fabricationUS20100295129 *Aug 4, 2010Nov 25, 2010Chau Robert SField effect transistor with narrow bandgap source and drain regions and method of fabricationUS20110027948 *Feb 3, 2011International Business Machines CorporationMethod for manufacturing a finfet deviceUS20110111565 *May 12, 2011Infineon Technologies AgDual gate finfetUS20110193164 *Jun 24, 2010Aug 11, 2011Huilong ZhuSemiconductor device and method for manufacturing the sameUS20120001229 *Mar 2, 2011Jan 5, 2012Institute of Microelectronics, Chinese Academy of SciencesSemiconductor Device and Method for Forming the SameUS20120126332 *Feb 24, 2011May 24, 2012Huilong ZhuSemiconductor device and method for forming the sameUS20120223331 *Mar 2, 2011Sep 6, 2012Institute of Microelectronics, Chinese Academy of SciencesSemiconductor device and method for forming the sameUS20130240828 *Dec 28, 2012Sep 19, 2013Kensuke OtaSemiconductor device and method of manufacturing the sameUS20130320399 *May 30, 2012Dec 5, 2013International Business Machines CorporationEmbedded planar source/drain stressors for a finfet including a plurality of finsUS20140027860 *Jul 27, 2012Jan 30, 2014Glenn A. GlassSelf-aligned 3-d epitaxial structures for mos device fabricationUS20140193955 *Mar 11, 2014Jul 10, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Hybrid Fin Field-Effect Transistor Structures and Related MethodsUS20150008484 *Sep 24, 2014Jan 8, 2015Intel CorporationHigh mobility strained channels for fin-based transistorsUS20150076514 *Sep 16, 2013Mar 19, 2015Stmicroelectronics, Inc.Method to induce strain in finfet channels from an adjacent regionUS20150303282 *Jun 30, 2015Oct 22, 2015Stmicroelectronics, Inc.Method to induce strain in finfet channels from an adjacent regionUS20150340290 *Nov 19, 2012Nov 26, 2015Institute of Microelectronics, Chinese Academy of SciencesSemiconductor device and method for manufacturing the sameWO2006002410A2 *Jun 21, 2005Jan 5, 2006International Business Machines CorporationCompressive sige <110> growth mosfet devicesWO2006002410A3 *Jun 21, 2005Dec 6, 2007Kevin K ChanCompressive sige <110> growth mosfet devicesWO2011038598A1 *Jun 24, 2010Apr 7, 2011Institute of Microelectronics, Chinese Academy of SciencesSemiconductor device and method thereof* Cited by examinerClassifications U.S. Classification257/348, 257/E21.703, 257/E29.275, 257/E27.112, 257/E29.298International ClassificationH01L27/01, H01L21/84, H01L29/786, H01L21/336, H01L27/12Cooperative ClassificationH01L29/785, H01L21/845, H01L29/66795, H01L27/1211European ClassificationH01L29/66M6T6F16F, H01L21/84F, H01L27/12B4, H01L29/78SLegal EventsDateCodeEventDescriptionJun 9, 2004ASAssignmentOwner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BEDELL, STEPHEN W.;CHAN, KEVIN K.;CHIDAMBARRAO, DURESETI;AND OTHERS;REEL/FRAME:014713/0674;SIGNING DATES FROM 20040128 TO 20040217Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION,NEW YOFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BEDELL, STEPHEN W.;CHAN, KEVIN K.;CHIDAMBARRAO, DURESETI;AND OTHERS;SIGNING DATES FROM 20040128 TO 20040217;REEL/FRAME:014713/0674Dec 6, 2013REMIMaintenance fee reminder mailedApr 11, 2014FPAYFee paymentYear of fee payment: 4Apr 11, 2014SULPSurcharge for late paymentSep 3, 2015ASAssignmentOwner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001Effective date: 20150629Oct 5, 2015ASAssignmentOwner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001Effective date: 20150910RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services