Source: http://www.google.com/patents/US6145045?dq=6,219,045
Timestamp: 2018-01-20 18:20:00
Document Index: 664018919

Matched Legal Cases: ['application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09']

Patent US6145045 - System for sending and receiving data on a Universal Serial Bus (USB) using ... - Google Patents
An apparatus for an method of sending and receiving data on a Universal Serial Bus using a memory shared among a number of endpoints are disclosed. The memory is a double buffer which allows the next packet to be prepared while the current packet is being transmitted. The invention also supports transmission...http://www.google.com/patents/US6145045?utm_source=gb-gplus-sharePatent US6145045 - System for sending and receiving data on a Universal Serial Bus (USB) using a memory shared among a number of end points
Publication number US6145045 A
Application number US 09/004,003
Also published as DE19900331A1, US6173355
Publication number 004003, 09004003, US 6145045 A, US 6145045A, US-A-6145045, US6145045 A, US6145045A
Patent Citations (5), Non-Patent Citations (14), Referenced by (105), Classifications (20), Legal Events (4)
System for sending and receiving data on a Universal Serial Bus (USB) using a memory shared among a number of end points
US 6145045 A
An apparatus for an method of sending and receiving data on a Universal Serial Bus using a memory shared among a number of endpoints are disclosed. The memory is a double buffer which allows the next packet to be prepared while the current packet is being transmitted. The invention also supports transmission retry.
1. An apparatus for receiving data on a non-isochronous endpoint pipe at a Universal Serial Bus (USB) endpoint from a USB host, comprising:
wherein said controller writes into said pointer data storage element a first pointer corresponding to a first buffer of said plurality of buffers, receives a first plurality of data into said first buffer as indicated by said pointer data storage element, writes into said pointer data storage element a second pointer corresponding to a second buffer of said plurality of buffers, and receives a second plurality of data into said second buffer as indicated by said pointer data storage element.
2. The apparatus of claim 1, wherein said controller is further configured to detect an error, and wherein when said controller detects said error, said controller continues receiving without writing another pointer until said error is handled.
3. The apparatus of claim 2, wherein said error is one of a CRC error, a bit stuff error, and a buffer error.
4. The apparatus of claim 1, wherein said at least one USB endpoint pipe is 16 USB endpoint pipes, and said plurality of USB endpoints is 16 USB endpoints.
5. The apparatus of claim 1, wherein said plurality of buffers are a double buffer.
6. An apparatus for receiving data on a non-isochronous endpoint pipe at a Universal Serial Bus (USB) endpoint from a USB host, comprising:
wherein said controller writes into said pointer data storage element a first pointer corresponding to a first buffer of said plurality of buffers, receives a first plurality of data into said first buffer as indicated by said pointer data storage element, writes into said pointer data storage element a second pointer corresponding to a second buffer of said plurality of buffers, receives a second plurality of data into said second buffer as indicated by said pointer data storage element, writes into said pointer data storage element a third pointer corresponding to said first buffer, and receives a third plurality of data into said first buffer as indicated by said pointer data storage element.
7. The apparatus of claim 6, wherein said controller is further configured to detect an error, and wherein when said controller detects said error, said controller continues receiving without writing another pointer until said error is handled.
8. The apparatus of claim 7, wherein said error is one of a CRC error, a bit stuff error, and a buffer error.
9. The apparatus of claim 6, wherein said at least one USB endpoint pipe is 16 USB endpoint pipes, and said plurality of USB endpoints is 16 USB endpoints.
10. The apparatus of claim 6, wherein said plurality of buffers are a double buffer.
11. A method of receiving data on a non-isochronous endpoint pipe at a Universal Serial Bus (USB) endpoint from a USB host, comprising the steps of:
generating a first pointer corresponding to a first buffer of a plurality of buffers shared among a plurality of USB endpoints, and storing said first pointer in a pointer data storage element:
generating a second pointer corresponding to a second buffer of said plurality of buffers, and storing said second pointer in said pointer data storage element; and
receiving a second plurality of data into said second buffer as indicated by said pointer data storage element.
detecting an error, and in accordance therewith continuing to receive without generating another pointer until said error is handled.
13. A method of receiving data on a non-isochronous endpoint pipe at a Universal Serial Bus (USB) endpoint from a USB host, comprising the steps of:
generating a third pointer corresponding to said first buffer, and storing said third pointer in said pointer data storage element; and
receiving a third plurality of data into said first buffer as indicated by said pointer data storage element.
The invention described in this application is an aspect of a larger set of inventions described in the following co-pending applications which are commonly owned by the assignee of the present invention, and are hereby incorporated by reference: U.S. patent application Ser. No. 09/003,897 still pending, U.S. patent application Ser. No. 09/004,004 still pending, U.S. patent application Ser. No. 09/003,963 now U.S. Pat. No. 6,070,208, U.S. patent application Ser. No. 09/004,002 still pending, U.S. patent application Ser. No. 09/004,005 still pending, and U.S. patent application Ser. No. 09/003,925 still pending.
Although this specification uses the term "data packet", the invention is also intended to apply to a plurality of data even if the data is not contained in a discrete packet.
The endpoint controller also maintains status to indicate when it is locked to the USB 1 KHz bus clock, and when a discontinuity occurs in the USB bus clock due to a missing or incorrect Start-Of-Frame packet. This is used by the software to adjust the queuing of isochronous packets. The current frame number is used by the endpoint controller to determine which isochronous buffer to transmit next.
In a preferred embodiment, the USB Serial Interface Engine (SIE) is comprised of a PHY and a MAC level. The PHY level includes the digital-clock recovery circuit, a digital glitch filter, End-- Of-- Packet detection circuitry, and bit-stuffing and de-stuffing logic. The MAC level includes packet formatting, CRC generation and checking, and endpoint address detection, and provides the necessary control to give the NAK, ACK and STALL responses as determined by the EPC for the specified endpoint pipe. The SIE is also responsible for detecting and reporting events on detection of USB-specific events, such as Reset, Suspend and Resume. The transmitter outputs of the UNIM module to the transceiver are well matched (under 1 ns) to minimize skew on the USB signals.
A new endpoint pipe (EPP) state can be defined for missing acknowledge I-- MAK. This state can be entered from the I-- ACT state if this is a command EPP when the host did not respond with an ACK or when the host's ACK was corrupted on its way to the node. In both cases, the buffer status is written to I-- WT and CWP is not incremented.
If while in the I-- MAK state and an IN token is received, the endpoint will resend the data, as before.
If while in the I-- MAK state and an OUT token is received, this then confirms that the previous ACK was corrupted on its way back to the node. The current OUT transaction will be NAKed, the data is ignored (but the I-- CMP buffer status is written), CWP is inverted, and the control word is read, which in turn causes the endpoint state to be updated (the normal status processing). This buffer status should be either O-- RDY or SKIP.
If the buffer status is O-- RDY then the next data packet will be received as in normal operation. If the buffer status is SKIP then another NAK will be sent. Data is resent at the current CWP.
For OUT buffers, the first byte stored is the byte following the PID. Similarly for IN buffers, the address points to the first byte of data to be transmitted, i.e., the byte immediately following the PID in the packet. The CRC is automatically calculated and appended to the packet, except when the IN token is received from the IS-- RDY state and the control word did not have the IS field set to 1.
______________________________________Value        State______________________________________0            Disabled DIS1            Input Idle I.sub.-- IDL2            Input Ready I.sub.-- RDY3            Input Active I.sub.-- ACT4            Stalled HALT5            Input Missed ACK I.sub.-- MAK6            Input Isochronous Ready IS.sub.-- RDY7            Input Isochronous Active IS.sub.-- ACT8            Setup Ready S.sub.-- RDY9            Output Idle O.sub.-- IDL10           Output Ready O.sub.-- RDY11           Cutput Active O.sub.-- ACT12           Setup Active S.sub.-- ACT13           Output Isochronous Idle OS.sub.-- IDL14           Output Isochronous Ready OS.sub.-- RDY15           Output Isochronous Active OS.sub.-- ACT______________________________________
______________________________________  Bits        Function Label______________________________________  31-11       BPA  10-0        00000000000______________________________________
______________________________________  Bits        Function Label______________________________________  31-11       BPB  10-0        00000000000______________________________________
Input Ready I-- RDY. This state is entered via an Input Ready command to this endpoint pipe or upon detection of another Input buffer at the end of a transfer. The command should only be given after a buffer has been allocated to this endpoint by writing the control word at the appropriate location in the endpoint array. This control word should point to a data buffer with data to return to the host in response to the next IN token received to this endpoint pipe. The PID value is transmitted as DATA0 when CWP is 0 and DATAL when CWP is 1.
Input Active I-- ACT. This state is entered upon receipt of an IN token when the selected endpoint state is currently Input Ready. While in this state, data is transferred from memory to the USB. Upon completion of the data transfer, an ACK handshake should be received within 16 bit times. At the end of this time-out period, if an ACK was not received, the buffer wait status is written back to the control word. However, the address and byte counter are not overwritten because a retransmission will occur and the current values need to be used again. If an ACK is received, the buffer status along with the current value of the address and byte counter are written. Then the other control word on this endpoint is read to determine the next state of the endpoint to be used the next time a token is directed to this endpoint pipe. If this endpoint is being used for a control transfer a transfer to the output Ready or Output Idle state can occur to complete the status phase of a control read transfer.
Output Ready O-- RDY. This state is entered after this endpoint pipe has been given a buffer in which to write data. This can be entered via an Output Ready command from the O-- IDL state after the appropriate word in the endpoint array is written, or upon detection of another Output buffer at the end of a transfer.
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2 8×930A×, 8×930H× Users Manual; Intel; pp. 6.1-10.1 Appendix B-D; 1997.
3 * U.S. application No. 09/003,897, filed Jan. 7, 1998.
4 * U.S. application No. 09/003,925, filed Jan. 7, 1998.
5 * U.S. application No. 09/003,963, filed Jan. 7, 1998.
6 * U.S. application No. 09/004,002, filed Jan. 7, 1998.
7 * U.S. application No. 09/004,004, filed Jan. 7, 1998.
8 * U.S. application No. 09/004,005, filed Jan. 7, 1998.
9 * Universal Serial Bus Common Class Specification; SystemSoft Corporation, Intel Corporation; pp. i v, 1 14; Nov. 4, 1997.
10 Universal Serial Bus Common Class Specification; SystemSoft Corporation, Intel Corporation; pp. i-v, 1-14; Nov. 4, 1997.
11 * Universal Seril Bus Specification; Compaq, Digital Equipment Corporation, IBM PC Company, Intel, Microsoft, NEC, Northern Telecom; pp. 1 268; Jan. 15, 1996.
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14 USB Feature Specification: Shared Endpoints; SystemSoft Corporation, Intel Corporation; pp. i-iii, 1-14; Dec. 4, 1997.
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U.S. Classification 710/310, 370/464, 714/799, 709/230, 714/4.2
International Classification H04L12/879, H04L12/861, H04L1/18, H04L1/00, G06F13/42
Cooperative Classification H04L49/901, H04L2001/0094, H04L49/90, H04L1/1848, H04L1/1835, G06F13/4295
European Classification H04L49/90C, H04L49/90, H04L1/18R3, G06F13/42S6
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FALIK, OHAD;BRIEF, DAVID;REEL/FRAME:009346/0169;SIGNING DATES FROM 19980224 TO 19980227