Source: http://www.google.com/patents/US20080246500?dq=5,758,352
Timestamp: 2014-03-17 16:10:31
Document Index: 186781062

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US20080246500 - High density interconnect system having rapid fabrication cycle - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises...http://www.google.com/patents/US20080246500?utm_source=gb-gplus-sharePatent US20080246500 - High density interconnect system having rapid fabrication cycleAdvanced Patent SearchPublication numberUS20080246500 A1Publication typeApplicationApplication numberUS 11/858,064Publication dateOct 9, 2008Filing dateSep 19, 2007Priority dateMay 23, 2000Also published asUS7382142, US7872482, US7884634, US20050275418, US20090153165, WO2005115068A2, WO2005115068A3, WO2005115068A8Publication number11858064, 858064, US 2008/0246500 A1, US 2008/246500 A1, US 20080246500 A1, US 20080246500A1, US 2008246500 A1, US 2008246500A1, US-A1-20080246500, US-A1-2008246500, US2008/0246500A1, US2008/246500A1, US20080246500 A1, US20080246500A1, US2008246500 A1, US2008246500A1InventorsFu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui ShanOriginal AssigneeFu Chiung Chong, Andrew Kao, Mckay Douglas, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui ShanExport CitationBiBTeX, EndNote, RefManReferenced by (3), Classifications (11), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetHigh density interconnect system having rapid fabrication cycleUS 20080246500 A1Abstract An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
CROSS REFERENCE TO RELATED APPLICATIONS This application is a Continuation of U.S. patent application Ser. No. 11/133,021 (NNEX0001CIP3), entitled High Density Interconnect System Having Rapid Fabrication Cycle, filed 18 May 2005, which claims priority to (NNEX0019PR) U.S. Provisional Application No. 60/573,541, entitled Quick-Change Probe Chip, filed 20 May 2004; (NNEX0021PR) U.S. Provisional Application No. 60/592,908, entitled Probe Card Assembly with Rapid Fabrication Cycle, filed 29 Jul. 2004; and (NNEX0015PR) U.S. Provisional Application No. 60/651,294, entitled Nano-Contactor Embodiments for IC Packages and Interconnect Components, filed 8 Feb. 2005.
U.S. patent application Ser. No. 11/133,021 (NNEX0001CIP3), entitled High Density Interconnect System Having Rapid Fabrication Cycle, filed 18 May 2005, is also a Continuation In Part of U.S. patent application Ser. No. 10/870,095 (NNEX0001CIP2), entitled Enhanced Compliant Probe Card Systems Having Improved Planarity, US Filing Date 16 Jun. 2004, which is a Continuation In Part of U.S. patent application Ser. No. 10/196,494 (NNEX0012), entitled Mosaic Decal Probe, filed 15 Jul. 2002, issued as U.S. Pat. No. 6,710,609 on 23 Mar. 2004.
U.S. patent application Ser. No. 10/870,095 (NNEX0001CIP2), entitled Enhanced Compliant Probe Card Systems Having Improved Planarity, US Filing Date 16 Jun. 2004, is also a Continuation In Part of U.S. patent application Ser. No. 10/178,103 (NNEX0001CIP), entitled Construction Structures and Manufacturing Processes for Probe Card Assemblies and Packages Having Wafer Level Springs, US Filing Date 24 Jun. 2002, issued as U.S. Pat. No. 6,917,525 on 12 Jul. 2005, which is a Continuation In Part of U.S. patent application Ser. No. 09/980,040 (NNEX0003), entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date 27 Nov. 2001, issued as U.S. Pat. No. 6,799,976 on 5 Oct. 2004, which claims priority from PCT Patent Application Serial No. PCT/US00/21012 (NNEX0003P), filed Jul. 27, 2000, which claims priority from U.S. Provisional Application No. 60/146,241 (NNEX0003PR), filed on 28 Jul. 1999.
U.S. patent application Ser. No. 09/980,040 (NNEX0003), entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date 27 Nov. 2001, issued as U.S. Pat. No. 6,799,976 on 5 Oct. 2004, also claims priority from PCT Patent Application Serial No. PCT/US00/14164 (NNEX0001P), entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, filed 23 May 2000, which claims priority from U.S. Provisional Application No. 60/136,636 (NNEX0001PR), entitled Wafer Interface for High Density Wafer Probe Card, filed on 27 May 1999.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Introductory disclosure regarding structures, processes and systems disclosed herein is seen in: U.S. Provisional Application No. 60/136,636 (NNEX0001PR), entitled Wafer Interface for High Density Probe Card, filed 27 May 1999; U.S. Provisional Application No. 60/146,241 (NNEX0003PR), entitled Method of Massively Parallel Testing of Circuits, filed 28 Jul. 1999; U.S. Provisional Application No. 60/573,541 (NNEX0019PR), entitled Quick-Change Probe Chip, filed 20 May 2004; U.S. Provisional Application No. 60/592,908 (NNEX0021PR), entitled Probe Card Assembly with Rapid Fabrication Cycle, filed 29 Jul. 2004; U.S. Provisional Application No. 60/651,294 (NNEX0015PR), entitled Nano-Contactor Embodiments for IC Packages and Interconnect Components, filed 8 Feb. 2005; U.S. patent application Ser. No. 10/870,095 (NNEX0001CIP2), entitled Enhanced Compliant Probe Card Systems Having Improved Planarity, US Filing Date 16 Jun. 2004; U.S. patent application Ser. No. 10/178,103 (NNEX0001CIP), entitled Construction Structures and Manufacturing Processes for Probe Card Assemblies and Packages Having Wafer Level Springs, US Filing Date 24 Jun. 2002; U.S. patent application Ser. No. 09/980,040 (NNEX0003), entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date 27 Nov. 2001; PCT Patent Application Serial No. PCT/US00/21012 (NNEX0003P), filed 27 Jul. 2000; PCT Patent Application Serial No. PCT/US00/14164 (NNEX0001P), entitled Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies, US Filing Date 23 May 2000; and U.S. patent application Ser. No. 10/069,902 (NNEX0004), entitled Systems for Testing and Packaging Integrated Circuits, filed 28 Jun. 2002, which is incorporated herein in its entirety by this reference thereto.
Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8461697Sep 2, 2011Jun 11, 2013Panasonic CorporationSemiconductor integrated circuit deviceUS8575954 *Jan 31, 2008Nov 5, 2013Advantest (Singapore) Pte LtdStructures and processes for fabrication of probe card assemblies with multi-layer interconnectUS20100244867 *Jan 31, 2008Sep 30, 2010Fu Chiung ChongStructures and Processes for Fabrication of Probe Card Assemblies with Multi-Layer Interconnect* Cited by examinerClassifications U.S. Classification324/754.14, 29/884, 324/755.05International ClassificationH05K7/06, G01R31/28, G01R1/073, H01R43/00, G01R31/02Cooperative ClassificationG01R1/07378, G01R31/2889European ClassificationG01R31/28G5CLegal EventsDateCodeEventDescriptionMar 20, 2012ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:VERIGY (SINGAPORE) PTE LTD;REEL/FRAME:027896/0018Effective date: 20120302Owner name: ADVANTEST (SINGAPORE) PTE LTD, SINGAPOREJul 7, 2010ASAssignmentOwner name: VERIGY (SINGAPORE) PTE. LTD.,SINGAPOREFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NANONEXUS (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC;REEL/FRAME:24640/301Effective date: 20100601Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NANONEXUS, INC.;REEL/FRAME:24640/291Effective date: 20100525Owner name: NANONEXUS (ASSIGNMENT FOR THE BENEFIT OF CREDITORSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NANONEXUS, INC.;REEL/FRAME:024640/0291Owner name: VERIGY (SINGAPORE) PTE. LTD., SINGAPOREFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NANONEXUS (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC;REEL/FRAME:024640/0301Dec 23, 2008ASAssignmentOwner name: NANONEXUS, INC., CALIFORNIAFree format text: LIEN RELEASE;ASSIGNOR:GLENN PATENT GROUP;REEL/FRAME:022024/0219Effective date: 20081223Owner name: NANONEXUS, INC.,CALIFORNIAFree format text: LIEN RELEASE;ASSIGNOR:GLENN PATENT GROUP;US-ASSIGNMENT DATABASE UPDATED:20100204;REEL/FRAME:22024/219Sep 5, 2008ASAssignmentOwner name: GLENN PATENT GROUP, CALIFORNIAFree format text: LIEN;ASSIGNOR:NANONEXUS, INC.;REEL/FRAME:021489/0108Effective date: 20080905Owner name: GLENN PATENT GROUP,CALIFORNIAFree format text: LIEN;ASSIGNOR:NANONEXUS, INC.;US-ASSIGNMENT DATABASE UPDATED:20100204;REEL/FRAME:21489/108RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google