Source: http://www.google.com/patents/US6307269?dq=5708422
Timestamp: 2014-07-14 00:13:49
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Patent US6307269 - Semiconductor device with chip size package - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the...http://www.google.com/patents/US6307269?utm_source=gb-gplus-sharePatent US6307269 - Semiconductor device with chip size packageAdvanced Patent SearchPublication numberUS6307269 B1Publication typeGrantApplication numberUS 09/113,500Publication dateOct 23, 2001Filing dateJul 10, 1998Priority dateJul 11, 1997Fee statusPaidAlso published asCN1208252A, CN1295346A, US6515371, US6639323, US20020047215, US20020050636, US20030207557Publication number09113500, 113500, US 6307269 B1, US 6307269B1, US-B1-6307269, US6307269 B1, US6307269B1InventorsYukiharu Akiyama, Tomoaki Kudaishi, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Asao Nishimura, Ichiro Anjo, Kunihiro Tsubosaki, Chuichi Miyazaki, Hiroshi Koyama, Masanori Shibamoto, Akira Nagai, Masahiko OginoOriginal AssigneeHitachi, Ltd., Hitachi Ulsi Systems Co., Ltd., Akita Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (4), Non-Patent Citations (1), Referenced by (10), Classifications (27), Legal Events (11) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device with chip size packageUS 6307269 B1Abstract A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.
a semiconductor chip including plural semiconductor elements on its main surface and plural connection terminals, said plural connection terminals being arranged on the periphery of said semiconductor chip; an elastic body arranged on the main surface of said semiconductor chip leaving said connection terminals exposed; an insulating tape formed on said elastic body comprising openings in an area where said connection terminals are arranged; plural leads formed on the surface of said insulating tape, in which one end is electrically connected to the said terminals and the other ends are arranged on said elastic body; plural bump electrodes formed at the other end of said plural leads; and a resin body for sealing said connection terminals of said semiconductor chip and one end of said leads; wherein said insulating tape comprises a first part arranged over said main surface of said semiconductor chip, and a second part protruding beyond said semiconductor chip in the vicinity of the periphery of said semiconductor chip wherein said plural connection terminals are arranged; and further comprising a dam piece formed as a separate body from said insulating tape in said second part of said insulating tape. 2. A semiconductor device comprising a semiconductor chip having connection terminals provided on the outer periphery of its main surface, comprising:
an elastic body arranged on the main surface of said semiconductor chip leaving said connection terminals exposed; a thin film wiring substrate comprising a substrate body having wiring whereof one end is electrically connected to said connection terminals via leads and the other ends are electrically connected to bump electrodes which are external terminals, and comprising substrate protruding parts having openings which leave said connection terminals exposed and which protrude beyond said openings and said semiconductor chip; sealing parts which seal said connection terminals of said semiconductor chip and seal said leads of said thin film wiring substrate; said substrate body and said substrate protruding parts of said thin film wiring substrate being formed in a one-piece construction; and wherein a dam piece is provided for preventing leakage of sealing resin when resin sealing is performed around said openings of said thin film wiring substrate. 3. A semiconductor device comprising a semiconductor chip having connection terminals provided on the outer periphery of its main surface, comprising
an elastic body arranged on the main surface of said semiconductor chip having openings for exposing said connection terminals, said elastic body comprising elastic body protruding parts which protrude beyond said openings and said semiconductor chip; a thin film wiring substrate comprising a substrate body having wiring whereof one end is electrically connected to said connection terminals via leads and the other ends are electrically connected to bump electrodes which are external terminals, and comprising substrate protruding parts having openings which leave said connection terminals exposed and which protrude beyond said openings and said semiconductor chip; and sealing parts which seal said connection terminals of said semiconductor chip and seal said leads of said thin film wiring substrate; said substrate body and said substrate protruding parts of said thin film wiring substrate being formed in a one-piece construction, and said thin film wiring substrate and said elastic body being formed in approximately the same size, wherein said semiconductor chip is attached so that its side faces are surrounded by said elastic body protruding parts of said elastic body. 4. A semiconductor device comprising:
a semiconductor chip including plural semiconductor elements on its main surface and plural connection terminals, said plural connection terminals being arranged on the periphery of said semiconductor chip an elastic body arranged on the main surface of said semiconductor chip leaving said connection terminals exposed; an insulating tape formed on said elastic body comprising openings in an area where said connection terminals are arranged; plural leads formed on the surface of said insulating tape, in which one end is electrically connected to the said terminals and the other ends are arranged on said elastic body; plural bump electrodes formed at the other end of said plural leads; and a resin body for sealing said connection terminals of said semiconductor chip and one end of said leads; wherein said insulating tape comprises a first part arranged over said main surface of said semiconductor chip, and a second part protruding beyond said semiconductor chip in the vicinity of the periphery of said semiconductor chip wherein said plural connection terminals are arranged; and further comprising an unconnected lead which is not connected to said connection terminals of said semiconductor chip, and said unconnected lead is bent towards said connection terminals. 5. A semiconductor device comprising:
a semiconductor chip including plural semiconductor elements on its main surface and plural connection terminals, said plural connection terminals being arranged on the periphery of said semiconductor chip; an elastic body arranged on the main surface of said semiconductor chip leaving said connection terminals exposed; an insulating tape formed on said elastic body comprising openings in an area where said connection terminals are arranged; plural leads formed on the surface of said insulating tape, in which one end is electrically connected to said terminals and the other ends are arranged on said elastic body; plural bump electrodes formed at the other end of said plural leads; and a resin body for sealing said connection terminals of said semiconductor chip and one end of said leads; wherein said insulating tape comprises a first part arranged over said main surface of said semiconductor chip, and a second part protruding beyond said semiconductor chip in the vicinity of the periphery of said semiconductor chip wherein said plural connection terminals are arranged, and wherein said elastic body is formed from a porous fluoride resin comprising an adhesive layer on its top surface and under surface. 6. A semiconductor device according to claim 5, wherein said elastic body comprises a skeleton layer formed from a three-dimensional mesh structure.
7. A semiconductor device comprising a semiconductor chip having connection terminals provided on the outer periphery of its main surface, comprising:
an elastic body arranged on the main surface of said semiconductor chip having openings for exposing said connection terminals, said elastic body comprising elastic body protruding parts which protrude beyond said openings and said semiconductor chip a thin film wiring substrate comprising a substrate body having wiring whereof one end is electrically connected to said connection terminals via leads and the other ends are electrically connected to bump electrodes which are external terminals, and comprising substrate protruding parts having openings which leave said connection terminals exposed and which protrude beyond said openings and said semiconductor chip; and sealing parts which seal said connection terminals of said semiconductor chip and seal said leads of said thin film wiring substrate; said substrate body and said substrate protruding parts of said thin film wiring substrate being formed in a one-piece construction, and said thin film wiring substrate and said elastic body being formed in approximately the same size, wherein either one of or both adhesive layers in said elastic body comprises a coloring agent. 8. A semiconductor device comprising:
a semiconductor chip having a quadrilateral main surface, a first end side of the main surface, a second, opposing end side of the main surface, a first row of connection terminals arranged parallel to and near the first end side on the main surface, a second row of connection terminals arranged parallel to and near the second end side on the main surface, and a plurality of semiconductor elements formed between the first row of connection terminals and second row of connection terminals on the main surface; a wiring substrate having a first portion arranged over the main surface of said semiconductor chip such that a rear surface of said wiring substrate is facing towards the main surface of said semiconductor chip, a second portion protruding from the first end side of the main surface of said semiconductor chip, and a third portion protruding from the second end side of the main surface of said semiconductor chip, wherein said wiring substrate has a first opening positioned over the first row of connection terminals and a second opening positioned over the second row of connection terminals; a plurality of wirings formed on the first portion of said wiring substrate; a plurality of bump electrodes arranged on the first portion of said wiring substrate, respectively, and each being electrically connected to a connection terminal at a corresponding one of the first and second rows of connection terminals through one of said wirings; and a resin body having a first portion sealing the first row of connection terminals and the first opening, and a second portion sealing the second row of connection terminals and the second opening, wherein a rear surface of the semiconductor chip, opposite of the main surface thereof, remains exposed, wherein the first portion of said resin body is formed as a bridge in the first opening of said wiring substrate and is formed as a bridge between a side face of said semiconductor chip, adjacent to the first end side, and a rear surface of the second portion of the wiring substrate, and wherein the second portion of said resin body is formed as a bridge in the second opening of said wiring substrate and is formed as a bridge between a side face of said semiconductor chip, adjacent to the second end side, and a rear surface of the third portion of said wiring substrate. 9. A semiconductor device according to claim 8, wherein the bridging surface of the first and second portion of the resin body remains exposed.
10. A semiconductor device according to claim 8, wherein the second and third parts of said wiring substrate function as a dam for preventing the flow of said resin body.
wherein a width of the first opening is larger than a distance between the second portion of said wiring substrate and the side face of said semiconductor chip adjacent the first end side, and wherein a width of the second opening is larger than a distance between the third portion of said wiring substrate and the side face of the semiconductor chip adjacent the second end side. 12. A semiconductor device according to claim 10,
wherein the first portion of said resin body is a sealing part which is made of potting method through the first opening, and wherein the second portion of said resin body is a sealing part which is made of potting method through the second opening. 13. A semiconductor device according to claim 8, wherein said bump electrodes are not provided on the second and third portions of said wiring substrate.
a semiconductor chip having a quadrilateral main surface, a first end side of the main surface, a second, opposing end side of the main surface, a first row of connection terminals arranged parallel to and near the first end side of the main surface, a second row of connection terminals arranged parallel to and near the second end side on the main surface, and a plurality of semiconductor elements formed between the first row of connection terminals and second row of connection terminals on the main surface; an elastic body arranged on the main surface of said semiconductor chip between the first row of connection terminals and the second row of connection terminals, leaving the connection terminals exposed; an insulating tape having a first portion arranged over the main surface of said semiconductor chip, through said elastic body such that a rear surface of said insulating tape is facing towards the main surface of said semiconductor chip, a second portion protruding from the first end side of the main surface of said semiconductor chip, a third portion protruding from the second end side of the main surface of the semiconductor chip, a first opening formed over the first row of connection terminals between the first and second portions, and a second opening formed over the second row of connection terminals between the first and third portions; a plurality of leads connected, respectively, to the first and second rows of connection terminals and extended over said elastic body; a plurality of bump electrodes electrically connected to the first and second rows of connection terminals through the leads, respectively, arranged on the first portion of said insulating tape; and a resin body having a first portion and a second portion, wherein the first portion of said resin body sealing the first row of connection terminals, the first opening, the leads connected to the first row of connection terminals, and a side face, adjacent to the first side, of said semiconductor chip, wherein the second portion of said resin body sealing the second row of connection terminals, the second opening, the leads connected to the second row of connection terminals, and a side face, adjacent to the second end side, of said semiconductor chip, and wherein the bump electrodes, electrically connected to the connection terminals, are arranged on the first portion of the insulating tape, and are not arranged on the second and third portions of said insulating tape. 15. A semiconductor device according to claim 14,
wherein the first portion of said resin body is formed as a bridge in the first opening of said insulating tape, and wherein the second portion of said resin body is formed as a bridge in the second opening of said insulating tape. 16. A semiconductor device according to claim 15,
wherein the first portion of said resin body is formed as a bridge between a side face, adjacent to the first end side, of said semiconductor chip and a rear surface of the second portion of said insulating tape, and wherein the second portion of said resin body is formed as a bridge between a side face, adjacent to the second end side, of the semiconductor chip and a rear surface of the third portion of said insulating tape. 17. A semiconductor device according to claim 16, wherein a rear surface of said semiconductor chip, opposite of the main surface thereof, remains exposed.
wherein a width of the first opening is larger than a distance between the second portion of said insulating tape and the side face of said semiconductor chip adjacent the first end side, and wherein a width of the second opening is larger than a distance between the third portion of said insulating tape and the side face of said semiconductor chip adjacent the second end side. 19. A semiconductor device according to claim 18,
wherein the first portion of said resin body is a sealing part which is made of potting method through the first opening, and wherein the second portion of said resin body is a sealing part which is made of potting method through the second opening. 20. A semiconductor device according to claim 14, wherein a rear surface of said semiconductor chip, opposite of the main surface thereof, remains exposed.
21. A semiconductor device according to claim 14, wherein the second and third parts of said insulating tape function as a dam for preventing the flow of said resin body, respectively.
22. A semiconductor device according to claim 14, wherein said elastic body is formed of a porous material.
23. A semiconductor device according to claim 14, wherein said resin body provides sealing parts and is made of potting method.
Structures of CSPs studied by the inventors for comparison purposes are described, for example, in �Nikkei Microdevices� Apr. 1, 1997, No. 142, pp. 44-53, published by Nikkei BP Co. on Apr. 1, 1997, and, in particular, the next generation CSP structure (comparison examples) described in FIG. 6, on page 48 thereof. This CSP comprises a semiconductor chip having electrode pads formed on its main surface, bump electrodes which are external terminals arranged over the main surface of the semiconductor chip, and a contour ring outside the semiconductor chip.
In other words, there was a problem in that the contour shape of the CSP was not fixed.
As the substrate protruding parts are not separate from the substrate body but are formed together with it in a one-piece construction, the substrate protruding parts need not be formed from costly materials.
As a result, the cost of manufacturing the semiconductor device is reduced.
The semiconductor device of this invention is a chip size structure having connection terminals provided on the outer periphery of its main surface. It comprises an elastic structure arranged on the main surface of the semiconductor chip comprising elastic protruding parts having openings which leave the connection terminals exposed, a thin film wiring substrate comprising a substrate body having wiring whereof one end is electrically connected to the aforesaid terminals via leads and the other ends are electrically connected to bump electrodes which are external terminals, and comprising substrate protruding parts having openings which leave the connection terminals exposed and which protrude beyond the openings and the semiconductor chip, and sealing parts which seal the connection terminals of the semiconductor chip and seal the leads of the thin film wiring substrate, the substrate body and the substrate protruding parts of the thin film wiring substrate being formed in a one-piece construction, and the thin film wiring substrate and the elastic structure having substantially the same size.
The method of manufacturing a semiconductor device according to this invention comprises a step for preparing a thin film wiring substrate which is a chip size structure having connection terminals provided on the outer periphery of its main surface, comprising a substrate body with wiring, and comprising substrate protruding parts which protrude beyond openings in which leads are connected to this wiring and formed in a one-piece construction with the substrate body, a step for joining an elastic structure and the substrate body of the thin film wiring substrate, a step for joining the main surface of the semiconductor chip and the elastic structure so as to expose the connection terminals of the semiconductor chip in the openings of the thin film wiring substrate, a step for electrically connecting the connection terminals of the semiconductor chip and the corresponding leads of the thin film wiring substrate, a step for sealing the connection terminals of the semiconductor chip and the leads of the thin film wiring substrate using a sealing resin comprising a low silica material so as to form sealing parts, a step for electrically connecting the wiring of the substrate body so as to form bump electrodes, and a step for simultaneously cutting the substrate protruding parts and sealing parts formed therein to a desired contour size.
The method of manufacturing a semiconductor device according to this invention comprises a step for preparing a thin film wiring substrate which is a chip size structure having connection terminals provided on the outer periphery of its main surface, comprising a substrate main body having wiring joined to an elastic structure and openings in which leads are connected to the wiring, wherein the substrate body is supported in a substrate frame by supporting parts of the elastic structure, a step for joining the main surface of the semiconductor chip and the elastic structure so as to leave the connection terminals of the semiconductor chip exposed in the openings of the thin film wiring substrate, a step for electrically connecting the connection terminals of the semiconductor chip and the corresponding leads of the thin film wiring substrate, a step for resin sealing the connection terminals of the semiconductor chip and the leads of the thin film wiring substrate so as to form sealing parts, a step for electrically connecting the wiring of the substrate body so as to form bump electrodes, a step for cutting the supporting part of the elastic structure so as to separate the substrate body from the substrate frame, and a step for exposing the exposed parts of the elastic structure.
FIGS. 2(a) to 2(c) are diagrams showing the structure of the semiconductor device shown in FIG. 1, in which FIG. 2(a) is a cross-sectional view through a line A�A in FIG. 1,
FIG. 2(b) is a cross-sectional view through a line B�B in FIG. 1, and
FIG. 2(c) is a cross-sectional view through a line C�C in FIG. 1.
FIG. 5 is a chart showing typical processing conditions in each stage of the production process shown in FIG. 4
FIGS. 9(a) and 9(b) are diagrams each showing a typical method of manufacturing the semiconductor device (CSP) according to the first embodiment of this invention, in which
FIG. 9(a) is a partial plan view showing an elastomer attachment, and
FIG. 9(b) is a partial plan view showing a semiconductor chip attachment.
FIGS. 15(a) to 15(c) are diagrams showing the structure of the semiconductor device shown in FIG. 14, in which
FIG. 15(a) is a cross-sectional view through a line A�A in FIG. 14,
FIG. 15(b) is a cross-sectional view through a line B�B in FIG. 14, and
FIG. 15(c) is a cross-sectional view through a line C�C in FIG. 14.
FIGS. 17(a) to 17(c) are diagrams showing the structure of the semiconductor device shown in FIG. 16, in which
FIG. 17(a) is a cross-sectional view through a line A�A in FIG. 16,
FIG. 17(b) is a cross-sectional view through a line B�B in FIG. 16, and
FIG. 17(c) is a cross-sectional view through a line C�C in FIG. 16.
FIGS. 19(a) to 19(c) are diagrams showing the structure of the semiconductor device shown in FIG. 18, in which
FIG. 19(a) is a cross-sectional view through a line A�A in FIG. 18,
FIG. 19(b) is a cross-sectional view through a line B�B in FIG. 18, and
FIG. 19(c) is a cross-sectional view through a line C�C in FIG. 18.
FIGS. 21(a) to 21(c) are diagrams showing the structure of the semiconductor device shown in FIG. 20, in which
FIG. 21(a) is a cross-sectional view through a line A�A in FIG. 20,
FIG. 21(b) is a cross-sectional view through a line B�B in FIG. 20, and
FIG. 21(c) is a cross-sectional view through a line C�C in FIG. 20.
FIGS. 23(a) to 23(c) are diagrams showing the structure of the semiconductor device shown in FIG. 22, in which
FIG. 23(a) is a cross-sectional view through a line A�A in FIG. 22,
FIG. 23(b) is a cross-sectional view through a line B�B in FIG. 22, and
FIG. 23(c) is a cross-sectional view through a line C�C in FIG. 22.
FIGS. 25(a) to 25(c) are diagrams showing the structure of the semiconductor device shown in FIG. 24, in which
FIG. 25(a) is a cross-sectional view through a line A�A in FIG. 24,
FIG. 25(b) is a cross-sectional view through a line B�B in FIG. 24, and
FIG. 25(c),is a cross-sectional view through a line C�C in FIG. 24.
FIG. 25(d) is the front view of the structure of the semiconductor device shown in FIG.24.
FIG. 25(e) is the side view of the structure of the semiconductor device shown in FIG.24.
FIGS. 29(a) to 29(c)are diagrams showing the structure of the semiconductor device shown in FIG. 28, in which
FIG. 29(a) is a cross-sectional view through a line A�A in FIG. 28,
FIG. 29(b) is a cross-sectional view through a line B�B in FIG. 28, and
FIG. 29(c) is a cross-sectional view through a line C�C in FIG. 28.
FIGS. 31(a) to 31(c) are diagrams showing the structure of the semiconductor device shown in FIG. 30, in which
FIG. 31(a) is a cross-sectional view through a line A�A in FIG. 30,
FIG. 31(b) is a cross-sectional view through a line B�B in FIG. 30, and
FIG. 31(c) is a cross-sectional view through a line C�C in FIG. 30.
FIGS. 33(a) to 33(c) are diagrams showing the structure of the semiconductor device shown in FIG. 32, in which
FIG. 33(a) is a cross-sectional view through a line A�A in FIG. 32,
FIG. 33(b) is a cross-sectional view through a line B�B in FIG. 32, and
FIG. 33(c) is a cross-sectional view through a line C�C in FIG. 32.
FIGS. 35(a) to 35(c) are diagrams showing the structure of the semiconductor device shown in FIG. 34, in which
FIG. 35(a) is a cross-sectional view through a line A�A in FIG. 34,
FIG. 35(b) is a cross-sectional view through a line B�B in FIG. 34, and
FIG. 35(c) is a cross-sectional view through a line C�C in FIG. 34.
FIGS. 37(a) to 37(c) are diagrams showing the structure of the semiconductor device shown in FIG. 36, in which
FIG. 37(a) is a cross-sectional view through a line A�A in FIG. 36,
FIG. 37(b) is a cross-sectional view through a line B�B in FIG. 36, and
FIG. 37(c) is a cross-sectional view through a line C�C in FIG. 36.
FIGS. 39(a) to 39(c) are diagrams showing the structure of the semiconductor device shown in FIG. 38, in which
FIG. 39(a) is a cross-sectional view through a line A�A in FIG. 38,
FIG. 39(b) is a cross-sectional view through a line B�B in FIG. 38, and
FIG. 39(c) is a cross-sectional view through a line C�C in FIG. 38.
FIGS. 40(a), 40(b), 40(c) are diagrams each showing an unconnected lead in the semiconductor device according to the fourteenth embodiment of this invention, in which
FIG. 40(a) is a cross-sectional view when the unconnected lead is deformed, and
FIGS. 40(b), 40(c) are cross-sectional views when the unconnected lead is not deformed.
FIGS. 43(a), 43(b), 43(c), 43(d) are enlarged partial cross-sections each showing an example of a lead tip processing sequence in a method of manufacturing a semiconductor device according to the sixteenth embodiment of this invention.
FIGS. 44(a), 44(b), 44(c) are enlarged partial cross-sections showing another example of a lead tip processing sequence in a method of manufacturing a semiconductor device according to the sixteenth embodiment of this invention, for comparison with the lead tip processing sequence of FIG. 43.
FIGS. 45(a), 45(b), 45(c) are enlarged partial cross-sections showing another example of a lead tip processing sequence in a method of manufacturing a semiconductor device according to the sixteenth embodiment of this invention, for comparison with the lead tip processing sequence of FIG. 43.
FIGS. 48(a) to 48(e) are diagrams showing typical elastomer compositions in a semiconductor device according to the eighteenth embodiment of this invention, in which FIGS. 48(a) to 48(d) show a 3-layer structure, FIG. 48(e) shows a 5-layer structure.
FIGS. 52(a), 52(b), 52(c) are diagrams showing the structure of the semiconductor device shown in FIG. 51, in which
FIG. 52(a) is a cross-sectional view through a line A�A in FIG. 51,
FIG. 52(b) is a cross-sectional view through a line B�B in FIG. 51, and
FIG. 52(c) is a cross-sectional view through a line C�C in FIG. 51.
FIGS. 53(a), 53(b) are enlarged partial cross-sections showing the structure of the semiconductor device shown in FIG. 52, in which
FIG. 53(a) is a diagram showing a part D in FIG. 52(b), and
FIG. 53(b) is a diagram showing a part E in FIG. 52(c).
FIGS. 54(a) to 54(f) are diagrams showing an example of a method of manufacturing a thin film wiring substrate used in the semiconductor device according to the twenty-first embodiment of this invention, in which
FIGS. 54(a), 54(c), 54(e) are partial plan views, and
FIGS. 54(b), 54(d), 54(f) are respectively cross-sections through a line A�A.
FIGS. 55(a) to 55(d) are diagrams showing an example of a method of manufacturing a thin film wiring substrate used in the semiconductor device according to the twenty-first embodiment of this invention, in which
FIGS. 55(a), 55(c) are partial plan views, and
FIGS. 55(b), 55(d) are respectively cross-sections through a line A�A.
FIGS. 56(a) to 56(f) are diagrams showing an example of a method of manufacturing a thin film wiring substrate used in the semiconductor device according to the twenty-first embodiment of this invention, in which
FIGS. 56(a), 56(d) are partial plan views,
FIGS. 56(b), 56(e) are respectively cross-sections through a line A�A, and
FIGS. 56(c), 56(f) are respectively cross-sections through a line B�B.
FIGS. 57(a) to 57(f) are diagrams showing an example of a method of manufacturing a thin film wiring substrate used in the semiconductor device according to the twenty-first embodiment of this invention, in which
FIGS. 57(a), 57(d) are partial plan views,
FIGS. 57(b), 57(e) are respectively cross-sections through a line A�A, and
FIGS. 57(c), 57(f) are respectively cross-sections through a line B�B.
FIGS. 58(a) to 58(f) are diagrams showing an example of a method of manufacturing a thin film wiring substrate used in the semiconductor device according to the twenty-first embodiment of this invention, in which
FIGS. 58(a), 58(d) are partial plan views,
FIGS. 58(b), 58(e) are respectively cross-sections through a line A�A, and
FIGS. 58(c), 58(f) are respectively cross-sections through a line B�B.
FIGS. 59(a), 59(b), 59(c) are diagrams showing an example of a method of manufacturing a thin film wiring substrate used in the semiconductor device according to a twenty-second embodiment of this invention, in which
FIG. 59(a) is a side view,
FIG. 59(b) is a plan view, and
FIG. 59(c) is a front view.
FIGS. 60(a), 60(b), 60(c), 60(d) are diagrams showing an example of the structure of a thin film wiring substrate according to a twenty-third embodiment of this invention, in
FIG. 60(a) is a base view,
FIG. 60(b) is a side view,
FIG. 60(c) is a plan view, and
FIG. 60(d) is a front view.
FIGS. 62(a), 62(b), 62(c) are diagrams showing cross-sections through the plan view shown in FIG. 61(a), in which
FIG. 62(a) is a cross-section showing the plane A�A,
FIG. 62(b) is a cross-section showing the plane B�B, and
FIG. 62(c) is a cross-section showing the plane C�C.
FIGS. 63(a), 63(b), 63(c) are diagrams showing an example of a state when sealing is complete in a manufacturing method according to the twenty-third embodiment of this invention, in which
FIG. 63(a) is a plan view,
FIG. 63(b) is a side view, and
FIG. 63(c) is a base view.
FIGS. 65(a) to 65(e) are diagrams each showing an example structure of a semiconductor device according to a twenty-fourth embodiment of this invention, in which
FIG. 65(a) is a base view,
FIG. 65(b) is a side view,
FIG. 65(c) is a plan view,
FIG. 65(d) is a front view, and
FIG. 65(e) is a cross-section through a line C�C in FIG. 65(c).
FIGS. 66(a), 66(b), 66(c) are diagrams showing an example structure of a semiconductor device according to a twenty-fifth embodiment of this invention, in which
FIG. 66(a) is a plan view,
FIG. 66(b) is a side view, and
FIG. 66(c) is a base view.
FIGS. 69(a), 69(b) are diagrams each showing an example of a state when sealing is complete in a manufacturing method according to the twenty-fifth embodiment of this invention, in which
FIG. 69(a) is a base view, and
FIG. 69(b) is a base view showing a semiconductor chip removed.
FIG. 1 is a plan view through the sealing parts of a typical structure of a semiconductor device (CSP) according to a first embodiment of this invention. FIGS. 2(a) to 2(c) are diagrams showing the structure of the semiconductor device shown in FIG. 1. FIG. 2(a) is a cross-sectional view through a line A�A in FIG. 1, FIG. 2(b) is a cross-sectional view through a line B�B in FIG. 1, FIG. 2(c) is a cross-sectional view through a line C�C in FIG. 1. FIGS. 3 (a,b,c,d) are specification tables showing example specifications of parts used in the semiconductor device shown in FIG. 1. FIG. 4 is a manufacturing sequence showing a typical process for manufacturing the semiconductor device shown in FIG. 1. FIG. 5 is a chart showing typical processing conditions in each stage of the production process shown in FIG. 4. FIG. 6, FIG. 7 and FIG. 8 are partial plan views showing a typical method of manufacturing a thin film wiring substrate used for a semiconductor device (CSP) according to the first embodiment of this invention. FIGS. 9(a) 9(b) are diagrams each showing a typical method of manufacturing the semiconductor device (CSP) according to the first embodiment of this invention. FIG. 9(a) is a partial plan view showing an elastomer attachment, FIG. 9(b) is a partial plan view showing a semiconductor chip attachment. FIG. 10 is a partial plan view showing an example of a cutting position in a method of manufacturing a semiconductor device (CSP) according to the first embodiment of this invention. FIGS. 11(a), 11(b) are perspective views showing an example of a lead cutting method in a method of manufacturing the semiconductor device (CSP) according to the first embodiment of this invention. FIGS. 12(a), 12(b), 12(c) are perspective views showing an example of an elastomer attachment state in a method of manufacturing a semiconductor device (CSP) according to the first embodiment of this invention. FIGS. 13(a), 13(b) are perspective views showing an example of a lead bonding method in a method of manufacturing a semiconductor device (CSP) according to the first embodiment of this invention. FIG. 27 is an enlarged partial view showing the detailed structure of the thin film wiring substrate shown in FIG. 8.
A semiconductor device (CSP11) according to the first embodiment shown by FIG. 1 and FIG. 2 is a small structure whereof the package size is near the chip size. It comprises a semiconductor chip 1 having a main surface 1 a and an electrode pad 1 b (connection terminal or bonding pad) 1 b formed on the outer peripheral part of the main surface 1 a, and bump electrodes 2 which are external terminals arranged on the inside of the semiconductor chip 1. This structure, wherein a pad is formed on the periphery of the chip and bump electrodes are arranged inside the chip, will hereafter be referred to as a peripheral pad fan-in CSP.
Describing the structure of this CPS11, it comprises an elastomer 3 (elastic structure) arranged on the main surface 1 a of the semiconductor chip 1 so as to leave electrode pads 1 b exposed, a thin film wiring substrate 4 comprising a substrate main body 4 a provided with wiring 4 d of which one end is electrically connected to the electrode pads 1 b of the semiconductor chip 1 via leads 4 c and the other ends are electrically connected to the bump electrodes 2, openings 4 e for exposing the electrode pads 1 b, and substrate protruding parts 4 b which protrude beyond these openings 4 e and the semiconductor chip 1, and sealing parts 5 which seal the electrode pads 1 b of the semiconductor chip 1 and seal the leads 4 c of the thin film wiring substrate 4, the substrate body 4 a and the substrate protruding parts 4 b of the thin film wiring substrate 4 being formed in a one-piece construction. (For the purpose of this invention, �wiring� shall be understood to mean parts formed on the tape, and �leads� shall be understood to mean parts protruding from the tape including the wiring.)
In this first embodiment, plural electrode pads 1 b (herein, six at one side) are disposed on the periphery of each of the two short sides at right angles (hereinafter referred to as the short side direction) to the longitudinal direction of the main surface 1 a of the rectangular semiconductor chip 1, and twelve bump electrodes 2 which are external terminals are therefore disposed in a grid shape covering a plan view area over the main surface of the semiconductor chip 1.
Twelve bump lands 4 f (FIG. 8(a)) which are electrically connected to the wiring 4 d and on which the bump electrodes 2 are mounted, are provided in the substrate body 4 a. The elastomer 3 is an insulating elastic material which supports the semiconductor chip 1, and is arranged between the thin film wiring substrate 4 and semiconductor chip 1. The elastomer 3 according to the first embodiment comprises protruding parts 3 b (elastic protruding parts) which protrude beyond the semiconductor chip 1. After assembling the CSP11, a predetermined side faces 3 a of the elastomer 3 (herein, the two side faces 3 a in the same direction as the longitudinal direction of the semiconductor chip 1) are exposed to the outside.
The specification of each part of the CSP11 (materials, dimensions and thickness, etc.) will now be described referring to FIGS. 3(a,b,c,d). It should however be understood that these specifications are only given as examples, and the invention is not to be construed as being limited in any way by them.
The elastomer 3 is a three-layer structure (FIG. 47) comprising a base layer (skeleton layer 3 d, referred to also as core layer) having adhesive layers 3 e on both sides. Examples of its application are specification {circle around (1)} and specification {circle around (2)} shown in FIGS. 3(a,b,c,d). Details of specification {circle around (1)} are given in Japanese Patent Application No. Hei 9-149106 and details of specification {circle around (2)} are given in Japanese Patent Application No. Hei 8-136159.
From the viewpoints of porosity and water repelling properties, it is also desirable that the base layer (skeleton layer 3 d) of the elastomer 3 is formed of a porous fluoride resin, i.e. it is desirable to use the elastomer of specification {circle around (1)}.
The sealing resin, which is the sealing material for forming the sealing parts 5, has the specification {circumflex over (1)} or the specification {circle around (1)} shown in FIGS. 3(a,b,c,d).
During cure bake after sealing, voids tend to form in the solvent type liquid resin when the solvent vaporizes, and it is therefore desirable to use the resin of specification {circle around (1)}.
As the substrate protruding parts 4 b protrude beyond the openings 4 e in the thin film wiring substrate 4, the sealing parts 5 may be formed as a bridge between the substrate protruding parts 4 b and the semiconductor chip 1 when the sealing resin is applied via the openings 4 e. As a stable seal is obtained sealing properties are improved, and as a result, humidity resistance is more reliable.
Next, twelve bump openings 4 j and two wiring join holes 4 e on both sides are formed by stamping as shown in FIG. 7(a), and the copper foil 4 h is laminated on the tape base material 4 g as shown in FIG. 7(b).
After etching the copper foil 4 h to form the wiring pattern, the copper foil 4 h is gold plated. The specification of this gold plating is that of the wiring plating shown in FIGS. 3(a,b,c,d). It may be gold plating having a thickness of 1.5 μm (wiring plating {circle around (1)} shown in FIGS. 3(a,b,c,d)), gold/nickel differential thickness plating (wiring plating {circle around (2)} shown in FIGS. 3(a,b,c,d)), or another type of plating.
Positioning holes 4 p for positioning during cutting are provided outside the upper and lower long holes 4 q of the substrate body 4 a (according to this embodiment a total of three holes is provided, i.e. one upper one and two lower ones, but there is no limit on the number of these positioning holes 4 p if they are provided outside both the upper and lower long holes 4 q. Recognition patterns 4 n formed of the same copper foil as the wiring pattern are also provided in these upper and lower long holes 4 q of the substrate body 4 a. These recognition patterns 4 n are used to recognize the position of the thin film wiring substrate 4 during cutting, etc., and are such that they can be recognized also from the reverse side of the thin film wiring substrate 4 (side on which there is no wiring pattern) during bonding. Specifically, they straddle the ends of the long holes 4 q so that they can be recognized from the top surface and under surface of the thin film wiring substrate 4.
It is therefore desirable that the value of P lies within a P value predetermined range of 0≦P≦300 μm, and preferably 0≦P≦100 μm, so that the escape path of the volatile gases is not obstructed by the substrate body 4 a, and so that the volatile gases produced can be released outside the sealing material.
It is therefore desirable that the position of the edge of the elastomer 3 relative to the edge of the substrate body 4 a is within a Q value predetermined range of for example 0≦Q≦100 μm, and preferably 0≦Q≦50 μm, so that correct bonding of the leads 4 c can be performed.
Subsequently, chip supply 23 (FIG. 4) is performed wherein the semiconductor chip 1 is supplied having the electrode pads 1 b on the outer periphery of the main surface la as shown in FIG. 2(a). Chip attachment 24 shown in FIG. 4 is then performed based on the chip attachment conditions shown in FIG. 5.
Herein, in the chip attachment 24, the main surface la of the semiconductor chip 1 is joined to the elastomer 3 as shown in FIG. 2(a) leaving the electrode pads 1 b of the semiconductor chip 1 exposed in the openings 4 e of the thin film wiring substrate 4, as shown in FIG. 1.
Next, inner lead connections 26 shown in FIG. 4 is performed based on the inner lead connection conditions shown in FIG. 5. Two sets of inner lead connection conditions {circle around (1)} and {circle around (2)} are shown in FIG. 5, however the inner lead connection conditions are not limited to this.
After bonding, the lead 4 c is pushed up by the bonding tool 7 so that it is just above the electrode pad 1 b. If a value obtained by dividing the stress produced in the taper-shaped tip of the lead 4 c by the stress produced at the edge of the substrate body 4 a is defined as a bending stress ratio alpha, this bending stress ratio α is given by the following expression from the dimensions of the taper-shaped lead 4 c: α=:L�(K−J)/(M�K) (FIG. 13(a)) The dimensions and shape of the lead 4 c are therefore designed such that the bending stress ratio α is within the range 1.0 to 1.75.
Specifically, a resin sealing 28 shown in FIG. 4 is performed using a sealing material (sealing resin) shown in the sealing material specifications of FIGS. 3(a,b,c,d).
Next, a sealing material cure bake 29 shown in FIG. 4 is performed based on the post-seal curing conditions shown in FIG. 5 so as to harden the sealing parts 5.
Also, a pole supply 30 (FIG. 4) is performed for supplying a bump pole material shown in the bump pole specifications of FIGS. 3(a,b,c,d) to the bump openings 4 j (FIG. 7(a)).
FIG. 14 is a plan view through the sealing parts of a typical structure of a semiconductor device (CSP) according to a second embodiment of this invention. FIGS. 15(a) to 15(c) are diagrams showing the structure of the semiconductor device shown in FIG. 14. FIG. 15(a) is a cross-sectional view through a line A�A in FIG. 14, FIG. 15(b) is a cross-sectional view through a line B�B in FIG. 14, FIG. 15(c) is a cross-sectional view through a line C�C in FIG. 14.
A CSP15 (semiconductor device) according to the fifth embodiment is a peripheral pad fan-in CSP as is the CSP14 of the fourth embodiment shown in FIG. 18 and FIG. 19. It has a substantially identical structure to that of the CSP14, however a difference from the CSP14 of the fourth embodiment is that seal openings 4m are provided at positions corresponding to the two opposite side faces 1 c in the longitudinal direction of the semiconductor chip 1 (FIG. 21(c)) in the substrate protruding parts 4 b of the thin film wiring substrate 4 in addition to the openings 4 e exposing the electrode pads 1 b, as shown in FIG. 20.
Specifically, the elastomer 3 in the CSP16 comprises the two openings 3 c exposing the electrode pads 1 b, and elastomer protruding parts 3 b (elastic structure protruding parts) which protrude beyond these openings 3 c and the semiconductor chip Hence, when the elastomer 3 is attached to the thin film wiring substrate 4, the positions of the two openings 4 e and 3 c in these members can be aligned.
FIG. 28 is a plan view through the sealing parts of a typical structure of a semiconductor device (CSP) according to an eighth embodiment of this invention. FIGS. 29(a) to 29(c) are diagrams showing the structure of the semiconductor device shown in FIG. 28. FIG. 29(a) is a cross-sectional view through a line A�A in FIG. 28, FIG. 29(b) is a cross-sectional view through a line B�B in FIG. 28, FIG. 29(c) is a cross-sectional view through a line C�C in FIG. 28.
As sealing resin can be applied to four positions, i.e. one of the openings 3 c, one of the openings 4 e, the seal opening 3 f and the seal opening 4 m, from the same direction, the sealing step is made easier and productivity is improved.
In the CSP41, as the elastomer 3 is a porous fluoride resin, and as the thickness of the elastomer 3 directly underneath the semiconductor chip 1 can be made much smaller than that of the outer periphery of the semiconductor chip 1, the semiconductor chip 1 can be attached so that the side faces 1 c on the outer periphery of the semiconductor chip 1 are surrounded by the elastomer protruding parts 3 b. Hence, flow of sealing resin to the outside during the resin sealing step 28 of FIG. 4 is prevented by the elastomer protruding parts 3 b and it is unnecessary to cut the sealing resin, so the CSP41 may be made compact.
FIG. 36 is a plan view through the sealing parts of a typical structure of a semiconductor device (CSP) according to a twelfth embodiment of this invention. FIGS. 37(a) to 37(c) are diagrams showing the structure of the semiconductor device shown in FIG. 36. FIG. 37(a) is a cross-sectional view through a line A�A in FIG. 36, FIG. 37(b) is a cross-sectional view through a line B�B in FIG. 36, FIG. 37(c) is a cross-sectional view through a line C�C in FIG. 36.
A CSP43 (semiconductor device) according to the thirteenth embodiment is a peripheral pad fan-in CSP as is the CSP17 of the seventh embodiment shown in FIG. 24. It has a substantially identical structure to that of the CSP17, however a difference from the CSP17 of the seventh embodiment is that the electrode pads 1 b are provided on the peripheries of the four sides of the main surface 1 a of the semiconductor chip 1.
In this process, instead of making a connection with the bonding tool 7 in the bonding step, the lead 4 c is pressed down by the bonding tool 7 (i.e. in the direction of the main surface 1 a of the semiconductor chip 1) to the extent that it does not touch the electrode pad 1 b. In both FIGS. 40(b) and (c), the unconnected lead 35 is not bent.
First, FIG. 41 shows the case where the thin film wiring substrate 4 is single layer surface wired. FIG. 41(a) shows the case where the external structure of the semiconductor device is that of the tape (e.g. the CSP11 of the first embodiment). FIG. 41(b) shows the case where the external structure of the semiconductor device is that of a sealed contour (e.g. the CSP12 of the second embodiment). FIG. 41(c) shows the case where the external structure of the semiconductor device is that of the elastomer (e.g. the CSP17 of the seventh embodiment).
FIGS. 43(a),43(b), 43(c), 43(d) are enlarged partial cross-sections showing an example of a lead tip processing sequence in a semiconductor device manufacturing method according to a sixteenth embodiment of this invention, as follows:
First, in the comparative example shown in FIG. 44, as a distance P shown in FIG. 44(a) is relatively long, the bonding tool 7 is moved (lowered) to perform bonding as shown in FIG. 44(b), and then the resin sealing 28 (FIG. 4) is performed to form the sealing part 5 as shown in FIG. 44(c) without tip processing of the leads 4 c. In this case, as the distance P shown in FIG. 44(a) is relatively long, the whole tip of the lead 4 c after bonding is completely enclosed within the sealing part 5 as shown in FIG. 44(c).
In the comparative example shown in FIG. 45, the distance P shown in FIG. 45(a) is relatively short. The bonding tool 7 is moved (lowered) to perform bonding as shown in FIG. 45(b), and the resin sealing 28 (FIG. 4) is performed to form the sealing part 5 as shown in FIG. 44(c) without tip processing of the lead 4 c. In this case, as the distance P shown in FIG. 45(a) is relatively short, tip processing of the lead 4 c after bonding is not performed as shown in FIG. 45(b), so the tip of the lead 4 c after bonding protrudes beyond the sealing part 5 so that it is exposed as shown in FIG. 45(c).
When the tip processing of the lead 4 c is performed, the bonding tool 7 may first be raised by a predetermined amount (e.g. 5 to 100 μm, but preferably 10 to 60 μm) at the same time as the pressure of the bonding tool 7 is removed, and then displaced horizontally by the predetermined amount (e.g. 10 to 300 μm, but preferably 30 to 200 μm) in the direction of the tip of the lead 4 c. Regarding the tip processing of the lead 4 c, the bonding tool 7 may be moved by the predetermined amount (e.g. 10 to 300 μm, but preferably 30 to 200 μm) in the direction of the tip of the lead 4 c only when at least the distance P is relatively short compared to a length L of the projecting lead 4 c and a thickness E of the elastomer 3 (e.g. P≦L−E, but preferably P≦L−E−100 μm). When the conditions regarding P, L, E shown in FIG. 43(a) are not satisfied, it is not necessary to perform tip processing of the lead 4 c. It will moreover be appreciated that it is not particularly necessary to perform tip processing of the lead 4 c regardless of the distance P, length L and thickness E shown in FIG. 43(a).
According to the sixteenth embodiment, regarding connection of the lead 4 c, the tip of the extra length of the lead 4 c is prevented from protrudeing more than is necessary above the top surface (main surface 1 a) of the semiconductor chip 1 regardless of the positions of the electrode pad 1 b on the semiconductor chip 1 even when a lead 4 c that is longer the required length is bonded.
Specific examples of the specification of the colored elastomer 3 are the specification {circle around (1)} and specification {circle around (2)} shown in FIG. 46. The coloring agent used here is carbon.
In the colored elastomer specifications {circle around (1)} and {circle around (2)} shown in FIG. 46, the adhesive layer 3 e on both sides of the skeleton layer 3 d contains the coloring agent, however the invention is not limited to this arrangement and the adhesive layer 3 e on only one side may contain the coloring agent.
In the specifications {circle around (1)} and {circle around (2)} shown in FIG. 46 of the seventeenth embodiment, the adhesive layers 3 e contain the coloring agent, however the intermediate layer which is the skeleton layer 3 d may also contain the coloring agent, or both the adhesive layer 3 e and the skeleton layer 3 d may contain the coloring agent.
In the specifications {circle around (1)} and {circle around (2)} shown in FIG. 46, the coloring agent was carbon particles, however the coloring material is not limited to this and may be another inorganic pigment or organic dye.
In the specification {circle around (1)} and {circle around (2)} shown in FIG. 46, the coloring agent is black carbon, but the coloring agent may be red, blue, green, pink, yellow or another color, or an intermediate color.
Also, by incorporating the coloring agent in at least one of the adhesive layers 3 e rather than the skeleton layer 3 d of the elastomer 3, the elastomer 3 can be colored at low cost.
As a result, the rigidity of the elastomer 3 is also reduced, so the elastomer easily molds to the contour of the leads 4 c and the contact of the elastomer 3 is improved.
Herein, the materials of each component of the elastomer 3 are not limited to those of the eighteenth embodiment shown in FIG. 47 and FIG. 48, and the elastomer may also be a multi-layer structure wherein the number of layers is not limited to three or five.
FIGS. 49(a), (b) are diagrams showing typical thicknesses of the skeleton layer and adhesive layers in an elastomer of a semiconductor device according to a nineteenth embodiment of this invention.
FIG. 49(b) shows the case where the tape side adhesive layer 3 g (adhesive layer adjacent to thin film wiring substrate) is thicker than the chip side adhesive layer 3 h. As an example, the thickness of the tape side adhesive layer 3 g is 75 μm, the thickness of the chip side adhesive layer 3 h is 50 μm, and the thickness of the skeleton layer which is the intermediate layer is 25 μm.
In the CSP17 shown in FIG. 50, the wiring width of connecting parts 4s which connect with the bump lands 4 f of the wiring 4 d formed in the thin film wiring substrate 4, is formed wider than the wiring width of the wiring 4 d at points remote from the connecting parts 4 s, and the wiring width of the connecting parts 4 s progressively becomes narrower with increasing distance from the bump lands 4 f. Specifically, in the wiring 4 d reaching the leads 4 c from the bump land 4 f formed in the tape base material 4 g (FIG. 27), the wiring width of the connecting parts 4 s which connect with the bump lands 4 f is wider than the wiring width of the wiring 4 d at points distant from these connecting parts 4 s, these parts tapering off so that the wiring width of the connecting part 4 s gradually becomes narrower with increasing distance from the bump lands 4 f. In the CSP17 shown in FIG. 50, the wiring width of all twelve of the connecting parts 4 s is formed wide, and these wide connecting parts 4 s progressively become narrower with increasing distance from the bump lands 4 f. The remaining features of the construction of the semiconductor device (CSP) according to the twentieth embodiment are identical to those of the CSP of the first to nineteenth embodiments, so their description will not be repeated.
However, it is not absolutely necessary to form the connecting parts 4 s described in the twentieth embodiment, and they may be omitted.
Hence, the elastomer 3 is attached to the thin film wiring substrate 4, the body of the elastomer 3 is attached to the substrate body 4 a of the thin film wiring substrate 4, and the eight supporting members 3 j of the elastomer 3 are arranged to straddle the long holes 4 q of the thin film wiring substrate 4 so as to attach them to the substrate frame 4 t. Next, four suspension members 4u supporting the substrate body 4 a shown in FIG. 55(a) are cut so that the substrate body 4 a is supported in the substrate frame 4 t by the supporting members 3 j of the elastomer 3.
The resin sealing 28 maybe performed also by the transfer mold method.
Next, a bump pole material is supplied to the bump openings 4 j of the substrate body 4 a, and the bump electrodes 2 are formed as shown in FIGS. 58(a)-(c) by passing the assembly through a reflow furnace, not shown.
In other words, in the CSP52, all the side faces of the elastomer 3 are exposed as the exposed parts 3 i after manufacture is complete, as shown in FIG. 59(a).
FIGS. 60(a) to 60(d) are plan views each showing a typical structure of a semiconductor device according to a twenty-third embodiment of this invention. FIG. 60(a) is a plan view, FIG. 60(b) is a side view, FIG. 60(c) is a plan view, FIG. 60(d) is a front view. FIGS. 61(a) to 61(b) are diagrams each showing an example of a state when sealing is complete in a method of manufacturing the semiconductor device according to the twenty-third embodiment of this invention. FIG. 61(a) is a plan view, FIG. 61(b) is a base plan view. FIGS. 62(a) to 62(c) show cross-sections of the plan view shown in FIG. 61(a). FIGS. 62(a) is a cross-sectional view through a line A�A, 62(b) is a cross-sectional view through a line B�B, 62(c) is a cross-sectional view through a line C�C. FIGS. 63(a) to 63(c) are diagrams each showing an example of a state when sealing is complete in a method of manufacturing the semiconductor device according to the twenty-third embodiment of this invention. FIG. 63(a) is a plan view, FIG. 63(b) is a side view, FIG. 63(c) is a base plan view. FIG. 64 is a schematic diagram showing an example of a gas release state in the semiconductor device according to the twenty-third embodiment.
The advantages of the CSP53 of the twenty-third embodiment and of its method of manufacture are as follows.
FIGS. 65(a) to 65(e) is a diagram of a typical structure of a semiconductor device according to a twenty-fourth embodiment of this invention. FIG. 65(a) is a base plan view, FIG. 65(b) is a side view, FIG. 65(c) is a plan view, FIG. 65(d) is a front view, FIG. 65(e) is a section through a line C�C in (c).
A CSP54 (semiconductor device) according to the twenty-fourth embodiment is a peripheral pad type fan-in CSP as is the CSP51 of the twenty-first embodiment shown in FIG. 51. It has a substantially identical structure to that of the CSP51, however differences from the CSP51 of the twenty-first embodiment are that openings 4 v for exposing the elastomer 3 are provided in the thin film wiring substrate 4 as shown in FIGS. 65(c), 65(e), and that there are no positions exposing the elastomer 3 other than the openings 4 v as shown in FIG. 65.
As a result, when the CSP54 is assembled, the elastomer 3 is exposed via these openings 4 v. Therefore, the exposed parts 3 i of the elastomer 3 are formed by the openings 4 v. In the CSP54, there are no positions exposing the elastomer 3 other than the openings 4 v. In other words, the resin sealing 28 is performed over all the side faces 1 c without exposing the side faces 1 c of the semiconductor chip 1 as shown in FIGS. 65(a) to 65(d).
Moreover, there is no particular limitation on the number of the openings 4 v. The remaining features of the construction of the CSP54 according to the twenty-fourth embodiment and of its method of manufacture are identical to those of the CSP51 of the twenty-first embodiment, so their description will not be repeated.
A CSP55 (semiconductor device) according to the twenty-fifth embodiment is a structure wherein pads are formed on the chip periphery, and the pad electrodes 1 b are formed both inside and outside the chip as shown in FIG. 66. Hereafter, this type of CSP will be referred to as a fan-in/fan-out CSP. Differences from the CSP51 of the twenty-first embodiment are that electrode pads 1 b are provided on the periphery of the four sides of the main surface 1 a of the semiconductor chip 1, and the bump electrodes 2 which are external terminals are arranged inside (substrate body 4 a) and outside (substrate protruding parts 4 b) the semiconductor chip 1.
The CSP55 comprises an elastomer 3 comprising the exposed parts 3 i for exposing the electrode pads 1 b (connection terminals) arranged on the main surface 1 a of the semiconductor chip 1, and the elastomer protruding parts 3 b (elastic structure protruding parts) which protrude beyond the periphery of the semiconductor chip 1, the thin film wiring substrate 4 comprising the substrate body 4 a provided with the wiring 4 d whereof one end is electrically connected to the electrode pads 1 b via the leads 4 c (FIG. 51) and the other end is electrically connected to the bump electrodes 2, and the substrate protruding parts 4 b provided with the openings 4 e for exposing the electrode pads 1 b (FIG. 51), these protruding parts protrudeing beyond the openings 4 e and the semiconductor chip 1, and the sealing parts 5 for sealing the electrode pads 1 b of the semiconductor chip 1 and the leads 4 c of the thin film wiring substrate 4. The thin film wiring substrate 4 and the elastomer 3 are formed in approximately the same size, and the bump electrodes 2 are provided in the substrate body 4 a. Therefore, in the CSP55, the thin film wiring substrate 4 comprises the substrate protruding parts 4 b formed in a one-piece construction with the substrate body 4 a and its outer periphery, the bump electrodes 2 being provided in these substrate protruding parts 4 b outside the semiconductor chip FIG. 67 to FIG. 69 show the structure of the CSP55 when the resin sealing 28 is complete. FIG. 67 is a plan view, FIG. 68 is a cross-sectional view, FIG. 69(a) is a base plan view seen from the under surface, and FIG. 69(b) is a view of the tape base material 4 g seen from the under surface through the semiconductor chip 1.
The substrate body 4 a and substrate protruding parts 4 b are connected and supported by the suspension members 4 u of the four angle pieces of the substrate body 4 a, via the four openings 4 e (FIG. 68(a)) formed in the outer periphery of the substrate body 4 a. In the outer periphery of the substrate protruding parts 4 b, the four long holes 4 q used for cutting are formed, and the substrate protruding parts 4 b are supported in the substrate frame 4 t by the suspension members 4 u of the four angle pieces.
The elastomer 3 of the twenty-fifth embodiment is formed with a shape substantially fitting that of the substrate body CSP11 and substrate protruding parts 4 b in the thin film wiring substrate 4 shown in FIG. 67, as shown in FIG. 69(a).
First, the substrate body 4 a comprising the wiring 4 d and the substrate protruding parts 4 b on its outer periphery are formed, the elastomer 3 which has effectively the same shape as that of the substrate protruding parts 4 b and substrate body CSP11 is joined to it, and the thin film wiring substrate 4 comprising the openings 4 e comprising the leads 4 c joined to the wiring 4 d is prepared.
For example in the first to twenty-fifth embodiments, the specifications of the components shown in FIGS. 3(a,b,c,d) and the process conditions shown in FIG. 5 are only examples of optimum conditions, and the invention is not necessarily limited to the examples shown in FIGS. 3(a,b,c,d) and FIG. 5.
(1) As the substrate body and substrate protruding parts of the thin film wiring substrate in the semiconductor device (CSP) are formed in a one-piece construction, the substrate protruding parts are not formed independently and therefore do not have to be formed of costly materials. This lowers the cost of manufacturing the semiconductor device.
(4) By forming the elastic structure of a porous fluoride resin, the water vapor produced during reflow can be released to the outside and at the same time, penetration of moisture into the semiconductor device is prevented by the water repelling properties of the fluoride resin. As a result, deterioration of the electrical characteristics of the semiconductor device is reduced.
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