Source: http://www.google.com/patents/US7389440?dq=5998925
Timestamp: 2016-05-25 11:13:57
Document Index: 476865315

Matched Legal Cases: ['Application No. 10', 'Application No. 10', 'Application No. 93120990', 'Application No. 93120990', 'Application No. 200410070913', 'Application No. 200410070913', 'Application No. 200410070913']

Patent US7389440 - Method, system, and apparatus for improving multi-core processor performance - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints....http://www.google.com/patents/US7389440?utm_source=gb-gplus-sharePatent US7389440 - Method, system, and apparatus for improving multi-core processor performanceAdvanced Patent SearchPublication numberUS7389440 B2Publication typeGrantApplication numberUS 11/336,681Publication dateJun 17, 2008Filing dateJan 20, 2006Priority dateJul 15, 2003Fee statusPaidAlso published asCN1577280A, CN100555227C, CN101320289A, CN101320289B, DE112004001320B3, US7392414, US7788519, US20050050310, US20060117199, US20060117200, US20060123263, US20060123264, US20070198872, WO2005010737A2Publication number11336681, 336681, US 7389440 B2, US 7389440B2, US-B2-7389440, US7389440 B2, US7389440B2InventorsDaniel W. Bailey, Todd Dutton, Tryggve FossumOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (23), Non-Patent Citations (19), Referenced by (9), Classifications (20), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod, system, and apparatus for improving multi-core processor performance
US 7389440 B2Abstract
1. A method for control of multi-core processors comprising:
assigning a first state to a core without an assigned thread;
causing the core to operate in the first state;
assigning a second state to one or more cores having a corresponding indication in a queue to store indications of cores with an assigned thread;
causing the one or more cores having indications in the queue to operate in the second state;
comparing the number of enabled cores to an executing core limit, assigning a third state for enabling the core to run a thread if the number of enabled cores is less than the executing core limit; and
assigning a fourth state to cause a core to be disabled.
2. The method of claim 1 wherein the queue is a first in first out (FIFO) queue.
3. The method of claim 1 wherein the executing core limit is based at least in part on a formula, wherein N depicts the number of threads that have context; % E depicts the percentage executing time; and % M depicts the percentage memory reference time and the formula is:
int (N�(% E/ (% E+% M))).
4. The method of claim 1 wherein the core transitions from a third state to the fourth state if the core is idle as it waits for completion of a memory operation.
5. The method of claim 1 wherein the core transitions from a third state to the fourth state if the core is idle as it waits for completion of a memory operation.
placing a first processing core of a plurality of processing cores into an execution queue to await enablement for execution of a thread assigned to the processing core;
determining the number of cores from the plurality of processing cores that are executing a thread assigned each respective core;
determining if the number of cores from the plurality of processing cores that are executing a thread is less than an executing core limit;
if the number from the plurality of processing cores that are executing a thread is less than the executing core limit and the first processing core is the next to be processed from the execution queue,
enabling the first processing core, and
removing the first processing core from the execution queue.
assigning a thread to the first processing core.
placing the first processing core into a waiting queue after a specified event occurs; and
disabling the first processing core.
9. The method of claim 8, wherein disabling the first processing core comprises:
disabling a clock to the first processor core.
placing the first processing core into the execution queue from the waiting queue after the specified event as completed.
removing the thread assignment from the first processing core after the thread has completed execution; and
12. The method of claim 11, wherein disabling the first processing core comprises:
13. The method of claim 6, wherein the execution queue is a first-in first-out (FIFO) queue.
14. The method of claim 6 wherein the executing core limit is based at least in part on formula, N*E/E+M′ wherein N depicts the number of threads that have context, E depicts the percentage executing time, M depicts the percentage memory reference time, and the result of the formula is rounded down to the nearest integer to represent the executing core limit. Description
The application is a division of U.S. patent application Ser. No. 10/621,228 filed Jul. 15, 2003 now abandoned and “A Method, System, and Apparatus for Improving Multi-Core Processor Performance,” and is related to three concurrently filed U.S. patent application Ser. No. 11/336,302 filed Jan. 20, 2006, U.S. patent application Ser. No. 11/336,303 filed Jan. 20, 2006, and U.S. patent application Ser. No. 11/336,015 filed Jan. 20, 2006.
int (N�(% E/(% E+% M)))
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No. 11/336,015, mailed Nov. 5, 2007, 10 pgs.10Office Action from U.S. Appl. No. 11/336,015, mailed Apr. 16, 2007, 13 pgs.11Office Action from U.S. Appl. No. 11/336,015, mailed Oct. 25, 2006, 7 pgs.12Office Action from U.S. Appl. No. 11/336,302, mailed Apr. 16, 2007.13Office Action from U.S. Appl. No. 11/336,302, mailed Nov. 6, 2006, 7 pgs.14Office Action from U.S. Appl. No. 11/336,303, mailed Jun. 13, 2007, 5 pgs.15Office Action from U.S. Appl. No. 11/336,303, mailed Nov. 22, 2006, 8 pgs.16Second Foreign Office Action from Counterpart Chinese Patent Application No. 200410070913.7, mailed Feb. 16, 2007.17Sholander, P., et al., "The Effect of Algorithm-Agile Encryption on ATM Quality of Service", IEEE, 1997, pp. 470-474.18The First Office Action issued in Chinese Patent Application No. 200410070913.7, mailed Jun. 23, 2006, 9 pgs (includes English translation).19Third Foreign Office Action from Counterpart Chinese Patent Application No. 200410070913.7, mailed Jun. 8, 2007.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8560871 *Dec 11, 2012Oct 15, 2013Intel CorporationMethod, apparatus, and system for optimizing frequency and performance in a multidie microprocessorUS8719607Dec 1, 2011May 6, 2014International Business Machines CorporationAdvanced Pstate structure with frequency computationUS8769323 *Mar 7, 2013Jul 1, 2014Intel CorporationMethod, apparatus, and system for optimizing frequency and performance in a multidie microprocessorUS8782466 *Feb 3, 2012Jul 15, 2014Hewlett-Packard Development Company, L.P.Multiple processing elementsUS8806248Sep 30, 2013Aug 12, 2014Intel CorporationMethod, apparatus, and system for optimizing frequency and performance in a multidie microprocessorUS9250682Dec 31, 2012Feb 2, 2016Intel CorporationDistributed power management for multi-core processorsUS9280172 *Dec 26, 2013Mar 8, 2016Intel CorporationMethod, apparatus, and system for optimizing frequency and performance in a multidie microprocessorUS20130205169 *Feb 3, 2012Aug 8, 2013Blaine D. GaitherMultiple processing elementsUS20140108849 *Dec 26, 2013Apr 17, 2014Jose P. AllareyMethod, apparatus, and system for optimizing frequency and performance in a multidie microprocessor* Cited by examinerClassifications U.S. Classification713/323, 713/320, 713/300International ClassificationG06F1/32, G06F1/00, G06F1/26Cooperative ClassificationG06F1/3287, G06F1/329, G06F1/3228, G06F1/3296, Y02B60/1282, G06F1/324, Y02B60/1217, Y02B60/1285, Y02B60/144European ClassificationG06F1/32P1D, G06F1/32P5S, G06F1/32P5V, G06F1/32P5T, G06F1/32P5FLegal EventsDateCodeEventDescriptionJan 20, 2006ASAssignmentOwner name: INTEL CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BAILEY, DANIEL W.;DUTTON, TODD;FOSSUM, TRYGGVE;REEL/FRAME:017500/0637;SIGNING DATES FROM 20030918 TO 20040127Sep 21, 2011FPAYFee paymentYear of fee payment: 4Dec 2, 2015FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services