Source: http://patents.com/us-9806163.html
Timestamp: 2018-09-18 13:26:56
Document Index: 286865987

Matched Legal Cases: ['Application No. 09705485', 'Application No. 08722595', 'Application No. 07', 'Application No. 07807139', 'Application No. 10004492', 'Application No. 10009574', 'Application No. 12001395', 'Application No. 10009579', 'Application No. 10', 'Application No. 10']

US Patent # 9,806,163. Semiconductor device having an nMOS SGT and a pMOS SGT - Patents.com
United States Patent 9,806,163
Masuoka , et al. October 31, 2017
Semiconductor device having an nMOS SGT and a pMOS SGT
A semiconductor device includes first and second fin-shaped silicon layers on a substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. First and second pillar-shaped silicon layers reside on the first and second fin-shaped silicon layers, respectively. An n-type diffusion layer resides in an upper portion of the first fin-shaped silicon layer and in upper and lower portions of the first pillar-shaped silicon layer. A p-type diffusion layer resides in an upper portion of the second fin-shaped silicon layer and upper and lower portions of the second pillar-shaped silicon layer. First and second gate insulating films and metal gate electrodes are around the first and second pillar-shaped silicon layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped silicon layers.
Masuoka; Fujio (Tokyo, JP), Nakamura; Hiroki (Tokyo, JP)
UNISANTIS ELECTRONICS SINGAPORE PTE. LTD. (Peninsula Plaza, SG)
Family ID: 1000002922214
15/147,097
US 20160247889 A1 Aug 25, 2016
14690582 Apr 20, 2015 9362353
14289919 May 29, 2014 9035384
13693524 Dec 4, 2012 8772175
61577189 Dec 19, 2011
Current CPC Class: H01L 29/42392 (20130101); H01L 21/823487 (20130101); H01L 21/823807 (20130101); H01L 21/823885 (20130101); H01L 27/092 (20130101); H01L 29/78696 (20130101); H01L 29/0653 (20130101); H01L 29/66666 (20130101); H01L 29/7827 (20130101); H01L 29/78642 (20130101); H01L 29/78654 (20130101); H01L 27/0924 (20130101)
Current International Class: H01L 21/84 (20060101); H01L 21/8234 (20060101); H01L 29/423 (20060101); H01L 29/66 (20060101); H01L 21/8238 (20060101); H01L 29/786 (20060101); H01L 27/092 (20060101); H01L 29/06 (20060101); H01L 29/78 (20060101)
Field of Search: ;257/288,350,384,385,315,316,317,E21.014,E21.042,E21.043,E21.048,E21.051,E21.151,E21.165,E21.173,E21.278,E21.293,E21.28
5017977 May 1991 Richardson
5312767 May 1994 Shimizu et al.
5382816 January 1995 Mitsui
5416350 May 1995 Watanabe
5480838 January 1996 Mitsui
5656842 August 1997 Iwamatsu et al.
5703386 December 1997 Yasuda et al.
5710447 January 1998 Tohyama
5780888 July 1998 Maeda et al.
5811336 September 1998 Kasai
5872037 February 1999 Iwamatsu et al.
5905283 May 1999 Kasai
5994735 November 1999 Maeda et al.
6121086 September 2000 Kuroda et al.
6127209 October 2000 Maeda et al.
6175138 January 2001 Noda
6373099 April 2002 Kikuchi et al.
6392271 May 2002 Alavi et al.
6406962 June 2002 Agnello et al.
6420751 July 2002 Maeda et al.
6461900 October 2002 Sundaresan et al.
6483171 November 2002 Forbes et al.
6658259 December 2003 McIntosh
6740937 May 2004 Sushihara
6849903 February 2005 Sushihara
6861684 March 2005 Skotnicki et al.
6878991 April 2005 Forbes
6943407 September 2005 Ouyang et al.
7193278 March 2007 Song
7198976 April 2007 Hirata
7233033 June 2007 Koyama et al.
7241655 July 2007 Tang et al.
7368334 May 2008 Yeo et al.
7374990 May 2008 Tang et al.
7579214 August 2009 Yamazaki et al.
7619675 November 2009 Horii
7829952 November 2010 Moniwa et al.
7872287 January 2011 Masuoka et al.
7977736 July 2011 Kim et al.
7977738 July 2011 Minami et al.
7981738 July 2011 Moniwa et al.
8039893 October 2011 Masuoka et al.
8058683 November 2011 Yoon et al.
8067800 November 2011 Hsieh
8110869 February 2012 Bhalla
8154076 April 2012 Takaishi
8188537 May 2012 Masuoka et al.
8227305 July 2012 Forbes
8378400 February 2013 Masuoka et al.
8482047 July 2013 Abbott et al.
8772175 July 2014 Masuoka et al.
8916478 December 2014 Masuoka et al.
9035384 May 2015 Masuoka et al.
9245889 January 2016 Masuoka
9362353 June 2016 Masuoka
2001/0052614 December 2001 Ishibashi
2002/0000624 January 2002 Takemura et al.
2002/0034853 March 2002 Alavi et al.
2002/0195652 December 2002 Maeda et al.
2003/0002093 January 2003 Hynecek
2003/0075758 April 2003 Sundaresan et al.
2004/0005755 January 2004 Moniwa et al.
2004/0113207 June 2004 Hsu et al.
2004/0135215 July 2004 Song
2004/0169293 September 2004 Sushihara
2004/0256639 December 2004 Ouyang et al.
2005/0127404 June 2005 Sushihara
2005/0281119 December 2005 Shibata et al.
2006/0007333 January 2006 Horii
2006/0033524 February 2006 Sushihara
2006/0043520 March 2006 Jerdev et al.
2006/0261406 November 2006 Chen
2007/0007601 January 2007 Hsu et al.
2007/0117324 May 2007 Previtali
2007/0173006 July 2007 Moniwa et al.
2008/0048245 February 2008 Kito et al.
2008/0173936 July 2008 Yoon et al.
2008/0210985 September 2008 Ogawa et al.
2008/0227241 September 2008 Nakabayashi et al.
2009/0032955 February 2009 Tanaka et al.
2009/0057722 March 2009 Masuoka et al.
2009/0065832 March 2009 Masuoka et al.
2009/0085088 April 2009 Takaishi
2009/0114989 May 2009 Hamamoto
2009/0159964 June 2009 Lee
2009/0174024 July 2009 Kim
2009/0197379 August 2009 Leslie
2009/0290082 November 2009 Yamazaki et al.
2009/0291551 November 2009 Cho
2010/0052029 March 2010 Huang
2010/0200731 August 2010 Masuoka et al.
2010/0200913 August 2010 Masuoka et al.
2010/0207172 August 2010 Masuoka et al.
2010/0207201 August 2010 Masuoka et al.
2010/0207213 August 2010 Masuoka et al.
2010/0213525 August 2010 Masuoka et al.
2010/0213539 August 2010 Masuoka et al.
2010/0219457 September 2010 Masuoka et al.
2010/0219483 September 2010 Masuoka et al.
2010/0270611 October 2010 Masuoka et al.
2010/0276750 November 2010 Tu
2010/0295123 November 2010 Lung et al.
2011/0073925 March 2011 Park et al.
2011/0215381 September 2011 Masuoka et al.
2011/0254067 October 2011 Abbott et al.
2011/0275207 November 2011 Moniwa et al.
2011/0303973 December 2011 Masuoka et al.
2011/0303985 December 2011 Masuoka
2012/0086051 April 2012 Wang et al.
2012/0196415 August 2012 Masuoka et al.
1507035 Jun 2004 CN
1610126 Apr 2005 CN
1983601 Jun 2007 CN
101542733 Sep 2009 CN
4443968 Nov 1995 DE
1770769 Apr 2007 EP
2197032 Jun 2010 EP
2239770 Oct 2010 EP
2239771 Oct 2010 EP
2244305 Oct 2010 EP
2246895 Nov 2010 EP
60-070757 Apr 1985 JP
61-013661 Jan 1986 JP
62-045058 Feb 1987 JP
62-190751 Aug 1987 JP
63-037633 Feb 1988 JP
63-158866 Jul 1988 JP
64-089560 Apr 1989 JP
01-175775 Jul 1989 JP
02-066969 Mar 1990 JP
02-071556 Mar 1990 JP
02-089368 Mar 1990 JP
02-188966 Jul 1990 JP
03-114233 May 1991 JP
03-145761 Jun 1991 JP
03-225873 Oct 1991 JP
04-234166 Aug 1992 JP
05-276442 Oct 1993 JP
06-021467 Jan 1994 JP
06-069441 Mar 1994 JP
06-237003 Aug 1994 JP
07-099311 Apr 1995 JP
07-321228 Dec 1995 JP
08-078533 Mar 1996 JP
09-008295 Jan 1997 JP
10-079482 Mar 1998 JP
10-223777 Aug 1998 JP
2000-012705 Jan 2000 JP
2000-068516 Mar 2000 JP
2000-243085 Sep 2000 JP
2000-244818 Sep 2000 JP
2001-028399 Jan 2001 JP
2001-237421 Aug 2001 JP
2001-339057 Dec 2001 JP
2001-352047 Dec 2001 JP
2002-009257 Jan 2002 JP
2002-033399 Jan 2002 JP
2002-231951 Aug 2002 JP
2002-246580 Aug 2002 JP
2002-246581 Aug 2002 JP
2003-068883 Mar 2003 JP
2003-142684 May 2003 JP
2003-179160 Jun 2003 JP
2003-224211 Aug 2003 JP
2004-079694 Mar 2004 JP
2004-096065 Mar 2004 JP
2004-153246 May 2004 JP
2004-193588 Jul 2004 JP
2004-259733 Sep 2004 JP
2004-319808 Nov 2004 JP
2005-012213 Jan 2005 JP
2005-135451 May 2005 JP
2006-024799 Jan 2006 JP
2006-514392 Apr 2006 JP
2006-294995 Oct 2006 JP
2007-0250652 Sep 2007 JP
2008-177565 Jul 2008 JP
2008-205168 Sep 2008 JP
2008-300558 Dec 2008 JP
2009-110049 May 2009 JP
2009-182316 Aug 2009 JP
2009-182317 Aug 2009 JP
2010-171055 Aug 2010 JP
2010-0213539 Sep 2010 JP
2010-258345 Nov 2010 JP
2011-066105 Mar 2011 JP
2011-071235 Apr 2011 JP
2011-077437 Apr 2011 JP
2011-211161 Oct 2011 JP
10-0132560 Dec 1997 KR
10-0200222 Jun 1999 KR
10-0327875 Sep 2002 KR
2004-0063348 Jul 2004 KR
WO 94/14198 Jun 1994 WO
WO 01/22494 Mar 2001 WO
WO 2006/127586 Nov 2006 WO
WO 2009/034623 Mar 2009 WO
WO 2009/034731 Mar 2009 WO
WO 2009/057194 May 2009 WO
WO 2009/095997 Aug 2009 WO
WO 2009/096001 Aug 2009 WO
WO 2009/096464 Aug 2009 WO
WO 2009/096465 Aug 2009 WO
WO 2009/096466 Aug 2009 WO
WO 2009/096470 Aug 2009 WO
WO 2009/102059 Aug 2009 WO
WO 2009/133957 Nov 2009 WO
WO 2011/111662 Sep 2011 WO
Agranov, G. et al., "Pixel Size Reduction of CMOS Image Sensors and Comparison of Characteristics", The Institute of Image Formation and Television Engineers (ITE) Technical Report, vol. 33, No. 38, pp. 9-12, Septemer 2009. cited by applicant .
Chen, Yijian et al., "Vertical integrated-gate CMOS for ultra-dense IC", Microelectronic Engineering, vol. 83, 2006, pp. 1745-1748. cited by applicant .
Choi, Yang-Kyu et al., "FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering," IEEE, 2002, 4 pages. cited by applicant .
Office Action for Chinese Patent Application Serial No. 200980103454.9, dated Oct. 31, 2012, 7 pages. cited by applicant .
Office Action for Chinese Patent Application Serial No. 200980103505.8, dated Nov. 1, 2012, 5 pages. cited by applicant .
Office Action for Chinese Patent Application Serial No. 201010171435.4, dated Dec. 21, 2012, 7 pages. cited by applicant .
Office Action for Chinese Patent Application Serial No. 2011100647037, dated Nov. 14, 2012, 6 pages. cited by applicant .
Office Action for Japanese Patent Application Serial No. 2009-538870, dated Nov. 8, 2012, 4 pages. cited by applicant .
Restriction Requirement for U.S. Appl. No. 13/412,959, dated Nov. 8, 2012, 6 pages. cited by applicant .
European Search Report for counterpart European Application No. 09705485.2, dated Feb. 14, 2011, 5 pages. cited by applicant .
Examination Report for European Application No. 08722595.9, dated Jul. 11, 2012, 4 pages. cited by applicant .
Examination Report in corresponding European Application No. 07 807 139.6, dated Jun. 11, 2012, 4 pages. cited by applicant .
Extended European Search Report for European Application No. 07807139.6, dated Jun. 24, 2011, 10 pages. cited by applicant .
Extended European Search Report for European Application No. 10004492.4, dated Jun. 21, 2012, 10 pages. cited by applicant .
Extended European Search Report for European Application No. 10009574.4, dated May 15, 2012, 6 pages. cited by applicant .
Extended European Search Report for European Application No. 12001395.8, dated Apr. 26, 2012, 7 pages. cited by applicant .
Extended European Search Report for European Application No. 10009579.3, dated Jun. 11, 2012, 11 pages. cited by applicant .
Guidash, R.M. et al. "A 0.6 .mu.m CMOS Pinned Photodiode Color Imager Technology", IEDM Digest Papers, pp. 927-929, 1997. cited by applicant .
Hieda, K. et al., "New Effects of Trench Isolated Transistor Using Side-Wall Gates", VLSI Research Center, Toshiba Corporation, 1987, 4 pages. cited by applicant .
International Preliminary Report on Patentability for International Application No. PCT/JP2008/051300, dated Aug. 31, 2010, 9 pages. cited by applicant .
International Preliminary Report on Patentability for International Application No. PCT/JP2009/051459, dated Aug. 31, 2010, 9 pages. cited by applicant .
International Preliminary Report on Patentability for International Application No. PCT/JP2011/055264, dated Oct. 11, 2012, 7 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2007/067732, dated Dec. 11, 2007, 2 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2007/071052, dated Jan. 29, 2008, 6 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2008/051300, dated May 13, 2008, 4 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2008/051301, dated Apr. 1, 2008, 2 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2008/051302, dated Apr. 8, 2008, 2 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2008/051304, dated Apr. 15, 2008, 2 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2008/058412, dated Jun. 10, 2008, 2 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2009/051459, dated Apr. 14, 2009, 4 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2009/051460, dated Apr. 21, 2009, 2 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2009/051461, dated Apr. 21, 2009, 2 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2009/051463, dated Feb. 24, 2009, 2 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2009/058629, dated Jun. 2, 2009, 2 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2011/070534, dated Dec. 6, 2011, 10 pages. cited by applicant .
International Search Report for International Application No. PCT/JP2011/071162, dated Dec. 13, 2011, 18 pages. cited by applicant .
Iwai, Makoto et al., "High-Performance Buried Gate Surrounding Gate Transistor for Future Three-Dimensional Devices", Japanese Journal of Applied Physics, 2004, vol. 43, No. 10, pp. 6904-6906. cited by applicant .
Kasano, Masahiro, "A 2.0.mu.m Pixel Pitch MOS Image Sensor with an Amorphous Si Film Color Filter," IEEE International Solid-State Circuits Conference, Feb. 8, 2005, 3 pages. cited by applicant .
Maeda, Shigenobu et al., "Impact of a Vertical .PHI.-Shape Transistor (V.PHI.T) Cell for 1 Gbit DRAM and Beyond," IEEE Transactions on Electron Devices, vol. 42, No. 12, Dec. 1995, pp. 2117-2124. cited by applicant .
Mendis, Sunetra K. et al. "A 128 .times. 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging System", IEDM93, Digest Papers, 22.6.1, pp. 583-586, 1993. cited by applicant .
Mistry et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", IEEE, pp. 247-250, 2007. cited by applicant .
Nakamura, Jun-ichi et al., "Nondestructive Readout Mode Static Induction Transistor (SIT) Photo Sensors," IEEE Transactions on Electron Devices, 1993, vol. 40, pp. 334-341. cited by applicant .
Nitayama, Akihiro et al., "Multi-Pillar Surrounding Gate Transistor (M-SGT) for Compact and High-Speed Circuits", IEEE Transactions on Electron Devices, vol. 3, No. 3, Mar. 1991, pp. 679-583. cited by applicant .
Non-Certified Partial Translation of Office Action from counterpart Korean Application No. 10-2010-7018204, dated Mar. 29, 2012, 1 page. cited by applicant .
Notice of Allowance for U.S. Appl. No. 12/704,955, dated Mar. 15, 2012, 8 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 13/447,721, dated Nov. 2, 2012, 9 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 12/700,294, dated Oct. 5, 2012, 7 pages. cited by applicant .
Office Action from co-pending U.S. Appl. No. 12/704,935, dated Nov. 18, 2011, 9 pages. cited by applicant .
Office Action from co-pending U.S. Appl. No. 12/894,923, dated Oct. 2, 2012, 21 pages. cited by applicant .
Office Action from co-pending U.S. Appl. No. 13/043,081, dated Jul. 16, 2012, 6 pages. cited by applicant .
Office Action from co-pending U.S. Appl. No. 13/046,113, dated Jan. 9, 2013, 6 pages. cited by applicant .
Office Action from co-pending U.S. Appl. No. 13/113,482, dated Jan. 2, 2013, 9 pages. cited by applicant .
Office Action from co-pending U.S. Appl. No. 13/412,959, dated Dec. 7, 2012, 9 pages. cited by applicant .
Office Action from co-pending U.S. Appl. No. 12/704,955, dated Dec. 8, 2011, 12 pages. cited by applicant .
Office Action from counterpart Korean Application No. 10-2010-7018204, dated Mar. 29, 2012, 7 pages. cited by applicant .
Takahashi, Hidekazu, "A 3.9.mu.m Pixel Pitch VGA Format 10b Digital Image Sensor with 1.5-Transistor/Pixel," IEEE International Solid-State Circuits Conference, Feb. 16, 2004, 10 pages. cited by applicant .
Takato, Hiroshi et al., "Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's," IEEE Transactions on Electron Devices, vol. 38, No. 3, Mar. 1991, pp. 573-578. cited by applicant .
Watanabe, S. et al., "A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's", IEEE Journal of Solid-State Circuits, vol. 30, No. 9, Sep. 1995, pp. 960-971. cited by applicant .
Written Opinion of the International Searching Authority for International Application No. PCT/JP2007/067732, dated Dec. 11, 2007, 4 pages. cited by applicant .
Written Opinion of the International Searching Authority for International Application No. PCT/JP2007/071052, dated Jan. 29, 2008, 9 pages. cited by applicant .
Written Opinion of the International Searching Authority for International Application No. PCT/JP2008/051300, dated Aug. 30, 2010, 8 pages. cited by applicant .
Written Opinion of the International Searching Authority for International Application No. PCT/JP2008/051301, dated Apr. 1, 2008, 5 pages. cited by applicant .
Written Opinion of the International Searching Authority for International Application No. PCT/JP2008/051302, dated Apr. 8, 2008, 5 pages. cited by applicant .
Written Opinion of the International Searching Authority for International Application No. PCT/JP2008/058412, dated Jun. 10, 2008, 4 pages. cited by applicant .
Written Opinion of the International Searching Authority for International Application No. PCT/JP2009/051459, dated Aug. 30, 2010, 8 pages. cited by applicant .
Written Opinion of the International Searching Authority for International Application No. PCT/JP2009/051460, dated Apr. 21, 2009, 5 pages. cited by applicant .
Written Opinion of the International Searching Authority for International Application No. PCT/JP2009/051461, dated Apr. 21, 2009, 6 pages. cited by applicant .
Written Opinion of the International Searching Authority for International Application No. PCT/JP2009/058629, dated Jun. 2, 2009, 4 pages. cited by applicant .
Wu et al., "High Performance 22/20nm FinFET CMOS Devices with Advanced High-K/Metal Gate Scheme", IEEE, pp. 27.1.1-27.1.4, 2010. cited by applicant .
Wuu, S.G. et al., "A Leading-Edge 0.9 .mu.m Pixel CMOS Image Sensor Technology with Backside Illumination: Future Challenges for Pixel Scaling", IEDM2010 Digest Papers, 14.1.1, pp. 332-335, 2010. cited by applicant .
Yonemoto, Kazuya, "A CMOS Image Sensor with a Simple FPN-Reduction Technology and a Hole Accumulated Diode," 2000 IEEE International Solid-State Circuits Conference, 9 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 12/894,923, dated Feb. 21, 2013, 5 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 12/894,923, dated Mar. 14, 2013, 5 pages. cited by applicant .
Restriction Requirement for U.S. Appl. No. 13/116,506, dated Feb. 28, 2013, 6 pages. cited by applicant .
Office Action for U.S. Appl. No. 13/412,959, dated Mar. 13, 2013, 7 pages. cited by applicant .
Office Action for Korean Patent Application Serial No. 9-5-2013-010869116, dated Feb. 18, 2013, 4 pages. cited by applicant .
International Search Report for PCT/JP2011/079300, dated Mar. 13, 2012, 5 pages. cited by applicant .
Lee, et al., "An Active Pixel Sensor Fabricated Using CMOS/CCD Process Technology" in Program IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, 1995, 5 pages. cited by applicant .
Murakami et al., "Technologies to Improve Photo-Sensitivity and Reduce VOD Shutter Voltage for CCD Image Sensors", IEEE Transactions on Electron Devices, vol. 47, No. 8, 2000, pp. 1566-1572. cited by applicant .
Takahashi et al., "A 3.9-.mu.m Pixel Pitch VGA Format 10-b Digital Output CMOS Image Sensor With 1.5 Transistor/Pixel", IEEE Journal of Solid-State Circuit, Vo.39, No. 12, 2004, pp. 2417-2425. cited by applicant .
Yasutomi et al, "A High-Speed CMOS Image Sensor with Global Electronic Shutter Pixel Using Pinned Diodes", IEEJ Trans. SM, vol. 129, No. 10, 2009, pp. 321-327. cited by applicant .
Notice of Allowance for U.S. Appl. No. 13/043,081, dated Mar. 18, 2013, 6 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 13/113,482, dated Apr. 4, 2013, 10 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 12/768,290, dated Apr. 18, 2013, 9 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 12/704,935, dated May 16, 2013, 10 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 13/046,113, dated May 13, 2013, 10 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 13/412,959, dated May 8, 2013, 9 pages. cited by applicant .
Office Action for U.S. Appl. No. 13/116,506, dated Jul. 18, 2013, 12 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 12/894,923, dated Jul. 2, 2013, 9 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 13/606,823, dated Jul. 8, 2013, 12 pages. cited by applicant .
English translation of previously cited International Search Report for PCT/JP2011/070534, dated Dec. 6, 2011, 2 pages. cited by applicant .
English translation of previously cited International Search Report for PCT/JP2011/071162, dated Dec. 13, 2011, 5 pages. cited by applicant .
Office Action for U.S. Appl. No. 13/917,040 dated Aug. 6, 2013, 5 pages. cited by applicant .
Copy of Ex Parte Quayle Action for U.S. Appl. No. 13/693,524 dated Feb. 20, 2014, 4 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 13/693,524 dated Mar. 18, 2014, 7 pages. cited by applicant .
Office Action for U.S. Appl. No. 14/066,095 dated Sep. 15, 2014, 7 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 14/066,095 dated Oct. 23, 2014, 7 pages. cited by applicant .
Office Action for U.S. Appl. No. 14/289,919 dated Feb. 5, 2015, 7 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 14/289,919 dated Mar. 18, 2015, 7 pages. cited by applicant .
Office Action for U.S. Appl. No. 14/537,322 dated Sep. 4, 2015, 7 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 14/537,322 dated Oct. 29, 2015, 7 pages. cited by applicant .
Office Action for U.S. Appl. No. 14/690,582 dated Dec. 22, 2015, 7 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 14/690,582 dated Mar. 29, 2016, 7 pages. cited by applicant .
Office Action for U.S. Appl. No. 14/963,432 dated May 25, 2016, 7 pages. cited by applicant .
Notice of Allowance for U.S. Appl. No. 14/963,432 dated Jul. 28, 2016, 8 pages. cited by applicant.
Assistant Examiner: Crite; Antonio
This application is a continuation application of U.S. patent application Ser. No. 14/690,582, filed Apr. 20, 2015, now U.S. Pat. No. 9,362,353, which is a continuation of U.S. patent application Ser. No. 14/289,919, filed May 29, 2014, now U.S. Pat. No. 9,035,384, which is a continuation of U.S. patent application Ser. No. 13/693,524, filed Dec. 4, 2012, now U.S. Pat. No. 8,772,175, which claims benefit of the filing date of Provisional U.S. Patent Application Ser. No. 61/577,189, filed Dec. 19, 2011, the entire contents of which are hereby incorporated by reference.
1. A semiconductor device comprising: a first fin-shaped layer including silicon on a substrate, wherein the first fin-shaped layer is a single-stage plateau extending in a first direction; a second fin-shaped layer including silicon on the substrate, wherein the second fin-shaped layer is a single-stage plateau extending in the first direction; a first insulating film around the first fin-shaped layer and the second fin-shaped layer; a first pillar-shaped layer including silicon on the first fin-shaped layer; a second pillar-shaped layer including silicon on the second fin-shaped layer, where a width of a bottom of the first pillar-shaped layer is equal to a width of a top of the first fin-shaped layer only in a width direction perpendicular to the first direction, and a width of a bottom of the second pillar-shaped layer is equal to a width of a top of the second fin-shaped layer only in the width direction; an n-type diffusion layer in an upper portion of the first fin-shaped layer and a lower portion of the first pillar-shaped layer; a p-type diffusion layer in an upper portion of the second fin-shaped layer and a lower portion of the second pillar-shaped layer; a gate insulating film around the first pillar-shaped layer; a first metal gate electrode around the gate insulating film; a gate insulating film around the second pillar-shaped layer; a second metal gate electrode around the gate insulating film; a metal gate line connected to the first metal gate electrode and to the second metal gate electrode and extending in a direction perpendicular to the first fin-shaped layer and the second fin-shaped layer.
In addition, usual MOS transistors use a first insulating film in order to decrease a parasitic capacitance between gate line and a substrate. For example, in FINFET (IEDM 2010 CC. Wu, et. al., 27.1.1-27.1.4), a first insulating film is formed around a fin-shaped semiconductor layer and then etched back to expose the fin-shaped semiconductor layer, thereby decreasing the parasitic capacitance between the gate line and the substrate. Also, in SGT, the first insulating film must be used for decreasing the parasitic capacitance between the gate line and the substrate. The SGT includes the pillar-shaped semiconductor layer in addition to the fin-shaped semiconductor layer, and thus some consideration is required for forming the pillar-shaped semiconductor layer.
A semiconductor device of the present invention includes a semiconductor device comprising: a first fin-shaped silicon layer on a substrate; a second fin-shaped silicon layer on the substrate, where the first fin-shaped silicon layer and the second fin-shaped silicon layer correspond to the dimensions of a sidewall pattern around a dummy pattern; a first insulating film around the first fin-shaped silicon layer and the second fin-shaped silicon layer; a first pillar-shaped silicon layer on the first fin-shaped silicon layer; a second pillar-shaped silicon layer on the second fin-shaped silicon layer; an n-type diffusion layer in an upper portion of the first fin-shaped silicon layer and a lower portion of the first pillar-shaped silicon layer; an n-type diffusion layer in an upper portion of the first pillar-shaped silicon layer; a p-type diffusion layer in an upper portion of the second fin-shaped silicon layer and a lower portion of the second pillar-shaped silicon layer; a p-type diffusion layer in an upper portion of the second pillar-shaped silicon layer; a gate insulating film around the first pillar-shaped silicon layer; a first metal gate electrode around the gate insulating film; a gate insulating film around the second pillar-shaped silicon layer; a second metal gate electrode around the gate insulating film; and a metal gate line connected to the first metal gate electrode and to the second metal gate electrode and extending in a direction perpendicular to the first fin-shaped silicon layer and the second fin-shaped silicon layer.
FIG. 1(a) is a plan view of a semiconductor device according to the present invention, FIG. 1(b) is a sectional view taken along line X-X' in FIG. 1(a), and FIG. 1(c) is a sectional view taken along line Y-Y' in FIG. 1(a).
FIG. 2(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 2(b) is a sectional view taken along line X-X' in FIG. 2(a), and FIG. 2(c) is a sectional view taken along line Y-Y' in FIG. 2(a).
FIG. 3(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 3(b) is a sectional view taken along line X-X' in FIG. 3(a), and FIG. 3(c) is a sectional view taken along line Y-Y' in FIG. 3(a).
FIG. 4(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 4(b) is a sectional view taken along line X-X' in FIG. 4(a), and FIG. 4(c) is a sectional view taken along line Y-Y' in FIG. 4(a).
FIG. 5(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 5(b) is a sectional view taken along line X-X' in FIG. 5(a), and FIG. 5(c) is a sectional view taken along line Y-Y' in FIG. 5(a).
FIG. 6(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 6(b) is a sectional view taken along line X-X' in FIG. 6(a), and FIG. 6(c) is a sectional view taken along line Y-Y' in FIG. 6(a).
FIG. 7(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 7(b) is a sectional view taken along line X-X' in FIG. 7(a), and FIG. 7(c) is a sectional view taken along line Y-Y' in FIG. 7(a).
FIG. 8(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 8(b) is a sectional view taken along line X-X' in FIG. 8(a), and FIG. 8(c) is a sectional view taken along line Y-Y' in FIG. 8(a).
FIG. 9(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 9(b) is a sectional view taken along line X-X' in FIG. 9(a), and FIG. 9(c) is a sectional view taken along line Y-Y' in FIG. 9(a).
FIG. 10(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 10(b) is a sectional view taken along line X-X' in FIG. 10(a), and FIG. 10(c) is a sectional view taken along line Y-Y' in FIG. 10(a).
FIG. 11(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 11(b) is a sectional view taken along line X-X' in FIG. 11(a), and FIG. 11(c) is a sectional view taken along line Y-Y' in FIG. 11(a).
FIG. 12(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 12(b) is a sectional view taken along line X-X' in FIG. 12(a), and FIG. 12(c) is a sectional view taken along line Y-Y' in FIG. 12(a).
FIG. 13(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 13(b) is a sectional view taken along line X-X' in FIG. 13(a), and FIG. 13(c) is a sectional view taken along line Y-Y' in FIG. 13(a).
FIG. 14(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 14(b) is a sectional view taken along line X-X' in FIG. 14(a), and FIG. 14(c) is a sectional view taken along line Y-Y' in FIG. 14(a).
FIG. 15(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 15(b) is a sectional view taken along line X-X' in FIG. 15(a), and FIG. 15(c) is a sectional view taken along line Y-Y' in FIG. 15(a).
FIG. 16(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 16(b) is a sectional view taken along line X-X' in FIG. 16(a), and FIG. 16(c) is a sectional view taken along line Y-Y' in FIG. 16(a).
FIG. 17(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 17(b) is a sectional view taken along line X-X' in FIG. 17(a), and FIG. 17(c) is a sectional view taken along line Y-Y' in FIG. 17(a).
FIG. 18(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 18(b) is a sectional view taken along line X-X' in FIG. 18(a), and FIG. 18(c) is a sectional view taken along line Y-Y' in FIG. 18(a).
FIG. 19(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 19(b) is a sectional view taken along line X-X' in FIG. 19(a), and FIG. 19(c) is a sectional view taken along line Y-Y' in FIG. 19(a).
FIG. 20(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 20(b) is a sectional view taken along line X-X' in FIG. 20(a), and FIG. 20(c) is a sectional view taken along line Y-Y' in FIG. 20(a).
FIG. 21(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 21(b) is a sectional view taken along line X-X' in FIG. 21(a), and FIG. 21(c) is a sectional view taken along line Y-Y' in FIG. 21(a).
FIG. 22(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 22(b) is a sectional view taken along line X-X' in FIG. 22(a), and FIG. 22(c) is a sectional view taken along line Y-Y' in FIG. 22(a).
FIG. 23(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 23(b) is a sectional view taken along line X-X' in FIG. 23(a), and FIG. 23(c) is a sectional view taken along line Y-Y' in FIG. 23(a).
FIG. 24(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 24(b) is a sectional view taken along line X-X' in FIG. 24(a), and FIG. 24(c) is a sectional view taken along line Y-Y' in FIG. 24(a).
FIG. 25(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 25(b) is a sectional view taken along line X-X' in FIG. 25(a), and FIG. 25(c) is a sectional view taken along line Y-Y' in FIG. 25(a).
FIG. 26(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 26(b) is a sectional view taken along line X-X' in FIG. 26(a), and FIG. 26(c) is a sectional view taken along line Y-Y' in FIG. 26(a).
FIG. 27(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 27(b) is a sectional view taken along line X-X' in FIG. 27(a), and FIG. 27(c) is a sectional view taken along line Y-Y' in FIG. 27(a).
FIG. 28(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 28(b) is a sectional view taken along line X-X' in FIG. 28(a), and FIG. 28(c) is a sectional view taken along line Y-Y' in FIG. 28(a).
FIG. 29(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 29(b) is a sectional view taken along line X-X' in FIG. 29(a), and FIG. 29(c) is a sectional view taken along line Y-Y' in FIG. 29(a).
FIG. 30(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 30(b) is a sectional view taken along line X-X' in FIG. 30(a), and FIG. 30(c) is a sectional view taken along line Y-Y' in FIG. 30(a).
FIG. 31(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 31(b) is a sectional view taken along line X-X' in FIG. 31(a), and FIG. 31(c) is a sectional view taken along line Y-Y' in FIG. 31(a).
FIG. 32(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 32(b) is a sectional view taken along line X-X' in FIG. 32(a), and FIG. 32(c) is a sectional view taken along line Y-Y' in FIG. 32(a).
FIG. 33(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 33(b) is a sectional view taken along line X-X' in FIG. 33(a), and FIG. 33(c) is a sectional view taken along line Y-Y' in FIG. 33(a).
FIG. 34(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 34(b) is a sectional view taken along line X-X' in FIG. 34(a), and FIG. 34(c) is a sectional view taken along line Y-Y' in FIG. 34(a).
FIG. 35(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 35(b) is a sectional view taken along line X-X' in FIG. 35(a), and FIG. 35(c) is a sectional view taken along line Y-Y' in FIG. 35(a).
FIG. 36(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 36(b) is a sectional view taken along line X-X' in FIG. 36(a), and FIG. 36(c) is a sectional view taken along line Y-Y' in FIG. 36(a).
FIG. 37(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 37(b) is a sectional view taken along line X-X' in FIG. 37(a), and FIG. 37(c) is a sectional view taken along line Y-Y' in FIG. 37(a).
FIG. 38(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 38(b) is a sectional view taken along line X-X' in FIG. 38(a), and FIG. 38(c) is a sectional view taken along line Y-Y' in FIG. 38(a).
FIG. 39(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 39(b) is a sectional view taken along line X-X' in FIG. 39(a), and FIG. 39(c) is a sectional view taken along line Y-Y' in FIG. 39(a).
FIG. 40(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 40(b) is a sectional view taken along line X-X' in FIG. 40(a), and FIG. 40(c) is a sectional view taken along line Y-Y' in FIG. 40(a).
FIG. 41(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 41(b) is a sectional view taken along line X-X' in FIG. 41(a), and FIG. 41(c) is a sectional view taken along line Y-Y' in FIG. 41(a).
FIG. 42(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 42(b) is a sectional view taken along line X-X' in FIG. 42(a), and FIG. 42(c) is a sectional view taken along line Y-Y' in FIG. 42(a).
FIG. 43(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 43(b) is a sectional view taken along line X-X' in FIG. 43(a), and FIG. 43(c) is a sectional view taken along line Y-Y' in FIG. 43(a).
FIG. 44(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 44(b) is a sectional view taken along line X-X' in FIG. 44(a), and FIG. 44(c) is a sectional view taken along line Y-Y' in FIG. 44(a).
FIG. 45(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 45(b) is a sectional view taken along line X-X' in FIG. 45(a), and FIG. 45(c) is a sectional view taken along line Y-Y' in FIG. 45(a).
FIG. 46(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 46(b) is a sectional view taken along line X-X' in FIG. 46(a), and FIG. 46(c) is a sectional view taken along line Y-Y' in FIG. 46(a).
FIG. 47(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 47(b) is a sectional view taken along line X-X' in FIG. 47(a), and FIG. 47(c) is a sectional view taken along line Y-Y' in FIG. 47(a).
FIG. 48(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 48(b) is a sectional view taken along line X-X' in FIG. 48(a), and FIG. 48(c) is a sectional view taken along line Y-Y' in FIG. 48(a).
FIG. 49(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 49(b) is a sectional view taken along line X-X' in FIG. 49(a), and FIG. 49(c) is a sectional view taken along line Y-Y' in FIG. 49(a).
FIG. 50(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 50(b) is a sectional view taken along line X-X' in FIG. 50(a), and FIG. 50(c) is a sectional view taken along line Y-Y' in FIG. 50(a).
FIG. 51(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 51(b) is a sectional view taken along line X-X' in FIG. 51(a), and FIG. 51(c) is a sectional view taken along line Y-Y' in FIG. 51(a).
FIG. 52(a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 52(b) is a sectional view taken along line X-X' in FIG. 52(a), and FIG. 52(c) is a sectional view taken along line Y-Y' in FIG. 52(a).
As shown in FIGS. 2(a)-2(c), a second oxide film 102 is formed for forming a dummy pattern on a silicon substrate 101. A nitride film or a laminated film of an oxide film and polysilicon may be used.
As shown in FIGS. 3(a)-3(c), a first resist 103 is formed for forming the dummy pattern.
As shown in FIGS. 4(a)-4(c), the second oxide film 102 is etched to form the dummy pattern 102.
As shown in FIGS. 5(a)-5(c), the first resist 103 is removed.
As shown in FIGS. 6(a)-6(c), a first nitride film 104 is deposited.
As shown in FIGS. 7(a)-7(c), the first nitride film 104 is etched to be left as a sidewall. Consequently, a first nitride film sidewall 104 is formed around the dummy pattern 102. The first nitride film sidewall 104 is used for etching silicon to form a first fin-shaped silicon layer 106 and a second fin-shaped silicon layer 105 which are connected to each other at the ends thereof to form a closed loop.
As shown in FIGS. 8(a)-8(c), the dummy pattern 102 is removed.
As shown in FIGS. 9(a)-9(c), the silicon substrate 101 is etched using the first nitride film sidewall 104 as a mask to form the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer 105 which are connected to each other at the ends thereof to form a closed loop.
As shown in FIGS. 10(a)-10(c), a first insulating film 107 is formed around the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer 105. As the first insulating film, an oxide film formed by high-density plasma, or an oxide film formed by low-pressure chemical vapor deposition may be used.
As shown in FIGS. 11(a)-11(c), the first nitride film sidewall 104 is removed. When the first nitride film sidewall 104 is removed during silicon etching or deposition of the oxide film, this step is not required.
As shown in FIGS. 12(a)-12(c), the first insulating film 107 is etched back to expose an upper portion of the first fin-shaped silicon layer 106 and an upper portion of the second fin-shaped silicon layer 105.
As shown in FIGS. 13(a)-13(c), a second resist 108 is formed so as to be perpendicular to the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer 105. A portion where each of the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer 105 intersects at right angles the second resist 108 becomes a pillar-shaped silicon layer. Since a linear resist can be used, the resist is unlikely to fall after patterning, thereby realizing a stable process.
As shown in FIGS. 14(a)-14(c), the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer are etched. A portion where the first fin-shaped silicon layer 106 and the second resist 108 intersect at right angles becomes a first pillar-shaped silicon layer 110. A portion where the second fin-shaped silicon layer 105 and the second resist 108 intersect at right angles becomes a second pillar-shaped silicon layer 109. Therefore, the width of the first pillar-shaped silicon layer 110 is equal to the width of the first fin-shaped silicon layer 106. Also, the width of the second pillar-shaped silicon layer 109 is equal to the width of the second fin-shaped silicon layer 105.
As shown in FIGS. 15(a)-15(c), the second resist 108 is removed.
As shown in FIGS. 16(a)-16(c), a third oxide film 111 is deposited, and a second nitride film 112 is formed. Since upper portions of the pillar-shaped silicon layers are subsequently covered with a gate insulating film and polysilicon gate electrodes, diffusion layers are formed in upper portions of the pillar-shaped silicon layers before covering of the pillar-shaped silicon layers.
As shown in FIGS. 17(a)-17(c), the second nitride film 112 is etched to be left as a sidewall.
As shown in FIGS. 18(a)-18(c), a third resist 113 is formed for forming the n-type diffusion layers by impurity implantation in an upper portion of the first pillar-shaped silicon layer 110, an upper portion of the first fin-shaped silicon layer 106, and a lower portion of the first pillar-shaped silicon layer 110.
As shown in FIGS. 19(a)-19(c), impurities such as arsenic or phosphorus are implanted to form a n-type diffusion layer 115 in an upper portion of the first pillar-shaped silicon layer 110, and n-type diffusion layers 116 and 117 in an upper portion of the first fin-shaped silicon layer 106.
As shown in FIGS. 20(a)-20(c), the third resist 113 is removed.
As shown in FIGS. 21(a)-21(c), the second nitride film 112 and the third oxide film 111 are removed.
As shown in FIGS. 22(a)-22(c), heat treatment is performed. The n-type diffusion layers 116 and 117 in an upper portion of the first fin-shaped silicon layer 106 are brought into contact with each other to form a n-type diffusion layer 118.
As shown in FIGS. 23(a)-23(c), a fourth oxide film 119 is deposited, and a third nitride film 120 is formed. Since upper portions of the pillar-shaped silicon layers are subsequently covered with a gate insulating film and polysilicon gate electrodes, diffusion layers are formed in upper portions of the pillar-shaped silicon layers before the pillar-shaped silicon layers are covered.
As shown in FIGS. 24(a)-24(c), the third nitride film 120 is etched to be left as a sidewall.
As shown in FIGS. 25(a)-25(c), a fourth resist 121 is formed for forming the p-type diffusion layers by impurity implantation in an upper portion of the second pillar-shaped silicon layer 109, an upper portion of the second fin-shaped silicon layer 105, and a lower portion of the second pillar-shaped silicon layer 109.
As shown in FIGS. 26(a)-26(c), impurities such as boron are implanted to form a p-type diffusion layer 122 in an upper portion of the second pillar-shaped silicon layer 109, and p-type diffusion layers 123 and 124 in an upper portion of the second fin-shaped silicon layer 105.
As shown in FIGS. 27(a)-27(c), the fourth resist 121 is removed.
As shown in FIGS. 28(a)-28(c), the third nitride film 120 and the fourth oxide film 119 are removed.
As shown in FIGS. 29(a)-29(c), heat treatment is performed. The p-type diffusion layers 123 and 124 in an upper portion of the second fin-shaped silicon layer 105 are brought into contact with each other to form a n-type diffusion layer 125.
Next, a description is given of a manufacturing method for forming a first polysilicon gate electrode 127a, a second polysilicon gate electrode 127b, and a polysilicon gate line 127c using polysilicon in order to use the gate-last process. In order to use the gate-last process, an interlayer insulating film is deposited, and then the polysilicon gate electrodes and the polysilicon gate line are exposed by chemical mechanical polishing. Therefore, it is necessary to prevent upper portions of the pillar-shaped silicon layers from being exposed by chemical mechanical polishing.
As shown in FIGS. 30(a)-30(c), a gate insulating film 126 is formed, and polysilicon 127 is deposited and then planarized. After planarization, the top position of the polysilicon 127 is higher than the gate insulating film 126 disposed on the n-type diffusion layer 115 in an upper portion of the first pillar-shaped silicon layer 110 and higher than the gate insulating film 126 disposed on the p-type diffusion layer 122 in an upper portion of the second pillar-shaped silicon layer 109. As a result, when in order to use the gate-last process, the polysilicon gate electrodes and the polysilicon gate line are exposed by chemical mechanical polishing after the interlayer insulating film is deposited, the upper portions of the pillar-shaped silicon layers are not exposed by chemical mechanical polishing.
In addition, a fourth nitride film 128 is deposited. The fourth nitride film 128 is a film which inhibits the formation of silicide in upper portions of the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c when the silicide is formed in upper portions of the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer 105.
As shown in FIGS. 31(a)-31(c), a fifth resist 129 is formed for forming the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c. A portion corresponding to the gate line is preferably perpendicular to the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer 105. This is because a parasitic capacitance between the gate line and the substrate is decreased.
As shown in FIGS. 32(a)-32(c), the fourth nitride film 128 is etched, and the polysilicon 127 is etched to form the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c.
As shown in FIGS. 33(a)-33(c), the gate insulating film 126 is etched.
As shown in FIGS. 34(a)-34(c), the fifth resist 129 is removed.
The manufacturing method for forming, using polysilicon, the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c in order to use the gate-last process is described above. After the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c are formed, the top position of polysilicon is higher than the gate insulating film 126 on the n-type diffusion layer 115 in an upper portion of the first pillar-shaped silicon layer 110 and higher than the gate insulating film 126 on the p-type diffusion layer 122 in an upper portion of the second pillar-shaped silicon layer 109.
A silicide is not formed in upper portions of the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c, in the n-type diffusion layer 115 in an upper portion of the first pillar-shaped silicon layer 110, and in the p-type diffusion layer 122 in an upper portion of the second pillar-shaped silicon layer 109. When the silicide is formed in the n-type diffusion layer 115 in an upper portion of the first pillar-shaped silicon layer 110, and in the p-type diffusion layer 122 in an upper portion of the second pillar-shaped silicon layer 109, the manufacturing process is enlarged.
As shown in FIGS. 35(a)-35(c), a fifth nitride film 130 is deposited.
As shown in FIGS. 36(a)-36(c), the fifth nitride film 130 is etched to be left as a sidewall.
As shown in FIGS. 37(a)-37(c), a metal such as nickel or cobalt is deposited to form silicide 131 in upper portions of the n-type diffusion layer 118 and the p-type diffusion layer 125 formed in upper portions of the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer 105, respectively. At this time, the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c are covered with the fifth nitride film 130 and the fourth nitride film 128, and the n-type diffusion layer 115 in an upper portion of the first pillar-shaped silicon layer 110 and the p-type diffusion layer 122 in an upper portion of the second pillar-shaped silicon layer 109 are covered with the gate insulating film 126, the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c, and thus a silicide is not formed in these portions.
Next, a gate-last manufacturing method is described, in which after an interlayer insulting film 133 is deposited, the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c are exposed, the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c are etched, and then a metal is deposited to form a first metal gate electrode 134a, a second metal gate electrode 134b, and a metal gate line 134c.
As shown in FIGS. 38(a)-38(c), a sixth nitride film 132 is deposited for protecting the silicide 131.
As shown in FIGS. 39(a)-39(c), an interlayer insulating film 133 is deposited and then planarized by chemical mechanical polishing.
As shown in FIGS. 40(a)-40(c), the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c are exposed by chemical mechanical polishing.
As shown in FIGS. 41(a)-41(c), the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c are etched. Wet etching is preferred.
As shown in FIGS. 42(a)-42(c), a metal 134 is deposited and then planarized to fill, with the metal 134, portions from which the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c have been removed. Atomic layer deposition is preferably used.
As shown in FIGS. 43(a)-43(c), the metal 134 is etched to expose the gate insulating film 126 formed on the n-type diffusion layer 115 in an upper portion of the first pillar-shaped silicon layer 110 and expose the gate insulating film 126 formed on the p-type diffusion layer 122 in an upper portion of the second pillar-shaped silicon layer 109. Consequently, the first metal gate electrode 134a, the second metal gate electrode 134b, and the metal gate line 134c are formed.
The gate-last manufacturing method is described above, in which after the interlayer insulating film 133 is deposited, the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c are exposed, the first polysilicon gate electrode 127a, the second polysilicon gate electrode 127b, and the polysilicon gate line 127c are etched, and then the metal 134 is deposited to form the first metal gate electrode 134a, the second metal gate electrode 134b, and the metal gate line 134c.
As shown in FIGS. 44(a)-44(c), an interlayer insulating film 135 is deposited and then planarized.
As shown in FIGS. 45(a)-45(c), a sixth resist 136 is formed for forming a first contact hole 138 on the first pillar-shaped silicon layer 110 and a second contact hole 137 on the second pillar-shaped silicon layer 109. Then, the interlayer insulating film 135 is etched to form the first contact hole 138 and the second contact hole 137.
As shown in FIGS. 46(a)-46(c), the sixth resist 136 is removed.
As shown in FIGS. 47(a)-47(c), a seventh resist 139 is formed for forming a third contact hole 140 and a fourth contact hole 141 on the metal gate line 134c and on the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer 105.
As shown in FIGS. 49(a)-49(c), the seventh resist 139 is removed, and the sixth nitride film 132 and the gate insulating film 126 are etched to expose the silicide 131, the n-type diffusion layer 115, and the p-type diffusion layer 122. Then, a metal is deposited to form a first contact 144, a second contact 143, a third contact 142, and a fourth contact 145.
As shown in FIGS. 50(a)-50(c), a metal 146 is deposited.
As shown in FIGS. 51(a)-51(c), eighth resists 147, 148, 149, and 150 are formed for forming the metal wiring, and the metal 146 is etched to form metal wirings 151, 152, 153, and 154.
As shown in FIGS. 52(a)-52(c), the eighth resists 147, 148, 149, and 150 are removed.
The resulting structure includes: the first fin-shaped silicon layer 106 formed on the substrate 101 and the second silicon layer 105 formed on the substrate 101, the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer 105 being connected to each other at the ends thereof to form a closed loop; the first insulating film 107 formed around the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer 105; the first pillar-shaped silicon layer 110 formed on the first fin-shaped silicon layer 106; the second pillar-shaped silicon layer 109 formed on the second fin-shaped silicon layer 105, the width of the first pillar-shaped silicon layer 110 being equal to the width of the first fin-shaped silicon layer 106 and the width of the second pillar-shaped silicon layer 109 being equal to the width of the second fin-shaped silicon layer 105; the n-type diffusion layer 118 formed in an upper portion of the first fin-shaped silicon layer 106 and a lower portion of the first pillar-shaped silicon layer 110; the n-type diffusion layer 115 formed in an upper portion of the first pillar-shaped silicon layer 110; the p-type diffusion layer 125 formed in an upper portion of the second fin-shaped silicon layer 105 and a lower portion of the second pillar-shaped silicon layer 109; the p-type diffusion layer 122 formed in an upper portion of the second pillar-shaped silicon layer 109; the silicide 131 formed in upper portions of the n-type diffusion layer 118 and the p-type diffusion layer 125 in an upper portion of the first fin-shaped silicon layer 106 and in an upper portion of the second fin-shaped silicon layer 105; the gate insulating film 126 formed around the first pillar-shaped silicon layer 110 and the first metal gate electrode 134a formed around the gate insulating film 126; the gate insulating film 126 formed around the second pillar-shaped silicon layer 109 and the second metal gate electrode 134b formed around the gate insulating film 126; the metal gate line 134c connected to the first metal gate electrode 134a and the second metal gate electrode 134b and extending in a direction perpendicular to the first fin-shaped silicon layer 106 and the second fin-shaped silicon layer 105; and the first contact 144 formed on the n-type diffusion layer 115 formed in an upper portion of the first pillar-shaped silicon layer 110 and the second contact 143 formed on the p-type diffusion layer 122 formed in an upper portion of the second pillar-shaped silicon layer 109, the first contact 144 being in direct contact with the n-type diffusion layer 115 formed in an upper portion of the first pillar-shaped silicon layer 110 and the second contact 143 being in direct contact with the p-type diffusion layer 122 formed in an upper portion of the second pillar-shaped silicon layer 109.
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