Source: http://www.google.com/patents/US7994594?dq=6437692
Timestamp: 2017-05-24 22:55:36
Document Index: 393056345

Matched Legal Cases: ['art.\n8', 'art.\n9', 'art.\n10', 'art.\n11', 'art.\n12', 'art.\n13', 'art 8', 'art 8', 'art 8', 'art 8', 'art 8', 'art 13', 'art 15', 'art 13', 'art 15', 'art 13', 'art 15', 'art 13', 'art 15']

Patent US7994594 - Electronic device, resonator, oscillator and method for manufacturing ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn electronic device includes a substrate, a functional structural body formed on the substrate and a covering structure for defining a cavity part having the functional structural body disposed therein, wherein the covering structure is provided with a side wall provided on the substrate and comprising...http://www.google.com/patents/US7994594?utm_source=gb-gplus-sharePatent US7994594 - Electronic device, resonator, oscillator and method for manufacturing electronic deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7994594 B2Publication typeGrantApplication numberUS 12/045,990Publication dateAug 9, 2011Filing dateMar 11, 2008Priority dateMar 15, 2007Fee statusPaidAlso published asUS8129804, US20080224241, US20110303457, US20120127683Publication number045990, 12045990, US 7994594 B2, US 7994594B2, US-B2-7994594, US7994594 B2, US7994594B2InventorsShogo Inaba, Akira SatoOriginal AssigneeSeiko Epson CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (20), Referenced by (16), Classifications (11), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetElectronic device, resonator, oscillator and method for manufacturing electronic device
US 7994594 B2Abstract
An electronic device includes a substrate, a functional structural body formed on the substrate and a covering structure for defining a cavity part having the functional structural body disposed therein, wherein the covering structure is provided with a side wall provided on the substrate and comprising an interlayer insulating layer surrounding the cavity part and a wiring layer; a first covering layer covering an upper portion of the cavity part and having an opening penetrating through the cavity part and composed of a laminated structure including a corrosion-resistant layer; and a second covering layer for closing the opening.
1. An electronic device comprising a substrate, a functional structural body formed on the substrate and a covering structure for defining a cavity part having the functional structural body disposed therein, wherein
the covering structure is provided with a side wall provided on the substrate and comprising an interlayer insulating layer surrounding the cavity part and a wiring layer; a first covering layer covering an upper portion of the cavity part and having an opening penetrating through the cavity part and composed of a laminated structure including a corrosion-resistant layer; and a second covering layer for closing the opening.
4. The electronic device according to claim 1, wherein the corrosion-resistant layer is configured of a layer provided in the uppermost layer of the first covering layer.
5. The electronic device according to claim 1, wherein the corrosion-resistant layer is configured of a layer provided in the lowermost layer of the first covering layer.
6. The electronic device according to claim 1, wherein the corrosion-resistant layer is configured of layers provided in the uppermost layer and lowermost layer of the first covering layer.
7. The electronic device according to claim 1, wherein the first covering layer is of a laminated structure in which a Ti layer, a TiN layer, an Al—Cu layer and a TiN layer are laminated in this order from the surface facing at the cavity part.
8. The electronic device according to claim 1, wherein the first covering layer is of a laminated structure in which a TiN layer, an Al—Cu layer, a Ti layer and a TiN layer are laminated in this order from the surface facing at the cavity part.
9. The electronic device according to claim 1, wherein the first covering layer is of a laminated structure in which a Ti layer, a TiN layer, an Al—Cu layer, a Ti layer and a TiN layer are laminated in this order from the surface facing at the cavity part.
10. The electronic device according to claim 1, wherein the first covering layer is of a laminated structure in which a Ti layer, an Al—Cu layer and a TiN layer are laminated in this order from the surface facing at the cavity part.
11. The electronic device according to claim 1, wherein the first covering layer is of a laminated structure in which a TiN layer, an Al—Cu layer and a TiN layer are laminated in this order from the surface facing at the cavity part.
12. An electronic device comprising a substrate having a functional structural body provided in the inside of a cavity part and a CMOS circuit part placed side by side on the substrate, wherein
a covering structure for defining the cavity part is provided with a side wall comprising an interlayer insulating layer surrounding the cavity part and a wiring layer and a first covering layer covering an upper portion of the cavity part and having an opening penetrating through the cavity part and composed of a laminated structure including a corrosion-resistant layer; and
at least one of the interlayer insulating layer and the wiring layer is a part of an interlayer insulating layer or a wiring layer of the CMOS circuit part.
13. A resonator comprising a substrate, a functional structural body formed on the substrate and a covering structure for defining a cavity part having the functional structural body disposed therein, wherein
14. An oscillator comprising a substrate having a functional structural body provided in the inside of a cavity part and an oscillation circuit-containing CMOS circuit part placed side by side on the substrate, wherein
15. A method for manufacturing an electronic device including a substrate, a functional structural body formed on the substrate and a covering structure for defining a cavity part having the functional structural body disposed therein, comprising
a functional structural forming process of forming the functional structural body together with a sacrifice layer on the substrate;
an interlayer insulating layer forming process of forming an interlayer insulating layer in the periphery including an upper part of the functional structural body;
a first covering layer forming process of forming a first covering layer composed of a laminated structure including a corrosion-resistant layer on the interlayer insulating layer and having an opening;
a release process of removing the interlayer insulating layer and the sacrifice layer on the functional structural body through the opening; and
a second covering layer forming process of forming a second covering layer for closing the opening.
16. A method for manufacturing an electronic device including a substrate having a functional structural body provided in the inside of a cavity part and a CMOS circuit part placed side by side on the substrates comprising
forming the functional structural body together with a sacrifice layer on the substrate;
forming a CMOS transistor;
forming an interlayer insulating layer in the periphery including an upper part of the functional structural body and an upper part of the CMOS transistor;
forming a first covering layer for covering the cavity part and having an opening, a wiring layer connected to the functional structural body and a wiring layer connected to the CMOS transistor in an upper part of the interlayer insulating layer;
forming a passivation membrane in the periphery including the first covering layers the wiring layer connected to the functional structural body and the wiring layer connected to the CMOS transistor;
removing the interlayer insulating layer and the sacrifice layer on the functional structural body through the opening; and
forming a second covering layer for closing the opening. Description
An advantage of some aspects of the invention is to provide a structure of each of an electronic device, a resonator and an oscillator capable of efficiently carrying out a manufacturing process of an electronic device comprising a functional structural body disposed in a cavity on a substrate and an electronic circuit, securing a manufacturing yield and reducing the manufacturing costs and a method for manufacturing an electronic device.
Also, it is desirable that the first covering layer is of a laminated structure in which a Ti layer, a TiN layer, an Al—Cu layer and a TiN layer are laminated in this order from the surface facing at the cavity part.
Also, it is desirable that the first covering layer is of a laminated structure in which a TiN layer, an Al—Cu layer, a Ti layer and a TiN layer are laminated in this order from the surface facing at the cavity part.
Furthermore, it is desirable that the first covering layer is of a laminated structure in which a Ti layer, a TiN layer, an Al—Cu layer, a Ti layer and a TiN layer are laminated in this order from the surface facing at the cavity part.
Also, it is desirable that the first covering layer is of a laminated structure in which a Ti layer, an Al—Cu layer and a TiN layer are laminated in this order from the surface facing at the cavity part.
Also, it is desirable that the first covering layer is of a laminated structure in which a TiN layer, an Al—Cu layer and a TiN layer are laminated in this order from the surface facing at the cavity part.
According to such a configuration, since in each of the functional structural body and the CMOS circuit part, the interlayer insulating layer and the wiring layer can be partially made common to each other, it is possible to achieve thinning or miniaturization. Also, the manufacture can be efficiently achieved by employing a semiconductor manufacturing process, and it is aimed to reduce the manufacturing costs.
Next, embodiments of the invention are described in detail with reference to the accompanying drawings. For convenience of illustration, the drawings as referred to in the following description are each a schematic view in which the reduction in length and width and thickness of members or portions is different from that in an actual scale.
First of all, a manufacturing method of an electronic device according to Embodiment 1 is described. FIGS. 1 to 8 are each a diagrammatic process view showing a manufacturing method of an electronic device according to an embodiment of the invention.
In the present embodiment, as shown in FIG. 3, a lower surrounding wall (guard ring) 3Y configured so as to planarly surround the MEMS structural body 3X is formed simultaneously with the MEMS structural body X. The lower surrounding wall 3Y is one configured of the same layer and same material as in the MEMS structural body 3X and is formed simultaneously with the MEMS structural body 3X by patterning the functional layer 3. In the illustrated embodiment, though the planar shape of the lower surrounding wall 3Y is formed, for example, in a quadrangular (square) shape, it may be any shape such as a circle and a polygon so far as it is a closed shape for surrounding the MEMS structural body 3X. The lower surrounding wall 3Y is preferably made of a raw material which is not substantially removed in a release process of removing the sacrifice layer 2 and interlayer insulating layers 4 and 6 (see FIG. 4) as described later (in other words, the removal method of the release process is a method having selectivity against etching between the raw material to be removed and the lower surrounding wall 3Y) and more desirably made of a conductive material. Examples of the conductive material include conductive semiconductors (semiconductors doped in a high concentration), polysilicons and metallic materials to be used in a corrosion-resistant layer as described later.
In the illustrated embodiment, the wiring layer 5 is formed as a single layer. However, plural wiring layers 5 may be laminated via a non-illustrated other interlayer insulating layer. In that case, the surround layer 5Y is also formed as plural layers. Here, it is preferable that the plural surrounding walls 5Y are connected through an opening part of the interlayer insulating layer. In particular, when the opening part itself and the connection portion of the surrounding wall which goes through the inside thereof are formed in a closed shape for surrounding the MEMS structural body 3X, the plural surrounding walls 5Y are configured as an integrated side wall.
As described above, in the case where an integrated side wall 10 Y (see FIG. 8) is formed by the lower surrounding wall 3Y, the surrounding wall 5Y and the first covering layer 7Y, the HEMS structural body 3X is completely surrounded by the substrate 1, the side wall 10Y and the first covering layer 7Y from a lower portion, an upper portion and a side portion.
The foregoing etching method does not substantially exhibit removal performance against the MEMS structural body 3X, the lower surrounding wall 3Y, the surrounding wall 5Y and the first covering layer 7Y. Therefore, even when the interlayer insulating layer 6, the interlayer insulating layer 4 and the sacrifice layer 2 existing in the surroundings of the MEMS structural body 3X are completely removed, it is possible to prevent the cavity part S from expansion to the outside of the lower surrounding wall 3Y and the surrounding wall 5Y. Here, when the release process is finished, the cavity part S is thoroughly rinsed. For example, the cavity part S is washed with water, and thereafter, the moisture is completely removed by using a displacement method or the like. The lower surrounding wall 3Y, the surrounding wall 5Y and a lower part of the first covering layer 7Y (connecting part in the through-hole 6 a) configure the foregoing surrounding covering part.
Next, a passivation membrane 8 configured of silicon oxide, silicon nitride, a resin material or the like is formed on the interlayer insulating layer 6, the first covering layer 7 and other portion (not illustrated) of the wiring layer 7 formed simultaneously therewith as shown in FIG. 8. As this passivation membrane 8, a surface passivation membrane made of silicon nitride, an insulating resist or the like can be used. By forming an opening part 8 a in the passivation membrane 8 by dry etching or the like, apart of each of the first covering layer 7Y and the wiring layer 7 is exposed to form a pad part for conductive connection. Also, an opening part 8 b is formed in the passivation membrane 8 simultaneously with the opening part 8 a, and a portion existing in an upper portion of the MEMS structural body 3X (a region where the opening 7 a is formed) is exposed by this opening part 8 b. So far as the passivation membrane 8 is made of a material capable of withstanding etching of the release process, or a mask of a resist or the like is formed on a surface of the passivation membrane 8, the formation and patterning of the passivation membrane 8 may be carried out prior to the release process as described later.
As shown in FIG. 9, the wiring layer 7 (first covering layer 7Y) is configured of a laminated structure of four layers including a first layer 7 b as the lowermost layer which is made of Ti, a second layer 7 c which is made of TiN, a third layer 7 d which is made of Al—Cu (alloy) and a fourth layer 7 e as the uppermost layer which is made of TiN from the surface facing at the cavity part S. The first layer 7 b enhances coverage against the interlayer insulating layer 6 as the lower layer and is formed in a thickness of from about 10 to 100 nm, and preferably from about 20 to 70 nm by, for example, a vapor deposition method, a sputtering method or the like. The second layer 7 c is a barrier layer for preventing the penetration of constitutional raw materials of the lower layer (for example, an Si atom), impurities or the like and is formed by, for example, a sputtering method, a CVD method, an ion plating method or the like and made to have a thickness of from about 50 to 200 nm, and preferably from about 80 to 150 nm. The third layer 7 d is configured of an alloy obtained by adding not more than 1 wt % of Cu to Al and is a principal layer for guaranteeing conductivity of the wiring layer 7. The third layer 7 d is formed by, for example, a vapor deposition method or a sputtering method and made to have a thickness of from about 500 to 1,000 nm, and preferably from about 700 to 900 nm. The fourth layer 7 e is configured as an antireflection membrane for photo process and can be formed by, for example, the same method as in the second layer 7 c. The fourth layer 7 e is made to have a thickness of from about 20 to 200 nm, and preferably from about 50 to 100 nm.
The first covering layer 7Y has the same laminated structure as in the wiring layer 7. Here, each of the raw materials which configure the wiring layer 7 is one provided with resistance to etching to be used at the time of a release process as described later (this etching is basically used for the purpose of removing a configuration portion mainly composed of silicon oxide). However, since the third layer (Al—Cu) 7 d does not have a thoroughly high etching selection ratio to silicon oxide, it is possibly removed by the etching over a long period of time. On the other hand, the first layer (Ti) 7 b, the second layer (TiN) 7 c and the fourth layer (TiN) 7 e have a high etching selection ratio so that they thoroughly withstand the etching over a long period of time.
For example, the first covering layer 7Y may be of a laminated structure in which a TiN layer, an Al—Cu layer, a Ti layer and a TiN layer are laminated in this order from the surface facing at the cavity part S and may also be of a laminated structure in which a Ti layer, a TiN layer, an Al—Cu layer, a Ti layer and a TiN layer are laminated in this order from the surface acing at the cavity part S.
Furthermore, the first covering layer 7Y may be of a laminated structure in which a Ti layer, an Al—Cu layer and a TiN layer are laminated in this order from the surface facing at the cavity part S and may also be of a laminated structure in which a TiN layer, an Al—Cu layer and a TiN layer are laminated in this order from the surface facing at the cavity part S.
Finally, as shown in FIG. 8, by forming a second covering layer 9 on the first covering layer 7Y, the opening 7 a is closed, thereby sealing the cavity part S. An electronic device 100 is thus accomplished. It is preferable that this second covering layer 9 is formed by a vapor phase epitaxy method, for example, a CVD method and a sputtering method. This is because according to this, the cavity part S can be sealed in a state of reduced pressure as it is. As the second covering layer 9 to be formed by a vapor phase epitaxy method, insulators such as silicon oxide and silicon nitride (CDV method), metals (for example, Al, W and Ti) or other conductive materials (sputtering method) and the like are exemplified.
The electronic device of the present embodiment has a covering structure in which the cavity part S for accommodating the MEMS structural body 3X therein is surrounded by the laminated structure of the interlayer insulating layers 4 and 6 and the wiring layers 5 and 7 and the cavity part S is defined by this covering structure. Accordingly, by configuring the first covering layer 7Y for covering the upper part of the cavity part S by a part of the wiring layer 7, it is possible to enhance the integrality with an electronic circuit requiring the foregoing laminated structure. Therefore, not only it is possible to aim to miniaturize the electronic device, but it is possible to suppress the manufacturing costs. In particular, when the first covering layer 7Y for covering the MEMS structural body 3X from an upper portion is configured of a conductive material composed of a part of the wiring layer 7, an electromagnetic mutual action with the outside can be reduced. In that case, needless to say, it is more favorable that the second covering layer 9 is also configured of a conductive material.
Furthermore, in the foregoing configuration, when the integrated side wall 10Y is formed so as to surround the MEMS structural body 3X, the removal range in the release process can be planarly completely limited, and therefore, it is possible to aim to further miniaturize the cavity part S. Also, when the whole of the side wall 10Y is configured of a conductive material, a blocking degree by the conductor of the MEMS structural body 3X is further enhanced, and therefore, it is possible to more reduce the electromagnetic mutual action between the MEMS structural body 3X and the outside. In particular, in view of the matter that the side wall 11Y and the first covering layer 7Y are connected to each other, the electromagnetic blocking effect of the MEMS structural body 3X can be further enhanced.
In this manufacturing process, after forming the passivation film B and also forming its opening part 8 b, the release process is carried out through the openings 7 a of the first covering layer 7Y. According to this method, since the passivation membrane 8 can be used as an etching mask at the time of release process, the resist forming process for forming the etching mask 9′ in the foregoing embodiment or the like can be omitted.
Subsequently, an electronic device according to Embodiment 2 is described with reference to the accompanying drawings. The electronic device according to the present embodiment is characterized in that a semiconductor substrate is used as a substrate and that a functional structural body disposed in the inside of a cavity part and a CMOS circuit part are placed side by side on the substrate.
Interlayer insulating layers 16 and 18 which are an insulating layer and which are composed of silicon oxide (SiO2) in more detail, PSG (phosphorus-doped glass) or TEOS (CVD membrane formed using, as a raw material gas, tetraethyl ortho-silicate, etc.) or the like, wiring layers 17A, 17B, 17C and 17D composed of a conductor layer of aluminum, etc., a first covering layer 19A and wiring layers 19B, 19C, 19D and 19E are formed on the substrate 11. These wiring layers 19B, 19C, 19D and 19E are made to act as a conductive pattern for forming a prescribed circuit on the substrate 11. A passivation membrane 21 composed of silicon oxide (SiO2), silicon nitride (Si3N4) or the like is laminated on the foregoing respective layers. This passivation membrane 21 is configured of a raw material having patterning (etching) selectivity against the interlayer insulating layers 16 and 18 and a sacrifice layer as described later. Furthermore, a second covering layer 22 is formed on the first covering layer 19A.
The first covering layer 19A is formed simultaneously with the wiring layers 19B, 19C, 19D and 19E. For example, a metallic layer is fabricated, and thereafter, the first covering layer 19A provided with the openings 19 a is formed simultaneously with external shapes of the first covering layer 19A and the respective wiring layers by means of patterning. Here, there may be the case where the first covering layer 19A is configured of a laminated structure of plural layers similar to other wiring layers. For example, a first layer (lowermost layer) is configured of Ti or TiN in a thickness of from 1 to 1,000 nm, and preferably about 50 nm; a second layer (middle layer) is configured of an Al—Cu alloy layer in a thickness of from 10 to 10,000 nm, and preferably about 800 nm; and a third layer (uppermost layer) is configured of TiN in a thickness of from 1 to 1,000 nm, and preferably about 50 nm. In that case, by removing the first layer to be disposed just above the cavity part C, it is possible to easily carry out the release process.
Also, with respect to the configuration of the first covering layer 19A, as described in Embodiment 1 (see FIG. 9), a laminated structure in which a Ti layer, a TiN layer, an Al—Cu layer and a Ti—N layer are laminated in this order from the surface facing at the cavity part C; a laminated structure in which a TiN layer, an Al—Cu layer, a Ti layer and a TiN layer are laminated in this order from the surface facing at the cavity part C; a laminated structure in which a Ti layer, a TiN layer, an Al—Cu layer, a Ti layer and a TiN layer are laminated in this order from the surface facing at the cavity part C; a laminated structure in which a Ti layer, an Al—Cu layer and a TiN layer are laminated in this order from the surface facing at the cavity part C; and a laminated structure in which a TiN layer, an Al—Cu layer and a TiN layer are laminated in this order from the surface facing at the cavity part C can be adapted.
FIG. 15 is a planar layout view showing a diagrammatic structure of an MEMS structural body region according to the present embodiment. In FIG. 15, the lower structure part 13A and the upper structure part 15A are formed in a substantially central part of the MEMS structural body region 150. A part of the lower structure part 13A and a part of the upper structure part 15S intersect each other and are disposed separately (see FIG. 14).
Next, an interlayer insulating layer 16 is formed on the foregoing structure by a sputtering method, a CVD method or the like, and a group of through-holes including the through-holes 17 a and 17 e is formed by means of patterning. Thereafter, an appropriate wiring pattern is formed on the interlayer insulating layer 16 by a vapor deposition method, a sputtering method, a CVD method or the like, and the wiring layer 17E conductively connected to the lower structure part 13A via the through-hole 17 e and the wiring layer 17A conductively connected to the upper structure part 15A via the through-hole 17 a are formed.
Next, as shown in FIG. 18, the first covering layer 19A and the wiring layers 19B, 19C, 19D, 19E and 19F are formed on the interlayer insulating layer 18 by a vapor deposition method, a sputtering method, a CVD method or the like. As to the MEMS structural body, a wiring layer for connecting each of the wiring layer 19F connected to the lower structure part 13A and the wiring layer 19B connected to the upper structure part 15R to the foregoing CMOS circuit part (CMOS transistor) is formed (wiring layer forming step) The openings 19 a are formed in the first covering layer 19A along with an external shape pattern or a wiring pattern by means of a fine patterning technology.
Subsequently, the interlayer insulating layers 18 and 16 and the sacrifice layer 14A existing beneath the openings 19 a are removed through the openings 19 a by a hydrofluoric acid aqueous solution, a buffer hydrofluoric acid aqueous solution, a hydrofluoric acid gas or the like (release process). According to this, the cavity part C is formed. Thereafter, the inner surface of the cavity part C is rinsed by means of water washing or the like.
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