Source: https://patents.google.com/patent/US8803229
Timestamp: 2018-07-23 16:06:54
Document Index: 791514708

Matched Legal Cases: ['Art. 94', 'Art. 94', 'Art. 94', 'Art. 94', 'Application No. 10', 'Application No. 10']

US8803229B2 - Nanowire transistor with surrounding gate - Google Patents
Nanowire transistor with surrounding gate Download PDF
US8803229B2
US8803229B2 US13417809 US201213417809A US8803229B2 US 8803229 B2 US8803229 B2 US 8803229B2 US 13417809 US13417809 US 13417809 US 201213417809 A US201213417809 A US 201213417809A US 8803229 B2 US8803229 B2 US 8803229B2
US13417809
US20120168855A1 (en )
This application is a Continuation of U.S. application Ser. No. 12/192,618, filed Aug. 15, 2008, now U.S. Pat. No. 8,134,197 which is a Divisional of U.S. application Ser. No. 11/397,527, filed Apr. 4, 2006, now issued as U.S. Pat. No. 7,425,491, both of which are incorporated herein by reference in their entirety.
1. An array of transistors comprising:
a plurality of transistors in rows and columns on the crystalline substrate, wherein row spacing between adjacent rows and column spacing between adjacent columns is determined by a minimum feature size (F) for a lithographic process; and
each transistor in the transistor array comprises:
a first source/drain region in the crystalline substrate;
a semiconductor pillar on the crystalline substrate in contact with the first source/drain region, the semiconductor pillar having a cross-sectional dimension in a direction substantially parallel with a surface of the substrate that is less than the minimum feature size F;
a second source/drain region in a top portion of the semiconductor pillar;
a gate insulator around the semiconductor pillar; and
a surrounding gate around and separated from the semiconductor pillar by the gate insulator.
2. The array of transistors of claim 1, wherein the cross-sectional dimension is on the order of one third of the minimum feature size.
3. The array of transistors of claim 1, wherein the semiconductor pillar has a height to provide a channel length on the order of 100 nm.
4. The array of transistors of claim 1, wherein the gate insulator includes an insulator material between the surrounding gate and the semiconductor pillar, and wherein the insulator material is also between the gate and the substrate.
5. The array of transistors of claim 1, wherein each transistor further comprises: a gate contact adjacent to and in contact with the surrounding gate, and wherein the surrounding gate and the gate contact each have a top surface below a top surface of the semiconductor pillar.
6. An array of transistors comprising a plurality of transistors arranged in rows and columns, wherein a lithographic process is used to fabricate features used to form the transistors in the array, and wherein the lithographic process is constrained by a minimum feature size, each transistor in the transistor array comprising:
a semiconductor pillar on the substrate in contact with the first source/drain region, the semiconductor pillar having a cross-sectional dimension less than the minimum feature size;
7. The array of transistors of claim 6, wherein the cross-sectional dimension is on the order of one third of the minimum feature size.
8. The array of transistors of claim 6, wherein the semiconductor pillar has a height to provide a channel length on the order of 100 nm, wherein the channel is between the first and second source/drain regions.
9. The array of transistors of claim 6, wherein the gate insulator includes an insulator material between the surrounding gate, and wherein the insulator material is also between the surrounding gate and the substrate.
10. The array of transistors of claim 6, wherein the array has a center-to-center spacing between adjacent rows of twice the minimum feature size.
11. The array of transistors of claim 6, wherein the array has a center-to-center spacing between adjacent columns of twice the minimum feature size.
12. The array of transistors array of claim 6, wherein the gate insulator includes silicon oxide.
13. A transistor fabricated on a substrate using a lithographic process constrained by a minimum feature size, the transistor comprising:
a surrounding gate around, and separated from, the semiconductor pillar by the gate insulator.
14. The transistor of claim 13, wherein the cross-sectional dimension is on the order of one third of the minimum feature size.
15. The transistor of claim 13, wherein the cross-sectional dimension is on the order of 30 nm.
16. The transistor of claim 13, wherein the surrounding gate insulator includes silicon oxide.
17. The transistor of claim 13, wherein the surrounding gate includes a polysilicon gate.
18. The transistor of claim 13, wherein the surrounding gate includes a metal gate.
19. A transistor fabricated on a crystalline substrate using a lithographic process constrained by a minimum feature size, the transistor comprising:
a semiconductor pillar on the substrate in contact with the first source/drain region, the semiconductor pillar having cross-sectional dimensions less than the minimum feature size in both a first direction and a second direction, the second direction orthogonal to the first direction, wherein the first and second directions are substantially parallel with a surface of the substrate;
a second source/drain region in a top portion of the semiconductor pillar, wherein the first and second source/drain regions define a channel region in the semiconductor pillar between the first and second source/drain regions;
20. The transistor of claim 19, wherein the cross-sectional dimensions are on the order of one third of the minimum feature size.
21. The transistor of claim 19, wherein the cross-sectional dimensions in the first and second direction are on the order of 30 nm, and the channel region in the semiconductor pillar has a length on the order of 100 nm between the first and second source/drain regions.
US13417809 2006-04-04 2012-03-12 Nanowire transistor with surrounding gate Active 2026-07-15 US8803229B2 (en)
US12192618 Continuation US8134197B2 (en) 2006-04-04 2008-08-15 Nanowire transistor with surrounding gate
US20120168855A1 true US20120168855A1 (en) 2012-07-05
US8803229B2 true US8803229B2 (en) 2014-08-12
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