Source: http://www.google.com/patents/US6374381?dq=5537618&ei=urENT6-uEoHegQe698i5Bw
Timestamp: 2016-05-25 23:19:34
Document Index: 565848961

Matched Legal Cases: ['arts 41', 'arts 41', 'arts 41', 'art 41', 'art 42', 'art 43', 'arts 41']

Patent US6374381 - Semiconductor memory device, and method of checking the semiconductor device ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor memory device has a memory circuit, a code tagging section, an error processing section, and a changeover circuit. The memory circuit writes and reads data into and from a memory area designated by an address signal. The code tagging section includes a write data register and an error...http://www.google.com/patents/US6374381?utm_source=gb-gplus-sharePatent US6374381 - Semiconductor memory device, and method of checking the semiconductor device and method of using the sameAdvanced Patent SearchPublication numberUS6374381 B1Publication typeGrantApplication numberUS 09/271,331Publication dateApr 16, 2002Filing dateMar 18, 1999Priority dateMar 19, 1998Fee statusPaidAlso published asCN1118830C, CN1229999APublication number09271331, 271331, US 6374381 B1, US 6374381B1, US-B1-6374381, US6374381 B1, US6374381B1InventorsTakaaki MoriyaOriginal AssigneeNec CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (24), Classifications (16), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor memory device, and method of checking the semiconductor device and method of using the same
US 6374381 B1Abstract
A semiconductor memory device has a memory circuit, a code tagging section, an error processing section, and a changeover circuit. The memory circuit writes and reads data into and from a memory area designated by an address signal. The code tagging section includes a write data register and an error correction code generation circuit for tagging an error checking code to input data, and sending it to the memory circuit as write data. The error processing section includes an error detection circuit and an error correction circuit for checking presence of an error after receiving read data from the memory circuit and correcting it when detected. The changeover circuit sends data from the code tagging section to the error processing section, and sends data from the code tagging section to the error processing section only when the address signal does not designate a memory area in the memory circuit.
s0=x1*x2*x3*x4 s1=x0*x2*x3*x5 s2=x0*x1*x3*x6 Herein, a code “*” in the foregoing formulae represents logical sum. Thereafter, the syndrome generation circuit 106-1 outputs the calculated syndrome values s0, s1 and s2 from EXOR gates 106C, 106F and 106J to the syndrome decode circuit 106-2.
EF=s0+s1+s2 In the foregoing eight formulae, a code “−” represents logical inversion and a code “+” represents logical sum. In FIG. 12 an error correction circuit for bits y4 to y6 corresponding to check bits x4 to x6 is omitted.
The error detection circuit 106 sends the foregoing flag generated as such to the error detection flag register 107. If there is no error, then the foregoing flag indicates “0” while if there is any error, then the foregoing flag indicates “1”. The error correction circuit 108 sends the generated bits y0 to y3 to the read data register 109 as the read data h4. Such an error correction code generation circuit 103, error detection circuit 106 and error correction circuit 108 constitute the ECC circuit.
The present invention has been made to solve the aforementioned problems of the prior art, and has an object to provide a semiconductor memory device capable of simplifying changeover between an ordinary mode and a test mode and of shortening test time for an error detection and error correction function, and further provide a method of checking the semiconductor memory device and a method of using the same.
Referring to the accompanying drawings there will be described varieties of preferred embodiments of the present invention.
The address signal a applied to the memory circuit 4 serves to select the memory parts 41, 42, and 43, and the memory areas in the memory circuit 4, and to control the changeover circuit 5. More specifically, upper rank 2 bits of the address signal a are used to designate the memory parts 41, 42, and 43, and to control the changeover circuit 5, and a third bit and bits after it are used to designate the memory areas of the memory parts 41, 42, and 43 upon writing and reading. Concretely, as shown in the next table 1, when the upper 2 bits of the address signal a are “00”, the address signal a indicate that an object to read and write is the memory part 41.
Likewise, when the upper 2 bits are “01”, the address signal a takes the memory part 42 as an object, and when the upper 2 bits are “10”, the address signal a takes the memory part 43 as an object. Further, when the upper rank 2 bits are “11”, the address signal a indicates a memory part which is not existent in the memory circuit 4. Thus, since the address signal a does not designate any memory part in the memory circuit, the memory circuit 4 does not write and read data. An address signal a with the upper 2 bits being “11” is used as a control signal for the changeover circuit 5.
In the ordinary mode, where the upper 2 bits of the address signal a are any of “00”, “01”, and “10”, the changeover circuit 5 connects the memory circuit 4 with the error detection circuit 6 and the error correction circuit 8.
In the test mode, the address signal a has its upper 2 bits being “11”, the changeover circuit 5 separates the memory circuit 4 and connects the error correction code generation circuit 3 with the error detection circuit 5 and the error correction circuit 8.
When data is written, an external device (not shown) designates any of the memory parts 41 to 43, and adds an address signal a designating any memory area of any of the memory parts to the address register 1. When the address signal a is the ordinary mode, i.e., it takes upper 2 bits being any of “00”, “01”, and “10”, the changeover circuit 5 connects the memory circuit 4 to the error detection circuit 6 and the error correction circuit 8.
The error detection circuit 6 judges based upon an error correction code tagged to the read data c whether the read data c involves any error therein or not. When there is any error in the read data c, the error detection circuit 6 sends a flag d2 having a value “1” to the detection flag register 7. The aforesaid external device is hereby informed of occurrence of error. The error detection circuit 6 sends a detection result d1 indicative of error detection to the error correction circuit 8. The error correction circuit 8 corrects the error in the read data c, and sends the read data to the read data register 9. The external device thus receives-the data where the error involved therein is corrected.
In the following, changeover operation from the ordinary mode to the test mode will be described. In the test mode, it is checked whether or not the ECC circuit composed of the error correction code generation circuit 3, error detection circuit 6, and error correction circuit 8 is normally operated in its error detection/correction function. Firstly, the external device sends an address signal a, in which the upper 2 bits are “11”, to the address register 1. The address register 1 sends the address signal a to the memory circuit 4 and the changeover circuit 5. The memory circuit 4, since the upper 2 bits of the address signal a are “11”, does not have a memory part corresponding to the value “11”. The memory circuit 11 hence does not write and read data. The changeover circuit 5, since the upper 2 bits of the address signal a are “11”, connects the error correction code generation circuit 3 to the error detection circuit 6 and the error correction circuit 8. The memory circuit 4 is thus bypassed.
When the device is used in the test mode, the external device, when it diagnoses the aforesaid ECC circuit, first checks whether or not the error detection circuit 6 and the error correction circuit 8 are normally operated. For this the external device executes first diagnosis. More specifically, the external device applies an address signal where upper rank 2 bits are set to be “11” to the address register 1. Hereby, the changeover circuit 5 connects the changeover circuit 13 to the error detection circuit 6 and the error correction circuit 8. Further, the external device applies a changeover signal e indicative of the aforesaid second changeover to the changeover circuit 13 through the test mode register 11. Hereby, the changeover circuit 13 connects the bypass 12 to the memory circuit 4 and the changeover circuit 5.
As understood in the aforesaid construction, when the changeover signal f is “0”, the inverter 22U outputs “1”. Accordingly, to the NAND gates 22Q to 22T the value “1” is applied, so that the changeover signal f of a value “0” does not influence output values from the inverters 22K to 22M. Likewise, in the NOR gate 22P the changeover signal of a value “0” does not influence an output from the NOR gate 22N. Thus, when the changeover signal f is “0”, the syndrome decode circuit 22-2 operates in the same fashion as the syndrome decode circuit 106-2 in FIG. 12.
When the changeover signal f is “1”, the inverter 22U applies a value “0” to the NAND gates 22Q to 22T. Hereby, outputs of the NAND gates 22Q to 22T become “1”. As a result, the error detection circuit 22 sends a detection result d1 of a value “1” indicative of no error. Simultaneously, when the changeover signal f is the value “1”, the NOR gate 22P sends an output of a value “0” to the error detection flag register 7 as a flag d2. The flag d2 here indicates no error in applied data.
Thus, when the changeover signal f is a value “1”, the syndrome decode circuit 22-2 is fixed to a state that indicates no error in inputted data irrespective of presence of any error in the inputted data.
When the embodiment is used in the ordinary mode, the aforesaid external device applies a signal for changing over the changeover circuit 13 and the error detection circuit 22 to the test mode register 21. Hereby, the test mode register 21 sends a changeover signal e indicative of first changeover to the changeover circuit 13 and the changeover signal f indicative of a value “0” to the error detection circuit 22. As a result, data from the write data register 2 is applied to the memory circuit 4 after passage through the error correction code generation circuit 3 and the changeover circuit 13. Further, data read from the memory circuit 4 is applied to the error correction circuit 8 and the error detection circuit 22. Thus, use in the ordinary mode is ensured.
The aforesaid external device applies to the test mode register 21 a signal for changing over the changeover circuit 13 and the error detection circuit 22. Hereby, the test mode register 21 sends a changeover signal e indicative of second changeover to the changeover circuit 13 and the changeover signal f indicative of a value “1” to the error detection circuit 22. Hereby, data from the write register 2 bypasses the error correction code generation circuit 3, and is written into the memory circuit 4 after passage through the changeover circuit 13.
The error detection circuit 22 is fixed to a state where read data c is correct at all times using the changeover signal f of a value “1”. The error detection circuit 22 sends to the error correction circuit 8 a detection result d1 indicative of a fact that the read data c is normal. The error correction circuit 8 after receiving the detection result d1 sends read data c read from the memory circuit 4 to the read register 9 without correcting error in the read data c.
In the error detection circuit 23 in FIG. 6, the changeover signal f is applied to the AND gate 23-3 through the inverter 23-2. When the changeover signal f is a value “0”, the inverter 23-2 provides an inverted output of the changeover signal f, i.e., the changeover signal f of a value “1” to the AND gate 23-3. Hereby, the AND gate 23-3 is opened to provide data from the syndrome generation circuit 23-1 to the syndrome decode circuit 23-4. Thus, the error detection circuit 23 achieves ordinary error detection.
When the changeover signal f is a value “1”, the inverter 23-2 applies an inverted output of the changeover signal f, i.e., the changeover signal of “0” to the AND gate 23-3. Hereby, the AND gate 23-3 is closed to prevent data from the syndrome generation circuit 23-1 from being applied to the syndrome decode circuit 23-4. In this case, the AND gate 23-3 provides an output of a value of “0” to the syndrome decode circuit 23-4. Thus, the syndrome decode circuit 23-4 provides a detection result d1 of a value “0” that indicates no error to the error correction circuit 8. Simultaneously, the syndrome decode circuit 23-4 outputs a flag d2 of a value “0” that indicates that there is no error in the read data c by receiving the value “0” from the AND gate 23-3.
Thus, the error detection circuit 23 is fixed using the changeover signal f of the value “1” to a state indicating that the read data c from the memory circuit 4 is correct at all times.
In the error detection circuit 24 in FIG. 7, the changeover signal f is applied to the AND gates 24-3, 24-4 through the inverter 24-2. When the changeover signal f is a value “0”, the inverter 24-2 provides an inverted output of the changeover signal f, i.e., the changeover signal f of a value “1” to the AND gates 24-3, 24-4. Hereby, the AND gates 24-3, 24-4 are opened to pass a detection result d1 and a flag d2 from the error detection circuit 24-1. Hereby, the error detection circuit 24 achieves ordinary error detection in the same fashion as the prior art error detection circuit 106 in FIG. 10.
When the changeover signal f is a value “1”, the inverter 24-2 provides an inverted output of the changeover signal f, i.e., the changeover signal of a value “0” to the AND gates 24-3, 24-4. Hereby, the AND gates 24-3, 24-4 are closed to bring a detection result d1 and a flag d2 from the error detection circuit 24 into 0. The error detection circuit 24 indicates using the flag d2 of a value “0” that the read data c from the memory circuit 4 is correct. The error detection circuit 24 further applies the detection result d1 of a value “0” that indicates no error to the error correction circuit 8. Hereby, the error detection circuit 24 is fixed to a state indicating the read data c from the memory circuit 4 is correct at all times.
Further, instead of the memory circuit 4 used in the first to sixth embodiments a memory circuit 31 illustrated in FIG. 9 may be used. The memory circuit 31 includes memory areas 31-1 to 31-(m+1) designated by addresses “0” to “m”. The number of the memory areas 31-1 to 31-(m+1) is not coincident with 2k, and falls within 2k to 2k+1. The number of the memory areas 31-1 to 31-(m+1) is one required by an external device on which the present semiconductor memory device is mounted.
The changeover circuit 5 may be changed over by designating an address “n” not possessing a memory area using the memory circuit 31.
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