Source: http://www.google.fr/patents/US5918043
Timestamp: 2013-05-19 05:58:45
Document Index: 404492532

Matched Legal Cases: ['Application No. 297630', 'Application No. 297630', 'Application No. 1', 'Application No. 1', 'Application No. 1', 'Application No. 1', 'Application No. 3', 'Application No. 3', 'Application No. 4', 'Application No. 4']

Brevet US5918043 - Method and apparatus for asynchronously stopping the clock in a processor - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Historique Web | Connexion Recherche avanc�e dans les brevets BrevetsAn apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes...http://www.google.fr/patents/US5918043?utm_source=gb-gplus-shareBrevet US5918043 - Method and apparatus for asynchronously stopping the clock in a processor Num�ro de publicationUS5918043 AType de publicationOctroi Num�ro de demande08/874,559 Date de publication29 juin 1999 Date de d�p�t13 juin 1997 Date de priorit�3 nov. 1992Autre r�f�rence de publicationUS5473767US5560001US5560002US5657483 InventeursJimmy S. ChengJames P. KardachTosaku Nakanishi Cessionnaire d'origineIntel Corporation Classification aux �tats-Unis713/601 Classification internationaleG06F11/00G06F11/267G06F1/10G06F1/26G06F1/04 Classification coop�rativeG06F1/26G06F11/2236G06F1/04G06F1/10G06F11/004H05K999/99 Classification europ�enneG06F 1/26G06F 11/00HG06F 11/22A12G06F 1/10G06F 1/04R�f�rencesCitations de brevets (90)Citations hors brevets (24) R�f�renc� par (5)Liens externesUSPTO Cession USPTO EspacenetMethod and apparatus for asynchronously stopping the clock in a processorUS 5918043 A R�sum� An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the/assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
We claim: 1. A computer system including a resonator for generating an oscillating signal and an integrated circuit (IC), said IC comprising: a phase-locked loop (PLL) circuit coupled to receive said oscillating signal, said PLL outputting an internal clock signal having a frequency which is a predetermined multiple of said oscillating signal; a central processing unit (CPU) for processing data synchronous with said internal clock signal; a microcode engine for executing a sequence of instructions, each instruction consisting of one or more microinstructions; an external signal coupled to said microcode engine causing said microcode engine to halt execution of said sequence of instructions on an instruction boundary; a logic circuit coupled to said microcode engine for masking said internal clock signal, thereby decoupling said internal clock signal from at least a portion of said CPU, in response to the assertion of said external signal, said logic circuit masking said internal clock signal after said microcode engine has halted execution of said sequence of instructions.
3. The computer system of claim 1 wherein said logic circuit includes a stop.sub.-- clock signal coupled to one input of a 2-input AND gate, the other input of said AND gate being coupled to said internal clock signal, the output of said AND gate being coupled to said portion of said CPU.
4. A computer system including: a means for generating an oscillatory signal; a means for multiplying said oscillating signal by a factor to produce a clock signal; a processing means for processing data synchronous with said clock signal; an execution means for executing a sequence of instructions, each instruction consisting of one or more microinstructions; a halting means coupled to said execution means for causing said sequence of instructions to halt execution on an instruction boundary; a logic means coupled to said execution means for masking said clock signal to decouple said clock signal from at least a portion of said processing means, said decoupling being initiated by said halting means, said logic means masking said clock signal after said execution means has halted the execution of said sequence of instructions.
5. A microprocessor having a pin for stopping the internal clock of said microprocessor on an instruction boundary comprising: a phase-locked loop circuit multiplying an oscillating signal by a factor to produce an internal clock signal; a mechanism for prioritizing a plurality of interrupt signals coupled to said microprocessor, said mechanism allowing said microprocessor to select any one of said signals on an instruction boundary; a microcode engine executing a set of instructions, each instruction consisting of a plurality of microinstructions; a logic circuit coupled to said mechanism for selectively masking said interrupt signal, the assertion of said pin causing said microcode engine to halt execution of said set of instructions on an instruction boundary and also causing said logic circuit to mask said interrupt signal after said mechanism recognizes said pin as a highest priority interrupt signal.
6. A method of stopping the clock of a microprocessor comprising the steps of: asserting an external pin to said microprocessor indicating that said clock is to be stopped; determining within the microcode engine of said microprocessor that a stop.sub.-- clock interrupt is pending; jumping to a microprogram which ensures that the central processing unit (CPU) of said microprocessor is in a known and stable state; signaling by said microcode engine to a logic circuit to assert a signal which masks said internal clock.
7. The method defined by claim 6 further comprising the step of: waiting by said microcode engine until said pin is deasserted.
8. The method according to claim 6 further comprising the steps of: de-asserting the stop clock pin; restarting the internal clock to said microprocessor; terminating by said microcode engine said microprogram so that said CPU can execute the next instruction.
9. The method according to claim 6 further comprising the steps, prior to said signaling step, of: emptying said microprocessor of active bus cycles; stopping a prefetcher within said microprocessor from prefetching.
10. The method according to claim 9 further comprising the step, after said emptying step, of generating a stop.sub.-- clock acknowledge bus cycle.
In the current embodiment, it is only the ICLK signal which is interrupted or halted in accordance with the present invention. The ICLK signal, shown being provided on line 33, clocks the vast majority of CPU operations, including program and instruction execution. As shown in FIG. 2, it is the ICLK signal that is selectively masked by AND gate 22. This masking operation is achieved by taking line 30 to a logical low potential, i.e., active low. Line 30 is labeled as STP.sub.-- MY.sub.-- CLK and is provided as an output from the STPCLK logic block 24. The STPCLK logic block 24 includes an ordinary state machine which is coupled to receive the CLK signal provided by PLL 21. In addition, STPCLK block 24 receives inputs from interrupt prioritizer 26 along line 29, from microcode engine 27, and also from the external STPCLK pin along line 28.
The present invention ensures that the processor is testable because it is always in a known state (i.e., the STPCLK microcode stops execution on an instruction boundary) whenever the ICLK signal is stopped. Furthermore, all pipelines and instruction queues are flushed by the microcode program. Microcode control also guarantees that execution is never halted in the middle of a bus cycle. This eliminates any precharging problems associated with bus cycles or pipeline stages. Because the STPCLK pin provides control of the ICLK signal at a point in the circuit beyond the phase-lock loop, this also permits an overdrive strategy, where in a new processor can be inserted where the PLL is internally multiplying the clock by some factor (e.g., 2
On the instruction boundary following the I2 instruction, the microcode engine determines that the STPCLK interrupt is pending and jumps to the STPCLK microcode program. The STPCLK microcode program then makes sure that the CPU is in a known and stable state prior to halting to the internal clock signal. This is shown occurring in FIG. 5 at decision block 51. Once the CPU is in a known state on an instruction on an instruction boundary, the STPCLK microcode program empties the bus unit of any outstanding bus cycles, generates a stop.sub.-- clock acknowledge bus cycle, and then empties the internal pipelines. This is shown occurring in FIG. 5 by blocks 52, 53 and 54. The STPCLK microcode program also stops the prefetcher from prefetching. In a preferred implementation, once all bus activity has been halted, a STPCLK acknowledge bus cycle can be run. The STPCLK ACK bus cycle is shown occurring in FIG. 4 just prior to the bus unit being deactivated.
What happens next is that the STPCLK microcode program tells the STPCLK logic block to assert the STP.sub.-- MY.sub.-- CLK signal, thereby masking the ICLK. FIG. 4 shows the STP.sub.-- MY.sub.-- CLK # signal going low just after the STPCLK ACK bus cycle is completed. At the same time, the ICLK signal is shown being deactivated. Once the STP.sub.-- MY.sub.-- CLK signal has been asserted, the ICLK signal to the CPU is halted and CPU logic operation ends. Assertion of the STP.sub.-- MY.sub.-- CLK signal is represented in the flowchart of FIG. 5 by block 55.
In one embodiment, the invention includes a microcode engine coupled to receive the signal provided by the external pin. In response, the microcode engine then executes a sequence of steps which stops the execution of the current instruction on an instruction boundary. The external pin is also coupled to a logic circuit which generates a signal that masks the CPU's clock. An interrupt mechanism is also utilized to prioritize the occurrence of the external stop.sub.-- clock signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
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