Source: http://www.google.com/patents/US6987966?dq=%235,519,867
Timestamp: 2014-09-23 06:57:08
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Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US6987966 - Adaptive radio transceiver with polyphase calibration - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including...http://www.google.com/patents/US6987966?utm_source=gb-gplus-sharePatent US6987966 - Adaptive radio transceiver with polyphase calibrationAdvanced Patent SearchPublication numberUS6987966 B1Publication typeGrantApplication numberUS 09/692,654Publication dateJan 17, 2006Filing dateOct 18, 2000Priority dateOct 21, 1999Fee statusPaidAlso published asUS6738601, US6917789, US6920311, US7116945, US7130579, US7233772, US7349673, US7356310, US7389087, US7697900, US7756472, US8023902, US8116690, US20040195917, US20050153664, US20050186925, US20070049205, US20070285154, US20080182526, US20080191313, US20080290966, US20100255792Publication number09692654, 692654, US 6987966 B1, US 6987966B1, US-B1-6987966, US6987966 B1, US6987966B1InventorsStephen Wu, Brima Ibrahim, Ahmadreza RofougaranOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (26), Non-Patent Citations (2), Referenced by (15), Classifications (63), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetAdaptive radio transceiver with polyphase calibrationUS 6987966 B1Abstract An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
CROSS-REFERENCE TO RELATED APPLICATION The present application is a continuation of co-pending patent application Ser. No. 09/634,552, filed Aug. 8, 2000, priority of which is hereby claimed under 35 U.S.C. � 120. The present application also claims priority under 35 U.S.C. � 119(e) to provisional Application Nos. 60/160,806, filed Oct. 21, 1999; Application No. 60/163,487, filed Nov. 4, 1999; Application No. 60/163,398, filed Nov. 4, 1999; Application No. 60/164,442, filed Nov. 9, 1999; Application No. 60/164,314, filed Nov. 9, 1999; Application No. 60/165,234, filed Nov. 11, 1999; Application No. 60/165,239, filed Nov. 11, 1999; Application No. 60/165,356; filed Nov. 12, 1999; Application No. 60/165,355, filed Nov. 12, 1999; Application No. 60/172,348, filed Dec. 16, 1999; Application No. 60/201,335, filed May 2, 2000; Application No. 60/201,157, filed May 2, 2000; Application No. 60/201,179, filed May 2, 2000; Application No. 60/202,997, filed May 10, 2000; Application No. 60/201,330, filed May 2, 2000. All these applications are expressly incorporated herein by referenced as though fully set forth in full.
SUMMARY OF THE INVENTION In one aspect of the present invention, a calibration circuit includes first and second digitally tunable filters, and control logic to digitally tune the first and second filters as a function of a first parameter of a first signal output from the first filter and a second parameter of a second signal output from the second filter.
For the resistor values shown in FIG. 6, the biquad stage outputs are: V OI = A ⁢ ( 1 + jRC ⁢ ⁢ ω ) ⁢ V II + 2 ⁢ QV IQ ( 1 + jRC ⁢ ⁢ ω ) 2 + 4 ⁢ Q 2 ( 1 ) and V OQ = A ⁢ - 2 ⁢ QV II + ( 1 + jRC ⁢ ⁢ ω ) ⁢ V IQ ( 1 + jRC ⁢ ⁢ ω ) 2 + 4 ⁢ Q 2 ( 2 ) FIG. 7 shows the frequency response for the complex biquad filter.
After the received signal is downconverted, the desired channel in the I path lags the one in the Q path, that is, VII=−jVIQ, and therefore: H ⁡ ( j ⁢ ⁢ ω ) = V o V I ⁢ ( j ⁢ ⁢ ω ) = A 1 + jRC ⁢ ⁢ ω - j2Q ( 3 ) This shows a passband gain of A 122 at a center frequency of 2Q/RC 124, with a 3-dB bandwidth of 2RC 126. Thus, the quality factor of the second-order stage will be Q. For the image signal however, the signal at the I branch leads, and as a result: H ⁡ ( j ⁢ ⁢ ω ) = A 1 + jRC ⁢ ⁢ ω + j2Q ( 4 ) which shows that the image located at 2Q/RC is rejected by 1 ( 1 + ( 4. ⁢ Q ) ⁢ 2 . Therefore, the biquad stage has an asymmetric frequency response, that is, the desired signal may be assigned to positive frequencies, whereas the image is attributed to negative frequencies. In general, the frequency response of the biquad stage is obtained by applying the following complex-domain transformation to a normalized real-domain lowpass filter: j ⁢ ⁢ ω - j ⁡ ( ω - ω 0 ) BW ( 5 ) where ω0 is the bandpass (BP) center frequency, and BW is the lowpass (LP) equivalent bandwidth, equal to half of the bandpass filter bandwidth. For instance, for a second-order biquad stage (as shown in FIG. 6), ω0=2Q/RC, and BW=1/RC. The biquad stage is designed by finding its LP equivalent frequency response using equation (5). Once the LP poles are known, the BP poles are calculated based on equation (5). Assume that the LP equivalent has n poles, and Pi,LP=αi+jβi is the ith pole. From equation (5), the BP pole will be:
The complex filter is realized by cascading n biquad stages. Therefore, similar to real-domain bandpass filters, an nth order complex filter uses 2�n integrators. Based on equation (3), each biquad stage has a pole equal to −1/RC+j2Q/RC. Thus: α i � BW = - 1 RC ( 7 ) and ω o + β i � BW = 2 ⁢ Q RC ( 8 ) Since the LP equivalent poles are located in the left-half plane, ai is always negative. The above equations set the value of Q and RC in each stage. The gain of each biquad stage can be adjusted based on the desired gain in the complex filter, and noise-linearity trade-off: increasing the gain of one biquad stage lowers the noise contributed by the following biquad stages, but it also degrades the linearity of the complex filter.
In addition to image rejection, the complex frequency transformation of the biquad stage (equation (5)) provides for its frequency response to be symmetric around its center frequency as shown in FIG. 7. This is in contrast to regular bandpass filters which use the following real-domain transformation: j ⁢ ⁢ ω → j ⁡ ( ω 2 - ω 0 2 ) BW � ω ( 9 ) This symmetric response in the biquad stage ensures a uniform group delay across the data band.
The described exemplary embodiment of the biquad stage can be modified to obtain a sharper rejection or notch at an undesired signal at a specific frequency. This can be achieved in the biquad stage by adding zeros. Assume that the input resistors at the biquad input (Ri 114 in FIG. 6) is replaced with an admittance Yi. For the received signal, the frequency response of the biquad stage will be equal to: H ⁡ ( j ⁢ ⁢ ω ) = R � Y i 1 + jRC ⁢ ⁢ ω - j2Q ( 10 ) FIG. 8 shows Yi having resistor Rz 128 and capacitor Cz 130.
FIG. 9 shows Yi with the capacitor Cz 132 connected to the Q input 134 and the resistor RZ connected to the I input 136. Now the current I will be equal to: I = V R z + jC z ⁢ ω � ( jV ) ( 12 ) Therefore, the input admittance will be equal to: Y i = 1 V = 1 R z - C z ⁢ ω ( 13 ) which indicates that the filter will have a zero equal to 1/RzCz at the jω axis.
FIG. 10 shows a single biquad stage modified to have a zero at the jω axis. The biquad stage includes capacitors 138, 140, 142, 144. The combination of capacitors 138, 140, 142, 148 and resistors 116, 118 determines a complex zero with respect to the center frequency. The transfer function for the received signal will be: H ⁡ ( j ⁢ ⁢ ω ) = A ⁢ 1 - RC z A ⁢ ω 1 + jRC ⁢ ⁢ ω - j2Q ( 14 ) Equation (14) is analogous to equation (3), with the difference that now a zero at A/RCz is added to the biquad stage of the complex filter. By knowing the LP equivalent characteristics of the biquad stage, the poles are calculated based on equation (6). The value of Q and RC in each biquad stage is designed by using equation (7) and equation (8). If the normalized LP zeros are at �ωz,LP, then the biquad stage should be realized with two biquad stages cascoded, and the frequency of zeros in the biquad stages will be (equation (5)):
The center frequency of the complex filter can be adjusted by setting 1/RuCu equal to a reference frequency generated, by way of example, the crystal oscillator in the controller. The filter is automatically tuned by monotonic successive approximation as described in detail in Section 4.0 herein. Once the value of RuCu is set, the complex filter characteristics depends only on four-bit code for the capacitors and the four-bit code for the resistors. For example, assume that the value of the resistors in the biquad stage of FIG. 6 is as following: Ri=nARu, Rf=nQRu, and Rc=nQRu. Likewise, assume that C=nCCu, where nC is a constant, and that 1/RuCi=ωu. The value of u is set to a reference crystal by a successive approximation feedback loop. The filter frequency response for the received signal will be: H ⁡ ( j ⁢ ⁢ ω ) = n F n A 1 + jn c ⁢ n F ⁢ R u ⁢ C u ⁢ ω - j ⁢ n F n Q ( 16 ) Therefore, the biquad stage gain (A), center frequency (ω0), and bandwidth (BW) will be equal to: A = n F n A ( 17 ) ω 0 = 1 n C ⁢ n Q � ω u ( 18 ) BW = 1 n C ⁢ n F � ω u ( 19 ) The above equations show that the characteristics of the biquad stage is independently programmed by varying nA, nF, and nQ. For instance, by setting nF, the gain of the biquad stage changes from nF/31 to nF by changing nA from 1 to 31.
Therefore, the RSSI maximum input level is S, and the ideal RSSI minimum input level is S/An where A is the gain of each differential amplifier and n is the number of the differential amplifiers. Thus, the ideal dynamic range is calculated as follows: Ideal ⁢ ⁢ Dynamic ⁢ ⁢ Range = 20 ⁢ log ⁢ S S A n = 20 ⁢ log ⁢ ⁢ A n = 20 ⁢ ( n ) ⁢ log ⁢ ⁢ A ( 22 ) However, in the case of a large amount of gain, the input level will be limited with the input noise and the dynamic range will also be limited to: Dynamic ⁢ ⁢ Range = 20 ⁢ log ⁢ S σ n ⁢ ⁢ σ n = total ⁢ ⁢ noise ⁢ ⁢ rms ⁢ ⁢ σ n = ( BW ) � Noise ⁢ ⁢ Factor ( 23 ) If each differential amplifier has the same input dynamic range VL and each full-wave rectifier has similar input dynamic range Vi, then the dynamic range of the logarithmic differential amplifier and the total RSSI circuitry are the same.
ΔRSSI=C log A 2n (30) C = Δ ⁢ ⁢ RSSI 2 ⁢ n ⁢ ⁢ log ⁢ ⁢ A ( 31 ) ( Ideal ) ⁢ RSSI = Δ ⁢ ⁢ RSSI 2 ⁢ n ⁢ ⁢ log ⁢ ⁢ A ⁢ log ⁢ ⁢ V in 2 ( 32 ) To find the relation between the gain of a differential amplifier, the gain of a rectifier, and the maximum input range of the combined differential amplifier and the rectifier, the RSSI will be calculated for the two consecutive differential amplifier and rectifier combinations (see equations (33) and (34)) for both ideal RSSI equations (32) and approximated RSSI equation (27): V in1 = S ( A ) n - m ( 33 ) V in2 = S ( A ) n - m - 1 ( 34 ) (Ideal)RSSI 2 −RSSI 1=log (A)2(35)
A clock generator can be used to generate a quadrature sinusoidal signal with controlled amplitude. The clock generator can be located in the receiver, or alternatively the LO Generator, and provides a clean sinusoidal IF from the square wave output of the divider in the LO Generator for downconverting the IF signal in the receiver path to baseband. FIG. 18 shows a block diagram and signal spectrum of a clock generator. A sinusoidal signal is generated from a square-wave using cascaded polyphase. FIG. 18 shows a clock generator block diagram. The clock generator outputs clk�I and clk�Q for the IF mixer buffer (see FIG. 17). The clock generator includes a polyphase filter at 3 fs 360, a polyphase filter at 5 fs 362, and a low pass filter 364. FIG. 19 a shows the input clock signal spectrum. FIG. 19 b shows the spectrum at 3 fs 366 and at 5 fs 368 polyphase. FIG. 19 c shows the sinusoidal signal generation after the low pass filter 364.
For N=2, the LO generator output will have a frequency of 1.5f1, and the closest spurs will be located �1f1 away from the output. These spurs can be rejected by positioning LC filters (not shown) at the output of each circuit in the LO generator. A second-order LC filter tuned to f0, with a quality factor Q, rejects a signal at a frequency of f as given in the following equation:  H ⁡ ( f )  = f Qf 0 [ 1 - ( f f 0 ) 2 ] 2 + ( f Qf 0 ) 2 ( 49 ) The following discussion changes based on the Q value. Considering a Q of about 5 for the inductor, with f0=1.5f1, the spur located at 2.5f1 is rejected by about 15 dB by each LC circuit. This spur is produced at the LO generator output due to the mixing of the VCO third harmonic (at 3 f1) with the divider output (at 0.5f1). This signal is attenuated by 10 dB since the third harmonic of a square-wave is one third of the main harmonic, 15 dB at the LC resonator at the mixers output tuned to 1.5f1, and another 15 dB at the output of the buffers (900, 902 in FIG. 33). This gives a total rejection of 40 dB. When applied to the mixers in the transmitter, this LO generator output will upconvert the baseband data to 2.5f1. With LC filters (not shown) positioned at the upconversion mixers and PA output in the transmitter, another 15+15=30 dB rejection is obtained (FIG. 33).
where ω1 is the VCO radian frequency, and ω2 is the divider radian frequency, equal to 0.5 ω1. By simplifying equation (25) and equation (26), the signals at the output of mixers will be: V out_I = - Sin ⁡ ( θ 2 ) � Sin ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 2 ) + Cos ⁡ ( θ 2 ) � Cos ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 2 ) ⁢ ⁢ and ( 52 ) V out_Q = - Sin ⁡ ( θ 2 ) � Cos ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 2 ) + Cos ⁡ ( θ 2 ) � Sin ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 2 ) ( 53 ) The above equations show that regardless of the value of θ, the outputs are always in quadrature. However, other effects should be evaluated. First, a spur at ω1−ω2=0.5 ω1 is produced at the output. This spur can be attenuated by 2�22=44 dB by the LC filters at the mixer and its buffer outputs. Thus, for 60 dB rejection, the single sideband mixers need to provide an additional 16 dB of rejection(about 0.158). Based on equation (53), tan(θ/2)=0.158, or θ�18�, phase accuracy of better than 18� can generally be achieved. Second, phase error at the VCO output lowers the mixer gain (term Cos(θ/2) in equation (52) or (53)). For a phase error of 18�, the gain reduction is, however, only 0.1 dB, which is negligible. For θ=90� (a single-phase VCO), both sidebands are equally upconverted at the mixer output. However, the LC filters reject the lower sideband by about 44 dB. The mixer gain will also be 3 dB lower. This will slightly increase the power consumption of the LO generator. If θ=180� (the VCO I and Q outputs are switched), the lower sideband is selected, and the desired sideband is completely rejected.
Similarly, the LO generator will not be sensitive to the phase imbalance of the divider outputs if the VCO is ideal. However, if there is some phase inaccuracy at both the divider and VCO outputs, the LO generator outputs will no longer be in quadrature. In fact, if the VCO output has a phase error of q, and the divider output has a phase error of q2, the LO generator outputs will be: V out_I = - Sin ⁡ ( θ 1 - θ 2 2 ) � Sin ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 1 - θ 2 2 ) + Cos ⁡ ( θ 1 + θ 2 2 ) � Cos ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 1 + θ 2 2 ) ⁢ ⁢ and ( 54 ) V out_Q = - Sin ⁡ ( θ 1 + θ 2 2 ) � Cos ⁡ ( ( ω 1 - ω 2 ) ⁢ t + θ 1 - θ 2 2 ) + Cos ⁡ ( θ 1 - θ 2 2 ) � Sin ⁡ ( ( ω 1 + ω 2 ) ⁢ t + θ 1 + θ 2 2 ) ( 55 ) This shows that the outputs still have phases of 0 and 90�, but their amplitudes are not equal. The amplitude imbalance is equal to: Δ ⁢ ⁢ A A = 2 ⁢ Cos ⁡ ( θ 1 + θ 2 2 ) - Cos ⁡ ( θ 1 - θ 2 2 ) Cos ⁡ ( θ 1 + θ 2 2 ) + Cos ⁡ ( θ 1 - θ 2 2 ) = 2 ⁢ tan ⁡ ( θ 1 2 ) � tan ⁡ ( θ 2 2 ) ( 56 ) If θ1 and θ2 are small and have an equal standard deviation, that is, the phase errors in the VCO and divider are the same in nature, then the output amplitude standard deviation will be: σ A ≈ ( σ θ ) 2 2 ( 57 ) where σA is the standard deviation of the output amplitude, and σθ is the phase standard deviation in radians. Equation (57) denotes that the phase inaccuracy in the VCO and divider has a second order effect on the LO generator. For instance, if θ1 and θ2 are on the same order and about 10�, the amplitude imbalance of the output signals will be only about 1.5%. In this case, the lower sideband will be about 15 dB rejected by the mixers, which will lead to a total attenuation of about 22+22+15=59 dB. This shows that the LO generator is robust to phase errors at the VCO or divider outputs, since typically phase errors of less than 5� can be obtained on chip.
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ClassificationH04B17/0037, H03F2203/45526, H03J2200/10, H03F3/19, H03H11/22, H03F1/56, H03H21/0012, H04B17/0027, H03F2203/45386, H03F2203/45528, H03H2011/0494, H03H7/42, H03F2200/336, H03F2203/45638, H03F3/45475, H03G3/001, H03B21/01, H03F3/45179, H03L7/18, H03H11/344, H03G11/00, H03B27/00, H03F2200/318, H03H21/0001, H03F2203/45138, H03L7/099, H03H11/1291, H03F2200/451, H03F3/245, H04B17/0012European ClassificationH04B17/00A2S, H04B17/00A3S, H03L7/18, H03F3/19, H03H11/22, H03B27/00, H03F3/24B, H03H11/34D, H03F3/45S1K, H03G11/00, H03H7/42, H03B21/01, H03G3/00D, H03L7/099, H03F3/45S1B, H04B17/00A1T, H03F1/56, H03H21/00B, H03H11/12F, H03H21/00ALegal EventsDateCodeEventDescriptionMar 14, 2013FPAYFee paymentYear of fee payment: 8Jun 11, 2009FPAYFee paymentYear of fee payment: 4Mar 12, 2001ASAssignmentOwner name: BROADCOM CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WU, STEPHEN;IBRAHIM, BRIMA;ROFOUGARAN, AHMADREZA;REEL/FRAME:011583/0672Effective date: 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