Source: http://www.google.com/patents/US6791248?dq=6,666,377
Timestamp: 2017-09-25 14:02:21
Document Index: 349402333

Matched Legal Cases: ['art 106', 'art 106', 'art 106', 'art 106', 'art 106', 'art 106', 'art 106', 'art 106', 'art 106', 'art 106', 'art 106', 'art 106', 'art 106']

Patent US6791248 - Field emission electron source - Google Patents
There is provided a field emission electron source at a low cost in which electrons can be emitted with a high stability and a high efficiency and a method of producing the same. In the field emission electron source, a strong electric field drift part 106 is formed on the n-type silicon substrate on...http://www.google.com/patents/US6791248?utm_source=gb-gplus-sharePatent US6791248 - Field emission electron source
Publication number US6791248 B2
Application number US 10/438,070
Also published as CN1182561C, CN1249525A, DE69914556D1, DE69914556T2, EP0989577A2, EP0989577A3, EP0989577B1, US6590321, US20030197457
Publication number 10438070, 438070, US 6791248 B2, US 6791248B2, US-B2-6791248, US6791248 B2, US6791248B2
Inventors Takuya Komoda, Tsutomu Ichihara, Koichi Aizawa, Nobuyoshi Koshida
Patent Citations (16), Non-Patent Citations (9), Referenced by (8), Classifications (15), Legal Events (6)
US 6791248 B2
There is provided a field emission electron source at a low cost in which electrons can be emitted with a high stability and a high efficiency and a method of producing the same. In the field emission electron source, a strong electric field drift part 106 is formed on the n-type silicon substrate on the principal surface thereof and a surface electrode 107 made of a gold thin film is formed on the strong electric field drift part 106. And the ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 101. In this field emission electron source 110, when the surface electrode 107 is disposed in the vacuum and a DC voltage is applied to the surface electrode 107 which is of a positive polarity with respect to the n-type silicon substrate 101 (ohmic electrode 2), electrons injected from the n-type silicon substrate 101 are drifted in the strong electric field drift part 106 and emitted through the surface electrode 107. The strong electric field drift part 106 comprises a drift region 161 which has a cross section in the structure of mesh at right angles to the direction of thickness of the n-type silicon substrate 1, which is an electrically conductive substrate, and a heat radiation region 162 which is filled in the voids of the mesh and has a heat conduction higher than that of the drift region 161.
1. A field emission electron source comprising:
an electrically conductive substrate having principal surfaces;
a strong electric field drift layer formed on one of the principal surfaces of said electrically conductive substrate, comprising at least a) semiconductor crystal regions formed in a manner to stand up vertically on said one of the principal surfaces of said electrically conductive substrate, and b) interspersed between said semiconductor crystal regions, semiconductor micro-crystal regions having nano-structures with a first insulating film having a thickness smaller than that of a micro-crystal of said semiconductor micro-crystal regions formed on a surface of said micro-crystal; and
a surface electrode of a thin conductive film formed on said strong electric field drift layer, wherein when a voltage is applied to make said surface electrode a positive electrode with respect to said electrically conductive substrate, electrons injected from said electrically conductive substrate are drifted in said strong electric field drift layer and are emitted through said surface electrode.
2. The field emission electron source of claim 1, wherein said strong electric field drift layer comprises at least a) drift regions for drifting electrons therethrough and b) heat radiation regions having a heat conductivity better than that of said drift regions, both regions being mixed and distributed uniformly on said one of the principal surfaces of said electrically conductive substrate.
3. The field emission electron source of claim 1, wherein said strong electric field drift layer is a layer made by alternately laminating layers whose porosities are different from each other in a direction of thickness of the electrically conductive substrate or is a layer whose porosity changes continuously in said direction of thickness.
4. The field emission electron source of claim 2, wherein said drift regions and said heat radiation regions are made of any one of a silicon or silicon carbide single-crystal, a silicon or silicon carbide poly-crystal, and an amorphous silicon or silicon carbide.
5. The field emission electron source of claim 1, wherein said semiconductor micro-crystal regions are made of a porous semiconductor material obtained by anodization.
6. The field emission electron source of claim 2, wherein said heat radiation regions are covered on the surface thereof by a second insulating film selected from an oxide film and a nitride film.
7. The field emission electron source of claim 1, wherein said first insulating film is selected from an oxide film and a nitride film.
8. The field emission electron source of claim 1, wherein the electrically conductive substrate is a substrate on a principal surface of which an electrically conductive film is formed.
9. The field emission electron source of claim 1, wherein said surface electrode comprises a thin metal film.
10. The field emission electron source of claim 1, wherein said surface electrode comprises a thin gold film.
11. The field emission electron source of claim 1, wherein said electrically conductive substrate has an ohmic electrode on a back surface thereof.
12. The field emission electron source of claim 1, wherein said electrically conductive substrate comprises an n-type silicon substrate and said strong electric field drift layer is formed from an undoped polysilicon layer.
13. The field emission electron source of claim 1, wherein no popping phenomenon occurs during electron emission.
14. A vacuum chamber, said vacuum chamber housing the field emission electron source of claim 1 and a collector electrode.
The present application is a continuation of U.S. application Ser. No. 09/404,656, filed Sep. 24, 1999, now U.S. Pat. No. 6,590,321, the disclosure of which is expressly incorporated by reference herein in its entirety.
Then, the inventors studied whole-heartedly the above drawbacks and found out that in the field emission electron source as disclosed in Japanese Patent Kokai Publication No. 8-250766, since a porous silicon layer formed by making the entire surface of the single crystal substrate on the principal surface side porous constructs a strong electric field drift layer into which electrons are injected, the strong electric field drift layer has a heat conductivity lower than that of the crystal substrate and the field emission electron source has a high thermal insulating characteristics, which results in that the temperature of the substrate rises relatively largely when voltage is applied and current is flown. Further the inventors found out that electrons are thermally excited and electrical resistivity of the single-crystal semiconductor substrate decrease when the temperature of the substrate increases, accompanied by increase of the amount of electrons emitted. Therefore, this structure is susceptible to the popping phenomenon during electron emission leading to unevenness in amount of electrons emitted.
In the present invention, said semiconductor crystal is preferably polysilicon. But other single crystal, poly-crystal and amorphous semiconductor, for example, poly-crystal semiconductor of IV group, IV—IV group compound semiconductor such as SiC, III-V group compound semiconductor such as GaAs, GaN and InP, and II-VI group semiconductor such as ZnSe may be used.
In the present invention, the semiconductor micro-crystal region is formed by making the single crystal or poly-crystal semiconductor porous by the anodization, which constructs a drift region; the details thereof are described in U.S. patent application Ser. No. 09/140,647, now U.S. Pat. No. 6,249,080, the content whereof is incorporated in this specification by reference. The insulating film preferably made of an oxide film or a nitride film.
In order to produce the field emission electron source, a part of the semiconductor region on the principal surface of the electrically conductive substrate is made porous by anodization in the direction of thickness, and then the semiconductor region and the porous semiconductor region are oxidized to form a heat radiation region and a drift region, finally a surface electrode made of a thin metal film being formed on the strong electric field drift part comprising the drift region and the heat radiation region.
Where said anodization is effected, 3) the magnetic field is applied to the electrically conductive substrate during the anodization in such a manner that the rate making the semiconductor region porous in the vertical direction to the one surface of the electrically conductive substrate is much faster than that in the other directions, with the result that the anisotropy in the rate of making the semiconductor region porous is enhanced. That is, in the region which is to be a drift region by oxidation after making porous, the anisotropy in the forming rate of the porous layer during the anodization is enhanced. Therefore, the controllability in the shape in the horizontal direction and in the direction of thickness of the drift region can be enhanced, with the result that the minute patterns of the-drift region and the heat radiation region can be formed with a good controllability in the direction of thickness.
As shown in FIG. 2, the field emission electron source according to this embodiment includes a polysilicon layer 5 oxidized by the rapid thermal oxidation technique on the principal surface of the n-type silicon substrate, aporous polysilicon layer 6 oxidized by the rapid thermal oxidation technique on the polysilicon layer 5 and a gold thin film, which is a thin metal film, formed on the porous polysilicon layer 6. And an ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1.
First the ohmic electrode 2 is formed on a back surface of the n-type silicon substrate 1, and then an undoped polysilicon layer 3 of about 1.5 μm in thickness is formed on a front surface of the n-type silicon substrate 1 opposite to the back surface, thereby to obtain a structure as shown in FIG. 3A. The polysilicon layer 3 is formed by the use of LPCVD process, using a vacuum of 20 Pa, a substrate temperature of 640 ° C., and a floating silane gas at 600 sccm.
Then, by effecting the rapid thermal oxidation (RTO) to the PPS layer 4 and the polysilicon layer 3, a structure shown in FIG. 3C is obtained. Reference numeral 5 in FIG. 3C denotes a part of the polysilicon layer processed by the rapid thermal oxidation and reference numeral 6 denotes a part of the PPS layer processed by the rapid thermal oxidation (hereinafter referred to as RTO-PPS layer 6). The rapid thermal oxidation process was conducted at an oxidation temperature of 900 ° C. for the oxidation period of one hour. In this embodiment, since the PPS layer 4 and polysilicon layer 3 are oxidized by the rapid thermal oxidation, the layers can be heated up to the oxidation temperature in several seconds, thus making it possible to suppress entrainment oxidation taking place when charging into a furnace in case the conventional oxidation apparatus of furnace tube type is used.
The field emission electron source 10 is housed in a vacuum chamber (not shown) and a collector electrode 21 (collector for emitted electrons) is disposed at a position so as to confront the thin gold film 7 as shown in FIG. 4. Inside of the vacuum chamber is evacuated to a degree of about 5×10−5 Pa. A DC voltage Vps is applied with the thin gold film 7 at a positive polarity with respect to the ohmic electrode 2 (i.e. n-type silicon substrate 1), and a DC voltage Vc is applied with the collector electrode 21 at a positive polarity with respect to the thin gold film 7. Measurements of the diode current Ips flowing between the thin gold film 7 and the ohmic electrode 2, and the electron emission current Ie flowing between the collector electrode 21 and the thin gold film 7 due to the emission of electrons e−from the field emission electron source 10 through the thin gold film 7 (alternate dash and dot line in FIG. 4 represents the emitted electron current) are shown in FIG. 5.
FIG. 6 shows Fowlev-Nordheim plot of the electron emission current Ie versus DC voltage Vps. The fact that the plots lie on a straight line indicates that the electron emission current Ie caused by the emission of electrons is due to the well-known quantum tunneling effect.
FIG. 7 is a graph showing the diode current Ips and the electron emission current Ie of the field emission electron source of this embodiment with change in time. Time is plotted along the horizontal axis and the current density is plotted along the vertical axis, while curve A shows the diode current Ips and curve shows the electron emission current Ie. Shown in FIG. 7 is the result obtained by setting the DC voltage Vps constant at 15 V and the DC voltage Vc constant at 100 V. As will be seen from FIG. 7, any popping phenomenon is not observed in both the diode current Ips and the electron emission current Ie with the field emission electron source 10 of this embodiment, so that the diode current Ips and the electron emission current Ie can be maintained substantially constant with time.
Now the dependency on the degree of vacuum of the electron emission current Ie of the field emission electron source 10 of this embodiment will be described below. FIG. 8 shows the diode current Ips and the electron emission current Ie changing as a function of the degree of vacuum of the argon atmosphere which surrounds the field emission electron source 10 of this embodiment. In FIG. 8, the degree of vacuum is plotted along the horizontal axis and the current density is plotted along the vertical axis. Curve A in the drawing represents the diode current Ips and curve B represents the electron emission current Ie. FIG. 8 shows that a substantially constant electron emission current Ie can be obtained in a range of degrees of vacuum from 10−4 Pa to about 1 Pa, indicating an insignificant dependence of the electron emission current Ie on the degree of vacuum. Thus, because of the low dependency on the degree of vacuum of the electron emission current Ie of the field emisison electron source 10 of this embodiment, stable emission of electrons of high efficiency can be maintained even when the degree of vacuum changes to some extent. Thus, because the satisfactory electron emission characteristic can be achieved even with a low degree of vacuum, it is not necessary to use the field emission electron source under a high degree of vacuum, and it is made possible to produce an apparatus which uses the field emission electron source 10 at a lower cost with handling thereof made easier.
First, in order to study the mechanism of the electron emission, when the cross section of the PPS layer 4 of the specimen shown in FIG. 3B after anodization was observed with a transmission type electron microscope (TEM), it was confirmed that the micro-crystal silicon layer having nano-structures (about 5 nm in the diameter) was grown around the columnar polysilicon. And when the cross section of the specimen shown in FIG. 3A after forming the polysilicon layer 3 was observed with a TEM, it was confirmed that the polysilicon layer 3 was composed of aggregates (columnar structure) of the fine columnar grains (crystal grain) oriented in the direction of the film growth (in the vertical direction in FIG. 3A). With comparison of these observation results with TEM, it is assumed that anodization of the polysilicon layer 3 progresses faster at the boundary of the grain, that is, anodization progresses in the direction of thickness between the columns of the columnar structure and the columnar silicon grain structure remains after anodization. This is because the rate of the formation of the porous layer (PPS layer 4) is faster than that in the case that the porous silicon layer is formed by anodizing the single-crystal silicon substrate and the space density of the micro-crystal silicon layer having nano-structures where the quantum confinement effect is developed is reduced, while the relatively large columnar grains remain. In this case, judging from the control of electric conductivity and the structural and heat stability, because the columnar grain structure remains, the porous poly-crystal silicon formed by anodizing the polysilicon layer in the columnar structure seems to have better properties than those of the porous poly-crystal silicon formed by anodizing the bulk polysilicon layer.
From the above-mentioned results of TEM observation, the porous polysilicon layer 6 (RTO-PPS layer 6) oxidized by a rapid thermal oxidation as shown in FIG. 3D, that is, the strong electric field drift layer is supposed to comprise at least, a polysilicon 61 which is columnar semiconductor crystal, a thin silicon oxide film 62 formed on the polysilicon 61, a micro-crystal silicon layer 63 which is a semiconductor micro-crystal intervened between the columnar polysilicon 61, and a silicon oxide film 64 which is formed on the surface of the micro-crystal silicon layer 63 and is an insulating film having a thickness smaller than the crystal grain size of said micro-crystal silicon layer 63, as shown in FIG. 1.
Therefore, in the field emission electron source 10 according to this embodiment, the electrons seem to be emitted in the following mechanism. When the DC voltage Vps, applied to the thin gold film 7 which is of a positive polarity with respect to the n-type silicon substrate 1, reaches a predetermined threshold value, electrons e− are injected from the n-type silicon substrate 1 into the RTO-PPS layer 6 by thermal excitation. At this time, since most of electric field applied to the RTO-PPS layer 6 is applied across the silicon oxide layer 64, the injected electrons e− are accelerated by the strong electric field applied across the silicon oxide layer 64 and are drifted through the space between the polysilicon 61 in the RTO-PPS layer 6 toward the surface in the direction of the arrow A in FIG. 1 (upward in FIG. 1). In this case, the drift length of the electrons in the RTO-PPS layer is very long as compared with the grain size of the micro-crystal silicon layer 63 as described below, the electrons reach the surface of the RTO-PPS layer 6 with almost no collision. The electrons e− which have reached the surface of the RTO-PPS layer 6 are hot electrons having a kinetic energy much higher by several kT or much more than that in the state of thermal equilibrium and easily penetrate the thin gold film 7 through the oxide layer at the top surface of the RTO-PPS layer 6 due to tunneling, thereby to be emitted to into the vacuum.
In the field emission electron source 10 of this embodiment, as described above with reference to FIG. 7, the electrons can be emitted without the occurrence of the popping noise and with a high efficiency and a high stability. This is because it is supposed that the surface of each grain in the RTO-PPS layer is made porous but the core of each grain (polysilicon 61 in FIG. 1) retains a crystal state and it is also supposed that heat generated by applying voltage transmits along the crystal (polysilicon 61 in FIG. 1) and radiates to the outside, therefore temperature rise of RTO-PPS layer being suppressed.
While the n-type silicon substrate 1 ((100) substrate having a resistivity of about 0.1 Ωcm) is used for the electrically conductive substrate in this embodiment, the electrically conductive substrate is not limited to the n-type silicon substrate and, for example, a metal substrate such as a chromium substrate, or a glass substrate with a conductive thin film such as an electrically conductive transparent thin film of, for example, indium tinoxide (ITO), platinum or chromium conductive film formed thereon may be used, in which case it is made possible to achieve larger emission area and lower production cost than in the case of using a semiconductor substrate such as n-type silicon substrate.
Where the conductive substrate is a semiconductor substrate, the polysilicon layer 3 may be formed on the conductive substrate by the use of LPCVD (Low Pressure Chemical Vapor Deposition) process, sputtering process or so on. Also the polysilicon layer may be formed by annealing an amorphous silicon layer formed on a conductive substrate by plasma-CVD process and crystalizing said layer. Where the conductive substrate is the combination of the glass substrate and the conductive thin film, the polysilicon layer 3 may be formed on the conductive thin film by annealing with an excimer laser to an amorphous silicon layer formed on the conductive thin film by CVD process. It is not limited to CVD process, the polysilicon layer 3 may be formed by CGS (Continuous Grain Silicon) process, catalytic CVD process, or so on. Where the polysilicon layer 3 is deposited on the substrate by CVD process or so on, the polysilicon layer to be deposited is influenced extremely by the orientation of the substrate. Therefore, where the polysilicon lyaer 3 is deposited on the substrate other than the (100) single-crystal silicon substrate, such deposition conditions may be set that the polysilicon grows in the perpendicular direction to the principal surface
The strong electric field drift part 106 according to the present embodiment comprises a drift region 161 of which the cross section at the right angles to the direction of thickness of the n-type silicon substrate 101, an electrically conductive substrate, is in the structure of mesh and in which the electrons are drifted, and a heat radiation region 162 which is filled in the crystals like openings of the mesh-like drift region and which has a heat conductivity higher than that of the drift region 161. That is, the heat radiation region 162 is formed in the pillared structure in the parallel direction to the direction of thickness of the n-type silicon substrate 101. In this case, the drift region 161 is made of oxidized porous silicon and the heat radiation region 162 is made of oxidized single-crystal silicon.
First the ohmic electrode 102 is formed on a back surface of the n-type silicon substrate 101, and then photoresist is applied to the principal surface of the n-type silicon substrate 101. Said photoresist is patterned with a photomask A shown in FIG. 13 to form a resist mask 103, resulting in the structure as shown in FIG. 12A. The photomask M is constructed in such a structure that the plane shape of the resist mask 103 is a generally minute square (for example, in the order of 0.1 μm). The photomask M may be constructed in such a structure that the plane shape of the resist mask 103 is a minute polygon, minute circle, minute star and the like other than a square.
Then the n-type silicon substrate 101 on the principal surface side thereof is subjected to anodization with a constant current while being irradiated with light. During this anodization, a liquid electrolyte made by mixing a 55 wt % aqueous solution of hydrogen fluoride and ethanol in a proportion of about 1:1 is used and a platinum electrode (not shown) is used as a negative electrode and the n-type silicon substrate 101 (ohmic electrode 102) is used as a positive electrode. By this anodization, the region which is not covered with resist mask 103 on the principal surface side of the n-type silicon substrate 101 is made porous and a porous layer 111 made of porous silicon is formed, resulting in the structure as shown in FIG. 11B. In FIG. 11B, reference numeral 112 designates a semiconductor layer composed of a part of the n-type silicon substrate 101. The semiconductor layer 112 is in the structure of a square pole. In this embodiment, the anodization process was conducted under conditions of a constant current density of 10 mA/cm2 and duration of anodization being 30 seconds, while irradiating the principal surface of the n-type silicon substrate 101 with light by means of a 500W tungsten lamp during the process of anodization. These conditions are proposed as an example and are not limited thereto. In this embodiment, the region on the principal surface side of the n-type silicon substrate 101 also serves as a semiconductor region.
Then, by effecting the rapid thermal oxidation (RTO) to the porous layer 111 and the semiconductor layer 112, a strong electric field drift part 106 is formed. Thereafter, the surface electrode 107 made of a gold thin film is formed by, for example, deposition on the strong electric field drift part 106, resulting in the structure as shown in FIG. 11C. In FIG. 11C, reference numeral 161 designates aporous layer 111 oxidized by rapid thermal oxidation corresponding to the above-mentioned drift region 161 and reference numeral 162 designates a semiconductor layer 112 oxidized by rapid thermal oxidation corresponding to the above-mentioned heat radiation region 162. That is, the strong electric field drift part 106 is composed of the drift region 161 and the heat radiation region 162 in FIG. 11C. The rapid thermal oxidation process was conducted at an oxidation temperature of 900° C. for the oxidation period of one hour. While the thickness of the surface electrode 107 is about 10 nm in this embodiment, the thickness is not limited to a particular value. While the metal thin film (for example, thin gold film) serving as the surface electrode 107 is formed by evaporation in this embodiment, the method of forming the thin metal film is not limited to evaporation and the thin metal film may be formed by sputtering. The field emission electron source 110 forms a diode with the surface electrode 107 serving as a positive electrode (anode) and the ohmic electrode 102 serving as a negative electrode (cathode). The current which flows when a DC voltage is applied between the positive electrode and the negative electrode is diode current.
Therefore, in the field emission electron source 110 according to this embodiment, the electrons seem to be emitted in the following mechanism. When the DC voltage applied to the surface electrode 107 which is of a positive polarity with respect to the n-type silicon substrate 101 (ohmic electrode 2) reaches a predetermined threshold value, electrons are injected from the n-type silicon substrate 101 into the strong electric drift part 106 by thermal excitation. On the other hand, there are a large number of micro-crystal silicon layers having nano-structures where the quantum confinement effect occurs in the drift region 161 of the strong electric field drift part 106, and on the surface of the micro-crystal silicon layer, the silicon oxide film having a thickness smaller than that the crystal grain size of the micro-crystal silicon layer is formed. At this time, since most of electric field applied to the strong electric field drift part 106 is applied across the silicon oxide layer formed on the surface of the micro-crystal silicon layer, the injected electrons are accelerated by the strong electric field applied across the silicon oxide film and are drifted in the drift region 161 toward the surface. In this case, the drift length of the electrons is very long as compared with the grain size of the micro-crystal silicon layer, the electrons reach the surface of the drift region 161 with almost no collision. The electrons which have reached the surface of the drift region 161 are hot electrons having a much higher kinetic energy several kT or much more higher than that in the state of thermal equilibrium and easily penetrate the surface electrode 107 through the oxide layer at the top surface of the drift part 106 due to tunneling, thereby to be emitted to into the vacuum.
In this embodiment, as described above, a part of the n-type silicon substrate 101 on the principal surface side thereof serves as a semiconductor region and this semiconductor region is anodized. However, any one of single-crystal silicon, poly-crystal silicon, amorphous silicon, single-crystal silicon carbide (SiC), poly-crystal silicon carbide or amorphous silicon carbide or so on may be laminated as a semiconductor region on the n-type silicon substrate and then anodization may be effected. Also, the electrically conductive substrate is not limited to the n-type silicon substrate and, for example, a metal substrate such as a chromium substrate, or a glass substrate with a conductive thin film such as an electrically conductive transparent thin film of, for example, indium tin oxide (ITO), platinum or chromium conductive film formed thereon may be used, in which case it is made possible to achieve larger emission area and lower production cost than in the case of using a semiconductor substrate such as n-type silicon substrate. Where the conductive substrate is a semiconductor substrate, the polysilicon layer may be formed on the conductive substrate by the use of LPCVD process, sputtering process or so on. Also the polysilicon layer may be formed by annealing an amorphous silicon layer formed on a conductive substrate by plasma-CVD process and crystalizing said layer. Where the conductive substrate is the combination of the glass substrate and the conductive thin film, the polysilicon layer may be formed on the conductive thin film by annealing with an excimer laser to an amorphous silicon layer formed on the conductive thin film by CVD process. It is not limited to CVD process, the polysilicon layer may be formed by CGS (Continuous Grain Silicon) process, catalytic CVD process, or so on. Where the polysilicon layer is deposited on the substrate by CVD process or so on, the polysilicon layer to be deposited is influenced extremely by the orientation of the substrate. Therefore, where the polysilicon layer is deposited on the substrate other than the (100) single-crystal silicon substrate, such deposition conditions may be set that the polysilicon grows in the perpendicular direction to the principal surface of the substrate.
The process of producing the field emission electron source of this embodiment is almost the same as that in the second embodiment and only the conditions of anodization are different. That is, in this embodiment, anodization under the first condition with current density being small and anodization under the second condition with current density being large are repeated alternately. At the time when anodization under the frist condition is completed one time, a porous layer having a low porosity is formed on the surface of the n-type silicon substrate. Then at the time when anodization under the second condition is completed, a porous layer having a high porosity is formed on one side of said porous layer having a low porosity adjacent the n-type silicon substrate 101.
Thus, since the field emission electron source 110 of this embodiment comprises a drift region 161 whose porosity changes continuously as described above, the overflow of the diode current can be suppressed more effectively and the efficiency of the electron emission can be enhanced, compared with the field emission electron source of the second embodiment.
US5360759 Sep 17, 1993 Nov 1, 1994 Siemens Aktiengesellschaft Method for manufacturing a component with porous silicon
US6285118 Nov 15, 1999 Sep 4, 2001 Matsushita Electric Works, Ltd. Field emission-type electron source and manufacturing method thereof and display using the electron source
US6498426 Apr 21, 2000 Dec 24, 2002 Matsushita Electric Works, Ltd. Field emission-type electron source and manufacturing method thereof
EP0874384A1 Mar 23, 1998 Oct 28, 1998 Pioneer Electronic Corporation Electron emission device and display device using the same
EP0913849A2 Aug 26, 1998 May 6, 1999 Matsushita Electric Works, Ltd. Field emission electron source, method of producing the same, and use of the same
JPH08250766A Title not available
JPH09259795A Title not available
JPH10269932A Title not available
1 C.A. Spindt et al., "Field Emitter Arrays for Vacuum Microelectronics" IEEE Transactions on Electron Devices, vol. 38, No. 10, Oct. 1991, pp. 2355-2363.
2 English Language Abstract of JP 10-269932. Oct. 9, 1998.
3 English Language Abstract of JP 8-250766. Sep. 27, 1996.
4 English Language Abstract of JP 9-259795. Oct. 3, 1997.
5 H.B. Michaelson, "The work function of the elements and it's periodicity", J. Appl. Phys., vol. 48, No. 11, Nov. 1977, pp. 4729-4733.
6 R.Sedlacik et al., "Photoconductivity study of self-supporting porous silicon", Thin Solid Films 255, pp. 269-271 (1995).
7 T.Komoda et al., "Mechanism of efficient and stable surface-emitting cold cathode based on porous polycrystalline silicon films", Journal of Vacuum Science & Technology B, vol. 17, No. 3, pp. 1076 et seq. (May 1999).
8 T.Oguro et al., "Mechanism of the visible electroluminescence from metal/porous silicon/n-Si devices", J. Appl. Phys. 81(3), pp. 1407-1412, Feb. 1, 1997.
9 Xia Sheng et al., "Surface Emitting Cold Cathode Based on Porous Silicon", Technical Report of IEICE, ED96-141, pp. 41-46 (Dec. 1996).
US7667233 * Nov 20, 2006 Feb 23, 2010 Samsung Sdi Co., Ltd. Display device, flat lamp and method of fabricating the display device and flat lamp
US7825591 * Feb 13, 2007 Nov 2, 2010 Panasonic Corporation Mesh structure and field-emission electron source apparatus using the same
US8653519 Mar 31, 2011 Feb 18, 2014 Panasonic Corporation Electronic device and method for manufacturing same
US20070114931 * Nov 21, 2006 May 24, 2007 Seung-Hyun Son Flat panel display device
US20070117251 * Nov 20, 2006 May 24, 2007 Samsung Sdi Co.,Ltd. Display device, flat lamp and method of fabricating the display device and flat lamp
US20070188090 * Feb 13, 2007 Aug 16, 2007 Matsushita Toshiba Picture Display Co., Ltd. Field-emission electron source apparatus
US20070188091 * Feb 13, 2007 Aug 16, 2007 Matsushita Toshiba Picture Display Co., Ltd. Mesh structure and field-emission electron source apparatus using the same
US20110163686 * Jul 8, 2009 Jul 7, 2011 Tsutomu Ichihara Lighting device
U.S. Classification 313/310, 313/496, 977/939
International Classification H01L33/00, H01J1/30, H01J1/312, H01J9/02
Cooperative Classification Y10S977/939, H01J9/025, B82Y10/00, H01J1/312, H01J2201/3125
European Classification B82Y10/00, H01J1/312, H01J9/02B2