Source: https://patents.google.com/patent/US9645820B2/en
Timestamp: 2019-11-13 05:28:18
Document Index: 312860381

Matched Legal Cases: ['Application No. 20157031234', 'Application No. 14817656', 'Application No. 103121591', 'Application No. 103121591', 'Application No. 103121591', 'Application No. 103121591']

US9645820B2 - Apparatus and method to reserve and permute bits in a mask register - Google Patents
Apparatus and method to reserve and permute bits in a mask register Download PDF
US9645820B2
US9645820B2 US13/929,563 US201313929563A US9645820B2 US 9645820 B2 US9645820 B2 US 9645820B2 US 201313929563 A US201313929563 A US 201313929563A US 9645820 B2 US9645820 B2 US 9645820B2
US13/929,563
US20150006847A1 (en
2013-06-27 Priority to US13/929,563 priority Critical patent/US9645820B2/en
2014-07-15 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: VALENTINE, ROBERT, OULD-AHMED-VALL, Elmoustapha
2015-01-01 Publication of US20150006847A1 publication Critical patent/US20150006847A1/en
2017-05-09 Publication of US9645820B2 publication Critical patent/US9645820B2/en
239000011162 core materials Substances 0 description 66
An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.
Embodiments of the invention relate generally to the field of computer systems. More particularly, the embodiments of the invention relate to an apparatus and method for reversing and permuting bits in a mask register.
An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction generally refers herein to macro-instructions—that is instructions that are provided to the processor for execution—as opposed to micro-instructions or micro-ops—that is the result of a processor's decoder decoding macro-instructions.
The instruction set architecture is distinguished from the microarchitecture, which is the set of processor design techniques used to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, Intel® Pentium 4 processors, Intel® Core™ processors, and processors from Advanced Micro Devices, Inc. of Sunnyvale Calif. implement nearly identical versions of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. For example, the same register architecture of the ISA may be implemented in different ways in different microarchitectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a Register Alias Table (RAT), a Reorder Buffer (ROB) and a retirement register file as described in U.S. Pat. No. 5,446,912; the use of multiple maps and a pool of registers as described in U.S. Pat. No. 5,207,132), etc. Unless otherwise specified, the phrases register architecture, register file, and register are used herein to refer to that which is visible to the software/programmer and the manner in which instructions specify registers. Where a distinction is required, the adjective logical, architectural, or software visible will be used to indicate registers/files in the register architecture, while different adjectives will be used to designation registers in a given microarchitecture (e.g., physical register, reorder buffer, retirement register, register pool).
Scientific, financial, auto-vectorized general purpose, RMS (recognition, mining, and synthesis), and visual and multimedia applications (e.g., 2D/3D graphics, image processing, video compression/decompression, voice recognition algorithms and audio manipulation) often require the same operation to be performed on a large number of data items (referred to as “data parallelism”). Single Instruction Multiple Data (SIMD) refers to a type of instruction that causes a processor to perform an operation on multiple data items. SIMD technology is especially suited to processors that can logically divide the bits in a register into a number of fixed-sized data elements, each of which represents a separate value. For example, the bits in a 64-bit register may be specified as a source operand to be operated on as four separate 16-bit data elements, each of which represents a separate 16-bit value. This type of data is referred to as packed data type or vector data type, and operands of this data type are referred to as packed data operands or vector operands. In other words, a packed data item or vector refers to a sequence of packed data elements; and a packed data operand or a vector operand is a source or destination operand of a SIMD instruction (also known as a packed data instruction or a vector instruction).
By way of example, one type of SIMD instruction specifies a single vector operation to be performed on two source vector operands in a vertical fashion to generate a destination vector operand (also referred to as a result vector operand) of the same size, with the same number of data elements, and in the same data element order. The data elements in the source vector operands are referred to as source data elements, while the data elements in the destination vector operand are referred to a destination or result data elements. These source vector operands are of the same size and contain data elements of the same width, and thus they contain the same number of data elements. The source data elements in the same bit positions in the two source vector operands form pairs of data elements (also referred to as corresponding data elements). The operation specified by that SIMD instruction is performed separately on each of these pairs of source data elements to generate a matching number of result data elements, and thus each pair of source data elements has a corresponding result data element. Since the operation is vertical and since the result vector operand is the same size, has the same number of data elements, and the result data elements are stored in the same data element order as the source vector operands, the result data elements are in the same bit positions of the result vector operand as their corresponding pair of source data elements in the source vector operands. In addition to this exemplary type of SIMD instruction, there are a variety of other types of SIMD instructions (e.g., that has only one or has more than two source vector operands; that operate in a horizontal fashion; that generates a result vector operand that is of a different size, that has a different size data elements, and/or that has a different data element order). It should be understood that the term destination vector operand (or destination operand) is defined as the direct result of performing the operation specified by an instruction, including the storage of that destination operand at a location (be it a register or at a memory address specified by that instruction) so that it may be accessed as a source operand by another instruction (by specification of that same location by the another instruction).
The SIMD technology, such as that employed by the Intel® Core™ processors having an instruction set including x86, MMX™, Streaming SIMD Extensions (SSE), SSE2, SSE3, SSE4.1, and SSE4.2 instructions, has enabled a significant improvement in application performance (Core™ and MMX™ are registered trademarks or trademarks of Intel Corporation of Santa Clara, Calif.). An additional set of future SIMD extensions, referred to the Advanced Vector Extensions (AVX) and using the VEX coding scheme, has been published.
FIG. 8 illustrates an apparatus for performing a mask bit reversal operation according to one embodiment of the invention;
FIG. 9 illustrates an apparatus for performing a mask bit permute operation according to another embodiment of the invention;
FIG. 10 illustrates a processor architecture including packet data register and packed data operation mask registers;
FIG. 11 illustrates a method for performing a mask bit reversal operation according to one embodiment of the invention;
FIG. 12 illustrates a method for performing a mask bit permute operation according to another embodiment of the invention.
Embodiments to Reverse and Permute Bits in a Mask Register
Mask registers as used herein effectively contain bits which correspond to elements in a vector register and track the elements upon which operations should be performed. For this reason it is needed to have common operations which can replicate similar behavior on these mask bits as for the vector registers and in general allow one to adjust these mask bits within the mask register.
One embodiment of the invention includes instructions that reverse the bits inside a mask register by replacing the bit at position n with the bit at the symmetric position depending on the mask size. Because each mask bit corresponds to a single vector element, the number of active bits in a mask register depends on both the size of the vector register (in bits) and the size of the elements. So different forms for different data types may be employed including, by way of example and not limitation, Byte (8-bit), Word (16-bit), Doubleword (32-bit), and Quadword (64-bit) sizes. One mask register may be used as a source and the results written to a second mask register.
Below is a pseudo code for a possible implementation of the proposed instruction for the doubleword form. Of course, this instruction can be implemented for other data types (byte, word and quadword).
KREVERSEBITSD kI, k2 FOR j ← 0 TO 31 DEST[j] ← SRC2[31−j]; j++; ENDFOR DEST[MAX_KL−1:32] ← 0
In the final line, DEST[MAX_KL-1:32]←0, means that bits are zeroed out if needed. For example, if the mask destination register is greater than 32 bits (e.g., 64 bits), then any bits over the first 32 are zeroed out.
FIG. 8 illustrates architectural components employed in one embodiment including bit reverse logic 805 for executing the mask reverse bits instruction. In response, the bit values from the mask in SRC2 802 are transferred into symmetric positions within the destination 804 as illustrated. For example, the bit reverse logic 805 transfers the bit at position 0 in the source 802 to bit position 31 in the destination 804; the bit at position 1 in the source 802 to bit position 30 in the destination 804, etc, until all bits have been transferred from the source to the destination, resulting in a symmetric, “mirror image” of the original bit arrangement. The resulting mask stored in the destination 804 may then be used for subsequent vector operations.
Another embodiment of the invention includes instructions which permute values from a first mask operand (destination) and a third operand (second source) and inserts them in the destination operand at the locations pointed by the indices in a second operand (first source). Note that these instructions permit one bit value from the source to be copied to more than one location in the destination operand. Because each mask bit corresponds to a single vector element, the number of active bits in a mask register depends on both the size of the vector register (in bits) and the size of the elements. So this permute operation has forms for different data types Byte (8-bit), Word (16-bit), Doubleword (32-bit), and Quadword (64-bit) sizes.
One embodiment of the instruction takes two sources: a mask register to be permuted and a vector register that contains the permute control. The result is written to a second mask register.
KPERMD k1, zmm1, k2 FOR j ← 0 TO 31 i ← j * 16 id ← SRC1[i+5:i] DEST[j] ← SRC2[id]; j++; ENDFOR DEST[MAX_KL−1:32] ← 0
In this embodiment, on each iteration, 6 bits in SCR1 are used as an index to identify a bit position in SRC2. This bit is then transferred to the destination mask register, DEST, at position j. Once again, in the final line, DEST[MAX_KL-1:32]←0, means that bits are zeroed out if needed. For example, if the mask destination register is greater than 32 bits (e.g., 64 bits), then any bits over the first 32 are zeroed out.
FIG. 9 illustrates architectural components employed in one embodiment including permute logic 905 for executing the mask permute instruction. In response to the indices read from the mask permute control register 901 (SRC1 in the example), bits from specified bit positions B0-B31 in the SRC2 register 902 are permuted to different bit positions P0-P31 in the destination register DST 904 (identified by the variable j). Using different indices in the permute control register, any bit from SRC2 902 may be copied to any bit position in DST 904.
FIG. 10 is a block diagram of an exemplary embodiment of a processor (processor core) 1000 to execute one or more mask bit reverse instructions 1004A (e.g., KREVERSEBITSD) and/or mask permute instructions 1004B (e.g., KPEMD). In some embodiments, the processor may be a general-purpose processor (e.g., of the type used in desktop, laptop, servers, and like computers). Alternatively, the processor may be a special-purpose processor. Examples of suitable special-purpose processors include, but are not limited to, network processors, communications processors, cryptographic processors, graphics processors, co-processors, embedded processors, digital signal processors (DSPs), and controllers, to name just a few examples. The processor may be any of various complex instruction set computing (CISC) processors, various reduced instruction set computing (RISC) processors, various very long instruction word (VLIW) processors, various hybrids thereof, or other types of processors entirely.
The processor 1000 includes architecturally-visible registers (e.g., an architectural register file) 1005. The architectural registers may also be referred to herein simply as registers. Unless otherwise specified or apparent, the phrases architectural register, register file, and register are used herein to refer to registers that are visible to the software and/or programmer and/or the registers that are specified by macroinstructions or assembly language instructions to identify operands. These registers are contrasted to other non-architectural or non-architecturally visible registers in a given microarchitecture (e.g., temporary registers used by instructions, reorder buffers, retirement registers, etc.). The registers generally represent on-die processor storage locations.
The illustrated architectural registers may include packed data registers 1006 operable to store packed or vector data. The illustrated architectural registers may also include packed data operation mask registers 1007. Each of the packed data operation mask registers may be operable to store a packed data operation mask. These registers may be referred to as writemask registers in this description. Packed data operands may be stored in the packed data registers 1007.
The processor also includes execution logic 1008 operable to execute or process the one or more of the mask bit reverse instructions 1004A and/or mask permute instructions 1004B. In some embodiments, the execution logic may include particular logic (e.g., particular circuitry or hardware potentially combined with firmware) to execute these instructions.
FIG. 11 illustrates an embodiment of the execution of a KREVERSEBITS instruction in a processor. A KREVESEBITS instruction with a first source register operand and a destination register operand, and an opcode is fetched at 1101.
The KREVESEBITS instruction is decoded by decoding logic at 1102.
The source operand values are retrieved/read at 1103. For example, the source registers are read.
The decoded KREVESEBITS instruction (or operations comprising such an instruction such as microoperations) is executed by execution resources such as one or more functional units at 1104 to replace each bits at position n with a bit at a symmetric position in the source mask register. The newly determined mask values are stored into the destination register operand at 1105. In some embodiments, the calculated values are stored in data elements of a packed data register. While 1104 and 1105 have been illustrated separately, in some embodiments they are performed together as a part of the execution of the instruction.
FIG. 12 illustrates an embodiment of the execution of a KPERM instruction in a processor. A KPERM instruction with a first source register operand and a destination register operand, and an opcode is fetched at 1201.
The KPERM instruction is decoded by decoding logic at 1202.
The source operand values are retrieved/read at 1203. For example, the control bits are read from one source register to determine how to permute the bits (e.g., SRC1 901 in FIG. 9) and the bits to be permuted are read from the other source register (e.g., SCR2 902).
The decoded KPERM instruction (or operations comprising such an instruction such as microoperations) is executed by execution resources such as one or more functional units at 1204 to permute bits from a source mask register (SRC2) into a destination mask register (DEST). The newly determined mask values are stored into the destination register operand at 1205. In some embodiments, the calculated values are stored in data elements of a packed data register. While 1204 and 1205 have been illustrated separately, in some embodiments they are performed together as a part of the execution of the instruction.
1. A processor to execute an instruction to perform the operations of:
reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and
performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.
2. The processor as in claim 1 wherein the source and destination mask registers store 32 bits of mask data.
3. The processor as in claim 1 wherein the source and destination mask registers store 64 bits of mask data.
4. The processor as in claim 1 wherein the instruction comprises a macroinstruction and wherein the operations comprise microoperations.
5. A processor to execute an instruction to perform the operations of:
reading a plurality of mask bits stored in a first source register and control data stored in a second source register, the mask bits associated with vector data elements of a vector register; and
performing a mask bit permute operation to copy each mask bit from the source mask register to a destination mask register, wherein the control data stored in the second source register causes a specified bit from the first source register to be copied to each bit in the destination register resulting in a permutation of the original mask bit arrangement.
6. The processor as in claim 5 wherein the source and destination mask registers store 32 bits of mask data.
7. The processor as in claim 5 wherein the source and destination mask registers store 64 bits of mask data.
8. The processor as in claim 5 wherein the instruction comprises a macroinstruction and wherein the operations comprise microoperations.
10. The method as in claim 9 wherein the source and destination mask registers store 32 bits of mask data.
11. The method as in claim 9 wherein the source and destination mask registers store 64 bits of mask data.
12. The method as in claim 9 wherein the instruction comprises a macroinstruction and wherein the operations comprise microoperations.
14. The method as in claim 13 wherein the source and destination mask registers store 32 bits of mask data.
15. The method as in claim 13 wherein the source and destination mask registers store 64 bits of mask data.
16. The method as in claim 13 wherein the instruction comprises a macroinstruction and wherein the operations comprise microoperations.
an input/output (IO) communication interface for communicating with one or more peripheral devices;
a network communication interface for communicatively coupling the system to a network; and
a processor to execute an instruction to perform the operations of:
18. The system as in claim 17 wherein the source and destination mask registers store 32 bits of mask data.
19. The system as in claim 17 wherein the source and destination mask registers store 64 bits of mask data.
20. The system as in claim 17 wherein the instruction comprises a macroinstruction and wherein the operations comprise microoperations.
21. The system as in claim 20 further comprising:
a display adapter to render graphics images in response to execution of the program code by the processor.
22. The system as in claim 21 further comprising:
a user input interface to receive control signals from a user input device, the processor executing the program code in response to the control signals.
US13/929,563 2013-06-27 2013-06-27 Apparatus and method to reserve and permute bits in a mask register Active 2035-01-07 US9645820B2 (en)
US13/929,563 US9645820B2 (en) 2013-06-27 2013-06-27 Apparatus and method to reserve and permute bits in a mask register
PCT/US2014/042789 WO2014209685A1 (en) 2013-06-27 2014-06-17 Apparatus and method to reverse and permute bits in a mask register
KR1020157031234A KR101713841B1 (en) 2013-06-27 2014-06-17 Apparatus and method to reverse and permute bits in a mask register
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US15/785,016 US10387148B2 (en) 2013-06-27 2017-10-16 Apparatus and method to reverse and permute bits in a mask register
US15/487,080 Continuation US10209988B2 (en) 2013-06-27 2017-04-13 Apparatus and method to reverse and permute bits in a mask register
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US9645820B2 true US9645820B2 (en) 2017-05-09
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US13/929,563 Active 2035-01-07 US9645820B2 (en) 2013-06-27 2013-06-27 Apparatus and method to reserve and permute bits in a mask register
US15/487,080 Active US10209988B2 (en) 2013-06-27 2017-04-13 Apparatus and method to reverse and permute bits in a mask register
US15/785,030 Active US10387149B2 (en) 2013-06-27 2017-10-16 Apparatus and method to reverse and permute bits in a mask register
US15/785,016 Active US10387148B2 (en) 2013-06-27 2017-10-16 Apparatus and method to reverse and permute bits in a mask register
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OULD-AHMED-VALL, ELMOUSTAPHA;VALENTINE, ROBERT;SIGNING DATES FROM 20130805 TO 20130811;REEL/FRAME:033329/0839