Source: https://patents.justia.com/patent/9176913
Timestamp: 2020-07-15 19:17:21
Document Index: 460033378

Matched Legal Cases: ['Application No. 200680037568', 'Application No. 12183475', 'Application No. 12183475', 'Application No. 10', 'Application No. 101132820', 'Application No. 201210331633']

US Patent for Coherence switch for I/O traffic Patent (Patent # 9,176,913 issued November 3, 2015) - Justia Patents Search
Justia Patents SnoopingUS Patent for Coherence switch for I/O traffic Patent (Patent # 9,176,913)
Sep 7, 2011 - Apple
Enabling network slicing in a 5G network with CP/UP separation
Methods and devices for managing packet data network connections
“Comprising.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or steps. Consider a claim that recites: “A processor comprising a cache . . . . ” Such a claim does not foreclose the processor from including additional components (e.g., a network interface, a crossbar).
“First,” “Second,” etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical) unless explicitly defined as such. For example, in a memory controller having five ports, the terms “first” and “second” ports can be used to refer to any two of the five ports.
Components shown within IC 10 may be coupled to each other using any suitable bus and/or interface mechanism. In some embodiments, these components may be connected using the Advanced Microcontroller Bus Architecture (AMBA®) protocol (from ARM® Holdings) or any other suitable on-chip interconnect specification for the connection and management of logic blocks. Examples of AMBA buses and/or interfaces may include Advanced eXtensible Interface (AXI), Advanced High-performance Bus (AHB), Advanced System Bus (ASB), Advanced Peripheral Bus (APB), and Advanced Trace Bus (ATB).
Coherence switch 12 may receive transactions from the I/O devices 16-20 and may convey the transactions to processor complex 22 or NRT block 26. In some embodiments, in response to receiving transactions, coherence switch 12 may issue corresponding memory requests to processor complex 22 or NRT block 26. Generally speaking, a transaction may comprise a memory request, and the term “memory request” is not limited to requests that are ultimately responded to by memory, but can also include requests that are satisfied by a cache. It is noted that the terms “memory request”, “transaction”, and “memory operation” may be used interchangeably throughout this disclosure.
The coherence switch 12 may determine if a transaction received from an I/O device (via multiplexer 14) is a cache-coherent or non-cache-coherent transaction using a variety of methods. Throughout this disclosure, a cache-coherent transaction may be referred to as a “coherent transaction” or “coherent memory request”, and a non-cache-coherent transaction may be referred to as a “non-coherent transaction” or “non-coherent memory request”. Generally speaking, a non-coherent transaction may correspond to a memory operation that is not checked against a cache. In one embodiment, the coherence switch 12 may determine if a transaction is coherent or non-coherent based on the I/O device from which the transaction is received. A first portion of I/O devices 16-20 may be designated as coherent devices, and a second portion of I/O devices 16-20 may be designated as non-coherent devices. In another embodiment, the coherence switch 12 may determine if a transaction is coherent or non-coherent based on a transaction identifier. Each I/O device may be assigned a range of transaction identifiers, and the identifiers may be designated for use as coherent or non-coherent transactions.
Turning now to FIG. 2, a block diagram of one embodiment of the operation of coherence switch 12 is shown. In one embodiment, multiplexer 14 may couple traffic to coherence switch 12. As shown in FIG. 2, coherent transactions are indicated by a capital “C”, with a subscript identifying different coherent transactions. For example, C1 may be the first coherent request received by coherence switch 12, C2 may be received subsequent to C1, and so on. Non-coherent transactions are indicated by a capital “NC”, with a subscript identifying different non-coherent requests. In some embodiments, the transactions may be broken up into packets, and the blocks in FIG. 2 may represent either transactions or packets.
Coherence switch 12 may receive the transactions from multiplexer 14 and the coherent and non-coherent transactions may be intermingled. As shown in FIG. 2, transactions may arrive at coherence switch 12 in the following order: C1, C2, NC1, C3, NC2. In one embodiment, coherence switch 12 may identify transactions as coherent or non-coherent based on identifiers accompanying the transactions. The coherence switch 12 may route coherent transactions (C1, C2, and C3) to the processor complex 22. The coherence switch 12 may route non-coherent transactions (NC1 and NC2) to the NRT block 26. In a similar fashion (not shown in FIG. 2), traffic returning from memory via processor complex 22 and NRT block 26 may be interleaved in coherence switch 12 and conveyed back to the multiplexer 14 on a single path as the return traffic makes its way back to the originating I/O devices.
Referring now to FIG. 5, one embodiment of a shadow copy of a configuration register is shown. Shadow register 74 is shown in FIG. 5, and software-writeable register 72 (of FIG. 4) may be arranged in a similar fashion to shadow register 74. Shadow register 74 may store a routing indicator for each address, and the routing indicator may be a single bit (i.e., 0 or 1). For example, in one embodiment, a routing indicator of ‘0’ may designate the coherent path for a particular address and a routing indicator of ‘1’ may designate the non-coherent path. Also, in one embodiment, the address may be the 9-bit identifier accompanying the transaction. In another embodiment, the transaction identifier may be mapped to a value that is used to access the address entry in shadow register 74. The routing indicator may indicate whether or not the corresponding transaction identifier, represented by the address value, is a coherent or non-coherent transaction. In other embodiments, the routing indicator may be a Boolean value (i.e., TRUE or FALSE), may be represented with more than a single bit, or may be represented by various other values or designations.
In another embodiment, shadow register 74 may be split up into multiple registers, with each register corresponding to an address range which is a portion of the total address range. Shadow register 74 is shown in FIG. 5 as containing 512 entries, but this is for illustrative purpose only. It is noted that shadow register 74 may include other numbers of address entries in other embodiments. It is further noted that in other embodiments, shadow register 74 may include other information and may be organized in any suitable manner. For example, in another embodiment, each entry of shadow register 74 may include a valid field to indicate if the particular address or identifier is currently being used or is “in flight” (i.e., has an outstanding transaction).
The coherence switch may route the first transaction on a first path in response to determining the first routing indicator has a first value (block 94). In one embodiment, the first value may be ‘0’ indicating the first transaction is a coherent request. The first path may go from the coherence switch to the ACP of a processor complex. The coherence switch may route the second transaction on a second path in response to determining the second routing indicator has a second value (block 96). In one embodiment, the second value may be ‘1’ indicating the second transaction is a non-coherent request. The second path may go from the coherence switch to a non-real-time (NRT) block and then to a NRT port of a memory controller.
a memory controller comprising a plurality of ports;
a processor complex coupled to a first port of the memory controller;
one or more input/output (I/O) devices; and
a coherence switch coupled to receive transactions from the one or more I/O devices;
wherein the coherence switch is configured to: determine if a received transaction is a coherent transaction or a non-coherent transaction, wherein a non-coherent transaction is a transaction for which a coherency check is not performed; route a received transaction on a first path to a first port of the memory controller responsive to determining the transaction is a coherent transaction, wherein the first path passes through the processor complex; route the received transaction on a second path to a second port of the memory controller responsive to determining the received transaction is a non-coherent transaction, wherein the second path bypasses the processor complex; maintain two copies of a configuration register, wherein a first copy is a software-writeable copy of the configuration register and a second copy is a working copy of the configuration register, wherein each copy stores an indicator for each transaction identifier that specifies whether a corresponding transaction should be routed to memory via the first path or via the second path; responsive to detecting a change to the software-writeable copy of the configuration register: stop accepting new transactions from the plurality of I/O devices; and responsive to determining all outstanding transactions have been routed: update the working copy of the configuration register to match the software-writeable copy of the configuration register; and accept new transactions from the plurality of I/O devices.
3. The apparatus as recited in claim 1, wherein the coherence switch is further configured to:
monitor a number of outstanding transactions.
5. The apparatus as recited in claim 1, wherein the memory controller is configured to:
receive real-time memory requests on the first port; and
receive non-real-time memory requests on the second port.
a coherence switch;
a processor complex comprising one or more processors;
a memory controller coupled to the processor complex and to the coherence switch; and
wherein the coherence switch is configured to: maintain a working copy of a configuration register and a shadow copy of the configuration register, wherein the shadow copy is a software-writeable copy of the working copy of the configuration register, wherein each copy stores an indicator for each transaction identifier that specifies whether a corresponding transaction should be routed to memory via a coherent path or via a non-coherent path; receive a plurality of transactions from the plurality of I/O devices; select either a coherent path or a non-coherent path for routing a received transaction based at least in part on a value stored in the shadow copy of the configuration register, wherein the indicator specifies if a received transaction is a coherent transaction or a non-coherent transaction, wherein a non-coherent transaction is a transaction for which a coherency check is not performed, wherein the coherent path passes through the processor complex to a first port of the memory controller, and wherein the non-coherent path bypasses the processor complex and passes through a second port of the memory controller; and responsive to detecting a change to the shadow copy of the configuration register: stop accepting new transactions from the plurality of I/O devices; and responsive to determining all outstanding transactions have been routed: update the working copy of the configuration register to match the shadow copy of the configuration register; and accept new transactions from the plurality of I/O devices.
10. The apparatus as recited in claim 8, wherein the apparatus further comprises a multiplexer, and wherein the coherence switch is further configured to:
receive return data on two separate ports;
intermingle the received data from the two separate ports; and
convey the intermingled data on a single path to the multiplexer.
receiving a first transaction and a second transaction at a coherence switch, wherein a first identifier accompanies the first transaction, and wherein a second identifier accompanies the second transaction;
accessing a first routing indicator in a configuration register using the first identifier, and accessing a second routing indicator in the configuration register using the second identifier, wherein the configuration register is configured to store an indicator which specifies whether a received transaction should be routed to memory via a first path or a second path, wherein a non-coherent transaction is a transaction for which a coherency check is not performed;
routing the first transaction on a first path responsive to the first routing indicator having a first value, wherein the first path passes through a processor complex to a first port of a memory controller;
routing the second transaction on a second path responsive to the second routing indicator having a second value, wherein the second value is different than the first value, and wherein the second path is coupled to a second port of the memory controller without passing through the processor complex;
maintaining two copies of a configuration register, wherein a first copy is a software-writeable copy of the configuration register and a second copy is a working CODY of the configuration register, wherein each coin stores an indicator for each transaction identifier that specifies whether a corresponding transaction should be routed to memory via the first path or via the second path;
responsive to detecting a change to the software-writeable copy of the configuration register: stop accepting new transactions from the plurality of I/O devices; and responsive to determining all outstanding transactions have been routed: updating the working copy of the configuration register to match the software-writeable copy of the configuration register; and accepting new transactions from the plurality of I/O devices.
a coherence switch coupled to the processor complex;
a multiplexer coupled to the coherence switch;
a plurality of I/O devices coupled to the multiplexer;
a memory controller comprising a plurality of ports, wherein the memory controller is coupled to the processor complex and to the coherence switch; and
wherein the coherence switch is configured to: maintain a working copy of a configuration register and a shadow copy of the configuration register, wherein the shadow copy is a software-writeable copy of the working copy of the configuration register, wherein each copy stores an indicator for each transaction identifier that specifies whether a corresponding transaction should be routed to memory via a coherent path or via a non-coherent path; receive a plurality of transactions from the plurality of I/O devices via the multiplexer; for each transaction, determine if the transaction is a coherent or non-coherent transaction; responsive to determining a received transaction is a coherent transaction, route the received transaction directly to the processor complex; responsive to determining a received transaction is a non-coherent transaction, route the received transaction directly to the memory controller wherein a non-coherent transaction is a transaction for which a coherency check is not performed; responsive to detecting a change to the shadow copy of the configuration register: stop accepting new transactions from the plurality of I/O devices; and responsive to determining all outstanding transactions have been routed: update the working copy of the configuration register to match the shadow copy of the configuration register; and accept new transactions from the plurality of I/O devices.
19. The system as recited in claim 18, wherein the pending update to the configuration register only applies to a first portion of the plurality of I/O devices, wherein a second portion of the plurality of I/O devices is unaffected by the pending update to the configuration register, and wherein responsive to detecting the pending update to the configuration register, the coherence switch is configured to:
stop accepting new transactions from the first portion of the plurality of I/O devices; and
accept new transactions from the second portion of the plurality of I/O devices.
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Patent number: 9176913
Patent Publication Number: 20130061003
Inventors: Timothy J. Millet (Mountain View, CA), Muditha Kanchana (San Jose, CA), Shailendra S. Desai (San Jose, CA)
Primary Examiner: Michael Alsip
Application Number: 13/226,718
Current U.S. Class: Snooping (711/146)
International Classification: G06F 13/40 (20060101); G06F 21/00 (20130101); G06F 13/00 (20060101);