Source: https://patents.google.com/patent/US8866830B2/en
Timestamp: 2018-10-21 01:07:33
Document Index: 135388911

Matched Legal Cases: ['Application No. 08016184', 'Application No. 2008', 'Application No. 08016184', 'Application No. 08016185', 'Application No. 95123833', 'Application No. 95123833', 'Application No. 95123607', 'Application No. 2008']

US8866830B2 - Memory controller interface for micro-tiled memory access - Google Patents
US8866830B2
US8866830B2 US13588995 US201213588995A US8866830B2 US 8866830 B2 US8866830 B2 US 8866830B2 US 13588995 US13588995 US 13588995 US 201213588995 A US201213588995 A US 201213588995A US 8866830 B2 US8866830 B2 US 8866830B2
US13588995
US20120306902A1 (en )
This application is a continuation of application Ser. No. 11/173,375, filed Jun. 30, 2005, now U.S. Pat. No. 8,253,751 which is hereby incorporated by reference.
Referring momentarily to FIG. 6, an address signal line bit map for a memory channel is illustrated using shared and independent address bits. That is, FIG. 6 is an address bit map that illustrates the interpretation of the address bits in a physical address. A set of I independent address bits (IAB) is provided to each sub-channel to support micro-tiling. A set of zero or more SA shared address bits (SAB) may be provided to all of the sub-channels. A set of Q sub-channel select bits (SSB) are used in the assignment of a memory request to a sub-channel. A set of P sub-channel data address bits (SDAB) are used to address the bytes in each cache-line within a DRAM memory. The set of P SDAB bits are typically the least significant bits of the address signal line map. The set of Q SSB bits and the P SDAB bits are not actually routed between the memory controller and the sub-channel memory, it being understood that the base address of the block of data being accessed is an integer multiple of the burst size. That is, the P SDAB bits may be generated internally by a memory integrated circuit such as by a DRAM device in accordance with double data rate (DDR) memory specifications. While FIG. 6 illustrates certain address bits being chosen to be shared and independent address bits, other address bits may be assigned instead. That is, the division of the address bits above the P sub-channel data address (SDAB) bits into the SA shared address (SAB) bits and the I independent address (JAB) bits in general is arbitrary.
In FIG. 4A, a 64 byte memory access transfers the data of a span 404, a 4×4 block of fragments . For example, span 404A is a first 64 byte memory access. Span 404B is a second 64 byte memory access. For example consider that the triangle 401 encompasses approximately fifty-seven pixels to render. For the 64 byte memory access case, ten memory accesses are needed to access the 65 fragments within the triangle. Data of an additional 95 fragments is accessed but might not be used.
The dual four-input multiplexer 900 is a pair of four to one multiplexers each having a first select control input S0 coupled together and a second select control input S1 coupled together. The first four to one multiplexer receives inputs 110-113 and provides the output 1Y in response to the select control inputs S0 and S1. The second four to one multiplexer receives inputs 2I0-2I3 and provides the output 2Y in response to the select control inputs S10 and S1. If S0 and S1 are both logical low or zero, the inputs 1I0 and 2I0 are multiplexed onto the respective outputs 1Y and 2Y. If S0 is a logical high or one and S1 is a logical low or zero, the inputs 1I1 and 2I1 are multiplexed onto the respective outputs 1Y and 2Y. If S0 is a logical low or zero and S1 is a logical high or one, the inputs 1I2 and 2I2 are multiplexed onto the respective outputs 1Y and 2Y. If S0 and S1 are both logical high or one, the inputs 1I3 and 2I3 are multiplexed onto the respective outputs 1Y and 2Y.
The micro-tile control logic 812B includes a first hex two-input multiplexer 901A, a second hex two-input multiplexer 901B, a plurality of AND gates 906-911, a plurality of inverters 913-918, and a thee-input OR gate 923 coupled together as illustrated in FIG. 9B. It is well understood that an OR gate may be formed by coupling the input of an inverter to the output of a NOR gate. The well known formation of an AND gate was previously provided.
The hex three-input multiplexer 960 has the first select control input S0 and the second select control input S1 to select which of the three inputs are to coupled to the respective outputs. As it possible with two select control inputs to select one of four, the truth table for the hex 3-input multiplexer will now be described. If both select bits S0 and S1 are set to zero, the 10 inputs are selected to be output from the multiplexer. If the S0 bit is set to 1 and the S1 bit is set to zero, the I1 inputs are selected to be output from the multiplexer. If the S1 bit it set to one, the I2 inputs are selected to be output from the multiplexer regardless of the bit setting for S0. That is, in this last case, S0 input into the hex 3-input multiplexer is a don't care when the S1 bit is set to one as it is over-riding.
a) a memory interface having a data bus;
b) a first datapath between said memory interface and a cache unit that is coupled to multiple processors;
c) a second datapath between said memory interface and a graphics controller;
d) logic circuitry to:
i) treat said data bus as part of a single data channel for a first memory accessing process whose data content is passed over said first datapath;
ii) treat different parts of said data bus as respective parts of multiple data channels for a second memory accessing process whose data content is passed over said second datapath, each of said multiple data channels having a smaller physical data bus width than said single data channel;
iii) generate additional addressing information for said second memory accessing process as compared to said first memory accessing process, wherein said additional addressing information appears on any of i) through iv) below:
i) additional addressing lines that emanate from said memory interface and that are dedicated for said second memory accessing process but not said first memory accessing process;
ii) unused ECC lines of said single data channel;
iii) address lines that are unused when a column address strobe is asserted;
iv) unused ECC pins of a memory module coupled to said memory interface.
2. The integrated circuit of claim 1 wherein said data bus has a 64 bit physical width.
3. The integrated circuit of claim 1 wherein said multiple data channels comprises four data channels.
4. The integrated circuit of claim 1 wherein said single data channel is a double data rate data channel.
5. The integrated circuit of claim 1 wherein said logic circuitry is to cause said additional addressing information to include different addresses on respective address lines of different ones of said multiple data channels.
performing the following with a memory controller:
by way of a first memory accessing process, transferring first data over a first data channel between a memory interface and at least one memory module;
transferring said first data between said memory interface and a cache that is coupled to multiple processors;
by way of a second memory accessing process, transferring second data over multiple data channels between said memory interface and said at least one memory module such that smaller units of data are individually passed over each of said multiple data channels than units of data passed over said first data channel during said first memory accessing process and such that said first data and said second data are passed over same data bus lines emanating from said memory interface, wherein said second memory accessing process includes passing additional addressing information through said memory interface for said second memory accessing process as compared to said first memory accessing process, said passing of said additional addressing information accomplished by any of i) through iv) below:
i) passing said additional addressing information on additional addressing lines that emanate from said memory interface and that are dedicated for said second memory accessing process but not said first memory accessing process;
ii) passing said additional addressing information on unused ECC lines of said single data channel;
iii) passing said additional addressing information on address lines that are unused when a column address strobe is asserted;
iv) passing said additional addressing information to unused ECC pins of a memory module coupled to said memory interface; and,
transferring said second data between said memory interface and a graphics controller.
7. The method of claim 6 wherein said data bus has a 64 bit physical width.
8. The method of claim 6 wherein said multiple data channels comprises four data channels.
9. The method of claim 6 wherein said single data channel is a double data rate data channel.
10. The method of claim 6 wherein said logic circuitry is to cause said additional addressing information to include different addresses on respective address lines of different ones of said multiple data channels.
non volatile memory storage acting as disk storage and coupled to an I/O controller;
12. The integrated circuit of claim 1 wherein said data bus has a 64 bit physical width.
13. The integrated circuit of claim 1 wherein said multiple data channels comprises four data channels.
14. The integrated circuit of claim 1 wherein said single data channel is a double data rate data channel.
15. The integrated circuit of claim 1 wherein said logic circuitry is to cause said additional addressing information to include different addresses on respective address lines of different ones of said multiple data channels.
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