Source: http://www.google.com/patents/US7088618?dq=6,199,048
Timestamp: 2017-11-18 04:08:04
Document Index: 125101747

Matched Legal Cases: ['§ 119', 'art 304', 'art 305', 'art 306', 'art 307', 'art 307', 'art 307', 'art 307', 'art, 307', 'art 307', 'art 307', 'art 307']

Patent US7088618 - Method of evaluating characteristics of semiconductor memory element, and ... - Google Patents
A characteristic evaluating method of precisely obtaining a resistance value of an offset region in a semiconductor memory element constructed so that the resistance value of the offset region positioned below a memory function element formed on one side or both sides of a gate electrode changes according...http://www.google.com/patents/US7088618?utm_source=gb-gplus-sharePatent US7088618 - Method of evaluating characteristics of semiconductor memory element, and method of extracting model parameter of semiconductor memory element
Publication number US7088618 B2
Application number US 10/986,271
Also published as US20050117419
Publication number 10986271, 986271, US 7088618 B2, US 7088618B2, US-B2-7088618, US7088618 B2, US7088618B2
Inventors Kozo Hoshino, Hiroshi Iwata, Akihide Shibata
Patent Citations (5), Referenced by (25), Classifications (16), Legal Events (5)
Method of evaluating characteristics of semiconductor memory element, and method of extracting model parameter of semiconductor memory element
US 7088618 B2
A characteristic evaluating method of precisely obtaining a resistance value of an offset region in a semiconductor memory element constructed so that the resistance value of the offset region positioned below a memory function element formed on one side or both sides of a gate electrode changes according to an amount of charges or a polarization state of charges accumulated in said memory function element includes: a step of obtaining each of a resistance value between two diffusion regions inclusive formed on both sides of a channel region disposed just below the gate electrode of the semiconductor memory element via a gate insulating film, a resistance value of the channel region, and a resistance value of the diffusion regions; and a step of calculating the resistance value of the offset region which isolates the channel region and the diffusion region from each other on the basis of a result of subtracting the resistance value of the channel region and the resistance value of the diffusion regions from the resistance value between the two diffusion regions.
Rchos=A×exp {B×(Vgs+C×Vbs)}+D
where a potential on the low potential side of said two diffusion regions is used as a reference potential, the resistance value of said offset region is set as Rchos, the potential of said gate electrode is set as Vgs, the potential of said semiconductor layer is set as Vbs, and A, B, C, and D are set as fitting parameters;
Rchos=Rchos0×{1+E×(Vds−Vds0)}
where a potential on the low potential side of said two diffusion regions is used as a reference potential, the resistance value of said offset region is set as Rchos, the potential of said gate electrode is set as Vgs, the potential of said semiconductor layer is set as Vbs, and A, B, C, and D are set as fitting parameters.
This Nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. JP2003-400231 filed in Japan on 28 Nov. 2003, the entire contents of which are hereby incorporated by reference.
The present invention has been achieved in view of the problems and its object is to provide a characteristic evaluating method of precisely obtaining a resistance value of an offset region of a semiconductor memory element constructed so that the resistance value of the offset region below the memory function element changes according to an amount of charges or a polarization state of charges accumulated in a memory function element formed on one side or both sides of a gate electrode, and a method and apparatus for extracting a model parameter for a circuit simulation for the semiconductor memory element.
FIG. 1 is a schematic cross section diagram of a main portion of a semiconductor memory element (first configuration example) as an object of the present invention;
Embodiments of a method of evaluating characteristics of a semiconductor memory element according to the present invention and a model parameter extracting method and apparatus will be described with reference to the drawings.
The memory function element can be formed by a normal semiconductor process in accordance with, for example, a method similar to the method of forming the sidewall spacer having the single-layer or multilayer structure on the sidewalls of the gate electrode. Specific examples are: a method of forming the gate electrode, after that, forming a single-layer film or multilayer film including the charge retaining film such as a film having the function of retaining charges (hereinafter, described as “charge retaining film”), charge retaining film/insulating film, insulating film/charge retaining film, or insulating film/charge retaining film/insulating film, and etching back the formed film under proper conditions so as to leave the films in a sidewall spacer shape; a method of forming an insulating film or charge retaining film, etching back the film under proper conditions so as to leave the film in the sidewall spacer shape, further forming the charge retaining film or insulating film, and similarly etching back the film so as to leave the film in the sidewall spacer shape; a method of applying or depositing an insulating film material in which particles made of a charge retaining material are spread on the semiconductor layer including the gate electrode, and etching back the material under proper conditions so as to leave the insulating film material in a sidewall spacer shape; and a method of forming a gate electrode, after that, forming the single-layer film or multilayer film, and patterning the film with a mask. According to another method, before the gate electrode is formed, the charge retaining film, charge retaining film/insulating film, insulating film/charge retaining film, insulating film/charge retaining film/insulating film, or the like is formed. An opening is formed in a region which becomes the channel region of the films, a gate electrode material film is formed on the entire surface, and the gate electrode material film is patterned in a shape including the opening and larger than the opening.
The principle of the programming operation of the semiconductor memory element will be described with reference to FIGS. 3 and 4. The case where whole memory functional elements 131 a and 131 b have the function of retaining charges will be described. “Programming” denotes here injection of electrons into the memory functional elements 131 a and 131 b when the semiconductor memory element is of the N channel type. Hereinafter, on assumption that the semiconductor memory element is of the N channel type, description will be given.
The principle of erasing operation of the semiconductor memory element will now be described with reference to FIGS. 5 and 6.
FIG. 11 shows drain current Id when the width W2 of the memory functional element 262 is fixed to 100 nm and the offset amount W1 is changed in the structure of the semiconductor memory element of FIG. 9. The drain current was obtained by device simulation on assumption that the memory functional element 262 is in erasing state (holes are accumulated), and the diffusion regions 212 and 213 serve as the source electrode and the drain electrode, respectively.
An embodiment of a method of evaluating characteristics of a semiconductor memory element and a model parameter extracting method according to the present invention will be described with reference to the drawings. In the following description, unless otherwise specified, it is assumed that the semiconductor memory element of the first configuration example or first modification is used as a semiconductor memory element.
The present invention provides a characteristic evaluating method of obtaining a resistance value of the offset region (hereinafter, appropriately referred to as “offset resistance value”) by subtracting the resistance value of the channel region just below the gate electrode and the resistance value of the diffusion regions from the resistance value between two diffusion regions. The resistance value between the two diffusion regions, the resistance value of the channel region just below the gate electrode, and the resistance value of the diffusion region can be relatively easily obtained as will be described later in concrete examples. Therefore, by subtracting the resistance value of the channel region just below the gate electrode and the resistance values of the diffusion regions from the resistance value between the two diffusion regions, the resistance value of the offset region which is important for extraction of the model parameter of the semiconductor memory element can be easily obtained.
The method of the present invention of modeling the offset resistance value obtained by the characteristic evaluating method and extracting a model parameter will be described below. A case where each of the diffusion regions is of the N type will be described here. Alternately, each of the diffusion regions in the present invention may be of the P type. The diffusion region of a low voltage out of the two diffusion regions will be called a source diffusion region and the diffusion region of a high voltage will be called a drain diffusion region (hereinafter, referred to as “source” and “drain”, respectively).
Rchos=A×exp{B×(Vgs+C×Vbs)}+D (1)
Rchos=Rchos0×{1+E×(Vds−Vds0)} (2)
Rt=(Rchg+Rchs+Rchd)+2×Rsh (3)
Rt=(Rchg+2×Rsh)+2×Rchos (4)
Rt={rch×L/(W−ΔW)+2×rsh×D1/(W−ΔW)}+2×Rchos (5)
The characteristic evaluating method in the embodiment is characterized in that the offset resistance value (Rchos) is calculated with precision by deriving the invalid gate width (ΔW) and the channel resistance value (rch) per predetermined size from an IGFET having an LDD (Lightly Doped Drain) region having little variation factors and a low degree of influence of variations (hereinafter, referred to as “LDD-structured transistor”) (see FIG. 15).
(Inclination)=δRt/δL=δRch/δLeff=rch/Weff=rch/(W−ΔW) (6)
rch(Ω/□)=(Inclination)×(W−ΔW) (7)
A concrete evaluating method will be described with reference to FIG. 18. First, in step S310, the total resistance value (Rt) between the source and drain inclusive obtained from the semiconductor memory element is plotted (the plot is indicated by solid marks in the graph). In step S330, each of graph straight lines is plotted at an inclination value of the graph straight line obtained from the LDD-structured transistor (the plot is indicated by hollow marks in the graph). AY-axis section when the gate length (L) becomes “0” is expressed by Equation (8) from Equation (5).
Rt=2×rsh×D1/(W−ΔW)+2×Rchos (8)
Rchos=A′×exp[B×{(Vgs−Vth)+C×Vbs}]+D=A′×exp{B×(Vgs+C×Vbs)−B×Vth}+D={A′/exp(B×Vth)}×exp{B×(Vgs+C×Vbs)}+D (9)
A=A′/exp(B×Vth) (10)
Rchos=A×exp{B×(Vgs+C×Vbs)}+D (11)
The offset resistance value of each of the source and drain sides determined above is given to (a) each of model parameters regarding source-drain parasitic resistance in the IGFET model or (b) each of resistive elements on the source and drain sides when a voltage variable resistive element is regarded as an external resistor and circuits disposed on both sides of the source and drain of the IGFET are regarded as equivalent circuits of the semiconductor memory element. The value of each of the model parameters regarding the source-drain parasitic resistance in the IGFET model at that time is set to “0”.
First, fitting is performed to the Ids-Vgs-Vbs characteristic under a sufficiently low drain voltage condition (for example, Vds=0.1 V, which is expressed as “Vds0” below) in the linear region by using SPICE parameters in the IGFET model (for example, BSIM3v3) (step S700).
Rchos′=Rchos0×{1+E×(Vds−Vds0)} (12)
An embodiment of a model parameter extracting apparatus for a semiconductor memory element according to the present invention (hereinafter, appropriately referred to as “inventive apparatus”) will be described with reference to the drawings.
The more-concrete configuration will be described with reference to the block diagram of FIG. 23. The apparatus is roughly constructed by a measurement controlling apparatus 301, a measuring apparatus 302, and an object 303 to be measured. The measurement controlling apparatus 301 is constructed by a measurement control part 304 such as a measurement program, an input part 305 such as a keyboard and a mouse, an output part 306 for performing display such as a CRT or liquid crystal display, and a calculation part 307 such as a CPU for performing a computing process. The calculation part 307 is constructed by a part 307 a for calculating total resistance value (Rt) between the source and drain inclusive of the semiconductor memory element, a part 307 b for calculating invalid gate width (ΔW) and a channel resistance value (rch) per predetermined size of an IGFET having a normal structure (for example, the LDD-structured transistor), a part, 307 c for calculating a diffusion resistance value (rsh) per predetermined size of the diffusion resistive element, a part 307 d for calculating the offset resistance value (Rchso) of the semiconductor memory element, a part 307 e for extracting the fitting parameters (A to E) of the model formula in the first embodiment, and a normal IGFET model parameter extracting part 307 f.
The operations of the apparatus for evaluating the characteristics of the semiconductor memory element and the model parameter extracting apparatus in the inventive apparatus will be described.
JPH0530427A Title not available
JPH0581075A Title not available
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U.S. Classification 365/185.05, 365/185.06, 365/185.14
International Classification G11C11/34, G11C11/22, H01L29/00, G11C16/04, H01L29/792, H01L27/115, H01L21/8247, H01L29/788, G11C16/26
Cooperative Classification G11C16/26, G11C16/0425
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOSHINO, KOZO;IWATA, HIROSHI;SHIBATA, AKIHIDE;REEL/FRAME:015985/0895;SIGNING DATES FROM 20041021 TO 20041025