Source: http://www.google.com/patents/US7989280?dq=6,606,102
Timestamp: 2015-04-28 15:37:52
Document Index: 542857681

Matched Legal Cases: ['Application No. 11', 'Application No. 094136197', 'Application No. 03817697', 'Application No. 10', 'Application No. 10', 'Application No. 200580009823', 'Application No. 200680021817', 'Application No. 05711376', 'Application No. 05711376', 'Application No. 112006001735', 'Application No. 10', 'Application No. 0724762', 'Application No. 200680023301', 'Application No. 03817699', 'Application No. 2006', 'Application No. 200580007279', 'Application No. 95122087', 'Application No. 95122087', 'Application No. 95123858', 'Application No. 95123858', 'Application No. 95123858', 'Application No. 95135820', 'Application No. 95135820', 'Application No. 95135820', 'Application No. 095143047', 'Application No. 10184650', 'Application No. 200680021817', 'Application No. 200580032314', 'Application No. 200680044431', 'Application No. 200580032314', 'Application No. 2005070131', 'Application No. 200604766']

Patent US7989280 - Dielectric interface for group III-V semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region....http://www.google.com/patents/US7989280?utm_source=gb-gplus-sharePatent US7989280 - Dielectric interface for group III-V semiconductor deviceAdvanced Patent SearchPublication numberUS7989280 B2Publication typeGrantApplication numberUS 12/338,839Publication dateAug 2, 2011Filing dateDec 18, 2008Priority dateNov 30, 2005Also published asCN101341583A, CN101341583B, EP1955366A1, EP1955366B1, EP2273538A2, EP2273538A3, EP2273538B1, US7485503, US20070123003, US20090095984, WO2007064492A1Publication number12338839, 338839, US 7989280 B2, US 7989280B2, US-B2-7989280, US7989280 B2, US7989280B2InventorsJustin K. Brask, Suman Datta, Mark L. Doczy, James M. Blackwell, Matthew V. Metz, Jack T. Kavalieros, Robert S. ChauOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (178), Referenced by (6), Classifications (27) External Links: USPTO, USPTO Assignment, EspacenetDielectric interface for group III-V semiconductor device
This application is a divisional of U.S. patent application Ser. No. 11/292,399, filed Nov. 30, 2005 now U.S. Pat. No. 7,485,503, entitled �DIELECTRIC INTERFACE FOR GROUP III-V SEMICONDUCTOR DEVICE,� the entire contents of which are hereby incorporated by reference herein.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4231149Oct 10, 1978Nov 4, 1980Texas Instruments IncorporatedNarrow band-gap semiconductor CCD imaging device and method of fabricationUS4487652Mar 30, 1984Dec 11, 1984Motorola, Inc.Semiconductor with insulating layerUS4711701Sep 16, 1986Dec 8, 1987Texas Instruments IncorporatedSelf-aligned transistor methodUS4751201Mar 4, 1987Jun 14, 1988Bell Communications Research, Inc.Reduced surface state densityUS4818715Jul 9, 1987Apr 4, 1989Industrial Technology Research InstituteMethod of fabricating a LDDFET with self-aligned silicideUS4871692Sep 30, 1988Oct 3, 1989Lee Hong HUsing compound of phosphorous with sulfur, selenium, tellurium or poloniumUS4872046Sep 1, 1987Oct 3, 1989University Of IllinoisHeterojunction semiconductor device with <001> tiltUS4905063Jun 21, 1988Feb 27, 1990American Telephone And Telegraph Company, At&T Bell LaboratoriesFloating gate memoriesUS4906589Feb 6, 1989Mar 6, 1990Industrial Technology Research InstituteInverse-T LDDFET with self-aligned silicideUS4907048Nov 23, 1987Mar 6, 1990Xerox CorporationDouble implanted LDD transistor self-aligned with gateUS4914059Aug 19, 1988Apr 3, 1990Yves NissimProcess for the heat flash vapour phase deposition of an insulating layer on a III-V material substrate and its application to the production of a MIS structureUS4994873Dec 26, 1989Feb 19, 1991Motorola, Inc.Local interconnect for stacked polysilicon deviceUS4996574Jun 30, 1989Feb 26, 1991Fujitsu LimitedMIS transistor structure for increasing conductance between source and drain regionsUS5023203Jun 23, 1989Jun 11, 1991Korea Electronics & Telecommunications Research Institute Et Al.Multilayer mask including intermediate spacerUS5120666May 2, 1990Jun 9, 1992Fujitsu LimitedManufacturing method for semiconductor deviceUS5124777Jan 3, 1991Jun 23, 1992Samsung Electronics Co., Ltd.Of strontium, barium, lanthanum and niobium oxides, crystal structureUS5179037Dec 24, 1991Jan 12, 1993Texas Instruments IncorporatedIntegration of lateral and vertical quantum well transistors in the same epitaxial stackUS5216271Sep 27, 1991Jun 1, 1993Kabushiki Kaisha ToshibaBiCMOS device with low bandgap CMOS contact regions and low bandgap bipolar base regionUS5278102Feb 12, 1993Jan 11, 1994Fujitsu LimitedSOI device and a fabrication process thereofUS5308999Feb 24, 1993May 3, 1994Fujitsu LimitedMOS FET having a thin film SOI structureUS5328810Nov 25, 1992Jul 12, 1994Micron Technology, Inc.Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic processUS5338959Mar 30, 1993Aug 16, 1994Samsung Electronics Co., Ltd.Thin film transistor with three dimensional multichannel structureUS5346836Aug 17, 1993Sep 13, 1994Micron Technology, Inc.Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnectsUS5346839Jan 8, 1993Sep 13, 1994Texas Instruments IncorporatedSidewall doping technique for SOI transistorsUS5357119Feb 19, 1993Oct 18, 1994Board Of Regents Of The University Of CaliforniaField effect devices having short period superlattice structures using Si and GeUS5391506Jan 27, 1993Feb 21, 1995Kawasaki Steel CorporationManufacturing method for semiconductor devices with source/drain formed in substrate projection.US5428237Nov 29, 1993Jun 27, 1995Canon Kabushiki KaishaSemiconductor device having an insulated gate transistorUS5466621Oct 25, 1993Nov 14, 1995Hitachi, Ltd.Method of manufacturing a semiconductor device having silicon islandsUS5475869May 27, 1994Dec 12, 1995Nec CorporationRadio base station capable of distinguishing between interference due to collisions of outgoing call signals and an external interference noiseUS5479033May 27, 1994Dec 26, 1995Sandia CorporationComplementary junction heterostructure field-effect transistorUS5482877Feb 16, 1994Jan 9, 1996Samsung Electronics Co., Ltd.Method for making a semiconductor device having a silicon-on-insulator structureUS5495115Aug 8, 1994Feb 27, 1996Hitachi, Ltd.Semiconductor crystalline laminate structure, forming method of the same, and semiconductor device employing the sameUS5514885Jan 13, 1995May 7, 1996Myrick; James J.Charge coupled deviceUS5521859Jan 17, 1995May 28, 1996Fujitsu LimitedSemiconductor memory device having thin film transistor and method of producing the sameUS5543351Oct 31, 1994Aug 6, 1996Matsushita Electric Industrial Co., Ltd.Method of producing electrically insulated silicon structureUS5545586May 13, 1994Aug 13, 1996Nec CorporationMethod of making a transistor having easily controllable impurity profileUS5563077Jun 20, 1995Oct 8, 1996Hyundai Electronics Industries Co., Ltd.Method of fabricating a thin film transistor having vertical channelUS5576227Nov 2, 1994Nov 19, 1996United Microelectronics Corp.Process for fabricating a recessed gate MOS deviceUS5578513Apr 20, 1995Nov 26, 1996Mitsubishi Denki Kabushiki KaishaMethod of making a semiconductor device having a gate all around type of thin film transistorUS5595919Feb 20, 1996Jan 21, 1997Chartered Semiconductor Manufacturing Pte Ltd.Method of making self-aligned halo process for reducing junction capacitanceUS5595941Feb 27, 1995Jan 21, 1997Mitsubishi Denki Kabushiki KaishaSemiconductorsUS5652454Jul 3, 1996Jul 29, 1997Iwamatsu; ToshiakiSemiconductor device on an SOI substrateUS5658806Oct 26, 1995Aug 19, 1997National Science CouncilMethod for fabricating thin-film transistor with bottom-gate or dual-gate configurationUS5665203Apr 28, 1995Sep 9, 1997International Business Machines CorporationSilicon etching methodUS5682048May 17, 1996Oct 28, 1997Nissan Motor Co., Ltd.Groove-type semiconductor deviceUS5698869Sep 13, 1995Dec 16, 1997Kabushiki Kaisha ToshibaInsulated-gate transistor having narrow-bandgap-sourceUS5701016Nov 24, 1995Dec 23, 1997Kabushiki Kaisha ToshibaSemiconductor device and method for its manufactureUS5716879Jan 13, 1997Feb 10, 1998Goldstar Electron Company, Ltd.Method of making a thin film transistorUS5739544Dec 12, 1995Apr 14, 1998Matsushita Electric Industrial Co., Ltd.Quantization functional device utilizing a resonance tunneling effect and method for producing the sameUS5760442Sep 29, 1995Jun 2, 1998Kabushiki Kaisha ToshibaSemiconductor device of a silicon on insulator metal-insulator type with a concave featureUS5770513May 2, 1995Jun 23, 1998Mitsubishi Denki Kabushiki KaishaMethod for producing semiconductor device with heat dissipation structureUS5773331Dec 17, 1996Jun 30, 1998International Business Machines CorporationMethod for making single and double gate field effect transistors with sidewall source-drain contactsUS5776821Aug 22, 1997Jul 7, 1998Vlsi Technology, Inc.Pre-gate side-walls exposed; removing oxide layer to reduce width while retaining a maskUS5793088Jun 18, 1996Aug 11, 1998Integrated Device Technology, Inc.Structure for controlling threshold voltage of MOSFETUS5804848Oct 31, 1997Sep 8, 1998Sony CorporationField effect transistor having multiple gate electrodes surrounding the channel regionUS5811324Feb 28, 1997Sep 22, 1998Lg Semicon Co., Ltd.Method for manufacturing thin film transistorUS5814895Dec 19, 1996Sep 29, 1998Sony CorporationStatic random access memory having transistor elements formed on side walls of a trench in a semiconductor substrateUS5821629Jul 12, 1995Oct 13, 1998United Microelectronics CorporationField isolation between active regions is not field oxide but doped silicon substrate; ultra-high density static random access memory cellUS5827769Nov 20, 1996Oct 27, 1998Intel CorporationMethod for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrodeUS5844278Sep 13, 1995Dec 1, 1998Kabushiki Kaisha ToshibaSemiconductor device having a projecting element regionUS5856225Nov 24, 1997Jan 5, 1999Chartered Semiconductor Manufacturing LtdCreation of a self-aligned, ion implanted channel region, after source and drain formationUS5859456Sep 9, 1996Jan 12, 1999Texas Instruments IncorporatedProgrammable integrated circuits utilizing lateral double diffused metal oxide semiconductor technologyUS5880015Oct 14, 1994Mar 9, 1999Sgs-Thomson Microelectronics, Inc.Method of producing stepped wall interconnects and gatesUS5883564Sep 11, 1996Mar 16, 1999General Motors CorporationMagnetic field sensor having high mobility thin indium antimonide active layer on thin aluminum indium antimonide buffer layerUS5888309Dec 29, 1997Mar 30, 1999Taiwan Semiconductor Manufacturing Company, Ltd.Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasmaUS5889304Jun 27, 1997Mar 30, 1999Kabushiki Kaisha ToshibaNonvolatile semiconductor memory deviceUS5899710Feb 25, 1998May 4, 1999Sony CorporationMethod for forming field effect transistor having multiple gate electrodes surrounding the channel regionUS5905285Feb 26, 1998May 18, 1999Advanced Micro Devices, Inc.Ultra short trench transistors and process for making sameUS5908313Dec 31, 1996Jun 1, 1999Intel CorporationMethod of forming a transistorUS5952701Aug 18, 1997Sep 14, 1999National Semiconductor CorporationDesign and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor valueUS5965914Dec 23, 1997Oct 12, 1999Mitsubishi Denki Kabushiki KaishaThin film transistor having a branched gate and channelUS5976767Oct 9, 1997Nov 2, 1999Micron Technology, Inc.Ammonium hydroxide etch of photoresist masked siliconUS5981400Sep 18, 1997Nov 9, 1999Cornell Research Foundation, Inc.Compliant universal substrate for epitaxial growthUS5985726Nov 6, 1998Nov 16, 1999Advanced Micro Devices, Inc.Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFETUS6013926Apr 18, 1997Jan 11, 2000Mitsubishi Denki Kabushiki KaishaSemiconductor device with refractory metal elementUS6018176Sep 8, 1997Jan 25, 2000Samsung Electronics Co., Ltd.Vertical transistor and memory cellUS6031249Jul 8, 1997Feb 29, 2000Semiconductor Energy Laboratory Co., Ltd.CMOS semiconductor device having boron doped channelUS6051452Jan 6, 1998Apr 18, 2000Kabushiki Kaisha ToshibaMethod for manufacturing a semiconductor device with ion implantationUS6054355Jun 29, 1998Apr 25, 2000Kabushiki Kaisha ToshibaMethod of manufacturing a semiconductor device which includes forming a dummy gateUS6063675Oct 24, 1997May 16, 2000Texas Instruments IncorporatedMethod of forming a MOSFET using a disposable gate with a sidewall dielectricUS6063677Oct 24, 1997May 16, 2000Texas Instruments IncorporatedMethod of forming a MOSFET using a disposable gate and raised source and drainUS6066869Oct 6, 1997May 23, 2000Micron Technology, Inc.Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitorUS6087208Mar 31, 1998Jul 11, 2000Advanced Micro Devices, Inc.Method for increasing gate capacitance by using both high and low dielectric gate materialUS6093621Apr 5, 1999Jul 25, 2000Vanguard International Semiconductor Corp.Method of forming shallow trench isolationUS6114201Jun 1, 1998Sep 5, 2000Texas Instruments-Acer IncorporatedMethod of manufacturing a multiple fin-shaped capacitor for high density DRAMsUS6114206Nov 6, 1998Sep 5, 2000Advanced Micro Devices, Inc.Multiple threshold voltage transistor implemented by a damascene processUS6117697Jul 27, 1998Sep 12, 2000The United States Of America As Represented By The Secretary Of The Air ForceDepositing an ultrathin active film responsive to changes in magnetic field energy onto a compliant layer of periodic table group 3-5 semiconductor material on semiconductor substrate, which is capable of retaining strain energyUS6117741Jan 5, 1999Sep 12, 2000Texas Instruments IncorporatedMethod of forming a transistor having an improved sidewall gate structureUS6120846Dec 23, 1997Sep 19, 2000Advanced Technology Materials, Inc.Simultaneously exposing insulating portion and electrically conductive portion of substrate to chemical vapor deposition process; during procedure selectively depositing bismuth based ferroelectric thin film on electrically conductive portionUS6133593Jul 23, 1999Oct 17, 2000The United States Of America As Represented By The Secretary Of The NavyChannel design to reduce impact ionization in heterostructure field-effect transistorsUS6144072Jan 15, 1999Nov 7, 2000Mitsubishi Denki Kabushiki KaishaSemiconductor device formed on insulating layer and method of manufacturing the sameUS6150222Jan 7, 1999Nov 21, 2000Advanced Micro Devices, Inc.Method of making a high performance transistor with elevated spacer formation and self-aligned channel regionsUS6153485Nov 9, 1998Nov 28, 2000Chartered Semiconductor Manufacturing Ltd.Forming transistorsUS6163053Nov 5, 1997Dec 19, 2000Ricoh Company, Ltd.Semiconductor device having opposite-polarity region under channelUS6165880Jun 15, 1998Dec 26, 2000Taiwan Semiconductor Manufacturing CompanyDouble spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuitsUS6174820Feb 16, 1999Jan 16, 2001Sandia CorporationUse of silicon oxynitride as a sacrificial material for microelectromechanical devicesUS6190975Dec 9, 1998Feb 20, 2001Matsushita Electric Industrial Co., Ltd.Method of forming HCMOS devices with a silicon-germanium-carbon compound semiconductor layerUS6200865Dec 4, 1998Mar 13, 2001Advanced Micro Devices, Inc.Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gateUS6218309Sep 30, 1999Apr 17, 2001Lam Research CorporationMethod of achieving top rounding and uniform etch depths while etching shallow trench isolation featuresUS6252262 *Dec 15, 1998Jun 26, 2001The United States Of America As Represented By The Secretary Of The NavyMetal passivating layer for III-V semiconductors, and improved gate contact for III-V-based metal-insulator-semiconductor (MIS) devices* Cited by examinerNon-Patent CitationsReference1 *Ashley et al. "High Speed, Low-Power InSb Transistors," IEEE, 1997, pp. 30.4.1-30.4.4.2Ashley, et al., "Novel InSb-based Quantum Well Transistors for High Speed, Low Power Applications", QinetiQ, Malvern Technology Center and Intel (2004), 4 pgs.3Ashley, et al., "Novel InSb-based Quantum Well Transistors for Ultra-High Speed, Low Power Logic Applications", IEEE 2004, pp. 2253-2256.4Auth, Christopher P. et al., Vertical, Fully-Depleted, Surrounding Gate MOSFETs on sub-0.1 um Thick Silicon Pillars, 54th Annual Device Research Conference Digest, 1996, 2 Pages.5Balakrishnan, G. et al., "Room-Temperature Optically-Pumped InGaSb Quantum Well Lasers Monolithically Grown on Si (100) Substrate", IEE 2005, 2 Pages, Mailed Feb. 12, 2005.6Bandyopadhyay, Krisanu et al., "Self-Assembled Monolayers of Small Aromatic Disulfide and Diselenide Molecules on Polycrystalline Gold Films:", Department of Chemistry & Regional Sophisticated Instrumentation Centre, India Institute of Technology, Apr. 30, 1999, 10 Pages.7Bednyi, et al., "Electronic State of the Surface of INP Modified by Treatment in Sulfur Vapor", Soviet Physics Semiconductors, Am. Inst. of Physics, New York, vol. 26, No. 8, Aug. 1, 1992, 2 pgs.8 *Bessolov and Lebedev., "Chacogenide passivation of III-V semiconductor surfaces", Semiconductores, 32, 1998, pp. 1141-1156.9Buchanan, D. A. et al., Fabrication of Midgap Metal Gates Compatible With Ultrathin Dielectrics, Applied Physics Letters, vol. 73.12, Sep. 21, 1998, 3 Pages.10Burenkov, A. et al., Corner Effect in Double and Triple Gate FinFETs, European Solid-State Device Research 2003, 33rd Conference on ESSDERC, 4 Pages.11Chang, L. et al., CMOS Circuit Performance Enhancement by Surface Orientation Optimization, IEEE Transactions on Electron Devices, vol. 51, No. 10, Oct. 2004, 7 Pages.12Chang, S. T. et al., 3-D Simulation of Strained Si/SiGe Heterojunction FinFets, Semiconductor Device Research Symposium, Dec. 2003, 2 Pages.13Chau, Robert, Advanced Metal Gate/High-K Dielectric Stacks for High-Performance CMOS Transistors, Components Research, Intel Corporation, 2004, 3 Pages.14Choi, Yang-Kyu et al., A Spacer Patterning Technology for Nanoscale CMOS, IEEE, (49)3, XP-001102694, Mar. 2002, 6 Pages.15Choi, Yang-Kyu et al., Sub-20nm CMOS FinFET Technologies, IEEE, IEDM, 2001, 4 Pages.16Claflin, B. et al., Interface Studies of Tungsten Nitride and Titanium Nitride Composite Metal Gate Electrodes With Thin Dielectric Layers, Journal of Vacuum Science and Technology A 16.3, May/Jun. 1998, 5 Pages.17Collaert, N, et al., A Functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node, IEEE Electron Device Letters, vol. 25, No. 8, Aug. 2004, 3 Pages.18Datta, et al., "85nm Gate Length Enhancement and Depletion Mode InSb Quantum Well Transistors for Ultra High Speed and Very Low Power Digital Logic Applications", IEEE Dec. 5, 2005, 4 pgs.19Examination Report from EP 06837855.3-1235 mailed Oct. 24, 2008, 13 pgs.20Final Office Action for U.S. Appl. No. 11/154,138 mailed Dec. 8, 2009, 13 Pages.21Final Office Action for U.S. Appl. No. 11/322,795 Mailed Jan. 13, 2010, 12 Pages.22Final Office Action for U.S. Appl. No. 11/335,103 mailed May 26, 2010, 14 Pages.23Final Office Action for U.S. Appl. No. 11/828,290, mailed Feb. 17, 2010, 18 Pages.24Final Office Action from U.S. Appl. No. 11/080,765 mailed Nov. 13, 2007, 13 Pages.25Final Office Action from U.S. Appl. No. 11/158,661 mailed Jan. 15, 2008, 25 Pages.26Final Office Action from U.S. Appl. No. 11/238,445 mailed May 14, 2007, 16 Pages.27Final Office Action from U.S. Appl. No. 11/240,487 mailed Sep. 21, 2009, 22 Pages.28Final Office Action from U.S. Appl. No. 11/305,452 mailed Jan. 21, 2011, 15 Pages.29Final Office Action from U.S. Appl. No. 11/305,452 mailed Nov. 13, 2009, 8 Pages.30Final Office Action from U.S. Appl. No. 11/498,901 mailed Dec. 17, 2009, 10 Pages.31Final Office Action from U.S. Appl. No. 11/498,901 mailed Sep. 1, 2010, 16 Pages.32Final Office Action from U.S. Appl. No. 12/025,665 mailed Jun. 10, 2009, 10 Pages.33Final Office Action from U.S.Appl. No. 11/498,901 mailed Nov. 17, 2008, 17 Pages.34First Office Action from Chinese Applications No. 2006800444311, mailed Nov. 25, 2009, 15 pgs.35Frank, et al., "HfO2 and AI2O3 Gate Dielectrics on GaAs Grown by Atomic Layer Deposition", Applied Physics Letters, vol. 86, Issue 15, id 152904, 2005, 1 pg.36Fried, David M. et al., High-Performance P-Type Independent-Gate FinFETs, IEEE 25(4), 2004, 3 Pages.37Fried, David M. et al., Improved Independent Gate N-Type FinFET Fabrication and Characterization, IEEE 24(9), Sep. 2003, 3 Pages.38German Office Action for German Patent Application No. 11 2006 003 576.2-33 mailed Dec. 12, 2008, 3 Pages.39 *Gonzalez et al., "Selenium passivation of GaAs (001): a combined experimental and theoretical study", J.Phys.Condens.Matter 16, 2004, pp. 2187-2206.40Guo, Jing et al., Performance Projections for Ballistic Carbon Nanotube Field-Effect Transistors, Applied Physics Letters 80(17), Apr. 29, 2002, 3 Pages.41Hisamoto, Digh et al., A Folded-Channel MOSFET for Deepsub-tenth Micron Era, 1998 IEEE International Electron Device Meeting Technical Digest, 3 Pages.42Hisamoto, Digh et al., A Fully Depleted Lean-Channel Transistor (DELTA)-A Novel Vertical Ultrathin SOI MOSFET, IEEE Electron Device Letters, V. 11 (1), Jan. 1990, 4 Pages.43Hisamoto, Digh et al., FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm, IEEE Transactions on Electron Devices, vol, 47, No. 12, Dec. 2000, 6 Pages.44Huang, Xuejue et al., "Sub 50 nm FinFET: PMOS", 1999 IEEE International Electron Device Meeting Technical Digest, 1999, 4 Pages.45Hwang, Jeong-Mo et al,. Novel Polysilicon/Tin Stacked-Gate Structure for Fully-Depleted SOI/CMOS, International Electronic Devices Meeting Technical Digest, 1992, 4 Pages.46Ieong, M. et al., Three Dimensional CMOS Devices and Integrated Circuits, IEEE CICC, San Jose, CA Sep. 21-24, 2003, 8 Pages.47International Preliminary Report on Patentability from Application No. PCT/US2006/024516 mailed Jan. 10, 2008, 11 Pages.48International Preliminary Report on Patentability from PCT/US2005/010505 mailed on Oct. 12, 2006, 16 Pages.49International Preliminary Report on Patentability from PCT/US2006/044601 mailed Jun. 12, 2008, 11 pgs.50International Search Report & Written Opinion from PCT/US2004/032442 mailed on Jun. 16, 2005, 12 Pages.51International Search Report & Written Opinion from PCT/US2005/000947 mailed on May 3, 2005, 14 Pages.52International Search Report & Written Opinion from PCT/US2005/033439 mailed on Jan. 31, 2006, 7 Pages.53International Search Report & Written Opinion from PCT/US2005/035380 mailed on Feb. 13, 2006, 14 Pages.54International Search Report & Written Opinion from PCT/US2005/037169 mailed on Feb. 23, 2006, 11 Pages.55International Search Report & Written Opinion from PCT/US2006/000378 mailed on May 24, 2006, 11 Pages.56International Search Report & Written Opinion from PCT/US2006/025751 mailed on Dec. 6, 2006, 14 Pages.57International Search Report & Written Opinion from PCT/US2006/037634 mailed on May 31, 2007, 21 Pages.58International Search Report & Written Opinion from PCT/US2006/037643 mailed on Jan. 24, 2007, 14 Pages.59International Search Report and Written Opinion from PCT/US2005/010505 mailed Aug. 26, 2005, 24 Pages.60International Search Report and Written Opinion from PCT/US2005/020339 mailed on Oct. 4, 2005, 12 Pages.61International Search Report and Written Opinion from PCT/US2006/044601 mailed Mar. 19, 2007, 17 pgs.62International Search Report from PCT/US 03/26242 mailed on Jan. 26, 2004, 8 Pages.63International Search Report from PCT/US 03/39727 mailed on Apr. 27, 2004, 6 Pages.64International Search Report from PCT/US 03/40320 mailed Jun. 2, 2004, 6 Pages.65International Search Report from PCT/US2003/26242 mailed Jan. 26, 2004, 8 Pages.66International Search Report PCT/US2003/40320 mailed Jun. 2, 2004, 6 Pages.67Invitation to Pay Additional Fees from PCT/US2004/032442 mailed on Apr. 12, 2005, 5 Pages.68IPO Search Report for Taiwan Patent Application No. 094136197, date mailed Sep. 19, 2008, 1 Page.69Jang, H.W., et al., "Incorporation of Oxygen Donors in AIGaN", J. Electrochem Soc 152, 2004, 5 pgs.70Javey, Ali et al., Ballistic carbon nanotube field-effect transistors, Nature, vol. 424, Aug. 7, 2003, 4 Pages.71Javey, Ali et al., High-k dielectrics for advanced carbon-nanotube transistors and logic gates, www.nature.com/naturematerials.com, 2002, 6 Pages.72Jin, B., Mobility Enhancement in Compressively Strained Sige Surface Channel PMOS Transistors with HFO2/TIN Gate Stack, Components Research, Intel Corporation, Oct. 2004, 12 Pages.73Jones, E. C. et al., Doping Challenges in Exploratory Devices for High Performance Logic, 14th Int'l Conference, Piscataway, NJ, Sep. 22-27, 2002, 6 Pages.74Kim, Sung M. et al., A Novel Multi-channel Field Effect Transistor (McFET) on Bulk Si for High Performance Sub-80nm Application, IEEE, 2004, 4 Pages.75Kuo, Charles et al,, "A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications", IEEE 50(12), (2003), 9 Pages.76Kuo, Charles et al., A Capacitorless Double-Gate DRAM Cell Design for High Density Applications, IEEE, 2002, 4 Pages.77 *Kuruvilla et al., "Passivation of GaAs (100) using selenium sulfide," J. Appl.Phys. 73, 1993, pp. 4384-4387.78Ludwig et al., FinFET Technology for Future Microprocessors, IEEE Int'l. SOI Conference, New Port Beach, CA, Sep. 29-Oct. 2, 2003, 2 Pages.79Martel, Richard et al., "Carbon Nanotube Field Effect Transistors for Logic Applications", IEEE 2001, 4 Pages.80Mayer, T. M. et al., "Chemical Vapor Deposition of Flouroalkylsilane Monolayer Films for Adhesion Control in Microelectromechanicai Systems", J. Vac. Sci. Technol. B. 18(5), 2000, 8 Pages.81 *Mistele et al., "Incorporation of Dielectric Layers into the Processing of III-Nitride-based Heterostructure Field-Effect Transistors", J. Electronic Materials, 32, 2003, pp. 355-363.82Mori, M. et al., "Heteroepitaxial Growth of InSb on a Si (0 0 1) Substrate Via AISb Buffer Layer", Applied Surface Science 216, 2003, 6 Pages.83Nackaerts et al,, "A 0.314um2 6T-SRAM Cell build with Tall Triple-Gate Devices for 45nm node applications using 0.75NA 193nm lithography", IEEE, 2004, 4 Pages.84Non-Final Office Action for European Application No. 03817697.0 Mailed Mar. 9, 2010, 5 Pages.85Non-Final Office Action for Korean Patent Application No. 10-2007-7030988 Mailed Mar. 12, 2010, 3 Pages.86Non-Final Office Action for U.S. Appl. No. 10/973,228 mailed Feb. 2, 2010, 22 Pages.87Non-Final Office Action for U.S. Appl. No. 11/240,440 mailed May 15, 2010, 8 Pages.88Non-Final Office Action for U.S. Appl. No. 11/240,487 mailed Dec. 11, 2009, 11 Pages.89Non-Final Office Action for U.S. Appl. No. 11/335,103 mailed Nov. 13, 2009, 17 Pages.90Non-final Office Action for U.S. Appl. No. 11/855,823 mailed Mar. 15, 2010 31 Pages.91Non-Final Office Action for U.S. Appl. No. 11/855,823, Mailed Jul. 23, 2009, 31 Pages.92Non-Final Office Action for U.S. Appl. No. 12/114,227 mailed Mar. 30, 2010, 30 Pages.93Non-Final Office Action for U.S. Appl. No. 12/259,464, Mailed Oct. 20, 2009, 41 Pages.94Non-Final Office Action for U.S. Appl. No. 12/369,642 mailed Apr. 27, 2010, 15 Pages.95Non-Final Office Action from U.S. Appl. No. 11/322,795 Mailed Jul. 28, 2009, 18 Pages.96Notice of Allowance and Fees for U.S. Appl. No. 11/855,823 Mailed Sep. 2, 2010, 33 Pages.97Notice of Allowance for U.S. Appl. No. 11/154,138 mailed Aug. 13, 2010, 10 Pages.98Notice of Allowance from U.S. Appl. No. 11/501,253 mailed Apr. 7, 2009, 5 Pages.99Notice of Preliminary Rejection mailed Sep. 14, 2009 for Korean Application No. 10-2007-7030988 incl. translation, 4 Pages.100Nowak, E. J. at al., "A Functional FinFET-DGCMOS SRAM Cell", Int'l. Electron Devices Meeting, San Francisco, CA Dec. 8-11, 2002, 4 Pages.101Nowak, E. J. et al., "Scaling Beyond the 65 nm Node with FinFET-DGCMOSs", IEEE CICC, San Jose, CA Sep. 21-24, 2003, 4 Pages.102Nowak, Edward J. et al., "Turning Silicon on Its Edge", IEEE Circuits & Devices Magazine vol. 1, Jan./Feb. 2004, 12 Pages.103Office Action for Chinese Patent Application No. 200580009823.X mailed Jun. 21, 2010, 5 Pages.104Office Action for Chinese Patent Application No. 200680021817.0 mailed Jun. 12, 2009, 11 Pages.105Office Action for European Application No. 05711376.3 mailed Jan. 11, 2010, 5 Pages.106Office Action for European Patent Application No. 05711376.3 mailed Jan. 11, 2010, 5 Pages.107Office Action for German Patent Application No. 112006001735.7 mailed Oct. 20, 2009, 6 Pages.108Office Action for Korean Patent Application No. 10-2007-7030988 mailed Aug. 10, 2010, 5 Pages.109Office Action for U.S. Appl. No. 11/332,189 mailed Jul. 8, 2010, 12 Pages.110Office Action for U.S. Appl. No. 12/333,248 mailed Nov. 30, 2009, 24 Pages.111Office Action for United Kingdom Patent Application No. 0724762.0 mailed Jul. 15, 2010, 10 Pages.112Office Action from Chinese Patent Application No. 200680023301.X mailed Jun. 26, 2009, 21 Pages.113Office Action from European Patent Application No. 03817699.6 mailed Aug. 29, 2007, 3 Pages.114Office Action from Japanese Application No. 2006-549560 mailed Apr. 13, 2010, 8 Pages.115Office Action from PRC Application No. 200580007279.5, PCT/US05/ 000947, mailed Apr. 4, 2008, 2 Pages.116Office Action from Taiwan Patent Application No. 95122087 mailed Dec. 16, 2008, 14 Pages.117Office Action from Taiwan Patent Application No. 95122087 mailed Jun. 20, 2008, 8 Pages.118Office Action from Taiwan Patent Application No. 95123858, dated Oct. 9, 2008, 10 Pages.119Office Action from Taiwan Patent Application No. 95123858-translation, mailed Mar. 3, 2009, 10 Pages.120Office Action from Taiwan Patent Application No. 95123858�translation, mailed Mar. 3, 2009, 10 Pages.121Office Action from Taiwan Patent Application No. 95135820 mailed Jun. 4, 2009, 18 Pages.122Office Action from Taiwan Patent Application No. 95135820 mailed Oct. 22, 2009, 5 Pages.123Office Action from Taiwan Patent Application No. 95135820 mailed on Jan. 9, 2009, 14 Pages.124Office Action from Taiwanese Patent Application No. 095143047, mailed Mar. 18, 2010, 7 pgs.125Office Action from U.S. Appl. 11/234,014 mailed Jan. 23, 2008, 9 Pages.126Office Action from U.S. Appl. No. 10/227,068 mailed Dec. 18, 2006, 25 Pages.127Office Action from U.S. Appl. No. 10/703,316 mailed Dec. 15, 2006, 22 Pages.128Office Action from U.S. Appl. No. 11/080,765 mailed May 2, 2007, 47 Pages.129Office Action from U.S. Appl. No. 11/154,138 mailed Jun. 23, 2009, 14 Pages.130Office Action from U.S. Appl. No. 11/238,445 mailed Oct. 20, 2006, 22 Pages.131Office Action from U.S. Appl. No. 11/238,447 mailed Apr. 6, 2007, 19 Pages.132Office Action from U.S. Appl. No. 11/238,447 mailed Sep. 27, 2007, 9 Pages.133Office Action from U.S. Appl. No. 11/240,487 mailed Mar. 17, 2009, 13 Pages.134Office Action from U.S. Appl. No. 11/292,399 mailed Apr. 21, 2008, 21 pgs.135Office Action from U.S. Appl. No. 11/305,452 mailed Apr. 18, 2008, 7 Pages.136Office Action from U.S. Appl. No. 11/305,452 mailed Aug. 4, 2010, 7 Pages.137Office Action from U.S. Appl. No. 11/305,452 mailed Feb. 9, 2009, 8 Pages.138Office Action from U.S. Appl. No. 11/322,795 mailed Mar. 4, 2009, 12 Pages.139Office Action from U.S. Appl. No. 11/498,901 mailed Aug. 1, 2008, 13 Pages.140Office Action from U.S. Appl. No. 11/498,901 mailed Jun. 8, 2009, 9 Pages.141Office Action from U.S. Appl. No. 11/498,901 mailed Mar. 26, 2010, 14 Pages.142Office Action from U.S. Appl. No. 11/501,253 mailed Dec. 12, 2008, 8 Pages.143Office Action from U.S. Appl. No. 11/501,253 mailed May 14, 2008, 12 Pages.144Office Action from U.S. Appl. No. 11/649,545 mailed Aug. 17, 2010, 7 Pages.145Office Action from U.S. Appl. No. 11/649,545 mailed Sep. 23, 2009, 25 Pages.146Office Action from U.S. Appl. No. 11/855,823, mailed Dec. 30, 2008, 18 Pages.147Office Action from U.S. Appl. No. 12/025,665 mailed on Nov. 12, 2008, 21 Pages.148Ohsawa, Takashi at al., "Memory Design Using a One-Transistor Gain Cell on SOI", IEEE 37(11), Nov. 2002, 13 Pages.149Park, Donggun et al., 3-dimensional nano-CMOS Transistors to Overcome Scaling Limits, IEEE 2004, ISBN 0-7803-8511-X, 6 Pages.150Park, Jae-Hyoun et al., Quantum-Wired MOSFET Photodetector Fabricated by Conventional Photolighography on SOI Substrate, Nanotechnology, 4th IEEE Conference on Munich, Germany, Aug. 16-19, 2004, Piscataway, NJ, 3 Pages.151Park, Jong-Tae at al., "Pi-Gate SOI MOSFET", IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001, 2 Pages.152Park, K.Y., et al., "Device Characteristics of AIGaN/GaN MIS-HFET Using A/203-HfO3 Laminated High-k Dielectric", Japan Journ of Appl.Phys. vol. 43, 2004, 3 pgs.153Park, T. et al., "Fabrication of Body-Tied FinFETs (Omega MOSFETS) Using Bulk Si Wafers", 2003 Symposia on VLSI Technology Digest of Technical Papers, Jun. 2003, 2 Pages.154Park, T. et al., "PMOS Body-Tied FinFET (Omega MOSFET) Characteristics", IEEE Device Research Conference, Piscataway, NJ, Jun. 23-25, 2003, 2 Pages.155 *Passlack et al. "Self-Aligned GaAs p-Channel Enhancement Mode MOS Heterostructure Field-Effect Transistor," IEEE Electron Device Letters, 23, 2002, pp. 508-510.156Scholz, S. et al., "MOVPE growth of GaAs on Ge substrates by inserting a thin low temperature buffer layer", Cryst. Res, Technol. 41, No. 2, Jan. 15, 2006, 6 Pages.157Search Report and Written Opinion for European Patent Application No. 10184650.9 mailed Jan. 31, 2011, 18 Pages.158Second Office Action for Chinese Application No. 200680021817.0 mailed Dec. 11, 2009, 11 Pages.159Second Office Action from Chinese Patent Application No. 200580032314.9 mailed May 8, 2009, 14 Pages.160Second Office Action from Chinese Patent Application No. 200680044431.1, mailed Apr. 30, 2010, 3 pgs.161Seevinck, Evert et al., Static-Noise Margin Analysis of MOS SRAM Cells, IEEE, Journal of Solid-State Circuits, (SC-22)5, Oct. 1987, 7 Pages.162Sieg, R. M. et al,, "Toward device-quality GaAs growth by molecular beam epitaxy on offcut Ge/Si�Ge/Si substrates", J. Vac. Sci. Technol. B, vol. 16, No. 3, May/Jun. 1998. 4 Pages.163Stadele, M. et al., A Comprehensive Study of Corner Effects in Tri-gate Transistors, IEEE 2004, 4 Pages.164Stolk, Peter A. et al., Device Modeling Statistical Dopant Fluctuations in MOS Transistors, IEEE Transactions on Electron Devices, (45)9, 1997, 4 Pages.165Subramanian, V., "A Bulk-Si-Compatible Ultrathin-body SOI Technology for Sub-100m MOSFETS", Proceeding of the 57th Annual Device Research Conference, (1999), 2 Pages.166Sugizaki, T. et al., Novel Multi-bit SONOS Type Flash Memory Using a High-k Charge Trapping Layer, VLSI Technology, 2003. Digest of Technical Papers. Symposium on Jun. 10-12, 2003, 2 Pages.167Tanaka, T. et al., Scalability Study on a Capacitorless IT-DRAM: From Single-gate PD-SOI to Double-gate FinDRAM, IEEE, 2004, 4 Pages.168Tang, Stephen H. et al., FinFET�A Quasi-Planar Double-Gate MOSFET, IEEE International Solid-State Circuits Conference, Feb. 6, 2001, 3 Pages.169Third Office Action for Chinese Application No. 200580032314.9 mailed Jan. 29, 2010, 21 Pages.170Tokoro, Kenji et al., Anisotropic Etching Properties of Silicon in KOH and TMAH Solutions, International Symposium on Micromechatronics and Human Science, IEEE, 1998, 6 Pages.171Wan, A. et al., "Characterization of GaAs grown by molecular beam epitaxy on vicinal Ge (100) substrates", J. Vac. Sci. Technol, B, vol. 22, No. 4, Jul. 27, 2004, 6 Pages.172Wang, X. et al., "Band alignments in sidewall strained Si/strained SiGe heterostructures", May 28, 2002, 5 Pages.173Wolf, Stanley et al., Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, Sep. 1986, 3 Pages.174Written Opinion from Patent Application No. 2005070131 mailed Mar. 18, 2007, 4 Pages.175Written Opinion from Singapore Patent Application No. 200604766-6 mailed Apr. 4, 2008, 4 Pages.176Xiong, W, et al., Corner Effect in Multiple-Gate SOI MOSFETs, IEEE, 2003, 3 Pages.177Xiong, Weize et al., Improvement of FinFET Electrical Characteristics by Hydrogen Annealing, IEEE Electron Device Letters, 25(8), Aug. 2004, 3 Pages.178Yang, Fu-Liang et al., 5nm-Gate Nanowire FinFET, IEEE, 2004, 2 Pages.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8258543 *Dec 7, 2009Sep 4, 2012Intel CorporationQuantum-well-based semiconductor devicesUS8536621Aug 9, 2012Sep 17, 2013Intel CorporationQuantum-well-based semiconductor devicesUS8674408Apr 30, 2013Mar 18, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Reducing source/drain resistance of III-V based transistorsUS8748269Aug 16, 2013Jun 10, 2014Intel CorporationQuantum-well-based semiconductor devicesUS8816391Nov 10, 2009Aug 26, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Source/drain engineering of devices with high-mobility channelsUS20110133168 *Dec 7, 2009Jun 9, 2011Gilbert DeweyQuantum-well-based semiconductor devices* Cited by examinerClassifications U.S. Classification438/197, 257/E21.398, 438/287, 257/189, 438/216, 257/E21.451, 257/E21.386International ClassificationH01L21/336Cooperative ClassificationH01L29/7784, H01L21/3141, H01L21/314, H01L29/517, H01L29/513, H01L21/31616, H01L21/28008, H01L21/31645, H01L29/495, H01L29/2003, H01L29/66462European ClassificationH01L21/314, H01L21/314A, H01L29/778C2B, H01L29/51B2, H01L29/51M, H01L21/28E, H01L29/49D, H01L29/66M6T6E3RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services