Source: http://www.google.com/patents/US7839860?dq=6,049,612
Timestamp: 2017-06-29 04:27:52
Document Index: 364253044

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 200405099', 'Application No. 200405336', 'Application No. 200401969', 'Application No. 200401973', 'Application No. 200401979', 'Application No. 200402060', 'Application No. 200402061', 'Application No. 200401975', 'Application No. 200401969', 'Application No. 200410047784', 'Application No. 200410038432', 'Application No. 200410038546', 'application No. 200410044503', 'Application No. 200410071497', 'Application No. 04255786', 'Application No. 04252205', 'Application No. 04251582', 'Application No. 04252056', 'Application No. 04252202', 'Application No. 04252057', 'Application No. 04252203', 'Application No. 04252054', 'Application No. 04252055', 'Application No. 04255609', 'Application No. 04255611', 'Application No. 04251581', 'Application No. 04252054', 'Application No. 04252056', 'Application No. 04252057', 'Application No. 04252202', 'Application No. 04252203', 'Application No. 200402057', 'Application No. 04255609', 'Application No. 04252055', 'Application No. 200410044503', 'Application No. 10', 'Application No. 200410044503', 'Application No. 200410043419', 'Application No. 200410045686', 'Application No. 200410087460', 'Application No. 200410038545', 'Application No. 04252205', 'Application No. 200410038545', 'Application No. 200410095171', 'Application No. 200410043419', 'Application No. 200410071498', 'Application No. 2004100950502', 'Application No. 200410095171', 'Application No. 200410044503', 'Application No. 200401166', 'Application No. 08153454', 'Application No. 04255786', 'Application No. 04255610', 'Application No. 04255609', 'Application No. 08153726', 'Application No. 08155263', 'Application No. 08153724', 'Application No. 200405336', 'Application No. 08155262', 'Application No. 04255610', 'Application No. 200405115', 'Application No. 200405129']

Patent US7839860 - Packet based video display interface - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA packet based display interface arranged to couple a multimedia source device to a multimedia sink device is disclosed that includes a transmitter unit coupled to the source device arranged to receive a source packet data stream in accordance with a native stream rate, a receiver unit coupled to the...http://www.google.com/patents/US7839860?utm_source=gb-gplus-sharePatent US7839860 - Packet based video display interfaceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7839860 B2Publication typeGrantApplication numberUS 12/137,458Publication dateNov 23, 2010Filing dateJun 11, 2008Priority dateMay 1, 2003Fee statusPaidAlso published asUS20090010253Publication number12137458, 137458, US 7839860 B2, US 7839860B2, US-B2-7839860, US7839860 B2, US7839860B2InventorsOsamu KobayashiOriginal AssigneeGenesis Microchip Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (214), Non-Patent Citations (139), Referenced by (19), Classifications (18), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetPacket based video display interface
US 7839860 B2Abstract
1. A system on a chip, comprising:
an interface that communicates with at least one bi-directional auxiliary channel and at least one uni-directional main link, the interface arranged to provide a communication channel between a first device and a second device, the
first device having a first device transmitter unit,
the second device connected by way of the interface to the first device, wherein the second device includes at least a second device input transceiver unit arranged to receive data from the first device transmitter unit by way of the at least one bi-directional auxiliary channel and the at least one uni-directional main link of the interface and a second device output transceiver unit arranged to receive data from the second device input transceiver unit by way of a second device linking unit that includes at least a second device main channel and at least a second device auxiliary channel, wherein the second device output transceiver unit includes a number of transmitter units connected to a system interface that includes at least a system main link and a system auxiliary channel, wherein a selected transmitter unit sends data over the system interface to a receiving circuit.
2. A system as recited in claim 1, wherein the first device is coupled to a third device.
3. A system as recited in claim 2, wherein the third device is connected to the second device by way of a hub.
4. A system as recited in claim 1, wherein the number of transmitter units includes a DVI transmitter unit.
5. A system as recited in claim 1, wherein the number of transmitter units includes a LVDS transmitter unit.
6. A system as recited in claim 1, wherein the number of transmitter units includes a video DAC transmitter unit.
7. A method of transferring data on a chip from a first device through a second device to a receiving circuit comprising:
transferring the data from a first device transmitter unit included in the first device to a second device input transceiver unit included in the second device by way of at least one uni-directional main link and at least one bi-directional auxiliary link, which are included in an interface connecting the first device transmitter unit and the second device input transceiver unit;
transferring the data from the second device input transceiver unit to a second device output transceiver unit included in the second device by way of a second device linking unit that includes at least one second device main channel and at least one second device auxiliary channel, wherein the second device output transceiver unit includes a number of transmitter units connected to a system interface that includes at least one system main link and at least one system auxiliary link; and
transferring the data from a selected one of the number of transmitter units to the receiving circuit by way of the system interface.
8. The method as recited in claim 7, wherein the first device is coupled to a third device.
9. The method as recited in claim 8, wherein the third device is connected to the second device by way of a hub.
10. The method as recited in claim 7, wherein the number of transmitter units includes a DVI transmitter unit.
11. The method as recited in claim 7, wherein the number of transmitter units includes a LVDS transmitter unit.
12. The method as recited in claim 7, wherein the number of transmitter units includes a video DAC transmitter unit.
This application is a Continuation in Part of and claims priority to U.S. patent application Ser. No. 10/726,794 filed Dec. 2, 2003 entitled “PACKET BASED VIDEO DISPLAY INTERFACE AND METHODS OF USE THEREOF” by Kobayashi that, in turn, takes priority under 35 U.S.C. 119(e) to (i) U.S. Provisional Patent Application No. 60/467,804, filed on May 1, 2003 entitled “DIGITAL/ANALOG VIDEO INTERCONNECT AND METHODS OF USE THEREOF” by Kobayashi, (ii) U.S. Provisional Patent Application No. 60/504,060, filed on Sep. 18, 2003 entitled “DIGITAL/ANALOG VIDEO INTERCONNECT AND METHODS OF USE THEREOF” by Kobayashi, (iii) U.S. Provisional Patent Application No. 60/474,085 filed on May 28, 2003 entitled “DIGITAL/ANALOG VIDEO INTERCONNECT AND METHODS OF USE THEREOF” by Kobayashi, and (iv) U.S. Provisional Patent Application No. 60/474,084 filed on May 28, 2003 entitled “SIMPLE ENUMERATION METHOD FOR THE LINK CLOCK RATE AND THE PIXEL/AUDIO CLOCK RATE” by Kobayashi, each of which is hereby incorporated by reference herein in their entirety.
However, in recent years, the exploding growth of digital systems has made the use of digital capable cables such as Digital Visual Interface (DVI) cables more desirable. It is well known that DVI is a digital interface standard created by the Digital Display Working Group (DDWG). Data are transmitted using the transition minimized differential signaling (TMDS) protocol, providing a digital signal from the PC's graphics subsystem to the display. DVI handles bandwidths in excess of 160 MHz and thus supports UXGA and HDTV with a single set of links.
Therefore, it would be desirable to have a digital interface that is more cost effective than current interfaces for coupling video sources and video displays. In some cases, the digital interface would also be backward compatible with analog video, such as VGA.
A system, comprising an interface that includes at least one bi-directional auxiliary channel and at least one uni-directional main link, a first device having a first device transmitter unit, a second device connected by way of the interface to the first device, wherein the second device includes at least a second device input transceiver unit arranged to receive data from the first device transmitter unit by way of the interface and a second device output transceiver unit arranged to receive data from the second device input transceiver unit by way of a second device linking unit that includes at least a second device main channel and at least a second device auxiliary channel, wherein the second device output transceiver unit includes a number of transmitter units connected to a system interface that includes at least a system main link and a system auxiliary channel, wherein a selected transmitter unit sends data over the system interface to a receiving circuit.
FIGS. 2A-2C illustrate a video interface system that is used to connect a video source and a video display unit in accordance with a number of embodiments of the invention.
FIG. 6 shows a high-level diagram of the multiplexed main link stream as an example of the stream shown in FIG. 5A.
FIG. 7 shows another example of a data stream in accordance with the invention.
FIGS. 27A and 27B show a flowchart for a link set up process in accordance with an embodiment of the invention.
For example, FIG. 1 shows a generalized representation of a cross platform packet based digital video display interface 100 in accordance with an embodiment of the invention. The interface 100 connects a transmitter 102 to a receiver 104 by way of a physical link 106 (also referred to as a pipe). In the described embodiment, a number of data streams 108-112 are received at the transmitter 102 that, if necessary, packetizes each into a corresponding number of data packets 114. These data packets are then formed into corresponding data streams each of which are passed by way of an associated virtual pipe 116-120 to the receiver 104. It should be noted that the link rate (i.e., the data packet transfer rate) for each virtual link can be optimized for the particular data stream resulting in the physical link 106 carrying data streams each having an associated link rate (each of which could be different from each other depending upon the particular data stream). The data streams 108-112 can take any number of forms such as video, graphic, audio, etc.
Typically, when the source is a video source, the data streams 108-112 include various video signals that can have any number and type of well-known formats, such as composite video, serial digital, parallel digital, RGB, or consumer digital video. The video signal can be an analog video signal provided the source 102 includes some form of an analog video source such as for example, an analog television, still camera, analog VCR, DVD player, camcorder, laser disk player, TV tuner, set top box (with satellite DSS or cable signal) and the like. The source 102 can also include a digital image source such as for example a digital television (DTV), digital still camera, and the like. The digital video signal can be any number and type of well known digital formats such as, SMPTE 274M-1995 (1920×1080 resolution, progressive or interlaced scan), SMPTE 296M-1997 (1280×720 resolution, progressive scan), as well as standard 480 progressive scan video.
For example, if the data stream 110 is an analog type signal, then an analog to digital converter (not shown) included in or coupled to the transmitter 102 will digitize the analog data which is then packetize by a packetizer that converts the digitized data stream 110 into a number of data packets 114 each of which will be transmitted to the receiver 104 by way of the virtual link 116. The receiver 104 will then reconstitute the data stream 110 by appropriately recombining the data packets 114 into their original format. It should be noted that the link rate is independent of the native stream rates. The only requirement is that the link bandwidth of the physical link 106 be higher than the aggregate bandwidth of data stream(s) to be transmitted. In the described embodiment, the incoming data (such as pixel data in the case of video data) is packed over the respective virtual link based upon a data mapping definition. In this way, the physical link 106 (or any of the constituent virtual links) does not, as does conventional interconnects such as DVI, carry one pixel data per link character clock.
FIG. 2 illustrates a system 200 based upon the system 100 shown in FIG. 1 that is used to connect a video source 202 and a video display unit 204. In the illustrated embodiment, the video source 202 can include either or both a digital image (or digital video source) 206 and an analog image (or analog video source) 208. In the case of the digital image source 206, a digital data stream 210 is provided to the transmitter 102 whereas in the case of the analog video source 208, an A/D converter unit 212 coupled thereto, converts an analog data stream 213 to a corresponding digital data stream 214. The digital data stream 214 is then processed in much the same manner as the digital data stream 210 by the transmitter 102. The display unit 204 can be an analog type display or a digital type display or in some cases can process either analog or digital signals provided thereto. In any case, the display unit 204 includes a display interface 216 that interfaces the receiver 104 with a display 218 and a D/A converter unit 220 in the case of an analog type display. In the described embodiment, the video source 202 can take any number of forms (such as a personal desktop computer, digital or analog TV, set top box, etc.) whereas the video display unit 204 can take the form of a video display (such as an LCD type display, CRT type display, etc.).
In the described embodiment, a main link data rate is chosen whose bandwidth exceeds the aggregate bandwidth of the constituent virtual links. Data sent to the interface arrives at the transmitter at its native rate. A time-base recovery (TBR) unit 226 within the receiver 104 regenerates the stream's original native rate using time stamps embedded in the main link data packets, if necessary. It should be noted, however, that for appropriately configured digital display devices 232 shown in FIG. 2B, time base recovery is unnecessary since display data is be sent to the display driver electronics at the link character clock rate, thereby greatly reducing the number of channels required with a commensurate reduction in complexity and cost for the display. For example, FIG. 2C illustrates an exemplary LCD panel 232 configured in such a way that no time base recovery is necessary since display data is essentially pipelined to the various column drivers 234 that are used in combination with row drivers 236 to drive selected display elements 238 in the array 240.
Pixel clock rate=2A*3B×5C×11D A=4 bits, B=2 bits, C=3 bits, and D=1 bit.
Even for a link whose link rate (which is the serial link bit rate/10 for a link that uses 10-bit character such as 8B/10B characters) may be different from the pixel clock rate, there is a benefit in defining the link rate with these four parameters, A′, B′, C′, and D′: The benefit is the simplicity in regenerating pixel/audio clocks from a link clock. For example, let's say the link rate is set as A′=6, B′=3, C′=7, and D′=0 and the corresponding link rate is 135 MHz. However, suppose the pixel clock rate is set as A=8, B=3, C=6, and D=0 (=108 MHz), then the pixel clock can be generated from link clock as pixel clock rate is equal to the link rate*22/5 1.
Freq_native=Freq_link_char*(TS19−0)/220 Eq (1)
It should be noted that, no time stamp is communicated for an audio stream. In this case, the source device informs the display device of the audio sample rate and number of bits per sample. By determining the audio rate based upon Eq (2) and the link character rate, the display device regenerates the original audio stream rate.
Audio rate=(audio sample rate)×(# bits per sample)×(# channels) Eq (2)
A main link data packet 400 shown in FIG. 4A includes a main link packet header 402 as shown in FIG. 4B that is formed of 16 bits where bits 3-0 are the Stream ID (SID) (indicating that maximum stream count is 16), bit 4 is the Time Stamp (TS) LSB. When bit 4 is equal to 1, this packet header has the least significant 4 bits of Time Stamp value (used only for uncompressed video stream). Bit 5 is a Video frame sequence bit which acts as the least significant bit of the frame counter which toggles from “0” to “1” or from “1” to “0” at the video frame boundary (used only for uncompressed video stream). Bits 7 and 6 are reserved whereas bits 8 through 10 are a 4-bit CRC (CRC) that checks errors for the previous eight bits. Bits 12-15 are Time Stamp/Stream ID Inversion. (TSP/SIDn) which for uncompressed video are used as four bits of 20-bit Time Stamp value.
FIG. 6 shows a high-level diagram of the multiplexed main link stream 600 as an example of the stream 510 shown in FIG. 5A when three streams are multiplexed over the main link 222. The three streams in this example are: UXGA graphics (Stream ID=1), 1280×720p video (Stream ID=2), and audio (Stream ID=3). The small packet header size of main link packet 400 minimizes the packet overhead, which results in the very high link efficiency. The reason the packet header can be so small is that the packet attributes are communicated via the auxiliary channel 224 prior to the transmission of the packets over main link 222.
Generally speaking, the sub-packet enclosure is an effective scheme when the main packet stream is an uncompressed video since an uncompressed video data stream has data idle periods corresponding to the video-blanking period. Therefore, main link traffic formed of an uncompressed video stream will include a series of Null special character packets during this period. By capitalizing on the ability to multiplex various data streams, certain implementations of the present invention use various methods to compensate for differences between the main link rate and the pixel data rate when the source stream is a video data stream. For example, as illustrated in FIG. 7, the pixel data rate is 0.5 Gb/sec, such that a bit of pixel data is transmitted every 2 ns. In this example, the link rate has been set to 1.25 Gb/sec, such that a bit of pixel data is transmitted each 0.8 ns. Here, transmitter 102 intersperses special characters between pixel data as illustrated in FIG. 8. Two special characters are disposed between a first bit of pixel data P1 and a second bit of pixel data P2. The special characters allow receiver 104 to distinguish each bit of pixel data. Interspersing the special characters between bits of pixel data also creates a steady stream of data that allows the link to maintain synchronization. In this example, the special characters are Null characters. No line buffer is needed for such methods, only a small FIFO, because the link rate is sufficiently fast. However, relatively more logic is required on the receiving side to reconstruct the video signal. The receiver needs to recognize when the special characters begin and end.
The single bi-directional auxiliary channel 224 provides a conduit for various support functions useful for link set up and supporting main link operations as well as to carry auxiliary application data such as USB traffic. For example, with the auxiliary channel 224, a display device can inform the source device of events such as sync loss, dropped packets and the results of training sessions (described below). For example, if a particular training session fails, the transmitter 102 adjusts the main link rate based upon pre-selected or determined results of the failed training session. In this way, the closed loop created by combining an adjustable, high speed main link with a relatively slow and very reliable auxiliary channel allows for robust operation over a variety of link conditions. It should be noted that in some cases (an example of which is shown in FIG. 5B), a logical bi-directional auxiliary channel 520 can be established using a portion 522 of the bandwidth of the main link 222 to transfer data from the source device 202 to the sink device 204 and a uni-directional back channel 524 from the sink device 204 to the source device 202. In some applications, use of this logical bi-directional auxiliary channel may be more desirable than using a half-duplex bi-directional channel described in FIG. 5A.
In addition to providing a training session conduit, the auxiliary channel 224 can be also used to carry main link packet stream descriptions thereby greatly reducing the overhead of packet transmissions on the main link 222. Furthermore, the auxiliary channel 224 can be configured to carry Extended Display Identification Data (EDID) information replacing the Display Data Channel (DDC) found on all monitors (EDID is a VESA standard data format that contains basic information about a monitor and its capabilities, including vendor information, maximum image size, color characteristics, factory pre-set timings, frequency range limits, and character strings for the monitor name and serial number. The information is stored in the display and is used to communicate with the system through the DDC which sits between the monitor and the PC graphics adapter. The system uses this information for configuration purposes, so the monitor and system can work together). In what is referred to as an extended protocol mode, the auxiliary channel can carry both asynchronous and isochronous packets as required to support additional data types such as keyboard, mouse and microphone.
In the described embodiment, the source device physical layer 1202 includes an electrical sub layer 1202-2 and a logical sub layer 1202-1. The electrical sub layer 1202-2 includes all circuitry for interface initialization/operation such as hot plug/unplug detection circuit, drivers/receivers/termination resistors, parallel-to-serial/serial-to-parallel conversions, and spread-spectrum-capable PLL's. The logical sub layer 1202-1 includes circuitry for, packetizing/de-packetizing, data scrambling/de-scrambling, pattern generation for link training, time-base recovery circuits, and data encoding/decoding such as 8B/10B (as specified in ANSI X3.230-1994, clause 11) that provides 256 link data characters and twelve control characters (an example of which is shown as FIG. 13) for the main link 222 and Manchester II for the auxiliary channel 224 (see FIG. 14).
It should be noted that the 8B/10B encoding algorithm is described, for example, in U.S. Pat. No. 4,486,739, which is hereby incorporated by reference. As known by those of skill in the art, the 8B/10B code is a block code that encodes 8-bit data blocks into 10-bit code words for serial transmission. In addition, the 8B/10B transmission code converts a byte wide data stream of random 1s and 0s into a DC balanced stream of 1s and 0s with a maximum run length of 5. Such codes provide sufficient signal transitions to enable reliable clock recovery by a receiver. Moreover, a DC balanced data stream proves to be advantageous for fiber optic and electromagnetic wire connections. The average number of 1s and 0s in the serial stream is be maintained at equal or nearly equal levels. The 8B/10B transmission code constrains the disparity between the number of 1s and 0s to be −2, 0, or 2 across 6 and 4 bit block boundaries. The coding scheme also implements additional codes for signaling, called command codes.
Since data stream attributes are transmitted over the auxiliary channel 224, the main link packet headers serve as stream identification numbers thereby greatly reducing overhead and maximizing link bandwidth. It should also be noted that neither the main link 222 nor the auxiliary link 224 has separate clock signal lines. In this way, the receivers on main link 222 and auxiliary link 224 sample the data and extract the clock from the incoming data stream. Fast phase locking for any phase lock loop (PLLs) circuit in the receiver electrical sub layer is important since the auxiliary channel 224 is half-duplex bi-directional and the direction of the traffic changes frequently. Accordingly, the PLL on the auxiliary channel receiver phase locks in as few as 16 data periods thanks to the frequent and uniform signal transitions of Manchester II (MII) code
At link set up time, the data rate of main link 222 is negotiated using the handshake over auxiliary channel 224. During this process, known sets of training packets are sent over the main link 222 at the highest link speed. Success or failure is communicated back to the transmitter 102 via the auxiliary channel 224. If the training fails, main link speed is reduced and training is repeated until successful. In this way, the source physical layer 1202 is made more resistant to cable problems and therefore more suitable for external host to monitor applications. However, unlike conventional display interfaces, the main channel link data rate is decoupled from the pixel clock rate. A link data rate is set so that link bandwidth exceeds the aggregate bandwidth of the transmitted streams.
The source link layer 1204 handles the link initialization and management. For example, upon receiving a hot plug detect event generated upon monitor power-up or connection of the monitor cable from the source physical layer 1202, the source device link layer 1204 evaluates the capabilities of the receiver via interchange over the auxiliary channel 224 to determine a maximum main link data rate as determined by a training session, the number of time-base recovery units on the receiver, available buffer size on both ends, availability of USB extensions and then notifies the stream source 1206 of an associated hot plug event. In addition, upon request from the stream source 1206, the source link layer 1204 reads the display capability (EDID or equivalent). During a normal operation, the source link layer 1204 sends the stream attributes to the receiver 104 via the auxiliary channel 224, notifies the stream source 1206 whether the main link 222 has enough resource for handling the requested data streams, notifies the stream source 1206 of link failure events such as sync loss and buffer overflow, and sends MCCS commands submitted by the stream source 1206 to the receiver via the auxiliary channel 224. All communications between the source link layer 1204 and the stream source/sink use the formats defined in the application profile layer 1214.
For example, the display device application profile layer (APL) 1216 is essentially an application-programming interface (API) describing the format for Stream Source/Sink communication over the main link 222 that includes a presentation format for data sent to or received from the interface 100. Since some aspects of the APL 1216 (such as the power management command format) are baseline monitor functions, they are common to all uses of the interface 100. Whereas other non-baseline monitor functions, such as data mapping format and stream attribute format, are unique to an application or a type of isochronous stream that is to be transmitted. Regardless of the application, the stream source 1206 queries the source link layer 1204 to ascertain whether the main link 222 is capable of handling the pending data stream(s) prior to the start any packet stream transmission on the main link 222.
When it is determined that the main link 222 is capable of supporting the pending packet stream(s), the stream source 1206 sends stream attributes to the source link layer 1204 that is then transmitted to the receiver over the auxiliary channel 224. These attributes are the information used by the receiver to identify the packets of a particular stream, to recover the original data from the stream and to format it back to the stream's native data rate. The attributes of the data stream are application dependent.
In those cases where the desired bandwidth is not available on the main link 222, the stream source 1206 may take corrective action by, for example, reducing the image refresh rate or color depth.
The display device physical layer 1208 isolates the display device link layer 1210 and the display device APL 1216 from the signaling technology used for link data transmission/reception. The main link 222 and the auxiliary channel 224 have their own physical layers, each consisting of a logical sub layer and an electrical sub layer that includes the connector specification. For example, the half-duplex, bi-directional auxiliary channel 224 has both a transmitter and a receiver at each end of the link as shown in FIG. 15. An auxiliary link transmitter 1502 is provided with link characters by a logical sub layer that are then serialized and transmitted to a corresponding auxiliary link receiver 1504. The receiver 1504, in turn, receives serialized link character from the auxiliary link 224 and de-serializes the data at a link character clock rate. It should be noted that the major functions of the source logical sub layers include signal encoding, packetizing, data scrambling (for EMI reduction), and training pattern generation for the transmitter port. While for the receiver port, the major functions of the receiver logical sub layer includes signal decoding, de-packetizing, data de-scrambling, and time-base recovery.
Still referring to FIG. 15, the auxiliary channel electrical sub layer contains the transmitter 1502 and the receiver 1504. The transmitter 1502 is provided with link characters by the logical sub layer, which it serializes and transmits out. The receiver 1504 receives serialized link characters from the link layer and subsequently de-serializes them at a link character clock rate. The positive and negative signals of auxiliary channel 224 are terminated to ground via 50-ohm termination resistors at each end of the link as shown. In the described implementation, the drive current is programmable depending on the link condition and ranges from approximately 8 mA to approximately 24 mA resulting in a range of Vdifferential_pp of approximately 400 mV to approximately 1.2V. In electrical idle modes, neither the positive nor the negative signal is driven. When starting transmission from the electrical idle state, the SYNC pattern must be transmitted and the link reestablished. In the described embodiment, the SYNC pattern consists of toggling the auxiliary channel differential pair signals at clock rate 28 times followed by four 1's in Manchester II code. The auxiliary channel master in the source device detects hot-plug and hot-unplug events by periodically driving or measuring the positive and negative signals of auxiliary channel 224.
As shown, the cable takes the form of a set of twisted pair wires, one for each of the Red (R), Green (G), and Blue (B) video signals provided in a typical RGB color based video system (such as PAL based TV systems). As known by those of skill in the art, twisted pair cable is a type of cable that consists of two independently insulated wires twisted around one another. It should be noted that in some other systems, the signals could also be component based signals (Pb, Pr, Y) used for NTSC video TV systems. Within the cable, each twisted pair is individually shielded. Two pins for +12V power and ground are provided. The characteristics impedance of each differential pair is 100 ohms+/−20%. The entire cable is also shielded. This outer shield and individual shields are shorted to the connector shells on both ends. The connector shells are shorted to ground in a source device. A connector 1700 as shown in FIG. 17 has 13 pins in one row having a pinout that is identical both for the connector on the source device end and that on the display device end. The source device supplies the power.
If at the state 1806 a display hot unplug event is detected, then the system transitions back to the standby state 1804. Otherwise the source drives the auxiliary channel with a positive and negative signal to wake up receiver and the receiver's subsequent response, if any, is checked. If there is no response received, then the receiver has not woken up and source remains in the state 1806. If, however, a signal is received from the display, then the display has woken up and the source is ready to read the receiver link capabilities (such as max link rate, buffer size, and number of time-base recovery units) and the system transitions to a main link initialization state 1808 and is ready to commence a training start notification phase.
At this point, a training session is started by sending a training pattern over the main link at a set link rate and checks an associated training status. The receiver sets a pass/fail bit for each of three phases and the transmitter will proceed to the next phase upon detection of pass only such that when a pass is detected, the main link is ready at that link rate. At this point, the interface transitions to a normal operation state 1810, otherwise, the link rate is reduced and the training session is repeated. During the normal operation state 1810, the source continues to periodically monitor a link status index, which if fails, a hot unplug event is detected and the system transitions to the standby state 1804 and waits for a hot plug detection event. If, however, a sync loss is detected, then the system transitions to state 1808 for a main link re-initiation event.
FIG. 20 shows a PC motherboard 2000 having an on-board graphics engine 2002 that incorporates a transmitter 2004 in accordance with the invention. It should be noted that the transmitter 2004 is a particular example of the transmitter 102 shown in FIG. 1. In the described embodiment, the transmitter 2004 is coupled to an connector 2006 (along the lines of the connector 1700) mounted on the motherboard 2000 which in turn is connected to a display device 2008 by way of a twisted pair cable 2010 coupled with a display device 2010.
As known in the art, PCI Express (developed by Intel Corporation of Santa Clara, Calif.) is a high-bandwidth, low pin count, serial, interconnect technology that also maintains software compatibility with existing PCI infrastructure. In this configuration, the PCI Express port is augmented to become compliant with the requirements of the cross platform interface which can directly drive a display device using a motherboard mounted connector as shown.
In situations where it is not practical to mount the connector on the motherboard, the signals can be routed through the SDVO slot of the PCI Express motherboard and brought to the back of the PC using a passive card connector as shown in FIG. 21. As is the case with the current generation of add-in graphics cards, a add-in graphics card can supplant the onboard graphics engine as shown in FIG. 22.
In the case of notebook applications, the transmitter on the motherboard graphics engine would drive through internal cabling, an integrated receiver/TCON which would drive the panel directly. For the most cost effective implementation, the receiver/TCON would be mounted on the panel thereby reducing the number of interconnect wires to 8 or 10 as shown in FIG. 23 All of the above examples assume integrated transmitters. However, is it quite feasible to implement as a standalone transmitter integrating into PCI and PCI Express environments through the AGP or SDVO slots, respectively, as shown in FIG. 24. A standalone transmitter will enable output streams without any change in graphics hardware or software.
FIG. 25 shows a flowchart detailing a process 2500 for determining an operational mode of the interface 100 in accordance with an embodiment of the invention. In this process, the operational mode will only be set to a digital mode if the video source and the display device are both digital. Otherwise, the operational mode will be set to analog mode. It should be noted that “analog mode” in this context can include both conventional VGA mode as well as enhanced analog mode having differential analog video with embedded alignment signal and bi-directional sideband. This enhanced analog mode will be described below.
FIG. 26 shows a flowchart detailing a process for providing a real time video image quality check in accordance with some aspects of the invention. In this example, all determinations of the process are made by a processor coupled to the display interface.
However, if the bit error rate is determined to be greater than the threshold value in step 2606, a determination is made (step 2608) as to whether the bit rate is greater than a minimum bit rate. If the bit rate is greater than a minimum bit rate, then the bit rate is lowered (step 2610) and the process returns to step 2604. If the bit rate is not greater than the minimum bit rate, then the mode is changed to analog mode (step 2612) and the process ends.
FIGS. 27A and 27B show a flowchart for a link set up process 2700 in accordance with an embodiment of the invention. The process 2700 begins at 2702 by the receiving of a hot plug detection event notification. At 2704 a main link inquiry is made by way of an associated auxiliary channel to determine a maximum data rate, a number of time base recovery units included in a receiver, and available buffer size. Next, at 2706, the maximum link data rate is verified by way of a training session and at 2708, a data stream source is notified of the hot plug event. At 2710, the capabilities of the display (using EDID, for example) are determined by way of the auxiliary channel and the display responds to the inquires at 2712 which, in turn, results a collaboration of the main link training session at 2714.
Next, at 2716, the stream source sends stream attributes to the receiver by way of the auxiliary channel and at 2718, the stream sources are further notified whether the main link is capable of supporting the requested number of data streams. At 2720, the various data packets are formed by adding associated packet headers and the multiplexing of a number of source streams is scheduled at 2722. At 2724 a determination is made whether or not the link status is OK. When the link status is not OK, then the source(s) are notified of a link failure event at 2726, otherwise, the link data streams are reconstructed into the native streams based upon the various packet headers at 2730. At 2732, the reconstructed native data streams are then passed to the display device.
FIG. 28 shows a flowchart detailing a process 2800 for performing a training session in accordance with an embodiment of the invention. It should be noted that the training session process 2800 is one implementation of the operation 2706 described in FIG. 27A. A training session is started at 2802 by sending a training pattern over the main link at a set link rate to the receiver. A typical link training pattern is shown in FIG. 11 in accordance with an embodiment of the invention. As illustrated, during the training session, a phase 1 represents the shortest run length while phase 2 is the longest. The receiver is to use these two phases to optimize the equalizer. In phase 3, both bit lock and character lock are achieved as long as the link quality is reasonable. At 2804, the receiver checks an associated training status and based upon the training status check, the receiver sets a pass/fail bit for each of three phases and the transmitter at 2806. At each phase, the receiver will proceed to the next phase upon detection of pass only and at 2810 and if the receiver does not detect a pass then the receiver reduces the link rate and repeats the training session. The main link is ready at that link rate at which a pass is detected at 2812.
FIG. 29 illustrates a computer system 2900 employed to implement the invention. Computer system 2900 is only an example of a graphics system in which the present invention can be implemented. Computer system 2900 includes central processing unit (CPU) 2910, random access memory (RAM) 2920, read only memory (ROM) 2925, one or more peripherals 2930, graphics controller 2960, primary storage devices 2940 and 2950, and digital display unit 2970. As is well known in the art, ROM acts to transfer data and instructions uni-directionally to the CPUs 2910, while RAM is used typically to transfer data and instructions in a bi-directional manner. CPUs 2910 may generally include any number of processors. Both primary storage devices 2940 and 2950 may include any suitable computer-readable media. A secondary storage medium 2990, which is typically a mass memory device, is also coupled bi-directionally to CPUs 2910 and provides additional data storage capacity. The mass memory device 2990 is a computer-readable medium that may be used to store programs including computer code, data, and the like. Typically, mass memory device 2990 is a storage medium such as a hard disk or a tape which generally slower than primary storage devices 2940, 2950. Mass memory storage device 2990 may take the form of a magnetic or paper tape reader or some other well-known device. It will be appreciated that the information retained within the mass memory device 2990, may, in appropriate cases, be incorporated in standard fashion as part of RAM 2920 as virtual memory.
CPUs 2910 are also coupled to one or more input/output devices 2980 that may include, but are not limited to, devices such as video monitors, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, or other well-known input devices such as, of course, other computers. Finally, CPUs 2910 optionally may be coupled to a computer or telecommunications network, e.g., an Internet network or an intranet network, using a network connection as shown generally at 2995. With such a network connection, it is contemplated that the CPUs 2910 might receive information from the network, or might output information to the network in the course of performing the above-described method steps. Such information, which is often represented as a sequence of instructions to be executed using CPUs 2910, may be received from and outputted to the network, for example, in the form of a computer data signal embodied in a carrier wave. The above-described devices and materials will be familiar to those of skill in the computer hardware and software arts.
FIG. 30 shows a system 3000 in accordance with an embodiment of the invention. System 3000 includes first device 3002 connected to second device 3004 by way interface 3006. It should be noted that interface 3006 can be implemented along the lines discussed with regards to FIGS. 1 and 2 above. First device 3002 includes transmitter unit 3008 coupled to transceiver unit 3010 by way of linking unit 3012 that includes at least a uni-directional main link and an auxiliary channel. In the described embodiment, transceiver unit 3010 can receive data from transmitter unit 3008 by way of linking unit 3012. Transceiver unit 3010 can, in turn, pass any received data to transceiver unit 3016 by way of linking unit 3018 (that can also include at least a unidirectional main link and at least an auxiliary channel). In the described embodiment, transceiver unit 3016 can include a number of transmitter modules each of which can transmit a selected data stream by way of unidirectional links 3020 to an appropriate sink device (not shown). For example, transceiver unit 3016 can include transmitter 102 as well as a DVI type transmitter, a LVDS type transmitter as well as a Video DAC in those cases where the sink device is analog in nature. It should be noted that in some situations, it may be advantageous to configure first device 3002 as a bridge type device coupled to third device 3022. In this case, third device 3022 can communicate with second device 3004 by way of hub 3026.
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