Source: http://www.google.es/patents/US8072837?dq=flatulence
Timestamp: 2013-05-24 03:23:37
Document Index: 163283249

Matched Legal Cases: ['Application No. 95', 'Application No. 95', 'Application No. 95', 'Application No. 95', 'Application No. 95', 'Application No. 95', 'Application No. 95']

Patente US8072837 - Circuit providing load isolation and memory domain translation for memory module - Google PatentesB�squeda Im�genes Maps Play YouTube Noticias Gmail Drive M�s » B�squeda avanzada de patentes | Historial web | Iniciar sesi�n B�squeda avanzada de patentesPatentesA circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select...http://www.google.es/patents/US8072837?utm_source=gb-gplus-sharePatente US8072837 - Circuit providing load isolation and memory domain translation for memory module N�mero de publicaci�nUS8072837 B1Tipo de publicaci�nConcesi�n N�mero de solicitud12/981,380 Fecha de publicaci�n6 Dic 2011 Fecha de presentaci�n29 Dic 2010 Fecha de prioridad5 Mar 2004Tambi�n publicado comoUS7881150US7916574US8081536US20100128507US20110085406 InventoresJayesh R. BhaktaJeffrey C. Solomon Cesionario originalNetlist, Inc. Clasificaci�n de EE.UU.365/230.6365/149365/233.13365/230.3365/51 Clasificaci�n internacionalG11C8/00 Clasificaci�n cooperativaG11C5/04 Clasificaci�n europeaG11C5/04ReferenciasCitas de patentes (104)Otras citas (162)Enlaces externosUSPTO Cesi�n de USPTO EspacenetCircuit providing load isolation and memory domain translation for memory moduleUS 8072837 B1 Resumen A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals. The circuit is further configurable to monitor command signals received by the memory module, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals, and to provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.
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