Source: https://patents.google.com/patent/US4850019
Timestamp: 2018-07-18 01:19:10
Document Index: 801288626

Matched Legal Cases: ['art 13', 'art 15', 'art 15', 'art 21', 'art 21', 'art 22', 'art 23', 'art 24', 'art 67', 'art 78', 'art 78', 'art 78', 'art 78', 'art 80', 'arts 81', 'arts 81', 'arts 81', 'arts 84', 'arts 84', 'arts 81', 'arts 78', 'arts 84']

US4850019A - Data randomization equipment - Google Patents
Data randomization equipment Download PDF
US4850019A
US4850019A US06926043 US92604386A US4850019A US 4850019 A US4850019 A US 4850019A US 06926043 US06926043 US 06926043 US 92604386 A US92604386 A US 92604386A US 4850019 A US4850019 A US 4850019A
US06926043
Input data is split by a splitting part into a plurality of block data having an equal data length to be processed through respective channels. Each channel data is subjected in a function operation part to a function operation in direct or indirect relation to all the other channel data to produce new channel data. Each channel data is subjected in a transform operation part to a transform operation to produce new channel data. All final channel data obtained after function and transform operations are combined by a combining part to obtain randomized data.
This invention relates to a data randomization equipment for randomizing digital data and to be used for random number generators for generating random numbers of digital data and for encrypting and decrypting processes of cryptographic equipment.
Exclusive OR part 13 takes exclusive OR between each bit of the expanded 48-bit data and a corresponding bit of 48-bit parameter data. The resultant 48-bit data is split into 8 blocks each of 6 bits, and these data blocks are fed to respective ROMs 141 to 148 which are commonly termed S boxes. The S boxes 141 to 148 each provide 4-bit data using the 6-bit input data as an address. The 32-bit data constituting the outputs of all the S boxes 141 to 148 is fed to a permutation part 15 constituted by a wired circuit. The permutation part 15 effects bit position re-arrangement of the 32-bit input data and yields the resultant output as a randomized output.
In this prior art equipment, with a change in the input to each of the S boxes 141 to 148, only one bit at the least to 4 bits at the most of the output undergo a change from "0" to "1" or from "1" to "0", that is, 2.5 bits, in average, of the output are changed. This means that with the occurrence of the change of one bit in the input data to the prior art data randomization equipment, only one bit in the least to 8 bits at the most, i.e., only 4 bits in average, of the 32-bit output data are changed. Further, with a change of one bit of the parameter data to this equipment only 2.5 bits of the output data are changed.
An object of the invention is to provide a data randomization equipment, in which nearly one half of the output data bits are changed with a change of one bit or a very small number of bits of the input data.
FIG. 1 is a view showing a concept of data randomization equipment;
FIG. 3 shows an example of the arrangement of the equipment according to the invention. Input data R is split by a splitting part 21 into a plurality of blocks each with a data length of n bits. The individual block data obtained from the splitting part 21 are processed as channel data through respective processing channels 25 to 28. In each of the processing channels, the channel data is processed through at least one function operation part 22 and, upon request, a transform part 23. The outputs of the individual channels 25 to 28 are combined by combining part 24 to be yielded as output data.
______________________________________1st step: R1 ← R1 ⊕ P0 ⊕ R0 in circuits 31 and 32     R2 ← R2 ⊕ P1 ⊕ R3 in circuits 35 and 362nd step: R1 ← (R1 + 1 + R2) mod 256 in circuit 333rd step: R1 ← cir R1 in circuit 344th step: R2 ← (R1 + R2) mod 256 in circuit 375th step: R2 ← cir R2 in circuit 386th step: R0 ← (R0 + R1) mod 256 in circuit 29     R3 ← (R3 + R2 + 1) mod 256 in circuit 397th step: R0 ← cir R0 in circuit 30     R3 ← cir R3 in circuit 41______________________________________
______________________________________1st step:   R1 ← ((R0 ⊕ P0) + R1 + 1) mod 256 in circuits   33 and 632nd step:   R1 ← cir R1 in circuit 343rd step:   R0 ← ((R0 + (R1 ⊕ P1)) mod 256 in circuits   29 and 644th step:   R0 ← cir R0 in circuit 30______________________________________
FIG. 9 shows an arrangement for randomizing input data without use of any external parameter data. In this instance, 64-bit input data is split by splitting part 67 into left and right block data each of 32 bits. The block data are fed to a first one of a plurality of cascade-connected randomization stages 76. In each randomization stage, right data is fed as left data input to the next randomization stage 76, and it is also fed to EOR circuit 77. Randomizing part 78 randomizes left data with the output of the EOR circuit 77 used as internal parameter data. The output of the randomizing part 78 is fed as right data to the next randomization stage 76. Suitable constant D0 is fed to the EOR circuit 77 in the first randomization stage 76, while in each of the following randomization stages, left data input to the immediately preceding randomization stage is fed to the EOR 77. The randomizing part 78 of each randomization stage 76 provides 32-bit data as part of 192-bit output data. This means that the 64-bit input data is expanded into 192 bits while it is randomized. The randomizing part 78 may be any one of the arrangements of FIGS. 3 to 6 described above.
The arrangement of FIG. 8 uses four randomization stages, but it of course is possible to provide a different number of randomization stages. FIG. 10 shows a 6-stage arrangement. In FIG. 10, parts corresponding to those in FIG. 8 are designated by like reference numerals, and their description is omitted. FIG. 11 shows an example of data randomization equipment for obtaining intermediate keys corresponding to a secret key in a case where the data randomization equipment of FIG. 10 is used for a cryptographic equipment. In this instance, the input secret key is 128-bit data, which is split in splitting part 80 into two block data each of 64 bits. The two block data are further split in splitting parts 81 and 82 into sub-block data each of 32 bits. The two right sub-block data obtained from the two splitting parts 81 and 82 are exclusively ORed in EOR circuit 83, the output of which is fed as left data to the first one of cascade-connected randomization stages 76. The two left sub-block data from the splitting parts 81 and 82 are fed to randomizing parts 84 and 85 for randomization with the respective right sub-block data. The randomized outputs of the randomizing parts 84 and 85 are fed to EOR circuit 86, the output of which is fed as right data to the first randomization stage 76. Randomization stages 76 are of the same arrangement as those shown in FIG. 9 except that EOR circuit 77 in a concerned randomization stage 76 receives left data input to the randomization stage preceded by three stages from the concerned stage 76. However, all "0" data D0 is fed to EOR circuit 77 of the first randomization stage 76, and the right sub-block data noted above of the splitting parts 81 and 82 are fed to the EOR circuits 77 of the second and third randomization stages 76, respectively. The outputs of the randomizing parts 78 of the respective randomization stages 76 and outputs of randomizing parts 84 and 85 are provided in combination as 244-bit output data.
1. Data randomization equipment comprising:
splitting means for splitting input data into a plurality of blocks of data each of which has the same data length;
a plurality of processing channels each of which is operative to successively process therealong respective block data supplied thereto as respective channel data from said splitting means;
at least one function operation means provided in each of said processing channels for subjecting the channel data in said processing channel to a function operation at least once to produce new data as channel data;
at least one branching means provided in each of said processing channels for supplying the channel data from said processing channel to the function operation means in another one of said processing channels, each of said function operation means performing its function operation in relation to the channel data received from said branching means of another one of said processing channels so that the channel data of each processing channel is eventually operated with the channel data of all the other processing channels; and
combining means for combining the channel data from the outputs of all of said processing channels to produce randomized output data.
22. Data randomization equipment comprising:
splitting means for splitting input data into four blocks of data each of which has the same data length;
four processing channels for processing the four blocks of data respectively supplied thereto as four channel data from said splitting means;
first function operation means in each of said four processing channels respectively for subjecting the channel data in each of said processing channels to a function operation in relation to the channel data of another one of said processing channels to produce new channel data;
first branching means provided in each of said four processing channels for supplying channel data from each of said processing channels to the first function operation means in another one of said processing channels;
second function operation means in each of at least two of said processing channels upstream of the respective first function operation means in said at least two processing channels for function-operating the corresponding channel data on the channel data of another one of said four processing channels to produce new channel data;
second branching means in each of at least two of said processing channels for supplying the corresponding channel data to said second function operation means in another one of said four processing channels; and
combining means for combining the four channel data outputs from said four processing channels to produce randomized output data.
US06926043 1985-11-08 1986-11-03 Data randomization equipment Expired - Lifetime US4850019A (en)
JP25039885A JPH0760292B2 (en) 1985-11-08 1985-11-08 Data randomization equipment
JP60-250398 1985-11-08
JP25265085A JPH0333269B2 (en) 1985-11-13 1985-11-13
JP60-252650 1985-11-13
US4850019A true US4850019A (en) 1989-07-18
ID=26539758
US06926043 Expired - Lifetime US4850019A (en) 1985-11-08 1986-11-03 Data randomization equipment
US (1) US4850019A (en)
EP (2) EP0454187B1 (en)
DE (4) DE3650365T2 (en)
EP1052611A1 (en) * 1998-01-27 2000-11-15 Nippon Telegraph and Telephone Corporation Data converter and recording medium on which program for executing data conversion is recorded
US20100150346A1 (en) * 2006-06-23 2010-06-17 Masao Nonaka Data encryption apparatus, data converting method, data converting program, recording medium and integrated circuit
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Modular Design of Information Encipherment for Computer Systems , by J. P. Pieprzyk, Computers & Security, vol. 4, No. 3, Sep. 1985, pp. 211 218. *
Structured Design of Substitution Permutation Encryption Networks , by J. B. Kam et al., IEEE Trans. on Computers, vol. C 28, No. 10, Oct. 1979, pp. 747 753. *
EP1052611A4 (en) * 1998-01-27 2003-08-06 Nippon Telegraph & Telephone Data converter and recording medium on which program for executing data conversion is recorded
US8135130B2 (en) 2006-06-23 2012-03-13 Panasonic Corporation Data encryption apparatus, data converting method, data converting program, recording medium and integrated circuit
DE3650365D1 (en) 1995-09-14 grant
EP0454187B1 (en) 1995-08-09 grant
EP0221538A3 (en) 1988-08-10 application
DE3650365T2 (en) 1996-02-08 grant
EP0454187A2 (en) 1991-10-30 application
DE3689510D1 (en) 1994-02-17 grant
EP0221538B1 (en) 1994-01-05 grant
EP0454187A3 (en) 1992-04-29 application
DE3689510T2 (en) 1994-05-19 grant
EP0221538A2 (en) 1987-05-13 application
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:SHIMIZU, AKIHIRO;MIYAGUCHI, SHOJI;REEL/FRAME:004631/0424
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHIMIZU, AKIHIRO;MIYAGUCHI, SHOJI;REEL/FRAME:004631/0424