Source: https://patents.google.com/patent/US8432007B2/en
Timestamp: 2018-08-21 11:15:28
Document Index: 764420972

Matched Legal Cases: ['§121', '§120', 'Application No. 102005053765', 'Application No. 2008', 'Application No. 2008', 'Application No. 2007', 'Application No. 2008', 'Application No. 2008']

US8432007B2 - MEMS package and method for the production thereof - Google Patents
US8432007B2
US8432007B2 US13075936 US201113075936A US8432007B2 US 8432007 B2 US8432007 B2 US 8432007B2 US 13075936 US13075936 US 13075936 US 201113075936 A US201113075936 A US 201113075936A US 8432007 B2 US8432007 B2 US 8432007B2
US13075936
US20110186943A1 (en )
This is a continuation application that claims the benefit pursuant to 35 U.S.C. §121 of U.S. National application Ser. No. 12/092,439, filed Aug. 25, 2008, which application claims the benefit pursuant to 35 USC §120 to WIPO PCT/DE2006/001945 filed Nov. 6, 2006, which claims the benefit of German Patent Application No. 102005053765.0 filed Nov. 10, 2005. Each of these applications is incorporated by reference in its entirety.
The MEMS chip and chip component can be arranged one next to the other on the carrier substrate and can be covered with a common large surface area enclosure, in particular, a laminate film. Preferably, the arrangement is made so that the laminate film encloses the MEMS chip and the one or more chip components separately against the top side of the carrier substrate. The shielding layer is the applied over a large surface area above the enclosure and preferably forms a seal with the top side of the carrier substrate.
Preferably, the MEMS chip is provided with a cover arranged under the enclosure, which covers either the sensitive MEMS structures on the active side or spans an optional upward-facing recess in the MEMS chip.
FIG. 16 shows a microelectromechanical system package where a chip component CB is embedded in the substrate TS.
FIGS. 16A ad 16B show arrangements in which the chip component is arranged on the carrier substrate and embedded in the substrate, respectively.
FIG. 1 shows a simple embodiment of the MEMS package, in which the MEMS chip MC and chip component CB are mounted one next to the other on the top side of the carrier substrate TS and are attached there, for example, by means of adhesive. The electrical contacting of the two components to the carrier substrate is realized with bonding wires BD. The enclosure AB is made from a cap sitting on the carrier substrate, which encloses underneath a cavity HR. The cap can be adhesively bonded, for example, on the carrier substrate TS and is made, for example, from a prefabricated plastic part. The shielding layer SL is applied on the cap and the surface of the carrier substrate with a thin-film method and is optionally reinforced with wet-chemical or galvanic methods. For example, a two-step process is suitable in which initially a metallic adhesive layer—for example, made from titanium, nickel, chromium, tungsten, or copper—is sputtered and then reinforced with copper or nickel with a galvanic or electroless method from solution. Suitable layer thicknesses for fulfilling the shielding function then lie in the range between 10 and 100 μm. Preferably, the carrier substrate TS has a terminal surface connected to ground that seals the shielding layer and thus grounds the layer. The cavity HR under the enclosure AB formed as a cap is used as a back volume for the function of the MEMS chip. The MEMS chip MC has, on the passive side facing toward the carrier substrate, a recess AN in which the MEMS chip is thinned until the MEMS structures of the active side are exposed. Underneath the recess, an opening OE formed as a perforation is provided in the carrier substrate, so that the (passive) bottom side of the MEMS chip is connected in the region of the recess AN to an ambient atmosphere or an ambient pressure.
As a carrier substrate TS, ceramic printed circuit board substrates are suitable in a multi-layer technology on a ceramic (HTCC—high temperature cofired ceramics, LTCC—low temperature cofired ceramics). Also suitable are high-temperature thermoplastics (e.g., PEI polyetherimide, PAEK polyaryl ether ketone, PSU polysulfone, PPS polyphenylene sulfide, PAI polyamidimide, PA polyamide, polyphthalamide, polybutylene terephthalate, or others) as the material for the carrier substrate TS, especially those in MID processing (molded interconnect device). Passive or active components can be embedded in the carrier substrate TS. In the case of a MEMS chip constructed as a microphone, these are in particular amplifiers or AD converters, and also devices protecting against EMI (electro-magnetic interference) and ESD (electro-static discharge).
FIG. 3 shows an arrangement in which the MEMS chip MC and chip component CB are placed as in FIG. 2. Unlike there, here the chip component CB is covered, but with a directly applied protective encapsulation, for example, a glob-top mass LG. An enclosure layer, for example, a laminated laminate film, is applied as another enclosure
AB both above the MEMS chip MC and also above the chip component CB provided with the protective enclosure LG. This fits tightly against the MEMS chip MC and can, as shown, span the recess AN on the (passive) bottom side of the MEMS chip MC. The shielding layer SL is in turn applied as a metallic layer on the surface of the enclosure layer, and forms an overall seal with the carrier substrate TS.
The shielding layer SL on the top side of the carrier substrate on which the MEMS chip and possibly other components are located is of essential significance for shielding the sensitive internal signal processing relative to external interference fields. This is especially relevant for use in mobile telephony, where the component is often arranged only a few centimeters from the antenna. The processing sequence discussed above, lamination—sputtering—electroplating, is only one possibility for producing this coating with good conductivity. In a few embodiments, e.g., the lamination process can be eliminated (cf. FIG. 5). It is also possible to produce a corresponding layer through dipping, casting, or spraying instead of lamination. For the metallization of plastic surfaces, a series of PVD, CVD, wet-chemical, and galvanic methods (or combinations of these) is known. For a structured metallization structure MS (see FIGS. 13, 14, 15) for the purpose of circuitry, their photolithographic structuring or a selective metallization is provided, e.g., laser-activated deposition or direct writing of the metallization structure with a jet printing method.
a ceramic carrier substrate having a top side,
a MEMS chip mounted in a flip-chip configuration on the top side of the carrier substrate,
at least one chip component on, or above, the top side of the carrier substrate or embedded in the carrier substrate,
a metallic shielding layer above the MEMS chip and the at least one chip component, the metallic shielding layer forming a seal with the top side of the carrier substrate, and
an enclosure between the metallic shielding layer and the MEMS chip; wherein:
the MEMS chip and the at least one chip component are electrically connected to each other or to external contacts on the carrier substrate;
the enclosure comprises a cover over at least part of the MEMS chip;
the metallic shielding layer is above the MEMS chip and the chip component.
2. The MEMS package of claim 1, wherein the enclosure comprises a laminate film applied above a surface area above the MEMS chip and the at least one chip component, the laminate film forming a seal with the carrier substrate.
3. The MEMS package of claim 1, wherein the enclosure comprises a rigid cap on the carrier substrate, the rigid cap and the carrier substrate defining a cavity, wherein the MEMS chip is in the cavity, and wherein the metallic shielding layer is directly on the rigid cap and on the carrier substrate in an edge region around the rigid cap.
4. The MEMS package of claim wherein the metallic shielding layer is in contact with the MEMS chip and contacts the cover, side surfaces of the MEMS chip and the top side of the carrier substrate.
5. The MEMS package of claim 1, wherein:
the MEMS chip has an active side that faces the top side of the carrier substrate, the MEMS chip being electrically and mechanically connected to the carrier substrate by one or more of bumps and electrically conductive adhesive,
the cover is above a passive side of the MEMS chip facing away from the top side of the carrier substrate,
the metallic shielding layer is on an outward surface of the laminate film.
6. The MEMS package of claim 5, wherein the electrically conductive adhesive comprises an anisotropic conductive adhesive having a conductivity that is perpendicular an adhesion surface.
7. A method for producing a MEMS package, comprising:
mounting a MEMS chip in a flip-chip configuration on a carrier substrate, the carrier substrate comprising external contacts, the carrier substrate having a top side;
arranging a chip component on or above the top side of the carrier substrate,
creating an electrical connection between the MEMS chip, the chip component, and the external contacts on the carrier substrate,
adding an enclosure comprising a laminate film above the MEMS chip and the chip component to form a cover over the MEMS chip, and
applying a metallic shielding layer comprising a metallic layer above the enclosure, the metallic shielding layer forming a seal with the top side of the carrier substrate; wherein
mounting the MEMS chip on the carrier substrate comprises mechanically connecting the MEMS chip to the carrier substrate by one or more of bumps and electrically conductive adhesive,
adding the enclosure to form the cover comprises adding the cover on a passive side of the MEMS chip facing away from the top side of the carrier substrate,
adding the enclosure comprises covering the MEMS chip, the cover, and the at least one chip component with the laminate film and applying the metallic shielding layer comprises applying the shielding layer on an outward surface of the laminate film.
8. The method of claim 7, wherein the enclosure comprises a laminate film, the laminate film forming a seal with the carrier substrate around the MEMS chip and the chip component, and
wherein applying the shielding layer comprises applying the shielding layer over a surface area on the laminate film and the carrier substrate such that the shielding layer forms a seal with the carrier substrate and is connected electrically at one or more positions to a contact surface of the carrier substrate.
9. The method of claim 7, wherein applying the shielding layer comprises generating the shielding layer at least partially by depositing metal from a solution.
10. The method of claim 7, wherein applying the shielding layer comprises generating the shielding layer at least partially by sputtering, a PVD or CVD process, or by evaporation of metal.
11. A micro electro-mechanical systems (MEMS) package comprising:
a metallic shielding layer above the MEMS chip and the at least one chip component, the metallic shielding layer forming a seal with the top side of the carrier substrate,
an enclosure between the metallic shielding layer and the MEMS chip, the enclosure forming a cover over at least a part of the MEMS chip; wherein:
the MEMS chip and the at least one chip component are one next to the other and electrically connected to each other or to external contacts on the carrier substrate;
an active side of the MEMS chip is electrically and mechanically connected to the carrier substrate by one or more of bumps and electrically conductive adhesive,
the MEMS chip, the cover, and the at least, one chip component are covered with the laminate film,
the metallic shielding layer above the MEMS chip and the chip component and is on an outward surface of the laminate film; and
the enclosure seals the MEMS chip and the chip component to the carrier substrate separately.
12. The MEMS package of claim 11, wherein the laminate film forms a seal with the carrier substrate.
13. The MEMS package of claim 11, wherein the enclosure comprises a rigid cap on the carrier substrate, the rigid cap and the carrier substrate defining a cavity, wherein the MEMS chip is in the cavity, and wherein the metallic shielding layer is directly on the rigid cap and on the carrier substrate in an edge region around the rigid cap.
14. The MEMS package of claim 11, wherein the metallic shielding layer is in contact with the MEMS chip and contacts the cover, side surfaces of the MEMS chip and the top side of the carrier substrate.
15. The MEMS package of claim 11, wherein:
16. The MEMS package of claim 15, wherein the electrically conductive adhesive comprises an anisotropic conductive adhesive having a conductivity that is perpendicular an adhesion surface.
17. The MEMS package of claim 11, wherein the carrier substrate comprises a diffusion-resistant, material and the metallic shielding layer binds to the diffusion-resistant material circumferentially.
18. The MEMS package of claim 1, wherein the carrier substrate comprises a diffusion-resistant material and the metallic shielding layer binds to the diffusion-resistant material circumferentially.
US13075936 2005-11-10 2011-03-30 MEMS package and method for the production thereof Active US8432007B2 (en)
DE200510053765 DE102005053765B4 (en) 2005-11-10 2005-11-10 MEMS package and process for preparing
US9243908 true 2008-08-25 2008-08-25
US13075936 US8432007B2 (en) 2005-11-10 2011-03-30 MEMS package and method for the production thereof
US12092439 Continuation
PCT/DE2006/001945 Continuation WO2007054070A1 (en) 2005-11-10 2006-11-06 Mems package and method for the production thereof
US9243908 Continuation 2008-08-25 2008-08-25
US20110186943A1 true US20110186943A1 (en) 2011-08-04
US8432007B2 true US8432007B2 (en) 2013-04-30
US12092439 Active 2027-07-18 US8169041B2 (en) 2005-11-10 2006-11-06 MEMS package and method for the production thereof
US13075936 Active US8432007B2 (en) 2005-11-10 2011-03-30 MEMS package and method for the production thereof
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US8169041B2 (en) 2012-05-01 grant
DE102005053765B4 (en) 2016-04-14 grant
JP2009514691A (en) 2009-04-09 application
WO2007054070A1 (en) 2007-05-18 application
US20110186943A1 (en) 2011-08-04 application
DE102005053765A1 (en) 2007-05-16 application
JP5130223B2 (en) 2013-01-30 grant
US20090001553A1 (en) 2009-01-01 application
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PAHL, WOLFGANG;LEIDL, ANTON;SEITZ, STEFAN;AND OTHERS;SIGNING DATES FROM 20050513 TO 20080527;REEL/FRAME:026087/0521