Source: http://www.google.com/patents/US20030074639?ie=ISO-8859-1
Timestamp: 2015-08-02 12:49:08
Document Index: 208767985

Matched Legal Cases: ['art 12', 'art 14', 'art 12', 'art 14', 'art 14', 'art 12', 'art 14', 'art 12', 'Application No. 2001', 'art 14', 'art 12', 'art 12', 'art 12']

Patent US20030074639 - Method for automatically correcting overlay alignment of a semiconductor wafer - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor wafer overlay correction method for an exposure process in a semiconductor fabricating stepper incorporates variations in equipment characteristics with time. The wafer overlay correction method includes measuring an overlay error correction value of a semiconductor wafer that is exposed...http://www.google.com/patents/US20030074639?utm_source=gb-gplus-sharePatent US20030074639 - Method for automatically correcting overlay alignment of a semiconductor waferAdvanced Patent SearchPublication numberUS20030074639 A1Publication typeApplicationApplication numberUS 10/233,556Publication dateApr 17, 2003Filing dateSep 4, 2002Priority dateOct 11, 2001Also published asUS6826743Publication number10233556, 233556, US 2003/0074639 A1, US 2003/074639 A1, US 20030074639 A1, US 20030074639A1, US 2003074639 A1, US 2003074639A1, US-A1-20030074639, US-A1-2003074639, US2003/0074639A1, US2003/074639A1, US20030074639 A1, US20030074639A1, US2003074639 A1, US2003074639A1InventorsChan-hoon Park, Bong-Su Cho, Hyun-Tae KangOriginal AssigneePark Chan-Hoon, Bong-Su Cho, Hyun-Tae KangExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (5), Classifications (5), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod for automatically correcting overlay alignment of a semiconductor wafer
US 20030074639 A1Abstract
A semiconductor wafer overlay correction method for an exposure process in a semiconductor fabricating stepper incorporates variations in equipment characteristics with time. The wafer overlay correction method includes measuring an overlay error correction value of a semiconductor wafer that is exposed by the stepper, calculating an overlay error correction value by summing the measured overlay error correction value, a variation in the stepper characteristics that is obtained through an empirical characterization of input changes, and a weighting value obtained from a predetermined plurality of wafer lots, and providing the calculated overlay error correction value to the semiconductor fabricating stepper to control an exposure process of a subsequent wafer lot. Images(4) Claims(3)
What is claimed is: 1. A wafer overlay correction method for an exposure process in a semiconductor fabricating stepper, comprising: measuring an overlay error correction value of a semiconductor wafer that is exposed by the stepper; calculating an overlay error correction value by summing the measured overlay error correction value, a variation in the stepper that is obtained through an empirical characterization of input changes, and a weighting value obtained from a predetermined plurality of wafer lots; and providing the calculated overlay error correction value to the stepper to control an exposure process of a subsequent wafer lot. 2. The method as claimed in claim 1, wherein the weighting value of the predetermined plurality of lots is a weighted average value of the latest ten lots measured in a same history data. 3. The method as claimed in claim 1, wherein the overlay error correction value is calculated using the following set of equations: X(k)=X.stepper(k)−X.ffwd(k)−X.kla(k)−X.bias(k)X.bias(k)=X.stepper(m)−X.ffwd(m)−X.kla(m)−x(m)x(k)=f[x(k−1),x(k−2),x(k−3), . . . ,x(k−m)]X.stepper(k)=X.ffwd(k)+X.bias(k)+x(k)
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to overlay alignment of a stepper in the fabrication of a semiconductor device. More particularly, the present invention relates to an overlay correction method for aligning semiconductor wafers that are exposed by a stepper. [0003] 2. Description of the Related Art [0004] In order to fabricate semiconductor devices, silicon wafers typically undergo various processes, such as cleaning, diffusion, photoresist coating, exposure, developing, etching, ion-implantation, and the like. Each one of these processes requires a corresponding piece of equipment. For an exposure process, a stepper is used to expose photoresists that have been coated on the wafers using light from a light source, so that the wafers may be patterned during subsequent developing and etching processes. [0005] In the exposure process, a predetermined number of wafers that have been coated with a photoresist are loaded into a carrier, which is then loaded on a table in the stepper. Since the wafers are typically exposed one layer at a time in the stepper, a fetch arm enters the carrier to select and grip one wafer to initiate the exposure process. Next, the table displaces by one pitch, thereby extracting one wafer from the carrier. As the wafer is removed from the carrier, a slider moves to receive the wafer and the wafer in the slider is thus transferred to a position where the wafer is to be exposed. The stepper performs an alignment process on the wafer and then steps through an exposure process at every unit chip location on a wafer to form a predetermined pattern on the wafer. Since the wafer needs to be accurately exposed in order to form a highly integrated chip, the wafers require accurate and proper alignment. [0006] A technique for correcting an overlay of a wafer in order to align a wafer accurately has been developed. In this conventional technique, a test wafer from a particular processing batch or lot is exposed, and a test exposure result is fed back to correct any misalignment of the test wafer. This alignment correction is stored and later used for aligning each wafer in that particular processing batch or lot. [0007]FIG. 1 illustrates a diagram of a conventional system for correcting an overlay of a wafer using such a technique. The conventional system of FIG. 1 includes a stepper 10 for performing a photolithographic process on a semiconductor device, an overlay measuring part 12 for measuring three sets of offset wafers during the exposure process in the stepper to create overlay characterization data, an interfacing part 14 connected to the stepper 10 and the overlay measuring part 12 in order to interface data signals that are input/output through a data bus 20, a data server 16 and an operator interface server 18, each of which is connected to the data bus 20. [0008] After the operator interface server 18 is input with various parameters required for the exposure process, associated input parameters are transferred to the interface part 14 via the data bus 20. The input parameters are then input to the stepper 10, which performs an exposure process according to the input parameters. The stepper 10 records and transmits product related process information, such as product title and type of the practically processed semiconductor device, recorded data, process parameters such as information regarding the reticule, or reticules, that were employed during an exposure process, a lot number, and the like to the data server 16 through the interfacing part 14 and the data bus 20. Simultaneously, the overlay measuring part 12 detects and records overlay data of wafers that are exposed in the stepper 10 in order to transmit the result to the data server 16 through the interface part 14 and the data bus 20. The data server 16 receives the overlay data that was measured in the overlay measuring part 12 during an exposure process in order to detect any misalignment and calculate error correction values for the overlay according to the following set of equations, hereinafter referred to as formula II: X(k)=X.stepper(k)−X.ffwd(k)−X.kla(k) [1]
[0009] wherein X(k) is a current overlay alignment value; X.stepper(k) is an error correction value of the overlay; X.ffwd(k) is a reference value for wafer alignment; X.kla(k) is an overlay-measured value; Z(m) is a weighted average value for a latest three lots, w1, w2, w3 are the weighted values; X(k−1) is a latest overlay alignment value; X(k−2) is a second latest overlay alignment value; and X(k−3) is a third latest overlay alignment value. [0010] The overlay error correction value X.stepper(k) in formula I is calculated by summing the weighted average value (w1:w2:w3→5:3:2) of the latest three lots measured in a same history and the reference value X.ffwd(k) for wafer alignment of a lot to be processed. The overlay error correction value X.stepper(k) is applied to the operator interface server 18 and provided as overlay data for an exposure process to be performed for a subsequent lot. At this time, the data server 16 divides and stores overlay data according to a grouping criteria, such as a same load of the same stepper, a same pattern of the same lot, a same device, and the like. Such division of the overlay data by the data server 16 results in forming groups of same types of overlay data, thereby maintaining consistency in data. [0011] Since the conventional overlay correction method as described above is performed by summing only the weighted average value of three lots that are within a range bounded by the latest data and the previous data and the reference value for the wafer alignment of a lot to be processed, variances in equipment characteristics with respect to time are not considered, thereby causing frequent specification failures. Further, there is a disadvantage in that a sample process is required due to a lack of historical data in a production line involving Job Shop Type Production and Small Batch Production. SUMMARY OF THE INVENTION [0012] In an effort to solve the problems as described above, it is a feature of an embodiment of the present invention to provide, in semiconductor fabricating stepper equipment, a semiconductor wafer overlay correction method for correcting a positioning of an overlay of a semiconductor wafer that incorporates variances in equipment characteristics with respect to time. [0013] It is another feature of an embodiment of the present invention to provide a semiconductor wafer overlay correction method that minimizes initialization time for sampling and exchanging wafers used for calibration of an exposure process for a production line for Job Shop Type Production and Small Batch Production, thereby increasing productivity. [0014] According to an aspect of the present invention, a wafer overlay correction method for an exposure process in a semiconductor fabricating stepper includes measuring an overlay error correction value of a semiconductor wafer that is exposed by the stepper, calculating an overlay error correction value by summing the measured overlay error correction value, a variation in the stepper that is obtained through an empirical characterization of input changes, and a weighting value obtained from a predetermined plurality of lots, and providing the calculated overlay error correction value to the stepper to control an exposure process of a subsequent wafer lot. The predetermined plurality of wafer lots may preferably include the latest ten lots measured in the same history data. [0015] These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.
BRIEF DESCRIPTION OF THE DRAWINGS [0016] The foregoing and other features and advantages of the present invention will be better understood from the following detailed description of preferred embodiments with reference to the accompanying drawings, in which: [0017]FIG. 1 illustrates a diagram of a conventional system for correcting an overlay alignment of a semiconductor wafer; [0018]FIG. 2 illustrates a flow chart showing the steps of a method for implementing an overlay error correction process that is used during a semiconductor wafer exposure process according to a preferred embodiment of the present invention; and [0019]FIG. 3 is an exemplary graph showing results of a comparison of a conventional overlay error correction process with an overlay error correction process according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION [0020] Korean Patent Application No. 2001-62565, entitled: “Method for Automatically Correcting Overlay Alignment of Semiconductor Wafer,” filed on Oct. 11, 2001, is incorporated by reference herein in its entirety. [0021] In the following description and drawings, like reference numerals are used to denote like elements, and detailed descriptions of well-known functions and structures are omitted. [0022] A method for correcting an overlay alignment of a wafer according to an embodiment of the present invention uses a same hardware system as that shown in FIG. 1, but uses a different algorithm for calculating an overlay error correction value in the data server 16. Since the hardware systems have been described in detail above, a further description will not be repeated here. [0023]FIG. 2 illustrates a flow chart showing the steps of a method for implementing an overlay error correction process that is used during a semiconductor wafer exposure process according to a preferred embodiment of the present invention. [0024]FIG. 3 is an exemplary graph showing results of comparing an overlay trend that is applied using a conventional overlay error correction method with the overlay trend that is applied using an overlay error correction method according to an embodiment of the present invention. [0025] Referring to FIGS. 1 and 2, in step 101, the operator interface server 18 is input with various parameters necessary to initiate and operate a wafer exposure process. Associated input parameters are transmitted to a stepper 10 via an interfacing part 14 and a data bus 20. In step 102, the stepper 10 initiates an exposure process according to the input parameters. In step 103, an overlay measuring part 12 measures overlay data of wafers exposed in the stepper 10 to thereafter transmit the measured data to a data server 16. In step 104, the data server 16 receives the measured data from the overlay measuring part 12 and calculates an overlay error correction value according to a set of equations, hereinafter referred to as formula II: X(k)=X.stepper(k)−X.ffwd(k)−X.kla(k)−X.bias(k) [4]
[0026] wherein X(k) is a current overlay alignment value; X.stepper(k) is an overlay error correction value; X.ffwd(k) is a reference value for wafer alignment; X.kla(k) is an overlay-measured value; x(k) is an estimated value in a variation of equipment through an empirical characterization of input changes; and X.bias(k) is a weighted average value obtained from the latest ten lots. [0027] The overlay error correction value X.stepper(k) in formula II is calculated by summing the weighted average value (w1:w2:w3 . . . w10→10:9:8 . . . :1) of the latest ten lots (i.e., most recently) measured in a same history, the reference value X.ffwd(k) for wafer alignment of a lot to be processed, and the variation of the stepper 10 through an empirical characterization of input changes in the stepper 10. In step 105, the overlay error correction value X.stepper(k) thus calculated is transmitted to the operator interface server 18, wherein it is stored as overlay data for an exposure process of a subsequent wafer lot. At this time, the data server 16 preferably divides and stores overlay data according to a grouping criteria, such as a same load of the same stepper, a same pattern of the same lot, a same device, and the like. Such division of the overlay data by the data server 16 results in forming groups of a same type of overlay data, thereby maintaining consistency in the data. [0028] In order to detect a variation in the stepper 10, an optical sensor may receive a light signal that is reflected from a reference mark on a reference plate to form a set pattern of the received light signal thereby determining a current position X of the stepper 10. Thereafter, a standard deviation σ is preferably calculated regarding the predetermined period of time and predetermined number of wafer lots out of the previously measured values. A variation ΔX may be obtained by calculating a difference value between the measured value of the current position X of the stepper 10 and a previously measured position X0 of the stepper 10. The variation ΔX thus calculated is transmitted to the data server 16 to be used in correction of an overlay error. [0029] As a result of applying such an overlay error correction method to the stepper 10, a plurality of dimensional parameters, such as OFFSET X/Y (i.e., a data value that is deviated from a reference alignment value in an X-axis or Y-axis), SCAL X/Y (i.e., a data value that is contracted or expanded relative to a reference value), ORTHONALITY (i.e., a data value that is inclined in an X-axis or Y-axis relative to a reference value), WROTY (i.e., a data value that is rotated in a whole direction relative to a reference value), RED X/Y (i.e., Reduction X/Y, a data value corresponding to SCAL X/Y that is obtained when only one chip out of a plurality of chips is measured), RROT X/Y (i.e., Reticle Rotation X/Y, a data value corresponding to WROTY that is obtained when only one chip out of a plurality of chips is measured), which represent data measured in the overlay measuring part 12, become similar or improved in a dispersion and a trend when compared with those obtained using the conventional method. [0030] For instance, as a result of checking an exemplary number of sample recommendations in a piece of stepper equipment (for example, No. 30) during the period of time from Apr. 27, 2001 to May 28, 2001, a sample recommendation using a conventional exposure method was 210 in frequency and the sample recommendation using an exposure process according to the present invention was 19 in frequency. Similarly, in another piece of stepper equipment (for example, No. 62) during the period from May 15, 2001 to May 28, 2001, a sample recommendation using the conventional exposure process was 153 in frequency and a sample recommendation using the exposure process according to the present invention was 24 in frequency. [0031] As a result of the comparison between the conventional overlay correction method and the overlay correction method according to the present invention, the overlay correction method of the present invention significantly decreases the number of sample recommendations over that of the conventional method, thereby resulting in an increase in productivity. [0032] As a result of the application of the conventional overlay correction method, a reworking rate in equipment No. 30 was a representative 5.9% during the period from Mar. 1, 2001 to Mar. 31, 2001. In contrast, as a result of application of the overlay correction method of the present invention, the reworking rate was a representative 2.8% during the same period of time. These results indicate that the overlay correction method of the present invention decreases the reworking rate by a representative 3.1% when compared with the conventional overlay correction method. [0033] Advantageously, according to a preferred embodiment of the present invention, while a semiconductor fabricating stepper performs an exposure process, an overlay error correction value is calculated by summing the measured overlay data and the variation in the stepper state as a weighted value over a representative ten lots, and the exposure process is performed taking the calculated overlay error correction value in account, thereby decreasing the dispersion in the overlay and the number of sampling recommendations, with an attendant increase in productivity. In addition, there is an advantage in that an exposure process is performed with a more accurate pattern and the reworking rate decreases, thereby increasing the working yield. [0034] In FIG. 3, the experimental data to the left of the vertical line A represent the dispersion of overlay-measured values in SCAL X/Y according to a conventional technique. The experimental data to the right of the vertical line A represent the dispersion of overlay-measured values in SCAL X/Y according to the present invention. The symbols ▪ represent the deviation from a reference value relative to a Y axis. The symbols  represent the deviation from a reference value relative to a X axis, every lots. Referring to FIG. 3, it indicates that the deviation of overlay-measured values decreased when compared with that in the conventional technique. [0035] A preferred embodiment of the present invention has been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS2151733May 4, 1936Mar 28, 1939American Box Board CoContainerCH283612A * Title not availableFR1392029A * Title not availableFR2166276A1 * Title not availableGB533718A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7159023Dec 16, 2003Jan 2, 2007Alexa InternetUse of web usage trail data to identify relationships between browsable itemsUS7184853May 18, 2005Feb 27, 2007Infineon Technologies Richmond, LpLithography method and system with correction of overlay offset errors caused by wafer processingUS7480892 *Aug 31, 2006Jan 20, 2009Nanya Technology CorporationOverlay markEP1536282A2 *Nov 25, 2004Jun 1, 2005Inficon Lt, Inc.Methods and systems for estimating reticle bias statesEP1843210A2 *Mar 26, 2007Oct 10, 2007ASML Netherlands BVMethod of aligning and exposing a substrate* Cited by examinerClassifications U.S. Classification430/22International ClassificationG03F7/20, H01L21/027Cooperative ClassificationG03F7/70633European ClassificationG03F7/70L10DLegal EventsDateCodeEventDescriptionSep 4, 2002ASAssignmentMay 16, 2008FPAYFee paymentYear of fee payment: 4Apr 24, 2012FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services