Source: http://www.google.com/patents/US7436063?ie=ISO-8859-1
Timestamp: 2014-07-26 13:52:13
Document Index: 453628496

Matched Legal Cases: ['arts 3', 'art 3', 'arts 3', 'art 3', 'art 3', 'art 3', 'arts 3', 'arts 3', 'art 3', 'Application No. 2004', 'in fine']

Patent US7436063 - Packaging substrate and semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate and comprises a wiring provided on a bonding surface to which...http://www.google.com/patents/US7436063?utm_source=gb-gplus-sharePatent US7436063 - Packaging substrate and semiconductor deviceAdvanced Patent SearchPublication numberUS7436063 B2Publication typeGrantApplication numberUS 11/242,125Publication dateOct 14, 2008Filing dateOct 4, 2005Priority dateOct 4, 2004Fee statusPaidAlso published asUS20060071333Publication number11242125, 242125, US 7436063 B2, US 7436063B2, US-B2-7436063, US7436063 B2, US7436063B2InventorsOsamu Miyata, Shingo HiguchiOriginal AssigneeRohm Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (8), Referenced by (28), Classifications (18), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetPackaging substrate and semiconductor deviceUS 7436063 B2Abstract A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate and comprises a wiring provided on a bonding surface to which the semiconductor chip is bonded, a plurality of electrode parts provided on the bonding surface and electrically connected to the wiring, a wiring protective layer for coating and protecting the wiring, electrode openings formed by partly opening the wiring protective layer for separately exposing each of the electrode parts from the wiring protective layer, and escape openings each formed in continuation with each of the electrode openings in the wiring protective layer for introducing therein a part of the connection metal body to be connected to each of the electrode parts to escape.
1. A packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate, comprising:
a wiring provided on a bonding surface to which the semiconductor chip is bonded,
a plurality of electrode parts provided on the bonding surface and electrically connected to the wiring,
a wiring protective layer for coating and protecting the wiring,
electrode openings formed by partly opening the wiring protective layer for separately exposing each of the electrode parts from the wiring protective layer, and
escape openings, each being formed in continuation with a respective electrode opening in the wiring protective layer and exposing a part of the wiring, each escape opening having a width greater than a width of the wiring and exposing an entire width of the part of the wiring, each escape opening introducing onto the exposed part of the wiring a part of the connection metal body that escapes into the escape opening when the connection metal body is connected to each of the electrode parts.
2. The packaging substrate according to claim 1, wherein the escape opening is formed along the wiring extending from the electrode opening formed in continuation with the escape opening.
a packaging substrate and
a semiconductor chip which has a plurality of connection metal bodies on a surface thereof and is bonded to the packaging substrate with the surface opposed to the packaging substrate,
the packaging substrate comprising:
a wiring provided on the bonding surface to which the semiconductor chip is bonded,
4. The semiconductor device according to claim 3, wherein the escape opening is formed along the wiring extending from the electrode opening formed in continuation with the escape opening.
the plurality of connection metal bodies includes a first metal body and a second metal body larger than the first metal body,
the electrode parts include a first electrode part and a second electrode part,
the electrode openings include a first electrode opening exposing the first electrode part and a second electrode opening exposing the second electrode part,
the escape opening include a first escape opening formed in continuation with the first electrode opening, and a second escape opening formed in continuation with the second electrode opening,
when the first and second metal bodies are respectively connected to the first and second electrode parts, the second metal body is pressed against the packaging substrate, and
when the second electrode opening is not spacious enough to accommodate all parts of the pressed second metal body, a portion of the second metal body escapes into the second escape opening, so that the semiconductor chip is bonded in a parallel position to the packaging substrate.
when the second electrode opening is not spacious enough to accommodate all parts of the pressed second metal body, a portion of the second metal body escapes into the second escape opening, so that the semiconductor chip is bonded in a parallel position to the packaging substrate. Description
The present invention relates to a packaging substrate to which a semiconductor chip is packaged, and a semiconductor device obtained by packaging a semiconductor chip to the packaging substrate.
Semiconductor devices of a flip chip bonding structure are hitherto known in which a semiconductor chip is bonded to a surface of a packaging substrate such as a printed wiring substrate in a face down manner.
In a semiconductor chip to be applied to such a semiconductor device of a flip chip bonding structure, a function surface thereof on which a function element is formed is coated with a passivation film. The passivation film is provided with a plurality of openings for partly exposing an internal wiring electrically connected to the function element as electrode pads. On each of the electrode pads, a metal ball of a fusible metal material such as solder is formed in a protruded manner. On the other hand, a surface of the packaging substrate is coated with a solder resist layer for protecting a wiring. The solder resist layer is provided with openings for partly exposing the wiring at the positions respectively corresponding to the electrode pads of the semiconductor chip.
Thus, the semiconductor chip is bonded to the surface of the packaging substrate with the function surface of the semiconductor chip opposed to the surface of the packaging substrate. Each metal ball is connected through the corresponding opening to the wiring on the packaging substrate, so that the semiconductor chip and the packaging substrate are connected with a predetermined distance therebetween and electrically connected to each other. Thereby, a semiconductor device of a flip chip bonding structure can be obtained.
However, the sizes (volumes) of the metal balls are not always strictly uniform with one another but somewhat different. Therefore, in a semiconductor device of a flip chip bonding structure, sometimes there occurs a problem that a semiconductor chip 102 is bonded to a packaging substrate 101 in an inclined manner as shown in FIG. 4. Especially in an ultra small semiconductor device to which a WL-CSP (Wafer Level-Chip Scale Package) technology has been applied, such a problem caused by the difference between the sizes of metal balls 103 remarkably appears.
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device in which a semiconductor chip is bonded in a parallel position to a packaging substrate, and a packaging substrate with which such a semiconductor device can be obtained.
A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate, and comprises a wiring provided on a bonding surface thereof to which the semiconductor chip is bonded, a plurality of electrode parts provided on the bonding surface and electrically connected to the wiring, a wiring protective layer for coating and protecting the wiring, electrode openings formed by partly opening the wiring protective layer for separately exposing each of the electrode parts from the wiring protective layer, and escape openings each formed in continuation with each of the electrode openings in the wiring protective layer for introducing therein a part of the connection metal body to be connected to each of the electrode parts to escape.
According to this arrangement, even if the sizes of the connection metal bodies of the semiconductor chip are different from one another, a part of each of relatively large-sized connection metal bodies can escape into the escape opening when the semiconductor chip is bonded to the packaging substrate and each connection metal body is connected to each electrode part, so that the distance between the semiconductor chip and the packaging substrate can be uniformalized with the distance corresponding to a relatively small-sized (the smallest-sized) connection metal body. As a result, a parallel position of the semiconductor chip to the packaging substrate can be ensured, thereby to obtain a semiconductor device in which the semiconductor chip is bonded in a parallel position to the packaging substrate.
Further, a semiconductor device according to the present invention comprises a packaging substrate and a semiconductor chip which has a plurality of connection metal bodies on a surface thereof and is bonded to the packaging substrate with the surface opposed to the packaging substrate, and the packaging substrate comprises a wiring provided on a bonding surface thereof to which the semiconductor chip is bonded, a plurality of electrode parts provided on the bonding surface and electrically connected to the wiring, a wiring protective layer for coating and protecting the wiring, electrode openings formed by partly opening the wiring protective layer for separately exposing each of the electrode parts from the wiring protective layer, and escape openings each formed in continuation with each of the electrode openings in the wiring protective layer for introducing therein a part of the connection metal body to be connected to each of the electrode parts to escape.
In other words, a semiconductor device according to the present invention comprises such a packaging substrate as abovementioned and a semiconductor chip which has a plurality of connection metal bodies on a surface thereof and is bonded to the packaging substrate with the surface opposed to the packaging substrate. Therefore, a semiconductor device in which a semiconductor chip is bonded in a parallel position to a packaging substrate can be obtained.
It is preferable that the escape opening is formed along the wiring extended from the electrode opening formed in continuation with the escape opening. With this arrangement, since the escape opening is formed along the wiring, the connection metal body can be led along the wiring (a molten solution of the connection metal body can be led along the wiring) into the escape opening when the connection metal body is connected to the electrode part. Therefore, with the use of this packaging substrate, a semiconductor device in which a semiconductor chip is bonded in a parallel position to the packaging substrate can be more surely obtained.
The abovementioned and other objects, features and advantages of the present invention will become more apparent from the following description of preferred embodiments given with reference to the appended drawings.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic sectional view showing the structure of a packaging substrate according to an embodiment of the present invention and a semiconductor chip to be bonded to the packaging substrate.
FIG. 2 is a plan view of a main part of the packaging substrate of FIG. 1.
FIG. 3 is a schematic sectional view showing the structure of a semiconductor device obtained by bonding the semiconductor chip to the packaging substrate of FIG. 1.
FIG. 4 is a schematic side view showing the structure of a conventional semiconductor device.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS FIG. 1 is a schematic sectional view showing the structure of a packaging substrate according to an embodiment of the present invention and a semiconductor chip to be bonded to the packaging substrate. And FIG. 2 is a plan view of a main part of the packaging substrate of FIG. 1.
The packaging substrate 1 comprises a thin resin substrate formed of a resin material such as a polyimide resin or an epoxy resin. On a surface 1 a as a bonding surface of the packaging substrate 1, a copper wiring 2 and a plurality of electrode parts 3 electrically connected to the copper wiring 2 respectively are formed. Each electrode part 3 is formed in a substantially circular shape in plan view. These copper wiring 2 and electrode parts 3 can be formed, for example, by plating.
Provided on the surface 1 a of the packaging substrate 1 is a solder resist layer 4 as a wiring protective layer for coating and protecting the copper wiring 2. The solder resist layer 4 is provided with a plurality of electrode openings 5 for separately exposing each electrode part 3 from the solder resist layer 4. Each electrode opening 5 is formed in a circular shape having a slightly larger diameter than that of the electrode part 3 in plan view at a position corresponding to each of the below mentioned plurality of metal balls 8. Further, the solder resist layer 4 is provided with escape openings 6 each of which is formed in a substantially rectangular shape in plan view and in continuation with each electrode opening 5. Each escape opening 6 is extended along the copper wiring 2 electrically connected to the electrode part 3 in each electrode opening 5.
To a semiconductor chip 7, for example, a WL-CSP (Wafer Level-Chip Scale Package) technology has been applied. A surface 7 a of this semiconductor chip 7, on which a function element is formed, is sealed with a protective resin layer. And disposed on the protective resin layer are a plurality of metal balls 8 as connection metal bodies each formed in a ball-like shape of a metal material such as solder. Each metal ball 8 is electrically connected to the function element.
The surface 7 a of the semiconductor chip 7 is opposed to the surface 1 a of the packaging substrate 1 and positioned in such a manner that the plurality of metal balls 8 can be vertically opposed respectively to the corresponding electrode openings 5 (electrode parts 3), and then, with being heated, the semiconductor chip 7 is pressed against the surface 1 a of the packaging substrate 1 by a bonding tool. Thereby, a semiconductor device of a flip chip bonding structure can be obtained in which the metal balls 8 are connected respectively to the corresponding electrode parts 3 and the semiconductor chip 7 is connected to the packaging substrate 1 with a predetermined distance therebetween.
Even if the sizes of the metal balls 8 are different from one another, molten solutions of relatively large-sized metal balls flow into the escape openings 6 respectively when the semiconductor chip 7 is, with being heated, pressed against the packaging substrate 1, so that a part of each of the relatively large-sized metal balls 8 can escape into the escape opening 6 as shown in FIG. 3. Therefore, the distance D between the semiconductor chip 7 and the packaging substrate 1 can be uniformalized with the distance corresponding to a relatively small-sized (the smallest-sized) metal ball 8. As a result, a parallel position of the semiconductor chip 7 to the packaging substrate 1 can be ensured, thereby to obtain a semiconductor device in which the semiconductor chip 7 is bonded in a parallel position to the packaging substrate 1.
Further, since the escape opening 6 is formed along the copper wiring 2, the molten solution of the metal ball 8 can be led along the copper wiring 2 into the escape opening 6 when the metal ball 8 is connected to the electrode part 3. Therefore, according to this embodiment, a semiconductor device in which the semiconductor chip 7 is bonded in a parallel position to the packaging substrate 1 can be more surely obtained.
Although the embodiment of the present invention has been described in detail, it is clearly understood that the same is by way of an example only for making apparent the technical contents of the invention, and the invention is not to be interpreted as limited to the example but the spirit and scope of the present invention is limited only by the terms of the appended claims.
In the abovementioned embodiment, a WL-CSP technology has been applied to the semiconductor chip 7, but the semiconductor chip 7 has only to be capable of being bonded to the packaging substrate 1 by a flip chip bonding technology and is not limited to one to which a WL-CSP technology has been applied.
This application corresponds to the Japanese Patent Application No. 2004-291731 filed in the Japan Patent Office on Oct. 4, 2004, and the whole disclosure of the Japanese application is incorporated in this application by citation.
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2013Stats Chippac, Ltd.Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframeUS8435834Sep 13, 2010May 7, 2013Stats Chippac, Ltd.Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSPUS8476761May 21, 2012Jul 2, 2013Stats Chippac, Ltd.Semiconductor device and method of confining conductive bump material during reflow with solder mask patchUS8492197Aug 17, 2010Jul 23, 2013Stats Chippac, Ltd.Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrateUS8525350Mar 25, 2010Sep 3, 2013Stats Chippac, Ltd.Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud bumpsUS8558378May 5, 2012Oct 15, 2013Stats Chippac, Ltd.Bump-on-lead flip chip interconnectionUS8563418Oct 7, 2011Oct 22, 2013Stats Chippac, Ltd.Semiconductor device and method of forming vertically offset bond on trace interconnects on different height tracesUS8574959Dec 3, 2010Nov 5, 2013Stats Chippac, Ltd.Semiconductor device and method of forming bump-on-lead interconnectionUS8659172Dec 9, 2010Feb 25, 2014Stats Chippac, Ltd.Semiconductor device and method of confining conductive bump material with solder mask patchUS8741766May 30, 2013Jun 3, 2014Stats Chippac, Ltd.Semiconductor device and method of confining conductive bump material during reflow with solder mask patchUS8742566Dec 26, 2012Jun 3, 2014Stats Chippac, Ltd.Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingersUS8759972Nov 29, 2011Jun 24, 2014Stats Chippac, Ltd.Semiconductor device and method of forming composite bump-on-lead interconnectionUSRE44355Jan 25, 2013Jul 9, 2013Stats Chippac, Ltd.Method of forming a bump-on-lead flip chip interconnection having higher escape routing densityUSRE44377Jul 23, 2012Jul 16, 2013Stats Chippac, Ltd.Bump-on-lead flip chip interconnectionUSRE44431Jul 23, 2012Aug 13, 2013Stats Chippac, Ltd.Bump-on-lead flip chip interconnectionUSRE44500Jan 28, 2013Sep 17, 2013Stats Chippac, Ltd.Semiconductor device and method of forming composite bump-on-lead interconnectionUSRE44524Feb 1, 2013Oct 8, 2013Stats Chippac, Ltd.Bump-on-lead flip chip interconnectionUSRE44562Jul 26, 2012Oct 29, 2013Stats Chippac, Ltd.Solder joint flip chip interconnection having relief structureUSRE44579Feb 1, 2013Nov 5, 2013Stats Chippac, Ltd.Semiconductor device and method of self-confinement of conductive bump material during reflow without solder maskUSRE44608Feb 1, 2013Nov 26, 2013Stats Chippac, Ltd.Solder joint flip chip interconnectionUSRE44761Feb 1, 2013Feb 11, 2014Stats Chippac, Ltd.Solder joint flip chip interconnection having relief structureClassifications U.S. Classification257/738, 257/778, 257/E23.07, 257/E23.069, 257/737, 257/780, 361/768, 361/767, 257/E23.01, 174/255, 257/779International ClassificationH01L23/48Cooperative ClassificationH01L2224/16, H01L2924/01078, H01L23/49838, H01L23/49816European ClassificationH01L23/498C4, H01L23/498GLegal EventsDateCodeEventDescriptionMar 14, 2012FPAYFee paymentYear of fee payment: 4Dec 9, 2005ASAssignmentOwner name: ROHM CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MIYATA, OSAMU;HIGUCHI, SHINGO;REEL/FRAME:017338/0696Effective date: 20051117RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google