Source: http://www.google.com/patents/US7343542?dq=7222078
Timestamp: 2015-01-25 22:46:57
Document Index: 719677131

Matched Legal Cases: ['art1', 'art1', 'art2', 'art2', 'art1', 'art1', 'art2', 'art2', 'art1', 'art2', 'art2']

Patent US7343542 - Methods and apparatuses for variable length encoding - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsMethods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of...http://www.google.com/patents/US7343542?utm_source=gb-gplus-sharePatent US7343542 - Methods and apparatuses for variable length encodingAdvanced Patent SearchPublication numberUS7343542 B2Publication typeGrantApplication numberUS 10/924,647Publication dateMar 11, 2008Filing dateAug 23, 2004Priority dateOct 24, 2002Fee statusPaidAlso published asUS6781529, US20050028070Publication number10924647, 924647, US 7343542 B2, US 7343542B2, US-B2-7343542, US7343542 B2, US7343542B2InventorsChien-Hsin Lin, Mushtaq Sarwar, Mike Lai, Mitchell OslickOriginal AssigneeApple Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (34), Non-Patent Citations (4), Referenced by (2), Classifications (8), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethods and apparatuses for variable length encodingUS 7343542 B2Abstract Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.
1. A method for execution by a microprocessor to perform variable length encoding, the method comprising:
receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded;
generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols, the plurality of first codewords having a plurality of lengths; and
outputting the plurality of first codewords and the plurality of lengths;
wherein the above operations are performed in response to the microprocessor receiving a single instruction.
2. A method as in claim 1 wherein the plurality of parameters comprises a plurality of indices and said generating concurrently the plurality of first codewords further comprises:
looking up simultaneously a plurality of entries from a plurality of look up tables respectively using the plurality of indices to generate the plurality of first codewords.
configuring a plurality of look up units to function as the plurality of look up tables.
4. A method as in claim 3 wherein each of the look up tables utilizes more than one of the plurality of look up units.
5. A method as in claim 2 wherein said generating concurrently the plurality of first codewords further comprises:
combining the plurality of parameters and the plurality of entries to generate the plurality of first codewords.
6. A method as in claim 5 wherein each entry of the plurality of entries comprises a first bit segment representing a second codeword and a second bit segment representing a bit length of the second codeword.
the plurality of parameters further comprises a plurality of sign indicators, each of which indicates a value of a sign bit of a corresponding one of the plurality of symbols;
each of the plurality of entries further comprises a third bit segment indicating whether or not to append a sign bit of a corresponding one of the plurality of symbols; and
a sign bit of a first symbol in the plurality of symbols, which symbol corresponds to a first entry in the plurality of entries, is appended to the second codeword represented by the first bit segment of the first entry when the third bit segment of the first entry indicates to append the sign bit.
8. A method as in claim 6 wherein the plurality of parameters further comprises a plurality of type indicators for the plurality of symbols respectively.
9. A method as in claim 8 wherein a zero is generated as one of the plurality of first codewords to represent a first symbol in the plurality of symbols when one of the plurality of type indicators, which corresponds to the first symbol, has a first value.
the plurality of parameters further comprises a plurality of third codewords, each of the plurality of third codewords corresponding to one of the plurality of symbols; and
one of the plurality of third codewords is used as one of the plurality of first codewords to represent a first symbol in the plurality of symbols when one of the plurality of type indicators, which corresponds to the first symbol, has a second value.
one of the plurality of first codewords that represents a first symbol in the plurality of symbols is generated from concatenating one of the plurality of third codewords that corresponds to the first symbol and the second codeword represented by the first bit segment of a first entry in the plurality of entries, which entry corresponds to the first symbol, when one of the plurality of type indicators, which corresponds to the first symbol, has a third value.
12. A machine readable medium containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to perform variable length encoding, the method comprising:
13. A medium as in claim 12 wherein the plurality of parameters comprises a plurality of indices and said generating concurrently the plurality of first codewords further comprises:
14. A medium as in claim 13 wherein the method further comprises:
15. A medium as in claim 14 wherein each of the look up tables utilizes more than one of the plurality of look up units.
16. A medium as in claim 13 wherein said generating concurrently the plurality of first codewords further comprises:
17. A medium as in claim 16 wherein each entry of the plurality of entries comprises a first bit segment representing a second codeword and a second bit segment representing a bit length of the second codeword.
18. A medium as in claim 17 wherein:
19. A medium as in claim 17 wherein the plurality of parameters further comprises a plurality of type indicators for the plurality of symbols respectively.
20. A medium as in claim 19 wherein a zero is generated as one of the plurality of first codewords to represent a first symbol in the plurality of symbols when one of the plurality of type indicators, which corresponds to the first symbol, has a first value.
21. A medium as in claim 19 wherein:
22. A medium as in claim 19 wherein:
23. A digital processing system to perform variable length encoding, the digital processing system comprising:
means for receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded;
means for generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols, the plurality of first codewords having a plurality of lengths; and
means for outputting the plurality of first codewords and the plurality of lenths;
wherein the above means operate in response to the microprocessor receiving a single instruction.
24. A digital processing system as in claim 23 wherein the plurality of parameters comprises a plurality of indices and said means for generating concurrently the plurality of first codewords further comprises:
means for looking up simultaneously a plurality of entries from a pluralityof look up tables respectively using the plurality of indices to generate the plurality of first codewords.
25. A digital processing system as in claim 24 further comprising:
means for configuring a plurality of look up units to function as the plurality of look up tables.
26. A digital processing system as in claim 25 wherein each of the look up tables utilizes more than one of the plurality of look up units.
27. A digital processing system as in claim 24 wherein said means for generating concurrently the plurality of first codewords further comprises:
means for combining the plurality of parameters and the plurality of entries to generate the plurality of first codewords.
28. A digital processing system as in claim 27 wherein each entry of the plurality of entries comprises a first bit segment representing a second codeword and a second bit segment representing a bit length of the second codeword.
29. A digital processing system as in claim 28 wherein:
the plurality of parameters further comprises a plurality of sign indicators, each of which indicates a value of a sign bit of a corresponding one of the plurality of symbol;
30. A digital processing system as in claim 28 wherein the plurality of parameters further comprises a plurality of type indicators for the plurality of symbols respectively.
31. A digital processing system as in claim 30 wherein a zero is generated as one of the plurality of first codewords to represent a first symbol in the plurality of symbols when one of the plurality of type indicators, which corresponds to the first symbol, has a first value.
32. A digital processing system as in claim 30 wherein:
33. A digital processing system as in claim 30 wherein:
34. A processing system to perform variable length encoding, the processing system comprising:
a plurality of vector registers; and
a vector execution unit coupled to the plurality of vector registers, in response to receiving a single instruction, the vector execution unit:
receiving a plurality of parameters from the plurality of vector registers, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded, generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols, the plurality of first codewords having a plurality of lengths, and outputting the plurality of first codewords and the plurality of lengths to at least one of the plurality of vector registers.
35. A processing system as in claim 34 wherein the vector execution unit further comprises a plurality of look up tables;
the plurality of parameters comprises a plurality of indices; and
the vector execution unit looks up simultaneously a plurality of entries from the plurality of look up tables respectively using the plurality of indices to generate concurrently the plurality of first codewords.
36. A processing system as in claim 35 wherein the vector execution unit comprises a plurality of look up units; and
the vector execution unit configures the plurality of look up units to function as the plurality of look up tables.
37. A processing system as in claim 36 wherein each of the look up tables utilizes more than one of the plurality of look up units.
38. A processing system as in claim 35 wherein the vector execution unit combines the plurality of parameters and the plurality of entries to generate concurrently the plurality of first codewords.
39. A processing system as in claim 38 wherein each entiy of the plurality of entries comprises a first bit segment representing a second codeword and a second bit segment representing a bit length of the second codeword.
40. A processing system as in claim 39 wherein:
41. A processing system as in claim 39 wherein the plurality of parameters further comprises a plurality of type indicators for the plurality of symbols respectively.
42. A processing system as in claim 41 wherein a zero is generated as one of the plurality of first codewords to represent a first symbol in the plurality of symbols when one of the plurality of type indicators, which corresponds to the first symbol, has a first value.
43. A processing system as in claim 41 wherein:
44. A processing system as in claim 41 wherein:
This application is a continuation application of U.S. patent application Ser. No. 10/280,225, filed Oct. 24, 2002 now U.S. Pat. 6,781,529.
FIELD OF THE INVENTION The invention relates to data processing systems using vector processing and Very Long Instruction Word (VLIW) architecture, more particularly to variable length encoding.
Since compressing images is a computational intensive operation, it is desireable to have highly efficient methods and apparatuses to perform run length encoding and variable length encoding.
SUMMARY OF THE DESCRIPTION Methods and apparatuses for variable length encoding using a vector processing unit are described here.
In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding including: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.
In one example according to this aspect, the plurality of parameters includes a plurality of indices; and to generate concurrently the plurality of first codewords, a plurality of entries are looked up simultaneously from a plurality of look up tables, which are configured from a plurality of look up units to function as the plurality of look up tables. Each of the look up tables utilizes more than one of the plurality of look up units. Each entry of the plurality of entries includes a first bit segment representing a second codeword and a second bit segment representing a bit length of the second codeword.
The plurality of parameters further includes a plurality of sign indicators, each of which indicates the value of a sign bit of a corresponding one of the plurality of symbols. Each of the plurality of entries further includes a third bit segment indicating whether or not to append a sign bit of a corresponding one of the plurality of symbols. A sign bit of a first symbol in the plurality of symbols, which corresponds to a first entry in the plurality of entries, is appended to the second codeword represented by the first bit segment of the first entry when the third bit segment of the first entry indicates to append the sign bit.
The plurality of parameters further includes a plurality of type indicators for the plurality of symbols respectively; and the plurality of parameters and the plurality of entries are combined to generate the plurality of first codewords.
When one of the plurality of type indicators, which corresponds to a first symbol in the plurality of symbols, has a first value, a zero is generated as one of the plurality of first codewords to represent the first symbol.
The plurality of parameters further includes a plurality of third codewords, each of the plurality of third codewords corresponding to one of the plurality of symbols.
When one of the plurality of type indicators, which corresponds to a first symbol in the plurality of symbols, has a second value, one of the plurality of third codewords is used as one of the plurality of first codewords to represent the first symbol.
When one of the plurality of type indicators, which corresponds to a first symbol in the plurality of symbols, has a third value, one of the plurality of first codewords that represents the first symbol is generated from concatenating one of the plurality of third codewords that corresponds to the first symbol and the second codeword represented by the first bit segment of a first entry in the plurality of entries, which entry corresponds to the first symbol.
FIG. 29 shows a detailed flow diagram for a method to pack bit streams according to one embodiment of the present invention.
In one embodiment of the present invention, system core logic 140 further includes media processor 101; and the components of system core logic 140 are integrated in a single-chip chipset. More details of a media processor integrated in a system core logic chip are described in a co-pending U.S. patent application, Ser. No. 10/038,700 entitled �Bus Controller Chipset� by Joseph P. Bratt, et al, which application is hereby incorporated here by reference. In another embodiment, a single-chip system logic chipset further includes interfaces to other system logics, such as universal serial bus (USB), Ethernet device, etc. However, in other embodiments, media processor 101 is not integrated in a system core logic chip, or not used (in which case the methods and apparatuses of the present invention can be implemented in at least one host processor).
The processing engine in FIG. 2 contains a set of execution units including: integer arithmetic/logical unit (IALU) 201, integer shift unit (ISHU) 202, floating-point unit (FPU) 203, load/store unit (LSU) 211, vector permute unit (VPU) 205, vector simple integer unit (VSIU) 206, vector complex integer unit (VCIU) 207, vector look-up table unit (VLUT) 208, vector floating-point unit (VFPU) 209, and branch/instruction unit (BRU) 240. Storage elements in the processing engine include: general purpose register file (GPR) 221, vector register file (VR) 231, look-up memory (LUM) 251 (located inside VLUT 208), local memory 213, instruction cache 243, and special purpose registers (SPR) 227. An entry in the vector register file is a vector register; and an entry in the general purpose register file is a scalar register. It is useful to note that a processing engine may contain more or less execution units as shown in FIG. 2. More than one functional unit of a kind may be included. For example,. in one embodiment, a processing engine may contain one IALU, two ISHU, one LSU, and one BRU units.
A vector look-up table unit (e.g., VLUT 208) can look up a vector of data items from a number of look-up tables simultaneously using a vector of indices. Some details of a vector look-up table unit, as well as more details of a VLIW processing engine, are described in a co-pending U.S. patent application, Ser. No. 10/038,351 entitled �Apparatus for Parallel Table Look-Up� by Joseph P. Bratt, et al, which application is hereby incorporated here by reference.
FIG. 6 illustrates an example to compute zero run values. The run values of the list of numbers in vectors vA0 (671), vA1 (673), . . . , vA7 (677) are computed and stored in vectors vD0 (681), vD1(683), . . . , vD7(687). To compute the first vector of run values vD0, a non-zero number is used as a reference (e.g., Bx) such that the first element 601 has a run value of zero (631). It is seen that vD0 contains a run value for each of the elements in vA0, including those which are equal to zero. For example, element 606, which is zero, has a run value of two, which indicates that there are two consecutive zero elements (elements 604 and 605) immediately preceding element 606. To compute run values in vD1, elements 608 and 638 are used as the reference point (Bx and Cx). Since element 608 is zero, one is added to run value 638 to obtain run value 641 for element 611. Thus, the run value (643) of element 613 is three, which indicates that there are three consecutive zero elements (elements 608, 611 and 612) immediately preceding element 613 in the list. Since each of the elements has a run value indicating the number of consecutive zero elements immediately preceding it in the list, an index indicating the location of the last non-zero element in the list can be determined from the number of elements in the list and the run value of the last element in the list. For example, the last element (651) in the list of elements stored in vectors vA0-vA7 is zero. The run value (655) of element 651 is 10. Thus, the last non-zero element is ten elements ahead of the last element (651) in the list. Since the number of elements in the list is 64, the index for element 651 is 63 (assuming the indices start from 0). Thus, the index for the last non-zero element (653) is 63−10−1 =52.
FIG. 10 shows a flow diagram for a method to compute an index pointing to the last non-zero element in a list of elements according to one embodiment of the present invention. If operation 1001 determines that the last element in the list is equal to zero, operation 1003 is used to compute the index pointing to the last non-zero element from the index of the last number; otherwise, operation 1005 is used to compute the index pointing to the last non-zero element from the result of subtracting the run value of the last element from the index of the last element. A1ternatively, a number of zeros can be appended to a given list of elements such that the last element of the expanded list is always zero. When such an expanded list is used, only operation 1005 is necessary.
FIG. 13 illustrates data representations for the execution of an instruction to variable length encode a plurality of symbols according to one embodiment of the present invention. Instruction vecvlc 1300 contains bit segments 1301-1307 for specifying the vector registers (vA, vB, vC) that contain the input data and the vector register (vD) for storing the results. Vector register file 1350 contains entries 1310, 1320, 1330, and 1340 (vector registers vA, vB, vC, and vD). Bit segments 1301, 1303, 1305 and 1307 specify respectively the locations of vector registers vD, vA, vB and vC in the vector register file. Vector register vA contains in bit segments 1311-1314 the vector of levels, which contains the values of the sign bits of the four symbols to be encodes. Vector register vB contains in bit segments 1321-1324 the vector of indices for looking up codewords from look up tables, as well as the vectors of types (in bit segments 1326-1329) for specifying the types of the coding operations, for encoding the four symbols. In one embodiment of the present invention, an execution unit contains 16 look up units; and each of the codeword look up tables contains 512 24-bit entries and, thus, requires 6 look up units. Therefore, only two symbols can be processed concurrently. Vector register vC contains bit segments 1331 and 1333 for specifying two special codewords (e.g., Escape codeword header, or Escape codeword) and bit segments 1332 and 1334 for specifying the bit lengths of the corresponding special codewords. Vector register vD contains bit segments 1341 and 1343 for storing the resulting codewords and bit segments 1342 and 1344 for storing the bit lengths of the corresponding codewords. One instruction is used for computing codewords using Level0 (1311), Level1 (1312), Index0 (1321), Index1 (1322), Type0 (1326) and Type1 (1327) from vector registers vA and vB with the input parameters in vC to generate variable length codewords for the first two symbols; and another instruction is used for computing codewords using Level2 (1313), Level3 (1314), Index2 (1323), Index3 (1324), Type2 (1328) and Type3 (1329) from vector registers vA and vB with the input parameters in vC to generate variable length codewords for the next two symbols (after the parameters in vC are updated for the next two symbols to be encoded when necessary). Since a 56-bit bit segment in input vector register vC is allocated for the storage of each of the special codewords, various formats of escape codes, end-of-block codewords, etc, can be used with instruction vecvlc.
FIG. 18 shows a block diagram representation of a circuit for the execution of a method to concatenate a plurality of variable length codewords according to one embodiment of the present invention. Vector register vA (1801) contains bit segments representing Codeword0 (1803), Codeword1 (1807) and their bit lengths (Length0 1805 and Length1 1809). While right shifter 1811 and logic Or Unit 1813 append Codeword1 (1807) after Codeword0 (1813) to concatenate the two codewords into bit stream 1833, concurrently, adder 1815 sums the bit lengths of Codeword0 and Codeword1 (Length0 1805 and Length1 1809) to compute the bit length (Length 1835) of the resulting bit stream (1833); and testers 1817 and 1819 determine whether the bit lengths of the input codewords (Codeword0 and Codeword1) are larger than zero. When Length0 (1805) for Codeword0 (1803) is zero, bit CCR0 (1823) in a condition register (e.g., special purpose register 227 in FIG. 2) is set to zero, otherwise, CCR0 (1823) is set to one. Similarly, bit CCR1 (1821) in the condition register is set to indicate whether or not Length1 (1809) is zero. The resulting bit stream (1833) and its bit length are stored in vector register vD (1831).
FIG. 24 shows a block diagram representation of a circuit for the execution of a method to pack bit streams according to one embodiment of the present invention. Vector register vB (2403) contains bit segments for specifying an input bit stream 2418 (BitStream) and it bit length 2419 (Length). Vector register vA (2401) contains bit segments for a bit stream 2411 (BitStream1) that has been packed in a previous packing operation and flags 2412 (Flag1) that indicate the state of the previous packing operation. Vector register vA (2401) also contains bit segments for storing parameters 2413-2416 (SrcStart1, SrcEnd1, DestStart1, DestEnd1) from the previous packing operation that can be used to compute the parameters required to perform the current packing operation (e.g., the available space and location for packing the bits from BitStream (2418), and others). More details about these parameters are described further below. Bit stream packing logic 2410 appends the bits from BitStream (2418) after BitStream1(2411) within the available space for packing to generate BitStream2 (2421). Flags 2422 (Flag2) are set to indicate the state of the current packing operation; and updated parameters 2423-2426 (SrcStart2, SrcEnd2, DestStart2, DestEnd2) are generated from the current packing operation. In one embodiment of the present invention, bits in a condition register (CCR0 and CCR1) are set to indicate whether or not all bits in BitStream (2418) are packed into BitStream2 (2421) and whether or not BitStream2 (2421) is fully packed (reached required bit length).
In an alternative embodiment of the present invention, parameters SrcStart1 (2413) and SrcEnd1 (2414) are used to indicate in BitStream (2418) the locations of the starting and ending bits of the input bit segment of BitStream (2418) to be packed by bit stream packing logic 2410 in the current packing operation; and parameters DestStart1 (2415) and DestEnd1 (2416) are used to indicate the locations of the starting and ending bits of the bit segment in a resulting bit stream that may be used to pack the bits from BitStream by bit steam packing logic 2410 in the current packing operation. Similarly, SrcStart2 (2423), SrcEnd2 (2424), DestStart2 (2425), DestEnd2 (2426) are updated by bit stream packing logic 2410 to indicate the remaining bits in BitStream (2418) that needs to be packed in the next packing operation, if any, and the available space in vD (2405) for the next packing operation. More details about such an embodiment are described below with the description of FIG. 26.
Multiplexer 2641 and tester 2643 select the smaller one from AvailSpace (2631) and InputBitLength (2633) as BitLength (2635), which is the number of bits to be packed in the current packing operation. Tester 2643 produces Underflow 2637, which indicates whether or not InputBitLength (2633) is smaller than AvailSpace (2631). When Underflow (2637) is one, multiplexer 2653 selects the sum of DestStart1 (2615) and BitLength (2635) as DestStart2 (2625) to indicate that the start point for packing the next bit stream is after the last bit packed in this operation; otherwise, multiplexer 2653 selects zero as DestStart2. DestEnd1 is saved as DestEnd2 without any modification.
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H03M13/00, H03M7/42Cooperative ClassificationH03M7/42European ClassificationH03M7/42Legal EventsDateCodeEventDescriptionAug 10, 2011FPAYFee paymentYear of fee payment: 4Apr 26, 2007ASAssignmentOwner name: APPLE INC., CALIFORNIAFree format text: CHANGE OF NAME;ASSIGNOR:APPLE COMPUTER, INC., A CALIFORNIA CORPORATION;REEL/FRAME:019231/0555Effective date: 20070109RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services