Source: https://patents.google.com/patent/US20080036631A1/en
Timestamp: 2019-09-18 14:54:33
Document Index: 379985964

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

US20080036631A1 - Low output skew double data rate serial encoder - Google Patents
US20080036631A1
US20080036631A1 US11/463,129 US46312906A US2008036631A1 US 20080036631 A1 US20080036631 A1 US 20080036631A1 US 46312906 A US46312906 A US 46312906A US 2008036631 A1 US2008036631 A1 US 2008036631A1
US8723705B2 (en
The present application claims priority to application Ser. No. 11/285,397 entitled “Double Data Rate Serial Encoder” filed Nov. 23, 2005, which claims priority to Provisional Application No. 60/630,853 entitled “MDDI Host Core Design” filed Nov. 24, 2004, Provisional Application No. 60/631,549 entitled “Mobile Display Digital Interface Host Camera Interface Device” filed Nov. 30, 2004, Provisional Application No. 60/632,825 entitled “Camera MDDI Host Device” filed Dec. 2, 2004, Provisional Application No. 60/633,071 entitled “MDDI Overview” filed Dec. 2, 2004, Provisional Application No. 60/633,084 entitled “MDDI Host Core Pad Design” filed Dec. 2, 2004, and Provisional Application No. 60/632,852 entitled “Implementation of the MDDI Host Controller” filed Dec. 2, 2004, which are assigned to the assignee hereof and hereby expressly incorporated herein by reference in their entireties.
Further, according to embodiments of the invention, an MDDI host may comprise one of several types of devices that can benefit from using the present invention. For example, the host could be a portable computer in the form of a handheld, laptop, or similar mobile computing device. It could also be a Personal Data Assistant (PDA), a paging device, or one of many wireless telephones or modems. Alternatively, the host could be a portable entertainment or presentation device such as a portable DVD or CD player, or a game playing device.
Furthermore, the host can reside as a host device or control element in a variety of other widely used or planned commercial products for which a high speed communication link with a client is desired. For example, a host could be used to transfer data at high rates from a video recording device to a storage based client for improved response, or to a high resolution larger screen for presentations. An appliance such as a refrigerator that incorporates an onboard inventory or computing system and/or Bluetooth connections to other household devices, can have improved display capabilities when operating in an internet or Bluetooth connected mode, or have reduced wiring needs for in-the-door displays (a client) and keypads or scanners (client) while the electronic computer or control systems (host) reside elsewhere in the cabinet. In general, those skilled in the art will appreciate the wide variety of modern electronic devices and appliances that may benefit from the use of this interface, as well as the ability to retrofit older devices with higher data rate transport of information utilizing limited numbers of conductors available in either newly added or existing connectors or cables. At the same time, an MDDI client may comprise a variety of devices useful for presenting information to an end user, or presenting information from a user to the host. For example, a micro-display incorporated in goggles or glasses, a projection device built into a hat or helmet, a small screen or even holographic element built into a vehicle, such as in a window or windshield, or various speaker, headphone, or sound systems for presenting high quality sound or music. Other presentation devices include projectors or projection devices used to present information for meetings, or for movies and television images. Other examples include the use of touch pads or sensitive devices, voice recognition input devices, security scanners, and so forth that may be called upon to transfer a significant amount of information from a device or system user with little actual “input” other than touch or sound from the user. In addition, docking stations for computers and car kits or desk-top kits and holders for wireless telephones may act as interface devices to end users or to other devices and equipment, and employ either clients (output or input devices such as mice) or hosts to assist in the transfer of data, especially where high speed networks are involved. However, those skilled in the art will readily recognize that the present invention is not limited to these devices, there being many other devices on the market, and proposed for use, that are intended to provide end users with high quality images and sound, either in terms of storage and transport or in terms of presentation at playback. The present invention is useful in increasing the data throughput between various elements or devices to accommodate the high data rates needed for realizing the desired user experience.
It is noted that the four logic layers 326, 328, 330, and 332 of multiplexer circuitry 324 are based on combinatorial logic and are not driven by clock signals.
Accordingly, signal propagation delays on different paths from the final data register stage and/or the select input register stage to the encoder output may be different.
Further, signal propagation delays could vary according to temperature and/or process variations in the encoder circuitry, making them difficult to monitor and/or to compensate for.
Typically, having different signal propagation delays on paths to the encoder output results in what is known as “output skew”, with the actual encoder output being skewed or distorted relative to a desired nominal output. Output skew may also result from the skewing of a single signal that contributes to the encoder output.
Flip-flops 634 and 636 are feedback flip-flops of the final data register stage having their outputs cross-coupled to XOR gates 628 and 630 of the first XOR stage.
In other embodiments, the feedback signals to XOR gates 628 and 630 are provided from the outputs of flip-flops 638 and 632 respectively, with flip-flops 634 and 636 eliminated from the final data register stage. A more stable design, however, is achieved by using flip-flops 634 and 636 to provide the feedback signals to the first XOR stage. This reduces any additional routing of the outputs of flip-flops 632 and 638, which then need to only be input into the final XOR stage of synchronizing circuit 626.
a synchronizing circuit coupled to the output of the multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit substantially eliminates any output glitches from the output of the multiplexer.
3. An encoder according to claim 1, wherein the multiplexer is a non-glitchless multiplexer.
7. An encoder according to claim 1, wherein the synchronizing circuit comprises a final data register stage.
8. An encoder according to claim 7, wherein the final data register stage is clock-driven.
9. An encoder according to claim 7, wherein the final data register is separated by a single logic layer from the output of the serial encoder, thereby resulting in a low output skew of the encoder.
10. An encoder according to claim 7, wherein the output of the serial encoder is solely determined by two signals from the final data register stage of the synchronizing circuit, thereby resulting in a low output skew of the encoder.
11. An encoder according to claim 1, wherein the encoder receives a parallel data input and serially outputs the data input onto a serial communications link.
12. An encoder according to claim 11, wherein the serial communications link is a Mobile Display Digital Interface (MDDI) link.
13. An encoder according to claim 1, wherein the synchronizing circuit is implemented using any dual edge flip-flop.
14. A serial encoder, comprising:
means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output.
15. A serial encoder according to claim 14, wherein said means for eliminating glitches includes a synchronizing circuit.
16. A serial encoder according to claim 14, wherein said serial outputting means outputs a bit at every edge of a clock signal, thereby making the serial encoder a double data rate encoder.
17. A serial encoder according to claim 14, wherein said means for eliminating glitches includes a clock-driven register stage.
18. A serial encoder according to claim 17, wherein said register stage is separated by a single logic layer from the serial encoder output, thereby resulting in a low output skew of the encoder.
19. A serial encoder according to claim 17, wherein the serial encoder output is solely determined by two signals from said register stage, thereby resulting in a low output skew of the encoder.
20. A serial encoder according to claim 14, wherein the encoder receives a parallel data input and serially outputs the data input onto a serial communications link.
21. A serial encoder according to claim 20, wherein the serial communications link is a Mobile Display Digital Interface (MDDI) link.
22. A serial encoder according to claim 14, wherein said means for eliminating glitches includes a dual edge flip-flop.
US8723705B2 US8723705B2 (en) 2014-05-13
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