Source: http://www.google.com/patents/US7676533?dq=7069184
Timestamp: 2014-11-28 17:12:20
Document Index: 424859712

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'art 200', 'art 300']

Patent US7676533 - System for executing SIMD instruction for real/complex FFT conversion - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn FFT conversion instruction based on a single instruction multiple data (�SIMD�) technique is executed to reduce the number of cycles for software to perform conversion processing used in an FFT computation. In an embodiment, the FFT conversion instruction implements two instances of a conversion...http://www.google.com/patents/US7676533?utm_source=gb-gplus-sharePatent US7676533 - System for executing SIMD instruction for real/complex FFT conversionAdvanced Patent SearchPublication numberUS7676533 B2Publication typeGrantApplication numberUS 10/953,584Publication dateMar 9, 2010Filing dateSep 30, 2004Priority dateSep 29, 2003Fee statusPaidAlso published asUS20050102341Publication number10953584, 953584, US 7676533 B2, US 7676533B2, US-B2-7676533, US7676533 B2, US7676533B2InventorsMark TauntonOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (13), Non-Patent Citations (10), Classifications (7), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSystem for executing SIMD instruction for real/complex FFT conversionUS 7676533 B2Abstract An FFT conversion instruction based on a single instruction multiple data (�SIMD�) technique is executed to reduce the number of cycles for software to perform conversion processing used in an FFT computation. In an embodiment, the FFT conversion instruction implements two instances of a conversion operation, i.e., 2-way SIMD, over two sets of complex points at once. A control register or variant opcode controls an inverse flag to control the behavior of the conversion process. In an embodiment, the control register contains a control bit to select between forward and inverse FFT context.
CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 60/506,732, filed Sep. 30, 2003, by Taunton, entitled �SIMD Instruction for Real/Complex FFT Conversion,� incorporated herein by reference in its entirety.
This application also claims the benefit of U.S. Provisional Application No. 60/506,487, filed Sep. 29, 2003, by Taunton, entitled �SIMD Instruction for Flexible FFT Butterfly,� incorporated herein by reference in its entirety.
This application also claims the benefit of U.S. Provisional Application No. 60/507,522, filed Oct. 2, 2003, by Taunton et al., entitled �Processor Execution Unit for Complex Operations,� incorporated herein by reference in its entirety.
This application also claims the benefit of U.S. Provisional Application No. 60/506,355, filed Sep. 29, 2003, by Taunton, entitled �SIMD Instruction for Complex Multiplication,� incorporated herein by reference in its entirety.
�Method, System, and Computer Program Product for Executing SIMD Instruction for Flexible FFT Butterfly,� U.S. patent application Ser. No. 10/952,169, by Mark Taunton, filed Sep. 29, 2004, incorporated herein by reference in its entirety; and �Methods for Performing Multiplication Operations on Operands Representing Complex Numbers,� U.S. patent application Ser. No. 10/951,867, by Mark Taunton, filed Sep. 29, 2004, incorporated herein by reference in its entirety. COPYRIGHT NOTICE A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection of the facsimile reproduction by any one of the patent document or patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
SUMMARY OF THE INVENTION The present invention is directed to methods, systems, and computer program products for performing an FFT computation. The present invention includes an FFT conversion instruction based on Single Instruction Multiple Data (�SIMD�) techniques. The FFT conversion instruction reduces the number of cycles needed to perform a conversion stage during an inverse or forward FFT computation. In an embodiment, the FFT conversion instruction of the present invention is implemented such that (typically using pipelining in the processor) a new instance of the FFT conversion instruction can be initiated every processor cycle, which reduces the cost of the conversion operation for a more efficient FFT computation.
In an embodiment, the FFT conversion instruction is executed during one stage of an FFT computation that performs an inverse FFT between N �complex� frequency-domain points and 2N �real� time-domain points. First, a standard representation or standard form of complex frequency-domain data is accessed for input. The standard form of frequency-domain data includes N points of complex amplitudes of distinct component frequencies. Next, the N points of complex frequency-domain data are �converted,� by executing use of the FFT conversion instruction of the present invention one or more times, into a modified data structure that includes N points of modified complex frequency-domain data. An N-point inverse FFT is performed on the N points of modified complex frequency-domain data to produce N points of complex time-domain data. Thereafter, the N points of complex time-domain data are rearranged by interleaving the N real and N imaginary data values of the complex data into a 2N-point output array which can represent purely real time-domain data values.
To control behavior of the FFT conversion instruction, a separate control register is provided to control an �inverse� flag. The control register contains a control bit that is utilized to select between forward and inverse FFT context. In another embodiment, variant opcodes are utilized to give behavioral control of the conversion operation, e.g. an FFT conversion instruction using one opcode can be used to perform a forward FFT conversion and an FFT conversion instruction using a different opcode can be used to perform an inverse FFT conversion.
BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES The present invention will be described with reference to the accompanying drawings.
DETAILED DESCRIPTION OF THE INVENTION The Fast Fourier Transform (FFT) conversion instruction of the present invention reduces the number of cycles needed to perform a conversion operation during an inverse and/or forward FFT computation using a single instruction multiple data (SIMD) technique. In an embodiment, the FFT conversion instruction is executable within a conversion stage of an FFT computation that transforms data between the frequency domain and the time domain (in either direction) within a digital signal processing environment. For example, an inverse FFT computation is executed at a transmitter to convert data values to be modulated (represented as complex amplitudes of distinct component frequencies) into a sequence of points in the time domain, which will form the basis of an analog signal subsequently transmitted. At a receiver, a reverse process uses the forward FFT computation to recreate the frequency-domain version of a received signal, which is then decoded to derive the communicated data values.
In an embodiment, the FFT conversion instruction directly implements two instances of an FFT conversion operation (i.e., 2-way SIMD) over two instances of two complex points at once. To control behavior of the conversion operation, a separate control register is provided to control an �inverse� flag. The control register contains a control bit that is utilized to select between forward and inverse FFT context. In another embodiment, variant opcodes are utilized to maintain behavioral control of the conversion operation, e.g. an FFT conversion instruction using one opcode can be used to perform a forward FFT conversion and an FFT conversion instruction using a different opcode can be used to perform an inverse FFT conversion.
FIG. 1 illustrates a logical representation of an FFT conversion operation 100 that translates between two representations of complex data, representing, for instance, the complex amplitudes of signals represented in the frequency domain. One or more examples of an instruction for implementing the somewhat similar �FFT butterfly� operation are described in the application entitled, �Method, System, and Computer Program Product for Executing SIMD Instruction for Flexible FFT Butterfly,� U.S. patent application Ser. No. 10/952,169, by Mark Taunton, filed Sep. 29, 2004, incorporated herein by reference in its entirety.
SumR=(a.re+b.re)/2SumI=(a.im+b.im)/2DiffR=(a.re−b.re)/2DiffI=(a.im−b.im)/2 SrDi=complex(SumR,DiffI) DrSi=complex(DiffR,SumI)Prod=DrSi�W A=SrDi+Prod B=complex(SrDi.re−Prod.re, Prod.im−SrDi.im) Equation 1
A �standard method� for implementing FFT computations (both forward and inverse) in such cases involves the use of a transform operating on 2N complex points. In the time domain (i.e., at the output of an inverse FFT, or the input of a forward FFT), the data values in the imaginary axis are required or assumed to be zero.
In the standard method for a forward FFT, this case is handled by setting the imaginary parts of the FFT complex input array to zero, and the real parts of the FFT complex input array to the values of 2N purely real time-domain data points to be transformed. A 2N-point forward FFT is then performed. The FFT output array, which consists of 2N complex points in the frequency domain, would automatically possess a mathematical property known as Hermitian symmetry, in which values of the upper half of the FFT output array would have a direct relationship to values in the lower half of the array. The rule is that for an array of 2N values numbered [0 . . . (2N−1)], possessing Hermitian symmetry, entry �2N-i� has a complex value equal to the complex conjugate of entry �i�. Thus, since the last N output values in the FFT output array will in the case under consideration represent the complex conjugate of the first N output values, there is no additional information that can be derived from the last N output values that is not already known from the first N output values. Therefore, the first N complex frequency-domain values contain all information representing the original 2N real points of time-domain data.
After the �N points� of incoming �complex� frequency-domain data has been transformed into a sequence of �2N points� of �real� time-domain data, the control flow ends as indicated at step 295.
As discussed above, step 206 in FIG. 2 and step 312 in FIG. 3 describe a conversion operation that, when executed, converts between a modified form and a standard form of elements of a complex frequency-domain data array. In an embodiment of the present invention, the conversion stage of the FFT computation, step 206 of the inverse FFT computation, or step 312 of the forward FFT computation, is described by the following pseudo code that represents the abstract function �CVT.� The function �CVT� in turn uses a conversion step �CVT_step� to convert two complex input values (such as, input values 102 and 104) into two complex output values (such as, output values 108 and 110). The function identified as conversion step CVT_step is one representation of the FFT conversion operation 100 of the present invention, as may be seen by comparison of it with Equation 1.
The following observations can be noted from the above CVT function. When �m� is zero and also when �m� is equal to N/2, the computation has redundant elements since �ix=iy� and so the same result is produced twice. The parameters �in[N]� and �out[N]� are arrays of N complex values. The notation �val.re� refers to the real part of the complex value �val�. Likewise, the notation �val.im� refers to the imaginary part of �val�. The parameter �inverse� is a logical control value that indicates whether the CVT function is being used as part of an inverse FFT (when true) or an forward FFT (when false). In an embodiment, the functions �sin� and �cos� used above can be replaced by a look-up into a table of constants for the particular value of angle, as determined by the index �m�. The arithmetic mode implied in the CVT function is as arbitrary real numbers (e.g., the �sin� and �cos� values are all real, between −1 and 1). Fixed point or floating point arithmetic can be used.
As discussed above with reference to FIG. 2 and FIG. 3, the input data points are complex frequency-domain data values represented in either standard form if an inverse FFT will be performed, or modified form if a forward FFT will be performed. In an embodiment, the parameter �inverse� 418 determines the direction of the transform and, hence, the form (i.e., modified or standard) of the input data points, as described in the above CVT function.
Next in data flow diagram 400, at complex multiplier unit 416, the complex value DrSi is multiplied by the complex twiddle factor operand 406, yielding as result another complex value, the product (Prod of Equation 1). As previously discussed, FFT conversion operation 100, as represented in data flow diagram 400, can be utilized during a conversion stage of a forward or inverse FFT, to convert between a standard form and a modified form of complex frequency-domain data. The direction of the transform in which the FFT conversion stage is used determines whether the conversion products are computed by accepting inputs in a modified form to produce outputs in a standard form or accepting inputs in a standard form to produce outputs in a modified form. As discussed above with reference to FIG. 2 and FIG. 3, the conversion operation is configured to produce a modified form for an inverse FFT, and a standard form for a forward FFT. In order to configure the function of the FFT conversion operation for the appropriate direction of transform, a signal 418 �inverse� is used; this is applied as a control signal to the complex multiplier unit 416. Its effect is that signal 416 is inactive (�not inverse�), the complex multiplier 416 performs a standard complex multiplication of the complex operand DrSi by the complex twiddle factor operand 406; when the signal 418 is active (�inverse�), the complex multiplier 416 performs a complex multiplication equivalent in effect to multiplying complex operand DrSi by the complex conjugate of complex twiddle factor operand 406. In an embodiment, the complex multiplication with optional conjugation of one operand is performed as described in U.S. Provisional Application No. 60/506,355, filed Sep. 29, 2003, by Taunton, entitled �SIMD Instruction for Complex Multiplication,� incorporated herein by reference in its entirety, or in U.S. patent application Ser. No. 10/951,867, filed Sep. 29, 2004, by Taunton, entitled �Methods for Performing Multiplication Operations on Operands Representing Complex Numbers,� incorporated herein by reference in its entirety.
At subtracter unit 422, a modified form of complex subtraction takes place; it should be noted that this is not a simple complex subtraction of the two terms SrDi and Prod, as might be expected. Rather it is modified in that the real part of Prod (Prod.re) is subtracted from the real part of SrDi (SrDi.re, also known as SumR), but the imaginary part of SrDi (SrDi.im, also known as DiffI) is subtracted from the imaginary part of Prod (Prod.im), rather than the other way which would be the case for a �normal� complex subtraction of Prod from SrDi (the output of the modified complex subtraction is effectively the complex conjugate of the output of a normal complex subtraction). The complex value resulting from this modified complex subtraction operation forms the second complex output operand 410 (comprised of real part in field H0 and imaginary part in field H1), representing complex output value B 110.
A SIMD digital processor can execute a single instruction to control the processing of multiple data values in parallel. To illustrate the principles of SIMD working, refer to FIG. 5, and consider the following instruction that is executable on the FirePath� digital processor produced by Broadcom Corporation (Irvine, Calif.):
The instruction mnemonic ADDH is an abbreviation for �ADD Halfwords�, where a halfword is the term used for a 16-bit quantity on the FirePath� processor. The instruction �ADDH c, a, b� takes as input two 64-bit operands 502 (i.e., �a� in the instruction) and 504 (i.e., �b) in the instruction), and writes the results back to a 64-bit operand 506 (i.e., �c� in the instruction). ADDH performs four 16-bit (halfword) additions: the value in each 16-bit lane (shown as H0, H1, H2, and H3) in input register 502 is added to the corresponding value in each 16-bit lane (shown as H0, H1, H2, and H3) in 504 to produce four 16-bit results (shown as H0, H1, H2, and H3) in output register 506, which is a 64-bit register.
The above-described SIMD method allows for a great increase in computational power compared with earlier types of processors where an instruction can only operate on a single set of input data values (e.g., one 16-bit operand from input register 502, one 16-bit operand from input register 504, giving one 16-bit result in output register 506). For situations�common in digital signal processing applications�where the same operation is to be performed repeatedly across an array of values, the above-described SIMD method allows a significant speed-up. In the above example, the speed-up is by a factor of four in the basic processing rate, since four add operations can be performed at once rather than only one.
The FFT conversion instruction of the present invention, including the FFT conversion operation 100, can be executed in multiple pipelines on a SIMD microprocessor, such as the FirePath� processor produced by Broadcom Corporation (Irvine, Calif.) and implemented in devices such as the BCM6510 and BCM6411 chips produced by Broadcom Corporation. One or more examples of a SIMD execution unit that is useful for implementing the present invention are described in the application entitled �Processor Execution Unit for Complex Operations� (U.S. Patent App. Ser. No. 60/507,522), which is incorporated herein by reference as though set forth in its entirety.
The FFT conversion instruction of the present invention addresses these concerns by reducing the number of cycles needed for software to perform a conversion operation (e.g., the conversion step �CVT_step� described in the above abstract function �CVT�) used in the conversion stage of a forward or inverse FFT, and therefore enables an increase in efficiency of FFT computations. As described in greater detail below, the FFT conversion instruction processes a plurality of instances of a conversion operation (e.g., 2-way SIMD, 4-way SIMD, 8-way SIMD, etc.) over two sets of complex points at once. In the case of more than 2-way SIMD arrangements, the issue of the ordering of the individual complex values in the input and output operands, wherein the values in the a input 102 and the A output 108 are dealt with in reverse order compared to the order of values in the other operands, can be extended easily in an obvious manner. In an embodiment, control of the behavior of the FFT conversion instruction is by means of a separate control register that contains a control bit to select between forward and inverse FFT context. To determine the behavior of the conversion operation, the control register can be utilized to control an �inverse� signal 418. The contents of the control register, and thus the state of signal 418, can be altered by the programmer. In another embodiment, the behavior of the FFT conversion instruction is controlled by variant opcode. For example, one opcode present as part of the instruction format which identifies an FFT conversion instruction can cause that the FFT conversion instruction to perform a conversion suitable for use in a forward FFT computation (by generating a suitable value for �inverse� signal 418), and another different opcode can cause the instruction to perform a conversion operation suitable for an inverse FFT computation, but generating an alternative value for �inverse� signal 418.
The FFT conversion instruction in execution performs a complete conversion step (e.g., the conversion step �CVT_step� described in the above abstract function �CVT�) for each of the 2 SIMD lanes of the input operands. The input values (a1, b0, W0) form one set of input values to convert, producing outputs A1 and B0. The input values (a0, b1, W1) form the other set, producing outputs A0 and B1.
In an embodiment, the FFT conversion instruction of the present invention is implemented such that (typically using pipelining in the processor) a new instance of the FFT conversion instruction can be initiated (if so programmed in software) on every processor cycle. By comparison, the equivalent operations on a processor not having the capability to execute the FFT conversion instruction of the present invention would typically cost eight cycles or more. Therefore, the FFT conversion instruction of the present invention reduces the cost of the conversion process (e.g., the conversion step �CVT_step� described in the above abstract function �CVT�) for a more efficient FFT execution.
An example implementation of the present invention is provided below in Function A, which includes pseudo code for the FFT conversion instruction of the present invention. The exemplary FFT conversion instruction is called �BFLYCH�, which is short for ButterFLY Conversion on Halfwords; however the choice of name or mnemonic here is incidental and any name could be used. (The use of the term Butterfly relates to the �FFT butterfly� operation which is a commonly used operation in implementing the main stages of the FFT as at step 209 of flowchart 200 or step 309 of flowchart 300. The FFT butterfly operation is described by Proakis, J. G. & Manolakis, D. G. in Digital Signal Processing, New York, Maxwell Macmillan, 1992, Chapter 9, ISBN 0-02-946378, incorporated herein by reference. The structure of the FFT conversion operation of the present invention has some similarity to the structure of FFT butterfly operation (but also several differences), hence the use of this name.) Instruction BFLYCH can be invoked for execution on a SIMD processor (adapted to execute the FFT conversion instruction of the present invention) by using an instruction line of the form:
The operation performed by instruction BFLYCH takes the original values of aA and bB as its two complex data inputs (i.e., input values a 102 and b 104, each comprising two complex values for a and two complex values for b), and the value of W as its twiddle factor input (i.e. twiddle factor values W0 and W1 forming twiddle factor 106). Upon completion, two 64-bit result operands (i.e. 408 and 410, representing output values A 108 and B 110, each comprised of two complex values) are written back to aA and bB, replacing the original values in those operands. An additional source of values used in the execution of instruction BFLYCH is a control register. In Function A (below), the variable BSR (which stands for the incidental name �Butterfly Status Register�) refers to the control register which contains a control bit called �Inverse�, which allows the FFT direction (forward or inverse) to be controlled. The control value of BSR.Inverse could alternatively be derived from use of variant opcodes as described above.
The instruction's behavior, including the effect of the control bit (or variant opcode) for the control signal BSR.Inverse, is described by the following pseudo code represented in Function A, in which �sN�, �dN�, �sum�, �diff�, �DiffR�, �ResultA�, and �ResultB� are internal temporary values:
sN=AVRSH (aA, bB)dN=DVRSH (aA, bB)sum.H0=sN.H0sum.H1=dN.H1sum.H2=sN.H2sum.H3=dN.H3diff.H0=dN.H0diff.H1=sN.H1diff.H2=dN.H2diff.H3=sN.H3DiffR=COMPMUL(diff, W)ResultA.H0=SSH(RNE15(ADDX(SHL15(Sum.H2), DiffR-X2)))ResultA.H1=SSH(RNE15(ADDX(DiffR.X3, SHL15(Sum.H3))))ResultA.H2=SSH(RNE15(ADDX(SHL15(Sum.H0), DiffR.X0)))ResultA.H3=SSH(RNE15(ADDX(DiffR.X1, SHL15(Sum.H1))))ResultB.H0=SSH(RNE15(SUBX(SHL15(Sum.H0), DiffR.X0)))ResultB.H1=SSH(RNE15(SUBX(DiffR.X1, SHL15(Sum.H1))))ResultB.H2=SSH(RNE15(SUBX(SHL15 (Sum.H2), Diff.X2)))ResultB.H3=SSH(RNE15(SUBX(Diff.X3, SHL15 (Sum.H3))))aA=ResultAbB=ResultB The various sub-functions used above are now defined.
SSH(v)=−32768, v<−32768;SSH(v)=+32767, v>+32767;SSH(v)=v, otherwise.
result.<14 . . . 0>=0result.<30 . . . 15>=v.<15 . . . 0>result.<31>=v.15result.<32>=v.15
val.n where n is an integer constant, means bit n of value val, where bit 0 is the least significant bit and bit 1 is the next more significant bit, etc.val.{i,j,k, . . . } where i,j,k, . . . are integer constants, is a shorthand way of writing val.i, valj, val.k, . . .val.<m . . . n> where m and n are integer constants and m>n, means the linear bit sequence (val.m, val.(m−1), . . . val.n) considered as an ordered composite multi-bit entity where val.m is the most significant bit and val.n the least significant bit of the sequenceval.H0 is equivalent to val.<15 . . . 0>val.H1 is equivalent to val.<31 . . . 16>val.H2 is equivalent to val.<47 . . . 32>val.H3 is equivalent to val.<63 . . . 48>val.X0 is equivalent to val.<32 . . . 0>val.X1 is equivalent to val.<65 . . . 33>val.X2 is equivalent to val.<98 . . . 66>val.X3 is equivalent to val.<131 . . . 99>
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4769779Dec 16, 1985Sep 6, 1988Texas Instruments IncorporatedSystolic complex multiplierUS6377970Mar 31, 1998Apr 23, 2002Intel CorporationMethod and apparatus for computing a sum of packed data elements using SIMD multiply circuitryUS6421696Aug 17, 1999Jul 16, 2002Advanced Micro Devices, Inc.System and method for high speed execution of Fast Fourier Transforms utilizing SIMD instructions on a general purpose processorUS6609140 *Nov 30, 2000Aug 19, 2003Mercury Computer Systems, Inc.Methods and apparatus for fast fourier transformsUS6839728 *Jun 22, 1999Jan 4, 2005Pts CorporationEfficient complex multiplication and fast fourier transform (FFT) implementation on the manarray architectureUS6963891 *Apr 4, 2000Nov 8, 2005Texas Instruments IncorporatedFast fourier transformUS7197095Dec 1, 2004Mar 27, 2007Interstate Electronics CorporationInverse fast fourier transform (IFFT) with overlap and addUS7197525Mar 14, 2003Mar 27, 2007Analog Devices, Inc.Method and system for fixed point fast fourier transform with improved SNRUS7233968 *Apr 30, 2003Jun 19, 2007Samsung Electronics Co., Ltd.Fast fourier transform apparatusUS7315878 *Sep 22, 2003Jan 1, 2008Lg Electronics, Inc.Fast Fourier transform deviceUS20050071403Sep 29, 2004Mar 31, 2005Broadcom CorporationMethod, system, and computer program product for executing SIMD instruction for flexible FFT butterflyUS20050071414Sep 29, 2004Mar 31, 2005Broadcom CorporationMethods for performing multiplication operations on operands representing complex numbersUS20050102342Aug 18, 2003May 12, 2005Greene Jonathan E.Methods and apparatus for fast fourier transforms* Cited by examinerNon-Patent CitationsReference1BCM6410/6420 Product Brief, 2 pages, Broadcom Corporation (2003).2Clark, P. "Broadcom's Firepath combines RISC, DSP elements," 2 pages, printed from www.commsdesign.com/showArticle.jhtml?articleID=10808435, 2 pages (Jun. 13, 2001).3Hot Chips 14 Archives (2002) General Information, 5 pages, printed from http://www.hotchips.org/archives/hc14/, (2002).4Office Action mailed Jan. 22, 2008 in U.S. Appl. No. 10/952,169 (File Wrapper Paper No. 20080116).5Office Action mailed May 22, 2008 in U.S. Appl. No. 10/952,169 (File Wrapper Paper No. 20080519).6Office Action mailed May 29, 2009 in U.S. Appl. No. 10/952,169 (File Wrapper Paper No. 20090527).7Office Action mailed Oct. 17, 2008 in U.S. Appl. No. 10/952,169 (File Wrapper Paper No. 20081015).8Proakis, J.G. and Manolakis, D.G., Digital Signal Processing: Principles, Algorithms, and Applications, Second Edition, Macmillan Publishing Company, pp. 684-760 (1992).9Wilson, S., Firepath(TM) Processor Architecture and Microarchitecture, 24 pages, downloaded from www.hotchips.org/archives/hc14, (presented Aug. 20, 2002).10Wilson, S., Firepath� Processor Architecture and Microarchitecture, 24 pages, downloaded from www.hotchips.org/archives/hc14, (presented Aug. 20, 2002).Classifications U.S. Classification708/404International ClassificationG06F17/14, G06F15/00Cooperative ClassificationG06F9/30014, G06F17/142European ClassificationG06F9/30A1A, G06F17/14F2Legal EventsDateCodeEventDescriptionSep 9, 2013FPAYFee paymentYear of fee payment: 4Sep 30, 2004ASAssignmentOwner name: BROADCOM CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAUNTON, MARK;REEL/FRAME:015858/0573Effective date: 20040930Owner name: BROADCOM CORPORATION,CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAUNTON, MARK;US-ASSIGNMENT DATABASE UPDATED:20100309;REEL/FRAME:15858/573RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google