Source: http://www.google.es/patents/US9490230
Timestamp: 2017-10-23 06:32:33
Document Index: 209229211

Matched Legal Cases: ['Application No. 61', 'Application No. 200980149285', 'Application No. 201080035256', 'Application No. 201180031606', 'Application No. 201310240369', 'Application No. 05736129', 'Application No. 2010', 'Application No. 2011540873', 'Application No. 2012', 'Application No. 2012', 'Application No. 05736129', 'Application No. 099137634', 'Application No. 098108067', 'Application No. 098119939', 'Application No. 099136720', 'Application No. 10117575']

Patente US9490230 - Selective die electrical insulation by additive process - Google Patentes
Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according...http://www.google.es/patents/US9490230?utm_source=gb-gplus-sharePatente US9490230 - Selective die electrical insulation by additive process
Número de publicación US9490230 B2
Número de solicitud US 14/868,090
Fecha de prioridad 27 Oct 2009
También publicado como US9147583, US20110266684, US20160020188, WO2011056668A2, WO2011056668A3
Número de publicación 14868090, 868090, US 9490230 B2, US 9490230B2, US-B2-9490230, US9490230 B2, US9490230B2
Inventores Jeffrey S. Leal
Citas de patentes (308), Otras citas (162), Clasificaciones (41), Eventos legales (4)
Selective die electrical insulation by additive process
US 9490230 B2
Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.
1. A method for forming a stacked die assembly, comprising:
on a plurality of die, electrically insulating a selected interconnect pad of a plurality of interconnect pads exposed at a selected region of a die by selectively applying a dielectric material onto the selected interconnect pad in the selected region of the die by selectively depositing at least one of a spot or a line of dielectric material via a nozzle onto the selected region of the die, the selectively depositing leaving nonselected interconnect pads exposed and free from depositing of the dielectric material thereon, such that the nonselected interconnect pads are available for electrical interconnection without requiring the deposited dielectric material to be removed from the nonselected interconnect pads, the nozzle being controlled so that the dielectric material flows from the nozzle during intervals when a flow axis of the nozzle is directed at the selected interconnect pad and does not flow from the nozzle during intervals when the flow axis is directed at an unselected interconnect pad; and
stacking the plurality of die such that front sides of the die are arranged in a plurality of parallel planes, wherein at least some of the interconnect pads are aligned in respective columns extending transverse to the parallel planes,
wherein in the stacked die assembly, at least one nonselected interconnect pad in a column is available for electrical interconnection and the selected interconnect pads in the same column are electrically insulated.
2. The method of claim 1 wherein the selected region of the die includes a selected region of a die sidewall, comprising selectively applying the dielectric material onto the selected region of the die sidewall surface.
3. The method of claim 1 wherein the selected region of the die includes a selected area of the front side of the die, comprising selectively applying the dielectric material onto the selected area of the front side of the die.
4. The method of claim 1 wherein the selected region of the die includes a selected area inboard of an interconnect pad, comprising selectively applying the dielectric material onto the selected area inboard of the interconnect pad.
5. The method of claim 1 wherein the selected region of the die includes a selected area of an interconnect margin of the die, comprising selectively applying the dielectric material onto the selected area of the interconnect margin.
6. The method of claim 1 wherein the selected region of the die includes a selected area adjacent an interconnect edge of the die, comprising selectively applying the dielectric material onto the selected area adjacent the interconnect edge.
7. The method of claim 1 wherein the selected region of the die includes a selected area between interconnect pads in a row of pads on the die, comprising selectively applying the dielectric material onto the selected area between interconnect pads.
8. The method of claim 1, further comprising forming a conformal electrically conductive trace contacting a nonselected interconnect pad and passing over an insulating region resulting from selectively applying the dielectric material over the selected region.
9. The method of claim 8 wherein forming the electrically conductive trace comprises depositing an electrically conductive material in flowable form and subsequently curing the material to form the trace.
10. The method of claim 8 wherein the dielectric material is characterized by having a surface at least partly nonwettable by the electrically conductive material.
11. The method of claim 8, further comprising treating the deposited dielectric material so that a surface thereof is at least partly nonwettable by the electrically conductive material.
12. The method of claim 1 wherein applying the dielectric material includes directing an aerosolized electrically insulative material onto the selected region.
13. The method of claim 1 wherein applying the dielectric material includes directing a curable electrically insulative material onto the selected region, further comprising curing the material.
14. A method for forming a stacked die assembly, comprising providing semiconductor die having electrical interconnect pads arranged in an interconnect margin adjacent an interconnect die edge;
stacking a plurality of said die such that front sides of the die are arranged in parallel planes, and such that the pads in successive die in the stack are arranged in a plurality of columns each extending transverse to the parallel planes;
selectively applying electrical insulation over selected pads at which electrical connection is not desired by selectively depositing at least one of a spot or a line of dielectric material via a nozzle onto the selected region of the die, the selectively depositing leaving nonselected pads exposed and free from depositing of the dielectric material thereon, such that the nonselected interconnect pads are available for electrical interconnection without requiring the deposited dielectric material to be removed from the nonselected interconnect pads, the nozzle being controlled so that the dielectric material flows from the nozzle during intervals when a flow axis of the nozzle is directed at the selected interconnect pad and does not flow from the nozzle during intervals when the flow axis is directed at an unselected interconnect pad; and
forming electrically conductive traces over the columns, wherein at least one trace electrically interconnects the nonselected interconnect pads in a column of the plurality of columns.
15. The method of claim 14, wherein the plurality of said die are in an offset configuration in which successive die in the stack are offset at the interconnect die edge.
16. The method of claim 1, wherein the stacking is performed prior to the electrically insulating the die.
17. The method of claim 14, wherein forming the electrically conductive traces comprises depositing an electrically conductive material in flowable form and subsequently curing the material to form the trace.
18. The method of claim 14, wherein the selectively depositing the dielectric material comprises directing an aerosolized electrically insulative material onto the selected region.
19. The method of claim 14, wherein the selectively depositing the dielectric material includes directing a curable electrically insulative material onto the selected region, and then curing the material.
20. The method of claim 14, wherein the selected region of the die includes a selected region of a die sidewall, and the selectively depositing the dielectric material deposits the dielectric material onto the selected region of the die sidewall.
The present application claims the benefit of the filing date of U.S. Provisional Application No. 61/255,429, filed Oct. 27, 2009 and is a continuation of U.S. patent application Ser. No. 12/913,529, filed Oct. 27, 2010, the disclosures of which are hereby incorporated herein by reference.
A typical semiconductor die has a front (“active”) side, in which the integrated circuitry is formed, a back side, and sidewalls. The sidewalls meet the front side at front edges and the back side at back edges. Semiconductor die typically are provided with interconnect pads (die pads) located at the front side for electrical interconnection of the circuitry on the die with other circuitry in the device in which the die is deployed. Some die as provided have die pads on the front side along one or more of the die margins, and these may be referred to as peripheral pad die. Other die as provided have die pads arranged in one or two rows at the front side near the center of the die, and these may be referred to as central pad die. The die may be “rerouted” to provide a suitable arrangement of interconnect pads at or near one or more of the margins of the die. A die margin along which interconnect pads are arranged may be referred to as an “interconnect margin”, the adjacent front die edge may be referred to as an “interconnect edge”, and a die sidewall adjacent an interconnect die edge may be referred to as an “interconnect sidewall”.
Die pads in processed semiconductor wafers as provided, or in singulated die, may not be arranged along one die edge, or along two adjacent die edges. The pads may be arranged in one or two rows near a centerline of the die, for example; or, if arranged along die edges, they may be arranged along two opposite die edges or along all four die edges, for example. Or, whatever the arrangement of pads on the wafer or on the die as provided, they may not be arranged in a suitable manner for a given end use; they may be located in an unsuitable sequence, or at an unsuitable pitch, for example). In such instances, the wafer or die as provided may if desired be further processed to reroute the original pads to new pad positions along one die edge or along two die edges, prior to mounting the die in stacks for interconnection according to the invention.
The invention features methods employing additive processes for electrically insulating selected surface regions on a stack of die, and methods for electrically interconnecting die in a stack of die, including additive processes for electrically insulating selected surface regions of the die. Regions that are not electrically insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.
In a subtractive process for electrically insulating a die or a stack of die, as outlined below, the front side (at least) of the die is covered by an electrically insulative coating, and interconnect pads on the die are made available for electrical connection by selectively removing the electrically insulative coating over the pads. When the interconnect material is deposited over the die in the stack, the material contacts only the exposed pads, and no electrical contact is made with pads (or with other die surfaces overlain by the interconnect material) that remain covered by the electrically insulative coating.
An additive process for electrically insulating selected surface regions of a die or a stack of die may provide significant advantages by way of simplifying processing and reducing materials costs and capital outlay. For instance, in a subtractive process, the insulative material is typically applied over a wide area; in an additive process, the insulative material can be applied only over areas where electrical insulation is specifically desired, and the additive process can require use of significantly less of the insulative material. Also, for instance, in a subtractive process, additional process steps are required to selectively remove the insulative material where required; in an additive process, the selective deposition of application of insulative material requires no removal step, and the deposition or application may be entirely automated, as appropriate. Also, for instance, the machinery (such as laser apparatus, for ablation of material to be removed, for example) that is required for selective removal of insulative material in a subtractive process may not otherwise be employed on the assembly line; such equipment can require significant capital outlay and may demand additional resources for maintenance. Also, for instance, the use of various techniques for selective removal of insulative material must be carefully tuned and monitored according both to the particular material being removed and to the various underlying materials, so that the removal process does not result in damage to any of the various underlying structures.
In one general aspect the invention features a method for electrically insulating a selected interconnect die pad by applying a dielectric material onto the interconnect pad surface.
In another general aspect the invention features a method for electrically insulating at least a selected region of an interconnect die sidewall by applying a dielectric material onto the selected region of the die sidewall surface.
In another general aspect the invention features a method for electrically insulating at least a selected region of the front side of a die by applying a dielectric material onto the selected region of the front side of the die.
In some embodiments applying the dielectric material includes directing an aerosolized electrically insulative material onto the region of the die sidewall. The material may be a curable material, and the method further includes curing the material.
In another general aspect the invention features a method for forming a stacked die assembly, by providing semiconductor die having electrical interconnect pads arranged in an interconnect margin adjacent an interconnect die edge; stacking a plurality of said die in an offset configuration in which successive die in the stack are offset at the interconnect die edge and in which pads in successive die in the stack are arranged in columns; electrically insulating selected pads at which electrical connection is not desired; and forming electrically conductive traces over the columns. Exposed pads (not electrically insulated) are contacted by the electrically conductive traces and, where a plurality of pads in a column are exposed, the exposed pads are electrically interconnected by the electrically conductive trace; insulated pads are not available for contact by the electrically conductive traces and, accordingly, insulated pads are not electrically connected to other pads in the column.
In some embodiments the method further includes electrically insulating at least a selected region of an interconnect sidewall of at least one of the die in the stack. In some embodiments the method further includes electrically insulating at least a selected region of the front side of at least one of the die in the stack; in some such embodiments the selected region includes an area of the front side of the die inboard of the die pads, and in some such embodiments the area includes rerouting circuitry; in some such embodiments the selected region includes an area of the front side of the die adjacent an interconnect edge, and may in some such embodiments include an area of the interconnect margin; in some such embodiments the selected region includes an area between die pads, for example adjacent die pads, in a row of die pads on a die.
The selectively applied insulation may be characterized by having a surface that is not “wettable” by the particular interconnect material that is to be applied over it, or that is wettable, if at all, to a limited extent, so that the subsequently applied interconnect material has a reduced tendency to “run out” or to “bleed” over the surface. Selection of materials having these properties can aid in formation of narrower interconnects, and of interconnects having narrower pitch, without risk of electrical short between adjacent interconnects or between an interconnect and a surface to which electrical connection is not desired.
In various embodiments, electrical insulation is provided according to the invention over areas where insulation is required (or is desirable), without a need to remove insulation from any areas where insulation is not required (and is not desirable).
The assemblies according to the invention can be used in computers, telecommunications equipment, and consumer and industrial electronics devices.
FIG. 1A is a diagrammatic sketch in a plan view showing interconnection of pads in a stack of die in an offset configuration.
FIG. 1B is a diagrammatic sketch showing interconnected stacked die in a sectional view as indicated at B-B in FIG. 1A.
FIG. 2A is a diagrammatic sketch in a plan view showing interconnection of pads in a stack of die in another offset configuration.
FIG. 2B is a diagrammatic sketch showing interconnected stacked die in a sectional view as indicated at B-B in FIG. 2A.
FIG. 3A is a diagrammatic sketch in a partial plan view showing the offset edges of an example of an 8-die offset stack.
FIG. 3B is a diagrammatic sketch in a partial sectional view of an 8-die offset stack, as indicated at B-B in FIG. 3A.
FIG. 5A is a diagrammatic sketch in a partial plan view showing the offset edges of an 8-die offset stack in an embodiment of the invention.
FIG. 5B is a diagrammatic sketch in a partial sectional view of an 8-die offset stack in an embodiment of the invention, as indicated at B-B in FIG. 5A.
FIG. 6A is a diagrammatic sketch in a partial plan view showing the offset edges of an 8-die offset stack, having selected die pads insulated according to an embodiment of the invention.
FIG. 6B is a diagrammatic sketch in a partial sectional view of an 8-die offset stack, as indicated at B-B in FIG. 6A, having selected die pads insulated according to an embodiment of the invention.
FIG. 7A is a diagrammatic sketch in a partial plan view showing the offset edges of an 8-die offset stack, interconnected according to an embodiment of the invention.
FIG. 7B is a diagrammatic sketch in a partial sectional view of an 8-die offset stack, as indicated at B-B in FIG. 7A, interconnected according to an embodiment of the invention.
FIG. 8A is a diagrammatic sketch in a partial plan view showing the offset edges of an 8-die offset stack in another embodiment of the invention.
FIG. 8B is a diagrammatic sketch in a partial sectional view of an 8-die offset stack in an embodiment of the invention, as indicated at B-B in FIG. 8A.
FIG. 9A is a diagrammatic sketch in a partial plan view showing the offset edges of an 8-die offset stack, having selected die pads insulated according to an embodiment of the invention.
FIG. 9B is a diagrammatic sketch in a partial sectional view of an 8-die offset stack, as indicated at B-B in FIG. 9A, having selected die pads insulated according to an embodiment of the invention.
FIG. 10A is a diagrammatic sketch in a partial plan view showing the offset edges of an 8-die offset stack, interconnected according to an embodiment of the invention.
FIG. 10B is a diagrammatic sketch in a partial sectional view of an 8-die offset stack, as indicated at B-B in FIG. 10A, interconnected according to an embodiment of the invention.
FIG. 11 is a diagrammatic sketch in a sectional view showing a portion of an aerosol application tool suitable for use in selectively applying an electrical insulation material according to an embodiment of the invention.
FIGS. 12A and 12B are diagrammatic sketches in plan view showing stages in deposition of an electrical insulation material according to an embodiment of the invention.
FIGS. 12D and 12E are diagrammatic sketches in plan view showing stages in deposition of an electrical insulation material according to another embodiment of the invention.
FIG. 12C is a diagrammatic sketch in a transverse sectional view of a deposited electrical insulation, taken at C-C′ in FIG. 12B.
FIGS. 13A-13C are diagrammatic sketches showing a stage in depositing electrical insulation material onto selected pads on a stack of die according to an embodiment of the invention. FIG. 13A is a transverse partial sectional view; FIG. 13B is a partial elevational view; and FIG. 13C is a partial plan view.
FIGS. 14A-14C are diagrammatic sketches showing a stage in depositing electrical insulation material onto interconnect die sidewalls on a stack of die according to an embodiment of the invention. FIG. 14A is a transverse partial sectional view; FIG. 14B is a partial elevational view; and FIG. 14C is a partial plan view.
FIGS. 15A-15C are diagrammatic sketches showing a stage in depositing electrical insulation material onto selected pads on a stack of die according to another embodiment of the invention. FIG. 15A is a transverse partial sectional view; FIG. 15B is a partial elevational view; and FIG. 15C is a partial plan view.
FIGS. 16A-16C are diagrammatic sketches showing a stage in depositing electrical insulation material onto interconnect die sidewalls on a stack of die according to another embodiment of the invention. FIG. 16A is a transverse partial sectional view; FIG. 16B is a partial elevational view; and FIG. 16C is a partial plan view.
FIG. 17A is a diagrammatic sketch in a partial sectional view showing a stage in interconnecting an offset die stack according to an embodiment of the invention, following deposition of electrical insulation material onto interconnect die sidewalls.
FIG. 17B is a diagrammatic sketch in a partial sectional view showing a stage in interconnecting an offset die stack as in FIG. 17A according to an embodiment of the invention, following deposition of electrical insulation material onto selected die pads.
FIG. 17C is a diagrammatic sketch in a partial sectional view showing a stage in interconnecting a selectively insulated offset die stack as in FIG. 17B according to an embodiment of the invention, following deposition of electrically conductive material over a column of die pads.
FIGS. 18A and 18B are diagrammatic sketches showing a stage in depositing electrical insulation material onto selected pads on a stack of die according to another embodiment of the invention. FIG. 18A is a transverse partial sectional view; and FIG. 18B is a partial plan view.
FIGS. 19A and 19B are diagrammatic sketches showing a stage in depositing electrical insulation material onto selected pads on a stack of die according to another embodiment of the invention. FIG. 19A is a transverse partial sectional view; and FIG. 19B is a partial plan view.
FIG. 20 is a diagrammatic sketch in a partial plan view showing a die having elongated pads in a fine pitch, and having rerouting traces exposed at the front side of the die.
FIGS. 21A, 21B 21C and 21D are diagrammatic sketches in partial plan view showing two stacked die, in stages of an electrical insulating process according to an embodiment of the invention.
FIG. 22 is a diagrammatic sketch showing interconnected stacked die in a sectional view.
FIGS. 23A, 23B, 23C are diagrammatic sketches showing stacked die in a sectional view, in stages of an electrical insulating process according to an embodiment of the invention.
Subtractive Electrical Insulation Procedure
S. J. S. McElrea et al. U.S. patent application Ser. No. 12/124,077, filed May 20, 2008, titled “Electrically interconnected stacked die assemblies”, which is incorporated herein by reference, describes among other things stacked die assemblies in which successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. The electrically conductive traces may be formed of a material that is applied in a flowable form and subsequently cured or allowed to cure. Examples of such materials include electrically conductive polymers such as filled polymers, for example filled epoxies or electrically conductive inks. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected. The electrically insulative coating prevents the electrically conductive material from making electrical contact with surfaces at which electrical continuity is not desired. Some examples of such constructs are illustrated in FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B herein.
FIG. 1A shows in a plan view an arrangement of stacked offset die, each die having interconnect terminals arranged in one margin adjacent a front die edge; and FIG. 1B shows the stack in a sectional view as indicated at B-B in FIG. 1A. Referring to the uppermost die 10 in the stack, for example, interconnect die pads (e.g., pads 18) are in this example situated in a row 17 alongside front die edge 16. The die margin in which the row 17 of pads is situated may be referred to as an “interconnect margin”, and the adjacent die edge 16 may be referred to as an “interconnect edge”; and the adjacent die sidewall 13 may be referred to as an “interconnect sidewall”. In this example corresponding interconnect pads on successive die are aligned in columns, as indicated for example at 19 in FIG. 1A; accordingly, the sectional view in FIG. 1B passes through one such column. The offset die stack presents as a stair shape, and by analogy the interconnect margins constitute the stair treads and the interconnect sidewalls constitute the stair risers. Each die in this example (e.g., die 10) is covered on all surfaces (back surface, front surface, sidewalls) by a conformal coating 14, provided with openings exposing interconnect pads 18. Successive coated die in the stack may, as in these examples, rest directly one upon another, such that the coating on the back side of an upper die can contact the coating on the front side of the underlying die. Optionally, or additionally, a die attach film may be laminated onto the back side of one or more of the die.
Interconnect pads on successive die in the stack are electrically interconnected by traces (e.g., trace 12) of an electrically conductive interconnect material. The interconnect material is a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. To form the traces, the stack of die may be supported, for example, at the back side of the lowest of the die in the stack, and the interconnect material may be applied along a trajectory over the pads to be connected and the die surfaces between them. The interconnect material may be applied using an application tool such as, for example, a syringe or a nozzle. The material exits the tool in a deposition direction generally toward the interconnect terminals, and the tool is moved over the die stack face in a work direction. The material is deposited while the tool is moved. The material may be extruded from the tool in a continuous flow, or, the material may exit the tool dropwise. The material may exit the tool as a jet of droplets, and is deposited as dots which coalesce upon or following contact with a stack face surface. The droplets may be very small, and may exit the tool as an aerosol spray.
As FIGS. 1A and 1B show, the die stack has a greater footprint than a single die, as a result of the horizontal displacement of the die. It may be preferable to minimize the footprint of the stack, and this may be accomplished by reducing the extent of horizontal displacement of the die, as illustrated for example in FIGS. 2A, 2B. Each die need be displaced only to an extent at least sufficient to expose enough of the area of the pads in the underlying die to permit the interconnect material to make good electrical contact with the pads and, accordingly, the extent of displacement, indicated for example at d in FIG. 2A, is shown greater than may be necessary. In principle, the displacement may be sufficient if at least a fraction of the area of the pads is left uncovered by the overlying die. In practice, if the uncovered area of a pad is too small, the interconnect material as deposited may not contact the pad over an area great enough to establish a good electrical connection when the material is cured. It may be preferred to minimize the extent of displacement, so as to minimize the footprint of the stack.
FIGS. 1A, 1B, 2A, 2B show the die stack following deposition of interconnect material for a single trace. The procedure is repeated to deposit traces connecting all the pads for which electrical interconnection is desired, and following deposition the material is cured. Optionally, a cure or partial cure of the interconnect material may be carried out prior to completion of a trace, or prior to completion of all the traces.
As noted above, where the front side of the die is covered by an electrically insulative coating, pads on the die are made available for electrical connection by selectively removing the electrically insulative coating over the pads. When the interconnect material is deposited over the die in the stack, the material contacts only the exposed pads, and no electrical contact is made with pads (or with other die surfaces overlain by the interconnect material) that remain covered by the electrically insulative coating. In FIGS. 1A, 2A all the pads on all the die are shown as being exposed for electrical connection by the conductive traces and, accordingly, each of the pads in each die is in these examples electrically connected to pads on the other die in the stack. Depending upon the pad layout design on the die, it may not be desired to make electrical connection of all the pads on a given die with pads on other die or with circuitry in an underlying support. In such circumstances, the electrically insulative coating over selected ones of the pads on each die may be removed to expose the selected pads, and the coating may be left in place on pads to which electrical connection is not desired.
This is illustrated with reference to FIGS. 3A, 3B, 4A, 4B. FIG. 3A shows by way of example a portion near the interconnect edge of an 8-die offset stack. Each die has a row 39 of pads (e.g., pads 38; 32 pads in this example). The pads may be referenced by numbers 1 through n (1-32 in this example) according to the pad locations, as suggested by the numerals in parentheses (1), (2), (3) . . . (31), (32) aligned with the pad positions on die 30 in FIG. 3A. The die are stacked one over another and offset so that the interconnect edge of each die (except the lowermost die) is set back with respect to the interconnect edge of the die underlying it. The die are arranged in the stack so that corresponding pad locations are aligned in columns. The stack is mounted on a support (here a substrate) 300 having interconnect sites (leads) 308. The lowermost die in the stack is oriented with the substrate so that the stack edge (lower die interconnect edge 36) overlaps the leads on the substrate, and so that the pad columns are aligned with the leads, so there is no interconnect span dimension next to the stack. The die in this example are each covered on all sides with a conformal insulative coating (of a material such as for example a parylene). Openings through the conformal coating were made in each die to expose selected interconnect die pads (pads 38, for example), while leaving selected other interconnect die pads protected (insulated), as at 34, for example. FIG. 3B is a sectional view thru the construct of FIG. 3A at the pad location (2) column, as indicated at B-B in FIG. 3A. In this column, the pads in the upper four die (e.g., pad 38 in the fourth die) are exposed by openings in the conformal insulative coating, and the pads in the lower four die (e.g., as indicated at 34 in the fifth die) are left covered.
FIGS. 4A, 4B show the interconnect portion of an 8-die offset stack, as in FIGS. 3A, 3B, electrically interconnected with interconnect traces formed over the pad columns (e.g., traces 42 over columns (1), (2), (3)). FIG. 4B is a sectional view thru the construct of FIG. 4A at the pad location (2) column, as indicated at B-B in FIG. 4A. The traces electrically connect exposed die pads in the column (e.g., pad 38) to other exposed die pads in the column and to a corresponding interconnect site 302 on the substrate 300. Pads that remain covered by the insulative coating (e.g., as indicated at 34), and other die surfaces overlain by the interconnect material are not electrically connected.
The procedure outlined above for die insulation and selection of pads to be electrically connected may be referred to a “subtractive process”, inasmuch as a dielectric coating is formed over all the pads, and pads to be electrically connected are exposed by selective removal of the coating over those pads.
Additive Insulation Procedure
Die insulation according to various embodiments described in this application may be referred to as an “additive process”. Here, a dielectric material is applied to areas of the die surface where electrical contact with the conductive interconnect traces is not desired, such as die pads that are not to be electrically connected, leaving uncovered the die pads that are to be electrically connected. The dielectric material prevents the subsequently applied electrically conductive material from making electrical contact with surfaces at which electrical continuity is not desired. No step of selectively removing dielectric coating is required.
FIG. 5A shows in plan view a portion near the interconnect edge of an 8-die offset stack. Each die has a row 59 of pads (e.g., pads 58; 32 pads in this example). The pads may be referenced by numbers 1 through n (1-32 in this example) according to the pad locations, as suggested by the numerals in parentheses (1), (2), (3) . . . (31), (32) aligned with the pad positions on die 50 in FIG. 5A. The die are stacked one over another and offset so that the interconnect edge of each die above the lowermost die is set back with respect to the interconnect edge of the die underlying it. The die are arranged in the stack so that corresponding pad locations are aligned in columns. The stack is mounted on a support (here a substrate) 500 having interconnect sites (leads) 508. The lowermost die in the stack is oriented with the substrate so that the stack edge (lower die interconnect edge 56) overlaps the leads on the substrate, and so that the pad columns are aligned with the leads, so there is no interconnect span dimension next to the stack. FIG. 5B shows the structure of FIG. 5A in a sectional view thru a column (the pad location (2) column in this example).
FIGS. 6A, 6B show a portion near the interconnect edge of an 8-die offset stack configured as in FIGS. 5A, 5B, in which selected die pads have been insulated according to an aspect of the invention. FIG. 6A is a plan view, and FIG. 6B is a sectional view thru the pad location (2) column. Particularly, with reference to the pad location (2) column in this example, a dielectric material has been selectively deposited (e.g., 54) on the location (2) pads on the lower four die in the stack, while the location (2) pads (e.g., pads 58) on the upper four die in the stack are left uncovered. And with reference to the pad location (3) column in this example, a dielectric material has been selectively deposited on the location (3) pads on the upper four die in the stack, while the location (3) pads on the lower four die in the stack are left uncovered. And with reference to the pad location (1) column in this example, no dielectric material has been selectively deposited on the location (1) pads, so that the location (1) pads on all eight die in the stack are left uncovered.
FIGS. 7A, 7B show a portion near the interconnect edge of an 8-die offset stack configured as in FIGS. 5A, 5B, and insulated according to an aspect of the invention as in FIGS. 6A, 6B, and electrically interconnected by conductive traces over the pad columns (e.g., conductive traces 72 over pad location columns (1), (2), (3)). FIG. 7A is a plan view, and FIG. 7B is a sectional view thru the pad location (2) column. Particularly, with reference to the pad location (2) column in this example, the electrically conductive trace 72 is formed over the various surfaces at the pad location column, and contacts the lead 508 at the substrate. The trace makes electrical contact with the position (2) pads on the upper four die, which were left uncovered; the trace makes no connection with the position (2) pads on the lower four die, which are covered by the dielectric material. Consequently, the position (2) pads (e.g., pads 58) on the upper four die in the stack are electrically interconnected to one another, and they are electrically connected to the corresponding lead 508 on the substrate, and the position (2) pads on the lower four die are not electrically connected to one another or to the substrate. With reference to the pad location (3) column in this example, the position (3) pads on the lower four die in the stack are electrically interconnected to one another and to the corresponding lead on the substrate, and the position (3) pads on the upper four die are not electrically connected to one another or to the substrate. And with reference to the pad location (1) column in this example, all the location (1) pads on all eight die in the stack are electrically connected to one another and to the corresponding lead on the substrate.
FIGS. 8A-8B, 9A-9B, 10A-10B show stages in the construction of an electrically interconnected die assembly according to another embodiment of the invention. These FIGs. show a portion near the interconnect edge of an 8-die offset stack, generally as in FIGS. 5A-5B, 6A-6B, 7A-7B, and the structure is similar, except that the die offset is greater in these FIGs., so that the die pads on underlying die are fully revealed by the offset. Particularly, FIGS. 9A, 9B illustrate a stage following insulation of selected pads.
FIG. 8A shows in plan view a portion near the interconnect edge of an 8-die offset stack. Each die has a row 89 of pads (e.g., pads 88; 32 pads in this example). The pads may be referenced by numbers 1 through n (1-32 in this example) according to the pad locations, as suggested by the numerals in parentheses (1), (2), (3) . . . (31), (32) aligned with the pad positions on die 80 in FIG. 8A. The die are stacked one over another and offset so that the interconnect edge of each die above the lowermost die is set back with respect to the interconnect edge of the die underlying it; in this example the offset is great enough to entirely expose pads on underlying die. The die are arranged in the stack so that corresponding pad locations are aligned in columns. The stack is mounted on a support (here a substrate) 800 having interconnect sites (leads) 808. The lowermost die in the stack is oriented with the substrate so that the pad columns are aligned with the leads. In this example, the stack edge (lower die interconnect edge 86) overlaps the leads on the substrate, so that so there is no interconnect span dimension next to the stack. FIG. 8B shows the structure of FIG. 8A in a sectional view thru a column (the pad location (2) column in this example). In other embodiments (not shown) the lowermost die in the stack may be aligned so that the stack edge (lower die interconnect edge) does not overlap the leads on the substrate; in particular, the lower die interconnect edge may be situated at an inboard edge of the leads (refer for example to FIGS. 19A, 19B), or the lower die interconnect edge may be set back (in an inboard direction) from the leads (refer for example to FIGS. 18A, 18B).
FIGS. 9A, 9B show a portion near the interconnect edge of an 8-die offset stack configured as in FIGS. 8A, 8B, in which selected die pads have been insulated according to an aspect of the invention. FIG. 9A is a plan view, and FIG. 9B is a sectional view thru the pad location (2) column. Particularly, with reference to the pad location (2) column in this example, a dielectric material has been selectively deposited (e.g., 94) on the location (2) pads on the lower four die in the stack, while the location (2) pads (e.g., pads 88) on the upper four die in the stack are left uncovered. And with reference to the pad location (3) column in this example, a dielectric material has been selectively deposited on the location (3) pads on the upper four die in the stack, while the location (3) pads on the lower four die in the stack are left uncovered. And with reference to the pad location (1) column in this example, no dielectric material has been selectively deposited on the location (1) pads, so that the location (1) pads on all eight die in the stack are left uncovered.
FIGS. 10A, 10B show a portion near the interconnect edge of an 8-die offset stack configured as in FIGS. 8A, 8B, and insulated according to an aspect of the invention as in FIGS. 9A, 9B, and electrically interconnected by conductive traces over the pad columns (e.g., conductive traces 102 over pad location columns (1), (2), (3)). FIG. 10A is a plan view, and FIG. 10B is a sectional view thru the pad location (2) column. Particularly, with reference to the pad location (2) column in this example, the electrically conductive trace 102 is formed over the various surfaces at the pad location column, and contacts the lead 808 at the substrate. The trace makes electrical contact with the position (2) pads on the upper four die, which were left uncovered; the trace makes no connection with the position (2) pads on the lower four die, which are covered by the dielectric material. Consequently, the position (2) pads (e.g., pads 88) on the upper four die in the stack are electrically interconnected to one another, and they are electrically connected to the corresponding lead 808 on the substrate, and the position (2) pads on the lower four die are not electrically connected to one another or to the substrate. With reference to the pad location (3) column in this example, the position (3) pads on the lower four die in the stack are electrically interconnected to one another and to the corresponding lead on the substrate, and the position (3) pads on the upper four die are not electrically connected to one another or to the substrate. And with reference to the pad location (1) column in this example, all the location (1) pads on all eight die in the stack are electrically connected to one another and to the corresponding lead on the substrate.
The dielectric material may be applied using any of a variety of techniques. In some embodiments the dielectric material is applied in an aerosol. Usually, the dielectric material is applied by aerosol jet printing. In aerosol jet printing the material is aerosolized and then entrained in a carrier as an aerodynamically focused droplet stream that can be directed through a nozzle onto a target surface. Suitable aerosol jet apparatus may include, for example, the M3D system, available from Optomec, Inc., Albuquerque, N.M. FIG. 11 shows a nozzle of an example of suitable aerosol jet apparatus, in a diagrammatic sectional view thru the nozzle axis. The nozzle 118 has a lumen 124 defined by an inner surface 112 of a generally tubular wall 110. An aerosol jet head (not shown in the FIG.) forms a flow of a sheath gas 115 surrounding a flow of aerosolized material 113. The flow of sheath gas and the entrained aerosolized material emerge from the tip 116 of the nozzle along a flow axis 117. The profile (that is, the shape in transverse section) and dimensions of the jet of aerosolized material can be controlled by selecting the dimensions of the nozzle lumen and by controlling the flow at various points around the flow axis. The jet profile may be generally round, for example circular or roughly circular. The apparatus may be manipulated to direct the jet toward a target surface, and the target and the nozzle may be moved in relation to one another as indicated by the arrow 119 to form a line of material on the target surface.
FIGS. 12A-12C show a resulting line of material. In the example shown here, the profile of the jet has an elongated round shape, so that at any instant it would be expected to deposit the material in a corresponding shape as illustrated 122 in FIG. 12A. Movement of the nozzle tip over the target surface in a direction as illustrated by the arrow 129 in FIG. 12A forms a line 124, as shown in FIG. 12B, having a width w generally corresponding to the width of the jet profile. FIG. 12C shows a transverse sectional view of a deposited line of material 124 on a target surface 125, having a width w and a thickness t.
The profile of the jet may have a shape other than an elongated round shape. FIGS. 12D and 12E show a resulting line of material in an embodiment in which the jet has a generally circular shape, so that at any instant it would be expected to deposit the material in a corresponding shape as illustrated 126 in FIG. 12D. Movement of the nozzle tip over the target surface in a direction as illustrated by the arrow 129 in FIG. 12D forms a line 128, as shown in FIG. 12E, having a width w generally corresponding to the width (diameter) of the jet profile.
The dielectric material may be applied by any of a variety of techniques. The dielectric material may be applied by a jetting technique, employing for example piezoelectric jetting apparatus to deposit the material by droplets. Suitable piezoelectric “inkjet” apparatus is available from, for example, FUJIFILM Dimatix, Inc., Santa Clara, Calif.; other suitable piezoelectric jetting apparatus is available from, for example, Nordson Asymtek, Carlsbad, Calif. Or, the dielectric material may be applied by a streaming technique, employing pump-driven apparatus to deposit the material in a column. Suitable streaming apparatus is available from, for example, Speedline Technologies, under the trade name SmartStream®.
The width of the deposited line of material can be set, within limits of the particular equipment, with some precision. The width of the deposited line of material may in some embodiments range from about 10 um or less to about 100 um or greater; in some embodiments the width of the deposited line of material is within a range about 10 um to about 100 um, such as, in a particular example, about 50 um. As will be appreciated, a specified width of deposited material will be determined according to the dimensions of the surface (such as, for example, the width and length of the die pad, or the width of the interconnect trace to be formed subsequently, or the width of the interconnect margin, or the die stack setback, or the height of the die sidewall) to be insulated. As described in more detail below, where a width (for example) of a surface to be covered exceeds a practical limit for the width of a deposited line of material, the material may be deposited by two or more adjacent (or overlapping) lines.
The thickness of the deposited line of material can be established by setting the rate of movement of the nozzle tip over the target surface; a thicker line results from a slower movement. The line should be thick enough to sufficiently electrically insulate the surface, and this depends among other things upon the dielectric properties of the material itself, and upon the electrical parameters in operation of the die assembly. The thickness of the deposited line may in some embodiments range from as thin as about 1 nm or less to about 20 um or greater. In some embodiments the thickness is in a range about 7 um to about 13 um, such as about 10 um. It may be desirable not to form the lines with a thickness excessively grater than required, so that the general planarity of the surfaces is not overly disrupted.
The electrically insulative material is capable of being atomized, and typical such materials are applied onto the target surface in an aerosol and then cured to form an electrically insulative covering. Suitable electrically insulative materials include, for example, low viscosity dielectric materials, sometimes referred to as “dielectric inks”. Examples include any of various inorganic dielectric materials, mixed in any of various curable organic carriers. Examples of suitable materials include titanate compounds (for example, barium titanate) as the inorganic dielectric material; and a curable organic polymer (such as a phenol resin, or an epoxy/melamine resin) as the organic carrier. Such materials may be obtained from, for example, NOF Corporation; or materials marketed under the name Loctite.
FIGS. 13A, 13B, 13C illustrate a stage in insulation of selected die pads by aerosol spray according to an embodiment of the invention. FIG. 13C is a partial plan view showing two pad columns in a stack of four die in an offset configuration; FIG. 13B is a partial elevational view taken toward the die sidewalls; and FIG. 13A is a partial sectional view at A-A′ thru the die stack at a pad column. Each of die 13, 13′, 13″, 13′″ in the stack has pads 138, 138′, 138″, 138′″ arranged in an interconnect margin of the die. The nozzle 130 in this illustration is oriented so that the flow axis 117 of the dielectric material is generally perpendicular to the plane of the front side of the die and, in this illustration the nozzle is moved in a work direction 139 generally parallel to the plane of the front side of the die, and generally aligned with an underlying pad column. In this example the jet apparatus is controlled so that the material flows discontinuously; that is, the material flows during intervals when the flow axis is directed at a selected target region (in this example, selected die pads). As a result the regions of the surface at the respective pads are covered with discrete patches of dielectric material. At the stage illustrated, patch 134 has been completed, fully covering pad 138 on die 13; deposition of patch 134′ is not yet complete, and a portion of pad 138′ has not yet been fully covered.
As may be appreciated, the nozzle need not be oriented so that the flow axis is generally perpendicular to the plane of the front side of the die; and the work direction need not be generally parallel to the plane of the front side of the die. An example of an alternative flow axis orientation is suggested by arrow 117′, and an example of an alternative work direction is suggested by arrow 139′; other arrangements are contemplated.
In a subsequent procedure, electrically conductive material will be applied in a flowable form and subsequently cured or allowed to cure to form the interconnect traces, as shown for example in FIGS. 10A, 10B. The electrically conductive material generally conforms to and contacts the surface onto which it is applied; the surface may include conductive features (such as die pads, for example) and semiconducting areas (such as a bare die surface, for example). Electric contact may or may not be made between the conductive trace and a conductive feature or semiconducting area over which the trace is formed, depending upon whether the feature or area has been insulated. As shown in FIGS. 9A, 9B, and 13A, 13B, 13C, die pads are selectively insulated according to embodiments of the invention by selectively applying a dielectric material onto certain of the pads where electrical connection is not desired, effectively preventing the interconnect material from contacting these selected pads.
Referring again to FIGS. 13A, 13B for illustration, the electrically conductive material additionally contacts areas of the die surface at the interconnect sidewalls 136, 136′, 136″, 136′″, and of the portions of the interconnect margin adjacent the die pads at the interconnect die edge and inboard from the pads (e.g., the portions 135, 137 of the interconnect margin adjacent pad 138. Where these areas of the die as provided (that is, before they are stacked) have been insulated, no further insulation treatment may be required. For example, as noted above, the die as provided may have a dielectric layer formed over the integrated circuitry except over the original die pads; and, where the die is rerouted, a dielectric layer may additionally be formed over the rerouting circuitry except over the new (rerouted) interconnect pads. In such instances no additional electrical insulation may be required in the interconnect margin adjacent the pads, or between the front side of a die and the back side of a die stacked over it. And, for example, the interconnect sidewalls of the die as provided may be insulated by a conformal dielectric coating; and in such instances no additional electrical insulation may be required at the die sidewalls.
Where the interconnect sidewalls of the die as provided have not been insulated, a dielectric material may be selectively applied to the interconnect sidewalls (or at least to areas of the interconnect sidewalls that will be contacted with the electrically conductive material for the conductive traces, particularly areas that are within the trajectory defined by the respective pad position columns). In one approach, FIGS. 14A, 14B, 14C illustrate a stage in insulation of selected areas of the interconnect sidewalls by aerosol spray according to an embodiment of the invention. FIG. 14C is a partial plan view showing two pad columns in a stack of four die in an offset configuration; FIG. 14B is a partial elevational view taken toward the die sidewalls; and FIG. 14A is a partial sectional view at A-A′ thru the die stack at a pad column. Each of die 13, 13′, 13″, 13′″ in the stack has interconnect die sidewalls 136, 136′, 136″, 136′″. The nozzle 138 in this illustration is oriented so that the flow axis 117 of the dielectric material is directed toward the die sidewalls and, in this illustration the nozzle is moved in a work direction 149 generally parallel to the plane of the front side of the die, and generally aligned with an underlying pad column. In this example the jet apparatus is controlled so that the material flows discontinuously; that is, the material flows during intervals when the flow axis is directed at a selected target region (in this example, selected areas of the die sidewalls). As a result the regions of the surface at the respective pads are covered with discrete patches of dielectric material. At the stage illustrated, patches 142′″, 142″, have been completed, on targeted areas of die sidewalls 136′″, 136″ on die 13′″, 13″; deposition of patch 142′ is not yet complete, and a portion of the targeted area of die sidewall 136′ has not yet been fully covered.
As may be appreciated, the nozzle may be oriented so that the flow axis is at any direction or angle within a range of directions toward the sidewalls; and the work direction need not be generally parallel to the plane of the front side of the die; and orientations and arrangements other than those shown in the illustration are contemplated.
Alternatively, the nozzle may be moved in a work direction generally over a pad column, and the flow of dielectric material may be interrupted only over pads where electrical connection is desired. Such an arrangement is shown by way of example in FIGS. 15A, 15B, 15C, illustrating a stage in insulation of selected areas of the interconnect sidewalls and of selected die pads by aerosol spray according to another embodiment of the invention. FIG. 15C is a partial plan view showing two pad columns in a stack of four die in an offset configuration; FIG. 15B is a partial elevational view taken toward the die sidewalls; and FIG. 15A is a partial sectional view at A-A′ thru the die stack at a pad column. Each of die 13, 13′, 13″, 13′″ in the stack has interconnect pads 138, 138′, 138″, 138′″, and interconnect die sidewalls 136, 136′, 136″, 136′″. The nozzle 130 in this illustration is oriented so that the flow axis 117 of the dielectric material is directed toward the die sidewalls and toward the die pads and, in this illustration the nozzle is moved in a work direction 159 generally parallel to the plane of the front side of the die, and generally aligned with an underlying pad column. In this example the jet apparatus is controlled so that the material flows continuously except during intervals when the flow axis is directed at a selected target region (in this example, selected die pads). As a result the regions of the surface defined by the pad columns are covered with lines of dielectric material, interrupted at die pads to be left uncovered. In the stage shown in the FIGs., the line 152 has been completed over areas of the sidewalls 136′″, 136″, and over the pads 138′″, 138″; and a portion of the targeted area of die sidewall 136′ has been partially covered. Die sidewall 136 has not yet been covered, and die pads 138′ and 138 have not been covered. If, for example, die pads 138′ and 138 are to be electrically connected, then as the nozzle progresses in the work direction 159 the flow of dielectric material will be interrupted so that the respective pad or pads are left substantially uncovered by dielectric material, while the remainder of the area of the sidewall 136′, and the area of the sidewall 136 are covered.
FIGS. 16A, 16B, 16C illustrate an approach to insulating the interconnect die sidewalls by aerosol spray according to another embodiment of the invention. FIG. 16C is a partial plan view showing two pad columns in a stack of four die in an offset configuration; FIG. 16B is a partial elevational view taken toward the die sidewalls; and FIG. 16A is a partial sectional view at A-A′ thru the die stack at a pad column. Each of die 13, 13′, 13″, 13′″ in the stack has interconnect die sidewalls 136, 136′, 136″, 136′″. The nozzle 138 in this illustration is oriented so that the flow axis 117 of the dielectric material is directed toward the die sidewalls and, in this illustration the nozzle 130 is moved in a work direction generally perpendicular to the plane of FIG. 16A, that is, in a direction generally parallel to an interconnect die edge. Accordingly, a line of dielectric material is deposited in a sweep along the die sidewall. As shown in the FIGs, the material flows continuously; alternatively the jet apparatus may be controlled to interrupt the flow of material so that it is deposited in patches onto selected areas of the die sidewalls located at the pad columns. In the stage shown in the FIGs., lines 162′″, 162″ have been completed on the die sidewall sidewalls 136′″, 136″; and the die sidewall 136′ has been partially covered by line 162′. Die sidewall 136 has not yet been covered. In the example shown the width of the material flow is insufficient to cover the die sidewall in a single pass in the work direction and, accordingly, the nozzle may be advanced in a direction such as is shown at 160 orthogonal to the work direction, so that successive passes of the nozzle progressively cover the surface.
In addition to insulation of interconnect sidewalls as shown for example in FIGS. 16A, 16B, 16C, selected areas of the front side of the die (such as, for example, selected die pads) may if necessary be insulated. FIGS. 17A, 17B, 17C show stages in a process in which interconnect sidewalls of an offset stack of die 170 are insulated by formation of lines or patches of dielectric material (FIG. 17A; e.g., material 172) on the die sidewalls generally as described above; and thereafter selected ones of the die pad 178 are insulated by formation of lines or patches of dielectric material (FIG. 17B; e.g., material 174), leaving certain die pads uncovered; and thereafter the uncovered pads are connected to one another and to leads 176 on the substrate by application of an electrically conductive material to form a trace 175.
As noted above with reference to FIGS. 12A-12E, any of various deposition profile shapes may be employed for depositing the insulative material. Coverage of a specified area that is larger than the deposition profile may be accomplished by moving the nozzle in a suitable work direction (as shown for example in FIGS. 13A, 13B) and, where necessary, by making multiple deposition passes (as shown for example in FIGS. 16A, 16B).
Where an area to be covered (such as a pad, for example) is suitably dimensioned and pitched, and where the material deposition profile is suitably dimensioned and shaped, it may be possible to insulate individual such areas (such as pads) by depositing a spot of insulative material without moving the nozzle. For example, the pad shape and dimensions may in some instances be about the same as the deposition profile, and the pad may be insulated by depositing a spot of material from a nozzle directed toward the pad. Where, for example the pads are rectangular as shown for example in FIG. 13C, and if the deposition profile is similarly rectangular (not shown in the FIGs.), patches of material such as the patch indicated at 134 in FIG. 13C may be formed, fully covering the pads, without moving the nozzle.
Similarly, where for example the pads are square (or roughly square rectangular), and if the deposition profile is round (for example circular or roughly circular), patches of material such as the patch indicated at 184 in FIG. 18C may be formed, fully covering the pads, without moving the nozzle.
FIGS. 19A, 19B, 19C, show an embodiment in which the deposition profile is round (for example circular or roughly circular), and has a width greater than the pad width, pads in a column on adjacent die may by covered by directing the nozzle (not shown) so that the deposition angle is normal to the larger die surface, and moving the nozzle in a direction 199 or 199, for example while forming a line 192 of insulative material. The flow of material from the nozzle may in such a scheme be interrupted whenever the flow axis is directed toward a selected die that is not to be insulated.
As noted above with reference for example to FIGS. 8A, 8B, the die stack may be mounted on a support such as a substrate, and may situated on the support in various ways: in some embodiments such that the die interconnect edge of the lowermost die in the stack overlaps the leads on the substrate; or such that the lower die interconnect edge is situated at an inboard edge of the leads; or such that the lower die interconnect edge is set back (in an inboard direction) from the leads.
FIGS. 18A and 18B additionally illustrate an example in which the die stack is positioned on the substrate 1800 such that the interconnect sidewall 136′″ of the lower die 13′″ is set back from the leads 1808 so that the electrical interconnect material (not shown in these FIGs.) spans a strip 1810 of the substrate surface between the die sidewall and the leads.
FIGS. 19A and 19B additionally illustrate an example in which the die stack is positioned on the substrate 1900 such that the interconnect sidewall 136′″ of the lower die 13′″ coincides with the inboard limit of the leads 1908.
The foregoing illustrations show embodiments, for illustrative purposes, in which the die pads are shaped generally as a rectangle, having a length only slightly greater than the width. Other pad shapes are contemplated, and may in some instances be preferred. The pads may have any of a variety of shapes. Particularly, for example where the pads are arranged in a very fine pitch, it may be desirable to have the pads elongated, to ensure a sufficient area for electrical contact with the interconnect material.
FIG. 20 shows a portion of the front side 202 of a die having elongated narrow generally rectangular pads 204 arranged in a row along a interconnect die edge 206. The pad pitch is indicated at Pp, and may in practice be as fine as 60 um or less; the pad length Lp is made sufficiently great so that the contact area of the pad will be sufficient to provide an electrical connection that has a suitably low resistance and is robust. The interconnect traces (not shown in the FIGs.) will be formed lengthwise the pads. The traces may be narrower than the pad width, and may contact the pads over a length somewhat less than the pad length. Pads that are not intended to be electrically connected will be selectively coated with a dielectric material, generally as described above.
As noted above, the die are stacked in an offset configuration, so that the interconnect sidewall (and interconnect edge) of each overlying die in the stack is set back to some extent from the interconnect edge of the die beneath it, exposing for interconnection at least a portion of the die pads on the underlying die. In the embodiments illustrated above, an overlying die may be set back only enough to expose part of the pads beneath; or the overlying die may be set back enough to expose the entire pads but none of the interconnect margin inboard of the pads; or the overlying die may be set back enough to expose an area of the front side of the die inboard of the pads. In this last circumstance, where the front side of the die as provided is insulated, no further insulation of the exposed inboard area of the front side of the die is necessary.
On the other hand, the front side of the die may in some instances not be insulated, or for example the die may have exposed rerouting circuitry inboard of the pads In such circumstances a greater offset would expose an area of the rerouting circuitry inboard of the pads, and this must be insulated to prevent contact with overlying electrical interconnect traces.
The die shown in FIG. 20 is an example of a die having exposed rerouting traces 208 in an area 209 inboard of the pads 204.
FIG. 21A shows two die, configured as in FIG. 20, stacked with a large offset. The interconnect edge 216 of the upper die 212 is set back from the interconnect edge 216′ of the lower die 212′, exposing not only the die pads but part of the rerouting circuitry in an area inboard of the pads on the lower die.
FIG. 21B shows the stacked die of FIG. 21A, following deposition of electrically insulative material in areas 215, 215′ over the exposed rerouting circuitry.
FIG. 21C shows the stack as in FIG. 21B, following deposition of electrically insulative material in areas 217, 217′ over selected pads that are not to be electrically connected, leaving pads to be connected, e.g., pads 214, 214′ exposed for contact with interconnect material (not shown in these FIGs.), to be subsequently deposited generally as described above.
As indicated above, electrically insulative material may additionally be selectively deposited over areas in the interconnect margin of the die; and/or electrically insulative material may additionally be selectively deposited over areas between interconnect pads, particularly adjacent pads in a row of pads, on the die.
These options are illustrated in a composite manner in FIG. 21D. FIG. 21D shows the stack as in FIG. 21B, following deposition of electrically insulative material in areas 219 of the front side of die 212 adjacent an interconnect edge 216, that is, in areas of the interconnect margin 218 of die 212. (In this illustration, deposition of electrically insulative material in areas of the front side of die 212′ adjacent an interconnect edge 216′ has not yet been carried out.) FIG. 21D additionally shows the stack as in FIG. 21B, following deposition of electrically insulative material in areas 213′ of the front side of die 212′ between adjacent pads 214′. (In this illustration, deposition of electrically insulative material between pads 214 on the front side of die 212 has not yet been carried out.)
Also, as indicated above, the selectively applied insulation may optionally be chosen so that it is characterized by having a surface that is not “wettable” by the particular interconnect material that is to be applied over it; or by having a surface that is wettable, if at all, to a limited extent, so that the subsequently applied interconnect material has a reduced tendency to “run out” or to “bleed” over the surface. Given the properties of a particular chosen interconnect material, a material for the selectively applied insulation may be chosen to have the desired “non-wettable” characteristics; or the selectively applied insulation may be treated following deposition to render the surface suitably “non-wettable” to the interconnect material.
Selection of materials having these properties can aid in formation of narrower interconnects, and of interconnects having narrower pitch, without risk of electrical short between adjacent interconnect traces or between an interconnect trace and an exposed surface to which electrical connection with the trace is not desired. Particularly, for example, with reference to FIG. 21D, where the selectively applied insulation in areas 213′ between pads 214′ has (or is treated to have) a “non-wettable” surface, the insulation can provide a barrier between adjacent pads, resisting flow, or “bleed”, or “run-out” of the subsequently applied interconnect material between adjacent interconnect traces.
Various structures other than the selectively deposited electrically insulative material as described herein, may obscure or cover various areas of the surface of the die, or of the stack of die, effectively making it unnecessary to selectively apply electrical insulation, as described herein, over those obscured or covered areas.
Reference is made, for example, to Jeffrey S. Leal et al. U.S. patent application Ser. No. 12/634,598, filed Dec. 9, 2009, titled “Semiconductor die interconnect formed by aerosol application of electrically conductive material”, which is incorporated herein by reference. This application describes among other things electrically interconnected offset die stack assemblies, in which a dielectric material such as an underfill material is deposited at the inside angle formed by a die sidewall and an underlying surface to form a fillet; and an interconnect trace is formed passing over the surface of the fillet. FIG. 22 herein illustrates an example of such a configuration. A die 2251 is mounted on a die attach surface of a substrate 2200; a die 2252 is mounted over the die 2251; and a die 2253 is mounted over the die 2252. In this example each die is affixed to the respective underlying surfaces using an adhesive. The die are in an offset configuration, having a large die sidewall 2116 offset that exposes a large area 2212 of the underlying die inboard of the die pads 2214. Rerouting traces 2213 are situated at the exposed surface 2212, and these must be protected from contact with the die-to-die interconnect traces. In the example shown in FIG. 22, a fillet 2190 is formed at the inside angle formed by the die sidewall 2116 and the surface 2212, and the interconnect trace 2191 is formed over the fillet. In such configurations abrupt corners are avoided in the surface over which the interconnect traces are formed. Particularly, for example, the surface of the fillet (for example, fillet 2190 in FIG. 22) slopes gradually onto the surface of the underlying feature (for example, surface 2212 of underlying die 2252 in FIG. 22). And, in these examples, the fillet meets the interconnect edge at the top of the upper die sidewall (for example, sidewall 2116 of die 2253 in FIG. 22), so that the outside corner over which the interconnect trace passes at the interconnect edge of the upper die is significantly less than a right angle. Interconnect traces formed over such gradually contoured surfaces can be more robust and reliable than traces formed over abruptly angled surfaces, particularly where the traces are very thin.
As FIG. 22 shows, the interconnect trace passes over a narrow area 2117 of the front side of each die adjacent the die edge, and over an area 2115 of the front side of each die inboard of the pads 2214. Where these areas are not protected by an electrical insulation in the die as provided, and where the inboard areas 2115 are not covered by the fillet, insulation may be provided by selective deposition of electrically interconnect material as described herein.
FIGS. 23A, 23B, 23C show stages in an example of a method for providing insulation to a die stack as in FIG. 22. The sectional view of FIG. 22 is taken at A-A′ in FIGS. 23B, 23C.
FIG. 23A shows the die stack prior to deposition of the fillet 2190. FIG. 23B shows, in a partial plan view, the die stack following selective deposition of electrically insulative material on the narrow areas 232 in the interconnect margins adjacent the die edges 2116. FIG. 23C shows, in a partial plan view as in FIG. 23B, the die stack following selective deposition of electrically insulative material on areas 235 inboard from the die pads; and following selective deposition of electrically insulative material over selected die pads (e.g., 2314) that are not to be electrically connected. The further inboard areas 2212, across which the rerouting traces 2213 pass, need not in these configurations be covered by selectively deposited electrical insulation, inasmuch as, in these configurations, these areas will be covered by the fillet material 2190.
As noted above, electrically insulative material may additionally be deposited in narrow areas between adjacent die pads.
As will be appreciated, the dielectric material may be selectively deposited over the various areas in any sequence, and formation of the fillet may be carried out either prior to or following selective deposition of the dielectric material.
US20010042906 1 Jun 2001 22 Nov 2001 Hisao Nakamura Semiconductor device and process for producing the same
US20040014309 17 Jul 2002 22 Ene 2004 Texas Instruments Incorporated Multilayer laser trim interconnect method
US20090146137 * 3 Sep 2008 11 Jun 2009 Young-Min Kim Display substrate and method of manufacturing the same
US20120061846 * 27 May 2010 15 Mar 2012 Hsio Technologies, Llc Compliant printed circuit area array semiconductor device package
TW200538754A Título no disponible
1 Advisory Action for U.S. Appl. No. 12/913,529 dated Oct. 21, 2014.
2 Advisory Action mailed Oct. 10, 2007, U.S. Appl. No. 11/016,558.
3 Advisory Action, mailed Oct. 20, 2008, App. No. 111744,153.
4 Advisory Action, mailed Oct. 20, 2008, U.S. Appl. No. 11/744,153 0.
5 Advisory Action, mailed Oct. 20, 2008, U.S. Appl. No. 11/744,153.
6 Amendment A filed Aug. 7, 2006 in response to Feb. 7, 2006 Office Action, U.S. Appl. No. 11/097,829 D.
7 Amendment a filed Aug. 7, 2006 in response to Feb. 7, 2006 Office Action, U.S. Appl. No. 11/097,829.
8 Amendment a filed Aug. 7, 2006 in response to Feb. 7, 2006 Quayle Action, U.S. Appl. No. 11/090,969.
9 Amendment and RCE filed Feb. 7, 2011 in repsonse to Aug. 5, 2010 Office Action, U.S. Appl. No. 12/143,157 0.
10 Amendment and RCE filed Feb. 7, 2011 in repsonse to Aug. 5, 2010 Office Action, U.S. Appl. No. 12/143,157.
11 Amendment and RCE filed Mar. 16, 2011 in response to Mar. 18, 2010 Office Action, App No. 11/1744,142 D.
12 Amendment and RCE filed Mar. 16, 2011 in response to Mar. 18, 2010 Office Action, U.S. Appl. No. 11/744,142.
13 Amendment and RCE filed Nov. 26, 2008 in response to Oct. 20, 2008 Advisory Action, U.S. Appl. No. 11/744,153 0.
14 Amendment and RCE filed Nov. 26, 2008 in response to Oct. 20, 2008 Advisory Action, U.S. Appl. No. 11/744,153.
15 Amendment filed 4/1108 in response to Dec. 31, 2007 Office Action, U.S. Appl. No. 11/744,153 0.
16 Amendment filed Apr. 1, 2008 in response to Dec. 31, 2007 Office Action , U.S. Appl. No. 11/744,153.
17 Amendment filed Apr. 11, 2008 in response to Dec. 31, 2007 Office Action, U.S. Appl. No. 11/744,153.
18 Amendment filed Apr. 8, 2009 in response to Dec. 15, 2008 Office Action, U.S. Appl. No. 11/016,558.
19 Amendment filed Dec. 3, 2009 in response to 813109 Office Action, U.S. Appl. No. 11/744,142 D.
20 Amendment filed Dec. 3, 2009 in response to Aug. 3, 2009 Office Action, U.S. Appl. No. 11/744,142.
21 Amendment filed Dec. 9, 2010 in response to Jun. 9, 2010 Office Action, U.S. Appl. No. 12/251,624 0.
22 Amendment filed Dec. 9, 2010 in response to Jun. 9, 2010 Office Action, U.S. Appl. No. 12/251,624.
23 Amendment filed Feb. 14, 2011 in response to Oct. 14, 2010 Office Action, U.S. Appl. No. 12/124,097 D.
24 Amendment filed Feb. 14, 2011 in response to Oct. 14, 2010 Office Action, U.S. Appl. No. 12/124,097.
25 Amendment filed Feb. 22, 2010 in response to Feb. 21, 2010 Office Action, U.S. Appl. No. 12/046,651.
26 Amendment filed Jan. 18, 2011 in response to Aug. 18, 2010 Office Action, U.S. Appl. No. 12/046,651.
27 Amendment filed Jan. 21, 2011 in response to Jul. 21, 2010 Office Action, U.S. Appl. No. 11/849,162.
28 Amendment filed Jan. 22, 2007 in response to Jul. 19, 2007 Office Action, U.S. Appl. No. 11/016,558.
29 Amendment filed Jan. 24, 2007 in response to Jan. 8, 2007 Office Action, App. No. 111097,829 D.
30 Amendment filed Jan. 24, 2007 in response to Jan. 8, 2007 Office Action, U.S. Appl. No. 11/097,829.
31 Amendment filed Jan. 29, 2010 in response to Dec. 28, 2010 Office Action, U.S. Appl. No. 12/403,175 0.
32 Amendment filed Jan. 29, 2010 in response to Dec. 28, 2010 Office Action, U.S. Appl. No. 12/403,175.
33 Amendment filed Jul. 26, 2010 in response to May 24, 2010 Office Action, U.S. Appl. No. 12/124,097 D.
34 Amendment filed Jul. 8, 2009 in response to Jun. 24, 2009 Office Action, U.S. Appl. No. 11/849,162.
35 Amendment filed Jun. 21, 2007 in response to Dec. 22, 2006 Office Action, U.S. Appl. No. 11/016,558.
36 Amendment filed Jun. 26, 2010 in response to May 24, 2010 Office Action, U.S. Appl. No. 12/124,097.
37 Amendment filed Jun. 27, 2008 in response to Mar. 27, 2008 Office Action, U.S. Appl. No. 11/016,558.
38 Amendment filed Jun. 30, 2009 in response to Dec. 30, 2009 Office Action, U.S. Appl. No. 12/143,157 0.
39 Amendment filed Jun. 30, 2009 in response to Dec. 30, 2009 Office Action, U.S. Appl. No. 12/143,157.
40 Amendment filed Mar. 1, 2010, U.S. Appl. No. 12/142,589, in response to Office Action mailed Dec. 1, 2009.
41 Amendment filed Mar. 27,2009 in response to Jan. 27, 2009 Office Action, U.S. Appl. No. 11/849,162.
42 Amendment filed Mar. 4, 2010 in response to Feb. 4, 2010 Office Action, U.S. Appl. No. 12/251,624 0.
43 Amendment filed Mar. 4, 2010 in response to Feb. 4, 2010 Office Action, U.S. Appl. No. 12/251,624.
44 Amendment filed May 22, 2009 in response to Apr. 20, 2009 Office Action, U.S. Appl. No. 11/744,142 D.
45 Amendment filed May 22, 2009 in response to Apr. 20, 2009 Office Action, U.S. Appl. No. 11/744,142.
46 Amendment filed May 29, 2007 in response to Mar. 30, 2007 Notice, U.S. Appl. No. 11/097,829 0.
47 Amendment filed May 29, 2007 in response to Mar. 30, 2007 Notice, U.S. Appl. No. 11/097,829.
48 Amendment filed Nov. 9, 2009 in response to Oct. 7, 2009 Office Action, U.S. Appl. No. 11/849,162.
49 Amendment filed Nov. 9, 2009 in response to Oct. 7, 2009 Office Action, U.S. Appl. No. 12/143,157 0.
50 Amendment filed Nov. 9, 2009 in response to Oct. 7, 2009 Office Action, U.S. Appl. No. 12/143,157.
51 Amendment filed Oct. 1, 2008 in response to Jul. 1, 2010 Office Action, U.S. Appl. No. 11/744,153.
52 Amendment filed Oct. 11, 2008 in response to Jul. 1, 2010 Office Action, App. No. 111744,153 0.
53 Amendment filed Oct. 14, 2008 in response to Sep. 15, 2008 Office Action, U.S. Appl. No. 11/016,558.
54 Amendment filed Sep. 19, 2007 in response to Jul. 19, 2007 Office Action, U.S. Appl. No. 11/016,558.
55 Chinese Office Action for Application No. 200980149285.2 dated Feb. 28, 2014.
56 Chinese Office Action for Application No. 201080035256.6 dated Jul. 17, 2014.
57 Chinese Office Action for Application No. 201180031606.6 dated Dec. 11, 2014.
58 Chinese Office Action for Application No. 201310240369.5 dated May 28, 2015.
59 EP Supplemental Search Report mailed Nov. 5, 2007, EP Application No. 05736129.7.
60 EP Supplementary Search Report dated Jun. 5, 2008 and mailed Jun. 12, 2008 for EP App. No. 05735136.3.
61 EP Supplementary Search Report mailed Jun. 5, 2008, EP App. No. 05735136.3.
62 Ex Parte Quayle Action mailed 217/06, U.S. Appl. No. 11/090,969
63 Final Office Action mailed 118/07, U.S. Appl. No. 11/097,829 D.
64 Final Office Action mailed Jan. 8, 2007, U.S. Appl. No. 11/097,829.
65 Final Office Action mailed Jul. 1, 2010, U.S. Appl. No. 11/744,153 0.
66 Final Office Action mailed Jul. 1, 2010, U.S. Appl. No. 11/744,153.
67 Final Office Action mailed Jul. 19, 2007, U.S. Appl. No. 11/016,558.
68 Final Office Action mailed Mar. 1, 2011, U.S. Appl. No. 12/251,624 0.
69 Final Office Action mailed Mar. 1, 2011, U.S. Appl. No. 12/251,624.
70 Final Office Action mailed Mar. 18, 2010, App No. 111744,142 D.
71 Final Office Action mailed Mar. 18, 2010, U.S. Appl. No. 11/744,142.
72 Final Office Action mailed Sep. 15, 2008, U.S. Appl. No. 11/016,558.
73 Final Office Action, mailed Aug. 5, 2010, Appl. No. 12/143,157 0.
74 Final Office Action, mailed Aug. 5, 2010, U.S. Appl. No. 12/143,157.
75 Final Rejection for U.S. Appl. No. 12/913,529 dated Jul. 9, 2014.
76 International Preliminary Report on Patentability for Application PCT/US2008/067541 mailed Jan. 7, 2010.
77 International Search Report & Wrillen Opinion, Application N90. PCT/US2008/066561, dated Dec. 31, 2008.
78 International Search Report and Wrillen Opinion, Appl. No. PCT/US2008/067722, dated Feb. 25, 2009.
79 International Search Report and Written Opinion dated Apr. 12, 2010, App. No. PCTIUS2009/55421 0.
80 International Search Report and Written Opinion dated Jan. 26, 2011, App. No. PCT/US2010/39639.
81 International Search Report and Written Opinion dated Mar. 17, 2009, App. No. PCT/US2008/079948.
82 International Search Report and Written Opinion dated Mar. 6, 2009, App. No. PCT/US2008/173365 0.
83 International Search Report and Written Opinion dated Oct. 6, 2009 , App. No. PCTIUS2009/36921 0.
84 International Search Report and Written Opinion for Application No. PCT/US08/09207 dated Jan. 16, 2009.
85 International Search Report and Written Opinion for Application No. PCT/US2009/047389 dated Jan. 14, 2010.
86 International Search Report and Written Opinion for Application No. PCT/US2010/054325 dated Jul. 28, 2011.
87 International Search Report and Written Opinion for PCT Application No. PCT/US2008/065788, mailed Sep. 30, 2008.
88 International Search Report and Written Opinion mailed Mar. 23, 2009, International Application No. PCT/US2008/074450.
89 International Search Report and Written Opnion for Application PCT/US20071021552 dated May 29, 2008.
90 International Search Report for Application No. PCT/US2009/003643 dated Aug. 28, 2009.
91 International Search Report for Application No. PCT/US2009/067386 dated Jul. 1, 2010.
92 International Search Report for Application No. PCT/US2010/039639 dated Jan. 26, 2011.
93 International Search Report for Application No. PCT/US2010/055472 dated Jul. 27, 2011.
94 International Search Report for PCT Application No. PCT/US2008/065793, mailed Dec. 22, 2008.
95 International Search Report for PCT Application No. PCT/US2008/067541 mailed Oct. 27, 2008.
96 Japanese Office Action for Application No. 2010-550853 dated Sep. 18, 2013.
97 Japanese Office Action for Application No. 2011540873 dated Jan. 22, 2014.
98 Japanese Office Action for Application No. 2012-517680 dated Jul. 25, 2014.
99 Japanese Office Action for Application No. 2012-517680 dated Jun. 1, 2015.
100 Ko, et al. Development of three-dimensional memory die stack packages using polymer insulated sidewall technique, 1999.
101 Non-Final Office Action for U.S. Appl. No. 12/913,529 dated Dec. 12, 2014.
102 Non-Final Office Action for U.S. Appl. No. 12/913,529 dated Dec. 20, 2013.
103 Notice of Allowability, mailed Oct. 19, 2006 U.S. Appl. No. 11/090,969.
104 Notice of Allowability, mailed Oct. 19, 2006, U.S. Appl. No. 11/090,969 D.
105 Notice of Allowability, mailed Oct. 19, 2006, U.S. Appl. No. 11/090,969.
106 Notice of Allowance mailed Dec. 17, 2009, U.S. Appl. No. 11/016,558.
107 Notice of Allowance mailed Feb. 27, 2009, U.S. Appl. No. 11/744,153 0.
108 Notice of Allowance mailed Feb. 27, 2009, U.S. Appl. No. 11/744,153.
109 Notice of Allowance, mailed Feb. 12, 2007, U.S. Appl. No. 11/097,829 D.
110 Notice of Allowance, mailed Feb. 12, 2007, U.S. Appl. No. 11/097,829.
111 Notice of Appeal filed Sep. 16, 2010 in response to Mar. 18, 2010 Office Action, U.S. Appl. No. 11/744,142 D.
112 Notice of Appeal filed Sep. 16, 2010 in response to Mar. 18, 2010 Office Action, U.S. Appl. No. 11/744,142.
113 Notice to File Corrected Papers, mailed Mar. 30, 2007, U.S. Appl. No. 11/097,829 0.
114 Notice to File Corrected Papers, mailed Mar. 30, 2007, U.S. Appl. No. 11/097,829.
115 Office Action (Restriction) mailed Apr. 20, 2009, U.S. Appl. No. 11/744,142 D.
116 Office Action (Restriction) mailed Apr. 20, 2009, U.S. Appl. No. 11/744,142.
117 Office Action (Restriction) mailed Dec. 28, 2010, U.S. Appl. No. 12/403,175 0.
118 Office Action (Restriction) mailed Dec. 28, 2010, U.S. Appl. No. 12/403,175.
119 Office Action (Restriction) mailed Feb. 4, 2010, U.S. Appl. No. 12/251,624 0.
120 Office Action (Restriction) mailed Feb. 4, 2010, U.S. Appl. No. 12/251,624.
121 Office Action (Restriction) mailed Jan. 21, 2010, U.S. Appl. No. 12/046,651.
122 Office Action (Restriction) mailed Jun. 24, 2009, U.S. Appl. No. 11/849,162.
123 Office Action (Restriction) mailed May 24, 2010, U.S. Appl. No. 12/124,097 D.
124 Office Action (Restriction) mailed May 24, 2010, U.S. Appl. No. 12/124,097.
125 Office Action (Restriction) mailed Oct. 7, 2009, U.S. Appl. No. 11/849,162.
126 Office Action (Restriction) mailed Oct. 7, 2009, U.S. Appl. No. 12/143,157 0.
127 Office Action (Restriction) mailed Oct. 7, 2009, U.S. Appl. No. 12/143,157.
128 Office Action mailed 217106, U.S. Appl. No. 11/097,829 D.
129 Office Action mailed Aug. 18, 2010, U.S. Appl. No. 12/046,651.
130 Office Action mailed Aug. 3, 2009, U.S. Appl. No. 11/744,142 D.
131 Office Action mailed Aug. 3, 2009, U.S. Appl. No. 11/744,142.
132 Office Action mailed Dec. 1, 2009, U.S. Appl. No. 12/142,589, titled "Wafer level surface passivation of stackable integrated circuit chips".
133 Office Action mailed Dec. 15, 2008, U.S. Appl. No. 11/016,558.
134 Office Action mailed Dec. 22, 2006, U.S. Appl. No. 11/016,558.
135 Office Action mailed Dec. 30, 2009, U.S. Appl. No. 12/143,157 0.
136 Office Action mailed Dec. 30, 2009, U.S. Appl. No. 12/143,157.
137 Office Action mailed Dec. 31, 2007, U.S. Appl. No. 11/744,153 0.
138 Office Action mailed Dec. 31, 2007, U.S. Appl. No. 11/744,153.
139 Office Action mailed Feb. 7, 2006, U.S. Appl. No. 11/097,829.
140 Office Action mailed Jan. 27, 2009, U.S. Appl. No. 11/849,162.
141 Office Action mailed Jul. 15, 2009, U.S. Appl. No. 11/016,558.
142 Office Action mailed Jul. 21, 2010, U.S. Appl. No. 11/849,162.
143 Office Action mailed Jun. 9, 2010, U.S. Appl. No. 12/251,624 0.
144 Office Action mailed Jun. 9, 2010, U.S. Appl. No. 12/251,624.
145 Office Action mailed Mar. 1, 2011, U.S. Appl. No. 12/143,157 0.
146 Office Action mailed Mar. 1, 2011, U.S. Appl. No. 12/143,157.
147 Office Action mailed Mar. 19, 2008, EP Application No. 05736129.7.
148 Office Action mailed Mar. 27, 2008, U.S. Appl. No. 11/016,558.
149 Office Action mailed Oct. 14, 2010, U.S. Appl. No. 12/124,097 D.
150 Office Action mailed Oct. 14, 2010, U.S. Appl. No. 12/124,097.
151 Response filed Aug. 5, 2009 in response to Jul. 15, 2009 Office Action, U.S. Appl. No. 11/016,558.
152 Response filed Oct. 19, 2007 to Oct. 10, 2007 Advisory Action, U.S. Appl. No. 11/016,558.
153 Supplemental Amendement filed Aug. 5, 2009, App. No. 111849,162.
154 Taiwanese Office Action and Search Report for Application No. 099137634 dated Dec. 22, 2015.
155 Taiwanese Office Action for Application No. 098108067 dated Dec. 25, 2013.
156 Taiwanese Office Action for Application No. 098119939 dated Aug. 29, 2014.
157 Taiwanese Office Action for Application No. 099136720 dated May 18, 2015.
158 Twainese Office Action for Application No. 10117575 dated Sep. 18, 2015.
159 U.S. Appl. No. 12/124,097, filed May 20, 2008.
160 Written Opinion of the International Searching Authority for Application No. No. PCT/US2010/055472 dated Jul. 27, 2011.
161 Written Opinion of the International Searching Authority for Application No. PCT/US2009/067386 dated Jul. 1, 2010.
162 Written Opinion of the International Searching Authority for Application No. PCT/US2010/039639 dated Jan. 26, 2011.
Clasificación internacional H01L25/065, H01L21/56, H01L21/768, H01L21/02, H01L25/00, H01L23/00, H01L21/324, H01L21/31, H01L21/469
Clasificación cooperativa H01L2224/76155, H01L21/02282, H01L2224/82355, H01L25/0657, H01L2924/01006, H01L2924/01082, H01L21/02288, H01L2924/14, H01L2224/24145, H01L21/76828, H01L2225/06524, H01L2924/01005, H01L2224/82101, H01L2924/01033, H01L2225/06562, H01L25/50, H01L2224/19, H01L21/31, H01L2924/01074, H01L24/19, H01L2924/01056, H01L21/76801, H01L2224/82051, H01L24/82, H01L24/25, H01L2224/82102, H01L2924/01047, H01L2225/06551, H01L24/24, H01L21/324, H01L2924/01013, H01L21/56
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEAL, JEFFREY S.;REEL/FRAME:036680/0360
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:VERTICAL CIRCUITS, INC.;REEL/FRAME:036692/0833
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:VERTICAL CIRCUITS (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC;REEL/FRAME:036702/0654