Source: http://www.google.fr/patents/US5468987
Timestamp: 2013-12-06 07:11:15
Document Index: 119487911

Matched Legal Cases: ['Application No. 3', 'Application No. 3', 'Application No. 4', 'Application No. 4', 'Application No. 4', 'Application No. 4', 'Application No. 4', 'Application No. 4', 'Application No. 4', 'Application No. 3']

Brevet US5468987 - Semiconductor device and method for forming the same - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Connexion Recherche avanc�e dans les brevets BrevetsIn a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate eiectrode and the gate insulating film to prevent invasion of movable...http://www.google.fr/patents/US5468987?utm_source=gb-gplus-shareBrevet US5468987 - Semiconductor device and method for forming the same Num�ro de publicationUS5468987 AType de publicationOctroi Num�ro de demandeUS 08/037,162 Date de publication21 nov. 1995 Date de d�p�t25 mars 1993 Date de priorit�6 mars 1991�tat de paiement des fraisPay�Autre r�f�rence de publicationUS5879969 Num�ro de publication037162, 08037162, US 5468987 A, US 5468987A, US-A-5468987, US5468987 A, US5468987A InventeursYasuhiko Takamura, Shunpei Yamazaki, Hongyong Zhang Cessionnaire d'origineSemiconductor Energy Laboratory Co., Ltd.Citations de brevets (11), R�f�renc� par (87), Classifications (35), �v�nements juridiques (5) Liens externes: USPTO, Cession USPTO, EspacenetSemiconductor device and method for forming the sameUS 5468987 A R�sum� In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate eiectrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate eiectrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion. Further, an aluminum oxide or silicon nitride is formed as an etching stopper between the gate electrode and the gate insulating film or between the substrate and the layer on the substrate, so that the over-etching can be prevented and the flatness of the eiement can be improved. In addition, a contact is formed in no consideration of the concept "contact hole".
What is claimed is: 1. An insulated gate thin film transistor comprising:a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer located over said channel region with said first insulating layer therebetween, said second insulating layer having opposed side edges; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween; and an anodic oxide coating covering a surface of said gate electrode, said oxide coating being formed by anodic oxidizing a surface of said gate electrode, wherein said first insulating layer extends beyond said side edges of the second insulating layer to cover a major surface of said source and drain regions and said side edges of the second insulating layer are approximately coextensive with edges of said anodic oxide coating. 2. The transistor of claim 1 wherein said side edges of said second insulating layer approximately correspond to boundaries between said source and channel regions and between said drain and channel regions.
3. An insulated gate field effect transistor comprising:a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer laminated on said first insulating layer; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween; and an anodic oxide coating formed on said gate electrode, wherein a boundary between said source and channel regions and a boundary between said drain and channel regions are each approximately aligned with side edges of both said first insulating layer and said second insulating layer. 4. The transistor of claim 3 wherein said side edges of both said first insulating layer and said second insulating layer are substantially aligned with side edges of said anodic oxide coating.
5. An insulated gate thin film transistor comprising:a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer located over said channel region with said first insulating layer therebetween, said second insulating layer having opposed side edges; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween, wherein said first insulating layer extends beyond said side edges of the second insulating layer to cover a major upper surface of said source and drain regions. 6. The transistor of claim 5 Wherein said side edges of said second insulating layer approximately correspond to boundaries between said source and channel regions and between said drain and channel regions, respectively.
8. An insulated gate field effect transistor comprising:a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer located over said channel region with said first insulating layer therebetween; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween, wherein both of said first insulating layer and said second insulating layer cover an upper surface of said source, drain and channel regions. 9. The transistor of claim 8 wherein at least one contact hole is provided for one of said source and drain regions through said first and second insulating layer.
15. An insulated gate thin film transistor comprising:a semiconductor layer having source, drain and channel regions therein; a first insulating layer contacting said semiconductor layer; a second insulating layer laminated on said first insulating layer; a gate electrode provided adjacent to said channel region with said first insulating layer and said second insulating layer interposed therebetween; and an anodic oxide coating formed on said gate electrode, wherein said second insulating layer has a higher conductivity than said first insulating layer. 16. The transistor of claim 15 wherein said first insulating layer comprises silicon oxide.
[Embodiment 1] FIG. 1 is cross-sectional views showing a manufacturing process of an embodiment. The detailed conditions of this embodiment are substantially identical to those of Japanese Patent Application No. 3-237100 which was filed by the inventor of this application, et.al, and the description thereof is not particularly made.
An N-O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 101. This glass has high strain temperature, but contains a large amount of lithium and natrium. Therefore, in order to prevent invasion of these movable ions from the substrate, a silicon nitride film 102 was formed in thickness of 10 to 50 nm on the substrate by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film serving as a sealer was formed in thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600 crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process by the photolithography and the reactive ion etching (RIE) method, thereby forming islandish semiconductor regions 104 (for N-channel TFT) and 105 (for P-channel TFT) as shown in FIG. 1(A).
Through these processes, the structure as shown in FIG. 1(C) was obtained. Naturally, the portion doped with the impurity by the ion injection method had low crystallinity, and thus it was substantially in a non-crystal state (amorphous state, or a polycrystal state close to the amorphous state). Therefore, a laser anneal treatment was conducted to restore crystallinity at the portion. This process may be carried out by a heat annealing treatment at 600 annealing condition as disclosed in Japanese Patent Application No. 3-237100 for example was adopted.
[Embodiment 2] FIG. 2 shows an embodiment in which this invention was applied to a TFT having two-layered channel which was invented by the inventor of this application, et.al., and described in applications filed on Feb. 25, 1992 entitled "THIN FILM INSULATING GATE TYPE OF SEMICONDUCTOR DEVICE AND A PRODUCING METHOD THEREFOR" (applicant: Semiconductor Energy Laboratory Co., Ltd, docketing numbers: P002042-01 to P002044-03).
[Embodiment 3] FIG. 3 shows a process for performing an anodic oxidation and then wiring using this invention. First, plural islandish semiconductor regions 302 were formed like the Embodiment 1, and a gate insulating film and a silicon, nitride film of this invention (if occasion demands) were formed. Thereafter, aluminum gate electrode/wirings 303 were formed as a first conductor layer by patterning (FIG. 3(A)).
[Embodiment 4] FIG. 4 is cross-sectional views showing a manufacturing process of this embodiment. The detailed conditions of this embodiment are substantially identical to those of Japanese Patent Application No. 4-30220 or No. 4-38837, and thus the description thereof is eliminated.
An N-O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 1. This glass has high strain temperature, but contains a large amount of lithium and natrium. Therefore, in order to prevent invasion of these movable ions from the substrate, a silicon nitride film 2 was formed in thickness of 10 to 50 nm on the substrate by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film serving as a sealer was formed in thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600 for 12 to 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process by the photolithography and the reactive ion etching (RIE) method, thereby forming islandish semiconductor regions 4 (for N-channel TFT) and 105 (for P-channel TFT) as shown in FIG. 4(A).
Through these processes, the structure as shown in FIG. 4(D) was obtained. Naturally, the portion doped with the impurity by the ion injection method had low crystallinity, and thus it was substantially in a non-crystal state (amorphous state, or a polycrystal state close to the amorphous state). Therefore, a laser anneal treatment was conducted to restore crystallinity at the portion. This process may be carried out by a heat annealing treatment at 600 annealing condition as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 preferably 500 to 700 torr), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.).
[Embodiment 5] FIG. 5 is cross-sectional views showing a manufacturing process of this embodiment. The detailed conditions of this embodiment are substantially identical to those of Japanese Patent Application No. 4-30220, and thus the description thereof is eliminated.
An N-O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 401. A silicon nitride film 402 was formed in thickness of 10 to 50 nm on the substrate by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film 403 serving as a sealer was formed in thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600 at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process to form islandish semiconductor regions 404 (for N-channel TFT) and 405 (for P-channel TFT) as shown in FIG. 5(A).
Through these processes, the structure as shown in FIG. 5(D) was obtained. In the laser doping technique, unlike the Embodiment 4, no laser annealing process or no heat annealing process is required because the injection of the impurities and the annealing treatment are simultaneously carried out. After the laser doping treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 atmosphere (1 to 700 torr or 500 to 700 torr), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.).
[Embodiment 6] FIG. 6 is cross-sectional views showing a manufacturing process of this embodiment. The detailed conditions of this embodiment are substantially identical to those of Japanese Patent Application No. 4-30220, and thus the description thereof is eliminated.
An N-O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 501. A silicon nitride film 502 was formed in thickness of 10 to 50 nm on the substrate by the plasma CVD method or the low pressure CVD method. Further, a silicon oxide film 503 serving as a sealer was formed in thickness of 100 to 800 nm by the sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process to form islandish semiconductor regions 504 (for N-channel TFT) and 505 (for P-channel TFT) as shown in FIG. 6(A).
Through these processes, the structure as shown in FIG. 6(D) was obtained. Naturally, the crystallinity of the portions to which the impurities were injected by the ion injection was extremely low, and these portions were substantially in a non-crystal state (amorphous state or polycrystal state close to the amorphous state). Therefore, the crystallinity was restored by the laser annealing treatment. This process may be replaced by the heat annealing treatment at 600 laser annealing treatment as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. Here, no short-wavelength ultraviolet rays below 250 nm wavelength is passed through the silicon nitride film 507, so that XeCl laser (308 nm wavelength) or XeF laser (351 nm wavelength) was used.
After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 hydrogen atmosphere (1 to 700 torr or 500 to 700 torr), to thereby depress lattice defects (dangling bond, etc.). Actually, delivery of hydrogen was little carried out between the inside of the semiconductor region and the outside thereof because the silicon nitride film 507 exists. Therefore, a large amount of hydrogen atoms are simultaneously injected into the semiconductor region in the plasma doping method, and on the other hand, in the ion injection method, a process of injecting hydrogen atoms is separately required. If the amount of hydrogen atoms is insufficient, hydrogen atoms are required to be separately doped even in the plasma doping method.
[Embodiment 7] FIG. 5 shows an embodiment in which this invention was applied to the TFT having two-layered channel which was invented by the inventor of this application, et.al., and described in applications filed on Feb. 25, 1992 entitled "THIN FILM ENSULATING GATE TYPE OF SEMICONDUCTOR DEVICE AND A PRODUCING METHOD THEREFOR" (applicant: Semiconductor Energy Laboratory Co., Ltd, docketing numbers: P002042-01 to P002044-03).
[Embodiment 8] FIG. 13 is cross-sectional views showing a manufacturing process of this embodiment.
An N-O glass produced by Nippon Electric Glass Co., Ltd was used as a substrate 1001. This glass has high strain temperature, however, contains a large amount of lithium and natrium. Therefore, in order to prevent invasion of these movable ions from the substrate and in order to prevent the over-etching, an aluminum oxide film 1002 was formed on the substrate 1001 in thickness of 10 to 50 nm by an organic metal CVD method. Further, a silicon oxide film 1003 serving as a sealer was formed on the aluminum oxide film 1002 in thickness of 100 to 800 nm by the sputtering method. An amorphous silicon film was formed in thickness of 20 to 100 nm on the silicon oxide film 1003 by the plasma CVD method, and then annealed at 600 crystallized. The result was subjected to the patterning process by the photolithography and the reactive ion etching (RIE) method to form islandish semiconductor regions 1004.
Subsequently, N-type impurity was doped into the semiconductor region 1004 by the well-known ion injection method to form N-type impurity regions (source, drain) 1005 and 1006. In the manner as described above, the structure as shown in FIG. 13(A) was obtained. Naturally, the crystallinity at the portion doped with the impurities by the ion injection method was extremely low, and this portion was substantially in a noncrystal (amorphous state, or polycrystal state close to the amorphous state). Therefore, the crystallinity at the portion was restored by the laser annealing treatment. This process may be replaced by the heat annealing treatment at 600 condition as disclosed in Japanese Patent Application No. 4-30220 for example was adopted. After the laser annealing treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 450 700 torr) to inject hydrogen atoms into the semiconductor region and depress the lattice defect (dangling bond, etc.).
[Embodiment 9] FIG. 14 is cross-sectional views showing a manufacturing process of this embodiment.
An N-O glass produced by Nippon Electric Glass Co., Ltd. was used as a substrate 1101. A silicon nitride film 1102 was formed in thickness of 10 to 50 nm on the substrate by the plasma CVD method or the low pressure CVD method. Further, a silicon oxide film 1103 serving as a sealer was formed in thickness of 100 to 800 nm by the sputtering method. An amorphous silicon film was formed on the silicon oxide film in thickness of 20 to 100 nm by the plasma CVD method, and annealed at 600 72 hours at nitrogen atmosphere to crystallize the amorphous silicon film. Subsequently, this result was subjected to a patterning process to form islandish semiconductor regions 1104.
Thereafter, an aluminum film was formed by the sputtering method or the electron beam deposition method, and then subjected to a patterning process to form gate electrode/wirings 1107 to 1109. Further, current was supplied to the gate electrode/wirings 1107 to 1109 in the electrolyte to form aluminum oxide films 1110 to 1112 by the anodic oxidation method. The anodic oxidation condition as disclosed in Japanese Patent Application No. 4-30220 which was invented by the inventor of this application, et.al was adopted in this embodiment. Further, by the laser doping technique (Japanese Patent Application No. 3-283981) which was invented by the inventor of this application, et.al, N-type impurity was doped into the semiconductor region 1104, thereby forming an N-type impurity region (source, drain). The laser doping method requires no laser annealing treatment and no heat annealing treatment which were required for the Embodiment 8 because the injection of the impurities and the annealing treatment were simultaneously carried out. After the laser doping treatment, the annealing treatment was carried out for 30 minutes to 3 hours at 250 tort or 500 to 700 tort), to thereby add hydrogen to the semiconductor region and depress lattice defects (dangling bond, etc.). This state is shown in FIG. 14(A).
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A-1D show a process for producing a semiconductor device (cross-sectional view) according to this invention;
SUMMARY OF THE INVENTION An object of this invention is to provide an insulating gate type of semiconductor device (an insulated gate field effect transistor) and a producing method therefor in which an overetching phenomenon is depressed to prohibit the diffusion of foreign elements from a substrate and flatness of the device is further improved.
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intensity profile* Cit� par l'examinateurClassifications Classification aux �tats-Unis257/412, 257/640, 257/E21.413, 257/308, 257/406, 257/E29.293, 257/E27.111, 257/411, 257/E29.151, 257/E29.29 Classification internationaleH01L21/60, G02F1/1362, H01L21/77, H01L29/786, H01L21/336, H01L27/12, H01L29/49 Classification coop�rativeH01L27/1214, G02F1/13454, H01L29/78675, G02F2001/136245, H01L29/78651, H01L29/4908, H01L29/78666, H01L27/12, H01L21/76897, H01L29/66757 Classification europ�enneH01L29/66M6T6F15A2, H01L21/768S, H01L29/786E, H01L27/12T, H01L27/12, H01L29/786E4B2, H01L29/49B, H01L29/786E4C2�v�nements juridiques DateCode�v�nementDescription27 avr. 2007FPAYFee paymentYear of fee payment: 1230 avr. 2003FPAYFee paymentYear of fee payment: 810 mai 1999FPAYFee paymentYear of fee payment: 420 mai 1993ASAssignmentOwner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAMAZAKI, SHUNPEI;ZHANG, HONGYONG;TAKEMURA, YASUHIKO;REEL/FRAME:006487/0798;SIGNING DATES FROM 19930421 TO 1993051220 mai 1993AS02Assignment of assignor's interestOwner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. 398, HASEffective date: 19930421Owner name: TAKEMURA, YASUHIKOEffective date: 19930428Owner name: YAMAZAKI, SHUNPEIOwner name: ZHANG, HONGYONGEffective date: 19930512Faire pivoterImage d'origineAccueil Google - Plan du site - T�l�chargements par lot sur l'USPTO - R�gles de confidentialit� - Conditions d'utilisation - � propos de Google�Brevets - Envoyer des commentairesDonn�es fournies par IFI CLAIMS Patent Services©2012 Google