Source: http://www.google.com/patents/US7529137?dq=552685
Timestamp: 2016-06-29 09:07:44
Document Index: 632921

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'application No. 60', 'art 2', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093']

Patent US7529137 - Methods of operating bandgap engineered memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsMemory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having...http://www.google.com/patents/US7529137?utm_source=gb-gplus-sharePatent US7529137 - Methods of operating bandgap engineered memoryAdvanced Patent SearchPublication numberUS7529137 B2Publication typeGrantApplication numberUS 11/830,582Publication dateMay 5, 2009Filing dateJul 30, 2007Priority dateJan 3, 2005Fee statusPaidAlso published asUS8264028, US20060202261, US20070268753Publication number11830582, 830582, US 7529137 B2, US 7529137B2, US-B2-7529137, US7529137 B2, US7529137B2InventorsHang-Ting Lue, Szu-Yu WangOriginal AssigneeMacronix International Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (64), Non-Patent Citations (37), Referenced by (4), Classifications (15), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethods of operating bandgap engineered memory
US 7529137 B2Abstract
Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.
This application is a continuation of U.S. patent application Ser. No. 11/324,540, filed Jan. 3, 2006, which is based upon, and claims priority under 35 U.S.C. �119(e) of: provisional U.S. Patent Application No. 60/640,229, filed on Jan. 3, 2005; provisional U.S. Patent Application No. 60/647,012, filed on Jan. 27, 2005; provisional U.S. Patent Application No. 60/689,231, filed on Jun. 10, 2005; and provisional U.S. patent application No. 60/689,314, filed on Jun. 10, 2005; the entire contents of each of which are incorporated herein by reference.
Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell. NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash Memory. Non-volatile memory is extensively used in the semiconductor industry and is a class of memory developed to prevent loss of programmed data. Typically, non-volatile memory can be programmed, read and/or erased based on the device's end-use requirements, and the programmed data can be stored for a long period of time.
The present invention relates to non-volatile memory devices, and more specifically, to non-volatile memory devices including a tunnel dielectric structure that facilitates self-converging erase operations while also maintaining charge retention in a charge storage layer of the memory device during retention states.
The present invention also includes non-volatile memory devices which comprise a plurality of memory cells (i.e., an array) in accordance with one or more of the embodiments described herein. As used herein, a “plurality” refers to two or more. Memory devices in accordance with the present invention exhibit significantly improved operational properties including increased erase speeds, improved charge retention and larger windows of operation.
The present invention also includes methods of operating non-volatile memory cells and arrays. Methods of operation in accordance with the present invention include resetting the memory devices by applying a self-converging method to tighten Vt distribution of the memory devices; programming at least one of the memory devices by channel +FN injection; and reading at least one of the memory devices by applying a voltage between an erased state level and a programmed state level of at least one of the memory devices. As used herein, the term “tighten” refers to the narrowing of the threshold voltage distribution among the many memory cells of an array. In general, threshold voltage distribution is “tightened” where the threshold voltages of several cells are within a narrow range of one another such that operation of the array is improved over conventional designs. For example, in some preferred embodiments, such as in a NAND array comprising memory cells in accordance with one or more embodiments of the present invention, a “tightened” threshold voltage distribution indicates that the threshold voltages of the various memory cells are within a 0.5V range of one another. In other array architectures employing memory cells in accordance with the present invention, the “tightened” threshold voltage distribution may have a range of about 1.0V from the upper limit to the lower limit.
As used herein, the phrase “small hole tunneling barrier height” refers generally to values which are less than the approximate hole tunneling barrier height of silicon dioxide. In particular, a small hole tunneling barrier height is preferably less than about 4.5 eV. More preferably, a small hole tunneling barrier height is less than or equal to about 1.9 eV.
Reference will now be made in detail to the invention and the presently preferred embodiments thereof, examples of which are illustrated in the accompanying drawings. Wherever possible, the same or similar reference numbers are used in the drawings and the description to refer to the same or like parts. It should be noted that the non-graph drawings are in greatly simplified form and are not to precise scale. In reference to the disclosure herein, for purposes of convenience and clarity only, directional terms, such as top, bottom, left, right, up, down, above, below, beneath, rear, and front, are used with respect to the accompanying drawings. Such directional terms used in conjunction with the following description of the drawings should not be construed to limit the scope of the invention in any manner not explicitly set forth in the appended claims. Although the disclosure herein refers to certain illustrated embodiments, it is to be understood that these embodiments are presented by way of example and not by way of limitation. It is to be understood and appreciated that the process steps and structures described herein do not cover a complete process flow for the manufacture of entire integrated circuits. The present invention may be practiced in conjunction with various integrated circuit fabrication techniques that are known in the art or to be developed.
Thus, for example, as depicted in FIGS. 1 a and 1 b, memory cells in accordance with the present invention may include: a multi-layer thin film tunnel dielectric structure, including a first silicon oxide layer O1, a first silicon nitride layer N1, and a second silicon oxide layer O2; a charge-storage layer, such as a second silicon nitride layer N2; and an insulating layer such as a third silicon oxide layer O3, on or over (“above”) a substrate, such as a semiconductor substrate (e.g., a silicon substrate). The tunneling dielectric structure allows hole tunneling from the substrate to the charge-storage layer during an erase/reset operation of the memory device. Preferably, the tunnel dielectric structure in a non-volatile memory cell of the present invention has a negligible charge-trapping efficiency, and more preferably, does not trap charge at all during memory operations.
FIGS. 14 a and 14 b illustrate possible electrical RESET schemes for an exemplary virtual ground array incorporating 2 bits/cell memory cells having a tunnel dielectric design discussed above. Before performing further P/E cycles, all the devices may first undergo an electrical “RESET”. A RESET process may ensure the Vt uniformity of memory cells in the same array and raise the device Vt to the convergent erased state. For example, applying Vg=−15 V for 1 sec, as shown in FIG. 14 a, may have the effect of injecting some charge into a charge trapping layer of silicon nitride to reach a dynamic balancing condition. With the RESET, even memory cells that are non-uniformly charged due, for example, to the plasma charging effect during their fabrication processes may have their Vt converged. An alternative way for creating a self-converging bias condition is to provide bias for both gate and substrate voltages. For example, referring to FIG. 14 b, Vg=−8 V and P-well=+7 V may be applied.
Referring to FIG. 23 a, in one example, the spaces (Ls) between word lines (WLs) may be formed with shallow junctions, such as shallow junctions of N+-doped regions, which may serve as source or drain regions of the memory devices. As illustrated in FIG. 23A, additional implantation and/or diffusion process, such as a tilt-angle pocket implantation, may be carried out to provide one or more “pocket” regions or pocket extensions of junctions that neighbor one or more of the shallow junction regions. In some examples, such configuration may provide better device characteristics.
After a memory array is manufactured, a reset operation may be performed to tighten the Vt distribution first before other operations of the memory array. FIG. 24 a illustrates an example of such operation. In one example, before other operations start, one may first apply VG=about −7 V and VP-well=+8 V to reset the array (The voltage drop of VG and VP-Well can be partitioned into the gate voltage into each WL and p-well). During RESET, the BL's can be floating, or raised to the same voltage as the P-Well. As illustrated in FIG. 24 b, the reset operation may provide excellent self-convergent properties. In one example, even SONONOS devices are initially charged to various Vts, the reset operation can “tighten” them to a Reset/Erase state. In one example, the reset time is about 100 msec. In that example, the memory array may use n-channel SONONOS devices with ONONO=15/20/18/70/90 angstroms having an N+-polysilicon gate with Lg/W=0.22/0.6 μm.
Generally, traditionally floating-gate devices are not capable of providing self-converging erase. In contrast, SONONOS devices may be operated with converging Reset/Erase methods. In some examples, this operation may become essential because the initial Vt distribution is often in a wide range due to certain process issues, such as process non-uniformity or plasma charging effects. The exemplary self-converging “Reset” may help to tighten, or narrow the range of, the initial Vt distribution of memory devices.
In examples of read operations, the selected WL may be raised to a voltage that is between an erased state level (EV) and a programmed state level (PV). Other WLs may serve as the “PASS gates” so that their gate voltages may be raised a voltage higher than PV. In some examples, erase operations may be similar to the reset operation noted above, which may allow self-convergence to the same or similar reset Vt.
In some examples, a split-gate design, such as a split-gate SONONOS-NAND design, may be used to achieve a more aggressive down-scaling of a memory array. FIG. 31 illustrates an example of using such design. Referring to FIG. 31, the spaces (Ls) between each word line, or between two neighboring memory devices sharing the same bit line, may be reduced. In one example, Ls may be shrunk to about or less than 30 nm. As illustrated, the memory devices using a split-gate design along the same bit line may share only one source region and one drain region. In other words, a split-gate SONONOS-NAND array may use no diffusion regions or junctions, such as N+-doped regions, for some of the memory devices. In one example, the design may also reduce or eliminate the need for shallow junctions and neighboring “pockets”, which in some examples may involve a more complicated manufacturing process. Furthermore, in some examples, the design is less affected by short-channel effects, because the channel length has been increased, such as increased to Lg=2F-Ls in one example.
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Digest, 2002, 931-934.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8264028 *Sep 11, 2012Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysUS8304911Nov 6, 2012Macronix International Co., Ltd.Semiconductor structure and manufacturing method of the sameUS9019764Nov 19, 2012Apr 28, 2015Aplus Flash Technology, Inc.Low-voltage page buffer to be used in NVM designUS20060202261 *Jan 3, 2006Sep 14, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays* Cited by examinerClassifications U.S. Classification365/185.28, 365/185.18, 365/185.01International ClassificationG11C16/04Cooperative ClassificationH01L29/66833, H01L27/11568, H01L27/115, G11C16/0491, G11C16/0475, G11C16/0483, H01L29/792European ClassificationH01L29/66M6T6F18, H01L29/792, H01L27/115, H01L27/115G4Legal EventsDateCodeEventDescriptionJan 19, 2010CCCertificate of correctionOct 1, 2012FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services