Source: http://www.google.com/patents/US5384710?dq=6,249,089
Timestamp: 2013-12-08 09:54:30
Document Index: 738567126

Matched Legal Cases: ['art 7', 'art 8', 'art 18', 'art 2', 'art 3', 'arts 14', 'art 4', 'arts 5', 'arts 10']

Patent US5384710 - Circuit level netlist generation - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsA design layout sequence for an application specific integrated circuit such as a gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example, bias drivers, I/O macros, and relationships...http://www.google.com/patents/US5384710?utm_source=gb-gplus-sharePatent US5384710 - Circuit level netlist generationPublication numberUS5384710 APublication typeGrantApplication numberUS 08/173,808Publication dateJan 24, 1995Filing dateDec 22, 1993Priority dateMar 13, 1990Fee statusLapsedPublication number08173808, 173808, US 5384710 A, US 5384710A, US-A-5384710, US5384710 A, US5384710AInventorsAmrit K. Lalchandani, Nim C. LamOriginal AssigneeNational Semiconductor CorporationPatent Citations (6), Non-Patent Citations (4), Referenced by (41), Classifications (8), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetCircuit level netlist generationUS 5384710 AAbstract A design layout sequence for an application specific integrated circuit such as a gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example, bias drivers, I/O macros, and relationships between chip pads and I/O signals. The design layout sequence culminates in a physical data base file. The connectivity of this physical data base file is checked by first generating a circuit level netlist file for the entire option, and then comparing the circuit level netlist with the physical data base file. In generating the circuit level netlist file, information is obtained from the logic netlist file, as well as from some of the other files created in the design-layout sequence. In addition, basic information from which the circuit level netlist is constructed is obtained from a skeleton file library and a subcircuit library. The contents and methodology for deriving the skeleton file library and the subcircuit library are discussed.
Various structures of the MDL netlist of FIG. 5 are identifiable. The redefined macro includes fundamental components 40, 50, and 52 and nodes 54 and 56, which correspond to #RQNPN.sub.-- 1 (switching transistor, NPN type), #IRLH.sub.-- 1 (low power load resistor), #IQCSH.sub.-- 1 (low power current source), $NET1 (net) and $NET2 (net) respectively in the OR05DL macro MDL file of FIG. 5. The programmable inputs to the current switch 46 are the five standard components 41-45, which receive inputs A1-A5 respectively and correspond to NPN transistors #QNPN.sub.-- 2, #QNPN.sub.-- 5, #QNPN.sub.-- 4, #QNPN.sub.-- 3, and #QNPN.sub.-- 1 respectively in the OR05DL macro MDL file of FIG. 5. It should be noted that inputs not used merely are excluded from the circuit schematic netlist file, which physically corresponds to maintaining certain switching transistors unconnected in the physical data base 24. The programmable outputs of the current switch 46 are the two high level components 60 and 62, which correspond to output emitter followers #IQOEFL.sub.-- 1 and #IQOEFL.sub. -- 2 respectively in the OR05DL macro MDL file of FIG. 5.
Various structures of the MDL netlist of FIG. 6 are identifiable. The redefined macro includes fundamental components 70, 76, and 82 and two circuit nodes, which correspond to RQNPN.sub.-- 1 (switching transistor, NPN type), IRLHH.sub.-- 1 (high power load resistor), IQCSHH.sub.-- 1 (high power current source), $NET1 (net) and $NET2 (net). The programmable inputs to the current switch are the five standard components 71-75, which receive inputs A1-A5 respectively and correspond to NPN transistors #QNPN.sub.-- 2, #QNPN.sub.-- 5, #QNPN.sub.-- 4, #QNPN.sub.-- 3, and #QNPN.sub.-- 1 respectively in the OR05DL macro MDL file of FIG. 6. It should be noted that inputs not used merely are excluded from the circuit schematic netlist file, which physically corresponds to maintaining certain switching transistors unconnected in the physical database 24. The programmable outputs of the current switch are the two high level components 78 and 80, which correspond to output emitter followers IQOEFH.sub.-- 1 and IQOEFH.sub.-- 2 respectively in the OR05DH macro MDL file of FIG. 6.
In step 114, the programmable inputs and outputs are extracted from each redefined macro based on the pin names contained in file `MACRO.`OVR. The netlists remaining after extraction are the base skeleton files. For example, the base skeleton files for the low and high power configurations of the OR gate of FIG. 3 are OR05DL.LSK and OR05DL.HSK, which are shown in FIGS. 7A and 7B respectively. The base skeleton netlist file for OR05DL includes the MDL expression of switching transistor 40 (#RQNPN.sub.-- 1), low power load resistor 50 (#IRLH.sub.-- 1), and low power current source 52 (IQCSH.sub.-- 1). The base skeleton netlist file for OR05DH includes the MDL expression of switching transistor 70 (#RQNPN.sub.-- 1), high power load resistor 76 (#IRLHH.sub.-- 1), and high power current source 82 (IQCSHH.sub.-- 1).
Step 204 is the creation of netlist generation system input files for the customer option. The files GENNET.LIS, DESIGN.BOV, DESIGN.MVA, and XXAUTOPIN.S50 simply are copied and renamed OPTION.sub.-- GENNET.LIS, OPTION.sub.-- DES.BOV, OPTION.MVA, and OPTION.sub.-- APIN.S50, where "OPTION" is the name of the customer option.
Program GET.sub.-- TOKEN is a line parser that skips over blank Spaces and tab delimiters, and returns a valid token of a text line. Program MASKNAME masks out old I/O signal names from XXAUTOPIN.S50 with new I/O signal names. Program READS50 generates a new $50 file with correct signal names.
Programs GET.sub.-- TOKEN (Part 7 of the Appendix), MASKNAME (Part 8 of the Appendix), and READS50 (Part 18 of the Appendix) are sub-programs called by program AUTOIO as needed.
Step 210 is executed by the program DEFGEN (Part 2 of the Appendix), which generates the text file OPTION.DEF specifying the physical coordinate of each I/O signal and power pad in the customer option. This information is used in appending the I/O signal names to their respective pads in the physical data base of the customer option. The input files to program DEFGEN are OPTION.sub.-- CHIP.IO, OPTION.sub.-- APIN.S50, CHIP.DEF, and the skeleton library files 34.
Step 212 is executed by the program FIXGENNET (Part 3 of the Appendix), which creates an output file OPTION.sub.-- GEN.LIS that is similar to file OPTION.sub.-- GENNET.LIS modified by extracting two specific macro types that are not relevant to the netlist generating step 32. These macro types, IN00X2/3 and OUT00X2/3, physically represent only a piece of metal layer. The input files to program FIXGENNET are OPTION.sub.-- CHIP.IO, OPTION.sub.-- GENNET.LIS, and the skeleton library files 34.
Step 214 is executed by the program NEWGENNET. Note that a different NEWGENNET program is used for each type of array, although the functions performed by the programs are identical. Programs NEWGENNET.sub.-- 4K, NEWGENNET.sub.-- 13K, NEWGENNET.sub.-- 14K, and NEWGENNET.sub.-- 14KRAM are used for 4K arrays, 1.3K arrays, 14K arrays, and 14K arrays with RAM respectively, and are listed in Parts 14, 15, 16 and 17 respectively of the Appendix. Program NEWGENNET generates a complete logic netlist of the customer option suitable for the circuit level netlist generating system by adding the I/O connectivity netlist information and the bias driver connectivity information for the customer option to the file OPTION.sub.-- GEN.LIS. The input files to program NEWGENNET are OPTION.sub.-- GEN.LIS, OPTION.sub.-- CHIP.IO, OPTION.sub.-- DES.BOV, and the skeleton library files 34.
Step 216 is executed by program GENBIO (Part 4 of the Appendix), which defines for each macro instance the names of the utilized inputs, the names of the utilized outputs, the base power of the macro instance, the output power of each of the utilized outputs, and the names of the inputs and outputs that are not utilized. This information is stored in file OPTION.sub.-- INST.DAT. Another output file called OPTION.sub.-- LAY.BOV containing external slave bias identification and overlay utilization information is generated also. The input files to the program GENBIO are OPTION.sub.-- NGEN.LIS and the skeleton library files 34.
Step 218 is executed by program GENMDL. Note that a different GENMDL program is used for each type of array, although the functions performed by the programs are identical. Program GENMDL 4K is used for 4K and 1.3K arrays, while program GENMDL.14K is used for 14K arrays and 14K arrays with RAM. Programs GENMDL.sub.-- 4K AND GENMDL.sub.-- 14K are listed in Parts 5 and 6 respectively of the Appendix. Program GENMDL generates a MDL circuit level netlist for every macrocell instance in the customer option by providing the appropriate base skeleton file and appending the appropriate I/O skeleton files for each macrocell instance, as specified by the macrocell instance. These netlists are collected in file OPTION.sub.-- MAC.MDL. Program GENMDL also generates file OPTION.sub.-- IPIN.DAT containing I/O pin information suitable for determining the connectivity between the various macrocell instances in the customer option. The input files for program GENMDL are OPTION.sub.-- INST.DAT, OPTION.sub.-- NGEN.LIS, OPTION.sub.-- LAY.BOV and the skeleton library files 34.
Step 220 is executed by program MERGEMDL. Note that a different MERGEMDL program is used for each type of array, although the functions performed by the programs are identical. Programs MERGEMDL.sub.-- 4K, MERGEMDL.sub.-- 13K, MERGEMDL.sub.-- 14K, and MERGEMDL.sub.-- 14KRAM are used for 4K arrays, 1.3K arrays, 14K arrays, and 14K arrays with RAM respectively, and are listed in Parts 10, 11, 12 and 13 respectively of the Appendix. Program MERGEMDL completes the circuit level MDL netlist by adding connectivity information to the collection of MDL circuit level netlists for every macrocell instance in the customer option. A working file called OPTION.sub.-- INET.MDL specifying the signal connectivity between macro instances is created. The complete netlist, which now contains MDL netlists for each instance and specifies the connectivity between the various instances, is further supplemented by subcircuit MDL files, which are merely appended from file SUBCKT.MDL, the subcircuit library 36. The resulting file is OPTION.MDL. The input files for program MERGEMDL are OPTION.sub.-- IPIN.DAT, OPTION.sub.-- MAC.MDL, SUBCKT.MDL, and OPTION.sub.-- NGEN.LIS.
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