Source: https://patents.google.com/patent/US5898883A/en
Timestamp: 2018-07-18 15:37:37
Document Index: 441355771

Matched Legal Cases: ['art 615', 'art 616', 'art 616', 'art 615', 'art 615', 'art 615', 'art 616', 'art 616']

US5898883A - Memory access mechanism for a parallel processing computer system with distributed shared memory - Google Patents
Memory access mechanism for a parallel processing computer system with distributed shared memory Download PDF
US5898883A
US5898883A US08368618 US36861895A US5898883A US 5898883 A US5898883 A US 5898883A US 08368618 US08368618 US 08368618 US 36861895 A US36861895 A US 36861895A US 5898883 A US5898883 A US 5898883A
US08368618
Here, the description will be made of the allocation of the main memory 614 in PU0 of the address map 601. This main memory 614 is accessed by the processor whose physical processor number is 0, that is physical PU0, among the eight processors described before constituting the group. Assume an address reference in the physical PU0, and assume that the logical PU number 0 is correlated to the physical PU number 0 in the processor number conversion table 117 in the physical PU0. The main memory 614 in the physical PU0 is logically divided into a part 615 which is allocated to the Local memory area in the physical PU0 and a part 616 which is allocated to the Global memory area existing in the logical PU0. As to the address to the main memory 614, with the address Adr. A as boundary, the addresses from (0) × to (Adr. A -1) are defined as the part 616 allocated to the Global memory area existing in the logical PU0, while the addresses from Adr. A to the maximum address (Adr. max) are defined as the part 615 allocated to the Local memory area. To the main memory part 615, the addresses starting with the head address of the Local memory area 605 and corresponding to the capacity of the main memory part 615 are exclusively allocated to physical PU0. Similarly, to the main memory part 616, the addresses starting with the head address of the Local memory area 606 and corresponding to the capacity of the main memory part 616 are exclusively allocated to physical PU0.
1. A memory access mechanism for a parallel processing distributed/shared memory computer system of a plurality of processors, each having memory, comprising:
a fixed length memory access request address having a variable-length Global/Local allocation field, so that when the field is locally set a remainder of the address is a local memory area address, and so that when the Global/Local allocation field is set globally the remainder of the address is a variable-length processor number field for specifying one of processors and a variable length offset field for specifying a Global address on a memory of a processor specified by the processor number field; and
a memory access interface for each of the processors, the memory access interface having means for identifying content of the Global/Local allocation field, means for extracting content of the processor number field, means for extracting content of the offset field, means for starting access to a local memory area when the means for identifying indicates locally set and when the means for identifying indicates set globally and the content of the processor number field indicates a local processor, and means for starting access to memory of another processor other than the local processor by an address of the offset field when the means for identifying indicates set globally and the processor number field indicates the another processor.
2. A memory access mechanism according to claim 1, wherein said means for identifying comprises a mask register for drawing out a part of the memory access request address by use of a mask;
said means for extracting content of the processor number field comprises a register for showing bit width of the offset field;
said means for extracting content of the offset field comprises a mask register for drawing out a part of the memory access request address by use of a mask; and
wherein content of each of said mask registers and the content of the register for showing bit width of the offset field, each being rewrittable in accordance with an instruction issued by one of the processors.
3. A memory access mechanism according to claim 1, wherein content of said processor number field is a logical processor number;
further including means for converting a logical processor number of said processor number field into a physical processor number; and
wherein each of said means for starting uses said physical processor number.
4. A memory access mechanism according to claim 3, wherein said means for identifying comprises a mask register for drawing out a part of the memory access request address by use of a mask;
5. A memory access mechanism according to claim 2, wherein said means for starting access to a local memory area comprises a base address register for holding address addition information for converting an offset head address of said memory access request address to a head address of the local memory area, and the content of said base address register being rewrittable in accordance with an instruction by a processor.
6. A parallel processing computer system, with distributed/shared memory, comprising:
a plurality of arithmetic processors;
a plurality of local memories, each locally coupled to a respective one of said processors and being divided into a local memory area and a global memory area;
a network interconnecting the processors for parallel processing as a parallel processing computer system;
each of the processors accessing the local memory area in the locally coupled local memory and the global memory area in each of the local memories of all others of said processors, to provide the parallel processing computer system with distributed/shared memory; and
each of said processors including a memory access interface receiving, storing and processing a fixed bit length memory access address having a variable length processor number field and a variable length memory address field.
7. A parallel processing computer system according to claim 6, further including a processor number converting unit for converting a logical processor number in the variable length processor number field into a physical processor number.
10. A parallel processing computer system according to claim 9, wherein said some of said processors have a memory map with addressable memory size corresponding to the fixed bit length of said memory access address; and
wherein said memory access interface of each processor dynamically allocates the global memory area within a locally coupled local memory so that maximum global memory area corresponds in size to maximum memory area that may be addressed according to the maximum bit length of the offset address.
11. A parallel processing computer system according to claim 9, wherein said memory access address includes a global/local identification field, for holding a one bit length value identifying the memory address field as holding a local or a global address;
wherein each local memory includes one-half allocation to said local memory area addressable by one value of the global/local identification field, and an other half allocation being said global memory area addressable by another value of said global/local allocation field; and
said global memory area being equally divided into memory global allocations, with a number of divisions being equal to a number of processors within the global group and the memory global allocations being respectively addressed by a value in the processor number field, whereby the maximum size of each memory global allocation is dynamically set to a maximum size depending upon the number of dynamically set processors within the global group.
12. A parallel processing computer system according to claim 11, wherein said local memory area is divided between an input/output allocation and a maximum local memory allocation, whereby the local processor globally addresses a divided allocation of the global memory area allocated to the local and other processors of the global group, and locally addresses local memory area of the local memory allocation and the input/output allocation.
14. A parallel processing computer system according to claim 13, wherein said some of said processors have a memory map with addressable memory size corresponding to the fixed bit length of said memory access address; and
wherein said memory access interface of each processor dynamically allocates the global memory area within the locally coupled local memory so that maximum global memory area corresponds in size to maximum memory area that may be addressed according to the maximum bit length of the offset address.
15. A parallel processing computer system according to claim 14, wherein each memory map includes global memory areas for only the some of said processors of said global group and not for others of said processors.
19. A parallel processing computer system according to claim 18, wherein said local memory access unit includes an offset address register for receiving an offset address from said memory address field, a software resettable base address register, an addition unit for adding output of the offset address register and output of the base address register to produce a result, and a result register for holding the result; and
said memory access interface further including an input/output access unit for receiving the result from said result register, and sending the result to said local memory area.
20. A parallel processing computer system according to claim 16, including means for software setting said global/local identification field to a variable length, including both a zero bit length and a one bit length.
23. A parallel processing computer system according to claim 22, wherein at least some of said processors have a memory map with addressable memory size corresponding to the fixed bit length of said memory access address; and
wherein said memory access interface of each processor dynamically allocates the global memory area within locally coupled local memory so that maximum global memory area corresponds in size to maximum memory area that may be addressed according to the maximum bit length of the offset address.
24. A parallel processing computer system according to claim 6, wherein said processor number field is a physical processor number field.
US08368618 1994-01-25 1995-01-04 Memory access mechanism for a parallel processing computer system with distributed shared memory Expired - Fee Related US5898883A (en)
JP2373894A JP3687990B2 (en) 1994-01-25 1994-01-25 Memory access mechanism
JP6-023738 1994-01-25
US5898883A true US5898883A (en) 1999-04-27
ID=12118657
US08368618 Expired - Fee Related US5898883A (en) 1994-01-25 1995-01-04 Memory access mechanism for a parallel processing computer system with distributed shared memory
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