Source: http://www.google.com/patents/US8145809?dq=5,884,272
Timestamp: 2014-12-27 09:49:37
Document Index: 88843496

Matched Legal Cases: ['art 500', 'art 500', 'arts 500', 'art 500', 'art 500', 'art 500']

Patent US8145809 - Busy detection logic for asynchronous communication port - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system...http://www.google.com/patents/US8145809?utm_source=gb-gplus-sharePatent US8145809 - Busy detection logic for asynchronous communication portAdvanced Patent SearchPublication numberUS8145809 B1Publication typeGrantApplication numberUS 12/044,831Publication dateMar 27, 2012Filing dateMar 7, 2008Priority dateMar 9, 2007Also published asUS8370543Publication number044831, 12044831, US 8145809 B1, US 8145809B1, US-B1-8145809, US8145809 B1, US8145809B1InventorsSyed Babar Raza, Pradeep BajpaiOriginal AssigneeCypress Semiconductor CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (87), Non-Patent Citations (67), Classifications (12), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetBusy detection logic for asynchronous communication portUS 8145809 B1Abstract An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.
RELATED U.S. APPLICATIONS This application claims the benefit of and priority to copending provisional patent application Ser. No. 60/906,042, entitled �Implementation of Logical End-Points in USB Device,� with filing date Mar. 9, 2007, and hereby incorporated by reference in its entirety.
FIELD OF INVENTION Embodiments of the present invention relate to communication synchronization.
BACKGROUND OF THE INVENTION Clock synchronization devices attempt to synchronize communication between two devices in different or independent clock domains or time domains. For example, the communication between a processor in a fast clock domain and a memory device in a slow clock domain may require synchronization in order for the devices to communicate (e.g., for the processor to access data stored in the memory device). Memory access synchronization may require that the memory be aware of which address or resource is being accessed by a processor.
SUMMARY OF THE INVENTION Accordingly, embodiments of the present invention are directed to a system and method for synchronizing device resource access information between independent time domains. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of the device issuing access requests. Embodiments of the present invention synchronize the device access information without restricting the pulse width of a read/write signal or requiring a high speed clock.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A-1B show block diagrams of a conventional synchronization designs.
Example System FIGS. 2-4 illustrate example components used by various embodiments of the present invention. Although specific components are disclosed in systems 200, 212A and 400 it should be appreciated that such components are examples. That is, embodiments of the present invention are well suited to having various other components or variations of the components recited in systems 200, 212A and 400. It is appreciated that the components in systems 200, 212A and 400 may operate with other components than those presented, and that not all of the components of systems 200, 212A and 400 may be required to achieve the goals of systems 200, 212A and 400.
Example Operations With reference to FIG. 5, exemplary flowchart 500 each illustrates example blocks used by various embodiments of the present invention. Flowchart 500 includes processes that, in various embodiments, are carried out by a processor under the control of computer-readable and computer-executable instructions. Although specific blocks are disclosed in flowcharts 500, such blocks are examples. That is, embodiments are well suited to performing various other blocks or variations of the blocks recited in flowchart 500. It is appreciated that the blocks in flowchart 500 may be performed in an order different than presented, and that not all of the blocks in flowchart 500 may be performed.
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No. 09/443,062 dated Aug. 8, 2000.67USPTO U.S. Appl. No. 12/044,862: "Arbitration Method for Programmable Multiple Clock Domain Bi-Directional Interface," Gupta et al., filed on Mar. 7, 2008; 33 pages.Classifications U.S. Classification710/58, 713/400, 710/52, 710/36International ClassificationG06F3/00, G06F1/12Cooperative ClassificationG06F1/04, G11C7/00, G06F13/00, G06F5/00, G11C7/109, G11C7/1075Legal EventsDateCodeEventDescriptionJun 2, 2008ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RAZA, SYED BABAR;BAJPAI, PRADEEP;REEL/FRAME:021028/0776Effective date: 20080528Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIARotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google