Source: http://www.google.com/patents/US7800401?dq=5708422
Timestamp: 2014-10-23 21:05:44
Document Index: 443786233

Matched Legal Cases: ['Application No. 200410033018', 'Application No. 200410033018', 'Application No. 04250564', 'Application No. 04250564', 'Application No. 04250564', 'Application No. 2004']

Patent US7800401 - Fracturable lookup table and logic element - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers...http://www.google.com/patents/US7800401?utm_source=gb-gplus-sharePatent US7800401 - Fracturable lookup table and logic elementAdvanced Patent SearchPublication numberUS7800401 B1Publication typeGrantApplication numberUS 11/841,727Publication dateSep 21, 2010Filing dateAug 20, 2007Priority dateFeb 10, 2003Fee statusPaidAlso published asUS8217678Publication number11841727, 841727, US 7800401 B1, US 7800401B1, US-B1-7800401, US7800401 B1, US7800401B1InventorsDavid Lewis, Bruce Pedersen, Sinan Kaptanoglu, Andy LeeOriginal AssigneeAltera CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (59), Non-Patent Citations (28), Classifications (5), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetFracturable lookup table and logic elementUS 7800401 B1Abstract A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
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Kaptanoglu et al., "A new high density and very low cost reprogrammable FPGA architecture", FPGA 99 Monterey Ca, pp. 3-12, 1999.Classifications U.S. Classification326/38, 326/41International ClassificationH03K19/177Cooperative ClassificationH03K19/177European ClassificationH03K19/177Legal EventsDateCodeEventDescriptionFeb 25, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google