Source: http://www.google.com/patents/US6356504?dq=6031454
Timestamp: 2016-10-01 10:47:28
Document Index: 339396874

Matched Legal Cases: ['art 122', 'art 122', 'art 122', 'art 124', 'art 126', 'art 122', 'art 122', 'arts 124']

Patent US6356504 - Address generating and decoding circuit for use in a burst-type and high ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA burst-type random access memory device according to the present invention includes an address generator that receives an initial address to generate a sequence of burst addresses according to either one of a single data rate mode and a double data rate mode. A decoding circuit decodes the burst address...http://www.google.com/patents/US6356504?utm_source=gb-gplus-sharePatent US6356504 - Address generating and decoding circuit for use in a burst-type and high-speed random access memory device which has a single data rate and a double data rate schemeAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6356504 B1Publication typeGrantApplication numberUS 09/653,442Publication dateMar 12, 2002Filing dateSep 1, 2000Priority dateSep 2, 1999Fee statusPaidPublication number09653442, 653442, US 6356504 B1, US 6356504B1, US-B1-6356504, US6356504 B1, US6356504B1InventorsEun-cheol KimOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (20), Classifications (18), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetAddress generating and decoding circuit for use in a burst-type and high-speed random access memory device which has a single data rate and a double data rate scheme
Video RAM (random access memory), synchronous RAM and burst RAM each require a sequence of internally generated addresses (referred to as “an address burst”, “an address sequence” or “a serial address”) to support a high-speed data access operation. Typically the start address of a particular address burst is provided from an external source (e.g. a host computer or a processor), and as subsequent clock signals arrive at the address generator, the following addresses in the burst are sequentially generated for the duration of the burst.
A burst-type random access memory device, for example, a synchronous static RAM (hereinafter, referred to as “SRAM”) has a sequential burst mode (or a linear burst mode) and an interleaved burst mode. Furthermore, the SRAM device operates at a single data rate (SDR) mode, and at a double data rate (DDR) mode. Tables showing the relationship between an initial address and a sequence of burst addresses according to a burst operation of SDR/DDR mode are illustrated in FIGS. 9A-9D.
The address generator 120 is driven by a first clock signal φ1 and a second clock signal φ2, and receives the initial address bit signals XA0 and XA1. And then, the address generator 120 generates a sequence of burst addresses ‘B1B0’, illustrated in FIGS. 9A-9D, according to control signals MODE and {overscore (DDR)}. The control signal MODE indicates a sequential mode or an interleaved mode, and the control signal {overscore (DDR)} indicates the SDR mode or the DDR mode. An operation of the address generator 120 will be more fully described below.
The burst address ‘B1B0’ thus generated is transferred to the pre-decoder 130. The pre-decoder 130 decodes the burst address ‘B1B0’ from the address generator 120 according to the control signals MODE and {overscore (DDR)}.
In the case that a random access memory device performs a burst operation of the SDR mode, there is activated only one of decoded signals D3-D0 generated as a result of decoding the burst address ‘B1B0’. The decoded signal thus activated is supplied to the decoder 140 with address bit signals Bn-B2, which are outputted from the address buffer 110 in synchronization with the first clock φ1. Then a signal Xi/Yi decoded by the decoder is used to select a word line or bit lines in either one of bank BANK1 and BANK2.
The carry generating part 122 illustrated in FIG. 2 outputs the lower address bit signal XA0 as the carry signal CARRY at a low-to-high transition of the first clock signal φ1 in the sequential burst mode (as seen in FIG. 7, at a first period of the burst mode). During the interleaved burst mode, the carry generating part 122 sets the carry signal CARRY to logically ‘0’ at a low-to-high transition of the clock signal φ1 regardless of a logic state of the lower address bit signal XA0. And the carry generating part 122 inverts a signal CARRY outputted at a previous period whenever the second clock signal φ2 transitions from a logic low level to a logic high level (as seen in FIG. 7, in a second period, a third period and a fourth period of the burst mode), and outputs the inverted signal as the carry signal CARRY.
Referring to FIG. 4, the pre-decoder 130 of the present invention receives a burst address ‘B1B0’ generated at the address generator illustrated in FIG. 1, and decodes the received burst address ‘B1B0’ according to an interleaved/sequential burst operation of the SDR or DDR mode. The pre-decoder 130 consists of four inverters INV10-INV13, four AND gates G5-G8 and four combination circuits 131-134 connected as illustrated in FIG. 4.
Assume that the burst-type SRAM device performs an interleaved burst operation of the SDR mode. Under this condition, the pre-decoder 130 decodes a burst address ‘B1B0’ generated at the address generator 120 to activate one of decoded signals D0-D3 at a logic high level and to inactivate remaining decoded signals at a logic low level. For example, when the burst address ‘B1B0’ is ‘01’, an output C1 of the AND gate G6 becomes high, and outputs of other AND gates G5, G7 and G8 become low. Since the SRAM device performs an interleaved burst operation of the SDR mode, the control signal MODE is high and the control signal {overscore (DDR)} is high. According to the above-mentioned condition, output signals D0, D2 and D3 of the first, third and fourth combination circuits 131, 133 and 134 become low, respectively, and an output signal D1 of the second combination circuit 132 becomes high.
Assume that the burst-type SRAM device performs an interleaved burst operation of the DDR mode. Under this condition, the pre-decoder 130 decodes a burst address ‘B1B0’ generated from the address generator 120 to activate two ones of decoded signals D0-D3 at a logic high level and to inactivate the others at a logic low level. For example, when the burst address ‘B1B0’ is ‘01’, an output signal C1 of the AND gate G6 becomes high, and output signals C0, C2 and C3 of other AND gates G5, G7 and G8 become low. Since the SRAM device performs the interleaved burst operation of the DDR mode, the control signal MODE is at a logic high level, and the control signal {overscore (DDR)} is at a logic low level. According to the above-described condition, the output signals D2 and D3 of the third and fourth combination circuits 133 and 134 become low, respectively, and the output signals D0 and D1 of the first and second combination circuits 131 and 132 become high, respectively.
Assume that the burst-type SRAM device operates in the SDR sequential burst mode. Under this condition, the control signal MODE has a logic low level, and the control signal {overscore (DDR)} has a logic high level. When a system clock XCLK transitions from a low level to a high level, an external address XAn-XA0 is provided to the SRAM device. At this time, an initial address ‘XA1XA0’ of the external address has one of ‘00’, ‘01’, ‘10’ and ‘11’. Assuming that the initial address ‘XA1XA0’ is ‘01’, the operation of the address generating and decoding circuit with regard to the SDR sequential burst mode will be described.
At a low-to-high transition of the clock signal φ1, the lower burst address generating part 124 outputs the lower address bit signal XA0 of logically ‘1’ through the transmission gate 127 and the inverters INV8 and INV3 as the lower burst address bit signal B0. Similarly, the upper burst address generating part 126 outputs the upper address bit signal XA1 of logically ‘0’ as the upper burst address bit signal B1. Therefore, in a first period of the SDR sequential burst mode, the externally provided initial address ‘XA1XA0’ of ‘01’ is directly output as the burst address ‘B1B0’. That is, the burst address ‘B1B0’ of the first period is ‘01’.
The burst address ‘B1B0’ of ‘01’ thus generated is provided to the pre-decoder 130. As described above, the pre-decoder 130 responds to the burst address ‘B1B0’ of ‘01’, the control signal MODE of a logic low level and the control signal {overscore (DDR)} of a logic high level to activate one (e.g., D1) of decoded signals D0-D3 at a logic high level. After this, the decoder 140 responds to remaining address bit signals Bn-B2 outputted from the address buffer 110 and the activated decoded signal D1 by the pre-decoder 130 to activate a word line (or bit lines) of either one of the banks BANK1 and BANK2.
Then, in a second period of the SDR sequential burst mode, as illustrated in FIG. 7, the clock signal φ1 is maintain low, while the clock signal φ2 has a low-to-high transition. The signal of the logic low level, which is maintained in the latch circuit L1 of the register 121, is transferred to the latch circuit L2 through the inverters INV5 and INV7 and the transmission gate 129, the signal of a logic low level maintained in the latch circuit L1 of the register 123 is transferred to the latch circuit L2 through the inverters INV5 and INV7 and the transmission gate 129, and the signal of a logic high level held in the latch circuit L1 of the register 125 is transferred to the latch circuit L2 through the inverters INV5 and INV7 and the transmission gate 129. As a result, the carry signal CARRY, the lower burst address bit signal B0 and the upper burst address bit signal B1 goes low, low and high, respectively. That is, the burst address ‘B1B0’ of ‘10’ is generated in the second period of the SDR sequential burst mode.
The burst address ‘B1B0’ of ‘10’ thus generated is provided to the pre-decoder 130, and the pre-decoder 130 responds to the burst address ‘B1B0’ of ‘10’, the control signal MODE of a logic low level and the control signal {overscore (DDR)} of a logic high level to then activate one D2 of decoded signals D0-D3 at a logic high level. After this, the decoder 140 responds to remaining address bit signals Bn-B2 from the address buffer 110 and the decoded signal D2 activated by the pre-decoder 130, and then activates a word line or bit lines in either one of the banks BANK1 and BANK2.
Then, in the third period of the SDR sequential burst mode, as illustrated in FIG. 7, the clock signal φ1 is maintained low, while the clock signal φ2 transitions from a logic low level to a logic high level. Thus, a signal of a logic high level held in the latch L1 of the register 121 is transferred to the latch L2 through the inverters INV5 and INV7 and the transmission gate 129, a signal of a logic high level held in the latch L1 of the register 123 is transferred to the latch L2 through the inverters INV5 and INV7 and the transmission gate 129, and a signal of a logic high level held in the latch L1 of the register 125 is transferred to the latch L2 through the inverters INV5 and INV7 and the transmission gate 129. As a result, the carry signal CARRY, the lower burst address bit signal B0 and the upper burst address bit signal B1 go high. That is, the burst address ‘B1B0’ of ‘11’, is generated in the third period of the SDR sequential burst mode, as illustrated in FIG. 7.
Similarly to the previous period, the burst address ‘B1B0’ of ‘11’ is provided to the pre-decoder 130. The pre-decoder 130 responds to the burst address ‘B1B0’ of ‘11’, the control signal MODE of a logic low level and the control signal of a logic high level, to thus activate signal D3 of decoded signals D0-D3. After this, the decoder 140 responds to remaining address bit signals Bn-B2 and the decoded signal D3 activated by the pre-decoder 130 to activate a word line or bit lines of a bank BANK1 or BANK2.
Then, in the fourth period of the SDR sequential burst mode, the clock signal φ1 is maintained low, while the clock signal φ2 has a low-to-high transition. Thus, a signal of a logic low level held in the latch L1 of the register 121 is transferred to the latch L2 through the inverters INV5 and INV7 and the transmission gate 129, a signal of a logic low level held in the latch L1 of the register 123 is transferred to the latch L2 through the inverters INV5 and INV7 and the transmission gate 129, and a signal of a logic low level held in the latch L1 of the register 125 is transferred to the latch L2 through the inverters INV5 and INV7 and the transmission gate 129. As a result, the carry signal CARRY, the lower burst address bit signal B0 and the upper burst address bit signal B1 all go low. That is, the burst address ‘B1B0’ of ‘00’ is generated in the fourth period of the SDR sequential burst mode, as illustrated in FIG. 7. The burst address ‘B1B0’ of ‘00’ thus generated is provided to the predecoder 130. The pre-decoder 130 responds to the burst address ‘B1B0’ of ‘00’, the control signal MODE of a logic low level and the control signal {overscore (DDR)} of a logic high level to then activate one D0 of decoded signals D0-D3 at a logic high level.
As described above, if the initial address ‘XA1XA0’ of ‘01’ is provided from the exterior, the address generator 120 of the present invention sequentially generates a sequence of internal burst addresses ‘B1B0’: ‘01’, ‘10’, ‘11’ and 00’. Furthermore, since a burst address generated by the address generator 120 is directly transferred to the pre-decoder 130 when the clock signal φ1 or φ2 transitions from a logic low level to a logic high level, an overall decoding speed is improved. Similarly, the address generating and decoding operation according to an SDR interleaved burst mode is performed identically or similarly to the above-described SDR sequential burst mode, and the description thereof is thus omitted.
The burst-type SRAM device operates a DDR interleaved burst mode, the operation of the address generating and decoding circuit according to the present invention will be more fully described with reference to the accompanying drawings. As illustrated in the above-described FIG. 9D, in the DDR burst interleaved burst mode, the control signal indicating a sequential burst mode or an interleaved burst mode goes high, and the control signal indicating the SDR mode or the DDR mode goes low. Assume that an initial address ‘XA1XA0’ of ‘01’ is provided from the exterior.
In particular, in the carry generating part 122, since the control signal MODE is high and the lower address bit signal XA0 is high, an output signal of the NOR gate G1 goes low. Therefore, the carry signal of a logic low level is outputted from the carry generating part 122 through the latch L1 and the inverter INV2. Similarly, the lower and upper burst address generating parts 124 and 126 output the lower burst address bit signal B0 of logically ‘1’ and the upper burst address bit signal B1 of logically ‘0’, respectively. The burst address ‘B1B0’ of ‘01’ generated from the address generator 120 is transferred to the pre-decoder 130 when the clock signal φ1 transitions from a logic low level to a logic high level (that is, a first period of the DDR interleaved burst mode).
The burst address ‘B1B0’ of ‘01’ thus generated is decoded by the pre-decoder 130 in FIG. 4 according to the control signals MODE and {overscore (DDR)}, so that decoded signals D0 and D1 are activated high. The decoder 140 responds to the decoded signals D0 and D1 and address bit signals Bn-B2 from the address buffer 110 to select a word line (or bit lines) of the respective banks BANK1 and BANK2 at the same time. After this, data is read from the respective banks BANK1 and BANK2 according to the well-known read manner. One of the two read data is outputted in a first logic state period of the external clock signal XCLK, and the other thereof is outputted in a second logic state period of the external clock signal XCLK.
Then, in a second period of the DDR interleaved burst mode, the clock signal φ1 is maintained low, while the clock signal φ2 has a low-to-high transition, as illustrated in FIG. 8. Thus, a signal of a logic high level held in the latch L1 of the register 121 is transferred to the latch L2 through the inverters INV5 and INV7 and the transmission gate 129, a signal of a logic high level held in the latch L1 of the register 123 is transferred to the latch L2 through the inverters INV5 and INV7 and the transmission gate 129, and a signal of a logic high level held in the latch L1 of the register 125 is transferred to the latch L2 through the inverters INV5 and INV7 and the transmission gate 129. As a result, signals CARRY, B0 and B1 go high. That is, the burst address ‘B1B0’ of ‘11’ is generated in the second period of the DDR interleaved burst mode, as illustrated in FIG. 8.
The burst address ‘B1B0’ of ‘11’ thus generated is decoded by the pre-decoder 130 in FIG. 4 according to logic states of the control signals MODE and {overscore (DDR)}, so that two decoded signals D2 and D3 are simultaneously activated high. The decoder 140 responds to the activated signals D2 and D3 and address bit signals Bn-B2 from the address buffer 110 to select a word line (or bit lines) of each of the banks BANK1 and BANK2. After this, data is read out from the banks BANK1 and BANK2 according to the well-known read manner. One of the two read data is outputted in a first logic state period of the clock XCLK, and the other thereof is outputted in a second state period of the clock XCLK.
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