Source: http://www.google.com/patents/US5241377?dq=7,550,386
Timestamp: 2014-03-14 06:26:25
Document Index: 651565046

Matched Legal Cases: ['art 2', 'art 1', 'art 23', 'art 23', 'art 23', 'art 23', 'art 23', 'art 23', 'art 23']

Patent US5241377 - Compact imager including a plurality of photodiode arrays - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn image sensor includes a plurality of photodiode arrays, each array including a plurality of photodiodes, the arrays being aligned in parallel and closely arranged, at least two charge transfer devices disposed parallel to and on opposite sides of the photodiode arrays. With this arrangement, the clearance...http://www.google.com/patents/US5241377?utm_source=gb-gplus-sharePatent US5241377 - Compact imager including a plurality of photodiode arraysAdvanced Patent SearchPublication numberUS5241377 APublication typeGrantApplication numberUS 07/793,142Publication dateAug 31, 1993Filing dateNov 18, 1991Priority dateJan 11, 1991Fee statusPaidPublication number07793142, 793142, US 5241377 A, US 5241377A, US-A-5241377, US5241377 A, US5241377AInventorsOsamu KanedaOriginal AssigneeMitsubishi Denki Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (13), Classifications (16), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetCompact imager including a plurality of photodiode arraysUS 5241377 AAbstract An image sensor includes a plurality of photodiode arrays, each array including a plurality of photodiodes, the arrays being aligned in parallel and closely arranged, at least two charge transfer devices disposed parallel to and on opposite sides of the photodiode arrays. With this arrangement, the clearance between the respective photodiode arrays can be reduced and the charges generated by the photodiodes having shallower potential wells can be completely transferred at high speed.
What is claimed is: 1. An image sensor comprising:a plurality of photodiode arrays, each array comprising a plurality of photodiodes for generating electrical charges in response to incident light, each photodiode having a potential well for storing electrical charges, said arrays being aligned along a main scanning direction parallel to each other and closely spaced to each other along a sub-scanning direction perpendicular to the main scanning direction; and first and second charge transfer elements disposed parallel to said photodiode arrays with said photodiode arrays therebetween for serially transferring electrical charges generated by said arrays from the potential wells and for outputting charges generated by said photodiodes in two adjacent photodiode arrays of said plurality of photodiode arrays, the photodiodes of a first of said two adjacent photodiode arrays having potentials lower in magnitude than the potentials of the photodiodes of the second of said two adjacent photodiode arrays after transfer of electrical charges by said first and second charge transfer elements, the charges generated by the second photodiode array being transferred in parallel independently of the transfer of charges generated by the first photodiode array. 2. The image sensor of claim 1 wherein a plurality of photodiodes including photodiodes selected from each of said plurality of photodiode arrays comprises one picture element.
FIELD OF THE INVENTION The present invention relates to an image sensor which converts optical information into electric signals. More particularly it relates to reduction of the chip size of a linear image sensor comprising three photodiode arrays aligned adjacent to one another on the same chip in a subscanning direction.
BACKGROUND OF THE INVENTION A linear image sensor is usually constituted by a single column of photo sensors such as photodiodes and it carries out only transverse scanning while vertical scanning is carried out mechanically or optically. The linear image sensor has been generally used for reading in a facsimile machine or an optical character recorder (OCR).
In this prior art device, since the image sensor moves in the sub-scanning direction 10a to read the copy, the differences in reading positions between B and G and between B and R (clearances L.sub.1 and L.sub.2 in FIG. 14) should be compensated with time. For this reason, line memories 7 having a number of stages corresponding to the clearances L.sub.1 and L.sub.2 are provided in the G transfer part 2 and the R transfer part 1, respectively, whereby signal outputs obtained by the reading the same portion of the copy by the respective R, G, and B sensors can be output from the output amplifier 9.
SUMMARY OF THE INVENTION It is an object of the present invention to provide an image sensor that requires no memory or only a small memory, compensating for the clearances between the respective photodiode arrays, thereby producing a small sized chip.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view illustrating the construction of an image sensor in accordance with a first embodiment of the present invention;
FIGS. 4(a) and 4(b) are sectional views taken along a line A-B of FIG. 3, schematically illustrating the potential levels in the substrate at time t.sub.0 and t.sub.1, respectively;
FIGS. 5(a) and 5(b) are sectional views taken along a line A-B of FIG. 3, schematically illustrating the potential levels in the substrate at time t.sub.2 and t.sub.3, respectively;
FIGS. 6(a) and 6(b) are sectional views taken along a line A-B of FIG. 3, schematically illustrating the potential levels in the substrate at time t.sub.4 and t.sub.5, respectively;
FIGS. 7(a) to 7(c) are sectional views taken along a line C-D of FIG. 3, schematically illustrating the potential levels below electrodes H.sub.1 and H.sub.2, respectively;
FIG. 2 is an enlarged view of a part of FIG. 1. In FIG. 2, the same reference numerals as those in FIG. 1 designate the same parts. Reference numeral 13 designates a B CCD channel and reference numeral 14 designates a G CCD channel. A gate pairs 17 including an H.sub.1 and H.sub.2 gate of the horizontal transfer CCD are produced on the B and G CCD channels 13 and 14.
FIGS. 4(a) to 6(b) are diagrams schematically illustrating the potential along a cross-section taken along a line A-B of FIG. 3 and FIGS. 7(a)-7(c) are diagram schematically illustrating the potential along a cross section taken along a line C-D of FIG. 3. In FIGS. 4(a) to 6(b), reference numeral 11 designates a B photodiode the B photodiode array 6 and reference numeral 12 designates a G photodiode of the G photodiode array 5. The potential well of the B photodiode 11 is shallower than that of the G photodiode 12. An H.sub.2 gate 17a of the horizontal transfer CCD is produced on the B CCD channel 13 and an H.sub.1 gate 17b of the horizontal transfer CCD is produced on the G CCD channel 14. The image sensor of this embodiment is produced on the substrate 20 whose potential level is represented by numeral 22. A signal charge 19a is detected at the B photodiode 11 and a signal charge 19b is detected at the G photodiode 12.
A description is given of the potential changes and the transition of G and B signal charges at times t.sub.O to t.sub.5 in accordance with the time chart of FIG. 8.
At time t.sub.0, the potentials of the barrier transfer gate (BTG) 15, the transfer gate (TG) 16a, the parallel transfer gate (PTG) 18, the H.sub.2 gate 17a on the B CCD channel 13, and the H.sub.1 gate 17b on the G CCD channel 14 are at low level and the signal charges 19a and 19b are stored in the B photodiode 11 and the G photodiode 12, respectively (FIG. 4(a)).
At time t.sub.1, the potential of the transfer gate 16a is at high level and the G signal charges 19b are transferred and drained into the B CCD channel 13. At this time, since the potential of the H.sub.2 gate 17a of the horizontal transfer CCD in the B CCD channel 13 is at high level, charges are easily stored there (FIG. 4(b)).
At time t.sub.2, the potential of the parallel transfer gate 18 is at high level and the G signal charges are stored in the potential well below the parallel transfer gate 18 (FIG. 5(a)).
At time t.sub.3, the potential of the parallel transfer gate 18 is at low level while that of the H.sub.1 gate 17b of the horizontal transfer CCD in the G CCD channel 14 is at high level, whereby the G signal charges are transferred and drained into the G CCD channel 14 (FIG. 5(b)).
At time t.sub.4, the potential of the parallel transfer gate 18 is at low level while that of the barrier gate 15 and that of the transfer gate 16a are at high level, whereby the B signal charges 19a are transferred and stored in the B CCD channel 13 (FIG. 6(a)). At this time, since the potential of the H.sub.2 gate 17a is at high level, charges are easily stored in the B CCD channel (FIG. 7(a)).
At time t.sub.5, the potential of the H.sub.1 gate 17b in the G CCD channel 14 is at high level while that of the H.sub.2 gate 17a in the B CCD channel 13 is at low level, whereby the B signal charges 19a stored in the potential well below the H.sub.2 gate 17a are transferred into the potential well below the H.sub.1 gate 17b in the B CCD channel 13 (FIGS. 6(b) and 7(b)). In this state, the B signal charges 19a and the G signal charges 19b are stored in the potential well below the H.sub.1 gate of horizontal CCD in the B horizontal transfer CCD channel 13 and in the potential well below the H.sub.1 gate of horizontal CCD in the G horizontal transfer CCD channel 14, respectively.
Thereafter, the potential levels of the H.sub.1 gate and the H.sub.2 gate of horizontal CCD are alternated between high and low and the B signal charges 19a are successively transferred (FIGS. 7(b) and 7(c)). At the same time the G signal charges 19b are successively transferred. Thus, both signal charges are horizontally transferred independently to the output amplifiers 9a and 9b with the same timing.
Since the transition of the G and B signal charges shown in FIGS. 9(a) to 9(f) is the same as that shown in FIGS. 4(a) to 6(b) a, description thereof will be omitted. The following description is mainly directed to the transition of R signal charges. The R signal charges are stored in the R photodiode 4 at time t.sub.0 similarly as the G and B signal charges and they are held in the R photodiode 4 until time t.sub.4 as shown in FIGS. 9(a) to 9(d). When the potential of the transfer gate 16b becomes high level at time t.sub.4, the R signal charges are transferred to the potential well below the H.sub.2 gate of horizontal transfer CCD in the R CCD channel as shown in FIG. 9(e). At time t.sub.5, the potential of H.sub.1 gate 17b becomes high level and the potential of the H.sub.2 gate 17a becomes low level, whereby the R signal charges are transferred to the potential well below the H.sub.2 gate of horizontal CCD, as shown in FIG. 9(f).
Accordingly, at time t.sub.5, the R signal charges detected by the R photodiode 4 are stored in the potential well below the H.sub.1 gate in the R CCD channel 31, the B signal charges detected by the B photodiode 6 are stored in the potential well below the H.sub.1 gate in the B CCD channel 13, and the G signal charges detected by the G photodiode 5 are stored in the potential well below the H.sub.1 gate in the G CCD channel 14. Thereafter, these three kinds of signal charges are horizontally transferred, independently, in parallel with one another while the potential level of the H.sub.1 gate and that of the H.sub.2 gate are alternated between high and low, thereby outputting R, G, and B signals to the output amplifiers 9a, 9b, and 9c, respectively, at the same time.
First of all, a description is given of a case where the G signal charges and the B signal charges are read out alternatingly like G, B, G, B . . . by the GB transfer part 23. FIG. 12(a) is an enlarged view of the GB transfer part 23 of FIG. 11 during the reading operation, FIG. 12(b) is a time chart showing clock pulses applied for operating the sensor, and FIG. 12(c) shows an output signal from the GB transfer part 23. In these figures, reference numeral 24 designates a separation band, reference character G.sub.t designates the position of G signal charges at time t, and the reference character B.sub.t designates the position of B signal charges at time t. As shown in these figures, at time t.sub.1, the potentials of the H.sub.1 gate 17b and the H.sub.2 gate 17a which are horizontal transfer gates of the CCD channel constituting the GB transfer part 23 and the potentials of the transfer gate 16a and the barrier transfer gate 15 are all at low level, and the G and B signal charges are stored in the respective photodiodes.
At time t.sub.2, the potentials of the transfer gate 16a and the H.sub.2 gate 17a are at high level and the G signal charges are transferred into the CCD channel below the H.sub.2 gate 17a. At time t.sub.3, the potential of the H.sub.1 gate 17b is at high level while that of the H.sub.2 gate 17a is at low level, and the G signal charges are transferred into the CCD channel below adjacent H.sub.1 gate. At time t.sub.4, the potential of the H.sub.1 gate 17b is at low level while that of the H.sub.2 gate 17a is at high level, and the G signal charges are transferred into the CCD channel below adjacent H.sub.2 gate. Furthermore, at time t.sub.5, the potential levels of the H.sub.1 gate and the H.sub.2 gate do not change while the potentials of the transfer gate 16a and the parallel transfer gate 15 become high level, whereby the B signal charges stored in the B photodiode are transferred into the CCD channel below the H.sub.2 gate of the G/B transfer part 23. Then, at time t.sub.6, the potential of the H.sub.1 gate is at high level while that of the H.sub.2 gate is at low level, and the B and G signal charges are transferred into the CCD channel below adjacent H.sub.1 gate. Thereafter, the potential levels of the H.sub.1 gate and the H.sub.2 gate are alternated between high and low, and the G and B signal charges are transferred successively, thereby obtaining the signal outputs like G, B, G B . . . as shown in FIG. 12(c).
As shown in these figures, the G signal charges stored in the G photodiode 5 are transferred into the CCD channel below the H.sub.2 gate of the GB transfer part 23' at time t.sub.2 and further transferred into the CCD channel below adjacent H.sub.1 gate at time t.sub.3 and then read out. Meanwhile, the B signal charges stored in the B photodiode 6 are transferred into the GB transfer part 23' at times t.sub.1 ' and t.sub.2 ' after the reading out of the G signal charges and then read out successively. As a result, the output signal as shown in FIG. 13(c) is obtained.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4134031 *Sep 19, 1977Jan 9, 1979Rca CorporationCharge injection devices and arrays and systems including such devicesUS4291390 *Sep 28, 1979Sep 22, 1981Massachusetts Institute Of TechnologyAnalog solid state memoryUS4349743 *Nov 14, 1980Sep 14, 1982Hitachi, Ltd.Solid-state imaging deviceUS4453177 *Mar 25, 1982Jun 5, 1984Thomson-CsfColor television cameraUS4528595 *Sep 13, 1983Jul 9, 1985Thomson-CsfLine transfer imager and television camera including such an imagerUS4553159 *Feb 16, 1983Nov 12, 1985Thomson-BrandtColor television camera comprising a trichrome matrix filterUS4590390 *Jun 24, 1982May 20, 1986Thomson-CsfSolid state photonic detector with charge transfer reader and image-forming target using such a detectorUS4658287 *Feb 29, 1984Apr 14, 1987Fairchild Camera And Instrument Corp.MOS imaging device with monochrome-color compatibility and signal readout versatilityUS4847692 *Jan 26, 1988Jul 11, 1989Fuji Photo Film Co., Ltd.Solid-state image pickup device with CCDS in an interline transfer system and improved charge transfer electrode structure* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5760431 *Sep 5, 1996Jun 2, 1998Massachusetts Institute Of TechnologyMultidirectional transfer charge-coupled deviceUS5784101 *Jan 31, 1995Jul 21, 1998Canon Kabushiki KaishaImage reading apparatus having charge transfer means between the plurality of lines of photoelectric conversion meansUS5946010 *Nov 29, 1996Aug 31, 1999Oki Data CorporationSerial copier, scanner, and printer employing continuous media transportUS5969830 *May 21, 1997Oct 19, 1999Nec CorporationColor linear image sensor and driving method thereforUS5995249 *Jul 30, 1997Nov 30, 1999Canon Kabushiki KaishaImage sensing device and image reading apparatus using the same that reduces the influence of color mixture due to intrapixel transferUS6078685 *Aug 18, 1995Jun 20, 2000Canon Kabushiki KaishaImage reading apparatus for reading a color image by irradiating light onto an object and photoelectrically converting light from the objectUS6781628 *Nov 25, 1998Aug 24, 2004Sony CorporationSolid-state image pickup device and method of driving the sameUS8243177 *Dec 18, 2009Aug 14, 2012CMOS Senor, Inc.Wafer-scale cluster image sensor chip and method with replicated gapless pixel line and signal readout circuit segmentsUS20110149132 *Dec 18, 2009Jun 23, 2011Weng-Lyang WangWafer-scale Cluster Image Sensor Chip and Method with Replicated Gapless Pixel Line and Signal Readout Circuit SegmentsCN1095143C *Aug 22, 1995Nov 27, 2002佳能株式会社Picture reading apapratus, picture processing apparatus and method thereofEP0696869A2 *Jul 31, 1995Feb 14, 1996Canon Kabushiki KaishaImage sensing device and image reading apparatus using the sameEP0703702A2 *Aug 21, 1995Mar 27, 1996Canon Kabushiki KaishaImage reading apparatus, image processing apparatus, and method thereforEP0886438A2 *Jul 31, 1995Dec 23, 1998Canon Kabushiki KaishaImage sensing device and image reading apparatus using same* Cited by examinerClassifications U.S. Classification348/265, 257/215, 348/281, 348/E03.22, 348/382International ClassificationH01L31/10, H01L29/762, H04N1/028, H01L27/148, H04N3/15, H01L21/339, H04N1/48Cooperative ClassificationH04N3/1575, H04N1/486European ClassificationH04N1/48C, H04N3/15FLegal EventsDateCodeEventDescriptionFeb 1, 2005FPAYFee paymentYear of fee payment: 12Feb 8, 2001FPAYFee paymentYear of fee payment: 8Feb 18, 1997FPAYFee paymentYear of fee payment: 4Nov 18, 1991ASAssignmentOwner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:KANEDA, OSAMU;REEL/FRAME:005917/0595Effective date: 19910917RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google