Source: http://www.google.com/patents/US7209997?dq=6,202,008
Timestamp: 2017-06-22 23:24:33
Document Index: 86570490

Matched Legal Cases: ['Application No. 00108822', 'Application No. 91908374', 'Application No. 91908374', 'Application No. 91908374', 'Application No. 00', 'Application No. 00', 'Application No. 00', 'Application No. 89', 'Application No. 91', 'Application No. 00010832', 'Application No. 00010832', 'Application No. 0010822', 'Application No. 0010822']

Patent US7209997 - Controller device and method for operating same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA controller device and method for operating same is disclosed. In one particular exemplary embodiment, the controller device may comprise output driver circuitry and input receiver circuitry. The output driver circuitry may output a value, a first operation code, a block size value, and second operation...http://www.google.com/patents/US7209997?utm_source=gb-gplus-sharePatent US7209997 - Controller device and method for operating sameAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7209997 B2Publication typeGrantApplication numberUS 10/716,596Publication dateApr 24, 2007Filing dateNov 20, 2003Priority dateApr 18, 1990Fee statusLapsedAlso published asUS6684285, US6715020, US6728819, US6751696, US6807598, US20010023466, US20020087777, US20020099896, US20020147877, US20030005208, US20060039213Publication number10716596, 716596, US 7209997 B2, US 7209997B2, US-B2-7209997, US7209997 B2, US7209997B2InventorsMichael Farmwald, Mark HorowitzOriginal AssigneeRambus Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (99), Non-Patent Citations (99), Referenced by (6), Classifications (80), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetController device and method for operating same
The contents of the sense amps thus may be held and used as a cache, allowing faster, repetitive access to small blocks of data. DRAM-based page-mode caches have been attempted in the prior art using conventional DRAM organizations but they are not very effective because several chips are required per computer word. Such a conventional page-mode cache contains many bits (for example, 32 chips×4 Kbits) but has very few independent storage entries. In other words, at any giv n point in time the s nse amps hold only a few different blocks or memory “locales” (a single block of 4K words, in the example above). Simulations have shown that upwards of 100 blocks are required to achieve high hit rates (>90% of requests find the requested data already in cache memory) regardless of the size of each block. See, for example, Anant Agarwal, et. al, “An Analytic Cache Model,” ACM Transactions on Computer Systems, Vol. 7(2), pp 184–215 (May 1989).
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3633166May 5, 1970Jan 4, 1972IbmData transmission method and serial loop data transmission systemUS3691534Nov 4, 1970Sep 12, 1972Gen Instrument CorpRead only memory system having increased data rate with alternate data readoutUS3740723Dec 28, 1970Jun 19, 1973IbmIntegral hierarchical binary storage elementUS3758761Aug 17, 1971Sep 11, 1973Texas Instruments IncSelf-interconnecting/self-repairable electronic systems on a sliceUS3771145Feb 1, 1971Nov 1, 1994Wiener Patricia P.Integrated circuit read-only memoryUS3821715Jan 22, 1973Jun 28, 1974Intel CorpMemory system for a multi chip digital computerUS3846763Jan 4, 1974Nov 5, 1974Honeywell Inf SystemsMethod and apparatus for automatic selection of translators in a data processing systemUS3882470Feb 4, 1974May 6, 1975Honeywell Inf SystemsMultiple register variably addressable semiconductor mass memoryUS3924241May 7, 1973Dec 2, 1975Burroughs CorpMemory cycle initiation in response to the presence of the memory addressUS3950735Jan 4, 1974Apr 13, 1976Honeywell Information Systems, Inc.Method and apparatus for dynamically controlling read/write operations in a peripheral subsystemUS3967206Mar 19, 1975Jun 29, 1976The United States Of America As Represented By The Secretary Of The ArmyDual edge and level (DEL) flip-flopUS3969706Oct 8, 1974Jul 13, 1976Mostek CorporationDynamic random access memory misfet integrated circuitUS3972028Dec 20, 1974Jul 27, 1976Olympia Werke AgData processing system including a plurality of memory chips each provided with its own address registerUS3975714Dec 20, 1974Aug 17, 1976Olympia Werke AgData processing system including an LSI chip containing a memory and its own address registerUS3983537Apr 1, 1974Sep 28, 1976Hawker Siddeley Dynamics LimitedReliability of random access memory systemsUS4007452Jul 28, 1975Feb 8, 1977Intel CorporationWafer scale integration systemUS4016545Jul 31, 1975Apr 5, 1977Harris CorporationPlural memory controller apparatusUS4038648Jun 3, 1974Jul 26, 1977Chesley Gilman DSelf-configurable circuit structure for achieving wafer scale integrationUS4047246Jan 10, 1977Sep 6, 1977Data General CorporationI/O bus transceiver for a data processing systemUS4048673Feb 27, 1976Sep 13, 1977Data General CorporationCpu - i/o bus interface for a data processing systemUS4084154May 1, 1975Apr 11, 1978Burroughs CorporationCharge coupled device memory system with burst modeUS4092665Dec 29, 1976May 30, 1978Xerox CorporationMethod and means for extracting variable length data from fixed length bytesUS4099231Oct 1, 1975Jul 4, 1978Digital Equipment CorporationMemory control system for transferring selected words in a multiple memory word exchange during one memory cycleUS4183095Sep 1, 1978Jan 8, 1980Ncr CorporationHigh density memory deviceUS4191996Jul 22, 1977Mar 4, 1980Chesley Gilman DSelf-configurable computer and memory systemUS4205373May 22, 1978May 27, 1980Ncr CorporationSystem and method for accessing memory connected to different bus and requesting subsystemUS4231104Apr 26, 1978Oct 28, 1980Teradyne, Inc.Generating timing signalsUS4234934Nov 30, 1978Nov 18, 1980Sperry Rand CorporationApparatus for scaling memory addressesUS4247817May 15, 1978Jan 27, 1981Teradyne, Inc.Transmitting electrical signals with a transmission time independent of distance between transmitter and receiverUS4249247Jan 8, 1979Feb 3, 1981Ncr CorporationRefresh system for dynamic RAM memoryUS4253147Apr 9, 1979Feb 24, 1981Rockwell International CorporationMemory unit with pipelined cycle of operationsUS4257097Dec 11, 1978Mar 17, 1981Bell Telephone Laboratories, IncorporatedMultiprocessor system with demand assignable program paging storesUS4263650Jan 30, 1979Apr 21, 1981Motorola, Inc.Digital data processing system with interface adaptor having programmable, monitorable control register thereinUS4286321Jun 18, 1979Aug 25, 1981International Business Machines CorporationCommon bus communication system in which the width of the address field is greater than the number of lines on the busUS4306298Oct 9, 1979Dec 15, 1981Texas Instruments IncorporatedMemory system for microprocessor with multiplexed address/data busUS4315308Dec 21, 1978Feb 9, 1982Intel CorporationInterface between a microprocessor chip and peripheral subsystemsUS4322635Nov 23, 1979Mar 30, 1982Texas Instruments IncorporatedHigh speed serial shift register for MOS integrated circuitUS4330852Nov 23, 1979May 18, 1982Texas Instruments IncorporatedSemiconductor read/write memory array having serial accessUS4333142Jul 12, 1979Jun 1, 1982Chesley Gilman DSelf-configurable computer and memory systemUS4337523Jun 9, 1980Jun 29, 1982Hitachi, Ltd.Bipolar memory circuitUS4338569Mar 11, 1980Jul 6, 1982Control Data CorporationDelay lock loopUS4354258Feb 11, 1980Oct 12, 1982Tokyo Shibaura Denki Kabushiki KaishaMemory board automatically assigned its address range by its positionUS4355376Sep 30, 1980Oct 19, 1982Burroughs CorporationApparatus and method for utilizing partially defective memory devicesUS4360870Jul 30, 1980Nov 23, 1982International Business Machines CorporationProgrammable I/O device identificationUS4373183Aug 20, 1980Feb 8, 1983Ibm CorporationBus interface units sharing a common bus using distributed control for allocation of the busUS4375665Jul 14, 1980Mar 1, 1983Texas Instruments IncorporatedEight bit standard connector bus for sixteen bit microcomputer using mirrored memory boardsUS4379222Aug 21, 1980Apr 5, 1983Ncr CorporationHigh speed shift registerUS4385350Jul 16, 1980May 24, 1983Ford Aerospace & Communications CorporationMultiprocessor system having distributed priority resolution circuitryUS4394753Nov 12, 1980Jul 19, 1983Siemens AktiengesellschaftIntegrated memory module having selectable operating functionsUS4405996Feb 6, 1981Sep 20, 1983Rca CorporationPrecharge with power conservationUS4408272Nov 3, 1980Oct 4, 1983Bell Telephone Laboratories, IncorporatedData control circuitUS4412286Mar 23, 1981Oct 25, 1983Dowd Brendan OTightly coupled multiple instruction multiple data computer systemUS4426685Mar 29, 1982Jan 17, 1984The United States Of America As Represented By The Secretary Of The NavySolid state delay deviceUS4435762Mar 6, 1981Mar 6, 1984International Business Machines CorporationBuffered peripheral subsystemsUS4443864Oct 13, 1981Apr 17, 1984Texas Instruments IncorporatedMemory system for microprocessor with multiplexed address/data busUS4445204Oct 5, 1981Apr 24, 1984Nippon Electric Co., Ltd.Memory deviceUS4449207Apr 29, 1982May 15, 1984Intel CorporationByte-wide dynamic RAM with multiplexed internal busesUS4466127May 16, 1979Aug 14, 1984Sanyo Electric Co., Ltd.Entry apparatus of digital value in memoryUS4468733Jun 4, 1981Aug 28, 1984Hitachi, Ltd.Multi-computer system with plural serial bus loopsUS4468738Jul 5, 1983Aug 28, 1984Ford Aerospace & Communications CorporationBus access arbitration using unitary arithmetic resolution logic and unique logical addresses of competing processorsUS4470114Mar 1, 1982Sep 4, 1984Burroughs CorporationHigh speed interconnection network for a cluster of processorsUS4480307Jan 4, 1982Oct 30, 1984Intel CorporationInterface for use between a memory and components of a module switching apparatusUS4481572Oct 13, 1981Nov 6, 1984Teledyne Industries, Inc.Multiconfigural computers utilizing a time-shared busUS4481625Oct 21, 1981Nov 6, 1984ElxsiHigh speed data bus systemUS4481647May 6, 1982Nov 6, 1984Tektronix, Inc.Method and apparatus of compensating for variations in signal propagation time existing within the channels of a multi-channel deviceUS4482999Dec 1, 1981Nov 13, 1984International Business Machines CorporationMethod of transmitting information between stations attached to a _unidirectional transmission ringUS4488218Jan 7, 1982Dec 11, 1984At&T Bell LaboratoriesDynamic priority queue occupancy scheme for access to a demand-shared busUS4494021Aug 30, 1982Jan 15, 1985Xerox CorporationSelf-calibrated clock and timing signal generator for MOS/VLSI circuitryUS4494186Jul 24, 1981Jan 15, 1985Honeywell Information Systems Inc.Automatic data steering and data formatting mechanismUS4499536Dec 9, 1981Feb 12, 1985Hitachi, Ltd.Signal transfer timing control using stored data relating to operating speeds of memory and processorUS4500905Sep 28, 1982Feb 19, 1985Tokyo Shibaura Denki Kabushiki KaishaStacked semiconductor device with sloping sidesUS4506348Jun 14, 1982Mar 19, 1985Allied CorporationVariable digital delay circuitUS4509142Dec 15, 1982Apr 2, 1985Texas Instruments IncorporatedSemiconductor memory device with pipeline accessUS4513370Jul 19, 1982Apr 23, 1985Amdahl CorporationData transfer control system and method for a plurality of linked stationsUS4513372Nov 15, 1982Apr 23, 1985Data General CorporationUniversal memoryUS4513374Nov 25, 1983Apr 23, 1985Ltv Aerospace And DefenseMemory systemUS4519034Sep 28, 1982May 21, 1985ElxsiI/O Bus clockUS4520465May 5, 1983May 28, 1985Motorola, Inc.Method and apparatus for selectively precharging column lines of a memoryUS4528661Feb 14, 1983Jul 9, 1985Prime Computer, Inc.Ring communications systemUS4535427Dec 6, 1982Aug 13, 1985Mostek CorporationControl of serial memoryUS4536795Feb 4, 1983Aug 20, 1985Victor Company Of Japan, Ltd.Video memory deviceUS4562435Sep 29, 1982Dec 31, 1985Texas Instruments IncorporatedVideo display system using serial/parallel access memoriesUS4566098May 14, 1984Jan 21, 1986Northern Telecom LimitedControl mechanism for a ring communication systemUS4566099Jul 1, 1983Jan 21, 1986Siemens AktiengesellschaftSynchronous clock generator for digital signal multiplex devicesUS4570220Nov 25, 1983Feb 11, 1986Intel CorporationHigh speed parallel bus and data transfer methodUS4571672Dec 19, 1983Feb 18, 1986Hitachi, Ltd.Access control method for multiprocessor systemsUS4586167Jan 4, 1984Apr 29, 1986Mitsubishi Denki Kabushiki KaishaSemiconductor memory deviceUS4589108May 3, 1984May 13, 1986Billy Jean CMultiplexer, demultiplexer and multiplexing-demultiplexing equipment with reconfigurable framesUS4595923Apr 24, 1984Jun 17, 1986ElxsiImproved terminator for high speed data busUS4597019Mar 19, 1984Jun 24, 1986Victor Company Of Japan, Ltd.Clock pulse generating circuit in a color video signal reproducing apparatusUS4607173Mar 14, 1984Aug 19, 1986At&T Bell LaboratoriesDual-clock edge triggered flip-flop circuitsUS4608700Jul 29, 1982Aug 26, 1986Massachusetts Institute Of TechnologySerial multi-drop data linkUS4616268Mar 5, 1984Oct 7, 1986Dainippon Screen Mfg. Co., Ltd.Method and system for increasing use efficiency of a memory of an image reproducing systemUS4625307Dec 13, 1984Nov 25, 1986United Technologies CorporationApparatus for interfacing between at least one channel and at least one busUS4628489Oct 3, 1983Dec 9, 1986Honeywell Information Systems Inc.Dual address RAMUS4629909Oct 19, 1984Dec 16, 1986American Microsystems, Inc.Flip-flop for storing data on both leading and trailing edges of clock signalUS4630193Apr 27, 1981Dec 16, 1986Textron, Inc.Time multiplexed processor busUS4631659Apr 1, 1985Dec 23, 1986Texas Instruments IncorporatedMemory interface with automatic delay stateUS4633735Oct 23, 1985Jan 6, 1987Nippondenso Co., Ltd.Automobile differential gear systemNon-Patent CitationsReference1"Fast Packet Bus for Microprocessor Systems with Caches", IBM Technical Disclosure Bulletin, pp. 279-282 (Jan. 1989).2"High Speed CMOS Databook", Integrated Device Technology Inc. Santa Clara, CA, 1988 pp. 9-1 to 9-14.3"LR2000 High Performance RISC Microprocessor Preliminary" LSI Logic Corp. 1988, pp. 1-15.4"LR2010 Floating Point Accelerator Preliminary" LSI Logic Corp. 1988, pp. 1-20.5A. Fielder et al., "A 3 NS IK X 4 Static Self-Timed GaAs RAM", IEEE Gallium Arsenide Integrated Circuit Symposium Technical Digest, pp. 67-70, (Nov. 1988).6A. L. Yuen, "A 32K ASIC Synchronous RAM Using a Two-Transistor Basic Cell", IEEE Journal of Solid State Circuits, vol. 27 No. 1, pp. 57-61 (Oct. 1989).7A. Yuen et. al., "A 32K ASIC Synchronous RAM Using a Two-Transistor Basic Cell", IEEE Journal of Solid State Circuits, vol. 24 No. 1, pp. 57-61 (Feb. 1989).8Alnes, Norsk Data Report, Nov. 10, 1988, SCI: A Proposal For.9Bakka et al., "SCI: Logical Level Proposals", SCI-Jan. 6, 1989-doc32, Norsk Data, Oslo, Norway, pp. 1-20, Jan. 6, 1989.10Boysel et al., "Four-Phase LSI Logic Offers New Approach to Computer Designer", Four-Phase Systems Inc. Cupertino, CA, Computer Design, Apr. 1970, pp. 141-146.11Boysel et al., "Random Access MOS Memory Packs More Bits To The Chip" , Electronics, Feb. 16, 1970, pp. 109-146.12Brief Communication in the Opposition against European patent 1 022 642 (Application No. 00108822.8), Apr. 16, 2004.13Communication of the Technical Board of Appeal 3.5.1 pursuant to Article 11 (1) of the rules of procedure of the Boards of Appeals in the Opposition against European patent 0 525 068 (Application No. 91908374.1-2201), Nov. 20, 2003.14D. Jones. "Synchronous static ram", Electronics and Wireless World, vol. 93, No. 1622, pp. 1243-1244 (Dec. 1987).15D. Wendell et. al., "A 3.5ns, 2Kx9 Self Timed SRAM", 1990 IEEE Symposium on VLSI Circuits (Feb. 1990).16D.T. Wong et al., "An 11-ns 8Kx18 CMOS Static RAM with 0.5-mum Devices", IEEE Journal of Solid State Circuits, vol. 23, No. 5, pp. 1095-1103 (Oct. 1988).17Decision of Feb. 12, 2004 by the Board of Appeals of the EPO in the Opposition against European patent 0 525 068 (Application No. 91908374.1).18Decision of the Technical Board of Appeal 3.5.1 of Feb. 12, 2004 in the Opposition against European patent 0 525 068 (Application No. 91908374.1-2201/0525068).19Emmerson et al., IEEE MICRO, Dec. 00, 1984, Fault Tolerance Achieved in VLSI.20European Search Report for EPO Patent Application No. 00 10 0018.21European Search Report for EPO Patent Application No. 00 10 822.22European Search Report for EPO Patent Application No. 00 101 1832.23European Search Report for EPO Patent Application No. 89 30 2613.24F. Miller et. al., "High Frequency System Operation Using Synchronous SRAMS", Midcon/87 Conference Record, pp. 430-432 Chicago, IL, USA; Sep. 15-17, 1987.25F. Towler et. al., "A 128k 6.5ns Access/ 5ns Cycle CMOS ECL Static RAM", 1989 IEEE International Solid State Circuits Conference, (Feb. 1989).26Fellin et al., Intel, Application Note, AP-132, Designing Memory Systems with the 8K x 8 iRAM, Jun. 1982.27Gelsinger et al., IEEE Spectrum Oct. 1989, Microprocessors circa 2000, 1989 (pp. 43-47).28GigaBit Logic, GaAs IC Data Book & Designer's Guide, May 1988, pp. 1.1-10.3.29Grover et al., "Precision Time-Transfer in Transport Networks Using Digital Crossconnect Systems", IEEE Paper 47.2 Globecom, 1988, pp. 1544-1548.30Gustavson et al., "The Scalable Interface Project (Superbus)" (DRAFT), SCI-22 Aug. 88-doc1 pp. 1-16, Aug. 22, 1988.31Gustavson, D. "Scalable Coherent Interface"; Invited Paper, COMPCON Spring '89, San Francisco, CA; IEEE, pp. 536-538 (Feb. 27-Mar. 3, 1989).32Gustavson, David B. et al., Aug. 22, 1988, SCIA [I and SCI 2], The Scalable Coherent Interface Project (Superbus), Draft.33Gustavson, David B., Nov. 28, 1988, SCI-C [1 and SCI 2], Scalable Coherent Interface.34H. Kuriyama et al., "A 4-Mbit CMOS SRAM With 8-NS Serial Access Time", IEEE Symposium On VLSI Circuits Digest Of Technical Papers, pp. 51-52, (Jun. 1990).35H. L. Kalter et al. "A 50-ns 16Mb DRAM with a 10-ns Data Rate and On-Chip ECC" IEEE Journal of Solid State Circuits, vol. 25 No. 5, pp. 1118-1128 (Oct. 1990).36Hansen et al., "A RISC Microprocessor With Integral MMU and Cache Interface", MIPS Computer Systems, Sunnyvale, CA, IEEE 1986 pp. 145-148.37Huber, Expert Report Regarding the Invention Claimed in Rambus' EP 0 525 068 Patent vs. The CVAX CMCTL-A CMOS Memory Controller Chip and Designing Memory Systems with the 8K x 8 iRAM, Jul. 13, 2004.38Hynix's Amended Supplemental Revised Preliminary Invalidity Contentions.39Intel, Electrical Specifications for iAPX 43204 Bus-Interface Unit (BIU) and iAPX 43205 Memory Control Unit (MCU), Mar. 1983.40Intel, Iapx 432 Interconnect Architecture Reference Manual, 1982.41Intel, iAPX 43204, iAPX 43205, Fault Tolerant Bus Interface and Memory Control Units, pp. 1-32, Mar. 1983.42Intel, Intel Publication No. 17 1874-001 Rev. A, 1981 iAPX432 IP Datasheet, Intel iAPX43203 VLSI Interface Processor Data Sheet.43Intel, Intel Publication No. 171873-001 Rev. A, 1981, iAPX432 GDP Datasheet, Intel iAPX43202 VLSI General Data Processor Data Sheet.44Intel, Memory Components Handbook, 1985.45Invalidity argument materials of potential licensee relating to claim 1 of U.S. Appl. No. 6,034,918, which is related to present U.S. Appl. No. 10/716,596 by virtue of the fact that both claim priority to U.S. Appl. No. 07/510,898 (now abandoned), citing J.L. Rodengen, The Legend of Amdahl, Write Stuff Syndicate, Inc., 2000, and FACOM M-780, Operating Manual, including two separate English language translations thereof.46Invalidity argument materials of potential licensee relating to claim 23 of U.S. Appl. No. 6,038,195, to which present U.S. Appl. No. 10/716,596 claims priority and is related by virtue of the fact that both claim priority to U.S. Appl. No. 07/510,898 (now abandoned), citing J.L. Rodengen, The Legend of Amdahl, Write Stuff Syndicate, Inc., 2000, and FACOM M-780, Operating Manual, including two separate English language translations thereof.47J. Chun et al., "A 1.2ns GaAs 4K Read Only Memory", IEEE Gallium Arsenide Integrated Circuit Symposium Technical Digest, pp. 83-86, (Nov. 1988).48J. Sonntag et al., "A Monolithic CMOS 10MHz DPLL for Burst-Mode Data Retiming", IEEE International Solid State Circuits Conference (ISSCC) Feb. 16, 1990).49JEDEC Standard No. 21C.50JEDEC, JC 42.3 Committee On MOS Memories, Dec. 6, 1989, Minutes Of Meeting No. 52 JC 42.3 Committee On MOS Memories w/Attachment K.51JEDEC, JC 42.3 Committee On Mos Memories, Dec. 7, 1988 Minutes Of Meeting No. 48 JC 42.3 Committee On MOS Memories WI Attachment L Proposal.52JEDEC, JC 42.3 Committee On MOS Memories, Sep. 14, 1988, Minutes Of Meeting No. 47 JC-42.3 Committee On MOS Memories w/Attachment L (Proposal).53JEDEC, JC 42.3 Committee On Sep. 12, 1989, Minutes of Meeting No. 51 JC 42.3 MOS Memories Committee On MOS Memories.54Jeong et al., Design of PLL-Based Clock Generation Circuits, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.55Johnson et al., Session XI: High Speed Logic; THAM 11.3: A Variable Delay Line Phase Loop for CPU-Coprocessor Synchronization, ISSCC 88, Thursday, Feb. 18, 1988, Continental Ballroom 6, 10:00 AM, pp. 142-143, 334 and 336.56Johnson, Mark G; Hudson, Edwin L., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 00, 1988, Johnson (IEEE Oct. 1988), A Variable Delay Line PLL For CPU- Coprocessor Synchronization.57K. Nogami et. al., "A 9-ns HIT-Delay 32-kbyte Cache Macro for High-Speed RISC", IEEE Journal of Solid State Circuits, vol. 25 No. 1, pp. 100-108 (Feb. 1990).58K. Numata et. al., "New Nibbled-Page Architecture for High Density DRAM's", IEEE Journal of Solid State Circuits, vol. 24 No. 4, pp. 900-904 (Aug. 1989).59K. Ohta, "A 1-Mbit DRAM with 33-MHz Serial I/O Ports", IEEE Journal of Solid State Circuits, vol. 21 No. 5, pp. 649-654 (Oct. 1986).60Knut Alnes, "Scalable Coherent Interface", SCI-Feb. 1989-doc52, (To appear in the Eurobus Conference Poceedings May 1989), pp. 1-8.61Knut Alnes, "SCI: A Proposal for SCI Operation", SCI-Nov. 10, 1988-doc.23, Norsk Data, Oslo, Norway, pp. 1-12, Nov. 10, 1988.62Knut Alnes, "SCI: A Proposal for SCI Operaton", SCI-Jan. 6, 1989-doc31, Norsk Data, Oslo, Norway, pp. 1-24, Jan. 6, 1989.63L. R. Metzeger, "A 16K CMOS PROM with Polysilicon Fusible Links", IEEE Journal of Solid State Circuits, vol. 18 No. 5, pp. 562-567 (Oct. 1983).64L. R. Metzeger, "A 16K CMOS PROM with Polysilicon Fusible Links", IEEE Journal of Solid State Circuits, vol. SC-18 No. 5, pp. 561-567 (Oct. 1983).65Lidington, Gary P., Digital Technical Journal, No. 7, Aug. 1988, pp. 79-86, Overview of the MicroVAX 3 500/3600 Processor Module.66Lidington, Gary P., Digital Technical Journal, No. 7, Aug. 1988, pp. 79-86, Overview of the MicroVAX 3500/3600 Processor Module.67Lu et al., The Future of DRAMs, ISSCC 88, Feb. 18, 2004, pp. 1-2.68M. Horowitz et al., "MIPS-X: A 20-MIPS Peak 32-bit Microprocessor with On-Chip Cache", IEEE Journal of Solid State Circuits, vol. 22 No. 5, pp. 790-799 (Oct. 1987).69M. Kimoto, "A 1.4ns/64kb RAM with 85ps/3680 Logic Gate Array", 1989 IEEE Custom Integrated Circuits Conference.70Minutes of the oral proceedings of Feb. 10, 2004 in the Opposition against European patent 0 525 068, Feb. 18, 2004.71Morgan, The CVAX CMCTL-A CMOS Memory Controller Chip, Digital Technical Journal, No. 7, Aug. 1988, pp. 139-143.72Moussouris et al., "A CMOS Processor with Integrated Systems Functions", MIPS Computer Systems, Sunnyvale, CA, IEEE 1986 pp. 126-130.73Moussouris, J. "The Advanced Systems Outlook-Life Beyond RISC: The next 30 years in high-performance computing", Computer Letter, Jul. 31, 1989 (an edited excerpt from an address at the fourth annual confernece on the Advanced Systems Outlook, in San Francisco, CA (Jun. 5)).74N. Siddique, "100-MHz DRAM Controller Sparks Multiprocessor Designs", Electronic Design. pp. 138-141, (Sep. 1986).75Numata, K. et. al., IEEE Journal of Solid State Circuits, vol. 24 No. 4, pp. 900-904, Aug. 00, 1989, New Nibbled -Page Architecture for High Density DRAM's.76Ohno, C.; "Self-Timed RAM: STRAM"; Fujitsu Sci. TechJ., 24, 4, pp. 293-300 (Dec. 1988).77Opposition against European patent 0 525 068, (Application No. 91 908 374.1-2201) (German & English Translation), Apr. 15, 2004.78Opposition against European patent 1004956, (Application No. 00010832.4) (German & English Translation), Jul. 15, 2004.79Opposition against European patent 1004956, (Application No. 00010832.4) (German & English Translation), Mar. 3, 2004).80Opposition against European patent 1022642, (Application No. 0010822.8) (German & English Translation), Jul. 15, 2004.81Opposition against European patent 1022642, (Application No. 0010822.8) (German & English Translation), Mar. 2, 2004).82Patterson et al., Computer Architecture A Quantitative Approach.83Patterson, David A. et al., Morgan Kaufmaim Publishers, Inc., San Francisco, CA 1996, Computer Architecture A Quantitative Approach (Second Edition), excerpts.84Peigrom, M. et al., ESSCIRC Dig. Tech. Papers, pp. 38-40, Sep. 00, 1986, A 32Kbit Variable Lenth Shift Register for Digital Audio Application.85Pelgrom et al., "A 32-kbit Variable-Length Shift Register for Digital Audio Application", IEEE Journal of Solid-State Circuits, vol. sc-22, No. 3, Jun. 1987, pp. 415-422.86Poon, T. C., et al., IEEE Journal of Solid State Circuits, vol. SC-22, No. 3, pp. 491-494, 1987, A CMOS DRAM-Controller Chip Implementation.87Prince et al., Semiconductor Memories, A Wiley-Interscience Publication, 1983.88R. L. Schmidt, "A memory Control Chip for Formatting Data into Blocks Suitable for Video Coding Applications", IEEE Transactions on Circuits And Systems, vol. 36 No. 10, pp. 1275-1280 (Oct. 1989).89Riordan T. "MIPS R2000 Processor Interface 78-00005(C)", MIPS Computer Systems, Sunnyvale, CA, Jun. 30, 1987, pp. 1-83.90S. Watanabe et. al., "AN Experimental 16-Mbit CMOS DRAM Chip with a 100-MHz Serial Read/Write Mode", IEEE Journal of Solid State Circuits, vol. 24, No. 3, pp. 763-770 (Jun. 1982).91Sawada, Kazuhiro et al., IEEE 1988 Custom Integrated Circuits Conference 1988, A 72K CMOS Channelless Gate Array With Embedded 1 Mbit Dynamic RAM.92Schanke, Morten, May 5, 1989, SCIB [1 and SCI 2], Proposal for Clock Distribution in SCI.93Summons To Attend Oral Proceedings Pursuant to Rule 71(1) EPC in the Opposition against European patent 1 004 956, Jul. 20, 2004.94Sutherland, Ivan E., Communications of the ACM, Jun. 1989, vol. 32, No. 6, Micropipelines.95T. Williams et al., "An Experimental 1-Mbit CMOS SRAM with Configurable Organization and Operation", IEEE Journal of Solid State Circuits, vol. 23, No. 5, pp. 1085-1094 (Oct. 1988).96T.L. Jeremiah et al., "Synchronous Packet Swtiching Memory and I/O Channel," IBM Tech. Disc. Bul,. vol. 24, No. 10, pp. 4986-4987 (Mar. 1982).97Watanabe, S. et. al., IEEE Journal of Solid State Circuits, vol. 24 No. 3, p. 763, Jun. 00, 1982, An Experimental 16-Mbit CMOS DRAM Chip with a 100-MHz Serial Read/Write Mode.98Watanabe, T.; "Session XIX: High Density SRAMS"; IEEE International Solid State Circuits Conference pp. 266-267 (1987).99Z. Amitai, "New System Archtitectures for DRAM Control and Error Correction", Monolithic Memories Inc., Electro/87 and Mini/Mico Northeast: Focusing on the OEM Conference Record, pp. 1132, 4/31-3, (Apr. 1987).Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8254205Jun 29, 2009Aug 28, 2012Hynix Semiconductor Inc.Circuit and method for shifting addressUS8461782Aug 27, 2009Jun 11, 2013Allegro Microsystems, LlcLinear or rotational motor driver identificationUS9172565Feb 18, 2014Oct 27, 2015Allegro Microsystems, LlcSignaling between master and slave components using a shared communication node of the master componentUS9552315Jan 6, 2012Jan 24, 2017Allegro Microsystems, LlcDetermining addresses of electrical components arranged in a daisy chainUS20100290306 *Jun 29, 2009Nov 18, 2010Jong Chern LeeCircuit and method for shifting addressUS20110055442 *Aug 27, 2009Mar 3, 2011Ward Michael GLinear or rotational motor driver identification* Cited by examinerClassifications U.S. Classification710/305, 365/189.17, 365/194International ClassificationG11C11/4076, G11C11/4096, G11C5/06, G11C5/00, G11C8/00, G11C7/10, G06F12/06, G06F11/10, G06F13/16, G06F13/376, G11C29/00, G06F11/00, G11C7/22, G06F12/02, G06F13/00Cooperative ClassificationG06F13/1605, G11C8/00, G06F11/1048, G06F13/1678, G11C7/222, G06F13/1694, G11C5/04, G11C29/88, G06F11/006, G11C7/1069, G11C7/1066, G11C2207/105, G06F13/1689, G11C7/1045, G11C11/4096, G11C8/12, G11C7/1006, G11C7/1012, G11C7/1057, G11C7/109, G11C11/4076, G06F13/376, G11C7/1051, G06F12/0661, G11C7/1078, G11C7/22, G11C2207/108, G11C7/225, G06F12/0684, G11C5/066, G11C7/1072, G06F12/0215, G06F13/161European ClassificationG11C5/06M, G11C8/12, G06F12/06K2D, G11C8/00, G11C7/10L, G11C11/4096, G11C7/10M7, G06F12/02C, G06F12/06K6, G06F13/16A, G11C7/10R, G11C11/4076, G06F13/16D9, G06F13/16D8, G11C7/10S, G06F13/16A2, G06F13/376, G11C5/04, G06F13/16D4, G11C29/88, G11C7/10R7, G11C7/10L3, G11C7/10R2, G11C7/22A, G11C7/10W5, G11C7/10R9, G11C7/22B, G11C7/10W, G11C7/22Legal EventsDateCodeEventDescriptionJul 14, 2009RRRequest for reexamination filedEffective date: 20090515Jul 28, 2009RRRequest for reexamination filedEffective date: 20090515Oct 12, 2010B1Reexamination certificate first reexaminationFree format text: THE PATENTABILITY OF CLAIMS 1-38 IS CONFIRMED.Oct 25, 2010FPAYFee paymentYear of fee payment: 4May 22, 2012B2Reexamination certificate second reexaminationFree format text: THE PATENTABILITY OF CLAIMS 1-38 IS CONFIRMED.Dec 5, 2014REMIMaintenance fee reminder mailedApr 24, 2015LAPSLapse for failure to pay maintenance feesJun 16, 2015FPExpired due to failure to pay maintenance feeEffective date: 20150424RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services