Source: http://www.google.com/patents/US7800623?dq=4200770
Timestamp: 2016-09-25 23:07:42
Document Index: 356452400

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 200405099', 'Application No. 200401969', 'Application No. 200401969', 'Application No. 200410047784', 'Application No. 200410038432', 'Application No. 200410038546', 'application No. 200410044503', 'Application No. 200410071497', 'Application No. 04255786', 'Application No. 04255610', 'Application No. 04255786', 'Application No. 04252205', 'Application No. 04251582', 'Application No. 04252056', 'Application No. 04252202', 'Application No. 04252057', 'Application No. 04252203', 'Application No. 04252054', 'Application No. 04255609', 'Application No. 04255611', 'Application No. 04251581', 'Application No. 04252054', 'Application No. 04252056', 'Application No. 04252057', 'Application No. 04252202', 'Application No. 04252203', 'Application No. 04255610', 'Application No. 04255609', 'Application No. 200402057', 'Application No. 04255609', 'Application No. 04252055', 'Application No. 200410044503', 'Application No. 200410044503', 'Application No. 200410043419', 'Application No. 200410045686', 'Application No. 200410087460', 'Application No. 04252205', 'Application No. 200410038545', 'Application No. 200410095171', 'Application No. 200410043419', 'Application No. 200410071498', 'Application No. 2004100950502', 'Application No. 200410095171', 'Application No. 200410044503', 'Application No. 08153454', 'Application No. 08153726', 'Application No. 08155263', 'Application No. 08153724', 'Application No. 08155262', 'Application No. 200401973', 'Application No. 200401979', 'Application No. 200402060', 'Application No. 200402061', 'Application No. 200401166', 'Application No. 200401975', 'Application No. 200405336', 'Application No. 200405115']

Patent US7800623 - Bypassing pixel clock generation and CRTC circuits in a graphics controller chip - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsIn a video processor unit, a method of providing a video data stream at a clock rate that is independent of a pixel clock rate. Receiving native video data from a video source at a native clock rate, storing the video data in a memory unit, reading selected portions of the video data at a memory clock...http://www.google.com/patents/US7800623?utm_source=gb-gplus-sharePatent US7800623 - Bypassing pixel clock generation and CRTC circuits in a graphics controller chipAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7800623 B2Publication typeGrantApplication numberUS 10/909,027Publication dateSep 21, 2010Filing dateJul 29, 2004Priority dateSep 18, 2003Fee statusPaidAlso published asCN1601598A, CN100437724C, EP1519349A2, EP1519349A3, US20050062699Publication number10909027, 909027, US 7800623 B2, US 7800623B2, US-B2-7800623, US7800623 B2, US7800623B2InventorsOsamu KobayashiOriginal AssigneeGenesis Microchip Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (183), Non-Patent Citations (131), Referenced by (3), Classifications (27), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetBypassing pixel clock generation and CRTC circuits in a graphics controller chip
US 7800623 B2Abstract
1. A pipelined method of displaying video data at a display unit, the display unit comprising: a display unit interface, a single line buffer used for storing video data to be displayed, the single line buffer having a size in accordance with a scan line for display;
and a plurality of display elements, the method comprising:
(a) receiving video data packets associated with the scan line for display at the display unit interface;
(b) directly populating the single line buffer using the video data packets received at the display unit interface within a line period τ, the line period τ corresponding to the scan line for display;
(c) only when the single line buffer is full, passing the video data stored in the single line buffer directly to selected of the plurality of display elements, corresponding to the scan line for display; and
(d) concurrently with passing the video data (c), directly populating the single line buffer using video data packets received at the display unit interface, the received video data packets associated with a next scan line for display.
2. The method of claim 1, wherein the display unit does not generate a clock signal.
3. The method of claim 1, wherein each of the video data packets includes at least a packet header and a packet payload, wherein the packet header includes a packet ID and wherein the packet payload includes video data suitable for driving a corresponding pixel.
4. The method of claim 1, wherein the plurality of display elements comprise thin film transistors.
5. The method of claim 1, wherein the video data packets are directly received by the display unit interface without using Hsync and Vsync timing and control signals and without using a pixel clock signal.
a display unit interface to receive packetized video data associated with a scan line for display directly from a video processing unit (VPU);
a single line buffer used for storing video data to be displayed, wherein the single line buffer is configured to have a size in accordance with a scan line, wherein the display unit interface directly forwards the packetized video data to the single line buffer, filling the single line buffer within a line period T, the line period T corresponding to the scan line for display, wherein only when the single line buffer is full, the packetized video data in the single line buffer is directly passed to selected of the plurality of display elements, wherein concurrently with passing the packetized video data in the single line buffer directly to selected of the plurality of display element, directly populating the single line buffer using packetized video data received at the display unit interface, the received packetized video data associated with a next scan line for display, and wherein the display apparatus does not generate a pixel clock.
7. The display apparatus of claim 6, wherein each of the video data packets of the packetized video data includes at least a packet header and a packet payload, wherein the packet header includes a packet ID and wherein the packet payload includes video data suitable for driving a corresponding pixel.
8. The display apparatus of claim 6, wherein the plurality of display elements comprise thin film transistors.
9. A non-transitory computer-readable medium having stored thereon data representing instructions that, when performed by a processing element of a display unit having a single line buffer having a size in accordance with a scan line and a plurality of display elements, the processor performs operations comprising:
(a) receiving video data packets associated with a scan line at a display unit interface;
(c) only when the single line buffer is full, passing the video data stored in the single line buffer directly to selected of the plurality of display elements; and
10. The computer-readable medium of claim 9, wherein the display unit does not generate a clock signal.
11. The computer-readable medium of claim 9, wherein the plurality of display elements comprise thin film transistors.
12. An integrated circuit configured to:
receive video data packets associated with a scan line for display;
directly populate a single line buffer using the received video data packets within a line period τ, the line period τ corresponding to the scan line for display, wherein the single line buffer has a size in accordance with a scan line;
forward the video data packets stored in the single line buffer to selected display elements only when the single line buffer becomes full; and
concurrently with forwarding the data packets to selected display elements, directly populate the single line buffer using received video data packets associated with a next scan line for display.
This patent application takes priority under 35 U.S.C. 119(e) to (i) U.S. Provisional Patent Application No. 60/504,060 filed on Sep. 18, 2003, entitled “DIGITAL/ANALOG VIDEO INTERCONNECT AND METHODS OF USE THEREOF” by Kobayashi, and (ii) U.S. Provisional Patent Application No. 60/562,737 filed on Apr. 15, 2004, entitled “BYPASSING PIXEL CLOCK GENEARATION AND CRTC CIRCUITS IN A GRAPHICS CONTROLLER CHIP” by Kobayashi each of which are hereby incorporated by reference herein in their entirety. This application is also related to the following co-pending U.S. Patent applications each of which are incorporated by reference, (i) U.S. patent application Ser. No. 10/726,802, entitled “METHOD OF ADAPTIVELY CONNECTING A VIDEO SOURCE AND A VIDEO DISPLAY” naming Kobayashi as inventor; (ii) U.S. patent application Ser. No. 10/726,438, entitled “METHOD AND APPARATUS FOR EFFICIENT TRANSMISSION OF MULTIMEDIA DATA PACKETS” naming Kobayashi as inventor; (iii) U.S. patent application Ser. No. 10/726,440, entitled “METHOD OF OPTIMIZING MULTIMEDIA PACKET TRANSMISSION RATE”, naming Kobayashi as inventor; (iv) U.S. patent application Ser. No. 10/727,131, entitled “USING AN AUXILARY CHANNEL FOR VIDEO MONITOR TRAINING”, naming Kobayashi as inventor; (v) U.S. patent application Ser. No. 10/726,350, entitled “TECHNIQUES FOR REDUCING MULTIMEDIA DATA PACKET OVERHEAD”, naming Kobayashi as inventor; (vi) U.S. patent application Ser. No. 10/726,362, entitled “PACKET BASED CLOSED LOOP VIDEO DISPLAY INTERFACE WITH PERIODIC STATUS CHECKS”, naming Kobayashi as inventor; (vii) U.S. patent application Ser. No. 10/726,895, entitled “MINIMIZING BUFFER REQUIREMENTS IN A DIGITAL VIDEO SYSTEM”, naming Kobayashi as inventor; and (viii) U.S. patent application Ser. No. 10/726,441, entitled “VIDEO INTERFACE ARRANGED TO PROVIDE PIXEL DATA INDEPENDENT OF A LINK CHARACTER CLOCK”, naming Kobayashi as inventor; (ix) U.S. patent application Ser. No. 10/726,934, entitled “ENUMERATION METHOD FOR THE LINK CLOCK RATE AND THE PIXEL/AUDIO CLOCK RATE”, naming Kobayashi as inventor, and (x) U.S. patent application Ser. No. 10/726,794, entitled “PACKET BASED VIDEO DISPLAY INTERFACE AND METHODS OF USE THEREOF” naming Kobayashi as inventor. This application is also related to the following co-pending applications: (x) U.S. patent application Ser. No. 10/909,103, entitled “USING PACKET TRANSFER FOR DRIVING LCD PANEL DRIVER ELECTRONICS” filed Jul. 29, 2004, naming Kobayashi as inventor; and (xi) U.S. patent application Ser. No. 10/909,085, entitled “PACKET BASED STREAM TRANSPORT SCHEDULER AND METHODS OF USE THEREOF” filed Jul. 29, 2004, naming Kobayashi as inventor.
The invention will now be described in terms of a representative LCD panel. However, it should be noted that any digital fixed pixel display, be it LCD, plasma, DLP based, is also suitable and therefore the use of an LCD panel in the following description should not be considered to limit either the scope or the intent of the invention. It should be noted that the invention is also well suited to be used in conjunction with any packet based video display interface such as described in copending U.S. patent application Ser. No. 10/726,794 entitled “PACKET BASED VIDEO DISPLAY INTERFACE AND METHODS OF USE THEREOF” by Kobayashi filed Dec. 3, 2003 and U.S. patent application Ser. No. 10/909,103 entitled “USING PACKET TRANSFER FOR DRIVING LCD PANEL DRIVER ELECTRONICS” by Kobayashi filed concurrently with this application each of which are incorporated herein by reference for all purposes.
Accordingly, FIG. 2 shows an exemplary video processor unit (VPU) 200 in accordance with an embodiment of the invention. The VPU 200 includes an interface 202 coupled to a video source (not shown) such as a CPU, DVD player, etc. capable of providing a video signal V1 at a native clock rate Φnative and a native video format. It should be noted that the video source can include either or both a digital image (i.e. still or digital video) source and/or an analog image (i.e., still or analog video) source. Accordingly, the video source provides various video signals that can have any number and type of well-known formats, such as composite video, serial digital, parallel digital, RGB, or consumer digital video. The video signal can be an analog video signal provided the source includes some form of an analog video source such as for example, an analog television, still camera, analog VCR, DVD player, camcorder, laser disk player, TV tuner, set top box (with satellite DSS or cable signal) and the like. The source can also include a digital image source such as for example a digital television (DTV), digital still camera, and the like. The digital video signal can be any number and type of well known digital formats such as, SMPTE 274M-1995 (1920�1080 resolution, progressive or interlaced scan), SMPTE 296M-1997 (1280�720 resolution, progressive scan), as well as standard 480 progressive scan video.
Once the video signal V2 has been properly formatted for display on the display unit 208, a packetizer 212 packetizes the video signal V2 into a number of data packets 214 in the form of a data stream 215. The data stream 215 is transmitted to the display 208 by way of a link 216 at a transmission rate referred to as a link rate LR that is independent of the native stream rate Φnative of the video data but is, however, directly related to the memory clock rate Φmemory (i.e., LR=α�Φmemory). In the described embodiment, the speed, or link rate, of the link 216 can be configured to include a number of logical data channels (not shown) that can be adjusted to compensate for link conditions. For example, at 2.5 Gbps per channel, the link 216 can support SXGA 60 Hz with a color depth of 18 bits per pixel over a single channel. It should be noted that a reduction in the number of channels reduces not only the cost of interconnect, but also reduces the power consumption which is an important consideration (and desirable) for power sensitive applications such as portable devices and the like. However, by increasing the number of channels to four, the link 216 can support WQSXGA (3200�2048 image resolution) with a color depth of 24-bits per pixel at 60 Hz. or QSXGA (2560�2048) with a color depth of 18-bits per pixel at 60 Hz, without data compression. Even at the lowest rate of 1.0 Gbps per channel, only two channels are required to support an uncompressed HDTV (i.e., 1080i or 720p) data stream.
FIG. 4 shows a high-level diagram of a data stream 400 for transmission over the link 216 formed of a number of video data packets 402 and audio data packets 404 multiplexed into the single data stream 400. In this example the video data packets 402 are consistent with UXGA graphics 1280�720p video (Stream ID=1) having an associated audio in the form of the audio packets 504 (Stream ID=2). In this example, each frame line is formed of at least 1280 pixels (or 3840 sub-pixels) therefore requiring 3840 data latches be used to store a single frame line of video data within the line period τ. For example, in one embodiment, when the data stream 400 is received at the display interface 322, a group of 3840 data packets (as defined by corresponding packet headers 406) are stored in a memory that takes the form of a frame buffer or a line buffer. It should also be noted, however, that the memory can be bypassed or be absent altogether if a strictly pipelined architecture is desired.
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