Source: http://www.google.es/patents/US7793039
Timestamp: 2017-11-18 15:32:16
Document Index: 237356256

Matched Legal Cases: ['Application No. 06', '§311', '§311', '§311', '§311', '§311', '§31', '§311', '§311', '§311']

Patente US7793039 - Interface for a semiconductor memory device and method for controlling the ... - Google Patentes
A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column address and a first code. The column address...http://www.google.es/patents/US7793039?utm_source=gb-gplus-sharePatente US7793039 - Interface for a semiconductor memory device and method for controlling the interface
Número de publicación US7793039 B2
Número de solicitud US 12/349,485
También publicado como US6401167, US6868474, US7197611, US7287119, US7330952, US7330953, US7360050, US7496709, US8019958, US8205056, US8560797, US20020178324, US20050160241, US20070147143, US20070159912, US20070198868, US20070242532, US20080091907, US20090129178, US20100332719, US20120005437, US20120173810, US20120173811
Número de publicación 12349485, 349485, US 7793039 B2, US 7793039B2, US-B2-7793039, US7793039 B2, US7793039B2
Inventores Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
Citas de patentes (231), Otras citas (300), Clasificaciones (27), Eventos legales (1)
US 7793039 B2
The operations and device selection arguments are presented to the core via the PRECH and SENSE timing signals while the remaining arguments are presented as signals which have setup and hold relationships to the timing signals. Specifically, as shown in FIGS. 2-4, PRECH and PRECHBANK form signals on line 204 a in which PRECHBANK presents the “bank” argument of the precharge operation, while SENSE, SENSEBANK and SENSEROW form signals on line 204 b in which SENSEBANK and SENSEROW present the “bank” and “row” arguments, respectively, for the sense operation. Each of the key primary row timing parameters, tRP, tRAS,min and tRCD can have significant variations between devices using the same design and across different designs using the same architecture.
In this sequence, close is an alternative timing of precharge but is otherwise functionally identical. This universal sequence allows any sequence of operations needed by an application to be performed in one pass through it without repeating any step in that sequence. A control mechanism that implements the universal sequence can be said to be conflict free. A conflict free control mechanism permits a new application reference to be started for every minimum data transfer. That is, the control mechanism itself will never introduce a resource restriction that stalls the memory requestor. There may be other reasons to stall the memory requestor, for example references to different rows of the same bank may introduce bank contention, but lack of control resources will not be a reason for stalling the memory requester
Initial Bank Transaction
State Final Bank State Type Operations Performed
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49 Exhibit 2A—Conception Claim Chart for Barth II, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 23 pages.
50 Exhibit 2B—Claim Charts for Actual Reduction to Practice of Delayed Write Inventions for Claims Under Reexamination, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 36 pages.
51 Exhibit 2C—Diligence Calendar Showing Barth II Activity, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 7 pages.
52 Exhibit 2—Declaration re Craig E. Hampel, mailed on Aug. 25, 2009 with the Patent Owner's First Supplemental Reply to Office Action in Ex Parte Reexamination of U.S. Patent 7,330,952, U.S. Appl. No. 90/009,371, filed Dec. 22, 2008, 24 pages.
53 Exhibit 30: Transmittal of Communication to Third Party Requester Inter Partes Reexamination, dated May 15, 2009.
54 Exhibit 31: Office Action dated May 8, 2009, received in U.S. Appl. No. 90/009,357.
55 Exhibit 32: Office Action dated May 8, 2009, received in U.S. Appl. No. 90/009,358.
56 Exhibit 33: Chart Demonstrating Anticipation and Obviousness of the Asserted Rambus Patent Claims with U.S. Patent 5,315,755 ("Farmwald") as the Primary Reference, Exhibit to the Initial Expert Report of Vivek Subramanian, filed June 12, 2009, in the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 47 pages.
57 Exhibit 34: Chart Demonstrating Anticipation and Obviousness of the Asserted Rambus Patent Claims with High Speed DRAMS with Innovative Architectures by Ohshima et al., ("Ohshima") as the Primary Reference, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of"Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 40 pages.
58 Exhibit 35: Chart Demonstrating Anticipation and Obviousness of the Asserted Barth I Patent Claims with U.S. Patent 6,748,507 ("Kawasaki") as the Primary Reference, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 75 pages.
59 Exhibit 36: Chart Demonstrating Anticipation and Obviousness of the Asserted Barth I Patent Claims with European Patent Application 0,605,887 ("Watanabe") as the Primary Reference, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 91 pages.
60 Exhibit 37: Chart Demonstrating Anticipation and Obviousness of the Asserted Barth I Patent Claims with U.S. Patent 5,272,664 ("Alexander") as the Primary Reference, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 75 pages.
61 Exhibit 38: Chart Demonstrating Anticipation and Obviousness of the Asserted Barth I Patent Claims with U.S. Patent 5,150,467 ("Hayes") as the Primary Reference, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 80 pages.
62 Exhibit 39: Chart Demonstrating Anticipation and Obviousness of the Asserted Rambus Patent Claims with A 500-Megabyte/s Data-Rate 4.5M DRAM by Kushiyama et al. ("Kushiyama") as the Primary Reference, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 34 pages.
63 Exhibit 3—List of Exhibits, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 3 pages.
64 Exhibit 40: Chart Demonstrating Obviousness Type Double Patenting of Certain of the Asserted Barth I Patent Claims over U.S. Patent 6,584,037 ("Farmwald ′037 patent"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 18 pages.
65 Exhibit 40: Chart Demonstrating Obviousness Type Double Patenting of Certain of the Asserted Barth I Patent Claims over U.S. Patent 6,584,037 ("Farmwald '037 patent"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 18 pages.
66 Exhibit 41: Comparison of Asserted Claims of U.S. Patent 7,177,998 to Prior Art Reference U.S. Patent 6,292,903 ("Coteus"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 25 pages.
67 Exhibit 42: Comparison of Asserted Claims of U.S. Patent 7,210,016 to Prior Art Reference U.S. Patent 6,292,903 ("Coteus"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 26 pages.
68 Exhibit 43: Comparison of Asserted Claims of U.S. Patent 7,177,998 to Prior Art References U.S. Patent 6,292,903 ("Coteus") and the Hotrail Paper, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 27 pages.
69 Exhibit 44: Comparison of Asserted Claims of U.S. Patent 7,210,016 to Prior Art References U.S. Patent 6.292.903 ("Coteus") and the Hotrail Paper, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 26 pages.
70 Exhibit 45: Comparison of Asserted Claims of U.S. Patent 7,177,998 to Prior Art Reference WO99/46687 ("Sato"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 34 pages.
71 Exhibit 46: Comparison of Asserted Claims of U.S. Patent 7,210,016 to Prior Art Reference WO99/46687 ("Sato"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 24 pages.
72 Exhibit 47: Comparison of Asserted Claims of U.S. Patent 7,177,998 to Prior Art References WO99/46687 ("Sato") and U.S. Patent 6,292,903 ("Coteus") or 5,646,904 U.S. Patent ("Ohno"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 42 pages.
73 Exhibit 48: Comparison of Asserted Claims of U.S. Patent 7,210,016 to Prior Art References WO99/46687 ("Sato") and U.S. Patent 6,292,903 ("Coteus") or 5,646,904 U.S. Patent ("Ohno"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 38 pages.
74 Exhibit 49: Comparison of Asserted Claims of U.S. Patent 7,177,998 to Prior Art Reference U.S. Patent 6,226,757 ("the Intel-Ware Patent"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 22 pages.
75 Exhibit 50: Comparison of Asserted Claims of U.S. Patent 7,210,016 to Prior Art Reference U.S. Patent 6,226,757 ("the Intel-Ware Patent"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 28 pages.
76 Exhibit 51: Comparison of Asserted Claims of U.S. Patent 7,177,998 to Prior Art References U.S. Patent 6,292,903 ("Coteus") and U.S. Patent 6,226,757 ("the Intel-Ware Patent"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 27 pages.
77 Exhibit 52: Comparison of Asserted Claims of U.S. Patent 7,210,016 to Prior Art References U.S. Patent 6,292,903 ("Coteus") and U.S. Patent 6,226,757 ("the Intel-Ware Patent"), Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 25 pages.
78 Exhibit 6 Complaint filed by Patent Owner in "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same, Including Graphics Cards and Motherboards," (U.S. ITC) filed Nov. 6, 2008, 219 pages.
79 Exhibit 6: CV of Vivek Subramanian, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 3 pages.
80 Exhibit 7 Complaint in Rambus Inc. v. NVIDIA Corp., C-08-03343JCS, filed in the Northern District of California, Jul. 10, 2008, 17 pages.
81 Exhibit 7: Vivek Subramanian List of Depositions and Trial Testimonies, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 2 pages.
82 Exhibit 8 Amendment to Final Office Action dated Aug. 21, 2006, U.S. Appl. No. 11/059,216, 9 pages.
83 Exhibit 8: Vivek Subramanian List of Publications and Presentations, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 10 pages.
84 Exhibit 9 Notice of Allowability dated Oct. 4, 2007, U.S. Appl. No. 11/692,162, which issued as U.S. Patent No. 7,330,953, 7 pages.
85 Exhibit 9 Notice of Allowability dated Oct. 9, 2007, U.S. Appl. No. 11/692,159, which issued as US Patent No. 7,330,952, 6 pages.
86 Exhibit 9 Notice of Allowability, dated Jun. 19, 2007, U.S. Appl. No. 11/681,384, which issued as US Patent 7,287,119, 18 pages.
87 Exhibit 9 Notice of Allowability, dated of Oct. 4, 2007, received in U.S. Appl. No. 11/681,375, which issued as US Patent No. 7,360,050, 6 pages.
88 Exhibit 9: Vivek Subramanian Materials Considered, Exhibit to the Initial Expert Report of Vivek Subramanian, filed Jun. 12, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," U.S. International Trade Commission, Investigation No. 337-TA-661, 3 pages.
89 Exhibit A-1—Background of Robert J. Murphy regarding Patent Owner's Response to Office Action dated Aug. 17, 2009, 6 pages.
90 Exhibit AA—Handwritten Notes dated Sep. 3, 1997 through Oct. 6, 1997, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 15 pages.
91 Exhibit A—Barth et al., U.S. patent No. 7,287,119 (the ′119 patent) re Request for Inter Partes Reexamination dated May 18, 2009, 59 pages.
92 Exhibit A—Barth et al., U.S. Patent No. 7,330,952 filed Mar. 27, 2007 ("the ′952 patent"), 61 pages.
93 Exhibit A—Barth et al., U.S. Patent No. 7,330,953 ("the ′953 patent"), Request for Inter Partes Reexamination, mailed Jun. 23, 2009, of U.S. Patent No. 7,330,953, issued Feb. 12, 2008, 62 pages.
94 Exhibit A—Barth et al., U.S. Patent No. 7,360,050 ("the ′050 patent") Request for Inter Partes Examination Under 35 U.S. C. ss. 311-318 Inter Partes Reexamination, U.S. Appl. No. 95/001,205, for U.S. Patent No. 7,360,050, filed Jul. 1, 2009, 60 pages.
95 Exhibit AB—Direct Implementation & Verification Meeting dated Sep. 9, 1997, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 4 pages.
96 Exhibit AC—Handwritten Notes dated Sep. 30, 1997 through Oct. 17, 1999, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 10 pages.
97 Exhibit AD—Excerpts from Radical Source Code File "Channel C," modified Aug. 11, 1997, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with Control Nos. 90/009,369 and 90/009,370, 16 pages.
98 Exhibit AE—Steven Woo E-mail Notice that Radical 4.01 is Available dated Aug. 14, 1997, Note the Change in Write—Track, Activate—Only, and Print—Bank at the End, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 3 pages.
99 Exhibit AF—Rick Barth E-mail dated Aug. 15, 1997, Re: Radical 4.01 Resend, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
100 Exhibit AG—Rambus Inc.—Company Confidential, Project: Direct RDRAM, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 348 pages.
101 Exhibit AH—Steven Woo E-mail dated Aug. 16, 1997, "Radical 4.02 and packer 1.05," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with Control Nos. 90/009,369 and 90/009,370, 2 pp.. Exhibit Ai - Steven Woo E-mail dated Aug. 18, 1997, "Format of Radical Parameter File," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with Control Nos. 90/009,369 and 90/009,370, 3 pp.
102 Exhibit AI—Steven Woo E-mail dated Aug. 18, 1997, "Format of Radical Parameter File," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. No. 90/009,369 and 90/009,370, 3 pages.
103 Exhibit AJ—"RMC.d1.v.vv—Verilog," —Verilog Source Files for the Rambus Controller Which Manages a One-Channel-Direct Memory Subsystem, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 229 pages.
104 Exhibit AL—Fred Ware E-mail dated Sep. 5, 1997, "RMC.c2.v.vv (VHDL)—Instructions for Receiving Files," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 3 pages.
105 Exhibit AM—Steven Woo E-mail dated Sep. 10, 1997, "—called . . . " re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
106 Exhibit AN—E-mail with Unknown Sender dated Sep. 11, 1997, "Re: Hello!" re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 3 pages.
107 Exhibit AO—Steven Woo E-mail dated Sep. 12, 1997, "Re: hello!," Confidential—FTC Docket No. 9302, RF0692380, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
108 Exhibit AP—Laura Fleming E-mail dated Sep. 15, 1997, "—gfx update," (part blacked out) RH366304, R213747, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
109 Exhibit AQ—Laura Fleming E-mail dated Sep. 24, 1997, "—simulation/emulation meeting," (parts blacked out) R2963344, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
110 Exhibit AR—Don Stark E-mail dated Sep. 26, 1997, "Re: Functional Breakdown of Logic," R1790497-R1790499, combined with Don Stark E-mail with same date titled, "Standard Cell Count*Width, Count," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 8 pages.
111 Exhibit AS—E-mail (Sender blacked out) dated Oct. 3, 1997, "Re: Programs," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
112 Exhibit AT—Steven Woo E-mail dated Oct. 10, 1997, "New Version of Radical," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
113 Exhibit AU—"Rambus Direct Series Technical Description, version 0.6," Rambus Confidential Trade Secret Information, Modified Aug. 12, 1997, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 280 pages.
114 Exhibit AV—"Power Control of a Synchronous Memory Device," Rambus Confidential, Modified Aug. 22, 1997, R2531794-R2531803, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 11 pages.
115 Exhibit AW—Fred Ware E-mail dated Sep. 13, 1997, "64M Direct Datasheet 0.6," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
116 Exhibit AX—"Direct Logical Application," Rambus Confidential, Modified Sep. 14, 1997, R2703435-R2703451, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 18 pages.
117 Exhibit AY—"Direct Serie Technical Description: Direct Logical Application," Rambus Confidential, Modified on Sep. 14, 1997, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 68 pages.
118 Exhibit AZ—Rambus Inc., "Direct Rdram 64/72-Mbit (256K×16/18×16d)—Advance Information," Last Modified Sep. 15, 1997, R08395-R08443, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 50 pages.
119 Exhibit B—"Rambus Direct Series Technical Description, version 0.5," (date blacked out), R4382681-R4382981, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 302 pages.
120 Exhibit BA—Rambus Confidential, "5.0 Interconnect," Modified Sep. 16, 1997, R2531947-R2531976, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 31 pages.
121 Exhibit BB—Fred Ware E-mail sent Sep. 19, 1997, "DataSheet," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
122 Exhibit BC—Rambus Confidential, "ET—Interface Overview," Modified Sep. 22, 1997, R2535135-R2535155, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 22 pages.
123 Exhibit BD—Rambus Inc., "Direct RDRAM, 64/72-Mbit (256K×16/18×16d)—Advance Information," Last Modified Oct. 2, 1997, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 49 pages.
124 Exhibit BI—Barth E-mail sent Oct. 1, 1997, (Subject blacked out), R66634251, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
125 Exhibit BM—Exhibit (JSC1) Excerpts from Radical Source Code File "genmaster.C," (date blacked out), re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 8 pages.
126 Exhibit BN—Exhibit (JSC2) Excerpts from Radical Source Code File "rb2master.C," (date blaced out), re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 8 pages.
127 Exhibit BO—Exhibit (JSC3) Excerpts from Radical Source Code File "rb2master.H," (date blacked out), re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
128 Exhibit BP—Exhibit (JSC4) Excerpts from Radical Source Code File "tile.out.save," (date blacked out), re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 7 pages.
129 Exhibit BQ—Attorney Client Privileged Work Product from genmaster.C (date blacked out), re Ex Parte Reexamination of U.S. Patent Nos. 7,330,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 17 pages.
130 Exhibit B—Ryan et al. ("Ryan"), U.S. Patent No. 6,044,429, filed on Jul. 10, 1997, 19 pages.
131 Exhibit B—U.S. Patent No. 6,044,429, Ryan et al. ("Ryan"), Request for Inter Partes Examination Under 35 U.S.C. §§311-318, Re U.S. Patent No. 7,360,050, U.S. Appl. No. 95/001,205 filed on Jul. 1, 2009, 19 pages.
132 Exhibit C, Tab 1—U.S. Patent No. 6,088,774 to Gillingham ("Gillingham") filed Sep. 19, 1997, 16 pages.
133 Exhibit C, Tab 1—U.S. Patent No. 6,088,774 to Gillingham ("Gillingham") Request for Inter Partes Examination Under 35 U.S.C. §§311-318, Re U.S. Patent No. 7,360,050, U.S. Appl. No. 95/001,205, filed on Jul. 1, 2009, 16 pages.
134 Exhibit C, Tab 2—U.S. Appl. No. 60/026,594 filed Sep. 20, 1996 (incorporated by reference in Gillingham), in Request for Inter Partes Examination Under 35 U.S.C. §§311-318 Re U.S. Patent No. 7,360,050, U.S. Appl. No. 95/001,205, filed on Jul. 1, 2009,12 pages.
135 Exhibit C, Tab 2—U.S. Appl. No. 60/026,594, filed Sep. 20, 1996, incorporated by Gillingham, 12 pages.
136 Exhibit C, Tab 3—U.S. Appl. No. 60/055,349 filed Aug. 11, 1997 (incorporated by reference in Gillingham) in Request for Inter Partes Examination Under 35 U.S.C. §§311-318 Re U.S. Patent No. 7,360,050, U.S. Appl. No. 95/001,205, filed on Jul. 1, 2009, 87 pages.
137 Exhibit C, Tab 3—U.S. Appl. No. 60/055,349 filed Aug. 11, 1997, incorporated by Gillingham, 87 pages.
138 Exhibit C, Tab 4—U.S. Appl. No. 60/057,092 filed Aug. 27, 1997 (incorporated by reference in Gillingham) in Request for Inter Partes Examination Under 35 U.S.C. §§311-318 Re U.S. Patent No. 7,360,050, U.S. Appl. No. 95/001,205, filed on Jul. 1, 2009, 345 pages.
139 Exhibit C, Tab 4—U.S. Appl. No. 60/057,092 filed Aug. 27, 1997, incorporated by Gillingham, 345 pages.
140 Exhibit C—Greg Davis E-mail (date blacked out), "Direct-Summary.Txt, Revision 2.11," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 8 pages.
141 Exhibit D, Tab 1—Inagaki, Y., JP 57-210495, Applicant NEC Corp., published Dec. 24, 1982 ("Inagaki"), in Request for Inter Partes Reexamination mailed Jun. 23, 2009, of U.S. Patent No. 7,287,119, issued Oct. 23, 2007, 9 pages.
142 Exhibit D, Tab 2—English translation of Inagaki, Y., JP 57-210495, Applicant NEC Corp., published Dec. 24, 1982 ("Inagaki"), in Request for Inter Partes Reexamination mailed Jun. 23, 2009, of U.S. Patent No. 7,287,119, issued Oct. 23, 2007, 16 pages.
143 Exhibit D—Greg Davis E-mail (date blacked out), "IT3 Strawman," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 10 pages.
144 Exhibit E—Fred Ware E-mail (date blacked out), "Further Feedback on 0.04 Proposal," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 3 pages.
145 Exhibit E—Kushiyama et al., "A 500-Megabyte/s Data-Rate 4.5M DRAM," ("Kushiyama"), in Request for Inter Partes Reexamination mailed Jun. 23, 2009 of U.S. Patent No. 7,287,119, issued Oct. 23, 2007, 12 pages.
146 Exhibit F, Tab 1—U.S. Patent No. 6,226,723, Gustavson, et al. ("Gustavson"), in Request for Inter Partes Reexamination mailed Jun. 23, 2009 of U.S. Patent No. 7,287,119, issued Oct. 23, 2007, 88 pages.
147 Exhibit F, Tab 2—Gustavson, D., et al., "Packetized Communicated for a High Performance Random Access Memory System," U.S. Appl. No. 60/026,419, filed Sep. 20, 1996, 13 pages.
148 Exhibit F, Tab 2—U.S. Appl. No. 60/026,419 filed Sep. 1996, incorporated by reference in Gustavson, in Request for Inter Partes Reexamination mailed Jun. 23, 2009 of U.S. Patent No. 7,287,119, Oct. 23, 2007, 13 pages.
149 Exhibit F, Tab 3—Gustavson, D., et al. "Packets for a High Performance Random Access Memory System," U.S. Appl. No. 60/026,896 filed Sep. 20, 1996, re Request for Inter Partes Reexamination filed Jul. 1, 2009, for U.S. Patent 7,287,119, U.S. Appl. No. 95/001,189, 24 pages.
150 Exhibit F, Tab 3—U.S. Appl. No. 60/026,896 filed Sep. 1996, incorporated by reference in Gustavson, Request for Inter Partes Reexamination mailed Jun. 23, 2009 of U.S. Patent No. 7,287,119, issued Oct. 23, 2007, 24 pages.
151 Exhibit F—David Roberts E-mail sent Aug. 6, 1997, "MTD 64MD Project Review: Aug. 1997," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed December 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 5 pages.
152 Exhibit G—Michael Ching E-mail dated Nov. 15, 1999, "Intel 820 Product Launch;" re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 4 pages.
153 Exhibit G—Oshima et al. ("Oshima"), "High Speed DRAMs with Innovative Architectures," Aug. 1994, re Request for Inter Partes Reexamination dated Jul. 1, 2009, U.S. Appl. No. 95/001,196 for U.S. Patent 7,330,952, 14 pages.
154 Exhibit G—U.S. Patent No. 7,287,109 issued Oct. 23, 2007, to Barth et al. ("Barth ′109"), 47 pages.
155 Exhibit H, Tab 1—U.S. Patent No. 5,966,343 to Thurston ("Thurston"), Request for Inter Partes Reexamination mailed Jun. 23, 2009, of U.S. Patent No. 7,330,952 issued Feb. 12, 2008, 20 pages.
156 Exhibit H, Tab 2—U.S. Appl. No. 60/034,470 filed Jan. 2, 1997, to which Thurston claims priority, Request for Inter Partes Reexamination mailed Jun. 23, 2009 of U.S. Patent No. 7,330,952, issued Feb. 12, 2008, 37 pages.
157 Exhibit H, Tab 3—U.S. Appl. No. 60/021,567, incorporated by reference by Thurston, Request for Inter Partes Reexamination mailed Jun. 23, 2009 of U.S. Patent No. 7,330,952 issued Feb. 12, 2008, 75 pages.
158 Exhibit H, Tab 4—U.S. Appl. No. 60/021,565, incorporated by reference by Thurston, Request for Inter Partes Reexamination mailed Jun. 23, 2009 of U.S. Patent No. 7,330,952, issued Feb. 12, 2008, 72 pages.
159 Exhibit H, Tab 5—U.S. Appl. No. 60/021,524, incorporated by reference by Thurston, Request for Inter Partes Reexamination mailed Jun. 23, 2009 of U.S. Patent No. 7,330,952, issued Feb. 12, 2008, 74 pages.
160 Exhibit H—Ohshima et al. ("Ohshima"), "High Speed DRAMs with Innovative Architectures," Aug. 1, 1994, 14 pages.
161 Exhibit H—Rambus Inc.—Company Confidential, Project: Direct RDRAM, Rev. 0.2, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 253 pages.
162 Exhibit I, Tab 1—U.S. Patent No. 5,966,343 to Thurston ("Thurston") issued Oct. 12, 1999, 20 Pages.
163 Exhibit I, Tab 2—Thurston, P., "Variable Latency Memory Circuit," U.S. Appl. No. 60/034,470 filed Jan. 2, 1997, re Request for Inter Partes Reexamination filed Jul. 1, 2009, for U.S. Patent 7,287,119, U.S. Appl. No. 95/001,189, 37 pages.
164 Exhibit I, Tab 2—U.S. Appl. No. 60/034,470 filed Jan. 2, 1997. Thurston claims priority to the ′470 application, 37 pages.
165 Exhibit I, Tab 3—Nakamura et al., "DRAM Architecture with Aligned Data Storage and Bond Pads," U.S. Appl. No. 60/021,565 filed Jul. 11, 1996, re Request for Inter Partes Reexamination filed Jul. 1, 1996, for U.S. Patent 7,287,119, U.S. Appl. No. 95/001,189, 72 pages.
166 Exhibit I, Tab 3—U.S. Appl. No. 60/021,565, filed Jul. 11, 1996, incorporated by reference by Thurston, 72 pages.
167 Exhibit I, Tab 4—Nakamura et al., "Four Bit Pre-Fetch SDRAM Column Select Architecture," U.S. Appl. No. 60/021,567 filed Jul. 11, 1996, re Request for Inter Partes Reexamination filed Jul. 1, 2009, for U.S. Patent 7,287,119, U.S. Appl. No. 95/001,189, 75 pages.
168 Exhibit I, Tab 4—U.S. Appl. No. 60/021,567, filed Jul. 11, 1996, incorporated by reference by Thurston, 75 pages.
169 Exhibit I, Tab 5—U.S. Appl. No. 60/021,524, filed Jul. 11, 1996, incorporated by reference by Thurston, 74 pages.
170 Exhibit I—U.S. Patent No. 5,430,676 to Ware et al. ("Ware"), Request for Inter Partes Reexamination mailed June 23, 2009, of U.S. Patent No. 7,330,952, issued Feb. 12, 2008, 27 pages.
171 Exhibit J—"RMC.d1.v.vv—Verilog" —Directory Containing the Verilog Source Files for the Rambus Memory Controller Which Manages a One-Channel-Direct Memory Subsystem, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 130 pages.
172 Exhibit J—JEDEC Standard No. 21-C, Release 4, Nov. 1993 ("the JEDEC Standard"), Request for Inter Partes Reexamination mailed Jun. 23, 2009 of U.S. Patent No. 7,330,952, issued Feb. 12, 2008, 186 pages.
173 Exhibit J—U.S. Patent No. 5,430,676 to Ware et al. ("Ware"), issued Jul. 4, 1995, 27 pages.
174 Exhibit K—Claim Chart for claims 1-28 of the ′953 patent based on Ryan, with additional reference to Gillingham, Gustavsom, Inagaki, and Kushiyama, Request for Inter Partes Reexamination, mailed Jun. 23, 2009, of U.S. Patent No. 7,330,953, issued Feb. 12, 2008, 44 pages.
175 Exhibit K—JEDEC Standard No. 21-C, Release 4, Nov. 1993 ("The JEDEC Standard"), 186 pages.
176 Exhibit K—Steven Woo E-mail, "Radical 3.0," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
177 Exhibit K—U.S. Patent No. 5,568,445 filed Mar. 2, 1995, to Park et al. ("Park") issued on Oct. 22, 1996, 21 pages.
178 Exhibit K—U.S. Patent No. 7,287,109 to Barth et al. ("Barth ′109") re Request for Inter Partes Reexamination filed Jul. 1, 2009, for U.S. Patent 7,360,050, U.S. Appl. No. 95/001,205, 47 pages.
179 Exhibit L—"8-MBIT (512K×16, 1024K×8) SmartVoltage Boot Block Flash Memory Family product preview" ("Intel Datasheet") dated Sep. 1995 re Request for Inter Partes Reexamination for U.S. Patent 7,330,952, 79 pages.
180 Exhibit L—Claim Chart for Claims 1-23 of the ′119 patent based on Ryan with additional reference to Gillingham, Gustavson, Inagaki, and Kushiyama, in Request for Inter Partes Reexamination dated Sep. 29, 2009, 30 pages.
181 Exhibit L—Claim chart for claims 1-28 of the ′953 patent based on Gilllingham, with additional reference to Ohshima and Ryan, Request for Inter Partes Reexamination, mailed Jun. 23, 2009, of U.S. Patent No. 7,330,953, issued Feb. 12, 2008, 59 pages.
182 Exhibit L—Claim Chart for claims 1-31 based on the ′050 patent based on Ryan, with additional reference to Gillingham, Gustavson, Inagaki, Kushiyama, re Request for Inter Partes Reexamination filed Jul. 1, 2009, for U.S. Patent 7,360,050, U.S. Appl. No. 95/001,205, 31 pages.
183 Exhibit L—Rambus Inc., "Direct RDRAM 64/72-Mbit (4M×16/18)—Advance Information," last modified Jul. 14, 1997, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 50 pages.
184 Exhibit M—Claim Chart for Claims 1-20 and 23 of the ′119 patent based on Gillingham with additional reference to Ohshima, in Request for Inter Partes Reexamination dated Sep. 29, 2009, 42 pages.
185 Exhibit M—Claim Chart for claims 1-26, 28, and 30 of the ′050 patent based on Gillingham, with additional reference to Ohshima and Ryan, re Request for Inter Partes Reexamination filed Jul. 1, 2009, for U.S. Patent 7,360,050, U.S. Appl. No. 95/001,205, 32 pages.
186 Exhibit M—Claim chart for claims 1-28 based on the ′952 patent based on Ryan, with additional reference to Gillingham, Gustavson, Inagaki, Kushiyama, Park, and the Intel Datasheet, re Request for Inter Partes Reexamination Sep. 29, 2009, 29 pages.
187 Exhibit M—Claim chart for claims 1-28 of the '953 patent based on Thurston, with additional reference to Gustavson, Inagaki, and Ryan, Request for Inter Partes Reexamination, mailed Jun. 23, 2009, of U.S. Patent No. 7,330,953, issued Feb. 12, 2008, 46 pages.
188 Exhibit M—Rambus Inc., Notice of Sending of New "Advanced" Version, 64/72M Direct RDRAM data sheet, FTC Docket No. 9302, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 6 pages.
189 Exhibit N—Claim chart for claims 1-28 of the ′952 patent based on Gillingham, with additional reference to Ohshima, Park, and the Intel Datasheet, re Request for Inter Partes Reexamination Sep. 29, 2009, 38 pages.
190 Exhibit N—Claim chart for claims 1-28 of the ′953 patent based on Ware, with additional reference to Gustavson and Ohshima, Request for Inter Partes Reexamination, mailed Jun. 23, 2009, of U.S. Patent No. 7,330,953, issued Feb. 12, 2008, 37 pages.
191 Exhibit N—Claim Chart for claims 1-31 of the '050 patent based on Thurston, with additional reference to Gustavson, Inagaki, the JEDEC Standard, Ryan, and Ware, re Request for Inter Partes Reexamination filed Jul. 1, 2009, for U.S. Patent 7,360,050, U.S. Appl. No. 95/001,205, 29 pages.
192 Exhibit N—Claim Chart for Claims 7 and 10-12 of the ′119 patent based on Barth '109 re Request for Inter Partes Reexamination dated Sep. 29, 2009, 7 pages.
193 Exhibit O—Claim Chart for Claims 1-23 of the ′119 patent based on Thurston with additional reference to Inagaki, Gustavson, and Kushiyama, in Request for Inter Partes Reexamination dated Sep. 29, 2009, 28 pages.
194 Exhibit O—Claim chart for claims 1-28 of the ′952 patent based on Thurston, with additional reference to Gustavson, Inagaki, Ryan, Park, and the Intel Datasheet, re Request for Inter Partes Reexamination Sep. 29, 2009, 28 pages.
195 Exhibit O—Claim chart for claims 1-28 of the ′953 patent based on the JEDEC Standard, with additional reference to Ware, Gustavson, and Inagaki, Request for Inter Partes Reexamination, mailed Jun. 23, 2009, of U.S. Patent No. 7,330,953, issued Feb. 12, 2008, 40 pages.
196 Exhibit O—Claim Chart for claims 1-31 of the ′050 patent based on Ware, with additional reference to Gustavson and Ohshima, re Request for Inter Partes Reexamination filed Jul. 1, 2009, for U.S. Patent 7,360,050, U.S. Appl. No. 95/001,205, 27 pages.
197 Exhibit P—Claim Chart for Claims 1-23 of the ′119 patent based on Ware with additional reference to Gustavson and Ohshima, in Request for Inter Partes Reexamination dated Sep. 29, 2009, 25 pages.
198 Exhibit P—Claim chart for claims 1-28 of the ′952 patent based on Ware, with additional reference to Gustavson, Ohshima, Park, and the Intel Datasheet re Request for Inter Partes Reexamination Sep. 29, 2009, 28 pages.
199 Exhibit P—Claim Chart for claims 1-31 of the ′050 patent based on the JEDEC Standard, with additional reference to Ware, Gustavson, and Inagaki, re Request for Inter Partes Reexamination filed Jul. 1, 2009, for U.S. Patent 7,360,050, U.S. Appl. No. 95/001,205, 29 pages.
200 Exhibit P—File History of the ′953 patent, Request for Inter Partes Reexamination, mailed Jun. 23, 2009, of U.S. Patent No. 7,330,953, issued Feb. 12, 2008, 275 pages.
201 Exhibit P—John Dillon E-mail sent Aug. 5, 1997, "Update 8/5," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 3 pages.
202 Exhibit Q, The complaint filed by Patent Owner in "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same Including Graphics Cards and Motherboards," (U.S. ITC) filed in Apr. 24, 2009 Request for Inter Partes Reexamination Under 35 USC §§31-318 re 6,470,405, 216 pages.
203 Exhibit Q—Claim Chart for Claims 1-23 of the ′119 patent based on the JEDEC Standard with additional reference to Ware, Gustavson, and Inagaki, re Request for Inter Partes Reexamination dated Sep. 29, 2009, 26 pages.
204 Exhibit Q—Claim chart for claims 1-28 of the ′952 patent based on the JEDEC Standard, with additional reference to Ware, Gustavson, Inagaki, Park, and the Intel Datasheet, re Request for Inter Partes Reexamination Sep. 29, 2009, 26 pages.
205 Exhibit Q—Claim chart for claims 22, 23, and 27 of the ′050 patent based on Barth ′109 re Request for Inter Partes Reexamination filed Jul. 1, 2009, for U.S. Patent 7,360,050, U.S. Appl. No. 95/001,205, 6 pages.
206 Exhibit Q—John Dillon E-mail sent Aug. 6, 1997, "Update 8/6," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
207 Exhibit R, The first amended complaint filed by Patent Owner in Rambus, Inc. v. Nvidia Corporation, 3:08-cv-03343-Si (N. D. Cal.) filed Apr. 24, 2009 in Request for Inter Partes Reexamination under 35 USC §§311-318 re 6,470,405, 18 pages.
208 Exhibit R—John Dillon E-mail sent Aug. 7, 1997, "—Meeting 8/7," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 2 pages.
209 Exhibit S, Rambus Inc.'s Opening Brief on Disputed Claim Terms dated Mar. 2, 2009, in the Matter of: "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same", United States International Trade Commission Investigation No. 337-661, Request for Inter Partes Reexamination under 35 USC §311-318 re 7,287,109, 65 pages.
210 Exhibit S, Rambus Inc.'s Opening Brief on Disputed Claim Terms, filed Mar. 2, 2009, In the matter of: "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," United States International Trade Commission Investigation No. 337-661, Request for Inter Partes Reexamination under 35 USC §§311-318 re 6,470,405, 65 pages.
211 Exhibit S—Handwritten Notes dated Aug. 8-Oct. 16, 1997, R3418717-R3418735, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 20 pages.
212 Exhibit S—The complaint filed by Patent Owner in "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same, Including Graphics Cards and Motherboards," re Request for Inter Partes Reexamination dated Jul. 1, 2009, U.S. Appl. No. 95/001,189 for U.S. Patent 7,287,119, 216 pages.
213 Exhibit S—The complaint filed by Patent Owner in "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same, Including Graphics Cards and Motherboards," re Request for Inter Partes Reexamination Sep. 29, 2009, 216 pages.
214 Exhibit T—Handwritten Notes dated Jul. 10-Sep. 30, 1997, R19224893-R19224977, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 86 pages.
215 Exhibit T—The first amended complaint filed by Patent Owner in Rambus Inc. v. NVIDIA Corporation, 3:08-cv-03343-SI (N. D. Cal.) re Request for Inter Partes Reexamination Sep. 29, 2009, 18 pages.
216 Exhibit T—The first amended complaint filed by Patent Owner in Rambus, Inc. v. NVIDIA Corporation, 3:08-cv-03343-SI (N. D. Cal.) re Request for Inter Partes Reexamination dated Jul. 1, 2009 with U.S. Appl. No. 95/001,189 for U.S. Patent 7,287,119, 18 pages.
217 Exhibit U—Dave Roberts E-mail sent Sep. 2, 1997, "MTD 64MD Project Review: Sep. 1997," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 6 pages.
218 Exhibit U—Rambus Inc.'s Opening Brief on Disputed Claim Terms, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," United States International Trade Commission, Investigation No. 337-661 re Request for Inter Partes Reexamination dated Jul. 1, 2009 with U.S. Appl. No. 95/001,189 for U.S. Patent 7,287,119, 65 pages.
219 Exhibit U—Rambus Inc.'s Opening Brief on Disputed Claim Terms, In the Matter of: "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," United States International Trade Commission, Investigation No. 337-661, re Request for Inter Partes Reexamination Sep. 29, 2009, 65 pages.
220 Exhibit V—John Privitera E-mail sent Sep. 3, 1997, "Verification Project Review," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 3 pages.
221 Exhibit W—Dave Roberts E-mail sent Oct. 6, 1997, "MTD 64MD Project Review: Oct. 1997," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 7 pages.
222 Exhibit X—Handwritten Notes dated Aug. 5-Oct. 6, 1997, R19232609-R19232629, Collected Nov. 2008, re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 22 pages.
223 Exhibit Y—John Dillon E-mail sent Aug. 7, 1997, "Package AR Update 8/7," re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 3 pages.
224 Exhibit Z—Handwritten Notes dated Aug. 7-Oct. 10, R19227628-R19227632, Collected Nov. 2008 re Ex Parte Reexamination of U.S. Patent Nos. 7,330,953 and 7,360,050 Barth et al. dated Aug. 19, 2009, both filed Dec. 23, 2008, with U.S. Appl. Nos. 90/009,369 and 90/009,370, 6 pages.
225 Feb. 20, 2009 Order Granting Ex Parte Reexamination re 7,287,119 in Office Communication, 9 pages.
226 Fujiwara, A. et al., "A 200MHz 16Mbit Synchronous DRAM with Block Access Mode," 1994 Symposium on VLSI Circuits Digest of Technical Papers, IEEE, 1994, 2 pages.
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229 Haining, T.R., et al., "Management Policies for Non-Volatile Write Caches," Int'l Conf. on Performane, Computing, and Communications, Feb. 10-12, 1999, pp. 321-328.
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243 Non-Final Office Action in Ex Parte Reexamination for 7,360,050 dated Apr. 10, 2009, 8 pages.
244 Non-Final Office Action mailed Apr. 10, 2009 in Ex Parte Reexamination for U.S. Patent No. 7,330,952, 8 pages.
245 Non-Final Office Action received in Ex Parte Reexamination in 7,287,119, dated Apr. 29, 2009, 10 pages.
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Clasificación de EE.UU. 711/105, 711/167
Clasificación internacional G11C7/10, G11C7/12, G06F12/00, G11C11/4096
Clasificación cooperativa G11C11/4093, G11C7/1006, G11C11/4076, G11C11/4096, G11C11/40611, G11C8/18, G11C8/12, G11C7/12, G11C7/22, G11C2207/2218, G11C11/406
Clasificación europea G11C7/22, G11C8/18, G11C11/406E, G11C11/4076, G11C8/12, G11C11/406, G11C11/4093, G11C7/12, G11C7/10L, G11C11/4096