Source: http://www.google.com/patents/US6807120?dq=Frischling
Timestamp: 2017-12-12 22:30:27
Document Index: 273079089

Matched Legal Cases: ['art 1', 'art 2', 'art 3', 'art 4', 'art 1', 'art 2', 'art 3', 'arts 1']

Patent US6807120 - Dynamic random access memory (DRAM) capable of canceling out complementary ... - Google Patents
A semiconductor device includes a first region having first bit lines, first word lines and first memory cells; a second region having second bit lines, second word lines and second memory cells; a third region having sense amplifiers placed between the first region and the second region; a first conductive...http://www.google.com/patents/US6807120?utm_source=gb-gplus-sharePatent US6807120 - Dynamic random access memory (DRAM) capable of canceling out complementary noise developed in plate electrodes of memory cell capacitors
Publication number US6807120 B2
Application number US 10/309,180
Also published as US6501672, US6944080, US7274613, US20030112682, US20050030783, US20050270889, US20070297257
Publication number 10309180, 309180, US 6807120 B2, US 6807120B2, US-B2-6807120, US6807120 B2, US6807120B2
Inventors Tomonori Sekiguchi, Kazuhiko Kajigaya, Katsutaka Kimura, Riichiro Takemura, Tsugio Takahashi, Yoshitaka Nakamura
Patent Citations (8), Referenced by (10), Classifications (39), Legal Events (10)
US 6807120 B2
A semiconductor device includes a first region having first bit lines, first word lines and first memory cells; a second region having second bit lines, second word lines and second memory cells; a third region having sense amplifiers placed between the first region and the second region; a first conductive layer being over the first region; a second conductive layer being over the second region; and a connecting layer, being over the third region, which electrically connects the first conductive layer with the second conductive layer. The sense amplifiers amplify differences in voltage between the first bit lines and the second bit lines. Each of the first memory cells includes a first storage capacitor having an electrode connected to the first conductive layer. Each of the second memory cells includes a second storage capacitor having an electrode connected to the second conductive layer.
a first region having a plurality of first bit lines, a plurality of first word lines and a plurality of first memory cells;
a second region having a plurality of second bit lines, a plurality of second word lines and a plurality of second memory cells;
a third region having a plurality of sense amplifiers placed between said first region and said second region;
a first conductive layer being over said first region;
a second conductive layer being over said second region; and
a connecting layer, being over said third region, which electrically connects said first conductive layer with said second conductive layer,
wherein said sense amplifiers amplify differences in voltage between said first bit lines and said second bit lines,
wherein each of said first memory cells includes a first storage capacitor having an electrode connected to said first conductive layer, and
wherein each of said second memory cells includes a second storage capacitor having an electrode connected to said second conductive layer.
2. A semiconductor device according to claim 1, wherein said connecting layer is formed of the same material as said first conductive layer and said second conductive layer.
This application is a Continuation of nonprovisional application Ser. No. 09/656,477, filed Sep. 6, 2000, now U.S. Pat. No. 6,501,672.
According to investigations subsequent to the completion of the present invention, it has been revealed that Japanese Patent Application Laid-Open No. Sho 59(1984)-2365 (hereinafter called “prior art 1”), Japanese Patent Application Laid-Open No. Sho 60(1985)195795 (hereinafter called “prior art 2”), Japanese Patent Application Laid-Open No. Sho 60(1985)-211871 (hereinafter called “prior art 3”), and Japanese Patent Application Laid-Open No. Hei 9(1997)-135009 (hereinafter called “prior art 4”) have existed as those considered to be related to the present invention to be described later.
According to the prior art 1, a problem developed due to the fact that a source voltage changed according to the operation of a peripheral circuit is not transferred to the entirety of a plate electrode, is solved by laying out voltage-supplying power or source wires at plural points of the plate electrode and uniformizing the potential of the plate electrode on the whole according to the change in potential due to the operation of the peripheral circuit. According to the prior art 2, a problem developed due to the fact that a relative potential change differs from a change in potential on the substrate side, is solved by connecting the two plate electrodes through a resistor having a time constant associated with the change in potential on the substrate side. In the prior art 3 on the other hand, the problem that a change in potential supplied to each plate electrode from its corresponding bit line through a storage capacitor would lead to the application of a voltage to the plate electrode, is solved by reducing the resistance of each wire connected to the plate electrode.
It has been desirable to reduce the cost of a dynamic RAM (hereinafter called simply “DRAM”). To this end, a reduction in chip size is most effective. A scale-down has heretofore been pushed forward to reduce a memory cell size. It is however necessary to change even an operating mode or system of a memory array and thereby make a further reduction in cell size. By changing the operating mode of the memory array from a two-intersection type to a one-intersection type, the cell size can ideally be reduced to 75% by using the same design rule. However, the one-intersection type memory array has a problem in that array noise placed on each bit line or the like is high, as compared with the two-intersection type memory array. Thus, a product application becomes difficult unless it is solved.
Therefore, a discussion has been made of noise developed when the memory cells employed in the conventional two-intersection type are used as they are to configure the one-intersection type memory array. Thus, it has been revealed that an unneglible parasitic capacity has existed between each bit line and the plate electrode when the memory cell is a COB (Capacitor over Bit-line) cell, so-called deep hole STC (such cylinder shape that a lower electrode SN of each capacitor is formed on an inner wall of a hole defined in an interlayer dielectric) except for the MOS capacity. Even if the techniques described in the prior arts 1 to 3 are used as they are to perform the supply of a voltage, it has been found out that the array noise placed on the bit line, could not be reduced.
Now consider, as one example, where a word line WL0 is activated so that a high-level (H) signal appears on a bit line BL1T alone and a low-level (L) signal is read out onto other bit lines BL0T and BL2T and the like. Further, the high-level (H) signal developed on the bit line BL1T is regarded as small due to the reason such as the leakage or the like of an electrical charge for holding information in each memory cell. When a sense amplifier is activated, such bit lines BL0T/B, BL2T/B, etc. that signals greatly appear between complementary bit lines, are amplified fast in signal.
In the present embodiment, memory arrays are divided into four as a whole although not restricted in particular. An address input circuit, a data input/output circuit, an input/output interface circuit comprising a row of bonding pads, and a power circuit including a step-down and a de-boosting circuit, etc. are provided in central portions 14 with being divided into the left and right with respect to the longitudinal direction of a semiconductor chip. Memory array controllers (AC) 11 and main word drivers (MWD) 12 are respectively placed in portions contiguous to the memory arrays located on both sides of these central portions 14. Each of the memory array controllers 11 comprises a control circuit for driving a sub word select line and a sense amplifier, and a main amplifier. In each individual memory arrays comprised of four divided into two on both sides and two up and down with respect to the longitudinal direction of the semiconductor chip as described above, column decoder areas (YDC) 13 are provided in upper and lower central portions with respect to the longitudinal direction of the semiconductor chip.
In each memory array referred to above, the main word driver area 12 forms or produces a signal for selecting a main word line which extends so as to penetrate one memory array corresponding to it. Sub-word select line drivers for sub-word selection are also provided in the main word driver areas 12. As will be described later, each sub-word select line driver extends in parallel to the main word line and produces a signal for selecting a sub-word select line. The column decoder 13 forms or produces a signal for selecting a column select line extended so as to penetrate one memory array corresponding to it.
Each of the memory arrays is divided into a plurality of memory cell arrays (hereinafter called “sub arrays”) 15. Th sub array 15 is formed so as to be surrounded by sense amplifier areas 16 and sub-word driver areas 17 as illustrated by its enlarged view. Portions where the sense amplifier areas 16 and the sub-word driver areas 17 intersect respectively, are called intersecting areas (cross areas) 18. A sense amplifier provided for the sense amplifier area 16 comprises a latch circuit having a CMOS configuration and is defined as a so-called one intersection system or open bit line system which amplifies signals on complementary bit lines extended to both sides of each sense amplifier with the sense amplifier as the center.
Since the 1024 bit lines are provided for each sub array 15, memory cells corresponding to about 4K are connected in a word line direction. Since the 512 sub-word lines are provided, memory cells corresponding to 512×32=16K are connected in the bit-line direction. Thus, one memory array has a storage capacity of 4K×16K=64 Mbits, and the four memory arrays have a storage capacity of 4×64M=256 Mbits as the whole of a memory chip 10.
In the present application, the term “MOS” is understood as a metal oxide semiconductor configuration originally called for simplicity or brevity. However, the recent generally-named MOSs include those obtained by changing a metal of essential portions of a semiconductor device to an electrical conductor such as polysilicon which does not belong to the metal and changing oxide to another insulator. Also CMOSs are now understood as having a wide technical meaning corresponding to a change in how to grasp the MOSs referred to above. MOSFETs are also similarly taken as the meaning including such a wide construction as substantially taken as an insulated-gate field effect transistor without being understood in a narrow sense. CMOSs, MOSFETs, etc. employed in the present invention follow general naming and include even transistors.
This is similar even to the sub-word drivers SWD. 512 sub-word lines WL provided in the sub array MAT0 are divided 256 by 256, which in turn are connected to their corresponding 256 sub-word drivers SWD of the sub-word driver arrays SWDA placed on both sides of the sub array MAT0. In the present embodiment, the-sub-word drivers SWD provided two by two are dispersively placed with two sub-word lines WL as each pair. Namely, two sub-word drivers are placed on the one-end side (on the upper side in the drawing) of the sub array MAT0 with the sub-word lines corresponding to two memory cells which share the use of a portion connected to each bit line, as one pair, whereas two sub-word drivers are placed on the other end side (on the lower side in the drawing) of the sub array MAT0 with the similar two sub-word lines adjacent thereto as one pair.
Although not shown in the drawing, the sub-word drivers SWD form or produce signals for selecting sub-word lines for sub arrays provided on both sides with the sub-word driver array SWDA in which the sub-word drivers are formed, interposed therebetween. Thus, the sub-word drivers SWD can be dispersively placed with satisfactory efficiency in association with the sub-word lines each formed so as to coincide with an array pitch of each memory cell, and the operation of selecting each sub-word line WL can be carried out at high speed.
Power switches MOSFETs Q3 and Q4 are respectively electrically connected to the common source lines CSN and CSP. Although not restricted in particular, a ground potential supply line VSSA is given or offered to the common source line CSN to which the sources of the N channel amplifying MOSFETs Q5 and Q6 are electrically connected, by the N channel power switch MOSFET Q3 dispersively laid out in such a sense amplifier area. The common source line CSP to which the sources of the P channel amplifying MOSFETs Q7 and Q8 are electrically connected, is provided with the N channel power MOSFET Q4 to supply and operating voltage VDD thereto.
As shown in FIG. 14, the local input/output lines SIO0T and SIO0B, and SIO1T and SIO1B extend over the sense amplifier arrays aligned along the extension direction of the main word lines. Signals amplified through sub amplifier circuits are transferred to main amplifiers provided in main word driver MWD units through main input/output lines each extended in the direction identical thereto. In one memory array obtained by dividing the memory chip into four on the memory chip, for example, the signals are outputted in parallel in 16-bit units according to the number of divisions of the sub array. The memory arrays divided into four respectively constitute memory banks as will be described later.
As to wiring for the substrate bias voltage VBB, a wiring layer M3 corresponding to the same layer as column selection lines YS is used in the longitudinal direction in FIG. 11 to place wires on each sub-word driver array SWDA and sub array MAT. A wiring layer M2 corresponding to the same layer as main word lines MWL is used in the longitudinal direction to thereby place wires on the sense amplifier array SAA and the sub arrays. On the sub arrays, these vertically and horizontally-extending wires are connected to one another by contacts TC2, whereby the resistance value of a power supply line for supplying the substrate bias voltage VBB can be reduced. Further, the resistance between P-type well regions PWELO and PWELl corresponding to the sub arrays MAT0 and MAT1 can be reduced owing to the adoption of such a wiring system. According to the present embodiment, noise developed in the substrate when the potential on each bit line BL is amplified according to the amplifying operation of the sense amplifier SA, can be canceled out at high speed and reduced, whereby an operating margin for a one-intersection DRAM array can greatly be enlarged in a manner similar to the embodiment shown in FIG. 1.
FIG. 13 is a circuit diagram of one embodiment of a sub-word driver employed in the dynamic RAM according to the present invention. In the present embodiment, one main word line MWL is provided with respect to eight sub word lines WL0 through WL7. Sub-word selection lines FX0 through FX7 and FX0B through FX7B are required to select one sub-word line from the eight sub-word lines. In the present embodiment, bit lines provided in one sub array are selected half by half by sub-word driver arrays SWDA provided on both sides thereof. Therefore, eight sub-word selection lines FX1, 2, 5 and 6 and FX1B, 2B, 5B and 6B for selecting the four sub-word lines corresponding to the half of the eight sub-word lines are extended over one sub-word driver array shown in the same drawing.
Eight sub-word selection lines FX0, 3, 4 and 7 and FX0B, 3B, 4B and 7B for selecting the four sub-word lines corresponding to the remaining half of the eight sub-word lines are extended over sub-word driver arrays provided on the opposite side with the unillustrated sub array interposed therebetween. Sub-word drivers corresponding to sub-word lines WL1 and WL2, WL2 and WL4, and WL5 and WL6 set with the two as each pair are alternately provided. Further, a sub-word line WL1 and a group sub-word line WL7 (different in main word line) adjacent thereto are set as one pair and two sub-word drivers are provided therefor.
FIG. 15 is a block diagram showing one embodiment of a dynamic RAM according to the present invention. The dynamic RAM showing the present embodiment is intended for a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory; hereinafter called simply “DDR SDRAM”). Although not restricted in particular, the DDR SDRAM according to the present embodiment is provided with four memory arrays 200A through 200D in association with four memory banks. The memory arrays 200A through 200D respectively associated with the four memory banks 0 through 3 are equipped with dynamic memory cells placed in matrix form. According to the drawing, selection terminals of memory cells placed in the same column are connected to their corresponding word lines (not shown) set every columns, and data input/output terminals of memory cells placed in the same row are connected to complementary data lines (not shown) set every rows.
In the case of a storage capacity of 256 Mbits, for example, an address terminal for inputting the address signal A14 as the column address signal is provided when a memory access is carried out in 2-bit units. In an ×4 bit configuration, the address signals up to the address signal A11 are rendered valid. In an ×8-bit configuration, the address signals up to the address signal A10 are made valid, and the address signals up to the address signal A9 are rendered valid in an ×16-bit configuration. In the case of a storage capacity of 64 Mbits, the address signals up to the address signal A10 are rendered valid in an ×4-bit configuration, and the address signals up to the address signal A9 are made valid in an ×8-bit configuration. Further, the address signals up to the address signal A8 are set valid in an ×16-bit configuration as shown in the drawing.
A mode register(Mode Register) 213 holds various operation mode information therein. Of the row decoders (Row Decoders) 201A through 201D, only one corresponding to the bank specified by a bank select (Bank Select) circuit 212 is activated to allow the operation of selecting a word line. Although not restricted in particular, a control circuit (Control Logic) 209 is supplied with external control signals such as clock signals CLK, /CLK (symbol / means that signals marked therewith are row enable signals), a clock enable signal CKE, a chip select signal /CS, a column address strobe signal /CAS, a row address strobe signal /RAS and a write enable signal /WE, etc., /DM and DQS, and address signals inputted through the mode register 213. The control circuit 209 forms internal timing signals for controlling an operation mode for the DDR SDRAM and the operations of the circuit blocks, based on changes in the levels of these signals, timing, etc. and is provided with input buffers respectively corresponding to the signals.
Other external input signals are rendered significant in synchronism with the rising edge of the internal clock signal. The chip select signal /CS provides instructions for the commencement of a command input cycle according to its low level. When the chip select signal /CS is of a high level (kept in a chip non-selected state), other inputs do not make sense. However, the state of selection of each memory bank, and its internal operations such as a burst operation, etc. to be described later are not affected by a change to the chip non-selected state. The respective signals /RAS, /CAS and /WE are different in function from corresponding signals employed in the normal DRAM and are set as significant signals upon defining command cycles to be described later.
When the ×16-bit configuration is set in 256 Mbits as described above, the column address signals are defined according to the levels of A0 through A9 in a read or write command (corresponding to a column address/read command or a column address/write command to be described later) cycle synchronized with the rising edge of the clock signal CLK (internal clock). Each of the column addresses defined in this way is set as a start address for a burst access.
This is a command required to start a burst read operation. Further, this is also a command for providing instructions for a column address strobe. The present command is specified according to /CS and /CAS=low level and /RAS and /WE=high level. Column addresses supplied to A0 through A9 (in the case of the ×16-bit configuration) at this time are captured as column address signals respectively. Thus, the captured column address signals are supplied to the column address counter 207 as burst start addresses.
Thus, unless D0 through D15 collide with one another at a data input/output terminal comprising 16 bits, for example, the precharge command and the row address strobe/bank active command for a memory bank different from a memory bank to be processed or handled by an unfinished command are issued during the execution of the corresponding command to thereby allow the commencement of an internal operation in advance. Since the DDR SDRAM according to the present embodiment performs the memory access in 16-bit units, has the addresses corresponding to about 4M, based on the addresses of A0 through A11, and comprises the four memory banks as described above, it has a storage capacity of about 256M bits (4M×4 banks×16 bits) as a whole.
A detailed read operation of the DDR SDRAM is as follows. The respective signals of the chip select /CS, /RAS and /CAS and write enable /WE are inputted in synchronism with the CLK signal. A row address and a bank select signal are inputted simultaneously with /RAS=0 and held in the row address buffer 205 and the bank select circuit 212 respectively. The row decoder 210 for the bank designated by the bank select circuit 212 decodes a row address signal and hence the corresponding memory cell array 200 outputs row overall data as a small signal. The outputted small signal is amplified by and held in the corresponding sense amplifier 202. Thus, the specified bank is rendered active (Active).
After 3 CLKs since the input of the row address, a column address and a bank select signal are inputted simultaneously with CAS=0 and respectively held in the column address buffer 206 and the bank select circuit 212. If the specified bank is active, then the held column address is outputted from the column address counter 207 and the corresponding column decoder 203 selects a column. The selected data is outputted from the sense amplifier 202. The data outputted at this time corresponds to two pairs or sets (8 bits in ×4-bit configuration and 32 bits in ×16-bit configuration)
The data outputted from the sense amplifier 202 is outputted from the data output circuit 211 to the outside of the chip through a data bus DataBus. Timing provided to output it is synchronized with both the rising and falling edges of QCLK outputted from the DLL 214. At this time, the two pairs of data are parallel-to-serial converted into data of one pair × two as described above. Simultaneously with the output of the data, the DQS buffer 215 outputs a data strobe signal DQS therefrom. When the burst length stored in the mode register 213 is 4 or more, the column address counter 207 automatically increments addresses to read out the next column data.
JPH09135009A Title not available
JPS592365A Title not available
JPS60195795A Title not available
JPS60211871A Title not available
US6944080 * Sep 13, 2004 Sep 13, 2005 Hitachi, Ltd. Dynamic random access memory(DRAM) capable of canceling out complimentary noise developed in plate electrodes of memory cell capacitors
US7274613 Aug 8, 2005 Sep 25, 2007 Elpida Memory, Inc. Dynamic random access memory (DRAM) capable of canceling out complementary noise development in plate electrodes of memory cell capacitors
US7542321 * Jul 24, 2007 Jun 2, 2009 Kabushiki Kaisha Toshiba Semiconductor memory device with power supply wiring on the most upper layer
US20050030783 * Sep 13, 2004 Feb 10, 2005 Hitachi, Ltd. Dynamic RAM and semiconductor device
US20050270889 * Aug 8, 2005 Dec 8, 2005 Hitachi, Ltd. Dynamic random access memory (DRAM) capable of canceling out complimentary noise development in plate electrodes of memory cell capacitors
US20090027941 * Jul 24, 2007 Jan 29, 2009 Hiroshi Maejima Semiconductor memory device with power supply wiring on the most upper layer
U.S. Classification 365/214, 257/E27.088, 365/208, 365/149, 257/E27.097, 365/207, 365/63, 365/72, 365/51
International Classification G11C7/18, H01L27/02, G11C11/4097, G11C8/00, H01L27/108, G11C5/02, G11C5/06, H01L21/8242, G11C11/34, G11C7/02, G11C11/401
Cooperative Classification G11C11/4074, H01L27/10814, H01L27/10897, G11C7/02, H01L27/10885, G11C7/18, G11C5/025, G11C11/4097, G11C5/063, H01L27/0214, H01L27/0207, H01L27/10882
European Classification G11C7/18, G11C11/4074, G11C7/02, H01L27/108P, G11C5/06H, G11C11/4097, G11C5/02S
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SEKIGUCHI, TOMONORI;KAJIGAYA, KAZUHIKO;KIMURA, KATSUTAKA;AND OTHERS;REEL/FRAME:013548/0047;SIGNING DATES FROM 20000731 TO 20000817