Source: http://www.google.com/patents/US4455647?dq=6,370,566
Timestamp: 2017-11-24 17:43:25
Document Index: 330911918

Matched Legal Cases: ['ART 308', 'ART 312', 'ART 308', 'ART 308', 'ART 312', 'ART 308', 'ART 312']

Patent US4455647 - Apparatus for establishing multi-address connections - Google Patents
A digital data telecommunications system comprises a central switching system and a plurality of line terminators each connecting the switching system to a pair of incoming and outgoing lines and each designed to convert serial data transmitted along the incoming and outgoing lines into formatted message...http://www.google.com/patents/US4455647?utm_source=gb-gplus-sharePatent US4455647 - Apparatus for establishing multi-address connections
Publication number US4455647 A
Application number US 06/388,087
Publication number 06388087, 388087, US 4455647 A, US 4455647A, US-A-4455647, US4455647 A, US4455647A
Inventors Enrique Gueldner
US 4455647 A
A digital data telecommunications system comprises a central switching system and a plurality of line terminators each connecting the switching system to a pair of incoming and outgoing lines and each designed to convert serial data transmitted along the incoming and outgoing lines into formatted message characters for transfer through the switching system, and vice-versa. Control data stored in a connection memory for the duration of a call enable the switching system to interconnect sequentially each calling line terminator with the respective called line terminator in a time multiplex mode for transmitting one message character at a time. An arrangement for establishing multi-address connections includes an additional line terminator connected to receive a character of a multi-address message from a calling line terminator across the switching system. A distributing data bus connects this line terminator in parallel to all line terminators entitled to receive a multi-address message. These receiving line terminators include control means for alternatively enabling the respective line terminator in a single address mode to receive a message character supplied by the switching system, and in a multi-address mode to receive serial data transmitted along said distributing data bus, respectively.
1. In a digital data telecommunications system comprising a central switching system and a plurality of line terminators each connecting the switching system to a pair of incoming and outgoing lines and each designed to convert serial data transmitted with various speeds and codes along the incoming and outgoing lines into formatted message characters received and emitted by the switching system, and vice-versa, wherein said switching system includes a connection control memory having storage cells each associated with a respective one of the line terminators, said cells storing control data and specifying the allocation between a calling line terminator and the respective called line terminator for the duration of the call, and said control data enabling the switching system to interconnect sequentially each calling line terminator with the respective called line terminator in a time multiplex mode for transmitting one message character at a time, the improvement constituting an arrangement for establishing multi-address connections, in combination with said central switching system, and comprising:
(1) an additional line terminator connected to receive a character of a multi-address message from a calling line terminator across the switching system, and having a serial output furnishing corresponding serial data;
(2) a distributing data base connecting said serial output of said additional line terminator in parallel to all line terminators entitled to receive a multi-address message; and
(3) said line terminators entitled to receive multi-address messages including control means for alternatively enabling the respective line terminator in a single address mode to receive a message character supplied by the switching system and to convert the same into serial data for emitting the data to the respective outgoing line, and in a multi-address mode to receive serial data transmitted along said distributing data bus, respectively, for transfer to said outgoing line, wherein each line terminator includes a line interface unit having a pair of external inputs and outputs connected to the associated incoming and outgoing line, respectively, and having a corresponding pair of internal inputs and outputs, wherein said line terminator further includes means for converting serial data received on the incoming line to formatted data characters, and vice-versa, said converting means having a pair of internal inputs and outputs connected to the respective ones of said internal inputs and outputs of said line interface unit, and having external parallel inputs and outputs connected to said central switching system for receiving and transmitting, respectively, a message character,
wherein said line terminator further includes means for controlling the operation of the line terminator and having control data inputs and outputs connected to receive and to transmit, respectively, control signals from and to the central switching system, and
wherein each of said line terminators entitled to receive a multi-address message further comprises:
switch means arranged between the line interface unit and the converting means for alternatively connecting the internal input of the line interface unit to the internal output of the converting means and to said distributing data bus, respectively, under control of said control means.
2. The improvement as recited in claim 1, wherein the central switching system is composed of (a) a central processing system connected to receive call requests from calling line terminators and designed to generate the connection control data, and (b) a communications controller including (i) means for storing this connection control data in said connection memory, (ii) means for scanning sequentially the line terminators by commanding the respective ones of said control means of said line terminators to supply a data control signal at said control output and (iii) means for temporarily interconnecting each line terminator in a calling status to a respective called line terminator; and wherein said central processing system further comprises:
call request control means for recognizing a specific call request as a multi-address call and for initiating the setting up of multi-address connections upon receipt of this request by commanding the communications controller to transmit to each predetermined line terminator, entitled to receive a multi-address message, a corresponding control signal forcing the respective line terminator to assume the multi-address mode; said call request control means acknowledging the request of the calling line terminator after this set up operation whereupon the requesting line terminator, in turn, is enabled to start the transfer of the multi-address message.
3. The improvement as recited in claim 2, wherein said call request control means of the central processing system include means for distinguishing between different call requests, each determining a respective group of the line terminators designated to receive the respective multi-address message.
4. The improvement according to claim 1, 2 or 3, wherein the digital data telecommunications system further includes a central distortion test system forming an off-line subsystem connected to the central switching system and being designed to distort incoming serial data in accordance with various discrete distortion levels ranging from zero to full distortion under control of said central processing system,
wherein said central distortion system is arranged between said additional line terminator and said distributing data bus, and
wherein the subsystem is utilized for transmitting both a multi-address message and a distorted text with the difference that a multi-address message is always directed to more than one line terminator and the respective receiving line terminators are forced by the central processing system to assume the multi-address mode, whereas the transmitted distorted text is only received by a line terminator requesting such service.
It is the object of the present invention to make possible a multi-address connection arrangement in combination with a digital data telecommunications system including a central switching system and a plurality of line terminators each connecting the switching system to a pair of incoming and outgoing lines transmitting serial data with various speeds and codes. Each line terminator is designed to convert the serial data into formatted message characters received and emitted by the switching system, and vice-versa. The switching system includes a connection control memory having storage cells each associated with a respective one of the line terminators. Each storage cell stores control data specifying the allocation between a calling line terminator and the respective called line terminator for the duration of a call. By means of these control data the switching system is enabled to connect sequentially each calling line terminator with the respective called line terminator in a time multiplex mode for transmitting one message character at a time.
A better understanding of the invention may be had by reference to this following description of a preferred embodiment in conjunction with the accompanying drawings.
DESCRIPTION OF THE PREFERRED EMBODIMENT The Central Exchange (FIG. 1)
The block diagram shown in FIG. 1 schematically represents a time multiplex digital telecommunications system with switching capabilities for handling digital communications services. It includes a central processor system represented by a central processor 10 and a processor bus 12 and performing the main control functions, especially for establishing through-connections between pairs of data terminals which are indicated as subscribers 14, and for terminating such connections.
The Timer of the Distortion System (FIGS. 2 and 3)
It has been indicated that the central distortion system can operate at various speeds and codes. For this reason, the timer 54 is provided for generating all clock signals necessary for the operation of the distortion sender 50 and the distortion receiver 52. For each of the operational baud rates, the timer derives two clock signals which are 16 times higher and 200 times higher, respectively than the associated baud rate. These clock signals are designated as x16 signals and x200 signals, respectively. The x16 signals are necessary to operate receiver and transmitter devices of the distortion sender 50 and the x200 signals determine the performance characteristic of the distortion receiver 52, in other words, these clock pulses are necessary to obtain the accuracy of the distortion receiver.
The master oscillator 202 is buffered from the dividing circuitry by a buffering NAND gate 204. A first binary count 206 is directly triggered by the master clock pulse of 30.72 MHz. This first counter 206 comprises a conventional integrated circuit SN74S 197 manufactured by Texas Instruments and is wired to provide a divide-by-2 output of 15.360 MHz and a divide-by-16 output of 1.920 MHz which furnishes the clock signal 9600 B×200. A first clock input of a second binary counter 208 constructed from the same integrated circuit is connected to the 15.360 MHz clock pulse and provides divide-by-two, divide-by-four, divide-by-eight and divide-by-sixteen outputs which carry a group of four further clock pulses associated with 4800 B, 2400 B, 1200 B and 600 B, respectively. A third binary counter 210 identically designed to the previous ones provides a divide-by-two output, a divide-by-four output and a divide-by-eight output furnishing the next group of clock signals corresponding to baud rates 300 B, 150 B and 75 B, respectively. An independent divider circuit of the third binary count derives a 10 KHz clock pulse corresponding to 50 B.
The next two counter stages 212 and 214 are composed of divide-by-12 counters comprising commercially available integrated circuits SN 74 LS 92 A and SN 74 LS 98 manufactured by Texas Instruments. The fourth counter 212 divides the 240 KHz clock signal by 6 to yield 40 KHz which corresponds to a 200 B×200 clock signal and divides that signal to give 20 KHz which corresponds to 100 B×200 and also provides a trigger input to the third binary counter for the independent divider circuit. The fifth binary counter 214 receives an 80 KHz trigger signal from the fourth counter and is wired to divide this input signal by 5 and by 2 to yield an 8 KHz clock pulse which corresponds to 200×40 B.
A NAND gate 222 connected by its input to the ripple carry output TC of the binary counter 220 and the outputs QC and QD of the binary counter 216 allows for a glitch-free reset by decoding the N-3 count and by triggering a modulo-3 reset circuit comprising two master-slave flipflops 224 and 226, respectively. Since the output of the second master-slave flipflop 226 is not symmetrical, a D flipflop 228 is provided for dividing the output signal of the second master-slave flipflop 226 by 2. The D flipflop 228 furnishes a symmetric 22 KHz pulse, which pulse corresponds to the 110 B×200 clock signal.
This divider circuitry derives from the master clock pulse 30.720 MHz in a similar manner a symmetric output pulse of 26.9 KHz representing the 134.5 B×200 clock pulse. The layout of the circuitry is identical to the aforementioned divider section, except for different hardwired low and high connections of the data inputs of the three binary counters 230, 232 and 234. These connections determine a pre-setting of these binary counters which in combination with the wiring of the enable inputs EP and the reset inputs MR determine a divide-by-N circuit, wherein N=571. This value can be derived in the same manner as outlined above with respect to the upper section. The high-frequency 16×baud rates are derived by a standard counter/divider chain which is similar to corresponding circuitry described above in conjunction with FIG. 2. Two further sections of divide-by-N circuits similar to those shown in FIG. 3 are used to derive the lower frequency baud rates of 110 B×16 and 135B×16. Since such clock divider circuits are very well known in the art and examples of corresponding circuits have been represented in FIGS. 2 and 3 no further presentation of schematics and detailed description is deemed to be necessary.
The Distortion Sender (FIG. 4)
Operation of the distortion sender 52 will be described in more detail in the following on two levels. The first level is keyed to a simplified block diagram shown in FIG. 4 representing the basic concept of the distortion sender. This description is followed by schematics which represent sections of the distorted sender in more detail.
FIG. 4 represents a clock select unit 302 which receives in parallel the various clock signals generated by the timer 52 described above. For simplification two groups of input signals are shown and designated ×200 signals and ×16 signals, respectively. The clock select unit 302, furthermore, receives an internal select control signal to be described later in more detail which signal triggers the selection of specific ones of the clock input signals in accordance with the speed of a subscriber requesting distortion test service. Another input signal to the distortion sender is a command clock signal which is identical with the 100 B×16 signal and is also furnished by the timer 52.
After receipt of two command words, the input control unit 304 automatically redirects the incoming data stream to the data UART 308 which is connected to a further data UART 312. Both universal asynchronous receiver/transmitter circuits are connected transmitter-to-receiver to generate a zero distortion data stream. Both the first and second data UART 308 and 312, respectively, are triggered by a common clock pulse which is dependent upon the desired baud rate. In accordance with the design of conventional UART's this clock pulse must be 16 times the desired baud rate, as indicated by a corresponding reference symbol B×16. This clock pulse is an output pulse of the clock select unit 302 and its actual pulse rate accordingly is dependent upon the baud rate specified by the previous distortion sender command code.
FIG. 5 represents the layout of the clock select unit 302 in more detail. At the left hand margin of the drawing two groups of input signals are shown which represent the ×200 signals and ×16 signals, respectively. These signals correspond to the entire range of baud rates from 9600 B down to 50 B which can be handled by the central exchange. Out of this wide range of possible transmission speeds, eight speeds can be preselected using a set-up structure of hand-wired headers which are schematically indicated and referenced 320, 320' and 322, 322'. By connecting one input connector to a respective one of the output connectors of the headers, each of the incoming clock signals can be related to a specific output line of a header, thus determining the relationship between incoming clock signal and a distortion system speed level. One possible connection scheme is indicated at header 320 by dotted lines. This connection scheme indicates that SPEED ZERO is associated with either a 9600 baud rate or a 75 baud rate. If headers 320 and 320' are programmed in this manner, headers 322 and 322' have to be wired accordingly.
Respective output lines of headcrs 320 and 320' are commonly connected across individual buffering devices which are schematically indicated bv a buffering circuit 324 to a respective data input of a multiplexor 326. This multiplexor is controlled by the select control signals which determine a 3-bit select code to allow for a 1-out-of-8 selection. This selection arrangement shows that by means of the headers 320 and 320', eight different transmission speeds can be preselected in accordance with system requirements assuming that not more than eight types of subscribers with different transmission speeds connected to an installed central exchange are connected to use the distortion test service. Of these pre-selected eight transmission speeds, in turn, one transmission speed is selected in accordance with the set-up command received by the distortion sender. At the output side of the multiplexor 326 there is arranged a D flipflop 328 which divides the output signal of the multiplexor 326 by 2 and generates a ×100 clock signal which is used by control logic of the distortion sender.
In a similar manner, the ×16 signals are preselected by the headers 322 and 322' and are furnished to a second multiplexor 330 across a buffering circuit 332. The second multiplexor 330 is controlled by the same bit combination specified by the select control signal and generates the selected ×16 clock signal utilized to control the operation of the data UART's 308 and 312 shown in FIG. 4.
In a similar manner, a second pair of D-flipflops 360 and 362, respectively is controlled by an output signal DATA READY 2 generated by the first data UART 308. This pair of D-flipflops furnishes a control signal DATA RESET 2 for resetting the data line of the associated receiver/transmitter circuit in synchronism with the clock signal B×16. In addition, the reverse condition of the D-flipflop 362 is utilized to generate a strobe pulse which when low enables to load the buffered data byte into a transmitter holding register of the second data UART 312. This strobe TRANSMIT LOAD is generated by means of a NAND gate 364 which is enabled by means of an inverter 366 as long as the first data UART 308 does not furnish an error signal FRAME ERROR 2.
The Distortion Level Select Control Logic (FIG. 9)
In the foregoing it was described that the data UART's 308 and 312 generate a serial stream of undistorted perfect data that will subsequently be distorted by the data distortion logic 316. This logic section of the distortion sender 50 is controlled by the distortion level select and control logic 314 which is shown in more detail in FIG. 9. This section of the distortion sender is basically controlled by the clock signal ×100 CLOCK generated by the clock select unit 302. This clock signal is divided-by-10 by a first clock divider circuit 380 and then again divided-by-1 by a second clock divider circuit 382.
This circuit arrangement now is operated in accordance with the serial data stream generated by the second data UART 312. This data stream is recognized in the distortion level select and control logic 314 in inverted form as designated by the reference DATA and fed to a pulse circuit 396 which includes two inverters connected to each other across an RC circuit and a clipping diode. This pulse circuit is triggered by a mark-to-space transition of the serial input data and furnishes a corresponding output signal which resets both the clock divider circuits 380 and 382 controlling the counting operation of these divider circuits to start at all zeros exactly in synchronism with a mark-to-space transition of the serial input data. More specifically, when the data input signal DATA goes high, the reset inputs RO of both clock divider circuits 380 and 382 are pulsed high and the clock divider circuits are reset. This resetting enables both output multiplexors 392 and 394 and, in addition, yields a data output FIXED DATA across an activated AND gate 398. This AND gate 398 is activated only when the enable signal for the output multiplexors 392 and 394 derived from the clock signal ×200 CLOCK and the least significant output QA of the second clock divider circuit 382 is present in combination with the occurrence of low level output signals "0" and "00" of the selector circuits 384 and 386. The output signal FIXED DATA thus comprises the perfect undistorted data.
The Distortion Logic and Output Interface (FIG. 10)
The output signals of the distortion level select and control logic form control input signals to the distortion logic 316 which is shown in FIG. 10 together with the output interface 318. The distortion logic comprises two further NOR gates 420 and 422, respectively, which act as selectors. These selectors receive the previously generated signals FIXED DATA and VARIABLE DATA and determine whether the input data will have mark or space distortion depending on whether the input signals MARK or SPACE received from the decoder 310 are in logic level "1".
The Multi-Address Service
The described optional feature of an electronic digital telecommunication system is designed such that it can be used for generating any kind of distorted data as requested by a subscriber for testing purposes and for transmitting undistorted data to a plurality of subscriber stations at the same time, which is in contrast to the setup of a normal call connection which provides for temporary communication links just between pairs of subscribers.
US7746251 * Nov 13, 2007 Jun 29, 2010 Qualcomm Incorporated High speed serializer/deserializer transmit architecture
US20080136689 * Nov 13, 2007 Jun 12, 2008 Qualcomm Incorporated High speed serializer/deserializer transmit architecture
WO1985000261A1 * Jun 25, 1984 Jan 17, 1985 Confertech International, Inc. Digital teleconferencing control device, system and method
WO1992002090A1 * Jul 6, 1991 Feb 6, 1992 Siemens Aktiengesellschaft Method of controlling a digital coupling-field store
U.S. Classification 370/270, 370/360, 370/241, 370/359, 370/216
Owner name: SIEMENS CORPORATION 186 WOOD AVE S ISELIN N J 088
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:GUELDNER, ENRIQUE;REEL/FRAME:004007/0458