Source: http://www.google.com/patents/US7405133?ie=ISO-8859-1&dq=6,826,762
Timestamp: 2014-03-17 10:46:42
Document Index: 413574853

Matched Legal Cases: ['Application No. 11', 'application No. 11', 'Application No. 100', 'Application No. 100', 'Application No. 100', 'Application No. 11', 'Application No. 11']

Patent US7405133 - Semiconductor device and method for manufacturing the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes,...http://www.google.com/patents/US7405133?utm_source=gb-gplus-sharePatent US7405133 - Semiconductor device and method for manufacturing the sameAdvanced Patent SearchPublication numberUS7405133 B2Publication typeGrantApplication numberUS 11/256,929Publication dateJul 29, 2008Filing dateOct 25, 2005Priority dateJun 30, 1999Fee statusLapsedAlso published asDE10031881A1, DE10031881B4, DE10066334B4, US6459111, US7022580, US20020190290, US20060038215Publication number11256929, 256929, US 7405133 B2, US 7405133B2, US-B2-7405133, US7405133 B2, US7405133B2InventorsKatsuaki Natori, Tomohiro Saito, Yoshihiro UozumiOriginal AssigneeKabushiki Kaisha ToshibaExport CitationBiBTeX, EndNote, RefManPatent Citations (30), Non-Patent Citations (6), Classifications (22), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and method for manufacturing the sameUS 7405133 B2Abstract A semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes, and an upper electrode formed on the surface of the ferroelectric film, wherein each of the capacitors is formed for each of the plurality of lower electrode.
CROSS-REFERENCE TO RELATED APPLICATIONS This is a division of application Ser. No. 10/222,813, filed Aug. 19, 2002, now U.S. Pat. No. 7,022,580 which is a division of Ser. No. 09/609,712, filed Jun. 30, 2000 (now U.S. Pat. No. 6,459,111) which are incorporated in their entirety herein by reference. This application is also based upon and claims priority from Japanese Patent Application No. 11-187018, filed Jun. 30, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION This invention relates to a semiconductor device provided with a capacitor wherein a ferroelectric film is employed as a dielectric film, and to a method for manufacturing such a semiconductor device.
BRIEF SUMMARY OF THE INVENTION Therefore, an object of this invention is to provide a semiconductor device provided with a capacitor wherein a ferroelectric film is employed as a dielectric film, and the ferroelectric film is prevented from being deteriorated.
DETAILED DESCRIPTION OF THE INVENTION The semiconductor device according to a first embodiment of this invention is featured in that it comprises a plurality of lower electrodes formed on a semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes, and an upper electrode formed on the surface of the ferroelectric film, wherein each of the capacitors is formed for each of the plurality of lower electrodes.
EXAMPLE 1 FIGS. 1A to 1E illustrate respectively a cross-sectional view illustrating the manufacturing steps of a semiconductor device according to a first example of this invention.
EXAMPLE 2 The manufacturing steps of a semiconductor device according to a second example of this invention will be explained with reference to FIGS. 2A to 2J illustrating respectively a cross-sectional view of the semiconductor device.
EXAMPLE 3 In this example, a method of manufacturing a ferroelectric capacitor wherein a barrier metal and a capacitor dielectric film are formed by a procedure which is different from the aforementioned procedure will be explained with reference to FIGS. 5A to 5L. Namely, FIGS. 5A to 5L illustrate respectively a cross-sectional view illustrating the manufacturing steps of a semiconductor device according to a third example of this invention.
EXAMPLE 4 The manufacturing steps of a semiconductor device according to a fourth example of this invention will be explained with reference to FIGS. 7A to 7H illustrating respectively a cross-sectional view of the semiconductor device.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5198384May 15, 1991Mar 30, 1993Micron Technology, Inc.Process for manufacturing a ferroelectric dynamic/non-volatile memory array using a disposable layer above storage-node junctionUS5330931Sep 23, 1993Jul 19, 1994Mcmaster UniversityMethod of making a capacitor for an integrated circuitUS5397908Dec 9, 1993Mar 14, 1995Micron Technology, Inc.Arrays of memory integrated circuitryUS5416042Jun 9, 1994May 16, 1995International Business Machines CorporationMethod of fabricating storage capacitors using high dielectric constant materialsUS5442585Jul 7, 1993Aug 15, 1995Kabushiki Kaisha ToshibaDevice having dielectric thin filmUS5693553Aug 13, 1996Dec 2, 1997Mitsubishi Denki Kabushiki KaishaSemiconductor device and manufacturing method of the sameUS5717236Oct 3, 1995Feb 10, 1998Mitsubishi Denki Kabushiki KaishaSemiconductor memory including stacked capacitor having a flat surfaceUS5789303Jul 11, 1996Aug 4, 1998Northern Telecom LimitedMethod of adding on chip capacitors to an integrated circuitUS5828092Apr 24, 1996Oct 27, 1998Siemens AktiengesellschaftSemiconductor memory device and method for its productionUS6051859Jan 16, 1998Apr 18, 2000Kabushiki Kaisha ToshibaDRAM having a cup-shaped storage node electrode recessed within an insulating layerUS6204172Sep 3, 1998Mar 20, 2001Micron Technology, Inc.Low temperature deposition of barrier layersUS6211542May 27, 1998Apr 3, 2001Ramtron International CorporationCompletely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced escapsulation layerUS6303958Jun 11, 1998Oct 16, 2001Kabushiki Kaisha ToshibaSemiconductor integrated circuit and method for manufacturing the sameDE4402216A1Jan 26, 1994Jul 28, 1994Samsung Electronics Co LtdHalbleiterbauelement mit Kondensatoren und zu seiner Herstellung geeignetes VerfahrenEP0448307A1Mar 15, 1991Sep 25, 1991Fujitsu LimitedMethod of producing a MESFETJP2000031396A Title not availableJP2000260956A Title not availableJPH0883894A Title not availableJPH1079478A Title not availableJPH1131682A Title not availableJPH1140768A Title not availableJPH07115140A Title not availableJPH08264719A Title not availableJPH08316430A Title not availableJPH09135007A Title not availableJPH09162311A Title not availableJPH09162369A Title not availableJPH10209391A Title not availableJPH10340871A Title not availableKR19990013932A Title not availableNon-Patent CitationsReference1Decision of Rejection issued by Japanese Patent Office, mailed Feb. 1, 2005, in Japanese application No. 11-187018, and English translation of Notice.2German Patent Office Action mailed by the German Patent Office on Aug. 4, 2005 in counterpart German Application No. 100 31 881.9-33.3German Patent Office Action mailed by the German Patent Office on Aug. 4, 2005 in counterpart German Application No. 100 66 244.7-33.4German Patent Office Action mailed by the German Patent Office on Jun. 26, 2007 in counterpart German Application No. 100 66 334.6-33.5Notification of Reasons for Rejection mailed by the Japanese Patent Office on Jul. 26, 2005 in counterpart Japanese Application No. 11-187018.6Notification of Reasons for Rejection, mailed Oct. 5, 2004, by the Japanese Patent Office, for Japanese Application No. 11-187018, and English-language translation thereof.Classifications U.S. Classification438/397, 257/E21.579, 257/E21.208, 257/E21.008, 257/E21.021, 438/244International ClassificationH01L21/8242, H01L27/04, H01L21/02, H01L27/108, H01L21/8246, H01L27/105, H01L21/822, H01L21/20Cooperative ClassificationH01L28/75, H01L28/55, H01L28/40, H01L27/10852, H01L21/76807European ClassificationH01L28/75, H01L28/40, H01L28/55Legal EventsDateCodeEventDescriptionSep 18, 2012FPExpired due to failure to pay maintenance feeEffective date: 20120729Jul 29, 2012LAPSLapse for failure to pay maintenance feesMar 12, 2012REMIMaintenance fee reminder mailedRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google