Source: http://www.google.com/patents/US7652338?dq=%22robert+sheehan%22
Timestamp: 2017-03-29 19:38:43
Document Index: 170853414

Matched Legal Cases: ['Application No. 06011395', 'Application No. 06011396', 'Application No. 04', 'Application No. 05', 'Application No. 06', 'Application No. 06', 'Application No. 2004']

Patent US7652338 - Efficient transistor structure - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn integrated circuit comprises first and second drain regions have a generally rectangular shape. First, second and third source regions have a generally rectangular shape, wherein the first source region is arranged between first sides of the first and second drain regions and the second and third...http://www.google.com/patents/US7652338?utm_source=gb-gplus-sharePatent US7652338 - Efficient transistor structureAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7652338 B2Publication typeGrantApplication numberUS 11/586,471Publication dateJan 26, 2010Filing dateOct 25, 2006Priority dateOct 22, 2003Fee statusPaidAlso published asUS7528444, US7851872, US7863657, US20070032063, US20070034903, US20070034904, US20070037353Publication number11586471, 586471, US 7652338 B2, US 7652338B2, US-B2-7652338, US7652338 B2, US7652338B2InventorsSehat SutardjaOriginal AssigneeMarvell World Trade Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (54), Non-Patent Citations (10), Referenced by (2), Classifications (33), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetEfficient transistor structure
US 7652338 B2Abstract
An integrated circuit comprises first and second drain regions have a generally rectangular shape. First, second and third source regions have a generally rectangular shape, wherein the first source region is arranged between first sides of the first and second drain regions and the second and third source regions are arranged adjacent to second sides of the first and second drain regions. Fourth and fifth source regions, wherein the fourth source region is arranged adjacent to third sides of the first and second drain regions and wherein the fifth source region is arranged adjacent to fourth sides of the first and second drain regions. A gate region is arranged between the first, second, third, fourth and fifth source regions and the first and second drain regions. First and second drain contacts that are arranged in the first and second drain regions.
first, second and third source regions that have a generally rectangular shape, wherein said first source region is arranged between first sides of said first and second drain regions and said second and third source regions are arranged adjacent to second sides of said first and second drain regions;
fourth and fifth source regions, wherein said fourth source region is arranged adjacent to third sides of said first and second drain regions and wherein said fifth source region is arranged adjacent to fourth sides of said first and second drain regions;
first and second drain contacts that are arranged in said first and second drain regions.
11. The integrated circuit of claim 1 further comprising at least one substrate contact arranged in at least one of said fourth and fifth source regions.
12. The integrated circuit of claim 11 wherein said at least one of said fourth and fifth source regions includes a relief area and further comprising arranging said substrate contact region in said relief area.
13. The integrated circuit of claim 11 wherein said at least one substrate contact has first and second dimensions that are less than corresponding first and second dimensions of said at least one of said fourth and fifth source regions.
14. The integrated circuit of claim 1 further comprising B source contacts arranged in each of said first, second and third source regions, where B is an integer greater than one.
15. The integrated circuit of claim 14 wherein said first and second drain contacts have an area D and said B source contacts have an area A and wherein said area D is greater than or equal to 2*B*A.
16. The integrated circuit of claim 15 where B is equal to one of 3 or 4.
17. The integrated circuit of claim 1 further comprising
a third drain region having a generally rectangular shape that is arranged adjacent to said third source region;
a sixth source region that has a generally rectangular shape and that is arranged adjacent to said third drain region;
seventh and eighth source regions arranged adjacent to said third drain region and said sixth source region; and
a substrate contact arranged between said fourth and fifth source regions and said seventh and eighth source regions.
18. The integrated circuit of claim 17 wherein said seventh and eighth source regions are co-linear with said fourth and fifth source regions and wherein said seventh and eighth source regions are driven from one side of said integrated circuit and said fourth and fifth source regions are driven from an opposite side of said integrated circuit.
19. The integrated circuit of claim 12 wherein said relief area is arranged along an edge of at least one of said fourth and fifth source regions.
20. The integrated circuit of claim 12 wherein said relief area is arranged in a center portion of at least one of said fourth and fifth source regions.
21. The integrated circuit of claim 1 wherein said integrated circuit includes laterally-diffused MOSFET transistors. Description
This application is a Continuation of U.S. patent application Ser. No. 11/524,113 filed Sep. 20, 2006, which application claims the benefit of U.S. Provisional Application Nos. 60/825,517, filed Sep. 13, 2006, 60/824,357, filed Sep. 1, 2006, 60/823,332, filed on Aug. 23, 2006, 60/821,008, filed Aug. 1, 2006 and 60/798,568, filed on May 8, 2006 and is a continuation-in-part of U.S. patent application Ser. No. 11/252,010 filed on Oct. 17, 2005, which is a continuation of U.S. patent application Ser. No. 10/691,237 filed on Oct. 22, 2003. The disclosure of the above application is incorporated herein by reference in its entirety.
As an alternative to placing the substrate contact 330 in the elongated source regions 344, a relief area may be provided in one or both sides of the source region 344 in areas 345-B1, 345-B2, 345-B3 and 345-B4. A substrate contact region 330 can be positioned in the relief area. The shape of the elongate source region 344 can be adjusted on an opposite side of the relief area to offset the effect of the relief area and to prevent reduction in current density in areas of the elongate source region 344 near the relief areas.
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