Source: http://www.google.com/patents/US20020048847?dq=6480844
Timestamp: 2016-12-10 09:08:21
Document Index: 368386258

Matched Legal Cases: ['art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 4', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1']

Patent US20020048847 - Method of mounting semiconductor chip part on substrate - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method of mounting a semiconductor chip part on a substrate, which is capable of realizing high efficiency and high reliability of the mounting works. A leading end of a conductive wire is contact-bonded onto each pad of a semiconductor chip part, followed by tearing of the wire, to form a two-step...http://www.google.com/patents/US20020048847?utm_source=gb-gplus-sharePatent US20020048847 - Method of mounting semiconductor chip part on substrateAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20020048847 A1Publication typeApplicationApplication numberUS 08/886,557Publication dateApr 25, 2002Filing dateJul 1, 1997Priority dateJan 9, 1997Also published asUS6482676Publication number08886557, 886557, US 2002/0048847 A1, US 2002/048847 A1, US 20020048847 A1, US 20020048847A1, US 2002048847 A1, US 2002048847A1, US-A1-20020048847, US-A1-2002048847, US2002/0048847A1, US2002/048847A1, US20020048847 A1, US20020048847A1, US2002048847 A1, US2002048847A1InventorsKazuhisa Tsunoi, Akira Fujii, Shunji Baba, Yoshikazu HiranoOriginal AssigneeKazuhisa Tsunoi, Akira Fujii, Shunji Baba, Yoshikazu HiranoExport CitationBiBTeX, EndNote, RefManReferenced by (51), Classifications (50), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetMethod of mounting semiconductor chip part on substrate
[0040] [0040]FIGS. 3A to 3F show sequence steps of mounting a semiconductor chip part on a substrate according to a second embodiment of the present invention, in which parts corresponding to those in the first embodiment are indicated by the same reference numerals. A plurality of pads 2 which are conductive electrodes for connection are formed on a semiconductor chip part 1, and lands 4 which are formed in a conductive wiring pattern correspondingly to the pads 2 are formed on a substrate 3 to be mounted with the semiconductor chip part 1. [0041] First, there are prepared a plurality of gold balls (ball members) 13 each containing gold in an amount of 95% or more, and a mask member 14 having a plurality of ball attracting through-holes 14 a each having a diameter smaller than that of each of the gold balls 13. The mask member 14 is formed of a glass glate, stainless steel plate or the like, and the ball attracting holes 14 a are formed correspondingly to the plurality of the pads 2 of the semiconductor chip part 1. [0042] At an attracting step shown in FIG. 3A, the mask member 14 is mounted on an attracting tool 16 having an air attracting function, heating function, and a pressurizing function, and one surface side of the mask member 14 is made negative in pressure by actuating the attracting function of the attracting tool 16, to attract the plurality of the gold balls 13 on the other surface side of the mask member 14. [0043] The process goes on to a bump forming step shown in FIG. 3B, in which the gold balls 13 attracted on the mask member 14 by continuously actuating the attracting function of the attracting tool 16 are aligned with the corresponding pads 2, and the mask member 14 is heated and simultaneously the gold balls 13 are pressurized on the semiconductor chip part 1 by actuating the heating and pressing functions of the attracting tool 16, so that the gold balls 13 are thermally contact-bonded on the corresponding pads 2, and at the same time part of each of the gold balls 13 is plastically deformed and inserted in the corresponding ball attracting holes 14 a to form a two-step bump 15 composed of an upper step portion 15 a having a relatively small volume and a lower step portion 15 b having a relatively large volume. [0044] A pressurizing force at the bump forming step is set at such a value as to form only a flat portion on part of the gold ball 13 but not to plastically deform the entire gold ball 13 by a surface of the mask member 14 on which the gold ball 13 is attracted. A ratio between the upper step portion 15 a and the lower step portion 15 b of the bump 15 can be freely adjusted by controlling the pressurizing force and heating temperature given from the attracting tool 16 or by suitably changing a diameter of each ball attracting hole 14 a of the mask member 14. [0045] At the next paste sticking step shown in FIGS. 3C and 3D, leading end portions of the bumps 15 are collectively embedded in an almost silver paste (conductive paste) 8 (see FIG. 3C), followed by pulling-up of the leading end portions of the bumps 15 (see FIG. 3D), to stick the almost silver paste 8 on the leading end portions (the upper step portions 15 a and part of the lower step portions 15 b) of the bumps 15. The reason why the almost silver paste 8 is stuck on the leading end portions of the bumps 15 is to ensure electric connection of the bumps 15 to the lands 4 of the substrate 3. In this embodiment, the almost silver paste 8 is made of a semi-fluidized epoxy resin filled with a filler composed of a plurality of finer silver pieces and another material. [0046] The process goes on to an adhesive coating step shown in FIG. 3E, in which the substrate 3 is coated with an adhesive 9 for adhesively bonding the semiconductor chip part 1 on the substrate 3. As the adhesive 9, there can be used an adhesive mainly composed of an insulating epoxy resin, or an anisotropic adhesive which is insulating in a normal state but which is made partially conductive, when applied with a pressure, only at a portion to which the pressure is applied. Further, although the adhesive 9 can be of a thermosetting type or a ultraviolet-ray hardening type, the thermosetting type adhesive is used in this embodiment. [0047] In the case of using the insulating adhesive, the coating of the adhesive must be performed with care taken not to stick the adhesive on the lands 4 of the substrate 3 for preventing electric connection between the bumps 15 and lands 4 from being obstructed by the adhesive. In the case of using the anisotropic adhesive, the surface of the substrate 3 on which the lands 4 are formed can be entirely coated with the adhesive without such a limitation. [0048] In the second embodiment, the adhesive 9 is of an insulating type which is made of a semi-fluidized material mainly composed of an epoxy resin incorporated with an acrylic resin. The reason why the acrylic resin is incorporated in the epoxy resin is to facilitate peeling of the semiconductor chip part 1 from the substrate 3 when it is observed that there occurs an inconvenience in mounting of the semiconductor chip part 1 on the substrate 3 after hardening of the adhesive. [0049] The use of such an epoxy resin based adhesive incorporated with an acrylic resin reduces frequencies of breakage of both the substrate 3 and the semiconductor chip part 1 at the peeling step, enabling re-use of both the substrate 3 and the semiconductor chip part 4 after the peeling step. In addition, the substrate 3 is coated with the adhesive 9 in this embodiment; however, the semiconductor chip part 1 may be coated with the adhesive 9. [0050] Finally, at a pressurizing step shown in FIGS. 3E and 3F, the semiconductor chip part 1 is positioned over the substrate 1 in a state in which the pads 2 of the semiconductor chip part 1 face to the corresponding lands 4 of the substrate 3 (see FIG. 3E) and the semiconductor chip part 1 is heated at a specific temperature and is applied with a specific pressure by a mounting tool (heating/pressing head) 10 (see FIG. 3F), to plastically deform the bumps 15 (the whole of the upper step portions 15 a and the lower step portions 15 b); and then, heating is stopped with pressurizing continued by the mounting tool 10, and after hardening of the thermosetting adhesive 9, pressurizing is stopped. The works of mounting the semiconductor chip part 1 on the substrate 3 are thus completed. [0051] A coated amount of the adhesive 9 on the substrate 3 is set at a value capable of preventing extrusion or shortage of the adhesive 9 during and after mounting the semiconductor chip part 1 on the substrate 3 in consideration of a distance between the semiconductor chip part 1 and the substrate 3 after mounting, pressure and temperature upon mounting, viscosity of the adhesive, and the like. In general, active layers 11 stacked for fabrication of the semiconductor chip part 1 are exposed on each side end surface of the semiconductor chip part 1 in a state extending up to a position which is about d/3 to d/2 (d: thickness of the semiconductor chip part 1) apart from the pad side. Accordingly, in the second embodiment, the coated amount of the adhesive 9 is set at a value sufficient to cover a region of the semiconductor chip part 1 lower than the position which is about d/3 to d/2 apart from the pad 2 side after mounting the semiconductor chip part 1 on the substrate 3 (see FIG. 3F). [0052] By setting the coated amount of the adhesive 9 at a value sufficient to cover a portion of each side end surface of the semiconductor chip part 1 in consideration of a distance between the semiconductor chip part 1 and the substrate 3 after mounting, pressure and temperature upon mounting, and the like as described above, the active layers 11 exposed on each side end surface of the semiconductor chip part 1 are covered with the adhesive 9, with a result that it is possible to prevent leakage between the active layers 11 and the substrate 3, corrosion due to permeation of moisture in the active layers 11, and the like. [0053] The pressurizing force applied between the semiconductor chip part 1 and the substrate 3 by the mounting tool 10 is set at a value of 5 g to 50 g per each bump in order to reliably join the bumps 15 to the corresponding lands 4. When the pressurizing force is less than 5 g per each bump, it is impossible to obtain a reliable joining therebetween, while when it is more than 50 g for each bump, there is a possibility of occurrence of breakage of the substrate 3 and the semiconductor chip part 1. [0054] In the case of using a multilayered printed wiring board composed of epoxy resin as the substrate 3, the above pressurizing force applied between the semiconductor chip part 1 and the substrate 3 by the mounting tool 10 must be set in such a manner that a press-in amount of lands (wiring pattern) on the printed wiring board is within a range of 7 μm to 30 μm in consideration of an effect exerted on inner layers (inner wiring layers of the multilayered printed wiring board). In the case of using, for example, a ceramic board as the substrate 3, there is no limitation of the press-in amount of the lands. [0055] The pressurizing force against the substrate 3 and the heating temperature of the semiconductor chip part 1 by the mounting tool 10 are controlled in such a manner that heights of the bumps 15 become 60 μm or less after mounting of the semiconductor chip part 1 and thereby the adhesive force of the adhesive 9 is balanced against the shrinkage force thereof. In the second embodiment, the wiring pattern (lands 4) on the substrate 3 is formed by stacking an aluminum layer, barrier metal layer, nickel layer, and gold layer in this order, and the total thickness of the wiring pattern is set to be 40 μm or less. [0056] According to the second embodiment having the above configuration, there can be obtained the following advantages. Namely, since the gold balls 13 are attracted in the ball attracting holes 14 a of the mask member 14 and then the mask member 14 is heated-and simultaneously pressed on the semiconductor chip part 1, there can be reduces frequencies of accidents that the metal balls are lost as in the related art method, and further, there can be alleviated a limitation of posture upon the heating/pressing work by the mounting tool 10. [0057] Since the gold balls 13 are plastically deformed not entirely but partially upon the work of forming the bumps 15 and the upper step portions 15 a and the lower step portions 15 b of the bumps 15 are entirely plastically deformed when the semiconductor chip part 1 is heated and pressurized on the substrate 3, there can be made larger margins of the bumps 15 for deformation when the semiconductor chip part 1 is heated and pressurized on the substrate 3. This makes it possible to closely join the bumps 15 on the corresponding lands 4 and hence to increase a reliability in connection between the pads 2 and the lands 4 through the bumps 15. [0058] Since the bumps 15 are plastically deformed by heating and pressurizing the semiconductor chip part 1 by the mounting tool 10, the bumps 15 are joined with the lands 4 by metallic bonding, to thereby realize a stable connection therebetween. Further, since the silver paste 8 filled with silver pieces is stuck on the bumps 15 before mounting of the semiconductor chip part 1 on the substrate 3, the silver pieces are interposed between the bumps 15 and the lands 4 or part of the silver pieces bite both or either of the bumps 15 and the lands 4, to thereby improve electric connection between the bumps 15 and the lands 4. [0059] The mounting method of the present invention has an effect of increasing efficiency and reliability in mounting work of a semiconductor chip part on a substrate. [0060] As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, the embodiments are therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by description preceding them, and all changes that fall within meets and bounds of the claims, or equivalence of such meets and bounds are therefore intended to be embraced by the claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7090482 *Dec 17, 2003Aug 15, 2006Matsushita Electric Industrial Co., Ltd.Semiconductor device package manufacturing method and semiconductor device package manufactured by the methodUS7456493 *Mar 20, 2006Nov 25, 2008Alps Electric Co., Ltd.Structure for mounting semiconductor part in which bump and land portion are hardly detached from each other and method of manufacturing mounting substrate used thereinUS7719108 *Jan 10, 2005May 18, 2010Lockheed Martin CorporationEnhanced reliability semiconductor packageUS7969015Jan 10, 2006Jun 28, 2011Cufer Asset Ltd. L.L.C.Inverse chip connectorUS7989958Jan 10, 2006Aug 2, 2011Cufer Assett Ltd. L.L.C.Patterned contactUS8021922Jun 25, 2010Sep 20, 2011Cufer Asset Ltd. L.L.C.Remote chip attachmentUS8042724Aug 6, 2007Oct 25, 2011Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V.Method for electrically connecting to a contact of a microelectronic component on a circuit board or substrateUS8053903Feb 24, 2010Nov 8, 2011Cufer Asset Ltd. L.L.C.Chip capacitive couplingUS8067312Apr 16, 2010Nov 29, 2011Cufer Asset Ltd. L.L.C.Coaxial through chip connectionUS8084851Feb 23, 2010Dec 27, 2011Cufer Asset Ltd. L.L.C.Side stacking apparatus and methodUS8093729Jul 16, 2007Jan 10, 2012Cufer Asset Ltd. L.L.C.Electrically conductive interconnect system and methodUS8154131Jan 10, 2006Apr 10, 2012Cufer Asset Ltd. L.L.C.Profiled contactUS8197626Apr 14, 2011Jun 12, 2012Cufer Asset Ltd. L.L.C.Rigid-backed, membrane-based chip toolingUS8197627Apr 15, 2011Jun 12, 2012Cufer Asset Ltd. L.L.C.Pin-type chip toolingUS8232194Oct 14, 2011Jul 31, 2012Cufer Asset Ltd. L.L.C.Process for chip capacitive couplingUS8283778Feb 16, 2007Oct 9, 2012Cufer Asset Ltd. L.L.C.Thermally balanced viaUS8456015Jan 6, 2010Jun 4, 2013Cufer Asset Ltd. L.L.C.Triaxial through-chip connectionUS8643186Jul 29, 2010Feb 4, 2014Cufer Asset Ltd. L.L.C.Processed wafer viaUS8846445Jun 20, 2011Sep 30, 2014Cufer Asset Ltd. L.L.C.Inverse chip connectorUS9147635Dec 13, 2010Sep 29, 2015Cufer Asset Ltd. L.L.C.Contact-based encapsulationUS9324629Mar 30, 2007Apr 26, 2016Cufer Asset Ltd. L.L.C.Tooling for coupling multiple electronic chipsUS9501733 *Jul 12, 2012Nov 22, 2016Assa Abloy AbMethod of manufacturing a functional inlayUS20040130024 *Dec 17, 2003Jul 8, 2004Norihito TsukaharaSemiconductor device package manufacturing method and semiconductor device package manufactured by the methodUS20060151581 *Jan 10, 2005Jul 13, 2006Murphy William EReliability enhancement processUS20060231953 *Mar 20, 2006Oct 19, 2006Alps Electric Co., Ltd.Structure for mounting semiconductor part in which bump and land portion are hardly detached from each other and method of manufacturing mounting substrate used thereinUS20060278980 *Jan 10, 2006Dec 14, 2006John TrezzaPatterned contactUS20060278988 *Jan 10, 2006Dec 14, 2006John TrezzaProfiled contactUS20060278994 *Jan 10, 2006Dec 14, 2006John TrezzaInverse chip connectorUS20060281303 *Jan 10, 2006Dec 14, 2006John TrezzaTack & fuse chip bondingUS20070158839 *Feb 16, 2007Jul 12, 2007John TrezzaThermally balanced viaUS20070172987 *Mar 30, 2007Jul 26, 2007Roger DugasMembrane-based chip toolingUS20070182020 *Mar 30, 2007Aug 9, 2007John TrezzaChip connectorUS20080061115 *Aug 6, 2007Mar 13, 2008Andreas OstmannMethod for electrically connecting to a contact of a microelectronic component on a circuit board or substrateUS20080171174 *Jul 16, 2007Jul 17, 2008John TrezzaElectrically conductive interconnect system and methodUS20090174079 *Mar 16, 2009Jul 9, 2009John TrezzaPlated pillar package formationUS20100140776 *Jan 6, 2010Jun 10, 2010John TrezzaTriaxial through-chip connectonUS20100148343 *Feb 23, 2010Jun 17, 2010John TrezzaSide stacking apparatus and methodUS20100197134 *Apr 16, 2010Aug 5, 2010John TrezzaCoaxial through chip connectionUS20100219503 *Feb 24, 2010Sep 2, 2010John TrezzaChip capacitive couplingUS20100261297 *Jun 25, 2010Oct 14, 2010John TrezzaRemote chip attachmentUS20100304565 *Jul 29, 2010Dec 2, 2010John TrezzaProcessed wafer viaUS20110039438 *Aug 12, 2009Feb 17, 2011Chih-Ming LaiHDMI Assembly and HDMI Port for the sameUS20110147932 *Dec 13, 2010Jun 23, 2011John TrezzaContact-based encapsulationUS20110212573 *Apr 14, 2011Sep 1, 2011John TrezzaRigid-backed, membrane-based chip toolingUS20110241059 *Mar 30, 2010Oct 6, 2011Arima Optoelectronics Corp.Led die structure and method for manufacturing the bottom terminal thereofCN101866864A *Apr 16, 2010Oct 20, 2010松下电器产业株式会社电子元件安装设备CN102473591A *Jul 13, 2010May 23, 2012佐治亚科技研究公司Interconnect assemblies and methods of making and using sameCN104471593A *Jul 12, 2012Mar 25, 2015爱莎·艾伯莱有限公司Method of manufacturing a functional inlayDE102005041354B3 *Aug 31, 2005Jan 25, 2007Siemens Audiologische Technik GmbhMethod of mounting components provided with gold stud bumps onto a circuit board using isostatic forceDE102006036728A1 *Aug 5, 2006Feb 7, 2008Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.Semiconductor chips contacting method for e.g. printed circuit board layer, involves applying conductive bumps on contact areas, where bumps penetrate one layer formed during connection of metal layer with surface of board layerWO2011008759A1 *Jul 13, 2010Jan 20, 2011Georgia Tech Research CorporationInterconnect assemblies and methods of making and using same* Cited by examinerClassifications U.S. Classification438/108, 257/E21.508, 257/E23.021, 257/E21.503, 257/E23.068International ClassificationH01L21/60, H01L23/485, H01L21/56, H01L23/498Cooperative ClassificationH01L2924/00014, H01L2224/05568, H01L2224/05573, H01L2224/45144, H01L2924/07802, H01L24/29, H01L2224/81193, H01L2224/81191, H01L2224/32225, H01L24/83, H01L2224/11822, H01L2924/01029, H01L24/11, H01L2924/01082, H01L23/49811, H01L2924/01004, H01L2224/13099, H01L2924/01005, H01L21/563, H01L2924/01006, H01L2224/83192, H01L2924/01075, H01L2924/01033, H01L2224/1134, H01L2224/73203, H01L24/12, H01L2924/01079, H01L2224/11003, H01L2924/01013, H01L24/16, H01L2224/13144, H01L2924/01047, H01L2224/73204, H01L2224/16225, H01L2224/11334European ClassificationH01L24/28, H01L24/12, H01L24/16, H01L24/11, H01L21/56F, H01L23/498CLegal EventsDateCodeEventDescriptionJul 1, 1997ASAssignmentOwner name: FUJITSU LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TSUNOI, KAZUHISA;FUJII, AKIRA;BABA, SHUNJI;AND OTHERS;REEL/FRAME:008658/0326Effective date: 19970619Apr 21, 2006FPAYFee paymentYear of fee payment: 4May 3, 2010FPAYFee paymentYear of fee payment: 8Jun 27, 2014REMIMaintenance fee reminder mailedNov 19, 2014LAPSLapse for failure to pay maintenance feesJan 6, 2015FPExpired due to failure to pay maintenance feeEffective date: 20141119RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services