Source: http://www.google.com/patents/US7834550?dq=645576
Timestamp: 2017-09-25 08:45:52
Document Index: 417580509

Matched Legal Cases: ['Application No. 2007100015717', 'Application No. 2007100072531', 'Application No. 2007100072531', 'Application No. 200710003941', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 200710001782', 'Application No. 95144932', 'Application No. 95145107']

Patent US7834550 - Organic light emitting display and fabricating method of the same - Google Patents
Disclosed are an organic light emitting display and a fabricating method of the same, which improve impact resistance and sealing property of a device using a reinforcing member besides a sealant. A first substrate includes a pixel region and a non-pixel region, at least one organic light emitting diode...http://www.google.com/patents/US7834550?utm_source=gb-gplus-sharePatent US7834550 - Organic light emitting display and fabricating method of the same
Publication number US7834550 B2
Application number US 11/540,024
Also published as CN103762319A, CN103762319B, EP1811589A2, EP1811589A3, US20070170605
Publication number 11540024, 540024, US 7834550 B2, US 7834550B2, US-B2-7834550, US7834550 B2, US7834550B2
Inventors Jong Woo Lee, Tae Seung Kim, Dae Ho Lim, Ho Seok Lee
Patent Citations (180), Non-Patent Citations (40), Referenced by (44), Classifications (9), Legal Events (4)
US 7834550 B2
Disclosed are an organic light emitting display and a fabricating method of the same, which improve impact resistance and sealing property of a device using a reinforcing member besides a sealant. A first substrate includes a pixel region and a non-pixel region, at least one organic light emitting diode is formed at the pixel region and has a first electrode, an organic layer, and a second electrode, and the non-pixel region is formed at a peripheral portion of the pixel region. A second substrate is bonded to one region of the first substrate having the pixel region. A frit is disposed between the non-pixel region of the first substrate and the second substrate for adhering the first and second substrates to each other. An adhesive being coated to be spaced along a peripheral region of the frit, and including at least two discontinuous portions. A reinforcing member is disposed between the frit and the adhesive.
This application claims the benefit of Korean Patent Application Nos. 10-2006-0025755, filed on Mar. 21, 2006, and 10-2006-0007353, filed on Jan. 24, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
One aspect of the invention provides an organic light emitting display (OLED) device. The device comprises: a first substrate; a second substrate placed over the first substrate, wherein each of the first and second substrates is made of a single layer or comprises a plurality of layers; an array of organic light-emitting pixels interposed between the first and second substrates; and a sealing structure interposed between the first and second substrates while surrounding the array, wherein the sealing structure, the first substrate and the second substrate in combination define an enclosed space in which the array is located; wherein the sealing structure comprises a first member, a second member and a third member, the first member comprising a first material, the second member comprising a second material, and the third member comprising a third material, and wherein the second member is located between and contacts the first and second members.
Hereinafter, embodiments according to the invention will be described with reference to the accompanying drawings. Here, when one element is connected to another element, one element may be either directly connected to another element or indirectly connected to another element via another element. Further, irrelevant elements are omitted for clarity. Also, like reference numerals refer to identical or functionally similar elements.
The pad portion 500 is formed at the first substrate 100 adjacent to the first scan driver 400 and the data driver 500. The pad portion 500 is electrically coupled to the scan supply line 410 and the data supply line 310, and supplies an electric signal to the plurality of scan lines S1, S2, S3, . . . , Sn and the plurality of data lines D1, D2, D3, . . . , Dm of the pixel region 100 a.
The frit 151 is disposed between a non-pixel region 100 b of the first substrate 100 and the second substrate 200, and adheres the first substrate 100 and the second substrate 200 to each other. In the illustrated built-in type scan driver 400, the pixel region 100 a and the scan driver 400 are sealed with the frit 151. In other embodiments, the scan driver 400 may be outside the frit. The frit may only enclose the pixel region 100 a. Since the frit 150 seals a gap between the first substrate 100 and the second substrate 200, an organic light emitting diode interposed between the first substrate 100 and the second substrate 200 can be protected from water or oxygen. The frit 151 may include a filler (not shown) and an absorbent (not shown). The filler may adjust a thermal expansion coefficient. The absorbent absorbs a laser or an infrared ray. Further, the frit 151 may be cured by a laser or ultra-violet ray irradiation. Here, an intensity of the laser irradiated to the frit ranges about 25 to about 60 W.
When a temperature of a glass material is rapidly dropped, a frit in a glass powder form is produced. The frit may include a glass powder and an oxide powder. Further, when organic materials are added to the frit, a frit paste in a gel state is formed. The paste in the gel state is applied along a sealing line of the second substrate. Thereafter, when the frit is sintered at a predetermined temperature, the organic materials are removed, leaving a cured frit in a solid state. In one embodiment, the sintering temperature may range from about 300° C. to about 700° C.
A semiconductor layer 112 may be formed over at least one region of the buffer layer 111. The semiconductor layer 112 includes an active layer 112 a and a source/drain region 112 b. A gate insulation layer 113 is formed over the buffer layer 111, covering the semiconductor layer 112. A gate electrode 114 is formed over one region of the gate insulation layer 113. The gate electrode 114 has a size corresponding to a width of the active layer 112 a.
An interlayer insulation 115 is formed over the gate insulation layer 113, covering have the gate electrode 114. Source and drain electrodes 116 a and 116 b are formed over predetermined regions of the interlayer insulation 115. The source and drain electrodes 116 a and 116 b are coupled to one exposed region of the source/drain region 112 b. A planarization layer 117 is formed on the interlayer insulation 115, covering the source and drain electrodes 116 a and 116 b.
A first electrode 119 is formed on one region of the planarization layer 117. The first electrode 119 is coupled with one exposed region of the source and drain electrodes 116 a and 116 b through a via hole 118.
When a temperature of a glass material is rapidly dropped, a frit in a glass power form is produced. The frit may include a glass powder and an oxide powder. Further, when organic materials are added to the frit, a frit paste in a gel state is formed. The paste in the gel state is applied along a sealing line of the second substrate. Thereafter, when the frit is sintered at a predetermined temperature, the organic materials are removed, leaving a cured a frit in a solid state. In one embodiment, the sintering temperature may range from about 300° C. to about 700° C.
When a temperature of a glass material is rapidly dropped, a frit in a glass power form is produced. The frit may include a glass powder and an oxide powder. Further, when organic materials are added to the frit 151, a paste in a gel state is formed. The paste in the gel state is applied along a sealing line of the second mother substrate 2000 using a first injector 160 a. Thereafter, when the frit 151 is sintered at a predetermined temperature, organic materials are removed, leaving a cured frit in a solid state. In one embodiment, the sintering temperature may range from about 300° C. to about 700° C. (FIG. 5A).
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U.S. Classification 313/512, 445/25, 315/169.3
Cooperative Classification H01L2251/566, Y10T428/10, H01L27/3244, H01L51/5246
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, JONG WOO;KIM, TAE SEUNG;LIM, DAE HO;AND OTHERS;REEL/FRAME:018376/0102