Source: https://patents.google.com/patent/US20070002664A1/en
Timestamp: 2019-03-26 06:45:36
Document Index: 11944246

Matched Legal Cases: ['art 90', 'arts 90', 'arts 90', 'art 90', 'art 90', 'art 90', 'art 90', 'art 90', 'art 112', 'art 98', 'art 98', 'art 98', 'art 98', 'art 94', 'arts 94', 'arts 94', 'art 94', 'art 94', 'art 94', 'art 94', 'art 94']

US20070002664A1 - Semiconductor memory device, and method of controlling the same - Google Patents
US20070002664A1
US20070002664A1 US11/515,852 US51585206A US2007002664A1 US 20070002664 A1 US20070002664 A1 US 20070002664A1 US 51585206 A US51585206 A US 51585206A US 2007002664 A1 US2007002664 A1 US 2007002664A1
US11/515,852
US7869296B2 (en
1999-11-09 Priority to JPHEI11-318458 priority Critical
1999-11-09 Priority to JP11-318458 priority
1999-11-09 Priority to JP31845899 priority
2003-07-22 Priority to US10/623,544 priority patent/US6947347B2/en
2005-07-27 Priority to US11/189,858 priority patent/US7495986B2/en
2006-09-06 Priority to US11/515,852 priority patent/US7869296B2/en
2006-09-06 Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
2007-01-04 Publication of US20070002664A1 publication Critical patent/US20070002664A1/en
2010-07-14 Assigned to FUJITSU SEMICONDUCTOR LIMITED reassignment FUJITSU SEMICONDUCTOR LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU MICROELECTRONICS LIMITED
2011-01-11 Publication of US7869296B2 publication Critical patent/US7869296B2/en
Another object of the present invention is to prevent the-feedthrough current (or leak path) of an internal circuit during a low power consumption mode.
The DRAM is provided with a VII starter 10, a VDD starter 12, a low power entry circuit 1 4, a command decoder 16, an internal voltage generator 18 and a main circuit unit 20. The internal voltage generator 18 has a low-pass filter 22, a reference voltage generator 24, a VDD supplying circuit 26, a booster 28, a precharging voltage generator 30, an internal supply voltage generator 32, a substrate voltage generator 34 and a VSS supplying circuit 36. The main circuit unit 20 has a memory core 38 and a peripheral circuit 40. Here, the low power entry circuit 14 corresponds to the entry circuit 1 shown in FIG. 2, and the VDD supplying circuit 26 and the VSS supplying circuit 36 correspond to the external voltage supplying circuit 3 shown in FIG. 2.
The VII starter 10 receives the internal supply voltage VII and the ground voltage VSS and outputs a start signal STTVII to the main circuit unit 20. The VII starter 10 is resets the main circuit unit 20 after the power supply is switched on until the internal supply voltage VII reaches a predetermined voltage, and it prevents the malfunction of the main circuit unit 20. The VDD starter 12 receives the power supply voltage VDD and the ground voltage VSS and outputs a start signal STTCRX. The VDD starter 12 inactivates the low power entry circuit 1 4 after the power supply is switched on until the power supply voltage VDD reaches a predetermined voltage and it prevents the malfunction of the circuit 14.
The substrate voltage generator 34 is composed of an oscillator 34 a and a pumping circuit 34 b. In response to the high level of a control signal VBBEN, the oscillator 34 a starts the oscillating operation to output an oscillating signal OSC. The pumping circuit 34b has a capacitor for repeating charge and discharge in response to the oscillating signal OSC from the oscillator 34 a, and a diode-connected nMOS transistor connected with one end of the capacitor. The charges of a p-type substrate connected with the anode are discharged by the pumping operation, which lowers the substrate voltage VBB. Making the substrate voltage VBB negative leads to gaining some effects such as reducing the influences of a shift in the threshold voltage of the memory cells due to the substrate effect so that the characteristics of the memory cells may be improved.
The sense amplifier 46 is constructed by connecting the inputs and outputs of two CMOS inverters with each other. Each of these CMOS inverters is connected at its outputs individually with the bit lines /BL and BL. The source of the pMOS and the source of the nMOS of each CMOS inverter are connected with power supply lines PSA and NSA, respectively. The voltages of these power supply lines PSA and NSA individually reach the VPR level during a standby state and during the inactivation of the sense amplifiers, and respectively change to the internal supply voltage VlI and the ground voltage VSS when the bit lines are amplified.
In response to the high level of the ULP signal, the low-pass filter 22 of the internal voltage generator 18 stops the supply of the power supply voltage to the reference voltage generator 24 and instead supplies the ground voltage VSS from the VSS supplying circuit 36. In response to the ground voltage VSS, the reference voltage generator 24 turns the reference voltages VPREF, VPRREFL, VPRREFH and VRFV to the ground level. The nMOS 28 b of the booster 28 shown in FIG. 4 and the nMOS 32 d of the internal supply voltage generator 32 shown- in FIG. 5 are switched off. As a result, the booster 28, the precharging voltage generator 30, the internal supply voltage generator 32 and the substrate voltage generator 34 are inactivated to stop their operations. Thus, all the conventional circuits remaining operative during the low power consumption mode are stopped. Therefore, the power consumption in the low power consumption mode is drastically reduced as compared with the conventional.
When these circuits are inactivated, the generations of the boost voltage VPP, the precharging voltage VPR, the internal supply voltage VlI and the substrate voltage VBB are stopped. However, the boost voltage VPP and the internal supply voltage VII are changed into the power supply voltage VDD by the VSS supplying circuit 36, and the substrate voltage VBB and the precharging circuit VPR are changed into the ground voltage VSS by the VSS supplying circuit 36. Therefore, the internal circuit of the main circuit unit 20 is prevented from having a leak path.
When the low power consumption mode is released, the CE1X signal is first turned to the high level (FIG. 13(j)). The combinational circuit 60 receives the high level of the CE1X signal to turn the node ND3 to the high level (FIG. 13(k)) and the ULP signal to the low level (FIG. 13(l)). 200 μs after the rising edge of the CE1X signal, the CE2Z signal is turned to the high level (FIG. 13(m)). In response to the high level of the CE2Z signal, a level of the node ND1 turns to the high level. During this period of 200 μs, the internal voltage generator 18 is activated to stabilize the individual internal voltages VPP, VPR, VlI and VBB at predetermined levels.
In FIG. 16, a level detecting circuit 74 comprises a differential amplifier 74a including a current mirror circuit and an inverter row 74 b which includes an odd number of inverters and receives the output of the differential amplifier 74 a. The differential amplifier 74 a is activated during the high level of the release signal REL, compares an internal power supply voltage VII with a reference voltage VREF, and outputs the comparison result to an inverter row 74 b. A generator for the internal power supply voltage VII generates a constant value of the internal power supply voltage VII independent of the fluctuation of the power supply voltage VDD supplied from the exterior. On the other hand, the reference voltage VREF varies depending on the fluctuation of the power supply voltage VDD.
The level detecting circuit 80 comprises: a differential amplifier 80 for comparing the internal power supply voltage VII with the reference voltage VREF; an inverter row 80 b including an even number of inverters; a differential amplifier 80 c for comparing a boost voltage VPP of a word line (not shown) with the power supply voltage VDD from the exterior; an inverter row 80 d including an even number of inverters; and an NAND gate 80 e. The boost voltage VPP generated by a booster is formed inside of the chip. The differential amplifiers 80 a and 80 c are identical to the differential amplifier 74 a in FIG. 16 and are activated upon receipt of the high level of the REL signal. The inverter rows 80 b and 80 d are constructed of the inverter in the initial stage and the inverter in the second stage of the inverter row 74 b in FIG. 16. The inverter row 80 b receives the output of the differential amplifier 80 a and outputs the received logic level to a NAND gate 80 e as a start signal STT1X. The inverter row 80 d receives the output of the differential amplifier 80c and outputs the received logic level to the NAND gate 80 e as a start, signal STT2X. The NAND gate 80 e operates as an OR circuit of negative logic and outputs a start signal STTPZ.
Due to the exit from the low power consumption mode, the power supply line of the internal power supply voltage VII and the power supply line of the power supply voltage VDD are disconnected and the generator for the internal power supply voltage VII initiates its operation. The internal power supply voltage VII goes low for some time from the initiation of the generator(FIG. 1.9(f)). The low level of the ST1X signal is output during a period where the internal power supply voltage VII is lower than the reference voltage VREF (for example, 1.25V) (FIG. 19(g)). Similarly, the connection between the power supply line of the boost voltage VPP and that of the power supply voltage VDD is disconnected and the generator for the boost voltage VPP initiates its operation. The boost voltage VPP goes low for some time from the initiation of the generator (FIG. 19(h)). The low level of the STT2X signal is output during a period where the boost voltage VPP is lower than the power supply voltage VDD (FIG. 19(i)).
The NAND gate 80 e in FIG. 18 outputs the high level of the STTPZ signal during a period where the STT1X signal or the STT2X signal is at low level (FIG. 190)). During the high level of the STTPZ signal, the start signal STTVII (FIG. 16)is turned to high level. The start signal STTVII functions as a reset signal and initializes a predetermined internal circuit of the main circuit unit 20 shown in FIG. 3.
This differential amplifier 90 a has a current mirror part 90 c composed of pMOSes, and a pair of differential input parts 90 d and 90 e composed of nMOSes. Both the inputs of the differential input, parts 90 d and 90 e receive the reference voltage VPREF and a control voltage VPP2 which is generated by shifting the level of the boost voltage VPP from the voltage generator 90 b. The differential input part 90 d is connected with the ground line VSS through the nMOS which is always on, and the differential input part 90 e is connected with the ground line VSS through the nMOS which is turned on when the low power signal NAPX is inactivated.
In short, the differential input part 90 d operates at all times, and the differential input part 90 e operates only when the low power signal NAPX is inactivated. During the low power consumption mode, he differential input part 90 e stops its operation so that the power consumption is reduced. The differential amplifier 90 a activates the boost enable signal (to the high level) when the control voltage VPP2 is lower than the reference voltage VPREF.
FIG. 29 shows the detail of the unit 12 of the substrate voltage generator 100.
In the pumping circuit 112 b, the pumping node PND interchangeably has the ground voltage and a negative voltage when the pMOSes and nMOS of the voltage supplying part 112 c and the capacitor 112 d receive the clock signal from the oscillator 112a. When the pumping node PND has a negative voltage, moreover, the electric charge of the substrate node VBB is pumped out to set the substrate node VBB to a negative voltage. The unit 112 stops its operation during the power consumption mode (while the low power signal NAPX is active).
In the detection unit 98 b, the gate of the pMOS of the reference voltage generating part 98 d and the gate of the nMOS 98 g are supplied with the inverted logic of the low power signal- NAPX. The remaining constructions are identical to those of the detection unit 98 a. In this embodiment, the CMOS inverter 98 f outputs the low level in response to the detection result at the level detecting part 98 e (i.e., the voltage of the output node NOUT1) when the substrate voltage VBB rises to −1.0 V in the normal operation mode. The output of the reference voltage generating part 98 d of the detection unit 98 b has the ground voltage VSS (at 0 V) when the low power signal NAPX is at the low level (during the power consumption mode). Therefore, the output node NOUT2 of the level detecting part 98 e has the low level at all times. In short, the detection unit 98 b is inactivated during the power consumption mode.
The differential amplifier 94 a has a current mirror part 94 d composed of pMOSes, and a pair of differential input parts 94 e and 94f composed of nMOSes. Both the inputs of the differential input parts 94 e and 94 f receive the reference voltage VPRREFL and the precharging voltage VPR. The differential input part 94 e is connected with the ground line VSS through the always on nMOS, and the differential input part 94 f is connected with the ground line VSS through the nMOS which is turned on when the low power signal NAPX is inactivated.
The differential input part 94 h operates at all times, but the differential input part 94i operates only when the low power signal NAPX is inactivated. During the low power consumption mode, the differential input part 94 i stops its operation so that the power consumption is reduced. The differential amplifier 94 b sets the output node NOUT4 to the low level when the reference voltage VPRREFH is lower than the precharging voltage VPR.
This oscillator 104 is provided with a ring oscillator 104 a having odd stages of CMOS inverters connected in cascade, and a buffer 104 b for extracting an oscillating signal OSCZ from the ring oscillator 104 a. Frames of broken lines in FIG. 33 are switches for adjusting the stage number (corresponding to the self-refreshing period) of the ring oscillator 104 a. The on/off of these switches are set by the blow of the polysilicon fuse or by the layout pattern of the photomask of the wiring layer. In this example, the stage number of the ring oscillator 104 a is set to “7”. The sources of the pMOSes and the nMOSes of the CMOS inverters are connected with the internal power supply line VII and the ground line VSS, respectively, through the pMOS loads and the nMOS loads. The gates of the pMOS loads and the nMOS loads are controlled with the control voltages PCNTL and NCNTL, respectively. The oscillator 104 has pMOSes and nMOSes for receiving the control of the low power signal NAPX. When the low power signal NAPX is activated, those pMOSes are turned on to fix the predetermined node of the ring oscillator 1.04 a to the high level, but the connections between the nMOSes of the CMOS inverters and the ground line VSS are broken when those nMOSes are turned off. As a result, the oscillator 104 stops its operation during the power consumption mode.
7. A method of operating a semiconductor memory including dynamic memory cells, comprising the step of:
entering a low power consumption mode, in which the dynamic memory cells do not retain data therein by prohibiting refresh operations, in response to a single external control signal supplied from an exterior via an external control terminal.
8. The method of operating a semiconductor memory according to claim 7, wherein the semiconductor memory enters the low power consumption mode in response to a voltage change of the single external control signal from a first voltage to a second voltage.
9. The method of operating a semiconductor memory according to claim 8, wherein the low power consumption mode is maintained while the single external control signal keeps the second voltage.
10. The method of operating a semiconductor memory according to claim 8, wherein the semiconductor memory exits the low power consumption mode in response to a reverse voltage change of the single external control signal from the second voltage to the first voltage.
11. A method of controlling a semiconductor memory including dynamic memory cells, comprising the step of:
outputting a single control signal to an external control terminal of the semiconductor memory so that the semiconductor memory enters a low power consumption mode, in which the dynamic memory cells do not retain data therein by prohibiting refresh operations.
12. The method of controlling the semiconductor memory according to claim 11, further including the step of:
13. The method of controlling the semiconductor memory according to claim 12, further comprising the step of:
14. The method of controlling the semiconductor memory according to claim 13, further comprising the step of:
a first memory including dynamic memory cells, having a low power consumption mode and a data terminal, the low cower consumption mode being a mode in which the dynamic memory cells do not retain data therein by prohibiting refresh operations, and the mode entered in response to a single external control signal supplied from an exterior via an external control terminal; and
16. The memory system according to claim 15, wherein data stored in the dynamic memory cells in the first memory is transferred to the flash memory cells in the second memory before the first memory enters the low power consumption mode.
17. The memory system according to claim 15, wherein data stored in the flash memory cells in the second memory is transferred to the dynamic memory cells in the first memory after the first memory exits the low power consumption mode.
18. A cellular phone having a service state and a waiting state, comprising:
a first memory including dynamic memory cells, having a low power consumption mode, a data terminal, and an external control terminal, the low power consumption mode being a mode in which the dynamic memory cells do not retain data therein while power is on by prohibiting refresh operations, and the external control terminal being for receiving a single external control signal; and
wherein data stored in the dynamic memory cells in the first memory is transferred to the flash memory cells in the second memory then the first memory enters the low power consumption mode in response to the single external control signal upon shifting from the service state to the waiting state, and
wherein the first memory exits the low power consumption mode in response to the single external control signal, and then data stored in the flash memory cells in the second memory is transferred to the dynamic memory cells in the first memory upon shifting from the waiting state to the service state.
19. A method of controlling a first memory including dynamic memory cells, having a low power consumption mode, a first data terminal, and an external control terminal, the low power consumption mode being a mode in which the dynamic memory cells do not retain data therein by prohibiting refresh operations, and the external control terminal being for receiving a single external control signal, and a second memory including flash memory cells and a second data terminal connected with the first data terminal of the first memory, comprising the steps of:
transferring data stored in the flash memory cells in the second memory to the dynamic memory cells in the first memory via the second and first data terminals after the first memory exits the low power consumption mode in response to the single external control signal.
US11/515,852 1999-11-09 2006-09-06 Semiconductor memory device, and method of controlling the same Active US7869296B2 (en)
US11/189,858 Division US7495986B2 (en) 1999-11-09 2005-07-27 Semiconductor memory device, and method of controlling the same
US12/234,969 Division US7688661B2 (en) 1999-11-09 2008-09-22 Semiconductor memory device, and method of controlling the same
US7869296B2 US7869296B2 (en) 2011-01-11
JP4809452B2 (en) 2011-11-09 Dual voltage generator utilizing a single charge pump generator and generation method thereof