Source: http://www.google.com/patents/US8111554?dq=5527183
Timestamp: 2014-10-02 07:09:02
Document Index: 725573911

Matched Legal Cases: ['Application No. 06771257', 'Application No. 200680019739', 'Application No. 200680019739', 'Application No. 2008', 'Application No. 200680019739', 'Application No. 200680019739', 'Application No. 200680019739', 'Application No. 2008', 'Application No. 7028257', 'Application No. 200680019739', 'Application No. 2008', 'Application No. 200680019739', 'Application No. 2008', 'Application No. 200680019739', 'Application No. 200680019739', 'Application No. 095119514']

Patent US8111554 - Starting program voltage shift with cycling of non-volatile memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements...http://www.google.com/patents/US8111554?utm_source=gb-gplus-sharePatent US8111554 - Starting program voltage shift with cycling of non-volatile memoryAdvanced Patent SearchPublication numberUS8111554 B2Publication typeGrantApplication numberUS 12/572,069Publication dateFeb 7, 2012Filing dateOct 1, 2009Priority dateJun 3, 2005Also published asCN101213613A, CN101213613B, CN102385924A, EP1886319A2, US7339834, US7630254, US7633812, US20060274583, US20080130368, US20080137431, US20100020613, WO2006132818A2, WO2006132818A3Publication number12572069, 572069, US 8111554 B2, US 8111554B2, US-B2-8111554, US8111554 B2, US8111554B2InventorsJeffrey LutzeOriginal AssigneeSandisk Technologies Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (35), Non-Patent Citations (32), Referenced by (2), Classifications (7), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetStarting program voltage shift with cycling of non-volatile memoryUS 8111554 B2Abstract A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.
1. A method for operating non-volatile storage elements, comprising:
storing an indicator;
reading the stored indicator;
programming user data in a set of non-volatile storage elements using programming pulses having a first initial magnitude, wherein the first initial magnitude corresponds to the stored indicator and each non-volatile storage element stores multiple bits of data;
calculating an error correction code from the user data;
in response to a request to read the user data, reading the user data from the set of non-volatile storage elements after the programming step using programming pulses having the first initial magnitude, the reading comprises applying read reference voltages to the set of non-volatile storage elements to determine a data state of each of the non-volatile storage elements;
checking the error correction code to determine a number of correctable bit errors of the user data which is read by the step of reading;
changing the indicator to an updated indicator when the number of correctable bit errors exceeds a threshold;
reading the updated indicator; and
programming the set of non-volatile storage elements for multiple programming cycles using programming pulses having a second initial magnitude, wherein the second initial magnitude corresponds to the updated indicator, the second initial magnitude is different than the first initial magnitude.
correcting the correctable bit errors.
the step of programming non-volatile storage elements using programming pulses having the first initial magnitude includes concurrently programming different non-volatile storage elements to different data states; and
the step of programming non-volatile storage elements for multiple program cycles using programming pulses having the second initial magnitude includes concurrently programming different non-volatile storage elements to different data states.
the user data is programmed into one or more pages of the set of non-volatile storage elements, each page comprising one or more sectors; and
the threshold is a predetermined number of at least two correctable bit errors per sector.
the reading comprises, for each of the read reference voltages, testing whether a threshold voltage of each of the non-volatile storage elements is above or below the read reference voltage, the non-volatile storage elements have threshold voltage distributions which correspond to the data states, and the read reference voltages are between the threshold voltage distributions.
the error correction code is stored with the user data in the set of non-volatile storage elements.
the reading of data is performed for a page of data.
9. A system which performs the method of claim 1.
a storage location for an indicator;
one or more control circuits in communication with the set of non-volatile storage elements and the storage location, the one or more control circuits: (a) store the indicator in the storage location, (b) read the stored indicator from the storage location, (c) program user data in the set of non-volatile storage elements using programming pulses having a first initial magnitude, wherein the first initial magnitude corresponds to the stored indicator and each non-volatile storage element stores multiple bits of data, (d) calculate an error correction code from the user data, (e) in response to a request to read the user data, to read the user data from the set of non-volatile storage elements, the one or more control circuits apply read reference voltages to the set of non-volatile storage elements to determine a data state of each of the non-volatile storage elements, (f) check the error correction code to determine a number of correctable bit errors of the user data which is read, (g) change the indicator to an updated indicator when the number of correctable bit errors exceeds a threshold, (h) read the updated indicator, and (i) program the set of non-volatile storage elements for multiple programming cycles using programming pulses having a second initial magnitude, wherein the second initial magnitude corresponds to the updated indicator, the second initial magnitude is different than the first initial magnitude.
CLAIM OF PRIORITY This application is a divisional application of U.S. patent application Ser. No. 12/018,279, now U.S. Pat. No. 7,630,254, �Starting Program Voltage Shift with Cycling of Non-Volatile Memory,� by Lutze, filed on Jan. 23, 2008, which is a continuation application of U.S. patent application Ser. No. 11/144,264, now U.S. Pat. No. 7,339,834, �Starting Program Voltage Shift with Cycling of Non-Volatile Memory,� by Lutze, filed on Jun. 3, 2005, incorporated herein by reference.
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled �Source Side Self Boosting Technique For Non-Volatile Memory,� and in U.S. Patent Application Publication 2005/0024939, titled �Detecting Over Programmed Memory,� filed on Jul. 29, 2003; both applications are incorporated herein by reference in their entirety.
Typically, the program voltage applied to the control gate during a program operation is applied as a series of pulses. In one embodiment, the magnitude of the pulses is increased with each successive pulse by a predetermined step size (e.g. 0.2 v, 0.3 v, 0.2 v, or others). FIG. 1 shows a program voltage signal Vpgm that can be applied to the control gates (or, in some cases, steering gates) of flash memory cells. The program voltage signal Vpgm includes a series of pulses that increase in magnitude over time. In the periods between the program pulses, verify operations are carried out. That is, the programming level of each cell of a group of cells being programmed in parallel is read between successive programming pulses to determine whether it is equal to or greater than a verify level to which it is being programmed. For arrays of multi-state flash memory cells, the memory cells may perform a verification step of each state to allow a determination of whether the cell has reached its data associated verify level. For example, a multi-state memory cell capable of storing data in four states may need to perform verify operations for three compare points.
SUMMARY OF THE INVENTION The technology described herein provides a solution for programming data faster, without increasing the risk of over programming. To achieve this result, one set of programming characteristics are used to program a new device, while another set of programming characteristics are used to program the device after use of that device.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts one example of a program voltage that can be applied to one or more control gates of flash memory devices.
DETAILED DESCRIPTION One example of a non-volatile memory system suitable for implementing the present invention uses the NAND flash memory structure, which includes arranging multiple transistors in series between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 2 is a top view showing one NAND string. FIG. 3 is an equivalent circuit thereof. The NAND string depicted in FIGS. 2 and 3 includes four transistors, 100, 102, 104 and 106, in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to bit line contact 126. Select gate 122 connects the NAND string to source line contact 128. Select gate 120 is controlled by applying the appropriate voltages to control gate 120CG. Select gate 122 is controlled by applying the appropriate voltages to control gate 122CG. Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate. Transistor 100 has control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0. In one embodiment, transistors 100, 102, 104 and 106 are each memory cells. In other embodiments, the memory cells may include multiple transistors or may be different than that depicted in FIGS. 2 and 3. Select gate 120 is connected to select line SGD. Select gate 122 is connected to select line SGS.
C-source control circuit 210 controls a common source line (labeled as �C-source� in FIG. 6) connected to the memory cells. P-well control circuit 208 controls the p-well voltage.
Each distinct threshold voltage range of FIG. 7 corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. One example assigns �11� to threshold voltage range E (state E), �10� to threshold voltage range A (state A), �00� to threshold voltage range B (state B) and �01� to threshold voltage range C (state C). However, in other embodiments, other schemes are used.
FIG. 8 illustrates an example of a two-pass technique of programming a multi-state memory cell that stores data for two different pages: a lower page and an upper page. Four states are depicted: state E (11), state A (10), state B (00) and state C (01). For state E, both pages store a �1.� For state A, the lower page stores a �0� and the upper page stores a �1.� For state B, both pages store �0.� For state C, the lower page stores �1� and the upper page stores �0.� Note that although specific bit patterns have been assigned to each of the states, different bit patterns may also be assigned. In a first programming pass, the cell's threshold voltage level is set according to the bit to be programmed into the lower logical page. If that bit is a logic �1,� the threshold voltage is not changed since it is in the appropriate state as a result of having been earlier erased. However, if the bit to be programmed is a logic �0,� the threshold level of the cell is increased to be state A, as shown by arrow 230. That concludes the first programming pass.
FIG. 9C depicts the process of programming the upper page. If the memory cell is in erased state E and the upper page is to remain at 1, then the memory cell will remain in state E. If the memory cell is in state E and its upper page data is to be programmed to 0, then the threshold voltage of the memory cell will be raised so that the memory cell is in state A. If the memory cell was in intermediate threshold voltage distribution 250 and the upper page data is to remain at 1, then the memory cell will be programmed to final state B. If the memory cell is in intermediate threshold voltage distribution 250 and the upper page data is to become data 0, then the threshold voltage of the memory cell will be raised so that the memory cell is in state C. The process depicted by FIGS. 9A-C reduces the effect of floating gate to floating gate coupling because only the upper page programming of neighbor memory cells will have an effect on the apparent threshold voltage of a given memory cell. An example of an alternate state coding is to move from distribution 250 to state C when the upper page data is a 1, and to move to state B when the upper page data is a 0. Although FIGS. 9A-C provide an example with respect to four data states and two pages of data, the concepts taught by FIGS. 19A-C can be applied to other implementations with more or less than four states and different than two pages. More detail about various programming schemes and floating gate to floating gate coupling can be found in U.S. patent application Ser. No. 11/099,133, titled �Compensating For Coupling During Read Operations Of Non-Volatile Memory,� filed on Apr. 5, 2005.
In one embodiment, fresh devices and used devices can be programmed with different programming parameters by varying the magnitude of the initial programming pulse of the programming signal Vpgm (see e.g. FIG. 1). FIG. 11 is a flow chart describing one embodiment of a process for programming non-volatile memory by varying the magnitude of the initial programming pulse over time. In step 300, the initial programming voltage is set. That is, the device determines the magnitude of the first pulse for the program signal Vpgm. In one example depicted in FIG. 11A, the magnitude of the first pulse of the program voltage applied to the controls gate is 16.9 v. Each successive pulse has a magnitude increased by 0.3 v in comparison to the previous pulse. In step 302, the device is operated for N cycles, where the number N is predetermined in advance or determined on the fly. In step 304, after N cycles, the magnitude of the initial programming pulse for Vpgm is decreased. In one example depicted in FIG. 11B, the magnitude of the first pulse of the program voltage Vpgm applied to the controls gates is decreased to 16.6 v. Each successive pulse has a magnitude increased by 0.3 v in comparison to the previous pulse. In step 306, the device is operated for M cycles (M can be the same or different than N), where the magnitude of the number M is determined in advance or on the fly. In step 308, after operating for N+M cycles, the initial programming voltage is decreased to a new value. In one example depicted in FIG. 11C, the magnitude of the first pulse of the program voltage Vpgm applied to the controls gates is decreased to 16.3 v. Each successive pulse has a magnitude increased by 0.3 v in comparison to the previous pulse. In step 310, the device is operated for an additional P cycles, where the magnitude of P is known in advance or determined on the fly. In step 312, the magnitude of the initial pulse for the program voltage Vpgm is decreased. In one example depicted in FIG. 11D, the magnitude of the first pulse of the program voltage Vpgm applied to the controls gates is decreased to 16.0 v. Each successive pulse has a magnitude increased by 0.3 v in comparison to the previous pulse. In step 314, the device is operated with the new initial pulse. The process of decreasing the magnitude of the initial programming pulse can continue for as many steps as desired.
FIG. 13 is a flow chart describing more details of programming memory cells, where the system counts the number of program cycles and adjusts the magnitude of the initial programming pulse accordingly. The process of FIG. 13 can be performed in response to receiving a request to program data. In step 402, the system will select the appropriate portions of memory to program. This may include selecting a block and/or page and/or sector to write to. At step 404, the cycle count is incremented. The cycle count is a count of the number of programming cycles. The cycle count can be stored in the flash memory array, the state machine, the controller, or another location. In one embodiment, the cycle count is stored in a register associated with the state machine. At step 406, the selected portion of memory is pre-programmed, which provides for even wearing of the flash memory. All memory cells in the chosen sector or page are programmed to the same threshold voltage range. Step 406 is an optional step. At step 408, all the memory cells to be programmed are then erased. For example, step 408 can include moving old memory cells to state E (see FIG. 7-9). At step 410, the system performs a soft programming process. During the erase process, it is possible that some of the memory cells have their threshold voltages lowered to a value that is below the distribution E (see FIG. 7-9). The soft programming process will apply program voltage pulses similar to FIG. 1 to memory cells so that their threshold voltages will increase to be within threshold voltage distribution E. In step 412, the system will access a flag that indicates the magnitude of the initial program pulse. For example, using the table of FIG. 12, if the part had performed 1,000 cycles, the magnitude of the program pulse for the initial pulse will be 16.6 volts. That initial value is set at step 412 by properly programming the charge pump. At step 414, the program count PC will be set to initially be zero. In step 416, a program pulse is applied to the appropriate word line(s). In step 418, the memory cells on that word line(s) are verified to see if they have reached the target threshold voltage level. If all the memory cells have reached the target threshold voltage level (step 420), then the programming process has completed successfully (status=pass) in step 422. If not all the memory cells have been verified, then it is determined in step 424 whether the program count PC is less than 20. If the program count is not less than 20, then the programming process has failed (step 426). If the program count is less than 20, than in step 428, the magnitude of program voltage signal Vpgm is incremented by the step size (e.g. 0.3 v) for the next pulse and the program count PC is incremented. Note that those memory cells that have reached their target threshold voltage are locked out of programming for the remainder of the current programming cycle. After step 428, the process of FIG. 13 continues at step 416 and the next program pulse is applied.
FIG. 15 is a flow chart describing the process for setting the magnitude of the initial pulse for the programming signal Vpgm, which is performed as part of step 412 of FIG. 13. In step 500, the flag written to by the process of FIG. 14 is read. If the flag indicates a large shift (step 502) then the magnitude of the initial pulse for the programming signal Vpgm is set to the initial magnitude less a large shift. Using the example of FIG. 12, the initial programming voltage Vpgm0 associated with a fresh device is 16.9 volts and the large shift is 0.9 volts; therefore, step 504 shifts the magnitude of the initial pulse to 16.0 volts. If the flag does not indicate a large shift (step 502), then the system determines whether the flag indicates a medium shift (step 506). If so, then the magnitude of the first pulse is set to Vpgm0 (e.g., 16.9 v) less a medium shift (e.g., 0.6 v). In the example of FIG. 12, step 508 would set the magnitude of the initial pulse to 16.3 volts. If the flag does not indicate a medium shift, then it is determined whether the flag indicates a small shift (step 510). If the flag indicates a small shift, then the magnitude of the first pulse is set to Vpgm0 less a small shift (e.g., 0.3 v) in step 512. If the flag does not indicate a small shift, then the magnitude of the first pulse remains at Vpgm0 (e.g., 16.9 v).
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