Source: http://www.google.com/patents/US6952370?dq=7,546,338
Timestamp: 2016-05-07 01:34:34
Document Index: 758973482

Matched Legal Cases: ['art 100', 'art 200', 'art 100', 'art 110', 'art 120', 'art 110', 'art 120', 'art 200', 'art 200', 'art 110', 'arts 111', 'art 111']

Patent US6952370 - Data output buffer capable of controlling data valid window in semiconductor ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThe primary objective of the present invention is to provide a data output buffer capable of preventing the phenomenon of a wide data valid window caused from early outputting of the first output data during data output operations. For this purpose, the present invention provides a data output buffer...http://www.google.com/patents/US6952370?utm_source=gb-gplus-sharePatent US6952370 - Data output buffer capable of controlling data valid window in semiconductor memory devicesAdvanced Patent SearchPublication numberUS6952370 B2Publication typeGrantApplication numberUS 10/749,428Publication dateOct 4, 2005Filing dateDec 31, 2003Priority dateMar 20, 2003Fee statusLapsedAlso published asCN1538451A, CN100386819C, US20040189352Publication number10749428, 749428, US 6952370 B2, US 6952370B2, US-B2-6952370, US6952370 B2, US6952370B2InventorsYoung-Jin JeonOriginal AssigneeHynix Semiconductor Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (1), Classifications (16), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetData output buffer capable of controlling data valid window in semiconductor memory devices
US 6952370 B2Abstract
The primary objective of the present invention is to provide a data output buffer capable of preventing the phenomenon of a wide data valid window caused from early outputting of the first output data during data output operations. For this purpose, the present invention provides a data output buffer circuit in a semiconductor memory device which includes: a driving part for receiving pull-up and pull-down control signals and driving a data output terminal with a voltage level corresponding to data read from a memory cell; and a controlling part for supplying the driving part with control signals to delay the first output of the read data for a designated delay time, and to cause the output of the driving part to retain high impedance state during the designated delay time.
driving means for receiving pull-up and pull-down control signals and driving a data output terminal with voltage levels corresponding to data read from a memory cell; and controlling means for supplying the driving means with control signals to delay the first output of the read data for a designated delay time, and to cause the output of the driving means to retain high impedance state during the designated delay time. 2. The data output buffer circuit as recited in claim 1, wherein the controlling means delays the first output of the read data so as to meet the ‘tLZ’ specification, the data output time from an external reference clock.
a latch means for holding pull-up and pull-down control signals corresponding to data read from a memory cell; a data out driver for amplifying and outputting the output of the latch means; and a controlling means for supplying the latch means with control signals to delay the first output of the read data for a designated delay time, and to cause the output of the data out driver to retain high impedance state during the designated delay time. 11. The data output buffer circuit as recited in claim 10, wherein the controlling means delays the first output of the read data so as to meet the ‘tLZ’ specification, the data output time from an external reference clock.
The present invention relates to a data output buffer in semiconductor memory devices, and more particularly to a data output buffer capable of adjusting the data valid window in semiconductor memory devices.
Various loads including output pads, off-chip loads, and measuring apparatuses, reaching about 50 pF in sum, are externally connected with a chip. So, a specially designed buffer, also called as output driver, instead of a conventional buffer is needed in order to drive these high loads.
Referring to FIG. 1, the data output buffer circuit according to the related art includes: a latch 10 for holding ‘NETUP1’ and ‘NETDN1’, which are output data of data control circuits within a chip; a data out driver 30 for outputting amplified data; and a data out pre-driver 20 for driving the data out driver 30.
On the other hand, the ‘NETUP1’ and ‘NETDN1’ signals mentioned above can be viewed as pull-up and pull-down control signals respectively. ‘NETUP1’ and ‘NETUP2’ each other have different logic values owing to the inverter INV. ‘NETDN1’ and ‘NETDN2’ have the same logic values.
While the data are not outputted, the ‘NETUP2’ node maintains ‘logic high’ (hereinafter, referred to as H), the power source voltage level VDD, and also the ‘NETUP2’ node maintains ‘logic low’ (hereinafter, referred to as L), the ground voltage level VSS, so as to disable both a PMOS transistor 30 a and an NMOS transistor 30 a, and cause the output DQ to maintain high impedance state (hereinafter, referred to as Hi-Z). On this occasion, Hi-Z corresponds to the half of the power source voltage level, namely ‘VDD/2’ level. During this time, the data control circuits output logic L to both ‘NETUP1’ and ‘NETDN1’.
When the output DQ is desired to be logic H, the data control circuits set logic H and L to ‘NETUP1’ and ‘NETDN1’ respectively so as to set logic L to both ‘NETUP2’ and ‘NETDN2’. When the output DQ is desired to be logic L, the data control circuits set logic L and H to ‘NETUP1’ and ‘NETDN1’ respectively so as to set logic H to both ‘NETUP2’ and ‘NETDN2’.
Referring to FIG. 3, in reality it is difficult for the Read operation of the DDR SDRAM to meet the ‘tLZ’ specification, the data out impedance time from CLK, in data specifications for a systems company.
As explained above, the fact that the first data output is outputted early in the related art output buffer circuits leads to the difficulty in the satisfaction of the ‘tLZ’ specification, namely +/−700 ps. To solve this problem, namely to meet the ‘tLZ’ specification, trying to delay the output of the data output buffer for an arbitrary time toward the positive direction with reference to the external clock CLK leads to another difficulty in the satisfaction of the skew specification ‘tAC’, the data out access time from CLK, namely +/−700 ps.
The primary objective of the present invention, to overcome the problem mentioned above, is to provide a data output buffer capable of preventing the phenomenon of a wide data valid window caused from early outputting of the first output data during data output operations.
In the related art, the first data output coming early results in an error of the ‘tLZ’ specification. In the circuit of FIG. 1, this error can be corrected by setting logic H to the NETUP2 node and logic L to the NETDN2 for a designated time upon the output of the first data.
The above objectives and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:
To overcome the problem mentioned before by reducing the ‘tLZ’ time, an embodiment of the present invention includes circuits for maintaining Hi-Z, namely VDD/2 voltage level, of the output of the output buffer.
The controlling part 100 plays a role to delay the first data output read from memory cells so as to satisfy the ‘tLZ’ specification, the data out impedance time from CLK, through finely adjusting the DOE signal. The DOE signal maintains logic H during the time when DQ, the output of the driving part 200, is requested to maintain Hi-Z, and maintains logic L during the output time of the read data.
In addition, the controlling part 100 includes a delaying subpart 110 and a switching subpart 120. The delaying subpart 110 generates the DOE_DELAY signal so as to satisfy the ‘tLZ’ specification by delaying the DOE signal. The switching subpart 120 controls the behavior of DQ by switching the inputs to the input terminals NETUP1 and NETDN1 of the driving part 200. The input terminals of the driving part 200 can take logic values either from the delaying subpart 110 for maintaining Hi-Z of DQ, namely both logic L, in response to the DOE_DELAY signal or from other input signals IN1 and IN2 for letting the value of DQ to change according to signals IN1 and IN2.
Two serially connected unit delaying subparts 111, 112 have two outputs: a 2-level delayed output ‘OUT2’ and a 4-level delayed output ‘OUT1’. On this occasion, the DOE_DELAY signal is generated by delaying the DOE signal in order to finely adjust the ‘tLZ’ time, the data out access time from CLK/CLKB, and the delay time of a 2-level inverter is less than or equal to 100 ps in general.
As discussed before, it is desirable to maintain this high impedance state of DQ so as to satisfy the ‘tLZ’ specification. Hence, this high impedance interval of DQ is adjusted by changing the number of levels of the unit delaying subpart 111 and 112, and then by making the DOE_DELAY signal take logic H DQ is outputted in response to the input signals IN1 and IN2.
Accordingly, in the data output buffer circuit of the present invention the ‘tLZ’ specification and the ‘tAC’ specification, data out access time from CLK/CLKB, can be separately adjusted.
In the related art, referring back to the timing diagram of FIG. 3, if all data outputs are delayed by delaying the internal data output in order to meet the ‘tLZ’ specification, the ‘tLZ’ specification of the first data D0 can be met. But, it is difficult to satisfy the consecutive ‘tAC’ specification owing to the + directional skew from the reference clock CLK.
The present invention, however, as shown in FIG. 5, can not only meet the ‘tAC’ specification, difficult to be satisfied in high speed interfaces like DDR SDRAM, but also finely adjust the ‘tLZ’ specification.
Accordingly, as explained above the present invention makes it possible not only to satisfy the data access time, the ‘tAC’ specification, but also to finely adjust the data output time from a reference clock, ‘tLZ’. Consequently, the present invention can greatly enhance the performance of the data output buffer circuit.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5526506Sep 4, 1990Jun 11, 1996Hyatt; Gilbert P.Computer system having an improved memory architectureUS5602999Apr 30, 1990Feb 11, 1997Hyatt; Gilbert P.Memory system having a plurality of memories, a plurality of detector circuits, and a delay circuitUS5708609Sep 5, 1996Jan 13, 1998Winbond Electronics Corp.Semiconductor memory device with dataline undershoot detection and reduced read access timeUS5895960Sep 23, 1997Apr 20, 1999Lucent Technologies Inc.Thin oxide mask level defined resistorUS6034916Oct 14, 1998Mar 7, 2000Samsung Electronics Co., Ltd.Data masking circuits and methods for integrated circuit memory devices, including data strobe signal synchronizationUS6643215 *Dec 19, 2001Nov 4, 2003Samsung Electronics Co., Ltd.Synchronous memory devices with synchronized latency control circuits and methods of operating sameJPH05144944A Title not availableJPH11250666A Title not availableKR20040074901A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleCN101025997BFeb 14, 2007Jun 13, 2012海力士半导体有限公司Data output driving circuit of semiconductor memory apparatusClassifications U.S. Classification365/189.05, 365/233.12, 365/194International ClassificationH03K19/094, G11C7/10, H03K19/0185Cooperative ClassificationG11C7/1057, H03K19/01855, H03K19/09429, G11C7/1051, G11C7/1066European ClassificationG11C7/10R7, G11C7/10R2, H03K19/094M2, G11C7/10R, H03K19/0185B8Legal EventsDateCodeEventDescriptionJun 1, 2004ASAssignmentOwner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JEON, YOUNG-JIN;REEL/FRAME:015410/0790Effective date: 20040426Mar 4, 2009FPAYFee paymentYear of fee payment: 4May 17, 2013REMIMaintenance fee reminder mailedOct 4, 2013LAPSLapse for failure to pay maintenance feesNov 26, 2013FPExpired due to failure to pay maintenance feeEffective date: 20131004RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services