Source: http://www.google.com/patents/US6965987?dq=5,666,293
Timestamp: 2015-05-05 16:45:18
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Matched Legal Cases: ['Application No. 1994', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 1994', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000', 'Application No. 2000']

Patent US6965987 - System and method for handling load and/or store operations in a superscalar ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order...http://www.google.com/patents/US6965987?utm_source=gb-gplus-sharePatent US6965987 - System and method for handling load and/or store operations in a superscalar microprocessorAdvanced Patent SearchPublication numberUS6965987 B2Publication typeGrantApplication numberUS 10/713,145Publication dateNov 15, 2005Filing dateNov 17, 2003Priority dateSep 29, 1992Fee statusLapsedAlso published asUS6230254, US6735685, US6957320, US7447876, US7844797, US7861069, US8019975, US20020188829, US20040128487, US20050188184, US20050283591, US20070101106, US20090217001Publication number10713145, 713145, US 6965987 B2, US 6965987B2, US-B2-6965987, US6965987 B2, US6965987B2InventorsCheryl Senter Brashears, Johannes Wang, Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Te-Li Lau, Sze-Shun Wang, Quang H. TrangOriginal AssigneeSeiko Epson CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (109), Non-Patent Citations (94), Referenced by (5), Classifications (38), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSystem and method for handling load and/or store operations in a superscalar microprocessor
Operation address1 address2 size mask LOAD . . . . . 1001 � 2 bytes 2 bits STORE . . . . . 1000 . . . . . 1011 4 bytes 2 bits If load address 1001 was compared with 1000 and 1011 without masking, no collision would be detected even though the store will actually write to bytes 1000, 1001, 1010 and 1011. If the two LSB's are masked out then the following addresses will result:
Operation address1 address2 size mask LOAD . . . . . 0100 � 4 bytes 2 bits STORE . . . . . 0001 . . . . . 1000 8 bytes 3 bits If three LSB's are masked out then the following addresses will result and the address collision will be detected:
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3346851Jul 8, 1964Oct 10, 1967Control Data CorpSimultaneous multiprocessing computer systemUS3541528Jan 6, 1969Nov 17, 1970IbmImplicit load and store mechanismUS3771138Aug 31, 1971Nov 6, 1973IbmApparatus and method for serializing instructions from two independent instruction streamsUS3789365Jun 3, 1971Jan 29, 1974Bunker RamoProcessor interrupt systemUS3916388May 30, 1974Oct 28, 1975IbmShifting apparatus for automatic data alignmentUS4034349Jan 29, 1976Jul 5, 1977Sperry Rand CorporationApparatus for processing interrupts in microprocessing systemsUS4084235Apr 14, 1975Apr 11, 1978Honeywell Information Systems Inc.Emulation apparatusUS4189768Mar 16, 1978Feb 19, 1980International Business Machines CorporationOperand fetch control improvementUS4189772Mar 16, 1978Feb 19, 1980International Business Machines CorporationOperand alignment controls for VFL instructionsUS4200927Jan 3, 1978Apr 29, 1980International Business Machines CorporationMulti-instruction stream branch processing mechanismUS4228495Dec 19, 1978Oct 14, 1980Allen-Bradley CompanyMultiprocessor numerical control systemUS4236206Oct 25, 1978Nov 25, 1980Digital Equipment CorporationCentral processor unit for executing instructions of variable lengthUS4296470Jun 21, 1979Oct 20, 1981International Business Machines Corp.Link register storage and restore system for use in an instruction pre-fetch micro-processor interrupt systemUS4315314Dec 19, 1979Feb 9, 1982Rca CorporationPriority vectored interrupt having means to supply branch address directlyUS4317170Sep 27, 1979Feb 23, 1982Hitachi, Ltd.Microinstruction controlled data processing system including micro-instructions with data align control featureUS4396982Nov 19, 1980Aug 2, 1983Hitachi, Ltd.Microinstruction controlled data processing system including microinstructions with data align control featureUS4410939Jul 16, 1980Oct 18, 1983Matsushita Electric Industrial Co. Ltd.System for program interrupt processing with quasi-stack of register-setsUS4434461Sep 15, 1980Feb 28, 1984Motorola, Inc.Microprocessor with duplicate registers for processing interruptsUS4454578May 19, 1981Jun 12, 1984Hitachi, Ltd.Data processing unit with pipelined operandsUS4456955Aug 18, 1981Jun 26, 1984Hitachi, Ltd.Alignment of one operand of a two operand arithmetic unitUS4459657Sep 22, 1981Jul 10, 1984Tokyo Shibaura Denki Kabushiki KaishaData processing system having re-entrant function for subroutinesUS4476525Aug 14, 1981Oct 9, 1984Nec CorporationPipeline-controlled data processing system capable of performing a plurality of instructions simultaneouslyUS4514803Apr 26, 1982Apr 30, 1985International Business Machines CorporationMethods for partitioning mainframe instruction sets to implement microprocessor based emulation thereofUS4569016Jun 30, 1983Feb 4, 1986International Business Machines CorporationMechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing systemUS4587612Oct 22, 1982May 6, 1986International Business Machines CorporationAccelerated instruction mapping external to source and target instruction streams for near realtime injection into the latterUS4626989Aug 5, 1983Dec 2, 1986Hitachi, Ltd.Data processor with parallel-operating operation unitsUS4654781Oct 30, 1984Mar 31, 1987Raytheon CompanyByte addressable memory for variable length instructions and dataUS4675806Mar 2, 1983Jun 23, 1987Fujitsu LimitedData processing unit utilizing data flow ordered executionUS4679141Apr 29, 1985Jul 7, 1987International Business Machines CorporationPageable branch history tableUS4714994Apr 30, 1985Dec 22, 1987International Business Machines Corp.Instruction prefetch buffer controlUS4722049Oct 11, 1985Jan 26, 1988Unisys CorporationApparatus for out-of-order program executionUS4734852Aug 30, 1985Mar 29, 1988Advanced Micro Devices, Inc.Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processorUS4739471Jun 28, 1985Apr 19, 1988Hewlett-Packard CompanyMethod and means for moving bytes in a reduced instruction set computerUS4739472Dec 6, 1985Apr 19, 1988Nec CorporationInformation processing device capable of rapidly processing instructions of different groupsUS4752873May 21, 1986Jun 21, 1988Hitachi Vlsi Eng. Corp.Data processor having a plurality of operating units, logical registers, and physical registers for parallel instructions executionUS4758948Nov 2, 1984Jul 19, 1988Inmos LimitedMicrocomputerUS4760519 *Sep 15, 1986Jul 26, 1988Prime Computer, Inc.Data processing apparatus and method employing collision detection and predictionUS4766566Aug 18, 1986Aug 23, 1988International Business Machines Corp.Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processingUS4771376Dec 4, 1986Sep 13, 1988Kabushiki Kaisha ToshibaProcessorUS4777592Jun 16, 1986Oct 11, 1988Nec CorporationInformation processing system comprising a register renewal waiting control circuit with renewal register number registering meansUS4794517 *Apr 15, 1985Dec 27, 1988International Business Machines CorporationThree phased pipelined signal processorUS4807115Oct 14, 1987Feb 21, 1989Cornell Research Foundation, Inc.Instruction issuing mechanism for processors with multiple functional unitsUS4814976Dec 23, 1986Mar 21, 1989Mips Computer Systems, Inc.RISC computer with unaligned reference handling and method for the sameUS4839797Jul 25, 1985Jun 13, 1989Nec CorporationMicroprocessor compatible with any software represented by different types of instruction formatsUS4858105Mar 26, 1987Aug 15, 1989Hitachi, Ltd.Pipelined data processor capable of decoding and executing plural instructions in parallelUS4897810Mar 2, 1989Jan 30, 1990Advanced Micro Devices, Inc.Asynchronous interrupt status bit circuitUS4901228Jul 15, 1987Feb 13, 1990Mitsubishi Denki K.K.Pipelined cache system using back up address registers for providing error recovery while continuing pipeline processingUS4901233Jul 20, 1987Feb 13, 1990International Business Machines CorporationComputer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveriesUS4903196May 2, 1986Feb 20, 1990International Business Machines CorporationMethod and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessorUS4916652Sep 30, 1987Apr 10, 1990International Business Machines CorporationDynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architecturesUS4924376Dec 29, 1986May 8, 1990Nec CorporationSystem for dynamically adjusting the accumulation of instructions in an instruction code prefetched pipelined computerUS4926323Mar 3, 1988May 15, 1990Advanced Micro Devices, Inc.Streamlined instruction processorUS4942520Jul 31, 1987Jul 17, 1990Prime Computer, Inc.Method and apparatus for indexing, accessing and updating a memoryUS4942525Nov 20, 1987Jul 17, 1990Hitachi, Ltd.Data processor for concurrent executing of instructions by plural execution unitsUS4985825Feb 3, 1989Jan 15, 1991Digital Equipment CorporationSystem for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computerUS4992931Dec 24, 1987Feb 12, 1991Kabushiki Kaisha ToshibaData alignment correction apparatus for properly formatting data structures for different computer architecturesUS4992934Mar 30, 1990Feb 12, 1991United Technologies CorporationReduced instruction set computing apparatus and methodsUS4992938Apr 23, 1990Feb 12, 1991International Business Machines CorporationInstruction control mechanism for a computing system with register renaming, map table and queues indicating available registersUS5003462May 31, 1988Mar 26, 1991International Business Machines CorporationApparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt meansUS5051940Apr 4, 1990Sep 24, 1991International Business Machines CorporationData dependency collapsing hardware apparatusUS5075849Dec 30, 1988Dec 24, 1991Hitachi, Ltd.Information processor providing enhanced handling of address-conflicting instructions during pipeline processingUS5101341Sep 2, 1988Mar 31, 1992Edgcore Technology, Inc.Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFOUS5127091Jan 13, 1989Jun 30, 1992International Business Machines CorporationSystem for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processorUS5133072Nov 13, 1986Jul 21, 1992Hewlett-Packard CompanyMethod for improved code generation in reduced instruction set computersUS5133077Jun 5, 1990Jul 21, 1992International Business Machines CorporationData processor having multiple execution units for processing plural classs of instructions in parallelUS5134561Dec 5, 1989Jul 28, 1992International Business Machines CorporationComputer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveriesUS5148528Feb 3, 1989Sep 15, 1992Digital Equipment CorporationMethod and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable lengthUS5148536Jul 25, 1988Sep 15, 1992Digital Equipment CorporationPipeline having an integral cache which processes cache misses and loads data in parallelUS5155843Jun 29, 1990Oct 13, 1992Digital Equipment CorporationError transition mode for multi-processor systemUS5168571Jan 24, 1990Dec 1, 1992International Business Machines CorporationSystem for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte dataUS5185868Jan 16, 1990Feb 9, 1993Advanced Micro Devices, Inc.Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchyUS5193206Aug 10, 1992Mar 9, 1993Motorola, Inc.Reduce instruction set microprocessorUS5226126Feb 21, 1990Jul 6, 1993Nexgen MicrosystemsProcessor having plurality of functional units for orderly retiring outstanding operations based upon its associated tagsUS5230068Feb 26, 1990Jul 20, 1993Nexgen MicrosystemsCache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequenceUS5233694Nov 8, 1989Aug 3, 1993Hitachi, Ltd.Pipelined data processor capable of performing instruction fetch stages of a plurality of instructions simultaneouslyUS5251306Jan 16, 1990Oct 5, 1993Advanced Micro Devices, Inc.Apparatus for controlling execution of a program in a computing deviceUS5261071Mar 21, 1991Nov 9, 1993Control Data System, Inc.Dual pipe cache memory with out-of-order issue capabilityUS5276848Aug 20, 1991Jan 4, 1994International Business Machines CorporationShared two level cache including apparatus for maintaining storage consistencyUS5317740Mar 7, 1991May 31, 1994Digital Equipment CorporationAlternate and iterative analysis of computer programs for locating translatable code by resolving callbacks and other conflicting mutual dependenciesUS5323489Nov 14, 1991Jun 21, 1994Bird Peter LMethod and apparatus employing lookahead to reduce memory bank contention for decoupled operand referencesUS5345569Sep 20, 1991Sep 6, 1994Advanced Micro Devices, Inc.Apparatus and method for resolving dependencies among a plurality of instructions within a storage deviceUS5355460Jul 29, 1993Oct 11, 1994International Business Machines CorporationIn-memory preprocessor for compounding a sequence of instructions for parallel computer system executionUS5371684Mar 31, 1992Dec 6, 1994Seiko Epson CorporationSemiconductor floor plan for a register renaming circuitUS5390355May 27, 1992Feb 14, 1995Tandem Computers IncorporatedComputer architecture capable of concurrent issuance and execution of general purpose multiple instructionsUS5418973Jun 22, 1992May 23, 1995Digital Equipment CorporationDigital computer system with cache controller coordinating both vector and scalar operationsUS5442757Mar 3, 1993Aug 15, 1995Nexgen, Inc.Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interruptsUS5487156 *Dec 5, 1990Jan 23, 1996Popescu; ValeriProcessor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetchedUS5539911Jan 8, 1992Jul 23, 1996Seiko Epson CorporationHigh-performance, superscalar-based computer system with out-of-order instruction executionUS5557763Jun 5, 1995Sep 17, 1996Seiko Epson CorporationSystem for handling load and/or store operations in a superscalar microprocessorUS5561776Jun 6, 1995Oct 1, 1996Hyundai Electronics AmericaProcessor architecture supporting multiple speculative branchingUS5574927Mar 25, 1994Nov 12, 1996International Meta Systems, Inc.RISC architecture computer configured for emulation of the instruction set of a target computerUS5592636Jun 6, 1995Jan 7, 1997Hyundai Electronics AmericaProcessor architecture supporting multiple speculative branches and trap handlingUS5606676Feb 9, 1995Feb 25, 1997Intel CorporationBranch prediction and resolution apparatus for a superscalar computer processorUS5619668Sep 22, 1994Apr 8, 1997Intel CorporationApparatus for register bypassing in a microprocessorUS5619730Sep 6, 1994Apr 8, 1997Mitsubishi Denki Kabushiki KaishaPipelining device in a parallel processing apparatus and an instruction supplying method thereforUS5625837Jun 6, 1995Apr 29, 1997Hyundai Electronics AmericaProcessor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition codeUS5627983Jun 6, 1995May 6, 1997Hyundai Electronics AmericaProcessor architecture providing out-of-order executionUS5651125Jul 10, 1995Jul 22, 1997Advanced Micro Devices, Inc.High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operationsUS5659782 *Sep 16, 1994Aug 19, 1997Seiko Epson CorporationSystem and method for handling load and/or store operations in a superscalar microprocessorUS5689720Feb 15, 1996Nov 18, 1997Seiko Epson CorporationHigh-performance superscalar-based computer system with out-of-order instruction executionUS5708841Sep 17, 1996Jan 13, 1998Hyundai Electronics AmericaProcessor architecture providing speculative, out of order execution of instructionsUS5768575Mar 13, 1995Jun 16, 1998Advanced Micro Devices, Inc.Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructionsUS5778210Jan 11, 1996Jul 7, 1998Intel CorporationMethod and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated timeUS5987593 *Nov 3, 1997Nov 16, 1999Seiko Epson CorporationSystem and method for handling load and/or store operations in a superscalar microprocessorUS6434693 *Nov 12, 1999Aug 13, 2002Seiko Epson CorporationSystem and method for handling load and/or store operations in a superscalar microprocessorUS6735685 *Jun 21, 1999May 11, 2004Seiko Epson CorporationSystem and method for handling load and/or store operations in a superscalar microprocessorUS20020188829 *Jul 9, 2002Dec 12, 2002Senter Cheryl D.System and method for handling load and/or store operations in a superscalar microprocessorUS20030056089 *Jul 1, 2002Mar 20, 2003Seiko Epson CorporationSystem and method for handling load and/or store operations in a superscalar microprocessorJPS60225943A Title not available* Cited by examinerNon-Patent CitationsReference1"Overlap of Store Multiple Operation With Succeeding Operations Through Second Set of General Purpose Registers," IBM Technical Disclosure Bulletin, vol. 28, No. 6, Nov. 1989, New York, NY, pp. 2727-2728.28-Bit Embedded Controller Handbook, Intel, 1989, pp. 1-1 thru 1-19 and 3-1 thru 3-37.3Acosta, Ram�n D. et al., "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Transactions On Computers, vol. C-35, No. 9, Sep. 1986, pp. 815-828.4Agerwala et al., "High Performance Reduced Instruction Set Processors," IBM Research Division, Mar. 31, 1987, pp. 1-61.5Aiken, A. and Nicolau, A., "Perfect Pipelining: A New Loop Parallelization Technique*," pp. 221-235.6Anderson, D.W. et al., "The IBM System/360 Model 91: Machine Philosophy And Instruction-Handling", IBM Journal, Jan. 1967, pp. 8-24.7Andrews, W., "Distinctions Blur Between DSP Solutions," Computer Design, vol. 28, No. 9, May 1, 1989, Littleton, Mass., pp. 86-99.8Bakoglu, H.B. et al., "IBM Second-Generation RISC Machine Organization", 1990 IEEE, pp. 173-178.9Boland, L.J., et al., "The IBM System/360 Model 91: Storage System", IBM Journal, Jan. 1967, pp. 54-68.10Charlesworth, A.E., "An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family," Computer, vol. 14, Sep. 1981, pp. 18-27.11Colwell, R.P. et al., "A VLIW Architecture for a Trace Scheduling Compiler," Proceedings of the 2<SUP>nd </SUP>International Congress on Architectural Support for Programming Languages and Operating Systems, Oct. 5-8, 1987, California, pp. 180-192.12Crawford, J., "The Execution Pipeline of the Intel i486 CPU," IEEE, 1990, pp. 254-258.13Decision of Final Rejection received Oct. 24, 2003 in Japanese Appl. No. JP 2000-008264, (3 pages) with translation (3 pages).14Decision of Final Rejection received Oct. 24, 2003 in Japanese Appl. No. JP 2000-008267, (3 pages) with translation (3 pages).15Decision of Final Rejection received Oct. 24, 2003 in Japanese Appl. No. JP2000-008265, (3 pages) with translation (3 pages).16Decision of Final Rejection received Oct. 24, 2003 in Japanese Appl. No. JP2000-008266, (3 pages) with translation (4 pages).17English-language translation of Japanese Laid-Open Patent Application No. H1-286030, (Nov. 17, 1989-date of publication), 9 pages.18English-language translation of Japanese Laid-Open Patent Application No. H2-130634, (May 18, 1990-date of publication), 56 pages.19English-language translation of Japanese Laid-Open Patent Application No. H2-148238, (Jun. 7, 1990-date of publication), 15 pages.20English-language translation of Japanese Laid-Open Patent Application No. H4-77925, (Mar. 12, 1992-date of publication), 33 pages.21English-language translation of Japanese Laid-Open Patent Application No. S58-217054, (Dec. 16, 1983-date of publication), 18 pages.22English-language translation of Japanese Laid-Open Patent Application No. S59-154548, (Sep. 3, 1984-date of publication), 15 pages.23English-language translation of Japanese Laid-Open Patent Application No. S61-33546, (Feb. 17, 1986-date of publication), 25 pages.24English-language translation of Kuga, M. et al., "Low-Level Parallel Processing Algorithms for the "Shinpu" Processor Based on the SIMP (Single Instruction Stream/Multiple Instruction Pipelining) Method," Transactions of Information Processing Society of Japan, Information Processing Society of Japan, vol. 30, No. 12, Dec. 1989, pp. 1603-1624.25English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 1994-509063, mailed Aug. 27, 2002, 5 pages.26English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 2000-008263, mailed Aug. 14, 2002, 5 pages.27English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 2000-008266, mailed Aug. 14, 2002, 5 pages.28English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 2000-008267, mailed Aug. 16, 2002, 6 pages.29English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 2000-008268, mailed Aug. 14, 2002, 5 pages.30English-language translation of Notification of Reason for Refusal for Japanese Patent Application No. 2000-008271, mailed Aug. 14, 2002, 5 pages.31Faix, M. and Schuenemann, C., "Combined Macro/Micro Program Machine," IBM Technical Disclosure Bulletin, vol. 14, No. 1, Jun. 1971, p. 298.32Foster et al., "Percolation of Code to Enhance Parallel Dispatching and Execution," IEEE Trans. On Computers, Dec. 1971, pp. 1411-1415.33Garth, S.C.J., "Combining RISC and CISC in PC Systems," IEEE, pp. 10/1-10/5.34Goodman, J.R. and Hsu, W., "Code Scheduling and Register Allocation in Large Basic Blocks," ACM, 1988, pp. 442-452.35Gross et al., "Optimizing Delayed Branches," Proceedings of the 5th Annual Workshop on Microprogramming, Oct. 5-7, 1982, pp. 114-120.36Groves, R.D. and Oehler, R., "An IBM Second Generation RISC Processor Architecture," IEEE, 1989, pp. 134-137.37Heath, S., "Architectural considerations for a M88000 superscalar RISC processor," pp. 6/1-6/6.38Hennessy et al., Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Inc., 1990 (in its entirety).39Horst, R.W. et al., "Multiple Instruction Issue in the NonStop Cyclone Processor," IEEE, 1990, pp. 216-226.40Hwu et al., "Checkpoint Repair for the High-Performance Out-of-Order Execution Machines," IEEE Trans. On Computers, vol. C-36, No. 12, Dec. 1987, pp. 1496-1514.41Hwu et al., "Exploiting Parallel Microprocessor Microarchitectures with a Compiler Code Generator," Proceedings of the 15th Annual Symposium on Computer Architecture, Jun. 1988, pp. 45-53.42Hwu et al., "HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality," Proceedings from ISCA-13, Tokyo, Japan, Jun. 2-5, 1986, pp. 297-306.43i486(TM) Microprocessor Hardware Reference Manual, Order No. 240552, Intel Corporation, Santa Clara, California, 1990.44i486(TM) Microprocessor Programmer's Reference Manual, Order No. 240486, Intel Corporation, Santa Clara, California, 1990.45IBM Journal of Research and Development, vol. 34, No. 1, Jan. 1990, pp. 1-70.46Jelemensky, J. et al., "New Microcomputer Features Advanced Hardware For Real-Time Control Applications," Electro Conference Record, vol. 14, Apr. 11, 1989, Los Angeles, CA, pp. 1-9.47Johnson, M., Superscalar Microprocessor Design, Prentice-Hall, 1991, pp. 50-53 and pp. 147-163.48Johnson, M., Superscalar Microprocessor Design, Prentice-Hall, Inc., 1991.49Johnson, William M., Super-Scalar Processor Design, (Dissertation), Copyright 1989, 134 pages.50Jouppi et al., "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines," Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 1989, pp. 272-282.51Jouppi, N.H., "Integration and Packaging Plateaus of Processor Performance," IEEE, 1989, pp. 229-232.52Jouppi, N.P., "The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance," IEEE Transactions on Computers, vol. 38, No. 12, Dec. 1989, pp. 1645-1658.53Keller, R.M., "Look-Ahead Processors," Computing Surveys, vol. 7, No. 4, Dec. 1975, pp. 177-195.54Kuga, M. et al., "Low-Level Parallel Processing Algorithms for the "Shinpu" Processor Based on the SIMP (Single Instruction Stream/Multiple Instruction Pipelining) Method," Transactions of Information Processing Society of Japan, Information Processing Society of Japan, vol. 30, No. 12, Dec. 1989, pp. 1603-1611.55Lam, M.S., "Instruction Scheduling For Superscalar Architectures," Annu. Rev. Comput. Sci., vol. 4, 1990, pp. 173-201.56Lee, R.B., "Precision Architecture," Computer, Jan. 1989, pp. 78-91.57McGeady, S., "The i960CA Superscalar Implementation of the 80960 Architecture", 1990 IEEE, pp. 232-240.58McNeley, K.J. and Milutinovic, V.M., "Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer," IEEE Micro, vol. 7, No. 1, pp. 60-71, Feb. 1987.59Melear, C., "The Design of the 88000 RISC Family," IEEE Micro, vol. 9, No. 2, Apr. 1989, Los Alamitos, CA, pp. 26-38.60Murakami, K. et al., "SIMP (Single Instruction stream/Multiple instruction Pipelining): A Novel High-Speed Single-Processor Architecture," ACM, 1989, pp. 78-85.61Nakano, H. et al., "A 80 Mflops 64-bit Microprocessor for Parallel Computer", IEEE 1991 Custom Integrated Circuits Conference, pp. 15.2.1-15.2.4.62Notification of Reason for Refusal for Japanese Patent Application No. 1994-509063, mailed Aug. 27, 2002, 3 pages.63Notification of Reason for Refusal for Japanese Patent Application No. 2000-008263, mailed Aug. 14, 2002, 3 pages.64Notification of Reason for Refusal for Japanese Patent Application No. 2000-008266, mailed Aug. 14, 2002, 3 pages.65Notification of Reason for Refusal for Japanese Patent Application No. 2000-008267, mailed Aug. 16, 2002, 3 pages.66Notification of Reason for Refusal for Japanese Patent Application No. 2000-008268, mailed Aug. 14, 2002, 3 pages.67Notification of Reason for Refusal for Japanese Patent Application No. 2000-008271, mailed Aug. 14, 2002, 3 pages.68Odnert, D. et al., "Architecture and Compiler Enhancements for PA-RISC Workstations," Proceedings from IEEE Compcon, Feb. 25-Mar. 1, 1991, San Francisco, CA, pp. 214-218.69Ohr, S., "Superlong instructions help supermini refine number crunching," Electronic Design, vol. 33, No. 26, Nov. 1985.70Patent Abstracts of Japan, vol. 009, No. 006 (P-326), Jan. 11, 1985.71Patent Abstracts of Japan, vol. 010, No. 089, Apr. 1986, & JP, A, 60 225 943 (Hitachi Seisakusho K K) Nov. 11, 1985.72Patent Abstracts of Japan, vol. 017, No. 082 (P-1489), Feb. 18, 1993.73Patent Abstracts of Japan, vol. 017, No. 084 (P-1490), Feb. 19, 1993.74Patt et al., "Critical Issues Regarding HPS, A High Performance Microarchitecture," Proceedings of the 18th Annual Workshop on Microprogramming, Dec. 1985, pp. 109-116.75Patt et al., "HPS, A New Microarchitecture: Rationale and Introduction," Proceedings of the 18th Annual Workshop on Microprogramming, Dec. 1985, pp. 103-108.76Pleszkun et al., "The Performance Potential of Multiple Functional Unit Processors," Proceedings of the 15th Annual Symposium on Computer Architecture, Jun. 1988, pp. 37-44.77Pleszkun et al., "WISQ: A Restartable Architecture Using Queues," Proceedings of the 14th International Symposium on Computer Architecture, Jun. 1987, pp. 290-299.78Popescu, V. et al., "The Metaflow Architecture," IEEE Micro, Jun. 1991, pp. 10-13 & 63-73.79Smith et al., "Implementation of Precise Interrupts in Pipelined Processors," Proceedings of the 12th Annual International Symposium on Computer Architecture, Jun. 1985, pp. 36-44.80Smith et al., "Limits on Multiple Instruction Issue," Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 1989, pp. 290-302.81Smith, J.E. et al., "Implementing Precise Interrupts in Pipelined Processors," IEEE Transactions on Computers, vol. 37, No. 5, May 1998, pp. 562-573.82Smith, M.D. et al., "Boosting Beyond Static Scheduling in a Superscalar Processor," IEEE, 1990, pp. 344-354.83Sohi et al., "Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors," 14<SUP>th </SUP>Int'l Symposium on Computer Architecture, Jun. 2-5, 1987, pp. 27-34.84Tetsuya Hara et al., "Organizations of An Extended Superscalar Processor Prototype Based on the SIMP (Single Instruction Stream/Multiple Instruction Pipelining) Architecture", Electronic Information Communication Society Technical Research Report CPSY90-38-63, Electronic Information Communication Society, Inc., Jul. 20, 1990, vol. 90, No. 144, pp 103-108 (with English language translation, 14 pages).85Thornton, J.E., Design of a Computer: The Control Data 6600, Control Data Corporation, 1970, pp. 58-140.86Tjaden et al., "Detection and Parallel Execution of Independent Instructions," IEEE Trans. On Computers, vol. C-19, No. 10, Oct. 1970, pp. 889-895.87Tjaden et al., "Representation of Concurrency with Ordering Matrices," IEEE Trans. On Computers, vol. C-22, No. 8, Aug. 1973, pp. 752-761.88Tjaden, Representation and Detection of Concurrency Using Ordering Matrices, (Dissertation), 1972, pp. 1-199.89Tomasulo, R.M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal, vol. 11, Jan. 1967, pp. 25-33.90Uht, A.K., "An Efficient Hardware Algorithm to Extract Concurrency From General-Purpose Code," Proceedings of the 19th Annual Hawaii International Conference on System Sciences, 1986, pp. 41-50.91Wedig, R.G., Detection of Concurrency In Directly Executed Language Instruction Streams, (Dissertation), Jun. 1982, pp. 1-179.92Weiss et al., "Instruction Issue Logic in Pipelined Supercomputers," Reprinted from IEEE Trans. on Computers, vol. C-33, No. 11, Nov. 1984, pp. 1013-1022.93Weiss, R., "Third-Generation RISC Processors," EDN, Mar. 30, 1992, pp. 96-108.94Wharton, J. J., "Parallel 486 pipelines produce peak processor performance," Microprocessor Report, vol. 3, No. 6, Jun. 1989, p13(5).Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7257699 *Feb 14, 2005Aug 14, 2007Sun Microsystems, Inc.Selective execution of deferred instructions in a processor that supports speculative executionUS8644051 *Sep 12, 2011Feb 4, 2014Kabushiki Kaisha ToshibaSemiconductor memory device and control method of the sameUS8935468 *Dec 31, 2012Jan 13, 2015Cadence Design Systems, Inc.Audio digital signal processorUS20120002457 *Sep 12, 2011Jan 5, 2012Kazushige KandaSemiconductor memory device and control method of the sameUS20140189231 *Dec 31, 2012Jul 3, 2014Tensilica, Inc.Audio Digital Signal Processor* Cited by examinerClassifications U.S. Classification712/245, 712/23, 711/214, 712/E09.037, 712/206, 712/E09.048, 712/E09.054, 712/E09.046, 712/219, 712/E09.033, 712/207, 712/230, 711/201International ClassificationG06F9/312, G06F9/00, G06F9/38, G06F9/318Cooperative ClassificationG06F9/3836, G06F9/3834, G06F9/30087, G06F9/3885, G06F9/30043, G06F9/3017, G06F9/3004, G06F9/3838, G06F9/3857, G06F9/3855European ClassificationG06F9/38D1, G06F9/30U, G06F9/30A2L, G06F9/30U2, G06F9/38T, G06F9/38E, G06F9/30A2, G06F9/30A8S, G06F9/38D, G06F9/38D4, G06F9/38E6Legal EventsDateCodeEventDescriptionJan 7, 2014FPExpired due to failure to pay maintenance feeEffective date: 20131115Nov 15, 2013LAPSLapse for failure to pay maintenance feesJun 28, 2013REMIMaintenance fee reminder mailedApr 15, 2009FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services