Source: http://www.google.com/patents/US5802057?dq=6,757,682
Timestamp: 2013-12-11 11:45:52
Document Index: 794649280

Matched Legal Cases: ['art 1', 'art 2', 'art 3', 'art 1', 'art 2', 'art 3']

Patent US5802057 - Fly-by serial bus arbitration - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsIn a first embodiment, multi-speed concatenated packet strings are transmitted by a first node on a serial bus. To accommodate multi-speed packets, a speed signal is transmitted immediately prior to the packet. In a second embodiment, ACK-concatenation is used to allow a node to transmit a data packet...http://www.google.com/patents/US5802057?utm_source=gb-gplus-sharePatent US5802057 - Fly-by serial bus arbitrationPublication numberUS5802057 APublication typeGrantApplication numberUS 08/565,690Publication dateSep 1, 1998Filing dateDec 1, 1995Priority dateDec 1, 1995Fee statusPaidAlso published asUS6385679, US6711173, US6721330, US6763414, US6904044, US8155112, US20020103947, US20020188783, US20030037161, US20030055999, US20040246959Publication number08565690, 565690, US 5802057 A, US 5802057A, US-A-5802057, US5802057 A, US5802057AInventorsWilliam S. Duckwall, Michael D. TeenerOriginal AssigneeApple Computer, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (5), Non-Patent Citations (4), Referenced by (81), Classifications (20), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetFly-by serial bus arbitrationUS 5802057 AAbstract In a first embodiment, multi-speed concatenated packet strings are transmitted by a first node on a serial bus. To accommodate multi-speed packets, a speed signal is transmitted immediately prior to the packet. In a second embodiment, ACK-concatenation is used to allow a node to transmit a data packet immediately after transmitting an acknowledge signal on the bus. The data packet need not be related to the ACK packet. In a third embodiment, a node which receives a first data packet followed by a data end signal on a child port, concatenates a second data packet onto the first data packet during retransmission. The second data packet is also transmitted down the bus in the direction of the node which originally transmitted the first data packet.
What is claimed is: 1. In an electronic system, a method of transmitting data packets on a serial bus configured in accordance with the IEEE-1394 Serial Bus Standard by a first node of the bus, the method comprising the steps of:transmitting a first speed signal for a first data packet to be transmitted on the serial bus by the first node; transmitting the first data packet at the first speed on the serial bus by the first node; transmitting a second speed signal for a second data packet to be transmitted on the serial bus by the first node; and transmitting the second data packet at the second speed on the serial bus by the first node. 2. A method of transmitting data packets on a serial bus as in claim 1 wherein the first node comprises a physical layer and a link layer.
3. A method of transmitting data packets on a serial bus as in claim 2 wherein the first speed signal is part of a first data prefix signal.
4. In an electronic system, a method for arbitrating for control of a bus by a first node of the bus, the method comprising the steps of:receiving a first packet transmitted on the bus at the first node; transmitting an acknowledge packet in response to the first packet on the bus by the first node without first requesting access to the bus; and transmitting a second packet which is concatenated onto the acknowledge packet on the bus by the first node wherein the first node does not request access to the bus prior to transmitting the second packet, and wherein the second packet includes a speed signal for the second packet. 5. A method for arbitrating for control of a bus as in claim 4 wherein the first node having a local timer, the timer for timing cycle intervals such that when the timer indicates that a new cycle start packet is due, the first node ceases to request the bus until after the arrival of a cycle start packet.
6. In an electronic system, a method for arbitrating for control of a bus by a first node of the bus, the first node having at least one child port and one other port, the method comprising the steps of:receiving a first packet transmitted on the bus on the child port of the first node; retransmitting the first packet received on the child port on the bus by the first node on the other port; and transmitting a second packet which is concatenated onto the first packet retransmitted on the bus by the first node on the other port wherein the first node does not request access to the bus prior to transmitting the second packet. 7. A method for arbitrating for control of a bus as in claim 6 further comprising the step of transmitting the second packet on the bus by the first node on the child port which received the first packet.
8. A method for arbitrating for control of a bus as in claim 6 wherein the first packet includes a data end string at the conclusion of the first packet and the step of retransmitting the first packet includes stripping the data end string from the first packet before transmitting the second packet.
9. A serial bus configured in accordance with the IEEE-1394 Serial Bus Standard and comprising:a plurality of nodes including a first node; a plurality of communications links interconnecting the nodes, wherein the first node transmits data packets on the serial bus by transmitting a first speed signal for a first data packet, transmitting the first data packet at the first speed, transmitting a second speed signal for a second data packet, and transmitting the second data packet at the second speed. 10. A serial bus as in claim 9 wherein the first node transmits the second speed signal without requesting access to the bus.
11. A serial bus as in claim 10 wherein the first node comprises a physical layer and a link layer.
12. A serial bus as in claim 11 wherein the first speed signal is part of a first data prefix signal.
13. A serial bus comprising:a plurality of nodes including a first node; a plurality of communications links interconnecting the nodes, wherein the first node arbitrates for control of the bus by receiving a first packet transmitted on the bus; transmitting an acknowledge packet in response to receiving the first packet without first requesting access to the bus; and transmitting a second packet which is concatenated onto the acknowledge packet without requesting access to the bus prior to transmitting the second packet, and wherein the second packet includes a speed signal for the second packet. 14. A serial bus claim 13 wherein the first node comprises a local timer, the timer for timing cycle intervals such that when the timer indicates that a new cycle start packet is due, the first node ceases to request the bus until after the arrival of the cycle start packet.
The computer system of FIG. 2 comprises a central processing unit (CPU) 10, a monitor 18, a printer 26, a hard drive 32, a scanner 36, a keyboard 42, and a mouse 46. The CPU 10 includes an internal hard drive 14. Each of the devices of the computer system is coupled to a node of the serial bus. In general, the device to which a node is coupled acts as the "local host" for that node. For example, the CPU 10 is the local host for the CPU node 12; the monitor 18 is the local host for the monitor node 16; the printer 26 is the local host for printer node 24; the hard drive 32 is the local host for the hard drive node 30; the scanner 36 is the local host for the scanner node 34; the keyboard 42 is the local host for keyboard node 40; the mouse 46 is the local host for mouse node 44; and the internal hard drive 14 is the local host for the internal hard drive node 15. It is not necessary for every node to have a local host, nor is it necessary that the local host always be powered.
A point-to-point link such as cable 20 is used to connect two nodes to one another. The CPU node 12 is coupled to internal hard drive node 15 by an internal link 21, to monitor node 16 by cable 20, and to keyboard node 40 by a cable 20e. The keyboard node 40 is coupled to the mouse node 44 by a cable 20f. The monitor node 16 is coupled to the nodes of other peripherals (not shown) by cable 20a and to the printer node 24 by cable 20b. The printer node 24 is coupled to the hard drive node 30 by cable 20c and to the scanner node 34 by cable 20d. Each of the cables 20-20f and the internal link 21 may be constructed in accordance with the P1394 Serial Bus Standard and includes a first differential signal pair for conducting a first signal, a second differential signal pair for conducting a second signal, and a pair of power lines.
There are two situations in the 1394 serial bus protocol in which a node can begin bus arbitration immediately after transmitting or retransmitting a data packet. The first case is isochronous arbitration. Since there are no acknowledge packets sent in response to isochronous packets, the nodes can begin arbitrating for the bus immediately. Second, immediate arbitration can occur during asynchronous arbitration if the last packet seen by the node was an acknowledge packet. Again, this is because there are no acknowledge packets sent in response to an acknowledge packet, so arbitration may begin immediately. This latter situation is not covered by the P1394 Serial Bus Standard, however, it is the subject of United States Patent Application Ser. No. 08/316,552 now U.S. Pat. No. 5, 495, 481, entitled "Method and Apparatus for Accelerating Arbitration In A Serial Bus By Detection of Acknowledged Packets," assigned to the Assignee of the present invention.
FIG. 5 shows the timing for typical concatenated packet transmission operations. In the diagram, D.sub.0 through D.sub.n are the data symbols of the packet, and ZZ represents a high impedance state. When the link 50 requests access to the serial bus, the phy 52 arbitrates for access. If the phy 52 wins the arbitration, it grants the bus to the link 50 by asserting transmit for one SClk cycle, followed by idle for one cycle. After sampling the transmit state from the phy 52, the link 50 takes over control of the interface by asserting either hold or transmit on the control bus 56. The link 50 asserts hold to keep ownership of the bus while preparing data. The phy 52 asserts the data on state on the serial bus during this time. When it is ready to begin transmitting a packet, the link 50 asserts transmit on the control bus 56 along with the first bits of the packet. After sending the last bits of the packet, the link asserts either idle or hold on the control bus 56 for one cycle, and then idle for one additional cycle before tri-stating the bus.
In accordance with the methods of the present invention, however, there is no requirement that the multiple packets be transmitted at the same speed. As shown in FIG. 6, multi-speed concatenated packet transmission is allowed for by providing a method for the link 50 to assert a new speed code for the next data packet on Data 0:1!. This allows the phy to send the appropriate speed signal on the serial bus as it sends out data prefix between packets. The change is included in the figure as *spd.
As noted above, when the link 50 is finished sending the last packet for the current bus ownership, it releases the bus by asserting idle on the control bus 56 for two SClk cycles. The phy 52 begins asserting idle on the control bus 56 one clock cycle after sampling idle from the link 50. It will be appreciated that whenever the data and control bus lines change "ownership" between the phy 52 and the link 50, there is an extra clock period allowed so that both sides of the interface can operate on registered versions of the interface signals, rather than having to respond to a control state on the next cycle.
The amount of time/bandwidth which will be saved using this method depends upon the transmitting node's distance from the root. For the root itself, the time saved is very slight, since the arbitration delay is ordinarily virtually zero. However, for a node five phys away from the root, the normal arbitration time is over a microsecond--enough time to transmit 100 to 400 bits of data depending on whether the transmit speed is 100, 200 or 400 Mbits per second.
This method does involve some higher level complication, however. For isochronous operation, the 1394 bus depends on having arbitration intervals between asynchronous packets so that the root node can successfully arbitrate for the bus. In fact, the root node uses a higher priority request, thereby insuring that it will win an arbitration cycle so that it can send a cycle start packet and begin isochronous arbitration. The above ACK-concatenation method could "break" the higher level isochronous protocol. That is, nodes could ricochet packets and ACKs around the bus for some time without resorting to a normal arbitration cycle. From the root's standpoint, the bus would be out of control.
Fortunately, however, this "out-of-control" situation is avoided because the link hardware already has the capability to avoid the situation. According to the P1394 Serial Bus Standard, each link has a timer which "goes off" when it is time for the next cycle start packet to be sent (or received). According to the P1394 Serial Bus Standard, only the root/cycle master node pays attention to the timer for arbitration purposes. When the timer goes off, the root sends a special priority bus request to its phy, which then arbitrates for the bus (and naturally wins).
Given that functional changes must be implemented in the link to enable ACK-concatenation without breaking 1394 bus protocol, phy ICs must be able to discriminate between links which have this capability and those which do not. Three possible methods present themselves, although other methods may also be used. First, a phy pin, which would be tied high or low at the time of board manufacture, to indicate to the phy whether ACK-concatenation is to be enabled or disabled could be used. Second, a register bit which could be written high (or low) by the link to enable ACK-concatenation could be used. This bit would be low (or high) after power-up reset, disabling ACK-concatenation. Third, one of the P1394 Serial Bus Standard reserved link request codes could be used for "fair bus request with ACK-concatenation".
ISOCHRONOUS RETRANSMISSION As discussed above, retransmission means that when the phy receives a packet on its port X, it retransmits the same packet on its port Y. Pursuant to the P1394 Serial Bus Standard, a phy can begin arbitration for the bus immediately after it completes retransmission. With regard to the packet concatenation methods of the present invention, then, there are two cases of interest: First, a phy can receive a packet on its parent port (i.e., the port leading up to the root node). In general, multiple phys may be receiving the packet at the same time, due to the branched tree topology of the bus. There is no way to effectively concatenate an extra packet in this case because there is no way to guarantee that other phys are not simultaneously doing the same thing. The scenario would lead to packet collisions. Second, a phy can receive a packet on a child port (i.e., a port directed away from the root node). This is a more useful scenario. Reception of a packet on a child port is a unique event on the bus. To be more precise, only one phy at a time on a branching topology serial bus can possibly detect the "end of packet" for a packet received on a child port.
FIG. 9, however, illustrates a packet sent by a branch node T. It's two child nodes C receive the packet simultaneously on their parent ports. T's parent port P also receives the packet. But node P is unique; it receives the packet on a child port. All three nodes P, C and C, may well detect "end of packet" simultaneously, but no other node in the network will detect "end of packet" for a packet received on a child port at the same time as P. So, in this specific case (reception of an isochronous packet on a child port) if the receiving node has its own isochronous packet that it needs to send, then it could dispense with arbitration and simply concatenate its isochronous packet onto the tail end of the received packet on the fly. FIG. 10 illustrates the chain of events for this embodiment of fly-by arbitration.
As shown in FIG. 10a, packet reception begins when a "data prefix" reaches the phy. Then, in FIG. 10b, retransmission begins with the data prefix being retransmitted by the phy. In FIG. 10c, the phy has completed retransmitting the data prefix and now continues retransmitting the data packet. This process continues in FIG. 10d.
The one practical limitation here is that in normal 1394 bus arbitration, isochronous bus arbitration wins tend to start at the root and work down the branches to the periphery of the bus. Thus, by the time a given node receives an isochronous packet on a child port, it will tend to have already transmitted its isochronous packets. The utility of this case (child port isochronous packet reception/concatenation) increases considerably if some additional mechanism is employed to get the bus grants out to the edges of the bus. One such method of doing so would be to employ the token style serial bus arbitration described in co-pending United States patent application Ser. No. 08/565,986 entitled Token Style Arbitration on a Serial Bus, assigned to the Assignee of the present invention. To summarize this method briefly, in token style isochronous arbitration the root node drops an unrequested bus grant down a daisy chain of nodes. The Nth node in the daisy chain then uses the grant to send its packets. Its terminal packet concludes with an encoding which signifies to its parent node that it has completed transmission, i.e., the grant is being passed back up. The next node then sends its packets, etc.
ASYNCHRONOUS RETRANSMISSION In this fourth case, when a node receives an ACK packet, it can immediately begin arbitrating for the bus as detailed in co-pending United States Patent Application Ser. No. 08/316,552 now U.S. Pat. No. 5,495,481, entitled Method and Apparatus for Accelerating Arbitration in a Serial Bus by Detection of Acknowledge Packets, assigned to the assignee of the present invention. As is discussed above, if the received ACK packet comes into a child port, the receiving node can dispense with arbitration all together, and simply concatenate its packet onto the ACK packet. Thus, the bus would end up with an ACK from one node concatenated onto an unrelated packet, perhaps at a different bit rate, from a different node entirely. However, for receiving nodes, at the link level, these concatenated packets appear simply as a series of packets. Indeed, the link has no way of determining whether a series of received packets were or were not concatenated together.
FIGS. 10a-10g illustrate the chain of events for one embodiment of the fly-by bus arbitration of the present invention.
The Institute of Electrical and Electronic Engineers (IEEE) has promulgated a number of different bus architecture standards, including IEEE standards document P1394, entitled P1394 High Performance Serial Bus, draft 8.0v3 (hereinafter the "P1394 Serial Bus Standard"). A typical serial bus having the P1394 standard architecture is comprised of a multiplicity of nodes that are interconnected via point-to-point links such as cables that each connect a single node of the serial bus to another node of the serial bus. Data packets are propagated throughout the serial bus using a number of point-to-point transactions, wherein a node that receives a packet from another node via a first point-to-point link retransmits the received packet via other point-to-point links. A tree network configuration and associated packet handling protocol insures that each node receives every packet once. The serial bus of the P1394 Serial Bus Standard may be used as an alternate bus for the parallel back plane bus of a computer system, as a low cost peripheral bus, or as a bus bridge between architecturally compatible buses.
The communications protocol of the P1394 Serial Bus Standard specifies two primary types of bus access: asynchronous access and isochronous access. Asynchronous access may be either "fair" or "cycle-master." Cycle-master access is used by nodes that need the next available opportunity to transfer data. Isochronous access is used by nodes that require guaranteed bandwidth. The transactions for each type of bus access are comprised of at least one "subaction," wherein a subaction is a complete one-way transfer operation.
FIGS. 1A-1C show different subactions according to the P1394 Serial Bus Standard. FIG. 1A shows a subaction for a fair write transaction. FIG. 1B shows a fair broadcast transaction. FIG. 1C shows a pair of concatenated subactions used for fair read and lock transactions. The subaction 1a of FIG. 1A includes an arbitration phase 2, a data transfer phase 3, and an acknowledge phase 4. During the arbitration phase 2, the arbitration protocol determines which of the nodes that have requested fair access to the serial bus will be granted control of the serial bus. The node that is granted control of the serial bus transmits a data packet on the serial bus during the data transfer phase 3. For some fair subactions, an acknowledge packet is used to signal receipt of the data packet, and the acknowledge phase 4 is provided so that a destination node may transmit such an acknowledge packet. To transmit the acknowledge packet, the destination node seizes control of the bus without arbitrating for control of the bus. An idle period 5 occurs between the data transfer phase 3 and acknowledge phase 4. Acknowledge packets are not required for fair broadcast transactions. Accordingly, FIG. 1B shows asynchronous broadcast subaction 1b, which merely includes the arbitration phase 2 and the data transfer phase 3.
Two subactions are typically required to complete a read or lock transaction; however, separate arbitration phases are not required for a subaction of the transaction. As shown in FIG. 1C, two subactions 1c and 1d are concatenated together such that there is a single arbitration phase followed by a first data transfer phase, a first idle period, a first acknowledge phase, a second data transfer phase, a second idle period, and a second acknowledge phase.
As shown in each of FIGS. 1A-1C, a period of idle time called a subaction gap 6 occurs after a subaction or a concatenated pair of subactions. The subaction gaps 6 shown as preceding each of the subactions 1a, 1b and 1c are the subaction gap 6 that occur after a previous subaction (not shown). Each subaction gap 6 is a constant amount of time, T.sub.SA, that, according to the P1394 Serial Bus Standard, a node must remain idle before it is allowed to initiate the beginning of the arbitration phase for the next subaction. The subaction gap time T.sub.SA is typically set by system software when the serial bus is initialized.
The insertion of a subaction gap 6 between fair subactions is a result of a simple mechanism used by each node of a typical P1394 serial bus to regulate arbitration timing. For asynchronous bus traffic, each node waits for at least a subaction gap after data transfer before requesting control of the bus. This timing is enforced whether the data transferred by a node is a data packet or an acknowledge packet. The duration of subaction gap 6 is selected to insure that an acknowledge packet is allowed to propagate through the serial bus to the source node before the nodes begin arbitrating for control of the bus. The subaction gap time T.sub.SA is guaranteed to be of adequate duration if it is defined to be greater than a worse case round trip delay time T.sub.RT of the serial bus to insure that a possible acknowledge packet is allowed to propagate throughout the serial bus before the nodes begin the arbitration phase of the next subaction. The delay time T.sub.RT includes the round trip propagation delay between the two nodes of the serial bus having the greatest intervening timing delay. The round-trip propagation delay T.sub.RT between the nodes is measured from the time that the source node completes transmission of the data packet to the time that the source node begins reception of the acknowledge packet.
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determinationWO2000052899A1 *Feb 21, 2000Sep 8, 2000Thomson Brandt GmbhMethod and apparatus for transferring data on a bus to or from a device to be controlled by said bus* Cited by examinerClassifications U.S. Classification370/408, 370/462, 370/465, 370/447International ClassificationH04L29/08, H04L12/64, H04L12/40, H04L29/06Cooperative ClassificationH04L12/40136, H04L12/40058, H04L29/06, H04L12/40084, H04L12/417, H04L29/06163, H04L29/08018, H04L29/08027European ClassificationH04L12/40M1, H04L29/06, H04L12/40F1, H04L12/40F5Legal EventsDateCodeEventDescriptionJan 29, 2010FPAYFee paymentYear of fee payment: 12May 29, 2007ASAssignmentOwner name: APPLE INC., CALIFORNIAFree format text: CHANGE OF NAME;ASSIGNOR:APPLE COMPUTER, INC.;REEL/FRAME:019382/0050Effective date: 20070109Feb 3, 2006FPAYFee paymentYear of fee payment: 8Feb 28, 2002FPAYFee paymentYear of fee payment: 4Dec 1, 1995AS02Assignment of assignor's interestOwner name: APPLE COMPUTER, INC. 1 INFINITE LOOP CUPERTINO, CAOwner name: DUCKWALL, WILLIAM S.Effective date: 19951201Owner name: TEENER, MICHAEL D.RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google