Source: http://www.google.fr/patents/US6025220
Timestamp: 2013-05-25 14:41:16
Document Index: 469380367

Matched Legal Cases: ['art 2', 'art 2', 'art 1', 'art 1', 'art 1', 'art 1']

Brevet US6025220 - Method of forming a polysilicon diode and devices incorporating such diode - Google�BrevetsRecherche Images Maps Play YouTube Actualit�s Gmail Drive Plus » Recherche avanc�e dans les brevets | Historique Web | Connexion Recherche avanc�e dans les brevets BrevetsA method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material, by methods such as conformal deposition, leaving...http://www.google.fr/patents/US6025220?utm_source=gb-gplus-shareBrevet US6025220 - Method of forming a polysilicon diode and devices incorporating such diode Num�ro de publicationUS6025220 AType de publicationOctroi Num�ro de demande08/665,325 Date de publication15 f�vr. 2000 Date de d�p�t18 juin 1996 Date de priorit�18 juin 1996Autre r�f�rence de publicationUS6229157US6392913 InventeursGurtej S. Sandhu Cessionnaire d'origineMicron Technology, Inc.Round Rock Research, Llc Classification aux �tats-Unis438/237257/E27.73257/E27.4257/E21.358438/238438/702 Classification internationaleH01L27/24H01L21/329H01L27/102 Classification coop�rativeH01L29/66136H01L45/06H01L45/144H01L27/1021H01L45/1233H01L27/2409 Classification europ�enneH01L 29/66M6D2RH01L 27/24DH01L 27/102DR�f�rencesCitations de brevets (42)Citations hors brevets (24) R�f�renc� par (204)Liens externesUSPTO Cession USPTO EspacenetMethod of forming a polysilicon diode and devices incorporating such diodeUS 6025220 A R�sum� A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material, by methods such as conformal deposition, leaving a generally vertical seam in the middle of the polysilicon material. An insulative material is deposited in the seam. The polysilicon material is appropriately doped and electrical contacts and conductors are added as required. The diode can be coupled to a chalcogenide resistive element to create a chalcogenide memory cell.
What is claimed is: 1. A method forming a diode on a semiconductor substrate assembly, comprising the steps of: providing a container in an insulative layer in said substrate assembly; forming a volume of polysilicon material within said container, said polysilicon material formed to leave a void within said polysilicon material; and forming a p-n junction within said volume of polysilicon material filling an insulating material within said void.
2. The method of claim 1, further comprising the step of placing a contact element above said polysilicon material.
5. A method of forming a diode on a semiconductor substrate, comprising the steps of: depositing a volume of a insulating material on said substrate and forming a container therein; depositing a conformal layer of polysilicon material over said insulating material and said container formed therein, said volume of polysilicon material deposited to leave a generally central void therein; depositing a insulating material within said void; and doping said polysilicon to define a p-n junction within said volume of polysilicon material.
6. The method of claim 5, wherein said volume of insulating material defining said container has an upper surface, and wherein said method further comprises the step of removing the portion of said conformal layer of polysilicon deposited above said upper surface of said insulating layer.
9. A method for forming a polysilicon diode on a semiconductor substrate, comprising the steps of: providing an electrode on a substrate; providing an insulating layer including a container defined therein, said container providing electrical access to said electrode; forming a conformal layer of polysilicon within said container, while defining a void within said container; doping said polysilicon material within said container to form p-n junction; and substantially filling said void with a insulative material.
10. The method of claim 9, wherein said step of doping said polysilicon material is performed at least in part through ion implantation.
11. A method for manufacturing a memory device having a memory cell therein, comprising the steps of: providing a semiconductor substrate; depositing a volume of a insulating material on said substrate and forming a container therein; depositing a conformal volume of polysilicon material within said container, said volume of polysilicon material deposited to leave a generally central void therein; depositing a insulating material within said void; doping said polysilicon to define a p-n junction within said volume of polysilicon material; and depositing a chalcogenide material in electrical communication with said polysilicon material.
12. The method of claim 11, wherein said chalcogenide material is deposited at least partially within said void in said polysilicon material.
13. A method of forming a diode in an integrated circuit, the method comprising the acts of: (a) forming a container having sidewalls in an insulative material formed on a substrate; (b) forming a layer of semiconductive material on the sidewalls of the container to create a peripheral semiconductive member having a substantially central void; and (c) doping the peripheral semiconductive material to create a diode.
14. The method, as set forth in claim 13, wherein act (a) comprises the acts of: disposing an insulative material on a substrate; and forming the container in the insulative material.
15. The method, as set forth in claim 13, wherein act (a) comprises the act of: forming a generally cylindrical container in said insulative material.
16. The method, as set forth in claim 13, wherein act (b) comprises the act of: conformally depositing the layer of semiconductive material within the container to cover the sidewalls and a bottom portion of the container.
17. The method, as set forth in claim 13, wherein act (c) comprises the act of: doping an impurity into the peripheral semiconductive member after it has been formed within the container.
18. The method, as set forth in claim 13, wherein act (c) comprises the act of: forming a peripheral p-n junction within the peripheral semiconductive member.
19. The method, as set forth in claim 13, further comprising the act of: substantially filling the void with a insulative material.
20. The method, as set forth in claim 13, further comprising the act of: forming a memory element in electrical contact with the peripheral semiconductive member.
21. The method, as set forth in claim 20, wherein the act of forming a memory element comprises the acts of: forming a first electrode in electrical contact with the peripheral semiconductive member; forming a layer of chalcogenide material over the first electrode; and forming a second electrode over the layer of chalcogenide material.
22. The method, as set forth in claim 13, wherein the acts are performed in the recited order.
Many chalcogenide alloys may be contemplated for use with the present invention. For example, alloys of tellurium, antimony and germanium may be particularly desirable, and alloys having from approximately 55-85 percent tellurium and on the order of 15-25 percent germanium are currently contemplated for use in chalcogenide memory cell devices. U.S. Pat. No. 5,335,219 is believed to be generally illustrative of the existing state of the art relative to chalcogenide materials, and is believed to provide explanations regarding the current theory of function and operation of chalcogenide elements and their use in memory cells. The specification of U.S. Pat. No. 5,335,219 to Ovshinski et al., issued Aug. 2, 1994, is incorporated herein by reference, for all purposes. An exemplary specific chalcogenide alloy suitable for use in memory cells in accordance with the present invention is one consisting of Te.sub.56 Ge.sub.22 Sb.sub.22.
Container 20 is partially filled with a film of polysilicon material 26. Preferably, the polysilicon is formed as a generally conformal film, which leaves a generally centrally located void or seam 30 within polysilicon material 26 within container 20. The film of polysilicon material 26 may be deposited through an appropriate desired technique, such as, for example, low pressure chemical vapor deposition (LPCVD), through pyrolysis of silane (SiH.sub.4). As is well-known, thin films of polycrystalline silicon typically include relatively small single crystal regions which are separated from one another by grain boundaries. Even if these grain boundaries do not exist in a polysilicon film at the time of deposition (i.e., a generally amorphous film, as deposited), subsequent processing steps common in the manufacture of semiconductor devices will typically raise the temperature of the polysilicon and cause formation of these grain boundaries. Typically, for optimized process conditions, a polysilicon film will include a generally columnar crystal grain structure which extends generally perpendicular to the surface on which deposition takes place; with the grain boundaries also, therefore, extending generally perpendicular to the surface upon which the deposition takes place.
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