Source: http://www.google.com/patents/US8068485?ie=ISO-8859-1&dq=5,966,702
Timestamp: 2014-09-15 02:33:51
Document Index: 264522968

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 200401969', 'Application No. 200401973', 'Application No. 200401969', 'Application No. 200410047784', 'Application No. 200410038432', 'Application No. 200410038546', 'application No. 200410044503', 'Application No. 200410071497', 'Application No. 04255786', 'Application No. 04252205', 'Application No. 04251582', 'Application No. 04252056', 'Application No. 04252202', 'Application No. 04252057', 'Application No. 04252203', 'Application No. 04252054', 'Application No. 10162586', 'Application No. 04255611', 'Application No. 04251581', 'Application No. 04252054', 'Application No. 04252056', 'Application No. 04252057', 'Application No. 04252202', 'Application No. 04252203', 'Application No. 04255609', 'Application No. 04252055', 'Application No. 04255610', 'Application No. 200410044503', 'Application No. 200410044503', 'Application No. 200410043419', 'Application No. 200410045686', 'Application No. 200410087460', 'Application No. 200410038545', 'Application No. 04252205', 'Application No. 200410038545', 'Application No. 200410095171', 'Application No. 200410043419', 'Application No. 200410071498', 'Application No. 2004100950502', 'Application No. 200410095171', 'Application No. 200410044503', 'Application No. 08153454', 'Application No. 08153726', 'Application No. 08155263', 'Application No. 08153724', 'Application No. 08155262']

Patent US8068485 - Multimedia interface - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA packet based display interface having a video processing unit arranged to couple a multimedia source device to a multimedia sink device is disclosed that includes a transmitter unit coupled to the source device arranged to receive a source packet data stream in accordance with a native stream rate,...http://www.google.com/patents/US8068485?utm_source=gb-gplus-sharePatent US8068485 - Multimedia interfaceAdvanced Patent SearchPublication numberUS8068485 B2Publication typeGrantApplication numberUS 11/747,844Publication dateNov 29, 2011Filing dateMay 11, 2007Priority dateMay 1, 2003Also published asCN101303639A, EP1990797A1, US20070286246Publication number11747844, 747844, US 8068485 B2, US 8068485B2, US-B2-8068485, US8068485 B2, US8068485B2InventorsOsamu KobayashiOriginal AssigneeGenesis Microchip Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (110), Non-Patent Citations (135), Referenced by (2), Classifications (20), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMultimedia interfaceUS 8068485 B2Abstract A packet based display interface having a video processing unit arranged to couple a multimedia source device to a multimedia sink device is disclosed that includes a transmitter unit coupled to the source device arranged to receive a source packet data stream in accordance with a native stream rate, a receiver unit coupled to the sink device, and a linking unit coupling the transmitter unit and the receiver unit arranged to transfer a multimedia data packet stream formed of a number of multimedia data packets based upon the source packet data stream in accordance with a link rate between the transmitter unit and the receiver unit.
1. A multimedia interface, comprising:
a receiver unit arranged to receive video data packets at a link character clock rate, eliminating the need for time base recovery on the video data packets, wherein the video data packets correspond to a native video data stream at a native video clock rate and neither a transmitted clock signal nor time stamps are utilized at the receiver unit;
a video enhancement unit coupled to the receiver unit arranged to process the received video data packets; and
a transmitter unit arranged to transmit the processed video packets at the link character clock rate, wherein the link character clock rate is independent of the native video clock rate;
wherein the video enhancement unit is included in a connector of a cable assembly configured to electrically connect a multimedia source and a multimedia sink with the video data packets processed by the video enhancement unit within the connector being passed on to the multimedia sink.
2. An interface as recited in claim 1, wherein the receiver unit comprises:
a regenerator unit arranged to convert the received video data packets to video data suitable for processing by the video enhancement unit.
3. An interface as recited in claim 2, wherein the video data suitable for processing by the video enhancement unit is a native video data.
4. An interface as recited in claim 3, wherein the video enhancement unit comprises:
an input node coupled to the regenerator unit arranged to receive the native video data; and
a video processor arrange to process the received native video according to video processing instructions.
5. An interface as recited in claim 3, wherein the transmitter unit comprises:
a transmitter input node arranged to receive the processed video data;
a generator unit arranged to convert the received processed video data into video data packets corresponding to the processed video data; and
a transmitter output node arranged to provide the video packets corresponding to the processed video data to external circuitry.
6. An interface as recited in claim 5, wherein a receiver input node is connected to a multimedia source device and wherein the transmitter output node is connected to a communication link.
7. An interface as recited in claim 6, wherein the receiver input node is connected to a communication link and wherein a transmitter output node is connected to a multimedia sink device.
8. An interface as recited in claim 7, wherein the communication link comprises:
a uni-directional main link having multiple lanes coupling the multimedia source to the multimedia sink arranged to carry the processed packetized video data packets from the transmitter output node to the multimedia sink at the link character clock rate;
a half duplex, bi-directional auxiliary channel connecting the multimedia source and the display that provides in concert with the uni-directional main link, a secondary communication link between the multimedia source and the display for transferring information between the multimedia source and the multimedia sink.
9. An interface as recited in claim 1, wherein the processing includes contrast enhancement.
10. An interface as recited in claim 1, further comprising:
a hot plug event detector unit arranged to automatically determine when an active sink device is connected to the receiver unit.
11. A cable assembly, comprising:
a uni-directional main link coupling a multimedia source to a multimedia sink arranged to carry a packetized multimedia data stream from the multimedia source to a multimedia display at a link character clock rate that is independent of a native multimedia clock rate, eliminating the need for time based recovery of the packetized multimedia data stream and neither a transmitted clock signal nor time stamps are utilized at the multimedia display;
a half duplex, bi-directional auxiliary channel connecting the multimedia source and the display that provides in concert with the uni-directional main link, a secondary communication link between the multimedia source and the display for transferring information between the multimedia source and the display, and
a connector arrangement arranged to electrically connect the uni-directional main link and the half duplex, bi-directional auxiliary channel to the multimedia source and the display comprising:
a video processing unit included in a connector of the connector arrangement, the video processing unit arranged to process video data received from the multimedia source and pass the processed video data to the display by way of the main link.
12. A cable assembly as recited in claim 11, wherein the multimedia data stream has an associated adjustable data stream link rate that is independent of the native stream rate.
13. A cable assembly as recited in claim 11, wherein the multimedia data stream is an isochronous and wherein the information transfer is an asynchronous.
14. A cable assembly as recited in claim 11, further comprising:
a hot plug event detector unit arranged to automatically determine when an active sink device is connected to the cable assembly.
15. A cable assembly as recited in claim 11, wherein the information carried by the auxiliary channel includes sync loss information, dropped packets information and the results of training session information.
16. A cable assembly as recited in claim 11, wherein the link rate is adjustable up to about 2.7 Gbps and an associated bandwidth of 270 Mbytes/sec.
17. A cable assembly as recited in claim 15, wherein the multimedia source informs the display device by way of the auxiliary channel of an audio sample rate and a number of bits per sample corresponding to an audio stream.
18. A cable assembly as recited in claim 11, wherein the auxiliary channel supports data transmission rates up to at least 480 Mbs between the multimedia source and the multimedia display using a self-clocked data signal.
19. A cable assembly as recited in claim 18, wherein when the interface is placed in a multi-master mode, either the multimedia source or the display can be a master device, and wherein serial data in response is passed from a responding slave device in response to a requesting master device over the auxiliary channel.
20. A cable assembly as recited in claim 19, further comprising:
an arbitration unit arranged to monitor auxiliary channel requests and provide for a priority of any conflicting requests.
a multimedia interface arranged to couple a multimedia source via a communication link to a multimedia display by carrying video packets at a link character lock rate, eliminating the need for time base recovery of the video packets and neither a transmitted clock signal nor time stamps are utilized at the multimedia display, comprising:
a cable assembly associated with the communication link of the multimedia interface, the electrical connector arrangement having a source side connector and a display side connector;
a video processor unit included in at least one of the source side connector and the display side connector to process video data received from the multimedia source and pass the processed video data to the multimedia display.
CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation in part of U.S. patent application Ser. No. 10/726,794 filed Dec. 2, 2003 entitled �PACKET BASED VIDEO DISPLAY INTERFACE AND METHODS OF USE THEREOF� by Kobayashi that, in turn, takes priority under 35 U.S.C. 119(e) to (i) U.S. Provisional Patent Application No. 60/467,804, filed on May 1, 2003 entitled �DIGITAL/ANALOG VIDEO INTERCONNECT AND METHODS OF USE THEREOF� by Kobayashi, (ii) U.S. Provisional Patent Application No. 60/504,060, filed on Sep. 18, 2003 entitled �DIGITAL/ANALOG VIDEO INTERCONNECT AND METHODS OF USE THEREOF� by Kobayashi, (iii) U.S. Provisional Patent Application No. 60/474,085 filed on May 28, 2003 entitled �DIGITAL/ANALOG VIDEO INTERCONNECT AND METHODS OF USE THEREOF� by Kobayashi, and (iv) U.S. Provisional Patent Application No. 60/474,084 filed on May 28, 2003 entitled �SIMPLE ENUMERATION METHOD FOR THE LINK CLOCK RATE AND THE PIXEL/AUDIO CLOCK RATE� by Kobayashi, each of which is hereby incorporated by reference herein in their entirety. This application is also related to the following co-pending U.S. patent applications each of which are herein incorporated by reference, (i) U.S. patent application Ser. No. 10/726,802 filed on Dec. 2, 2003 entitled �METHOD OF ADAPTIVELY CONNECTING A VIDEO SOURCE AND A VIDEO DISPLAY� by Kobayashi; (ii) U.S. patent application Ser. No. 10/726,438 filed Dec. 2, 2003 that has issued as U.S. Pat. No. 7,068,686 and continuing U.S. patent application Ser. No. 11/291,015 that has issued as U.S. Pat. No. 7,177,329, both entitled �METHOD AND APPARATUS FOR EFFICIENT TRANSMISSION OF MULTIMEDIA DATA PACKETS� by Kobayashi; (iii) U.S. patent application Ser. No. 10/726,440 filed Dec. 2, 2003 entitled �METHOD OF OPTIMIZING MULTIMEDIA PACKET TRANSMISSION RATE� by Kobayashi; (iv) U.S. patent application Ser. No. 10/727,131 filed Dec. 2, 2003 that has issued as U.S. Pat. No. 7,088,741 entitled �USING AN AUXILIARY CHANNEL FOR VIDEO MONITOR TRAINING� by Kobayashi; (v) U.S. patent application Ser. No. 10/726,350 filed Dec. 2, 2003 entitled �TECHNIQUES FOR REDUCING MULTIMEDIA DATA PACKET OVERHEAD� by Kobayashi; (vi) U.S. patent application Ser. No. 10/726,362 filed Dec. 2, 2003 entitled �PACKET BASED CLOSED LOOP VIDEO DISPLAY INTERFACE WITH PERIODIC STATUS CHECKS� by Kobayashi; (vii) U.S. patent application Ser. No. 10/726,895 filed Dec. 2, 2003 entitled �MINIMIZING BUFFER REQUIREMENTS IN A DIGITAL VIDEO SYSTEM� by Kobayashi; (viii) U.S. patent application Ser. No. 10/726,441 filed Dec. 2, 2003 entitled �VIDEO INTERFACE ARRANGED TO PROVIDE PIXEL DATA INDEPENDENT OF A LINK CHARACTER CLOCK� by Kobayashi; and (ix) U.S. patent application Ser. No. 10/726,934 filed Dec. 2, 2003 that has issued as U.S. Pat. No. 6,992,987 entitled �ENUMERATION METHOD FOR THE LINK CLOCK RATE AND THE PIXEL/AUDIO CLOCK RATE� by Kobayashi. This application is also related to the following co-pending applications: (x) U.S. patent application Ser. No. 10/909,103 filed Jul. 29, 2004 entitled �USING PACKET TRANSFER FOR DRIVING LCD PANEL DRIVER ELECTRONICS� by Kobayashi; (xi) U.S. patent application Ser. No. 10/909,027 filed Jul. 29, 2004 entitled �BYPASSING PIXEL CLOCK GENERATION AND CRTC CIRCUITS IN A GRAPHICS CONTROLLER CHIP� by Kobayashi, (xi) U.S. patent application Ser. No. 10/909,085 filed Jul. 29, 2004 entitled �PACKET BASED STREAM TRANSPORT SCHEDULER AND METHODS OF USE THEREOF� by Kobayashi, and (xii) U.S. patent application Ser. No. 10/762,680 filed Jan. 21, 2004 entitled �PACKET BASED HIGH DEFINITION HIGH-BANDWIDTH DIGITAL CONTENT PROTECTION� by Kobayashi.
Therefore, it would be desirable to have a digital interface that is more cost effective than current interfaces (such as DVI) for coupling video sources and video displays. In some cases, the digital interface would also be backward compatible with analog video, such as VGA.
SUMMARY OF THE INVENTION A multimedia interface is described. The interface includes at least a receiver unit arranged to receive video data packets at a link rate, wherein the video data packets correspond to a native video data stream at a native video clock rate; a video enhancement unit coupled to the receiver unit arranged to process the received video data packets; and a transmitter unit arranged to transmit the processed video packets at the link rate, wherein the link rate is independent of the native video clock rate.
In another embodiment, a system is disclosed that includes at least the following: a multimedia source arranged to provide a reduced set of multimedia formats each at a native multimedia clock rate; a multimedia display; and
a multimedia interface arranged to couple the portable multimedia source and the display. In the described embodiment, the interface includes a uni-directional main link coupling the multimedia source to the multimedia sink arranged to carry a packetized multimedia data stream from the multimedia source to the multimedia display at a link rate that is independent of the native multimedia clock rate, a half duplex, bi-directional auxiliary channel connecting the multimedia source and the display that provides in concert with the uni-directional main link, a secondary communication link between the multimedia source and the display for transferring information between the multimedia source and the display, and a connector arrangement arranged to electrically connect the uni-directional main link and the half duplex, bi-directional auxiliary channel to the multimedia source and the display. The connector includes, at least, a video processing unit arranged to process video data received from the multimedia source and pass the processed video data to the display by way of the main link.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a generalized representation of a cross platform display interface in accordance with an embodiment of the invention.
FIG. 30 illustrates a system based upon the system shown in FIG. 1 that is used to connect multimedia source to multimedia sink (display) that includes a video processing unit.
FIG. 31 shows a representative video processing unit in accordance with an embodiment of the invention.
DETAILED DESCRIPTION OF SELECTED EMBODIMENTS Reference will now be made in detail to a particular embodiment of the invention, an example of which is illustrated in the accompanying drawings. While the invention will be described in conjunction with the particular embodiment, it will be understood that it is not intended to limit the invention to the described embodiment. To the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.
The described interface is a point-to-point, packet-based, plug & play, serial digital display interface that is both open and scalable that is suitable for use with, but not limited to, desktop monitors as well as providing LCD connectivity within notebook/all-in-one PC's, and consumer electronics display devices including HDTV displays and the like. Unlike conventional display interfaces that transmit a single video raster plus timing signals such as Vsync, Hsync, DE, etc., the inventive interface provides a system of multi-stream packet transfer capable of transferring one or more packet streams simultaneously in the form of �virtual pipes� established within a physical link.
In the case where the source 102 provides an analog image signal, an analog-to-digital converter (A/D) converts an analog voltage or current signal into a discrete series of digitally encoded numbers (signal) forming in the process an appropriate digital image data word suitable for digital processing. Any of a wide variety of A/D converters can be used. By way of example, other A/D converters include, for example those manufactured by: Philips, Texas Instrument, Analog Devices, Brooktree and others.
For example, if the data stream 110 is an analog type signal, the an analog to digital converter (not shown) included in or coupled to the transmitter 102 will digitize the analog data which is then packetized by a packetizer that converts the digitized data stream 110 into a number of data packets 114 each of which will be transmitted to the receiver 104 by way of the virtual link 116. The receiver 104 will then reconstitute the data stream 110 by appropriately recombining the data packets 114 into their original format. It should be noted that the link rate is independent of the native stream rates. The only requirement is that the link bandwidth of the physical link 106 be higher than the aggregate bandwidth of data stream(s) to be transmitted. In the described embodiment, the incoming data (such as pixel data in the case of video data) is packed over the respective virtual link based upon a data mapping definition. In this way, the physical link 106 (or any of the constituent virtual links) does not, as does conventional interconnects such as DVI, carry one pixel data per link character clock.
In the described embodiment, the source device physical layer 1202 includes an electrical sub layer 1202-1 and a logical sub layer 1202-2. The electrical sub layer 1202-1 includes all circuitry for interface initialization/operation such as hot plug/unplug detection circuit, drivers/receivers/termination resistors, parallel-to-serial/serial-to-parallel conversions, and spread-spectrum-capable PLL's. The logical sub layer 1202-2 includes circuitry for, packetizing/de-packetizing, data scrambling/de-scrambling, pattern generation for link training, time-base recovery circuits, and data encoding/decoding such as 8B/10B (as specified in ANSI X3.230-1994, clause 11) that provides 256 link data characters and twelve control characters (an example of which is shown as FIG. 13) for the main link 222 and Manchester II for the auxiliary channel 224 (see FIG. 14).
The major functions of auxiliary channel logical sub layer include data encoding and decoding, framing/de-framing of data and there are two options in auxiliary channel protocol: standalone protocol (limited to link setup/management functions in a point-to-point topology) is a lightweight protocol that can be managed by the Link Layer state-machine or firmware and extended protocol that supports other data types such as USB traffic and topologies such as daisy-chained sink devices. It should be noted that the data encoding and decoding scheme is identical regardless of the protocol whereas framing of data differs between the two. Still referring to FIG. 15, the auxiliary channel electrical sub layer contains the transmitter 1502 and the receiver 1504. The transmitter 1502 is provided with link characters by the logical sub layer, which it serializes and transmits out. The receiver 1504 receives serialized link character from the link layer and subsequently de-serializes it at link character clock rate. The positive and negative signals of auxiliary channel 224 are terminated to ground via 50-ohm termination resistors at each end of the link as shown. In the described implementation, the drive current is programmable depending on the link condition and ranges from approximately 8 mA to approximately 24 mA resulting in a range of Vdifferential_pp of approximately 400 mV to approximately 1.2V. In electrical idle modes, neither the positive nor the negative signal is driven. When starting transmission from the electrical idle state, the SYNC pattern must be transmitted and the link reestablished. In the described embodiment, the SYNC pattern consists of toggling a auxiliary channel differential pair signals at clock rate 28 times followed by four 1's in Manchester II code. The auxiliary channel master in the source device detects hot-plug and hot-unplug events by periodically driving or measuring the positive and negative signals of auxiliary channel 224.
In the described embodiment, the main link 222 supports discrete, variable link rates that are integer multiples of the local crystal frequency (see FIG. 3 for a representative set of link rates consonant with a local crystal frequency of 24-MHz). As shown in FIG. 16, the main link 222 (being a unidirectional channel) has only a transmitter 1602 at the source device and only a receiver 1604 at the display device.
The invention will now be described in terms of state diagrams shown in FIGS. 18 and 19 described below. Accordingly, FIG. 18 shows the source state diagram described below. At an off state 1802, the system is off such that the source is disabled. If the source is enabled, then the system transitions to a standby state 1804 suitable for power saving and receiver detection. In order to detect whether or not the receiver is present (i.e., hot plug/play), the auxiliary channel is periodically pulsed (such as for 1 us every 10 ms) and a measure of a voltage drop across the termination resistors during the driving is measured. If it is determined that a receiver is present based upon the measured voltage drop, then the system transitions to a detected receiver state 1806 indicating that a receiver has been detected, i.e, a hot plug event has been detected. If, however, there is no receiver detected, then the receiver detection is continued until such time, if ever, a receiver is detected or a timeout has elapsed. It should be noted that in some cases the source device may choose to go to �OFF� state from which no further display detection is attempted.
In situations where it is not practical to mount the connector on the motherboard, the signals can be routed through the SDVO slot of the PCI Express motherboard and brought to the back of the PC using a passive card connector as shown in FIG. 21. As is the case with the current generation of add-in graphics cards, an add-in graphics card can supplant the onboard graphics engine as shown in FIG. 23.
FIG. 27 shows a flowchart for a link set up process 2700 in accordance with an embodiment of the invention. The process 2700 begins at 2702 by the receiving of a hot plug detection event notification. At 2704 a main link inquiry is made by way of an associated auxiliary channel to determine a maximum data rate, a number of time base recovery units included in a receiver, and available buffer size. Next, at 2706, the maximum link data rate is verified by way of a training session and at 2708, a data stream source is notified of the hot plug event. At 2710, the capabilities of the display (using EDID, for example) are determined by way of the auxiliary channel and the display responds to the inquiries at 2712 which, in turn, results a collaboration of the main link training session at 2714.
FIG. 30 illustrates system 3000 based upon the system 100 shown in FIG. 1 that is used to connect multimedia source 3002 to multimedia sink (display) 3004 by way of communication link 3006 by way of connectors (source side connector 3008 and/or display side connector 3010). In the described embodiment, one (or both) connectors 3008 or 3010 can include video processor unit 3012 arranged to process video data received from multimedia source 3002 prior to being passed by way of communication link 3006 to multimedia sink 3004. It should be noted, however, that video processing unit 3012 can also be incorporated into source side connector 3008 in addition to or in place of source side connector 3010.
Although the following discussion describes a source side video enhancement unit, it should be noted that the discussion that follows also applies to a display side video processing unit as well. In the described embodiment, video processing unit 3012 processes video data received from multimedia source 3002 prior to being passed by way of communication link 3006 to display 3004. Multimedia source 3002 can take the form of a video device (DVD player, video multi-media player, and so on) that can support video formats such as 480(i,p), 720p, 1080(i,p) and so on. Communication link 3006 can also include half duplex, bi-directional auxiliary channel 3014 capable of supporting data transmission rates up to at least 480 Mbs using a self-clocked data signal (based upon Manchester II channel coding, for example) providing an optional USB compatible data link. Therefore, in those cases where display 3004 is USB compatible (i.e., includes an optional USB port 3016), auxiliary channel 3014 can provide a USB compatible conduit between multimedia source 3002 and display 3004. In this way, any of a number of USB related transactions (such as file transfers) between multimedia source 3002 and display 3004 can be accommodated. In addition, hot plug detect (HPD) channel 3018 provides a conduit to carry HPD signal 3020 that can be used for hot swapping.
In the described embodiment, the auxiliary channel master in the form of multimedia source 3002 detects hot-plug and hot-unplug events by periodically driving (or measuring) positive and negative signals of auxiliary channel 3014. Power pins 3022 and 3024 provide an interface from multimedia source and display internal power supplies 3026 and 3028 respectively that can be used to power a dongle (repeater, interface converter, etc.). In the described embodiment, internal power supplies 3026 and 3028 can provide power on the order of 1.0 W or larger at approximately 5-12 V at about 500 mA maximum current.
During operation, packetizer 3030 included in transmitter 3032 packetizes native multimedia data 3034 (that can be either analog or digital) generated by and received from, for example, video unit 3036 to form packetized video data stream 3038. In this situation, multimedia source 3002 acts as a master device and display 3004 as the slave device in that it is multimedia source 3002 that initiates any transaction for which display 3004 provides an appropriate response. Video data stream 3038 is then passed by way of transmitter 3032 to video processing unit 3012 for further processing. For example, FIG. 31 shows a representative implementation of video processing unit 3100 in accordance with an embodiment of the invention. The video processing unit 3100 includes a receiver portion 3102 having an input node 3104 suitable for receiving video data packets from packetized video data stream 3038. The received video data packets are, in turn, forwarded to de-packetizer unit 3106 that regenerates the native video data corresponding to native video multimedia data 3034 as input to processor 3108. Processor 3108, in turn, processes the native video data according to pre-selected set of instructions provided by, for example, external memory devices. Processor 3108, in turn, outputs processed video data to transmitter unit 3110 where packetizer 3112 packetizes the processed video data into processed packetized video data stream 3114 that is output to transmitter output node 3116.
Referring back to FIG. 30, once processed video stream 3114 is received at receiver 3038 connected to display side connector 3012, de-packetizer 3040 converts the data packets to video stream 3042 corresponding to a processed version of native video stream 3034 using any number of well known techniques as input to display controller 3044. For example, receiver 3038 can include a time-base recovery (TBR) unit (not shown) that regenerates the native rate of video stream 3034 using time stamps embedded in data packets of video stream 3008. It should be noted, however, that for appropriately configured digital display devices (shown, for example, in FIG. 2C), time base recovery is unnecessary since display data is be sent to the display driver electronics included in display controller 3044 at the link character clock rate, thereby greatly reducing the number of channels required with a commensurate reduction in complexity and cost for the display.
In the case whereby display 3004 is USB (or other similar technology) enabled, system 3000 can be considered operable in what is referred to as a multi-master mode in which either multimedia source 3002 or display 3004 can take on the role of master/slave. For example, in the situation illustrated in FIG. 31, USB enabled multimedia source 3002 (such as a portable digital camera, multimedia player, or a PC having digital photo library management software, for example) includes memory 3046 coupled to multimedia source processor 3048 arranged to receive and respond to data (or file) request 3050 generated by USB enabled display 3004. Upon receipt of data request 3050, processor 3048 responds by generating and forwarding a memory read command 3054 to memory 3046 that responds by forwarding requested data 3056 back to processor 3048 that, in turn, forwards requested data 3056 back to display 3004 by way of bi-directional auxiliary channel 3014. Since bi-directional auxiliary channel 3014 is half duplex in nature, in order to prevent collisions on bi-directional auxiliary channel 3014, arbitration control unit 3058 monitors bus commands generated by display processor 3060 and multimedia source processor 3048. If any collision or potential collision is detected, then arbitration control unit 3058 can give priority to either multimedia source 3002 or display 3004. In the described embodiment, however, multimedia source 3002 is generally given priority over display 3004 by holding any display 3004 requests (using, for example, time stretching techniques available in I2C bus architectures) until such time as bi-directional auxiliary bus 3014 is available.
Once requested data 3056 (in the form of serial bus (USB) data, for example) has been received by receiver 3038, requested data 3056 is forwarded to display processor 3060 where it can be further processed (such as image enhancement, superposition of graphical or textual data, etc.) or not and then forwarded to and stored in memory 3062 for subsequent display on displayer 3064, for example.
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