Source: http://www.google.com/patents/US5530959?ie=ISO-8859-1
Timestamp: 2014-07-10 14:25:29
Document Index: 192628277

Matched Legal Cases: ['Application No. 95303159', 'Application No. 95303159', 'Application No. 95303159', 'Application No. 95303159', 'Application No. 95303159', 'Application No. 95303159', 'Application No. 95303159', 'Application No. 95303159']

Patent US5530959 - Self-synchronizing scrambler/descrambler without error multiplication - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA self-synchronizing scrambler/descrambler arrangement operates in two modes. In the first, or start-up mode, predetermined data is coupled to the scrambler and transmitted to the descrambler. This data is used to "seed", i.e., load, storage devices in the scrambler and descrambler with the same information....http://www.google.com/patents/US5530959?utm_source=gb-gplus-sharePatent US5530959 - Self-synchronizing scrambler/descrambler without error multiplicationAdvanced Patent SearchPublication numberUS5530959 APublication typeGrantApplication numberUS 08/245,755Publication dateJun 25, 1996Filing dateMay 18, 1994Priority dateMay 18, 1994Fee statusLapsedAlso published asEP0683584A1Publication number08245755, 245755, US 5530959 A, US 5530959A, US-A-5530959, US5530959 A, US5530959AInventorsDaniel AmranyOriginal AssigneeAt&T Corp.Export CitationBiBTeX, EndNote, RefManPatent Citations (9), Non-Patent Citations (11), Referenced by (22), Classifications (8), Legal Events (15) External Links: USPTO, USPTO Assignment, EspacenetSelf-synchronizing scrambler/descrambler without error multiplicationUS 5530959 AAbstract A self-synchronizing scrambler/descrambler arrangement operates in two modes. In the first, or start-up mode, predetermined data is coupled to the scrambler and transmitted to the descrambler. This data is used to "seed", i.e., load, storage devices in the scrambler and descrambler with the same information. After a predetermined time interval, the start-up mode is terminated, and the scrambler and descrambler each operate in a steady-state mode. In this mode, the information loaded in the scrambler and descrambler devices are used to form the scrambler and descrambler key signals. Advantageously, in the steady-state mode, the occurrence of transmission errors does not effect the contents of the storage devices in the scrambler and descrambler. Hence, the prior art problem of error multiplication is avoided. In applications where a number of coded and multiplexed data channels are communicated over the communications channel linking the scrambler and descrambler, this approach allows the use of a single scrambler/descrambler without degrading the coding benefits.
What is claimed: 1. Apparatus comprisingmeans for receiving a scrambled digital signal; and means for descrambling said received digital signal, said descrambling means being operative in first and second time intervals, said descrambling means descrambling said received scrambled signal in said first and second time intervals using a key signal, said descrambling means including means for forming said key signal, said key signal forming means forming said key signal in said first time interval in response to said received scrambled signal in this interval, said key signal forming means being unresponsive to said received scrambled signal in said second time interval; wherein said descrambling means includes a means for controlling that examines an output of said descrambling means and controls the duration of said first time interval in response to this examination. 2. The apparatus of claim 1 wherein said key signal forming means during said second time interval is responsive to said key signal formed during said first time interval.
TECHNICAL FIELD The present invention relates to a scrambling and descrambling technique which is self-synchonizing and avoids error multiplication problems.
BACKGROUND OF THE INVENTION Scrambling of digital signals is routinely used in certain communications applications. In others, such as data communications systems, scrambling is typically done to assure transitions in the received data signal and thereby avoid loss of synchronization in the data recovery process. It is also used to assure "whiteness" of data for adaptive processors. Transmission delays across the communications channel are never constant, and, as such, there is always a need to synchronize the scrambler and descrambler with the inherently unknown system delay. One commonly-used prior art self-synchronizing arrangement scrambles/descrambles using a "key" signal. Within the transmitter, the data signal is scrambled using the key signal while, within the receiver, the received scrambled data signal is descrambled using the same key signal. The key signal is typically derived from the scrambled data signal is the scrambler and descrambler. The problem with this arrangement is that a single difference between the transmitted and received scrambled data signal results in a multiplication of errors in the descrambled data signal. In an effort to avoid the above described error multiplication problem, a technique known as "closed-loop" scrambling/descrambling has been done. In this mode of scrambling, the keys stored in the scrambler and descrambler are prestored and are updated only using the contents stored in each register. As a result, the updating is independent of errors in the received signal and the problem of error multiplication is avoided. There are two major shortcomings with closed loop scrambling/descrambling. First, synchronization of the scrambler and descrambler operations must be provided by communicating signals between these devices in addition to the scrambled data. In certain applications, such as high-speed voice and video applications, this is difficult and expensive to implement. Second, seeding the scrambler and descrambler with the same information for forming the initial key signals is oftentimes impractical for certain system applications. It would, therefore, be extremely desirable if an inexpensive, easy to implement, self-synchronizing, scrambling/descrambling arrangement could be provided which overcomes the problem of error multiplication.
SUMMARY OF THE INVENTION Pursuant to the present invention, a self-synchronizing scrambler/descrambler arrangement is proposed wherein the scrambler is "seeded" or provided with predetermined data during a start-up time interval. In this interval, the predetermined data or seed is stored in the scrambler and descrambler. After this start-up interval, the scrambler and descrambler each operate in a "closed-loop" mode wherein the presence of errors in the received scrambled data does not produce error multiplication. Advantageously, this arrangement can be used in applications where as a single data channel is communicated between the scrambler and descrambler as well as applications where a number of multiplexed data channels are communicated.
BRIEF DESCRIPTION OF THE DRAWING FIGS. 1-3 are each a block schematic diagram of different prior art scrambling/descrambling arrangements;
DETAILED DESCRIPTION The prior art problem of error multiplication with scrambler/descrambler arrangements using keys is shown in FIG. 1. Illustrative prior art self-synchronizing scrambling/descrambling arrangement 100 includes scrambler 150 and descrambler 160. Within the scrambler, shift register 101 stores information and exclusive-OR gate 102 modulo-2 adds the contents of two predetermined shift register locations to form the key signal. For purposes of illustration, it shall be assumed in this discussion that two locations are used and these are designated as Qiand Qn. Of course, as is well-known in the art, more than two locations may be used. Exclusive-OR gate 103 scrambles the data using the key signal. The scrambled data is transmitted and also coupled to shift register 101. Within the receiver, the scrambled data is coupled to shift register 104 and exclusive-OR gate 105. The descrambling is provided by modulo-2 adding or "half-adding" scrambled data with the key signal formedby exclusive-OR gate 106. Gate 106 forms this key signal, which is identical to that used in the scrambler, by half-adding the contents of shift register locations Qi and Qn. The problem of error multiplication arises because a single error in the state of the descrambler input signal, relative to its transmitted counterpart, is coupled to shift register 104 in the descrambler where it will subsequently appear at least two times in the formation of the descramblerkey signal. The signal coupled to scrambler 150 may be an uncoded digital signal or may be a coded digital signal. The addition of coder 170 and decoder 180 reflects the latter case. The coding scheme employed includes block, e.g., Reed-Solomon, and trellis, e.g. convolutional, coding. In anyevent, the problem of error multiplication is especially troublesome since decoder performance is significantly deteriorated.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3920894 *Mar 11, 1974Nov 18, 1975Bell Telephone Labor IncPseudo-random parallel word generatorUS4304962 *Aug 25, 1965Dec 8, 1981Bell Telephone Laboratories, IncorporatedData scramblerUS4663500 *Jun 23, 1986May 5, 1987Nec CorporationCryptographic systemUS4817148 *Jul 6, 1987Mar 28, 1989Wegener Communications, Inc.Signal scrambling transmission systemUS4856063 *Jan 27, 1988Aug 8, 1989Technical Communication CorporationNo-overhead synchronization for cryptographic systemsUS5235645 *Jun 12, 1992Aug 10, 1993Northwest Starscan Limited PartnershipScrambler/descrambler system for data transmissionUS5241602 *May 22, 1992Aug 31, 1993Byeong Gi LeeParallel scrambling systemUS5321754 *Sep 19, 1991Jun 14, 1994Northern Telecom LimitedSequence synchronizationJPS56122542A * Title not available* Cited by examinerNon-Patent CitationsReference1 *AT&T Technical Journal, Sep. Oct. 1986, USA, vol. 65, No. 5, ISSN 8756 2324, pp. 123 136, Doowhan Choi: Parallel scrambling techniques for digital multiplexers Comment: Listed as particularly relevant if combined with another document of the same category, on European Search Report for European Application No. 95303159.8.2AT&T Technical Journal, Sep.-Oct. 1986, USA, vol. 65, No. 5, ISSN 8756-2324, pp. 123-136, Doowhan Choi: "Parallel scrambling techniques for digital multiplexers" Comment: Listed as particularly relevant if combined with another document of the same category, on European Search Report for European Application No. 95303159.8.3 *European Search Report dated Aug. 31, 1995, regarding EPO Application No. EP 95303159.8.4 *Hewlett Packard Journal, Mar. 1976, USA. vol. 27, No. 7, ISSN 0018 1153, pp. 18 24, A 50 Mbit/s pattern generator and error detector for evaluating digital communications system performance by I. R. Young et al. Comment: Listed as particularly relevant if combined with another document of the same category, on European Search Report for European Application No. 95303159.8.5Hewlett-Packard Journal, Mar. 1976, USA. vol. 27, No. 7, ISSN 0018-1153, pp. 18-24, "A 50-Mbit/s pattern generator and error detector for evaluating digital communications system performance" by I. R. Young et al. Comment: Listed as particularly relevant if combined with another document of the same category, on European Search Report for European Application No. 95303159.8.6 *Nachrichtentechnische Zeitschrift, Dec. 1974, West Germany, vol. 27, No. 12, ISSN 0027 707X, Muller, H.; Bit sequence independence through scramblers in digital communication systems , p. 476, left column, line 37 line 56, figures 2,6. Comment: Listed as particularly relevant if combined with another document of the same category, on European Search Report for European Application No. 95303159.8.7Nachrichtentechnische Zeitschrift, Dec. 1974, West Germany, vol. 27, No. 12, ISSN 0027-707X, Muller, H.; "Bit sequence independence through scramblers in digital communication systems", p. 476, left column, line 37-line 56, figures 2,6. Comment: Listed as particularly relevant if combined with another document of the same category, on European Search Report for European Application No. 95303159.8.8 *Patent Abstracts of Japan, vol. 005 No. 198 (E 087), 16 Dec. 1981 & JP A 56 122542 (Fujitsu Ltd; Others: 01, 26 Sep. 1981 *Abstract* Comment: Astract listed as technological background on European Search Report for European Application No. 95303159.8.9Patent Abstracts of Japan, vol. 005 No. 198 (E-087), 16 Dec. 1981 & JP-A-56 122542 (Fujitsu Ltd; Others: 01, 26 Sep. 1981 *Abstract* Comment: Astract listed as technological background on European Search Report for European Application No. 95303159.8.10W. Wesley Peterson and E. J. Weldon, Jr., "Error-Correcting Codes", Second Edition, Jul. 1981, The MIT Press, pp. 206-211, 472-492.11 *W. Wesley Peterson and E. J. Weldon, Jr., Error Correcting Codes , Second Edition, Jul. 1981, The MIT Press, pp. 206 211, 472 492.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5748734 *Apr 2, 1996May 5, 1998Lucent Technologies Inc.Circuit and method for generating cryptographic keysUS6215876Dec 31, 1997Apr 10, 2001Transcrypt International, Inc.Apparatus for and method of detecting initialization vector errors and maintaining cryptographic synchronization without substantial increase in overheadUS6249582Dec 31, 1997Jun 19, 2001Transcrypt International, Inc.Apparatus for and method of overhead reduction in a block cipherUS6373951 *Feb 26, 1997Apr 16, 2002Telex Communications, Inc.Synchronization technique and method and apparatus for transmitting and receiving coded signalsUS6496582 *Jan 16, 1997Dec 17, 2002Canon Kabushiki KaishaInformation processing apparatus and method thereforUS6792566 *Mar 23, 2001Sep 14, 2004Via Technologies, Inc.Method and apparatus of pre-loading a seed for a test code of a physical layer deviceUS6820230Mar 5, 2002Nov 16, 2004The United States Of America As Represented By The Secretary Of The NavySelf synchronous scrambler apparatus and method for use in dense wavelength division multiplexingUS6862701 *Mar 6, 2001Mar 1, 2005Agilent Technologies, Inc.Data communication system with self-test facilityUS6933862 *Oct 14, 2003Aug 23, 2005Agilent Technologies, Inc.Power consumption stabilization system and methodUS7099352 *Jan 3, 2001Aug 29, 2006Juniper Networks, Inc.System, apparatus, and method for increasing resiliency in communicationsUS7142136 *May 5, 2004Nov 28, 2006Samsung Electronics Co., Ltd.Data modulating method and apparatus, data demodulating method and apparatus, and code arranging methodUS7155016Oct 27, 1999Dec 26, 2006Paradyne CorporationCommunication device and method for using non-self-synchronizing scrambling in a communication systemUS7227949Jan 30, 2003Jun 5, 2007Texas Instruments IncorporatedSeparate self-synchronizing packet-based scrambler having replay variationUS7415112 *Jul 29, 2003Aug 19, 2008Zarbana Digital Fund LlcParallel scrambler/descramblerUS7450034Nov 21, 2007Nov 11, 2008Samsung Electronics Co., Ltd.Data modulating method and apparatus, data demodulating method and apparatus, and code arranging methodUS7450035Nov 21, 2007Nov 11, 2008Samsung Electronics Co., Ltd.Data modulating method and apparatus, data demodulating method and apparatus, and code arranging methodUS7570667Jul 13, 2006Aug 4, 2009Juniper Networks, Inc.System, apparatus, and method for increasing resiliency in communicationsUS7760881 *Oct 21, 2003Jul 20, 2010Sony CorporationData processing apparatus and data reception processing apparatusUS7876241Nov 21, 2007Jan 25, 2011Samsung Electronics Co., Ltd.Data modulating method and apparatus, data demodulating method and apparatus, and code arranging methodUS7913151 *May 24, 2007Mar 22, 2011Pmc-Sierra, Inc.Forward error correction with self-synchronous scramblersUS7986717Jun 26, 2009Jul 26, 2011Juniper Networks, Inc.System, apparatus, and method for increasing resiliency in communicationsUS8020077Feb 2, 2011Sep 13, 2011Pmc-Sierra, Inc.Forward error correction with self-synchronous scramblers* Cited by examinerClassifications U.S. Classification380/268International ClassificationH04L9/20, H03M13/27, H04L25/03, H04L9/12, H04L7/00Cooperative ClassificationH04L25/03866European ClassificationH04L25/03E3Legal EventsDateCodeEventDescriptionJun 4, 2010ASAssignmentEffective date: 20100524Owner name: CONEXANT SYSTEMS, INC. (SUCCESSOR TO GLOBESPAN SEMFree format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A. (SUCCESSOR TO BANKAMERICA BUSINESS CREDIT, INC.);REEL/FRAME:24523/455Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A. (SUCCESSOR TO BANKAMERICA BUSINESS CREDIT, INC.);REEL/FRAME:024523/0455Aug 12, 2008FPExpired due to failure to pay maintenance feeEffective date: 20080625Jun 25, 2008LAPSLapse for failure to pay maintenance feesDec 31, 2007REMIMaintenance fee reminder mailedFeb 1, 2007ASAssignmentOwner name: BROOKTREE BROADBAND HOLDING, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBESPANVIRATA, INC.;REEL/FRAME:018826/0939Effective date: 20040228Owner name: BROOKTREE BROADBAND HOLDING, INC.,CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBESPANVIRATA, INC.;REEL/FRAME:18826/939Nov 21, 2006ASAssignmentOwner name: BANK OF NEW YORK TRUST COMPANY, N.A., THE, ILLINOIFree format text: SECURITY AGREEMENT;ASSIGNOR:BROOKTREE BROADBAND HOLDING, INC.;REEL/FRAME:018573/0337Effective date: 20061113Owner name: BANK OF NEW YORK TRUST COMPANY, N.A., THE,ILLINOISFree format text: SECURITY AGREEMENT;ASSIGNOR:BROOKTREE BROADBAND HOLDING, INC.;US-ASSIGNMENT DATABASE UPDATED:20100525;REEL/FRAME:18573/337Free format text: SECURITY AGREEMENT;ASSIGNOR:BROOKTREE BROADBAND HOLDING, INC.;REEL/FRAME:18573/337Nov 2, 2006ASAssignmentOwner name: CONEXANT, INC., NEW JERSEYFree format text: CHANGE OF NAME;ASSIGNOR:GLOBESPANVIRATA, INC.;REEL/FRAME:018471/0286Effective date: 20040528Owner name: GLOBESPAN SEMICONDUCTOR INC., NEW JERSEYFree format text: CHANGE OF NAME;ASSIGNOR:GLOBESPAN TECHNOLOGIES INC.;REEL/FRAME:018471/0124Effective date: 19971121Owner name: GLOBESPAN, INC., NEW JERSEYFree format text: CHANGE OF NAME;ASSIGNOR:GLOBESPAN SEMICONDUCTOR INC.;REEL/FRAME:018471/0138Effective date: 19990504Owner name: GLOBESPANVIRATA, INC., NEW JERSEYFree format text: CHANGE OF NAME;ASSIGNOR:GLOBESPAN, INC.;REEL/FRAME:018471/0253Effective date: 20011214Owner name: CONEXANT, INC.,NEW JERSEYFree format text: CHANGE OF NAME;ASSIGNOR:GLOBESPANVIRATA, INC.;US-ASSIGNMENT DATABASE UPDATED:20100525;REEL/FRAME:18471/286Free format text: CHANGE OF NAME;ASSIGNOR:GLOBESPANVIRATA, INC.;REEL/FRAME:18471/286Oct 30, 2003FPAYFee paymentYear of fee payment: 8Nov 30, 1999FPAYFee paymentYear of fee payment: 4Jun 11, 1998ASAssignmentOwner name: BANKAMERICA BUSINESS CREDIT, INC., CALIFORNIAFree format text: SECURITY AGREEMENT;ASSIGNOR:GLOBESPAN SEMICONDUCTOR INC.;REEL/FRAME:009257/0806Effective date: 19980514Jan 23, 1997ASAssignmentOwner name: AT&T CORP., NEW JERSEYFree format text: BILL OF SALE, CONVEYANCE, ASSIGNMENT AND TRANSFER OF ASSETS;ASSIGNOR:AT&T IPM CORP.;REEL/FRAME:008423/0761Effective date: 19950825Nov 12, 1996ASAssignmentOwner name: LUCENT TECHNOLOGIES INC., NEW JERSEYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AT&T CORP.;REEL/FRAME:008178/0161Effective date: 19960329Oct 10, 1996ASAssignmentOwner name: GLOBESPAN TECHNOLOGIES, INC. (FKA CAP ACQUISITIONFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LUCENT TECHNOLOGIES, INC.;REEL/FRAME:008167/0561Effective date: 19960731Jun 7, 1995ASAssignmentOwner name: AT&T CORP., NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AMERICAN TELELPHONE AND TELEGRAPH COMPANY;REEL/FRAME:007527/0274Effective date: 19940420Owner name: AT&T IPM CORP., FLORIDAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AT&T CORP.;REEL/FRAME:007528/0038Effective date: 19950523May 18, 1994ASAssignmentOwner name: AT&T CORP., NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AMRANY, DANIEL;REEL/FRAME:007079/0466Effective date: 19940516RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google