Source: http://www.google.com/patents/US7968958?ie=ISO-8859-1&dq=4200770
Timestamp: 2015-03-31 16:06:13
Document Index: 416042463

Matched Legal Cases: ['art 25', 'art 25', 'art 25', 'art 25', 'art 25', 'art 25', 'art 21', 'art 25', 'art 25', 'arts 11', 'arts 11', 'art 25', 'art 25', 'art 25', 'art 25', 'art 25', 'application No. 2008101284838', 'Application No. 2008']

Patent US7968958 - Semiconductor device and manufacturing method of the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device includes: a sensor element having a plate shape with a surface and including a sensor structure disposed in a surface portion of the sensor element; and a plate-shaped cap element bonded to the surface of the sensor element. The cap element has a wiring pattern portion facing the...http://www.google.com/patents/US7968958?utm_source=gb-gplus-sharePatent US7968958 - Semiconductor device and manufacturing method of the sameAdvanced Patent SearchPublication numberUS7968958 B2Publication typeGrantApplication numberUS 12/213,711Publication dateJun 28, 2011Filing dateJun 24, 2008Priority dateJul 2, 2007Fee statusPaidAlso published asEP2011762A2, EP2011762A3, US8264051, US20090008728, US20110147863Publication number12213711, 213711, US 7968958 B2, US 7968958B2, US-B2-7968958, US7968958 B2, US7968958B2InventorsTetsuo Fujii, Kazuhiko SugiuraOriginal AssigneeDenso CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (39), Non-Patent Citations (3), Referenced by (2), Classifications (12), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and manufacturing method of the same
US 7968958 B2Abstract
In the present embodiment, an N-type (100) silicon layer having a specific resistance ranging from, e.g., 0.001 Ω�cm to 0.02 Ω�cm is used as the first silicon layer 11. As the second silicon layer 12, an N-type (100) silicon substrate having a specific resistance ranging from, e.g., 0.001 Ω�cm to 10 Ω�cm is used
First, in the step shown in FIG. 5A, the monocrystalline silicon substrate 21 having a specific resistance of, e.g., 0.01 Ω�cm oriented in the (100) plane is prepared, which is a so-called silicon wafer. On the silicon substrate 21, a Si3N4 film with a thickness ranging from 1 μm to 2 μm is formed as the first insulating film 22. The Si3N4 film can be formed by an LPCVD method or a plasma CVD method.
Next, as shown in FIG. 6, the sensor portion 10 and the cap portion 20 are bonded to each other. Specifically, the wiring layer 14 of the sensor portion 10 and the second wiring layer 25 of the cap portion 20 are brought into opposing relation, the respective surfaces thereof are activated by sputtering with argon ions or the like in high vacuum, and then the wiring layers 14 and 25 are solidly bonded at a temperature ranging from a room temperature to 500� C. by a so-called direct bonding method, as shown in JP-H10-92702 A. In this manner, the peripheral portion 19 of the sensor portion 10 and the hermetically sealing part 25 b of the cap portion 10 are bonded to hermetically seal the sensor structures. On the other hand, by bonding the fixed electrode portions 17, the movable electrode fixing portions 15, and the connection portion 18 of the sensor portion 10 to the wiring part 25 a of the cap portion 25, the sensor structures and the connection portion 18 of the sensor portion 10 are electrically connected.
Additionally, the wiring part 25 a and the hermetically sealing part 25 b, each composing the second wiring layer 25, have equal heights from the surface of the silicon substrate 21. This allows the connection portion 18 and the sensor structures to be electrically connected by the wiring part 25 a by merely bonding the sensor portion 10 and the cap portion 20, and also allows the sensor structures to be hermetically sealed by the hermetically sealing part 25 b. Moreover, the recessed part 21 a is provided in the cap portion 20 to expose the connection portion 18 of the sensor portion 10 therefrom. The arrangement can keep a tool for performing wire bonding from contact with the cap portion 20, and also allows easy wire bonding to the connection portion 18. As a result, it is also unnecessary to provide the cap portion 20 with through holes for wire bonding. This can prevent an increase in the size of the cap portion 20, and therefore allows a reduction in chip size.
In the present embodiment, a description will be given only of a portion different from the semiconductor device according to the second embodiment. FIG. 9 is a schematic cross-sectional view of the semiconductor dynamic quantity sensor according to the present embodiment. The present embodiment has a configuration in which the wiring layer 14 is not provided on the first silicon layer 11 in the sensor portion 10 shown in FIG. 8, and the wiring part 25 a and the hermetically sealing part 25 b of the second wiring layer 25 of the cap portion 20 are connected directly to the first silicon layer 11 of the sensor portion 10. Particularly in the case where P-type silicon is used in the first silicon layer 11 and an Al layer is used as the second wiring layer 25, the specific resistance of silicon is in the range of 0.01 to 1 Ω�cm so that an ohmic contact is more easily made than with N-type silicon. Accordingly, P-type silicon at a relatively low concentration can be used.
By thus providing the substrate contact parts 11 a electrically connecting the peripheral portion 19 and the second silicon layer 12 to be located therebetween, the second silicon layer 12 can be set at the same potential as that of the silicon substrate 21 of the cap portion 20, and a shield structure can be formed. Since this allows the second silicon layer 12 to reduce influence from the outside, a shield effect higher than that of the structure shown in FIG. 15 can be obtained. In the case of forming the polysilicon layer by a CVD method in the manufacturing method, when the polysilicon layer is formed at a higher temperature ranging from, e.g., 900� C. to 1200� C., the portions of the substrate contact parts 11 a can be formed of monocrystalline silicon by epitaxial growth.
In the present embodiment, the wiring layer 14 is removed from the movable electrode 100 so that the upper gap of a height corresponding to the thickness of the wiring layer 14 removed from the movable electrode 110 is formed. The acceleration in the Z-axis direction is detected by detecting a change in the distance between the movable electrode 110 and the counter electrode 25 c. Thus, by providing the counter electrode 25 c on the second insulating film 24, the distance between the movable electrode 110 and the counter electrode 25 c can be reduced to a value smaller than in the case where the first wiring layer 23 is used as the fixed electrode. Accordingly, the output range of a detected value can be widened.
In each of the embodiments described above, the semiconductor device provided with the hermetically sealing part 25 b is shown. However, the hermetically sealing part 25 b functions to hermetically seal the sensor structures 15 to 17, and need not necessarily be provided in the semiconductor device. In other words, the semiconductor device may also have a structure which is not provided with the hermetically sealing part 25 b. In each of the embodiments described above, N-type monocrystalline silicon is used for each of the silicon layers 11 and 12 of the sensor portion 10. However, it is also possible to use, e.g., an N+-type monocrystalline silicon. Although the silicon substrate 21 and the silicon layers 11 and 12 that have been used heretofore are each at a high concentration, it is also possible to use a substrate and layers obtained by implanting impurity ions into a low-concentration substrate and low-concentration layers, or a substrate and layers each obtained by increasing the concentration of the entire part or only a surface thereof by a vapor-phase impurity diffusion method or the like.
In the embodiments described above, the individual acceleration sensors each for detecting the acceleration in the Z-axis direction or in the direction perpendicular to the Z-axis direction have been described. However, it is also possible to produce a biaxial acceleration sensor in which an acceleration sensor for detecting the acceleration in the Z-axis direction and an acceleration sensor for detecting the acceleration in the direction perpendicular to the Z-axis direction are integrated on a single chip. Likewise, it is also possible to integrate sensors capable of respectively detecting accelerations along the Z-axis, along the X-axis, and along a Y-axis perpendicular to the X-axis and the Z-axis on a single chip. In this case, each of the acceleration sensors for detecting the accelerations in the individual axis directions can be individually encircled by the hermetically sealing part 25 b, or all the acceleration sensors can also be encircled by a single hermetically sealing part 25 b. While the invention has been described with reference to preferred embodiments thereof, it is to be understood that the invention is not limited to the preferred embodiments and constructions. The invention is intended to cover various modification and equivalent arrangements. In addition, while the various combinations and configurations, which are preferred, other combinations and configurations, including more, less or only a single element, are also within the spirit and scope of the invention.
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sealing package micro sensor pp. 1-8, published Jul. 4, 2001.2Office Action dated Dec. 4, 2009 issued in the corresponding Chinese patent application No. 2008101284838 (English translation enclosed).3Office Action dated Jun. 2, 2009 from the Japan Patent Office in the corresponding JP Application No. 2008-004144 (and English Translation).* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8067769 *Nov 24, 2006Nov 29, 2011Panasonic Electric Works Co., Ltd.Wafer level package structure, and sensor device obtained from the same package structureUS20090282917 *May 19, 2008Nov 19, 2009Cenk AcarIntegrated multi-axis micromachined inertial sensing unit and method of fabrication* Cited by examinerClassifications U.S. Classification257/415, 257/E29.324, 257/419, 257/417, 257/418International ClassificationH01L29/84Cooperative ClassificationB81B2207/097, G01P15/0802, B81C2203/0118, B81B7/007, B81B2207/07European ClassificationB81B7/00P14Legal EventsDateCodeEventDescriptionDec 19, 2014FPAYFee paymentYear of fee payment: 4Jun 24, 2008ASAssignmentOwner name: DENSO CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUJII, TETSUO;SUGIURA, KAZUHIKO;REEL/FRAME:021187/0735;SIGNING DATES FROM 20080610 TO 20080611RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services