Source: https://patents.google.com/patent/US20070290322A1/en
Timestamp: 2019-09-18 09:57:35
Document Index: 745510266

Matched Legal Cases: ['art 700', 'art 700', 'art 700', 'art 700', 'art 900', 'art 900', 'art 900']

US20070290322A1 - Thermal improvement for hotspots on dies in integrated circuit packages - Google Patents
US20070290322A1
US20070290322A1 US11/514,916 US51491606A US2007290322A1 US 20070290322 A1 US20070290322 A1 US 20070290322A1 US 51491606 A US51491606 A US 51491606A US 2007290322 A1 US2007290322 A1 US 2007290322A1
US11/514,916
US9013035B2 (en
2007-12-20 Publication of US20070290322A1 publication Critical patent/US20070290322A1/en
2015-04-21 Publication of US9013035B2 publication Critical patent/US9013035B2/en
P═P D +P S =ACV 2 f+VI leak
where A is the gate activity factor, C is the total capacitance load of all gates, V is the peak-to-peak supply voltage swing, f is the frequency, and Ileak is the leakage current. The static power term, PS=VIleak, is the static power dissipated due to leakage current, Ileak. A further description regarding static power is provided in Kim et al, Leakage Current: Moore's Law Meets Static Power, IEEE Computer, 36(12): 68-75, December 2003, which is incorporated by reference herein in its entirety.
For example, FIG. 1A shows a die up plastic ball grid array (PBGA) package 100 integrated with a drop-in heat spreader 104. In package 100, IC die 102 is attached to a substrate 110 by die attach material 106 and is interconnected with wirebond 114. Package 100 can be connected to a printed wire board (PWB) (not shown) by solder balls 108. A drop-in heat spreader 104 is mounted to substrate 110, and conducts heat away from die 102. Mold compound 112 encapsulates package 100, including die 102, wirebond 114, all or part of drop-in heat spreader 104, and all or part of the upper surface of substrate 110. Drop-in heat spreader 104 is commonly made of copper or other material that is thermally more conductive than mold compound 112. Thermal conductivity values are around 390 W/m*° C. for copper and 0.8 W/m*° C. for mold compound materials, respectively.
For example, FIG. 1B shows a perspective view of a silicon die 102, and in particular shows the temperature distribution on silicon die 102 in a PBGA with no external heat sink. The temperature difference across the die 102 is 13.5° C. FIG. 1C shows die 102 of FIG. 1B, illustrating the effect of adding a drop in heat spreader and a heat sink to the package of die 102. The temperature difference remains 13.0° C. with a large size (45 mm×45 mm×25 mm) external aluminum pin-fin heat sink attached on top of the exposed drop-in heat spreader. Both the drop-in heat spreader and the external heat sink are ineffective to reduce the on-chip temperature differences caused by the hot spots.
Active on-chip cooling methods that use electrical energy to remove heat from the IC chip are known in the art. For example, some have suggested pumping liquid coolant through micro-channels engraved in silicon to circulate on the semiconductor die and carry away waste heat. A further description regarding liquid cooling is provided in Bush, “Fluid Cooling Plugs Direct onto CMOS,” Electronic News, Jul. 20, 2005, http://www.reed-electronics.com/electronicnews/article/CA626959?nid=2019 &rid=550846255), which is incorporated by reference herein in its entirety. See also Singer, “Chip Heat Removal with Microfluidic Backside Cooling,” Electronic News, Jul. 20, 2005, which is incorporated by reference herein in its entirety.
Methods and apparatuses for improved integrated circuit (IC) packages are described herein.
Methods, systems, and apparatuses for IC device packaging technology are described herein. In particular, methods, systems, and apparatuses for the (1) cooling of hotspots on IC semiconductor die, (2) heat spreading for IC packages, and (3) thermal interconnection technology in IC packaging are described.
In embodiments, thermal interconnect members are thermally conductive solder balls, solder bumps, posts, or other thermally conductive structures. In further embodiments, the thermal interconnect members are also electrically conductive. For the purposes of illustration, exemplary embodiments using a solder ball-based thermal interconnect structure are referred to below to explain the principles of the invention. However, embodiments may use other thermal interconnect structures. Thermal interconnect members may be made of a metal, such as gold, copper, aluminum, silver, nickel, or tin, may be made of a combination of metals/alloy, such as solder, a eutectic (tin, lead), a lead-free solder, may be made of a thermally conductive epoxy or other adhesive material, or may be made of other thermally conductive materials. In an embodiment, a thermal interconnect member is made of a core material that is coated with a bonding material such as solder, gold, silver, an epoxy, or other joining materials that mechanically bonds the thermal interconnect member with contact pads on a semiconductor die. In an embodiment, thermal interconnect members may be pre-deposited at pre-defined contact pads on a surface of the semiconductor die. In a further embodiment, one or more thermal interconnect members are also coupled to a heat spreader.
By attaching thermal interconnect members with a high power dissipation density to contact pads at areas on the die, which may be referred to as points or “blocks”, heat generated within these hotspots (also known as hot blocks) can be conducted away from the IC die directly to the external environment or through a thermally conductive heat spreader (if present) to the environment. In an embodiment, the placement of the one or more thermal interconnect members is based on a power map of a semiconductor die for a specific application. In another application, the same semiconductor die may have different on-chip thermal interconnect member locations if a different power maps results from the application. For example, this may occur when different functional blocks of the die switch from a “power-up” mode to a “power-down” mode, or vice versa, for different applications.
FIGS. 2D-2E show perspective views of an exemplary embodiment of a die up BGA IC package 250. FIG. 2F illustrates a side cross sectional view of package 250. Package 250 is similar to package 200, except that mold compound 112 does not encapsulate top surfaces 252 of thermal interconnect members 208. In an embodiment, a top layer of mold compound 112 is removed to expose surfaces 252 of thermal interconnect members 208. In such an embodiment, thermal interconnect members 208 are truncated to form the planar exposed surfaces 252 of thermal interconnect members 208, and surfaces 252 are co-planar with a top surface of mold compound 112. Surfaces 252 can also be referred to as thermal contact pads. Exposed surfaces 252 on package 250 can be used for electrical connections (e.g., ground, power, or signal) to die 102. Various methods exist to truncate the solder spheres embedded in a package mold, including the method illustrated in FIG. 5E, and further described below. Additional example description for solder ball truncation and exposure on a mold top are provided in U.S. Pat. Appl. No. 60/799,657, titled “Interconnect Structure and Formation for Package Stacking of Molded Plastic Area Array Package,” filed May 12, 2006, which is incorporated by reference herein in its entirety.
For example, in an embodiment where thermal interconnect members 208 are solder balls, a junction-to-case thermal resistance is reduced because the thermal conductivity of typical (lead-free and tin/lead) IC package solder balls is around 50˜60 W/m*° C., which is many times higher than a typical mold compound 112, which may have a thermal conductivity of approximately 0.8 W/m*° C., for example. Furthermore, the solder balls forming thermal interconnect members 208 attached to IC die 102 extend the heat conduction area from the surface of die 102 to a top surface of mold compound 112. The thermal performance improvement is particularly significant for packages with a small size of die 102, when the solder balls displace a relatively large area of mold compound 112 on the top surface of die 102, providing a conductive path for heat dissipation through the top surface of package 250. Furthermore, when an external heat sink device, such as a heat sink or a metal plate, is attached to the top of a package such as packages 200 and 250, the thermal performance of the package may improve. Examples of such embodiments are described in detail below.
In embodiments, thermal interconnects facilitate on-chip power/heat dissipation from pre-selected locations on a semiconductor die. In an exemplary embodiment, at least one thermal interconnect is attached to an IC die and coupled to at least one heat spreader embedded or attached to the IC package. In an example embodiment, the heat spreader is encapsulated in a mold compound. The heat spreader may be exposed on a top surface of the package for heat dissipation to the ambient environment, including for attachment of a heat sink. The heat spreader can alternatively be entirely encapsulated within the mold compound of a molded IC package.
In an embodiment, a distance between a bottom surface of an integrated heat spreader and a top surface of the die is less than a “loop-height” of the wire bond (i.e., a distance from the apex of the wire loop to the surface of IC die). In such an embodiment, a size of the heat spreader may be confined by a space between the wire bond pads on the opposite sides of the top surface of the IC die.
In an embodiment where the thermal interconnects are electrically conductive, one or more thermal interconnects may be attached to the ground or power net of the IC die to provide an alternative route for current or on-chip power delivery from the heat spreader. Examples of such an arrangement are described in U.S. patent application Ser. No. 10/952,172, titled “Die Down Ball Grid Array Packages And Method For Making Same,” filed Sep. 29, 2004, which is incorporated herein by reference in its entirety. This may be effective in reducing the lengths of on-chip power supply current paths, thus reducing IR voltage drops within the IC die.
In an embodiment, the size of the heat spreader is less than a size of the package mold body, as illustrated in FIGS. 3A-3C. Alternatively, the size of the heat spreader size can also be substantially the same size as the package mold body, or larger than the size of package mold body. Examples of this are described in U.S. patent application Ser. No. 10/870,927, titled “Apparatus and Method for Thermal and Electromagnetic Interference (EMI) Shielding Enhancement in Die-Up Array Packages,” filed Jun. 21, 2004, which is incorporated by reference herein in its entirety.
FIGS. 3A-3E illustrate exemplary embodiments of molded plastic fine pitch ball grid array (BGA) packages having a heat spreader 302 which is at least partially covered by mold compound 112. In the embodiments of FIGS. 3A-3E, the configuration of heat spreader 302 is varied from package to package.
FIGS. 4A-4B illustrate exemplary embodiments of molded plastic ball grid array (PBGA) packages having at least one thermal interconnect member 208 coupled to an integrated heat spreader 302.
Embodiments of the invention can be implemented in many IC packages. For example, FIGS. 5A-5C illustrate example embodiments having at least one thermal interconnect member 208 and a heat spreader 502 integrated with a leadframe package. For example, FIG. 5A illustrates a package 500 in which die 102 is attached to a die attach pad 504 of a leadframe 516. Leadframe 516 includes a plurality of leads 518 and die attach pad 504. Die 102 is electrically interconnected with die attach pad 504 and/or leads 518 by one or more wire bonds 514. Furthermore, leads 518 may be electrically interconnected with die attach pad 504 with one or more wire bonds 514. Heat spreader 502 is cap-shaped, having a cavity 520 facing towards die 102. Die 102 and a bottom surface 522 in cavity 520 of heat spreader 502 are connected by one or more thermal interconnect members 208, which may or may not be truncated.
FIGS. 6A and 6B illustrate example embodiments of no-lead quad flat packages (QFP), also known as micro leadframe packages (MLP) or micro lead frame (MLF) IC packages, each having at least one thermal interconnect member 208 and a heat spreader 602 integrated therein. For example, FIG. 6A illustrates a package 600 in which die 102 is attached to a die attach pad 604. Die 102 is electrically interconnected with die attach pad 604 and/or leads 616 by one or more wire bonds 614. Heat spreader 602 is cap-shaped, having a cavity 620 facing towards die 102. Die 102 and a bottom surface 622 in cavity 620 of heat spreader 602 are connected by one or more thermal interconnect members 208, which may or may not be truncated.
FIG. 7A shows a flowchart 700 providing an example process for manufacturing embodiments of the invention. Flowchart 700 is described with reference to FIGS. 7B-D, which show a BGA package at various stages of manufacture. Flowchart 700 may be applied in a modified or non-modified manner to manufacture other package types, as would be understood by persons skilled in the relevant art(s) from the teachings herein. In flowchart 700, an optional step of attaching a heat spreader (step 710) may be performed depending on whether a heat spreader is desired to be present.
FIG. 9A shows a flowchart 900 providing an example process for manufacturing embodiments of the invention. Flowchart 900 is described with reference to FIGS. 9B-D, which show a BGA package at various stages of manufacture. Flowchart 900 may be applied in a modified or non-modified manner to manufacture other package types, as would be understood by persons skilled in the relevant art(s) from the teachings herein.
In embodiments, thermal interconnect members may be used to couple a heat spreader to a substrate in an integrated circuit package. For example, FIGS. 10A-10C illustrate cross-sectional views of example BGA packages having a heat spreader thermally coupled to the package substrate, according to exemplary embodiments of the invention. The embodiments of FIGS. 10A-10C are provided for illustrative purposes. In alternative embodiments, thermal interconnect members may be used in other types of IC packages to couple heat spreaders to substrates. Furthermore, when the thermal interconnect members are solder balls, they may be truncated or non-truncated. Other materials such as copper, gold, other metals and/or metal alloys can be used for thermal interconnect members, including the materials described elsewhere herein or otherwise known.
an IC die having a contact pad, wherein the contact pad is located at a hotspot on a surface of the IC die that has a temperature that is higher than a temperature of a second location on the surface of the die during operation of the die; and
a thermal interconnect member attached to the contact pad.
2. The IC package of claim 1, wherein the thermal interconnect member is configured to cause a temperature of the hotspot to decrease towards a temperature of the second location during operation of the die.
a mold compound that encapsulates the die and at least a portion of the thermal interconnect member.
4. The package of claim 1, wherein the thermal interconnect member is electrically and thermally coupled to the contact pad.
a heat spreader thermally coupled to the thermal interconnect member.
6. The package of claim 5, wherein the heat spreader is electrically coupled to the thermal interconnect member.
a mold compound that encapsulates the die, the thermal interconnect member, and a portion of the heat spreader.
a mold compound that encapsulates the die, the thermal interconnect member, and the heat spreader.
9. The package of claim 5, wherein the heat spreader has an area plated with a material at a location attached to the thermal interconnect member.
a heat spreader thermally coupled to the first thermal interconnect member and the at least one additional thermal interconnect member.
14. The package of claim 3, wherein a surface of the mold compound has a cavity formed therein.
a heat spreader mounted in the cavity.
16. The package of claim 3, wherein a portion of the thermal interconnect member is exposed at a surface of the mold compound.
(a) attaching a die to a substrate, the die having a contact pad located at a hotspot on a surface of the IC die that radiates more heat relative to a second location on the surface of the die during operation of the die;
(c) coupling a thermal interconnect member to the contact pad; and
(d) encapsulating the die, at least one wire bond, and at least a portion of the thermal interconnect member in a mold compound.
(e) exposing the at least one thermal interconnect member.
removing an entire layer of the mold compound.
27. The method of claim 25, wherein step (e) further comprises:
removing a portion of a layer of the mold compound.
(e) coupling a heat spreader to the thermal interconnect member.
29. The method of claim 28, wherein step (e) is performed before step (d).
attaching the plated area to a surface of the thermal interconnect member.
34. The method of claim 24, wherein step (c) comprises:
coupling at least one additional thermal interconnect member to at least one additional contact pad on the surface of the die, the at least one additional contact pad being located on at least one additional hotspot on the surface of the die.
(e) coupling a heat spreader to the first thermal interconnect member and the at least one additional thermal interconnect member.
(e) forming a cavity in a surface of the mold compound.
(f) mounting a heat spreader in the cavity.
38. The method of claim 24, wherein the thermal interconnect member is a solder ball, wherein step (c) comprises:
mounting the solder ball to the contact pad.
39. The method of claim 25, wherein the thermal interconnect member is a solder ball, wherein step (e) comprises:
truncating the solder ball.
(e) performing a thermal analysis of the die to determine at least one hotspot of the die.
41. An integrated circuit (IC) package, comprising:
a thermal interconnect member that couples the first surface of the substrate to a surface of the heat spreader.
42. The IC package of claim 41, wherein the thermal interconnect member is a solder ball.
a second thermal interconnect member that couples the contact pad to the surface of the heat spreader.
45. The IC package of claim 41, wherein the thermal interconnect member is attached to an electrically conductive feature on the first surface of the substrate.
(b) coupling a thermal interconnect member to the substrate;
(c) encapsulating the die and at least a portion of the thermal interconnect member in a mold compound; and
51. The method of claim 50, wherein step (b) is performed before step (d).
attaching a second thermal interconnect member to a contact pad located on a surface of the IC die at a hotspot that radiates more heat relative to a second location on the surface of the die during operation of the die.
54. The method of claim 50, wherein the thermal interconnect member is a solder ball, wherein step (b) comprises:
coupling the solder ball to the substrate.
55. The method of claim 50, wherein step (b) comprises:
coupling a plurality of thermal interconnect members to the substrate; and
coupling the plurality of thermal interconnect members to the heat spreader.
US11/514,916 2006-06-20 2006-09-05 Thermal improvement for hotspots on dies in integrated circuit packages Active 2029-04-21 US9013035B2 (en)
EP07004382A EP1870933A2 (en) 2006-06-20 2007-03-02 Thermal improvement for hotspots on dies in integrated circuit packages
CN200710126476XA CN101127334B (en) 2006-06-20 2007-06-18 Integrated circuit packages and its manufacture method
TW096122029A TWI423404B (en) 2006-06-20 2007-06-20 Thermal improvement for hotspots on dies in integrated circuit packages
HK08108181.4A HK1119482A1 (en) 2006-06-20 2008-07-24 Integrated circuit package and its manufacturing process
US14/668,276 US20150200149A1 (en) 2006-06-20 2015-03-25 Thermal improvement for hotspots on dies in integrated circuit packages
US14/668,276 Division US20150200149A1 (en) 2006-06-20 2015-03-25 Thermal improvement for hotspots on dies in integrated circuit packages
US20070290322A1 true US20070290322A1 (en) 2007-12-20
US9013035B2 US9013035B2 (en) 2015-04-21
US11/514,916 Active 2029-04-21 US9013035B2 (en) 2006-06-20 2006-09-05 Thermal improvement for hotspots on dies in integrated circuit packages
US14/668,276 Abandoned US20150200149A1 (en) 2006-06-20 2015-03-25 Thermal improvement for hotspots on dies in integrated circuit packages
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHAO, SAM ZIQUN;KHAN, REZAUR RAHMAN;REEL/FRAME:018263/0782