Source: http://www.google.com/patents/US20070269931?ie=ISO-8859-1
Timestamp: 2015-04-28 08:09:56
Document Index: 76076495

Matched Legal Cases: ['Application No. 2006', 'art 44', 'art 46', 'art 44', 'art 42', 'art 44', 'art 42', 'art 44', 'art 42', 'art 42', 'art 42', 'art 42']

Patent US20070269931 - Wafer level package and method of fabricating the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsWafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the...http://www.google.com/patents/US20070269931?utm_source=gb-gplus-sharePatent US20070269931 - Wafer level package and method of fabricating the sameAdvanced Patent SearchPublication numberUS20070269931 A1Publication typeApplicationApplication numberUS 11/752,219Publication dateNov 22, 2007Filing dateMay 22, 2007Priority dateMay 22, 2006Also published asUS7847416, US20090267211Publication number11752219, 752219, US 2007/0269931 A1, US 2007/269931 A1, US 20070269931 A1, US 20070269931A1, US 2007269931 A1, US 2007269931A1, US-A1-20070269931, US-A1-2007269931, US2007/0269931A1, US2007/269931A1, US20070269931 A1, US20070269931A1, US2007269931 A1, US2007269931A1InventorsHyun-Soo Chung, In-Young Lee, Son-Kwan Hwang, Dong-Ho Lee, Seong-Deok HwangOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManReferenced by (16), Classifications (30), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetWafer level package and method of fabricating the same
US 20070269931 A1Abstract
Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.
1. A method of fabricating a wafer level package, the method comprising:
forming one or more semiconductor chips on a wafer, each semiconductor chip having a connection pad; patterning a bottom surface of the wafer to form a trench under at least a portion of the connection pad; patterning a bottom surface of the trench to form a via hole exposing a bottom surface of the connection pad; and forming a connecting device connected to the connection pad through the via hole. 2. The method of claim 1, wherein the wafer comprises chip regions where the semiconductor chips are disposed and a scribe lane region between the chip regions, and
wherein the trench is formed under the scribe lane region and edges of the chip regions. 3. The method of claim 2, wherein the trench has a larger width than the scribe lane region.
4. The method of claim 2, wherein the via hole penetrates the wafer under edges of the chip regions, such that the bottom surface of the via hole and the connection pad can be coupled.
5. The method of claim 2, after forming the connecting device, further comprising:
performing a sawing process to cut the wafer along the scribe lane region to separate each of the semiconductor chips; and stacking the separated semiconductor chips sequentially on an interconnection substrate, wherein the stacking of the separated semiconductor chips comprises attaching the connecting device formed on one semiconductor chip to the connection pad formed on another semiconductor chip. 6. The method of claim 5, after stacking the separated semiconductor chips on the interconnection substrate, further comprising:
injecting a protection layer into a gap between the interconnection substrate and the semiconductor chips to enclose the connecting device. 7. The method of claim 5, wherein the sawing process comprises forming a buffer layer filling the trench, the buffer layer exposing a bottom region of the connecting device.
8. The method of claim 1, wherein the trench is formed by using at least one of a sawing process, and a photolithography and etching process.
9. The method of claim 1, wherein forming the trench comprises:
patterning a backside of the wafer until the portion of the wafer in the trench has a thickness in a range of about 1 to about 50 micrometers. 10. The method of claim 1, wherein the via hole is formed using at least one of a laser drilling process, and a photolithography and etching process.
11. The method of claim 10, wherein the photolithography and etching process comprises an etch recipe having an etch selectivity between the connection pad and the wafer.
12. The method of claim 10, wherein the laser drilling process comprises:
forming a preliminary via hole under the connection pad using laser drilling; and etching the preliminary via hole, thereby forming the via hole. 13. The method of claim 1, before forming the via hole, further comprising performing a backside polishing process to decrease a thickness of the wafer.
14. The method of claim 13, wherein the backside polishing process is performed before forming the trench.
15. The method of claim 13, wherein the backside polishing process is performed after forming the trench.
16. The method of claim 13, wherein the backside polishing process comprises forming a sacrificial layer filling the trench.
17. The method of claim 16, wherein the sacrificial layer has an etch selectivity with respect to the wafer.
18. The method of claim 13, wherein the backside polishing process comprises forming a supporting layer on the wafer.
19. The method of claim 18, wherein the supporting layer is removable by exposure to one or more of heat and ultraviolet radiation.
20. The method of claim 18, wherein the supporting layer has substantially the same thermal expansion coefficient as the wafer.
21. The method of claim 1, wherein forming the connecting device comprises:
forming a connecting plug which fills the via hole and is connected to the connection pad; and forming a bump connected to the connection pad through the connecting plug. 22. The method of claim 21, wherein forming the connecting device further comprises:
forming an under-bump metallization (UBM) pattern before forming the connecting plugs, the UBM pattern covering the bottom surface of the connection pad exposed through the via hole. 23. The method of claim 21, wherein forming the connecting device further comprises at least one of an electroplating process, a solder jet process, a screen printing process, and a Controlled Collapse Chip Connection New Process (C4NP).
24. The method of claim 23, wherein the connection pad are a seed layer for the electroplating process when the electroplating process is used to form the connecting device.
25. The method of claim 1, wherein forming each of the semiconductor chips comprises:
forming an internal circuit comprising microelectronic devices on the wafer; forming an interconnection structure connecting the microelectronic devices with each other; forming an input/output pad connected to the internal circuit through the interconnection structure; and forming a redistribution structure connected to the input/output pad, wherein the redistribution structure comprises the connection pad which is disposed on the via hole and electrically connects the connecting device to the input/output pad. 26. A wafer level package, comprising:
an interconnection substrate; and one or more semiconductor chips stacked on the interconnection substrate, wherein at least one of the semiconductor chips comprises:
a central region for an internal circuit and a connection region disposed adjacent to the central region;
a redistribution structure connected to the internal circuit on the semiconductor chip, the redistribution structure comprising a connection pad disposed on the connection region; and
a connecting device in the connection region, the connecting device penetrating through the semiconductor chip and connected to the connection pad,
wherein the thickness of the connection region is smaller than the thickness of the central region.
27. The wafer level package of claim 26, wherein the at least one of the semiconductor chips further comprises a semiconductor substrate, the internal circuit disposed on the semiconductor substrate, an interconnection structure connected to the internal circuit, and an input/output pad connected to the interconnection structure,
wherein the connecting device comprises a connection plug penetrating the semiconductor chip and a bump disposed under the connection region to be connected to the connection plug. 28. The wafer level package of claim 27, wherein the thickness of the bump is larger than the difference in thickness between the central region and the connection region.
29. The wafer level package of claim 27, further comprising:
an under-bump metallization (UBM) layer interposed between the connection plug and the connection pad. 30. The wafer level package of claim 29, wherein the UBM layer comprises one or more of nickel (Ni), chrome (Cr), copper (Cu), tungsten titanium (TiW) and gold (Au).
31. The wafer level package of claim 27, wherein the semiconductor chips are electrically connected to each other through the bump of a semiconductor chip and the connection pad of another semiconductor chip.
32. The wafer level package of claim 31 further comprising:
a protection layer disposed between the semiconductor chips, the protection layer enclosing the bump. 33. The wafer level package of claim 27, wherein the bump of the at least one of semiconductor chips contacts a connection terminal on the interconnection substrate, thereby electrically connecting the at least one of semiconductor chips to the interconnection substrate.
34. The wafer level package of claim 33, further comprising a protection layer disposed between the at least one of semiconductor chips and the interconnection substrate, the protection layer enclosing the bump.
This U.S. non-provisional patent application claims priority under 35 U.S.C. � 119 to Korean Patent Application No. 2006-45802, filed on May 22, 2006, the entire contents of which are hereby incorporated by reference.
The present invention relates to a semiconductor package and a method of fabricating the same. More specifically, the present invention is directed to a wafer level package and a method of fabricating the same.
Generally, semiconductor manufacturing can be divided into two kinds of processes. The two kinds of processes are a front-end process to manufacture IC chips on a wafer by means of processes such as photolithography/deposition/etch, and a back-end process involving assembling and packaging each of the IC chips. Four significant functions of the packaging process are as follows:
1. Protection of the IC chips from the environment and handling damage.
2. Completing interconnections to carry electrical signals into and out of the IC chip.
3. Providing physical support for the IC chip.
4. Heat dissipation.
In addition to the above explained functions, as semiconductor devices continue to be scaled down and as portable electronic devices are becoming popular, several additional functions, such as the enhancement of electrical performance and reductions in cost, weight and thickness, are being required from the packaging process. Recently in order to satisfy this technological demand, methods of using an interconnection structure which penetrates semiconductor chips to electrically connect the semiconductor chips have been proposed.
FIG. 1 is a cross-sectional view of a conventional stack-type package.
Referring to FIG. 1, a plurality of package units 60 are stacked sequentially on an interconnection substrate 20 having a connection terminal 22 and a bump 24 coupled to the connection terminal 22. Each of the package units 60 includes a semiconductor chip 10 having input/output pads 12 and an interconnection structure penetrating the semiconductor chip 10 to be connected to the input/output pads 12.
More specifically, the interconnection structure includes a bottom conductive pattern 30 which is connected to the input/output pad 12 and covers an inside wall of a via hole 11 penetrating the semiconductor chip 10, a plug pattern 40 filling the via hole 11 having the bottom conductive pattern 30, and an under-bump metallization (UBM) pattern 50 disposed on the plug pattern 40. Here, the plug pattern 40 may be divided into a plug part 44 filling the via hole 11, a connecting part 46 which is disposed on the plug part 44 to be extended to a top surface of the input/output pad 12, and a protruding part 42 which is disposed under the plug part 44 to protrude from a bottom surface of the semiconductor chip 10. The protruding part 42 and the plug part 44 may be formed by the same process or by separate fabricating processes.
According to the above explained conventional art, the package units 60 and the interconnection substrate 20 are electrically connected through the interconnection structure. More specifically, the protruding part 42 of one package unit is electrically connected to the UBM pattern 50 of another package unit or the connection terminal 22 of the interconnection substrate 20. Since the conventional wire bonding process can be minimized or eliminated by the afore-mentioned connecting method, this package technology using the plug structure is especially desirable in application fields in which a high performance and a small form-factor are required.
However, according to conventional art, in order to construct the via hole 11 and an interconnection structure penetrating the via hole 11, a complicated fabricating process is required which may increase the fabricating costs and increase the number of defective products. In addition, in order to secure stability of the electrical connections, a solder bump may be formed at a bottom surface of the package units 60. (For example, the protruding part 42 may be substituted with a solder bump). However, contrary to the technical trend toward a small thickness in the packaging art, this method results in an increase of the space h1 between the package units 60 and an increase of the space h2 between the package unit 60 and the interconnection substrate 20. Also, in the conventional packaging scheme, a break of the protruding part 42 may often occur because a mechanical force may be focused on the protruding part 42 during the process for adhering semiconductor chips.
Exemplary embodiments of the present invention are directed to a wafer level package and method of fabricating the same. In an exemplary embodiment, the method may include fabricating a wafer level package comprising: forming semiconductor chips having a connection pad on a wafer; patterning a bottom surface of the wafer to form a trench under the connection pad; patterning a bottom surface of the trench to form a via hole exposing a bottom surface of the connection pad; and forming a connecting device connected to the connection pad through the via hole.
In another exemplary embodiment, the device may include a wafer level package having semiconductor chips stacked on an interconnection substrate, wherein the wafer level package comprises: the semiconductor chip comprising a central region for an internal circuit and a connection region disposed around the central region; a redistribution structure connected to the internal circuit on the semiconductor chip, the redistribution structure comprising a connection pad formed on the connection region; and a connecting device in the connection region, the connecting device penetrating through the semiconductor chip to be connected to the connection pad, wherein the thickness of the connection region is smaller than that of the central region.
Embodiments of the present invention provide a wafer level package with reduced fabrication costs, lower overall package thickness, and improved reliability as compared to the conventional art.
FIG. 2A and FIG. 2B are process flow charts to describe a method of fabricating a wafer level package according to exemplary embodiments of the present invention.
FIGS. 3A to 7A, FIG. 8 and FIG. 9 are cross-sectional views illustrating a method of fabricating a wafer level package according to an embodiment of the present invention.
FIGS. 3B to 7B are perspective views illustrating a method of fabricating a wafer level package according to an embodiment of the present invention.
FIG. 10 is a perspective view illustrating a wafer level package according to embodiments of the present invention.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being �on� another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numbers refer to like elements throughout.
FIG. 2A is a process flow chart of a method of fabricating a wafer level package according to exemplary embodiments of the present invention. FIGS. 3A to 7A, FIG. 8 and FIG. 9 are cross-sectional views of a method of fabricating a wafer level package according to some embodiments. Also, FIGS. 3B to 7B are perspective views of a method of fabricating a wafer level package according to some embodiments.
Referring to FIG. 2A, FIG. 3A and FIG. 3B, semiconductor chips are formed on a wafer 100 (S10). The wafer 100 includes chip regions CR where the semiconductor chips are formed and a scribe lane region SR disposed between the chip regions CR. Each of the semiconductor chips are separated from the wafer by a subsequent sawing process S70, which is performed along the scribe lane region SR. Each of the semiconductor chips has an internal circuit (not illustrated) and input/output pads 110 connected to the internal circuits. The internal circuit includes microelectronic devices (not shown) and the semiconductor chips also include an interconnection structure (not shown) connecting the microelectronic devices to the input/output pads 110. In addition, a protection layer pattern 120 exposing the input/output pad 110 may be disposed on the wafer 100.
Subsequently, a redistribution structure 130 is formed on the resultant structure where the input/output pads 110 are formed by means of a redistribution process (S20). The redistribution structure 130 is extended across the top of the chip region CR and is connected to the input/output pad 110. An insulation layer 140 may be disposed on the redistribution structure 130. The insulation layer 140 has openings 145 which are formed over the chip region CR to expose top surfaces of the redistribution structure 130. The insulation layer 140 may be made of adhesive material. A region of the redistribution structure 130 exposed by the openings 145 is used as a connecting pad for electrical connection with other semiconductor chips.
The process of forming a redistribution structure 130 may include forming a mold layer which has a mold opening defining a shape of the redistribution structure 130 on the wafer with the input/output pad 110 and filling the mold opening with a metal layer which is formed by using an electroplating method. According to an exemplary embodiment of the present invention, before forming the metal layer, forming a seed layer used as a seed electrode during the electroplating process may further be included. The thickness of the mold layer (the thickness of the redistribution structure 130, in essence) may be in a range of about 1 to 50 micrometers, and more desirably between about 2 to 10 micrometers. However, the method of fabricating the redistribution structure 130 is not limited to the specific method described above and may be fabricated using other known methods.
Referring to FIG. 2A, FIG. 4A and FIG. 4B, a trench 105 having a smaller thickness than the wafer 100 is formed on the back side 101 of the wafer where the redistribution structure 130 (S30) is formed. The trench 105 is formed along the scribe lane region SR, and a width W2 of the trench 105 is formed larger than a width W1 of the scribe lane region SR. In detail, the chip region CR may be separated into a central region R1 where the internal circuits are disposed, and a connection region R2 disposed around the central region R1. The trench 105 is formed at the scribe lane region SR and the connection region R2.
The depth of the trench 105 is a process variable which decides the length of via holes that are subsequently formed. According to an exemplary embodiment, the method of forming the trench 105 includes patterning the back side of the wafer 100 until the thickness of the wafer 100 in the trench regions is in a range of about 1 to 50 micrometers. The patterning is done at the scribe lane region SR and the connection regions R2. The patterning to form the trench 105 may be performed by using a physical method such as a sawing process. In other words, a sawing process may be used to partially saw through the wafer 100, thereby forming the trench 105. In this method, the depth of the saw blade in the wafer 100 during the sawing process will determine the depth of the trench 105 and the thickness of the wafer 100 remaining in the trench regions. Commonly used patterning methods comprising photolithography and etch processes may also be used.
Referring to FIG. 2A, FIG. 5A and FIG. 5B, the back side of the wafer 100 with the trench 105 is polished (S40). The thickness of the wafer 100 decreases so that thickness of the resulting structure comprising the redistribution structure 130 becomes t2 which is smaller than the initial thickness t1. According to the present invention, the resulting thickness t2 may be between approximately tens of micrometers and millimeters.
According to an exemplary embodiment of the present invention, in order to prevent the trench 105 from changing its shape, the back side-polishing process may further include forming a sacrificial layer (not illustrated) filling the trench 105. The sacrificial layer may be made of material having etch selectivity to the wafer 100. Also, the back-side polishing process may include forming a supporting layer (not illustrated) on the wafer 100. This is done in order to prevent damage to the redistribution structure 130 and the semiconductor chip due to mechanical force during the back side-polishing process. The supporting layer may be made of material which is removable by exposing the material to heat or ultraviolet radiation. Also, the supporting layer may be made of material having essentially the same thermal expansion coefficient as a wafer with semiconductor chips.
Referring to FIG. 2A, FIG. 6A and FIG. 6B, a via hole 106 penetrating the wafer 100 is formed on the bottom surface of the trench 105 (S50). The via hole 106 is formed in the connection region R2 (in other words, at the edge of the semiconductor chip). Also, the via hole 106 is formed to expose a bottom surface of the redistribution structure 130 (more specifically, the connecting pad).
The process of forming the via hole 106 may include patterning the wafer 100. The via hole 106 may be formed under the connecting pad by using a laser drilling technique. According to another embodiment of the present invention, the via hole 106 may be formed by using a conventional patterning method including photolithography and etch processes. In this case, the etch process may be performed by using an etch recipe having etch selectivity towards the connecting pad (i.e. the redistribution structure 130). In other words, the redistribution structure 130 is made of a metallic material, the wafer 100 is made of silicon, and an insulation layer such as silicon oxide and silicon nitride (a part of the semiconductor chip) is disposed between the wafer 100 and the redistribution structure 130. Therefore, an etch recipe having etch selectivity towards the metallic material is used to perform the etch process of forming the via hole 106. This etch process of forming the via hole 106 includes etching the silicon, the silicon oxide and the silicon nitride using the etch recipe.
According to another exemplary embodiment of the invention, the wafer 100 is patterned by using the laser drilling technique. Therefore, forming a preliminary via hole under the connecting pad and completing the via hole by extending the preliminary via hole may be included. In order to extend the preliminary via hole, a method of etching the backside of the wafer may be utilized.
According to an exemplary embodiment of the invention, as described above, the redistribution structure 130 may be formed by electroplating using a seed layer. In such case, the via hole 106 is formed to expose the bottom surface of the seed layer.
Referring to FIG. 2A, FIG. 7A and FIG. 7B, a connecting device 150 is formed to be connected to the redistribution structure 130 through the via hole 106 (S60). The connecting device 150 includes a connecting plug 152 filling the via hole 106 and a bump 155 disposed on a bottom portion of the connecting plug 152. As a result, the connecting device 150 is disposed at the connection region R2 as shown in FIG. 7A.
Forming the connecting device 150 is performed by using one of electroplating, solder jet, screen printing or C4NP (Controlled Collapse Chip Connection New Process). For example, the connecting plug 152 may be formed using electroplating which uses the redistribution structure 130 (especially, the seed layer) as a seed electrode. Also, the bump 155 may be formed using one or more of a solder jet process, a screen printing process and C4NP.
In order to improve adhesion between the connecting device 150 and the redistribution structure 130, a UBM layer (not shown) covering a bottom surface of the via hole 106 may be further formed before forming the connecting plug 152. The UBM layer may be made of one or more chosen from nickel (Ni), chrome (Cr), copper (Cu), tungsten titanium (TiW) and gold (Au).
Also, considering that the bump 155 functions as an electrically connecting path to other semiconductor chips, the bump 155 is formed so that it may have a larger thickness t4 than the depth t3 of the trench 105. In other words, the thickness t4 of the bump 155 is larger than the difference in thickness between the central region R1 and the connection region R2.
Referring to FIG. 2A and FIG. 8, a sawing process is performed on the resultant structure where the connecting device 150 is mounted to separate each semiconductor chip (S70). The sawing process includes cutting the wafer 100 along the scribe lane region SR.
According to an embodiment of the present invention, in order to prevent the connecting device 150 (especially, the bump) from being physically damaged, forming a buffer layer filling the trench 105 may be further performed before performing the sawing process. Considering the fact that the function of the bump is to electrically connect components, the buffer layer is formed to expose the bottom region of the bump 155.
Referring to FIG. 9, the redistribution structure 130 and the connecting device 150 are disposed on the separated semiconductor chip. The semiconductor chip constitutes a package unit 400, several of which construct a wafer level package of the invention. In some embodiments of the invention, the package units 400 may be connected to each other through the connecting pad (portion of redistribution structure 130 exposed by the via hole 106 and the opening 145) and the connecting device 150. While being connected, the package units 400 are stacked sequentially on an interconnection substrate 200 having a connection terminal 210. More specifically, a bump 155 of one package unit 400 is connected directly to the top surface of the connecting pad of another package unit 400 or on a connection terminal 210 of the interconnection substrate 200. The interconnection substrate 200 may have an external bump 240 connected to an external electronic device and an interconnection 230 and a pad 220 connecting the connection terminal 210 and the external bump 240.
According to this invention, a protection layer 160 may be interposed between the package units 400, in order to prevent the package units 400 from sticking to each other and to prevent physical damage to the bump 155. In an embodiment of the invention, the above-mentioned buffer layer may be utilized as the protection layer 160. The protection layer 160 may be formed by injecting insulative material such as epoxy, in between the package units 400.
FIG. 2B illustrates a process flow chart of a method of manufacturing a wafer level package according to another embodiment of the present invention.
Referring to FIG. 2B, according to this embodiment, the trench 105 and the via hole 106 are formed after the backside polishing process (S40) is performed. As a result, this embodiment is similar to the exemplary embodiment formerly described referring to FIG. 2A, except for this difference in the process order.
In the case where the backside of the wafer 100 is polished before forming the trench 105, it is possible to prevent the above described physical damage to the trench 105 caused by the backside polishing process. Also, the thickness of the wafer 100 is decreased as a result of this backside polishing process before the trench 105 is formed. Thus, it is possible to decrease the thickness to be etched during the trench forming process. As is well-known in the art, increases in etch thickness causes more process error in the etch process. Consequently, following the process order of this embodiment enables control of the wafer thickness at the trench 105 and the depth of the via hole 106 more accurately.
FIG. 10 illustrates a perspective view of a wafer level package of the present invention.
Referring to FIG. 9 and FIG. 10, the wafer level package of this invention includes a plurality of package units 400 stacked sequentially. The package units 400 may include a semiconductor substrate 100 where semiconductor chips are built and a connecting terminal or connecting device 150 electrically connected to the semiconductor chip. These stacked package units 400 are adhered to the interconnection substrate 200 having the connection terminal 210.
More specifically, the semiconductor chip may include an internal circuit formed at the semiconductor substrate 100, a redistribution structure 130, and an input/output pad 110 connecting to the redistribution structure 130. Here, the semiconductor substrate 100 may be divided into a central region R1 where the internal circuits of the semiconductor chip are disposed and a connection region R2 disposed at the exterior of the central region R1. According to this invention, the connection region R2 has a smaller thickness than the central region R1. Accordingly, in the connection region R2, as shown in FIG. 9, a trench 105 defined by a sidewall of the central region R1 is formed.
The connecting device 150 is formed to penetrate the semiconductor substrate 100 at the connection region R2. In order to do this, the connecting device 150 includes a connecting plug 152 filling the via hole 106 penetrating the semiconductor substrate 100 and a bump 155 formed within the trench 105 while being connected to the connecting plug 152. According to some embodiments of the present invention, the height of the bump 155 may be larger than the depth (i.e. the difference in thickness between the central region R1 and the connection region R2) of the trench 105.
According to an exemplary embodiment, the connecting device 150 is electrically connected to the input/output pad 110 through a redistribution structure 130 which is disposed on the semiconductor substrate 100. The redistribution structure 130 includes a connecting pad which is disposed in the connection region R2 to be connected to the connecting device 150. A UBM layer (not shown) may be interposed between the connecting pad and the connecting plug 152. Also, as shown in FIG. 9, a protection layer 160 surrounding the bump 155 may be further interposed between the package units 400.
According to an exemplary embodiment of the present invention, a trench is formed along a scribe lane region. Then, a connecting terminal penetrating the bottom surface of the trench is formed. Therefore, stress due to an overly protruded connecting terminal and its resulting decrease in connection reliability may be minimized. Also, as the connecting terminal is formed in the trench, it is possible to decrease the thickness of the entire package. Further, since the trench is formed before the via hole, the depth of the via hole can be reduced, thereby reducing the fabrication costs of the wafer level package of the present invention compared to conventional methods.
Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7704796Jun 4, 2008Apr 27, 2010Stats Chippac, Ltd.Semiconductor device and method of forming recessed conductive vias in saw streetsUS7847382Mar 26, 2009Dec 7, 2010Stats Chippac Ltd.Integrated circuit packaging system with package stacking and method of manufacture thereofUS7952176Dec 9, 2008May 31, 2011Stats Chippac Ltd.Integrated circuit packaging system and method of manufacture thereofUS7986045 *Aug 20, 2008Jul 26, 2011Honda Motor Co., Ltd.Semiconductor device having an increased area of one of the opposing electrode parts for preventing generation of unconnected positions the electrodes on the bonded wafersUS8193615 *Jul 31, 2008Jun 5, 2012DigitalOptics Corporation Europe LimitedSemiconductor packaging process using through silicon viasUS8334169Apr 27, 2011Dec 18, 2012Stats Chippac Ltd.Integrated circuit packaging system and method of manufacture thereofUS8406004Dec 9, 2008Mar 26, 2013Stats Chippac Ltd.Integrated circuit packaging system and method of manufacture thereofUS8421201 *Jun 22, 2009Apr 16, 2013Stats Chippac Ltd.Integrated circuit packaging system with underfill and methods of manufacture thereofUS8432045Dec 9, 2010Apr 30, 2013Tessera, Inc.Conductive pads defined by embedded tracesUS8685793Sep 16, 2010Apr 1, 2014Tessera, Inc.Chip assembly having via interconnects joined by platingUS8686565Sep 16, 2010Apr 1, 2014Tessera, Inc.Stacked chip assembly having vertical viasUS8772137 *Dec 18, 2013Jul 8, 2014Taiwan Semiconductor Manufacturing Co., Ltd.Semiconductor wafer with assisting dicing structure and dicing method thereofUS8772908Aug 20, 2012Jul 8, 2014Tessera, Inc.Conductive pads defined by embedded tracesUS8835223Jan 23, 2014Sep 16, 2014Tessera, Inc.Chip assembly having via interconnects joined by platingUS20120018893 *Jul 23, 2010Jan 26, 2012Tessera Research LlcMethods of forming semiconductor elements using micro-abrasive particle streamWO2010091245A2 *Feb 5, 2010Aug 12, 2010Qualcomn IncorporatedScribe-line through silicon vias* Cited by examinerClassifications U.S. Classification438/109International ClassificationH01L21/00Cooperative ClassificationH01L29/0657, H01L25/0657, H01L2924/01024, H01L25/50, H01L2924/01079, H01L2924/01006, H01L2924/01047, H01L2924/01038, H01L21/76898, H01L2924/01093, H01L2225/06586, H01L2924/01033, H01L2924/01029, H01L2225/06555, H01L2924/01074, H01L2225/06541, H01L2225/06513, H01L2224/0401, H01L2224/06181, H01L2224/13025, H01L2224/94, H01L2224/05548, H01L2224/05567, H01L2224/0557European ClassificationH01L25/50, H01L24/19, H01L25/10J, H01L21/768TLegal EventsDateCodeEventDescriptionMay 22, 2007ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHUNG, HYUN-SOO;LEE, IN-YOUNG;HWANG, SON-KWAN;AND OTHERS;REEL/FRAME:019329/0389Effective date: 20070517RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services