Source: https://patents.google.com/patent/US7050353B2/en
Timestamp: 2019-12-16 08:05:24
Document Index: 363528561

Matched Legal Cases: ['art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12', 'art 12']

US7050353B2 - Semiconductor memory having burst transfer function - Google Patents
Semiconductor memory having burst transfer function Download PDF
US7050353B2
US7050353B2 US10/994,630 US99463004A US7050353B2 US 7050353 B2 US7050353 B2 US 7050353B2 US 99463004 A US99463004 A US 99463004A US 7050353 B2 US7050353 B2 US 7050353B2
US10/994,630
US20050073903A1 (en
Yoshiaki Okuyama
2002-04-15 Priority to JP2002-111877 priority Critical
2002-04-15 Priority to JP2002111877 priority
2002-05-30 Priority to JP2002-156832 priority
2002-05-30 Priority to JP2002156832A priority patent/JP4078119B2/en
2002-11-21 Priority to US10/300,800 priority patent/US6847570B2/en
2004-11-23 Priority to US10/994,630 priority patent/US7050353B2/en
2005-04-07 Publication of US20050073903A1 publication Critical patent/US20050073903A1/en
2006-05-23 Publication of US7050353B2 publication Critical patent/US7050353B2/en
This is a Division of application Ser. No. 10/300,800 filed Nov. 21, 2002 now U.S. Pat. No. 6,847,570.
The arbiter 12 has a refresh judging part 12 a, a refresh holding part 12 b, a command generating part 12 c, and an access holding part 12 d.
The refresh judging part 12 a, which has an RS flip-flop, operates during a low level of the active signal ACTZ, and judges which is the first to arrive, the refresh request signal REFZ or an access signal ACSZ. The access signal ACSZ is a signal indicative of the OR logic (negative logic) of the /CE and /ADS signals. That is, when the /CE or /ADS signal changes to a low level, the supply of an access command is detected and the ACSZ signal is outputted. The refresh judging part 12 a, when judging that the REFZ signal is the first to arrive, causes a refresh enable signal REFENZ to change to a high level. The refresh judging part 12 a, when judging that the ACSZ signal is the first to arrive, holds the refresh enable signal REFENZ at a low level.
The refresh holding part 12 b holds the refresh request signal REFZ when the refresh enable signal REFENZ exhibits the low level or when the burst signal BSTZ exhibits a high level. The held refresh request signal REFZ is outputted as the refresh starting signal REFS1 and as a refresh starting signal REFS2 in synchronization with a falling edge of the burst signal BSTZ. The refresh holding part 12 b outputs the refresh starting signals REFS1 and REFS2 in response to the refresh request signal REFZ when the refresh enable signal REFENZ exhibits the high level and further when the burst signal BSTZ exhibits the low level. The refresh holding part 12 b stops outputting the refresh starting signal REFS in synchronization with a refresh stopping signal RSTPZ outputted at the completion of the refresh operation.
Firstly, an address signal ADD (A0) and /ADS, /CE and /OE signals are supplied in synchronization with the rising edge of the zeroth CLK signal (FIG. 3( a)). That is, a read command is supplied. The arbiter 12 outputs an access signal ACSZ in response to the /ADS and /CE signals (FIG. 3( b)).
After the access signal ACSZ is outputted, a refresh request signal REFZ is outputted (FIG. 3( c)). The refresh judging part 12 a judges that the ACSZ signal is the first to arrive, and holds the refresh enable signal REFENZ at a low level. The refresh holding part 12 b receives the low level of the REFENZ signal, and holds the refresh request signal REFZ until a starting of the refresh operation, as shown by dashed lines in the figure (FIG. 3( d)).
The access holding part 12 d receives the ACSZ signal and outputs the access starting signal ACSS. The command generating part 12 c receives the ACSS signal and outputs an active signal ACTZ (FIG. 3( e)). The ACTZ signal's turning to the high level causes the memory cell array 28 to shift from a standby state STBY to an active state ACTV.
The burst control circuit 16 shown in FIG. 1 receives an access command and outputs a burst signal BSTZ (FIG. 3( f)) and a wait signal WAIT (FIG. 3( g)). The system incorporating the pseudo SRAM, receiving the wait signal WAIT to detect that no read data are outputted from the pseudo SRAM, may access another device for example. Therefore, the utilization ratio of the system bus is improved.
Thereafter, the burst read operation is started, and the first read data D0 and D1 are outputted to the data buses DB (FIG. 3( h)). Thereafter, the read operation of the memory cell array 28 is completed, and the read data D2 and D3 are outputted. The burst control circuit 16 causes the burst signal BSTZ to change to a low level (FIG. 3( i)).
The memory cell array 28 is deactivated after the read data D2 and D3 are outputted. The refresh holding part 12 b of the arbiter 12 outputs refresh starting signals REFS1 and REFS2 for starting the refresh operation in synchronization with the falling edge of the burst signal BSTZ (FIG. 3( j)). Thus, the refresh starting signals REFS1 and REFS2 are outputted, after the operation of the memory cell array 28, without waiting for the completion of the outputting of the read data D2 and D3 from the burst transfer register 32. Starting, before the completion of the outputting of the read data, the refresh operation that does not use the data buses DB can improve the utilization ratio of the data buses DB. More specifically, the next access command can be received with an earlier timing.
The active signal ACTZ changes, in response to the refresh starting signal REFS2, to the high level again, which causes the refresh operation to be executed (FIG. 3( k)). That is, the state of the memory cell array 28 changes to a refresh state REF while the read data D2 and D3 are being transferred to the data input/output terminals DQ.
A refresh stopping signal RSTPZ is outputted in synchronization with a completion of the refresh operation, and the refresh starting signal REFS1 and active signal ACTZ change to their respective low levels (FIG. 3( l), (m)). Then, the state of the memory cell array 28 changes to a standby state STBY. Thereafter, /CE and /OE signals are caused to exhibit their respective high levels, resulting in a completion of the burst read operation (FIG. 3( n)).
Firstly, a refresh request signal REFZ is outputted (FIG. 4( a)). The refresh judging part 12 a judges that the refresh request signal REFZ is the first to arrive, and causes a refresh enable signal REFENZ to change to a high level (FIG. 4( b)). At this moment, since the memory cell array 28 is in a standby state STBY, a burst signal BSTZ has not been outputted. Accordingly, the refresh holding part 12 b receives the REFENZ signal and outputs refresh starting signals REFS1 and REFS2 (FIG. 4( c)).
Thereafter, in synchronization with the rising edge of the zeroth CLK signal, an address signal ADD (A0) and /ADS, /CE and /OE signals are supplied, and an access signal ACSZ changes to a high level (FIG. 4( d)). The command generating part 12 c outputs an active signal ACTZ in response to the refresh starting signal REFS2 (FIG. 4( e)). Then, the refresh operation is executed. A wait signal WAIT changes to a high level during the refresh operation and at the beginning of the active period (FIG. 4( f)). A detailed description of the wait signal WAIT will be made later with reference to FIG. 6.
The access holding part 12 d receives the high level of the ACTZ signal and holds the ACSZ signal (FIG. 4( g)). The access holding part 12 d outputs the ACTZ signal in synchronization with the falling edge of the ACTZ signal corresponding to a completion of the refresh operation (FIG. 4( h)). The ACTZ signal's turning to the high level causes the memory cell array 28 to shift from the refresh state REF directly to an active state ACTV without undergoing a standby state STBY. Accordingly, the burst read operation can be started earlier.
Thereafter, similarly to FIG. 3, the burst read operation is executed, and read data D0–D3 are outputted (FIG. 4( i)).
In the figure, the word lines WL corresponding to read data Dn-3, Dn-2, Dn-1 and Dn are different from the word lines WL corresponding to the read data D0, D1, D2 and D3. That is, the selections of the word lines WL are switched during the eighth clock period. A refresh operation is executed when the word lines WL are switched. The operations designated by reference labels (a) through (m) in FIG. 5 are the same as the operations designated by the same reference labels in FIG. 3, and hence their detailed descriptions are omitted.
During the period when read data cannot be outputted due to the switching of the word lines WL, a wait signal WAIT is outputted (FIG. 5( n)).
In order to switch the word lines WL, the arbiter 12 and burst control circuit 16 shown in FIG. 1 reactivate the once inactivated burst signal BSTZ and active signal ACTZ (FIG. 5( o)). Then, the burst read operation of the memory cells MC connected to the word lines WL selected anew is carried out.
Firstly, an access command (in this example, a read command because of the low level of the /OE signal) is supplied, and the burst control circuit 16 shown in FIG. 1 causes the burst signal BSTZ to change to a high level (FIG. 7( a)). The high level of the burst signal BSTZ cancels the resetting of the shift register 16 a. The shift register 16 a causes, in synchronization with external clock signals CLK, count signals BCNT1–4 to sequentially change to high levels (FIG. 7( b)).
The flip-flop circuit 16 c is set in synchronization with the rising edge of the count signal BCNT1, and the wait signal WAIT1 changes to a high level (FIG. 7( c)).
An enable signal BCNTEN changes to a high level in synchronization with the rising edge of the count signal BCNT3 (FIG. 7( d)). The flip-flop circuit 16 c is reset by the high level of the enable signal BCNTEN, and the wait signal WAIT1 changes to a low level (FIG. 7( e)).
The high level of the enable signal BCNTEN causes the burst clock signals BCLK to be outputted in synchronization with external clock signals CLK (FIG. 7( f)). The burst clock signal BCLK (strobe signal) is outputted a number of times that corresponds to the burst length BL set in the mode register. Then, read data are outputted to the data input/output terminals DQ in synchronization with the burst clock signals BCLK.
The burst control circuit 16 causes, in synchronization with the sixth external clock signal CLK, the burst signal BSTZ to change to a low level (FIG. 7( g)). That is, the burst signal BSTZ is outputted in accordance with the period during which the burst clock signals BCLK are outputted. The low level of the burst signal BSTZ resets the shift register 16 a, causing the count signals BCNT1–4 to change to low levels (FIG. 7( h)).
The low level of the count signal BCNT3 causes the enable signal BCNTEN to change to a low level, which causes the outputting of the burst clock signals BCLK to be stopped (FIG. 7( i)). Consequently, the outputting of read data is started in accordance with the latency LTC set in the mode register, and the read data are outputted a number of times that corresponds to the burst length BL (FIG. 7( j)).
Firstly, an address signal ADD (An) and /ADS, /CE and /OE signals are supplied in synchronization with the rising edge of the zeroth CLK signal (FIG. 9( a)). The timing control circuit 22 shown in FIG. 1 outputs an address latch signal ELAT for latching the address signal ADD supplied from the exterior (FIG. 9( b)). The address latch 24 latches the address signal ADD (An) in synchronization with the address latch signal ELAT (FIG. 9( c)).
Next, the timing control circuit 22 outputs a read amplifier enable signal RAEN (FIG. 9( d)). The read amplifier enable signal RAEN activates the read/write amplifier 30, causing parallel read data D0 and D1 to be outputted to the data buses DB0 and DB1 (FIG. 9( e)). The parallel read data D0 and D1 are converted into serial data by the data registers of the burst transfer register 32 in synchronization with the burst clock signals BCLK, and then sequentially outputted to the common data bus CDB. Then, the read data D0 and D1 are outputted from the data input/output terminals DQ in synchronization with clock signals CLK (FIG. 9( f)).
Next, the timing control circuit 22 outputs an address latch signal ILAT (FIG. 9( g)). The address latch 24 latches the internal address signal IADD (An+1) in synchronization with the address latch signal ILAT (FIG. 9( h)). Then, in a similar manner to the above, read data D2 and D3 corresponding to the internal address signal IADD are outputted (FIG. 9( i)).
Thereafter, the timing control circuit 22 sequentially outputs address latch signals ILAT (FIG. 9( j)), and read data are sequentially outputted in accordance with the internal address signal IADD generated by the burst address counter 20 (FIG. 9( k)).
Firstly, an address signal ADD (An) and /ADS, /CE and /WE signals are supplied in synchronization with the rising edge of the zeroth CLK signal (FIG. 10( a)). The timing control circuit 22 shown in FIG. 1 outputs an address latch signal ELAT for latching the address signal ADD supplied from the exterior (FIG. 10( b)). The address latch 24 latches the address signal ADD (An) in synchronization with the address latch signal ELAT (FIG. 10( c)).
In the write operation, write data are sequentially supplied in synchronization with the respective rising edges of CLK signals in such a manner that this sequential supply of write data starts in synchronization with the rising edge of the CLK signal at which the access command is received (FIG. 10( d)). The data registers of the burst transfer register 32 sequentially hold the write data from the common data bus CDB in synchronization with the burst clock signals BCLK, and transfers the held data to the data buses DB0 and DB1. That is, the serial write data on the common data bus CDB are converted into parallel write data (FIG. 10( e)).
The read/write amplifier 30 writes, in synchronization with a write amplifier enable signal WAEN, the write data supplied from the data buses DB0 and DB1 into the memory cell array 28 (FIG. 10( f)).
Thereafter, similarly to FIG. 9, an internal address signal IADD is latched in synchronization with an address latch signal ILAT (FIG. 10( g)). Then, write data D3, D4, D5 and others are sequentially written into the memory cells MC corresponding to the internal address signal IADD (FIG. 10( h)).
The mode setting control circuit 18 receives the signals of predetermined logic values at the address and command terminals four times successively, and then receives, as the set signals for setting the read latency LTC and burst length BL, the signals CODE5 and CODE 6 supplied to the address terminals. This eliminates the necessity to provide any dedicated terminals for setting the operation mode.
In FIG. 1S, a refresh request occurs immediately after an access command is received. That is, a refresh operation is executed after a read operation. In this example, the read latency LTC is set to “4”.
Firstly, a read command is supplied in synchronization with the rising edge of the zeroth CLK signal, and the arbiter 12 shown in FIG. 2 outputs an access signal ACSZ (FIG. 15 (a)). The refresh judging part 12 a of the arbiter 12 receives a refresh request signal REFZ after the read command is supplied. Accordingly, a refresh enable signal REFENZ is held at a low level (FIG. 15( b)). The command generating part 12 c outputs an active signal ACTZ in response to the access signal ACSZ (FIG. 15( c)). The active signal ACTZ's tuning to a high level causes the memory cell array 28 to shift from a standby state STBY to an active state ACTV.
Next, a burst signal BSTZ changes to a high level, and a wait signal WAIT exhibits a high level for a predetermined time. The timing control circuit 38 outputs read amplifier enable signals RAEN in synchronization with the respective rising edges of the third through sixth clock signals CLK (FIG. 15( d)). The burst control circuit 16 outputs burst clock signals BCLK in synchronization with the respective rising edges of the third through sixth clock signals CLK (FIG. 15( e)). Then, the read operation is executed, and read data Dn-3, Dn-2, Dn-1 and Dn are sequentially outputted to the data bus DB (FIG. 15( f)).
In the present embodiment, the read/write amplifier 40 outputs the read data Dn-3, Dn-2, Dn-1 and Dn in accordance with the respective clock signals CLK. Accordingly, the memory cell array 28 must operate until the fourth read data Dn is transferred to the read/write amplifier 40. Therefore, the length of the period of the active state ACTV is one clock cycle longer than in the first embodiment (FIG. 5) (FIG. 15( g)).
After a completion of the read operation, the refresh operation is executed (FIG. 15 (h)). The refresh operation is executed one clock cycle later than in the first embodiment (FIG. 5). Accordingly, the next read operation in the full burst operation also starts one clock cycle later. Therefore, the data transfer rate is lower than in the first embodiment (FIG. 5).
Firstly, the clock generating circuit 46 a shown in FIG. 17 is activated, by the low level of a chip enable signal /CE, to start the outputting of internal clock signals RCLK1 (FIG. 20( a)). The low level of the chip enable signal /CE and the low level of an output enable signal /OE cause a read control signal RDZ to be outputted (FIG. 20( b)). The shift register 46 b causes, in synchronization with the second clock signal CLK, a count signal BCNT3 to change to a high level (FIG. 20( c)).
The combinational circuit 46 c is activated, by the high levels of the read control signal RDZ and count signal BCNT3, to output clock signals CLK as read burst clock signals RBCLK (FIG. 20( d)). That is, the outputting of the read burst clock signals RBCLK is started in synchronization with the third clock signal CLK.
Thereafter, similarly to the first embodiment, read data are sequentially outputted in synchronization with the read burst clock signals RBCLK. The system incorporating the pseudo SRAM receives the first read data in synchronization with the rising edge of the fourth clock signal CLK (FIG. 20( e)).
The burst address counter 20 shown in FIG. 16 counts up by receiving, via the timing control circuit 22, a control signal outputted from the burst control circuit 46 in synchronization with the starting of the outputting of the read burst clock signals RBCLK, and then outputs the count value as an internal address signal IADD (FIG. 20( f)).
Firstly, the clock generating circuit 46 d shown in FIG. 18 is activated, by a low level of a chip enable signal /CE, to start the outputting of internal clock signals WCLK1 (FIG. 21 (a)). The low level of the chip enable signal /CE and the low level of a write enable signal /WE cause a write control signal WRZ to be outputted (FIG. 21( b)). The shift register 46 e causes, in synchronization with the third clock signal CLK, a count signal BCNT4 to change to a high level (FIG. 21( c)).
The combinational circuit 46 f is activated, by the high levels of the write control signal WRZ and count signal BCNT4, to output clock signals CLK as write burst clock signals WBCLK (FIG. 21( d)). That is, the outputting of the write burst clock signals WBCLK is started in synchronization with the fourth clock signal CLK.
The system incorporating the pseudo SRAM outputs the first write data to the pseudo SRAM in synchronization with, for example, the falling edge of the third clock signal CLK (FIG. 21( e)). The pseudo SRAM receives this write data in synchronization with the rising edge of the fourth clock signal CLK, and transfers the write data to the common data bus CDB (FIG. 21( f)). The write data on the common data bus CDB are transferred to a data bus DB (DB0 or DB1) in synchronization with write burst clock signals WBCLK.
The burst address counter 20 shown in FIG. 16 counts up by receiving, via the timing control circuit 22, a control signal outputted from the burst control circuit 46 in synchronization with the starting of the outputting of the write burst clock signals WBCLK, and then generates the count value as an internal address signal IADD (FIG. 21( g)). Thereafter, the sequentially supplied write data are transferred to the data bus DB in synchronization with the write burst clock signals WBCLK, and then written into the memory cells MC.
The mode setting control circuit 54 has a mode register 54 a and switch circuits' 54 b connected to the respective eight-bit outputs A0–A7 of the mode register 54 a. The mode register 54 a, which is the same as the mode register of the third embodiment, can set the burst length BL, read latency RLTC and write latency WLTC according to the method previously described with reference to FIG. 19.
The burst control circuit 52 starts the outputting of internal clock signals RCLK1 in response to the activation of an output enable signal /OE during the read operation (FIG. 26 (a)). The basic timings of the following operations during the burst read operation are the same as in the third embodiment (FIG. 20), and hence their descriptions are omitted.
The burst control circuit 52 starts the outputting of internal clock signals WCLK1 in response to the activation of a write enable signal /WE during the write operation (FIG. 27 (a)). The basic timings of the following operations during the burst write operation are the same as in the third embodiment (FIG. 21), and hence their descriptions are omitted.
The mode setting control circuit 56 has a mode register 56 a and mode setting circuits 56 b that receive the respective eight-bit outputs A0–A7 of the mode register 56 a. The mode register 56 a, which is the same as the mode register of the third embodiment, can set the burst length BL, read latency RLTC and write latency WLTC according to the method previously described with reference to FIG. 19.
The foregoing first and second embodiments are described as examples wherein the latency LTC during the burst read operation is set to ‘4’. The present invention, however, is not limited to such embodiments. The latency LTC may be set to an optimum value in accordance with the clock cycle.
The foregoing third, fourth and fifth embodiments are described as examples wherein the read and write latencies RLTC and WLTC are set independently of each other. The present invention, however, is not limited to such embodiments. For example, as shown in FIG. 30, the bits A4–A2 of the mode register may be common to the read and write latencies RLTC and WLTC. Instead, the write latency WLTC may be set to be always smaller than the read latency RLTC by “1”. In such a case, the number of the bits of the mode register can be reduced.
a first burst control circuit for outputting a strobe signal having a predetermined number of pulses, the output corresponding to an access command for successively burst accessing said memory cell array; and
a data input/output circuit for successively inputting/outputting data to be transferred to/from said memory cell array in synchronization with each of said pulses of the strobe signal, wherein
said first burst control circuit comprises:
a level detecting circuit for detecting that one of command signals supplied as said access command turns to its active level; and
an output control circuit for starting outputting said strobe signal after measuring a predetermined time from the detection of said level detecting circuit.
during a read operation, said first burst control circuit starts outputting said strobe signals said predetermined time after detection of an active level of a chip enable signal that is one of said command signals, said strobe signal being a signal for outputting data transferred from said memory cell array.
during a read operation, said first burst control circuit starts outputting said strobe signals said predetermined time after detection of an active level of an output enable signal that is one of said command signals, said strobe signal being a signal for outputting data transferred from said memory cell array.
during a write operation, said first burst control circuit starts outputting said strobe signals said predetermined time after a detection of an active level of a chip enable signal that is one of said command signals, said strobe signal being a signal for inputting data to be transferred to said memory cell array.
during a write operation, said first burst control circuit starts outputting said strobe signals said predetermined time after a detection of an active level of a write enable signal that is one of said command signals, said strobe signal being a signal for inputting data to be transferred to said memory cell array.
said predetermined time in read operation and in write operation are different from each other.
said predetermined time in read operation and in write operation are equal to each other.
an address counter for receiving an external address supplied corresponding to said access command and for sequentially generating internal addresses that follow said external address, wherein
said address counter counts up to generate said internal addresses, in response to start of outputting said strobe signal.
a mode register for setting said predetermined time from exterior, and wherein
said first burst control circuit measures said predetermined time in accordance with a value set in said mode register.
10. The semiconductor memory according to claim 1, further comprising
a switch structured by a conductive pattern which is formed on the semiconductor substrate in accordance with a pattern shape of a photomask used in a fabrication process of the semiconductor memory, and wherein
said first burst control circuit measures said predetermined time in accordance with a voltage value of a destination of said conductive pattern.
a fuse in which information indicative of said predetermined time is programmed, and wherein
said first burst control circuit measures said predetermined time in accordance with the information programmed in said fuse.
US10/994,630 2002-04-15 2004-11-23 Semiconductor memory having burst transfer function Active US7050353B2 (en)
JP2002-111877 2002-04-15
JP2002111877 2002-04-15
JP2002-156832 2002-05-30
JP2002156832A JP4078119B2 (en) 2002-04-15 2002-05-30 Semiconductor memory
US10/300,800 US6847570B2 (en) 2002-04-15 2002-11-21 Semiconductor memory having burst transfer function and internal refresh function
US10/994,630 US7050353B2 (en) 2002-04-15 2004-11-23 Semiconductor memory having burst transfer function
US10/300,800 Division US6847570B2 (en) 2002-04-15 2002-11-21 Semiconductor memory having burst transfer function and internal refresh function
US20050073903A1 US20050073903A1 (en) 2005-04-07
US7050353B2 true US7050353B2 (en) 2006-05-23
ID=28677636
US10/300,800 Active US6847570B2 (en) 2002-04-15 2002-11-21 Semiconductor memory having burst transfer function and internal refresh function
US10/994,630 Active US7050353B2 (en) 2002-04-15 2004-11-23 Semiconductor memory having burst transfer function
US (2) US6847570B2 (en)
EP (2) EP1355318B1 (en)
JP (1) JP4078119B2 (en)
KR (2) KR100888833B1 (en)
CN (1) CN1225697C (en)
DE (2) DE60213560T2 (en)
TW (1) TW580704B (en)
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2002-05-30 JP JP2002156832A patent/JP4078119B2/en active Active
2002-11-18 EP EP20020025813 patent/EP1355318B1/en active Active
2002-11-18 EP EP05018142A patent/EP1612803B1/en active Active
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2002-11-21 US US10/300,800 patent/US6847570B2/en active Active
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US20030198098A1 (en) 2003-10-23
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JP4524759B2 (en) 2010-08-18 Detection circuit for mixed asynchronous and synchronous memory operations
KR20020095109A (en) 2002-12-20 Semiconductor memory device with non-volatile memory and random access memory