Source: http://www.google.com/patents/US7555631?ie=ISO-8859-1&dq=%22peter+l+basel%22+%22lsi+logic%22
Timestamp: 2015-05-25 11:25:43
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Matched Legal Cases: ['Application No. 01', 'Application No. 01', 'Application No. 02', 'Application No. 02', 'Application No. 63', 'Application No. 01', 'Application No. 55', 'Application No. 55', 'Application No. 59', 'Application No. 59', 'Application No. 61']

Patent US7555631 - RISC microprocessor architecture implementing multiple typed register sets - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0])...http://www.google.com/patents/US7555631?utm_source=gb-gplus-sharePatent US7555631 - RISC microprocessor architecture implementing multiple typed register setsAdvanced Patent SearchPublication numberUS7555631 B2Publication typeGrantApplication numberUS 10/060,086Publication dateJun 30, 2009Filing dateJan 31, 2002Priority dateJul 8, 1991Fee statusLapsedAlso published asDE69230057D1, DE69230057T2, EP0547216A1, EP0547216B1, EP0911724A2, EP0911724A3, US5493687, US5560035, US5682546, US5838986, US6044449, US6249856, US7685402, US7941636, US20010034823, US20030115440, US20070113047, US20100106942, WO1993001543A1Publication number060086, 10060086, US 7555631 B2, US 7555631B2, US-B2-7555631, US7555631 B2, US7555631B2InventorsSanjiv Garg, Derek J. Lentz, Le Trong Nguyen, Sho Long ChenOriginal AssigneeSanjiv Garg, Lentz Derek J, Le Trong Nguyen, Sho Long ChenExport CitationBiBTeX, EndNote, RefManPatent Citations (60), Non-Patent Citations (99), Referenced by (1), Classifications (33), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetRISC microprocessor architecture implementing multiple typed register sets
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4128880Jun 30, 1976Dec 5, 1978Cray Research, Inc.Computer vector register processingUS4212076Sep 24, 1976Jul 8, 1980Giddings & Lewis, Inc.Digital computer structure providing arithmetic and boolean logic operations, the latter controlling the formerUS4626989Aug 5, 1983Dec 2, 1986Hitachi, Ltd.Data processor with parallel-operating operation unitsUS4675806Mar 2, 1983Jun 23, 1987Fujitsu LimitedData processing unit utilizing data flow ordered executionUS4722049Oct 11, 1985Jan 26, 1988Unisys CorporationApparatus for out-of-order program executionUS4807115Oct 14, 1987Feb 21, 1989Cornell Research Foundation, Inc.Instruction issuing mechanism for processors with multiple functional unitsUS4926323Mar 3, 1988May 15, 1990Advanced Micro Devices, Inc.Streamlined instruction processorUS4980817Aug 31, 1987Dec 25, 1990Digital EquipmentVector register system for executing plural read/write commands concurrently and independently routing data to plural read/write portsUS5093783Aug 2, 1985Mar 3, 1992Nec CorporationMicrocomputer register bank accessingUS5125092Jan 9, 1989Jun 23, 1992International Business Machines CorporationMethod and apparatus for providing multiple condition code fields to to allow pipelined instructions contention free access to separate condition codesUS5133077Jun 5, 1990Jul 21, 1992International Business Machines CorporationData processor having multiple execution units for processing plural classs of instructions in parallelUS5179689Jul 10, 1990Jan 12, 1993Texas Instruments IncorporatedDataprocessing device with instruction cacheUS5201056May 2, 1990Apr 6, 1993Motorola, Inc.RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation outputUS5214786Apr 13, 1987May 25, 1993Hitachi, Ltd.RISC system performing calls and returns without saving or restoring window pointers and delaying saving until multi-register areas are filledUS5226126Feb 21, 1990Jul 6, 1993Nexgen MicrosystemsProcessor having plurality of functional units for orderly retiring outstanding operations based upon its associated tagsUS5230068Feb 26, 1990Jul 20, 1993Nexgen MicrosystemsCache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequenceUS5241636Feb 14, 1990Aug 31, 1993Intel CorporationMethod for parallel instruction execution in a computerUS5249286Nov 24, 1992Sep 28, 1993National Semiconductor CorporationSelectively locking memory locations within a microprocessor's on-chip cacheUS5442757Mar 3, 1993Aug 15, 1995Nexgen, Inc.Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interruptsUS5487156Dec 5, 1990Jan 23, 1996Popescu; ValeriProcessor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetchedUS5493687 *Jul 8, 1991Feb 20, 1996Seiko Epson CorporationRISC microprocessor architecture implementing multiple typed register setsUS5560035 *Jun 5, 1995Sep 24, 1996Seiko Epson CorporationRISC microprocessor architecture implementing multiple typed register setsUS5561776Jun 6, 1995Oct 1, 1996Hyundai Electronics AmericaProcessor architecture supporting multiple speculative branchingUS5592636Jun 6, 1995Jan 7, 1997Hyundai Electronics AmericaProcessor architecture supporting multiple speculative branches and trap handlingUS5617554Dec 23, 1994Apr 1, 1997Intel CorporationPhysical address size selection and page size selection in an address translatorUS5625837Jun 6, 1995Apr 29, 1997Hyundai Electronics AmericaProcessor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition codeUS5627983Jun 6, 1995May 6, 1997Hyundai Electronics AmericaProcessor architecture providing out-of-order executionUS5682546 *Jun 19, 1996Oct 28, 1997Seiko Epson CorporationRISC microprocessor architecture implementing multiple typed register setsUS5708841Sep 17, 1996Jan 13, 1998Hyundai Electronics AmericaProcessor architecture providing speculative, out of order execution of instructionsUS5745375Sep 29, 1995Apr 28, 1998Intel CorporationApparatus and method for controlling power usageUS5768575Mar 13, 1995Jun 16, 1998Advanced Micro Devices, Inc.Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructionsUS5797025Nov 14, 1996Aug 18, 1998Hyundai Electronics America, Inc.Processor architecture supporting speculative, out of order execution of instructions including multiple speculative branchingUS5802605Nov 25, 1996Sep 1, 1998Intel CorporationPhysical address size selection and page size selection in an address translatorUS5819101Jul 21, 1997Oct 6, 1998Intel CorporationMethod for packing a plurality of packed data elements in response to a pack instructionUS5832293Aug 15, 1997Nov 3, 1998Hyundai Electronics America, Inc.Processor architecture providing speculative, out of order execution of instructions and trap handlingUS5838986 *Sep 25, 1997Nov 17, 1998Seiko Epson CorporationRISC microprocessor architecture implementing multiple typed register setsUS5881275Feb 13, 1997Mar 9, 1999Intel CorporationMethod for unpacking a plurality of packed data into a result packed dataUS6044449 *Nov 10, 1998Mar 28, 2000Seiko Epson CorporationRISC microprocessor architecture implementing multiple typed register setsUS6249856 *Jan 10, 2000Jun 19, 2001Seiko Epson CorporationRISC microprocessor architecture implementing multiple typed register setsUS6385634Aug 31, 1995May 7, 2002Intel CorporationMethod for performing multiply-add operations on packed dataUS6418529Mar 31, 1998Jul 9, 2002Intel CorporationApparatus and method for performing intra-add operationUS20010034823Apr 24, 2001Oct 25, 2001Sanjiv GargRISC microprocessor architecture implementing multiple register setsEP0170284A2Aug 2, 1985Feb 5, 1986Nec CorporationMicrocomputerEP0213843A2Aug 14, 1986Mar 11, 1987Advanced Micro Devices, Inc.Digital processor controlEP0241909A2Apr 14, 1987Oct 21, 1987Hitachi, Ltd.Information processing apparatusEP0454636A1Apr 24, 1991Oct 30, 1991SGS-THOMSON MICROELECTRONICS S.r.l.Method for carrying out a boolean operation between any two bits of any two registersGB2190521A Title not availableJPH0335324A Title not availableJPH01142831A Title not availableJPH01199233A Title not availableJPH02118757A Title not availableJPH02211534A Title not availableJPH02224025A Title not availableJPH02226342A Title not availableJPH05197544A Title not availableJPS5757345A Title not availableJPS6140650A Title not availableJPS60144830A Title not availableJPS62242243A Title not availableJPS63192135A Title not available* Cited by examinerNon-Patent CitationsReference1Acosta, R. D. et al., "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Transactions On Computers, IEEE, vol. C-35, No. 9, Sep. 1986, pp. 815-828.2Adams, R.G. et al., "Utilising low level parallelism in general purpose code: the HARP project," Microprocessing and Microprogramming, Elsevier Science Publishers, B.V., vol. 29, No. 3, Oct. 1990, pp. 137-149.3Agerwala, T. and Cocke, J., A High Performance Reduced Instruction Set Processors, IBM Research Division, Mar. 31, 1987, pp. 1-61.4Aiken, A. and Nicolau, A., "Perfect Pipelining: A New Loop Parallelization Technique*," ESOP '88, 2nd European Symposium on Programming, Springer, ISBN 3-540-19027-9, 1988, pp. 221-235.5Albert, A.J., "User Configurable Local Storage Registers," IBM Technical Disclosure Bulletin, IBM, vol. 18, No. 12, May 1976, pp. 3971-3975.6Baker, T., "Headroom and Legroom in the 80960 Architecture," COMPCON Spring '90: Thirty-Fifth IEEE Computer Society International Conference, IEEE Computer Society, 1990, pp. 299-306.7Birman, M. et al., "Design of a High-Speed Arithmetic Datapath," Proceedings 1988 IEEE International Conference on Computer Design: VLSI in Computers & Processors, IEEE, Oct. 3-5, 1988, pp. 214-216.8Butler, M. and Patt, Y., "An Improved Area-Efficient Register Alias Table for Implementing HPS," University of Michigan, Ann Arbor, Michigan, 24 pages (Jan. 1990).9Butler, M. et al., "Single Instruction Stream Parallelism Is Greater than Two," Proceedings of the 18th Annual International Symposium on Computer Architecture, ACM, pp. 276-286 (May 1991).10Charlesworth, A.E., "An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family," Computer, IEEE, vol. 14, Sep. 1981, pp. 18-27.11Colwell, R.P. et al., "A VLIW Architecture for a Trace Scheduling Compiler," Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, Oct. 1987, pp. 180-192.12Complaint, 7 pages, filed Oct. 11, 2006, in Transmeta Corporation v. Intel Corporation, in the U.S. District Court for the District of Delaware, Case No. 1:06-cv-00633.13Convex Architecture Handbook, Version 1, Convex Computer Corporation, 1984.14Copy of European Search Report from EP Appl. No. 99102406.8, 3 pages, Completed Nov. 24, 1999.15English Language Abstract for JP Patent Publication No. 1-142831, (1 page).16English Language Abstract for JP Patent Publication No. 3-35324, (1 page).17English Language Abstract for JP Patent Publication No. 63-192135, (1 page) Aug. 9, 1988.18English Language Abstract for JP Patent Publication No. No. 1-199233.19English Language Abstract for JP patent Publication No. No. 5-197544 Aug. 6, 1993.20First Amended Complaint, 7 pages, filed Dec. 12, 2006, in Transmeta Corporation v. Intel Corporation, in the U.S. District Court for the District of Delaware, Case No. 1:06-cv-00633.21Foster, C.C. and Riseman, E.M., "Percolation of Code to Enhance Parallel Dispatching and Execution," IEEE Trans. On Computers, IEEE, Dec. 1971, pp. 1411-1415.22G. Myers et al., The 80960 Microprocessor Architecture, John Wiley & Sons, Inc., 1988.23Goodman, J.R. and Hsu, W., "Code Scheduling and Register Allocation in Large Basic Blocks," Proceedings of the 2nd Internatio nal Conference on Supercomputing, ACM Press, 1998, pp. 442-452.24Gross, T.R. and Hennessy, J.L., "Optimizing Delayed Branches," Proceedings of the 5th Annual Workshop on Microprogramming, IEEE, Oct. 5-7, 1982, pp. 114-120.25Groves, R.D. and Oehler, R., "An IBM Second Generation RISC Processor Architecture," COMPCON 90: 35th IEEE Computer Society International Conference, IEEE, Feb. 26, 1990, pp. 166-172.26Hennessy, J.L. and Patterson, D.A., Computer Architecture: A Quantitative Approach, Morgan Kaufman Publishers, pp. xi-xv, 257-278, 290-314 and 449 (1990).27Horst, R.W. et al., "Multiple Instruction Issue in the NonStop Cyclone Processor," Proceedings of the 17th Annual International Symposium on Computer Architecture, ACM Press, 1990, pp. 216-226.28Hunter, C., Series 32000 Programmer's Reference Manual, Prentice-Hall Inc., Englewood Cliffs, NJ, 1987, pp. 2-4, 2-21, 2-23, 6-14 and 6-126.29Hwang, K. and Briggs, F.A., Computer Architecture and Parallel Processing, McGraw-Hill, 1984, pp. 264-280.30Hwu, W. and Patt, Y., "Design Choices for the HPSm Microprocessor Chip," Proceedings of the Twentieth Annual Hawaii International Conference on System Sciences, pp. 330-336 (1987).31Hwu, W. and Patt, Y., "HPSm2: A Refined Single-Ship Microengine," HICSS '88, IEEE, pp. 30-40 (1988).32Hwu, W. and Patt, Y.N., "HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality," Proceedings from ISCA-13, IEEE, Tokyo, Japan, Jun. 2-5, 1986, pp. 297-306.33Hwu, W. W. and Patt, Y.N., "Checkpoint Repair for High-Performance Out-of-Order Execution Machines," IEEE Transactions On Computers, IEEE, vol. C-36, No. 12, Dec. 1987, pp. 1496-1514.34Hwu, W.W. and Chang, P.P., "Exploiting Parallel Microprocessor Microarchitectures with a Compiler Code Generator," Proceedings of the 15th Annual Symposium on Computer Architecture, IEEE, Jun. 1988, pp. 45-53.35Hwu, W-M. et al., "An HPS Implementation of VAX: Initial Design and Analysis," Proceedings of the Nineteenth Annual Hawaii International Conference on System Sciences, pp. 282-291 (1986).36IBM Journal of Research and Development, IBM, vol. 34, No. 1, Jan. 1990, pp. 1-70.37Intel Corporation's Answer, Affirmative Defenses, and Counterclaims to Transmeta's First Amended Complaint, 27 pages, files Jan. 9, 2007, in Transmeta Corporation v. Intel Corporation, in the U.S. District Court for the District of Delaware, Case No. 1:06-cv-00633.38Intel Corporation's Opening Claim Construction Brief, 76 pages, dated Oct. 19, 2007, in Transmeta Corporation v. Intel Corporation, in the U.S. District for the District of Delaware, Case No. 1:06-cv-00633.39Intel Corporation's Responses to Transmeta's First Set of Interrogatories to Intel Corporation (Nos. 1-24) - Redacted Public Version, 132 pages, dated May 18, 2007, in Transmeta Corporation v. Intel Corporation, in the U.S. District for the District of Delaware, Case No. 1:06-cv-00633.40Intel Corporation's Supplemental Responses to Transmeta Interrogatory Nos. 8, 9, 12, 19, and 21-23 - Redacted Public Version, 27 pages, dated Aug. 23, 2007, in Transmeta Corporation v. Intel Corporation, in the U.S. District for the District of Delaware, Case No. 1:06-cv-00633.41Intrater et al., "A Superscalar Microprocessor,"IEEE Proceedings of the 17th Convention of Electrical & Electronics Engineers In Israel, pp. 267-270 (Mar. 1991).42Japanese language copy of the Notice of Rejection and the English language translation, issued by the Japanese Patent Office in Appl. No. 2004-010369, dated Jun. 1, 2005 (9 pages).43Japanese language copy of the Notice of Rejection and the English language translation, issued by the Japanese Patent Office in Appl. No. 517306, dated Aug. 26, 2003 (3 pages).44Japanese language copy of the Notice of Rejection and the English language translation, issued by the Japanese Patent Office in Appl. No. 5-502403, dated Jul. 22, 2003 (10 pages).45Japanese language copy of the Notice of Rejection and the English language translation, issued by the Japanese Patent Office in Appl. No. 5-502403, dated Mar. 2, 2004 (9 pages).46Johnson, W. M., Super-Scalar Processor Design, (Dissertation), Copyright 1989, 134 pages.47Jouppi, N.H., "Integration and Packaging Plateaus of Processor Performance," International Conference of Computer Design, IEEE, Oct. 2-4, 1989, pp. 229-232.48Jouppi, N.P. and Wall, D.W., "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines," Proceedings-3rd International Conference on Architectural Support for Programming Languages and Operating Systems, ACM Press, Apr. 1989, pp. 272-282.49Jouppi, N.P., "The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance," IEEE Transactions on Computers, IEEE, vol. 38, No. 12, Dec. 1989, pp. 1645-1658.50Kanai, T. et al., "A 16-bit Microcomputer FPD70423 for Serial Communication," NEC Research & Development, NEC, vol. 32, No. 3, Jul. 1991, pp. 350-360.51Keller, R.M., "Look-Ahead Processors," Computing Surveys, ACM, vol. 7, No. 4, Dec. 1975, pp. 177-195.52Kogge, P.M., The Architecture of Pipelined Computers, Hemisphere Publishing, 1981, pp. 167-172.53Lam, M.S., "Instruction Scheduling For Superscalar Architectures," Annu. Rev. Comput. Sci., Annual Reviews, Inc., vol. 4, 1990, pp. 173-201.54Lee, R.B., "Precision Architecture," IEEE Computer, IEEE, pp. 78-91, Jan. 1989.55Maejima, H. et al., "A 16-bit Microprocessor with Multi-Register Bank Architecture," Proc. Fall Joint Computer Conference, IEEE, Nov. 2-6, 1986, pp. 1014-1019.56Margulis, N., "i860 microprocessor internal architecture," Microprocessors and Microsystems, Butterworth & Co. Ltd., vol. 14, No. 2, Mar. 1990, pp. 89-96.57McGeady, "The i960CA SuperScalar Implementation of the 80960 Architecture," IEEE, pp. 232-240 (1990).58Melear, "The Design of the 88000 RISC Family," IEEE Micro, vol. 9, No. 2, pp. 26-38 (Apr. 1989).59Miller et al., "Exploiting Large Register Sets," Microprocessors and Microsystems, Butterworth-Heinemann Ltd., vol. 14, No. 6, Jul. 1990, pp. 333-340.60Molnar, K. et al., "A 40 MHz 64-Bit Floating-Point Co-Processor," 1989 IEEE International Solid-State Circuits Conference, IEEE, Feb. 1989, pp. 48, 49 and 287.61Murakami, K. et al., "SIMP (Single Instruction stream/Multiple instruction Pipelining): A Novel High-Speed Single-Processor Architecture," Proceedings of the 16th Annual International Symposium on Computer Architecture, ACM Press, 1989, pp. 78-85.62Odnert, D. et al., "Architecture and Compiler Enhancements for PA-RISC Workstations," COMPCON Spring '91 digest of papers, IEEE, 1991, pp. 214-218.63Patent Abstracts of Japan, Publication No. 02-211534, English Language Abstract for JP Patent Application No. 01-031652 (Document AM3), Aug. 22, 1990.64Patent Abstracts of Japan, Publication No. 02-211534, English Language Abstract for JP Patent Application No. 01-031652, (2 pages).65Patent Abstracts of Japan, Publication No. 02-226342, English Language Abstract for JP Patent Application No. 02-001127 (Document AL3), Sep. 7, 1990.66Patent Abstracts of Japan, Publication No. 02-226342, English Language Abstract for JP Patent Application No. 02-001127, (1 page).67Patent Abstracts of Japan, Publication No. 2-118757, English Language Abstract for JP Patent Application No. 63-271010, (2 pages).68Patent Abstracts of Japan, Publication No. 2-224025, English Language Abstract for JP Patent Application No. 01-270136, (1 page).69Patent Abstracts of Japan, Publication No. 57-057345, English Language Abstract for JP Patent Application No. 55-132633 (Document AK3), Apr. 6, 1982.70Patent Abstracts of Japan, Publication No. 57-057345, English Language Abstract for JP Patent Application No. 55-132633, (2 pages).71Patent Abstracts of Japan, Publication No. 60-144830, English Language Abstract for JP Patent Application No. 59-000424, (2 pages).72Patent Abstracts of Japan, Publication No. 61-40650, English Language Abstract for JP Patent Application No. 59-163061, (1 page).73Patent Abstracts of Japan, Publication No. 62-242243, English Language Abstract for JP Patent Application No. 61-085442, (2 pages).74Patt et al., "Run-Time Generation of HPS Microinstructions From a VAX Instruction Stream," Proceedings of MICRO 19 Workshop, New York, pp. 75-81 (Oct. 1986).75Patt, Y.N. et al., "Critical Issues Regarding HPS, A High Performance Microarchitecture," Proceedings of the 18th Annual Workshop on Microprogramming, ACM, Dec. 1985, pp. 109-116.76Patt, Y.N. et al., "Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers," COMPCON 86, IEEE, pp. 254-258 (1986).77Patt, Y.N. et al., "HPS, A New Microarchitecture: Rationale and Introduction," Proceedings of the 18th Annual Workshop on Microprogramming, ACM, Dec. 1985, pp. 103-108.78Patterson, D. A. and S�quin, C.H., "A VLSI RISC," Computer, IEEE, vol. 15, No. 9, Sep. 1982, pp. 8-18 and 20-21.79Peleg, A. and Weiser, U., "Future Trends in Microprocessors: Out-of-Order Execution, Speculative Branching and their CISC Performance Potential", IEEE, pp. 263-266 (1991).80Pleszkun, A.R. and Sohi, G.S., "The Performance Potential of Multiple Functional Unit Processors*," Proceedings of the 15th Annual Symposium on Computer Architecture, IEEE, Jun. 1988, pp. 37-44.81Pleszkun, A.R. et al., "WISQ: A Restartable Architecture Using Queues," Proceedings of the 14th International Symposium on Computer Architecture, ACM, Jun. 1987, pp. 290-299.82Popescu et al, "The Metaflow Archictecture," IEEE Micro, vol. 11, No. 3, pp. 10-13, 63-73 (Jun. 1991).83Russell, R.M., "The CRAY-1 Computer System," Communications of the ACM, ACM, vol. 21, No. 1, Jan. 1978, pp. 63-72.84Smith, J.E. and Pleszkun, A.R.,"Implementation of Precise Interrupts in Pipelined Processors," Proceedings of the 12th Annual International Symposium on Computer Architecture, IEEE, Jun. 1985, pp. 36-44.85Smith, M.D. et al., "Boosting Beyond Static Scheduling in a Superscalar Processor," ACM SIGARCH Computer Architecture News, ACM Press, vol. 18, Issue 3, Jun. 1990, pp. 344-354.86Smith, M.D. et al., "Limits on Multiple Instruction Issue," Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, Apr. 1989, pp. 290-302.87Sohi, G. S. and Vajapeyam, S., "Instruction Issue Logic For High-Performance, Interruptable Pipelined Processors," Proceedings of the 14th Annual International Symposium on Computer Architecture, ACM, Jun. 2-5, 1987, pp. 27-34.88Steven, G.B. et al., "HARP: A parallel pipelined RISC processor," Microprocessors and Microsystems, Butterworth & Co. Ltd., vol. 13, No. 9,Nov. 1989, pp. 579-586.89Swensen, J.A. and Patt, Y.N., "Hierarchical Registers for Scientific Computers," Conference Proceedings: 1988 International Conference on Supercomputing, ICS, Jul. 4-8, 1988, pp. 346-353.90Third-Generation TMS320 User's Guide, Texas Insturments, 1988.91Thomton, J.E., Design of a Computer: The Control Data 6600, Control Data Corporation, 1970, pp. 58-140.92Tjaden, G.J., Representation and Detection of Concurrency Using Ordering Matrices, (Dissertation), UMI Dissertation Services, 1972, pp. 1-199.93Tjaden, G.S. and Flynn, M.J., "Detection and Parallel Execution of Independent Instruction," IEEE Transactions On Computers, IEEE, vol. C-19, No. 10, Oct. 1970, pp. 889-895.94Tjaden, G.S. and Flynn, M.J., "Representation of Concurrency with Ordering Matrices," IEEE Transactions On Computers, IEEE, vol. C-22, No. 8, Aug. 1973, pp. 752-761.95U.S. Appl. No. 07/259,345, filed Oct. 18, 1988, Barbour.96Uht, A.K., "An Efficient Hardware Algorithm to Extract Concurrency From General-Purpose Code," Proceedings of the 19th Annual Hawaii International Conference on System Sciences, University of Hawaii, IEEE, 1986, pp. 41-50.97Wedig, R.G., Detection of Concurrency In Directly Executed Language Instruction Streams, (Dissertation), UMI, Jun. 1982, pp. 1-179.98Weiss, S. and Smith, J.E., "Instruction Issue Logic in Pipelined Supercomputers," IEEE Transactions on Computers, IEEE, vol. C-33, No. 11, Nov. 1984, pp. 1013-1022 (77-86).99Wilson, J.E. et al., "On Tuning the Microarchitecture of an HPS Implementation of the VAX," Proceedings of the 20th Annual Workshop on Microprogramming, IEEE Computer Society, pp. 162-167 (Dec. 1-4, 1987).Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7941636 *Dec 31, 2009May 10, 2011Intellectual Venture Funding LlcRISC microprocessor architecture implementing multiple typed register sets* Cited by examinerClassifications U.S. Classification712/23, 712/228International ClassificationG06F9/46, G06F9/34, G06F9/42, G06F9/48, G06F9/318, G06F15/00, G06F9/305, G06F9/30, G06F9/38Cooperative ClassificationG06F9/30123, G06F9/30116, G06F9/30112, G06F9/3012, G06F9/3851, G06F9/30036, G06F9/30029, G06F9/30167, G06F9/30181, G06F9/3013, G06F9/30138European ClassificationG06F9/30A1L, G06F9/30R5, G06F9/30X, G06F9/30R4D, G06F9/30A1P, G06F9/30R4C, G06F9/30R5D, G06F9/30T4T, G06F9/30R5C, G06F9/30R5X, G06F9/38E4Legal EventsDateCodeEventDescriptionAug 20, 2013FPExpired due to failure to pay maintenance feeEffective date: 20130630Jun 30, 2013LAPSLapse for failure to pay maintenance feesFeb 11, 2013REMIMaintenance fee reminder mailedApr 3, 2009ASAssignmentOwner name: TRANSMETA LLC, CALIFORNIAFree format text: MERGER;ASSIGNOR:TRANSMETA CORPORATION;REEL/FRAME:022494/0500Effective date: 20090127Owner name: TRANSMETA LLC,CALIFORNIAFree format text: MERGER;ASSIGNOR:TRANSMETA CORPORATION;US-ASSIGNMENT DATABASE UPDATED:20100216;REEL/FRAME:22494/500Free format text: MERGER;ASSIGNOR:TRANSMETA CORPORATION;US-ASSIGNMENT DATABASE UPDATED:20100225;REEL/FRAME:22494/500Free format text: MERGER;ASSIGNOR:TRANSMETA CORPORATION;US-ASSIGNMENT DATABASE UPDATED:20100323;REEL/FRAME:22494/500Owner name: TRANSMETA LLC,CALIFORNIAFree format text: MERGER;ASSIGNOR:TRANSMETA CORPORATION;US-ASSIGNMENT DATABASE UPDATED:20100323;REEL/FRAME:22494/500Effective date: 20090127Owner name: TRANSMETA LLC,CALIFORNIAFree format text: MERGER;ASSIGNOR:TRANSMETA CORPORATION;US-ASSIGNMENT DATABASE UPDATED:20100225;REEL/FRAME:22494/500Effective date: 20090127Owner name: TRANSMETA LLC,CALIFORNIAFree format text: MERGER;ASSIGNOR:TRANSMETA CORPORATION;REEL/FRAME:022494/0500Effective date: 20090127Owner name: TRANSMETA LLC,CALIFORNIAFree format text: MERGER;ASSIGNOR:TRANSMETA CORPORATION;US-ASSIGNMENT DATABASE UPDATED:20100216;REEL/FRAME:22494/500Effective date: 20090127Mar 4, 2009ASAssignmentOwner name: INTELLECTUAL VENTURE FUNDING LLC, NEVADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRANSMETA LLC;REEL/FRAME:022343/0219Effective date: 20090128Owner name: INTELLECTUAL VENTURE FUNDING LLC,NEVADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRANSMETA LLC;US-ASSIGNMENT DATABASE UPDATED:20100216;REEL/FRAME:22343/219Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRANSMETA LLC;US-ASSIGNMENT DATABASE UPDATED:20100225;REEL/FRAME:22343/219Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRANSMETA LLC;US-ASSIGNMENT DATABASE UPDATED:20100323;REEL/FRAME:22343/219Owner name: INTELLECTUAL VENTURE FUNDING LLC,NEVADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRANSMETA LLC;US-ASSIGNMENT DATABASE UPDATED:20100225;REEL/FRAME:22343/219Effective date: 20090128Owner name: INTELLECTUAL VENTURE FUNDING LLC,NEVADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRANSMETA LLC;REEL/FRAME:022343/0219Effective date: 20090128Owner name: INTELLECTUAL VENTURE FUNDING LLC,NEVADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRANSMETA LLC;US-ASSIGNMENT DATABASE UPDATED:20100323;REEL/FRAME:22343/219Effective date: 20090128Owner name: INTELLECTUAL VENTURE FUNDING LLC,NEVADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRANSMETA LLC;US-ASSIGNMENT DATABASE UPDATED:20100216;REEL/FRAME:22343/219Effective date: 20090128RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services