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Patent US5543351 - Method of producing electrically insulated silicon structure - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA silicon substrate comprises at least two surfaces extending substantially along respective crystal faces of (111) crystal orientation of the silicon, the crystal faces of (111) crystal orientation crossing with each other, an electrically insulating layer formed by oxidizing the silicon substrate from...http://www.google.com/patents/US5543351?utm_source=gb-gplus-sharePatent US5543351 - Method of producing electrically insulated silicon structureAdvanced Patent SearchPublication numberUS5543351 APublication typeGrantApplication numberUS 08/331,733Publication dateAug 6, 1996Filing dateOct 31, 1994Priority dateMar 19, 1992Fee statusPaidAlso published asUS5405454Publication number08331733, 331733, US 5543351 A, US 5543351A, US-A-5543351, US5543351 A, US5543351AInventorsYoshihiko Hirai, Kiyoshi Morimoto, Yasuaki Terui, Masaaki Niwa, Juro Yasui, Kenji Okada, Masaharu Udagawa, Koichiro YukiOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (20), Non-Patent Citations (10), Referenced by (57), Classifications (14), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetMethod of producing electrically insulated silicon structureUS 5543351 AAbstract A silicon substrate comprises at least two surfaces extending substantially along respective crystal faces of (111) crystal orientation of the silicon, the crystal faces of (111) crystal orientation crossing with each other, an electrically insulating layer formed by oxidizing the silicon substrate from the surfaces, and an electrically conductive portion insulated electrically by the electrically insulating layer from an outside of the silicon substrate.
What is claimed is: 1. A method for producing a quantum portion of a silicon substrate insulated electrically from an outside of the silicon substrate, said method comprising:etching the silicon substrate to form at least two surfaces of the silicon substrate extending substantially along respective crystal faces of (111) crystal orientation of the silicon substrate, said at least two surfaces having a first flatness and a first linearity; and oxidizing a portion of the silicon substrate from the surfaces to form an electrically insulating layer, to form the quantum portion under the electrically insulating layer so that the electrically insulating layer insulates electrically the quantum portion of the silicon substrate from the outside of the silicon substrate and to form a boundary between the quantum portion and the electrically insulating layer, the boundary having a second flatness and a second linearity, at least one of the second flatness and the second linearity being superior to the first flatness or the first linearity. 2. A method according to claim 1, wherein a pre-formed surface of the silicon substrate extending in a direction substantially perpendicular to a crystal face of (100) crystal orientation of the silicon substrate under an etching-resistant layer is etched to form the surfaces, so that a constricted neck portion of the silicon substrate is formed by a join of the surfaces.
3. A method according to claim 1, wherein a pre-formed surface of the silicon substrate extending under an etching-resistant layer to form an acute angle between a crystal face of (100) crystal orientation of the silicon substrate and the pre-formed surface is etched to form the surfaces, so that a constricted neck portion of the silicon substrate is formed by a join of the surfaces.
4. A method according to claim 1, wherein a pre-formed surface of the silicon substrate extending in a direction substantially parallel to a crystal face of (100) crystal orientation of the silicon substrate is etched to form the surfaces, so that a trapezoidal portion of the silicon substrate is formed by the surfaces.
5. A method according to claim 1, wherein an etching-resistant layer is arranged on the silicon substrate before etching the silicon substrate, and the etching-resistant layer is removed from the silicon substrate after etching the silicon substrate and before oxidizing the portion of the silicon substrate, so that the quantum portion is surrounded by the electrically insulating layer.
6. A method acceding to claim 1, wherein an etching-resistant layer is arranged on the silicon substrate before etching the silicon substrate, and the etching-resistant layer is removed from the silicon substrate after oxidizing the portion of the silicon substrate, so that a part of the quantum portion is exposed to the outside of the silicon substrate.
7. A method according to claim 1, wherein an etching-resistant layer is arranged on the silicon substrate before etching the silicon substrate, the etching-resistant layer is removed from the silicon substrate after oxidizing the portion of the silicon substrate so that a part of the quantum portion is exposed to the outside of the silicon substrate, and a surface of the part of the quantum portion is oxidized.
8. A method according to claim 1, wherein a silicon oxide layer is formed in the silicon substrate before etching the silicon substrate, so that a part of the silicon substrate on the silicon oxide layer is etched and another part of the silicon substrate under the silicon oxide layer is not etched.
9. A method according to claim 1, wherein the silicon substrate is formed on a silicon oxide layer before etching the silicon substrate.
10. A method according to claim 1, wherein the silicon substrate is formed on an electrically semi-conductive layer before etching the silicon substrate.
11. A method according to claim 1, wherein the silicon substrate is formed on a high-impurity-concentration electrically semi-conductive layer before etching the silicon substrate.
12. A method according to claim 1, wherein the silicon substrate is formed on a high-boron-concentration electrically semi-conductive layer before etching the silicon substrate.
13. A method according to claim 1, wherein an etching-resistant layer is arranged on the silicon substrate before etching the silicon substrate, and an angular error of a side of the etching-resistant layer relative to an imaginary cross line of the crystal faces of (111) crystal orientation is within �1 degree.
14. A method according to claim 1, wherein the portion of the silicon substrate is oxidized by an oxygen plasma from the surfaces.
15. A method according to claim 1, wherein the portion of the silicon substrate is oxidized thermally from the surfaces.
16. A method according to claim 1, wherein the quantum portion has at least one dimension not exceeding 100 nm.
This is a division of application Ser. No. 08/030,556 filed Mar. 12, 1993 now U.S. Pat. No. 5,405,454.
BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT The present invention relates to electrically insulated silicon structures and producing methods therefor. A silicon substrate used in the present invention may be pure without impurity, or may include an impurity. It is important for the present invention to be applied to a crystalline structure as a silicon crystal.
JAPANESE JOURNAL OF APPLIED PHYSICS, VOL. 27, NO. 9, SEPTEMBER, 1988, pp. L1778-L1779 by Shimizu et al. and Extended Abstracts (The 37th Spring Meeting, 1990); The Japan Society of Applied Physics and Related Societies No. 2, 30a-SB-5, page 613 by Iwameji et al. disclose fabrications of fine silicon structures.
In these disclosures, as shown in FIGS. 3A and 3B, a crystal face of (111) crystal orientation which is the most anti-etching or etching-resistant face in the silicon is utilized for forming an outer surface of the silicon structure. When a silicon substrate 10 on which an anti-etching pattern layer 12 is formed through lithography is etched by ethylene-diamine solution or potassium hydroxide solution or the like, side walls 13 extending along the crystal face of the (111) crystal orientation of the silicon remain to form a projection 40 with a trapezoid cross-section.
OBJECT AND SUMMARY OF THE INVENTION An object of the present invention is to provide an electrically insulated silicon dot or wire whose outer boundary facing an electrically insulating layer has an improved sufficient positional accuracy, flatness and linearity for an electrically conductive or semi-conductive quantum dot or wire.
According to the present invention, a silicon substrate comprises,
at least two surfaces extending substantially along respective crystal faces of (111) crystal orientation of the silicon, the crystal faces of (111) crystal orientation crossing with each other,
an electrically insulating layer formed by oxidizing the silicon substrate from the surfaces, and
an electrically conductive portion insulated electrically by the electrically insulating layer from an outside of the silicon Substrate.
According to the present invention, a method for producing an electrically conductive portion of a silicon substrate insulated electrically from an outside of the silicon substrate comprises the steps of
etching the silicon substrate to form at least two surfaces of the silicon substrate extending substantially along respective crystal faces of (111) crystal orientation of the silicon, the crystal faces of (111) crystal orientation crossing with each other, and
oxidizing the silicon substrate from the surfaces to form an electrically insulating layer and to leave a electrically conductive portion under the electrically insulating layer so that the electrically insulating layer insulates electrically the electrically conductive portion of the silicon substrate from the outside of the silicon substrate.
Since the electrically insulating layer is formed on the electrically conductive portion by oxidizing the silicon substrate from the surfaces extending substantially along the crystal faces of (111) crystal orientation of the silicon, the positional accuracy, flatness and linearity of the outer boundary of the electrically conductive portion facing to the electrically insulating layer are improved by those of the surfaces and are superior to those of the surfaces. Therefore, the boundary between the electrically conductive portion and the electrically insulating layer or an outer surface of the electrically conductive portion is preferable for the electrically conductive or semi-conductive quantum dot or wire.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B are schematic oblique-projection views showing embodiments of the present invention, respectively.
FIG. 1C is a schematic cross-sectional view showing the embodiments of FIGS. 1A and 1B.
FIGS. 2A-2D are schematic oblique-projection cross-sectional views showing a method for producing the embodiment of FIG. 1A.
FIGS. 3A and 3B are schematic oblique-projection cross-sectional views showing a prior-art method for producing a silicon shape.
FIGS. 4A-4G are schematic oblique-projection cross-sectional views showing another method for producing another embodiment of the present invention.
FIGS. 5A-5D are schematic oblique-projection cross-sectional views showing another method for producing another embodiment of the present invention.
FIGS. 6A-6D are schematic oblique-projection views cross-sectional showing another method for producing another embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In embodiments shown in FIGS. 1A and 1B, a silicon substrate 10 has four side walls 23 extending substantially along respective crystal faces of (111) crystal orientation of the silicon. One pair of the side walls 23 extending substantially along the crystal faces crossing with each other is included on a sub-portion 15 of the silicon substrate 10, and another one pair of the side walls 23 extending substantially along the crystal faces crossing with each other is included on a main-portion 14 of the silicon substrate 10. The silicon substrate 10 has an silicon oxide layer 25 which extends from the side walls 23 and which is formed by oxidizing the silicon substrate 10 from the side walls 23 so that an electrically conductive or semi-conductive wire 31 or dot 32 in the sub-portion 15 is electrically partitioned from an electrically conductive or semi-conductive portion 24 in the main-portion 14 by the silicon oxide layer 25. Since the silicon substrate 10 is oxidized from the side walls 23 extending substantially along the crystal faces of (111) crystal orientation of the silicon, a boundary between the silicon oxide layer 25 and the electrically conductive or semi-conductive wire 31 or dot 32 can be correctly positioned, and has a flatness and lineartry superior to those of the side walls 23.
In a method as shown in FIGS. 2A-2D, firstly, an upper surface along a crystal face of (100) crystal orientation of a silicon substrate 10 with an impurity or without the impurity is thermally oxidated by a depth of about 100 nm in a dry oxygen gas of 90� C. Subsequently, on the thermally oxidated upper surface, a rectangular resist mask is formed by a photolithography process. Two opposed sides of the rectangular resist mask extend substantially parallel or perpendicular to the <110> direction of the silicon substrate 10, that is, substantially parallel to an imaginary cross line formed by crystal faces of (111) crystal orientation of the silicon substrate 10. An angular error of each of the opposed sides of the rectangular resist mask relative to the <110> direction or the imaginary cross line within �1 degree can be permitted. The thermally oxidated upper surface with the rectangular resist mask thereon is etched in CF4 gas through a reactive ion etching process so that a part of the thermally oxidated upper surface on which the rectangular resist mask is arranged remains and another part of the thermally oxidated upper surface on which the rectangular resist mask is not arranged is removed by the etching to expose a new upper surface of the silicon Substrate 10. The part of the thermally oxidated upper surface on which the rectangular resist mask is arranged forms an etching-resistant layer 12 on the silicon substrate 10, as shown in FIG. 2A. When the electrically conductive or semi-conductive quantum dot or line is desired, a width of the etching-resistant layer 12 must be adjusted and checked accurately.
Subsequently, the new upper surface is etched and displaced through a silicon dry etching process, but, the silicon substrate 10 under the etching-resistant layer 12 is prevented from being etched through the silicon dry etching process by the etching-resistant layer 12, so that a difference in level of a boundary between the etching-resistant layer 12 and the silicon substrate 10 relative to the new upper surface after being etched and displaced is formed by 200 nm, and side walls 22 extending between the boundary and the new upper surface after being etched and displaced is formed, as shown in FIG. 2B. It is preferable for an angle 21 between each of the side walls 22 and the new upper surface after being etched and displaced to be 90�. Conditions for the silicon dry etching process using, for example, the reactive ion etching process, for obtaining the angle 21 of 90� are as follows:
A flow rate of (SiCl4) gas:a flow rate of (SF6) gas:a flow rate of (CH2 F2) gas:a flow rate of (O2) gas is 12:13:40:19, in an etching gas,
a micro-wave electric power for energizing an electric discharge field in the gas is 160 W,
a high-frequency energizing power for a reaction region is 40 W, and
an etching rate of the silicon substrate 10 is about 500 nm/min.
Even if the angle 21 of 90� cannot be obtained, it is necessary for the angle 21 to be more than 90�.
Subsequently, the new upper surface after being etched and displaced is further etched through a crystal anisotropic (wet chemical) etching process in which an etching rate or speed in a direction perpendicular to the crystal face of (111) crystal orientation of the silicon substrate 10 is about 1/100 of an etching rate or speed in a direction perpendicular to the crystal face of (110) crystal orientation of the silicon substrate 10 and of an etching rate or speed in a direction perpendicular to the crystal face of (100) crystal orientation of the silicon substrate 10 so that a surface along the crystal face of (111) crystal orientation of the silicon substrate 10 remains and the other surfaces along the crystal faces of <110> crystal orientation and (100) crystal orientation of the silicon substrate 10 does not remain on the silicon substrate 10, after the crystal anisotropy etching process. Therefore, side walls 13 extending along the crystal faces of 111 crystal orientation of the silicon substrate 10 crossing each other remain to form a constricted neck portion 20 with a width of 10 nm so that the silicon substrate 10 is divided to a main part 14 and a sub-part 15 by the constricted neck portion 20, as shown in FIG. 2C. When the angle 21 is 90�, an intersecting line of the side walls 13 along the crystal faces of 111 crystal orientation of the silicon substrate 10 crossing each other in the constricted neck portion 20 is positioned at a substantially central level of the above mentioned difference in level of the boundary between the etching-resistant layer 12 and the silicon substrate 10 relative to the new upper surface after being etched and displaced. An angle between each of the side walls 13 along the crystal faces of 111 crystal orientation and the boundary along the crystal faces of 100 crystal orientation between the etching-resistant layer 12 and the silicon substrate 10 is 54.7�.
When an etchant mixture for the crystal anisotropy etching in which a mole percentage of ethylenediamine (NH2 (CH2)2 NH2) is 43.8%, a mole percentage of pyrocatechol (C6 H5 (OH8) is 4.2%, and a mole percentage of pure water (H2 O) is 52% is used and a temperature thereof is 100� C., the etching rate or speed in the direction perpendicular to the crystal face of 111 crystal orientation of the silicon substrate 10 is 7 nm/min, that is, about 1/40 of the etching rate or speed in the direction perpendicular to the crystal face of 110 crystal orientation of the silicon substrate 10 and of the etching rate or speed in the direction perpendicular to the crystal face of 100 crystal orientation of the silicon substrate 10. Therefore, a shape of the constricted neck portion 20, particularly the width thereof, can be accurately adjusted by controlling a time of the crystal anisotropic etching. A linearity and flatness of each of the side walls 13 are improved by the crystal anisotropy etching in the direction perpendicular to the crystal faces of 111 crystal orientation, and a crystal damage or defect of the silicon substrate 10 caused by the dry etching process is removed by the crystal anisotropy etching. Therefore, a crystalline structure in the main part 14 and the sub-part 15 is substantially perfect.
Finally, the etching-resistant layer 12 is removed by hydrofluoric acid, and the silicon substrate 10 is thermally oxidized by a depth of about 50 nm from the side walls 13 thereof in a dry oxygen gas of 900� C. to form an oxidized layer 24 so that the constricted neck portion 20 is oxidized completely, an electrically conductive or semi-conductive portion 31 which is not oxidized to remain in the sub-part 15 is electrically separated and insulated from the main part 14, and a size of the electrically conductive or semi-conductive portion 31 which is not oxidized to remain in the sub-part 15 is minimized by the oxidation. Further, a flatness and linearity of a boundary between the oxidized layer 24 and the remaining electrically conductive or semi-conductive portion 31 are further improved in comparison with those of an outer shape of the side walls 13. An electrical potential barrier height of the oxidized layer 24 reaches about 3 eV.
The upper surface along the crystal face of 100 crystal orientation of the silicon substrate 10 may be oxidized for the etching-resistant layer 12 through a pyrogenic-oxidizing process or steam-oxidation process, instead of the oxidizing in the dry oxygen gas. Alternatively, a silicon-oxide layer or silicon-nitride layer for the etching-resistant layer 12 may be formed on the upper surface of the silicon substrate 10 through a low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) or plasma vapor deposition process. A potassium hydroxide (KOH) solution or a mixture of hydrazine, isopropyl alcohol and pure water may be used as the etchant for the crystal anisotropic etching, instead of the ethylene-diamine type solution. The pyrogenic-oxidation process or steam oxidation process or plasma-oxidation process may be used for oxidizing the side walls 13 to form the oxidized layer 24, instead of the oxidizing in the dry oxygen gas.
In a method as shown in FIGS. 4A-4G, firstly, a silicon-nitride layer with a thickness of about 40 nm is formed through the low-pressure chemical vapor deposition (LPCVD) process on the upper surface along the crystal face of 100 crystal orientation of a silicon substrate 10 with the impurity or without the impurity. Subsequently, on the silicon-nitride layer, a rectangular resist mask is formed by a photolithography process. Two opposed sides of the rectangular resist mask extend substantially parallel or perpendicular to the axis of 110 crystal orientation of the silicon substrate 10, that is, substantially parallel to the imaginary cross line formed by the crystal faces of 111 crystal orientation of the silicon substrate 10. The silicon-nitride layer with the rectangular resist mask thereon is etched so that a pair of the silicon-nitride layer on which the rectangular resist mask is arranged remains and another part of the silicon-nitride layer on which the rectangular resist mask is not arranged is removed by the etching to expose a new upper surface of the silicon substrate 10. The part of the silicon-nitride layer on which the rectangular resist mask is arranged forms an etching-resistant layer 212 on the silicon substrate 10, as shown in FIG. 4A.
Subsequently, the new upper surface is etched and displaced through a silicon dry etching process, but, the silicon substrate 10 under the etching-resistant layer 212 is prevented from being etched through the silicon dry etching process by the etching-resistant layer 12, so that a difference in level of a boundary between the etching-resistant layer 212 and the silicon substrate 10 relative to the new upper surface after being etched and displaced is 200 nm, and side walls 222 extending between the boundary and the new upper surface after being etched and displaced are formed, as shown in FIG. 4B.
Subsequently, the new upper surface after being etched and displaced is further etched through the crystal anisotropic etching process. Therefore, side walls 213 extending along the crystal faces of 111 crystal orientation of the silicon substrate 10 crossing each other remains to form a constricted neck portion 220 with a width of 10 nm so that the silicon substrate 10 is divided to a main part 214 and a sub-part 215 by the constricted neck portion 220, as shown in FIG. 4C.
Subsequently, while the etching-resistant layer 212 remains on the sub-part 215, the silicon substrate 10 is thermally oxidized from the side walls 213 thereof in the dry oxygen gas of 900� C. to form an oxidized layer 224, so that an upper surface of the sub-part 215 is prevented from being oxidized by the silicon-nitride etching-resistant layer 212, the constricted neck portion 220 is oxidized completely, an electrically conductive or semi-conductive portion 231 which is not oxidized to remain in the sub-part 215 is electrically separated and insulated from the main part 214, and a size of the electrically conductive or semi-conductive portion 231 which is not oxidized to remain in the sub-part 215 is minimized by the oxidation, as shown in FIG. 4D. Further, a flatness and linearity of a boundary between the oxidized layer 224 and the remaining electrically conductive or semi-conductive portion 231 are further improved in comparison with those of an outer shape of the side walls 213.
Subsequently, the silicon-nitride etching-resistant layer 212 is removed from the upper surface of the sub-part 215 by a thermal phosphoric acid solution so that the electrically conductive or semi-conductive portion 231 a part of which is surrounded by the oxidized layer 224 and another part of which is exposed as shown in FIG. 4E is formed.
If the resist mask is circular or square, the electrically conductive or semi-conductive portion 231 is a dot-like shape.
Subsequently, a thin oxide gate layer 240 with a thickness of 10 nm is formed as shown in FIG. 4F, by oxidizing thermally an upper surface of the electrically conductive or semi-conductive portion 231 in the oxygen gas of 900� C. Thereafter, an aluminum gate electrode layer 241 with a thickness of 500 nm is formed over the electrically conductive or semi-conductive portion 231 as shown in FIG. 4G, by sputtering.
In a method as shown in FIGS. 5A-5D, the present invention is applied to a semiconductor or insulator (SOI), whose structure is formed through a separation-by-implanted-oxygen (SIMOX) process. In the separation-by-implanted-oxygen process, after oxygen ions are inserted into a silicon substrate 310, by an ion implantation process with an oxygen ion dosing rate of 1.8 * 1018 cm-2 and an accelerating voltage of 200 keV while keeping a temperature of the silicon substrate 310 at 500�-600� C., from an upper surface thereof extending along a crystal face of 100 crystal orientation of the silicon substrate 310 with an impurity or without the impurity, the silicon substrate 310 is treated with heat in a temperature of 1300� C. for six hours so that an embedded electrically insulating (silicon-oxide) layer 311 with a thickness of 0.4 μm is formed in the silicon substrate 310 and an upper silicon layer 320 of the silicon substrate 310 is electrically separated or insulated by the electrically insulating (silicon-oxide) layer 311 from the remaining portion of the silicon substrate 310, as shown in FIG. 5A. A thickness of the upper silicon layer 320 can be easily decreased to about 150 nm through a thermal oxidation and an etching process with a hydrofluoric acid.
Subsequently, the upper silicon layer 320 is thermally oxidated by a depth of about 100 nm in a dry oxygen gas of 900� C. Subsequently, on the thermally oxidated upper surface, a rectangular resist mask is formed by a photolithography process. Two opposed sides of the rectangular resist mask extend substantially parallel or perpendicular to the <110> direction of the silicon substrate 310, that is, substantially parallel to an imaginary cross line formed by crystal faces of (111) crystal orientation of the silicon substrate 310. An angular error of each of the opposed sides of the rectangular resist mask relative to the <110> direction or the imaginary cross line within �1 degree can be permitted. The thermally oxidated upper surface with the rectangular resist mask thereon is etched in CF4 gas through the reactive ion etching process so that a part of the thermally oxidated upper surface on which the rectangular resist mask is arranged remains and another part of the thermally oxidated upper surface on which the rectangular resist mask is not arranged is removed by the etching to expose a new upper surface of the upper silicon layer 320. The part of the thermally oxidated upper surface on which the rectangular resist mask is arranged forms an etching-resistant layer 312 on the upper silicon layer 320, as shown in FIG. 5B. When the electrically conductive or semi-conductive quantum dot or wire is desired, a width of the etching-resistant layer 312 must be adjusted and checked accurately. An angular error of each of opposed sides of the etching-resistant layer 312 relative to the axis of 110 crystal orientation or the imaginary cross line is preferably maintained within �1 degree.
Subsequently, the new upper surface of the upper silicon layer 320 with the etching-resistant layer 312 thereon is etched through an anisotropic etching process in which the electrically insulating (silicon-oxide) layer 311 is not etched, an etching rate or speed in a direction perpendicular to the crystal face of 111 crystal orientation of the silicon substrate 310 or upper silicon layer 320 is about 1/100 of an etching rate or speed in a direction perpendicular to the crystal face of 110 crystal orientation of the silicon substrate 310 or upper silicon layer 320 and of an etching rate or speed in a direction perpendicular to the crystal face of 100 crystal orientation of the silicon substrate 310 or upper silicon layer 320, so that a surface along the crystal face of 111 crystal orientation of the silicon substrate 310 or upper silicon layer 320 remains and the other surfaces along the crystal faces of 110 crystal orientation and 100 crystal orientation of the silicon substrate 310 do not remain on the silicon substrate 310 or electrically insulating (silicon-oxide) layer 311, after the crystal anisotropy etching process. Therefore, side walls 313 of a part of the upper silicon layer 320 extending along the crystal faces of 111 crystal orientation of the silicon substrate 310 or upper silicon layer 320 crossing each other under the etching-resistant layer 312 remains on the electrically insulating silicon-oxide layer 311 to form a trapezoidal portion 315 under the etching-resistant layer 312, as shown in FIG. 5C. An angle between each of the side walls 313 and the electrically insulating silicon-oxide layer 311 is 54.7�, and a height of the trapezoidal portion 315 is equal to a thickness of the upper silicon layer 320.
When an etchant mixture for the anisotropic etching in which a mole percentage of ethylene-diamine (NH2 (CH)2 NH2) is 43.8%, a mole percentage of pyrocatechol (C6 H5 (OH8) is 4.2%, and a mole percentage of pure water (H2 O) is 52% is used and a temperature thereof is 100� C., the etching rate or speed in the direction perpendicular to the crystal face of 111 crystal orientation of the silicon substrate 10 is 7 nm/min, that is, about 1/40 of the etching rate or speed in the direction perpendicular to the crystal face of 110 crystal orientation of the silicon substrate 10 and of the etching rate or speed in the direction perpendicular to the crystal face of 100 crystal orientation of the silicon substrate 10. Therefore, a shape of the trapezoidal portion 315, particularly the width thereof, can be accurately adjusted by controlling a time of the anisotropic etching. A linearity and flatness of each of the side walls 313 are improved by the crystal anisotropic etching in the direction perpendicular to the crystal faces of 111 crystal orientation.
Finally, the etching-resistant layer 312 is removed by a hydrofluoric acid, and the trapezoidal portion 315 is thermally oxidized by a depth of about 20 nm from the side walls 313 thereof in a dry oxygen gas of 900� C. to form an oxidized layer 324 in the trapezoidal portion 315 to leave an electrically conductive or semi-conductive portion which is not oxidized to remain in the trapezoidal portion 315, and a size of the electrically conductive or semi-conductive portion which is not oxidized to remain in the trapezoidal portion 315 is minimized by the oxidation. Further, a flatness and linearity of a boundary between the oxidized layer 324 in the trapezoidal portion 315 and the remaining electrically conductive or semi-conductive portion in the trapezoidal portion 315 are further improved in comparison with those of an outer shape of the side walls 313. An electrical potential barrier height of the oxidized layer 324 reaches about 3 eV.
A silicon layer as the upper silicon layer 320 on the electrically insulating layer 311 may be formed by recrystallization of a silicon layer onto a silicon-oxide layer, epitaxial growth of the silicon layer on the silicon-oxide layer or sticking together the silicon layer and the silicon-oxide layer. The upper surface of the upper silicon layer 320 may be oxidized for the etching-resistant layer 312 through a pyrogenic-oxidation process or steam-oxidation process, instead of the oxidizing in the dry oxygen gas. Alternatively, a silicon-oxide layer or silicon-nitride layer for the etching-resistant layer 312 may be formed on the upper surface of the upper silicon layer 320 through a low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) or plasma vapor deposition process. A potassium hydroxide (KOH) solution or a mixture of hydrazine, isopropyl alcohol and pure water may be used as the etchant for the crystal anisotropic etching, instead of the ethylene-diamine type solution. The pyrogenic-oxidation process or steam-oxidation process or oxygen-plasma-gas-oxidation process may be used for oxidizing the side walls 313 to form the oxidized layer 324, instead of the oxidizing in the dry oxygen gas.
In a method as shown in FIGS. 6A-6D, a silicon substrate 410 is treated for 45 minutes with heat of 950� C. in an electric furnace through which (B2 H6) gas diluted to 1000 ppm with argon gas flows with a flow rate of 210 cm3 /min, oxygen gas flows with a flow rate of 13 cm3 /min and nitrogen gas flows with a flow rate of 1300 cm3 /min, so that an upper portion of the silicon substrate 410 is changed to a high-impurity-concentration P-channel layer 411. Subsequently, a boron glass formed on the high-impurity-concentration P-channel layer 411 during the above heat treatment is removed in a dark room by dilute hydrofluoric acid. Subsequently, a low temperature epitaxial growth of a low-impurity-concentration N-channel layer 420 by a thickness of about 150 nm on the high-impurity-concentration P-channel layer 411 is performed by a sputtering equipment in which a temperature of the silicon substrate 410 is about 300� C., bias voltage for the silicon substrate 410 is 5 V, RF power is 40 W, a target material is a monocrystalline silicone doped with phosphorus by about 1017 cm-3 and bias voltage for the target is 200 V, so that a sharp P-N junction is formed, as shown in FIG. 6A. In order to prevent the sharp P-N junction from being damaged, it is necessary for the silicon substrate 410 with the P-N junction to be treated under a low-temperature condition.
Subsequently, a silicon-oxide layer with a thickness of about 100 nm is formed over the low-impurity-concentration N-channel layer 420 in a temperature of 300� C. through the plasma chemical vapor deposition process. Subsequently, on the silicon-oxide layer over the low-impurity-concentration N-channel layer 420, a rectangular resist mask is formed by the photolithography process. Two opposed sides of the rectangular resist mask extend substantially parallel or perpendicular to the <110> direction of the low-impurity-concentration N-channel layer 420, that is, substantially parallel to an imaginary cross line formed by crystal faces of (111) crystal orientation of the low-impurity-concentration N-channel layer 420. An angular error of each of the opposed sides of the rectangular resist mask relative to the <110> direction or the imaginary cross line within �1 degree can be permitted. The silicon-oxide layer with the rectangular resist mask thereon is etched in CF4 gas through the reactive ion etching process so that a part of the thermally oxidated upper surface on which the rectangular resist mask is arranged remains and another part of the thermally oxidated upper surface on which the rectangular resist mask is not arranged is removed by the etching to expose a new upper surface of the low-impurity-concentration N-channel layer 420. The part of the thermally oxidated upper surface on which the rectangular resist mask is arranged forms an etching-resistant layer 412 on the low-impurity-concentration N-channel layer 420, as shown in FIG. 6B. When the electrically conductive or semi-conductive quantum dot or wire is desired, a width of the etching-resistant layer 412 must be adjusted and checked accurately.
Subsequently, the new upper surface of the low-impurity-concentration N-channel layer 420 with the etching-resistant layer 412 thereon is etched through an anisotropic etching process in which the high-impurity concentration P-channel layer 411 with an impurity concentration of 1020 cm-3 is not etched, an etching rate or speed in a direction perpendicular to the crystal face of 111 crystal orientation of the low-impurity-concentration N-channel layer 420 is about 1/100 of the etching rate or speed in a direction perpendicular to the <110> direction of the low-impurity-concentration N-channel layer 420 and of an etching rate of speed in a direction perpendicular to the crystal face of (100) crystal orientation of the low-impurity-concentration N-channel layer 420, so that a surface along the crystal face of (111) crystal orientation of the low-impurity concentration N-channel layer 420 remains and the other surfaces along the crystal faces of (110) crystal orientation and (100) crystal orientation of the low-impurity-concentration N-channel layer 420 do not remain on the high-impurity-concentration P-channel layer 411, after the crystal anisotropic etching process. Therefore, side walls 413 of a part of the low-impurity-concentration N-channel layer 420 extending along the crystal faces of (111) crystal orientation of the low-impurity-concentration N-channel layer 420 crossing each other under the etching-resistant layer 412 remain on the high-impurity-concentration P-channel layer 411 to form a trapezoidal portion 415 under the etching-resistant layer 412, as shown in FIG. 6C. An angle between each of the side walls 413 and the high-impurity-concentration P-channel layer 411 is 54.7�, and a height of the trapezoidal portion 415 is equal to a thickness of the low-impurity-concentration N-channel layer 420.
When an etchant mixture for the anisotropic etching in which a mole percentage of ethylene-diamine NH2 (CH)2 NH2) is 43.8%, a mole percentage of pyrocatechol (C6 H5 (OH)8) is 4.2%, and a mole percentage of pure water (H2 O) is 52% is used and a temperature thereof is 100� C., the etching rate or speed in the direction perpendicular to the crystal face of 111 crystal orientation of the low-impurity-concentration N-channel layer 420 is 7 nm/min, that is, about 1/40 of the etching rate or speed in the direction perpendicular to the crystal face of 110 crystal orientation of the low-impurity-concentration N-channel layer 420 and of the etching rate or speed in the direction perpendicular to the crystal face of 100 crystal orientation of the low-impurity-concentration N-channel layer 420. Therefore, a shape of the trapezoidal portion 415, particularly the width thereof, can be accurately adjusted by controlling a time of the crystal anisotropic etching. A linearity and flatness of each of the side walls 413 are improved by the crystal anisotropic etching in the direction perpendicular to the crystal faces of 111 crystal orientation.
Finally, the etching-resistant layer 412 is removed by a hydrofluoric acid, and an exposed surface of the trapezoidal portion 415 and an upper surface of the high-impurity-concentration P-channel layer 411 are oxidized in an oxygen plasma or an oxygen ion to form an oxidized layer 424 in the trapezoidal portion 415 to leave an electrically conductive or semi-conductive portion which is not oxidized to remain in the trapezoidal portion 415, and a size of the electrically conductive or semi-conductive portion which is hot oxidized to remain An the trapezoidal portion 315 is minimized by the oxidation. Further, a flatness and linearity of a boundary between the oxidized layer 424 in the trapezoidal portion 415 and the remaining electrically conductive or semi-conductive portion in the trapezoidal portion 415 are further improved in comparison with those of an outer shape of the side walls 413 by the oxidation. An electrical potential barrier height of the oxidized layer 424 reaches about 3 eV.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3761785 *Apr 23, 1971Sep 25, 1973Bell Telephone Labor IncMethods for making transistor structuresUS4485551 *Dec 16, 1982Dec 4, 1984Rockwell International CorporationNPN Type lateral transistor separated from substrate by O.D.E. for minimal interference therefrom and method for producing sameUS4497685 *Oct 24, 1983Feb 5, 1985Rockwell International CorporationMasking, etching and oxidizing a substrateUS4584762 *Dec 5, 1983Apr 29, 1986Rockwell International CorporationLateral transistor separated from substrate by intersecting slots filled with substrate oxide for minimal interference therefrom and method for producing sameUS4611387 *Apr 8, 1985Sep 16, 1986Rockwell International CorporationProcess for producing NPN type lateral transistorsUS4649627 *Jun 28, 1984Mar 17, 1987International Business Machines CorporationMethod of fabricating silicon-on-insulator transistors with a shared elementUS4851078 *Jun 29, 1987Jul 25, 1989Harris CorporationDielectric isolation process using double wafer bondingUS5258326 *Mar 27, 1992Nov 2, 1993Eastman Kodak CompanyGood interfaceUS5262346 *Dec 16, 1992Nov 16, 1993International Business Machines CorporationNitride polish stop for forming SOI wafersUS5296719 *Jul 20, 1992Mar 22, 1994Matsushita Electric Industrial Co., Ltd.Quantum device and fabrication method thereofUS5313484 *Jun 15, 1992May 17, 1994Fujitsu LimitedQuantum box or quantum wire semiconductor structure and methods of producing sameEP0069191A1 *Feb 25, 1982Jan 12, 1983Rockwell International CorporationComplementary NPN and PNP lateral transistors separated from substrate by intersecting slots filled with substrate oxide for minimal interference therefrom and method for producing sameJPH034442A * Title not availableJPH0341748A * Title not availableJPH02303048A * Title not availableJPH03110855A * Title not availableJPH03240255A * Title not availableJPH04324955A * Title not availableJPS61154141A * Title not availableJPS62229855A * Title not available* Cited by examinerNon-Patent CitationsReference1D. G. Hasko, "Fabrication of Submicrometer Freestanding Single-Crystal Gallium Arsenide and Silicon Structures for Quantum Transport Studies", J. Vac. Sci. Technol. B6(6), Nov./Dec. 1988, pp. 1849-1851.2 *D. G. Hasko, Fabrication of Submicrometer Freestanding Single Crystal Gallium Arsenide and Silicon Structures for Quantum Transport Studies , J. Vac. Sci. Technol. B6(6), Nov./Dec. 1988, pp. 1849 1851.3K. Itoh, et al, "Universal Conductance Fluctuations in Mesoscopic n+. Si Wires", Anderson Localization, Proceedings of the International Symposium, Tokyo, Japan, Aug. 16-18, 1987, pp. 352-359.4 *K. Itoh, et al, Universal Conductance Fluctuations in Mesoscopic n . Si Wires , Anderson Localization, Proceedings of the International Symposium, Tokyo, Japan, Aug. 16 18, 1987, pp. 352 359.5Kazuhiro SHIMIZU, et al "Fabrication of MOS Nanostructure by Employing Electron Beam Lithography and Anisotropic Wet Etching of Silicon", Japanese Journal of Applied Physics, vol. 30, No. 3A, Mar. 1991, pp. L415-L417.6Kazuhiro SHIMIZU, et al "Fabrication of Nanostructure by Anisotropic Wet Etching of Silicon", Japanese Journal of Applied Physics, vol. 27, No. 9, Sep. 1988, pp. L1778-L1779.7 *Kazuhiro SHIMIZU, et al Fabrication of MOS Nanostructure by Employing Electron Beam Lithography and Anisotropic Wet Etching of Silicon , Japanese Journal of Applied Physics, vol. 30, No. 3A, Mar. 1991, pp. L415 L417.8 *Kazuhiro SHIMIZU, et al Fabrication of Nanostructure by Anisotropic Wet Etching of Silicon , Japanese Journal of Applied Physics, vol. 27, No. 9, Sep. 1988, pp. L1778 L1779.9X. lwameji, et al "Fabrication of Thin Silicon Wires by Anisotropic Etching of a SOI Layer" Extended Abstracts (The 37th Spring Meeting, 1990). The Japan Society of Applied Physics and Related Societies, No. 2, 30a-SB-5, pp. 613.10 *X. lwameji, et al Fabrication of Thin Silicon Wires by Anisotropic Etching of a SOI Layer Extended Abstracts (The 37th Spring Meeting, 1990). The Japan Society of Applied Physics and Related Societies, No. 2, 30a SB 5, pp. 613.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6316337 *Sep 21, 1998Nov 13, 2001Nec CorporationProduction process of SOI substrateUS6653653Jul 13, 2001Nov 25, 2003Quantum Logic Devices, Inc.Single-electron transistors and fabrication methods in which a projecting feature defines spacing between electrodesUS6756614 *Feb 26, 2001Jun 29, 2004Hitachi, Ltd.Thin film semiconductor device, polycrystalline semiconductor thin film production process and production apparatusUS6784082Sep 17, 2002Aug 31, 2004North Carolina State UniversityMethods of fabricating single electron transistors in which the thickness of an insulating layer defines spacing between electrodesUS7115454Sep 26, 2003Oct 3, 2006Hitachi, Ltd.Thin film semiconductor device, polycrystalline semiconductor thin film production and process and production apparatusUS7172932Jun 8, 2004Feb 6, 2007Hitachi, Ltd.Thin film semiconductor device, polycrystalline semiconductor thin film production process and production apparatusUS7297568 *Jun 2, 2003Nov 20, 2007Japan Science And Technology AgencyThree-dimensional structural body composed of silicon fine wire, its manufacturing method, and device using sameUS7329913Dec 27, 2004Feb 12, 2008Intel CorporationNonplanar transistors with metal gate electrodesUS7361958Sep 30, 2004Apr 22, 2008Intel CorporationNonplanar transistors with metal gate electrodesUS7396711Dec 27, 2005Jul 8, 2008Intel CorporationMethod of fabricating a multi-cornered filmUS7449373Mar 31, 2006Nov 11, 2008Intel CorporationMethod of ion implanting for tri-gate devicesUS7456476Jun 27, 2003Nov 25, 2008Intel CorporationNonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabricationUS7479421Sep 28, 2005Jan 20, 2009Intel CorporationProcess for integrating planar and non-planar CMOS transistors on a bulk substrate and article made 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nanoscale channel transistorsUS7902014Jan 3, 2007Mar 8, 2011Intel CorporationCMOS devices with a single work function gate electrode and method of fabricationUS7915167Sep 29, 2005Mar 29, 2011Intel CorporationFabrication of channel wraparound gate structure for field-effect transistorUS7960794Dec 20, 2007Jun 14, 2011Intel CorporationNon-planar pMOS structure with a strained channel region and an integrated strained CMOS flowUS7989280Dec 18, 2008Aug 2, 2011Intel CorporationDielectric interface for group III-V semiconductor deviceUS8067818Nov 24, 2010Nov 29, 2011Intel CorporationNonplanar device with thinned lower body portion and method of fabricationUS8071457 *Jan 7, 2010Dec 6, 2011Globalfoundries Inc.Low capacitance precision resistorUS8071983May 8, 2009Dec 6, 2011Intel CorporationSemiconductor device structures and methods of forming semiconductor structuresUS8084818Jan 12, 2006Dec 27, 2011Intel CorporationHigh mobility tri-gate devices and methods of fabricationUS8183646Feb 4, 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CorporationField effect transistor with narrow bandgap source and drain regions and method of fabricationDE112006001589B4 *Jun 20, 2006Oct 25, 2012Intel CorporationVerfahren zur Bildung von HalbleiterstrukturenWO2003007384A2 *Jul 12, 2002Jan 23, 2003Univ North Carolina StateSingle-electron transistors and fabrication methodsWO2003007385A1 *Jul 12, 2002Jan 23, 2003Quantum Logic Devices IncSingle-electron transistors and fabrication methods in which a projecting feature defines spacing between electrodesWO2007002426A2 *Jun 20, 2006Jan 4, 2007Intel CorpSemiconductor device structures and methods of forming semiconductor structures* Cited by examinerClassifications U.S. Classification438/410, 438/701, 257/E21.404, 438/962, 257/E29.004International ClassificationH01L29/04, H01L21/335Cooperative ClassificationY10S438/962, H01L29/66439, H01L29/045, B82Y10/00European ClassificationB82Y10/00, H01L29/66M6T6D, H01L29/04BLegal EventsDateCodeEventDescriptionApr 18, 2008ASAssignmentOwner name: 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