Source: http://www.google.com/patents/US5802399?dq=4200770
Timestamp: 2017-02-22 13:19:03
Document Index: 444770813

Matched Legal Cases: ['art 910', 'art 910', 'art 910', 'art 920', 'art 920', 'art 920']

Patent US5802399 - Data transfer control unit for reducing memory requirements in an ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA data transfer control unit for controlling data transfer between a main processing part executing information processing and a memory part accessed by the main processing part has a bit width control part for controlling the bit width of the transferred data so that a first bit width of a port for...http://www.google.com/patents/US5802399?utm_source=gb-gplus-sharePatent US5802399 - Data transfer control unit for reducing memory requirements in an information processor by converting bit width of data being transferred between memory and processing partsAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS5802399 APublication typeGrantApplication numberUS 08/679,147Publication dateSep 1, 1998Filing dateJul 12, 1996Priority dateSep 22, 1995Fee statusPaidPublication number08679147, 679147, US 5802399 A, US 5802399A, US-A-5802399, US5802399 A, US5802399AInventorsManabu Yumoto, Tsuyoshi Muramatsu, Souichi MiyataOriginal AssigneeSharp Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (112), Classifications (6), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetData transfer control unit for reducing memory requirements in an information processor by converting bit width of data being transferred between memory and processing parts
It is assumed that the bit widths of the data transferred between the main processing part 910 and the RAM 903 are set at 12 bits and 8 bits on the main processing part 910 side and on the RAM 903 side respectively, and the number of words storable in the RAM 903 is set at 32 in the processor 900. In this case, the memory capacity of the RAM 903 is 32×8=256 bits. If the main processing part 910 is directly connected with the RAM 903 with no provision of the static data precision conversion processing part 920 in the processor 900, however, 12 bits are required for one word on the RAM 903 side and the necessary memory capacity is 384 bits. Namely, it comes to that the memory capacity required for the RAM 903 is reduced to 256/384=3/4 times as compared with the case of employing no static data precision conversion processing part 920, due to the employment of the processing part 920.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4837678 *Apr 7, 1987Jun 6, 1989Culler Glen JInstruction sequencer for parallel operation of functional unitsUS4947366 *Oct 2, 1987Aug 7, 1990Advanced Micro Devices, Inc.Input/output controller incorporating address mapped input/output windows and read ahead/write behind capabilitiesUS5548766 *Jun 7, 1995Aug 20, 1996Nec CorporationMicroprocessor for selecting data bus terminal width regardless of data transfer modeJPH06209504A * Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5941941 *Oct 3, 1997Aug 24, 1999Nec CorporationBit width controlling methodUS6311239 *Oct 29, 1998Oct 30, 2001Cypress Semiconductor Corp.Architecture, circuitry and method for transmitting n-bit wide data over m-bit wide mediaUS6414609Sep 10, 2001Jul 2, 2002Fujitsu LimitedData width conversion apparatus and data processing apparatusUS6606641 *Apr 20, 1998Aug 12, 2003Koninklijke Philips Electronics N.V.System for varying the dynamic range of coefficients in a digital filterUS7051194Mar 21, 2001May 23, 2006Sharp Kabushiki KaishaSelf-synchronous transfer control circuit and data driven information processing device using the sameUS7103702 *Jan 29, 2004Sep 5, 2006Fuji Photo Film Co., LtdMemory deviceUS7152131Dec 27, 2002Dec 19, 2006Renesas Technology Corp.Data processor having an access size control unitUS7171496 *Sep 24, 2003Jan 30, 2007Sharp Kabushiki KaishaData bus width conversion apparatus and data processing apparatusUS7259702 *Oct 14, 2005Aug 21, 2007Sanyo Electric Co., Ltd.Memory deviceUS7277975Nov 2, 2004Oct 2, 2007Sonics, Inc.Methods and apparatuses for decoupling a request from one or more solicited responsesUS7280539 *Jul 18, 2002Oct 9, 2007Sharp Kabushiki KaishaData driven type information processing apparatusUS7286067 *Feb 13, 2006Oct 23, 2007Sandisk Il Ltd.Appliance with communication protocol emulationUS7475168 *Mar 10, 2005Jan 6, 2009Sonics, Inc.Various methods and apparatus for width and burst conversionUS7515471Oct 19, 2006Apr 7, 2009Mosaid Technologies IncorporatedMemory with output controlUS7529149Dec 12, 2006May 5, 2009Mosaid Technologies IncorporatedMemory system and method with serial and parallel modesUS7543088 *Mar 10, 2005Jun 2, 2009Sonics, Inc.Various methods and apparatuses for width and burst conversionUS7620756 *Aug 21, 2006Nov 17, 2009International Business Machines CorporationMethod and apparatus for updating wide storage array over a narrow busUS7652922Dec 30, 2005Jan 26, 2010Mosaid Technologies IncorporatedMultiple independent serial link memoryUS7719892Jul 25, 2008May 18, 2010Mosaid Technologies IncorproatedFlash memory device with data output controlUS7747833Dec 22, 2006Jun 29, 2010Mosaid Technologies IncorporatedIndependent link and bank selectionUS7826294Nov 21, 2008Nov 2, 2010Mosaid Technologies IncorporatedMemory with output controlUS7885140Feb 15, 2008Feb 8, 2011Mosaid Technologies IncorporatedClock mode determination in a memory systemUS7904639Aug 17, 2007Mar 8, 2011Mosaid Technologies IncorporatedModular command structure for memory and memory systemUS7945755Apr 9, 2010May 17, 2011Mosaid Technologies IncorporatedIndependent link and bank selectionUS7957173Mar 11, 2009Jun 7, 2011Mosaid Technologies IncorporatedComposite memory having a bridging device for connecting discrete memory devices to a systemUS8000144Mar 26, 2010Aug 16, 2011Mosaid Technologies IncorporatedMethod and system for accessing a flash memory deviceUS8032676Nov 2, 2004Oct 4, 2011Sonics, Inc.Methods and apparatuses to manage bandwidth mismatches between a sending device and a receiving deviceUS8037235Dec 18, 2008Oct 11, 2011Mosaid Technologies IncorporatedDevice and method for transferring data to a non-volatile memory deviceUS8072819May 10, 2007Dec 6, 2011Semiconductor Components Industries, LlcMemory device with parallel interfaceUS8122202Aug 22, 2007Feb 21, 2012Peter GillinghamReduced pin count interfaceUS8134852Jul 31, 2009Mar 13, 2012Mosaid Technologies IncorporatedBridge device architecture for connecting discrete memory devices to a systemUS8139390Jul 8, 2008Mar 20, 2012Mosaid Technologies IncorporatedMixed data rates in memory devices and systemsUS8169849Mar 27, 2009May 1, 2012Mosaid Technologies IncorporatedMemory system and method with serial and parallel modesUS8194481Dec 17, 2009Jun 5, 2012Mosaid Technologies IncorporatedSemiconductor device with main memory unit and auxiliary memory unit requiring preset operationUS8199598Sep 15, 2010Jun 12, 2012Mosaid Technologies IncorporatedMemory with output controlUS8219778Feb 27, 2008Jul 10, 2012Microchip Technology IncorporatedVirtual memory interfaceUS8285960Mar 31, 2011Oct 9, 2012Mosaid Technologies IncorporatedIndependent link and bank selectionUS8363444Feb 3, 2012Jan 29, 2013Mosaid Technologies IncorporatedBridge device architecture for connecting discrete memory devices to a systemUS8407395Aug 22, 2007Mar 26, 2013Mosaid Technologies IncorporatedScalable memory systemUS8427897May 3, 2012Apr 23, 2013Mosaid Technologies IncorporatedMemory with output controlUS8432767Jan 13, 2011Apr 30, 2013Mosaid Technologies IncorporatedClock mode determination in a memory systemUS8521980Jul 16, 2009Aug 27, 2013Mosaid Technologies IncorporatedSimultaneous read and write data transferUS8549209Jul 24, 2009Oct 1, 2013Mosaid Technologies IncorporatedBridging device having a configurable virtual page sizeUS8582382May 19, 2010Nov 12, 2013Mosaid Technologies IncorporatedMemory system having a plurality of serially connected devicesUS8594110Jan 11, 2008Nov 26, 2013Mosaid Technologies IncorporatedRing-of-clusters network topologiesUS8644108Apr 26, 2013Feb 4, 2014Mosaid Technologies IncorporatedClock mode determination in a memory systemUS8654601Apr 22, 2013Feb 18, 2014Mosaid Technologies IncorporatedMemory with output controlUS8671252Feb 26, 2013Mar 11, 2014Mosaid Technologies IncorporatedScalable memory systemUS8737105Apr 21, 2011May 27, 2014Conversant Intellectual Property Management Inc.Bridge device architecture for connecting discrete memory devices to a systemUS8738879Sep 10, 2012May 27, 2014Conversant Intellectual Property Managament Inc.Independent link and bank selectionUS8743610Jun 29, 2011Jun 3, 2014Conversant Intellectual Property Management Inc.Method and system for accessing a flash memory deviceUS8812768Feb 19, 2008Aug 19, 2014Conversant Intellectual Property Management Inc.System having one or more memory devicesUS8825939Jun 18, 2008Sep 2, 2014Conversant Intellectual Property Management Inc.Semiconductor memory device suitable for interconnection in a ring topologyUS8825966Feb 2, 2012Sep 2, 2014Mosaid Technologies IncorporatedReduced pin count interfaceUS8825967Feb 21, 2012Sep 2, 2014Conversant Intellectual Property Management Inc.Independent write and read control in serially-connected devicesUS8843694Nov 22, 2011Sep 23, 2014Conversant Intellectual Property Management Inc.System and method of page buffer operation for memory devicesUS8880780Aug 23, 2011Nov 4, 2014Conversant Intellectual Property Management IncorporatedApparatus and method for using a page buffer of a memory device as a temporary cacheUS8886871Sep 30, 2011Nov 11, 2014Conversant Intellectual Property Management IncorporatedApparatus and method of page program operation for memory devices with mirror back-up of dataUS8898415Aug 8, 2013Nov 25, 2014Conversant Intellectual Property Management Inc.Simultaneous read and write data transferUS8902910Oct 18, 2013Dec 2, 2014Conversant Intellectual Property Management Inc.Ring-of-clusters network topologiesUS9013921Dec 5, 2013Apr 21, 2015Samsung Electronics Co., Ltd.Semiconductor memory deviceUS9021162 *Mar 20, 2012Apr 28, 2015Olympus CorporationData packet generation apparatus and data packet generation methodUS9230654Mar 8, 2013Jan 5, 2016Conversant Intellectual Property Management Inc.Method and system for accessing a flash memory deviceUS9240227Nov 8, 2006Jan 19, 2016Conversant Intellectual Property Management Inc.Daisy chain cascading devicesUS20010028629 *Mar 21, 2001Oct 11, 2001Takuji UneyamaSelf-synchronous transfer control circuit and data driven information processing device using the sameUS20030002474 *Mar 21, 2001Jan 2, 2003Thomas AlexanderMulti-stream merge network for data width conversion and multiplexingUS20030043837 *Jul 18, 2002Mar 6, 2003Shingo KamitaniData driven type information processing apparatusUS20030135684 *Dec 27, 2002Jul 17, 2003Makoto SaenData processor having an access size control unitUS20040064595 *Sep 24, 2003Apr 1, 2004Noriyuki TanakaData bus width conversion apparatus and data processing apparatusUS20040184306 *Jan 29, 2004Sep 23, 2004Fuji Photo Film Co., Ltd.Memory deviceUS20050210164 *Mar 10, 2005Sep 22, 2005Wolf-Dietrich WeberVarious methods and apparatuses for width and burst conversionUS20050216641 *Mar 10, 2005Sep 29, 2005Wolf-Dietrich WeberVarious methods and apparatus for width and burst conversionUS20060092944 *Nov 2, 2004May 4, 2006Wingard Drew EMethods and apparatuses to manage bandwidth mismatches between a sending device and a receiving deviceUS20060095635 *Nov 2, 2004May 4, 2006Vinogradov Glenn SMethods and apparatuses for decoupling a request from one or more solicited responsesUS20060123164 *Oct 14, 2005Jun 8, 2006Toshiki RaiMemory deviceUS20060195635 *Feb 13, 2006Aug 31, 2006M-Systems Flash Disk Pioneers, Ltd.Appliance with communication protocol emulationUS20070076479 *Dec 30, 2005Apr 5, 2007Mosaid Technologies IncorporatedMultiple independent serial link memoryUS20070153576 *Oct 19, 2006Jul 5, 2007Hakjune OhMemory with output controlUS20070216553 *May 10, 2007Sep 20, 2007Toshiki RaiMemory deviceUS20080049505 *Aug 22, 2007Feb 28, 2008Mosaid Technologies IncorporatedScalable memory systemUS20080126634 *Aug 21, 2006May 29, 2008International Business Machines CorporationMethod and apparatus for updating wide storage array over a narrow busUS20080137461 *Dec 12, 2006Jun 12, 2008Hong Beom PyeonMemory system and method with serial and parallel modesUS20080201496 *Aug 22, 2007Aug 21, 2008Peter GillinghamReduced pin count interfaceUS20080201548 *Feb 19, 2008Aug 21, 2008Mosaid Technologies IncorporatedSystem having one or more memory devicesUS20080201588 *Jan 23, 2008Aug 21, 2008Mosaid Technologies IncorporatedSemiconductor device and method for reducing power consumption in a system having interconnected devicesUS20080279003 *Jul 25, 2008Nov 13, 2008Mosaid Technologies IncorporatedMultiple independent serial link memoryUS20090039927 *Feb 15, 2008Feb 12, 2009Mosaid Technologies IncorporatedClock mode determination in a memory systemUS20090073768 *Nov 21, 2008Mar 19, 2009Mosaid Technologies IncorporatedMemory with output controlUS20090154284 *Jun 18, 2008Jun 18, 2009Hakjune OhSemiconductor memory device suitable for interconnection in a ring topologyUS20090185442 *Mar 27, 2009Jul 23, 2009Mosaid Technologies IncorporatedMemory system and method with serial and parallel modesUS20090216964 *Feb 27, 2008Aug 27, 2009Michael PalladinoVirtual memory interfaceUS20100011174 *Jul 8, 2008Jan 14, 2010Mosaid Technologies IncorporatedMixed data rates in memory devices and systemsUS20100091536 *Mar 11, 2009Apr 15, 2010Mosaid Technologies IncorporatedComposite memory having a bridging device for connecting discrete memory devices to a systemUS20100091538 *Jul 31, 2009Apr 15, 2010Mosaid Technologies IncorporatedBridge device architecture for connecting discrete memory devices to a systemUS20100115172 *Oct 28, 2009May 6, 2010Mosaid Technologies IncorporatedBridge device having a virtual page bufferUS20100115214 *Jul 24, 2009May 6, 2010Mosaid Technologies IncorporatedBridging device having a configurable virtual page sizeUS20100157715 *Dec 17, 2009Jun 24, 2010Hong-Beom PyeonSemiconductor device with main memory unit and auxiliary memory unit requiring preset operationUS20100161877 *Dec 18, 2008Jun 24, 2010Hong Beom PyeonDevice and method for transferring data to a non-volatile memory deviceUS20100182838 *Mar 26, 2010Jul 22, 2010Mosaid Technologies IncorporatedFlash memory device with data output controlUS20100199057 *Apr 9, 2010Aug 5, 2010Mosaid Technologies IncorporatedIndependent link and bank selectionUS20110002171 *Sep 15, 2010Jan 6, 2011Mosaid Technologies IncorporatedMemory with output controlUS20110016279 *Jul 16, 2009Jan 20, 2011Mosaid Technologies IncorporatedSimultaneous read and write data transferUS20110110165 *Jan 13, 2011May 12, 2011Mosaid Technologies IncorporatedClock mode determination in a memory systemUS20110131383 *Jan 28, 2011Jun 2, 2011Mosaid Technologies IncorporatedModular command structure for memory and memory systemUS20110179245 *Mar 31, 2011Jul 21, 2011Mosaid Technologies IncorporatedIndependent link and bank selectionUS20110194365 *Apr 21, 2011Aug 11, 2011Mosaid Technologies IncorporatedBridge device architecture for connecting discrete memory devices to a systemUS20110235426 *May 19, 2010Sep 29, 2011Mosaid Technologies IncorporatedFlash memory system having a plurality of serially connected devicesUS20120246360 *Mar 20, 2012Sep 27, 2012Olympus CorporationData processing apparatus and data processing methodCN101138158B *Feb 9, 2006May 4, 2016圣迪斯克以色列有限公司通信协议模拟装置EP1069512A2 *Jul 11, 2000Jan 17, 2001Matsushita Electric Industrial Co., Ltd.Data processing apparatus with buffering between busesEP1069512A3 *Jul 11, 2000Dec 15, 2004Matsushita Electric Industrial Co., Ltd.Data processing apparatus with buffering between busesWO2006085323A3 *Feb 9, 2006Apr 12, 2007Milsys LtdAppliance with communication protocol emulation* Cited by examinerClassifications U.S. Classification710/66International ClassificationG06F13/40, G06F12/04, G06F13/36Cooperative ClassificationG06F13/4018European ClassificationG06F13/40D1WLegal EventsDateCodeEventDescriptionJul 12, 1996ASAssignmentOwner name: SHARP KABUSHIKI KAISHA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YUMOTO, MANABU;MURAMATSU, TSUYOSHI;MIYATA, SOUICHI;REEL/FRAME:008102/0536Effective date: 19960624Feb 7, 2002FPAYFee paymentYear of fee payment: 4Feb 3, 2006FPAYFee paymentYear of fee payment: 8Jan 29, 2010FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services