Source: https://patents.google.com/patent/US20040098560?oq=6289460
Timestamp: 2018-03-22 08:56:19
Document Index: 751475939

Matched Legal Cases: ['ART1', 'ART 0', 'ART 0', 'ART 0', 'ART 1', 'ART 0', 'ART 1', 'ART0']

US20040098560A1 - Paging scheme for a microcontroller for extending available register space - Google Patents
Paging scheme for a microcontroller for extending available register space Download PDF
US20040098560A1
US20040098560A1 US10295721 US29572102A US2004098560A1 US 20040098560 A1 US20040098560 A1 US 20040098560A1 US 10295721 US10295721 US 10295721 US 29572102 A US29572102 A US 29572102A US 2004098560 A1 US2004098560 A1 US 2004098560A1
US10295721
US6898689B2 (en )
Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein. The one of the addressable memory locations associated with both the generated address in the at least a portion of the address space in the processing system and the page pointer is then accessed
The present invention pertains in general to systems for interfacing a processor with a peripheral device through special function registers and, more particularly, to a paging scheme to expand the I/O memory capability of a given processor to facilitate interfacing with a plurality of peripheral devices.
Processors are provided Special Function Registers (SFRs) that allow a processor to access control/configuration/status information for a particular peripheral device such as a Universal Asynchronous Receiver/Transmitter (UART), a Serial Port Interface (SPI), etc., or other resource To interface with each of these peripherals, or resources, the processor need only address the SFR associated with that peripheral device in order to provide configuration information, status information, control information, etc. for that particular peripheral device or to communicate with that particular peripheral device to forward information thereto or retrieve information therefrom so as to, for example, activate that peripheral device. One such product that utilizes SFRs to communicate with peripheral devices is a C8051 manufactured by Cygnal Integrated Products, the present assignee. The problem that exists with current products is that the processors have a finite address space for SFRs and, as such, are limited in the number of SFRs (and, as a result, resources/peripherals) that can be addressed and, thus, facilitated.
The present invention disclosed and claimed herein, in one aspect thereof, comprises a method for paging at least a portion of an address space in a processing system. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein. The one of the addressable memory locations associated with both the generated address in the at least a portion of the address space in the processing system and the page pointer is then accessed.
[0005]FIG. 1 illustrates an overall block diagram of an integrated circuit utilizing the paging scheme of the present disclosure;
[0006]FIG. 2 illustrates a diagrammatic view of the operation for interfacing between the CPU and the peripheral;
[0007]FIG. 3 illustrates a diagrammatic view of the address space for the pageable registers and the persistent registers;
[0008]FIG. 4 illustrates a more detailed diagrammatic view of the address space;
[0009]FIG. 5 illustrates a diagrammatic view of the operation of a persistent register;
[0010]FIG. 6 illustrates a block diagram of a persistent register;
[0011]FIG. 7 illustrates a detailed diagram of the address mapping for the paging pointer;
[0012]FIG. 8 illustrates a flowchart depicting the operation for configuring the SFRs on the different pages in memory;
[0013]FIG. 9 illustrates a flowchart depicting the run mode operation;
[0014]FIG. 10 illustrates a diagrammatic view of the page pointer stack;
[0015]FIG. 11 illustrates a diagrammatic view of an interrupt sequence operating in the CPU;
[0016]FIG. 12 illustrates a flowchart for the interrupt operation of the page pointer;
[0017]FIG. 13 illustrates a diagrammatic view of the page stack control;
[0018]FIG. 14 illustrates a block diagram of the page pointer stack;
[0020]FIG. 16 illustrates a flow chart for one example of the use of an interrupt service routine for two different resources.
Referring now to FIG. 1, there is illustrated a block diagram of system 102 for interfacing with a plurality of peripheral devices 104. Sometimes these peripheral devices 104 are referred to as system resources, as they provide an expansion of the capabilities of the overall system 102. The system 102 includes a central processing unit (CPU) 106 which is operable to interface through a bus connection 108 to an input/output device (1/0) 110 with the peripheral devices 104. The CPU 106 can be implemented with a microprocessor, a microcontroller unit or any type of processing device that has the capability of operating in an address space and generating addresses to Write or Read information to or from a storage device. The CPU 106 in the present embodiment has the ability to address through the bus 108 a finite number of addressable memory locations that exist within a defined CPU address space, typically limited by the width of the address bus. Each of the peripheral devices 104 has to be associated with an addressable location in addressable memory space. However, if the number of SFRs exceeds the number of available addressable memory locations, then the addressable memory space needs to be expanded. The J/0 device 110 of the present disclosure has the capability of addressing with more addressable memory locations than exist within CPU memory space, thus allowing more peripheral devices 104 to be accommodated. The I/O device has a paging function that is facilitated through control signals received from the CPU 106 through a paging interface 114 with the I/O device 110. Therefore, the CPU 106 can address the defined CPU address space in a conventional manner but provide control signals to the I/O device 110 to select different pages in an expanded address space, as will be described hereinbelow.
In operation, as will be described in more detail hereinbelow, the CPU 106 writes the page pointer to the SFR 210, the default being for page “0,”after which the page mapping device 204 then points to a different page. The CPU 106 will then run in its normal mode and access the peripheral device 104 in accordance with the normal operating mode program. For example, suppose that in the SFR address space the timer function for a UART, an existing peripheral device, was associated with an SFR address “88 h” in one example. To the program of CPU 106, this UART function will always be at that location in the SFR address space for a given page. If another UART were available, but associated with a different page, that particular function would be associated with that SFR at that address location “88 h” for that associated page. By merely changing the page pointer, a different UART is retrieved for access by the CPU 106, but the code that operates with any particular function of the UART need not be changed, as the address in SFR address space has not changed, just the page. With the paging scheme of the present disclosure, 256 pages of SFR address space can be accessed that will allow a large number of resources such as UARTs to be facilitated, each with a different configuration. As such, this will allow multiple UARTs, for example, to exist on different pages, each with a common SFR address on the associated page, and only the page pointer needs to be changed in order to select the particular UART. For example, if an SFR for a UART function were set at SFR address 88 h, the instruction coded need only concern itself with this address and not with the page, this allowing a common routine to be utilized for physically different but similar resources to be interfaced with, such as UARTs. This advantage will be described in more detail hereinbelow with respect to the handling of interrupts.
Referring now to FIG. 3, there is illustrated a diagrammatic view of the portion of the memory space occupied by the SFR registers. This portion of the memory space is associated with a plurality of registers, these registers being either pageable registers 302 or persistent registers 304. Pageable registers are registers that are accessible through both the address within the SFR address space and the page pointer. The persistent registers 304 occupy both the SFR space and the “page pointer space” which defines which page a register is present in. The persistent register constitutes a register that exists in the SFR space for all pages and does not change, i.e., it is the same hardware register. Persistent registers 304 alias to two or more (i.e., ALL) pages of the SFR address space. This will be described in more detail hereinbelow.
Referring now to FIG. 4, there is illustrated a diagrammatic view of the SFR register space. A plurality of pages of SFR register space are illustrated, each comprising a plurality of SFR registers R0, R1, . . . , RN. Each page contains the same number of registers which, in the present disclosure for the CPU 106 comprising an 8051 microprocessor, is 128 SFRs. By changing the page pointer, a different set of registers can be accessed in the address space. However, as will be described hereinbelow, there are certain ones of the registers that occupy different pages in the address space but are in effect the same physical hardware register, these referred to as “persistent” SFRs.
Referring now to FIG. 5, there is illustrated a diagrammatic view of two pages, PageX and PageY. PageX is illustrated by page 502 and PageY is illustrated by a page 504. Page 502 illustrates a single persistent register 506 that is disposed within the set of R0, R1, . . . , RN. This persistent register 506 is addressable by one of the SFR addresses. When the pointer is changed to that associated with the page 504, a different set of registers will be addressed. However, when the address of the persistent register in PageY is impressed upon the address bus, the same persistent register 506 will be accessed. One reason for having persistent registers is to facilitate the need for certain SFRs to remain the same regardless of the page. For example, there are accumulator SFRs that contain information that must “persist” between pages, i.e., they cannot change. Further, there are certain I/O functions that also persist and will have the same configuration or the same contents of the SFR regardless of the page. Additional information associated with the 8051 processor that is both stored in the SFR address space and is required for operation thereof regardless of the page are such things as the Data Pointer Low/High, Stack Pointer, Interrupt Enables, Accumulators, B-Register, etc. This eliminates the need to configure those registers for each page, such that a copy would exist on each page. If there were in fact a separate set of physical registers for each page, then the common registers would have to have information transferred therebetween for all operating modes and for all pages, i.e., they would have to maintain coherency therebetween. However, the system could operate without persistent SFRs, either by reproducing the information in each page or by program instructions that would result in returning to a default page for certain operations.
The address decoder 612 is a conventional combinatorial logic device that is operable to decode the address that is comprised of the SFR address and the page pointer as the eight Most Significant Bits (MSBs) to provide a concatenated address of {page pointer, SFR address}. In the present disclosure, the appropriate SFR is then selected by activating one of the plurality of select lines 206. The address decoder is hard coded to ignore the eight MSBs associated with the page pointer for all of the persistent SFRs, such that the same register is selected for all values of the page pointer, i.e., the same physical SFR exists on each page of SFR expanded memory space. However, it should be understood that a particular SFR could be rendered persistent as to only select pages in the SFR address space and not as to all pages. For example, “one SFR” could be persistent as to pages 0-6 in a ten page SFR address space, with separate physical SFRs associated with that “one SFR” address location provided for each of the remaining pages 7-9.
Referring now to FIG. 7, there is illustrated a block diagram of the overall system of the present disclosure. The pages of SFRs are illustrated by pages 702 that range in page number from “0” to “N.” Each SFR 208 is addressable from an address generated by a combination of an address in the SFR address space on bus 202 and the page pointer/address on bus 212 that was output from the page pointer SFR 210. The SFR addresses range from “0” to “N” (normalized to the first address) such that there are N+1 SFR addresses in the SFR address space of the CPU 106. There are M+1 pages of SFR addresses such that the total number of SFR addressable locations are (M+1) (N+1).
Many of the resources 708, in this embodiment, provides an interrupt to the CPU 106, these interrupts provided on separate interrupt lines 712. When the interrupt occurs, the CPU 106, operating in its normal mode, will service that interrupt. This results in the cessation of the normal operation of the CPU 106 and the execution of an interrupt handling service routine. Internal to the CPU 106, there is an interrupt “stack” that is operable to store the return address in the program, which address constitutes the location within the program to which the program returns after handling the interrupt. Further, interrupts have various priority levels. If, during the handling of a low priority interrupt, a high priority interrupt is received, this will result in interruption of that interrupt handling service routine to then launch an interrupt handling service routine for the higher priority interrupt. When the higher priority interrupt has been handled, this will return the program to continue handling the lower priority interrupt, after which the program will return to the point of the program where the original interrupt was encountered, i.e., return to the main program code execution. This will be described in more detail hereinbelow.
The page pointer SFR 210 is, in the present embodiment, comprised of a register file 1002 that comprises a last-in first-out (LIFO) register stack, this being a hardware stack (register file 1002 hereinafter referred to as a “stack”). This allows the page pointer associated with the interrupting source to be “pushed” onto the stack 1002 during the handling of the interrupt and, when the return instruction is received from the interrupt handling service routine in the CPU 106, the stack 1002 will be “popped.” This stack 1002 associated with the page pointer 210 is controlled by a page stack control block 714, which is a hardware stack control device. This page stack control block 714 is operable to interface with data such that it can receive a new page pointer to push onto the stack 1002, receive stack pointer control information from the CPU 106 through a bus 716 and also receive the interrupts on the interrupt lines 712. Interrupt vector information IVEC will also be received on a bus 1302, as will be described hereinbelow. The page stack control block 714 contains a lookup table (LUT) 718 that contains information as to page pointers for the various interrupt lines 712, each associated with one of the resources. The page stack control block 714 is operable to control the page pointer stack 1002 to either push the stack 1002 or pop the stack 1002 and also to load page pointer information therein via a bus 720. In the present embodiment, as will be described hereinbelow, the page pointer stack 1002 is three registers deep, each of the registers existing within the SFR space, i.e., each location in the stack 1002 occupies an addressable location within the SFR address space for each of the pages 702.
Referring now to FIG. 8, there is illustrated a flowchart depicting the original configuration operation of the CPU 106 for configuring SFRs. The program is initiated at a Start block 802 and then proceeds to a Configure block 804 wherein the system initiates a configuration operation wherein the SFRs are initially configured. The program flows to a function block 806 to set the page value initially to a default page value of “Page0.” The program then flows to a function block 808 to configure the SFR for that page and the particular SFR. In this block 808, all SFRs for a given page will be configured to the extent that configurable peripheral devices exist in association with that page. The program then flows to a decision block 810 to determine if the last page in the SFR address space has been configured. If not, then the program flows along the “N” path to a function block 812 to select the next page and then configures SFRs in that page. When the last page of the SFRs has been configured the program flows to an End block 814. It should be understood that the SFRs can be configured and reconfigured randomly also, it being noted that the SFRs may not need to be configured at all.
Referring now to FIG. 10, there is illustrated a block diagram of the stack 1002. As was described hereinabove, various interrupts can be received from the peripheral units 104 (also comprising resources 708), which can be serviced. When an interrupt is acknowledged, the page pointer for the page associated with the resource 708 or peripheral 104 that generated the interrupt will be determined and then the operation of the system in SFR address space is switched to the page associated with the resource 708, which associated interrupt was acknowledged. This requires the page pointer for that page. A lookup table (not shown) is accessed to determine the page pointer for that interrupt and then this page pointer stored in the page pointer SFR 210 by pushing it to the stack 1002. However, at the end of the interrupt service routine, it is necessary to restore code execution to the original page. This is facilitated automatically upon detecting a “Return from Interrupt” (RETI) instruction thereby popping the page pointer from the stack 1002.
There are provided in this stack 1002 the page pointer SFR 210, an intermediate SFR 1004 and a bottom SFR 1006. As will be described hereinbelow, there are two levels of priority that are facilitated by the stack 1002, because the CPU 106 handles two levels of priority, thus dictating the required depth of the stack 1002. If a low priority interrupt is initially received, the page pointer for the low priority interrupt will be pushed onto the stack 1002 and the original page pointer pushed down to the SFR 1004. If a high priority interrupt is then received, this will override the operation of the low priority interrupt and this high priority interrupt's page pointer will be pushed into SFR 210, the low priority interrupt page pointer pushed into the intermediate SFR 1004 and the original page pointer pushed into the SFR 1006 at the bottom. Each of these SFRs 210, 1004 and 1006 exist within the SFR address space and are persistent, i.e., they exist in all pages. Each of the SFRs 210, 1004 and 1006 are addressable with associated enable lines 206. Each of the SFR registers 210, 1004 and 1006 also interfaces with the data bus 203, such that page pointers can actually be inserted into the stack below the current page pointer. The stack 1002 can be “pushed” or “popped” and is cleared by a reset.
Referring now to FIG. 12, there is illustrated a flowchart depicting the operation of the stack 1002. The program is initiated at a block 1202 and then proceeds to a decision block 1204 to determine if an interrupt has occurred. If an interrupt has been acknowledged, the program flows along the “Y” path to a function block 1206 to determine if the interrupt is a high priority interrupt. If so, the program proceeds along the “Y” path to a decision block 1208 to determine if the current interrupt being serviced is a high priority interrupt. If so, this indicates that the received interrupt is on the same priority level as the interrupt currently being serviced, i.e., a high priority interrupt, and, if so, this interrupt must be queued. This will result in the program flowing along the “Y” path from the decision block 1208 to a function block 1210 where the interrupt is queued. However, if the current interrupt is not a high priority interrupt, i.e., it is either operating on the current pointer associated with the main program code or it is servicing a low priority interrupt, the program will flow along the “N” path to a function block 1212 wherein the stack is pushed such that the received interrupt is serviced with the pointer associated with the interrupting resource. The program then flows to a function block 1214 to service the interrupt and then to a decision block 1216 to determine if the interrupt service routine for the interrupt has completed, this being indicated by the generation of a Return Interrupt Signal (RETI). If not, the program will flow along the “N” path back to the input of function block 1214 to continue servicing the interrupt. When the RETI signal is received, the program will flow from the decision block 1216 along a “Y” path to a function block 1218 to pop the stack.
When it was determined that the receive interrupt was not a high priority interrupt at decision block 1206, the program will flow from the decision block 1206 along the “N” path to a decision block 1220 to determine if the system is currently servicing an interrupt, this being indicated by the stack being pushed down at least one level and, if so, this will indicate that a low priority interrupt is being serviced which is on the same level as the received interrupt, resulting in the program flowing along the “Y” path to a function block 1222 to queue the interrupt. If an interrupt is not being serviced, the program will flow along the “N” path from decision block 1220 to the input of function block 1212 where the page pointer is pushed onto the stack.
After the interrupt has been serviced (noting that this operation includes a plurality of steps), the program will flow from the function block 1218 where the stack was popped to a decision block 1224 where a decision will be made as to whether there are any high priority interrupts in the queue. This, of course, would have been the situation if the previous interrupt being serviced were associated with a high priority interrupt when a high priority interrupt is received. If there are other high priority interrupts in the queue, i.e., these received during the servicing of the current high priority interrupt, the program will flow along the “Y” path to fetch the high priority interrupt in the queue, this indicated in a function block 1226, and then to the input of the function block 1212 to push the page pointer associated with the high priority interrupt onto the stack. If there are no high priority interrupts in the high priority interrupt queue, then the program will flow along the “N” path from the decision block 1224 to a decision block 1228 to determine if there are any low priority interrupts in the low priority interrupt queue. If so, the program flows along the “Y” path to the function block 1212 in order to push the next low priority interrupt onto the stack, it being noted that the low priority interrupts will be serviced in the order they were received. If no more interrupts are in the high priority or low priority interrupt queues, then the program will flow along the “N” path from the decision block 1228 to a Return block 1232.
CPU signals “sp_int” & “sp_reti” are qualified to produce
Special function register “SFR_PAGE” is the access port to RFILE_0
or the “TOP” of the SFR page stack. This value always reflects the
interrupt vector lines “cpu_ivec” are decoded and the SFR page,
“SFR page stack”
“will NOT” cause a coincident stack push/pop.
input scan_en; // scan shift enable
input rst; // asynchronous reset
input clk; // chip clock
input [7:0] sfrpage_d; // sfrpage “d-term”
input sfr_wr; // sfr write strobe
input [7:0] sfr_wdata; // sfr write data
input sfr_sfrpgcn_rs; // sfr page control register select
output [7:0] sfr_sfrpgcn_rdata; // sfr page control read data
input sfr_sfrpage_rs; // sfr page register select
output [7:0] sfr_sfrpage_rdata; // sfr page read data
input sfr_sfrnext_rs; // sfr next register select
output [7:0] sfr_sfrnext_rdata; // sfr next read data
input sfr_sfrlast_rs; // sfr last register select
output [7:0] sfr_sfrlast_rdata; // sfr last read data
input sp_reti; // decrement stack pointer register
input sp_int; // increment stack pointer register
input dbi_active; // DBI indicator
wire [7:0] sfr_sfrpage_rdata, // sfrpage register read data
sfr_sfrnext_rdata, // sfrnext register read data
sfr_sfrlast_rdata; // sfrlast register read data
wire [7:0] rfile_0, // TOP ---- of stack
rfile_1, //
rfile_2; // BOTTOM - of stack
wire sp_int_q, //
sp_reti_q; //
wire sfrpage_enable; // sfr page enable
// SFR Page Control SFR - power on reset = “enabled”
// Signals “sp_int” and “sp_reti” are 2 clocks long.
// We need to make a one-clock long pulse.
wire page_stack_push = sp_int & ˜sp_int_q & ˜dbi_active;
wire page_stack_pop = sp_reti & ˜sp_reti_q ˜dbi_active;
page_stack_push ? sfrpage_d : rfile_1;
page_stack_push ? rfile_0 : rfile_2;
page_stack_push ? rfile_1 : 8′h00;
// interrupt vector lines “cpu_ivec” are decoded and the SFR page,
wire [15:0] cpu_ivec; // CPU interrupt vector input
reg [7:0] sfrpage_d; //
8′h63 :sfrpage_d = 8′h03; // CP2
8′hab :sfrpage_d = 8′h03; // DMA
8′h5b :sfrpage_d = 8′h02; // CP1
8′h83 :sfrpage_d = 8′h02; // T4
8′h8b :sfrpage_d = 8′h02; // adc2 WINT (SAR 08)
8′h93 :sfrpage_d = 8′h02; // adc2 CINT (SAR 08)
8′h53 :sfrpage_d = 8′h01; // CP0 FIF
8′h73 :sfrpage_d = 8′h01; // T3
8′h7b :sfrpage_d = 8′h01; // adc1 CINT (SAR 16 slave)
8′h9b :sfrpage_d = 8′h01; // CAN
8′ha3 :sfrpage_d = 8′h01; // UART1
default: sfrpage_d = 8′h00; // all other resources
When an interrupt is acknowledged, the table lookup block 1303 will index the appropriate page pointer or value (from table 1304) with the interrupt vector (1302) and place it onto bus 1306. A page stack control block 1340 determines when to push or pop the “page pointer stack” based on the CPU 106 “software stack” information. When it pushes the page stack, this is indicative that the interrupt has been acknowledged. At the end of the interrupt service routine for the interrupt, the RETI instruction will be generated and a pop operation indicated that will pop the page stack. When an interrupt is not being serviced, multiplexer 1312 is operable to receive on the other input thereof the data for input to the page pointer SFR 210 such that any of the registers 210, 1320 or 1322 can be written to. There are situations where it is desirable to write information into the SFRs 1320 and 1322, these being user defined options. Although they are not utilized for the normal stack operation, they can be facilitated, since all of the SFR locations are writeable and readable locations.
Referring now to FIG. 14, there is illustrated a schematic diagram of one embodiment of the page stack 1002. Each of the registers 210, 1004 and 1006 are comprised of a plurality of D-type flip flops 1402. The flip flops 1402 for only the first bit, the “0”bits, are illustrated. Each of the D-inputs has associated therewith a multiplexer 1404 that has four inputs. The first input is for the page pointer to be pushed. The second input is for CPU SFR data Writes from the SFR data bus. The third input is connected to the Q-output of the D flip flop 1402 from the next adjacent register. In this example, the multiplexer 1404 illustrated as associated with page pointer SFR 210 has a third input thereof connected to the Q-output of flip flop 1402 associated with SFR 1004. The fourth input of multiplexer 1404 is connected to the Q-output of flip flop 1402 within the associated SFR to associate directly with multiplexer 1404 to provide a Hold path. The third input is utilized for the pop operation wherein the data from the adjacent register is clocked into the flip flop 1402 and the fourth input is utilized for a hold operation wherein the data of a particular flip flop 1402 is clocked back onto itself.
Register Address SFR Page Description
ACC 0xE0 All Pages Accumulator
ADC0CF 0xBC 0 ADC0 Configuration
ADC0CN 0xE8 0 ADC0 Control
ADC0GTH 0xC5 0 ADC0 Greater-Than High
ADC0GTL 0xC4 0 ADC0 Greater-Than Low
ADC0H 0xBF 0 ADC0 Data Word High
ADC0L 0xBE 0 ADC0 Data Word Low
ADC0LTH 0xC7 0 ADC0 Less-Than High
ADC0LTL 0xC6 0 ADC0 Less-Than Low
ADC2 0xBE 2 ADC2 Data Word
ADC2CF 0xBC 2 ADC2 Analog Multiplexer Configuration
ADC2CN 0xE8 2 ADC2 Control
ADC2GT 0xC4 1 ADC2 Window Comparator Greater-Than
ADC2LT 0xC6 1 ADC2 Window Comparator Less-Than
AMX0CF 0xBA 0 ADC0 Multiplexer Configuration
AMX0PRT 0xBD 0 ADC0 Port 3 I/O Pin Select
AMX0SL 0xBB 0 ADC0 Multiplexer Channel Select
AMX2SL 0xBB 2 ADC2 Analog Multiplexer Channel Select
B 0xF0 All Pages B Register
CAN0ADR 0xDA 1 CAN0 Address
CAN0CN 0xF8 1 CAN0 Control
CAN0DATH 0xD9 1 CAN0 Data Register High
CAN0DATL 0xD8 1 CAN0 Data Register Low
CAN0STA 0xC0 1 CAN0 Status
CAN0TST 0xDB 1 CAN0 Test Register
CKCON 0x8E 0 Clock Control
CLKSEL 0x97 F Oscillator Clock Selection Register
CPT0MD 0x89 1 Comparator 0 Mode Selection
CPT1MD 0x89 2 Comparator 1 Mode Selection
CPT2MD 0x89 3 Comparator 2 Mode Selection
CPT0CN 0x88 1 Comparator 0 Control
CPT1CN 0x88 2 Comparator 1 Control
CPT2CN 0x88 3 Comparator 2 Control
DAC0CN 0xD4 0 DAC0 Control
DAC0H 0xD3 0 DAC0 High
DAC0L 0xD2 0 DAC0 Low
DAC1CN 0xD4 1 DAC1 Control
DAC1H 0xD3 1 DAC1 High Byte
DAC1L 0xD2 1 DAC1 Low Byte
DPH 0x83 All Pages Data Pointer High
DPL 0x82 All Pages Data Pointer Low
EIE1 0xE6 All Pages Extended Interrupt Enable 1
EIE2 0xE7 All Pages Extended Interrupt Enable 2
EIP1 0xF6 All Pages Extended Interrupt Priority 1
EIP2 0xF7 All Pages Extended Interrupt Priority 2
EMI0CF 0xA3 0 EMIF Configuration
EMI0CN 0xA2 0 External Memory Interface Control
EMI0TC 0xA1 0 EMIF Timing Control
FLACL 0xB7 F FLASH Access Limit
FLSCL 0xB7 0 FLASH Scale
HVA0CN 0xD6 0 High Voltage Differential Amp Control
IE 0xA8 All Pages Interrupt Enable
IP 0xB8 All Pages Interrupt Priority
OSCICL 0x8B F Internal Oscillator Calibration
OSCICN 0x8A F Internal Oscillator Control
OSCXCN 0x8C F External Oscillator Control
P0 0x80 All Pages Port 0 Latch
P0MDOUT 0xA4 F Port 0 Output Mode Configuration
P1 0x90 All Pages Port 1 Latch
P1MDIN 0xAD F Port 1 Input Mode Configuration
P1MDOUT 0xA5 F Port 1 Output Mode Configuration
P2 0xA0 All Pages Port 2 Latch
P2MDIN 0xAE F Port 2 Input Mode Configuration
P2MDOUT 0xA6 F Port 2 Output Mode Configuration
P3 0xB0 All Pages Port 3 Latch
P3MDIN 0xAF F Port 3 Input Mode Configuration
P3MDOUT 0xA7 F Port 3 Output Mode Configuration
†P4 0xC8 F Port 4 Latch
†P4MDOUT 0x9C F Port 4 Output Mode Configuration
†P5 0xD8 F Port 5 Latch
†P5MDOUT 0x9D F Port 5 Output Mode Configuration
†P6 0xE8 F Port 6 Latch
†P6MDOUT 0x9E F Port 6 Output Mode Configuration
†P7 0xF8 F Port 7 Latch
†P7MDOUT 0x9F F Port 7 Output Mode Configuration
PCA0CN 0xD8 0 PCA Control
PCA0CPH0 0xFC 0 PCA Capture 0 High
PCA0CPH1 0xFE 0 PCA Capture 1 High
PCA0CPH2 0xEA 0 PCA Capture 2 High
PCA0CPH3 0xEC 0 PCA Capture 3 High
PCA0CPH4 0xEE 0 PCA Capture 4 High
PCA0CPH5 0xE2 0 PCA Capture 5 High
PCA0CPL0 0xFB 0 PCA Capture 0 Low
PCA0CPL1 0xFD 0 PCA Capture 1 Low
PCA0CPL2 0xE9 0 PCA Capture 2 Low
PCA0CPL3 0xEB 0 PCA Capture 3 Low
PCA0CPL4 0xED 0 PCA Capture 4 Low
PCA0CPL5 0xE1 0 PCA Capture 5 Low
PCA0CPM0 0xDA 0 PCA Module 0 Mode Register
PCA0CPM1 0xDB 0 PCA Module 1 Mode Register
PCA0CPM2 0xDC 0 PCA Module 2 Mode Register
PCA0CPM3 0xDD 0 PCA Module 3 Mode Register
PCA0CPM4 0xDE 0 PCA Module 4 Mode Register
PCA0CPM5 0xDF 0 PCA Module 5 Mode Register
PCA0H 0xFA 0 PCA Counter High
PCA0L 0xF9 0 PCA Counter Low
PCA0MD 0xD9 0 PCA Mode
PCON 0x87 All Pages Power Control
PSCTL 0x8F 0 Program Store R/W Control
PSW 0xD0 All Pages Program Status Word
RCAP2H 0xCB 0 Timer/Counter 2 Capture/Reload High
RCAP2L 0xCA 0 Timer/Counter 2 Capture/Reload Low
RCAP3H 0xCB 1 Timer/Counter 3 Capture/Reload High
RCAP3L 0xCA 1 Timer/Counter 3 Capture/Reload Low
RCAP4H 0xCB 2 Timer/Counter 4 Capture/Reload High
RCAP4L 0xCA 2 Timer/Counter 4 Capture/Reload Low
REF0CN 0xD1 0 Programmable Voltage Reference Control
RSTSRC 0xEF 0 Reset Source Register
SADDR0 0xA9 0 UART 0 Slave Address
SADEN0 0xB9 0 UART 0 Slave Address Enable
SBUF0 0x99 0 UART 0 Data Buffer
SBUF1 0x99 1 UART 1 Data Buffer
SCON0 0x98 0 UART 0 Control
SCON1 0x98 1 UART 1 Control
SFRPAGE 0x84 All Pages SFR Page Register
SFRPGCN 0x96 F SFR Page Control Register
SFRNEXT 0x85 All Pages SFR Next Page Stack Access Register
SFRLAST 0x86 All Pages SFR Last Page Stack Access Register
SMB0ADR 0xC3 0 SMBus Slave Address
SMB0CN 0xC0 0 SMBus Control
SMB0CR 0xCF 0 SMBus Clock Rate
SMB0DAT 0xC2 0 SMBus Data
SMB0STA 0xC1 0 SMBus Status
SP 0x81 All Pages Stack Pointer
SPI0CFG 0x9A 0 SPI Configuration
SPI0CKR 0x9D 0 SPI Clock Rate Control
SPI0CN 0xF8 0 SPI Control
SPI0DAT 0x9B 0 SPI Data
SSTA0 0x91 0 UART0 Status and Clock Selection
TCON 0x88 0 Timer/Counter Control
TH0 0x8C 0 Timer/Counter 0 High
TH1 0x8D 0 Timer/Counter 1 High
TL0 0x8A 0 Timer/Counter 0 Low
TL1 0x8B 0 Timer/Counter 1 Low
TMOD 0x89 0 Timer/Counter Mode
TMR2CF 0xC9 0 Timer/Counter 2 Configuration
TMR2CN 0xC8 0 Timer/Counter 2 Control
TMR2H 0xCD 0 Timer/Counter 2 High
TMR2L 0xCC 0 Timer/Counter 2 Low
TMR3CF 0xC9 1 Timer/Counter 3 Configuration
TMR3CN 0xC8 1 Timer 3 Control
TMR3H 0xCD 1 Timer/Counter 3 High
TMR3L 0xCC 1 Timer/Counter 3 Low
TMR4CF 0xC9 2 Timer/Counter 4 Configuration
TMR4CN 0xC8 2 Timer/Counter 4 Control
TMR4H 0xCD 2 Timer/Counter 4 High
TMR4L 0xCC 2 Timer/Counter 4 Low
WDTCN 0xFF All Pages Watchdog Timer Control
XBR0 0xE1 F Port I/O Crossbar Control 0
XBR1 0xE2 F Port I/O Crossbar Control 1
XBR2 0xE3 F Port I/O Crossbar Control 2
XBR3 0xE4 F Port I/O Crossbar Control 3
providing a plurality of addressable memory locations arranged in pages, each of the addressable memory locations in each of the pages occupying at least a portion of the address space of the processing system and having an associated address in the address space of the processing system;
storing a page pointer;
generating an address in the at least a portion of the address space of the processing system;
at least one of the addressable memory locations in at least two of the pages having the same address and having identical information stored therein; and
accessing the one of the addressable memory locations associated with both the generated address in the at least a portion of the address space in the processing system and the page pointer.
2. The method of claim 1 wherein the step of storing the page pointer comprises the step of storing the page pointer in one of the addressable memory locations in each of the pages having the same address such that the step of generating an address generates the address of the one of the addressable memory locations and the step accessing the one of the addressable memory locations is operable to access the page pointer regardless of the value of the page pointer.
providing a physical pointer memory device;
storing the page pointer in the physical page pointer memory device; and
designating the physical page pointer memory device as one of the plurality of addressable memory locations in each of the pages.
4. The method of claim 1 and further comprising the step of providing a plurality of physical memory devices and associating each of the plurality of physical memory devices with one of the plurality of addressable memory locations in the at least a portion of the address space in the processing system and one of the pages.
7. The method of claim 4 wherein the step of storing the page pointer comprises the step of storing the page pointer in one of the addressable memory locations in each of the pages and having the same address such that the step of generating an address generates the address of the one of the addressable memory locations and the step accessing the one of the addressable memory locations is operable to access the page pointer regardless of the value of the page pointer.
designating the physical page pointer memory device as one of a plurality of addressable memory locations in each of the pages.
9. The method of claim 1, and further comprising the step of changing the value of the stored page pointer to a new value such that a different page of the addressable memory locations is accessed by the step of accessing.
a plurality of addressable memory locations arranged in pages, each of said addressable memory locations in each of said pages occupying at least a portion of the processor address space and having an associated address in the processor address space;
a page pointer stored in a storage location;
an address generator for generating an address in the at least a portion of the processor address space;
at least one of said addressable memory locations in at least two of said pages having the same address and having identical information stored therein; and
memory access device for accessing the one of the addressable memory locations associated with both said generated address in the at least a portion of the processor address space and said page pointer.
13. The processing system of claim 12 wherein said storage location comprises one of the addressable memory locations in each of said pages having the same address such that address generator generates the address of the one of the addressable memory locations and memory access device is operable to access said page pointer regardless of the value of said page pointer.
said storage location comprises a physical pointer memory device; and
said physical page pointer memory device designated as one of the plurality of addressable memory locations in each of said pages.
15. The processing system of claim 12 and further comprising a plurality of physical memory devices and each of said plurality of physical memory devices associated with one of the plurality of addressable memory locations in the at least a portion of the processor address space and one of said pages.
said physical page pointer memory device is designated as one of a plurality of addressable memory locations in each of said pages.
20. The processing system of claim 12, and further comprising a page controller for changing the value of said stored page pointer to a new value such that a different page of the addressable memory locations is accessed by said memory access device.
22. The processing system of claim 21, wherein said page controller is operable change the value of said pointer at the top of said register stack to the previous value by popping said register stack.
US10295721 2002-11-15 2002-11-15 Paging scheme for a microcontroller for extending available register space Active 2023-08-07 US6898689B2 (en)
US10295721 US6898689B2 (en) 2002-11-15 2002-11-15 Paging scheme for a microcontroller for extending available register space
US20040098560A1 true true US20040098560A1 (en) 2004-05-20
US6898689B2 US6898689B2 (en) 2005-05-24
ID=32297284
US10295721 Active 2023-08-07 US6898689B2 (en) 2002-11-15 2002-11-15 Paging scheme for a microcontroller for extending available register space
US (1) US6898689B2 (en)
US6898689B2 (en) 2005-05-24 grant
US7171542B1 (en) 2007-01-30 Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:STORVIK, ALVIN C., II;FERNALD, KENNETH W.;HIGHLEY, PAUL;AND OTHERS;REEL/FRAME:013505/0494