Source: http://www.google.com/patents/US20060125113?ie=ISO-8859-1
Timestamp: 2015-01-27 08:27:10
Document Index: 308250441

Matched Legal Cases: ['art 211', 'art 211', 'art 211', 'art 211', 'art 211', 'art 211', 'art 211', 'art 213']

Patent US20060125113 - Flip chip package with anti-floating structure - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA flip chip package with an anti-floating structure comprises a leadframe, a flip chip, and a plurality of solders. The leadframe comprises a plurality of leads and a fastening part. At least one locking hole is formed on an upper surface of the fastening part. The flip chip comprises an active surface,...http://www.google.com/patents/US20060125113?utm_source=gb-gplus-sharePatent US20060125113 - Flip chip package with anti-floating structureAdvanced Patent SearchPublication numberUS20060125113 A1Publication typeApplicationApplication numberUS 11/296,489Publication dateJun 15, 2006Filing dateDec 8, 2005Priority dateDec 14, 2004Also published asUS7368806, US20080179739Publication number11296489, 296489, US 2006/0125113 A1, US 2006/125113 A1, US 20060125113 A1, US 20060125113A1, US 2006125113 A1, US 2006125113A1, US-A1-20060125113, US-A1-2006125113, US2006/0125113A1, US2006/125113A1, US20060125113 A1, US20060125113A1, US2006125113 A1, US2006125113A1InventorsChien Liu, Meng-Jen Wang, Sheng-Tai TsaiOriginal AssigneeChien Liu, Meng-Jen Wang, Sheng-Tai TsaiExport CitationBiBTeX, EndNote, RefManReferenced by (7), Classifications (39), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetFlip chip package with anti-floating structureUS 20060125113 A1Abstract A flip chip package with an anti-floating structure comprises a leadframe, a flip chip, and a plurality of solders. The leadframe comprises a plurality of leads and a fastening part. At least one locking hole is formed on an upper surface of the fastening part. The flip chip comprises an active surface, and at least one locking protrusion and a plurality of bumps formed on the active surface. The locking protrusion is correspondingly plugged into the locking hole to act as an anti-floating structure for the flip chip package. When the solders are used for connecting the bumps with the leads by reflowing, the anti-floating structure will prevent the flip chip from floating up, and the solders will not generate necking after reflowing. Images(4) Claims(20)
1. A flip chip package with an anti-floating structure, comprising: a leadframe having a plurality of leads and a fastening part, the fastening part having at least one locking hole; a flip chip having an active surface and at least one locking protrusion, the locking protrusion and a plurality of bumps being formed on the active surface, the locking protrusion being plugged into the locking hole of the fastening part; and a plurality of solders for connecting the bumps to the leads. 2. The flip chip package according to claim 1, wherein the locking hole comprises a notch. 3. The flip chip package according to claim 1, wherein the outside diameter of the locking protrusion is slightly larger than that of the locking hole. 4. The flip chip package according to claim 1, wherein the locking protrusion is used for grounding or thermal conducting. 5. The flip chip package according to claim 1, wherein the height of the locking protrusion is larger than that of the bumps. 6. The flip chip package according to claim 1, further comprising a molding compound for sealing the bumps and the locking protrusion. 7. The flip chip package according to claim 6, wherein the fastening part comprises a lower surface exposed outside the molding compound. 8. The flip chip package according to claim 6, wherein each of the leads comprises a lower surface exposed outside the molding compound. 9. The flip chip package according to claim 1, further comprising a bonding agent applied into the locking hole, so as to fix the locking protrusion with the locking hole. 10. A flip chip package with an anti-floating structure, comprising: a chip carrier having an upper surface, a lower surface, a plurality of contacts and at least one locking hole, the contacts being exposed at the upper surface and the locking hole being exposed at the upper surface; a flip chip having an active surface, at least one locking protrusion and a plurality of bumps, the locking protrusion and the bumps being formed on the active surface, the locking protrusion being plugged into the locking hole; and a plurality of solders for connecting the bumps to the contacts. 11. The flip chip package according to claim 10, wherein the chip carrier is a circuit substrate. 12. The flip chip package according to claim 11, wherein the chip carrier comprises a dielectric layer and a copper layer, the dielectric layer having at least one first hole, and the copper layer being formed on the dielectric layer and having at least one second hole aligned with the first hole, thereby forming the locking hole. 13. The flip chip package according to claim 12, wherein the aperture of the second hole of the copper layer is smaller than that of the first hole of the dielectric layer. 14. The flip chip package according to claim 10, wherein the outside diameter of the locking protrusion is slightly larger than the size of the locking hole. 15. The flip chip package according to claim 10, wherein the locking protrusion is used for grounding or thermal conducting. 16. The flip chip package according to claim 10, wherein the height of the locking protrusion is larger than that of the bumps. 17. The flip chip package according to claim 10, further comprising a molding compound for sealing the bumps and the locking protrusion. 18. The flip chip package according to claim 10, further comprising a bonding agent applied into the locking hole, so as to fix the locking protrusion to the locking hole. 19. The flip chip package according to claim 10, wherein the locking protrusion is formed at the center of the active surface of the flip chip. 20. The flip chip package according to claim 10, wherein the locking protrusion is formed at the periphery or corner of the active surface of the flip chip.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip package, and more particularly to a flip chip package with an anti-floating structure, which facilitates the solder to connect the bumps of a flip chip with a leadframe. 2. Description of the Related Art In the recent development of packaging technique, the flip chip package has become the current focus. A conventional flip chip package is used to flip-chip bond a chip to a leadframe, so as to reduce the package cost. As disclosed in ROC Patent Publication No. 567598, entitled �Flip Chip Package of Semiconductor Chips�, it comprises a leadframe, a semiconductor chip, a plurality of first bumps, and a plurality of second bumps. The leadframe comprises a die pad and a plurality of leads. The semiconductor chip comprises an active surface and a back surface opposite to the active surface on which a plurality of first solder pads and second solder pads are formed. The first bumps and the second bumps are disposed on the corresponding first solder pads and second solder pads respectively, so that the semiconductor chip becomes a flip chip. The semiconductor chip is arranged with the active surface facing the leadframe, and the first bumps and the second bumps are connected to the die pad and the leads, respectively. However, since the first bumps and the second bumps are low temperature eutectic bumps so as to be soldered to the leads, when they are soldered to the die pad and the leads, the leads of the leadframe do not have a solder mask to define the soldering area, and the heights of the first bumps and the second bumps will thus be affected by collapse and diffusion. Referring to FIGS. 1 and 2, another conventional bonding method that is to bond the high-temperature bumps of a flip chip to a leadframe through the solder is disclosed. The conventional flip chip package 100 mainly comprises a leadframe 110, a flip chip 120, and a plurality of eutectic solders 130. The leadframe 110 comprises a plurality of leads 111 that comprise the eutectic solders 130 formed beforehand. The flip chip 120 comprises a plurality of high temperature bumps 121, e.g., high lead bumps, such as lead/tin 95/5, so that the high lead bumps 121 will not be melted during reflowing of the eutectic solders 130, thus avoiding the collapse and diffusion of the bumps 121. Referring to FIG. 2, the eutectic solders 130 are used for soldering the high temperature bumps 121 of the flip chip 120 to the leads 111 of the leadframe 110. During the process of reflowing, the flip chip 120 may always float up because of the surface tension of the eutectic solders 130, such that the solders 130 may form a necking portion 131 at one side near the leadframe 110 after reflowing. Therefore, the stress is easily concentrated on the necking portion 131, which may easily break off. Consequently, there is an existing need for a flip chip package with an anti-floating structure to solve the above-mentioned problems. SUMMARY OF THE INVENTION An objective of the present invention is to provide a flip chip package with an anti-floating structure. A leadframe comprises a plurality of leads and a fastening part. The fastening part comprises at least one locking hole. A flip chip comprises a plurality of bumps and at least one locking protrusion. When the bumps of the flip chip are bonded with the leads of the leadframe through a plurality of solders, the locking protrusion is correspondingly plugged into the locking hole to act as anti-floating structure for the flip chip package. The anti-floating structure is used for fastening the flip chip to the leadframe, so as to prevent the flip chip from floating up when reflowing, and the solders will not generate necking after reflowing. Another objective of the present invention is to provide a flip chip package with an anti-floating structure, wherein a bonding agent is applied into the locking hole to fasten the locking protrusion to the locking hole. Therefore when the solders are used to connect the bumps with the leads, the flip chip may be prevented from floating up, and the solders will not generate necking after reflowing. The flip chip package with an anti-floating structure according to the present invention comprises a leadframe, a flip chip, and a plurality of solders, wherein the leadframe comprises a plurality of leads and a fastening part. The fastening part comprises at least one locking hole. The flip chip comprises an active surface and at least one locking protrusion and a plurality of bumps formed on the active surface. The locking protrusion is plugged into the locking hole, and the solders are used for connecting the leads with the bumps.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic sectional view of a conventional flip chip package when being flip-chip bonded; FIG. 2 is a schematic sectional view of a conventional flip chip package when generating necking of the solders after being flip-chip bonded; FIG. 3 is a schematic sectional view of a flip chip package with an anti-floating structure when being flip-chip bonded according to a first embodiment of the present invention; FIG. 4 is a schematic sectional view of a flip chip package with an anti-floating structure after being molded according to the first embodiment of the present invention; and FIG. 5 is a schematic sectional view of a flip chip package with an anti-floating structure according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following embodiments, with reference to the accompanying drawings. Referring to FIGS. 3 and 4, according to a first embodiment of the present invention, a flip chip package 200 with an anti-floating structure comprises a leadframe 210, a flip chip 220, a plurality of solders 230, and a molding compound 240. The leadframe 210 comprises a fastening part 211 and a plurality of leads 212. The fastening part 211 has an upper surface 213 and a lower surface 214, and is smaller than the flip chip 220. The fastening part 211 may be rectangular plate shaped or strip shaped. The upper surface 213 of the fastening part 211 comprises at least one locking hole 215. Preferably, the fastening part 211 comprises a plurality of symmetrically distributed locking holes 215, which are formed by semi-etching process, and each of the locking holes 215 has a notch. Each lead 212 comprises an upper surface 216 and a lower surface 217. The flip chip 220 comprises an active surface 221 and at least one locking protrusion 222. The locking protrusion 222 and a plurality of bumps 223 are formed on the active surface 221. In this embodiment, the locking protrusion 222 is located at the center portion of the active surface 221, whereas the bumps 223 are located at the periphery of the active surface 221. The outside diameter of the locking protrusion 222 is slightly larger than the size of the locking hole 215, so that the locking protrusion 222 can be plugged into the locking hole 215. Furthermore, a bonding agent (not shown) may be applied into the locking hole 215, to bond and fix the locking protrusion 222 in the locking hole 215. The locking protrusion 222 may be ground bump or dummy bump with thermal conducting function. Preferably, the height of the locking protrusion 222 is larger than that of the bumps 223. The bumps 223 are high temperature bumps (high lead bumps, such as lead/tin 95/5 or lead/tin 90/10), or metal materials with melting point of higher than 200� C. (higher than that of the solders 230), and they may be the bumps that cannot be reflowed, such as copper, nickel, gold. The solders 230 are eutectic solders for connecting the leads 212 with the bumps 223 after reflowing. As shown in FIG. 3, the flip chip 220 is flip-chip bonded to the leadframe 210 with the active surface 221 facing the upper surface 213 of the fastening part 211. When the bumps 223 of the flip chip 220 are bonded to the upper surface 216 of the leads 212 of the leadframe 210 through the solders 230, the locking protrusion 222 of the flip chip 220 is correspondingly plugged into the locking hole 215 to act as an anti-floating structure for the flip chip package 200, so as to fix the gap between the flip chip 220 and the leadframe 210 in the perpendicular direction, thus preventing the flip chip 220 from floating up during reflowing. Furthermore, when the bumps 223 and the leads 212 are is 5 soldered and bonded by the solders 230, the locking protrusion 222 is plugged into the locking hole 215; thus, due to a fixed gap, no necking portion will be formed in the solders 230. As shown in FIG. 4, the molding compound 240 seals the bumps 223 and the locking protrusion 222. In this embodiment, the lower surface 214 of the fastening part 211 and the lower surface 217 of the leads 212 are exposed outside the molding compound 240, so as to form a flip chip package without pins. Since the locking protrusion 222 of the flip chip 220 is plugged into the locking hole 215 of the fastening part 213 to fix the gap between the flip chip 220 and the leadframe 210, the flip chip 220 is prevented from floating up or sliding aside when the solders 230 are reflowed, and the bumps 223 of the flip chip 220 will keep contact with the leads 212 of the leadframe 210, so as to avoid the solders 230 from generating necking at one side near the leadframe 210, thus enhancing reliability. Furthermore, the flip chip package provided by the present invention is used to solve the problem that the flip chip floats up when soldered to the chip carrier through the solders. In addition to the leadframe, other chip carriers may also be applied. Referring to FIG. 5, according to a second embodiment of the present invention, a flip chip package 300 with an anti-floating structure mainly comprises a chip carrier 310, a flip chip 320 with a plurality of locking protrusions 322, a plurality of solders 330, and a molding compound 340. The chip carrier 310 has an upper surface 311 and a lower surface 312. The chip carrier 310 further has a plurality of contacts 313 (such as connecting pads) exposed at the upper surface 311, and at least one locking hole 314 exposed at the upper surface 311. The chip carrier 310 may be selected from a group consisting of a printed circuit board, a ceramic circuit board, a leadframe, and a metal carrier. In this embodiment, since the chip carrier 310 is a circuit substrate, such as a printed circuit board or a ceramic circuit board, it may comprise a dielectric layer 315 and a copper layer 316. The dielectric layer 315 comprises at least one first hole 315 a, whereas the copper layer 316 is formed on the dielectric layer 315 and comprises at least one second hole 316 a aligned with the first hole 315 a. The first hole 315 a and the second hole 316 a form the locking hole 314. Furthermore, the copper layer 316 and the contacts 313 may be made of the same copper foil. Preferably, the aperture of the second hole 316 a of the copper layer 316 is smaller than that of the first hole 315 a of the dielectric layer 315, thus providing the locking hole 314 with a notch, to facilitate plugging of the locking protrusion 322. The flip chip 320 comprises an active surface 321 on which at least one of the locking protrusions 322 and a plurality of bumps 323 are formed. In this embodiment, the bumps 323 are arranged in a grid array, with the locking protrusion 322 disposed at the periphery or corner of the active surface 321. The bumps 323 are soldered to the contacts 313 by the reflowing of the solders 330, and the locking protrusion 322 is plugged into the locking hole 314. In addition, after flip-chip bonding, the molding compound 340 can be formed on the upper surface 311 of the chip carrier 310 by stamping or other techniques, to seal the bumps 323 and the locking protrusion 322. In this embodiment, the flip chip 320 is also sealed and wrapped by the molding compound 340. In addition, a plurality of solder balls 350 or other external conducting elements may be further disposed on the lower surface 312 of the chip carrier 310. By means of plugging the locking protrusion 322 into the locking hole 314, inappropriate floating up and disengagement of the flip chip 320 may be avoided during the reflowing process of the solders 330 and the formation process of the molding compound 340. While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention may not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope as defined in the appended claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7435624 *Apr 28, 2006Oct 14, 2008Sandisk CorporationMethod of reducing mechanical stress on a semiconductor die during fabricationUS8415779 *Mar 15, 2011Apr 9, 2013Freescale Semiconductor, Inc.Lead frame for semiconductor packageUS8476772 *Nov 24, 2010Jul 2, 2013Stats Chippac, Ltd.Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor dieUS20110248390 *Mar 15, 2011Oct 13, 2011Freescale Semiconductor, Inc.Lead frame for semiconductor packageUS20110260303 *Apr 23, 2010Oct 27, 2011Stats Chippac, Ltd.Semiconductor Device and Method of Forming Openings in Thermally-Conductive Frame of FO-WLCSP to Dissipate Heat and Reduce Package HeightUS20120126429 *Nov 24, 2010May 24, 2012Stats Chippac, Ltd.Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor DieUS20130214316 *Aug 12, 2012Aug 22, 2013Hon Hai Precision Industry Co., Ltd.Led device with structure for precisely locating leds thereon and method for manufacturing the same* Cited by examinerClassifications U.S. Classification257/778, 257/E23.033, 257/E23.039International ClassificationH01L23/495, H01L23/48, H01L23/31, H01L21/60Cooperative ClassificationH01L2224/10135, H01L2224/10165, H01L2224/81139, H01L2224/81141, H01L2224/16, H01L2924/01029, H01L2924/014, H01L2924/01006, H01L2924/01322, H01L2224/81815, H01L24/81, H01L2224/81136, H01L2224/8121, H01L2924/01082, H01L2924/15311, H01L23/4951, H01L23/4952, H01L23/3114, H01L23/3128, H01L24/16, H01L2224/81193, H01L2924/01079, H01L2924/0105, H01L2224/13099, H01L2924/01033, H01L2224/1403European ClassificationH01L24/16, H01L24/81, H01L23/31H1, H01L23/495A4, H01L23/31H2B, H01L23/495C2Legal EventsDateCodeEventDescriptionNov 7, 2011FPAYFee paymentYear of fee payment: 4Dec 8, 2005ASAssignmentOwner name: ADVANCED SEMICONDUCTOR ENGINEERING, INC., TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIU, CHIEN;WANG, MENG-JEN;TSAI, SHENG-TAI;REEL/FRAME:017338/0203Effective date: 20050829RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services