Source: http://www.google.com/patents/US8159897?dq=ascentive
Timestamp: 2016-09-26 16:56:51
Document Index: 48162049

Matched Legal Cases: ['Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10', 'Application No. 10']

Patent US8159897 - Two levels of voltage regulation supplied for logic and data programming ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsSystems and methods involve the use of a flash memory device having multiple flash memory cells. A first interface is adapted to receive power for selectively programming each flash memory cell. A second interface is adapted to receive power supplied to logic level circuitry to perform the selection...http://www.google.com/patents/US8159897?utm_source=gb-gplus-sharePatent US8159897 - Two levels of voltage regulation supplied for logic and data programming voltage of a memory deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8159897 B2Publication typeGrantApplication numberUS 12/715,979Publication dateApr 17, 2012Filing dateMar 2, 2010Priority dateMay 15, 2006Fee statusPaidAlso published asUS7701797, US20070263469, US20100157674, WO2007134281A2, WO2007134281A3Publication number12715979, 715979, US 8159897 B2, US 8159897B2, US-B2-8159897, US8159897 B2, US8159897B2InventorsMichael J. Cornwell, Christopher P. DudteOriginal AssigneeApple Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (102), Non-Patent Citations (36), Referenced by (2), Classifications (15), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetTwo levels of voltage regulation supplied for logic and data programming voltage of a memory device
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5023646May 12, 1989Jun 11, 1991Minolta Camera Kabushiki KaishaAutomatic focus detection systemUS5109496Sep 27, 1989Apr 28, 1992International Business Machines CorporationMost recently used address translation system with least recently used (LRU) replacementUS5394450Apr 13, 1993Feb 28, 1995Waferscale Integration, Inc.Circuit for performing arithmetic operationsUS5412601Aug 30, 1993May 2, 1995Nippon Steel CorporationNon-volatile semiconductor memory device capable of storing multi-value data in each memory cellUS5424978Mar 14, 1994Jun 13, 1995Nippon Steel CorporationNon-volatile semiconductor memory cell capable of storing more than two different data and method of using the sameUS5515321Dec 23, 1994May 7, 1996Nippon Steel CorporationData reading method in semiconductor storage device capable of storing three- or multi-valued data in one memory cellUS5541883May 9, 1995Jul 30, 1996Integrated Device Technology, Inc.Method and apparatus for simultaneous long writes of multiple cells of a row in a static ramUS5541886Dec 27, 1994Jul 30, 1996Intel CorporationMethod and apparatus for storing control information in multi-bit non-volatile memory arraysUS5563838Mar 14, 1995Oct 8, 1996Micron Electronics, Inc.Module having voltage control circuit to reduce surges in potentialUS5602987Dec 29, 1993Feb 11, 1997Sandisk CorporationFlash EEprom systemUS5671229May 25, 1994Sep 23, 1997Sandisk CorporationFlash eeprom system with defect handlingUS5712815Apr 22, 1996Jan 27, 1998Advanced Micro Devices, Inc.Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cellsUS5719808Mar 21, 1995Feb 17, 1998Sandisk CorporationFlash EEPROM systemUS5745414Nov 26, 1996Apr 28, 1998Information Storage Devices, Inc.Integrated circuit system having reference cells for improving the reading of storage cellsUS5801980May 1, 1997Sep 1, 1998Invox TechnologyTesting of an analog memory using an on-chip digital input/output interfaceUS5812814Feb 24, 1994Sep 22, 1998Kabushiki Kaisha ToshibaAlternative flash EEPROM semiconductor memory systemUS5867721Nov 28, 1997Feb 2, 1999Intel CorporationSelecting an integrated circuit from different integrated circuit array configurationsUS5870041Dec 23, 1996Feb 9, 1999Samsung Electronics, Co., Ltd.Analog-to-digital converter with digital compensationUS5910924Aug 26, 1997Jun 8, 1999Hitachi, Ltd.Semiconductor integrated circuit including voltage converter effective at low operational voltagesUS5946257Aug 22, 1997Aug 31, 1999Micron Technology, Inc.Selective power distribution circuit for an integrated circuitUS5946714Apr 16, 1997Aug 31, 1999Mitsubishi Denki Kabushiki KaishaSemiconductor storage device utilizing address management tables and table state maps for managing data storage and retrievalUS6023781Sep 16, 1997Feb 8, 2000Nippon Steel CorporationMultilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read programUS6058060Dec 31, 1998May 2, 2000Invox TechnologyMulti-bit-per-cell and analog/multi-level non-volatile memories with improved resolution and signal-to noise ratioUS6072676Apr 13, 1998Jun 6, 2000Analog Devices, Inc.Protection circuit for an excitation current sourceUS6081447Mar 5, 1999Jun 27, 2000Western Digital CorporationWear leveling techniques for flash EEPROM systemsUS6097638Feb 11, 1998Aug 1, 2000Kabushiki Kaisha ToshibaSemiconductor memory deviceUS6134141Dec 31, 1998Oct 17, 2000Sandisk CorporationDynamic write process for high bandwidth multi-bit-per-cell and analog/multi-level non-volatile memoriesUS6141492Aug 26, 1999Oct 31, 2000Canon Kabushiki KaishaRecording apparatus for compressing and recording moving and still imagesUS6149316Jan 29, 1997Nov 21, 2000Sandisk CorporationFlash EEprom systemUS6166960Sep 24, 1999Dec 26, 2000Microchip Technology, IncorporatedMethod, system and apparatus for determining that a programming voltage level is sufficient for reliably programming an eepromUS6184726Jun 29, 1999Feb 6, 2001Sandisk CorporationAdjustable level shifter circuits for analog or multilevel memoriesUS6243290Aug 25, 2000Jun 5, 2001Hitachi, Ltd.Nonvolatile semiconductor memory deviceUS6259627Jan 27, 2000Jul 10, 2001Multi Level Memory TechnologyRead and write operations using constant row line voltage and variable column line loadUS6297988Feb 25, 2000Oct 2, 2001Advanced Micro Devices, Inc.Mode indicator for multi-level memoryUS6313493Aug 26, 1998Nov 6, 2001Matsushita Electric Industrial Co., Ltd.Semiconductor device and method for fabricating the same, memory core chip and memory peripheral circuit chipUS6424569Feb 25, 2000Jul 23, 2002Advanced Micro Devices, Inc.User selectable cell programmingUS6424748Apr 5, 1999Jul 23, 2002Mustek Systems Inc.Method for increasing bit number of digital image signals generated by a scannerUS6426893Feb 17, 2000Jul 30, 2002Sandisk CorporationFlash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocksUS6552929Feb 8, 2001Apr 22, 2003Advanced Micro Devices, Inc.Piggyback programming using an extended first pulse for multi-level cell flash memory designsUS6711059Sep 27, 2002Mar 23, 2004Lexar Media, Inc.Memory controllerUS6721820May 15, 2002Apr 13, 2004M-Systems Flash Disk Pioneers Ltd.Method for improving performance of a flash-based storage system using specialized flash controllersUS6757842Sep 6, 2002Jun 29, 2004Sandisk CorporationFlash EEprom systemUS6763424Jan 19, 2001Jul 13, 2004Sandisk CorporationPartial block data programming and reading operations in a non-volatile memoryUS6831858Aug 8, 2003Dec 14, 2004Sharp Kabushiki KaishaNon-volatile semiconductor memory device and data write control method for the sameUS6856546Nov 13, 2001Feb 15, 2005Sandisk CorporationMulti-state memoryUS6914846Dec 26, 2002Jul 5, 2005Sandisk CorporationFlash EEprom systemUS6925009Aug 18, 2004Aug 2, 2005Kabushiki Kaisha ToshibaSemiconductor memoryUS6937513Oct 16, 2003Aug 30, 2005Lsi Logic CorporationIntegrated NAND and nor-type flash memory device and method of using the sameUS6947332Jul 28, 2003Sep 20, 2005Sandisk CorporationComputer memory cards using flash EEPROM integrated circuit chips and memory-controller systemsUS6963505Oct 29, 2003Nov 8, 2005Aifun Semiconductors Ltd.Method circuit and system for determining a reference voltageUS7006379Mar 1, 2005Feb 28, 2006Kabushiki Kaisha ToshibaSemiconductor memoryUS7016231Oct 18, 2004Mar 21, 2006Renesas Technology Corp.Nonvolatile memoryUS7088615Jul 27, 2004Aug 8, 2006Sandisk CorporationMulti-state memoryUS7137011Jan 15, 2002Nov 14, 2006Sandisk CorporationRemovable mother/daughter peripheral cardUS7162569Feb 14, 2005Jan 9, 2007Sandisk CorporationPipelined parallel programming operation in a non-volatile memory systemUS7164561Mar 31, 2004Jan 16, 2007Sandisk CorporationVoltage regulator using protected low voltage devicesUS7170781Apr 7, 2005Jan 30, 2007Sandisk CorporationMulti-bit-per-cell flash EEPROM memory with refreshUS7212067Aug 1, 2003May 1, 2007Sandisk CorporationVoltage regulator with bypass for multi-voltage storage systemUS7218570Dec 17, 2004May 15, 2007Sandisk 3D LlcApparatus and method for memory operations using address-dependent conditionsUS7237046Mar 29, 2004Jun 26, 2007Sandisk Il Ltd.Data storage device with full access by all usersUS7237074Jun 13, 2003Jun 26, 2007Sandisk CorporationTracking cells for a memory systemUS7240219Nov 12, 2003Jul 3, 2007Sandisk Il Ltd.Method and system for maintaining backup of portable storage devicesUS7274602May 30, 2006Sep 25, 2007Spansion LlcStorage device and control method thereforUS7286394Jul 13, 2005Oct 23, 2007Renesas Technology Corp.Non-volatile semiconductor memory device allowing concurrent data writing and data readingUS7304883Jun 8, 2005Dec 4, 2007Matsushita Electric Industrial Co., Ltd.Semiconductor integrated circuitUS7317630Jul 15, 2005Jan 8, 2008Atmel CorporationNonvolatile semiconductor memory apparatusUS7391193Jan 25, 2005Jun 24, 2008Sandisk CorporationVoltage regulator with bypass modeUS7477549Jun 15, 2007Jan 13, 2009Kabushiki Kaisha ToshibaReference current generating circuit of nonvolatile semiconductor memory deviceUS20020021602Feb 14, 2000Feb 21, 2002Fukashi MorishitaSemiconductor device allowing external setting of internal power supply voltage generated by a voltage down converter at the time of testingUS20020140463Mar 15, 2001Oct 3, 2002Paul CheungProgrammable soft-start control for charge pumpUS20030086293Nov 2, 2001May 8, 2003Sandisk CorporationError management for writable tracking storage unitsUS20030103398Dec 11, 2002Jun 5, 2003Hieu Van TranSub-volt sensing for digital multilevel flash memoryUS20030137877Jan 18, 2002Jul 24, 2003Nima MokhlesiNoise reduction technique for transistors and small devices utilizing an episodic agitationUS20030217323May 20, 2002Nov 20, 2003Sandisk CorporationIncreasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored dataUS20040042269Aug 5, 2003Mar 4, 2004Hitachi, Ltd.Nonvolatile memory apparatusUS20040114427Dec 5, 2003Jun 17, 2004Sharp Kabushiki KaishaSemiconductor memory device and method for correcting memory cell dataUS20040145955Jan 15, 2004Jul 29, 2004Renesas Technology CorporationSemiconductor deviceUS20040179397Mar 25, 2004Sep 16, 2004Btg International Inc.Electrically alterable non-volatile memory with n-bits per cellUS20040205290Mar 26, 2004Oct 14, 2004Renesas Technology Corp.Memory deviceUS20040205418Feb 27, 2004Oct 14, 2004Kenji SakaueECC control apparatusUS20050007801Jul 6, 2004Jan 13, 2005Ron BarzilaiMulti-purpose non-volatile memory cardUS20050024128Aug 1, 2003Feb 3, 2005John PasternakVoltage regulator with bypass for multi-voltage storage systemUS20050027928Nov 12, 2003Feb 3, 2005M-Systems Flash Disk Pioneers, Ltd.SDRAM memory device with an embedded NAND flash controllerUS20050052934Sep 9, 2003Mar 10, 2005Tran Hieu VanUnified multilevel cell memoryUS20050146919Dec 29, 2003Jul 7, 2005Ellis Robert M.Memory system segmented power supply and controlUS20050172207Jan 30, 2004Aug 4, 2005Radke William H.Error detection and correction scheme for a memory deviceUS20050179421Mar 31, 2004Aug 18, 2005Yongliang WangVoltage regulator using protected low voltage devicesUS20050180209Apr 23, 2004Aug 18, 2005M-Systems Flash Disk Pioneers, Ltd.Method of managing a multi-bit-cell flash memoryUS20050242835Apr 30, 2004Nov 3, 2005Xilinx, Inc.Reconfiguration port for dynamic reconfiguration-controllerUS20050246520Apr 30, 2004Nov 3, 2005Xilinx, Inc.Reconfiguration port for dynamic reconfiguration-system monitor interfaceUS20050248364Apr 30, 2004Nov 10, 2005Xilinx, Inc.Reconfiguration port for dynamic reconfigurationUS20050262323May 21, 2004Nov 24, 2005Woo Steven CSystem and method for improving performance in computer memory systems supporting multiple memory access latenciesUS20050273548Jun 4, 2004Dec 8, 2005Micron Technology, Inc.Memory system with user configurable density/performance optionUS20060101193Mar 14, 2005May 11, 2006M-Systems Flash Disk Pioneers, Ltd.States encoding in multi-bit flash cells for optimizing error rateUS20060164054Jan 25, 2005Jul 27, 2006Yongliang WangVoltage regulator with bypass modeUS20060215454Mar 22, 2006Sep 28, 2006Samsung Electronics Co., Ltd.Nonvolatile memory device and method for storing status information using multiple stringsUS20060294295Jun 24, 2005Dec 28, 2006Yukio FukuzoDRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a deviceUS20070074093Jan 6, 2006Mar 29, 2007M-Systems Flash Disk Pioneers Ltd.NAND flash memory controller exporting and NAND interfaceUS20070091677Apr 5, 2006Apr 26, 2007M-Systems Flash Disk Pioneers Ltd.Method for recovering from errors in flash memoryUS20070220388Mar 2, 2006Sep 20, 2007Quereshi Qadeer AApparatus and method for adjusting an operating parameter of an integrated circuitUS20070226434May 22, 2007Sep 27, 2007Guterman Daniel CData recovery in a memory system using tracking cellsUS20080018377Jan 9, 2007Jan 24, 2008Hwi-Taek ChungSemiconductor memory device controlling output voltage level of high voltage generator according to temperature variationNon-Patent CitationsReference1Inoue, et al. "NAND Flash Applications Design Guide: System Solutions from Toshiba America Electronic Components, Inc." Apr. 2003, pp. 1-29.2International Search Report & Written Opinion, PCT/US2007/068699, mailed Feb. 8, 2008, 16 pages.3International Search Report & Written Opinion, PCT/US2007/068799, mailed Jan. 30, 2008, 14 pages.4International Search Report & Written Opinion, PCT/US2007/068802, Mailed Jan. 22, 2008, 17 pages.5International Search Report & Written Opinion, PCT/US2007/068810, mailed Jan. 22, 2008, 15 pages.6International Search Report & Written Opinion, PCT/US2007/068851, mailed Jun. 20, 2008, 36 pages.7International Search Report & Written Opinion, PCT/US2007/068859, mailed Jan. 22, 2008, 19 pages.8International Search Report & Written Opinion, PCT/US2007/068903, mailed Jan. 22, 2008, 16 pages.9International Search Report & Written Opinion, PCT/US2007/068950, mailed Jan. 16, 2008, 19 pages.10International Search Report & Written Opinion, PCT/US2007/068958, mailed Feb. 8, 2008, 17 pages.11International Search Report & Written Opinion, PCT/US2007/068966, mailed Jun. 12, 2008, 29 pages.12Korean Intellectual Property Office, Korean Office Action for Application No. 10-2011-7010646, dated Jul. 28, 2011, 1 page.13Korean Intellectual Property Office, Korean Office Action for Application No. 10-2011-7010652, dated Jul. 28, 2011, 3 pages.14Korean Intellectual Property Office, Korean Office Action in Application No. 10-2008-7030400, dated Feb. 10, 2011, 4 pags.15Korean Intellectual Proprty Office, Korean Office Action for Application No. 10-2011-7010645, dated Jul. 28, 2011, 1 page.16Korean Intellectual Proprty Office, Korean Office Action for Application No. 10-2011-7010649, dated Jul. 28, 2011, 2 pages.17Korean Intellectual Proprty Office, Korean Office Action for Application No. 10-2011-7010650, dated Jul. 28, 2011, 1 page.18Korean Intellectual Proprty Office, Korean Office Action for Application No. 10-2011-7010651, dated Jul. 28, 2011, 1 page.19Korean Intellectual Prorpty Office, Korean Office Action for Application No. 10-2011-7010647, dated Jul. 28, 2011, 2 pages.20U.S. Appl. No. 11/694,693, filed Mar. 30, 2007, Non-final Office Action mailed Jul. 2, 2008, 9 pages.21U.S. Appl. No. 11/694,694, filed Mar. 30, 2007, Non-final Office Action, mailed Jul. 9, 2008, 22 pages.22U.S. Appl. No. 11/694,694, Final Office Action, mailed Feb. 4, 2009, 19 pages.23U.S. Appl. No. 11/694,712, filed Mar. 30, 2007, Non-final Office Action mailed Aug. 21, 2008, 12 pages.24U.S. Appl. No. 11/694,712, Final Office Action, mailed Feb. 9, 2009, 11 pages.25U.S. Appl. No. 11/694,712, Non Final Office Action, mailed Apr. 10, 2009, 9 pages.26U.S. Appl. No. 11/694,739 Office Action (Non Final), mailed Apr. 2, 2009, 17 pages.27U.S. Appl. No. 11/694,742, filed Mar. 30, 2007,Non-final Office Action, mailed Aug. 20, 2008, 10 pages.28U.S. Appl. No. 11/694,763 Office Action (Non Final), mailed Mar. 19, 2009, 16 pages.29USPTO Final Office Action in U.S. Appl. No. 11/694,791, mailed Jun. 24, 2010, 7 pages.30USPTO Non-Final Office Action in U.S. Appl. No. 11/694,779, mailed Jan. 6, 2010, 24 pages.31USPTO Non-Final Office Action in U.S. Appl. No. 11/694,791, mailed Feb. 5, 2010, 12 pages.32USPTO Non-Final Office Action in U.S. Appl. No. 11/694,799, mailed Feb. 8, 2010, 11 pages.33USPTO Non-Final Office Action in U.S. Appl. No. 11/694,799, mailed Jul. 9, 2010, 7 pages.34USPTO Non-Final Office Action in U.S. Appl. No. 12/469,604, mailed Mar. 19, 2010, 7 pages.35USPTO Non-Final Office Action in U.S. Appl. No. 12/571,144, mailed Sep. 16, 2010, 9 pages.36USPTO Non-Final Office Action in U.S. Appl. No. 12/625,339, mailed Mar. 31, 2010, 8 pages.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8713404 *Jul 1, 2011Apr 29, 2014Apple Inc.Controller interface providing improved data reliabilityUS20130007562 *Jul 1, 2011Jan 3, 2013Apple Inc.Controller Interface Providing Improved Data Reliability* Cited by examinerClassifications U.S. Classification365/226, 365/185.18, 365/185.22International ClassificationG11C5/14Cooperative ClassificationG11C2211/5641, G11C16/30, G11C5/145, G11C16/0483, G11C11/5642, G11C11/5628European ClassificationG11C11/56D2, G11C16/30, G11C11/56D4, G11C16/04N, G11C5/14PLegal EventsDateCodeEventDescriptionSep 30, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services