Source: http://www.google.com/patents/US6327244?dq=6076065
Timestamp: 2016-05-28 18:19:09
Document Index: 62872082

Matched Legal Cases: ['art 4', 'art 9', 'art 4', 'art 4', 'art 9', 'art 4', 'art 9']

Patent US6327244 - Packet handler - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA packet handler includes an interface circuit of an ATM handler corresponding in one-to-one relation to each input/output port of an ATM switch. A switch interface including a disconnection circuit and a distribution circuit controls the cell flow from each interface circuit to a corresponding input...http://www.google.com/patents/US6327244?utm_source=gb-gplus-sharePatent US6327244 - Packet handlerAdvanced Patent SearchPublication numberUS6327244 B1Publication typeGrantApplication numberUS 09/210,849Publication dateDec 4, 2001Filing dateDec 15, 1998Priority dateApr 5, 1996Fee statusPaidAlso published asUS5903544, US6850485, US7502380, US20020012317, US20050100044Publication number09210849, 210849, US 6327244 B1, US 6327244B1, US-B1-6327244, US6327244 B1, US6327244B1InventorsKen'ichi Sakamoto, Yasunari Shinohara, Takahiko KozakiOriginal AssigneeKen'ichi Sakamoto, Yasunari Shinohara, Takahiko KozakiExport CitationBiBTeX, EndNote, RefManPatent Citations (14), Referenced by (9), Classifications (21), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetPacket handler
US 6327244 B1Abstract
A packet handler includes an interface circuit of an ATM handler corresponding in one-to-one relation to each input/output port of an ATM switch. A switch interface including a disconnection circuit and a distribution circuit controls the cell flow from each interface circuit to a corresponding input port and the cell from the output ports of the ATM switch to each interface circuit. In a set of the interface circuits, one redundant transmission path can be replaced arbitrarily with two nonredundant independant transmission paths. The ATM communication system can thus accomodate redundant transmission paths and nonredundant transmission paths in an arbitrary ratio.
What is claimed is: 1. A method of transmitting packets in a packet handler which has a plurality of slots each of which having installed therein a line interface and a switch for switching packets, said method comprising the steps of:
if a plurality of pairs of line interfaces, each of which is connected to a packet handler by their respective redundant transmission paths, are installed into the slots the following steps are performed: receiving packets at one line interface pair of the line interface pairs, transferring the packets received at one line interface of the one line interface pair to the switch, blocking the packets received at the other line interface of the one line interface pair so as not to transfer packets from the other line interface to the switch, and multi-casting, at the switch, said packets from the one line interface to other line interface pairs of the line interface pairs; and if a plurality of line interfaces, each of which is connected to a packet handler by its respective non-redundant transmission path, are installed into the slots the following steps are performed: receiving packets at each one of the line interfaces, transferring the packets from the one line interface to the switch, and transferring the packets from the one line interface to another line interface of the line interfaces. 2. A packet handler comprising:
a plurality of slots each of which having installed therein a line interface; a switch for switching packets; and a circuit which is capable of, if a plurality of pairs of line interfaces each of which is connected to a packet handler by their respective redundant transmission paths are installed into said slots, transferring packets that one line interface of one of the line interface pairs receives to said switch and blocking packets that the other line interface of the one of the line interface pairs receives so as not to transfer packets from the other line interface to said switch, and which is capable of, if a plurality of line interfaces each of which is connected to a packet handler by its respective non-redundant transmission path are installed into said slots, transferring packets that each one of the line interfaces of the line interface receives to said switch, wherein said switch multi-casts the packets from the one line interface of the one of the line interface pairs to other line interface pairs, of the line interface pairs and transfers the packets from the one line interface of the line interfaces to other line interfaces of the line interfaces.
this application is continuation of Ser. No. 08/826,523, filed Apr. 3, 1997, now U.S. Pat. No. 5,903,544.
The present invention relates to a packet handler. More particulary the present invention relates to a packet handler of synchronous transfer mode (ATM) for fixed-length packets.
An ATM handler for transferring various information in fixed-length packets (hereinafter referred to as “cells”), as shown by reference numeral 1 in FIG. 2, for example, comprises a plurality of line interfaces (hereinafter referred to as the interface circuit) 3 for accommodating a plurality of transmission paths 2 (2-1 to 2-n′) each including a pair of input and output lines, an ATM switch common part 4 including an ATM switch (ATM SW) 5 for distributing the input cells passed through each interface circuit 3 among the interface circuits in accordance with the routing information contained in the cell header, and a control part 9 connected to the interface circuits 3 and the ATM common switch part 4 through a control line 10.
In employing a redundant transmission path, an interface circuit 3-i for accommodating one redundant transmission path 2-i (i=1 to n) is paired with an interface circuit 3-i′ for accommodating the other transmission path 2-i′. One of the interface circuits is used as an active path, and the other as a standby path. The input cells from the interface circuits for active path are selected by a selector and input to an ATM switch 5. In such a case, as shown in FIG. 2, for example, a switching interface 6 including a selector 11 is provided for each pair of the interface circuits 3. In this way, only the input cells arriving from the interface circuits for an active path are led to input ports I (I-1 to I-n) of the ATM switch 5. The cells output from the output ports O (O-1 to O-n) of the ATM switch 5 are distributed between the two interface circuits of the pair at the switching interface 6.
In order to achieve the above-mentioned objects, according to one aspect of the present invention, there is provided an ATM handler comprising a plurality of input/output ports, a packet switch cicuit for distributing the input packets from the input ports among the output ports as determined by the header information, a plurality of line interfaces corresponding to the input/output ports for accommodating a transmission path including an input line and an output line, and an input transfer control circuit for controlling the transfer of input packets in such a manner that the line interfaces are separated into a plurality of sets of a predetermined number. Each set of the line interfaces accommodates redundant transmission paths such that only the input packets from a line interface constituting an active path are applied to the corresponding input port of the packet switch while at the same time blocking flow of the packets from the other line interfaces constituting a standby path into the corresponding input ports of the packet switch. Each set of the line interfaces accommodates independent nonredundant transmission paths such that the input packets from each line interface are applied to the corresponding input ports of the packet switch.
The switch interface may include, for example, two gates for allowing or blocking the flow of packets from each line interface into corresponding input ports of the packet switch, and a control signal circuit for generating a control signal to be applied to each of the two gate in accordance with the operation mode of the transmission paths. The control signal generating circuit generates a control signal for opening one of the two gate and closing the other in the case where the transmission paths are in redundant mode, and a control signal for opening each of the gates in the case where he transmission paths are in nonredundant mode.
According to an embodiment of the invention, each switch interface includes a first register for storing the control information indicating the operation mode of a corresponding pair of transmission paths, and a second register for storing the control information designating the transmission path constituting an active path or a standby path in the case where the transmission paths are operated in redundant mode. The control signal generating cicuits generates a gate control signal in accordance with the status of the control information stored in the first and second registers.
The foregoing and other objects, advantages, manner of operation and novel features of the present invention will be understood from the following detailed description when read in connection with the accompanying drawings, in which
FIG. 8 is a diagram showing an ATM handler according to another embodiment of the invention.
An ATM handler 1 includes a plurality of interface circuits 3 (3-1 to 3-n) for accommodating a plurality of transmission paths 2 (2-1 to 2-n), respectively, an ATM switch common part 4, and a control part 9 connected to the interface circuits 3 and the ATM witch common part 4 through a control transfer path 10. In FIG. 1, each interface circuit 3 is shown in a block. In an actual handler, however, as described later with reference to FIG. 5, the interface circuit 3 includes an input line interface 3 a connected to an input line and an output line interface 3 b connected to an output line, each having the physical layer processing function and the ATM layer processing function.
In the ATM handler according to this embodiment, the number of the interface circuits 3 corresponds to the number of input/output ports of the ATM switch. Each switch interface 6 includes a disconnection circuit 7 inserted between a set of input ports I-i, I-(i+1) and two input line interfaces 3 a connected to two transmission paths 2-i, 2-(i+1), respectively, and a distribution circuit 8 arranged between a set of output ports O-i, O-(i+1) and two output line interfaces 3 b connected to the transmission paths 2-i, 2-(i+1), respectively.
The functions of the disconnection circuit 7 and the distribution circuit 8 will be explained with reference to FIGS. 5A and 5B. In FIGS. 5A and 5B, the solid lines show the signal x flow, and the marks indicate the signals being disconnected.
FIG. 5A shows the status of the switch interface 6 with two interface circuits 3 accommodating nonredundant paths. In this case, the disconnection circuit 7 supplies the input cells from the input line interfaces 3 a-i, 3 a-(i+1) without blocking to the two input ports I-i, I-(i+1) of the ATM switch 5.
In FIG. 5A, numerals 20-i and 20-(i+1) designate queue buffers formed in the common buffer memory of the ATM switch 5 and correspond to the output ports O-i and 0-(i+1), respectively. The cells (output cells) retrieved from these queue buffers are supplied through the distribution circuit 8 to the output line interfaces 3 b-i, 3 b-(i+1), respectively, and after removing the internal cell information therefrom, are sent out to the transmission paths (output lines).
According to this embodiment, as evident from FIG. 5C, for example, the output signal from one of a pair of input line interfaces 3 a-i and 3 a-(i+1), i.e., the input line interface 3 a-i for active path, is applied through the disconnection circuit 7 to the input port I-i of the ATM switch 5, while the output signal from the input line interface 3 a-(i+1) for standby path is blocked by the disconnection circuit so that the input port I-(i+1) remains unused.
The ATM switch 5 forms a queue buffer 20-i corresponding to the output port O-i connected to the output line 2-i constituting one of the redundant output lines. The output cells retrieved from the queue buffer 20-i are supplied to a pair of output line interfaces 3 b-i, 3 b-(i+1) through the distribution circuit 8, thereby sending out the same signal (cell) to the redundant transmission paths 2-i, 2-(i+1).
FIG.6 shows the switch interface 6 including the is connection circuit 7 and the distribution circuit 8 according to an embodiment. The input signal wire from the interface circuit 3-i is designated as 34-0, the input signal wire from the interface circuit 3-(i+1) as 34-1, the output signal to the interface circuit 3-i as 35-0, and the output signal line to the interface circuit 3-(i+1) as 35-1.
In the case where each of the interface circuits 3-i and 3-(i+1) constituting the interface circuit pair accommodates a redundant transmission path, the value “0” indicating a “redundant architecture” is set in the register 31, and a value indicating a particular input signal wire constituting an active path is set in the register 30. In the case where the interface circuits 3-i, 3-(i+1) accommodate two nonredundant independent transmission paths, on the other hand, the value “1” indicating a “redundant architecture” is set in the register 31.
relation between the values set in the two registers (including the register 31 for setting the redundant architecture and the register 30 for setting an active path) and the status of each of the two AND gates 32-0, 32-1 is shown in FIG. 7.
The distribution circuit 8 sends out the output cells of the output port O-i of the ATM switch to the output signal wire 35-0 of the two output signal wires, and the output signal selected by a selector 38 is sent out to the other output signal wire 35-1. The selector 38 is supplied with the output signals of the two output ports O-i and O-(i+1) of the ATM switch and adapted to selectively output one of the two output signals in accordance with the setting of the redundant setting register 31.
In this example, assume the transmission paths are redundant. The setting of the redundant setting register 31 is “0” and therefore the same output (the output of the output port O-i) is produced on the output signal line 35-1 as on the output signal line 35-0. In the case where the transmission paths are nonredundant, on the other hand, the setting of the register 31 is “1” and an output (the output of the output port O-(i+1) different from that of the output signal line 35-0 is produced on the output signal line 35-1.
The output value (count value) of the counter corresponds to the output ports. Each time of count-up, therefore, the cell destination output port is switched. Also, the band control table has stored therein the output port information corresponding to the count values of the counter. Each time the count is updated, therefore, the output port information is generated. On the basis of the a output port information, the read address table is accessed thereby to produce a queue buffer read address corresponding to the output ports.
In this example, a plurality of line cards 41 are divided into two line card groups (blocks 45-0 and 45-1). The line cards LIFi-0 (i=1 to n) of one line card group (block 45-0) is paired with each line card LIFi-1 (i=1 to n) of the other line card group (block 45-1), so that the interface circuit of each pair constituting a redundant system is connected to each switch interface 6 on the ATM switch card 43.
The operation mode (independent mode or redundant. mode) of the transmission paths accommodated in each line card of the ATM handler according to the invention can be designated by the setting of the control register arranged in the switch interface on the ATM switch card. The setting of the control register can be determined by an instruction from the control part 9 or by way of an input unit connected to the ATM switch card. The present invention, therefore, can provide a versatile system for meeting the requirement of each network configuration.
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