Source: https://patents.google.com/patent/KR100771871B1/en
Timestamp: 2020-07-02 13:43:03
Document Index: 328582758

Matched Legal Cases: ['art 105', 'art 105', 'art 110', 'art 105', 'art 110', 'art 110', 'art 110', 'art 105', 'art 110', 'art 110', 'art 105']

KR100771871B1 - Semiconductor device including vertical channel transistor - Google Patents
Semiconductor device including vertical channel transistor Download PDF
KR100771871B1
KR100771871B1 KR1020060046544A KR20060046544A KR100771871B1 KR 100771871 B1 KR100771871 B1 KR 100771871B1 KR 1020060046544 A KR1020060046544 A KR 1020060046544A KR 20060046544 A KR20060046544 A KR 20060046544A KR 100771871 B1 KR100771871 B1 KR 100771871B1
KR1020060046544A
홍민종
2006-05-24 Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
2006-05-24 Priority to KR1020060046544A priority Critical patent/KR100771871B1/en
2007-11-01 Publication of KR100771871B1 publication Critical patent/KR100771871B1/en
239000011295 pitch Substances 0.000 claims abstract description 114
239000010410 layers Substances 0.000 description 91
229910021350 transition metal silicides Inorganic materials 0.000 description 1
A semiconductor device having a vertical channel transistor is provided. The semiconductor device includes a substrate and a plurality of active pillars extending upwardly from the substrate. The active pillars have channel portions, respectively. The active pillars are arranged at a first pitch in odd and even columns, and the active pillars arranged in the even rows are shifted by a second pitch with respect to the active pillars arranged in the odd columns, and the odd and even columns The rows are arranged at a third pitch.
Semiconductor device including vertical channel transistor
1A to 1G are layout views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
2A through 2N are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, taken along cut line X-X 'of FIGS. 1A through 1G.
3A through 3N are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, taken along the cutting line Y-Y 'of FIGS. 1A through 1G.
4A through 4D are layout views sequentially illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment of the present invention.
5A through 5D are layout views sequentially illustrating a method of manufacturing a semiconductor device, according to another embodiment of the present invention.
6A through 6D are layout views sequentially illustrating a method of manufacturing a semiconductor device, according to another embodiment of the present invention.
7 is a layout diagram of a hard mask pattern according to a technique before improvement.
100: substrate 210: hard mask pattern
P 1 : First pitch P 2 : Second pitch
P 3 : Pitch 3 B / L: Bit Line
100a: device isolation trench P: active pillar
110: channel portion 230: surrounding gate electrode
231: word line 250a: storage node electrode
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a vertical channel transistor.
In a semiconductor device employing a planar type transistor in which a gate electrode is formed on a semiconductor substrate and a junction region is formed on both sides of the gate electrode, a channel length is to be reduced as the integration density of the semiconductor device is increased. Attempts are continuing. However, reducing channel length may result in short channel effects such as drain induced barrier lowering (DIBL), hot carrier effects and punch through. In order to prevent such a short channel effect, various methods have been proposed, such as a method of reducing the depth of the junction region and a method of extending the channel length by forming a groove in the channel portion.
However, as the integration density of semiconductor memory devices, particularly dynamic random access memory (DRAM), is approaching giga bits, the above attempts to prevent short channel effects are also reaching their limit.
To solve this problem, vertical channel transistors having channels in a direction perpendicular to the substrate have been studied. In manufacturing such vertical channel transistors, the substrate may be etched to form an active pillar having a channel region. The pitch of these active pillars is very small and its top surface is generally square, increasing the difficulty of the photolithography process. Therefore, there is a disadvantage in that expensive photolithography equipment must be used.
SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device including a vertical channel transistor having high integration and having photolithography affinity and a method of manufacturing the same.
In order to achieve the above technical problem, an embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate and a plurality of active pillars extending upwardly from the substrate. The active pillars have channel portions, respectively. The active pillars are arranged in a first pitch in odd and even rows, and the active pillars arranged in the even rows are shifted by a second pitch with respect to the active pillars arranged in the odd columns, and the odd columns and the Even rows are arranged in a third pitch.
In one embodiment, a word line may be disposed between odd rows and even rows of the active pillars. The word line surrounds a portion of the channel portion of the active pillar located in the odd row and a portion of the channel portion of the active pillar located in the even row. Specifically, surrounding gate electrodes are provided at outer peripheries of the active pillars to surround channel portions of the active pillars, and in this case, the word line includes surround gate electrodes positioned in the odd rows and surround gates located in the even rows. It may be electrically connected to the gate electrodes. The word lines may be arranged at a first pitch.
In one embodiment, bitlines may be provided in the substrate, each extending along the columns of the active pillars. The bit lines may be arranged at a third pitch.
In one embodiment, storage node electrodes may be provided on the active pillars to respectively connect the active pillars. The array of storage node electrodes may be the same as the array of active pillars.
In another embodiment, a bit line formed in the substrate between odd and even rows of the active pillars may be provided. The bit line connects active pillars located in the odd row and active pillars located in the even row. The bit lines may be arranged at a first pitch. In this case, word lines extending along the columns may be arranged, and the word lines may be arranged at a third pitch.
In another embodiment, the storage node electrodes can be tiled and arranged to have a first pitch and a third pitch in columns and rows, respectively.
In order to achieve the above technical problem, another embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate and a plurality of active pillars extending upwardly from the substrate. The active pillars have channel portions, respectively, and have a first pitch and a third pitch in columns and rows, and are arranged in a checkerboard shape. Storage node electrodes are disposed on the active pillars to respectively connect the active pillars. The storage node electrodes are arranged at a first pitch in odd and even columns, and the storage node electrodes arranged in the even rows are shifted by a second pitch relative to the storage node electrodes arranged in the odd columns, and the odd number is The rows and even rows are arranged in a third pitch.
The second pitch may be 1/2 of the first pitch. In addition, the first pitch may be 2/3 to 3/2 times of the third pitch.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the figures, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.
1A to 1G are layout views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 2A through 2N are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, taken along cut line X-X 'of FIGS. 1A through 1G. 3A through 3N are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, taken along the cutting line Y-Y 'of FIGS. 1A through 1G.
1A, 2A, and 3A, a substrate 100 is provided. The substrate 100 may be a silicon single crystal substrate, a silicon on insulator (SOI) substrate, or an epitaxial substrate having an epitaxial layer formed on a base substrate.
A pad oxide film is formed on the substrate 100. The pad oxide layer may be formed by thermal oxidation. A hard mask film is laminated on the pad oxide film. The hard mask layer may be a material having an etch selectivity with respect to the pad oxide layer and the substrate. The hard mask layer may be, for example, a silicon nitride layer or a silicon oxynitride layer. Subsequently, a photoresist film is formed on the hard mask film, and a photoresist pattern (not shown) is formed by exposing the photoresist film with a mask to a first exposure mask (not shown) on which a first exposure pattern (not shown) is drawn. do. Thereafter, the hard mask film and the pad oxide film are etched using the photoresist pattern as a mask. As a result, the hard mask patterns 210 and the pad oxide layer patterns 205 below them are formed. Thereafter, the photoresist pattern is removed to expose the hard mask patterns 210.
The hard mask patterns 210 are arranged in columns and rows. Specifically, the hard mask patterns 210 are arranged in a first pitch P 1 in odd and even columns, and the hard mask patterns 210 arranged in the even columns are arranged in the odd columns. The hard mask patterns 210 are shifted by the second pitch P 2 and disposed. The second pitch P 2 may be 1/2 of the first pitch P 1 .
In addition, the odd columns and the even columns may be arranged in a third pitch P 3 . In this case, odd rows of the hard mask patterns 210 may include hard mask patterns 210 located in the odd columns, and even rows of the hard mask patterns 210 may include hard masks located in the even columns. It is composed of patterns 210. Therefore, the hard mask patterns 210 are arranged at twice the pitch of the third pitch P 3 , that is, 2P 3 in the odd rows and the even rows. The first pitch P 1 may be 2/3 to 3/2 times greater than the third pitch P 3 . In an embodiment, the first pitch P 1 may be the same as the third pitch P 3 . Here, odd and even numbers are defined for convenience of description and may be interchanged.
The exposure mask for forming the hard mask patterns 210 includes first exposure patterns having the same arrangement as that of the hard mask patterns 210 illustrated in FIG. 1A. At this time, the critical pitch Pcr can be calculated by the following equation.
In the above formula, P x is the pitch in the x-axis direction, and P y is the pitch in the y-axis direction.
Applying Equation 1 to the present embodiment, P x is 2P 3 because it is the pitch of the hard mask pattern 210 in the row, and P y is P 1 because it is the pitch of the hard mask pattern 210 in the column. to be. In addition, the third pitch (P 3) and the first pitch (P 1) is equal to said first pitch (P 1) is the minimum feature size if 2 times the (F minimum feature size), P x = 2P 3 Since = 2P 1 = 4F, P y = P 1 = 2F, the critical pitch Pcr is calculated by
On the other hand, Figure 7 is a layout showing the arrangement of the hard mask pattern according to the prior art. Referring to FIG. 7, the hard mask patterns 21 are tiled, arranged in the same pitch, 2F, in the odd and even rows, and arranged in the same pitch, 2F, in the odd and even rows. In this case, when the critical pitch Pcr is calculated by Equation 1, P x = 2F and P y = 2F.
Therefore, the critical pitch (Pcr of FIG. 1A) according to the present embodiment is larger than the critical pitch (Pcr of FIG. 7) according to the pre-improvement technique. Therefore, according to this embodiment, there is an effect that the threshold pitch for forming hard mask patterns is relaxed. As a result, the difficulty of the photolithography process for forming the hard mask patterns may be reduced, thereby improving the mass productivity of the semiconductor manufacturing process.
The unit cell area C is shown in FIG. 1A. The length of one side of the unit cell region C is equal to the pitch of the hard mask patterns 210 in the odd or even columns, that is, the first pitch P1, and the length of the other side is equal to the odd and the odd columns. It is equal to the pitch between even rows, that is, the third pitch P 3 . When the first pitch P 1 and the third pitch P 3 are the same and the first pitch P 1 is twice the minimum feature size F, the unit cell area C The squared feature size of is 4F 2 .
1A, 2B and 3B, The substrate 100 is etched by a predetermined depth using the hard mask patterns 210 as a mask to form first source / drain portions 105 having a pillar shape made of a substrate material. Such etching may be an anisotropic etch. Therefore, the width of the first source / drain part 105 may be the same as the width of the hard mask pattern 210, and the arrangement of the first source / drain part 105 may be the aforementioned hard mask patterns 210. May be the same as
Subsequently, the spacer material is stacked on the substrate 100 on which the first source / drain portion 105 is formed and the spacer material is etched back to form a sidewall of the first source / drain portion 105. The spacer 215 is formed in the gap. The spacer 215 may also be formed on sidewalls of the hard mask pattern 210. The spacer material may be a material having an etch selectivity with respect to the substrate 100. For example, the spacer material may be a silicon nitride film or a silicon oxynitride film.
1A, 2C, and 3C, the substrate 100 is etched by a predetermined depth using the hard mask pattern 210 and the spacer 215 as a mask. Such etching may be anisotropic etching. As a result, a pillar-shaped channel portion 110 is formed integrally with the first source / drain portion 105 and extending downwardly thereof. The channel unit 110 and the first source / drain unit 105 positioned on the channel unit 110 form an active pillar P. Referring to FIG. Accordingly, the active pillars P are formed to extend upward from the substrate 100 and have channel portions 110, respectively. In addition, since the channel part 110 and the first source / drain part 105 are formed using the hard mask pattern 210 as a mask, the active pillar P is arranged in the above-described hard mask patterns 210. ) Is equivalent to
Subsequently, sidewalls of the channel part 110 are etched by a predetermined width using the hard mask pattern 210 and the spacer 215 as a mask. As a result, the channel part 110 is recessed in the direction of the center axis of the channel part 110 by a predetermined width, and a space part is formed between the substrate 100 and the first source / drain part 105. The width of the channel unit 110 may be reduced. Etching the side wall of the channel portion 110 is preferably isotropic etching.
A gate insulating layer 112 is formed on the recessed channel portion 110. At the same time, the insulating film 112 may be formed on the substrate 100 exposed between the active pillars P. The gate insulating layer 112 is preferably a thermal oxide film formed using a thermal oxidation method, but is not limited thereto. The gate insulating film 112 may be a deposition oxide film. The gate insulating layer 112 may be a silicon oxide layer (SiO 2 ), a hafnium oxide layer (HfO 2 ), a tantalum oxide layer (Ta 2 O 5 ), or an ONO (oxide / nitride / oxide) layer.
Subsequently, a channel impurity region (not shown) may be formed in the channel portion 110 by doping the channel impurities in the channel portion 110. The channel impurity region may function to suppress a short channel effect of the transistor.
A gate conductive film is laminated on the substrate 100. The gate conductive layer may be a polysilicon layer or a silicon germanium layer doped with n-type or p-type impurities. Thereafter, the gate conductive layer is anisotropically etched to form a gate electrode 230 filling the space. In detail, the gate electrodes 230 are surround gate electrodes 230 that surround the channel portions 110, respectively.
As such, when the channel part 110 is formed to be recessed by a predetermined width in the central axis direction, when an operating voltage is applied to the gate electrode 230 surrounding the channel part 110, the recessed channel. The portion 110, that is, the channel portion 110 having a narrow width, may be fully depleted. As a result, the amount of current flowing through the channel unit 110, that is, the channel current may be increased.
1B, 2D, and 3D, bit line impurity regions 100_B are formed by doping bit line impurities in the substrate 100 exposed by the active pillars P. Referring to FIGS. The bit line impurities may be n-type impurities such as phosphorus (P) or arsenic (As), and the doping may be performed by using an ion implantation method. The bit line impurities are preferably doped with a sufficiently high dose to reduce sheet resistance.
Referring to FIGS. 1C, 2E, and 3E, a first interlayer insulating layer 220 is stacked on the substrate 100. The first interlayer insulating layer 220 may be planarized until the hard mask pattern 210 is exposed. Thereafter, a photoresist pattern (not shown) is formed on the first interlayer insulating film 220, and the first interlayer insulating film 220 is etched using the photoresist pattern as a mask to expose the substrate 100. After the etching, the exposed substrate 100 is etched by a predetermined depth. As a result, a device isolation trench 100a extending in the column direction is formed in the substrate 100 exposed between the columns of the active pillars P. As shown in FIG. The isolation trench 100a penetrates through the bit line impurity region 100_B of FIGS. 1B, 2D, and 3D. As a result, burried bit lines B / L each extending along the columns of the active pillars P are defined. A region adjacent to the active pillar P of the buried bit line B / L serves as a second source / drain portion. The buried bit lines B / L may be arranged at a third pitch P 3 .
1C, 2F, and 3F, a buried insulating layer 225 filling the device isolation trench 100a is stacked on the substrate 100 on which the device isolation trench 100a is formed. The device isolation trench 100a buried by the buried insulating layer 225 becomes a device isolation unit. Subsequently, the buried insulating layer 225 may be planarized until the hard mask pattern 210 is exposed.
1D, 2G, and 3G, a photoresist pattern (not shown) is formed on the first interlayer insulating film 220 and the buried insulating film 225, and the photoresist pattern is used as a mask. The interlayer insulating film 220 and the buried insulating film 225 are etched. As a result, grooves G that expose the active pillars P are formed in the first interlayer insulating layer 220 and the buried insulating layer 225. Specifically, each of the grooves G is located between odd rows and even rows of the active pillars P, and a portion of the active pillars P located in the odd rows and the active pillars P located in the even rows. To expose a portion of the. In other words, in plan view, the groove G is arranged to cross a portion of the active pillar located in the odd row and a portion of the active pillar P located in the even row. In addition, in the groove G, the channel portion 110 of the active pillar P, specifically, the surrounding gate electrode 230 surrounding the channel portion 110 is exposed. Meanwhile, an insulating layer covering the bit line B / L may remain at the bottom of the groove G.
1E, 2H, and 3H, a word line conductive layer is embedded in the groove G. The word line conductive layer may include a transition metal layer such as tungsten (W), cobalt (Co), nickel (Ni), and titanium (Ti), a tungsten silicide layer (WSix), a cobalt silicide layer (CoSix), or a nickel silicide layer (NiSix). And a transition metal silicide film such as a titanium silicide film (TiSix) and a tungsten nitride film (WN) / tungsten film (W).
Subsequently, the word line conductive layer is etched back to form word lines 231 in the groove G. As a result, the word line 231 is located between the odd rows and the even rows of the active pillars P, so that a portion of the channel portion 110 of the active pillars P located in the odd rows and the even rows. Wrap a portion of the channel portion 110 of the active pillar (P) located in. Further, the word line 231 electrically connects to the surrounding gate electrodes 230 positioned in the odd row and the surrounding gate electrodes 230 located in the even row. In other words, in plan view, the word line 231 is disposed to cross a portion of the active pillar P located in the odd row and a portion of the active pillar P located in the even row. Therefore, since the word line 231 is physically connected without being disconnected by the active pillar P, line resistance may be reduced. Further, the word line 231 is preferably in the form of a straight line. The word lines 231 may be arranged in a first pitch P 1 .
1E, 2I, and 3I, a second interlayer insulating layer 235 filling the groove G is stacked on a substrate on which the word line 231 is formed. Thereafter, the second interlayer insulating layer 235 is planarized until the hard mask pattern 210 is exposed.
1E, 2J, and 3J, the exposed hard mask pattern 210 and the pad oxide layer 205 disposed under the exposed hard mask pattern 210 are removed to expose the first source / drain portion 105. In this process, a portion of the spacer 215, that is, a portion formed on sidewalls of the hard mask pattern 210 and the pad oxide layer 205 may also be removed. As a result, a contact hole 235a is formed in the second interlayer insulating layer 235 to expose the first source / drain portion 105.
Subsequently, an insulating spacer layer is stacked on the substrate including the exposed first source / drain unit 105, and the insulating spacer layer is etched back to expose the surface of the first source / drain unit 105. An insulating spacer (not shown) may be formed on the sidewall of the contact hole 235a. The insulating spacer layer may be a material having an etch selectivity with respect to the second interlayer insulating layer 235 and the first source / drain part 105. For example, the insulating spacer layer may be a silicon nitride layer or a silicon oxynitride layer.
1F, 2K, and 3K, dopants are doped in the exposed first source / drain portion 105 to form a source / drain region (not shown). The impurity may be the first type impurity. Specifically, the impurities may be n-type impurities such as phosphorus (P) or arsenic (As).
Subsequently, a pad conductive film is laminated to sufficiently fill the contact hole 235a. The pad conductive layer is planarized until the surface of the second interlayer insulating layer 235 is exposed to form a contact pad 240 connected to the first source / drain portion 105 in the contact hole 235a. . The pad conductive layer may be a polysilicon layer containing n-type impurities.
An etch stop layer 243 and a mold insulating layer 245 are sequentially stacked on the substrate on which the contact pad 240 is formed. The height of the storage node electrode, which will be described later, may be determined according to the thickness of the mold insulating layer 245. The mold insulating layer 245 may be formed of a silicon oxide layer. The etch stop layer 243 is a film having an etch selectivity with respect to the mold insulating layer 245, and is formed to protect the interlayer insulating layers 220 and 235 below. When the mold insulating layer 245 is formed of a silicon oxide layer, the etch stop layer 243 may be formed of a silicon nitride layer or a silicon oxynitride layer.
After the photoresist film is formed on the mold insulating layer 245, the photoresist film is exposed using a second exposure mask in which a second exposure pattern is shown. As a result, a photoresist pattern 247 is formed on the mold insulating layer 245. Thereafter, the mold insulating layer 245 and the etch stop layer 243 are etched using the photoresist pattern 247 as a mask to form the contact pads in the mold insulating layer 245 and the etch stop layer 243. An electrode region 245a in the form of a contact hole exposing 240 is defined. Etching the mold insulating layer 245 and the etch stop layer 243 may be performed using a dry etching method capable of anisotropic etching.
Since the electrode regions 245a are formed to be aligned with the active pillars P, the electrode regions 245a are arranged in the active pillars P, that is, the hard mask patterns 210 of FIG. 1A. May be the same as Accordingly, the threshold pitch in the photolithography process for forming the electrode regions 245a may be the same as the threshold pitch in the photolithography process for forming the hard mask patterns 210 of FIG. 1A. Therefore, the difficulty of the photolithography process for forming the electrode regions 245a may be reduced, and thus the mass productivity of the semiconductor manufacturing process may be improved.
1F, 2L, and 3L, a storage conductive layer 250 having a predetermined thickness is stacked along a bottom surface and a sidewall of the electrode region 245a and an upper portion of the mold insulating layer 245. The storage conductive layer 250 may be formed using doped polysilicon, Ti, TiN, TaN, W, WN, Ru, Pt, Ir, or multiple layers thereof.
A buffer insulating layer 255 is stacked on the storage conductive layer 250. The buffer insulating layer 255 is formed to fill the inside of the electrode region 245a. Preferably, the buffer insulating layer 255 is formed using atomic layer deposition. The buffer insulating film 255 is preferably a silicon oxide film, more preferably a silicon oxide film having an etching selectivity similar to that of the mold insulating film 245.
1G, 2M, and 3M, the buffer insulating layer 255 and the storage conductive layer 250 are planarized etched until the surface of the mold insulating layer 245 is exposed. The planarization etch may be chemical mechanical polishing or etch back. As a result, the storage node electrodes 250a in the form of a cylinder covering the bottom and sidewalls of the electrode region 245a and positioned on the active pillars P and connected to the active pillars P, respectively. Is formed.
1G, 2N, and 3N, the buffer insulating layer 255 and the mold insulating layer 245 inside the electrode region 245a are removed. Removing the buffer insulating layer 255 and the mold insulating layer 245 may be performed using a wet etching solution. The wet etching solution may be diluted hydrofluoric acid (HF) solution or BOE (Buffered Oxide Etch) solution. As a result, the inner and outer surfaces of the cylindrical storage node electrode 250a are exposed, and the etch stop layer 243 is exposed around the storage node electrode 250a. As a result, formation of the storage node electrode 250a on the substrate 100 is completed. The storage node electrode 250a is connected to the contact pad 240. The storage node electrode 250a may be formed using a polysilicon film, a titanium film, a nickel film, a titanium nitride film, or a ruthenium film doped with n-type impurities. However, in another embodiment of the present invention, forming the contact pad 240 may be omitted, and in this case, the storage node electrode 250a may be formed to be directly connected to the first source / drain unit 105. Can be.
Since the arrangement of the storage node electrode 250a is limited by the electrode region 245a, the storage node electrode 250a may be the same as the arrangement of the active pillars P. In the present exemplary embodiment, a single cylinder storage (OCS) type node electrode is described as the storage node electrode 250a. However, the present invention is not limited thereto, and the plate-type storage node electrode or the active pillar P is formed on the upper side. It is also possible to apply the pillar-type storage node electrode extended to the.
Subsequently, a dielectric film (not shown) is stacked on the surface of the storage node electrode 250a, and a plate electrode (not shown) surrounding the storage node electrode 250a is formed on the dielectric film. The storage node electrode, the dielectric layer, and the plate electrode constitute a capacitor.
4A through 4D are layout views sequentially illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment of the present invention. The manufacturing method of the semiconductor device according to the present embodiment is similar to the manufacturing method of the semiconductor device described with reference to FIGS. 1A to 1G, 2A to 2N, and 3A to 3N except for arrangement of bit lines and word lines. Do.
Referring to FIG. 4A, hard mask patterns 210_1 are formed on the substrate 100_1. The hard mask patterns 210_1 may be disposed in the same manner as the hard mask patterns 210 of FIG. 1A described with reference to FIG. 1A.
Referring to FIG. 4B, the substrate 100_1 is etched using the hard mask patterns 210_1 as a mask to form active pillars P_1 having channel portions under the hard mask patterns 210_1. do. A bit line B formed in a substrate between odd and even rows of the active pillars P_1 and connected to the active pillars P_1 positioned in the odd rows and the active pillars P_1 located in the even rows. / L_1) is disposed. In this case, since the bit line B / L_1 is physically connected without being disconnected by the active pillar P_1, line resistance may be reduced. The bit lines B / L_1 may be arranged in a first pitch P 1 .
Referring to FIG. 4C, word lines 231_1 extending along the columns of the active pillars P_1 are further disposed on the substrate 100_1. When the surrounding gate electrodes surrounding the channel portions of the active pillars P_1 are positioned at the outer circumferences of the active pillars P_1, the word lines 231_1 are connected to the surrounding gate electrodes located in the respective columns. Connect electrically. The word lines 231_1 may be arranged as a third pitch P 3 .
Referring to FIG. 4D, storage node electrodes 250a_1 are connected to the active pillars P_1 on the active pillars P_1. The arrangement of the storage node electrodes 250a_1 may be the same as the arrangement of the active pillars P_1.
5A to 5D are layout views sequentially illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment of the present invention. The method of manufacturing a semiconductor device according to the present exemplary embodiment is similar to the method of manufacturing the semiconductor device described with reference to FIGS. 1A to 1G, 2A to 2N, and 3A to 3N except for arrangement of storage node electrodes.
5A through 5D, the hard mask patterns 210_2, the active pillars P_2, the bit lines B / L_2, and the word lines 231_2 may include the hard mask patterns described with reference to FIGS. 1A through 1G. Fields 210, active pillars P, bit lines B / L, and word lines 231, respectively. However, the storage node electrodes 250a_2 are tiled unlike the storage node electrodes 250a of FIG. 1G described with reference to FIG. 1G. Specifically, the storage node electrodes 250a_2 are arranged in the first pitch P 1 in all the columns and in the third pitch P 3 in all the rows. The first pitch P 1 may be 2/3 to 3/2 times greater than the third pitch P 3 . In an embodiment, the first pitch P 1 may be the same as the third pitch P 3 . In addition, even-numbered rows of the storage node electrodes 250a_2 may not be shifted by a predetermined pitch with respect to odd-numbered columns. In plan view, the storage node electrodes 250a_2 are disposed to overlap the upper portion of the active pillar P_2 positioned in the odd row and overlap the lower portion of the active pillar P_2 positioned in the even row.
In manufacturing the semiconductor device according to the present embodiment, the critical pitch of the photolithography process for forming the storage node electrodes 250a_2 is not relaxed, but the photolithography process for forming the hard mask patterns 210_2. The critical pitch of can be relaxed.
6A through 6D are layout views sequentially illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment of the present invention. The method of manufacturing a semiconductor device according to the present embodiment may include the method of manufacturing the semiconductor device described with reference to FIGS. 1A to 1G, 2A to 2N, and 3A to 3N except for the arrangement of a hard mask pattern and an active pillar. similar.
Referring to FIG. 6A, the hard mask patterns 210_3 are tiled. Specifically, the hard mask patterns 210_3 are arranged in the first pitch P 1 in all the columns, and are arranged in the third pitch P 3 in all the rows. The first pitch P 1 may be 2/3 to 3/2 times greater than the third pitch P 3 . In an embodiment, the first pitch P 1 may be the same as the third pitch P 3 . In addition, even numbers of the hard mask patterns 210_3 may not be shifted by a predetermined pitch with respect to odd columns. The substrate 100_3 is etched using the hard mask patterns 210_3 as a mask to form active pillars P_3 having channel portions under the hard mask patterns 210_3. Therefore, the active pillars P_3 and the hard mask patterns 210_3 have the same arrangement.
Referring to FIG. 6B, a bit line B / L_3 extending along the column of the active pillars P_3 may be disposed in the substrate 100_3.
Referring to FIG. 6C, word lines 231_3 extending along the rows of the active pillars P_3 are further disposed on the substrate 100_3. When the surrounding gate electrodes surrounding the channel portions of the active pillars P_3 are positioned on the outer circumferences of the active pillars P_3, the respective word lines 231_3 are surrounded by the surrounding gate electrodes in each row. Electrically connected to
Alternatively, the bit line B / L_3 may extend along the row of the active pillars, and the word line 231_3 may extend along the column of the active pillars.
Referring to FIG. 6D, storage node electrodes 250a_3 respectively connected to the active pillars P_3 are disposed on the active pillars P_3. The storage node electrodes 250a_3 are identical to the arrangement of the storage node electrodes 250a of FIG. 1G described with reference to FIG. 1G. Accordingly, the storage node electrodes 250a_3 are arranged in the first pitch P 1 in odd and even columns, and the storage node electrodes 250a_3 arranged in the even rows are stored in the odd columns. The second pitch P 2 is shifted with respect to the node electrodes 250a_3. In addition, the odd columns and the even columns may be arranged in a third pitch P 3 . In plan view, the storage node electrodes 250a_3 are disposed to overlap the lower portion of the active pillar P_3 positioned in the odd column and overlap the upper portion of the active pillar P_3 positioned in the even column.
On the other hand, the second pitch (P 2) is to 2/3 times the first pitch may be one half of (P 1), said first pitch (P 1) has a third pitch (P 3) It may be 3/2 times.
In manufacturing the semiconductor device according to the present embodiment, the critical pitch of the photolithography process for forming the hard mask patterns 210_3 is not relaxed, but the photolithography process for forming the storage node electrodes 250a_3. The critical pitch of can be relaxed.
As described above, according to the present invention, in manufacturing a vertical channel transistor, active pillars and / or storage node electrodes are arranged at a first pitch in odd and even columns, and active pillars arranged in the even columns. And / or photolithography for forming the active pillars and / or storage node electrodes by shifting and arranging storage node electrodes by a second pitch relative to active pillars and / or storage node electrodes arranged in the odd rows. The critical pitch of the process can be relaxed. As a result, the difficulty of the photolithography process can be reduced.
A plurality of active pillars extending upwardly from the substrate and having channel portions, respectively;
The active pillars are arranged at a first pitch in odd and even columns, and the active pillars arranged in the even rows are shifted by a second pitch with respect to the active pillars arranged in the odd columns, and the odd and even columns And the rows are arranged in a third pitch.
And a word line positioned between the odd and even rows of the active pillars, the word line surrounding a portion of the channel portion of the active pillar located in the odd row and a portion of the channel portion of the active pillar located in the even row. device.
Further comprising surrounding gate electrodes surrounding respective channel portions of the active pillars,
And the word line is electrically connected to the surrounding gate electrodes positioned in the odd row and the surrounding gate electrodes located in the even row.
And the word lines are arranged in a first pitch.
And bit lines in the substrate, each of which extends along the rows of the active pillars.
And the bit lines are arranged at a third pitch.
And a bit line formed in the substrate between the odd and even rows of the active pillars and connected to the active pillars located in the odd row and the active pillars located in the even row.
And the bit lines are arranged in a first pitch.
And word lines extending along the columns, respectively.
Wherein each word line is electrically connected to surrounding gate electrodes located in each column.
And the word lines are arranged at a third pitch.
And storage node electrodes disposed on the active pillars and connected to the active pillars, respectively.
And the array of storage node electrodes is the same as the array of active pillars.
And the storage node electrodes are tiled and arranged to have a first pitch and a third pitch in columns and rows, respectively.
And the second pitch is 1/2 of the first pitch.
The first pitch is a semiconductor device, characterized in that 2/3 times to 3/2 times the third pitch.
A plurality of active pillars extending in an upward direction from the substrate and having channel portions, respectively, arranged in a checkerboard shape having a first pitch and a third pitch in columns and rows, respectively; And
Storage node electrodes are connected to the active pillars on the active pillars, respectively, and the storage node electrodes are arranged at a first pitch in odd and even rows, and the storage node electrodes are arranged in the even rows. And shifted by a second pitch with respect to the storage node electrodes arranged in the odd rows, wherein the odd columns and the even columns are arranged in the third pitch.
And a word line extending along the row of active pillars and a bit line extending along the column of active pillars.
And a wordline extending along the column of active pillars and a bitline extending along the row of active pillars.
And the first pitch is 2/3 to 3/2 times the third pitch.
KR1020060046544A 2006-05-24 2006-05-24 Semiconductor device including vertical channel transistor KR100771871B1 (en)
KR1020060046544A KR100771871B1 (en) 2006-05-24 2006-05-24 Semiconductor device including vertical channel transistor
US11/802,647 US20070284623A1 (en) 2006-05-24 2007-05-24 Semiconductor device having vertical channel transistor
KR100771871B1 true KR100771871B1 (en) 2007-11-01
ID=38820997
US (1) US20070284623A1 (en)
KR (1) KR100771871B1 (en)
KR101132301B1 (en) 2008-02-29 2012-04-05 주식회사 하이닉스반도체 Method of manufacturing semiconductor device
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US8362536B2 (en) 2010-05-20 2013-01-29 Samsung Electronics Co., Ltd. Semiconductor device having vertical channel transistor and methods of fabricating the same
KR101543516B1 (en) * 2013-08-16 2015-08-11 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor arrangement with one or more semiconductor columns
KR101417764B1 (en) 2008-09-26 2014-07-09 삼성전자주식회사 Vertical semiconductor device and method for manufacturing the same
JP5680801B1 (en) * 2013-06-10 2015-03-04 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Semiconductor device manufacturing method and semiconductor device
JP5731073B1 (en) * 2013-06-17 2015-06-10 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Semiconductor device manufacturing method and semiconductor device
JP5872054B2 (en) * 2013-06-17 2016-03-01 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Semiconductor device manufacturing method and semiconductor device
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2006-05-24 KR KR1020060046544A patent/KR100771871B1/en not_active IP Right Cessation
2007-05-24 US US11/802,647 patent/US20070284623A1/en not_active Abandoned
US10294101B2 (en) 2013-08-16 2019-05-21 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement with one or more semiconductor columns
US10290737B2 (en) 2013-08-16 2019-05-14 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement with one or more semiconductor columns
US20070284623A1 (en) 2007-12-13
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