Source: http://www.google.com/patents/US4812969?dq=6322901
Timestamp: 2015-08-02 02:20:04
Document Index: 645243037

Matched Legal Cases: ['art 2', 'art 2', 'art 2', 'art 1', 'art 2', 'art 2']

Patent US4812969 - Address translation unit - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn address translation unit for use in a computer system having a multi-virtual space comprises a full associative translation lookaside buffer (TLB) which includes, for each entry, an associative memory array which stores and compares addresses. The associative memory array is provided with a circuit...http://www.google.com/patents/US4812969?utm_source=gb-gplus-sharePatent US4812969 - Address translation unitAdvanced Patent SearchPublication numberUS4812969 APublication typeGrantApplication numberUS 06/865,840Publication dateMar 14, 1989Filing dateMay 22, 1986Priority dateMay 24, 1985Fee statusPaidPublication number06865840, 865840, US 4812969 A, US 4812969A, US-A-4812969, US4812969 A, US4812969AInventorsKatsuaki Takagi, Hirokazu Aoki, Norio Nakagawa, Yoshimune HagiwaraOriginal AssigneeHitachi, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (7), Referenced by (27), Classifications (7), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetAddress translation unit
US 4812969 AAbstract
An address translation unit for use in a computer system having a multi-virtual space comprises a full associative translation lookaside buffer (TLB) which includes, for each entry, an associative memory array which stores and compares addresses. The associative memory array is provided with a circuit which, when a specific value is set in a common area field, invalidates comparison in a space number field.
1. An address translation unit including an associative translation look aside buffer (TLB) comprising:(A) an associative array portion including a plurality of entries, each of which includes(a) a common area flag field for storing flag information indicating whether a predetermined logical address corresponds to a common area in a multi-virtual space, wherein either one of the programs and data commonly used by devices accessing said multi-virtual space are disposed in said common area, (b) a space number field for storing a logical address value, (c) a logical address field for storing a logical address value, (d) a coincidence detection line disposed along said space number field and said logical address field, (e) means for comparing an input space number with a first value stored in said space number field, for comparing an input logical address with a second value stored in said logical address field, for generating a coincidence output on said coincidence detection line when said input space number and said input logical address coincide with said first and said second values, respectively, and for generating said coincidence output on said coincidence detection line when said flag information stored in said common area flag field indicates that said logical address value stored in said logical address field corresponds to said common area in said multi-virtual space and when said input logical address coincides with said second value stored in said logical address field, regardless of said first value stored in said space number field; and (B) a data portion including(a) means for selecting one of a plurality of physical addresses in response to outputs on said coincidence detection line of said associative array portion. 2. An address translation unit as claimed in claim 1, wherein each of said plurality of entries of said associative array portion further includes;a switching element disposed midway of said coincidence detection line to be turned on and off depending on a value of a memory cell storing said flag information of said common area flag field; wherein said space number field includes an array of first memory cells connected to said coincidence detection line on a first side of said switching element, for storing said space number value, and wherein said logical address field includes an array of second memory cells connected to said coincidence detection line on a second side of said switching element, for storing said logical value, wherein said switching element is turned off depending on said value of said memory cell storing said flag information so as to ignore said first value stored in said array of first memory cells. 3. An address translation unit as claimed in claim 1, wherein said space number field of said associative array portion further includes a mask flag cell for storing data, so that said value of said space number field can be masked by a mask pattern depending on the data stored in said mask flag cell.
This invention relates to an address translation unit suitable for use in a computer system, especially, a microcomputer system having a multi-virtual space.
It is a primary object of the present invention to provide an address translation unit including a full associative TLB for use in a system having a multi-virtual space, in which the TLB includes, for each entry, a space number field, a common area flag field and a logical address field, and comparison between space numbers is not done when a common area flag is set already in the common area flag field.
FIG. 1 is a block diagram of a full associative TLB employed in an embodiment of the present invention.
Preferred embodiments of the address translation unit according to the present invention will be described with reference to the drawings.
The operation of the TLB shown in FIG. 1 will be numerically described with reference to FIG. 2. Suppose now that the contents of the entries No. 0 to No. 4 are as illustrated. It will be seen that the valid flag V is "0" in the case of the entry No. 4, and this entry No. 4 is excepted from the object of comparison. The values of the logical address fields 104 are the same in the case of the entries No. 1 and No. 2. However, they are separate spaces, because the common area flags C are "0", and the space number fields 103 have different values "5" and "3". Therefore, the corresponding physical addresses are PA1 and PA2 which are different from each other. In the case of the entry No. 3, the common area flag C is "1". Therefore, regardless of the value of the space number field 103, it is deemed that coincidence is reached in the result of space number comparison.
Suppose that a space number SN="3" and a logical address LA=LA1 are applied as inputs to the TLB. Then, coincidence occurs in the entry No. 2, and the coincidence detection signal 112 is selected. Consequently, the physical address PA2 appears at the output of the data part 2.
On the other hand, when the space number input SN is SN="1", and the logical address input LA is LA=LA3, there is no entry where the space number SN coincides with the space number data. However, in the case of the entry No. 3 where the common area flag C is "1", it is deemed that coincidence is attained for all the values of the space number SN. On the other hand, from the aspect of comparison of the logical address LA, coincidence is attained in the entry No. 3 where the logical address is LA3. Thus, the entry No. 3 is selected, and the coincidence detection signal 113 is selected. Consequently, the physical address PA3 appears at the output of the data part 2.
DSi -DSO, DC and DLj -DLO. The write on the lines operation into the data part 2 is carried out by firstly having the associative array part associative with a predetermined pattern to set either one of the coincidence detection signal lines to "1", so that the transistors 221 and 222 of the data cell 220 are turned on. Then, the write operation is completed by setting the line WDE
to "1" and setting the write data on the lines DPk -DPO.
In the address translation, let us assume that necessary information has already been set in the associative array part 1 and the data part 2 before the address translation. It is also noted that each of the lines WCE, WDE, WO -Wn is fixed to "0". Before initiating the address translation, the line PCG is set to "1" and the coincidence detection lines 110a, 110b and the data lines 251, 252 are precharged. At this time, the line tH is set to "0" to control the word line 110c of the data part 2 to become "0". Thereafter, when PCG is set to "0", with the retrieval information being set on the lines DSi -DSO and DLj -DLO, the information is compared with the data stored in each address cell 120. As the result of the comparison in all the cells, only the coincidence detection line 110b of the entry that brings about coincidence is set to "1". At this time, if the common flag cell 130 in an entry stores "0", the comparison with all the data of SN, LA and V is carried out. However, if the common flag cell in an entry stores "1", the comparison with the data of only LA and V is carried out, and the coincidence detection line 110a which indicates the comparison result with the data of SN is isolated so as to be omitted from the object of the comparison. Thus, when the timing signal tH is set to "1" at the time the level of the coincidence detection line 110b has been established, the result of the coincidence detection is delivered to the word line 110c, and the content of the data cell 220 to the coincident entry is outputted on the data lines 251 and 252. The data on the data lines 251 and 252 are then inputted to the sense amplifier 240, and the amplified data are outputted on the read-out information lines RPk -RPO. In this way, the logical address LA can be translated into the physical address PA on the lines RPk -RPO.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4068303 *Mar 22, 1976Jan 10, 1978Hitachi, Ltd.Address translation managing system with translation pair purgingUS4376297 *Jun 2, 1980Mar 8, 1983Signetics CorporationVirtual memory addressing deviceUS4453230 *Jun 21, 1982Jun 5, 1984Tokyo Shibaura Electric Co., Ltd.Address conversion systemUS4456954 *Jun 15, 1981Jun 26, 1984International Business Machines CorporationVirtual machine system with guest architecture emulation using hardware TLB's for plural level address translationsUS4551797 *Aug 31, 1983Nov 5, 1985Amdahl CorporationApparatus for reverse translationUS4612612 *Aug 30, 1983Sep 16, 1986Amdahl CorporationVirtually addressed cacheUS4733350 *Dec 17, 1984Mar 22, 1988Fujitsu LimitedImproved purge arrangement for an address translation control system* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS4922415 *Mar 1, 1985May 1, 1990Hemdal Goran A HData processing system for converting virtual to real addresses without requiring instruction from the central processing unitUS4943913 *Feb 10, 1988Jul 24, 1990International Business Machines CorporationOperating system accessing control blocks by using home address space segment table to control instruction and operand fetch and store operationsUS4985828 *Feb 16, 1988Jan 15, 1991Hitachi, Ltd.Method and apparatus for generating a real address multiple virtual address spaces of a storageUS5045996 *Nov 15, 1989Sep 3, 1991Xerox CorporationMultiprocessor cache memory housekeepingUS5123101 *Aug 23, 1989Jun 16, 1992Xerox CorporationMultiple address space mapping technique for shared memory wherein a processor operates a fault handling routine upon a translator missUS5129071 *Apr 3, 1989Jul 7, 1992Hitachi, Ltd.Address translation apparatus in virtual machine system using a space identifier field for discriminating datoff (dynamic address translation off) virtual machinesUS5237671 *Jun 14, 1989Aug 17, 1993Silicon Graphics, Inc.Translation lookaside buffer shutdown schemeUS5239635 *Dec 10, 1991Aug 24, 1993Digital Equipment CorporationVirtual address to physical address translation using page tables in virtual memoryUS5263140 *Jan 23, 1991Nov 16, 1993Silicon Graphics, Inc.Variable page size per entry translation look-aside bufferUS5295251 *Sep 21, 1990Mar 15, 1994Hitachi, Ltd.Method of accessing multiple virtual address spaces and computer systemUS5317710 *Apr 3, 1991May 31, 1994Hitachi, Ltd.Invalidation of entries in a translation table by providing the machine a unique identification thereby disallowing a match and rendering the entries invalidUS5325507 *Feb 18, 1993Jun 28, 1994Silicon Graphics, Inc.Translation lookaside buffer shutdown schemeUS5712998 *Mar 19, 1996Jan 27, 1998Intel CorporationFast fully associative translation lookaside buffer with the ability to store and manage information pertaining to at least two different page sizesUS5890220 *May 31, 1995Mar 30, 1999Hitachi, Ltd.Address conversion apparatus accessible to both I/O devices and processor and having a reduced number of index buffersUS6026476 *Aug 6, 1997Feb 15, 2000Intel CorporationFast fully associative translation lookaside bufferUS6047362 *Nov 8, 1996Apr 4, 2000Sun Microsystems, Inc.Delayed removal of address mapping for terminated processesUS6112278 *Sep 30, 1996Aug 29, 2000Lsi Logic CorporationMethod to store initiator information for SCSI data transferUS6266755 *Dec 23, 1996Jul 24, 2001Mips Technologies, Inc.Translation lookaside buffer with virtual address conflict preventionUS7165164Sep 24, 2003Jan 16, 2007Intel CorporationMethod and apparatus including heuristic for sharing TLB entriesUS7194597Dec 22, 2005Mar 20, 2007Intel CorporationMethod and apparatus for sharing TLB entriesUS8751797 *Apr 7, 2008Jun 10, 2014Stmicroelectronics (Research & Development) LimitedIntegrated circuit with restricted data accessUS20080250228 *Apr 7, 2008Oct 9, 2008Stmicroelectronics LimitedIntegrated circuit with restricted data accessCN1315060C *Mar 7, 2002May 9, 2007智权第一公司Transfer translation sideviewing buffer for storing memory type dataEP0491498A2 *Dec 3, 1991Jun 24, 1992Sun Microsystems, Inc.Apparatus and method for a space saving translation lookaside buffer for content addressable memoryEP0496288A2 *Jan 17, 1992Jul 29, 1992Mips Computer Systems, Inc.Variable page size per entry translation look-aside bufferEP0717360A2 *Oct 24, 1995Jun 19, 1996International Business Machines CorporationProcessing system for performing address translations and method of operationWO1996012231A1 *Oct 13, 1995Apr 25, 1996Silicon Graphics IncA translation buffer for detecting and preventing conflicting virtual addresses from being stored therein* Cited by examinerClassifications U.S. Classification711/209, 711/207, 711/E12.065International ClassificationG06F12/10, G06F12/08Cooperative ClassificationG06F12/1036European ClassificationG06F12/10L2Legal EventsDateCodeEventDescriptionMay 22, 1986ASAssignmentOwner name: HITACHI, LTD.,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TAKAGI, KATSUAKI;AOKI, HIROKAZU;NAKAGAWA, NORIO;AND OTHERS;REEL/FRAME:004560/0819Effective date: 19860515Jun 29, 1992FPAYFee paymentYear of fee payment: 4Sep 3, 1996FPAYFee paymentYear of fee payment: 8Aug 30, 2000FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services