Source: http://www.google.de/patents/US5869843
Timestamp: 2013-05-19 09:47:25
Document Index: 371907876

Matched Legal Cases: ['art 2', 'art 2', 'art 2', 'art 2', 'art 1', 'art 1']

Patent US5869843 - Memory array having a multi-state element and method for forming such array ... - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr » Erweiterte Patentsuche | Webprotokoll | Anmelden Erweiterte Patentsuche PatenteA memory device having a plurality of memory arrays. Each array has a plurality of memory cells, each memory cell including an electrode defining a respective contact area. Each memory array is formed by depositing a continuous chalcogenide layer. This chalcogenide layer, even when continuous, will have...http://www.google.de/patents/US5869843?utm_source=gb-gplus-sharePatent US5869843 - Memory array having a multi-state element and method for forming such array or cells thereof Ver�ffentlichungsnummerUS5869843 APublikationstypErteilung Anmeldenummer08/486,639 Ver�ffentlichungsdatum9. Febr. 1999Eingetragen7. Juni 1995 Priorit�tsdatum7. Juni 1995Auch ver�ffentlicht unterUS6077729WO1996041380A1 ErfinderSteven T. HarshfieldUrspr�nglich Bevollm�chtigterMicron Technology, Inc.Round Rock Research, Llc US-Klassifikation257/5257/3257/E27.4257/2257/4Internationale KlassifikationH01L27/115H01L27/24H01L29/792H01L21/8247H01L29/788H01L27/105G11C11/56 UnternehmensklassifikationH01L27/24 Europ�ische KlassifikationH01L27/24ReferenzenPatentzitate (36)Nichtpatentzitate (22) Referenziert von (347)Externe LinksUSPTO USPTO-Zuordnung EspacenetMemory array having a multi-state element and method for forming such array or cells thereofUS 5869843 A Zusammenfassung A memory device having a plurality of memory arrays. Each array has a plurality of memory cells, each memory cell including an electrode defining a respective contact area. Each memory array is formed by depositing a continuous chalcogenide layer. This chalcogenide layer, even when continuous, will have active areas formed above the electrodes, and a conductive layer electrically coupling at least a portion of the active areas. The memory array can also include a dielectric volume surrounding at least a portion of the plurality of electrodes. The electrodes can be contacts, plugs or pillars deposited in etched openings in the dielectric volume.
What is claimed is: 1. A memory array having a plurality of memory cells, at least a portion of said memory array comprising: a substrate; a dielectric layer disposed on said substrate; a plurality of individual conductive members being formed in said dielectric layer and being coupled to said substrate, said plurality of individual conductive members being arranged in rows; a plurality of strips of multi-state material, one respective strip of multi-state material disposed on each of the respective rows of said plurality of individual conductive members; and a plurality of strips of conductive material, one respective strip of conductive material disposed on each respective strip of multi-state material.
10. A memory array having a plurality of memory cells, at least a portion of said memory array comprising: a substrate; a dielectric layer disposed on said substrate; a plurality of individual conductive members being formed in said dielectric layer, a first end portion of each of said plurality of individual conductive members extending above said dielectric layer and a second end portion of each of said plurality of individual conductive members being coupled to said substrate; a plurality of dielectric spacers, each of said plurality of dielectric spacers being disposed about a respective first end portion of said plurality of individual conductive members; a continuous layer of multi-state material disposed on a first plurality of said plurality of individual conductive members; and a continuous layer of conductive material disposed on said continuous layer of multi-state material.
14. A memory array having a plurality of memory cells, at least a portion of said memory array comprising: a plurality of individual conductive members being arranged in rows, each of said plurality of individual conductive members having a width; a plurality of strips of multi-state material, a respective one of said plurality of strips of multi-state material being disposed on a respective one of said rows of said plurality of individual conductive members, each of said plurality of strips of multi-state material having a width greater than the width of said individual conductive members in said respective one of said rows; and a plurality of strips of conductive material, a respective one of said plurality of strips of conductive material being disposed on a respective one of said plurality of strips of multi-state material.
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