Source: http://www.google.com/patents/US4731678?ie=ISO-8859-1&dq=inassignee:doubleclick
Timestamp: 2014-08-27 11:44:20
Document Index: 88439565

Matched Legal Cases: ['art 62', 'art 62', 'art 64', 'art 64', 'art 66', 'art 67', 'art 69', 'art 69', 'art 62']

Patent US4731678 - Digital data recording and reproducing method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA digital data recording and reproducing method in which a digital data sequence is divided into 8-bit digital data sequences. When the divided 8-bit digital data sequences are encoded into 14-bit code, an 8-bit digital data sequence wherein the value of its DSV (digital sum variation) is limited to...http://www.google.com/patents/US4731678?utm_source=gb-gplus-sharePatent US4731678 - Digital data recording and reproducing methodAdvanced Patent SearchPublication numberUS4731678 APublication typeGrantApplication numberUS 06/832,774Publication dateMar 15, 1988Filing dateFeb 25, 1986Priority dateFeb 25, 1985Fee statusPaidAlso published asDE3682412D1, EP0193153A2, EP0193153A3, EP0193153B1Publication number06832774, 832774, US 4731678 A, US 4731678A, US-A-4731678, US4731678 A, US4731678AInventorsKousou TakeuchiOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManReferenced by (29), Classifications (13), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetDigital data recording and reproducing methodUS 4731678 AAbstract A digital data recording and reproducing method in which a digital data sequence is divided into 8-bit digital data sequences. When the divided 8-bit digital data sequences are encoded into 14-bit code, an 8-bit digital data sequence wherein the value of its DSV (digital sum variation) is limited to a predetermined range is selected from two codes which are assigned to correspond to the 8-bit digital data sequence. In the encoding process, the number of "0" bits which are inserted between two "1" bits in the code sequence is restricted to a number of from one to eight so that the DC component in the code sequence can be eliminated. A bit sequence which never arises in two successive 14-bit code words may then be used as a frame synchronizing signal.
What is claimed is: 1. A digital data recording and reproducing method, comprising the steps of:dividing a string of inputted digital data into successive 8-bit information words; assigning to each 8-bit information word at least one 14-bit NRZI code word in which the number of "0" bits inserted between two successive "1" bits in each 14-bit NRZI code word is between one and eight, inclusive; determining the digital sum variation of the preceding 14-bit NRZI code words forming an NRZI coded waveform representative of successive 8-bit information words in said string of inputted digital data; and selecting one of said assigned 14-bit NRZI code words to represent the next 8-bit information word divided from said string of inputted digital data as a function of the polarity of an NRZI code word digital sum of said selected one 14-bit NRZI code word and the polarity of the determined digital sum variation sum that said selected one 14-bit NRZI code word tends to decrease the absolute value of the digital sum variation of the NRZI coded waveform. 2. A digital data recording and reproducing method in accordance with claim 1, wherein said assigning step comprises the steps of:calculating the NRZI code word digital sum of respective 14-bit NRZI code words assigned to each of said 8-bit information words; assigning a 14-bit code in which the calculated code word digital sum is zero to one of said 8-bit information words by one-to-one correspondence; and assigning a pair of 14-bit codes in which the calculated code word digital sums have different absolute values and are greater than and less than zero, respectively, to another one of said 8-bit information words by one-to-one correspondence. 3. A digital data recording and reproducing method in accordance with claim 2, wherein said selecting step comprises the steps of:determining whether the calculated code word digital sums are positive or zero when the digital sum variation of the preceding 14-bit NRZI code words is positive and the polarity of the last bit of the immediately preceding 14-bit NRZI code word of said NRZI coded waveform is positive and when the digital sum variation of the preceding 14-bit NRZI code words is negative and the polarity of the last bit of the immediately preceding 14-bit NRZI code word of said NRZI coded waveform is negative; and determining whether the calculated code word digital sums are negative or zero when the digital sum variation of the preceding 14-bit NRZI code words is positive and the polarity of the last bit of the immediately preceding 14-bit NRZI code word of said NRZI coded waveform is negative and when the digital sum variation of the preceding 14-bit NRZI code words is negative and the polarity of the last bit of the immediately preceding 14-bit NRZI code word of said NRZI coded waveform is positive. 4. An apparatus for recording and reproducing digital data, comprising:means for dividing a string of inputted digital data into successive 8-bit information words; means for assigning to each successive 8-bit information word at least one 14-bit NRZI code word in which the number of "0" bits inserted between two successive "1" bits in each 14-bit code word is between one and eight, inclusive; means for issuing a control signal for selecting one of said assigned 14-bit NRZI code words assigned to said 8-bit information words as a function of the polarity of an NRZI code word digital sum of said assigned 14-bit NRZI code words and the polarity of the digital sum variation of the preceding 14-bit NRZI code words forming an NRZI coded waveform representative of successive 8-bit information words in said string of inputted digital data such that said selected one 14-bit NRZI code word tends to decrease the absolute value of the digital sum variation of the NRZI coded waveform; and means responsive to said control signal for selecting said one assigned 14-bit NRZI code word to represent an inputted 8-bit information word divided from said string of inputted digital data. 5. An apparatus for recording and reproducing digital data in accordance with claim 4, wherein said control signal issuing means comprises:means for calculating a variation of the digital sum variation of the preceding 14-bit NRZI code words which will be caused by said selected one 14-bit NRZI code word; means for adding said variation of the digital sum variation to the digital sum variation of the preceding 14-bit NRZI code words; means for storing the sum outputted by said adding means; and means for discriminating an updated value of the digital sum variation as the sum from said adding means stored in said storing means. 6. An apparatus for recording and reproducing digital data in accordance with claim 4, wherein said control signal issuing means comprises:means for determining whether the code word digital sum of said selected one 14-bit NRZI code word is positive or zero when the digital sum variation of the preceding 14-bit NRZI code words and the last bit of the immediately preceding 14-bit NRZI code word of said NRZI coded waveform have the same non-zero polarity and for determining whether the code word digital sum of said selected one 14-bit NRZI code word is negative or zero when the digital sum variation of the preceding 14-bit NRZI code words and the last bit of the immediately preceding 14-bit NRZI code word of said NRZI coded waveform have different non-zero polarities. 7. An apparatus for recording and reproducing digital data in accordance with claim 4, further comprising means for adding a frame synchronizing signal at predetermined intervals to the NRZI coded waveform comprised of successive 14-bit NRZI code words, said frame synchronizing signal being a bit sequence which never occurs in two successive 14-bit NRZI code words.
8. An apparatus for recording and reproducing digital data in accordance with claim 7, wherein said frame synchronizing signal is an N-bit sequence (N≧16) including a pattern "1000000010000000" which does not coincide with any continuous 16-bit code sequence formed by any successive 14-bit NRZI code words in said NRZI coded waveform.
The present invention relates generally to a digital data processing method, and more particularly, to a new and improved method for encoding and reproducing binary digital data and for recording a synchronizing signal thereof.
When digital data are recorded on a magnetic tape or are reproduced therefrom by using a rotary magnetic head, encoded binary signals corresponding to the digital data are generally transmitted to the rotary magnetic head through a rotary transformer. If the encoded binary signals contain a DC component, however, these signals are not normally recorded on the magnetic tape since the rotary transformer does not transmit the DC component.
A prior art device for eliminating the DC component of the encoded binary signals is shown in U.S. Pat. No. 4,216,460. In this patent, the 8-bit word is transformed into a 10-bit code word; however, the density ratio is smaller than 1, the density ratio being defined as: Density ratio=Tmin/T, where T is the cyclic time of the data bit and Tmin is the minimum magnetization reversal interval.
In other prior art, such as U.S. Pat. No. 4,323,931, a three position modulation method, which is a high density modulation method, is disclosed. The density ratio of this method is greater than 1, but the DC component in the encoded binary signal is not eliminated.
In the conventional digital data recording method, the digital data sequence is divided into predetermined data units. A frame synchronizing signal and an error detection code are added to each data unit, thereby forming a frame of data. The frame with the frame synchronizing signal and the error detecting code is encoded and recorded on a recording medium. During the reproducing process, the frame synchronizing signal is detected from the reproduced code sequence. The detected frame synchronizing signals are used for synchronization of clock signals and for control of the starting point, whereby the respective units of the digital data are distinguished from each other. As mentioned above, since the frame synchronizing signal has an important function, it must be surely detected.
Thus, in the prior art a method must be selected from the many kinds of methods for avoiding misdetection of the frame synchronizing signal when the position of a bit is shifted to an abnormal position. A special bit sequence, for example, a bit sequence with a long magnetization reversal interval, is thus frequently adopted. However, the plural bit sequence may exist in the code sequence and there is thus a fear of misdetection of the frame synchronizing signal. In order to avoid the above-mentioned misdetection, a protection circuit for the synchronizing signal which cyclically issues the frame synchronizing signal is necessary. Nevertheless, there is a defect in such a circuit in that when the frame synchronizing signals of continuous data units are not detected due to dropout of the recording medium, a comparatively long time is required for resumption of the certain detection of the frame synchronizing signals. Therefore, it is required to select the most suitable protection circuit system for the synchronizing signal in accordance with the function of the recording and reproducing apparatus. These circuits are generally formed by complex circuits; hence, a careful design of the system is required.
OBJECT AND SUMMARY OF THE INVENTION An object of the present invention is to provide a digital encoding method having a high density ratio for magnetic recording wherein the DC component of a code sequence is small and a magnetization reversal interval is minimized.
Another object of the present invention is to provide a digital encoding method wherein a digital data sequence is cut into equal predetermined sections of digital data and a frame synchronizing signal and an error detecting code may be added to each digital data unit. As a result, when the digital data is reproduced, misdetection of the frame synchronizing signal decreases. In this specification, the high level and the low level of the encoded signal are shown by representations of "1" and "0", respectively.
In order to realize the first object, the digital data sequence is divided into 8-bit digital data, and every 8-bit digital data sequence is encoded into 14-bit NRZI (nonreturn-to-zero inverted)) codes, wherein when this 8-bit digital data is encoded, the number of bits of value "0" which are inserted between two bits of value "1" are restricted to less than or equal to eight bits.
In order to realize the second object, the 8-bit digital data is encoded into a 14-bit NRZI code sequence, an optionally selected successive 16-bit code is taken out from the 14-bit code sequence, and the 16-bit code is made so that it does not coincide with an N bit code sequence (N>16) including a bit sequence "1000000010000000". The N bit code sequence is then recorded as a frame synchronizing signal on a recording medium.
The digital data recording and reproducing method in accordance with the present invention thus comprises:
dividing inputted digital data into 8-bit digital data words,
selecting one of two codes wherein an absolute value of the digital sum variation of the NRZI coded input waveform in which a code sequence of the digital data is encoded to NRZI code decreases, the selected code being selected such that the number of "0" bits inserted between two "1" bits in a code sequence is restricted to a number from one to eight when the 8-bit digital data is allotted to one or two codes,
producing NRZI coding of a code sequence in which an 8-bit digital data word is sequentially coded,
issuing a control signal which selects a 14-bit code wherein an absolute value of the digital sum variation of a waveform of the NRZI code decreases, and
issuing a 14-bit code corresponding to the 8-bit digital data word by inputting the control signal.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an encoder for use in the digital data recording and reproducing method in accordance with the present invention.
FIG. 2 is a timing chart showing a change of polarity in a digital code sequence and a change of DSV (digital sum variation) in a code sequence wherein an eight bit digital data word is encoded into 14-bit code, in accordance with the embodiment of the present invention.
FIG. 3 is a timing chart showing an operation of the encoder in the embodiment in accordance with the present invention.
FIG. 4 is a circuit diagram of a decoder in the embodiment in accordance with the present invention.
FIG. 5 is a timing chart showing an operation of the decoder shown in FIG. 4.
FIG. 6(a) is a block diagram of an encoding and a recording circuit in the embodiment in accordance with the present invention.
FIG. 6(b) is a block diagram of a decoding and reproducing circuit in the embodiment in accordance with the present invention.
FIG. 7 is a frame construction in the embodiment in accordance with the present invention.
FIG. 8 is a circuit diagram of the circuit for adding the frame synchronizing signal of the embodiment in accordance with the present invention.
FIG. 9 is a timing chart showing an operation of the circuit for adding the frame synchronizing signal shown in FIG. 8.
FIG. 10 is a circuit diagram of the detecting circuit of the embodiment in accordance with the present invention.
FIG. 11(a) and FIG. 11(b) are timing charts showing an operation of the CDS (code word digital sum) in the embodiment in accordance with the present invention.
FIG. 12(a), FIG. 12(b) and FIG. 12(c) are timing charts showing a relation between the CDS and the DSV of the embodiment in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS An encoding method in accordance with the present invention operates to convert an 8-bit digital data word into 14-bit code. As is well known, a 14-bit binary code can have sixteen thousand, three hundred and eighty-four different values. Four hundred and seven code patterns of 8-bit digital data are selected from the sixteen thousand, three hundred and eighty-four data values according to an algorithm, which will be described below. A truth table of codes is shown in Table 1, in which the 8-bit data is numbered according to the hexadecimal system.
TABLE 1______________________________________Group A             Group BData  Code        C D S     Code      C D S______________________________________00    01001010101010             0         01001010101010                                 001    01010100101010             0         01010100101010                                 002    01010101010010             0         01010101010010                                 003    10010010101010             0         10010010101010                                 004    10010101001010             0         10010101001010                                 005    10010101010100             0         10010101010100                                 006    10100100101010             0         10100100101010                                 007    10100101010010             0         10100101010010                                 008    10101001001010             0         10101001001010                                 009    10101001010100             0         10101001010100                                 00A    10101010010010             0         10101010010010                                 00B    10101010100100             0         10101010100100                                 00C    01001001010010             0         01001001010010                                 00D    01010010010010             0         01010010010010                                 00E    01010010100100             0         01010010100100                                 00F    01001001000100             0         01001001000100                                 010    10001000100100             0         10001000100100                                 011    10001001001000             0         10001001001000                                 012    10010001000100             0         10010001000100                                 013    10010010001000             0         10010010001000                                 014    01001000101010             0         01001000101010                                 015    01001010100010             0         01001010100010                                 016    01010001001010             0         01010001001010                                 017    01010001010100             0         01010001010100                                 018    01010100100010             0         01010100100010                                 019    01010101000100             0         01010101000100                                 01A    10010001010010             0         10010001010010                                 01B    10010010100010             0         10010010100010                                 01C    10100010010010             0         10100010010010                                 01D    10100010100100             0         10100010100100                                 01E    10100100100010             0         10100100100010                                 01F    10100101000100             0         10100101000100                                 020    01000100010010             0         01000100010010                                 021    01000100100100             0         01000100100100                                 022    01000101001000             0         01000101001000                                 023    01001000100010             0         01001000100010                                 024    01001010001000             0         01001010001000                                 025    01010010000100             0         01010010000100                                 026    10000100010100             0         10000100010100                                 027    10000100101000             0         10000100101000                                 028    10001000010010             0         10001000010010                                 029    10001010010000             0         10001010010000                                 02A    10010000100010             0         10010000100010                                 02B    10010100010000             0         10010100010000                                 02C    10100010000100             0         10100010000100                                 02D    10100100001000             0         10100100001000                                 02E    10010000101010             0         10010000101010                                 02F    10010101000010             0         10010101000010                                 030    10100001001010             0         10100001001010                                 031    10100001010100             0         10100001010100                                 032    10101001000010             0         10101001000010                                 033    10101010000100             0         10101010000100                                 034    01000010001010             0         01000010001010                                 035    01000010010100             0         01000010010100                                 036    01000010101000             0         01000010101000                                 037    01010001000010             0         01010001000010                                 038    01010100001000             0         01010100001000                                 039    10000100001010             0         10000100001010                                 03A    10000101010000             0         10000101010000                                 03B    10100001000010             0         10100001000010                                 03C    10101000010000             0         10101000010000                                 03D    01000100000100             0         01000100000100                                 03E    01001000001000             0         01001000001000                                 03F    01000010000010             0         01000010000010                                 040    01010000010000             0         01010000010000                                 041    10001000000100             0         10001000000100                                 042    10010000001000             0         10010000001000                                 043    10000100000010             0         10000100000010                                 044    10100000010000             0         10100000010000                                 045    01001001010100             2         00010100100100                                 -446    01001010100100             2         00100100010100                                 -447    01010100100100             2         00101000100100                                 -448    10001001010010             2         01001000101000                                 -449    10010010010010             2         01010010010000                                 -44A    00010101010010             -2        10000100100010                                 44B    00101010100010             -2        00100010010000                                 44C    01010010100010             -2        10000010000100                                 44D    00001000101010             -2        01010100001010                                 44E    00010001010100             -2        10000101010010                                 44F    00010101000100             -2        10100101010000                                 450    10100100010010             2         00001010010010                                 -451    10100101001000             2         00100100001010                                 -452    10000100010010             2         00101000010010                                 -453    00010001001000             2         01001001010000                                 -454    00100100010000             2         10010000101000                                 -455    10101000101010             2         10100001001000                                 -456    00101000100010             -2        01000101000010                                 457    01000100010100             -2        10000101000100                                 458    01001000010010             -2        10001010000100                                 459    00100010101010             2         00001010000100                                 -45A    01010001000100             -2        00010001010000                                 45B    10001000101000             -2        01000010001000                                 45C    00101010001010             2         01001000001010                                 -45D    01000100101010             2         10010000010100                                 -45E    10010010010000             -2        01000001010010                                 45F    00001000100010             -2        10000001001010                                 460    00010010000100             -2        10010010000010                                 461    01010010001010             2         00010010000010                                 -462    00010000010000             -2        00010000010100                                 463    01010000101010             -2        01000001000100                                 464    01010100010010             2         10010000001010                                 -465    10001010100010             2         00100100000010                                 -466    10010100100010             2         01001000000010                                 -467    10100010001010             2         10010000000010                                 -468    10100010101000             2         00010100010100                                 -669    10101010001000             2         00101000101000                                 -66A    10100101000010             -2        10001010001010                                 66B    01000100100010             2         00001010010100                                 -66C    10000010001010             2         00010100001010                                 -66D    10001000100010             2         00101000010100                                 -66E    10010010000100             2         01010000101000                                 -66F    00010000100100             2         10100001010000                                 -670    01000100001010             -2        10001010101000                                 671    01010000100010             -2        10010100101000                                 672    10001001010000             -2        10000010001000                                 673    10100001000100             -2        10000101010100                                 674    00010001000010             -2        10010101010000                                 675    00100100000100             -2        10101001010000                                 676    10101010000010             -2        00100001010000                                 677    00100001000100             2         01010000010100                                 -678    10001000001010             -2        01000010010000                                 679    01001000010000             2         00001010000010                                 -67A    00101000001000             -2        10101000001010                                 67B    10001000001000             2         01010000001010                                 -67C    00100101000010             2         00010100000010                                 -67D    01010000001000             -2        00100000101000                                 67E    01000010010010             2         10100000001010                                 -67F    10001000000010             -2        10000000100010                                 680    01001001000010             2         01010000000010                                 -681    01000010100100             2         00101000000010                                 -682    10010000000100             -2        01000001001000                                 683    01000100000010             -2        10001010000010                                 684    00100001010010             2         10100000010100                                 -685    01001000000100             -2        10000010100010                                 686    00100010000010             -2        10000010101010                                 687    10100000100010             -2        10000001000100                                 688    01000100001000             2         10100000101000                                 -689    00010010010000             2         00101000001010                                 -68A    10100000101010             -2        10000101000010                                 68B    00010100001000             -2        10101000010100                                 68C    00001010001000             -2        10010100001010                                 68D    10010000010010             -2        10000101001010                                 68E    10001000010100             -2        10101000101000                                 68F    01000101010000             -2        10010100010100                                 690    00001010100010             -2        10001010010100                                 691    00001000101000             2         01010001010000                                 -692    10001010001000             2         00101001010000                                 -693    10000100100100             2         00010101010000                                 -694    01000101000100             2         00001010101000                                 -695    00100010100010             2         00001010001010                                 -696    10100001010010             2         10000100010000                                 697    10101000100010             2         00010100101000                                 -698    10100010010100             2         10100000000100                                 -499    10010101000100             2         01010000000100                                 -49A    10010001010100             2         00101000000100                                 -49B    10001000101010             2         10100000010010                                 -49C    01010101000010             -2        10000000010000                                 49D    00001010101010             -2        00100000010010                                 49E    01010010101000             2         00010100000100                                 -49F    00001000001000             -2        10010100000100                                 4A0    00001001000100             -2        10000010100100                                 4A1    10100010001000             -2        01001010000010                                 4A2    01000101010010             2         10100000100100                                 -4A3    00101010101000             2         01010000010010                                 -4A4    10010000100100             -2        10000001000010                                 4A5    01010100010000             -2        00100000100100                                 4A6    01001010010000             -2        00010000101000                                 4A7    10101010100010             2         00001001000010                                 -4A8    01000100101000             -2        10001001000010                                 4A9    00101010001000             -2        10000010010010                                 4AA    00100010101000             -2        01000010100010                                 4AB    10001010101010             2         10010001010000                                 -4AC    00100010001000             2         01010000100100                                 -4AD    10001001000100             2         01001000010100                                 -4AE    10101001000100             2         00100101010000                                 -4AF    10100100100100             2         00001010100100                                 -4B0    00100010001010             -2        10101000010010                                 4B1    00010100100010             -2        10100100001010                                 4B2    00001001010010             -2        01010101010000                                 4B3    10100010100010             -2        01000010101010                                 4B4    01010001010010             -2        01000100010000                                 4B5    00101000101010             -2        00100001001000                                 4B6    10010010100100             2         10100010010000                                 -4B7    10010001001010             2         01010001001000                                 -4B8    01010101001000             2         00101010010000                                 -4B9    01010010010100             2         00100100101000                                 -4BA    01001010010010             2         00010101001000                                 -4BB    01001001001010             2         00010100010010                                 -4BC    00101010010100             2         00010010101000                                 -4BD    00100101010100             2         00010010001010                                 -4BE    00100101001010             2         00001001010100                                 -4BF    10101001010010             2         00001001001010                                 -4C0    00010100101010             -2        10101010010000                                 4C1    10101010101000             -2        10101000100100                                 4C2    10101010001010             -2        10100100101000                                 4C3    10100010101010             -2        10100100010100                                 4C4    10100100010000             -2        10010100010010                                 4C5    10010001001000             -2        10010010101000                                 4C6    01010010001000             -2        10010010001010                                 4C7    01001001001000             -2        10001010100100                                 4C8    01001000100100             -2        10001010010010                                 4C9    00101001000100             -2        10000100101010                                 4CA    00100101001000             -2        01010100101000                                 4CB    00100100010010             -2        01010100010100                                 4CC    00100010010100             -2        01001010101000                                 4CD    00010010100100             -2        01001010001010                                 4CE    00010010010010             -2        01000101010100                                 4CF    00010001001010             -2        01000101001010                                 4D0    00101001010010             -2        10001000010000                                 4D1    10101010010100             -2        10000100001000                                 4D2    10010101010010             2         00101001001000                                 -4D3    10010100101010             2         00010010010100                                 -4D4    10100101010100             -2        10101001001000                                 4D5    10100101001010             -2        10010101001000                                 4D6    01010101010100             -2        10010100100100                                 4D7    01010101001010             -2        10010010010100                                 4D8    01010010101010             -2        10001001010100                                 4D9    00101010101010             -2        10001001001010                                 4DA    00100100100100             -2        01001010010100                                 4DB    10101010101010             2         00001000010000                                 -4DC    00100000010000             0         00100000010000                                 0DD    00001000000100             0         00001000000100                                 0DE    00010000001000             0         00010000001000                                 0DF    00101000010000             0         00101000010000                                 0E0    00100001000010             0         00100001000010                                 0E1    00001010010000             0         00001010010000                                 0E2    00101010000100             0         00101010000100                                 0E3    00101001000010             0         00101001000010                                 0E4    00100001010100             0         00100001010100                                 0E5    00010101000010             0         00010101000010                                 0E6    00010000101010             0         00010000101010                                 0E7    00100100001000             0         00100100001000                                 0E8    00100010000100             0         00100010000100                                 0E9    00010100010000             0         00010100010000                                 0EA    00010000100010             0         00010000100010                                 0EB    00001001001000             0         00001001001000                                 0EC    00001000010010             0         00001000010010                                 0ED    00100101000100             0         00100101000100                                 0EE    00100100100010             0         00100100100010                                 0EF    00100010100100             0         00100010100100                                 0F0    00100001001010             0         00100001001010                                 0F1    00010010100010             0         00010010100010                                 0F2    00010001010010             0         00010001010010                                 0F3    00010101010100             0         00010101010100                                 0F4    00010101001010             0         00010101001010                                 0F5    00010010001000             0         00010010001000                                 0F6    00010001000100             0         00010001000100                                 0F7    00001000100100             0         00001000100100                                 0F8    00100010010010             0         00100010010010                                 0F9    00101010100100             0         00101010100100                                 0FA    00101010010010             0         00101010010010                                 0FB    00101001010100             0         00101001010100                                 0FC    00101001001010             0         00101001001010                                 0FD    00100101010010             0         00100101010010                                 0FE    00100100101010             0         00100100101010                                 0FF    00010010101010             0         00010010101010                                 0______________________________________
The 407 selected code patterns satisfy the following conditions: (1) The value of an end bit of the 14-bit code is "0". (2) At least one bit of value "0" is inserted between two bits of value "1" in the code, the number of bits of value "0" inserted therebetween being restricted to eight and below. (3) The number of consecutive bits of the 14-bit code of value "0" at both of the end parts of the code are restricted to 4 and below. Therefore, one bit of value "0" up to eight bits of value "0" are contained between two bits of value "1" in the code sequence.
According to these conditions, the following numbers of 14-bit patterns (as shown in Table 1) are selected according to the respective value of the code word digital sum (hereinafter referred to as CDS):
105 patterns at CDS=0;
68 patterns at CDS=+2;
83 patterns at CDS=-2;
58 patterns at CDS=+4;
45 patterns at CDS=-4;
25 patterns at CDS=+6; and
25 patterns at CDS=-6.
The two-hundred fifty-six 14-bit code patterns shown in Table 1 are thus selected from the above-mentioned four hundred and seven 14-bit patterns.
Digital Sum Variation (hereinafter referred to as DSV) is a sum wherein all positive values "1" corresponding to a hill portion and all negative values "-1" corresponding to a valley portion of the waveform which is encoded by an NRZI system are added as shown in FIG. 2. In the present invention, a polarity of the starting bit of NRZI encoding is made negative. Taking this into consideration, the above-mentioned 14-bit code is assigned to successive 8-bit words of digital data as follows:
A code word digital sum (which is a value of the DSV from the head to end of the NRZI code word) of the 14-bit code is calculated, and the 14-bit codes in which the CDS is equal to zero (CDS=0) are allotted uniquely to each of the digital data words in one-to-one correspondence. (In FIG. 11(a) and FIG. 11(b), for example, the respective CDSs are "+4" and "0".) However, the number of 14-bit codes in which CDS equals "0" is less than the 256 words which are required. Therefore, remnants are allotted to 14-bit codes in which the CDS is not equal to "0". However, when 14-bit codes in which CDS is not equal to zero (CDS≠0) are allotted to the digital data by one-to-one correspondence, the DSV thereof is liable to diverge. In order to prevent divergence, two kinds of 14-bit codes for the cases that CDS≠0 are combined, and either of the two is selected depending on the digital sum variation. Respective "pairs" of the codes are combined in accordance with the following pairs of CDSs:
CDS=+2 and CDS=-4,
CDS=-2 and CDS=+4,
CDS=+2 and CDS=-6, and
CDS=-2 and CDS=+6
which are allotted to the digital data. In the above-mentioned pairs of code, as shown in Table 1, a code having a small CDS in value, for example, a code of CDS=�2 is grouped in a "group A". The codes of CDS=�4 and CDS=�6 are grouped in a "group B". The code of CDS=0 belongs to both group A and group B.
A selecting method of 14-bit codes corresponding to the 8-bit words of digital data is elucidated as follows: The encoding of the digital data is processed according to a value of the DSV at an end of the present code corresponding to the digital data and a polarity of the NRZI encoded digital data. The polarity is positive when the end bit of the above-mentioned NRZI code is assigned to the positive polarity "1" and negative when the end bit is "0". The head bit of the code is made negative, and the DSV is determined from the head bit of the code.
The change of the DSV value and the polarity are shown in FIG. 2. The polarity of the waveform of the NRZI encoded data alternates at the bit of value "1" of the code sequence. The relation between the CDS and the DSV of the code is as shown in FIG. 12. As shown in FIG. 12(a), the code wherein the value of CDS is positive increases DSV when the polarity of the starting point of the code is negative, and decreases DSV when the polarity of the starting pont of the code is positive. As shown in FIG. 12(b), the code wherein the value of CDS is negative decreases DSV when the polarity of the starting point of the code is negative, and increases DSV when the polarity of the starting point of code is positive. As shown in FIG. 12(c), the code wherein the value of CDS is "0" maintains DSV at a constant value independent of the polarity of the starting point of the code.
The manner of selecting the code is shown in Table 2. In Table 2, the polarity of the end bit of the preceding code is designated "POL".
TABLE 2__________________________________________________________________________Polarity of DSVat the end point    Polarity at theof the preceding    end point of the     Changing ofcode     preceding code (POL)               Usable code                         DSV__________________________________________________________________________Positive Positive   Code wherein CDS                         Decrease or               is positive or                         constant               zero    Negative   Code wherein CDS                         Decrease or                                B               is negative or                         constant               zeroZero     Positive   Code of   +2 or  C    Negative   group A   0 or                         +2Negative Positive   Code wherein CDS                         Increase or                                D               is negative or                         constant               zero    Negative   Code wherein CDS                         Increase or                                E               is positive or                         constant               zero__________________________________________________________________________
In accordance with Table 2, the code is selected as DSV goes to a negative value by referring to POL when the value of DSV at the end of the preceding code is positive, and it goes to positive value by referring to POL when the polarity of DSV at the end of the preceding code is negative. Therefore, the change of the value of DSV is restricted in a constant range wherein the value "0" is in the center of the constant range.
As shown in column A of Table 2, when the polarity of DSV at the end point of the code which corresponds to a preceding digital data word of the present digital data word is positive, the polarity (POL) is also positive. The code wherein CDS is positive or zero is selected from the group A and the group B corresponding to the digital data, and is allotted to the digital data. As shown in FIG. 12(a), when POL is positive, DSV can be shifted to negative at the same absolute value of CDS. Furthermore, when both CDSs of the codes of group A and B are "0", the code wherein CDS is equal to "0"0 is allotted, and the value of DSV is held at a constant value as shown in FIG. 12(c).
As shown in column B of Table 2, when the polarity of DSV at the end point of the code which corresponds to a preceding digital data word is positive, and the POL is negative, the code wherein CDS is negative or zero is selected from the group A and the group B corresponding to the digital data. As shown in FIG. 12(b) and FIG. 12(c), when a code in which CDS is negative is selected, if POL is negative, DSV can be shifted to negative at an absolute value of CDS. Moreover, when a code wherein CDS is "0" is selected, the value of DSV is held at constant value.
As shown in column D of Table 2, when the polarity of DSV at the end point of the code which corresponds to a preceding digital data word of the present digital data is negative and the POL is positive, the code wherein CDS is negative or zero is selected from the group A and the group B corresponding to the digital data, and is allotted to the digital data. As shown in FIG. 12(b) and FIG. 12(c), when a code in which CDS is negative is selected, if POL is positive, DSV can be shifted to positive for an absolute value of CDS. Moreover, when a code in which CDS is "0" is selected, the value of DSV is held at a constant value.
As shown in column E of Table 2, when the polarity of DSV at the end point of the code which corresponds to a preceding digital data word of the present digital data word is negative and the POL is negative, the code wherein CDS is positive or zero is selected from the group A and the group B corresponding to the digital data, and is allotted to the digital data. As shown in FIG. 12(a) and FIG. 12(c), when a code in which CDS is positive is selected, if POL is negative, DSV can be shifted to positive for an absolute value of CDS. Moreover, when a code in which CDS is "0" is selected, the value of DSV is held at a constant value.
When the polarity of DSV at the end point of the code which corresponds to the preceding digital data word is negative, a DSV-flag corresponds to the bit with value "1". When the value of DSV for the above-mentioned condition is positive, the DSV-flag corresponds to the bit with value "0". When the polarity for the above-mentioned condition is negative, a polarity flag POL corresponds to the bit of value "1", and when the polarity for the above-mentioned condition is positive, the polarity signal POL corresponds to the bit of value "0". When the exclusive logical sum of the DSV-flag and the polarity signal POL is "1", the encoding code wherein CDS is negative or zero is allotted to the digital data.
As shown in column C of Table 2, when the polarity of DSV at the end point of the code which corresponds to the preceding digital data word of the present digital data word is zero, the code of the group A wherein the absolute value of CDS is small is allotted to the digital data independent of the polarity, and variance of DSV is thus �2 or zero. As a result, the value of DSV of the code sequence is limited to a constant range within a range of a constant value "0". In the present embodiment, for example, the absolute value of DSV is equal to or within +9, and the value of CDS is "0", "+2" or "+4" at the end part of the respective codes.
An example of an encoding circuit for encoding the algorithm in accordance with the present invention is shown in FIG. 1, and the timing chart for the operation of the encoding circuit is shown in FIG. 3.
In FIG. 1, parallel 8-bit digital data words are inputted to a ROM 13 and a ROM 14 through an input terminal 1. A reset signal is applied to a five bit latch 17 through a reset input terminal 3, and a latch clock is inputted to the latch 17 through a latch clock input terminal 5. An output code is issued from a code output terminal 7. A shift/load switching signal is applied to a 14-bit shift register 15 through a shift/load switching signal input terminal 9. A code readout clock is also inputted to the shift register through a code readout clock terminal 11. The output of the code output ROM 13 is applied to the shift register 15. ROM 14 issues CDS signals and polarity signals. A 4-bit full-adder 16 is connected between the ROM 14 and the latch 17. A distinction circuit 18 is formed by three OR gates and detects the value of DSV at the end point of a code in which a preceding digital data word of the present digital data word is encoded. A selection circuit 19 is formed by an exclusive OR gate.
The encoding operation is shown by the timing chart of FIG. 3. A low level reset signal for an initial setting is inputted to the latch 17 at a time as shown in FIG. 3 at (a), and the output level of the latch 17 is set to "0". As a result, the distinction signal from the distinction circuit 18, the selection signal and the polarity signal are set to "0". Parallel 8-bit digital data words are inputted to the ROM 13 and the ROM 14 in order of d0, d1 d2, d3, . . . through the digital data input terminal 1. Furthermore, the distinction signal and the selection signal are inputted to the ROM 13 over signal lines 20 and 21, respectively. The distinction signal, the selection signal and the polarity signal are inputted to the ROM 14 over signal lines 20, 21 and 22, respectively. The distinction signal is an output signal wherein a value of DSV at the end point of a preceding digital data word of the present digital data word is discriminated by the distinction circuit 18. When DSV is "0", the output signal is "0". When DSV is not "0", the output signal is "1". The selection signal, on the other hand, is an output signal of the selection circuit 19 and is equal to an exclusive logical sum of the polarity signal (A positive signal is "0", and a negative signal is "1".) and a DSV-flag 23 (A positive flag is shown by "0", and a negative flag is shown by "1".) which shows the polarity of DSV.
The ROM 13 processes the 8-bit digital data word, the distinction signal and the selection signal, and then outputs a 14-bit code to the shift register 15 according to conditions as shown in Table 2. As shown in Table 2, when the distinction signal (DSV) is "0", the code of the group A wherein an absolute value of CDS is smaller than one of two codes corresponding to the 8-bit digital data word which is encoded is selected. When the distinction signal is "1" and the selection signal is "0", namely, in Table 2 when DSV at the end point of the code wherein the preceding digital data word of the present digital data word is encoded is positive and the polarity is also positive, and furthermore, when DSV is negative and the polarity is negative, the code wherein CDS is positive or zero is selected from the above-mentioned two codes (A or B). When the selection signal is "1", namley in Table 2 when DSV is positive and the polarity is negative, furthermore when the DSV is negative and the polarity is positive, the code wherein CDS is negative or zero is selected from the above-mentioned two codes (A or B).
A shift/load switching signal is inputted to the shift register 15 through the shift/load switching signal input terminal 9, and the code which is outputted from the ROM 13 is parallelly inputted to the shift register 15 when the shift/load switching signal turns to a low level as shown in FIG. 3. Code readout clocks are inputted at a timing as shown in FIG. 3 from the clock input terminal 11, and the above-mentioned code is serially read. The code which is converted to the serial code is issued from the output terminal 7 in order of D0, D1, D2, D3, . . . at a timing as shown in FIG. 3. In FIG. 3, the time period is enlarged on the abscissa which is drawn by dotted lines. The code which is outputted by the ROM 13 is decided in the ROM 14 in view of the input 8-bit digital data, the distinction signal and the selection signal.
A variation of DSV which is caused by CDS of the code which is issued from the ROM 14 is outputted in accordance with the polarity signal. When the variation of DSV is zero, the variation is represented by the binary "0000", and similarly when the variations of DSV are +2, +4, +6, -2, -4 and -6, the respective variations are represented by the binary codes "0010", "0100", "0110", "1110", "1100" and "1010", respectively. These variations are inputted to the 4-bit full-adder 16. When the number of the bit "1" of the above-mentioned decided code is odd, the ROM 14 reverses the polarity of the input polarity signal and output to the latch 17. When the number of the bit "1" is even, the ROM 14 does not reverse the polarity of the input polarity signal and output to the latch 17.
In the 4-bit full adder 16, the value of DSV at the end point of the code sequence wherein the preceding digital data of the present digital data are encoded is issued from the latch 17, and the variations of DSV in accordance with the code of the present digital data are added. The value of DSV at the end point of the code wherein the above-mentioned present digital data is encoded is output to the latch 17. In the latch 17, the inputted new DSV and the polarity signal are held by a rise of a latch clock which is inputted from the latch clock input terminal 5 at a timing as shown in FIG. 3.
The value of DSV at the end point of the code wherein the above-mentioned present digital data is encoded and output from the latch 17 is applied to the distinction circuit 18 over line 23-26 and is used for encoding the next digital data word with respect to the present digital data word.
The polarity signal is inputted to the selection circuit 19 and to the ROM 14 and is used for encoding the next digital data word. The above-mentioned process is repeated and the encoding is continued. Secondly, an NRZI coding is applied to the code sequence wherein the digital data sequence is encoded into an NRZI code sequence, and the NRZI code is recorded on the magnetic recording medium through a rotary transformer and a magnetic head of the recording part. In the reproduction process, the NRZI code sequence is reproduced through the common rotary transformer and a magnetic head of the reproducing part, and the NRZI decoding is processed in the NRZI decoder so that decoding of the 8-14 code may be performed.
An embodiment of a decoding circuit in accordance with the present invention is shown in FIG. 4. The code is inputted to a 14-bit shift register 52 through an input terminal 30. Clock signals are inputted through an input terminal 32. Output signals of the shift register 52 are applied to a 14-bit latch 53. Latch clock signals are inputted through a latch clock input terminal 34. Output signals of the latch 53 are inputted to a ROM 54 for decoding. Decoded digital data are issued parallelly from output terminals 36-43. A timing chart showing the operation of the decoding circuit is shown in FIG. 5. As shown, the reproduced code is inputted to the shift register 52 sequentially in the order, D0, D1, D2 . . . The clock signals are inputted to the shift register 52 through the terminal 32 at a timing as shown in FIG. 5, where the range of the clock along the abscissa is shown enlarged by a dotted line.
The code sequence which is sequentially inputted from the terminal 30 is shifted bit by bit so as to be synchronous with the clock before being issued to the latch 53 from the shift register 52. The reproduced code sequence is separated into 14-bit code words and is issued to the ROM 54 from the latch 53. For this object, the latch clock which is formed by detecting the frame synchronizing signal (as will be described below) is inputted into the latch 53 through the terminal 34 at a timing as shown in FIG. 5, and the data is latched by the rise of the clock pulse. The 14-bit code which is issued from the latch 53 is inputted to the ROM 54 as an address, and 8-bit digital data 44-51 corresponding to the above-mentioned 14-bit code are outputted. The decoded digital data are outputted parallelly from the output terminals 36-43.
As mentioned above, since the number of bits of value "0" inserted between two "1" bits is restricted to be from one to eight, the code may be recorded on the magnetic recording medium. The minimum magnetization reversal interval becomes 1.14 T (where T is a periodic time of the digital data); the maximum magnetization reversal interval becomes 5.14 T; and DR becomes 1.14 so that high density recording may be realized. The encoded digital data of the respective pairs of CDS=+2 and CDS=-4, CDS=-2 and CDS=+4, CDS=+2 and CDS=-6 and CDS=-2 and CDS=+6 are allotted to the digital data, and when DSV is not zero, DSV can be restricted to �9 and below so that the DC component is decreased. Correspondence between the digital data and the code as shown in Table 1 is changeable. For instance, if two codes wherein polarities and absolute values of CDS are different from each other are combined, the combinations of the codes may be freely selected.
The frame synchronizing signal is elucidated as follows: The value of the end bit of the code is "0", and one or more "0" bits are contained between two "1" bits. However, the maximum number of the successive "0" bits are limited to eight in each 14-bit code. Furthermore, the maximum number of the successive "0" bits is limited to four at the head part and the tail part of the code. Furthermore, the 14-bit code in which three or more "0" bits continue at the head part or the tail part is excepted from the code. Moreover, the code in which seven or more "0" bits follow the above-mentioned successive three "0" bits and a "1" bit which is inserted between the two groups of "0" bits is also excepted from the code. Therefore, the pattern of "10000000" appears at the successive part of the code; however, the successive patterns of "10000000" do not appear at the front and the rear of the above-mentioned pattern. Therefore, the pattern of "1000000010000000" does not appear in the code sequence. The bit "10" is thus added to the end of the pattern in order to meet the above-mentioned restriction of succession of "0" bits. Similarly, the bit "10" is added to the head of the pattern in order to meet the restriction of continuation of the "0" bits and to make CDS of the frame synchronizing signal equal to zero.
The following 28-bits of "XXXXXXXXXX100000001000000010" are thus used for a frame synchronizing signal. (The part which is shown by "X" represents an optionally decided ten bits of "10" wherein the restriction of succession of the "0" bits is satisfied and CDS of the 28-bit synchronizing signal becomes "0".)
In FIG. 6(a), the block diagram of a signal processing circuit including an addition part for the frame synchronizing signal and a detection part in accordance with the present invention is shown. The digital data are inputted to a frame forming part 62 through a digital data input terminal 60. The output of the frame forming part 62 is applied to an encoder 63. The output of the encoder 63 is applied to a frame synchronizing a signal addition part 64. The output of the frame synchronizing signal addition part 64 is applied to an NRZI encoder 65. The output of the NRZI encoder 65 is recorded on a recording medium through a recording part 66.
In a reproduction process, as shown in FIG. 6(b), the recorded signals are detected by a reproduction part 67 and are decoded by an NRZI decoder 68. The output of the NRZI decoder is inputted to a frame synchronizing a signal detection part 69 and a shift register 70. The output of the shift register 70 is applied to a decoder 71. An encoded digital data separation signal is outputted from the frame synchronizing signal detection part 69 and is inputted to the shift register 70 via line 74. The output of the decoder 71 is applied to a shift register 72 and is issued from a digital data output terminal 73.
As shown in FIG. 7, a dummy synchronizing signal, an address, an address error detecting code and an error correction code are added to a digital data word, thereby to form a frame in the frame forming part 62. The frame is outputted to the encoder 63 and is encoded in accordance with the above-mentioned 8-14 encode algorithm by the encoder 63, the encoded frame signal being applied to the frame synchronizing signal addition circuit 64. In the frame synchronizing signal addition circuit 64, the dummy synchronizing signal which consists of a 28-bit signal is replaced by the normal synchronizing signal of "XXXXXXXXXX100000001000000010".
The frame synchronizing signal addition circuit 64 is shown in FIG. 8. A switching signal and the code sequence are inputted to a switching circuit 86 in accordance with the timing as shown in FIG. 9 through a switching signal input terminal 80 and the code sequence input terminal 81, respectively. The code sequence wherein the frame synchronizing signal is replaced is outputted from the code output terminal 85. A shift/load signal and a readout clock are inputted to a shift register 87 in accordance with the timing as shown in FIG. 9 through a shift/load signal input terminal 82 and a readout clock input terminal 83, respectively. The shift register 87 is a 28-bit parallel input and serial output shift register. The shift register 87 reads a frame synchronizing signal in accordance with the shift/load signal 82 and outputs the frame synchronizing signal over signal line 84 to the switching circuit 86 in synchronization with readout clock 83. In the switching circuit, the dummy synchronizing signal of the code sequence is thus replaced by the frame synchronizing signal before the code is outputted.
The frame synchronizing signal detection circuit 69 is shown in FIG. 10. The reproduced code sequence is inputted to a 16-bit shift register 91 in the frame synchronizing signal detection circuit 69 from input terminal 90. The above-mentioned reproduced code sequence is shifted bit-by-bit by the clock signal 94 in the shift register 91. The output of the shift register 91 is inputted to a comparator 92 and is compared with a 16-bit pattern "1000000010000000" which does not appear in the code sequence of the 28-bit frame synchronizing signal, and the synchronizing signal of each frame is detected. When the ouput of the shift register 91 agrees with the 16-bit pattern, a detecting signal 93 is output from the comparator 92 and is applied to a counter 95. The counter 95 is loaded with a predetermined value by the detecting signal 93 and is operated as a counter wherein the figure is taken up at fourteen. As a result, a code dividing signal 96 for dividing the reproduced code sequence into respective codes is outputted.
As shown in FIG. 6, the shift register 70 divides the reproduced code sequence which is inputted serially into the codes to be applied to the decoder 71. In the decoder 71, the 8-bit digital data corresponding to the inputted code is outputted to the shift register 72. The inputted 8-bit digital data is then outputted serially from the digital data output terminal 73. As mentioned above, the frame synchronizing signal including the 16-bit pattern "1000000010000000" which does not appear in the code sequence, when 8-14 encoding is adopted, is recorded. Hence, the frame synchronizing signal can be detected precisely by a simple circuit.
Referenced byCiting PatentFiling datePublication dateApplicantTitleUS4835628 *May 11, 1987May 30, 1989Exabyte CorporationApparatus and method for formatting and recording digital data on magnetic tapeUS5077721 *Jun 21, 1989Dec 31, 1991Sony CorporationData recording and/or reproducing method and data recording mediumUS5196848 *Jul 12, 1991Mar 23, 1993Kabushiki Kaisha ToshibaCode modulation system using modulated data code tablesUS5267099 *Mar 18, 1991Nov 30, 1993Matsushita Electric Industrial Co., Ltd.Digital signal recording/reproducing systemUS5349349 *Sep 17, 1992Sep 20, 1994Sony CorporationModulator circuit for a recording for a digital recording mediumUS5365232 *Aug 31, 1993Nov 15, 1994Mitsubishi Denki Kabushiki KaishaData conversion method, pilot signal formation method using the same and rotary magnetic head device for use thereinUS5570248 *Aug 9, 1994Oct 29, 1996Mitsubishi Denki Kabushiki KaishaMethod and system using encoded periodic digital sum variation (DSV) as pilot signal and controlling tracking error using crosstalk from the pilot signalUS5644307 *Mar 10, 1995Jul 1, 1997Sony CorporationModulation method, recording method, reproducing method, recording and reproducing apparatus, recording and reproducing method, and reproducing apparatusUS5699061 *Jul 1, 1996Dec 16, 1997Sony CorporationMethod and apparatus for generating NRZI code with limited runs of onesUS5852520 *Jul 31, 1996Dec 22, 1998Mitsubishi Denki Kabushiki KaishaData conversion method, pilot signal formation method using the same rotary magnetic head device for use thereinUS6246551Oct 20, 1998Jun 12, 2001Ecrix CorporationOverscan helical scan head for non-tracking tape subsystems reading at up to 1X speed and methods for simulation of sameUS6307701Oct 20, 1998Oct 23, 2001Ecrix CorporationVariable speed recording method and apparatus for a magnetic tape driveUS6308298Nov 16, 1998Oct 23, 2001Ecrix CorporationMethod of reacquiring clock synchronization on a non-tracking helical scan tape deviceUS6364234Mar 10, 2000Apr 2, 2002Michael Donald LangianoTape loop/slack prevention method and apparatus for tape driveUS6367048Nov 16, 1998Apr 2, 2002Mcauliffe RichardMethod and apparatus for logically rejecting previously recorded track residue from magnetic mediaUS6381706Oct 20, 1998Apr 30, 2002Ecrix CorporationFine granularity rewrite method and apparatus for data storage deviceUS6421805Nov 16, 1998Jul 16, 2002Exabyte CorporationRogue packet detection and correction method for data storage deviceUS6603618Nov 16, 1998Aug 5, 2003Exabyte CorporationMethod and system for monitoring and adjusting tape position using control data packetsUS6624960Mar 10, 2000Sep 23, 2003Exabyte CorporationCurrent sensing drum/cleaning wheel positioning method and apparatus for magnetic storage systemUS6654425Oct 9, 1997Nov 25, 2003Sanyo Electric Co., Ltd.Method and circuit for digital modulation and method and circuit for digital demodulationUS6768432 *Jan 29, 2002Jul 27, 2004Koninklijke Philips Electronics N.V.Method of converting a series of m-bit information words into a modulated signalUS7039141 *Aug 16, 2001May 2, 2006Hitachi, Ltd.Data synchronization detection device, information recording device, information reproduction device, information recording format, signal processing device, information recording and reproducing device, and information recording mediumUS7277842Apr 3, 2001Oct 2, 2007Tandberg Data CorporationOverscan helical scan head for non-tracking tape subsystems reading at up to 1X speed and methods for simulation of sameUSRE40312Feb 25, 2004May 13, 2008Pioneer Electronic CorporationDigital data transmitting methodCN1722283BFeb 1, 1995Apr 28, 2010皇家菲利浦电子有限公Method of converting a series of m-bit information words to a modulated signal, coding device, recording medium and decoding deviceCN101577133BFeb 1, 1995Sep 7, 2011皇家菲利浦电子有限公司Decoding device and reading-out deviceEP0650263A1 *Sep 20, 1994Apr 26, 1995Sony CorporationCoding and decoding methods and magnetic recording apparatusEP0674393A1 *Mar 14, 1995Sep 27, 1995Sony CorporationModulation method, recording method, reproducing method, recording and reproducing apparatus, recording and reproducing method, and reproducing apparatusWO1988009031A1 *May 9, 1988Nov 17, 1988Exabyte CorpForming digital data for magnetic tape* Cited by examinerClassifications U.S. Classification360/40, G9B/20.041, G9B/20.015, G9B/27.033International ClassificationG11B20/12, G11B20/14, G11B27/30Cooperative ClassificationG11B20/1426, G11B20/12, G11B27/3027European ClassificationG11B20/14A2B, G11B20/12, G11B27/30CLegal EventsDateCodeEventDescriptionSep 7, 1999FPAYFee paymentYear of fee payment: 12Aug 28, 1995FPAYFee paymentYear of fee payment: 8Aug 8, 1991FPAYFee paymentYear of fee payment: 4Feb 25, 1986ASAssignmentOwner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., 1006, OAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:TAKEUCHI, KOUSOU;REEL/FRAME:004522/0228Effective date: 19860219RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google