Source: http://www.google.com/patents/US4965218?dq=6,460,050
Timestamp: 2014-08-20 05:32:03
Document Index: 639302621

Matched Legal Cases: ['application No. 002', 'application No. 137', 'application No. 002', 'application No. 002', 'application No. 004', 'application No. 113', 'application No. 789']

Patent US4965218 - Self-aligned gate realignment employing planarizing overetch - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA method of providing a self-aligned gate (SAG) transistor or FET is disclosed. The method permits large aligment tolerances during manufacture of the SAG FET. A reduction in gate resistance is accomplished by including a second layer of gate metallization, which is highly conductive, after the n+ implant...http://www.google.com/patents/US4965218?utm_source=gb-gplus-sharePatent US4965218 - Self-aligned gate realignment employing planarizing overetchAdvanced Patent SearchPublication numberUS4965218 APublication typeGrantApplication numberUS 07/235,393Publication dateOct 23, 1990Filing dateAug 23, 1988Priority dateOct 21, 1985Fee statusLapsedPublication number07235393, 235393, US 4965218 A, US 4965218A, US-A-4965218, US4965218 A, US4965218AInventorsArthur E. Geissberger, Robert A. Sadler, Paulette Luper, Matthew L. BalzanOriginal AssigneeItt CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (8), Non-Patent Citations (2), Referenced by (32), Classifications (40), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSelf-aligned gate realignment employing planarizing overetchUS 4965218 AAbstract A method of providing a self-aligned gate (SAG) transistor or FET is disclosed. The method permits large aligment tolerances during manufacture of the SAG FET. A reduction in gate resistance is accomplished by including a second layer of gate metallization, which is highly conductive, after the n+ implant and activation anneal without any critical realignment to the first layer of gate metal. The provision of the second layer after the anneal precludes degradation of the conductivity of the second gate metal by interdiffusion with the first (refractory) gate metal during the anneal. The large tolerance for misalignment of the gate mask level is obtained by a planarization of the anneal cap until the top surface of the first layer of gate metal is exposed, all without the need for a separate mask and etch step to open contact "windows" through the planarization anneal cap layers. The remaining adjacent encapsulant then acts as an insulator over the FET channel region and allows for gross misalignment of the second gate metallization without FET performance degradation. Using this technique, substantially increased performance can be obtained from a self-aligned FET while maintaining the basic simplicity of the RG process.
We claim: 1. A process for the manufacture of self-aligned gate GaAs FET's having reduced gate length and improved gate resistance comprising:(a) providing a substrate; (b) forming a layer of GaAs on said substrate; (c) forming an active channel region in said layer of GaAs; (d) forming a first patterned gate layer comprising a gate of a refractory metal; (e) ion implanting source and drain regions on respective sides of said gate; (f) providing a first dielectric layer over said first patterned gate layer and said source and drain regions; (g) providing a sacrificial layer of etchable material over said first dielectric layer; (h) exposing a top portion of said first patterned gate layer by non-selectively etching said sacrificial layer and said dielectric layer, said top portion having a lateral expanse encompassing said gate; (i) providing a non-critically aligned photoresist mask over the dielectric layer and patterning said photoresist mask to expose said top portion; (j) forming a second gate layer of a material having low sheet resistivity overlying said photoresist mask and directly contacting said top portion through said photoresist mask; and (k) removing said photoresist mask and lifting off said second gate layer overlying said photoresist mask to leave a non-critically aligned second gate layer directly contacting said top portion. 2. A process as claimed in claim 1, wherein said step of planarizing said first dielectric layer comprises covering said first dielectric layer with a sacrificial planarization layer; andetching said sacrificial planarization layer and first dielectric layer in an etch environment exhibiting a unity etch ratio with respect to said sacrificial planarization layer and said first dielectric layer to improve the planarity of said first dielectric layer. 3. A process as claimed in claim 1, wherein said source and drain regions are activated prior to said step of covering said first gate layer with a first dielectric layer.
4. A process as claimed in claim 1, wherein said second gate layer forms a first level interconnect.
5. A process for the manufacture of self-aligned gate GaAs FET's having reduced gate length and improved gate resistance comprising:(a) providing a substrate; (b) forming a layer of GaAs on said substrate; (c) forming an active channel region in said layer of GaAs; (d) forming a first patterned gate layer comprising a gate of a refractory metal; (e) ion implanting source and drain regions on respective sides of said gate; (f) providing a first dielectric layer over said first patterned gate layer and said source and drain regions; (g) exposing a top portion of said first patterned gate layer by reactive ion etching of said dielectric layer; (h) providing a non-critically aligned photoresist mask over the dielectric layer and patterning said photoresist mask to expose said top portion; (i) forming a second gate layer of a material having low sheet resistivity overlying said photoresist mask and directly contacting said top portion through said photoresist mask; and (j) removing said photoresist mask and lifting off said second gate layer overlying said photoresist mask to leave a non-critically aligned second gate layer directly contacting said top portion. Description
RELATED APPLICATIONS This application is a continuation-in-part of commonly owned U.S. patent application No. 002,084, filed Jan. 12, 1987, now abandoned, and a division of commonly owned U.S. patent application No. 137,309, filed Dec. 23, 1987, now issued as U.S. Pat. No. 4,847,212, which was itself a continuation-in-part of each of U.S. patent application No. 002,083, filed Jan. 12, 1987, now issued as U.S. Pat. No. 4,782,032, U.S. patent application No. 002,084 (identified above), U.S. patent application No. 004,992, filed Jan. 20, 1987, currently pending, and U.S. patent application No. 113,367, filed Oct. 21, 1987, currently pending, the latter application being a continuation of U.S. patent application No. 789,523, filed Oct. 21, 1985, now abandoned.
The processes currently being used fall into two categories: (1) Thermally-Stable Refractory Gate (RG), and (2) Substitutional Gate (SG). From a processing standpoint, the RG process is simpler and easier to manufacture than the SG process, but it places stringent requirements on the thermal stability of the Schottky gate metallization. The SG approach places no unusual thermal stability requirements on the gate metal but does require the difficult formation of a tri-layer gate substitution mask with a carefully controlled T-shaped profile.
While the RG approach may be superior overall to the SG approach, previous embodiments of the RG approach have suffered the need to compromise some aspects of the process due to inadequate technology. One major problem in the past has been that the thermal stability of the gate metal is insufficient to permit annealing of the self-aligned n+ implant at temperatures higher than 750� C.-800� C., whereas optimum activation of the channel implants of the device occurs at temperatures above 800� C. and are generally in the range between about 810� C.-850� C. for furnace anneals and generally above 900� C. for RTA (rapid thermal annealing). This necessitates one of two possible compromises: either annealing both the initial channel implant and the subsequent device region at an annealing temperature compatible with the n+ implanted regions, or doing two separate anneals, a channel anneal before gate formation at an optimum time-temperature product and then a source/drain anneal at a lower than optimum temperature. In either case, the implant activation and electron mobility in the source and drain implant regions suffer, so that the FET characteristics are less than optimum.
Another disadvantage of some embodiments of the RG approach is the use of a photoresist mask to plasma etch the refractory gate metal. Thus, since this approach results in an FET without an overhanging "T-gate" structure, it allows no means to space the position of the gate from the edges of the self-aligned n+ regions, and therefore no means to optimize the gate structure simultaneously with respect to both capacitance (Cgd) and series resistance.
It is another object of the present invention to provide a FET which allows gate line widths of 1 micrometer or less to be easily defined optically.
These and other objects of the invention which will become apparent hereinafter are accomplished by the present invention which provides a process for making a field-effect transistor comprising one or more of the structural and process innovations of the present invention including: (i) the step of heating a gallium arsenide substrate having first channel forming and second source-drain forming ions implanted therein and a high temperature resistant metallization layer used to self-align the source and drain implants, where the metallization layer includes 1 to 20 atomic percent titanium and includes tungsten, and the metallization layer is deposited on the substrate and heated to a high temperature sufficient to anneal the ion implanted regions of the substrate and activate the ions implanted therein; (ii) the step of forming a gate metallization layer on said substrate which layer is fabricated from titanium-tungsten nitride (TiWNx) and is used both as a diffusion barrier between a gold conductor and the GaAs channel of the transistor and as a Schottky junction forming refractory gate; (iii) masking of a portion of the channel region on the drain side of the gate electrode before performing an n+ self-aligned source and drain implant, so that the n+ implanted source-drain region is asymmetrical on the two sides of the gate electrode to obtain minimum desired parasitic source resistance, without the deleterious effects on gate-drain breakdown voltage, gate-drain capacitance, source-drain breakdown voltage, and output resistance that accompany a high doping level adjacent to the drain side of the gate; iv) overcoming the disadvantage of the high gate resistance for a Thermally-Stable Refractory Gate SAG FET while maintaining large alignment tolerances and reducing gate resistance by including a second gate metallization layer, which has a higher conductivity than the refractory gate layer and which may be formed after the n+ self-aligned source/drain implant and preferably after the activation anneal thus precluding degradation of the conductivity of the second gate metal by interdiffusion with the first (refractory) gate metal during activation. A large tolerance for misalignment of the gate mask level may be obtained by a planarization etch of the anneal cap which is continued long enough to expose the top surface of the first gate metallization. This may be done without any initial aperture delineation for the gate since the vertical height of the gate metal causes the gate to be the highest physical structure on the chip surface and thus to become exposed first during the planar etch. The remaining encapsulant adjacent the sides of the first gate metallization layer then acts as an insulator over the FET channel region and other portions of the substrate and allows for gross misalignment (�0.5 micron) of the second gate metallization layer without FET performance degradation. Using this innovation for reducing resistance in a refractory gate substantially increases performance of self-aligned GaAs devices while maintaining the basic simplicity of the RG process.
Processing of a semiconductor wafer 11 is illustrated, commencing in FIG. 2, where a gallium arsenide (GaAs) substrate 12 is initially cleaned in solvents and then etched to remove that portion of the substrate 12 which may have been damaged by the use of a mechanical slurry polishing process. It has been found that by removing at least approximately 5 micrometers from each of the substrate surfaces, the damaged portion will be removed and improved electrical properties will result. A problem in removing the material from the substrate is that a pitted or rough-textured surface may result with certain etchants. A preferred etchant which avoids this problem is a mixture of sulfuric acid, hydrogen peroxide and water (H2 SO4 :H2 O2 :H2 O) in a ratio of 5:1:1, used at a temperature in the range of approximately 30� C.-40� C. This etchant does not damage the wafer 11 and leaves a smooth finish on the surfaces of the wafer 11 which aids in further processing of the wafer, especially when performing photolithography.
The ion implantation step is performed in any known manner. In one method, the wafer 11 is supported in a vacuum chamber and a beam of ions is uniformly swept over it and implanted into the GaAs substrate 12 through the window 17. The implanted region is indicated at 19. The material of the dielectric layer 14 preferably has an amorphous structure, thus minimizing planar channeling effects of the arriving ions through the layer 14. If somewhat steeper implant profiles are desired, the dielectric layer 14 may be eliminated or reduced in thickness to about 300 Å since some dielectric covering is very useful for protecting the GaAs during photoresist stripping, and the implant made directly (or less indirectly) into the GaAs substrate 12. After the implant is performed, the photoresist layer 18 is removed, for instance, in an oxygen plasma.
Additional selective implant steps may be performed by forming another photoresist layer (not shown) on top of the dielectric layer 14, patterning the photoresist layer to form new window areas and implanting the desired dopant material through the new window areas into and through the dielectric layer 14 and into the GaAs substrate 12. The additional photoresist is thereafter removed. Thus, many different types of active and passive devices can be fabricated on the same wafer, for example, enhancement-mode and depletion-mode FET's, diodes and resistors. This is made possible by the formation, in the GaAs substrate, of multiple ion implanted regions having different impurities and/or impurity concentrations.
After completing the desired selective implant steps, the dielectric layer 14 is removed in a suitable manner for the dielectric employed. For SiO2, a hydrogen fluoride (HF) etch is satisfactory. A metallization layer 20 is formed on a surface 26 which includes the implanted surface of the wafer 11. The metallization layer 20 may be formed of titanium-tungsten (TiW). One method of formation of the layer 20 is accomplished by the sputter deposition of titanium-tungsten to a depth of 2000 Å. Known metallization layers consist of titanium and tungsten in an atomic ratio of 30:70. This is equivalent to 10 weight percent titanium and 90 weight percent tungsten. Sputter targets of this composition were originally employed in the silicon semiconductor industry to sputter deposit a titanium-tungsten diffusion barrier layer between, for example, aluminum and polysilicon. When these sputter targets were used in the gallium arsenide industry to deposit titanium-tungsten to form a temperature-stable Schottky contact, it was found that annealing at temperatures higher than 800� C. caused degradation of the electrical properties of the TiW:GaAs Schottky barrier. However, activation efficiency of silicon as an n-type dopant generally requires annealing at temperatures above 800� C. It therefore became necessary to perform two annealing steps--one, prior to gate formation, at a temperature of 830� C.-850� C. to achieve optimum activation of the channel implants and a second after any required high-dose ion implants for source and drain optimization, at a lower temperature of 750� C.-800� C. to prevent functional degradation of the then present Schottky gate. The second low-temperature annealing resulted in less than optimum levels of implant activation and electron mobility in the source and drain regions for the following reasons. Typically, silicon is used as an ion-implanted dopant for GaAs. Silicon is amphoteric and thus can act as an n-type and a p-type dopant depending upon whether it bonds into a Gallium site (n-type) or an Arsenic site. Annealing time and temperature will determine whether the silicon bonds predominantly into Gallium sites to act as an electron donor (n-type) or into Arsenic sites to act as an electron acceptor (p-type). At certain annealing times and temperature products the portion of silicon atoms which become electron donors is maximized. This is the desired condition since n-type GaAs material has higher electron mobility. There is an optimum anneal schedule well known in the semiconductor industry where temperatures between about 800� C. and 950� C. and for times between about 10 and 30 minutes will increase n/p type activation. Rapid thermal annealing may also be employed according to schedules known for RTA anneals, including temperatures as high as 1050� and times as short as 10 seconds. A second anneal, following a first optimum anneal, degrades the n/p activation ratio initially obtained. Thus, the second anneal is typically conducted at lower temperatures, i.e. about 800� C. for about 10 minutes, which is less than optimum (i.e. 810� C. for 20 minutes). Thus, the source and drain n+ activation is not optimized. For the channel, 90% efficiency (n/p) is desired. Thus, annealing at the required lower temperature results in less than optimum implant activation efficiency and electron mobility in the n+ regions.
Unexpectedly, it has been found that a mixture of 1 atomic percent titanium to 20 atomic percent titanium with a respective 99 to 80 atomic percent tungsten ratio in the deposited layer 20 gives thermal stability to the layer so that it can withstand furnace annealing at temperatures between 800� C.-950� C. without degradation of the electrical properties of the titanium-tungsten:gallium arsenide Schottky barrier. Preferably, annealing is performed at temperatures in the range of approximately 810� C.-850� C. to achieve optimum ion implant activation. Due to the thermalstability of the metallization layer 20 at high temperatures, it became possible to perform only one annealing step at the higher temperatures, resulting in optimum activation of both implants, increased electron mobility and therefore reduced parasitic resistances and higher transconductance. Other improved FET characteristics which result from the single higher-temperature annealing step include operation of the device at a lower drain-source bias voltage which results in low power dissipation relative to operation under higher bias conditions, or faster switching time with the same power dissipation and bias level. With increases in the percentage of titanium in the mixture, the thermal stability begins to degrade due to TiAs compound formation at the metal to semiconductor interface. Thus, with the reduced titanium level, the stability of the TiW during high temperature processing is achieved.
It has been found that the use of a high-resolution positive photoresist or an image reversal resist (IR resist) to define a metal etch mask by evaporation and liftoff enables gate linewidths of 1 micrometer or less to be defined much more easily than with the use of a photoresist etch mask with currently available photoresists. IR resist withstands an RIE much better than standard positive resist, but the metal etch mask is better still. In addition, the metal etch mask 22 serves as an excellent implant mask as discussed below. In the event that photoresists are identified which have satisfactory resolution and masking properties, then such photoresist could conveniently be used in place of the metal etch mask described above.
The n+ implant is masked from the region of the T-shaped structures 24 by the etch mask 22, with the separation of each gate edge from the adjacent n+ region determined by the plasma undercut of the gate metal. The plasma undercut can be controlled accurately enough during etching to allow optimization of the gate structure with respect to both gate capacitance and series resistance. The photoresist mask 28 is removed in an O2 plasma, and the etch mask 22 is dissolved in hydrochloric acid at 55� C., which also removes any photoresist residues which may remain.
The wafer is then covered with approximately 5000 Å or less of a dielectric encapsulant 30 and annealed at approximately 810� C. for about 20 minutes. The encapsulant 30 is provided to protect the GaAs wafer 11 from disassociation since the arsenic may otherwise vaporize at the high annealing temperature. Because the atomic ratio of the TiW elements enables the layer 20 to have unusually high thermal stability, only one annealing step for both channel and source-drain n+ implants is needed. As discussed above, this allows optimum n/p activation of each implant, thus higher electron mobility, reduced parasitic resistances as well as superior device characteristics may be obtained. It also eliminates one annealing furnace and the need for two separate annealing process steps thereby resulting in decreased fabrication time and cost. The dielectric encapsulant 30 may be of silicon dioxide (SiO2), silicon nitride (SiN), polyimide or silicon oxynitride (SiON). Deposition, as by CVD or plasma deposition (PECVD), of these dielectrics is preferred except for polyimide which may be spun on as with photoresists.
Preferred materials for the contacts 32 are a layered structure of 150 Å nickel, then 200 Å germanium and then 2000 Å gold, although a first layer of a gold-germanium compound overlayed with nickel would also be suitable. While the method employing removal of the encapsulant is simpler from a processing standpoint, the second method has the advantage of retaining most of the encapsulant and thus providing more complete gate passivation, leading to greater device reliability. With either approach, the material of the contacts 32 may be deposited by sputtering rather than evaporation, with the advantage of better inherent surface cleaning and more reproducible contact properties.
(1) a brief argon etch under conditions of low pressure and high power
20 mTorr, 0.4 W/cm2 (2) a CF4 etch at medium pressure and power of sufficient length to remove the refractory metal from the unmasked regions of the wafer
40 mTorr, 0.2 W/cm2 (3) a CF4 :O2 He (40:10:50 partial pressures) etch at high pressure and low power to produce the desired undercut
200 mTorr, 0.08 W/cm2 The wafer is preferably not exposed to atmosphere but is kept in vacuo between successive etch steps.
The third step is a self-limiting etch which undercuts the etch mask by a reproducible amount. The etch parameters may be adjusted to tailor the undercut dimension for a particular application. For the etch conditions set forth above, and for a refractory layer 20 having a thickness of about 2000 Å and an etch mask 22 having a width of about 1.4 micrometers, the self-limiting undercut of the etch mask 22 is about 0.4 micrometers on each side at the gate. Thus, the gate length of 0.5 micrometers results. If the etch mask dimension is changed, so is the resulting gate dimension, since the 0.4 micrometers undercut is still provided. In another example, where the second etch step was permitted to overetch somewhat longer than in the above example, it was found that the undercut of the etch mask was about 0.3 micrometers. Thus, it can be seen that varying one aspect of the etch process can alter the extent of self-limited undercut. Helium was selected as an inert gas due to its longer mean free path than Argon's. It is believed that other inert gases could be employed.
After the T-gate formation, a selective self-aligned n+ ion implantation may be carried out to create high conductivity regions in the semiconductor wafer for low resistance source and drain contacts. The T-gate comprises the self-aligned implant mask (etch mask 22) while a patterned photoresist mask 28 provides for device isolation. Referring to FIG. 10, this further step in the process is depicted. After selectively etching the gate metal and removing the excess metal by plasma or reactive-ion etching, the wafer is then coated with a photoresist layer 28 and patterned according to conventional techniques to define implant windows 27a, 27b including openings in the photoresist on both halves of the device. Suitable dopant ions are then implanted into the semiconductor in the region of the openings thus forming an asymmetrical device structure. In the situation illustrated, an n-type channel 19 is implanted with a second n-type implant to form n+ regions 41, 43 such that the gate is adjacent to an n+ region 41 on its source side, but separated from the n+ region 43 by some distance "d" on the drain side. The preferred distance for this separation "d" is about 1 micrometer but it could be as little as 0.5 micrometers and as much as the gate-to-drain electrode distance. Essentially, the preferred dopant ion is silicon, although any n-type dopant ion may be used. As one can see from FIG. 10, the areas 41 and 43 which respectively constitute the source and drain regions of the FET device are heavily doped by means of the dopant ions and are n+ regions, indicating high conductivity relative to the channel.
In order to obtain this result, the encapsulant 51 is conformally provided such that it has a vertical thickness on horizontal surfaces which is about the same as its horizontal thickness on vertical surfaces. SiON, Si3 N4 and SiO2 can all be conformally applied and their thickness on both horizontal and vertical surfaces will be nearly identical. Using SiON as an example, a conformal layer 51 of about 100 nm thickness is provided as shown in FIG. 11a, by plasma enhanced chemical vapor deposition. This results in a vertical thickness of SiON of 100 nm over horizontal surfaces, and a 100 nm wide spacer of SiON adjacent the gate having a vertical height (thickness) of about the gate height (200 nm) plus the 100 nm thickness of the SiON layer. Thus, about 300 nm of SiON, measured vertically, is provided adjacent the gate. This spacer has sufficient thickness to substantially prevent vertical ion penetration therethrough during an ion implant step where the implant energy is selected to be about 100 Kev and where the implanted ions are silicon.
The transition region is laterally spaced from the gate. The use of the sidewall as an implant mask provides a distinct benefit in avoiding short channel effects. Short channel effects may be encountered if the transition regions contact the gate metal. If the undercut is 0.4 um, it is imperative to use the transition region if an EFET is to work since a source to gate dimension of about 0.3 micrometer or more is generally not functional. A desirable distance from the transition region to the gate is less than 0.1 micrometers but, in order to avoid short channel effects, the transition region should be laterally spaced from the gate.
FIG. 11b illustrates the tapered implant profile including intermediate regions 66, 68 having an n' doping level (about 3-8�1017 ions/cm3), highly doped regions 41, 43 having an n+ doping level (greater than about 1.0�1018 ions/cm3) and the lightly doped channel 19 (about 1-4�1017 ions/cm3), assuming implant thickness or depths of less than about 0.2 micrometers for the channel. The n' implant is masked by photoresist 64 for ensuring that conductive n-doped regions of the substrate are not formed to provide unintentional interconnections, via the substrate, of adjacent devices. By masking the substrate with a suitable thickness of photoresist, device isolation is maintained. The gate (and overlying SiON) masks the channel 19 between the spacers to prevent extra implantation into the channel.
In an overall process flow as described herein, the benefits of this process option can be clearly seen when the channel is formed by implanting silicon at 90 Kev through 85 nm of PECVD SiON followed by removal of the SiON and direct deposit of 200 nm of T:WN onto the GaAs channel by reactive sputtering in an atmosphere of 25% N2 in Ar. An Ni etch mask 150 nm thick is formed by evaporation and liftoff to define the gate. The three step self-limiting undercut T-gate forming sequencer described with respect to FIG. 9 follows and silicon is implanted at 120 Kev into bare GaAs to form n+ regions. Then the etch mask is chemically removed. 100 nm of PECVD SiON is conformally deposited to provide an anneal cap and self-aligned implant spacers for the following 100 Kev silicon implant. An 810� C. anneal completes the sequence. It is noted that the purpose of the anneal is to activate all of the implanted silicon.
Referring to FIG. 12, there is shown the next step in the process. After annealing, the annealed cap is planarized. This is accomplished by first spinning a thick layer, perhaps 2000 to 5000 angstroms, of a planarizing material 52 such as polyimide or photoresist onto the encapsulated wafer thus forming the layer 52. It is preferred that the photoresist's thickness be at least as thick as the height of the first level gate metal. The coated wafer is then plasma etched in an admixture of CF4 and O2 in which the ratio of the two gases is adjusted so that the dielectric encapsulant 51 and the planarizing layer. 52 have approximately equal etch rates. The wafer is etched until all of the photoresist 52 has been removed in addition to the bulges in the encapsulant 51 caused by the underlying first level gate metal. The exact ratio of the CF4 /O2 mix needed to establish a unity etch rate ratio is dependent upon the refractive index of the encapsulant. In one preferred manner of practicing the invention, polyimide is used as the planarization dielectric. Polyimide has been found to provide a lower Cgs and lower gm than results from the use of SiON. In design of circuits using devices made with polyimide, the lower Cgs more than compensates for the reduced gm and the circuit performance is improved overall. These differences are believed to be due to, at least in part, surface charge and interlayer stresses. In a preferred manner of practicing the invention, the planarizing etch continues until the top surface of the first level gate metal is exposed along substantially its entire lateral expanse. This may be facilitated by continuing the CF4 /O2 etch long enough to overetch the dielectric resulting in a structure where the top surface of the gate protrudes above the level of the surrounding dielectric. This obviates the need for critically aligning a mask with the dielectrically covered gate portion for contact window formation. This process sequence is shown in FIGS. 14a-14c where the cap 51 and planarizing layer 52 shown in FIG. 14a are etched until the top 20' of gate 20 is cleared along its entire lateral expanse. The etch is halted before the dielectric 51 is consumed or etched through at locations other than the gate metal tracks such that a continuous dielectric isolation of the channel is provided, except for its contact to the gate. FIG. 14c shows a liftoff mask 55 used for non-critically aligning a supplemental gate conducting layer with the refractory gate. The misalignment tolerance of this process is excellent.
The step of applying the supplemental gate layer to the top portion of the underlying gate layer is substantially similar to that described previously with respect to FIGS. 3b and 4. Once the structure of FIG. 14c is obtained, the supplemental gate conducting layer is evaporated onto the structure and upon chemically etching away the mask 55, excess metal from the supplemental gate conducting layer is lifted off. The conducting layer 56 which remains on the entire lateral expanse of the gate is similar in function to layer 57 illustrated in FIGS. 13a-13c and is described below in common with layer 57.
Referring to FIG. 13A, there is shown the alternative step in the process where windows are patterned in the encapsulant 51 over the refractory gate metal area 20 by realigning the gate mask and patterning photoresist material thereupon followed by chemically etching the encapsulant. In this approach, it is important that the etch be terminated before any portion of the GaAs is exposed. According to the preferred manner of practicing this aspect of the invention, a non-critically aligned photoresist mask is then provided over the patterned encapsulant 51 and patterned to expose substantially the entire top surface of the gate which was previously etched to clear the top of the gate of encapsulant 51.
It is noted that the two layer metallization, consisting of layers 20 and 57, can be considered to be the gate of the FET device. More accurately, however, the gate consists of layer 20 while layer 57 provides supplemental conductivity and might more appropriately be considered a part of the gate contact structure. Layer. 57 has a very low sheet resistance which is typically 0.06 ohms/sq. and could also be used as the first level interconnect metal if the FET is incorporated in an integrated circuit. Hence, as one can see from FIG. 13C, one has access to the source and drain of the device via the ohmic contacts 32 and access to the gate electrodes via the second metallization layer 57. This, of course, is substantially different from the implementation previously described with respect to FIG. 7 where the first level interconnect is connected to gate pads at the end of each gate finger. The provision of the second layer 57 of metal having low sheet resistance over substantially the full gate (rather than only at gate contact locations) provides greatly improved device characteristics.
As is evident from the above, in circuits where multilevel metal interconnect is to be employed, it is possible to obtain the advantage of reduced gate resistance in an already existing metallization step without resulting in increased gate length and without requiring line resolution to the dimensions of the gate length. The two layer gate/gate contact structure and the planarizing sequence provide advantages over prior structures and processes.
To form a second-level interconnect metallization, reference is made to FIG. 7 where the wafer may be coated with a suitable dielectric material to form a layer 36 over the planarized surface. This permits the second level metal to be a global interconnect. An organic material such as polyimide may be used for the dielectric material. Other dielectric materials include inorganic materials such as plasma-deposited SiN or SiON. Openings 38 are opened in the dielectric layer 36 by plasma etching through a patterned photoresist layer 40. The openings 38 permit contact between the additional level of interconnect metallization 35 shown in FIG. 1 with the underlying first-level interconnect metal 34, the gate 20, or the dual layer metal 12, 25 shown in FIG. 13c.
Another aspect of the present invention involves the process of efficiently providing asymmetrical spacing of the source and drain implants from the gate. Referring again to FIG. 8, there is shown in general a semiconductor wafer or substrate 12 containing an active channel region 19. The fabrication process essentially begins with the formation of the active channel area for the FET. This may be accomplished by epitaxial layer growth on a suitable substrate, followed by electrical isolation of the intended device area, or alternately, by selective ion implantation of suitable dopants in desired regions of the semiconductor. The entire surface is then coated with a thin layer 20 of suitable metallization having sufficient thermal stability to withstand annealing at temperatures in the range 750� to 950� C. without degradation of its Schottky barrier properties. Examples of Schottky gate metallizations suitable for this purpose are titanium-tungsten, titanium-tungsten nitride, tungsten nitride and tungsten silicide, although any metallization which will survive the anneal step may be used.
Referring to FIG. 10, the wafer is then coated with a photoresist 28 which is patterned to have openings 27a and 27b on respective source and drain sides of the device. Suitable dopant ions are then implanted into the semiconductor in the region of the openings 27a and 27b thus forming an asymmetrical device structure with the gate adjacent (but for the overlap of mask 22) to the heavily doped region 41 on its source side but separated from the heavily doped region 43 some distance "d" on the drain side. The preferred distance for this separation is about 1 micrometer, but it could be as little as 0.5 micrometers and as much as the gate-to-drain electrode separation distance. The preferred dopant ion is silicon, although any dopant may be used. N-type doping is generally preferred and this can be obtained with silicon by meeting the anneal schedule criteria for n-type activation as previously described. This then suggests the utilization of a TiWN gate which can withstand an 810� C. anneal for 20 minutes without substantial degradation.
After completing the desired selective implant steps, the dielectric layer 14 is removed in hydrogen fluoride (HF). A metallization layer 20 is formed on a surface 26 which is the implanted surface of the wafer 11, all as shown in FIG. 3b. The metallization layer 20 is formed of titanium-tungsten nitride (TiWNx or TiWN for convenience). No stoichiometry is implied by this notation. This layer 20 of TiWNx departs from the metal layer 20 previously described with respect to FIG. 3 where the layer 20 was formed by the sputter deposition of titanium-tungsten to a depth of 2000 Å.
A second, and much more immediate factor, is the relative stability of TiWNx compared with TiW at the elevated temperatures encountered during sputtering of TiWNx and during the anneal and activation steps in FET manufacture. TiAs formation at the Schottky junction in TiW gate structures is detrimental to Schottky quality. Thus, the use of TiWNx as a Schottky gate provides superior characteristics relative to gates of TiW.
The photoresist mask 28 having windows 27 for the high-dose ion implant is formed on the surface 26 of the wafer 11. The gold mask 22 serves as a self-aligned structure for the ions which are directed to the window regions. The ions will be implanted in the regions at both sides of the T-shaped structures 24, with a controllable lateral separation between the gate's edges and the adjacent n+ regions. The metal etch mask 22 allows the creation of an implant-to-implant spacing larger than the gate length. This is an important feature of an optimized GaAs SAG process, since only by controlling the difference between these two dimensions can the device be optimized in the trade-off between gate capacitance and breakdown voltage versus parasitic series resistance. As previously explained, the photoresist 28 may be asymmetrically located relative to the gate to provide increased spacing of the n+ region (on the drain side of the gate) from the gate metal to further optimize device features, especially gate to drain capacitance. By using photoresist rather than the gate itself or another metal layer contacting the gate to laterally space the drain-side n+ implant from the gate, the capacitive coupling from the gate to the drain is still further reduced.
The wafer is then covered with approximately 3000 Å or less of a dielectric encapsulant 30. If an n' transition region is to be implanted to permit lower resistance between the n+ region and the n channel, the previously described process option is implemented and the structure is then annealed at approximately 850� C. for 20 minutes. The encapsulant 30 protects the GaAs wafer 11 from disassociation since the arsenic may vaporize at the high annealing temperature. Because the atomic percent of the nitrogen in the TiWNx enables the layer 20 to have unusually high thermal stability, only one annealing step for the channel, transition region and n+ region ion implants is needed. As discussed above, this allows optimum n-type activation of each implant, higher electron mobility, reduced parasitic resistances and superior device characteristics. It also eliminates the need for at least one annealing furnace and the need for separate annealing process steps thereby resulting in decreased fabrication costs. Still further, the TiAs formation typically encountered in prior approaches is not encountered due to the substantially greater stability of TiWNx relative to TiW and TiAs.
In order to ensure that the barrier properties of the TiWNx layer 20 are maintained and not severely degraded during subsequent processing of the wafer 11, the dielectric encapsulant 30 is selected to be plasma enhanced chemical vapor deposited silicon oxynitride (SiON) having a refractive index in the range of 1.55 to 1.95. This range of refractive indices is indicative of SiON having a good thermal match, i.e. similar coefficient of thermal expansion, with the gate and GaAs. A 1.55 refractive index is preferred. To establish an index of refraction of the SiON film in the given range, the N2 O/SiH4 gas flow ratio is adjusted during deposition of the encapsulant film. The encapsulant preferably totally encapsulates the gate.
In another preferred method as shown in FIG. 6, the annealing encapsulant 30 is left in place on the wafer 11 and embedded contacts 32 are formed by plasma etching the ohmic contact patterns through the encapsulant to the surface 26, then evaporating the metallization into the etched pattern and lifting off the pattern. Preferred materials for the contacts 32 include a first layer of a gold-germanium compound overlayed with nickel or a layered structure of nickel, germanium and gold. The contacts 32 are then alloyed into the GaAs surface 26 by rapidly heating to 380� C.-400� C. for 10 to 30 seconds, preferably with quartz-halogen tungsten lamps.
Additional levels of interconnect may be formed in the same way, and, if desired, the wafer can be given a final dielectric passivation coating for added electrical and scratch protection. Of course, conventional air-bridge technology may be used for second (and subsequent) levels of interconnect rather than the approach described above. In the foregoing description, dopants have generally been referred to as n-type. However, it is to be understood that the use of opposite dopant types could also be employed without departing from the invention. Also, where reference is made to implanting of an n-type dopant, it is intended to encompass the implantation of dopants which cause the implanted region to be n-type following activation. Thus, silicon is to be included since proper activation of silicon can cause it to be predominantly n-type after activation.
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