Source: http://www.google.com/patents/US6753206?dq=6289460
Timestamp: 2014-12-26 05:56:13
Document Index: 166392252

Matched Legal Cases: ['art 101', 'art 102', 'art 101', 'art 102', 'art 101', 'art 101', 'art 111', 'art 112', 'art 111', 'art 112', 'art 101', 'art 111', 'art 101', 'art 111', 'arts 102', 'art 111', 'art 101', 'art 101', 'art 101', 'art 101', 'art 101', 'art 111', 'art 101', 'art 101', 'art 101', 'art 101', 'art 101', 'art 111', 'art 111', 'art 101', 'art 101', 'art 101']

Patent US6753206 - Dual-chip integrated circuit package with unaligned chip arrangement and ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated...http://www.google.com/patents/US6753206?utm_source=gb-gplus-sharePatent US6753206 - Dual-chip integrated circuit package with unaligned chip arrangement and method of manufacturing the sameAdvanced Patent SearchPublication numberUS6753206 B2Publication typeGrantApplication numberUS 10/289,796Publication dateJun 22, 2004Filing dateNov 7, 2002Priority dateApr 12, 1999Fee statusPaidAlso published asUS6498391, US20030057566Publication number10289796, 289796, US 6753206 B2, US 6753206B2, US-B2-6753206, US6753206 B2, US6753206B2InventorsChien-Ping Huang, Lian-Cherng Chiang, Michael ChangOriginal AssigneeSiliconware Precision Industries Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (6), Classifications (45), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetDual-chip integrated circuit package with unaligned chip arrangement and method of manufacturing the sameUS 6753206 B2Abstract A dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated circuit package is used to pack two integrated circuit chips in an unaligned chip arrangement, in which the first integrated circuit chip is mounted to one side of the inner part of the first set of leads, and the second integrated circuit chip is mounted to the other side of the same in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing formed between the two sets of leads. This unaligned chip arrangement can help facilitate the wire-bonding process for the bonding pads on the second integrated circuit chip. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the first set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads. The particular structure of the dual-chip integrated circuit package allows no restriction to the relative size between the two integrated circuit chips, thus allowing flexible selection for the combination of the two integrated circuit chips. Moreover, the dual-chip integrated circuit package can help save layout space on the circuit board and offers more functionality and storage capacity.
preparing a leadframe having a first set of loads and a second act of leads, the first and second sets of leads being each defined into an inner part and an outer part, with a spacing being defined between the inner part of the first set of leads and the inner part of the second act of leads, wherein the inner part of the first set of leads is greater in length than the inner part of the second set of leads; mounting a first integrated circuit chip and a second integrated circuit chip on opposite sides of the inner part of the first set of leads, the first integrated circuit chip having a front side where at least one row of bonding pads are formed and a back side insulatively attached to a first side of the inner part of the first set of leads; and the second integrated circuit chip having a front side where one row of bonding pads are formed, with the front aide being insulatively partially attached to a second side of the inner part of the first set of leads in such a mariner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing; performing a first wire-bonding process to bond a first act of bonding wires to electrically connect the bonding pads on the first integrated circuit chip to the inner part of selected set of leads; performing a second wire-bonding process to bond a second set of bonding wires to electrically connect the bonding pads on the second integrated circuit chip to the inner part of selected set of leads; and performing a molding process to form an encapsulant for encapsulating the first integrated circuit chip, the second integrated circuit chip, the first set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads.
This application is a Division of Ser. No. 09/473,308, filed Dec. 28, 1999, U.S. Pat. No. 6,498,391.
A DIP (Dual In-Line Package) is a type of integrated circuit package that includes a metal leadframe with a die pad and a plurality of leads. An integrated circuit chip is mounted on the die pad and electrically connected via a set of conductive wires to the leads, and an encapsulant is formed to encapsulate the entire integrated circuit chip, the entire die pad, and part of the lead fingers therein so as to allow easy handling and utilization of the integrated circuit package and to protect the enclosed integrated circuit chip from being contaminated or damaged by outside objects.
In the design and manufacture, it is usually desired to mount as many integrated circuit chips in a single integrated circuit package as possible so as to allow one single integrated circuit package to offer more functions. An integrated circuit package that packs two integrated circuit chips therein is customarily referred to as a dual-chip integrated circuit package. Since a dual-chip integrated circuit package packs two integrated circuit chips rather than just one, it can help save layout space on the circuit board and offers more functionality and storage capacity. A conventional dual-chip integrated circuit package is disclosed in U.S. Pat. No. 5,012,323, whose structure is briefly described in the following with reference to FIGS. 8-10.
As shown in FIG. 8, the U.S. Pat. No. 5,012,323 utilizes a dual-row lead-frame 21 which includes a left part and a right part (as delimited by the dashed line 25). The left part includes a set of left-outer leads 23LO and a set of left-inner leads 23LI, while the right part includes a set of right-outer leads 23RO and a set of right-inner leads 23RI. Further, the left part is formed with a left slot 26L between the left-outer leads 23LO and the left-inner leads 23LI (as the area enclosed in the dashed box), while the right part is formed with a right slot 26R between the right-outer leads 23RO and the right-inner leads 23RI (as the area enclosed in the dashed box). The dual-chip integrated circuit package is used to pack two integrated circuit chips therein, including an upper die 41 and a lower die 43, as shown in FIGS. 9 and 10. The lower die 43 has its top side attached by means of an insulative adhesive layer 44 on the bottom side of the left-inner leads 23LI and the right-inner leads 23RI, while the upper die 41 has its back side attached by means of another insulative adhesive layer 42 on the upper side of the left-inner leads 23LI and the right-inner leads 23RI. As illustrated in FIGS. 9 and 10, the lower die 43 should be greater in size than the upper die 41 so as to allow the left side 43L and the right side 43R of the lower die 43 to extend respectively into the left slot 26L and the right slot 26R; and the length from the left side 41L to the right side 41R of the upper die 41 should be less than the distance between the left slot 26L and the right slot 26R so as to facilitate the wire-bonding process for electrically connecting the bonding pads 43LP and 43RP via the bonding wires 47 to the left-outer leads 23LO, the left-inner leads 23LI, the right-outer leads 23RO, and the right-inner leads 23RI. In a similar manner, the bonding pads 41LP, 41RP on the left side 41L and the right side 41R of the upper die 41 are electrically connected via the bonding wires 47 to the left-outer leads 23LO, the left-inner leads 23LI, the right-outer leads 23RO, and the right-inner leads 23RI. An encapsulant 24 is then molded to enclose the upper die 41, the lower die 43, the left-outer leads 23LO, the left-inner leads 23LI, the right-outer leads 23RO, and the right-inner leads 23RI.
The foregoing patent allows two integrated circuit chips of different purposes, for example a microprocessor chip and a memory chip, to be packed in the same integrated circuit package. Moreover, since each integrated circuit chip is attached on the leads of the leadframe, it can help reduce the jointed area between the integrated circuit chip and the leads; and as a result, delamination between the integrated circuit chip and the leads can be prevented under temperature change conditions. One drawback to the forgoing patent, however, is that the lower die 43 should be greater in size than the upper die 41 (see FIGS. 9 and 10) so as to allow the left side 43L and the right side 43R of the lower die 43 to extend into the left slot 26L and the right slot 26R for the purpose of positioning the bonding pads 43LP and 43RP in the left slot 26L and the right slot 26R to facilitate the wire-bonding process. For this reason, the foregoing patent is only suitable for use in TYPE II integrated circuit packages, which is the type whose outer leads are arranged on the longer sides of the integrated circuit package, and is unsuitable for use in TYPE I integrated circuit packages, which is the type whose outer leads are arranged on the shorter sides of the integrated circuit package. The flash memory chip is typically and suitably encapsulated a TYPE I integrated circuit package. Therefore, the fore-going patent cannot be used to pack two integrated circuit chips of which at least one is a flash memory chip to provide a doubled storage capacity from a single integrated circuit package. Still one more drawback to the foregoing patent is that the jointed area between each integrated circuit chip and the leads of the leadframe is still considered large.
SUMMARY OF THE INVENTION It is therefore an objective of this invention to provide a dual-chip integrated circuit package and a method of manufacturing the same, which can be used to pack two integrated circuit chips of various relative sizes.
It is another objective of this invention to provide a dual-chip integrated circuit package and a method of manufacturing the same, which is suitable for use to pack flash memory chips.
The dual-chip integrated circuit package of the invention includes the following constituent parts: (a) a leadframe having a first set of leads and a second set of leads, the first and second sets of leads being each defined into an inner part and an outer part, with a spacing being defined between the inner part of the first set of leads and the inner part of the second set of leads; (b) a first integrated circuit chip having a first side where at least one row of bonding pads are formed and a second side insulatively attached to a first side of the inner part of the first set of leads; (c) a second integrated circuit chip having a first side where at least one row of bonding pads are formed, with part of the first side being insulatively attached to a second side of the inner part of the first set of leads in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing; (d) a first set of bonding wires for electrically connecting the bonding pads on the first integrated circuit chip to selected part of the leads; (e) a second set of bonding wires for electrically connecting the bonding pads on the second integrated circuit chip to selected part of the leads; and (f) an encapsulant for encapsulating the first integrated circuit chip, the second integrated circuit chip, the first set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads.
FIG. 3 shows a schematic perspective view of the dual-chip integrated circuit package of FIG. 1 with a part cut away to show the inside structure;
FIG. 10 (PRIOR ART) shows a schematic sectional view of the integrated circuit package of FIG. 9 cutting through the line 10�10.
In this specification, the terms �die� and �chip� are interchangeable, which refer to an integrated circuit device cut from a fabricated wafer.
As shown in FIGS. 1 and 2, the dual-chip integrated circuit package of the invention includes a leadframe 1, a first integrated circuit chip 3, a second integrated circuit chip 5, a first set of bonding wires 6, a second set of bonding wires 7, and an encapsulant 8. The leadframe 1 is formed with a first set of leads 10 and a second set of leads 11. The first integrated circuit chip 3 is mounted on one side of the first set of leads 10 while the second integrated circuit chip 5 is mounted on the opposite side of the same. The first set of bonding wires 6 are used to electrically connect the first integrated circuit chip 3 to the second set of leads 11; while the second set of bonding wires 7 are used to electrically connect the second integrated circuit chip 5 to the first set of leads 10. The encapsulant 8 is used to encapsulate the two integrated circuit chips 3, 5, the bonding wires 6, 7, and part of the leads 10, 11 therein.
The first set of leads 10 is defined into an inner part 101 and an outer part 102, with the inner part 101 being enclosed in the encapsulant 8 and the outer part 102 being exposed to the outside of the encapsulant 8. The inner part 101 of the first set of leads 10 has a front side 103 and a back side 104. The first integrated circuit chip 3 is mounted on the front side 103 of the inner part 101 of the first set of leads 10, while the second integrated circuit chip 5 is mounted on the back side 104 of the same. Similarly, the second set of leads 11 is defined into an inner part 111 and an outer part 112, with the inner part 111 being enclosed in the encapsulant 8 and the outer part 112 being exposed to the outside of the encapsulant 8. A spacing 12 is defined between the inner part 101 of the first set of leads 10 and the inner part 111 of the second set of leads 11, which allows the second set of bonding wires 7 to pass therethrough. In accordance with the invention, the inner part 101 of the first set of leads 10 should be greater in length than either the first integrated circuit chip 3 or the inner part 111 of the second set of leads 11, so that the spacing 12 can be located at a distance away from the center of the leadframe 1. The leadframe 1 is made of a conductive material, such as copper, an copper alloy, an alloy of ferrite and nickel. The first integrated circuit chip 3 can be electrically coupled to an external device (not shown) via the first set of leads 10 and/or the second set of leads 11 of the leadframe 1, while the second integrated circuit chip 5 can do the same via the first set of leads 10 and/or the second set of leads 11 of the leadframe 1. The outer parts 102, 112 of the leads 10, 11 can be bent through a trim/form process into either a gull-wing shape, a J-like shape, or an L-like shape.
In this preferred embodiment, the two integrated circuit chips 3, 5 are each a flash memory device, which is formed with only one row of bonding pads, i.e., the first integrated circuit chip 3 is formed with one row of bonding pads 31 and the second integrated circuit chip 5 is also formed with only one row of bonding pads 51. The bonding pads 31 are formed on the front side 30 of the first integrated circuit chip 3 and positioned near the spacing 12, which are used to electrically connect the first integrated circuit chip 3 to the inner part 111 of the second sets of leads 11 via the first set of bonding wires 6. The back side 32 of the first integrated circuit chip 3 is attached by means of an insulative adhesive layer 90, such as a layer of polyimide resin or epoxy resin, on the front side 103 of the inner part 101 of the first set of leads 10, and which is positioned in such a manner as to leave a blank area 105 on the front edge of the inner part 101 of the first set of leads 10 to serve as a wire-bonding area for the second set of bonding wires 7. The front side 50 of the second integrated circuit chip 5 has one part attached by means of another insulative adhesive layer 91 on the back side 104 of the inner part 101 of the first set of leads 10, and the other part extending into the spacing 12 to allow the bonding pads 51 to be positioned within the spacing 12 so that the bonding pads 51 can be conveniently connected via the second set of bonding wires 7 to the inner part 101 of the first set of leads 10. This unaligned chip arrangement for the two integrated circuit chips 3, 5 allows a reduced dimension to the area of the inner part 101 of the first set of leads 10 that is attached to both of the two integrated circuit chips 3, 5, so that the invention can help eliminate the adverse effect of delamination due to temperature change in the encapsulating process that would otherwise occur in the prior art thus making the resultant integrated circuit package more reliable in use. Moreover, since the two integrated circuit chips 3, 5 are attached to the leads of a leadframe rather than to a die pad, the jointed area between the chips and the leadframe can be reduced as compared to the prior art, so that the possibility of delamination can be further reduced.
With the invention, there is no restriction to the relative size between the first integrated circuit chip 3 and the second integrated circuit chip 5, which means that the first integrated circuit chip 3 can be either greater than, equal to, or less than the second integrated circuit chip 5, provided that these two integrated circuit chips 3, 5 can be fitted to the inside space defined by the integrated circuit package.
The bonding wires 6, 7 are made of an electrically-conductive material, such as gold, copper, aluminum, or an alloy of these metals. The first set of bonding wires 6 are connected between the bonding pads 31 on the first integrated circuit chip 3 and the front side 113 of the inner part 111 of the second set of leads 11, while the second set of bonding wires 7 are connected between the bonding pads 51 on the second integrated circuit chip 5 and the front side 103 of the inner part 101 of the first set of leads 10. Since the bonding wires 6, 7 are both connected to the front sides 103, 113 of the leads 10, 11, the wire-bonding process can be easily carried out with conventional equipment and process. Moreover, since the two integrated circuit chips 3, 5 are oppositely attached to the inner part 101 of the first set of leads 10, they can provide a more firm support to the wire-bonding process, allowing the bonding wires 6, 7 to be reliably bonded in position. Furthermore, since the second set of bonding wires 7 are separated by a substantial distance from the upper surface 80 of the encapsulant 8, it allows the second set of bonding wires 7 to be bonded without having to use the precision wire looping control, allowing the manufacture process to be less complex.
Referring to FIG. 4 together with FIGS. 1-3, in the first step 401, a first chip-mounting process is performed to mount the second integrated circuit chip 5 on the back side 104 of the inner part 101 of the first set of leads 10 in such a manner that a part of the second integrated circuit chip 5 is attached by means of an insulative adhesive layer 91 and the other part is extending into the spacing 12, allowing the bonding pads 51 on the front side 50 of the second integrated circuit chip 5 to be positioned in the spacing 12.
In the next step 402, without having to turn the leadframe 1 upside down, a second chip-mounting process is performed to mount the first integrated circuit chip 3 in such a manner that the back side 32 of the first integrated circuit chip 3 is attached by means of an insulative adhesive layer 90 on the front side 103 of the inner part 101 of the first set of leads 10.
In the next step 403, a first wire-bonding process is performed to bond the second set of bonding wires 7 between the bonding pads 51 on the second integrated circuit chip 5 and the wire-bonding area 105 on the inner part 101 of the first set of leads 10, allowing the second integrated circuit chip 5 to be electrically connected to the first set of leads 10. These bonding wires 7 pass through the spacing 12.
In the next step 404, a second wire-bonding process is performed to bond the first set of bonding wires 6 between the bonding pads 31 on the first integrated circuit chip 3 and the front side 113 of the inner part 111 of the second set of leads 11, allowing the first integrated circuit chip 3 to be electrically connected to the second set of leads 11.
In the next step 405, a molding process is performed to form the encapsulant 8. During this process, since the two integrated circuit chips 3, 5 can be firmly supported by the first set of leads 10, the combined structure of the first integrated circuit chip 3, the second integrated circuit chip 5, and the first set of leads 10 would not be affected by the pressure from the encapsulation resin flow that would otherwise cause chip inclination and exposure of the bonding wires to the outside.
In the next step 406, a curing process is performed on the encapsulant 8. This process is a conventional technique so description thereof will not be further detailed.
In the final step 407, a trim/form process is performed on the leads 10, 11. This process is also a conventional technique so description thereof will not be further detailed This completes the manufacture of the dual-chip integrated circuit package of the invention.
As shown, this embodiment differs from the previous one only in that the two sets of bonding wires 6 b, 7 b are connected in a different manner; i.e., the first set of bonding wires 6 b are used to electrically connect the first integrated circuit chip 3 b to the first set of leads 10 b (rather than the second set of leads 11 b as in the case of the previous embodiment), and the second set of bonding wires 7 b are used to electrically connect the second integrated circuit chip 5 b to the second set of leads 11 b (rather than the first set of leads 10 b as in the case of the previous embodiment).
FIG. 6 is a schematic sectional diagram of the third preferred embodiment of the dual-chip integrated circuit package according to the invention. For distinguishing purpose, the reference numerals in FIG. 6 are appended with the letter �c�.
In this embodiment, the first integrated circuit chip 3 c is the type that includes two parallel rows of bonding pads 31 c, such as an ASIC chip or a DRAM chip, while the second integrated circuit chip 5 c is a flash memory chip including only one row of bonding pads 51 c. The two rows of bonding pads 31 c are connected via a first set of bonding wires 6 c respectively to the inner part 111 c of the second set of leads 11 c and to the inner part 101 c of the first set of leads 10 c, while the bonding pads 51 c are electrically connected via a second set of bonding wires 7 c to the wire-bonding area 105 c in the inner part 101 c of the first set of leads 10 c. Fourth Preferred Embodiment (FIG. 7)
As shown, this embodiment is mostly the same as the first embodiment except that an additional third set of bonding wires 13 d are connected between the inner part 101 d of the first set of leads 10 d and the inner part hid of the second set of leads 11 d for the purpose of parallel coupling the two integrated circuit chips 3 d, 5 d. The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5012323Nov 20, 1989Apr 30, 1991Micron Technology, Inc.Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframeUS5615475 *Aug 21, 1995Apr 1, 1997Staktek CorporationMethod of manufacturing an integrated package having a pair of die on a common lead frameUS5689135 *Dec 19, 1995Nov 18, 1997Micron Technology, Inc.Multi-chip device and method of fabrication employing leads over and under processesUS5804874Mar 4, 1997Sep 8, 1998Samsung Electronics Co., Ltd.Stacked chip package device employing a plurality of lead on chip type semiconductor chipsUS5898212Jan 17, 1997Apr 27, 1999Lg Semicon Co., Ltd.Lead frame and semiconductor packageUS6087718 *Dec 15, 1997Jul 11, 2000Lg Semicon Co., Ltd.Stacking type semiconductor chip package* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7029931 *Feb 3, 2004Apr 18, 2006Micron Technology, Inc.Stacked die module and techniques for forming a stacked die moduleUS7618848Aug 9, 2006Nov 17, 2009Stats Chippac Ltd.Integrated circuit package system with supported stacked dieUS7727816 *Jul 21, 2006Jun 1, 2010Stats Chippac Ltd.Integrated circuit package system with offset stacked dieUS7968996Sep 23, 2009Jun 28, 2011Stats Chippac Ltd.Integrated circuit package system with supported stacked dieUS8018041Apr 13, 2010Sep 13, 2011Stats Chippac Ltd.Integrated circuit package system with offset stacked dieUS8759954Aug 3, 2011Jun 24, 2014Stats Chippac Ltd.Integrated circuit package system with offset stacked die* Cited by examinerClassifications U.S. Classification438/109, 257/686, 257/E23.052, 257/E23.039, 438/64, 257/777, 257/E23.124International ClassificationH01L23/31, H01L23/495Cooperative ClassificationH01L24/32, H01L24/48, H01L24/49, H01L2225/06562, H01L2224/45124, H01L24/45, H01L2224/45147, H01L2924/01033, H01L2924/01005, H01L2924/01029, H01L2224/32245, H01L2224/73265, H01L2224/32014, H01L2924/01006, H01L23/3107, H01L2924/01047, H01L2924/01028, H01L2224/49171, H01L2924/01079, H01L2224/73215, H01L2224/48091, H01L2924/14, H01L2224/4826, H01L23/49575, H01L2924/01013, H01L2924/01082, H01L2224/45144, H01L23/4951, H01L2224/48247, H01L2924/1433, H01L2224/85439European ClassificationH01L24/49, H01L24/31, H01L23/495L, H01L23/495A4, H01L23/31HLegal EventsDateCodeEventDescriptionSep 22, 2011FPAYFee paymentYear of fee payment: 8Sep 27, 2007FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google