Source: http://www.google.com/patents/US6417725?ie=ISO-8859-1&dq=5,884,272
Timestamp: 2015-05-04 13:20:13
Document Index: 490108819

Matched Legal Cases: ['art 2', 'art 2', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09']

Patent US6417725 - High speed reference buffer - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA circuit to generate a reference voltage from a power supply based on a predetermined voltage level, the reference voltage being used by a switched capacitor analog to digital converter includes a follower connected between the power supply and a current source to output the reference voltage. An amplifier...http://www.google.com/patents/US6417725?utm_source=gb-gplus-sharePatent US6417725 - High speed reference bufferAdvanced Patent SearchPublication numberUS6417725 B1Publication typeGrantApplication numberUS 09/648,462Publication dateJul 9, 2002Filing dateAug 28, 2000Priority dateAug 28, 2000Fee statusPaidPublication number09648462, 648462, US 6417725 B1, US 6417725B1, US-B1-6417725, US6417725 B1, US6417725B1InventorsFarbod Aram, Sehat SutardjaOriginal AssigneeMarvell International, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (17), Non-Patent Citations (18), Referenced by (14), Classifications (10), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetHigh speed reference buffer
US 6417725 B1Abstract
A circuit to generate a reference voltage from a power supply based on a predetermined voltage level, the reference voltage being used by a switched capacitor analog to digital converter includes a follower connected between the power supply and a current source to output the reference voltage. An amplifier is connected in a negative feedback arrangement with the reference voltage and the predetermined voltage level so as to provide an output, and a buffer provides a buffered output based on the output of the amplifier. A low pass filter provides a filtered voltage for the follower based on the buffered output, and a charge pump, connected to the buffered output, causes current to flow to the buffered output. The input impedance of the buffer as viewed from the charge bump is low for low frequencies and higher for higher frequencies, whereas the input impendence of the filter as viewed from the charge pump is low for high frequencies and higher for lower frequencies.
What is claimed is: 1. A circuit to generate a reference voltage from a power supply, based on a predetermined voltage level, the reference voltage being used by a switched capacitor analog-to-digital converter, said circuit comprising:
a follower connected between the power supply and a current source to output the reference voltage; an amplifier connected in a negative feedback arrangement with the reference voltage and the predetermined voltage level so as to provide an output; a buffer to provide a buffered output based on the output of said amplifier; a low pass filter to provide a filtered voltage for said follower based on the buffered output; and a charge pump connected to the buffered output to cause current to flow to the buffered output; wherein input impedance of said buffer as viewed from said charge pump is low for low frequencies and higher for higher frequencies; and wherein input impedance of said filter as viewed from said charge pump is low for high frequencies and higher for lower frequencies. 2. A circuit according to claim 1, wherein said low pass filter comprises a resistor/capacitor circuit.
3. A circuit to generate a reference voltage, from a power supply, based on a predetermined voltage level, the reference voltage being used by a switched capacitor analog-to-digital converter, said circuit comprising:
a follower connected between the power supply and a current source to output the reference voltage; an amplifier connected in a negative feedback arrangement with the reference voltage and the predetermined voltage level so as to provide an output; a buffer to provide a buffered output based on the output of said amplifier; a low pass filter to provide a filtered voltage for said follower based on the buffered output; and a charge pump connected to the buffered output to cause current to flow to the buffered output; wherein input impedance of said buffer as viewed from said charge pump is low for low frequencies and higher for higher frequencies; and wherein input impedance of said filter as viewed from said charge pump is low for high frequencies and higher for lower frequencies, wherein said buffer includes a current sink in amplified feedback relation with a capacitor-shunted amplifier such that the input impedance of said buffer for low frequencies is the reciprocal of transconductance of said current sink divided by gain of said capacitor-shunted amplifier, and such that the input impedance of said buffer for higher frequencies is the inverse of transconductance of said current sink. 4. A circuit to generate a reference voltage, from a power supply, based on a predetermined voltage level, the reference voltage being used by a switched capacitor analog-to-digital converter, said circuit comprising:
follower means connected between the power supply and a current source, for outputting the reference voltage; amplifier means connected in a negative feedback arrangement with the reference voltage and the predetermined voltage level, for providing an output; buffer means for providing a buffered output based on the output of said amplifier means; low pass filter means for providing a filtered voltage for said follower means based on the buffered output; and charge pump means connected to the buffered output for causing current to flow to the buffered output; wherein input impedance of said buffer means as viewed from said charge pump means is low for low frequencies and higher for higher frequencies; and wherein input impedance of said filter means as viewed from said charge pump means is low for high frequencies and higher for lower frequencies. 5. A circuit according to claim 4, wherein said low pass filter means comprises a resistor/capacitor circuit.
6. A circuit to generate a reference voltage, from a power supply, based on a predetermined voltage level, the reference voltage being used by a switched capacitor analog-to-digital converter, said circuit comprising:
follower means connected between the power supply and a current source, for outputting the reference voltage; amplifier means connected in a negative feedback arrangement with the reference voltage and the predetermined voltage level, for providing an output; buffer means for providing a buffered output based on the output of said amplifier means; low pass filter means for providing a filtered voltage for said follower means based on the buffered output; and charge pump means connected to the buffered output for causing current to flow to the buffered output; wherein input impedance of said buffer means as viewed from said charge pump means is low for low frequencies and higher for higher frequencies; and wherein input impedance of said filter means as viewed from said charge pump means is low for high frequencies and higher for lower frequencies, wherein said buffer means includes current sink means in amplified feedback relation with a capacitor-shunted amplifier means such that the input impedance of said buffer means for low frequencies is the reciprocal of transconductance of said current sink means divided by gain of said capacitor-shunted amplifier means, and such that the input impedance of said buffer means for higher frequencies is the inverse of transconductance of said current sink means. 7. A reference voltage circuit to generate a reference voltage from a power supply comprising:
a charge pump; a buffer responsive to said charge pump and an amplified voltage to provide a bias voltage; a low pass filter responsive to the bias voltage to provide a filtered bias voltage; a follower responsive to the power supply, a current source, and the filtered bias voltage, to output the reference voltage; and an amplifier configured in a negative feedback arrangement with the reference voltage and a predetermined voltage to provide the amplified voltage, wherein input impedance of said buffer as viewed from said charge pump is low for low frequencies and higher for higher frequencies; and wherein input impedance of said filter as viewed from said charge pump is low for high frequencies and higher for lower frequencies. 8. A reference voltage circuit to generate a reference voltage from a power supply comprising:
charge pump means for providing a current; buffer means responsive to said charge pump and an amplified voltage for providing a bias voltage; low pass filter means for filtering the bias voltage to provide a filtered bias voltage; follower means responsive to the power supply, a current source, and the filtered bias voltage, for outputting the reference voltage; and amplifier means for differentially amplifying the reference voltage and a predetermined voltage to provide the amplified voltage, wherein input impedance of said buffer means as viewed from said charge pump means is low for low frequencies and higher for higher frequencies; and wherein input impedance of said filter means as viewed from said charge pump means is low for high frequencies and higher for lower frequencies. 9. A method for generating a reference voltage from a power supply comprising the steps of:
providing a current; buffering the current and an amplified voltage for providing a bias voltage such that an input impedance is low for low frequencies and higher for higher frequencies; low pass filtering the bias voltage to provide a filtered bias voltage such that an input impedence is low for high frequencies and higher for lower frequencies; outputting the reference voltage responsive to the power supply, a current source, and the filtered bias voltage; and differentially amplifying the reference voltage and a predetermined voltage to provide the amplified voltage.
This application is related to four other applications and all four applications are listed below. The contents of the two other applications, each filed concurrently herewith, are incorporated herein by reference as if set forth in full. (1) �Switched Capacitor Filter for Reference Voltages in Analog to Digital Converter� filed on Aug. 28, 2000 and assigned Ser. No. 09/648770; (2) �Analog-To-Digital Converter With Enhanced Differential Non-Linearity� filed on Aug. 22, 2000 and assigned Ser. No. 09/643819; (3) �Charge Pump for Reference Voltages in Analog to Digital Converter� filed on Aug. 28, 2000 and assigned Ser. No. 09/648464; and (4) �Frequency Compensation For a Linear Regulator�filed on Sep. 1, 2000 and assigned Ser. No. 09/654392.
The present invention relates to switched capacitor analog to digital converters (ADCs) and particularly relates to a current sink for use in establishing reference voltages for such ADCs.
Switched capacitor ADCs provide efficient high speed conversion of analog signals to digital signals. A representative switched capacitor ADC is shown at 10 in FIG. 1, in the form of a multi-stage pipelined ADC. As seen there, ADC 10 includes multiple stages, such as stages 11 and 12, each providing one or more bits of digital data to a digital correction circuit 15, which resolves the digital output from each stage into an overall digital output 16 that corresponds to an analog input 17. Each stage is a switched capacitor circuit operating in response to clock signals such as φ1 and φ2 and comparing an analog voltage input to thresholds based on reference signals Vrefp and Vrefn so as to produce the digital outputs as well as a residual analog signal. The residual analog signal is provided as input to the subsequent stage,
For proper operation of ADC 10, generators are needed for phase and timing signals as well as for reference voltages. These are shown respectively at 20 and 30 of FIG. 1. Thus, generator 20 for phase and timing signals generates clock signal φ1 for use during the sample phase of multiple stages 11 and 12, as well as clock signal φ2 for use during the amplification phase of multiple stages 11 and 12. Likewise, generator 30 generates reference voltages vrefp and Vrefn for use by multiple stages 11 and 12. The focus of the present application is on the generator 30 for the reference voltages.
FIG. 2 shows a conventional generator 30 for generating reference voltage Vrefp; a similar circuit shown schematically at 31 is used to generate reference voltage Vrefn. As shown in FIG. 2, generator 30 includes a follower 32 connected between voltage source V+ and a current source 35 which, in turn, is connected to ground. Follower 32 is driven at its gate side by amplifier 34, which is connected in negative feedback relationship using a reference voltage Vref as a reference and the output Vref as negative feedback. With this arrangement, follower 32 is driven by amplifier 34 so as to provide an output Vrefp with good current capabilities stabilized through negative feedback at a voltage level corresponding to Vref.
Problems arise, however, in use of generators in the form shown at 30. For example, due to higher frequency switching of generator 30, and due to noise/glitches generated from MDACS and capacitors which are connected to the reference generator 30, the amplifier 34 (FIG. 2) needs to be very fast, such that it can react quickly to the noise and reset Vrefp to an ideal value (e.g., preferably within a fraction of a clock period). How ever, this would be difficult to achieve for high speed ADcs. Also, amplifier thermal noise would be high in such cases, which would make the Vrefp signal noisy.
An alternative is to design a low bandwidth amplifier to slowly servo Vrefp, and to use an external capacitor (e.g., with a sufficiently large capacitance) to lower the impedance seen by the reference at high frequencies. This alternative may minimize switching glitches and noise, but it also requires extra circuitry, and for example, an extra pin.
Another problem involves the value of Vrefp relative to the source voltage V+. Specifically, because a voltage drop Vgs exists between the gate and source of follower 32, and because it is not possible for amplifier 34 to output a voltage greater than the supply voltage V+, the value of Vrefp must be lower than V+ by at least an amount equal to Vgs. Typically, Vgs is around 1v, and for adequate design margins, Vrefp is typically set to a value 1.5v less than source voltage V+. This amount of voltage drop, however, is wasteful and unnecessarily limits the dynamic conversion range of multiple stages 11 through 12.
In its most preferred form, a generator for reference voltage signals according to the invention is shown at 100 in FIG. 3. As seen there, the generator includes a follower 132 connected between a voltage source V+ and a current source 135 connected in turn to ground, as well as an amplifier 134 connected in negative feedback relationship with a reference voltage. Negative feedback to amplifier 134 is provided from the output of follower 132 (which forms the reference voltage signals Vrefp or Vrefn that are supplied to the ADC) through a switched capacitor filter 200.
Generator 100 generates reference voltages Vrefp and Vrefn for use by each of multiple stages 11 through 12. As �shown in FIG. 3, generator 100 generates reference voltage Vrefp which is output from the source terminal of follower 132 which is connected between voltage supply V+ and a current source 135 which in turn is connected to ground. Follower 132 is driven in negative feedback relationship to Vrefp through amplifier 134 whose reference is reference signal Vref. The negative feedback leg for amplifier 134 is provided through filter 200 which is a switched capacitor filter operating in synchronism with phase and timing signals φ1 and φ2 so as to sample and filter reference voltage Vrefp during known quiescent periods of the φ1 sample phase and the φ2 amplification phase.
A complementary reference voltage generator 101 is provided for Vrefn. Circuit 101 involves components similar to switched capacitor filter 200, current sink 300 and charge pump 400, but operates those components in complementary relationship to those of generator 100 in correspondence to the reversed roles of φ1 and φ2 in the generator
Each of the components of switched capacitor filter 200, current sink 300 and charge pump 400, are described in more detail below,
FIGS. 4A and 4B are views for explaining switched capacitor filter 200, which provides a final and settled value of the reference Vrefp signal for the feedback leg of amplifier 134. One difference between FIGS. 4A and 4B involves the presence in FIG. 4A of current sink 300 and charge pump 400, whereas those components are absent in the view of FIG. 4B. These views are therefore intended to reinforce the notion that less than all three components (i.e., switched capacitor filter 200, current sink 300 and charge pump 400) may be used in a generator for reference voltages, still with advantageous results.
General operating features of a switched capacitor filter 200 will be described with reference to FIGS. 4C through 4E. A source signal waveform is illustrated in each of these figures. As shown in FIGS. 4C and 4D, a combination of switches φ1 and φ2 (e.g., switches driven by clocks φ1 and φ2, respectively) and capacitor Cp1 is modeled as a resistor R=1/(f�Cp1), where f is the frequency of the φ1 and φ2 clocks. When φ1 and φ2 are non-overlapping clocks (e.g., as shown in FIG. 5), RCp2 low pass feedback is provided by the configuration shown in FIG. 4E, with R=T/Cp1=1/(f�Cp1). FIG. 4E illustrates the settling of the source signal.
Referring to FIGS. 4A and 4B, filter 200 includes switched capacitors Cp1 and Cp2 switched in accordance with clock signals φa and φb. Clock signals φa and φb are, in turn, timed relative to clock signal φ1 (sample) and clock signal φ2 (amplify) for ADC 10. Preferably, the value of Cp2 is much greater than Cp1. For example, Cp2 is advantageously ten times the size of Cp1, such as Cp2=1 picofarad and Cp1=100 femtofarads. The purpose of this relationship is explained in more detail below.
In general, φa is driven in synchronism with φ2 (amplification), but only after a time T1 from when amplification commences. The purpose for this delay T1 is to ensure that Vrefp has recovered to a relatively stable value after any initial noise spikes generated during initial stages of amplification by multiple stages 11 through 12. When φa closes, Cp1 samples the value of Vrefp, and holds that value after φa opens, during which time φb remains open.
φb, on the other hand, is driven in synchronism with φ1 (sample), or more precisely is driven out of synchronism with φa. φb closes while φa is open, thereby allowing any charge accumulated on capacitor Cp2 to mix with the charge newly acquired by capacitor Cp1, which reflects the current voltage level of Vrefp. It is the voltage accumulated on Cp2 that is provided to the negative feedback leg of amplifier 134, and that value is maintained even after φb opens.
FIG. 5 is a timing diagram showing operation of switched capacitor filter 200. As previously described, φ1 and φ2 are sample and amplification signals, respectively, φa is driven in synchronism with amplification phase φ2 but commencing a short time T1 after amplification begins, and φb is driven out of synchronism with φa and preferably in synchronism with φ1. Immediately after amplification phase φ2 commences, Vrefp is subjected to a voltage spike which is quickly accommodated by follower 132 so as to return to a nominal value. T1 is selected at design time so that it is timed for this nominal value. After time T1, φa closes thereby allowing the voltage on capacitor Cp1 (designated as Vcp1) to follow any change in voltage level that might have occurred since the last closure of φa. φa then opens, followed by closure of φb, at which time the charge on capacitor Cp1 is mixed with the charge currently stored on capacitor Cp2, thereby resulting in a change in voltage impressed across capacitor Cp2 (designated as Vcp2). As further shown in FIG. 5, the output value of Vrefp follows the change in voltage across capacitor, Cp2 by virtue of the negative feedback relationship caused by amplifier 134.
The value for capacitor Cp2 is much greater than that for Cp1 because the purpose of capacitor Cp1 is to sample the voltage of Vrefp quickly, whereas the purpose of capacitor Cp2 is to accumulate charge over a longer period of time and to provide a reasonable damping effect with good response time. This relationship is obtained with the previously-described 10:1 ratio between capacitances for cp2 and Cp1. In a preferred embodiment, the pole (p) of the Cp2 capacitor is p=(Cp1/Cp2)�f, where f equals 125 MHz, Cp1/Cp2 equals 0.1, yielding a pole (p) of 12.5 MHz.
Because capacitor Cp2 is filtered from high frequency noise injected by ADC 10 onto Vrefp, noise rejection from amplifier 134 (and onto follower 132) is greatly enhanced with respect to conventional feedback relationships. That noise rejection is reflected by the absence of any external capacitor such as Cext found in conventional voltage generators, because such an external capacitor is ordinarily not required.
Charge pump 400 is provided so as to produce an artificially elevated voltage level for follower 134, so that it is possible to run the reference voltages Vrefp and Vrefn very close to supply voltage V+, in spite of the presence of the voltage drop Vgs from gate to source of follower 132. FIG. 6 shows the operational principles of charge pump 400.
As shown in FIG. 6, the reference voltage Vrefp for ADC 10 is generated from the source terminal of follower 132 which is connected between supply voltage V+ and a current source, which, in turn, is connected to ground. Vrefp is monitored through a negative feedback relationship to amplifier 134 whose reference is provided by a reference voltage Vref and whose feedback leg is connected to switched capacitor filter 200. Alternatively, switched capacitor filter 200 need not be supplied. The output of amplifier 134 is provided to the gate of sink 135, whose source is connected to the gate of follower 132. Sink 135 is provided to allow a sink of current from drain to gate of follower 132, thereby providing an effectively low impedance looking inwardly toward sink 135 and amplifier 134.
Specifically, charge pump 400 takes voltage source V+ through a current source and a biasing resistor R3 and connects to two pairs of diagonally complementary switches S1 and S2. These switches operate in connection with capacitors C1 and C1 a which are biased in synchronism with operation of switches S1 and S2 through biasing pulse Vpulse.
Diagonally complementary operations of switches S1 and S2 occur in the right leg of charge pump 400. Thus, while switch S2 in the left leg is open, switch S1 in the right leg is closed, thereby providing a biased voltage previously-impressed on capacitor C1 a to voltage V5. This diagonally-complementary operation of switches ensures that the voltage at V5 is artificially elevated relative to supply voltage V+.
In practice, of course, the biased voltages across capacitors C1 and C1 a are depleted by operation of current sink 135. This is shown in the waveforms of FIG. 7.
As shown in FIG. 7 and as previously described, switches S1 and S2 operate complementarily, and Vpulse operates in synchronism with closure of switch S2. During the time when switch S1 is closed, the voltage from capacitor C1 at V4 charges to the value of supply voltage V+. Thereafter, when switch S1 opens and switch S2 closes, and the voltage of capacitor C1 is biasedby issuance of Vpulse, the voltage at V4 increases to an elevated level relative to supply voltage V+ as signified by V++. Operation of current sink 135, however, discharges capacitor C1, thereby resulting in a charge/discharge cycle signified at V5 in FIG. 7. Notably, although the voltage V5 does not maintain its highest level at V++, it nevertheless maintains an average level which is elevated with respect to V+.
As shown in FIG. 8, and focusing on the left leg of charge pump 400, switch S1 is formed by FET 401, and switch S2 is formed by a back-to-back connection of FET 402 and PMOSPET 404. Switch S1 is driven inversely from Vpulse through inverter 405, and capacitor C1 is biased in coordination with Vpulse through dual inverters 406. In addition, a helper capacitor C3 is switched and biased in coordination with capacitor C1 through FET 407 which operates as a switch.
Closure of switch S2 is a two-part operation. In the first part, since the value of V4 is approximately twice the value of reference voltage V+, it is not possible for FET 402 to turn on and allow capacitor C1 to discharge to current sink 135. However, by virtue of the diagonally complementary operation of the switches in the right and left legs of charge pump 400, FET 409 is currently on and voltage at V4′ is currently the same as supply voltage V+. The supply voltage drives the gate of PMOSFET 404 which therefore turns on and allows discharge of capacitor C1 to current sink 135. As capacitor C1 discharges, voltage at V4 decreases and will eventually decrease to a point where PMOS 404 can no longer remain on. However, by that time, the biased voltage from capacitor C3 allows FET 402 to turn on, thereby maintaining an �ON� state for switch S2 and continuously allowing capacitor C1 to discharge to sink 135. As will be appreciated by one of ordinary skill in the art, capacitor C2 and buffer 405 are configured as a level shifter.
Charge pump 400 can be modeled as a resistor Rcp and a voltage supply that preferably supplies a voltage of approximately two times (e.g., 2V+) a voltage source (e.g., V+), as shown in FIG. 10. A voltage V5 (i.e., V5=Vrefp+Vgs) is established such that the current (i) through the charge pump (e.g., Rcp) can be approximated by i=(2V+−(Vrefp+Vgs))/Rcp.
As shown in FIG. 9, current sink 300 includes a low pass filter 301 which may include a simple RC circuit, which provides an input impedance (as viewed from the charge pump) that is low for high frequencies and higher for lower frequencies. The output of low pass filter 301 is provided to follower 132. The input to low pass filter 301 is provided by a buffer composed of the combination of FETs 302, 303 and 304 and capacitors C1 and C2. Operation of this buffer is described in more detail below. Generally speaking, however, the buffer provides a buffered output based on the output of amplifier 134 and further provides an input impedance (as viewed from the charge pump) which is low for low frequencies and higher for high frequencies, thereby acting as a current sink for the output of charge pump 400.
The buffer is referred to generally at reference numeral 310 At low frequency operation of buffer 310, the impedance thereof is influenced primarily by the transconductance of FET 302 since capacitor C1 is essentially open. Specifically, at low frequencies the impedance of buffer 310 is the inverse of the transconductance of FET 302, divided by the gain provided by FETs 303 and 304, As a consequence, low frequency impedance of buffer 310 is lower than that of current sink 135 (FIG. 6) because of the amplifying effect of FETs 303 and 304.
At mid to high frequencies, capacitor C1 shorts. Consequently, in the absence of low pass filter 301, the input impendence of buffer 310 would increase to approximately the inverse of the transconductance of FET 302 (i.e., not divided by the gain of FETs 303 and 304). However, the presence of low pass filter 301 effectively ensures that at higher frequencies, the overall input impedance of current sink 300 remains low.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5162668 *May 4, 1992Nov 10, 1992International Business Machines CorporationSmall dropout on-chip voltage regulators with boosted power supplyUS5548205Jun 7, 1995Aug 20, 1996National Semiconductor CorporationMethod and circuit for control of saturation current in voltage regulatorsUS5648718Sep 29, 1995Jul 15, 1997Sgs-Thomson Microelectronics, Inc.Voltage regulator with load pole stabilizationUS5706240 *Mar 13, 1996Jan 6, 1998Sgs-Thomson Microelectronics S.R.L.Voltage regulator for memory deviceUS5852359Jul 8, 1997Dec 22, 1998Stmicroelectronics, Inc.Voltage regulator with load pole stabilizationUS5909109Dec 15, 1997Jun 1, 1999Cherry Semiconductor CorporationVoltage regulator predriver circuitUS5929616Jun 25, 1997Jul 27, 1999U.S. Philips CorporationDevice for voltage regulation with a low internal dissipation of energyUS6011666Jun 13, 1997Jan 4, 2000Fujitsu LimitedDisk unit and portable electronic equipmentUS6061306Jul 20, 1999May 9, 2000James BuchheimPortable digital player compatible with a cassette playerUS6084387Feb 3, 1999Jul 4, 2000Nec CorporationPower source circuit for generating positive and negative voltage sourcesUS6184746 *Aug 13, 1999Feb 6, 2001Advanced Micro Devices, Inc.PLL power supply filter (with pump) having a wide voltage range and immunity to oxide overstressUS6188212 *Apr 28, 2000Feb 13, 2001Burr-Brown CorporationLow dropout voltage regulator circuit including gate offset servo circuit powered by charge pumpUS6194887 *Nov 5, 1999Feb 27, 2001Nec CorporationInternal voltage generatorEP0982732A1Aug 24, 1999Mar 1, 2000Saehan Information Systems Inc.Portable MP3 player having various functionsEP0999549A2Nov 2, 1999May 10, 2000Telian A/V SystemsMP3 car playerJPH1028053A Title not availableWO1999048296A1Mar 16, 1999Sep 23, 1999Intertrust Tech CorpMethods and apparatus for continuous control and protection of media content* Cited by examinerNon-Patent CitationsReference1Bhupendra K. Ahuja, "An Improved Frequency Compensation Technique for CMOS Operational Amplifiers", IEEE Journal of Solid-State Circuits, vol. SC-18, No. 6, Dec. 1983, pp. 629-633.2Curtis Settles, "DSP-augmented CPU cores promise performance boost for ultra-compact drives", Data Storage, May 2000, pp. 35-38.3Paul C. Yu, et al., "A 2.5-V, 12-b, 5-Msample/s Pipelined CMOS ADC," IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp. 1854-1861.4Quantum Online / Inside Hard Disk Drives, "Part 2-A Closer Look at Hard Disk Drives"; "Chapter 3-Inside Hard Disk Drives-How They Work", Jun. 7, 2000.5Quantum Online / Inside Hard Disk Drives, "Part 2�A Closer Look at Hard Disk Drives"; "Chapter 3�Inside Hard Disk Drives�How They Work", Jun. 7, 2000.6Quantum Online / Recent Technological Developments, "Chapter 4-The Impact of Leading-Edge Technology on Mass Storage", Jun. 7, 2000.7Quantum Online / Recent Technological Developments, "Chapter 4�The Impact of Leading-Edge Technology on Mass Storage", Jun. 7, 2000.8Sehat Sutarja and Paul R. Gray, "A Pipelined 13-bit, 250-ks/s, 5-V Analog-to-Digital Converter", IEEE Journal of Solid-State Circuits, vol. 23, No. 6, Dec. 1988, pp. 1316-1323.9Stephen H. Lewis and Paul R. Gray, "A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 6, Dec. 1987, pp. 954-961.10Stephen H. Lewis, "Optimizing the Stage Resolution in Pipelined Multistage, Analog-to-Digital Converters for Video-Rate Applications", IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 30, No. 8, Aug. 1992, pp. 516-523.11Stephen H. Lewis, "Optimizing the Stage Resolution in Pipelined Multistage, Analog-to-Digital Converters for Video-Rate Applications", IEEE Transactions on Circuits and Systems�II: Analog and Digital Signal Processing, vol. 30, No. 8, Aug. 1992, pp. 516-523.12Stephen H. Lewis, et al., "A 10-b 20-Msample/s Analog-to-Digital Converter", IEEE Journal of Solid-State Circuits, vol. 27, No. 3, Mar. 1992, pp. 351-358.13Stephen H. Lewis, et al., "Indirect Testing of Digital-Correction Circuits in Analog-to-Digital Converters with Redundancy," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 42, No. 7, Jul. 1995, pp. 437-445.14Stephen H. Lewis, et al., "Indirect Testing of Digital-Correction Circuits in Analog-to-Digital Converters with Redundancy," IEEE Transactions on Circuits and Systems�II: Analog and Digital Signal Processing, vol. 42, No. 7, Jul. 1995, pp. 437-445.15U.S. application No. 09/643,819, Aram, filed Aug. 22, 2000.16U.S. application No. 09/648,464, Aram, filed Aug. 28, 2000.17U.S. application No. 09/648,770, Aram et al., filed Aug. 28, 2000.18U.S. application No. 09/654,392, Aram, filed Sep. 1, 2000.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6583746 *May 9, 2002Jun 24, 2003Mitsubishi Denki Kabushiki KaishaA/D converter with high speed input circuitUS6891357 *Apr 17, 2003May 10, 2005International Business Machines CorporationReference current generation system and methodUS7098735 *Apr 30, 2004Aug 29, 2006Broadcom CorporationReference buffer with dynamic current controlUS7132821Apr 11, 2005Nov 7, 2006International Business Machines CorporationReference current generation systemUS7215182Sep 12, 2005May 8, 2007Analog Devices, Inc.High-performance, low-noise reference generatorsUS7288990 *Dec 2, 2005Oct 30, 2007Broadcom CorporationReference buffer with dynamic current controlUS7382305Feb 26, 2007Jun 3, 2008Analog Devices, Inc.Reference generators for enhanced signal converter accuracyUS7573414 *Dec 6, 2007Aug 11, 2009Texas Instruments IncorporatedMaintaining a reference voltage constant against load variationsUS7636057May 2, 2008Dec 22, 2009Analog Devices, Inc.Fast, efficient reference networks for providing low-impedance reference signals to signal converter systemsUS7652601May 2, 2008Jan 26, 2010Analog Devices, Inc.Fast, efficient reference networks for providing low-impedance reference signals to signal processing systemsUS7719345Jul 9, 2008May 18, 2010Mediatek Inc.Reference buffer circuitsUS7791405 *May 28, 2008Sep 7, 2010Infineon Technologies AgMethod for controlling an output voltage and voltage controllerUS7830288Jan 25, 2010Nov 9, 2010Analog Devices, Inc.Fast, efficient reference networks for providing low-impedance reference signals to signal processing systemsDE10215748A1 *Apr 10, 2002Dec 24, 2003Infineon Technologies AgVerfahren und Schaltungsanordnung zur elektronischen Spannungsregelung* Cited by examinerClassifications U.S. Classification327/541, 327/543, 341/155, 323/313International ClassificationH02M3/07, H03M1/12Cooperative ClassificationH02M3/073, H02M2003/077, H03M1/12European ClassificationH02M3/07SLegal EventsDateCodeEventDescriptionJan 9, 2014FPAYFee paymentYear of fee payment: 12Jan 11, 2010FPAYFee paymentYear of fee payment: 8Jan 9, 2006FPAYFee paymentYear of fee payment: 4Feb 2, 2001ASAssignmentOwner name: MARVELL INTERNATIONAL LTD., BERMUDAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL TECHNOLOGY GROUP, LTD.;REEL/FRAME:011562/0263Effective date: 20010119Owner name: MARVELL INTERNATIONAL LTD. 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