Source: http://www.google.com/patents/US4731837?dq=actionscript
Timestamp: 2015-08-02 04:59:35
Document Index: 798974351

Matched Legal Cases: ['Application No. 1', 'Application No. 1', 'Application No. 1', 'Application No. 2', 'Application No. 1', 'Application No. 1']

Patent US4731837 - Method and device for secure transmission and of television pictures - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA process for scrambling and unscrambling the image part of a sampled MAC ne video signal excluding the synchronization signal begins by dividing at two dividing points the MAC luminance signal and the chrominance signal to form two pairs of segments that are adjacent in each pair. For both transmission...http://www.google.com/patents/US4731837?utm_source=gb-gplus-sharePatent US4731837 - Method and device for secure transmission and of television picturesAdvanced Patent SearchPublication numberUS4731837 APublication typeGrantApplication numberUS 06/909,617Publication dateMar 15, 1988Filing dateSep 22, 1986Priority dateMar 21, 1983Fee statusLapsedAlso published asDE3464188D1, EP0119945A1, EP0119945B1, US4633310Publication number06909617, 909617, US 4731837 A, US 4731837A, US-A-4731837, US4731837 A, US4731837AInventorsChristian J. F. GautierOriginal AssigneeEtablissement Public De Diffusion Dit "Telediffusion De France"Export CitationBiBTeX, EndNote, RefManPatent Citations (3), Referenced by (4), Classifications (5), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetMethod and device for secure transmission and of television pictures
US 4731837 AAbstract
A process for scrambling and unscrambling the image part of a sampled MAC ne video signal excluding the synchronization signal begins by dividing at two dividing points the MAC luminance signal and the chrominance signal to form two pairs of segments that are adjacent in each pair. For both transmission and reception each one of two dividing points between the two segments is synchronously defined in a pseudo-random manner to form a pair slightly overlapping in the neighborhood of the pertinent dividing point. The segments are processed in each pair as a whole in order to scramble prior to transmission and again to unscramble upon reception so as to restore the initial video signal.
1. A process for scrambling and unscrambling the image part of a sampled MAC line video signal excluding the synchronization signal, said process comprising the steps of respectively dividing at two dividing points the MAC luminance signal and the chrominance signal to form two pairs of segments that are adjacent in each pair, each one of the segments comprising at least two samples, synchronously defining in a pseudo-random manner for both transmission and reception each one of two dividing points between the two segments, the two segments forming a pair slightly overlapping in the neighborhood of the pertinent dividing point, and processing the segments in each pair as a whole in order to scramble prior to transmission and again to unscramble upon reception so as to restore the initial video signal.
2. A process according to claim 1, wherein both of the division points are similarly positioned in both the luminance signal and the chrominance signal.
This is a division of Ser. No. 590,708, filed Mar. 19, 1984, now U.S. Pat. No. 4,633,310.
It is recalled that, generally speaking, scrambled television broadcasts are meant for users who are equipped with unscrambling means sufficient to permit them to post on the screen of their receiving sets clear images. The images posted on the screens of the receiving sets of other users are unrecognizable and difficult, if not painful, to watch. The scrambled signal may be carried over any transmission path using the standards which are in force, whether in the ground or broadcast network, or satellite network.
A first component brings into play inversions of modulation polarity. In this respect, it is possible to mention the processes described in the French Application. No. 2 330 236, West German Application No. 1 907 580, French Application No. 1 034 776, U.S. Pat. No. 2,972,009 and West German Application No. 1 254 676.
The second and third scrambling components bring into play position shifts of the information carried by a television image line, with respect to the synchronization signals. Those shifts affect either to totality of the information of the line, causing a simple lag effect, or they affect portions of lines, causing circular shifting effects.
Simple lag effects, which constitute the second scrambling component, make it difficult, if not painful, for the comprehension of the transmission but alone, they do not ensure the confidentiality of the message. That results from the fact that the television image transmission standards do not permit any important shifts between the synchronization information and the image information, without cutting off from the image a length of information equal to the maximum shift. Simple lag effects are provided for in the following patents: French Application No. 2 330 236, West German Application No. 1 907 580, U.S. Pat. Nos. 2,510,046, 2,619,530 and West German Application No. 1 254 676. It is also possible to include the effect created in U.S. Pat. No. 2,892,882, where the width of the line synchronization impulse is made to vary between two values.
FIG. 1 represents a video signal line having a positive polarity, comprising the line synchronization impulse S, the elimination level P, the chrominance burst CH and the useful signal V. The original time t0 of the periods corresponds to the front or leading edge of the synchronization signal S. Between time t2, corresponding to the beginning of the suppression level, and time t1, immediately preceding the beginning of the reference burst, the video signal still is directly transmitted, that is to say, sampled, but without passage into the memory. The time elasped between t0 and t1 is 5.24 microseconds. The chrominance burst, which ends 5.24 microseconds after t1, is sampled, then put into memory, as is the remainder of the non-scrambled line. Scrambling essentially bears on the useful signal V, which ends at time t2, that is to say 52 microseconds after the end of burst CH. Signal V is sampled, then written into memory, in order to be, partially at least, read in an order which is different from the one it was written in. The unit formed by signals CH and V is sampled on 1014 useful samples, sampling being done, for example, at the frequency of 17.734 MHz, which corresponds to 11,235 times the line frequency HL. Under those conditions, samples V1 to V92 correspond to the reference burst CH, while samples V93 to V1014 form the useful signal V.
In the scrambling circuit represented in FIG. 4, the analog video signal to be scrambled is introduced by connection E into a fitering and adaptation circuit 1. Circuit 1 is first of all a filter which performs the frequential calibrating of the signal from 0 to 6 MHz. That filtering is necessary prior to the sampling, in order to avoid the spectrum recoiling phenomena. Circuit 1 also executes an adaptation, delivering at its output a signal under a low impedance.
Circuit 3 extracts from the incidence analog video signal time informations which are the line synchronization signals and the scan synchronization signals, and it develops the switching signal which is transmitted, through line 5, to clamping circuit 2. Such a circuit is commercialy available under Reference No. TDA9400 or TDA 9500, sold by the ITT Semiconductors firm. Circuit 3 has an FT output for the scan clock synchronization, and an output FH for the line synchronization. Those outputs are connected to the inputs of a line identification circuit 6.
Circuit 6 is a line counting device, one output 7 of which delivers characteristic signals of idenfication of lines 17 and 623, an output 8 and an output 11 which identifies the scan suppression lines. Output FH is connected to the input of the governing input for the controlling of an oscillator 9 which preferably is of the auxiliary oscillator type, and which is provided to generate a clock at the frequency of 1135 FH, that is to say again 17.734 MHz. Oscillator 9 has an output H which delivers the sampling clock or general point clock.
The output of multiplexer 16 is connected to an input of an OR gate 60, the output of which is connected to the input of a digital/analog converter 19, the clock input H of which is connected to 9. The analog output of D/A converter 19 is connected to the input of a correction and filtering circuit 26. Circuit 26 corrects the weakening of the high frequencies of the useful signal, and it eliminates the undesirable residues produced by the sampling.
Reading counter 21 has its authorization input connected to the output 61 of the line time base 5, its clock input connected to H, and a loading input connected to the output of a pseudo-random sequence generator 24. When counter 21 is enabled, it counts as a function of the number of p supplied by the generator 24, in a manner which will be described below.
Circuit 4 is a circuit which produces the data which the receiver needs in order for it to find the unscrambling key. Through connection 8, it receives from the line identification circuit 6, the information of time position of lines 310 and 622. It delivers, through line 27, for one part to generator 24, the data of the unscrambling key and, for the other part, to a data insertion circuit 30, the same data of the key. Circuit 4 has another output 28 which makes it possible for it to signal each change of key to the receiver. To that end, output 28 is connected to the input of an OR gate 62 the output of which is connected to an input of an AND gate 63 with three inputs, the second input of which is connected to clock H, the third input of which is connected, by means of an inverter 4, to an output 65 of the line time base 25, and the output of which is connected to the second input of the OR gate 60. The second input of the OR gate 62 is connected to the output 7 of the line identification circuit 6. With respect to the structure of circuit 4, reference will be made to the description of French Pat. No. 2 459 595.
In the unscrambling circuit in FIG. 5, the analog video signal which is scrambled and is received from the scrambling circuit in FIG. 4, is introduced through the connection Er. The unscrambling circuit in FIG. 5 comprises numerous elementary circuits, either identical or similar to those of the scrambling circuit. Indeed, there is found in it, an input filter 33, a clamping circuit 34, an analog/digital converter 36, two sample memories 37 and 38, a three input multiplexer 39, a digital/analog converter 40, an output filter 41, a synchronization extraction circuit 42, a line counter 43, a controlled oscillator 44, a divider by 2, 45, two multiplexers with two inputs 46 and 47, a writing counter 48, a reading counter 49, a line time base 50, a logical circuit 51, and an random sequence generator 52, the corresponding circuits in FIG. 4 being the circuits 1, 2, 12, 14, 15, 16, 19, 26, 3, 6, 9, 10, 22, 23, 20, 21, 25, 32 and 24. All of the interconnections between corresponding circuits are practically the same ones. However, there will be noted that between the output of clamping circuit 34 and the output of the A/N coverter 36, there is mounted in series an amplifier with CAG 35, and that the output of multiplexer 39 is directly connected to the input of the D/A converter 40. Finally, the output of filter 41 constitutes the output of the descrambling circuit. In addition, circuit 4 is replaced by two circuits 56 and 58, and circuit 30 obviously is eliminated.
In practice, the access control circuit 58 is a DIDON data receiver the description of which can be found in French Pat. No. 2 313 825. Circuit 58 receives the complete video signal from filter 33, it draws out of the data transmitted in certain lines of scan elimination affected to that service, the key calculation data which have been transmitted, it combines them with the data recorded on the subscription card 59, as described in French Pat. No. 2 459,595, and finally, it presents at its output, what has been agreed to call the key.
In the scrambling mode illustrated in FIG. 3a, from address 92, the reading of the memory is then done at address (p+k), then counter 21 is decremented until address 93, then the address jumps to p and finally the counter is incremented until address (1014-k). It is necessary to note here that the pseudo-random generator 24 is capable of delivering any number of p's between 1 and 1024, something which, without any precaution, would position the cut off outside the V93 to V1014 zone represented in FIG. 1. That is why reading counter 21 comprises means to add 128 to the number p supplied by 24 when the latter is inferior to 93, and to cut off 16 from that number which is supplied when the latter is inferior to 104.
In the manner represented in FIG. 3a, starting from address 92, the writing in the memory is first done at address (p+k), then counter 48 is decremented until address 93, then the counter sends no writing address during k' strokes of the clock, then it jumps to the address (p+k+1) and finally it is incremented until address (1014-k).
In the mode of scrambling, illustrated in FIG. 3c, starting from address 92, a reading of the memory is first done at address 93, then the counter is incremented until address (p +k), then the address jumps to address (1014-k) and, finally, the counter is decremented to address p.
Those who are skilled in the art will readily perceive how to modify the invention. Therefore, the appended claims are to be construed to cover all equivalent structures which fall within the true scope of spirit of the invention.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4600942 *Nov 27, 1984Jul 15, 1986Telease, Inc.Secure coding and decoding system and method for television program signalsUS4633310 *Mar 19, 1984Dec 30, 1986Gautier Christian J FMethod and device for secure transmission and of television picturesFR2431809A1 * Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS4995079 *Aug 7, 1989Feb 19, 1991Samsung Electronics Co., Ltd.Canal+ decoder switching circuit for video cassette recordersUS5191609 *Mar 26, 1991Mar 2, 1993Samsung Electronics Co., Ltd.Scrambling and unscrambling circuitUS5933499 *Oct 14, 1994Aug 3, 1999Canon Kabushiki KaishaImage processing apparatusUS6519341Jun 18, 1999Feb 11, 2003Canon Kabushiki KaishaMethod and apparatus for outputting a high definition image* Cited by examinerClassifications U.S. Classification380/215, 348/E07.059International ClassificationH04N7/169Cooperative ClassificationH04N7/1696European ClassificationH04N7/169CLegal EventsDateCodeEventDescriptionAug 9, 1991FPAYFee paymentYear of fee payment: 4Jun 30, 1995FPAYFee paymentYear of fee payment: 8Oct 5, 1999REMIMaintenance fee reminder mailedMar 12, 2000LAPSLapse for failure to pay maintenance feesMay 23, 2000FPExpired due to failure to pay maintenance feeEffective date: 20000315RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services