Source: https://patents.google.com/patent/JP3984014B2/en
Timestamp: 2020-01-24 18:45:01
Document Index: 758023482

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JP3984014B2 - Method for manufacturing substrate for semiconductor device and substrate for semiconductor device - Google Patents
Method for manufacturing substrate for semiconductor device and substrate for semiconductor device Download PDF
JP3984014B2
JP3984014B2 JP2001293781A JP2001293781A JP3984014B2 JP 3984014 B2 JP3984014 B2 JP 3984014B2 JP 2001293781 A JP2001293781 A JP 2001293781A JP 2001293781 A JP2001293781 A JP 2001293781A JP 3984014 B2 JP3984014 B2 JP 3984014B2
JP2001293781A
JP2003100641A (en
藤 力 佐
田 敬 山
島 一 郎 水
野 元 永
松 尚 人 親
2001-09-26 Priority to JP2001293781A priority Critical patent/JP3984014B2/en
2003-04-04 Publication of JP2003100641A publication Critical patent/JP2003100641A/en
2007-09-26 Publication of JP3984014B2 publication Critical patent/JP3984014B2/en
A field effect transistor formed on an SOI (Silicon On Insulator) substrate can operate at high speed and can constitute a high-speed logic circuit. In recent years, there is a great demand for semiconductor devices such as system LSIs in which such high-speed logic circuits and DRAMs are mixedly mounted.
On the other hand, when the DRAM is formed in the SOI layer, charges are accumulated in the body region of the DRAM memory cell transistor due to the substrate floating effect of the SOI layer, causing deterioration of retention due to unexpected leakage of the DRAM and the sense amplifier circuit. In such a case, the threshold value of the pair transistor is shifted.
In order to solve this substrate floating effect, there is a method of controlling the potential of the SOI layer by providing a contact in the element region.
However, since the contact is provided in the element region, the cell area of the DRAM, the area of the sense amplifier circuit, and the like increase, and high integration cannot be achieved.
Therefore, there is a method of forming a substrate provided with an SOI region and a non-SOI region (hereinafter referred to as a partial SOI substrate). The SOI region has a semiconductor layer formed on an insulating layer formed on a semiconductor substrate, and the non-SOI region has a single crystal layer formed on the semiconductor substrate without an insulating layer interposed therebetween.
The semiconductor device formed in the non-SOI region is not affected by the substrate floating effect. Therefore, by forming a field effect transistor in the SOI region and forming a DRAM in the non-SOI region, a system LSI on which a high-speed logic circuit and a DRAM not affected by the substrate floating effect are mounted can be formed.
As a first method for forming a partial SOI substrate, a SIMOX (Separation by Implantation of Silicon) method (refer to Japanese Patent Laid-Open No. 10-303385 or Symposium on VLSI2000) is used as a first method, and an insulating film is patterned as a second method. A method of bonding another silicon substrate on a silicon substrate (see JP-A-8-316431), and as a third method, a SOI layer and an insulating layer (hereinafter also referred to as a BOX (Buried Oxide) layer) of the SOI substrate are partially There are methods for removing by etching (see JP-A-7-106434, JP-A-11-238860 or JP-A-2000-91534).
According to the SIMOX method, which is the first method, oxygen ions are implanted, and defects are likely to occur in the SOI layer crystal or the bulk layer crystal. According to the second method, there is a region where the silicon substrates are bonded together. Therefore, in the portion where the silicon substrates are bonded to each other, the crystal orientation is shifted and a crystal defect occurs. According to the third method, a step is generated at the boundary between the SOI region and the non-SOI region, which adversely affects subsequent processes such as a reduction in focus margin in the lithography process.
On the other hand, according to the third method, although there is a step between the SOI region and the non-SOI region, there are few crystal defects of the SOI substrate and the quality is compared with the first method and the second method. Good.
In order to flatten the step between the SOI region and the non-SOI region generated by the third method, there is a method in which an epitaxial layer is formed in the non-SOI region and polished (see Japanese Patent Laid-Open No. 2000-243944).
However, according to this method, since the BOX layer is etched by RIE (Reactive Ion Etching), the silicon substrate under the BOX layer is damaged by the plasma and causes crystal defects.
Therefore, regardless of RIE etc., NH 4 It is preferable to selectively remove the BOX layer by wet etching by chemical reaction using F solution or the like. However, since wet etching using a solution is isotropic, the BOX layer is side-etched.
6A and 6B are enlarged cross-sectional views of a partial SOI substrate having an SOI region and a non-SOI region obtained by wet-etching the BOX layer 20 according to a conventional method. On the semiconductor substrate 10, a BOX layer 20, an SOI layer 30 and a mask layer 40 are formed in the order of the BOX layer 20, the SOI layer 30 and the mask layer 40. The SOI layer 30 is etched by RIE using the patterned mask layer 40. Furthermore, the BOX layer 20 is selectively wet etched using a solution.
Here, in the semiconductor substrate 10, the region where the BOX layer 20 and the SOI layer 30 remain is the SOI region 60, and the region where the BOX layer 20 and the SOI do not remain is the non-SOI region 70. A region where one of the BOX layer 20 or the SOI layer 30 remains and the other does not remain is defined as a boundary region 80.
Next, in the non-SOI region 70, the semiconductor substrate 10 is exposed. A single crystal layer 50 is grown from the exposed surface of the semiconductor substrate 10.
When the BOX layer 20 is wet-etched, the BOX layer 20 is side-etched not only in the substrate direction toward the semiconductor substrate 10 but also in the lateral direction perpendicular to the direction toward the surface of the semiconductor substrate 10. As a result, the SOI layer 30 may be lifted off in a pattern in which the width of the SOI layer 30 is not more than twice the side-etched width. Further, when the single crystal layer 50 is grown, the single crystal also grows from the side surface of the SOI layer 30. Since the SOI layer 30 is located higher than the surface of the semiconductor substrate 10, the single crystal from the side surface of the SOI layer 30 grows higher than the single crystal from the semiconductor substrate 10. Therefore, the bump 55 is formed at or near the boundary region 80 (see FIG. 6A). Crystal defects occur on the surface of the semiconductor device substrate in the vicinity of the bump 55. Further, in order to form a flat semiconductor device substrate, a polishing process for polishing the bumps 55 is required.
Since the mask layer 40 is removed in a later step, the substrate surface becomes flat if the flat surface of the single crystal layer 50 and the surface of the SOI layer 30 are in the same plane. Accordingly, in FIG. 6A, the flat surface of the single crystal layer 50 and the surface of the SOI layer 30 are drawn at the same level.
As a method for solving these problems, as shown in FIG. 6B, there is a method in which the side surface of the SOI layer 30 is covered with a sidewall protective film 90 after the SOI layer 30 is etched. This reduces the risk that the SOI layer 30 will lift off.
However, when the sidewall protective film 90 is thinner than the BOX layer 20, the back surface of the SOI layer 30 is exposed when the BOX layer 20 is etched. Therefore, the single crystal still grows from the back surface of the SOI layer 30 and the bump 55 is formed at or near the boundary region 80.
On the other hand, forming the sidewall protective film 90 thicker than the thickness of the BOX layer 20 is not preferable because it increases the manufacturing cost and makes the process for forming the sidewall protective film 90 difficult.
Therefore, an object of the present invention is to provide a method for manufacturing a substrate for a semiconductor device having a flat surface in which there are few defects in a surface crystal and there is no step between a region having an SOI structure and a region having no SOI structure. And providing a substrate for a semiconductor device.
A method of manufacturing a substrate for a semiconductor device according to an embodiment of the present invention includes a mask layer forming step of forming a patterned mask layer on a semiconductor layer insulated from the semiconductor substrate by an electrically insulating layer. A trench forming step of etching at least the semiconductor layer according to the pattern of the mask layer to form a trench penetrating the insulating layer; and a protective layer deposited on the semiconductor substrate that is thinner than the thickness of the insulating layer. A protective portion forming step for forming a sidewall protective portion covering the side surface of the trench by etching; an etching step for etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and the insulating layer is etched. A single crystal layer forming step for growing a single crystal layer from the exposed surface of the semiconductor substrate. Comprising a flop, the.
Preferably, in the etching step, the insulating layer from the bottom surface of the trench to the semiconductor substrate is etched at least a portion relatively close to the bottom surface of the trench and a portion relatively close to the semiconductor substrate is etched. It is a two-stage etching step in which etching is performed separately from the substrate side etching to be etched, and the protection portion forming step is performed before the trench side etching or before the substrate side etching.
Preferably, the trench side etching is anisotropic etching, and the substrate side etching is isotropic etching.
Preferably, both of the etching in the trench side etching and the etching in the substrate side etching are isotropic etching, and in the trench side etching, the insulating layer existing under the semiconductor layer is etched toward the side surface of the trench. The protective part forming step is performed after the trench side etching and before the substrate side etching, and the side wall protective part includes the side surface of the trench and the insulating layer etched by the trench side etching. Formed below the semiconductor layer.
Preferably, the isotropic etching is wet etching performed in a liquid phase, and the anisotropic etching is dry etching performed in a gas phase.
In the trench formation step, the etching of the semiconductor layer is isotropic etching, and the semiconductor layer existing under the mask layer is etched in the direction of the side surface of the trench, and in the protection portion formation step, The sidewall protection part may be formed below the semiconductor layer where the semiconductor layer etched by the trench forming step was present, and the etching in the etching step may be isotropic etching.
According to another embodiment of the present invention, there is provided a method of manufacturing a substrate for a semiconductor device, comprising: forming a patterned mask layer on a semiconductor layer insulated from the semiconductor substrate by an electrically insulating insulating layer; Forming at least one of the semiconductor layers isotropically according to the pattern of the mask layer to etch the semiconductor layer existing under the mask layer in the direction of the side surface of the trench and penetrating into the insulating layer; A trench forming step for forming a trench; and isotropically etching the insulating layer from the bottom surface of the trench to the semiconductor substrate to etch the insulating layer present under the semiconductor layer toward a side surface of the trench An etching step, and a single connection from the surface of the semiconductor substrate exposed by etching the insulating layer. Growing a layer.
Preferably, the isotropic etching is wet etching performed in a liquid phase.
A semiconductor device substrate according to an embodiment of the present invention includes a semiconductor substrate having a surface, an electrically insulating insulating layer, and a semiconductor layer insulated by the insulating layer formed on the surface. An insulating region, a non-insulating region having a single crystal layer formed on the surface, and a sidewall protection part covering at least a side surface of the semiconductor layer present in a boundary region between the insulating region and the non-insulating region. And the side surface of the insulating layer that exists in the boundary region between the insulating region and the non-insulating region is located closer to the non-insulating region than the side surface of the semiconductor layer.
Preferably, the thickness of the side wall protection part from the side surface of the semiconductor layer is smaller than the thickness of the insulating layer from the semiconductor substrate.
Preferably, of the side surfaces of the insulating layer, the side surface in the vicinity of the semiconductor substrate is present closer to the non-insulating region than the side wall of the semiconductor layer.
Of the side surfaces of the insulating layer, the side surface in the vicinity of the semiconductor layer may be closer to the insulating region than the side wall of the semiconductor layer.
A semiconductor device substrate according to another embodiment of the present invention includes a semiconductor substrate having a surface, a first insulating layer that is electrically insulative on the surface, and insulation by the first insulating layer. An insulating region having a second insulating layer formed on the semiconductor layer, and a non-insulating region having a single crystal layer formed on the surface, the insulating region The side surface of the semiconductor layer and the side surface of the first insulating layer that exist at the boundary between the insulating region and the non-insulating region are both side surfaces of the second insulating layer that exist at the boundary between the insulating region and the non-insulating region. It exists in the said insulating region side rather than.
Preferably, the side surface of the first insulating layer is located closer to the insulating region than the side surface of the semiconductor layer.
Preferably, the distance h from the surface of the semiconductor substrate to the surface of the semiconductor layer and the distance d between the side surface of the semiconductor layer and the side surface of the second insulating layer satisfy d / h ≧ 0.75.
Embodiments of the present invention will be described below with reference to the drawings. Note that this embodiment does not limit the present invention. All drawings are schematic for ease of understanding. It is easy for those skilled in the art to conceive any combination of the following embodiments.
FIG. 1 is an enlarged cross-sectional view of a semiconductor device substrate illustrating a method of manufacturing a semiconductor device substrate according to a first embodiment of the present invention in the order of steps.
Referring to FIG. 1A, an insulating layer 22 that is electrically insulating is formed on the surface of a semiconductor substrate 12, and a semiconductor layer 32 that is insulated from the semiconductor substrate by the insulating layer 22 is formed. That is, the SOI structure is formed on the semiconductor substrate 12. A commercially available SOI substrate may be used.
A mask layer is formed on the semiconductor layer 32 and patterned. In the present embodiment, an oxide layer 35 is formed on the semiconductor layer 32, and a nitride layer 42 is formed on the oxide layer 35. That is, two mask layers 35 and 42 are formed. The oxide layer 35 reduces stress from the nitride film 42 to the semiconductor layer 32 and protects the semiconductor layer 32.
The semiconductor substrate 12 and the semiconductor layer 32 are, for example, silicon substrates, and the insulating layer 22 and the oxide layer 35 are, for example, silicon oxide films. The nitride film 42 is, for example, a silicon nitride film. In the present embodiment, the thickness of the insulating layer 22 is about 400 nm or about 200 nm, and the thickness of the semiconductor layer 32 is about 200 nm.
Next, the semiconductor layer 32 is etched according to the patterned mask layers 35 and 42. Thereby, a trench 54 penetrating into the insulating layer 22 is formed. The trench 54 has a surface portion of the insulating layer 22 exposed by etching of the semiconductor layer 32 as a bottom surface and a side portion of the semiconductor layer 32 exposed by etching of the semiconductor layer 32 as a side surface.
Referring to FIG. 1B, next, the semiconductor layer 32 is oxidized to form an oxide layer 37 on the side surface of the trench 54. Further, a protective layer 92 thinner than the thickness of the insulating layer 22 is deposited on the semiconductor substrate 12. In the present embodiment, the protective layer 92 is deposited by LPCVD (Low Pressure Chemical Vapor Deposition). The oxide layer 37 protects the semiconductor layer 32 from the protective layer 92. The protective layer 92 is indicated by a broken line in FIG. By etching this protective layer 92 anisotropically toward the surface of the semiconductor substrate 12, the side wall protection part 94 remains on the side surface of the trench 54. Thereby, the side wall protection part 94 covers the side surface of the trench 54. The protective layer 92 and the sidewall protective part 94 are made of, for example, a nitride material or an oxide material. In the present embodiment, the sidewall protection part 94 is made of a nitride material.
When the sidewall protection part 94 is made of an oxide material, it is etched at the same time as the insulating layer 22 is etched. However, by sufficiently reducing the film thickness t of the insulating layer 22, the surface of the semiconductor substrate 12 can be exposed without exposing the semiconductor layer 32.
Referring to FIG. 1C, the insulating layer 22 existing from the bottom surface of the trench 54 to the semiconductor substrate 12 is etched. In the present embodiment, the insulating layer 22 is etched in two stages, being divided into a trench side etching that etches a portion relatively close to the bottom surface of the trench 54 and a substrate side etching that etches a portion relatively close to the semiconductor substrate 12. The
First, trench side etching is performed. That is, the region of the insulating layer 22 exposed from the side wall protection part 94 is selectively etched anisotropically by RIE or the like. Thereby, the insulating layer 22 is etched to the position of the broken line shown in FIG. Since the insulating layer 22 remains on the semiconductor substrate 12, the semiconductor substrate 12 is not damaged by RIE plasma or the like.
Subsequently, the substrate side etching of the insulating layer 22 is performed. That is, NH 4 The insulating layer 22 is etched by wet etching using an F solution or the like until the semiconductor substrate 12 is exposed. Wet etching does not damage the semiconductor substrate 12 because the insulating layer 22 is chemically etched. Therefore, the semiconductor substrate 12 has relatively few crystal defects.
Since the insulating layer 22 has already been anisotropically etched up to the broken line in FIG. 1C, even if the remaining insulating layer 22 is isotropically etched by wet etching, the surface of the semiconductor substrate 10 is reached. The width of the insulating layer 22 that is side-etched in the lateral direction perpendicular to the direction in which it goes is smaller than in the prior art. The width of the insulating layer 22 to be side-etched depends on the distance from the broken line in FIG. 1C to the surface of the semiconductor substrate 12, that is, the remaining film thickness t of the insulating layer 22 remaining after the trench side etching. To do.
Therefore, even if the protective layer 92 is thinner than the insulating layer 22, it is possible to prevent the insulating layer 22 from being side-etched under the semiconductor layer 32 by adjusting the remaining film thickness t. Therefore, the semiconductor layer 32 is not exposed. The remaining film thickness t is smaller than the thickness t ′ from the side surface of the semiconductor layer 32 of the sidewall protective layer 94. For example, the remaining film thickness t is about 50 nm, and the thickness t ′ is about 100 nm.
Referring to FIG. 1D, a single crystal layer 52 is formed inside trench 54 by epitaxially growing a single crystal from the surface of semiconductor substrate 12. In the present embodiment, the single crystal layer 52 is formed by a selective epitaxial growth method. Since the surface of the semiconductor substrate 12 is exposed and the semiconductor layer 32 is not exposed, the single crystal grows from the semiconductor substrate 12 and does not grow from the semiconductor layer 32.
Here, in the semiconductor substrate 12, a region where the insulating layer 22 and the semiconductor layer 32 exist is defined as an insulating region 62, and a region where the insulating layer 22 and the semiconductor layer 32 do not exist and the single crystal layer 52 is formed. Is a non-insulating region 72. A region where the side wall protection part 94 is formed and a region where one of the insulating layer 22 or the semiconductor layer 32 remains and the other does not remain are defined as a boundary region 82. In each attached drawing, each of the insulating region 62, the non-insulating region 72, and the boundary region 82 is distinguished by a broken line.
Since the single crystal grows from the semiconductor substrate 12 and does not grow from the semiconductor layer 32, no bump is formed in the boundary region 82 or in the vicinity thereof. Accordingly, no crystal defects are generated on the surface of the single crystal layer 52 in the vicinity of the boundary region 82.
In this embodiment mode, mask layers 35 and 42 are removed in a later step, so that single crystal layer 52 is formed such that the surface of single crystal layer 52 and the surface of semiconductor layer 32 are flush with each other. . Thus, the substrate surface 98 of the semiconductor device substrate 100 after the mask layers 35 and 42 are removed becomes flat. In this way, the semiconductor device substrate 100 having the flat substrate surface 98 is formed.
Since the sidewall protection part 94 is made of a nitride material, the sidewall protection part 94 is also removed to the surface of the semiconductor layer 32 when the mask layers 35 and 42 are removed by ashing or the like. Accordingly, a flat substrate surface 98 is formed from the insulating region 62 through the boundary region 82 to the non-insulating region 72. In this way, the semiconductor device substrate 200 is formed.
Therefore, the semiconductor device substrate 100 includes an insulating region in which the semiconductor substrate 12 and the electrically insulating layer 22 and the semiconductor layer 32 insulated by the insulating layer 22 are formed on the surface of the semiconductor substrate 12. 62, a non-insulating region 72 having a single crystal layer 52 formed on the surface of the semiconductor substrate 12, and a side wall covering at least the side surface of the semiconductor layer 32 existing in the boundary region 82 between the insulating region 62 and the non-insulating region 72 And a protection unit 94.
The side surface of the insulating layer 22 present in the boundary region 82 between the insulating region 62 and the non-insulating region 72 is present closer to the non-insulating region 72 than the side surface of the semiconductor layer 32.
In the insulating region 62 and the non-insulating region 72 of the semiconductor device substrate 100, a semiconductor device suitable for each characteristic can be formed.
FIG. 2 is an enlarged cross-sectional view of a semiconductor device substrate illustrating a method of manufacturing a semiconductor device substrate according to a second embodiment of the present invention in the order of steps.
Referring to FIG. 2A, first, as in FIG. 1A, the insulating layer 22, the semiconductor layer 32, and the mask layers 35 and 42 are formed over the semiconductor substrate 12.
A portion of the semiconductor layer 32 and the insulating layer 22 is anisotropically etched by RIE according to the patterned mask layers 35 and 42. That is, the trench 54 is formed and the insulating layer 22 is etched on the trench side. Thereby, a trench 54 penetrating into the insulating layer 22 is formed. The trench 54 has a portion of the insulating layer 22 exposed by etching the semiconductor layer 32 as a bottom surface and a side portion of the semiconductor layer 32 and the insulating layer 22 exposed by etching of the semiconductor layer 32 as a side surface.
Referring to FIG. 2 (B), side wall protecting portion 94 is formed on the side surface of trench 54 as in the first embodiment. However, unlike the first embodiment, the side surface of the trench 54 is formed by the side portions of the semiconductor layer 32 and the insulating layer 22, so that the side wall protection portion 94 is not only the side portion of the semiconductor layer 32 but also the insulating layer 22. Cover the sides as well.
Referring to FIG. 2C, the insulating layer 22 remaining from the bottom surface of the trench 54 to the semiconductor substrate 12 is wet-etched. That is, in the present embodiment, the trench side etching of the insulating layer 22 is performed after the substrate side etching is performed and the side wall protection part 94 is formed.
During the trench side etching, a part of the insulating layer 22 on the trench 54 side has already been etched by the trench side etching. Accordingly, a portion of the insulating layer 22 remaining relatively close to the semiconductor substrate 12 is isotropically etched by substrate side etching. Thereby, even if the protective layer 92 (see FIG. 1B) is thinner than the insulating layer 22, the insulating layer 22 is not side-etched under the semiconductor layer 32 by adjusting the remaining film thickness t of the insulating layer 22. Can be.
In the present embodiment, the remaining film thickness t can be made smaller than the thickness t ′ of the sidewall protective layer 94 from the side surface of the semiconductor layer 32. That is, in the substrate-side etching, the semiconductor device substrate 200 has a margin in the horizontal direction by the difference between the remaining film thickness t and the thickness t ′. Therefore, the semiconductor layer 32 is not exposed after the substrate side etching.
In addition, the semiconductor device substrate 200 has a vertical margin corresponding to the thickness of the insulating layer 22 that has already been etched in the trench-side etching. Therefore, the semiconductor layer 32 is not exposed even if the etching further proceeds in the substrate side etching.
FIG. 2E is an enlarged view of a portion indicated by a broken-line circle Z when overetching is performed beyond the thickness t ′ of the sidewall protective layer 94 in the substrate side etching. According to FIG. 2E, the vertical margin is indicated by t ″. The thickness t ″ is equal to the thickness of the insulating layer 22 that has already been etched during the trench-side etching. Even when the substrate side etching is over-etched to the thickness t ′ or more of the sidewall protective layer 94, the semiconductor layer 32 is not exposed.
Therefore, in the present embodiment, the substrate-side etching can etch the insulating layer 22 by the thickness of the sum of t ′ and t ″. That is, when considering both the horizontal margin and the vertical margin, the total margin is the sum of t ′ and t ″.
In this embodiment, since the insulating layer 22 is wet etched until the semiconductor substrate 12 is exposed, crystal defects are unlikely to occur in the semiconductor substrate 12.
Referring to FIG. 2D, single crystal layer 52 is formed inside trench 54 by epitaxially growing single crystal layer 52 from the surface of semiconductor substrate 12.
Similar to the first embodiment, since the surface of the semiconductor substrate 12 is exposed and the semiconductor layer 32 is not exposed, the single crystal layer 52 is epitaxially grown from the semiconductor substrate 12 and is not grown from the semiconductor layer 32.
Therefore, no bump is formed in or near the boundary region 82. Accordingly, no crystal defects are generated on the surface of the single crystal layer 52 in the vicinity of the boundary region 82. In the present embodiment, since mask layers 35 and 42 are removed in a later step, single crystal layer 52 is formed so that the surface of single crystal layer 52 and the surface of semiconductor layer 32 are flush with each other. Is done. Thus, the substrate surface 98 of the semiconductor device substrate 100 after the mask layers 35 and 42 are removed becomes flat. In this way, the semiconductor device substrate 100 having the flat substrate surface 98 is formed.
The semiconductor device substrate 200 is formed such that, of the side surfaces of the insulating layer 22, the side surface near the semiconductor substrate 12 exists closer to the non-insulating region 72 than the side wall of the semiconductor layer 32.
In FIG. 2D, depending on the conditions for growing the single crystal layer 52, a space may be generated at the edge u at the boundary between the sidewall protection portion 94 and the insulating layer 22.
FIG. 3 is an enlarged cross-sectional view of a semiconductor device substrate illustrating a method of manufacturing a semiconductor device substrate according to a third embodiment of the present invention in the order of steps.
Referring to FIG. 3A, first, as in FIG. 1A, an insulating layer 22, a semiconductor layer 32, and mask layers 35 and 42 are formed over the semiconductor substrate 12.
Next, the semiconductor layer 32 is anisotropically etched by RIE according to the patterned mask layers 35 and 42. Thereby, a trench 54 penetrating into the insulating layer 22 is formed. The trench 54 has a surface portion of the insulating layer 22 exposed by etching of the semiconductor layer 32 as a bottom surface and a side portion of the semiconductor layer 32 exposed by etching of the semiconductor layer 32 as a side surface.
Further, a portion of the insulating layer 22 on the trench 54 side is wet etched. That is, the trench side etching of the insulating layer 22 is performed. Since the insulating layer 22 is isotropically etched by wet etching, the insulating layer 22 existing under the semiconductor layer 32 is perpendicular to the direction of the side surface of the trench 54, that is, the direction toward the surface of the semiconductor substrate 12. Etching in the horizontal direction. Thereby, the side and bottom of the semiconductor layer 32 are exposed.
Referring to FIG. 3B, a side wall protecting portion 94 is formed on the side surface of trench 54 as in the first embodiment. However, the sidewall protection part 94 is formed not only on the side part of the semiconductor layer 32 but also below the semiconductor layer 32 where the side-etched insulating layer 22 was present. Therefore, even if the protective layer 92 is deposited thinner than the insulating layer 22, the thickness t ′ from the side surface of the insulating layer 22 of the sidewall protective layer 94 is thicker than the remaining film thickness t of the insulating layer 22. Even after the semiconductor layer 32 is not exposed.
Referring to FIG. 3C, the insulating layer 22 existing from the bottom surface of the trench 54 to the semiconductor substrate 12 is wet-etched. That is, in the present embodiment, the substrate-side etching of the insulating layer 22 is performed after the trench-side etching is performed and the sidewall protection part 94 is formed.
Similar to the second embodiment, during the trench side etching, a part of the insulating layer 22 on the trench 54 side is already etched. Accordingly, in the substrate side etching, the portion of the insulating layer 22 remaining relatively close to the semiconductor substrate 12 is isotropically etched by the substrate side etching. Thereby, as described above, even if the protective layer 92 is deposited thinner than the insulating layer 22, the insulating layer 22 is moved to the bottom of the semiconductor layer 32 by adjusting the film thickness t of the remaining insulating layer 22. -It can be prevented from being etched. Therefore, the semiconductor layer 32 is not exposed. The remaining film thickness t is smaller than the thickness t ′ from the side surface of the insulating layer 22 of the sidewall protective layer 94.
Further, as in FIG. 2E, a vertical margin may be considered. Thereby, even if the insulating layer 22 is side-etched to a thickness t ′ or more in the substrate side etching, the semiconductor layer 32 is not exposed.
In general, it cannot be clearly specified how much the remaining thickness t of the insulating layer 22 can protect the semiconductor substrate 12 from damage caused by RIE plasma.
However, according to the present embodiment, both the trench side etching and the substrate side etching are isotropic etching. Therefore, since the insulating layer 22 is not etched by RIE, there is no possibility that the semiconductor substrate 12 is damaged through the insulating layer 22 by the trench side etching, and crystal defects in the semiconductor substrate 12 are further less likely to occur. .
Referring to FIG. 3D, single crystal layer 52 is formed inside trench 54 by epitaxially growing single crystal layer 52 from the surface of semiconductor substrate 12.
As in the first embodiment, since the surface of the semiconductor substrate 12 is exposed but the semiconductor layer 32 is not exposed, the single crystal layer 52 is epitaxially grown from the semiconductor substrate 12 and does not grow from the semiconductor layer 32. .
Therefore, no bump is formed in the boundary region 82 or in the vicinity thereof, and no crystal defect occurs.
In the present embodiment, since mask layers 35 and 42 are removed in a later step, single crystal layer 52 is formed so that the surface of single crystal layer 52 and the surface of semiconductor layer 32 are flush with each other. Is done. Thus, the substrate surface 98 of the semiconductor device substrate 100 after the mask layers 35 and 42 are removed becomes flat. In this way, the semiconductor device substrate 100 having the flat substrate surface 98 is formed.
Since the sidewall protection part 94 is made of a nitride material, the sidewall protection part 94 is also removed to the surface of the semiconductor layer 32 when the mask layers 35 and 42 are removed by ashing or the like. Accordingly, a flat substrate surface 98 is formed from the insulating region 62 through the boundary region 82 to the non-insulating region 72. Thus, the semiconductor device substrate 300 is formed.
In the semiconductor device substrate 300, the side surface in the vicinity of the semiconductor substrate 12 among the side surfaces of the insulating layer 22 exists on the non-insulating region side 72 relative to the side wall of the semiconductor layer 32. The side surface in the vicinity of the layer 32 exists on the insulating region side 82 from the side wall of the semiconductor layer 32.
FIG. 4 is an enlarged cross-sectional view of a semiconductor device substrate illustrating a method of manufacturing a semiconductor device substrate according to a fourth embodiment of the present invention in the order of steps.
First, as in FIG. 1A, the insulating layer 22, the semiconductor layer 32, and the mask layers 35 and 42 are formed over the semiconductor substrate 12.
Next, referring to FIG. 4A, the semiconductor layer 32 is isotropically etched in accordance with the patterned mask layers 35 and 42 to form a trench 54 penetrating into the insulating layer 22. Thereby, the semiconductor layer 32 existing under the mask layers 35 and 42 is side-etched in the direction of the side surface of the trench 54. That is, the semiconductor layer 32 is side-etched in the lateral direction perpendicular to the direction toward the surface of the semiconductor substrate 12.
Referring to FIG. 4B, side wall protecting portion 94 is formed on the side surface of trench 54 in the same manner as in the first embodiment. The side wall protection part 94 penetrates under the mask layers 35 and 42 and covers the side part of the semiconductor layer 32. Therefore, although the protective layer 92 (see FIG. 1B) deposited to form the side wall protection portion 94 is thinner than the insulating layer 22, the side wall protection from the side surface of the trench 54 is achieved. The thickness of the portion 94 in the horizontal direction is larger than the thickness of the insulating layer 22.
Referring to FIG. 4C, the insulating layer 22 existing from the bottom surface of the trench 54 to the semiconductor substrate 12 is wet-etched. In the present embodiment, unlike the first to third embodiments, the insulating layer 22 is etched by one wet etching. Since the lateral thickness t ′ of the sidewall protection part 94 from the side surface of the trench 54 is thicker than the film thickness t of the insulating layer 22, the semiconductor layer 32 is not exposed even if the insulating layer 22 is side-etched.
In this embodiment mode, the insulating layer 22 is not etched by the etching shown in FIG. However, as shown in FIG. 4E, part of the insulating layer 22 may be etched. As a result, the insulating layer 22 is side-etched to expose a part of the bottom surface of the semiconductor layer 32, and the side wall protection part 94 covers a part of the bottom surface of the semiconductor layer 32 in FIG. Thereby, the etching of the insulating layer 22 in FIG. 4C can be processed in consideration of not only the margin in the horizontal direction but also the margin in the vertical direction, as in the embodiment shown in FIG. That is, the semiconductor layer 32 can be designed not to be exposed even if the insulating layer 22 is side-etched to a thickness t ′ or more.
Referring to FIG. 4D, single crystal layer 52 is formed inside trench 54 by epitaxially growing single crystal layer 52 from the surface of semiconductor substrate 12.
Therefore, no bump is formed in or near the boundary region 82. Accordingly, no crystal defects are generated on the surface of the single crystal layer 52 in the vicinity of the boundary region 82.
Since the sidewall protection part 94 is made of a nitride material, when the mask layers 35 and 42 are removed by ashing or the like, the sidewall protection part 94 is also removed to the surface of the semiconductor layer 32. Accordingly, a flat substrate surface 98 is formed from the insulating region 62 through the boundary region 82 to the non-insulating region 72. In this way, the semiconductor device substrate 400 is formed.
The semiconductor device substrate 400 is a mask in which the side surface of the semiconductor layer 12 and the side surface of the insulating layer 22 existing at the boundary between the insulating region 62 and the non-insulating region 72 are both present at the boundary between the insulating region 62 and the non-insulating region 72. It exists on the insulating region 62 side with respect to the side surfaces of the layers 35 and 42.
FIG. 5 is an enlarged cross-sectional view of a semiconductor device substrate illustrating a method of manufacturing a semiconductor device substrate according to a fifth embodiment of the present invention in the order of steps.
FIG. 5A shows a state similar to that in FIG. Therefore, the semiconductor layer 32 existing under the mask layers 35 and 42 is side-etched in the direction of the side surface of the trench 54.
FIG. 5B shows a state after the insulating layer 22 is etched. In the present embodiment, unlike the other embodiments, the side wall protection portion is not formed. Further, since the insulating layer 22 is wet-etched, it is side-etched in the lateral direction perpendicular to the direction toward the surface of the semiconductor substrate 12.
In the present embodiment, both the semiconductor layer 32 and the insulating layer 22 are wet etched. Therefore, the side surface of the semiconductor layer 12 and the side surface of the insulating layer 22 are both located closer to the insulating region 62 than the side surfaces of the mask layers 35 and 42 existing at the boundary between the insulating region 62 and the non-insulating region 72. The insulating layer 22 is wet etched after the semiconductor layer 32. Therefore, the side surface of the insulating layer 22 exists closer to the insulating region 62 than the side surface of the semiconductor layer 32. Therefore, the mask layers 35 and 42, the semiconductor layer 32, and the insulating layer 22 are formed in a reverse step shape.
Further, the distance h from the surface of the semiconductor substrate 12 to the surface of the semiconductor layer 32 and the distance d between the side surface of the semiconductor layer 32 and the side surface of the mask layer 35 or 42 satisfy d / h ≧ 0.75. The reason is described below.
Referring to FIG. 5D, a single crystal layer 52 is formed inside trench 54 by epitaxially growing a single crystal from the surface of semiconductor substrate 12 and the side surface of semiconductor layer 32.
In general, when silicon is epitaxially grown, the growth rate of silicon crystal growing in the direction X perpendicular to the crystal plane (100) of the silicon substrate and the direction Y perpendicular to the crystal plane (010) of the silicon substrate The ratio to the growth rate of the growing silicon crystal is 1: 0.75.
In the present embodiment, the surface of the semiconductor substrate 12 corresponds to the crystal plane (100), and the side surface of the semiconductor layer 32 corresponds to the crystal plane (010).
Crystals also grow from the side surfaces of the semiconductor layer 32, but crystals from the side surfaces of the semiconductor layer 32 are prevented from growing beyond the surface of the semiconductor layer 32 to the outside of the trench 54 by the mask layer 35. In order for the crystal from the semiconductor layer 32 to grow beyond the surface of the semiconductor layer 32, the crystal from the side surface of the semiconductor layer 32 must grow in the lateral direction, that is, in the direction Y, by a distance d or more.
On the other hand, the crystal grown from the surface of the semiconductor substrate 12 is 1 / 0.75 = 1.33 times faster than the rate at which the crystal grows in the direction X.
Therefore, in the present embodiment, when the distance h and the distance d satisfy d / h ≧ 0.75, before the crystal grown from the semiconductor layer 32 grows beyond the surface of the semiconductor layer 32, the semiconductor substrate 12 Crystals growing from the surface exceed the surface of the semiconductor layer 32. Accordingly, bumps are not generated on the surface of the single crystal layer 52 formed in the non-insulating region 72, and no crystal defects are generated.
In the present embodiment, the mask layers 35 and 42 are removed in a later step.
The single crystal layer 52 is formed so that the surface of the single crystal layer 52 and the surface of the semiconductor layer 32 are in the same plane. Thus, the substrate surface 98 of the semiconductor device substrate 100 after the mask layers 35 and 42 are removed becomes flat. In this way, the semiconductor device substrate 100 having the flat substrate surface 98 is formed. Accordingly, a flat substrate surface 98 is formed from the insulating region 62 through the boundary region 82 to the non-insulating region 72.
Therefore, according to the present embodiment, a flat semiconductor device substrate 500 with few crystal defects can be formed without providing the sidewall protective layer 92.
Although the embodiments according to the present invention have been described above, in these embodiments, the shape and material of the side wall protection part 94 and the film thickness or the remaining film thickness t of the insulating layer 22 are determined by the deposition process and etching. It can be changed arbitrarily by adjusting the process. Accordingly, it is easy for those skilled in the art to prevent the semiconductor layer 32 from being exposed after the insulating layer 22 is etched on the substrate side, and such an embodiment has all the effects of the present invention. Belongs to the range.
According to the method for manufacturing a substrate for a semiconductor device according to the present invention, a flat surface having few defects in a surface crystal and no step between a region having an SOI structure and a region having no SOI structure. A substrate for a semiconductor device is provided.
The substrate for a semiconductor device according to the present invention has a flat surface with few defects in the surface crystal and no step between the region having the SOI structure and the region not having the SOI structure.
FIG. 1 is an enlarged cross-sectional view of a semiconductor device substrate illustrating a method of manufacturing a semiconductor device substrate according to a first embodiment of the present invention in the order of steps;
FIG. 2 is an enlarged cross-sectional view of a semiconductor device substrate illustrating a method of manufacturing a semiconductor device substrate according to a second embodiment of the present invention in the order of steps;
FIG. 3 is an enlarged cross-sectional view of a semiconductor device substrate illustrating a method of manufacturing a semiconductor device substrate according to a third embodiment of the present invention in the order of steps;
FIG. 4 is an enlarged cross-sectional view of a semiconductor device substrate showing a method of manufacturing a semiconductor device substrate according to a fourth embodiment of the present invention in the order of steps;
FIG. 5 is an enlarged cross-sectional view of a semiconductor device substrate showing a method of manufacturing a semiconductor device substrate according to a fifth embodiment of the present invention in the order of steps;
FIG. 6 is an enlarged cross-sectional view of a partial SOI substrate having an SOI region and a non-SOI region obtained by wet-etching the BOX layer 20 according to a conventional method.
10, 12 Semiconductor substrate
20, 22 Insulating layer
30, 32 Semiconductor layer
35, 40, 42 Mask layer
50, 52 single crystal layer
54 Trench
62 Insulation area
72 Non-insulated region
82 Boundary area
92 Protective layer
100, 200, 300, 400, 500 Semiconductor device substrate
A mask layer forming step of forming a patterned mask layer on the semiconductor layer insulated from the semiconductor substrate by an electrically insulating insulating layer;
A trench forming step of etching at least the semiconductor layer according to a pattern of the mask layer to form a trench penetrating the insulating layer;
A protective part forming step of forming a side wall protective part that covers a side surface of the trench by etching a protective layer deposited on the semiconductor substrate thinner than a thickness of the insulating layer;
An etching step of etching the insulating layer from a bottom surface of the trench to the semiconductor substrate;
A single crystal layer forming step of growing a single crystal layer from the surface of the semiconductor substrate exposed by etching the insulating layer ;
In the etching step, the insulating layer from the bottom surface of the trench to the semiconductor substrate is etched on at least a portion relatively close to the bottom surface of the trench and a substrate on which a portion relatively close to the semiconductor substrate is etched. A two-stage etching step that etches separately into side etching,
The method for manufacturing a substrate for a semiconductor device, wherein the protection portion forming step is performed before the trench side etching or before the substrate side etching .
The trench side etching is anisotropic etching,
2. The method for manufacturing a substrate for a semiconductor device according to claim 1 , wherein the substrate side etching is isotropic etching.
The etching in the trench side etching and the substrate side etching are both isotropic etching, and in the trench side etching, the insulating layer present under the semiconductor layer is etched in the direction of the side surface of the trench,
The protective part forming step is performed after the trench side etching and before the substrate side etching, and the side wall protective part includes the side surface of the trench and the insulating layer etched by the trench side etching. The method for manufacturing a substrate for a semiconductor device according to claim 1 , wherein the method is formed below the semiconductor layer.
The isotropic etching is a wet etching performed in a liquid phase,
Claim 2 or method of manufacturing a substrate for a semiconductor device according to claim 3, characterized in that etching of the anisotropic is dry etching performed in the gas phase.
In the trench forming step, the etching of the semiconductor layer is isotropic etching, and the semiconductor layer present under the mask layer is etched in the direction of the side surface of the trench,
In the protective part forming step, the sidewall protective part is formed below the semiconductor layer where the semiconductor layer etched by the trench forming step was present,
The method of manufacturing a substrate for a semiconductor device according to claim 1, wherein the etching in the etching step is isotropic etching.
At least the semiconductor layer is isotropically etched according to the pattern of the mask layer, and the semiconductor layer existing under the mask layer is etched toward the side surface of the trench to form a trench penetrating the insulating layer. A trench forming step;
An etching step of isotropically etching the insulating layer from the bottom surface of the trench to the semiconductor substrate to etch the insulating layer present under the semiconductor layer in a direction toward the side surface of the trench;
A single crystal layer forming step of growing a single crystal layer from the surface of the semiconductor substrate exposed by etching the insulating layer;
A method for manufacturing a substrate for a semiconductor device comprising:
The method of manufacturing a substrate for a semiconductor device according to claim 6 , wherein the isotropic etching is wet etching performed in a liquid phase.
An insulating region in which an electrically insulating insulating layer and a semiconductor layer insulated by the insulating layer are formed on the surface;
A non-insulating region having a single crystal layer formed on the surface;
A side wall protecting portion covering at least a side surface of the semiconductor layer present in a boundary region between the insulating region and the non-insulating region;
The side surface of the insulating layer present in the boundary region between the insulating region and the non-insulating region exists on the non-insulating region side of the side surface of the semiconductor layer ,
A substrate for a semiconductor device, wherein, of the side surfaces of the insulating layer, a side surface in the vicinity of the semiconductor substrate is located closer to the non-insulating region than a side wall of the semiconductor layer .
9. The substrate for a semiconductor device according to claim 8 , wherein a thickness of the side wall protection part on a side surface of the semiconductor layer is larger than a thickness of the insulating layer on the semiconductor substrate.
9. The substrate for a semiconductor device according to claim 8 , wherein, of the side surfaces of the insulating layer, a side surface in the vicinity of the semiconductor layer is located closer to the insulating region than a side wall of the semiconductor layer.
A first insulating layer that is electrically insulative and a semiconductor layer insulated by the first insulating layer are formed on the surface, and a second insulating layer is formed on the semiconductor layer. An insulating region;
A non-insulating region having a single crystal layer formed on the surface,
The side surface of the semiconductor layer and the side surface of the first insulating layer existing at the boundary between the insulating region and the non-insulating region are both the second insulating layer existing at the boundary between the insulating region and the non-insulating region. A substrate for a semiconductor device, wherein the substrate is present on a side closer to the insulating region than a side surface of the layer.
The substrate for a semiconductor device according to claim 11 , wherein a side surface of the first insulating layer is present on a side closer to the insulating region than a side surface of the semiconductor layer.
The distance h from the surface of the semiconductor substrate to the surface of the semiconductor layer and the distance d between the side surface of the semiconductor layer and the side surface of the second insulating layer are:
The substrate for a semiconductor device according to claim 12 , wherein d / h ≧ 0.75 is satisfied.
JP2001293781A 2001-09-26 2001-09-26 Method for manufacturing substrate for semiconductor device and substrate for semiconductor device Expired - Fee Related JP3984014B2 (en)
JP2001293781A JP3984014B2 (en) 2001-09-26 2001-09-26 Method for manufacturing substrate for semiconductor device and substrate for semiconductor device
US10/237,206 US7187035B2 (en) 2001-09-26 2002-09-09 Semiconductor device comprising multiple layers with trenches formed on a semiconductor substrate
KR20020058106A KR100488379B1 (en) 2001-09-26 2002-09-25 Substrate for semiconductor device and method of fabricating the same
CN 02143261 CN1229853C (en) 2001-09-26 2002-09-25 Substrate producing method for semiconductor device and substrate for semiconductor device
TW91122016A TW557507B (en) 2001-09-26 2002-09-25 Method of manufacturing substrate of semiconductor device and substrate of semiconductor device
US11/455,735 US7521300B2 (en) 2001-09-26 2006-06-20 Semiconductor device substrate including a single-crystalline layer and method of manufacturing semiconductor device substrate
JP2003100641A JP2003100641A (en) 2003-04-04
JP3984014B2 true JP3984014B2 (en) 2007-09-26
ID=19115500
JP2001293781A Expired - Fee Related JP3984014B2 (en) 2001-09-26 2001-09-26 Method for manufacturing substrate for semiconductor device and substrate for semiconductor device
US (2) US7187035B2 (en)
JP (1) JP3984014B2 (en)
KR (1) KR100488379B1 (en)
CN (1) CN1229853C (en)
TW (1) TW557507B (en)
WO2008126891A1 (en) * 2007-04-11 2008-10-23 Ulvac, Inc. Dry etching method
US7750430B2 (en) 2007-10-31 2010-07-06 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
2001-09-26 JP JP2001293781A patent/JP3984014B2/en not_active Expired - Fee Related
2002-09-09 US US10/237,206 patent/US7187035B2/en active Active
2002-09-25 KR KR20020058106A patent/KR100488379B1/en not_active IP Right Cessation
2002-09-25 TW TW91122016A patent/TW557507B/en not_active IP Right Cessation
2002-09-25 CN CN 02143261 patent/CN1229853C/en not_active IP Right Cessation
2006-06-20 US US11/455,735 patent/US7521300B2/en not_active Expired - Fee Related
CN1411033A (en) 2003-04-16
KR20030027723A (en) 2003-04-07
US20030057490A1 (en) 2003-03-27
US20060234478A1 (en) 2006-10-19
JP2003100641A (en) 2003-04-04
US7187035B2 (en) 2007-03-06
KR100488379B1 (en) 2005-05-11
TW557507B (en) 2003-10-11
US7521300B2 (en) 2009-04-21
CN1229853C (en) 2005-11-30
US6404014B1 (en) 2002-06-11 Planar and densely patterned silicon-on-insulator structure