Source: http://www.google.com/patents/US7235435?dq=inventor:%22Arthur+R.+Hair%22&ei=VAy0Tsa4NYTl0QGQiqWiBA
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Patent US7235435 - Method for fabricating thin film transistor with multiple gates using metal ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA thin film transistor with multiple gates using an MILC process which is capable of materializing multiple gates without increasing dimensions and a method thereof. The thin film transistor has a semiconductor layer which is formed on a insulating substrate in a zigzag shape; and a gate electrode which...http://www.google.com/patents/US7235435?utm_source=gb-gplus-sharePatent US7235435 - Method for fabricating thin film transistor with multiple gates using metal induced lateral crystallizationAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7235435 B2Publication typeGrantApplication numberUS 11/011,584Publication dateJun 26, 2007Filing dateDec 15, 2004Priority dateDec 19, 2001Fee statusPaidAlso published asCN1207792C, CN1431718A, EP1326282A2, EP1326282A3, US6815267, US7001802, US7112475, US7208352, US7235434, US7294537, US7381990, US20030113957, US20040253772, US20050093065, US20050095753, US20050158920, US20050158928, US20050191798, US20050191799Publication number011584, 11011584, US 7235435 B2, US 7235435B2, US-B2-7235435, US7235435 B2, US7235435B2InventorsWoo-Young SoOriginal AssigneeSamsung Sdi Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (52), Non-Patent Citations (7), Classifications (38), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod for fabricating thin film transistor with multiple gates using metal induced lateral crystallization
Referring to FIG. 1A and FIG. 2A, a buffer layer 11 is formed on a insulating substrate 10 such as a glass substrate, and an amorphous silicon film is patterned using a first mask (which is not shown in the drawings) after depositing an amorphous silicon film on the buffer layer 11 so that a semiconductor layer 12 a having an amorphous silicon film is formed, wherein the semiconductor layer 12 a comprising an amorphous silicon film has a “c” shaped structure equipped with body parts 12L1 and 12L2 and a connection part 12B connecting the body parts 12L1 and 12L2.
Although several embodiments of the present invention exemplify that the semiconductor layer 12 a has a “c” shaped structure equipped with a pair of body parts 12L1 and 12L2 and a connection part 12B connecting the body parts 12L1 and 12L2, the semiconductor layer 12 a is not necessarily limited to such a structure, but can have a “E” or “z” shaped structure, or a combination thereof equipped with a plurality of body parts 12L, wherein each of the plurality of body parts 12L are connected by a plurality of connection parts 12B so that the semiconductor layer 12 a has a zigzag shaped structure.
On the other hand, the gate electrode 16 has a structure of multiple gates since parts overlapping each of the body parts 12L act as a gate where the semiconductor layer 12 a is not formed in a “c” shape, but formed in a zigzag shape equipped with a plurality of body parts 12L.
Impurity areas 12-11–12-13 for source/drain regions are formed by ion-implanting impurities, for example, N-type or P-type impurities into the semiconductor layer 12 a comprising an amorphous silicon film after forming the gate electrode 16.
Each of impurity areas 39 a–39 d for source/drain regions are formed by ion-implanting high concentrated impurities of P-type or N-type into the first semiconductor layer 40 a and the second semiconductor layer 40 b using the gate electrode 37 as a mask, wherein a part overlapped by the first gate 37-1 in the first semiconductor layer 40 a acts as a first channel region while a part overlapped by the second gate 37-2 in the second semiconductor layer 40 b acts as a second channel region.
Referring to FIG. 5A and FIG. 6A, a buffer layer 51 is formed on an insulating substrate 50 such as a glass substrate, and an amorphous silicon film is deposited on the buffer layer 51. A semiconductor layer 52 a comprising an amorphous silicon film is formed by patterning the amorphous silicon film using a first mask (which is not shown in the drawings). The semiconductor layer 52 a comprising an amorphous silicon film has a “c” shaped structure equipped with body parts 52L1 and 52L2 and a connection part 52B to connect the body parts 52L1 and 52L2.
Although a “c” shaped structure is illustrated in the drawings in which the semiconductor layer 52 a is equipped with a pair of body parts 52L1 and 52L2 and a connection part 52B to connect the body parts 52L1 and 52L2, the semiconductor layer 52 a is not limited to the body parts 52L1 and 52L2 and the connection part 52B, but can be equipped with a plurality of body parts 52L, wherein the plurality of body parts 52L are connected by a plurality of connection parts 52B respectively so that the semiconductor layer 52 a has a zigzag shaped structure.
Subsequently, a “c” shaped semiconductor layer 82 is formed by patterning the polycrystalline silicon film 82 b using a mask for the semiconductor layer after removing the metal film 83, as illustrated in FIG. 8C. This embodiment can be applied to a thin film transistor having the same structure as in the embodiment of FIGS. 1A to 1D so that an MILC surface 82 c exists outside channel regions. Thereafter, a thin film transistor with multiple gates is fabricated by the same method as in the embodiment of FIGS. 1A to 1D.
Subsequently, a “c” shaped semiconductor layer 92 is formed by patterning the polycrystalline silicon film 92 b using a mask for the semiconductor layer after removing the metal film 93, as illustrated in FIG. 9C. This embodiment can be applied to a thin film transistor having the same structure as in the embodiment of FIG. 7 so that an MILC surface 92 c exists outside channel regions during formation of multiple gates. Thereafter, a thin film transistor with multiple gates is fabricated in the same method as in the previous embodiment.
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No. 11/105,382, filed Apr. 14, 2005, So, Samsung SDI Co., Ltd.Classifications U.S. Classification438/150, 438/166, 438/151, 438/168, 257/E29.275, 257/E27.111, 257/E21.412, 438/187, 257/E29.137, 257/E29.28International ClassificationH01L21/20, H01L29/786, H01L21/336, H01L27/12, H01L29/423, H01L21/77, H01L21/00, H01L21/84Cooperative ClassificationH01L21/02488, H01L29/6675, H01L29/78696, H01L29/78609, H01L27/1277, H01L21/02422, H01L29/42384, H01L21/02672, H01L29/78645, H01L21/02532, H01L27/12European ClassificationH01L29/66M6T6F15A, H01L21/02K4C1A3, H01L21/02K4A1K, H01L21/02K4B1J, H01L21/02K4T8C3, H01L29/423D2B8, H01L29/786B2, H01L29/786D, H01L29/786SLegal EventsDateCodeEventDescriptionDec 12, 2008ASAssignmentOwner name: SAMSUNG MOBILE DISPLAY CO., LTD., KOREA, REPUBLICFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SAMSUNG SDI CO., LTD.;REEL/FRAME:022010/0001Effective date: 20081209Owner name: SAMSUNG MOBILE DISPLAY CO., LTD.,KOREA, REPUBLIC OFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SAMSUNG SDI CO., LTD.;REEL/FRAME:022010/0001Effective date: 20081209Nov 24, 2010FPAYFee paymentYear of fee payment: 4Aug 29, 2012ASAssignmentOwner name: SAMSUNG DISPLAY CO., LTD., KOREA, REPUBLIC OFFree format text: MERGER;ASSIGNOR:SAMSUNG MOBILE DISPLAY CO., LTD.;REEL/FRAME:028868/0326Effective date: 20120702Dec 29, 2014FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services