Source: http://www.google.com/patents/US8005105?dq=US+6,313,853
Timestamp: 2015-02-27 22:18:07
Document Index: 626164777

Matched Legal Cases: ['Application No. 05798761', 'Application No. 200580032948', 'Application No. 200580032948', 'Application No. 200580032948', 'Application No. 200580032888', 'Application No. 200580032947', 'Application No. 200580032947']

Patent US8005105 - Method and system for configuring fibre channel ports - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA fiber channel switch element for routing fiber channel frame is provided. The switch element includes a fiber channel port that can be configured to support plural data transfer rates. The data transfer rate may be 1 G, 2 G, 4 G, 8 G or 10 G. The switch element includes a clock configuration module...http://www.google.com/patents/US8005105?utm_source=gb-gplus-sharePatent US8005105 - Method and system for configuring fibre channel portsAdvanced Patent SearchPublication numberUS8005105 B2Publication typeGrantApplication numberUS 12/473,150Publication dateAug 23, 2011Filing dateMay 27, 2009Priority dateJul 21, 2003Also published asUS7558281, US20050018650, US20090290584Publication number12473150, 473150, US 8005105 B2, US 8005105B2, US-B2-8005105, US8005105 B2, US8005105B2InventorsFrank R. Dropps, Gary M. Papenfuss, Ernest G. KohlweyOriginal AssigneeQlogic, CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (32), Non-Patent Citations (41), Classifications (15), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for configuring fibre channel ports
US 8005105 B2Abstract
1. A switch element for routing information, comprising:
wherein a clock rate for one data transfer rate is not an integer multiple of a clock rate for another data transfer rate at which the same port is configured to operate;
wherein the same port uses one interface to support one or more lanes for receiving and transferring information at the plurality of data transfer rates; and the one interface includes a plurality of selectable serial/de-serializer (SERDES), where a higher number of SERDES and a higher number of lanes are selected for a first data transfer rate, and a lower number of SERDES and a lower number of lanes are selected for supporting a second data transfer rate, where the first data transfer rate is higher than the second data transfer rate.
2. The element of claim 1, wherein the one data transfer rate is 1 G (gigabit per second).
6. The switch element of claim 1, wherein the one data transfer rate is equal to or greater 10 G (gigabit per second).
7. The switch element of claim 1, wherein the switch element includes a clock configuration module for providing a clock signal that is based on a configured data transfer rate for the same port.
8. The switch element of claim 1, wherein when a source port is operating at a lower data transfer rate than a destination port, a receive segment of the port sends a signal to a transmit segment to avoid an under flow condition.
9. The switch element of claim 8, wherein the receive segment waits for a certain frame length after a frame is written and before the frame is read for transmission, where the certain frame length depends upon a data transfer rate of the source port and the destination port.
10. The switch element of claim 1, wherein multiple lanes are configured for the port to operate as a single 10 G multi lane port and the same port uses the multiple lanes for the same port to operate as a different port at a rate lower than 10 G.
11. he switch element of claim 1, wherein same transmit and receive pipelines are used by the same port configured to operate at different speeds.
12. The switch element of claim 1, wherein transmit and receive pipelines are selected from a plurality of receive pipelines and transmit pipelines, depending upon a data transfer rate at which the port is configured to operate.
13. The switch element of claim 1, wherein a receive buffer for the port is shared by multiple lanes, when the port is configured to operate at different rates.
14. The switch element of claim 1, wherein a separate receive buffer is used for each of the plurality of lanes when the same port is configured to operate at different rates.
15. The switch element of claim 1, wherein each of the plurality of lanes is configured to operate at a different rate depending on the configuration of the port.
16. The switch element of claim 1, wherein the port auto-negotiates with other ports, the rate at which the configurable port is operating.
20. The switch element of claim 17, wherein the port auto-negotiates the rate at which it is operating with other ports. Description
This application is a continuation of U.S. application Ser. No. 10/894,917, filed Jul. 20, 2004, now U.S. Pat. No. 7,558,281, the '917 application claims priority under 35 U.S.C. �119(e)(1) to the following provisional patent applications:
Fibre channel links/ports can operate (i.e. receive and/or transmit data) in different speeds, for example, 1 gigabit per second (�G�), 2 G, 4 G, 8 G and now 10 G. 10 G ports can be implemented using a single link supporting a serial stream of 10.5 G serial data stream or by four physical lanes of 3.1875 G serial data stream where each lane carries 1 byte of a 4-byte transmitted word.
The base clock rate for 10 G ports is not an even multiple of 1 G/2 G/4 G/8 G rate, which means that conventional 100 ports cannot easily be scaled down to operate at 1 G/2 G/4 G/8 G. Although 10 G as a standard is gaining popularity, there are many legacy devices that still operate and will continue to operate at lower data rates (1 G/2 G/4 G/8 G).
TSM 346 chooses the data to be sent to the link transmitter, and enforces all fibre Channel rules for transmission. TSM 346 receives requests to transmit from loop state machine 320, IBUF 70A (shown as TARB request 346A) and from various other IOP 66 functions via control registers 326 (shown as IBUF Request 345A). TSM 346 also handles all credit management functions, so that Fibre Channel connectionless frames are transmitted only when there is link credit to do so.
XC_Port
Also on the transmit side, modules 340-343 are used for each lane 344A-344D, i.e., each lane can have its own module 340-343. Parity module 340 checks for parity errors and encode module 341 encodes 8-bit data to 10 bit data. Mux 342 sends the 10-bit data to a smoothing FIFO (�TxSMF�) module 342B that handles clock variation on the transmit side. SERDES 343 then sends the data out to the link.
In FIG. 6, TPORT 312A can be configured as a 1 G or 1 G/2 G/4 G/8 G port. If the port operates at 10 G, then all lanes 344A-344D are used to transmit frames. At a lower rate, fewer lanes may be used, for example; only lane 344A may be used for 1 G/2 G/4 G/8 G rate.
Module 201 also generates SERDES (for example, 302A) configuration signal 201A and phased locked loop (�PLL�) 202 configuration signal 201B. An external oscillator (not shown) (which may operate at 106.25 MHz) feeds into PLL 204 that generates an output 204A for SERDES 68 (or 302, 302A-302D). Signal 202A is also sent to PLL 203 that generates FCLK 209 and FCLK10 G 210.
For a 10 G port (XG_PORT), the receive pipe operates at RCLK 206 (at 1 G/2 G/4 G/8 G) or RCLK10 G 206A (at 10 G). The transmit pipe area operates in the FCLK10 G 207A clock domain. The output from a 10 G transmit pipe (for example, 802) is fed into SERDES 343. When an XG_PORT is configured as 1 G/2 G/4 G/8 G port, then the 1 G/2 G/4 G/8 G transmit pipe regions (for example, 803) operate at FCLK10 G, as shown in FIG. 2 and the transmit port output is sent to SERDES 343 as 10-bit data (instead of 40-bit for 10 G (10 bit per lane).
Crossbar 50 operates at 10 G in FCLK10 G clock domain 210.
Two 1 G source ports sending data to a single 2 G destination results in the destination having a bandwidth of 200 MB/S, four 1 G source ports sending data to a single 4 G destination results in a bandwidth of 400 MB/S, eight 1 G source ports sending data to a single 8 G destination results in a bandwidth of 800 MB/s. Twelve 1 G source ports sending data to a single 10G destination results in a bandwidth of 1200 MB/s. Two 2 G source ports sending data to a single 4 G destination results in a maximum bandwidth of 400 MB/s.
Between SERDES 302 and the write side of SMF 305, all components operate at the recovered clock 202A (for example, 106.25 MHz for 1 G, 212.5 MHz for 2 G, 425 MHz for 4 G and 850 MHz for 8 G. It is noteworthy that the data width may be doubled to reduce the recovered clock frequency in half.). Between the read side of SMF 305 and the write side of RBUF 69A, all modules operate at the rate specified by the Tx_Rate bit, described above.
To avoid underflow, RBUF 69A reads and transfers data when the rate for the read address is less then the rate for the write address.
When a source port operates at 2G and the destination port operates at 4 G, RBUF 69A read operation waits until ⅚th maximum length frame. If a source port operates at 10 G and the destination port operates at 10 G, then RBUF 69A waits for �th maximum length frame to avoid under flow.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5638518Oct 24, 1994Jun 10, 1997Lsi Logic CorporationNode loop core for implementing transmission protocol in fibre channelUS5687387Mar 24, 1995Nov 11, 1997Packard Bell NecEnhanced active port replicator having expansion and upgrade capabilitiesUS5751710Jun 11, 1996May 12, 1998Cisco Technology, Inc.Technique for connecting cards of a distributed network switchUS6148421May 29, 1998Nov 14, 2000Crossroads Systems, Inc.Error detection and recovery for sequential access devices in a fibre channel protocolUS6311204 *Oct 11, 1996Oct 30, 2001C-Cube Semiconductor Ii Inc.Processing system with register-based process sharingUS6339813Jan 7, 2000Jan 15, 2002International Business Machines CorporationMemory system for permitting simultaneous processor access to a cache line and sub-cache line sectors fill and writeback to a system memoryUS6625157May 20, 1999Sep 23, 2003Advanced Micro Devices, Inc.Apparatus and method in a network switch port for transferring data between buffer memory and transmit and receive state machines according to a prescribed interface protocolUS6700877Jul 23, 1998Mar 2, 2004Siemens AktiengesellschaftMethod and bus system for automatic address allocationUS6983342Oct 8, 2002Jan 3, 2006Lsi Logic CorporationHigh speed OC-768 configurable link layer chipUS7239641Aug 13, 2001Jul 3, 2007Brocade Communications Systems, Inc.Quality of service using virtual channel translationUS7275103Dec 18, 2002Sep 25, 2007Veritas Operating CorporationStorage path optimization for SANsUS7310389Mar 14, 2002Dec 18, 2007Syntle Sys Research, IncMethod and apparatus for determining the errors of a multi-valued data signal that are outside the limits of an eye maskUS7319669Nov 22, 2002Jan 15, 2008Qlogic, CorporationMethod and system for controlling packet flow in networksUS7334046Aug 5, 2002Feb 19, 2008Qlogic, CorporationSystem and method for optimizing frame routing in a networkUS7352701Sep 19, 2003Apr 1, 2008Qlogic, CorporationBuffer to buffer credit recovery for in-line fibre channel credit extension devicesUS7362702Oct 29, 2002Apr 22, 2008Qlogic, CorporationRouter with routing processors and methods for virtualizationUS7406092Jul 20, 2004Jul 29, 2008Qlogic, CorporationProgrammable pseudo virtual lanes for fibre channel systemsUS7424533May 23, 2003Sep 9, 2008Cisco Technology, Inc.Method and apparatus for role-based access controlUS7447224Jul 20, 2004Nov 4, 2008Qlogic, CorporationMethod and system for routing fibre channel framesUS7492780Feb 25, 2005Feb 17, 2009Xilinx, Inc.Method and apparatus for detecting timeout for packets transmitted in a packet-switched point-to-point communication architectureUS20020067726Sep 27, 2001Jun 6, 2002Engines Incorporated PursuantContent-based forwarding/filtering in a network switching deviceUS20020124102Mar 1, 2001Sep 5, 2002International Business Machines CorporationNon-zero credit management to avoid message lossUS20030037159Aug 6, 2001Feb 20, 2003Yongdong ZhaoTimer rollover handling mechanism for traffic policingUS20030095549Nov 5, 2002May 22, 2003Vixel CorporationMethods and apparatus for fibre channel interconnection of private loop devicesUS20030120791 *Dec 20, 2001Jun 26, 2003Weber David M.Multi-thread, multi-speed, multi-mode interconnect protocol controllerUS20030152076Sep 19, 2002Aug 14, 2003Barry LeeVertical instruction and data processing in a network processor architectureUS20030179748Dec 5, 2002Sep 25, 2003George William R.Hardware-enforced loop-level hard zoning for fibre channel switch fabricUS20030191883Apr 5, 2002Oct 9, 2003Sycamore Networks, Inc.Interface for upgrading serial backplane application from ethernet to gigabit ethernetUS20040027989Jan 21, 2003Feb 12, 2004Brocade Communications Systems, Inc.Cascade credit sharing for fibre channel linksUS20040088444 *Oct 29, 2003May 6, 2004Broadcom CorporationMulti-rate, multi-port, gigabit serdes transceiverUS20040153863Sep 12, 2003Aug 5, 2004Finisar CorporationNetwork analysis omniscent loop state machineUS20050099970Nov 6, 2003May 12, 2005Halliday David J.Method and apparatus for mapping TDM payload data* Cited by examinerNon-Patent CitationsReference1"Communication Under Rule 71(3) EPC indicating allowance of application dated Apr. 9, 2010 from European Patent Office for European Application No. 05798761.2".2"Final Office Action from USPTO dated Aug. 16, 2010 for U.S. Appl. No. 10/956,501".3"Final Office Action from USPTO dated Feb. 12, 2010 for U.S. Appl. No. 10/894,732".4"Final Office Action from USPTO dated Mar. 4, 2010 for U.S. Appl. No. 10/957,465".5"Final Office Action from USPTO dated May 14, 2009 for U.S. Appl. No. 11/560,317".6"Final Office Action from USPTO dated Nov. 10, 2009 for U.S. Appl. No. 11/057,912".7"Final Office Action from USPTO dated Oct. 26, 2009 for U.S. Appl. No. 10/894,546".8"Final Office Action from USPTO dated Sep. 15, 2009 for U.S. Appl. No. 10/956,501".9"Notice of Allowance from USPTO date Jan. 6, 2011 for U.S. Appl. No. 10/894,732".10"Notice of Allowance from USPTO dated Apr. 7, 2010 for U.S. Appl. No. 11/682,199".11"Notice of Allowance from USPTO dated Aug. 18, 2010 for U.S. Appl. No. 10/957,465".12"Notice of Allowance from USPTO dated Aug. 18, 2010 for U.S. Appl. No. 12/191,890".13"Notice of Allowance from USPTO dated Aug. 19, 2010 for U.S. Appl. 12/267,188".14"Notice of Allowance from USPTO dated Jan. 21, 2010 for U.S. Appl. No. 10/894,547".15"Notice of Allowance from USPTO dated Jul. 19, 2010 for U.S. Appl. No. 10/894,546".16"Notice of Allowance from USPTO dated Jul. 6, 2009 for U.S. Appl. No. 10/894,587".17"Notice of Allowance from USPTO dated Jul. 9, 2009 for U.S. Appl. No. 10/894,726".18"Notice of Allowance from USPTO dated May 18, 2009 for U.S. Appl. No. 10/894,917".19"Notice of Allowance from USPTO dated May 26, 2009 for U.S. Appl. No. 10/894,627".20"Notice of Allowance from USPTO dated May 28, 2010 for U.S. Appl. No. 12/141,519".21"Notice of Allowance from USPTO dated May 5, 2009 for U.S. Appl. No. 10/798,468".22"Notification of Grant of Patent from the State Intellectual Property Office of P.R.C. dated Mar. 25, 2010 for Chinese Application No. 200580032948.4".23"Office Action dated Jun. 19, 2009 from State Intellectual Property Office for Chinese Application No. 200580032948.4".24"Office Action from China State Intellectual Property Office dated Dec. 11, 2009 for Chinese Application No. 200580032948.4".25"Office Action from Chinese State Intellectual Property Office dated Jul. 10, 2009 for Chinese Application No. 200580032888.6".26"Office Action from State Intellectual Property Office dated Dec. 4, 2009 for Chinese Application No. 200580032947.X".27"Office Action from State Intellectual Property Office of China dated May 20, 2010 for Chinese Application No. 200580032947.X".28"Office Action from USPTO dated Apr. 23, 2010 for U.S. Appl. No. 12/191,890".29"Office Action from USPTO dated Dec. 2, 2009 for U.S. Appl. No. 12/141,519".30"Office Action from USPTO dated Jan. 6, 2010 for U.S. Appl. No. 10/956,501".31"Office Action from USPTO dated Jul. 23, 2009 for U.S. Appl. No. 10/894,732".32"Office Action from USPTO dated Jun. 10, 2010 for U.S. Appl. No. 12/259,197".33"Office Action from USPTO dated Jun. 25, 2009 for U.S. Appl. No. 10/894,547".34"Office Action from USPTO dated Mar. 29, 2010 for U.S. Appl. No. 12/189,502".35"Office Action from USPTO dated May 14, 2009 for U.S. Appl. No. 11/682,199".36"Office Action from USPTO dated May 27, 2010 for U.S. Appl. No. 12/267,188".37"Office Action from USPTO dated Oct. 28, 2010 for U.S. Appl. No. 12/189,502".38"Office Action from USPTO dated Sep. 23, 2010 for U.S. Appl. No. 12/476,068".39"Office Action from USPTO dated Sep. 25, 2009 for U.S. Appl. No. 11/682,199".40"Office Action from USPTO dated Sep. 8, 2009 for U.S. Appl. No. 11/743,852".41"Office Action from USTPO dated Jan. 26, 2010 for U.S. Appl. No. 10/956,501".Classifications U.S. Classification370/422, 370/537, 710/313International ClassificationG06F13/38, H04L12/28, H04J3/02, H04L12/56, G06F13/20Cooperative ClassificationH04L49/101, H04L49/357, H04L49/65, G06F13/385European ClassificationG06F13/38A2, H04L49/35H2, H04L49/65Legal EventsDateCodeEventDescriptionOct 18, 2011CCCertificate of correctionDec 21, 2010ASAssignmentOwner name: QLOGIC, CORPORATION, CALIFORNIAEffective date: 20040714Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DROPPS, FRANK R.;PAPENFUSS, GARY M.;KOHLWEY, ERNEST G.;REEL/FRAME:025534/0151RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services