Source: http://www.google.com/patents/US5813036?dq=6,455,937
Timestamp: 2014-03-07 09:29:40
Document Index: 291341834

Matched Legal Cases: ['ART1', 'ART1', 'ART1', 'ART1', 'ART1', 'ART1', 'ART1']

Patent US5813036 - Predictive snooping of cache memory for master-initiated accesses - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsWhen a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take...http://www.google.com/patents/US5813036?utm_source=gb-gplus-sharePatent US5813036 - Predictive snooping of cache memory for master-initiated accessesAdvanced Patent SearchPublication numberUS5813036 APublication typeGrantApplication numberUS 08/851,666Publication dateSep 22, 1998Filing dateMay 6, 1997Priority dateJul 7, 1995Fee statusPaidAlso published asUS5710906, US6405291, US20020069333, US20040139245Publication number08851666, 851666, US 5813036 A, US 5813036A, US-A-5813036, US5813036 A, US5813036AInventorsSubir Ghosh, Hsu-Tien TungOriginal AssigneeOpti Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (3), Non-Patent Citations (2), Referenced by (19), Classifications (8), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetPredictive snooping of cache memory for master-initiated accessesUS 5813036 AAbstract When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.
We claim: 1. A method for reading data in a burst from a memory to a PCI master in response to a burst read access by said PCI master, said burst read access identifying a starting address in a line Ln of said memory, in a system which includes a CPU having a first level cache, comprising the steps of:reading data from said memory according to said burst read access; and simultaneously performing an inquiry cycle of line Ln+1 in said first level cache. 2. A method according to claim 1, further comprising the step, of performing an inquiry cycle of line Ln in said first level cache prior to said step of reading data according to said burst read access.
3. A method for transferring data in a burst between a PCI master and a memory in response to an access of said memory by said PCI master, in a system which includes a CPU having a first level cache, said access identifying a starting address, said first level cache having a first cache line to which a first line of said memory containing said starting address can be mapped, said first level cache further having a next sequential line to which a next sequential line of said memory sequentially beyond the first line of said memory can be mapped, comprising the steps of:snooping said first level cache for said first cache line; transferring data according to said access; and after completing the snoop of said first cache line, automatically snooping said first level cache for said next sequential cache line without waiting for said transfer to reach the end of said first line. 4. A method according to claim 3, wherein said CPU has a host address bus and an EADS# signal input and performs a snoop of said first level cache in response to assertion of said EADS# signal,wherein said step of snooping said first level cache for said first cache line comprises a step of driving said starting address from said PCI master onto said host address bus and asserting said EADS# signal. 5. A method according to claim 3, wherein said access is a write access and wherein said snoop of said first level cache for said first cache line generates a cache hit to a modified line of said first cache, further comprising the steps of:writing back data from said first cache line to said memory prior to said step of transferring data according to said access; and invalidating said first cache line in said first level cache. 6. A method according to claim 3, wherein said access is a write access and wherein said snoop of said first level cache for said first cache line generates a cache hit to an unmodified line of said first cache, further comprising the step of invalidating said first cache line in said first level cache.
7. A method according to claim 3, wherein said access is a read access and wherein said snoop of said first level cache for said first cache line generates a cache hit to a modified line of said first cache, further comprising the step of writing back data from said first cache line to said memory prior to said step of transferring data according to said access.
8. A method according to claim 7, wherein said system further includes a second level cache.
9. Controller apparatus for a computer system which includes a memory, a PCI master and a processor having a first level cache, said controller apparatus comprising circuitry which, in response to a burst read access initiated by said PCI master which identifies a starting address in a line Ln of said memory, reads data from said memory according to said burst read access and simultaneously performs an inquiry cycle of line Ln+1 in said first level cache.
10. Apparatus according to claim 9, wherein said circuitry further performs an inquiry cycle of line Ln in said first level cache in response to said burst read access and prior to reading data from said memory according to said burst read access.
11. Apparatus according to claim 9, further comprising said memory.
12. Apparatus according to claim 9, further comprising said PCI master.
13. Apparatus according to claim 9, further comprising said processor.
14. Apparatus according to claim 9, wherein said memory comprises a cache memory.
15. Apparatus according to claim 9, wherein said memory comprises secondary memory.
16. Apparatus according to claim 15, wherein said memory further comprises a cache memory.
17. A computer system comprising:a memory subsystem; a PCI master; a processor having a first level cache; and controller apparatus including circuitry which, in response to a burst read access initiated by said PCI master which identifies a starting address in a line Ln of said memory subsystem, reads data from said memory subsystem according to said burst read access and simultaneously performs an inquiry cycle of line Ln+1 in said first level cache. 18. Controller apparatus for a computer system which includes a memory, a PCI master and a processor having a first level cache, said controller apparatus comprising circuitry which, in response to a burst read access initiated by said PCI master which identifies a starting address in a starting line Ln of said memory, snoops said first level cache for said starting line; transfers data with said memory according to said burst read access; and after completing the snoop of said first level cache for said starting line, automatically snoops said first level cache for a next sequential line after said starting line without waiting for said transfer to reach the end of said starting line.
19. Apparatus according to claim 18, further comprising said memory.
20. Apparatus according to claim 18, further comprising said PCI master.
21. Apparatus according to claim 18, further comprising said processor.
22. Apparatus according to claim 18, wherein said memory comprises a cache memory.
23. Apparatus according to claim 18, wherein said memory comprises secondary memory.
24. Apparatus according to claim 23, wherein said memory further comprises a cache memory.
25. Apparatus according to claim 18, wherein said processor has a host address bus and an EADS# signal input and performs a snoop of said first level cache in response to assertion of said EADS# signal,and wherein said controller apparatus snoops said first level cache for said starting line by driving said starting address from said PCI master onto said host address bus and asserting said EADS# signal. 26. A computer system comprising:a memory subsystem; a PCI master; a processor having a first level cache; and controller apparatus including circuitry which, in response to a burst read access initiated by said PCI master which identifies a starting address in a starting line Ln of said memory, snoops said first level cache for said starting line; transfers data with said memory according to said burst read access; and after completing the snoop of said first level cache for said starting line, automatically snoops said first level cache for a next sequential line after said starting line without waiting for said transfer to reach the end of said starting line. Description
FIG. 1 is an overall block diagram illustrating pertinent features of a computer system incorporating the invention. The system includes a host processing subsystem 110 connected to a host bus 112. The host bus 112 includes address lines (including HA(31:3) and BE#(7:0)), data lines HD(63:0) and various control lines designated generally as 114. A core logic chipset in the system includes a system controller (SYSC) and an integrated peripherals controller (IPC), indicated generally as 116. The SYSCIPC 116 is connected to the host bus 112, and is also connected to a PCI-bus 118. The PCI-bus 118 includes command and address lines C/BE#(3:0) and AD(31:0), respectively, as well as PCI-bus control lines 120. The SYSC/IPC 116 is also connected to an ISA bus 122, which includes address lines SA and LA, data lines SD and XD, and varcons ISA control lines 124. The SYSC/IPC is also connected to a secondary memory subsystem 126, which is also connected to the address and data leads of the host bus 112. The secondary memory subsystem 126 includes DRAM 128, the address inputs of which are connected via lines MA(11:0) to outputs of the SYSC/IPC 116, and the data port MD(63:0) of which is coupled to the data lines of host bus 112 via a bi-directional buffer 142. The high order 32 bits of the data port, MD(63:32), are also connected back to the SYSC/IPC 116. The secondary memory subsystem 126 also includes a second-level cache 130, the data port of which is connected to the host bus 112 data lines. The high-order bits of the address port for the cache 130 are connected to the output of an address latch 132, the input port of which is connected to receive address lines HA(31:5) from the host bus 112. The next two lower order bits A(4:3) for the address port of L2 cache 130 are driven by signals CHA(4:3) from the SYSC/IPC 116. The secondary memory subsystem 126 communicates via control lines 134 with the SYSC/IPC 116. Various additional buffers and latches are included in the system as well, but they are omitted from FIG. 1 for simplicity of illustration.
An inquire cycle is initiated by the external device by first asserting HOLD or AHOLD to the Pentium processor in order to force the Pentium to float its address bus. Alternatively, the Pentium processor may be forced off the bus due to BOFF#. The external device then drives an inquire address onto the Pentium address leads, drives an INV signal and asserts EADS#. Because the entire 32-byte cache line is affected by an inquire cycle, the inquire address need only include address bits 31:5. These bits are sufficient to identify a "line address". As used herein, a line address is the portion of an address necessary to uniquely identify a data unit of the size of one cache line: (32 bytes for the Pentium). Similarly, a "byte address" includes all address bits since they are all needed to uniquely identify a desired byte, and, in general, a "data unit address" includes whatever address bits are required to uniquely specify an item having the number of bytes in the data unit.
If the processor returns HITM# asserted, then the external device should release the host bus 112 to allow the Pentium processor to perform a write-back cycle. ADS# for the write-back cycle will occur no earlier than two host bus clock cycles after assertion of HITM#. The 32-byte cache line is then written back from L1 cache 212 into secondary memory 126 using the i486-type burst protocol. Note that in certain situations, the Pentium processor may not perform a write-back. Whether or not a write-back is performed, the processor negates HITM# when the L1 cache 212 is consistent with the secondary memory subsystem 126 and the external device can proceed to access the desired memory location in secondary memory 126. Note that if the external device asserted HOLD to the processor to perform the inquire cycle, the processor waits until HOLD is negated before performing the write-back cycle.
The IPC contains an ISA-bus controller and includes the equivalent of an industry standard 82C206, a real-time clock interface, a DMA controller, and a power management unit.
Referring again to FIG. 1, ISA-bus 122 preferably is included in the system, although it is not necessary to an embodiment of the invention. The signal lines and data transfer protocols on ISA-bus 122 are described in the following documents, all incorporated herein by reference: IBM, "Technical Reference, Personal Computer AT" (1985) ; Sanchez, "IBM Microcomputers: A Programmer's Handbook" (McGraw-Hill: 1990); MicroDesign Resources, "PC Chip Sets" (1992); Solari, "AT Bus Design" (San Diego: Annabooks, 1990).
A. Starting Quad Word 00. No HITM#
FIG. 4 is a timing diagram illustrating the operation of the system of FIG. 1 in a situation where a PCI master has requested a burst read access to an address at the beginning of a cache line-sized block in the secondary memory address space (i.e., the low-order five bits of the address are 0, referred to herein by the shorthand that the address ends in `00`). In the illustration of FIG. 4, it is assumed that neither the first cache line to be accessed (with cache line address ending in 00), nor the second cache line to be accessed (with cache line address ending in 20) is cached modified in either the L1 or L2 caches. Either or both lines may be present in the L1 cache, but not in a modified state. It is assumed that neither line is present in the L2 cache 130.
On the HCLK rising edge which begins HCLK period 1, the host processing subsystem 110 recognizes HOLD asserted, and asserts HLDA in response, as illustrated in waveform 426. HLDA remains asserted for the entire burst transfer. The processor is now off the host bus 112, and inquiry and data transfer cycles can proceed. In PCI clock cycle 2/3, the PCI master device 138 places the dword address of the first desired transfer onto the AD lines of the PCI-bus 118. It also at this time places a command on the C/BE# lines of PCI-bus 118, and asserts FRAME# to the system controller 116. (See waveforms 414 and 416.) As mentioned, this address ends in `00`, and designates the first quad word in a cache-line-sized block of the secondary memory address space. The system controller 116 translates this address onto the host bus address lines HA(31:3) as illustrated in waveform 436.
The last Dword in the cache line-sized block of DRAM 128, Dword 1C, is transferred to the PCI device 138 on the rising edge of PCICLK which begins PCICLK cycle 54/55. Note, however, that no delay is incurred before the transfer of Dword 20, which is the first Dword of the next cache line address. In fact, in the situation illustrated in FIG. 4, all of the data transfers in the burst take place at a constant rate, specifically one Dword in every two PCICLK cycles, even as the burst continues beyond the cache line boundary. This is a consequence of the features of the present embodiment of the invention.
B. Starting Quad Word 00, HITM# On Initial Cache Snoop
C. During Burst Transfer. Snoop of Next Cache Line Produces HITM# Asserted.
Also in response to HITM# asserted, the system controller 116 negates HOLD in HCLK cycle 31 in order to allow the write-back cycle to take place. At the beginning of HCLK cycle 32, the host processing subsystem 110 samples HOLD negated and negates HLDA in response thereto. In HCLK cycle 33, the host processing subsystem 110 asserts HADS#, and the write-back cycle consisting of four BRDY#'s takes place. The system controller 116 samples HADS# asserted at the beginning of HCLK cycle 34, and if the PCI device or another device desires control of the host bus 112, the system controller 116 can reassert HOLD as early as HCLK cycle 35 in order to reclaim the host bus 112 as soon as the write back is complete. Thus the write back cycle has taken place, the system controller 116 is master on the host bus 112, and the PCI-bus master device 138 can restart its burst transfer at the beginning of the next secondary memory line.
Referring to FIG. 7, in PCICLK cycle 2/3, the PCI device 138 drives the quad word address QWA(18) of the first desired transfer of the burst, onto the PCI-bus 118 AD lines. It asserts FRAME# in PCICLK cycle 2/3 and asserts IRDY# in PCICLK cycle 4/5. The system controller 116 translates the line address portion of the starting quad word address, specifically line address (00), onto the host bus 112 address lines HA(31:5) in HCLK cycle 4. In response to FRAME# and IRDY# asserted at the beginning of HCLK cycle 6, system controller 116 asserts EADS# in HCLK cycle 6 to initiate an inquiry cycle. The system controller 116 samples HITM# negated at the beginning of HCLK cycle 9, and in response thereto, after synchronization, asserts TRDY# to the PCI device 138 in PCICLK cycle 24/25. By this time, the first Dword of the transfer, D(18), is present on the PCI-bus 118 AD(31:0) lines. D(18) is transferred on the rising edge which begins PCICLK cycle 26/27. The transfer of dword D(1C) is delayed somewhat, however, because a determination must first be made as to whether to simultaneously assert STOP#. (If STOP# is to be asserted, it must be asserted simultaneously with the final TRDY#.) In response to IRDY# and TRDY# both sampled asserted at the beginning of PCICLK cycle 26/27, the system controller 116 drives the next line address, line address 20, onto HA(31:5). Also in PCICLK cycle 26/27, HACALE is asserted. Further, in HCLK cycle 29, the system controller 116 asserts EADS# to the host processing subsystem 110 in order to initiate the next line L1 cache inquiry. As in the illustration of FIG. 6, should HITM# be returned asserted, the system controller 116 would stop the burst on the PCI-bus 118 at this time and allow a write-back to take place. In the illustration of FIG. 7, however, HIFM# is sampled negated at the beginning of HCLK cycle 32. In response thereto, the system controller 116 asserts TRDY# in PCICLK cycle 34/35 and the last data unit D(1C) is transferred without a simultaneous assertion of STOP#. TRDY# is again asserted in PCICLK cycle 38/39, and the first data unit (D(20)) of the next secondary memory line (line address (20)) is transferred on the PCICLK rising edge which begins cycle 40/41. Data units then continue to be transferred in the manner described above with respect to FIGS. 4 and 6, until the burst is terminated either by the PCI device 138 on its own initiative, or by the system controller 116 in response to HITM# sampled asserted. It can be seen that although some delay is incurred at the secondary memory line boundary (note the delay in FIG. 7 between the second and third assertions of TRDY#), this delay is significantly shorter than the delay which is incurred by the conventional technique of automatically stopping the burst at the cache line boundary, forcing the PCI device to re-arbitrate for the PCI-bus 118, perform a new PCI-bus address phase, and wait for a new snoop cycle to take place for the new line address.
The system of FIG. 1 solves this problem through the use of a latch 132 coupled between HA(31:5) and the A (31:5) lines of the address port of the L2 cache 130. The latch 132 is enabled by HACALE,. driven by the system controller 116 (latch 132 is transparent when HACALE=1, and is latched when HACALE=0). As can be seen in each of FIGS. 4, 5, 6 and 7, the system controller 116 negates HACALE before it changes the line address on HA(31:5) and reasserts HACALE after the last quad word of the current L2 cache line has been transmitted to the system controller 116. HACALE opens latch 132 while the system controller 116 is still driving the next line address onto HA(31:5), and again closes the latch before it begins driving the third line address onto HA(31:5) for the next predictive snoop cycle.
TABLE I______________________________________DMA/Master Read Cycle SummaryDMA/MasterRead Cycle         Type of         Type ofL1    L2      Data     Cycle for                         Type of Cycle                                  CycleCache Cache   Source   L1 Cache                         for L2 Cache                                  for DRAM______________________________________Hit   Hit     L2 Cache No     Read the Bytes                                  No Change                  Change RequestedhitM  Hit     L1 Cache Castout                         Write CPU                                  No Change                         Data, Read                         Back the Bytes                         RequestedHit   Miss    DRAM     No     No Change                                  Read the                  Change          Bytes                                  RequestedhitM  Miss    L1 Cache Castout                         No Change                                  Write CPU                                  Data, Read                                  Back the                                  Bytes                                  RequestedMiss  Hit     L2 Cache No     Read the Bytes                                  No Change                  Change RequestedMiss  Miss    DRAM     No     No Change                                  Read                  Change______________________________________
TABLE II______________________________________DMA/Master Write Cycle SummaryDMA/MasterWrite Cycle     Data      Type of  Type of Type ofL1    L2      Destina-  Cycle for                          Cycle   CycleCache Cache   tion      L1 Cache                          for L2 Cache                                  for DRAM______________________________________Hit   Hit     DRAM,     Invalidate                          Write Master                                  Write Master         L2 Cache         Data    DatahitM  Hit     DRAM,     Castout,                          Write CPU                                  Write CPU         L2 Cache  Invalidate                          Data, Write                                  Data,                          Master Data                                  Write Master                                  DataHit   Miss    DRAM      Invalidate                          No Change                                  Write Master                                  DatahitM  Miss    DRAM      Castout,                          No Change                                  Write CPU                   Invalidate     Data, Write                                  Master DataMiss  Hit     DRAM,     No     Write Master                                  Write Master         L2 Cache  Change Data    DataMiss  Miss    DRAM      No     No Change                                  Write Master                   Change         Data______________________________________
LT2 is connected to one input of a three-input NAND gate 818. The second input of NAND gate 818 receives DISLT2B, which can be assumed to remain-high, and an LSTART1B signal, which is high as long as the system controller 116 is not yet certain that the data in secondary memory 126 at the secondary memory line address specified by the PCI master 138 is the latest copy of the data. That is, LSTART1B goes low after the host processing subsystem 110 brings HITM# high, either immediately after EADS# or following an L1 cache write-back cycle.
The output of NAND gate 818 is connected to one input of a two-input NAND gate 820, the other input of which is connected to the output of a two-input NAND gate 822. One input of NAND gate 822 is connected to receive a PSNEN signal, which enables the pre-snoop feature and can be assumed to be high throughout, and the other input is connected to receive a PSNSTR1 signal. The latter signal is used during predictive snoop operations, which take place later in the burst (see PCICLK cycle 32/33 in FIG. 4, e.g.). At the initial assertion of FRAME#, PSNSTR1 remains low. As described below, PSNSTR1 will carry a high-going pulse when it is desired to assert EADS# for predictive snoop cycle later in the burst. Accordingly, as can be seen, the output of NAND gate 820, designated SLT2TG ("synchronous local T2 trigger") carries a high-going, one PCICLK-cycle-wide pulse, in the PCICLK cycle following that in which FRAME# was :asserted. SLT2TG will also carry a one PCICLK-cycle-wide high-going pulse at the time a predictive snoop cycle is to take place.
The output of NAND gate 842 is connected to the D input of a D flip-flop 846, clocked by the CLK signal to produce a Q output designated CK.sub.-- EADS. CK.sub.-- EADS is connected to the D input of another flip-flop 848, clocked by CLK, to produce on its QN output the EADS1B signal. CK.sub.-- EADS and EADSlB are fed back to the two inputs of NAND gate 844 as previously stated. It can be seen that because of this feedback, the output of NAND gate 842 will carry a high-going pulse which is the width of two HCLK cycles.
The output of NAND gate 842 is connected to the D input of another D flip-flop 850, which id clocked by an ECLK signal. ECLK ("early clock") is equivalent to HCLK, except that it operates a few nanoseconds earlier. The Q output of flip-flop 850 is connected to the `0` input of an inverting multiplexer 852, the output of which carries an EADSO signal for the EADS# output of system controller 116. The `1` input of multiplexer 852 receives a CPU.sub.-- WT signal, and the select input receives an AHOLDOB signal. AHOLDOB is low at all pertinent times, so EADS# carries the output of flip-flop 850.
The Q output of flip-flop 906 is inverted and qualified, in three-input NAND gate 910, by IRDY and MFRAME. IRDY is the inverse of the PCI-bus 118 IRDY# signal, and as previously explained, MFRAME essentially follows the inverse of the PCI-bus FRAME# signal. Thus, NAND gate 910 blocks the output of flip-flop 906 if the PCI device 138 has already indicated that the present transfer is to be the last transfer of the burst. Otherwise, the output of NAND gate 910 (called FTRDTGB ("first TRDY# trigger")) carries a one PCICLK-wide low-going pulse, beginning with the PCICLK rising edge that ends the first PCI transfer of the current line of secondary memory.
STOPTGP is connected to one input of a four-input NAND gate 1020, the other inputs of which are connected to FRAMEI, IRDY (equivalent to the inverse of the PCI-bus IRDY# signal) and PCICYC. Thus, NAND gate 1020 qualifies STOPTGP to ensure that a PCI cycle is currently taking place, and IRDY# and FRAME# are still asserted. The output of NAND gate 1020 is connected to one input of a three-input NAND gate 1022. A second input of NAND gate 1022 is connected to the output of a NAND gate 1024, which receives STOPTG1 (previously described) and STOP (equivalent to the inverse of STOP#). The third input of NAND gate 1022 is connected to the output of a NAND gate 1026, which receives NOFRAME and a signal NOFRDNLB, described below. The output of NAND gate 1022 is connected to the D input of an LCLKI-clocked flip-flop 1028, the Q output of which is the NOFRAME signal connected back to an input of NAND gate 1026. It can be seen that NOFRAME will be asserted by a flip-flop 1028 in the PCICLK cycle following that in which STOPTGP was asserted, assuming the master has not yet terminated the burst, and will remain asserted until either STOP# is asserted or the NOFRDN1B signal is negated.
The output of NAND gate 1034 is, connected to one input of a D flip-flop 1038, the QN output of which is NORed with an inverted version of the Q output of flip-flop 1038 to produce an NOFRDN1 signal. Flip-flop 1038 is clocked on LCLKIB. NOFRDN1 is inverted by an inverter 1040 to produce the NOFRDN1B signal provided to NAND gate 1026. NOFRDN1 is also connected to the D input of a flip-flop 1042, which is clocked on LCLKI, the QN output of which is connected back to the third input of NAND gate 1036. The effect of flip-flops 1028, 1038 and 1042, and their associated logic gates, is to make NOFRAME have a width of at least one PCICLK cycle and to ensure that the CPU has sufficient time to generate HITM#.
STOPTGP is also connected to one input of a three-input NAND gate 1044, which qualifies the signal once again to ensure that the current cycle is a PCI cycle and that the master has not yet negated FRAME# (because STOP# can be asserted only when FRAME# is active). The circuitry also includes two other NAND gates 1046 and 1048, each of which go low to trigger STOP# in situations not pertinent to the present invention. A fourth NAND gate 1050 receives FRAME and STOP as inputs. The outputs of NAND gates 1044, 1046, 1048 and 1050 are connected to respective inputs of a four-input NAND gate 1052, the output of which, designated STOP.sub.-- TG, is connected to the D input of an LCLKI-clocked flip-flop 1054. The Q output of flip-flop 1054 is the STOP signal connected back to NAND gates 1050 and 1024, and the QN output of flip-flop 1054 is the output signal which drives STOP# on the PCI-bus 118. It can be seen, therefore, that STOP# will have a width of one PCICLK cycle in response to STOPTGP produced by NAND gate 1018.
LSTRT.sub.-- TB is connected to one input of a NOR gate 1218, the other input of which receives a signal which can be assumed herein to remain low at all times pertinent to the invention. The output of NOR gate 1218 is connected to the D input of another flip-flop 1220, which is clocked on LCLKI. The inverting clear input of flip-flop 1220 is connected to the same output of AND gate 1212 which clears flip-flop 1210. The QN output of flip-flop 1220 is NORed with an inverted version of a Q output of flip-flop 1220 to produce an LSTRT1 signal. LSTRT1 is inverted by an inverter 1222 and fed back as LSTRT1B to a fourth input of NAND gate 1214. Thus, after qualifications, LSTRT1 goes high, synchronously with PCICLK, after HITM#=1 or after HITM#=0 and the write-back cycle is complete.
The Q output of flip-flop 1236, LSTARTM, is connected to one input of a NOR gate 1238, the output of which is the LST.sub.-- TGR signal fed back to NAND gate 1228. The other input of NOR gate 1238 receives the LSTART1 signal as described hereinafter. LSTARIM is also connected to one input of another NAND gate 1240, the other input of which receives SYSMMD (high when the specified address is within the DRAM 128 address space). SYSMEMD is also connected to one input of a three-input NAND gate 1242, a second input of which receives LSTART1. The outputs of NAND gates 1240 and 1242 are connected to respective inputs of another NAND gate 1244, the output of which is connected to the D input of an LCLKI-clocked flip-flop 1246. The Q output of flip-flop 1246 forms the LSTART1 signal, connected as previously described to one input of NOR gate 1238 and to one input of NAND gate 1242. The QN output of flip-flop 1246 is the LSTART1B signal which is fed back to AND gate 1212 as previously described. It can be seen that after LSTRT causes LSTARTM to go high, LST.sub.-- TGR will go low, causing LSTARTM to go low again in the next PCICLK cycle. LST.sub.-- TGR will not go high at this time, however, because when LSTARTM went high, it caused LSTART1 to also go high in the next PCICLK cycle, thereby maintaining LST.sub.-- TGR low.
FIGS. 4-7 are timing diagrams illustrating the operation of the system of FIG. 1; and FIGS. 8-12 are schematic diagrams of circuitry in the system controller of FIG. 1.
General information on the various forms of IBM PC AT-compatible computers can be found in IBM, "Technical Reference, Personal Computer AT" (1985), in Sanchez, "IBM Microcomputers: A Programmer's Handbook" (McGraw-Hill: 1990), in MicroDesign Resources, "PC Chip Sets" (1992), and in Solari, "AT Bus Design" (San Diego: Annabooks, 1990). See also the various data books and data sheets published by Intel Corporation concerning the structure and use of the 80x86 family of microprocessors, including Intel Corp., "Pentium� Processor", Preliminary Data Sheet (1993); Intel Corp., "Pentium� Processor User's Manual" (1994); "i486 Microprocessor Hardware Reference Manual", published by Intel Corporation, copyright date 1990, "386 SX Microprocessor", data sheet, published by Intel Corporation (1990), and "386 DX Microprocessor", data sheet, published by Intel Corporation (1990). In addition, a typical core logic chipset includes the OPTi 82C802G and either the 82C601 or 82C602, all incorporated herein by reference. The 82C802G is described in OPTi, Inc., "OPTi PC/AT Single Chip 82C802G Data Book", Version 1.2a (Dec. 1, 1993), and the 82C601 and 82C602 are described in OPTi, Inc., "PC/AT Data Buffer Chips, Preliminary, 82C601/82C602 Data Book", Version 1.0e (Oct. 13, 1993). All the above references are incorporated herein by reference.
As the x86 family of microprocessors has advanced, additional functions have been included on the microprocessor chip itself. For example, while i386-compatible microprocessors did not include any cache memory on-chip, the i486-compatible microprocessors did. Specifically, these microprocessors included a level one, "write-through" cache memory.
Because of the burst mode of PCI masters, the problem of performing inquire cycles is somewhat more difficult when the bus master is a PCI-bus master than when it is a CPU bus master or ISA-bus master. According to the Pentium databooks, every data transfer to or from the memory address space which is cached by the L1 cache should be preceded by an inquire cycle. This would severely hamper the performance of PCI masters performing burst cycles to or from secondary memory. Many PCI-bus controller chipsets speed up these transfers by performing an inquire cycle only once per cache line instead of on each data transfer. These controllers simply assume that no change will be made to the cache line contents during the remainder of the PCI-bus master burst transfer with the corresponding line of secondary memory. The Intel 82433LX local bus accelerator, for example, maintains a PCI-to-memory read prefetch buffer equal in depth to the length of one cache line, so that if the Pentium processor performs a write-back cycle in response to the inquire cycle, the local bus accelerator chip can capture the remaining words of the cache line for easy completion of further PCI-bus master read accesses within the burst. The 82433LX is described in Intel, "82340 PCIset Cache/Memory Subsystem" (April 1994), incorporated herein by reference.
Although the invention is described herein with respect to a PCI-bus Pentium system, its usefulness is not limited to such systems. The invention is useful whenever an L1 cache is present which can use a write-back protocol, and which supports inquire cycles, and whenever an I/O bus is present which has a linear-incrementing capability or mode which can continue beyond an L1 cache line boundary.
This application is a continuation of U.S. patent applicaton Ser. No. 08/499,610, filed Jul. 7, 1995, now U.S. Pat. No. 5,710,906.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5341427 *Apr 23, 1993Aug 23, 1994Motorola, Inc.Algorithm independent cryptographic key management apparatusUS5535363 *Jul 12, 1994Jul 9, 1996Intel CorporationMethod and apparatus for skipping a snoop phase in sequential accesses by a processor in a shared multiprocessor memory systemUS5630094 *Jan 20, 1995May 13, 1997Intel CorporationIntegrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions* Cited by examinerNon-Patent CitationsReference1Intel, "Pentium Family User's Manual--vol. 2:82496/82497 Cache Controller and 82491/82492 Cache SRAM Data Book"; pp. 3-18, 3-19, & 5-95, 1994.2 *Intel, Pentium Family User s Manual vol. 2:82496/82497 Cache Controller and 82491/82492 Cache SRAM Data Book ; pp. 3 18, 3 19, & 5 95, 1994.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5930821 *May 12, 1997Jul 27, 1999Integrated Device Technology, Inc.Method and apparatus for shared cache lines in split data/code cachesUS5983024 *Nov 26, 1997Nov 9, 1999Honeywell, Inc.Method and apparatus for robust data broadcast on a peripheral component interconnect busUS6141735 *Apr 29, 1998Oct 31, 2000Elkhoury; Bassam N.Performing a memory access cycle in a multi-processor computer systemUS6266723Mar 29, 1999Jul 24, 2001Lsi Logic CorporationMethod and system for optimizing of peripheral component interconnect PCI bus transfersUS6279081Dec 22, 1998Aug 21, 2001Hewlett-Packard CompanySystem and method for performing memory fetches for an ATM cardUS6405288 *Aug 10, 1999Jun 11, 2002Via Technologies, Inc.Method and system for controlling the memory access operation by central processing unit in a computer systemUS6446172 *Jun 18, 1999Sep 3, 2002Via Technologies, Inc.Method and system for controlling the memory access operation performed by a central processing unit in a computer systemUS6470416 *Jun 18, 1999Oct 22, 2002Via Technologies, Inc.Method and system for controlling the memory access operation by central processing unit in a computer system (2)US6654854 *Jun 25, 1999Nov 25, 2003Hewlett-Packard Development Company, L.P.Caching method using cache tag and cache data stored in dynamic RAM embedded in logic chipUS6658537 *May 8, 1998Dec 2, 20033Com CorporationDMA driven processor cacheUS6745298 *Jun 16, 1999Jun 1, 2004Intel CorporationInternal processor buffering for implicit writebacksUS6775749 *Jan 29, 2002Aug 10, 2004Advanced Micro Devices, Inc.System and method for performing a speculative cache fillUS6829665 *Sep 28, 2001Dec 7, 2004Hewlett-Packard Development Company, L.P.Next snoop predictor in a host controllerUS6993633 *Jul 28, 2000Jan 31, 2006Hitachi, Ltd.Computer system utilizing speculative read requests to cache memoryUS7051162Apr 7, 2003May 23, 2006Hewlett-Packard Development Company, L.P.Methods and apparatus used to retrieve data from memory before such data is requestedUS7055005Apr 7, 2003May 30, 2006Hewlett-Packard Development Company, L.P.Methods and apparatus used to retrieve data from memory into a RAM controller before such data is requestedUS7523245Aug 22, 2006Apr 21, 2009Opti, Inc.Compact ISA-bus interfaceUS7689758Jul 12, 2007Mar 30, 2010Atmel CorporationDual bus matrix architecture for micro-controllersUSRE37980 *Nov 3, 2000Feb 4, 2003Compaq Computer CorporationBus-to-bus bridge in computer system, with fast burst memory range* Cited by examinerClassifications U.S. Classification711/146, 711/E12.35, 711/E12.57International ClassificationG06F12/08Cooperative ClassificationG06F12/0835, G06F12/0862European ClassificationG06F12/08B4P4P, G06F12/08B8Legal EventsDateCodeEventDescriptionMar 22, 2010FPAYFee paymentYear of fee payment: 12Mar 22, 2006FPAYFee paymentYear of fee payment: 8Apr 9, 2002REMIMaintenance fee reminder mailedMar 21, 2002FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google