Source: https://patents.google.com/patent/JP5795260B2/en
Timestamp: 2019-11-19 23:58:50
Document Index: 341268626

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JP5795260B2 - Transistor with embedded strain-inducing material having a step-shaped structure - Google Patents
Transistor with embedded strain-inducing material having a step-shaped structure Download PDF
JP5795260B2
JP5795260B2 JP2011542724A JP2011542724A JP5795260B2 JP 5795260 B2 JP5795260 B2 JP 5795260B2 JP 2011542724 A JP2011542724 A JP 2011542724A JP 2011542724 A JP2011542724 A JP 2011542724A JP 5795260 B2 JP5795260 B2 JP 5795260B2
JP2011542724A
JP2012514317A (en
クロンホルツ ステファン
パパゲオルギウ ヴァシリオス
ビアニンク ガンダ
2008-12-31 Priority to DE102008063427.1 priority Critical
2008-12-31 Priority to DE200810063427 priority patent/DE102008063427B4/en
2009-12-29 Application filed by アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ, アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ filed Critical アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ
2012-06-21 Publication of JP2012514317A publication Critical patent/JP2012514317A/en
2015-10-14 Publication of JP5795260B2 publication Critical patent/JP5795260B2/en
In general, this disclosure relates to integrated circuit fabrication, and more particularly to a transistor having a channel region that is distorted by using a buried semiconductor material to increase charge carrier mobility within the channel region of the transistor.
The manufacture of complex integrated circuits requires the provision of a large number of transistor elements that are representative of the main circuit elements for the complex circuit. For example, in complex integrated circuits currently available, millions of transistors may be provided. In general, many process technologies have been implemented so far, and for complex circuits such as microprocessors, memory chips, etc., due to their superior characteristics considering operating speed and / or power consumption and / or cost effectiveness, At present, CMOS technology is the most promising approach. In CMOS circuits, complementary transistors, i.e., p-channel transistors and n-channel transistors are used to design circuit elements such as inverters and other logic gates in order to design highly complex circuit assemblies such as CPUs, memory chips, etc. Used to form. In the manufacture of complex integrated circuits using CMOS technology, a plurality of transistors, an n-channel transistor and a p-channel transistor, are formed on a substrate that includes a crystalline semiconductor layer. MOS transistors, or generally field effect transistors, have a plurality of so-called pn junctions, regardless of whether n-channel transistors or p-channel transistors are considered, and the pn junctions are heavily doped It is formed by the interface between the drain and source regions and the inversely or lightly doped channel region disposed between the drain and source regions. The conductivity of the channel region, ie the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated from the channel region by a thin insulating layer. When a conductive channel is formed by applying an appropriate control voltage to the gate electrode, the conductivity of the channel region depends on the dopant concentration and charge carrier mobility, and in addition, given the channel region in the transistor width direction. This extension also depends on the distance between the source and drain regions, also called channel length. Thus, the reduction in channel length and the accompanying reduction in channel resistance are the dominant design criteria for achieving an increase in the operating speed of integrated circuits.
However, the continued reduction in transistor dimensions has caused many problems with it, and these problems do not seem to unduly offset the benefits that can be obtained by steadily reducing the channel length of MOS transistors. Needs to be addressed. For example, in the drain and source regions, highly sophisticated dopant profiles in the vertical and lateral directions are required to provide low sheet resistance and contact resistance with the desired channel controllability. Also, to maintain the required channel controllability, the gate dielectric material is also adapted to channel length reduction. However, some mechanisms for maintaining high channel controllability can also have a negative impact on the charge mobility in the channel region of the transistor, so the benefits gained by reducing the channel length are partially It may cancel out.
Continuous dimension reduction of critical dimensions, i.e. transistor gate length, requires highly complex process technology adaptations and possibly new developments, and less obvious performance due to lower mobility It can also contribute to the improvement, thus increasing the charge carrier mobility in the channel region for a given channel length to improve the channel conductivity of the transistor element, thereby significantly reducing the critical dimension It has been proposed to avoid or defer many of the process adaptations associated with device scaling while allowing performance improvements equivalent to advances to the required technical standards.
One effective mechanism for increasing the charge carrier mobility is that of the lattice structure in the channel region, for example by generating a tensile or compressive stress in the vicinity of the channel region so as to cause a corresponding strain in the channel region. An improvement, which results in improved mobility for electrons and holes, respectively. For example, creating a tensile strain in the channel region for a standard crystal structure of active silicon material, ie, a (100) surface orientation with a channel length aligned in the <110> direction, can reduce the mobility of electrons. Will increase and then change directly to the corresponding increase in conductivity. On the other hand, compressive strain in the channel region can increase the mobility of holes, thereby providing the possibility of enhancing the performance of p-type transistors. Strained silicon can be considered a “new” type of semiconductor material that allows for the production of fast and powerful semiconductor devices without the need for expensive semiconductor materials, while sufficient The introduction of stress or strain engineering into integrated circuit manufacturing is a very promising approach since many manufacturing techniques established in
Thus, it has been proposed to introduce a silicon / germanium material, for example adjacent to the channel region, so as to induce a compressive stress that can result in a corresponding strain. When forming a Si / Ge material, the drain and source regions of the PMOS transistor are selectively recessed to form a cavity, while the NMOS transistor is masked and then the silicon / germanium material is selected into the cavity of the PMOS transistor by epitaxial growth. Formed.
While this technology offers significant benefits in terms of improving the performance of p-channel transistors and thus in terms of overall CMOS device performance, it increases the distortion that is ultimately achieved, especially in modern semiconductor devices that include multiple transistor elements. In view of the above, the offset from the channel region of silicon / germanium material should be reduced, which relates to the technique described above for incorporating strained silicon-germanium alloys into the drain and source regions of p-channel transistors It has been found that an increase in the variability of the resulting device performance may be observed, which will be described in more detail with reference to FIGS. 1a to 1e.
FIG. 1a schematically shows a cross-sectional view of a conventional semiconductor device 100 comprising a p-channel transistor 150A and an n-channel transistor 150B, where the performance of the transistor 150A is based on a strained silicon / germanium alloy as described above. It will be enhanced on the basis. The semiconductor device 100 includes a substrate 101, such as a silicon substrate, on which a buried insulating layer 102 may be formed. A crystalline silicon layer 103 is formed on the buried insulating layer 102, thereby forming an SOI (silicon-on-insulator) configuration. For example, the parasitic junction capacitance of transistors 150A and 150B can be reduced compared to a bulk structure, ie, a structure in which the thickness of silicon layer 103 would be significantly greater than the vertical extension of transistors 150A and 150B into layer 103. Considering the performance of the entire transistor, the SOI structure will be advantageous. Transistors 150A and 150B may be formed within and above respective “active” regions, generally indicated by 103A and 103B, respectively, where the active regions are shallow trench isolations. isolation) such as isolation). In the illustrated manufacturing stage, the transistors 150A and 150B include a gate electrode structure 151. The gate electrode structure 151 can be understood as a structure including a conductive electrode material 151A that represents an actual gate electrode. The conductive electrode material 151A will be formed on the gate insulating layer 151B, thereby electrically insulating the gate electrode material 151A from the channel regions 152 located within the corresponding active regions 103A and 103B, respectively. can do. The gate electrode structure 151 will also include a cap layer 151C made of, for example, silicon nitride. Further, the spacer structure 105 will be formed on the side wall of the gate electrode structure 151 in the transistor 150A, so that the gate electrode material 151A can be sealed in combination with the cap layer 151C. On the other hand, a mask layer 105A will be formed above the transistor 150B, so that the corresponding gate electrode material 151A can be sealed to cover the active region 103B. Further, a mask 106, such as a resist mask, may be formed to cover the mask layer 105A while exposing the transistor 150A.
The conventional semiconductor device 100 shown in FIG. 1a can be formed based on the following process strategy.
The active regions 103A, 103B can be defined based on the isolation structure 104, which can be formed by using well-established photolithography, etching, deposition and planarization techniques. Thereafter, the basic doping level in the corresponding active region 103A, 103B will be established, for example by an implantation process carried out based on a suitable masking regime. A gate electrode structure 151 is then formed using a complex lithography and patterning regime to obtain a gate electrode material 151A and a gate insulating layer 151B, where the cap layer 151C will also be patterned. The mask layer 105A may then be deposited, for example, by well-established low pressure CVD (chemical vapor deposition) techniques, whereby silicon nitride is optionally combined with a silicon dioxide material as an etch stop liner. Will be formed. Low pressure CVD techniques will provide a high degree of controllability, but will exhibit some degree of non-uniformity across the substrate 101 and may result in increased thickness at the substrate edge relative to the center of the substrate. As a result, when the device 100 is exposed to an anisotropic etching environment to form the mask 106 and form the spacer structure 105 from the previously deposited mask layer 105A, the resulting width of 105W Non-uniformity may occur, and this non-uniformity may result in a slightly increased width at the periphery of the substrate 101 as compared to the central area of the substrate 101, for example. Since the spacer structure 105 will substantially define the lateral offset of the cavity that will be formed in the active region 103A by anisotropic etching techniques, the corresponding lateral offset will also be the mask layer. It may vary slightly according to non-uniformities introduced during the deposition of 105A and the subsequent execution of the anisotropic etching process. On the other hand, in sophisticated applications, the lateral strain of the corresponding strained silicon / germanium alloy will be reduced in view of increasing the overall strain in the adjacent channel region 152, thereby The width 105W will need to be reduced to position the strained silicon / germanium alloy close to the channel region 152. Typically, the distortion in the channel region 152 will increase in an inverse proportion to the reduced width 105W, resulting in a sophisticated need to yield a reasonably small width 105W. In the process strategy, variations due to the deposition of layer 105A and the subsequent etching process will also be increased in an extremely proportional manner, resulting in transistor 150A as a result of extremely reduced semiconductor devices. Can contribute to a large degree of variation in performance.
FIG. 1 b schematically shows the semiconductor device 100 during an anisotropic plasma assisted etching process 107, which has a corresponding anisotropic etching behavior in combination with appropriately selected plasma conditions. As obtained, suitable etching chemicals based on, for example, hydrogen bromide can be used in combination with suitable organic additives. However, as already explained, some variability will also be introduced during the plasma assisted etching process 107, which can lead to significant changes in transistor performance, especially even small differences in lateral offset. It can also contribute to the overall variation when considering highly sophisticated transistors that can result. Thus, the width of the previous deposition of layer 105A and the corresponding anisotropic etching process to form the spacer structure 105 and possibly the combined anisotropic etching process used to form each cavity 107A. Due to the change of 105W, the location and size of the cavity 107A will also exhibit a corresponding degree of variation.
FIG. 1c schematically shows the semiconductor device 100 in a further advanced manufacturing stage. That is, after forming cavity 107A (see FIG. 1b), mask 106 is removed and a selective epitaxial growth process is performed to deposit silicon / germanium alloy 109 in transistor 150A while transistor 150B is masked. Covered by layer 105A. Corresponding selective epitaxial growth recipes are well established, with significant deposition of silicon / germanium material on the exposed crystalline silicon surface, while corresponding material deposition on the dielectric surface is significant. Corresponding process parameters such as pressure, temperature, precursor flow rate, etc. are appropriately selected so that they can be reduced or ignored. Since the intrinsic lattice constant of silicon / germanium is greater than that of silicon, the silicon / germanium material 109 will be grown in a strained state, thereby corresponding compression in the adjacent channel region 152 as well. A compressively strained material can be obtained that will cause strain. The magnitude of the compressive strain may depend on the location and size of the previously formed cavity and the germanium concentration in the material 109. Thus, for given process parameters during the selective epitaxial growth process to form material 109, the mask layer 105A is formed, the spacer structure 105 is patterned, and the priorities for forming the cavity 107A. Variations in the manufacturing process thus will result in specific non-uniformities in transistor performance across the substrate 101.
FIG. 1d schematically shows the semiconductor device 100 in a further advanced manufacturing stage, in which the mask layer 105A, the spacer structure 105 and the cap layer 151C (see FIG. 1a) have been removed, which is sufficient. Can be achieved by selective etching techniques established in the past. Thereafter, further processing may continue by forming drain and source regions according to device requirements.
FIG. 1e schematically illustrates the semiconductor device 100 in a manufacturing stage where the basic transistor structure is substantially completed. As shown, the transistors 150A, 150B will include a sidewall spacer structure 153, which may be accommodated depending on the required complexity of the dopant profile of the drain and source regions 154. One or more spacer elements 153A may be included in combination with an etch stop liner 153B. The spacer structure 153 can be formed according to well-established techniques, i.e., depositing an etch stop liner 153B and corresponding mask layer, which are then anisotropically etched to form the spacer element 153A. Can be formed by patterning. Prior to forming the spacer structure 153, a suitable implantation process will be performed to define an extension region 154E, which may be formed on the drain and source regions 154D that may be formed based on the spacer structure 153. In combination, the drain and source regions 154 are representative. Thereafter, annealing the device 100 will activate the dopant, so that the implantation-induced damage can also be recrystallized, at least to some extent. Thereafter, further processing may continue by forming metal silicide regions and corresponding contact structures, possibly based on strained dielectric materials according to well-established process strategies. As noted above, for sophisticated applications, the performance of transistor 150A will be substantially determined by the strain inducing mechanism provided by silicon / germanium alloy 109, in this case especially from channel region 152. While a reasonably high degree of variation in the desirably reduced lateral offset of the silicon / germanium material 109 can cause a low manufacturing yield, in other cases a corresponding offset from the channel region 152 is present. The ability of the strain inducing mechanism provided by the material 109 may not be fully utilized because it needs to be maintained larger than desired.
In view of the circumstances described above, the present disclosure provides techniques and semiconductor devices in which high transistor performance can be achieved with an epitaxially grown semiconductor alloy while avoiding or at least reducing the effects of one or more of the problems identified above. Is related to.
In general, the present disclosure can form a cavity in the active region of a transistor device with increased controllability with respect to a lateral offset relative to the channel region based on two or more dedicated spacer elements, thereby providing a cavity and Accordingly, the present invention relates to a semiconductor device and technology that enables a step-shaped structure of a strain-induced semiconductor alloy to be formed therein. For example, the first portion of the cavity may be provided with a reduced depth that can be achieved based on a sufficiently controllable etching process and a desirable small offset from the channel region, which is described above. In the past, a process sequence based on two or more spacer elements can be used to define the structure of the strain-induced semiconductor alloy, since process non-uniformities that would otherwise result in significant transistor variations can be reduced. A high degree of flexibility can be achieved. Thereafter, in one or more additional etching processes, the overall process non-uniformity is reduced despite the fact that the cavity depth and lateral expansion can be adapted to obtain a high overall strain-inducing effect. Can be reduced. In addition, in some exemplary aspects disclosed herein, a manufacturing sequence for forming a strain-inducing semiconductor alloy based on two or more spacer elements may also include, for example, in situ doping. In consideration of the material composition, etc., it is possible to provide high flexibility in providing the semiconductor alloy with different characteristics. As a result, the scalability of the strain-inducing mechanism obtained from embedded semiconductor alloys does not unduly compromise the uniformity of transistor characteristics and does not contribute significantly to overall process complexity. Can be enlarged.
One exemplary method disclosed herein forms a first recess in a crystalline semiconductor region with an offset from a gate electrode structure defined by a first sidewall spacer formed on a sidewall of the gate electrode. Where the first recess extends to a first depth. The method further comprises forming a second recess in the crystalline semiconductor region with an offset from a gate electrode structure defined by a second sidewall spacer formed on the first sidewall spacer. Then, the second recess extends to a second depth that is greater than the first depth. Additionally, the method comprises forming a strain inducing semiconductor alloy in the first and second recesses by performing a selective epitaxial growth process.
A further exemplary method disclosed herein includes a second gate electrode structure formed above and over a first semiconductor region having a first gate electrode structure formed thereon. Forming a first spacer layer above the semiconductor region; The method further comprises selectively forming a first sidewall spacer from the first spacer layer on the sidewall of the first gate electrode structure. Further, a first etching process is performed to form a cavity in the first semiconductor region based on the first sidewall spacer. Additionally, a second sidewall spacer is formed on the first sidewall spacer, and a second etching process is performed to increase the cavity depth based on the second sidewall spacer. Finally, a strain-inducing semiconductor alloy is formed in the cavity.
One exemplary semiconductor device disclosed herein comprises a transistor formed above a substrate, the transistor comprising a gate electrode structure formed above a crystalline semiconductor region and comprising a gate electrode material. I have. The transistor further comprises a first strain inducing semiconductor alloy formed in the crystalline semiconductor region and having a first depth and a first lateral offset from the gate electrode material. Additionally, a second strain-inducing semiconductor alloy is formed in the crystalline semiconductor region, the second strain-inducing semiconductor alloy having a second depth and a second lateral offset from the gate electrode material. Where the first and second depths are different and the first and second lateral offsets are different.
Various embodiments of the present disclosure are defined in the appended claims, and will become more apparent with the following detailed description when taken in conjunction with the accompanying drawings.
FIG. 1A is a cross-sectional view (part 1) schematically illustrating a conventional semiconductor device with a p-channel transistor during various manufacturing stages for forming a silicon / germanium alloy based on a complex conventional manufacturing sequence. FIG. 1B is a cross-sectional view (part 2) schematically illustrating a conventional semiconductor device with p-channel transistors during various stages of manufacturing to form a silicon / germanium alloy based on a complex conventional manufacturing sequence. FIG. 1C is a cross-sectional view (part 3) schematically illustrating a conventional semiconductor device with p-channel transistors during various stages of manufacturing to form a silicon / germanium alloy based on a complex conventional manufacturing sequence. FIG. 1D is a cross-sectional view (part 4) schematically illustrating a conventional semiconductor device with p-channel transistors during various stages of manufacturing to form a silicon / germanium alloy based on a complex conventional manufacturing sequence. FIG. 1E is a cross-sectional view (part 5) schematically illustrating a conventional semiconductor device with p-channel transistors during various stages of manufacturing to form a silicon / germanium alloy based on a complex conventional manufacturing sequence. FIG. 2A is a cross-sectional view (part 1) schematically illustrating a semiconductor device during various manufacturing steps for forming a strain-inducing semiconductor alloy based on a stepped cavity according to an exemplary embodiment. FIG. 2B is a cross-sectional view (part 2) schematically illustrating a semiconductor device during various manufacturing steps for forming a strain-inducing semiconductor alloy based on a stepped cavity according to an exemplary embodiment. FIG. 2C is a cross-sectional view (part 3) schematically illustrating a semiconductor device during various manufacturing steps for forming a strain-inducing semiconductor alloy based on a stepped cavity according to an exemplary embodiment. FIG. 2D is a cross-sectional view (part 4) schematically illustrating a semiconductor device during various manufacturing steps for forming a strain-inducing semiconductor alloy based on a stepped cavity according to an exemplary embodiment. FIG. 2E is a cross-sectional view (part 5) schematically illustrating a semiconductor device during various manufacturing steps for forming a strain-inducing semiconductor alloy based on a stepped cavity according to an exemplary embodiment. FIG. 2F is a cross-sectional view (part 6) schematically illustrating a semiconductor device during various manufacturing steps for forming a strain-inducing semiconductor alloy based on a stepped cavity according to an exemplary embodiment. FIG. 2G is a cross-sectional view (part 7) schematically illustrating a semiconductor device during various manufacturing steps for forming a strain-inducing semiconductor alloy based on a stepped cavity according to an exemplary embodiment. FIG. 2H is a cross-sectional view (part 1) schematically illustrating a semiconductor device in which a graded cavity can be formed based on two different epitaxial growth steps according to a further exemplary embodiment. FIG. 2I is a cross-sectional view (part 2) schematically illustrating a semiconductor device in which a graded cavity can be formed based on two different epitaxial growth steps according to a further exemplary embodiment. FIG. 2J schematically illustrates a semiconductor device during various manufacturing stages in which stepped cavities can be formed by reducing the width of the spacer structure and performing an intermediate etching process according to a further exemplary embodiment. It is a figure (the 1). FIG. 2K schematically illustrates a semiconductor device during various manufacturing stages in which a graded cavity can be formed by reducing the width of the spacer structure and performing an intermediate etching process in accordance with a further exemplary embodiment. It is a figure (the 2). FIG. 2L is a cross-sectional view schematically illustrating a semiconductor device during various manufacturing stages in which a graded cavity can be formed by reducing the width of the spacer structure and performing an intermediate etching process in accordance with a further exemplary embodiment. It is a figure (the 3). FIG. 2M schematically illustrates a semiconductor device in a further advanced manufacturing stage in which drain and source regions may be provided at least partially in a strain-inducing semiconductor alloy according to an exemplary embodiment.
The present disclosure will be described with reference to the following detailed description and the embodiments described in the drawings, which, however, limit the disclosure to certain disclosed exemplary embodiments. While not intended, the illustrative embodiments described are merely illustrative of various aspects of the disclosure, and the scope of the disclosure is defined by the appended claims. It should be understood that
In general, the present disclosure is based on an appropriate sequence for forming corresponding cavities adjacent to and offset from a gate electrode structure, so that the sophisticated lateral and longitudinal structures of the strain-inducing semiconductor alloy Describes technologies and semiconductor devices that can be achieved. The stepped shape structure of the cavities allows for a reduced lateral offset from the channel region because excessive exposure to the etching environment can be avoided by limiting the depth of the corresponding etching process While still allowing for a high degree of controllability. Thereafter, one or more further etching processes may be performed based on appropriately configured spacer elements, in which the cavity depth may be increased, but one or more additional spacer elements may be included. An increased offset can be provided, thereby reducing the impact of etch-related non-uniformities on the final transistor characteristics obtained. As a result, a reasonably large amount of strain-inducing semiconductor alloy can be formed in the cavity, where it is reduced from the channel region at height levels that are very close to the height level of the gate insulating layer. Although lateral offsets can be achieved, a high degree of controllability of the corresponding cavities and subsequent deposition processes is achieved, so that it does not cause significant device variability. Some exemplary embodiments disclosed herein also provide a high degree of flexibility in designing the overall properties of the strain-inducing semiconductor alloy, for example by providing the semiconductor alloy with different degrees of in-situ doping. Can thereby provide the possibility to adjust the desired dopant profile with great flexibility. Also, in some exemplary aspects disclosed herein, a stepped-shaped structure of the cavity can be achieved based on two or more spacer elements, which are additional elements. Since it can be formed without the need for lithographic steps, it can contribute to a highly efficient overall manufacturing process flow. In another exemplary embodiment, the stepped shape structure of the cavity can be achieved by providing a spacer structure that can be sequentially reduced in width and subsequent etching process. Which can continuously increase the depth of the exposed portion of the cavity while continuously decreasing the lateral offset from the channel region, in this case the final The etching step can be performed with a high degree of controllability based on dedicated spacer elements. In this final etching process, the required depth can also be reduced, so that again high process uniformity can be achieved. Accordingly, the present disclosure provides manufacturing techniques and semiconductor devices in which additional strain induction such as silicon / germanium alloys, silicon / germanium / tin alloys, silicon / tin alloys, silicon / carbon alloys, etc. is provided. The effect of the semiconductor alloy is 50 nm and much more because the step-wise structure of these materials and the associated manufacturing sequence can provide high process uniformity and thus reduced variation in transistor characteristics. Since even transistor elements with small critical dimensions can be enhanced, they can provide a certain degree of scalability of these performance enhancement mechanisms.
Further exemplary embodiments are described in more detail below with reference to FIGS. 2A-2M, and FIGS. 1A-1E may be referenced again if necessary.
FIG. 2A schematically shows a cross-sectional view of the semiconductor device 200, and the semiconductor device 200 may include a substrate 201 and a semiconductor layer 203 formed above the substrate 201. The substrate 201, in combination with the semiconductor layer 203, can represent any suitable device architecture, such as a bulk structure, an SOI structure, etc., as described with reference to the semiconductor device 100 shown in FIGS. 1A-1E. . For example, in the case of an SOI structure, a buried insulating layer (not shown) may be disposed between the substrate 201 and the semiconductor layer 203 as described above. The semiconductor device 200 may also include an isolation structure 204, which may isolate the first active region or semiconductor region 203A from the second active semiconductor region 203B, each of the semiconductor layers 203. The corresponding transistors 250A and 250B are formed inside and above. In the illustrated manufacturing stage, the transistors 250A and 250B may include a gate electrode structure 251. The gate electrode structure 251 may include a gate electrode material 251A and a gate insulating layer 251B, and the gate insulating layer 251B includes a gate electrode structure 251B. The electrode material 251A may be separated from the channel regions 252 of the active regions 203A and 203B, respectively. Further, the gate electrode structure 251 may include the cap layer 251 </ b> C as described above with reference to the semiconductor device 100. Further, an etch stop liner 215, such as an oxide material, may be formed on the side wall of the gate electrode material 251A, and may also be formed on the material of the active regions 203A, 203B. For example, in some exemplary embodiments, the active regions 203A, 203B may be substantially composed of a silicon material, and thus the layer 215 may be representative of a silicon dioxide material. However, it should be understood that in other cases the liner material may be deposited in the form of silicon dioxide, silicon nitride, etc., for example. In this case, the etch stop liner 215 may also be formed on the exposed surface of the cap layer 251C. In one embodiment, a spacer layer 205A made of silicon dioxide may be formed above the semiconductor region 203B and the gate electrode structure 251 of the transistor 250B. On the other hand, the spacer element 205 may be formed on the side wall of the gate electrode structure 251, that is, on the etching stop liner 215 provided thereon. The spacer element 205 may have a well-defined width 205W, which may substantially determine the lateral offset of the strain-inducing semiconductor alloy that will be formed in subsequent manufacturing steps. Excessive transistor variations in transistor 250A can be reduced by selecting an appropriate etch depth in combination with lateral width 205W, thereby reducing the overall process as described in more detail later. In some exemplary embodiments, the width 205W may be selected to be a few nanometers or less, such as approximately 2 nm or less, because uniformity can be increased.
The semiconductor device 200 shown in FIG. 2A can be formed based on the following process. The isolation structure 204 and the gate electrode structure 251 can be formed by using process techniques as previously discussed with reference to the device 100. Thereafter, if necessary, an etch stop liner 215 may be formed, for example, by oxidation, deposition, etc., followed by deposition of the spacer layer 205A, which may be accomplished by well established CVD techniques. . As already explained, corresponding further process sequences can provide enhanced uniformity in forming a gradually shaped cavity that can reduce any process-related transistor variation. Thus, the thickness of the spacer layer 205A may be selected to obtain the desired reduced width 205W. In some exemplary embodiments, the spacer layer 205A may be formed based on a silicon dioxide material using a well established deposition recipe. In other exemplary embodiments, the spacer layer 205A may be provided in the form of a different material, such as silicon nitride, and other suitable materials may be used as additional sidewalls, as will be described later. It may be used in subsequent manufacturing steps to provide spacer elements. An etch mask 206, such as a resist mask, may then be formed by lithography to expose the spacer layer 205A above the transistor 250A and cover the spacer layer 205A above the transistor 250B. After that, if the etching stop liner 215 is provided, an appropriate anisotropy is selected so as to remove the material of the spacer layer 205A selectively with respect to it or at least selectively with respect to the material of the semiconductor region 203A. An etching process may be performed, thereby providing a spacer element 205 having a width 205W.
FIG. 2B schematically illustrates the semiconductor device 200 when exposed to an etching environment 207, which uses a material of the semiconductor region 203A as a spacer to form a first recess or cavity portion 207A. There may be an anisotropic plasma assisted etching process for selective removal with respect to element 205. In the embodiment shown in FIG. 2B, the etching process 207 may be performed based on the etching mask 206, while in other exemplary embodiments, the mask 206 is removed prior to performing the etching process 207. In this case, the spacer layer 205A may be used as a mask for protecting the semiconductor region 203B and the gate electrode structure 251 of the transistor 250B. In contrast to conventional strategies, the etching process 207 can be performed for a given chemical so that a high degree of controllability and associated uniformity of the lateral offset from the channel region 252 of the recess 207A can be achieved. It should be understood that this may be performed to obtain a reduced depth of recess 207A by selecting a corresponding reduced etch time. As a result, the corresponding variation in lateral etch rate during process 207 can be reduced compared to a process strategy that requires a significant depth of the corresponding cavity, such as cavity 107A in FIG. Even for the overall reduced lateral offset defined by 205W, increased uniformity of the resulting transistor characteristics across the substrate can be achieved. Therefore, by forming the recess 207A with a reduced depth, excellent control of the lateral position of the strain-inducing material can be achieved based on a well-established selective anisotropic etching recipe.
In yet another embodiment, the etch process 207 may be performed based on a wet chemical etch recipe, where again the reduced depth of the recess 207A provides a highly controllable lateral etch rate. As a result, a corresponding clear lateral offset can be obtained based on the initial spacer thickness 205W. For example, as a result of the reduced depth of recess 207A, an isotropic wet chemical etching environment may be established, and in that etching environment, the corresponding lateral etch rate will also be sufficiently controllable. For example, while providing excellent integrity of the gate insulating layer 251B at the edge of the gate electrode structure 251, the lateral offset of the recess 207A from the channel region 252 does not compromise the uniformity of transistor characteristics. , Can be adjusted based on small values.
FIG. 2C schematically illustrates the semiconductor device 200 in a further advanced manufacturing stage. As shown, the recess 207A may be formed with a depth 207D facing down in the semiconductor region 203A, and the depth 207D may provide high overall process control as described above. Further, a further spacer layer 216 is formed above the first and second transistors 250A and 250B. Here, the spacer layer 216 may be made of a material different from that of the spacer layer 205A. For example, in one exemplary embodiment, spacer layer 216 may be composed of silicon nitride, while spacer layer 205A may be formed based on silicon dioxide. In other exemplary embodiments, as previously discussed, as long as the spacer layer 205A and the associated spacer element 205 would be formed of a material having different etch characteristics than the spacer layer 216, It should be understood that the spacer layer 216 may be composed of different materials such as silicon dioxide. The spacer layer 216 may be provided with a suitable thickness in combination with the corresponding etching process parameters to obtain a suitable thickness of the spacer element that will be formed based on the spacer layer 216. Any well established deposition technique may be used for this purpose.
FIG. 2D schematically illustrates the semiconductor device 200 during a further anisotropic etching process 211 to form a spacer element 216A on at least the spacer element 205 in the transistor 250A. For this purpose, well-established selective anisotropic etching recipes are available, where, for example, silicon nitride material can be selectively removed with respect to silicon dioxide material and silicon material. Also, in the embodiment shown in FIG. 2D, the anisotropic etch process 211 can be performed as an unmasked process, thereby also forming a corresponding spacer element 216A on the spacer layer 205A in the transistor 250B. Can do. As a result, the spacer element 216A of the transistor 250A can be provided without an additional lithography step, thereby contributing to a highly efficient overall manufacturing flow. In other exemplary embodiments, the spacer layer during the etch process 211, for example, due to less obvious etch selectivity of the process 211 and / or due to the reduced thickness of the spacer layer 205A. If material removal of 205A is deemed inappropriate, an additional etch mask, such as etch mask 206, may be formed to cover transistor 250B prior to performing etch process 211. As a result, during the etching process 211, the recess 207A formed in the semiconductor region 203A can be exposed while simultaneously the spacer element 216A can be formed with the desired width 216W. For example, to obtain the desired stepped shape of the semiconductor material that will be further formed in region 203A, while at the same time achieving a high degree of controllability of the resulting lateral shape of the cavity, A width of 216W may be selected. In addition, the required degree of material removal will be significantly lower compared to conventional strategies where the corresponding cavities would need to be formed in a single etching step, resulting in a longitudinal cavity of the resulting cavity. Direction expansion can also be controlled with increased efficiency.
FIG. 2E schematically illustrates the semiconductor device 200 when exposed to a further etching process 217, where the additional recess 217A is within the exposed portion of the previously formed recess 207A. May be formed. Thus, a lateral offset of the further recess 217A can be defined based on the process parameters of the etching environment 217 and the width 216W of the spacer element 216A, while its depth is a process for a given removal rate during the process 217. Can be adjusted based on time. In some exemplary embodiments, the recess 217A may be formed to extend to a depth 217D, which is the final desired depth of the cavity represented by the recesses 207A and 217A, for example, It may correspond to 50 to 90 percent of the thickness of the base layer 203. In this case, the depth 217D should be considered as a combination of the depth obtained between the depth of the recess 207A and the further etching process 217. The most critical effect on transistor variations will be presented by the “shallow portion”, ie, the recess 207A, which can be provided with high controllability as described above, Even if the depth 217D is significantly greater than the initially defined depth 207D, which may result in some variation in lateral offset from the channel region 252 relative to the recess 217A, the overall transistor variation It should be understood that can be significantly improved.
If desired, one or more additional spacer elements, such as spacer element 216, may be formed, for example, based on the same material, and further increase the depth of the corresponding portion of the previously formed recess. It should be understood that a subsequent etching process may be performed, and again, the lateral offset for the channel region 252 may be increased stepwise.
FIG. 2F schematically illustrates the semiconductor device 200 when exposed to a further etching environment 218 that selectively removes the spacer element 216A relative to the spacer element 205 and the spacer layer 205A. May be designed to. In other exemplary embodiments, as already described, if the process for forming the spacer element 216A in transistor 250A was performed based on a corresponding etch mask as previously discussed, Transistor 250B may be covered by spacer layer 216. In this case, the spacer layer 216 and spacer element 216A of the transistor 250A may be removed during the etching process 218. For example, if the spacer element 216A is composed of silicon nitride, a well-established etching recipe based on, for example, heated phosphoric acid may be used. In other cases, when the spacer element 216A is provided in the form of a silicon dioxide material, other suitable recipes such as dilute hydrofluoric acid (HF) may be used, while the spacer layer 205A and spacer 205 are , The integrity of the corresponding material covered by those elements can be provided. After the etching process 218, a corresponding cavity 218A that can thus be constituted by the recesses 207A, 217A is formed in the semiconductor region 203A.
FIG. 2G schematically illustrates the semiconductor device 200 in a further advanced manufacturing stage, in which the selective epitaxial growth process 210 may be performed to fill the cavities 218A with the strain-induced semiconductor alloy 209. In some exemplary embodiments, transistor 250A may represent a p-channel transistor, where the crystallographic structure of semiconductor region 203A is along the current flow direction, ie, the horizontal direction in FIG. 2G. The compressive strain component acting in this manner may be such that it can provide enhanced transistor performance as described above. Accordingly, the semiconductor alloy 209 may be provided in the form of a silicon / germanium alloy, in which case the germanium proportion may be selected according to the desired strain component to be introduced into the channel region 252. Also, the stepped shape of the cavity 218A can achieve a corresponding stepped configuration of material 209, where the shallow portion 209A can be located in close proximity to the channel region 252 while the device As already described with reference to 100, excessive transistor variations can be avoided. In other exemplary embodiments, the semiconductor alloy 209 may comprise tin, for example in combination with silicon or silicon / germanium, which can also provide a compressive strain component in the channel region 252. In yet another exemplary embodiment, transistor 250A may represent a transistor whose performance may be increased based on a tensile strain component, where the tensile strain component is a semiconductor alloy 209 in the form of a silicon / carbon alloy. Can be achieved.
During the selective epitaxial growth process 210, the spacer element 205 and the spacer layer 205A essentially avoid significant semiconductor deposition and concomitantly maintain the integrity of the gate electrode structure 251 of the transistors 250A, 250B and the semiconductor region. 203B can also act as a growth mask to maintain this.
Thereafter, further processing is continued by removing the spacer elements 205 and spacer layer 205A based on a well established etching recipe such as hydrofluoric acid if these elements are composed of silicon dioxide material. You can do it. In other cases, any other selective etch recipe may be used, for example, if the spacer 205 and spacer layer 205A are composed of silicon nitride, the heated phosphoric acid may be May be used. Thereafter, cap layer 251C may be removed by any suitable etching recipe, such as heated phosphoric acid, and then further processing may continue, as described with reference to device 100, for example, shown in FIG. 1E. It's okay. For example, drain and source extension regions (not shown) may be formed, followed by appropriate spacer structures, which are then used to define deep drain and source regions based on ion implantation. Here, the corresponding implantation process for transistor 250A can be greatly enhanced by introducing appropriate dopant species based on selective epitaxial growth process 210. Thus, in this case, the desired degree of in situ doping can be achieved during the process 210. Thereafter, if desired, a suitable annealing process may be performed to initiate some dopant diffusion and to activate the dopant and recrystallize the implantation induced damage. A metal silicide may then be formed according to device requirements.
FIG. 2H schematically illustrates a semiconductor device 200 according to a further exemplary embodiment. As shown, the spacer element 216A may still be present and the device 200 may be exposed to the first epitaxial growth process 210B to fill the first portion 209B into the recess 217A. Thus, during the epitaxial growth process 210B, desirable process parameters may be established with respect to, for example, in-situ doping, material composition, etc., to provide desirable characteristics for the lower portion 209B. For example, the degree of in-situ doping may be selected to substantially correspond to the desired dopant concentration in the deep drain and source areas for transistor 250A. Also, if desired, the concentration of strain-inducing species in alloy 209B may be adapted according to overall device requirements. For example, if a compressive strain component is desired, a reasonably high concentration of germanium, tin, etc. may be provided.
Thereafter, an etching process 218 (see FIG. 2F) may be performed to remove the spacer elements 216A from the transistors 250A, 250B, in which case the corresponding spacer elements are not formed in the transistors as described above. As previously discussed, the corresponding spacer layer may be removed from above transistor 250B. A corresponding cleaning recipe may be used to prepare the exposed surface portion of material 201B for further selective epitaxial growth processes.
FIG. 2I schematically illustrates the semiconductor device 200 when exposed to the deposition environment of a further selective epitaxial growth process 210A. Accordingly, a shallow portion 209A of the strain-inducing semiconductor alloy 209 may be formed, where, in addition to the enhanced overall surface topography of the material 209, the different properties of the material 209A are also subject to process and device requirements. Can be adjusted. For example, appropriate in-situ doping may be achieved during process 210A so that further profiling of the drain and source regions that will be further formed can be greatly mitigated or eliminated altogether. This can also contribute to a further enhanced drain-inducing effect, because the implantation-induced relaxation effect can be reduced. Further, if desired, the material composition may be selected to be different as compared to material 209B, if desired. After the epitaxial growth process 210A, further processing may continue as described above.
With reference to FIGS. 2J-2L, further exemplary embodiments are described below, in which a step-shaped cavity is formed by reducing the width of the spacer structure and performing a corresponding cavity etching process. A structure can be achieved.
FIG. 2J schematically illustrates the semiconductor device 200 in one manufacturing stage, in which a spacer element 216A may be formed at least in the transistor 250A, while the second transistor 250B includes a spacer layer 205A. Depending on the etch stop capability, a corresponding spacer layer or spacer element 216A may be provided. That is, if excessive exposure of the spacer layer 205A to more than one etching environment is deemed inappropriate, the spacer element 216A may be formed based on the corresponding resist mask, and the spacer layer may be a transistor layer. It may be maintained above 250B. Also, the spacer element 216A may be provided with a width 216T, which in combination with the width 205W of the spacer element 205 may represent a desired offset with respect to the maximum depth of the corresponding cavity. Based on the spacer element 216A, the device 200 may be exposed to the etching environment 227 to form a corresponding recess 227A. With respect to any process parameter of the etching process 227, the same criteria already described for forming the recesses 207A, 217A (see FIG. 2F) may be applied.
FIG. 2K schematically shows the semiconductor device 200 when exposed to a further etching environment 218A, in which a portion of the spacer element 216A may be removed. For example, if the spacer element 216A is composed of silicon nitride, the etching environment can be established based on heated phosphoric acid. In other cases, any other suitable etching recipe may be used. During the etching process 218A, the width of the spacer element 216A may be trimmed in a highly controllable manner, for example, as a result, a stepped shaped cavity that may include a recess 227A in the illustrated manufacturing stage. A reduced spacer element 216R may be maintained to adjust for further lateral offsets.
FIG. 2L schematically illustrates the semiconductor device 200 when exposed to a further etching environment 237, during which the depth of the recess 227A may be increased while a further recess 237A is formed at the same time. The recess 237A may have a lateral offset relative to the channel region 252 determined by the width of the spacer element 216R. Thereafter, a further etching process similar to process 218A (see FIG. 2K) may be performed to remove the spacer element 216R, thereby exposing the spacer 205, which is compared to the spacer element 216R. The obvious etch selectivity thus allows the lateral offset of the corresponding recess to be defined with a high degree of uniformity. As a result, in subsequent etching processes that may be based on etching parameters similar to process 237, shallow recesses are formed with a high degree of process uniformity and a desirable reduced offset from the channel region 252, as described above. obtain. On the other hand, the depth of corresponding recesses 227A, 237A may be further increased, while shallow recesses may be formed with a minimum desired lateral offset. Thus, in this case as well, a corresponding cavity with a step-shaped structure will be achieved, and again, a high process uniformity can provide a corresponding stable transistor characteristic. Thus, after forming the graded cavity for transistor 250A, as described above, the spacer element 205 and spacer layer 205A are removed and the graded cavity is filled with a suitable semiconductor alloy. May continue further processing.
FIG. 2M schematically illustrates the semiconductor device 200 in a further advanced manufacturing stage. As shown, the transistors 250A, 250B may include a spacer structure 253 that is designed to adjust the lateral and vertical dopant profiles of at least the drain and source regions 254 within the transistor 250B. May have been. That is, in the illustrated embodiment, the drain and source regions 254 of transistor 250B are based on an implantation sequence combined with providing spacer structures 253 to adjust the lateral and vertical profiles of region 254. And may be formed. As previously mentioned, the semiconductor alloy 209 is in situ doped because a reduced amount of dopant species may need to be incorporated by the ion implantation process, thereby reducing the stress relaxation effects of the corresponding implantation process. It may be provided as a material, thereby providing high flexibility in designing the overall dopant profile of the corresponding drain and source regions 254. In other cases, as discussed above, at least a significant concentration for the drain and source extension regions 254E may be provided based on in situ doping of at least a portion of the material 209, in which case the stepped shape of the material 209 This allows the corresponding dopant species to be located in close proximity to the channel region. Also, in some exemplary embodiments, the dopant profile of the drain and source regions 254 may be established substantially entirely based on the in-situ doping material 209, which may have different dopant concentrations as described above. You may have. In this case, if desired, the final dopant profile can be adjusted if necessary, for example based on the introduction of a counter-doping species, which typically corresponds to the corresponding implantation process. It will require a significantly reduced dose during this period, so it will not generate too much injection-induced damage. As a result, during the corresponding annealing process 219, if the corresponding pn junction is to be located “outside” of the material 209, it will eventually be initiated, for example, by initiating some dopant diffusion. While the desired dopant profile can be adjusted, in other cases, significant dopant diffusion can be suppressed by using well-established annealing techniques such as laser-based techniques, flashlight annealing processes. In this case, although the effective annealing time may be very short to suppress excessive dopant diffusion, dopant activation and recrystallization of implantation induced damage can be achieved.
Thereafter, further processing may continue, for example by forming metal silicide regions in the drain and source regions 254 and, if necessary, in the gate electrode structure 251 and then depositing any suitable interlayer dielectric material. The interlayer dielectric material may also be comprised of a high internal stress level dielectric material to further enhance the performance of transistor 250A and / or transistor 250B.
As a result, the present disclosure provides a semiconductor device and corresponding manufacturing techniques, in which a step-shaped shape of the strain-inducing semiconductor material can be provided based on a patterning sequence that includes providing two different spacer elements. Capable of providing high overall process uniformity and allowing strain-inducing materials to be placed very close to the channel region without unduly reducing overall transistor variability become.
Further modifications and variations of this disclosure will be apparent to those skilled in the art in view of this specification. Accordingly, this specification is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the disclosure. It should be understood that the form shown and described herein is to be taken as the presently preferred embodiment.
Is offset from said first gate electrode structure by a first sidewall spacer formed on the sidewalls of the first gate electrode structure, a first plurality of recesses extending to a first depth first crystalline semiconductor region Forming a first spacer layer above the first gate electrode structure and above the second gate electrode structure formed on the second crystalline semiconductor region, A first mask is formed to cover the second gate electrode structure and the first spacer layer formed above the second crystalline semiconductor region, and the first spacer layer is used to form the first spacer layer. Forming sidewall spacers and removing material from the first crystalline semiconductor region in the presence of the first sidewall spacers and the first mask ;
A second plurality of recesses that are offset from the first gate electrode structure by a second sidewall spacer formed on the first sidewall spacer and extend to a second depth that is deeper than the first depth are provided. Forming in the first crystalline semiconductor region, removing the first mask, depositing a second spacer layer, and above the second gate electrode structure and the second crystalline semiconductor. Forming a second mask above the region, and forming the second sidewall spacer from the second spacer layer in the presence of the second mask ;
The method of claim 1 , comprising forming a strain-inducing semiconductor alloy in the first and second recesses by performing a selective epitaxial growth process .
Forming the strain-inducing semiconductor alloy comprises filling the first plurality of recesses with a first portion of the strain-inducing semiconductor alloy in the presence of the first side wall spacer and the first side wall. Performing a first epitaxial growth process to fill a portion of the second plurality of recesses with a second portion of the strain-inducing semiconductor alloy in the presence of a spacer and the second sidewall spacer. the method of claim 2.
4. The method of claim 3, wherein the first portion and the second portion of the strain-inducing semiconductor alloy differ in at least the degree of in-situ doping .
The method of claim 2 , wherein the strain-inducing semiconductor alloy comprises tin .
Forming the first plurality of recesses and the second plurality of recesses includes forming a first portion of the second plurality of recesses, and forming at least a part of the second sidewall spacer. and removing, including, and forming in common a second portion and said first plurality of recesses of said second plurality of recesses, the method of claim 1.
The method of claim 1, wherein the first sidewall spacer is comprised of silicon dioxide and the second sidewall spacer is comprised of silicon nitride .
A third plurality of recesses having a leading Symbol third depth shallower than the first depth and the second depth, said first plurality of recesses or the second offset of the plurality of recesses the method of claim 1 which comprises forming a third plurality of recesses being offset from the gate electrode structure by small offset than.
9. The method of claim 8 , comprising filling the first plurality of recesses, the second plurality of recesses, and the third plurality of recesses with a semiconductor alloy.
JP2011542724A 2008-12-31 2009-12-29 Transistor with embedded strain-inducing material having a step-shaped structure Active JP5795260B2 (en)
JP2012514317A JP2012514317A (en) 2012-06-21
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JP2011542724A Active JP5795260B2 (en) 2008-12-31 2009-12-29 Transistor with embedded strain-inducing material having a step-shaped structure
JP2006019727A (en) 2006-01-19 Strained p-type metal oxide semiconductor field effect transistor (mosfet) structure having slanted, incorporated silicon-germanium source-drain and/or extension, and manufacturing method for the same
US20090130803A1 (en) 2009-05-21 Stressed field effect transistor and methods for its fabrication
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