Source: http://www.google.com/patents/US7978753?ie=ISO-8859-1&dq=2040248
Timestamp: 2015-03-27 13:01:24
Document Index: 595838299

Matched Legal Cases: ['Application No. 60', 'Application No. 99', 'Application No. 04022871', 'Application No. 2000', 'Application No. 23409', 'Application No. 23409', 'Application No. 2', 'Application No. 2357551', 'Application No. 2000', 'Application No. 2000', 'Application No. 2008', 'Application No. 2008', 'Application No. 2357551', 'Application No. 2', 'Application No. 2', 'Application No. 2']

Patent US7978753 - Multicarrier transmission system with low power sleep mode and rapid-on ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA multicarrier transceiver is provided with a sleep mode in which it idles with reduced power consumption when it is not needed to transmit or receive data. The full transmission and reception capabilities of the transceiver are quickly restored when needed, without requiring the full (and time-consuming)...http://www.google.com/patents/US7978753?utm_source=gb-gplus-sharePatent US7978753 - Multicarrier transmission system with low power sleep mode and rapid-on capabilityAdvanced Patent SearchPublication numberUS7978753 B2Publication typeGrantApplication numberUS 12/615,946Publication dateJul 12, 2011Filing dateNov 10, 2009Priority dateJan 26, 1998Fee statusPaidAlso published asUS7697598, US8437382, US8611404, US8750352, US20040160906, US20050185726, US20060078060, US20060233273, US20100054312, US20110235691, US20130243051, US20140086287, US20140286379Publication number12615946, 615946, US 7978753 B2, US 7978753B2, US-B2-7978753, US7978753 B2, US7978753B2InventorsJohn A. Greszczuk, Richard W. Gross, Halil Padir, Michael A. TzannesOriginal AssigneeAware, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (44), Non-Patent Citations (33), Referenced by (3), Classifications (15), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMulticarrier transmission system with low power sleep mode and rapid-on capability
US 7978753 B2Abstract
1. A multicarrier transceiver having a sleep mode capability, comprising
A. means responsive to a sleep mode command for:
(1) storing selected state parameters characteristic of the communications channel over which the transceiver is operating; and
(2) reducing power to selected portions of transceiver circuitry;
B. means responsive to a wake-up command for:
(1) restoring power to said transceiver;
(2) restoring the state of said transceiver from said sleep mode by means of said stored parameters; and
C. means for maintaining a common, synchronized data frame count between said transceiver and a remote transceiver with which it communicates, to thereby facilitate restoration of communication without reinitialization of said transceiver, wherein the state parameters include one or more parameters selected from the group comprising frequency-domain equalizer coefficients, time-domain equalizer coefficients, echo canceller coefficients, bit allocations, coding parameters, fine gains, and subchannel gains.
2. A multicarrier transceiver according to claim 1 in which the means for maintaining said frame count comprises a signal defining a timing reference during at least the time when said first transceiver is in sleep mode.
3. A multicarrier transceiver according to claim 2 in which said signal comprises a pilot tone transmitted from one transceiver to another with which it is in communication.
4. A multicarrier transceiver according to claim 3 in which said pilot tone is transmitted between said transceivers during both normal operation and reduced power operation.
5. A multicarrier transceiver according to claim 1 in which maintaining synchronization includes maintaining synchronization of frame counters between said transceivers.
6. A multi carrier transceiver according to claim 5 in which maintaining synchronization further includes maintaining synchronization of the phase of a synchronizing signal transmitted between said transceivers.
7. A multicarrier transceiver according to claim 1 including means to transmit an idle symbol to said remote transceiver when said transceiver is in sleep mode.
8. A multicarrier transceiver according to claim 1 including means to transmit to said remote transceiver a short test signal on awaking from sleep mode in order to determine whether transmission conditions have changed sufficiently during sleep mode to require reinitialization of said transceiver on emerging from sleep mode.
9. A method of providing a sleep mode in a multicarrier transceiver characterized by a plurality of state parameters characteristic of the communications channel over which the transceiver is operating and requiring initialization of said parameters for normal communications, comprising the steps of:
A. storing selected ones of said state parameters in response to a sleep mode command;
B. reducing power to selected portions of the circuitry following said storing;
C. restoring power to said selected portions in response to an awaken signal; and
D. restoring the state of said transceiver from said stored parameters in response to said wakeup signal to thereby obviate reinitialization of said transceiver, wherein the state parameters include one or more parameters selected from the group comprising frequency-domain equalizer coefficients, time-domain equalizer coefficients, echo canceller coefficients, bit allocations, coding parameters, fine gains, and subchannel gains.
10. A method according to claim 9 including the step of maintaining synchronization in said transceiver with a synchronization signal transmitted to said transceiver during the time that said transceiver is in sleep mode. Description
This application is a continuation of application Ser. No. 11/425,507 filed Jun. 21, 2006, which is a continuation of application Ser. No. 11/289,516 filed Nov. 30, 2005, which is a continuation of application Ser. No. 11/090,183 filed Mar. 28, 2005, which is a continuation of application Ser. No. 10/778,083 filed Feb. 17, 2004, which is a continuation of application Ser. No. 10/175,815 filed Jun. 21, 2002, which is a continuation of application Ser. No. 09/581,400 filed Jun. 13, 2000 now U.S. Pat. No. 6,445,730 which is a 371 of International Application No. PCT/US99/01539 filed Jan. 26, 1999, which claims benefit of and priority to U.S. Application No. 60/072,447 filed Jan. 26, 1998 entitled �Multicarrier Transmission System with a Low Power Sleep Mode and with Instant-On Capability� each of which are incorporated herein by reference in their entirety.
Multicarrier transmission systems provide high speed data links between communication points. Such systems have recently been introduced for communications over the local subscriber loop that connects a telephone service subscriber to a central telephone office; in this important application they are commonly referred to as �xDSL� systems, where the �x� specifies a particular variant of DSL (digital subscriber loop) communications, e.g., ADSL (asynchronous digital subscriber loop), HDSL (High-Speed Digital Subscriber Loop), etc. These will be referred to generically herein simply as �DSL� systems.
In such systems, a pair of transceivers communicate with other by dividing the overall bandwidth of the channel interconnecting the subscriber and the central office into a large number of separate subchannels, each of limited bandwidth, operating in parallel with each other. For example, one common system divides three subscriber line channel into two hundred and fifty six subchannels, each of 4.3 kilohertz bandwidth. A first group of these (e.g., one hundred ninety six) is allocated to communications from the central office to the subscriber (this is known as the �downstream� direction); a second group (e.g., thirty-two) is allocated to communications from the subscriber to the central office (this is known as the �upstream� direction). The remaining subchannels are allocated to administrative, overhead and control (AOC) functions.
Data to be communicated over the link is divided into groups of bits, one group for each subchannel. The group of bits allocated to a given subchannel is modulated onto a carrier whose frequency is specific to that channel. Typically, quadrature amplitude modulation (QAM) is used for this purpose, and the group of bits is mapped into a vector defined by one of the points of a �constellation� which specifies the allowable data points for transmission over that subchannel at a particular time. Each vector or data point thus comprises a unique symbol representing a specific bit configuration for transmission as a group over its associated subchannel. During the time period allocated for transmission of a symbol (commonly referred to as a �symbol period� or �frame�), each subchannel transmits its symbol in parallel with all other subchannels so that large amounts of data can be transmitted during each frame.
The problem of signal impairment is especially serious in those xDSL configurations which carry the DSL communications on a common line with ordinary voice communications but which omit the use of a �splitter� at either the subscriber premises the central office or both. A �splitter� is basically a filter which separates the low-frequency voice communications (e.g., from zero to four kilohertz) from the higher frequency data communications (which may extend up into the megahertz band) and provides a strong degree of isolation between the two. In the absence of a splitter, unique provisions must be made to accommodate voice and data communications on the same line. For a more detailed description of the problem and its solution, see the co-pending application of Richard Gross et al. entitled �Splitterless Multicarrier Modem�, Serial No. PCT/US98 21442, filed Oct. 9, 1998, and assigned to the assignee of the present invention, the disclosure of which is incorporated herein by reference.
Because of their extensive use in Internet communications as well as in other applications, DSL transceivers are commonly maintained in the �on� state, ready to transmit or receive once they have been installed and initialized. Thus, such modems consume a significant amount of power, even when they are not actively transmitting or receiving data. It is generally desirable to limit this power consumption, both for environmental reasons as well as to prolong the life of the equipment. Further, such modems may be implemented or incorporated in part or in whole in computer equipment such as in personal computers for home and business use, and such computers increasingly incorporate power conservation procedures. See, for example, U.S. Pat. No. 5,428,790, �Computer Power Management System�, issued Jun. 27, 1995 on the application of L. D. Harper. Thus, it is desirable to provide an ADSL modem which can accommodate power conservation procedures in equipment with which it is associated, as well as independently of such equipment as may be appropriate.
Because of the complexity of DSL transceivers, and the conditions under which they must operate, it is necessary to initialize them prior to the transmission and reception of data. This initialization includes, inter alia, channel corrections such as �training� the frequency-domain and time-domain equalizers and the echo cancellers; setting the channel gains; negotiating the transmission and reception data rates; adjusting the fine gains on the subchannels over which communication is to take place; setting the coding parameters; and the like. Additionally, it includes measuring the signal-to-noise ratio of each of the subchannels, calculating the bit-allocation tables characteristic of each under given conditions of transmission, and exchanging these tables with other modems with a given modem communicates. For more detailed discussion of these procedures, refer to the application of Richard Gross et al., cited above and incorporated herein by reference. These procedures can require from seconds to tens of seconds. In a new installation, the time required is inconsequential. However, in an already-operating installation, the time required to initialize or re-initialize the system after a suspension of operation in connection with power conservation is generally unacceptable, since it is typically desired to have the modem respond to request for service nearly instantaneously.
For purposes of explanation, the present invention will be described in the context of an ADSL system having a first transceiver located at the site of a customer's premises (referred to hereinafter as the �CPE transceiver�) and a second transceiver located at a local central telephone office (hereinafter referred to as the �CO transceiver�). The two are interconnected for communication by means of a common telephone line over which voice and data are to be transmitted, and the CO transceiver is commonly connected into a broader network such as the Internet to and from which data is to be communicated. The system will be described as using Fourier transform technology for modulation and demodulation of the data to be transmitted. It will be understood, however, that the invention is not limited to this environment, and is applicable to point-to-point communications is other environments, and with other forms of modulation/demodulation. Further, since the CPE transceiver and CO transceiver are very similar, the invention will be explained in connection with a detailed illustration of the CPE transceiver only.
In FIG. 1, a DSL transceiver 10 in accordance with the present invention has a transmitter section 12 for transmitting data over a digital subscriber line 14 and a receiver section 16 for receiving data from the line. The transmitter section 12 is formed from an input buffer and converter (IBC) 18 that receives a serial string of data (e.g., binary digits) bi to be transmitted and converts the data into a plurality of pairs of complex-valued symbols Xi and their conjugates XN-i=X*i, i=0, 1, . . . N. Typically, the buffer 18 holds at least a frame of data (a frame comprising the amount of data to be transmitted during one symbol period). The pairs of symbols Xi and X*i are applied to an Inverse Fast Fourier Transform (IFFT) 20 to provide real time output signals Xj, j=0, 1, . . . N/2−1. The latter in turn are converted to serial form in a parallel-to-serial convener (PSC) 22 and then applied to a digital-to-analog converter (DAC) 24 for application to a line driver 26. The converter 24 may apply a cyclic prefix to the signals Xj to combat intersymbol interference caused by the transmission medium. The driver 26 may incorporate a gain control section (GC) 26 a for controlling the signal amplitude (and thus power) as it is applied to a communication channel such as the digital subscriber line 14.
A Frame Counter (FC) 24 connected to the controller 32 maintains a count of the number of frames of data transmitted from or received by the transceiver 10. The clock 30 maintains the count in counter 34 synchronous with that of a corresponding counter (not shown) in the CO transceiver. In DSL systems, typically, data is communicated in the form of a sequence of data frames (e.g., sixty-eight frames for ADSL as specified in ITU Document G.992.2), followed by a synchronization frame, each frame having a duration of one symbol period of approximately two hundred and fifty microseconds. Together, the sixty-nine frames comprise a �superframe�. Thus, the counter 34 typically maintains a count modulo sixty-nine. Finally, a State Memory (SM) 36 connected to the controller 32 records the state of the transceiver for reasons discussed more fully below.
Turning now to the receiver section 16, it is formed from a line conditioner 50; an analog-to-digital converter (ADC) 52; a serial-to-parallel converter 54; a Fast Fourier Transform (FFT) section 56; a decoder 58; and a parallel-to-serial converter 60. The conditioner 50 compensates for transmission distortions introduced by the line 14, and commonly includes a frequency-domain equalizer (FDQ) 50 a; a time-domain equalizer (TDQ) 50 b; and an echo canceller (EC) 50 c, among other elements. The ADC 52 converts the received signal to digital form and applies it to the serial-to-parallel converter 54. The converter 54 removes any cyclic prefix that may have been appended to the signal before it was transmitted, and applies the resultant signal to the FFT 56 which effectively �demodulates� the received signal. The output of the FFT is applied to decoder 58 which, in conjunction with a bit-allocation-table 62, recovers the symbols Xi and Xi and the bits associated with them. The output of detector 58 is applied to the parallel-to-serial converter 60 which restores the data stream, bi, that was originally applied to the transmitter. The controller 32 also controls the operation of the receiver portion 16 of the transceiver 10.
In the sleep mode, the FFT 56 is preferably dormant. Accordingly, the timing reference signal for PLL 62 is provided from the output of the analog to digital convener 52 via a detector 64 which extracts the timing signal from the signal appearing on line 14 during sleep mode, by calculating the DFT of the synchronizing pilot tone. Controller 32 controls the switching of the input to PLL 62 between these two sources so that the PLL remains locked to the CO transceiver timing reference.
As noted earlier, the transceiver of the present invention will commonly be incorporated in a computer such as a personal computer; indeed, it may be implemented as an integral part of such a computer, which may have a power conservation capability for activation when the computer is not in active operation. It is thus desirable that the transceiver be able to suspend operations and enter a �sleep� mode in which it consumes reduced power when it is not needed for data transmission or reception, but nonetheless be able to resume transmission or reception almost instantaneously, e.g., within a few frames.
Further, when the ADSL transceiver is implemented as an integral part of a computer, it may often be the case that the processing power of the computer is, at a given moment, devoted to another task such as graphics, word processing, and the like, and is thus unable to service the transceiver. In such circumstances, it is possible that a frame that is assembled for transmission to the CO transceiver, and thence to some network connected to it, is incomplete, and thus would generate errors if transmitted. Accordingly, the transceiver of the present invention is responsive to such conditions by entering an �idle� state in which it ceases active transmission of data while the computer is elsewhere occupied. This state is similar in many ways to the sleep mode state although, of course, its purpose is not power conservation, and thus in the idle state the power to selected portions of the transceiver may, but need not, be reduced. The idle state maintains synchronous signaling between the CPE and CO transceivers but no data is transmitted. On receipt of the idle indicator from the CPE, the CO transceiver transmits idle cells to the network to maintain connection with the network.
Considering for the moment the first two cases, the CPE transceiver responds to the indication by transmitting to the CO transceiver an �Intend To Enter Sleep Mode� notification (step 82). This notification indicates that the transceiver is about to undergo a change of state, and may take any of a variety of forms; preferably it is a message, but may also comprise a tone, an inverted sync signal, a flag, or even the cessation of data transmission itself. The notification may advantageously be transmitted over one of the embedded operations channels of the system. It provides the CO transceiver an opportunity to prepare itself to enter sleep mode, and also to signal the CPE transceiver if entrance into sleep mode is not appropriate or desirable at the particular moment.
If entrance into sleep mode is permissible at this time; the CO transceiver responds to the power down or idle signal by transmitting an �Acknowledge Sleep Mode� notification (step 84) to the CPE transceiver. This and subsequent notifications described in connection with the sleep or idle mode may similarly take any of a variety of forms such as described above for the �Intend To Enter Sleep Mode� notification, but again preferably is in the form of a message transmitted over an embedded operations channel.
After it has received acknowledgment from the CO transceiver, the CPE transceiver transmits an �Entering Sleep Mode� notification (step 86) to the CO transceiver and ceases transmission, either immediately or after a given number of frames. The CO transceiver detects this notification; transmits its own �Entering Sleep Mode� notification (step 88); and enters sleep mode (step 90). In pursuance of this, the CO transceiver stores its state in its own state memory corresponding to the state memory 38 of CPE transceiver 10. The state of the CO or CPE transceivers preferably includes at least the frequency and time-domain equalizer coefficients (FDQ; TDQ) and the echo-canceller coefficients (ECC) of its receiver portion and the gain of its transmitter portion; the transmission and reception data rates; the transmission and reception coding parameters; the-transmission fine gains; and the Bit Allocation Tables. The CO transceiver continues to advance the frame count and superframe count during the period of power-down in order to ensure synchrony with the remote CPE transceiver when communications are resumed. In order to maintain synchronization during the power down or idle state, the CO transceiver continues to transmit to the CPE transceiver the synchronizing pilot tone 62 a. It may, at this time, perform its own power reduction. In particular, it may reduce or cut off power to the digital modulator/demodulator portions of its transmitter and receiver sections (corresponding to the IFFT 20 and FFT 56 of the CPE transceiver, FIG. 1); this provides a significant power reduction. Further, it may reduce power to parts of the analog circuitry. Power will be maintained, of course, to at least that portion of the analog driver circuitry which transmits the pilot tone and other control signals to the CPE transceiver, and to line circuits required to monitor the line 14 for signals from the CPE transceiver.
In a central office, the rest of the equipment is still operating, and while the link between the CO transceiver and the CPE transceiver is in a sleep state, user data provided by the CO transceiver will be benign idle data such as ATM Idle-Cells or HDLC Flag octets, and not generate false data errors to other equipment.
In response to the �Entering Sleep Mode� notification from the CO transceiver, the CPE transceiver enters the sleep mode (step 92). In particular, it stores its state (step 94) in state memory 38; as noted above in connection with the CO transceiver, this includes preferably at least the frequency and time-domain equalizer coefficients (FDQ; TDQ) and the echo-canceller coefficients (ECC) of its receiver and the gain of its transmitter; the transmission and reception data rates; the transmission and reception coding parameters; the transmission fine gains; and the Bit Allocation Tables. The phase and frequency offset of the phase-locked loop 62 is maintained by continued operation of the loop. The CPE transceiver 10 then reduces power to the digital modulator/demodulator circuitry comprising IFFT 20 and FFT 56, as well as to and transmitter data line drivers 26. However, it continues to advance the frame counter 34 in accordance with the received synchronizing signal 62 a. However, the CPE controller 32 now causes this signal to be applied to the PLL 62 from the output of the ADC 52 (FIG. 1) via the detector 64, which implements the DFT of a single tone, instead of directly from the output of the FFT 56 as was previously the case. This enables the FFT 56 to be powered down. The CPE and CO transceivers then operate in sleep mode (steps 95 and 97, respectively) until they awaken.
During the sleep mode state, the CO transceiver continues to monitor (step 90) the data subscriber line 14 for an �Exiting Sleep Mode� signal from the CPE transceiver (step 96). The CPE transceiver transmits this signal when its controller receives an �Awaken� indication (step 98) from an external source such as a computer in which it is installed or from other sources, or when its controller detects the presence of new data in the input buffer 18. In response to the �Awaken� signal, the CPE transceiver retrieves its stored state from the state memory 38; restores full power to its circuitry; and restores the output of the FFT 56 to the input of the PLL 62 (step 96). The CO transceiver, on detecting the �Exit Sleep Mode� notification from the CPE transceiver (step 99), thereupon exits sleep mode by restoring its state and restoring power. On waking up from sleep mode, the CPE transceiver can begin transmitting immediately or after only a few frames delay, since it need not repeat the initialization that was earlier required to establish the requisite parameters (e.g., frequency and time-domain equalizer coefficients (FDQ; TDQ, echo-canceller coefficients (ECC), transmitter gains; transmission and reception data rates; transmission and reception coding parameters; transmission fine gains; and Bit Allocation Tables) required for reliable communications. The same is true for the CO transceiver.
The present invention enables rapid resumption of transmissions, whether recovering from a power down or from an enforced idle condition due to temporary unavailability of processor resources in the case of an embedded transceiver, i.e., a transceiver implemented largely software and sharing CPU processing power with the other applications which may from time to time divert CPU resources from the transceiver. In particular, the transceiver of the present invention is capable of recovering full data transmission capabilities within a period of a few frames.
It should also be understood that it is possible, and in various circumstances may be desirable, to operate in a �partial� sleep mode, in which only part of each transceiver is powered down. For example, where data transfer is one-way (when, for example, receiving video at the CPE transceiver from the CO transceiver without any upstream data being sent in return to the CO), the CO receiver and the CPE transmitter may operate in the sleep mode, while the CO transmitter and the CPE receiver are operating in full power mode.
In normal operation, the CPU passes data and control signals to the ITU 200 via the bus interface unit 204. Data from the CPU that is to be transmitted over the line 14 is stored in the buffer 206 and passed through the digital-to-analog converter portion of unit 208 for application to the line 214 through the analog front end. Conversely, data that is received from the line 14 is passed through the digital-to-analog converter portion of unit 208 to the buffer 206 and thence to the CPU 202 via the interface 204. The CPU processes the data flowing in the different directions in the manner illustrated in connection with FIG. 1, i.e., it performs the requisite IFFT and FFT transforms on the data as appropriate. The idle indicator generator may be inactive in this state.
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No. 11/289,516 mailed Mar. 27, 2006.33Series G: Transmission Systems and Media, Digital Systems and Networks, "Spitterless Asymmetric Digital Subscriber Line (ADSL) transceivers," ITU-T G.992.2, International Telecommunication Union, Jun. 1999.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8437382Jun 3, 2011May 7, 2013Tq Delta, LlcMulticarrier transmission system with low power sleep mode and rapid-on capabilityUS8611404May 6, 2013Dec 17, 2013Tq Delta, LlcMulticarrier transmission system with low power sleep mode and rapid-on capabilityUS8750352Nov 27, 2013Jun 10, 2014Tq Delta, LlcMulticarrier transmission system with low power sleep mode and rapid-on capabilityClassifications U.S. Classification375/219International ClassificationH04L5/16, H04K1/10, H04M11/06Cooperative ClassificationH04W52/0241, H04L12/40169, H04W52/0235, H04L12/40006, Y02B60/50, H04M11/06, H04L27/2601European ClassificationH04L12/40A, H04W52/02T4G, H04W52/02T4C, H04M11/06Legal EventsDateCodeEventDescriptionSep 10, 2014FPAYFee paymentYear of fee payment: 4Oct 18, 2012ASAssignmentOwner name: TQ DELTA, LLC, TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AWARE, INC.;REEL/FRAME:029154/0937Effective date: 20120920RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services