Source: https://patents.google.com/patent/US9281969B2/en
Timestamp: 2020-01-26 14:06:06
Document Index: 73395279

Matched Legal Cases: ['Application No. 201180007515', 'Application No. 201280025948', 'Application No. 201180007515', 'Application No. 201280025948', 'Application No. 201180007515', 'Application No. 11742641', 'Application No. 12803660', 'Application No. 12804105', 'Application No. 2012', 'Application No. 2012', 'Application No. 101123341']

US9281969B2 - Configurable multi-dimensional driver and receiver - Google Patents
US9281969B2
US9281969B2 US14/300,166 US201414300166A US9281969B2 US 9281969 B2 US9281969 B2 US 9281969B2 US 201414300166 A US201414300166 A US 201414300166A US 9281969 B2 US9281969 B2 US 9281969B2
US14/300,166
US20140286388A1 (en
2014-06-09 Application filed by Lattice Semiconductor Corp filed Critical Lattice Semiconductor Corp
2014-06-09 Priority to US14/300,166 priority patent/US9281969B2/en
2014-09-25 Publication of US20140286388A1 publication Critical patent/US20140286388A1/en
2015-03-10 Assigned to SILICON IMAGE, INC. reassignment SILICON IMAGE, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GONDI, SRIKANTH, ISAAC, ROGER
2016-03-08 Publication of US9281969B2 publication Critical patent/US9281969B2/en
This application is a divisional application of U.S. patent application Ser. No. 13/174,616 filed on Jun. 30, 2011, the contents of which are incorporated by reference herein.
FIG. 6 illustrates an embodiment of a reflection cancellation block of a driver. In some embodiments, to provide reflection cancellation, each of the N units in a slice may be further divided into L units, as illustrated in reflection cancellation block 680 of FIG. 6. As used herein, the L units may be referred to as “sub-units”. In this illustration, a first sub-unit of the L sub-units includes a first transistor (M111) 612 with a first terminal coupled with supply voltage VDD and a second terminal coupled with a first end of a first resistor (R111) 614. A second end of R111 614 is coupled with a first end of a second resistor (R112) 616 and to the communication channel. A second end of R112 616 is coupled with a first terminal of second transistor (M112) 618, where a second terminal of M112 618 is coupled with ground. An input data signal sample from one of a plurality of elements of a predriver 605 is received at the gates of M11 and M12. Further, each additional sub-unit of the reflection cancellation block 680 contains elements constructed in the same manner, such as an (L−1)th sub-unit comprising a first transistor (M121) 622, a first resistor (R121) 624, a second resistor (R122) 626, and a second transistor (M122) 628, and continuing through an Lth sub-unit comprising a first transistor (M131) 632, a first resistor (R131) 634, a second resistor (R132) 636, and a second transistor (M132) 638. The values of the elements reflect the existence of N slices containing M elements, each containing L sub-units, with a transistor gate width of W/(M*N *L) and a resistance of R*N*M*L ohms.
In some embodiments, a time adjustment block, such as a DLL (delay locked loop)/phase interpolation unit 602, may be used to provide precise control of the timing necessary for canceling reflective components. As illustrated, phases clk1, clk2, and continuing to clk1 from the DLL/phase interpolator unit 602 may be used to control the timing of the signals coming from the elements of the pre-driver 605. In some embodiments, the phase difference between each of these phases (clk1, clk2, . . . , clk1) may be in the order of multiples of tf, the time of flight across the channel.
In some embodiments, the driver 900 is coupled with a first end of a channel (CHAN) 960, where a receiver (RX) 962 is connected to a second end of CHAN. In some embodiments, an output of RX is coupled with a reference voltage selection block 964, which receives a plurality of voltages (Vref1 through VrefN) and provides a selected voltage as a second input of RX 962. RX 962 and Vref selection block are further coupled with a backchannel (BCHAN) 970. Data received from the back channel is received by a calibration logic block 974, which provides phase codes from a calibration phase. In some embodiments, an apparatus includes a DLL 978 and phase interpolators 976 (such as elements of DLL/phase interpolator unit 602 illustrated in FIG. 6). In some embodiments, the DLL 978 provides quadrature clock elements clki, clkq, clki_bar, and clkq_bar to phase interpolators 976, which also received the phase codes from the calibration logic and which generates the delayed sample clock signals Clk1, C1k2, and continuing through ClkL and generates a forwarded clock signal, where the forward clock signal is transferred via a forward clock channel (FCCHAN) 972 for clocking of RX 962.
In some embodiments, the receiving apparatus 1065 further includes a reflection cancellation block 1080, the reflection cancellation block including a second plurality of flip-flops or latches connected in a series coupled with the output of RX 1070, shown as a first reflection flip-flop (FFRef1) 1083, a second flip-flop (FFRef2) 1084, and continuing through an L-th reflection flip-flop (FFRef1) 1085. In some embodiments, each of the reflection flip-flops 1083-1085 receives a separate delayed clock signal, illustrated as FFRef1 1083 receiving clk1, FFRef2 1084 receiving clk2, and continuing FFRefL 1085 receiving clkL. In some embodiments, a sampled output of each of the first plurality of flip-flops and each of the second plurality of flip-flops is summed by a summing block or other element 1090, the resulting sum being provided as a second input of RX 1070.
In some embodiments, the reflection cancellation block 1080 further includes an eye monitor 1081 receiving an output of the receiver 1070 to monitor the eye output. The eye monitor 1081 is coupled with calibration logic block 1082, which provides phase codes. In some embodiments, an apparatus includes a DLL 1086 and phase interpolators 1087 (such as elements of DLL/phase interpolator unit 602 illustrated in FIG. 6). In some embodiments, the DLL 1086 provides quadrature clock elements clki, clkq, clki_bar, and clkq_bar to phase interpolators 1087, which also received the phase codes from the calibration logic block 1082 and which generates the delayed sample clock signals clk1, clk2, and continuing through clkL
1. A reflection cancellation apparatus comprising:
a predriver including a plurality of elements, each of the plurality of elements to receive one of a plurality of clock signals and to provide a data sample delayed by a time determined by the respective clock signal;
a plurality of circuit units each coupled to receive a data signal sample from a respective one of the plurality of elements of the predriver, and each of the plurality of circuit units coupled at an output node to output an output signal to an communication channel; and
a time adjustment unit to generate the plurality of clock signals and to adjust timing of the plurality of clock signals to at least partially cancels noise in the output signal caused by a signal reflection from the communication channel, wherein the plurality of clock signals have phase differences that respectively correspond to different multiples of an expected time of flight across the communication channel.
2. The reflection cancellation apparatus of claim 1, wherein each of the plurality of circuit units comprises:
a first transistor, a first terminal of the first transistor being coupled with a supply voltage;
a first resistor, a first end of the first resistor being coupled with a second terminal of the first transistor and a second end of the first resistor being coupled with the output node;
a second transistor, a first terminal of the second transistor being coupled with ground; and
a second resistor, a first end of the second resistor being coupled with a second terminal of the second transistor and a second end of the second resistor being coupled with the output node.
3. The reflection cancellation apparatus of claim 1, wherein the time adjustment unit includes:
a delayed lock loop element to receive a clock signal and generate a plurality of phase-adjusted clock signals; and
a phase interpolator element coupled with the delayed lock loop element to receive the plurality of phase-adjusted clock signals, the phase interpolator element to receive data signal phase codes from calibration logic and generate the plurality of clocks signals based on the plurality of phase-adjusted clocks signals and the phase codes.
4. The reflection cancellation apparatus of claim 3, further comprising:
calibration logic to generate the phase codes based on feedback from a receiver.
5. A method for canceling a reflection from a communication channel coupled to a driver circuit, the method comprising:
generating a plurality of clock signals, wherein the plurality of clock signals have phase differences that respectively correspond to different multiples of an expected time of flight across the communication channel;
delaying a plurality data samples by different delay times, the different delay times each corresponding to one of the plurality of clock signals;
generating an output signal based on the plurality of delayed samples each having different delay times; and
adjusting the different delay times applied to the plurality of data samples such that a signal reflection from transmitting the output signal over the channel is at least partially canceled.
6. The method of claim 5, wherein the generating the plurality of clock signals comprises:
receiving a clock signal and generate a plurality of phase-adjusted clock signals; and
receiving data signal phase codes from calibration logic; and
generating the plurality of clocks signals based on the plurality of phase-adjusted clocks signals and the data signal phase codes.
generating the phase codes based on feedback from a receiver.
a first device coupled with the communication channel, the first device including a driver apparatus to drive data signals on the communication channel, the driver apparatus comprising:
a plurality of circuit units each coupled to receive a data signal sample from a respective one of the plurality of elements of the predriver, and each of the plurality of circuit units coupled at an output node to output an output signal to the communication channel; and
a time adjustment unit to generate the plurality of clock signals and to adjust timing of the plurality of clock signals to at least partially cancels noise in the output signal caused by a signal reflection from the communication channel, wherein the plurality of clock signals have phase differences that respectively correspond to different multiples of an expected time of flight across the communication channel;
a second device coupled with the communication channel, the second device including a receiver to receive the output signal from the communication channel.
9. The communication system of claim 8, wherein each of the plurality of circuit units comprises:
10. The communication system of claim 8, wherein the time adjustment unit includes:
11. The communication system of claim 10, wherein the driver circuit further comprises:
calibration logic to generate the phase codes based on feedback from the receiver.
12. The communication system of claim 8, wherein the second device further comprises:
a reference voltage selection block coupled to an receive an output of the receiver and to provide one of a plurality of reference voltages as a second input to the receiver.
US14/300,166 2011-06-30 2014-06-09 Configurable multi-dimensional driver and receiver Active US9281969B2 (en)
US13/174,616 Division US8760188B2 (en) 2011-06-30 2011-06-30 Configurable multi-dimensional driver and receiver
US20140286388A1 US20140286388A1 (en) 2014-09-25
US9281969B2 true US9281969B2 (en) 2016-03-08
KR102032854B1 (en) * 2012-12-20 2019-10-16 에스케이하이닉스 주식회사 Signal transfer circuit
CN1105974C (en) 1994-12-19 2003-04-16 三星电子株式会社 Data transmission device
US20030218477A1 (en) 2002-05-24 2003-11-27 Samsung Electronics Co., Ltd. Circuit and method for controlling on-die signal termination
CN1538703A (en) 2003-02-26 2004-10-20 三星电子株式会社 Hybrid-type data transmission appartus andmethod for high performance wireless LAN
US20050007145A1 (en) 2003-07-10 2005-01-13 International Business Machines Corporation Thevenins receiver
US7032058B2 (en) * 1999-10-19 2006-04-18 Rambus Inc. Apparatus and method for topography dependent signaling
US7046056B2 (en) * 2002-03-22 2006-05-16 Rambus Inc. System with dual rail regulated locked loop
CN1959801A (en) 2005-11-10 2007-05-09 威盛电子股份有限公司 Dual-function drivers
US20070127614A1 (en) * 2005-12-07 2007-06-07 Nec Electronics Corporation Communication device
US7345602B2 (en) * 2005-07-28 2008-03-18 Nec Electronics Corporation Pre-emphasis circuit
US20080284466A1 (en) 2007-05-18 2008-11-20 Cranford Jr Hayden Clavie Driver Circuit
US7493095B2 (en) * 2003-09-11 2009-02-17 Xilinx, Inc. PMA RX in coarse loop for high speed sampling
US20090125260A1 (en) 2007-11-08 2009-05-14 Siemens Aktiengesellschaft Method and device for performing a frequency analysis of an ac voltage signal, in particular on a power grid
JP2009225406A (en) 2008-03-19 2009-10-01 Seiko Epson Corp Integrated circuit device, electro-optical device and electronic device
WO2009125260A1 (en) 2008-04-11 2009-10-15 Thinklogical Inc. Multirate transmission system for parallel input data
TWI333658B (en) 2003-02-10 2010-11-21 Samsung Electronics Co Ltd Method of driving transistor and shift register performing the same
US7840727B2 (en) * 2005-07-28 2010-11-23 Nec Electronics Corporation Serial-to-parallel conversion/parallel-to-serial conversion/ FIFO unified circuit
TWI335013B (en) 2005-03-28 2010-12-21 Seiko Epson Corp Display driver and electronic instrument
US7916560B2 (en) * 2007-07-12 2011-03-29 Hynix Semiconductor Inc. Semiconductor memory device
CN102075462A (en) 2009-09-29 2011-05-25 雷凌科技股份有限公司 Multimode Ethernet line driver
US8050317B2 (en) * 2007-01-19 2011-11-01 Samsung Electronics Co., Ltd. Receiver with equalizer and method of operation
USRE43539E1 (en) * 2001-12-19 2012-07-24 Elpida Memory, Inc. Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit
US8290028B2 (en) * 2007-06-01 2012-10-16 Renesas Electronics Corporation Input/output circuit
US20130148448A1 (en) * 2002-08-23 2013-06-13 Elpida Memory, Inc. Memory system and data transmission method
US20130191562A1 (en) * 2002-07-17 2013-07-25 Chronologic Pty Ltd Synchronized multichannel universal serial bus
US8520765B2 (en) * 2008-08-29 2013-08-27 Sony Corporation Information processing apparatus, signal transmission method and decoding method
US8570904B2 (en) * 2009-02-18 2013-10-29 Dust Networks, Inc. Localization in a network
US20140107997A1 (en) * 2010-04-19 2014-04-17 Altera Corporation Simulation Tool for High-Speed Communications Links
US8760977B2 (en) * 2011-04-28 2014-06-24 Lsi Corporation Systems and methods for data write loopback based timing control
US7203260B2 (en) * 2001-09-05 2007-04-10 Silicon Image, Inc. Tracked 3X oversampling receiver
US6888417B2 (en) * 2001-09-05 2005-05-03 Silicon Image, Inc. Voltage controlled oscillator
US7453833B2 (en) 2003-02-26 2008-11-18 Samsung Electronics Co., Ltd. Hybrid-type data transmission apparatus and method suitable for high-performance wireless LAN
TW200803407A (en) 2006-05-30 2008-01-01 Pixart Imaging Inc A data communication system
CN101904100A (en) 2007-12-17 2010-12-01 美商豪威科技股份有限公司 Replica bias circuit for high speed low voltage common mode driver
US20140372785A1 (en) * 2011-06-28 2014-12-18 Microsoft Corporation High-speed i/o data system
Bae, Seung-Jun et al., "An 80nm 4Gb/s/pin 32 bit 512Mb GDDR4 Graphics DRAM with Low Power and Low Noise Data Bus Inversion," IEEE J. Solid-State Circuits, Jan. 2008.
Balamurugan, G. et al., "Modeling and Analysis of High-Speed I/O Links," IEEE Transactions on Advanced Packaging, May 2009.
Chinese First Office Action, Chinese Application No. 201180007515.9, Jul. 16, 2014, 23 pages.
Chinese First Office Action, Chinese Application No. 201280025948.1, Jan. 4, 2015, 14 pages.
Chinese Second Office Action, Chinese Application No. 201180007515.9, Mar. 9, 2015, 11 pages.
Chinese Second Office Action, Chinese Application No. 201280025948.1, Sep. 22, 2015, 14 pages.
Chinese Third Office Action, Chinese Application No. 201180007515.9, Sep. 8, 2015, 8 pages.
Dettloff, W. D. et al., "A 32mW 7.4Gb/s Protocol-Agile Source-Series Terminated Transmitter in 45nm CMOS SOI," IEEE International Solid-State Circuits Conference, Feb. 2010.
Drost, R.J. et al., "An 8-Gb/s/pin Simultaneously Bidirectional Transceiver in 0.35-mum CMOS," IEEE Journal of Solid-State Circuits, Nov. 2004, pp. 1894-1908, vol. 39, No. 11.
Drost, R.J. et al., "An 8-Gb/s/pin Simultaneously Bidirectional Transceiver in 0.35-μm CMOS," IEEE Journal of Solid-State Circuits, Nov. 2004, pp. 1894-1908, vol. 39, No. 11.
European Extended Search Report, European Application No. 11742641.1, Jun. 15, 2015. 5 pages.
European Extended Search Report, European Application No. 12803660.5, Oct. 7, 2014, 11 pages.
European Extended Search Report, European Application No. 12804105.0, Nov. 24, 2014, 9 pages.
Japanese Office Action, Japanese Application No. 2012-552909, Feb. 10, 2015, 4 pages (with English Summary).
Japanese Office Action, Japanese Application No. 2012-552909, Sep. 8, 2015, 3 pages. (with English summary).
Kossel, M. et al., "A T-Coil Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS with <-16 dB Return Loss Over 10 GHz Bandwidth," IEEE Journal of Solid-State Circuits, Dec. 2008, pp. 2905-2920, vol. 43, No. 12.
Lee , H. et al., "A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface," IEEE J. Solid-State Circuits, Apr. 2009.
Leibowitz, B. et al., "A 4.3GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling," IEEE J. Solid-State Circuits, Apr. 2010.
Palermo, S. et al., "A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects," IEEE J. Solid-State Circuits, May 2008.
Partovi, H. et al., "Single-ended Transceiver Design Techniques for 5.33Gb/s Graphics Applications," IEEE International Solid-State Circuits Conference, Feb. 2009.
Razavi, B., "Prospects of CMOS Technology for High-Speed Optical Communication Circuits," IEEE J. Solid-State Circuits, Sep. 2002.
Ross, Kevin, The Basics-Very Basic Circuits, Mar. 1997, www.seattlerobotics.org.
Taiwan Office Action, Taiwan Application No. 101123341, Oct. 5, 2015, 10 pages.
United States Office Action, U.S. Appl. No. 13/174,616, Jan. 15, 2013, 15 pages.
Wong, K-L J. et al., "A 27mW 3.6-Gb/s I/O Transceiver," IEEE J. Solid-State Circuits, Apr. 2004.
US8760188B2 (en) 2014-06-24
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GONDI, SRIKANTH;ISAAC, ROGER;REEL/FRAME:035130/0905