Source: http://www.google.com/patents/US5448640?ie=ISO-8859-1&dq=6,631,400
Timestamp: 2014-10-23 06:17:52
Document Index: 16299607

Matched Legal Cases: ['art 11', 'art 12', 'art 11', 'art 13', 'art 12', 'art 14', 'art 13', 'art 15', 'art 14']

Patent US5448640 - Parallel distributed sample descrambling circuit for cell-based asynchronous ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA parallel distributed sample descrambler part for a cell-based ATM physical layer, comprising a PRBS generator for generating an 8-bit random number when being set to any value other than "0" in response to an initial value set signal upon initialization, to execute a generation polynomial for distributed...http://www.google.com/patents/US5448640?utm_source=gb-gplus-sharePatent US5448640 - Parallel distributed sample descrambling circuit for cell-based asynchronous transfer mode physical layerAdvanced Patent SearchPublication numberUS5448640 APublication typeGrantApplication numberUS 08/213,709Publication dateSep 5, 1995Filing dateMar 16, 1994Priority dateMar 18, 1993Fee statusPaidPublication number08213709, 213709, US 5448640 A, US 5448640A, US-A-5448640, US5448640 A, US5448640AInventorsYoung S. Kim, Song I. Choi, Hong S. ParkOriginal AssigneeElectronics And Telecommunications Research Institute, Korea Telecommunications AuthorityExport CitationBiBTeX, EndNote, RefManPatent Citations (8), Referenced by (8), Classifications (10), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetParallel distributed sample descrambling circuit for cell-based asynchronous transfer mode physical layerUS 5448640 AAbstract A parallel distributed sample descrambler part for a cell-based ATM physical layer, comprising a PRBS generator for generating an 8-bit random number when being set to any value other than "0" in response to an initial value set signal upon initialization, to execute a generation polynomial for distributed sample descrambling given by x31 +x28 +1, and a descrambler for adding 8 bits of reception data to 8 bits of the random number from the PRBS generator, respectively, to perform the descrambling of the reception data and outputting the descrambled data bits. A sample processor extracts two bits for synchronization of the descrambler from the 8-bit random number from the PRBS generator as first and second samples in response to an external sampling clock and an external synchronous clock. The sample processor also extracts highest first and second bits of a syndrome signal from a cell delineation part in a cell-based ATM physical layer receiver as transmitter PRBS samples in response to the external sampling clock and the external synchronous clock. The sample processor compares the extracted first and second samples and the extracted syndrome signal highest first and second bits with each other and outputs first and second synchronous signals for the PRBS generator in accordance with the compared result.
What is claimed is: 1. A parallel distributed sample descrambling circuit for a cell-based ATM physical layer, comprising:PRBS generation means for generating an 8-bit random number when being set to any value other than "0" in response to an initial value set signal upon initialization, to execute a generation polynomial for distributed sample descrambling given by x31 +x28 +1; descrambling means for adding 8 bits of reception data to 8 bits of the random number from said PRBS generation means, respectively, to perform the descrambling of the reception data and outputting the descrambled data bits; and sample processing means responsive to an external sampling clock and an external synchronous clock, for extracting two bits for synchronization of said descrambling means from the 8-bit random number from said PRBS generation means as first and second samples, extracting highest first and second bits of a syndrome signal from a cell delineation part in a cell-based ATM physical layer receiver as transmitter PRBS samples, comparing the extracted first and second samples and the extracted syndrome signal highest first and second bits with each other and outputting first and second synchronous signals for said PRBS generation means in accordance with the compared result. 2. A parallel distributed sample descrambling circuit for a cell-based ATM physical layer, as set forth in claim 1, wherein said PRBS generation means includes:first to fourth-stage registers connected in series, each of said first to fourth-stage registers having a set terminal for inputting the initial value set signal; first to eighth exclusive-OR gates for inputting outputs from said third and fourth-stage registers and outputting the 8 bits of the random number, respectively; a first correction circuit connected between output terminals of said second to eighth exclusive-OR gates and input terminals of said first-stage register, for transferring the second to eighth bits of the random number from said second to eighth exclusive-OR gates except the first bit from said first exclusive-OR gate to said first-stage register; a second correction circuit connected between output terminals of said first-stage register and said first exclusive-OR gate and input terminals of said second-stage register, for transferring a 7-bit output from said first-stage register and the first bit from said first exclusive-OR gate to said second-stage register; a third correction circuit connected between output terminals of said second-stage register and input terminals of said third-stage register, for transferring an 8-bit output from said second-stage register to said third-stage register; and a fourth correction circuit connected between output terminals of said third-stage register and input terminals of said fourth-stage register, for transferring an 8-bit output from said third-stage register to said fourth-stage register; each of said first to fourth correction circuits inverting input transition data to a corresponding one of said first to fourth-stage registers in response to the first and second synchronous signals from said sample processing means. 3. A parallel distributed sample descrambling circuit for a cell-based ATM physical layer, as set forth in claim 2, wherein said first to fourth correction circuits are constructed to invert bits for correction only when the first and second synchronous signals from said sample processing means are logically "high".
SUMMARY OF THE INVENTION Therefore, the present invention has been made in view of the above problem, and it is an object of the present invention to provide a parallel distributed sample descrambler partfor a cell-based ATM physical layer in which an operation speed of the circuit can be reduced (for example, to 19.44 Mbps when a transmission speed of the ATM physical layer is 155.52 Mbps) by an 8-bit parallel process using a general semiconductor.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, there is shown a block diagram of a cell-based ATM physical layer receiver to which the present invention is applied. As shown in this drawing, the cell-based ATM physical layer receiver comprises a controller 16 for generating a clock as a control signal, a line interface part 11 for receiving ATM cell data from a transmission medium and extracting a clock from the received ATM cell data, a cell delineation part 12 for calculating a syndrome using a HEC code of the ATM cell data received by the line interface part 11 to find a cell boundary, a distributed sample (DS) descrambler part 13 for descrambling the ATM cell data synchronized by the cell delineation part 12, a cell processimg part 14 connected to the DS descrambler part 13 for discriminating whether a received cell is an ATM cell or an operation and administration maintenance (OAM) cell and transmitting the discriminated ATM cell to an ATM layer, and an OAM cell processing part 15 for receiving the OAM cell from the cell processing part 14 and performing an operation administration maintenance of the received OAM cell.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4719643 *Sep 15, 1986Jan 12, 1988Gte Communication Systems CorporationIn a digital telecommunications systemUS5163092 *Nov 28, 1990Nov 10, 1992Siemens AktiengesellschaftParallel scrambler used in sonet data transmissionUS5245661 *May 22, 1992Sep 14, 1993Byeong Gi LeeDistributed sample scrambling systemUS5257311 *Apr 30, 1992Oct 26, 1993Fujitsu LimitedSystem for monitoring ATM cross-connecting apparatus by inside-apparatus monitoring cellUS5283831 *Apr 10, 1991Feb 1, 1994British TelecommunicationsMethod of synchronizing the pseudo-random binary sequence in a descramblerUS5321754 *Sep 19, 1991Jun 14, 1994Northern Telecom LimitedSequence synchronizationUS5349611 *Jan 13, 1993Sep 20, 1994Ampex Systems CorporationRecovering synchronization in a data streamUS5355415 *Mar 15, 1993Oct 11, 1994Byeong Gi LeeParallel distributed sample scrambling system* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5946398 *Aug 28, 1997Aug 31, 1999Level One Communications, Inc.State synchronized cipher text scramblerUS5984521 *May 6, 1997Nov 16, 1999Samsung Electronics, Co., Ltd.Method and apparatus for generating descrambling data for CD-ROM decoderUS6122376 *Aug 31, 1999Sep 19, 2000Level One Communications, Inc.State synchronized cipher text scramblerUS6414957 *Nov 30, 1998Jul 2, 2002Electronics And Telecommunications Research InstituteParallel processor for use in distributed sample scramblerUS6452927Dec 29, 1995Sep 17, 2002Cypress Semiconductor CorporationMethod and apparatus for providing a serial interface between an asynchronous transfer mode (ATM) layer and a physical (PHY) layerUS6553120 *Nov 4, 1997Apr 22, 2003Centre National De La Recherche ScientifiqueMethod for data decorrelationUS7206945 *Dec 12, 2002Apr 17, 2007Lg Electronics Inc.Parallel distributed sample descrambling apparatus of passive optical network and method thereofWO1997027694A1 *Jan 22, 1997Jul 31, 1997Ericsson Telefon Ab L MDigital transmission on parallel optical links* Cited by examinerClassifications U.S. Classification380/268, 380/46, 370/515International ClassificationH04L9/22, H04Q3/00, H04L9/12, H04K1/04Cooperative ClassificationH04L9/0656, H04L9/12European ClassificationH04L9/12Legal EventsDateCodeEventDescriptionFeb 9, 2007FPAYFee paymentYear of fee payment: 12Dec 25, 2002FPAYFee paymentYear of fee payment: 8Feb 22, 1999FPAYFee paymentYear of fee payment: 4Mar 16, 1994ASAssignmentOwner name: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITOwner name: KOREA TELECOMMUNICATION AUTHORITY, KOREA, REPUBLICFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, YOUNG SUP;CHOI, SONG IN;PARK, HONG SHIK;REEL/FRAME:006917/0385Effective date: 19940304RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google