Source: https://patents.google.com/patent/US9659630B2/en
Timestamp: 2019-06-25 07:57:50
Document Index: 516691123

Matched Legal Cases: ['Application No. 2011', 'Application No. 09774013', 'Application No. 09774012', 'Application No. 13157772', 'Application No. 098120886', 'Application No. 098114848', 'Application No. 2011', 'application No. 200980125792', 'Application No. 2011']

US9659630B2 - Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes - Google Patents
Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes Download PDF
US9659630B2
US9659630B2 US13/619,682 US201213619682A US9659630B2 US 9659630 B2 US9659630 B2 US 9659630B2 US 201213619682 A US201213619682 A US 201213619682A US 9659630 B2 US9659630 B2 US 9659630B2
US13/619,682
US20130010552A1 (en
2012-09-14 Priority to US13/619,682 priority patent/US9659630B2/en
2013-01-10 Publication of US20130010552A1 publication Critical patent/US20130010552A1/en
2017-05-23 Publication of US9659630B2 publication Critical patent/US9659630B2/en
This application is a continuation of U.S. patent application Ser. No. 12/166,871, filed Jul. 2, 2008, and issued as U.S. Pat. No. 8,289,760, on Oct. 16, 2012. This application and patent are incorporated by reference herein in their entirety and for any purposes.
FIG. 4 is a packet diagram showing the format of a downstream packet that can be coupled to the memory system of FIG. 1, 2 or 3 or a memory system according to some other embodiment of the invention for the indirect operating mode.
FIG. 7 is a packet diagram showing the format of an upstream packet that can be coupled from the memory system of FIG. 1, 2 or 3 or a memory system according to some other embodiment of the invention.
The format of a downstream packet 150 that can be coupled to the memory system of FIG. 1, 2 or 3 or a memory system according to some other embodiment of the invention is shown in FIG. 4. The downstream packet 150 may be, as explained above, 32 bits wide, and it contains a first field 152. In the indirect operating mode, the first field 152 includes a 4-bit command 156 (“Cmd 3:0”), and 28 bits of an upper address 158 (“UAddress”). The nature of the command 156 and upper address 158 will be described in connection with FIG. 6.
The commands corresponding to the Cmd1 bits 272 are also shown in FIG. 8. The command “0000” is again for a no operation “NOP” command, and the command “0001” is again a naked command (“NAK”) that acknowledges a read memory request but indicates that the data could not be read because of an error. The command “0100” acknowledges a prior write request, and the command “0101” is a naked command that acknowledges a prior write request but indicates that the write data was in error. The remaining commands of “Cmd1” are reserved for implementing other features.
1. A memory device system comprising:
a plurality of stacked memory device dice connected to each other through a plurality of conductors, a memory device dice of the plurality of stacked memory device dice comprising a plurality of memory cells;
a logic die coupled to the plurality of stacked memory device dice through a plurality of conductors, the logic die being configured to write data to and read data from the plurality of stacked memory device dice responsive to one or more received packets, the logic die including a command processing circuit, the command processing circuit configured to receive the one or more packets and configured to selectively operate in at least one of a first mode and a second mode, wherein in the first mode, the command processing circuit is configured to interpret a position of bits of a field of a packet of the one or more packets as a row address strobe signal and a column address strobe signal, and wherein in the second mode, the command processing circuit is configured to interpret the position of bits of the field of the packet as at least a portion of a command code.
2. The memory device system of claim 1, wherein the command processing circuit is further configured to, in the second mode, provide memory commands and memory addresses to the at least one of the plurality of stacked memory device dice based on the command code.
3. The memory device system of claim 2, wherein the memory commands are different than the command code.
4. The memory device system of claim 1, wherein the command processing circuit is further configured to, in the first mode, provide the row address strobe signal and the column address strobe signal to the at least one of the plurality of stacked memory device dice based on the command code.
5. The memory device system of claim 1, wherein in the first mode, the bits of the field further correspond to a write enable signal.
6. The memory device system of claim 1, wherein, in the first mode, the command processing circuit is configured to provide data corresponding to the one or more packets in to the plurality of stacked memory dice in an order the one or more packets are received at the command processing circuit.
7. The memory device system of claim 1, wherein, in the second mode, the command processing circuit is configured to provide data corresponding to the one or more packets in to the plurality of stacked memory dice based on a preset order.
8. The memory device system of claim 7, wherein, in the second mode, the preset order is different than an order the one or more packets are received at the command processing circuit.
9. The memory device system of claim 1, wherein the first mode is a direct mode and the second mode is an indirect mode.
10. The memory device system of claim 2, wherein the first mode is a direct mode and the second mode is an indirect mode.
a plurality of stacked memory device dice connected to each other through a plurality of conductors, a memory device dice of the plurality of stacked memory device dice memory device dice comprising a plurality of memory cells having locations corresponding to respective memory addresses; and
a logic die coupled to the plurality of stacked memory device dice, the logic die configured to receive one or more packets, the logic die further configured to selectively operate in at least one of a first mode and a second mode, wherein, in the first mode, the logic die is configured to interpret a position of bits of a field of a packet of the one or more packets as a row address strobe signal and a column address strobe signal, respectively and to apply a first set of commands to the plurality of stacked memory device dice based on the row address strobe signal and the column address strobe signal, and wherein, in the second mode, the logic die is configured to interpret the position of bits of the field of the packet as at least a portion of a command code and to apply a second set of commands to the plurality of stacked memory device dice based on the command code.
12. The system of claim 11, wherein the logic die comprises a command register configured to, in the first mode, receive the packet and to couple a memory device dice of the plurality of stacked memory device dice to the row address strobe signal and the column address strobe signal.
13. The system of claim 12, wherein the field further comprises bits corresponding to a write enable signal, and wherein the command register is further configured to, in the first mode, couple the memory device dice of the plurality of stacked memory device dice to the write enable signal.
14. The system of claim 12, wherein the command register further is configured to, in the in the second mode, receive the packet and provide a memory packet to the memory device dice of the plurality of stacked memory device dice based on the command code.
15. The system of claim 14, wherein the memory device dice is configured to, in the in the second mode, receive the memory packet and to determine a memory address responsive to data of the packet.
16. The system of claim 14, wherein the logic die is configured to operate in the first mode and in the second mode contemporaneously.
17. The system of claim 11, further comprising a memory access device configured to provide the one or more packets to the logic die.
18. The system of claim 11, wherein the first mode is a direct mode and the second mode is an indirect mode.
receiving one or more packets at a logic die of a memory system, the logic die configured to selectively operate in at least one of a first mode or a second mode;
in response to a packet of the one or more packets received by the logic die, interpreting, in a first mode, a position of bits of a field of a packet of the one or more packets as a row address strobe signal and a column address strobe signal;
coupling, in the first mode, the a row address strobe signal and the column address strobe signal to a memory device dice of a plurality of stacked memory device dice of the memory system;
interpreting, in a second mode, the position of bits of the field of the packet as at least a portion of a command code;
determining, in the second mode, a memory command signal and an address signal based on the command code; and
providing, in the second mode, the memory command signal and the memory address signal to the memory device dice of a plurality of stacked memory device dice of the memory system based on the command code.
20. The method of claim 19, further comprising determining, in the first mode, a write enable signal based on corresponding bits of the field of the packet.
21. The method of claim 19, further comprising storing, in the first mode, data in the memory device dice based on a command signal, the row address strobe signal, and the column address strobe signal.
22. The method of claim 21, further comprising storing, in the second mode, the data in the memory device dice based on the memory command signal and the memory address signal.
23. The method of claim 19, further comprising receiving, in the first mode, data from the memory device dice based on a command signal, the row address strobe signal, and the column address strobe signal.
24. The method of claim 23, further comprising receiving, in the second mode, the data from the memory device dice based on the memory command signal and the memory address signal.
25. The method of claim 23, wherein the command signal, the row address strobe signal, and the column address signal have a different format than the memory command signal and the memory address signal.
26. The method of claim 19, wherein the first mode is a direct mode and the second mode is an indirect mode.
US13/619,682 2008-07-02 2012-09-14 Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes Active US9659630B2 (en)
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