Source: http://www.google.com/patents/US7834392?dq=7,619,961
Timestamp: 2017-12-15 09:36:47
Document Index: 259351830

Matched Legal Cases: ['Application No. 02826596', 'Application No. 02826596', 'Application No. 02826596', 'Application No. 07', 'Application No. 07002287', 'Application No. 07002288', 'Application No. 07002289', 'Application No. 02', 'Application No. 07002287', 'Application No. 07002289', 'Application No. 07002288', 'Application No. 07002289', 'Application No. 200710135802', 'Application No. 204', 'Application No. 2004', 'Application No. 2003', 'Application No. 96151683', 'Application No. 02826596', 'Application No. 200710135802', 'Application No. 2009', 'Application No. 91132182', 'Application No. 96151684', 'Application No. 2004', 'Application No. 2003', 'Application No. 02826596', 'Application No. 02826596']

Patent US7834392 - Multi-state non-volatile integrated circuit memory systems that employ ... - Google Patents
Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one...http://www.google.com/patents/US7834392?utm_source=gb-gplus-sharePatent US7834392 - Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
Publication number US7834392 B2
Application number US 12/510,077
Also published as CN1610976A, CN100539195C, DE60219666D1, DE60219666T2, EP1446840A1, EP1446840A4, EP1446840B1, EP1777750A2, EP1777750A3, EP1777750B1, EP1777751A2, EP1777751A3, EP1777751B1, EP1777752A2, EP1777752A3, EP1777752B1, US6925007, US7341918, US7342279, US7479677, US7579247, US20030109093, US20050157551, US20050180210, US20080116509, US20080119026, US20090286370, WO2003038907A1
Publication number 12510077, 510077, US 7834392 B2, US 7834392B2, US-B2-7834392, US7834392 B2, US7834392B2
Patent Citations (136), Non-Patent Citations (63), Referenced by (8), Classifications (34), Legal Events (3)
US 7834392 B2
14. The non-volatile memory of claim 11, wherein the at least two gates include at least one gate formed from a conductive line having a length extending in a direction perpendicular to the channel and at least one gate formed from a conductive line having a length extending in a direction parallel with the channel.
Programming the right segment, region 173: Substrate 163: 0 volts; source 152: VS=0 volts; drain 153: VD=5 volts; control gate 157: VSG=8.8 volts; and word line 160; VWL=the threshold VT 177 of the device on the left side plus about 1 volt.
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US20030209754 Apr 25, 2003 Nov 13, 2003 Interuniversitair Microelektronica Centrum (Imec) Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure
US20030211689 Apr 22, 2003 Nov 13, 2003 Samsung Electronics Co., Inc. Nonvolatile memory device with a non-planar gate-insulating layer and method of fabricating the same
US20040009642 Jun 5, 2003 Jan 15, 2004 Samsung Electronics Co., Ltd. Method of fabricating non-volatile memory device having a structure of silicon-oxide-nitride-oxide-silicon
US20040009645 May 28, 2003 Jan 15, 2004 Samsung Electronics Co., Ltd. Eeprom and method of fabricating the same
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KR20000005467A Title not available
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WO2001013378A1 Feb 28, 2000 Feb 22, 2001 Fujitsu Limited Multiple-bit nonvolatile memory using non-conductive charge trap gate
WO2001065567A Title not available
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International Classification H01L29/792, H01L21/8247, G11C16/04, H01L29/788, H01L21/8246, H01L27/115, G11C11/56
Cooperative Classification B82Y10/00, G11C16/0483, H01L29/4234, H01L29/7923, G11C16/0466, G11C16/0475, G11C11/5671, G11C2216/06, G11C16/0491, H01L27/11521, H01L27/11524, H01L27/115, H01L27/11568, Y10S438/947
European Classification H01L29/423D2B3, H01L27/115, H01L29/792B, H01L27/115G4, G11C16/04N, H01L27/115F4N, B82Y10/00, G11C11/56M, H01L27/115F4, G11C16/04M
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