Source: http://www.google.com/patents/US7206021?dq=5,758,352
Timestamp: 2016-06-26 02:52:07
Document Index: 193677745

Matched Legal Cases: ['arts 4', 'art 3', 'art 5', 'arts 4', 'art 4', 'art 5', 'art 5']

Patent US7206021 - Hybrid pixel interpolating apparatus and hybrid pixel interpolating method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA hybrid pixel interpolating apparatus (1) has a function of converting raw image data (D1) having one color component for each pixel into pixel interpolated data in which each pixel has a plurality of color components. This hybrid pixel interpolating apparatus (1) includes: a register (2) for holding...http://www.google.com/patents/US7206021?utm_source=gb-gplus-sharePatent US7206021 - Hybrid pixel interpolating apparatus and hybrid pixel interpolating methodAdvanced Patent SearchPublication numberUS7206021 B2Publication typeGrantApplication numberUS 10/364,381Publication dateApr 17, 2007Filing dateFeb 12, 2003Priority dateFeb 21, 2002Fee statusPaidAlso published asUS20030156205Publication number10364381, 364381, US 7206021 B2, US 7206021B2, US-B2-7206021, US7206021 B2, US7206021B2InventorsGen Sasaki, Takashi MatsutaniOriginal AssigneeMega Chips CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (13), Referenced by (10), Classifications (17), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetHybrid pixel interpolating apparatus and hybrid pixel interpolating method
Next, as a concrete example of the hybrid pixel interpolating apparatus 1 according to the first preferred embodiment, a hybrid pixel interpolating apparatus according to the second preferred embodiment and a method thereof will be described. FIG. 2 is a schematic configuration view showing a hybrid pixel interpolating apparatus according to the present preferred embodiment. This hybrid pixel interpolating apparatus comprises a register 2 for holding pixel data of a local region of raw image data D1 inputted from external; pixel interpolating parts 4 1 and 4 2 for executing a pixel interpolating processes in different manners; a mixing coefficient calculating part 3 for calculating mixing coefficients α and 1−α (0≦α≦1); and a mixing part 5 for mixing interpolated data DI1 and DI2 respectively outputted from the pixel interpolating parts 4 1 and 4 2. It is to be noted that the numerical range of mixing coefficient a (0≦α≦1) is represented by a decimal in decimal notation, however the value of “1” which is the upper limitation of mixing coefficient α is actually determined depending on the digital processing system.
The contents of the above process in the pixel interpolating part 4 1 can be mathematically represented as follows. Representing pixel value of the current pixel Pc by “Sc”, and pixel values of color components that are lacking in the current pixel Pc as “S1” and “S2”, the following expressions (1) and (2) can be satisfied.
Then the adder circuit 24 adds values inputted from the first and the second converting circuits 20 and 23 to output internal coefficients β (0≦β≦1) to a subtracter circuit 25, “0” terminal of a first selector 27 and “1” terminal of a second selector 28, respectively. The subtracter circuit 25 outputs to “1” terminal of the first selector 27, a value (=1−β) obtained by subtracting the internal coefficient β from the upper limit value of internal coefficient β.
The first selector 27 selects either “0” terminal or “1” terminal in accordance with whether a logical value of a selection signal St supplied from a register 26 is “0” or “1”, and outputs data inputted from the selected terminal to the mixing part 5 as a mixing coefficient α. The register 26 holds the selection signal St transmitted from, for example, a CPU (not shown) and supplies it to the first selector 27 and the second selector 28. A logical value of the selection signal St is set at “0” by default. On the other hand, the second selector 28 selects either “0” terminal or “1” terminal in accordance with whether a logical value of a selection signal St supplied from a register 26 is “0” or “1”, and outputs data inputted from the selected terminal to the mixing part 5 as a mixing coefficient 1−α.
The converting circuits 20 and 23 convert the pixel value Sc of the current pixel Pc and the ratio (=Mn/Mx) indicating the degree of deviation in color into other values in accordance with the conversion tables 20 c and 23 c. Therefore, by adjusting the conversion curves of the respective conversion tables 20 c and 23 c, it is possible to optimize the mixing coefficients α and 1−α to control the deterioration in image quality as small as possible. In addition, when the converting circuits 20 and 23 have a plurality of conversion tables which can be switched at liberty, by switching the conversion table in correspondence with the plural situations, it is possible to optimize the mixing coefficients α and 1−α. Concretely, the situation where the present hybrid pixel interpolating apparatus is incorporated into a digital camera supporting a plurality of imaging modes can be assumed. As the imaging modes, “landscape imaging mode”, “portrait imaging mode”, “close up mode”, “night imaging mode” and the like can be exemplified, and for each imaging mode, an optimum conversion table can be selected.
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