Source: http://www.google.com/patents/US8193567?dq=6246862
Timestamp: 2015-06-30 00:02:34
Document Index: 801219743

Matched Legal Cases: ['Application No. 094136197', 'Application No. 10', 'Application No. 200680023301', 'Application No. 03817697', 'Application No. 11', 'Application No. 112006001735', 'Application No. 2006', 'Application No. 10', 'Application No. 200680023301', 'Application No. 03817699', 'Application No. 05711376', 'Application No. 06815547', 'Application No. 10', 'Application No. 95122087', 'Application No. 95122087', 'Application No. 95123858', 'Application No. 95123858', 'Application No. 95123858', 'Application No. 95135820', 'Application No. 95135820', 'Application No. 95134963', 'Application No. 200680021817', 'Application No. 200580032314', 'Application No. 200507013', 'Application No. 200604766']

Patent US8193567 - Process for integrating planar and non-planar CMOS transistors on a bulk ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths....http://www.google.com/patents/US8193567?utm_source=gb-gplus-sharePatent US8193567 - Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made therebyAdvanced Patent SearchPublication numberUS8193567 B2Publication typeGrantApplication numberUS 12/333,248Publication dateJun 5, 2012Filing dateDec 11, 2008Priority dateSep 28, 2005Also published asCN101292346A, CN101292346B, EP1929516A2, US7479421, US20070069293, US20090090976, WO2007038575A2, WO2007038575A3Publication number12333248, 333248, US 8193567 B2, US 8193567B2, US-B2-8193567, US8193567 B2, US8193567B2InventorsJack T. Kavalieros, Justin K. Brask, Brian S. Doyle, Uday Shah, Suman Datta, Mark L. Doczy, Matthew V. Metz, Robert S. ChauOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (105), Non-Patent Citations (90), Referenced by (4), Classifications (21) External Links: USPTO, USPTO Assignment, EspacenetProcess for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
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No. 12/114,227 mailed Mar. 30, 2010, 10 pgs.87Second Office Action for Chinese Patent Application No. 200680021817.0 mailed Dec. 11, 2009, 10 pgs.88Third Office Action for Chinese Patent Application No. 200580032314.9 mailed Jan. 29, 2010, 13 pgs.89Written Opinion from Singapore Patent Application No. 200507013-1 issued May 18, 2007, 4 pgs.90Written Opinion from Singapore Patent Application No. 200604766-6 mailed Apr. 4, 2008, 4 pgs.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8569159 *Apr 23, 2012Oct 29, 2013International Business Machines CorporationCMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabricationUS8587068 *Jan 26, 2012Nov 19, 2013International Business Machines CorporationSRAM with hybrid FinFET and planar transistorsUS20120199910 *Apr 23, 2012Aug 9, 2012International Business Machines CorporationCmos structure including non-planar hybrid orientation substrate with planar gate electrodes & method for fabricationUS20130273705 *Jun 10, 2013Oct 17, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Multi-Fin Device and Method of Making Same* Cited by examinerClassifications U.S. Classification257/288, 257/368, 257/E29.264, 257/369International ClassificationH01L29/76Cooperative ClassificationH01L21/823828, H01L29/785, H01L21/823807, H01L21/823821, H01L29/7851, H01L29/1037, H01L21/823431, H01L29/66795, H01L29/66545European ClassificationH01L29/10D2B1, H01L21/8238G, H01L29/66M6T6F16F, H01L21/8234F, H01L21/8238F, H01L29/78S, H01L21/8238CRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services