Source: https://patents.google.com/patent/US7714360?oq=6008737
Timestamp: 2018-06-19 22:16:38
Document Index: 63690290

Matched Legal Cases: ['art 6', 'art 6', 'art 6', 'art 6', 'art 1', 'art 1', 'arts 4']

US7714360B2 - Surface-stabilized semiconductor device - Google Patents
Surface-stabilized semiconductor device Download PDF
US7714360B2
US7714360B2 US11961620 US96162007A US7714360B2 US 7714360 B2 US7714360 B2 US 7714360B2 US 11961620 US11961620 US 11961620 US 96162007 A US96162007 A US 96162007A US 7714360 B2 US7714360 B2 US 7714360B2
US11961620
US20080121876A1 (en )
The p-type organic semiconductor overlay 6 assures a carrier (hole) mobility of 1.5 cm2/V·s at a maximum, much less than the carrier (electron) mobility of the electron supply layer 9 of III-V compound semiconductors. Essentially, therefore, the organic semiconductor overlay 6 is an insulator, so that the current flowing through this overlay between drain 4 and gate 5 and between source 3 and gate 5 is negligibly small. It will thus be appreciated that the organic semiconductor overlay 6 serves not just for elimination of current collapse but for surface protection or stabilization of the main semiconductor region 1.
The HEMT seen here is of the same construction as that of FIG. 1 except for a p-type organic semiconductor overlay 6 a which covers all of that part of the major surface 12 of the main semiconductor region 1 which lies between drain 4 and gate 5. The limited coverage of the semiconductor surface 12 by the overlay 6 a is effective for restriction of the lessening of electrons, and consequent current collapse, in the underlying part of the two-dimensional electron gas layer 11.
This embodiment differs from that of FIG. 2 only in an organic semiconductor overlay 6 b which covers only part of that part of the major surface 12 of the main semiconductor region 1 which lies between drain 4 and gate 5. A spacing exists between gate 5 and overlay 6 b. This overlay 6 b is nearly as effective as its FIG. 2 counterpart 6 a.
The organic semiconductor overlay 6 c depicted here is similar in size and positioning to its FIG. 3 counterpart 6 b, but a spacing exists between drain 4 and overlay 6 c instead of between gate 5 and overlay 6 c. This overlay 6 c is also nearly as effective as its FIG. 2 counterpart 6 a.
The organic semiconductor overlay 6 d is here placed between drain 4 and gate 5 but spaced from both of them. This overlay 6 d is also nearly as effective as its FIG. 2 counterpart 6 a.
This embodiment differs from that of FIG. 1 in additionally incorporating a protective covering 13 of a solid insulator or dielectric, preferably silicon oxide (SiO2), enveloping the major surface 12 of the main semiconductor region 1. The organic semiconductor overlay 6 e is held against the major surface 12 of the main semiconductor region 1 via the protective covering 13. Both electron supply layer 9 and protective covering 13 provide the dielectric of a capacitor, serving to prevent current collapse in a manner set forth previously in conjunction with the FIG. 1 embodiment.
The HEMT shown here is similar in construction to that of FIG. 6 except for the addition of a resistive Schottky barrier field plate 14. The field plate 14 is shown interposed between main semiconductor region 1 and protective covering 13, covering part of that part of the major surface 12 of the main semiconductor region which lies between drain 4 and gate 5, with a spacing from the drain. Thus the field plate 14 is electrically coupled directly to the gate 4 and makes Schottky contact with the major surface 12 of the main semiconductor region 1. The organic semiconductor overlay 6 e is of the same placement as that of FIG. 6.
A different position is here suggested for a resistive Schottky barrier field plate 14 a, all the other constructional details of this embodiment, including the organic semiconductor overlay 6 e, being the same as those of the FIG. 7 embodiment. Placed in direct contact with the drain 4, the field plate 14 a extends toward, and terminates short of, the gate 5. The field plate 14 a of this placement is also conducive to the mitigation of field concentration between drain 4 and gate 5.
This embodiment features a modified main semiconductor region 1 a and is otherwise substantially analogous with the FIG. 1 HEMT. The modified main semiconductor region 1 a is identical with its FIG. 1 counterpart 1 except for an n+-type source contact layer 15 and n+-type drain contact layer 16 which are both formed on the n-type electron supply layer 9 and which are spaced from each other. The source 3 is formed on the source contact layer 15, and the drain 4 on the drain contact layer 16. The source contact layer 15 and drain contact layer 16 are both made with a nitride semiconductor such as AlGaN, with an n-type impurity concentration higher than that of the electron supply layer 9. The organic semiconductor overlay 6 covers both source contact layer 15 and drain contact layer 16 and the remaining exposed surface of the electron supply layer 9.
Another modified main semiconductor region 1 b is included in the HEMT of FIG. 10, which is otherwise identical with its FIG. 1 counterpart. The modified main semiconductor region 1 b differs from its FIG. 1 counterpart 1 only in having an additional layer 17, known as a cap layer, on the electron supply layer 9. The cap layer 17 is made from undoped AlGaN or GaN. The source 3 and drain 4 are both formed directly on cap layer 17 in low resistance contact therewith, while the gate 5 is formed on the cap layer 17 in Schottky contact therewith. Alternatively, the source 3 and drain 4 maybe placed in low resistance contact with the electron supply layer 9 and out of contact with the cap layer 17.
This embodiment features still another modified main semiconductor region 1 c and a modified organic semiconductor overlay 6 f and is identical with the FIG. 1 embodiment in all the other details of construction. The modified main semiconductor region 1 c comprises, in addition to the buffer layer 7, a hole transit layer 8 a in place of the electron transit layer 8 of the foregoing embodiments, and a hole supply layer 9 a of p-doped semiconductor (e.g., p-AlGaN) in place of the electron supply layer 9 of the foregoing embodiments. A heterojunction exists between hole transit layer 8 a and hole supply layer 9 a, resulting in the creation of a two-dimensional hole gas layer 11 a in the hole transit layer 8 a.
The invention is here shown applied to an SBD. Structurally, the SBD is equivalent to the HEMT of FIG. 1 except for an ohmic electrode 4 a and Schottky electrode 5 a on the main semiconductor region 1. These electrodes 4 a and 5 a are of the same make as their FIG. 1 counterparts 4 and 5, respectively. The organic semiconductor overlay 6 covers all the major surface 12 of the main semiconductor region 1 except where the electrodes 4 a and 5 a are formed.
The invention is also applicable to an insulated-gate FET (IGFET) as in FIG. 13. The IGFET is similar in construction to the HEMT of FIG. 1 except for a main semiconductor region 1 d, source electrode 3 b, drain electrode 4 b, gate electrode 5 b, and gate insulator 20.
This embodiment represents an application of the instant invention to a pn-junction diode. The diode is structurally analogous with the HEMT of FIG. 1 except for a main semiconductor region 1 e, cathode 3 c, and anode 4 c.
(f) an organic semiconductor overlay of a second conductivity type, opposite to the first conductivity type, at least partly covering the second semiconductor layer in a position between the first and the second electrode for surface stabilization, the organic semiconductor overlay having a carrier mobility less than the carrier mobility of the second semiconductor layer.
US11961620 2005-07-13 2007-12-20 Surface-stabilized semiconductor device Active US7714360B2 (en)
JP2005-204966 2005-07-13
JP2005204966A JP4730529B2 (en) 2005-07-13 2005-07-13 Field-effect transistor
JP2006-204966 2005-07-13
PCT/JP2006/311214 WO2007007486A1 (en) 2005-07-13 2006-06-05 Field effect transistor
US20080121876A1 true US20080121876A1 (en) 2008-05-29
US7714360B2 true US7714360B2 (en) 2010-05-11
ID=37636885
US11961620 Active US7714360B2 (en) 2005-07-13 2007-12-20 Surface-stabilized semiconductor device
US (1) US7714360B2 (en)
JP (1) JP4730529B2 (en)
WO (1) WO2007007486A1 (en)
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